From cbf50b3ab915b81605c001882ce8ca90347a0f54 Mon Sep 17 00:00:00 2001 From: Raphael <68374617+raphaelscholle@users.noreply.github.com> Date: Wed, 20 Mar 2024 22:28:20 +0100 Subject: [PATCH] dumbtest --- Kconfig | 7 +- build_chroot.sh | 2 +- common.mk | 142 + core/crypto/ccmp.c | 127 +- core/crypto/gcmp.c | 2 +- core/crypto/wlancrypto_wrap.h | 7 + core/mesh/rtw_mesh.c | 274 +- core/mesh/rtw_mesh.h | 2 +- core/mesh/rtw_mesh_hwmp.c | 258 +- core/mesh/rtw_mesh_hwmp.h | 2 +- core/mesh/rtw_mesh_pathtbl.c | 79 +- core/mesh/rtw_mesh_pathtbl.h | 2 +- core/monitor/rtw_radiotap.c | 245 +- core/monitor/rtw_radiotap.h | 3 +- core/rtw_ap.c | 3048 +- core/rtw_beamforming.c | 503 +- core/rtw_br_ext.c | 432 +- core/rtw_btc.c | 107 + core/rtw_chplan.c | 5251 +- core/rtw_chplan.h | 208 +- core/rtw_cmd.c | 4658 +- core/rtw_csa.c | 484 + core/rtw_debug.c | 9417 +- core/rtw_fake_ap.c | 480 + core/rtw_ft.c | 487 +- core/rtw_he.c | 1464 + core/rtw_ieee80211.c | 790 +- core/rtw_io.c | 879 +- core/rtw_ioctl_query.c | 2 +- core/rtw_ioctl_set.c | 260 +- core/rtw_mbo.c | 1122 +- core/rtw_mem.c | 43 - core/rtw_mi.c | 347 +- core/rtw_mlme.c | 4044 +- core/rtw_mlme_ext.c | 18677 +-- core/rtw_mp.c | 4140 +- core/rtw_p2p.c | 2414 +- core/rtw_phl.c | 2755 + core/rtw_phl_cmd.c | 396 + core/rtw_pwrctrl.c | 1063 +- core/rtw_recv.c | 3525 +- core/rtw_recv_shortcut.c | 247 + core/rtw_rf.c | 1214 +- core/rtw_rm.c | 314 +- core/rtw_rm_fsm.c | 72 +- core/rtw_rm_util.c | 145 +- core/rtw_scan.c | 3435 + core/rtw_sdio.c | 41 +- core/rtw_sec_cam.c | 1059 + core/rtw_security.c | 599 +- core/rtw_sreset.c | 99 +- core/rtw_sta_mgt.c | 580 +- core/rtw_swcrypto.c | 31 +- core/rtw_tdls.c | 337 +- core/rtw_trx.c | 153 + core/rtw_trx_pci.c | 309 + core/rtw_trx_sdio.c | 537 + core/rtw_trx_usb.c | 108 + core/rtw_vht.c | 658 +- core/rtw_wapi.c | 222 +- core/rtw_wapi_sms4.c | 84 +- core/rtw_wlan_util.c | 6639 +- core/rtw_wnm.c | 611 +- core/rtw_wow.c | 1031 + core/rtw_xmit.c | 9723 +- core/rtw_xmit_shortcut.c | 917 + core/wds/rtw_wds.c | 6 +- include/_hal_api_tmp.h | 483 + include/_hal_rate.h | 1154 + include/autoconf.h | 193 +- include/basic_types.h | 55 +- include/byteorder/big_endian.h | 2 +- include/byteorder/generic.h | 24 +- include/byteorder/little_endian.h | 2 +- include/byteorder/swab.h | 4 +- include/byteorder/swabb.h | 2 +- include/circ_buf.h | 2 +- include/drv_conf.h | 332 +- include/drv_types.h | 1687 +- include/drv_types_pci.h | 38 +- include/drv_types_sdio.h | 21 +- include/drv_types_usb.h | 51 + include/ethernet.h | 2 +- include/gspi_hal.h | 11 +- include/gspi_ops.h | 36 - include/ieee80211.h | 520 +- include/ieee80211_ext.h | 2 +- include/if_ether.h | 2 +- include/ip.h | 2 +- include/linux/wireless.h | 2 +- include/mlme_osdep.h | 2 +- include/osdep_intf.h | 62 +- include/osdep_service.h | 460 +- include/osdep_service_bsd.h | 409 +- include/osdep_service_linux.h | 715 +- include/pci_ops.h | 125 +- include/pci_ops_linux.h | 24 + include/phl_api_tmp.h | 36 + include/recv_osdep.h | 34 +- include/rtw_android.h | 12 +- include/rtw_ap.h | 51 +- include/rtw_beamforming.h | 304 +- include/rtw_br_ext.h | 4 +- include/rtw_btc.h | 36 + include/rtw_byteorder.h | 2 +- include/rtw_cfg.h | 44 + include/rtw_cmd.h | 333 +- include/rtw_csa.h | 91 + include/rtw_debug.h | 194 +- include/rtw_efuse.h | 346 +- include/rtw_event.h | 22 +- include/rtw_ft.h | 51 +- include/rtw_he.h | 975 + include/rtw_ht.h | 2 +- include/rtw_hwsim_intf.h | 31 + include/rtw_io.h | 490 +- include/rtw_ioctl.h | 4 +- include/rtw_ioctl_query.h | 2 +- include/rtw_ioctl_set.h | 10 +- include/rtw_mbo.h | 119 +- include/rtw_mcc.h | 303 +- include/rtw_mem.h | 12 + include/rtw_mi.h | 68 +- include/rtw_mlme.h | 334 +- include/rtw_mlme_ext.h | 596 +- include/rtw_mp.h | 1078 +- include/rtw_p2p.h | 85 +- include/rtw_phl.h | 133 + include/rtw_phl_cmd.h | 26 + include/rtw_pwrctrl.h | 409 +- include/rtw_qos.h | 4 +- include/rtw_recv.h | 478 +- include/rtw_recv_shortcut.h | 60 + include/rtw_rf.h | 141 +- include/rtw_rm.h | 10 +- include/rtw_rm_fsm.h | 3 +- include/rtw_rm_util.h | 8 +- include/rtw_scan.h | 288 + include/rtw_sdio.h | 4 +- include/rtw_sec_cam.h | 203 + include/rtw_security.h | 31 +- include/rtw_sreset.h | 2 +- include/rtw_swcrypto.h | 5 + include/rtw_tdls.h | 2 +- include/rtw_trx.h | 71 + include/rtw_trx_ops.h | 99 + include/rtw_trx_pci.h | 26 + include/rtw_trx_sdio.h | 24 + include/rtw_trx_usb.h | 21 + include/rtw_version.h | 2 +- include/rtw_vht.h | 86 +- include/rtw_wapi.h | 8 +- include/rtw_wnm.h | 22 +- include/rtw_wow.h | 186 + include/rtw_xmit.h | 523 +- include/rtw_xmit_shortcut.h | 95 + include/sdio_ops.h | 179 +- include/sdio_ops_linux.h | 51 +- include/sta_info.h | 82 +- include/usb_ops.h | 122 +- include/usb_ops_linux.h | 54 +- include/wifi.h | 166 +- include/wlan_bssdef.h | 12 +- include/xmit_osdep.h | 81 +- os_dep/linux/custom_gpio_linux.c | 97 +- os_dep/linux/ioctl_cfg80211.c | 6438 +- os_dep/linux/ioctl_cfg80211.h | 94 +- os_dep/linux/ioctl_efuse.c | 1538 + os_dep/linux/ioctl_linux.c | 8611 +- os_dep/linux/ioctl_mp.c | 2917 +- os_dep/linux/mlme_linux.c | 23 +- os_dep/linux/os_intfs.c | 3624 +- os_dep/linux/recv_linux.c | 185 +- os_dep/linux/rhashtable.c | 4 +- os_dep/linux/rhashtable.h | 2 +- os_dep/linux/rtw_android.c | 130 +- os_dep/linux/rtw_cfg.c | 1809 + os_dep/linux/rtw_cfgvendor.c | 290 +- os_dep/linux/rtw_cfgvendor.h | 22 +- os_dep/linux/rtw_proc.c | 2529 +- os_dep/linux/rtw_proc.h | 2 +- os_dep/linux/rtw_rhashtable.c | 3 +- os_dep/linux/rtw_rhashtable.h | 2 +- os_dep/linux/usb_intf.c | 1035 +- os_dep/linux/usb_ops_linux.c | 1157 +- os_dep/linux/wifi_regd.c | 458 +- os_dep/linux/wifi_regd.h | 5 +- os_dep/linux/xmit_linux.c | 399 +- os_dep/osdep_service.c | 2674 +- os_dep/osdep_service_linux.c | 858 + phl/custom/phl_custom.c | 463 + phl/custom/phl_custom.h | 42 + phl/custom/phl_custom_api.h | 19 + phl/custom/phl_custom_def.h | 83 + phl/custom/phl_custom_fb.c | 479 + phl/custom/phl_custom_fb.h | 83 + phl/hal_g6/btc/btc.mk | 50 + phl/hal_g6/btc/btc_8852b/btc_8852b.c | 400 + phl/hal_g6/btc/btc_8852b/btc_8852b.h | 29 + phl/hal_g6/btc/hal_btc.c | 1803 + phl/hal_g6/btc/hal_btc.h | 1341 + phl/hal_g6/btc/halbtc_action.c | 2009 + phl/hal_g6/btc/halbtc_action.h | 275 + phl/hal_g6/btc/halbtc_dbg_cmd.c | 2043 + phl/hal_g6/btc/halbtc_dbg_cmd.h | 24 + phl/hal_g6/btc/halbtc_def.c | 523 + phl/hal_g6/btc/halbtc_def.h | 21 + phl/hal_g6/btc/halbtc_fw.c | 842 + phl/hal_g6/btc/halbtc_fw.h | 305 + phl/hal_g6/btc/halbtc_fwdef.h | 420 + phl/hal_g6/efuse/hal_efuse.c | 1393 + phl/hal_g6/efuse/hal_efuse.h | 81 + phl/hal_g6/efuse/hal_efuse_export.h | 135 + phl/hal_g6/hal.mk | 96 + phl/hal_g6/hal_acs.c | 32 + phl/hal_g6/hal_acs.h | 21 + phl/hal_g6/hal_api.c | 94 + phl/hal_g6/hal_api.h | 969 + phl/hal_g6/hal_api_bb.c | 2242 + phl/hal_g6/hal_api_bb.h | 258 + phl/hal_g6/hal_api_btc.c | 657 + phl/hal_g6/hal_api_btc.h | 40 + phl/hal_g6/hal_api_drv.h | 384 + phl/hal_g6/hal_api_efuse.c | 593 + phl/hal_g6/hal_api_efuse.h | 109 + phl/hal_g6/hal_api_mac.c | 8933 + phl/hal_g6/hal_api_mac.h | 658 + phl/hal_g6/hal_api_rf.c | 1292 + phl/hal_g6/hal_api_rf.h | 232 + phl/hal_g6/hal_beamform.c | 1188 + phl/hal_g6/hal_beamform.h | 200 + phl/hal_g6/hal_c2h.c | 60 + phl/hal_g6/hal_c2h.h | 21 + phl/hal_g6/hal_cam.c | 72 + phl/hal_g6/hal_cap.c | 605 + phl/hal_g6/hal_chan.c | 172 + phl/hal_g6/hal_chan.h | 33 + phl/hal_g6/hal_chan_info.c | 103 + phl/hal_g6/hal_chan_info.h | 30 + phl/hal_g6/hal_com_i.c | 334 + phl/hal_g6/hal_config.h | 65 + phl/hal_g6/hal_csi_buffer.c | 589 + phl/hal_g6/hal_csi_buffer.h | 95 + phl/hal_g6/hal_custom.c | 86 + phl/hal_g6/hal_custom.h | 43 + phl/hal_g6/hal_dbcc.c | 174 + phl/hal_g6/hal_dbcc.h | 20 + phl/hal_g6/hal_def.h | 1265 + phl/hal_g6/hal_def_btc.h | 18 + phl/hal_g6/hal_def_mac.h | 18 + phl/hal_g6/hal_def_phy.h | 18 + phl/hal_g6/hal_ext_tx_pwr_lmt.c | 69 + phl/hal_g6/hal_fw.c | 268 + phl/hal_g6/hal_fw.h | 32 + phl/hal_g6/hal_general_def.h | 287 + phl/hal_g6/hal_headers.h | 86 + phl/hal_g6/hal_headers_le.h | 344 + phl/hal_g6/hal_init.c | 1561 + phl/hal_g6/hal_io.c | 799 + phl/hal_g6/hal_io.h | 123 + phl/hal_g6/hal_ld_file.c | 2055 + phl/hal_g6/hal_ld_file.h | 240 + phl/hal_g6/hal_led.c | 73 + phl/hal_g6/hal_mcc.c | 418 + phl/hal_g6/hal_mcc.h | 25 + phl/hal_g6/hal_mcc_def.h | 19 + phl/hal_g6/hal_notify.c | 72 + phl/hal_g6/hal_notify.h | 34 + phl/hal_g6/hal_p2pps.c | 89 + phl/hal_g6/hal_ps.c | 370 + phl/hal_g6/hal_ps.h | 24 + phl/hal_g6/hal_regulation.c | 23 + phl/hal_g6/hal_rx.c | 551 + phl/hal_g6/hal_rx.h | 38 + phl/hal_g6/hal_ser.c | 103 + phl/hal_g6/hal_ser.h | 18 + phl/hal_g6/hal_sound.c | 1025 + phl/hal_g6/hal_sound.h | 69 + phl/hal_g6/hal_sta.c | 802 + phl/hal_g6/hal_sta.h | 26 + phl/hal_g6/hal_str_proc.c | 248 + phl/hal_g6/hal_str_proc.h | 43 + phl/hal_g6/hal_struct.h | 334 + phl/hal_g6/hal_thermal.c | 166 + phl/hal_g6/hal_trx_mit.c | 118 + phl/hal_g6/hal_twt.c | 37 + phl/hal_g6/hal_tx.c | 414 + phl/hal_g6/hal_tx.h | 45 + phl/hal_g6/hal_txpwr.c | 43 + phl/hal_g6/hal_txpwr.h | 25 + phl/hal_g6/hal_usb.c | 291 + phl/hal_g6/hal_usb.h | 60 + phl/hal_g6/hal_wow.c | 447 + phl/hal_g6/hal_wow.h | 23 + phl/hal_g6/mac/chip_cfg.h | 81 + phl/hal_g6/mac/chip_cfg_drv.h | 62 + phl/hal_g6/mac/errors.h | 274 + phl/hal_g6/mac/feature_cfg.h | 87 + phl/hal_g6/mac/feature_cfg_drv.h | 53 + phl/hal_g6/mac/fw_ax/inc_hdr/fwcmd_intf.h | 6128 + phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.c | 125838 +++++++++++++++ phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.h | 42 + .../mac/fw_ax/rtl8852b/hal8852b_fw_log.c | 719 + .../mac/fw_ax/rtl8852b/hal8852b_fw_log.h | 724 + .../mac/fw_ax/rtl8852b/hal8852b_fw_u1.c | 98850 +++++++++++ .../mac/fw_ax/rtl8852b/hal8852b_fw_u1.h | 42 + phl/hal_g6/mac/halmac_wpp.h | 37 + phl/hal_g6/mac/hv_type.h | 1093 + phl/hal_g6/mac/mac.mk | 128 + phl/hal_g6/mac/mac_ax.c | 544 + phl/hal_g6/mac/mac_ax.h | 128 + phl/hal_g6/mac/mac_ax/_usb.c | 79 + phl/hal_g6/mac/mac_ax/_usb.h | 124 + phl/hal_g6/mac/mac_ax/addr_cam.c | 763 + phl/hal_g6/mac/mac_ax/addr_cam.h | 330 + phl/hal_g6/mac/mac_ax/cmac_tx.c | 1853 + phl/hal_g6/mac/mac_ax/cmac_tx.h | 787 + phl/hal_g6/mac/mac_ax/coex.c | 498 + phl/hal_g6/mac/mac_ax/coex.h | 282 + phl/hal_g6/mac/mac_ax/cpuio.c | 1042 + phl/hal_g6/mac/mac_ax/cpuio.h | 719 + phl/hal_g6/mac/mac_ax/dbcc.c | 233 + phl/hal_g6/mac/mac_ax/dbcc.h | 53 + phl/hal_g6/mac/mac_ax/dbg_cmd.c | 1676 + phl/hal_g6/mac/mac_ax/dbg_cmd.h | 723 + phl/hal_g6/mac/mac_ax/dbgpkg.c | 6024 + phl/hal_g6/mac/mac_ax/dbgpkg.h | 1153 + phl/hal_g6/mac/mac_ax/dbgport_hw.c | 812 + phl/hal_g6/mac/mac_ax/dbgport_hw.h | 471 + phl/hal_g6/mac/mac_ax/dle.c | 2834 + phl/hal_g6/mac/mac_ax/dle.h | 704 + phl/hal_g6/mac/mac_ax/efuse.c | 3962 + phl/hal_g6/mac/mac_ax/efuse.h | 1059 + phl/hal_g6/mac/mac_ax/flash.c | 944 + phl/hal_g6/mac/mac_ax/flash.h | 52 + phl/hal_g6/mac/mac_ax/fwcmd.c | 3275 + phl/hal_g6/mac/mac_ax/fwcmd.h | 849 + phl/hal_g6/mac/mac_ax/fwcmd_intf_f2p.h | 519 + phl/hal_g6/mac/mac_ax/fwdl.c | 1262 + phl/hal_g6/mac/mac_ax/fwdl.h | 429 + phl/hal_g6/mac/mac_ax/fwofld.c | 2064 + phl/hal_g6/mac/mac_ax/fwofld.h | 936 + phl/hal_g6/mac/mac_ax/gpio.c | 735 + phl/hal_g6/mac/mac_ax/gpio.h | 318 + phl/hal_g6/mac/mac_ax/gpio_cmd.h | 321 + phl/hal_g6/mac/mac_ax/h2c_agg.c | 243 + phl/hal_g6/mac/mac_ax/h2c_agg.h | 32 + phl/hal_g6/mac/mac_ax/hci_fc.c | 1735 + phl/hal_g6/mac/mac_ax/hci_fc.h | 155 + phl/hal_g6/mac/mac_ax/hdr_conv.c | 90 + phl/hal_g6/mac/mac_ax/hdr_conv.h | 56 + phl/hal_g6/mac/mac_ax/hw.c | 2780 + phl/hal_g6/mac/mac_ax/hw.h | 1169 + phl/hal_g6/mac/mac_ax/hw_seq.c | 110 + phl/hal_g6/mac/mac_ax/hw_seq.h | 70 + phl/hal_g6/mac/mac_ax/hwamsdu.c | 226 + phl/hal_g6/mac/mac_ax/hwamsdu.h | 128 + phl/hal_g6/mac/mac_ax/init.c | 867 + phl/hal_g6/mac/mac_ax/init.h | 260 + phl/hal_g6/mac/mac_ax/la_mode.c | 132 + phl/hal_g6/mac/mac_ax/la_mode.h | 130 + phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.c | 521 + phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.h | 509 + phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.c | 1913 + phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.h | 46 + phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.c | 798 + phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.h | 32 + .../mac/mac_ax/mac_8852b/pwr_seq_8852b.c | 1486 + .../mac/mac_ax/mac_8852b/pwr_seq_8852b.h | 30 + .../mac/mac_ax/mac_8852b/pwr_seq_func_8852b.c | 2466 + .../mac/mac_ax/mac_8852b/pwr_seq_func_8852b.h | 43 + phl/hal_g6/mac/mac_ax/mac_ax_dfs.h | 28 + phl/hal_g6/mac/mac_ax/mac_ax_mac_info.h | 47 + phl/hal_g6/mac/mac_ax/mac_txccxrpt.h | 146 + phl/hal_g6/mac/mac_ax/mcc.c | 945 + phl/hal_g6/mac/mac_ax/mcc.h | 413 + phl/hal_g6/mac/mac_ax/mport.c | 2688 + phl/hal_g6/mac/mac_ax/mport.h | 271 + phl/hal_g6/mac/mac_ax/p2p.c | 367 + phl/hal_g6/mac/mac_ax/p2p.h | 118 + phl/hal_g6/mac/mac_ax/phy_misc.c | 116 + phl/hal_g6/mac/mac_ax/phy_misc.h | 26 + phl/hal_g6/mac/mac_ax/phy_rpt.c | 529 + phl/hal_g6/mac/mac_ax/phy_rpt.h | 98 + phl/hal_g6/mac/mac_ax/power_saving.c | 793 + phl/hal_g6/mac/mac_ax/power_saving.h | 354 + phl/hal_g6/mac/mac_ax/pwr.c | 373 + phl/hal_g6/mac/mac_ax/pwr.h | 120 + phl/hal_g6/mac/mac_ax/pwr_seq_func.c | 80 + phl/hal_g6/mac/mac_ax/pwr_seq_func.h | 28 + phl/hal_g6/mac/mac_ax/role.c | 1199 + phl/hal_g6/mac/mac_ax/role.h | 351 + phl/hal_g6/mac/mac_ax/rrsr.c | 133 + phl/hal_g6/mac/mac_ax/rrsr.h | 107 + phl/hal_g6/mac/mac_ax/rx_filter.c | 429 + phl/hal_g6/mac/mac_ax/rx_filter.h | 169 + phl/hal_g6/mac/mac_ax/rx_forwarding.c | 446 + phl/hal_g6/mac/mac_ax/rx_forwarding.h | 113 + phl/hal_g6/mac/mac_ax/security_cam.c | 1120 + phl/hal_g6/mac/mac_ax/security_cam.h | 335 + phl/hal_g6/mac/mac_ax/ser.c | 675 + phl/hal_g6/mac/mac_ax/ser.h | 747 + phl/hal_g6/mac/mac_ax/sounding.c | 1999 + phl/hal_g6/mac/mac_ax/sounding.h | 399 + phl/hal_g6/mac/mac_ax/spatial_reuse.c | 84 + phl/hal_g6/mac/mac_ax/spatial_reuse.h | 29 + phl/hal_g6/mac/mac_ax/sta_sch.c | 485 + phl/hal_g6/mac/mac_ax/sta_sch.h | 103 + phl/hal_g6/mac/mac_ax/state_mach.h | 221 + phl/hal_g6/mac/mac_ax/status.c | 149 + phl/hal_g6/mac/mac_ax/status.h | 73 + phl/hal_g6/mac/mac_ax/tblupd.c | 2430 + phl/hal_g6/mac/mac_ax/tblupd.h | 629 + .../mac/mac_ax/tcpip_checksum_offload.c | 124 + .../mac/mac_ax/tcpip_checksum_offload.h | 94 + phl/hal_g6/mac/mac_ax/trx_desc.c | 632 + phl/hal_g6/mac/mac_ax/trx_desc.h | 226 + phl/hal_g6/mac/mac_ax/trxcfg.c | 1842 + phl/hal_g6/mac/mac_ax/trxcfg.h | 276 + phl/hal_g6/mac/mac_ax/twt.c | 286 + phl/hal_g6/mac/mac_ax/twt.h | 134 + phl/hal_g6/mac/mac_ax/wowlan.c | 1775 + phl/hal_g6/mac/mac_ax/wowlan.h | 836 + phl/hal_g6/mac/mac_def.h | 15212 ++ phl/hal_g6/mac/mac_hw_info.h | 75 + phl/hal_g6/mac/mac_reg.h | 18433 +++ phl/hal_g6/mac/pcie_reg.h | 95 + phl/hal_g6/mac/pltfm_cfg.h | 161 + phl/hal_g6/mac/pltfm_cfg_drv.h | 69 + phl/hal_g6/mac/rxdesc.h | 152 + phl/hal_g6/mac/txdesc.h | 565 + phl/hal_g6/mac/type.h | 1873 + phl/hal_g6/phy/bb/bb.mk | 95 + phl/hal_g6/phy/bb/halbb.c | 1061 + phl/hal_g6/phy/bb/halbb.h | 395 + phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.c | 327 + phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.h | 51 + .../phy/bb/halbb_8852b/halbb_8852b_api.c | 2116 + .../phy/bb/halbb_8852b/halbb_8852b_api.h | 210 + .../phy/bb/halbb_8852b/halbb_8852b_api_ex.h | 35 + .../phy/bb/halbb_8852b/halbb_cr_info_8852b.h | 13825 ++ .../phy/bb/halbb_8852b/halbb_hwimg_8852b.c | 333 + .../phy/bb/halbb_8852b/halbb_hwimg_8852b.h | 50 + .../halbb_8852b/halbb_hwimg_raw_data_8852b.h | 1128 + .../halbb_hwimg_raw_data_8852b_gain.h | 31 + .../phy/bb/halbb_8852b/halbb_reg_cfg_8852b.c | 139 + .../phy/bb/halbb_8852b/halbb_reg_cfg_8852b.h | 34 + .../bb/halbb_8852b/halbb_version_rtl8852b.h | 30 + phl/hal_g6/phy/bb/halbb_ant_div.c | 1451 + phl/hal_g6/phy/bb/halbb_ant_div.h | 285 + phl/hal_g6/phy/bb/halbb_api.c | 2331 + phl/hal_g6/phy/bb/halbb_api.h | 73 + phl/hal_g6/phy/bb/halbb_api_ex.h | 129 + phl/hal_g6/phy/bb/halbb_auto_dbg.c | 122 + phl/hal_g6/phy/bb/halbb_auto_dbg.h | 55 + phl/hal_g6/phy/bb/halbb_cfg_ic.h | 46 + phl/hal_g6/phy/bb/halbb_cfo_trk.c | 1089 + phl/hal_g6/phy/bb/halbb_cfo_trk.h | 158 + phl/hal_g6/phy/bb/halbb_ch_info.c | 819 + phl/hal_g6/phy/bb/halbb_ch_info.h | 105 + phl/hal_g6/phy/bb/halbb_ch_info_ex.h | 126 + phl/hal_g6/phy/bb/halbb_cmn_rpt.c | 1226 + phl/hal_g6/phy/bb/halbb_cmn_rpt.h | 144 + phl/hal_g6/phy/bb/halbb_cmn_rpt_ex.h | 104 + phl/hal_g6/phy/bb/halbb_dbcc.c | 151 + phl/hal_g6/phy/bb/halbb_dbcc.h | 41 + phl/hal_g6/phy/bb/halbb_dbcc_ex.h | 36 + phl/hal_g6/phy/bb/halbb_dbg.c | 1581 + phl/hal_g6/phy/bb/halbb_dbg.h | 219 + phl/hal_g6/phy/bb/halbb_dbg_cmd.c | 865 + phl/hal_g6/phy/bb/halbb_dbg_cmd.h | 82 + phl/hal_g6/phy/bb/halbb_dbg_cmd_ex.h | 39 + phl/hal_g6/phy/bb/halbb_dbg_cmd_table.h | 134 + phl/hal_g6/phy/bb/halbb_dfs.c | 745 + phl/hal_g6/phy/bb/halbb_dfs.h | 173 + phl/hal_g6/phy/bb/halbb_dfs_ex.h | 39 + phl/hal_g6/phy/bb/halbb_dig.c | 2474 + phl/hal_g6/phy/bb/halbb_dig.h | 338 + phl/hal_g6/phy/bb/halbb_dig_ex.h | 50 + phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.c | 441 + phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.h | 57 + phl/hal_g6/phy/bb/halbb_dyn_csi_rsp_ex.h | 39 + phl/hal_g6/phy/bb/halbb_edcca.c | 614 + phl/hal_g6/phy/bb/halbb_edcca.h | 134 + phl/hal_g6/phy/bb/halbb_edcca_ex.h | 41 + phl/hal_g6/phy/bb/halbb_env_mntr.c | 3523 + phl/hal_g6/phy/bb/halbb_env_mntr.h | 428 + phl/hal_g6/phy/bb/halbb_env_mntr_ex.h | 216 + phl/hal_g6/phy/bb/halbb_ex.h | 191 + phl/hal_g6/phy/bb/halbb_export_fun.h | 64 + phl/hal_g6/phy/bb/halbb_features.h | 122 + phl/hal_g6/phy/bb/halbb_fwofld.c | 926 + phl/hal_g6/phy/bb/halbb_fwofld.h | 43 + phl/hal_g6/phy/bb/halbb_hw_cfg.c | 327 + phl/hal_g6/phy/bb/halbb_hw_cfg.h | 58 + phl/hal_g6/phy/bb/halbb_hw_cfg_ex.h | 41 + phl/hal_g6/phy/bb/halbb_ic_hw_info.h | 350 + phl/hal_g6/phy/bb/halbb_ic_sw_info.h | 56 + phl/hal_g6/phy/bb/halbb_init.c | 616 + phl/hal_g6/phy/bb/halbb_init.h | 29 + phl/hal_g6/phy/bb/halbb_init_ex.h | 37 + phl/hal_g6/phy/bb/halbb_interface.c | 582 + phl/hal_g6/phy/bb/halbb_interface.h | 216 + phl/hal_g6/phy/bb/halbb_interface_ex.h | 53 + phl/hal_g6/phy/bb/halbb_la_mode.c | 2254 + phl/hal_g6/phy/bb/halbb_la_mode.h | 433 + phl/hal_g6/phy/bb/halbb_la_mode_ex.h | 36 + phl/hal_g6/phy/bb/halbb_math_lib.c | 426 + phl/hal_g6/phy/bb/halbb_math_lib.h | 121 + phl/hal_g6/phy/bb/halbb_math_lib_ex.h | 38 + phl/hal_g6/phy/bb/halbb_mp.c | 853 + phl/hal_g6/phy/bb/halbb_mp_ex.h | 217 + phl/hal_g6/phy/bb/halbb_physts.c | 2702 + phl/hal_g6/phy/bb/halbb_physts.h | 746 + phl/hal_g6/phy/bb/halbb_physts_ex.h | 97 + phl/hal_g6/phy/bb/halbb_physts_ie_b_endian.h | 1191 + phl/hal_g6/phy/bb/halbb_physts_ie_l_endian.h | 1168 + phl/hal_g6/phy/bb/halbb_plcp_gen.c | 871 + phl/hal_g6/phy/bb/halbb_plcp_gen.h | 264 + phl/hal_g6/phy/bb/halbb_plcp_tx.c | 2406 + phl/hal_g6/phy/bb/halbb_plcp_tx.h | 370 + phl/hal_g6/phy/bb/halbb_plcp_tx_ex.h | 224 + phl/hal_g6/phy/bb/halbb_pmac_setting.c | 733 + phl/hal_g6/phy/bb/halbb_pmac_setting.h | 53 + phl/hal_g6/phy/bb/halbb_pmac_setting_ex.h | 113 + phl/hal_g6/phy/bb/halbb_precomp.h | 144 + phl/hal_g6/phy/bb/halbb_psd.c | 504 + phl/hal_g6/phy/bb/halbb_psd.h | 96 + phl/hal_g6/phy/bb/halbb_pwr_ctrl.c | 955 + phl/hal_g6/phy/bb/halbb_pwr_ctrl.h | 100 + phl/hal_g6/phy/bb/halbb_pwr_ctrl_ex.h | 32 + phl/hal_g6/phy/bb/halbb_ra.c | 2121 + phl/hal_g6/phy/bb/halbb_ra.h | 282 + phl/hal_g6/phy/bb/halbb_ra_b_endian.h | 252 + phl/hal_g6/phy/bb/halbb_ra_ex.h | 38 + phl/hal_g6/phy/bb/halbb_ra_l_endian.h | 250 + phl/hal_g6/phy/bb/halbb_rua_tbl.c | 1566 + phl/hal_g6/phy/bb/halbb_rua_tbl.h | 64 + phl/hal_g6/phy/bb/halbb_rua_tbl_b_endian.h | 408 + phl/hal_g6/phy/bb/halbb_rua_tbl_ex.h | 459 + phl/hal_g6/phy/bb/halbb_rua_tbl_l_endian.h | 408 + phl/hal_g6/phy/bb/halbb_statistics.c | 1497 + phl/hal_g6/phy/bb/halbb_statistics.h | 385 + phl/hal_g6/phy/bb/halbb_types.h | 33 + phl/hal_g6/phy/bb/halbb_wpp.h | 64 + phl/hal_g6/phy/rf/halrf.c | 2398 + phl/hal_g6/phy/rf/halrf.h | 289 + phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.c | 815 + phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.h | 55 + .../phy/rf/halrf_8852b/halrf_8852b_api.c | 286 + .../phy/rf/halrf_8852b/halrf_8852b_api.h | 44 + .../phy/rf/halrf_8852b/halrf_8852b_api_ex.h | 30 + .../phy/rf/halrf_8852b/halrf_dack_8852b.c | 702 + .../phy/rf/halrf_8852b/halrf_dack_8852b.h | 38 + .../phy/rf/halrf_8852b/halrf_dpk_8852b.c | 1599 + .../phy/rf/halrf_8852b/halrf_dpk_8852b.h | 52 + .../phy/rf/halrf_8852b/halrf_efuse_8852b.c | 337 + .../phy/rf/halrf_8852b/halrf_efuse_8852b.h | 111 + .../phy/rf/halrf_8852b/halrf_hwimg_8852b.c | 1168 + .../phy/rf/halrf_8852b/halrf_hwimg_8852b.h | 93 + .../halrf_hwimg_nctl_raw_data_8852b.h | 1352 + .../halrf_8852b/halrf_hwimg_raw_data_8852b.h | 10738 ++ .../phy/rf/halrf_8852b/halrf_iqk_8852b.c | 2089 + .../phy/rf/halrf_8852b/halrf_iqk_8852b.h | 106 + .../phy/rf/halrf_8852b/halrf_kfree_8852b.c | 228 + .../phy/rf/halrf_8852b/halrf_kfree_8852b.h | 55 + .../phy/rf/halrf_8852b/halrf_psd_8852b.c | 328 + .../phy/rf/halrf_8852b/halrf_psd_8852b.h | 39 + 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phl/hal_g6/phy/rf/halrf_hw_cfg.c | 230 + phl/hal_g6/phy/rf/halrf_hw_cfg.h | 36 + phl/hal_g6/phy/rf/halrf_hw_cfg_ex.h | 38 + phl/hal_g6/phy/rf/halrf_hwimg.h | 38 + phl/hal_g6/phy/rf/halrf_ic_hw_info.h | 105 + phl/hal_g6/phy/rf/halrf_ic_sw_info.h | 42 + phl/hal_g6/phy/rf/halrf_init.c | 379 + phl/hal_g6/phy/rf/halrf_init.h | 32 + phl/hal_g6/phy/rf/halrf_init_ex.h | 38 + phl/hal_g6/phy/rf/halrf_interface.c | 191 + phl/hal_g6/phy/rf/halrf_interface.h | 135 + phl/hal_g6/phy/rf/halrf_iqk.c | 833 + phl/hal_g6/phy/rf/halrf_iqk.h | 116 + phl/hal_g6/phy/rf/halrf_kfree.h | 45 + phl/hal_g6/phy/rf/halrf_pmac.c | 173 + phl/hal_g6/phy/rf/halrf_pmac.h | 142 + phl/hal_g6/phy/rf/halrf_precomp.h | 150 + phl/hal_g6/phy/rf/halrf_psd.h | 39 + phl/hal_g6/phy/rf/halrf_pwr_table.c | 1311 + phl/hal_g6/phy/rf/halrf_pwr_table.h | 375 + phl/hal_g6/phy/rf/halrf_pwr_track.h | 214 + phl/hal_g6/phy/rf/halrf_struct.h | 25 + phl/hal_g6/phy/rf/halrf_txgapk.h | 55 + phl/hal_g6/phy/rf/halrf_wpp.h | 52 + phl/hal_g6/phy/rf/rf.mk | 94 + phl/hal_g6/rtl8852b/hal_trx_8852b.c | 651 + phl/hal_g6/rtl8852b/hal_trx_8852b.h | 172 + phl/hal_g6/rtl8852b/rtl8852b.h | 41 + phl/hal_g6/rtl8852b/rtl8852b.mk | 50 + phl/hal_g6/rtl8852b/rtl8852b_cmd.c | 18 + phl/hal_g6/rtl8852b/rtl8852b_hal.h | 90 + phl/hal_g6/rtl8852b/rtl8852b_halinit.c | 668 + phl/hal_g6/rtl8852b/rtl8852b_mac.c | 18 + phl/hal_g6/rtl8852b/rtl8852b_ops.c | 76 + phl/hal_g6/rtl8852b/rtl8852b_phy.c | 17 + phl/hal_g6/rtl8852b/rtl8852b_phy.h | 20 + phl/hal_g6/rtl8852b/rtl8852b_spec.h | 19 + phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.c | 402 + phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.h | 28 + phl/hal_g6/rtl8852b/usb/rtl8852bu.h | 21 + phl/hal_g6/rtl8852b/usb/rtl8852bu_hal.h | 48 + phl/hal_g6/rtl8852b/usb/rtl8852bu_halinit.c | 341 + phl/hal_g6/rtl8852b/usb/rtl8852bu_halmac.c | 16 + phl/hal_g6/rtl8852b/usb/rtl8852bu_io.c | 31 + phl/hal_g6/rtl8852b/usb/rtl8852bu_led.c | 16 + phl/hal_g6/rtl8852b/usb/rtl8852bu_ops.c | 65 + phl/hal_g6/test/hal_test_module.c | 18 + phl/hal_g6/test/mp/hal_test_mp.c | 34 + phl/hal_g6/test/mp/hal_test_mp_api.h | 255 + phl/hal_g6/test/mp/hal_test_mp_cal.c | 285 + phl/hal_g6/test/mp/hal_test_mp_config.c | 409 + phl/hal_g6/test/mp/hal_test_mp_efuse.c | 496 + phl/hal_g6/test/mp/hal_test_mp_reg.c | 311 + phl/hal_g6/test/mp/hal_test_mp_rx.c | 203 + phl/hal_g6/test/mp/hal_test_mp_tx.c | 211 + phl/hal_g6/test/mp/hal_test_mp_txpwr.c | 316 + phl/hci/phl_trx_def_usb.h | 50 + phl/hci/phl_trx_usb.c | 2006 + phl/hci/phl_trx_usb.h | 59 + phl/phl.mk | 121 + phl/phl_acs.c | 105 + phl/phl_acs.h | 24 + phl/phl_api.h | 684 + phl/phl_api_drv.c | 159 + phl/phl_api_drv.h | 96 + phl/phl_btc.h | 34 + phl/phl_btc_def.h | 181 + phl/phl_btc_fsm.c | 464 + phl/phl_btc_fsm.h | 40 + phl/phl_chan.c | 1532 + phl/phl_chan.h | 87 + phl/phl_chan_info.c | 366 + phl/phl_chan_info.h | 41 + phl/phl_chnlplan.c | 199 + phl/phl_chnlplan.h | 132 + phl/phl_chnlplan_6g.c | 38 + phl/phl_chnlplan_6g.h | 85 + phl/phl_cmd_btc.c | 515 + phl/phl_cmd_btc.h | 21 + phl/phl_cmd_dispatch.h | 162 + phl/phl_cmd_dispatch_engine.c | 770 + phl/phl_cmd_dispatcher.c | 2482 + phl/phl_cmd_dispr_controller.c | 684 + phl/phl_cmd_fsm.c | 782 + phl/phl_cmd_fsm.h | 56 + phl/phl_cmd_general.c | 658 + phl/phl_cmd_general.h | 35 + phl/phl_cmd_job.c | 198 + phl/phl_cmd_job.h | 126 + phl/phl_cmd_ps.c | 1900 + phl/phl_cmd_ps.h | 47 + phl/phl_cmd_scan.c | 966 + phl/phl_cmd_ser.c | 918 + phl/phl_cmd_ser.h | 30 + phl/phl_config.h | 431 + phl/phl_connect.c | 533 + phl/phl_connect.h | 100 + phl/phl_country.c | 260 + phl/phl_country.h | 46 + phl/phl_debug.c | 217 + phl/phl_debug.h | 186 + phl/phl_def.h | 3200 + phl/phl_dm.c | 136 + phl/phl_dm.h | 36 + phl/phl_ecsa.c | 974 + phl/phl_ecsa.h | 57 + phl/phl_ecsa_export.h | 150 + phl/phl_ext_tx_pwr_lmt.c | 95 + phl/phl_ext_tx_pwr_lmt_def.h | 29 + phl/phl_fsm.c | 2197 + phl/phl_fsm.h | 282 + phl/phl_git_info.h | 43 + phl/phl_headers.h | 145 + phl/phl_headers_core.h | 60 + phl/phl_init.c | 2500 + phl/phl_led.c | 1033 + phl/phl_led.h | 22 + phl/phl_led_def.h | 97 + phl/phl_list.h | 229 + phl/phl_mcc.c | 3887 + phl/phl_mcc.h | 87 + phl/phl_mcc_def.h | 93 + phl/phl_mr.c | 3667 + phl/phl_mr.h | 185 + phl/phl_msg_hub.c | 398 + phl/phl_msg_hub.h | 37 + phl/phl_notify.c | 122 + phl/phl_notify.h | 30 + phl/phl_p2pps.c | 765 + phl/phl_p2pps.h | 68 + phl/phl_p2pps_def.h | 35 + phl/phl_pkt_ofld.c | 1106 + phl/phl_pkt_ofld.h | 235 + phl/phl_ps.c | 425 + phl/phl_ps.h | 54 + phl/phl_regulation.c | 1242 + phl/phl_regulation.h | 96 + phl/phl_regulation_6g.c | 331 + phl/phl_regulation_6g.h | 23 + phl/phl_regulation_def.h | 175 + phl/phl_role.c | 1280 + phl/phl_role.h | 82 + phl/phl_rx.c | 1715 + phl/phl_rx.h | 70 + phl/phl_rx_agg.c | 284 + phl/phl_rx_agg.h | 33 + phl/phl_scan.h | 169 + phl/phl_scan_fsm.c | 1489 + phl/phl_scan_fsm.h | 31 + phl/phl_scan_instance.c | 319 + phl/phl_scan_instance.h | 62 + phl/phl_sec.c | 239 + phl/phl_ser_def.h | 40 + phl/phl_ser_fsm.c | 1387 + phl/phl_ser_fsm.h | 41 + phl/phl_sound.c | 1764 + phl/phl_sound.h | 248 + phl/phl_sound_cmd.c | 581 + phl/phl_sound_cmd.h | 52 + phl/phl_sound_fsm.c | 762 + phl/phl_sound_fsm.h | 94 + phl/phl_sta.c | 2488 + phl/phl_sta.h | 167 + phl/phl_status.h | 49 + phl/phl_struct.h | 351 + phl/phl_sw_cap.c | 862 + phl/phl_sw_cap.h | 33 + phl/phl_test.h | 71 + phl/phl_test_def.h | 152 + phl/phl_thermal.c | 163 + phl/phl_thermal.h | 26 + phl/phl_trx_def.h | 605 + phl/phl_trx_mit.c | 133 + phl/phl_trx_mit.h | 28 + phl/phl_twt.c | 2173 + phl/phl_twt.h | 268 + phl/phl_tx.c | 2212 + phl/phl_tx.h | 93 + phl/phl_txpwr.c | 43 + phl/phl_txpwr.h | 24 + phl/phl_types.h | 225 + phl/phl_util.c | 227 + phl/phl_util.h | 115 + phl/phl_version.h | 28 + phl/phl_watchdog.c | 231 + phl/phl_watchdog.h | 40 + phl/phl_wow.c | 1803 + phl/phl_wow.h | 132 + phl/phl_wow_def.h | 306 + phl/phl_wpp.h | 286 + phl/pltfm_ops.h | 28 + phl/pltfm_ops_linux.h | 957 + phl/pltfm_ops_macos.h | 528 + phl/pltfm_ops_none.h | 863 + phl/pltfm_ops_windows.h | 891 + phl/rtw_general_def.h | 621 + phl/test/cmd_disp_test.c | 1069 + phl/test/cmd_disp_test.h | 27 + phl/test/mp/phl_test_mp.c | 494 + phl/test/mp/phl_test_mp_api.h | 28 + phl/test/mp/phl_test_mp_cal.c | 346 + phl/test/mp/phl_test_mp_config.c | 495 + phl/test/mp/phl_test_mp_def.h | 731 + phl/test/mp/phl_test_mp_efuse.c | 811 + phl/test/mp/phl_test_mp_reg.c | 321 + phl/test/mp/phl_test_mp_rx.c | 323 + phl/test/mp/phl_test_mp_tx.c | 1045 + phl/test/mp/phl_test_mp_txpwr.c | 495 + phl/test/phl_dbg_cmd.c | 1443 + phl/test/phl_dbg_cmd.h | 101 + phl/test/phl_ps_dbg_cmd.c | 247 + phl/test/phl_ps_dbg_cmd.h | 37 + phl/test/phl_ser_dbg_cmd.c | 124 + phl/test/phl_ser_dbg_cmd.h | 21 + phl/test/test_module.c | 758 + phl/test/trx_test.c | 1331 + phl/test/trx_test.h | 198 + phl/test/verify/dbcc/phl_test_dbcc.c | 216 + phl/test/verify/dbcc/phl_test_dbcc_api.h | 23 + phl/test/verify/dbcc/phl_test_dbcc_def.h | 118 + phl/test/verify/phl_test_verify.c | 394 + phl/test/verify/phl_test_verify_api.h | 34 + phl/test/verify/phl_test_verify_def.h | 60 + platform/aml_s905.mk | 45 + platform/android_intel_x86.mk | 11 + platform/android_x86.mk | 8 + platform/arm_1319.mk | 33 + platform/arm_1619b.mk | 36 + platform/arm_rk3588.mk | 34 + platform/arm_sunxi.mk | 25 + platform/autoconf_arm_9617b.h | 8 + platform/autoconf_i386_ap_func.h | 19 + platform/autoconf_mips_98d.h | 35 + platform/custom_country_chplan.h | 2 +- platform/i386_pc.mk | 21 + platform/mips_98d.mk | 14 + platform/nv_tk1.mk | 17 + platform/nv_tk1_ubuntu.mk | 14 + platform/platform_linux_pc_pci.c | 99 + platform/platform_mips_98d_pci.c | 171 + platform/platform_ops.c | 18 - platform/platform_ops.h | 28 +- 832 files changed, 671274 insertions(+), 69915 deletions(-) create mode 100644 common.mk create mode 100644 core/rtw_btc.c create mode 100644 core/rtw_csa.c create mode 100644 core/rtw_fake_ap.c create mode 100644 core/rtw_he.c create mode 100644 core/rtw_phl.c create mode 100644 core/rtw_phl_cmd.c create mode 100644 core/rtw_recv_shortcut.c create mode 100644 core/rtw_scan.c create mode 100644 core/rtw_sec_cam.c create mode 100644 core/rtw_trx.c create mode 100644 core/rtw_trx_pci.c create mode 100644 core/rtw_trx_sdio.c create mode 100644 core/rtw_trx_usb.c create mode 100644 core/rtw_wow.c create mode 100644 core/rtw_xmit_shortcut.c create mode 100644 include/_hal_api_tmp.h create mode 100644 include/_hal_rate.h create mode 100644 include/drv_types_usb.h create mode 100644 include/pci_ops_linux.h create mode 100644 include/phl_api_tmp.h create mode 100644 include/rtw_btc.h create mode 100644 include/rtw_cfg.h create mode 100644 include/rtw_csa.h create mode 100644 include/rtw_he.h create mode 100644 include/rtw_hwsim_intf.h create mode 100644 include/rtw_phl.h create mode 100644 include/rtw_phl_cmd.h create mode 100644 include/rtw_recv_shortcut.h create mode 100644 include/rtw_scan.h create mode 100644 include/rtw_sec_cam.h create mode 100644 include/rtw_trx.h create mode 100644 include/rtw_trx_ops.h create mode 100644 include/rtw_trx_pci.h create mode 100644 include/rtw_trx_sdio.h create mode 100644 include/rtw_trx_usb.h create mode 100644 include/rtw_wow.h create mode 100644 include/rtw_xmit_shortcut.h create mode 100644 os_dep/linux/ioctl_efuse.c create mode 100644 os_dep/linux/rtw_cfg.c create mode 100644 os_dep/osdep_service_linux.c create mode 100644 phl/custom/phl_custom.c create mode 100644 phl/custom/phl_custom.h create mode 100644 phl/custom/phl_custom_api.h create mode 100644 phl/custom/phl_custom_def.h create mode 100644 phl/custom/phl_custom_fb.c create mode 100644 phl/custom/phl_custom_fb.h create mode 100644 phl/hal_g6/btc/btc.mk create mode 100644 phl/hal_g6/btc/btc_8852b/btc_8852b.c create mode 100644 phl/hal_g6/btc/btc_8852b/btc_8852b.h create mode 100644 phl/hal_g6/btc/hal_btc.c create mode 100644 phl/hal_g6/btc/hal_btc.h create mode 100644 phl/hal_g6/btc/halbtc_action.c create mode 100644 phl/hal_g6/btc/halbtc_action.h create mode 100644 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phl/hal_g6/hal_api_mac.c create mode 100644 phl/hal_g6/hal_api_mac.h create mode 100644 phl/hal_g6/hal_api_rf.c create mode 100644 phl/hal_g6/hal_api_rf.h create mode 100644 phl/hal_g6/hal_beamform.c create mode 100644 phl/hal_g6/hal_beamform.h create mode 100644 phl/hal_g6/hal_c2h.c create mode 100644 phl/hal_g6/hal_c2h.h create mode 100644 phl/hal_g6/hal_cam.c create mode 100644 phl/hal_g6/hal_cap.c create mode 100644 phl/hal_g6/hal_chan.c create mode 100644 phl/hal_g6/hal_chan.h create mode 100644 phl/hal_g6/hal_chan_info.c create mode 100644 phl/hal_g6/hal_chan_info.h create mode 100644 phl/hal_g6/hal_com_i.c create mode 100644 phl/hal_g6/hal_config.h create mode 100644 phl/hal_g6/hal_csi_buffer.c create mode 100644 phl/hal_g6/hal_csi_buffer.h create mode 100644 phl/hal_g6/hal_custom.c create mode 100644 phl/hal_g6/hal_custom.h create mode 100644 phl/hal_g6/hal_dbcc.c create mode 100644 phl/hal_g6/hal_dbcc.h create mode 100644 phl/hal_g6/hal_def.h create mode 100644 phl/hal_g6/hal_def_btc.h create mode 100644 phl/hal_g6/hal_def_mac.h create mode 100644 phl/hal_g6/hal_def_phy.h create mode 100644 phl/hal_g6/hal_ext_tx_pwr_lmt.c create mode 100644 phl/hal_g6/hal_fw.c create mode 100644 phl/hal_g6/hal_fw.h create mode 100644 phl/hal_g6/hal_general_def.h create mode 100644 phl/hal_g6/hal_headers.h create mode 100644 phl/hal_g6/hal_headers_le.h create mode 100644 phl/hal_g6/hal_init.c create mode 100644 phl/hal_g6/hal_io.c create mode 100644 phl/hal_g6/hal_io.h create mode 100644 phl/hal_g6/hal_ld_file.c create mode 100644 phl/hal_g6/hal_ld_file.h create mode 100644 phl/hal_g6/hal_led.c create mode 100644 phl/hal_g6/hal_mcc.c create mode 100644 phl/hal_g6/hal_mcc.h create mode 100644 phl/hal_g6/hal_mcc_def.h create mode 100644 phl/hal_g6/hal_notify.c create mode 100644 phl/hal_g6/hal_notify.h create mode 100644 phl/hal_g6/hal_p2pps.c create mode 100644 phl/hal_g6/hal_ps.c create mode 100644 phl/hal_g6/hal_ps.h create mode 100644 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mode 100644 phl/hal_g6/mac/mac_ax/addr_cam.h create mode 100644 phl/hal_g6/mac/mac_ax/cmac_tx.c create mode 100644 phl/hal_g6/mac/mac_ax/cmac_tx.h create mode 100644 phl/hal_g6/mac/mac_ax/coex.c create mode 100644 phl/hal_g6/mac/mac_ax/coex.h create mode 100644 phl/hal_g6/mac/mac_ax/cpuio.c create mode 100644 phl/hal_g6/mac/mac_ax/cpuio.h create mode 100644 phl/hal_g6/mac/mac_ax/dbcc.c create mode 100644 phl/hal_g6/mac/mac_ax/dbcc.h create mode 100644 phl/hal_g6/mac/mac_ax/dbg_cmd.c create mode 100644 phl/hal_g6/mac/mac_ax/dbg_cmd.h create mode 100644 phl/hal_g6/mac/mac_ax/dbgpkg.c create mode 100644 phl/hal_g6/mac/mac_ax/dbgpkg.h create mode 100644 phl/hal_g6/mac/mac_ax/dbgport_hw.c create mode 100644 phl/hal_g6/mac/mac_ax/dbgport_hw.h create mode 100644 phl/hal_g6/mac/mac_ax/dle.c create mode 100644 phl/hal_g6/mac/mac_ax/dle.h create mode 100644 phl/hal_g6/mac/mac_ax/efuse.c create mode 100644 phl/hal_g6/mac/mac_ax/efuse.h create mode 100644 phl/hal_g6/mac/mac_ax/flash.c create mode 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phl/hal_g6/mac/mac_ax/role.c create mode 100644 phl/hal_g6/mac/mac_ax/role.h create mode 100644 phl/hal_g6/mac/mac_ax/rrsr.c create mode 100644 phl/hal_g6/mac/mac_ax/rrsr.h create mode 100644 phl/hal_g6/mac/mac_ax/rx_filter.c create mode 100644 phl/hal_g6/mac/mac_ax/rx_filter.h create mode 100644 phl/hal_g6/mac/mac_ax/rx_forwarding.c create mode 100644 phl/hal_g6/mac/mac_ax/rx_forwarding.h create mode 100644 phl/hal_g6/mac/mac_ax/security_cam.c create mode 100644 phl/hal_g6/mac/mac_ax/security_cam.h create mode 100644 phl/hal_g6/mac/mac_ax/ser.c create mode 100644 phl/hal_g6/mac/mac_ax/ser.h create mode 100644 phl/hal_g6/mac/mac_ax/sounding.c create mode 100644 phl/hal_g6/mac/mac_ax/sounding.h create mode 100644 phl/hal_g6/mac/mac_ax/spatial_reuse.c create mode 100644 phl/hal_g6/mac/mac_ax/spatial_reuse.h create mode 100644 phl/hal_g6/mac/mac_ax/sta_sch.c create mode 100644 phl/hal_g6/mac/mac_ax/sta_sch.h create mode 100644 phl/hal_g6/mac/mac_ax/state_mach.h create mode 100644 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100644 phl/phl_util.c create mode 100644 phl/phl_util.h create mode 100644 phl/phl_version.h create mode 100644 phl/phl_watchdog.c create mode 100644 phl/phl_watchdog.h create mode 100644 phl/phl_wow.c create mode 100644 phl/phl_wow.h create mode 100644 phl/phl_wow_def.h create mode 100644 phl/phl_wpp.h create mode 100644 phl/pltfm_ops.h create mode 100644 phl/pltfm_ops_linux.h create mode 100644 phl/pltfm_ops_macos.h create mode 100644 phl/pltfm_ops_none.h create mode 100644 phl/pltfm_ops_windows.h create mode 100644 phl/rtw_general_def.h create mode 100644 phl/test/cmd_disp_test.c create mode 100644 phl/test/cmd_disp_test.h create mode 100644 phl/test/mp/phl_test_mp.c create mode 100644 phl/test/mp/phl_test_mp_api.h create mode 100644 phl/test/mp/phl_test_mp_cal.c create mode 100644 phl/test/mp/phl_test_mp_config.c create mode 100644 phl/test/mp/phl_test_mp_def.h create mode 100644 phl/test/mp/phl_test_mp_efuse.c create mode 100644 phl/test/mp/phl_test_mp_reg.c create mode 100644 phl/test/mp/phl_test_mp_rx.c create mode 100644 phl/test/mp/phl_test_mp_tx.c create mode 100644 phl/test/mp/phl_test_mp_txpwr.c create mode 100644 phl/test/phl_dbg_cmd.c create mode 100644 phl/test/phl_dbg_cmd.h create mode 100644 phl/test/phl_ps_dbg_cmd.c create mode 100644 phl/test/phl_ps_dbg_cmd.h create mode 100644 phl/test/phl_ser_dbg_cmd.c create mode 100644 phl/test/phl_ser_dbg_cmd.h create mode 100644 phl/test/test_module.c create mode 100644 phl/test/trx_test.c create mode 100644 phl/test/trx_test.h create mode 100644 phl/test/verify/dbcc/phl_test_dbcc.c create mode 100644 phl/test/verify/dbcc/phl_test_dbcc_api.h create mode 100644 phl/test/verify/dbcc/phl_test_dbcc_def.h create mode 100644 phl/test/verify/phl_test_verify.c create mode 100644 phl/test/verify/phl_test_verify_api.h create mode 100644 phl/test/verify/phl_test_verify_def.h create mode 100644 platform/aml_s905.mk create mode 100644 platform/android_intel_x86.mk create mode 100644 platform/android_x86.mk create mode 100644 platform/arm_1319.mk create mode 100644 platform/arm_1619b.mk create mode 100644 platform/arm_rk3588.mk create mode 100644 platform/arm_sunxi.mk create mode 100644 platform/autoconf_arm_9617b.h create mode 100644 platform/autoconf_i386_ap_func.h create mode 100644 platform/autoconf_mips_98d.h create mode 100644 platform/i386_pc.mk create mode 100644 platform/mips_98d.mk create mode 100644 platform/nv_tk1.mk create mode 100644 platform/nv_tk1_ubuntu.mk create mode 100644 platform/platform_linux_pc_pci.c create mode 100644 platform/platform_mips_98d_pci.c diff --git a/Kconfig b/Kconfig index 4c65974..fb88418 100644 --- a/Kconfig +++ b/Kconfig @@ -1,5 +1,6 @@ -config RTL8822BU - tristate "Realtek 8822B USB WiFi" +config RTL8852BU + tristate "Realtek 8852B USB WiFi" depends on USB help - Help message of RTL8822B \ No newline at end of file + Help message of RTL8852BU + diff --git a/build_chroot.sh b/build_chroot.sh index a47c94f..af31952 100644 --- a/build_chroot.sh +++ b/build_chroot.sh @@ -42,7 +42,7 @@ if [[ -e /etc/os-release && $(grep -c "Raspbian" /etc/os-release) -gt 0 ]]; then else sudo apt update sudo apt install -y build-essential flex bc bison dkms -make KSRC=/usr/src/linux-headers-6.3.13-060313-generic O="" modules +make ARCH=x86 CROSS_COMPILE= -C /usr/src/linux-headers-6.3.13-060313-generic M=/opt/additionalFiles modules mkdir -p package/lib/modules/6.3.13-060313-generic/kernel/drivers/net/wireless/ cp *.ko package/lib/modules/6.3.13-060313-generic/kernel/drivers/net/wireless/ ls -a diff --git a/common.mk b/common.mk new file mode 100644 index 0000000..a32ab26 --- /dev/null +++ b/common.mk @@ -0,0 +1,142 @@ +########### OS_DEP PATH ################################# +_OS_INTFS_FILES := os_dep/osdep_service.o \ + os_dep/osdep_service_linux.o \ + os_dep/linux/rtw_cfg.o \ + os_dep/linux/os_intfs.o \ + os_dep/linux/ioctl_linux.o \ + os_dep/linux/xmit_linux.o \ + os_dep/linux/mlme_linux.o \ + os_dep/linux/recv_linux.o \ + os_dep/linux/ioctl_cfg80211.o \ + os_dep/linux/rtw_cfgvendor.o \ + os_dep/linux/wifi_regd.o \ + os_dep/linux/rtw_android.o \ + os_dep/linux/rtw_proc.o \ + os_dep/linux/nlrtw.o \ + os_dep/linux/rtw_rhashtable.o + +ifeq ($(CONFIG_HWSIM), y) + _OS_INTFS_FILES += os_dep/linux/hwsim/medium/local.o + _OS_INTFS_FILES += os_dep/linux/hwsim/medium/sock_udp.o + _OS_INTFS_FILES += os_dep/linux/hwsim/medium/loopback.o + _OS_INTFS_FILES += os_dep/linux/hwsim/core.o + _OS_INTFS_FILES += os_dep/linux/hwsim/txrx.o + _OS_INTFS_FILES += os_dep/linux/hwsim/netdev.o + _OS_INTFS_FILES += os_dep/linux/hwsim/cfg80211.o + _OS_INTFS_FILES += os_dep/linux/hwsim/platform_dev.o + + _OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o +else + _OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_intf.o + _OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o +endif + +ifeq ($(CONFIG_MP_INCLUDED), y) +_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o \ + os_dep/linux/ioctl_efuse.o +endif + +ifeq ($(CONFIG_SDIO_HCI), y) +_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o +endif + +ifeq ($(CONFIG_GSPI_HCI), y) +_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o +endif + +########### CORE PATH ################################# +_CORE_FILES := core/rtw_cmd.o \ + core/rtw_security.o \ + core/rtw_debug.o \ + core/rtw_io.o \ + core/rtw_ioctl_query.o \ + core/rtw_ioctl_set.o \ + core/rtw_ieee80211.o \ + core/rtw_mlme.o \ + core/rtw_mlme_ext.o \ + core/rtw_sec_cam.o \ + core/rtw_mi.o \ + core/rtw_wlan_util.o \ + core/rtw_vht.o \ + core/rtw_he.o \ + core/rtw_pwrctrl.o \ + core/rtw_rf.o \ + core/rtw_chplan.o \ + core/monitor/rtw_radiotap.o \ + core/rtw_recv.o \ + core/rtw_recv_shortcut.o \ + core/rtw_sta_mgt.o \ + core/rtw_ap.o \ + core/rtw_csa.o \ + core/wds/rtw_wds.o \ + core/mesh/rtw_mesh.o \ + core/mesh/rtw_mesh_pathtbl.o \ + core/mesh/rtw_mesh_hwmp.o \ + core/rtw_xmit.o \ + core/rtw_xmit_shortcut.o \ + core/rtw_p2p.o \ + core/rtw_tdls.o \ + core/rtw_br_ext.o \ + core/rtw_sreset.o \ + core/rtw_rm.o \ + core/rtw_rm_fsm.o \ + core/rtw_rm_util.o \ + core/rtw_trx.o \ + core/rtw_beamforming.o \ + core/rtw_scan.o + #core/efuse/rtw_efuse.o + +_CORE_FILES += core/rtw_phl.o \ + core/rtw_phl_cmd.o + +EXTRA_CFLAGS += -I$(src)/core/crypto +_CORE_FILES += core/crypto/aes-internal.o \ + core/crypto/aes-internal-enc.o \ + core/crypto/aes-gcm.o \ + core/crypto/aes-ccm.o \ + core/crypto/aes-omac1.o \ + core/crypto/ccmp.o \ + core/crypto/gcmp.o \ + core/crypto/aes-siv.o \ + core/crypto/aes-ctr.o \ + core/crypto/sha256-internal.o \ + core/crypto/sha256.o \ + core/crypto/sha256-prf.o \ + core/crypto/rtw_crypto_wrap.o \ + core/rtw_swcrypto.o + +ifeq ($(CONFIG_WOWLAN), y) +_CORE_FILES += core/rtw_wow.o +endif + +ifeq ($(CONFIG_PCI_HCI), y) +_CORE_FILES += core/rtw_trx_pci.o +endif + +ifeq ($(CONFIG_USB_HCI), y) +_CORE_FILES += core/rtw_trx_usb.o +endif + +ifeq ($(CONFIG_SDIO_HCI), y) +_CORE_FILES += core/rtw_sdio.o +_CORE_FILES += core/rtw_trx_sdio.o +endif + +ifeq ($(CONFIG_MP_INCLUDED), y) +_CORE_FILES += core/rtw_mp.o +endif + +ifeq ($(CONFIG_WAPI_SUPPORT), y) +_CORE_FILES += core/rtw_wapi.o \ + core/rtw_wapi_sms4.o +endif + +ifeq ($(CONFIG_BTC), y) +_CORE_FILES += core/rtw_btc.o +endif + +ifeq ($(CONFIG_RTW_MBO), y) +_CORE_FILES += core/rtw_mbo.o core/rtw_ft.o core/rtw_wnm.o +endif + +OBJS += $(_OS_INTFS_FILES) $(_CORE_FILES) diff --git a/core/crypto/ccmp.c b/core/crypto/ccmp.c index 3ebd487..793e2b4 100644 --- a/core/crypto/ccmp.c +++ b/core/crypto/ccmp.c @@ -47,7 +47,7 @@ static void ccmp_aad_nonce(_adapter *padapter, const struct ieee80211_hdr *hdr, fc |= WLAN_FC_ISWEP; WPA_PUT_LE16(aad, fc); pos = aad + 2; - os_memcpy(pos, GetAddr1Ptr((u8 *)hdr), 3 * ETH_ALEN); + os_memcpy(pos, hdr->addr1, 3 * ETH_ALEN); pos += 3 * ETH_ALEN; seq = le_to_host16(hdr->seq_ctrl); seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */ @@ -383,3 +383,128 @@ u8 * ccmp_256_encrypt(_adapter *padapter, const u8 *tk, u8 *frame, size_t len, s return crypt; } + +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +void core_ccmp_encrypt(const u8 *tk, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata, + u8 *qos, u8 *pn, int keyid, size_t *encrypted_len) +{ + u8 aad[30], nonce[13]; + size_t aad_len; + u8 *crypt, *pos; + struct ieee80211_hdr *hdr; + size_t enc_hdrlen, enc_datalen = 0; + + if (hdrlen < 24) + return; + + enc_hdrlen = hdrlen + 8; + enc_datalen = datalen + 8; + + crypt = os_malloc(enc_hdrlen + enc_hdrlen + AES_BLOCK_SIZE); + if (crypt == NULL) + return; + + if (pn == NULL) { + os_memcpy(crypt, phdr, hdrlen + 8); + hdr = (struct ieee80211_hdr *) crypt; + hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP); + pos = crypt + hdrlen + 8; + } else { + os_memcpy(crypt, phdr, hdrlen); + hdr = (struct ieee80211_hdr *) crypt; + hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP); + pos = crypt + hdrlen; + *pos++ = pn[5]; /* PN0 */ + *pos++ = pn[4]; /* PN1 */ + *pos++ = 0x00; /* Rsvd */ + *pos++ = 0x20 | (keyid << 6); + *pos++ = pn[3]; /* PN2 */ + *pos++ = pn[2]; /* PN3 */ + *pos++ = pn[1]; /* PN4 */ + *pos++ = pn[0]; /* PN5 */ + } + + os_memset(aad, 0, sizeof(aad)); + ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce); + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len); + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, 13); + + if (aes_ccm_ae(tk, 16, nonce, 8, pdata, datalen, aad, aad_len, + pos, pos + datalen) < 0) { + rtw_mfree(crypt, hdrlen + 8 + datalen + 8 + AES_BLOCK_SIZE); + return; + } + + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP encrypted", crypt + enc_hdrlen, datalen); + + /* Copy @enc back to @frame and free @enc */ + _rtw_memcpy(phdr, crypt, enc_hdrlen); + _rtw_memcpy(pdata, crypt + enc_hdrlen, enc_datalen); + + rtw_mfree(crypt, enc_hdrlen+enc_datalen+AES_BLOCK_SIZE); + + return; +} + + +void core_ccmp_256_encrypt(const u8 *tk, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata, + u8 *qos, u8 *pn, int keyid, size_t *encrypted_len) +{ + u8 aad[30], nonce[13]; + size_t aad_len; + u8 *crypt, *pos; + struct ieee80211_hdr *hdr; + size_t enc_hdrlen, enc_datalen = 0; + + if (hdrlen < 24) + return; + + enc_hdrlen = hdrlen + 8; + enc_datalen = datalen + 16; + + crypt = os_malloc(enc_hdrlen + enc_hdrlen + AES_BLOCK_SIZE); + + if (crypt == NULL) + return; + + if (pn == NULL) { + os_memcpy(crypt, phdr, hdrlen + 8); + hdr = (struct ieee80211_hdr *) crypt; + hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP); + pos = crypt + hdrlen + 8; + } else { + os_memcpy(crypt, phdr, hdrlen); + hdr = (struct ieee80211_hdr *) crypt; + hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP); + pos = crypt + hdrlen; + *pos++ = pn[5]; /* PN0 */ + *pos++ = pn[4]; /* PN1 */ + *pos++ = 0x00; /* Rsvd */ + *pos++ = 0x20 | (keyid << 6); + *pos++ = pn[3]; /* PN2 */ + *pos++ = pn[2]; /* PN3 */ + *pos++ = pn[1]; /* PN4 */ + *pos++ = pn[0]; /* PN5 */ + } + + os_memset(aad, 0, sizeof(aad)); + ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce); + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 AAD", aad, aad_len); + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 nonce", nonce, 13); + + if (aes_ccm_ae(tk, 32, nonce, 16, pdata, datalen, aad, aad_len, + pos, pos + datalen) < 0) { + rtw_mfree(crypt, enc_hdrlen + enc_datalen + AES_BLOCK_SIZE); + return; + } + + wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 encrypted", crypt + enc_hdrlen, datalen); + + _rtw_memcpy(phdr, crypt, enc_hdrlen); + _rtw_memcpy(pdata, crypt + enc_hdrlen, enc_datalen); + + rtw_mfree(crypt, enc_hdrlen+enc_datalen+AES_BLOCK_SIZE); +} + + +#endif diff --git a/core/crypto/gcmp.c b/core/crypto/gcmp.c index 9141d55..251e567 100644 --- a/core/crypto/gcmp.c +++ b/core/crypto/gcmp.c @@ -41,7 +41,7 @@ static void gcmp_aad_nonce(_adapter * padapter, const struct ieee80211_hdr *hdr, fc &= ~(WLAN_FC_RETRY | WLAN_FC_PWRMGT | WLAN_FC_MOREDATA); WPA_PUT_LE16(aad, fc); pos = aad + 2; - os_memcpy(pos, GetAddr1Ptr((u8 *)hdr), 3 * ETH_ALEN); + os_memcpy(pos, hdr->addr1, 3 * ETH_ALEN); pos += 3 * ETH_ALEN; seq = le_to_host16(hdr->seq_ctrl); seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */ diff --git a/core/crypto/wlancrypto_wrap.h b/core/crypto/wlancrypto_wrap.h index b909a43..d39ce99 100644 --- a/core/crypto/wlancrypto_wrap.h +++ b/core/crypto/wlancrypto_wrap.h @@ -31,4 +31,11 @@ u8* gcmp_encrypt(_adapter *padapter, const u8 *tk, size_t tk_len, const u8 *fram size_t hdrlen, const u8 *qos, const u8 *pn, int keyid, size_t *encrypted_len); +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +void core_ccmp_encrypt(const u8 *tk, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata, + u8 *qos, u8 *pn, int keyid, size_t *encrypted_len); + +void core_ccmp_256_encrypt(const u8 *tk, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata, + u8 *qos, u8 *pn, int keyid, size_t *encrypted_len); +#endif #endif /* WLANCRYPTO_WRAP_H */ diff --git a/core/mesh/rtw_mesh.c b/core/mesh/rtw_mesh.c index fad46e8..a8a8d9e 100644 --- a/core/mesh/rtw_mesh.c +++ b/core/mesh/rtw_mesh.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -356,12 +356,11 @@ static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter) struct mlme_priv *mlme = &adapter->mlmepriv; _queue *queue = &(mlme->scanned_queue); _list *head, *list; - _irqL irqL; struct wlan_network *scanned = NULL; struct sta_info *sta = NULL; bool need = 0; - _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(mlme->scanned_queue.lock)); head = get_list_head(queue); list = get_next(head); @@ -371,7 +370,7 @@ static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter) if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms && rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned) - && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.PhyInfo.rssi) #if CONFIG_RTW_MACADDR_ACL && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE #endif @@ -388,7 +387,7 @@ static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter) } } - _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(mlme->scanned_queue.lock)); return need; } @@ -468,11 +467,11 @@ struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter) struct sta_priv *stapriv = &adapter->stapriv; struct sta_info *sacrifice = NULL; - enter_critical_bh(&stapriv->asoc_list_lock); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); sacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter); - exit_critical_bh(&stapriv->asoc_list_lock); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); return sacrifice; } @@ -491,7 +490,7 @@ static void rtw_mesh_acnode_rsvd_chk(_adapter *adapter) if (plink_ctl->acnode_rsvd != acnode_rsvd) { plink_ctl->acnode_rsvd = acnode_rsvd; RTW_INFO(FUNC_ADPT_FMT" acnode_rsvd = %d\n", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd); - update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1, 0); + rtw_update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1, 0); } } @@ -659,7 +658,7 @@ static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter) struct blacklist_ent *ent = NULL; struct wlan_network *scanned = NULL; - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); head = &blist->queue; list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { @@ -682,7 +681,7 @@ static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter) } } - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); } #endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ @@ -714,7 +713,7 @@ void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scann goto exit; if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms - || (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi) + || (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.PhyInfo.rssi) || !rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1) #if CONFIG_RTW_MACADDR_ACL || rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE @@ -742,7 +741,7 @@ void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scann , scanned->network.MacAddress , BSS_EX_TLV_IES(&scanned->network) , BSS_EX_TLV_IES_LEN(&scanned->network) - , scanned->network.Rssi + , scanned->network.PhyInfo.rssi , GFP_ATOMIC ); #endif @@ -777,10 +776,10 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) } #endif - enter_critical_bh(&(plink_ctl->lock)); + _rtw_spinlock_bh(&(plink_ctl->lock)); /* check established peers */ - enter_critical_bh(&stapriv->asoc_list_lock); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); head = &stapriv->asoc_list; list = get_next(head); @@ -808,7 +807,7 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network)); forwarding = rtw_bss_is_forwarding(&(plink->scanned->network)); - mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr); + mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->phl_sta->mac_addr); /* CTO_MGATE required, remove peer without CTO_MGATE */ if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) { @@ -821,12 +820,12 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) if (cto_mgate && !forwarding && !mgate) SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms); else - rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->phl_sta->mac_addr); } else { /* cto_mgate_conf ongoing */ if (cto_mgate && !forwarding && !mgate) { if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) { - rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr); + rtw_mesh_cto_mgate_blacklist_add(adapter, sta->phl_sta->mac_addr); /* CTO_MGATE required, remove peering can't achieve CTO_MGATE */ if (rtw_mesh_cto_mgate_required(adapter)) { @@ -836,7 +835,7 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) } } else { SET_CTO_MGATE_CONF_DISABLED(plink); - rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->phl_sta->mac_addr); } } #endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ @@ -859,7 +858,7 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) } } - exit_critical_bh(&stapriv->asoc_list_lock); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); /* check non-established peers */ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { @@ -886,7 +885,7 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) #endif } - exit_critical_bh(&(plink_ctl->lock)); + _rtw_spinunlock_bh(&(plink_ctl->lock)); if (flush_num) { u8 sta_addr[ETH_ALEN]; @@ -894,9 +893,9 @@ void rtw_mesh_peer_status_chk(_adapter *adapter) for (i = 0; i < flush_num; i++) { sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]); - _rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(sta_addr, sta->phl_sta->mac_addr, ETH_ALEN); - updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE, _FALSE); rtw_mesh_expire_peer(adapter, sta_addr); } @@ -929,7 +928,7 @@ static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter) if (!rtw_mesh_cto_mgate_required(adapter)) goto exit; - enter_critical_bh(&(mlme->scanned_queue.lock)); + _rtw_spinlock_bh(&(mlme->scanned_queue.lock)); head = get_list_head(queue); pos = get_next(head); @@ -937,7 +936,7 @@ static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter) scanned = LIST_CONTAINOR(pos, struct wlan_network, list); if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms - && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.PhyInfo.rssi) #if CONFIG_RTW_MACADDR_ACL && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE #endif @@ -956,7 +955,7 @@ static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter) if (rtw_end_of_queue_search(head, pos)) ret = 1; - exit_critical_bh(&(mlme->scanned_queue.lock)); + _rtw_spinunlock_bh(&(mlme->scanned_queue.lock)); exit: return ret; @@ -1003,7 +1002,6 @@ u8 rtw_mesh_select_operating_ch(_adapter *adapter) struct mlme_priv *mlme = &adapter->mlmepriv; _queue *queue = &(mlme->scanned_queue); _list *head, *pos; - _irqL irqL; struct wlan_network *scanned = NULL; int i; /* statistics for candidate accept peering */ @@ -1015,7 +1013,7 @@ u8 rtw_mesh_select_operating_ch(_adapter *adapter) u8 max_cand_ch = 0; u8 max_cand_cnt = 0; - _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(mlme->scanned_queue.lock)); head = get_list_head(queue); pos = get_next(head); @@ -1024,7 +1022,7 @@ u8 rtw_mesh_select_operating_ch(_adapter *adapter) pos = get_next(pos); if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms - && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.PhyInfo.rssi) #if CONFIG_RTW_MACADDR_ACL && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE #endif @@ -1061,7 +1059,7 @@ u8 rtw_mesh_select_operating_ch(_adapter *adapter) } } - _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(mlme->scanned_queue.lock)); return max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch; } @@ -1127,7 +1125,7 @@ void dump_mesh_networks(void *sel, _adapter *adapter) if (!mesh_networks) return; - enter_critical_bh(&queue->lock); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); @@ -1146,7 +1144,7 @@ void dump_mesh_networks(void *sel, _adapter *adapter) mesh_networks[mesh_network_cnt++] = network; } - exit_critical_bh(&queue->lock); + _rtw_spinunlock_bh(&queue->lock); RTW_PRINT_SEL(sel, " %-17s %-3s %-4s %-5s %-32s %-10s" " %-3s %-3s %-4s" @@ -1250,7 +1248,7 @@ void dump_mesh_networks(void *sel, _adapter *adapter) , established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' ')))) , MAC_ARG(network->network.MacAddress) , network->network.Configuration.DSConfig - , network->network.Rssi + , network->network.PhyInfo.rssi , age_ms < 99999 ? age_ms : 99999 , network->network.mesh_id.Ssid , GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(mesh_conf_ie + 2) @@ -1278,7 +1276,7 @@ void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset) /* prevent secondary channel offset mismatch */ if (*req_bw > CHANNEL_WIDTH_20) { *req_bw = CHANNEL_WIDTH_20; - *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *req_offset = CHAN_OFFSET_NO_EXT; } } } @@ -1756,11 +1754,10 @@ static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, si if (sac) { struct sta_priv *stapriv = &adapter->stapriv; - _irqL irqL; u8 sta_addr[ETH_ALEN]; u8 updated = _FALSE; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); if (!rtw_is_list_empty(&sac->asoc_list)) { rtw_list_delete(&sac->asoc_list); stapriv->asoc_list_cnt--; @@ -1770,12 +1767,12 @@ static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, si #endif STA_SET_MESH_PLINK(sac, NULL); } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sac->phl_sta->mac_addr)); - _rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN); - updated = ap_free_sta(adapter, sac, 0, 0, 1); + _rtw_memcpy(sta_addr, sac->phl_sta->mac_addr, ETH_ALEN); + updated = ap_free_sta(adapter, sac, 0, 0, 1, 0); rtw_mesh_expire_peer(stapriv->padapter, sta_addr); associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); @@ -1785,11 +1782,10 @@ static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, si } else #endif if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) { - _irqL irqL; u8 *ies = NULL; u16 ies_len = 0; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); plink = _rtw_mesh_plink_get(adapter, peer_addr); if (!plink) @@ -1846,7 +1842,7 @@ static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, si } release_plink_ctl: - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); } mpm_log: @@ -2143,11 +2139,10 @@ struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr) struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent = NULL; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); ent = _rtw_mesh_plink_get(adapter, hwaddr); - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ent; } @@ -2158,9 +2153,8 @@ struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent = NULL; int i, j = 0; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { if (plink_ctl->ent[i].valid == _TRUE && plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB @@ -2172,7 +2166,7 @@ struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 j++; } } - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ent; } @@ -2229,12 +2223,11 @@ int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr) { struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; - _irqL irqL; int ret; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); ret = _rtw_mesh_plink_add(adapter, hwaddr); - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ret; } @@ -2244,13 +2237,12 @@ int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state) struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent = NULL; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); ent = _rtw_mesh_plink_get(adapter, hwaddr); if (ent) ent->plink_state = state; - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ent ? _SUCCESS : _FAIL; } @@ -2261,15 +2253,14 @@ int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek) struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent = NULL; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); ent = _rtw_mesh_plink_get(adapter, hwaddr); if (ent) { _rtw_memcpy(ent->aek, aek, 32); ent->aek_valid = 1; } - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ent ? _SUCCESS : _FAIL; } @@ -2282,15 +2273,14 @@ int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr) struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent = NULL; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); ent = _rtw_mesh_plink_get(adapter, hwaddr); if (ent) { if (IS_PEER_CONF_DISABLED(ent)) SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms); } - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return ent ? _SUCCESS : _FAIL; } @@ -2324,9 +2314,8 @@ int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr) struct mesh_plink_ent *ent = NULL; u8 exist = _FALSE; int i; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { if (plink_ctl->ent[i].valid == _TRUE && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE @@ -2340,7 +2329,7 @@ int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr) if (exist == _TRUE) _rtw_mesh_plink_del_ent(adapter, ent); - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); return exist == _TRUE ? _SUCCESS : RTW_ALREADY; } @@ -2370,9 +2359,8 @@ void rtw_mesh_plink_ctl_deinit(_adapter *adapter) struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *ent; int i; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { ent = &plink_ctl->ent[i]; #ifdef CONFIG_RTW_MESH_DRIVER_AID @@ -2382,7 +2370,7 @@ void rtw_mesh_plink_ctl_deinit(_adapter *adapter) if (ent->rx_conf_ies && ent->rx_conf_ies_len) rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len); } - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); _rtw_spinlock_free(&plink_ctl->lock); @@ -2477,7 +2465,6 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli u8 *tlv_ies; u16 tlv_ieslen; struct rtw_ieee802_11_elems elems; - _irqL irqL; int i; u16 status = 0; int ret = _FAIL; @@ -2487,26 +2474,26 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) { RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); goto exit; } if (plink->rx_conf_ies_len < 4) { RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); goto exit; } #ifdef CONFIG_RTW_MESH_DRIVER_AID if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) { RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); goto exit; } if (plink->tx_conf_ies_len < 4) { RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); goto exit; } #endif @@ -2519,7 +2506,7 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) { RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); goto exit; } @@ -2564,13 +2551,13 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli /* AID */ #ifdef CONFIG_RTW_MESH_DRIVER_AID - sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2); + sta->phl_sta->aid = RTW_GET_LE16(plink->tx_conf_ies + 2); #else - sta->cmn.aid = plink->aid; + sta->phl_sta->aid = plink->aid; #endif - stapriv->sta_aid[sta->cmn.aid - 1] = sta; + stapriv->sta_aid[sta->phl_sta->aid - 1] = sta; RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr), sta->phl_sta->aid); sta->state &= (~WIFI_FW_ASSOC_STATE); sta->state |= WIFI_FW_ASSOC_SUCCESS; @@ -2583,7 +2570,7 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli sta->metrics.data_rate = 10; sta->alive = _TRUE; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); if (rtw_is_list_empty(&sta->asoc_list)) { STA_SET_MESH_PLINK(sta, plink); /* TBD: up layer timeout mechanism */ @@ -2597,11 +2584,11 @@ static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *pli } #endif } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); bss_cap_update_on_sta_join(adapter, sta); sta_info_update(adapter, sta); - report_add_sta_event(adapter, sta->cmn.mac_addr); + report_add_sta_event(adapter, sta->phl_sta->mac_addr); ret = _SUCCESS; @@ -2621,7 +2608,7 @@ int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state) struct sta_info *del_sta = NULL; int ret = _SUCCESS; - _enter_critical_bh(&(plink_ctl->lock), &irqL2); + _rtw_spinlock_bh(&(plink_ctl->lock), &irqL2); plink = _rtw_mesh_plink_get(adapter, mac); if (!plink) { @@ -2640,7 +2627,7 @@ int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state) if (sac) { del_sta = sac; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock, &irqL); if (!rtw_is_list_empty(&del_sta->asoc_list)) { rtw_list_delete(&del_sta->asoc_list); stapriv->asoc_list_cnt--; @@ -2650,9 +2637,9 @@ int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state) #endif STA_SET_MESH_PLINK(del_sta, NULL); } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock, &irqL); RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->phl_sta->mac_addr)); } } } else @@ -2681,7 +2668,7 @@ int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state) if (!del_sta) goto release_plink_ctl; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock, &irqL); if (!rtw_is_list_empty(&del_sta->asoc_list)) { rtw_list_delete(&del_sta->asoc_list); stapriv->asoc_list_cnt--; @@ -2691,18 +2678,18 @@ int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state) #endif STA_SET_MESH_PLINK(del_sta, NULL); } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock, &irqL); } release_plink_ctl: - _exit_critical_bh(&(plink_ctl->lock), &irqL2); + _rtw_spinunlock_bh(&(plink_ctl->lock), &irqL2); if (del_sta) { u8 sta_addr[ETH_ALEN]; u8 updated = _FALSE; - _rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN); - updated = ap_free_sta(adapter, del_sta, 0, 0, 1); + _rtw_memcpy(sta_addr, del_sta->phl_sta->mac_addr, ETH_ALEN); + updated = ap_free_sta(adapter, del_sta, 0, 0, 1, 0); rtw_mesh_expire_peer(stapriv->padapter, sta_addr); associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); @@ -2730,7 +2717,7 @@ u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state { struct cmd_obj *cmdobj; struct mesh_set_plink_cmd_parm *parm; - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -2750,6 +2737,7 @@ u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state rtw_mfree(parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_MESH_PLINK_STATE); cmdobj->sctx = &sctx; @@ -2758,10 +2746,10 @@ u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state res = rtw_enqueue_cmd(cmdpriv, cmdobj); if (res == _SUCCESS) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&cmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&cmdpriv->sctx_mutex, NULL); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&cmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&cmdpriv->sctx_mutex, NULL); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -2875,7 +2863,7 @@ void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink) if (frame) { struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; struct wireless_dev *wdev = adapter->rtw_wdev; - s32 freq = rtw_ch2freq(mlmeext->cur_channel); + s32 freq = rtw_ch2freq(mlmeext->chandef.chan); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC); @@ -2898,9 +2886,8 @@ void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr) struct rtw_mesh_info *minfo = &adapter->mesh_info; struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; struct mesh_plink_ent *plink; - _irqL irqL; - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); plink = _rtw_mesh_plink_get(adapter, peer_addr); if (!plink) @@ -2909,12 +2896,11 @@ void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr) _rtw_mesh_expire_peer_ent(adapter, plink); exit: - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); } u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) { - _irqL irqL; _list *head, *list; struct sta_info *sta; struct sta_priv *stapriv = &adapter->stapriv; @@ -2925,7 +2911,7 @@ u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) if (rtw_linked_check(adapter) == _FALSE) goto exit; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); head = &stapriv->asoc_list; list = get_next(head); @@ -2939,14 +2925,14 @@ u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) if (stainfo_offset_valid(stainfo_offset)) sta_alive_list[sta_alive_num++] = stainfo_offset; } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); for (i = 0; i < sta_alive_num; i++) { sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]); if (!sta) continue; - issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500); + issue_qos_nulldata(adapter, sta->phl_sta->mac_addr, 7, ps, 3, 500, _FALSE); annc_cnt++; } @@ -2954,9 +2940,9 @@ u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) return annc_cnt; } -static void mpath_tx_tasklet_hdl(unsigned long data) +static void mpath_tx_tasklet_hdl(void *priv) { - _adapter *adapter = (_adapter *)data; + _adapter *adapter = (_adapter *)priv; struct rtw_mesh_info *minfo = &adapter->mesh_info; struct xmit_frame *xframe; _list *list, *head; @@ -2968,13 +2954,13 @@ static void mpath_tx_tasklet_hdl(unsigned long data) while (1) { tmp_len = 0; - enter_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinlock_bh(&minfo->mpath_tx_queue.lock); if (minfo->mpath_tx_queue_len) { rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); tmp_len = minfo->mpath_tx_queue_len; minfo->mpath_tx_queue_len = 0; } - exit_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinunlock_bh(&minfo->mpath_tx_queue.lock); if (!tmp_len) break; @@ -3005,10 +2991,10 @@ static void rtw_mpath_tx_queue_flush(_adapter *adapter) _rtw_init_listhead(&tmp); - enter_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinlock_bh(&minfo->mpath_tx_queue.lock); rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); minfo->mpath_tx_queue_len = 0; - exit_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinunlock_bh(&minfo->mpath_tx_queue.lock); head = &tmp; list = get_next(head); @@ -3307,7 +3293,6 @@ void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg) void rtw_mesh_cfg_init(_adapter *adapter) { - struct registry_priv *regsty = adapter_to_regsty(adapter); struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS; @@ -3338,8 +3323,8 @@ void rtw_mesh_cfg_init(_adapter *adapter) #endif #if CONFIG_RTW_MESH_DATA_BMC_TO_UC - mcfg->b2u_flags_msrc = regsty->msrc_b2u_flags; - mcfg->b2u_flags_mfwd = regsty->mfwd_b2u_flags; + mcfg->b2u_flags_msrc = 0; + mcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST; #endif } @@ -3376,17 +3361,18 @@ void rtw_mesh_init_mesh_info(_adapter *adapter) rtw_mesh_pathtbl_init(adapter); _rtw_init_queue(&minfo->mpath_tx_queue); - tasklet_init(&minfo->mpath_tx_tasklet, - mpath_tx_tasklet_hdl, - (unsigned long)adapter); + tasklet_init(&minfo->mpath_tx_tasklet + , (void(*)(unsigned long))mpath_tx_tasklet_hdl + , (unsigned long)adapter); + rtw_mrc_init(adapter); _rtw_init_listhead(&minfo->preq_queue.list); _rtw_spinlock_init(&minfo->mesh_preq_queue_lock); - rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter); - rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter); - rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter); + rtw_init_timer(&adapter->mesh_path_timer, rtw_ieee80211_mesh_path_timer, adapter); + rtw_init_timer(&adapter->mesh_path_root_timer, rtw_ieee80211_mesh_path_root_timer, adapter); + rtw_init_timer(&adapter->mesh_atlm_param_req_timer, rtw_mesh_atlm_param_req_timer, adapter); _init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL); } @@ -3453,7 +3439,7 @@ int rtw_mesh_nexthop_resolve(_adapter *adapter, if (!(mpath->flags & RTW_MESH_PATH_RESOLVING)) rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START); - enter_critical_bh(&mpath->frame_queue.lock); + _rtw_spinlock_bh(&mpath->frame_queue.lock); if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) { xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list); @@ -3464,7 +3450,7 @@ int rtw_mesh_nexthop_resolve(_adapter *adapter, rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue)); mpath->frame_queue_len++; - exit_critical_bh(&mpath->frame_queue.lock); + _rtw_spinunlock_bh(&mpath->frame_queue.lock); ret = RTW_RA_RESOLVING; if (xframe_to_free) @@ -3504,7 +3490,7 @@ int rtw_mesh_nexthop_lookup(_adapter *adapter, next_hop = rtw_rcu_dereference(mpath->next_hop); if (next_hop) { - _rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(ra, next_hop->phl_sta->mac_addr, ETH_ALEN); err = 0; } @@ -3532,9 +3518,9 @@ int rtw_mesh_nexthop_lookup(_adapter *adapter, !(mpath->flags & RTW_MESH_PATH_FIXED) && !(mpath->flags & RTW_MESH_PATH_BCAST_PREQ) && mpath->is_root && nexthop_alive == _FALSE) { - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mpath->flags |= RTW_MESH_PATH_BCAST_PREQ; - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); } endlookup: @@ -3550,7 +3536,6 @@ static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter { struct sta_priv *stapriv = &adapter->stapriv; struct xmit_priv *xmitpriv = &adapter->xmitpriv; - _irqL irqL; _list *head, *list; struct sta_info *sta; char b2u_sta_id[NUM_STA]; @@ -3558,7 +3543,7 @@ static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter bool bmc_need = _FALSE; int i; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); head = &stapriv->asoc_list; list = get_next(head); @@ -3572,7 +3557,7 @@ static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter if (stainfo_offset_valid(stainfo_offset)) b2u_sta_id[b2u_sta_num++] = stainfo_offset; } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); if (!b2u_sta_num) goto exit; @@ -3583,10 +3568,10 @@ static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]); if (!(sta->state & WIFI_ASOC_STATE) - || _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE - || (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE) - || is_broadcast_mac_addr(sta->cmn.mac_addr) - || is_zero_mac_addr(sta->cmn.mac_addr)) + || _rtw_memcmp(sta->phl_sta->mac_addr, msa, ETH_ALEN) == _TRUE + || (ori_ta && _rtw_memcmp(sta->phl_sta->mac_addr, ori_ta, ETH_ALEN) == _TRUE) + || is_broadcast_mac_addr(sta->phl_sta->mac_addr) + || is_zero_mac_addr(sta->phl_sta->mac_addr)) continue; b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid); @@ -3605,7 +3590,7 @@ static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter attrib->mb2u = 1; attrib->mseq = *b2u_mseq; attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0; - _rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(attrib->ra, sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); _rtw_memcpy(attrib->mda, mda, ETH_ALEN); _rtw_memcpy(attrib->msa, msa, ETH_ALEN); @@ -3693,7 +3678,7 @@ int rtw_mesh_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xfra , etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0 , os_qid, b2u_list, &b2u_num, &b2u_mseq); if (bmc_need == _FALSE) { - res = RTW_BMC_NO_NEED; + res = RTW_ORI_NO_NEED; goto exit; } } @@ -3868,7 +3853,7 @@ int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, s goto exit; switch (rattrib->to_fr_ds) { - case 2: + case 1: if (!IS_MCAST(GetAddr1Ptr(whdr))) goto exit; *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); @@ -3956,7 +3941,7 @@ int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe ae = mctrl->flags & MESH_FLAGS_AE; mlen = ae_to_mesh_ctrl_len[ae]; switch (rattrib->to_fr_ds) { - case 2: + case 1: *da = mda; if (ae == MESH_FLAGS_AE_A4) *sa = mctrl->eaddr1; @@ -4085,7 +4070,7 @@ int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe int act = 0; u8 ae_need; #if CONFIG_RTW_MESH_DATA_BMC_TO_UC - bool bmc_need = _TRUE; + bool ori_need = _TRUE; u8 b2u_num = 0; #endif @@ -4109,11 +4094,11 @@ int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe if (!mppath) rtw_mpp_path_add(adapter, proxied_addr, mpp_addr); else { - enter_critical_bh(&mppath->state_lock); + _rtw_spinlock_bh(&mppath->state_lock); if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE) _rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN); mppath->exp_time = rtw_get_current_time(); - exit_critical_bh(&mppath->state_lock); + _rtw_spinunlock_bh(&mppath->state_lock); } rtw_rcu_read_unlock(); } @@ -4317,12 +4302,12 @@ int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe if (is_mda_bmc && rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3) ) { - bmc_need = rtw_mesh_data_bmc_to_uc(adapter - , da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1 + ori_need = rtw_mesh_data_bmc_to_uc(adapter + , da, sa, mda, msa, ae_need, rframe->u.hdr.psta->phl_sta->mac_addr, mctrl->ttl - 1 , os_qid, b2u_list, &b2u_num, &fwd_mseq); } - if (bmc_need == _TRUE) + if (ori_need == _TRUE) #endif { xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid); @@ -4361,12 +4346,17 @@ int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe *fwd_frame = xframe; } - act |= RTW_RX_MSDU_ACT_FORWARD; - if (is_mda_bmc) - minfo->mshstats.fwded_mcast++; - else - minfo->mshstats.fwded_unicast++; - minfo->mshstats.fwded_frames++; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (ori_need || b2u_num) +#endif + { + act |= RTW_RX_MSDU_ACT_FORWARD; + if (is_mda_bmc) + minfo->mshstats.fwded_mcast++; + else + minfo->mshstats.fwded_unicast++; + minfo->mshstats.fwded_frames++; + } exit: return act; diff --git a/core/mesh/rtw_mesh.h b/core/mesh/rtw_mesh.h index 5410ba4..f91770c 100644 --- a/core/mesh/rtw_mesh.h +++ b/core/mesh/rtw_mesh.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/core/mesh/rtw_mesh_hwmp.c b/core/mesh/rtw_mesh_hwmp.c index 04be425..22d19af 100644 --- a/core/mesh/rtw_mesh_hwmp.c +++ b/core/mesh/rtw_mesh_hwmp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,7 +16,6 @@ #ifdef CONFIG_RTW_MESH #include -#include #define RTW_TEST_FRAME_LEN 8192 #define RTW_MAX_METRIC 0xffffffff @@ -273,7 +272,9 @@ static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 *pos++ = WLAN_EID_RANN; break; default: + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); return _FAIL; } @@ -394,10 +395,165 @@ int rtw_mesh_path_error_tx(_adapter *adapter, return 0; } +static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi) +{ + static const u32 base[4][10] = { + { 6500000, + 13000000, + 19500000, + 26000000, + 39000000, + 52000000, + 58500000, + 65000000, + 78000000, + /* not in the spec, but some devices use this: */ + 86500000, + }, + { 13500000, + 27000000, + 40500000, + 54000000, + 81000000, + 108000000, + 121500000, + 135000000, + 162000000, + 180000000, + }, + { 29300000, + 58500000, + 87800000, + 117000000, + 175500000, + 234000000, + 263300000, + 292500000, + 351000000, + 390000000, + }, + { 58500000, + 117000000, + 175500000, + 234000000, + 351000000, + 468000000, + 526500000, + 585000000, + 702000000, + 780000000, + }, + }; + u32 bitrate; + int bw_idx; + + if (mcs > 9) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (nss > 4 || nss < 1) { + RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n"); + } + + switch (bw) { + case CHANNEL_WIDTH_160: + bw_idx = 3; + break; + case CHANNEL_WIDTH_80: + bw_idx = 2; + break; + case CHANNEL_WIDTH_40: + bw_idx = 1; + break; + case CHANNEL_WIDTH_20: + bw_idx = 0; + break; + default: + RTW_HWMP_INFO("bw = %d currently not supported\n", bw); + return 0; + } + + bitrate = base[bw_idx][mcs]; + bitrate *= nss; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi) +{ + int modulation, streams, bitrate; + + /* the formula below does only work for MCS values smaller than 32 */ + if (mcs >= 32) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (bw > 1) { + RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n"); + return 0; + } + + modulation = mcs & 7; + streams = (mcs >> 3) + 1; + + bitrate = (bw == 1) ? 13500000 : 6500000; + + if (modulation < 4) + bitrate *= (modulation + 1); + else if (modulation == 4) + bitrate *= (modulation + 2); + else + bitrate *= (modulation + 3); + + bitrate *= streams; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +/** + * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz) + * @rate_idx: DESC_RATEXXXX & 0x7f + * @sgi: DESC_RATEXXXX >> 7 + * Returns: bitrate in 100kbps + */ +static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi) +{ + u32 bitrate; + + if (rate_idx <= DESC_RATE54M){ + u16 ofdm_rate[12] = {10, 20, 55, 110, + 60, 90, 120, 180, 240, 360, 480, 540}; + bitrate = ofdm_rate[rate_idx]; + } else if ((DESC_RATEMCS0 <= rate_idx) && + (rate_idx <= DESC_RATEMCS31)) { + u8 mcs = rate_idx - DESC_RATEMCS0; + bitrate = rtw_get_ht_bitrate(mcs, bw, sgi); + } else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) && + (rate_idx <= DESC_RATEVHTSS4MCS9)) { + u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10; + u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1; + bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi); + } else { + /* 60Ghz ??? */ + bitrate = 1; + } + + return bitrate; +} + static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta) { - struct dm_struct *dm = adapter_to_phydm(adapter); - int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT; + int device_constant = rtw_hal_phydm_get_plcp(adapter, sta->phl_sta->macid) << RTW_ARITH_SHIFT; u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT; u32 s_unit = 1 << RTW_ARITH_SHIFT; u32 err; @@ -501,9 +657,9 @@ static void rtw_hwmp_preq_frame_process(_adapter *adapter, if (preq_is_gate) rtw_mesh_path_add_gate(path); else if (path->is_gate) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } } path = NULL; @@ -539,9 +695,9 @@ static void rtw_hwmp_preq_frame_process(_adapter *adapter, path->gate_asked = false; rtw_mesh_path_add_gate(path); } else if (path->is_gate) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } } rtw_rcu_read_unlock(); @@ -553,9 +709,9 @@ static void rtw_hwmp_preq_frame_process(_adapter *adapter, if (preq_is_gate) rtw_mesh_path_add_gate(path); else if (path->is_gate) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } } path = NULL; @@ -672,13 +828,13 @@ static void rtw_hwmp_prep_frame_process(_adapter *adapter, if (path && path->gate_asked) { flags = RTW_PREP_IE_FLAGS(prep_elem); if (flags & BIT(7)) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); path->gate_asked = false; - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); if (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } } } @@ -699,15 +855,15 @@ static void rtw_hwmp_prep_frame_process(_adapter *adapter, rtw_rcu_read_lock(); path = rtw_mesh_path_lookup(adapter, originator_addr); if (path) - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); else goto fail; if (!(path->flags & RTW_MESH_PATH_ACTIVE)) { - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); goto fail; } - _rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN); - exit_critical_bh(&path->state_lock); + _rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->phl_sta->mac_addr, ETH_ALEN); + _rtw_spinunlock_bh(&path->state_lock); --ttl; flags = RTW_PREP_IE_FLAGS(prep_elem); lifetime = RTW_PREP_IE_LIFETIME(prep_elem); @@ -760,10 +916,10 @@ static void rtw_hwmp_perr_frame_process(_adapter *adapter, if (path) { struct sta_info *sta; - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); sta = rtw_next_hop_deref_protected(path); if (path->flags & RTW_MESH_PATH_ACTIVE && - rtw_ether_addr_equal(ta, sta->cmn.mac_addr) && + rtw_ether_addr_equal(ta, sta->phl_sta->mac_addr) && !(path->flags & RTW_MESH_PATH_FIXED) && (!(path->flags & RTW_MESH_PATH_SN_VALID) || RTW_SN_GT(target_sn, path->sn) || target_sn == 0)) { @@ -772,14 +928,14 @@ static void rtw_hwmp_perr_frame_process(_adapter *adapter, path->sn = target_sn; else path->sn += 1; - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); if (!mshcfg->dot11MeshForwarding) goto endperr; rtw_mesh_path_error_tx(adapter, ttl, target_addr, target_sn, perr_reason_code, bcast_addr); } else - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } endperr: rtw_rcu_read_unlock(); @@ -881,9 +1037,9 @@ static void rtw_hwmp_rann_frame_process(_adapter *adapter, path->gate_asked = false; rtw_mesh_path_add_gate(path); } else if (path->is_gate) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } if (ttl <= 1) { @@ -957,7 +1113,7 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, } else { path = rtw_mesh_path_lookup(adapter, originator_addr); if (path) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); if (path->flags & RTW_MESH_PATH_FIXED) fresh_info = _FALSE; else if ((path->flags & RTW_MESH_PATH_ACTIVE) && @@ -990,7 +1146,7 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, rtw_rcu_read_unlock(); return 0; } - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); } if (fresh_info) { @@ -1008,10 +1164,10 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, path->rann_metric = new_metric; } #endif - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); rtw_mesh_path_tx_pending(path); } else - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } /* Update and check transmitter routing info */ @@ -1023,7 +1179,7 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, path = rtw_mesh_path_lookup(adapter, ta); if (path) { - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); if ((path->flags & RTW_MESH_PATH_FIXED) || ((path->flags & RTW_MESH_PATH_ACTIVE) && (last_hop_metric > path->metric))) @@ -1034,7 +1190,7 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, rtw_rcu_read_unlock(); return 0; } - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); } if (fresh_info) { @@ -1043,10 +1199,10 @@ static u32 rtw_hwmp_route_info_get(_adapter *adapter, path->exp_time = rtw_time_after(path->exp_time, exp_time) ? path->exp_time : exp_time; rtw_mesh_path_activate(path); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); rtw_mesh_path_tx_pending(path); } else - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } rtw_rcu_read_unlock(); @@ -1136,9 +1292,9 @@ void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags) return; } - enter_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinlock_bh(&minfo->mesh_preq_queue_lock); if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) { - exit_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinunlock_bh(&minfo->mesh_preq_queue_lock); rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); if (rtw_print_ratelimit()) RTW_HWMP_INFO("PREQ node queue full\n"); @@ -1148,7 +1304,7 @@ void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags) _rtw_spinlock(&path->state_lock); if (path->flags & RTW_MESH_PATH_REQ_QUEUED) { _rtw_spinunlock(&path->state_lock); - exit_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinunlock_bh(&minfo->mesh_preq_queue_lock); rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); return; } @@ -1169,7 +1325,7 @@ void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags) rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list); ++minfo->preq_queue_len; - exit_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinunlock_bh(&minfo->mesh_preq_queue_lock); if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter))) rtw_mesh_work(&adapter->mesh_work); @@ -1219,11 +1375,11 @@ void rtw_mesh_path_start_discovery(_adapter *adapter) BOOLEAN is_root_add_chk = _FALSE; BOOLEAN da_is_peer, force_preq_bcast; - enter_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinlock_bh(&minfo->mesh_preq_queue_lock); if (!minfo->preq_queue_len || rtw_time_before(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter))) { - exit_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinunlock_bh(&minfo->mesh_preq_queue_lock); return; } @@ -1231,22 +1387,22 @@ void rtw_mesh_path_start_discovery(_adapter *adapter) struct rtw_mesh_preq_queue, list); rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */ --minfo->preq_queue_len; - exit_critical_bh(&minfo->mesh_preq_queue_lock); + _rtw_spinunlock_bh(&minfo->mesh_preq_queue_lock); rtw_rcu_read_lock(); path = rtw_mesh_path_lookup(adapter, preq_node->dst); if (!path) goto enddiscovery; - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) { - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); goto enddiscovery; } path->flags &= ~RTW_MESH_PATH_REQ_QUEUED; if (preq_node->flags & RTW_PREQ_Q_F_START) { if (path->flags & RTW_MESH_PATH_RESOLVING) { - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); goto enddiscovery; } else { path->flags &= ~RTW_MESH_PATH_RESOLVED; @@ -1257,7 +1413,7 @@ void rtw_mesh_path_start_discovery(_adapter *adapter) } else if (!(path->flags & RTW_MESH_PATH_RESOLVING) || path->flags & RTW_MESH_PATH_RESOLVED) { path->flags &= ~RTW_MESH_PATH_RESOLVING; - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); goto enddiscovery; } @@ -1273,7 +1429,7 @@ void rtw_mesh_path_start_discovery(_adapter *adapter) ttl = mshcfg->element_ttl; if (ttl == 0) { minfo->mshstats.dropped_frames_ttl++; - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); goto enddiscovery; } @@ -1287,7 +1443,7 @@ void rtw_mesh_path_start_discovery(_adapter *adapter) #endif da_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA); force_preq_bcast = !!(path->flags & RTW_MESH_PATH_BCAST_PREQ); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); da = rtw_hwmp_preq_da(path, is_root_add_chk, da_is_peer, force_preq_bcast); @@ -1320,7 +1476,7 @@ void rtw_mesh_path_timer(void *ctx) if (suspending) return; #endif - enter_critical_bh(&path->state_lock); + _rtw_spinlock_bh(&path->state_lock); if (path->flags & RTW_MESH_PATH_RESOLVED || (!(path->flags & RTW_MESH_PATH_RESOLVING))) { path->flags &= ~(RTW_MESH_PATH_RESOLVING | @@ -1328,7 +1484,7 @@ void rtw_mesh_path_timer(void *ctx) RTW_MESH_PATH_ROOT_ADD_CHK | RTW_MESH_PATH_PEER_AKA | RTW_MESH_PATH_BCAST_PREQ); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); } else if (path->discovery_retries < rtw_max_preq_retries(adapter)) { ++path->discovery_retries; path->discovery_timeout *= 2; @@ -1340,7 +1496,7 @@ void rtw_mesh_path_timer(void *ctx) if (path->gate_asked) retry |= RTW_PREQ_Q_F_REFRESH; - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); rtw_mesh_queue_preq(path, retry); } else { path->flags &= ~(RTW_MESH_PATH_RESOLVING | @@ -1350,7 +1506,7 @@ void rtw_mesh_path_timer(void *ctx) RTW_MESH_PATH_PEER_AKA | RTW_MESH_PATH_BCAST_PREQ); path->exp_time = rtw_get_current_time(); - exit_critical_bh(&path->state_lock); + _rtw_spinunlock_bh(&path->state_lock); if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) { ret = rtw_mesh_path_send_to_gates(path); if (ret) @@ -1489,9 +1645,9 @@ static void rtw_update_metric_directly(_adapter *adapter) if (!sta) continue; - rate_idx = rtw_get_current_tx_rate(adapter, sta); + rate_idx = rtw_hal_get_current_tx_rate(adapter, sta); sgi = rtw_get_current_tx_sgi(adapter, sta); - bw = sta->cmn.bw_mode; + bw = sta->phl_sta->chandef.bw; rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi); sta->metrics.data_rate = rate; } diff --git a/core/mesh/rtw_mesh_hwmp.h b/core/mesh/rtw_mesh_hwmp.h index 9433417..466570e 100644 --- a/core/mesh/rtw_mesh_hwmp.h +++ b/core/mesh/rtw_mesh_hwmp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/core/mesh/rtw_mesh_pathtbl.c b/core/mesh/rtw_mesh_pathtbl.c index b74b567..97840a6 100644 --- a/core/mesh/rtw_mesh_pathtbl.c +++ b/core/mesh/rtw_mesh_pathtbl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -111,16 +111,16 @@ void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info * rtw_rcu_assign_pointer(mpath->next_hop, sta); - enter_critical_bh(&mpath->frame_queue.lock); + _rtw_spinlock_bh(&mpath->frame_queue.lock); head = &mpath->frame_queue.queue; list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { xframe = LIST_CONTAINOR(list, struct xmit_frame, list); list = get_next(list); - _rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(xframe->attrib.ra, sta->phl_sta->mac_addr, ETH_ALEN); } - exit_critical_bh(&mpath->frame_queue.lock); + _rtw_spinunlock_bh(&mpath->frame_queue.lock); } static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr, @@ -134,7 +134,7 @@ static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr, /* update next hop */ rtw_rcu_read_lock(); - next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr; + next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->phl_sta->mac_addr; _rtw_memcpy(attrib->ra, next_hop, ETH_ALEN); rtw_rcu_read_unlock(); _rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN); @@ -166,7 +166,6 @@ static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, _list *list, *head; _list failq; u32 failq_len; - _irqL flags; if (rtw_warn_on(gate_mpath == from_mpath)) return; @@ -175,11 +174,11 @@ static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, _rtw_init_listhead(&failq); - _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + _rtw_spinlock_bh(&from_mpath->frame_queue.lock); rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq); failq_len = from_mpath->frame_queue_len; from_mpath->frame_queue_len = 0; - _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); + _rtw_spinunlock_bh(&from_mpath->frame_queue.lock); head = &failq; list = get_next(head); @@ -196,10 +195,10 @@ static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, rtw_list_delete(&fskb->list); failq_len--; rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath); - _enter_critical_bh(&gate_mpath->frame_queue.lock, &flags); + _rtw_spinlock_bh(&gate_mpath->frame_queue.lock); rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue)); gate_mpath->frame_queue_len++; - _exit_critical_bh(&gate_mpath->frame_queue.lock, &flags); + _rtw_spinunlock_bh(&gate_mpath->frame_queue.lock); #if 0 /* TODO: copy */ skb = rtw_skb_copy(fskb); @@ -223,10 +222,10 @@ static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, if (!copy) return; - _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + _rtw_spinlock_bh(&from_mpath->frame_queue.lock); rtw_list_splice(&failq, &from_mpath->frame_queue.queue); from_mpath->frame_queue_len += failq_len; - _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); + _rtw_spinunlock_bh(&from_mpath->frame_queue.lock); } @@ -240,9 +239,9 @@ static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params); if (mpath && rtw_mpath_expired(mpath)) { - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mpath->flags &= ~RTW_MESH_PATH_ACTIVE; - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); } return mpath; } @@ -302,9 +301,9 @@ __rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx) return NULL; if (rtw_mpath_expired(mpath)) { - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mpath->flags &= ~RTW_MESH_PATH_ACTIVE; - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); } return mpath; } @@ -345,7 +344,7 @@ void dump_mpath(void *sel, _adapter *adapter) mpath = rtw_mesh_path_lookup_by_idx(adapter, idx); if (mpath) { _rtw_memcpy(dst, mpath->dst, ETH_ALEN); - _rtw_memcpy(next_hop, mpath->next_hop->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(next_hop, mpath->next_hop->phl_sta->mac_addr, ETH_ALEN); sn = mpath->sn; metric = mpath->metric; qlen = mpath->frame_queue_len; @@ -414,14 +413,14 @@ int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath) goto err_rcu; } - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mcfg = &mpath->adapter->mesh_cfg; mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mcfg->path_gate_timeout_factor * mpath->gate_ann_int); if (mpath->is_gate) { err = -EEXIST; - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); goto err_rcu; } @@ -442,10 +441,10 @@ int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath) _rtw_spinunlock(&tbl->gates_lock); - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); if (ori_num_gates == 0) { - update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); + rtw_update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); #if CONFIG_RTW_MESH_CTO_MGATE_CARRIER if (!rtw_mesh_cto_mgate_required(mpath->adapter)) rtw_netif_carrier_on(mpath->adapter->pnetdev); @@ -481,7 +480,7 @@ void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) minfo = &mpath->adapter->mesh_info; mpath->is_gate = false; - enter_critical_bh(&tbl->gates_lock); + _rtw_spinlock_bh(&tbl->gates_lock); rtw_hlist_del_rcu(&mpath->gate_list); ori_num_gates = minfo->num_gates; minfo->num_gates--; @@ -502,10 +501,10 @@ void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) rtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter)); } - exit_critical_bh(&tbl->gates_lock); + _rtw_spinunlock_bh(&tbl->gates_lock); if (ori_num_gates == 1) { - update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); + rtw_update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); #if CONFIG_RTW_MESH_CTO_MGATE_CARRIER if (rtw_mesh_cto_mgate_required(mpath->adapter)) rtw_netif_carrier_off(mpath->adapter->pnetdev); @@ -610,7 +609,7 @@ struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter, new_mpath->frame_queue_len = 0; new_mpath->exp_time = rtw_get_current_time(); _rtw_spinlock_init(&new_mpath->state_lock); - rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath); + rtw_init_timer(&new_mpath->timer, rtw_mesh_path_timer, new_mpath); return new_mpath; } @@ -771,10 +770,10 @@ void rtw_mesh_plink_broken(struct sta_info *sta) if (rtw_rcu_access_pointer(mpath->next_hop) == sta && mpath->flags & RTW_MESH_PATH_ACTIVE && !(mpath->flags & RTW_MESH_PATH_FIXED)) { - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mpath->flags &= ~RTW_MESH_PATH_ACTIVE; ++mpath->sn; - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); rtw_mesh_path_error_tx(adapter, adapter->mesh_cfg.element_ttl, mpath->dst, mpath->sn, @@ -791,10 +790,10 @@ static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, { _adapter *adapter = mpath->adapter; - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED; rtw_mesh_gate_del(tbl, mpath); - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); _cancel_timer_ex(&mpath->timer); ATOMIC_DEC(&adapter->mesh_info.mpaths); ATOMIC_DEC(&tbl->entries); @@ -999,20 +998,20 @@ void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath) _rtw_init_listhead(&q); /* move to local queue */ - enter_critical_bh(&mpath->frame_queue.lock); + _rtw_spinlock_bh(&mpath->frame_queue.lock); if (mpath->frame_queue_len) { rtw_list_splice_init(&mpath->frame_queue.queue, &q); q_len = mpath->frame_queue_len; mpath->frame_queue_len = 0; } - exit_critical_bh(&mpath->frame_queue.lock); + _rtw_spinunlock_bh(&mpath->frame_queue.lock); if (q_len) { /* move to mpath_tx_queue */ - enter_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinlock_bh(&minfo->mpath_tx_queue.lock); rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue); minfo->mpath_tx_queue_len += q_len; - exit_critical_bh(&minfo->mpath_tx_queue.lock); + _rtw_spinunlock_bh(&minfo->mpath_tx_queue.lock); /* schedule mpath_tx_tasklet */ tasklet_hi_schedule(&minfo->mpath_tx_tasklet); @@ -1098,10 +1097,10 @@ void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath) _rtw_init_listhead(&tmp); - enter_critical_bh(&mpath->frame_queue.lock); + _rtw_spinlock_bh(&mpath->frame_queue.lock); rtw_list_splice_init(&mpath->frame_queue.queue, &tmp); mpath->frame_queue_len = 0; - exit_critical_bh(&mpath->frame_queue.lock); + _rtw_spinunlock_bh(&mpath->frame_queue.lock); head = &tmp; list = get_next(head); @@ -1123,7 +1122,7 @@ void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath) */ void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop) { - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); rtw_mesh_path_assign_nexthop(mpath, next_hop); mpath->sn = 0xffff; mpath->metric = 0; @@ -1131,7 +1130,7 @@ void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *nex mpath->exp_time = 0; mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID; rtw_mesh_path_activate(mpath); - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); rtw_ewma_err_rate_init(&next_hop->metrics.err_rate); /* init it at a low value - 0 start is tricky */ rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1); @@ -1200,14 +1199,14 @@ void rtw_mesh_path_tbl_expire(_adapter *adapter, RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n", FUNC_ADPT_ARG(adapter), mpath->dst, mpath->gate_timeout, rtw_get_current_time()); - enter_critical_bh(&mpath->state_lock); + _rtw_spinlock_bh(&mpath->state_lock); if (mpath->gate_asked) { /* asked gate before */ rtw_mesh_gate_del(tbl, mpath); - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); } else { mpath->gate_asked = true; mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int); - exit_critical_bh(&mpath->state_lock); + _rtw_spinunlock_bh(&mpath->state_lock); rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n", FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root); diff --git a/core/mesh/rtw_mesh_pathtbl.h b/core/mesh/rtw_mesh_pathtbl.h index be0c409..7ff4d8b 100644 --- a/core/mesh/rtw_mesh_pathtbl.h +++ b/core/mesh/rtw_mesh_pathtbl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/core/monitor/rtw_radiotap.c b/core/monitor/rtw_radiotap.c index e9ebc7d..4012513 100644 --- a/core/monitor/rtw_radiotap.c +++ b/core/monitor/rtw_radiotap.c @@ -17,7 +17,38 @@ #ifdef CONFIG_WIFI_MONITOR #include -#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) +#include +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +/** + * FIELD_PREP() - prepare a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP() masks and shifts up the value. The result should + * be combined with other fields of the bitfield using logical OR. + */ +#define FIELD_PREP(_mask, _val) \ + ({ \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) +#endif + +#define __encode_bits(w, v, field) FIELD_PREP((u##w)(field), v) +#define __u16_encode_bits(v, field) __encode_bits(16, v, field) +#define __le16_encode_bits(v, field) cpu_to_le16(__encode_bits(16, v, field)) +#define __be16_encode_bits(v, field) cpu_to_be16(__encode_bits(16, v, field)) +#define __u32_encode_bits(v, field) __encode_bits(32, v, field) +#define __le32_encode_bits(v, field) cpu_to_le32(__encode_bits(32, v, field)) +#define __be32_encode_bits(v, field) cpu_to_be32(__encode_bits(32, v, field)) +#define __u64_encode_bits(v, field) __encode_bits(64, v, field) +#define __le64_encode_bits(v, field) cpu_to_le64(__encode_bits(64, v, field)) +#define __be64_encode_bits(v, field) cpu_to_be64(__encode_bits(64, v, field)) + #define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a)) @@ -53,6 +84,99 @@ #define IEEE80211_CHAN_QUARTER 0x8000 /* Quarter channel (5 MHz wide) */ #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)) +#define IEEE80211_RADIOTAP_HE 23 + +struct ieee80211_radiotap_he { + u16 data1, data2, data3, data4, data5, data6; +}; + +enum ieee80211_radiotap_he_bits { + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3, + + IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 0x0004, + IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 0x0008, + IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 0x0010, + IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 0x0020, + IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 0x0040, + IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 0x0080, + IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 0x0100, + IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 0x0200, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 0x0400, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 0x0800, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 0x2000, + IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 0x4000, + IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 0x0001, + IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 0x0002, + IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 0x0004, + IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 0x0008, + IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 0x0010, + IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 0x0020, + IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 0x0040, + IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 0x0080, + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 0x3f00, + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 0x4000, + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 0x003f, + IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 0x0040, + IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 0x0080, + IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 0x0f00, + IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000, + IEEE80211_RADIOTAP_HE_DATA3_CODING = 0x2000, + IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 0x4000, + IEEE80211_RADIOTAP_HE_DATA3_STBC = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 0x000f, + IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 0x7ff0, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 0x000f, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 0x00f0, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 0x0f00, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 0xf000, + + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 0x000f, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10, + + IEEE80211_RADIOTAP_HE_DATA5_GI = 0x0030, + IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0, + IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1, + IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2, + + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 0x00c0, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3, + IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 0x0700, + IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 0x3000, + IEEE80211_RADIOTAP_HE_DATA5_TXBF = 0x4000, + IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA6_NSTS = 0x000f, + IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 0x0010, + IEEE80211_RADIOTAP_HE_DATA6_TXOP = 0x7f00, + IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 0x8000, +}; + +#endif + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) #define IEEE80211_RADIOTAP_VHT 21 /* For IEEE80211_RADIOTAP_VHT */ @@ -161,7 +285,8 @@ static inline void _rtw_radiotap_fill_flags(struct rx_pkt_attrib *a, u8 *flags) } -sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) +sint rtw_fill_radiotap_hdr(_adapter *padapter, + struct rx_pkt_attrib *a, struct rtw_recv_pkt *rx_req, u8 *buf) { #define RTAP_HDR_MAX 64 @@ -170,20 +295,18 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) u8 rx_cnt = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - int i = 0; u8 tmp_8bit = 0; u16 tmp_16bit = 0; u32 tmp_32bit = 0; u64 tmp_64bit = 0; - _pkt *pskb = NULL; + struct sk_buff *pskb = NULL; struct ieee80211_radiotap_header *rtap_hdr = NULL; u8 *ptr = NULL; - /* + /* radiotap length (include header 8) 11G length: 36 (0x0040002f) 11N length: @@ -197,7 +320,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION; /* each antenna information */ - rx_cnt = rf_type_to_rf_rx_cnt(pHalData->rf_type); + rx_cnt = GET_HAL_RFPATH_NUM(padapter->dvobj); #if 0 if (rx_cnt > 1) { rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE) | @@ -228,7 +351,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) if (!IS_ALIGNED(rt_len, 8)) rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */ - tmp_64bit = cpu_to_le64(a->free_cnt); + tmp_64bit = cpu_to_le64(rx_req->mdata.freerun_cnt); _rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8); rt_len += 8; } @@ -239,9 +362,9 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rt_len += 1; /* rate */ - if (a->data_rate <= DESC_RATE54M) { + if (rx_req->mdata.rx_rate <= RTW_DATA_RATE_OFDM54) { rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RATE); - hdr_buf[rt_len] = hw_rate_to_m_rate(a->data_rate); + hdr_buf[rt_len] = hwrate_to_mrate(rx_req->mdata.rx_rate); rt_len += 1; } @@ -256,12 +379,12 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) /* channel flags */ tmp_16bit = 0; - if (pHalData->current_band_type == 0) + if (WIFI_ROLE_IS_ON_24G(padapter)) tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ); else tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); - if (a->data_rate <= DESC_RATE11M) { + if (rx_req->mdata.rx_rate <= RTW_DATA_RATE_CCK11) { /* CCK */ tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK); } else { @@ -318,7 +441,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) #endif /* MCS information, Required Alignment: 1 bytes */ - if (a->data_rate >= DESC_RATEMCS0 && a->data_rate <= DESC_RATEMCS31) { + if (rx_req->mdata.rx_rate >= RTW_DATA_RATE_MCS0 && rx_req->mdata.rx_rate <= RTW_DATA_RATE_MCS31) { rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_MCS); /* Structure u8 known, u8 flags, u8 mcs */ @@ -326,7 +449,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_BW; if (moif->u.snif_info.ofdm_bw) hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40; - if (a->bw == CHANNEL_WIDTH_40) + if (rx_req->mdata.bw == CHANNEL_WIDTH_40) hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40; else hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_20; @@ -360,13 +483,13 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_MCS; /* u8 mcs */ - hdr_buf[rt_len + 2] = a->data_rate - DESC_RATEMCS0; + hdr_buf[rt_len + 2] = rx_req->mdata.rx_rate - RTW_DATA_RATE_MCS0; rt_len += 3; } /* AMPDU, Required Alignment: 4 bytes */ - if (a->ampdu) { + if (rx_req->mdata.ampdu) { static u32 ref_num = 0x10000000; static u8 ppdu_cnt = 0; @@ -376,8 +499,8 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rt_len = ((rt_len + 3) & 0xFFFC); /* Alignment */ /* u32 reference number */ - if (a->ppdu_cnt != ppdu_cnt) { - ppdu_cnt = a->ppdu_cnt; + if (rx_req->mdata.ppdu_cnt != ppdu_cnt) { + ppdu_cnt = rx_req->mdata.ppdu_cnt; ref_num += 1; } tmp_32bit = cpu_to_le32(ref_num); @@ -401,7 +524,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN); } - if (a->ampdu_eof) { + if (rx_req->mdata.ampdu_end_pkt) { tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN); tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF); } @@ -414,7 +537,8 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) } /* VHT, Required Alignment: 2 bytes */ - if (a->data_rate >= DESC_RATEVHTSS1MCS0 && a->data_rate <= DESC_RATEVHTSS4MCS9) { + if (rx_req->mdata.rx_rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rx_req->mdata.rx_rate <= RTW_DATA_RATE_VHT_NSS4_MCS9) { + rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_VHT); rt_len += (rt_len % 2); /* Alignment */ @@ -484,7 +608,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) if (moif->u.snif_info.ofdm_bw) tmp_8bit = moif->u.snif_info.ofdm_bw; else - tmp_8bit = a->bw; + tmp_8bit = rx_req->mdata.bw; switch (tmp_8bit) { case CHANNEL_WIDTH_20: @@ -505,13 +629,13 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rt_len += 1; /* u8 mcs_nss[4] */ - if ((DESC_RATEVHTSS1MCS0 <= a->data_rate) && - (a->data_rate <= DESC_RATEVHTSS4MCS9)) { + if ((RTW_DATA_RATE_VHT_NSS1_MCS0 <= rx_req->mdata.rx_rate) && + (rx_req->mdata.rx_rate <= RTW_DATA_RATE_VHT_NSS4_MCS9)) { /* User 0 */ /* MCS */ - hdr_buf[rt_len] = ((a->data_rate - DESC_RATEVHTSS1MCS0) % 10) << 4; + hdr_buf[rt_len] = cpu_to_le16 (((rx_req->mdata.rx_rate - RTW_DATA_RATE_VHT_NSS1_MCS0) % 10) << 4); /* NSS */ - hdr_buf[rt_len] |= (((a->data_rate - DESC_RATEVHTSS1MCS0) / 10) + 1); + hdr_buf[rt_len] |= cpu_to_le16((((rx_req->mdata.rx_rate - RTW_DATA_RATE_VHT_NSS1_MCS0) / 10) + 1)); } rt_len += 4; @@ -529,6 +653,73 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rt_len += 2; } + /* HE, Required Alignment: 2 bytes */ + if (rx_req->mdata.rx_rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rx_req->mdata.rx_rate <= RTW_DATA_RATE_HE_NSS4_MCS11) { + + struct ieee80211_radiotap_he he_hdr; + u8 ltf, he_gi, ss; + + _rtw_memset(&he_hdr, 0, sizeof(struct ieee80211_radiotap_he)); + rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_HE); + + rt_len += (rt_len % 2); /* Alignment */ + /* Structure + u16 data1, data2, data3, data4, data5, data6 */ + + /* HE PPDU Format: 0=HE_SU, 1=HE_EXT_SU, 2=HE_MU, 3=HE_TRIG */ + he_hdr.data1 |= 0x0000; + he_hdr.data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN); + he_hdr.data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN); + + he_hdr.data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN); + he_hdr.data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN); + + he_hdr.data3 |= __le16_encode_bits((rx_req->mdata.rx_rate & 0xf), IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS); + + he_hdr.data5 |= cpu_to_le16((rx_req->mdata.bw)); + + switch (rx_req->mdata.rx_gi_ltf) { + case 0x0: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_3_2; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X; + break; + case 0x1: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_0_8; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X; + break; + case 0x2: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_1_6; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X; + break; + case 0x3: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_0_8; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X; + break; + case 0x4: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_1_6; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X; + break; + case 0x5: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_0_8; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X; + break; + default: + he_gi = IEEE80211_RADIOTAP_HE_DATA5_GI_0_8; + ltf = IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X; + break; + } + + he_hdr.data5 |= __le16_encode_bits(he_gi, IEEE80211_RADIOTAP_HE_DATA5_GI); + he_hdr.data5 |= __le16_encode_bits(ltf, IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); + + ss = cpu_to_le16(((0x70 & rx_req->mdata.rx_rate) >> 4) + 1); + he_hdr.data6 |= __le16_encode_bits(ss, IEEE80211_RADIOTAP_HE_DATA6_NSTS); + + _rtw_memcpy(&hdr_buf[rt_len], &he_hdr, sizeof(struct ieee80211_radiotap_he)); + + rt_len += sizeof(struct ieee80211_radiotap_he); + } + /* frame timestamp, Required Alignment: 8 bytes */ if (0) { //(a->free_cnt) { rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_TIMESTAMP); @@ -536,7 +727,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */ /* u64 timestamp */ - tmp_64bit = cpu_to_le64(a->free_cnt); + tmp_64bit = cpu_to_le64(rx_req->mdata.freerun_cnt); _rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8); rt_len += 8; @@ -577,7 +768,7 @@ sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf) #endif /* push to skb */ - pskb = (_pkt *)buf; + pskb = (struct sk_buff *)buf; if (skb_headroom(pskb) < rt_len) { RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__); ret = _FAIL; diff --git a/core/monitor/rtw_radiotap.h b/core/monitor/rtw_radiotap.h index affacd1..f6599d8 100644 --- a/core/monitor/rtw_radiotap.h +++ b/core/monitor/rtw_radiotap.h @@ -55,7 +55,8 @@ struct moinfo { }u; }; -sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf); +sint rtw_fill_radiotap_hdr(_adapter *padapter, + struct rx_pkt_attrib *a, struct rtw_recv_pkt *rx_req, u8 *buf); void rx_query_moinfo(struct rx_pkt_attrib *a, u8 *desc); diff --git a/core/rtw_ap.c b/core/rtw_ap.c index ec72564..1b424d4 100644 --- a/core/rtw_ap.c +++ b/core/rtw_ap.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_AP_C_ #include -#include #ifdef CONFIG_AP_MODE @@ -173,6 +172,7 @@ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *d u8 *p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; u32 i, offset, ielen = 0, ie_offset, remainder_ielen = 0; + /* Search element id (index) exits or not */ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) { pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); @@ -190,6 +190,7 @@ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *d i += (pIE->Length + 2); } + /* Backup remainder IE */ if (p != NULL && ielen > 0) { ielen += 2; @@ -220,7 +221,7 @@ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *d _rtw_memcpy(dst_ie, data, len); dst_ie += len; - /* copy remainder IE */ + /* Append remainder IE */ if (pbackup_remainder_ie) { _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); @@ -268,6 +269,40 @@ void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index) pnetwork->IELength = offset + remainder_ielen; } +void rtw_remove_bcn_ie_ex(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8* pindex_ex, u8 index_ex_len) +{ + u8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; + uint offset, ielen, ie_offset, remainder_ielen = 0; + u8 *pie = pnetwork->IEs; + + p = rtw_get_ie_ex(pie + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, index, pindex_ex, index_ex_len, NULL, &ielen); + if (p != NULL && ielen > 0) { + premainder_ie = p + ielen; + + ie_offset = (sint)(p - pie); + + remainder_ielen = pnetwork->IELength - ie_offset - ielen; + + dst_ie = p; + } else + return; + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if (pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + /* copy remainder IE */ + if (pbackup_remainder_ie) { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork->IELength = offset + remainder_ielen; +} u8 chk_sta_is_alive(struct sta_info *psta); u8 chk_sta_is_alive(struct sta_info *psta) @@ -275,8 +310,8 @@ u8 chk_sta_is_alive(struct sta_info *psta) u8 ret = _FALSE; #ifdef DBG_EXPIRATION_CHK RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" - , MAC_ARG(psta->cmn.mac_addr) - , psta->cmn.rssi_stat.rssi + , MAC_ARG(psta->phl_sta->mac_addr) + , 0 /* TODO: psta->phl_sta->hal_sta->rssi_stat.rssi */ /* , STA_RX_PKTS_ARG(psta) */ , STA_RX_PKTS_DIFF_ARG(psta) , psta->expire_to @@ -325,7 +360,7 @@ u8 chk_sta_is_alive(struct sta_info *psta) static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta) { int ret = _FAIL; - u8 *target_addr = psta->cmn.mac_addr; + u8 *target_addr = psta->phl_sta->mac_addr; if (MLME_IS_AP(adapter)) { /* issue null data to check sta alive */ @@ -365,40 +400,8 @@ static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta) } #endif -#ifdef RTW_CONFIG_RFREG18_WA -static void rtw_check_restore_rf18(_adapter *padapter) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u32 reg; - u8 union_ch = 0, union_bw = 0, union_offset = 0, setchbw = _FALSE; - - reg = rtw_hal_read_rfreg(padapter, 0, 0x18, 0x3FF); - if ((reg & 0xFF) == 0) - setchbw = _TRUE; - reg = rtw_hal_read_rfreg(padapter, 1, 0x18, 0x3FF); - if ((reg & 0xFF) == 0) - setchbw = _TRUE; - - if (setchbw) { - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)) { - RTW_INFO("Hit RF(0x18)=0!! restore original channel setting.\n"); - union_ch = pmlmeext->cur_channel; - union_offset = pmlmeext->cur_ch_offset ; - union_bw = pmlmeext->cur_bwmode; - } else { - RTW_INFO("Hit RF(0x18)=0!! set ch(%x) offset(%x) bwmode(%x)\n", union_ch, union_offset, union_bw); - } - /* Initial the channel_bw setting procedure. */ - pHalData->current_channel = 0; - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - } -} -#endif - void expire_timeout_chk(_adapter *padapter) { - _irqL irqL; _list *phead, *plist; u8 updated = _FALSE; struct sta_info *psta = NULL; @@ -431,15 +434,7 @@ void expire_timeout_chk(_adapter *padapter) rtw_wds_path_expire(padapter); #endif -#ifdef CONFIG_MCC_MODE - /* then driver may check fail due to not recv client's frame under sitesurvey, - * don't expire timeout chk under MCC under sitesurvey */ - - if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE) - return; -#endif - - _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->auth_list_lock); phead = &pstapriv->auth_list; plist = get_next(phead); @@ -458,7 +453,7 @@ void expire_timeout_chk(_adapter *padapter) #ifdef CONFIG_ATMEL_RC_PATCH - if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) + if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->phl_sta->mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -476,16 +471,16 @@ void expire_timeout_chk(_adapter *padapter) } - _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->auth_list_lock); for (i = 0; i < flush_num; i++) { psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); RTW_INFO(FUNC_ADPT_FMT" auth expire "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); rtw_free_stainfo(padapter, psta); psta = NULL; } - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -502,8 +497,8 @@ void expire_timeout_chk(_adapter *padapter) plist = get_next(plist); #ifdef CONFIG_ATMEL_RC_PATCH RTW_INFO("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__, - psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]); - if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) + psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->phl_sta->mac_addr[0], psta->phl_sta->mac_addr[5]); + if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->phl_sta->mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -527,6 +522,7 @@ void expire_timeout_chk(_adapter *padapter) /* check sta by delba(addba) for 11n STA */ /* ToDo: use CCX report to check for all STAs */ /* RTW_INFO("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); */ + if (psta->expire_to <= (pstapriv->expire_to - 50)) { RTW_INFO("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2); psta->under_exist_checking = 0; @@ -535,7 +531,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2); psta->under_exist_checking = 1; /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ + send_delba(padapter, 1, psta->phl_sta->mac_addr);/* */ /* originator */ psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ } @@ -585,7 +581,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); - issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority); + issue_addba_req(padapter, psta->phl_sta->mac_addr, (u8)priority); _set_timer(&psta->addba_retry_timer, ADDBA_TO); @@ -609,11 +605,11 @@ void expire_timeout_chk(_adapter *padapter) psta->expire_to = pstapriv->expire_to; psta->state |= WIFI_STA_ALIVE_CHK_STATE; - /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */ + /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->phl_sta->mac_addr)); */ /* to update bcn with tim_bitmap for this station */ - rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); + rtw_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); if (!pmlmeext->active_keep_alive_check) continue; @@ -634,14 +630,14 @@ void expire_timeout_chk(_adapter *padapter) && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2) ) { RTW_INFO(FUNC_ADPT_FMT" sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); wakeup_sta_to_xmit(padapter, psta); } } } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); if (chk_alive_num) { #if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) @@ -656,24 +652,17 @@ void expire_timeout_chk(_adapter *padapter) #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK if (pmlmeext->active_keep_alive_check) { - #ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't switch channel under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - switch_channel_by_drv = _FALSE; - } - #endif if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) + || pmlmeext->chandef.chan != union_ch) switch_channel_by_drv = _FALSE; /* switch to correct channel of current network before issue keep-alive frames */ - if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->chandef.chan) { backup_ch = rtw_get_oper_ch(padapter); backup_bw = rtw_get_oper_bw(padapter); backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw, _FALSE); } } #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ @@ -687,7 +676,7 @@ void expire_timeout_chk(_adapter *padapter) psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); #ifdef CONFIG_ATMEL_RC_PATCH - if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE) + if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->phl_sta->mac_addr, ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -704,13 +693,13 @@ void expire_timeout_chk(_adapter *padapter) psta->keep_alive_trycnt++; if (ret == _SUCCESS) { RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" is alive\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); psta->expire_to = pstapriv->expire_to; psta->keep_alive_trycnt = 0; continue; } else if (psta->keep_alive_trycnt <= 3) { RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" keep_alive_trycnt=%d\n" - , FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt); + , FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->phl_sta->mac_addr), psta->keep_alive_trycnt); psta->expire_to = 1; continue; } @@ -719,7 +708,7 @@ void expire_timeout_chk(_adapter *padapter) psta->keep_alive_trycnt = 0; del_asoc_list[i] = chk_alive_list[i]; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -729,7 +718,7 @@ void expire_timeout_chk(_adapter *padapter) #endif STA_SET_MESH_PLINK(psta, NULL); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); } /* delete loop */ @@ -740,11 +729,11 @@ void expire_timeout_chk(_adapter *padapter) continue; psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]); - _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(sta_addr, psta->phl_sta->mac_addr, ETH_ALEN); RTW_INFO(FUNC_ADPT_FMT" asoc expire "MAC_FMT", state=0x%x\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state); - updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr), psta->state); + updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE, _FALSE); #ifdef CONFIG_RTW_MESH if (MLME_IS_MESH(padapter)) rtw_mesh_expire_peer(padapter, sta_addr); @@ -755,168 +744,117 @@ void expire_timeout_chk(_adapter *padapter) if (pmlmeext->active_keep_alive_check) { /* back to the original operation channel */ if (switch_channel_by_drv == _TRUE && backup_ch > 0) - set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw, _FALSE); } #endif } -#ifdef RTW_CONFIG_RFREG18_WA - rtw_check_restore_rf18(padapter); -#endif associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } -void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta) -{ - unsigned char sta_band = 0; - u64 tx_ra_bitmap = 0; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; - - if (!psta) - return; - - if (!(psta->state & WIFI_ASOC_STATE)) - return; - - rtw_hal_update_sta_ra_info(padapter, psta); - tx_ra_bitmap = psta->cmn.ra_info.ramask; - - if (pcur_network->Configuration.DSConfig > 14) { - - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_5N; - - if (tx_ra_bitmap & 0xff0) - sta_band |= WIRELESS_11A; - - /* 5G band */ -#ifdef CONFIG_80211AC_VHT - if (psta->vhtpriv.vht_option) - sta_band = WIRELESS_11_5AC; -#endif - } else { - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_24N; - - if (tx_ra_bitmap & 0xff0) - sta_band |= WIRELESS_11G; - - if (tx_ra_bitmap & 0x0f) - sta_band |= WIRELESS_11B; - } - - psta->wireless_mode = sta_band; - rtw_hal_update_sta_wset(padapter, psta); - RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", - __FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode); -} - #ifdef CONFIG_BMC_TX_RATE_SELECT u8 rtw_ap_find_mini_tx_rate(_adapter *adapter) { - _irqL irqL; _list *phead, *plist; - u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate; + u8 mini_tx_rate = DESC_RATEVHTSS4MCS9, sta_tx_rate; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &adapter->stapriv; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); plist = get_next(plist); - sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F; - if (sta_tx_rate < miini_tx_rate) - miini_tx_rate = sta_tx_rate; + sta_tx_rate = psta->phl_sta->ra_info.curr_tx_rate & 0x7F; + if (sta_tx_rate < mini_tx_rate) + mini_tx_rate = sta_tx_rate; } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); - return miini_tx_rate; + return mini_tx_rate; } u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate) { - PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); - u8 tx_ini_rate = ODM_RATE6M; + u8 tx_ini_rate = DESC_RATE6M; switch (tx_rate) { - case ODM_RATEVHTSS3MCS9: - case ODM_RATEVHTSS3MCS8: - case ODM_RATEVHTSS3MCS7: - case ODM_RATEVHTSS3MCS6: - case ODM_RATEVHTSS3MCS5: - case ODM_RATEVHTSS3MCS4: - case ODM_RATEVHTSS3MCS3: - case ODM_RATEVHTSS2MCS9: - case ODM_RATEVHTSS2MCS8: - case ODM_RATEVHTSS2MCS7: - case ODM_RATEVHTSS2MCS6: - case ODM_RATEVHTSS2MCS5: - case ODM_RATEVHTSS2MCS4: - case ODM_RATEVHTSS2MCS3: - case ODM_RATEVHTSS1MCS9: - case ODM_RATEVHTSS1MCS8: - case ODM_RATEVHTSS1MCS7: - case ODM_RATEVHTSS1MCS6: - case ODM_RATEVHTSS1MCS5: - case ODM_RATEVHTSS1MCS4: - case ODM_RATEVHTSS1MCS3: - case ODM_RATEMCS15: - case ODM_RATEMCS14: - case ODM_RATEMCS13: - case ODM_RATEMCS12: - case ODM_RATEMCS11: - case ODM_RATEMCS7: - case ODM_RATEMCS6: - case ODM_RATEMCS5: - case ODM_RATEMCS4: - case ODM_RATEMCS3: - case ODM_RATE54M: - case ODM_RATE48M: - case ODM_RATE36M: - case ODM_RATE24M: - tx_ini_rate = ODM_RATE24M; + case DESC_RATEVHTSS3MCS9: + case DESC_RATEVHTSS3MCS8: + case DESC_RATEVHTSS3MCS7: + case DESC_RATEVHTSS3MCS6: + case DESC_RATEVHTSS3MCS5: + case DESC_RATEVHTSS3MCS4: + case DESC_RATEVHTSS3MCS3: + case DESC_RATEVHTSS2MCS9: + case DESC_RATEVHTSS2MCS8: + case DESC_RATEVHTSS2MCS7: + case DESC_RATEVHTSS2MCS6: + case DESC_RATEVHTSS2MCS5: + case DESC_RATEVHTSS2MCS4: + case DESC_RATEVHTSS2MCS3: + case DESC_RATEVHTSS1MCS9: + case DESC_RATEVHTSS1MCS8: + case DESC_RATEVHTSS1MCS7: + case DESC_RATEVHTSS1MCS6: + case DESC_RATEVHTSS1MCS5: + case DESC_RATEVHTSS1MCS4: + case DESC_RATEVHTSS1MCS3: + case DESC_RATEMCS15: + case DESC_RATEMCS14: + case DESC_RATEMCS13: + case DESC_RATEMCS12: + case DESC_RATEMCS11: + case DESC_RATEMCS7: + case DESC_RATEMCS6: + case DESC_RATEMCS5: + case DESC_RATEMCS4: + case DESC_RATEMCS3: + case DESC_RATE54M: + case DESC_RATE48M: + case DESC_RATE36M: + case DESC_RATE24M: + tx_ini_rate = DESC_RATE24M; break; - case ODM_RATEVHTSS3MCS2: - case ODM_RATEVHTSS3MCS1: - case ODM_RATEVHTSS2MCS2: - case ODM_RATEVHTSS2MCS1: - case ODM_RATEVHTSS1MCS2: - case ODM_RATEVHTSS1MCS1: - case ODM_RATEMCS10: - case ODM_RATEMCS9: - case ODM_RATEMCS2: - case ODM_RATEMCS1: - case ODM_RATE18M: - case ODM_RATE12M: - tx_ini_rate = ODM_RATE12M; + case DESC_RATEVHTSS3MCS2: + case DESC_RATEVHTSS3MCS1: + case DESC_RATEVHTSS2MCS2: + case DESC_RATEVHTSS2MCS1: + case DESC_RATEVHTSS1MCS2: + case DESC_RATEVHTSS1MCS1: + case DESC_RATEMCS10: + case DESC_RATEMCS9: + case DESC_RATEMCS2: + case DESC_RATEMCS1: + case DESC_RATE18M: + case DESC_RATE12M: + tx_ini_rate = DESC_RATE12M; break; - case ODM_RATEVHTSS3MCS0: - case ODM_RATEVHTSS2MCS0: - case ODM_RATEVHTSS1MCS0: - case ODM_RATEMCS8: - case ODM_RATEMCS0: - case ODM_RATE9M: - case ODM_RATE6M: - tx_ini_rate = ODM_RATE6M; + case DESC_RATEVHTSS3MCS0: + case DESC_RATEVHTSS2MCS0: + case DESC_RATEVHTSS1MCS0: + case DESC_RATEMCS8: + case DESC_RATEMCS0: + case DESC_RATE9M: + case DESC_RATE6M: + tx_ini_rate = DESC_RATE6M; break; - case ODM_RATE11M: - case ODM_RATE5_5M: - case ODM_RATE2M: - case ODM_RATE1M: - tx_ini_rate = ODM_RATE1M; + case DESC_RATE11M: + case DESC_RATE5_5M: + case DESC_RATE2M: + case DESC_RATE1M: + tx_ini_rate = DESC_RATE1M; break; default: - tx_ini_rate = ODM_RATE6M; + tx_ini_rate = DESC_RATE6M; break; } - if (hal_data->current_band_type == BAND_ON_5G) - if (tx_ini_rate < ODM_RATE6M) - tx_ini_rate = ODM_RATE6M; + if (WIFI_ROLE_IS_ON_5G(adapter)) + if (tx_ini_rate < DESC_RATE6M) + tx_ini_rate = DESC_RATE6M; return tx_ini_rate; } @@ -945,7 +883,7 @@ void rtw_update_bmc_sta_tx_rate(_adapter *adapter) tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate); #endif - psta->init_rate = hw_rate_to_m_rate(tx_rate); + psta->init_rate = hwrate_to_mrate(tx_rate); _exit: RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate)); @@ -954,6 +892,8 @@ void rtw_update_bmc_sta_tx_rate(_adapter *adapter) void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta) { +/* ToDo: need API to query hal_sta->ra_info.ramask */ +#if 0 #ifdef CONFIG_BMC_TX_LOW_RATE struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); #endif @@ -968,74 +908,20 @@ void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta) psta->init_rate = padapter->bmc_tx_rate; else { #ifdef CONFIG_BMC_TX_LOW_RATE - if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0)) - rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/ + if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->phl_sta->ra_info.ramask && 0xFF0)) + rate_idx = get_lowest_rate_idx_ex(psta->phl_sta->ra_info.ramask, 4); /*from basic rate*/ else - rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + rate_idx = get_lowest_rate_idx(psta->phl_sta->ra_info.ramask); /*from basic rate*/ #else - rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + rate_idx = get_highest_rate_idx(psta->phl_sta->ra_info.ramask); /*from basic rate*/ #endif if (rate_idx < 12) psta->init_rate = brate_table[rate_idx]; else psta->init_rate = MGN_1M; } - - RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate)); -} - -void update_bmc_sta(_adapter *padapter) -{ - _irqL irqL; - unsigned char network_type; - int supportRateNum = 0; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; - struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); - - if (psta) { - psta->cmn.aid = 0;/* default set to 0 */ -#ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) - psta->qos_option = 1; - else #endif - psta->qos_option = 0; -#ifdef CONFIG_80211N_HT - psta->htpriv.ht_option = _FALSE; -#endif /* CONFIG_80211N_HT */ - - psta->ieee8021x_blocked = 0; - - _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); - - /* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */ - - supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates); - network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig); - if (IsSupportedTxCCK(network_type)) - network_type = WIRELESS_11B; - else if (network_type == WIRELESS_INVALID) { /* error handling */ - if (pcur_network->Configuration.DSConfig > 14) - network_type = WIRELESS_11A; - else - network_type = WIRELESS_11B; - } - update_sta_basic_rate(psta, network_type); - psta->wireless_mode = network_type; - - rtw_hal_update_sta_ra_info(padapter, psta); - - _enter_critical_bh(&psta->lock, &irqL); - psta->state = WIFI_ASOC_STATE; - _exit_critical_bh(&psta->lock, &irqL); - - rtw_sta_media_status_rpt(padapter, psta, 1); - rtw_init_bmc_sta_tx_rate(padapter, psta); - - } else - RTW_INFO("add_RATid_bmc_sta error!\n"); - + RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate)); } #if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING) @@ -1062,11 +948,9 @@ void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta) SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); } if (cur_beamform_cap) - RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap); + RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->phl_sta->aid, cur_beamform_cap); phtpriv_sta->beamform_cap = cur_beamform_cap; - psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap; - } #endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/ @@ -1074,10 +958,11 @@ void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta) * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode */ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) { - _irqL irqL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_role_cap = &(wrole->proto_role_cap); #ifdef CONFIG_80211N_HT struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; struct ht_priv *phtpriv_sta = &psta->htpriv; @@ -1098,6 +983,9 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* update sta's cap */ + psta->phl_sta->chandef.chan = pmlmeext->chandef.chan; + psta->phl_sta->chandef.band = (psta->phl_sta->chandef.chan > 14) ? BAND_ON_5G : BAND_ON_24G; + /* ERP */ VCS_update(padapter, psta); #ifdef CONFIG_80211N_HT @@ -1110,21 +998,21 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* bwmode */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) - psta->cmn.bw_mode = CHANNEL_WIDTH_40; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_40; else - psta->cmn.bw_mode = CHANNEL_WIDTH_20; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; if (phtpriv_sta->op_present && !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op)) - psta->cmn.bw_mode = CHANNEL_WIDTH_20; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; if (psta->ht_40mhz_intolerant) - psta->cmn.bw_mode = CHANNEL_WIDTH_20; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; - if (pmlmeext->cur_bwmode < psta->cmn.bw_mode) - psta->cmn.bw_mode = pmlmeext->cur_bwmode; + if (pmlmeext->chandef.bw < psta->phl_sta->chandef.bw) + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; - phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; + phtpriv_sta->ch_offset = pmlmeext->chandef.offset; /* check if sta support s Short GI 20M */ @@ -1133,7 +1021,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* check if sta support s Short GI 40M */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) { - if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ + if (psta->phl_sta->chandef.bw == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ phtpriv_sta->sgi_40m = _TRUE; else phtpriv_sta->sgi_40m = _FALSE; @@ -1145,16 +1033,22 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid); + RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->phl_sta->aid); } /* B7 B8 B9 Config STBC setting */ if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid); + RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->phl_sta->aid); } + psta->phl_sta->asoc_cap.stbc_ht_tx = + GET_HT_CAP_ELE_TX_STBC((u8 *)(&phtpriv_sta->ht_cap)); + psta->phl_sta->asoc_cap.stbc_ht_rx = + proto_role_cap->stbc_ht_tx ? + GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap)) : 0; + #ifdef CONFIG_BEAMFORMING update_sta_info_apmode_ht_bf_cap(padapter, psta); #endif @@ -1163,18 +1057,18 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) phtpriv_sta->sgi_20m = _FALSE; phtpriv_sta->sgi_40m = _FALSE; - psta->cmn.bw_mode = CHANNEL_WIDTH_20; - phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = CHAN_OFFSET_NO_EXT; } phtpriv_sta->ldpc_cap = cur_ldpc_cap; phtpriv_sta->stbc_cap = cur_stbc_cap; /* Rx AMPDU */ - send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ + send_delba(padapter, 0, psta->phl_sta->mac_addr);/* recipient */ /* TX AMPDU */ - send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ + send_delba(padapter, 1, psta->phl_sta->mac_addr);/* */ /* originator */ phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */ phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */ #endif /* CONFIG_80211N_HT */ @@ -1182,21 +1076,23 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT update_sta_vht_info_apmode(padapter, psta); #endif - psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); - update_ldpc_stbc_cap(psta); - /* todo: init other variables */ +#ifdef CONFIG_80211AX_HE + update_sta_he_info_apmode(padapter, psta); +#endif - _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + psta->phl_sta->chandef.offset = (psta->phl_sta->chandef.bw > CHANNEL_WIDTH_20) ? + pmlmeext->chandef.offset : CHAN_OFFSET_NO_EXT; + /* ToDo: need API to inform hal_sta->ra_info.is_support_sgi */ + /* psta->phl_sta->ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); */ + update_ldpc_stbc_cap(psta); - /* add ratid */ - /* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */ + /* todo: init other variables */ - /* ap mode */ - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); + _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); /* Check encryption */ if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) @@ -1204,21 +1100,8 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) psta->state |= WIFI_ASOC_STATE; - _exit_critical_bh(&psta->lock, &irqL); -} - -#ifdef CONFIG_RTW_80211K -static void update_rm_cap(u8 *frame_head, _adapter *pa, u32 pktlen, int offset) -{ - u8 *res; - sint len; - - res = rtw_get_ie(frame_head + offset, _EID_RRM_EN_CAP_IE_, &len, - pktlen - offset); - if (res != NULL) - _rtw_memcpy((void *)pa->rmpriv.rm_en_cap_def, (res + 2), len); + _rtw_spinunlock_bh(&psta->lock); } -#endif static void update_ap_info(_adapter *padapter, struct sta_info *psta) { @@ -1229,7 +1112,12 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; #endif /* CONFIG_80211N_HT */ - psta->wireless_mode = pmlmeext->cur_wireless_mode; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + psta->qos_option = 1; +#endif + + psta->phl_sta->wmode = pmlmeext->cur_wireless_mode; psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates); _rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen); @@ -1255,8 +1143,8 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) phtpriv_ap->sgi_40m = _FALSE; } - psta->cmn.bw_mode = pmlmeext->cur_bwmode; - phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset; + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; + phtpriv_ap->ch_offset = pmlmeext->chandef.offset; phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */ phtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */ @@ -1265,11 +1153,33 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + +#ifdef CONFIG_80211AX_HE + _rtw_memcpy(&psta->hepriv, &pmlmepriv->hepriv, sizeof(struct he_priv)); +#endif /* CONFIG_80211AX_HE */ + #endif /* CONFIG_80211AC_VHT */ #endif /* CONFIG_80211N_HT */ + _rtw_spinlock_bh(&psta->lock); psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */ + psta->state |= WIFI_ASOC_STATE; + _rtw_spinunlock_bh(&psta->lock); + + rtw_init_bmc_sta_tx_rate(padapter, psta); +} + +void rtw_ap_set_edca(_adapter *padapter, enum rtw_ac ac, u32 parm) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = rtw_get_stainfo(pstapriv, padapter->phl_role->mac_addr); + + if (psta && psta->phl_sta) { + psta->phl_sta->asoc_cap.edca[ac].ac = ac; + psta->phl_sta->asoc_cap.edca[ac].param = parm; + } + rtw_hw_set_edca(padapter, ac, parm); } static void rtw_set_hw_wmm_param(_adapter *padapter) @@ -1287,8 +1197,8 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) acm_mask = 0; #ifdef CONFIG_80211N_HT if (pregpriv->ht_enable && - (is_supported_5g(pmlmeext->cur_wireless_mode) || - (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))) + (WIFI_ROLE_IS_ON_5G(padapter) || + (pmlmeext->cur_wireless_mode & WLAN_MD_11N))) aSifsTime = 16; else #endif /* CONFIG_80211N_HT */ @@ -1299,10 +1209,10 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); - if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) { + if (pmlmeext->cur_wireless_mode & (WLAN_MD_11G | WLAN_MD_11A)) { ECWMin = 4; ECWMax = 10; - } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { + } else if (pmlmeext->cur_wireless_mode & WLAN_MD_11B) { ECWMin = 5; ECWMax = 10; } else { @@ -1312,15 +1222,15 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) TXOP = 0; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 0, acParm); + rtw_ap_set_edca(padapter, 1, acParm); + rtw_ap_set_edca(padapter, 2, acParm); ECWMin = 2; ECWMax = 3; TXOP = 0x2f; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 3, acParm); } else { edca[0] = edca[1] = edca[2] = edca[3] = 0; @@ -1338,7 +1248,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) ECWMax = 10; TXOP = 0; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 1, acParm); edca[XMIT_BK_QUEUE] = acParm; RTW_INFO("WMM(BK): %x\n", acParm); @@ -1348,7 +1258,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) ECWMax = 6; TXOP = 0; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 0, acParm); edca[XMIT_BE_QUEUE] = acParm; RTW_INFO("WMM(BE): %x\n", acParm); @@ -1358,7 +1268,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) ECWMax = 4; TXOP = 94; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 2, acParm); edca[XMIT_VI_QUEUE] = acParm; RTW_INFO("WMM(VI): %x\n", acParm); @@ -1368,7 +1278,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) ECWMax = 3; TXOP = 47; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + rtw_ap_set_edca(padapter, 3, acParm); edca[XMIT_VO_QUEUE] = acParm; RTW_INFO("WMM(VO): %x\n", acParm); @@ -1468,7 +1378,6 @@ static void update_hw_ht_param(_adapter *padapter) #endif /* CONFIG_80211N_HT */ static void rtw_ap_check_scan(_adapter *padapter) { - _irqL irqL; _list *plist, *phead; u32 delta_time, lifetime; struct wlan_network *pnetwork = NULL; @@ -1480,16 +1389,16 @@ static void rtw_ap_check_scan(_adapter *padapter) lifetime = SCANQUEUE_LIFETIME; /* 20 sec */ - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE) if (padapter->registrypriv.wifi_spec) { do_scan = _TRUE; reason |= RTW_AUTO_SCAN_REASON_2040_BSS; } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); -#ifdef CONFIG_RTW_ACS +#if defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) if (padapter->registrypriv.acs_auto_scan) { do_scan = _TRUE; reason |= RTW_AUTO_SCAN_REASON_ACS; @@ -1500,15 +1409,15 @@ static void rtw_ap_check_scan(_adapter *padapter) if (_TRUE == do_scan) { RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__); rtw_drv_scan_by_self(padapter, reason); - rtw_scan_wait_completed(padapter); + rtw_scan_abort(padapter, 0); } -#ifdef CONFIG_RTW_ACS +#if defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) if (padapter->registrypriv.acs_auto_scan) rtw_acs_stop(padapter); #endif - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); @@ -1555,7 +1464,7 @@ static void rtw_ap_check_scan(_adapter *padapter) } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); #ifdef CONFIG_80211N_HT pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/ #endif @@ -1576,9 +1485,6 @@ void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) /* update capability after cur_wireless_mode updated */ update_capinfo(adapter, rtw_get_capability(pnetwork)); - /* update bc/mc sta_info */ - update_bmc_sta(adapter); - /* update AP's sta info */ sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress); if (!sta) { @@ -1590,38 +1496,6 @@ void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) update_ap_info(adapter, sta); } -#ifdef CONFIG_FW_HANDLE_TXBCN -bool rtw_ap_nums_check(_adapter *adapter) -{ - if (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM) - return _TRUE; - return _FALSE; -} -u8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj) -{ - u8 vap_id; - - for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) { - if (!(dvobj->vap_map & BIT(vap_id))) - break; - } - - if (vap_id < CONFIG_LIMITED_AP_NUM) - dvobj->vap_map |= BIT(vap_id); - - return vap_id; -} -u8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id) -{ - if (vap_id >= CONFIG_LIMITED_AP_NUM) { - RTW_ERR("%s - vapid(%d) failed\n", __func__, vap_id); - rtw_warn_on(1); - return _FAIL; - } - dvobj->vap_map &= ~ BIT(vap_id); - return _SUCCESS; -} -#endif static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter) { int i; @@ -1638,11 +1512,111 @@ static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter) } } } + +void rtw_core_ap_swch_start(_adapter *padapter, struct createbss_parm *parm) +{ + struct dvobj_priv *pdvobj = padapter->dvobj; + int i; + u8 ht_option = 0; + RTW_INFO("%s\n", __func__); + + if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) + parm->do_rfk = _TRUE; + + if (parm->ch_to_set != 0) { + set_channel_bwmode(padapter, parm->ch_to_set, parm->offset_to_set, parm->bw_to_set, parm->do_rfk); + rtw_phl_mr_dump_cur_chandef(adapter_to_dvobj(padapter)->phl, padapter->phl_role); + } + +#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + for (i = 0; i < pdvobj->iface_nums; i++) { + if (!(parm->ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i]) + continue; + + #ifdef CONFIG_80211N_HT + ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option; + #endif + + rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i] + , pdvobj->padapters[i]->mlmeextpriv.chandef.chan + , pdvobj->padapters[i]->mlmeextpriv.chandef.bw + , pdvobj->padapters[i]->mlmeextpriv.chandef.offset + , ht_option, 0); + + } +#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */ + rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), parm->ifbmp, 1); +} + +void rtw_core_ap_start(_adapter *padapter, struct createbss_parm *parm) +{ +#define DUMP_ADAPTERS_STATUS 0 + struct dvobj_priv *pdvobj = padapter->dvobj; + int i; + RTW_INFO("%s\n", __func__); + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); + dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); + } + + for (i = 0; i < pdvobj->iface_nums; i++) { + struct mlme_priv *mlme; + + if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) + continue; + + /* update beacon content only if bstart_bss is _TRUE */ + if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE) + continue; + + mlme = &(pdvobj->padapters[i]->mlmepriv); + + #ifdef CONFIG_80211N_HT + if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) { + /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ + mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); + mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; + rtw_update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE, 0); + } + #endif + + rtw_update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE, 0); + } + + /* after chanctx_add & before send bcn */ +#ifndef CONFIG_AP_CMD_DISPR + rtw_hw_start_bss_network(padapter); +#endif + + rtw_scan_abort(padapter, 0); + + _rtw_iface_undersurvey_chk(__func__, padapter); + /* send beacon */ + rtw_hal_set_hwreg(padapter, HW_VAR_RESUME_BCN, NULL); + { +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING) || defined(CONFIG_HWSIM) + + for (i = 0; i < pdvobj->iface_nums; i++) { + if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) + continue; + + if (send_beacon(pdvobj->padapters[i]) == _FAIL) + RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i])); + } +#endif + } +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (MLME_IS_AP(padapter) && padapter->tbtx_capability == _TRUE) { + _set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1); + RTW_INFO("Start token dispatch\n"); + } +#endif +} + void start_bss_network(_adapter *padapter, struct createbss_parm *parm) { #define DUMP_ADAPTERS_STATUS 0 u8 mlme_act = MLME_ACTION_UNKNOWN; - u8 val8; u16 bcn_interval; u32 acparm; struct registry_priv *pregpriv = &padapter->registrypriv; @@ -1654,14 +1628,14 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); struct dvobj_priv *pdvobj = padapter->dvobj; s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE; - u8 u_ch = 0, u_bw, u_offset; - bool set_u_ch; - u8 doiqk = _FALSE; - /* use for check ch bw offset can be allowed or not */ - u8 chbw_allow = _TRUE; + struct rtw_chan_def chdef_to_set = {0}; + u8 do_rfk = _FALSE; int i; u8 ifbmp_ch_changed = 0; - +#ifdef CONFIG_MCC_MODE + struct rtw_phl_com_t *phl_com = GET_PHL_COM(pdvobj); + u8 mcc_sup = phl_com->dev_cap.mcc_sup; +#endif if (parm->req_ch != 0) { /* bypass other setting, go checking ch, bw, offset */ mlme_act = MLME_OPCH_SWITCH; @@ -1682,6 +1656,7 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) } bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; + pmlmeinfo->bcn_interval = bcn_interval; /* check if there is wps ie, */ /* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */ @@ -1702,43 +1677,41 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) /* pmlmeinfo->HT_caps_enable = _TRUE; */ update_hw_ht_param(padapter); - } + } else + pmlmeinfo->HT_enable = _FALSE; #endif /* #CONFIG_80211N_HT */ #ifdef CONFIG_80211AC_VHT if (pmlmepriv->vhtpriv.vht_option) { pmlmeinfo->VHT_enable = _TRUE; update_hw_vht_param(padapter); - } + } else + pmlmeinfo->VHT_enable = _FALSE; #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + if (pmlmepriv->hepriv.he_option) { + pmlmeinfo->HE_enable = _TRUE; + update_hw_he_param(padapter); + } else + pmlmeinfo->HE_enable = _FALSE; +#endif /* CONFIG_80211AX_HE */ + if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at first time */ /* WEP Key will be set before this function, do not clear CAM. */ if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) && !MLME_IS_MESH(padapter) /* mesh group key is set before this function */ ) - flush_all_cam_entry(padapter); /* clear CAM */ + flush_all_cam_entry(padapter, PHL_CMD_DIRECTLY, 0); /* clear CAM */ } - /* set MSR to AP_Mode */ - Set_MSR(padapter, _HW_STATE_AP_); - - /* Set BSSID REG */ - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress); - - /* Set Security */ - val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf; - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); - - /* Beacon Control related register */ - rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); - - rtw_hal_rcr_set_chk_bssid(padapter, mlme_act); +#ifdef CONFIG_RTW_MULTI_AP + rtw_map_config_monitor(padapter, mlme_act); +#endif chbw_decision: ifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp - , req_ch, req_bw, req_offset - , &u_ch, &u_bw, &u_offset, &chbw_allow, &set_u_ch); + , req_ch, req_bw, req_offset, &chdef_to_set); for (i = 0; i < pdvobj->iface_nums; i++) { if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) @@ -1760,188 +1733,32 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp); #endif -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* - * due to check under rtw_ap_chbw_decision - * if under MCC mode, means req channel setting is the same as current channel setting - * if not under MCC mode, mean req channel setting is not the same as current channel setting - */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n" - , FUNC_ADPT_ARG(padapter)); - - goto update_beacon; - - } - } - - /* issue null data to AP for all interface connecting to AP before switch channel setting for softap */ - rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1); -#endif /* CONFIG_MCC_MODE */ - - if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) { - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); - } - - if (set_u_ch) - set_channel_bwmode(padapter, u_ch, u_offset, u_bw); - - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + { + u8 phl_uch = pmlmeext->chandef.chan; + enum channel_width phl_ubw = pmlmeext->chandef.bw; + enum chan_offset phl_uoffset = pmlmeext->chandef.offset; + bool is_chctx_add = false; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); -#ifdef CONFIG_MCC_MODE - /* after set_channel_bwmode for backup IQK */ - if (rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow) == _FAIL) { - /* MCC setting fail, update to buddy's channel */ - rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset); - pnetwork->Configuration.DSConfig = u_ch; - padapter->mlmeextpriv.cur_channel = u_ch; - padapter->mlmeextpriv.cur_bwmode = u_bw; - padapter->mlmeextpriv.cur_ch_offset = u_offset; - - if (ifbmp_ch_changed == 0) { - u8 ht_option = 0; + is_chctx_add = rtw_phl_chanctx_add(dvobj->phl, padapter->phl_role, + &phl_uch, &phl_ubw, &phl_uoffset); -#ifdef CONFIG_80211N_HT - ht_option = padapter->mlmepriv.htpriv.ht_option; -#endif + rtw_hw_update_chan_def(padapter); + rtw_mi_update_union_chan_inf(padapter, phl_uch, phl_uoffset, phl_ubw); - rtw_cfg80211_ch_switch_notify(padapter - , padapter->mlmeextpriv.cur_channel - , padapter->mlmeextpriv.cur_bwmode - , padapter->mlmeextpriv.cur_ch_offset - , ht_option, 0); - } + RTW_INFO("%s => chctx_add:%s\n", __func__, (is_chctx_add) ? "Y" : "N"); + RTW_INFO("Core - CH:%d, BW:%d OFF:%d\n", chdef_to_set.chan, chdef_to_set.bw, chdef_to_set.offset); + RTW_INFO("PHL- CH:%d, BW:%d OFF:%d\n",phl_uch, phl_ubw, phl_uoffset); } -#endif - -#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - for (i = 0; i < pdvobj->iface_nums; i++) { - if (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i]) - continue; - - { - u8 ht_option = 0; - - #ifdef CONFIG_80211N_HT - ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option; - #endif - rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i] - , pdvobj->padapters[i]->mlmeextpriv.cur_channel - , pdvobj->padapters[i]->mlmeextpriv.cur_bwmode - , pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset - , ht_option, 0); - } - } -#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */ - rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), parm->ifbmp, 1); + parm->ifbmp_ch_changed = ifbmp_ch_changed; + parm->ch_to_set = chdef_to_set.chan; + parm->offset_to_set = chdef_to_set.offset; + parm->bw_to_set = chdef_to_set.bw; + parm->do_rfk = do_rfk; - if (DUMP_ADAPTERS_STATUS) { - RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); - dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); - } - -#ifdef CONFIG_MCC_MODE -update_beacon: -#endif - - for (i = 0; i < pdvobj->iface_nums; i++) { - struct mlme_priv *mlme; - - if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) - continue; - - /* update beacon content only if bstart_bss is _TRUE */ - if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE) - continue; - - mlme = &(pdvobj->padapters[i]->mlmepriv); - - #ifdef CONFIG_80211N_HT - if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) { - /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ - mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); - mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; - update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE, 0); - } - #endif - - update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE, 0); - } - - if (mlme_act != MLME_OPCH_SWITCH - && pmlmeext->bstart_bss == _TRUE - ) { -#ifdef CONFIG_SUPPORT_MULTI_BCN - _irqL irqL; - - _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - if (rtw_is_list_empty(&padapter->list)) { - #ifdef CONFIG_FW_HANDLE_TXBCN - padapter->vap_id = rtw_ap_allocate_vapid(pdvobj); - #endif - rtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q)); - pdvobj->nr_ap_if++; - pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if; - } - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - - #ifdef CONFIG_SWTIMER_BASED_TXBCN - rtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if); - rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space)); - #endif /*CONFIG_SWTIMER_BASED_TXBCN*/ - -#endif /*CONFIG_SUPPORT_MULTI_BCN*/ - - #ifdef CONFIG_HW_P0_TSF_SYNC - correct_TSF(padapter, mlme_act); - #endif - } - - rtw_scan_wait_completed(padapter); - - _rtw_iface_undersurvey_chk(__func__, padapter); - /* send beacon */ - ResumeTxBeacon(padapter); - { -#if !defined(CONFIG_INTERRUPT_BASED_TXBCN) -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING) -#ifdef CONFIG_SWTIMER_BASED_TXBCN - if (pdvobj->nr_ap_if == 1 - && mlme_act != MLME_OPCH_SWITCH - ) { - RTW_INFO("start SW BCN TIMER!\n"); - _set_timer(&pdvobj->txbcn_timer, bcn_interval); - } -#else - for (i = 0; i < pdvobj->iface_nums; i++) { - if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) - continue; - - if (send_beacon(pdvobj->padapters[i]) == _FAIL) - RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i])); - } -#endif -#endif -#endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */ - -#ifdef CONFIG_FW_HANDLE_TXBCN - if (mlme_act != MLME_OPCH_SWITCH - && pmlmeext->bstart_bss == _TRUE) - rtw_ap_mbid_bcn_en(padapter, padapter->vap_id); -#endif - } -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (MLME_IS_AP(padapter) && padapter->tbtx_capability == _TRUE) { - _set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1); - RTW_INFO("Start token dispatch\n"); - } -#endif -} +} int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) { @@ -1957,7 +1774,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) u8 channel, network_type; u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01}; u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; - HT_CAP_AMPDU_DENSITY best_ampdu_density; + u8 WIFI_ALLIANCE_OUI[] = {0x50, 0x6f, 0x9a}; + HT_CAP_AMPDU_DENSITY best_ampdu_density = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -2008,7 +1826,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) rtw_ap_check_scan(padapter); - pbss_network->Rssi = 0; + pbss_network->PhyInfo.rssi= 0; _rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN); @@ -2018,9 +1836,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p); /* capability */ - /* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */ - /* cap = le16_to_cpu(cap); */ - cap = RTW_GET_LE16(ie); + p = rtw_get_capability_from_ie(ie); + cap = RTW_GET_LE16(p); /* SSID */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); @@ -2028,10 +1845,6 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len); pbss_network->Ssid.SsidLength = ie_len; -#ifdef CONFIG_P2P - _rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); - padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength; -#endif } #ifdef CONFIG_RTW_MESH @@ -2046,6 +1859,10 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } #endif + /* Parsing extended capabilities IE */ + rtw_parse_ext_cap_ie(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), ie \ + , pbss_network->IELength, _BEACON_IE_OFFSET_); + /* chnnel */ channel = 0; pbss_network->Configuration.Length = 0; @@ -2061,7 +1878,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* parsing ERP_IE */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) { - if(padapter->registrypriv.wireless_mode == WIRELESS_11B ) { + if(padapter->registrypriv.wireless_mode == WLAN_MD_11B) { pbss_network->IELength = pbss_network->IELength - *(p+1) - 2; ret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0); @@ -2227,12 +2044,9 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } psecuritypriv->mfp_opt = mfp_opt; -#ifdef CONFIG_RTW_80211K /* RRM */ update_rm_cap(pbuf, padapter, len, _BEACON_IE_OFFSET_); -#endif /* CONFIG_RTW_80211K */ - /* wmm */ ie_len = 0; pmlmepriv->qospriv.qos_option = 0; @@ -2272,16 +2086,15 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K; struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); -#ifdef CONFIG_RTW_DEBUG if (0) { RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter)); dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); } -#endif /* CONFIG_RTW_DEBUG */ + pHT_caps_ie = p; ht_cap = _TRUE; - network_type |= WIRELESS_11_24N; + network_type |= WLAN_MD_11N; rtw_ht_use_default_setting(padapter); @@ -2321,7 +2134,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) u8 rx_nss = 0; int i; - rx_nss = GET_HAL_RX_NSS(padapter); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); /* RX MCS Bitmask */ switch (rx_nss) { @@ -2338,7 +2151,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R); break; default: - RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss); + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", + GET_HAL_RFPATH(adapter_to_dvobj(padapter)), rx_nss); } for (i = 0; i < 10; i++) *(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; @@ -2358,6 +2172,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* Compressed Steering Number Antennas */ SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1); rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + if (rf_num > 3) + rf_num = 3; SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num); } @@ -2368,17 +2184,18 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* Explicit Compressed Beamforming Feedback Capable */ SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2); rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + if (rf_num > 3) + rf_num = 3; SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num); } #endif /* CONFIG_BEAMFORMING */ _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len); -#ifdef CONFIG_RTW_DEBUG + if (0) { RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter)); dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); } -#endif /* CONFIG_RTW_DEBUG */ } /* parsing HT_INFO_IE */ @@ -2421,28 +2238,32 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) #endif #ifdef CONFIG_80211AC_VHT - pmlmepriv->ori_vht_en = 0; + pmlmepriv->vhtpriv.upper_layer_setting = _FALSE; pmlmepriv->vhtpriv.vht_option = _FALSE; if (pmlmepriv->htpriv.ht_option == _TRUE && pbss_network->Configuration.DSConfig > 14 && REGSTY_IS_11AC_ENABLE(pregistrypriv) && is_supported_vht(pregistrypriv->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + && RFCTL_REG_EN_11AC(rfctl) ) { - /* Parsing VHT CAP IE */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + /* Parsing VHT_CAP_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, + &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) vht_cap = _TRUE; + else + RTW_INFO(FUNC_ADPT_FMT" No vht_capability_ie from hostapd/wpa_supplicant\n", FUNC_ADPT_ARG(padapter)); - /* Parsing VHT OPERATION IE */ - - if (vht_cap == _TRUE - && MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */ - ) { - rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_); - pmlmepriv->ori_vht_en = 1; + /* Update VHT related IEs */ + if (vht_cap == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" VHT IEs is configured by hostapd/wpa_supplicant\n", FUNC_ADPT_ARG(padapter)); + pmlmepriv->vhtpriv.upper_layer_setting = _TRUE; pmlmepriv->vhtpriv.vht_option = _TRUE; + + rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, + pbss_network->IELength - _BEACON_IE_OFFSET_); + rtw_check_vht_ies(padapter, pbss_network); } else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { rtw_vht_ies_detach(padapter, pbss_network); rtw_vht_ies_attach(padapter, pbss_network); @@ -2453,40 +2274,89 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) rtw_vht_ies_detach(padapter, pbss_network); #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + pmlmepriv->hepriv.he_option = _FALSE; + + /* An HE STA is also a VHT STA if operating in the 5 GHz band */ + /* An HE STA is also a HT STA in the 2GHz band */ + if (REGSTY_IS_11AX_ENABLE(pregistrypriv) + && is_supported_he(pregistrypriv->wireless_mode) + && RFCTL_REG_EN_11AX(rfctl) + && ((channel > 14 && pmlmepriv->vhtpriv.vht_option == _TRUE) || + (channel <= 14 && pmlmepriv->htpriv.ht_option == _TRUE)) + ) { + u8 he_cap = _FALSE; + u8 he_cap_eid_ext = WLAN_EID_EXTENSION_HE_CAPABILITY; + + p = rtw_get_ie_ex(ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_, + WLAN_EID_EXTENSION, &he_cap_eid_ext, 1, NULL, &ie_len); + if (p && ie_len > 0) + he_cap = _TRUE; + + /* If He capability is in beacon IE, enable he_option */ + pmlmepriv->hepriv.he_option = he_cap; + rtw_he_use_default_setting(padapter); + if (REGSTY_IS_11AX_AUTO(pregistrypriv)) { + rtw_he_ies_detach(padapter, pbss_network); + rtw_he_ies_attach(padapter, pbss_network); + } + } + if (pmlmepriv->hepriv.he_option == _FALSE) + rtw_he_ies_detach(padapter, pbss_network); +#endif + #ifdef CONFIG_80211N_HT if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode) && - pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 && - pbss_network->IELength + 10 <= MAX_IE_SZ) { - uint len = 0; + pbss_network->Configuration.DSConfig <= 14 /*&& padapter->registrypriv.wifi_spec == 1*/) { - SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); - pmlmepriv->ext_capab_ie_len = 10; - rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); - pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + #ifdef CONFIG_RTW_WNM + rtw_wnm_add_btm_ext_cap(pmlmepriv->ext_capab_ie_data, + &(pmlmepriv->ext_capab_ie_len)); + #endif + #ifdef CONFIG_RTW_MBO + rtw_mbo_add_internw_ext_cap(pmlmepriv->ext_capab_ie_data, + &(pmlmepriv->ext_capab_ie_len)); + #endif + rtw_add_ext_cap_info(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), BSS_COEXT); + rtw_update_ext_cap_ie(pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len, pbss_network->IEs, \ + &(pbss_network->IELength), _BEACON_IE_OFFSET_); } #endif /* CONFIG_80211N_HT */ - pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); - - rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ - , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1); - rtw_warn_on(pmlmepriv->ori_ch == 0); - - { - /* alloc sta_info for ap itself */ - - struct sta_info *sta; +#ifdef CONFIG_RTW_80211K + padapter->rmpriv.enable = _FALSE; + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_RMEnabledCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len) { + RTW_INFO("[%s]Get EID_RMEnabledCapability, len = %d\n", __func__, ie_len); + padapter->rmpriv.enable = _TRUE; + _rtw_memcpy(padapter->rmpriv.rm_en_cap_def, p + 2, ie_len); + } +#endif /* CONFIG_RTW_80211K */ - sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); - if (!sta) { - sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); - if (sta == NULL) - return _FAIL; +#ifdef CONFIG_RTW_MBO + ie_len = 0; + pmlmepriv->mbopriv.enable = _FALSE; + for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) { + p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if ((p) && (_rtw_memcmp(p + 2, WIFI_ALLIANCE_OUI, 3)) && (*(p+5) == MBO_OUI_TYPE)) { + /* find MBO-OCE information element */ + pmlmepriv->mbopriv.enable = _TRUE; + rtw_mbo_ie_handler(padapter, &pmlmepriv->mbopriv, p + 6, ie_len - 4); + break; } + if ((p == NULL) || (ie_len == 0)) + break; } +#endif /* CONFIG_RTW_MBO */ + + pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); + + rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ + , &pmlmepriv->ori_chandef.chan, (u8 *)&pmlmepriv->ori_chandef.bw, (u8 *)&pmlmepriv->ori_chandef.offset, 1, 1); + rtw_warn_on(pmlmepriv->ori_chandef.chan == 0); - rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK); + ret = rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK); { int sk_band = RTW_GET_SCAN_BAND_SKIP(padapter); @@ -2494,12 +2364,10 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) RTW_CLR_SCAN_BAND_SKIP(padapter, sk_band); } - rtw_indicate_connect(padapter); - - pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */ - - /* update bc/mc sta_info */ - /* update_bmc_sta(padapter); */ + if (ret) { + rtw_indicate_connect(padapter); + pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */ + } return ret; @@ -2512,7 +2380,6 @@ void rtw_macaddr_acl_init(_adapter *adapter, u8 period) struct wlan_acl_pool *acl; _queue *acl_node_q; int i; - _irqL irqL; if (period >= RTW_ACL_PERIOD_NUM) { rtw_warn_on(1); @@ -2524,7 +2391,7 @@ void rtw_macaddr_acl_init(_adapter *adapter, u8 period) _rtw_spinlock_init(&(acl_node_q->lock)); - _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinlock_bh(&(acl_node_q->lock)); _rtw_init_listhead(&(acl_node_q->queue)); acl->num = 0; acl->mode = RTW_ACL_MODE_DISABLED; @@ -2532,7 +2399,7 @@ void rtw_macaddr_acl_init(_adapter *adapter, u8 period) _rtw_init_listhead(&acl->aclnode[i].list); acl->aclnode[i].valid = _FALSE; } - _exit_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinunlock_bh(&(acl_node_q->lock)); } static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only) @@ -2540,7 +2407,6 @@ static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_onl struct sta_priv *stapriv = &adapter->stapriv; struct wlan_acl_pool *acl; _queue *acl_node_q; - _irqL irqL; _list *head, *list; struct rtw_wlan_acl_node *acl_node; @@ -2552,7 +2418,7 @@ static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_onl acl = &stapriv->acl_list[period]; acl_node_q = &acl->acl_node_q; - _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinlock_bh(&(acl_node_q->lock)); head = get_list_head(acl_node_q); list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { @@ -2565,7 +2431,7 @@ static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_onl acl->num--; } } - _exit_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinunlock_bh(&(acl_node_q->lock)); if (!clear_only) _rtw_spinlock_free(&(acl_node_q->lock)); @@ -2604,7 +2470,6 @@ void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode) int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) { - _irqL irqL; _list *list, *head; u8 existed = 0; int i = -1, ret = 0; @@ -2622,7 +2487,7 @@ int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) acl = &stapriv->acl_list[period]; acl_node_q = &acl->acl_node_q; - _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinlock_bh(&(acl_node_q->lock)); head = get_list_head(acl_node_q); list = get_next(head); @@ -2662,7 +2527,7 @@ int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) } release_lock: - _exit_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinunlock_bh(&(acl_node_q->lock)); if (!existed && (i < 0 || i >= NUM_ACL)) ret = -1; @@ -2677,7 +2542,6 @@ int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) { - _irqL irqL; _list *list, *head; int ret = 0; struct rtw_wlan_acl_node *acl_node; @@ -2695,7 +2559,7 @@ int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) acl = &stapriv->acl_list[period]; acl_node_q = &acl->acl_node_q; - _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinlock_bh(&(acl_node_q->lock)); head = get_list_head(acl_node_q); list = get_next(head); @@ -2714,7 +2578,7 @@ int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) } } - _exit_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinunlock_bh(&(acl_node_q->lock)); RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n" , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr) @@ -2725,10 +2589,87 @@ int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) return ret; } #endif /* CONFIG_RTW_MACADDR_ACL */ +#ifdef CONFIG_CMD_DISP +u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk) +{ + struct set_stakey_parm param; + u8 res = _SUCCESS; + + _rtw_memcpy(param.addr, addr, ETH_ALEN); + param.algorithm = alg; + param.keyid = keyid; + if (!!(alg & _SEC_TYPE_256_)) + _rtw_memcpy(param.key, key, 32); + else + _rtw_memcpy(param.key, key, 16); + param.gk = gk; + + set_stakey_hdl(adapter, ¶m, PHL_CMD_NO_WAIT, 0); +exit: + return res; +} + +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +{ + return rtw_ap_set_sta_key(padapter + , psta->phl_sta->mac_addr + , psta->dot118021XPrivacy + , psta->dot118021x_UncstKey.skey + , 0 + , 0 + ); +} + +static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx) +{ + u8 keylen; + struct setkey_parm setkeyparm; + int res = _SUCCESS; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + _rtw_memset(&setkeyparm, 0, sizeof(struct setkey_parm)); + + setkeyparm.keyid = (u8)keyid; + if (is_wep_enc(alg)) + padapter->securitypriv.key_mask |= BIT(setkeyparm.keyid); + + setkeyparm.algorithm = alg; + + setkeyparm.set_tx = set_tx; + + switch (alg) { + case _WEP40_: + keylen = 5; + break; + case _WEP104_: + keylen = 13; + break; + case _GCMP_256_: + case _CCMP_256_: + keylen = 32; + break; + case _TKIP_: + case _TKIP_WTMIC_: + case _AES_: + case _GCMP_: + #ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + #endif + default: + keylen = 16; + } + _rtw_memcpy(&(setkeyparm.key[0]), key, keylen); + setkey_hdl(padapter, &setkeyparm, PHL_CMD_NO_WAIT, 0); + +exit: + return res; +} +#else /* CONFIG_FSM */ u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk) { - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct cmd_obj *cmd; struct set_stakey_parm *param; u8 res = _SUCCESS; @@ -2738,6 +2679,7 @@ u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, res = _FAIL; goto exit; } + cmd->padapter = adapter; param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); if (param == NULL) { @@ -2766,7 +2708,7 @@ u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) { return rtw_ap_set_sta_key(padapter - , psta->cmn.mac_addr + , psta->phl_sta->mac_addr , psta->dot118021XPrivacy , psta->dot118021x_UncstKey.skey , 0 @@ -2779,7 +2721,7 @@ static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set u8 keylen; struct cmd_obj *pcmd; struct setkey_parm *psetkeyparm; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(padapter)->cmdpriv); int res = _SUCCESS; /* RTW_INFO("%s\n", __FUNCTION__); */ @@ -2789,6 +2731,8 @@ static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set res = _FAIL; goto exit; } + pcmd->padapter = padapter; + psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm)); if (psetkeyparm == NULL) { rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); @@ -2821,13 +2765,16 @@ static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set case _TKIP_WTMIC_: case _AES_: case _GCMP_: + #ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + #endif default: keylen = 16; } _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); - pcmd->cmdcode = CMD_SET_KEY; /*_SetKey_CMD_;*/ + pcmd->cmdcode = CMD_SET_KEY; /*_SetKey_CMD_*/ pcmd->parmbuf = (u8 *)psetkeyparm; pcmd->cmdsz = (sizeof(struct setkey_parm)); pcmd->rsp = NULL; @@ -2842,7 +2789,7 @@ static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set return res; } - +#endif int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) { RTW_INFO("%s\n", __FUNCTION__); @@ -2873,7 +2820,6 @@ int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) { #define HIQ_XMIT_COUNTS (6) - _irqL irqL; struct sta_info *psta_bmc; _list *xmitframe_plist, *xmitframe_phead; struct xmit_frame *pxmitframe = NULL; @@ -2891,7 +2837,7 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) return H2C_SUCCESS; - _enter_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinlock_bh(&pxmitpriv->lock); if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { int tx_counts = 0; @@ -2924,9 +2870,9 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) pxmitframe->attrib.triggered = 1; if (xmitframe_hiq_filter(pxmitframe) == _TRUE) - pxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/ + pxmitframe->attrib.qsel = rtw_hal_get_qsel(padapter,QSLT_HIGH_ID);/*HIQ*/ - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); if (tx_counts == HIQ_XMIT_COUNTS) break; @@ -2951,7 +2897,7 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) } } - _exit_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinunlock_bh(&pxmitpriv->lock); #if 0 /* HIQ Check */ @@ -2975,14 +2921,14 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type); + RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->phl_sta->mac_addr), sta_info_type); #ifdef CONFIG_80211N_HT if (sta_info_type & STA_INFO_UPDATE_BW) { if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) { if (pmlmepriv->sw_to_20mhz) { - psta->cmn.bw_mode = CHANNEL_WIDTH_20; - /*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/ + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; + /*psta->htpriv.ch_offset = CHAN_OFFSET_NO_EXT;*/ psta->htpriv.sgi_40m = _FALSE; } else { /*TODO: Switch back to 40MHZ?80MHZ*/ @@ -3015,27 +2961,6 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, } -static void update_bcn_ext_capab_ie(_adapter *padapter) -{ - sint ie_len = 0; - unsigned char *pbuf; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); - u8 *ie = pnetwork->IEs; - u8 null_extcap_data[8] = {0}; - - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) - rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_); - - if ((pmlmepriv->ext_capab_ie_len > 0) && - (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE)) - rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len); - -} - static void update_bcn_erpinfo_ie(_adapter *padapter) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -3111,7 +3036,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter) pht_info = (struct HT_info_element *)(p + 2); /* for STA Channel Width/Secondary Channel Offset*/ - if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) { + if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->chandef.chan <= 14)) { if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE) || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) { SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0); @@ -3132,12 +3057,12 @@ static void update_bcn_htinfo_ie(_adapter *padapter) if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE) && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) { - if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) { + if (pmlmeext->chandef.bw >= CHANNEL_WIDTH_40) { SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1); SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, - (pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ? + (pmlmeext->chandef.offset == CHAN_OFFSET_UPPER) ? HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW); pmlmepriv->sw_to_20mhz = 0; @@ -3228,7 +3153,7 @@ static void update_bcn_wps_ie(_adapter *padapter) if (pbackup_remainder_ie) rtw_mfree(pbackup_remainder_ie, remainder_ielen); - /* deal with the case without set_tx_beacon_cmd() in update_beacon() */ + /* deal with the case without set_tx_beacon_cmd() in rtw_update_beacon() */ #if defined(CONFIG_INTERRUPT_BASED_TXBCN) || defined(CONFIG_PCI_HCI) if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { u8 sr = 0; @@ -3250,6 +3175,74 @@ static void update_bcn_p2p_ie(_adapter *padapter) } +static u8 update_csa_ie(_adapter *padapter) +{ + u8 update = _FALSE; +#ifdef CONFIG_ECSA_PHL + struct core_ecsa_info *ecsa_info = &(padapter->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 csa_data[CSA_IE_LEN] = {0}; + u8 csa_ch = ecsa_param->new_chan_def.chan; + u8 csa_count = ecsa_param->count; + u8 *ies = pnetwork->IEs + _BEACON_IE_OFFSET_; + sint ies_len = pnetwork->IELength - _BEACON_IE_OFFSET_; + u8 *csa_ie; + sint csa_ie_len; + + if (!CHK_ECSA_STATE(padapter, ECSA_ST_SW_START)) + return update; + + csa_ie = rtw_get_ie(ies, WLAN_EID_CHANNEL_SWITCH, &csa_ie_len, ies_len); + + if (csa_ie == NULL) { + if (csa_count > 0) { + /* add new CSA IE */ + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch=%u, count=%u, add CSA IE\n", + FUNC_ADPT_ARG(padapter), csa_ch, csa_count); + + csa_data[CSA_SWITCH_MODE] = ecsa_param->mode; + csa_data[CSA_NEW_CH] = csa_ch; + csa_data[CSA_SWITCH_COUNT] = csa_count; + rtw_add_bcn_ie(padapter, pnetwork, WLAN_EID_CHANNEL_SWITCH, csa_data, CSA_IE_LEN); + update = _TRUE; + } else if (csa_ch > 0) { + /* count = 0, means switching channel immediately */ + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch=%d, count=0, switch channel immediately\n", + FUNC_ADPT_ARG(padapter), csa_ch); + SET_ECSA_STATE(padapter, ECSA_ST_SW_DONE); + } + } else if (csa_ie && csa_ie_len == CSA_IE_LEN) { + if (csa_count > 0) { + /* update CSA IE */ + #ifdef DBG_CSA + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch=%u, count=%u, update CSA IE\n", + FUNC_ADPT_ARG(padapter), csa_ch, csa_count); + #endif + + csa_ie[2 + CSA_SWITCH_COUNT] = csa_count; + } else { + /* remove CSA IE */ + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch=%u, count=%u, remove CSA IE\n", + FUNC_ADPT_ARG(padapter), csa_ch, csa_count); + + rtw_remove_bcn_ie(padapter, pnetwork, WLAN_EID_CHANNEL_SWITCH); + SET_ECSA_STATE(padapter, ECSA_ST_SW_DONE); + } + update = _TRUE; + } else { + RTW_ERR("CSA : "FUNC_ADPT_FMT" unexpected case\n", FUNC_ADPT_ARG(padapter)); + } + + if (ecsa_param->count > 0) + ecsa_param->count--; + +#endif /* CONFIG_ECSA_PHL */ + return update; +} + static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui) { RTW_INFO("%s\n", __FUNCTION__); @@ -3270,7 +3263,6 @@ static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui) void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag) { - _irqL irqL; struct mlme_priv *pmlmepriv; struct mlme_ext_priv *pmlmeext; bool updated = 1; /* treat as upadated by default */ @@ -3284,7 +3276,7 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, cons if (pmlmeext->bstart_bss == _FALSE) return; - _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->bcn_update_lock); switch (ie_id) { case _TIM_IE_: @@ -3307,10 +3299,6 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, cons update_bcn_htinfo_ie(padapter); break; - case _EXT_CAP_IE_: - update_bcn_ext_capab_ie(padapter); - break; - #ifdef CONFIG_RTW_MESH case WLAN_EID_MESH_CONFIG: updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network)); @@ -3318,6 +3306,9 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, cons updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network)); break; #endif + case WLAN_EID_CHANNEL_SWITCH: + updated = update_csa_ie(padapter); + break; case _VENDOR_SPECIFIC_IE_: update_bcn_vendor_spec_ie(padapter, oui); @@ -3331,7 +3322,7 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, cons if (updated) pmlmepriv->update_bcn = _TRUE; - _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->bcn_update_lock); #ifndef CONFIG_INTERRUPT_BASED_TXBCN #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING) @@ -3405,7 +3396,7 @@ void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_l if (beacon_updated) { - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); + rtw_update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW); } @@ -3532,12 +3523,11 @@ void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type { /* update associcated stations cap. */ if (updated == _TRUE) { - _irqL irqL; _list *phead, *plist; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -3551,7 +3541,7 @@ void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type associated_stainfo_update(padapter, psta, sta_info_type); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); } @@ -3583,7 +3573,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble++; - if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + if ((pmlmeext->cur_wireless_mode > WLAN_MD_11B) && (pmlmepriv->num_sta_no_short_preamble == 1)) beacon_updated = _TRUE; } @@ -3593,7 +3583,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble--; - if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + if ((pmlmeext->cur_wireless_mode > WLAN_MD_11B) && (pmlmepriv->num_sta_no_short_preamble == 0)) beacon_updated = _TRUE; } @@ -3616,7 +3606,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 1) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); } } @@ -3628,7 +3618,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); } } @@ -3652,7 +3642,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time++; - if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + if ((pmlmeext->cur_wireless_mode > WLAN_MD_11B) && (pmlmepriv->num_sta_no_short_slot_time == 1)) beacon_updated = _TRUE; } @@ -3662,7 +3652,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time--; - if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + if ((pmlmeext->cur_wireless_mode > WLAN_MD_11B) && (pmlmepriv->num_sta_no_short_slot_time == 0)) beacon_updated = _TRUE; } @@ -3675,7 +3665,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n", - MAC_ARG(psta->cmn.mac_addr), ht_capab); + MAC_ARG(psta->phl_sta->mac_addr), ht_capab); if (psta->no_ht_set) { psta->no_ht_set = 0; @@ -3689,7 +3679,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) } RTW_INFO("%s STA " MAC_FMT " - no " "greenfield, num of non-gf stations %d\n", - __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + __FUNCTION__, MAC_ARG(psta->phl_sta->mac_addr), pmlmepriv->num_sta_ht_no_gf); } @@ -3700,7 +3690,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) } RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, " "num of 20MHz HT STAs %d\n", - __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + __FUNCTION__, MAC_ARG(psta->phl_sta->mac_addr), pmlmepriv->num_sta_ht_20mhz); } @@ -3709,7 +3699,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) psta->ht_40mhz_intolerant = 1; pmlmepriv->num_sta_40mhz_intolerant++; RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ", - __FUNCTION__, MAC_ARG(psta->cmn.mac_addr)); + __FUNCTION__, MAC_ARG(psta->phl_sta->mac_addr)); } } else { @@ -3720,14 +3710,14 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->htpriv.ht_option == _TRUE) { RTW_INFO("%s STA " MAC_FMT " - no HT, num of non-HT stations %d\n", - __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + __FUNCTION__, MAC_ARG(psta->phl_sta->mac_addr), pmlmepriv->num_sta_no_ht); } } if (rtw_ht_operation_update(padapter) > 0) { - update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0); beacon_updated = _TRUE; } } @@ -3737,7 +3727,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (MLME_IS_MESH(padapter)) { struct sta_priv *pstapriv = &padapter->stapriv; - update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0); + rtw_update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0); if (pstapriv->asoc_list_cnt == 1) _set_timer(&padapter->mesh_atlm_param_req_timer, 0); beacon_updated = _TRUE; @@ -3745,7 +3735,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) #endif if (beacon_updated) - update_beacon(padapter, 0xFF, NULL, _TRUE, 0); + rtw_update_beacon(padapter, 0xFF, NULL, _TRUE, 0); /* update associcated stations cap. */ associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); @@ -3764,16 +3754,16 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) if (!psta) return beacon_updated; - if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid)) { + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); beacon_updated = _TRUE; - update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0); } if (psta->no_short_preamble_set) { psta->no_short_preamble_set = 0; pmlmepriv->num_sta_no_short_preamble--; - if (pmlmeext->cur_wireless_mode > WIRELESS_11B + if (pmlmeext->cur_wireless_mode > WLAN_MD_11B && pmlmepriv->num_sta_no_short_preamble == 0) beacon_updated = _TRUE; } @@ -3783,14 +3773,14 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_non_erp--; if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0); } } if (psta->no_short_slot_time_set) { psta->no_short_slot_time_set = 0; pmlmepriv->num_sta_no_short_slot_time--; - if (pmlmeext->cur_wireless_mode > WIRELESS_11B + if (pmlmeext->cur_wireless_mode > WLAN_MD_11B && pmlmepriv->num_sta_no_short_slot_time == 0) beacon_updated = _TRUE; } @@ -3820,14 +3810,14 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) } if (rtw_ht_operation_update(padapter) > 0) { - update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0); } #endif /* CONFIG_80211N_HT */ #ifdef CONFIG_RTW_MESH if (MLME_IS_MESH(padapter)) { - update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0); + rtw_update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0); if (pstapriv->asoc_list_cnt == 0) _cancel_timer_ex(&padapter->mesh_atlm_param_req_timer); beacon_updated = _TRUE; @@ -3835,7 +3825,7 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) #endif if (beacon_updated == _TRUE) - update_beacon(padapter, 0xFF, NULL, _TRUE, 0); + rtw_update_beacon(padapter, 0xFF, NULL, _TRUE, 0); #if 0 /* update associated stations cap. */ @@ -3848,26 +3838,31 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) } -u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue) +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue, u8 disassoc) { - _irqL irqL; u8 beacon_updated = _FALSE; if (!psta) return beacon_updated; + RTW_INFO("%s sta "MAC_FMT"\n", __func__, MAC_ARG(psta->phl_sta->mac_addr)); + if (active == _TRUE) { #ifdef CONFIG_80211N_HT /* tear down Rx AMPDU */ - send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ + send_delba(padapter, 0, psta->phl_sta->mac_addr);/* recipient */ /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ + send_delba(padapter, 1, psta->phl_sta->mac_addr);/* */ /* originator */ #endif /* CONFIG_80211N_HT */ - if (!MLME_IS_MESH(padapter)) - issue_deauth(padapter, psta->cmn.mac_addr, reason); + if (!MLME_IS_MESH(padapter)) { + if (disassoc == _TRUE) + issue_disassoc(padapter, psta->phl_sta->mac_addr, reason); + else + issue_deauth(padapter, psta->phl_sta->mac_addr, reason); + } } #ifdef CONFIG_RTW_MESH @@ -3875,18 +3870,16 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso rtw_mesh_path_flush_by_nexthop(psta); #endif -#ifdef CONFIG_BEAMFORMING - beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1); -#endif - #ifdef CONFIG_80211N_HT psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ #endif + /* clear cam entry / key */ + rtw_clearstakey_cmd(padapter, psta, enqueue); - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); psta->state &= ~(WIFI_ASOC_STATE | WIFI_UNDER_KEY_HANDSHAKE); #ifdef CONFIG_IOCTL_CFG80211 @@ -3895,13 +3888,14 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso psta->pauth_frame = NULL; psta->auth_len = 0; } + if (psta->passoc_req && psta->assoc_req_len > 0) { - rtw_mfree(psta->passoc_req , psta->assoc_req_len); + rtw_mfree(psta->passoc_req, psta->assoc_req_len); psta->passoc_req = NULL; psta->assoc_req_len = 0; } #endif /* CONFIG_IOCTL_CFG80211 */ - _exit_critical_bh(&psta->lock, &irqL); + _rtw_spinunlock_bh(&psta->lock); if (!MLME_IS_MESH(padapter)) { #ifdef CONFIG_RTW_WDS @@ -3910,9 +3904,9 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso #ifdef CONFIG_IOCTL_CFG80211 #ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->phl_sta->mac_addr, reason); #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->phl_sta->mac_addr, reason); #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */ #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ @@ -3923,18 +3917,14 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); - report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE); - - /* clear cam entry / key */ - rtw_clearstakey_cmd(padapter, psta, enqueue); - + report_del_sta_event(padapter, psta->phl_sta->mac_addr, reason, enqueue, _FALSE); + return beacon_updated; } int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) { - _irqL irqL; _list *phead, *plist; int ret = 0; struct sta_info *psta = NULL; @@ -3949,7 +3939,7 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) RTW_INFO(FUNC_NDEV_FMT" with ch:%u, offset:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset); - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -3958,10 +3948,10 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); plist = get_next(plist); - issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset); + issue_action_spct_ch_switch(padapter, psta->phl_sta->mac_addr, new_ch, ch_offset); psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset); @@ -3970,7 +3960,6 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) int rtw_sta_flush(_adapter *padapter, bool enqueue) { - _irqL irqL; _list *phead, *plist; int ret = 0; struct sta_info *psta = NULL; @@ -3983,10 +3972,8 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return ret; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); - /* pick sta from sta asoc_queue */ - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { @@ -4009,16 +3996,18 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) else rtw_warn_on(1); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); + + RTW_INFO(FUNC_NDEV_FMT" flush_num:%d\n", FUNC_NDEV_ARG(padapter->pnetdev), flush_num); /* call ap_free_sta() for each sta picked */ for (i = 0; i < flush_num; i++) { u8 sta_addr[ETH_ALEN]; psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); - _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(sta_addr, psta->phl_sta->mac_addr, ETH_ALEN); - ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue); + ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue, _FALSE); #ifdef CONFIG_RTW_MESH if (MLME_IS_MESH(padapter)) rtw_mesh_expire_peer(padapter, sta_addr); @@ -4075,15 +4064,20 @@ void sta_info_update(_adapter *padapter, struct sta_info *psta) psta->vhtpriv.vht_option = _FALSE; #endif +#ifdef CONFIG_80211AX_HE + /* update 802.11AX he cap. */ + if (WLAN_STA_HE & flags) + psta->hepriv.he_option = _TRUE; + else + psta->hepriv.he_option = _FALSE; + + if (pmlmepriv->hepriv.he_option == _FALSE) + psta->hepriv.he_option = _FALSE; +#endif + update_sta_info_apmode(padapter, psta); } -/* called >= TSR LEVEL for USB or SDIO Interface*/ -void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) -{ - if (psta->state & WIFI_ASOC_STATE) - rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */ -} /* restore hw setting from sw data structures */ void rtw_ap_restore_network(_adapter *padapter) { @@ -4091,7 +4085,6 @@ void rtw_ap_restore_network(_adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; struct security_priv *psecuritypriv = &(padapter->securitypriv); - _irqL irqL; _list *phead, *plist; u8 chk_alive_num = 0; char chk_alive_list[NUM_STA]; @@ -4102,7 +4095,11 @@ void rtw_ap_restore_network(_adapter *padapter) , RTW_CMDF_DIRECTLY ); - set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + set_channel_bwmode(padapter, + pmlmeext->chandef.chan, + pmlmeext->chandef.offset, + pmlmeext->chandef.bw, + _FALSE); rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY); @@ -4112,7 +4109,7 @@ void rtw_ap_restore_network(_adapter *padapter) rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE); } - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -4128,16 +4125,24 @@ void rtw_ap_restore_network(_adapter *padapter) chk_alive_list[chk_alive_num++] = stainfo_offset; } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); for (i = 0; i < chk_alive_num; i++) { psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); - if (psta == NULL) + if (psta == NULL){ RTW_INFO(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter)); - else if (psta->state & WIFI_ASOC_STATE) { + } else if (psta->state & WIFI_ASOC_STATE) { rtw_sta_media_status_rpt(padapter, psta, 1); - Update_RA_Entry(padapter, psta); + /* + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(adapter)->phl, + sta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_DIRECTLY, + 0); + */ /* pairwise key */ /* per sta pairwise key and settings */ if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || @@ -4156,7 +4161,9 @@ void start_ap_mode(_adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#ifdef CONFIG_CONCURRENT_MODE struct security_priv *psecuritypriv = &padapter->securitypriv; +#endif pmlmepriv->update_bcn = _FALSE; @@ -4193,7 +4200,9 @@ void start_ap_mode(_adapter *padapter) _rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data)); pmlmepriv->ext_capab_ie_len = 0; +#ifdef CONFIG_CONCURRENT_MODE psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID; +#endif for (i = 0 ; i < pstapriv->max_aid; i++) pstapriv->sta_aid[i] = NULL; @@ -4203,17 +4212,8 @@ void start_ap_mode(_adapter *padapter) rtw_wds_pathtbl_init(padapter); #endif - psta = rtw_get_bcmc_stainfo(padapter); - /*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ - if (psta) - rtw_free_stainfo(padapter, psta); - /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ - - rtw_init_bcmc_stainfo(padapter); - if (rtw_mi_get_ap_num(padapter)) RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G); - } void stop_ap_mode(_adapter *padapter) @@ -4222,10 +4222,8 @@ void stop_ap_mode(_adapter *padapter) struct sta_info *psta = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#ifdef CONFIG_SUPPORT_MULTI_BCN - struct dvobj_priv *pdvobj = padapter->dvobj; - _irqL irqL; -#endif + int chanctx_num = 0; + struct rtw_chan_def chan_def = {0}; RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter)); @@ -4264,15 +4262,6 @@ void stop_ap_mode(_adapter *padapter) /* free_assoc_sta_resources */ rtw_free_all_stainfo(padapter); - psta = rtw_get_bcmc_stainfo(padapter); - if (psta) { - rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(padapter, psta); - /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ - } - - pmlmepriv->ap_isolate = 0; #ifdef CONFIG_RTW_WDS adapter_set_use_wds(padapter, 0); #endif @@ -4281,48 +4270,20 @@ void stop_ap_mode(_adapter *padapter) #endif rtw_free_mlme_priv_ie_data(pmlmepriv); -#ifdef CONFIG_SUPPORT_MULTI_BCN - if (pmlmeext->bstart_bss == _TRUE) { - #ifdef CONFIG_FW_HANDLE_TXBCN - u8 free_apid = CONFIG_LIMITED_AP_NUM; - #endif - - _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - pdvobj->nr_ap_if--; - if (pdvobj->nr_ap_if > 0) - pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if; - else - pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; - #ifdef CONFIG_FW_HANDLE_TXBCN - rtw_ap_release_vapid(pdvobj, padapter->vap_id); - free_apid = padapter->vap_id; - padapter->vap_id = CONFIG_LIMITED_AP_NUM; - #endif - rtw_list_delete(&padapter->list); - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - #ifdef CONFIG_FW_HANDLE_TXBCN - rtw_ap_mbid_bcn_dis(padapter, free_apid); - #endif - - #ifdef CONFIG_SWTIMER_BASED_TXBCN - rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space)); - - if (pdvobj->nr_ap_if == 0) - _cancel_timer_ex(&pdvobj->txbcn_timer); - #endif - } -#endif - pmlmeext->bstart_bss = _FALSE; rtw_hal_rcr_set_chk_bssid(padapter, self_action); - -#ifdef CONFIG_HW_P0_TSF_SYNC - correct_TSF(padapter, self_action); +#ifdef CONFIG_RTW_MULTI_AP + rtw_map_config_monitor(padapter, self_action); #endif +#if 0 + chanctx_num = rtw_phl_chanctx_del(adapter_to_dvobj(padapter)->phl, + padapter->phl_role, &chan_def); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */ + if (chanctx_num && chan_def.chan != 0) { + set_channel_bwmode(padapter, chan_def.chan, chan_def.offset, chan_def.bw, _FALSE); + rtw_mi_update_union_chan_inf(padapter, chan_def.chan, chan_def.offset, chan_def.bw); + } #endif #ifdef CONFIG_RTW_WDS @@ -4333,12 +4294,51 @@ void stop_ap_mode(_adapter *padapter) #endif /* CONFIG_NATIVEAP_MLME */ +void rtw_ap_update_clients_rainfo(struct _ADAPTER *a, enum phl_cmd_type flag) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct mlme_ext_priv *pmlmeext = &(a->mlmeextpriv); + struct sta_priv *pstapriv = &a->stapriv; + struct sta_info *psta; + const struct sta_info *ap_self_psta = rtw_get_stainfo(pstapriv, a->phl_role->mac_addr); + _list *plist, *phead; + u8 i; + + /* update RA mask of all clients */ + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + /* no need to update RA info of ap self */ + if (psta && psta != ap_self_psta) { + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; + rtw_phl_cmd_change_stainfo(GET_PHL_INFO(d), + psta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + flag, + 0); + } + } + } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); +} + void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset) { #define UPDATE_VHT_CAP 1 #define UPDATE_HT_CAP 1 #ifdef CONFIG_80211AC_VHT struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; +#endif +#ifdef CONFIG_80211AX_HE + struct he_priv *hepriv = &adapter->mlmepriv.hepriv; #endif { u8 *p; @@ -4361,6 +4361,12 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, change_band_update_ie(adapter, bss, ch); } +#ifdef CONFIG_80211AX_HE + if (hepriv->he_option == _TRUE) { + /* CONFIG_80211AX_HE_TODO */ + } +#endif + #ifdef CONFIG_80211AC_VHT if (vhtpriv->vht_option == _TRUE) { u8 *vht_cap_ie, *vht_op_ie; @@ -4369,7 +4375,7 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); - center_freq = rtw_get_center_ch(ch, bw, offset); + center_freq = rtw_phl_get_center_ch(ch, bw, offset); /* update vht cap ie */ if (vht_cap_ie && vht_cap_ielen) { @@ -4389,10 +4395,12 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, /* update vht op ie */ if (vht_op_ie && vht_op_ielen) { if (bw < CHANNEL_WIDTH_80) { + RTW_INFO(FUNC_ADPT_FMT" update VHT 20/40M\n", FUNC_ADPT_ARG(adapter)); SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); } else if (bw == CHANNEL_WIDTH_80) { + RTW_INFO(FUNC_ADPT_FMT" update VHT 80M, center_freq = %u\n", FUNC_ADPT_ARG(adapter), center_freq); SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); @@ -4436,16 +4444,16 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, if (ht_op_ie && ht_op_ielen) { SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch); switch (offset) { - case HAL_PRIME_CHNL_OFFSET_LOWER: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA); + case CHAN_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, IEEE80211_SCA); break; - case HAL_PRIME_CHNL_OFFSET_UPPER: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB); + case CHAN_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, IEEE80211_SCB); break; - case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + case CHAN_OFFSET_NO_EXT: default: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN); break; + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, IEEE80211_SCN); } if (bw >= CHANNEL_WIDTH_40) @@ -4477,7 +4485,7 @@ static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp if (MLME_IS_ASOC(iface)) { RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface) - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset , dec_ch[i], dec_bw[i], dec_offset[i] , MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : ""); } else { @@ -4504,23 +4512,26 @@ static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp /* ch setting differs from existing one */ if (MLME_IS_ASOC(iface) - && (mlmeext->cur_channel != dec_ch[i] - || mlmeext->cur_bwmode != dec_bw[i] - || mlmeext->cur_ch_offset != dec_offset[i]) + && (mlmeext->chandef.chan != dec_ch[i] + || mlmeext->chandef.bw != dec_bw[i] + || mlmeext->chandef.offset != dec_offset[i]) ) { if (rtw_linked_check(iface) == _TRUE) { #ifdef CONFIG_SPCT_CH_SWITCH if (1) rtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]); else + #endif + #ifdef CONFIG_ECSA_PHL + if (CHK_ECSA_STATE(iface, ECSA_ST_NONE)) #endif rtw_sta_flush(iface, _FALSE); } } - mlmeext->cur_channel = dec_ch[i]; - mlmeext->cur_bwmode = dec_bw[i]; - mlmeext->cur_ch_offset = dec_offset[i]; + mlmeext->chandef.chan = dec_ch[i]; + mlmeext->chandef.bw = dec_bw[i]; + mlmeext->chandef.offset = dec_offset[i]; rtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]); } @@ -4531,7 +4542,7 @@ static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - RT_CHANNEL_INFO *chset = rfctl->channel_set; + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); int ch_idx; u8 ret = _SUCCESS; @@ -4561,11 +4572,12 @@ static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, c if (*bw > CHANNEL_WIDTH_20) (*bw)--; if (*bw == CHANNEL_WIDTH_20) { - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; break; } } + if (rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_dfs_chbw(chset, ch, *bw, *offset)) { RTW_WARN("%s DFS channel %u can't be used\n", caller, ch); ret = _FAIL; @@ -4633,8 +4645,7 @@ static bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_c } u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp - , s16 req_ch, s8 req_bw, s8 req_offset - , u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow, bool *set_u_ch) + , s16 req_ch, s8 req_bw, s8 req_offset, struct rtw_chan_def *chdef) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); @@ -4651,14 +4662,16 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp WLAN_BSSID_EX *network; struct mi_state mstate; struct mi_state mstate_others; + bool set_u_ch = _FALSE; u8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp; u8 ifbmp_ch_changed = 0; bool ifbmp_all_mesh = 0; _adapter *iface; int i; - - *set_u_ch = _FALSE; - +#ifdef CONFIG_MCC_MODE + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + u8 mcc_sup = phl_com->dev_cap.mcc_sup; +#endif #ifdef CONFIG_RTW_MESH for (i = 0; i < dvobj->iface_nums; i++) if ((ifbmp & BIT(i)) && dvobj->padapters) @@ -4697,7 +4710,7 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp dec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch; if (req_bw <= REQ_BW_NONE) { if (req_bw == REQ_BW_ORI) - dec_bw[i] = iface->mlmepriv.ori_bw; + dec_bw[i] = iface->mlmepriv.ori_chandef.bw; else dec_bw[i] = cur_ie_bw[i]; } else @@ -4715,31 +4728,30 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp } #ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter) && req_ch == 0) { - if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) { + if (mcc_sup && req_ch == 0) { + /* will disable MCC in ap starter prepare after v10 merge */ + if (rtw_hw_mcc_chk_inprogress(adapter)) { u8 if_id = adapter->iface_id; mlmeext = &(adapter->mlmeextpriv); - /* check channel settings are the same */ - if (cur_ie_ch[if_id] == mlmeext->cur_channel - && cur_ie_bw[if_id] == mlmeext->cur_bwmode - && cur_ie_offset[if_id] == mlmeext->cur_ch_offset) { + if (cur_ie_ch[if_id] == mlmeext->chandef.chan + && cur_ie_bw[if_id] == mlmeext->chandef.bw + && cur_ie_offset[if_id] == mlmeext->chandef.offset) { RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n" , FUNC_ADPT_ARG(adapter)); - - *chbw_allow = _FALSE; goto exit; } else { - RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n" + RTW_WARN(FUNC_ADPT_FMT"request channel settings are different from current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n" , FUNC_ADPT_ARG(adapter) , cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id] - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); - + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset); + #if 0 rtw_hal_set_mcc_setting_disconnect(adapter); + #endif } - } + } } #endif /* CONFIG_MCC_MODE */ @@ -4761,26 +4773,20 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp rtw_chset_sync_chbw(chset , &dec_ch[i], &dec_bw[i], &dec_offset[i] , &u_ch, &u_bw, &u_offset, 1, 0); - *set_u_ch = _TRUE; - - /* channel bw offset can be allowed, not need MCC */ - *chbw_allow = _TRUE; + set_u_ch = _TRUE; } else { #ifdef CONFIG_MCC_MODE - if (MCC_EN(iface)) { + if (mcc_sup) { mlmeext = &(iface->mlmeextpriv); - mlmeext->cur_channel = *ch = dec_ch[i]; - mlmeext->cur_bwmode = *bw = dec_bw[i]; - mlmeext->cur_ch_offset = *offset = dec_offset[i]; + mlmeext->chandef.chan = chdef->chan= dec_ch[i]; + mlmeext->chandef.bw = chdef->bw= dec_bw[i]; + mlmeext->chandef.offset = chdef->offset= dec_offset[i]; - /* channel bw offset can not be allowed, need MCC */ - *chbw_allow = _FALSE; RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface) - , *ch, *bw, *offset); + , chdef->chan, chdef->bw, chdef->offset); goto exit; } #endif /* CONFIG_MCC_MODE */ - /* set this for possible ch change when join down*/ set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING); } @@ -4795,38 +4801,33 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) continue; iface = dvobj->padapters[i]; - - rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]); - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(iface)) - rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]); - #endif - #ifdef CONFIG_MCC_MODE - if (MCC_EN(iface)) { + if (mcc_sup) { if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) { mlmeext = &(iface->mlmeextpriv); - mlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i]; - mlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i]; - mlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i]; - /* channel bw offset can not be allowed, need MCC */ - *chbw_allow = _FALSE; + mlmeext->chandef.chan = chdef->chan = dec_ch[i] = cur_ie_ch[i]; + mlmeext->chandef.bw = chdef->bw = dec_bw[i] = cur_ie_bw[i]; + mlmeext->chandef.offset = chdef->offset = dec_offset[i] = cur_ie_offset[i]; RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface) - , *ch, *bw, *offset); + , chdef->chan, chdef->bw, chdef->offset); goto exit; - } else - /* channel bw offset can be allowed, not need MCC */ - *chbw_allow = _TRUE; + } } #endif /* CONFIG_MCC_MODE */ + rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]); + #endif + if (req_ch == 0 && dec_bw[i] > u_bw && rtw_chset_is_dfs_chbw(chset, u_ch, u_bw, u_offset) ) { /* request comes from upper layer, prevent from additional channel waiting */ dec_bw[i] = u_bw; if (dec_bw[i] == CHANNEL_WIDTH_20) - dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + dec_offset[i] = CHAN_OFFSET_NO_EXT; } /* follow */ @@ -4835,7 +4836,7 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp , &u_ch, &u_bw, &u_offset, 1, 0); } - *set_u_ch = _TRUE; + set_u_ch = _TRUE; } else { /* autonomous decision */ @@ -4843,9 +4844,6 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp u8 max_bw; bool by_int_info; - /* autonomous decision, not need MCC */ - *chbw_allow = _TRUE; - if (req_ch <= REQ_CH_NONE) /* channel is not specified */ goto choose_chbw; @@ -4909,8 +4907,8 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp if (req_bw <= REQ_BW_NONE) { if (req_bw == REQ_BW_ORI) { - if (max_bw < iface->mlmepriv.ori_bw) - max_bw = iface->mlmepriv.ori_bw; + if (max_bw < iface->mlmepriv.ori_chandef.bw) + max_bw = iface->mlmepriv.ori_chandef.bw; } else { if (max_bw < cur_ie_bw[i]) max_bw = cur_ie_bw[i]; @@ -4919,8 +4917,8 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) { if (ori_ch == 0) - ori_ch = mlmeext->cur_channel; - else if (ori_ch != mlmeext->cur_channel) + ori_ch = mlmeext->chandef.chan; + else if (ori_ch != mlmeext->chandef.chan) rtw_warn_on(1); } else { if (ori_ch == 0) @@ -4945,7 +4943,7 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp if (dec_bw[i] > u_bw) dec_bw[i] = u_bw; if (dec_bw[i] == CHANNEL_WIDTH_20) - dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + dec_offset[i] = CHAN_OFFSET_NO_EXT; else dec_offset[i] = u_offset; @@ -4955,7 +4953,7 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp #endif } - *set_u_ch = _TRUE; + set_u_ch = _TRUE; } ifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp @@ -4966,18 +4964,16 @@ u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp if (u_ch != 0) RTW_INFO("%s union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset); - if (*set_u_ch == _TRUE) { - rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); - *ch = u_ch; - *bw = u_bw; - *offset = u_offset; - } - if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY)) { /* scanning, leave ch setting to scan state machine */ - *set_u_ch = _FALSE; + set_u_ch = _FALSE; } + if (set_u_ch == _TRUE) { + chdef->chan= u_ch; + chdef->bw = u_bw; + chdef->offset= u_offset; + } exit: return ifbmp_ch_changed; } @@ -4987,7 +4983,6 @@ u8 rtw_ap_sta_states_check(_adapter *adapter) struct sta_info *psta; struct sta_priv *pstapriv = &adapter->stapriv; _list *plist, *phead; - _irqL irqL; u8 rst = _FALSE; if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) @@ -4996,7 +4991,7 @@ u8 rtw_ap_sta_states_check(_adapter *adapter) if (pstapriv->auth_list_cnt !=0) return _TRUE; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { @@ -5014,169 +5009,10 @@ u8 rtw_ap_sta_states_check(_adapter *adapter) break; } } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); return rst; } -/*#define DBG_SWTIMER_BASED_TXBCN*/ -#ifdef CONFIG_SWTIMER_BASED_TXBCN -void tx_beacon_handlder(struct dvobj_priv *pdvobj) -{ -#define BEACON_EARLY_TIME 20 /* unit:TU*/ - _irqL irqL; - _list *plist, *phead; - u32 timestamp[2]; - u32 bcn_interval_us; /* unit : usec */ - u64 time; - u32 cur_tick, time_offset; /* unit : usec */ - u32 inter_bcn_space_us; /* unit : usec */ - u32 txbcn_timer_ms; /* unit : ms */ - int nr_vap, idx, bcn_idx; - int i; - u8 val8, late = 0; - _adapter *padapter = NULL; - - i = 0; - - /* get first ap mode interface */ - _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - if (rtw_is_list_empty(&pdvobj->ap_if_q.queue) || (pdvobj->nr_ap_if == 0)) { - RTW_INFO("[%s] ERROR: ap_if_q is empty!or nr_ap = %d\n", __func__, pdvobj->nr_ap_if); - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - return; - } else - padapter = LIST_CONTAINOR(get_next(&(pdvobj->ap_if_q.queue)), struct _ADAPTER, list); - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - - if (NULL == padapter) { - RTW_INFO("[%s] ERROR: no any ap interface!\n", __func__); - return; - } - - - bcn_interval_us = DEFAULT_BCN_INTERVAL * NET80211_TU_TO_US; - if (0 == bcn_interval_us) { - RTW_INFO("[%s] ERROR: beacon interval = 0\n", __func__); - return; - } - - /* read TSF */ - timestamp[1] = rtw_read32(padapter, 0x560 + 4); - timestamp[0] = rtw_read32(padapter, 0x560); - while (timestamp[1]) { - time = (0xFFFFFFFF % bcn_interval_us + 1) * timestamp[1] + timestamp[0]; - timestamp[0] = (u32)time; - timestamp[1] = (u32)(time >> 32); - } - cur_tick = timestamp[0] % bcn_interval_us; - - - _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - - nr_vap = (pdvobj->nr_ap_if - 1); - if (nr_vap > 0) { - inter_bcn_space_us = pdvobj->inter_bcn_space * NET80211_TU_TO_US; /* beacon_interval / (nr_vap+1); */ - idx = cur_tick / inter_bcn_space_us; - if (idx < nr_vap) /* if (idx < (nr_vap+1))*/ - bcn_idx = idx + 1; /* bcn_idx = (idx + 1) % (nr_vap+1);*/ - else - bcn_idx = 0; - - /* to get padapter based on bcn_idx */ - padapter = NULL; - phead = get_list_head(&pdvobj->ap_if_q); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - padapter = LIST_CONTAINOR(plist, struct _ADAPTER, list); - - plist = get_next(plist); - - if (i == bcn_idx) - break; - - i++; - } - if ((NULL == padapter) || (i > pdvobj->nr_ap_if)) { - RTW_INFO("[%s] ERROR: nr_ap_if = %d, padapter=%p, bcn_idx=%d, index=%d\n", - __func__, pdvobj->nr_ap_if, padapter, bcn_idx, i); - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - return; - } -#ifdef DBG_SWTIMER_BASED_TXBCN - RTW_INFO("BCN_IDX=%d, cur_tick=%d, padapter=%p\n", bcn_idx, cur_tick, padapter); -#endif - if (((idx + 2 == nr_vap + 1) && (idx < nr_vap + 1)) || (0 == bcn_idx)) { - time_offset = bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US; - if ((s32)time_offset < 0) - time_offset += inter_bcn_space_us; - - } else { - time_offset = (idx + 2) * inter_bcn_space_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US; - if (time_offset > (inter_bcn_space_us + (inter_bcn_space_us >> 1))) { - time_offset -= inter_bcn_space_us; - late = 1; - } - } - } else - /*#endif*/ { /* MBSSID */ - time_offset = 2 * bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US; - if (time_offset > (bcn_interval_us + (bcn_interval_us >> 1))) { - time_offset -= bcn_interval_us; - late = 1; - } - } - _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); - -#ifdef DBG_SWTIMER_BASED_TXBCN - RTW_INFO("set sw bcn timer %d us\n", time_offset); -#endif - txbcn_timer_ms = time_offset / NET80211_TU_TO_US; - _set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms); - - if (padapter) { -#ifdef CONFIG_BCN_RECOVERY - rtw_ap_bcn_recovery(padapter); -#endif /*CONFIG_BCN_RECOVERY*/ - -#ifdef CONFIG_BCN_XMIT_PROTECT - rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms); -#endif /*CONFIG_BCN_XMIT_PROTECT*/ - -#ifdef DBG_SWTIMER_BASED_TXBCN - RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port); -#endif - /* bypass TX BCN queue if op ch is switching/waiting */ - if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - && !IS_CH_WAITING(adapter_to_rfctl(padapter)) - ) { - /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);*/ - /*issue_beacon(padapter, 0);*/ - send_beacon(padapter); - } - } - -#if 0 - /* handle any buffered BC/MC frames*/ - /* Don't dynamically change DIS_ATIM due to HW will auto send ACQ after HIQ empty.*/ - val8 = *((unsigned char *)priv->beaconbuf + priv->timoffset + 4); - if (val8 & 0x01) { - process_mcast_dzqueue(priv); - priv->pkt_in_dtimQ = 0; - } -#endif - -} - -void tx_beacon_timer_handlder(void *ctx) -{ - struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; - _adapter *padapter = pdvobj->padapters[0]; - - if (padapter) - set_tx_beacon_cmd(padapter, 0); -} -#endif - void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap) { sta->capability = RTW_GET_LE16(cap); @@ -5196,7 +5032,7 @@ u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num); if (rate_num == 0) { RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); status = _STATS_FAILURE_; goto exit; } @@ -5239,6 +5075,7 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct sta->wpa2_group_cipher = 0; sta->wpa_pairwise_cipher = 0; sta->wpa2_pairwise_cipher = 0; + sta->akm_suite_type = 0; _rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie)); if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) { @@ -5249,35 +5086,47 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct sta->dot8021xalg = 1;/* psk, todo:802.1x */ sta->wpa_psk |= BIT(1); + /* RSN optional field absent; the validation is already checked in rtw_rsne_info_parse() */ + if (!group_cipher) { + RTW_INFO("STA lacks WPA2 Group Suite Cipher --> Default\n"); + group_cipher = sec->wpa2_group_cipher; + } + if (!pairwise_cipher) { + RTW_INFO("STA lacks WPA2 Pairwise Suite Cipher --> Default\n"); + pairwise_cipher = sec->wpa2_pairwise_cipher; + } + if (!akm) { + RTW_INFO("STA lacks WPA2 AKM Cipher --> Default\n"); + akm = sec->akmp; + } + sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher; sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher; - sta->akm_suite_type = akm; + if (MLME_IS_AP(adapter) && (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) && (MFP_NO == mfp_opt)) { status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION; goto exit; } - if (MLME_IS_AP(adapter) && (!CHECK_BIT(sec->akmp, akm))) { - status = WLAN_STATUS_AKMP_NOT_VALID; - goto exit; - } - + /* RSN optional field exists but no match */ if (!sta->wpa2_group_cipher) { status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; goto exit; } - if (!sta->wpa2_pairwise_cipher) { status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; goto exit; } - - } else { + if (MLME_IS_AP(adapter) && (!CHECK_BIT(sec->akmp, akm))) { + status = WLAN_STATUS_AKMP_NOT_VALID; + goto exit; + } + } + else { status = WLAN_STATUS_INVALID_IE; goto exit; } - } else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) { wpa_ie = elems->wpa_ie; @@ -5308,12 +5157,12 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct wpa_ie = NULL; wpa_ie_len = 0; } + if (sec->dot11PrivacyAlgrthm != _NO_PRIVACY_) { /*check if amsdu is allowed */ if (rtw_check_amsdu_disable(adapter->registrypriv.amsdu_mode, spp_opt) == _TRUE) sta->flags |= WLAN_STA_AMSDU_DISABLE; } - if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt < MFP_OPTIONAL) || (mfp_opt == MFP_REQUIRED && sec->mfp_opt < MFP_OPTIONAL) ) { @@ -5347,7 +5196,7 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct (CHECK_BIT(WLAN_AKM_TYPE_SAE, sta->akm_suite_type)) && (WLAN_AUTH_OPEN == sta->authalg)) { /* WPA3-SAE, PMK caching */ - if (rtw_cached_pmkid(adapter, sta->cmn.mac_addr) == -1) { + if (rtw_cached_pmkid(adapter, sta->phl_sta->mac_addr) == -1) { RTW_INFO("SAE: No PMKSA cache entry found\n"); status = WLAN_STATUS_INVALID_PMKID; goto exit; @@ -5404,7 +5253,7 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct if (sec->wpa_psk == 0) { RTW_INFO("STA " MAC_FMT ": WPA/RSN IE in association request, but AP don't support WPA/RSN\n", - MAC_ARG(sta->cmn.mac_addr)); + MAC_ARG(sta->phl_sta->mac_addr)); status = WLAN_STATUS_INVALID_IE; goto exit; } @@ -5550,6 +5399,39 @@ void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw return; } +void rtw_ap_parse_sta_he_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + + sta->flags &= ~WLAN_STA_HE; + +#ifdef CONFIG_80211AX_HE + if (mlme->hepriv.he_option == _FALSE) + goto exit; + + _rtw_memset(&sta->hepriv, 0, sizeof(struct he_priv)); + if (elems->he_capabilities && (elems->he_capabilities_len <= HE_CAP_ELE_MAX_LEN)) { + sta->flags |= WLAN_STA_HE; + _rtw_memcpy(sta->hepriv.he_cap, elems->he_capabilities, elems->he_capabilities_len); + + if (elems->he_operation && (elems->he_operation_len <= HE_OPER_ELE_MAX_LEN)) { + _rtw_memcpy(sta->hepriv.he_op, elems->he_operation, elems->he_operation_len); + sta->hepriv.op_present = 1; + } + +#if 0 + if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) { + _rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1); + sta->vhtpriv.notify_present = 1; + } +#endif + } +exit: +#endif + + return; +} + void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len) { sta->flags &= ~WLAN_STA_MULTI_AP; @@ -5573,7 +5455,6 @@ static bool rtw_ap_data_bmc_to_uc(_adapter *adapter { struct sta_priv *stapriv = &adapter->stapriv; struct xmit_priv *xmitpriv = &adapter->xmitpriv; - _irqL irqL; _list *head, *list; struct sta_info *sta; char b2u_sta_id[NUM_STA]; @@ -5581,7 +5462,7 @@ static bool rtw_ap_data_bmc_to_uc(_adapter *adapter bool bmc_need = _FALSE; int i; - _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&stapriv->asoc_list_lock); head = &stapriv->asoc_list; list = get_next(head); @@ -5590,37 +5471,36 @@ static bool rtw_ap_data_bmc_to_uc(_adapter *adapter sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); list = get_next(list); - + stainfo_offset = rtw_stainfo_offset(stapriv, sta); if (stainfo_offset_valid(stainfo_offset)) b2u_sta_id[b2u_sta_num++] = stainfo_offset; } - _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); if (!b2u_sta_num) goto exit; for (i = 0; i < b2u_sta_num; i++) { - struct xmit_frame *b2uframe; + struct xmit_frame *b2uframe = NULL; struct pkt_attrib *attrib; sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]); if (!(sta->state & WIFI_ASOC_STATE) - || _rtw_memcmp(sta->cmn.mac_addr, sa, ETH_ALEN) == _TRUE - || (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE) - || is_broadcast_mac_addr(sta->cmn.mac_addr) - || is_zero_mac_addr(sta->cmn.mac_addr)) + || _rtw_memcmp(sta->phl_sta->mac_addr, sa, ETH_ALEN) == _TRUE + || (ori_ta && _rtw_memcmp(sta->phl_sta->mac_addr, ori_ta, ETH_ALEN) == _TRUE) + || is_broadcast_mac_addr(sta->phl_sta->mac_addr) + || is_zero_mac_addr(sta->phl_sta->mac_addr)) continue; - b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid); - if (!b2uframe) { + if (core_tx_alloc_xmitframe(adapter, &b2uframe, os_qid) == FAIL) { bmc_need = _TRUE; break; } attrib = &b2uframe->attrib; - _rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(attrib->ra, sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); #ifdef CONFIG_RTW_WDS if (adapter_use_wds(adapter) && (sta->flags & WLAN_STA_WDS)) { @@ -5651,11 +5531,13 @@ static int rtw_ap_nexthop_resolve(_adapter *adapter, struct xmit_frame *xframe) int ret = _SUCCESS; #ifdef CONFIG_RTW_WDS - if (adapter_use_wds(adapter) - && rtw_wds_nexthop_lookup(adapter, attrib->dst, attrib->ra) == 0 - ) { - if (_rtw_memcmp(attrib->dst, attrib->ra, ETH_ALEN) == _FALSE) - attrib->wds = 1; + if (adapter_use_wds(adapter)) { + if (rtw_wds_nexthop_lookup(adapter, attrib->dst, attrib->ra) == 0) { + if (_rtw_memcmp(attrib->dst, attrib->ra, ETH_ALEN) == _FALSE) + attrib->wds = 1; + } else { + ret = _FAIL; + } } else #endif _rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN); @@ -5663,17 +5545,79 @@ static int rtw_ap_nexthop_resolve(_adapter *adapter, struct xmit_frame *xframe) return ret; } -int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list) +#ifdef CONFIG_RTW_WDS +static void rtw_ap_data_flood_for_unknown_da(_adapter *adapter, const u8 *da, + const u8 *sa, const u8 *ori_ta, + u16 os_qid, _list *f_list) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + _list *head, *list; + struct sta_info *sta; + char sta_id[NUM_STA]; + u8 sta_num = 0; + int i; + + _rtw_spinlock_bh(&stapriv->asoc_list_lock); + head = &stapriv->asoc_list; + list = get_next(head); + + while ((rtw_end_of_queue_search(head, list)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + sta_id[sta_num++] = stainfo_offset; + } + + _rtw_spinunlock_bh(&stapriv->asoc_list_lock); + + if (!sta_num) + goto exit; + + for (i = 0; i < sta_num; i++) { + struct xmit_frame *frame; + struct pkt_attrib *attrib; + + sta = rtw_get_stainfo_by_offset(stapriv, sta_id[i]); + if (!(sta->state & WIFI_ASOC_STATE) + || !(sta->flags & WLAN_STA_WDS) + || _rtw_memcmp(sta->phl_sta->mac_addr, sa, ETH_ALEN) == _TRUE + || (ori_ta && _rtw_memcmp(sta->phl_sta->mac_addr, ori_ta, ETH_ALEN) == _TRUE) + || is_broadcast_mac_addr(sta->phl_sta->mac_addr) + || is_zero_mac_addr(sta->phl_sta->mac_addr)) + continue; + + if (core_tx_alloc_xmitframe(adapter, &frame, os_qid) == FAIL) + break; + + attrib = &frame->attrib; + + _rtw_memcpy(attrib->ra, sta->phl_sta->mac_addr, ETH_ALEN); + _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(attrib->dst, da, ETH_ALEN); + _rtw_memcpy(attrib->src, sa, ETH_ALEN); + attrib->wds = 1; + + rtw_list_insert_tail(&frame->list, f_list); + } + +exit: + return; +} +#endif /* CONFIG_RTW_WDS */ + +int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, + struct sk_buff *pkt, _list *f_list) { struct pkt_file pktfile; struct ethhdr etherhdr; struct pkt_attrib *attrib; - struct rtw_mesh_path *mpath = NULL, *mppath = NULL; u8 is_da_mcast; - u8 addr4_need; -#if CONFIG_RTW_AP_DATA_BMC_TO_UC - bool bmc_need = _TRUE; -#endif + int res = _SUCCESS; _rtw_open_pktfile(pkt, &pktfile); @@ -5681,23 +5625,22 @@ int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe res = _FAIL; goto exit; } - + xframe->pkt = pkt; -#if CONFIG_RTW_AP_DATA_BMC_TO_UC - _rtw_init_listhead(b2u_list); +#if defined(CONFIG_RTW_WDS) || CONFIG_RTW_AP_DATA_BMC_TO_UC + _rtw_init_listhead(f_list); #endif is_da_mcast = IS_MCAST(etherhdr.h_dest); if (is_da_mcast) { #if CONFIG_RTW_AP_DATA_BMC_TO_UC if (rtw_ap_src_b2u_policy_chk(adapter->b2u_flags_ap_src, etherhdr.h_dest) - && adapter->registrypriv.wifi_spec == 0 - && adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4) - ) { - bmc_need = rtw_ap_data_bmc_to_uc(adapter - , etherhdr.h_dest, etherhdr.h_source, NULL, os_qid, b2u_list); - if (bmc_need == _FALSE) { - res = RTW_BMC_NO_NEED; + && adapter->registrypriv.wifi_spec == 0 + && adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4)) { + if (rtw_ap_data_bmc_to_uc(adapter, etherhdr.h_dest, + etherhdr.h_source, NULL, + os_qid, f_list) == 0) { + res = RTW_ORI_NO_NEED; goto exit; } } @@ -5710,10 +5653,20 @@ int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe _rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN); _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); - if (is_da_mcast) + if (is_da_mcast) { _rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN); - else + } else { res = rtw_ap_nexthop_resolve(adapter, xframe); + #ifdef CONFIG_RTW_WDS + if (res != _SUCCESS) { + /* unknown DA, flood frame to every WDS STA */ + rtw_ap_data_flood_for_unknown_da(adapter, etherhdr.h_dest, + etherhdr.h_source, NULL, + os_qid, f_list); + res = RTW_ORI_NO_NEED; + } + #endif + } exit: return res; @@ -5731,7 +5684,7 @@ int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, str goto exit; switch (rattrib->to_fr_ds) { - case 1: + case 2: if (IS_MCAST(GetAddr1Ptr(whdr))) goto exit; _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); @@ -5773,10 +5726,10 @@ int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, str #endif process_pwrbit_data(adapter, rframe, *sta); - + if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) process_wmmps_data(adapter, rframe, *sta); - + if (get_frame_sub_type(whdr) & BIT(6)) { /* No data, will not indicate to upper layer, temporily count it here */ count_rx_stats(adapter, rframe, *sta); @@ -5793,12 +5746,12 @@ int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, str int rtw_ap_rx_msdu_act_check(union recv_frame *rframe , const u8 *da, const u8 *sa , u8 *msdu, enum rtw_rx_llc_hdl llc_hdl - , struct xmit_frame **fwd_frame, _list *b2u_list) + , struct xmit_frame **fwd_frame, _list *f_list) { _adapter *adapter = rframe->u.hdr.adapter; struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; struct rtw_wds_path *wpath; - u8 is_da_bmc = IS_MCAST(da); + u8 is_da_bmc = IS_MCAST(da); u8 is_da_self = !is_da_bmc && _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN); u8 is_da_peer = 0; int in_wds_tbl = 0; @@ -5807,15 +5760,12 @@ int rtw_ap_rx_msdu_act_check(union recv_frame *rframe struct pkt_attrib *xattrib; u8 fwd_ra[ETH_ALEN] = {0}; int act = 0; -#if CONFIG_RTW_AP_DATA_BMC_TO_UC - bool bmc_need = _TRUE; -#endif #ifdef CONFIG_RTW_WDS /* update/create wds info for SA, RA */ if (adapter_use_wds(adapter) && (rframe->u.hdr.psta->state & WIFI_ASOC_STATE) - && _rtw_memcmp(sa, rframe->u.hdr.psta->cmn.mac_addr, ETH_ALEN) == _FALSE + && _rtw_memcmp(sa, rframe->u.hdr.psta->phl_sta->mac_addr, ETH_ALEN) == _FALSE ) { rtw_rcu_read_lock(); wpath = rtw_wds_path_lookup(adapter, sa); @@ -5836,12 +5786,14 @@ int rtw_ap_rx_msdu_act_check(union recv_frame *rframe if (is_da_bmc) { /* DA is bmc addr */ act |= RTW_RX_MSDU_ACT_INDICATE; + #if 0 /* TODO: ap_isolate */ if (adapter->mlmepriv.ap_isolate) goto exit; + #endif goto fwd_chk; } - + if (is_da_self) { /* DA is self, indicate */ act |= RTW_RX_MSDU_ACT_INDICATE; @@ -5858,6 +5810,7 @@ int rtw_ap_rx_msdu_act_check(union recv_frame *rframe if (in_wds_tbl || is_da_peer) { /* DA is known (peer or can be forwarded by peer) */ + #if 0 /* TODO: ap_isolate */ if (adapter->mlmepriv.ap_isolate) { #if defined(DBG_RX_DROP_FRAME) RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") through peer, ap_isolate\n" @@ -5865,12 +5818,21 @@ int rtw_ap_rx_msdu_act_check(union recv_frame *rframe #endif goto exit; } + #endif goto fwd_chk; } /* DA is unknown*/ act |= RTW_RX_MSDU_ACT_INDICATE; - goto exit; + #if 0 /* TODO: ap_isolate */ + if (adapter->mlmepriv.ap_isolate) { + /* + * unknown DA and ap_isolate, indicate only + * (bridge will not forward packets to originating port) + */ + goto exit; + } + #endif fwd_chk: @@ -5879,48 +5841,69 @@ int rtw_ap_rx_msdu_act_check(union recv_frame *rframe os_qid = rtw_os_recv_select_queue(msdu, llc_hdl); -#if CONFIG_RTW_AP_DATA_BMC_TO_UC - _rtw_init_listhead(b2u_list); - - if (is_da_bmc - && rtw_ap_fwd_b2u_policy_chk(adapter->b2u_flags_ap_fwd, da, rattrib->to_fr_ds == 3 && !IS_MCAST(rattrib->ra)) - && adapter->registrypriv.wifi_spec == 0 - && adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4) - ) { - bmc_need = rtw_ap_data_bmc_to_uc(adapter - , da, sa, rframe->u.hdr.psta->cmn.mac_addr - , os_qid, b2u_list); - } +#if defined(CONFIG_RTW_WDS) || CONFIG_RTW_AP_DATA_BMC_TO_UC + _rtw_init_listhead(f_list); +#endif - if (bmc_need == _TRUE) +#if CONFIG_RTW_AP_DATA_BMC_TO_UC + if (is_da_bmc) { + if (rtw_ap_fwd_b2u_policy_chk(adapter->b2u_flags_ap_fwd, da, rattrib->to_fr_ds == 3 && !IS_MCAST(rattrib->ra)) + && adapter->registrypriv.wifi_spec == 0 + && adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4) + ) { + if (rtw_ap_data_bmc_to_uc(adapter + , da, sa, rframe->u.hdr.psta->phl_sta->mac_addr + , os_qid, f_list) == 0 + ) { + if (!rtw_is_list_empty(f_list)) + goto set_act_fwd; + else + goto exit; + } + } + } else #endif - { - xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid); - if (!xframe) { - #ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n" - , FUNC_ADPT_ARG(adapter)); - #endif +#ifdef CONFIG_RTW_WDS + if (adapter_use_wds(adapter) && !in_wds_tbl && !is_da_peer) { + /* unknown DA, flood frame to every WDS STA except receiving one */ + rtw_ap_data_flood_for_unknown_da(adapter + , da, sa, rframe->u.hdr.psta->phl_sta->mac_addr + , os_qid, f_list); + if (!rtw_is_list_empty(f_list)) + goto set_act_fwd; + else goto exit; - } + } else +#endif + ; - xattrib = &xframe->attrib; + if (core_tx_alloc_xmitframe(adapter, &xframe, os_qid) == FAIL) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" core_tx_alloc_xmitframe fail\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } - _rtw_memcpy(xattrib->dst, da, ETH_ALEN); - _rtw_memcpy(xattrib->src, sa, ETH_ALEN); - _rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + xattrib = &xframe->attrib; - #ifdef CONFIG_RTW_WDS - if (in_wds_tbl && _rtw_memcmp(da, fwd_ra, ETH_ALEN) == _FALSE) { - _rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN); - xattrib->wds = 1; - } else - #endif - _rtw_memcpy(xattrib->ra, da, ETH_ALEN); + _rtw_memcpy(xattrib->dst, da, ETH_ALEN); + _rtw_memcpy(xattrib->src, sa, ETH_ALEN); + _rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN); - *fwd_frame = xframe; - } + #ifdef CONFIG_RTW_WDS + if (in_wds_tbl && _rtw_memcmp(da, fwd_ra, ETH_ALEN) == _FALSE) { + _rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN); + xattrib->wds = 1; + } else + #endif + _rtw_memcpy(xattrib->ra, da, ETH_ALEN); + *fwd_frame = xframe; + +#if defined(CONFIG_RTW_WDS) || CONFIG_RTW_AP_DATA_BMC_TO_UC +set_act_fwd: +#endif act |= RTW_RX_MSDU_ACT_FORWARD; exit: @@ -5954,16 +5937,16 @@ void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat) if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; - RTW_DBG("%s: %6ph\n", __FUNCTION__, pstat->cmn.mac_addr); + RTW_DBG("%s: %6ph\n", __FUNCTION__, pstat->phl_sta->mac_addr); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) return; /* update attribute */ pattrib = &pmgntframe->attrib; + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_24MB); // issue action request using OFDM rate? 20190320 Bruce add update_mgntframe_attrib(padapter, pattrib); - pattrib->rate = MGN_24M; /* issue action request using OFDM rate? 20190716 Bruce add */ - + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; @@ -5972,7 +5955,7 @@ void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat) fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); @@ -5994,5 +5977,758 @@ void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat) } #endif /* CONFIG_RTW_TOKEN_BASED_XMIT */ -#endif /* CONFIG_AP_MODE */ +void rtw_ap_set_sta_wmode(_adapter *padapter, struct sta_info *sta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + enum wlan_mode network_type = WLAN_MD_INVALID; + +#ifdef CONFIG_80211AX_HE + if (sta->hepriv.he_option == _TRUE) + network_type = WLAN_MD_11AX; +#endif +#ifdef CONFIG_80211AC_VHT + if (network_type == WLAN_MD_INVALID) { + if (sta->vhtpriv.vht_option == _TRUE) + network_type = WLAN_MD_11AC; + } +#endif +#ifdef CONFIG_80211N_HT + if (network_type == WLAN_MD_INVALID) { + if (sta->htpriv.ht_option == _TRUE) + network_type = WLAN_MD_11N; + } +#endif + + if (pcur_network->Configuration.DSConfig > 14) + network_type |= WLAN_MD_11A; + else { + if ((cckratesonly_included(sta->bssrateset, sta->bssratelen)) == _TRUE) + network_type |= WLAN_MD_11B; + else if ((cckrates_included(sta->bssrateset, sta->bssratelen)) == _TRUE) + network_type |= WLAN_MD_11BG; + else + network_type |= WLAN_MD_11G; + } + + sta->phl_sta->wmode = network_type; +} + +#if defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) +void rtw_acs_start(_adapter *padapter) +{ + RTW_INFO(FUNC_ADPT_FMT" not support\n", FUNC_ADPT_ARG(padapter)); +} + +void rtw_acs_stop(_adapter *padapter) +{ + RTW_INFO(FUNC_ADPT_FMT" not support\n", FUNC_ADPT_ARG(padapter)); +} +#endif /* defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) */ + +#ifdef CONFIG_AP_CMD_DISPR + +static enum rtw_phl_status _ap_start_swch_start_notify(struct _ADAPTER *padapter) +{ + struct dvobj_priv *d = adapter_to_dvobj(padapter); + struct rtw_wifi_role_t *role = padapter->phl_role; + enum rtw_phl_status status; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SWCH_START); + + msg.band_idx = padapter->phl_role->hw_band; + msg.rsvd[0] = (u8*)role; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + + return status; +} + +static void _ap_start_swch_done_notify_cb(void *priv, struct phl_msg *msg) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": ap_start_cmd_state=%u\n", + FUNC_ADPT_ARG(a), a->ap_start_cmd_state); + + if (msg->inbuf) { + rtw_vmfree(msg->inbuf, msg->inlen); + msg->inbuf = NULL; + } +} + +static enum rtw_phl_status +_ap_start_swch_done_notify(struct _ADAPTER *a, struct rtw_chan_def *chandef) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u8 *info = NULL; + enum rtw_phl_status status; + + + info = rtw_vmalloc(sizeof(struct rtw_chan_def)); + if (!info) { + RTW_ERR(FUNC_ADPT_FMT ": Allocate msg hub buffer fail!\n", + FUNC_ADPT_ARG(a)); + return RTW_PHL_STATUS_RESOURCE; + } + _rtw_memcpy(info, chandef, sizeof(struct rtw_chan_def)); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SWCH_DONE); + msg.band_idx = a->phl_role->hw_band; + msg.inbuf = info; + msg.inlen = sizeof(struct rtw_chan_def); + + attr.completion.completion = _ap_start_swch_done_notify_cb; + attr.completion.priv = a; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + rtw_vmfree(info, sizeof(struct rtw_chan_def)); + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + } + + return status; +} + +static void _ap_start_end_notify_cb(void *priv, struct phl_msg *msg) +{ + + if (msg->inbuf) { + rtw_vmfree(msg->inbuf, msg->inlen); + msg->inbuf = NULL; + } +} + +static enum rtw_phl_status +_ap_start_end_notify(struct _ADAPTER *padapter, bool success, bool abort) +{ + struct rtw_wifi_role_t *role = padapter->phl_role; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u8 *info = NULL; + + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_AP_START\n", FUNC_ADPT_ARG(padapter)); + + info = rtw_vmalloc(sizeof(u8)); + if (info == NULL) { + RTW_ERR("%s: alloc buffer failed!\n", __func__); + return RTW_PHL_STATUS_RESOURCE; + } + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_START_END); + if (success) { + *info = RTW_PHL_STATUS_SUCCESS; + } else { + *info = RTW_PHL_STATUS_FAILURE; + } + + msg.inbuf = info; + msg.inlen = 1; + msg.band_idx = role->hw_band; + msg.rsvd[0] = (u8*)role; + + if(abort) + attr.opt = MSG_OPT_SEND_IN_ABORT; + attr.completion.completion = _ap_start_end_notify_cb; + attr.completion.priv = padapter; + + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + rtw_vmfree(info, sizeof(u8)); + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(padapter), status); + } + + return status; +} + +static void ap_free_cmdobj(struct cmd_obj *pcmd) +{ + struct _ADAPTER *padapter = pcmd->padapter; + + if (!pcmd) + return; + + + if (pcmd->sctx) { + if (pcmd->res == H2C_SUCCESS) + rtw_sctx_done(&pcmd->sctx); + else + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR); + } + + rtw_free_cmd_obj(pcmd); + + return; +} + +static void _ap_start_cmd_done(struct cmd_obj *pcmd) +{ + struct _ADAPTER *padapter = pcmd->padapter; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + struct rtw_wifi_role_t *role = padapter->phl_role; + enum rtw_phl_status status; + + RTW_INFO("%s: +\n", __func__); + + if (!padapter->ap_start_cmd_token){ + RTW_ERR("%s : token is NULL!\n", __func__); + return; + } + + status = rtw_phl_free_cmd_token(GET_PHL_INFO(d), + role->hw_band, &padapter->ap_start_cmd_token); + + padapter->ap_start_cmd_token = 0; + padapter->ap_start_cmd_state = 0; + + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": free_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(padapter), status); + + ap_free_cmdobj(pcmd); + + RTW_INFO("%s: -\n", __func__); +} + +enum rtw_phl_status rtw_free_bcn_entry(struct _ADAPTER *padapter){ + + struct dvobj_priv *d = adapter_to_dvobj(padapter); + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + +#ifdef RTW_PHL_BCN + status = rtw_phl_free_bcn_entry(d->phl, padapter->phl_role); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s - phl_free_bcn_entry failed\n", __func__); + } +#endif + + return status; +} + +static enum phl_mdl_ret_code _ap_start_req_acquired(void *dispr, void *priv) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + struct createbss_parm *parm = (struct createbss_parm *)pcmd->parmbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rtw_wifi_role_t *role = padapter->phl_role; + struct rtw_phl_com_t *phl_com = role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + + if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE) + || parm->req_ch != 0 + ){ + start_bss_network(padapter, parm); + } + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_START_PREPARE); + msg.band_idx = role->hw_band; + + status = rtw_phl_send_msg_to_dispr(phl_info, + &msg, + &attr, + NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + return MDL_RET_FAIL; + } else { + SET_STATUS_FLAG(padapter->ap_start_cmd_state, CMD_APSTART_ACQUIRE); + return MDL_RET_SUCCESS; + } +} + +static enum phl_mdl_ret_code _ap_start_req_abort(void *dispr, void *priv) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + + if (TEST_STATUS_FLAG(padapter->ap_start_cmd_state, CMD_APSTART_ACQUIRE)) { + status = _ap_start_end_notify(padapter, false, true); + } + + padapter->ap_start_cmd_state = 0; + RTW_INFO("%s\n", __func__); + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ap_start_req_ev_hdlr(void *dispr, void *priv, struct phl_msg* msg) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + struct createbss_parm *parm = (struct createbss_parm *)pcmd->parmbuf; + struct rtw_wifi_role_t *wifi_role = padapter->phl_role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + void *d = phlcom_to_drvpriv(phl_com); + struct phl_msg nextmsg = {0}; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + RTW_DBG(FUNC_ADPT_FMT ": + msg_id=0x%08x\n", + FUNC_ADPT_ARG(padapter), msg->msg_id); + + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_AP_START) { + RTW_INFO(FUNC_ADPT_FMT ": Message is not from ap start module, " + "skip msg_id=0x%08x\n", FUNC_ADPT_ARG(padapter), msg->msg_id); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + return MDL_RET_IGNORE; + } + + if (IS_MSG_FAIL(msg->msg_id)) { + RTW_WARN(FUNC_ADPT_FMT ": cmd dispatcher notify cmd failure on " + "msg_id=0x%08x\n", FUNC_ADPT_ARG(padapter), msg->msg_id); + } + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_AP_START); + nextmsg.band_idx = wifi_role->hw_band; + + switch(MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_AP_START_PREPARE: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_AP_START_PREPARE\n", FUNC_ADPT_ARG(padapter)); + status = _ap_start_swch_start_notify(padapter); + if(status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR("%s :: [MSG_EVT_AP_START_PREPARE] rtw_phl_send_msg_to_dispr failed\n", __func__); + break; + } + case MSG_EVT_SWCH_START: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_SWCH_START\n", FUNC_ADPT_ARG(padapter)); + rtw_core_ap_swch_start(padapter, parm); + status = _ap_start_swch_done_notify(padapter, &wifi_role->chandef); + if(status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR("%s :: [SWCH_START] rtw_phl_send_msg_to_dispr failed\n", __func__); + break; + } + + case MSG_EVT_SWCH_DONE: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_SWCH_DONE\n", FUNC_ADPT_ARG(padapter)); + status = rtw_phl_ap_started(adapter_to_dvobj(padapter)->phl, padapter->phl_role); + if(status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR("%s :: [MSG_EVT_SWCH_DONE] rtw_phl_send_msg_to_dispr failed\n", __func__); + break; + } + case MSG_EVT_AP_START: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_AP_START\n", FUNC_ADPT_ARG(padapter)); + rtw_core_ap_start(padapter, parm); /* send beacon */ + status = _ap_start_end_notify(padapter, true, false); + break; + } + + case MSG_EVT_AP_START_END: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_AP_START_END\n", FUNC_ADPT_ARG(padapter)); + if (msg->inbuf == NULL) { + RTW_WARN("[MSG_EVT_AP_START_END] Msg info buffer NULL!\n"); + break; + } + + if (*(msg->inbuf) == RTW_PHL_STATUS_FAILURE){ + RTW_WARN("[MSG_EVT_AP_START_END] Msg_inbuf is FAIL!\n"); + stop_ap_hdl(padapter); + } + + _ap_start_cmd_done(pcmd); + break; + } + + default: + /* unknown state */ + break; + } + + + if (status != RTW_PHL_STATUS_SUCCESS) { + /* Trigger stop AP flow when start AP failure */ + stop_ap_hdl(padapter); + _ap_start_cmd_done(pcmd); + } + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ap_start_req_set_info(void *dispr, void *priv, struct phl_module_op_info* info) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + + return MDL_RET_IGNORE; +} + +static enum phl_mdl_ret_code _ap_start_req_query_info(void *dispr, void *priv, struct phl_module_op_info* info) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + + switch (info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8*)padapter->phl_role; + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + return ret; +} + +static void rtw_cmd_ap_start_req_init(struct cmd_obj *pcmd, struct phl_cmd_token_req *fgreq) +{ + struct _ADAPTER *padapter = pcmd->padapter; + u8 res = _SUCCESS; + + /* Fill foreground command request */ + fgreq->module_id= PHL_FG_MDL_AP_START; + fgreq->priv = pcmd; + fgreq->role = padapter->phl_role; + + fgreq->acquired = _ap_start_req_acquired; + fgreq->abort = _ap_start_req_abort; + fgreq->msg_hdlr = _ap_start_req_ev_hdlr; + fgreq->set_info = _ap_start_req_set_info; + fgreq->query_info = _ap_start_req_query_info; + + padapter->ap_start_cmd_state = 0; + padapter->ap_start_cmd_token = 0; + + RTW_INFO("%s\n", __func__); +} + +enum rtw_phl_status rtw_ap_start_cmd(struct cmd_obj *pcmd) +{ + struct _ADAPTER *padapter = pcmd->padapter; + struct phl_cmd_token_req fgreq={0}; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + enum rtw_phl_status status; + struct rtw_wifi_role_t *role = padapter->phl_role; + + rtw_cmd_ap_start_req_init(pcmd, &fgreq); + + RTW_DBG(FUNC_ADPT_FMT ": \n", FUNC_ADPT_ARG(padapter)); + + /* cmd_dispatcher would copy whole phl_cmd_token_req */ + status = rtw_phl_add_cmd_token_req(d->phl, role->hw_band, &fgreq, &padapter->ap_start_cmd_token); + if((status != RTW_PHL_STATUS_SUCCESS) && + (status != RTW_PHL_STATUS_PENDING)) + goto error; + + status = RTW_PHL_STATUS_SUCCESS; + +error: + return status; + +} + +static void _ap_stop_cmd_done(struct cmd_obj *pcmd) +{ + struct _ADAPTER *padapter = pcmd->padapter; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + struct rtw_wifi_role_t *role = padapter->phl_role; + enum rtw_phl_status status; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + + if (!padapter->ap_stop_cmd_token){ + RTW_ERR("%s : token is NULL!\n", __func__); + return; + } + + status = rtw_phl_free_cmd_token(GET_PHL_INFO(d), + role->hw_band, &padapter->ap_stop_cmd_token); + + padapter->ap_stop_cmd_token = 0; + padapter->ap_stop_cmd_state = 0; + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": free_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(padapter), status); + + ap_free_cmdobj(pcmd); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); +} + +static enum rtw_phl_status _ap_stop_ap_stop_notify(struct _ADAPTER *adapter) +{ + struct dvobj_priv *d = adapter_to_dvobj(adapter); + struct rtw_wifi_role_t *role = adapter->phl_role; + enum rtw_phl_status status; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_STOP); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_STOP); + + msg.band_idx = adapter->phl_role->hw_band; + msg.rsvd[0] = (u8*)role; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", FUNC_ADPT_ARG(adapter), status); + } + return status; +} + +static void _ap_stop_abort_notify_cb(void *priv, struct phl_msg *msg) +{ + _adapter *padapter = (_adapter *)priv; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + struct _ADAPTER *adapter = (struct _ADAPTER *)priv; + enum rtw_phl_status phl_status = RTW_PHL_STATUS_SUCCESS; + struct rtw_chan_def chan_def = {0}; + u8 chctx_num = 0; + +#ifdef RTW_PHL_BCN + phl_status = rtw_phl_free_bcn_entry(d->phl, adapter->phl_role); + if (phl_status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s - phl_free_bcn_entry failed\n", __func__); + } +#endif +} + +static enum rtw_phl_status _ap_stop_abort_notify(struct _ADAPTER *adapter, bool abort) +{ + struct dvobj_priv *d = adapter_to_dvobj(adapter); + struct rtw_wifi_role_t *role = adapter->phl_role; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_STOP); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_STOP); + msg.band_idx = role->hw_band; + msg.rsvd[0] = (u8*)role; + + if(abort) + attr.opt = MSG_OPT_SEND_IN_ABORT; + attr.completion.completion = _ap_stop_abort_notify_cb; + attr.completion.priv = adapter; + + status = rtw_phl_send_msg_to_dispr(d->phl, + &msg, + &attr, + NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("[%s] Abort send msg fail!\n", __func__); + } + + return status; +} + +static enum phl_mdl_ret_code _ap_stop_req_acquired(void *dispr, void *priv) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + struct rtw_wifi_role_t *role = padapter->phl_role; + struct rtw_phl_com_t *phl_com = role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + struct phl_msg msg = {0}; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + + SET_STATUS_FLAG(padapter->ap_stop_cmd_state, CMD_APSTOP_ACQUIRE); + + rtw_phl_ap_stop(adapter_to_dvobj(padapter)->phl, role); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + + return MDL_RET_SUCCESS; + +} + +static enum phl_mdl_ret_code _ap_stop_req_abort(void *dispr, void *priv) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + + if(TEST_STATUS_FLAG(padapter->ap_stop_cmd_state, CMD_APSTOP_STARTED)){ + /* case1: MSG_EVT_AP_STOP has been processed*/ + } + else if(TEST_STATUS_FLAG(padapter->ap_stop_cmd_state, CMD_APSTOP_ACQUIRE)){ + /* case2: MSG_EVT_AP_STOP in msgQ + case3: MSG_EVT_AP_STOP doesn't back to msg_hdlr yet */ + if (RTW_PHL_STATUS_SUCCESS != _ap_stop_abort_notify(padapter, true)) { + /* do not execute core_mr_handle because do not know if the I/O operation is acceptable */ + //core_mr_delete_chctx(adapter, &chctx_num, &chan_def); + } + } + else{ + /* apstop token stay in tokenOpQ */ + } + + padapter->ap_stop_cmd_state = 0; + RTW_INFO("%s\n", __func__); + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ap_stop_req_ev_hdlr(void *dispr, void *priv, struct phl_msg* msg) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + struct rtw_wifi_role_t *wifi_role = padapter->phl_role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + void *d = phlcom_to_drvpriv(phl_com); + struct phl_msg nextmsg = {0}; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + RTW_DBG(FUNC_ADPT_FMT ": + msg_id=0x%08x\n", + FUNC_ADPT_ARG(padapter), msg->msg_id); + + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_AP_STOP) { + RTW_INFO(FUNC_ADPT_FMT ": Message is not from ap stop module, " + "skip msg_id=0x%08x\n", FUNC_ADPT_ARG(padapter), msg->msg_id); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + return MDL_RET_IGNORE; + } + + if (IS_MSG_FAIL(msg->msg_id)) { + RTW_WARN(FUNC_ADPT_FMT ": cmd dispatcher notify cmd failure on " + "msg_id=0x%08x\n", FUNC_ADPT_ARG(padapter), msg->msg_id); + } + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_AP_STOP); + nextmsg.band_idx = wifi_role->hw_band; + + switch(MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_AP_STOP_PREPARE: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_AP_STOP_PREPARE\n", FUNC_ADPT_ARG(padapter)); + status = _ap_stop_ap_stop_notify(padapter); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s :: [MSG_EVT_AP_STOP_PREPARE] ap_stop_notify fail\n", __func__); + _ap_stop_cmd_done(pcmd); + } + break; + } + case MSG_EVT_AP_STOP: + { + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_SWCH_START\n", FUNC_ADPT_ARG(padapter)); + stop_ap_hdl(padapter); + rtw_phl_ap_stop_resume_hdlr(phl_info, wifi_role); + _ap_stop_cmd_done(pcmd); + break; + } + default: + /* unknown state */ + break; + } + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ap_stop_req_set_info(void *dispr, void *priv, struct phl_module_op_info* info) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *padapter = pcmd->padapter; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(padapter)); + + return MDL_RET_IGNORE; +} + +static enum phl_mdl_ret_code _ap_stop_req_query_info(void *dispr, void *priv, struct phl_module_op_info* info) +{ + struct cmd_obj *pcmd = (struct cmd_obj *)priv; + struct _ADAPTER *a = pcmd->padapter; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + switch (info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8*)a->phl_role; + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return ret; +} + +static void rtw_cmd_ap_stop_req_init(struct cmd_obj *pcmd, struct phl_cmd_token_req *fgreq) +{ + struct _ADAPTER *padapter = pcmd->padapter; + + RTW_DBG(FUNC_ADPT_FMT ": \n", FUNC_ADPT_ARG(padapter)); + /* Fill foreground command request */ + fgreq->module_id= PHL_FG_MDL_AP_STOP; + fgreq->priv = pcmd; + fgreq->role = padapter->phl_role; + + fgreq->acquired = _ap_stop_req_acquired; + fgreq->abort = _ap_stop_req_abort; + fgreq->msg_hdlr = _ap_stop_req_ev_hdlr; + fgreq->set_info = _ap_stop_req_set_info; + fgreq->query_info = _ap_stop_req_query_info; + + padapter->ap_stop_cmd_state = 0; + padapter->ap_stop_cmd_token = 0; +} + +enum rtw_phl_status rtw_ap_stop_cmd(struct cmd_obj *pcmd) +{ + struct _ADAPTER *padapter = pcmd->padapter; + struct phl_cmd_token_req fgreq={0}; + struct dvobj_priv *d = adapter_to_dvobj(padapter); + enum rtw_phl_status pstatus; + struct rtw_wifi_role_t *role = padapter->phl_role; + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(padapter)); + + rtw_cmd_ap_stop_req_init(pcmd, &fgreq); + + /* cmd_dispatcher would copy whole phl_cmd_token_req */ + pstatus = rtw_phl_add_cmd_token_req(d->phl, role->hw_band, &fgreq, &padapter->ap_stop_cmd_token); + if((pstatus != RTW_PHL_STATUS_SUCCESS) && + (pstatus != RTW_PHL_STATUS_PENDING)) + goto error; + + pstatus = RTW_PHL_STATUS_SUCCESS; + +error: + return pstatus; + +} + +#endif +#endif /* CONFIG_AP_MODE */ diff --git a/core/rtw_beamforming.c b/core/rtw_beamforming.c index 8eda985..5ec7987 100644 --- a/core/rtw_beamforming.c +++ b/core/rtw_beamforming.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,19 +15,86 @@ #define _RTW_BEAMFORMING_C_ #include -#include #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 +#ifdef RTW_WKARD_TX_DISABLE_BFEE +void rtw_core_bf_watchdog(_adapter *padapter) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + struct rtw_wifi_role_t *wrole = NULL; + struct rtw_phl_stainfo_t *psta = NULL; + struct rtw_stats *phl_stats = NULL; + bool enable_bfee = false; + + do { + if (padapter == NULL) + break; + + if (1 != pregpriv->dyn_txbf) { + break; + } + + wrole = padapter->phl_role; + //psta = padapter->stainfo; + + if (wrole == NULL) + break; + psta = rtw_phl_get_stainfo_self(adapter_to_dvobj(padapter)->phl, wrole); + + if (psta == NULL) + break; + + if (PHL_RTYPE_STATION != wrole->type) + break; + + if (MLME_NO_LINK == wrole->mstate) + break; + + if ((wrole->proto_role_cap.he_su_bfme || + wrole->proto_role_cap.he_mu_bfme) && + (psta->asoc_cap.he_su_bfmr || psta->asoc_cap.he_mu_bfmr)) { + enable_bfee = true; + } + + if ((wrole->proto_role_cap.vht_su_bfme || + wrole->proto_role_cap.vht_mu_bfme) && + (psta->asoc_cap.vht_su_bfmr || + psta->asoc_cap.vht_mu_bfmr)) { + enable_bfee = true; + } + + if (wrole->proto_role_cap.ht_su_bfme && + psta->asoc_cap.ht_su_bfmr) + enable_bfee = true; + + if (enable_bfee == false) + break; + + phl_stats = &(phl_com->phl_stats); + if ((phl_stats->tx_traffic.lvl > phl_stats->rx_traffic.lvl) && + (phl_stats->tx_traffic.lvl >= RTW_TFC_HIGH)) { + enable_bfee = false; + } + + /*Per wrole->hw_band to control bfee, not per hw_port*/ + rtw_phl_bfee_ctrl(GET_PHL_INFO(dvobj), wrole, enable_bfee); + /*RTW_INFO("[WKARD] Enable/Disable BFee function : BFee %d\n", enable_bfee);*/ + } while (0); +} +#endif /*RTW_WKARD_TX_DISABLE_BFEE*/ + +#if 0 struct ndpa_sta_info { u16 aid:12; u16 feedback_type:1; u16 nc_index:3; }; -static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid) +static void _get_txvector_parameter(_adapter *adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid) { struct mlme_priv *mlme; u16 aid; @@ -45,10 +112,10 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * * a DLS or TDLS peer STA */ - aid = sta->cmn.aid; + aid = sta->phl_sta->aid; bssid = adapter_mac_addr(adapter); RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n", - __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid)); + __FUNCTION__, sta->phl_sta->aid, MAC_ARG(bssid)); /* AID[0:8] */ aid &= 0x1FF; @@ -70,7 +137,7 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * *g_id = 63; } else { /* Addressed to AP */ - bssid = sta->cmn.mac_addr; + bssid = sta->phl_sta->mac_addr; RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid)); /* BSSID[39:47] */ @@ -84,23 +151,24 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * /* * Parameters - * adapter struct _adapter* + * adapter _adapter* * sta struct sta_info* * sta_bf_cap beamforming capabe of sta * sounding_dim Number of Sounding Dimensions * comp_steering Compressed Steering Number of Beamformer Antennas Supported */ -static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, +static void _get_sta_beamform_cap(_adapter *adapter, struct sta_info *sta, u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering) { struct beamforming_info *info; - struct mlme_priv *mlme; struct ht_priv *ht; - u16 ht_bf_cap; #ifdef CONFIG_80211AC_VHT struct vht_priv *vht; - u16 vht_bf_cap; #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + struct he_priv *he; +#endif /* CONFIG_80211AX_HE */ + u16 bf_cap; *sta_bf_cap = 0; @@ -112,126 +180,67 @@ static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, #ifdef CONFIG_80211AC_VHT vht = &adapter->mlmepriv.vhtpriv; #endif /* CONFIG_80211AC_VHT */ - mlme = &adapter->mlmepriv; - if (is_supported_ht(sta->wireless_mode) == _FALSE) - return; - - /* HT */ - if (check_fwstate(mlme, WIFI_AP_STATE)) { - /* Get peer clinet's BF cap: the cap. is intersected with associated AP.*/ - ht_bf_cap = sta->htpriv.beamform_cap; - RTW_INFO("At AP state, peer sta's ht_bf_cap=0x%x\n", ht_bf_cap); +#ifdef CONFIG_80211AX_HE + he = &adapter->mlmepriv.hepriv; +#endif /* CONFIG_80211AX_HE */ - if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { - info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT; - *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; - *comp_steering = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; - RTW_INFO("%s: we support BEAMFORMER_CAP_HT_EXPLICIT\n", __func__); - } - if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { - info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; - *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT; - *sounding_dim = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; - RTW_INFO("%s: we support BEAMFORMEE_CAP_HT_EXPLICIT\n", __func__); - } - } else { - /* Get adapter's BF Cap: the cap. is intersected with associated AP.*/ - ht_bf_cap = ht->beamform_cap; - RTW_INFO("At non-AP state, adapter's ht_bf_cap=0x%x\n", ht_bf_cap); + if (is_supported_ht(sta->phl_sta->wmode) == _TRUE) { + /* HT */ + bf_cap = ht->beamform_cap; - if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { + if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT; - *sounding_dim = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; - RTW_INFO("%s: we support BEAMFORMEE_CAP_HT_EXPLICIT\n", __func__); + *sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; } - if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { + if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT; *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; - *comp_steering = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; - RTW_INFO("%s: we support BEAMFORMER_CAP_HT_EXPLICIT\n", __func__); + *comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; } } #ifdef CONFIG_80211AC_VHT + if (is_supported_vht(sta->phl_sta->wmode) == _TRUE) { + /* VHT */ + bf_cap = vht->beamform_cap; - if (is_supported_vht(sta->wireless_mode) == _FALSE) - return; - - /* VHT */ - if (check_fwstate(mlme, WIFI_AP_STATE)) { - /* Get peer clinet's BF cap: the cap. is intersected with associated AP.*/ - vht_bf_cap = sta->vhtpriv.beamform_cap; - RTW_INFO("At AP state, peer sta's vht_bf_cap=0x%x\n", vht_bf_cap); - - /* We are SU Beamformer because the STA is SU Beamformee */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { - info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU; - *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU; - RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_SU\n", __func__); - - /* We are MU Beamformer because the STA is MU Beamformee */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { - info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU; - *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU; - RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_MU\n", __func__); - } - - *comp_steering = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; - } /* We are SU Beamformee because the STA is SU Beamformer */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU; *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU; - RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_SU\n", __func__); - - /* The STA is MU Beamformer, but we(AP) should not be MU Beamformee */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { - RTW_WARN("%s: Associated STA should not be a MU BFer.\n", __func__); - } - *sounding_dim = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; - } - } else { - /* Get adapter's BF Cap: the cap. is intersected with associated AP.*/ - vht_bf_cap = vht->beamform_cap; - RTW_INFO("At non-AP state, adapter's vht_bf_cap=0x%x\n", vht_bf_cap); - - /* We are SU Beamformee */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { - info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU; - *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU; - RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_SU\n", __func__); - - /* We are MU Beamformee */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { + /* We are MU Beamformee because the STA is MU Beamformer */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU; *sta_bf_cap |= BEAMFORMER_CAP_VHT_MU; - RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_MU\n", __func__); } - *sounding_dim = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + *sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; } - /* We are SU Beamformer */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + /* We are SU Beamformer because the STA is SU Beamformee */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU; *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU; - RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_SU\n", __func__); - /* We are MU Beamformer, but client should not be a MU Beamformer */ - if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { - RTW_WARN("%s: non-AP state should not support MU BFer.\n", __func__); + /* We are MU Beamformer because the STA is MU Beamformee */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU; + *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU; } - *comp_steering = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + *comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } } #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ } -static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) +static u8 _send_ht_ndpa_packet(_adapter *adapter, u8 *ra, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -269,7 +278,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) return _FALSE; } - txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer); + txrate = rtw_hal_get_htndp_tx_rate(adapter, bfee->comp_steering_num_of_bfer); /* update attribute */ attrib = &pmgntframe->attrib; @@ -277,7 +286,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ attrib->subtype = WIFI_ACTION_NOACK; attrib->bwmode = bw; - /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + /*attrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID);*/ /* set in update_mgntframe_attrib() */ attrib->order = 1; attrib->rate = (u8)txrate; attrib->bf_pkt_type = 0; @@ -289,7 +298,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) /* Frame control */ pwlanhdr->frame_ctl = 0; set_frame_sub_type(pframe, attrib->subtype); - set_order_bit(pframe); + set_htc_order_bit(pframe); /* Duration */ if (pmlmeext->cur_wireless_mode == WIRELESS_11B) @@ -329,7 +338,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) return _TRUE; } -static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw) +static u8 _send_vht_ndpa_packet(_adapter *adapter, u8 *ra, u16 aid, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -365,7 +374,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_ return _FALSE; } - txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer); + txrate = rtw_hal_get_vht_ndp_tx_rate(adapter, bfee->comp_steering_num_of_bfer); /* update attribute */ attrib = &pmgntframe->attrib; @@ -373,7 +382,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_ /*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ attrib->subtype = WIFI_NDPA; attrib->bwmode = bw; - /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + /*attrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID);*/ /* set in update_mgntframe_attrib() */ attrib->rate = (u8)txrate; attrib->bf_pkt_type = 0; @@ -386,7 +395,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_ set_frame_sub_type(pframe, attrib->subtype); /* Duration */ - if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + if (WIFI_ROLE_IS_ON_5G(adapter) || is_supported_ht(pmlmeext->cur_wireless_mode)) aSifsTime = 16; else aSifsTime = 10; @@ -435,7 +444,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_ return _TRUE; } -static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) +static u8 _send_vht_mu_ndpa_packet(_adapter *adapter, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -486,7 +495,7 @@ static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ attrib->subtype = WIFI_NDPA; attrib->bwmode = bw; - /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + /*attrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID);*/ /* set in update_mgntframe_attrib() */ attrib->rate = (u8)txrate; /* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */ if (info->sounding_info.candidate_mu_bfee_cnt > 1) @@ -503,7 +512,7 @@ static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) set_frame_sub_type(pframe, attrib->subtype); /* Duration */ - if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + if (WIFI_ROLE_IS_ON_5G(adapter) || is_supported_ht(pmlmeext->cur_wireless_mode)) aSifsTime = 16; else aSifsTime = 10; @@ -552,7 +561,7 @@ static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) return _TRUE; } -static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll) +static u8 _send_bf_report_poll(_adapter *adapter, u8 *ra, u8 bFinalPoll) { /* General */ struct xmit_priv *pxmitpriv; @@ -579,7 +588,7 @@ static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll) /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ attrib->subtype = WIFI_BF_REPORT_POLL; attrib->bwmode = CHANNEL_WIDTH_20; - /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + /*attrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID);*/ /* set in update_mgntframe_attrib() */ attrib->rate = MGN_6M; if (bFinalPoll) attrib->bf_pkt_type = 3; @@ -614,7 +623,7 @@ static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll) return _TRUE; } -static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave) +static void _sounding_update_min_period(_adapter *adapter, u16 period, u8 leave) { struct beamforming_info *info; struct beamformee_entry *bfee; @@ -659,7 +668,7 @@ static void _sounding_init(struct sounding_info *sounding) sounding->sound_remain_cnt_per_period = 0; } -static void _sounding_reset_vars(PADAPTER adapter) +static void _sounding_reset_vars(_adapter *adapter) { struct beamforming_info *info; struct sounding_info *sounding; @@ -691,7 +700,7 @@ static void _sounding_reset_vars(PADAPTER adapter) * -2 Fail to prepare sounding list, because beamformee state not ready * */ -static int _sounding_get_list(PADAPTER adapter) +static int _sounding_get_list(_adapter *adapter) { struct beamforming_info *info; struct sounding_info *sounding; @@ -778,7 +787,7 @@ static int _sounding_get_list(PADAPTER adapter) return ret; } -static void _sounding_handler(PADAPTER adapter) +static void _sounding_handler(_adapter *adapter) { struct beamforming_info *info; struct sounding_info *sounding; @@ -927,7 +936,7 @@ static void _sounding_handler(PADAPTER adapter) rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING); } -static void _sounding_force_stop(PADAPTER adapter) +static void _sounding_force_stop(_adapter *adapter) { struct beamforming_info *info; struct sounding_info *sounding; @@ -951,7 +960,7 @@ static void _sounding_force_stop(PADAPTER adapter) static void _sounding_timer_handler(void *FunctionContext) { - PADAPTER adapter; + _adapter *adapter; struct beamforming_info *info; struct sounding_info *sounding; static u8 delay = 0; @@ -959,7 +968,7 @@ static void _sounding_timer_handler(void *FunctionContext) RTW_DBG("+%s\n", __FUNCTION__); - adapter = (PADAPTER)FunctionContext; + adapter = (_adapter *)FunctionContext; info = GET_BEAMFORM_INFO(adapter); sounding = &info->sounding_info; @@ -995,7 +1004,7 @@ static void _sounding_timer_handler(void *FunctionContext) static void _sounding_timeout_timer_handler(void *FunctionContext) { - PADAPTER adapter; + _adapter *adapter; struct beamforming_info *info; struct sounding_info *sounding; struct beamformee_entry *bfee; @@ -1003,7 +1012,7 @@ static void _sounding_timeout_timer_handler(void *FunctionContext) RTW_WARN("+%s\n", __FUNCTION__); - adapter = (PADAPTER)FunctionContext; + adapter = (_adapter *)FunctionContext; info = GET_BEAMFORM_INFO(adapter); sounding = &info->sounding_info; @@ -1025,7 +1034,7 @@ static void _sounding_timeout_timer_handler(void *FunctionContext) rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1); } -static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter) +static struct beamformer_entry *_bfer_get_free_entry(_adapter *adapter) { u8 i = 0; struct beamforming_info *info; @@ -1043,7 +1052,7 @@ static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter) return NULL; } -static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra) +static struct beamformer_entry *_bfer_get_entry_by_addr(_adapter *adapter, u8 *ra) { u8 i = 0; struct beamforming_info *info; @@ -1063,7 +1072,7 @@ static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra return NULL; } -static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, +static struct beamformer_entry *_bfer_add_entry(_adapter *adapter, struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering) { struct mlme_priv *mlme; @@ -1077,7 +1086,7 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr); + bfer = _bfer_get_entry_by_addr(adapter, sta->phl_sta->mac_addr); if (!bfer) { bfer = _bfer_get_free_entry(adapter); if (!bfer) @@ -1086,14 +1095,14 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, bfer->used = _TRUE; _get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid); - _rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(bfer->mac_addr, sta->phl_sta->mac_addr, ETH_ALEN); bfer->cap = bf_cap; bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; bfer->NumofSoundingDim = sounding_dim; if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) { info->beamformer_mu_cnt += 1; - bfer->aid = sta->cmn.aid; + bfer->aid = sta->phl_sta->aid; } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { info->beamformer_su_cnt += 1; @@ -1112,7 +1121,7 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, return bfer; } -static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry) +static void _bfer_remove_entry(_adapter *adapter, struct beamformer_entry *entry) { struct beamforming_info *info; @@ -1135,18 +1144,18 @@ static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry) info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT); } -static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position) +static u8 _bfer_set_entry_gid(_adapter *adapter, u8 *addr, u8 *gid, u8 *position) { struct beamformer_entry bfer; - memset(&bfer, 0, sizeof(bfer)); - memcpy(bfer.mac_addr, addr, ETH_ALEN); + _rtw_memset(&bfer, 0, sizeof(bfer)); + _rtw_memcpy(bfer.mac_addr, addr, ETH_ALEN); /* Parsing Membership Status Array */ - memcpy(bfer.gid_valid, gid, 8); + _rtw_memcpy(bfer.gid_valid, gid, 8); /* Parsing User Position Array */ - memcpy(bfer.user_position, position, 16); + _rtw_memcpy(bfer.user_position, position, 16); /* Config HW GID table */ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer, @@ -1155,7 +1164,7 @@ static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position) return _SUCCESS; } -static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter) +static struct beamformee_entry *_bfee_get_free_entry(_adapter *adapter) { u8 i = 0; struct beamforming_info *info; @@ -1173,7 +1182,7 @@ static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter) return NULL; } -static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra) +static struct beamformee_entry *_bfee_get_entry_by_addr(_adapter *adapter, u8 *ra) { u8 i = 0; struct beamforming_info *info; @@ -1193,7 +1202,7 @@ static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra return NULL; } -static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore) +static u8 _bfee_get_first_su_entry_idx(_adapter *adapter, struct beamformee_entry *ignore) { struct beamforming_info *info; struct beamformee_entry *bfee; @@ -1226,7 +1235,7 @@ static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry * 2015.05.25. Created by tynli. * */ -static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore) +static u8 _bfee_get_first_mu_entry_idx(_adapter *adapter, struct beamformee_entry *ignore) { struct beamforming_info *info; struct beamformee_entry *bfee; @@ -1248,7 +1257,7 @@ static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry return 0xFF; } -static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, +static struct beamformee_entry *_bfee_add_entry(_adapter *adapter, struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering) { struct mlme_priv *mlme; @@ -1262,7 +1271,7 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr); + bfee = _bfee_get_entry_by_addr(adapter, sta->phl_sta->mac_addr); if (!bfee) { bfee = _bfee_get_free_entry(adapter); if (!bfee) @@ -1270,15 +1279,15 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, } bfee->used = _TRUE; - bfee->aid = sta->cmn.aid; - bfee->mac_id = sta->cmn.mac_id; - bfee->sound_bw = sta->cmn.bw_mode; + bfee->aid = sta->phl_sta->aid; + bfee->mac_id = sta->phl_sta->macid; + bfee->sound_bw = sta->phl_sta->chandef.bw; _get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid); - sta->cmn.bf_info.g_id = bfee->g_id; - sta->cmn.bf_info.p_aid = bfee->p_aid; + sta->phl_sta->bf_info.g_id = bfee->g_id; + sta->phl_sta->bf_info.p_aid = bfee->p_aid; - _rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(bfee->mac_addr, sta->phl_sta->mac_addr, ETH_ALEN); bfee->txbf = _FALSE; bfee->sounding = _FALSE; bfee->sound_period = 40; @@ -1359,7 +1368,7 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, return bfee; } -static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry) +static void _bfee_remove_entry(_adapter *adapter, struct beamformee_entry *entry) { struct beamforming_info *info; u8 idx; @@ -1402,7 +1411,7 @@ static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry) _sounding_update_min_period(adapter, 0, _TRUE); } -static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid) +static enum beamforming_cap _bfee_get_entry_cap_by_macid(_adapter *adapter, u8 macid) { struct beamforming_info *info; struct beamformee_entry *bfee; @@ -1422,7 +1431,7 @@ static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 ma return BEAMFORMING_CAP_NONE; } -static void _beamforming_enter(PADAPTER adapter, void *p) +static void _beamforming_enter(_adapter *adapter, void *p) { struct mlme_priv *mlme; struct ht_priv *htpriv; @@ -1449,23 +1458,19 @@ static void _beamforming_enter(PADAPTER adapter, void *p) info = GET_BEAMFORM_INFO(adapter); sta_copy = (struct sta_info *)p; - sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr); + sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->phl_sta->mac_addr); if (!sta) { RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n", - __FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr)); + __FUNCTION__, MAC_ARG(sta_copy->phl_sta->mac_addr)); return; } - - RTW_INFO("%s: find STA info for " MAC_FMT "\n", - __FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr)); - if (sta != sta_copy) { RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n", - __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr)); + __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->phl_sta->mac_addr)); } /* The current setting does not support Beaforming */ - wireless_mode = sta->wireless_mode; + wireless_mode = sta->phl_sta->wmode; if ((is_supported_ht(wireless_mode) == _FALSE) && (is_supported_vht(wireless_mode) == _FALSE)) { RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__); @@ -1475,6 +1480,9 @@ static void _beamforming_enter(PADAPTER adapter, void *p) if ((0 == htpriv->beamform_cap) #ifdef CONFIG_80211AC_VHT && (0 == vhtpriv->beamform_cap) +#endif +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ #endif ) { RTW_INFO("The configuration disabled Beamforming! Skip...\n"); @@ -1523,12 +1531,12 @@ static void _beamforming_enter(PADAPTER adapter, void *p) } } -static void _beamforming_reset(PADAPTER adapter) +static void _beamforming_reset(_adapter *adapter) { RTW_ERR("%s: Not ready!!\n", __FUNCTION__); } -static void _beamforming_leave(PADAPTER adapter, u8 *ra) +static void _beamforming_leave(_adapter *adapter, u8 *ra) { struct beamforming_info *info; struct beamformer_entry *bfer = NULL; @@ -1566,7 +1574,7 @@ static void _beamforming_leave(PADAPTER adapter, u8 *ra) RTW_INFO("-%s\n", __FUNCTION__); } -static void _beamforming_sounding_down(PADAPTER adapter, u8 status) +static void _beamforming_sounding_down(_adapter *adapter, u8 status) { struct beamforming_info *info; struct sounding_info *sounding; @@ -1627,7 +1635,7 @@ static void _beamforming_sounding_down(PADAPTER adapter, u8 status) rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0); } -static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len) +static void _c2h_snd_txbf(_adapter *adapter, u8 *buf, u8 buf_len) { struct beamforming_info *info; u8 res; @@ -1648,7 +1656,7 @@ static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len) */ enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid) { - PADAPTER adapter; + _adapter *adapter; enum beamforming_cap cap = BEAMFORMING_CAP_NONE; @@ -1658,22 +1666,22 @@ enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid) return cap; } -struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra) +struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(_adapter *adapter, u8 *ra) { return _bfer_get_entry_by_addr(adapter, ra); } -struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra) +struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(_adapter *adapter, u8 *ra) { return _bfee_get_entry_by_addr(adapter, ra); } -void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame) +void rtw_bf_get_ndpa_packet(_adapter *adapter, union recv_frame *precv_frame) { RTW_DBG("+%s\n", __FUNCTION__); } -u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame) +u32 rtw_bf_get_report_packet(_adapter *adapter, union recv_frame *precv_frame) { u32 ret = _SUCCESS; struct beamforming_info *info; @@ -1758,7 +1766,7 @@ u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame) return ret; } -u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position) +u8 rtw_bf_send_vht_gid_mgnt_packet(_adapter *adapter, u8 *ra, u8 *gid, u8 *position) { /* General */ struct xmit_priv *xmitpriv; @@ -1820,7 +1828,7 @@ u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *positi * Description: * On VHT GID management frame by an MU beamformee. */ -void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame) +void rtw_bf_get_vht_gid_mgnt_packet(_adapter *adapter, union recv_frame *precv_frame) { u8 *pframe; u8 *ta, *gid, *position; @@ -1843,7 +1851,7 @@ void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_fr _bfer_set_entry_gid(adapter, ta, gid, position); } -void rtw_bf_init(PADAPTER adapter) +void rtw_bf_init(_adapter *adapter) { struct beamforming_info *info; @@ -1868,8 +1876,8 @@ void rtw_bf_init(PADAPTER adapter) info->cur_csi_rpt_rate = HALMAC_OFDM24; _sounding_init(&info->sounding_info); - rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter); - rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter); + rtw_init_timer(&info->sounding_timer, _sounding_timer_handler, adapter); + rtw_init_timer(&info->sounding_timeout_timer, _sounding_timeout_timer_handler, adapter); info->SetHalBFEnterOnDemandCnt = 0; info->SetHalBFLeaveOnDemandCnt = 0; @@ -1881,7 +1889,7 @@ void rtw_bf_init(PADAPTER adapter) info->sounding_running = 0; } -void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf) +void rtw_bf_cmd_hdl(_adapter *adapter, u8 type, u8 *pbuf) { switch (type) { case BEAMFORMING_CTRL_ENTER: @@ -1916,29 +1924,29 @@ void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf) } } -u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) +u8 rtw_bf_cmd(_adapter *adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) { - struct cmd_obj *ph2c; + struct cmd_obj *cmd; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 *wk_buf; u8 res = _SUCCESS; - if (!enqueue) { rtw_bf_cmd_hdl(adapter, type, pbuf); goto exit; } - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = adapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -1946,7 +1954,7 @@ u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) if (pbuf != NULL) { wk_buf = rtw_zmalloc(size); if (wk_buf == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd, sizeof(struct cmd_obj)); rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); res = _FAIL; goto exit; @@ -1963,23 +1971,26 @@ u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) pdrvextra_cmd_parm->size = size; pdrvextra_cmd_parm->pbuf = wk_buf; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: return res; } -void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta) +void rtw_bf_update_attrib(_adapter *adapter, struct pkt_attrib *attrib, struct sta_info *sta) { +/* bf_cmn_info move to hal_sta */ +#if 0 if (sta) { - attrib->txbf_g_id = sta->cmn.bf_info.g_id; - attrib->txbf_p_aid = sta->cmn.bf_info.p_aid; + attrib->txbf_g_id = sta->phl_sta->bf_info.g_id; + attrib->txbf_p_aid = sta->phl_sta->bf_info.p_aid; } +#endif } -void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len) +void rtw_bf_c2h_handler(_adapter *adapter, u8 id, u8 *buf, u8 buf_len) { switch (id) { case CMD_ID_C2H_SND_TXBF: @@ -1989,7 +2000,7 @@ void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len) } #define toMbps(bytes, secs) (rtw_division64(bytes >> 17, secs)) -void rtw_bf_update_traffic(PADAPTER adapter) +void rtw_bf_update_traffic(_adapter *adapter) { struct beamforming_info *info; struct sounding_info *sounding; @@ -2035,13 +2046,13 @@ void rtw_bf_update_traffic(PADAPTER adapter) time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp); time = (time > 1000) ? time/1000 : 1; tp[i] = toMbps(tx_bytes, time); - tx_rate[i] = rtw_get_current_tx_rate(adapter, sta); + tx_rate[i] = rtw_hal_get_current_tx_rate(adapter, sta); RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n", __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]); } } - sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate); + sounding_idx = rtw_hal_get_sounding_info(adapter, tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate); for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { bfee = &info->bfee_entry[i]; @@ -2074,121 +2085,5 @@ void rtw_bf_update_traffic(PADAPTER adapter) } } } - -#else /* !RTW_BEAMFORMING_VERSION_2 */ - -/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/ -u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame) -{ - u32 ret = _SUCCESS; - - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_struct *pDM_Odm = &(pHalData->odmpriv); - - ret = beamforming_get_report_frame(pDM_Odm, precv_frame); - return ret; -} - -void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_struct *pDM_Odm = &(pHalData->odmpriv); - - beamforming_get_ndpa_frame(pDM_Odm, precv_frame); -} - -void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &(pHalData->odmpriv); - - /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/ - switch (type) { - case BEAMFORMING_CTRL_ENTER: { - struct sta_info *psta = (void *)pbuf; - u16 staIdx = psta->cmn.mac_id; - - beamforming_enter(pDM_Odm, staIdx, adapter_mac_addr(psta->padapter)); - break; - } - case BEAMFORMING_CTRL_LEAVE: - beamforming_leave(pDM_Odm, pbuf); - break; - default: - break; - - } -} - -u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) -{ - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 res = _SUCCESS; - - /*20170214 ad_hoc mode and mp_mode not support BF*/ - if ((padapter->registrypriv.mp_mode == 1) - || (pmlmeinfo->state == WIFI_FW_ADHOC_STATE)) - return res; - - if (enqueue) { - u8 *wk_buf; - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; - } - - if (pbuf != NULL) { - wk_buf = rtw_zmalloc(size); - if (wk_buf == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); - rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); - res = _FAIL; - goto exit; - } - - _rtw_memcpy(wk_buf, pbuf, size); - } else { - wk_buf = NULL; - size = 0; - } - - pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID; - pdrvextra_cmd_parm->type = type; - pdrvextra_cmd_parm->size = size; - pdrvextra_cmd_parm->pbuf = wk_buf; - - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - } else - beamforming_wk_hdl(padapter, type, pbuf); - -exit: - - - return res; -} - -void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) -{ - if (psta) { - pattrib->txbf_g_id = psta->cmn.bf_info.g_id; - pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid; - } -} -#endif /* !RTW_BEAMFORMING_VERSION_2 */ - +#endif #endif /* CONFIG_BEAMFORMING */ diff --git a/core/rtw_br_ext.c b/core/rtw_br_ext.c index 9d09a7d..26e17f6 100644 --- a/core/rtw_br_ext.c +++ b/core/rtw_br_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,6 +17,8 @@ #ifdef __KERNEL__ #include #include + #include + #include #include #include #endif @@ -55,6 +57,8 @@ #define NAT25_IPV4 01 #define NAT25_IPV6 02 +#define NAT25_IPX 03 +#define NAT25_APPLE 04 #define NAT25_PPPOE 05 #define RTL_RELAY_TAG_LEN (ETH_ALEN) @@ -108,9 +112,9 @@ static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_ta skb_put(skb, data_len); /* have a room for new tag */ - memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); + _rtw_memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); ph->length = htons(ntohs(ph->length) + data_len); - memcpy((unsigned char *)ph->tag, tag, data_len); + _rtw_memcpy((unsigned char *)ph->tag, tag, data_len); return data_len; } @@ -129,7 +133,7 @@ static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len) tail_len = (int)(tail - end); if (tail_len > 0) - memmove(src, src + len, tail_len); + _rtw_memmove(src, src + len, tail_len); skb_trim(skb, skb->len - len); return 0; @@ -158,21 +162,54 @@ static __inline__ int __nat25_has_expired(_adapter *priv, static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr, unsigned int *ipAddr) { - memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); networkAddr[0] = NAT25_IPV4; - memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4); + _rtw_memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4); +} + + +static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) +{ + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + _rtw_memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4); + _rtw_memcpy(networkAddr + 5, ipxNodeAddr, 6); +} + + +static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr) +{ + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + _rtw_memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4); + _rtw_memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2); +} + + +static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, + unsigned short *network, unsigned char *node) +{ + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_APPLE; + _rtw_memcpy(networkAddr + 1, (unsigned char *)network, 2); + networkAddr[3] = *node; } static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr, unsigned char *ac_mac, unsigned short *sid) { - memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); networkAddr[0] = NAT25_PPPOE; - memcpy(networkAddr + 1, (unsigned char *)sid, 2); - memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6); + _rtw_memcpy(networkAddr + 1, (unsigned char *)sid, 2); + _rtw_memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6); } @@ -180,10 +217,10 @@ static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networ static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr, unsigned int *ipAddr) { - memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + _rtw_memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); networkAddr[0] = NAT25_IPV6; - memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16); + _rtw_memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16); } @@ -212,7 +249,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char RTW_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); - memcpy(mac, replace_mac, 6); + _rtw_memcpy(mac, replace_mac, 6); return 1; } } @@ -223,7 +260,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char RTW_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); - memcpy(mac, replace_mac, 6); + _rtw_memcpy(mac, replace_mac, 6); return 1; } } @@ -234,7 +271,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char RTW_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); - memcpy(mac, replace_mac, 6); + _rtw_memcpy(mac, replace_mac, 6); return 1; } } @@ -245,7 +282,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char RTW_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); - memcpy(mac, replace_mac, 6); + _rtw_memcpy(mac, replace_mac, 6); return 1; } } @@ -256,7 +293,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char RTW_INFO("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); - memcpy(mac, replace_mac, 6); + _rtw_memcpy(mac, replace_mac, 6); return 1; } } @@ -275,7 +312,7 @@ static void convert_ipv6_mac_to_mc(struct sk_buff *skb) /*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/ dst_mac[0] = 0x33; dst_mac[1] = 0x33; - memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4); + _rtw_memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4); #if defined(__LINUX_2_6__) /*modified by qinjunjie,warning:should not remove next line*/ skb->pkt_type = PACKET_MULTICAST; @@ -292,6 +329,19 @@ static __inline__ int __nat25_network_hash(unsigned char *networkAddr) x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + return x & (NAT25_HASH_SIZE - 1); + } else if (networkAddr[0] == NAT25_IPX) { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); + } else if (networkAddr[0] == NAT25_APPLE) { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3]; + return x & (NAT25_HASH_SIZE - 1); } else if (networkAddr[0] == NAT25_PPPOE) { unsigned long x; @@ -327,9 +377,8 @@ static __inline__ int __nat25_network_hash(unsigned char *networkAddr) static __inline__ void __network_hash_link(_adapter *priv, struct nat25_network_db_entry *ent, int hash) { - /* Caller must _enter_critical_bh already! */ - /* _irqL irqL; */ - /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + /* Caller must _rtw_spinlock_bh already! */ + /* _rtw_spinlock_bh(&priv->br_ext_lock); */ ent->next_hash = priv->nethash[hash]; if (ent->next_hash != NULL) @@ -337,15 +386,14 @@ static __inline__ void __network_hash_link(_adapter *priv, priv->nethash[hash] = ent; ent->pprev_hash = &priv->nethash[hash]; - /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + /* _rtw_spinunlock_bh(&priv->br_ext_lock); */ } static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) { - /* Caller must _enter_critical_bh already! */ - /* _irqL irqL; */ - /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + /* Caller must _rtw_spinlock_bh already! */ + /* _rtw_spinlock_bh(&priv->br_ext_lock); */ *(ent->pprev_hash) = ent->next_hash; if (ent->next_hash != NULL) @@ -353,7 +401,7 @@ static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) ent->next_hash = NULL; ent->pprev_hash = NULL; - /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + /* _rtw_spinunlock_bh(&priv->br_ext_lock); */ } @@ -361,15 +409,14 @@ static int __nat25_db_network_lookup_and_replace(_adapter *priv, struct sk_buff *skb, unsigned char *networkAddr) { struct nat25_network_db_entry *db; - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinlock_bh(&priv->br_ext_lock); db = priv->nethash[__nat25_network_hash(networkAddr)]; while (db != NULL) { - if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + if (!_rtw_memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { if (!__nat25_has_expired(priv, db)) { /* replace the destination mac address */ - memcpy(skb->data, db->macAddr, ETH_ALEN); + _rtw_memcpy(skb->data, db->macAddr, ETH_ALEN); atomic_inc(&db->use_count); #ifdef CL_IPV6_PASS @@ -419,14 +466,14 @@ static int __nat25_db_network_lookup_and_replace(_adapter *priv, db->networkAddr[10]); #endif } - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); return 1; } db = db->next_hash; } - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); return 0; } @@ -436,16 +483,16 @@ static void __nat25_db_network_insert(_adapter *priv, { struct nat25_network_db_entry *db; int hash; - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + + _rtw_spinlock_bh(&priv->br_ext_lock); hash = __nat25_network_hash(networkAddr); db = priv->nethash[hash]; while (db != NULL) { - if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { - memcpy(db->macAddr, macAddr, ETH_ALEN); + if (!_rtw_memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + _rtw_memcpy(db->macAddr, macAddr, ETH_ALEN); db->ageing_timer = jiffies; - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); return; } @@ -454,25 +501,25 @@ static void __nat25_db_network_insert(_adapter *priv, db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db)); if (db == NULL) { - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); return; } - memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); - memcpy(db->macAddr, macAddr, ETH_ALEN); + _rtw_memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); + _rtw_memcpy(db->macAddr, macAddr, ETH_ALEN); atomic_set(&db->use_count, 1); db->ageing_timer = jiffies; __network_hash_link(priv, db, hash); - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); } static void __nat25_db_print(_adapter *priv) { - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + + _rtw_spinlock_bh(&priv->br_ext_lock); #ifdef BR_EXT_DEBUG static int counter = 0; @@ -546,7 +593,7 @@ static void __nat25_db_print(_adapter *priv) } #endif - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); } @@ -559,8 +606,8 @@ static void __nat25_db_print(_adapter *priv) void nat25_db_cleanup(_adapter *priv) { int i; - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + + _rtw_spinlock_bh(&priv->br_ext_lock); for (i = 0; i < NAT25_HASH_SIZE; i++) { struct nat25_network_db_entry *f; @@ -570,8 +617,8 @@ void nat25_db_cleanup(_adapter *priv) g = f->next_hash; if (priv->scdb_entry == f) { - memset(priv->scdb_mac, 0, ETH_ALEN); - memset(priv->scdb_ip, 0, 4); + _rtw_memset(priv->scdb_mac, 0, ETH_ALEN); + _rtw_memset(priv->scdb_ip, 0, 4); priv->scdb_entry = NULL; } __network_hash_unlink(f); @@ -581,15 +628,15 @@ void nat25_db_cleanup(_adapter *priv) } } - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); } void nat25_db_expire(_adapter *priv) { int i; - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + + _rtw_spinlock_bh(&priv->br_ext_lock); /* if(!priv->ethBrExtInfo.nat25_disable) */ { @@ -655,8 +702,8 @@ void nat25_db_expire(_adapter *priv) #endif #endif if (priv->scdb_entry == f) { - memset(priv->scdb_mac, 0, ETH_ALEN); - memset(priv->scdb_ip, 0, 4); + _rtw_memset(priv->scdb_mac, 0, ETH_ALEN); + _rtw_memset(priv->scdb_ip, 0, 4); priv->scdb_entry = NULL; } __network_hash_unlink(f); @@ -669,7 +716,7 @@ void nat25_db_expire(_adapter *priv) } } - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); } @@ -691,8 +738,8 @@ static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int continue; for (i = 0; i < MAX_IP_MC_ENTRY; i++) { - if (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) { - memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN); + if (pstat->ipmc[i].used && !_rtw_memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) { + _rtw_memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN); return 1; } } @@ -759,7 +806,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) if (*((unsigned char *)&iph->daddr + 3) == 0xff) { /* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */ RTW_INFO("NAT25: Set DA as boardcast\n"); - memset(skb->data, 0xff, ETH_ALEN); + _rtw_memset(skb->data, 0xff, ETH_ALEN); } else { /* forward unknow IP packet to upper TCP/IP */ RTW_INFO("NAT25: Replace DA with BR's MAC\n"); @@ -768,7 +815,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) printk("Re-init netdev_br_init() due to br_mac==0!\n"); netdev_br_init(priv->pnetdev); } - memcpy(skb->data, priv->br_mac, ETH_ALEN); + _rtw_memcpy(skb->data, priv->br_mac, ETH_ALEN); } } } @@ -802,7 +849,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]); /* change to ARP sender mac address to wlan STA address */ - memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); + _rtw_memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); arp_ptr += arp->ar_hln; sender = (unsigned int *)arp_ptr; @@ -830,7 +877,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) /* change to ARP target mac address to Lookup result */ arp_ptr = (unsigned char *)(arp + 1); arp_ptr += (arp->ar_hln + arp->ar_pln); - memcpy(arp_ptr, skb->data, ETH_ALEN); + _rtw_memcpy(arp_ptr, skb->data, ETH_ALEN); } return 0; @@ -839,6 +886,226 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) } } + /*---------------------------------------------------*/ + /* Handle IPX and Apple Talk frame */ + /*---------------------------------------------------*/ + else if ((protocol == __constant_htons(ETH_P_IPX)) || + (protocol == __constant_htons(ETH_P_ATALK)) || + (protocol == __constant_htons(ETH_P_AARP))) { + unsigned char ipx_header[2] = {0xFF, 0xFF}; + struct ipxhdr *ipx = NULL; + struct elapaarp *ea = NULL; + struct ddpehdr *ddp = NULL; + unsigned char *framePtr = skb->data + ETH_HLEN; + + if (protocol == __constant_htons(ETH_P_IPX)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet II)\n"); + ipx = (struct ipxhdr *)framePtr; + } else { /* if(protocol <= __constant_htons(ETH_FRAME_LEN)) */ + if (!_rtw_memcmp(ipx_header, framePtr, 2)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n"); + ipx = (struct ipxhdr *)framePtr; + } else { + unsigned char ipx_8022_type = 0xE0; + unsigned char snap_8022_type = 0xAA; + + if (*framePtr == snap_8022_type) { + unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; /* IPX SNAP ID */ + unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; /* Apple Talk AARP SNAP ID */ + unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; /* Apple Talk DDP SNAP ID */ + + framePtr += 3; /* eliminate the 802.2 header */ + + if (!_rtw_memcmp(ipx_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + RTW_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n"); + ipx = (struct ipxhdr *)framePtr; + } else if (!_rtw_memcmp(aarp_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + ea = (struct elapaarp *)framePtr; + } else if (!_rtw_memcmp(ddp_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + ddp = (struct ddpehdr *)framePtr; + } else { + DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0], + framePtr[1], framePtr[2], framePtr[3], framePtr[4]); + return -1; + } + } else if (*framePtr == ipx_8022_type) { + framePtr += 3; /* eliminate the 802.2 header */ + + if (!_rtw_memcmp(ipx_header, framePtr, 2)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n"); + ipx = (struct ipxhdr *)framePtr; + } else + return -1; + } + } + } + + /* IPX */ + if (ipx != NULL) { + switch (method) { + case NAT25_CHECK: + if (!_rtw_memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) { + RTW_INFO("NAT25: Check IPX skb_copy\n"); + return 0; + } + return -1; + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n", + ipx->ipx_dest.net, + ipx->ipx_dest.node[0], + ipx->ipx_dest.node[1], + ipx->ipx_dest.node[2], + ipx->ipx_dest.node[3], + ipx->ipx_dest.node[4], + ipx->ipx_dest.node[5], + ipx->ipx_dest.sock, + ipx->ipx_source.net, + ipx->ipx_source.node[0], + ipx->ipx_source.node[1], + ipx->ipx_source.node[2], + ipx->ipx_source.node[3], + ipx->ipx_source.node[4], + ipx->ipx_source.node[5], + ipx->ipx_source.sock); + + if (!_rtw_memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) { + RTW_INFO("NAT25: Use IPX Net, and Socket as network addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock); + + /* change IPX source node addr to wlan STA address */ + _rtw_memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN); + } else + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + if (!_rtw_memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) { + RTW_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + /* replace IPX destination node addr with Lookup destination MAC addr */ + _rtw_memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN); + } else { + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + } + return 0; + + default: + return -1; + } + } + + /* AARP */ + else if (ea != NULL) { + /* Sanity check fields. */ + if (ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) { + DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n"); + return -1; + } + + switch (method) { + case NAT25_CHECK: + return 0; + + case NAT25_INSERT: { + /* change to AARP source mac address to wlan STA address */ + _rtw_memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN); + + RTW_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + /* change to AARP destination mac address to Lookup result */ + _rtw_memcpy(ea->hw_dst, skb->data, ETH_ALEN); + } + return 0; + + default: + return -1; + } + } + + /* DDP */ + else if (ddp != NULL) { + switch (method) { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + return 0; + + default: + return -1; + } + } + + return -1; + } /*---------------------------------------------------*/ /* Handle PPPoE frame */ @@ -871,7 +1138,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) return -1; } - memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN, + _rtw_memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN, pOldTag->tag_data, old_tag_len); if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) { @@ -887,7 +1154,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) /* insert the magic_code+client mac in relay tag */ pMagic = (unsigned short *)tag->tag_data; *pMagic = htons(MAGIC_CODE); - memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN); + _rtw_memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN); /* Add relay tag */ if (__nat25_add_pppoe_tag(skb, tag) < 0) @@ -897,13 +1164,13 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) (ph->code == PADI_CODE ? "PADI" : "PADR")); } else { /* not add relay tag */ if (priv->pppoe_connection_in_progress && - memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { + _rtw_memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n"); return -2; } if (priv->pppoe_connection_in_progress == 0) - memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN); + _rtw_memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN); priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; } @@ -920,7 +1187,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) if (!priv->ethBrExtInfo.addPPPoETag && priv->pppoe_connection_in_progress && - !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) + !_rtw_memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) priv->pppoe_connection_in_progress = 0; } return 0; @@ -955,7 +1222,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) return -1; } - memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN); + _rtw_memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN); if (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN) offset = TAG_HDR_LEN; @@ -975,7 +1242,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n"); return -1; } - memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); + _rtw_memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; } } else { @@ -1062,7 +1329,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3], iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]); - if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { + if (_rtw_memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr); __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); __nat25_db_print(priv); @@ -1144,8 +1411,7 @@ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) } if (!priv->ethBrExtInfo.nat25_disable) { - _irqL irqL; - _enter_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinlock_bh(&priv->br_ext_lock); /* * This function look up the destination network address from * the NAT2.5 database. Return value = -1 means that the @@ -1153,20 +1419,20 @@ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) */ if (!priv->ethBrExtInfo.nat25sc_disable && (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) && - !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) { - memcpy(skb->data, priv->scdb_mac, ETH_ALEN); + !_rtw_memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) { + _rtw_memcpy(skb->data, priv->scdb_mac, ETH_ALEN); - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); } else { - _exit_critical_bh(&priv->br_ext_lock, &irqL); + _rtw_spinunlock_bh(&priv->br_ext_lock); retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); } } else { if (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) && - !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) || + !_rtw_memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) || ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) && - !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) { + !_rtw_memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) { /* for traffic to upper TCP/IP */ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); } @@ -1194,7 +1460,7 @@ void mac_clone(_adapter *priv, unsigned char *addr) { struct sockaddr sa; - memcpy(sa.sa_data, addr, ETH_ALEN); + _rtw_memcpy(sa.sa_data, addr, ETH_ALEN); RTW_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); rtl8192cd_set_hwaddr(priv->dev, &sa); @@ -1205,9 +1471,9 @@ int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb) { if (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) { if (!(skb->data[ETH_ALEN] & 1)) { /* check any other particular MAC add */ - if (memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) && + if (_rtw_memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) && ((priv->dev->br_port) && - memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) { + _rtw_memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) { mac_clone(priv, skb->data + ETH_ALEN); priv->macclone_completed = 1; } @@ -1289,22 +1555,22 @@ void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; struct nat25_network_db_entry *db; int hash; - /* _irqL irqL; */ - /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + + /* _rtw_spinlock_bh(&priv->br_ext_lock); */ __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr); hash = __nat25_network_hash(networkAddr); db = priv->nethash[hash]; while (db != NULL) { - if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { - /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + if (!_rtw_memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + /* _rtw_spinunlock_bh(&priv->br_ext_lock); */ return (void *)db; } db = db->next_hash; } - /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + /* _rtw_spinunlock_bh(&priv->br_ext_lock); */ return NULL; } diff --git a/core/rtw_btc.c b/core/rtw_btc.c new file mode 100644 index 0000000..573d867 --- /dev/null +++ b/core/rtw_btc.c @@ -0,0 +1,107 @@ +/****************************************************************************** + * + * Copyright(c) 2013 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifdef CONFIG_BTC + +#include + +typedef struct _btcdbginfo { + void* p_msgprn_hdl; + struct submit_ctx btc_dbg_info_sctx; +} BTCDBGINFO, *PBTCDBGINFO; + +BTCDBGINFO GLBtcDbgInfo; + +#define BTC_INFO_DUMP_TIMEOUT_MS 3000 + +static void rtw_btc_info_dump_init(_adapter *padapter) +{ + GLBtcDbgInfo.p_msgprn_hdl = NULL; +} + +static void rtw_btc_info_dump_set(_adapter *padapter, void* p_msgprn_hdl, u32 timeout_ms) +{ + GLBtcDbgInfo.p_msgprn_hdl = p_msgprn_hdl; + rtw_sctx_init(&GLBtcDbgInfo.btc_dbg_info_sctx, timeout_ms); +} + +static void rtw_btc_info_dump(const char *pmsg) +{ + if (GLBtcDbgInfo.p_msgprn_hdl == NULL) + return; + + _RTW_PRINT_SEL(GLBtcDbgInfo.p_msgprn_hdl, "%s", pmsg); +} + +static int rtw_btc_info_dump_callback(void *priv, enum RTW_PHL_BTC_NOTIFY ntfy, struct rtw_phl_btc_ntfy *info) +{ + struct submit_ctx *sctx = &GLBtcDbgInfo.btc_dbg_info_sctx; + + rtw_sctx_done(&sctx); + + return 0; +} + +static int rtw_btc_info_dump_wait(_adapter *padapter) +{ + return rtw_sctx_wait(&GLBtcDbgInfo.btc_dbg_info_sctx, __func__); +} + +void rtw_btc_disp_btc_info(_adapter *padapter, void* p_msgprn_hdl, u8 info_type) +{ + struct rtw_phl_btc_ntfy ntfy = {0}; + struct rtw_phl_btc_coex_info_param *pcinfo = &ntfy.u.cinfo; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_btc_ops phl_btc_ops = {rtw_btc_info_dump}; + + pcinfo->query_type = info_type; + + ntfy.notify = PHL_BTC_NTFY_COEX_INFO; + ntfy.ops = &phl_btc_ops; + ntfy.priv = padapter; + ntfy.ntfy_cb = rtw_btc_info_dump_callback; + + rtw_btc_info_dump_set(padapter, p_msgprn_hdl, BTC_INFO_DUMP_TIMEOUT_MS); + + rtw_phl_btc_notify(dvobj->phl, ntfy.notify, &ntfy); + + /* wait here until info dump finishes or timeout expires */ + rtw_btc_info_dump_wait(padapter); + + rtw_btc_info_dump_init(padapter); +} + +void rtw_btc_set_dbg(_adapter *padapter, u32 *pDbgModule) +{ +} + +u32 rtw_btc_get_dbg(_adapter *padapter, u8 *pStrBuf, u32 bufSize) +{ + return 0; +} + +#if 0 +u16 rtw_btc_btreg_read(_adapter *padapter, u8 type, u16 addr, u32 *data) +{ + return 0; +} + +u16 rtw_btc_btreg_write(_adapter *padapter, u8 type, u16 addr, u16 val) +{ + return _SUCCESS; +} +#endif + +#endif /* CONFIG_BTC */ + diff --git a/core/rtw_chplan.c b/core/rtw_chplan.c index 82b3671..eb8de60 100644 --- a/core/rtw_chplan.c +++ b/core/rtw_chplan.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2018 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,9 +16,75 @@ #include -#define RTW_DOMAIN_MAP_VER "54" -#define RTW_DOMAIN_MAP_M_VER "g" -#define RTW_COUNTRY_MAP_VER "27" +#ifndef USE_RTW_REGD +#define USE_RTW_REGD 0 +#endif + +#if defined(PHL_FEATURE_NIC) +/* +* some PHL regulation APIs doesn't have pure database query function, even have, still need pointer of phl as context +* here use a global variable to workaround, this is workable for one-driver-one-dev situation +*/ +static void *phl_info; + +static enum rtw_regd phl_regulation_to_regd(enum REGULATION reg) +{ + switch (reg) { + case REGULATION_WW: + return RTW_REGD_WW; + case REGULATION_ETSI: + return RTW_REGD_ETSI; + case REGULATION_FCC: + return RTW_REGD_FCC; + case REGULATION_MKK: + return RTW_REGD_MKK; + case REGULATION_KCC: + return RTW_REGD_KCC; + case REGULATION_NCC: + return RTW_REGD_NCC; + case REGULATION_ACMA: + return RTW_REGD_ACMA; + case REGULATION_NA: + return RTW_REGD_NA; + case REGULATION_IC: + return RTW_REGD_IC; + case REGULATION_CHILE: + return RTW_REGD_CHILE; + case REGULATION_MEX: + return RTW_REGD_MEX; + case REGULATION_MAX: + default: + RTW_WARN("unknown reg:%d\n", reg); + rtw_warn_on(1); + return RTW_REGD_NA; + } +}; + +static REGULATION_TXPWR_LMT phl_tpo_to_txpwr_lmt(enum TP_OVERWRITE tpo) +{ + switch (tpo) { + case TPO_CHILE: + return TXPWR_LMT_CHILE; + case TPO_QATAR: + return TXPWR_LMT_QATAR; + case TPO_UKRAINE: + return TXPWR_LMT_UKRAINE; + case TPO_CN: + return TXPWR_LMT_CN; + case TPO_NA: + return TXPWR_LMT_DEF; + default: + RTW_WARN("unknown tpo:%d\n", tpo); + rtw_warn_on(1); + return TXPWR_LMT_DEF; + } +} +#endif + +#if USE_RTW_REGD +#define RTW_DOMAIN_MAP_VER "57" +#define RTW_DOMAIN_MAP_M_VER "h" +#define RTW_COUNTRY_MAP_VER "31" struct ch_list_t { u8 *len_ch_attr; @@ -34,6 +100,11 @@ struct ch_list_t { #define CLA_5G_B3_DFS BIT5 #define CLA_5G_B4_DFS BIT6 +#define CLA_6G_B1_PASSIVE BIT0 +#define CLA_6G_B2_PASSIVE BIT1 +#define CLA_6G_B3_PASSIVE BIT2 +#define CLA_6G_B4_PASSIVE BIT3 + #define CH_LIST_ENT(_len, arg...) \ {.len_ch_attr = (u8[_len + 2]) {_len, ##arg}, } @@ -42,390 +113,721 @@ struct ch_list_t { #define CH_LIST_ATTRIB(_ch_list) (_ch_list.len_ch_attr[CH_LIST_LEN(_ch_list) + 1]) enum rtw_chd_2g { - RTW_CHD_2G_00 = 0, - RTW_CHD_2G_01 = 1, - RTW_CHD_2G_02 = 2, - RTW_CHD_2G_03 = 3, - RTW_CHD_2G_04 = 4, - RTW_CHD_2G_05 = 5, - RTW_CHD_2G_06 = 6, + RTW_CHD_2G_INVALID = 0, + + RTW_CHD_2G_00, + RTW_CHD_2G_01, + RTW_CHD_2G_02, + RTW_CHD_2G_03, + RTW_CHD_2G_04, + RTW_CHD_2G_05, + RTW_CHD_2G_06, RTW_CHD_2G_MAX, RTW_CHD_2G_NULL = RTW_CHD_2G_00, }; enum rtw_chd_5g { - RTW_CHD_5G_00 = 0, - RTW_CHD_5G_01 = 1, - RTW_CHD_5G_02 = 2, - RTW_CHD_5G_03 = 3, - RTW_CHD_5G_04 = 4, - RTW_CHD_5G_05 = 5, - RTW_CHD_5G_06 = 6, - RTW_CHD_5G_07 = 7, - RTW_CHD_5G_08 = 8, - RTW_CHD_5G_09 = 9, - RTW_CHD_5G_10 = 10, - RTW_CHD_5G_11 = 11, - RTW_CHD_5G_12 = 12, - RTW_CHD_5G_13 = 13, - RTW_CHD_5G_14 = 14, - RTW_CHD_5G_15 = 15, - RTW_CHD_5G_16 = 16, - RTW_CHD_5G_17 = 17, - RTW_CHD_5G_18 = 18, - RTW_CHD_5G_19 = 19, - RTW_CHD_5G_20 = 20, - RTW_CHD_5G_21 = 21, - RTW_CHD_5G_22 = 22, - RTW_CHD_5G_23 = 23, - RTW_CHD_5G_24 = 24, - RTW_CHD_5G_25 = 25, - RTW_CHD_5G_26 = 26, - RTW_CHD_5G_27 = 27, - RTW_CHD_5G_28 = 28, - RTW_CHD_5G_29 = 29, - RTW_CHD_5G_30 = 30, - RTW_CHD_5G_31 = 31, - RTW_CHD_5G_32 = 32, - RTW_CHD_5G_33 = 33, - RTW_CHD_5G_34 = 34, - RTW_CHD_5G_35 = 35, - RTW_CHD_5G_36 = 36, - RTW_CHD_5G_37 = 37, - RTW_CHD_5G_38 = 38, - RTW_CHD_5G_39 = 39, - RTW_CHD_5G_40 = 40, - RTW_CHD_5G_41 = 41, - RTW_CHD_5G_42 = 42, - RTW_CHD_5G_43 = 43, - RTW_CHD_5G_44 = 44, - RTW_CHD_5G_45 = 45, - RTW_CHD_5G_46 = 46, - RTW_CHD_5G_47 = 47, - RTW_CHD_5G_48 = 48, - RTW_CHD_5G_49 = 49, - RTW_CHD_5G_50 = 50, - RTW_CHD_5G_51 = 51, + RTW_CHD_5G_INVALID = 0, + + RTW_CHD_5G_00, + RTW_CHD_5G_01, + RTW_CHD_5G_02, + RTW_CHD_5G_03, + RTW_CHD_5G_04, + RTW_CHD_5G_05, + RTW_CHD_5G_06, + RTW_CHD_5G_07, + RTW_CHD_5G_08, + RTW_CHD_5G_09, + RTW_CHD_5G_10, + RTW_CHD_5G_11, + RTW_CHD_5G_12, + RTW_CHD_5G_13, + RTW_CHD_5G_14, + RTW_CHD_5G_15, + RTW_CHD_5G_16, + RTW_CHD_5G_17, + RTW_CHD_5G_18, + RTW_CHD_5G_19, + RTW_CHD_5G_20, + RTW_CHD_5G_21, + RTW_CHD_5G_22, + RTW_CHD_5G_23, + RTW_CHD_5G_24, + RTW_CHD_5G_25, + RTW_CHD_5G_26, + RTW_CHD_5G_27, + RTW_CHD_5G_28, + RTW_CHD_5G_29, + RTW_CHD_5G_30, + RTW_CHD_5G_31, + RTW_CHD_5G_32, + RTW_CHD_5G_33, + RTW_CHD_5G_34, + RTW_CHD_5G_35, + RTW_CHD_5G_36, + RTW_CHD_5G_37, + RTW_CHD_5G_38, + RTW_CHD_5G_39, + RTW_CHD_5G_40, + RTW_CHD_5G_41, + RTW_CHD_5G_42, + RTW_CHD_5G_43, + RTW_CHD_5G_44, + RTW_CHD_5G_45, + RTW_CHD_5G_46, + RTW_CHD_5G_47, + RTW_CHD_5G_48, + RTW_CHD_5G_49, + RTW_CHD_5G_50, + RTW_CHD_5G_51, + RTW_CHD_5G_52, RTW_CHD_5G_MAX, RTW_CHD_5G_NULL = RTW_CHD_5G_00, }; static const struct ch_list_t rtw_channel_def_2g[] = { - /* 0, RTW_CHD_2G_00 */ CH_LIST_ENT(0, 0), - /* 1, RTW_CHD_2G_01 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, CLA_2G_12_14_PASSIVE), - /* 2, RTW_CHD_2G_02 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0), - /* 3, RTW_CHD_2G_03 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0), - /* 4, RTW_CHD_2G_04 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0), - /* 5, RTW_CHD_2G_05 */ CH_LIST_ENT(4, 10, 11, 12, 13, 0), - /* 6, RTW_CHD_2G_06 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, CLA_2G_12_14_PASSIVE), + /* RTW_CHD_2G_INVALID */ CH_LIST_ENT(0, 0), + /* RTW_CHD_2G_00 */ CH_LIST_ENT(0, 0), + /* RTW_CHD_2G_01 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, CLA_2G_12_14_PASSIVE), + /* RTW_CHD_2G_02 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0), + /* RTW_CHD_2G_03 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0), + /* RTW_CHD_2G_04 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0), + /* RTW_CHD_2G_05 */ CH_LIST_ENT(4, 10, 11, 12, 13, 0), + /* RTW_CHD_2G_06 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, CLA_2G_12_14_PASSIVE), }; #if CONFIG_IEEE80211_BAND_5GHZ static const struct ch_list_t rtw_channel_def_5g[] = { - /* 0, RTW_CHD_5G_00 */ CH_LIST_ENT(0, 0), - /* 1, RTW_CHD_5G_01 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 2, RTW_CHD_5G_02 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 3, RTW_CHD_5G_03 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 4, RTW_CHD_5G_04 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 5, RTW_CHD_5G_05 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 6, RTW_CHD_5G_06 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, 0), - /* 7, RTW_CHD_5G_07 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), - /* 8, RTW_CHD_5G_08 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_DFS), - /* 9, RTW_CHD_5G_09 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0), - /* 10, RTW_CHD_5G_10 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS), - /* 11, RTW_CHD_5G_11 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B3_DFS), - /* 12, RTW_CHD_5G_12 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 13, RTW_CHD_5G_13 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), - /* 14, RTW_CHD_5G_14 */ CH_LIST_ENT(4, 36, 40, 44, 48, 0), - /* 15, RTW_CHD_5G_15 */ CH_LIST_ENT(4, 149, 153, 157, 161, 0), - /* 16, RTW_CHD_5G_16 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0), - /* 17, RTW_CHD_5G_17 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 18, RTW_CHD_5G_18 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 19, RTW_CHD_5G_19 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 20, RTW_CHD_5G_20 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 21, RTW_CHD_5G_21 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 22, RTW_CHD_5G_22 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 23, RTW_CHD_5G_23 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 24, RTW_CHD_5G_24 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), - /* 25, RTW_CHD_5G_25 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), - /* 26, RTW_CHD_5G_26 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), - /* 27, RTW_CHD_5G_27 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), - /* 28, RTW_CHD_5G_28 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE), - /* 29, RTW_CHD_5G_29 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE), - /* 30, RTW_CHD_5G_30 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B4_PASSIVE), - /* 31, RTW_CHD_5G_31 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), - /* 32, RTW_CHD_5G_32 */ CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), - /* 33, RTW_CHD_5G_33 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 34, RTW_CHD_5G_34 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B3_DFS), - /* 35, RTW_CHD_5G_35 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B3_DFS), - /* 36, RTW_CHD_5G_36 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_PASSIVE | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), - /* 37, RTW_CHD_5G_37 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE), - /* 38, RTW_CHD_5G_38 */ CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 39, RTW_CHD_5G_39 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_DFS), - /* 40, RTW_CHD_5G_40 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 41, RTW_CHD_5G_41 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), - /* 42, RTW_CHD_5G_42 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), - /* 43, RTW_CHD_5G_43 */ CH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), - /* 44, RTW_CHD_5G_44 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), - /* 45, RTW_CHD_5G_45 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B4_PASSIVE), - /* 46, RTW_CHD_5G_46 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_PASSIVE), - /* 47, RTW_CHD_5G_47 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), - /* 48, RTW_CHD_5G_48 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 49, RTW_CHD_5G_49 */ CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 50, RTW_CHD_5G_50 */ CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), - /* 51, RTW_CHD_5G_51 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_INVALID */ CH_LIST_ENT(0, 0), + /* RTW_CHD_5G_00 */ CH_LIST_ENT(0, 0), + /* RTW_CHD_5G_01 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_02 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_03 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_04 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_05 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_06 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, 0), + /* RTW_CHD_5G_07 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), + /* RTW_CHD_5G_08 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_DFS), + /* RTW_CHD_5G_09 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0), + /* RTW_CHD_5G_10 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS), + /* RTW_CHD_5G_11 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B3_DFS), + /* RTW_CHD_5G_12 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_13 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), + /* RTW_CHD_5G_14 */ CH_LIST_ENT(4, 36, 40, 44, 48, 0), + /* RTW_CHD_5G_15 */ CH_LIST_ENT(4, 149, 153, 157, 161, 0), + /* RTW_CHD_5G_16 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0), + /* RTW_CHD_5G_17 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_18 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_19 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_20 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_21 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_22 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_23 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_24 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_25 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), + /* RTW_CHD_5G_26 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), + /* RTW_CHD_5G_27 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), + /* RTW_CHD_5G_28 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE), + /* RTW_CHD_5G_29 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE), + /* RTW_CHD_5G_30 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_31 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_32 */ CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS), + /* RTW_CHD_5G_33 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_34 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B3_DFS), + /* RTW_CHD_5G_35 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B3_DFS), + /* RTW_CHD_5G_36 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_PASSIVE | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_37 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE), + /* RTW_CHD_5G_38 */ CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_39 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_DFS), + /* RTW_CHD_5G_40 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_41 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_42 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_43 */ CH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_44 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_45 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B4_PASSIVE), + /* RTW_CHD_5G_46 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_PASSIVE), + /* RTW_CHD_5G_47 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE), + /* RTW_CHD_5G_48 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_49 */ CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_50 */ CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_51 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, CLA_5G_B2_DFS | CLA_5G_B3_DFS), + /* RTW_CHD_5G_52 */ CH_LIST_ENT(28, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, 169, 173, 177, CLA_5G_B2_DFS | CLA_5G_B3_DFS), }; #endif /* CONFIG_IEEE80211_BAND_5GHZ */ struct chplan_ent_t { - u8 regd_2g; /* value of REGULATION_TXPWR_LMT */ + u8 regd_2g; /* value of enum rtw_regd */ u8 chd_2g; #if CONFIG_IEEE80211_BAND_5GHZ - u8 regd_5g; /* value of REGULATION_TXPWR_LMT */ + u8 regd_5g; /* value of enum rtw_regd */ u8 chd_5g; #endif }; #if CONFIG_IEEE80211_BAND_5GHZ -#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = _regd_2g, .chd_2g = _chd_2g, .regd_5g = _regd_5g, .chd_5g = _chd_5g} +#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = RTW_REGD_##_regd_2g, .chd_2g = RTW_CHD_2G_##_chd_2g, .regd_5g = RTW_REGD_##_regd_5g, .chd_5g = RTW_CHD_5G_##_chd_5g} #else -#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = _regd_2g, .chd_2g = _chd_2g} +#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = RTW_REGD_##_regd_2g, .chd_2g = RTW_CHD_2G_##_chd_2g} #endif -#define CHPLAN_ENT_NOT_DEFINED CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_NULL, TXPWR_LMT_NONE, RTW_CHD_5G_NULL) +#define CHPLAN_ENT_NOT_DEFINED CHPLAN_ENT(NA, INVALID, NA, INVALID) static const struct chplan_ent_t RTW_ChannelPlanMap[] = { - /* 0x00 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_49), - /* 0x01 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_50), - /* 0x02 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_03, TXPWR_LMT_ETSI, RTW_CHD_5G_07), - /* 0x03 */ CHPLAN_ENT(TXPWR_LMT_ACMA, RTW_CHD_2G_02, TXPWR_LMT_ACMA, RTW_CHD_5G_33), - /* 0x04 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_51), - /* 0x05 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x06 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x07 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x08 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x09 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0A */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0B */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0C */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0D */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0E */ CHPLAN_ENT_NOT_DEFINED, - /* 0x0F */ CHPLAN_ENT_NOT_DEFINED, - /* 0x10 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x11 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x12 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x13 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x14 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x15 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x16 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x17 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x18 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x19 */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1A */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1B */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1C */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1D */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1E */ CHPLAN_ENT_NOT_DEFINED, - /* 0x1F */ CHPLAN_ENT_NOT_DEFINED, - /* 0x20 */ CHPLAN_ENT(TXPWR_LMT_WW, RTW_CHD_2G_01, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x21 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x22 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x23 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_04, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x24 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_05, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x25 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_03), - /* 0x26 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_02), - /* 0x27 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_04, TXPWR_LMT_MKK, RTW_CHD_5G_02), - /* 0x28 */ CHPLAN_ENT(TXPWR_LMT_KCC, RTW_CHD_2G_01, TXPWR_LMT_KCC, RTW_CHD_5G_05), - /* 0x29 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_06), - /* 0x2A */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x2B */ CHPLAN_ENT(TXPWR_LMT_IC, RTW_CHD_2G_02, TXPWR_LMT_IC, RTW_CHD_5G_33), - /* 0x2C */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x2D */ CHPLAN_ENT(TXPWR_LMT_CHILE, RTW_CHD_2G_01, TXPWR_LMT_CHILE, RTW_CHD_5G_22), - /* 0x2E */ CHPLAN_ENT(TXPWR_LMT_WW, RTW_CHD_2G_03, TXPWR_LMT_WW, RTW_CHD_5G_37), - /* 0x2F */ CHPLAN_ENT(TXPWR_LMT_CHILE, RTW_CHD_2G_01, TXPWR_LMT_CHILE, RTW_CHD_5G_38), - /* 0x30 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_07), - /* 0x31 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_08), - /* 0x32 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_09), - /* 0x33 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_10), - /* 0x34 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_01), - /* 0x35 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_03), - /* 0x36 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_04), - /* 0x37 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_04, TXPWR_LMT_MKK, RTW_CHD_5G_10), - /* 0x38 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_04, TXPWR_LMT_MKK, RTW_CHD_5G_11), - /* 0x39 */ CHPLAN_ENT(TXPWR_LMT_NCC, RTW_CHD_2G_03, TXPWR_LMT_NCC, RTW_CHD_5G_12), - /* 0x3A */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_02), - /* 0x3B */ CHPLAN_ENT(TXPWR_LMT_ACMA, RTW_CHD_2G_02, TXPWR_LMT_ACMA, RTW_CHD_5G_01), - /* 0x3C */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_10), - /* 0x3D */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_15), - /* 0x3E */ CHPLAN_ENT(TXPWR_LMT_KCC, RTW_CHD_2G_02, TXPWR_LMT_KCC, RTW_CHD_5G_03), - /* 0x3F */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_22), - /* 0x40 */ CHPLAN_ENT(TXPWR_LMT_NCC, RTW_CHD_2G_03, TXPWR_LMT_NCC, RTW_CHD_5G_13), - /* 0x41 */ CHPLAN_ENT(TXPWR_LMT_WW, RTW_CHD_2G_06, TXPWR_LMT_NONE, RTW_CHD_5G_00), - /* 0x42 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_14), - /* 0x43 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_06), - /* 0x44 */ CHPLAN_ENT(TXPWR_LMT_NCC, RTW_CHD_2G_03, TXPWR_LMT_NCC, RTW_CHD_5G_09), - /* 0x45 */ CHPLAN_ENT(TXPWR_LMT_ACMA, RTW_CHD_2G_01, TXPWR_LMT_ACMA, RTW_CHD_5G_01), - /* 0x46 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_15), - /* 0x47 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_10), - /* 0x48 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_07), - /* 0x49 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_06), - /* 0x4A */ CHPLAN_ENT(TXPWR_LMT_IC, RTW_CHD_2G_03, TXPWR_LMT_IC, RTW_CHD_5G_33), - /* 0x4B */ CHPLAN_ENT(TXPWR_LMT_KCC, RTW_CHD_2G_02, TXPWR_LMT_KCC, RTW_CHD_5G_22), - /* 0x4C */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_28), - /* 0x4D */ CHPLAN_ENT(TXPWR_LMT_MEXICO, RTW_CHD_2G_02, TXPWR_LMT_MEXICO, RTW_CHD_5G_01), - /* 0x4E */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_42), - /* 0x4F */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_MKK, RTW_CHD_5G_43), - /* 0x50 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_16), - /* 0x51 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_09), - /* 0x52 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_17), - /* 0x53 */ CHPLAN_ENT(TXPWR_LMT_NCC, RTW_CHD_2G_03, TXPWR_LMT_NCC, RTW_CHD_5G_18), - /* 0x54 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_15), - /* 0x55 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_01), - /* 0x56 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_19), - /* 0x57 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_20), - /* 0x58 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_MKK, RTW_CHD_5G_14), - /* 0x59 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_21), - /* 0x5A */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_FCC, RTW_CHD_5G_44), - /* 0x5B */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_FCC, RTW_CHD_5G_45), - /* 0x5C */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_FCC, RTW_CHD_5G_43), - /* 0x5D */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_08), - /* 0x5E */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_03), - /* 0x5F */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_MKK, RTW_CHD_5G_47), - /* 0x60 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_09), - /* 0x61 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_01), - /* 0x62 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_03), - /* 0x63 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_23), - /* 0x64 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_MKK, RTW_CHD_5G_24), - /* 0x65 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_24), - /* 0x66 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_27), - /* 0x67 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_25), - /* 0x68 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_27), - /* 0x69 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_25), - /* 0x6A */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_25), - /* 0x6B */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_29), - /* 0x6C */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_26), - /* 0x6D */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_28), - /* 0x6E */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_25), - /* 0x6F */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_ETSI, RTW_CHD_5G_06), - /* 0x70 */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_ETSI, RTW_CHD_5G_30), - /* 0x71 */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_ETSI, RTW_CHD_5G_25), - /* 0x72 */ CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_00, TXPWR_LMT_ETSI, RTW_CHD_5G_31), - /* 0x73 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_01), - /* 0x74 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_19), - /* 0x75 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_32), - /* 0x76 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_02, TXPWR_LMT_FCC, RTW_CHD_5G_22), - /* 0x77 */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_01, TXPWR_LMT_ETSI, RTW_CHD_5G_34), - /* 0x78 */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_03, TXPWR_LMT_FCC, RTW_CHD_5G_35), - /* 0x79 */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_MKK, RTW_CHD_5G_02), - /* 0x7A */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_28), - /* 0x7B */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_46), - /* 0x7C */ CHPLAN_ENT(TXPWR_LMT_ETSI, RTW_CHD_2G_02, TXPWR_LMT_ETSI, RTW_CHD_5G_47), - /* 0x7D */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_04, TXPWR_LMT_MKK, RTW_CHD_5G_48), - /* 0x7E */ CHPLAN_ENT(TXPWR_LMT_MKK, RTW_CHD_2G_02, TXPWR_LMT_MKK, RTW_CHD_5G_48), - /* 0x7F */ CHPLAN_ENT(TXPWR_LMT_FCC, RTW_CHD_2G_01, TXPWR_LMT_FCC, RTW_CHD_5G_03), + [0x00] = CHPLAN_ENT(ETSI , 02, ETSI , 49), + [0x01] = CHPLAN_ENT(ETSI , 02, ETSI , 50), + [0x02] = CHPLAN_ENT(ETSI , 03, ETSI , 07), + [0x03] = CHPLAN_ENT(ACMA , 02, ACMA , 33), + [0x04] = CHPLAN_ENT(ETSI , 02, ETSI , 51), + [0x05] = CHPLAN_ENT(ETSI , 02, ETSI , 06), + [0x06] = CHPLAN_ENT(ETSI , 02, ETSI , 07), + [0x07] = CHPLAN_ENT(ETSI , 02, ETSI , 23), + [0x08] = CHPLAN_ENT(ETSI , 02, ETSI , 21), + [0x09] = CHPLAN_ENT(ETSI , 02, ETSI , 17), + [0x1A] = CHPLAN_ENT(NA , 00, NA , 00), + [0x1B] = CHPLAN_ENT(FCC , 02, FCC , 52), + [0x20] = CHPLAN_ENT(WW , 01, NA , 00), + [0x21] = CHPLAN_ENT(ETSI , 02, NA , 00), + [0x22] = CHPLAN_ENT(FCC , 03, NA , 00), + [0x23] = CHPLAN_ENT(MKK , 04, NA , 00), + [0x24] = CHPLAN_ENT(ETSI , 05, NA , 00), + [0x25] = CHPLAN_ENT(FCC , 03, FCC , 03), + [0x26] = CHPLAN_ENT(ETSI , 01, ETSI , 02), + [0x27] = CHPLAN_ENT(MKK , 04, MKK , 02), + [0x28] = CHPLAN_ENT(KCC , 01, KCC , 05), + [0x29] = CHPLAN_ENT(FCC , 01, FCC , 06), + [0x2A] = CHPLAN_ENT(FCC , 02, NA , 00), + [0x2B] = CHPLAN_ENT(IC , 02, IC , 33), + [0x2C] = CHPLAN_ENT(MKK , 02, NA , 00), + [0x2D] = CHPLAN_ENT(CHILE, 01, CHILE, 22), + [0x2E] = CHPLAN_ENT(WW , 03, WW , 37), + [0x2F] = CHPLAN_ENT(CHILE, 01, CHILE, 38), + [0x30] = CHPLAN_ENT(FCC , 01, FCC , 07), + [0x31] = CHPLAN_ENT(FCC , 01, FCC , 08), + [0x32] = CHPLAN_ENT(FCC , 01, FCC , 09), + [0x33] = CHPLAN_ENT(FCC , 01, FCC , 10), + [0x34] = CHPLAN_ENT(FCC , 03, FCC , 01), + [0x35] = CHPLAN_ENT(ETSI , 01, ETSI , 03), + [0x36] = CHPLAN_ENT(ETSI , 01, ETSI , 04), + [0x37] = CHPLAN_ENT(MKK , 04, MKK , 10), + [0x38] = CHPLAN_ENT(MKK , 04, MKK , 11), + [0x39] = CHPLAN_ENT(NCC , 03, NCC , 12), + [0x3A] = CHPLAN_ENT(ETSI , 02, ETSI , 02), + [0x3B] = CHPLAN_ENT(ACMA , 02, ACMA , 01), + [0x3C] = CHPLAN_ENT(ETSI , 02, ETSI , 10), + [0x3D] = CHPLAN_ENT(ETSI , 02, ETSI , 15), + [0x3E] = CHPLAN_ENT(KCC , 02, KCC , 03), + [0x3F] = CHPLAN_ENT(FCC , 03, FCC , 22), + [0x40] = CHPLAN_ENT(NCC , 03, NCC , 13), + [0x41] = CHPLAN_ENT(WW , 06, NA , 00), + [0x42] = CHPLAN_ENT(ETSI , 02, ETSI , 14), + [0x43] = CHPLAN_ENT(FCC , 03, FCC , 06), + [0x44] = CHPLAN_ENT(NCC , 03, NCC , 09), + [0x45] = CHPLAN_ENT(ACMA , 01, ACMA , 01), + [0x46] = CHPLAN_ENT(FCC , 03, FCC , 15), + [0x47] = CHPLAN_ENT(ETSI , 01, ETSI , 10), + [0x48] = CHPLAN_ENT(ETSI , 01, ETSI , 07), + [0x49] = CHPLAN_ENT(ETSI , 01, ETSI , 06), + [0x4A] = CHPLAN_ENT(IC , 03, IC , 33), + [0x4B] = CHPLAN_ENT(KCC , 02, KCC , 22), + [0x4C] = CHPLAN_ENT(FCC , 03, FCC , 28), + [0x4D] = CHPLAN_ENT(MEX , 02, MEX , 01), + [0x4E] = CHPLAN_ENT(ETSI , 02, ETSI , 42), + [0x4F] = CHPLAN_ENT(NA , 00, MKK , 43), + [0x50] = CHPLAN_ENT(ETSI , 01, ETSI , 16), + [0x51] = CHPLAN_ENT(ETSI , 01, ETSI , 09), + [0x52] = CHPLAN_ENT(ETSI , 01, ETSI , 17), + [0x53] = CHPLAN_ENT(NCC , 03, NCC , 18), + [0x54] = CHPLAN_ENT(ETSI , 01, ETSI , 15), + [0x55] = CHPLAN_ENT(FCC , 03, FCC , 01), + [0x56] = CHPLAN_ENT(ETSI , 01, ETSI , 19), + [0x57] = CHPLAN_ENT(FCC , 03, FCC , 20), + [0x58] = CHPLAN_ENT(MKK , 02, MKK , 14), + [0x59] = CHPLAN_ENT(ETSI , 01, ETSI , 21), + [0x5A] = CHPLAN_ENT(NA , 00, FCC , 44), + [0x5B] = CHPLAN_ENT(NA , 00, FCC , 45), + [0x5C] = CHPLAN_ENT(NA , 00, FCC , 43), + [0x5D] = CHPLAN_ENT(ETSI , 02, ETSI , 08), + [0x5E] = CHPLAN_ENT(ETSI , 02, ETSI , 03), + [0x5F] = CHPLAN_ENT(MKK , 02, MKK , 47), + [0x60] = CHPLAN_ENT(FCC , 03, FCC , 09), + [0x61] = CHPLAN_ENT(FCC , 02, FCC , 01), + [0x62] = CHPLAN_ENT(FCC , 02, FCC , 03), + [0x63] = CHPLAN_ENT(ETSI , 01, ETSI , 23), + [0x64] = CHPLAN_ENT(MKK , 02, MKK , 24), + [0x65] = CHPLAN_ENT(ETSI , 02, ETSI , 24), + [0x66] = CHPLAN_ENT(FCC , 03, FCC , 27), + [0x67] = CHPLAN_ENT(FCC , 03, FCC , 25), + [0x68] = CHPLAN_ENT(FCC , 02, FCC , 27), + [0x69] = CHPLAN_ENT(FCC , 02, FCC , 25), + [0x6A] = CHPLAN_ENT(ETSI , 02, ETSI , 25), + [0x6B] = CHPLAN_ENT(FCC , 01, FCC , 29), + [0x6C] = CHPLAN_ENT(FCC , 01, FCC , 26), + [0x6D] = CHPLAN_ENT(FCC , 02, FCC , 28), + [0x6E] = CHPLAN_ENT(FCC , 01, FCC , 25), + [0x6F] = CHPLAN_ENT(NA , 00, ETSI , 06), + [0x70] = CHPLAN_ENT(NA , 00, ETSI , 30), + [0x71] = CHPLAN_ENT(NA , 00, ETSI , 25), + [0x72] = CHPLAN_ENT(NA , 00, ETSI , 31), + [0x73] = CHPLAN_ENT(FCC , 01, FCC , 01), + [0x74] = CHPLAN_ENT(FCC , 02, FCC , 19), + [0x75] = CHPLAN_ENT(ETSI , 01, ETSI , 32), + [0x76] = CHPLAN_ENT(FCC , 02, FCC , 22), + [0x77] = CHPLAN_ENT(ETSI , 01, ETSI , 34), + [0x78] = CHPLAN_ENT(FCC , 03, FCC , 35), + [0x79] = CHPLAN_ENT(MKK , 02, MKK , 02), + [0x7A] = CHPLAN_ENT(ETSI , 02, ETSI , 28), + [0x7B] = CHPLAN_ENT(ETSI , 02, ETSI , 46), + [0x7C] = CHPLAN_ENT(ETSI , 02, ETSI , 47), + [0x7D] = CHPLAN_ENT(MKK , 04, MKK , 48), + [0x7E] = CHPLAN_ENT(MKK , 02, MKK , 48), + [0x7F] = CHPLAN_ENT(WW , 01, WW , 36), }; const int RTW_ChannelPlanMap_size = sizeof(RTW_ChannelPlanMap) / sizeof(RTW_ChannelPlanMap[0]); +#endif /* USE_RTW_REGD */ u8 rtw_chplan_get_default_regd_2g(u8 id) { - return RTW_ChannelPlanMap[id].regd_2g; +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + return phl_regulation_to_regd(rtw_phl_get_domain_regulation_2g(id)); +#else + if (id < RTW_ChannelPlanMap_size) + return RTW_ChannelPlanMap[id].regd_2g; + return RTW_REGD_NA; +#endif } u8 rtw_chplan_get_default_regd_5g(u8 id) { #if CONFIG_IEEE80211_BAND_5GHZ - return RTW_ChannelPlanMap[id].regd_5g; +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + return phl_regulation_to_regd(rtw_phl_get_domain_regulation_5g(id)); #else - return TXPWR_LMT_NONE; + if (id < RTW_ChannelPlanMap_size) + return RTW_ChannelPlanMap[id].regd_5g; +#endif #endif + return RTW_REGD_NA; } -u8 rtw_chplan_get_default_regd(u8 id) +bool rtw_is_channel_plan_valid(u8 id) { - u8 regd_2g = rtw_chplan_get_default_regd_2g(id); - u8 regd_5g = rtw_chplan_get_default_regd_5g(id); +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + if (rtw_phl_valid_regulation_domain(id)) + return _TRUE; + else + return _FALSE; +#else + if (id < RTW_ChannelPlanMap_size) { + const struct chplan_ent_t *chplan_map = &RTW_ChannelPlanMap[id]; - if (regd_2g != TXPWR_LMT_NONE && regd_5g != TXPWR_LMT_NONE) { - if (regd_2g != regd_5g) - RTW_WARN("channel_plan:0x%02x, regd_2g:%u, regd_5g:%u not the same\n", id, regd_2g, regd_5g); - return regd_5g; + if (chplan_map->chd_2g != RTW_CHD_2G_INVALID + #if CONFIG_IEEE80211_BAND_5GHZ + && chplan_map->chd_5g != RTW_CHD_5G_INVALID + #endif + ) + return _TRUE; } - return regd_2g != TXPWR_LMT_NONE ? regd_2g : regd_5g; + + return _FALSE; +#endif } -bool rtw_chplan_is_empty(u8 id) +bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) { - const struct chplan_ent_t *chplan_map = &RTW_ChannelPlanMap[id]; - - if (chplan_map->chd_2g == RTW_CHD_2G_NULL - #if CONFIG_IEEE80211_BAND_5GHZ - && chplan_map->chd_5g == RTW_CHD_5G_NULL - #endif - ) - return _TRUE; + int i; + for (i = 0; i < MAX_CHANNEL_NUM_2G_5G; i++) { + if (regsty->excl_chs[i] == 0) + break; + if (regsty->excl_chs[i] == ch) + return _TRUE; + } return _FALSE; } -bool rtw_is_channel_plan_valid(u8 id) +/* + * Search the @param ch in chplan by given @param id + * @id: the given channel plan id + * @ch: the given channel number + * + * return the index of channel_num in channel_set, -1 if not found + */ +static bool rtw_chplan_get_ch(u8 id, const u32 ch, u8 *flags) +{ + u8 index, chan, attrib; + + if (flags) + *flags = 0; + +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + if (phl_info) { + struct rtw_regulation_chplan plan; + + /* this function check for capability inside */ + if (rtw_phl_query_specific_chplan(phl_info, id, &plan)) { + for (index = 0; index < plan.cnt; index++) { + if (plan.ch[index].band != BAND_ON_24G && plan.ch[index].band != BAND_ON_5G) + continue; + if (plan.ch[index].channel != ch) + continue; + if (flags) { + if (plan.ch[index].property & CH_PASSIVE) + *flags |= RTW_CHF_NO_IR; + if (plan.ch[index].property & CH_DFS) + *flags |= RTW_CHF_DFS; + } + return 1; + } + } + } +#else +#if CONFIG_IEEE80211_BAND_5GHZ + if (ch > 14) { + u8 chd_5g = RTW_ChannelPlanMap[id].chd_5g; + + attrib = CH_LIST_ATTRIB(rtw_channel_def_5g[chd_5g]); + + for (index = 0; index < CH_LIST_LEN(rtw_channel_def_5g[chd_5g]); index++) { + if (CH_LIST_CH(rtw_channel_def_5g[chd_5g], index) == ch) { + if (flags) { + if ((rtw_is_5g_band1(ch) && (attrib & CLA_5G_B1_PASSIVE)) /* band1 passive */ + || (rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_PASSIVE)) /* band2 passive */ + || (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_PASSIVE)) /* band3 passive */ + || (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_PASSIVE)) /* band4 passive */ + ) + *flags |= RTW_CHF_NO_IR; + + if ((rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_DFS)) + || (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_DFS)) + || (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_DFS))) + *flags |= RTW_CHF_DFS; + } + return 1; + } + } + } else +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + { + u8 chd_2g = RTW_ChannelPlanMap[id].chd_2g; + + attrib = CH_LIST_ATTRIB(rtw_channel_def_2g[chd_2g]); + + for (index = 0; index < CH_LIST_LEN(rtw_channel_def_2g[chd_2g]); index++) { + if (CH_LIST_CH(rtw_channel_def_2g[chd_2g], index) == ch) { + if (flags) { + if (ch >= 12 && ch <= 14 && (attrib & CLA_2G_12_14_PASSIVE)) + *flags |= RTW_CHF_NO_IR; + } + return 1; + } + } + } +#endif /* defined(PHL_FEATURE_NIC) && !USE_RTW_REGD */ + + return 0; +} + +#if CONFIG_IEEE80211_BAND_6GHZ +#if USE_RTW_REGD +enum rtw_chd_6g { + RTW_CHD_6G_INVALID = 0, + + RTW_CHD_6G_00, + RTW_CHD_6G_01, + RTW_CHD_6G_02, + RTW_CHD_6G_03, + RTW_CHD_6G_04, + RTW_CHD_6G_05, /* 6G Worldwide */ + + RTW_CHD_6G_MAX, + RTW_CHD_6G_NULL = RTW_CHD_6G_00, +}; + +static const struct ch_list_t rtw_channel_def_6g[] = { + /* RTW_CHD_6G_INVALID */ CH_LIST_ENT(0, 0), + /* RTW_CHD_6G_00 */ CH_LIST_ENT(0, 0), + /* RTW_CHD_6G_01 */ CH_LIST_ENT(24, 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89, 93, 0), + /* RTW_CHD_6G_02 */ CH_LIST_ENT(6, 97, 101, 105, 109, 113, 117, 0), + /* RTW_CHD_6G_03 */ CH_LIST_ENT(18, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189, 0), + /* RTW_CHD_6G_04 */ CH_LIST_ENT(11, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 0), + /* RTW_CHD_6G_05 */ CH_LIST_ENT(59, 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, CLA_6G_B1_PASSIVE | CLA_6G_B2_PASSIVE | CLA_6G_B3_PASSIVE | CLA_6G_B4_PASSIVE), +}; + +struct chplan_6g_ent_t { + u8 regd; /* value of enum rtw_regd */ + u8 chd; +}; + +#define CHPLAN_6G_ENT(_regd, _chd) {.regd = RTW_REGD_##_regd, .chd = RTW_CHD_6G_##_chd} + +#define CHPLAN_6G_ENT_NOT_DEFINED CHPLAN_6G_ENT(NA, INVALID) + +static const struct chplan_6g_ent_t rtw_chplan_6g_map[] = { + [0x00] = CHPLAN_6G_ENT(NA , 00), + [0x01] = CHPLAN_6G_ENT(FCC , 01), + [0x02] = CHPLAN_6G_ENT(FCC , 02), + [0x03] = CHPLAN_6G_ENT(FCC , 03), + [0x04] = CHPLAN_6G_ENT(FCC , 04), + [0x7F] = CHPLAN_6G_ENT(WW , 05), +}; + +const int rtw_chplan_6g_map_size = sizeof(rtw_chplan_6g_map) / sizeof(rtw_chplan_6g_map[0]); +#endif /* USE_RTW_REGD */ + +u8 rtw_chplan_get_default_regd_6g(u8 id) { - return id < RTW_ChannelPlanMap_size && !rtw_chplan_is_empty(id); +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + /* wait PHL ready */ + return RTW_REGD_NA; +#else + if (id < rtw_chplan_6g_map_size) + return rtw_chplan_6g_map[id].regd; + return RTW_REGD_NA; +#endif } -bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) +bool rtw_is_channel_plan_6g_valid(u8 id) +{ +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + /* TODO: wait PHL ready */ + return _FALSE; +#else + if (id < rtw_chplan_6g_map_size) { + const struct chplan_6g_ent_t *chplan_map = &rtw_chplan_6g_map[id]; + + if (chplan_map->chd != RTW_CHD_6G_INVALID) + return _TRUE; + } + + return _FALSE; +#endif +} + +bool rtw_regsty_is_excl_chs_6g(struct registry_priv *regsty, u8 ch) { int i; - for (i = 0; i < MAX_CHANNEL_NUM; i++) { - if (regsty->excl_chs[i] == 0) + for (i = 0; i < MAX_CHANNEL_NUM_6G; i++) { + if (regsty->excl_chs_6g[i] == 0) break; - if (regsty->excl_chs[i] == ch) + if (regsty->excl_chs_6g[i] == ch) return _TRUE; } return _FALSE; } +/* + * Search the @param ch in chplan by given @param id + * @id: the given channel plan id + * @ch: the given channel number + * + * return the index of channel_num in channel_set, -1 if not found + */ +static bool rtw_chplan_6g_get_ch(u8 id, const u32 ch, u8 *flags) +{ + u8 index, chan, attrib; + u8 chd_6g; + + if (flags) + *flags = 0; + +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + if (phl_info) { + /* Wait PHL ready */ + } +#else + chd_6g = rtw_chplan_6g_map[id].chd; + + attrib = CH_LIST_ATTRIB(rtw_channel_def_6g[chd_6g]); + + for (index = 0; index < CH_LIST_LEN(rtw_channel_def_6g[chd_6g]); index++) { + if (CH_LIST_CH(rtw_channel_def_6g[chd_6g], index) == ch) { + if (flags) { + if ((rtw_is_6g_band1(ch) && (attrib & CLA_6G_B1_PASSIVE)) /* band1 passive */ + || (rtw_is_6g_band2(ch) && (attrib & CLA_6G_B2_PASSIVE)) /* band2 passive */ + || (rtw_is_6g_band3(ch) && (attrib & CLA_6G_B3_PASSIVE)) /* band3 passive */ + || (rtw_is_6g_band4(ch) && (attrib & CLA_6G_B4_PASSIVE)) /* band4 passive */ + ) + *flags |= RTW_CHF_NO_IR; + } + return 1; + } + } +#endif + + return 0; +} +#endif /* CONFIG_IEEE80211_BAND_6GHZ */ + +/* + * Check if the @param ch, bw, offset is valid for the given @param id, id_6g + * @ch_set: the given channel set + * @ch: the given channel number + * @bw: the given bandwidth + * @offset: the given channel offset + * + * return valid (1) or not (0) + */ +u8 rtw_chplan_is_chbw_valid(u8 id, u8 id_6g, enum band_type band, u8 ch, u8 bw, u8 offset + , bool allow_primary_passive, bool allow_passive, struct registry_priv *regsty) +{ + u8 cch; + u8 *op_chs; + u8 op_ch_num; + u8 op_ch; + u8 valid = 0; + int i; + int ch_idx; + u8 flags; + +#if CONFIG_IEEE80211_BAND_6GHZ + if (band == BAND_ON_6G) + goto exit; +#endif + + cch = rtw_get_center_ch(ch, bw, offset); /* TODO: 6G */ + + if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num)) /* TODO: 6G */ + goto exit; + + for (i = 0; i < op_ch_num; i++) { + op_ch = *(op_chs + i); + if (0) + RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, op_ch); + #if CONFIG_IEEE80211_BAND_6GHZ + if (band == BAND_ON_6G) { + if (!rtw_chplan_6g_get_ch(id_6g, op_ch, &flags) + || (regsty && rtw_regsty_is_excl_chs_6g(regsty, op_ch) == _TRUE)) + break; + } else + #endif + { + if (!rtw_chplan_get_ch(id, op_ch, &flags) + || (regsty && rtw_regsty_is_excl_chs(regsty, op_ch) == _TRUE)) + break; + } + if (flags & RTW_CHF_NO_IR) { + if (!allow_passive + || (!allow_primary_passive && op_ch == ch)) + break; + } + } + + if (op_ch_num != 0 && i == op_ch_num) + valid = 1; + +exit: + return valid; +} + const char *_regd_src_str[] = { [REGD_SRC_RTK_PRIV] = "RTK_PRIV", [REGD_SRC_OS] = "OS", [REGD_SRC_NUM] = "UNKNOWN", }; -static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *channel_set) +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD +static u8 init_channel_set_from_rtk_priv(_adapter *adapter, RT_CHANNEL_INFO *channel_set) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - struct registry_priv *regsty = adapter_to_regsty(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct registry_priv *regsty = adapter_to_regsty(adapter); u8 ChannelPlan = rfctl->ChannelPlan; - u8 index, chanset_size = 0; + struct rtw_regulation_chplan plan = {0}; + u8 index, chanset_size = 0; + int i = 0; + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + + /* Set and query channel plan from PHL*/ + if (IS_ALPHA2_WORLDWIDE(rfctl->alpha2) || IS_ALPHA2_UNSPEC(rfctl->alpha2)) { + if (rtw_phl_regulation_set_domain(GET_PHL_INFO(dvobj), rfctl->ChannelPlan, REGU_RSN_DEFAULT) != true) { + RTW_WARN("rtw_phl_regulation_set_domain() != true\n"); + goto exit; + } + #if CONFIG_IEEE80211_BAND_6GHZ && 0 /* Wait PHL ready */ + /* set 6g domain code */ + #endif + } else { + if (rtw_phl_regulation_set_country(GET_PHL_INFO(dvobj), rfctl->alpha2, REGU_RSN_DEFAULT) != true) { + RTW_WARN("rtw_phl_regulation_set_country() != true\n"); + goto exit; + } + } + + if (rtw_phl_regulation_query_chplan(GET_PHL_INFO(dvobj), REGULQ_CHPLAN_FULL, NULL, &plan) != true) { + RTW_WARN("rtw_phl_regulation_query_chplan() return false\n"); + goto exit; + } + + for (i = 0; i < plan.cnt; i++) { + if (rtw_regsty_is_excl_chs(regsty, plan.ch[i].channel) == _TRUE) + continue; + + if (plan.ch[i].property & CH_DFS) { + #if CONFIG_DFS + channel_set[chanset_size].flags |= RTW_CHF_DFS; + #else + continue; + #endif + } + + channel_set[chanset_size].band = plan.ch[i].band; + channel_set[chanset_size].ChannelNum = plan.ch[i].channel; + if (plan.ch[i].property & CH_PASSIVE) + channel_set[chanset_size].flags |= RTW_CHF_NO_IR; + + if (channel_set[chanset_size].flags & RTW_CHF_NO_IR) { + if (!rtw_rfctl_reg_allow_beacon_hint(rfctl) || !rtw_chinfo_allow_beacon_hint(&channel_set[chanset_size])) + RTW_INFO("band:%s ch%u is NO_IR%s while beacon hint not allowed\n" + , band_str(plan.ch[i].band), plan.ch[i].channel, plan.ch[i].property & CH_DFS ? " DFS" : ""); + } + + chanset_size++; + } + + #ifdef CONFIG_DFS_MASTER + for (i = 0; i < chanset_size; i++) + channel_set[i].non_ocp_end_time = rtw_get_current_time(); + #endif + +exit: + if (chanset_size) + RTW_INFO(FUNC_ADPT_FMT" ch num:%d\n", FUNC_ADPT_ARG(adapter), chanset_size); + else + RTW_WARN(FUNC_ADPT_FMT" final chset has no channel\n", FUNC_ADPT_ARG(adapter)); + + return chanset_size; +} +#else +static u8 init_channel_set_from_rtk_priv_2g_5g(_adapter *adapter, RT_CHANNEL_INFO *channel_set, u8 *ch_num) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct registry_priv *regsty = adapter_to_regsty(adapter); + u8 chplan = rfctl->ChannelPlan; + u8 index, chanset_size = *ch_num; u8 b5GBand = _FALSE, b2_4GBand = _FALSE; u8 ch, attrib; -#ifdef CONFIG_DFS_MASTER - int i; -#endif - if (!rtw_is_channel_plan_valid(ChannelPlan)) { - RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); - return chanset_size; + if (!rtw_is_channel_plan_valid(chplan)) { + RTW_ERR(FUNC_ADPT_FMT" invalid chplan:0x%02X\n", FUNC_ADPT_ARG(adapter), chplan); + goto exit; } + RTW_INFO(FUNC_ADPT_FMT" chplan:0x%02X\n", FUNC_ADPT_ARG(adapter), chplan); - _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); - - if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G)) + if (is_supported_24g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_2G)) b2_4GBand = _TRUE; - if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G)) + if (is_supported_5g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_5G)) b5GBand = _TRUE; - if (b2_4GBand == _FALSE && b5GBand == _FALSE) { - RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); - return chanset_size; - } - if (b2_4GBand) { - u8 chd_2g = RTW_ChannelPlanMap[ChannelPlan].chd_2g; + u8 chd_2g = RTW_ChannelPlanMap[chplan].chd_2g; attrib = CH_LIST_ATTRIB(rtw_channel_def_2g[chd_2g]); @@ -439,14 +841,15 @@ static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *ch break; } + channel_set[chanset_size].band = BAND_ON_24G; channel_set[chanset_size].ChannelNum = ch; if (ch >= 12 && ch <= 14 && (attrib & CLA_2G_12_14_PASSIVE)) channel_set[chanset_size].flags |= RTW_CHF_NO_IR; if (channel_set[chanset_size].flags & RTW_CHF_NO_IR) { - if (rfctl->country_ent || ch <= 11) - RTW_INFO("ch%u is PASSIVE\n", ch); + if (!rtw_rfctl_reg_allow_beacon_hint(rfctl) || !rtw_chinfo_allow_beacon_hint(&channel_set[chanset_size])) + RTW_INFO("band:%s ch%u is NO_IR while beacon hint not allowed\n", band_str(BAND_ON_24G), ch); } chanset_size++; @@ -456,7 +859,7 @@ static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *ch #if CONFIG_IEEE80211_BAND_5GHZ if (b5GBand) { bool dfs; - u8 chd_5g = RTW_ChannelPlanMap[ChannelPlan].chd_5g; + u8 chd_5g = RTW_ChannelPlanMap[chplan].chd_5g; attrib = CH_LIST_ATTRIB(rtw_channel_def_5g[chd_5g]); @@ -477,6 +880,7 @@ static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *ch break; } + channel_set[chanset_size].band = BAND_ON_5G; channel_set[chanset_size].ChannelNum = ch; if ((rtw_is_5g_band1(ch) && (attrib & CLA_5G_B1_PASSIVE)) /* band1 passive */ @@ -490,44 +894,122 @@ static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *ch channel_set[chanset_size].flags |= RTW_CHF_DFS; if (channel_set[chanset_size].flags & RTW_CHF_NO_IR) { - if (rfctl->country_ent || (channel_set[chanset_size].flags & RTW_CHF_DFS)) - RTW_INFO("ch%u is PASSIVE%s\n", ch, dfs ? " DFS" : ""); + if (!rtw_rfctl_reg_allow_beacon_hint(rfctl) || !rtw_chinfo_allow_beacon_hint(&channel_set[chanset_size])) + RTW_INFO("band:%s ch%u is NO_IR%s while beacon hint not allowed\n", band_str(BAND_ON_5G), ch, dfs ? " DFS" : ""); } chanset_size++; } } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ - #ifdef CONFIG_DFS_MASTER +exit: + *ch_num = chanset_size; + + return chanset_size; +} + +#if CONFIG_IEEE80211_BAND_6GHZ +static u8 init_channel_set_from_rtk_priv_6g(_adapter *adapter, RT_CHANNEL_INFO *channel_set, u8 *ch_num) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct registry_priv *regsty = adapter_to_regsty(adapter); + u8 chplan_6g = rfctl->chplan_6g; + u8 index, chanset_size = *ch_num; + bool band_6g = _FALSE; + u8 chd_6g; + u8 ch, attrib; + + if (!rtw_is_channel_plan_6g_valid(chplan_6g)) { + RTW_ERR(FUNC_ADPT_FMT" invalid chplan_6g:0x%02X\n", FUNC_ADPT_ARG(adapter), chplan_6g); + goto exit; + } + RTW_INFO(FUNC_ADPT_FMT" chplan_6g:0x%02X\n", FUNC_ADPT_ARG(adapter), chplan_6g); + + if (is_supported_6g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_6G)) + band_6g = _TRUE; + if (!band_6g) + goto exit; + + chd_6g = rtw_chplan_6g_map[chplan_6g].chd; + + attrib = CH_LIST_ATTRIB(rtw_channel_def_6g[chd_6g]); + + for (index = 0; index < CH_LIST_LEN(rtw_channel_def_6g[chd_6g]); index++) { + ch = CH_LIST_CH(rtw_channel_def_6g[chd_6g], index); + if (rtw_regsty_is_excl_chs_6g(regsty, ch) == _TRUE) + continue; + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].band = BAND_ON_6G; + channel_set[chanset_size].ChannelNum = ch; + + if ((rtw_is_6g_band1(ch) && (attrib & CLA_6G_B1_PASSIVE)) /* band1 passive */ + || (rtw_is_6g_band2(ch) && (attrib & CLA_6G_B2_PASSIVE)) /* band2 passive */ + || (rtw_is_6g_band3(ch) && (attrib & CLA_6G_B3_PASSIVE)) /* band3 passive */ + || (rtw_is_6g_band4(ch) && (attrib & CLA_6G_B4_PASSIVE)) /* band4 passive */ + ) + channel_set[chanset_size].flags |= RTW_CHF_NO_IR; + + chanset_size++; + } + +exit: + *ch_num = chanset_size; + + return chanset_size; +} +#endif /* CONFIG_IEEE80211_BAND_6GHZ */ + +static u8 init_channel_set_from_rtk_priv(_adapter *adapter, RT_CHANNEL_INFO *channel_set) +{ + u8 chanset_size = 0; +#ifdef CONFIG_DFS_MASTER + int i; +#endif + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + + init_channel_set_from_rtk_priv_2g_5g(adapter, channel_set, &chanset_size); + +#if CONFIG_IEEE80211_BAND_6GHZ + init_channel_set_from_rtk_priv_6g(adapter, channel_set, &chanset_size); +#endif + +#ifdef CONFIG_DFS_MASTER for (i = 0; i < chanset_size; i++) channel_set[i].non_ocp_end_time = rtw_get_current_time(); - #endif -#endif /* CONFIG_IEEE80211_BAND_5GHZ */ +#endif if (chanset_size) - RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" - , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); + RTW_INFO(FUNC_ADPT_FMT" ch num:%d\n", FUNC_ADPT_ARG(adapter), chanset_size); else - RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n" - , FUNC_ADPT_ARG(padapter), ChannelPlan); + RTW_WARN(FUNC_ADPT_FMT" final chset has no channel\n", FUNC_ADPT_ARG(adapter)); return chanset_size; } +#endif /* defined(PHL_FEATURE_NIC) && !USE_RTW_REGD */ u8 init_channel_set(_adapter *adapter) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); if (rfctl->regd_src == REGD_SRC_RTK_PRIV) - return init_channel_set_from_rtk_priv(adapter, rfctl->channel_set); + rfctl->max_chan_nums = init_channel_set_from_rtk_priv(adapter, rfctl->channel_set); #ifdef CONFIG_REGD_SRC_FROM_OS else if (rfctl->regd_src == REGD_SRC_OS) - return rtw_os_init_channel_set(adapter, rfctl->channel_set); + rfctl->max_chan_nums = rtw_os_init_channel_set(adapter, rfctl->channel_set); #endif - else + else { + rfctl->max_chan_nums = 0; rtw_warn_on(1); + } - return 0; + return rfctl->max_chan_nums; } bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo) @@ -568,36 +1050,40 @@ bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offs return rtw_chset_is_dfs_range(chset, hi, lo); } -u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss) -{ -#ifndef RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE -#define RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE 0 -#endif - +/* channel specific beacon hint rules */ #ifndef RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 #define RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 0 #endif - #ifndef RTW_CHPLAN_BEACON_HINT_ON_DFS_CH #define RTW_CHPLAN_BEACON_HINT_ON_DFS_CH 0 #endif +bool rtw_chinfo_allow_beacon_hint(struct _RT_CHANNEL_INFO *chinfo) +{ + return (RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 || !(chinfo->band == BAND_ON_24G && chinfo->ChannelNum <= 11)) + && (RTW_CHPLAN_BEACON_HINT_ON_DFS_CH || !(chinfo->flags & RTW_CHF_DFS)); +} + +u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss) +{ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); RT_CHANNEL_INFO *chset = rfctl->channel_set; u8 ch = bss->Configuration.DSConfig; int chset_idx = rtw_chset_search_ch(chset, ch); + RT_CHANNEL_INFO *chinfo; u8 act_cnt = 0; if (chset_idx < 0) goto exit; - if ((chset[chset_idx].flags & RTW_CHF_NO_IR) - && (RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE || !rfctl->country_ent || IS_ALPHA2_WORLDWIDE(rfctl->country_ent->alpha2)) - && (RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 || !(ch <= 11)) - && (RTW_CHPLAN_BEACON_HINT_ON_DFS_CH || !(chset[chset_idx].flags & RTW_CHF_DFS)) + chinfo = &chset[chset_idx]; + + if ((chinfo->flags & RTW_CHF_NO_IR) + && rtw_rfctl_reg_allow_beacon_hint(rfctl) + && rtw_chinfo_allow_beacon_hint(chinfo) ) { - RTW_INFO("%s: change ch:%d to active\n", __func__, ch); - chset[chset_idx].flags &= ~RTW_CHF_NO_IR; + RTW_INFO("%s: change band:%s ch:%d to active\n", __func__, band_str(chinfo->band), ch); + chinfo->flags &= ~RTW_CHF_NO_IR; act_cnt++; } @@ -605,25 +1091,317 @@ u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss) return act_cnt; } -const char *_rtw_dfs_regd_str[] = { +const char *const _regd_inr_str[] = { + [RTW_REGD_SET_BY_INIT] = "INIT", + [RTW_REGD_SET_BY_USER] = "USER", + [RTW_REGD_SET_BY_COUNTRY_IE] = "COUNTRY_IE", + [RTW_REGD_SET_BY_DRIVER] = "DRIVER", + [RTW_REGD_SET_BY_CORE] = "CORE", + [RTW_REGD_SET_BY_NUM] = "UNKNOWN", +}; + +const char *const _regd_str[] = { + [RTW_REGD_NA] = "NA", + [RTW_REGD_FCC] = "FCC", + [RTW_REGD_MKK] = "MKK", + [RTW_REGD_ETSI] = "ETSI", + [RTW_REGD_IC] = "IC", + [RTW_REGD_KCC] = "KCC", + [RTW_REGD_NCC] = "NCC", + [RTW_REGD_ACMA] = "ACMA", + [RTW_REGD_CHILE] = "CHILE", + [RTW_REGD_MEX] = "MEX", + [RTW_REGD_WW] = "WW", +}; + +const char *const _rtw_edcca_mode_str[] = { + [RTW_EDCCA_NORM] = "NORMAL", + [RTW_EDCCA_ADAPT] = "ADAPT", + [RTW_EDCCA_CS] = "CS", +}; + +const char *const _rtw_dfs_regd_str[] = { [RTW_DFS_REGD_NONE] = "NONE", [RTW_DFS_REGD_FCC] = "FCC", [RTW_DFS_REGD_MKK] = "MKK", [RTW_DFS_REGD_ETSI] = "ETSI", }; -#ifdef CONFIG_80211AC_VHT -#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) -#else -#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) -#endif +const char *const _txpwr_lmt_str[] = { + [TXPWR_LMT_NONE] = "NONE", + [TXPWR_LMT_FCC] = "FCC", + [TXPWR_LMT_MKK] = "MKK", + [TXPWR_LMT_ETSI] = "ETSI", + [TXPWR_LMT_IC] = "IC", + [TXPWR_LMT_KCC] = "KCC", + [TXPWR_LMT_NCC] = "NCC", + [TXPWR_LMT_ACMA] = "ACMA", + [TXPWR_LMT_CHILE] = "CHILE", + [TXPWR_LMT_UKRAINE] = "UKRAINE", + [TXPWR_LMT_MEXICO] = "MEXICO", + [TXPWR_LMT_CN] = "CN", + [TXPWR_LMT_QATAR] = "QATAR", + [TXPWR_LMT_WW] = "WW", + [TXPWR_LMT_NUM] = NULL, +}; -#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac) \ - {.alpha2 = (_alpha2), .chplan = (_chplan) \ - COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ - } +const REGULATION_TXPWR_LMT _txpwr_lmt_alternate[] = { + [TXPWR_LMT_NONE] = TXPWR_LMT_NONE, + [TXPWR_LMT_FCC] = TXPWR_LMT_FCC, + [TXPWR_LMT_MKK] = TXPWR_LMT_MKK, + [TXPWR_LMT_ETSI] = TXPWR_LMT_ETSI, + [TXPWR_LMT_WW] = TXPWR_LMT_WW, + [TXPWR_LMT_NUM] = TXPWR_LMT_NUM, + + [TXPWR_LMT_IC] = TXPWR_LMT_FCC, + [TXPWR_LMT_KCC] = TXPWR_LMT_ETSI, + [TXPWR_LMT_NCC] = TXPWR_LMT_FCC, + [TXPWR_LMT_ACMA] = TXPWR_LMT_ETSI, + [TXPWR_LMT_CHILE] = TXPWR_LMT_FCC, + [TXPWR_LMT_UKRAINE] = TXPWR_LMT_ETSI, + [TXPWR_LMT_MEXICO] = TXPWR_LMT_FCC, + [TXPWR_LMT_CN] = TXPWR_LMT_ETSI, + [TXPWR_LMT_QATAR] = TXPWR_LMT_ETSI, +}; -#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP +const enum rtw_edcca_mode_t _rtw_regd_to_edcca_mode[RTW_REGD_NUM] = { + [RTW_REGD_NA] = RTW_EDCCA_MODE_NUM, + [RTW_REGD_MKK] = RTW_EDCCA_CS, + [RTW_REGD_ETSI] = RTW_EDCCA_ADAPT, + [RTW_REGD_WW] = RTW_EDCCA_ADAPT, +}; + +const REGULATION_TXPWR_LMT _rtw_regd_to_txpwr_lmt[] = { + [RTW_REGD_NA] = TXPWR_LMT_NUM, + [RTW_REGD_FCC] = TXPWR_LMT_FCC, + [RTW_REGD_MKK] = TXPWR_LMT_MKK, + [RTW_REGD_ETSI] = TXPWR_LMT_ETSI, + [RTW_REGD_IC] = TXPWR_LMT_IC, + [RTW_REGD_KCC] = TXPWR_LMT_KCC, + [RTW_REGD_NCC] = TXPWR_LMT_NCC, + [RTW_REGD_ACMA] = TXPWR_LMT_ACMA, + [RTW_REGD_CHILE] = TXPWR_LMT_CHILE, + [RTW_REGD_MEX] = TXPWR_LMT_MEXICO, + [RTW_REGD_WW] = TXPWR_LMT_WW, +}; + +char *rtw_get_edcca_modes_str(char *buf, u8 modes[]) +{ +#define EDCCA_MODE_SEQ_COMPARE(result, operand) (result == RTW_EDCCA_MODE_NUM ? operand : (operand == RTW_EDCCA_MODE_NUM ? result : (result != operand ? -1 : result))) + + int mode = RTW_EDCCA_MODE_NUM; + int cnt = 0; + + mode = EDCCA_MODE_SEQ_COMPARE(mode, modes[BAND_ON_24G]); +#if CONFIG_IEEE80211_BAND_5GHZ + mode = EDCCA_MODE_SEQ_COMPARE(mode, modes[BAND_ON_5G]); +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + mode = EDCCA_MODE_SEQ_COMPARE(mode, modes[BAND_ON_6G]); +#endif + + if (mode != -1) { /* all available values are the same */ + cnt += snprintf(buf + cnt, EDCCA_MODES_STR_LEN - cnt - 1, "%s(%u)", rtw_edcca_mode_str(mode), mode); + if (cnt >= EDCCA_MODES_STR_LEN - 1) + goto exit; + } else { + cnt += snprintf(buf + cnt, EDCCA_MODES_STR_LEN - cnt - 1, "%s(%u) ", rtw_edcca_mode_str(modes[BAND_ON_24G]), modes[BAND_ON_24G]); + if (cnt >= EDCCA_MODES_STR_LEN - 1) + goto exit; + #if CONFIG_IEEE80211_BAND_5GHZ + cnt += snprintf(buf + cnt, EDCCA_MODES_STR_LEN - cnt - 1, "%s(%u) ", rtw_edcca_mode_str(modes[BAND_ON_5G]), modes[BAND_ON_5G]); + if (cnt >= EDCCA_MODES_STR_LEN - 1) + goto exit; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + cnt += snprintf(buf + cnt, EDCCA_MODES_STR_LEN - cnt - 1, "%s(%u) ", rtw_edcca_mode_str(modes[BAND_ON_6G]), modes[BAND_ON_6G]); + if (cnt >= EDCCA_MODES_STR_LEN - 1) + goto exit; + #endif + buf[cnt - 1] = 0; + } + +exit: + return buf; +} + +void rtw_edcca_mode_update(struct dvobj_priv *dvobj) +{ + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + + if (regsty->adaptivity_en == 0) { + /* force disable */ + rfctl->edcca_mode_2g = RTW_EDCCA_NORM; + #if CONFIG_IEEE80211_BAND_5GHZ + rfctl->edcca_mode_5g = RTW_EDCCA_NORM; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + rfctl->edcca_mode_6g = RTW_EDCCA_NORM; + #endif + + } else if (regsty->adaptivity_en == 1) { + /* force enable */ + if (!regsty->adaptivity_mode) { + /* adaptivity */ + rfctl->edcca_mode_2g = RTW_EDCCA_ADAPT; + #if CONFIG_IEEE80211_BAND_5GHZ + rfctl->edcca_mode_5g = RTW_EDCCA_ADAPT; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + rfctl->edcca_mode_6g = RTW_EDCCA_ADAPT; + #endif + } else { + /* carrier sense */ + rfctl->edcca_mode_2g = RTW_EDCCA_CS; + #if CONFIG_IEEE80211_BAND_5GHZ + rfctl->edcca_mode_5g = RTW_EDCCA_CS; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + rfctl->edcca_mode_6g = RTW_EDCCA_CS; + #endif + } + + } else { + u8 modes[BAND_MAX]; + char buf[EDCCA_MODES_STR_LEN]; + + /* by regulatory setting */ + #ifdef CONFIG_REGD_SRC_FROM_OS + if (rfctl->regd_src == REGD_SRC_OS + && rfctl->ChannelPlan == RTW_CHPLAN_UNSPECIFIED + ) { + modes[BAND_ON_24G] = rfctl->edcca_mode_2g = RTW_EDCCA_ADAPT; + #if CONFIG_IEEE80211_BAND_5GHZ + modes[BAND_ON_5G] = rfctl->edcca_mode_5g = RTW_EDCCA_ADAPT; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + modes[BAND_ON_6G] = rfctl->edcca_mode_6g = RTW_EDCCA_ADAPT; + #endif + RTW_PRINT("mapping %scountry:%c%c to edcca_mode:%s\n" + , RFCTL_REG_WORLDWIDE(rfctl) ? "" : "unsupported " + , rfctl->alpha2[0] + , rfctl->alpha2[1] + , rtw_get_edcca_modes_str(buf, modes) + ); + } else + #endif + { + modes[BAND_ON_24G] = rfctl->edcca_mode_2g = + rfctl->edcca_mode_2g_override != RTW_EDCCA_DEF ? rfctl->edcca_mode_2g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_2g(rfctl->ChannelPlan)); + #if CONFIG_IEEE80211_BAND_5GHZ + modes[BAND_ON_5G] = rfctl->edcca_mode_5g = + rfctl->edcca_mode_5g_override != RTW_EDCCA_DEF ? rfctl->edcca_mode_5g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_5g(rfctl->ChannelPlan)); + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + modes[BAND_ON_6G] = rfctl->edcca_mode_6g = + rfctl->edcca_mode_6g_override != RTW_EDCCA_DEF ? rfctl->edcca_mode_6g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_6g(rfctl->chplan_6g)); + #endif + RTW_PRINT("update edcca_mode:%s\n" + , rtw_get_edcca_modes_str(buf, modes) + ); + } + } +} + +u8 rtw_get_edcca_mode(struct dvobj_priv *dvobj, enum band_type band) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + u8 edcca_mode = RTW_EDCCA_NORM; + + if (band == BAND_ON_24G) + edcca_mode = rfctl->edcca_mode_2g; + #if CONFIG_IEEE80211_BAND_5GHZ + else if (band == BAND_ON_5G) + edcca_mode = rfctl->edcca_mode_5g; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + else if (band == BAND_ON_6G) + edcca_mode = rfctl->edcca_mode_6g; + #endif + + return edcca_mode; +} + +char *rtw_get_txpwr_lmt_names_str(char *buf, const char *names[], u8 unknown_bmp) +{ +#define NAME_DIFF ((void *)1) +/* input comes form organized database, string with same content will not have different pointer */ +#define NAME_SEQ_COMPARE(result, operand) (result == NULL ? operand : (operand == NULL ? result : (result != operand ? NAME_DIFF : result))) + + const char *name = NULL; + int cnt = 0; + + name = NAME_SEQ_COMPARE(name, names[BAND_ON_24G]); +#if CONFIG_IEEE80211_BAND_5GHZ + name = NAME_SEQ_COMPARE(name, names[BAND_ON_5G]); +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + name = NAME_SEQ_COMPARE(name, names[BAND_ON_6G]); +#endif + + if (name != NAME_DIFF) { /* all available values are the same */ + cnt += snprintf(buf + cnt, TXPWR_NAMES_STR_LEN - cnt - 1, "%s%s", (unknown_bmp & BIT(BAND_ON_24G)) ? "?" : "", name); + if (cnt >= TXPWR_NAMES_STR_LEN - 1) + goto exit; + } else { + cnt += snprintf(buf + cnt, TXPWR_NAMES_STR_LEN - cnt - 1, "%s%s ", (unknown_bmp & BIT(BAND_ON_24G)) ? "?" : "", names[BAND_ON_24G]); + if (cnt >= TXPWR_NAMES_STR_LEN - 1) + goto exit; + #if CONFIG_IEEE80211_BAND_5GHZ + cnt += snprintf(buf + cnt, TXPWR_NAMES_STR_LEN - cnt - 1, "%s%s ", (unknown_bmp & BIT(BAND_ON_5G)) ? "?" : "", names[BAND_ON_5G]); + if (cnt >= TXPWR_NAMES_STR_LEN - 1) + goto exit; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + cnt += snprintf(buf + cnt, TXPWR_NAMES_STR_LEN - cnt - 1, "%s%s ", (unknown_bmp & BIT(BAND_ON_6G)) ? "?" : "", names[BAND_ON_6G]); + if (cnt >= TXPWR_NAMES_STR_LEN - 1) + goto exit; + #endif + buf[cnt - 1] = 0; + } + +exit: + return buf; +} + +#if CONFIG_IEEE80211_BAND_5GHZ +#define COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_5G_OVERRIDE(_val) , .edcca_mode_5g_override = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_5G_OVERRIDE(_val) +#endif + +#if CONFIG_IEEE80211_BAND_6GHZ +#define COUNTRY_CHPLAN_ASSIGN_CHPLAN_6G(_val) , .chplan_6g = (_val) +#define COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_6G_OVERRIDE(_val) , .edcca_mode_6g_override = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_CHPLAN_6G(_val) +#define COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_6G_OVERRIDE(_val) +#endif + +#if defined(CONFIG_80211AC_VHT) || defined(CONFIG_80211AX_HE) +#define COUNTRY_CHPLAN_ASSIGN_PROTO_EN(_val) , .proto_en = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_PROTO_EN(_val) +#endif + +#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _chplan_6g, _txpwr_lmt_override, _en_11ax, _en_11ac) \ + {.alpha2 = (_alpha2), .chplan = (_chplan) \ + COUNTRY_CHPLAN_ASSIGN_CHPLAN_6G(_chplan_6g) \ + , .edcca_mode_2g_override = RTW_EDCCA_DEF \ + COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_5G_OVERRIDE(RTW_EDCCA_DEF) \ + COUNTRY_CHPLAN_ASSIGN_EDCCA_MODE_6G_OVERRIDE(RTW_EDCCA_DEF) \ + , .txpwr_lmt_override = TXPWR_LMT_##_txpwr_lmt_override \ + COUNTRY_CHPLAN_ASSIGN_PROTO_EN((_en_11ax ? CHPLAN_PROTO_EN_AX : 0) | (_en_11ac ? CHPLAN_PROTO_EN_AC : 0)) \ + } + +static const struct country_chplan world_wide_chplan = + COUNTRY_CHPLAN_ENT(WORLDWIDE_ALPHA2, RTW_CHPLAN_WORLDWIDE, RTW_CHPLAN_6G_WORLDWIDE, DEF, 1, 1); + +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP #include "../platform/custom_country_chplan.h" @@ -631,1442 +1409,1442 @@ const char *_rtw_dfs_regd_str[] = { #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x34, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x30, 1), - COUNTRY_CHPLAN_ENT("CN", 0x51, 1), - COUNTRY_CHPLAN_ENT("CO", 0x34, 1), - COUNTRY_CHPLAN_ENT("CR", 0x34, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x34, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x34, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x34, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x3D, 0), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x47, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x34, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x34, 1), - COUNTRY_CHPLAN_ENT("PE", 0x34, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x34, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x34, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("UA", 0x36, 0), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x36, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */ static const struct country_chplan RTL8821AU_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x34, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x3D, 0), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 0), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("UA", 0x36, 0), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x36, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */ static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */ static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x34, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 0), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("UA", 0x36, 0), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x36, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */ static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AW", 0x34, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BB", 0x34, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BN", 0x47, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x20, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x34, 1), - COUNTRY_CHPLAN_ENT("CR", 0x34, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x34, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x34, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GD", 0x76, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GN", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x34, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HT", 0x34, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x34, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x34, 1), - COUNTRY_CHPLAN_ENT("PE", 0x34, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x34, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x34, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("RW", 0x26, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SC", 0x34, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VC", 0x34, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AW", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BB", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x20, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ET", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GD", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AW", 0x34, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BS", 0x34, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x20, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x34, 1), - COUNTRY_CHPLAN_ENT("CR", 0x34, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x34, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x34, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GD", 0x76, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x34, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MG", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x34, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x34, 1), - COUNTRY_CHPLAN_ENT("PE", 0x34, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x34, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x34, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("RW", 0x26, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("SZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AW", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BS", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x20, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ET", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GD", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */ static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BB", 0x34, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x20, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x34, 1), - COUNTRY_CHPLAN_ENT("CR", 0x34, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x34, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x34, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x34, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HT", 0x34, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x34, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x34, 1), - COUNTRY_CHPLAN_ENT("PE", 0x34, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x34, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x34, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("YE", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BB", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x20, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("YE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AW", 0x34, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x20, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x34, 1), - COUNTRY_CHPLAN_ENT("CR", 0x34, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x34, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x34, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("EH", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GD", 0x76, 1), - COUNTRY_CHPLAN_ENT("GF", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x34, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x34, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x34, 1), - COUNTRY_CHPLAN_ENT("PE", 0x34, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x34, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x34, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("RW", 0x26, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SC", 0x34, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("ST", 0x34, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TF", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x39, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x34, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("YT", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AW", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x20, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EH", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ET", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GD", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SC", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ST", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x39, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("YT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */ static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x2A, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x76, 1), - COUNTRY_CHPLAN_ENT("CR", 0x76, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x76, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x76, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x61, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x34, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NA", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x76, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x76, 1), - COUNTRY_CHPLAN_ENT("PE", 0x76, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x76, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x76, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x76, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("US", 0x76, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x2A, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x34, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */ static const struct country_chplan RTL8822BE_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BB", 0x76, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BM", 0x76, 1), - COUNTRY_CHPLAN_ENT("BN", 0x47, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BS", 0x76, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x2B, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x76, 1), - COUNTRY_CHPLAN_ENT("CR", 0x76, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x76, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x76, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("EH", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FJ", 0x76, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GE", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GI", 0x26, 1), - COUNTRY_CHPLAN_ENT("GL", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GN", 0x26, 1), - COUNTRY_CHPLAN_ENT("GP", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x61, 1), - COUNTRY_CHPLAN_ENT("GU", 0x76, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HT", 0x76, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x3D, 0), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MG", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MO", 0x35, 1), - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x4D, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NA", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x76, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x76, 1), - COUNTRY_CHPLAN_ENT("PE", 0x76, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x76, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x76, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SC", 0x76, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("ST", 0x76, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TF", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), - COUNTRY_CHPLAN_ENT("TW", 0x76, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x76, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("YT", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BB", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BM", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BS", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x2B, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EH", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FJ", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GP", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GU", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MO", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x4D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ST", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, UKRAINE, 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("YT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */ static const struct country_chplan RTL8821CE_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BB", 0x76, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BM", 0x76, 1), - COUNTRY_CHPLAN_ENT("BN", 0x47, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BS", 0x76, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x2B, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x76, 1), - COUNTRY_CHPLAN_ENT("CR", 0x76, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x76, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x76, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("EH", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FJ", 0x76, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GE", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GI", 0x26, 1), - COUNTRY_CHPLAN_ENT("GL", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GN", 0x26, 1), - COUNTRY_CHPLAN_ENT("GP", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x61, 1), - COUNTRY_CHPLAN_ENT("GU", 0x76, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HT", 0x76, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("ID", 0x3D, 0), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x28, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MG", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MO", 0x35, 1), - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x4D, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NA", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x76, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x76, 1), - COUNTRY_CHPLAN_ENT("PE", 0x76, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x76, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x76, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SC", 0x76, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("ST", 0x76, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TF", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TW", 0x76, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x76, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("YT", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BB", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BM", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BS", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x2B, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EH", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ET", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FJ", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GP", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GU", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0x00, DEF , 0, 0), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x28, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MO", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x4D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ST", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, UKRAINE, 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("YT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822CE) /* 2018 certify */ static const struct country_chplan RTL8822CE_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), - COUNTRY_CHPLAN_ENT("AW", 0x76, 1), - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), - COUNTRY_CHPLAN_ENT("BB", 0x76, 1), - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("BM", 0x76, 1), - COUNTRY_CHPLAN_ENT("BN", 0x47, 1), - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), - COUNTRY_CHPLAN_ENT("BS", 0x76, 1), - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CA", 0x2B, 1), - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), - COUNTRY_CHPLAN_ENT("CO", 0x76, 1), - COUNTRY_CHPLAN_ENT("CR", 0x76, 1), - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), - COUNTRY_CHPLAN_ENT("DO", 0x76, 1), - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), - COUNTRY_CHPLAN_ENT("EC", 0x76, 1), - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), - COUNTRY_CHPLAN_ENT("EH", 0x47, 1), - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), - COUNTRY_CHPLAN_ENT("FJ", 0x76, 1), - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), - COUNTRY_CHPLAN_ENT("GE", 0x26, 1), - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), - COUNTRY_CHPLAN_ENT("GI", 0x26, 1), - COUNTRY_CHPLAN_ENT("GL", 0x26, 1), - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), - COUNTRY_CHPLAN_ENT("GN", 0x26, 1), - COUNTRY_CHPLAN_ENT("GP", 0x26, 1), - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), - COUNTRY_CHPLAN_ENT("GT", 0x61, 1), - COUNTRY_CHPLAN_ENT("GU", 0x76, 1), - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), - COUNTRY_CHPLAN_ENT("HT", 0x76, 1), - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), - COUNTRY_CHPLAN_ENT("KM", 0x26, 1), - COUNTRY_CHPLAN_ENT("KR", 0x4B, 1), - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), - COUNTRY_CHPLAN_ENT("MG", 0x26, 1), - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), - COUNTRY_CHPLAN_ENT("MO", 0x35, 1), - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), - COUNTRY_CHPLAN_ENT("MX", 0x4D, 1), - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("NA", 0x26, 1), - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), - COUNTRY_CHPLAN_ENT("NI", 0x76, 1), - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), - COUNTRY_CHPLAN_ENT("PA", 0x76, 1), - COUNTRY_CHPLAN_ENT("PE", 0x76, 1), - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), - COUNTRY_CHPLAN_ENT("PR", 0x76, 1), - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), - COUNTRY_CHPLAN_ENT("PY", 0x76, 1), - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), - COUNTRY_CHPLAN_ENT("SC", 0x76, 1), - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), - COUNTRY_CHPLAN_ENT("ST", 0x76, 1), - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), - COUNTRY_CHPLAN_ENT("SZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), - COUNTRY_CHPLAN_ENT("TF", 0x26, 1), - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), - COUNTRY_CHPLAN_ENT("TW", 0x76, 1), - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), - COUNTRY_CHPLAN_ENT("US", 0x76, 1), - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), - COUNTRY_CHPLAN_ENT("YT", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), + COUNTRY_CHPLAN_ENT("AE", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AO", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AR", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AU", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AW", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("AZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BB", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BH", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BM", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BO", 0x73, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BS", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BW", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("BY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CA", 0x2B, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CL", 0x2D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CN", 0x48, 0x00, CN , 0, 1), + COUNTRY_CHPLAN_ENT("CO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CY", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("CZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DO", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EG", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("EH", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ES", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ET", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FJ", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("FR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GP", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GT", 0x61, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GU", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("GW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HK", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HT", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("HU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IL", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IN", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("IT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JM", 0x32, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JO", 0x49, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("JP", 0x27, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KE", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KH", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KR", 0x4B, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("KZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LB", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("LV", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MA", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MC", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ME", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ML", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MO", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MQ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MU", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MW", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MX", 0x4D, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MY", 0x63, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("MZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NA", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NI", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NP", 0x48, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("NZ", 0x45, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("OM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PA", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PE", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PR", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("PY", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("QA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RO", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RS", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("RU", 0x59, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SC", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SE", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SG", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SI", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SK", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SL", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SN", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ST", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SV", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("SZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TD", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TF", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TH", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TJ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TN", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TR", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TW", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("TZ", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UA", 0x35, 0x00, UKRAINE, 0, 1), + COUNTRY_CHPLAN_ENT("UG", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("US", 0x76, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("UZ", 0x47, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("VN", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("YT", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZA", 0x35, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZM", 0x26, 0x00, DEF , 0, 1), + COUNTRY_CHPLAN_ENT("ZW", 0x26, 0x00, DEF , 0, 1), }; #endif @@ -2123,255 +2901,269 @@ static u16 rtw_def_module_country_chplan_map(const struct country_chplan **hal_m #else static const struct country_chplan country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AD", 0x26, 1), /* Andorra */ - COUNTRY_CHPLAN_ENT("AE", 0x35, 1), /* United Arab Emirates */ - COUNTRY_CHPLAN_ENT("AF", 0x42, 1), /* Afghanistan */ - COUNTRY_CHPLAN_ENT("AG", 0x76, 1), /* Antigua & Barbuda */ - COUNTRY_CHPLAN_ENT("AI", 0x26, 1), /* Anguilla(UK) */ - COUNTRY_CHPLAN_ENT("AL", 0x26, 1), /* Albania */ - COUNTRY_CHPLAN_ENT("AM", 0x26, 1), /* Armenia */ - COUNTRY_CHPLAN_ENT("AN", 0x76, 1), /* Netherlands Antilles */ - COUNTRY_CHPLAN_ENT("AO", 0x47, 1), /* Angola */ - COUNTRY_CHPLAN_ENT("AQ", 0x26, 1), /* Antarctica */ - COUNTRY_CHPLAN_ENT("AR", 0x61, 1), /* Argentina */ - COUNTRY_CHPLAN_ENT("AS", 0x76, 1), /* American Samoa */ - COUNTRY_CHPLAN_ENT("AT", 0x26, 1), /* Austria */ - COUNTRY_CHPLAN_ENT("AU", 0x45, 1), /* Australia */ - COUNTRY_CHPLAN_ENT("AW", 0x76, 1), /* Aruba */ - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), /* Azerbaijan */ - COUNTRY_CHPLAN_ENT("BA", 0x26, 1), /* Bosnia & Herzegovina */ - COUNTRY_CHPLAN_ENT("BB", 0x76, 1), /* Barbados */ - COUNTRY_CHPLAN_ENT("BD", 0x26, 1), /* Bangladesh */ - COUNTRY_CHPLAN_ENT("BE", 0x26, 1), /* Belgium */ - COUNTRY_CHPLAN_ENT("BF", 0x26, 1), /* Burkina Faso */ - COUNTRY_CHPLAN_ENT("BG", 0x26, 1), /* Bulgaria */ - COUNTRY_CHPLAN_ENT("BH", 0x48, 1), /* Bahrain */ - COUNTRY_CHPLAN_ENT("BI", 0x26, 1), /* Burundi */ - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), /* Benin */ - COUNTRY_CHPLAN_ENT("BM", 0x76, 1), /* Bermuda (UK) */ - COUNTRY_CHPLAN_ENT("BN", 0x47, 1), /* Brunei */ - COUNTRY_CHPLAN_ENT("BO", 0x73, 1), /* Bolivia */ - COUNTRY_CHPLAN_ENT("BR", 0x62, 1), /* Brazil */ - COUNTRY_CHPLAN_ENT("BS", 0x76, 1), /* Bahamas */ - COUNTRY_CHPLAN_ENT("BT", 0x26, 1), /* Bhutan */ - COUNTRY_CHPLAN_ENT("BV", 0x26, 1), /* Bouvet Island (Norway) */ - COUNTRY_CHPLAN_ENT("BW", 0x35, 1), /* Botswana */ - COUNTRY_CHPLAN_ENT("BY", 0x26, 1), /* Belarus */ - COUNTRY_CHPLAN_ENT("BZ", 0x76, 1), /* Belize */ - COUNTRY_CHPLAN_ENT("CA", 0x2B, 1), /* Canada */ - COUNTRY_CHPLAN_ENT("CC", 0x26, 1), /* Cocos (Keeling) Islands (Australia) */ - COUNTRY_CHPLAN_ENT("CD", 0x26, 1), /* Congo, Republic of the */ - COUNTRY_CHPLAN_ENT("CF", 0x26, 1), /* Central African Republic */ - COUNTRY_CHPLAN_ENT("CG", 0x26, 1), /* Congo, Democratic Republic of the. Zaire */ - COUNTRY_CHPLAN_ENT("CH", 0x26, 1), /* Switzerland */ - COUNTRY_CHPLAN_ENT("CI", 0x42, 1), /* Cote d'Ivoire */ - COUNTRY_CHPLAN_ENT("CK", 0x26, 1), /* Cook Islands */ - COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), /* Chile */ - COUNTRY_CHPLAN_ENT("CM", 0x26, 1), /* Cameroon */ - COUNTRY_CHPLAN_ENT("CN", 0x48, 1), /* China */ - COUNTRY_CHPLAN_ENT("CO", 0x76, 1), /* Colombia */ - COUNTRY_CHPLAN_ENT("CR", 0x76, 1), /* Costa Rica */ - COUNTRY_CHPLAN_ENT("CV", 0x26, 1), /* Cape Verde */ - COUNTRY_CHPLAN_ENT("CX", 0x45, 1), /* Christmas Island (Australia) */ - COUNTRY_CHPLAN_ENT("CY", 0x26, 1), /* Cyprus */ - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), /* Czech Republic */ - COUNTRY_CHPLAN_ENT("DE", 0x26, 1), /* Germany */ - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), /* Djibouti */ - COUNTRY_CHPLAN_ENT("DK", 0x26, 1), /* Denmark */ - COUNTRY_CHPLAN_ENT("DM", 0x76, 1), /* Dominica */ - COUNTRY_CHPLAN_ENT("DO", 0x76, 1), /* Dominican Republic */ - COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), /* Algeria */ - COUNTRY_CHPLAN_ENT("EC", 0x76, 1), /* Ecuador */ - COUNTRY_CHPLAN_ENT("EE", 0x26, 1), /* Estonia */ - COUNTRY_CHPLAN_ENT("EG", 0x47, 1), /* Egypt */ - COUNTRY_CHPLAN_ENT("EH", 0x47, 1), /* Western Sahara */ - COUNTRY_CHPLAN_ENT("ER", 0x26, 1), /* Eritrea */ - COUNTRY_CHPLAN_ENT("ES", 0x26, 1), /* Spain, Canary Islands, Ceuta, Melilla */ - COUNTRY_CHPLAN_ENT("ET", 0x26, 1), /* Ethiopia */ - COUNTRY_CHPLAN_ENT("FI", 0x26, 1), /* Finland */ - COUNTRY_CHPLAN_ENT("FJ", 0x76, 1), /* Fiji */ - COUNTRY_CHPLAN_ENT("FK", 0x26, 1), /* Falkland Islands (Islas Malvinas) (UK) */ - COUNTRY_CHPLAN_ENT("FM", 0x76, 1), /* Micronesia, Federated States of (USA) */ - COUNTRY_CHPLAN_ENT("FO", 0x26, 1), /* Faroe Islands (Denmark) */ - COUNTRY_CHPLAN_ENT("FR", 0x26, 1), /* France */ - COUNTRY_CHPLAN_ENT("GA", 0x26, 1), /* Gabon */ - COUNTRY_CHPLAN_ENT("GB", 0x26, 1), /* Great Britain (United Kingdom; England) */ - COUNTRY_CHPLAN_ENT("GD", 0x76, 1), /* Grenada */ - COUNTRY_CHPLAN_ENT("GE", 0x26, 1), /* Georgia */ - COUNTRY_CHPLAN_ENT("GF", 0x26, 1), /* French Guiana */ - COUNTRY_CHPLAN_ENT("GG", 0x26, 1), /* Guernsey (UK) */ - COUNTRY_CHPLAN_ENT("GH", 0x26, 1), /* Ghana */ - COUNTRY_CHPLAN_ENT("GI", 0x26, 1), /* Gibraltar (UK) */ - COUNTRY_CHPLAN_ENT("GL", 0x26, 1), /* Greenland (Denmark) */ - COUNTRY_CHPLAN_ENT("GM", 0x26, 1), /* Gambia */ - COUNTRY_CHPLAN_ENT("GN", 0x26, 1), /* Guinea */ - COUNTRY_CHPLAN_ENT("GP", 0x26, 1), /* Guadeloupe (France) */ - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), /* Equatorial Guinea */ - COUNTRY_CHPLAN_ENT("GR", 0x26, 1), /* Greece */ - COUNTRY_CHPLAN_ENT("GS", 0x26, 1), /* South Georgia and the Sandwich Islands (UK) */ - COUNTRY_CHPLAN_ENT("GT", 0x61, 1), /* Guatemala */ - COUNTRY_CHPLAN_ENT("GU", 0x76, 1), /* Guam (USA) */ - COUNTRY_CHPLAN_ENT("GW", 0x26, 1), /* Guinea-Bissau */ - COUNTRY_CHPLAN_ENT("GY", 0x44, 1), /* Guyana */ - COUNTRY_CHPLAN_ENT("HK", 0x35, 1), /* Hong Kong */ - COUNTRY_CHPLAN_ENT("HM", 0x45, 1), /* Heard and McDonald Islands (Australia) */ - COUNTRY_CHPLAN_ENT("HN", 0x32, 1), /* Honduras */ - COUNTRY_CHPLAN_ENT("HR", 0x26, 1), /* Croatia */ - COUNTRY_CHPLAN_ENT("HT", 0x76, 1), /* Haiti */ - COUNTRY_CHPLAN_ENT("HU", 0x26, 1), /* Hungary */ - COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), /* Indonesia */ - COUNTRY_CHPLAN_ENT("IE", 0x26, 1), /* Ireland */ - COUNTRY_CHPLAN_ENT("IL", 0x47, 1), /* Israel */ - COUNTRY_CHPLAN_ENT("IM", 0x26, 1), /* Isle of Man (UK) */ - COUNTRY_CHPLAN_ENT("IN", 0x48, 1), /* India */ - COUNTRY_CHPLAN_ENT("IO", 0x26, 1), /* British Indian Ocean Territory (UK) */ - COUNTRY_CHPLAN_ENT("IQ", 0x26, 1), /* Iraq */ - COUNTRY_CHPLAN_ENT("IR", 0x26, 0), /* Iran */ - COUNTRY_CHPLAN_ENT("IS", 0x26, 1), /* Iceland */ - COUNTRY_CHPLAN_ENT("IT", 0x26, 1), /* Italy */ - COUNTRY_CHPLAN_ENT("JE", 0x26, 1), /* Jersey (UK) */ - COUNTRY_CHPLAN_ENT("JM", 0x32, 1), /* Jamaica */ - COUNTRY_CHPLAN_ENT("JO", 0x49, 1), /* Jordan */ - COUNTRY_CHPLAN_ENT("JP", 0x27, 1), /* Japan- Telec */ - COUNTRY_CHPLAN_ENT("KE", 0x47, 1), /* Kenya */ - COUNTRY_CHPLAN_ENT("KG", 0x26, 1), /* Kyrgyzstan */ - COUNTRY_CHPLAN_ENT("KH", 0x26, 1), /* Cambodia */ - COUNTRY_CHPLAN_ENT("KI", 0x26, 1), /* Kiribati */ - COUNTRY_CHPLAN_ENT("KM", 0x26, 1), /* Comoros */ - COUNTRY_CHPLAN_ENT("KN", 0x76, 1), /* Saint Kitts and Nevis */ - COUNTRY_CHPLAN_ENT("KR", 0x4B, 1), /* South Korea */ - COUNTRY_CHPLAN_ENT("KW", 0x26, 1), /* Kuwait */ - COUNTRY_CHPLAN_ENT("KY", 0x76, 1), /* Cayman Islands (UK) */ - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), /* Kazakhstan */ - COUNTRY_CHPLAN_ENT("LA", 0x26, 1), /* Laos */ - COUNTRY_CHPLAN_ENT("LB", 0x26, 1), /* Lebanon */ - COUNTRY_CHPLAN_ENT("LC", 0x76, 1), /* Saint Lucia */ - COUNTRY_CHPLAN_ENT("LI", 0x26, 1), /* Liechtenstein */ - COUNTRY_CHPLAN_ENT("LK", 0x26, 1), /* Sri Lanka */ - COUNTRY_CHPLAN_ENT("LR", 0x26, 1), /* Liberia */ - COUNTRY_CHPLAN_ENT("LS", 0x26, 1), /* Lesotho */ - COUNTRY_CHPLAN_ENT("LT", 0x26, 1), /* Lithuania */ - COUNTRY_CHPLAN_ENT("LU", 0x26, 1), /* Luxembourg */ - COUNTRY_CHPLAN_ENT("LV", 0x26, 1), /* Latvia */ - COUNTRY_CHPLAN_ENT("LY", 0x26, 1), /* Libya */ - COUNTRY_CHPLAN_ENT("MA", 0x47, 1), /* Morocco */ - COUNTRY_CHPLAN_ENT("MC", 0x26, 1), /* Monaco */ - COUNTRY_CHPLAN_ENT("MD", 0x26, 1), /* Moldova */ - COUNTRY_CHPLAN_ENT("ME", 0x26, 1), /* Montenegro */ - COUNTRY_CHPLAN_ENT("MF", 0x76, 1), /* Saint Martin */ - COUNTRY_CHPLAN_ENT("MG", 0x26, 1), /* Madagascar */ - COUNTRY_CHPLAN_ENT("MH", 0x76, 1), /* Marshall Islands (USA) */ - COUNTRY_CHPLAN_ENT("MK", 0x26, 1), /* Republic of Macedonia (FYROM) */ - COUNTRY_CHPLAN_ENT("ML", 0x26, 1), /* Mali */ - COUNTRY_CHPLAN_ENT("MM", 0x26, 1), /* Burma (Myanmar) */ - COUNTRY_CHPLAN_ENT("MN", 0x26, 1), /* Mongolia */ - COUNTRY_CHPLAN_ENT("MO", 0x35, 1), /* Macau */ - COUNTRY_CHPLAN_ENT("MP", 0x76, 1), /* Northern Mariana Islands (USA) */ - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), /* Martinique (France) */ - COUNTRY_CHPLAN_ENT("MR", 0x26, 1), /* Mauritania */ - COUNTRY_CHPLAN_ENT("MS", 0x26, 1), /* Montserrat (UK) */ - COUNTRY_CHPLAN_ENT("MT", 0x26, 1), /* Malta */ - COUNTRY_CHPLAN_ENT("MU", 0x26, 1), /* Mauritius */ - COUNTRY_CHPLAN_ENT("MV", 0x47, 1), /* Maldives */ - COUNTRY_CHPLAN_ENT("MW", 0x26, 1), /* Malawi */ - COUNTRY_CHPLAN_ENT("MX", 0x4D, 1), /* Mexico */ - COUNTRY_CHPLAN_ENT("MY", 0x63, 1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), /* Mozambique */ - COUNTRY_CHPLAN_ENT("NA", 0x26, 1), /* Namibia */ - COUNTRY_CHPLAN_ENT("NC", 0x26, 1), /* New Caledonia */ - COUNTRY_CHPLAN_ENT("NE", 0x26, 1), /* Niger */ - COUNTRY_CHPLAN_ENT("NF", 0x45, 1), /* Norfolk Island (Australia) */ - COUNTRY_CHPLAN_ENT("NG", 0x75, 1), /* Nigeria */ - COUNTRY_CHPLAN_ENT("NI", 0x76, 1), /* Nicaragua */ - COUNTRY_CHPLAN_ENT("NL", 0x26, 1), /* Netherlands */ - COUNTRY_CHPLAN_ENT("NO", 0x26, 1), /* Norway */ - COUNTRY_CHPLAN_ENT("NP", 0x48, 1), /* Nepal */ - COUNTRY_CHPLAN_ENT("NR", 0x26, 1), /* Nauru */ - COUNTRY_CHPLAN_ENT("NU", 0x45, 1), /* Niue */ - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), /* New Zealand */ - COUNTRY_CHPLAN_ENT("OM", 0x26, 1), /* Oman */ - COUNTRY_CHPLAN_ENT("PA", 0x76, 1), /* Panama */ - COUNTRY_CHPLAN_ENT("PE", 0x76, 1), /* Peru */ - COUNTRY_CHPLAN_ENT("PF", 0x26, 1), /* French Polynesia (France) */ - COUNTRY_CHPLAN_ENT("PG", 0x35, 1), /* Papua New Guinea */ - COUNTRY_CHPLAN_ENT("PH", 0x35, 1), /* Philippines */ - COUNTRY_CHPLAN_ENT("PK", 0x51, 1), /* Pakistan */ - COUNTRY_CHPLAN_ENT("PL", 0x26, 1), /* Poland */ - COUNTRY_CHPLAN_ENT("PM", 0x26, 1), /* Saint Pierre and Miquelon (France) */ - COUNTRY_CHPLAN_ENT("PR", 0x76, 1), /* Puerto Rico */ - COUNTRY_CHPLAN_ENT("PT", 0x26, 1), /* Portugal */ - COUNTRY_CHPLAN_ENT("PW", 0x76, 1), /* Palau */ - COUNTRY_CHPLAN_ENT("PY", 0x76, 1), /* Paraguay */ - COUNTRY_CHPLAN_ENT("QA", 0x35, 1), /* Qatar */ - COUNTRY_CHPLAN_ENT("RE", 0x26, 1), /* Reunion (France) */ - COUNTRY_CHPLAN_ENT("RO", 0x26, 1), /* Romania */ - COUNTRY_CHPLAN_ENT("RS", 0x26, 1), /* Serbia, Kosovo */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 1), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("RW", 0x26, 1), /* Rwanda */ - COUNTRY_CHPLAN_ENT("SA", 0x35, 1), /* Saudi Arabia */ - COUNTRY_CHPLAN_ENT("SB", 0x26, 1), /* Solomon Islands */ - COUNTRY_CHPLAN_ENT("SC", 0x76, 1), /* Seychelles */ - COUNTRY_CHPLAN_ENT("SE", 0x26, 1), /* Sweden */ - COUNTRY_CHPLAN_ENT("SG", 0x35, 1), /* Singapore */ - COUNTRY_CHPLAN_ENT("SH", 0x26, 1), /* Saint Helena (UK) */ - COUNTRY_CHPLAN_ENT("SI", 0x26, 1), /* Slovenia */ - COUNTRY_CHPLAN_ENT("SJ", 0x26, 1), /* Svalbard (Norway) */ - COUNTRY_CHPLAN_ENT("SK", 0x26, 1), /* Slovakia */ - COUNTRY_CHPLAN_ENT("SL", 0x26, 1), /* Sierra Leone */ - COUNTRY_CHPLAN_ENT("SM", 0x26, 1), /* San Marino */ - COUNTRY_CHPLAN_ENT("SN", 0x26, 1), /* Senegal */ - COUNTRY_CHPLAN_ENT("SO", 0x26, 1), /* Somalia */ - COUNTRY_CHPLAN_ENT("SR", 0x74, 1), /* Suriname */ - COUNTRY_CHPLAN_ENT("ST", 0x76, 1), /* Sao Tome and Principe */ - COUNTRY_CHPLAN_ENT("SV", 0x30, 1), /* El Salvador */ - COUNTRY_CHPLAN_ENT("SX", 0x76, 1), /* Sint Marteen */ - COUNTRY_CHPLAN_ENT("SZ", 0x26, 1), /* Swaziland */ - COUNTRY_CHPLAN_ENT("TC", 0x26, 1), /* Turks and Caicos Islands (UK) */ - COUNTRY_CHPLAN_ENT("TD", 0x26, 1), /* Chad */ - COUNTRY_CHPLAN_ENT("TF", 0x26, 1), /* French Southern and Antarctic Lands (FR Southern Territories) */ - COUNTRY_CHPLAN_ENT("TG", 0x26, 1), /* Togo */ - COUNTRY_CHPLAN_ENT("TH", 0x35, 1), /* Thailand */ - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), /* Tajikistan */ - COUNTRY_CHPLAN_ENT("TK", 0x45, 1), /* Tokelau */ - COUNTRY_CHPLAN_ENT("TM", 0x26, 1), /* Turkmenistan */ - COUNTRY_CHPLAN_ENT("TN", 0x47, 1), /* Tunisia */ - COUNTRY_CHPLAN_ENT("TO", 0x26, 1), /* Tonga */ - COUNTRY_CHPLAN_ENT("TR", 0x26, 1), /* Turkey, Northern Cyprus */ - COUNTRY_CHPLAN_ENT("TT", 0x76, 1), /* Trinidad & Tobago */ - COUNTRY_CHPLAN_ENT("TV", 0x21, 0), /* Tuvalu */ - COUNTRY_CHPLAN_ENT("TW", 0x76, 1), /* Taiwan */ - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), /* Tanzania */ - COUNTRY_CHPLAN_ENT("UA", 0x35, 1), /* Ukraine */ - COUNTRY_CHPLAN_ENT("UG", 0x26, 1), /* Uganda */ - COUNTRY_CHPLAN_ENT("US", 0x76, 1), /* United States of America (USA) */ - COUNTRY_CHPLAN_ENT("UY", 0x30, 1), /* Uruguay */ - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), /* Uzbekistan */ - COUNTRY_CHPLAN_ENT("VA", 0x26, 1), /* Holy See (Vatican City) */ - COUNTRY_CHPLAN_ENT("VC", 0x76, 1), /* Saint Vincent and the Grenadines */ - COUNTRY_CHPLAN_ENT("VE", 0x30, 1), /* Venezuela */ - COUNTRY_CHPLAN_ENT("VG", 0x76, 1), /* British Virgin Islands (UK) */ - COUNTRY_CHPLAN_ENT("VI", 0x76, 1), /* United States Virgin Islands (USA) */ - COUNTRY_CHPLAN_ENT("VN", 0x35, 1), /* Vietnam */ - COUNTRY_CHPLAN_ENT("VU", 0x26, 1), /* Vanuatu */ - COUNTRY_CHPLAN_ENT("WF", 0x26, 1), /* Wallis and Futuna (France) */ - COUNTRY_CHPLAN_ENT("WS", 0x76, 1), /* Samoa */ - COUNTRY_CHPLAN_ENT("YE", 0x26, 1), /* Yemen */ - COUNTRY_CHPLAN_ENT("YT", 0x26, 1), /* Mayotte (France) */ - COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), /* South Africa */ - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), /* Zambia */ - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), /* Zimbabwe */ + COUNTRY_CHPLAN_ENT("AD", 0x3A, 0x00, DEF , 1, 1), /* Andorra */ + COUNTRY_CHPLAN_ENT("AE", 0x5E, 0x00, DEF , 1, 1), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AF", 0x42, 0x00, DEF , 1, 1), /* Afghanistan */ + COUNTRY_CHPLAN_ENT("AG", 0x76, 0x00, DEF , 1, 1), /* Antigua & Barbuda */ + COUNTRY_CHPLAN_ENT("AI", 0x5E, 0x00, DEF , 1, 1), /* Anguilla(UK) */ + COUNTRY_CHPLAN_ENT("AL", 0x5E, 0x00, DEF , 1, 1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x5E, 0x00, DEF , 1, 1), /* Armenia */ + COUNTRY_CHPLAN_ENT("AN", 0x76, 0x00, DEF , 1, 1), /* Netherlands Antilles */ + COUNTRY_CHPLAN_ENT("AO", 0x5E, 0x00, DEF , 1, 1), /* Angola */ + COUNTRY_CHPLAN_ENT("AQ", 0x26, 0x00, DEF , 1, 1), /* Antarctica */ + COUNTRY_CHPLAN_ENT("AR", 0x4D, 0x00, DEF , 1, 1), /* Argentina */ + COUNTRY_CHPLAN_ENT("AS", 0x76, 0x00, DEF , 1, 1), /* American Samoa */ + COUNTRY_CHPLAN_ENT("AT", 0x5E, 0x00, DEF , 1, 1), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x03, 0x00, DEF , 1, 1), /* Australia */ + COUNTRY_CHPLAN_ENT("AW", 0x76, 0x00, DEF , 1, 1), /* Aruba */ + COUNTRY_CHPLAN_ENT("AZ", 0x5E, 0x00, DEF , 1, 1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x5E, 0x00, DEF , 1, 1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x76, 0x00, DEF , 1, 1), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x5E, 0x00, DEF , 1, 1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x5E, 0x00, DEF , 1, 1), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x5E, 0x00, DEF , 1, 1), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x5E, 0x00, DEF , 1, 1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x06, 0x00, DEF , 1, 1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x3A, 0x00, DEF , 1, 1), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x3A, 0x00, DEF , 1, 1), /* Benin */ + COUNTRY_CHPLAN_ENT("BM", 0x76, 0x00, DEF , 1, 1), /* Bermuda (UK) */ + COUNTRY_CHPLAN_ENT("BN", 0x06, 0x00, DEF , 1, 1), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x61, 0x00, DEF , 1, 1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x62, 0x00, DEF , 1, 1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x76, 0x00, DEF , 1, 1), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BT", 0x5E, 0x00, DEF , 1, 1), /* Bhutan */ + COUNTRY_CHPLAN_ENT("BV", 0x5E, 0x00, DEF , 1, 1), /* Bouvet Island (Norway) */ + COUNTRY_CHPLAN_ENT("BW", 0x5E, 0x00, DEF , 1, 1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x08, 0x00, DEF , 0, 1), /* Belarus */ + COUNTRY_CHPLAN_ENT("BZ", 0x76, 0x00, DEF , 1, 1), /* Belize */ + COUNTRY_CHPLAN_ENT("CA", 0x2B, 0x00, DEF , 1, 1), /* Canada */ + COUNTRY_CHPLAN_ENT("CC", 0x3A, 0x00, DEF , 1, 1), /* Cocos (Keeling) Islands (Australia) */ + COUNTRY_CHPLAN_ENT("CD", 0x3A, 0x00, DEF , 1, 1), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x3A, 0x00, DEF , 1, 1), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x3A, 0x00, DEF , 1, 1), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x5E, 0x00, DEF , 1, 1), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x42, 0x00, DEF , 1, 1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CK", 0x5E, 0x00, DEF , 1, 1), /* Cook Islands */ + COUNTRY_CHPLAN_ENT("CL", 0x76, 0x00, CHILE , 1, 1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x5E, 0x00, DEF , 1, 1), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x06, 0x00, CN , 1, 1), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x76, 0x00, DEF , 1, 1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x76, 0x00, DEF , 1, 1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x5E, 0x00, DEF , 1, 1), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CX", 0x03, 0x00, DEF , 1, 1), /* Christmas Island (Australia) */ + COUNTRY_CHPLAN_ENT("CY", 0x5E, 0x00, DEF , 1, 1), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x5E, 0x00, DEF , 1, 1), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x5E, 0x00, DEF , 1, 1), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x3A, 0x00, DEF , 1, 1), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x5E, 0x00, DEF , 1, 1), /* Denmark */ + COUNTRY_CHPLAN_ENT("DM", 0x76, 0x00, DEF , 1, 1), /* Dominica */ + COUNTRY_CHPLAN_ENT("DO", 0x76, 0x00, DEF , 1, 1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x00, 0x00, DEF , 1, 1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x76, 0x00, DEF , 1, 1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x5E, 0x00, DEF , 1, 1), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x3C, 0x00, DEF , 1, 1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x3C, 0x00, DEF , 1, 1), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("ER", 0x3A, 0x00, DEF , 1, 1), /* Eritrea */ + COUNTRY_CHPLAN_ENT("ES", 0x5E, 0x00, DEF , 1, 1), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x3A, 0x00, DEF , 1, 1), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x5E, 0x00, DEF , 1, 1), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x76, 0x00, DEF , 1, 1), /* Fiji */ + COUNTRY_CHPLAN_ENT("FK", 0x3A, 0x00, DEF , 1, 1), /* Falkland Islands (Islas Malvinas) (UK) */ + COUNTRY_CHPLAN_ENT("FM", 0x76, 0x00, DEF , 1, 1), /* Micronesia, Federated States of (USA) */ + COUNTRY_CHPLAN_ENT("FO", 0x3A, 0x00, DEF , 1, 1), /* Faroe Islands (Denmark) */ + COUNTRY_CHPLAN_ENT("FR", 0x5E, 0x00, DEF , 1, 1), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x5E, 0x00, DEF , 1, 1), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x5E, 0x00, DEF , 1, 1), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("GD", 0x76, 0x00, DEF , 1, 1), /* Grenada */ + COUNTRY_CHPLAN_ENT("GE", 0x5E, 0x00, DEF , 1, 1), /* Georgia */ + COUNTRY_CHPLAN_ENT("GF", 0x3A, 0x00, DEF , 1, 1), /* French Guiana */ + COUNTRY_CHPLAN_ENT("GG", 0x5E, 0x00, DEF , 1, 1), /* Guernsey (UK) */ + COUNTRY_CHPLAN_ENT("GH", 0x5E, 0x00, DEF , 1, 1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x3A, 0x00, DEF , 1, 1), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x5E, 0x00, DEF , 1, 1), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x3A, 0x00, DEF , 1, 1), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x3A, 0x00, DEF , 1, 1), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x3A, 0x00, DEF , 1, 1), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x5E, 0x00, DEF , 1, 1), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x5E, 0x00, DEF , 1, 1), /* Greece */ + COUNTRY_CHPLAN_ENT("GS", 0x3A, 0x00, DEF , 1, 1), /* South Georgia and the Sandwich Islands (UK) */ + COUNTRY_CHPLAN_ENT("GT", 0x76, 0x00, DEF , 1, 1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x76, 0x00, DEF , 1, 1), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x3A, 0x00, DEF , 1, 1), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GY", 0x44, 0x00, DEF , 1, 1), /* Guyana */ + COUNTRY_CHPLAN_ENT("HK", 0x5E, 0x00, DEF , 1, 1), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HM", 0x03, 0x00, DEF , 1, 1), /* Heard and McDonald Islands (Australia) */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 0x00, DEF , 1, 1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x5E, 0x00, DEF , 1, 1), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x76, 0x00, DEF , 0, 1), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x5E, 0x00, DEF , 1, 1), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x5D, 0x00, DEF , 1, 1), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x5E, 0x00, DEF , 1, 1), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x5E, 0x00, DEF , 1, 1), /* Israel */ + COUNTRY_CHPLAN_ENT("IM", 0x3A, 0x00, DEF , 1, 1), /* Isle of Man (UK) */ + COUNTRY_CHPLAN_ENT("IN", 0x06, 0x00, DEF , 1, 1), /* India */ + COUNTRY_CHPLAN_ENT("IO", 0x3A, 0x00, DEF , 1, 1), /* British Indian Ocean Territory (UK) */ + COUNTRY_CHPLAN_ENT("IQ", 0x05, 0x00, DEF , 1, 1), /* Iraq */ + COUNTRY_CHPLAN_ENT("IR", 0x3A, 0x00, DEF , 0, 0), /* Iran */ + COUNTRY_CHPLAN_ENT("IS", 0x5E, 0x00, DEF , 1, 1), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x5E, 0x00, DEF , 1, 1), /* Italy */ + COUNTRY_CHPLAN_ENT("JE", 0x3A, 0x00, DEF , 1, 1), /* Jersey (UK) */ + COUNTRY_CHPLAN_ENT("JM", 0x76, 0x00, DEF , 1, 1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x05, 0x00, DEF , 1, 1), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x7D, 0x00, DEF , 1, 1), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x5E, 0x00, DEF , 1, 1), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x5E, 0x00, DEF , 1, 1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x5E, 0x00, DEF , 1, 1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("KI", 0x5E, 0x00, DEF , 1, 1), /* Kiribati */ + COUNTRY_CHPLAN_ENT("KM", 0x3A, 0x00, DEF , 1, 1), /* Comoros */ + COUNTRY_CHPLAN_ENT("KN", 0x76, 0x00, DEF , 1, 1), /* Saint Kitts and Nevis */ + COUNTRY_CHPLAN_ENT("KR", 0x4B, 0x00, DEF , 1, 1), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x5E, 0x00, DEF , 1, 1), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KY", 0x76, 0x00, DEF , 1, 1), /* Cayman Islands (UK) */ + COUNTRY_CHPLAN_ENT("KZ", 0x5E, 0x00, DEF , 1, 1), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("LA", 0x5E, 0x00, DEF , 1, 1), /* Laos */ + COUNTRY_CHPLAN_ENT("LB", 0x5E, 0x00, DEF , 1, 1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LC", 0x76, 0x00, DEF , 1, 1), /* Saint Lucia */ + COUNTRY_CHPLAN_ENT("LI", 0x5E, 0x00, DEF , 1, 1), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x5E, 0x00, DEF , 1, 1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x5E, 0x00, DEF , 1, 1), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x5E, 0x00, DEF , 1, 1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x5E, 0x00, DEF , 1, 1), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x5E, 0x00, DEF , 1, 1), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x5E, 0x00, DEF , 1, 1), /* Latvia */ + COUNTRY_CHPLAN_ENT("LY", 0x5E, 0x00, DEF , 1, 1), /* Libya */ + COUNTRY_CHPLAN_ENT("MA", 0x3C, 0x00, DEF , 1, 1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x5E, 0x00, DEF , 1, 1), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x5E, 0x00, DEF , 1, 1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x3A, 0x00, DEF , 1, 1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MF", 0x76, 0x00, DEF , 1, 1), /* Saint Martin */ + COUNTRY_CHPLAN_ENT("MG", 0x5E, 0x00, DEF , 1, 1), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MH", 0x76, 0x00, DEF , 1, 1), /* Marshall Islands (USA) */ + COUNTRY_CHPLAN_ENT("MK", 0x3A, 0x00, DEF , 1, 1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x5E, 0x00, DEF , 1, 1), /* Mali */ + COUNTRY_CHPLAN_ENT("MM", 0x3A, 0x00, DEF , 1, 1), /* Burma (Myanmar) */ + COUNTRY_CHPLAN_ENT("MN", 0x5E, 0x00, DEF , 1, 1), /* Mongolia */ + COUNTRY_CHPLAN_ENT("MO", 0x5E, 0x00, DEF , 1, 1), /* Macau */ + COUNTRY_CHPLAN_ENT("MP", 0x76, 0x00, DEF , 1, 1), /* Northern Mariana Islands (USA) */ + COUNTRY_CHPLAN_ENT("MQ", 0x3A, 0x00, DEF , 1, 1), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x5E, 0x00, DEF , 1, 1), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MS", 0x3A, 0x00, DEF , 1, 1), /* Montserrat (UK) */ + COUNTRY_CHPLAN_ENT("MT", 0x5E, 0x00, DEF , 1, 1), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x5E, 0x00, DEF , 1, 1), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MV", 0x3C, 0x00, DEF , 1, 1), /* Maldives */ + COUNTRY_CHPLAN_ENT("MW", 0x5E, 0x00, DEF , 1, 1), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x4D, 0x00, DEF , 1, 1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x07, 0x00, DEF , 1, 1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x5E, 0x00, DEF , 1, 1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x5E, 0x00, DEF , 1, 1), /* Namibia */ + COUNTRY_CHPLAN_ENT("NC", 0x3A, 0x00, DEF , 1, 1), /* New Caledonia */ + COUNTRY_CHPLAN_ENT("NE", 0x5E, 0x00, DEF , 1, 1), /* Niger */ + COUNTRY_CHPLAN_ENT("NF", 0x03, 0x00, DEF , 1, 1), /* Norfolk Island (Australia) */ + COUNTRY_CHPLAN_ENT("NG", 0x75, 0x00, DEF , 1, 1), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x76, 0x00, DEF , 1, 1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x5E, 0x00, DEF , 1, 1), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x5E, 0x00, DEF , 1, 1), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x06, 0x00, DEF , 1, 1), /* Nepal */ + COUNTRY_CHPLAN_ENT("NR", 0x3A, 0x00, DEF , 1, 1), /* Nauru */ + COUNTRY_CHPLAN_ENT("NU", 0x03, 0x00, DEF , 1, 1), /* Niue */ + COUNTRY_CHPLAN_ENT("NZ", 0x03, 0x00, DEF , 1, 1), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x5E, 0x00, DEF , 1, 1), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x76, 0x00, DEF , 1, 1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x76, 0x00, DEF , 1, 1), /* Peru */ + COUNTRY_CHPLAN_ENT("PF", 0x3A, 0x00, DEF , 1, 1), /* French Polynesia (France) */ + COUNTRY_CHPLAN_ENT("PG", 0x5E, 0x00, DEF , 1, 1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x5E, 0x00, DEF , 1, 1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 0x00, DEF , 1, 1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x5E, 0x00, DEF , 1, 1), /* Poland */ + COUNTRY_CHPLAN_ENT("PM", 0x3A, 0x00, DEF , 1, 1), /* Saint Pierre and Miquelon (France) */ + COUNTRY_CHPLAN_ENT("PR", 0x76, 0x00, DEF , 1, 1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PS", 0x5E, 0x00, DEF , 1, 1), /* Palestine */ + COUNTRY_CHPLAN_ENT("PT", 0x5E, 0x00, DEF , 1, 1), /* Portugal */ + COUNTRY_CHPLAN_ENT("PW", 0x76, 0x00, DEF , 1, 1), /* Palau */ + COUNTRY_CHPLAN_ENT("PY", 0x76, 0x00, DEF , 1, 1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x5E, 0x00, QATAR , 1, 1), /* Qatar */ + COUNTRY_CHPLAN_ENT("RE", 0x3A, 0x00, DEF , 1, 1), /* Reunion (France) */ + COUNTRY_CHPLAN_ENT("RO", 0x5E, 0x00, DEF , 1, 1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x5E, 0x00, DEF , 1, 1), /* Serbia */ + COUNTRY_CHPLAN_ENT("RU", 0x09, 0x00, DEF , 1, 1), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x5E, 0x00, DEF , 1, 1), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x5E, 0x00, DEF , 1, 1), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("SB", 0x3A, 0x00, DEF , 1, 1), /* Solomon Islands */ + COUNTRY_CHPLAN_ENT("SC", 0x76, 0x00, DEF , 1, 1), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x5E, 0x00, DEF , 1, 1), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x5E, 0x00, DEF , 1, 1), /* Singapore */ + COUNTRY_CHPLAN_ENT("SH", 0x3A, 0x00, DEF , 1, 1), /* Saint Helena (UK) */ + COUNTRY_CHPLAN_ENT("SI", 0x5E, 0x00, DEF , 1, 1), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SJ", 0x3A, 0x00, DEF , 1, 1), /* Svalbard (Norway) */ + COUNTRY_CHPLAN_ENT("SK", 0x5E, 0x00, DEF , 1, 1), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x5E, 0x00, DEF , 1, 1), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SM", 0x3A, 0x00, DEF , 1, 1), /* San Marino */ + COUNTRY_CHPLAN_ENT("SN", 0x3A, 0x00, DEF , 1, 1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SO", 0x3A, 0x00, DEF , 1, 1), /* Somalia */ + COUNTRY_CHPLAN_ENT("SR", 0x74, 0x00, DEF , 1, 1), /* Suriname */ + COUNTRY_CHPLAN_ENT("ST", 0x76, 0x00, DEF , 1, 1), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x76, 0x00, DEF , 1, 1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("SX", 0x76, 0x00, DEF , 1, 1), /* Sint Marteen */ + COUNTRY_CHPLAN_ENT("SZ", 0x5E, 0x00, DEF , 1, 1), /* Swaziland */ + COUNTRY_CHPLAN_ENT("TC", 0x3A, 0x00, DEF , 1, 1), /* Turks and Caicos Islands (UK) */ + COUNTRY_CHPLAN_ENT("TD", 0x3A, 0x00, DEF , 1, 1), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x3A, 0x00, DEF , 1, 1), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x5E, 0x00, DEF , 1, 1), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x5E, 0x00, DEF , 1, 1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x5E, 0x00, DEF , 1, 1), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TK", 0x03, 0x00, DEF , 1, 1), /* Tokelau */ + COUNTRY_CHPLAN_ENT("TM", 0x3A, 0x00, DEF , 1, 1), /* Turkmenistan */ + COUNTRY_CHPLAN_ENT("TN", 0x04, 0x00, DEF , 1, 1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TO", 0x3A, 0x00, DEF , 1, 1), /* Tonga */ + COUNTRY_CHPLAN_ENT("TR", 0x5E, 0x00, DEF , 1, 1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TT", 0x76, 0x00, DEF , 1, 1), /* Trinidad & Tobago */ + COUNTRY_CHPLAN_ENT("TV", 0x21, 0x00, DEF , 0, 0), /* Tuvalu */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 0x00, DEF , 1, 1), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x5E, 0x00, DEF , 1, 1), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x5E, 0x00, UKRAINE, 1, 1), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x3A, 0x00, DEF , 1, 1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x76, 0x7F, DEF , 1, 1), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x30, 0x00, DEF , 1, 1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x3C, 0x00, DEF , 1, 1), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("VA", 0x3A, 0x00, DEF , 1, 1), /* Holy See (Vatican City) */ + COUNTRY_CHPLAN_ENT("VC", 0x76, 0x00, DEF , 1, 1), /* Saint Vincent and the Grenadines */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 0x00, DEF , 1, 1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VG", 0x76, 0x00, DEF , 1, 1), /* British Virgin Islands (UK) */ + COUNTRY_CHPLAN_ENT("VI", 0x76, 0x00, DEF , 1, 1), /* United States Virgin Islands (USA) */ + COUNTRY_CHPLAN_ENT("VN", 0x5E, 0x00, DEF , 1, 1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VU", 0x26, 0x00, DEF , 1, 1), /* Vanuatu */ + COUNTRY_CHPLAN_ENT("WF", 0x3A, 0x00, DEF , 1, 1), /* Wallis and Futuna (France) */ + COUNTRY_CHPLAN_ENT("WS", 0x76, 0x00, DEF , 1, 1), /* Samoa */ + COUNTRY_CHPLAN_ENT("XK", 0x3A, 0x00, DEF , 1, 1), /* Kosovo */ + COUNTRY_CHPLAN_ENT("YE", 0x3A, 0x00, DEF , 1, 1), /* Yemen */ + COUNTRY_CHPLAN_ENT("YT", 0x5E, 0x00, DEF , 1, 1), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x5E, 0x00, DEF , 1, 1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x5E, 0x00, DEF , 1, 1), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x5E, 0x00, DEF , 1, 1), /* Zimbabwe */ }; #endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT or newest */ +/* +* rtw_get_chplan_worldwide - +* @ent: the buf to copy country_chplan entry content +*/ +void rtw_get_chplan_worldwide(struct country_chplan *ent) +{ + _rtw_memcpy(ent, &world_wide_chplan, sizeof(*ent)); +} + /* * rtw_get_chplan_from_country - * @country_code: string of country code +* @ent: the buf to copy country_chplan entry content * -* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given +* Return _TRUE or _FALSE when unsupported country_code is given */ -const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +bool rtw_get_chplan_from_country(const char *country_code, struct country_chplan *ent) { - const struct country_chplan *ent = NULL; +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + struct country_chplan phl_ent = {.alpha2 = "\0\0"}; +#endif const struct country_chplan *map = NULL; u16 map_sz = 0; char code[2]; @@ -2386,38 +3178,315 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod #elif RTW_DEF_MODULE_REGULATORY_CERT map_sz = rtw_def_module_country_chplan_map(&map); #else + #if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD +{ + struct rtw_regulation_country_chplan plan; + + _rtw_memset(&plan, 0, sizeof(plan)); + if (rtw_phl_query_country_chplan(code, &plan)) { + _rtw_memcpy(phl_ent.alpha2, code, 2); + phl_ent.chplan = plan.domain_code; + #if CONFIG_IEEE80211_BAND_6GHZ + phl_ent.chplan_6g = RTW_CHPLAN_6G_NULL; /* TODO: get from PHL */ + #endif + phl_ent.edcca_mode_2g_override = RTW_EDCCA_DEF; + #if CONFIG_IEEE80211_BAND_5GHZ + phl_ent.edcca_mode_5g_override = RTW_EDCCA_DEF; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + phl_ent.edcca_mode_6g_override = RTW_EDCCA_DEF; + #endif + phl_ent.txpwr_lmt_override = phl_tpo_to_txpwr_lmt(plan.tpo); + #if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + phl_ent.proto_en = 0 + | ((plan.support_mode & SUPPORT_11AC) ? CHPLAN_PROTO_EN_AC : 0) + | ((plan.support_mode & SUPPORT_11AX) ? CHPLAN_PROTO_EN_AX : 0) + ; + #endif + map = &phl_ent; + map_sz = 1; + } +} + #else map = country_chplan_map; map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); + #endif #endif for (i = 0; i < map_sz; i++) { if (strncmp(code, map[i].alpha2, 2) == 0) { - ent = &map[i]; - break; + if (ent) + _rtw_memcpy(ent, &map[i], sizeof(*ent)); + return _TRUE; } } - return ent; + return _FALSE; +} + +void rtw_chplan_ioctl_input_mapping(u16 *chplan, u16 *chplan_6g) +{ + if (chplan) { + if (*chplan == RTW_CHPLAN_IOCTL_UNSPECIFIED) + *chplan = RTW_CHPLAN_UNSPECIFIED; + else if (*chplan == RTW_CHPLAN_IOCTL_NULL) + *chplan = RTW_CHPLAN_NULL; + } + + if (chplan_6g) { + if (*chplan_6g == RTW_CHPLAN_IOCTL_UNSPECIFIED) + *chplan_6g = RTW_CHPLAN_6G_UNSPECIFIED; + else if (*chplan_6g == RTW_CHPLAN_IOCTL_NULL) + *chplan_6g = RTW_CHPLAN_6G_NULL; + } +} + +bool rtw_chplan_ids_is_world_wide(u8 chplan, u8 chplan_6g) +{ + return !(chplan == RTW_CHPLAN_NULL + #if CONFIG_IEEE80211_BAND_6GHZ + && chplan_6g == RTW_CHPLAN_6G_NULL + #endif + ) + && (chplan == RTW_CHPLAN_WORLDWIDE || chplan == RTW_CHPLAN_NULL) + #if CONFIG_IEEE80211_BAND_6GHZ + && (chplan_6g == RTW_CHPLAN_6G_WORLDWIDE || chplan_6g == RTW_CHPLAN_6G_NULL) + #endif + ; +} + +/* + * Check if the @param ch, bw, offset is valid for the given @param ent + * @ch_set: the given channel set + * @ch: the given channel number + * @bw: the given bandwidth + * @offset: the given channel offset + * + * return valid (1) or not (0) + */ +u8 rtw_country_chplan_is_chbw_valid(struct country_chplan *ent, enum band_type band, u8 ch, u8 bw, u8 offset + , bool allow_primary_passive, bool allow_passive, struct registry_priv *regsty) +{ + u8 chplan_6g = RTW_CHPLAN_6G_NULL; + u8 valid = 0; + + if (bw >= CHANNEL_WIDTH_80 && !COUNTRY_CHPLAN_EN_11AC(ent)) + goto exit; + + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = ent->chplan_6g; + #endif + + valid = rtw_chplan_is_chbw_valid(ent->chplan, chplan_6g, band, ch, bw, offset + , allow_primary_passive, allow_passive, regsty); + +exit: + return valid; +} + +static void rtw_country_chplan_get_edcca_modes(const struct country_chplan *ent, u8 modes[]) +{ + modes[BAND_ON_24G] = + ent->edcca_mode_2g_override != RTW_EDCCA_DEF ? ent->edcca_mode_2g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_2g(ent->chplan)); + #if CONFIG_IEEE80211_BAND_5GHZ + modes[BAND_ON_5G] = + ent->edcca_mode_5g_override != RTW_EDCCA_DEF ? ent->edcca_mode_5g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_5g(ent->chplan)); + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + modes[BAND_ON_6G] = + ent->edcca_mode_6g_override != RTW_EDCCA_DEF ? ent->edcca_mode_6g_override : + rtw_regd_to_edcca_mode(rtw_chplan_get_default_regd_6g(ent->chplan_6g)); + #endif +} + +static void rtw_country_chplan_get_txpwr_lmts(const struct country_chplan *ent, u8 txpwr_lmt[]) +{ + txpwr_lmt[BAND_ON_24G] = + ent->txpwr_lmt_override != TXPWR_LMT_DEF ? ent->txpwr_lmt_override : + rtw_regd_to_txpwr_lmt(rtw_chplan_get_default_regd_2g(ent->chplan)); + #if CONFIG_IEEE80211_BAND_5GHZ + txpwr_lmt[BAND_ON_5G] = + ent->txpwr_lmt_override != TXPWR_LMT_DEF ? ent->txpwr_lmt_override : + rtw_regd_to_txpwr_lmt(rtw_chplan_get_default_regd_5g(ent->chplan)); + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + txpwr_lmt[BAND_ON_6G] = + ent->txpwr_lmt_override != TXPWR_LMT_DEF ? ent->txpwr_lmt_override : + rtw_regd_to_txpwr_lmt(rtw_chplan_get_default_regd_6g(ent->chplan_6g)); + #endif +} + +#ifdef CONFIG_80211D +const char *const _cis_status_str[] = { + [COUNTRY_IE_SLAVE_NOCOUNTRY] = "NOCOUNTRY", + [COUNTRY_IE_SLAVE_UNKNOWN] = "UNKNOWN", + [COUNTRY_IE_SLAVE_OPCH_NOEXIST] = "OPCH_NOEXIST", + [COUNTRY_IE_SLAVE_APPLICABLE] = "APPLICABLE", + [COUNTRY_IE_SLAVE_STATUS_NUM] = "INVALID", +}; + +void dump_country_ie_slave_records(void *sel, struct rf_ctl_t *rfctl, bool skip_noset) +{ + int i; + + RTW_PRINT_SEL(sel, " %-6s %-4s %-4s %s\n", "alpha2", "band", "opch", "status"); + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (skip_noset && strncmp(rfctl->cisr[i].alpha2, "\x00\x00", 2) == 0) + continue; + RTW_PRINT_SEL(sel, "%c%d "ALPHA2_FMT" %4s %4u %s\n" + , i == rfctl->effected_cisr_id ? '*' : ' ', i, ALPHA2_ARG(rfctl->cisr[i].alpha2) + , band_str(rfctl->cisr[i].band), rfctl->cisr[i].opch, cis_status_str(rfctl->cisr[i].status)); + } } -void dump_country_chplan(void *sel, const struct country_chplan *ent) +enum country_ie_slave_status rtw_get_chplan_from_recv_country_ie(_adapter *adapter + , enum band_type band, u8 opch, const u8 *country_ie, struct country_chplan *ent + , struct country_ie_slave_record *cisr, const char *caller_msg) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + const char *country_code = country_ie ? country_ie + 2 : NULL; + u8 chplan_6g = RTW_CHPLAN_6G_NULL; + enum country_ie_slave_status ret; + + _rtw_memset(ent, 0, sizeof(*ent)); + + if (!country_code || strncmp(country_code, "XX", 2) == 0) { + if (caller_msg && country_code) + RTW_INFO("%s("ADPT_FMT") noncountry \"XX\"\n", caller_msg, ADPT_ARG(adapter)); + ret = COUNTRY_IE_SLAVE_NOCOUNTRY; + goto exit; + } + + if (!rtw_get_chplan_from_country(country_code, ent)) { + if (caller_msg) { + if (is_alpha(country_code[0]) == _FALSE || is_alpha(country_code[1]) == _FALSE) { + RTW_INFO("%s("ADPT_FMT") country_code is not alpha2, use world wide instead\n" + , caller_msg, ADPT_ARG(adapter)); + } else { + RTW_INFO("%s("ADPT_FMT") unsupported country_code:\"%c%c\", use world wide\n" + , caller_msg, ADPT_ARG(adapter), country_code[0], country_code[1]); + } + } + rtw_get_chplan_worldwide(ent); + ret = COUNTRY_IE_SLAVE_UNKNOWN; + goto exit; + } + + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = ent->chplan_6g; + #endif + + if (!rtw_chplan_is_chbw_valid(ent->chplan, chplan_6g, band, opch + , CHANNEL_WIDTH_20, CHAN_OFFSET_NO_EXT, 1, 1, regsty) + ) { + u8 edcca_modes[BAND_MAX]; + + if (caller_msg) { + RTW_INFO("%s("ADPT_FMT") \"%c%c\" no band:%s ch:%u, use world wide with ori edcca modes\n" + , caller_msg, ADPT_ARG(adapter), country_code[0], country_code[1], band_str(band), opch); + } + rtw_country_chplan_get_edcca_modes(ent, edcca_modes); + rtw_get_chplan_worldwide(ent); + ent->edcca_mode_2g_override = edcca_modes[BAND_ON_24G]; + #if CONFIG_IEEE80211_BAND_5GHZ + ent->edcca_mode_5g_override = edcca_modes[BAND_ON_5G]; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + ent->edcca_mode_6g_override = edcca_modes[BAND_ON_6G]; + #endif + ret = COUNTRY_IE_SLAVE_OPCH_NOEXIST; + goto exit; + } + + if (caller_msg) { + RTW_INFO("%s("ADPT_FMT") country_code:\"%c%c\" is applicapble\n" + , caller_msg, ADPT_ARG(adapter), country_code[0], country_code[1]); + } + ret = COUNTRY_IE_SLAVE_APPLICABLE; + +exit: + if (cisr) { + _rtw_memcpy(cisr->alpha2, country_code ? country_code : "\x00\x00", 2); + cisr->band = band; + cisr->opch = opch; + cisr->status = ret; + } + + return ret; +} + +enum country_ie_slave_status rtw_get_chplan_from_cisrs(struct rf_ctl_t *rfctl + , struct country_chplan *ent, const char *caller_msg) +{ + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + _adapter *adapter = dvobj->padapters[rfctl->effected_cisr_id]; + struct country_ie_slave_record *cisr = &rfctl->cisr[rfctl->effected_cisr_id]; + const u8 country_ie[4] = {WLAN_EID_COUNTRY, 2, cisr->alpha2[0], cisr->alpha2[1]}; + enum country_ie_slave_status status; + + status = rtw_get_chplan_from_recv_country_ie(adapter, cisr->band, cisr->opch, country_ie, ent, NULL, caller_msg); + rtw_warn_on(cisr->status != status); + + return status; +} +#endif /* CONFIG_80211D */ + +void dump_country_chplan(void *sel, const struct country_chplan *ent, bool regd_info) { char buf[16]; + char *pos = buf; if (ent->chplan == RTW_CHPLAN_UNSPECIFIED) - sprintf(buf, "NA"); + pos += sprintf(pos, "NA"); + else + pos += sprintf(pos, "0x%02X", ent->chplan); + +#if CONFIG_IEEE80211_BAND_6GHZ + if (ent->chplan_6g == RTW_CHPLAN_6G_UNSPECIFIED) + pos += sprintf(pos, " NA"); else - sprintf(buf, "0x%02X", ent->chplan); + pos += sprintf(pos, " 0x%02X", ent->chplan_6g); +#endif + + RTW_PRINT_SEL(sel, "\"%c%c\", %s" + , ent->alpha2[0], ent->alpha2[1], buf); + + if (regd_info) { + u8 edcca_modes[BAND_MAX]; + u8 txpwr_lmts[BAND_MAX]; + + rtw_country_chplan_get_edcca_modes(ent, edcca_modes); + _RTW_PRINT_SEL(sel, " {%-6s", rtw_edcca_mode_str(edcca_modes[BAND_ON_24G])); + #if CONFIG_IEEE80211_BAND_5GHZ + _RTW_PRINT_SEL(sel, " %-6s", rtw_edcca_mode_str(edcca_modes[BAND_ON_5G])); + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + _RTW_PRINT_SEL(sel, " %-6s", rtw_edcca_mode_str(edcca_modes[BAND_ON_6G])); + #endif + _RTW_PRINT_SEL(sel, "}"); - RTW_PRINT_SEL(sel, "\"%c%c\", %s%s\n" - , ent->alpha2[0], ent->alpha2[1], buf - , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" - ); + rtw_country_chplan_get_txpwr_lmts(ent, txpwr_lmts); + _RTW_PRINT_SEL(sel, " {%-7s", txpwr_lmt_str(txpwr_lmts[BAND_ON_24G])); + #if CONFIG_IEEE80211_BAND_5GHZ + _RTW_PRINT_SEL(sel, " %-7s", txpwr_lmt_str(txpwr_lmts[BAND_ON_5G])); + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + _RTW_PRINT_SEL(sel, " %-7s", txpwr_lmt_str(txpwr_lmts[BAND_ON_6G])); + #endif + _RTW_PRINT_SEL(sel, "}"); + } + + _RTW_PRINT_SEL(sel, " %s", COUNTRY_CHPLAN_EN_11AX(ent) ? "ax" : " "); + _RTW_PRINT_SEL(sel, " %s", COUNTRY_CHPLAN_EN_11AC(ent) ? "ac" : " "); + + _RTW_PRINT_SEL(sel, "\n"); } -void dump_country_chplan_map(void *sel) +void dump_country_chplan_map(void *sel, bool regd_info) { - const struct country_chplan *ent; + struct country_chplan ent; u8 code[2]; #if RTW_DEF_MODULE_REGULATORY_CERT @@ -2427,23 +3496,47 @@ void dump_country_chplan_map(void *sel) RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); #endif + rtw_get_chplan_worldwide(&ent); + dump_country_chplan(sel, &ent, regd_info); + + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + if (rtw_get_chplan_from_country(code, &ent) == _FALSE) + continue; + + dump_country_chplan(sel, &ent, regd_info); + } + } +} + +void dump_country_list(void *sel) +{ + u8 code[2]; + + RTW_PRINT_SEL(sel, "%s ", WORLDWIDE_ALPHA2); + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { - ent = rtw_get_chplan_from_country(code); - if (!ent) + if (!rtw_get_chplan_from_country(code, NULL)) continue; - dump_country_chplan(sel, ent); + _RTW_PRINT_SEL(sel, "%c%c ", code[0], code[1]); } } + _RTW_PRINT_SEL(sel, "\n"); } void dump_chplan_id_list(void *sel) { +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + u8 id_search_max = 255; +#else + u8 id_search_max = RTW_ChannelPlanMap_size - 1; +#endif u8 first = 1; int i; - for (i = 0; i < RTW_ChannelPlanMap_size; i++) { + for (i = 0; i <= id_search_max; i++) { if (!rtw_is_channel_plan_valid(i)) continue; @@ -2453,24 +3546,124 @@ void dump_chplan_id_list(void *sel) } else _RTW_PRINT_SEL(sel, "0x%02X ", i); } + if (first == 0) + _RTW_PRINT_SEL(sel, "\n"); } +void dump_chplan_country_list(void *sel) +{ +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + u8 id_search_max = 255; +#else + u8 id_search_max = RTW_ChannelPlanMap_size - 1; +#endif + int i; + + for (i = 0; i <= id_search_max; i++) { + struct country_chplan ent; + u8 code[2]; + u8 first; + + if (!rtw_is_channel_plan_valid(i)) + continue; + + first = 1; + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + if (!rtw_get_chplan_from_country(code, &ent) || ent.chplan != i) + continue; + + if (first) { + RTW_PRINT_SEL(sel, "0x%02X %c%c ", i, code[0], code[1]); + first = 0; + } else + _RTW_PRINT_SEL(sel, "%c%c ", code[0], code[1]); + } + } + if (first == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +} + +#if CONFIG_IEEE80211_BAND_6GHZ +void dump_chplan_6g_id_list(void *sel) +{ +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + u8 id_search_max = 255; +#else + u8 id_search_max = rtw_chplan_6g_map_size - 1; +#endif + u8 first = 1; + int i; + + for (i = 0; i <= id_search_max; i++) { + if (!rtw_is_channel_plan_6g_valid(i)) + continue; + + if (first) { + RTW_PRINT_SEL(sel, "0x%02X ", i); + first = 0; + } else + _RTW_PRINT_SEL(sel, "0x%02X ", i); + } + if (first == 0) + _RTW_PRINT_SEL(sel, "\n"); +} + +void dump_chplan_6g_country_list(void *sel) +{ +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + u8 id_search_max = 255; +#else + u8 id_search_max = rtw_chplan_6g_map_size - 1; +#endif + int i; + + for (i = 0; i <= id_search_max; i++) { + struct country_chplan ent; + u8 code[2]; + u8 first; + + if (!rtw_is_channel_plan_6g_valid(i)) + continue; + + first = 1; + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + if (!rtw_get_chplan_from_country(code, &ent) || ent.chplan_6g != i) + continue; + + if (first) { + RTW_PRINT_SEL(sel, "0x%02X %c%c ", i, code[0], code[1]); + first = 0; + } else + _RTW_PRINT_SEL(sel, "%c%c ", code[0], code[1]); + } + } + if (first == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +} +#endif /* CONFIG_IEEE80211_BAND_6GHZ */ + #ifdef CONFIG_RTW_DEBUG void dump_chplan_test(void *sel) { +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD +#else int i, j; - /* check redundent */ - for (i = 0; i < RTW_CHD_2G_MAX; i++) { - for (j = 0; j < i; j++) { + /* check 2G CHD redundent */ + for (i = RTW_CHD_2G_00; i < RTW_CHD_2G_MAX; i++) { + for (j = RTW_CHD_2G_00; j < i; j++) { if (CH_LIST_LEN(rtw_channel_def_2g[i]) == CH_LIST_LEN(rtw_channel_def_2g[j]) && _rtw_memcmp(&CH_LIST_CH(rtw_channel_def_2g[i], 0), &CH_LIST_CH(rtw_channel_def_2g[j], 0), CH_LIST_LEN(rtw_channel_def_2g[i]) + 1) == _TRUE) RTW_PRINT_SEL(sel, "2G chd:%u and %u is the same\n", i, j); } } - /* check invalid channel */ - for (i = 0; i < RTW_CHD_2G_MAX; i++) { + /* check 2G CHD invalid channel */ + for (i = RTW_CHD_2G_00; i < RTW_CHD_2G_MAX; i++) { for (j = 0; j < CH_LIST_LEN(rtw_channel_def_2g[i]); j++) { if (rtw_ch2freq(CH_LIST_CH(rtw_channel_def_2g[i], j)) == 0) RTW_PRINT_SEL(sel, "2G invalid ch:%u at (%d,%d)\n", CH_LIST_CH(rtw_channel_def_2g[i], j), i, j); @@ -2478,17 +3671,17 @@ void dump_chplan_test(void *sel) } #if CONFIG_IEEE80211_BAND_5GHZ - /* check redundent */ - for (i = 0; i < RTW_CHD_5G_MAX; i++) { - for (j = 0; j < i; j++) { + /* check 5G CHD redundent */ + for (i = RTW_CHD_5G_00; i < RTW_CHD_5G_MAX; i++) { + for (j = RTW_CHD_5G_00; j < i; j++) { if (CH_LIST_LEN(rtw_channel_def_5g[i]) == CH_LIST_LEN(rtw_channel_def_5g[j]) && _rtw_memcmp(&CH_LIST_CH(rtw_channel_def_5g[i], 0), &CH_LIST_CH(rtw_channel_def_5g[j], 0), CH_LIST_LEN(rtw_channel_def_5g[i]) + 1) == _TRUE) RTW_PRINT_SEL(sel, "5G chd:%u and %u is the same\n", i, j); } } - /* check invalid channel */ - for (i = 0; i < RTW_CHD_5G_MAX; i++) { + /* check 5G CHD invalid channel */ + for (i = RTW_CHD_5G_00; i < RTW_CHD_5G_MAX; i++) { for (j = 0; j < CH_LIST_LEN(rtw_channel_def_5g[i]); j++) { if (rtw_ch2freq(CH_LIST_CH(rtw_channel_def_5g[i], j)) == 0) RTW_PRINT_SEL(sel, "5G invalid ch:%u at (%d,%d)\n", CH_LIST_CH(rtw_channel_def_5g[i], j), i, j); @@ -2496,7 +3689,26 @@ void dump_chplan_test(void *sel) } #endif - /* check redundent */ +#if CONFIG_IEEE80211_BAND_6GHZ + /* check 6G CHD redundent */ + for (i = RTW_CHD_6G_00; i < RTW_CHD_6G_MAX; i++) { + for (j = RTW_CHD_6G_00; j < i; j++) { + if (CH_LIST_LEN(rtw_channel_def_6g[i]) == CH_LIST_LEN(rtw_channel_def_6g[j]) + && _rtw_memcmp(&CH_LIST_CH(rtw_channel_def_6g[i], 0), &CH_LIST_CH(rtw_channel_def_6g[j], 0), CH_LIST_LEN(rtw_channel_def_6g[i]) + 1) == _TRUE) + RTW_PRINT_SEL(sel, "6G chd:%u and %u is the same\n", i, j); + } + } + + /* check 6G CHD invalid channel */ + for (i = RTW_CHD_6G_00; i < RTW_CHD_6G_MAX; i++) { + for (j = 0; j < CH_LIST_LEN(rtw_channel_def_6g[i]); j++) { + if (rtw_6gch2freq(CH_LIST_CH(rtw_channel_def_6g[i], j)) == 0) + RTW_PRINT_SEL(sel, "6G invalid ch:%u at (%d,%d)\n", CH_LIST_CH(rtw_channel_def_6g[i], j), i, j); + } + } +#endif + + /* check chplan 2G_5G redundent */ for (i = 0; i < RTW_ChannelPlanMap_size; i++) { if (!rtw_is_channel_plan_valid(i)) continue; @@ -2507,10 +3719,71 @@ void dump_chplan_test(void *sel) RTW_PRINT_SEL(sel, "channel plan 0x%02x and 0x%02x is the same\n", i, j); } } + +#if CONFIG_IEEE80211_BAND_6GHZ + /* check chplan 6G redundent */ + for (i = 0; i < rtw_chplan_6g_map_size; i++) { + if (!rtw_is_channel_plan_6g_valid(i)) + continue; + for (j = 0; j < i; j++) { + if (!rtw_is_channel_plan_6g_valid(j)) + continue; + if (_rtw_memcmp(&rtw_chplan_6g_map[i], &rtw_chplan_6g_map[j], sizeof(rtw_chplan_6g_map[i])) == _TRUE) + RTW_PRINT_SEL(sel, "channel plan 6g 0x%02x and 0x%02x is the same\n", i, j); + } + } +#endif + + + /* check country invalid chplan/chplan_6g */ +{ + struct country_chplan ent; + u8 code[2]; + + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + if (!rtw_get_chplan_from_country(code, &ent)) + continue; + if (!rtw_is_channel_plan_valid(ent.chplan)) + RTW_PRINT_SEL(sel, "country \"%c%c\" has invalid chplan:0x%02X\n", code[0], code[1], ent.chplan); + #if CONFIG_IEEE80211_BAND_6GHZ + if (!rtw_is_channel_plan_6g_valid(ent.chplan_6g)) + RTW_PRINT_SEL(sel, "country \"%c%c\" has invalid chplan_6g:0x%02X\n", code[0], code[1], ent.chplan_6g); + #endif + } + } +} +#endif } #endif /* CONFIG_RTW_DEBUG */ void dump_chplan_ver(void *sel) { +#if defined(PHL_FEATURE_NIC) && !USE_RTW_REGD + struct rtw_regulation_info info = {0}; + + if (!rtw_phl_query_regulation_info(phl_info, &info)) { + RTW_PRINT_SEL(sel, "query chplan version fail\n"); + return; + } + RTW_PRINT_SEL(sel, "%d-%d\n", info.chplan_ver, info.country_ver); +#else RTW_PRINT_SEL(sel, "%s%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_DOMAIN_MAP_M_VER, RTW_COUNTRY_MAP_VER); +#endif +} + +void rtw_set_phl_regulation_ctx(struct dvobj_priv *dvobj) +{ +#ifdef PHL_FEATURE_NIC + if (!phl_info) + phl_info = GET_PHL_INFO(dvobj); +#endif } + +void rtw_clear_phl_regulation_ctx(struct dvobj_priv *dvobj) +{ +#ifdef PHL_FEATURE_NIC + if (phl_info == GET_PHL_INFO(dvobj)) + phl_info = NULL; +#endif +} \ No newline at end of file diff --git a/core/rtw_chplan.h b/core/rtw_chplan.h index bfe1ab2..210db08 100644 --- a/core/rtw_chplan.h +++ b/core/rtw_chplan.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2018 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,13 +15,30 @@ #ifndef __RTW_CHPLAN_H__ #define __RTW_CHPLAN_H__ -#define RTW_CHPLAN_UNSPECIFIED 0xFF +#define RTW_CHPLAN_IOCTL_NULL 0xFFFE /* special value by ioctl: null(empty) chplan */ +#define RTW_CHPLAN_IOCTL_UNSPECIFIED 0xFFFF /* special value by ioctl: no change (keep original) */ -u8 rtw_chplan_get_default_regd(u8 id); -bool rtw_chplan_is_empty(u8 id); +#define RTW_CHPLAN_NULL 0x1A +#define RTW_CHPLAN_WORLDWIDE 0x7F +#define RTW_CHPLAN_UNSPECIFIED 0xFF +#define RTW_CHPLAN_6G_NULL 0x00 +#define RTW_CHPLAN_6G_WORLDWIDE 0x7F +#define RTW_CHPLAN_6G_UNSPECIFIED 0xFF + +u8 rtw_chplan_get_default_regd_2g(u8 id); +u8 rtw_chplan_get_default_regd_5g(u8 id); bool rtw_is_channel_plan_valid(u8 id); bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch); +#if CONFIG_IEEE80211_BAND_6GHZ +u8 rtw_chplan_get_default_regd_6g(u8 id); +bool rtw_is_channel_plan_6g_valid(u8 id); +bool rtw_regsty_is_excl_chs_6g(struct registry_priv *regsty, u8 ch); +#endif + +u8 rtw_chplan_is_chbw_valid(u8 id, u8 id_6g, enum band_type band, u8 ch, u8 bw, u8 offset + , bool allow_primary_passive, bool allow_passive, struct registry_priv *regsty); + enum regd_src_t { REGD_SRC_RTK_PRIV = 0, /* Regulatory settings from Realtek framework (Realtek defined or customized) */ REGD_SRC_OS = 1, /* Regulatory settings from OS */ @@ -38,10 +55,18 @@ u8 init_channel_set(_adapter *adapter); bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo); bool rtw_chset_is_dfs_ch(struct _RT_CHANNEL_INFO *chset, u8 ch); bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offset); +bool rtw_chinfo_allow_beacon_hint(struct _RT_CHANNEL_INFO *chinfo); u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss); -#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) -#define IS_ALPHA2_WORLDWIDE(_alpha2) (strncmp(_alpha2, "00", 2) == 0) +#define ALPHA2_FMT "%c%c" +#define ALPHA2_ARG(a2) ((is_alpha(a2[0]) || is_decimal(a2[0])) ? a2[0] : '-'), ((is_alpha(a2[1]) || is_decimal(a2[1])) ? a2[1] : '-') + +#define WORLDWIDE_ALPHA2 "00" +#define UNSPEC_ALPHA2 "99" + +#define IS_ALPHA2_WORLDWIDE(_alpha2) (strncmp(_alpha2, WORLDWIDE_ALPHA2, 2) == 0) +#define IS_ALPHA2_UNSPEC(_alpha2) (strncmp(_alpha2, UNSPEC_ALPHA2, 2) == 0) +#define SET_UNSPEC_ALPHA2(_alpha2) do { _rtw_memcpy(_alpha2, UNSPEC_ALPHA2, 2); } while (0) #define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ #define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ @@ -54,7 +79,51 @@ u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss); #define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ #define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */ #define RTW_MODULE_RTL8821CE BIT10 /* RTL8821CE */ -#define RTW_MODULE_RTL8822CE BIT11 /* RTL8822CE */ + +enum rtw_regd_inr { + RTW_REGD_SET_BY_INIT = 0, + RTW_REGD_SET_BY_USER = 1, + RTW_REGD_SET_BY_COUNTRY_IE = 2, + + /* below is not used for REGD_SRC_RTK_PRIV */ + RTW_REGD_SET_BY_DRIVER = 3, + RTW_REGD_SET_BY_CORE = 4, + + RTW_REGD_SET_BY_NUM, +}; + +extern const char *const _regd_inr_str[]; +#define regd_inr_str(inr) (((inr) >= RTW_REGD_SET_BY_NUM) ? _regd_inr_str[RTW_REGD_SET_BY_NUM] : _regd_inr_str[(inr)]) + +enum rtw_regd { + RTW_REGD_NA = 0, + RTW_REGD_FCC = 1, + RTW_REGD_MKK = 2, + RTW_REGD_ETSI = 3, + RTW_REGD_IC = 4, + RTW_REGD_KCC = 5, + RTW_REGD_NCC = 6, + RTW_REGD_ACMA = 7, + RTW_REGD_CHILE = 8, + RTW_REGD_MEX = 9, + RTW_REGD_WW, + RTW_REGD_NUM, +}; + +extern const char *const _regd_str[]; +#define regd_str(regd) (((regd) >= RTW_REGD_NUM) ? _regd_str[RTW_REGD_NA] : _regd_str[(regd)]) + +enum rtw_edcca_mode_t { + RTW_EDCCA_NORM = 0, /* normal */ + RTW_EDCCA_ADAPT = 1, /* adaptivity */ + RTW_EDCCA_CS = 2, /* carrier sense */ + + RTW_EDCCA_MODE_NUM, + RTW_EDCCA_DEF = RTW_EDCCA_MODE_NUM, /* default (ref to domain code), used at country chplan map's override field */ +}; + +extern const char *const _rtw_edcca_mode_str[]; +#define rtw_edcca_mode_str(mode) (((mode) >= RTW_EDCCA_MODE_NUM) ? _rtw_edcca_mode_str[RTW_EDCCA_NORM] : _rtw_edcca_mode_str[(mode)]) enum rtw_dfs_regd { RTW_DFS_REGD_NONE = 0, @@ -65,31 +134,140 @@ enum rtw_dfs_regd { RTW_DFS_REGD_AUTO = 0xFF, /* follow channel plan */ }; -extern const char *_rtw_dfs_regd_str[]; +extern const char *const _rtw_dfs_regd_str[]; #define rtw_dfs_regd_str(region) (((region) >= RTW_DFS_REGD_NUM) ? _rtw_dfs_regd_str[RTW_DFS_REGD_NONE] : _rtw_dfs_regd_str[(region)]) +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_NONE = 0, /* no limit */ + TXPWR_LMT_FCC = 1, + TXPWR_LMT_MKK = 2, + TXPWR_LMT_ETSI = 3, + TXPWR_LMT_IC = 4, + TXPWR_LMT_KCC = 5, + TXPWR_LMT_NCC = 6, + TXPWR_LMT_ACMA = 7, + TXPWR_LMT_CHILE = 8, + TXPWR_LMT_UKRAINE = 9, + TXPWR_LMT_MEXICO = 10, + TXPWR_LMT_CN = 11, + TXPWR_LMT_QATAR = 12, + TXPWR_LMT_WW, /* smallest of all available limit, keep last */ + + TXPWR_LMT_NUM, + TXPWR_LMT_DEF = TXPWR_LMT_NUM, /* default (ref to domain code), used at country chplan map's override field */ +} REGULATION_TXPWR_LMT; + +extern const char *const _txpwr_lmt_str[]; +#define txpwr_lmt_str(regd) (((regd) >= TXPWR_LMT_NUM) ? _txpwr_lmt_str[TXPWR_LMT_NUM] : _txpwr_lmt_str[(regd)]) + +extern const REGULATION_TXPWR_LMT _txpwr_lmt_alternate[]; +#define txpwr_lmt_alternate(ori) (((ori) > TXPWR_LMT_NUM) ? _txpwr_lmt_alternate[TXPWR_LMT_WW] : _txpwr_lmt_alternate[(ori)]) + +#define TXPWR_LMT_ALTERNATE_DEFINED(txpwr_lmt) (txpwr_lmt_alternate(txpwr_lmt) != txpwr_lmt) + +extern const enum rtw_edcca_mode_t _rtw_regd_to_edcca_mode[RTW_REGD_NUM]; +#define rtw_regd_to_edcca_mode(regd) (((regd) >= RTW_REGD_NUM) ? RTW_EDCCA_NORM : _rtw_regd_to_edcca_mode[(regd)]) + +extern const REGULATION_TXPWR_LMT _rtw_regd_to_txpwr_lmt[]; +#define rtw_regd_to_txpwr_lmt(regd) (((regd) >= RTW_REGD_NUM) ? TXPWR_LMT_WW : _rtw_regd_to_txpwr_lmt[(regd)]) + +#define EDCCA_MODES_STR_LEN (((6 + 3 + 1) * BAND_MAX) + 1) +char *rtw_get_edcca_modes_str(char *buf, u8 modes[]); +void rtw_edcca_mode_update(struct dvobj_priv *dvobj); +u8 rtw_get_edcca_mode(struct dvobj_priv *dvobj, enum band_type band); + +#define TXPWR_NAMES_STR_LEN (((1 + 7 + 1) * BAND_MAX) + 1) +char *rtw_get_txpwr_lmt_names_str(char *buf, const char *names[], u8 unknown_bmp); + +#define CHPLAN_PROTO_EN_AC BIT0 +#define CHPLAN_PROTO_EN_AX BIT1 +#define CHPLAN_PROTO_EN_ALL 0xFF + struct country_chplan { - char alpha2[2]; /* "00" means worldwide */ + char alpha2[2]; u8 chplan; -#ifdef CONFIG_80211AC_VHT - u8 en_11ac; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 chplan_6g; +#endif + u8 edcca_mode_2g_override:2; +#if CONFIG_IEEE80211_BAND_5GHZ + u8 edcca_mode_5g_override:2; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + u8 edcca_mode_6g_override:2; +#endif + u8 txpwr_lmt_override; +#if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + u8 proto_en; #endif }; #ifdef CONFIG_80211AC_VHT -#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac) +#define COUNTRY_CHPLAN_EN_11AC(_ent) (((_ent)->proto_en & CHPLAN_PROTO_EN_AC) ? 1 : 0) #else #define COUNTRY_CHPLAN_EN_11AC(_ent) 0 #endif -const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); +#ifdef CONFIG_80211AX_HE +#define COUNTRY_CHPLAN_EN_11AX(_ent) (((_ent)->proto_en & CHPLAN_PROTO_EN_AX) ? 1 : 0) +#else +#define COUNTRY_CHPLAN_EN_11AX(_ent) 0 +#endif + +void rtw_get_chplan_worldwide(struct country_chplan *ent); +bool rtw_get_chplan_from_country(const char *country_code, struct country_chplan *ent); + +void rtw_chplan_ioctl_input_mapping(u16 *chplan, u16 *chplan_6g); +bool rtw_chplan_ids_is_world_wide(u8 chplan, u8 chplan_6g); + +u8 rtw_country_chplan_is_chbw_valid(struct country_chplan *ent, enum band_type band, u8 ch, u8 bw, u8 offset + , bool allow_primary_passive, bool allow_passive, struct registry_priv *regsty); -void dump_country_chplan(void *sel, const struct country_chplan *ent); -void dump_country_chplan_map(void *sel); +enum country_ie_slave_status { + COUNTRY_IE_SLAVE_NOCOUNTRY = 0, + COUNTRY_IE_SLAVE_UNKNOWN = 1, + COUNTRY_IE_SLAVE_OPCH_NOEXIST = 2, + COUNTRY_IE_SLAVE_APPLICABLE = 3, + + COUNTRY_IE_SLAVE_STATUS_NUM, +}; + +struct country_ie_slave_record { + char alpha2[2]; /* country code get from connected AP of STA ifaces, "\x00\x00" is not set */ + enum band_type band; + u8 opch; + enum country_ie_slave_status status; +}; + +#ifdef CONFIG_80211D +extern const char *const _cis_status_str[]; +#define cis_status_str(s) (((s) >= COUNTRY_IE_SLAVE_STATUS_NUM) ? _cis_status_str[COUNTRY_IE_SLAVE_STATUS_NUM] : _cis_status_str[(s)]) + +void dump_country_ie_slave_records(void *sel, struct rf_ctl_t *rfctl, bool skip_noset); + +enum country_ie_slave_status rtw_get_chplan_from_recv_country_ie(_adapter *adapter + , enum band_type band, u8 opch, const u8 *country_ie, struct country_chplan *ent + , struct country_ie_slave_record *cisr, const char *caller_msg); + +enum country_ie_slave_status rtw_get_chplan_from_cisrs(struct rf_ctl_t *rfctl + , struct country_chplan *ent, const char *caller_msg); +#endif + +void dump_country_chplan(void *sel, const struct country_chplan *ent, bool regd_info); +void dump_country_chplan_map(void *sel, bool regd_info); +void dump_country_list(void *sel); void dump_chplan_id_list(void *sel); +void dump_chplan_country_list(void *sel); +#if CONFIG_IEEE80211_BAND_6GHZ +void dump_chplan_6g_id_list(void *sel); +void dump_chplan_6g_country_list(void *sel); +#endif #ifdef CONFIG_RTW_DEBUG void dump_chplan_test(void *sel); #endif void dump_chplan_ver(void *sel); +void rtw_set_phl_regulation_ctx(struct dvobj_priv *dvobj); +void rtw_clear_phl_regulation_ctx(struct dvobj_priv *dvobj); + #endif /* __RTW_CHPLAN_H__ */ diff --git a/core/rtw_cmd.c b/core/rtw_cmd.c index f9d755f..15768c1 100644 --- a/core/rtw_cmd.c +++ b/core/rtw_cmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_CMD_C_ #include -#include #ifndef DBG_CMD_EXECUTE #define DBG_CMD_EXECUTE 0 @@ -25,17 +24,17 @@ Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. No irqsave is necessary. */ - -sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) +u32 rtw_init_cmd_priv(struct dvobj_priv *dvobj) { - sint res = _SUCCESS; - + u32 res = _SUCCESS; + struct cmd_priv *pcmdpriv = &dvobj->cmdpriv; + pcmdpriv->dvobj = dvobj; + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); - /* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */ _rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0); - _rtw_init_queue(&(pcmdpriv->cmd_queue)); + #endif /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ @@ -48,7 +47,7 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) goto exit; } - pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1)); + pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1)); pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); @@ -59,175 +58,48 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); - pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0; + pcmdpriv->cmd_issued_cnt = 0; _rtw_mutex_init(&pcmdpriv->sctx_mutex); -exit: - - - return res; - -} - -#ifdef CONFIG_C2H_WK -static void c2h_wk_callback(_workitem *work) -{ - struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk); - _adapter *adapter = container_of(evtpriv, _adapter, evtpriv); - u8 *c2h_evt; - c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly; - u8 id, seq, plen; - u8 *payload; - - evtpriv->c2h_wk_alive = _TRUE; - - while (!rtw_cbuf_empty(evtpriv->c2h_queue)) { - c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue); - if (c2h_evt != NULL) { - /* This C2H event is read, clear it */ - c2h_evt_clear(adapter); - } else { - c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN); - if (c2h_evt == NULL) { - rtw_warn_on(1); - continue; - } - - /* This C2H event is not read, read & clear now */ - if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) { - rtw_mfree(c2h_evt, C2H_REG_LEN); - continue; - } - } - - /* Special pointer to trigger c2h_evt_clear only */ - if ((void *)c2h_evt == (void *)evtpriv) - continue; - - if (!rtw_hal_c2h_valid(adapter, c2h_evt) - || rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS - ) { - rtw_mfree(c2h_evt, C2H_REG_LEN); - continue; - } - - if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) { - /* Handle directly */ - rtw_hal_c2h_handler(adapter, id, seq, plen, payload); - rtw_mfree(c2h_evt, C2H_REG_LEN); - } else { - /* Enqueue into cmd_thread for others */ - rtw_c2h_reg_wk_cmd(adapter, c2h_evt); - rtw_mfree(c2h_evt, C2H_REG_LEN); - } - } - - evtpriv->c2h_wk_alive = _FALSE; -} -#endif /* CONFIG_C2H_WK */ - -sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) -{ - sint res = _SUCCESS; - - -#ifdef CONFIG_H2CLBK - _rtw_init_sema(&(pevtpriv->lbkevt_done), 0); - pevtpriv->lbkevt_limit = 0; - pevtpriv->lbkevt_num = 0; - pevtpriv->cmdevt_parm = NULL; -#endif - - /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ - ATOMIC_SET(&pevtpriv->event_seq, 0); - pevtpriv->evt_done_cnt = 0; - -#ifdef CONFIG_EVENT_THREAD_MODE - - _rtw_init_sema(&(pevtpriv->evt_notify), 0); - - pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); - if (pevtpriv->evt_allocated_buf == NULL) { - res = _FAIL; - goto exit; - } - pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3); - - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ + 4); - - if (pevtpriv->allocated_c2h_mem == NULL) { - res = _FAIL; - goto exit; - } - - pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4\ - - ((u32)(pevtpriv->allocated_c2h_mem) & 3); -#endif /* end of CONFIG_SDIO_HCI */ - - _rtw_init_queue(&(pevtpriv->evt_queue)); + ATOMIC_SET(&pcmdpriv->event_seq, 0); + pcmdpriv->evt_done_cnt = 0; exit: - -#endif /* end of CONFIG_EVENT_THREAD_MODE */ - -#ifdef CONFIG_C2H_WK - _init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL); - pevtpriv->c2h_wk_alive = _FALSE; - pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1); -#endif - - return res; + } -void _rtw_free_evt_priv(struct evt_priv *pevtpriv) +void rtw_free_cmd_priv(struct dvobj_priv *dvobj) { + struct cmd_priv *pcmdpriv = &dvobj->cmdpriv; + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ + _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); + _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); + _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema)); + #endif + if (pcmdpriv->cmd_allocated_buf) + rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); -#ifdef CONFIG_EVENT_THREAD_MODE - _rtw_free_sema(&(pevtpriv->evt_notify)); - - if (pevtpriv->evt_allocated_buf) - rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); -#endif - -#ifdef CONFIG_C2H_WK - _cancel_workitem_sync(&pevtpriv->c2h_wk); - while (pevtpriv->c2h_wk_alive) - rtw_msleep_os(10); - - while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) { - void *c2h; - c2h = rtw_cbuf_pop(pevtpriv->c2h_queue); - if (c2h != NULL && c2h != (void *)pevtpriv) - rtw_mfree(c2h, 16); - } - rtw_cbuf_free(pevtpriv->c2h_queue); -#endif - - + if (pcmdpriv->rsp_allocated_buf) + rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); + _rtw_mutex_free(&pcmdpriv->sctx_mutex); } -void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) +static int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) { + u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */ + struct dvobj_priv *dvobj = pcmdpriv->dvobj; - if (pcmdpriv) { - _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); - _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); - /* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */ - _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema)); - if (pcmdpriv->cmd_allocated_buf) - rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + if (cmd_obj->cmdcode == CMD_SET_CHANPLAN) + bAllow = _TRUE; - if (pcmdpriv->rsp_allocated_buf) - rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); + if (cmd_obj->no_io) + bAllow = _TRUE; - _rtw_mutex_free(&pcmdpriv->sctx_mutex); - } + return _SUCCESS; } /* @@ -243,16 +115,16 @@ ISR/Call-Back functions can't call this sub-function. extern u8 dump_cmd_id; #endif -sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ +static sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) { - _irqL irqL; - + unsigned long sp_flags; if (obj == NULL) goto exit; - /* _enter_critical_bh(&queue->lock, &irqL); */ - _enter_critical(&queue->lock, &irqL); + /* _rtw_spinlock_bh(&queue->lock); */ + _rtw_spinlock_irq(&queue->lock, &sp_flags); if (to_head) rtw_list_insert_head(&obj->list, &queue->queue); @@ -295,23 +167,85 @@ sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) } #endif /* DBG_CMD_QUEUE */ - /* _exit_critical_bh(&queue->lock, &irqL); */ - _exit_critical(&queue->lock, &irqL); + /* _rtw_spinunlock_bh(&queue->lock); */ + _rtw_spinunlock_irq(&queue->lock, &sp_flags); exit: return _SUCCESS; } +#else +static sint _rtw_enqueue_cmd(struct cmd_obj *obj, bool to_head) +{ + u32 res; + + res = rtw_enqueue_phl_cmd(obj); + +#ifdef DBG_CMD_QUEUE + if (dump_cmd_id) { + RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode); + if (obj->cmdcode == CMD_SET_MLME_EVT) { + if (obj->parmbuf) { + struct rtw_evt_header *evt_hdr = (struct rtw_evt_header *)(obj->parmbuf); + RTW_INFO("evt_hdr->id:%d\n", evt_hdr->id); + } + } + if (obj->cmdcode == CMD_SET_DRV_EXTRA) { + if (obj->parmbuf) { + struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf); + RTW_INFO("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id); + } + } + } +#endif /* DBG_CMD_QUEUE */ + return res; +} +#endif + +u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) +{ + int res = _FAIL; + + if (cmd_obj == NULL) + goto exit; + + res = rtw_cmd_filter(pcmdpriv, cmd_obj); + if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) { + if (cmd_obj->cmdsz > MAX_CMDSZ) { + RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ); + rtw_warn_on(1); + } + + if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) { + struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + + if (extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + rtw_free_cmd_obj(cmd_obj); + goto exit; + } + + + res = _rtw_enqueue_cmd(cmd_obj, 0); + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ + if (res == _SUCCESS) + _rtw_up_sema(&pcmdpriv->cmd_queue_sema); + #endif + +exit: + return res; +} +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) { - _irqL irqL; struct cmd_obj *obj; + unsigned long sp_flags; - - /* _enter_critical_bh(&(queue->lock), &irqL); */ - _enter_critical(&queue->lock, &irqL); + /* _rtw_spinlock_bh(&(queue->lock)); */ + _rtw_spinlock_irq(&queue->lock, &sp_flags); #ifdef DBG_CMD_QUEUE if (queue->queue.prev->next != &queue->queue) { @@ -357,144 +291,22 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) rtw_list_delete(&obj->list); } - /* _exit_critical_bh(&(queue->lock), &irqL); */ - _exit_critical(&queue->lock, &irqL); + /* _rtw_spinunlock_bh(&(queue->lock)); */ + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return obj; } -u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) -{ - u32 res; - res = _rtw_init_cmd_priv(pcmdpriv); - return res; -} - -u32 rtw_init_evt_priv(struct evt_priv *pevtpriv) -{ - int res; - res = _rtw_init_evt_priv(pevtpriv); - return res; -} - -void rtw_free_evt_priv(struct evt_priv *pevtpriv) -{ - _rtw_free_evt_priv(pevtpriv); -} - -void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) -{ - _rtw_free_cmd_priv(pcmdpriv); -} - -int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj); -int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) -{ -#ifndef CONFIG_MAC_LOOPBACK_DRIVER - u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */ -#else - u8 bAllow = _TRUE; /* hw_init_completed is _FALSE in the case of MAC loopback*/ -#endif - -#ifdef SUPPORT_HW_RFOFF_DETECTED - /* To decide allow or not */ - if ((adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect) - && (!pcmdpriv->padapter->registrypriv.usbss_enable) - ) { - if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) { - struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; - if (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) { - /* RTW_INFO("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); */ - bAllow = _TRUE; - } - } - } -#endif - - if (cmd_obj->cmdcode == CMD_SET_CHANPLAN) - bAllow = _TRUE; - - if (cmd_obj->no_io) - bAllow = _TRUE; - - if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE)) - || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE /* com_thread not running */ - ) { - if (DBG_CMD_EXECUTE) - RTW_INFO(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter) - , CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running)); - if (0) - rtw_warn_on(1); - - return _FAIL; - } - return _SUCCESS; -} - - - -u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) -{ - int res = _FAIL; - PADAPTER padapter = pcmdpriv->padapter; - - - if (cmd_obj == NULL) - goto exit; - - cmd_obj->padapter = padapter; - -#ifdef CONFIG_CONCURRENT_MODE - /* change pcmdpriv to primary's pcmdpriv */ - if (!is_primary_adapter(padapter)) - pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv); -#endif - - res = rtw_cmd_filter(pcmdpriv, cmd_obj); - if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) { - if (cmd_obj->cmdsz > MAX_CMDSZ) { - RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ); - rtw_warn_on(1); - } - - if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) { - struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; - - if (extra_parm->pbuf && extra_parm->size > 0) - rtw_mfree(extra_parm->pbuf, extra_parm->size); - } - rtw_free_cmd_obj(cmd_obj); - goto exit; - } - - res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0); - - if (res == _SUCCESS) - _rtw_up_sema(&pcmdpriv->cmd_queue_sema); - -exit: - - - return res; -} - struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) { struct cmd_obj *cmd_obj; - cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); return cmd_obj; } - -void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) -{ - pcmdpriv->cmd_done_cnt++; - /* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */ -} - +#endif void rtw_free_cmd_obj(struct cmd_obj *pcmd) { if (pcmd->parmbuf != NULL) { @@ -511,67 +323,146 @@ void rtw_free_cmd_obj(struct cmd_obj *pcmd) /* free cmd_obj */ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); } - - -void rtw_stop_cmd_thread(_adapter *adapter) -{ - if (adapter->cmdThread) { - _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); - rtw_thread_stop(adapter->cmdThread); - adapter->cmdThread = NULL; - } -} - -thread_return rtw_cmd_thread(thread_context context) +void rtw_run_cmd(_adapter *padapter, struct cmd_obj *pcmd, bool discard) { u8 ret; - struct cmd_obj *pcmd; - u8 *pcmdbuf, *prspbuf; + u8 *pcmdbuf; systime cmd_start_time; u32 cmd_process_time; u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); - PADAPTER padapter = (PADAPTER)context; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(padapter)->cmdpriv); struct drvextra_cmd_parm *extra_parm = NULL; - _irqL irqL; - thread_enter("RTW_CMD_THREAD"); + cmd_start_time = rtw_get_current_time(); + pcmdpriv->cmd_issued_cnt++; - pcmdbuf = pcmdpriv->cmd_buf; - prspbuf = pcmdpriv->rsp_buf; - ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); - _rtw_up_sema(&pcmdpriv->start_cmdthread_sema); + if (discard) + goto post_process; + if (pcmd->cmdsz > MAX_CMDSZ) { + RTW_ERR("%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } - while (1) { - if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { - RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter)); - break; - } + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) { + RTW_ERR("%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } - if (RTW_CANNOT_RUN(padapter)) { - RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", - FUNC_ADPT_ARG(padapter), - rtw_is_drv_stopped(padapter) ? "True" : "False", - rtw_is_surprise_removed(padapter) ? "True" : "False"); - break; - } + cmd_hdl = wlancmds[pcmd->cmdcode].cmd_hdl; + if (!cmd_hdl) { + RTW_ERR("%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + if (DBG_CMD_EXECUTE) + RTW_INFO(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd) + , pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : "")); + + pcmdbuf = pcmdpriv->cmd_buf; + _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz); + ret = cmd_hdl(pcmd->padapter, pcmdbuf); + pcmd->res = ret; + + pcmdpriv->cmd_seq++; + +post_process: + + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); + if (pcmd->sctx) { + if (0) + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); + if (pcmd->res == H2C_SUCCESS) + rtw_sctx_done(&pcmd->sctx); + else + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR); + } + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); + + cmd_process_time = rtw_get_passing_time_ms(cmd_start_time); + if (cmd_process_time > 1000) { + RTW_INFO(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time); + if (0) + rtw_warn_on(1); + } + + /* call callback function for post-processed */ + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) + pcmd_callback = wlancmds[pcmd->cmdcode].callback; + else + pcmd_callback = NULL; + + if (pcmd_callback == NULL) { + rtw_free_cmd_obj(pcmd); + } else { + /* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */ + pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */ + } +} +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ +void rtw_stop_cmd_thread(_adapter *adapter) +{ + if (adapter->cmdThread) { + _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); + rtw_thread_stop(adapter->cmdThread); + adapter->cmdThread = NULL; + } +} + +thread_return rtw_cmd_thread(thread_context context) +{ + u8 ret; + struct cmd_obj *pcmd; + u8 *pcmdbuf, *prspbuf; + systime cmd_start_time; + u32 cmd_process_time; + u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); + void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); + _adapter *padapter = (_adapter *)context; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct drvextra_cmd_parm *extra_parm = NULL; + unsigned long sp_flags; + + rtw_thread_enter("RTW_CMD_THREAD"); + + pcmdbuf = pcmdpriv->cmd_buf; + prspbuf = pcmdpriv->rsp_buf; + ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); + _rtw_up_sema(&pcmdpriv->start_cmdthread_sema); - _enter_critical(&pcmdpriv->cmd_queue.lock, &irqL); + + while (1) { + if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { + RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter)); + break; + } + + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(padapter), + dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False", + dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False"); + break; + } + + _rtw_spinlock_irq(&pcmdpriv->cmd_queue.lock, &sp_flags); if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) { /* RTW_INFO("%s: cmd queue is empty!\n", __func__); */ - _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + _rtw_spinunlock_irq(&pcmdpriv->cmd_queue.lock, &sp_flags); continue; } - _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + _rtw_spinunlock_irq(&pcmdpriv->cmd_queue.lock, &sp_flags); _next: - if (RTW_CANNOT_RUN(padapter)) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False" + , dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False" , __LINE__); break; } @@ -615,7 +506,7 @@ thread_return rtw_cmd_thread(thread_context context) } #if CONFIG_DFS else if (pcmd->cmdcode == CMD_SET_CHANSWITCH) - adapter_to_rfctl(padapter)->csa_ch = 0; + adapter_to_rfctl(padapter)->csa_chandef.chan = 0; #endif goto post_process; } @@ -655,7 +546,7 @@ thread_return rtw_cmd_thread(thread_context context) post_process: - _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + _rtw_mutex_lock_interruptible(&(pcmd->padapter->cmdpriv.sctx_mutex)); if (pcmd->sctx) { if (0) RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); @@ -664,7 +555,7 @@ thread_return rtw_cmd_thread(thread_context context) else rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR); } - _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + _rtw_mutex_unlock(&(pcmd->padapter->cmdpriv.sctx_mutex)); cmd_process_time = rtw_get_passing_time_ms(cmd_start_time); if (cmd_process_time > 1000) { @@ -674,7 +565,7 @@ thread_return rtw_cmd_thread(thread_context context) } /* call callback function for post-processed */ - if (pcmd->cmdcode < (sizeof(wlancmds) / sizeof(struct rtw_cmd))) + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) pcmd_callback = wlancmds[pcmd->cmdcode].callback; else pcmd_callback = NULL; @@ -715,16 +606,16 @@ thread_return rtw_cmd_thread(thread_context context) } #if CONFIG_DFS else if (pcmd->cmdcode == CMD_SET_CHANSWITCH) - adapter_to_rfctl(padapter)->csa_ch = 0; + adapter_to_rfctl(padapter)->csa_chandef.chan = 0; #endif - _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + _rtw_mutex_lock_interruptible(&(pcmd->padapter->cmdpriv.sctx_mutex)); if (pcmd->sctx) { if (0) RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP); } - _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + _rtw_mutex_unlock(&(pcmd->padapter->cmdpriv.sctx_mutex)); rtw_free_cmd_obj(pcmd); } while (1); @@ -735,145 +626,8 @@ thread_return rtw_cmd_thread(thread_context context) return 0; } - - -#ifdef CONFIG_EVENT_THREAD_MODE -u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) -{ - _irqL irqL; - int res; - _queue *queue = &pevtpriv->evt_queue; - - - res = _SUCCESS; - - if (obj == NULL) { - res = _FAIL; - goto exit; - } - - _enter_critical_bh(&queue->lock, &irqL); - - rtw_list_insert_tail(&obj->list, &queue->queue); - - _exit_critical_bh(&queue->lock, &irqL); - - /* rtw_evt_notify_isr(pevtpriv); */ - -exit: - - - return res; -} - -struct evt_obj *rtw_dequeue_evt(_queue *queue) -{ - _irqL irqL; - struct evt_obj *pevtobj; - - - _enter_critical_bh(&queue->lock, &irqL); - - if (rtw_is_list_empty(&(queue->queue))) - pevtobj = NULL; - else { - pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list); - rtw_list_delete(&pevtobj->list); - } - - _exit_critical_bh(&queue->lock, &irqL); - - - return pevtobj; -} - -void rtw_free_evt_obj(struct evt_obj *pevtobj) -{ - - if (pevtobj->parmbuf) - rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz); - - rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj)); - -} - -void rtw_evt_notify_isr(struct evt_priv *pevtpriv) -{ - pevtpriv->evt_done_cnt++; - _rtw_up_sema(&(pevtpriv->evt_notify)); -} -#endif - -void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm) -{ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - - _rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm)); - pparm->scan_mode = pmlmepriv->scan_mode; -} - -/* -rtw_sitesurvey_cmd(~) - ### NOTE:#### (!!!!) - MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock -*/ -u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm) -{ - u8 res = _FAIL; - struct cmd_obj *ph2c; - struct sitesurvey_parm *psurveyPara; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - -#ifdef CONFIG_LPS - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 0); #endif -#ifdef CONFIG_P2P_PS - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); -#endif /* CONFIG_P2P_PS */ - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) - return _FAIL; - - psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); - if (psurveyPara == NULL) { - rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); - return _FAIL; - } - - if (pparm) - _rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm)); - else - psurveyPara->scan_mode = pmlmepriv->scan_mode; - - rtw_free_network_queue(padapter, _FALSE); - - init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, CMD_SITE_SURVEY); - - set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY); - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - - if (res == _SUCCESS) { - u32 scan_timeout_ms; - - pmlmepriv->scan_start_time = rtw_get_current_time(); - scan_timeout_ms = rtw_scan_timeout_decision(padapter); - mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms); - - rtw_led_control(padapter, LED_CTL_SITE_SURVEY); - } else - _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); - - - return res; -} - void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { @@ -887,13 +641,12 @@ void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) } -#ifdef CONFIG_AP_MODE static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset) { struct cmd_obj *cmdobj; struct createbss_parm *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -921,6 +674,11 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc parm->req_ch = req_ch; parm->req_bw = req_bw; parm->req_offset = req_offset; + parm->ifbmp_ch_changed = 0; + parm->ch_to_set = 0; + parm->bw_to_set = 0; + parm->offset_to_set = 0; + parm->do_rfk = _FALSE; } if (flags & RTW_CMDF_DIRECTLY) { @@ -936,22 +694,23 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_CREATE_BSS); if (flags & RTW_CMDF_WAIT_ACK) { cmdobj->sctx = &sctx; - rtw_sctx_init(&sctx, 2000); + rtw_sctx_init(&sctx, 5000); } res = rtw_enqueue_cmd(pcmdpriv, cmdobj); if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { - rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + res = rtw_sctx_wait(&sctx, __func__); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } } @@ -986,25 +745,81 @@ inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags , req_ch, req_bw, req_offset ); } -#endif /* CONFIG_AP_MODE */ -u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) +#ifdef CONFIG_80211D +/* Return corresponding country_chplan setting */ +static bool rtw_joinbss_check_country_ie(_adapter *adapter, const WLAN_BSSID_EX *network, struct country_chplan *ent, WLAN_BSSID_EX *out_network) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + bool ret = 0; + + if (rfctl->regd_src == REGD_SRC_RTK_PRIV + && !rtw_rfctl_is_disable_sw_channel_plan(rfctl_to_dvobj(rfctl)) + ) { + struct mlme_priv *mlme = &adapter->mlmepriv; + const u8 *country_ie = NULL; + sint country_ie_len = 0; + + if (rtw_iface_accept_country_ie(adapter)) { + country_ie = rtw_get_ie(BSS_EX_TLV_IES(network) + , WLAN_EID_COUNTRY, &country_ie_len, BSS_EX_TLV_IES_LEN(network)); + if (country_ie) { + if (country_ie_len < 6) { + country_ie = NULL; + country_ie_len = 0; + } else + country_ie_len += 2; + } + } + + if (country_ie) { + enum country_ie_slave_status status; + + rtw_buf_update(&mlme->recv_country_ie, &mlme->recv_country_ie_len, country_ie, country_ie_len); + + status = rtw_get_chplan_from_recv_country_ie(adapter + , network->Configuration.DSConfig > 14 ? BAND_ON_5G : BAND_ON_24G + , network->Configuration.DSConfig, country_ie, ent, NULL, __func__); + if (status != COUNTRY_IE_SLAVE_NOCOUNTRY) + ret = 1; + + if (out_network) { + _rtw_memcpy(BSS_EX_IES(out_network) + BSS_EX_IES_LEN(out_network) + , country_ie, country_ie_len); + BSS_EX_IES_LEN(out_network) += country_ie_len; + } + } else + rtw_buf_free(&mlme->recv_country_ie, &mlme->recv_country_ie_len); + } + + return ret; +} +#endif /* CONFIG_80211D */ + +u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) { u8 *auth, res = _SUCCESS; uint t_len = 0; WLAN_BSSID_EX *psecnetwork; struct cmd_obj *pcmd; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct qos_priv *pqospriv = &pmlmepriv->qospriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct registry_priv *pregistrypriv = &padapter->registrypriv; +#ifdef CONFIG_80211D + struct country_chplan country_ent; +#endif + struct country_chplan *req_chplan = NULL; #ifdef CONFIG_80211N_HT struct ht_priv *phtpriv = &pmlmepriv->htpriv; #endif /* CONFIG_80211N_HT */ #ifdef CONFIG_80211AC_VHT struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + struct he_priv *phepriv = &pmlmepriv->hepriv; +#endif /* CONFIG_80211AX_HE */ NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -1019,21 +834,14 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) res = _FAIL; goto exit; } -#if 0 - /* for IEs is pointer */ - t_len = sizeof(u32) + sizeof(NDIS_802_11_MAC_ADDRESS) + 2 + - sizeof(NDIS_802_11_SSID) + sizeof(u32) + - sizeof(NDIS_802_11_RSSI) + sizeof(NDIS_802_11_NETWORK_TYPE) + - sizeof(NDIS_802_11_CONFIGURATION) + - sizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE) + - sizeof(NDIS_802_11_RATES_EX) + sizeof(WLAN_PHY_INFO) + sizeof(u32) + MAX_IE_SZ; -#endif + pcmd->padapter = padapter; + /* for IEs is fix buf size */ t_len = sizeof(WLAN_BSSID_EX); /* for hidden ap to set fw_state here */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) { + if (!MLME_IS_STA(padapter) || !MLME_IS_ADHOC(padapter)) { switch (ndis_network_mode) { case Ndis802_11IBSS: set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); @@ -1055,8 +863,8 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) /* save AP beamform_cap info for BCM IOT issue */ if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) get_vht_bf_cap(pnetwork->network.IEs, - pnetwork->network.IELength, - &pvhtpriv->ap_bf_cap); + pnetwork->network.IELength, + &pvhtpriv->ap_bf_cap); #endif /* Modified by Arvin 2015/05/13 @@ -1117,6 +925,15 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) } } +#ifdef RTW_WKARD_UPDATE_PHL_ROLE_CAP + rtw_update_phl_cap_by_rgstry(padapter); +#endif + +#ifdef CONFIG_80211D + if (rtw_joinbss_check_country_ie(padapter, &pnetwork->network, &country_ent, psecnetwork)) + req_chplan = &country_ent; +#endif + #ifdef CONFIG_80211N_HT phtpriv->ht_option = _FALSE; if (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) { @@ -1133,7 +950,7 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) /* rtw_restructure_ht_ie */ rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], pnetwork->network.IELength - 12, &psecnetwork->IELength, - pnetwork->network.Configuration.DSConfig); + pnetwork->network.Configuration.DSConfig, req_chplan); } } } @@ -1143,7 +960,8 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) if (phtpriv->ht_option && REGSTY_IS_11AC_ENABLE(pregistrypriv) && is_supported_vht(pregistrypriv->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + && ((req_chplan && COUNTRY_CHPLAN_EN_11AC(req_chplan)) + || (!req_chplan && RFCTL_REG_EN_11AC(rfctl))) ) { u8 vht_enable = 0; @@ -1154,12 +972,30 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) if (vht_enable == 1) rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], - pnetwork->network.IELength, &psecnetwork->IELength); + pnetwork->network.IELength, &psecnetwork->IELength, req_chplan); } +#endif /* CONFIG_80211AC_VHT */ + +#ifdef CONFIG_80211AX_HE + phepriv->he_option = _FALSE; + if (((phtpriv->ht_option && pnetwork->network.Configuration.DSConfig <= 14) +#ifdef CONFIG_80211AC_VHT + || (pvhtpriv->vht_option && pnetwork->network.Configuration.DSConfig > 14) #endif + ) + && REGSTY_IS_11AX_ENABLE(pregistrypriv) + && is_supported_he(pregistrypriv->wireless_mode) + && ((req_chplan && COUNTRY_CHPLAN_EN_11AX(req_chplan)) + || (!req_chplan && RFCTL_REG_EN_11AX(rfctl))) + ) { + rtw_restructure_he_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], + pnetwork->network.IELength, &psecnetwork->IELength, req_chplan); + } +#endif /* CONFIG_80211AX_HE */ + #endif /* CONFIG_80211N_HT */ - rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); + rtw_append_extended_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); #ifdef CONFIG_RTW_80211R rtw_ft_validate_akm_type(padapter, pnetwork); @@ -1177,7 +1013,7 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) pcmd->cmdsz = sizeof(WLAN_BSSID_EX); _rtw_init_listhead(&pcmd->list); - pcmd->cmdcode = CMD_JOINBSS;/* _JoinBss_CMD_ */ + pcmd->cmdcode = CMD_JOINBSS; /*_JoinBss_CMD_;*/ pcmd->parmbuf = (unsigned char *)psecnetwork; pcmd->rsp = NULL; pcmd->rspsz = 0; @@ -1190,15 +1026,86 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) return res; } +#ifdef CONFIG_STA_CMD_DISPR +/* for sta_mode only */ +static u8 sta_disassoc_cmd(struct _ADAPTER *a, u32 deauth_timeout_ms, int flags) +{ + struct cmd_priv *cmdpriv = &adapter_to_dvobj(a)->cmdpriv; + struct cmd_obj *cmd = NULL; + struct disconnect_parm *param = NULL; + struct submit_ctx sctx; + enum rtw_phl_status status; + int ret; + u8 res = _FAIL; + + + if (!MLME_IS_ASOC(a)) + return _SUCCESS; + + param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); + if (!param) { + RTW_ERR(FUNC_ADPT_FMT ": alloc param FAIL!", FUNC_ADPT_ARG(a)); + goto exit; + } + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmd)); + if (!cmd) { + RTW_ERR(FUNC_ADPT_FMT ": alloc cmd FAIL!", FUNC_ADPT_ARG(a)); + rtw_mfree((u8 *)param, sizeof(*param)); + goto exit; + } + + param->deauth_timeout_ms = deauth_timeout_ms; + init_h2fwcmd_w_parm_no_rsp(cmd, param, CMD_DISCONNECT); + cmd->padapter = a; + if (flags & RTW_CMDF_WAIT_ACK) { + cmd->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + status = rtw_disconnect_cmd(a, cmd); + if (status != RTW_PHL_STATUS_SUCCESS) { + /* param & cmd would be freed in rtw_enqueue_cmd() */ + RTW_ERR(FUNC_ADPT_FMT ": send disconnect cmd FAIL!(0x%x)\n", + FUNC_ADPT_ARG(a), status); + goto exit; + } + res = _SUCCESS; + + if (flags & RTW_CMDF_WAIT_ACK) { + ret = rtw_sctx_wait(&sctx, __func__); + if (ret == _FAIL) + res = _FAIL; + _rtw_spinlock(&a->disconnect_lock); + if (a->discon_cmd) { + a->discon_cmd->sctx = NULL; + /* + * a->discon_param would be + * freed by disconnect cmd dispatcher. + */ + } + _rtw_spinunlock(&a->disconnect_lock); + } + +exit: + return res; +} +#endif /* CONFIG_STA_CMD_DISPR */ + u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */ { struct cmd_obj *cmdobj = NULL; struct disconnect_parm *param = NULL; - struct cmd_priv *cmdpriv = &padapter->cmdpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct submit_ctx sctx; u8 res = _SUCCESS; + +#ifdef CONFIG_STA_CMD_DISPR + if (MLME_IS_STA(padapter)) + return sta_disassoc_cmd(padapter, deauth_timeout_ms, flags); +#endif /* CONFIG_STA_CMD_DISPR */ + /* prepare cmd parameter */ param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); if (param == NULL) { @@ -1220,33 +1127,38 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for rtw_mfree((u8 *)param, sizeof(*param)); goto exit; } + cmdobj->padapter = padapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, param, CMD_DISCONNECT); if (flags & RTW_CMDF_WAIT_ACK) { cmdobj->sctx = &sctx; rtw_sctx_init(&sctx, 2000); } res = rtw_enqueue_cmd(cmdpriv, cmdobj); - if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + if (res == _FAIL) { + RTW_ERR(FUNC_ADPT_FMT ": enqueue disconnect cmd FAIL!\n", + FUNC_ADPT_ARG(padapter)); + goto exit; + } + if (flags & RTW_CMDF_WAIT_ACK) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&cmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&cmdpriv->sctx_mutex); } } exit: - - return res; } -#ifdef CONFIG_AP_MODE -u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags) + +u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags) { +#ifdef CONFIG_AP_MODE struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -1265,13 +1177,14 @@ u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags) parm->type = 0; parm->size = 0; parm->pbuf = NULL; - + /* need enqueue, prepare cmd_obj and enqueue */ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); if (cmdobj == NULL) { res = _FAIL; goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); @@ -1284,35 +1197,37 @@ u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags) if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } } + exit: return res; +#endif } -#endif /* CONFIG_AP_MODE */ #ifdef CONFIG_RTW_TOKEN_BASED_XMIT u8 rtw_tx_control_cmd(_adapter *adapter) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 res = _SUCCESS; - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL){ + + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL){ res = _FAIL; goto exit; } + cmd->padapter = adapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -1321,9 +1236,9 @@ u8 rtw_tx_control_cmd(_adapter *adapter) pdrvextra_cmd_parm->type = 0; pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: return res; @@ -1334,7 +1249,7 @@ u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE netw { struct cmd_obj *cmdobj; struct setopmode_parm *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -1359,6 +1274,7 @@ u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE netw rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_OPMODE); @@ -1371,10 +1287,10 @@ u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE netw if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } } @@ -1382,44 +1298,36 @@ u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE netw return res; } +#ifdef CONFIG_CMD_DISP u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue) { - struct cmd_obj *ph2c; - struct set_stakey_parm *psetstakey_para; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct set_stakey_rsp *psetstakey_rsp = NULL; + struct set_stakey_parm setstakey_para; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; u8 key_len =16; - u8 res = _SUCCESS; - - - psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); - if (psetstakey_para == NULL) { - res = _FAIL; - goto exit; - } + u8 res = _SUCCESS; - _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memset(&setstakey_para, 0, sizeof(struct set_stakey_parm)); + _rtw_memcpy(setstakey_para.addr, sta->phl_sta->mac_addr, ETH_ALEN); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; + if (MLME_IS_STA(padapter)) + setstakey_para.algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; else - GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); + GET_ENCRY_ALGO(psecuritypriv, sta, setstakey_para.algorithm, _FALSE); - if ((psetstakey_para->algorithm == _GCMP_256_) || (psetstakey_para->algorithm == _CCMP_256_)) + if ((setstakey_para.algorithm == _GCMP_256_) || (setstakey_para.algorithm == _CCMP_256_)) key_len = 32; if (key_type == GROUP_KEY) { - _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, key_len); - psetstakey_para->gk = 1; + _rtw_memcpy(&setstakey_para.key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, key_len); + setstakey_para.gk = 1; } else if (key_type == UNICAST_KEY) - _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, key_len); + _rtw_memcpy(&setstakey_para.key, &sta->dot118021x_UncstKey, key_len); #ifdef CONFIG_TDLS else if (key_type == TDLS_KEY) { - _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, key_len); - psetstakey_para->algorithm = (u8)sta->dot118021XPrivacy; + _rtw_memcpy(&setstakey_para.key, sta->tpk.tk, key_len); + setstakey_para.algorithm = (u8)sta->dot118021XPrivacy; } #endif /* CONFIG_TDLS */ @@ -1427,43 +1335,120 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool padapter->securitypriv.busetkipkey = _TRUE; if (enqueue) { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); - res = _FAIL; - goto exit; - } - - psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp)); - if (psetstakey_rsp == NULL) { - rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); - rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); - res = _FAIL; - goto exit; - } - - init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY); - ph2c->rsp = (u8 *) psetstakey_rsp; - ph2c->rspsz = sizeof(struct set_stakey_rsp); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + set_stakey_hdl(padapter, &setstakey_para, PHL_CMD_NO_WAIT, 0); } else { - set_stakey_hdl(padapter, (u8 *)psetstakey_para); - rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + set_stakey_hdl(padapter, &setstakey_para, PHL_CMD_DIRECTLY, 0); } exit: + return res; +} + +u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) +{ + struct cmd_obj *cmd; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + s16 cam_id = 0; + u8 res = _SUCCESS; + + if (!sta) { + RTW_ERR("%s sta == NULL\n", __func__); + goto exit; + } + + if (!enqueue) + rtw_hw_del_all_key(padapter, sta, PHL_CMD_DIRECTLY, 0); + else + rtw_hw_del_all_key(padapter, sta, PHL_CMD_NO_WAIT, 0); + +exit: + + + return res; +} +#else /* CONFIG_FSM */ +u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue) +{ + struct cmd_obj *pcmd; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 key_len =16; + u8 res = _SUCCESS; + + + psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (psetstakey_para == NULL) { + res = _FAIL; + goto exit; + } + + _rtw_memcpy(psetstakey_para->addr, sta->phl_sta->mac_addr, ETH_ALEN); + + if (MLME_IS_STA(padapter)) + psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; + else + GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); + + if ((psetstakey_para->algorithm == _GCMP_256_) || (psetstakey_para->algorithm == _CCMP_256_)) + key_len = 32; + + if (key_type == GROUP_KEY) { + _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, key_len); + psetstakey_para->gk = 1; + } else if (key_type == UNICAST_KEY) + _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, key_len); +#ifdef CONFIG_TDLS + else if (key_type == TDLS_KEY) { + _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, key_len); + psetstakey_para->algorithm = (u8)sta->dot118021XPrivacy; + } +#endif /* CONFIG_TDLS */ + + /* jeff: set this becasue at least sw key is ready */ + padapter->securitypriv.busetkipkey = _TRUE; + + if (enqueue) { + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res = _FAIL; + goto exit; + } + pcmd->padapter = padapter; + psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp)); + if (psetstakey_rsp == NULL) { + rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res = _FAIL; + goto exit; + } + init_h2fwcmd_w_parm_no_rsp(pcmd, psetstakey_para, CMD_SET_STAKEY); + pcmd->rsp = (u8 *) psetstakey_rsp; + pcmd->rspsz = sizeof(struct set_stakey_rsp); + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + } else { + set_stakey_hdl(padapter, (u8 *)psetstakey_para); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + } +exit: return res; } u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) { - struct cmd_obj *ph2c; + struct cmd_obj *cmd; struct set_stakey_parm *psetstakey_para; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct set_stakey_rsp *psetstakey_rsp = NULL; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; s16 cam_id = 0; - u8 res = _SUCCESS; + u8 res = _SUCCESS; if (!sta) { RTW_ERR("%s sta == NULL\n", __func__); @@ -1471,42 +1456,39 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) } if (!enqueue) { - while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) { - RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id); - clear_cam_entry(padapter, cam_id); - rtw_camid_free(padapter, cam_id); - } + rtw_hw_del_all_key(padapter, sta, PHL_CMD_DIRECTLY, 0); } else { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); if (psetstakey_para == NULL) { - rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } + cmd->padapter = padapter; psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp)); if (psetstakey_rsp == NULL) { - rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); - rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + rtw_mfree((u8 *)cmd, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)psetstakey_para, sizeof(struct set_stakey_parm)); res = _FAIL; goto exit; } - init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY); - ph2c->rsp = (u8 *) psetstakey_rsp; - ph2c->rspsz = sizeof(struct set_stakey_rsp); + init_h2fwcmd_w_parm_no_rsp(cmd, psetstakey_para, CMD_SET_STAKEY); + cmd->rsp = (u8 *) psetstakey_rsp; + cmd->rspsz = sizeof(struct set_stakey_rsp); - _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(psetstakey_para->addr, sta->phl_sta->mac_addr, ETH_ALEN); psetstakey_para->algorithm = _NO_PRIVACY_; - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); } @@ -1515,25 +1497,27 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) return res; } +#endif u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr) { - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct cmd_obj *ph2c; - struct addBaReq_parm *paddbareq_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct cmd_obj *cmd; + struct addBaReq_parm *paddbareq_parm; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; paddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm)); if (paddbareq_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -1541,74 +1525,103 @@ u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr) paddbareq_parm->tid = tid; _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN); - init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, CMD_ADD_BAREQ); + init_h2fwcmd_w_parm_no_rsp(cmd, paddbareq_parm, CMD_ADD_BAREQ); /* RTW_INFO("rtw_addbareq_cmd, tid=%d\n", tid); */ /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: - - return res; } -u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq) +u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, + struct ADDBA_request *paddba_req, u8 status, + u8 size, u16 start_seq) { - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct cmd_obj *ph2c; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct cmd_obj *cmd; struct addBaRsp_parm *paddBaRsp_parm; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm)); if (paddBaRsp_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } _rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN); + _rtw_memcpy(&(paddBaRsp_parm->preq), paddba_req, sizeof(struct ADDBA_request)); paddBaRsp_parm->tid = tid; paddBaRsp_parm->status = status; paddBaRsp_parm->size = size; paddBaRsp_parm->start_seq = start_seq; - init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, CMD_ADD_BARSP); + init_h2fwcmd_w_parm_no_rsp(cmd, paddBaRsp_parm, CMD_ADD_BARSP); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: return res; } + +u8 rtw_delba_cmd(struct _ADAPTER *a, u8 *addr, u16 tid) +{ + struct cmd_priv *cmdpriv = &adapter_to_dvobj(a)->cmdpriv; + struct cmd_obj *cmd = NULL; + struct addBaReq_parm *parm = NULL; + + + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (!cmd) + return _FAIL; + cmd->padapter = a; + + parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm)); + if (!parm) { + rtw_mfree(cmd, sizeof(struct cmd_obj)); + return _FAIL; + } + + parm->tid = tid; + _rtw_memcpy(parm->addr, addr, ETH_ALEN); + init_h2fwcmd_w_parm_no_rsp(cmd, parm, CMD_DELBA); + + return rtw_enqueue_cmd(cmdpriv, cmd); +} + /* add for CONFIG_IEEE80211W, none 11w can use it */ u8 rtw_reset_securitypriv_cmd(_adapter *padapter) { - struct cmd_obj *ph2c; + struct cmd_obj *cmd; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -1618,15 +1631,13 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter) pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: - - return res; } @@ -1640,7 +1651,7 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int f { struct cmd_obj *cmd; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -1653,6 +1664,7 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int f res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { @@ -1676,36 +1688,37 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int f if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmd->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } } exit: return res; } - +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; u8 res = _SUCCESS; /* only primary padapter does this cmd */ - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -1714,65 +1727,21 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) pdrvextra_cmd_parm->type = 0; pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - -exit: - - - return res; - -} - -u8 rtw_iqk_cmd(_adapter *padapter, u8 flags) -{ - struct cmd_obj *pcmdobj; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct submit_ctx sctx; - u8 res = _SUCCESS; - - if (flags & RTW_CMDF_DIRECTLY) { - /* no need to enqueue, do the cmd hdl */ - rtw_iqk_hdl(padapter, NULL); - } else { - /* need enqueue, prepare cmd_obj and enqueue */ - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmdobj == NULL) { - res = _FAIL; - goto exit; - } - - init_h2fwcmd_w_parm_no_parm_rsp(pcmdobj, CMD_DO_IQK); - - if (flags & RTW_CMDF_WAIT_ACK) { - pcmdobj->sctx = &sctx; - rtw_sctx_init(&sctx, 10 * 1000); - } - - res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); - - if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { - rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); - if (sctx.status == RTW_SCTX_SUBMITTED) - pcmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); - } - } + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: - return res; } - +#endif u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) { struct cmd_obj *pcmdobj; struct set_ch_parm *set_ch_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -1791,6 +1760,7 @@ u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) set_ch_parm->ch = ch; set_ch_parm->bw = bw; set_ch_parm->ch_offset = ch_offset; + set_ch_parm->do_rfk = _FALSE;/*TODO - Need check if do_rfk*/ if (flags & RTW_CMDF_DIRECTLY) { /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ @@ -1800,12 +1770,13 @@ u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); } else { /* need enqueue, prepare cmd_obj and enqueue */ - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); res = _FAIL; goto exit; } + pcmdobj->padapter = padapter; init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, CMD_SET_CHANNEL); @@ -1818,45 +1789,45 @@ u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) pcmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } } /* do something based on res... */ - exit: - RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res); - - return res; } -static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, enum regd_src_t regd_src, u8 swconfig) +static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags + , u8 chplan, u8 chplan_6g, const struct country_chplan *country_ent + , enum regd_src_t regd_src, enum rtw_regd_inr inr + , const struct country_ie_slave_record *cisr) { struct cmd_obj *cmdobj; - struct SetChannelPlan_param *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct SetChannelPlan_param *parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; +#ifdef PLATFORM_LINUX + bool rtnl_lock_needed = rtw_rtnl_lock_needed(adapter_to_dvobj(adapter)); +#endif u8 res = _SUCCESS; /* check if allow software config */ - if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) { + if (rtw_rfctl_is_disable_sw_channel_plan(adapter_to_dvobj(adapter)) == _TRUE) { res = _FAIL; goto exit; } - /* if country_entry is provided, replace chplan */ - if (country_ent) + if (country_ent) { + /* if country_entry is provided, replace chplan */ chplan = country_ent->chplan; - - /* check input parameter */ - if (regd_src == REGD_SRC_RTK_PRIV && !rtw_is_channel_plan_valid(chplan)) { - res = _FAIL; - goto exit; + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = country_ent->chplan_6g; + #endif } /* prepare cmd parameter */ @@ -1866,8 +1837,27 @@ static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const str goto exit; } parm->regd_src = regd_src; - parm->country_ent = country_ent; + parm->inr = inr; + if (country_ent) { + _rtw_memcpy(&parm->country_ent, country_ent, sizeof(parm->country_ent)); + parm->has_country = 1; + } parm->channel_plan = chplan; +#if CONFIG_IEEE80211_BAND_6GHZ + parm->channel_plan_6g = chplan_6g; +#endif +#ifdef CONFIG_80211D + if (cisr) { + _rtw_memcpy(&parm->cisr, cisr, sizeof(*cisr)); + parm->has_cisr = 1; + } +#endif +#ifdef PLATFORM_LINUX + if (flags & (RTW_CMDF_DIRECTLY | RTW_CMDF_WAIT_ACK)) + parm->rtnl_lock_needed = rtnl_lock_needed; /* synchronous call, follow caller's */ + else + parm->rtnl_lock_needed = 1; /* asynchronous call, always needed */ +#endif if (flags & RTW_CMDF_DIRECTLY) { /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ @@ -1882,6 +1872,7 @@ static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const str rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_CHANPLAN); @@ -1894,10 +1885,10 @@ static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const str if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -1910,8 +1901,24 @@ static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const str goto exit; } parm->regd_src = regd_src; - parm->country_ent = country_ent; + parm->inr = inr; + if (country_ent) { + _rtw_memcpy(&parm->country_ent, country_ent, sizeof(parm->country_ent)); + parm->has_country = 1; + } parm->channel_plan = chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + parm->channel_plan_6g = chplan_6g; + #endif + #ifdef CONFIG_80211D + if (cisr) { + _rtw_memcpy(&parm->cisr, cisr, sizeof(*cisr)); + parm->has_cisr = 1; + } + #endif + #ifdef PLATFORM_LINUX + parm->rtnl_lock_needed = rtnl_lock_needed; /* synchronous call, follow caller's */ + #endif if (H2C_SUCCESS != rtw_set_chplan_hdl(adapter, (u8 *)parm)) res = _FAIL; @@ -1925,48 +1932,48 @@ static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const str return res; } -inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig) +inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 chplan_6g, enum rtw_regd_inr inr) { - return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, REGD_SRC_RTK_PRIV, swconfig); + return _rtw_set_chplan_cmd(adapter, flags, chplan, chplan_6g, NULL, REGD_SRC_RTK_PRIV, inr, NULL); } -inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig) +inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, enum rtw_regd_inr inr) { - const struct country_chplan *ent; - if ((is_alpha(country_code[0]) == _FALSE - || is_alpha(country_code[1]) == _FALSE) - && (strncmp(country_code, "00", 2) != 0) + struct country_chplan ent; + + if (IS_ALPHA2_WORLDWIDE(country_code)) { + rtw_get_chplan_worldwide(&ent); + goto cmd; + } + + if (is_alpha(country_code[0]) == _FALSE + || is_alpha(country_code[1]) == _FALSE ) { RTW_PRINT("%s input country_code is not alpha2\n", __func__); return _FAIL; } - ent = rtw_get_chplan_from_country(country_code); - - if (ent == NULL) { + if (!rtw_get_chplan_from_country(country_code, &ent)) { RTW_PRINT("%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]); return _FAIL; } - RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan); +cmd: + RTW_PRINT("%s country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]); - return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, REGD_SRC_RTK_PRIV, swconfig); + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, RTW_CHPLAN_6G_UNSPECIFIED, &ent, REGD_SRC_RTK_PRIV, inr, NULL); } #ifdef CONFIG_REGD_SRC_FROM_OS -inline u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region) +inline u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region, enum rtw_regd_inr inr) { - struct country_chplan *ent; - const struct country_chplan *rtk_ent; - - /* allocate entry for regd source out of driver */ - ent = rtw_malloc(sizeof(*ent)); - if (ent == NULL) - return _FAIL; + struct country_chplan ent; + struct country_chplan rtk_ent; + bool rtk_ent_exist; - rtk_ent = rtw_get_chplan_from_country(country_code); + rtk_ent_exist = rtw_get_chplan_from_country(country_code, &rtk_ent); - _rtw_memcpy(ent->alpha2, country_code, 2); + _rtw_memcpy(ent.alpha2, country_code, 2); /* * Regulation follows OS, the internal txpwr limit selection is searched by alpha2 @@ -1976,22 +1983,33 @@ inline u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country * 2. WW when driver has no support of this alpha2 */ - ent->chplan = rtk_ent ? rtk_ent->chplan : RTW_CHPLAN_UNSPECIFIED; - #ifdef CONFIG_80211AC_VHT - ent->en_11ac = 1; + ent.chplan = rtk_ent_exist ? rtk_ent.chplan : RTW_CHPLAN_UNSPECIFIED; + #if CONFIG_IEEE80211_BAND_6GHZ + ent.chplan_6g = rtk_ent_exist ? rtk_ent.chplan_6g : RTW_CHPLAN_6G_UNSPECIFIED; + #endif + ent.edcca_mode_2g_override = rtk_ent_exist ? rtk_ent.edcca_mode_2g_override : RTW_EDCCA_DEF; + #if CONFIG_IEEE80211_BAND_5GHZ + ent.edcca_mode_5g_override = rtk_ent_exist ? rtk_ent.edcca_mode_5g_override : RTW_EDCCA_DEF; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + ent.edcca_mode_6g_override = rtk_ent_exist ? rtk_ent.edcca_mode_6g_override : RTW_EDCCA_DEF; + #endif + ent.txpwr_lmt_override = rtk_ent_exist ? rtk_ent.txpwr_lmt_override : TXPWR_LMT_DEF; + #if defined(CONFIG_80211AC_VHT) || defined(CONFIG_80211AX_HE) + ent.proto_en = CHPLAN_PROTO_EN_ALL; #endif /* TODO: dfs_region */ - return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, REGD_SRC_OS, 1); + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, RTW_CHPLAN_6G_UNSPECIFIED, &ent, REGD_SRC_OS, inr, NULL); } #endif /* CONFIG_REGD_SRC_FROM_OS */ -u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **resp) +u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **chplan) { struct cmd_obj *cmdobj; struct get_channel_plan_param *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _FAIL; @@ -2002,7 +2020,7 @@ u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **res parm = rtw_zmalloc(sizeof(*parm)); if (parm == NULL) goto exit; - parm->resp = resp; + parm->chplan = chplan; if (flags & RTW_CMDF_DIRECTLY) { /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ @@ -2016,6 +2034,7 @@ u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **res rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_GET_CHANPLAN); @@ -2028,10 +2047,10 @@ u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **res if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -2041,7 +2060,7 @@ u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **res parm = rtw_zmalloc(sizeof(*parm)); if (parm == NULL) goto exit; - parm->resp = resp; + parm->chplan = chplan; if (H2C_SUCCESS == rtw_get_chplan_hdl(adapter, (u8 *)parm)) res = _SUCCESS; @@ -2054,23 +2073,35 @@ u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **res return res; } -u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed) +#ifdef CONFIG_80211D +inline u8 rtw_apply_recv_country_ie_cmd(_adapter *adapter, int flags, enum band_type band,u8 opch, const u8 *country_ie) { - struct cmd_obj *pcmdobj; - struct LedBlink_param *ledBlink_param; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct country_chplan ent; + struct country_ie_slave_record cisr; - u8 res = _SUCCESS; + rtw_get_chplan_from_recv_country_ie(adapter, band, opch, country_ie, &ent, &cisr, NULL); + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, RTW_CHPLAN_6G_UNSPECIFIED + , NULL, REGD_SRC_RTK_PRIV, RTW_REGD_SET_BY_COUNTRY_IE, &cisr); +} +#endif /* CONFIG_80211D */ +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD +u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed) +{ + struct cmd_obj *pcmdobj; + struct LedBlink_param *ledBlink_param; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u8 res = _SUCCESS; - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { res = _FAIL; goto exit; } + pcmdobj->padapter = padapter; - ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param)); + ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param)); if (ledBlink_param == NULL) { rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); res = _FAIL; @@ -2083,22 +2114,22 @@ u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed) res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); exit: - - return res; } +#endif /*CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD*/ u8 rtw_set_csa_cmd(_adapter *adapter) { struct cmd_obj *cmdobj; - struct cmd_priv *cmdpriv = &adapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + u8 res = _SUCCESS; cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); if (cmdobj == NULL) { res = _FAIL; goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_parm_rsp(cmdobj, CMD_SET_CHANSWITCH); res = rtw_enqueue_cmd(cmdpriv, cmdobj); @@ -2112,15 +2143,16 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) u8 res = _SUCCESS; #ifdef CONFIG_TDLS struct cmd_obj *pcmdobj; - struct TDLSoption_param *TDLSoption; + struct TDLSoption_param *TDLSoption; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { res = _FAIL; goto exit; } + pcmdobj->padapter = padapter; TDLSoption = (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param)); if (TDLSoption == NULL) { @@ -2143,72 +2175,6 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) return res; } -u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter) -{ - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; - - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - -exit: - return res; -} - -u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter) -{ - struct cmd_obj *cmdobj; - struct drvextra_cmd_parm *parm; - struct cmd_priv *cmdpriv = &adapter->cmdpriv; - u8 res = _SUCCESS; - - cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (cmdobj == NULL) { - res = _FAIL; - goto exit; - } - - parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (parm == NULL) { - rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; - } - - parm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID; - parm->type = 0; - parm->size = 0; - parm->pbuf = NULL; - - init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(cmdpriv, cmdobj); - -exit: - return res; -} u8 rtw_ssmps_wk_hdl(_adapter *adapter, struct ssmps_cmd_parm *ssmp_param) { u8 res = _SUCCESS; @@ -2230,8 +2196,8 @@ u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue struct cmd_obj *cmdobj; struct drvextra_cmd_parm *cmd_parm; struct ssmps_cmd_parm *ssmp_param; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + u8 res = _SUCCESS; if (enqueue) { cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); @@ -2239,6 +2205,7 @@ u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue res = _FAIL; goto exit; } + cmdobj->padapter = adapter; cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (cmd_parm == NULL) { @@ -2289,9 +2256,9 @@ u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer) u32 tx_tp_mbits, rx_tp_mbits; if (!MLME_IS_STA(adapter) || - !hal_is_mimo_support(adapter) || + !rtw_hw_is_mimo_support(adapter_to_dvobj(adapter)) || !pmlmeext->ssmps_en || - (pmlmeext->cur_channel > 14) + (pmlmeext->chandef.chan > 14) ) return enter_smps; @@ -2301,8 +2268,8 @@ u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer) rtw_warn_on(1); return enter_smps; } - - if (psta->cmn.mimo_type == RF_1T1R) + /*TODO*/ + if (psta->phl_sta->asoc_cap.nss_tx == 1) return enter_smps; tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10; @@ -2337,17 +2304,17 @@ u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer) } if (enter_smps) { - if (!from_timer && psta->cmn.sm_ps != SM_PS_STATIC) + if (!from_timer && psta->phl_sta->sm_ps != SM_PS_STATIC) rtw_ssmps_enter(adapter, psta); } else { - if (!from_timer && psta->cmn.sm_ps != SM_PS_DISABLE) + if (!from_timer && psta->phl_sta->sm_ps != SM_PS_DISABLE) rtw_ssmps_leave(adapter, psta); else { u8 ps_change = _FALSE; - if (enter_smps && psta->cmn.sm_ps != SM_PS_STATIC) + if (enter_smps && psta->phl_sta->sm_ps != SM_PS_STATIC) ps_change = _TRUE; - else if (!enter_smps && psta->cmn.sm_ps != SM_PS_DISABLE) + else if (!enter_smps && psta->phl_sta->sm_ps != SM_PS_DISABLE) ps_change = _TRUE; if (ps_change) @@ -2360,11 +2327,11 @@ u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer) #endif /*CONFIG_SUPPORT_STATIC_SMPS*/ #ifdef CONFIG_CTRL_TXSS_BY_TP -void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta) +void rtw_ctrl_txss_update(_adapter *adapter, struct sta_info *sta) { struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); - pmlmeext->txss_momi_type_bk = sta->cmn.mimo_type; + pmlmeext->txss_bk = sta->phl_sta->asoc_cap.nss_rx; } u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss) @@ -2376,26 +2343,37 @@ u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss) if (pmlmeext->txss_1ss == tx_1ss) return _FALSE; - - if (pwrpriv->bLeisurePs && pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + /* + if (pwrpriv->bLeisurePs && pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) { lps_changed = _TRUE; LPS_Leave(adapter, "LPS_CTRL_TXSS"); } + */ RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] set tx to %d ss\n", - ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), + ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr), (tx_1ss) ? 1 : rtw_get_sta_tx_nss(adapter, sta)); - /*ra re-registed*/ - sta->cmn.mimo_type = (tx_1ss) ? RF_1T1R : pmlmeext->txss_momi_type_bk; - rtw_phydm_ra_registed(adapter, sta); + /*update ra*/ + if (tx_1ss) + sta->phl_sta->asoc_cap.nss_rx = 1; + else + sta->phl_sta->asoc_cap.nss_rx = pmlmeext->txss_bk; + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(adapter)->phl, + sta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_DIRECTLY, + 0); /*configure trx mode*/ - rtw_phydm_trx_cfg(adapter, tx_1ss); + /*rtw_phydm_trx_cfg(adapter, tx_1ss);*/ pmlmeext->txss_1ss = tx_1ss; - + /* if (lps_changed) LPS_Enter(adapter, "LPS_CTRL_TXSS"); + */ return rst; } @@ -2413,7 +2391,7 @@ u8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 struct cmd_obj *cmdobj; struct drvextra_cmd_parm *cmd_parm; struct txss_cmd_parm *txss_param; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -2435,6 +2413,7 @@ u8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 res = _FAIL; goto exit; } + cmdobj->padapter = adapter; cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (cmd_parm == NULL) { @@ -2458,10 +2437,10 @@ u8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 res = rtw_enqueue_cmd(pcmdpriv, cmdobj); if (res == _SUCCESS && (flag & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -2481,7 +2460,7 @@ void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer) u32 tx_tp_mbits; if (!MLME_IS_STA(adapter) || - !hal_is_mimo_support(adapter) || + !rtw_hw_is_mimo_support(adapter_to_dvobj(adapter)) || !pmlmeext->txss_ctrl_en ) return; @@ -2527,7 +2506,7 @@ void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss) struct sta_info *psta; if (!MLME_IS_STA(adapter) || - !hal_is_mimo_support(adapter) + !rtw_hw_is_mimo_support(adapter_to_dvobj(adapter)) ) return; @@ -2784,12 +2763,12 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo; #endif -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC if (padapter->registrypriv.wifi_spec != 1) { BusyThresholdHigh = 25; BusyThresholdLow = 10; } else -#endif /* CONFIG_BT_COEXIST */ +#endif /* CONFIG_BTC */ { BusyThresholdHigh = 100; BusyThresholdLow = 75; @@ -2848,7 +2827,7 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_AUTOSETUP /* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */ - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) { + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_TDLS) == _TRUE) { if ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) { _rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN); issue_tdls_dis_req(padapter, &txmgmt); @@ -2886,11 +2865,12 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) session_tracker_chk_cmd(padapter, NULL); #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 - rtw_bf_update_traffic(padapter); -#endif /* RTW_BEAMFORMING_VERSION_2 */ -#endif /* CONFIG_BEAMFORMING */ - +#ifdef RTW_WKARD_TX_DISABLE_BFEE + /*For each padapter*/ + rtw_core_bf_watchdog(padapter); +#endif +#endif + pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; @@ -2905,7 +2885,7 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) } -#ifdef CONFIG_AP_MODE + /* for 11n Logo 4.2.31/4.2.32 */ static void dynamic_update_bcn_check(_adapter *padapter) { @@ -2932,8 +2912,8 @@ static void dynamic_update_bcn_check(_adapter *padapter) && _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) { if (rtw_ht_operation_update(padapter) > 0) { - update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); + rtw_update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); } } #endif /* CONFIG_80211N_HT */ @@ -2946,8 +2926,8 @@ static void dynamic_update_bcn_check(_adapter *padapter) && _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) { if (rtw_ht_operation_update(padapter) > 0) { - update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); + rtw_update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0); + rtw_update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0); } ATOMIC_SET(&pmlmepriv->olbc, _FALSE); @@ -2958,12 +2938,118 @@ static void dynamic_update_bcn_check(_adapter *padapter) count ++; } } -#endif /* CONFIG_AP_MODE */ + +struct turbo_edca_setting{ + u32 edca_ul; /* uplink, tx */ + u32 edca_dl; /* downlink, rx */ +}; + +#define TURBO_EDCA_ENT(UL, DL) {UL, DL} + +#define TURBO_EDCA_MODE_NUM 8 +static struct turbo_edca_setting ctrl_turbo_edca[TURBO_EDCA_MODE_NUM] = { + /* { UL, DL } */ + TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */ + + TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */ + + TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */ + + TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */ + + TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */ + + TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */ + + TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */ + + TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */ +}; + +void rtw_turbo_edca(_adapter *padapter) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + u32 edca_be_ul = padapter->last_edca; + u32 edca_be_dl = padapter->last_edca; + u32 ac_parm = padapter->last_edca; + u8 ac; + u8 is_linked = _FALSE; + + if (padapter->dis_turboedca == DIS_TURBO) + return; + + if (rtw_mi_check_status(padapter, MI_ASSOC)) + is_linked = _TRUE; + + if (is_linked != _TRUE) + return; + + if (pregpriv->wifi_spec == 1) + return; + + /* keep this condition at last check */ + if (padapter->dis_turboedca == DIS_TURBO_USE_MANUAL) { + if (padapter->edca_param_mode < TURBO_EDCA_MODE_NUM) { + + struct turbo_edca_setting param; + + param = ctrl_turbo_edca[padapter->edca_param_mode]; + edca_be_ul = param.edca_ul; + edca_be_dl = param.edca_dl; + } else { + edca_be_ul = padapter->edca_param_mode; + edca_be_dl = padapter->edca_param_mode; + } + } + + if (phl_com->phl_stats.tx_traffic.lvl == RTW_TFC_HIGH) + ac_parm = edca_be_ul; + else if (phl_com->phl_stats.tx_traffic.lvl != RTW_TFC_HIGH) + ac_parm = edca_be_dl; + else + return; + + if (padapter->last_edca != ac_parm) { + ac = 0; + /*RTW_INFO("%s, edca(0x%08x), lvl(%d), sts(%d)\n", __func__, ac_parm, + phl_com->phl_stats.tx_traffic.lvl, phl_com->phl_stats.tx_traffic.sts);*/ + rtw_hw_set_edca(padapter, ac, ac_parm); + padapter->last_edca = ac_parm; + } +} + +u32 rtw_get_turbo_edca(_adapter *padapter, u8 aifs, u8 ecwmin, u8 ecwmax, u8 txop) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + u32 ret = 0; + u8 decide_txop = txop; + u8 default_txop = 0x5e; + u32 ac_parm = padapter->last_edca; + u8 ac = 0;/*BE*/ + + if (padapter->dis_turboedca == DIS_TURBO) + return ret; + + if (pregpriv->wifi_spec == 1) + return ret; + + if (default_txop > txop) + decide_txop = default_txop; + else + decide_txop = txop; + + ac_parm = aifs | (ecwmin << 8) | (ecwmax << 12) | (decide_txop << 16); + + return ac_parm; + +} void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) { - #ifdef CONFIG_AP_MODE #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { expire_timeout_chk(padapter); #ifdef CONFIG_RTW_MESH @@ -2971,14 +3057,13 @@ void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) rtw_mesh_peer_status_chk(padapter); #endif } + #endif #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - dynamic_update_bcn_check(padapter); - #endif /* CONFIG_AP_MODE */ - linked_status_chk(padapter, 0); traffic_status_watchdog(padapter, 0); + rtw_turbo_edca(padapter); /* for debug purpose */ _linked_info_dump(padapter); @@ -2989,55 +3074,77 @@ void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) } + void rtw_dynamic_chk_wk_hdl(_adapter *padapter) { rtw_mi_dynamic_chk_wk_hdl(padapter); -#ifdef CONFIG_MP_INCLUDED - if (rtw_mp_mode_check(padapter) == _FALSE) -#endif - { + #ifdef DBG_CONFIG_ERROR_DETECT - rtw_hal_sreset_xmit_status_check(padapter); - rtw_hal_sreset_linked_status_check(padapter); + rtw_hal_sreset_xmit_status_check(padapter); + rtw_hal_sreset_linked_status_check(padapter); #endif - } /* if(check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY)==_FALSE) */ { #ifdef DBG_RX_COUNTER_DUMP rtw_dump_rx_counters(padapter); #endif - dm_DynamicUsbTxAgg(padapter, 0); } - rtw_hal_dm_watchdog(padapter); - /* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */ +#ifdef CONFIG_RTW_MULTI_AP + rtw_ch_util_rpt(padapter); +#endif + +#ifdef CONFIG_DFS_MASTER + rtw_chset_chk_non_ocp_finish(adapter_to_rfctl(padapter)); +#endif -#ifdef CONFIG_BT_COEXIST - /* BT-Coexist */ - rtw_btcoex_Handler(padapter); +#ifdef CONFIG_IPS_CHECK_IN_WD + /* always call rtw_ps_processor() at last one. */ + rtw_ps_processor(padapter); #endif +} +void rtw_dynamic_chk_wk_sw_hdl(_adapter *padapter) +{ #ifdef CONFIG_RTW_MULTI_AP rtw_ch_util_rpt(padapter); #endif + rtw_update_phl_edcca_mode(padapter); + #ifdef CONFIG_DFS_MASTER rtw_chset_chk_non_ocp_finish(adapter_to_rfctl(padapter)); #endif +} + +void rtw_dynamic_chk_wk_hw_hdl(_adapter *padapter) +{ + rtw_mi_dynamic_chk_wk_hdl(padapter); + +#ifdef DBG_CONFIG_ERROR_DETECT + rtw_hal_sreset_xmit_status_check(padapter); + rtw_hal_sreset_linked_status_check(padapter); +#endif + + /* if(check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY)==_FALSE) */ + { +#ifdef DBG_RX_COUNTER_DUMP + rtw_dump_rx_counters(padapter); +#endif + } #ifdef CONFIG_IPS_CHECK_IN_WD /* always call rtw_ps_processor() at last one. */ rtw_ps_processor(padapter); #endif -#ifdef CONFIG_MCC_MODE - rtw_hal_mcc_sw_status_check(padapter); -#endif /* CONFIG_MCC_MODE */ - - rtw_hal_periodic_tsf_update_chk(padapter); +#ifdef RTW_DETECT_HANG + rtw_is_hang_check(padapter); +#endif } + #ifdef CONFIG_LPS struct lps_ctrl_wk_parm { s8 lps_level; @@ -3060,9 +3167,6 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type, u8 *buf) switch (lps_ctrl_type) { case LPS_CTRL_SCAN: /* RTW_INFO("LPS_CTRL_SCAN\n"); */ -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_ScanNotify(padapter, _TRUE); -#endif /* CONFIG_BT_COEXIST */ if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { /* connect */ LPS_Leave(padapter, "LPS_CTRL_SCAN"); @@ -3078,25 +3182,16 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type, u8 *buf) /* Reset LPS Setting */ pwrpriv->LpsIdleCount = 0; rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_MediaStatusNotify(padapter, mstatus); -#endif /* CONFIG_BT_COEXIST */ break; case LPS_CTRL_DISCONNECT: /* RTW_INFO("LPS_CTRL_DISCONNECT\n"); */ mstatus = 0;/* disconnect */ -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_MediaStatusNotify(padapter, mstatus); -#endif /* CONFIG_BT_COEXIST */ LPS_Leave(padapter, "LPS_CTRL_DISCONNECT"); rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); break; case LPS_CTRL_SPECIAL_PACKET: /* RTW_INFO("LPS_CTRL_SPECIAL_PACKET\n"); */ rtw_set_lps_deny(padapter, LPS_DELAY_MS); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP); -#endif /* CONFIG_BT_COEXIST */ LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET"); break; case LPS_CTRL_LEAVE: @@ -3139,7 +3234,7 @@ static u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; struct lps_ctrl_wk_parm *wk_parm = NULL; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -3183,6 +3278,7 @@ static u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level res = _FAIL; goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); @@ -3195,10 +3291,10 @@ static u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -3232,21 +3328,22 @@ void rtw_dm_in_lps_hdl(_adapter *padapter) u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -3256,14 +3353,12 @@ u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter) pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: - return res; - } void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) @@ -3273,11 +3368,6 @@ void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) if (dtim <= 0 || dtim > 16) return; -#ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) - return; -#endif - #ifdef CONFIG_LPS_LCLK _enter_pwrlock(&pwrpriv->lock); #endif @@ -3289,12 +3379,12 @@ void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) pwrpriv->dtim = dtim; } - if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) { + if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PM_PS_MODE_ACTIVE)) { u8 ps_mode = pwrpriv->pwr_mode; /* RTW_INFO("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); */ - rtw_exec_lps(padapter, ps_mode); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); } #ifdef CONFIG_LPS_LCLK @@ -3307,10 +3397,10 @@ void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u8 res = _SUCCESS; /* #ifdef CONFIG_CONCURRENT_MODE if (padapter->hw_port != HW_PORT0) @@ -3318,15 +3408,16 @@ u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim) #endif */ { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -3336,404 +3427,254 @@ u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim) pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); } - exit: - return res; - } -#if (RATE_ADAPTIVE_SUPPORT == 1) -void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime) + +#ifdef CONFIG_POWER_SAVING +void power_saving_wk_hdl(_adapter *padapter) { - rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime)); + rtw_ps_processor(padapter); } - -u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime) +#endif +/* add for CONFIG_IEEE80211W, none 11w can use it */ +void reset_securitypriv_hdl(_adapter *padapter) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + rtw_reset_securitypriv(padapter); +} - u8 res = _SUCCESS; +#ifdef CONFIG_IOCTL_CFG80211 +#if 0 /*!CONFIG_PHL_ARCH*/ +static u8 _p2p_roch_cmd(_adapter *adapter + , u64 cookie, struct wireless_dev *wdev + , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type + , unsigned int duration + , u8 flags +) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct p2p_roch_parm *roch_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + struct submit_ctx sctx; + u8 cancel = duration ? 0 : 1; + u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + roch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm)); + if (roch_parm == NULL) { res = _FAIL; goto exit; } - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; + roch_parm->cookie = cookie; + roch_parm->wdev = wdev; + if (!cancel) { + _rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel)); + roch_parm->ch_type = ch_type; + roch_parm->duration = duration; } - pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID; - pdrvextra_cmd_parm->type = minRptTime; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); -exit: + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm)) + res = _FAIL; + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + res = _FAIL; + goto exit; + } + parm->ec_id = P2P_PROTO_WK_CID; + parm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK; + parm->size = sizeof(*roch_parm); + parm->pbuf = (u8 *)roch_parm; - return res; + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + cmdobj->padapter = adapter; -} + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); -#endif + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } -#ifdef CONFIG_ANTENNA_DIVERSITY -void antenna_select_wk_hdl(_adapter *padapter, u8 antenna) -{ - rtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE); + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; } +#endif /*!CONFIG_PHL_ARCH*/ -u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue) +inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - u8 bSupportAntDiv = _FALSE; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct mgnt_tx_parm *mgnt_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + struct submit_ctx sctx; u8 res = _SUCCESS; - int i; - - rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); - if (_FALSE == bSupportAntDiv) - return _FAIL; - for (i = 0; i < dvobj->iface_nums; i++) { - if (rtw_linked_check(dvobj->padapters[i])) - return _FAIL; + mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm)); + if (mgnt_parm == NULL) { + res = _FAIL; + goto exit; } - if (_TRUE == enqueue) { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + mgnt_parm->tx_ch = tx_ch; + mgnt_parm->no_cck = no_cck; + mgnt_parm->buf = buf; + mgnt_parm->len = len; + mgnt_parm->wait_ack = wait_ack; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm)) + res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); res = _FAIL; goto exit; } - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + parm->ec_id = MGNT_TX_WK_CID; + parm->type = 0; + parm->size = sizeof(*mgnt_parm); + parm->pbuf = (u8 *)mgnt_parm; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; - pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID; - pdrvextra_cmd_parm->type = antenna; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - } else - antenna_select_wk_hdl(padapter, antenna); -exit: + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); - return res; + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } +exit: + return res; } #endif -void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta) +#ifdef CONFIG_POWER_SAVING +u8 rtw_ps_cmd(_adapter *padapter) { - if (psta) - set_sta_rate(padapter, psta); -} + struct cmd_obj *ppscmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; -u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta) -{ - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; +#ifdef CONFIG_CONCURRENT_MODE + if (!is_primary_adapter(padapter)) + goto exit; +#endif - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ppscmd == NULL) { res = _FAIL; goto exit; } + ppscmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } - pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID; + pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; pdrvextra_cmd_parm->type = 0; pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = psta; - - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + res = rtw_enqueue_cmd(pcmdpriv, ppscmd); exit: - - return res; - -} - -void power_saving_wk_hdl(_adapter *padapter) -{ - rtw_ps_processor(padapter); -} - -/* add for CONFIG_IEEE80211W, none 11w can use it */ -void reset_securitypriv_hdl(_adapter *padapter) -{ - rtw_reset_securitypriv(padapter); -} - -#ifdef CONFIG_P2P -u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType) -{ - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return res; - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID; - pdrvextra_cmd_parm->type = intCmdType; /* As the command tppe. */ - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; /* Must be NULL here */ - - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - -exit: - - - return res; - -} -#endif /* CONFIG_P2P */ - -#ifdef CONFIG_IOCTL_CFG80211 -static struct rtw_roch_parm *rtw_alloc_roch_parm(_adapter *adapter - , u64 cookie, struct wireless_dev *wdev - , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type - , unsigned int duration - , u8 flags -) -{ - struct rtw_roch_parm *roch_parm; - bool cancel = duration ? 0 : 1; - - roch_parm = (struct rtw_roch_parm *)rtw_zmalloc(sizeof(struct rtw_roch_parm)); - if (!roch_parm) - return NULL; - - roch_parm->cookie = cookie; - roch_parm->wdev = wdev; - if (!cancel) { - _rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel)); - roch_parm->ch_type = ch_type; - roch_parm->duration = duration; - } - - return roch_parm; -} - -inline u8 rtw_roch_cmd(_adapter *adapter - , u64 cookie, struct wireless_dev *wdev - , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type - , unsigned int duration - , u8 flags -) -{ - struct rtw_roch_parm *roch_parm; - - roch_parm = rtw_alloc_roch_parm(adapter, cookie, wdev, ch, ch_type, duration, flags); - if (!roch_parm) - return _FAIL; - - return rtw_roch_wk_cmd(adapter, ROCH_RO_CH_WK, roch_parm, flags); -} - -inline u8 rtw_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags) -{ - struct rtw_roch_parm *roch_parm; - - roch_parm = rtw_alloc_roch_parm(adapter, cookie, wdev, NULL, 0, 0, flags); - if (!roch_parm) - return _FAIL; - - return rtw_roch_wk_cmd(adapter, ROCH_CANCEL_RO_CH_WK, roch_parm, flags); -} - -inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags) -{ - struct cmd_obj *cmdobj; - struct drvextra_cmd_parm *parm; - struct mgnt_tx_parm *mgnt_parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; - struct submit_ctx sctx; - u8 res = _SUCCESS; - - mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm)); - if (mgnt_parm == NULL) { - res = _FAIL; - goto exit; - } - - mgnt_parm->tx_ch = tx_ch; - mgnt_parm->no_cck = no_cck; - mgnt_parm->buf = buf; - mgnt_parm->len = len; - mgnt_parm->wait_ack = wait_ack; - - if (flags & RTW_CMDF_DIRECTLY) { - /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ - if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm)) - res = _FAIL; - rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); - } else { - /* need enqueue, prepare cmd_obj and enqueue */ - parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (parm == NULL) { - rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); - res = _FAIL; - goto exit; - } - - parm->ec_id = MGNT_TX_WK_CID; - parm->type = 0; - parm->size = sizeof(*mgnt_parm); - parm->pbuf = (u8 *)mgnt_parm; - - cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); - if (cmdobj == NULL) { - res = _FAIL; - rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); - rtw_mfree((u8 *)parm, sizeof(*parm)); - goto exit; - } - - init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); - - if (flags & RTW_CMDF_WAIT_ACK) { - cmdobj->sctx = &sctx; - rtw_sctx_init(&sctx, 10 * 1000); - } - - res = rtw_enqueue_cmd(pcmdpriv, cmdobj); - - if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { - rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); - if (sctx.status == RTW_SCTX_SUBMITTED) - cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); - if (sctx.status != RTW_SCTX_DONE_SUCCESS) - res = _FAIL; - } - } - -exit: - return res; -} -#endif - -u8 rtw_ps_cmd(_adapter *padapter) -{ - struct cmd_obj *ppscmd; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - - u8 res = _SUCCESS; - -#ifdef CONFIG_CONCURRENT_MODE - if (!is_primary_adapter(padapter)) - goto exit; -#endif - - ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ppscmd == NULL) { - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - - res = rtw_enqueue_cmd(pcmdpriv, ppscmd); - -exit: - - return res; - } +#endif /*CONFIG_POWER_SAVING*/ #if CONFIG_DFS -void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj) +void rtw_dfs_ch_switch_hdl(_adapter *adapter) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); - _adapter *pri_adapter = dvobj_get_primary_adapter(dvobj); - struct mlme_ext_priv *pmlmeext = &pri_adapter->mlmeextpriv; - u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter); - u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(adapter); + u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(adapter); s16 req_ch; - u8 req_bw = CHANNEL_WIDTH_20, req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 req_bw = CHANNEL_WIDTH_20, req_offset = CHAN_OFFSET_NO_EXT, csa_timer = _FALSE; + u8 need_discon = _FALSE; - rtw_hal_macid_sleep_all_used(pri_adapter); + rtw_hal_macid_sleep_all_used(adapter); - if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0 - && !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch) + if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_chandef.chan) >= 0 + && !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_chandef.chan) ) { /* CSA channel available and valid */ - req_ch = rfctl->csa_ch; - RTW_INFO("%s valid CSA ch%u\n", __func__, rfctl->csa_ch); + req_ch = rfctl->csa_chandef.chan; + RTW_INFO("CSA : %s valid CSA ch%u\n", __func__, rfctl->csa_chandef.chan); + csa_timer = _TRUE; } else if (ifbmp_m) { /* no available or valid CSA channel, having AP/MESH ifaces */ req_ch = REQ_CH_NONE; - RTW_INFO("%s ch sel by AP/MESH ifaces\n", __func__); + need_discon = _TRUE; + RTW_INFO("CSA : %s ch sel by AP/MESH ifaces\n", __func__); } else { /* no available or valid CSA channel and no AP/MESH ifaces */ - if (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode) + if (!is_supported_24g(dvobj_to_regsty(dvobj)->band_type) #ifdef CONFIG_DFS_MASTER || rfctl->radar_detected #endif @@ -3741,32 +3682,33 @@ void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj) req_ch = 36; else req_ch = 1; - RTW_INFO("%s switch to ch%d\n", __func__, req_ch); + need_discon = _TRUE; + RTW_INFO("CSA : %s switch to ch%d\n", __func__, req_ch); } - /* only support 80 Mhz so far */ - if(rfctl->csa_ch_width == 1 || rfctl->csa_ch_width == 2 || rfctl->csa_ch_width == 3) { - if (rtw_get_offset_by_chbw(req_ch, CHANNEL_WIDTH_80, &req_offset)) { + if (!need_discon) { + if (rfctl->csa_ch_width == 1) { req_bw = CHANNEL_WIDTH_80; + req_offset = rfctl->csa_chandef.offset; + } else if (rfctl->csa_ch_width == 0 && rfctl->csa_chandef.offset != CHAN_OFFSET_NO_EXT) { + req_bw = CHANNEL_WIDTH_40; + req_offset = rfctl->csa_chandef.offset; } else { req_bw = CHANNEL_WIDTH_20; - req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + req_offset = CHAN_OFFSET_NO_EXT; + } + + /* get correct offset and check ch/bw/offset is valid or not */ + if (!rtw_get_offset_by_chbw(req_ch, req_bw, &req_offset)) { + req_bw = CHANNEL_WIDTH_20; + req_offset = CHAN_OFFSET_NO_EXT; } - } else if(rfctl->csa_ch_offset == 1) { - req_bw = CHANNEL_WIDTH_40; - req_offset = HAL_PRIME_CHNL_OFFSET_LOWER; - } else if(rfctl->csa_ch_offset == 3) { - req_bw = CHANNEL_WIDTH_40; - req_offset = HAL_PRIME_CHNL_OFFSET_UPPER; - } else{ - req_bw = CHANNEL_WIDTH_20; - req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; } - RTW_INFO("req_ch=%d, req_bw=%d, req_offset=%d, ifbmp_m=0x%02x, ifbmp_s=0x%02x\n" + RTW_INFO("CSA : req_ch=%d, req_bw=%d, req_offset=%d, ifbmp_m=0x%02x, ifbmp_s=0x%02x\n" , req_ch, req_bw, req_offset, ifbmp_m, ifbmp_s); - /* update ch, bw, offset for all asoc STA ifaces */ + /* check all STA ifaces status */ if (ifbmp_s) { _adapter *iface; int i; @@ -3775,19 +3717,33 @@ void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj) iface = dvobj->padapters[i]; if (!iface || !(ifbmp_s & BIT(iface->iface_id))) continue; - - /* update STA mode ch/bw/offset */ - iface->mlmeextpriv.cur_channel = req_ch; - iface->mlmeextpriv.cur_bwmode = req_bw; - iface->mlmeextpriv.cur_ch_offset = req_offset; - /* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */ - iface->mlmepriv.cur_network.network.Configuration.DSConfig = req_ch; - set_fwstate(&iface->mlmepriv, WIFI_CSA_UPDATE_BEACON); - + + if (need_discon) { + set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING); + issue_deauth(iface, get_bssid(&iface->mlmepriv), WLAN_REASON_DEAUTH_LEAVING); + } else { + /* update STA mode ch/bw/offset */ + iface->mlmeextpriv.chandef.chan= req_ch; + iface->mlmeextpriv.chandef.bw = req_bw; + iface->mlmeextpriv.chandef.offset = req_offset; + /* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */ + iface->mlmepriv.cur_network.network.Configuration.DSConfig = req_ch; + set_fwstate(&iface->mlmepriv, WIFI_CSA_UPDATE_BEACON); + + #ifdef CONFIG_80211D + if (iface->mlmepriv.recv_country_ie) { + if (rtw_apply_recv_country_ie_cmd(iface, RTW_CMDF_DIRECTLY + , req_ch > 14 ? BAND_ON_5G : BAND_ON_24G, req_ch + , iface->mlmepriv.recv_country_ie) != _SUCCESS + ) + RTW_WARN(FUNC_ADPT_FMT" rtw_apply_recv_country_ie_cmd() fail\n", FUNC_ADPT_ARG(iface)); + } + #endif + } } } - if (rfctl->csa_ch > 0) { + if (csa_timer) { RTW_INFO("pmlmeext->csa_timer 70 seconds\n"); /* wait 70 seconds for receiving beacons */ _set_timer(&pmlmeext->csa_timer, CAC_TIME_MS + 10000); @@ -3795,33 +3751,53 @@ void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj) #ifdef CONFIG_AP_MODE if (ifbmp_m) { + u8 execlude = 0; + + if (need_discon) + execlude = ifbmp_s; /* trigger channel selection with consideraton of asoc STA ifaces */ rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY - , ifbmp_m, 0, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE); + , ifbmp_m, execlude, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE); } else #endif { /* no AP/MESH iface, switch DFS status and channel directly */ rtw_warn_on(req_ch <= 0); #ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, 0); + if (need_discon) + rtw_dfs_rd_en_decision(adapter, MLME_OPCH_SWITCH, ifbmp_s); + else + rtw_dfs_rd_en_decision(adapter, MLME_OPCH_SWITCH, 0); #endif - LeaveAllPowerSaveModeDirect(pri_adapter); - set_channel_bwmode(pri_adapter, req_ch, req_offset, req_bw); + + set_channel_bwmode(adapter, req_ch, req_offset, req_bw, _TRUE); /* update union ch/bw/offset for STA only */ - rtw_mi_update_union_chan_inf(pri_adapter, req_ch, req_offset, req_bw); + rtw_mi_update_union_chan_inf(adapter, req_ch, req_offset, req_bw); rtw_rfctl_update_op_mode(rfctl, 0, 0); } - - rfctl->csa_ch = 0; - rfctl->csa_switch_cnt = 0; - rfctl->csa_ch_offset = 0; - rfctl->csa_ch_width = 0; - rfctl->csa_ch_freq_seg0 = 0; - rfctl->csa_ch_freq_seg1 = 0; - rtw_hal_macid_wakeup_all_used(pri_adapter); - rtw_mi_os_xmit_schedule(pri_adapter); + /* make asoc STA ifaces disconnect */ + if (ifbmp_s && need_discon) { + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface || !(ifbmp_s & BIT(iface->iface_id))) + continue; + rtw_disassoc_cmd(iface, 0, RTW_CMDF_DIRECTLY); + rtw_indicate_disconnect(iface, 0, _FALSE); + #ifndef CONFIG_STA_CMD_DISPR + rtw_free_assoc_resources(iface, _TRUE); + #endif + rtw_free_network_queue(iface, _TRUE); + } + } + + reset_csa_param(rfctl); + + rtw_hal_macid_wakeup_all_used(adapter); + rtw_mi_os_xmit_schedule(adapter); } #endif /* CONFIG_DFS */ @@ -3866,20 +3842,21 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter) u8 rtw_chk_hi_queue_cmd(_adapter *padapter) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -3889,12 +3866,11 @@ u8 rtw_chk_hi_queue_cmd(_adapter *padapter) pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: - return res; } @@ -3904,6 +3880,7 @@ u8 rtw_dfs_rd_hdl(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 open_chan; u8 cch; if (!rfctl->radar_detect_enabled) @@ -3911,7 +3888,8 @@ u8 rtw_dfs_rd_hdl(_adapter *adapter) cch = rtw_get_center_ch(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); - if (dvobj->oper_channel != rfctl->radar_detect_ch + open_chan = rtw_get_oper_ch(adapter); + if (open_chan != rfctl->radar_detect_ch || rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300 ) { /* offchannel, bypass radar detect */ @@ -3951,7 +3929,7 @@ u8 rtw_dfs_rd_hdl(_adapter *adapter) rtw_nlrtw_cac_abort_event(adapter, cch, rfctl->radar_detect_bw); rtw_nlrtw_radar_detect_event(adapter, cch, rfctl->radar_detect_bw); - rtw_dfs_ch_switch_hdl(dvobj); + rtw_dfs_ch_switch_hdl(adapter); if (rfctl->radar_detect_enabled) goto set_timer; @@ -3971,23 +3949,16 @@ u8 rtw_dfs_rd_hdl(_adapter *adapter) rtw_nlrtw_cac_finish_event(adapter, cch, rfctl->radar_detect_bw); if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) { - u8 doiqk = _TRUE; + u8 do_rfk = _TRUE; u8 u_ch, u_bw, u_offset; - rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); - if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) - set_channel_bwmode(adapter, u_ch, u_offset, u_bw); + set_channel_bwmode(adapter, u_ch, u_offset, u_bw, do_rfk); else rtw_warn_on(1); - doiqk = _FALSE; - rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); - - #ifdef CONFIG_AP_MODE - ResumeTxBeacon(adapter); + rtw_hal_set_hwreg(adapter, HW_VAR_RESUME_BCN, NULL); rtw_mi_tx_beacon_hdl(adapter); - #endif } } @@ -4003,13 +3974,14 @@ u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue) { struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 res = _FAIL; if (enqueue) { cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); if (cmdobj == NULL) goto exit; + cmdobj->padapter = adapter; parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (parm == NULL) { @@ -4061,7 +4033,7 @@ static void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, b rfctl->radar_detected = 0; if (IS_CH_WAITING(rfctl)) - StopTxBeacon(adapter); + rtw_hal_set_hwreg(adapter, HW_VAR_STOP_BCN, NULL); if (!rfctl->radar_detect_enabled) { RTW_INFO("%s set radar_detect_enabled\n", __func__); @@ -4103,7 +4075,7 @@ static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, _cancel_timer_ex(&rfctl->radar_detect_timer); if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) { - ResumeTxBeacon(adapter); + rtw_hal_set_hwreg(adapter, HW_VAR_RESUME_BCN, NULL); rtw_mi_tx_beacon_hdl(adapter); } @@ -4119,10 +4091,6 @@ static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, rfctl->radar_detect_ch = ch; rfctl->radar_detect_bw = bw; rfctl->radar_detect_offset = offset; - } else { - rfctl->radar_detect_ch = 0; - rfctl->radar_detect_bw = 0; - rfctl->radar_detect_offset = 0; } } @@ -4181,19 +4149,19 @@ void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp) if (sync_ch == _TRUE) { if (!MLME_IS_OPCH_SW(adapter)) { - if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) { + if (!rtw_is_chbw_grouped(mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset, u_ch, u_bw, u_offset)) { RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter) - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset); + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset, u_ch, u_bw, u_offset); goto apply; } - rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + rtw_sync_chbw(&mlmeext->chandef.chan, (u8 *)(&mlmeext->chandef.bw), (u8 *)(&mlmeext->chandef.offset) , &u_ch, &u_bw, &u_offset); } } else { - u_ch = mlmeext->cur_channel; - u_bw = mlmeext->cur_bwmode; - u_offset = mlmeext->cur_ch_offset; + u_ch = mlmeext->chandef.chan; + u_bw = mlmeext->chandef.bw; + u_offset = mlmeext->chandef.offset; } } @@ -4242,13 +4210,15 @@ u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter) { struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 res = _FAIL; cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); if (cmdobj == NULL) goto exit; + cmdobj->padapter = adapter; + parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (parm == NULL) { rtw_mfree(cmdobj, sizeof(struct cmd_obj)); @@ -4270,207 +4240,1367 @@ u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter) #endif /* CONFIG_AP_MODE */ -#ifdef CONFIG_BT_COEXIST -struct btinfo { - u8 cid; - u8 len; - - u8 bConnection:1; - u8 bSCOeSCO:1; - u8 bInQPage:1; - u8 bACLBusy:1; - u8 bSCOBusy:1; - u8 bHID:1; - u8 bA2DP:1; - u8 bFTP:1; - - u8 retry_cnt:4; - u8 rsvd_34:1; - u8 rsvd_35:1; - u8 rsvd_36:1; - u8 rsvd_37:1; - - u8 rssi; - - u8 rsvd_50:1; - u8 rsvd_51:1; - u8 rsvd_52:1; - u8 rsvd_53:1; - u8 rsvd_54:1; - u8 rsvd_55:1; - u8 eSCO_SCO:1; - u8 Master_Slave:1; - - u8 rsvd_6; - u8 rsvd_7; +#if 0 /*def RTW_PHL_DBG_CMD*/ + +u8 sample_txwd[] = +{ +/*dword 00*/ 0x80, 0x00, 0x40, 0x00, +/*dword 01*/ 0x00, 0x00, 0x00, 0x00, +/*dword 02*/ 0xF2, 0x05, 0x00, 0x00, +/*dword 03*/ 0x3E, 0x11, 0x00, 0x00, +/*dword 04*/ 0x00, 0x00, 0x00, 0x00, +/*dword 05*/ 0x00, 0x00, 0x00, 0x00, +/*dword 06*/ 0x00, 0x07, 0x9B, 0x63, +/*dword 07*/ 0x3F, 0x00, 0x00, 0x00, +/*dword 08*/ 0x00, 0x00, 0x00, 0x00, +/*dword 09*/ 0x00, 0x00, 0x00, 0x00, +/*dword 10*/ 0x0C, 0x00, 0x00, 0x00, +/*dword 11*/ 0x00, 0x00, 0x00, 0x00, }; -void btinfo_evt_dump(void *sel, void *buf) -{ - struct btinfo *info = (struct btinfo *)buf; - - RTW_PRINT_SEL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len); +#define WD_SPEC(_name, _idx_dw, _bit_start, _bit_end) { \ + .name = (_name), \ + .idx_dw = (_idx_dw), \ + .bit_start = (_bit_start), \ + .bit_end = (_bit_end) \ +} - if (info->len > 2) - RTW_PRINT_SEL(sel, "byte2:%s%s%s%s%s%s%s%s\n" - , info->bConnection ? "bConnection " : "" - , info->bSCOeSCO ? "bSCOeSCO " : "" - , info->bInQPage ? "bInQPage " : "" - , info->bACLBusy ? "bACLBusy " : "" - , info->bSCOBusy ? "bSCOBusy " : "" - , info->bHID ? "bHID " : "" - , info->bA2DP ? "bA2DP " : "" - , info->bFTP ? "bFTP" : "" - ); +struct parse_wd { + char name[32]; + u8 idx_dw; + u8 bit_start; + u8 bit_end; +}; - if (info->len > 3) - RTW_PRINT_SEL(sel, "retry_cnt:%u\n", info->retry_cnt); +#define MAX_PHL_CMD_LEN 200 +#define MAX_PHL_CMD_NUM 10 +#define MAX_PHL_CMD_STR_LEN 200 + +char *get_next_para_str(char *para) +{ + return (para+MAX_PHL_CMD_STR_LEN); +} + +static struct parse_wd parse_txwd_8852ae_full[] = { + WD_SPEC("EN_HWSEQ_MODE" , 0, 0, 1), + WD_SPEC("HW_SSN_SEL" , 0, 2, 3), + WD_SPEC("SMH_EN" , 0, 4, 4), + WD_SPEC("HWAMSDU" , 0, 5, 5), + WD_SPEC("HW_AES_IV" , 0, 6, 6), + WD_SPEC("WD page" , 0, 7, 7), + WD_SPEC("CHK_EN" , 0, 8, 8), + WD_SPEC("WP_INT" , 0, 9, 9), + WD_SPEC("STF mode" , 0, 10, 10), + WD_SPEC("HEADERwLLC_LEN" , 0, 11, 15), + WD_SPEC("CHANNEL_DMA" , 0, 16, 19), + WD_SPEC("FW_download" , 0, 20, 20), + WD_SPEC("PKT_OFFSET" , 0, 21, 21), + WD_SPEC("WDINFO_EN" , 0, 22, 22), + WD_SPEC("MOREDATA" , 0, 23, 23), + WD_SPEC("WP_OFFSET" , 0, 24, 31), + + WD_SPEC("SHCUT_CAMID" , 1, 0, 7), + WD_SPEC("DMA_TXAGG_NUM" , 1, 8, 15), + WD_SPEC("PLD(Packet ID)" , 1, 16, 31), + + WD_SPEC("TXPKTSIZE" , 2, 0, 13), + WD_SPEC("RU_TC" , 2, 14, 16), + WD_SPEC("QSEL" , 2, 17, 22), + WD_SPEC("TID_indicate" , 2, 23, 23), + WD_SPEC("MACID" , 2, 24, 30), + WD_SPEC("RSVD" , 2, 31, 31), + + WD_SPEC("Wifi_SEQ" , 3, 0, 11), + WD_SPEC("AGG_EN" , 3, 12, 12), + WD_SPEC("BK" , 3, 13, 13), + WD_SPEC("RTS_TC" , 3, 14, 19), + WD_SPEC("DATA_TC" , 3, 20, 25), + WD_SPEC("MU_2nd_TC" , 3, 26, 28), + WD_SPEC("MU_TC" , 3, 29, 31), + + WD_SPEC("TIMESTAMP" , 4, 0, 15), + WD_SPEC("AES_IV_L" , 4, 16, 31), + + WD_SPEC("AES_IV_H" , 5, 0, 31), + + WD_SPEC("MBSSID" , 6, 0, 3), + WD_SPEC("Multiport_ID" , 6, 4, 6), + WD_SPEC("RSVD" , 6, 7, 7), + WD_SPEC("DATA_BW_ER" , 6, 8, 8), + WD_SPEC("DISRTSFB" , 6, 9, 9), + WD_SPEC("DISDATAFB" , 6, 10, 10), + WD_SPEC("DATA_LDPC" , 6, 11, 11), + WD_SPEC("DATA_STBC" , 6, 12, 13), + WD_SPEC("DATA_DCM" , 6, 14, 14), + WD_SPEC("DATA_ER" , 6, 15, 15), + WD_SPEC("DataRate" , 6, 16, 24), + WD_SPEC("GI_LTF" , 6, 25, 27), + WD_SPEC("DATA_BW" , 6, 28, 29), + WD_SPEC("USERATE_SEL" , 6, 30, 30), + WD_SPEC("ACK_CH_INFO" , 6, 31, 31), + + WD_SPEC("MAX_AGG_NUM" , 7, 0, 7), + WD_SPEC("BCN_SRCH_SEQ" , 7, 8, 9), + WD_SPEC("NAVUSEHDR" , 7, 10, 10), + WD_SPEC("BMC" , 7, 11, 11), + WD_SPEC("A_CTRL_BQR" , 7, 12, 12), + WD_SPEC("A_CTRL_UPH" , 7, 13, 13), + WD_SPEC("A_CTRL_BSR" , 7, 14, 14), + WD_SPEC("A_CTRL_CAS" , 7, 15, 15), + WD_SPEC("DATA_RTY_LOWEST_RATE" , 7, 16, 24), + WD_SPEC("DATA_TXCNT_LMT" , 7, 25, 30), + WD_SPEC("DATA_TXCNT_LMT_SEL" , 7, 31, 31), + + WD_SPEC("SEC_CAM_IDX" , 8, 0, 7), + WD_SPEC("SEC_HW_ENC" , 8, 8, 8), + WD_SPEC("SECTYPE" , 8, 9, 12), + WD_SPEC("lifetime_sel" , 8, 13, 15), + WD_SPEC("RSVD" , 8, 16, 16), + WD_SPEC("FORCE_TXOP" , 8, 17, 17), + WD_SPEC("AMPDU_DENSITY" , 8, 18, 20), + WD_SPEC("LSIG_TXOP_EN" , 8, 21, 21), + WD_SPEC("TXPWR_OFSET_TYPE" , 8, 22, 24), + WD_SPEC("RSVD" , 8, 25, 25), + WD_SPEC("obw_cts2self_dup_type" , 8, 26, 29), + WD_SPEC("RSVD" , 8, 30, 31), + + WD_SPEC("Signaling_TA_PKT_EN" , 9, 0, 0), + WD_SPEC("NDPA" , 9, 1, 2), + WD_SPEC("SND_PKT_SEL" , 9, 3, 5), + WD_SPEC("SIFS_Tx" , 9, 6, 6), + WD_SPEC("HT_DATA_SND" , 9, 7, 7), + WD_SPEC("RSVD" , 9, 8, 8), + WD_SPEC("RTT_EN" , 9, 9, 9), + WD_SPEC("SPE_RPT" , 9, 10, 10), + WD_SPEC("BT_NULL" , 9, 11, 11), + WD_SPEC("TRI_FRAME" , 9, 12, 12), + WD_SPEC("NULL_1" , 9, 13, 13), + WD_SPEC("NULL_0" , 9, 14, 14), + WD_SPEC("RAW" , 9, 15, 15), + WD_SPEC("Group_bit" , 9, 16, 23), + WD_SPEC("RSVD" , 9, 24, 25), + WD_SPEC("BCNPKT_TSF_CTRL" , 9, 26, 26), + WD_SPEC("Signaling_TA_PKT_SC" , 9, 27, 30), + WD_SPEC("FORCE_BSS_CLR" , 9, 31, 31), + + WD_SPEC("SW_DEFINE" , 10, 0, 3), + WD_SPEC("RSVD" , 10, 4, 26), + WD_SPEC("RTS_EN" , 10, 27, 27), + WD_SPEC("CTS2SELF" , 10, 28, 28), + WD_SPEC("CCA_RTS" , 10, 29, 30), + WD_SPEC("HW_RTS_EN" , 10, 31, 31), + + WD_SPEC("RSVD" , 11, 0, 3), + WD_SPEC("NDPA_duration" , 11, 4, 26), +}; - if (info->len > 4) - RTW_PRINT_SEL(sel, "rssi:%u\n", info->rssi); +static struct parse_wd parse_rxwd_8852ae[] = { + WD_SPEC("PKT_LEN" , 0, 0, 13), + WD_SPEC("SHIFT" , 0, 14, 15), + WD_SPEC("WL_HD_IV_LEN" , 0, 16, 21), + WD_SPEC("BB_SEL" , 0, 22, 22), + WD_SPEC("MAC_INFO_VLD" , 0, 23, 23), + WD_SPEC("RPKT_TYPE" , 0, 24, 27), + WD_SPEC("DRV_INFO_SIZE" , 0, 28, 30), + WD_SPEC("LONG_RXD" , 0, 31, 31), + + WD_SPEC("PPDU_TYPE" , 1, 0, 3), + WD_SPEC("PPDU_CNT" , 1, 4, 6), + WD_SPEC("SR_EN" , 1, 7, 7), + WD_SPEC("USER_ID" , 1, 8, 15), + WD_SPEC("RX_DATARATE" , 1, 16, 24), + WD_SPEC("RX_GI_LTF" , 1, 25, 27), + WD_SPEC("NON_SRG_PPDU" , 1, 28, 28), + WD_SPEC("INTER_PPDU" , 1, 29, 29), + WD_SPEC("BW" , 1, 30, 31), + + WD_SPEC("FREERUN_CNT" , 2, 0, 31), + + WD_SPEC("A1_MATCH" , 3, 1, 1), + WD_SPEC("SW_DEC" , 3, 2, 2), + WD_SPEC("HW_DEC" , 3, 3, 3), + WD_SPEC("AMPDU" , 3, 4, 4), + WD_SPEC("AMPDU_END_PKT" , 3, 5, 5), + WD_SPEC("AMSDU" , 3, 6, 6), + WD_SPEC("AMSDU_CUT" , 3, 7, 7), + WD_SPEC("LAST_MSDU" , 3, 8, 8), + WD_SPEC("BYPASS" , 3, 9, 9), + WD_SPEC("CRC32" , 3, 10, 10), + WD_SPEC("MAGIC_WAKE" , 3, 11, 11), + WD_SPEC("UNICAST_WAKE" , 3, 12, 12), + WD_SPEC("PATTERN_WAKE" , 3, 13, 13), + WD_SPEC("GET_CH_INFO" , 3, 14, 14), + WD_SPEC("RX_STATISTICS" , 3, 15, 15), + WD_SPEC("PATTERN_IDX" , 3, 16, 20), + WD_SPEC("TARGET_IDC" , 3, 21, 23), + WD_SPEC("CHKSUM_OFFLOAD_EN" , 3, 24, 24), + WD_SPEC("WITH_LLC" , 3, 25, 25), + WD_SPEC("RSVD" , 3, 26, 31), + + WD_SPEC("TYPE" , 4, 0, 1), + WD_SPEC("MC" , 4, 2, 2), + WD_SPEC("BC" , 4, 3, 3), + WD_SPEC("MD" , 4, 4, 4), + WD_SPEC("MF" , 4, 5, 5), + WD_SPEC("PWR" , 4, 6, 6), + WD_SPEC("QOS" , 4, 7, 7), + WD_SPEC("TID" , 4, 8, 11), + WD_SPEC("EOSP" , 4, 12, 12), + WD_SPEC("HTC" , 4, 13, 13), + WD_SPEC("QNULL" , 4, 14, 14), + WD_SPEC("RSVD" , 4, 15, 15), + WD_SPEC("SEQ" , 4, 16, 27), + WD_SPEC("FRAG" , 4, 28, 31), + + WD_SPEC("SEC_CAM_IDX" , 5, 0, 7), + WD_SPEC("ADDR_CAM" , 5, 8, 15), + WD_SPEC("MAC_ID" , 5, 16, 23), + WD_SPEC("RX_PL_ID" , 5, 24, 27), + WD_SPEC("ADDR_CAM_VLD" , 5, 28, 28), + WD_SPEC("ADDR_FWD_EN" , 5, 29, 29), + WD_SPEC("RX_PL_MATCH" , 5, 30, 30), + WD_SPEC("RSVD" , 5, 31, 31), +}; - if (info->len > 5) - RTW_PRINT_SEL(sel, "byte5:%s%s\n" - , info->eSCO_SCO ? "eSCO_SCO " : "" - , info->Master_Slave ? "Master_Slave " : "" - ); -} -static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len) -{ -#define BTINFO_WIFI_FETCH 0x23 -#define BTINFO_BT_AUTO_RPT 0x27 -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - struct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf; -#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */ - struct btinfo *info = (struct btinfo *)buf; -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - u8 cmd_idx; - u8 len; +enum WD_TYPE { + TXWD_INFO = 0, + TXWD_INFO_BODY, + RXWD, - cmd_idx = info->cid; +}; - if (info->len > buf_len - 2) { - rtw_warn_on(1); - len = buf_len - 2; - } else - len = info->len; - - /* #define DBG_PROC_SET_BTINFO_EVT */ -#ifdef DBG_PROC_SET_BTINFO_EVT -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - RTW_INFO("%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\n" - , __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); -#else/* !CONFIG_BT_COEXIST_SOCKET_TRX */ - btinfo_evt_dump(RTW_DBGDUMP, info); -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ -#endif /* DBG_PROC_SET_BTINFO_EVT */ - - /* transform BT-FW btinfo to WiFI-FW C2H format and notify */ - if (cmd_idx == BTINFO_WIFI_FETCH) - buf[1] = 0; - else if (cmd_idx == BTINFO_BT_AUTO_RPT) - buf[1] = 2; -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - else if (0x01 == cmd_idx || 0x02 == cmd_idx) - buf[1] = buf[0]; -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - rtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]); -} - -u8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len) -{ - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - u8 *btinfo; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; - u8 res = _SUCCESS; +u32 get_txdesc_element_val(u32 val_dw, u8 bit_start, u8 bit_end) +{ + u32 mask = 0; + u32 i = 0; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; + if(bit_start>31 + || bit_end>31 + || (bit_start>bit_end)){ + printk("[%s] error %d %d\n", __FUNCTION__, bit_start, bit_end); + return 0; } - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; + for(i = bit_start; i<=bit_end; i++){ + mask |= (1<>bit_start); +} - pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = len; - pdrvextra_cmd_parm->pbuf = btinfo; - _rtw_memcpy(btinfo, buf, len); +void parse_wd_8852ae(_adapter *adapter, u32 type, u32 idx_wd, u8 *wd) +{ + u32 i, val = 0; + u32 cur_dw = 0xFF; + u32 idx, val_dw = 0; + u32 array_size = 0; + struct parse_wd *parser = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + if(wd==NULL) + return; - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + if(type == TXWD_INFO_BODY){ + parser = parse_txwd_8852ae_full; + array_size = ARRAY_SIZE(parse_txwd_8852ae_full); + } + else if(type == RXWD){ + parser = parse_rxwd_8852ae; + array_size = ARRAY_SIZE(parse_rxwd_8852ae); + } -exit: - return res; -} + for(i = 0; i>>> WD[%03d].dw%02d = 0x%08x \n", idx_wd, cur_dw, val_dw); + } -static void rtw_btc_reduce_wl_txpwr_hdl(_adapter *adapter, u32 pwr_lvl) -{ - rtw_btcoex_set_reduced_wl_pwr_lvl(adapter, pwr_lvl); - rtw_btcoex_do_reduce_wl_pwr_lvl(adapter); + val = get_txdesc_element_val(val_dw, + parser[i].bit_start, parser[i].bit_end); + + printk("%s[%d:%d] = (0x%x)\n", + parser[i].name, + parser[i].bit_end, parser[i].bit_start, val); + } + printk("\n"); + +} + + +void compare_wd_8852ae(_adapter *adapter, u32 type, u8 *wd1, u8 *wd2) +{ + u32 i, val1, val2 = 0; + u32 cur_dw = 0xFF; + u32 idx, val_dw1, val_dw2 = 0; + u32 array_size = 0; + struct parse_wd *parser = NULL; + + if((wd1==NULL) ||(wd2==NULL)) + return; + + if(type == TXWD_INFO_BODY){ + parser = parse_txwd_8852ae_full; + array_size = ARRAY_SIZE(parse_txwd_8852ae_full); + } - RTW_INFO(FUNC_ADPT_FMT ": BTC reduce WL TxPwr %d dB!\n", - FUNC_ADPT_ARG(adapter), pwr_lvl); + for(i = 0; icmdpriv; - u8 res = _SUCCESS; + struct core_logs *log = &adapter->core_logs; + u32 idx = 0; - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmdobj == NULL) { - res = _FAIL; - goto exit; + printk("drvTx MAP"); + for(idx=0; idxdrvTx[idx]; + if(idx >= log->txCnt_all) + break; + printk("[drvTx %03d]\n", idx); + printk("type=%d totalSz=%d virtAddr=%p\n", record->type, record->totalSz, record->virtAddr[0]); + } + + printk("========= \n\n"); + printk("phlTx MAP"); + for(idx=0; idxphlTx[idx]; + u32 idx1 = 0; + if(idx >= log->txCnt_phl) + break; + printk("[phlTx %03d]\n", idx); + printk("type=%d totalSz=%d fragNum=%d\n", record->type, record->totalSz, record->fragNum); + for(idx1=0; idx1fragNum; idx1++){ + printk("frag#%d: len=%d virtaddr=%p \n", idx1, + record->fragLen[idx1], record->virtAddr[idx1]); + printk("frag#%d: phyAddrH=%d phyAddrL=%p \n", idx1, + record->phyAddrH[idx1], record->phyAddrL[idx1]); + } + } + + printk("========= \n\n"); + printk("TxRcycle MAP"); + for(idx=0; idxtxRcycle[idx]; + u32 idx1 = 0; + if(idx >= log->txCnt_recycle) + break; + printk("[TxRcycle %03d]\n", idx); + printk("type=%d totalSz=%d fragNum=%d\n", record->type, record->totalSz, record->fragNum); + for(idx1=0; idx1fragNum; idx1++){ + printk("frag#%d: len=%d virtaddr=%p \n", idx1, + record->fragLen[idx1], record->virtAddr[idx1]); + printk("frag#%d: phyAddrH=%d phyAddrL=%p \n", idx1, + record->phyAddrH[idx1], record->phyAddrL[idx1]); + } + } +} + +void core_dump_map_rx(_adapter *adapter) +{ + struct core_logs *log = &adapter->core_logs; + u32 idx = 0; + + printk("drvRx MAP"); + for(idx=0; idxdrvRx[idx]; + if(idx >= log->rxCnt_all) + break; + printk("[drvRx %03d]\n", idx); + printk("type=%d totalSz=%d virtAddr=%p\n", record->type, record->totalSz, record->virtAddr[0]); + printk("wl_seq=%d wl_type=0x%x wl_subtype=0x%x\n", record->wl_seq, record->wl_type, record->wl_subtype); + } + + printk("========= \n\n"); + printk("phlRx MAP"); + for(idx=0; idxphlRx[idx]; + if(idx >= log->rxCnt_phl) + break; + printk("[phlRx %03d]\n", idx); + printk("type=%d totalSz=%d virtAddr=%p\n", record->type, record->totalSz, record->virtAddr[0]); + } + + printk("========= \n\n"); + printk("rxRcycle MAP"); + for(idx=0; idxrxRcycle[idx]; + if(idx >= log->rxCnt_recycle) + break; + printk("[rxRcycle %03d]\n", idx); + printk("type=%d totalSz=%d virtAddr=%p\n", record->type, record->totalSz, record->virtAddr[0]); + } + +} + + +void core_dump_record(_adapter *adapter, u8 dump_type) +{ + struct core_logs *log = &adapter->core_logs; + u32 idx = 0; + + printk("txCnt_all: %d (%d) \n", log->txCnt_all, log->txCnt_all%CORE_LOG_NUM); + printk("txCnt_data: %d \n", log->txCnt_data); + printk("txCnt_mgmt: %d \n", log->txCnt_mgmt); + printk("txCnt_phl: %d (%d), Sz=%d \n", log->txCnt_phl, log->txCnt_phl%CORE_LOG_NUM, log->txSize_phl); + printk("txCnt_recycle: %d (%d), Sz=%d \n", log->txCnt_recycle, log->txCnt_recycle%CORE_LOG_NUM, log->txSize_recycle); + + printk("rxCnt_all: %d (%d) \n", log->rxCnt_all, log->rxCnt_all%CORE_LOG_NUM); + printk("rxCnt_data: %d (retry=%d)\n", log->rxCnt_data, log->rxCnt_data_retry); + printk("rxCnt_mgmt: %d \n", log->rxCnt_mgmt); + printk("rxCnt_phl: %d (%d), Sz=%d \n", log->rxCnt_phl, log->rxCnt_phl%CORE_LOG_NUM, log->rxSize_phl); + printk("rxCnt_recycle: %d (%d), Sz=%d\n", log->rxCnt_recycle, log->rxCnt_recycle%CORE_LOG_NUM, log->rxSize_recycle); +#ifdef CONFIG_RTW_CORE_RXSC + printk("enable_rxsc: %d \n", adapter->enable_rxsc); + printk("rxCnt_data: orig=%d shortcut=%d(ratio=%d)\n", + log->rxCnt_data_orig, log->rxCnt_data_shortcut, + log->rxCnt_data_shortcut*100/(log->rxCnt_data_orig+log->rxCnt_data_shortcut)); + printk("rxCnt_coreInd: %d \n", log->rxCnt_coreInd); +#endif + + if(dump_type == REC_DUMP_TX){ + core_dump_map_tx(adapter); + } + else if(dump_type == REC_DUMP_RX){ + core_dump_map_rx(adapter); + } + else if(dump_type == REC_DUMP_ALL){ + core_dump_map_tx(adapter); + core_dump_map_rx(adapter); + } +} + +void core_add_record(_adapter *adapter, u8 type, void *p) +{ + struct core_logs *log = &adapter->core_logs; + + if(!adapter->record_enable) + return; + + if(type == REC_TX_DATA){ + u32 idx = log->txCnt_all%CORE_LOG_NUM; + struct core_record *record = &(log->drvTx[idx]); + struct sk_buff *skb = p; + + log->txCnt_data++; + record->type = type; + record->totalSz = skb->len; + record->virtAddr[0] = skb->data; + } + + if(type == REC_TX_MGMT){ + u32 idx = log->txCnt_all%CORE_LOG_NUM; + struct core_record *record = &(log->drvTx[idx]); + struct xmit_frame *pxframe = p; + + log->txCnt_mgmt++; + record->type = type; + record->totalSz = pxframe->attrib.pktlen; + record->virtAddr[0] = pxframe->buf_addr; + } + + if(type == REC_TX_PHL || type == REC_TX_PHL_RCC){ + u32 idx = 0; + struct core_record *record = NULL; + struct rtw_xmit_req *txreq = p; + + if(type == REC_TX_PHL){ + idx = log->txCnt_phl%CORE_LOG_NUM; + record = &(log->phlTx[idx]); + log->txCnt_phl++; + } + + if(type == REC_TX_PHL_RCC){ + idx = log->txCnt_recycle%CORE_LOG_NUM; + record = &(log->txRcycle[idx]); + log->txCnt_recycle++; + } + + record->type = type; + record->totalSz = 0; + record->fragNum = txreq->pkt_cnt; + + { + struct rtw_pkt_buf_list *pkt_list =(struct rtw_pkt_buf_list *)txreq->pkt_list; + u32 idx1 = 0; + for(idx1=0; idx1pkt_cnt; idx1++){ + if(idx1 >= MAX_FRAG){ + printk("!! WARN[%s][%d] type=%d frag>= %d \n", + __FUNCTION__, __LINE__, type, MAX_FRAG); + break; + } + record->totalSz += pkt_list->length; + record->fragLen[idx1] = pkt_list->length; + record->virtAddr[idx1] = pkt_list->vir_addr; + record->phyAddrL[idx1] = pkt_list->phy_addr_l; + record->phyAddrH[idx1] = pkt_list->phy_addr_h; + pkt_list++; + } + } + + if(type == REC_TX_PHL) + log->txSize_phl += record->totalSz; + else if(type == REC_TX_PHL_RCC) + log->txSize_recycle += record->totalSz; + + } + + if(type == REC_RX_PHL || type == REC_RX_PHL_RCC){ + u32 idx = 0; + struct core_record *record = NULL; + struct rtw_recv_pkt *rx_req = p; + struct rtw_pkt_buf_list *pkt = rx_req->pkt_list; + + if(type == REC_RX_PHL){ + idx = log->rxCnt_phl%CORE_LOG_NUM; + record = &(log->phlRx[idx]); + log->rxCnt_phl++; + } + + if(type == REC_RX_PHL_RCC){ + idx = log->rxCnt_recycle%CORE_LOG_NUM; + record = &(log->rxRcycle[idx]); + log->rxCnt_recycle++; + } + + record->type = type; + record->totalSz = pkt->length; + record->virtAddr[0] = pkt->vir_addr; + + if(type == REC_RX_PHL) + log->rxSize_phl += record->totalSz; + else if(type == REC_RX_PHL_RCC) + log->rxSize_recycle += record->totalSz; + } + + if(type == REC_RX_DATA || type == REC_RX_MGMT){ + u32 idx = log->rxCnt_all%CORE_LOG_NUM; + struct core_record *record = &(log->drvRx[idx]); + union recv_frame *prframe = p; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + + if(type == REC_RX_DATA){ + log->rxCnt_data++; + } + + if(type == REC_RX_MGMT){ + log->rxCnt_mgmt++; + } + + record->type = type; + record->totalSz = prframe->u.hdr.len; + record->virtAddr[0] = prframe->u.hdr.rx_data; + + record->wl_seq = pattrib->seq_num; + record->wl_type = pattrib->wl_type; + record->wl_subtype = pattrib->wl_subtype; + + } + + if(type == REC_RX_DATA_RETRY){ + log->rxCnt_data_retry++; + } + + log->txCnt_all = log->txCnt_mgmt + log->txCnt_data; + log->rxCnt_all = log->rxCnt_mgmt + log->rxCnt_data; +} + + +void phl_dump_map_tx(_adapter *adapter) +{ + struct phl_logs *log = &adapter->phl_logs; + u32 idx = 0; + + printk("txBd MAP"); + for(idx=0; idxtxBd[idx]; + if(idx >= log->txCnt_bd) + break; + printk("[txBd %03d]\n", idx); + { + u8 *tmp=record->bd_buf; + u32 len = record->bd_len; + u32 idx1 = 0; + if(tmp == NULL) + break; + for(idx1=0; idx1txWd[idx]; + if(idx >= log->txCnt_wd) + break; + printk("[txWd %03d]\n", idx); + { + u8 *tmp=record->wd_buf; + u32 len = record->wd_len; + u32 idx1 = 0; + if(tmp == NULL) + break; + for(idx1=0; idx1wd_buf); + //compare_wd_8852ae(adapter, TXWD_INFO_BODY, record->wd_buf, sample_txwd); + } + + printk("========= \n\n"); + printk("wpRecycle MAP"); + for(idx=0; idxwpRecycle[idx]; + if(idx >= log->txCnt_recycle) + break; + printk("[txRecycle %03d]\n", idx); + printk("wp_seq=%d \n", record->wp_seq); + } +} + +void phl_dump_map_rx(_adapter *adapter) +{ + struct phl_logs *log = &adapter->phl_logs; + u32 idx = 0; + + printk("rxPciMap MAP"); + for(idx=0; idxrxPciMap[idx]; + if(idx >= log->rxCnt_map) + break; + printk("[rxPciMap %03d]\n", idx); + printk("phyAddrL=%p len=%d\n", record->phyAddrL, record->map_len); + } + + + printk("========= \n\n"); + printk("rxPciUnmap MAP"); + for(idx=0; idxrxPciUnmap[idx]; + if(idx >= log->rxCnt_unmap) + break; + printk("[rxPciUnmap %03d]\n", idx); + printk("phyAddrL=%p len=%d\n", record->phyAddrL, record->map_len); + } + + printk("========= \n\n"); + printk("rxWd MAP"); + for(idx=0; idxrxWd[idx]; + if(idx >= log->rxCnt_wd) + break; + printk("[rxWd %03d]\n", idx); + { + u8 *tmp = record->wd_buf; + u32 len = record->wd_len; + u32 idx1 = 0; + if(tmp == NULL) + break; + for(idx1=0; idx1wd_buf); + } + + printk("========= \n\n"); + printk("rxAmpdu MAP"); + for(idx=0; idx= log->rxCnt_ampdu) + break; + printk("[rxAmpdu %03d] = %d\n", idx, log->rxAmpdu[idx]); + } + +} + +void phl_dump_record(_adapter *adapter, u8 dump_type) +{ + struct phl_logs *log = &adapter->phl_logs; + u32 idx = 0; + + printk("txBd: %d (%d) \n", log->txCnt_bd, log->txCnt_bd%CORE_LOG_NUM); + printk("txWd: %d (%d) \n", log->txCnt_wd, log->txCnt_wd%CORE_LOG_NUM); + printk("wpCnt_recycle: %d (%d) \n", log->txCnt_recycle, log->txCnt_recycle%CORE_LOG_NUM); + + printk("rxMap: %d (%d), Sz=%d \n", log->rxCnt_map, log->rxCnt_map%CORE_LOG_NUM, log->rxSize_map); + printk("rxUnmap: %d (%d), Sz=%d \n", log->rxCnt_unmap, log->txCnt_wd%CORE_LOG_NUM, log->rxSize_map); + printk("rxWd: %d (%d) \n", log->rxCnt_wd, log->rxCnt_wd%CORE_LOG_NUM); + printk("rxCnt_ampdu: %d (%d) \n", log->rxCnt_ampdu, log->rxCnt_ampdu%CORE_LOG_NUM); + + if(dump_type == REC_DUMP_TX) + phl_dump_map_tx(adapter); + else if(dump_type == REC_DUMP_RX) + phl_dump_map_rx(adapter); + else if(dump_type == REC_DUMP_ALL){ + phl_dump_map_tx(adapter); + phl_dump_map_rx(adapter); + } +} + +u32 tmp_rx_last_ppdu = 0; + +void phl_add_record(void *d, u8 type, void *p, u32 num) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + _adapter *adapter = dvobj_get_primary_adapter(pobj); + struct phl_logs *log = &adapter->phl_logs; + + if(!adapter->record_enable) + return; + + if(type == REC_TXWD){ + u32 idx = log->txCnt_wd%CORE_LOG_NUM; + struct record_txwd *record = &(log->txWd[idx]); + + log->txCnt_wd++; + record->wd_len = num; + memset((u8 *)record->wd_buf, 0, MAX_TXWD_SIZE); + memcpy((u8 *)record->wd_buf, p, num); + } + + if(type == REC_TXBD){ + u32 idx = log->txCnt_bd%CORE_LOG_NUM; + struct record_txbd *record = &(log->txBd[idx]); + + log->txCnt_bd++; + record->bd_len = num; + memset((u8 *)record->bd_buf, 0, MAX_TXBD_SIZE); + memcpy((u8 *)record->bd_buf, p, num); + } + + if(type == REC_WP_RCC){ + u32 idx = log->txCnt_recycle%CORE_LOG_NUM; + struct record_wp_rcc *record = &(log->wpRecycle[idx]); + + log->txCnt_recycle++; + record->wp_seq = num; + } + + if(type == REC_RX_MAP || type == REC_RX_UNMAP){ + struct record_pci *record = NULL; + if(type == REC_RX_MAP) { + u32 idx = log->rxCnt_map%CORE_LOG_NUM; + record = &(log->rxPciMap[idx]); + log->rxCnt_map++; + log->rxSize_map+=num; + } + else if(type == REC_RX_UNMAP) { + u32 idx = log->rxCnt_unmap%CORE_LOG_NUM; + record = &(log->rxPciUnmap[idx]); + log->rxCnt_unmap++; + log->rxSize_map+=num; + } + record->phyAddrL = p; + record->map_len = num; + } + + if(type == REC_RXWD){ + u32 idx = log->rxCnt_wd%CORE_LOG_NUM; + struct record_rxwd *record = &(log->rxWd[idx]); + + log->rxCnt_wd++; + record->wd_len = num; + memset((u8 *)record->wd_buf, 0, MAX_RXWD_SIZE); + memcpy((u8 *)record->wd_buf, p, num); + } + + if(type == REC_RX_AMPDU){ + u32 idx = 0; + + if(log->rxCnt_ampdu == 0 && (log->rxAmpdu[0] == 0)) + tmp_rx_last_ppdu = num; + + if(tmp_rx_last_ppdu != num){ + tmp_rx_last_ppdu = num; + + log->rxCnt_ampdu ++; + idx = log->rxCnt_ampdu%CORE_LOG_NUM; + log->rxAmpdu[idx] = 1; + } + else{ + idx = log->rxCnt_ampdu%CORE_LOG_NUM; + log->rxAmpdu[idx]++; + } +} + +} + +void core_cmd_record_trx(_adapter *adapter, void *cmd_para, u32 para_num) +{ + u32 idx = 0; + char *para = (char *)cmd_para; + + if(para_num<=0) + return; + + if(!strcmp(para, "start")){ + u8 *log = NULL; + log = (u8*)&adapter->core_logs; + memset(log, 0, sizeof(struct core_logs)); + log = (u8*)&adapter->phl_logs; + memset(log, 0, sizeof(struct phl_logs)); + adapter->record_enable = 1; + }else if(!strcmp(para, "stop")){ + adapter->record_enable = 0; + }else if(!strcmp(para, "dump")){ + u32 dump_type = 0; + para=get_next_para_str(para); + sscanf(para, "%d", &dump_type); + phl_dump_record(adapter, (u8)dump_type); + } +} + +void reset_txforce_para(_adapter *adapter) +{ + adapter->txForce_rate = INV_TXFORCE_VAL; + adapter->txForce_agg = INV_TXFORCE_VAL; + adapter->txForce_aggnum = INV_TXFORCE_VAL; + adapter->txForce_gi = INV_TXFORCE_VAL; +} + +void core_cmd_txforce(_adapter *adapter, void *cmd_para, u32 para_num) +{ + u32 idx = 0; + char *para = (char *)cmd_para; + + if(para_num<=0) + return; + + if(!strcmp(para, "start")){ + adapter->txForce_enable = 1; + reset_txforce_para(adapter); + }else if(!strcmp(para, "stop")){ + adapter->txForce_enable = 0; + reset_txforce_para(adapter); + }else if(!strcmp(para, "rate")){ + u32 rate = 0; + para=get_next_para_str(para); + sscanf(para, "%x", &rate); + adapter->txForce_rate = rate; + }else if(!strcmp(para, "agg")){ + u32 agg = 0; + para=get_next_para_str(para); + sscanf(para, "%x", &agg); + adapter->txForce_agg = agg; + }else if(!strcmp(para, "aggnum")){ + u32 aggnum = 0; + para=get_next_para_str(para); + sscanf(para, "%d", &aggnum); + adapter->txForce_aggnum = aggnum; + }else if(!strcmp(para, "gi")){ + u32 gi = 0; + para=get_next_para_str(para); + sscanf(para, "%d", &gi); + adapter->txForce_gi = gi; + }else if(!strcmp(para, "macid")){ + + }else if(!strcmp(para, "retry")){ + + } +} + +#ifdef CONFIG_RTW_CORE_RXSC +void core_cmd_rxsc(_adapter *adapter, void *cmd_para, u32 para_num) +{ + u32 idx = 0; + char *para = (char *)cmd_para; + + printk("core_cmd_rxsc \n"); + + if(para_num<=0) + return; + + if(!strcmp(para, "enable")){ + printk("enable"); + adapter->enable_rxsc = 1; + }else if(!strcmp(para, "disable")){ + printk("disable"); + adapter->enable_rxsc = 0; + }else if(!strcmp(para, "dump")){ + struct core_logs *log = &adapter->core_logs; + printk("dump"); + printk("enable_rxsc: %d \n", adapter->enable_rxsc); + printk("rxCnt_data: orig=%d shortcut=%d(ratio=%d)\n", + log->rxCnt_data_orig, log->rxCnt_data_shortcut, + log->rxCnt_data_shortcut*100/(log->rxCnt_data_orig+log->rxCnt_data_shortcut)); + } + +} +#endif + +void core_sniffer_rx(_adapter *adapter, u8 *pkt, u32 pktlen) +{ + struct sk_buff* pskb = NULL; + + if(!adapter->sniffer_enable) + return; + + if(pkt==NULL) + return; + + pskb = dev_alloc_skb(pktlen+200); + + if(pskb == NULL){ + return; +} + + _rtw_memcpy(pskb->data, pkt, pktlen); + pskb->len = pktlen; + + skb_reset_mac_header(pskb); + pskb->dev = adapter->pnetdev; + pskb->dev->type = ARPHRD_IEEE80211; + pskb->ip_summed = CHECKSUM_UNNECESSARY; + pskb->pkt_type = PACKET_OTHERHOST; + pskb->protocol = htons(ETH_P_802_2); + netif_receive_skb(pskb); + + return; +} + +void core_cmd_sniffer(_adapter *adapter, void *cmd_para, u32 para_num) + { + u32 idx=0; + char *para = (char *)cmd_para; + + if(para_num<=0) + return; + + if(!strcmp(para, "start")){ + adapter->sniffer_enable = 1; + }else if(!strcmp(para, "stop")){ + adapter->sniffer_enable = 0; + } +} + + +#define LEN_TEST_BUF 2000 +u8 test_buf[LEN_TEST_BUF]; + +#ifdef CONFIG_PCI_HCI +#include +#endif + +#include "../phl/phl_headers.h" +#include "../phl/phl_api.h" +#include "../phl/hal_g6/hal_api_mac.h" +#include "../phl/hal_g6/mac/mac_reg.h" + + +#define SHOW_REG32(adapter, reg) \ + do { \ + printk("\t%04X = %08X\n", \ + (reg), rtw_phl_read32(adapter->dvobj->phl, reg)); \ + } while (0) + +#define SHOW_REG32_MSG(adapter, reg, msg) \ + do { \ + printk("\t%04X = %08X - %s\n", \ + (reg), rtw_phl_read32(adapter->dvobj->phl, reg), msg); \ + } while (0) + +#define SHOW_REG16(adapter, reg) \ + do { \ + printk("\t%04X = %04X\n", \ + (reg), rtw_phl_read16(adapter->dvobj->phl, reg)); \ + } while (0) + +#define SHOW_REG16_MSG(adapter, reg, msg) \ + do { \ + printk("\t%04X = %04X - %s\n", \ + (reg), rtw_phl_read16(adapter->dvobj->phl, reg), msg); \ + } while (0) + + +static inline void _show_RX_counter(_adapter *adapter) +{ + /* Show RX PPDU counters */ + int i; + u32 reg32 = rtw_phl_read32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL); + static const char *cnt_name[] = {"Invalid packet", + "RE-CCA", + "RX FIFO overflow", + "RX packet full drop", + "RX packet dma OK", + "UD 0", + "UD 1", + "UD 2", + "UD 3", + "continuous FCS error", + "RX packet filter drop", + "CSI packet DMA OK", + "CSI packet DMA drop", + "RX MAC stop" + }; + + printk("CMAC0 RX PPDU Counters @%04X:\n", R_AX_RX_DBG_CNT_SEL); + reg32 &= ~(B_AX_RX_CNT_IDX_MSK << B_AX_RX_CNT_IDX_SH); + for (i = 30; i < 44; i++) { + rtw_phl_write32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL, + reg32 | (i << B_AX_RX_CNT_IDX_SH)); + printk(" %02X: %d - %s\n", i, + ( + ( rtw_phl_read32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL) + >> B_AX_RX_DBG_CNT_SH) + & B_AX_RX_DBG_CNT_MSK), + cnt_name[i - 30]); + } + + reg32 = rtw_phl_read32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL_C1); + printk("CMAC1 RX PPDU Counters @%04X:\n", R_AX_RX_DBG_CNT_SEL_C1); + reg32 &= ~(B_AX_RX_CNT_IDX_MSK << B_AX_RX_CNT_IDX_SH); + for (i = 30; i < 44; i++) { + rtw_phl_write32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL_C1, + reg32 | (i << B_AX_RX_CNT_IDX_SH)); + printk(" %02X: %d - %s\n", i, + ( + ( rtw_phl_read32(adapter->dvobj->phl, R_AX_RX_DBG_CNT_SEL_C1) + >> B_AX_RX_DBG_CNT_SH) + & B_AX_RX_DBG_CNT_MSK), + cnt_name[i - 30]); + } +} /* _show_RX_counter */ + +void _show_TX_dbg_status(_adapter *adapter) +{ + u32 reg32 = rtw_phl_read32(adapter->dvobj->phl, 0x9F1C); + printk("TX Debug: 0x%08X\n", reg32); +} + +void _show_BCN_dbg_status(_adapter *adapter) +{ + SHOW_REG32_MSG(adapter, R_AX_PORT_CFG_P0, "PORT_CFG_P0"); + SHOW_REG32_MSG(adapter, R_AX_TBTT_PROHIB_P0, "TBTT_PROHIB_P0"); + SHOW_REG32_MSG(adapter, R_AX_EN_HGQ_NOLIMIT, "EN_HGQ_NOLIMIT"); + SHOW_REG32_MSG(adapter, R_AX_TBTT_AGG_P0, "TBTT_AGG_P0"); + + SHOW_REG32_MSG(adapter, R_AX_PORT_CFG_P0_C1, "PORT_CFG_P0_C1"); + SHOW_REG32_MSG(adapter, R_AX_TBTT_PROHIB_P0_C1, "TBTT_PROHIB_P0_C1"); + SHOW_REG32_MSG(adapter, R_AX_EN_HGQ_NOLIMIT_C1, "EN_HGQ_NOLIMIT_C1"); + SHOW_REG32_MSG(adapter, R_AX_TBTT_AGG_P0_C1, "TBTT_AGG_P0_C1"); + + SHOW_REG32_MSG(adapter, R_AX_WCPU_FW_CTRL, "R_AX_WCPU_FW_CTRL"); +} + + +void core_cmd_dump_debug(_adapter *adapter, void *cmd_para, u32 para_num) +{ + printk("TX path registers: \n"); + + SHOW_REG32_MSG(adapter, R_AX_RXQ_RXBD_IDX, "RX_BD_IDX"); + SHOW_REG32_MSG(adapter, R_AX_RPQ_RXBD_IDX, "RP_BD_IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH0_TXBD_IDX, "ACH0 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH1_TXBD_IDX, "ACH1 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH2_TXBD_IDX, "ACH2 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH3_TXBD_IDX, "ACH3 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH4_TXBD_IDX, "ACH4 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH5_TXBD_IDX, "ACH5 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH6_TXBD_IDX, "ACH6 IDX"); + SHOW_REG32_MSG(adapter, R_AX_ACH7_TXBD_IDX, "ACH7 IDX"); + SHOW_REG32_MSG(adapter, R_AX_CH8_TXBD_IDX, "CH8 IDX"); + SHOW_REG32_MSG(adapter, R_AX_CH9_TXBD_IDX, "CH9 IDX"); + SHOW_REG32_MSG(adapter, R_AX_CH10_TXBD_IDX, "CH10 IDX"); + SHOW_REG32_MSG(adapter, R_AX_CH11_TXBD_IDX, "CH11 IDX"); + SHOW_REG32_MSG(adapter, R_AX_CH12_TXBD_IDX, "CH12 IDX"); +#ifdef R_AX_PCIE_DBG_CTRL + SHOW_REG32_MSG(adapter, R_AX_PCIE_DBG_CTRL, "DBG_CTRL"); +#else + SHOW_REG32_MSG(adapter, 0x11C0, "DBG_CTRL"); +#endif + SHOW_REG32_MSG(adapter, R_AX_DBG_ERR_FLAG, "DBG_ERR"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_HIMR00, "IMR0"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_HISR00, "ISR0"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_HIMR10, "IMR1"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_HISR10, "IMR1"); + SHOW_REG16_MSG(adapter, R_AX_ACH0_BDRAM_RWPTR, "CH0"); + SHOW_REG16_MSG(adapter, R_AX_ACH1_BDRAM_RWPTR, "CH1"); + SHOW_REG16_MSG(adapter, R_AX_ACH2_BDRAM_RWPTR, "CH2"); + SHOW_REG16_MSG(adapter, R_AX_ACH3_BDRAM_RWPTR, "CH3"); + SHOW_REG16_MSG(adapter, R_AX_ACH4_BDRAM_RWPTR, "CH4"); + SHOW_REG16_MSG(adapter, R_AX_ACH5_BDRAM_RWPTR, "CH5"); + SHOW_REG16_MSG(adapter, R_AX_ACH6_BDRAM_RWPTR, "CH6"); + SHOW_REG16_MSG(adapter, R_AX_ACH7_BDRAM_RWPTR, "CH7"); + SHOW_REG16_MSG(adapter, R_AX_CH8_BDRAM_RWPTR, "CH8"); + SHOW_REG16_MSG(adapter, R_AX_CH9_BDRAM_RWPTR, "CH9"); + SHOW_REG16_MSG(adapter, R_AX_CH10_BDRAM_RWPTR, "CH10"); + SHOW_REG16_MSG(adapter, R_AX_CH11_BDRAM_RWPTR, "CH11"); + SHOW_REG16_MSG(adapter, R_AX_CH12_BDRAM_RWPTR, "CH12"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_DMA_STOP1, "DMA_STOP1"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_DMA_BUSY1, "DMA_BUSY1"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_DMA_STOP2, "DMA_STOP2"); + SHOW_REG32_MSG(adapter, R_AX_PCIE_DMA_BUSY2, "DMA_BUSY2"); + SHOW_REG32(adapter, 0x8840); + SHOW_REG32(adapter, 0x8844); + SHOW_REG32(adapter, 0x8854); + SHOW_REG16(adapter, 0xCA22); + SHOW_REG32(adapter, 0x8AA8); + + /* Show TX PPDU counters */ + do { + int i; + u32 reg32 = rtw_phl_read32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT); + + printk("CMAC0 TX PPDU Counters @%04X:\n", R_AX_TX_PPDU_CNT); + + reg32 &= ~(B_AX_PPDU_CNT_IDX_MSK << B_AX_PPDU_CNT_IDX_SH); + for (i = 0; i < 11; i++) { + rtw_phl_write32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT, + reg32 | (i << B_AX_PPDU_CNT_IDX_SH)); + printk(" %02X: %d\n", i, + ( + ( rtw_phl_read32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT) + >> B_AX_TX_PPDU_CNT_SH) + & B_AX_TX_PPDU_CNT_MSK)); + } + + reg32 = rtw_phl_read32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT_C1); + + printk("CMAC1 TX PPDU Counters @%04X:\n", R_AX_TX_PPDU_CNT_C1); + + reg32 &= ~(B_AX_PPDU_CNT_IDX_MSK << B_AX_PPDU_CNT_IDX_SH); + for (i = 0; i < 11; i++) { + rtw_phl_write32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT_C1, + reg32 | (i << B_AX_PPDU_CNT_IDX_SH)); + printk(" %02X: %d\n", i, + ( + ( rtw_phl_read32(adapter->dvobj->phl, R_AX_TX_PPDU_CNT_C1) + >> B_AX_TX_PPDU_CNT_SH) + & B_AX_TX_PPDU_CNT_MSK)); + } + } while (0); + + /* Show RX PPDU counters */ + _show_RX_counter(adapter); + + _show_TX_dbg_status(adapter); + + _show_BCN_dbg_status(adapter); + +} + +void core_cmd_dump_reg(_adapter *adapter, void *cmd_para, u32 para_num) +{ + u32 *para = (u32 *)cmd_para; + void *phl = adapter->dvobj->phl; + u32 reg_start, reg_end; + u32 idx = 0; + + reg_start = para[0]; + reg_end = reg_start + para[1]; + + while(1) { + if((reg_start>=reg_end) || (reg_start >= 0xffff)) + break; + + printk("[%04x] %08x %08x %08x %08x \n", + reg_start, + rtw_phl_read32(phl, reg_start), rtw_phl_read32(phl, reg_start+4), + rtw_phl_read32(phl, reg_start+8), rtw_phl_read32(phl, reg_start+12)); + + reg_start+=16; + } +} + +enum _CORE_CMD_PARA_TYPE { + CMD_PARA_DEC = 0, + CMD_PARA_HEX, + CMD_PARA_STR, +}; + +struct test_cmd_list { + const char *name; + void (*fun)(_adapter *, void *, u32); + enum _CORE_CMD_PARA_TYPE para_type; +}; + +void test_dump_dec(_adapter *adapter, void *cmd_para, u32 para_num) +{ + u32 idx = 0; + u32 *para = (u32 *)cmd_para; + DBGP("para_num=%d\n", para_num); + + for(idx=0; idx 0){ + tmp = strsep(&buf, ","); + + if(tmp){ + if(type == CMD_PARA_HEX) + sscanf(tmp, "%x", para); + else if(type == CMD_PARA_DEC) + sscanf(tmp, "%d", para); + para += 1; + *num = *num+1; + } + else + return; + + if(buf && (len>strlen(tmp))) + get_all_cmd_para_value(adapter, buf, strlen(buf), para, type, num); + else + return; + } + } + +void get_all_cmd_para_str(_adapter *adapter, char *buf, u32 len, char *para, u8 type, u32* num) +{ + u8 *tmp = NULL; + + if(!buf || !len) + return; + + DBGP("type=%d buf=%s para=%p num=%d\n", type, buf, para, *num); + + if(len > 0){ + tmp = strsep(&buf, ","); + + if(tmp){ + strcpy(para, tmp); + para += MAX_PHL_CMD_STR_LEN; + *num = *num+1; } + else + return; - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; + if(buf && (len>strlen(tmp))) + get_all_cmd_para_str(adapter, buf, strlen(buf), para, type, num); + else + return; + } } - pdrvextra_cmd_parm->ec_id = BTC_REDUCE_WL_TXPWR_CID; - pdrvextra_cmd_parm->type = val; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; +struct test_cmd_list core_test_cmd_list[] = { + {"dec", test_dump_dec, CMD_PARA_DEC}, + {"hex", test_dump_hex, CMD_PARA_HEX}, + {"str", test_dump_str, CMD_PARA_STR}, + {"dump_reg", core_cmd_dump_reg, CMD_PARA_HEX}, + {"dump_debug", core_cmd_dump_debug, CMD_PARA_DEC}, + {"record", core_cmd_record_trx, CMD_PARA_STR}, + {"txforce", core_cmd_txforce, CMD_PARA_STR}, + {"sniffer", core_cmd_sniffer, CMD_PARA_STR}, +#ifdef CONFIG_RTW_CORE_RXSC + {"rxsc", core_cmd_rxsc, CMD_PARA_STR}, +#endif +}; - init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); +void core_cmd_phl_handler(_adapter *adapter, char *extra) +{ + u32 para[MAX_PHL_CMD_NUM]={0}; + char para_str[MAX_PHL_CMD_NUM][MAX_PHL_CMD_STR_LEN]={0}; + char *cmd_name, *cmd_para = NULL; + struct test_cmd_list *cmd = &core_test_cmd_list; + u32 array_size = ARRAY_SIZE(core_test_cmd_list); + u32 i = 0; + + cmd_name = strsep(&extra, ","); - res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + if(!cmd_name){ + for(i = 0; iname); + return; + } -exit: - return res; + for(i = 0; iname, cmd_name)){ + void *cmd_para = NULL; + u32 cmd_para_num = 0; + if(cmd->para_type == CMD_PARA_DEC || cmd->para_type == CMD_PARA_HEX){ + cmd_para = para; + if(extra) + get_all_cmd_para_value(adapter, extra, strlen(extra), para, cmd->para_type, &cmd_para_num); + } + else{ + cmd_para = para_str; + if(extra) + get_all_cmd_para_str(adapter, extra, strlen(extra), para_str, cmd->para_type, &cmd_para_num); + } + + cmd->fun(adapter, cmd_para, cmd_para_num); + break; + } + } + } -#endif /* CONFIG_BT_COEXIST */ + +#endif u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) { struct cmd_obj *pcmdobj; struct drvextra_cmd_parm *pdrvextra_cmd_parm; u8 *ph2c_content; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 res = _SUCCESS; pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); @@ -4478,6 +5608,7 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) res = _FAIL; goto exit; } + pcmdobj->padapter = adapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { @@ -4512,48 +5643,40 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) #ifdef CONFIG_MP_INCLUDED static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); int ret = H2C_SUCCESS; - uint status = _SUCCESS; + uint status = _FALSE; + struct mp_priv *pmppriv = &padapter->mppriv; + struct rtw_test_module_info test_module_info; + struct rtw_mp_test_rpt my_mp_test_rpt; if (mp_cmd_id == MP_START) { if (padapter->registrypriv.mp_mode == 0) { - rtw_intf_stop(padapter); - rtw_hal_deinit(padapter); - padapter->registrypriv.mp_mode = 1; -#ifdef CONFIG_BT_COEXIST - padapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist; - pHalData->EEPROMBluetoothCoexist = _FALSE; -#endif -#ifdef CONFIG_RF_POWER_TRIM - if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter) && !IS_HARDWARE_TYPE_8822C(padapter)) { - padapter->registrypriv.RegPwrTrimEnable = 1; - rtw_hal_read_chip_info(padapter); - } -#endif /*CONFIG_RF_POWER_TRIM*/ - rtw_reset_drv_sw(padapter); -#ifdef CONFIG_NEW_NETDEV_HDL - if (!rtw_is_hw_init_completed(padapter)) { - status = rtw_hal_init(padapter); - if (status == _FAIL) { - ret = H2C_REJECTED; - goto exit; - } - rtw_hal_iface_init(padapter); + + test_module_info.tm_mode = RTW_DRV_MODE_MP; + test_module_info.tm_type = RTW_TEST_SUB_MODULE_MP; + pmppriv->keep_ips_status = dvobj->phl_com->dev_sw_cap.ps_cap.ips_en; + pmppriv->keep_lps_status = dvobj->phl_com->dev_sw_cap.ps_cap.lps_en; + dvobj->phl_com->dev_sw_cap.ps_cap.ips_en = PS_OP_MODE_DISABLED; + dvobj->phl_com->dev_sw_cap.ps_cap.lps_en = PS_OP_MODE_DISABLED; + + rtw_phl_test_submodule_init(dvobj->phl_com, &test_module_info); +#ifdef CONFIG_BTC + if (dvobj->phl_com->dev_cap.btc_mode == BTC_MODE_NORMAL ||\ + dvobj->phl_com->dev_cap.btc_mode == BTC_MODE_BT) { + + pmppriv->mp_keep_btc_mode = dvobj->phl_com->dev_cap.btc_mode; + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SWITCH_BT_PATH); + RTW_INFO("config BTC to WL Only\n"); } -#else - status = rtw_hal_init(padapter); - if (status == _FAIL) { - ret = H2C_REJECTED; - goto exit; +#endif + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_PHY_INDEX); + status = rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_START_DUT); + + if (status == _TRUE) { + padapter->registrypriv.mp_mode = 1; + MPT_InitializeAdapter(padapter, 1); } -#endif /*CONFIG_NEW_NETDEV_HDL*/ -#ifndef RTW_HALMAC - rtw_intf_start(padapter); -#endif /* !RTW_HALMAC */ -#ifdef RTW_HALMAC /*for New IC*/ - MPT_InitializeAdapter(padapter, 1); -#endif /* CONFIG_MP_INCLUDED */ } if (padapter->registrypriv.mp_mode == 0) { @@ -4567,55 +5690,33 @@ static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) goto exit; } padapter->mppriv.mode = MP_ON; - MPT_PwrCtlDM(padapter, 0); } padapter->mppriv.bmac_filter = _FALSE; -#ifdef CONFIG_RTL8723B -#ifdef CONFIG_USB_HCI - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0280); -#else - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0000); -#endif -#ifdef CONFIG_FOR_RTL8723BS_VQ0 - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0280); -#endif - rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ - rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ -#endif - odm_write_dig(&pHalData->odmpriv, 0x20); } else if (mp_cmd_id == MP_STOP) { if (padapter->registrypriv.mp_mode == 1) { + + status = rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_STOP_DUT); + RTW_INFO("RTW_MP_CONFIG_CMD_STOP_DUT %s\n", status == _TRUE ? "ok" : "fail"); + rtw_phl_test_get_rpt(dvobj->phl_com, (u8*)&my_mp_test_rpt, sizeof(my_mp_test_rpt)); + + if (my_mp_test_rpt.status == _TRUE) + RTW_INFO("TM Sub finished OK!!!\n"); +#ifdef CONFIG_BTC + if (pmppriv->mp_keep_btc_mode != BTC_MODE_MAX) { + pmppriv->btc_path = pmppriv->mp_keep_btc_mode; + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SWITCH_BT_PATH); + } +#endif + test_module_info.tm_mode = RTW_DRV_MODE_NORMAL; + test_module_info.tm_type = RTW_TEST_SUB_MODULE_MP; + dvobj->phl_com->dev_sw_cap.ps_cap.ips_en = pmppriv->keep_ips_status; + dvobj->phl_com->dev_sw_cap.ps_cap.lps_en = pmppriv->keep_lps_status; + + rtw_phl_test_submodule_deinit(dvobj->phl_com, &test_module_info); + MPT_DeInitAdapter(padapter); - rtw_intf_stop(padapter); - rtw_hal_deinit(padapter); padapter->registrypriv.mp_mode = 0; -#ifdef CONFIG_BT_COEXIST - pHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex; -#endif - rtw_reset_drv_sw(padapter); -#ifdef CONFIG_NEW_NETDEV_HDL - if (!rtw_is_hw_init_completed(padapter)) { - status = rtw_hal_init(padapter); - if (status == _FAIL) { - ret = H2C_REJECTED; - goto exit; - } - rtw_hal_iface_init(padapter); - } -#else - status = rtw_hal_init(padapter); - if (status == _FAIL) { - ret = H2C_REJECTED; - goto exit; - } -#endif /*CONFIG_NEW_NETDEV_HDL*/ -#ifndef RTW_HALMAC - rtw_intf_start(padapter); -#endif /* !RTW_HALMAC */ } if (padapter->mppriv.mode != MP_OFF) { @@ -4637,7 +5738,7 @@ u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) { struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -4665,6 +5766,7 @@ u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); @@ -4677,10 +5779,10 @@ u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -4709,7 +5811,7 @@ static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr) struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; u8 *str = NULL; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -4745,6 +5847,7 @@ static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr) rtw_mfree(str, RTW_CUSTOMER_STR_LEN); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); @@ -4755,10 +5858,10 @@ static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr) if (res == _SUCCESS) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -4778,30 +5881,31 @@ inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr) } #endif /* CONFIG_RTW_CUSTOMER_STR */ -u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type) +u8 rtw_c2h_wk_cmd(_adapter *padapter, u8 *pbuf, u16 length, u8 type) { - struct cmd_obj *ph2c; + struct cmd_obj *cmd; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; u8 *extra_cmd_buf; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } extra_cmd_buf = rtw_zmalloc(length); if (extra_cmd_buf == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd, sizeof(struct cmd_obj)); rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); res = _FAIL; goto exit; @@ -4813,31 +5917,23 @@ u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type) pdrvextra_cmd_parm->size = length; pdrvextra_cmd_parm->pbuf = extra_cmd_buf; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); exit: return res; } -#ifdef CONFIG_FW_C2H_REG -inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt) -{ - return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG); -} -#endif - -#ifdef CONFIG_FW_C2H_PKT +#define C2H_TYPE_PKT 1 inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length) { return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT); } -#endif static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms) { - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct cmd_obj *cmdobj; struct RunInThread_param *parm; struct submit_ctx sctx; @@ -4848,6 +5944,7 @@ static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void * res = _FAIL; goto exit; } + cmdobj->padapter = adapter; parm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param)); if (NULL == parm) { @@ -4869,10 +5966,10 @@ static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void * if (res == _SUCCESS && timeout_ms >= 0) { rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&cmdpriv->sctx_mutex, NULL); + _rtw_mutex_lock_interruptible(&cmdpriv->sctx_mutex); if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; - _exit_critical_mutex(&cmdpriv->sctx_mutex, NULL); + _rtw_mutex_unlock(&cmdpriv->sctx_mutex); if (sctx.status != RTW_SCTX_DONE_SUCCESS) res = _FAIL; } @@ -4880,7 +5977,6 @@ static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void * exit: return res; } - u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context) { return _rtw_run_in_thread_cmd(adapter, func, context, -1); @@ -4891,36 +5987,10 @@ u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *con return _rtw_run_in_thread_cmd(adapter, func, context, timeout_ms); } -#ifdef CONFIG_FW_C2H_REG -s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter) -{ - s32 ret = _FAIL; - u8 buf[C2H_REG_LEN] = {0}; - u8 id, seq, plen; - u8 *payload; - - if (!c2h_evt) { - /* No c2h event in cmd_obj, read c2h event before handling*/ - if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS) - goto exit; - c2h_evt = buf; - } - - rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload); - - if (filter && filter(adapter, id, seq, plen, payload) == _FALSE) - goto exit; - - ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload); - -exit: - return ret; -} -#endif /* CONFIG_FW_C2H_REG */ u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) { - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct cmd_obj *cmdobj; struct drvextra_cmd_parm *cmd_parm; struct st_cmd_parm *st_parm; @@ -4931,6 +6001,7 @@ u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *loca res = _FAIL; goto exit; } + cmdobj->padapter = adapter; cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (cmd_parm == NULL) { @@ -4988,7 +6059,6 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) { struct st_ctl_t *st_ctl = &sta->st_ctl; int i; - _irqL irqL; _list *plist, *phead, *pnext; _list dlist; struct session_tracker *st = NULL; @@ -5009,7 +6079,7 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) _rtw_init_listhead(&dlist); - _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinlock_bh(&st_ctl->tracker_q.lock); phead = &st_ctl->tracker_q.queue; plist = get_next(phead); @@ -5047,7 +6117,7 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) #endif } - _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinunlock_bh(&st_ctl->tracker_q.lock); plist = get_next(&dlist); while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { @@ -5071,11 +6141,10 @@ void session_tracker_chk_for_adapter(_adapter *adapter) struct sta_priv *stapriv = &adapter->stapriv; struct sta_info *sta; int i; - _irqL irqL; _list *plist, *phead; u8 op_wfd_mode = MIRACAST_DISABLED; - _enter_critical_bh(&stapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&stapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(stapriv->sta_hash[i]); @@ -5091,7 +6160,7 @@ void session_tracker_chk_for_adapter(_adapter *adapter) } } - _exit_critical_bh(&stapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&stapriv->sta_hash_lock); #ifdef CONFIG_WFD adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode); @@ -5118,7 +6187,6 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) u32 remote_naddr = parm->remote_naddr; u16 remote_port = parm->remote_port; struct session_tracker *st = NULL; - _irqL irqL; _list *plist, *phead; u8 free_st = 0; u8 alloc_st = 0; @@ -5135,7 +6203,7 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) st_ctl = &sta->st_ctl; - _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinlock_bh(&st_ctl->tracker_q.lock); phead = &st_ctl->tracker_q.queue; plist = get_next(phead); @@ -5167,7 +6235,7 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) } unlock: - _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinunlock_bh(&st_ctl->tracker_q.lock); if (free_st) { rtw_mfree((u8 *)st, sizeof(struct session_tracker)); @@ -5186,9 +6254,9 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) st->set_time = rtw_get_current_time(); st->status = ST_STATUS_CHECK; - _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinlock_bh(&st_ctl->tracker_q.lock); rtw_list_insert_tail(&st->list, phead); - _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinunlock_bh(&st_ctl->tracker_q.lock); } } @@ -5228,7 +6296,7 @@ u8 rtw_req_per_cmd(_adapter *adapter) { struct cmd_obj *cmdobj; struct drvextra_cmd_parm *parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -5249,6 +6317,7 @@ u8 rtw_req_per_cmd(_adapter *adapter) rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } + cmdobj->padapter = adapter; init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA); @@ -5269,22 +6338,22 @@ void rtw_ac_parm_cmd_hdl(_adapter *padapter, u8 *_ac_parm_buf, int ac_type) switch (ac_type) { case XMIT_VO_QUEUE: RTW_INFO(FUNC_NDEV_FMT" AC_VO = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&ac_parm_buf)); + rtw_ap_set_edca(padapter, 3, ac_parm_buf); break; case XMIT_VI_QUEUE: RTW_INFO(FUNC_NDEV_FMT" AC_VI = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&ac_parm_buf)); + rtw_ap_set_edca(padapter, 2, ac_parm_buf); break; case XMIT_BE_QUEUE: RTW_INFO(FUNC_NDEV_FMT" AC_BE = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&ac_parm_buf)); + rtw_ap_set_edca(padapter, 0, ac_parm_buf); break; case XMIT_BK_QUEUE: RTW_INFO(FUNC_NDEV_FMT" AC_BK = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&ac_parm_buf)); + rtw_ap_set_edca(padapter, 1, ac_parm_buf); break; default: @@ -5293,7 +6362,6 @@ void rtw_ac_parm_cmd_hdl(_adapter *padapter, u8 *_ac_parm_buf, int ac_type) } - u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) { int ret = H2C_SUCCESS; @@ -5308,13 +6376,16 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) case STA_MSTATUS_RPT_WK_CID: rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf); break; - + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ case DYNAMIC_CHK_WK_CID:/*only primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */ rtw_dynamic_chk_wk_hdl(padapter); break; + #endif + #ifdef CONFIG_POWER_SAVING case POWER_SAVING_CTRL_WK_CID: power_saving_wk_hdl(padapter); break; + #endif #ifdef CONFIG_LPS case LPS_CTRL_WK_CID: lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type, pdrvextra_cmd->pbuf); @@ -5326,11 +6397,6 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type); break; #endif -#if (RATE_ADAPTIVE_SUPPORT == 1) - case RTP_TIMER_CFG_WK_CID: - rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type); - break; -#endif #ifdef CONFIG_ANTENNA_DIVERSITY case ANT_SELECT_WK_CID: antenna_select_wk_hdl(padapter, pdrvextra_cmd->type); @@ -5341,15 +6407,6 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type); break; #endif -#ifdef CONFIG_P2P - case P2P_PROTO_WK_CID: - /* - * Commented by Albert 2011/07/01 - * I used the type_size as the type command - */ - ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); - break; -#endif #ifdef CONFIG_AP_MODE case CHECK_HIQ_WK_CID: rtw_chk_hi_queue_hdl(padapter); @@ -5364,38 +6421,16 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) break; case C2H_WK_CID: switch (pdrvextra_cmd->type) { - #ifdef CONFIG_FW_C2H_REG - case C2H_TYPE_REG: - c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL); - break; - #endif - #ifdef CONFIG_FW_C2H_PKT case C2H_TYPE_PKT: rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); break; - #endif default: RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type); rtw_warn_on(1); break; } break; -#ifdef CONFIG_BEAMFORMING - case BEAMFORMING_WK_CID: - beamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); - break; -#endif - case DM_RA_MSK_WK_CID: - rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf); - break; -#ifdef CONFIG_BT_COEXIST - case BTINFO_WK_CID: - rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); - break; - case BTC_REDUCE_WL_TXPWR_CID: - rtw_btc_reduce_wl_txpwr_hdl(padapter, pdrvextra_cmd->type); - break; -#endif + #ifdef CONFIG_DFS_MASTER case DFS_RADAR_DETECT_WK_CID: rtw_dfs_rd_hdl(padapter); @@ -5407,12 +6442,6 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) case SESSION_TRACKER_WK_CID: session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf); break; - case EN_HW_UPDATE_TSF_WK_CID: - rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL); - break; - case PERIOD_TSF_UPDATE_END_WK_CID: - rtw_hal_periodic_tsf_update_chk(padapter); - break; case TEST_H2C_CID: rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]); break; @@ -5427,29 +6456,11 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) break; #endif -#ifdef CONFIG_RTW_REPEATER_SON - case RSON_SCAN_WK_CID: - rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type); - break; -#endif - #ifdef CONFIG_IOCTL_CFG80211 case MGNT_TX_WK_CID: ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf); break; #endif /* CONFIG_IOCTL_CFG80211 */ - -#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) - case ROCH_WK_CID: - ret = rtw_roch_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); - break; -#endif /* (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) */ - -#ifdef CONFIG_MCC_MODE - case MCC_CMD_WK_CID: - ret = rtw_mcc_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); - break; -#endif /* CONFIG_MCC_MODE */ #if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) case REQ_PER_CMD_WK_CID: ret = rtw_req_per_cmd_hdl(padapter); @@ -5477,6 +6488,16 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) case TBTX_CONTROL_TX_WK_CID: tx_control_hdl(padapter); break; +#endif +#ifdef ROKU_PRIVATE + case FIND_REMOTE_WK_CID: + ret = issue_action_find_remote(padapter); + break; +#ifdef CONFIG_P2P + case HIDE_SSID_WK_CID: + issue_beacon(padapter, 0); + break; +#endif #endif default: break; @@ -5488,33 +6509,16 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) return ret; } -void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd) -{ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - - if (pcmd->res == H2C_DROPPED) { - /* TODO: cancel timer and do timeout handler directly... */ - /* need to make timeout handlerOS independent */ - mlme_set_scan_to_timer(pmlmepriv, 1); - } else if (pcmd->res != H2C_SUCCESS) { - mlme_set_scan_to_timer(pmlmepriv, 1); - } - - /* free cmd */ - rtw_free_cmd_obj(pcmd); -} -void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) +void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) { - _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (pcmd->res != H2C_SUCCESS) { - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); set_fwstate(pmlmepriv, WIFI_ASOC_STATE); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); goto exit; } #ifdef CONFIG_BR_EXT @@ -5528,8 +6532,7 @@ void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) exit: return; } - -void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) +void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -5537,38 +6540,35 @@ void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) if (pcmd->res == H2C_DROPPED) { /* TODO: cancel timer and do timeout handler directly... */ /* need to make timeout handlerOS independent */ - _set_timer(&pmlmepriv->assoc_timer, 1); + set_assoc_timer(pmlmepriv, 1); /*_set_timer(&pmlmepriv->assoc_timer, 1);*/ } else if (pcmd->res != H2C_SUCCESS) - _set_timer(&pmlmepriv->assoc_timer, 1); + set_assoc_timer(pmlmepriv, 1); /*_set_timer(&pmlmepriv->assoc_timer, 1);*/ rtw_free_cmd_obj(pcmd); - } void rtw_create_ibss_post_hdl(_adapter *padapter, int status) { - _irqL irqL; struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network); if (status != H2C_SUCCESS) - _set_timer(&pmlmepriv->assoc_timer, 1); + set_assoc_timer(pmlmepriv, 1); /*_set_timer(&pmlmepriv->assoc_timer, 1);*/ - _cancel_timer_ex(&pmlmepriv->assoc_timer); + /*_cancel_timer_ex(&pmlmepriv->assoc_timer);*/ + cancel_assoc_timer(pmlmepriv); - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); { - _irqL irqL; - pwlan = _rtw_alloc_network(pmlmepriv); - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); if (pwlan == NULL) { pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); if (pwlan == NULL) { - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); goto createbss_cmd_fail; } pwlan->last_scanned = rtw_get_current_time(); @@ -5588,18 +6588,18 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status) #endif _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); /* we will set WIFI_ASOC_STATE when there is one more sat to join us (rtw_stassoc_event_callback) */ } createbss_cmd_fail: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); return; } -void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) +void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) { struct sta_priv *pstapriv = &padapter->stapriv; @@ -5611,7 +6611,7 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) goto exit; } - /* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ + /* psta->phl_sta->aid = psta->phl_sta->macid = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ exit: @@ -5620,7 +6620,7 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) } -void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) +void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { rtw_free_cmd_obj(pcmd); @@ -5636,7 +6636,7 @@ u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type) { struct cmd_obj *cmdobj; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; u8 *ac_parm_buf = NULL; u8 sz; u8 res = _SUCCESS; @@ -5647,6 +6647,7 @@ u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type) res = _FAIL; goto exit; } + cmdobj->padapter = adapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { @@ -5678,33 +6679,210 @@ u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type) return res; } -/* Driver writes beacon length to REG for FW adjusting beacon receive time */ -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW -u8 rtw_write_bcnlen_to_fw_cmd(_adapter *padapter, u16 bcn_len) +char UNKNOWN_CID[16] = "UNKNOWN_EXTRA"; +char *rtw_extra_name(struct drvextra_cmd_parm *pdrvextra_cmd) { - struct cmd_obj *pcmd; - struct write_bcnlen_param *parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; + switch(pdrvextra_cmd->ec_id) { + case NONE_WK_CID: + return "NONE_WK_CID"; + break; + case STA_MSTATUS_RPT_WK_CID: + return "STA_MSTATUS_RPT_WK_CID"; + break; + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + case DYNAMIC_CHK_WK_CID: + return "DYNAMIC_CHK_WK_CID"; + break; + #endif + case DM_CTRL_WK_CID: + return "DM_CTRL_WK_CID"; + break; + case PBC_POLLING_WK_CID: + return "PBC_POLLING_WK_CID"; + break; + #ifdef CONFIG_POWER_SAVING + case POWER_SAVING_CTRL_WK_CID: + return "POWER_SAVING_CTRL_WK_CID"; + #endif + break; + case LPS_CTRL_WK_CID: + return "LPS_CTRL_WK_CID"; + break; + case ANT_SELECT_WK_CID: + return "ANT_SELECT_WK_CID"; + break; + case P2P_PS_WK_CID: + return "P2P_PS_WK_CID"; + break; + case CHECK_HIQ_WK_CID: + return "CHECK_HIQ_WK_CID"; + break; + case C2H_WK_CID: + return "C2H_WK_CID"; + break; + case RESET_SECURITYPRIV: + return "RESET_SECURITYPRIV"; + break; + case FREE_ASSOC_RESOURCES: + return "FREE_ASSOC_RESOURCES"; + break; + case DM_IN_LPS_WK_CID: + return "DM_IN_LPS_WK_CID"; + break; + case LPS_CHANGE_DTIM_CID: + return "LPS_CHANGE_DTIM_CID"; + break; + case DFS_RADAR_DETECT_WK_CID: + return "DFS_RADAR_DETECT_WK_CID"; + break; + case DFS_RADAR_DETECT_EN_DEC_WK_CID: + return "DFS_RADAR_DETECT_EN_DEC_WK_CID"; + break; + case SESSION_TRACKER_WK_CID: + return "SESSION_TRACKER_WK_CID"; + break; + case TEST_H2C_CID: + return "TEST_H2C_CID"; + break; + case MP_CMD_WK_CID: + return "MP_CMD_WK_CID"; + break; + case CUSTOMER_STR_WK_CID: + return "CUSTOMER_STR_WK_CID"; + break; + case MGNT_TX_WK_CID: + return "MGNT_TX_WK_CID"; + break; + case REQ_PER_CMD_WK_CID: + return "REQ_PER_CMD_WK_CID"; + break; + case SSMPS_WK_CID: + return "SSMPS_WK_CID"; + break; +#ifdef CONFIG_CTRL_TXSS_BY_TP + case TXSS_WK_CID: + return "TXSS_WK_CID"; + break; +#endif + case AC_PARM_CMD_WK_CID: + return "AC_PARM_CMD_WK_CID"; + break; +#ifdef CONFIG_AP_MODE + case STOP_AP_WK_CID: + return "STOP_AP_WK_CID"; + break; +#endif +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT + case TBTX_CONTROL_TX_WK_CID: + return "TBTX_CONTROL_TX_WK_CID"; + break; +#endif +#ifdef ROKU_PRIVATE + case FIND_REMOTE_WK_CID: + return "FIND_REMOTE_WK_CID"; + break; +#ifdef CONFIG_P2P + case HIDE_SSID_WK_CID: + return "HIDE_SSID_WK_CID"; + break; +#endif +#endif + case MAX_WK_CID: + return "MAX_WK_CID"; + break; + default: + return UNKNOWN_CID; + break; + } + return UNKNOWN_CID; +} - pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd == NULL) { +char UNKNOWN_CMD[16] = "UNKNOWN_CMD"; +char *rtw_cmd_name(struct cmd_obj *pcmd) +{ + struct rtw_evt_header *pev; + + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) + return UNKNOWN_CMD; + + if (pcmd->cmdcode == CMD_SET_MLME_EVT) + return rtw_evt_name((struct rtw_evt_header*)pcmd->parmbuf); + + if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) + return rtw_extra_name((struct drvextra_cmd_parm*)pcmd->parmbuf); + + return wlancmds[pcmd->cmdcode].name; +} + +#ifdef ROKU_PRIVATE +u8 rtw_find_remote_wk_cmd(_adapter *adapter) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { res = _FAIL; goto exit; } - parm = (struct write_bcnlen_param *)rtw_zmalloc(sizeof(struct write_bcnlen_param)); - if (parm == NULL) { - rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + cmdobj->padapter = adapter; + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } - parm->bcn_len = bcn_len; - init_h2fwcmd_w_parm_no_rsp(pcmd, parm, CMD_WRITE_BCN_LEN); - res = rtw_enqueue_cmd(pcmdpriv, pcmd); + pdrvextra_cmd_parm->ec_id = FIND_REMOTE_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + +exit: + return res; +} + +#ifdef CONFIG_P2P +u8 rtw_hide_ssid_wk_cmd(_adapter *adapter) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + cmdobj->padapter = adapter; + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = HIDE_SSID_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); exit: return res; + } -#endif /* CONFIG_WRITE_BCN_LEN_TO_FW */ +#endif +#endif diff --git a/core/rtw_csa.c b/core/rtw_csa.c new file mode 100644 index 0000000..eba91af --- /dev/null +++ b/core/rtw_csa.c @@ -0,0 +1,484 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_CSA_C_ +#include + +#if CONFIG_DFS +void reset_csa_param(struct rf_ctl_t *rfctl) +{ + rfctl->csa_mode = 0; + rfctl->csa_switch_cnt = 0; + rfctl->csa_ch_width = 0; + _rtw_memset(&(rfctl->csa_chandef), 0, sizeof(struct rtw_chan_def)); +} + +/* Get ch/bw/offset of CSA from rfctl, and check these parameters is valid or not */ +bool rtw_get_csa_setting(struct dvobj_priv *d, s16 *req_ch, u8 *req_bw, u8 *req_offset) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(d); + struct _ADAPTER *a = dvobj_get_primary_adapter(d); + u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(a); + bool valid = _TRUE; + + *req_ch = REQ_CH_NONE; + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + + if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_chandef.chan) >= 0 + && !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_chandef.chan) + ) { + /* CSA channel available and valid */ + *req_ch = rfctl->csa_chandef.chan; + RTW_INFO("CSA : "FUNC_ADPT_FMT" valid CSA ch%u\n", FUNC_ADPT_ARG(a), + rfctl->csa_chandef.chan); + } else if (ifbmp_m) { + /* no available or valid CSA channel, having AP/MESH ifaces */ + *req_ch = REQ_CH_NONE; + valid = _FALSE; + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch sel by AP/MESH ifaces\n", FUNC_ADPT_ARG(a)); + goto exit; + } else { + /* no available or valid CSA channel and no AP/MESH ifaces */ + if (!is_supported_24g(dvobj_to_regsty(d)->band_type)) + *req_ch = 36; + else + *req_ch = 1; + valid = _FALSE; + RTW_INFO("CSA : "FUNC_ADPT_FMT" switch to ch%d, then disconnect with AP\n", + FUNC_ADPT_ARG(a), *req_ch); + goto exit; + } + + if (rfctl->csa_ch_width == 1) { + *req_bw = CHANNEL_WIDTH_80; + *req_offset = rfctl->csa_chandef.offset; + } else if (rfctl->csa_ch_width == 0 && rfctl->csa_chandef.offset != CHAN_OFFSET_NO_EXT) { + *req_bw = CHANNEL_WIDTH_40; + *req_offset = rfctl->csa_chandef.offset; + } else { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + } + + /* get correct offset and check ch/bw/offset is valid or not */ + if (!rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset)) { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + } + +exit: + return valid; +} + +#ifdef CONFIG_ECSA_PHL +static void reset_ecsa_param(struct _ADAPTER *a) +{ + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + + SET_ECSA_STATE(a, ECSA_ST_NONE); + ecsa_info->ecsa_allow_case = 0; + ecsa_info->ecsa_delay_time = 0; + ecsa_info->channel_width = 0; + ecsa_info->bss_param = NULL; + _rtw_memset(ecsa_param, 0, sizeof(struct rtw_phl_ecsa_param)); +} + +bool rtw_mr_is_ecsa_running(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct _ADAPTER *iface; + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + u8 i; + + for (i = 0; i < d->iface_nums; i++) { + iface = d->padapters[i]; + if (!iface) + continue; + if (!CHK_ECSA_STATE(iface, ECSA_ST_NONE)) + return _TRUE; + } + return _FALSE; +} + +static void rtw_ecsa_update_sta_chan_info(struct _ADAPTER *a, struct rtw_chan_def new_chan_def) +{ + struct mlme_ext_priv *pmlmeext = &a->mlmeextpriv; + struct mlme_priv *pmlmepriv = &a->mlmepriv; + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(d); + u8 new_ch = new_chan_def.chan; + u8 new_bw = (u8)new_chan_def.bw; + u8 new_offset = (u8)new_chan_def.offset; + bool is_chctx_add = _FALSE; + + pmlmeext->chandef.chan= new_ch; + pmlmeext->chandef.bw = new_bw; + pmlmeext->chandef.offset = new_offset; + pmlmepriv->cur_network.network.Configuration.DSConfig = new_ch; + + /* update wifi role chandef */ + rtw_hw_update_chan_def(a); + + /* update chanctx */ + rtw_phl_chanctx_del(d->phl, a->phl_role, NULL); + is_chctx_add = rtw_phl_chanctx_add(d->phl, a->phl_role, + &new_chan_def.chan, &new_chan_def.bw, &new_chan_def.offset); + if (is_chctx_add == _FALSE) + RTW_ERR("CSA : "FUNC_ADPT_FMT" chan_ctx add fail!", FUNC_ADPT_ARG(a)); + + set_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON); + + /* STA wait 70 seconds for receiving beacons in DFS channel */ + if (rtw_chset_is_dfs_chbw(rfctl->channel_set, new_ch, new_bw, new_offset)) { + RTW_INFO("CSA : set csa_timer to 70 seconds\n"); + _set_timer(&pmlmeext->csa_timer, CAC_TIME_MS + 10000); + } + + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(a, MLME_OPCH_SWITCH, 0); + #endif +} + +static void rtw_ecsa_update_ap_chan_info(struct _ADAPTER *a, struct rtw_chan_def new_chan_def) +{ + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct createbss_parm *parm; + + ecsa_info->bss_param = (struct createbss_parm *)rtw_zmalloc(sizeof(struct createbss_parm)); + if (ecsa_info->bss_param) { + parm = ecsa_info->bss_param; + parm->adhoc = 0; + parm->ifbmp = BIT(a->iface_id); + parm->excl_ifbmp = 0; + parm->req_ch = new_chan_def.chan; + parm->req_bw = new_chan_def.bw; + parm->req_offset = new_chan_def.offset; + parm->ifbmp_ch_changed = 0; + parm->ch_to_set = 0; + parm->bw_to_set = 0; + parm->offset_to_set = 0; + parm->do_rfk = _FALSE; + + start_bss_network(a, parm); + } else { + RTW_ERR("CSA : can't allocate memory for bss_param\n"); + } +} + +void rtw_ecsa_update_probe_resp(struct xmit_frame *xframe) +{ + struct _ADAPTER *a = xframe->padapter; + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + struct pkt_attrib *pattrib = &xframe->attrib; + u8 hdr_len = sizeof(struct rtw_ieee80211_hdr_3addr); + u8 *ies; + sint ies_len; + u8 *csa_ie; + sint csa_ie_len; + + ies = xframe->buf_addr + TXDESC_OFFSET + hdr_len + _BEACON_IE_OFFSET_; + ies_len = pattrib->pktlen - hdr_len - _BEACON_IE_OFFSET_; + + csa_ie = rtw_get_ie(ies, WLAN_EID_CHANNEL_SWITCH, &csa_ie_len, ies_len); + + if (csa_ie == NULL) + return; + + csa_ie[2 + CSA_SWITCH_COUNT] = ecsa_param->count; + + #ifdef DBG_CSA + RTW_INFO("CSA : update csa count of probe response = %u\n", csa_ie[2 + CSA_SWITCH_COUNT]); + #endif +} + +void rtw_ecsa_update_beacon(void *priv, struct rtw_wifi_role_t *role) +{ +#ifdef CONFIG_AP_MODE + struct dvobj_priv *d = (struct dvobj_priv *)priv; + struct _ADAPTER *a = d->padapters[role->id]; + _update_beacon(a, WLAN_EID_CHANNEL_SWITCH, NULL, _TRUE, 0, "update CSA count"); +#endif +} + +/* PHL MR module check core layer if AP mode can switch channel now */ +bool rtw_ap_check_ecsa_allow( + void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def, + enum phl_ecsa_start_reason reason, + u32 *delay_start_ms +) +{ + struct dvobj_priv *d = (struct dvobj_priv *)priv; + struct _ADAPTER *a = d->padapters[role->id]; + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + bool ecsa_allow = _TRUE; + u8 i; + + /* TODO : need to check MCC-ECSA case */ + /* if (!(ecsa_info->ecsa_allow_case & BIT(reason))) { */ + if (0) { + RTW_INFO("CSA : "FUNC_ADPT_FMT" : Case %u not support!\n", FUNC_ADPT_ARG(a), reason); + ecsa_allow = _FALSE; + goto exit; + } + + /* Check DFS channel */ + if (!rtw_phl_regulation_valid_channel(GET_PHL_INFO(d), + chan_def.band, + chan_def.chan, + (CH_PASSIVE | CH_DFS))) { + RTW_ERR("CSA : "FUNC_ADPT_FMT" : DFS channel (%u) not support!\n", + FUNC_ADPT_ARG(a), chan_def.chan); + ecsa_allow = _FALSE; + goto exit; + } + + if (ecsa_info->ecsa_delay_time != 0) + *delay_start_ms = ecsa_info->ecsa_delay_time; + else if (reason <= ECSA_START_MCC_5G_TO_24G) + *delay_start_ms = MCC_ECSA_DELAY_START_TIME; + RTW_INFO("CSA : %s : ECSA will delay %u ms\n", __func__, *delay_start_ms); + + SET_ECSA_STATE(a, ECSA_ST_SW_START); +exit: + return ecsa_allow; +} + +void rtw_ecsa_mr_update_chan_info_by_role( + void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def new_chan_def +) +{ + struct dvobj_priv *d = (struct dvobj_priv *)priv; + struct _ADAPTER *a = d->padapters[role->id]; + struct mlme_ext_priv *pmlmeext = &a->mlmeextpriv; + struct mlme_priv *pmlmepriv = &a->mlmepriv; + + RTW_INFO("CSA : "FUNC_ADPT_FMT", new ch/bw/offset = %u,%u,%u\n", FUNC_ADPT_ARG(a), \ + new_chan_def.chan, new_chan_def.bw, new_chan_def.offset); + + if (role->type == PHL_RTYPE_STATION || role->type == PHL_RTYPE_P2P_GC) + rtw_ecsa_update_sta_chan_info(a, new_chan_def); + else if (role->type == PHL_RTYPE_AP ||role->type == PHL_RTYPE_P2P_GO) + rtw_ecsa_update_ap_chan_info(a, new_chan_def); +} + +bool rtw_ecsa_check_tx_resume_allow(void *priv, struct rtw_wifi_role_t *role) +{ + /* TODO */ + /* Is DFS slave still monitoring channel ? + If Yes, return False to PHL; If no, return True to PHL */ + struct dvobj_priv *d = (struct dvobj_priv *)priv; + struct _ADAPTER *a = d->padapters[role->id]; + + RTW_INFO("CSA : "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(a)); + return 1; +} + +void rtw_ecsa_complete(void *priv, struct rtw_wifi_role_t *role) +{ + struct dvobj_priv *d = (struct dvobj_priv *)priv; + struct _ADAPTER *a = d->padapters[role->id]; + struct rf_ctl_t *rfctl = dvobj_to_rfctl(d); + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct createbss_parm *parm = ecsa_info->bss_param; + u8 i, ht_option = 0; + + RTW_INFO("CSA : "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(a)); + rtw_phl_mr_dump_cur_chandef(d->phl, role); + + if (role->type == PHL_RTYPE_STATION || role->type == PHL_RTYPE_P2P_GC) { + /* + * TODO + * STA mode need to update RA if it receive CHANNEL_SWITCH_WRAPPER IE + * STA mode update its RA at rtw_check_bcn_info() now + */ + rtw_rfctl_update_op_mode(rfctl, 0, 0); + } else if (role->type == PHL_RTYPE_AP ||role->type == PHL_RTYPE_P2P_GO) { + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + for (i = 0; i < d->iface_nums; i++) { + if (!(parm->ifbmp_ch_changed & BIT(i)) || !d->padapters[i]) + continue; + + #ifdef CONFIG_80211N_HT + ht_option = d->padapters[i]->mlmepriv.htpriv.ht_option; + #endif + + rtw_cfg80211_ch_switch_notify(d->padapters[i] + , d->padapters[i]->mlmeextpriv.chandef.chan + , d->padapters[i]->mlmeextpriv.chandef.bw + , d->padapters[i]->mlmeextpriv.chandef.offset + , ht_option, 0); + } + #endif + rtw_rfctl_update_op_mode(adapter_to_rfctl(a), parm->ifbmp, 1); + + rtw_core_ap_start(a, parm); + + rtw_ap_update_clients_rainfo(a, PHL_CMD_DIRECTLY); + + rtw_mfree((u8 *)parm, sizeof(struct createbss_parm)); + } + + rtw_mi_os_xmit_schedule(a); + + reset_ecsa_param(a); +} + +/* Get ch/bw/offset of CSA from adapter, and check these parameters is valid or not */ +static bool rtw_sta_get_ecsa_setting(struct _ADAPTER *a, s16 *req_ch, u8 *req_bw, u8 *req_offset) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(a); + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(a); + u8 csa_chan = ecsa_param->new_chan_def.chan; + u8 csa_offset = ecsa_param->new_chan_def.offset; + bool valid = _TRUE; + + *req_ch = REQ_CH_NONE; + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + + if (rtw_chset_search_ch(rfctl->channel_set, csa_chan) >= 0 + && !rtw_chset_is_ch_non_ocp(rfctl->channel_set, csa_chan) + ) { + /* CSA channel available and valid */ + *req_ch = csa_chan; + RTW_INFO("CSA : "FUNC_ADPT_FMT" valid CSA ch%u\n", FUNC_ADPT_ARG(a), csa_chan); + } else if (ifbmp_m) { + /* no available or valid CSA channel, having AP/MESH ifaces */ + *req_ch = REQ_CH_NONE; + valid = _FALSE; + RTW_INFO("CSA : "FUNC_ADPT_FMT" ch sel by AP/MESH ifaces\n", FUNC_ADPT_ARG(a)); + goto exit; + } else { + /* no available or valid CSA channel and no AP/MESH ifaces */ + /* TODO : DFS slave may need to switch channel as soon as possible before disconnect */ + #if 0 + if (!is_supported_24g(adapter_to_regsty(a)->band_type)) + *req_ch = 36; + else + *req_ch = 1; + #endif + valid = _FALSE; + RTW_INFO("CSA : "FUNC_ADPT_FMT" switch to ch %d, then disconnect with AP\n", + FUNC_ADPT_ARG(a), *req_ch); + goto exit; + } + + /* Transform channel_width to bandwidth 20/40/80M */ + if (ecsa_info->channel_width == 1) { + *req_bw = CHANNEL_WIDTH_80; + *req_offset = csa_offset; + } else if (ecsa_info->channel_width == 0 && csa_offset != CHAN_OFFSET_NO_EXT) { + *req_bw = CHANNEL_WIDTH_40; + *req_offset = csa_offset; + } else { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + } + + /* Get correct offset and check ch/bw/offset is valid or not */ + if (!rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset)) { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = CHAN_OFFSET_NO_EXT; + } + + /* Update result to ecsa_param */ + ecsa_param->new_chan_def.chan = *req_ch; + ecsa_param->new_chan_def.bw = *req_bw; + ecsa_param->new_chan_def.offset = *req_offset; + +exit: + return valid; +} + +static void rtw_sta_ecsa_invalid_hdl(struct _ADAPTER *a, s16 req_ch, u8 req_bw, u8 req_offset) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(d); + u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(a); + struct rtw_chan_def mr_chdef = {0}; + + if (!ifbmp_s) + return; + + set_fwstate(&a->mlmepriv, WIFI_OP_CH_SWITCHING); + issue_deauth(a, get_bssid(&a->mlmepriv), WLAN_REASON_DEAUTH_LEAVING); + + /* Decide whether enable DFS slave radar detection or not */ + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(a, MLME_OPCH_SWITCH, ifbmp_s); + #endif + + /* TODO : DFS slave may need to switch channel as soon as possible before disconnect */ + + /* This context can't I/O, so use RTW_CMDF_DIRECTLY */ + rtw_disassoc_cmd(a, 0, RTW_CMDF_DIRECTLY); + rtw_indicate_disconnect(a, 0, _FALSE); + #ifndef CONFIG_STA_CMD_DISPR + rtw_free_assoc_resources(a, _TRUE); + #endif + rtw_free_network_queue(a, _TRUE); + RTW_INFO("CSA : "FUNC_ADPT_FMT" disconnect with AP\n", FUNC_ADPT_ARG(a)); + + reset_ecsa_param(a); + + rtw_mi_os_xmit_schedule(a); +} + +void rtw_trigger_phl_ecsa_start(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + + /* STA need to check ecsa setting */ + if (ecsa_param->ecsa_type == ECSA_TYPE_STA) { + s16 req_ch; + u8 req_bw, req_offset; + + if (!rtw_sta_get_ecsa_setting(a, &req_ch, &req_bw, &req_offset)) { + /* we should handle error case by core layer self */ + rtw_sta_ecsa_invalid_hdl(a, req_ch, req_bw, req_offset); + return; + } + } + + if (rtw_phl_ecsa_start(GET_PHL_INFO(d), role, ecsa_param) != RTW_PHL_STATUS_SUCCESS) + RTW_ERR("CSA : Start PHL ECSA fail\n"); + +#if 0 /* TODO : ECSA */ + if(0) { + if(!rtw_phl_get_chandef_from_operating_class(param.ch, + param.op_class, + &(param.new_chan_def))){ + RTW_INFO("[CSA] Get chandef fail!Use 20 MHz to switch\n"); + param.new_chan_def.band = rtw_phl_get_band_type(param.ch); + param.new_chan_def.chan = param.ch; + param.new_chan_def.bw = CHANNEL_WIDTH_20; + param.new_chan_def.offset = CHAN_OFFSET_NO_EXT; + } + } +#endif +} +#endif /* CONFIG_ECSA_PHL */ +#endif /* CONFIG_DFS */ diff --git a/core/rtw_debug.c b/core/rtw_debug.c index f2eea7a..91dc0d4 100644 --- a/core/rtw_debug.c +++ b/core/rtw_debug.c @@ -15,7 +15,7 @@ #define _RTW_DEBUG_C_ #include -#include +#include "_hal_rate.h" #ifdef CONFIG_RTW_DEBUG const char *rtw_log_level_str[] = { @@ -42,22 +42,26 @@ const char *rtw_log_level_str[] = { void dump_drv_version(void *sel) { RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION); - // RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); + RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); } -#ifdef CONFIG_PROC_DEBUG void dump_drv_cfg(void *sel) { -extern uint rtw_recvbuf_nr; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) char *kernel_version = utsname()->release; RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version); #endif +#ifdef CONFIG_RTW_ANDROID + RTW_PRINT_SEL(sel, "Android Driver: %d\n", CONFIG_RTW_ANDROID); +#else + RTW_PRINT_SEL(sel, "Linux Driver: \n"); +#endif /* CONFIG_RTW_ANDROID */ + RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION); RTW_PRINT_SEL(sel, "------------------------------------------------\n"); + #ifdef CONFIG_IOCTL_CFG80211 RTW_PRINT_SEL(sel, "CFG80211\n"); #ifdef RTW_USE_CFG80211_STA_EVENT @@ -77,6 +81,19 @@ extern uint rtw_recvbuf_nr; #ifdef CONFIG_CONCURRENT_MODE RTW_PRINT_SEL(sel, "CONFIG_CONCURRENT_MODE\n"); + + #ifdef CONFIG_RTW_STATIC_NDEV_NUM + RTW_PRINT_SEL(sel, "CONFIG_RTW_STATIC_NDEV_NUM = %d\n", CONFIG_RTW_STATIC_NDEV_NUM); + #endif + #if (RTW_P2P_GROUP_INTERFACE == 1) + RTW_PRINT_SEL(sel, "RTW_P2P_GROUP_INTERFACE\n"); + #endif + #ifdef RTW_DEDICATED_P2P_DEVICE + RTW_PRINT_SEL(sel, "RTW_DEDICATED_P2P_DEVICE\n"); + #endif + #if defined(CONFIG_P2P) && defined(CONFIG_SEL_P2P_IFACE) + RTW_PRINT_SEL(sel, "CONFIG_SEL_P2P_IFACE = %d\n", CONFIG_SEL_P2P_IFACE); + #endif #endif #ifdef CONFIG_POWER_SAVING @@ -132,9 +149,7 @@ extern uint rtw_recvbuf_nr; #endif RTW_PRINT_SEL(sel, "CONFIG_RTW_ADAPTIVITY_EN = %d\n", CONFIG_RTW_ADAPTIVITY_EN); -#if (CONFIG_RTW_ADAPTIVITY_EN) - RTW_PRINT_SEL(sel, "ADAPTIVITY_MODE = %s\n", (CONFIG_RTW_ADAPTIVITY_MODE) ? "carrier_sense" : "normal"); -#endif + RTW_PRINT_SEL(sel, "CONFIG_RTW_ADAPTIVITY_MODE = %d\n", CONFIG_RTW_ADAPTIVITY_MODE); #ifdef CONFIG_WOWLAN RTW_PRINT_SEL(sel, "CONFIG_WOWLAN - "); @@ -166,9 +181,6 @@ extern uint rtw_recvbuf_nr; BUSY_TRAFFIC_SCAN_DENY_PERIOD); #endif -#ifdef CONFIG_RTW_TPT_MODE - RTW_PRINT_SEL(sel, "CONFIG_RTW_TPT_MODE\n"); -#endif #ifdef CONFIG_USB_HCI #ifdef CONFIG_SUPPORT_USB_INT @@ -189,9 +201,7 @@ extern uint rtw_recvbuf_nr; #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_RX\n"); #endif -#ifdef CONFIG_PREALLOC_RECV_SKB - RTW_PRINT_SEL(sel, "CONFIG_PREALLOC_RECV_SKB\n"); -#endif + #ifdef CONFIG_FIX_NR_BULKIN_BUFFER RTW_PRINT_SEL(sel, "CONFIG_FIX_NR_BULKIN_BUFFER\n"); #endif @@ -220,40 +230,32 @@ extern uint rtw_recvbuf_nr; #endif RTW_PRINT_SEL(sel, "CONFIG_IFACE_NUMBER = %d\n", CONFIG_IFACE_NUMBER); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - RTW_PRINT_SEL(sel, "CONFIG_MI_WITH_MBSSID_CAM\n"); -#endif -#ifdef CONFIG_SWTIMER_BASED_TXBCN - RTW_PRINT_SEL(sel, "CONFIG_SWTIMER_BASED_TXBCN\n"); -#endif -#ifdef CONFIG_FW_HANDLE_TXBCN - RTW_PRINT_SEL(sel, "CONFIG_FW_HANDLE_TXBCN\n"); - RTW_PRINT_SEL(sel, "CONFIG_LIMITED_AP_NUM = %d\n", CONFIG_LIMITED_AP_NUM); -#endif -#ifdef CONFIG_CLIENT_PORT_CFG - RTW_PRINT_SEL(sel, "CONFIG_CLIENT_PORT_CFG\n"); -#endif + + #ifdef CONFIG_PCI_TX_POLLING RTW_PRINT_SEL(sel, "CONFIG_PCI_TX_POLLING\n"); #endif RTW_PRINT_SEL(sel, "CONFIG_RTW_UP_MAPPING_RULE = %s\n", (CONFIG_RTW_UP_MAPPING_RULE == 1) ? "dscp" : "tos"); + /*GEORGIA_TODO_TRX - need get trx buff accroding to IC spec*/ RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n"); RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME); + /* RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF); RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ); RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF); RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ); RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ); + */ RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n"); RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME); - RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d, rtw_recvbuf_nr = %d\n", NR_RECVBUFF, rtw_recvbuf_nr); + /* + RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d\n", NR_RECVBUFF); RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ); + */ } -#endif /* CONFIG_PROC_DEBUG */ - void dump_log_level(void *sel) { @@ -271,249 +273,21 @@ void dump_log_level(void *sel) #endif } -#ifdef CONFIG_SDIO_HCI -void sd_f0_reg_dump(void *sel, _adapter *adapter) -{ - int i; - - for (i = 0x0; i <= 0xff; i++) { - if (i % 16 == 0) - RTW_PRINT_SEL(sel, "0x%02x ", i); - - _RTW_PRINT_SEL(sel, "%02x ", rtw_sd_f0_read8(adapter, i)); - - if (i % 16 == 15) - _RTW_PRINT_SEL(sel, "\n"); - else if (i % 8 == 7) - _RTW_PRINT_SEL(sel, "\t"); - } -} - -void sdio_local_reg_dump(void *sel, _adapter *adapter) -{ - int i, j = 1; - - for (i = 0x0; i < 0x100; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%02x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, (0x1025 << 16) | i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -} -#endif /* CONFIG_SDIO_HCI */ - -void mac_reg_dump(void *sel, _adapter *adapter) -{ - int i, j = 1; - - RTW_PRINT_SEL(sel, "======= MAC REG =======\n"); - - for (i = 0x0; i < 0x800; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - -#ifdef CONFIG_RTL8814A - { - for (i = 0x1000; i < 0x1650; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - } -#endif /* CONFIG_RTL8814A */ - -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \ - || defined(CONFIG_RTL8723F) - for (i = 0x1000; i < 0x1800; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif /* CONFIG_RTL8822B or 8821c*/ - -#if defined(CONFIG_RTL8192F) - for (i = 0x1000; i < 0x1100; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - for (i = 0x1300; i < 0x1360; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif - -#if defined(CONFIG_RTL8814B) - for (i = 0x2000; i < 0x2800; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - - for (i = 0x3000; i < 0x3800; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif - -} - -void bb_reg_dump(void *sel, _adapter *adapter) -{ - int i, j = 1; - - RTW_PRINT_SEL(sel, "======= BB REG =======\n"); - for (i = 0x800; i < 0x1000; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \ - || defined(CONFIG_RTL8723F) - for (i = 0x1800; i < 0x2000; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif /* CONFIG_RTL8822B */ - -#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F) - for (i = 0x2c00; i < 0x2c60; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - - for (i = 0x2d00; i < 0x2df0; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - - for (i = 0x4000; i < 0x4060; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - - for (i = 0x4100; i < 0x4200; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - -#endif /* CONFIG_RTL8822C || CONFIG_RTL8814B || CONFIG_8723F */ - -#if defined(CONFIG_RTL8814B) - for (i = 0x5200; i < 0x5400; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif /* CONFIG_RTL8814B */ - -#if defined(CONFIG_RTL8723F) - /* TSSI related */ - for (i = 0x4300; i < 0x43C0; i += 4) { - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } -#endif /* CONFIG_RTL8723F */ -} - -void bb_reg_dump_ex(void *sel, _adapter *adapter) -{ - int i; - - RTW_PRINT_SEL(sel, "======= BB REG =======\n"); - for (i = 0x800; i < 0x1000; i += 4) { - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - _RTW_PRINT_SEL(sel, "\n"); - } - -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) - for (i = 0x1800; i < 0x2000; i += 4) { - RTW_PRINT_SEL(sel, "0x%04x", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); - _RTW_PRINT_SEL(sel, "\n"); - } -#endif /* CONFIG_RTL8822B */ -} - -void rf_reg_dump(void *sel, _adapter *adapter) -{ - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - int i, j = 1, path; - u32 value; - u8 path_nums = hal_spec->rf_reg_path_num; - - RTW_PRINT_SEL(sel, "======= RF REG =======\n"); - - for (path = 0; path < path_nums; path++) { - RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path); - for (i = 0; i < 0x100; i++) { - value = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff); - if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%02x ", i); - _RTW_PRINT_SEL(sel, " 0x%08x ", value); - if ((j++) % 4 == 0) - _RTW_PRINT_SEL(sel, "\n"); - } - } -} void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos) { - struct recv_priv *precvpriv = &(adapter->recvpriv); - if (precvpriv->sink_udpport > 0) { - if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { - precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq; - precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C))); - if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) { - if(precvpriv->pre_rtp_rxseq == 65535 ) { - if( precvpriv->cur_rtp_rxseq != 0) { - RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq); + struct recv_info *precvinfo = &(adapter->recvinfo); + if (precvinfo->sink_udpport > 0) { + if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvinfo->sink_udpport)) { + precvinfo->pre_rtp_rxseq = precvinfo->cur_rtp_rxseq; + precvinfo->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C))); + if (precvinfo->pre_rtp_rxseq + 1 != precvinfo->cur_rtp_rxseq) { + if(precvinfo->pre_rtp_rxseq == 65535 ) { + if( precvinfo->cur_rtp_rxseq != 0) { + RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvinfo->pre_rtp_rxseq, precvinfo->cur_rtp_rxseq); } } else { - RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq); + RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvinfo->pre_rtp_rxseq, precvinfo->cur_rtp_rxseq); } } } @@ -542,17 +316,17 @@ void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj) u8 bw; RTW_PRINT_SEL(sel, "%-6s", "bw"); - if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) + if (rtw_hw_chk_proto_cap(dvobj, PROTO_CAP_11AC)) _RTW_PRINT_SEL(sel, " %-15s", "vht"); _RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck"); for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { - if (!hal_is_bw_support(adapter, bw)) + if (!rtw_hw_is_bw_support(adapter_to_dvobj(adapter), bw)) continue; RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw)); - if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) { + if (rtw_hw_chk_proto_cap(dvobj, PROTO_CAP_11AC)) { _RTW_PRINT_SEL(sel, " %03x %03x %03x %03x" , RATE_BMP_GET_VHT_4SS(rfctl->rate_bmp_vht_by_bw[bw]) , RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw]) @@ -577,32 +351,12 @@ void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj) void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) { -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); int i; _adapter *iface; u8 u_ch, u_bw, u_offset; -#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) - char str_val[64] = {'\0'}; -#endif dump_mi_status(sel, dvobj); -#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN) - RTW_PRINT_SEL(sel, "[AP] LIMITED_AP_NUM:%d\n", CONFIG_LIMITED_AP_NUM); - RTW_PRINT_SEL(sel, "[AP] vap_map:0x%02x\n", dvobj->vap_map); -#endif -#ifdef CONFIG_HW_P0_TSF_SYNC - RTW_PRINT_SEL(sel, "[AP] p0 tsf sync port = %d\n", dvobj->p0_tsf.sync_port); - RTW_PRINT_SEL(sel, "[AP] p0 tsf timer offset = %d\n", dvobj->p0_tsf.offset); -#endif -#ifdef CONFIG_CLIENT_PORT_CFG - RTW_PRINT_SEL(sel, "[CLT] clt_num = %d\n", dvobj->clt_port.num); - RTW_PRINT_SEL(sel, "[CLT] clt_map = 0x%02x\n", dvobj->clt_port.bmp); -#endif -#ifdef CONFIG_FW_MULTI_PORT_SUPPORT - RTW_PRINT_SEL(sel, "[MI] default port id:%d\n\n", dvobj->dft.port_id); -#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */ - RTW_PRINT_SEL(sel, "dev status:%s%s\n\n" , dev_is_surprise_removed(dvobj) ? " SR" : "" , dev_is_drv_stopped(dvobj) ? " DS" : "" @@ -612,11 +366,11 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) #define P2P_INFO_TITLE_FMT " %-3s %-4s" #define P2P_INFO_TITLE_ARG , "lch", "p2ps" #ifdef CONFIG_IOCTL_CFG80211 -#define P2P_INFO_VALUE_FMT " %3u %c%3u" -#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo) +#define P2P_INFO_VALUE_FMT " %3u %c" +#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ' #else -#define P2P_INFO_VALUE_FMT " %3u %4u" -#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo) +#define P2P_INFO_VALUE_FMT " %3u" +#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel #endif #define P2P_INFO_DASH "---------" #else @@ -627,37 +381,17 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) #define P2P_INFO_DASH #endif -#ifdef DBG_TSF_UPDATE -#define TSF_PAUSE_TIME_TITLE_FMT " %-5s" -#define TSF_PAUSE_TIME_TITLE_ARG , "tsfup" -#define TSF_PAUSE_TIME_VALUE_FMT " %5d" -#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0) -#else -#define TSF_PAUSE_TIME_TITLE_FMT "" -#define TSF_PAUSE_TIME_TITLE_ARG -#define TSF_PAUSE_TIME_VALUE_FMT "" -#define TSF_PAUSE_TIME_VALUE_ARG -#endif - -#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) -#define INFO_FMT " %-4s" -#define INFO_ARG , "info" -#define INFO_CNT_FMT " %-20s" -#define INFO_CNT_ARG , str_val -#else #define INFO_FMT "" #define INFO_ARG #define INFO_CNT_FMT "" #define INFO_CNT_ARG -#endif - RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s %-5s" + + RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-17s %-4s %-7s %-5s" P2P_INFO_TITLE_FMT - TSF_PAUSE_TIME_TITLE_FMT " %s"INFO_FMT"\n" - , "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch", "class" + , "id", "ifname", ' ', "netif_up", "macaddr", "port", "ch", "class" P2P_INFO_TITLE_ARG - TSF_PAUSE_TIME_TITLE_ARG , "status"INFO_ARG); RTW_PRINT_SEL(sel, "---------------------------------------------------------------" @@ -667,65 +401,21 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) { - #if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) - _rtw_memset(&str_val, '\0', sizeof(str_val)); - #endif - #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN) - if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { - u8 len; - char *p = str_val; - char tmp_str[10] = {'\0'}; - - len = snprintf(tmp_str, sizeof(tmp_str), "%s", "ap_id:"); - strncpy(p, tmp_str, len); - p += len; - _rtw_memset(&tmp_str, '\0', sizeof(tmp_str)); - #ifdef DBG_HW_PORT - len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->vap_id, iface->hw_port, iface->client_port); - #else - len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->vap_id); - #endif - strncpy(p, tmp_str, len); - } - #endif - #ifdef CONFIG_CLIENT_PORT_CFG - if (MLME_IS_STA(iface)) { - u8 len; - char *p = str_val; - char tmp_str[10] = {'\0'}; - - len = snprintf(tmp_str, sizeof(tmp_str), "%s", "c_pid:"); - strncpy(p, tmp_str, len); - p += len; - _rtw_memset(&tmp_str, '\0', sizeof(tmp_str)); - #ifdef DBG_HW_PORT - len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->client_port, iface->hw_port, iface->client_port); - #else - len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->client_port); - #endif - strncpy(p, tmp_str, len); - } - #endif - - RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u %5u" + RTW_PRINT_SEL(sel, "%2d %-15s %c %3u "MAC_FMT" %4hhu %3u,%u,%u %5u" P2P_INFO_VALUE_FMT - TSF_PAUSE_TIME_VALUE_FMT " "MLME_STATE_FMT" " INFO_CNT_FMT"\n" , i, iface->registered ? ADPT_ARG(iface) : NULL , iface->registered ? 'R' : ' ' - , iface->bup , iface->netif_up - , iface->net_closed , MAC_ARG(adapter_mac_addr(iface)) , rtw_hal_get_port(iface) - , iface->mlmeextpriv.cur_channel - , iface->mlmeextpriv.cur_bwmode - , iface->mlmeextpriv.cur_ch_offset - , rtw_get_op_class_by_chbw(iface->mlmeextpriv.cur_channel - , iface->mlmeextpriv.cur_bwmode - , iface->mlmeextpriv.cur_ch_offset) + , iface->mlmeextpriv.chandef.chan + , iface->mlmeextpriv.chandef.bw + , iface->mlmeextpriv.chandef.offset + , rtw_get_op_class_by_chbw(iface->mlmeextpriv.chandef.chan + , iface->mlmeextpriv.chandef.bw + , iface->mlmeextpriv.chandef.offset) P2P_INFO_VALUE_ARG - TSF_PAUSE_TIME_VALUE_ARG , MLME_STATE_ARG(iface) INFO_CNT_ARG ); @@ -740,14 +430,15 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) RTW_PRINT_SEL(sel, "%55s %3u,%u,%u %5u\n" , "union:" , u_ch, u_bw, u_offset, rtw_get_op_class_by_chbw(u_ch, u_bw, u_offset)); - +#if 0 RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n" , "oper:" - , dvobj->oper_channel - , dvobj->oper_bwmode - , dvobj->oper_ch_offset + , dvobj->chandef.chan + , dvobj->chandef.bw + , dvobj->chandef.offset , rfctl->offch_state ); +#endif #ifdef CONFIG_DFS_MASTER if (rfctl->radar_detect_ch != 0) { @@ -784,10 +475,8 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) _RTW_PRINT_SEL(sel, "\n"); } #endif /* CONFIG_DFS_MASTER */ -#endif /* CONFIG_RTW_DEBUG || CONFIG_PROC_DEBUG */ } -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) #define SEC_CAM_ENT_ID_TITLE_FMT "%-2s" #define SEC_CAM_ENT_ID_TITLE_ARG "id" #define SEC_CAM_ENT_ID_VALUE_FMT "%2u" @@ -825,11 +514,9 @@ void dump_sec_cam_ent_title(void *sel, u8 has_id) } else RTW_PRINT_SEL(sel, SEC_CAM_ENT_TITLE_FMT"\n", SEC_CAM_ENT_TITLE_ARG); } -#endif void dump_sec_cam(void *sel, _adapter *adapter) { -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; struct sec_cam_ent ent; @@ -838,15 +525,13 @@ void dump_sec_cam(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "HW sec cam:\n"); dump_sec_cam_ent_title(sel, 1); for (i = 0; i < cam_ctl->num; i++) { - rtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key); + rtw_hal_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key); dump_sec_cam_ent(sel , &ent, i); } -#endif } void dump_sec_cam_cache(void *sel, _adapter *adapter) { -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; int i; @@ -857,30 +542,7 @@ void dump_sec_cam_cache(void *sel, _adapter *adapter) if (dvobj->cam_cache[i].ctrl != 0) dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i); } -#endif -} - -static u8 fwdl_test_chksum_fail = 0; -static u8 fwdl_test_wintint_rdy_fail = 0; - -bool rtw_fwdl_test_trigger_chksum_fail(void) -{ - if (fwdl_test_chksum_fail) { - RTW_PRINT("fwdl test case: trigger chksum_fail\n"); - fwdl_test_chksum_fail--; - return _TRUE; - } - return _FALSE; -} -bool rtw_fwdl_test_trigger_wintint_rdy_fail(void) -{ - if (fwdl_test_wintint_rdy_fail) { - RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n"); - fwdl_test_wintint_rdy_fail--; - return _TRUE; - } - return _FALSE; } static u8 del_rx_ampdu_test_no_tx_fail = 0; @@ -936,7 +598,6 @@ u16 rtw_ap_linking_test_force_asoc_fail(void) } #endif -#ifdef CONFIG_PROC_DEBUG int proc_get_defs_param(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -988,6 +649,7 @@ ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); char tmp[32]; u32 addr, val, len; @@ -1012,13 +674,13 @@ ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t switch (len) { case 1: - rtw_write8(padapter, addr, (u8)val); + rtw_phl_write8(dvobj->phl, addr, (u8)val); break; case 2: - rtw_write16(padapter, addr, (u16)val); + rtw_phl_write16(dvobj->phl, addr, (u16)val); break; case 4: - rtw_write32(padapter, addr, val); + rtw_phl_write32(dvobj->phl, addr, val); break; default: RTW_INFO("error write length=%d", len); @@ -1026,7 +688,6 @@ ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t } } - return count; } @@ -1038,6 +699,7 @@ int proc_get_read_reg(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); if (proc_get_read_addr == 0xeeeeeeee) { RTW_PRINT_SEL(m, "address not initialized\n"); @@ -1046,13 +708,16 @@ int proc_get_read_reg(struct seq_file *m, void *v) switch (proc_get_read_len) { case 1: - RTW_PRINT_SEL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr)); + RTW_PRINT_SEL(m, "reg_read8(0x%x)=0x%x\n", proc_get_read_addr, + rtw_phl_read8(dvobj->phl, proc_get_read_addr)); break; case 2: - RTW_PRINT_SEL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr)); + RTW_PRINT_SEL(m, "reg_read16(0x%x)=0x%x\n", proc_get_read_addr, + rtw_phl_read16(dvobj->phl, proc_get_read_addr)); break; case 4: - RTW_PRINT_SEL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr)); + RTW_PRINT_SEL(m, "reg_read32(0x%x)=0x%x\n", proc_get_read_addr, + rtw_phl_read32(dvobj->phl, proc_get_read_addr)); break; default: RTW_PRINT_SEL(m, "error read length=%d\n", proc_get_read_len); @@ -1095,9 +760,95 @@ ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t c } +ssize_t proc_set_mac_dbg_status_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + char tmp[32] = {0}; + u32 val[2] = {0}; + u32 en; + u8 en_u8; + + if (count < 1) { + RTW_INFO("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x", &en); + + if (num != 1) { + RTW_INFO("invalid mac_dbg_status_dump parameter!\n"); + return count; + } + en_u8 = (u8)en; + rtw_phl_mac_dbg_status_dump(dvobj->phl, val, &en_u8); + if (en & BIT0) + RTW_INFO_DUMP("ss_dbgpkg: ", (const u8 *)val, 8); + } + return count; + +} + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST +int proc_get_ignore_go_and_low_rssi_in_scan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + RTW_PRINT_SEL(m, "ignore_go_in_scan=%d, ignore_low_rssi_in_scan=%d\n", + pregpriv->ignore_go_in_scan, pregpriv->ignore_low_rssi_in_scan); + return 0; +} + +ssize_t proc_set_ignore_go_and_low_rssi_in_scan(struct file *file, + const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + char tmp[32] = {0}; + int enable = 0; + int num = 0, low_rssi=0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d %d", &enable, &low_rssi); + RTW_INFO("num=%d enable=%d low_rssi=%d\n", num, enable, low_rssi); + + if (num != 2) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + + pregpriv->ignore_go_in_scan = enable; + pregpriv->ignore_low_rssi_in_scan = low_rssi; + } + return count; +} +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + +#ifdef CONFIG_PROC_DEBUG + int proc_get_rx_stat(struct seq_file *m, void *v) { - _irqL irqL; _list *plist, *phead; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1108,7 +859,7 @@ int proc_get_rx_stat(struct seq_file *m, void *v) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(pstapriv->sta_hash[i]); plist = get_next(phead); @@ -1119,10 +870,10 @@ int proc_get_rx_stat(struct seq_file *m, void *v) if (pstats == NULL) continue; - if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { - RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { + RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts); pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta); RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt); @@ -1139,13 +890,12 @@ int proc_get_rx_stat(struct seq_file *m, void *v) } } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); return 0; } int proc_get_tx_stat(struct seq_file *m, void *v) { - _irqL irqL; _list *plist, *phead; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1160,28 +910,23 @@ int proc_get_tx_stat(struct seq_file *m, void *v) u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; struct submit_ctx gotc2h; - if (!adapter->hal_func.reqtxrpt) { - RTW_PRINT_SEL(m, "Not support.\n"); - return 0; - } - - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(pstapriv->sta_hash[i]); plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { - _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN); - mac_id[macid_rec_idx] = psta->cmn.mac_id; + if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { + _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->phl_sta->mac_addr, ETH_ALEN); + mac_id[macid_rec_idx] = psta->phl_sta->macid; macid_rec_idx++; } } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < macid_rec_idx; i++) { _rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN); pstapriv_primary->c2h_adapter_id = adapter->iface_id; @@ -1192,7 +937,7 @@ int proc_get_tx_stat(struct seq_file *m, void *v) psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]); if(psta) { pstats = &psta->sta_stats; -#if (!defined(ROKU_PRIVATE) && !defined(CONFIG_RTW_MULTI_AP)) +#ifndef ROKU_PRIVATE RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); @@ -1241,8 +986,21 @@ int proc_get_sec_info(struct seq_file *m, void *v) sec->ndisauthtype, sec->ndisencryptstatus); RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted); + RTW_PRINT_SEL(m, "wpa_psk="); + if(sec->wpa_psk & BIT(0)) + RTW_PRINT_SEL(m, "WPA "); + if(sec->wpa_psk & BIT(1)) + RTW_PRINT_SEL(m, "WPA2 "); + RTW_PRINT_SEL(m, "\n"); + RTW_PRINT_SEL(m, "wpa2_group_cipher=%d\n", sec->wpa2_group_cipher); + RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=%d\n", sec->wpa2_pairwise_cipher); + RTW_PRINT_SEL(m, "wpa_group_cipher=%d\n", sec->wpa_group_cipher); + RTW_PRINT_SEL(m, "wpa_pairwise_cipher=%d\n", sec->wpa_pairwise_cipher); + RTW_PRINT_SEL(m, "80211W_enable=%d\n", sec->mfp_opt); + RTW_PRINT_SEL(m, "akm_suite_bitmap=0x%x\n", sec->akmp); #ifdef DBG_SW_SEC_CNT + RTW_PRINT_SEL(m, "==sw counters(bc, mc, uc)==\n"); RTW_PRINT_SEL(m, "wep_sw_enc_cnt=%llu, %llu, %llu\n" , sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc); RTW_PRINT_SEL(m, "wep_sw_dec_cnt=%llu, %llu, %llu\n" @@ -1402,736 +1160,858 @@ ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, siz } #endif /* CONFIG_LAYER2_ROAMING */ -#ifdef CONFIG_WAR_OFFLOAD -int proc_get_war_offload_enable(struct seq_file *m, void *v) + +int proc_get_qos_option(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - if (_TRUE == pwrpriv->wowlan_war_offload_mode) { - RTW_PRINT_SEL(m, "\n[ Offload Feature Enabled ]\n"); + RTW_PRINT_SEL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option); - if (WAR_ARP_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n ARP Reponse offload enabled\n"); - } -#ifdef CONFIG_OFFLOAD_MDNS_V4 - if (WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n MDNS v4 Reponse offload enabled\n"); - } - if (WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n MDNS v4 Wakeup offload enabled\n"); - } -#endif /* CONFIG_OFFLOAD_MDNS_v4 */ -#ifdef CONFIG_OFFLOAD_MDNS_V6 - if (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n MDNS v6 Reponse offload enabled\n"); - } - if (WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n MDNS v6 Wakeup offload enabled\n"); - } -#endif /* CONFIG_OFFLOAD_MDNS_V6 */ + return 0; +} - if (WAR_ARP_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) { - RTW_PRINT_SEL(m, "\n ARP Request wakeup enabled\n"); - } +int proc_get_ht_option(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - } else { - RTW_PRINT_SEL(m, "\n[ Offload Feature Disabled ]\n"); - } +#ifdef CONFIG_80211N_HT + RTW_PRINT_SEL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option); +#endif /* CONFIG_80211N_HT */ return 0; } -ssize_t proc_set_war_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_rf_info(struct seq_file *m, void *v) { - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - char tmp[32]; - u32 offload_cfg = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + RTW_PRINT_SEL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n", + pmlmeext->chandef.chan, pmlmeext->chandef.bw, pmlmeext->chandef.offset); - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n", + rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter)); - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } + return 0; +} - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%x", &offload_cfg); +int proc_get_scan_param(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; - if (num == 1) { - RTW_INFO(FUNC_ADPT_FMT ": Set war offload cfg = %x\n", FUNC_ADPT_ARG(padapter), offload_cfg); - pwrpriv->wowlan_war_offload_ctrl = offload_cfg; - pwrpriv->wowlan_war_offload_mode = offload_cfg?_TRUE:_FALSE; +#define SCAN_PARAM_TITLE_FMT "%10s" +#define SCAN_PARAM_VALUE_FMT "%-10u" +#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms" +#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms +#ifdef CONFIG_80211N_HT +#define SCAN_PARAM_TITLE_FMT_HT " %15s %13s" +#define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u" +#define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size" +#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size +#else +#define SCAN_PARAM_TITLE_FMT_HT "" +#define SCAN_PARAM_VALUE_FMT_HT "" +#define SCAN_PARAM_TITLE_ARG_HT +#define SCAN_PARAM_VALUE_ARG_HT +#endif +#ifdef CONFIG_SCAN_BACKOP +#define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s" +#define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u" +#define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max" +#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max +#else +#define SCAN_PARAM_TITLE_FMT_BACKOP "" +#define SCAN_PARAM_VALUE_FMT_BACKOP "" +#define SCAN_PARAM_TITLE_ARG_BACKOP +#define SCAN_PARAM_VALUE_ARG_BACKOP +#endif - } - } + RTW_PRINT_SEL(m, + SCAN_PARAM_TITLE_FMT + SCAN_PARAM_TITLE_FMT_HT + SCAN_PARAM_TITLE_FMT_BACKOP + "\n" + SCAN_PARAM_TITLE_ARG + SCAN_PARAM_TITLE_ARG_HT + SCAN_PARAM_TITLE_ARG_BACKOP + ); - return count; + RTW_PRINT_SEL(m, + SCAN_PARAM_VALUE_FMT + SCAN_PARAM_VALUE_FMT_HT + SCAN_PARAM_VALUE_FMT_BACKOP + "\n" + SCAN_PARAM_VALUE_ARG + SCAN_PARAM_VALUE_ARG_HT + SCAN_PARAM_VALUE_ARG_BACKOP + ); + + return 0; } -ssize_t proc_set_war_offload_ipv4_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - char tmp[128]; - u32 ip_addr = 0, ip_subnet = 0, ip_gateway = 0, index = 0; - struct war_ipv4_fmt* pip_info = &pwrpriv->wowlan_war_offload_ipv4; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + char tmp[32] = {0}; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + u16 scan_ch_ms; +#define SCAN_PARAM_INPUT_FMT "%hu" +#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms +#ifdef CONFIG_80211N_HT + u8 rx_ampdu_accept; + u8 rx_ampdu_size; +#define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu" +#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size +#else +#define SCAN_PARAM_INPUT_FMT_HT "" +#define SCAN_PARAM_INPUT_ARG_HT +#endif +#ifdef CONFIG_SCAN_BACKOP + u16 backop_ms; + u8 scan_cnt_max; +#define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu" +#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max +#else +#define SCAN_PARAM_INPUT_FMT_BACKOP "" +#define SCAN_PARAM_INPUT_ARG_BACKOP +#endif + + if (count < 1) return -EFAULT; - } if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d %x %x %x", &index, &ip_addr, &ip_subnet, &ip_gateway); - - if (num == 4) { - pip_info->ip_addr[index-1] = ip_addr; - pip_info->ip_subnet[index-1] = ip_subnet; - pip_info->ip_gateway[index-1] = ip_gateway; - RTW_INFO(FUNC_ADPT_FMT "Setup IPv4 address:\n", FUNC_ADPT_ARG(padapter)); - RTW_INFO("Index(%d) IP=%d.%d.%d.%d\n", index, (ip_addr & 0xff), ((ip_addr & 0xff00)>>8), ((ip_addr & 0xff0000)>>16), ((ip_addr & 0xff000000)>>24)); - } else { - RTW_INFO("Wrong input buffer count (%d)\n", num); - return -EFAULT; - } + + int num = sscanf(tmp, + SCAN_PARAM_INPUT_FMT + SCAN_PARAM_INPUT_FMT_HT + SCAN_PARAM_INPUT_FMT_BACKOP + SCAN_PARAM_INPUT_ARG + SCAN_PARAM_INPUT_ARG_HT + SCAN_PARAM_INPUT_ARG_BACKOP + ); + + if (num-- > 0) + ss->scan_ch_ms = scan_ch_ms; +#ifdef CONFIG_80211N_HT + if (num-- > 0) + ss->rx_ampdu_accept = rx_ampdu_accept; + if (num-- > 0) + ss->rx_ampdu_size = rx_ampdu_size; +#endif +#ifdef CONFIG_SCAN_BACKOP + if (num-- > 0) + ss->backop_ms = backop_ms; + if (num-- > 0) + ss->scan_cnt_max = scan_cnt_max; +#endif } return count; } - -ssize_t proc_set_war_offload_ipv6_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_scan_abort(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { + char tmp[32]; struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - char tmp[255]; - u32 ip_addr = 0, ip_subnet = 0, ip_gateway = 0; - struct war_ipv6_fmt* pip_info = &pwrpriv->wowlan_war_offload_ipv6; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + u32 timeout = 0; if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO("argument size is less than 1\n"); return -EFAULT; } if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num; - int i; - u32 index; - u16 val[64]; - u16 big_endian_val[64]; + int num = 0; - num = sscanf(tmp, "%d %hx:%hx:%hx:%hx:%hx:%hx:%hx:%hx", &index, &val[0], &val[1], &val[2], &val[3], &val[4], &val[5], &val[6], &val[7]); - for (i=0;i<8;i++) { - big_endian_val[i] = htons(val[i]); + num = sscanf(tmp, "%d", &timeout); + if (num != 1) { + RTW_INFO("invalid parameter!\n"); + return count; } - _rtw_memcpy(pip_info->ipv6_addr[index-1], big_endian_val, RTW_IPv6_ADDR_LEN); - if (num == 9) { - RTW_INFO(FUNC_ADPT_FMT "Setup IPv6 address\n", FUNC_ADPT_ARG(padapter)); - } else { - RTW_INFO("Wrong input count (%d)\n", num); - return -EFAULT; - } + rtw_scan_abort(padapter, timeout); } return count; } -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) - -int proc_get_war_offload_mdns_domain_name(struct seq_file *m, void *v) +int proc_get_scan_abort(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - - if (_TRUE == pwrpriv->wowlan_war_offload_mode) { - if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) { - RTW_PRINT_SEL(m, "\nDomain Name:[%s](%d)\n\n", - pwrpriv->wowlan_war_offload_mdns_domain_name, pwrpriv->wowlan_war_offload_mdns_domain_name_len); - } else { - RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n"); - } - } else { - RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n"); - } + return 0; } - -ssize_t proc_set_war_offload_mdns_domain_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) + +int proc_get_survey_info(struct seq_file *m, void *v) { - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - char tmp[MAX_MDNS_DOMAIN_NAME_LEN+1]; - char domain_name[MAX_MDNS_DOMAIN_NAME_LEN+1]; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + _list *plist, *phead; + s32 notify_signal; + s16 notify_noise = 0; + u16 index = 0, ie_cap = 0; + unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL; + unsigned char *ie_p2p = NULL, *ssid = NULL; + char flag_str[64]; + int ielen = 0; + u32 wpsielen = 0; +#ifdef CONFIG_RTW_MESH + const char *ssid_title_str = "ssid/mesh_id"; +#else + const char *ssid_title_str = "ssid"; +#endif - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); + phead = get_list_head(queue); + if (!phead) + goto _exit; + plist = get_next(phead); + if (!plist) + goto _exit; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str); + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is large than MAX_MDNS_DOMAIN_NAME_LEN(%d)\n", FUNC_ADPT_ARG(padapter), MAX_MDNS_DOMAIN_NAME_LEN); - rtw_warn_on(1); - return -EFAULT; - } + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%s", domain_name); - if(1 == num) { - pwrpriv->wowlan_war_offload_mdns_domain_name_len = strlen(domain_name); - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_domain_name, 0x00, MAX_MDNS_DOMAIN_NAME_LEN); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_domain_name, domain_name, strlen(domain_name)); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) { + notify_signal = rtw_phl_rssi_to_dbm(padapter->recvinfo.signal_strength);/* dbm */ + } else { + notify_signal = rtw_phl_rssi_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */ } - } - - return count; -} +#if 0 /*def CONFIG_BACKGROUND_NOISE_MONITOR*/ + if (IS_NM_ENABLE(padapter)) + notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); +#endif -int proc_get_war_offload_mdns_machine_name(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - int i=0; - - if (_TRUE == pwrpriv->wowlan_war_offload_mode) { - if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) { - for(i=0; iwowlan_war_offload_mdns_mnane_num; i++) - { - RTW_PRINT_SEL(m, "[%d]", i); - rtw_wow_war_mdns_dump_buf(m, "Machine Name", - pwrpriv->wowlan_war_offload_mdns_mnane[i].name, pwrpriv->wowlan_war_offload_mdns_mnane[i].name_len); - } - RTW_PRINT_SEL(m, "\n"); - } else { - RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n"); - } - } else { - RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n"); + ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); + ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); + ie_cap = rtw_get_capability(&pnetwork->network); + ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen); + ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen); + ssid = pnetwork->network.Ssid.Ssid; + sprintf(flag_str, "%s%s%s%s%s%s%s%s", + (ie_wpa) ? "[WPA]" : "", + (ie_wpa2) ? "[WPA2]" : "", + (!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "", + (ie_wps) ? "[WPS]" : "", + (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : + (pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "", + (ie_cap & BIT(0)) ? "[ESS]" : "", + (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) ? "[B]" : \ + (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_RSP) ? "[P]" : "[U]", + (ie_p2p) ? "[P2P]" : ""); + RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d %3d %4d %4d %5d %32s %32s\n", + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + pnetwork->network.PhyInfo.rssi, + notify_signal, + notify_noise, + rtw_get_passing_time_ms(pnetwork->last_scanned), + flag_str, + pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid + ); + plist = get_next(plist); } +_exit: + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); return 0; } - -ssize_t proc_set_war_offload_mdns_machine_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - char tmp[MAX_MDNS_MACHINE_NAME_LEN*3-1+1]; + u8 _status = _FALSE; + u8 ssc_chk; + char tmp[32] = {0}; + char cmd[8] = {0}; + bool acs = 0; - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); + if (count < 1) return -EFAULT; - } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length, %lu, is large than MAX_MDNS_MACHINE_NAME_LEN(%d)\n", FUNC_ADPT_ARG(padapter), (count+1)/3, MAX_MDNS_MACHINE_NAME_LEN); - rtw_warn_on(1); + if (count > sizeof(tmp)) { + rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%s", cmd); - if( strncmp(tmp, "clean", 5) == 0 ) - { - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_mnane, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_mnane)); - pwrpriv->wowlan_war_offload_mdns_mnane_num = 0; - }else{ - int idx = pwrpriv->wowlan_war_offload_mdns_mnane_num; - if(idx == MAX_MDNS_MACHINE_NAME_NUM){ - RTW_INFO(FUNC_ADPT_FMT ": the num of machine name is already %d(MAX_MDNS_MACHINE_NAME_NUM)!\n", FUNC_ADPT_ARG(padapter), MAX_MDNS_MACHINE_NAME_NUM); - return -EFAULT; - } - if(rtw_wow_war_mdns_parser_pattern(tmp, pwrpriv->wowlan_war_offload_mdns_mnane[idx].name, - (u32 *) &pwrpriv->wowlan_war_offload_mdns_mnane[idx].name_len, MAX_MDNS_MACHINE_NAME_LEN)) - pwrpriv->wowlan_war_offload_mdns_mnane_num++; - } - } + if (num < 1) + return count; - return count; -} + if (strcmp("acs", cmd) == 0) + acs = 1; + } +#if 1 + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + if (ssc_chk != SS_ALLOW) + goto exit; -int proc_get_war_offload_mdns_service_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - struct war_mdns_service_info *psinfo = pwrpriv->wowlan_war_offload_mdns_service; - int i=0, j=0; - - if (_TRUE == pwrpriv->wowlan_war_offload_mode) { - if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) { - for(i=0; iwowlan_war_offload_mdns_service_info_num; i++) - { - RTW_PRINT_SEL(m, "[%d] service info ===> \n", i+1); - RTW_PRINT_SEL(m, "\tservice-transport-domain : %s(%d)- %s(%d)- %s(%d)\n", - psinfo[i].service, psinfo[i].service_len, - psinfo[i].transport, psinfo[i].transport_len, - psinfo[i].domain, psinfo[i].domain_len); - RTW_PRINT_SEL(m, "\ttarget for srv rsp : %s(%d)\n", psinfo[i].target, psinfo[i].target_len); - RTW_PRINT_SEL(m, "\tport : %x-%x, ttl : %d \n", psinfo[i].port[0], psinfo[i].port[1], psinfo[i].ttl); - j = psinfo[i].txt_rsp_idx; - RTW_PRINT_SEL(m, "\ttype txt rsp. [%d] \n", j); - rtw_wow_war_mdns_dump_txt(m, "type txt rsp. (Str)", - pwrpriv->wowlan_war_offload_mdns_txt_rsp[j].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[j].txt_len); - - } - RTW_PRINT_SEL(m, "\n"); - } else { - RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n"); - } - } else { - RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n"); + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) + goto cancel_ps_deny; + if (!rtw_is_adapter_up(padapter)) { + RTW_INFO("scan abort!! adapter cannot use\n"); + goto cancel_ps_deny; + } +#else +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(padapter)) { + RTW_INFO("MP mode block Scan request\n"); + goto exit; + } +#endif + if (rtw_is_scan_deny(padapter)) { + RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); + goto exit; } - return 0; -} - -ssize_t proc_set_war_offload_mdns_service_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - struct war_mdns_service_info *psinfo = pwrpriv->wowlan_war_offload_mdns_service; - u8 idx = 0, port[2], i=0; - char *tmp=NULL; - char srv[MAX_MDNS_SERVICE_NAME_LEN+1], trans[MAX_MDNS_TRANS_LEN+1], domain[MAX_MDNS_DOMAIN_LEN+1]; - char target[MAX_MDNS_TARGET_LEN+1]; - u32 ttl, tmp_txt_len=0, port0 =0, port1 =0; - u16 max_input_size = (MAX_MDNS_SERVICE_NAME_LEN+MAX_MDNS_TRANS_LEN+MAX_MDNS_DOMAIN_LEN+MAX_MDNS_TARGET_LEN+2); - int txt_idx; + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) + goto cancel_ps_deny; - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; + if (!rtw_is_adapter_up(padapter)) { + RTW_INFO("scan abort!! adapter cannot use\n"); + goto cancel_ps_deny; } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; + if (rtw_mi_busy_traffic_check(padapter)) { + RTW_INFO("scan abort!! BusyTraffic == _TRUE\n"); + goto cancel_ps_deny; } - if (count > (sizeof(char)*(max_input_size)) ) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO("scan abort!! AP mode process WPS\n"); + goto cancel_ps_deny; + } + if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) { + RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state); + goto cancel_ps_deny; } - tmp = rtw_zvmalloc(sizeof(char)*(max_input_size)); - if (NULL == tmp) { - RTW_INFO(FUNC_ADPT_FMT ": tmp buffer allocate fail!!\n", FUNC_ADPT_ARG(padapter)); - count = -EFAULT; - goto exit; +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(padapter, + WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) { + RTW_INFO("scan abort!! buddy_fwstate check failed\n"); + goto cancel_ps_deny; } +#endif +#endif - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%15s %4s %5s %63s %x %x %u %d", srv, trans, domain, target, &port0, &port1, &ttl, &txt_idx); - /* MAX_MDNS_SERVICE_NAME_LEN(15), MAX_MDNS_TRANS_LEN(4), MAX_MDNS_DOMAIN_LEN(5), MAX_MDNS_TARGET_LEN(63) */ - int idx = pwrpriv->wowlan_war_offload_mdns_service_info_num; - u16 curent_txt_total_size = 0; - //u16 sscanf_parameter_length = strlen(srv)+strlen(trans)+strlen(domain)+strlen(target)+2+2+4+1+num; - - if( strncmp(srv, "clean", 5) == 0 ) { - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_service, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_service)); - pwrpriv->wowlan_war_offload_mdns_service_info_num = 0; - } - /*else if(count != sscanf_parameter_length) - { - RTW_INFO(FUNC_ADPT_FMT ": Length of total parameters does not match the input buffer. (%d != %lu)\n", - FUNC_ADPT_ARG(padapter), sscanf_parameter_length, count); - RTW_INFO(FUNC_ADPT_FMT ": Please check the content and length of each parameter.\n", FUNC_ADPT_ARG(padapter)); - RTW_INFO(FUNC_ADPT_FMT ": input buffer = (%s)(%lu)!\n\n", FUNC_ADPT_ARG(padapter), tmp, count); - RTW_INFO(FUNC_ADPT_FMT ": srv = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), srv, strlen(srv)); - RTW_INFO(FUNC_ADPT_FMT ": trans = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), trans, strlen(trans)); - RTW_INFO(FUNC_ADPT_FMT ": domain = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), domain, strlen(domain)); - RTW_INFO(FUNC_ADPT_FMT ": target = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), target, strlen(target)); - RTW_INFO(FUNC_ADPT_FMT ": port = %x-%x, ttl = %d!\n", FUNC_ADPT_ARG(padapter), port0, port1, ttl); - RTW_INFO(FUNC_ADPT_FMT ": txt idx = %d!\n", FUNC_ADPT_ARG(padapter), txt_idx); - count = -EFAULT; - goto exit; - }*/else - { - port[0] = (u8)port0; - port[1] = (u8)port1; + if (acs) { + #ifdef CONFIG_RTW_ACS + _status = rtw_set_acs_sitesurvey(padapter); + #endif + } else + _status = rtw_sitesurvey_cmd(padapter, NULL); + +cancel_ps_deny: + rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); +exit: + return count; +} +#ifdef ROKU_PRIVATE +int proc_get_infra_ap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; +#ifdef CONFIG_80211AC_VHT + struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap; +#endif + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + + if (MLME_IS_STA(padapter)) { + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + unsigned int i, j; + unsigned int Rx_ss = 0, Tx_ss = 0; - if(txt_idx >= MAX_MDNS_TXT_NUM) { - RTW_INFO(FUNC_ADPT_FMT ": input txt idx, %d, is out of range (0~%d)!\n", FUNC_ADPT_ARG(padapter), txt_idx, MAX_MDNS_TXT_NUM-1); - count = -EFAULT; - goto exit; + RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_PRINT_SEL(m, "Supported rate="); + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) + break; + RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]); + } + RTW_PRINT_SEL(m, "\n"); +#ifdef CONFIG_80211N_HT + if (pmlmeinfo->ht_vht_received & BIT(0)) { + RTW_PRINT_SEL(m, "Supported MCS set="); + for (i = 0; i < 16 ; i++) + RTW_PRINT_SEL(m, " 0x%02x", phtpriv->MCS_set_infra_ap[i]); + RTW_PRINT_SEL(m, "\n"); + RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap); + RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap); + RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap); + RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap); + RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap); } +#endif - if(pwrpriv->wowlan_war_offload_mdns_txt_rsp[txt_idx].txt_len == 0) { - RTW_INFO(FUNC_ADPT_FMT ": wowlan_war_offload_mdns_txt_rsp[%d] is null! Please initiate it first.\n", FUNC_ADPT_ARG(padapter), txt_idx); - count = -EFAULT; - goto exit; +#ifdef CONFIG_80211AC_VHT + if (pmlmeinfo->ht_vht_received & BIT(1)) { + RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap); + RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap); + RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap); } - - // 1. set the value of members for this new service - psinfo[idx].service_len = strlen(srv); - _rtw_memcpy(psinfo[idx].service, srv, psinfo[idx].service_len ); - psinfo[idx].transport_len = strlen(trans); - _rtw_memcpy(psinfo[idx].transport, trans, psinfo[idx].transport_len ); - psinfo[idx].domain_len = strlen(domain); - _rtw_memcpy(psinfo[idx].domain, domain, psinfo[idx].domain_len ); - psinfo[idx].target_len = strlen(target); - _rtw_memcpy(psinfo[idx].target, target, psinfo[idx].target_len ); - _rtw_memcpy(psinfo[idx].port, port, 2 ); - psinfo[idx].ttl = ttl; - psinfo[idx].txt_rsp_idx = txt_idx; - pwrpriv->wowlan_war_offload_mdns_service_info_num++; - } - } +#endif + } else + RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + } else + RTW_PRINT_SEL(m, "this only applies to STA mode\n"); + return 0; +} -exit: - if(tmp) - rtw_vmfree(tmp, sizeof(char)*(max_input_size)); - return count; +#endif /* ROKU_PRIVATE */ + +static int wireless_mode_to_str(u32 mode, char *str) +{ + str[0]='\0'; + if (mode & WLAN_MD_11A) + sprintf(str+strlen(str),"%s","A/"); + if (mode & WLAN_MD_11B) + sprintf(str+strlen(str),"%s","B/"); + if (mode & WLAN_MD_11G) + sprintf(str+strlen(str),"%s","G/"); + #ifdef CONFIG_80211N_HT + if (mode & WLAN_MD_11N) + sprintf(str+strlen(str),"%s","N/"); + #endif + #ifdef CONFIG_80211AC_VHT + if (mode & WLAN_MD_11AC) + sprintf(str+strlen(str),"%s","AC/"); + #endif + #ifdef CONFIG_80211AX_HE + if (mode & WLAN_MD_11AX) + sprintf(str+strlen(str),"%s","AX/"); + #endif + if (strlen(str)>1) + str[strlen(str)-1]='\0'; + return strlen(str); } -int proc_get_war_offload_mdns_txt_rsp(struct seq_file *m, void *v) +int proc_get_ap_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - int i=0; - - if (_TRUE == pwrpriv->wowlan_war_offload_mode) { - if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) || - (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ) { - for(i=0; iwowlan_war_offload_mdns_txt_rsp_num; i++) { - RTW_PRINT_SEL(m, "[%d]", i); - if(pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len==0){ - RTW_PRINT_SEL(m, " (null)\n"); - continue; - } - rtw_wow_war_mdns_dump_txt(m, "type txt rsp. (Str)", - pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len); - rtw_wow_war_mdns_dump_buf(m, "type txt rsp. (Hex)", - pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len); - } - RTW_PRINT_SEL(m, "\n"); + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + char wl_mode[16]; + + /* ap vendor */ + char vendor[VENDOR_NAME_LEN] = {0}; + get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor); + RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor); + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + wireless_mode_to_str(psta->phl_sta->wmode, wl_mode); + RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d(%s), cur_ch_offset=%d\n", pmlmeext->chandef.chan, pmlmeext->chandef.bw, ch_width_str(pmlmeext->chandef.bw), pmlmeext->chandef.offset); + RTW_PRINT_SEL(m, "wireless_mode=0x%x(%s), rtsen=%d, cts2slef=%d hw_rts_en=%d\n", + psta->phl_sta->wmode, wl_mode, psta->rtsen, psta->cts2self, psta->hw_rts_en); + /* ToDo: need API to query hal_sta->ra_info.rate_id */ + /* RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid, psta->phl_sta->ra_info.rate_id); */ + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid); +#ifdef CONFIG_80211N_HT + RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->phl_sta->chandef.bw, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); + RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap); +#endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(m, "vht_en=%u, upper_layer_setting=%u, vht_sgi_80m=%u\n", psta->vhtpriv.vht_option, psta->vhtpriv.upper_layer_setting, psta->vhtpriv.sgi_80m); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); + RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); + if (psta->vhtpriv.vht_option) { + RTW_MAP_DUMP_SEL_ALWAYS(m, "vht_cap=", psta->vhtpriv.vht_cap, 32); } else { - RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n"); + RTW_PRINT_SEL(m, "vht_cap=N/A\n"); } - } else { - RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n"); - } +#endif +#ifdef CONFIG_80211AX_HE + RTW_PRINT_SEL(m, "he_en=%d\n", psta->hepriv.he_option); + if (psta->hepriv.he_option) { + RTW_MAP_DUMP_SEL_ALWAYS(m, "he_cap=", psta->hepriv.he_cap, HE_CAP_ELE_MAX_LEN); + } else { + RTW_PRINT_SEL(m, "he_cap=N/A\n"); + } +#endif +#ifdef CONFIG_RECV_REORDERING_CTRL + sta_rx_reorder_ctl_dump(m, psta); +#endif + } else + RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); return 0; } -ssize_t proc_set_war_offload_mdns_txt_rsp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - u16 max_input_size = (1+6+MAX_MDNS_TXT_SINGLE_LEN+2); - char* tmp=NULL; - char op[7]={0}, txt_str[MAX_MDNS_TXT_SINGLE_LEN+1]={0}; - int idx; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + struct recv_info *precvinfo = &padapter->recvinfo; + char cmd[32] = {0}; + u8 cnt = 0; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count > sizeof(cmd)) { + rtw_warn_on(1); return -EFAULT; } - tmp = rtw_zvmalloc(sizeof(char)*(max_input_size)); - if (NULL == tmp) { - RTW_INFO(FUNC_ADPT_FMT ": tmp buffer allocate fail!!\n", FUNC_ADPT_ARG(padapter)); - count = -EFAULT; - goto exit; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - if( strncmp(tmp, "clean", 5) == 0 ) - { - /* clean ==> */ - if(pwrpriv->wowlan_war_offload_mdns_service_info_num==0){ - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_txt_rsp)); - }else{ - RTW_INFO(FUNC_ADPT_FMT ": Txt rsp are refered! (Current service_info_num = %d)\n", FUNC_ADPT_ARG(padapter), pwrpriv->wowlan_war_offload_mdns_service_info_num); - count = -EFAULT; - goto exit; - } - - }else{ - /* set ==> */ - int num = sscanf(tmp, "%d %6s %256c", &idx, op, txt_str); - u16 sscanf_parameter_length = 0, txt_len = 0; - - txt_len = (strlen(txt_str)>MAX_MDNS_TXT_SINGLE_LEN)?MAX_MDNS_TXT_SINGLE_LEN:(strlen(txt_str)-1); - txt_str[txt_len]='\0'; - sscanf_parameter_length = 1 + strlen(op) + txt_len + num; - - if(count != sscanf_parameter_length) { - RTW_INFO(FUNC_ADPT_FMT ": Length of total parameters does not match the input buffer. (%d != %lu)(num=%d)\n", - FUNC_ADPT_ARG(padapter), sscanf_parameter_length, count, num); - RTW_INFO(FUNC_ADPT_FMT ": Please check the content and length of each parameter.\n", FUNC_ADPT_ARG(padapter)); - RTW_INFO(FUNC_ADPT_FMT ": input buffer = (%s)(%lu)!\n\n", FUNC_ADPT_ARG(padapter), tmp, count); - RTW_INFO(FUNC_ADPT_FMT ": op. = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), op, strlen(op)); - RTW_INFO(FUNC_ADPT_FMT ": txt = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), txt_str, strlen(txt_str)); - count = -EFAULT; - goto exit; - } else { - - u16 offset; - - if(idx >= MAX_MDNS_TXT_NUM) { - RTW_INFO(FUNC_ADPT_FMT ": the index, %d, is over the range of txt rsp(0~%d)!\n", FUNC_ADPT_ARG(padapter), idx, MAX_MDNS_TXT_NUM-1); - count = -EFAULT; - goto exit; - } - - if( strncmp(op, "new", 3) == 0 ) { - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt, 0, pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len); - pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len = 0; - }else if(strncmp(op, "append", 6) == 0 ){ - if((pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len+strlen(txt_str)+1) > MAX_MDNS_TXT_LEN) { - RTW_INFO(FUNC_ADPT_FMT ": the txt rsp(%d) will be over the limitation(%d) if append input string(%lu)!\n", FUNC_ADPT_ARG(padapter), - pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len, - MAX_MDNS_TXT_LEN, strlen(txt_str)+1); - count = -EFAULT; - goto exit; - } - }else{ - RTW_INFO(FUNC_ADPT_FMT ": Invaild op str %s (new/append only)!\n", FUNC_ADPT_ARG(padapter), op); - count = -EFAULT; - goto exit; - } - - offset = pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len; - pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt[offset++] = strlen(txt_str); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt + offset, txt_str, strlen(txt_str)); - pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len += (strlen(txt_str) + 1); /* actul len with length field */ + if (buffer && !copy_from_user(cmd, buffer, count)) { + int num = sscanf(cmd, "%hhx", &cnt); - /* Dump ==> */ - //RTW_PRINT_SEL(RTW_DBGDUMP, "[%d]", idx); - //rtw_wow_war_mdns_dump_txt(RTW_DBGDUMP, "type txt rsp. (Str)", - // pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len); - } + if (num == 1 && cnt == 0) { + precvinfo->dbg_rx_ampdu_drop_count = 0; + precvinfo->dbg_rx_ampdu_forced_indicate_count = 0; + precvinfo->dbg_rx_ampdu_loss_count = 0; + precvinfo->dbg_rx_dup_mgt_frame_drop_count = 0; + precvinfo->dbg_rx_ampdu_window_shift_cnt = 0; + precvinfo->dbg_rx_conflic_mac_addr_cnt = 0; + precvinfo->dbg_rx_drop_count = 0; } } -exit: - if(tmp) - rtw_vmfree(tmp, sizeof(char)*(max_input_size)); return count; - } -#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */ -#endif /* CONFIG_WAR_OFFLOAD */ - - - -int proc_get_qos_option(struct seq_file *m, void *v) +int proc_get_trx_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; + int i; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - RTW_PRINT_SEL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option); - - return 0; -} + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct recv_info *precvinfo = &padapter->recvinfo; + struct recv_priv *precvpriv = &adapter_to_dvobj(padapter)->recvpriv; + struct hw_xmit *phwxmit; + struct trx_data_buf_q *litexmitbuf_q = &dvobj->litexmitbuf_q; + struct trx_data_buf_q *literecvbuf_q = &dvobj->literecvbuf_q; +#ifdef CONFIG_USB_HCI + struct trx_urb_buf_q *xmit_urb_q = &dvobj->xmit_urb_q; + struct trx_urb_buf_q *recv_urb_q = &dvobj->recv_urb_q; +#endif + u16 vo_params[4]={0}, vi_params[4]={0}, be_params[4]={0}, bk_params[4]={0}; -int proc_get_ht_option(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + rtw_hal_read_edca(padapter, vo_params, vi_params, be_params, bk_params); -#ifdef CONFIG_80211N_HT - RTW_PRINT_SEL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option); -#endif /* CONFIG_80211N_HT */ + RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]); - return 0; -} + dump_os_queue(m, padapter); -int proc_get_rf_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + #if 0 /*CONFIG_CORE_XMITBUF*/ + RTW_PRINT_SEL(m, "free_xmitbuf_cnt=%d\n" + , pxmitpriv->free_xmitbuf_cnt); + RTW_PRINT_SEL(m, "free_ext_xmitbuf_cnt=%d\n" + , pxmitpriv->free_xmit_extbuf_cnt); + #endif - RTW_PRINT_SEL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n", - pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + RTW_PRINT_SEL(m, "free_xmitframe_cnt=%d\n" + , pxmitpriv->free_xmitframe_cnt); + RTW_PRINT_SEL(m, "free_xframe_ext_cnt=%d\n" + , pxmitpriv->free_xframe_ext_cnt); + RTW_PRINT_SEL(m, "free_recvframe_cnt=%d\n" + , precvpriv->free_recvframe_cnt); - RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n", - rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter)); + RTW_PRINT_SEL(m, "free_litexmitbuf_cnt=%d\n" + , litexmitbuf_q->free_data_buf_cnt); + RTW_PRINT_SEL(m, "free_recvbuf_cnt=%d\n" + , literecvbuf_q->free_data_buf_cnt); + for (i = 0; i < 4; i++) { + phwxmit = pxmitpriv->hwxmits + i; + RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); + } + + rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m); + +#ifdef CONFIG_USB_HCI + RTW_PRINT_SEL(m, "tx_urb_cnt=%d\n", xmit_urb_q->free_urb_buf_cnt); + RTW_PRINT_SEL(m, "rx_urb_cnt=%d\n", recv_urb_q->free_urb_buf_cnt); + RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(dvobj->rx_pending_cnt))); +#endif + + /* Folowing are RX info */ + RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvinfo->dbg_rx_drop_count); + /* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */ + RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvinfo->dbg_rx_ampdu_drop_count); + /* How many times the Rx Reorder Timer is triggered. */ + RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvinfo->dbg_rx_ampdu_forced_indicate_count); + /* Total counts of packets loss */ + RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvinfo->dbg_rx_ampdu_loss_count); + RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvinfo->dbg_rx_dup_mgt_frame_drop_count); + RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvinfo->dbg_rx_ampdu_window_shift_cnt); + /*The same mac addr counts*/ + RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvinfo->dbg_rx_conflic_mac_addr_cnt); return 0; } -int proc_get_scan_param(struct seq_file *m, void *v) +static const char *rtw_data_rate_str(enum rtw_data_rate rate) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct ss_res *ss = &mlmeext->sitesurvey_res; + if (rate >= RTW_DATA_RATE_CCK1 && rate <= RTW_DATA_RATE_CCK11) { + switch (rate) { +#define CASE_CCK_RATE(cck) case RTW_DATA_RATE_CCK ## cck: return "CCK_" # cck "M" + CASE_CCK_RATE(1); + CASE_CCK_RATE(2); + CASE_CCK_RATE(5_5); + CASE_CCK_RATE(11); +#undef CASE_CCK_RATE + default: + return "CCK_UNKNOWN"; + } + } else if (rate >= RTW_DATA_RATE_OFDM6 && rate <= RTW_DATA_RATE_OFDM54) { + switch (rate) { +#define CASE_OFDM_RATE(ofdm) case RTW_DATA_RATE_OFDM ## ofdm: return "OFDM_" # ofdm "M" + CASE_OFDM_RATE(6); + CASE_OFDM_RATE(9); + CASE_OFDM_RATE(12); + CASE_OFDM_RATE(18); + CASE_OFDM_RATE(24); + CASE_OFDM_RATE(36); + CASE_OFDM_RATE(48); + CASE_OFDM_RATE(54); +#undef CASE_OFDM_RATE + default: + return "OFDM_UNKNOWN"; + } + } else if (rate >= RTW_DATA_RATE_MCS0 && rate <= RTW_DATA_RATE_MCS31) { + switch (rate) { +#define CASE_HT_RATE(mcs) case RTW_DATA_RATE_MCS ## mcs: return "MCS_" # mcs + CASE_HT_RATE(0); + CASE_HT_RATE(1); + CASE_HT_RATE(2); + CASE_HT_RATE(3); + CASE_HT_RATE(4); + CASE_HT_RATE(5); + CASE_HT_RATE(6); + CASE_HT_RATE(7); + CASE_HT_RATE(8); + CASE_HT_RATE(9); + CASE_HT_RATE(10); + CASE_HT_RATE(11); + CASE_HT_RATE(12); + CASE_HT_RATE(13); + CASE_HT_RATE(14); + CASE_HT_RATE(15); + CASE_HT_RATE(16); + CASE_HT_RATE(17); + CASE_HT_RATE(18); + CASE_HT_RATE(19); + CASE_HT_RATE(20); + CASE_HT_RATE(21); + CASE_HT_RATE(22); + CASE_HT_RATE(23); + CASE_HT_RATE(24); + CASE_HT_RATE(25); + CASE_HT_RATE(26); + CASE_HT_RATE(27); + CASE_HT_RATE(28); + CASE_HT_RATE(29); + CASE_HT_RATE(30); + CASE_HT_RATE(31); +#undef CASE_HT_RATE + default: + return "HT_UNKNOWN"; + } + } else if (rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS4_MCS9) { + switch (rate) { +#define CASE_VHT_RATE(ss, mcs) case RTW_DATA_RATE_VHT_NSS ## ss ##_MCS ##mcs: return "VHT_SS" #ss "MCS" #mcs + CASE_VHT_RATE(1, 0); + CASE_VHT_RATE(1, 1); + CASE_VHT_RATE(1, 2); + CASE_VHT_RATE(1, 3); + CASE_VHT_RATE(1, 4); + CASE_VHT_RATE(1, 5); + CASE_VHT_RATE(1, 6); + CASE_VHT_RATE(1, 7); + CASE_VHT_RATE(1, 8); + CASE_VHT_RATE(1, 9); + CASE_VHT_RATE(2, 0); + CASE_VHT_RATE(2, 1); + CASE_VHT_RATE(2, 2); + CASE_VHT_RATE(2, 3); + CASE_VHT_RATE(2, 4); + CASE_VHT_RATE(2, 5); + CASE_VHT_RATE(2, 6); + CASE_VHT_RATE(2, 7); + CASE_VHT_RATE(2, 8); + CASE_VHT_RATE(2, 9); + CASE_VHT_RATE(3, 0); + CASE_VHT_RATE(3, 1); + CASE_VHT_RATE(3, 2); + CASE_VHT_RATE(3, 3); + CASE_VHT_RATE(3, 4); + CASE_VHT_RATE(3, 5); + CASE_VHT_RATE(3, 6); + CASE_VHT_RATE(3, 7); + CASE_VHT_RATE(3, 8); + CASE_VHT_RATE(3, 9); + CASE_VHT_RATE(4, 0); + CASE_VHT_RATE(4, 1); + CASE_VHT_RATE(4, 2); + CASE_VHT_RATE(4, 3); + CASE_VHT_RATE(4, 4); + CASE_VHT_RATE(4, 5); + CASE_VHT_RATE(4, 6); + CASE_VHT_RATE(4, 7); + CASE_VHT_RATE(4, 8); + CASE_VHT_RATE(4, 9); +#undef CASE_VHT_RATE + default: + return "VHT_UNKNOWN"; + } + } else if (rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rate <= RTW_DATA_RATE_HE_NSS4_MCS11) { + switch (rate) { +#define CASE_HE_RATE(ss, mcs) case RTW_DATA_RATE_HE_NSS ## ss ##_MCS ##mcs: return "HE_SS" #ss "MCS" #mcs + CASE_HE_RATE(1, 0); + CASE_HE_RATE(1, 1); + CASE_HE_RATE(1, 2); + CASE_HE_RATE(1, 3); + CASE_HE_RATE(1, 4); + CASE_HE_RATE(1, 5); + CASE_HE_RATE(1, 6); + CASE_HE_RATE(1, 7); + CASE_HE_RATE(1, 8); + CASE_HE_RATE(1, 9); + CASE_HE_RATE(1, 10); + CASE_HE_RATE(1, 11); + CASE_HE_RATE(2, 0); + CASE_HE_RATE(2, 1); + CASE_HE_RATE(2, 2); + CASE_HE_RATE(2, 3); + CASE_HE_RATE(2, 4); + CASE_HE_RATE(2, 5); + CASE_HE_RATE(2, 6); + CASE_HE_RATE(2, 7); + CASE_HE_RATE(2, 8); + CASE_HE_RATE(2, 9); + CASE_HE_RATE(2, 10); + CASE_HE_RATE(2, 11); + CASE_HE_RATE(3, 0); + CASE_HE_RATE(3, 1); + CASE_HE_RATE(3, 2); + CASE_HE_RATE(3, 3); + CASE_HE_RATE(3, 4); + CASE_HE_RATE(3, 5); + CASE_HE_RATE(3, 6); + CASE_HE_RATE(3, 7); + CASE_HE_RATE(3, 8); + CASE_HE_RATE(3, 9); + CASE_HE_RATE(3, 10); + CASE_HE_RATE(3, 11); + CASE_HE_RATE(4, 0); + CASE_HE_RATE(4, 1); + CASE_HE_RATE(4, 2); + CASE_HE_RATE(4, 3); + CASE_HE_RATE(4, 4); + CASE_HE_RATE(4, 5); + CASE_HE_RATE(4, 6); + CASE_HE_RATE(4, 7); + CASE_HE_RATE(4, 8); + CASE_HE_RATE(4, 9); + CASE_HE_RATE(4, 10); + CASE_HE_RATE(4, 11); +#undef CASE_HE_RATE + default: + return "HE_UNKNOWN"; + } + } -#define SCAN_PARAM_TITLE_FMT "%10s" -#define SCAN_PARAM_VALUE_FMT "%-10u" -#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms" -#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms -#ifdef CONFIG_80211N_HT -#define SCAN_PARAM_TITLE_FMT_HT " %15s %13s" -#define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u" -#define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size" -#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size -#else -#define SCAN_PARAM_TITLE_FMT_HT "" -#define SCAN_PARAM_VALUE_FMT_HT "" -#define SCAN_PARAM_TITLE_ARG_HT -#define SCAN_PARAM_VALUE_ARG_HT -#endif -#ifdef CONFIG_SCAN_BACKOP -#define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s" -#define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u" -#define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max" -#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max -#else -#define SCAN_PARAM_TITLE_FMT_BACKOP "" -#define SCAN_PARAM_VALUE_FMT_BACKOP "" -#define SCAN_PARAM_TITLE_ARG_BACKOP -#define SCAN_PARAM_VALUE_ARG_BACKOP -#endif + return "ALL_UNKNOWN"; +} - RTW_PRINT_SEL(m, - SCAN_PARAM_TITLE_FMT - SCAN_PARAM_TITLE_FMT_HT - SCAN_PARAM_TITLE_FMT_BACKOP - "\n" - SCAN_PARAM_TITLE_ARG - SCAN_PARAM_TITLE_ARG_HT - SCAN_PARAM_TITLE_ARG_BACKOP - ); +int proc_get_rate_ctl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u16 data_rate = 0; + u8 sgi = 0, data_fb = 0; - RTW_PRINT_SEL(m, - SCAN_PARAM_VALUE_FMT - SCAN_PARAM_VALUE_FMT_HT - SCAN_PARAM_VALUE_FMT_BACKOP - "\n" - SCAN_PARAM_VALUE_ARG - SCAN_PARAM_VALUE_ARG_HT - SCAN_PARAM_VALUE_ARG_BACKOP - ); + if (adapter->fix_rate != NO_FIX_RATE) { + data_rate = GET_FIX_RATE(adapter->fix_rate); + sgi = GET_FIX_RATE_SGI(adapter->fix_rate); + data_fb = adapter->data_fb ? 1 : 0; + RTW_PRINT_SEL(m, "FIXED %s%s%s\n" + , rtw_data_rate_str(data_rate) + , data_rate >= RTW_DATA_RATE_MCS0 ? (sgi ? " SGI" : " LGI") : "" + , data_fb ? " FB" : "" + ); + RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb); + } else + RTW_PRINT_SEL(m, "RA\n"); return 0; } -ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct ss_res *ss = &mlmeext->sitesurvey_res; - - char tmp[32] = {0}; + char tmp[32]; + u16 fix_rate = NO_FIX_RATE; + u8 data_fb = 0; - u16 scan_ch_ms; -#define SCAN_PARAM_INPUT_FMT "%hu" -#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms -#ifdef CONFIG_80211N_HT - u8 rx_ampdu_accept; - u8 rx_ampdu_size; -#define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu" -#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size -#else -#define SCAN_PARAM_INPUT_FMT_HT "" -#define SCAN_PARAM_INPUT_ARG_HT -#endif -#ifdef CONFIG_SCAN_BACKOP - u16 backop_ms; - u8 scan_cnt_max; -#define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu" -#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max -#else -#define SCAN_PARAM_INPUT_FMT_BACKOP "" -#define SCAN_PARAM_INPUT_ARG_BACKOP -#endif if (count < 1) return -EFAULT; @@ -2142,68 +2022,87 @@ ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hx %hhu", &fix_rate, &data_fb); - int num = sscanf(tmp, - SCAN_PARAM_INPUT_FMT - SCAN_PARAM_INPUT_FMT_HT - SCAN_PARAM_INPUT_FMT_BACKOP - SCAN_PARAM_INPUT_ARG - SCAN_PARAM_INPUT_ARG_HT - SCAN_PARAM_INPUT_ARG_BACKOP - ); + if (num >= 1) { + u16 fix_rate_ori = adapter->fix_rate; - if (num-- > 0) - ss->scan_ch_ms = scan_ch_ms; -#ifdef CONFIG_80211N_HT - if (num-- > 0) - ss->rx_ampdu_accept = rx_ampdu_accept; - if (num-- > 0) - ss->rx_ampdu_size = rx_ampdu_size; -#endif -#ifdef CONFIG_SCAN_BACKOP - if (num-- > 0) - ss->backop_ms = backop_ms; - if (num-- > 0) - ss->scan_cnt_max = scan_cnt_max; -#endif + adapter->fix_rate = fix_rate; + #if 0 /*GEORGIA_TODO_FIXIT*/ + if (fix_rate == 0xFF) + hal_data->ForcedDataRate = 0; + else + hal_data->ForcedDataRate = hwrate_to_mrate(fix_rate & 0x7F); + #endif + if (adapter->fix_bw != NO_FIX_BW && fix_rate_ori != fix_rate) + rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter)); + } + if (num >= 2) + adapter->data_fb = data_fb ? 1 : 0; } return count; } -int proc_get_scan_abort(struct seq_file *m, void *v) +#ifdef CONFIG_AP_MODE +int proc_get_bmc_tx_rate(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u32 pass_ms; - - pass_ms = rtw_scan_abort_timeout(adapter, 10000); - RTW_PRINT_SEL(m, "%u\n", pass_ms); + if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) { + RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n"); + return 0; + } + RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate)); return 0; } -#ifdef CONFIG_RTW_REPEATER_SON -int proc_get_rson_data(struct seq_file *m, void *v) +ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 bmc_tx_rate; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &bmc_tx_rate); + + if (num >= 1) + /*adapter->bmc_tx_rate = hwrate_to_mrate(bmc_tx_rate);*/ + adapter->bmc_tx_rate = bmc_tx_rate; + } + + return count; +} +#endif /*CONFIG_AP_MODE*/ + + +int proc_get_tx_power_offset(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char rson_data_str[256]; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - rtw_rson_get_property_str(padapter, rson_data_str); - RTW_PRINT_SEL(m, "%s\n", rson_data_str); + RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset); return 0; } -ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); - char tmp[64] = {0}; - int num; - u8 field[10], value[64]; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 power_offset = 0; if (count < 1) return -EFAULT; @@ -2214,130 +2113,87 @@ ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%s %s", field, value); - if (num != 2) { - RTW_INFO("Invalid format : echo > son_data\n"); - return count; - } - RTW_INFO("field=%s value=%s\n", field, value); - num = rtw_rson_set_property(padapter, field, value); - if (num != 1) { - RTW_INFO("Invalid field(%s) or value(%s)\n", field, value); - return count; + + int num = sscanf(tmp, "%hhu", &power_offset); + + if (num >= 1) { + if (power_offset > 5) + power_offset = 0; + + adapter->power_offset = power_offset; } } + return count; } -#endif /*CONFIG_RTW_REPEATER_SON*/ -int proc_get_survey_info(struct seq_file *m, void *v) +int proc_get_bw_ctl(struct seq_file *m, void *v) { - _irqL irqL; struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - _list *plist, *phead; - s32 notify_signal; - s16 notify_noise = 0; - u16 index = 0, ie_cap = 0; - unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL; - unsigned char *ie_p2p = NULL, *ssid = NULL; - char flag_str[64]; - int ielen = 0; - u32 wpsielen = 0; -#ifdef CONFIG_RTW_MESH - const char *ssid_title_str = "ssid/mesh_id"; -#else - const char *ssid_title_str = "ssid"; -#endif - u8 rsni = 255; - - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - phead = get_list_head(queue); - if (!phead) - goto _exit; - plist = get_next(phead); - if (!plist) - goto _exit; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 data_bw = 0; -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_show_survey_info(m, plist, phead); -#else + if (adapter->fix_bw != NO_FIX_BW) { + data_bw = adapter->fix_bw; + RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw)); + } else + RTW_PRINT_SEL(m, "Auto\n"); - RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %4s %5s %32s %32s \n", - "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "rsni", "age", "flag", ssid_title_str); - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + return 0; +} - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (!pnetwork) - break; +ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 fix_bw; - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { - notify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);/* dbm */ - } else { - notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */ - } + if (count < 1) + return -EFAULT; -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - if (IS_NM_ENABLE(padapter)) - notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); -#endif -#ifdef CONFIG_RTW_ACS - rsni = rtw_acs_get_rsni(padapter, (int)(pnetwork->network.Rssi), pnetwork->network.Configuration.DSConfig); -#endif + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } - ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); - ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); - ie_cap = rtw_get_capability(&pnetwork->network); - ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen); -#ifdef CONFIG_P2P - ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen); -#endif - ssid = pnetwork->network.Ssid.Ssid; - sprintf(flag_str, "%s%s%s%s%s%s%s", - (ie_wpa) ? "[WPA]" : "", - (ie_wpa2) ? "[WPA2]" : "", - (!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "", - (ie_wps) ? "[WPS]" : "", - (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : - (pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "", - (ie_cap & BIT(0)) ? "[ESS]" : "", - (ie_p2p) ? "[P2P]" : ""); - RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d %4d %4d %4d %4d %5d %32s %32s\n", - ++index, - MAC_ARG(pnetwork->network.MacAddress), - pnetwork->network.Configuration.DSConfig, - (int)pnetwork->network.Rssi, - notify_signal, - notify_noise, - rsni, - rtw_get_passing_time_ms(pnetwork->last_scanned), - flag_str, - pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid - ); - plist = get_next(plist); + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu", &fix_bw); + + if (num >= 1) { + u8 fix_bw_ori = adapter->fix_bw; + + adapter->fix_bw = fix_bw; + + if (adapter->fix_rate != NO_FIX_RATE && fix_bw_ori != fix_bw) + rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter)); + } } -#endif -_exit: - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - return 0; + return count; } -ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +#ifdef DBG_RX_COUNTER_DUMP +int proc_get_rx_cnt_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n"); + RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n"); + RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n"); + RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n"); + RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode); + + return 0; +} +ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 _status = _FALSE; - u8 ssc_chk; - char tmp[32] = {0}; - char cmd[8] = {0}; - bool acs = 0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 dump_rx_cnt_mode; if (count < 1) return -EFAULT; @@ -2348,338 +2204,157 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_ } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%s", cmd); - if (num < 1) - return count; + int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode); - if (strcmp("acs", cmd) == 0) - acs = 1; + if (num == 1) { + rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode); + adapter->dump_rx_cnt_mode = dump_rx_cnt_mode; + } } -#if 1 - ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); - if (ssc_chk != SS_ALLOW) - goto exit; - - rtw_ps_deny(padapter, PS_DENY_SCAN); - if (_FAIL == rtw_pwr_wakeup(padapter)) - goto cancel_ps_deny; - if (!rtw_is_adapter_up(padapter)) { - RTW_INFO("scan abort!! adapter cannot use\n"); - goto cancel_ps_deny; - } -#else -#ifdef CONFIG_MP_INCLUDED - if (rtw_mp_mode_check(padapter)) { - RTW_INFO("MP mode block Scan request\n"); - goto exit; - } + return count; +} #endif - if (rtw_is_scan_deny(padapter)) { - RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } - rtw_ps_deny(padapter, PS_DENY_SCAN); - if (_FAIL == rtw_pwr_wakeup(padapter)) - goto cancel_ps_deny; - if (!rtw_is_adapter_up(padapter)) { - RTW_INFO("scan abort!! adapter cannot use\n"); - goto cancel_ps_deny; +ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - if (rtw_mi_busy_traffic_check(padapter)) { - RTW_INFO("scan abort!! BusyTraffic == _TRUE\n"); - goto cancel_ps_deny; + if (buffer && !copy_from_user(tmp, buffer, count)) + sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail); + + return count; +} + +ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - RTW_INFO("scan abort!! AP mode process WPS\n"); - goto cancel_ps_deny; + if (buffer && !copy_from_user(tmp, buffer, count)) + sscanf(tmp, "%u", &g_wait_hiq_empty_ms); + + return count; +} + +ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state); - goto cancel_ps_deny; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + u32 wait_ms = 0; + u8 force_fail = 0; + int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail); + + if (num >= 1) + sta_linking_test_wait_ms = wait_ms; + if (num >= 2) + sta_linking_test_force_fail = force_fail; } -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, - WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) { - RTW_INFO("scan abort!! buddy_fwstate check failed\n"); - goto cancel_ps_deny; + return count; +} + +#ifdef CONFIG_AP_MODE +ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } -#endif -#endif - if (acs) { - #ifdef CONFIG_RTW_ACS - _status = rtw_set_acs_sitesurvey(padapter); - #endif - } else - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); + if (buffer && !copy_from_user(tmp, buffer, count)) { + u16 force_auth_fail = 0; + u16 force_asoc_fail = 0; + int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail); + + if (num >= 1) + ap_linking_test_force_auth_fail = force_auth_fail; + if (num >= 2) + ap_linking_test_force_asoc_fail = force_asoc_fail; + } -cancel_ps_deny: - rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); -exit: return count; } -#ifdef ROKU_PRIVATE -int proc_get_infra_ap(struct seq_file *m, void *v) +#endif /* CONFIG_AP_MODE */ + +int proc_get_ps_dbg_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; - struct sta_info *psta; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; -#ifdef CONFIG_80211AC_VHT - struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap; -#endif - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct sta_priv *pstapriv = &padapter->stapriv; - - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); - if (psta) { - unsigned int i, j; - unsigned int Rx_ss = 0, Tx_ss = 0; - struct recv_reorder_ctrl *preorder_ctrl; - - RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - RTW_PRINT_SEL(m, "Supported rate="); - for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { - if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) - break; - RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]); - } - RTW_PRINT_SEL(m, "\n"); -#ifdef CONFIG_80211N_HT - if (pmlmeinfo->ht_vht_received & BIT(0)) { - RTW_PRINT_SEL(m, "Supported MCS set="); - for (i = 0; i < 16 ; i++) - RTW_PRINT_SEL(m, " 0x%02x", phtpriv->MCS_set_infra_ap[i]); - RTW_PRINT_SEL(m, "\n"); - RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap); - RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap); - RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap); - RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap); - RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap); - } -#endif - -#ifdef CONFIG_80211AC_VHT - if (pmlmeinfo->ht_vht_received & BIT(1)) { - RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap); - RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap); - RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap); - RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap); - } -#endif - } else - RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); - } else - RTW_PRINT_SEL(m, "this only applies to STA mode\n"); - return 0; -} - -#endif /* ROKU_PRIVATE */ - -static int wireless_mode_to_str(u32 mode, char *str) -{ - str[0]='\0'; - if (mode&WIRELESS_11A) - sprintf(str+strlen(str),"%s","A/"); - if (mode&WIRELESS_11B) - sprintf(str+strlen(str),"%s","B/"); - if (mode&WIRELESS_11G) - sprintf(str+strlen(str),"%s","G/"); - if (mode&(WIRELESS_11_24N|WIRELESS_11_5N)) - sprintf(str+strlen(str),"%s","N/"); - if (mode&WIRELESS_11AC) - sprintf(str+strlen(str),"%s","AC/"); - - if (strlen(str)>1) - str[strlen(str)-1]='\0'; - - return strlen(str); -} - -int proc_get_ap_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - struct sta_info *psta; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_priv *pstapriv = &padapter->stapriv; - char wl_mode[16]; - - /* ap vendor */ - char vendor[VENDOR_NAME_LEN] = {0}; - get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor); - RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor); - - psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); - if (psta) { - wireless_mode_to_str(psta->wireless_mode, wl_mode); - RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d(%s), cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, ch_width_str(pmlmeext->cur_bwmode), pmlmeext->cur_ch_offset); - RTW_PRINT_SEL(m, "wireless_mode=0x%x(%s), rtsen=%d, cts2slef=%d\n", psta->wireless_mode, wl_mode, psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", - psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); -#ifdef CONFIG_80211N_HT - RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" - , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); - RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); - RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); - RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap); -#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT - RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m); - RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); - RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); -#endif - sta_rx_reorder_ctl_dump(m, psta); - } else - RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); - - return 0; -} - -ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct recv_priv *precvpriv = &padapter->recvpriv; - char cmd[32] = {0}; - u8 cnt = 0; - - if (count > sizeof(cmd)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(cmd, buffer, count)) { - int num = sscanf(cmd, "%hhx", &cnt); - - if (num == 1 && cnt == 0) { - precvpriv->dbg_rx_ampdu_drop_count = 0; - precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; - precvpriv->dbg_rx_ampdu_loss_count = 0; - precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; - precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; - precvpriv->dbg_rx_drop_count = 0; - } - } - - return count; -} - -int proc_get_trx_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - int i; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct recv_priv *precvpriv = &padapter->recvpriv; - struct hw_xmit *phwxmit; - u16 vo_params[4], vi_params[4], be_params[4], bk_params[4]; - - padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params); - - RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]); - RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]); - RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]); - RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]); - - dump_os_queue(m, padapter); - - RTW_PRINT_SEL(m, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n" - , pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt); - RTW_PRINT_SEL(m, "free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\n" - , pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt); - RTW_PRINT_SEL(m, "free_recvframe_cnt=%d\n" - , precvpriv->free_recvframe_cnt); - - for (i = 0; i < pxmitpriv->hwxmit_entry; i++) { - phwxmit = pxmitpriv->hwxmits + i; -#ifdef CONFIG_RTW_MGMT_QUEUE - if (i == pxmitpriv->hwxmit_entry - 1) - RTW_PRINT_SEL(m, "%d, hw_mgmt_q.accnt=%d\n", i, phwxmit->accnt); - else -#endif - RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); - } - - rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m); - -#ifdef CONFIG_USB_HCI - RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); -#endif - - dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv); - - /* Folowing are RX info */ - RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count); - /* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */ - RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count); - /* How many times the Rx Reorder Timer is triggered. */ - RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count); - /* Total counts of packets loss */ - RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count); - RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count); - RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt); - /*The same mac addr counts*/ - RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt); - return 0; -} - -int proc_get_rate_ctl(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 data_rate = 0, sgi = 0, data_fb = 0; + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - if (adapter->fix_rate != 0xff) { - data_rate = adapter->fix_rate & 0x7F; - sgi = adapter->fix_rate >> 7; - data_fb = adapter->data_fb ? 1 : 0; - RTW_PRINT_SEL(m, "FIXED %s%s%s\n" - , HDATA_RATE(data_rate) - , data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : "" - , data_fb ? " FB" : "" - ); - RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb); - } else - RTW_PRINT_SEL(m, "RA\n"); + RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt); + RTW_PRINT_SEL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt); + RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_error_cnt); + RTW_PRINT_SEL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt); + RTW_PRINT_SEL(m, "dbg_sdio_init_error_cnt=%d\n", pdbgpriv->dbg_sdio_init_error_cnt); + RTW_PRINT_SEL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt); + RTW_PRINT_SEL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt); + RTW_PRINT_SEL(m, "dbg_suspend_cnt=%d\n", pdbgpriv->dbg_suspend_cnt); + RTW_PRINT_SEL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt); + RTW_PRINT_SEL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt); + RTW_PRINT_SEL(m, "dbg_deinit_fail_cnt=%d\n", pdbgpriv->dbg_deinit_fail_cnt); + RTW_PRINT_SEL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt); + RTW_PRINT_SEL(m, "dbg_ps_insuspend_cnt=%d\n", pdbgpriv->dbg_ps_insuspend_cnt); + RTW_PRINT_SEL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt); + RTW_PRINT_SEL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt); + RTW_PRINT_SEL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt); + RTW_PRINT_SEL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt); + RTW_PRINT_SEL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt); + RTW_PRINT_SEL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt); + RTW_PRINT_SEL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt); + RTW_PRINT_SEL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt); + RTW_PRINT_SEL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt); + RTW_PRINT_SEL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt); + RTW_PRINT_SEL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt); + RTW_PRINT_SEL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt); + RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt); + RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt); + RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt); + RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt); return 0; } - -#ifdef CONFIG_PHDYM_FW_FIXRATE -void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate); -#endif -ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dvobj_priv *dvobj = adapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; char tmp[32]; - u8 fix_rate = 0xFF; -#ifdef CONFIG_PHDYM_FW_FIXRATE - u8 bw = 0; -#else - u8 data_fb = 0; -#endif + u8 ps_dbg_cmd_id; if (count < 1) return -EFAULT; @@ -2690,1306 +2365,312 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c } if (buffer && !copy_from_user(tmp, buffer, count)) { -#ifdef CONFIG_PHDYM_FW_FIXRATE - struct dm_struct *dm = adapter_to_phydm(adapter); - u8 en = 1, macid = 255; - _irqL irqL; - _list *plist, *phead; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &(adapter->stapriv); - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - uint mac_id[NUM_STA]; - int i, macid_rec_idx = 0; - int num = sscanf(tmp, "%hhx %hhu %hhu", &fix_rate, &bw, &macid); - - if (num < 1) { - RTW_INFO("Invalid input!! \"ex: echo > /proc/.../rate_ctl\"\n"); - return count; - } - - if ((fix_rate == 0) || (fix_rate == 0xFF)) - en = 0; - - if (macid != 255) { - RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, macid, bw, fix_rate); - phydm_fw_fix_rate(dm, en, macid, bw, fix_rate); - return count; - } - - /* no specific macid, apply to all macids except bc/mc macid */ - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (i = 0; i < NUM_STA; i++) { - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); - if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { - mac_id[macid_rec_idx] = psta->cmn.mac_id; - macid_rec_idx++; - } - } - } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - - for (i = 0; i < macid_rec_idx; i++) { - RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, mac_id[i], bw, fix_rate); - phydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate); - } -#else - int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb); - if (num >= 1) { - u8 fix_rate_ori = adapter->fix_rate; + int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id); - adapter->fix_rate = fix_rate; - if (fix_rate == 0xFF) - hal_data->ForcedDataRate = 0; - else - hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F); + if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/ + _rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv)); - if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate) - rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter)); - } - if (num >= 2) - adapter->data_fb = data_fb ? 1 : 0; -#endif } return count; } -#ifdef CONFIG_AP_MODE -int proc_get_bmc_tx_rate(struct seq_file *m, void *v) + +#ifdef CONFIG_DBG_COUNTER + +int proc_get_rx_logs(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rx_logs *rx_logs = &padapter->rx_logs; - if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) { - RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n"); - return 0; - } - - RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate)); - return 0; -} - -ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 bmc_tx_rate; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &bmc_tx_rate); - - if (num >= 1) - /*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/ - adapter->bmc_tx_rate = bmc_tx_rate; - } - - return count; -} -#endif /*CONFIG_AP_MODE*/ - - -int proc_get_tx_power_offset(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset); - return 0; -} - -ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 power_offset = 0; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu", &power_offset); - - if (num >= 1) { - if (power_offset > 5) - power_offset = 0; - - adapter->power_offset = power_offset; - } - } - - return count; -} - -int proc_get_bw_ctl(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 data_bw = 0; - - if (adapter->fix_bw != 0xff) { - data_bw = adapter->fix_bw; - RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw)); - } else - RTW_PRINT_SEL(m, "Auto\n"); - - return 0; -} - -ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 fix_bw; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu", &fix_bw); - - if (num >= 1) { - u8 fix_bw_ori = adapter->fix_bw; - - adapter->fix_bw = fix_bw; - - if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw) - rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter)); - } - } - - return count; -} - -#ifdef DBG_RX_COUNTER_DUMP -int proc_get_rx_cnt_dump(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - int i; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n"); - RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n"); - RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n"); - RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n"); - RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode); - - return 0; -} -ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 dump_rx_cnt_mode; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode); - - if (num == 1) { - rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode); - adapter->dump_rx_cnt_mode = dump_rx_cnt_mode; - } - } - - return count; -} -#endif - -ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) - sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail); - - return count; -} - -ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) - sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail); - - return count; -} - -ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) - sscanf(tmp, "%u", &g_wait_hiq_empty_ms); - - return count; -} - -ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - u32 wait_ms = 0; - u8 force_fail = 0; - int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail); - - if (num >= 1) - sta_linking_test_wait_ms = wait_ms; - if (num >= 2) - sta_linking_test_force_fail = force_fail; - } - - return count; -} - -#ifdef CONFIG_AP_MODE -ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - u16 force_auth_fail = 0; - u16 force_asoc_fail = 0; - int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail); - - if (num >= 1) - ap_linking_test_force_auth_fail = force_auth_fail; - if (num >= 2) - ap_linking_test_force_asoc_fail = force_asoc_fail; - } - - return count; -} -#endif /* CONFIG_AP_MODE */ - -int proc_get_ps_dbg_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = padapter->dvobj; - struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - - RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt); - RTW_PRINT_SEL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt); - RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_error_cnt); - RTW_PRINT_SEL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt); - RTW_PRINT_SEL(m, "dbg_sdio_init_error_cnt=%d\n", pdbgpriv->dbg_sdio_init_error_cnt); - RTW_PRINT_SEL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt); - RTW_PRINT_SEL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt); - RTW_PRINT_SEL(m, "dbg_suspend_cnt=%d\n", pdbgpriv->dbg_suspend_cnt); - RTW_PRINT_SEL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt); - RTW_PRINT_SEL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt); - RTW_PRINT_SEL(m, "dbg_deinit_fail_cnt=%d\n", pdbgpriv->dbg_deinit_fail_cnt); - RTW_PRINT_SEL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt); - RTW_PRINT_SEL(m, "dbg_ps_insuspend_cnt=%d\n", pdbgpriv->dbg_ps_insuspend_cnt); - RTW_PRINT_SEL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt); - RTW_PRINT_SEL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt); - RTW_PRINT_SEL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt); - RTW_PRINT_SEL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt); - RTW_PRINT_SEL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt); - RTW_PRINT_SEL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt); - RTW_PRINT_SEL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt); - RTW_PRINT_SEL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt); - RTW_PRINT_SEL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt); - RTW_PRINT_SEL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt); - RTW_PRINT_SEL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt); - RTW_PRINT_SEL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt); - RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt); - RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt); - RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt); - RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt); - - return 0; -} -ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter->dvobj; - struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - char tmp[32]; - u8 ps_dbg_cmd_id; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id); - - if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/ - _rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv)); - - } - - return count; -} - - -#ifdef CONFIG_DBG_COUNTER - -int proc_get_rx_logs(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct rx_logs *rx_logs = &padapter->rx_logs; - - RTW_PRINT_SEL(m, - "intf_rx=%d\n" - "intf_rx_err_recvframe=%d\n" - "intf_rx_err_skb=%d\n" - "intf_rx_report=%d\n" - "core_rx=%d\n" - "core_rx_pre=%d\n" - "core_rx_pre_ver_err=%d\n" - "core_rx_pre_mgmt=%d\n" - "core_rx_pre_mgmt_err_80211w=%d\n" - "core_rx_pre_mgmt_err=%d\n" - "core_rx_pre_ctrl=%d\n" - "core_rx_pre_ctrl_err=%d\n" - "core_rx_pre_data=%d\n" - "core_rx_pre_data_wapi_seq_err=%d\n" - "core_rx_pre_data_wapi_key_err=%d\n" - "core_rx_pre_data_handled=%d\n" - "core_rx_pre_data_err=%d\n" - "core_rx_pre_data_unknown=%d\n" - "core_rx_pre_unknown=%d\n" - "core_rx_enqueue=%d\n" - "core_rx_dequeue=%d\n" - "core_rx_post=%d\n" - "core_rx_post_decrypt=%d\n" - "core_rx_post_decrypt_wep=%d\n" - "core_rx_post_decrypt_tkip=%d\n" - "core_rx_post_decrypt_aes=%d\n" - "core_rx_post_decrypt_wapi=%d\n" - "core_rx_post_decrypt_hw=%d\n" - "core_rx_post_decrypt_unknown=%d\n" - "core_rx_post_decrypt_err=%d\n" - "core_rx_post_defrag_err=%d\n" - "core_rx_post_portctrl_err=%d\n" - "core_rx_post_indicate=%d\n" - "core_rx_post_indicate_in_oder=%d\n" - "core_rx_post_indicate_reoder=%d\n" - "core_rx_post_indicate_err=%d\n" - "os_indicate=%d\n" - "os_indicate_ap_mcast=%d\n" - "os_indicate_ap_forward=%d\n" - "os_indicate_ap_self=%d\n" - "os_indicate_err=%d\n" - "os_netif_ok=%d\n" - "os_netif_err=%d\n", - rx_logs->intf_rx, - rx_logs->intf_rx_err_recvframe, - rx_logs->intf_rx_err_skb, - rx_logs->intf_rx_report, - rx_logs->core_rx, - rx_logs->core_rx_pre, - rx_logs->core_rx_pre_ver_err, - rx_logs->core_rx_pre_mgmt, - rx_logs->core_rx_pre_mgmt_err_80211w, - rx_logs->core_rx_pre_mgmt_err, - rx_logs->core_rx_pre_ctrl, - rx_logs->core_rx_pre_ctrl_err, - rx_logs->core_rx_pre_data, - rx_logs->core_rx_pre_data_wapi_seq_err, - rx_logs->core_rx_pre_data_wapi_key_err, - rx_logs->core_rx_pre_data_handled, - rx_logs->core_rx_pre_data_err, - rx_logs->core_rx_pre_data_unknown, - rx_logs->core_rx_pre_unknown, - rx_logs->core_rx_enqueue, - rx_logs->core_rx_dequeue, - rx_logs->core_rx_post, - rx_logs->core_rx_post_decrypt, - rx_logs->core_rx_post_decrypt_wep, - rx_logs->core_rx_post_decrypt_tkip, - rx_logs->core_rx_post_decrypt_aes, - rx_logs->core_rx_post_decrypt_wapi, - rx_logs->core_rx_post_decrypt_hw, - rx_logs->core_rx_post_decrypt_unknown, - rx_logs->core_rx_post_decrypt_err, - rx_logs->core_rx_post_defrag_err, - rx_logs->core_rx_post_portctrl_err, - rx_logs->core_rx_post_indicate, - rx_logs->core_rx_post_indicate_in_oder, - rx_logs->core_rx_post_indicate_reoder, - rx_logs->core_rx_post_indicate_err, - rx_logs->os_indicate, - rx_logs->os_indicate_ap_mcast, - rx_logs->os_indicate_ap_forward, - rx_logs->os_indicate_ap_self, - rx_logs->os_indicate_err, - rx_logs->os_netif_ok, - rx_logs->os_netif_err - ); - - return 0; -} - -int proc_get_tx_logs(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct tx_logs *tx_logs = &padapter->tx_logs; - - RTW_PRINT_SEL(m, - "os_tx=%d\n" - "os_tx_err_up=%d\n" - "os_tx_err_xmit=%d\n" - "os_tx_m2u=%d\n" - "os_tx_m2u_ignore_fw_linked=%d\n" - "os_tx_m2u_ignore_self=%d\n" - "os_tx_m2u_entry=%d\n" - "os_tx_m2u_entry_err_xmit=%d\n" - "os_tx_m2u_entry_err_skb=%d\n" - "os_tx_m2u_stop=%d\n" - "core_tx=%d\n" - "core_tx_err_pxmitframe=%d\n" - "core_tx_err_brtx=%d\n" - "core_tx_upd_attrib=%d\n" - "core_tx_upd_attrib_adhoc=%d\n" - "core_tx_upd_attrib_sta=%d\n" - "core_tx_upd_attrib_ap=%d\n" - "core_tx_upd_attrib_unknown=%d\n" - "core_tx_upd_attrib_dhcp=%d\n" - "core_tx_upd_attrib_icmp=%d\n" - "core_tx_upd_attrib_active=%d\n" - "core_tx_upd_attrib_err_ucast_sta=%d\n" - "core_tx_upd_attrib_err_ucast_ap_link=%d\n" - "core_tx_upd_attrib_err_sta=%d\n" - "core_tx_upd_attrib_err_link=%d\n" - "core_tx_upd_attrib_err_sec=%d\n" - "core_tx_ap_enqueue_warn_fwstate=%d\n" - "core_tx_ap_enqueue_warn_sta=%d\n" - "core_tx_ap_enqueue_warn_nosta=%d\n" - "core_tx_ap_enqueue_warn_link=%d\n" - "core_tx_ap_enqueue_warn_trigger=%d\n" - "core_tx_ap_enqueue_mcast=%d\n" - "core_tx_ap_enqueue_ucast=%d\n" - "core_tx_ap_enqueue=%d\n" - "intf_tx=%d\n" - "intf_tx_pending_ac=%d\n" - "intf_tx_pending_fw_under_survey=%d\n" - "intf_tx_pending_fw_under_linking=%d\n" - "intf_tx_pending_xmitbuf=%d\n" - "intf_tx_enqueue=%d\n" - "core_tx_enqueue=%d\n" - "core_tx_enqueue_class=%d\n" - "core_tx_enqueue_class_err_sta=%d\n" - "core_tx_enqueue_class_err_nosta=%d\n" - "core_tx_enqueue_class_err_fwlink=%d\n" - "intf_tx_direct=%d\n" - "intf_tx_direct_err_coalesce=%d\n" - "intf_tx_dequeue=%d\n" - "intf_tx_dequeue_err_coalesce=%d\n" - "intf_tx_dump_xframe=%d\n" - "intf_tx_dump_xframe_err_txdesc=%d\n" - "intf_tx_dump_xframe_err_port=%d\n", - tx_logs->os_tx, - tx_logs->os_tx_err_up, - tx_logs->os_tx_err_xmit, - tx_logs->os_tx_m2u, - tx_logs->os_tx_m2u_ignore_fw_linked, - tx_logs->os_tx_m2u_ignore_self, - tx_logs->os_tx_m2u_entry, - tx_logs->os_tx_m2u_entry_err_xmit, - tx_logs->os_tx_m2u_entry_err_skb, - tx_logs->os_tx_m2u_stop, - tx_logs->core_tx, - tx_logs->core_tx_err_pxmitframe, - tx_logs->core_tx_err_brtx, - tx_logs->core_tx_upd_attrib, - tx_logs->core_tx_upd_attrib_adhoc, - tx_logs->core_tx_upd_attrib_sta, - tx_logs->core_tx_upd_attrib_ap, - tx_logs->core_tx_upd_attrib_unknown, - tx_logs->core_tx_upd_attrib_dhcp, - tx_logs->core_tx_upd_attrib_icmp, - tx_logs->core_tx_upd_attrib_active, - tx_logs->core_tx_upd_attrib_err_ucast_sta, - tx_logs->core_tx_upd_attrib_err_ucast_ap_link, - tx_logs->core_tx_upd_attrib_err_sta, - tx_logs->core_tx_upd_attrib_err_link, - tx_logs->core_tx_upd_attrib_err_sec, - tx_logs->core_tx_ap_enqueue_warn_fwstate, - tx_logs->core_tx_ap_enqueue_warn_sta, - tx_logs->core_tx_ap_enqueue_warn_nosta, - tx_logs->core_tx_ap_enqueue_warn_link, - tx_logs->core_tx_ap_enqueue_warn_trigger, - tx_logs->core_tx_ap_enqueue_mcast, - tx_logs->core_tx_ap_enqueue_ucast, - tx_logs->core_tx_ap_enqueue, - tx_logs->intf_tx, - tx_logs->intf_tx_pending_ac, - tx_logs->intf_tx_pending_fw_under_survey, - tx_logs->intf_tx_pending_fw_under_linking, - tx_logs->intf_tx_pending_xmitbuf, - tx_logs->intf_tx_enqueue, - tx_logs->core_tx_enqueue, - tx_logs->core_tx_enqueue_class, - tx_logs->core_tx_enqueue_class_err_sta, - tx_logs->core_tx_enqueue_class_err_nosta, - tx_logs->core_tx_enqueue_class_err_fwlink, - tx_logs->intf_tx_direct, - tx_logs->intf_tx_direct_err_coalesce, - tx_logs->intf_tx_dequeue, - tx_logs->intf_tx_dequeue_err_coalesce, - tx_logs->intf_tx_dump_xframe, - tx_logs->intf_tx_dump_xframe_err_txdesc, - tx_logs->intf_tx_dump_xframe_err_port - ); - - return 0; -} - -int proc_get_int_logs(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, - "all=%d\n" - "err=%d\n" - "tbdok=%d\n" - "tbder=%d\n" - "bcnderr=%d\n" - "bcndma=%d\n" - "bcndma_e=%d\n" - "rx=%d\n" - "rx_rdu=%d\n" - "rx_fovw=%d\n" - "txfovw=%d\n" - "mgntok=%d\n" - "highdok=%d\n" - "bkdok=%d\n" - "bedok=%d\n" - "vidok=%d\n" - "vodok=%d\n", - padapter->int_logs.all, - padapter->int_logs.err, - padapter->int_logs.tbdok, - padapter->int_logs.tbder, - padapter->int_logs.bcnderr, - padapter->int_logs.bcndma, - padapter->int_logs.bcndma_e, - padapter->int_logs.rx, - padapter->int_logs.rx_rdu, - padapter->int_logs.rx_fovw, - padapter->int_logs.txfovw, - padapter->int_logs.mgntok, - padapter->int_logs.highdok, - padapter->int_logs.bkdok, - padapter->int_logs.bedok, - padapter->int_logs.vidok, - padapter->int_logs.vodok - ); - - return 0; -} - -#endif /* CONFIG_DBG_COUNTER */ - -int proc_get_hw_status(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = padapter->dvobj; - struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - struct registry_priv *regsty = dvobj_to_regsty(dvobj); - - if (regsty->check_hw_status == 0) - RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n"); - else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1 - && pdbgpriv->dbg_rx_fifo_curr_overflow == 1 - && pdbgpriv->dbg_rx_fifo_diff_overflow == 1 - ) - RTW_PRINT_SEL(m, "RX FIFO full count: no implementation\n"); - else { - RTW_PRINT_SEL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n" - , pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow); - } - - return 0; -} - -ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = padapter->dvobj; - struct registry_priv *regsty = dvobj_to_regsty(dvobj); - char tmp[32]; - u32 enable; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &enable); - - if (num == 1 && regsty && enable <= 1) { - regsty->check_hw_status = enable; - RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status); - } - } - - return count; -} - -#ifdef CONFIG_HUAWEI_PROC -int proc_get_huawei_trx_info(struct seq_file *sel, void *v) -{ - struct net_device *dev = sel->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dm_struct *dm = adapter_to_phydm(padapter); - struct sta_info *psta; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct ra_sta_info *ra_info; - u8 curr_tx_sgi = _FALSE; - u8 curr_tx_rate = 0; - u8 mac_id; -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - u8 isCCKrate, rf_path; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); - struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; -#endif - - if (!dm->is_linked) { - RTW_PRINT_SEL(sel, "NO link\n\n"); - return 0; - } - - /*============ tx info ============ */ - for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) { - if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) { - psta = macid_ctl->sta[mac_id]; - if (!psta) - continue; - - RTW_PRINT_SEL(sel, "STA [" MAC_FMT "]\n", MAC_ARG(psta->cmn.mac_addr)); - - ra_info = &psta->cmn.ra_info; - curr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta); - curr_tx_rate = rtw_get_current_tx_rate(padapter, psta); - RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n", - HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L"); - RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw)); - } - } - - /*============ rx info ============ */ - RTW_PRINT_SEL(sel, "rx_rate : %s\n", HDATA_RATE(dm->rx_rate)); -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE; - - for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) { - if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path))) - continue; - if (!isCCKrate) - _RTW_PRINT_SEL(sel , "RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n", - rf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]); - } -#endif - RTW_PRINT_SEL(sel, "\n"); - return 0; -} -#endif /* CONFIG_HUAWEI_PROC */ - -int proc_get_trx_info_debug(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - /*============ tx info ============ */ - rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m); - - /*============ rx info ============ */ - rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE); - - return 0; -} - -int proc_get_rx_signal(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvpriv.rssi); -#ifdef CONFIG_MP_INCLUDED - if (padapter->registrypriv.mp_mode == 1) { - struct dm_struct *odm = adapter_to_phydm(padapter); - if (padapter->mppriv.antenna_rx == ANTENNA_A) - RTW_PRINT_SEL(m, "Antenna: A\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_B) - RTW_PRINT_SEL(m, "Antenna: B\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_C) - RTW_PRINT_SEL(m, "Antenna: C\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_D) - RTW_PRINT_SEL(m, "Antenna: D\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_AB) - RTW_PRINT_SEL(m, "Antenna: AB\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_BC) - RTW_PRINT_SEL(m, "Antenna: BC\n"); - else if (padapter->mppriv.antenna_rx == ANTENNA_CD) - RTW_PRINT_SEL(m, "Antenna: CD\n"); - else - RTW_PRINT_SEL(m, "Antenna: __\n"); - - RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate)); - return 0; - } else -#endif - { - /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */ - RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); - RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); - } -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - rtw_odm_get_perpkt_rssi(m, padapter); - rtw_get_raw_rssi_info(m, padapter); -#endif - return 0; -} - -ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u32 is_signal_dbg, signal_strength; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); - - if (num < 1) - return count; - - is_signal_dbg = is_signal_dbg == 0 ? 0 : 1; - - if (is_signal_dbg && num < 2) - return count; - - signal_strength = signal_strength > 100 ? 100 : signal_strength; - - padapter->recvpriv.is_signal_dbg = is_signal_dbg; - padapter->recvpriv.signal_strength_dbg = signal_strength; - - if (is_signal_dbg) - RTW_INFO("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength); - else - RTW_INFO("set %s\n", "HW_SIGNAL_STRENGTH"); - - } - - return count; - -} - -int proc_get_mac_rptbuf(struct seq_file *m, void *v) -{ -#ifdef CONFIG_RTL8814A - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u16 i; - u16 mac_id; - u32 shcut_addr = 0; - u32 read_addr = 0; - - RTW_PRINT_SEL(m, "TX ShortCut:\n"); - for (mac_id = 0; mac_id < 64; mac_id++) { - rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5)); - shcut_addr = 0x8000; - shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7); - RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5)); - for (i = 0; i < 30; i++) { - read_addr = 0; - read_addr = shcut_addr | (i << 2); - RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr)); - if (!((i + 1) % 4)) - RTW_PRINT_SEL(m, "\n"); - if (i == 29) - RTW_PRINT_SEL(m, "\n"); - } - } -#endif /* CONFIG_RTL8814A */ - return 0; -} - -#ifdef CONFIG_80211N_HT - -int proc_get_ht_enable(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (pregpriv) - RTW_PRINT_SEL(m, "%d\n", pregpriv->ht_enable); - - return 0; -} - -ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - char tmp[32]; - u32 mode; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &mode); - - if ( num == 1 && pregpriv && mode < 2) { - pregpriv->ht_enable = mode; - RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable); - } - } - - return count; - -} - -int proc_get_bw_mode(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (pregpriv) - RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->bw_mode); - - return 0; -} - -ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - char tmp[32]; - u32 mode; - u8 bw_2g; - u8 bw_5g; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%x ", &mode); - bw_5g = mode >> 4; - bw_2g = mode & 0x0f; - - if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) { - pregpriv->bw_mode = mode; - printk("bw_mode=0x%x\n", mode); - } - } - - return count; - -} - -int proc_get_ampdu_enable(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (pregpriv) - RTW_PRINT_SEL(m, "%d\n", pregpriv->ampdu_enable); - - return 0; -} - -ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - char tmp[32]; - u32 mode; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &mode); - - if (num == 1 && pregpriv && mode < 2) { - pregpriv->ampdu_enable = mode; - printk("ampdu_enable=%d\n", mode); - } - - } - - return count; - -} - - -void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter) -{ - struct registry_priv *regsty = adapter_to_regsty(adapter); - int i; - - RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n" - , "", "20M", "40M", "80M", "160M"); - for (i = 0; i < 4; i++) - RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1 - , regsty->rx_ampdu_sz_limit_by_nss_bw[i][0] - , regsty->rx_ampdu_sz_limit_by_nss_bw[i][1] - , regsty->rx_ampdu_sz_limit_by_nss_bw[i][2] - , regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]); -} - -int proc_get_rx_ampdu(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - _RTW_PRINT_SEL(m, "accept: "); - if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID) - RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)"); - else - RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)"); - - _RTW_PRINT_SEL(m, "size: "); - if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) { - RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:"); - dump_regsty_rx_ampdu_size_limit(m, padapter); - } else - RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)"); - RTW_PRINT_SEL(m, "\n"); - - RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size"); - - _RTW_PRINT_SEL(m, "%-19d %-17u\n" - , padapter->fix_rx_ampdu_accept - , padapter->fix_rx_ampdu_size); - - return 0; -} - -ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 accept; - u8 size; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu %hhu", &accept, &size); - - if (num >= 1) - rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED); - if (num >= 2) - rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED); - - rtw_rx_ampdu_apply(padapter); - } - - return count; -} -#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT -int proc_get_tx_aval_th(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - - if (padapter) { + RTW_PRINT_SEL(m, + "intf_rx=%d\n" + "intf_rx_err_recvframe=%d\n" + "intf_rx_err_skb=%d\n" + "intf_rx_report=%d\n" + "core_rx=%d\n" + "core_rx_pre=%d\n" + "core_rx_pre_ver_err=%d\n" + "core_rx_pre_mgmt=%d\n" + "core_rx_pre_mgmt_err_80211w=%d\n" + "core_rx_pre_mgmt_err=%d\n" + "core_rx_pre_ctrl=%d\n" + "core_rx_pre_ctrl_err=%d\n" + "core_rx_pre_data=%d\n" + "core_rx_pre_data_wapi_seq_err=%d\n" + "core_rx_pre_data_wapi_key_err=%d\n" + "core_rx_pre_data_handled=%d\n" + "core_rx_pre_data_err=%d\n" + "core_rx_pre_data_unknown=%d\n" + "core_rx_pre_unknown=%d\n" + "core_rx_enqueue=%d\n" + "core_rx_dequeue=%d\n" + "core_rx_post=%d\n" + "core_rx_post_decrypt=%d\n" + "core_rx_post_decrypt_wep=%d\n" + "core_rx_post_decrypt_tkip=%d\n" + "core_rx_post_decrypt_aes=%d\n" + "core_rx_post_decrypt_wapi=%d\n" + "core_rx_post_decrypt_hw=%d\n" + "core_rx_post_decrypt_unknown=%d\n" + "core_rx_post_decrypt_err=%d\n" + "core_rx_post_defrag_err=%d\n" + "core_rx_post_portctrl_err=%d\n" + "core_rx_post_indicate=%d\n" + "core_rx_post_indicate_in_oder=%d\n" + "core_rx_post_indicate_reoder=%d\n" + "core_rx_post_indicate_err=%d\n" + "os_indicate=%d\n" + "os_indicate_ap_mcast=%d\n" + "os_indicate_ap_forward=%d\n" + "os_indicate_ap_self=%d\n" + "os_indicate_err=%d\n" + "os_netif_ok=%d\n" + "os_netif_err=%d\n", + rx_logs->intf_rx, + rx_logs->intf_rx_err_recvframe, + rx_logs->intf_rx_err_skb, + rx_logs->intf_rx_report, + rx_logs->core_rx, + rx_logs->core_rx_pre, + rx_logs->core_rx_pre_ver_err, + rx_logs->core_rx_pre_mgmt, + rx_logs->core_rx_pre_mgmt_err_80211w, + rx_logs->core_rx_pre_mgmt_err, + rx_logs->core_rx_pre_ctrl, + rx_logs->core_rx_pre_ctrl_err, + rx_logs->core_rx_pre_data, + rx_logs->core_rx_pre_data_wapi_seq_err, + rx_logs->core_rx_pre_data_wapi_key_err, + rx_logs->core_rx_pre_data_handled, + rx_logs->core_rx_pre_data_err, + rx_logs->core_rx_pre_data_unknown, + rx_logs->core_rx_pre_unknown, + rx_logs->core_rx_enqueue, + rx_logs->core_rx_dequeue, + rx_logs->core_rx_post, + rx_logs->core_rx_post_decrypt, + rx_logs->core_rx_post_decrypt_wep, + rx_logs->core_rx_post_decrypt_tkip, + rx_logs->core_rx_post_decrypt_aes, + rx_logs->core_rx_post_decrypt_wapi, + rx_logs->core_rx_post_decrypt_hw, + rx_logs->core_rx_post_decrypt_unknown, + rx_logs->core_rx_post_decrypt_err, + rx_logs->core_rx_post_defrag_err, + rx_logs->core_rx_post_portctrl_err, + rx_logs->core_rx_post_indicate, + rx_logs->core_rx_post_indicate_in_oder, + rx_logs->core_rx_post_indicate_reoder, + rx_logs->core_rx_post_indicate_err, + rx_logs->os_indicate, + rx_logs->os_indicate_ap_mcast, + rx_logs->os_indicate_ap_forward, + rx_logs->os_indicate_ap_self, + rx_logs->os_indicate_err, + rx_logs->os_netif_ok, + rx_logs->os_netif_err + ); - switch(dvobj->tx_aval_int_thr_mode) { - case 0: - RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (auto) \n", dvobj->tx_aval_int_thr_mode); - break; - case 1: - RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (fixed)\n", dvobj->tx_aval_int_thr_mode); - RTW_PRINT_SEL(m, "tx_aval_threshold = 0x%x\n", dvobj->tx_aval_int_thr_value); - break; - case 2: - RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u(by sdio_tx_max_len)\n", dvobj->tx_aval_int_thr_mode); - break; - default: - break; - } - } return 0; } -ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer - , size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - char tmp[32]; - u32 mode; - u32 threshold; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d %d ",&mode, &threshold); - - if(num >= 1) - dvobj->tx_aval_int_thr_mode = mode; - if(num >= 2) - dvobj->tx_aval_int_thr_value = threshold; - RTW_INFO("dvobj->tx_aval_int_thr_mode= 0x%x\n", mode); - RTW_INFO("dvobj->tx_aval_int_thr_value= 0x%x(range need 1~255)\n", threshold); - } - - return count; -} -#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/ - -int proc_get_rx_ampdu_factor(struct seq_file *m, void *v) +int proc_get_tx_logs(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tx_logs *tx_logs = &padapter->tx_logs; + RTW_PRINT_SEL(m, + "os_tx=%d\n" + "os_tx_err_up=%d\n" + "os_tx_err_xmit=%d\n" + "os_tx_m2u=%d\n" + "os_tx_m2u_ignore_fw_linked=%d\n" + "os_tx_m2u_ignore_self=%d\n" + "os_tx_m2u_entry=%d\n" + "os_tx_m2u_entry_err_xmit=%d\n" + "os_tx_m2u_entry_err_skb=%d\n" + "os_tx_m2u_stop=%d\n" + "core_tx=%d\n" + "core_tx_err_pxmitframe=%d\n" + "core_tx_err_brtx=%d\n" + "core_tx_upd_attrib=%d\n" + "core_tx_upd_attrib_adhoc=%d\n" + "core_tx_upd_attrib_sta=%d\n" + "core_tx_upd_attrib_ap=%d\n" + "core_tx_upd_attrib_unknown=%d\n" + "core_tx_upd_attrib_dhcp=%d\n" + "core_tx_upd_attrib_icmp=%d\n" + "core_tx_upd_attrib_active=%d\n" + "core_tx_upd_attrib_err_ucast_sta=%d\n" + "core_tx_upd_attrib_err_ucast_ap_link=%d\n" + "core_tx_upd_attrib_err_sta=%d\n" + "core_tx_upd_attrib_err_link=%d\n" + "core_tx_upd_attrib_err_sec=%d\n" + "core_tx_ap_enqueue_warn_fwstate=%d\n" + "core_tx_ap_enqueue_warn_sta=%d\n" + "core_tx_ap_enqueue_warn_nosta=%d\n" + "core_tx_ap_enqueue_warn_link=%d\n" + "core_tx_ap_enqueue_warn_trigger=%d\n" + "core_tx_ap_enqueue_mcast=%d\n" + "core_tx_ap_enqueue_ucast=%d\n" + "core_tx_ap_enqueue=%d\n" + "intf_tx=%d\n" + "intf_tx_pending_ac=%d\n" + "intf_tx_pending_fw_under_survey=%d\n" + "intf_tx_pending_fw_under_linking=%d\n" + "intf_tx_pending_xmitbuf=%d\n" + "intf_tx_enqueue=%d\n" + "core_tx_enqueue=%d\n" + "core_tx_enqueue_class=%d\n" + "core_tx_enqueue_class_err_sta=%d\n" + "core_tx_enqueue_class_err_nosta=%d\n" + "core_tx_enqueue_class_err_fwlink=%d\n" + "intf_tx_direct=%d\n" + "intf_tx_direct_err_coalesce=%d\n" + "intf_tx_dequeue=%d\n" + "intf_tx_dequeue_err_coalesce=%d\n" + "intf_tx_dump_xframe=%d\n" + "intf_tx_dump_xframe_err_txdesc=%d\n" + "intf_tx_dump_xframe_err_port=%d\n", + tx_logs->os_tx, + tx_logs->os_tx_err_up, + tx_logs->os_tx_err_xmit, + tx_logs->os_tx_m2u, + tx_logs->os_tx_m2u_ignore_fw_linked, + tx_logs->os_tx_m2u_ignore_self, + tx_logs->os_tx_m2u_entry, + tx_logs->os_tx_m2u_entry_err_xmit, + tx_logs->os_tx_m2u_entry_err_skb, + tx_logs->os_tx_m2u_stop, + tx_logs->core_tx, + tx_logs->core_tx_err_pxmitframe, + tx_logs->core_tx_err_brtx, + tx_logs->core_tx_upd_attrib, + tx_logs->core_tx_upd_attrib_adhoc, + tx_logs->core_tx_upd_attrib_sta, + tx_logs->core_tx_upd_attrib_ap, + tx_logs->core_tx_upd_attrib_unknown, + tx_logs->core_tx_upd_attrib_dhcp, + tx_logs->core_tx_upd_attrib_icmp, + tx_logs->core_tx_upd_attrib_active, + tx_logs->core_tx_upd_attrib_err_ucast_sta, + tx_logs->core_tx_upd_attrib_err_ucast_ap_link, + tx_logs->core_tx_upd_attrib_err_sta, + tx_logs->core_tx_upd_attrib_err_link, + tx_logs->core_tx_upd_attrib_err_sec, + tx_logs->core_tx_ap_enqueue_warn_fwstate, + tx_logs->core_tx_ap_enqueue_warn_sta, + tx_logs->core_tx_ap_enqueue_warn_nosta, + tx_logs->core_tx_ap_enqueue_warn_link, + tx_logs->core_tx_ap_enqueue_warn_trigger, + tx_logs->core_tx_ap_enqueue_mcast, + tx_logs->core_tx_ap_enqueue_ucast, + tx_logs->core_tx_ap_enqueue, + tx_logs->intf_tx, + tx_logs->intf_tx_pending_ac, + tx_logs->intf_tx_pending_fw_under_survey, + tx_logs->intf_tx_pending_fw_under_linking, + tx_logs->intf_tx_pending_xmitbuf, + tx_logs->intf_tx_enqueue, + tx_logs->core_tx_enqueue, + tx_logs->core_tx_enqueue_class, + tx_logs->core_tx_enqueue_class_err_sta, + tx_logs->core_tx_enqueue_class_err_nosta, + tx_logs->core_tx_enqueue_class_err_fwlink, + tx_logs->intf_tx_direct, + tx_logs->intf_tx_direct_err_coalesce, + tx_logs->intf_tx_dequeue, + tx_logs->intf_tx_dequeue_err_coalesce, + tx_logs->intf_tx_dump_xframe, + tx_logs->intf_tx_dump_xframe_err_txdesc, + tx_logs->intf_tx_dump_xframe_err_port + ); - if (padapter) - RTW_PRINT_SEL(m, "rx ampdu factor = %x\n", padapter->driver_rx_ampdu_factor); - - return 0; -} - -ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer - , size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u32 factor; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &factor); - - if (padapter && (num == 1)) { - RTW_INFO("padapter->driver_rx_ampdu_factor = %x\n", factor); - - if (factor > 0x03) - padapter->driver_rx_ampdu_factor = 0xFF; - else - padapter->driver_rx_ampdu_factor = factor; - } - } - - return count; + return 0; } -int proc_get_tx_max_agg_num(struct seq_file *m, void *v) +int proc_get_int_logs(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - if (padapter) - RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num); + RTW_PRINT_SEL(m, + "all=%d\n" + "err=%d\n" + "tbdok=%d\n" + "tbder=%d\n" + "bcnderr=%d\n" + "bcndma=%d\n" + "bcndma_e=%d\n" + "rx=%d\n" + "rx_rdu=%d\n" + "rx_fovw=%d\n" + "txfovw=%d\n" + "mgntok=%d\n" + "highdok=%d\n" + "bkdok=%d\n" + "bedok=%d\n" + "vidok=%d\n" + "vodok=%d\n", + padapter->int_logs.all, + padapter->int_logs.err, + padapter->int_logs.tbdok, + padapter->int_logs.tbder, + padapter->int_logs.bcnderr, + padapter->int_logs.bcndma, + padapter->int_logs.bcndma_e, + padapter->int_logs.rx, + padapter->int_logs.rx_rdu, + padapter->int_logs.rx_fovw, + padapter->int_logs.txfovw, + padapter->int_logs.mgntok, + padapter->int_logs.highdok, + padapter->int_logs.bkdok, + padapter->int_logs.bedok, + padapter->int_logs.vidok, + padapter->int_logs.vodok + ); return 0; } -ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer - , size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 agg_num; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx ", &agg_num); - - if (padapter && (num == 1)) { - RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num); - - padapter->driver_tx_max_agg_num = agg_num; - } - } - - return count; -} +#endif /* CONFIG_DBG_COUNTER */ -int proc_get_rx_ampdu_density(struct seq_file *m, void *v) +int proc_get_hw_status(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); - - if (padapter) - RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing); + if (regsty->check_hw_status == 0) + RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n"); + else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1 + && pdbgpriv->dbg_rx_fifo_curr_overflow == 1 + && pdbgpriv->dbg_rx_fifo_diff_overflow == 1 + ) + RTW_PRINT_SEL(m, "RX FIFO full count: no implementation\n"); + else { + RTW_PRINT_SEL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n" + , pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow); + } return 0; } -ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = padapter->dvobj; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); char tmp[32]; - u32 density; + u32 enable; if (count < 1) return -EFAULT; @@ -4001,84 +2682,76 @@ ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &density); - - if (padapter && (num == 1)) { - RTW_INFO("padapter->driver_rx_ampdu_spacing = %x\n", density); + int num = sscanf(tmp, "%d ", &enable); - if (density > 0x07) - padapter->driver_rx_ampdu_spacing = 0xFF; - else - padapter->driver_rx_ampdu_spacing = density; + if (num == 1 && regsty && enable <= 1) { + regsty->check_hw_status = enable; + RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status); } } return count; } -int proc_get_tx_ampdu_density(struct seq_file *m, void *v) +int proc_get_trx_info_debug(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + /*============ tx info ============ */ + rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m); - if (padapter) - RTW_PRINT_SEL(m, "tx ampdu density = %x\n", padapter->driver_ampdu_spacing); + /*============ rx info ============ */ + /*rtw_hal_set_phydm_var(padapter, HAL_PHYDM_RX_INFO_DUMP, m, _FALSE);*/ return 0; } -ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_rx_signal(struct seq_file *m, void *v) { - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u32 density; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &density); - if (padapter && (num == 1)) { - RTW_INFO("padapter->driver_ampdu_spacing = %x\n", density); + RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvinfo.rssi); +#if 0//def CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) { + struct dm_struct *odm = adapter_to_phydm(padapter); + if (padapter->mppriv.antenna_rx == ANTENNA_A) + RTW_PRINT_SEL(m, "Antenna: A\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_B) + RTW_PRINT_SEL(m, "Antenna: B\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_C) + RTW_PRINT_SEL(m, "Antenna: C\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_D) + RTW_PRINT_SEL(m, "Antenna: D\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_AB) + RTW_PRINT_SEL(m, "Antenna: AB\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_BC) + RTW_PRINT_SEL(m, "Antenna: BC\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_CD) + RTW_PRINT_SEL(m, "Antenna: CD\n"); + else + RTW_PRINT_SEL(m, "Antenna: __\n"); - if (density > 0x07) - padapter->driver_ampdu_spacing = 0xFF; - else - padapter->driver_ampdu_spacing = density; - } + RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate)); + return 0; + } else +#endif + { + /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvinfo.rxpwdb); */ + RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvinfo.signal_strength); + RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvinfo.signal_qual); } - return count; -} - -int proc_get_tx_quick_addba_req(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (padapter) - RTW_PRINT_SEL(m, "tx_quick_addba_req = %x\n", pregpriv->tx_quick_addba_req); - return 0; } -ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 enable; + u32 is_signal_dbg, signal_strength; if (count < 1) return -EFAULT; @@ -4090,92 +2763,58 @@ ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &enable); + int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); - if (padapter && (num == 1)) { - pregpriv->tx_quick_addba_req = enable; - RTW_INFO("tx_quick_addba_req = %d\n", pregpriv->tx_quick_addba_req); - } - } + if (num < 1) + return count; - return count; -} -#ifdef CONFIG_TX_AMSDU -int proc_get_tx_amsdu(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + is_signal_dbg = is_signal_dbg == 0 ? 0 : 1; - if (padapter) - { - RTW_PRINT_SEL(m, "tx amsdu = %d\n", padapter->tx_amsdu); - RTW_PRINT_SEL(m, "amsdu set timer conut = %u\n", pxmitpriv->amsdu_debug_set_timer); - RTW_PRINT_SEL(m, "amsdu time out count = %u\n", pxmitpriv->amsdu_debug_timeout); - RTW_PRINT_SEL(m, "amsdu coalesce one count = %u\n", pxmitpriv->amsdu_debug_coalesce_one); - RTW_PRINT_SEL(m, "amsdu coalesce two count = %u\n", pxmitpriv->amsdu_debug_coalesce_two); - } + if (is_signal_dbg && num < 2) + return count; - return 0; -} + signal_strength = signal_strength > PHL_MAX_RSSI ? PHL_MAX_RSSI : signal_strength; -ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - char tmp[32]; - u32 amsdu; + padapter->recvinfo.is_signal_dbg = is_signal_dbg; + padapter->recvinfo.signal_strength_dbg = signal_strength; - if (count < 1) - return -EFAULT; + if (is_signal_dbg) + RTW_INFO("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength); + else + RTW_INFO("set %s\n", "HW_SIGNAL_STRENGTH"); - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d ", &amsdu); - - if (padapter && (num == 1)) { - RTW_INFO("padapter->tx_amsdu = %x\n", amsdu); + return count; - if (amsdu > 3) - padapter->tx_amsdu = 0; - else if(amsdu == 3) - { - pxmitpriv->amsdu_debug_set_timer = 0; - pxmitpriv->amsdu_debug_timeout = 0; - pxmitpriv->amsdu_debug_coalesce_one = 0; - pxmitpriv->amsdu_debug_coalesce_two = 0; - } - else - padapter->tx_amsdu = amsdu; - } - } +} - return count; +int proc_get_mac_rptbuf(struct seq_file *m, void *v) +{ + return 0; } -int proc_get_tx_amsdu_rate(struct seq_file *m, void *v) +#ifdef CONFIG_80211N_HT + +int proc_get_ht_enable(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - if (padapter) - RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate); + if (pregpriv) + RTW_PRINT_SEL(m, "%d\n", pregpriv->ht_enable); return 0; } -ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 amsdu_rate; + u32 mode; if (count < 1) return -EFAULT; @@ -4187,39 +2826,39 @@ ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, siz if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &amsdu_rate); + int num = sscanf(tmp, "%d ", &mode); - if (padapter && (num == 1)) { - RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate); - padapter->tx_amsdu_rate = amsdu_rate; + if ( num == 1 && pregpriv && mode < 2) { + pregpriv->ht_enable = mode; + RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable); } } return count; + } -#endif /* CONFIG_TX_AMSDU */ -#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT -int proc_get_vht_24g_enable(struct seq_file *m, void *v) +int proc_get_bw_mode(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; if (pregpriv) - RTW_PRINT_SEL(m, "%d\n", pregpriv->vht_24g_enable); + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->bw_mode); return 0; } -ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; u32 mode; + u8 bw_2g; + u8 bw_5g; if (count < 1) return -EFAULT; @@ -4231,78 +2870,33 @@ ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, si if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%x ", &mode); + bw_5g = mode >> 4; + bw_2g = mode & 0x0f; - if ((num == 1) && pregpriv && (mode < 2)) { - pregpriv->vht_24g_enable = mode; - RTW_INFO("vht_24g_enable = %d\n", pregpriv->vht_24g_enable); + if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) { + pregpriv->bw_mode = mode; + printk("bw_mode=0x%x\n", mode); } } return count; } -#endif - -ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - char tmp[32] = {0}; - u32 num = 0, enable = 0, rrsr_val = 0; /* gpio_mode:0 input 1:output; */ - - if (count < 2) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%d 0x%x", &enable, &rrsr_val); - RTW_INFO("num=%u enable=%d rrsr_val=0x%x\n", num, enable, rrsr_val); - pregpriv->en_dyn_rrsr = enable; - pregpriv->set_rrsr_value = rrsr_val; - rtw_phydm_dyn_rrsr_en(padapter, enable); - rtw_phydm_set_rrsr(padapter, rrsr_val, TRUE); - - } - return count; - -} -int proc_get_dyn_rrsr(struct seq_file *m, void *v) { - - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - u32 init_rrsr =0xFFFFFFFF; - - if (padapter) - RTW_PRINT_SEL(m, "en_dyn_rrsr = %d fixed_rrsr_value =0x%x %s\n" - , pregpriv->en_dyn_rrsr - , pregpriv->set_rrsr_value - , (pregpriv->set_rrsr_value == init_rrsr)?"(default)":"(fixed)" - ); - return 0; -} -int proc_get_en_fwps(struct seq_file *m, void *v) +int proc_get_ampdu_enable(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; if (pregpriv) - RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n" - , pregpriv->check_fw_ps); + RTW_PRINT_SEL(m, "%d\n", pregpriv->ampdu_enable); return 0; } -ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4322,150 +2916,111 @@ ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t co int num = sscanf(tmp, "%d ", &mode); - if (num == 1 && pregpriv && mode < 2) { - pregpriv->check_fw_ps = mode; - RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps); + if (num == 1 && pregpriv && mode < 2) { + pregpriv->ampdu_enable = mode; + printk("ampdu_enable=%d\n", mode); } } return count; + +} + + +void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + int i; + + RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n" + , "", "20M", "40M", "80M", "160M"); + for (i = 0; i < 4; i++) + RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1 + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][0] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][1] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][2] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]); } -/* -int proc_get_two_path_rssi(struct seq_file *m, void *v) +int proc_get_rx_ampdu(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - if(padapter) - RTW_PRINT_SEL(m, "%d %d\n", - padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]); + _RTW_PRINT_SEL(m, "accept: "); + if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID) + RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)"); + else + RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)"); - return 0; -} -*/ -#ifdef CONFIG_80211N_HT -void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter) -{ - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct ht_priv *phtpriv = &pmlmepriv->htpriv; - #ifdef CONFIG_80211AC_VHT - struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - #endif + _RTW_PRINT_SEL(m, "size: "); + if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) { + RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:"); + dump_regsty_rx_ampdu_size_limit(m, padapter); + } else + RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)"); + RTW_PRINT_SEL(m, "\n"); - #ifdef CONFIG_80211AC_VHT - RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X"); - #endif - RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X"); + RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size"); - #ifdef CONFIG_80211AC_VHT - RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X"); - #endif - RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X"); + _RTW_PRINT_SEL(m, "%-19d %-17u\n" + , padapter->fix_rx_ampdu_accept + , padapter->fix_rx_ampdu_size); - #ifdef CONFIG_BEAMFORMING - #ifdef CONFIG_80211AC_VHT - RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X"); - #endif - RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X"); - #endif + return 0; } -void rtw_get_dft_phy_cap(void *sel, _adapter *adapter) +ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n"); - rtw_ht_use_default_setting(adapter); - #ifdef CONFIG_80211AC_VHT - rtw_vht_use_default_setting(adapter); - #endif - #ifdef CONFIG_80211N_HT - rtw_dump_dft_phy_cap(sel, adapter); - #endif -} + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 accept; + u8 size; -void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) -{ - struct registry_priv *pregistry_priv = &adapter->registrypriv; + if (count < 1) + return -EFAULT; - RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n"); - #if 0 - RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap); - RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/ - #endif - #ifdef CONFIG_80211N_HT - RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/ + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } - RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/ - #endif /* CONFIG_80211N_HT */ - #ifdef CONFIG_BEAMFORMING - #if 0 - RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/ - RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/ - #endif + if (buffer && !copy_from_user(tmp, buffer, count)) { - /* - * BIT0: Enable VHT SU Beamformer - * BIT1: Enable VHT SU Beamformee - * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer - * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee - * BIT4: Enable HT Beamformer - * BIT5: Enable HT Beamformee - */ - RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4)) ? "V" : "X"); - RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X"); + int num = sscanf(tmp, "%hhu %hhu", &accept, &size); - RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num); - RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num); - #endif + if (num >= 1) + rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED); + if (num >= 2) + rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED); + + rtw_rx_ampdu_apply(padapter); + } + + return count; } -int proc_get_stbc_cap(struct seq_file *m, void *v) +int proc_get_rx_ampdu_factor(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - if (pregpriv) - RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap); + + if (padapter) + RTW_PRINT_SEL(m, "rx ampdu factor = %x\n", padapter->driver_rx_ampdu_factor); return 0; } -ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer + , size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 mode; + u32 factor; if (count < 1) return -EFAULT; @@ -4477,35 +3032,40 @@ ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t c if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%d ", &factor); - if (num == 1 && pregpriv) { - pregpriv->stbc_cap = mode; - RTW_INFO("stbc_cap = 0x%02x\n", mode); + if (padapter && (num == 1)) { + RTW_INFO("padapter->driver_rx_ampdu_factor = %x\n", factor); + + if (factor > 0x03) + padapter->driver_rx_ampdu_factor = 0xFF; + else + padapter->driver_rx_ampdu_factor = factor; } } return count; } -int proc_get_rx_stbc(struct seq_file *m, void *v) + +int proc_get_tx_max_agg_num(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - if (pregpriv) - RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc); + + if (padapter) + RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num); return 0; } -ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer + , size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 mode; + u8 agg_num; if (count < 1) return -EFAULT; @@ -4517,36 +3077,36 @@ ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t co if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%hhx ", &agg_num); + + if (padapter && (num == 1)) { + RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num); - if (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) { - pregpriv->rx_stbc = mode; - printk("rx_stbc=%d\n", mode); + padapter->driver_tx_max_agg_num = agg_num; } } return count; - } -int proc_get_ldpc_cap(struct seq_file *m, void *v) + +int proc_get_rx_ampdu_density(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - if (pregpriv) - RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap); + + if (padapter) + RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing); return 0; } -ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 mode; + u32 density; if (count < 1) return -EFAULT; @@ -4558,36 +3118,39 @@ ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t c if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%d ", &density); - if (num == 1 && pregpriv) { - pregpriv->ldpc_cap = mode; - RTW_INFO("ldpc_cap = 0x%02x\n", mode); + if (padapter && (num == 1)) { + RTW_INFO("padapter->driver_rx_ampdu_spacing = %x\n", density); + + if (density > 0x07) + padapter->driver_rx_ampdu_spacing = 0xFF; + else + padapter->driver_rx_ampdu_spacing = density; } } return count; } -#ifdef CONFIG_BEAMFORMING -int proc_get_txbf_cap(struct seq_file *m, void *v) + +int proc_get_tx_ampdu_density(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - if (pregpriv) - RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap); + + if (padapter) + RTW_PRINT_SEL(m, "tx ampdu density = %x\n", padapter->driver_ampdu_spacing); return 0; } -ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 mode; + u32 density; if (count < 1) return -EFAULT; @@ -4599,38 +3162,43 @@ ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t c if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%d ", &density); - if (num == 1 && pregpriv) { - pregpriv->beamform_cap = mode; - RTW_INFO("beamform_cap = 0x%02x\n", mode); + if (padapter && (num == 1)) { + RTW_INFO("padapter->driver_ampdu_spacing = %x\n", density); + + if (density > 0x07) + padapter->driver_ampdu_spacing = 0xFF; + else + padapter->driver_ampdu_spacing = density; } } return count; } -#endif -#endif /* CONFIG_80211N_HT */ -/*int proc_get_rssi_disp(struct seq_file *m, void *v) +int proc_get_tx_quick_addba_req(struct seq_file *m, void *v) { struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (padapter) + RTW_PRINT_SEL(m, "tx_quick_addba_req = %x\n", pregpriv->tx_quick_addba_req); + return 0; } -*/ -/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u32 enable=0; + u32 enable; if (count < 1) - { - RTW_INFO("argument size is less than 1\n"); return -EFAULT; - } if (count > sizeof(tmp)) { rtw_warn_on(1); @@ -4639,254 +3207,100 @@ ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t c if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%x", &enable); - - if (num != 1) { - RTW_INFO("invalid set_rssi_disp parameter!\n"); - return count; - } + int num = sscanf(tmp, "%d ", &enable); - if(enable) - { - RTW_INFO("Linked info Function Enable\n"); - padapter->bLinkInfoDump = enable ; - } - else - { - RTW_INFO("Linked info Function Disable\n"); - padapter->bLinkInfoDump = 0 ; + if (padapter && (num == 1)) { + pregpriv->tx_quick_addba_req = enable; + RTW_INFO("tx_quick_addba_req = %d\n", pregpriv->tx_quick_addba_req); } - } return count; - } - -*/ -#ifdef CONFIG_AP_MODE - -int proc_get_all_sta_info(struct seq_file *m, void *v) +#ifdef CONFIG_TX_AMSDU +int proc_get_tx_amsdu(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _irqL irqL; - struct sta_info *psta; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; int i; - _list *plist, *phead; - - RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); - RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); - - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - - for (i = 0; i < NUM_STA; i++) { - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); - - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - - plist = get_next(plist); - - /* if(extra_arg == psta->cmn.aid) */ - { - RTW_PRINT_SEL(m, "==============================\n"); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", - psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); -#ifdef CONFIG_RTS_FULL_BW - if(psta->vendor_8812) - RTW_PRINT_SEL(m,"Vendor Realtek 8812\n"); -#endif/*CONFIG_RTS_FULL_BW*/ -#ifdef CONFIG_80211N_HT - RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d, ht_bitrate=%u\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate - , rtw_desc_rate_to_bitrate(psta->cmn.bw_mode, psta->init_rate, psta->cmn.bw_mode ? psta->htpriv.sgi_40m : psta->htpriv.sgi_20m) / 10); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" - , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); - RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); - RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable); - RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); -#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT - RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d, vht_bitrate=%u\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m - , psta->vhtpriv.vht_option ? rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, psta->vhtpriv.sgi_80m, psta->vhtpriv.vht_highest_rate) / 2 : 0); - RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); - RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); -#endif - RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len); - RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt); - RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt); - RTW_PRINT_SEL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt); - RTW_PRINT_SEL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt); - -#ifdef CONFIG_RTW_MGMT_QUEUE - RTW_PRINT_SEL(m, "management sleepq_len=%d\n", psta->mgmt_sleepq_len); - RTW_PRINT_SEL(m, "sta_xmitpriv.mgmt_q_qcnt=%d\n", psta->sta_xmitpriv.mgmt_q.qcnt); -#endif - - RTW_PRINT_SEL(m, "capability=0x%x\n", psta->capability); - RTW_PRINT_SEL(m, "flags=0x%x\n", psta->flags); - RTW_PRINT_SEL(m, "wpa_psk=0x%x\n", psta->wpa_psk); - RTW_PRINT_SEL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); - RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); - RTW_PRINT_SEL(m, "qos_info=0x%x\n", psta->qos_info); - RTW_PRINT_SEL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); - - sta_rx_reorder_ctl_dump(m, psta); - -#ifdef CONFIG_TDLS - RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state); - RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime); -#endif /* CONFIG_TDLS */ - RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta)); - RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts); - RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts); - RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta)); - RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes); - RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes); - if (psta->sta_stats.rx_tp_kbits >> 10) - RTW_PRINT_SEL(m, "rx_tp =%d (Mbps)\n", psta->sta_stats.rx_tp_kbits >> 10); - else - RTW_PRINT_SEL(m, "rx_tp =%d (Kbps)\n", psta->sta_stats.rx_tp_kbits); - - RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); - RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); - if (psta->sta_stats.tx_tp_kbits >> 10) - RTW_PRINT_SEL(m, "tx_tp =%d (Mbps)\n", psta->sta_stats.tx_tp_kbits >> 10); - else - RTW_PRINT_SEL(m, "tx_tp =%d (Kbps)\n", psta->sta_stats.tx_tp_kbits); -#ifdef CONFIG_RTW_80211K - RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap)); -#endif - dump_st_ctl(m, &psta->st_ctl); - - if (STA_OP_WFD_MODE(psta)) - RTW_PRINT_SEL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta)); - - RTW_PRINT_SEL(m, "tx_bitrate_100kbps=%u\n", rtw_desc_rate_to_bitrate(psta->cmn.bw_mode, rtw_get_current_tx_rate(padapter, psta), rtw_get_current_tx_sgi(padapter, psta))); - RTW_PRINT_SEL(m, "rx_bitrate_100kbps=%u\n", rtw_desc_rate_to_bitrate(psta->cmn.bw_mode, psta->curr_rx_rate & 0x7f, (psta->curr_rx_rate & 0x80) >> 7)); - RTW_PRINT_SEL(m, "rssi=%d\n", psta->cmn.rssi_stat.rssi); - RTW_PRINT_SEL(m, "==============================\n"); - } - - } - - } - - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - - return 0; -} -#endif - -#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER -int proc_get_rtkm_info(struct seq_file *m, void *v) -{ -#ifdef CONFIG_USB_HCI - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct recv_priv *precvpriv = &padapter->recvpriv; - struct recv_buf *precvbuf; - - precvbuf = (struct recv_buf *)precvpriv->precv_buf; -#endif /* CONFIG_USB_HCI */ - - RTW_PRINT_SEL(m, "============[RTKM Info]============\n"); - RTW_PRINT_SEL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb()); - RTW_PRINT_SEL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size()); - - RTW_PRINT_SEL(m, "============[Driver Info]============\n"); - RTW_PRINT_SEL(m, "NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB); -#ifdef CONFIG_USB_HCI - RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", precvbuf->alloc_sz); -#else /* !CONFIG_USB_HCI */ - RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", MAX_RECVBUF_SZ); -#endif /* !CONFIG_USB_HCI */ - - return 0; -} -#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ - -#ifdef DBG_MEMORY_LEAK -#include -extern atomic_t _malloc_cnt;; -extern atomic_t _malloc_size;; - -int proc_get_malloc_cnt(struct seq_file *m, void *v) -{ - RTW_PRINT_SEL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt)); - RTW_PRINT_SEL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size)); + if (padapter) + { + RTW_PRINT_SEL(m, "tx amsdu = %d\n", padapter->tx_amsdu); + RTW_PRINT_SEL(m, "amsdu set timer conut = %u\n", pxmitpriv->amsdu_debug_set_timer); + RTW_PRINT_SEL(m, "amsdu time out count = %u\n", pxmitpriv->amsdu_debug_timeout); + for (i = 0; i < (AMSDU_DEBUG_MAX_COUNT - 1); i++) { + RTW_PRINT_SEL(m, "amsdu coalesce %d count = %u\n", + i + 1, pxmitpriv->amsdu_debug_coalesce[i]); + } + RTW_PRINT_SEL(m, "amsdu coalesce >%d count = %u\n", + i, pxmitpriv->amsdu_debug_coalesce[i]); + RTW_PRINT_SEL(m, "amsdu tasklet count = %u\n", pxmitpriv->amsdu_debug_tasklet); + RTW_PRINT_SEL(m, "amsdu enqueue count = %u\n", pxmitpriv->amsdu_debug_enqueue); + RTW_PRINT_SEL(m, "amsdu dequeue count = %u\n", pxmitpriv->amsdu_debug_dequeue); + } return 0; } -#endif /* DBG_MEMORY_LEAK */ -#ifdef CONFIG_FIND_BEST_CHANNEL -int proc_get_best_channel(struct seq_file *m, void *v) +ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = m->private; + struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + char tmp[32]; + u32 i, amsdu; - for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { - if (rfctl->channel_set[i].ChannelNum == 1) - index_24G = i; - if (rfctl->channel_set[i].ChannelNum == 36) - index_5G = i; + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { - /* 2.4G */ - if (rfctl->channel_set[i].ChannelNum == 6) { - if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { - index_24G = i; - best_channel_24G = rfctl->channel_set[i].ChannelNum; - } - } + if (buffer && !copy_from_user(tmp, buffer, count)) { - /* 5G */ - if (rfctl->channel_set[i].ChannelNum >= 36 - && rfctl->channel_set[i].ChannelNum < 140) { - /* Find primary channel */ - if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) - && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { - index_5G = i; - best_channel_5G = rfctl->channel_set[i].ChannelNum; - } - } + int num = sscanf(tmp, "%d ", &amsdu); - if (rfctl->channel_set[i].ChannelNum >= 149 - && rfctl->channel_set[i].ChannelNum < 165) { - /* find primary channel */ - if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) - && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { - index_5G = i; - best_channel_5G = rfctl->channel_set[i].ChannelNum; + if (padapter && (num == 1)) { + RTW_INFO("padapter->tx_amsdu = %x\n", amsdu); + + if (amsdu == 255) { + pxmitpriv->amsdu_debug_set_timer = 0; + pxmitpriv->amsdu_debug_timeout = 0; + pxmitpriv->amsdu_debug_tasklet = 0; + pxmitpriv->amsdu_debug_enqueue = 0; + pxmitpriv->amsdu_debug_dequeue = 0; + for (i = 0; i < AMSDU_DEBUG_MAX_COUNT; i++) + pxmitpriv->amsdu_debug_coalesce[i] = 0; + } else { + padapter->tx_amsdu = amsdu; } } -#if 1 /* debug */ - RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n", - rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count); -#endif } - RTW_PRINT_SEL(m, "best_channel_5G = %d\n", best_channel_5G); - RTW_PRINT_SEL(m, "best_channel_24G = %d\n", best_channel_24G); + return count; +} + +int proc_get_tx_amsdu_rate(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (padapter) + RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate); return 0; } -ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); char tmp[32]; + u32 amsdu_rate; if (count < 1) return -EFAULT; @@ -4897,140 +3311,131 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size } if (buffer && !copy_from_user(tmp, buffer, count)) { - int i; - for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) - rfctl->channel_set[i].rx_count = 0; - RTW_INFO("set %s\n", "Clean Best Channel Count"); + int num = sscanf(tmp, "%d ", &amsdu_rate); + + if (padapter && (num == 1)) { + RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate); + padapter->tx_amsdu_rate = amsdu_rate; + } } return count; } -#endif /* CONFIG_FIND_BEST_CHANNEL */ +#endif /* CONFIG_TX_AMSDU */ +#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_BT_COEXIST -int proc_get_btcoex_dbg(struct seq_file *m, void *v) +#ifdef CONFIG_80211AC_VHT +int proc_get_vht_24g_enable(struct seq_file *m, void *v) { struct net_device *dev = m->private; - PADAPTER padapter; - char buf[512] = {0}; - padapter = (PADAPTER)rtw_netdev_priv(dev); + struct _ADAPTER *a = (struct _ADAPTER *)rtw_netdev_priv(dev); + struct registry_priv *regpriv = &a->registrypriv; - rtw_btcoex_GetDBG(padapter, buf, 512); - _RTW_PRINT_SEL(m, "%s", buf); + if (regpriv) + RTW_PRINT_SEL(m, "%d\n", regpriv->vht_24g_enable); return 0; } -ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - PADAPTER padapter; - u8 tmp[80] = {0}; - u32 module[2] = {0}; - u32 num; - - padapter = (PADAPTER)rtw_netdev_priv(dev); + struct _ADAPTER *a = (struct _ADAPTER *)rtw_netdev_priv(dev); + struct registry_priv *regpriv = &a->registrypriv; + char tmp[32]; + u32 mode; - /* RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */ - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", - FUNC_ADPT_ARG(padapter)); + if (count < 1) + return -EFAULT; + if (count > sizeof(tmp)) { + rtw_warn_on(1); return -EFAULT; } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", - FUNC_ADPT_ARG(padapter)); + if (buffer && !copy_from_user(tmp, buffer, count)) { - return -EFAULT; + int num = sscanf(tmp, "%d ", &mode); + + if ((num == 1) && regpriv && (mode < 2)) { + regpriv->vht_24g_enable = mode; + RTW_INFO("vht_24g_enable = %d\n", regpriv->vht_24g_enable); + } } - num = count; - if (num > (sizeof(tmp) - 1)) - num = (sizeof(tmp) - 1); + return count; +} +#endif /* CONFIG_80211AC_VHT */ - if (copy_from_user(tmp, buffer, num)) { - RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", - FUNC_ADPT_ARG(padapter)); +ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - return -EFAULT; - } + char tmp[32] = {0}; + u32 num = 0, enable = 0, rrsr_val = 0; /* gpio_mode:0 input 1:output; */ - num = sscanf(tmp, "%x %x", module, module + 1); - if (1 == num) { - if (0 == module[0]) - _rtw_memset(module, 0, sizeof(module)); - else - _rtw_memset(module, 0xFF, sizeof(module)); - } else if (2 != num) { - RTW_INFO(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n", - FUNC_ADPT_ARG(padapter), tmp); + if (count < 2) + return -EFAULT; - if (0 == num) - return -EFAULT; + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - RTW_INFO(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n", - FUNC_ADPT_ARG(padapter), module[0], module[1]); - rtw_btcoex_SetDBG(padapter, module); + if (buffer && !copy_from_user(tmp, buffer, count)) { + num = sscanf(tmp, "%d 0x%x", &enable, &rrsr_val); + RTW_INFO("num=%u enable=%d rrsr_val=0x%x\n", num, enable, rrsr_val); + pregpriv->en_dyn_rrsr = enable; + pregpriv->set_rrsr_value = rrsr_val; + /*rtw_phydm_dyn_rrsr_en(padapter, enable);*/ + /*rtw_phydm_set_rrsr(padapter, rrsr_val, _TRUE);*/ + } return count; + } +int proc_get_dyn_rrsr(struct seq_file *m, void *v) { -int proc_get_btcoex_info(struct seq_file *m, void *v) -{ struct net_device *dev = m->private; - PADAPTER padapter; - const u32 bufsize = 40 * 100; - u8 *pbuf = NULL; - - padapter = (PADAPTER)rtw_netdev_priv(dev); - - pbuf = rtw_zmalloc(bufsize); - if (NULL == pbuf) - return -ENOMEM; - - rtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize); - - _RTW_PRINT_SEL(m, "%s\n", pbuf); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + u32 init_rrsr =0xFFFFFFFF; - rtw_mfree(pbuf, bufsize); + if (padapter) + RTW_PRINT_SEL(m, "en_dyn_rrsr = %d fixed_rrsr_value =0x%x %s\n" + , pregpriv->en_dyn_rrsr + , pregpriv->set_rrsr_value + , (pregpriv->set_rrsr_value == init_rrsr)?"(default)":"(fixed)" + ); return 0; } - -#ifdef CONFIG_RF4CE_COEXIST -int proc_get_rf4ce_state(struct seq_file *m, void *v) +int proc_get_en_fwps(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 state = 0, voice = 0; - - state = rtw_btcoex_GetRf4ceLinkState(adapter); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect"); + if (pregpriv) + RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n" + , pregpriv->check_fw_ps); return 0; } -/* This interface is designed for user space application to inform RF4CE state - * Initial define for DHC 1295 E387 project - * - * echo state voice > rf4ce_state - * state - * 0: RF4CE disconnected - * 1: RF4CE connected - */ -ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - u8 state; + u32 mode; if (count < 1) return -EFAULT; @@ -5040,92 +3445,152 @@ ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_ return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) { + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if (num == 1 && pregpriv && mode < 2) { + pregpriv->check_fw_ps = mode; + RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps); + } + + } + + return count; +} + +#ifdef CONFIG_80211N_HT +void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + #ifdef CONFIG_80211AC_VHT + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + #endif + + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X"); + + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X"); + + #ifdef CONFIG_BEAMFORMING + #ifdef CONFIG_80211AX_HE + RTW_PRINT_SEL(sel, "[DFT CAP] HE MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_HE_MU_MIMO_AP_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HE MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_HE_MU_MIMO_STA_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HE SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_HE_BEAMFORMER_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HE SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_HE_BEAMFORMEE_ENABLE)) ? "V" : "X"); + #endif + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X"); + #endif +} + +void rtw_get_dft_phy_cap(void *sel, _adapter *adapter) +{ + RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n"); + rtw_ht_use_default_setting(adapter); + #ifdef CONFIG_80211AC_VHT + rtw_vht_get_real_setting(adapter); + #endif + #ifdef CONFIG_80211N_HT + rtw_dump_dft_phy_cap(sel, adapter); + #endif +} + +void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) +{ + struct registry_priv *pregistry_priv = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n"); + #if 0 + RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/ + #endif + #ifdef CONFIG_80211N_HT + RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%04x\n", pregistry_priv->stbc_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HE STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT10)) ? "V" : "X"); /*BIT10: Enable HE STBC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HE STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT8)) ? "V" : "X"); /*BIT8: Enable HE STBC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HE STBC Tx(>80M) : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT11)) ? "V" : "X"); /*BIT11: Enable HE STBC Tx(>80M)*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HE STBC Rx(>80M) : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT9)) ? "V" : "X"); /*BIT9: Enable HE STBC Rx(>80M)*/ + - int num = sscanf(tmp, "%hhx", &state); + RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/ + #endif /* CONFIG_80211N_HT */ + #ifdef CONFIG_BEAMFORMING + #if 0 + RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/ + #endif - if (num >= 1) - rtw_btcoex_SetRf4ceLinkState(adapter, state); - } + /* + * BIT0: Enable VHT SU Beamformer + * BIT1: Enable VHT SU Beamformee + * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer + * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee + * BIT4: Enable HT Beamformer + * BIT5: Enable HT Beamformee + */ + RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X"); - return count; + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num); + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num); + #endif } -#endif /* CONFIG_RF4CE_COEXIST */ -#endif /* CONFIG_BT_COEXIST */ -#if defined(DBG_CONFIG_ERROR_DETECT) -int proc_get_sreset(struct seq_file *m, void *v) +int proc_get_stbc_cap(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "0x%04x\n", pregpriv->stbc_cap); - if (psrtpriv->dbg_sreset_ctrl == _TRUE) { - RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt); - RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt); - RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt); - RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt); - RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt); - RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case); - RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt); - } return 0; } -ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; - s32 trigger_point; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%d", &trigger_point); - - if (num < 1) - return count; - - if (trigger_point == SRESET_TGP_NULL) - rtw_hal_sreset_reset(padapter); - else if (trigger_point == SRESET_TGP_INFO) - psrtpriv->dbg_sreset_ctrl = _TRUE; - else - sreset_set_trigger_point(padapter, trigger_point); - } - - return count; - -} -#endif /* DBG_CONFIG_ERROR_DETECT */ - -#ifdef CONFIG_PCI_HCI - -ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct pci_dev *pdev = pdvobjpriv->ppcidev; - struct pci_dev *bridge_pdev = pdev->bus->self; - - char tmp[32] = { 0 }; - int num; - - u32 reg = 0, value = 0; + u32 mode; if (count < 1) return -EFAULT; @@ -5137,69 +3602,36 @@ ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buf if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%x %x", ®, &value); - if (num != 2) { - RTW_INFO("invalid parameter!\n"); - return count; - } - - if (reg >= 0x1000) { - RTW_INFO("invalid register!\n"); - return count; - } + int num = sscanf(tmp, "%d ", &mode); - if (value > 0xFF) { - RTW_INFO("invalid value! Only one byte\n"); - return count; + if (num == 1 && pregpriv) { + pregpriv->stbc_cap = mode; + RTW_INFO("stbc_cap = 0x%02x\n", mode); } - - RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", - FUNC_ADPT_ARG(padapter), reg, value); - - pci_write_config_byte(bridge_pdev, reg, value); } + return count; } - -int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v) +int proc_get_ldpc_cap(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct pci_dev *pdev = pdvobjpriv->ppcidev; - struct pci_dev *bridge_pdev = pdev->bus->self; - - u32 tmp[4] = { 0 }; - u32 i, j; - - RTW_PRINT_SEL(m, "\n***** PCI Host Device Configuration Space*****\n\n"); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - for (i = 0; i < 0x1000; i += 0x10) { - for (j = 0 ; j < 4 ; j++) - pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j); + if (pregpriv) + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap); - RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", - i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, - tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, - tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, - tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); - } return 0; } - -ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct pci_dev *pdev = pdvobjpriv->ppcidev; - - char tmp[32] = { 0 }; - int num; - - u32 reg = 0, value = 0; + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; if (count < 1) return -EFAULT; @@ -5211,324 +3643,348 @@ ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, si if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%x %x", ®, &value); - - if (num != 2) { - RTW_INFO("invalid parameter!\n"); - return count; - } - - - if (reg >= 0x1000) { - RTW_INFO("invalid register!\n"); - return count; - } + int num = sscanf(tmp, "%d ", &mode); - if (value > 0xFF) { - RTW_INFO("invalid value! Only one byte\n"); - return count; + if (num == 1 && pregpriv) { + pregpriv->ldpc_cap = mode; + RTW_INFO("ldpc_cap = 0x%02x\n", mode); } - - RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", - FUNC_ADPT_ARG(padapter), reg, value); - - pci_write_config_byte(pdev, reg, value); - - } + return count; } - - -int proc_get_pci_conf_space(struct seq_file *m, void *v) +#ifdef CONFIG_BEAMFORMING +int proc_get_txbf_cap(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct pci_dev *pdev = pdvobjpriv->ppcidev; - struct pci_dev *bridge_pdev = pdev->bus->self; - - u32 tmp[4] = { 0 }; - u32 i, j; - - RTW_PRINT_SEL(m, "\n***** PCI Device Configuration Space *****\n\n"); - - for (i = 0; i < 0x1000; i += 0x10) { - for (j = 0 ; j < 4 ; j++) - pci_read_config_dword(pdev, i + j * 4, tmp+j); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", - i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, - tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, - tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, - tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); - } + if (pregpriv) + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap); return 0; -} - - -int proc_get_pci_aspm(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); - u8 tmp8 = 0; - u16 tmp16 = 0; - u32 tmp32 = 0; - u8 l1_idle = 0; - - - RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); - - pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); - - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); - - tmp8 = rtw_hal_pci_l1off_capability(padapter); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); - - RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n"); - - pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); - - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); - - tmp8 = rtw_hal_pci_l1off_nic_support(padapter); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); +} - RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n"); +ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); + if (count < 1) + return -EFAULT; - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); - l1_idle = tmp8 & 0x38; - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + if (buffer && !copy_from_user(tmp, buffer, count)) { - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + int num = sscanf(tmp, "%d ", &mode); - RTW_PRINT_SEL(m, "********* MISC **********\n"); - RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3); - RTW_PRINT_SEL(m, "*************************\n"); + if (num == 1 && pregpriv) { + pregpriv->beamform_cap = mode; + RTW_INFO("beamform_cap = 0x%02x\n", mode); + } + } -#ifdef CONFIG_PCI_DYNAMIC_ASPM - RTW_PRINT_SEL(m, "Dynamic ASPM mode: %d (%s)\n", pcipriv->aspm_mode, - pcipriv->aspm_mode == ASPM_MODE_PERF ? "Perf" : - pcipriv->aspm_mode == ASPM_MODE_PS ? "PS" : "Und"); + return count; +} #endif +#endif /* CONFIG_80211N_HT */ +/*int proc_get_rssi_disp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; return 0; } +*/ -int proc_get_rx_ring(struct seq_file *m, void *v) +/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - _irqL irqL; - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct recv_priv *precvpriv = &padapter->recvpriv; - struct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE]; - int i, j; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 enable=0; - RTW_PRINT_SEL(m, "rx ring (%p)\n", rx_ring); - RTW_PRINT_SEL(m, " dma: 0x%08x\n", (int) rx_ring->dma); - RTW_PRINT_SEL(m, " idx: %d\n", rx_ring->idx); + if (count < 1) + { + RTW_INFO("argument size is less than 1\n"); + return -EFAULT; + } - _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); - for (i = 0; i < precvpriv->rxringcount; i++) { -#ifdef CONFIG_TRX_BD_ARCH - struct rx_buf_desc *entry = &rx_ring->buf_desc[i]; -#else - struct recv_stat *entry = &rx_ring->desc[i]; -#endif - struct sk_buff *skb = rx_ring->rx_buf[i]; + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } - RTW_PRINT_SEL(m, " desc[%03d]: %p, rx_buf[%03d]: 0x%08x\n", - i, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb))); + if (buffer && !copy_from_user(tmp, buffer, count)) { - for (j = 0; j < sizeof(*entry) / 4; j++) { - if ((j % 4) == 0) - RTW_PRINT_SEL(m, " 0x%03x", j); + int num = sscanf(tmp, "%x", &enable); - RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[j]); + if (num != 1) { + RTW_INFO("invalid set_rssi_disp parameter!\n"); + return count; + } - if ((j % 4) == 3) - RTW_PRINT_SEL(m, "\n"); + if(enable) + { + RTW_INFO("Linked info Function Enable\n"); + padapter->bLinkInfoDump = enable ; + } + else + { + RTW_INFO("Linked info Function Disable\n"); + padapter->bLinkInfoDump = 0 ; } + } - _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); - return 0; + return count; + } -int proc_get_tx_ring(struct seq_file *m, void *v) +*/ +#ifdef CONFIG_AP_MODE + +void dump_phl_tring_status(struct seq_file *m, _adapter *padapter, struct sta_info *psta) { - _irqL irqL; - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - int i, j, k; + int i = 0; + u16 tring_len = 0; - _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); - for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) { - struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; + RTW_PRINT_SEL(m, "PHL_tring_len="); + for (i = 0; i < MAX_PHL_RING_CAT_NUM; i++) { + tring_len = rtw_phl_tring_rsc(padapter->dvobj->phl, psta->phl_sta->macid, i); + RTW_PRINT_SEL(m, "%d ", tring_len); + } + RTW_PRINT_SEL(m, "\n"); +} - RTW_PRINT_SEL(m, "tx ring[%d] (%p)\n", i, tx_ring); - RTW_PRINT_SEL(m, " dma: 0x%08x\n", (int) tx_ring->dma); - RTW_PRINT_SEL(m, " idx: %d\n", tx_ring->idx); - RTW_PRINT_SEL(m, " entries: %d\n", tx_ring->entries); - /* RTW_PRINT_SEL(m, " queue: %d\n", tx_ring->queue); */ - RTW_PRINT_SEL(m, " qlen: %d\n", tx_ring->qlen); +int proc_get_all_sta_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *pstapriv = &padapter->stapriv; + int i; + _list *plist, *phead; - for (j = 0; j < pxmitpriv->txringcount[i]; j++) { -#ifdef CONFIG_TRX_BD_ARCH - struct tx_buf_desc *entry = &tx_ring->buf_desc[j]; - RTW_PRINT_SEL(m, " buf_desc[%03d]: %p\n", j, entry); -#else - struct tx_desc *entry = &tx_ring->desc[j]; - RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); -#endif + RTW_MAP_DUMP_SEL_ALWAYS(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_MAP_DUMP_SEL_ALWAYS(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); - for (k = 0; k < sizeof(*entry) / 4; k++) { - if ((k % 4) == 0) - RTW_PRINT_SEL(m, " 0x%03x", k); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); - RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[k]); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); - if ((k % 4) == 3) - RTW_PRINT_SEL(m, "\n"); - } - } - } - _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - return 0; -} + plist = get_next(plist); -#ifdef DBG_TXBD_DESC_DUMP -int proc_get_tx_ring_ext(struct seq_file *m, void *v) -{ - _irqL irqL; - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct rtw_tx_desc_backup *pbuf; - int i, j, k, idx; + /* if(extra_arg == psta->phl_sta->aid) */ + { + RTW_PRINT_SEL(m, "==============================\n"); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_PRINT_SEL(m, "ieee8021x_blocked=%d\n", psta->ieee8021x_blocked); + RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d, hw_rts_en=%d\n", + psta->rtsen, psta->cts2self, psta->hw_rts_en); + /* ToDo: need API to query hal_sta->ra_info.rate_id */ + /* RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid, psta->phl_sta->hal_sta->ra_info.rate_id); */ + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid); +#ifdef CONFIG_RTS_FULL_BW + if(psta->vendor_8812) + RTW_PRINT_SEL(m,"Vendor Realtek 8812\n"); +#endif/*CONFIG_RTS_FULL_BW*/ +#ifdef CONFIG_80211N_HT + RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->phl_sta->chandef.bw, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable); + RTW_PRINT_SEL(m, "Is_8K_AMSDU = %d\n", (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_MAX_AMSDU)?1:0); + RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); + RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); + if (psta->vhtpriv.vht_option) { + RTW_MAP_DUMP_SEL_ALWAYS(m, "vht_cap=", psta->vhtpriv.vht_cap, 32); + } else { + RTW_PRINT_SEL(m, "vht_cap=N/A\n"); + } +#endif +#ifdef CONFIG_80211AX_HE + RTW_PRINT_SEL(m, "he_en=%d\n", psta->hepriv.he_option); + if (psta->hepriv.he_option) { + RTW_MAP_DUMP_SEL_ALWAYS(m, "he_cap=", psta->hepriv.he_cap, HE_CAP_ELE_MAX_LEN); + } else { + RTW_PRINT_SEL(m, "he_cap=N/A\n"); + } +#endif + RTW_PRINT_SEL(m, "tx_nss=%d\n", rtw_get_sta_tx_nss(padapter, psta)); + RTW_PRINT_SEL(m, "rx_nss=%d\n", rtw_get_sta_rx_nss(padapter, psta)); + RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len); + RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt); + RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt); + RTW_PRINT_SEL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt); + RTW_PRINT_SEL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt); - RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n"); - RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT); - RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN); - RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN); + RTW_PRINT_SEL(m, "capability=0x%x\n", psta->capability); + RTW_PRINT_SEL(m, "flags=0x%x\n", psta->flags); + RTW_PRINT_SEL(m, "isPMF=%d\n", (psta->flags & WLAN_STA_MFP)?1:0); + RTW_PRINT_SEL(m, "wpa_psk=0x%x\n", psta->wpa_psk); + RTW_PRINT_SEL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); + RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); + RTW_PRINT_SEL(m, "qos_info=0x%x\n", psta->qos_info); + RTW_PRINT_SEL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); + RTW_PRINT_SEL(m, "AuthAlgrthm=0x%x\n", psta->authalg); +#ifdef CONFIG_RECV_REORDERING_CTRL + sta_rx_reorder_ctl_dump(m, psta); +#endif +#ifdef CONFIG_TDLS + RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state); + RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime); +#endif /* CONFIG_TDLS */ + if(psta->bssratelen >= 0 && psta->bssratelen <= 16) + RTW_MAP_DUMP_SEL_ALWAYS(m, "bssrateset=", psta->bssrateset, psta->bssratelen); + RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta)); + RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts); + RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts); + RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta)); + RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes); + RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes); + if (psta->sta_stats.rx_tp_kbits >> 10) + RTW_PRINT_SEL(m, "rx_tp =%d (Mbps)\n", psta->sta_stats.rx_tp_kbits >> 10); + else + RTW_PRINT_SEL(m, "rx_tp =%d (Kbps)\n", psta->sta_stats.rx_tp_kbits); - if (!pxmitpriv->dump_txbd_desc) { - RTW_PRINT_SEL(m, "Dump function is disabled.\n"); - return 0; - } + RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); + RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); + if (psta->sta_stats.tx_tp_kbits >> 10) + RTW_PRINT_SEL(m, "tx_tp =%d (Mbps)\n", psta->sta_stats.tx_tp_kbits >> 10); + else + RTW_PRINT_SEL(m, "tx_tp =%d (Kbps)\n", psta->sta_stats.tx_tp_kbits); +#ifdef CONFIG_RTW_80211K + RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap)); +#endif + dump_st_ctl(m, &psta->st_ctl); - _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); - for (i = 0; i < HW_QUEUE_ENTRY; i++) { - struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; + if (STA_OP_WFD_MODE(psta)) + RTW_PRINT_SEL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta)); - idx = rtw_get_tx_desc_backup(padapter, i, &pbuf); + dump_phl_tring_status(m, padapter, psta); + RTW_PRINT_SEL(m, "==============================\n"); + } - RTW_PRINT_SEL(m, "Tx ring[%d]", i); - switch (i) { - case 0: - RTW_PRINT_SEL(m, " (VO)\n"); - break; - case 1: - RTW_PRINT_SEL(m, " (VI)\n"); - break; - case 2: - RTW_PRINT_SEL(m, " (BE)\n"); - break; - case 3: - RTW_PRINT_SEL(m, " (BK)\n"); - break; - case 4: - RTW_PRINT_SEL(m, " (BCN)\n"); - break; - case 5: - RTW_PRINT_SEL(m, " (MGT)\n"); - break; - case 6: - RTW_PRINT_SEL(m, " (HIGH)\n"); - break; - case 7: - RTW_PRINT_SEL(m, " (TXCMD)\n"); - break; - default: - RTW_PRINT_SEL(m, " (?)\n"); - break; } - RTW_PRINT_SEL(m, " Entries: %d\n", TX_BAK_FRMAE_CNT); - RTW_PRINT_SEL(m, " Last idx: %d\n", idx); + } + + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); + + return 0; +} - for (j = 0; j < TX_BAK_FRMAE_CNT; j++) { - RTW_PRINT_SEL(m, " desc[%03d]:\n", j); +#endif - for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) { - if ((k % 4) == 0) - RTW_PRINT_SEL(m, " 0x%03x", k); +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER +int proc_get_rtkm_info(struct seq_file *m, void *v) +{ + RTW_PRINT_SEL(m, "============[RTKM Info]============\n"); + RTW_PRINT_SEL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb()); + RTW_PRINT_SEL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size()); - RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]); + RTW_PRINT_SEL(m, "============[Driver Info]============\n"); - if ((k % 4) == 3) - RTW_PRINT_SEL(m, "\n"); - } + return 0; +} +#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ -#if 1 /* data dump */ - if (pbuf->tx_desc_size) { - RTW_PRINT_SEL(m, " data[%03d]:\n", j); +#ifdef DBG_MEMORY_LEAK +#include +extern ATOMIC_T _malloc_cnt; +extern ATOMIC_T _malloc_size; - for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) { - if ((k % 4) == 0) - RTW_PRINT_SEL(m, " 0x%03x", k); +int proc_get_malloc_cnt(struct seq_file *m, void *v) +{ + RTW_PRINT_SEL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt)); + RTW_PRINT_SEL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size)); - RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]); + return 0; +} +#endif /* DBG_MEMORY_LEAK */ - if ((k % 4) == 3) - RTW_PRINT_SEL(m, "\n"); - } - RTW_PRINT_SEL(m, "\n"); +#ifdef CONFIG_FIND_BEST_CHANNEL +int proc_get_best_channel(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; + + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + if (rfctl->channel_set[i].ChannelNum == 1) + index_24G = i; + if (rfctl->channel_set[i].ChannelNum == 36) + index_5G = i; + } + + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + /* 2.4G */ + if (rfctl->channel_set[i].ChannelNum == 6) { + if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { + index_24G = i; + best_channel_24G = rfctl->channel_set[i].ChannelNum; } -#endif + } - RTW_PRINT_SEL(m, " R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp); + /* 5G */ + if (rfctl->channel_set[i].ChannelNum >= 36 + && rfctl->channel_set[i].ChannelNum < 140) { + /* Find primary channel */ + if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { + index_5G = i; + best_channel_5G = rfctl->channel_set[i].ChannelNum; + } + } - pbuf = pbuf + 1; + if (rfctl->channel_set[i].ChannelNum >= 149 + && rfctl->channel_set[i].ChannelNum < 165) { + /* find primary channel */ + if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { + index_5G = i; + best_channel_5G = rfctl->channel_set[i].ChannelNum; + } } - RTW_PRINT_SEL(m, "\n"); +#if 1 /* debug */ + RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n", + rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count); +#endif } - _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + RTW_PRINT_SEL(m, "best_channel_5G = %d\n", best_channel_5G); + RTW_PRINT_SEL(m, "best_channel_24G = %d\n", best_channel_24G); return 0; } -ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - _irqL irqL; struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); char tmp[32]; - u32 reset = 0; - u32 dump = 0; if (count < 1) return -EFAULT; @@ -5539,217 +3995,177 @@ ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_ } if (buffer && !copy_from_user(tmp, buffer, count)) { + int i; + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) + rfctl->channel_set[i].rx_count = 0; - int num = sscanf(tmp, "%u %u", &dump, &reset); - - if (num != 2) { - RTW_INFO("invalid parameter!\n"); - return count; - } - - _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); - pxmitpriv->dump_txbd_desc = (BOOLEAN) dump; - - if (reset == 1) - rtw_tx_desc_backup_reset(); - - _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); - + RTW_INFO("set %s\n", "Clean Best Channel Count"); } return count; } +#endif /* CONFIG_FIND_BEST_CHANNEL */ -#endif - -#endif - -#ifdef CONFIG_WOWLAN -int proc_get_wow_enable(struct seq_file *m, void *v) +#ifdef CONFIG_BTC +int proc_get_btc_dbg(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *registry_pair = &padapter->registrypriv; + _adapter *padapter; + char buf[512] = {0}; + padapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_btc_get_dbg(padapter, buf, 512); + + _RTW_PRINT_SEL(m, "%s", buf); - RTW_PRINT_SEL(m, "wow - %s\n", (registry_pair->wowlan_enable)? "enable" : "disable"); return 0; } -ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) +ssize_t proc_set_btc_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *registry_pair = &padapter->registrypriv; - char tmp[8]; - int num = 0; - int mode = 0; + _adapter *padapter; + u8 tmp[80] = {0}; + u32 module[2] = {0}; + u32 num; - if (count < 1) - return -EFAULT; + padapter = (_adapter *)rtw_netdev_priv(dev); + + /* RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */ + + if (NULL == buffer) { + RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", + FUNC_ADPT_ARG(padapter)); - if (count > sizeof(tmp)) { - rtw_warn_on(1); return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) - num = sscanf(tmp, "%d", &mode); - else + if (count < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", + FUNC_ADPT_ARG(padapter)); + return -EFAULT; + } - if (num != 1) { - RTW_ERR("%s: %s - invalid parameter!\n", __func__, tmp); - return -EINVAL; + num = count; + if (num > (sizeof(tmp) - 1)) + num = (sizeof(tmp) - 1); + + if (copy_from_user(tmp, buffer, num)) { + RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", + FUNC_ADPT_ARG(padapter)); + + return -EFAULT; } - if (mode == 1) { - RTW_PRINT("%s: wowlan - enable\n", __func__); - } else if (mode == 0) { - RTW_PRINT("%s: wowlan - disable\n", __func__); - } else { - RTW_ERR("%s: %s - invalid parameter!, mode=%d\n", - __func__, tmp, mode); - return -EINVAL; + num = sscanf(tmp, "%x %x", module, module + 1); + if (1 == num) { + if (0 == module[0]) + _rtw_memset(module, 0, sizeof(module)); + else + _rtw_memset(module, 0xFF, sizeof(module)); + } else if (2 != num) { + RTW_INFO(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n", + FUNC_ADPT_ARG(padapter), tmp); + + if (0 == num) + return -EFAULT; } - registry_pair->wowlan_enable = mode; + RTW_INFO(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n", + FUNC_ADPT_ARG(padapter), module[0], module[1]); + rtw_btc_set_dbg(padapter, module); return count; } -int proc_get_pattern_info(struct seq_file *m, void *v) +int proc_get_btc_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 val8; - char str_1[128]; - char *p_str; - int i = 0 , j = 0, k = 0; - int len = 0, max_len = 0, total = 0; - - p_str = str_1; - max_len = sizeof(str_1); - - total = pwrpriv->wowlan_pattern_idx; + _adapter *padapter; - rtw_set_default_pattern(padapter); + padapter = (_adapter *)rtw_netdev_priv(dev); - /*show pattern*/ - RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n"); - RTW_PRINT_SEL(m, "pattern number: %d\n", total); - RTW_PRINT_SEL(m, "support default patterns: %c\n", - (pwrpriv->default_patterns_en) ? 'Y' : 'N'); + rtw_btc_disp_btc_info(padapter, (void*)m, 0); - for (k = 0; k < total ; k++) { - RTW_PRINT_SEL(m, "\npattern idx: %d\n", k); - RTW_PRINT_SEL(m, "pattern content:\n"); + return 0; +} +#endif /* CONFIG_BTC */ - p_str = str_1; - max_len = sizeof(str_1); - for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { - _rtw_memset(p_str, 0, max_len); - len = 0; - for (j = 0 ; j < 8 ; j++) { - val8 = pwrpriv->patterns[k].content[i * 8 + j]; - len += snprintf(p_str + len, max_len - len, - "%02x ", val8); - } - RTW_PRINT_SEL(m, "%s\n", p_str); - } - RTW_PRINT_SEL(m, "\npattern mask:\n"); - for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { - _rtw_memset(p_str, 0, max_len); - len = 0; - for (j = 0 ; j < 8 ; j++) { - val8 = pwrpriv->patterns[k].mask[i * 8 + j]; - len += snprintf(p_str + len, max_len - len, - "%02x ", val8); - } - RTW_PRINT_SEL(m, "%s\n", p_str); - } +#if defined(DBG_CONFIG_ERROR_DETECT) +int proc_get_sreset(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + HAL_DATA_TYPE *pHalData = GET_PHL_COM(psdpriv); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; - RTW_PRINT_SEL(m, "\npriv_pattern_len:\n"); - RTW_PRINT_SEL(m, "pattern_len: %d\n", pwrpriv->patterns[k].len); - RTW_PRINT_SEL(m, "*****************\n"); + if (psrtpriv->dbg_sreset_ctrl == _TRUE) { + RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt); + RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt); + RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt); + RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt); + RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt); + RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case); + RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt); } - return 0; } -ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) +ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct wowlan_ioctl_param poidparam; - u8 tmp[MAX_WKFM_PATTERN_STR_LEN + 1] = {0}; - int ret = 0; - u8 index = 0; - - poidparam.subcode = 0; + HAL_DATA_TYPE *pHalData = GET_PHL_COM(adapter_to_dvobj(padapter)); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + char tmp[32]; + s32 trigger_point; if (count < 1) return -EFAULT; - if (count >= sizeof(tmp)) { - RTW_ERR("%s: pattern string is too long, count=%zu\n", - __func__, count); + if (count > sizeof(tmp)) { + rtw_warn_on(1); return -EFAULT; } - if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) { - RTW_ERR("priv-pattern is full(idx: %d)\n", - pwrpriv->wowlan_pattern_idx); - RTW_ERR("please clean priv-pattern first\n"); - return -ENOMEM; - } - if (buffer && !copy_from_user(tmp, buffer, count)) { - if (strncmp(tmp, "clean", 5) == 0) { - poidparam.subcode = WOWLAN_PATTERN_CLEAN; - rtw_hal_set_hwreg(padapter, - HW_VAR_WOWLAN, (u8 *)&poidparam); - } else { - index = pwrpriv->wowlan_pattern_idx; - ret = rtw_wowlan_parser_pattern_cmd(tmp, - pwrpriv->patterns[index].content, - &pwrpriv->patterns[index].len, - pwrpriv->patterns[index].mask); - if (ret == _TRUE) - pwrpriv->wowlan_pattern_idx++; - } - } else { - rtw_warn_on(1); - return -EFAULT; + + int num = sscanf(tmp, "%d", &trigger_point); + + if (num < 1) + return count; + + if (trigger_point == SRESET_TGP_NULL) + rtw_hal_sreset_reset(padapter); + else if (trigger_point == SRESET_TGP_INFO) + psrtpriv->dbg_sreset_ctrl = _TRUE; + else + sreset_set_trigger_point(padapter, trigger_point); } return count; -} - -int proc_get_wakeup_event(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *registry_par = &padapter->registrypriv; - RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event); - return 0; } +#endif /* DBG_CONFIG_ERROR_DETECT */ -ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) +#ifdef CONFIG_PCI_HCI + +ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - struct registry_priv *registry_par = &padapter->registrypriv; - u32 wakeup_event = 0; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv); + struct pci_dev *pdev = pci_data->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; - u8 tmp[8] = {0}; - int num = 0; + char tmp[32] = { 0 }; + int num; + + u32 reg = 0, value = 0; if (count < 1) return -EFAULT; @@ -5759,96 +4175,73 @@ ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) - num = sscanf(tmp, "%u", &wakeup_event); - else - return -EFAULT; + if (buffer && !copy_from_user(tmp, buffer, count)) { - if (num == 1 && wakeup_event <= 0x0f) { - registry_par->wakeup_event = wakeup_event; + num = sscanf(tmp, "%x %x", ®, &value); + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } - if (wakeup_event & BIT(1)) - pwrctrlpriv->default_patterns_en = _TRUE; - else - pwrctrlpriv->default_patterns_en = _FALSE; + if (reg >= 0x1000) { + RTW_INFO("invalid register!\n"); + return count; + } - rtw_wow_pattern_sw_reset(padapter); + if (value > 0xFF) { + RTW_INFO("invalid value! Only one byte\n"); + return count; + } - RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n", - __func__, registry_par->wakeup_event, - pwrctrlpriv->default_patterns_en); - } else { - return -EINVAL; - } + RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", + FUNC_ADPT_ARG(padapter), reg, value); + pci_write_config_byte(bridge_pdev, reg, value); + } return count; } -int proc_get_wakeup_reason(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 val = pwrpriv->wowlan_last_wake_reason; - RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val); - return 0; -} -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN -int proc_dump_wow_keep_alive_info(struct seq_file *m, void *v) { +int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - int i; - - RTW_PRINT_SEL(m, "wowlan_keep_alive_mode: %d\n", pwrpriv->wowlan_keep_alive_mode); - RTW_PRINT_SEL(m,"LocKeepAlive: %d\n", pwrpriv->keep_alive_pattern_loc ); - RTW_PRINT_SEL(m, "keep_alive_pattern_len: %d\n", pwrpriv->keep_alive_pattern_len); - RTW_PRINT_SEL(m,"keep_alive_pattern= \n" ); - for (i=0 ; i < pwrpriv->keep_alive_pattern_len ; i++) { - RTW_PRINT_SEL(m,"[0x%x] ",pwrpriv->keep_alive_pattern[i]); - if(i%8 == 7) - RTW_PRINT_SEL(m,"\n"); - } - RTW_PRINT_SEL(m,"\n"); - RTW_PRINT_SEL(m," wowlan_keep_alive_period= %d ms\n", pwrpriv->wowlan_keep_alive_period*100); - RTW_PRINT_SEL(m," wowlan_keep_alive_retry_counter= %d\n", pwrpriv->wowlan_keep_alive_retry_counter); - RTW_PRINT_SEL(m," wowlan_keep_alive_retry_interval= %d ms\n", pwrpriv->wowlan_keep_alive_retry_interval*100); - return 0; -} -#endif /* CONFIG_WOW_KEEP_ALIVE_PATTERN*/ + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv); + struct pci_dev *pdev = pci_data->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; -#endif /*CONFIG_WOWLAN*/ + u32 tmp[4] = { 0 }; + u32 i, j; -#ifdef CONFIG_GPIO_WAKEUP -int proc_get_wowlan_gpio_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 gpio_index = pwrpriv->wowlan_gpio_index; - u8 gpio_output_state = pwrpriv->wowlan_gpio_output_state; - u8 val = pwrpriv->is_high_active; + RTW_PRINT_SEL(m, "\n***** PCI Host Device Configuration Space*****\n\n"); - RTW_PRINT_SEL(m, "wakeup_gpio_idx: %d\n", gpio_index); -#if (!defined(CONFIG_WAKEUP_GPIO_INPUT_MODE) && !defined(CONFIG_RTW_ONE_PIN_GPIO)) - RTW_PRINT_SEL(m, "current_gpio_output_state: %d\n", gpio_output_state); -#endif - RTW_PRINT_SEL(m, "high_active: %d\n", val); + for (i = 0; i < 0x1000; i += 0x10) { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j); + RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); + } return 0; } -ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) + +ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - char tmp[32] = {0}; - int num = 0; - u32 is_high_active = 0; - u8 val8 = 0; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv); + struct pci_dev *pdev = pci_data->ppcidev; + + char tmp[32] = { 0 }; + int num; + + u32 reg = 0, value = 0; if (count < 1) return -EFAULT; @@ -5860,374 +4253,290 @@ ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%u", &is_high_active); + num = sscanf(tmp, "%x %x", ®, &value); - if (num != 1) { - RTW_INFO("Invalid format\n"); + if (num != 2) { + RTW_INFO("invalid parameter!\n"); return count; } - is_high_active = is_high_active == 0 ? 0 : 1; - pwrpriv->is_high_active = is_high_active; + if (reg >= 0x1000) { + RTW_INFO("invalid register!\n"); + return count; + } - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); + if (value > 0xFF) { + RTW_INFO("invalid value! Only one byte\n"); + return count; + } -#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE - if (pwrpriv->is_high_active == 0) - rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index); - else - rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, - GPIO_OUTPUT_LOW); -#else - val8 = (pwrpriv->is_high_active == 0) ? 1 : 0; - rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE); - rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, val8); -#endif - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", + FUNC_ADPT_ARG(padapter), reg, value); - RTW_INFO("%s set GPIO_%d to %s_ACTIVE\n", __func__, - pwrpriv->wowlan_gpio_index, - pwrpriv->is_high_active ? "HIGH" : "LOW"); - } + pci_write_config_byte(pdev, reg, value); + + } return count; } -#endif /* CONFIG_GPIO_WAKEUP */ -#ifdef CONFIG_P2P_WOWLAN -int proc_get_p2p_wowlan_info(struct seq_file *m, void *v) + +int proc_get_pci_conf_space(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct p2p_wowlan_info peerinfo = pwdinfo->p2p_wow_info; - if (_TRUE == peerinfo.is_trigger) { - RTW_PRINT_SEL(m, "is_trigger: TRUE\n"); - switch (peerinfo.wowlan_recv_frame_type) { - case P2P_WOWLAN_RECV_NEGO_REQ: - RTW_PRINT_SEL(m, "Frame Type: Nego Request\n"); - break; - case P2P_WOWLAN_RECV_INVITE_REQ: - RTW_PRINT_SEL(m, "Frame Type: Invitation Request\n"); - break; - case P2P_WOWLAN_RECV_PROVISION_REQ: - RTW_PRINT_SEL(m, "Frame Type: Provision Request\n"); - break; - default: - break; - } - RTW_PRINT_SEL(m, "Peer Addr: "MAC_FMT"\n", MAC_ARG(peerinfo.wowlan_peer_addr)); - RTW_PRINT_SEL(m, "Peer WPS Config: %x\n", peerinfo.wowlan_peer_wpsconfig); - RTW_PRINT_SEL(m, "Persistent Group: %d\n", peerinfo.wowlan_peer_is_persistent); - RTW_PRINT_SEL(m, "Intivation Type: %d\n", peerinfo.wowlan_peer_invitation_type); - } else - RTW_PRINT_SEL(m, "is_trigger: False\n"); - return 0; -} -#endif /* CONFIG_P2P_WOWLAN */ -#ifdef CONFIG_BCN_CNT_CONFIRM_HDL -int proc_get_new_bcn_max(struct seq_file *m, void *v) -{ - extern int new_bcn_max; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv); + struct pci_dev *pdev = pci_data->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; - RTW_PRINT_SEL(m, "%d", new_bcn_max); - return 0; -} + u32 tmp[4] = { 0 }; + u32 i, j; -ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - extern int new_bcn_max; + RTW_PRINT_SEL(m, "\n***** PCI Device Configuration Space *****\n\n"); - if (count < 1) - return -EFAULT; + for (i = 0; i < 0x1000; i += 0x10) { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(pdev, i + j * 4, tmp+j); - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; + RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); } - if (buffer && !copy_from_user(tmp, buffer, count)) - sscanf(tmp, "%d ", &new_bcn_max); - - return count; + return 0; } -#endif -#ifdef CONFIG_POWER_SAVING -int proc_get_ps_info(struct seq_file *m, void *v) + + +int proc_get_pci_aspm(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 ips_mode = pwrpriv->ips_mode_req; - u8 lps_mode = pwrpriv->power_mgnt; - u8 lps_level = pwrpriv->lps_level; -#ifdef CONFIG_LPS_1T1R - u8 lps_1t1r = pwrpriv->lps_1t1r; -#endif -#ifdef CONFIG_WOWLAN - u8 wow_lps_mode = pwrpriv->wowlan_power_mgmt; - u8 wow_lps_level = pwrpriv->wowlan_lps_level; - #ifdef CONFIG_LPS_1T1R - u8 wow_lps_1t1r = pwrpriv->wowlan_lps_1t1r; - #endif -#endif /* CONFIG_WOWLAN */ - char *str = ""; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv); + struct pci_priv *pcipriv = &(pci_data->pcipriv); + u8 tmp8 = 0; + u16 tmp16 = 0; + u32 tmp32 = 0; + u8 l1_idle = 0; - RTW_PRINT_SEL(m, "======Power Saving Info:======\n"); - RTW_PRINT_SEL(m, "*IPS:\n"); - if (ips_mode == IPS_NORMAL) { -#ifdef CONFIG_FWLPS_IN_IPS - str = "FW_LPS_IN_IPS"; -#else - str = "Card Disable"; -#endif - } else if (ips_mode == IPS_NONE) - str = "NO IPS"; - else if (ips_mode == IPS_LEVEL_2) - str = "IPS_LEVEL_2"; - else - str = "invalid ips_mode"; + RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); - RTW_PRINT_SEL(m, " IPS mode: %s\n", str); - RTW_PRINT_SEL(m, " IPS enter count:%d, IPS leave count:%d\n", - pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts); - RTW_PRINT_SEL(m, "------------------------------\n"); - RTW_PRINT_SEL(m, "*LPS:\n"); + pci_read_config_dword(pci_data->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); - if (lps_mode == PS_MODE_ACTIVE) - str = "NO LPS"; - else if (lps_mode == PS_MODE_MIN) - str = "MIN"; - else if (lps_mode == PS_MODE_MAX) - str = "MAX"; - else if (lps_mode == PS_MODE_DTIM) - str = "DTIM"; - else - sprintf(str, "%d", lps_mode); + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, " LPS mode: %s\n", str); + tmp8 = rtw_hal_pci_l1off_capability(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); - if (pwrpriv->dtim != 0) - RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim); - RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n", - pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts); + RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n"); - if (lps_level == LPS_LCLK) - str = "LPS_LCLK"; - else if (lps_level == LPS_PG) - str = "LPS_PG"; - else - str = "LPS_NORMAL"; - RTW_PRINT_SEL(m, " LPS level: %s\n", str); + pci_read_config_word(pci_data->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); -#ifdef CONFIG_LPS_1T1R - RTW_PRINT_SEL(m, " LPS 1T1R: %d\n", lps_1t1r); -#endif + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); -#ifdef CONFIG_WOWLAN - RTW_PRINT_SEL(m, "------------------------------\n"); - RTW_PRINT_SEL(m, "*WOW LPS:\n"); + tmp8 = rtw_hal_pci_l1off_nic_support(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); - if (wow_lps_mode == PS_MODE_ACTIVE) - str = "NO LPS"; - else if (wow_lps_mode == PS_MODE_MIN) - str = "MIN"; - else if (wow_lps_mode == PS_MODE_MAX) - str = "MAX"; - else if (wow_lps_mode == PS_MODE_DTIM) - str = "DTIM"; - else - sprintf(str, "%d", wow_lps_mode); + RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n"); - RTW_PRINT_SEL(m, " WOW LPS mode: %s\n", str); + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); - if (wow_lps_level == LPS_LCLK) - str = "LPS_LCLK"; - else if (wow_lps_level == LPS_PG) - str = "LPS_PG"; - else - str = "LPS_NORMAL"; - RTW_PRINT_SEL(m, " WOW LPS level: %s\n", str); + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + l1_idle = tmp8 & 0x38; + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); - #ifdef CONFIG_LPS_1T1R - RTW_PRINT_SEL(m, " WOW LPS 1T1R: %d\n", wow_lps_1t1r); - #endif -#endif /* CONFIG_WOWLAN */ + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "********* MISC **********\n"); + RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3); + RTW_PRINT_SEL(m, "*************************\n"); + +#ifdef CONFIG_PCI_DYNAMIC_ASPM + RTW_PRINT_SEL(m, "Dynamic ASPM mode: %d (%s)\n", pcipriv->aspm_mode, + pcipriv->aspm_mode == ASPM_MODE_PERF ? "Perf" : + pcipriv->aspm_mode == ASPM_MODE_PS ? "PS" : "Und"); +#endif - RTW_PRINT_SEL(m, "=============================\n"); return 0; } -ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_rx_ring(struct seq_file *m, void *v) { - struct net_device *dev = data; - struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[8]; - int num = 0; - int mode = 0; - int en = 0; - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } + return 0; +} - if (!buffer || copy_from_user(tmp, buffer, count)) - goto exit; +int proc_get_tx_ring(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + int i, j, k; + unsigned long sp_flags; - num = sscanf(tmp, "%d %d", &mode, &en); - if (num > 2) { - RTW_ERR("%s: invalid parameter!\n", __FUNCTION__); - goto exit; - } + _rtw_spinlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); + for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) { + struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; - if (num == 1 && mode == 0) { - /* back to original LPS/IPS Mode */ - RTW_INFO("%s: back to original LPS/IPS Mode\n", __FUNCTION__); + RTW_PRINT_SEL(m, "tx ring[%d] (%p)\n", i, tx_ring); + RTW_PRINT_SEL(m, " dma: 0x%08x\n", (int) tx_ring->dma); + RTW_PRINT_SEL(m, " idx: %d\n", tx_ring->idx); + RTW_PRINT_SEL(m, " entries: %d\n", tx_ring->entries); + /* RTW_PRINT_SEL(m, " queue: %d\n", tx_ring->queue); */ + RTW_PRINT_SEL(m, " qlen: %d\n", tx_ring->qlen); - rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt); - - rtw_pm_set_ips(adapter, adapter->registrypriv.ips_mode); + for (j = 0; j < pxmitpriv->txringcount[i]; j++) { +#ifdef CONFIG_TRX_BD_ARCH + struct tx_buf_desc *entry = &tx_ring->buf_desc[j]; + RTW_PRINT_SEL(m, " buf_desc[%03d]: %p\n", j, entry); +#else + struct tx_desc *entry = &tx_ring->desc[j]; + RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); +#endif -#ifdef CONFIG_WOWLAN - RTW_INFO("%s: back to original WOW LPS Mode\n", __FUNCTION__); + for (k = 0; k < sizeof(*entry) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); - rtw_pm_set_wow_lps(adapter, adapter->registrypriv.wow_power_mgnt); -#endif /* CONFIG_WOWLAN */ + RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[k]); - goto exit; - } - - if (mode == 1) { - /* LPS */ - RTW_INFO("%s: LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); - if (rtw_pm_set_lps(adapter, en) != 0 ) - RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); - - } else if (mode == 2) { - /* IPS */ - RTW_INFO("%s: IPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); - if (rtw_pm_set_ips(adapter, en) != 0 ) - RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); - } -#ifdef CONFIG_WOWLAN - else if (mode == 3) { - /* WOW LPS */ - RTW_INFO("%s: WOW LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); - if (rtw_pm_set_wow_lps(adapter, en) != 0 ) - RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + } } -#endif /* CONFIG_WOWLAN */ - else - RTW_ERR("%s: invalid parameter, mode = %d!\n", __FUNCTION__, mode); + _rtw_spinunlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); -exit: - return count; + return 0; } -#ifdef CONFIG_WMMPS_STA -int proc_get_wmmps_info(struct seq_file *m, void *v) +#ifdef DBG_TXBD_DESC_DUMP +int proc_get_tx_ring_ext(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - char *uapsd_max_sp_str=""; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_desc_backup *pbuf; + int i, j, k, idx; + unsigned long sp_flags; - if (pregpriv){ - switch(pregpriv->uapsd_max_sp_len) { - case 0: - uapsd_max_sp_str = "NO_LIMIT"; - break; - case 1: - uapsd_max_sp_str = "TWO_MSDU"; - break; - case 2: - uapsd_max_sp_str = "FOUR_MSDU"; - break; - case 3: - uapsd_max_sp_str = "SIX_MSDU"; - break; - default: - uapsd_max_sp_str = "UNSPECIFIED"; - break; + RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n"); + RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN); + RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN); + + if (!pxmitpriv->dump_txbd_desc) { + RTW_PRINT_SEL(m, "Dump function is disabled.\n"); + return 0; + } + + _rtw_spinlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); + for (i = 0; i < HW_QUEUE_ENTRY; i++) { + struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; + + idx = rtw_get_tx_desc_backup(padapter, i, &pbuf); + + RTW_PRINT_SEL(m, "Tx ring[%d]", i); + switch (i) { + case 0: + RTW_PRINT_SEL(m, " (VO)\n"); + break; + case 1: + RTW_PRINT_SEL(m, " (VI)\n"); + break; + case 2: + RTW_PRINT_SEL(m, " (BE)\n"); + break; + case 3: + RTW_PRINT_SEL(m, " (BK)\n"); + break; + case 4: + RTW_PRINT_SEL(m, " (BCN)\n"); + break; + case 5: + RTW_PRINT_SEL(m, " (MGT)\n"); + break; + case 6: + RTW_PRINT_SEL(m, " (HIGH)\n"); + break; + case 7: + RTW_PRINT_SEL(m, " (TXCMD)\n"); + break; + default: + RTW_PRINT_SEL(m, " (?)\n"); + break; } - RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n"); - RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str); - RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable); - RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled"); - RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled"); - RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled"); - RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled"); - RTW_PRINT_SEL(m, "============================\n"); - } + RTW_PRINT_SEL(m, " Entries: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " Last idx: %d\n", idx); - return 0; -} + for (j = 0; j < TX_BAK_FRMAE_CNT; j++) { + RTW_PRINT_SEL(m, " desc[%03d]:\n", j); -ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - char tmp[32]; - u8 uapsd_ac_setting; - u8 uapsd_max_sp_len_setting; + for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); - if (count < 1) - return -EFAULT; + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]); - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } - if (buffer && !copy_from_user(tmp, buffer, count)) { +#if 1 /* data dump */ + if (pbuf->tx_desc_size) { + RTW_PRINT_SEL(m, " data[%03d]:\n", j); - int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting); + for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); - if (pregpriv) { - if (num >= 1) { - pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting; - RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len); - } + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]); - if (num >= 2) { - pregpriv->uapsd_ac_enable = uapsd_ac_setting; - RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable); + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + RTW_PRINT_SEL(m, "\n"); } - } - } - - return count; -} -#endif /* CONFIG_WMMPS_STA */ -#endif /* CONFIG_POWER_SAVING */ +#endif -#ifdef CONFIG_TDLS -int proc_get_tdls_enable(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; + RTW_PRINT_SEL(m, " R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp); - if (pregpriv) - RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled"); + pbuf = pbuf + 1; + } + RTW_PRINT_SEL(m, "\n"); + } + _rtw_spinunlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); return 0; } -ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); char tmp[32]; - u32 en_tdls = 0; + u32 reset = 0; + u32 dump = 0; + unsigned long sp_flags; if (count < 1) return -EFAULT; @@ -6239,462 +4548,290 @@ ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_ if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &en_tdls); + int num = sscanf(tmp, "%u %u", &dump, &reset); - if (num == 1 && pregpriv) { - if (en_tdls > 0) - rtw_enable_tdls_func(padapter); - else - rtw_disable_tdls_func(padapter, _TRUE); + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; } - } - return count; -} + _rtw_spinlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); + pxmitpriv->dump_txbd_desc = (BOOLEAN) dump; -static int proc_tdls_display_tdls_function_info(struct seq_file *m) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; - u8 SpaceBtwnItemAndValueTmp = 0; - BOOLEAN FirstMatchFound = _FALSE; - int j = 0; + if (reset == 1) + rtw_tx_desc_backup_reset(); - RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE"); + _rtw_spinunlock_irq(&dvobj_to_pci(pdvobjpriv)->irq_th_lock, &sp_flags); -#ifdef CONFIG_TDLS_CH_SW - RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State"); - if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE) - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE"); - else { - for (j = 0; j < 32; j++) { - if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) { - if (FirstMatchFound == _FALSE) { - SpaceBtwnItemAndValueTmp = 1; - FirstMatchFound = _TRUE; - } else - SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; - switch (BIT(j)) { - case TDLS_INITIATOR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); - break; - case TDLS_RESPONDER_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); - break; - case TDLS_LINKED_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); - break; - case TDLS_WAIT_PTR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); - break; - case TDLS_ALIVE_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); - break; - case TDLS_CH_SWITCH_ON_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); - break; - case TDLS_PEER_AT_OFF_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); - break; - case TDLS_CH_SW_INITIATOR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); - break; - case TDLS_WAIT_CH_RSP_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); - break; - default: - RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); - break; - } - } - } } - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num); - RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset); - RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack); -#endif - - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE"); - - return 0; + return count; } - -static int proc_tdls_display_network_info(struct seq_file *m) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - int i = 0; - u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; - - /* Display the linked AP/GO info */ - RTW_PRINT_SEL(m, "============[Associated AP/GO Info]============\n"); - - if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & WIFI_ASOC_STATE)) { - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid); - RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress)); - - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); - for (i = 0; i < 8; i++) { - if (pmlmeext->cur_wireless_mode & BIT(i)) { - switch (BIT(i)) { - case WIRELESS_11B: - RTW_PRINT_SEL(m, "%4s", "11B "); - break; - case WIRELESS_11G: - RTW_PRINT_SEL(m, "%4s", "11G "); - break; - case WIRELESS_11A: - RTW_PRINT_SEL(m, "%4s", "11A "); - break; - case WIRELESS_11_24N: - RTW_PRINT_SEL(m, "%7s", "11_24N "); - break; - case WIRELESS_11_5N: - RTW_PRINT_SEL(m, "%6s", "11_5N "); - break; - case WIRELESS_AUTO: - RTW_PRINT_SEL(m, "%5s", "AUTO "); - break; - case WIRELESS_11AC: - RTW_PRINT_SEL(m, "%5s", "11AC "); - break; - } - } - } - RTW_PRINT_SEL(m, "\n"); - - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); - switch (padapter->securitypriv.dot11PrivacyAlgrthm) { - case _NO_PRIVACY_: - RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY"); - break; - case _WEP40_: - RTW_PRINT_SEL(m, "%s\n", "WEP 40"); - break; - case _TKIP_: - RTW_PRINT_SEL(m, "%s\n", "TKIP"); - break; - case _TKIP_WTMIC_: - RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC"); - break; - case _AES_: - RTW_PRINT_SEL(m, "%s\n", "AES"); - break; - case _WEP104_: - RTW_PRINT_SEL(m, "%s\n", "WEP 104"); - break; -#if 0 /* no this setting */ - case _WEP_WPA_MIXED_: - RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed"); - break; + #endif - case _SMS4_: - RTW_PRINT_SEL(m, "%s\n", "SMS4"); - break; -#ifdef CONFIG_IEEE80211W - case _BIP_CMAC_128_: - RTW_PRINT_SEL(m, "%s\n", "BIP"); - break; -#endif /* CONFIG_IEEE80211W */ - } - RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->cur_channel); - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset"); - switch (pmlmeext->cur_ch_offset) { - case HAL_PRIME_CHNL_OFFSET_DONT_CARE: - RTW_PRINT_SEL(m, "%s\n", "N/A"); - break; - case HAL_PRIME_CHNL_OFFSET_LOWER: - RTW_PRINT_SEL(m, "%s\n", "Lower"); - break; - case HAL_PRIME_CHNL_OFFSET_UPPER: - RTW_PRINT_SEL(m, "%s\n", "Upper"); - break; - } +#endif - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); - switch (pmlmeext->cur_bwmode) { - case CHANNEL_WIDTH_20: - RTW_PRINT_SEL(m, "%s\n", "20MHz"); - break; - case CHANNEL_WIDTH_40: - RTW_PRINT_SEL(m, "%s\n", "40MHz"); - break; - case CHANNEL_WIDTH_80: - RTW_PRINT_SEL(m, "%s\n", "80MHz"); - break; - case CHANNEL_WIDTH_160: - RTW_PRINT_SEL(m, "%s\n", "160MHz"); - break; - case CHANNEL_WIDTH_80_80: - RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); - break; - } - } else - RTW_PRINT_SEL(m, "No association with AP/GO exists!\n"); +#ifdef CONFIG_WOWLAN +int proc_get_wow_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *registry_pair = &padapter->registrypriv; + RTW_PRINT_SEL(m, "wow - %s\n", (registry_pair->wowlan_enable)? "enable" : "disable"); return 0; } -static int proc_tdls_display_tdls_sta_info(struct seq_file *m) +ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *registry_pair = &padapter->registrypriv; + char tmp[8]; + int num = 0; + int mode = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%d", &mode); + else + return -EFAULT; + + if (num != 1) { + RTW_ERR("%s: %s - invalid parameter!\n", __func__, tmp); + return -EINVAL; + } + + if (mode == 1) { + RTW_PRINT("%s: wowlan - enable\n", __func__); + } else if (mode == 0) { + RTW_PRINT("%s: wowlan - disable\n", __func__); + } else { + RTW_ERR("%s: %s - invalid parameter!, mode=%d\n", + __func__, tmp, mode); + return -EINVAL; + } + + registry_pair->wowlan_enable = mode; + + return count; +} + +int proc_get_pattern_info(struct seq_file *m, void *v) { +// TODO(jw.hou): Get pattern info from PHL. +#if 0 struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_priv *pstapriv = &padapter->stapriv; - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *psta; - int i = 0, j = 0; - _irqL irqL; - _list *plist, *phead; - u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; - u8 SpaceBtwnItemAndValueTmp = 0; - u8 NumOfTdlsStaToShow = 0; - BOOLEAN FirstMatchFound = _FALSE; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 val8; + char str_1[128]; + char *p_str; + int i = 0 , j = 0, k = 0; + int len = 0, max_len = 0, total = 0; - /* Search for TDLS sta info to display */ - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (i = 0; i < NUM_STA; i++) { - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); - if (psta->tdls_sta_state != TDLS_STATE_NONE) { - /* We got one TDLS sta info to show */ - RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow); - RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr)); - RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State"); - SpaceBtwnItemAndValueTmp = 0; - FirstMatchFound = _FALSE; - for (j = 0; j < 32; j++) { - if (psta->tdls_sta_state & BIT(j)) { - if (FirstMatchFound == _FALSE) { - SpaceBtwnItemAndValueTmp = 1; - FirstMatchFound = _TRUE; - } else - SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; - switch (BIT(j)) { - case TDLS_INITIATOR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); - break; - case TDLS_RESPONDER_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); - break; - case TDLS_LINKED_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); - break; - case TDLS_WAIT_PTR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); - break; - case TDLS_ALIVE_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); - break; - case TDLS_CH_SWITCH_ON_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); - break; - case TDLS_PEER_AT_OFF_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); - break; - case TDLS_CH_SW_INITIATOR_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); - break; - case TDLS_WAIT_CH_RSP_STATE: - RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); - break; - default: - RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); - break; - } - } - } + p_str = str_1; + max_len = sizeof(str_1); - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); - for (j = 0; j < 8; j++) { - if (psta->wireless_mode & BIT(j)) { - switch (BIT(j)) { - case WIRELESS_11B: - RTW_PRINT_SEL(m, "%4s", "11B "); - break; - case WIRELESS_11G: - RTW_PRINT_SEL(m, "%4s", "11G "); - break; - case WIRELESS_11A: - RTW_PRINT_SEL(m, "%4s", "11A "); - break; - case WIRELESS_11_24N: - RTW_PRINT_SEL(m, "%7s", "11_24N "); - break; - case WIRELESS_11_5N: - RTW_PRINT_SEL(m, "%6s", "11_5N "); - break; - case WIRELESS_AUTO: - RTW_PRINT_SEL(m, "%5s", "AUTO "); - break; - case WIRELESS_11AC: - RTW_PRINT_SEL(m, "%5s", "11AC "); - break; - } - } - } - RTW_PRINT_SEL(m, "\n"); + total = pwrpriv->wowlan_pattern_idx; - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); - switch (psta->cmn.bw_mode) { - case CHANNEL_WIDTH_20: - RTW_PRINT_SEL(m, "%s\n", "20MHz"); - break; - case CHANNEL_WIDTH_40: - RTW_PRINT_SEL(m, "%s\n", "40MHz"); - break; - case CHANNEL_WIDTH_80: - RTW_PRINT_SEL(m, "%s\n", "80MHz"); - break; - case CHANNEL_WIDTH_160: - RTW_PRINT_SEL(m, "%s\n", "160MHz"); - break; - case CHANNEL_WIDTH_80_80: - RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); - break; - case CHANNEL_WIDTH_5: - RTW_PRINT_SEL(m, "%s\n", "5MHz"); - break; - case CHANNEL_WIDTH_10: - RTW_PRINT_SEL(m, "%s\n", "10MHz"); - break; - default: - RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid"); - break; - } + rtw_set_default_pattern(padapter); - RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); - switch (psta->dot118021XPrivacy) { - case _NO_PRIVACY_: - RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY"); - break; - case _WEP40_: - RTW_PRINT_SEL(m, "%s\n", "WEP 40"); - break; - case _TKIP_: - RTW_PRINT_SEL(m, "%s\n", "TKIP"); - break; - case _TKIP_WTMIC_: - RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC"); - break; - case _AES_: - RTW_PRINT_SEL(m, "%s\n", "AES"); - break; - case _WEP104_: - RTW_PRINT_SEL(m, "%s\n", "WEP 104"); - break; -#if 0 /* no this setting */ - case _WEP_WPA_MIXED_: - RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed"); - break; -#endif - case _SMS4_: - RTW_PRINT_SEL(m, "%s\n", "SMS4"); - break; -#ifdef CONFIG_IEEE80211W - case _BIP_CMAC_128_: - RTW_PRINT_SEL(m, "%s\n", "BIP"); - break; -#endif /* CONFIG_IEEE80211W */ - } + /*show pattern*/ + RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n"); + RTW_PRINT_SEL(m, "pattern number: %d\n", total); + RTW_PRINT_SEL(m, "support default patterns: %c\n", + (pwrpriv->default_patterns_en) ? 'Y' : 'N'); + + for (k = 0; k < total ; k++) { + RTW_PRINT_SEL(m, "\npattern idx: %d\n", k); + RTW_PRINT_SEL(m, "pattern content:\n"); - RTW_PRINT_SEL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime); - RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts); - RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts); + p_str = str_1; + max_len = sizeof(str_1); + for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { + _rtw_memset(p_str, 0, max_len); + len = 0; + for (j = 0 ; j < 8 ; j++) { + val8 = pwrpriv->patterns[k].content[i * 8 + j]; + len += snprintf(p_str + len, max_len - len, + "%02x ", val8); } + RTW_PRINT_SEL(m, "%s\n", p_str); } + RTW_PRINT_SEL(m, "\npattern mask:\n"); + for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { + _rtw_memset(p_str, 0, max_len); + len = 0; + for (j = 0 ; j < 8 ; j++) { + val8 = pwrpriv->patterns[k].mask[i * 8 + j]; + len += snprintf(p_str + len, max_len - len, + "%02x ", val8); + } + RTW_PRINT_SEL(m, "%s\n", p_str); + } + + RTW_PRINT_SEL(m, "\npriv_pattern_len:\n"); + RTW_PRINT_SEL(m, "pattern_len: %d\n", pwrpriv->patterns[k].len); + RTW_PRINT_SEL(m, "*****************\n"); } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - if (NumOfTdlsStaToShow == 0) { - RTW_PRINT_SEL(m, "============[TDLS Peer STA Info]============\n"); - RTW_PRINT_SEL(m, "No TDLS direct link exists!\n"); - } +#endif return 0; } -int proc_get_tdls_info(struct seq_file *m, void *v) +ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *registry_par = &adapter->registrypriv; + struct rtw_wowcam_upd_info wowcam_info = {0}; + u8 tmp[MAX_WKFM_PATTERN_STR_LEN + 1] = {0}; + + if (!(registry_par->wakeup_event & BIT(3))) { + RTW_INFO("%s: customized pattern disabled, wakeup_event: %#2x\n", + __func__, registry_par->wakeup_event); + return -EOPNOTSUPP; + } + + if (count < 1) + return -EINVAL; + + if (count >= sizeof(tmp)) { + RTW_ERR("%s: pattern string is too long, count=%zu\n", + __func__, count); + return -EINVAL; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + if (strncmp(tmp, "clean", 5) == 0) { + rtw_wow_pattern_clean(adapter, RTW_CUSTOMIZED_PATTERN); + } else { + if (rtw_wowlan_parser_pattern_cmd(tmp, + wowcam_info.ptrn, + &wowcam_info.ptrn_len, + wowcam_info.mask)) { + if (_FAIL == rtw_wow_pattern_set(adapter, + &wowcam_info, + RTW_CUSTOMIZED_PATTERN)) + return -EFAULT; + } else { + return -EINVAL; + } + } + } else { + rtw_warn_on(1); + return -EFAULT; + } + + return count; +} + +int proc_get_wakeup_event(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct sta_priv *pstapriv = &padapter->stapriv; - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *psta; - int i = 0, j = 0; - _irqL irqL; - _list *plist, *phead; - u8 SpaceBtwnItemAndValue = 41; - u8 SpaceBtwnItemAndValueTmp = 0; - u8 NumOfTdlsStaToShow = 0; - BOOLEAN FirstMatchFound = _FALSE; + struct registry_priv *registry_par = &padapter->registrypriv; - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { - RTW_PRINT_SEL(m, "No tdls info can be shown since hal doesn't support tdls\n"); - return 0; + RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event); + return 0; +} + +ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + u32 wakeup_event = 0; + + u8 tmp[8] = {0}; + int num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - proc_tdls_display_tdls_function_info(m); - proc_tdls_display_network_info(m); - proc_tdls_display_tdls_sta_info(m); + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%u", &wakeup_event); + else + return -EFAULT; - return 0; + if (num == 1 && wakeup_event <= 0x1f) { + registry_par->wakeup_event = wakeup_event; + + if (!(wakeup_event & BIT(1))) + rtw_wow_pattern_clean(padapter, RTW_DEFAULT_PATTERN); + + if (!(wakeup_event & BIT(3))) + rtw_wow_pattern_clean(padapter, RTW_CUSTOMIZED_PATTERN); + + RTW_INFO("%s: wakeup_event: %#2x\n", + __func__, registry_par->wakeup_event); + } else { + return -EINVAL; + } + + return count; } -#endif -int proc_get_monitor(struct seq_file *m, void *v) +int proc_get_wakeup_reason(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 val = pwrpriv->wowlan_last_wake_reason; - if (MLME_IS_MONITOR(padapter)) { - RTW_PRINT_SEL(m, "Monitor mode : Enable\n"); - RTW_PRINT_SEL(m, "Device type : %u\n", dev->type); + RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val); + return 0; +} +#endif /*CONFIG_WOWLAN*/ - RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n", - rtw_get_oper_ch(padapter), - rtw_get_oper_choffset(padapter), - rtw_get_oper_bw(padapter)); - } else - RTW_PRINT_SEL(m, "Monitor mode : Disable\n"); +#ifdef CONFIG_GPIO_WAKEUP +int proc_get_wowlan_gpio_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wow_priv *wowpriv = adapter_to_wowlan(padapter); + struct rtw_wow_gpio_info *wow_gpio = &wowpriv->wow_gpio; + + RTW_PRINT_SEL(m, "wakeup_gpio_idx: %d\n", WAKEUP_GPIO_IDX); + RTW_PRINT_SEL(m, "high_active: %d\n", wow_gpio->gpio_active); return 0; } -ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) { - char tmp[32]; struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u16 target_type; - u8 target_ch, target_offset, target_bw; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + void *phl = GET_PHL_INFO(dvobj); + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct wow_priv *wowpriv = adapter_to_wowlan(padapter); + struct rtw_wow_gpio_info *wow_gpio = &wowpriv->wow_gpio; + char tmp[32] = {0}; + int num = 0; + u32 is_high_active = 0; - if (count < 3) { - RTW_INFO("argument size is less than 3\n"); + if (count < 1) return -EFAULT; - } if (count > sizeof(tmp)) { rtw_warn_on(1); @@ -6702,996 +4839,1249 @@ ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t co } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = 0; - num = sscanf(tmp, "type %hu", &target_type); - if ((num == 1) && - ((target_type != ARPHRD_IEEE80211) && - (target_type != ARPHRD_IEEE80211_RADIOTAP))) { - dev->type = ARPHRD_IEEE80211_RADIOTAP; - return count; - } + num = sscanf(tmp, "%u", &is_high_active); - num = sscanf(tmp, "%hhu %hhu %hhu", &target_ch, &target_offset, &target_bw); - if (num != 3) { - RTW_INFO("invalid write_reg parameter!\n"); + if (num != 1) { + RTW_INFO("Invalid format\n"); return count; } - padapter->mlmeextpriv.cur_channel = target_ch; - set_channel_bwmode(padapter, target_ch, target_offset, target_bw); + wow_gpio->dev2hst_high = is_high_active == 0 ? 1 : 0; + wow_gpio->gpio_active = is_high_active; + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + status = rtw_phl_cfg_wow_sw_gpio_ctrl(phl, wow_gpio); + + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + RTW_INFO("set %s %d\n", "gpio_high_active", + wow_gpio->gpio_active); + RTW_INFO("%s: set GPIO_%d %d as default. status=%d\n", + __func__, WAKEUP_GPIO_IDX, wow_gpio->dev2hst_high, status); } return count; } +#endif /* CONFIG_GPIO_WAKEUP */ + +#ifdef CONFIG_P2P_WOWLAN +int proc_get_p2p_wowlan_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct p2p_wowlan_info peerinfo = pwdinfo->p2p_wow_info; + if (_TRUE == peerinfo.is_trigger) { + RTW_PRINT_SEL(m, "is_trigger: TRUE\n"); + switch (peerinfo.wowlan_recv_frame_type) { + case P2P_WOWLAN_RECV_NEGO_REQ: + RTW_PRINT_SEL(m, "Frame Type: Nego Request\n"); + break; + case P2P_WOWLAN_RECV_INVITE_REQ: + RTW_PRINT_SEL(m, "Frame Type: Invitation Request\n"); + break; + case P2P_WOWLAN_RECV_PROVISION_REQ: + RTW_PRINT_SEL(m, "Frame Type: Provision Request\n"); + break; + default: + break; + } + RTW_PRINT_SEL(m, "Peer Addr: "MAC_FMT"\n", MAC_ARG(peerinfo.wowlan_peer_addr)); + RTW_PRINT_SEL(m, "Peer WPS Config: %x\n", peerinfo.wowlan_peer_wpsconfig); + RTW_PRINT_SEL(m, "Persistent Group: %d\n", peerinfo.wowlan_peer_is_persistent); + RTW_PRINT_SEL(m, "Intivation Type: %d\n", peerinfo.wowlan_peer_invitation_type); + } else + RTW_PRINT_SEL(m, "is_trigger: False\n"); + return 0; +} +#endif /* CONFIG_P2P_WOWLAN */ +#ifdef CONFIG_POWER_SAVING +int proc_get_ps_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 ips_mode = pwrpriv->ips_mode_req; + u8 lps_mode = pwrpriv->power_mgnt; + u8 lps_level = pwrpriv->lps_level; +#ifdef CONFIG_LPS_1T1R + u8 lps_1t1r = pwrpriv->lps_1t1r; +#endif +#ifdef CONFIG_WOWLAN + u8 wow_lps_mode = pwrpriv->wowlan_power_mgmt; + u8 wow_lps_level = pwrpriv->wowlan_lps_level; + #ifdef CONFIG_LPS_1T1R + u8 wow_lps_1t1r = pwrpriv->wowlan_lps_1t1r; + #endif +#endif /* CONFIG_WOWLAN */ + char *str = ""; + + RTW_PRINT_SEL(m, "======Power Saving Info:======\n"); + RTW_PRINT_SEL(m, "*IPS:\n"); + + if (ips_mode == IPS_NORMAL) { +#ifdef CONFIG_FWLPS_IN_IPS + str = "FW_LPS_IN_IPS"; +#else + str = "Card Disable"; +#endif + } else if (ips_mode == IPS_NONE) + str = "NO IPS"; + else if (ips_mode == IPS_LEVEL_2) + str = "IPS_LEVEL_2"; + else + str = "invalid ips_mode"; + + RTW_PRINT_SEL(m, " IPS mode: %s\n", str); + RTW_PRINT_SEL(m, " IPS enter count:%d, IPS leave count:%d\n", + pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts); + RTW_PRINT_SEL(m, "------------------------------\n"); + RTW_PRINT_SEL(m, "*LPS:\n"); -#ifdef RTW_SIMPLE_CONFIG -/* For RtwSimleConfig */ -int proc_get_simple_config(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + if (lps_mode == PM_PS_MODE_ACTIVE) + str = "NO LPS"; + else if (lps_mode == PM_PS_MODE_MIN) + str = "MIN"; + else if (lps_mode == PM_PS_MODE_MAX) + str = "MAX"; + else if (lps_mode == PM_PS_MODE_DTIM) + str = "DTIM"; + else + sprintf(str, "%d", lps_mode); - RTW_PRINT_SEL(m, "RTW Simple Config : %s\n", padapter->rtw_simple_config ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, " LPS mode: %s\n", str); - return 0; -} + if (pwrpriv->dtim != 0) + RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim); + RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n", + pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts); -ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - char tmp[32]; - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 ret; + if (lps_level == LPS_LCLK) + str = "LPS_LCLK"; + else if (lps_level == LPS_PG) + str = "LPS_PG"; + else + str = "LPS_NORMAL"; + RTW_PRINT_SEL(m, " LPS level: %s\n", str); - if (count < 1) { - RTW_INFO("argument size is less than 1\n"); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } +#ifdef CONFIG_LPS_1T1R + RTW_PRINT_SEL(m, " LPS 1T1R: %d\n", lps_1t1r); +#endif - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhd", &ret); +#ifdef CONFIG_WOWLAN + RTW_PRINT_SEL(m, "------------------------------\n"); + RTW_PRINT_SEL(m, "*WOW LPS:\n"); - padapter->rtw_simple_config = ret ? _TRUE : _FALSE; - } + if (wow_lps_mode == PM_PS_MODE_ACTIVE) + str = "NO LPS"; + else if (wow_lps_mode == PM_PS_MODE_MIN) + str = "MIN"; + else if (wow_lps_mode == PM_PS_MODE_MAX) + str = "MAX"; + else if (wow_lps_mode == PM_PS_MODE_DTIM) + str = "DTIM"; + else + sprintf(str, "%d", wow_lps_mode); - return count; -} -#endif + RTW_PRINT_SEL(m, " WOW LPS mode: %s\n", str); -#ifdef DBG_XMIT_BLOCK -int proc_get_xmit_block(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + if (wow_lps_level == LPS_LCLK) + str = "LPS_LCLK"; + else if (wow_lps_level == LPS_PG) + str = "LPS_PG"; + else + str = "LPS_NORMAL"; + RTW_PRINT_SEL(m, " WOW LPS level: %s\n", str); - dump_xmit_block(m, padapter); + #ifdef CONFIG_LPS_1T1R + RTW_PRINT_SEL(m, " WOW LPS 1T1R: %d\n", wow_lps_1t1r); + #endif +#endif /* CONFIG_WOWLAN */ + RTW_PRINT_SEL(m, "=============================\n"); return 0; } -ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 xb_mode, xb_reason; - - if (count < 1) - return -EFAULT; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[8]; + int num = 0; + int mode = 0; + int en = 0; if (count > sizeof(tmp)) { rtw_warn_on(1); return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason); - - if (num != 2) { - RTW_INFO("invalid parameter!\n"); - return count; - } + if (!buffer || copy_from_user(tmp, buffer, count)) + goto exit; - if (xb_mode == 0)/*set*/ - rtw_set_xmit_block(padapter, xb_reason); - else if (xb_mode == 1)/*clear*/ - rtw_clr_xmit_block(padapter, xb_reason); - else - RTW_INFO("invalid parameter!\n"); + num = sscanf(tmp, "%d %d", &mode, &en); + if (num > 2) { + RTW_ERR("%s: invalid parameter!\n", __FUNCTION__); + goto exit; } - return count; -} -#endif + if (num == 1 && mode == 0) { + /* back to original LPS/IPS Mode */ + RTW_INFO("%s: back to original LPS/IPS Mode\n", __FUNCTION__); -#include -int proc_get_efuse_map(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; - int i, j; - u8 ips_mode = IPS_NUM; - u16 mapLen; + rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt); + + rtw_pm_set_ips(adapter, adapter->registrypriv.ips_mode); - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); - if (mapLen > EFUSE_MAX_MAP_LEN) - mapLen = EFUSE_MAX_MAP_LEN; +#ifdef CONFIG_WOWLAN + RTW_INFO("%s: back to original WOW LPS Mode\n", __FUNCTION__); - ips_mode = pwrctrlpriv->ips_mode; - rtw_pm_set_ips(padapter, IPS_NONE); -#ifdef CONFIG_EFUSE_CONFIG_FILE - if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) { - RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH); - if (pHalData->bautoload_fail_flag) - RTW_PRINT_SEL(m, "File Autoload fail!!!\n"); - } else if (pHalData->efuse_file_status == EFUSE_FILE_FAILED) { - RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH); - if (pHalData->bautoload_fail_flag) - RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); - } else -#endif + rtw_pm_set_wow_lps(adapter, adapter->registrypriv.wow_power_mgnt); +#endif /* CONFIG_WOWLAN */ - { - RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n"); - if (pHalData->bautoload_fail_flag) - RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); - } - for (i = 0; i < mapLen; i += 16) { - RTW_PRINT_SEL(m, "0x%02x\t", i); - for (j = 0; j < 8; j++) - RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]); - RTW_PRINT_SEL(m, "\t"); - for (; j < 16; j++) - RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]); - RTW_PRINT_SEL(m, "\n"); + goto exit; } - - if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) { - RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n"); - return 0; + + if (mode == 1) { + /* LPS */ + RTW_INFO("%s: LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); + if (rtw_pm_set_lps(adapter, en) != 0 ) + RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); + + } else if (mode == 2) { + /* IPS */ + RTW_INFO("%s: IPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); + if (rtw_pm_set_ips(adapter, en) != 0 ) + RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); } - - RTW_PRINT_SEL(m, "\n"); - RTW_PRINT_SEL(m, "HW eFuse Map\n"); - for (i = 0; i < mapLen; i += 16) { - RTW_PRINT_SEL(m, "0x%02x\t", i); - for (j = 0; j < 8; j++) - RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); - RTW_PRINT_SEL(m, "\t"); - for (; j < 16; j++) - RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); - RTW_PRINT_SEL(m, "\n"); +#ifdef CONFIG_WOWLAN + else if (mode == 3) { + /* WOW LPS */ + RTW_INFO("%s: WOW LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en); + if (rtw_pm_set_wow_lps(adapter, en) != 0 ) + RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en); } +#endif /* CONFIG_WOWLAN */ + else + RTW_ERR("%s: invalid parameter, mode = %d!\n", __FUNCTION__, mode); - rtw_pm_set_ips(padapter, ips_mode); - - return 0; +exit: + return count; } -ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +#ifdef CONFIG_WMMPS_STA +int proc_get_wmmps_info(struct seq_file *m, void *v) { -#if 0 - char tmp[256] = {0}; - u32 addr, cnts; - u8 efuse_data; - - int jj, kk; - - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - u8 ips_mode = IPS_NUM; - - if (count < 3) { - RTW_INFO("argument size is less than 3\n"); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data); + struct registry_priv *pregpriv = &padapter->registrypriv; + char *uapsd_max_sp_str=""; - if (num != 3) { - RTW_INFO("invalid write_reg parameter!\n"); - return count; + if (pregpriv){ + switch(pregpriv->uapsd_max_sp_len) { + case 0: + uapsd_max_sp_str = "NO_LIMIT"; + break; + case 1: + uapsd_max_sp_str = "TWO_MSDU"; + break; + case 2: + uapsd_max_sp_str = "FOUR_MSDU"; + break; + case 3: + uapsd_max_sp_str = "SIX_MSDU"; + break; + default: + uapsd_max_sp_str = "UNSPECIFIED"; + break; } + + RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n"); + RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str); + RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable); + RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "============================\n"); } - ips_mode = pwrctrlpriv->ips_mode; - rtw_pm_set_ips(padapter, IPS_NONE); - if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL) - RTW_INFO("WARN - rtw_efuse_map_write error!!\n"); - rtw_pm_set_ips(padapter, ips_mode); -#endif - return count; + + return 0; } -#ifdef CONFIG_IEEE80211W -ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct sta_info *psta; - _list *plist, *phead; - _irqL irqL; - char tmp[16]; - u8 mac_addr[NUM_STA][ETH_ALEN]; - u32 key_type; - u8 index; + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u8 uapsd_ac_setting; + u8 uapsd_max_sp_len_setting; - if (count > 2) { - RTW_INFO("argument size is more than 2\n"); + if (count < 1) return -EFAULT; - } - if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { - - int num = sscanf(tmp, "%x", &key_type); - - if (num != 1) { - RTW_INFO("invalid read_reg parameter!\n"); - return count; - } - RTW_INFO("0: set sa query request , key_type=%d\n", key_type); + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; } - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { - RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); - /* TX unicast sa_query to AP */ - issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { - /* TX unicast sa_query to every client STA */ - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (index = 0; index < NUM_STA; index++) { - psta = NULL; + if (buffer && !copy_from_user(tmp, buffer, count)) { - phead = &(pstapriv->sta_hash[index]); - plist = get_next(phead); + int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); + if (pregpriv) { + if (num >= 1) { + pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting; + RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len); } - } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) { - if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) { - if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN) - && !IS_MCAST(&mac_addr[index][0])) { - issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type); - RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); - } + if (num >= 2) { + pregpriv->uapsd_ac_enable = uapsd_ac_setting; + RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable); } } } return count; } +#endif /* CONFIG_WMMPS_STA */ +#endif /* CONFIG_POWER_SAVING */ -int proc_get_tx_sa_query(struct seq_file *m, void *v) +#ifdef CONFIG_TDLS +int proc_get_tdls_enable(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled"); - RTW_PRINT_SEL(m, "%s\n", __func__); return 0; } -ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct sta_info *psta; - _list *plist, *phead; - _irqL irqL; - char tmp[16]; - u8 mac_addr[NUM_STA][ETH_ALEN]; - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - u32 key_type = 0; - u8 index; + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 en_tdls = 0; + if (count < 1) + return -EFAULT; - if (count > 2) { - RTW_INFO("argument size is more than 2\n"); + if (count > sizeof(tmp)) { + rtw_warn_on(1); return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { + if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%x", &key_type); + int num = sscanf(tmp, "%d ", &en_tdls); - if (num != 1) { - RTW_INFO("invalid read_reg parameter!\n"); - return count; + if (num == 1 && pregpriv) { + if (en_tdls > 0) + rtw_enable_tdls_func(padapter); + else + rtw_disable_tdls_func(padapter, _TRUE); } - RTW_INFO("key_type=%d\n", key_type); } - if (key_type < 0 || key_type > 4) - return count; - - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { - if (key_type == 3) /* key_type 3 only for AP mode */ - return count; - /* TX unicast deauth to AP */ - issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type); -#ifdef CONFIG_AP_MODE - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { - u8 updated = _FALSE; - if (key_type == 3) - issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY); + return count; +} - /* TX unicast deauth to every client STA */ - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (index = 0; index < NUM_STA; index++) { - psta = NULL; +static int proc_tdls_display_tdls_function_info(struct seq_file *m) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + u8 SpaceBtwnItemAndValueTmp = 0; + BOOLEAN FirstMatchFound = _FALSE; + int j = 0; - phead = &(pstapriv->sta_hash[index]); - plist = get_next(phead); + RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE"); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); +#ifdef CONFIG_TDLS_CH_SW + RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State"); + if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE) + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE"); + else { + for (j = 0; j < 32; j++) { + if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) { + if (FirstMatchFound == _FALSE) { + SpaceBtwnItemAndValueTmp = 1; + FirstMatchFound = _TRUE; + } else + SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; + switch (BIT(j)) { + case TDLS_INITIATOR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); + break; + case TDLS_RESPONDER_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); + break; + case TDLS_LINKED_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); + break; + case TDLS_WAIT_PTR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); + break; + case TDLS_ALIVE_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); + break; + case TDLS_CH_SWITCH_ON_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); + break; + case TDLS_PEER_AT_OFF_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); + break; + case TDLS_CH_SW_INITIATOR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); + break; + case TDLS_WAIT_CH_RSP_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); + break; + default: + RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); + break; + } } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + } - for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) { - if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) { - if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) { - if (key_type != 3) - issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num); + RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset); + RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack); +#endif - psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]); - if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) { - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { - rtw_list_delete(&psta->asoc_list); - pstapriv->asoc_list_cnt--; - #ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (psta->tbtx_enable) - pstapriv->tbtx_asoc_list_cnt--; - #endif - updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE"); - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - } + return 0; +} - RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); +static int proc_tdls_display_network_info(struct seq_file *m) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + int i = 0; + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + + /* Display the linked AP/GO info */ + RTW_PRINT_SEL(m, "============[Associated AP/GO Info]============\n"); + + if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & WIFI_ASOC_STATE)) { + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid); + RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress)); + + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); + for (i = 0; i < 8; i++) { + if (pmlmeext->cur_wireless_mode & BIT(i)) { + switch (BIT(i)) { + case WIRELESS_11B: + RTW_PRINT_SEL(m, "%4s", "11B "); + break; + case WIRELESS_11G: + RTW_PRINT_SEL(m, "%4s", "11G "); + break; + case WIRELESS_11A: + RTW_PRINT_SEL(m, "%4s", "11A "); + break; + case WIRELESS_11_24N: + RTW_PRINT_SEL(m, "%7s", "11_24N "); + break; + case WIRELESS_11_5N: + RTW_PRINT_SEL(m, "%6s", "11_5N "); + break; + case WIRELESS_AUTO: + RTW_PRINT_SEL(m, "%5s", "AUTO "); + break; + case WIRELESS_11AC: + RTW_PRINT_SEL(m, "%5s", "11AC "); + break; } } } + RTW_PRINT_SEL(m, "\n"); - associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); -#endif /* CONFIG_AP_MODE */ - } + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); + switch (padapter->securitypriv.dot11PrivacyAlgrthm) { + case _NO_PRIVACY_: + RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY"); + break; + case _WEP40_: + RTW_PRINT_SEL(m, "%s\n", "WEP 40"); + break; + case _TKIP_: + RTW_PRINT_SEL(m, "%s\n", "TKIP"); + break; + case _TKIP_WTMIC_: + RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC"); + break; + case _AES_: + RTW_PRINT_SEL(m, "%s\n", "AES"); + break; + case _WEP104_: + RTW_PRINT_SEL(m, "%s\n", "WEP 104"); + break; +#if 0 /* no this setting */ + case _WEP_WPA_MIXED_: + RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed"); + break; +#endif + case _SMS4_: + RTW_PRINT_SEL(m, "%s\n", "SMS4"); + break; +#ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + RTW_PRINT_SEL(m, "%s\n", "BIP"); + break; +#endif /* CONFIG_IEEE80211W */ + } - return count; -} + RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->chandef.chan); + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset"); + switch (pmlmeext->chandef.offset) { + case CHAN_OFFSET_NO_EXT: + RTW_PRINT_SEL(m, "%s\n", "SCN"); + break; + case CHAN_OFFSET_UPPER: + RTW_PRINT_SEL(m, "%s\n", "SCA"); + break; + case CHAN_OFFSET_LOWER: + RTW_PRINT_SEL(m, "%s\n", "SCB"); + break; + } -int proc_get_tx_deauth(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); + switch (pmlmeext->chandef.bw) { + case CHANNEL_WIDTH_20: + RTW_PRINT_SEL(m, "%s\n", "20MHz"); + break; + case CHANNEL_WIDTH_40: + RTW_PRINT_SEL(m, "%s\n", "40MHz"); + break; + case CHANNEL_WIDTH_80: + RTW_PRINT_SEL(m, "%s\n", "80MHz"); + break; + case CHANNEL_WIDTH_160: + RTW_PRINT_SEL(m, "%s\n", "160MHz"); + break; + case CHANNEL_WIDTH_80_80: + RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); + break; + } + } else + RTW_PRINT_SEL(m, "No association with AP/GO exists!\n"); - RTW_PRINT_SEL(m, "%s\n", __func__); return 0; } -ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_tdls_display_tdls_sta_info(struct seq_file *m) { - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct sta_info *psta; + int i = 0, j = 0; _list *plist, *phead; - _irqL irqL; - char tmp[16]; - u8 mac_addr[NUM_STA][ETH_ALEN]; - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - u32 tx_auth; - u8 index; - + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + u8 SpaceBtwnItemAndValueTmp = 0; + u8 NumOfTdlsStaToShow = 0; + BOOLEAN FirstMatchFound = _FALSE; - if (count > 2) { - RTW_INFO("argument size is more than 2\n"); - return -EFAULT; - } + /* Search for TDLS sta info to display */ + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if (psta->tdls_sta_state != TDLS_STATE_NONE) { + /* We got one TDLS sta info to show */ + RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow); + RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State"); + SpaceBtwnItemAndValueTmp = 0; + FirstMatchFound = _FALSE; + for (j = 0; j < 32; j++) { + if (psta->tdls_sta_state & BIT(j)) { + if (FirstMatchFound == _FALSE) { + SpaceBtwnItemAndValueTmp = 1; + FirstMatchFound = _TRUE; + } else + SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; + switch (BIT(j)) { + case TDLS_INITIATOR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); + break; + case TDLS_RESPONDER_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); + break; + case TDLS_LINKED_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); + break; + case TDLS_WAIT_PTR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); + break; + case TDLS_ALIVE_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); + break; + case TDLS_CH_SWITCH_ON_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); + break; + case TDLS_PEER_AT_OFF_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); + break; + case TDLS_CH_SW_INITIATOR_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); + break; + case TDLS_WAIT_CH_RSP_STATE: + RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); + break; + default: + RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); + break; + } + } + } - if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); + for (j = 0; j < 8; j++) { + if (psta->phl_sta->wmode & BIT(j)) { + switch (BIT(j)) { + case WIRELESS_11B: + RTW_PRINT_SEL(m, "%4s", "11B "); + break; + case WIRELESS_11G: + RTW_PRINT_SEL(m, "%4s", "11G "); + break; + case WIRELESS_11A: + RTW_PRINT_SEL(m, "%4s", "11A "); + break; + case WIRELESS_11_24N: + RTW_PRINT_SEL(m, "%7s", "11_24N "); + break; + case WIRELESS_11_5N: + RTW_PRINT_SEL(m, "%6s", "11_5N "); + break; + case WIRELESS_AUTO: + RTW_PRINT_SEL(m, "%5s", "AUTO "); + break; + case WIRELESS_11AC: + RTW_PRINT_SEL(m, "%5s", "11AC "); + break; + } + } + } + RTW_PRINT_SEL(m, "\n"); - int num = sscanf(tmp, "%x", &tx_auth); + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); + switch (psta->phl_sta->chandef.bw) { + case CHANNEL_WIDTH_20: + RTW_PRINT_SEL(m, "%s\n", "20MHz"); + break; + case CHANNEL_WIDTH_40: + RTW_PRINT_SEL(m, "%s\n", "40MHz"); + break; + case CHANNEL_WIDTH_80: + RTW_PRINT_SEL(m, "%s\n", "80MHz"); + break; + case CHANNEL_WIDTH_160: + RTW_PRINT_SEL(m, "%s\n", "160MHz"); + break; + case CHANNEL_WIDTH_80_80: + RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); + break; + case CHANNEL_WIDTH_5: + RTW_PRINT_SEL(m, "%s\n", "5MHz"); + break; + case CHANNEL_WIDTH_10: + RTW_PRINT_SEL(m, "%s\n", "10MHz"); + break; + default: + RTW_PRINT_SEL(m, "(%d)%s\n", psta->phl_sta->chandef.bw, "invalid"); + break; + } - if (num != 1) { - RTW_INFO("invalid read_reg parameter!\n"); - return count; - } - RTW_INFO("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth); - } + RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); + switch (psta->dot118021XPrivacy) { + case _NO_PRIVACY_: + RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY"); + break; + case _WEP40_: + RTW_PRINT_SEL(m, "%s\n", "WEP 40"); + break; + case _TKIP_: + RTW_PRINT_SEL(m, "%s\n", "TKIP"); + break; + case _TKIP_WTMIC_: + RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC"); + break; + case _AES_: + RTW_PRINT_SEL(m, "%s\n", "AES"); + break; + case _WEP104_: + RTW_PRINT_SEL(m, "%s\n", "WEP 104"); + break; +#if 0 /* no this setting */ + case _WEP_WPA_MIXED_: + RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed"); + break; +#endif + case _SMS4_: + RTW_PRINT_SEL(m, "%s\n", "SMS4"); + break; +#ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + RTW_PRINT_SEL(m, "%s\n", "BIP"); + break; +#endif /* CONFIG_IEEE80211W */ + } - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { - if (tx_auth == 1) { - /* TX unicast auth to AP */ - issue_auth(padapter, NULL, 0); - } else if (tx_auth == 2) { - /* TX unicast auth to AP */ - issue_assocreq(padapter); + RTW_PRINT_SEL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime); + RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts); + RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts); + } } } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); + if (NumOfTdlsStaToShow == 0) { + RTW_PRINT_SEL(m, "============[TDLS Peer STA Info]============\n"); + RTW_PRINT_SEL(m, "No TDLS direct link exists!\n"); + } - return count; -} - -int proc_get_tx_auth(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "%s\n", __func__); return 0; } -#endif /* CONFIG_IEEE80211W */ -#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA -static u32 phase_idx; -int proc_get_pathb_phase(struct seq_file *m, void *v) +int proc_get_tdls_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_info *psta; + int i = 0, j = 0; + _list *plist, *phead; + u8 SpaceBtwnItemAndValue = 41; + u8 SpaceBtwnItemAndValueTmp = 0; + u8 NumOfTdlsStaToShow = 0; + BOOLEAN FirstMatchFound = _FALSE; - RTW_PRINT_SEL(m, "PathB phase index =%d\n", phase_idx); - return 0; -} - -ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - int num; - u32 tmp_idx; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_TDLS) == _FALSE) { + RTW_PRINT_SEL(m, "No tdls info can be shown since hal doesn't support tdls\n"); + return 0; } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + proc_tdls_display_tdls_function_info(m); + proc_tdls_display_network_info(m); + proc_tdls_display_tdls_sta_info(m); - if (buffer && !copy_from_user(tmp, buffer, count)) { - num = sscanf(tmp, "%u", &tmp_idx); - if ((tmp_idx < 0) || (tmp_idx > 11)) { - RTW_INFO(FUNC_ADPT_FMT "Invalid input value\n", FUNC_ADPT_ARG(padapter)); - return count; - } - phase_idx = tmp_idx; - rtw_hal_set_pathb_phase(padapter, phase_idx); - } - return count; + return 0; } #endif -#ifdef CONFIG_MCC_MODE -int proc_get_mcc_info(struct seq_file *m, void *v) +int proc_get_monitor(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - dump_adapters_status(m, adapter_to_dvobj(adapter)); - rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter)); - return 0; -} + if (MLME_IS_MONITOR(padapter)) { + RTW_PRINT_SEL(m, "Monitor mode : Enable\n"); + RTW_PRINT_SEL(m, "Device type : %u\n", dev->type); -int proc_get_mcc_policy_table(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n", + rtw_get_oper_ch(padapter), + rtw_get_oper_choffset(padapter), + rtw_get_oper_bw(padapter)); + } else + RTW_PRINT_SEL(m, "Monitor mode : Disable\n"); - rtw_hal_dump_mcc_policy_table(m); return 0; } -ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { + char tmp[32]; struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 en_mcc = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + u16 target_type; + u8 target_ch, target_offset, target_bw; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count < 3) { + RTW_INFO("argument size is less than 3\n"); return -EFAULT; } if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - u8 i = 0; - int num = sscanf(tmp, "%u", &en_mcc); + int num = 0; - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + num = sscanf(tmp, "type %hu", &target_type); + if ((num == 1) && + ((target_type != ARPHRD_IEEE80211) && + (target_type != ARPHRD_IEEE80211_RADIOTAP))) { + dev->type = ARPHRD_IEEE80211_RADIOTAP; + return count; } - RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc); - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - iface->registrypriv.en_mcc = en_mcc; + num = sscanf(tmp, "%hhu %hhu %hhu", &target_ch, &target_offset, &target_bw); + if (num != 3) { + RTW_INFO("invalid write_reg parameter!\n"); + return count; } + + padapter->mlmeextpriv.chandef.chan = target_ch; + set_channel_bwmode(padapter, target_ch, target_offset, target_bw, _TRUE); } return count; } - -ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +#ifdef DBG_XMIT_BLOCK +int proc_get_xmit_block(struct seq_file *m, void *v) { - struct net_device *dev = data; + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 enable_runtime_duration = 0, mcc_duration = 0, type = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u %u %u", &enable_runtime_duration, &type, &mcc_duration); - - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - if (num > 3) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - if (num == 2) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - if (num >= 1) { - SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration); - RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable"); - } - if (num == 3) { - RTW_INFO("type:%d, mcc duration:%d\n", type, mcc_duration); - rtw_set_mcc_duration_cmd(padapter, type, mcc_duration); - } - } + dump_xmit_block(m, padapter); - return count; + return 0; } -#ifdef CONFIG_MCC_PHYDM_OFFLOAD -ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_phydm_enable = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + char tmp[32]; + u8 xb_mode, xb_reason; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count < 1) return -EFAULT; - } if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - u8 i = 0; - int num = sscanf(tmp, "%u", &mcc_phydm_enable); - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason); + + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; } - RTW_INFO("%s: mcc phydm enable = %d\n", __func__, mcc_phydm_enable); - rtw_set_mcc_phydm_offload_enable_cmd(padapter, mcc_phydm_enable, _TRUE); + if (xb_mode == 0)/*set*/ + rtw_set_xmit_block(padapter, xb_reason); + else if (xb_mode == 1)/*clear*/ + rtw_clr_xmit_block(padapter, xb_reason); + else + RTW_INFO("invalid parameter!\n"); } return count; } #endif -ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_efuse_map(struct seq_file *m, void *v) { - struct net_device *dev = data; +#if 0 + struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_single_tx_criteria = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - u8 i = 0; - int num = sscanf(tmp, "%u", &mcc_single_tx_criteria); - - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - RTW_INFO("%s: mcc_single_tx_criteria = %d\n", __func__, mcc_single_tx_criteria); - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - iface->registrypriv.rtw_mcc_single_tx_cri = mcc_single_tx_criteria; - } - - - } - - return count; -} + HAL_DATA_TYPE *pHalData = GET_PHL_COM(adapter_to_dvobj(padapter)); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + struct efuse_info *efuse = adapter_to_efuse(padapter); + int i, j; + u8 ips_mode = IPS_NUM; + u16 mapLen; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); + if (mapLen > EFUSE_MAX_MAP_LEN) + mapLen = EFUSE_MAX_MAP_LEN; -ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_ap_bw20_target_tp = 0; + ips_mode = pwrctrlpriv->ips_mode; + rtw_pm_set_ips(padapter, IPS_NONE); - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; + if (efuse->file_status == EFUSE_FILE_LOADED) { + RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH); + if (efuse->is_autoload_fail) + RTW_PRINT_SEL(m, "File Autoload fail!!!\n"); + } else if (efuse->file_status == EFUSE_FILE_FAILED) { + RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH); + if (efuse->is_autoload_fail) + RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); + } else { + RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n"); + if (efuse->is_autoload_fail) + RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); } - - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; + for (i = 0; i < mapLen; i += 16) { + RTW_PRINT_SEL(m, "0x%02x\t", i); + for (j = 0; j < 8; j++) + RTW_PRINT_SEL(m, "%02X ", efuse->data[i + j]); + RTW_PRINT_SEL(m, "\t"); + for (; j < 16; j++) + RTW_PRINT_SEL(m, "%02X ", efuse->data[i + j]); + RTW_PRINT_SEL(m, "\n"); } - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; + if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) { + RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n"); + return 0; } - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_ap_bw20_target_tp); - - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - RTW_INFO("%s: mcc_ap_bw20_target_tp = %d\n", __func__, mcc_ap_bw20_target_tp); - - padapter->registrypriv.rtw_mcc_ap_bw20_target_tx_tp = mcc_ap_bw20_target_tp; - - + RTW_PRINT_SEL(m, "\n"); + RTW_PRINT_SEL(m, "HW eFuse Map\n"); + for (i = 0; i < mapLen; i += 16) { + RTW_PRINT_SEL(m, "0x%02x\t", i); + for (j = 0; j < 8; j++) + RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); + RTW_PRINT_SEL(m, "\t"); + for (; j < 16; j++) + RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); + RTW_PRINT_SEL(m, "\n"); } - return count; + rtw_pm_set_ips(padapter, ips_mode); +#endif + return 0; } -ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#if 0 + char tmp[256] = {0}; + u32 addr, cnts; + u8 efuse_data; + + int jj, kk; + struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_ap_bw40_target_tp = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + u8 ips_mode = IPS_NUM; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count < 3) { + RTW_INFO("argument size is less than 3\n"); return -EFAULT; } if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_ap_bw40_target_tp); - - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } - - RTW_INFO("%s: mcc_ap_bw40_target_tp = %d\n", __func__, mcc_ap_bw40_target_tp); - - padapter->registrypriv.rtw_mcc_ap_bw40_target_tx_tp = mcc_ap_bw40_target_tp; + int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data); + if (num != 3) { + RTW_INFO("invalid write_reg parameter!\n"); + return count; + } } - + ips_mode = pwrctrlpriv->ips_mode; + rtw_pm_set_ips(padapter, IPS_NONE); + if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL) + RTW_INFO("WARN - rtw_efuse_map_write error!!\n"); + rtw_pm_set_ips(padapter, ips_mode); +#endif return count; } -ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +#ifdef CONFIG_IEEE80211W +ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_ap_bw80_target_tp = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + /* macid_ctl move to phl */ + /* struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); */ + struct sta_info *psta; + _list *plist, *phead; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u32 key_type; + u8 index; + void *phl = GET_PHL_INFO(dvobj); + u16 macid_num = rtw_phl_get_macid_max_num(phl); - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count > 2) { + RTW_INFO("argument size is more than 2\n"); return -EFAULT; } - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_ap_bw80_target_tp); + int num = sscanf(tmp, "%x", &key_type); - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + if (num != 1) { + RTW_INFO("invalid read_reg parameter!\n"); + return count; } + RTW_INFO("0: set sa query request , key_type=%d\n", key_type); + } - RTW_INFO("%s: mcc_ap_bw80_target_tp = %d\n", __func__, mcc_ap_bw80_target_tp); + if (MLME_IS_STA(padapter) + && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { + RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); + /* TX unicast sa_query to AP */ + issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { + /* TX unicast sa_query to every client STA */ + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (index = 0; index < NUM_STA; index++) { + psta = NULL; - padapter->registrypriv.rtw_mcc_ap_bw80_target_tx_tp = mcc_ap_bw80_target_tp; + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + _rtw_memcpy(&mac_addr[psta->phl_sta->macid][0], psta->phl_sta->mac_addr, ETH_ALEN); + } + } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); + for (index = 0; index < macid_num && index < NUM_STA; index++) { + if (rtw_phl_macid_is_used(phl, index) && !rtw_phl_macid_is_bmc(phl, index)) { + if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN) + && !IS_MCAST(&mac_addr[index][0])) { + issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type); + RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); + } + } + } } return count; } -ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_tx_sa_query(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "%s\n", __func__); + return 0; +} + +ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_sta_bw20_target_tp = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + /* macid_ctl move to phl */ + /* struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); */ + struct sta_info *psta; + _list *plist, *phead; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u32 key_type = 0; + u8 index; + void *phl = GET_PHL_INFO(dvobj); + u16 macid_num = rtw_phl_get_macid_max_num(phl); - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count > 2) { + RTW_INFO("argument size is more than 2\n"); return -EFAULT; } - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_sta_bw20_target_tp); + int num = sscanf(tmp, "%x", &key_type); - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + if (num != 1) { + RTW_INFO("invalid read_reg parameter!\n"); + return count; } - - RTW_INFO("%s: mcc_sta_bw20_target_tp = %d\n", __func__, mcc_sta_bw20_target_tp); - - padapter->registrypriv.rtw_mcc_sta_bw20_target_tx_tp = mcc_sta_bw20_target_tp; - - + RTW_INFO("key_type=%d\n", key_type); } + if (key_type > 4) + return count; - return count; -} - -ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_sta_bw40_target_tp = 0; - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + if (MLME_IS_STA(padapter) + && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { + if (key_type == 3) /* key_type 3 only for AP mode */ + return count; + /* TX unicast deauth to AP */ + issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + u8 updated = _FALSE; - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } + if (key_type == 3) + issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY); - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } + /* TX unicast deauth to every client STA */ + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (index = 0; index < NUM_STA; index++) { + psta = NULL; - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_sta_bw40_target_tp); + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + _rtw_memcpy(&mac_addr[psta->phl_sta->macid][0], psta->phl_sta->mac_addr, ETH_ALEN); + } } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); + + for (index = 0; index < macid_num && index < NUM_STA; index++) { + if (rtw_phl_macid_is_used(phl, index) && !rtw_phl_macid_is_bmc(phl, index)) { + if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) { + if (key_type != 3) + issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type); - RTW_INFO("%s: mcc_sta_bw40_target_tp = %d\n", __func__, mcc_sta_bw40_target_tp); + psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]); + if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) { + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + #ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (psta->tbtx_enable) + pstapriv->tbtx_asoc_list_cnt--; + #endif + updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE, _FALSE); - padapter->registrypriv.rtw_mcc_sta_bw40_target_tx_tp = mcc_sta_bw40_target_tp; + } + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); + } + RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); + } + } + } + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } return count; } -ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +int proc_get_tx_deauth(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "%s\n", __func__); + return 0; +} + +ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[255]; - u32 mcc_sta_bw80_target_tp = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + /* macid_ctl move to phl */ + /*struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); */ + struct sta_info *psta; + _list *plist, *phead; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u32 tx_auth; + u8 index; - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + if (count > 2) { + RTW_INFO("argument size is more than 2\n"); return -EFAULT; } - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u", &mcc_sta_bw80_target_tp); + int num = sscanf(tmp, "%x", &tx_auth); - if (num < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; + if (num != 1) { + RTW_INFO("invalid read_reg parameter!\n"); + return count; } + RTW_INFO("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth); + } - RTW_INFO("%s: mcc_sta_bw80_target_tp = %d\n", __func__, mcc_sta_bw80_target_tp); - - padapter->registrypriv.rtw_mcc_sta_bw80_target_tx_tp = mcc_sta_bw80_target_tp; - - + if (MLME_IS_STA(padapter) + && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { + if (tx_auth == 1) { + /* TX unicast auth to AP */ + issue_auth(padapter, NULL, 0); + } else if (tx_auth == 2) { + /* TX unicast auth to AP */ + issue_assocreq(padapter); + } } return count; } -#endif /* CONFIG_MCC_MODE */ + +int proc_get_tx_auth(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "%s\n", __func__); + return 0; +} +#endif /* CONFIG_IEEE80211W */ int proc_get_ack_timeout(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 ack_timeout_val; -#ifdef CONFIG_RTL8821C - u8 ack_timeout_val_cck; -#endif + u8 ack_timeout_val = 0; + u8 ack_timeout_val_cck = 0; - ack_timeout_val = rtw_read8(padapter, REG_ACKTO); + rtw_hal_get_hwreg(padapter, HW_VAR_ACKTO, &ack_timeout_val); + rtw_hal_get_hwreg(padapter, HW_VAR_ACKTO_CCK, &ack_timeout_val_cck); -#ifdef CONFIG_RTL8821C - ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C); RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck); RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val); -#else - RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val); -#endif - return 0; } @@ -7700,7 +6090,8 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u32 ack_timeout_ms, ack_timeout_ms_cck; + u32 tmp_v1 = 0, tmp_v2 = 0; + u8 ack_to_ms = 0, ack_to_cck_ms = 0; if (count > sizeof(tmp)) { rtw_warn_on(1); @@ -7708,30 +6099,26 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_ } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck); + int num = sscanf(tmp, "%u %u", &tmp_v1, &tmp_v2); -#ifdef CONFIG_RTL8821C - if (num < 2) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter)); - return -EINVAL; - } -#else if (num < 1) { RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); return -EINVAL; } -#endif - /* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */ - rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms); -#ifdef CONFIG_RTL8821C + if (tmp_v1) { + ack_to_ms = (u8)tmp_v1; + rtw_hal_set_hwreg(padapter, HW_VAR_ACKTO, &ack_to_ms); + } + + if (tmp_v2) { + ack_to_cck_ms = (u8)tmp_v2; + rtw_hal_set_hwreg(padapter, HW_VAR_ACKTO_CCK, &ack_to_cck_ms); + } + /* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */ /* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */ - rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck); - RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck); - RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms); -#else - RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms); -#endif + RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_to_cck_ms); + RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_to_ms); } return count; @@ -7739,10 +6126,12 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_ ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { + +#if 0 /*GEORGIA_TODO_FIXIT*/ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); - HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal = GET_PHL_COM(adapter_to_dvobj(adapter)); char tmp[32]; u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0; @@ -7780,70 +6169,23 @@ ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t } return count; +#endif + return 0; } int proc_get_fw_offload(struct seq_file *m, void *v) { +#if 0 /*GEORGIA_TODO_FIXIT*/ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal = GET_PHL_COM(adapter_to_dvobj(adapter)); RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable"); +#endif return 0; } -#ifdef CONFIG_FW_HANDLE_TXBCN -extern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map); -ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u32 fw_tbtt_rpt, fw_bcn_offload; - - - if (buffer == NULL) { - RTW_INFO("input buffer is NULL!\n"); - return -EFAULT; - } - - if (count < 1) { - RTW_INFO("input length is 0!\n"); - return -EFAULT; - } - - if (count > sizeof(tmp)) { - RTW_INFO("input length is too large\n"); - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d %x",&fw_bcn_offload, &fw_tbtt_rpt); - - if (num < 2) { - RTW_INFO("input parameters < 2\n"); - return -EINVAL; - } - rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt); - } - - return count; -} - -int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - RTW_PRINT_SEL(m, "FW BCN offload:%s\n", dvobj->fw_bcn_offload ? "enable" : "disable"); - RTW_PRINT_SEL(m, "FW TBTT RPT:%x\n", dvobj->vap_tbtt_rpt_map); - return 0; -} - -#endif #ifdef CONFIG_CTRL_TXSS_BY_TP ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) @@ -8210,6 +6552,297 @@ int proc_get_smps(struct seq_file *m, void *v) } #endif /*CONFIG_SUPPORT_STATIC_SMPS*/ +#ifdef RTW_DETECT_HANG +int proc_get_hang_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &pdvobjpriv->drv_dbg; + struct hang_info *phang_info = &pdbgpriv->dbg_hang_info; + struct fw_hang_info *pfw_hang_info = &phang_info->dbg_fw_hang_info; + struct rxff_hang_info *prxff_hang_info = &phang_info->dbg_rxff_hang_info; + u8 is_hang = _FALSE; + u8 fw_gone = _FALSE; + + if (dev_is_surprise_removed(pdvobjpriv)) + is_hang = _TRUE; + + if (pfw_hang_info->dbg_is_fw_gone && + rtw_hw_get_init_completed(pdvobjpriv) && + !padapter->registrypriv.mp_mode) + fw_gone = _TRUE; + + if (pfw_hang_info->dbg_is_fw_hang || is_hang || fw_gone || + prxff_hang_info->dbg_is_rxff_hang) { + RTW_PRINT_SEL(m, "1\n"); + + if (pfw_hang_info->dbg_is_fw_hang) + RTW_PRINT_SEL(m, "FW hang\n"); + if (prxff_hang_info->dbg_is_rxff_hang) + RTW_PRINT_SEL(m, "RXFF hang\n"); + if (is_hang) + RTW_PRINT_SEL(m, "surprise remove\n"); + if (fw_gone) + RTW_PRINT_SEL(m, "FW gone\n"); + } else { + RTW_PRINT_SEL(m, "0\n"); + } + + RTW_PRINT_SEL(m, "Enter cnt = %d\n", phang_info->enter_cnt); +exit: + return 0; +} +#endif /* RTW_DETECT_HANG */ + +int proc_get_chan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n", + rtw_get_oper_ch(padapter), + rtw_get_oper_choffset(padapter), + rtw_get_oper_bw(padapter)); + + RTW_PRINT_SEL(m, "PHL ch=%d\n", + rtw_phl_get_cur_ch(padapter->phl_role)); + return 0; +} + +ssize_t proc_set_chan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 target_ch, target_offset, target_bw; +#ifdef DBG_CONFIG_CMD_DISP + u8 cmd_type = 0xFF; + u8 cmd_to = 0; +#endif + if (count < 3) { + RTW_INFO("argument size is less than 3\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = 0; +#ifdef DBG_CONFIG_CMD_DISP + num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu", + &target_ch, &target_offset, &target_bw, + &cmd_type, &cmd_to); + if (num != 5) { + RTW_INFO("invalid write_reg parameter!\n"); + return count; + } + + padapter->cmd_type = cmd_type; + padapter->cmd_timeout = cmd_to; +#else + num = sscanf(tmp, "%hhu %hhu %hhu", + &target_ch, &target_offset, &target_bw); + if (num != 3) { + RTW_INFO("invalid write_reg parameter!\n"); + return count; + } +#endif + set_channel_bwmode(padapter, target_ch, target_offset, target_bw, _FALSE); + } + + return count; +} + +int proc_get_mr_test(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return 0; +} + +ssize_t proc_set_mr_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 mode, param, param_1, param_2; + bool show_caller; + + if (count < 2) { + RTW_INFO("argument size is less than 3\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = 0; + + num = sscanf(tmp, "%hhu %hhu %hhu %hhu", &mode, ¶m, ¶m_1, ¶m_2); + if (num < 2) { + RTW_INFO("invalid write_reg parameter!\n"); + return count; + } +#ifdef PHL_MR_PROC_CMD + if (mode == 1) { + show_caller = (param) ? _TRUE : _FALSE; + rtw_phl_mr_dump_info(dvobj->phl, show_caller); + } + else if (mode == 2) { + show_caller = (param) ? _TRUE : _FALSE; + rtw_phl_mr_dump_band_ctl(dvobj->phl, show_caller); + } + else if (mode == 3) { + if (param == 1) + rtw_phl_mr_dump_mac_addr(dvobj->phl, padapter->phl_role); + else if (param == 2) + rtw_phl_mr_buddy_dump_mac_addr(dvobj->phl, padapter->phl_role); + } + else if (mode == 4 || mode == 5) { + u8 chan; + enum channel_width bw; + enum chan_offset offset; + bool rst, is_add; + + is_add = (mode == 4) ? _TRUE : _FALSE; + chan = param; + bw = param_1; + offset = param_2; + + rst = rtw_phl_chanctx_test(dvobj->phl, padapter->phl_role, is_add, &chan, &bw, &offset); + RTW_INFO("%s s_ch:%d,s_bw:%d,s_offset:%d, r_ch:%d, r_bw:%d, r_offset:%d\n", + __func__, param, param_1, param_2, chan, bw, offset); + } + else if (mode == 6) { + show_caller = (param) ? _TRUE : _FALSE; + rtw_phl_sta_dump_info(dvobj->phl, show_caller, padapter->phl_role, param_1); + } +#endif + } + + return count; +} + +int proc_get_deny_legacy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "deny_legacy = 0x%x\n", pregpriv->deny_legacy); + + if (pmlmeext) + RTW_PRINT_SEL(m, "cur_wireless_mode = 0x%x\n", pmlmeext->cur_wireless_mode); + + return 0; +} + +ssize_t proc_set_deny_legacy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u8 legacy; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu ", &legacy); + + if (num == 1 && pregpriv) { + pregpriv->deny_legacy = legacy; + RTW_INFO("deny_legacy=%d\n", legacy); + } + } + + return count; +} + +#ifdef CONFIG_80211AX_HE +int proc_get_tx_ul_mu_disable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rtw_he_actrl_om *cur_om_info = &(pmlmepriv->hepriv.om_info); + + RTW_PRINT_SEL(m, "OM ul_mu_disable = %s\n", cur_om_info->om_actrl_ele.ul_mu_disable ? "True" : "False"); + return 0; +} + +ssize_t proc_set_tx_ul_mu_disable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_he_actrl_om om_info; + u8 om_mask = 0; + char tmp[32]; + u8 ul_mu_disable; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu ", &ul_mu_disable); + + if (num == 1) { + om_mask = om_mask | OM_UL_MU_DIS; + /*om_info.actrl_om_normal_tx = _TRUE;*/ + /*om_info.actrl_om_normal_tx_cnt = 8;*/ + if (ul_mu_disable == _TRUE) + om_info.om_actrl_ele.ul_mu_disable = _TRUE; + else + om_info.om_actrl_ele.ul_mu_disable = _FALSE; + +#if 0 + /*om others control setting*/ + om_mask = om_mask | OM_RX_NSS; + om_info.om_actrl_ele.rx_nss = 1; + om_mask = om_mask | OM_CH_BW; + om_info.om_actrl_ele.channel_width= 2; + om_mask = om_mask | OM_TX_NSTS; + om_info.om_actrl_ele.tx_nsts= 2; + om_mask = om_mask | OM_ER_SU_DIS; + om_info.om_actrl_ele.er_su_disable = _TRUE; + om_mask = om_mask | OM_DL_MU_RR; + om_info.om_actrl_ele.dl_mu_mimo_rr= _TRUE; + om_mask = om_mask | OM_UL_MU_DATA_DIS; + om_info.om_actrl_ele.ul_mu_data_disable= _TRUE; +#endif + rtw_he_set_om_info(padapter, om_mask, &om_info); + issue_qos_nulldata(padapter, NULL, 0, 0, 3, 10, _TRUE); + } + } + + return count; +} +#endif + #endif /* CONFIG_PROC_DEBUG */ #define RTW_BUFDUMP_BSIZE 16 #if 1 @@ -8244,6 +6877,34 @@ inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, } #endif } + +inline void RTW_BUF_DUMP_SEL_ALWAYS(void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen) +{ + int __i; + u8 *ptr = (u8 *)_hexdata; + + if (_titlestring) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + _RTW_PRINT_SEL(sel, "%s", _titlestring); + if (_hexdatalen >= RTW_BUFDUMP_BSIZE) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (__i = 0; __i < _hexdatalen; __i++) { + if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + if (_idx_show) + _RTW_PRINT_SEL(sel, "0x%03X: ", __i); + } + _RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); + if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + _RTW_PRINT_SEL(sel, "\n"); +} #else inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out) { diff --git a/core/rtw_fake_ap.c b/core/rtw_fake_ap.c new file mode 100644 index 0000000..3b277c9 --- /dev/null +++ b/core/rtw_fake_ap.c @@ -0,0 +1,480 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include + +static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +#ifdef RTW_PHL_TEST_FPGA +static const u8 ap_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x88, 0x52, 0xa0}; +u8 ap_ssid[] = {'p','h','l','-','5','g'}; +#else +static const u8 ap_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x12, 0x34, 0x56}; +u8 ap_ssid[] = {'f','a','k','e','a','p'}; +#endif +u8 ap_ch = 1; +u16 ap_beacon_interval = 100; /* unit: ms */ +u16 ap_capability_info = 0x0001; +u8 ap_datarate[] = {0x82, 0x84, 0x8b, 0x96, 0xc, 0x12, 0x18, 0x24}; + +int rtw_fakeap_tx(struct _ADAPTER *a, struct xmit_frame *frame) +{ + u8 *data = frame->buf_addr + TXDESC_OFFSET; + u32 data_len = frame->attrib.last_txcmdsz; + struct sk_buff *skb; + u8 *buf; + + + if (GetFrameType(data) != WIFI_MGT_TYPE) + return _FAIL; + + switch (get_frame_sub_type(data)) { + case WIFI_AUTH: + case WIFI_ASSOCREQ: + case WIFI_REASSOCREQ: + case WIFI_PROBEREQ: + break; + + default: + return _FAIL; + } + + skb = rtw_skb_alloc(data_len); + buf = skb_put(skb, data_len); + _rtw_memcpy(buf, data, data_len); + rtw_free_xmitbuf(&a->xmitpriv, frame->pxmitbuf); + rtw_free_xmitframe(&a->xmitpriv, frame); + + skb_queue_tail(&adapter_to_dvobj(a)->fakeap.rxq, skb); + _set_workitem(&adapter_to_dvobj(a)->fakeap.work); + + return _SUCCESS; +} + +static void add_ie(struct sk_buff *skb, u8 index, u8 len, const u8 *source) +{ + u8 *buf; + + + buf = skb_put(skb, 2 + len); + *buf = index; + *(buf + 1) = len; + if (len > 0) + _rtw_memcpy(buf + 2, source, len); +} + +void rtw_fakeap_bcn_timer_hdl(void *p) +{ + struct dvobj_priv *d; + struct sk_buff *skb; + struct rtw_ieee80211_hdr *wlanhdr; + int len; + u8 *buf; + u8 hdrlen; + + + d = (struct dvobj_priv*)p; + hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + len = hdrlen + _FIXED_IE_LENGTH_ + + 2 + sizeof(ap_ssid) + + 2 + sizeof(ap_datarate) + + 2 + 1; + skb = rtw_skb_alloc(len); + _rtw_memset(skb->data, 0, len); + + buf = skb_put(skb, hdrlen); + wlanhdr = (struct rtw_ieee80211_hdr*)buf; + set_frame_sub_type(&wlanhdr->frame_ctl, WIFI_BEACON); + _rtw_memcpy(wlanhdr->addr1, bcast_addr, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr2, ap_addr, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr3, ap_addr, ETH_ALEN); + + buf = skb_put(skb, _FIXED_IE_LENGTH_); + /* timestamp: 8 bytes */ + /* beacon interval: 2 bytes */ + *(u16*)(buf + 8) = ap_beacon_interval; + /* capability info: 2 bytes */ + *(u16*)(buf + 10) = ap_capability_info; + + /* SSID */ + add_ie(skb, _SSID_IE_, sizeof(ap_ssid), ap_ssid); + + /* supported rates... */ + add_ie(skb, _SUPPORTEDRATES_IE_, sizeof(ap_datarate), ap_datarate); + + /* DS parameter set */ + add_ie(skb, _DSSET_IE_, 1, &ap_ch); + + skb_queue_tail(&d->fakeap.rxq, skb); + _set_workitem(&d->fakeap.work); +} + +static void rx_prepare(struct _ADAPTER *adapter, union recv_frame *r) +{ + struct rx_pkt_attrib *a; + + + /* init recv_frame */ + _rtw_init_listhead(&r->u.hdr.list); + r->u.hdr.len = 0; + a = &r->u.hdr.attrib; + _rtw_memset(a, 0, sizeof(*a)); + + /* fill sec related attrib, iv_len and icv_len will be filled by + * validate_recv_data_frame() */ + a->crc_err = 0; + a->icv_err = 0; + a->encrypt = 0; + + /* fill rx pkt attrib */ + a->hdrlen = 0; + a->bw = CHANNEL_WIDTH_MAX; + a->pkt_len = 0; + a->pkt_rpt_type = NORMAL_RX; + a->drvinfo_sz = 0; + a->bdecrypted = 0; + a->qos = 0; + a->priority = 0; + a->amsdu = 0; + a->mdata = 0; + a->mfrag = 0; + a->seq_num = 0; + a->frag_num = 0; + a->data_rate = DESC_RATE6M; + a->ppdu_cnt = 1; + a->free_cnt = 0; +} + +static union recv_frame* gen_probersp(struct _ADAPTER *a) +{ + union recv_frame *r; + u32 len; + struct sk_buff *skb; + struct rtw_ieee80211_hdr *wlanhdr; + u8 *buf; + u8 hdrlen; + u8 ielen; + + + r = rtw_alloc_recvframe(&a->recvpriv.free_recv_queue); + if (!r) { + RTW_ERR("%s: alloc recvframe failed!\n", __func__); + return NULL; + } + rtw_init_recvframe(r, &a->recvpriv); + rx_prepare(a, r); + + hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + len = RXDESC_OFFSET + hdrlen + _CAPABILITY_ + _STATUS_CODE_ + _ASOC_ID_ + + 2 + sizeof(ap_ssid) + + 2 + sizeof(ap_datarate) + + 2 + 1; + skb = rtw_skb_alloc(len); + _rtw_memset(skb->data, 0, len); + skb->dev = a->pnetdev; + skb_reserve(skb, RXDESC_OFFSET); + r->u.hdr.pkt = skb; + + buf = skb_put(skb, hdrlen); + wlanhdr = (struct rtw_ieee80211_hdr*)buf; + set_frame_sub_type(&wlanhdr->frame_ctl, WIFI_PROBERSP); + _rtw_memcpy(wlanhdr->addr1, adapter_mac_addr(a), ETH_ALEN); + _rtw_memcpy(wlanhdr->addr2, ap_addr, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr3, ap_addr, ETH_ALEN); + + buf = skb_put(skb, _FIXED_IE_LENGTH_); + /* timestamp: 8 bytes */ + /* beacon interval: 2 bytes */ + *(u16*)(buf + 8) = ap_beacon_interval; + /* capability info: 2 bytes */ + *(u16*)(buf + 10) = ap_capability_info; + + /* SSID */ + add_ie(skb, _SSID_IE_, sizeof(ap_ssid), ap_ssid); + + /* supported rates... */ + add_ie(skb, _SUPPORTEDRATES_IE_, sizeof(ap_datarate), ap_datarate); + + /* DS parameter set */ + add_ie(skb, _DSSET_IE_, 1, &ap_ch); + + /* handle r->u.hdr.attrib */ + + /* handle recv_frame pointer */ + r->u.hdr.len = skb->len; + r->u.hdr.rx_head = skb->head; + r->u.hdr.rx_data = skb->data; + r->u.hdr.rx_tail = skb_tail_pointer(skb); + r->u.hdr.rx_end = skb_end_pointer(skb); + + return r; +} + +static union recv_frame* gen_beacon(struct _ADAPTER *a, struct sk_buff *beacon) +{ + union recv_frame *r; + u32 len; + struct sk_buff *skb; + struct rtw_ieee80211_hdr *wlanhdr; + u8 *buf; + u8 hdrlen; + + + r = rtw_alloc_recvframe(&a->recvpriv.free_recv_queue); + if (!r) { + RTW_ERR("%s: alloc recvframe failed!\n", __func__); + return NULL; + } + rtw_init_recvframe(r, &a->recvpriv); + rx_prepare(a, r); + + hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + len = RXDESC_OFFSET + beacon->len; + skb = rtw_skb_alloc(len); + _rtw_memset(skb->data, 0, len); + skb->dev = a->pnetdev; + skb_reserve(skb, RXDESC_OFFSET); + r->u.hdr.pkt = skb; + + buf = skb_put(skb, beacon->len); + _rtw_memcpy(buf, beacon->data, beacon->len); + + /* handle r->u.hdr.attrib */ + + /* handle recv_frame pointer */ + r->u.hdr.len = skb->len; + r->u.hdr.rx_head = skb->head; + r->u.hdr.rx_data = skb->data; + r->u.hdr.rx_tail = skb_tail_pointer(skb); + r->u.hdr.rx_end = skb_end_pointer(skb); + + return r; +} + +static union recv_frame *gen_auth(struct _ADAPTER *a, u8 *bssid) +{ + union recv_frame *r; + u32 len; + struct sk_buff *skb; + struct rtw_ieee80211_hdr *wlanhdr; + u8 *buf; + u8 hdrlen; + + + r = rtw_alloc_recvframe(&a->recvpriv.free_recv_queue); + if (!r) { + RTW_ERR("%s: alloc recvframe failed!\n", __func__); + return NULL; + } + rtw_init_recvframe(r, &a->recvpriv); + rx_prepare(a, r); + + hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + len = RXDESC_OFFSET + hdrlen + + _AUTH_ALGM_NUM_ + _AUTH_SEQ_NUM_ + _STATUS_CODE_; + skb = rtw_skb_alloc(len); + _rtw_memset(skb->data, 0, len); + skb->dev = a->pnetdev; + skb_reserve(skb, RXDESC_OFFSET); + r->u.hdr.pkt = skb; + + buf = skb_put(skb, hdrlen); + wlanhdr = (struct rtw_ieee80211_hdr*)buf; + set_frame_sub_type(&wlanhdr->frame_ctl, WIFI_AUTH); + _rtw_memcpy(wlanhdr->addr1, adapter_mac_addr(a), ETH_ALEN); + _rtw_memcpy(wlanhdr->addr2, bssid, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr3, bssid, ETH_ALEN); + + /* setting auth algo number */ + buf = skb_put(skb, _AUTH_ALGM_NUM_); + *(u16*)buf = cpu_to_le16(0);; + + /* setting auth seq number */ + buf = skb_put(skb, _AUTH_SEQ_NUM_); + *(u16*)buf = cpu_to_le16(2); + + /* setting status code... */ + buf = skb_put(skb, _STATUS_CODE_); + *(u16*)buf = cpu_to_le16(0); + + /* handle r->u.hdr.attrib */ + + /* handle recv_frame pointer */ + r->u.hdr.len = skb->len; + r->u.hdr.rx_head = skb->head; + r->u.hdr.rx_data = skb->data; + r->u.hdr.rx_tail = skb_tail_pointer(skb); + r->u.hdr.rx_end = skb_end_pointer(skb); + + return r; +} + +static union recv_frame *gen_assocrsp(struct _ADAPTER *a, u8 *bssid) +{ + union recv_frame *r; + u32 len; + struct sk_buff *skb; + struct rtw_ieee80211_hdr *wlanhdr; + u8 *buf; + u8 hdrlen; + + + r = rtw_alloc_recvframe(&a->recvpriv.free_recv_queue); + if (!r) { + RTW_ERR("%s: alloc recvframe failed!\n", __func__); + return NULL; + } + rtw_init_recvframe(r, &a->recvpriv); + rx_prepare(a, r); + + hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + len = RXDESC_OFFSET + hdrlen + + _CAPABILITY_ + _STATUS_CODE_ + _ASOC_ID_ + + 2 + sizeof(ap_datarate); + skb = rtw_skb_alloc(len); + _rtw_memset(skb->data, 0, len); + skb->dev = a->pnetdev; + skb_reserve(skb, RXDESC_OFFSET); + r->u.hdr.pkt = skb; + + buf = skb_put(skb, hdrlen); + wlanhdr = (struct rtw_ieee80211_hdr*)buf; + set_frame_sub_type(&wlanhdr->frame_ctl, WIFI_ASSOCRSP); + _rtw_memcpy(wlanhdr->addr1, adapter_mac_addr(a), ETH_ALEN); + _rtw_memcpy(wlanhdr->addr2, bssid, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr3, bssid, ETH_ALEN); + + + /* capability info: 2 bytes */ + buf = skb_put(skb, _CAPABILITY_); + *(u16*)buf = ap_capability_info; + + /* status code: 2 bytes */ + buf = skb_put(skb, _STATUS_CODE_); + *(u16*)buf = 0; + + /* AID: 2 bytes */ + buf = skb_put(skb, _ASOC_ID_); + *(u16*)buf = 100; + + /* supported rates... */ + add_ie(skb, _SUPPORTEDRATES_IE_, sizeof(ap_datarate), ap_datarate); + + /* handle r->u.hdr.attrib */ + + /* handle recv_frame pointer */ + r->u.hdr.len = skb->len; + r->u.hdr.rx_head = skb->head; + r->u.hdr.rx_data = skb->data; + r->u.hdr.rx_tail = skb_tail_pointer(skb); + r->u.hdr.rx_end = skb_end_pointer(skb); + +// recvframe_put(r, buflen); +// pre_recv_entry(r, NULL); + + return r; +} + +static union recv_frame* fakeap_dispatcher(struct _ADAPTER *a, + struct sk_buff *skb) +{ + u8 *pframe; + union recv_frame *rframe = NULL; + + + pframe = skb->data; + RTW_INFO("A1-" MAC_FMT "\n", MAC_ARG(GetAddr1Ptr(pframe))); + RTW_INFO("A2-" MAC_FMT "\n", MAC_ARG(get_addr2_ptr(pframe))); + RTW_INFO("A3-" MAC_FMT "\n", MAC_ARG(GetAddr3Ptr(pframe))); + + if (GetFrameType(pframe) != WIFI_MGT_TYPE) + return NULL; + + switch (get_frame_sub_type(pframe)) { + case WIFI_AUTH: + { + u16 algo, seq; + + algo = le16_to_cpu(*(u16 *)(pframe + WLAN_HDR_A3_LEN)); + seq = le16_to_cpu(*(u16 *)(pframe + WLAN_HDR_A3_LEN + 2)); + + if ((algo == 0) && (seq == 1)) + rframe = gen_auth(a, GetAddr1Ptr(pframe)); + } + break; + + case WIFI_ASSOCREQ: + case WIFI_REASSOCREQ: + rframe = gen_assocrsp(a, GetAddr1Ptr(pframe)); + break; + + case WIFI_PROBEREQ: + rframe = gen_probersp(a); + break; + + case WIFI_BEACON: + rframe = gen_beacon(a, skb); + + default: + break; + } + + return rframe; +} + +extern sint validate_recv_frame(struct _ADAPTER*, union recv_frame*); +void rtw_fakeap_work(struct work_struct *work) +{ + struct dvobj_priv *d; + struct _ADAPTER *a; + struct sk_buff_head *pktq; + struct sk_buff *skb, *tmp; + u8 *ta, *ra; + union recv_frame *rframe; + int i; + + + d = container_of(work, struct dvobj_priv, fakeap.work); + + pktq = &d->fakeap.rxq; + skb_queue_walk_safe(pktq, skb, tmp) { + __skb_unlink(skb, pktq); + + ta = get_addr2_ptr(skb->data); + ra = GetAddr1Ptr(skb->data); + if (is_broadcast_mac_addr(ra) + && (_rtw_memcmp(ta, ap_addr, ETH_ALEN)==_TRUE) + && (get_frame_sub_type(skb->data) == WIFI_BEACON)) { + for (i = 0; i < d->iface_nums; i++) { + a = d->padapters[i]; + if (a) { + rframe = fakeap_dispatcher(a, skb); + if (rframe) { + validate_recv_frame(a, rframe); + rframe = NULL; + } + } + } + } else { + a = rtw_get_iface_by_macddr(dvobj_get_primary_adapter(d), + ta); + if (a) + rframe = fakeap_dispatcher(a, skb); + } + rtw_skb_free(skb); + if (rframe) { + validate_recv_frame(a, rframe); + rframe = NULL; + } + } +} diff --git a/core/rtw_ft.c b/core/rtw_ft.c index 1ba55ce..f4113e6 100644 --- a/core/rtw_ft.c +++ b/core/rtw_ft.c @@ -14,7 +14,6 @@ *****************************************************************************/ #include -#include #ifdef CONFIG_RTW_80211R @@ -36,7 +35,7 @@ void rtw_ft_info_init(struct ft_roam_info *pft) _rtw_memset(pft, 0, sizeof(struct ft_roam_info)); pft->ft_flags = 0 | RTW_FT_EN - /* | RTW_FT_OTD_EN */ + | RTW_FT_OTD_EN #ifdef CONFIG_RTW_BTM_ROAM | RTW_FT_BTM_ROAM #endif @@ -89,11 +88,11 @@ u8 rtw_ft_chk_roaming_candidate( u32 mdie_len = 0; struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); - if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12], - _MDIE_, &mdie_len, competitor->network.IELength-12))) { + if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, + &mdie_len, competitor->network.IELength-12))) { RTW_INFO("FT : MDIE not foud in competitor!\n"); return _FALSE; - } + } if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2)) { RTW_INFO("FT : unmatched MDIE!\n"); @@ -103,22 +102,24 @@ u8 rtw_ft_chk_roaming_candidate( /*The candidate don't support over-the-DS*/ if (rtw_ft_valid_otd_candidate(padapter, pmdie)) { RTW_INFO("FT: ignore the candidate(" - MAC_FMT ") for over-the-DS\n", + MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); - /* rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); */ - return _FALSE; + /* rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); */ + return _FALSE; } if (rtw_ft_chk_flags(padapter, RTW_FT_TEST_RSSI_ROAM)) { - if (!_rtw_memcmp(padapter->mlmepriv.cur_network.network.MacAddress, - competitor->network.MacAddress, ETH_ALEN) ) { - competitor->network.Rssi +=20; - RTW_FT_INFO("%s : update "MAC_FMT" RSSI to %d for RTW_FT_TEST_RSSI_ROAM\n", + if (!_rtw_memcmp( + padapter->mlmepriv.cur_network.network.MacAddress, + competitor->network.MacAddress, ETH_ALEN)) { + competitor->network.PhyInfo.rssi +=20; + RTW_FT_INFO("%s : update "MAC_FMT + " RSSI to %d for RTW_FT_TEST_RSSI_ROAM\n", __func__, MAC_ARG(competitor->network.MacAddress), - (int)competitor->network.Rssi); + (int)competitor->network.PhyInfo.rssi); rtw_ft_clr_flags(padapter, RTW_FT_TEST_RSSI_ROAM); } - } + } return _TRUE; } @@ -132,18 +133,21 @@ void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) if (psta == NULL) psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress); - if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { - + if (padapter->securitypriv.dot11AuthAlgrthm == + dot11AuthAlgrthm_8021X) { padapter->securitypriv.binstallGrpkey = _FALSE; padapter->securitypriv.busetkipkey = _FALSE; padapter->securitypriv.bgrpkey_handshake = _FALSE; psta->ieee8021x_blocked = _TRUE; - psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; - - _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); + psta->dot118021XPrivacy = \ + padapter->securitypriv.dot11PrivacyAlgrthm; + _rtw_memset((u8 *)&psta->dot118021x_UncstKey, + 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiprxmickey, + 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiptxmickey, + 0, sizeof(union Keytype)); } } @@ -157,43 +161,45 @@ void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; - _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); rtw_ft_update_stainfo(padapter, pnetwork); ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); - if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); - else + if (ft_evt_parms.ies) { + _rtw_memcpy((void *)ft_evt_parms.ies, + pft_roam->ft_event.ies, ft_evt_parms.ies_len); + } else goto err_2; ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN); - if (ft_evt_parms.target_ap) - _rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN); - else + if (ft_evt_parms.target_ap) { + _rtw_memcpy((void *)ft_evt_parms.target_ap, + pstassoc->macaddr, ETH_ALEN); + } else goto err_1; ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; - /* It's a KERNEL issue between v4.11 ~ v4.16, + /* It's a KERNEL issue between v4.11 ~ v4.16, * <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new(). - * v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() + * v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() * even then DRIVER don't support RIC. * >= v4.17, issue should correct as "100 + ies_len + ric_ies_len". - */ + */ #if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \ (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))) if (!ft_evt_parms.ric_ies_len) ft_evt_parms.ric_ies_len = ft_evt_parms.ies_len; - else - ft_evt_parms.ric_ies_len += ft_evt_parms.ies_len; - #endif - - rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); + else + ft_evt_parms.ric_ies_len += ft_evt_parms.ies_len; + #endif + + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); - RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap)); + RTW_INFO("%s: to "MAC_FMT"\n", __func__, + MAC_ARG(ft_evt_parms.target_ap)); rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); err_1: @@ -212,31 +218,50 @@ void rtw_ft_validate_akm_type(_adapter *padapter, /*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/ if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) { - ptmp = rtw_get_ie(&pnetwork->network.IEs[12], - _MDIE_, &tmp_len, (pnetwork->network.IELength-12)); + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], + _MDIE_, &tmp_len, + (pnetwork->network.IELength-12)); if (ptmp) { pft_roam->mdid = *(u16 *)(ptmp+2); pft_roam->ft_cap = *(ptmp+4); - RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", - MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap); + RTW_INFO("FT: target "MAC_FMT + " mdid=(0x%2x), capacity=(0x%2x)\n", + MAC_ARG(pnetwork->network.MacAddress), + pft_roam->mdid, pft_roam->ft_cap); + rtw_ft_set_flags(padapter, RTW_FT_PEER_EN); - RTW_FT_INFO("%s : peer support FTOTA(0x%02x)\n", __func__, pft_roam->ft_flags); + + RTW_FT_INFO("%s : peer support FTOTA(0x%02x)," + " ft_roam_on_expired=0x%02x\n", + __func__, pft_roam->ft_flags, + pft_roam->ft_roam_on_expired); if (rtw_ft_otd_roam_en(padapter)) { rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN); - RTW_FT_INFO("%s : peer support FTOTD(0x%02x)\n", __func__, pft_roam->ft_flags); + RTW_FT_INFO("%s : peer support FTOTD(0x%02x)\n", + __func__, pft_roam->ft_flags); + } else { + pft_roam->ft_cap &= ~BIT(0); + rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); + RTW_FT_INFO("%s : update mdid=0x%02x, " + "cap=0x%02x, flag=0x%02x\n", + __func__, pft_roam->mdid, + pft_roam->ft_cap, + pft_roam->ft_flags); } } else { /* Don't use FT roaming if target AP cannot support FT */ - rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_clr_flags(padapter, + (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); rtw_ft_reset_status(padapter); } } else { /* It could be a non-FT connection */ - rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_clr_flags(padapter, + (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); rtw_ft_reset_status(padapter); - } + } RTW_FT_INFO("%s : ft_flags=0x%02x\n", __func__, pft_roam->ft_flags); } @@ -250,29 +275,51 @@ void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame) uint len = precv_frame->u.hdr.len; WLAN_BSSID_EX *pbss; - if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) + if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) && (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) { pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX)); if (pbss) { - if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { + if (collect_bss_info( + padapter, precv_frame, pbss) == _SUCCESS) { struct beacon_keys recv_beacon; - update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_update_network( + &(pmlmepriv->cur_network.network), + pbss, padapter, _TRUE); + /* Move into rtw_get_bcn_keys */ /* rtw_get_bcn_info(&(pmlmepriv->cur_network)); */ - + /* update bcn keys */ - if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { - RTW_FT_INFO("%s: beacon keys ready\n", __func__); - _rtw_memcpy(&pmlmepriv->cur_beacon_keys, - &recv_beacon, sizeof(recv_beacon)); - if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) { - _rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE); - pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength; + if (rtw_get_bcn_keys(padapter, pframe, len, + &recv_beacon) == _TRUE) { + + RTW_FT_INFO("%s: beacon keys ready\n", + __func__); + + _rtw_memcpy( + &pmlmepriv->cur_beacon_keys, + &recv_beacon, + sizeof(recv_beacon)); + + if (is_hidden_ssid( + recv_beacon.ssid, + recv_beacon.ssid_len)) { + + _rtw_memcpy( + pmlmepriv->cur_beacon_keys.ssid, + pmlmeinfo->network.Ssid.Ssid, + IW_ESSID_MAX_SIZE); + + pmlmepriv->cur_beacon_keys.ssid_len = \ + pmlmeinfo->network.Ssid.SsidLength; } } else { - RTW_ERR("%s: get beacon keys failed\n", __func__); - _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); + RTW_ERR("%s: get beacon keys failed\n", + __func__); + _rtw_memset( + &pmlmepriv->cur_beacon_keys, + 0, sizeof(recv_beacon)); } #ifdef CONFIG_BCN_CNT_CONFIRM_HDL pmlmepriv->new_beacon_cnts = 0; @@ -282,9 +329,11 @@ void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame) } /* check the vendor of the assoc AP */ - pmlmeinfo->assoc_AP_vendor = - check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), - (len - sizeof(struct rtw_ieee80211_hdr_3addr))); + pmlmeinfo->assoc_AP_vendor = + check_assoc_AP( + pframe + sizeof(struct rtw_ieee80211_hdr_3addr), + (len - sizeof(struct rtw_ieee80211_hdr_3addr)) + ); /* update TSF Value */ update_TSF(pmlmeext, pframe, len); @@ -304,9 +353,11 @@ void rtw_ft_start_clnt_join(_adapter *padapter) if (rtw_ft_otd_roam(padapter)) { pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; pft_roam->ft_event.ies = - (pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16); + (pft_roam->ft_action + \ + sizeof(struct rtw_ieee80211_hdr_3addr) + 16); pft_roam->ft_event.ies_len = - (pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr)); + (pft_roam->ft_action_len - \ + sizeof(struct rtw_ieee80211_hdr_3addr)); /*Not support RIC*/ pft_roam->ft_event.ric_ies = NULL; @@ -320,26 +371,26 @@ void rtw_ft_start_clnt_join(_adapter *padapter) } u8 rtw_ft_update_rsnie( - _adapter *padapter, u8 bwrite, + _adapter *padapter, u8 bwrite, struct pkt_attrib *pattrib, u8 **pframe) { struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); u8 *pie; u32 len; - pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, + pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, pft_roam->updated_ft_ies_len); if (!bwrite) return (pie)?_SUCCESS:_FAIL; - + if (pie) { - *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, - pie+2, &(pattrib->pktlen)); + *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, + pie+2, &(pattrib->pktlen)); } else return _FAIL; - return _SUCCESS; + return _SUCCESS; } static u8 rtw_ft_update_mdie( @@ -350,10 +401,10 @@ static u8 rtw_ft_update_mdie( u32 len = 3; if (rtw_ft_roam(padapter)) { - if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, &len, pft_roam->updated_ft_ies_len))) { pie = (pie + 2); /* ignore md-id & length */ - } else + } else return _FAIL; } else { *((u16 *)&mdie[0]) = pft_roam->mdid; @@ -361,8 +412,9 @@ static u8 rtw_ft_update_mdie( pie = &mdie[0]; } - *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen)); - return _SUCCESS; + *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, + len, pie, &(pattrib->pktlen)); + return _SUCCESS; } static u8 rtw_ft_update_ftie( @@ -372,17 +424,17 @@ static u8 rtw_ft_update_ftie( u8 *pie; u32 len; - if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, pft_roam->updated_ft_ies_len)) != NULL) { - *pframe = rtw_set_ie(*pframe, _FTIE_, len , - (pie+2), &(pattrib->pktlen)); + *pframe = rtw_set_ie(*pframe, _FTIE_, len, + (pie+2), &(pattrib->pktlen)); } else return _FAIL; - return _SUCCESS; + return _SUCCESS; } -void rtw_ft_build_auth_req_ies(_adapter *padapter, +void rtw_ft_build_auth_req_ies(_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe) { u8 ftie_append = _TRUE; @@ -399,7 +451,7 @@ void rtw_ft_build_auth_req_ies(_adapter *padapter, rtw_ft_update_ftie(padapter, pattrib, pframe); } -void rtw_ft_build_assoc_req_ies(_adapter *padapter, +void rtw_ft_build_assoc_req_ies(_adapter *padapter, u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe) { if (!pattrib || !(*pframe)) @@ -412,7 +464,7 @@ void rtw_ft_build_assoc_req_ies(_adapter *padapter, return; if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe)) - rtw_ft_update_ftie(padapter, pattrib, pframe); + rtw_ft_update_ftie(padapter, pattrib, pframe); } u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len) @@ -432,13 +484,15 @@ u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len) if (!pframe || !len) return _FAIL; - - rtw_buf_update(&pmlmepriv->auth_rsp, + + rtw_buf_update(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len, pframe, len); pft_roam->ft_event.ies = - (pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6); + (pmlmepriv->auth_rsp + \ + sizeof(struct rtw_ieee80211_hdr_3addr) + 6); pft_roam->ft_event.ies_len = - (pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6); + (pmlmepriv->auth_rsp_len - \ + sizeof(struct rtw_ieee80211_hdr_3addr) - 6); /*Not support RIC*/ pft_roam->ft_event.ric_ies = NULL; @@ -446,7 +500,7 @@ u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len) _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); rtw_ft_report_reassoc_evt(padapter, target_ap_addr); - return ret; + return ret; } static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr) @@ -466,7 +520,8 @@ void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr) RTW_FT_INFO("%s : try OTD roaming\n", __func__); rtw_ft_start_clnt_action(padapter, pTargetAddr); } else { - /*wait a little time to retrieve packets buffered in the current ap while scan*/ + /* wait a little time to retrieve packets buffered + in the current ap while scan*/ RTW_FT_INFO("%s : start roaming timer\n", __func__); _set_timer(&pmlmeext->ft_roam_timer, 30); } @@ -497,9 +552,11 @@ void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr) pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; pwlanhdr->frame_ctl = 0; - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, + get_my_bssid(&pmlmeinfo->network), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&pmlmeinfo->network), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; @@ -536,7 +593,6 @@ void rtw_ft_report_evt(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; - _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); rtw_ft_update_stainfo(padapter, pnetwork); @@ -546,33 +602,35 @@ void rtw_ft_report_evt(_adapter *padapter) ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); - if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); - else + if (ft_evt_parms.ies) { + _rtw_memcpy((void *)ft_evt_parms.ies, + pft_roam->ft_event.ies, ft_evt_parms.ies_len); + } else goto err_2; ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN); - if (ft_evt_parms.target_ap) - _rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN); - else + if (ft_evt_parms.target_ap) { + _rtw_memcpy((void *)ft_evt_parms.target_ap, + pnetwork->MacAddress, ETH_ALEN); + } else goto err_1; ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; - /* It's a KERNEL issue between v4.11 ~ v4.16, + /* It's a KERNEL issue between v4.11 ~ v4.16, * <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new(). - * v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() + * v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() * even then DRIVER don't support RIC. * >= v4.17, issue should correct as "100 + ies_len + ric_ies_len". - */ + */ #if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \ (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))) ft_evt_parms.ric_ies_len = (ft_evt_parms.ies_len <= 100 )? (0):(ft_evt_parms.ies_len - 100); #endif - - rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); + + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); RTW_INFO("FT: rtw_ft_report_evt\n"); rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); @@ -585,7 +643,7 @@ void rtw_ft_report_evt(_adapter *padapter) void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr) { struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(padapter)->cmdpriv); struct cmd_obj *pcmd_obj = NULL; struct stassoc_event *passoc_sta_evt = NULL; struct rtw_evt_header *evt_hdr = NULL; @@ -604,6 +662,7 @@ void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr) } _rtw_init_listhead(&pcmd_obj->list); + pcmd_obj->padapter = padapter; pcmd_obj->cmdcode = CMD_SET_MLME_EVT; pcmd_obj->cmdsz = cmdsz; pcmd_obj->parmbuf = pevtcmd; @@ -615,8 +674,11 @@ void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr) evt_hdr->id = EVT_FT_REASSOC; evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN); + passoc_sta_evt = \ + (struct stassoc_event *)(pevtcmd + \ + sizeof(struct rtw_evt_header)); + _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), + pMacAddr, ETH_ALEN); rtw_enqueue_cmd(pcmdpriv, pcmd_obj); } @@ -631,13 +693,15 @@ void rtw_ft_link_timer_hdl(void *ctx) if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) { if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) { pft_roam->ft_req_retry_cnt++; - rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + rtw_ft_issue_action_req(padapter, + (u8 *)pmlmepriv->roam_network->network.MacAddress); _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); } else { - pft_roam->ft_req_retry_cnt = 0; - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA); - else + pft_roam->ft_req_retry_cnt = 0; + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + rtw_ft_set_status(padapter, + RTW_FT_ASSOCIATED_STA); + } else rtw_ft_reset_status(padapter); } } @@ -649,20 +713,215 @@ void rtw_ft_roam_timer_hdl(void *ctx) struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); RTW_FT_INFO("%s : try roaming\n", __func__); - receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress - , WLAN_REASON_ACTIVE_ROAM, _FALSE); + receive_disconnect(padapter, + pmlmepriv->cur_network.network.MacAddress, + WLAN_REASON_ACTIVE_ROAM, _FALSE); } void rtw_ft_roam_status_reset(_adapter *padapter) { struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); - if ((rtw_to_roam(padapter) > 0) && + if ((rtw_to_roam(padapter) > 0) && (!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) { rtw_ft_reset_status(padapter); - } - + } + padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE; } +void rtw_ft_peer_info_init(struct sta_info *psta) +{ + struct rtw_sta_ft_info_t *peer = &(psta->ft_peer); + _rtw_memset(peer, 0, sizeof(struct rtw_sta_ft_info_t)); +} + +void rtw_ft_peer_info_free(struct sta_info *psta) +{ + struct rtw_sta_ft_info_t *peer = &(psta->ft_peer); + + rtw_buf_free(&peer->md_ie, &peer->md_len); + rtw_buf_free(&peer->rsn_ie, &peer->rsn_len); + rtw_buf_free(&peer->ft_ie, &peer->ft_len); +} + +int rtw_ft_update_sta_ies(_adapter *padapter, + struct cfg80211_update_ft_ies_params *ie) +{ + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct sta_priv *pstapriv = &(padapter->stapriv); + struct sta_info *psta; + struct rtw_sta_ft_info_t *peer_info; + u8 *ptr, *paddr; + u32 len; + int ret = 0; + + if (!CHECK_BIT(WLAN_AKM_TYPE_FT_PSK, psecuritypriv->akmp) + && !CHECK_BIT(WLAN_AKM_TYPE_FT_8021X, psecuritypriv->akmp) + && !CHECK_BIT(WLAN_AKM_TYPE_FT_OVER_SAE, psecuritypriv->akmp)) { + RTW_FT_INFO("%s : AKM=0x%x\n", __func__, psecuritypriv->akmp); + goto exit; + } + + if ((ie->ie_len == 0) || + (ie->ie_len >= RTW_FT_MAX_IE_SZ)) { + ret = - EINVAL; + goto exit; + } + + if ((ptr = rtw_get_ie(ie->ie, WLAN_EID_VENDOR_SPECIFIC, + &len , ie->ie_len)) == NULL) { + RTW_ERR("FT : no station mac address found in ies\n"); + ret = -EINVAL; + goto exit; + } + + if (len != ETH_ALEN) { + RTW_ERR("FT : invalid station mac length(%u)\n", len); + ret = -EINVAL; + goto exit; + } + + paddr = ptr + 2; + if ((psta = rtw_get_stainfo(pstapriv, paddr)) == NULL) { + RTW_ERR("FT : sta "MAC_FMT" not found!\n", MAC_ARG(paddr)); + ret = -EINVAL; + goto exit; + } + + RTW_FT_INFO("%s : update sta "MAC_FMT" ie, len=%lu\n", + __func__, MAC_ARG(paddr), ie->ie_len); + RTW_FT_DUMP("ie = ", ie->ie, ie->ie_len); + + peer_info = &(psta->ft_peer); + if ((ptr = rtw_get_ie(ie->ie, EID_WPA2, &len , ie->ie_len)) != NULL) { + rtw_buf_update(&peer_info->rsn_ie, + &peer_info->rsn_len, ptr + 2, len); + RTW_FT_DUMP("rsn_ie = ", peer_info->rsn_ie, + peer_info->rsn_len); + } + + if ((ptr = rtw_get_ie(ie->ie, _MDIE_, &len , ie->ie_len)) != NULL) { + rtw_buf_update(&peer_info->md_ie, + &peer_info->md_len, ptr + 2, len); + RTW_FT_DUMP("md_ie = ", + peer_info->md_ie, peer_info->md_len); + } + + if ((ptr = rtw_get_ie(ie->ie, _FTIE_, &len , ie->ie_len)) != NULL) { + rtw_buf_update(&peer_info->ft_ie, + &peer_info->ft_len, ptr + 2, len); + RTW_FT_DUMP("ft_ie = ", + peer_info->ft_ie, peer_info->ft_len); + } + + if (psta->authalg == WLAN_AUTH_FT) + issue_asocrsp(padapter, 0, psta, WIFI_REASSOCRSP); +exit: + return ret; +} + +void rtw_ft_update_assocresp_ies(struct net_device *net, + struct cfg80211_ap_settings *settings) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pinfo = &(pmlmepriv->ft_roam); + u8 *ie, *bcn_tail_ies, *assocrsp_ies; + int ielen, bcn_tail_len, assocrsp_ies_len, ret = 0; + + bcn_tail_ies = (u8 *)settings->beacon.tail; + bcn_tail_len = (u32)settings->beacon.tail_len; + assocrsp_ies = (u8 *)settings->beacon.assocresp_ies; + assocrsp_ies_len = (u32)settings->beacon.assocresp_ies_len; + + if ((bcn_tail_len > 0) && + ((ie = rtw_get_ie(bcn_tail_ies, _MDIE_, + &ielen , bcn_tail_len)) != NULL)) { + pinfo->mdid = *(u16 *)(ie + 2); + pinfo->ft_cap = *(ie + 4); + RTW_FT_INFO("%s : mdid = 0x%04x, cap=0x%02x\n", + __func__, pinfo->mdid, pinfo->ft_cap); + } + + if ((assocrsp_ies_len > 0) && + ((ie = rtw_get_ie(assocrsp_ies, _FTIE_, + &ielen , assocrsp_ies_len)) != NULL)) { + _rtw_memset(pinfo->updated_ft_ies, 0, RTW_FT_MAX_IE_SZ); + _rtw_memcpy(pinfo->updated_ft_ies, ie + 2, ielen); + pinfo->updated_ft_ies_len = ielen; + RTW_FT_DUMP("FT : ft ie = ", ie + 2, ielen); + } + +} + +void rtw_ft_process_ft_auth_rsp(_adapter *padapter, u8 *pframe, u32 len) +{ + struct sta_priv *pstapriv = &(padapter->stapriv); + struct sta_info *psta = NULL; + u8 *ptr; + u32 plen; + + ptr = pframe + IEEE80211_3ADDR_LEN + _AUTH_IE_OFFSET_; + plen = len - IEEE80211_3ADDR_LEN - _AUTH_IE_OFFSET_; + + psta = rtw_get_stainfo(pstapriv, GetAddr1Ptr(pframe)); + if (psta) { + _rtw_spinlock_bh(&psta->lock); + psta->state &= ~WIFI_FW_AUTH_NULL; + psta->state |= WIFI_FW_AUTH_SUCCESS; + psta->expire_to = pstapriv->assoc_to; + _rtw_spinunlock_bh(&psta->lock); + } +} + +void rtw_ft_build_assoc_rsp_ies(_adapter *padapter, + struct sta_info *psta, struct pkt_attrib *pattrib, u8 **pframe) +{ + struct ft_roam_info *prinfo = &(padapter->mlmepriv.ft_roam); + struct rtw_sta_ft_info_t *peer_info; + u8 *pie, mdie[3] = {0}; + u32 ielen; + + if (psta == NULL) + return; + + if (psta->authalg != WLAN_AUTH_FT) { + *((u16 *)&mdie[0]) = prinfo->mdid; + mdie[2] = prinfo->ft_cap; + pie = mdie; + ielen = 3; + + if (prinfo->mdid > 0) { + *pframe = rtw_set_ie(((u8 *)*pframe), + _MDIE_, ielen , pie, &(pattrib->pktlen)); + } + + if (prinfo->updated_ft_ies_len > 0) { + *pframe = rtw_set_ie(((u8 *)*pframe), + _FTIE_, prinfo->updated_ft_ies_len, + prinfo->updated_ft_ies, &(pattrib->pktlen)); + } + } else { + peer_info = &(psta->ft_peer); + if (peer_info->rsn_len > 0) { + *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, + peer_info->rsn_len, peer_info->rsn_ie, + &(pattrib->pktlen)); + } + + if (peer_info->md_len > 0) { + *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, + peer_info->md_len, peer_info->md_ie, + &(pattrib->pktlen)); + } + + if (peer_info->ft_len > 0) { + *pframe = rtw_set_ie(((u8 *)*pframe), _FTIE_, + peer_info->ft_len, peer_info->ft_ie, + &(pattrib->pktlen)); + } + } + +} #endif /* CONFIG_RTW_80211R */ diff --git a/core/rtw_he.c b/core/rtw_he.c new file mode 100644 index 0000000..b539dba --- /dev/null +++ b/core/rtw_he.c @@ -0,0 +1,1464 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_HE_C + +#include + +#ifdef CONFIG_80211AX_HE + +/* for now cover BW 20/40/80 bounded in 2SS */ +const u16 HE_MCS_DATA_RATE[3][MAX_HE_GI_TYPE][MAX_HE_MCS_INDEX] = { + { /* 20M */ + { /* 3.2us */ + 14, 29, 43, 58, 87, 117, 131, 146, 175, 195, 219, 243, + 29, 58, 87, 117, 175, 234, 263, 292, 351, 390, 438, 487, + }, + { /* 1.6us */ + 16, 32, 48, 65, 97, 130, 146, 162, 195, 216, 243, 270, + 32, 65, 97, 130, 195, 260, 292, 325, 390, 433, 487, 541, + }, + { /* 0.8us */ + 17, 34, 51, 68, 103, 137, 154, 172, 206, 229, 258, 286, + 34, 68, 103, 137, 206, 275, 309, 344, 413, 458, 516, 573, + } + }, + { /* 40M */ + { /* 3.2us */ + 29, 58, 87, 117, 175, 234, 263, 292, 351, 390, 438, 487, + 58, 117, 175, 234, 351, 468, 526, 585, 702, 780, 877, 975, + }, + { /* 1.6us */ + 32, 65, 97, 130, 195, 260, 292, 325, 390, 433, 487, 541, + 65, 130, 195, 260, 390, 520, 585, 650, 780, 866, 975, 1083, + }, + { /* 0.8us */ + 34, 68, 103, 138, 206, 275, 309, 344, 413, 458, 516, 573, + 68, 137, 206, 275, 413, 550, 619, 688, 825, 917, 1032, 1147, + } + }, + { /* 80M */ + { /* 3.2us */ + 61, 122, 183, 245, 367, 490, 551, 612, 735, 816, 918, 1020, + 122, 245, 367, 490, 735, 980, 1102, 1225, 1470, 1633, 1839, 2041, + }, + { /* 1.6us */ + 68, 136, 204, 272, 408, 544, 612, 680, 816, 907, 1020, 1134, + 136, 272, 408, 544, 816, 1088, 1225, 1361, 1633, 1814, 2041, 2268, + }, + { /* 0.8us */ + 72, 144, 216, 288, 432, 576, 648, 720, 864, 960, 1080, 1200, + 144, 288, 432, 576, 864, 1153, 1297, 1441, 1729, 1921, 2161, 2402, + } + } +}; + +u16 rtw_he_mcs_to_data_rate(u8 bw, u8 guard_int, u8 he_mcs_rate) +{ + u8 gi = 2; /* use 0.8us GI since 2XLTF_0.8us GI is mandatory in HE */ + u8 mcs_idx = he_mcs_rate - MGN_HE1SS_MCS0; + + return HE_MCS_DATA_RATE[bw][gi][mcs_idx]; +} + +static u8 rtw_he_get_highest_rate(u8 *he_mcs_map) +{ + u8 i, j; + u8 bit_map; + u8 he_mcs_rate = 0; + + /* currently only consider the BW 80M */ + for (i = 0; i < 2; i++) { + if (he_mcs_map[i] != 0xff) { + /* max to 4SS, each SS contains 2 bit */ + for (j = 0; j < 8; j += 2) { + bit_map = (he_mcs_map[i] >> j) & 3; + + if (bit_map != 3) + he_mcs_rate = MGN_HE1SS_MCS7 + 12 * j / 2 + i * 48 + 2 * bit_map; + } + } + } + + /*RTW_INFO("####### HighestHEMCSRate is %x\n", he_mcs_rate);*/ + return he_mcs_rate; +} + +void rtw_he_use_default_setting(_adapter *padapter) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *role_cap = &(wrole->proto_role_cap); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + + phepriv->he_highest_rate = rtw_he_get_highest_rate(role_cap->he_rx_mcs); +} + +static void rtw_he_set_asoc_cap_supp_mcs(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start, u8 supp_mcs_len) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *role_cap = &(wrole->proto_role_cap); + int nss = 0, nss_tx = 0, nss_rx = 0; + u8 mcs_from_role = HE_MSC_NOT_SUPP; + u8 mcs_from_ie = HE_MSC_NOT_SUPP; + u8 mcs_val_rx = HE_MSC_NOT_SUPP; + u8 mcs_val_tx = HE_MSC_NOT_SUPP; + + _rtw_memset(phl_sta->asoc_cap.he_rx_mcs, HE_MSC_NOT_SUPP_BYTE, HE_CAP_ELE_SUPP_MCS_LEN_RX_80M); + _rtw_memset(phl_sta->asoc_cap.he_tx_mcs, HE_MSC_NOT_SUPP_BYTE, HE_CAP_ELE_SUPP_MCS_LEN_TX_80M); + + /* only deal with <= 80MHz now */ + for (nss = 1; nss <= 8; nss++) { + + mcs_val_rx = HE_MSC_NOT_SUPP; + mcs_val_tx = HE_MSC_NOT_SUPP; + + switch (nss) { + case 1: + mcs_from_role = GET_HE_CAP_MCS_1SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_1SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_1SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_1SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 2: + mcs_from_role = GET_HE_CAP_MCS_2SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_2SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_2SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_2SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 3: + mcs_from_role = GET_HE_CAP_MCS_3SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_3SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_3SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_3SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 4: + mcs_from_role = GET_HE_CAP_MCS_4SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_4SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_4SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_4SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 5: + mcs_from_role = GET_HE_CAP_MCS_5SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_5SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_5SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_5SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 6: + mcs_from_role = GET_HE_CAP_MCS_6SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_6SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_6SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_6SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 7: + mcs_from_role = GET_HE_CAP_MCS_7SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_7SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_7SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_7SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + case 8: + mcs_from_role = GET_HE_CAP_MCS_8SS(role_cap->he_tx_mcs); + mcs_from_ie = GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_rx = (mcs_from_role < mcs_from_ie) ? mcs_from_role : mcs_from_ie; + + mcs_from_role = GET_HE_CAP_MCS_8SS(role_cap->he_rx_mcs); + mcs_from_ie = GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(ele_start); + if ((mcs_from_role != HE_MSC_NOT_SUPP) && (mcs_from_ie != HE_MSC_NOT_SUPP)) + mcs_val_tx = mcs_from_ie; + + SET_HE_CAP_MCS_8SS(phl_sta->asoc_cap.he_rx_mcs, mcs_val_rx); + SET_HE_CAP_MCS_8SS(phl_sta->asoc_cap.he_tx_mcs, mcs_val_tx); + break; + } + + if (mcs_val_rx != HE_MSC_NOT_SUPP) + nss_rx++; + + if (mcs_val_tx != HE_MSC_NOT_SUPP) + nss_tx++; + } + + phl_sta->asoc_cap.nss_rx = nss_rx; + phl_sta->asoc_cap.nss_tx = nss_tx; +} + +static void rtw_he_set_asoc_cap_ppe_thre(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start) +{ + u8 nsts, rumsk, i, j, offset, shift; + u16 ppe8, ppe16; + + if (phl_sta->asoc_cap.pkt_padding != 3) + return; + + nsts = GET_HE_CAP_PPE_NSTS(ele_start); + rumsk = GET_HE_CAP_PPE_PU_IDX_BITMASK(ele_start); + shift = 7; + + for (i = 0; i <= nsts; i ++) { + for (j = 0; j < 4; j++) { + if (rumsk & (BIT(0) << j)) { + offset = shift / 8; + ppe16 = LE_BITS_TO_2BYTE(ele_start + offset, shift % 8, 3); + shift += 3; + offset = shift / 8; + ppe8 = LE_BITS_TO_2BYTE(ele_start + offset, shift % 8, 3); + shift += 3; + phl_sta->asoc_cap.ppe_thr[i][j] = ((ppe16 & 0x07) | ((ppe8 & 0x07) << 3)); + } else { + phl_sta->asoc_cap.ppe_thr[i][j] = 0; + } + } + } +} + +static void update_sta_he_mac_cap_apmode(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start) +{ + /* CONFIG_80211AX_HE_TODO - we may need to refer to role_cap when setting some of asoc_cap */ +#if 0 + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *role_cap = &(wrole->proto_role_cap); +#endif + + phl_sta->asoc_cap.htc_rx = GET_HE_MAC_CAP_HTC_HE_SUPPORT(ele_start); + phl_sta->asoc_cap.twt = GET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(ele_start); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(ele_start)) << 1); + phl_sta->asoc_cap.trig_padding = GET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(ele_start); + phl_sta->asoc_cap.all_ack = GET_HE_MAC_CAP_ALL_ACK_SUPPORT(ele_start); + phl_sta->asoc_cap.a_ctrl = GET_HE_MAC_CAP_TRS_SUPPORT(ele_start); + phl_sta->asoc_cap.a_ctrl |= ((GET_HE_MAC_CAP_BRS_SUPPORT(ele_start)) << 1); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_BC_TWT_SUPPORT(ele_start)) << 2); + phl_sta->asoc_cap.a_ctrl |= ((GET_HE_MAC_CAP_OM_CTRL_SUPPORT(ele_start)) << 2); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(ele_start)) << 3); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_PSR_RESPONDER(ele_start)) << 4); + phl_sta->asoc_cap.ops = GET_HE_MAC_CAP_OPS_SUPPORT(ele_start); + phl_sta->asoc_cap.amsdu_in_ampdu = + GET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(ele_start); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(ele_start)) << 5); + phl_sta->asoc_cap.ht_vht_trig_rx = + GET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(ele_start); +} + +static void update_sta_he_phy_cap_apmode(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start, u8 *supp_mcs_len) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *role_cap = &(wrole->proto_role_cap); + struct role_cap_t *cap = &(wrole->cap); + + if (phl_sta->chandef.band == BAND_ON_24G) { + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(0)) + phl_sta->chandef.bw = (wrole->chandef.bw < CHANNEL_WIDTH_40) ? + wrole->chandef.bw : CHANNEL_WIDTH_40; + } else if (phl_sta->chandef.band == BAND_ON_5G) { + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(1)) + phl_sta->chandef.bw = (wrole->chandef.bw < CHANNEL_WIDTH_80) ? + wrole->chandef.bw : CHANNEL_WIDTH_80; + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(2)) + *supp_mcs_len += 4; + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(3)) + *supp_mcs_len += 4; + } + + phl_sta->asoc_cap.he_ldpc = (GET_HE_PHY_CAP_LDPC_IN_PAYLOAD(ele_start) & role_cap->he_ldpc); + + if (phl_sta->asoc_cap.er_su) { + phl_sta->asoc_cap.ltf_gi = (BIT(RTW_GILTF_2XHE16) | + BIT(RTW_GILTF_2XHE08) | BIT(RTW_GILTF_1XHE16) | + (GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(ele_start) ? + BIT(RTW_GILTF_LGI_4XHE32) : 0) | + (GET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_SGI_4XHE08) : 0) | + (GET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_1XHE08) : 0)); + } else { + phl_sta->asoc_cap.ltf_gi = (BIT(RTW_GILTF_2XHE16) | + BIT(RTW_GILTF_2XHE08) | BIT(RTW_GILTF_1XHE16) | + (GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(ele_start) ? + BIT(RTW_GILTF_LGI_4XHE32) : 0) | + (GET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_SGI_4XHE08) : 0) | + (GET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_1XHE08) : 0)); + } + + phl_sta->asoc_cap.stbc_he_tx = GET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.stbc_he_rx = (GET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(ele_start) & role_cap->stbc_he_tx); + phl_sta->asoc_cap.doppler_tx = GET_HE_PHY_CAP_DOPPLER_TX(ele_start); + phl_sta->asoc_cap.doppler_rx = (GET_HE_PHY_CAP_DOPPLER_RX(ele_start) & role_cap->doppler_tx); + + phl_sta->asoc_cap.dcm_max_const_tx = + GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(ele_start); + if (phl_sta->asoc_cap.dcm_max_const_tx > role_cap->dcm_max_const_rx) + phl_sta->asoc_cap.dcm_max_const_tx = role_cap->dcm_max_const_rx; + + phl_sta->asoc_cap.dcm_max_nss_tx = (GET_HE_PHY_CAP_DCM_MAX_NSS_TX(ele_start) & role_cap->dcm_max_nss_rx); + + phl_sta->asoc_cap.dcm_max_const_rx = + GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(ele_start); + if (phl_sta->asoc_cap.dcm_max_const_rx > role_cap->dcm_max_const_tx) + phl_sta->asoc_cap.dcm_max_const_rx = role_cap->dcm_max_const_tx; + + phl_sta->asoc_cap.dcm_max_nss_rx = (GET_HE_PHY_CAP_DCM_MAX_NSS_RX(ele_start) & role_cap->dcm_max_nss_tx); + + phl_sta->asoc_cap.partial_bw_su_er = + GET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(ele_start); + phl_sta->asoc_cap.he_su_bfmr = GET_HE_PHY_CAP_SU_BFER(ele_start); + phl_sta->asoc_cap.he_su_bfme = GET_HE_PHY_CAP_SU_BFEE(ele_start); + phl_sta->asoc_cap.he_mu_bfmr = GET_HE_PHY_CAP_MU_BFER(ele_start); + phl_sta->asoc_cap.bfme_sts = + GET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.bfme_sts_greater_80mhz = + GET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.num_snd_dim = + GET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.num_snd_dim_greater_80mhz = + GET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.ng_16_su_fb = GET_HE_PHY_CAP_NG_16_SU_FEEDBACK(ele_start); + phl_sta->asoc_cap.ng_16_mu_fb = GET_HE_PHY_CAP_NG_16_MU_FEEDBACK(ele_start); + phl_sta->asoc_cap.cb_sz_su_fb = + GET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(ele_start); + phl_sta->asoc_cap.cb_sz_mu_fb = + GET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_su_bfm_fb = + GET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_mu_bfm_fb = + GET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_cqi_fb = GET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(ele_start); + phl_sta->asoc_cap.partial_bw_su_er = + GET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(ele_start); + phl_sta->asoc_cap.pwr_bst_factor = + GET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(ele_start); + phl_sta->asoc_cap.max_nc = GET_HE_PHY_CAP_MAX_NC(ele_start); + phl_sta->asoc_cap.stbc_tx_greater_80mhz = + (GET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(ele_start) & role_cap->stbc_rx_greater_80mhz); + phl_sta->asoc_cap.stbc_rx_greater_80mhz = + (GET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(ele_start) & role_cap->stbc_tx_greater_80mhz); + phl_sta->asoc_cap.dcm_max_ru = GET_HE_PHY_CAP_DCM_MAX_RU(ele_start); + phl_sta->asoc_cap.long_sigb_symbol = + GET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(ele_start); + phl_sta->asoc_cap.non_trig_cqi_fb = + GET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(ele_start); + phl_sta->asoc_cap.tx_1024q_ru = + (GET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(ele_start) & role_cap->rx_1024q_ru); + phl_sta->asoc_cap.rx_1024q_ru = + (GET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(ele_start) & role_cap->tx_1024q_ru); + phl_sta->asoc_cap.fbw_su_using_mu_cmprs_sigb = + GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(ele_start); + phl_sta->asoc_cap.fbw_su_using_mu_non_cmprs_sigb = + GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(ele_start); + + if (GET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(ele_start)) + phl_sta->asoc_cap.pkt_padding = 3; + else + phl_sta->asoc_cap.pkt_padding = GET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(ele_start); +} + +static void update_sta_he_supp_mcs_apmode(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start, u8 supp_mcs_len) +{ + rtw_he_set_asoc_cap_supp_mcs(padapter, phl_sta, ele_start, supp_mcs_len); +} + +static void update_sta_he_ppe_thre_apmode(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start) +{ + rtw_he_set_asoc_cap_ppe_thre(padapter, phl_sta, ele_start); +} + +void update_sta_he_info_apmode(_adapter *padapter, void *sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct rtw_phl_stainfo_t *phl_sta = psta->phl_sta; + struct he_priv *phepriv_sta = &psta->hepriv; + u8 *ele_start = NULL; + u8 supp_mcs_len = 4; + + if (phepriv_sta->he_option == _FALSE) + return; + + ele_start = &(phepriv_sta->he_cap[1]); + update_sta_he_mac_cap_apmode(padapter, phl_sta, ele_start); + + ele_start += HE_CAP_ELE_MAC_CAP_LEN; + update_sta_he_phy_cap_apmode(padapter, phl_sta, ele_start, &supp_mcs_len); + + ele_start += HE_CAP_ELE_PHY_CAP_LEN; + update_sta_he_supp_mcs_apmode(padapter, phl_sta, ele_start, supp_mcs_len); + + ele_start += supp_mcs_len; + update_sta_he_ppe_thre_apmode(padapter, phl_sta, ele_start); +} + +void update_hw_he_param(_adapter *padapter) +{ + /* CONFIG_80211AX_HE_TODO */ +} + +static void HE_mac_caps_handler(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start) +{ + phl_sta->asoc_cap.htc_rx = GET_HE_MAC_CAP_HTC_HE_SUPPORT(ele_start); + phl_sta->asoc_cap.twt = GET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(ele_start); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(ele_start)) << 1); + phl_sta->asoc_cap.trig_padding = GET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(ele_start); + phl_sta->asoc_cap.all_ack = GET_HE_MAC_CAP_ALL_ACK_SUPPORT(ele_start); + phl_sta->asoc_cap.a_ctrl = GET_HE_MAC_CAP_TRS_SUPPORT(ele_start); + phl_sta->asoc_cap.a_ctrl |= ((GET_HE_MAC_CAP_BRS_SUPPORT(ele_start)) << 1); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_BC_TWT_SUPPORT(ele_start)) << 2); + phl_sta->asoc_cap.a_ctrl |= ((GET_HE_MAC_CAP_OM_CTRL_SUPPORT(ele_start)) << 2); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(ele_start)) << 3); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_PSR_RESPONDER(ele_start)) << 4); + phl_sta->asoc_cap.ops = GET_HE_MAC_CAP_OPS_SUPPORT(ele_start); + phl_sta->asoc_cap.amsdu_in_ampdu = + GET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(ele_start); + phl_sta->asoc_cap.twt |= ((GET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(ele_start)) << 5); + phl_sta->asoc_cap.ht_vht_trig_rx = + GET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(ele_start); +} + +static void HE_phy_caps_handler(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start, u8 *supp_mcs_len) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *role_cap = &(wrole->proto_role_cap); + + if (phl_sta->chandef.band == BAND_ON_24G) { + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(0)) + phl_sta->chandef.bw = (wrole->chandef.bw < CHANNEL_WIDTH_40) ? + wrole->chandef.bw : CHANNEL_WIDTH_40; + } else if (phl_sta->chandef.band == BAND_ON_5G) { + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(1)) + phl_sta->chandef.bw = (wrole->chandef.bw < CHANNEL_WIDTH_80) ? + wrole->chandef.bw : CHANNEL_WIDTH_80; + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(2)) + *supp_mcs_len += 4; + if (GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(ele_start) & BIT(3)) + *supp_mcs_len += 4; + } + phl_sta->asoc_cap.he_ldpc = GET_HE_PHY_CAP_LDPC_IN_PAYLOAD(ele_start); + if (phl_sta->asoc_cap.er_su) { + phl_sta->asoc_cap.ltf_gi = (BIT(RTW_GILTF_2XHE16) | + BIT(RTW_GILTF_2XHE08) | BIT(RTW_GILTF_1XHE16) | + (GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(ele_start) ? + BIT(RTW_GILTF_LGI_4XHE32) : 0) | + (GET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_SGI_4XHE08) : 0) | + (GET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_1XHE08) : 0)); + } else { + phl_sta->asoc_cap.ltf_gi = (BIT(RTW_GILTF_2XHE16) | + BIT(RTW_GILTF_2XHE08) | BIT(RTW_GILTF_1XHE16) | + (GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(ele_start) ? + BIT(RTW_GILTF_LGI_4XHE32) : 0) | + (GET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_SGI_4XHE08) : 0) | + (GET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(ele_start) ? + BIT(RTW_GILTF_1XHE08) : 0)); + } + phl_sta->asoc_cap.stbc_he_tx = GET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.stbc_he_rx = (GET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(ele_start) & role_cap->stbc_he_tx); + phl_sta->asoc_cap.doppler_tx = GET_HE_PHY_CAP_DOPPLER_TX(ele_start); + phl_sta->asoc_cap.doppler_rx = (GET_HE_PHY_CAP_DOPPLER_RX(ele_start) & role_cap->doppler_tx); + phl_sta->asoc_cap.dcm_max_const_tx = + GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(ele_start); + phl_sta->asoc_cap.dcm_max_nss_tx = GET_HE_PHY_CAP_DCM_MAX_NSS_TX(ele_start); + phl_sta->asoc_cap.dcm_max_const_rx = + GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(ele_start); + phl_sta->asoc_cap.dcm_max_nss_rx = GET_HE_PHY_CAP_DCM_MAX_NSS_RX(ele_start); + phl_sta->asoc_cap.partial_bw_su_er = + GET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(ele_start); + phl_sta->asoc_cap.he_su_bfmr = GET_HE_PHY_CAP_SU_BFER(ele_start); + phl_sta->asoc_cap.he_su_bfme = GET_HE_PHY_CAP_SU_BFEE(ele_start); + phl_sta->asoc_cap.he_mu_bfmr = GET_HE_PHY_CAP_MU_BFER(ele_start); + phl_sta->asoc_cap.bfme_sts = + GET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.bfme_sts_greater_80mhz = + GET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.num_snd_dim = + GET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.num_snd_dim_greater_80mhz = + GET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(ele_start); + + RTW_INFO("%s: HE STA assoc_cap:\n", __func__); + RTW_INFO("- SU BFer: %d\n", phl_sta->asoc_cap.he_su_bfmr); + RTW_INFO("- SU BFee: %d\n", phl_sta->asoc_cap.he_su_bfme); + RTW_INFO("- MU BFer: %d\n", phl_sta->asoc_cap.he_mu_bfmr); + RTW_INFO("- BFee STS: %d\n", phl_sta->asoc_cap.bfme_sts); + RTW_INFO("- BFee STS(>80MHz): %d\n", phl_sta->asoc_cap.bfme_sts_greater_80mhz); + RTW_INFO("- BFer SND DIM number: %d\n", phl_sta->asoc_cap.num_snd_dim); + RTW_INFO("- BFer SND DIM number(>80MHz): %d\n", phl_sta->asoc_cap.num_snd_dim_greater_80mhz); + + phl_sta->asoc_cap.ng_16_su_fb = GET_HE_PHY_CAP_NG_16_SU_FEEDBACK(ele_start); + phl_sta->asoc_cap.ng_16_mu_fb = GET_HE_PHY_CAP_NG_16_MU_FEEDBACK(ele_start); + phl_sta->asoc_cap.cb_sz_su_fb = + GET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(ele_start); + phl_sta->asoc_cap.cb_sz_mu_fb = + GET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_su_bfm_fb = + GET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_mu_bfm_fb = + GET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(ele_start); + phl_sta->asoc_cap.trig_cqi_fb = GET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(ele_start); + phl_sta->asoc_cap.partial_bw_su_er = + GET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(ele_start); + phl_sta->asoc_cap.pwr_bst_factor = + GET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(ele_start); + phl_sta->asoc_cap.max_nc = GET_HE_PHY_CAP_MAX_NC(ele_start); + phl_sta->asoc_cap.stbc_tx_greater_80mhz = + GET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.stbc_rx_greater_80mhz = + GET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(ele_start); + phl_sta->asoc_cap.dcm_max_ru = GET_HE_PHY_CAP_DCM_MAX_RU(ele_start); + phl_sta->asoc_cap.long_sigb_symbol = + GET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(ele_start); + phl_sta->asoc_cap.non_trig_cqi_fb = + GET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(ele_start); + phl_sta->asoc_cap.tx_1024q_ru = + GET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(ele_start); + phl_sta->asoc_cap.rx_1024q_ru = + GET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(ele_start); + phl_sta->asoc_cap.fbw_su_using_mu_cmprs_sigb = + GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(ele_start); + phl_sta->asoc_cap.fbw_su_using_mu_non_cmprs_sigb = + GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(ele_start); + + if (GET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(ele_start)) + phl_sta->asoc_cap.pkt_padding = 3; + else + phl_sta->asoc_cap.pkt_padding = GET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(ele_start); +} + +static void HE_supp_mcs_handler(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start, u8 supp_mcs_len) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + + rtw_he_set_asoc_cap_supp_mcs(padapter, phl_sta, ele_start, supp_mcs_len); + phepriv->he_highest_rate = rtw_he_get_highest_rate(phl_sta->asoc_cap.he_rx_mcs); +} + +static void HE_ppe_thre_handler(_adapter *padapter, struct rtw_phl_stainfo_t *phl_sta, u8 *ele_start) +{ + rtw_he_set_asoc_cap_ppe_thre(padapter, phl_sta, ele_start); +} + +void HE_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_info *psta = NULL; + struct rtw_phl_stainfo_t *phl_sta = NULL; + u8 *ele_start = (&(pIE->data[0]) + 1); + u8 supp_mcs_len = 4; + + if (pIE == NULL) + return; + + if (phepriv->he_option == _FALSE) + return; + + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta == NULL) + return; + if (psta->phl_sta == NULL) + return; + + phl_sta = psta->phl_sta; + + /* HE MAC Caps */ + HE_mac_caps_handler(padapter, phl_sta, ele_start); + ele_start += HE_CAP_ELE_MAC_CAP_LEN; + + /* HE PHY Caps */ + HE_phy_caps_handler(padapter, phl_sta, ele_start, &supp_mcs_len); + ele_start += HE_CAP_ELE_PHY_CAP_LEN; + + /* HE Supp MCS Set */ + HE_supp_mcs_handler(padapter, phl_sta, ele_start, supp_mcs_len); + ele_start += supp_mcs_len; + + /* HE PPE Thresholds */ + HE_ppe_thre_handler(padapter, phl_sta, ele_start); + + pmlmeinfo->HE_enable = 1; +} + +void HE_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_info *psta = NULL; + struct rtw_phl_stainfo_t *phl_sta = NULL; + u8 *ele_start = (&(pIE->data[0]) + 1); + struct dvobj_priv *d; + void *phl; + u8 pre_bsscolor = 0; + u16 pre_rts_th = 0; + + if (pIE == NULL) + return; + + if (phepriv->he_option == _FALSE) + return; + + d = adapter_to_dvobj(padapter); + phl = GET_PHL_INFO(d); + + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta == NULL) + return; + if (psta->phl_sta == NULL) + return; + + phl_sta = psta->phl_sta; + phl_sta->tf_trs = _TRUE; + + phl_sta->asoc_cap.er_su = !GET_HE_OP_PARA_ER_SU_DISABLE(ele_start); + if (!GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(ele_start)) { + + pre_bsscolor = phl_sta->asoc_cap.bsscolor; + phl_sta->asoc_cap.bsscolor = GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(ele_start); + + /* rx thread & assoc timer callback, use cmd no_wait */ + if (pre_bsscolor != phl_sta->asoc_cap.bsscolor) { + RTW_INFO("%s, Update BSS Color = %d\n", __func__, phl_sta->asoc_cap.bsscolor); +#ifdef CONFIG_CMD_DISP + rtw_phl_cmd_wrole_change(phl, + padapter->phl_role, + WR_CHG_BSS_COLOR, + (u8 *)&phl_sta->asoc_cap.bsscolor, + sizeof(phl_sta->asoc_cap.bsscolor), + PHL_CMD_NO_WAIT, + 0); +#else + /* role change here, but no implementation for not CMD_DISP case */ +#endif + } + } + + pre_rts_th = phl_sta->asoc_cap.rts_th; + phl_sta->asoc_cap.rts_th = + GET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(ele_start); + + if ((phl_sta->asoc_cap.rts_th > 0) && + (phl_sta->asoc_cap.rts_th != TXOP_DUR_RTS_TH_DISABLED)) { + struct rtw_rts_threshold val = {0}; + + /* time preference */ + val.rts_len_th = 0xffff; + /* IE field unit 32us, parameter unit 1us */ + val.rts_time_th = phl_sta->asoc_cap.rts_th * 32; + /* rx thread & assoc timer callback, use cmd no_wait */ + if (pre_rts_th != phl_sta->asoc_cap.rts_th) { + RTW_INFO("%s, Update TXOP Duration RTS Threshold =%d\n", __func__, phl_sta->asoc_cap.rts_th); +#ifdef CONFIG_CMD_DISP + rtw_phl_cmd_wrole_change(phl, + padapter->phl_role, + WR_CHG_RTS_TH, + (u8 *)&val, + sizeof(struct rtw_rts_threshold), + PHL_CMD_NO_WAIT, + 0); +#else + /* role change here, but no implementation for not CMD_DISP case */ +#endif + } + } +} + +void HE_mu_edca_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE, u8 first) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_info *psta = NULL; + struct rtw_phl_stainfo_t *phl_sta = NULL; + u8 *ele_start = (&(pIE->data[0]) + 1); + struct dvobj_priv *d; + void *phl; + struct rtw_mu_edca_param edca = {0}; + u8 pre_cnt = 0, cur_cnt = 0; + u8 i = 0; + + if (pIE == NULL) + return; + + if (phepriv->he_option == _FALSE) + return; + + d = adapter_to_dvobj(padapter); + phl = GET_PHL_INFO(d); + if (!phl) + return; + + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta == NULL) + return; + if (psta->phl_sta == NULL) + return; + + phl_sta = psta->phl_sta; + + pre_cnt = phepriv->pre_he_muedca_cnt; + cur_cnt = GET_HE_MU_EDCA_QOS_INFO_UPDATE_CNT(ele_start); + if (cur_cnt != pre_cnt || first == _TRUE) { + phepriv->pre_he_muedca_cnt = cur_cnt; + phl_sta->asoc_cap.mu_edca[0].ac = + GET_HE_MU_EDCA_BE_ACI(ele_start); + phl_sta->asoc_cap.mu_edca[0].aifsn = + GET_HE_MU_EDCA_BE_AIFSN(ele_start); + phl_sta->asoc_cap.mu_edca[0].cw = + GET_HE_MU_EDCA_BE_ECW_MIN_MAX(ele_start); + phl_sta->asoc_cap.mu_edca[0].timer = + GET_HE_MU_EDCA_BE_TIMER(ele_start); + phl_sta->asoc_cap.mu_edca[1].ac = + GET_HE_MU_EDCA_BK_ACI(ele_start); + phl_sta->asoc_cap.mu_edca[1].aifsn = + GET_HE_MU_EDCA_BK_AIFSN(ele_start); + phl_sta->asoc_cap.mu_edca[1].cw = + GET_HE_MU_EDCA_BK_ECW_MIN_MAX(ele_start); + phl_sta->asoc_cap.mu_edca[1].timer = + GET_HE_MU_EDCA_BK_TIMER(ele_start); + phl_sta->asoc_cap.mu_edca[2].ac = + GET_HE_MU_EDCA_VI_ACI(ele_start); + phl_sta->asoc_cap.mu_edca[2].aifsn = + GET_HE_MU_EDCA_VI_AIFSN(ele_start); + phl_sta->asoc_cap.mu_edca[2].cw = + GET_HE_MU_EDCA_VI_ECW_MIN_MAX(ele_start); + phl_sta->asoc_cap.mu_edca[2].timer = + GET_HE_MU_EDCA_VI_TIMER(ele_start); + phl_sta->asoc_cap.mu_edca[3].ac = + GET_HE_MU_EDCA_VO_ACI(ele_start); + phl_sta->asoc_cap.mu_edca[3].aifsn = + GET_HE_MU_EDCA_VO_AIFSN(ele_start); + phl_sta->asoc_cap.mu_edca[3].cw = + GET_HE_MU_EDCA_VO_ECW_MIN_MAX(ele_start); + phl_sta->asoc_cap.mu_edca[3].timer = + GET_HE_MU_EDCA_VO_TIMER(ele_start); + for (i = 0; i < 4; i++) { +#ifdef CONFIG_CMD_DISP + rtw_phl_cmd_wrole_change(phl, + padapter->phl_role, + WR_CHG_MU_EDCA_PARAM, + (u8 *)&phl_sta->asoc_cap.mu_edca[i], + sizeof(struct rtw_mu_edca_param), + PHL_CMD_NO_WAIT, + 0); +#endif + RTW_INFO("%s, Update HE MU EDCA AC(%d) aifsn(%d) cw(0x%x) timer(0x%x)\n", + __func__, + phl_sta->asoc_cap.mu_edca[i].ac, + phl_sta->asoc_cap.mu_edca[i].aifsn, + phl_sta->asoc_cap.mu_edca[i].cw, + phl_sta->asoc_cap.mu_edca[i].timer); + } + + if (first) { +#ifdef CONFIG_CMD_DISP + rtw_phl_cmd_wrole_change(phl, + padapter->phl_role, + WR_CHG_MU_EDCA_CFG, + (u8 *)&first, + sizeof(first), + PHL_CMD_NO_WAIT, + 0); +#else + /* role change here, but no implementation for not CMD_DISP case */ +#endif + } + } +} + +static int rtw_build_he_mac_caps(struct protocol_cap_t *proto_cap, u8 *pbuf) +{ + /* Set HE MAC Capabilities Information */ + + int info_len = HE_CAP_ELE_MAC_CAP_LEN; + + if (proto_cap->htc_rx) + SET_HE_MAC_CAP_HTC_HE_SUPPORT(pbuf, 1); + + if (proto_cap->twt & BIT(0)) + SET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(pbuf, 1); + + if (proto_cap->twt & BIT(1)) + SET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(pbuf, 1); + + if (proto_cap->trig_padding) + SET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(pbuf, + proto_cap->trig_padding); + + if (proto_cap->all_ack) + SET_HE_MAC_CAP_ALL_ACK_SUPPORT(pbuf, 1); + + if (proto_cap->htc_rx && (proto_cap->a_ctrl & BIT(0))) + SET_HE_MAC_CAP_TRS_SUPPORT(pbuf, 1); + + if (proto_cap->a_ctrl & BIT(1)) + SET_HE_MAC_CAP_BRS_SUPPORT(pbuf, 1); + + if (proto_cap->twt & BIT(2)) + SET_HE_MAC_CAP_BC_TWT_SUPPORT(pbuf, 1); + + if (proto_cap->htc_rx && (proto_cap->a_ctrl & BIT(2))) + SET_HE_MAC_CAP_OM_CTRL_SUPPORT(pbuf, 1); + + SET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(pbuf, 2); + + if (proto_cap->twt & BIT(3)) + SET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(pbuf, 1); + + if (proto_cap->twt & BIT(4)) + SET_HE_MAC_CAP_PSR_RESPONDER(pbuf, 1); + + if (proto_cap->ops) + SET_HE_MAC_CAP_OPS_SUPPORT(pbuf, 1); + + if (proto_cap->amsdu_in_ampdu) + SET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(pbuf, 1); + + if (proto_cap->twt & BIT(5)) + SET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(pbuf, 1); + + if (proto_cap->ht_vht_trig_rx) + SET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(pbuf, 1); + + return info_len; +} + +static int rtw_build_he_phy_caps(struct protocol_cap_t *proto_cap, u8 *pbuf) +{ + /* struct rtw_chan_def *chan_def = &(wrole->chandef); */ + /* Set HE PHY Capabilities Information */ + + int info_len = HE_CAP_ELE_PHY_CAP_LEN; + +#if 1 + SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(pbuf, (BIT(0) | BIT(1))); +#else + u8 bw_cap = 0; + + if (phy_cap->bw_sup & BW_CAP_40M) + bw_cap |= BIT(0); + if (phy_cap->bw_sup & BW_CAP_80M) + bw_cap |= BIT(1); + + if (chan_def->band == BAND_ON_24G) { + if (chan_def->bw == CHANNEL_WIDTH_40) + SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(pbuf, BIT(0)); + } else if (chan_def->band == BAND_ON_5G) { + if (chan_def->bw == CHANNEL_WIDTH_80) + SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(pbuf, BIT(1)); + else if (chan_def->bw == CHANNEL_WIDTH_160) + SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(pbuf, (BIT(1) | BIT(2))); + else if (chan_def->bw == CHANNEL_WIDTH_80_80) + SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(pbuf, (BIT(1) | BIT(3))); + } +#endif + + SET_HE_PHY_CAP_DEVICE_CLASS(pbuf, HE_DEV_CLASS_A); + + if (proto_cap->he_ldpc) + SET_HE_PHY_CAP_LDPC_IN_PAYLOAD(pbuf, 1); + + SET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(pbuf, 1); + + if (proto_cap->he_rx_ndp_4x32) { + SET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(pbuf, 1); + RTW_INFO("NDP_4x32 is set.\n");; + } + + if (proto_cap->stbc_he_tx) + SET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(pbuf, 1); + + if (proto_cap->stbc_he_rx) + SET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(pbuf, 1); + + if (proto_cap->doppler_tx) + SET_HE_PHY_CAP_DOPPLER_TX(pbuf, 1); + + if (proto_cap->doppler_rx) + SET_HE_PHY_CAP_DOPPLER_RX(pbuf, 1); + + if (proto_cap->dcm_max_const_tx) + SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(pbuf, + proto_cap->dcm_max_const_tx); + + if (proto_cap->dcm_max_nss_tx) + SET_HE_PHY_CAP_DCM_MAX_NSS_TX(pbuf, 1); + + if (proto_cap->dcm_max_const_rx) + SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(pbuf, + proto_cap->dcm_max_const_rx); + + if (proto_cap->dcm_max_nss_rx) + SET_HE_PHY_CAP_DCM_MAX_NSS_RX(pbuf, 1); + + if (proto_cap->partial_bw_su_in_mu) + SET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(pbuf, 1); + + if (proto_cap->he_su_bfmr) + SET_HE_PHY_CAP_SU_BFER(pbuf, 1); + + if (proto_cap->he_su_bfme) + SET_HE_PHY_CAP_SU_BFEE(pbuf, 1); + + if (proto_cap->he_mu_bfmr) + SET_HE_PHY_CAP_MU_BFER(pbuf, 1); + + if (proto_cap->bfme_sts) + SET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(pbuf, + proto_cap->bfme_sts); + + if (proto_cap->bfme_sts_greater_80mhz) + SET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(pbuf, + proto_cap->bfme_sts_greater_80mhz); + + if (proto_cap->num_snd_dim) + SET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(pbuf, + proto_cap->num_snd_dim); + + if (proto_cap->num_snd_dim_greater_80mhz) + SET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(pbuf, + proto_cap->num_snd_dim_greater_80mhz); + + if (proto_cap->ng_16_su_fb) + SET_HE_PHY_CAP_NG_16_SU_FEEDBACK(pbuf, 1); + + if (proto_cap->ng_16_mu_fb) + SET_HE_PHY_CAP_NG_16_MU_FEEDBACK(pbuf, 1); + + if (proto_cap->cb_sz_su_fb) + SET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(pbuf, 1); + + if (proto_cap->cb_sz_mu_fb) + SET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(pbuf, 1); + + if (proto_cap->trig_su_bfm_fb) + SET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(pbuf, 1); + + if (proto_cap->trig_mu_bfm_fb) + SET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(pbuf, 1); + + if (proto_cap->trig_cqi_fb) + SET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(pbuf, 1); + + if (proto_cap->partial_bw_su_er) + SET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(pbuf, 1); + + if (proto_cap->pwr_bst_factor) + SET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(pbuf, 1); + + SET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(pbuf, 1); + + if (proto_cap->max_nc) + SET_HE_PHY_CAP_MAX_NC(pbuf, proto_cap->max_nc); + + if (proto_cap->stbc_tx_greater_80mhz) + SET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(pbuf, 1); + + if (proto_cap->stbc_rx_greater_80mhz) + SET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(pbuf, 1); + + SET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(pbuf, 1); + SET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(pbuf, 1); + + if (proto_cap->dcm_max_ru) + SET_HE_PHY_CAP_DCM_MAX_RU(pbuf, proto_cap->dcm_max_ru); + + if (proto_cap->long_sigb_symbol) + SET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(pbuf, 1); + + if (proto_cap->non_trig_cqi_fb) + SET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(pbuf, 1); + + if (proto_cap->tx_1024q_ru) + SET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(pbuf, 1); + + if (proto_cap->rx_1024q_ru) + SET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(pbuf, 1); + + if (proto_cap->fbw_su_using_mu_cmprs_sigb) + SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(pbuf, 1); + + if (proto_cap->fbw_su_using_mu_non_cmprs_sigb) + SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(pbuf, 1); + + if (proto_cap->pkt_padding) + SET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(pbuf, + proto_cap->pkt_padding); + + return info_len; +} + +static int rtw_build_he_supp_mcs(struct protocol_cap_t *proto_cap, u8 *pbuf) +{ + + /* struct rtw_chan_def *chan_def = &(wrole->chandef); */ + + /* Set HE Supported MCS and NSS Set */ + + int info_len = 4; + + _rtw_memset(pbuf, HE_MSC_NOT_SUPP_BYTE, info_len); + + _rtw_memcpy(pbuf, proto_cap->he_rx_mcs, HE_CAP_ELE_SUPP_MCS_LEN_RX_80M); + + _rtw_memcpy(pbuf + 2, proto_cap->he_tx_mcs, HE_CAP_ELE_SUPP_MCS_LEN_TX_80M); + + return info_len; +} + +static int rtw_build_he_ppe_thre(struct protocol_cap_t *proto_cap, u8 *pbuf) +{ + /* Set HE PPE Thresholds (optional) */ + + int info_len = 0; + + return info_len; +} + +u32 rtw_get_dft_he_cap_ie(_adapter *padapter, struct phy_cap_t *phy_cap, + struct protocol_cap_t *proto_cap, u8 *pbuf) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + u32 he_cap_total_len = 0, len = 0; + u8* pcap_start = phepriv->he_cap; + u8* pcap = pcap_start; + + _rtw_memset(pcap, 0, HE_CAP_ELE_MAX_LEN); + + /* Ele ID Extension */ + *pcap++ = WLAN_EID_EXTENSION_HE_CAPABILITY; + + /* HE MAC Caps */ + pcap += rtw_build_he_mac_caps(proto_cap, pcap); + + /* HE PHY Caps */ + pcap += rtw_build_he_phy_caps(proto_cap, pcap); + + /* HE Supported MCS and NSS Set */ + pcap += rtw_build_he_supp_mcs(proto_cap, pcap); + + /* HE PPE Thresholds (optional) */ + pcap += rtw_build_he_ppe_thre(proto_cap, pcap); + + he_cap_total_len = (pcap - pcap_start); + + pbuf = rtw_set_ie(pbuf, WLAN_EID_EXTENSION, he_cap_total_len, pcap_start, &len); + + return len; +} + +u32 rtw_build_he_cap_ie(_adapter *padapter, u8 *pbuf) +{ + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_cap = &(wrole->proto_role_cap); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + u32 he_cap_total_len = 0, len = 0; + u8* pcap_start = phepriv->he_cap; + u8* pcap = pcap_start; + + _rtw_memset(pcap, 0, HE_CAP_ELE_MAX_LEN); + + /* Ele ID Extension */ + *pcap++ = WLAN_EID_EXTENSION_HE_CAPABILITY; + + /* HE MAC Caps */ + pcap += rtw_build_he_mac_caps(proto_cap, pcap); + + /* HE PHY Caps */ + pcap += rtw_build_he_phy_caps(proto_cap, pcap); + + /* HE Supported MCS and NSS Set */ + pcap += rtw_build_he_supp_mcs(proto_cap, pcap); + + /* HE PPE Thresholds (optional) */ + pcap += rtw_build_he_ppe_thre(proto_cap, pcap); + + he_cap_total_len = (pcap - pcap_start); + + pbuf = rtw_set_ie(pbuf, WLAN_EID_EXTENSION, he_cap_total_len, pcap_start, &len); + + return len; +} + +u32 rtw_restructure_he_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + u32 ielen; + u8 *out_he_op_ie, *he_cap_ie, *he_op_ie; + u8 he_cap_eid_ext = WLAN_EID_EXTENSION_HE_CAPABILITY; + u8 he_op_eid_ext = WLAN_EID_EXTENSION_HE_OPERATION; + + rtw_he_use_default_setting(padapter); + + he_cap_ie = rtw_get_ie_ex(in_ie + 12, in_len - 12, WLAN_EID_EXTENSION, &he_cap_eid_ext, 1, NULL, &ielen); + if (!he_cap_ie || (ielen > (HE_CAP_ELE_MAX_LEN + 2))) + goto exit; + he_op_ie = rtw_get_ie_ex(in_ie + 12, in_len - 12, WLAN_EID_EXTENSION, &he_op_eid_ext, 1, NULL, &ielen); + if (!he_op_ie || (ielen > (HE_OPER_ELE_MAX_LEN + 2))) + goto exit; + + /* TODO: channel width adjustment according to current chan plan or request chan plan */ + + *pout_len += rtw_build_he_cap_ie(padapter, out_ie + *pout_len); + + phepriv->he_option = _TRUE; + +exit: + return phepriv->he_option; +} + +static int rtw_build_he_oper_params(_adapter *padapter, u8 *pbuf) +{ + /* Set HE Operation Parameters */ + + int info_len = HE_OPER_PARAMS_LEN; + + SET_HE_OP_PARA_DEFAULT_PE_DUR(pbuf, 0x4); + + return info_len; +} + +static int rtw_build_he_oper_bss_color_info(_adapter *padapter, u8 *pbuf) +{ + /* Set BSS Color Information */ + int info_len = HE_OPER_BSS_COLOR_INFO_LEN; + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_cap = &(wrole->proto_role_cap); + + SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(pbuf, proto_cap->bsscolor); + + return info_len; +} + +static int rtw_build_he_oper_basic_mcs_set(_adapter *padapter, u8 *pbuf) +{ + /* Set Basic HE-MCS and NSS Set */ + + int info_len = HE_OPER_BASIC_MCS_LEN; + + _rtw_memset(pbuf, HE_MSC_NOT_SUPP_BYTE, info_len); + + SET_HE_OP_BASIC_MCS_1SS(pbuf, HE_MCS_SUPP_MSC0_TO_MSC11); + SET_HE_OP_BASIC_MCS_2SS(pbuf, HE_MCS_SUPP_MSC0_TO_MSC11); + + return info_len; +} + +static int rtw_build_vht_oper_info(_adapter *padapter, u8 *pbuf) +{ + /* Set VHT Operation Information (optional) */ + + int info_len = 0; + + return info_len; +} + +static int rtw_build_max_cohost_bssid_ind(_adapter *padapter, u8 *pbuf) +{ + /* Set Max Co-Hosted BSSID Indicator (optional) */ + + int info_len = 0; + + return info_len; +} + +static int rtw_build_6g_oper_info(_adapter *padapter, u8 *pbuf) +{ + /* Set 6GHz Operation Information (optional) */ + + int info_len = 0; + + return info_len; +} + +u32 rtw_build_he_operation_ie(_adapter *padapter, u8 *pbuf) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct he_priv *phepriv = &pmlmepriv->hepriv; + u32 he_oper_total_len = 0, len = 0; + u8* poper_start = phepriv->he_op; + u8* poper = poper_start; + + _rtw_memset(poper, 0, HE_OPER_ELE_MAX_LEN); + + /* Ele ID Extension */ + *poper++ = WLAN_EID_EXTENSION_HE_OPERATION; + + /* HE Oper Params */ + poper += rtw_build_he_oper_params(padapter, poper); + + /* BSS Color Info */ + poper += rtw_build_he_oper_bss_color_info(padapter, poper); + + /* Basic MCS and NSS Set */ + poper += rtw_build_he_oper_basic_mcs_set(padapter, poper); + + /* VHT Oper Info */ + poper += rtw_build_vht_oper_info(padapter, poper); + + /* Max Co-Hosted BSSID Indicator */ + poper += rtw_build_max_cohost_bssid_ind(padapter, poper); + + /* 6G Oper Info */ + poper += rtw_build_6g_oper_info(padapter, poper); + + he_oper_total_len = (poper - poper_start); + + pbuf = rtw_set_ie(pbuf, WLAN_EID_EXTENSION, he_oper_total_len, poper_start, &len); + + return len; +} + +void HEOnAssocRsp(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ht_AMPDU_len; + + if (!pmlmeinfo->VHT_enable) + return; + + if (!pmlmeinfo->HE_enable) + return; + + RTW_INFO("%s\n", __FUNCTION__); + + /* AMPDU related settings here ? */ +} + +void rtw_he_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 he_cap_eid_ext = WLAN_EID_EXTENSION_HE_CAPABILITY; + u8 cap_len, operation_len; + uint len = 0; + sint ie_len = 0; + u8 *p = NULL; + + p = rtw_get_ie_ex(pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_, + WLAN_EID_EXTENSION, &he_cap_eid_ext, 1, NULL, &ie_len); + if (p && ie_len > 0) + return; + + rtw_he_use_default_setting(padapter); + + cap_len = rtw_build_he_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength); + pnetwork->IELength += cap_len; + + operation_len = rtw_build_he_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength); + pnetwork->IELength += operation_len; + + pmlmepriv->hepriv.he_option = _TRUE; +} + +void rtw_he_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 he_cap_eid_ext = WLAN_EID_EXTENSION_HE_CAPABILITY; + u8 he_op_eid_ext = WLAN_EID_EXTENSION_HE_OPERATION; + + rtw_remove_bcn_ie_ex(padapter, pnetwork, WLAN_EID_EXTENSION, &he_cap_eid_ext, 1); + rtw_remove_bcn_ie_ex(padapter, pnetwork, WLAN_EID_EXTENSION, &he_op_eid_ext, 1); + + pmlmepriv->hepriv.he_option = _FALSE; +} + +u8 rtw_he_htc_en(_adapter *padapter, struct sta_info *psta) +{ + return 1; +} + +void rtw_he_fill_htc(_adapter *padapter, struct pkt_attrib *pattrib, u32 *phtc_buf) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rtw_he_actrl_om *cur_om_info = &(pmlmepriv->hepriv.om_info); + + SET_HE_VAR_HTC(phtc_buf); + SET_HE_VAR_HTC_CID_CAS(phtc_buf); + + /* CONFIG_80211AX_HE_TODO */ + + if ((pattrib->type == WIFI_DATA_TYPE && + cur_om_info->actrl_om_normal_tx && + cur_om_info->actrl_om_normal_tx_cnt != 0) || + pattrib->type == WIFI_MGT_TYPE) { + + SET_HE_VAR_HTC_CID_OM(phtc_buf); + SET_HE_VAR_HTC_OM_RX_NSS(phtc_buf, cur_om_info->om_actrl_ele.rx_nss); + SET_HE_VAR_HTC_OM_CH_WIDTH(phtc_buf, cur_om_info->om_actrl_ele.channel_width); + SET_HE_VAR_HTC_OM_UL_MU_DIS(phtc_buf, cur_om_info->om_actrl_ele.ul_mu_disable); + SET_HE_VAR_HTC_OM_TX_NSTS(phtc_buf, cur_om_info->om_actrl_ele.tx_nsts); + SET_HE_VAR_HTC_OM_ER_SU_DIS(phtc_buf, cur_om_info->om_actrl_ele.er_su_disable); + SET_HE_VAR_HTC_OM_DL_MU_MIMO_RR(phtc_buf, cur_om_info->om_actrl_ele.dl_mu_mimo_rr); + SET_HE_VAR_HTC_OM_UL_MU_DATA_DIS(phtc_buf, cur_om_info->om_actrl_ele.ul_mu_data_disable); + if (cur_om_info->actrl_om_normal_tx_cnt) { + /*RTW_INFO("%s, cur_om_info->actrl_om_normal_tx_cnt=%d\n", __func__, cur_om_info->actrl_om_normal_tx_cnt);*/ + cur_om_info->actrl_om_normal_tx_cnt --; + } + } + +} + +void rtw_he_set_om_info(_adapter *padapter, u8 om_mask, struct rtw_he_actrl_om *om_info) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rtw_he_actrl_om *cur_om_info = &(pmlmepriv->hepriv.om_info); + + if (om_mask & OM_RX_NSS) + cur_om_info->om_actrl_ele.rx_nss = om_info->om_actrl_ele.rx_nss; + + if (om_mask & OM_CH_BW) + cur_om_info->om_actrl_ele.channel_width= om_info->om_actrl_ele.channel_width; + + if (om_mask & OM_UL_MU_DIS) + cur_om_info->om_actrl_ele.ul_mu_disable= om_info->om_actrl_ele.ul_mu_disable; + + if (om_mask & OM_TX_NSTS) + cur_om_info->om_actrl_ele.tx_nsts= om_info->om_actrl_ele.tx_nsts; + + if (om_mask & OM_ER_SU_DIS) + cur_om_info->om_actrl_ele.er_su_disable= om_info->om_actrl_ele.er_su_disable; + + if (om_mask & OM_DL_MU_RR) + cur_om_info->om_actrl_ele.dl_mu_mimo_rr= om_info->om_actrl_ele.dl_mu_mimo_rr; + + if (om_mask & OM_UL_MU_DATA_DIS) + cur_om_info->om_actrl_ele.ul_mu_data_disable= om_info->om_actrl_ele.ul_mu_data_disable; + + cur_om_info->actrl_om_normal_tx = om_info->actrl_om_normal_tx; + cur_om_info->actrl_om_normal_tx_cnt = om_info->actrl_om_normal_tx_cnt; +#if 0 + RTW_INFO("%s, cur_om_info->om_actrl_ele.rx_nss = %d\n", __func__, cur_om_info->om_actrl_ele.rx_nss); + RTW_INFO("%s, cur_om_info->om_actrl_ele.channel_width = %d\n", __func__, cur_om_info->om_actrl_ele.channel_width); + RTW_INFO("%s, cur_om_info->om_actrl_ele.ul_mu_disable = %d\n", __func__, cur_om_info->om_actrl_ele.ul_mu_disable); + RTW_INFO("%s, cur_om_info->om_actrl_ele.tx_nsts = %d\n", __func__, cur_om_info->om_actrl_ele.tx_nsts); + RTW_INFO("%s, cur_om_info->om_actrl_ele.er_su_disable = %d\n", __func__, cur_om_info->om_actrl_ele.er_su_disable); + RTW_INFO("%s, cur_om_info->om_actrl_ele.dl_mu_mimo_rr = %d\n", __func__, cur_om_info->om_actrl_ele.dl_mu_mimo_rr); + RTW_INFO("%s, cur_om_info->om_actrl_ele.ul_mu_data_disable = %d\n", __func__, cur_om_info->om_actrl_ele.ul_mu_data_disable); +#endif +} + +void rtw_he_init_om_info(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rtw_he_actrl_om *cur_om_info = &(pmlmepriv->hepriv.om_info); + struct rtw_wifi_role_t *wrole = padapter->phl_role; + + cur_om_info->om_actrl_ele.rx_nss = wrole->proto_role_cap.nss_rx - 1; + + switch (wrole->chandef.bw) { + case CHANNEL_WIDTH_20: + cur_om_info->om_actrl_ele.channel_width = 0; + break; + case CHANNEL_WIDTH_40: + cur_om_info->om_actrl_ele.channel_width = 1; + break; + case CHANNEL_WIDTH_80: + cur_om_info->om_actrl_ele.channel_width = 2; + break; + case CHANNEL_WIDTH_160: + case CHANNEL_WIDTH_80_80: + cur_om_info->om_actrl_ele.channel_width = 3; + break; + default: + RTW_WARN("%s, HE OM control not support CH BW (%d), set to 0 (20M)\n", __func__, wrole->chandef.bw); + cur_om_info->om_actrl_ele.channel_width = 0; + break; + } + + cur_om_info->om_actrl_ele.ul_mu_disable = _FALSE; + cur_om_info->om_actrl_ele.tx_nsts = wrole->proto_role_cap.nss_tx - 1; + cur_om_info->om_actrl_ele.er_su_disable = _FALSE; + cur_om_info->om_actrl_ele.dl_mu_mimo_rr = _FALSE; + cur_om_info->om_actrl_ele.ul_mu_data_disable = _FALSE; + cur_om_info->actrl_om_normal_tx = _FALSE; + cur_om_info->actrl_om_normal_tx_cnt = 0; + +} + + +#endif /* CONFIG_80211AX_HE */ + diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c index d9bf9cb..e2843f1 100644 --- a/core/rtw_ieee80211.c +++ b/core/rtw_ieee80211.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -14,12 +14,8 @@ *****************************************************************************/ #define _IEEE80211_C -#ifdef CONFIG_PLATFORM_INTEL_BYT - #include -#endif #include - u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; u16 RTW_WPA_VERSION = 1; u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 }; @@ -31,12 +27,16 @@ u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 }; u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; +u8 WPA_CIPHER_SUITE_AES_CMAC[] = { 0x00, 0x50, 0xf2, 6 }; +u8 WPA_CIPHER_SUITE_GCMP[] = { 0x00, 0x50, 0xf2, 8 }; +u8 WPA_CIPHER_SUITE_GCMP_256[] = { 0x00, 0x50, 0xf2, 9 }; +u8 WPA_CIPHER_SUITE_CCMP_256[] = { 0x00, 0x50, 0xf2, 10 }; u16 RSN_VERSION_BSD = 1; u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; -u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; +/*u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };*/ u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; u8 RSN_CIPHER_SUITE_AES_128_CMAC[] = { 0x00, 0x0f, 0xac, 6 }; u8 RSN_CIPHER_SUITE_GCMP[] = { 0x00, 0x0f, 0xac, 8 }; @@ -62,6 +62,7 @@ u8 WLAN_AKM_FILS_SHA256[] = {0x00, 0x0f, 0xac, 14}; u8 WLAN_AKM_FILS_SHA384[] = {0x00, 0x0f, 0xac, 15}; u8 WLAN_AKM_FT_FILS_SHA256[] = {0x00, 0x0f, 0xac, 16}; u8 WLAN_AKM_FT_FILS_SHA384[] = {0x00, 0x0f, 0xac, 17}; + /* ----------------------------------------------------------- * for adhoc-master to generate ie and provide supported-rate to fw * ----------------------------------------------------------- */ @@ -84,20 +85,6 @@ u8 WIFI_OFDMRATES[] = { IEEE80211_OFDM_RATE_54MB }; -const char *MGN_RATE_STR(enum MGN_RATE rate) -{ - u8 hw_rate; - - if (rate == MGN_MCS32) - return "MCS32"; - - hw_rate = MRateToHwRate(rate); - if (hw_rate == DESC_RATE1M && rate != MGN_1M) - hw_rate = DESC_RATE_NUM; /* invalid case */ - - return HDATA_RATE(hw_rate); -} - u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; @@ -239,16 +226,16 @@ int rtw_check_network_type(unsigned char *rate, int ratelen, int channel) { if (channel > 14) { if ((rtw_is_cckrates_included(rate)) == _TRUE) - return WIRELESS_INVALID; + return WLAN_MD_INVALID; else - return WIRELESS_11A; + return WLAN_MD_11A; } else { /* could be pure B, pure G, or B/G */ if ((rtw_is_cckratesonly_included(rate)) == _TRUE) - return WIRELESS_11B; + return WLAN_MD_11B; else if ((rtw_is_cckrates_included(rate)) == _TRUE) - return WIRELESS_11BG; + return WLAN_MD_11BG; else - return WIRELESS_11G; + return WLAN_MD_11G; } } @@ -266,7 +253,7 @@ u8 *rtw_set_ie ( u8 *pbuf, sint index, - uint len, + uint len, /* IE content length, not entire IE length */ const u8 *source, uint *frlen /* frame length */ ) @@ -297,26 +284,26 @@ inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) { - if (ch_offset == SCN) - return HAL_PRIME_CHNL_OFFSET_DONT_CARE; - else if (ch_offset == SCA) - return HAL_PRIME_CHNL_OFFSET_LOWER; - else if (ch_offset == SCB) - return HAL_PRIME_CHNL_OFFSET_UPPER; + if (ch_offset == IEEE80211_SCN) + return CHAN_OFFSET_NO_EXT; + else if (ch_offset == IEEE80211_SCA) + return CHAN_OFFSET_UPPER; + else if (ch_offset == IEEE80211_SCB) + return CHAN_OFFSET_LOWER; - return HAL_PRIME_CHNL_OFFSET_DONT_CARE; + return CHAN_OFFSET_NO_EXT; } inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) { - if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) - return SCN; - else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) - return SCA; - else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) - return SCB; + if (ch_offset == CHAN_OFFSET_NO_EXT) + return IEEE80211_SCN; + else if (ch_offset == CHAN_OFFSET_UPPER) + return IEEE80211_SCA; + else if (ch_offset == CHAN_OFFSET_LOWER) + return IEEE80211_SCB; - return SCN; + return IEEE80211_SCN; } inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset) @@ -413,6 +400,60 @@ u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_le return (u8 *)target_ie; } +/** + * rtw_ies_update_ie - Find matching IEs and update it + * + * @ies: address of IEs to search + * @ies_len: address of length of ies, will update to new length + * @offset: the offset to start scarch + * @eid: element ID to match + * @content: new content will update to matching element + * @content_len: length of new content + * Returns: _SUCCESS: ies is updated, _FAIL: not updated + */ +u8 rtw_ies_update_ie(u8 *ies, uint *ies_len, uint ies_offset, u8 eid, const u8 *content, u8 content_len) +{ + u8 ret = _FAIL; + u8 *target_ie; + u32 target_ielen; + u8 *start, *remain_ies = NULL, *backup_ies = NULL; + uint search_len, remain_len = 0; + sint offset; + + if (ies == NULL || *ies_len == 0 || *ies_len <= ies_offset) + goto exit; + + start = ies + ies_offset; + search_len = *ies_len - ies_offset; + + target_ie = rtw_get_ie(start, eid, &target_ielen, search_len); + if (target_ie && target_ielen) { + if (target_ielen != content_len) { + remain_ies = target_ie + 2 + target_ielen; + remain_len = search_len - (remain_ies - start); + + backup_ies = rtw_malloc(remain_len); + if (!backup_ies) + goto exit; + + _rtw_memcpy(backup_ies, remain_ies, remain_len); + } + + _rtw_memcpy(target_ie + 2, content, content_len); + *(target_ie + 1) = content_len; + ret = _SUCCESS; + + if (target_ielen != content_len) { + remain_ies = target_ie + 2 + content_len; + _rtw_memcpy(remain_ies, backup_ies, remain_len); + offset = content_len - target_ielen; + *ies_len = *ies_len + offset; + } + } +exit: + return ret; +} + /** * rtw_ies_remove_ie - Find matching IEs and remove * @ies: Address of IEs to search @@ -457,32 +498,24 @@ int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 o return ret; } -void rtw_set_supported_rate(u8 *SupportedRates, uint mode) +void rtw_set_supported_rate(u8 *SupportedRates, uint mode, u8 ch) { + int is_2G_band = 1; + + if (ch > 14) + is_2G_band = 0; _rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); - switch (mode) { - case WIRELESS_11B: - _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); - break; + if (is_2G_band) { + if (mode & WLAN_MD_11B) + _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); - case WIRELESS_11G: - case WIRELESS_11A: - case WIRELESS_11_5N: - case WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */ - case WIRELESS_11_5AC: + if (mode & ~WLAN_MD_11B) /* NOT B only */ + _rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, + WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); + } else {/* 5G and 6G */ _rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); - break; - - case WIRELESS_11BG: - case WIRELESS_11G_24N: - case WIRELESS_11_24N: - case WIRELESS_11BG_24N: - _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); - _rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); - break; - } } @@ -528,7 +561,7 @@ u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode) sint ie_len; uint network_ielen = pbss_network->IELength; - if (mode == WIRELESS_11B) { + if (mode == WLAN_MD_11B) { /*only keep CCK in support_rate IE and remove whole ext_support_rate IE*/ rtw_filter_suppport_rateie(pbss_network, CCK); p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); @@ -536,24 +569,24 @@ u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode) rtw_ies_remove_ie(ie , &network_ielen, _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, NULL, 0); pbss_network->IELength -= ie_len; } - network_type = WIRELESS_11B; + network_type = WLAN_MD_11B; } else { if (pbss_network->Configuration.DSConfig > 14) { /* Remove CCK in support_rate IE */ rtw_filter_suppport_rateie(pbss_network, OFDM); - network_type = WIRELESS_11A; + network_type = WLAN_MD_11A; } else { - if ((mode & WIRELESS_11B) == 0) { + if ((mode & WLAN_MD_11B) == 0) { /* Remove CCK in support_rate IE */ rtw_filter_suppport_rateie(pbss_network, OFDM); - network_type = WIRELESS_11G; + network_type = WLAN_MD_11G; } else { - network_type = WIRELESS_11BG; + network_type = WLAN_MD_11BG; } } } - rtw_set_supported_rate(pbss_network->SupportedRates, network_type); + rtw_set_supported_rate(pbss_network->SupportedRates, network_type, pbss_network->Configuration.DSConfig); return network_type; } @@ -608,20 +641,20 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv) ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz); /* supported rates */ - if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) { + if (pregistrypriv->wireless_mode == WLAN_MD_11ABGN) { if (pdev_network->Configuration.DSConfig > 14) - wireless_mode = WIRELESS_11A_5N; + wireless_mode = WLAN_MD_11AN; else - wireless_mode = WIRELESS_11BG_24N; - } else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */ + wireless_mode = WLAN_MD_11BGN; + } else if (pregistrypriv->wireless_mode == WLAN_MD_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */ if (pdev_network->Configuration.DSConfig > 14) - wireless_mode = WIRELESS_11_5AC; + wireless_mode = WLAN_MD_5G_MIX; else - wireless_mode = WIRELESS_11BG_24N; + wireless_mode = WLAN_MD_24G_MIX; } else wireless_mode = pregistrypriv->wireless_mode; - rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ; + rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode, pdev_network->Configuration.DSConfig) ; rateLen = rtw_get_rateset_len(pdev_network->SupportedRates); @@ -875,34 +908,43 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info) { const u8 *pos = ie; - u16 ver; u16 cnt; _rtw_memset(info, 0, sizeof(struct rsne_info)); - if (ie + ie_len < pos + 4) + /* wpa2-imp 4.2.2 F */ + if (ie + ie_len < pos + RSN_HEADER_LEN) { + RTW_INFO("%s: Invalid RSN IE length\n", __func__); goto err; + } if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2) goto err; - pos += 2; - /* Version */ - ver = RTW_GET_LE16(pos); - if(1 != ver) + /* wpa2-imp 4.2.2 A */ + if ((u16)(*(ie + 2)) != RSN_VERSION_BSD) { + RTW_INFO("%s: Invalid RSN version\n", __func__); goto err; - pos += 2; + } + pos += RSN_HEADER_LEN; - /* Group CS */ - if (ie + ie_len < pos + 4) { - if (ie + ie_len != pos) + /* ------------------- */ + /* Group CS processing */ + /* ------------------- */ + /* wpa2-imp 4.2.2 G */ + if (ie + ie_len < pos + RSN_SELECTOR_LEN) { + if (ie + ie_len != pos) { + RTW_INFO("%s: Group Cipher Suite truncated\n", __func__); goto err; + } goto exit; } info->gcs = (u8 *)pos; - pos += 4; + pos += RSN_SELECTOR_LEN; - /* Pairwise CS */ + /* ---------------------- */ + /* Pairwise CS processing */ + /* ---------------------- */ if (ie + ie_len < pos + 2) { if (ie + ie_len != pos) goto err; @@ -910,16 +952,28 @@ int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info) } cnt = RTW_GET_LE16(pos); pos += 2; - if (ie + ie_len < pos + 4 * cnt) { - if (ie + ie_len != pos) + + /* wpa-imp 4.2.2 B D */ + if (cnt == 0) { + RTW_INFO("%s: Pairwise Suite Count Invalid\n", __func__); + goto err; + } + + /* wpa2-imp 4.2.2 H L */ + if (ie + ie_len < pos + RSN_SELECTOR_LEN * cnt) { + if (ie + ie_len != pos) { + RTW_INFO("%s: Pairwise Suite truncated\n", __func__); goto err; + } goto exit; } info->pcs_cnt = cnt; info->pcs_list = (u8 *)pos; - pos += 4 * cnt; + pos += RSN_SELECTOR_LEN * cnt; - /* AKM */ + /* -------------- */ + /* AKM processing */ + /* -------------- */ if (ie + ie_len < pos + 2) { if (ie + ie_len != pos) goto err; @@ -927,40 +981,69 @@ int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info) } cnt = RTW_GET_LE16(pos); pos += 2; - if (ie + ie_len < pos + 4 * cnt) { - if (ie + ie_len != pos) + + /* wpa-imp 4.2.2 C D */ + if (cnt == 0) { + RTW_INFO("%s: AKM Count Invalid\n", __func__); + goto err; + } + + /* wpa2-imp 4.2.2 I M */ + if (ie + ie_len < pos + RSN_SELECTOR_LEN * cnt) { + if (ie + ie_len != pos) { + RTW_INFO("%s: AKM truncated\n", __func__); goto err; + } goto exit; } info->akm_cnt = cnt; info->akm_list = (u8 *)pos; - pos += 4 * cnt; + pos += RSN_SELECTOR_LEN * cnt; - /* RSN cap */ + /* ------------------------- */ + /* RSN Capability processing */ + /* ------------------------- */ + /* wpa2-imp 4.2.2 J */ if (ie + ie_len < pos + 2) { - if (ie + ie_len != pos) + if (ie + ie_len != pos) { + RTW_INFO("%s: RSN Capability truncated\n", __func__); goto err; + } goto exit; } info->cap = (u8 *)pos; pos += 2; - /* PMKID */ + /* ---------------- */ + /* PMKID processing */ + /* ---------------- */ + /* wpa2-imp 4.2.2 K */ if (ie + ie_len < pos + 2) { - if (ie + ie_len != pos) + if (ie + ie_len != pos) { + RTW_INFO("%s: PMKID count truncated\n", __func__); goto err; + } goto exit; } cnt = RTW_GET_LE16(pos); pos += 2; - if (ie + ie_len < pos + 16 * cnt) - goto err; + + /* wpa2-imp 4.2.2 N */ + if (ie + ie_len < pos + RSN_PMKID_LEN * cnt) { + if (ie + ie_len != pos || cnt) { + RTW_INFO("%s: PMKID list truncated\n", __func__); + goto err; + } + goto exit; + } info->pmkid_cnt = cnt; info->pmkid_list = (u8 *)pos; - pos += 16 * cnt; + pos += RSN_PMKID_LEN * cnt; - /* Group Mgmt CS */ - if (ie + ie_len < pos + 4) { + /* --------------------------------------- */ + /* Group Management Cipher Suit processing */ + /* --------------------------------------- */ + if (ie + ie_len < pos + RSN_SELECTOR_LEN) { if (ie + ie_len != pos) goto err; goto exit; @@ -994,10 +1077,8 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, if (pairwise_cipher) { *pairwise_cipher = 0; - if (info.pcs_list) { - for (i = 0; i < info.pcs_cnt; i++) - *pairwise_cipher |= rtw_get_rsn_cipher_suite(info.pcs_list + 4 * i); - } + for (i = 0; i < info.pcs_cnt; i++) + *pairwise_cipher |= rtw_get_rsn_cipher_suite(info.pcs_list + 4 * i); } if (gmcs) { @@ -1009,10 +1090,8 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, if (akm) { *akm = 0; - if (info.akm_list) { - for (i = 0; i < info.akm_cnt; i++) - *akm |= rtw_get_akm_suite_bitmap(info.akm_list + 4 * i); - } + for (i = 0; i < info.akm_cnt; i++) + *akm |= rtw_get_akm_suite_bitmap(info.akm_list + 4 * i); } if (mfp_opt) { @@ -1020,13 +1099,11 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, if (info.cap) *mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap); } - if (spp_opt) { *spp_opt = 0; if (info.cap) *spp_opt = GET_RSN_CAP_SPP_OPT(info.cap); - } - + } exit: return ret; } @@ -1356,6 +1433,102 @@ u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen) return (u8 *)oweie_ptr; } +/* Add extended capabilities element infomation into ext_cap_data of driver */ +void rtw_add_ext_cap_info(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 cap_info) +{ + u8 byte_offset = cap_info >> 3; + u8 bit_offset = cap_info % 8; + + ext_cap_data[byte_offset] |= BIT(bit_offset); + + /* Enlarge the length of EXT_CAP_IE */ + if (byte_offset + 1 > *ext_cap_data_len) + *ext_cap_data_len = byte_offset + 1; + + #ifdef DBG_EXT_CAP_IE + RTW_INFO("%s : cap_info = %u, byte_offset = %u, bit_offset = %u, ext_cap_data_len = %u\n", \ + __func__, cap_info, byte_offset, bit_offset, *ext_cap_data_len); + #endif +} + +/* Remvoe extended capabilities element infomation from ext_cap_data of driver */ +void rtw_remove_ext_cap_info(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 cap_info) +{ + u8 byte_offset = cap_info >> 3; + u8 bit_offset = cap_info % 8; + u8 i, max_len = 0; + + ext_cap_data[byte_offset] &= (~BIT(bit_offset)); + + /* Reduce the length of EXT_CAP_IE */ + for (i = 0; i < WLAN_EID_EXT_CAP_MAX_LEN; i++) { + if (ext_cap_data[i] != 0x0) + max_len = i + 1; + } + *ext_cap_data_len = max_len; + + #ifdef DBG_EXT_CAP_IE + RTW_INFO("%s : cap_info = %u, byte_offset = %u, bit_offset = %u, ext_cap_data_len = %u\n", \ + __func__, cap_info, byte_offset, bit_offset, *ext_cap_data_len); + #endif +} + +/** + * rtw_update_ext_cap_ie - add/update/remove the extended capabilities element of frame + * + * @ext_cap_data: from &(mlme_priv->ext_capab_ie_data) + * @ext_cap_data_len: length of ext_cap_data + * @ies: address of ies, e.g. pnetwork->IEs + * @ies_len: address of length of ies, e.g. &(pnetwork->IELength) + * @ies_offset: offset of ies, e.g. _BEACON_IE_OFFSET_ + */ +u8 rtw_update_ext_cap_ie(u8 *ext_cap_data, u8 ext_cap_data_len, u8 *ies, u32 *ies_len, u8 ies_offset) +{ + u8 *extcap_ie; + uint extcap_len_field = 0; + uint ie_len = 0; + + if (ext_cap_data_len != 0) { + extcap_ie = rtw_get_ie(ies + ies_offset, WLAN_EID_EXT_CAP, &extcap_len_field, *ies_len - ies_offset); + + if (extcap_ie == NULL) { + rtw_set_ie(ies + *ies_len, WLAN_EID_EXT_CAP, ext_cap_data_len, ext_cap_data, &ie_len); + *ies_len += ie_len; + } else { + rtw_ies_update_ie(ies, ies_len, ies_offset, WLAN_EID_EXT_CAP, ext_cap_data, ext_cap_data_len); + } + } else { + rtw_ies_remove_ie(ies, ies_len, ies_offset, WLAN_EID_EXT_CAP, NULL, 0); + } + + return _SUCCESS; +} + +void rtw_parse_ext_cap_ie(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 *ies, u32 ies_len, u8 ies_offset) +{ + u8 *extcap_ie; + uint extcap_len_field = 0; + u8 i; + + extcap_ie = rtw_get_ie(ies + ies_offset, WLAN_EID_EXT_CAP, &extcap_len_field, ies_len - ies_offset); + + if (extcap_ie != NULL) { + extcap_ie = extcap_ie + 2; /* element id and length filed */ + if (*ext_cap_data_len == 0) { + _rtw_memcpy(ext_cap_data, extcap_ie, extcap_len_field); + *ext_cap_data_len = extcap_len_field; + } else { + for (i = 0; i < extcap_len_field; i++) + ext_cap_data[i] |= extcap_ie[i]; + } + + #ifdef DBG_EXT_CAP_IE + for (i = 0; i < extcap_len_field; i++) + RTW_INFO("%s : Parse extended capabilties[%u] = 0x%x\n", __func__, i, extcap_ie[i]); + #endif + } +} + static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen, struct rtw_ieee802_11_elems *elems, int show_errors) @@ -1460,6 +1633,25 @@ static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen, } +static int rtw_ieee802_11_parse_ext_elems(u8 *start, uint elen, struct rtw_ieee802_11_elems *elems) +{ + u8 *pos = start; + u8 id = *pos; + + switch (id) { + case WLAN_EID_EXTENSION_HE_CAPABILITY: + elems->he_capabilities = pos; + elems->he_capabilities_len = elen; + return 0; + case WLAN_EID_EXTENSION_HE_OPERATION: + elems->he_operation = pos; + elems->he_operation_len = elen; + return 0; + default: + return -1; + } +} + /** * ieee802_11_parse_elems - Parse information elements in management frames * @start: Pointer to the start of IEs @@ -1608,6 +1800,9 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, elems->rann_len = elen; break; #endif + case WLAN_EID_EXTENSION: + rtw_ieee802_11_parse_ext_elems(pos, elen, elems); + break; default: unknown++; if (!show_errors) @@ -1667,34 +1862,6 @@ u8 convert_ip_addr(u8 hch, u8 mch, u8 lch) return (key_char2num(hch) * 100) + (key_char2num(mch) * 10) + key_char2num(lch); } -#ifdef CONFIG_PLATFORM_INTEL_BYT -#define MAC_ADDRESS_LEN 12 - -int rtw_get_mac_addr_intel(unsigned char *buf) -{ - int ret = 0; - int i; - struct file *fp = NULL; - mm_segment_t oldfs; - unsigned char c_mac[MAC_ADDRESS_LEN]; - char fname[] = "/config/wifi/mac.txt"; - int jj, kk; - - RTW_INFO("%s Enter\n", __FUNCTION__); - - ret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN); - if (ret < MAC_ADDRESS_LEN) - return -1; - - for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2) - buf[jj] = key_2char2num(c_mac[kk], c_mac[kk + 1]); - - RTW_INFO("%s: read from file mac address: "MAC_FMT"\n", - __FUNCTION__, MAC_ARG(buf)); - - return 0; -} -#endif /* CONFIG_PLATFORM_INTEL_BYT */ /* * Description: @@ -1769,11 +1936,6 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) goto err_chk; } - /* platform specified */ -#ifdef CONFIG_PLATFORM_INTEL_BYT - if (rtw_get_mac_addr_intel(mac) == 0) - goto err_chk; -#endif /* Use the mac address stored in the Efuse */ if (hw_mac_addr) { @@ -1804,7 +1966,6 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) RTW_INFO("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out)); } -#ifdef CONFIG_RTW_DEBUG #ifdef CONFIG_80211N_HT void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len) { @@ -1867,34 +2028,8 @@ void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len) } #endif /* CONFIG_80211N_HT */ -void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len) -{ - const u8 *pos = ie; - u16 id; - u16 len; - - const u8 *wps_ie; - uint wps_ielen; - - wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); - if (wps_ie != ie || wps_ielen == 0) - return; - - pos += 6; - while (pos - ie + 4 <= ie_len) { - id = RTW_GET_BE16(pos); - len = RTW_GET_BE16(pos + 2); - - RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len - , ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)"); - - pos += (4 + len); - } -} -#endif /* CONFIG_RTW_DEBUG */ void dump_ies(void *sel, const u8 *buf, u32 buf_len) { -#ifdef CONFIG_RTW_DEBUG const u8 *pos = buf; u8 id, len; @@ -1910,6 +2045,9 @@ void dump_ies(void *sel, const u8 *buf, u32 buf_len) #ifdef CONFIG_80211AC_VHT dump_vht_cap_ie(sel, pos, len + 2); dump_vht_op_ie(sel, pos, len + 2); +#endif +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ #endif dump_wps_ie(sel, pos, len + 2); #ifdef CONFIG_P2P @@ -1924,7 +2062,31 @@ void dump_ies(void *sel, const u8 *buf, u32 buf_len) pos += (2 + len); } -#endif /* CONFIG_RTW_DEBUG */ +} + +void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *pos = ie; + u16 id; + u16 len; + + const u8 *wps_ie; + uint wps_ielen; + + wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); + if (wps_ie != ie || wps_ielen == 0) + return; + + pos += 6; + while (pos - ie + 4 <= ie_len) { + id = RTW_GET_BE16(pos); + len = RTW_GET_BE16(pos + 2); + + RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (4 + len); + } } /** @@ -1944,7 +2106,7 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u *ch = 0; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; p = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len); if (p && ie_len > 0) @@ -1975,11 +2137,11 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u if (*bw == CHANNEL_WIDTH_40) { switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { - case SCA: - *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + case IEEE80211_SCA: + *offset = CHAN_OFFSET_UPPER; break; - case SCB: - *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + case IEEE80211_SCB: + *offset = CHAN_OFFSET_LOWER; break; } } @@ -1996,8 +2158,12 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u *bw = CHANNEL_WIDTH_80; } } -#endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ + +#endif /* CONFIG_80211AC_VHT */ } #endif /* CONFIG_80211N_HT */ } @@ -2075,7 +2241,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset else if (*g_bw == CHANNEL_WIDTH_20) rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); - if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + if (*req_offset == CHAN_OFFSET_NO_EXT) { RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__); rtw_warn_on(1); *req_bw = CHANNEL_WIDTH_20; @@ -2087,14 +2253,14 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset else if (*g_bw == CHANNEL_WIDTH_20) rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); - if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + if (*req_offset == CHAN_OFFSET_NO_EXT) { RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__); rtw_warn_on(1); *req_bw = CHANNEL_WIDTH_20; } break; case CHANNEL_WIDTH_20: - *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *req_offset = CHAN_OFFSET_NO_EXT; break; default: RTW_ERR("%s req unsupported BW:%u\n", __func__, *req_bw); @@ -2107,7 +2273,6 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset } } -#ifdef CONFIG_P2P /** * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies. * @in_ie: Pointer of the first p2p ie @@ -2517,7 +2682,56 @@ void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) break; } } -#endif /* CONFIG_P2P */ + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST +int rtw_chk_p2p_wildcard_ssid(WLAN_BSSID_EX *bss_ex) +{ + if (_rtw_memcmp(bss_ex->Ssid.Ssid, "DIRECT-", P2P_WILDCARD_SSID_LEN)) + return _SUCCESS; + else + return _FAIL; +} + +int rtw_chk_p2p_ie(WLAN_BSSID_EX *bss_ex) +{ + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex); + + u8 *ie; + uint ie_len_ori; + + ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori); + if(ie) + return _SUCCESS; + else + return _FAIL; +} +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + +void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *pos = ie; + u8 id; + u16 len; + + const u8 *wfd_ie; + uint wfd_ielen; + + wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); + if (wfd_ie != ie || wfd_ielen == 0) + return; + + pos += 6; + while (pos - ie + 3 <= ie_len) { + id = *pos; + len = RTW_GET_BE16(pos + 1); + + RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (3 + len); + } +} /** * rtw_get_wfd_ie - Search WFD IE from a series of IEs @@ -2573,84 +2787,6 @@ u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) return (u8 *)wfd_ie_ptr; } -uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg) -{ -#define DBG_DEL_WFD_IE 0 - - u8 *target_ie; - u32 target_ie_len; - uint ies_len = ies_len_ori; - int index = 0; - - while (1) { - target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len); - if (target_ie && target_ie_len) { - u8 *next_ie = target_ie + target_ie_len; - uint remain_len = ies_len - (next_ie - ies); - - if (DBG_DEL_WFD_IE && msg) { - RTW_INFO("%s %d before\n", __func__, index); - dump_ies(RTW_DBGDUMP, ies, ies_len); - - RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len); - RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len); - RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len); - } - - _rtw_memmove(target_ie, next_ie, remain_len); - _rtw_memset(target_ie + remain_len, 0, target_ie_len); - ies_len -= target_ie_len; - - if (DBG_DEL_WFD_IE && msg) { - RTW_INFO("%s %d after\n", __func__, index); - dump_ies(RTW_DBGDUMP, ies, ies_len); - } - - index++; - } else - break; - } - - return ies_len; -} - -void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex) -{ -#define DBG_BSS_EX_DEL_WFD_IE 0 - u8 *ies = BSS_EX_TLV_IES(bss_ex); - uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex); - uint ies_len; - - ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL); - bss_ex->IELength -= ies_len_ori - ies_len; -} - -#ifdef CONFIG_WFD -void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len) -{ - const u8 *pos = ie; - u8 id; - u16 len; - - const u8 *wfd_ie; - uint wfd_ielen; - - wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); - if (wfd_ie != ie || wfd_ielen == 0) - return; - - pos += 6; - while (pos - ie + 3 <= ie_len) { - id = *pos; - len = RTW_GET_BE16(pos + 1); - - RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len - , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); - - pos += (3 + len); - } -} - /** * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE * @wfd_ie: Address of WFD IE to search @@ -2741,6 +2877,47 @@ u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 * return NULL; } +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg) +{ +#define DBG_DEL_WFD_IE 0 + + u8 *target_ie; + u32 target_ie_len; + uint ies_len = ies_len_ori; + int index = 0; + + while (1) { + target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len); + if (target_ie && target_ie_len) { + u8 *next_ie = target_ie + target_ie_len; + uint remain_len = ies_len - (next_ie - ies); + + if (DBG_DEL_WFD_IE && msg) { + RTW_INFO("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + + RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len); + RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len); + RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len); + } + + _rtw_memmove(target_ie, next_ie, remain_len); + _rtw_memset(target_ie + remain_len, 0, target_ie_len); + ies_len -= target_ie_len; + + if (DBG_DEL_WFD_IE && msg) { + RTW_INFO("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + } + + index++; + } else + break; + } + + return ies_len; +} + uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id) { #define DBG_DEL_WFD_ATTR 0 @@ -2788,6 +2965,17 @@ inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ie return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen); } +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex) +{ +#define DBG_BSS_EX_DEL_WFD_IE 0 + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL); + bss_ex->IELength -= ies_len_ori - ies_len; +} + void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) { #define DBG_BSS_EX_DEL_WFD_ATTR 0 @@ -2845,7 +3033,6 @@ void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) break; } } -#endif /* CONFIG_WFD */ #ifdef CONFIG_RTW_MULTI_AP void dump_multi_ap_ie(void *sel, const u8 *ie, u32 ie_len) @@ -3073,23 +3260,6 @@ u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate) return max_rate; } -u8 rtw_ht_cap_get_rx_nss(u8 *ht_cap) -{ - u8 *ht_mcs_set = HT_CAP_ELE_SUP_MCS_SET(ht_cap); - - return rtw_ht_mcsset_to_nss(ht_mcs_set); -} - -u8 rtw_ht_cap_get_tx_nss(u8 *ht_cap) -{ - u8 *ht_mcs_set = HT_CAP_ELE_SUP_MCS_SET(ht_cap); - - if (GET_HT_CAP_ELE_TX_MCS_DEF(ht_cap) && GET_HT_CAP_ELE_TRX_MCS_NEQ(ht_cap)) - return GET_HT_CAP_ELE_TX_MAX_SS(ht_cap) + 1; - - return rtw_ht_cap_get_rx_nss(ht_cap); -} - int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action) { const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); @@ -3122,41 +3292,23 @@ int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *act } static const char *_action_public_str[] = { - [ACT_PUBLIC_BSSCOEXIST] = "ACT_PUB_BSSCOEXIST", - [ACT_PUBLIC_DSE_ENABLE] = "ACT_PUB_DSE_ENABLE", - [ACT_PUBLIC_DSE_DEENABLE] = "ACT_PUB_DSE_DEENABLE", - [ACT_PUBLIC_DSE_REG_LOCATION] = "ACT_PUB_DSE_REG_LOCATION", - [ACT_PUBLIC_EXT_CHL_SWITCH] = "ACT_PUB_EXT_CHL_SWITCH", - [ACT_PUBLIC_DSE_MSR_REQ] = "ACT_PUB_DSE_MSR_REQ", - [ACT_PUBLIC_DSE_MSR_RPRT] = "ACT_PUB_DSE_MSR_RPRT", - [ACT_PUBLIC_MP] = "ACT_PUB_MP", - [ACT_PUBLIC_DSE_PWR_CONSTRAINT] = "ACT_PUB_DSE_PWR_CONSTRAINT", - [ACT_PUBLIC_VENDOR] = "ACT_PUB_VENDOR", - [ACT_PUBLIC_GAS_INITIAL_REQ] = "ACT_PUB_GAS_INITIAL_REQ", - [ACT_PUBLIC_GAS_INITIAL_RSP] = "ACT_PUB_GAS_INITIAL_RSP", - [ACT_PUBLIC_GAS_COMEBACK_REQ] = "ACT_PUB_GAS_COMEBACK_REQ", - [ACT_PUBLIC_GAS_COMEBACK_RSP] = "ACT_PUB_GAS_COMEBACK_RSP", - [ACT_PUBLIC_TDLS_DISCOVERY_RSP] = "ACT_PUB_TDLS_DISCOVERY_RSP", - [ACT_PUBLIC_LOCATION_TRACK] = "ACT_PUB_LOCATION_TRACK", - [ACT_PUBLIC_QAB_REQ] = "ACT_PUB_QAB_REQ", - [ACT_PUBLIC_QAB_RSP] = "ACT_PUB_QAB_RSP", - [ACT_PUBLIC_QMF_POLICY] = "ACT_PUB_QMF_POLICY", - [ACT_PUBLIC_QMF_POLICY_CHANGE] = "ACT_PUB_QMF_POLICY_CHANGE", - [ACT_PUBLIC_QLOAD_REQ] = "ACT_PUB_QLOAD_REQ", - [ACT_PUBLIC_QLOAD_REPORT] = "ACT_PUB_QLOAD_REPORT", - [ACT_PUBLIC_HCCA_TXOP_ADV] = "ACT_PUB_HCCA_TXOP_ADV", - [ACT_PUBLIC_HCCA_TXOP_RSP] = "ACT_PUB_HCCA_TXOP_RSP", - [ACT_PUBLIC_PUBLIC_KEY] = "ACT_PUB_PUBLIC_KEY", - [ACT_PUBLIC_CH_AVAILABILITY_QUERY] = "ACT_PUB_CH_AVAILABILITY_QUERY", - [ACT_PUBLIC_CH_SCHEDULE_MGMT] = "ACT_PUB_CH_SCHEDULE_MGMT", - [ACT_PUBLIC_CONTACT_VERI_SIGNAL] = "ACT_PUB_CONTACT_VERI_SIGNAL", - [ACT_PUBLIC_GDD_ENABLE_REQ] = "ACT_PUB_GDD_ENABLE_REQ", - [ACT_PUBLIC_GDD_ENABLE_RSP] = "ACT_PUB_GDD_ENABLE_RSP", - [ACT_PUBLIC_NETWORK_CH_CONTROL] = "ACT_PUB_NETWORK_CH_CONTROL", - [ACT_PUBLIC_WHITE_SPACE_MAP_ANN] = "ACT_PUB_WHITE_SPACE_MAP_ANN", - [ACT_PUBLIC_FTM_REQ] = "ACT_PUB_FTM_REQ", - [ACT_PUBLIC_FTM] = "ACT_PUB_FTM", - [ACT_PUBLIC_MAX] = "ACT_PUB_RSVD", + "ACT_PUB_BSSCOEXIST", + "ACT_PUB_DSE_ENABLE", + "ACT_PUB_DSE_DEENABLE", + "ACT_PUB_DSE_REG_LOCATION", + "ACT_PUB_EXT_CHL_SWITCH", + "ACT_PUB_DSE_MSR_REQ", + "ACT_PUB_DSE_MSR_RPRT", + "ACT_PUB_MP", + "ACT_PUB_DSE_PWR_CONSTRAINT", + "ACT_PUB_VENDOR", + "ACT_PUB_GAS_INITIAL_REQ", + "ACT_PUB_GAS_INITIAL_RSP", + "ACT_PUB_GAS_COMEBACK_REQ", + "ACT_PUB_GAS_COMEBACK_RSP", + "ACT_PUB_TDLS_DISCOVERY_RSP", + "ACT_PUB_LOCATION_TRACK", + "ACT_PUB_RSVD", }; const char *action_public_str(u8 action) @@ -3178,11 +3330,11 @@ void rtw_set_spp_amsdu_mode(u8 mode, u8 *rsn_ie, int rsn_ie_len) return; if (mode == RTW_AMSDU_MODE_NON_SPP ) { - spp_req_cap = 0; /* SPP_CAP=0, SPP_REQ=0 */ + spp_req_cap = 0; } else if (mode == RTW_AMSDU_MODE_SPP) { - spp_req_cap = SPP_CAP | SPP_REQ; + spp_req_cap = SPP_CAP|SPP_REQ; } else if (mode == RTW_AMSDU_MODE_ALL_DROP) { - spp_req_cap = SPP_REQ; /* SPP_CAP=0, SPP_REQ=1 */ + spp_req_cap = SPP_REQ; } else { RTW_INFO("%s unexpected mode = %d, please check the config\n", __func__, mode); return; diff --git a/core/rtw_io.c b/core/rtw_io.c index 734d3e5..ce0c703 100644 --- a/core/rtw_io.c +++ b/core/rtw_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -45,415 +45,6 @@ jackson@realtek.com.tw #define _RTW_IO_C_ #include -#include - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D) - #define rtw_le16_to_cpu(val) val - #define rtw_le32_to_cpu(val) val - #define rtw_cpu_to_le16(val) val - #define rtw_cpu_to_le32(val) val -#else - #define rtw_le16_to_cpu(val) le16_to_cpu(val) - #define rtw_le32_to_cpu(val) le32_to_cpu(val) - #define rtw_cpu_to_le16(val) cpu_to_le16(val) - #define rtw_cpu_to_le32(val) cpu_to_le32(val) -#endif - - -u8 _rtw_read8(_adapter *adapter, u32 addr) -{ - u8 r_val; - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr); - _read8 = pintfhdl->io_ops._read8; - - r_val = _read8(pintfhdl, addr); - return r_val; -} - -u16 _rtw_read16(_adapter *adapter, u32 addr) -{ - u16 r_val; - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr); - _read16 = pintfhdl->io_ops._read16; - - r_val = _read16(pintfhdl, addr); - return rtw_le16_to_cpu(r_val); -} - -u32 _rtw_read32(_adapter *adapter, u32 addr) -{ - u32 r_val; - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr); - _read32 = pintfhdl->io_ops._read32; - - r_val = _read32(pintfhdl, addr); - return rtw_le32_to_cpu(r_val); - -} - -int _rtw_write8(_adapter *adapter, u32 addr, u8 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int ret; - _write8 = pintfhdl->io_ops._write8; - - ret = _write8(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} -int _rtw_write16(_adapter *adapter, u32 addr, u16 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int ret; - _write16 = pintfhdl->io_ops._write16; - - val = rtw_cpu_to_le16(val); - ret = _write16(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} -int _rtw_write32(_adapter *adapter, u32 addr, u32 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); - int ret; - _write32 = pintfhdl->io_ops._write32; - - val = rtw_cpu_to_le32(val); - ret = _write32(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} - -int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = (struct intf_hdl *)(&(pio_priv->intf)); - int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); - int ret; - _writeN = pintfhdl->io_ops._writeN; - - ret = _writeN(pintfhdl, addr, length, pdata); - - return RTW_STATUS_CODE(ret); -} - -#ifdef CONFIG_SDIO_HCI -u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr) -{ - u8 r_val = 0x00; - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr); - - _sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8; - - if (_sd_f0_read8) - r_val = _sd_f0_read8(pintfhdl, addr); - else - RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return r_val; -} - -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -u8 _rtw_sd_iread8(_adapter *adapter, u32 addr) -{ - u8 r_val = 0x00; - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr); - - _sd_iread8 = pintfhdl->io_ops._sd_iread8; - - if (_sd_iread8) - r_val = _sd_iread8(pintfhdl, addr); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return r_val; -} - -u16 _rtw_sd_iread16(_adapter *adapter, u32 addr) -{ - u16 r_val = 0x00; - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr); - - _sd_iread16 = pintfhdl->io_ops._sd_iread16; - - if (_sd_iread16) - r_val = _sd_iread16(pintfhdl, addr); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return r_val; -} - -u32 _rtw_sd_iread32(_adapter *adapter, u32 addr) -{ - u32 r_val = 0x00; - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr); - - _sd_iread32 = pintfhdl->io_ops._sd_iread32; - - if (_sd_iread32) - r_val = _sd_iread32(pintfhdl, addr); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return r_val; -} - -int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val) -{ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int ret = -1; - - _sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8; - - if (_sd_iwrite8) - ret = _sd_iwrite8(pintfhdl, addr, val); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return RTW_STATUS_CODE(ret); -} - -int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val) -{ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int ret = -1; - - _sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16; - - if (_sd_iwrite16) - ret = _sd_iwrite16(pintfhdl, addr, val); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return RTW_STATUS_CODE(ret); -} -int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val) -{ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); - int ret = -1; - - _sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32; - - if (_sd_iwrite32) - ret = _sd_iwrite32(pintfhdl, addr, val); - else - RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - - return RTW_STATUS_CODE(ret); -} - -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ - -#endif /* CONFIG_SDIO_HCI */ - -int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int ret; - _write8_async = pintfhdl->io_ops._write8_async; - - ret = _write8_async(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} -int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int ret; - _write16_async = pintfhdl->io_ops._write16_async; - val = rtw_cpu_to_le16(val); - ret = _write16_async(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} -int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val) -{ - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); - int ret; - _write32_async = pintfhdl->io_ops._write32_async; - val = rtw_cpu_to_le32(val); - ret = _write32_async(pintfhdl, addr, val); - - return RTW_STATUS_CODE(ret); -} - -void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) -{ - void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - - - if (RTW_CANNOT_RUN(adapter)) { - return; - } - - _read_mem = pintfhdl->io_ops._read_mem; - - _read_mem(pintfhdl, addr, cnt, pmem); - - -} - -void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) -{ - void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - - - _write_mem = pintfhdl->io_ops._write_mem; - - _write_mem(pintfhdl, addr, cnt, pmem); - - -} - -void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) -{ - u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - - - if (RTW_CANNOT_RUN(adapter)) { - return; - } - - _read_port = pintfhdl->io_ops._read_port; - - _read_port(pintfhdl, addr, cnt, pmem); - - -} - -void _rtw_read_port_cancel(_adapter *adapter) -{ - void (*_read_port_cancel)(struct intf_hdl *pintfhdl); - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - - _read_port_cancel = pintfhdl->io_ops._read_port_cancel; - - RTW_DISABLE_FUNC(adapter, DF_RX_BIT); - - if (_read_port_cancel) - _read_port_cancel(pintfhdl); -} - -u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) -{ - u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - u32 ret = _SUCCESS; - - - _write_port = pintfhdl->io_ops._write_port; - - ret = _write_port(pintfhdl, addr, cnt, pmem); - - - return ret; -} - -u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms) -{ - int ret = _SUCCESS; - struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem; - struct submit_ctx sctx; - - rtw_sctx_init(&sctx, timeout_ms); - pxmitbuf->sctx = &sctx; - - ret = _rtw_write_port(adapter, addr, cnt, pmem); - - if (ret == _SUCCESS) { - ret = rtw_sctx_wait(&sctx, __func__); - - if (ret != _SUCCESS) - pxmitbuf->sctx = NULL; - } - - return ret; -} - -void _rtw_write_port_cancel(_adapter *adapter) -{ - void (*_write_port_cancel)(struct intf_hdl *pintfhdl); - struct io_priv *pio_priv = &adapter->iopriv; - struct intf_hdl *pintfhdl = &(pio_priv->intf); - - _write_port_cancel = pintfhdl->io_ops._write_port_cancel; - - RTW_DISABLE_FUNC(adapter, DF_TX_BIT); - - if (_write_port_cancel) - _write_port_cancel(pintfhdl); -} -int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops)) -{ - struct io_priv *piopriv = &padapter->iopriv; - struct intf_hdl *pintf = &piopriv->intf; - - if (set_intf_ops == NULL) - return _FAIL; - - piopriv->padapter = padapter; - pintf->padapter = padapter; - pintf->pintf_dev = adapter_to_dvobj(padapter); - - set_intf_ops(padapter, &pintf->io_ops); - - return _SUCCESS; -} /* * Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR @@ -482,471 +73,3 @@ void rtw_reset_continual_io_error(struct dvobj_priv *dvobj) { ATOMIC_SET(&dvobj->continual_io_error, 0); } - -#ifdef DBG_IO -#define RTW_IO_SNIFF_TYPE_RANGE 0 /* specific address range is accessed */ -#define RTW_IO_SNIFF_TYPE_VALUE 1 /* value match for sniffed range */ - -struct rtw_io_sniff_ent { - u8 chip; - u8 hci; - u32 addr; - u8 type; - union { - u32 end_addr; - struct { - u32 mask; - u32 val; - bool equal; - } vm; /* value match */ - } u; - bool trace; - char *tag; - bool (*assert_protsel)(_adapter *adapter, u32 addr, u8 len); -}; - -#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \ - {.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,} - -#define RTW_IO_SNIFF_RANGE_PROT_ENT(_chip, _hci, _addr, _end_addr, _assert_protsel, _tag) \ - {.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = 1, .assert_protsel = _assert_protsel, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,} - -#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \ - {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} - -/* part or all sniffed range is enabled (not all 0) */ -#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \ - {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} - -/* part or all sniffed range is disabled (not all 1) */ -#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \ - {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} - -const struct rtw_io_sniff_ent read_sniff[] = { -#ifdef DBG_IO_HCI_EN_CHK - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"), - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"), - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"), -#endif -#ifdef DBG_IO_SNIFF_EXAMPLE - RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "read TXPAUSE"), - RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"), -#endif -#ifdef DBG_IO_PROT_SEL - RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x1501, 0x1513, rtw_assert_protsel_port, "protsel port"), - RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x153a, 0x153b, rtw_assert_protsel_atimdtim, "protsel atimdtim"), -#endif -}; - -const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent); - -const struct rtw_io_sniff_ent write_sniff[] = { -#ifdef DBG_IO_HCI_EN_CHK - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"), - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"), - RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"), -#endif -#ifdef DBG_IO_8822C_1TX_PATH_EN - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x02, 1, 0, "write tx_path_en_cck A enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x01, 1, 0, "write tx_path_en_cck B enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x03, 1, 1, "write tx_path_en_cck AB enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x01, 1, 0, "write tx_path_en_ofdm_1sts A enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x02, 1, 0, "write tx_path_en_ofdm_1sts B enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x03, 1, 1, "write tx_path_en_ofdm_1sts AB enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x01, 1, 0, "write tx_path_en_ofdm_2sts A enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x02, 1, 0, "write tx_path_en_ofdm_2sts B enabled"), - RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x03, 1, 1, "write tx_path_en_ofdm_2sts AB enabled"), -#endif -#ifdef DBG_IO_SNIFF_EXAMPLE - RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "write TXPAUSE"), - RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"), -#endif -}; - -const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent); - -static bool match_io_sniff_ranges(_adapter *adapter - , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len) -{ - - /* check if IO range after sniff end address */ - if (addr > sniff->u.end_addr) - return 0; - - if (sniff->assert_protsel && - sniff->assert_protsel(adapter, addr, len)) - return 0; - - return 1; -} - -static bool match_io_sniff_value(_adapter *adapter - , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) -{ - u8 sniff_len; - s8 mask_shift; - u32 mask; - s8 value_shift; - u32 value; - bool ret = 0; - - /* check if IO range after sniff end address */ - sniff_len = 4; - while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) { - sniff_len--; - if (sniff_len == 0) - goto exit; - } - if (sniff->addr + sniff_len <= addr) - goto exit; - - /* align to IO addr */ - mask_shift = (sniff->addr - addr) * 8; - value_shift = mask_shift + bitshift(sniff->u.vm.mask); - if (mask_shift > 0) - mask = sniff->u.vm.mask << mask_shift; - else if (mask_shift < 0) - mask = sniff->u.vm.mask >> -mask_shift; - else - mask = sniff->u.vm.mask; - - if (value_shift > 0) - value = sniff->u.vm.val << value_shift; - else if (mask_shift < 0) - value = sniff->u.vm.val >> -value_shift; - else - value = sniff->u.vm.val; - - if ((sniff->u.vm.equal && (mask & val) == (mask & value)) - || (!sniff->u.vm.equal && (mask & val) != (mask & value)) - ) { - ret = 1; - if (0) - RTW_INFO(FUNC_ADPT_FMT" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n" - , FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal); - } - -exit: - return ret; -} - -static bool match_io_sniff(_adapter *adapter - , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) -{ - bool ret = 0; - - if (sniff->chip != MAX_CHIP_TYPE - && sniff->chip != rtw_get_chip_type(adapter)) - goto exit; - if (sniff->hci - && !(sniff->hci & rtw_get_intf_type(adapter))) - goto exit; - if (sniff->addr >= addr + len) /* IO range below sniff start address */ - goto exit; - - switch (sniff->type) { - case RTW_IO_SNIFF_TYPE_RANGE: - ret = match_io_sniff_ranges(adapter, sniff, i, addr, len); - break; - case RTW_IO_SNIFF_TYPE_VALUE: - if (len == 1 || len == 2 || len == 4) - ret = match_io_sniff_value(adapter, sniff, i, addr, len, val); - break; - default: - rtw_warn_on(1); - break; - } - -exit: - return ret; -} - -u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val) -{ - int i; - bool trace = 0; - u32 match = 0; - - for (i = 0; i < read_sniff_num; i++) { - if (match_io_sniff(adapter, &read_sniff[i], i, addr, len, val)) { - match++; - trace |= read_sniff[i].trace; - if (read_sniff[i].tag) - RTW_INFO("DBG_IO TAG %s\n", read_sniff[i].tag); - } - } - - rtw_warn_on(trace); - - return match; -} - -u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val) -{ - int i; - bool trace = 0; - u32 match = 0; - - for (i = 0; i < write_sniff_num; i++) { - if (match_io_sniff(adapter, &write_sniff[i], i, addr, len, val)) { - match++; - trace |= write_sniff[i].trace; - if (write_sniff[i].tag) - RTW_INFO("DBG_IO TAG %s\n", write_sniff[i].tag); - } - } - - rtw_warn_on(trace); - - return match; -} - -struct rf_sniff_ent { - u8 path; - u16 reg; - u32 mask; -}; - -struct rf_sniff_ent rf_read_sniff_ranges[] = { - /* example for all path addr 0x55 with all RF Reg mask */ - /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ -}; - -struct rf_sniff_ent rf_write_sniff_ranges[] = { - /* example for all path addr 0x55 with all RF Reg mask */ - /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ -}; - -int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent); -int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent); - -bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask) -{ - int i; - - for (i = 0; i < rf_read_sniff_num; i++) { - if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path) - if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask)) - return _TRUE; - } - - return _FALSE; -} - -bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask) -{ - int i; - - for (i = 0; i < rf_write_sniff_num; i++) { - if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path) - if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask)) - return _TRUE; - } - - return _FALSE; -} - -void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line) -{ - if (match_read_sniff(adapter, addr, len, val)) { - switch (len) { - case 1: - RTW_INFO("DBG_IO %s:%d read8(0x%04x) return 0x%02x\n" - , caller, line, addr, val); - break; - case 2: - RTW_INFO("DBG_IO %s:%d read16(0x%04x) return 0x%04x\n" - , caller, line, addr, val); - break; - case 4: - RTW_INFO("DBG_IO %s:%d read32(0x%04x) return 0x%08x\n" - , caller, line, addr, val); - break; - default: - RTW_INFO("DBG_IO %s:%d readN(0x%04x, %u)\n" - , caller, line, addr, len); - } - } -} - -void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, len, val)) { - switch (len) { - case 1: - RTW_INFO("DBG_IO %s:%d write8(0x%04x, 0x%02x)\n" - , caller, line, addr, val); - break; - case 2: - RTW_INFO("DBG_IO %s:%d write16(0x%04x, 0x%04x)\n" - , caller, line, addr, val); - break; - case 4: - RTW_INFO("DBG_IO %s:%d write32(0x%04x, 0x%08x)\n" - , caller, line, addr, val); - break; - default: - RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n" - , caller, line, addr, len); - } - } -} - -u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u8 val = _rtw_read8(adapter, addr); - - if (match_read_sniff(adapter, addr, 1, val)) { - RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n" - , caller, line, addr, val); - } - - return val; -} - -u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u16 val = _rtw_read16(adapter, addr); - - if (match_read_sniff(adapter, addr, 2, val)) { - RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n" - , caller, line, addr, val); - } - - return val; -} - -u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u32 val = _rtw_read32(adapter, addr); - - if (match_read_sniff(adapter, addr, 4, val)) { - RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n" - , caller, line, addr, val); - } - - return val; -} - -int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 1, val)) { - RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n" - , caller, line, addr, val); - } - - return _rtw_write8(adapter, addr, val); -} -int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 2, val)) { - RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n" - , caller, line, addr, val); - } - - return _rtw_write16(adapter, addr, val); -} -int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 4, val)) { - RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n" - , caller, line, addr, val); - } - - return _rtw_write32(adapter, addr, val); -} -int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, length, 0)) { - RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n" - , caller, line, addr, length); - } - - return _rtw_writeN(adapter, addr, length, data); -} - -#ifdef CONFIG_SDIO_HCI -u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u8 val = _rtw_sd_f0_read8(adapter, addr); - -#if 0 - if (match_read_sniff(adapter, addr, 1, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n" - , caller, line, addr, val); - } -#endif - - return val; -} - -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u8 val = rtw_sd_iread8(adapter, addr); - - if (match_read_sniff(adapter, addr, 1, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n" - , caller, line, addr, val); - } - - return val; -} - -u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u16 val = _rtw_sd_iread16(adapter, addr); - - if (match_read_sniff(adapter, addr, 2, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n" - , caller, line, addr, val); - } - - return val; -} - -u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line) -{ - u32 val = _rtw_sd_iread32(adapter, addr); - - if (match_read_sniff(adapter, addr, 4, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n" - , caller, line, addr, val); - } - - return val; -} - -int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 1, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n" - , caller, line, addr, val); - } - - return _rtw_sd_iwrite8(adapter, addr, val); -} -int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 2, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n" - , caller, line, addr, val); - } - - return _rtw_sd_iwrite16(adapter, addr, val); -} -int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) -{ - if (match_write_sniff(adapter, addr, 4, val)) { - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n" - , caller, line, addr, val); - } - - return _rtw_sd_iwrite32(adapter, addr, val); -} - -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ - -#endif /* CONFIG_SDIO_HCI */ - -#endif diff --git a/core/rtw_ioctl_query.c b/core/rtw_ioctl_query.c index 9392138..7647e80 100644 --- a/core/rtw_ioctl_query.c +++ b/core/rtw_ioctl_query.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/core/rtw_ioctl_set.c b/core/rtw_ioctl_set.c index 060546c..3b02394 100644 --- a/core/rtw_ioctl_set.c +++ b/core/rtw_ioctl_set.c @@ -15,7 +15,6 @@ #define _RTW_IOCTL_SET_C_ #include -#include extern void indicate_wx_scan_complete_event(_adapter *padapter); @@ -69,10 +68,8 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) return ret; } -u8 rtw_do_join(_adapter *padapter); u8 rtw_do_join(_adapter *padapter) { - _irqL irqL; _list *plist, *phead; u8 *pibss = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -81,7 +78,7 @@ u8 rtw_do_join(_adapter *padapter) u8 ret = _SUCCESS; - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); @@ -105,7 +102,7 @@ u8 rtw_do_join(_adapter *padapter) } if (_rtw_queue_empty(queue) == _TRUE) { - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); /* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */ @@ -134,14 +131,13 @@ u8 rtw_do_join(_adapter *padapter) goto exit; } else { int select_ret; - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); if (select_ret == _SUCCESS) { pmlmepriv->to_join = _FALSE; - _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + set_assoc_timer(pmlmepriv, MAX_JOIN_TIMEOUT); /*_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);*/ } else { if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { - #ifdef CONFIG_AP_MODE /* submit createbss_cmd to change to a ADHOC_MASTER */ /* pmlmepriv->lock has been acquired by caller... */ @@ -165,7 +161,8 @@ u8 rtw_do_join(_adapter *padapter) } pmlmepriv->to_join = _FALSE; - #endif /* CONFIG_AP_MODE */ + + } else { /* can't associate ; reset under-linking */ _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); @@ -205,7 +202,6 @@ u8 rtw_do_join(_adapter *padapter) u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) { - _irqL irqL; u8 status = _SUCCESS; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -219,7 +215,7 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) goto exit; } - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); RTW_INFO("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); @@ -231,16 +227,19 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) { if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) + if (!MLME_IS_STA(padapter)) goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */ } else { rtw_disassoc_cmd(padapter, 0, 0); - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { + #ifdef CONFIG_STA_CMD_DISPR + if (MLME_IS_STA(padapter) == _FALSE) + #endif /* CONFIG_STA_CMD_DISPR */ + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); - - rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); + } if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); @@ -266,7 +265,7 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) status = rtw_do_join(padapter); release_mlme_lock: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); exit: @@ -276,7 +275,6 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) { - _irqL irqL; u8 status = _SUCCESS; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -286,12 +284,12 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) RTW_PRINT("set ssid [%s] fw_state=0x%08x\n", ssid->Ssid, get_fwstate(pmlmepriv)); - if (!rtw_is_hw_init_completed(padapter)) { + if (!rtw_hw_is_init_completed(adapter_to_dvobj(padapter))) { status = _FAIL; goto exit; } - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); RTW_INFO("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) @@ -303,17 +301,16 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) { - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) { + if (!MLME_IS_STA(padapter)) { if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) { /* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */ rtw_disassoc_cmd(padapter, 0, 0); - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); - - rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); - + } if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); @@ -330,11 +327,13 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) rtw_disassoc_cmd(padapter, 0, 0); - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE){ + #ifdef CONFIG_STA_CMD_DISPR + if (MLME_IS_STA(padapter) == _FALSE) + #endif /* CONFIG_STA_CMD_DISPR */ + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); - - rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); - + } if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); @@ -363,7 +362,7 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) status = rtw_do_join(padapter); release_mlme_lock: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); exit: @@ -375,7 +374,6 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch) { - _irqL irqL; u8 status = _SUCCESS; bool bssid_valid = _TRUE; bool ssid_valid = _TRUE; @@ -395,12 +393,7 @@ u8 rtw_set_802_11_connect(_adapter *padapter, goto exit; } - if (!rtw_is_hw_init_completed(padapter)) { - status = _FAIL; - goto exit; - } - - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); RTW_PRINT(FUNC_ADPT_FMT" fw_state=0x%08x\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); @@ -435,16 +428,15 @@ u8 rtw_set_802_11_connect(_adapter *padapter, status = rtw_do_join(padapter); release_mlme_lock: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); exit: return status; } u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, - NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags) + NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags) { - _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &pmlmepriv->cur_network; NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode); @@ -466,19 +458,24 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, #endif } - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); is_linked = check_fwstate(pmlmepriv, WIFI_ASOC_STATE); is_adhoc_master = check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); /* flags = 0, means enqueue cmd and no wait */ if (flags != 0) - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); if ((is_linked == _TRUE) || (*pold_state == Ndis802_11IBSS)) rtw_disassoc_cmd(padapter, 0, flags); - if ((is_linked == _TRUE) || - (is_adhoc_master == _TRUE)) + if ((is_adhoc_master == _TRUE) + || ((is_linked == _TRUE) +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + ) rtw_free_assoc_resources_cmd(padapter, _TRUE, flags); if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) { @@ -489,7 +486,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, /* flags = 0, means enqueue cmd and no wait */ if (flags != 0) - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); *pold_state = networktype; @@ -502,9 +499,6 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, case Ndis802_11Infrastructure: set_fwstate(pmlmepriv, WIFI_STATION_STATE); - - if (ap2sta_mode) - rtw_init_bcmc_stainfo(padapter); break; case Ndis802_11APMode: @@ -539,159 +533,39 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, /* SecClearAllKeys(adapter); */ - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } - return ret; } u8 rtw_set_802_11_disassociate(_adapter *padapter) { - _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { - rtw_disassoc_cmd(padapter, 0, 0); - rtw_indicate_disconnect(padapter, 0, _FALSE); /* modify for CONFIG_IEEE80211W, none 11w can use it */ - rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); + if (1 +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); + rtw_indicate_disconnect(padapter, 0, _FALSE); if (_FAIL == rtw_pwr_wakeup(padapter)) RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__); } - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); return _TRUE; } -#if 1 -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) -{ - _irqL irqL; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - u8 res = _TRUE; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - res = rtw_sitesurvey_cmd(padapter, pparm); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - - return res; -} - -#else -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) -{ - _irqL irqL; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - u8 res = _TRUE; - - - - if (padapter == NULL) { - res = _FALSE; - goto exit; - } - if (!rtw_is_hw_init_completed(padapter)) { - res = _FALSE; - goto exit; - } - - if ((check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) || - (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) { - /* Scan or linking is in progress, do nothing. */ - res = _TRUE; - - - } else { - if (rtw_is_scan_deny(padapter)) { - RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter)); - indicate_wx_scan_complete_event(padapter); - return _SUCCESS; - } - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - - res = rtw_sitesurvey_cmd(padapter, pparm); - - _exit_critical_bh(&pmlmepriv->lock, &irqL); - } -exit: - - - return res; -} -#endif - -#ifdef CONFIG_RTW_ACS -u8 rtw_set_acs_sitesurvey(_adapter *adapter) -{ - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct sitesurvey_parm parm; - u8 uch; - u8 ch_num = 0; - int i; - BAND_TYPE band; - u8 (*center_chs_num)(u8) = NULL; - u8 (*center_chs)(u8, u8) = NULL; - u8 ret = _FAIL; - - if (!rtw_mi_get_ch_setting_union(adapter, &uch, NULL, NULL)) - goto exit; - - _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm)); - parm.scan_mode = SCAN_PASSIVE; - parm.bw = CHANNEL_WIDTH_20; - parm.acs = 1; - - for (band = BAND_ON_2_4G; band < BAND_MAX; band++) { - if (band == BAND_ON_2_4G) { - center_chs_num = center_chs_2g_num; - center_chs = center_chs_2g; - } else - #ifdef CONFIG_IEEE80211_BAND_5GHZ - if (band == BAND_ON_5G) { - center_chs_num = center_chs_5g_num; - center_chs = center_chs_5g; - } else - #endif - { - center_chs_num = NULL; - center_chs = NULL; - } - - if (!center_chs_num || !center_chs) - continue; - - if (rfctl->ch_sel_within_same_band) { - if (rtw_is_2g_ch(uch) && band != BAND_ON_2_4G) - continue; - #ifdef CONFIG_IEEE80211_BAND_5GHZ - if (rtw_is_5g_ch(uch) && band != BAND_ON_5G) - continue; - #endif - } - - ch_num = center_chs_num(CHANNEL_WIDTH_20); - for (i = 0; i < ch_num && parm.ch_num < RTW_CHANNEL_SCAN_AMOUNT; i++) { - parm.ch[parm.ch_num].hw_value = center_chs(CHANNEL_WIDTH_20, i); - parm.ch[parm.ch_num].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; - parm.ch_num++; - } - } - - ret = rtw_set_802_11_bssid_list_scan(adapter, &parm); - -exit: - return ret; -} -#endif /* CONFIG_RTW_ACS */ - u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode) { struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -808,21 +682,28 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta)); #ifdef CONFIG_80211N_HT - if (is_supported_ht(psta->wireless_mode)) { - max_rate = rtw_ht_mcs_rate((psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 + if (is_supported_ht(psta->phl_sta->wmode)) { + max_rate = rtw_ht_mcs_rate((psta->phl_sta->chandef.bw == CHANNEL_WIDTH_40) ? 1 : 0 , short_GI , psta->htpriv.ht_cap.supp_mcs_set ); } #ifdef CONFIG_80211AC_VHT - else if (is_supported_vht(psta->wireless_mode)) - max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; + else if (is_supported_vht(psta->phl_sta->wmode)) + max_rate = ((rtw_vht_mcs_to_data_rate(psta->phl_sta->chandef.bw, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; +#ifdef CONFIG_80211AX_HE + else if (is_supported_he(psta->phl_sta->wmode)) + max_rate = + ((rtw_he_mcs_to_data_rate(psta->phl_sta->chandef.bw, + psta->phl_sta->asoc_cap.ltf_gi, + pmlmepriv->hepriv.he_highest_rate) + 1) >> 1) * 10; +#endif /* CONFIG_80211AX_HE */ #endif /* CONFIG_80211AC_VHT */ else #endif /* CONFIG_80211N_HT */ { /*station mode show :station && ap support rate; softap :show ap support rate*/ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + if (MLME_IS_STA(adapter)) get_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/ @@ -831,7 +712,7 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) /*RTW_INFO("%s rate=%02X \n", __func__, rate);*/ /*check STA support rate or not */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(adapter)) { for (j = 0; j < sta_bssrate_len; j++) { /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ if ((rate | IEEE80211_BASIC_RATE_MASK) @@ -863,9 +744,10 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) * * Return _SUCCESS or _FAIL */ -int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) +int rtw_set_scan_mode(_adapter *adapter, enum rtw_phl_scan_type scan_mode) { - if (scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE) + if (scan_mode != RTW_PHL_SCAN_ACTIVE && + scan_mode != RTW_PHL_SCAN_PASSIVE) return _FAIL; adapter->mlmepriv.scan_mode = scan_mode; @@ -880,12 +762,12 @@ int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) * * Return _SUCCESS or _FAIL */ -int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan, u8 chplan_6g, enum rtw_regd_inr inr) { struct registry_priv *regsty = adapter_to_regsty(adapter); if (!REGSTY_REGD_SRC_FROM_OS(regsty)) - return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1); + return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, chplan_6g, inr); RTW_WARN("%s(): not applied\n", __func__); return _SUCCESS; } @@ -897,13 +779,13 @@ int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) * * Return _SUCCESS or _FAIL */ -int rtw_set_country(_adapter *adapter, const char *country_code) +int rtw_set_country(_adapter *adapter, const char *country_code, enum rtw_regd_inr inr) { #ifdef CONFIG_RTW_IOCTL_SET_COUNTRY struct registry_priv *regsty = adapter_to_regsty(adapter); if (!REGSTY_REGD_SRC_FROM_OS(regsty)) - return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1); + return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, inr); #endif RTW_WARN("%s(): not applied\n", __func__); return _SUCCESS; diff --git a/core/rtw_mbo.c b/core/rtw_mbo.c index 44f93ad..02de6c0 100644 --- a/core/rtw_mbo.c +++ b/core/rtw_mbo.c @@ -12,9 +12,9 @@ * more details. * *****************************************************************************/ +#define _RTW_MBO_C #include -#include #ifdef CONFIG_RTW_MBO @@ -25,7 +25,7 @@ #define RTW_MBO_INFO(fmt, arg...) \ RTW_INFO(fmt, arg) #define RTW_MBO_DUMP(str, data, len) \ - RTW_INFO_DUMP(str, data, len) + RTW_INFO_DUMP(str, data, len) #else #define RTW_MBO_INFO(fmt, arg...) do {} while (0) #define RTW_MBO_DUMP(str, data, len) do {} while (0) @@ -42,15 +42,18 @@ module_param(rtw_mbo_cell_data_conn, int, 0644); static u8 wfa_mbo_oui[] = {0x50, 0x6F, 0x9A, 0x16}; -#define rtw_mbo_get_oui(p) ((u8 *)(p) + 2) +#define rtw_mbo_get_oui(p) ((u8 *)(p) + 2) -#define rtw_mbo_get_attr_id(p) ((u8 *)(p)) +#define rtw_mbo_get_attr_id(p) ((u8 *)(p)) -#define rtw_mbo_get_disallow_res(p) ((u8 *)(p) + 3) +#define rtw_mbo_get_disallow_res(p) ((u8 *)(p) + 3) #define rtw_mbo_set_1byte_ie(p, v, l) \ rtw_set_fixed_ie((p), 1, (v), (l)) +#define rtw_mbo_set_2byte_ie(p, v, l) \ + rtw_set_fixed_ie((p), 2, (v), (l)) + #define rtw_mbo_set_4byte_ie(p, v, l) \ rtw_set_fixed_ie((p), 4, (v), (l)) @@ -68,60 +71,194 @@ static u8 wfa_mbo_oui[] = {0x50, 0x6F, 0x9A, 0x16}; _offset++; \ } \ } while(0) - + + +void rtw_mbo_ie_init(_adapter *padapter, struct mbo_priv *mbopriv) +{ + if(!mbopriv) + return; + mbopriv->assoc_disallow = 0; + mbopriv->cellular_aware = 0; + mbopriv->ch_list_num = 0; + mbopriv->mbo_oce_element_len = 6; + mbopriv->mbo_oce_element[0] = 0xdd; + mbopriv->mbo_oce_element[1] = mbopriv->mbo_oce_element_len; + mbopriv->mbo_oce_element[2] = 0x50; + mbopriv->mbo_oce_element[3] = 0x6f; + mbopriv->mbo_oce_element[4] = 0x9a; + mbopriv->mbo_oce_element[5] = 0x16; +} + +void rtw_mbo_fill_non_prefer_channel_list(_adapter *padapter, struct mbo_priv *mbopriv, + const u8 *pbuf, u8 len) +{ + u8 op_class = 0; + u8 preference = 0; + int i; + + /* invalid length */ + if(len != 0 && len < 3) + return; + + /* reset non-prefer channel list */ + mbopriv->ch_list_num = 0; + op_class = *pbuf; + preference = *(pbuf + len - 2); + + if (len == 3 && mbopriv->ch_list_num < MBO_CH_LIST_MAX_NUM) { + mbopriv->ch_list[mbopriv->ch_list_num].op_class = op_class; + mbopriv->ch_list[mbopriv->ch_list_num].preference = preference; + mbopriv->ch_list[mbopriv->ch_list_num].channel = 0; + mbopriv->ch_list_num += 1; + RTW_INFO("[%s:%d]channel = %d, preference = %d\n", __func__, __LINE__, 0, preference); + } else { + for (i = 0; i < len - 3; i++) { + if(mbopriv->ch_list_num >= MBO_CH_LIST_MAX_NUM) + break; + mbopriv->ch_list[mbopriv->ch_list_num].op_class = op_class; + mbopriv->ch_list[mbopriv->ch_list_num].preference = preference; + mbopriv->ch_list[mbopriv->ch_list_num].channel = *(pbuf + 1 + i); + mbopriv->ch_list_num += 1; + RTW_INFO("[%s:%d]channel = %d, preference = %d\n", __func__, __LINE__, + *(pbuf + 1 + i), preference); + } + } +} + +void rtw_mbo_ie_handler(_adapter *padapter, struct mbo_priv *mbopriv, const u8 *pbuf, uint limit_len) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + uint total_len = 0; + u8 attribute_id = 0; + u8 attribute_len = 0; + const u8 *p = pbuf; + + if(!mbopriv) + return; + + rtw_mbo_ie_init(padapter, mbopriv); + _rtw_memcpy(mbopriv->mbo_oce_element + 6, pbuf, limit_len); + mbopriv->mbo_oce_element[1] = limit_len + 4; + + while (total_len <= limit_len) { + attribute_id = *p; + attribute_len = *(p + 1); + total_len += attribute_len; + if(total_len > limit_len) + break; + + switch (attribute_id) { + case MBO_AP_CAPABILITY: + if(attribute_len == 1){ + RTW_INFO("[%s]Find attribute MBO_AP_CAPABILITY\n", __func__); + if(*(p+2) & 0x40) + mbopriv->cellular_aware = 1; + } + break; + case ASSOCIATION_DISALLOW: + if(attribute_len == 1){ + RTW_INFO("[%s]Find attribute ASSOCIATION_DISALLOW\n", __func__); + mbopriv->assoc_disallow = *(p+2); + } + break; + case NON_PREFER_CHANNEL_RPT: + RTW_INFO("[%s]Find attribute NON_PREFER_CHANNEL_RPT\n", __func__); + rtw_mbo_fill_non_prefer_channel_list(padapter, mbopriv, p + 2, attribute_len); + break; + case CELLULAR_DATA_CAPABILITY: + case CELLULAR_DATA_CONNECT_PREFER: + case TRANS_REASON_CODE: + case TRANS_REJECT_REASON_CODE: + case ASSOCIATION_RETRY_DELAY: + break; + default: + RTW_ERR("[%s]Unknown MBO attribute %d\n", __func__, attribute_id); + } + + p += (attribute_len + 2); + } +} + +void rtw_ap_parse_sta_mbo_element(_adapter *padapter, + struct sta_info *psta, u8 *ies_buf, u16 ies_len) +{ + uint ie_len = 0; + u8 *p; + u8 WIFI_ALLIANCE_OUI[] = {0x50, 0x6f, 0x9a}; + + ie_len = 0; + for (p = ies_buf; ; p += (ie_len + 2)) { + p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (ies_len - (ie_len + 2))); + if ((p) && (_rtw_memcmp(p + 2, WIFI_ALLIANCE_OUI, 3)) && (*(p+5) == MBO_OUI_TYPE)) { + /* find MBO-OCE information element */ + psta->mbopriv.enable = _TRUE; + rtw_mbo_ie_handler(padapter, &psta->mbopriv, p + 6, ie_len - 4); + break; + } + if ((p == NULL) || (ie_len == 0)) + break; + } +} + static u8 *rtw_mbo_ie_get(u8 *pie, u32 *plen, u32 limit) { const u8 *p = pie; u32 tmp, i; - + if (limit <= 1) return NULL; i = 0; *plen = 0; while (1) { - if ((*p == _VENDOR_SPECIFIC_IE_) && + if ((*p == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(rtw_mbo_get_oui(p), wfa_mbo_oui, 4))) { *plen = *(p + 1); - RTW_MBO_DUMP("VENDOR_SPECIFIC_IE MBO: ", p, *(p + 1)); + /* RTW_MBO_DUMP("VENDOR_SPECIFIC_IE MBO: ", p, *(p + 1)); */ return (u8 *)p; } else { tmp = *(p + 1); p += (tmp + 2); i += (tmp + 2); } - + if (i >= limit) break; } - - return NULL; + + return NULL; } -static u8 *rtw_mbo_attrs_get(u8 *pie, u32 limit, u8 attr_id, u32 *attr_len) +static u8 *rtw_mbo_attrs_get(u8 *pie, + u32 limit, u8 attr_id,u32 *attr_len, u8 dbg) { u8 *p = NULL; u32 offset, plen = 0; if ((pie == NULL) || (limit <= 1)) goto exit; - + if ((p = rtw_mbo_ie_get(pie, &plen, limit)) == NULL) goto exit; /* shift 2 + OUI size and move to attributes content */ p = p + 2 + sizeof(wfa_mbo_oui); plen = plen - 4; - RTW_MBO_DUMP("Attributes contents: ", p, plen); + + if (dbg) + RTW_MBO_DUMP("Attributes contents: ", p, plen); if ((p = rtw_get_ie(p, attr_id, attr_len, plen)) == NULL) goto exit; - RTW_MBO_INFO("%s : id=%u(len=%u)\n", __func__, attr_id, *attr_len); - RTW_MBO_DUMP("contents : ", p, *attr_len); + if (dbg) { + RTW_MBO_INFO("%s : id=%u(len=%u)\n", + __func__, attr_id, *attr_len); + RTW_MBO_DUMP("contents : ", (p + 2), *attr_len); + } exit: - return p; + return p; } @@ -133,22 +270,32 @@ static u32 rtw_mbo_attr_sz_get( switch (id) { case RTW_MBO_ATTR_NPREF_CH_RPT_ID: { - struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter); - struct npref_ch_rtp *prpt = &(prfctl->ch_rtp); + struct rf_ctl_t *prfctl = \ + adapter_to_rfctl(padapter); + struct npref_ch_rtp *prpt = \ + &(prfctl->ch_rtp); struct npref_ch* pch; u32 i, attr_len, offset; for (i=0; i < prpt->nm_of_rpt; i++) { pch = &prpt->ch_rpt[i]; - /*attr_len = ch list + op class + preference + reason */ + /*attr_len = ch list + op class + + preference + reason */ attr_len = pch->nm_of_ch + 3; - /* offset = id + len field + attr_len */ + /* offset = id + len field + + attr_len */ offset = attr_len + 2; len += offset; - } + } } break; + case RTW_MBO_ATTR_ASSOC_RETRY_DELAY_ID: + len = 4; + break; + case RTW_MBO_ATTR_AP_CAP_ID: case RTW_MBO_ATTR_CELL_DATA_CAP_ID: + case RTW_MBO_ATTR_ASSOC_DISABLED_ID: + case RTW_MBO_ATTR_TRANS_RES_ID: case RTW_MBO_ATTR_TRANS_REJ_ID: len = 3; break; @@ -163,11 +310,12 @@ static void rtw_mbo_build_mbo_ie_hdr( u8 **pframe, struct pkt_attrib *pattrib, u8 payload_len) { u8 eid = RTW_MBO_EID; - u8 len = payload_len + 4; + u8 len = payload_len + 4; *pframe = rtw_mbo_set_1byte_ie(*pframe, &eid, &(pattrib->pktlen)); *pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_4byte_ie(*pframe, wfa_mbo_oui, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_4byte_ie(*pframe, + wfa_mbo_oui, &(pattrib->pktlen)); } void rtw_mbo_build_cell_data_cap_attr( @@ -180,38 +328,108 @@ void rtw_mbo_build_cell_data_cap_attr( /* used Cellular Data Capabilities from supplicant */ if (!rtw_mbo_wifi_logo_test(padapter) && - pmlmepriv->pcell_data_cap_ie && pmlmepriv->cell_data_cap_len == 1) { + pmlmepriv->pcell_data_cap_ie && + pmlmepriv->cell_data_cap_len == 1) { cell_data_con = *pmlmepriv->pcell_data_cap_ie; - RTW_MBO_INFO("%s : used Cellular Data Capabilities(%u) from supplicant!\n", - __func__, *pmlmepriv->pcell_data_cap_ie); } - + + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &cell_data_con, &(pattrib->pktlen)); +} + + +static void rtw_mbo_build_ap_cap_Indication_attr( + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib, u8 cap_ind) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 attr_id = RTW_MBO_ATTR_AP_CAP_ID; + u8 attr_len = 1; + u8 ap_cap_ind = cap_ind; + + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &ap_cap_ind, &(pattrib->pktlen)); +} + +static void rtw_mbo_build_ap_disallowed_attr( + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib, u8 code) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 attr_id = RTW_MBO_ATTR_ASSOC_DISABLED_ID; + u8 attr_len = 1; + u8 reason = 0; + + if (code > 0) { + reason = code; + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &attr_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &reason, &(pattrib->pktlen)); + } +} + +static void rtw_mbo_build_ap_trans_reason_attr( + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib, u8 code) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 attr_id = RTW_MBO_ATTR_TRANS_RES_ID; + u8 attr_len = 1; + u8 reason = 0; + + reason = code; + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &attr_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &reason, &(pattrib->pktlen)); + } + +static void rtw_mbo_build_ap_assoc_retry_delay_attr( + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib, u16 code) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 attr_id = RTW_MBO_ATTR_ASSOC_RETRY_DELAY_ID; + u8 attr_len = 2; + u16 delay = 0; + + delay = code; *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_2byte_ie(*pframe, + (u8 *)&delay, &(pattrib->pktlen)); } static void rtw_mbo_update_cell_data_cap( _adapter *padapter, u8 *pie, u32 ie_len) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u8 *mbo_attr; + u8 *mbo_attr; u32 mbo_attrlen; if ((pie == NULL) || (ie_len == 0)) return; - mbo_attr = rtw_mbo_attrs_get(pie, ie_len, - RTW_MBO_ATTR_CELL_DATA_CAP_ID, &mbo_attrlen); + mbo_attr = rtw_mbo_attrs_get(pie, ie_len, + RTW_MBO_ATTR_CELL_DATA_CAP_ID, &mbo_attrlen, 0); if ((mbo_attr == NULL) || (mbo_attrlen == 0) ) { RTW_INFO("MBO : Cellular Data Capabilities not found!\n"); return; } - rtw_buf_update(&pmlmepriv->pcell_data_cap_ie, + rtw_buf_update(&pmlmepriv->pcell_data_cap_ie, &pmlmepriv->cell_data_cap_len, (mbo_attr + 2), mbo_attrlen); - RTW_MBO_DUMP("rtw_mbo_update_cell_data_cap : ", + RTW_MBO_DUMP("rtw_mbo_update_cell_data_cap : ", pmlmepriv->pcell_data_cap_ie, pmlmepriv->cell_data_cap_len); } @@ -224,7 +442,7 @@ void rtw_mbo_update_ie_data( static u8 rtw_mbo_current_op_class_get(_adapter *padapter) { struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter); - struct p2p_channels *pch_list = &(prfctl->channel_list); + struct p2p_channels *pch_list = &(prfctl->channel_list); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct p2p_reg_class *preg_class; int class_idx, ch_idx; @@ -233,22 +451,25 @@ static u8 rtw_mbo_current_op_class_get(_adapter *padapter) for(class_idx =0; class_idx < pch_list->reg_classes; class_idx++) { preg_class = &pch_list->reg_class[class_idx]; for (ch_idx = 0; ch_idx <= preg_class->channels; ch_idx++) { - if (pmlmeext->cur_channel == preg_class->channel[ch_idx]) { + if (pmlmeext->chandef.chan == \ + preg_class->channel[ch_idx]) { cur_op_class = preg_class->reg_class; - RTW_MBO_INFO("%s : current ch : %d, op class : %d\n", - __func__, pmlmeext->cur_channel, cur_op_class); + RTW_MBO_INFO("%s : current ch : %d," + " op class : %d\n", + __func__, pmlmeext->chandef.chan, + cur_op_class); break; } } } - + return cur_op_class; } static void rtw_mbo_supp_op_classes_get(_adapter *padapter, u8 *pclasses) { struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter); - struct p2p_channels *pch_list = &(prfctl->channel_list); + struct p2p_channels *pch_list = &(prfctl->channel_list); int class_idx; if (pclasses == NULL) @@ -256,11 +477,12 @@ static void rtw_mbo_supp_op_classes_get(_adapter *padapter, u8 *pclasses) RTW_MBO_INFO("%s : support op class \n", __func__); for(class_idx = 0; class_idx < pch_list->reg_classes; class_idx++) { - *(pclasses + class_idx) = pch_list->reg_class[class_idx].reg_class; - RTW_MBO_INFO("%u ,", *(pclasses + class_idx)); + *(pclasses + class_idx) = \ + pch_list->reg_class[class_idx].reg_class; + RTW_MBO_INFO("%u ,", *(pclasses + class_idx)); } - RTW_MBO_INFO("%s : \n", __func__); + RTW_MBO_INFO("%s : \n", __func__); } void rtw_mbo_build_supp_op_class_elem( @@ -283,11 +505,11 @@ void rtw_mbo_build_supp_op_class_elem( RTW_MBO_DUMP("op class :", payload, reg_class_nm); - /* Current Operating Class field + Operating Class field + /* Current Operating Class field + Operating Class field + OneHundredAndThirty Delimiter field */ - len = reg_class_nm + 3; - *pframe = rtw_set_ie(*pframe, EID_SupRegulatory, len , - payload, &(pattrib->pktlen)); + len = reg_class_nm + 3; + *pframe = rtw_set_ie(*pframe, EID_SupRegulatory, len , + payload, &(pattrib->pktlen)); } static u8 rtw_mbo_construct_npref_ch_rpt_attr( @@ -303,7 +525,7 @@ static u8 rtw_mbo_construct_npref_ch_rpt_attr( if (prpt->nm_of_rpt == 0) { *plen = 0; return _FALSE; - } + } for (i=0; i < prpt->nm_of_rpt; i++) { pch = &prpt->ch_rpt[i]; @@ -321,7 +543,7 @@ static u8 rtw_mbo_construct_npref_ch_rpt_attr( *plen += offset; if (*plen >= buf_len) { - RTW_ERR("MBO : construct non-preferred channel report fail!\n"); + RTW_ERR("MBO : construct non-preferred-ch rpt fail!\n"); return _FALSE; } } @@ -342,19 +564,22 @@ void rtw_mbo_build_npref_ch_rpt_attr( if (ptmp == NULL) return; - if (rtw_mbo_construct_npref_ch_rpt_attr(padapter, ptmp, tmp_sz, &body_len) == _FALSE) { + if (rtw_mbo_construct_npref_ch_rpt_attr( + padapter, ptmp, tmp_sz, &body_len) == _FALSE) { rtw_mfree(ptmp, tmp_sz); return; - } + } RTW_MBO_DUMP("Non-preferred Channel Report :", ptmp, body_len); - *pframe = rtw_mbo_set_nbyte_ie(*pframe, body_len, ptmp, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_nbyte_ie(*pframe, body_len, + ptmp, &(pattrib->pktlen)); rtw_mfree(ptmp, tmp_sz); } void rtw_mbo_build_trans_reject_reason_attr( - _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib, u8 *pres) + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib, u8 *pres) { u8 attr_id = RTW_MBO_ATTR_TRANS_REJ_ID; u8 attr_len = 1; @@ -362,13 +587,14 @@ void rtw_mbo_build_trans_reject_reason_attr( len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_TRANS_REJ_ID); if ((len == 0) || (len > 3)) { - RTW_ERR("MBO : build Transition Rejection Reason attribute fail(len=%u)\n", len); + RTW_ERR("MBO : build Transition Rejection Reason" + " attribute fail(len=%u)\n", len); return; } - + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len); *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen)); *pframe = rtw_mbo_set_1byte_ie(*pframe, pres, &(pattrib->pktlen)); } @@ -378,39 +604,41 @@ u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork) u32 attr_len = 0; u8 disallow = _FALSE; - if (pnetwork == NULL) - goto exit; - - p = rtw_mbo_attrs_get(pnetwork->network.IEs, - pnetwork->network.IELength, - RTW_MBO_ATTR_ASSOC_DISABLED_ID, - &attr_len); - - if (p == NULL) { - RTW_MBO_INFO("%s :Assoc Disallowed attribute not found!\n",__func__); + if ((pnetwork == NULL) || \ + ((p = rtw_mbo_attrs_get( + pnetwork->network.IEs, + pnetwork->network.IELength, + RTW_MBO_ATTR_ASSOC_DISABLED_ID, + &attr_len, 0)) == NULL)) { goto exit; } - + RTW_MBO_DUMP("Association Disallowed attribute :",p , attr_len + 2); RTW_INFO("MBO : block "MAC_FMT" assoc disallowed reason %d\n", - MAC_ARG(pnetwork->network.MacAddress), *(rtw_mbo_get_disallow_res(p))); + MAC_ARG(pnetwork->network.MacAddress), + *(rtw_mbo_get_disallow_res(p))); disallow = _TRUE; exit: return disallow; } -void rtw_mbo_build_exented_cap( +void rtw_mbo_build_extended_cap( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) { - u8 content[8] = { 0 }; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - rtw_wnm_set_ext_cap_btm(content, 1); - rtw_mbo_set_ext_cap_internw(content, 1); - *pframe = rtw_set_ie(*pframe, - EID_EXTCapability, - 8, - content, + if (!rtw_mbo_wifi_logo_test(padapter)) + return; + + rtw_wnm_add_btm_ext_cap(pmlmepriv->ext_capab_ie_data, + &(pmlmepriv->ext_capab_ie_len)); + rtw_mbo_add_internw_ext_cap(pmlmepriv->ext_capab_ie_data, + &(pmlmepriv->ext_capab_ie_len)); + *pframe = rtw_set_ie(*pframe, + WLAN_EID_EXT_CAP, + pmlmepriv->ext_capab_ie_len, + pmlmepriv->ext_capab_ie_data, &(pattrib->pktlen)); } @@ -422,8 +650,8 @@ static void rtw_mbo_non_pref_chans_dump(struct npref_ch* pch) for (i=0; i < pch->nm_of_ch; i++) rtw_sprintf(buf, 128, "%s,%d", buf, pch->chs[i]); - RTW_MBO_INFO("%s : op_class=%01x, ch=%s, preference=%d, reason=%d\n", - __func__, pch->op_class, buf, pch->preference, pch->reason); + RTW_MBO_INFO("%s : op_class=%01x, ch=%s, preference=%d, reason=%d\n", + __func__, pch->op_class, buf, pch->preference, pch->reason); } static u8 rtw_mbo_non_pref_chan_exist(struct npref_ch* pch, u8 ch) @@ -437,7 +665,7 @@ static u8 rtw_mbo_non_pref_chan_exist(struct npref_ch* pch, u8 ch) break; } } - + return found; } @@ -454,7 +682,7 @@ static struct npref_ch* rtw_mbo_non_pref_chan_get( for (i=0; i < prpt->nm_of_rpt; i++) { if ((prpt->ch_rpt[i].op_class == op_class) && - (prpt->ch_rpt[i].preference == prefe) && + (prpt->ch_rpt[i].preference == prefe) && (prpt->ch_rpt[i].reason == res)) { pch = &prpt->ch_rpt[i]; break; @@ -465,7 +693,8 @@ static struct npref_ch* rtw_mbo_non_pref_chan_get( } static void rtw_mbo_non_pref_chan_set( - struct npref_ch* pch, u8 op_class, u8 ch, u8 prefe, u8 res, u8 update) + struct npref_ch* pch, u8 op_class, + u8 ch, u8 prefe, u8 res, u8 update) { u32 offset = pch->nm_of_ch; @@ -491,14 +720,15 @@ static void rtw_mbo_non_pref_chans_update( struct npref_ch* pch; if (pch_rpt->nm_of_rpt >= RTW_MBO_MAX_CH_RPT_NUM) { - RTW_ERR("MBO : %d non_pref_chan entries supported!", + RTW_ERR("MBO : %d non_pref_chan entries supported!", RTW_MBO_MAX_CH_RPT_NUM); return; } if (pch_rpt->nm_of_rpt == 0) { pch = &pch_rpt->ch_rpt[0]; - rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE); + rtw_mbo_non_pref_chan_set(pch, op_class, + ch, prefe, res, _FALSE); pch_rpt->nm_of_rpt = 1; return; } @@ -506,10 +736,13 @@ static void rtw_mbo_non_pref_chans_update( pch = rtw_mbo_non_pref_chan_get(padapter, op_class, prefe, res); if (pch == NULL) { pch = &pch_rpt->ch_rpt[pch_rpt->nm_of_rpt]; - rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE); + rtw_mbo_non_pref_chan_set(pch, op_class, + ch, prefe, res, _FALSE); pch_rpt->nm_of_rpt++; - } else - rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _TRUE); + } else { + rtw_mbo_non_pref_chan_set(pch, op_class, + ch, prefe, res, _TRUE); + } rtw_mbo_non_pref_chans_dump(pch); } @@ -520,22 +753,23 @@ static void rtw_mbo_non_pref_chans_set( char *pnext; u32 op_class, ch, prefe, res; int i = 0; - + do { pnext = strsep(¶m, " "); if (pnext == NULL) break; sscanf(pnext, "%d:%d:%d:%d", &op_class, &ch, &prefe, &res); - rtw_mbo_non_pref_chans_update(padapter, op_class, ch, prefe, res); - + rtw_mbo_non_pref_chans_update(padapter, op_class, + ch, prefe, res); + if ((i++) > 10) { RTW_ERR("MBO : overflow %d \n", i); break; } - - } while(param != '\0'); - + + } while (param != (char*)'\0'); + } static void rtw_mbo_non_pref_chans_del( @@ -543,13 +777,13 @@ static void rtw_mbo_non_pref_chans_del( { struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter); struct npref_ch_rtp *prpt = &(prfctl->ch_rtp); - + RTW_INFO("%s : delete non_pref_chan %s\n", __func__, param); _rtw_memset(prpt, 0, sizeof(struct npref_ch_rtp)); } ssize_t rtw_mbo_proc_non_pref_chans_set( - struct file *pfile, const char __user *buffer, + struct file *pfile, const char __user *buffer, size_t count, loff_t *pos, void *pdata) { struct net_device *dev = pdata; @@ -566,22 +800,26 @@ ssize_t rtw_mbo_proc_non_pref_chans_set( } if (buffer && !copy_from_user(tmp, buffer, count)) { - if (strncmp(tmp, "add", 3) == 0) - rtw_mbo_non_pref_chans_set(padapter, &tmp[4], (count - 4)); - else if (strncmp(tmp, "delete", 6) == 0) - rtw_mbo_non_pref_chans_del(padapter, &tmp[7], (count - 7)); - else { - RTW_ERR("MBO : Invalid format : echo [add|delete] :::\n"); + if (strncmp(tmp, "add", 3) == 0) { + rtw_mbo_non_pref_chans_set(padapter, + &tmp[4], (count - 4)); + } else if (strncmp(tmp, "delete", 6) == 0) { + rtw_mbo_non_pref_chans_del(padapter, + &tmp[7], (count - 7)); + } else { + RTW_ERR("MBO : Invalid format : echo [add|delete]" + " :::\n"); return -EFAULT; } - } + } #ifdef CONFIG_RTW_WNM if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0); + check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + rtw_wnm_issue_action(padapter, + RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0); #endif - + return count; } @@ -599,26 +837,25 @@ int rtw_mbo_proc_non_pref_chans_get( RTW_PRINT_SEL(m, "op_class ch preference reason \n"); RTW_PRINT_SEL(m, "=======================================================\n"); - if (prpt->nm_of_rpt == 0) { RTW_PRINT_SEL(m, " empty table \n"); return 0; } for (i=0; i < prpt->nm_of_rpt; i++) { - pch = &prpt->ch_rpt[i]; + pch = &prpt->ch_rpt[i]; buf[0]='\0'; for (j=0; j < pch->nm_of_ch; j++) { if (j == 0) rtw_sprintf(buf, 32, "%02u", pch->chs[j]); - else + else rtw_sprintf(buf, 32, "%s,%02u", buf, pch->chs[j]); } RTW_PRINT_SEL(m, " %04u %20s %02u %02u\n", - pch->op_class, buf, pch->preference, pch->reason); + pch->op_class, buf, pch->preference, pch->reason); } - + return 0; } @@ -644,13 +881,14 @@ ssize_t rtw_mbo_proc_cell_data_set( rtw_mbo_cell_data_conn = mbo_cell_data; #ifdef CONFIG_RTW_WNM if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0); + check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + rtw_wnm_issue_action(padapter, + RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0); + } #endif } } - return count; } @@ -662,7 +900,389 @@ int rtw_mbo_proc_cell_data_get( _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); #endif - RTW_PRINT_SEL(m, "Cellular Data Connectivity : %d\n", rtw_mbo_cell_data_conn); + RTW_PRINT_SEL(m, "Cellular Data Connectivity : %d\n", + rtw_mbo_cell_data_conn); + return 0; +} + + +static void rtw_mbo_disassoc(_adapter *padapter, u8 *da, + u8 reason, u8 wait_ack) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe; + u16 *fctrl; + int ret = _FAIL; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + pattrib->key_type = IEEE80211W_RIGHT_KEY; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_DISASSOC); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + reason = cpu_to_le16(reason); + pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , + (unsigned char *)&reason, &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + if (wait_ack) + dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else + dump_mgntframe(padapter, pmgntframe); + RTW_MBO_INFO("%s : reason %u\n", __func__, reason); +} + +static void rtw_mbo_construct_user_btm_req( + _adapter *padapter, struct btm_req_hdr *phdr, + u8 *purl, u32 url_len, struct wnm_btm_cant *pbtm_cant) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser = &(pmbo_attr->user_raw); + struct wnm_btm_cant *puser_cant = NULL; + + if (phdr) { + puser->hdr.req_mode = phdr->req_mode; + puser->hdr.disassoc_timer = phdr->disassoc_timer; + puser->hdr.validity_interval = phdr->validity_interval; + puser->hdr.term_duration.tsf = phdr->term_duration.tsf; + puser->hdr.term_duration.duration = \ + phdr->term_duration.duration; + puser->hdr.term_duration.id = 0x4; + puser->hdr.term_duration.len = 0xa; + RTW_MBO_INFO("%s : req-mode=0x%x, disassoc_timer=%u, " + "validity_interval=%u, tsf=%llu, " + "duration=%u\n", __func__, + puser->hdr.req_mode, puser->hdr.disassoc_timer, + puser->hdr.validity_interval, + puser->hdr.term_duration.tsf, + puser->hdr.term_duration.duration); + } + + if (purl && url_len) { + /* TODO */ + } + + if (pbtm_cant) { + struct wnm_btm_cant *pbtm_tb = NULL; + u8 i, idx, found = _FALSE; + + for (i = 0; i < RTW_MAX_NB_RPT_NUM; i++) { + puser_cant = &puser->btm_cants[i]; + if (_rtw_memcmp(pbtm_cant->nb_rpt.bssid, + puser_cant->nb_rpt.bssid, ETH_ALEN)) { + puser_cant->nb_rpt.bss_info = \ + pbtm_cant->nb_rpt.bss_info; + puser_cant->nb_rpt.reg_class = \ + pbtm_cant->nb_rpt.reg_class; + puser_cant->nb_rpt.ch_num = \ + pbtm_cant->nb_rpt.ch_num; + puser_cant->nb_rpt.phy_type = \ + pbtm_cant->nb_rpt.phy_type; + puser_cant->preference = \ + pbtm_cant->preference; + idx = i; + found = _TRUE; + break; + } + } + + if (!found) { + if (puser->candidate_cnt >= RTW_MAX_NB_RPT_NUM) + puser->candidate_cnt = 0; + puser_cant = &puser->btm_cants[puser->candidate_cnt]; + puser_cant->nb_rpt.id = \ + RTW_WLAN_ACTION_WNM_NB_RPT_ELEM; + puser_cant->nb_rpt.len = 0x10; + _rtw_memcpy(puser_cant->nb_rpt.bssid, + pbtm_cant->nb_rpt.bssid, ETH_ALEN); + puser_cant->nb_rpt.bss_info = \ + pbtm_cant->nb_rpt.bss_info; + puser_cant->nb_rpt.reg_class = \ + pbtm_cant->nb_rpt.reg_class; + puser_cant->nb_rpt.ch_num = \ + pbtm_cant->nb_rpt.ch_num; + puser_cant->nb_rpt.phy_type = \ + pbtm_cant->nb_rpt.phy_type; + puser_cant->preference = \ + pbtm_cant->preference; + idx = puser->candidate_cnt; + puser->candidate_cnt++; + } + + RTW_MBO_INFO("%s:%s idx=%u, bssid("MAC_FMT")," + " bss_info(0x%04X), reg_class(0x%02X)," + " ch(%d), phy_type(0x%02X), preference(0x%02X)\n", + __func__, (found)?"update":"new", idx, + MAC_ARG(puser_cant->nb_rpt.bssid), + puser_cant->nb_rpt.bss_info, + puser_cant->nb_rpt.reg_class, + puser_cant->nb_rpt.ch_num, + puser_cant->nb_rpt.phy_type, + puser_cant->preference); + + } /* end of if (pbtm_cant) */ +} + +static void rtw_mbo_reset_user_btm_req_preference(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser = &(pmbo_attr->user_raw); + struct wnm_btm_cant *puser_cant = NULL; + u8 i; + + for (i = 0; i < RTW_MAX_NB_RPT_NUM; i++) { + puser_cant = &puser->btm_cants[i]; + if (_rtw_memcmp(adapter_mac_addr(padapter), + puser_cant->nb_rpt.bssid, ETH_ALEN)) { + puser_cant->preference = 0; + RTW_MBO_INFO("%s : reset "MAC_FMT" BTM preference\n", + __func__, MAC_ARG(puser_cant->nb_rpt.bssid)); + break; + } + } + +} + +ssize_t rtw_mbo_proc_attr_set( + struct file *pfile, const char __user *buffer, + size_t count, loff_t *pos, void *pdata) +{ + struct net_device *dev = pdata; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser = &(pmbo_attr->user_raw); + u32 id, val; + u8 tmp[64] = {0}; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) + return -EFAULT; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d %d", &id, &val); + switch (id) { + case RTW_MBO_ATTR_AP_CAP_ID: + pmbo_attr->ap_cap_ind = val; + break; + case RTW_MBO_ATTR_CELL_DATA_CAP_ID: + pmbo_attr->cell_data_cap = val; + break; + case RTW_MBO_ATTR_ASSOC_DISABLED_ID: + pmbo_attr->assoc_disallow = val; + break; + case RTW_MBO_ATTR_TRANS_RES_ID: + pmbo_attr->reason = val; + break; + case RTW_MBO_ATTR_ASSOC_RETRY_DELAY_ID: + pmbo_attr->delay = val; + break; + case RTW_MBO_TEST_CMD_REST: + RTW_INFO("%s : RTW_MBO_TEST_CMD_REST\n", + __func__); + _rtw_memset(pmbo_attr, 0, + sizeof(struct mbo_attr_info)); + pmbo_attr->mbo_spec_test = 1; + break; + case RTW_MBO_TEST_CMD_BTM_REQ_SET: + if (count >= 10) { + struct btm_req_hdr btm_hdr; + u32 disassoc_imnt, term_bit; + u32 term_tsf, term_duration; + + _rtw_memset(&btm_hdr, 0, + sizeof(btm_hdr)); + + num = sscanf(tmp, "%d %u %u %u %u", + &id, &disassoc_imnt, + &term_bit, &term_tsf, + &term_duration); + + if (num < 5) + break; + + if (disassoc_imnt > 0) + btm_hdr.req_mode |= \ + DISASSOC_IMMINENT; + + if (term_bit > 0) + btm_hdr.req_mode |= \ + BSS_TERMINATION_INCLUDED; + + btm_hdr.term_duration.tsf = term_tsf; + btm_hdr.term_duration.duration = \ + term_duration; + + rtw_mbo_construct_user_btm_req( + padapter, &btm_hdr, NULL, 0, + NULL); + } + break; + case RTW_MBO_TEST_CMD_BTM_REQ_SEND: + if (count >= 12) { + u8 mac_str[18] = {0}; + u8 dst_mac[ETH_ALEN] = {0}; + u32 cand_list = 0, disassoc_timer = 0; + + num = sscanf(tmp, "%d %s %u %u", + &id, mac_str, &cand_list, + &disassoc_timer); + + if (num < 4) + break; + + if (sscanf(mac_str, MAC_SFMT, + MAC_SARG( + dst_mac)) != 6) { + break; + } + + puser->append_mbo_ie = _TRUE; + puser->hdr.dialog_token++; + puser->hdr.validity_interval = 0xf; + if (cand_list > 0) + puser->hdr.req_mode |= \ + PREFERRED_CANDIDATE_LIST_INCLUDED; + + + puser->hdr.disassoc_timer = \ + disassoc_timer; + + if ((puser->hdr.req_mode & \ + DISASSOC_IMMINENT) == \ + DISASSOC_IMMINENT) { + rtw_mbo_reset_user_btm_req_preference(padapter); + if (pmbo_attr->delay == 0) + pmbo_attr->delay = 1; + if (puser->hdr.disassoc_timer == 0) + puser->hdr.disassoc_timer = 1000; + } + + if ((puser->hdr.req_mode & \ + BSS_TERMINATION_INCLUDED) == \ + BSS_TERMINATION_INCLUDED) { + puser->append_mbo_ie = _FALSE; + } + + if (!puser->candidate_cnt) { + struct wnm_btm_cant cant; + _rtw_memset(&cant, 0, + sizeof(cant)); + _rtw_memcpy(cant.nb_rpt.bssid, + adapter_mac_addr(padapter), + ETH_ALEN); + cant.nb_rpt.reg_class = 115; + cant.nb_rpt.ch_num = 36; + cant.preference = 0; + rtw_mbo_construct_user_btm_req( + padapter, NULL, + NULL, 0, &cant); + } + + rtw_wnm_issue_btm_req(padapter, dst_mac, + &puser->hdr, NULL, 0, + (u8 *)&puser->btm_cants, + puser->candidate_cnt); + + if ((puser->hdr.term_duration.duration) + && (puser->hdr.req_mode & \ + BSS_TERMINATION_INCLUDED) == \ + BSS_TERMINATION_INCLUDED) { + rtw_mbo_disassoc(padapter, + dst_mac, 3, _TRUE); + } + + if ((puser->hdr.req_mode & \ + DISASSOC_IMMINENT) == \ + DISASSOC_IMMINENT) { + rtw_mbo_disassoc(padapter, + dst_mac, 3, _TRUE); + } + } /* end of if (count >= 12) */ + + break; + case RTW_MBO_TEST_CMD_NB_BSS_ADD: + if (count >= 12) { + u8 bss_str[18]; + struct wnm_btm_cant cant; + u32 op, op_ch, perf; + + num = sscanf(tmp, "%d %s %u %u %u", + &id, bss_str, &op, &op_ch, + &perf); + if (num < 5) + break; + _rtw_memset(&cant, 0, sizeof(cant)); + if (sscanf(bss_str, MAC_SFMT, + MAC_SARG( + cant.nb_rpt.bssid)) != 6) { + break; + } + + cant.nb_rpt.reg_class = op; + cant.nb_rpt.ch_num = op_ch; + cant.preference = perf; + rtw_mbo_construct_user_btm_req( + padapter, NULL, NULL, 0, + &cant); + } /* end of if (count >= 12) */ + break; + default: + break; + } + } + + return count; +} + +int rtw_mbo_proc_attr_get( + struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + + RTW_PRINT_SEL(m, "AP Capability Indication : %d\n", + pmbo_attr->ap_cap_ind); + RTW_PRINT_SEL(m, "Cellular Data Capabilities : %d\n", + pmbo_attr->cell_data_cap); + RTW_PRINT_SEL(m, "Association Disallowed : %d\n", + pmbo_attr->assoc_disallow); return 0; } @@ -670,14 +1290,15 @@ static void rtw_mbo_non_pref_chan_subelem_parsing( _adapter *padapter, u8 *subelem, size_t subelem_len) { u8 *pnon_pref_chans; - u32 non_pref_chan_offset, op_subelem_len; + u32 non_pref_chan_offset, op_subelem_len; u32 oui_offset = 3; /* wpa_supplicant don't apped OUI Type */ u32 oui_type_offset = 0; - RTW_MBO_DUMP("Non-preferred Channel subelem : ", subelem , subelem_len); + RTW_MBO_DUMP("Non-preferred Channel subelem : ", + subelem , subelem_len); - /* Subelem : + /* Subelem : Vendor Specific | Length | WFA OUI | OUI Type | MBO Attributes */ non_pref_chan_offset = 2 + oui_offset + oui_type_offset; pnon_pref_chans = subelem + non_pref_chan_offset; @@ -685,7 +1306,8 @@ static void rtw_mbo_non_pref_chan_subelem_parsing( /* wpa_supplicant don't indicate non_pref_chan length, so we cannot get how many non_pref_chan in a wnm notification */ - RTW_MBO_DUMP("Non-preferred Channel : ", pnon_pref_chans, op_subelem_len); + RTW_MBO_DUMP("Non-preferred Channel : ", + pnon_pref_chans, op_subelem_len); } void rtw_mbo_wnm_notification_parsing( @@ -698,19 +1320,18 @@ void rtw_mbo_wnm_notification_parsing( if ((pdata == NULL) || (data_len == 0)) return; - RTW_MBO_DUMP("WNM notification data : ", pdata, data_len); + RTW_MBO_DUMP("WNM notification data : ", pdata, data_len); paction = (u8 *)pdata + sizeof(struct rtw_ieee80211_hdr_3addr); category = paction[0]; action = paction[1]; dialog = paction[2]; type = paction[3]; - if ((action == RTW_WLAN_ACTION_WNM_NOTIF_REQ) && + if ((action == RTW_WLAN_ACTION_WNM_NOTIF_REQ) && (type == WLAN_EID_VENDOR_SPECIFIC)) { - rtw_mbo_non_pref_chan_subelem_parsing(padapter, &paction[4], + rtw_mbo_non_pref_chan_subelem_parsing(padapter, &paction[4], (data_len - sizeof(struct rtw_ieee80211_hdr_3addr))); } - } void rtw_mbo_build_wnm_notification( @@ -728,37 +1349,54 @@ void rtw_mbo_build_wnm_notification( if (rtw_mbo_cell_data_conn > 0) { len = 0x5; - *pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_4byte_ie(*pframe, cell_data_cap_oui, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen)); - RTW_MBO_INFO("%s : Cellular Data Capabilities subelemen\n", __func__); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &subelem_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_4byte_ie(*pframe, + cell_data_cap_oui, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &cell_data_con, &(pattrib->pktlen)); + RTW_MBO_INFO("%s : Cellular Data Capabilities subelemen\n", + __func__); RTW_MBO_DUMP(":", pcont, len + 2); pcont += len + 2 ; } if (prpt->nm_of_rpt == 0) { len = 0x4; - *pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen)); - RTW_MBO_INFO("%s :Non-preferred Channel Report subelement without data\n", __func__); - return; + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &subelem_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_4byte_ie(*pframe, + non_pref_ch_oui, &(pattrib->pktlen)); + RTW_MBO_INFO("%s :Non-preferred Channel Report subelement" + " without data\n", __func__); + return; } for (i=0; i < prpt->nm_of_rpt; i++) { - pch = &prpt->ch_rpt[i]; - /* OUI(3B) + OUT-type(1B) + op-class(1B) + ch list(nB) + pch = &prpt->ch_rpt[i]; + /* OUI(3B) + OUT-type(1B) + op-class(1B) + ch list(nB) + Preference(1B) + reason(1B) */ len = pch->nm_of_ch + 7; - *pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->op_class, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_nbyte_ie(*pframe, pch->nm_of_ch, pch->chs, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->preference, &(pattrib->pktlen)); - *pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->reason, &(pattrib->pktlen)); - RTW_MBO_INFO("%s :Non-preferred Channel Report subelement\n", __func__); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &subelem_id, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &len, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_4byte_ie(*pframe, + non_pref_ch_oui, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &pch->op_class, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_nbyte_ie(*pframe, + pch->nm_of_ch, pch->chs, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &pch->preference, &(pattrib->pktlen)); + *pframe = rtw_mbo_set_1byte_ie(*pframe, + &pch->reason, &(pattrib->pktlen)); + RTW_MBO_INFO("%s :Non-preferred Channel Report" + " subelement\n", __func__); RTW_MBO_DUMP(":", pcont, len); pcont = *pframe; } @@ -768,15 +1406,16 @@ void rtw_mbo_build_probe_req_ies( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) { u32 len =0; - - rtw_mbo_build_exented_cap(padapter, pframe, pattrib); + + rtw_mbo_build_extended_cap(padapter, pframe, pattrib); len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID); if ((len == 0) || (len > 3)) { - RTW_ERR("MBO : build Cellular Data Capabilities attribute fail(len=%u)\n", len); + RTW_ERR("MBO : build Cellular Data Capabilities" + " attribute fail(len=%u)\n", len); return; } - + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len); rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib); } @@ -785,7 +1424,7 @@ void rtw_mbo_build_assoc_req_ies( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) { u32 len = 0; - + rtw_mbo_build_supp_op_class_elem(padapter, pframe, pattrib); len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID); @@ -794,10 +1433,195 @@ void rtw_mbo_build_assoc_req_ies( RTW_ERR("MBO : build assoc MBO IE fail(len=%u)\n", len); return; } - + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len); rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib); rtw_mbo_build_npref_ch_rpt_attr(padapter, pframe, pattrib); } +static void rtw_mbo_build_ap_capability( + _adapter *padapter, u8 **pframe, + struct pkt_attrib *pattrib) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + u8 *pcap = NULL; + u32 cap_len = 0, flen = 0; + + if ((pcap = rtw_mbo_attrs_get( + (cur_network->IEs + _FIXED_IE_LENGTH_), + (cur_network->IELength - _FIXED_IE_LENGTH_), + RTW_MBO_ATTR_AP_CAP_ID, &cap_len, 0)) != NULL) + return; + + flen += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_AP_CAP_ID); + if (pmbo_attr->assoc_disallow > 0) + flen += rtw_mbo_attr_sz_get(padapter, + RTW_MBO_ATTR_ASSOC_DISABLED_ID); + if (flen > 0) { + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, flen); + rtw_mbo_build_ap_cap_Indication_attr(padapter, pframe, + pattrib, pmbo_attr->ap_cap_ind); + + if (pmbo_attr->assoc_disallow > 0) { + rtw_mbo_build_ap_disallowed_attr(padapter, pframe, + pattrib, pmbo_attr->assoc_disallow); + } + } /* end of if (flen > 0) */ + +} + +void rtw_mbo_attr_info_init(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + + _rtw_memset(pmbo_attr, 0, sizeof(struct mbo_attr_info)); +} + +void rtw_mbo_process_assoc_req( + _adapter *padapter, u8 *pie, int ie_len) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + u8 non_pref_ch = 0, ch_op_pref = 1; + u8 *pattr = NULL, *ptr = NULL; + u32 attr_len = 0, ch_nums = 0; + int i, j; + + if (!pie || !ie_len) + return; + + if ((pattr = rtw_mbo_attrs_get(pie, ie_len, + RTW_MBO_ATTR_NPREF_CH_RPT_ID, &attr_len, 1)) == NULL) + return; + + if (attr_len < 3) + return; + + ch_nums = (attr_len - 3); + + /* shfit to non-preferred ch rpt field */ + ptr = pattr + 3; + RTW_MBO_DUMP("non-preferred ch rpt :", ptr, ch_nums); + + ch_op_pref = *(ptr + ch_nums); + RTW_MBO_INFO("%s : ch_op_pref=0x%02x\n", __func__, ch_op_pref); + + if (ch_op_pref >= 2) { + RTW_MBO_INFO("%s : unknow ch operating preference(0x%02x)\n", + __func__, ch_op_pref); + return; + } + + for (i = 0; i < ch_nums; i++) { + if (i >= RTW_MBO_MAX_CH_LIST_NUM) + break; + non_pref_ch = *(ptr + i); + RTW_MBO_INFO("%s : non-pref ch %u found in assoc-req\n", + __func__, non_pref_ch); + + if (rtw_mbo_wifi_spec_test(padapter)) { + struct mbo_user_btm_req_pkt *puser_raw = \ + &(pmbo_attr->user_raw); + struct wnm_btm_cant *pcant = NULL; + + for (j = 0; j < RTW_MAX_NB_RPT_NUM; j++) { + pcant = &puser_raw->btm_cants[j]; + if ((pcant->nb_rpt.ch_num == non_pref_ch) && \ + (ch_op_pref == 0)) { + RTW_MBO_INFO("%s : reset " + "preference(%u) for non-preference ch\n", + __func__, pcant->preference); + pcant->preference = 0; + } + } + } + + } /* end of for-loop ch_nums */ + +} + +void rtw_mbo_build_beacon_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) +{ + rtw_mbo_build_ap_capability(padapter, pframe, pattrib); +} + +void rtw_mbo_build_probe_rsp_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) +{ + rtw_mbo_build_ap_capability(padapter, pframe, pattrib); +} + +void rtw_mbo_build_assoc_rsp_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + u8 *pcap = NULL; + u32 len = 0, cap_len = 0 ; + + /* driver would't reload all assoc-rsp ie from hostapd */ + #if 0 + if ((pcap = rtw_mbo_attrs_get( + (cur_network->IEs + _FIXED_IE_LENGTH_), + (cur_network->IELength - _FIXED_IE_LENGTH_), + RTW_MBO_ATTR_AP_CAP_ID, &cap_len, 0)) != NULL) + return; + #endif + + len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_AP_CAP_ID); + if (pmbo_attr->assoc_disallow > 0) + len += rtw_mbo_attr_sz_get(padapter, + RTW_MBO_ATTR_ASSOC_DISABLED_ID); + + if (len > 0) { + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len); + rtw_mbo_build_ap_cap_Indication_attr( + padapter, pframe, pattrib, pmbo_attr->ap_cap_ind); + if (pmbo_attr->assoc_disallow > 0) { + rtw_mbo_build_ap_disallowed_attr(padapter, pframe, + pattrib, pmbo_attr->assoc_disallow); + } + } + +} + +void rtw_mbo_build_wnm_btmreq_reason_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser = &(pmbo_attr->user_raw); + u8 *pcap = NULL; + u32 len = 0, cap_len = 0 ; + + if (!puser->append_mbo_ie) + return; + + len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_AP_CAP_ID); + len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_TRANS_RES_ID); + len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_ASSOC_RETRY_DELAY_ID); + + rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len); + + rtw_mbo_build_ap_cap_Indication_attr( + padapter, pframe, pattrib, pmbo_attr->ap_cap_ind); + + rtw_mbo_build_ap_trans_reason_attr(padapter, pframe, + pattrib, pmbo_attr->reason); + + rtw_mbo_build_ap_assoc_retry_delay_attr(padapter, pframe, + pattrib, pmbo_attr->delay); +} #endif /* CONFIG_RTW_MBO */ diff --git a/core/rtw_mem.c b/core/rtw_mem.c index d42a4fb..d9f5652 100644 --- a/core/rtw_mem.c +++ b/core/rtw_mem.c @@ -21,49 +21,6 @@ MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); MODULE_AUTHOR("Realtek Semiconductor Corp."); MODULE_VERSION("DRIVERVERSION"); -/* for MAX_RECVBUF_SZ */ -#if defined(CONFIG_RTL8188E) -#include -#elif defined(CONFIG_RTL8188F) -#include -#elif defined(CONFIG_RTL8188GTV) -#include -#elif defined(CONFIG_RTL8710B) -#include -#elif defined(CONFIG_RTL8192E) -#include -#elif defined(CONFIG_RTL8192F) -#include -#elif defined(CONFIG_RTL8723B) -#include -#elif defined(CONFIG_RTL8703B) -#include -#elif defined(CONFIG_RTL8723D) -#include -#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) -#include -#elif defined(CONFIG_RTL8822B) -#include -#elif defined(CONFIG_RTL8822C) -#include -#elif defined(CONFIG_RTL8814A) -#include -#elif defined(CONFIG_RTL8814B) -#include -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -#define MAX_RTKM_RECVBUF_SZ MAX_RECVBUF_SZ -#define MAX_RTKM_NR_PREALLOC_RECV_SKB NR_RECVBUFF -#else /* !CONFIG_SDIO_HCI */ -#ifdef CONFIG_PLATFORM_MSTAR_HIGH - #define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */ -#else - #define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */ -#endif /* CONFIG_PLATFORM_MSTAR_HIGH */ -#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16 -#endif /* !CONFIG_SDIO_HCI */ - struct sk_buff_head rtk_skb_mem_q; struct u8 *rtk_buf_mem[NR_RECVBUFF]; diff --git a/core/rtw_mi.c b/core/rtw_mi.c index 099cd36..d00b8fe 100644 --- a/core/rtw_mi.c +++ b/core/rtw_mi.c @@ -15,43 +15,16 @@ #define _RTW_MI_C_ #include -#include void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mi_state *iface_state = &dvobj->iface_state; - if (!ch) { - dvobj->union_ch_bak = dvobj->union_ch; - dvobj->union_bw_bak = dvobj->union_bw; - dvobj->union_offset_bak = dvobj->union_offset; - } - dvobj->union_ch = ch; - dvobj->union_bw = bw; - dvobj->union_offset = offset; -} - -#ifdef DBG_IFACE_STATUS -#ifdef CONFIG_P2P -static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter) -{ - int i; - _adapter *iface; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - u8 p2p_listen_scan_state = _FALSE; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) || - rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) { - p2p_listen_scan_state = _TRUE; - break; - } - } - return p2p_listen_scan_state; + iface_state->union_ch = ch; + iface_state->union_bw = bw; + iface_state->union_offset = offset; } -#endif -#endif u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter) { @@ -73,11 +46,11 @@ u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter) #ifdef DBG_IFACE_STATUS if (rst == _FALSE) { RTW_ERR("%s Not stay in union channel\n", __func__); - if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE) + if (GET_PHL_COM(adapter_to_dvobj(adapter))->bScanInProcess == _TRUE) RTW_ERR("ScanInProcess\n"); - #ifdef CONFIG_P2P - if (_rtw_mi_p2p_listen_scan_chk(adapter)) - RTW_ERR("P2P in listen or scan state\n"); + #ifdef CONFIG_IOCTL_CFG80211 + if (rtw_cfg80211_get_is_roch(adapter)) + RTW_ERR("Doing remain on channel\n"); #endif RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset); RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset); @@ -95,8 +68,8 @@ u8 rtw_mi_stayin_union_band_chk(_adapter *adapter) u_ch = rtw_mi_get_union_chan(adapter); o_ch = rtw_get_oper_ch(adapter); - u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; - o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; + u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_24G; + o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_24G; if (u_ch != o_ch) if(u_band != o_band) @@ -118,7 +91,7 @@ int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 int i; u8 ch_ret = 0; u8 bw_ret = CHANNEL_WIDTH_20; - u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 offset_ret = CHAN_OFFSET_NO_EXT; int num = 0; if (ch) @@ -126,7 +99,7 @@ int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 if (bw) *bw = CHANNEL_WIDTH_20; if (offset) - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -142,22 +115,22 @@ int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 continue; if (num == 0) { - ch_ret = mlmeext->cur_channel; - bw_ret = mlmeext->cur_bwmode; - offset_ret = mlmeext->cur_ch_offset; + ch_ret = mlmeext->chandef.chan; + bw_ret = mlmeext->chandef.bw; + offset_ret = mlmeext->chandef.offset; num++; continue; } - if (ch_ret != mlmeext->cur_channel) { + if (ch_ret != mlmeext->chandef.chan) { num = 0; break; } - if (bw_ret < mlmeext->cur_bwmode) { - bw_ret = mlmeext->cur_bwmode; - offset_ret = mlmeext->cur_ch_offset; - } else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) { + if (bw_ret < mlmeext->chandef.bw) { + bw_ret = mlmeext->chandef.bw; + offset_ret = mlmeext->chandef.offset; + } else if (bw_ret == mlmeext->chandef.bw && offset_ret != mlmeext->chandef.offset) { num = 0; break; } @@ -187,6 +160,7 @@ inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset); } +/* For now, not return union_ch/bw/offset */ void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate) { _adapter *iface; @@ -199,7 +173,7 @@ void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state if (!iface || !(ifbmp & BIT(iface->iface_id))) continue; - if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(iface)) { MSTATE_STA_NUM(mstate)++; if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { MSTATE_STA_LD_NUM(mstate)++; @@ -262,10 +236,10 @@ void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state #ifdef CONFIG_IOCTL_CFG80211 if (rtw_cfg80211_get_is_mgmt_tx(iface)) MSTATE_MGMT_TX_NUM(mstate)++; - + #ifdef CONFIG_P2P if (rtw_cfg80211_get_is_roch(iface) == _TRUE) MSTATE_ROCH_NUM(mstate)++; - + #endif #endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_P2P if (MLME_IS_PD(iface)) @@ -289,6 +263,7 @@ inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate) return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate); } +/* For now, not handle union_ch/bw/offset */ inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a) { d->sta_num += a->sta_num; @@ -369,6 +344,7 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct mi_state *iface_state = &dvobj->iface_state; struct mi_state tmp_mstate; + u8 u_ch, u_offset, u_bw; if (state == WIFI_MONITOR_STATE || state == 0xFFFFFFFF @@ -381,6 +357,16 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) rtw_mi_status(adapter, &tmp_mstate); _rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state)); + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) + rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw); + else { + if (0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + RTW_INFO("%s-[ERROR] cannot get union channel\n", __func__); + rtw_warn_on(1); + } + } + #ifdef DBG_IFACE_STATUS DBG_IFACE_STATUS_DUMP(adapter); #endif @@ -526,6 +512,49 @@ u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter) return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop); } +static u8 _rtw_mi_disconnect(_adapter *adapter, void *data) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) + && check_fwstate(mlme, WIFI_ASOC_STATE)) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(adapter, mlmeext->chandef.chan, mlmeext->chandef.offset); + else + #endif + #ifdef CONFIG_STA_CMD_DISPR + rtw_phl_cmd_stop_beacon(adapter_to_dvobj(adapter)->phl, adapter->phl_role, _TRUE, PHL_CMD_NO_WAIT, 0); + #else + rtw_phl_cmd_stop_beacon(adapter_to_dvobj(adapter)->phl, adapter->phl_role, _TRUE, PHL_CMD_DIRECTLY, 0); + #endif + rtw_sta_flush(adapter, _FALSE); + + rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0); + set_fwstate(mlme, WIFI_OP_CH_SWITCHING); + rtw_phl_chanctx_del(adapter_to_dvobj(adapter)->phl, adapter->phl_role, NULL); + + } else if (MLME_IS_STA(adapter) + && check_fwstate(mlme, WIFI_ASOC_STATE)) { + rtw_disassoc_cmd(adapter, 500, RTW_CMDF_DIRECTLY); +#ifndef CONFIG_STA_CMD_DISPR + rtw_free_assoc_resources(adapter, _TRUE); +#endif /* !CONFIG_STA_CMD_DISPR */ + rtw_indicate_disconnect(adapter, 0, _FALSE); + } + return _TRUE; +} + +u8 rtw_mi_disconnect(_adapter *adapter) +{ + return _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_disconnect); +} +u8 rtw_mi_buddy_disconnect(_adapter *adapter) +{ + return _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_disconnect); +} + static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data) { struct net_device *pnetdev = padapter->pnetdev; @@ -615,7 +644,7 @@ static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data) bool bwait = *(bool *)data; if (bwait) - rtw_scan_abort(adapter); + rtw_scan_abort(adapter, 0); else rtw_scan_abort_no_wait(adapter); @@ -635,6 +664,7 @@ void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait) _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort); } +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self) { int i; @@ -687,6 +717,7 @@ void rtw_mi_buddy_stop_drv_threads(_adapter *adapter) { _rtw_mi_stop_drv_threads(adapter, _TRUE); } +#endif static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data) { @@ -716,51 +747,24 @@ void rtw_mi_buddy_reset_drv_sw(_adapter *adapter) _rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw); } -static u8 _rtw_mi_intf_start(_adapter *adapter, void *data) -{ - rtw_intf_start(adapter); - return _TRUE; -} -void rtw_mi_intf_start(_adapter *adapter) -{ - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start); -} -void rtw_mi_buddy_intf_start(_adapter *adapter) -{ - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start); -} - -static u8 _rtw_mi_intf_stop(_adapter *adapter, void *data) -{ - rtw_intf_stop(adapter); - return _TRUE; -} -void rtw_mi_intf_stop(_adapter *adapter) -{ - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop); -} -void rtw_mi_buddy_intf_stop(_adapter *adapter) -{ - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop); -} - -#ifdef CONFIG_NEW_NETDEV_HDL u8 rtw_mi_hal_iface_init(_adapter *padapter) { int i; _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - - u8 ret = _TRUE; + u8 ret = _SUCCESS; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; - if (iface && iface->netif_up) - rtw_hal_iface_init(padapter); + if (iface && iface->netif_up) { + ret = rtw_hw_iface_init(iface); + if (ret == _FAIL) + break; + } } return ret; } -#endif + static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data) { @@ -812,13 +816,12 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms) } #endif /*CONFIG_SET_SCAN_DENY_TIMER*/ -#ifdef CONFIG_AP_MODE static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data) { if (!MLME_IS_STA(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter)); - update_beacon(padapter, 0xFF, NULL, _TRUE, 0); + rtw_update_beacon(padapter, 0xFF, NULL, _TRUE, 0); } return _TRUE; } @@ -832,47 +835,6 @@ void rtw_mi_buddy_beacon_update(_adapter *padapter) { _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update); } -#endif /* CONFIG_AP_MODE */ - -#ifndef CONFIG_MI_WITH_MBSSID_CAM -static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *sel) -{ - u8 mac_addr[ETH_ALEN] = {0}; - - rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr); - RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", - ADPT_ARG(padapter), padapter->hw_port, MAC_ARG(mac_addr)); - - return _TRUE; -} -void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter) -{ - _rtw_mi_process(padapter, _FALSE, sel, _rtw_mi_hal_dump_macaddr); -} -void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter) -{ - _rtw_mi_process(padapter, _TRUE, sel, _rtw_mi_hal_dump_macaddr); -} -#endif - -#ifdef CONFIG_PCI_HCI -static u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data) -{ - if (rtw_txframes_pending(padapter)) { - /* try to deal with the pending packets */ - tasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet)); - } - return _TRUE; -} -void rtw_mi_xmit_tasklet_schedule(_adapter *padapter) -{ - _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule); -} -void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter) -{ - _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule); -} -#endif u8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data) { @@ -985,9 +947,9 @@ static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data) pdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop; /* Rx */ - pdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes; - pdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts; - pdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop; + pdvobjpriv->traffic_stat.rx_bytes += padapter->recvinfo.rx_bytes; + pdvobjpriv->traffic_stat.rx_pkts += padapter->recvinfo.rx_pkts; + pdvobjpriv->traffic_stat.rx_drop += padapter->recvinfo.rx_drop; return _TRUE; } u8 rtw_mi_traffic_statistics(_adapter *padapter) @@ -1004,7 +966,7 @@ u8 rtw_mi_check_miracast_enabled(_adapter *padapter) return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled); } -#ifdef CONFIG_XMIT_THREAD_MODE +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ static u8 _rtw_mi_check_pending_xmitbuf(_adapter *padapter , void *data) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -1022,7 +984,8 @@ u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter) #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -static u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self) +#include +static u8 _rtw_mi_dequeue_xmit(_adapter *padapter , bool exclude_self) { int i; u8 queue_empty = _TRUE; @@ -1036,18 +999,18 @@ static u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self) if ((exclude_self) && (iface == padapter)) continue; - queue_empty &= _dequeue_writeport(iface); + queue_empty &= sdio_dequeue_xmit(iface); } } return queue_empty; } -u8 rtw_mi_dequeue_writeport(_adapter *padapter) +u8 rtw_mi_sdio_dequeue_xmit(_adapter *padapter) { - return _rtw_mi_dequeue_writeport(padapter, _FALSE); + return _rtw_mi_dequeue_xmit(padapter, _FALSE); } -u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter) +u8 rtw_mi_sdio_buddy_dequeue_xmit(_adapter *padapter) { - return _rtw_mi_dequeue_writeport(padapter, _TRUE); + return _rtw_mi_dequeue_xmit(padapter, _TRUE); } #endif static void _rtw_mi_adapter_reset(_adapter *padapter , u8 exclude_self) @@ -1074,6 +1037,18 @@ void rtw_mi_buddy_adapter_reset(_adapter *padapter) _rtw_mi_adapter_reset(padapter, _TRUE); } +static u8 _rtw_mi_dynamic_check_handlder(struct _ADAPTER *a, void *data) +{ + rtw_iface_dynamic_check_handlder(a); + return _TRUE; +} + +u8 rtw_mi_dynamic_check_handlder(struct _ADAPTER *a) +{ + return _rtw_mi_process(a, _FALSE, NULL, _rtw_mi_dynamic_check_handlder); +} + +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data) { rtw_iface_dynamic_check_timer_handlder(adapter); @@ -1087,6 +1062,7 @@ u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter) { return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder); } +#endif static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data) { @@ -1149,7 +1125,7 @@ u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart) return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl); } -#if defined(CONFIG_AP_MODE) && defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) void rtw_mi_ap_info_restore(_adapter *adapter) { int i; @@ -1177,8 +1153,6 @@ u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart) return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_sreset_adapter_hdl); } - -#ifdef CONFIG_AP_MODE static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data) { if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) @@ -1220,33 +1194,14 @@ u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter) { return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_set_tx_beacon_cmd); } -#endif /* CONFIG_AP_MODE */ #ifdef CONFIG_P2P -static u8 _rtw_mi_p2p_chk_state(_adapter *adapter, void *data) -{ - struct wifidirect_info *pwdinfo = &(adapter->wdinfo); - enum P2P_STATE state = *(enum P2P_STATE *)data; - - return rtw_p2p_chk_state(pwdinfo, state); -} -u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state) -{ - u8 in_data = p2p_state; - - return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_p2p_chk_state); -} -u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state) -{ - u8 in_data = p2p_state; - - return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_p2p_chk_state); -} static u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data) { struct wifidirect_info *pwdinfo = &(adapter->wdinfo); - if (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE) + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) || + rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) return _TRUE; return _FALSE; } @@ -1269,6 +1224,7 @@ _adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id) rtw_warn_on(1); return iface; } + dvobj = adapter_to_dvobj(padapter); dvobj = adapter_to_dvobj(padapter); return dvobj->padapters[iface_id]; @@ -1281,6 +1237,10 @@ _adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr) u8 bmatch = _FALSE; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); +#ifdef RTW_PHL_TEST_FPGA + return dvobj->padapters[0]; +#endif + for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && (_rtw_memcmp(mac_addr, adapter_mac_addr(iface), ETH_ALEN))) { @@ -1319,7 +1279,7 @@ _adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port) #ifdef DBG_SKB_PROCESS void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union recv_frame *pcloneframe) { - _pkt *pkt_copy, *pkt_org; + struct sk_buff *pkt_copy, *pkt_org; pkt_org = precvframe->u.hdr.pkt; pkt_copy = pcloneframe->u.hdr.pkt; @@ -1363,7 +1323,8 @@ void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union } #endif -static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe) +static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, + union recv_frame *precvframe, union recv_frame *pcloneframe) { s32 ret = _SUCCESS; #ifdef CONFIG_SKB_ALLOCATED @@ -1394,29 +1355,27 @@ static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame * #ifdef DBG_SKB_PROCESS rtw_dbg_skb_process(adapter, precvframe, pcloneframe); #endif + validate_recv_frame(adapter, pcloneframe); - if (pphy_status) - rx_query_phy_status(pcloneframe, pphy_status); - - ret = rtw_recv_entry(pcloneframe); } else { - ret = -1; - RTW_INFO("%s()-%d: rtw_os_alloc_recvframe() failed!\n", __func__, __LINE__); + ret = _FAIL; + RTW_ERR("%s()-%d: rtw_os_alloc_recvframe() failed!\n", __func__, __LINE__); } - } return ret; } -void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status) + +void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, + union recv_frame *precvframe) { int i; s32 ret = _SUCCESS; _adapter *iface = NULL; union recv_frame *pcloneframe = NULL; - struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/ - _queue *pfree_recv_queue = &precvpriv->free_recv_queue; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct recv_priv *precvpriv = &dvobj->recvpriv; + _queue *pfree_recv_queue = &precvpriv->free_recv_queue; u8 *fhead = get_recvframe_data(precvframe); u8 type = GetFrameType(fhead); @@ -1431,15 +1390,16 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf pcloneframe = rtw_alloc_recvframe(pfree_recv_queue); if (pcloneframe) { - ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe); - if (_SUCCESS != ret) { - if (ret == -1) - rtw_free_recvframe(pcloneframe, pfree_recv_queue); - /*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/ - } + ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pcloneframe); + if (ret == _FAIL) + RTW_ERR("_rtw_mi_buddy_clone_bcmc_packet failed!\n"); + + rtw_free_recvframe(pcloneframe); + } else { + RTW_ERR("%s rtw_alloc_recvframe failed\n", __func__); + rtw_warn_on(1); } } - } #ifdef CONFIG_PCI_HCI @@ -1503,31 +1463,6 @@ u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter) return ifbmp; } -void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b) -{ -#ifdef CONFIG_CONCURRENT_MODE - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - - int i; - _adapter *iface = NULL; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - - if (macid_ctl->iface_bmc[iface->iface_id] != INVALID_SEC_MAC_CAM_ID) { - if (macid_ctl->iface_bmc[iface->iface_id] == camid_a) - macid_ctl->iface_bmc[iface->iface_id] = camid_b; - else if (macid_ctl->iface_bmc[iface->iface_id] == camid_b) - macid_ctl->iface_bmc[iface->iface_id] = camid_a; - iface->securitypriv.dot118021x_bmc_cam_id = macid_ctl->iface_bmc[iface->iface_id]; - } - } -#endif -} - u8 rtw_mi_get_assoc_if_num(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index 024c144..9def9e3 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -13,13 +13,9 @@ * *****************************************************************************/ #define _RTW_MLME_C_ +#include -#include -#ifdef CONFIG_PLATFORM_CMAP_INTFS -#include "../os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.h" -#endif -extern void indicate_wx_scan_complete_event(_adapter *padapter); extern u8 rtw_do_join(_adapter *padapter); @@ -27,11 +23,11 @@ void rtw_init_mlme_timer(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter); - rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter); + rtw_init_timer(&(pmlmepriv->assoc_timer), rtw_join_timeout_handler, padapter); + rtw_init_timer(&(pmlmepriv->scan_to_timer), rtw_scan_timeout_handler, padapter); #ifdef CONFIG_SET_SCAN_DENY_TIMER - rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter); + rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), rtw_set_scan_deny_timer_hdl, padapter); #endif #ifdef RTK_DMP_PLATFORM @@ -70,7 +66,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pmlmepriv->pscanned = NULL; init_fwstate(pmlmepriv, WIFI_STATION_STATE); pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; - pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */ + pmlmepriv->scan_mode = RTW_PHL_SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */ _rtw_spinlock_init(&(pmlmepriv->lock)); _rtw_init_queue(&(pmlmepriv->free_bss_pool)); @@ -112,17 +108,20 @@ sint _rtw_init_mlme_priv(_adapter *padapter) _rtw_init_queue(&(pmlmepriv->unassoc_sta_queue)); for (i = 0; i < UNASOC_STA_SRC_NUM; i++) pmlmepriv->unassoc_sta_mode_of_stype[i] = padapter->registrypriv.unassoc_sta_mode_of_stype[i]; + if (padapter->registrypriv.max_unassoc_sta_cnt != 0) pmlmepriv->max_unassoc_sta_cnt = padapter->registrypriv.max_unassoc_sta_cnt; else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G) pmlmepriv->max_unassoc_sta_cnt = MAX_UNASSOC_STA_CNT; else pmlmepriv->max_unassoc_sta_cnt = MAX_UNASSOC_STA_CNT * 2; + pbuf = rtw_zvmalloc(pmlmepriv->max_unassoc_sta_cnt * (sizeof(struct unassoc_sta_info))); if (pbuf == NULL) { res = _FAIL; goto exit; } + pmlmepriv->free_unassoc_sta_buf = pbuf; unassoc_sta = (struct unassoc_sta_info *) pbuf; for (i = 0; i < pmlmepriv->max_unassoc_sta_cnt; i++) { @@ -131,9 +130,6 @@ sint _rtw_init_mlme_priv(_adapter *padapter) unassoc_sta++; } } -#ifdef CONFIG_PLATFORM_CMAP_INTFS - rtw_init_timer(&pmlmepriv->cmap_unassoc_sta_timer, padapter, cmap_unassoc_sta_report_info_timer, padapter); -#endif #endif /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ @@ -148,7 +144,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) #define RTW_ROAM_RSSI_DIFF_TH 10 #define RTW_ROAM_SCAN_INTERVAL (5) /* 5*(2 second)*/ #define RTW_ROAM_RSSI_THRESHOLD 70 -#define RTW_ROAM_DICONNECT_DELAY 20 + pmlmepriv->roam_flags = CONFIG_ROAMING_FLAG; pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS; @@ -162,11 +158,18 @@ sint _rtw_init_mlme_priv(_adapter *padapter) #ifdef CONFIG_RTW_80211R rtw_ft_info_init(&pmlmepriv->ft_roam); #endif + +#ifdef CONFIG_RTW_MBO #ifdef CONFIG_LAYER2_ROAMING #if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) rtw_roam_nb_info_init(padapter); pmlmepriv->ch_cnt = 0; #endif +#endif +#endif + +#ifdef CONFIG_RTW_MBO + rtw_mbo_attr_info_init(padapter); #endif pmlmepriv->defs_lmt_sta = 2; @@ -180,7 +183,6 @@ sint _rtw_init_mlme_priv(_adapter *padapter) return res; } -void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv); void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv) { _rtw_spinlock_free(&pmlmepriv->lock); @@ -194,35 +196,47 @@ void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv) #endif } +static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen) +{ + if (*ppie) { + rtw_mfree(*ppie, *plen); + *plen = 0; + *ppie = NULL; + } +} + void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) { +#ifdef CONFIG_80211D + rtw_buf_free(&pmlmepriv->recv_country_ie, &pmlmepriv->recv_country_ie_len); +#endif +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - rtw_buf_free(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); - rtw_buf_free(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); - rtw_buf_free(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); - rtw_buf_free(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); - - rtw_buf_free(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); - rtw_buf_free(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); - rtw_buf_free(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); - rtw_buf_free(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); - rtw_buf_free(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); - rtw_buf_free(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); + + rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len); #endif #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) - rtw_buf_free(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len); - rtw_buf_free(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len); - rtw_buf_free(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len); - rtw_buf_free(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len); - rtw_buf_free(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len); - rtw_buf_free(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len); #endif #ifdef CONFIG_RTW_80211R - rtw_buf_free(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len); + rtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len); #endif #ifdef CONFIG_RTW_MBO rtw_buf_free(&pmlmepriv->pcell_data_cap_ie, &pmlmepriv->cell_data_cap_len); @@ -239,7 +253,7 @@ int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_ u32 *t_ie_len = NULL; int ret = _FAIL; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto success; if (wfd_info->wfd_enable == _TRUE) @@ -340,14 +354,12 @@ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) if (pmlmepriv->free_bss_buf) rtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network)); + #ifdef CONFIG_RTW_MULTI_AP if (is_primary_adapter(adapter)) { if (pmlmepriv->free_unassoc_sta_buf) rtw_vmfree(pmlmepriv->free_unassoc_sta_buf, pmlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info)); } -#ifdef CONFIG_PLATFORM_CMAP_INTFS - _cancel_timer_ex(&pmlmepriv->cmap_unassoc_sta_timer); -#endif #endif } exit: @@ -356,17 +368,15 @@ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) { - _irqL irqL; - if (pnetwork == NULL) goto exit; - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); rtw_list_insert_tail(&pnetwork->list, &queue->queue); - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); exit: @@ -377,12 +387,11 @@ sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) /* struct wlan_network *_rtw_dequeue_network(_queue *queue) { - _irqL irqL; struct wlan_network *pnetwork; - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); if (_rtw_queue_empty(queue) == _TRUE) @@ -395,7 +404,7 @@ struct wlan_network *_rtw_dequeue_network(_queue *queue) rtw_list_delete(&(pnetwork->list)); } - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); return pnetwork; @@ -404,13 +413,12 @@ struct wlan_network *_rtw_dequeue_network(_queue *queue) struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ { - _irqL irqL; struct wlan_network *pnetwork; _queue *free_queue = &pmlmepriv->free_bss_pool; _list *plist = NULL; - _enter_critical_bh(&free_queue->lock, &irqL); + _rtw_spinlock_bh(&free_queue->lock); if (_rtw_queue_empty(free_queue) == _TRUE) { pnetwork = NULL; @@ -437,7 +445,7 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue pmlmepriv->num_of_scanned++; exit: - _exit_critical_bh(&free_queue->lock, &irqL); + _rtw_spinunlock_bh(&free_queue->lock); return pnetwork; @@ -447,7 +455,6 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo { u32 delta_time; u32 lifetime = SCANQUEUE_LIFETIME; - _irqL irqL; _queue *free_queue = &(pmlmepriv->free_bss_pool); @@ -467,7 +474,7 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo goto exit; } - _enter_critical_bh(&free_queue->lock, &irqL); + _rtw_spinlock_bh(&free_queue->lock); rtw_list_delete(&(pnetwork->list)); @@ -478,7 +485,7 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo /* RTW_INFO("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); */ - _exit_critical_bh(&free_queue->lock, &irqL); + _rtw_spinunlock_bh(&free_queue->lock); exit: return; @@ -496,7 +503,7 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * if (pnetwork->fixed == _TRUE) goto exit; - /* _enter_critical(&free_queue->lock, &irqL); */ + /* _rtw_spinlock_irq(&free_queue->lock, &sp_flags); */ rtw_list_delete(&(pnetwork->list)); @@ -504,7 +511,7 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * pmlmepriv->num_of_scanned--; - /* _exit_critical(&free_queue->lock, &irqL); */ + /* _rtw_spinunlock_irq(&free_queue->lock, &sp_flags); */ exit: return; @@ -512,7 +519,7 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) { - _irqL irqL; + _list *phead, *plist; struct wlan_network *pnetwork; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -520,7 +527,7 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) - _enter_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinlock_bh(&scanned_queue->lock); phead = get_list_head(scanned_queue); plist = get_next(phead); @@ -535,7 +542,7 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) } - _exit_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinunlock_bh(&scanned_queue->lock); } @@ -548,7 +555,7 @@ sint rtw_if_up(_adapter *padapter) sint res; - if (RTW_CANNOT_RUN(padapter) || + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter)) || (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) { res = _FALSE; } else @@ -604,38 +611,18 @@ void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) _rtw_free_mlme_priv(pmlmepriv); } -int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); -int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) +int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) { int res; res = _rtw_enqueue_network(queue, pnetwork); return res; } -/* -static struct wlan_network *rtw_dequeue_network(_queue *queue) -{ - struct wlan_network *pnetwork; - pnetwork = _rtw_dequeue_network(queue); - return pnetwork; -} -*/ - -struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv); -struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ -{ - struct wlan_network *pnetwork; - pnetwork = _rtw_alloc_network(pmlmepriv); - return pnetwork; -} - -void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall); void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)/* (struct wlan_network *pnetwork, _queue *free_queue) */ { _rtw_free_network(pmlmepriv, pnetwork, is_freeall); } -void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork); void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork) { _rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork); @@ -683,11 +670,10 @@ struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr) struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr) { struct wlan_network *pnetwork; - _irqL irqL; - _enter_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinlock_bh(&scanned_queue->lock); pnetwork = _rtw_find_network(scanned_queue, addr); - _exit_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinunlock_bh(&scanned_queue->lock); return pnetwork; } @@ -716,14 +702,11 @@ inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE; } -int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst) { u16 s_cap, d_cap; - if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE) - return _FALSE; - _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2); _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2); @@ -731,14 +714,6 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) s_cap = le16_to_cpu(s_cap); d_cap = le16_to_cpu(d_cap); - -#ifdef CONFIG_P2P - if ((feature == 1) && /* 1: P2P supported */ - (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE) - ) - return _TRUE; -#endif - /* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, * it considers these two packets are sent from different AP. * Therefore, the scan queue may store two scan results of the same hidden AP, likes below. @@ -781,7 +756,7 @@ struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_n while (plist != phead) { found = LIST_CONTAINOR(plist, struct wlan_network , list); - if (is_same_network(&network->network, &found->network, 0)) + if (is_same_network(&network->network, &found->network)) break; plist = get_next(plist); @@ -795,15 +770,14 @@ struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_n struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) { - _irqL irqL; struct wlan_network *found = NULL; if (scanned_queue == NULL || network == NULL) goto exit; - _enter_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinlock_bh(&scanned_queue->lock); found = _rtw_find_same_network(scanned_queue, network); - _exit_critical_bh(&scanned_queue->lock, &irqL); + _rtw_spinunlock_bh(&scanned_queue->lock); exit: return found; @@ -838,30 +812,30 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) } -void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, +void rtw_update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie) { #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 u8 ss_ori = dst->PhyInfo.SignalStrength; u8 sq_ori = dst->PhyInfo.SignalQuality; u8 ss_smp = src->PhyInfo.SignalStrength; - long rssi_smp = src->Rssi; + s8 rssi_smp = src->PhyInfo.rssi; #endif - long rssi_ori = dst->Rssi; + s8 rssi_ori = dst->PhyInfo.rssi; u8 sq_smp = src->PhyInfo.SignalQuality; u8 ss_final; u8 sq_final; - long rssi_final; + s8 rssi_final; #ifdef CONFIG_ANTENNA_DIVERSITY - rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */ + rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src->PhyInfo.rssi, need consider again */ #endif #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { - RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n" + RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%d, ss_smp:%3u, sq_smp:%3u, rssi_smp:%d\n" , FUNC_ADPT_ARG(padapter) , src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig , ss_ori, sq_ori, rssi_ori @@ -871,25 +845,25 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, #endif /* The rule below is 1/5 for sample value, 4/5 for history value */ - if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) { + if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) { /* Take the recvpriv's value for the connected AP*/ - ss_final = padapter->recvpriv.signal_strength; - sq_final = padapter->recvpriv.signal_qual; + ss_final = padapter->recvinfo.signal_strength; + sq_final = padapter->recvinfo.signal_qual; /* the rssi value here is undecorated, and will be used for antenna diversity */ if (sq_smp != 101) /* from the right channel */ - rssi_final = (src->Rssi + dst->Rssi * 4) / 5; + rssi_final = (src->PhyInfo.rssi + dst->PhyInfo.rssi * 4) / 5; else rssi_final = rssi_ori; } else { if (sq_smp != 101) { /* from the right channel */ ss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5; sq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5; - rssi_final = (src->Rssi + dst->Rssi * 4) / 5; + rssi_final = (src->PhyInfo.rssi + dst->PhyInfo.rssi * 4) / 5; } else { /* bss info not receving from the right channel, use the original RX signal infos */ ss_final = dst->PhyInfo.SignalStrength; sq_final = dst->PhyInfo.SignalQuality; - rssi_final = dst->Rssi; + rssi_final = dst->PhyInfo.rssi; } } @@ -899,349 +873,67 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, dst->Reserved[1] = src->Reserved[1]; _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src)); } -#ifdef CONFIG_LAYER2_ROAMING - dst->tsf = src->tsf; -#endif + dst->PhyInfo.SignalStrength = ss_final; dst->PhyInfo.SignalQuality = sq_final; - dst->Rssi = rssi_final; + dst->PhyInfo.rssi = rssi_final; #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { - RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n" + RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%d\n" , FUNC_ADPT_ARG(padapter) - , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi); - } -#endif - -#if 0 /* old codes, may be useful one day... - * RTW_INFO("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); */ - if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) { - - /* RTW_INFO("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); */ - if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) { - padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; - last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; - padapter->recvpriv.signal_qual_data.total_val -= last_evm; - } - padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi); - - padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi); - if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) - padapter->recvpriv.signal_qual_data.index = 0; - - /* RTW_INFO("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); */ - - /* <1> Showed on UI for user,in percentage. */ - tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num; - padapter->recvpriv.signal = (u8)tmpVal; /* Link quality */ - - src->Rssi = translate_percentage_to_dbm(padapter->recvpriv.signal) ; - } else { - /* RTW_INFO("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); */ - src->Rssi = (src->Rssi + dst->Rssi) / 2; /* dBM */ + , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), + dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->PhyInfo.rssi); } - - /* RTW_INFO("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); */ - #endif - } -static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +#ifdef CONFIG_RTW_MULTI_AP +void rtw_map_config_monitor_act_non(_adapter *adapter) { - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - - - rtw_bug_check(&(pmlmepriv->cur_network.network), - &(pmlmepriv->cur_network.network), - &(pmlmepriv->cur_network.network), - &(pmlmepriv->cur_network.network)); - - if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) { - - /* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */ - { - update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE); - rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs), - pmlmepriv->cur_network.network.IELength); - } - } - - + rtw_map_config_monitor(adapter, MLME_ACTION_NONE); } - -/* - -Caller must hold pmlmepriv->lock first. - - -*/ -bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +void rtw_map_config_monitor(_adapter *adapter, u8 self_act) { - _irqL irqL; - _list *plist, *phead; - u32 bssid_ex_sz; - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(adapter->wdinfo); -#endif /* CONFIG_P2P */ - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - struct wlan_network *choice = NULL; - int target_find = 0; - u8 feature = 0; - bool update_ie = _FALSE; - - _enter_critical_bh(&queue->lock, &irqL); - phead = get_list_head(queue); - plist = get_next(phead); - -#if 0 - RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n", - __func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength); -#endif - -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - feature = 1; /* p2p enable */ -#endif - - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; - - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - - rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork); - -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && - (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) { - target_find = 1; - break; - } -#endif - - if (is_same_network(&(pnetwork->network), target, feature)) { - target_find = 1; - break; - } - - if (rtw_roam_flags(adapter)) { - /* TODO: don't select netowrk in the same ess as choice if it's new enough*/ - } - if (pnetwork->fixed) { - plist = get_next(plist); - continue; - } - -#ifdef CONFIG_RSSI_PRIORITY - if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength)) - #ifdef CONFIG_RTW_MESH - if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) - || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) - #endif - choice = pnetwork; -#else - if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned)) - #ifdef CONFIG_RTW_MESH - if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) - || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) - #endif - choice = pnetwork; -#endif - plist = get_next(plist); - - } - - - /* If we didn't find a match, then get a new network slot to initialize - * with this beacon's information */ - /* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */ - if (!target_find) { - if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { - /* If there are no more slots, expire the choice */ - /* list_del_init(&choice->list); */ - pnetwork = choice; - if (pnetwork == NULL) - goto unlock_scan_queue; - -#ifdef CONFIG_RSSI_PRIORITY - RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n", - __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength); -#else - RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n", - __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); -#endif - -#ifdef CONFIG_ANTENNA_DIVERSITY - rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL); -#endif - _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); - pnetwork->bcn_keys_valid = 0; - if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) - rtw_update_bcn_keys_of_network(pnetwork); - /* variable initialize */ - pnetwork->fixed = _FALSE; - pnetwork->last_scanned = rtw_get_current_time(); - pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned; - #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT - pnetwork->acnode_stime = 0; - pnetwork->acnode_notify_etime = 0; - #endif -#ifdef CONFIG_LAYER2_ROAMING - pnetwork->network.tsf = target->tsf; -#endif - pnetwork->network_type = 0; - pnetwork->aid = 0; - pnetwork->join_res = 0; - - /* bss info not receving from the right channel */ - if (pnetwork->network.PhyInfo.SignalQuality == 101) - pnetwork->network.PhyInfo.SignalQuality = 0; - } else { - /* Otherwise just pull from the free list */ - - pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */ - if (pnetwork == NULL) - goto unlock_scan_queue; - - bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); - target->Length = bssid_ex_sz; -#ifdef CONFIG_ANTENNA_DIVERSITY - rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL); -#endif - _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz); - pnetwork->bcn_keys_valid = 0; - if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) - rtw_update_bcn_keys_of_network(pnetwork); - - /* bss info not receving from the right channel */ - if (pnetwork->network.PhyInfo.SignalQuality == 101) - pnetwork->network.PhyInfo.SignalQuality = 0; - - rtw_list_insert_tail(&(pnetwork->list), &(queue->queue)); - - } - } else { - /* we have an entry and we are going to update it. But this entry may - * be already expired. In this case we do the same as we found a new - * net and call the new_net handler - */ - #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT - systime last_scanned = pnetwork->last_scanned; - #endif - struct beacon_keys bcn_keys; - bool bcn_keys_valid = 0; - bool is_hidden_ssid_ap = 0; - - pnetwork->last_scanned = rtw_get_current_time(); - - if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) { - if (target->InfrastructureMode == Ndis802_11Infrastructure) { - is_hidden_ssid_ap = hidden_ssid_ap(target); - if (!is_hidden_ssid_ap) /* update last time it's non hidden ssid AP */ - pnetwork->last_non_hidden_ssid_ap = rtw_get_current_time(); - } - bcn_keys_valid = rtw_get_bcn_keys_from_bss(target, &bcn_keys); - } + struct mi_state mstate, mstate_s; + void *phl = GET_PHL_INFO(adapter_to_dvobj(adapter)); - if (target->InfrastructureMode == Ndis802_11_mesh - || target->Reserved[0] >= pnetwork->network.Reserved[0]) - update_ie = _TRUE; - else if (target->InfrastructureMode == Ndis802_11Infrastructure && !pnetwork->fixed - && rtw_get_passing_time_ms(pnetwork->last_non_hidden_ssid_ap) > SCANQUEUE_LIFETIME) - update_ie = _TRUE; - else if (bcn_keys_valid) { - if (is_hidden_ssid(bcn_keys.ssid, bcn_keys.ssid_len)) { - /* hidden ssid, replace with current beacon ssid directly */ - _rtw_memcpy(bcn_keys.ssid, pnetwork->bcn_keys.ssid, pnetwork->bcn_keys.ssid_len); - bcn_keys.ssid_len = pnetwork->bcn_keys.ssid_len; - } - if (rtw_bcn_key_compare(&pnetwork->bcn_keys, &bcn_keys) == _FALSE) - update_ie = _TRUE; - } - - #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT - if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) - || pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig - || rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms - || !rtw_bss_is_same_mbss(&pnetwork->network, target) - ) { - pnetwork->acnode_stime = 0; - pnetwork->acnode_notify_etime = 0; - } - #endif + rtw_mi_status_no_self(adapter, &mstate); + rtw_mi_status_no_others(adapter, &mstate_s); - if (bcn_keys_valid) { - _rtw_memcpy(&pnetwork->bcn_keys, &bcn_keys, sizeof(bcn_keys)); - pnetwork->bcn_keys_valid = 1; - } else if (update_ie) - pnetwork->bcn_keys_valid = 0; - - update_network(&(pnetwork->network), target, adapter, update_ie); + switch (self_act) { + case MLME_AP_STARTED: + mstate_s.ap_num = 1; + break; + case MLME_AP_STOPPED: + mstate_s.ap_num = 0; + break; + case MLME_ACTION_NONE: + break; + default: + break; } - #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT - if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) - rtw_mesh_update_scanned_acnode_status(adapter, pnetwork); - #endif - -unlock_scan_queue: - _exit_critical_bh(&queue->lock, &irqL); - -#ifdef CONFIG_RTW_MESH - if (pnetwork && MLME_IS_MESH(adapter) - && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) - && !check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) - ) - rtw_chk_candidate_peer_notify(adapter, pnetwork); -#endif - - return update_ie; -} - -void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); -void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) -{ - bool update_ie; - /* _queue *queue = &(pmlmepriv->scanned_queue); */ - - /* _enter_critical_bh(&queue->lock, &irqL); */ - -#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) - if (adapter->registrypriv.wifi_spec == 0) - rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); -#endif - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) - rtw_bss_ex_del_wfd_ie(pnetwork); - /* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */ - update_ie = rtw_update_scanned_network(adapter, pnetwork); - - if (update_ie) - update_current_network(adapter, pnetwork); - - /* _exit_critical_bh(&queue->lock, &irqL); */ - + rtw_mi_status_merge(&mstate, &mstate_s); + if (MSTATE_AP_NUM(&mstate) && + rtw_unassoc_sta_src_chk(adapter, UNASOC_STA_SRC_RX_NMY_UC)) + rtw_phl_enter_mon_mode(phl, adapter->phl_role); + else + rtw_phl_leave_mon_mode(phl, adapter->phl_role); } -#ifdef CONFIG_RTW_MULTI_AP void rtw_unassoc_sta_set_mode(_adapter *adapter, u8 stype, u8 mode) { - if (stype >= UNASOC_STA_SRC_NUM - || mode >= UNASOC_STA_MODE_NUM) + if (stype >= UNASOC_STA_SRC_NUM || mode >= UNASOC_STA_MODE_NUM) return; adapter = GET_PRIMARY_ADAPTER(adapter); - if (adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == mode) return; - - adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] = mode; - rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), adapter, 2000); + adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] = mode; + rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_map_config_monitor_act_non)), adapter, 2000); } bool rtw_unassoc_sta_src_chk(_adapter *adapter, u8 stype) @@ -1250,11 +942,9 @@ bool rtw_unassoc_sta_src_chk(_adapter *adapter, u8 stype) return 0; adapter = GET_PRIMARY_ADAPTER(adapter); - return adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == UNASOC_STA_MODE_ALL || (adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == UNASOC_STA_MODE_INTERESTED - && adapter->mlmepriv.interested_unassoc_sta_cnt) - ; + && adapter->mlmepriv.interested_unassoc_sta_cnt); } const char *unasoc_sta_src_str[] = { @@ -1280,30 +970,29 @@ void dump_unassoc_sta(void *sel, _adapter *adapter) adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - for (i = 0; i < UNASOC_STA_SRC_NUM; i++) { - RTW_PRINT_SEL(sel, "[%u]%-6s:%u(%s)\n", i, unasoc_sta_src_str[i] - , mlmepriv->unassoc_sta_mode_of_stype[i], unasoc_sta_mode_str[mlmepriv->unassoc_sta_mode_of_stype[i]]); + RTW_PRINT_SEL(sel, "[%u]%-6s:%u(%s)\n", i, unasoc_sta_src_str[i], + mlmepriv->unassoc_sta_mode_of_stype[i], + unasoc_sta_mode_str[mlmepriv->unassoc_sta_mode_of_stype[i]]); } - RTW_PRINT_SEL(sel, "interested_unassoc_sta_cnt:%u\n", mlmepriv->interested_unassoc_sta_cnt); + + RTW_PRINT_SEL(sel, "interested_unassoc_sta_cnt:%u\n", + mlmepriv->interested_unassoc_sta_cnt); unassoc_sta_arr = rtw_zvmalloc(mlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info *)); if (!unassoc_sta_arr) return; - enter_critical_bh(&queue->lock); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); - while (rtw_end_of_queue_search(head, list) == _FALSE) { unassoc_sta = LIST_CONTAINOR(list, struct unassoc_sta_info, list); list = get_next(list); - unassoc_sta_arr[unassoc_sta_cnt++] = unassoc_sta; } - exit_critical_bh(&queue->lock); - + _rtw_spinunlock_bh(&queue->lock); RTW_PRINT_SEL(sel, " %17s %18s %6s\n", "mac_addr", "measure_delta_time", "rssi"); for (i = 0; i < unassoc_sta_cnt; i++) { @@ -1312,12 +1001,11 @@ void dump_unassoc_sta(void *sel, _adapter *adapter) u32 measure_delta_time; unassoc_sta = unassoc_sta_arr[i]; - measure_delta_time = rtw_systime_to_ms(rtw_get_current_time() - unassoc_sta->time); - RTW_PRINT_SEL(sel, "%c "MAC_FMT" %18u %6d\n" - , unassoc_sta->interested ? '*' : ' ' - , MAC_ARG(unassoc_sta->addr), measure_delta_time, unassoc_sta->recv_signal_power); + , unassoc_sta->interested ? '*' : ' ' + , MAC_ARG(unassoc_sta->addr), measure_delta_time, + unassoc_sta->recv_signal_power); } rtw_vmfree(unassoc_sta_arr, mlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info *)); @@ -1325,20 +1013,20 @@ void dump_unassoc_sta(void *sel, _adapter *adapter) static void del_unassoc_sta(struct mlme_priv *mlmepriv, struct unassoc_sta_info *unassoc_sta) { - _irqL irqL; _queue *free_queue = &(mlmepriv->free_unassoc_sta_queue); if (unassoc_sta->interested) mlmepriv->interested_unassoc_sta_cnt--; + if (mlmepriv->interested_unassoc_sta_cnt == 0) { rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv) - , ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv)); + , ((void *)(rtw_map_config_monitor_act_non)), mlme_to_adapter(mlmepriv)); } - _enter_critical_bh(&free_queue->lock, &irqL); + _rtw_spinlock_bh(&free_queue->lock); rtw_list_delete(&(unassoc_sta->list)); rtw_list_insert_tail(&(unassoc_sta->list), &(free_queue->queue)); - _exit_critical_bh(&free_queue->lock, &irqL); + _rtw_spinunlock_bh(&free_queue->lock); } static u8 del_unassoc_sta_chk(struct mlme_priv *mlmepriv, struct unassoc_sta_info *unassoc_sta) @@ -1357,39 +1045,31 @@ static u8 del_unassoc_sta_chk(struct mlme_priv *mlmepriv, struct unassoc_sta_inf return UNASOC_STA_DEL_CHK_ALIVE; del_unassoc_sta(mlmepriv, unassoc_sta); - return UNASOC_STA_DEL_CHK_DELETED; } static struct unassoc_sta_info *alloc_unassoc_sta(struct mlme_priv *mlmepriv) { - _irqL irqL; struct unassoc_sta_info *unassoc_sta; _queue *free_queue = &mlmepriv->free_unassoc_sta_queue; _list *list = NULL; - - _enter_critical_bh(&free_queue->lock, &irqL); - + _rtw_spinlock_bh(&free_queue->lock); if (_rtw_queue_empty(free_queue) == _TRUE) { unassoc_sta = NULL; goto exit; } - list = get_next(&(free_queue->queue)); + list = get_next(&(free_queue->queue)); unassoc_sta = LIST_CONTAINOR(list, struct unassoc_sta_info, list); - rtw_list_delete(&unassoc_sta->list); - _rtw_memset(unassoc_sta->addr, 0, ETH_ALEN); unassoc_sta->recv_signal_power = 0; unassoc_sta->time = 0; unassoc_sta->interested = 0; exit: - _exit_critical_bh(&free_queue->lock, &irqL); - + _rtw_spinunlock_bh(&free_queue->lock); return unassoc_sta; - } void rtw_del_unassoc_sta_queue(_adapter *adapter) @@ -1397,26 +1077,22 @@ void rtw_del_unassoc_sta_queue(_adapter *adapter) struct unassoc_sta_info *unassoc_sta; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); - while ((rtw_end_of_queue_search(head, list)) == _FALSE) { unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list); list = get_next(list); - del_unassoc_sta(mlmepriv, unassoc_sta); } - _exit_critical_bh(&queue->lock, &irqL); - + _rtw_spinunlock_bh(&queue->lock); } void rtw_del_unassoc_sta(_adapter *adapter, u8 *addr) @@ -1424,14 +1100,14 @@ void rtw_del_unassoc_sta(_adapter *adapter, u8 *addr) struct unassoc_sta_info *unassoc_sta; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); + head = get_list_head(queue); list = get_next(head); @@ -1446,7 +1122,7 @@ void rtw_del_unassoc_sta(_adapter *adapter, u8 *addr) } unlock_unassoc_sta_queue: - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); } void rtw_rx_add_unassoc_sta(_adapter *adapter, u8 stype, u8 *addr, s8 recv_signal_power) @@ -1455,25 +1131,22 @@ void rtw_rx_add_unassoc_sta(_adapter *adapter, u8 stype, u8 *addr, s8 recv_signa struct unassoc_sta_info *oldest_unassoc_sta = NULL; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); - while ((rtw_end_of_queue_search(head, list)) == _FALSE) { unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list); list = get_next(list); - if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) { - if (unassoc_sta->interested - || mlmepriv->unassoc_sta_mode_of_stype[stype] >= UNASOC_STA_MODE_ALL - ) { + if (unassoc_sta->interested || + mlmepriv->unassoc_sta_mode_of_stype[stype] >= + UNASOC_STA_MODE_ALL) { unassoc_sta->recv_signal_power = recv_signal_power; unassoc_sta->time = rtw_get_current_time(); goto unlock_unassoc_sta_queue; @@ -1499,13 +1172,14 @@ void rtw_rx_add_unassoc_sta(_adapter *adapter, u8 stype, u8 *addr, s8 recv_signa } else goto unlock_unassoc_sta_queue; } + _rtw_memcpy(unassoc_sta->addr, addr, ETH_ALEN); unassoc_sta->recv_signal_power = recv_signal_power; unassoc_sta->time = rtw_get_current_time(); rtw_list_insert_tail(&(unassoc_sta->list), &(queue->queue)); unlock_unassoc_sta_queue: - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); } void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr) @@ -1514,14 +1188,14 @@ void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr) struct unassoc_sta_info *oldest_unassoc_sta = NULL; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); + head = get_list_head(queue); list = get_next(head); @@ -1535,7 +1209,7 @@ void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr) mlmepriv->interested_unassoc_sta_cnt++; if (mlmepriv->interested_unassoc_sta_cnt == 1) { rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv) - , ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv)); + , ((void *)(rtw_map_config_monitor_act_non)), mlme_to_adapter(mlmepriv)); } } goto unlock_unassoc_sta_queue; @@ -1558,6 +1232,7 @@ void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr) } else goto unlock_unassoc_sta_queue; } + _rtw_memcpy(unassoc_sta->addr, addr, ETH_ALEN); unassoc_sta->interested = 1; unassoc_sta->recv_signal_power = 0; @@ -1566,11 +1241,11 @@ void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr) mlmepriv->interested_unassoc_sta_cnt++; if (mlmepriv->interested_unassoc_sta_cnt == 1) { rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv) - , ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv)); + , ((void *)(rtw_map_config_monitor_act_non)), mlme_to_adapter(mlmepriv)); } unlock_unassoc_sta_queue: - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); } void rtw_undo_interested_unassoc_sta(_adapter *adapter, u8 *addr) @@ -1578,14 +1253,13 @@ void rtw_undo_interested_unassoc_sta(_adapter *adapter, u8 *addr) struct unassoc_sta_info *unassoc_sta; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); @@ -1599,14 +1273,15 @@ void rtw_undo_interested_unassoc_sta(_adapter *adapter, u8 *addr) mlmepriv->interested_unassoc_sta_cnt--; if (mlmepriv->interested_unassoc_sta_cnt == 0) { rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv) - , ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv)); + , ((void *)(rtw_map_config_monitor_act_non)), mlme_to_adapter(mlmepriv)); } } + goto unlock_unassoc_sta_queue; } } unlock_unassoc_sta_queue: - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); } void rtw_undo_all_interested_unassoc_sta(_adapter *adapter) @@ -1614,14 +1289,13 @@ void rtw_undo_all_interested_unassoc_sta(_adapter *adapter) struct unassoc_sta_info *unassoc_sta; struct mlme_priv *mlmepriv; _queue *queue; - _irqL irqL; _list *head, *list; adapter = GET_PRIMARY_ADAPTER(adapter); mlmepriv = &(adapter->mlmepriv); queue = &(mlmepriv->unassoc_sta_queue); - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); head = get_list_head(queue); list = get_next(head); @@ -1634,46 +1308,15 @@ void rtw_undo_all_interested_unassoc_sta(_adapter *adapter) mlmepriv->interested_unassoc_sta_cnt--; if (mlmepriv->interested_unassoc_sta_cnt == 0) { rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv) - , ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv)); + , ((void *)(rtw_map_config_monitor_act_non)), mlme_to_adapter(mlmepriv)); goto unlock_unassoc_sta_queue; } } } unlock_unassoc_sta_queue: - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); } -u8 rtw_search_unassoc_sta(_adapter *adapter, u8 *addr, struct unassoc_sta_info *ret_sta) -{ - struct unassoc_sta_info *unassoc_sta = NULL; - struct mlme_priv *mlmepriv; - _queue *queue; - _irqL irqL; - _list *head, *list; - u8 searched = 0; - - adapter = GET_PRIMARY_ADAPTER(adapter); - mlmepriv = &(adapter->mlmepriv); - queue = &(mlmepriv->unassoc_sta_queue); - - _enter_critical_bh(&queue->lock, &irqL); - head = get_list_head(queue); - list = get_next(head); - - while ((rtw_end_of_queue_search(head, list)) == _FALSE) { - unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list); - list = get_next(list); - - if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) { - memcpy(ret_sta, unassoc_sta, sizeof(struct unassoc_sta_info)); - searched = 1; - break; - } - } - _exit_critical_bh(&queue->lock, &irqL); - - return searched; -} #endif /* CONFIG_RTW_MULTI_AP */ /* select the desired network based on the capability of the (i)bss. @@ -1682,7 +1325,6 @@ u8 rtw_search_unassoc_sta(_adapter *adapter, u8 *addr, struct unassoc_sta_info * * (3) WMM * (4) HT * (5) others */ -int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) { struct security_priv *psecuritypriv = &adapter->securitypriv; @@ -1739,700 +1381,52 @@ int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) return bselected; } -#ifdef CONFIG_80211D -static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) +static void free_scanqueue(struct mlme_priv *pmlmepriv) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - struct registry_priv *pregistrypriv; - struct mlme_ext_priv *pmlmeext; - RT_CHANNEL_INFO *chplan_new; - u8 channel; - u8 i; - - - pregistrypriv = &padapter->registrypriv; - pmlmeext = &padapter->mlmeextpriv; - - /* Adjust channel plan by AP Country IE */ - if (pregistrypriv->enable80211d - && (!pmlmeext->update_channel_plan_by_ap_done)) { - u8 *ie, *p; - u32 len; - RT_CHANNEL_PLAN chplan_ap; - RT_CHANNEL_INFO *chplan_sta = NULL; - u8 country[4]; - u8 fcn; /* first channel number */ - u8 noc; /* number of channel */ - u8 j, k; - - ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (!ie) - return; - if (len < 6) - return; - - ie += 2; - p = ie; - ie += len; - - _rtw_memset(country, 0, 4); - _rtw_memcpy(country, p, 3); - p += 3; - RTW_INFO("%s: 802.11d country=%s\n", __FUNCTION__, country); - - i = 0; - while ((ie - p) >= 3) { - fcn = *(p++); - noc = *(p++); - p++; - - for (j = 0; j < noc; j++) { - if (fcn <= 14) - channel = fcn + j; /* 2.4 GHz */ - else - channel = fcn + j * 4; /* 5 GHz */ - - chplan_ap.Channel[i++] = channel; - } - } - chplan_ap.Len = i; + _queue *free_queue = &pmlmepriv->free_bss_pool; + _queue *scan_queue = &pmlmepriv->scanned_queue; + _list *plist, *phead, *ptemp; -#ifdef CONFIG_RTW_DEBUG - i = 0; - RTW_INFO("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid); - while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) { - _RTW_INFO("%02d,", chplan_ap.Channel[i]); - i++; - } - _RTW_INFO("}\n"); -#endif - chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); - if (!chplan_sta) - goto done_update_chplan_from_ap; + _rtw_spinlock_bh(&scan_queue->lock); + _rtw_spinlock_bh(&free_queue->lock); - _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); -#ifdef CONFIG_RTW_DEBUG - i = 0; - RTW_INFO("%s: STA channel plan {", __FUNCTION__); - while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { - _RTW_INFO("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].flags & RTW_CHF_NO_IR ? 'p' : 'a'); - i++; - } - _RTW_INFO("}\n"); -#endif + phead = get_list_head(scan_queue); + plist = get_next(phead); - _rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set)); - chplan_new = rfctl->channel_set; + while (plist != phead) { + ptemp = get_next(plist); + rtw_list_delete(plist); + rtw_list_insert_tail(plist, &free_queue->queue); + plist = ptemp; + pmlmepriv->num_of_scanned--; + } - i = j = k = 0; - if (pregistrypriv->wireless_mode & WIRELESS_11G) { - do { - if ((i == MAX_CHANNEL_NUM) - || (chplan_sta[i].ChannelNum == 0) - || (chplan_sta[i].ChannelNum > 14)) - break; + _rtw_spinunlock_bh(&free_queue->lock); + _rtw_spinunlock_bh(&scan_queue->lock); - if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14)) - break; - - if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - i++; - j++; - k++; - } else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; -#if 0 - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; -#else - chplan_new[k].flags |= RTW_CHF_NO_IR; -#endif - i++; - k++; - } else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - j++; - k++; - } - } while (1); - - /* change AP not support channel to Passive scan */ - while ((i < MAX_CHANNEL_NUM) - && (chplan_sta[i].ChannelNum != 0) - && (chplan_sta[i].ChannelNum <= 14)) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; -#if 0 - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; -#else - chplan_new[k].flags |= RTW_CHF_NO_IR; -#endif - i++; - k++; - } - - /* add channel AP supported */ - while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - j++; - k++; - } - } else { - /* keep original STA 2.4G channel plan */ - while ((i < MAX_CHANNEL_NUM) - && (chplan_sta[i].ChannelNum != 0) - && (chplan_sta[i].ChannelNum <= 14)) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; - i++; - k++; - } - - /* skip AP 2.4G channel plan */ - while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) - j++; - } - - if (pregistrypriv->wireless_mode & WIRELESS_11A) { - do { - if ((i >= MAX_CHANNEL_NUM) - || (chplan_sta[i].ChannelNum == 0)) - break; - - if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0)) - break; - - if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - i++; - j++; - k++; - } else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; -#if 0 - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; -#else - chplan_new[k].flags |= RTW_CHF_NO_IR; -#endif - i++; - k++; - } else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - j++; - k++; - } - } while (1); - - /* change AP not support channel to Passive scan */ - while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; -#if 0 - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; -#else - chplan_new[k].flags |= RTW_CHF_NO_IR; -#endif - i++; - k++; - } - - /* add channel AP supported */ - while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) { - chplan_new[k].ChannelNum = chplan_ap.Channel[j]; - j++; - k++; - } - } else { - /* keep original STA 5G channel plan */ - while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { - chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; - if (chplan_sta[i].flags & RTW_CHF_NO_IR) - chplan_new[k].flags |= RTW_CHF_NO_IR; - i++; - k++; - } - } - - pmlmeext->update_channel_plan_by_ap_done = 1; - rtw_nlrtw_reg_change_event(padapter); - -#ifdef CONFIG_RTW_DEBUG - k = 0; - RTW_INFO("%s: new STA channel plan {", __FUNCTION__); - while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) { - _RTW_INFO("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].flags & RTW_CHF_NO_IR ? 'p' : 'c'); - k++; - } - _RTW_INFO("}\n"); -#endif - -#if 0 - /* recover the right channel index */ - channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; - k = 0; - while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) { - if (chplan_new[k].ChannelNum == channel) { - RTW_INFO("%s: change mlme_ext sitesurvey channel index from %d to %d\n", - __FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k); - pmlmeext->sitesurvey_res.channel_idx = k; - break; - } - k++; - } -#endif - -done_update_chplan_from_ap: - if (chplan_sta) - rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); - } -} -#endif - -void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) -{ - _irqL irqL; - u32 len; - u8 val8; - WLAN_BSSID_EX *pnetwork; - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - - pnetwork = (WLAN_BSSID_EX *)pbuf; - - len = get_WLAN_BSSID_EX_sz(pnetwork); - if (len > (sizeof(WLAN_BSSID_EX))) { - return; - } - -#ifdef CONFIG_RTW_80211K - val8 = 0; - rtw_hal_get_hwreg(adapter, HW_VAR_FREECNT, &val8); - - /* use TSF if no free run counter */ - if (val8==0) - pnetwork->PhyInfo.free_cnt = (u32)rtw_hal_get_tsftr_by_port( - adapter, rtw_hal_get_port(adapter)); -#endif - - if (pnetwork->InfrastructureMode == Ndis802_11Infrastructure) { - #ifdef CONFIG_80211D - process_80211d(adapter, pnetwork); - #endif - if (MLME_IS_SCAN(adapter)) { - adapter->mlmeextpriv.sitesurvey_res.activate_ch_cnt - += rtw_process_beacon_hint(adapter, pnetwork); - } - } - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - - /* update IBSS_network 's timestamp */ - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) { - if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) { - struct wlan_network *ibss_wlan = NULL; - _irqL irqL; - - _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); - if (ibss_wlan) { - _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - goto exit; - } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - } - } - - /* lock pmlmepriv->lock when you accessing network_q */ - if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _FALSE) { - if (pnetwork->Ssid.Ssid[0] == 0) - pnetwork->Ssid.SsidLength = 0; - rtw_add_network(adapter, pnetwork); - } - -exit: - - _exit_critical_bh(&pmlmepriv->lock, &irqL); - - - return; -} - -void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) -{ - _irqL irqL; - struct surveydone_event *parm = (struct surveydone_event *)pbuf; - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - -#ifdef CONFIG_MLME_EXT - mlmeext_surveydone_event_callback(adapter); -#endif - - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - if (pmlmepriv->wps_probe_req_ie) { - u32 free_len = pmlmepriv->wps_probe_req_ie_len; - pmlmepriv->wps_probe_req_ie_len = 0; - rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); - pmlmepriv->wps_probe_req_ie = NULL; - } - - - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); - /* rtw_warn_on(1); */ - } - - if (pmlmeext->scan_abort == _TRUE) - pmlmeext->scan_abort = _FALSE; - - _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - - _cancel_timer_ex(&pmlmepriv->scan_to_timer); - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_set_signal_stat_timer(&adapter->recvpriv); -#endif - - if (pmlmepriv->to_join == _TRUE) { - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) { - set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); - - if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS) - _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); - #ifdef CONFIG_AP_MODE - else { - WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); - u8 *pibss = adapter->registrypriv.dev_network.MacAddress; - - /* pmlmepriv->fw_state ^= WIFI_UNDER_SURVEY; */ /* because don't set assoc_timer */ - _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); - - - _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); - _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); - - rtw_update_registrypriv_dev_network(adapter); - rtw_generate_random_ibss(pibss); - - /*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/ - init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); - - if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) - RTW_ERR("rtw_create_ibss_cmd FAIL\n"); - - pmlmepriv->to_join = _FALSE; - } - #endif /* CONFIG_AP_MODE */ - } - } else { - int s_ret; - set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); - pmlmepriv->to_join = _FALSE; - s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); - if (_SUCCESS == s_ret) - _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); - else if (s_ret == 2) { /* there is no need to wait for join */ - _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); - rtw_indicate_connect(adapter); - } else { - RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); - - if (rtw_to_roam(adapter) != 0) { - struct sitesurvey_parm scan_parm; - u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE); - - rtw_init_sitesurvey_parm(adapter, &scan_parm); - _rtw_memcpy(&scan_parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); - scan_parm.ssid_num = 1; - - if (rtw_dec_to_roam(adapter) == 0 - || (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC) - || _SUCCESS != rtw_sitesurvey_cmd(adapter, &scan_parm) - ) { - rtw_set_to_roam(adapter, 0); - rtw_free_assoc_resources(adapter, _TRUE); - rtw_indicate_disconnect(adapter, 0, _FALSE); - } else - pmlmepriv->to_join = _TRUE; - } else - rtw_indicate_disconnect(adapter, 0, _FALSE); - _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); - } - } - } else { - if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE) - #if (defined(CONFIG_RTW_WNM) && defined(CONFIG_RTW_80211R)) - || rtw_wnm_btm_roam_triggered(adapter) - #endif - ) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { - if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { - #ifdef CONFIG_RTW_80211R - rtw_ft_start_roam(adapter, - (u8 *)pmlmepriv->roam_network->network.MacAddress); - #else - receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress - , WLAN_REASON_ACTIVE_ROAM, _FALSE); - #endif - } - } - } - } - - /* RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */ - - _exit_critical_bh(&pmlmepriv->lock, &irqL); - -#ifdef CONFIG_P2P_PS - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); -#endif /* CONFIG_P2P_PS */ - - rtw_mi_os_xmit_schedule(adapter); - -#ifdef CONFIG_DRVEXT_MODULE_WSC - drvext_surveydone_callback(&adapter->drvextpriv); -#endif - -#ifdef DBG_CONFIG_ERROR_DETECT - { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - if (pmlmeext->sitesurvey_res.bss_cnt == 0) { - /* rtw_hal_sreset_reset(adapter); */ - } - } -#endif - -#ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_surveydone_event_callback(adapter); -#endif /* CONFIG_IOCTL_CFG80211 */ - - rtw_indicate_scan_done(adapter, _FALSE); - -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) - rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE); -#endif - - if (parm->activate_ch_cnt) { - op_class_pref_apply_regulatory(adapter, REG_BEACON_HINT); - rtw_nlrtw_reg_beacon_hint_event(adapter); - } - -#ifdef CONFIG_RTW_MESH - #if CONFIG_RTW_MESH_OFFCH_CAND - if (rtw_mesh_offch_candidate_accepted(adapter)) { - u8 ch; - - ch = rtw_mesh_select_operating_ch(adapter); - if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) { - u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter); - - if (ifbmp) { - /* switch to selected channel */ - rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE); - issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0); - } else - rtw_warn_on(1); - } - } - #endif -#endif /* CONFIG_RTW_MESH */ - -#ifdef CONFIG_RTW_ACS - if (parm->acs) { - u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter); - - if (ifbmp) - rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, REQ_CH_INT_INFO, REQ_BW_ORI, REQ_OFFSET_NONE); - } -#endif -} - -u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval) -{ - u8 ss_condition = SS_ALLOW; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct registry_priv *registry_par = &adapter->registrypriv; - - -#ifdef CONFIG_MP_INCLUDED - if (rtw_mp_mode_check(adapter)) { - RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_MP_MODE; - goto _exit; - } -#endif - -#ifdef DBG_LA_MODE - if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) { - RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_LA_MODE; - goto _exit; - } -#endif - -#ifdef CONFIG_RTW_REPEATER_SON - if (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { - RTW_INFO("%s ("ADPT_FMT") blocking scan for under rson scanning process\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_RSON_SCANING; - goto _exit; - } -#endif -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(adapter)->block_scan == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BLOCK_SCAN; - goto _exit; - } -#endif - - if (adapter_to_dvobj(adapter)->scan_deny == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") tpt mode, scan deny!\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BLOCK_SCAN; - goto _exit; - } - - if (rtw_is_scan_deny(adapter)) { - RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BY_DRV; - goto _exit; - } - -#ifdef CONFIG_ADAPTIVITY_DENY_SCAN - if (registry_par->adaptivity_en - && rtw_phydm_get_edcca_flag(adapter) - && rtw_is_2g_ch(GET_HAL_DATA(adapter)->current_channel)) { - RTW_WARN(FUNC_ADPT_FMT": Adaptivity block scan! (ch=%u)\n", - FUNC_ADPT_ARG(adapter), - GET_HAL_DATA(adapter)->current_channel); - ss_condition = SS_DENY_ADAPTIVITY; - goto _exit; - } -#endif /* CONFIG_ADAPTIVITY_DENY_SCAN */ - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){ - if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_SELF_AP_UNDER_WPS; - goto _exit; - } else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n", - caller, ADPT_ARG(adapter), pmlmepriv->fw_state); - ss_condition = SS_DENY_SELF_AP_UNDER_LINKING; - goto _exit; - } else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n", - caller, ADPT_ARG(adapter), pmlmepriv->fw_state); - ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY; - goto _exit; - } - } else { - if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n", - caller, ADPT_ARG(adapter), pmlmepriv->fw_state); - ss_condition = SS_DENY_SELF_STA_UNDER_LINKING; - goto _exit; - } else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n", - caller, ADPT_ARG(adapter), pmlmepriv->fw_state); - ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY; - goto _exit; - } - } - -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS; - goto _exit; - - } else if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY)) { - RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BUDDY_UNDER_SURVEY; - goto _exit; - } -#endif /* CONFIG_CONCURRENT_MODE */ - -#ifdef RTW_BUSY_DENY_SCAN - /* - * busy traffic check - * Rules: - * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow - * scan, otherwise goto rule 2. - * 2. Deny scan if any interface is busy, otherwise allow scan. - */ - if (pmlmepriv->lastscantime - && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) > - registry_par->scan_interval_thr) - && rtw_mi_busy_traffic_check(adapter)) { - RTW_WARN("%s ("ADPT_FMT") : scan abort!! BusyTraffic\n", - caller, ADPT_ARG(adapter)); - ss_condition = SS_DENY_BUSY_TRAFFIC; - goto _exit; - } -#endif /* RTW_BUSY_DENY_SCAN */ - -_exit: - return ss_condition; -} - -static void free_scanqueue(struct mlme_priv *pmlmepriv) -{ - _irqL irqL, irqL0; - _queue *free_queue = &pmlmepriv->free_bss_pool; - _queue *scan_queue = &pmlmepriv->scanned_queue; - _list *plist, *phead, *ptemp; - - - _enter_critical_bh(&scan_queue->lock, &irqL0); - _enter_critical_bh(&free_queue->lock, &irqL); - - phead = get_list_head(scan_queue); - plist = get_next(phead); - - while (plist != phead) { - ptemp = get_next(plist); - rtw_list_delete(plist); - rtw_list_insert_tail(plist, &free_queue->queue); - plist = ptemp; - pmlmepriv->num_of_scanned--; - } - - _exit_critical_bh(&free_queue->lock, &irqL); - _exit_critical_bh(&scan_queue->lock, &irqL0); - -} +} void rtw_reset_rx_info(_adapter *adapter) { - struct recv_priv *precvpriv = &adapter->recvpriv; + struct recv_info *precvinfo = &adapter->recvinfo; - precvpriv->dbg_rx_ampdu_drop_count = 0; - precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; - precvpriv->dbg_rx_ampdu_loss_count = 0; - precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; - precvpriv->dbg_rx_drop_count = 0; - precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; + precvinfo->dbg_rx_ampdu_drop_count = 0; + precvinfo->dbg_rx_ampdu_forced_indicate_count = 0; + precvinfo->dbg_rx_ampdu_loss_count = 0; + precvinfo->dbg_rx_dup_mgt_frame_drop_count = 0; + precvinfo->dbg_rx_ampdu_window_shift_cnt = 0; + precvinfo->dbg_rx_drop_count = 0; + precvinfo->dbg_rx_conflic_mac_addr_cnt = 0; } /* -*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock -*/ + * Note: There may be I/O in following functions: + * rtw_free_stainfo() + * rtw_init_self_stainfo() + */ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) { - _irqL irqL; struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct wlan_network *tgt_network = &pmlmepriv->cur_network; @@ -2446,10 +1440,16 @@ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + if (MLME_IS_STA(adapter)) { struct sta_info *psta; psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); + if (!psta) { + RTW_WARN("[TODO]" FUNC_ADPT_FMT ": fail to find stainfo" + "(" MAC_FMT ")\n", + FUNC_ADPT_ARG(adapter), + MAC_ARG(tgt_network->network.MacAddress)); + } #ifdef CONFIG_TDLS rtw_free_all_tdls_sta(adapter, _TRUE); @@ -2459,9 +1459,10 @@ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR); #endif /* CONFIG_TDLS */ - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ rtw_free_stainfo(adapter, psta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_init_self_stainfo(adapter); + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ } @@ -2469,17 +1470,10 @@ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) struct sta_info *psta; rtw_free_all_stainfo(adapter); - - psta = rtw_get_bcmc_stainfo(adapter); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(adapter, psta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - - rtw_init_bcmc_stainfo(adapter); } if (lock_scanned_queue) - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){ RTW_INFO("Dont free disconnecting network of scanned_queue due to uner %s %s phase\n\n", @@ -2493,7 +1487,8 @@ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) RTW_INFO("Free disconnecting network of scanned_queue\n"); rtw_free_network_nolock(adapter, pwlan); #ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + if (rtw_p2p_chk_role(&adapter->wdinfo, P2P_ROLE_CLIENT) || + rtw_p2p_chk_role(&adapter->wdinfo, P2P_ROLE_GO)) { rtw_set_scan_deny(adapter, 2000); /* rtw_clear_scan_deny(adapter); */ } @@ -2503,13 +1498,13 @@ void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) } if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1)) - /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) { + /*||MLME_IS_STA(adapter)*/) { if (pwlan) rtw_free_network_nolock(adapter, pwlan); } if (lock_scanned_queue) - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); adapter->securitypriv.key_mask = 0; @@ -2558,10 +1553,6 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); -#ifdef CONFIG_WAPI_SUPPORT - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; -#endif u8 *wps_ie = NULL; uint wpsie_len = 0; @@ -2573,6 +1564,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate /* force to clear cur_network_scanned's SELECTED REGISTRAR */ if (pmlmepriv->cur_network_scanned) { WLAN_BSSID_EX *current_joined_bss = &(pmlmepriv->cur_network_scanned->network); + if (current_joined_bss) { wps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_, current_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len); @@ -2592,9 +1584,8 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate _clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE); #ifdef CONFIG_WAPI_SUPPORT - psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr); + if (MLME_IS_STA(padapter)) + rtw_wapi_return_one_sta_info(padapter, NULL); else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) rtw_wapi_return_all_sta_info(padapter); @@ -2617,6 +1608,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate rtw_tx_control_cmd(padapter); } #endif + /* rtw_phl_chanctx_del(adapter_to_dvobj(padapter)->phl, padapter->phl_role, NULL); */ rtw_os_indicate_disconnect(padapter, reason, locally_generated); @@ -2637,16 +1629,11 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate #ifdef CONFIG_LPS rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0); #endif - -#ifdef CONFIG_BEAMFORMING - beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1); -#endif /*CONFIG_BEAMFORMING*/ - } inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) { - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO(FUNC_ADPT_FMT" aborted=%d\n", FUNC_ADPT_ARG(padapter), aborted); rtw_os_indicate_scan_done(padapter, aborted); @@ -2659,7 +1646,9 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) pwrpriv = adapter_to_pwrctl(padapter); rtw_set_ips_deny(padapter, 0); #ifdef CONFIG_IPS_CHECK_IN_WD + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1); + #endif #else /* !CONFIG_IPS_CHECK_IN_WD */ _rtw_set_pwr_state_check_timer(pwrpriv, 1); #endif /* !CONFIG_IPS_CHECK_IN_WD */ @@ -2667,7 +1656,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) #endif /* CONFIG_IPS */ } -static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) +static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms) { systime start; u32 pass_ms; @@ -2676,155 +1665,90 @@ static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) start = rtw_get_current_time(); - pmlmeext->scan_abort = abort; - - while (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) - && rtw_get_passing_time_ms(start) <= timeout_ms) { + pmlmeext->join_abort = abort; + if (abort) + set_link_timer(pmlmeext, 1); - if (RTW_CANNOT_RUN(adapter)) + while (rtw_get_passing_time_ms(start) <= timeout_ms + && (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) + ) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) break; - RTW_INFO(FUNC_NDEV_FMT"fw_state=WIFI_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev)); + RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter)); rtw_msleep_os(20); } - if (_TRUE == abort) { - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) { - if (!RTW_CANNOT_RUN(adapter)) - RTW_INFO(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev)); -#ifdef CONFIG_PLATFORM_MSTAR - /*_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);*/ - set_survey_timer(pmlmeext, 0); - mlme_set_scan_to_timer(pmlmepriv, 50); -#endif - rtw_indicate_scan_done(adapter, _TRUE); + if (abort) { + if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) { + if (!RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) + RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter)); } } - pmlmeext->scan_abort = _FALSE; + pmlmeext->join_abort = 0; pass_ms = rtw_get_passing_time_ms(start); return pass_ms; - -} - -void rtw_scan_wait_completed(_adapter *adapter) -{ - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; - - _rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms); } -u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms) +u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms) { - return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms); + return _rtw_wait_join_done(adapter, _TRUE, timeout_ms); } -void rtw_scan_abort_no_wait(_adapter *adapter) -{ - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); - - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) - pmlmeext->scan_abort = _TRUE; -} - -void rtw_scan_abort(_adapter *adapter) -{ - rtw_scan_abort_timeout(adapter, 200); -} - -static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms) -{ - systime start; - u32 pass_ms; - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); - - start = rtw_get_current_time(); - - pmlmeext->join_abort = abort; - if (abort) - set_link_timer(pmlmeext, 1); - - while (rtw_get_passing_time_ms(start) <= timeout_ms - && (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) - #ifdef CONFIG_IOCTL_CFG80211 - || rtw_cfg80211_is_connect_requested(adapter) - #endif - ) - ) { - if (RTW_CANNOT_RUN(adapter)) - break; - - RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter)); - rtw_msleep_os(20); - } - - if (abort) { - if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) - #ifdef CONFIG_IOCTL_CFG80211 - || rtw_cfg80211_is_connect_requested(adapter) - #endif - ) { - if (!RTW_CANNOT_RUN(adapter)) - RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter)); - } - } - - pmlmeext->join_abort = 0; - pass_ms = rtw_get_passing_time_ms(start); - - return pass_ms; -} - -u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms) -{ - return _rtw_wait_join_done(adapter, _TRUE, timeout_ms); -} - -static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) +static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) { int i; struct sta_info *psta = NULL; struct recv_reorder_ctrl *preorder_ctrl; struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#if defined(CONFIG_RTW_MULTI_AP) || defined(CONFIG_RTS_FULL_BW) + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#endif #ifdef CONFIG_RTS_FULL_BW - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct wlan_network *cur_network = &(pmlmepriv->cur_network); #endif/*CONFIG_RTS_FULL_BW*/ psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress); - if (psta == NULL) + if (psta == NULL) { + RTW_ERR("%s: can not find "MAC_FMT"\n", __func__, MAC_ARG(pnetwork->network.MacAddress)); psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress); + } if (psta) { /* update ptarget_sta */ RTW_INFO("%s\n", __FUNCTION__); - psta->cmn.aid = pnetwork->join_res; + /* assign aid */ + psta->phl_sta->aid = pnetwork->join_res; update_sta_info(padapter, psta); /* update station supportRate */ psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates); _rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen); - rtw_hal_update_sta_ra_info(padapter, psta); + update_sta_ra_info(padapter, psta); - psta->wireless_mode = pmlmeext->cur_wireless_mode; - rtw_hal_update_sta_wset(padapter, psta); + psta->phl_sta->wmode = pmlmeext->cur_wireless_mode; - /* sta mode */ - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* security related */ #ifdef CONFIG_RTW_80211R if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) - && (psta->ft_pairwise_key_installed == _FALSE)) { + && (psta->ft_pairwise_key_installed == _FALSE)) #else - if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { + if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) #endif + { u8 *ie; sint ie_len; u8 mfp_opt = MFP_NO; @@ -2842,7 +1766,6 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL) psta->flags |= WLAN_STA_MFP; } - if (padapter->securitypriv.dot11PrivacyAlgrthm != _NO_PRIVACY_ ) { /*check if amsdu is allowed */ if (rtw_check_amsdu_disable(padapter->registrypriv.amsdu_mode, spp_opt) == _TRUE) @@ -2869,7 +1792,6 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ /* todo: check if AP can send A-MPDU packets */ for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ preorder_ctrl = &psta->recvreorder_ctrl[i]; preorder_ctrl->enable = _FALSE; preorder_ctrl->indicate_seq = 0xffff; @@ -2882,29 +1804,30 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl ,preorder_ctrl->rec_abba_rsp_ack ); #endif - preorder_ctrl->wend_b = 0xffff; +#ifdef CONFIG_RECV_REORDERING_CTRL preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ +#endif preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; } - } -#ifdef CONFIG_RTW_80211K - _rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5); -#endif -#ifdef CONFIG_RTW_MULTI_AP - if (padapter->multi_ap & MULTI_AP_BACKHAUL_STA) { - u8 multi_ap = rtw_get_multi_ap_ie_ext(pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 - , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6); - - if (multi_ap & MULTI_AP_BACKHAUL_BSS) /* backhaul bss, enable WDS */ - psta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS; - else if (multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */ - psta->flags |= WLAN_STA_MULTI_AP; + #ifdef CONFIG_RTW_80211K + _rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5); + #endif + #ifdef CONFIG_RTW_MULTI_AP + if (padapter->multi_ap & MULTI_AP_BACKHAUL_STA) { + u8 multi_ap = rtw_get_multi_ap_ie_ext(pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6); + + if (multi_ap & MULTI_AP_BACKHAUL_BSS) /* backhaul bss, enable WDS */ + psta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS; + else if (multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */ + psta->flags |= WLAN_STA_MULTI_AP; + } + #endif + #ifdef CONFIG_RTS_FULL_BW + rtw_parse_sta_vendor_ie_8812(padapter, psta, BSS_EX_TLV_IES(&cur_network->network), BSS_EX_TLV_IES_LEN(&cur_network->network)); + #endif } -#endif -#ifdef CONFIG_RTS_FULL_BW - rtw_parse_sta_vendor_ie_8812(padapter, psta, BSS_EX_TLV_IES(&cur_network->network), BSS_EX_TLV_IES_LEN(&cur_network->network)); -#endif return psta; } @@ -2927,28 +1850,27 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * _rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ); cur_network->aid = pnetwork->join_res; + #ifdef CONFIG_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvinfo); + #endif - -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_set_signal_stat_timer(&padapter->recvpriv); -#endif - padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; - padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; - /* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */ - padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); + /*RTW_WKARD_CORE_RSSI_V1 - GEORGIA MUST REFINE*/ + padapter->recvinfo.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; + padapter->recvinfo.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; + /* the ptarget_wlan->network.PhyInfo.rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */ + padapter->recvinfo.rssi = ptarget_wlan->network.PhyInfo.rssi; #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" "\n" , FUNC_ADPT_ARG(padapter) - , padapter->recvpriv.signal_strength - , padapter->recvpriv.rssi - , padapter->recvpriv.signal_qual + , padapter->recvinfo.signal_strength + , padapter->recvinfo.rssi + , padapter->recvinfo.signal_qual ); #endif -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_set_signal_stat_timer(&padapter->recvpriv); -#endif - + #ifdef CONFIG_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvinfo); + #endif /* update fw_state */ /* will clr WIFI_UNDER_LINKING here indirectly */ switch (pnetwork->network.InfrastructureMode) { @@ -2991,7 +1913,6 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * /* #define REJOIN */ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) { - _irqL irqL; static u8 retry = 0; struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL; struct sta_priv *pstapriv = &adapter->stapriv; @@ -3009,14 +1930,14 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) goto exit; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; if (pnetwork->join_res > 0) { - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); retry = 0; if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) { /* s1. find ptarget_wlan */ @@ -3030,13 +1951,13 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); if (pcur_sta) { - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ rtw_free_stainfo(adapter, pcur_sta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ } ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(adapter)) { if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; } @@ -3044,7 +1965,7 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) } else { ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(adapter)) { if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; } @@ -3055,17 +1976,17 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork); else { RTW_PRINT("Can't find ptarget_wlan when joinbss_event callback\n"); - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); goto ignore_joinbss_callback; } /* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(adapter)) { ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork); if (ptarget_sta == NULL) { RTW_ERR("Can't update stainfo when joinbss_event callback\n"); - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); goto ignore_joinbss_callback; } @@ -3081,20 +2002,22 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) } /* s5. Cancle assoc_timer */ - _cancel_timer_ex(&pmlmepriv->assoc_timer); + /*_cancel_timer_ex(&pmlmepriv->assoc_timer);*/ + cancel_assoc_timer(pmlmepriv); } else { - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); goto ignore_joinbss_callback; } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); } else if (pnetwork->join_res == -4) { rtw_reset_securitypriv(adapter); pmlmepriv->join_status = status; - _set_timer(&pmlmepriv->assoc_timer, 1); + /*_set_timer(&pmlmepriv->assoc_timer, 1);*/ + set_assoc_timer(pmlmepriv, 1); /* rtw_free_assoc_resources(adapter, _TRUE); */ @@ -3112,7 +2035,8 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) if (res == _SUCCESS) { /* extend time of assoc_timer */ - _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + /*_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);*/ + set_assoc_timer(pmlmepriv, MAX_JOIN_TIMEOUT); retry++; } else if (res == 2) { /* there is no need to wait for join */ _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); @@ -3120,7 +2044,8 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) } else { #endif pmlmepriv->join_status = status; - _set_timer(&pmlmepriv->assoc_timer, 1); + /*_set_timer(&pmlmepriv->assoc_timer, 1);*/ + set_assoc_timer(pmlmepriv, 1); /* rtw_free_assoc_resources(adapter, _TRUE); */ _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); @@ -3131,7 +2056,7 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) } ignore_joinbss_callback: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); exit: return; @@ -3139,17 +2064,17 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) { - struct wlan_network *pnetwork = (struct wlan_network *)pbuf; + struct wlan_network *pnetwork = (struct wlan_network *)pbuf; - mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); - + rtw_set_hw_after_join(adapter, pnetwork->join_res); rtw_mi_os_xmit_schedule(adapter); - } void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected) { +/* ToDo H2C */ +#if 0 struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; bool miracast_enabled = 0; bool miracast_sink = 0; @@ -3162,21 +2087,21 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn return; } - if (sta->cmn.mac_id >= macid_ctl->num) { + if (sta->phl_sta->macid >= macid_ctl->num) { RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" - , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); + , FUNC_ADPT_ARG(adapter), sta->phl_sta->macid); rtw_warn_on(1); return; } - if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) { + if (!rtw_macid_is_used(macid_ctl, sta->phl_sta->macid)) { RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n" - , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); + , FUNC_ADPT_ARG(adapter), sta->phl_sta->macid); connected = 0; rtw_warn_on(1); } - if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) { + if (connected && !rtw_macid_is_bmc(macid_ctl, sta->phl_sta->macid)) { miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter); miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK); @@ -3218,13 +2143,14 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn , miracast_enabled , miracast_sink , role - , sta->cmn.mac_id + , sta->phl_sta->macid ); +#endif } u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected) { - struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter_to_dvobj(adapter)->cmdpriv; struct cmd_obj *cmdobj; struct drvextra_cmd_parm *cmd_parm; struct sta_media_status_rpt_cmd_parm *rpt_parm; @@ -3235,6 +2161,7 @@ u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool co res = _FAIL; goto exit; } + cmdobj->padapter = adapter; cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (cmd_parm == NULL) { @@ -3273,7 +2200,6 @@ inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) { - _irqL irqL; struct sta_info *psta; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; @@ -3293,20 +2219,20 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) u8 *passoc_req = NULL; u32 assoc_req_len = 0; - rtw_sta_media_status_rpt(adapter, psta, 1); + rtw_alloc_stainfo_hw(&adapter->stapriv, psta); -#ifdef CONFIG_MCC_MODE - rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE); -#endif /* CONFIG_MCC_MODE */ +#if 0 + rtw_sta_media_status_rpt(adapter, psta, 1); +#else + rtw_hw_connected_apmode(adapter, psta); +#endif #ifndef CONFIG_AUTO_AP_MODE - ap_sta_info_defer_update(adapter, psta); - if (!MLME_IS_MESH(adapter)) { /* report to upper layer */ RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); #ifdef CONFIG_IOCTL_CFG80211 - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); if (psta->passoc_req && psta->assoc_req_len > 0) { passoc_req = rtw_zmalloc(psta->assoc_req_len); if (passoc_req) { @@ -3314,7 +2240,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); } } - _exit_critical_bh(&psta->lock, &irqL); + _rtw_spinunlock_bh(&psta->lock); if (passoc_req && assoc_req_len > 0) { rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); @@ -3326,18 +2252,8 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) } #endif /* !CONFIG_AUTO_AP_MODE */ -#ifdef CONFIG_BEAMFORMING - beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0); -#endif/*CONFIG_BEAMFORMING*/ if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm)) rtw_ap_wep_pk_setting(adapter, psta); - - #ifdef CONFIG_PLATFORM_CMAP_INTFS - if (MLME_IS_AP(adapter)) { - cmap_intfs_nl_sta_event(psta->cmn.mac_addr, adapter_mac_addr(adapter), 1 - , psta->passoc_req + IEEE80211_3ADDR_LEN, psta->assoc_req_len - IEEE80211_3ADDR_LEN); - } - #endif } goto exit; } @@ -3360,23 +2276,23 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) psta->ieee8021x_blocked = _FALSE; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { if (adapter->stapriv.asoc_sta_count == 2) { - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); pmlmepriv->cur_network_scanned = ptarget_wlan; if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); /* a sta + bc/mc_stainfo (not Ibss_stainfo) */ rtw_indicate_connect(adapter); } } - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); mlmeext_sta_add_event_callback(adapter, psta); @@ -3396,18 +2312,17 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) #ifdef CONFIG_IEEE80211W void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) { -#ifdef CONFIG_AP_MODE - _irqL irqL; struct sta_info *psta; struct stadel_event *pstadel = (struct stadel_event *)pbuf; struct sta_priv *pstapriv = &adapter->stapriv; + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); if (psta) { u8 updated = _FALSE; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -3415,66 +2330,79 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) if (psta->tbtx_enable) pstapriv->tbtx_asoc_list_cnt--; #endif - updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE, _FALSE); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); } -#endif /* CONFIG_AP_MODE */ + + + } #endif /* CONFIG_IEEE80211W */ -void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) + +/* Note: the caller should already have lock of a->mlmepriv.lock */ +/* Note2: There may be I/O in rtw_free_assoc_resources() */ +static void _stadel_posthandle_sta(struct _ADAPTER *a, + struct stadel_event *stadel) { - struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct mlme_priv *mlme = &a->mlmepriv; + u16 reason = *((unsigned short *)stadel->rsvd); + bool roam = _FALSE; + struct wlan_network *roam_target = NULL; - if (mac_id < macid_ctl->num) { - u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */ - RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter) - , mac_id, id_is_shared ? " shared" : ""); +#ifdef CONFIG_LAYER2_ROAMING +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam_expired(a, reason)) + mlme->ft_roam.ft_roam_on_expired = _TRUE; + else + mlme->ft_roam.ft_roam_on_expired = _FALSE; +#endif + if (a->registrypriv.wifi_spec == 1) { + roam = _FALSE; + } else if ((reason == WLAN_REASON_EXPIRATION_CHK) + && rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) { + roam = _TRUE; + } else if ((reason == WLAN_REASON_ACTIVE_ROAM) + && rtw_chk_roam_flags(a, RTW_ROAM_ACTIVE)) { + roam = _TRUE; + roam_target = mlme->roam_network; + } +#ifdef CONFIG_RTW_80211R + if ((reason == WLAN_REASON_ACTIVE_ROAM) + && rtw_ft_chk_flags(a, RTW_FT_BTM_ROAM)) { + roam = _TRUE; + roam_target = mlme->roam_network; + } +#endif - if (!id_is_shared) { - rtw_hal_macid_drop(adapter, mac_id); - rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); - /* - * For safety, prevent from keeping macid sleep. - * If we can sure all power mode enter/leave are paired, - * this check can be removed. - * Lucas@20131113 - */ - /* wakeup macid after disconnect. */ - /*if (MLME_IS_STA(adapter))*/ - rtw_hal_macid_wakeup(adapter, mac_id); - } + if (roam == _TRUE) { + if (rtw_to_roam(a) > 0) + rtw_dec_to_roam(a); /* this stadel_event is caused by roaming, decrease to_roam */ + else if (rtw_to_roam(a) == 0) + rtw_set_to_roam(a, a->registrypriv.max_roaming_times); } else { - RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" - , FUNC_ADPT_ARG(adapter), mac_id); - rtw_warn_on(1); + rtw_set_to_roam(a, 0); } -} -void rtw_sta_mstatus_report(_adapter *adapter) -{ - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct wlan_network *tgt_network = &pmlmepriv->cur_network; - struct sta_info *psta = NULL; +#endif /* CONFIG_LAYER2_ROAMING */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { - psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); - if (psta) - rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id); - else { - RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress)); - rtw_warn_on(1); - } - } +#if 0 + rtw_free_uc_swdec_pending_queue(adapter_to_dvobj(a)); +#endif + if (MLME_IS_ASOC(a)) + rtw_free_assoc_resources(a, _TRUE); + rtw_free_mlme_priv_ie_data(mlme); + + rtw_indicate_disconnect(a, *(u16 *)stadel->rsvd, stadel->locally_generated); + + _rtw_roaming(a, roam_target); } void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) { - _irqL irqL, irqL2; - struct sta_info *psta; struct wlan_network *pwlan = NULL; WLAN_BSSID_EX *pdev_network = NULL; @@ -3484,15 +2412,6 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) struct wlan_network *tgt_network = &(pmlmepriv->cur_network); RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); -#ifdef CONFIG_LAYER2_ROAMING - if (pmlmepriv->roam_network) - rtw_msleep_os(RTW_ROAM_DICONNECT_DELAY); -#endif - rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); - -#ifdef CONFIG_MCC_MODE - rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE); -#endif /* CONFIG_MCC_MODE */ psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); @@ -3501,15 +2420,16 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) /*rtw_warn_on(1);*/ } - if (psta) + if (psta) { rtw_wfd_st_switch(psta, 0); + psta->hw_decrypted = _FALSE; + } if (MLME_IS_MESH(adapter)) { rtw_free_stainfo(adapter, psta); goto exit; } -#ifdef CONFIG_AP_MODE if (MLME_IS_AP(adapter)) { #ifdef CONFIG_IOCTL_CFG80211 #ifdef COMPAT_KERNEL_RELEASE @@ -3519,80 +2439,30 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ #endif /* CONFIG_IOCTL_CFG80211 */ - #ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_nl_sta_event(pstadel->macaddr, adapter_mac_addr(adapter), 0, NULL, 0); - #endif + rtw_hw_disconnect(adapter, psta); rtw_free_stainfo(adapter, psta); goto exit; } -#endif /* CONFIG_AP_MODE */ mlmeext_sta_del_event_callback(adapter); - _enter_critical_bh(&pmlmepriv->lock, &irqL2); - - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - u16 reason = *((unsigned short *)(pstadel->rsvd)); - bool roam = _FALSE; - struct wlan_network *roam_target = NULL; - -#ifdef CONFIG_LAYER2_ROAMING -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam_expired(adapter, reason)) - pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE; - else - pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE; -#endif - if (adapter->registrypriv.wifi_spec == 1) - roam = _FALSE; - else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) - roam = _TRUE; - else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { - roam = _TRUE; - roam_target = pmlmepriv->roam_network; - } - -#ifdef CONFIG_RTW_80211R - if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_ft_chk_flags(adapter, RTW_FT_BTM_ROAM)) { - roam = _TRUE; - roam_target = pmlmepriv->roam_network; - } -#endif - - if (roam == _TRUE) { - if (rtw_to_roam(adapter) > 0) - rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */ - else if (rtw_to_roam(adapter) == 0) - rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times); - } else - rtw_set_to_roam(adapter, 0); -#endif /* CONFIG_LAYER2_ROAMING */ - - rtw_free_uc_swdec_pending_queue(adapter); + _rtw_spinlock_bh(&pmlmepriv->lock); - rtw_free_assoc_resources(adapter, _TRUE); - rtw_free_mlme_priv_ie_data(pmlmepriv); - - rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated); - -#ifdef CONFIG_LAYER2_ROAMING - _rtw_roaming(adapter, roam_target); -#endif - } + if (MLME_IS_STA(adapter)) + _stadel_posthandle_sta(adapter, pstadel); -#ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) || - check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { + if (MLME_IS_ADHOC_MASTER(adapter) || + MLME_IS_ADHOC(adapter)) { - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ rtw_free_stainfo(adapter, psta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ if (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */ /* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */ - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); /* free old ibss network */ /* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); @@ -3600,7 +2470,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) pwlan->fixed = _FALSE; rtw_free_network_nolock(adapter, pwlan); } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); /* re-create ibss */ pdev_network = &(adapter->registrypriv.dev_network); pibss = adapter->registrypriv.dev_network.MacAddress; @@ -3614,7 +2484,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) rtw_generate_random_ibss(pibss); - if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { + if (MLME_IS_ADHOC(adapter)) { set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE); } @@ -3625,8 +2495,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) } } -#endif /* CONFIG_AP_MODE */ - _exit_critical_bh(&pmlmepriv->lock, &irqL2); + + _rtw_spinunlock_bh(&pmlmepriv->lock); exit: #ifdef CONFIG_RTS_FULL_BW rtw_set_rts_bw(adapter); @@ -3634,7 +2504,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) return; } -void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) +void rtw_wmm_event_callback(_adapter *padapter, u8 *pbuf) { WMMOnAssocRsp(padapter); @@ -3648,11 +2518,10 @@ void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) void rtw_join_timeout_handler(void *ctx) { _adapter *adapter = (_adapter *)ctx; - _irqL irqL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; #if 0 - if (rtw_is_drv_stopped(adapter)) { + if (dev_is_drv_stopped(adapter_to_dvobj(adapter))) { _rtw_up_sema(&pmlmepriv->assoc_terminate); return; } @@ -3662,11 +2531,11 @@ void rtw_join_timeout_handler(void *ctx) RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); - if (RTW_CANNOT_RUN(adapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) return; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); #ifdef CONFIG_LAYER2_ROAMING if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */ @@ -3684,10 +2553,13 @@ void rtw_join_timeout_handler(void *ctx) } else { RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__); #ifdef CONFIG_RTW_80211R - rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + /* rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); */ rtw_ft_reset_status(adapter); #endif rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); +#ifdef CONFIG_STA_CMD_DISPR + rtw_connect_abort(adapter); +#endif break; } } @@ -3695,6 +2567,11 @@ void rtw_join_timeout_handler(void *ctx) } else #endif { +#ifdef CONFIG_STA_CMD_DISPR + if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) + rtw_connect_abort(adapter); +#endif /* CONFIG_STA_CMD_DISPR */ + rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); free_scanqueue(pmlmepriv);/* ??? */ @@ -3702,12 +2579,11 @@ void rtw_join_timeout_handler(void *ctx) /* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */ rtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); #endif /* CONFIG_IOCTL_CFG80211 */ - } pmlmepriv->join_status = 0; /* reset */ - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); #ifdef CONFIG_DRVEXT_MODULE_WSC @@ -3716,34 +2592,6 @@ void rtw_join_timeout_handler(void *ctx) -} - -/* -* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey -* @adapter: pointer to _adapter structure -*/ -void rtw_scan_timeout_handler(void *ctx) -{ - _adapter *adapter = (_adapter *)ctx; - _irqL irqL; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - - _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); - - _exit_critical_bh(&pmlmepriv->lock, &irqL); - -#ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_surveydone_event_callback(adapter); -#endif /* CONFIG_IOCTL_CFG80211 */ - - rtw_indicate_scan_done(adapter, _TRUE); - -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) - rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE); -#endif } void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) @@ -3759,7 +2607,7 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) *reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED; rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL); - if (hal_chk_bw_cap(adapter, BW_CAP_40M) + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(adapter), BW_CAP_40M) && is_client_associated_to_ap(adapter) == _TRUE && u_ch >= 1 && u_ch <= 14 && adapter->registrypriv.wifi_spec @@ -3790,92 +2638,6 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) return; } -void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) -{ - struct sitesurvey_parm parm; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - int i; -#if 1 - u8 ssc_chk; - - ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); - if( ssc_chk == SS_DENY_BUSY_TRAFFIC) { - #ifdef CONFIG_LAYER2_ROAMING - if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter)); - else - #endif - { - RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } - } - else if (ssc_chk != SS_ALLOW) - goto exit; - - if (!rtw_is_adapter_up(padapter)) - goto exit; -#else - if (rtw_is_scan_deny(padapter)) - goto exit; - - if (!rtw_is_adapter_up(padapter)) - goto exit; - - if (rtw_mi_busy_traffic_check(padapter)) { -#ifdef CONFIG_LAYER2_ROAMING - if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) { - RTW_INFO("need to roam, don't care BusyTraffic\n"); - } else -#endif - { - RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } - } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } - if (check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) == _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" WIFI_UNDER_SURVEY|WIFI_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } - -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS))) { - RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter)); - goto exit; - } -#endif -#endif - - RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason); - - /* only for 20/40 BSS */ - if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) { - rtw_init_sitesurvey_parm(padapter, &parm); - for (i=0;i<14;i++) { - parm.ch[i].hw_value = i + 1; - parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; - } - parm.ch_num = 14; - rtw_set_802_11_bssid_list_scan(padapter, &parm); - goto exit; - } - -#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) - if ((reason == RTW_AUTO_SCAN_REASON_ROAM) - && (rtw_roam_nb_scan_list_set(padapter, &parm))) - goto exit; -#endif - - rtw_init_sitesurvey_parm(padapter, &parm); - parm.reason = reason; - rtw_set_802_11_bssid_list_scan(padapter, &parm); -exit: - return; -} static void rtw_auto_scan_handler(_adapter *padapter) { @@ -3885,7 +2647,8 @@ static void rtw_auto_scan_handler(_adapter *padapter) rtw_mlme_reset_auto_scan_int(padapter, &reason); #ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) + if (rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_CLIENT) || + rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_GO)) goto exit; #endif @@ -3909,19 +2672,56 @@ static u8 is_drv_in_lps(_adapter *adapter) #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE) - #ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE) - #endif ) is_in_lps = _TRUE; #endif /* CONFIG_LPS_LCLK_WD_TIMER*/ return is_in_lps; } + +void rtw_iface_dynamic_check_handlder(struct _ADAPTER *a) +{ + if (!a->netif_up) + return; + + /* auto site survey */ + rtw_auto_scan_handler(a); + +#ifdef CONFIG_BR_EXT +if (!adapter_use_wds(a)) { + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); + #endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */ + + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + if (a->pnetdev->br_port + #else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + if (rcu_dereference(a->pnetdev->rx_handler_data) + #endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + && (MLME_IS_STA(a) || MLME_IS_ADHOC(a))) { + /* expire NAT2.5 entry */ + void nat25_db_expire(_adapter *priv); + nat25_db_expire(a); + + if (a->pppoe_connection_in_progress > 0) + a->pppoe_connection_in_progress--; + if (a->pppoe_connection_in_progress > 0) + a->pppoe_connection_in_progress--; + } + + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_unlock(); + #endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */ +} +#endif /* CONFIG_BR_EXT */ +} + void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) { +#ifdef CONFIG_AP_MODE struct mlme_priv *pmlmepriv = &adapter->mlmepriv; +#endif /* CONFIG_AP_MODE */ - if (adapter->net_closed == _TRUE) + if (!adapter->netif_up) return; #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ if (is_drv_in_lps(adapter)) { @@ -3930,18 +2730,17 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) linked_status_chk(adapter, 1); bEnterPS = traffic_status_watchdog(adapter, 1); + #if 0 /*PS TODO ...*/ if (bEnterPS) { /* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */ rtw_hal_dm_watchdog_in_lps(adapter); } else { /* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0) in traffic_status_watchdog() */ } + #endif } #endif /* CONFIG_LPS_LCLK_WD_TIMER */ - /* auto site survey */ - rtw_auto_scan_handler(adapter); - #ifdef CONFIG_AP_MODE if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) { #ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK @@ -3954,41 +2753,14 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) } #endif /*CONFIG_AP_MODE*/ - -#ifdef CONFIG_BR_EXT -if (!adapter_use_wds(adapter)) { -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) - rcu_read_lock(); -#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */ - -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - if (adapter->pnetdev->br_port -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - if (rcu_dereference(adapter->pnetdev->rx_handler_data) -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { - /* expire NAT2.5 entry */ - void nat25_db_expire(_adapter *priv); - nat25_db_expire(adapter); - - if (adapter->pppoe_connection_in_progress > 0) - adapter->pppoe_connection_in_progress--; - /* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */ - if (adapter->pppoe_connection_in_progress > 0) - adapter->pppoe_connection_in_progress--; - } - -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */ -} -#endif /* CONFIG_BR_EXT */ - + rtw_iface_dynamic_check_handlder(adapter); } /*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/ static void collect_sta_traffic_statistics(_adapter *adapter) { +/* ToDo */ +#if 0 struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; struct sta_info *sta; u64 curr_tx_bytes = 0, curr_rx_bytes = 0; @@ -3997,7 +2769,7 @@ static void collect_sta_traffic_statistics(_adapter *adapter) for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) { + if (sta && !is_broadcast_mac_addr(sta->phl_sta->mac_addr)) { if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes) sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes) @@ -4018,16 +2790,16 @@ static void collect_sta_traffic_statistics(_adapter *adapter) curr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/ curr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/ - sta->cmn.tx_moving_average_tp = - (sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/ + sta->phl_sta->tx_moving_average_tp = + (sta->phl_sta->tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/ - sta->cmn.rx_moving_average_tp = - (sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/ + sta->phl_sta->rx_moving_average_tp = + (sta->phl_sta->rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/ rtw_collect_bcn_info(sta->padapter); if (adapter->bsta_tp_dump) - dump_sta_traffic(RTW_DBGDUMP, adapter, sta); + rtw_hal_dump_sta_traffic(RTW_DBGDUMP, adapter, sta); sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes; @@ -4035,19 +2807,23 @@ static void collect_sta_traffic_statistics(_adapter *adapter) sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes; } } +#endif } void rtw_sta_traffic_info(void *sel, _adapter *adapter) { +/* ToDo */ +#if 0 struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; struct sta_info *sta; int i; for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) - dump_sta_traffic(sel, adapter, sta); + if (sta && !is_broadcast_mac_addr(sta->phl_sta->mac_addr)) + rtw_hal_dump_sta_traffic(sel, adapter, sta); } +#endif } /*#define DBG_TRAFFIC_STATISTIC*/ @@ -4097,7 +2873,7 @@ static void collect_traffic_statistics(_adapter *padapter) #endif } - +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ void rtw_dynamic_check_timer_handlder(void *ctx) { struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; @@ -4113,10 +2889,10 @@ void rtw_dynamic_check_timer_handlder(void *ctx) } #endif - if (!rtw_is_hw_init_completed(adapter)) + if (!rtw_hw_is_init_completed(pdvobj)) goto exit; - if (RTW_CANNOT_RUN(adapter)) + if (RTW_CANNOT_RUN(pdvobj)) goto exit; collect_traffic_statistics(adapter); @@ -4129,36 +2905,90 @@ void rtw_dynamic_check_timer_handlder(void *ctx) exit: _set_timer(&pdvobj->dynamic_chk_timer, 2000); } +#endif +#ifdef CONFIG_CMD_GENERAL +void rtw_core_watchdog_sw_hdlr(void *drv_priv) +{ + struct dvobj_priv *pdvobj = (struct dvobj_priv *)drv_priv; + struct _ADAPTER *adapter = dvobj_get_primary_adapter(pdvobj); + if (!adapter) + goto exit; +#if (MP_DRIVER == 1) + /* for MP ODM dynamic Tx power tracking */ + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { + /* RTW_INFO("%s mp_dm =0 return\n", __func__); */ + goto exit; + } +#endif + if (!rtw_hw_is_init_completed(pdvobj)) + goto exit; -#ifdef CONFIG_SET_SCAN_DENY_TIMER -inline bool rtw_is_scan_deny(_adapter *adapter) -{ - struct mlme_priv *mlmepriv = &adapter->mlmepriv; - return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE; -} + collect_traffic_statistics(adapter); + collect_sta_traffic_statistics(adapter); + rtw_mi_dynamic_check_handlder(adapter); + rtw_dynamic_chk_wk_sw_hdl(adapter); -inline void rtw_clear_scan_deny(_adapter *adapter) -{ - struct mlme_priv *mlmepriv = &adapter->mlmepriv; - ATOMIC_SET(&mlmepriv->set_scan_deny, 0); - if (0) - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); +exit: + return; } -void rtw_set_scan_deny_timer_hdl(void *ctx) +void rtw_core_watchdog_hw_hdlr(void *drv_priv) { - _adapter *adapter = (_adapter *)ctx; + struct dvobj_priv *pdvobj = (struct dvobj_priv *)drv_priv; + struct _ADAPTER *adapter = dvobj_get_primary_adapter(pdvobj); + + if (!adapter) + goto exit; +#if (MP_DRIVER == 1) + /* for MP ODM dynamic Tx power tracking */ + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { + /* RTW_INFO("%s mp_dm =0 return\n", __func__); */ + goto exit; + } +#endif + if (!rtw_hw_is_init_completed(pdvobj)) + goto exit; - rtw_clear_scan_deny(adapter); + if (RTW_CANNOT_RUN(pdvobj)) + goto exit; + + rtw_dynamic_chk_wk_hw_hdl(adapter); + +exit: + return; } -void rtw_set_scan_deny(_adapter *adapter, u32 ms) +#else +int rtw_dynamic_check_handlder(void *ctx, void *parm, bool discard) { - struct mlme_priv *mlmepriv = &adapter->mlmepriv; - if (0) - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - ATOMIC_SET(&mlmepriv->set_scan_deny, 1); - _set_timer(&mlmepriv->set_scan_deny_timer, ms); + struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; + struct _ADAPTER *adapter = dvobj_get_primary_adapter(pdvobj); + + if (!adapter) + goto exit; + +#if (MP_DRIVER == 1) + /* for MP ODM dynamic Tx power tracking */ + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { + /* RTW_INFO("%s mp_dm =0 return\n", __func__); */ + goto exit; + } +#endif + + if (!rtw_hw_is_init_completed(pdvobj)) + goto exit; + + if (RTW_CANNOT_RUN(pdvobj)) + goto exit; + + collect_traffic_statistics(adapter); + collect_sta_traffic_statistics(adapter); + rtw_mi_dynamic_check_handlder(adapter); + rtw_dynamic_chk_wk_hdl(adapter); + +exit: + + return 0; } #endif @@ -4184,34 +3014,23 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme && rtw_chset_is_ch_non_ocp(chset, ch)) goto exit; -#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) - if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor)) - goto update; - goto exit; -#endif - if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) goto exit; if (rtw_is_desired_network(adapter, competitor) == _FALSE) goto exit; -#ifdef CONFIG_RTW_ROAM_QUICKSCAN - if (competitor->network.PhyInfo.SignalStrength > CONFIG_RTW_ROAM_QUICKSCAN_TH) - adapter->mlmeextpriv.quickscan_next = _TRUE; -#endif - #ifdef CONFIG_LAYER2_ROAMING if (mlme->need_to_roam == _FALSE) goto exit; #endif - RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d dBm, age:%5d\n", + RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n", (competitor == mlme->cur_network_scanned) ? "*" : " " , competitor->network.Ssid.Ssid, MAC_ARG(competitor->network.MacAddress), competitor->network.Configuration.DSConfig, - (int)competitor->network.Rssi, + (int)competitor->network.PhyInfo.rssi, rtw_get_passing_time_ms(competitor->last_scanned) ); @@ -4241,10 +3060,10 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms) goto exit; - if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th) + if (competitor->network.PhyInfo.rssi - mlme->cur_network_scanned->network.PhyInfo.rssi < mlme->roam_rssi_diff_th) goto exit; - if (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi) + if (*candidate != NULL && (*candidate)->network.PhyInfo.rssi >= competitor->network.PhyInfo.rssi) goto exit; #else goto exit; @@ -4260,7 +3079,6 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme int rtw_select_roaming_candidate(struct mlme_priv *mlme) { - _irqL irqL; int ret = _FAIL; _list *phead; _adapter *adapter; @@ -4273,7 +3091,7 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) goto exit; } - _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(mlme->scanned_queue.lock)); phead = get_list_head(queue); adapter = (_adapter *)mlme->nic_hdl; @@ -4294,7 +3112,7 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) , pnetwork->network.Ssid.Ssid , MAC_ARG(pnetwork->network.MacAddress) , pnetwork->network.Configuration.DSConfig - , (int)pnetwork->network.Rssi); + , (int)pnetwork->network.PhyInfo.rssi); rtw_check_roaming_candidate(mlme, &candidate, pnetwork); @@ -4302,36 +3120,13 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) if (candidate == NULL) { /* if parent note lost the path to root and there is no other cadidate, report disconnection */ -#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) - struct rtw_rson_struct rson_curr; - u8 rson_score; - - rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr); - rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi); - if (check_fwstate(mlme, WIFI_ASOC_STATE) - && ((rson_score == RTW_RSON_SCORE_NOTCNNT) - || (rson_score == RTW_RSON_SCORE_NOTSUP))) - receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress - , WLAN_REASON_EXPIRATION_CHK, _FALSE); -#endif RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); ret = _FAIL; goto exit; } else { -#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) - struct rtw_rson_struct rson_curr; - u8 rson_score; - - rtw_get_rson_struct(&(candidate->network), &rson_curr); - rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi); - RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__, - candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), - candidate->network.Configuration.DSConfig, rson_score); -#else RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), candidate->network.Configuration.DSConfig); -#endif mlme->roam_network = candidate; if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE) @@ -4340,7 +3135,7 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) ret = _SUCCESS; exit: - _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(mlme->scanned_queue.lock)); return ret; } @@ -4367,25 +3162,6 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme && rtw_chset_is_ch_non_ocp(chset, ch)) goto exit; -#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) - s16 rson_score; - struct rtw_rson_struct rson_data; - - if (rtw_rson_choose(candidate, competitor)) { - *candidate = competitor; - rtw_get_rson_struct(&((*candidate)->network), &rson_data); - rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi); - RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n", - mlme->assoc_ssid.Ssid, - (*candidate)->network.Ssid.Ssid, - MAC_ARG((*candidate)->network.MacAddress), - (*candidate)->network.Configuration.DSConfig, - rson_score); - return _TRUE; - } - return _FALSE; -#endif - /* check bssid, if needed */ if (mlme->assoc_by_bssid == _TRUE) { if (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE) @@ -4412,21 +3188,21 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme } #endif - if (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) { + if (*candidate == NULL || (*candidate)->network.PhyInfo.rssi < competitor->network.PhyInfo.rssi) { *candidate = competitor; updated = _TRUE; } if (updated) { RTW_INFO("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] " - "new candidate: %s("MAC_FMT", ch%u) rssi:%d dBm\n", + "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n", mlme->assoc_by_bssid, mlme->assoc_ssid.Ssid, rtw_to_roam(adapter), (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress), (*candidate)->network.Configuration.DSConfig, - (int)(*candidate)->network.Rssi + (int)(*candidate)->network.PhyInfo.rssi ); } @@ -4447,7 +3223,6 @@ pmlmepriv->lock int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) { - _irqL irqL; int ret; _list *phead; _adapter *adapter; @@ -4460,7 +3235,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) adapter = (_adapter *)pmlmepriv->nic_hdl; - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); #ifdef CONFIG_LAYER2_ROAMING if (pmlmepriv->roam_network) { @@ -4487,7 +3262,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) , pnetwork->network.Ssid.Ssid , MAC_ARG(pnetwork->network.MacAddress) , pnetwork->network.Configuration.DSConfig - , (int)pnetwork->network.Rssi); + , (int)pnetwork->network.PhyInfo.rssi); rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork); @@ -4525,27 +3300,21 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) #endif { rtw_disassoc_cmd(adapter, 0, 0); + if (1 +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(adapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources_cmd(adapter, _TRUE, 0); rtw_indicate_disconnect(adapter, 0, _FALSE); - rtw_free_assoc_resources_cmd(adapter, _TRUE, 0); } } -#ifdef CONFIG_ANTENNA_DIVERSITY - rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); - if (_TRUE == bSupportAntDiv) { - u8 CurrentAntenna; - rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL); - RTW_INFO("#### Opt_Ant_(%s) , cur_Ant(%s)\n", - (MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? "MAIN_ANT" : "AUX_ANT", - (MAIN_ANT == CurrentAntenna) ? "MAIN_ANT" : "AUX_ANT" - ); - } -#endif set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); ret = rtw_joinbss_cmd(adapter, candidate); exit: - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); return ret; @@ -4553,10 +3322,10 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) { - struct cmd_obj *pcmd; - struct setauth_parm *psetauthparm; - struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); - sint res = _SUCCESS; + struct cmd_obj *pcmd; + struct setauth_parm *psetauthparm; + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(adapter)->cmdpriv); + sint res = _SUCCESS; pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); @@ -4564,6 +3333,7 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) res = _FAIL; /* try again */ goto exit; } + pcmd->padapter = adapter; psetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm)); if (psetauthparm == NULL) { @@ -4575,33 +3345,97 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm)); psetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm; - pcmd->cmdcode = CMD_SET_AUTH; + pcmd->cmdcode = CMD_SET_AUTH; /* _SetAuth_CMD_;*/ pcmd->parmbuf = (unsigned char *)psetauthparm; pcmd->cmdsz = (sizeof(struct setauth_parm)); pcmd->rsp = NULL; pcmd->rspsz = 0; - _rtw_init_listhead(&pcmd->list); - res = rtw_enqueue_cmd(pcmdpriv, pcmd); - exit: + return res; +} +#ifdef CONFIG_CMD_DISP +sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue) +{ + u8 keylen; + struct setkey_parm setkeyparm; + sint res = _SUCCESS; - return res; + _rtw_memset(&setkeyparm, 0, sizeof(struct setkey_parm)); + + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { + /* BIP use keyid 4 or 5 */ + if (keyid >= 4) + setkeyparm.algorithm = (unsigned char)psecuritypriv->dot11wCipher; + else + setkeyparm.algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy; + } else { + setkeyparm.algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm; + + } + setkeyparm.keyid = (u8)keyid;/* 0~3 */ + setkeyparm.set_tx = set_tx; + if (is_wep_enc(setkeyparm.algorithm)) + adapter->securitypriv.key_mask |= BIT(setkeyparm.keyid); + + RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", setkeyparm.algorithm, setkeyparm.keyid, adapter->securitypriv.key_mask); + + switch (setkeyparm.algorithm) { + + case _WEP40_: + keylen = 5; + _rtw_memcpy(&(setkeyparm.key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _WEP104_: + keylen = 13; + _rtw_memcpy(&(setkeyparm.key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _TKIP_: + keylen = 16; + _rtw_memcpy(&setkeyparm.key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + break; + case _AES_: + case _GCMP_: + keylen = 16; + _rtw_memcpy(&setkeyparm.key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + break; + case _GCMP_256_: + case _CCMP_256_: + keylen = 32; + _rtw_memcpy(&setkeyparm.key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + break; + #ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + keylen = 16; + _rtw_memcpy(&setkeyparm.key, &psecuritypriv->dot11wBIPKey[keyid], keylen); + break; + #endif /* CONFIG_IEEE80211W */ + default: + res = _FAIL; + goto exit; + } -} + if (enqueue) + setkey_hdl(adapter, &setkeyparm, PHL_CMD_NO_WAIT, 0); + else + setkey_hdl(adapter, &setkeyparm, PHL_CMD_DIRECTLY, 0); +exit: + return res; +} +#else /* CONFIG_FSM */ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue) { - u8 keylen; - struct cmd_obj *pcmd; - struct setkey_parm *psetkeyparm; - struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); - sint res = _SUCCESS; + u8 keylen; + struct cmd_obj *pcmd; + struct setkey_parm *psetkeyparm; + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(adapter)->cmdpriv); + sint res = _SUCCESS; psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm)); @@ -4612,7 +3446,11 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { - psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy; + /* BIP use keyid 4 or 5 */ + if (keyid >= 4) + psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot11wCipher; + else + psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy; } else { psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm; @@ -4648,6 +3486,12 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke keylen = 32; _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); break; + #ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + keylen = 16; + _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot11wBIPKey[keyid], keylen); + break; + #endif /* CONFIG_IEEE80211W */ default: res = _FAIL; rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); @@ -4662,8 +3506,9 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke res = _FAIL; /* try again */ goto exit; } + pcmd->padapter = adapter; - pcmd->cmdcode =CMD_SET_KEY; + pcmd->cmdcode = CMD_SET_KEY; /*_SetKey_CMD_*/ pcmd->parmbuf = (u8 *)psetkeyparm; pcmd->cmdsz = (sizeof(struct setkey_parm)); pcmd->rsp = NULL; @@ -4682,7 +3527,7 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke return res; } - +#endif #ifdef CONFIG_WMMPS_STA /* * rtw_uapsd_use_default_setting @@ -4869,9 +3714,9 @@ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, u * * */ -static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) +static int SecIsInPMKIDList(_adapter *adapter, u8 *bssid) { - struct security_priv *psecuritypriv = &Adapter->securitypriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; int i = 0; do { @@ -4895,9 +3740,9 @@ static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) } -int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid) +int rtw_cached_pmkid(_adapter *adapter, u8 *bssid) { - return SecIsInPMKIDList(Adapter, bssid); + return SecIsInPMKIDList(adapter, bssid); } int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent) @@ -4918,9 +3763,6 @@ int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent) if (i_ent < 0 && info.pmkid_cnt == 0) goto exit; - if (info.pmkid_list == NULL) - goto exit; - if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) { RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID)); @@ -5045,15 +3887,15 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter) pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */ - pdev_network->Rssi = 0; + pdev_network->PhyInfo.rssi = 0; pdev_network->Configuration.DSConfig = (pregistrypriv->channel); if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) { pdev_network->Configuration.ATIMWindow = (0); - if (pmlmeext->cur_channel != 0) - pdev_network->Configuration.DSConfig = pmlmeext->cur_channel; + if (pmlmeext->chandef.chan != 0) + pdev_network->Configuration.DSConfig = pmlmeext->chandef.chan; else pdev_network->Configuration.DSConfig = 1; } @@ -5120,12 +3962,15 @@ void rtw_joinbss_reset(_adapter *padapter) #ifdef CONFIG_80211N_HT -void rtw_ht_use_default_setting(_adapter *padapter) +void rtw_ht_get_dft_setting(_adapter *padapter, + struct protocol_cap_t *dft_proto_cap, + struct role_cap_t *dft_cap) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; struct registry_priv *pregistrypriv = &padapter->registrypriv; BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + u8 stbc_rx = 0; #ifdef CONFIG_BEAMFORMING BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; #endif /* CONFIG_BEAMFORMING */ @@ -5135,17 +3980,20 @@ void rtw_ht_use_default_setting(_adapter *padapter) else phtpriv->bss_coexist = 0; + /*dft_proto_cap->sgi_40;*/ phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE; + /*dft_proto_cap->sgi_20;*/ phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE; /* LDPC support */ - rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); CLEAR_FLAGS(phtpriv->ldpc_cap); + bHwLDPCSupport = (dft_proto_cap->ht_ldpc) ? _TRUE : _FALSE; if (bHwLDPCSupport) { if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4)) SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX); } - rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + + bHwLDPCSupport = (dft_cap->tx_ht_ldpc) ? _TRUE : _FALSE; if (bHwLDPCSupport) { if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5)) SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX); @@ -5154,35 +4002,27 @@ void rtw_ht_use_default_setting(_adapter *padapter) RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap); /* STBC */ - rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); CLEAR_FLAGS(phtpriv->stbc_cap); - if (bHwSTBCSupport) { - if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5)) - SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX); - } - rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); - if (bHwSTBCSupport) { - if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4)) - SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX); - } + if (dft_proto_cap->stbc_ht_tx) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX); + + if (dft_proto_cap->stbc_ht_rx) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX); + if (phtpriv->stbc_cap) RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap); /* Beamforming setting */ CLEAR_FLAGS(phtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 -#ifdef CONFIG_CONCURRENT_MODE /* only enable beamforming in STA client mode */ - if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)) -#else - if ((MLME_IS_AP(padapter) && !MLME_IS_GO(padapter)) || - (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter))) -#endif -#endif + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) { - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); + bHwSupportBeamformer = (dft_proto_cap->ht_su_bfmr) ? _TRUE : _FALSE; + bHwSupportBeamformee = (dft_proto_cap->ht_su_bfme) ? _TRUE : _FALSE; + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); RTW_INFO("[HT] HAL Support Beamformer\n"); @@ -5194,6 +4034,66 @@ void rtw_ht_use_default_setting(_adapter *padapter) } #endif /* CONFIG_BEAMFORMING */ } + +void rtw_ht_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + u8 stbc_rx = 0; +#ifdef CONFIG_BEAMFORMING + BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; +#endif /* CONFIG_BEAMFORMING */ + + if (pregistrypriv->wifi_spec) + phtpriv->bss_coexist = 1; + else + phtpriv->bss_coexist = 0; + + phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE; + phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE; + + /* LDPC support */ + if (padapter->phl_role->proto_role_cap.ht_ldpc) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX); + + if (padapter->phl_role->cap.tx_ht_ldpc) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX); + + if (phtpriv->ldpc_cap) + RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap); + + /* STBC */ + if (padapter->phl_role->proto_role_cap.stbc_ht_tx) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX); + + if (padapter->phl_role->proto_role_cap.stbc_ht_rx) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX); + + if (phtpriv->stbc_cap) + RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap); + + /* Beamforming setting */ + CLEAR_FLAGS(phtpriv->beamform_cap); +#ifdef CONFIG_BEAMFORMING + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) + { + if (padapter->phl_role->proto_role_cap.ht_su_bfmr) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + RTW_INFO("[HT] HAL Support Beamformer\n"); + } + + if (padapter->phl_role->proto_role_cap.ht_su_bfme) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + RTW_INFO("[HT] HAL Support Beamformee\n"); + } + } +#endif /* CONFIG_BEAMFORMING */ +} void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len) { unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; @@ -5210,13 +4110,13 @@ void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len) } #if defined(CONFIG_80211N_HT) /* the fucntion is >= passive_level */ -unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel) +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel, struct country_chplan *req_chplan) { u32 ielen, out_len; - u32 rx_packet_offset, max_recvbuf_sz; - HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; - HT_CAP_AMPDU_DENSITY best_ampdu_density; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = 0; + HT_CAP_AMPDU_DENSITY best_ampdu_density = 0; unsigned char *p, *pframe; + enum band_type band = channel > 14 ? BAND_ON_5G : BAND_ON_24G; struct rtw_ieee80211_ht_cap ht_capie; u8 cbw40_enable = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; @@ -5240,11 +4140,11 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20; /* check if 40MHz is allowed according to hal cap and registry */ - if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { - if (channel > 14) { + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_40M)) { + if (band == BAND_ON_5G) { if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) cbw40_enable = 1; - } else { + } else if (band == BAND_ON_24G) { if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) cbw40_enable = 1; } @@ -5253,12 +4153,12 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui if (cbw40_enable) { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); RT_CHANNEL_INFO *chset = rfctl->channel_set; - u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = CHAN_OFFSET_NO_EXT; if (in_ie == NULL) { /* TDLS: TODO 20/40 issue */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - oper_bw = padapter->mlmeextpriv.cur_bwmode; + if (MLME_IS_STA(padapter)) { + oper_bw = padapter->mlmeextpriv.chandef.bw; if (oper_bw > CHANNEL_WIDTH_40) oper_bw = CHANNEL_WIDTH_40; } else @@ -5269,42 +4169,45 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui if (p && ielen == HT_OP_IE_LEN) { if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) { switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) { - case SCA: + case IEEE80211_SCA: oper_bw = CHANNEL_WIDTH_40; - oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + oper_offset = CHAN_OFFSET_UPPER; break; - case SCB: + case IEEE80211_SCB: oper_bw = CHANNEL_WIDTH_40; - oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + oper_offset = CHAN_OFFSET_LOWER; break; } } } - // IOT issue : AP TP-Link WDR6500 + /* IOT issue : AP TP-Link WDR6500 */ if(oper_bw == CHANNEL_WIDTH_40){ p = rtw_get_ie(in_ie, WLAN_EID_HT_CAP, &ielen, in_len); if (p && ielen == HT_CAP_IE_LEN) { oper_bw = GET_HT_CAP_ELE_CHL_WIDTH(p + 2) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; if(oper_bw == CHANNEL_WIDTH_20) - oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + oper_offset = CHAN_OFFSET_NO_EXT; } } } /* adjust bw to fit in channel plan setting */ if (oper_bw == CHANNEL_WIDTH_40 - && oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */ - && (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1) + && oper_offset != CHAN_OFFSET_NO_EXT /* check this because TDLS has no info to set offset */ + ) { + if ((req_chplan && !rtw_country_chplan_is_chbw_valid(req_chplan, band, channel, oper_bw, oper_offset, 1, 1, pregistrypriv)) + || (!req_chplan && !rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1)) || (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset)) - ) - ) { - oper_bw = CHANNEL_WIDTH_20; - oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - rtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1)); - if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl)) - rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset)); + ) { + oper_bw = CHANNEL_WIDTH_20; + oper_offset = CHAN_OFFSET_NO_EXT; + rtw_warn_on(req_chplan && !rtw_country_chplan_is_chbw_valid(req_chplan, band, channel, oper_bw, oper_offset, 1, 1, pregistrypriv)); + rtw_warn_on(!req_chplan && !rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1)); + if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl)) + rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset)); + } } if (oper_bw == CHANNEL_WIDTH_40) { @@ -5332,23 +4235,20 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui } /* RX STBC */ - if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { - if ((pregistrypriv->rx_stbc == 0x3) || /* enable for 2.4/5 GHz */ - ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) || /* enable for 2.4GHz */ - ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) || /* enable for 5GHz */ - (pregistrypriv->wifi_spec == 1)) { - /* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */ - rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); - SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss); - RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss); - } + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX) || + (pregistrypriv->wifi_spec == 1)) { + rx_stbc_nss = padapter->phl_role->proto_role_cap.stbc_ht_rx; + if (rx_stbc_nss > 3) + rx_stbc_nss = 3; + SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss); + RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss); } /* fill default supported_mcs_set */ _rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16); /* update default supported_mcs_set */ - rx_nss = GET_HAL_RX_NSS(padapter); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); switch (rx_nss) { case 1: @@ -5369,29 +4269,15 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R); break; default: - RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss); + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", + GET_HAL_RFPATH(adapter_to_dvobj(padapter)), rx_nss); } - { - rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); - rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); - if (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) { - RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__); - ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU; - } + if (padapter->phl_role->proto_role_cap.max_amsdu_len > 0) { + /*SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(&ht_capie, 1);*/ + RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __func__); + ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU; } - /* - AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k - AMPDU_para [4:2]:Min MPDU Start Spacing - */ - - /* - #if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI) - ht_capie.ampdu_params_info = 2; - #else - ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); - #endif - */ if (padapter->driver_rx_ampdu_factor != 0xFF) max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor; @@ -5428,6 +4314,8 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui /* Compressed Steering Number Antennas */ SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1); rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + if (rf_num > 3) + rf_num = 3; SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num); } @@ -5439,6 +4327,8 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2); rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + if (rf_num > 3) + rf_num = 3; #ifdef CONFIG_80211AC_VHT /* IOT action suggested by Yu Chen 2017/3/3 */ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && @@ -5475,10 +4365,8 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) /* struct sta_info *bmc_sta, *psta; */ struct rtw_ieee80211_ht_cap *pht_capie; struct ieee80211_ht_addt_info *pht_addtinfo; - /* struct recv_reorder_ctrl *preorder_ctrl; */ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; - /* struct recv_priv *precvpriv = &padapter->recvpriv; */ struct registry_priv *pregistrypriv = &padapter->registrypriv; /* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -5526,7 +4414,7 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) /* todo: */ } - if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_40M)) { if (channel > 14) { if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) cbw40_enable = 1; @@ -5543,7 +4431,8 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) int i; u8 rx_nss = 0; - rx_nss = GET_HAL_RX_NSS(padapter); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); + /* update the MCS set */ for (i = 0; i < 16; i++) @@ -5556,7 +4445,7 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) break; case 2: #ifdef CONFIG_DISABLE_MCS13TO15 - if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) + if (pmlmeext->chandef.bw == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); else #endif @@ -5574,20 +4463,21 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) /* switch to the 40M Hz mode accoring to the AP */ /* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */ + /* Secondary Channel Offset */ switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) { - case EXTCHNL_OFFSET_UPPER: - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + case IEEE80211_SCA: + pmlmeext->chandef.offset = CHAN_OFFSET_UPPER; break; - case EXTCHNL_OFFSET_LOWER: - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + case IEEE80211_SCB: + pmlmeext->chandef.offset = CHAN_OFFSET_LOWER; break; default: - pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmlmeext->chandef.bw = CHANNEL_WIDTH_20; + pmlmeext->chandef.offset = CHAN_OFFSET_NO_EXT; RTW_INFO("%s : ch offset is not assigned for HT40 mod , update cur_bwmode=%u, cur_ch_offset=%u\n", - __func__, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + __func__, pmlmeext->chandef.bw, pmlmeext->chandef.offset); break; } } @@ -5647,6 +4537,7 @@ void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitfra #ifdef CONFIG_80211N_HT static u8 rtw_issue_addbareq_check(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy) { + struct registry_priv *pregpriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct registry_priv *pregistry = &padapter->registrypriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -5655,6 +4546,9 @@ static u8 rtw_issue_addbareq_check(_adapter *padapter, struct xmit_frame *pxmitf if (bmcst) return _FALSE; + if (pregpriv->wifi_spec == 1) + return _TRUE; + if (pregistry->tx_quick_addba_req == 0) { if ((issue_when_busy == _TRUE) && (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE)) return _FALSE; @@ -5715,38 +4609,45 @@ void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u } #endif /* CONFIG_80211N_HT */ -void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) +void rtw_append_extended_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; #ifdef CONFIG_80211AC_VHT struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; #endif /* CONFIG_80211AC_VHT */ - u8 cap_content[8] = { 0 }; - u8 *pframe; - u8 null_content[8] = {0}; + u8 *ext_cap_data = pmlmepriv->ext_capab_ie_data; + u8 *ext_cap_data_len = &(pmlmepriv->ext_capab_ie_len); if (phtpriv->bss_coexist) - SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1); + rtw_add_ext_cap_info(ext_cap_data, ext_cap_data_len, BSS_COEXT); #ifdef CONFIG_80211AC_VHT if (pvhtpriv->vht_option) - SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1); + rtw_add_ext_cap_info(ext_cap_data, ext_cap_data_len, OP_MODE_NOTIFICATION); #endif /* CONFIG_80211AC_VHT */ #ifdef CONFIG_RTW_WNM - rtw_wnm_set_ext_cap_btm(cap_content, 1); + rtw_add_ext_cap_info(ext_cap_data, ext_cap_data_len, BSS_TRANSITION); #endif #ifdef CONFIG_RTW_MBO - rtw_mbo_set_ext_cap_internw(cap_content, 1); + rtw_add_ext_cap_info(ext_cap_data, ext_cap_data_len, INTERWORKING); +#endif + +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ + +#ifdef CONFIG_STA_MULTIPLE_BSSID + rtw_add_ext_cap_info(ext_cap_data, ext_cap_data_len, MULTI_BSSID); #endif + /* From 802.11 specification,if a STA does not support any of capabilities defined in the Extended Capabilities element, then the STA is not required to transmit the Extended Capabilities element. */ - if (_FALSE == _rtw_memcmp(cap_content, null_content, 8)) - pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len); + rtw_update_ext_cap_ie(ext_cap_data, *ext_cap_data_len, out_ie, pout_len, _BEACON_IE_OFFSET_); } #endif @@ -5771,12 +4672,11 @@ inline u8 rtw_to_roam(_adapter *adapter) void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) { - _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); _rtw_roaming(padapter, tgt_network); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) { @@ -5809,7 +4709,7 @@ void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) else { RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__); #ifdef CONFIG_RTW_80211R - rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + /* rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); */ rtw_ft_reset_status(padapter); #endif rtw_indicate_disconnect(padapter, 0, _FALSE); @@ -5834,7 +4734,7 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) else allowed_bw = REGSTY_BW_5G(regsty); - allowed_bw = hal_largest_bw(adapter, allowed_bw); + allowed_bw = rtw_hw_largest_bw(adapter_to_dvobj(adapter), allowed_bw); if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80) *req_bw = CHANNEL_WIDTH_80; @@ -5842,7 +4742,7 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) *req_bw = CHANNEL_WIDTH_40; else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) { *req_bw = CHANNEL_WIDTH_20; - *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *req_offset = CHAN_OFFSET_NO_EXT; } else return _FALSE; @@ -5854,7 +4754,7 @@ sint rtw_linked_check(_adapter *padapter) if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter) || MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter) ) { - if (padapter->stapriv.asoc_sta_count > 2) + if (padapter->stapriv.asoc_sta_count > 1) return _TRUE; } else { /* Station mode */ @@ -5866,29 +4766,33 @@ sint rtw_linked_check(_adapter *padapter) /*#define DBG_ADAPTER_STATE_CHK*/ u8 rtw_is_adapter_up(_adapter *padapter) { + struct dvobj_priv *dvobj; + if (padapter == NULL) return _FALSE; - if (RTW_CANNOT_RUN(padapter)) { + dvobj = adapter_to_dvobj(padapter); + + if (RTW_CANNOT_RUN(dvobj)) { #ifdef DBG_ADAPTER_STATE_CHK RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n" , FUNC_ADPT_ARG(padapter) - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False"); #endif return _FALSE; } - if (!rtw_is_hw_init_completed(padapter)) { + if (padapter->netif_up == _FALSE) { #ifdef DBG_ADAPTER_STATE_CHK - RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO(FUNC_ADPT_FMT " FALSE -(netif_up == _FALSE)\n", FUNC_ADPT_ARG(padapter)); #endif return _FALSE; } - if (padapter->bup == _FALSE) { + if (padapter->phl_role == NULL) { #ifdef DBG_ADAPTER_STATE_CHK - RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO(FUNC_ADPT_FMT " FALSE -(phl_role == NULL)\n", FUNC_ADPT_ARG(padapter)); #endif return _FALSE; } @@ -5976,3 +4880,1251 @@ void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx) , MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp))); } +#ifdef CONFIG_STA_CMD_DISPR +/* software setting top half for connect abort */ +static void _connect_abort_sw_top_half(struct _ADAPTER *a) +{ + cancel_link_timer(&a->mlmeextpriv); + cancel_assoc_timer(&a->mlmepriv); + a->mlmeextpriv.join_abort = 1; +} + +/* software setting bottom half for connect abort */ +static void _connect_abort_sw_bottom_half(struct _ADAPTER *a) +{ + /* ref: rtw_joinbss_event_prehandle(), join_res == -4 */ + _clr_fwstate_(&a->mlmepriv, WIFI_UNDER_LINKING); + rtw_reset_securitypriv(a); + a->mlmeextpriv.join_abort = 0; +} + +/* + * _connect_disconncet_hw - Handle hardware part of connect abort and fail + * @a: struct _ADAPTER * + * + * Handle hardware part of connect fail. + * Most implement is reference from bottom half of rtw_joinbss_event_callback() + * with join_res < 0. + * + * Reference functions: + * 1. rtw_joinbss_event_callback() + * 2. rtw_set_hw_after_join(a, -1) + * 3. rtw_hw_connect_abort() + */ +static void _connect_disconnect_hw(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + void *phl; + u8 *mac; + struct sta_info *sta; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + /* ref: rtw_set_hw_after_join(a, -1) */ + mac = (u8*)a->mlmeextpriv.mlmext_info.network.MacAddress; + sta = rtw_get_stainfo(&a->stapriv, mac); + if (!sta) { + RTW_ERR(FUNC_ADPT_FMT ": stainfo(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(a), MAC_ARG(mac)); + return; + } + + /* bottom half of rtw_hw_connect_abort() - start */ + rtw_phl_chanctx_del(phl, a->phl_role, NULL); + /* restore original union ch */ + rtw_join_done_chk_ch(a, -1); + /* free connecting AP sta info */ + rtw_free_stainfo(a, sta); + rtw_init_self_stainfo(a); + /* bottom half of rtw_hw_connect_abort() - end */ + + /* bottom half of rtw_joinbss_event_callback() */ + rtw_mi_os_xmit_schedule(a); +} + +static void _connect_abort_notify_cb(void *priv, struct phl_msg *msg) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": connect_st=%u\n", + FUNC_ADPT_ARG(a), a->connect_state); + + _connect_disconnect_hw(a); + _connect_abort_sw_bottom_half(a); + + _rtw_spinlock(&a->connect_st_lock); + if ((a->connect_state != CONNECT_ST_ACQUIRED) || !a->connect_abort) { + RTW_ERR(FUNC_ADPT_FMT ": connect_st=%u, abort is %s !\n", + FUNC_ADPT_ARG(a), a->connect_state, + a->connect_abort?"true":"false"); + } else { + a->connect_state = CONNECT_ST_IDLE; + a->connect_abort = false; + } + _rtw_spinunlock(&a->connect_st_lock); +} + +static enum rtw_phl_status _connect_abort_notify(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status status; + + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT); + msg.band_idx = a->phl_role->hw_band; + msg.rsvd[0] = (u8*)a->phl_role; + + attr.opt = MSG_OPT_SEND_IN_ABORT; + attr.completion.completion = _connect_abort_notify_cb; + attr.completion.priv = a; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + + return status; +} + +static void _connect_swch_done_notify_cb(void *priv, struct phl_msg *msg) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": connect_st=%u\n", + FUNC_ADPT_ARG(a), a->connect_state); + + if (msg->inbuf) { + rtw_vmfree(msg->inbuf, msg->inlen); + msg->inbuf = NULL; + } +} + +static enum rtw_phl_status _connect_swch_done_notify(struct _ADAPTER *a, + struct rtw_chan_def *chandef) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u8 *info = NULL; + enum rtw_phl_status status; + + + info = rtw_vmalloc(sizeof(struct rtw_chan_def)); + if (!info) { + RTW_ERR(FUNC_ADPT_FMT ": Allocate msg hub buffer fail!\n", + FUNC_ADPT_ARG(a)); + return RTW_PHL_STATUS_RESOURCE; + } + _rtw_memcpy(info, chandef, sizeof(struct rtw_chan_def)); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SWCH_DONE); + msg.band_idx = a->phl_role->hw_band; + msg.inbuf = info; + msg.inlen = sizeof(struct rtw_chan_def); + + attr.completion.completion = _connect_swch_done_notify_cb; + attr.completion.priv = a; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + rtw_vmfree(info, sizeof(struct rtw_chan_def)); + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + } + + return status; +} + +static void _connect_cmd_done(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + enum rtw_phl_status status; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + if (!a->connect_token){ + RTW_ERR(FUNC_ADPT_FMT ": token is NULL!\n", FUNC_ADPT_ARG(a)); + return; + } + + _rtw_spinlock(&a->connect_st_lock); + status = rtw_phl_free_cmd_token(GET_PHL_INFO(d), + role->hw_band, &a->connect_token); + a->connect_token = 0; + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": free_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + a->connect_state = CONNECT_ST_IDLE; + a->connect_abort = false; + _rtw_spinunlock(&a->connect_st_lock); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); +} + +static enum phl_mdl_ret_code _connect_acquired(void* dispr, void *priv) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + struct dvobj_priv *d = adapter_to_dvobj(a); + struct _WLAN_BSSID_EX *network = &a->mlmeextpriv.mlmext_info.network; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + _rtw_spinlock(&a->connect_st_lock); + if (a->connect_state != CONNECT_ST_REQUESTING) + RTW_ERR(FUNC_ADPT_FMT ": connect_st=%u, not requesting?!\n", + FUNC_ADPT_ARG(a), a->connect_state); + a->connect_state = CONNECT_ST_ACQUIRED; + _rtw_spinunlock(&a->connect_st_lock); + + /*rtw_hw_prepare_connect(a, NULL, network->MacAddress);*/ + rtw_phl_connect_prepare(GET_PHL_INFO(d), a->phl_role, + network->MacAddress); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _connect_abort(void* dispr, void *priv) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + bool inner_abort = false; + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + _rtw_spinlock(&a->connect_st_lock); + RTW_INFO(FUNC_ADPT_FMT ": connect_st=%u, abort is %s\n", + FUNC_ADPT_ARG(a), a->connect_state, + a->connect_abort?"true":"false"); + if (a->connect_state == CONNECT_ST_IDLE) { + _rtw_spinunlock(&a->connect_st_lock); + return MDL_RET_SUCCESS; + } + if (!a->connect_abort) { + RTW_INFO(FUNC_ADPT_FMT ": framework asking abort!\n", + FUNC_ADPT_ARG(a)); + a->connect_abort = true; + inner_abort = true; + } + _rtw_spinunlock(&a->connect_st_lock); + + _connect_abort_sw_top_half(a); + if (inner_abort) { + /* ref: rtw_join_timeout_handler() */ + _rtw_spinlock_bh(&a->mlmepriv.lock); + a->mlmepriv.join_status = WLAN_STATUS_UNSPECIFIED_FAILURE; + rtw_indicate_disconnect(a, a->mlmepriv.join_status, _FALSE); +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_indicate_disconnect(a, a->mlmepriv.join_status, _FALSE); +#endif /* CONFIG_IOCTL_CFG80211 */ + a->mlmepriv.join_status = 0; + _rtw_spinunlock_bh(&a->mlmepriv.lock); + } + + if (a->connect_state == CONNECT_ST_ACQUIRED) + phl_status = _connect_abort_notify(a); + a->connect_token = 0; /* framework will free this token later */ + if (phl_status != RTW_PHL_STATUS_SUCCESS) { + /* No callback function, everything should be done here */ + _connect_abort_sw_bottom_half(a); + _rtw_spinlock(&a->connect_st_lock); + a->connect_state = CONNECT_ST_IDLE; + a->connect_abort = false; + _rtw_spinunlock(&a->connect_st_lock); + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _connect_msg_hdlr(void* dispr, void* priv, + struct phl_msg* msg) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = NULL; + struct _WLAN_BSSID_EX *network = &a->mlmeextpriv.mlmext_info.network; + struct sta_info *sta = NULL; + u8 u_ch; + enum channel_width u_bw; + enum chan_offset u_offset; + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status status; + enum phl_mdl_ret_code mdl_err; + int err; + u32 res; + + + RTW_DBG(FUNC_ADPT_FMT ": + msg_id=0x%08x\n", + FUNC_ADPT_ARG(a), msg->msg_id); + + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_CONNECT) { + RTW_INFO(FUNC_ADPT_FMT ": Message is not from connect module, " + "skip msg_id=0x%08x\n", FUNC_ADPT_ARG(a), msg->msg_id); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return MDL_RET_IGNORE; + } + + if (IS_MSG_FAIL(msg->msg_id)) { + RTW_WARN(FUNC_ADPT_FMT ": cmd dispatcher notify cmd failure on " + "msg_id=0x%08x\n", FUNC_ADPT_ARG(a), msg->msg_id); + if (MSG_EVT_ID_FIELD(msg->msg_id) != MSG_EVT_DISCONNECT) + goto send_disconnect; + } + + role = a->phl_role; + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_CONNECT); + nextmsg.band_idx = role->hw_band; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_CONNECT_START: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_CONNECT_START\n", + FUNC_ADPT_ARG(a)); + + /* ref: top half of rtw_join_cmd_hdl() */ + + sta = rtw_get_stainfo(&a->stapriv, a->phl_role->mac_addr); + rtw_free_stainfo(a, sta); + sta = rtw_alloc_stainfo(&a->stapriv, network->MacAddress); + if (sta == NULL) { + RTW_ERR(FUNC_ADPT_FMT ": alloc sta " MAC_FMT " fail!\n", + FUNC_ADPT_ARG(a), MAC_ARG(network->MacAddress)); + rtw_init_self_stainfo(a); + goto send_disconnect; + } + + /* check channel, bandwidth, offset and switch */ + u_ch = a->mlmeextpriv.chandef.chan; + u_bw = a->mlmeextpriv.chandef.bw; + u_offset = a->mlmeextpriv.chandef.offset; + if (!rtw_phl_chanctx_add(GET_PHL_INFO(d), role, + &u_ch, &u_bw, &u_offset)) + goto send_disconnect; + + rtw_hw_update_chan_def(a); + rtw_mi_update_union_chan_inf(a, u_ch, (u8)u_offset, (u8)u_bw); + +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_antenna_select_cmd(a, network->PhyInfo.Optimum_antenna, _FALSE); +#endif + + #ifdef CONFIG_80211D + rtw_joinbss_update_regulatory(a, network); + #endif + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SWCH_START); + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &nextmsg, &attr, NULL); + break; + + case MSG_EVT_SWCH_START: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_SWCH_START\n", + FUNC_ADPT_ARG(a)); + if (!role) { + RTW_ERR(FUNC_ADPT_FMT ": role == NULL\n", + FUNC_ADPT_ARG(a)); + break; + } + + /* ref: bottom half of rtw_join_cmd_hdl() */ + RTW_DBG(FUNC_ADPT_FMT ": Switch to channel before link: " + "chan(%d), bw(%d), offset(%d)\n", + FUNC_ADPT_ARG(a), + d->iface_state.union_ch, d->iface_state.union_bw, + d->iface_state.union_offset); + set_channel_bwmode(a, d->iface_state.union_ch, + d->iface_state.union_offset, + d->iface_state.union_bw, _TRUE); + + status = _connect_swch_done_notify(a, &role->chandef); + break; + + case MSG_EVT_SWCH_DONE: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_SWCH_DONE\n", + FUNC_ADPT_ARG(a)); + + /* ref: last part of rtw_join_cmd_hdl() */ + cancel_link_timer(&a->mlmeextpriv); + start_clnt_join(a); + + break; + + case MSG_EVT_CONNECT_LINKED: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_CONNECT_LINKED\n", + FUNC_ADPT_ARG(a)); + + /* ref: top half of rtw_joinbss_event_callback() */ + err = rtw_set_hw_after_join(a, 0); + if (err) { + RTW_ERR(FUNC_ADPT_FMT ": set hardware fail(%d) during " + "connecting!\n", + FUNC_ADPT_ARG(a), err); + goto send_disconnect; + } + + break; + + case MSG_EVT_CONNECT_END: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_CONNECT_END\n", + FUNC_ADPT_ARG(a)); + + /* ref: bottom half of rtw_set_hw_after_join() */ + sta = rtw_get_stainfo(&a->stapriv, network->MacAddress); + if (sta) + rtw_xmit_queue_clear(sta); + else + RTW_ERR(FUNC_ADPT_FMT ": stainfo(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(a), MAC_ARG(network->MacAddress)); + + /* ref: bottom half of rtw_joinbss_event_callback() */ + rtw_mi_os_xmit_schedule(a); + + _connect_cmd_done(a); +#ifdef CONFIG_LAYER2_ROAMING + if (a->securitypriv.dot11PrivacyAlgrthm == _NO_PRIVACY_) + dequeuq_roam_pkt(a); +#endif + break; + + case MSG_EVT_DISCONNECT_PREPARE: + RTW_WARN(FUNC_ADPT_FMT ": MSG_EVT_DISCONNECT_PREPARE\n", + FUNC_ADPT_ARG(a)); + + /* STA connect fail case, top half */ + + /* top half of rtw_joinbss_event_callback() */ + err = rtw_set_hw_after_join(a, -1); + if (err) { + RTW_ERR(FUNC_ADPT_FMT ": set hardware fail(%d) during " + "connect abort!\n", + FUNC_ADPT_ARG(a), err); + } + + rtw_phl_disconnect(GET_PHL_INFO(d), a->phl_role, false); + + break; + + case MSG_EVT_DISCONNECT: + RTW_WARN(FUNC_ADPT_FMT ": MSG_EVT_DISCONNECT\n", + FUNC_ADPT_ARG(a)); + + /* STA connect fail case, bottom half */ + _connect_disconnect_hw(a); + + _connect_cmd_done(a); + break; + + default: + break; + } + + goto exit; + +send_disconnect: + /* + * Trigger software handle and notify OS by rtw_joinbss_event_prehandle() + * Trigger hardware handle by sending MSG_EVT_DISCONNECT + */ + res = report_join_res(a, -4, WLAN_STATUS_UNSPECIFIED_FAILURE); + if (res != _SUCCESS) { + /* + * Fail to send MSG_EVT_DISCONNECT_PREPARE, do jobs in + * MSG_EVT_DISCONNECT_PREPARE and MSG_EVT_DISCONNECT directly + * here. + */ + + /* ref: rtw_set_hw_after_join(a, -1) */ + a->mlmepriv.wpa_phase = _FALSE; + sta = rtw_get_stainfo(&a->stapriv, network->MacAddress); + if (sta) { + /* rtw_hw_connect_abort(a, sta) */ + rtw_hw_del_all_key(a, sta, PHL_CMD_DIRECTLY, 0); + status = rtw_phl_cmd_update_media_status( + GET_PHL_INFO(d), + sta->phl_sta, NULL, false, + PHL_CMD_DIRECTLY, 0); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR(FUNC_ADPT_FMT ": update media status " + "fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + } + _connect_disconnect_hw(a); + } else { + RTW_ERR(FUNC_ADPT_FMT ": stainfo(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(a), MAC_ARG(network->MacAddress)); + } + + _connect_cmd_done(a); + } + +exit: + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _connect_set_info(void* dispr, void* priv, + struct phl_module_op_info* info) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + + return MDL_RET_IGNORE; +} + +static enum phl_mdl_ret_code _connect_query_info(void* dispr, void* priv, + struct phl_module_op_info* info) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + switch (info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8*)a->phl_role; + ret = MDL_RET_SUCCESS; + break; + +#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + case FG_REQ_OP_GET_ISSUE_NULL_OPS: + { + u8 (*issue_null)(void *, u8, bool) = scan_issu_null_data_cb; + info->outbuf = (u8 *)issue_null; + info->outlen = 0; + ret = MDL_RET_SUCCESS; + } + break; +#endif + + default: + break; + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return ret; +} + +enum rtw_phl_status rtw_connect_cmd(struct _ADAPTER *a, + struct _WLAN_BSSID_EX *network) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + struct rtw_chan_def *chdef; + struct mi_state mstate = {0}; + struct phl_cmd_token_req *cmd_req; + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + + + RTW_DBG(FUNC_ADPT_FMT ": st=%u\n", + FUNC_ADPT_ARG(a), a->connect_state); + + _rtw_spinlock(&a->connect_st_lock); + + if (a->connect_state != CONNECT_ST_IDLE) { + status = RTW_PHL_STATUS_SUCCESS; + RTW_WARN(FUNC_ADPT_FMT ": connect is on going...\n", + FUNC_ADPT_ARG(a)); + goto exit; + } + + if ((network->IELength > MAX_IE_SZ) || (network->IELength < 2)) { + status = RTW_PHL_STATUS_INVALID_PARAM; + RTW_ERR(FUNC_ADPT_FMT ": invalid IE length(%u)\n", + FUNC_ADPT_ARG(a), network->IELength); + goto exit; + } + + /* ref: top half of rtw_join_cmd_hdl(), software only */ + /* Todo: disconnect before connecting */ + /*set_hw_before_join(a);*/ + + /* Update HT/VHT/HE CAP and chan/bw/offset to a->mlmeextpriv.mlmext_info.network */ + update_join_info(a, network); + + /* check channel, bandwidth, offset and switch */ + chdef = &a->mlmeextpriv.chandef; + if (!rtw_phl_chanctx_chk(GET_PHL_INFO(d), role, + chdef->chan, chdef->bw, chdef->offset)) { + /* ref: not group case in rtw_chk_start_clnt_join() */ + rtw_mi_status_no_self(a, &mstate); + RTW_WARN(FUNC_ADPT_FMT ": channel group fail! ld_sta_num:%u, " + "ap_num:%u, mesh_num:%u\n", + FUNC_ADPT_ARG(a), MSTATE_STA_LD_NUM(&mstate), + MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); + if ((MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + + MSTATE_MESH_LD_NUM(&mstate)) >= 4) { + status = RTW_PHL_STATUS_RESOURCE; + goto exit; + } + rtw_mi_buddy_disconnect(a); + } + + cmd_req = &a->connect_req; + cmd_req->role = role; + status = rtw_phl_add_cmd_token_req(GET_PHL_INFO(d), + role->hw_band, + cmd_req, &a->connect_token); + if ((status != RTW_PHL_STATUS_SUCCESS) + && (status != RTW_PHL_STATUS_PENDING)) { + RTW_ERR(FUNC_ADPT_FMT ": add_cmd_token_req fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + goto exit; + } + + a->connect_state = CONNECT_ST_REQUESTING; + status = RTW_PHL_STATUS_SUCCESS; + +exit: + _rtw_spinunlock(&a->connect_st_lock); + + RTW_DBG(FUNC_ADPT_FMT ": - st=%u ret=%u\n", + FUNC_ADPT_ARG(a), a->connect_state, status); + return status; +} + +void rtw_connect_abort(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + enum rtw_phl_status status; + + + RTW_WARN(FUNC_ADPT_FMT ": connect_st=%u, abort=%u\n", + FUNC_ADPT_ARG(a), a->connect_state, a->connect_abort); + if (a->connect_state == CONNECT_ST_NOT_READY) + return; + + _rtw_spinlock(&a->connect_st_lock); + if ((a->connect_state == CONNECT_ST_IDLE) || a->connect_abort) { + _rtw_spinunlock(&a->connect_st_lock); + return; + } + a->mlmepriv.wpa_phase = _FALSE; + a->connect_abort = true; + _rtw_spinunlock(&a->connect_st_lock); + + status = rtw_phl_cancel_cmd_token(GET_PHL_INFO(d), + role->hw_band, + &a->connect_token); + a->connect_token = 0; + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR(FUNC_ADPT_FMT ": cancel_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + /* Cancel fail, and something needed to be handled by self */ + /* Release connect resource (software) */ + _connect_abort_sw_top_half(a); + _connect_abort_sw_bottom_half(a); + + _rtw_spinlock(&a->connect_st_lock); + a->connect_state = CONNECT_ST_IDLE; + a->connect_abort = false; + _rtw_spinunlock(&a->connect_st_lock); + } +} + +#define _CONNECT_ABORT_TO_ 5000 /* unit: ms */ +/** + * rtw_connect_abort_wait() - Abort connect FG and wait to finish + * @a pointer of struct _ADAPTER + * + * Send cancel cmd to framework and wait connect FG to stop. + * + * Return 0 for connect FG already stopped, -1 for sending cancel command + * fail, or -2 for waiting connect FG stop timeout. + */ +int rtw_connect_abort_wait(struct _ADAPTER *a) +{ + u32 timeout = _CONNECT_ABORT_TO_; + systime start_t; + u32 pass_t = 0; + u32 msg_i; /* message interval */ + u32 msg_t = 0; /* next time point to print message */ + int err = 0; + + + if (a->connect_state == CONNECT_ST_NOT_READY) + return err; + + msg_i = timeout / 10; /* at most print 10 msg in whole waiting time */ + if (!msg_i) + msg_i = 1; + + _rtw_spinlock(&a->connect_st_lock); + start_t = rtw_get_current_time(); + while (a->connect_state != CONNECT_ST_IDLE) { + if (pass_t >= msg_t) { + RTW_INFO(FUNC_ADPT_FMT ": connect st=%u, %u ms/%u pass...\n", + FUNC_ADPT_ARG(a), a->connect_state, pass_t, timeout); + msg_t += msg_i; + } + _rtw_spinunlock(&a->connect_st_lock); + + pass_t = rtw_get_passing_time_ms(start_t); + if (pass_t > timeout) { + RTW_ERR(FUNC_ADPT_FMT ": Timeout, fail to abort connect!" + " used:%u > max:%u ms\n", + FUNC_ADPT_ARG(a), pass_t, timeout); + err = -2; /* Timeout */ + _rtw_spinlock(&a->connect_st_lock); + break; + } + rtw_connect_abort(a); + rtw_msleep_os(1); + + _rtw_spinlock(&a->connect_st_lock); + } + _rtw_spinunlock(&a->connect_st_lock); + + return err; +} + +void rtw_connect_req_free(struct _ADAPTER *a) +{ + if (a->connect_state == CONNECT_ST_NOT_READY) + return; + + rtw_connect_abort_wait(a); + + _rtw_spinlock_free(&a->connect_st_lock); + /* Terminate state, lock protection is not necessary */ + a->connect_state = CONNECT_ST_NOT_READY; +} + +void rtw_connect_req_init(struct _ADAPTER *a) +{ + struct phl_cmd_token_req *req; + + + if (a->connect_state != CONNECT_ST_NOT_READY) { + RTW_WARN(FUNC_ADPT_FMT ": connect_st=%u, not NOT_READY?!\n", + FUNC_ADPT_ARG(a), a->connect_state); + return; + } + + _rtw_spinlock_init(&a->connect_st_lock); + + req = &a->connect_req; + req->module_id = PHL_FG_MDL_CONNECT; + req->priv = a; + req->role = NULL; /* a->phl_role, but role will change by time */ + req->acquired = _connect_acquired; + req->abort = _connect_abort; + req->msg_hdlr = _connect_msg_hdlr; + req->set_info = _connect_set_info; + req->query_info = _connect_query_info; + + /* initialize state, lock protection is not necessary */ + a->connect_state = CONNECT_ST_IDLE; + a->connect_abort = false; +} + +enum rtw_phl_status rtw_connect_disconnect_prepare(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status status; + + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT_PREPARE); + msg.band_idx = a->phl_role->hw_band; + msg.rsvd[0] = (u8*)a->phl_role; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + + return status; +} + +static enum rtw_phl_status _disconnect_done_notify(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_wifi_role_t *wrole = a->phl_role; + enum rtw_phl_status status; + + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_DISCONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT); + msg.band_idx = wrole->hw_band; + msg.rsvd[0] = (u8*)wrole; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": send_msg_to_dispr fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + + return status; +} + +static void _disconnect_free_cmdobj(struct _ADAPTER *a) +{ + struct cmd_obj *cmd; + + + cmd = a->discon_cmd; + if (!cmd) + return; + + _rtw_spinlock(&a->disconnect_lock); + + a->discon_cmd = NULL; + + if (cmd->sctx) { + if (cmd->res == H2C_SUCCESS) + rtw_sctx_done(&cmd->sctx); + else + rtw_sctx_done_err(&cmd->sctx, RTW_SCTX_DONE_CMD_ERROR); + } + + _rtw_spinunlock(&a->disconnect_lock); + + rtw_free_cmd_obj(cmd); +} + +static void _disconnect_cmd_done(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + enum rtw_phl_status status; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + _rtw_spinlock(&a->disconnect_lock); + /* avoid to race with rtw_disconnect_abort() */ + + if (!a->disconnect_token) { + RTW_WARN(FUNC_ADPT_FMT ": Others try to stop disconnect!\n", + FUNC_ADPT_ARG(a)); + _rtw_spinunlock(&a->disconnect_lock); + return; + } + + status = rtw_phl_free_cmd_token(GET_PHL_INFO(d), + role->hw_band, &a->disconnect_token); + if (status != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": free_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + a->disconnect_token = 0; + + _rtw_spinunlock(&a->disconnect_lock); + + _disconnect_free_cmdobj(a); +} + +static enum phl_mdl_ret_code _disconnect_acquired(void* dispr, void *priv) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + struct dvobj_priv *d = adapter_to_dvobj(a); + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + rtw_phl_disconnect(GET_PHL_INFO(d), a->phl_role, true); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _disconnect_abort(void* dispr, void *priv) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + /* + * Framework will free disconnect token automatically after abort, + * so do all in _disconnect_cmd_done() besides rtw_phl_free_cmd_token(). + * ref: _disconnect_cmd_done() + */ + if (a->disconnect_token) { + RTW_WARN(FUNC_ADPT_FMT ": framework asking abort!\n", + FUNC_ADPT_ARG(a)); + a->disconnect_token = 0; + } + + _disconnect_free_cmdobj(a); + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _disconnect_msg_hdlr(void* dispr, void* priv, + struct phl_msg* msg) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + struct disconnect_parm *discon; + struct stadel_event *stadel; + struct _WLAN_BSSID_EX *network; + u8 is_issue_deauth; + u32 retry = 0; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + + RTW_DBG(FUNC_ADPT_FMT ": + msg_id=0x%08x\n", + FUNC_ADPT_ARG(a), msg->msg_id); + + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_DISCONNECT) { + RTW_INFO(FUNC_ADPT_FMT ": Message is not from disconnect module, " + "skip msg_id=0x%08x\n", FUNC_ADPT_ARG(a), msg->msg_id); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return MDL_RET_IGNORE; + } + + /* Whether msg fail or not */ + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_DISCONNECT_PREPARE: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_DISCONNECT_PREPARE\n", + FUNC_ADPT_ARG(a)); + + /* + * ref: Top half of disconnect_hdl(), before and including + * rtw_mlmeext_disconnect(). + * Note: The bottom half, after rtw_mlmeext_disconnect(), + * would be put to case MSG_EVT_DISCONNECT. + */ + + if ((a->discon_cmd->cmdcode == CMD_SET_MLME_EVT) +#if CONFIG_DFS + || IS_RADAR_DETECTED(adapter_to_rfctl(a)) + || adapter_to_rfctl(a)->csa_chandef.chan +#endif + ) + is_issue_deauth = 0; + else + is_issue_deauth = 1; + + if (is_issue_deauth) { +#ifdef CONFIG_PLATFORM_ROCKCHIPS + /* + * To avoid connecting to AP fail during resume process, + * change retry count from 5 to 1 + */ + retry = 1; +#else /* !CONFIG_PLATFORM_ROCKCHIPS */ + discon = (struct disconnect_parm*)a->discon_cmd->parmbuf; + retry = discon->deauth_timeout_ms / 100; +#endif /* !CONFIG_PLATFORM_ROCKCHIPS */ + + network = &a->mlmeextpriv.mlmext_info.network; + issue_deauth_ex(a, network->MacAddress, + WLAN_REASON_DEAUTH_LEAVING, + retry, 100); + } + + rtw_mlmeext_disconnect(a); + + status = _disconnect_done_notify(a); + if (status == RTW_PHL_STATUS_SUCCESS) + break; + /* fall through */ + + case MSG_EVT_DISCONNECT: + RTW_DBG(FUNC_ADPT_FMT ": MSG_EVT_DISCONNECT\n", + FUNC_ADPT_ARG(a)); + + + if (a->discon_cmd->cmdcode == CMD_SET_MLME_EVT) { + /* EVT_DEL_STA case */ + /* ref: bottom half of rtw_stadel_event_callback() */ + stadel = (struct stadel_event*)(a->discon_cmd->parmbuf + + sizeof(struct rtw_evt_header)); + _stadel_posthandle_sta(a, stadel); + } else { + rtw_free_assoc_resources(a, _TRUE); + } + + rtw_phl_disconnected_resume_hdlr(GET_PHL_INFO(adapter_to_dvobj(a)), + a->phl_role); + _disconnect_cmd_done(a); + break; + + default: + break; + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _disconnect_set_info(void* dispr, void* priv, + struct phl_module_op_info* info) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return MDL_RET_IGNORE; +} + +static enum phl_mdl_ret_code _disconnect_query_info(void* dispr, void* priv, + struct phl_module_op_info* info) +{ + struct _ADAPTER *a = (struct _ADAPTER *)priv; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + switch (info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8 *)a->phl_role; + ret = MDL_RET_SUCCESS; + break; + default: + break; + } + + RTW_DBG(FUNC_ADPT_FMT ": -\n", FUNC_ADPT_ARG(a)); + return ret; +} + +enum rtw_phl_status rtw_disconnect_cmd(struct _ADAPTER *a, struct cmd_obj *pcmd) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + struct rtw_evt_header *hdr; + struct stadel_event *stadel; + struct sta_info *sta; + struct phl_cmd_token_req *cmd_req; + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + if (a->disconnect_token) { + RTW_WARN(FUNC_ADPT_FMT ": disconnect is on going...\n", + FUNC_ADPT_ARG(a)); + return RTW_PHL_STATUS_FAILURE; + } + + if (pcmd->cmdcode == CMD_SET_MLME_EVT) { + /* EVT_DEL_STA case */ + /* ref: top half of rtw_stadel_event_callback() */ + hdr = (struct rtw_evt_header*)pcmd->parmbuf; + stadel = (struct stadel_event *)(pcmd->parmbuf + sizeof(*hdr)); + sta = rtw_get_stainfo(&a->stapriv, stadel->macaddr); + if (!sta) { + RTW_ERR(FUNC_ADPT_FMT ": stainfo(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(a), MAC_ARG(stadel->macaddr)); + return RTW_PHL_STATUS_FAILURE; + } + rtw_wfd_st_switch(sta, 0); + sta->hw_decrypted = _FALSE; + } + + a->discon_cmd = pcmd; + cmd_req = &a->disconnect_req; + cmd_req->role = role; + + phl_status = rtw_phl_add_cmd_token_req(GET_PHL_INFO(d), + role->hw_band, + cmd_req, &a->disconnect_token); + if ((phl_status != RTW_PHL_STATUS_SUCCESS) + && (phl_status != RTW_PHL_STATUS_PENDING)) { + RTW_WARN(FUNC_ADPT_FMT ": add_cmd_token_req fail(0x%x)!\n", + FUNC_ADPT_ARG(a), phl_status); + return RTW_PHL_STATUS_FAILURE; + } + + RTW_DBG(FUNC_ADPT_FMT ": - token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + return RTW_PHL_STATUS_SUCCESS; +} + +/* Wait disconnect FG to finish */ +static bool _disconnect_wait(struct _ADAPTER *a, u32 timeout) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + systime start; + u32 pass_t; + u32 msg_i; /* message interval */ + u32 msg_t = 0; /* next time point to print message */ + enum rtw_phl_status status; + bool terminated = false; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + msg_i = timeout / 10; /* at most print 10 msg in whole waiting time */ + if (!msg_i) + msg_i = 1; + start = rtw_get_current_time(); + do { + _rtw_spinlock(&a->disconnect_lock); + pass_t = rtw_get_passing_time_ms(start); + if (!a->discon_cmd) { + _rtw_spinunlock(&a->disconnect_lock); + terminated = true; + break; + } + _rtw_spinunlock(&a->disconnect_lock); + + if (pass_t >= msg_t) { + RTW_DBG(FUNC_ADPT_FMT ": Waiting disconnect FG, %u ms/%u pass...\n", + FUNC_ADPT_ARG(a), pass_t, timeout); + msg_t += msg_i; + } + if (pass_t > timeout) { + RTW_ERR(FUNC_ADPT_FMT ": Timeout! used:%u > max:%u ms\n", + FUNC_ADPT_ARG(a), pass_t, timeout); + break; + } + + rtw_usleep_os(_rtw_systime_to_us(1)); /* sleep 1/HZ sec */ + } while (1); + RTW_DBG(FUNC_ADPT_FMT ": Stop waiting disconnect FG, cost %u ms\n", + FUNC_ADPT_ARG(a), pass_t); + +exit: + RTW_DBG(FUNC_ADPT_FMT ": - %s\n", FUNC_ADPT_ARG(a), terminated?"OK":"Fail!"); + return terminated; +} + +/** + * rtw_disconnect_abort() - Send cmd to abort disconnect FG + * @a pointer of struct _ADAPTER + * + * Send cancel cmd to framework to stop disconnect FG. + * + * Return 0 for sending command ok, 1 for not necessary to send command because + * no disconnect FG exist, or negative status code returned from function + * rtw_phl_cancel_cmd_token(). + */ +static int rtw_disconnect_abort(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + u32 token; + enum rtw_phl_status status; + int err = 0; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + _rtw_spinlock(&a->disconnect_lock); + /* avoid to race with _disconnect_cmd_done() */ + + if (!a->disconnect_token) { + _rtw_spinunlock(&a->disconnect_lock); + err = 1; + goto exit; + } + + token = a->disconnect_token; + status = rtw_phl_cancel_cmd_token(GET_PHL_INFO(d), + role->hw_band, &token); + if (status == RTW_PHL_STATUS_SUCCESS) { + a->disconnect_token = 0; + } else { + err = -status; + RTW_ERR(FUNC_ADPT_FMT ": cancel_cmd_token fail(0x%x)!\n", + FUNC_ADPT_ARG(a), status); + } + + _rtw_spinunlock(&a->disconnect_lock); + +exit: + RTW_DBG(FUNC_ADPT_FMT ": - err=%d\n", FUNC_ADPT_ARG(a), err); + return err; +} + +#define _DISCONNECT_ABORT_TO_ 3000 /* unit: ms */ +/** + * rtw_disconnect_abort_wait() - Abort disconnect FG and wait to finish + * @a pointer of struct _ADAPTER + * + * Send cancel cmd to framework and wait disconnect FG to stop. + * + * Return 0 for disconnect FG already stopped, -1 for sending cancel command + * fail, or -2 for waiting disconnect FG stop timeout. + */ +int rtw_disconnect_abort_wait(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_wifi_role_t *role = a->phl_role; + u32 token; + enum rtw_phl_status status; + int ret, err = 0; + + + RTW_DBG(FUNC_ADPT_FMT ": + token=0x%08x\n", + FUNC_ADPT_ARG(a), a->disconnect_token); + + if (!a->disconnect_token) + goto exit; + + ret = rtw_disconnect_abort(a); + if (ret) { + if (ret < 0) + err = -1; /* Fail to send cancel cmd */ + goto exit; + } + + if (!_disconnect_wait(a, _DISCONNECT_ABORT_TO_)) + err = -2; /* Timeout */ + +exit: + RTW_DBG(FUNC_ADPT_FMT ": - err=%d\n", FUNC_ADPT_ARG(a), err); + return err; +} + +void rtw_disconnect_req_free(struct _ADAPTER *a) +{ + rtw_disconnect_abort_wait(a); + + _rtw_spinlock_free(&a->disconnect_lock); +} + +void rtw_disconnect_req_init(struct _ADAPTER *a) +{ + struct phl_cmd_token_req *req; + + + _rtw_spinlock_init(&a->disconnect_lock); + + req = &a->disconnect_req; + req->module_id = PHL_FG_MDL_DISCONNECT; + req->priv = a; + req->role = NULL; /* a->phl_role, but role will change by time */ + req->acquired = _disconnect_acquired; + req->abort = _disconnect_abort; + req->msg_hdlr = _disconnect_msg_hdlr; + req->set_info = _disconnect_set_info; + req->query_info = _disconnect_query_info; +} +#endif /* CONFIG_STA_CMD_DISPR */ diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index 4d01847..462455c 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_MLME_EXT_C_ #include -#include struct mlme_handler mlme_sta_tbl[] = { {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, @@ -87,6 +86,8 @@ struct action_handler OnAction_tbl[] = { #endif {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, {RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht}, + {RTW_WLAN_CATEGORY_HE, "ACTION_HE", &OnAction_he}, + {RTW_WLAN_CATEGORY_PROTECTED_HE, "ACTION_PROTECTED_HE", &OnAction_protected_he}, {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, #ifdef CONFIG_RTW_TOKEN_BASED_XMIT {RTW_WLAN_CATEGORY_TBTX, "ACTION_TBTX_TOKEN", &OnAction_tbtx_token} @@ -152,7 +153,7 @@ static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { if (rtw_chset_search_ch(channel_set, ch) == -1) continue; -#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT) +#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT) /* CONFIG_80211AX_HE_TODO */ if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8)) continue; @@ -175,169 +176,52 @@ static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set } #if CONFIG_TXPWR_LIMIT -void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl) +bool rtw_rfctl_is_current_txpwr_lmt(struct rf_ctl_t *rfctl, const char *name) { - u8 regd; - struct regd_exc_ent *exc; - struct txpwr_lmt_ent *ent; - _irqL irqL; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - rfctl->regd_name = NULL; - - if (rfctl->txpwr_regd_num == 0) { - RTW_PRINT("there is no any txpwr_regd\n"); - goto release_lock; - } - - /* search from exception mapping */ - exc = _rtw_regd_exc_search(rfctl - , rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL - , rfctl->ChannelPlan); - if (exc) { - u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1; - - if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0) - rfctl->regd_name = regd_str(TXPWR_LMT_NONE); - else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0) - rfctl->regd_name = regd_str(TXPWR_LMT_WW); - else { - ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name); - if (ent) - rfctl->regd_name = ent->regd_name; - } - - RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n" - , has_country ? exc->country[0] : '0' - , has_country ? exc->country[1] : '0' - , exc->domain - , rfctl->regd_name ? "" : " unknown" - , exc->regd_name - ); - if (rfctl->regd_name) - goto release_lock; - } - -#ifdef CONFIG_REGD_SRC_FROM_OS - if (rfctl->regd_src == REGD_SRC_OS) { - if (IS_ALPHA2_WORLDWIDE(rfctl->country_ent->alpha2)) - rfctl->regd_name = regd_str(TXPWR_LMT_WW); - else { - char alpha2[3] = { - rfctl->country_ent->alpha2[0], rfctl->country_ent->alpha2[1], 0}; - - ent = _rtw_txpwr_lmt_get_by_name(rfctl, alpha2); - if (ent) - rfctl->regd_name = ent->regd_name; - } + const char *cur_name; + int band; - if (rfctl->regd_name) { - RTW_PRINT("mapping country:%c%c to regd_name:%s\n" - , rfctl->country_ent->alpha2[0] - , rfctl->country_ent->alpha2[1] - , rfctl->regd_name - ); - goto release_lock; - } - - if (rfctl->ChannelPlan == RTW_CHPLAN_UNSPECIFIED) { - rfctl->regd_name = regd_str(TXPWR_LMT_WW); - RTW_PRINT("mapping unsupported country:%c%c to regd_name:%s\n" - , rfctl->country_ent->alpha2[0] - , rfctl->country_ent->alpha2[1] - , rfctl->regd_name - ); - goto release_lock; - } - } -#endif - - /* follow default channel plan mapping */ - regd = rtw_chplan_get_default_regd(rfctl->ChannelPlan); - if (regd == TXPWR_LMT_NONE) - rfctl->regd_name = regd_str(TXPWR_LMT_NONE); - else if (regd == TXPWR_LMT_WW) - rfctl->regd_name = regd_str(TXPWR_LMT_WW); - else { - ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); - if (ent) - rfctl->regd_name = ent->regd_name; + for (band = 0; band < BAND_MAX; band++) { + cur_name = rtw_phl_get_pw_lmt_regu_type_str(GET_PHL_INFO(rfctl_to_dvobj(rfctl)), band); + if (cur_name && strcmp(name, cur_name) == 0) + return 1; } - RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n" - , rfctl->ChannelPlan - , rfctl->regd_name ? "" : " unknown" - , regd_str(regd) - ); - if (rfctl->regd_name) - goto release_lock; - - switch (regd) { - /* - * To support older chips without new predefined regd: - * - use FCC if IC or CHILE or MEXICO not found - * - use ETSI if KCC or ACMA not found - */ - case TXPWR_LMT_IC: - case TXPWR_LMT_KCC: - case TXPWR_LMT_NCC: - case TXPWR_LMT_ACMA: - case TXPWR_LMT_CHILE: - case TXPWR_LMT_MEXICO: - if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_NCC || regd == TXPWR_LMT_CHILE || regd == TXPWR_LMT_MEXICO) - regd = TXPWR_LMT_FCC; - else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA) - regd = TXPWR_LMT_ETSI; - ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); - if (ent) - rfctl->regd_name = ent->regd_name; - RTW_PRINT("alternate regd_name:%s %s\n" - , regd_str(regd) - , rfctl->regd_name ? "is used" : "not found" - ); - if (rfctl->regd_name) - break; - /* fall through */ - default: - rfctl->regd_name = regd_str(TXPWR_LMT_WW); - RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW)); - break; - }; - -release_lock: - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + return 0; } #endif /* CONFIG_TXPWR_LIMIT */ -int rtw_rfctl_init(_adapter *adapter) +int rtw_rfctl_init(struct dvobj_priv *dvobj) { - struct registry_priv *regsty = adapter_to_regsty(adapter); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); int ret; - _rtw_mutex_init(&rfctl->offch_mutex); + rfctl->user_ChannelPlan = RTW_CHPLAN_UNSPECIFIED; +#if CONFIG_IEEE80211_BAND_6GHZ + rfctl->user_chplan_6g = RTW_CHPLAN_6G_UNSPECIFIED; +#endif -#if CONFIG_TXPWR_LIMIT - _rtw_mutex_init(&rfctl->txpwr_lmt_mutex); - _rtw_init_listhead(&rfctl->reg_exc_list); - _rtw_init_listhead(&rfctl->txpwr_lmt_list); +#ifdef CONFIG_80211D + rfctl->country_ie_slave_en_role = regsty->country_ie_slave_en_role; + rfctl->country_ie_slave_en_ifbmp = regsty->country_ie_slave_en_ifbmp; + rfctl->effected_cisr_id = CONFIG_IFACE_NUMBER; #endif rfctl->ch_sel_within_same_band = 1; + rfctl->last_edcca_mode_op_band = BAND_MAX; + #ifdef CONFIG_DFS_MASTER rfctl->dfs_region_domain = regsty->dfs_region_domain; rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; - rtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl); + rtw_init_timer(&(rfctl->radar_detect_timer), rtw_dfs_rd_timer_hdl, rfctl); #endif #if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT rfctl->dfs_slave_with_rd = 1; #endif - if (regsty->antenna_gain != UNSPECIFIED_MBM) - rfctl->antenna_gain = regsty->antenna_gain; - ret = op_class_pref_init(adapter); if (ret != _SUCCESS) op_class_pref_deinit(adapter); @@ -345,35 +229,197 @@ int rtw_rfctl_init(_adapter *adapter) return ret; } -void rtw_rfctl_deinit(_adapter *adapter) +void rtw_rfctl_deinit(struct dvobj_priv *dvobj) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); _rtw_mutex_free(&rfctl->offch_mutex); -#if CONFIG_TXPWR_LIMIT - rtw_regd_exc_list_free(rfctl); - rtw_txpwr_lmt_list_free(rfctl); - _rtw_mutex_free(&rfctl->txpwr_lmt_mutex); + op_class_pref_deinit(adapter); +} + +/* + * Description: + * Use hardware(efuse), driver parameter(registry) and default channel plan + * to decide which one should be used. + * + * Parameters: + * rfctl pointer of rfctl + * hw_alpha2 country code from HW (efuse/eeprom/mapfile) + * hw_chplan domain code from HW (efuse/eeprom/mapfile) + * hw_chplan_6g 6g domain code from HW (efuse/eeprom/mapfile) + * hw_force_chplan if forcing HW channel plan setting (efuse/eeprom/mapfile) + * will modified tif HW channel plan setting is invlid, will + */ +void rtw_rfctl_decide_init_chplan(struct rf_ctl_t *rfctl, + const char *hw_alpha2, u8 hw_chplan, u8 hw_chplan_6g, u8 hw_force_chplan) +{ + struct registry_priv *regsty; + char *sw_alpha2; + const struct country_chplan *country_ent = NULL; + struct country_chplan ent; + int chplan = -1; + int chplan_6g = -1; + + u8 sw_chplan; + u8 def_chplan = RTW_CHPLAN_WORLDWIDE; /* worldwide, used when HW, SW both invalid */ +#if CONFIG_IEEE80211_BAND_6GHZ + u8 sw_chplan_6g; + u8 def_chplan_6g = RTW_CHPLAN_6G_WORLDWIDE; /* worldwide, used when HW, SW both invalid */ +#endif + + if (hw_alpha2) { + if (rtw_get_chplan_from_country(hw_alpha2, &ent)) { + /* get chplan from hw country code, by pass hw chplan setting */ + country_ent = &ent; + chplan = ent.chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = ent.chplan_6g; + #endif + goto chk_sw_config; + } else + RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(hw_chplan)) + chplan = hw_chplan; + else if (hw_force_chplan == _TRUE) { + RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan); + /* hw infomaton invalid, refer to sw information */ + hw_force_chplan = _FALSE; + } + +#if CONFIG_IEEE80211_BAND_6GHZ + if (rtw_is_channel_plan_6g_valid(hw_chplan_6g)) + chplan_6g = hw_chplan_6g; + else if (hw_force_chplan == _TRUE) { + RTW_PRINT("%s unsupported hw_chplan_6g:0x%02X\n", __func__, hw_chplan_6g); + /* hw infomaton invalid, refer to sw information */ + hw_force_chplan = _FALSE; + } +#endif + +chk_sw_config: + if (hw_force_chplan == _TRUE) + goto done; + + regsty = dvobj_to_regsty(rfctl_to_dvobj(rfctl)); + sw_alpha2 = regsty->alpha2; + sw_chplan = regsty->channel_plan; + #if CONFIG_IEEE80211_BAND_6GHZ + sw_chplan_6g = regsty->channel_plan_6g; + #endif + + if (sw_alpha2 && !IS_ALPHA2_UNSPEC(sw_alpha2)) { + if (IS_ALPHA2_WORLDWIDE(sw_alpha2) + || rtw_get_chplan_from_country(sw_alpha2, &ent) + ) { + /* get chplan from sw country code, by pass sw chplan setting */ + if (IS_ALPHA2_WORLDWIDE(sw_alpha2)) + rtw_get_chplan_worldwide(&ent); + country_ent = &ent; + chplan = ent.chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = ent.chplan_6g; + #endif + goto done; + } else + RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(sw_chplan)) { + /* cancel hw_alpha2 because chplan is specified by sw_chplan */ + country_ent = NULL; + chplan = sw_chplan; + } else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED) + RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan); + +#if CONFIG_IEEE80211_BAND_6GHZ + if (rtw_is_channel_plan_6g_valid(sw_chplan_6g)) { + /* cancel hw_alpha2 because chplan_6g is specified by sw_chplan_6g */ + country_ent = NULL; + chplan_6g = sw_chplan_6g; + } else if (sw_chplan_6g != RTW_CHPLAN_6G_UNSPECIFIED) + RTW_PRINT("%s unsupported sw_chplan_6g:0x%02X\n", __func__, sw_chplan_6g); #endif -#ifdef CONFIG_REGD_SRC_FROM_OS - if (rfctl->regd_src == REGD_SRC_OS) - rtw_mfree((void *)rfctl->country_ent, sizeof(struct country_chplan)); +done: + if (chplan == -1) { + RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan); + chplan = def_chplan; + } else + RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan); + +#if CONFIG_IEEE80211_BAND_6GHZ + if (chplan_6g == -1) { + RTW_PRINT("%s use def_chplan_6g:0x%02X\n", __func__, def_chplan_6g); + chplan_6g = def_chplan_6g; + } else + RTW_PRINT("%s chplan_6g:0x%02X\n", __func__, chplan_6g); #endif - op_class_pref_deinit(adapter); + if (!country_ent) { + if (rtw_chplan_ids_is_world_wide(chplan, chplan_6g)) + rtw_get_chplan_worldwide(&ent); + else { + SET_UNSPEC_ALPHA2(ent.alpha2); + ent.edcca_mode_2g_override = RTW_EDCCA_DEF; + #if CONFIG_IEEE80211_BAND_5GHZ + ent.edcca_mode_5g_override = RTW_EDCCA_DEF; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + ent.edcca_mode_6g_override = RTW_EDCCA_DEF; + #endif + ent.txpwr_lmt_override = TXPWR_LMT_DEF; + #if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + ent.proto_en = CHPLAN_PROTO_EN_ALL; + #endif + } + } else { + RTW_PRINT("%s country code:\"%c%c\"\n", __func__ + , country_ent->alpha2[0], country_ent->alpha2[1]); + } + + rfctl->disable_sw_chplan = hw_force_chplan; + + rfctl->regd_inr = RTW_REGD_SET_BY_INIT; + rfctl->init_alpha2[0] = rfctl->alpha2[0] = ent.alpha2[0]; + rfctl->init_alpha2[1] = rfctl->alpha2[1] = ent.alpha2[1]; + rfctl->init_ChannelPlan = rfctl->ChannelPlan = chplan; +#if CONFIG_IEEE80211_BAND_6GHZ + rfctl->init_chplan_6g = rfctl->chplan_6g = chplan_6g; +#endif + rfctl->edcca_mode_2g_override = ent.edcca_mode_2g_override; +#if CONFIG_IEEE80211_BAND_5GHZ + rfctl->edcca_mode_5g_override = ent.edcca_mode_5g_override; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + rfctl->edcca_mode_6g_override = ent.edcca_mode_6g_override; +#endif +#if CONFIG_TXPWR_LIMIT + rfctl->txpwr_lmt_override = ent.txpwr_lmt_override; +#endif +#if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + rfctl->proto_en = ent.proto_en; +#endif } -void rtw_rfctl_chplan_init(_adapter *adapter) +void rtw_rfctl_chplan_init(struct dvobj_priv *dvobj) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); - rfctl->max_chan_nums = init_channel_set(adapter); + init_channel_set(adapter); op_class_pref_apply_regulatory(adapter, REG_CHANGE); init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list); } +bool rtw_rfctl_is_disable_sw_channel_plan(struct dvobj_priv *dvobj) +{ + return dvobj_to_rfctl(dvobj)->disable_sw_chplan; +} + void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op) { struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); @@ -401,9 +447,9 @@ void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op) } else if (!MLME_IS_ASOC(iface) || MLME_IS_OPCH_SW(iface)) continue; - ch = mlmeext->cur_channel; - bw = mlmeext->cur_bwmode; - offset = mlmeext->cur_ch_offset; + ch = mlmeext->chandef.chan; + bw = mlmeext->chandef.bw; + offset = mlmeext->chandef.offset; if_op_class[i] = rtw_get_op_class_by_chbw(ch, bw, offset); if_op_ch[i] = if_op_class[i] ? ch : 0; @@ -449,20 +495,21 @@ void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op) continue; if (0) RTW_INFO(ADPT_FMT": %u,%u,%u\n", ADPT_ARG(iface) - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset); } if (notify) rtw_nlrtw_radio_opmode_notify(rfctl); +} -#ifdef CONFIG_PLATFORM_CMAP_INTFS - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - cmap_intfs_nl_bss_status_event(iface, 0); - } +/* domain status specific beacon hint rules */ +#ifndef RTW_CHPLAN_BEACON_HINT_SPECIFIC_COUNTRY +#define RTW_CHPLAN_BEACON_HINT_SPECIFIC_COUNTRY 0 #endif + +bool rtw_rfctl_reg_allow_beacon_hint(struct rf_ctl_t *rfctl) +{ + return RTW_CHPLAN_BEACON_HINT_SPECIFIC_COUNTRY || RFCTL_REG_WORLDWIDE(rfctl) || RFCTL_REG_ALPHA2_UNSPEC(rfctl); } inline u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl) @@ -578,10 +625,19 @@ bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl) { +#if 0 + struct rtw_chan_def cur_chandef = {0}; + _adapter *adapter = NULL; + + rtw_get_oper_chdef(adapter, &cur_chandef); + return _rtw_rfctl_overlap_radar_detect_ch(rfctl - , rfctl_to_dvobj(rfctl)->oper_channel - , rfctl_to_dvobj(rfctl)->oper_bwmode - , rfctl_to_dvobj(rfctl)->oper_ch_offset); + , rfctl_to_dvobj(rfctl)->chandef.chan + , rfctl_to_dvobj(rfctl)->chandef.bw + , rfctl_to_dvobj(rfctl)->chandef.offset); +#else + return _FALSE; +#endif } bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl) @@ -621,7 +677,7 @@ bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch) { - return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE); + return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, CHAN_OFFSET_NO_EXT); } u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) @@ -769,7 +825,6 @@ void rtw_chset_chk_non_ocp_finish(struct rf_ctl_t *rfctl) u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms) { - struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); u32 non_ocp_ms; u32 cac_ms; u8 in_rd_range = 0; /* if in current radar detection range*/ @@ -881,9 +936,6 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw #define DBG_CHOOSE_SHORTEST_WAITING_CH 0 #endif struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); -#ifdef CONFIG_RTW_ACS - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(dvobj_get_primary_adapter(dvobj)); -#endif struct registry_priv *regsty = dvobj_to_regsty(dvobj); u8 ch, bw, offset; u8 ch_c = 0, bw_c = 0, offset_c = 0; @@ -902,7 +954,7 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw /* full search and narrow bw judegement first to avoid potetial judegement timing issue */ for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { - if (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) + if (!rtw_hw_is_bw_support(dvobj, bw)) continue; for (i = 0; i < rfctl->max_chan_nums; i++) { @@ -963,7 +1015,7 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw waiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms); #endif - #ifdef CONFIG_RTW_ACS + #if 0 /* def CONFIG_RTW_ACS */ if (by_int_info) { /* for now, consider only primary channel */ int_factor = hal_data->acs.interference_time[i]; @@ -1012,7 +1064,6 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw return _FALSE; } -#ifdef CONFIG_PROC_DEBUG #define RTW_CHF_FMT "%s%s%s%s%s%s" #define RTW_CHF_ARG_NO_IR(flags) (flags & RTW_CHF_NO_IR) ? " NO_IR" : "" @@ -1030,7 +1081,7 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw RTW_CHF_ARG_NO_80MHZ(flags) \ RTW_CHF_ARG_NO_160MHZ(flags) -void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num) +static void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num) { char buf[8]; u8 i; @@ -1046,7 +1097,7 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num) snprintf(buf, 8, "0"); RTW_PRINT_SEL(sel, "%3u %4u %4s"RTW_CHF_FMT"\n" - , ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), buf + , ch_set[i].ChannelNum, rtw_ch2freq_by_band(ch_set[i].band, ch_set[i].ChannelNum), buf , RTW_CHF_ARG(ch_set[i].flags) ); } @@ -1054,6 +1105,45 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num) RTW_PRINT_SEL(sel, "total ch number:%d\n", i); } +#if CONFIG_TXPWR_LIMIT +static void dump_chplan_txpwr_lmts(void *sel, struct get_chplan_resp *chplan) +{ + char buf[TXPWR_NAMES_STR_LEN]; + + RTW_PRINT_SEL(sel, "txpwr_lmt:%s\n", rtw_get_txpwr_lmt_names_str(buf, chplan->txpwr_lmt_name, 0)); +} +#endif + +static void dump_chplan_edcca_modes(void *sel, struct get_chplan_resp *chplan) +{ + u8 modes[BAND_MAX]; + char buf[EDCCA_MODES_STR_LEN]; + + modes[BAND_ON_24G] = chplan->edcca_mode_2g; +#if CONFIG_IEEE80211_BAND_5GHZ + modes[BAND_ON_5G] = chplan->edcca_mode_5g; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + modes[BAND_ON_6G] = chplan->edcca_mode_6g; +#endif + + RTW_PRINT_SEL(sel, "edcca_mode:%s\n", rtw_get_edcca_modes_str(buf, modes)); +} + +void dump_cur_country(void *sel, struct rf_ctl_t *rfctl) +{ + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + struct get_chplan_resp *chplan; + int i; + + if (rtw_get_chplan_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_WAIT_ACK, &chplan) == _FAIL) + return; + + RTW_PRINT_SEL(sel, "%c%c\n", chplan->alpha2[0], chplan->alpha2[1]); + + rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num); +} + void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl) { struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); @@ -1065,27 +1155,46 @@ void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl) return; RTW_PRINT_SEL(sel, "regd_src:%s(%d)\n", regd_src_str(chplan->regd_src), chplan->regd_src); + RTW_PRINT_SEL(sel, "regd_inr:%s\n", regd_inr_str(chplan->regd_inr)); - if (chplan->has_country) - dump_country_chplan(sel, &chplan->country_ent); + RTW_PRINT_SEL(sel, "alpha2:%c%c\n", chplan->alpha2[0], chplan->alpha2[1]); + +#ifdef CONFIG_80211AX_HE + RTW_PRINT_SEL(sel, "ax:%d\n", (chplan->proto_en & CHPLAN_PROTO_EN_AX) ? 1 : 0); +#endif +#ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "ac:%d\n", (chplan->proto_en & CHPLAN_PROTO_EN_AC) ? 1 : 0); +#endif + + if (chplan->channel_plan == RTW_CHPLAN_UNSPECIFIED) + RTW_PRINT_SEL(sel, "chplan:NA\n"); else RTW_PRINT_SEL(sel, "chplan:0x%02X\n", chplan->channel_plan); +#if CONFIG_IEEE80211_BAND_6GHZ + if (chplan->chplan_6g == RTW_CHPLAN_6G_UNSPECIFIED) + RTW_PRINT_SEL(sel, "chplan_6g:NA\n"); + else + RTW_PRINT_SEL(sel, "chplan_6g:0x%02X\n", chplan->chplan_6g); +#endif + #if CONFIG_TXPWR_LIMIT - RTW_PRINT_SEL(sel, "PLS regd:%s\n", chplan->regd_name); + dump_chplan_txpwr_lmts(sel, chplan); #endif + dump_chplan_edcca_modes(sel, chplan); + #ifdef CONFIG_DFS_MASTER RTW_PRINT_SEL(sel, "dfs_domain:%s(%u)\n", rtw_dfs_regd_str(chplan->dfs_domain), chplan->dfs_domain); #endif - for (i = 0; i < MAX_CHANNEL_NUM; i++) + for (i = 0; i < MAX_CHANNEL_NUM_2G_5G; i++) if (regsty->excl_chs[i] != 0) break; - if (i < MAX_CHANNEL_NUM) { + if (i < MAX_CHANNEL_NUM_2G_5G) { RTW_PRINT_SEL(sel, "excl_chs:"); - for (i = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0; i < MAX_CHANNEL_NUM_2G_5G; i++) { if (regsty->excl_chs[i] == 0) break; _RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]); @@ -1093,11 +1202,26 @@ void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl) _RTW_PRINT_SEL(sel, "\n"); } +#if CONFIG_IEEE80211_BAND_6GHZ + for (i = 0; i < MAX_CHANNEL_NUM_6G; i++) + if (regsty->excl_chs_6g[i] != 0) + break; + + if (i < MAX_CHANNEL_NUM_6G) { + RTW_PRINT_SEL(sel, "excl_chs_6g:"); + for (i = 0; i < MAX_CHANNEL_NUM_6G; i++) { + if (regsty->excl_chs_6g[i] == 0) + break; + _RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs_6g[i]); + } + _RTW_PRINT_SEL(sel, "\n"); + } +#endif + dump_chset(sel, chplan->chset, chplan->chset_num); rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num); } -#endif /* * Search the @param ch in given @param ch_set @@ -1121,6 +1245,29 @@ int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) return -1; } +/* + * Search the @param ch of @param band in given @param ch_set + * @ch_set: the given channel set + * @band: the given band + * @ch: the given channel number + * + * return the index of channel_num in channel_set, -1 if not found + */ +int rtw_chset_search_ch_by_band(RT_CHANNEL_INFO *ch_set, enum band_type band, const u32 ch) +{ + int i; + + if (ch == 0) + return -1; + + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { + if (band == ch_set[i].band && ch == ch_set[i].ChannelNum) + return i; + } + + return -1; +} + /* * Check if the @param ch, bw, offset is valid for the given @param ch_set * @ch_set: the given channel set @@ -1140,7 +1287,7 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset int i; int ch_idx; - cch = rtw_get_center_ch(ch, bw, offset); + cch = rtw_phl_get_center_ch(ch, bw, offset); if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num)) goto exit; @@ -1152,8 +1299,8 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset if (ch_idx == -1) break; if (ch_set[ch_idx].flags & RTW_CHF_NO_IR) { - if ((!allow_primary_passive && ch_set[ch_idx].ChannelNum == ch) - || (!allow_passive && ch_set[ch_idx].ChannelNum != ch)) + if (!allow_passive + || (!allow_primary_passive && ch_set[ch_idx].ChannelNum == ch)) break; } if (bw >= CHANNEL_WIDTH_40) { @@ -1279,25 +1426,18 @@ Following are the initialization functions for WiFi MLME int init_hw_mlme_ext(_adapter *padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 rx_bar_enble = _TRUE; /* * Sync driver status and hardware setting */ - - /* Modify to make sure first time change channel(band) would be done properly */ - pHalData->current_channel = 0; - pHalData->current_channel_bw = CHANNEL_WIDTH_MAX; - #if CONFIG_IEEE80211_BAND_5GHZ - pHalData->current_band_type = BAND_MAX; - #else - pHalData->current_band_type = BAND_ON_2_4G; - #endif - /* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */ rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble); - set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + set_channel_bwmode(padapter, + pmlmeext->chandef.chan, + pmlmeext->chandef.offset, + pmlmeext->chandef.bw, + _FALSE); return _SUCCESS; } @@ -1312,7 +1452,7 @@ void init_mlme_default_rate_set(_adapter *padapter) unsigned char supported_mcs_set[16] = {0xff, 0xff, 0xff, 0xff, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; #endif - if (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) { + if (is_supported_tx_cck(padapter->registrypriv.wireless_mode)) { unsigned char datarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_}; _rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM); @@ -1321,7 +1461,7 @@ void init_mlme_default_rate_set(_adapter *padapter) offset_basicrate += B_MODE_RATE_NUM; RTW_INFO("%s: support CCK\n", __func__); } - if(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) { + if(is_suuported_tx_ofdm(padapter->registrypriv.wireless_mode)) { unsigned char datarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_}; unsigned char basicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_}; _rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM); @@ -1350,39 +1490,39 @@ static void init_mlme_ext_priv_value(_adapter *padapter) #ifdef CONFIG_IEEE80211W pmlmeext->sa_query_seq = 0; #endif - pmlmeext->cur_channel = padapter->registrypriv.channel; - pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmlmeext->chandef.chan = padapter->registrypriv.channel; + pmlmeext->chandef.bw = CHANNEL_WIDTH_20; + pmlmeext->chandef.offset = CHAN_OFFSET_NO_EXT; pmlmeext->retry = 0; pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; init_mlme_default_rate_set(padapter); - if ((pmlmeext->cur_channel > 14) || ((padapter->registrypriv.wireless_mode & WIRELESS_11B) == 0)) + if ((pmlmeext->chandef.chan > 14) || ((padapter->registrypriv.wireless_mode & WLAN_MD_11B) == 0)) pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB; else pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB; mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + #if 0 pmlmeext->sitesurvey_res.channel_idx = 0; + #endif pmlmeext->sitesurvey_res.bss_cnt = 0; pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO; pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID; #ifdef CONFIG_SCAN_BACKOP - mlmeext_assign_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); + mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); #ifdef CONFIG_AP_MODE - #ifdef CONFIG_CUSTOMER_EZVIZ_CHIME2 - mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME | SS_BACKOP_EN_NL); - #else - mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); - #endif + mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); #endif #ifdef CONFIG_RTW_MESH mlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); #endif + #if 0 pmlmeext->sitesurvey_res.scan_cnt = 0; + #endif pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH; pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS; #endif @@ -1390,6 +1530,7 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0; #endif pmlmeext->scan_abort = _FALSE; + pmlmeext->scan_abort_to = _FALSE; pmlmeinfo->state = WIFI_FW_NULL_STATE; pmlmeinfo->reauth_count = 0; @@ -1417,31 +1558,32 @@ static void init_mlme_ext_priv_value(_adapter *padapter) _rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX); pmlmeinfo->ht_vht_received = 0; #endif /* ROKU_PRIVATE */ -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW - pmlmeinfo->last_bcn_len = 0; -#endif } void init_mlme_ext_timer(_adapter *padapter) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter); - rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter); -#ifdef CONFIG_RTW_80211R - rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter); - rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter); +#if 0 + rtw_init_timer(&pmlmeext->survey_timer, survey_timer_hdl, padapter); #endif - -#ifdef CONFIG_RTW_REPEATER_SON - rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->link_timer, link_timer_hdl, padapter); +#ifdef CONFIG_RTW_80211R + rtw_init_timer(&pmlmeext->ft_link_timer, rtw_ft_link_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_roam_timer, rtw_ft_roam_timer_hdl, padapter); #endif #ifdef CONFIG_RTW_TOKEN_BASED_XMIT - rtw_init_timer(&pmlmeext->tbtx_xmit_timer, padapter, rtw_tbtx_xmit_timer_hdl, padapter); - rtw_init_timer(&pmlmeext->tbtx_token_dispatch_timer, padapter, rtw_tbtx_token_dispatch_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->tbtx_xmit_timer, rtw_tbtx_xmit_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->tbtx_token_dispatch_timer, rtw_tbtx_token_dispatch_timer_hdl, padapter); +#endif +#ifdef ROKU_PRIVATE + rtw_init_timer(&pmlmeext->find_remote_timer, find_remote_timer_hdl, padapter); +#ifdef CONFIG_P2P + rtw_init_timer(&pmlmeext->hide_ssid_timer, hide_ssid_hdl, padapter); #endif -#ifdef CONFIG_DFS - rtw_init_timer(&pmlmeext->csa_timer, padapter->pnetdev, csa_timer_hdl, padapter); +#endif +#if CONFIG_DFS + rtw_init_timer(&pmlmeext->csa_timer, csa_timer_hdl, padapter); #endif } @@ -1457,8 +1599,6 @@ int init_mlme_ext_priv(_adapter *padapter) pmlmeext->padapter = padapter; - /* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */ - init_mlme_ext_priv_value(padapter); pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq; @@ -1469,7 +1609,6 @@ int init_mlme_ext_priv(_adapter *padapter) #endif pmlmeext->last_scan_time = 0; - pmlmeext->mlmeext_init = _TRUE; #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK @@ -1482,9 +1621,6 @@ int init_mlme_ext_priv(_adapter *padapter) pmlmeext->fixed_chan = 0xFF; #endif - pmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor; - pmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor; - #ifdef CONFIG_SUPPORT_STATIC_SMPS pmlmeext->ssmps_en = _FALSE; pmlmeext->ssmps_tx_tp_th = SSMPS_TX_TP_TH;/*Mbps*/ @@ -1511,12 +1647,18 @@ void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext) if (!padapter) return; - if (rtw_is_drv_stopped(padapter)) { - _cancel_timer_ex(&pmlmeext->survey_timer); - _cancel_timer_ex(&pmlmeext->link_timer); -#ifdef CONFIG_DFS + if (dev_is_drv_stopped(adapter_to_dvobj(padapter))) { + /*cancel_survey_timer(pmlmeext);*/ /*_cancel_timer_ex(&pmlmeext->survey_timer);*/ + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ +#ifdef ROKU_PRIVATE + _cancel_timer_ex(&pmlmeext->find_remote_timer); +#ifdef CONFIG_P2P + _cancel_timer_ex(&pmlmeext->hide_ssid_timer); +#endif +#endif +#if CONFIG_DFS _cancel_timer_ex(&pmlmeext->csa_timer); -#endif /* CONFIG_DFS */ +#endif } } @@ -1531,10 +1673,10 @@ static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len) p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_); if (p) { channel = *(p + 2); - if (padapter->mlmeextpriv.cur_channel >= channel) - return padapter->mlmeextpriv.cur_channel - channel; + if (padapter->mlmeextpriv.chandef.chan >= channel) + return padapter->mlmeextpriv.chandef.chan - channel; else - return channel - padapter->mlmeextpriv.cur_channel; + return channel - padapter->mlmeextpriv.chandef.chan; } else return 0; } @@ -1549,11 +1691,11 @@ static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, uni /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI { struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE) + if (!MLME_IS_STA(padapter)) return; if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) @@ -1581,8 +1723,6 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 *pframe = precv_frame->u.hdr.rx_data; struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe)); - struct recv_priv *precvpriv = &padapter->recvpriv; - #if 0 { @@ -1603,11 +1743,11 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI { struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE) + if (!MLME_IS_STA(padapter)) return; if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) @@ -1647,7 +1787,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) if (GetRetry(pframe)) { if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) { /* drop the duplicate management frame */ - precvpriv->dbg_rx_dup_mgt_frame_drop_count++; + padapter->recvinfo.dbg_rx_dup_mgt_frame_drop_count++; RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); return; } @@ -1668,7 +1808,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; - /* fall through */ + /* fall through */ case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); @@ -1712,34 +1852,27 @@ u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) bool response = _TRUE; #ifdef CONFIG_IOCTL_CFG80211 - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { - if (rtw_cfg80211_get_is_roch(padapter) == _FALSE - || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel - || adapter_wdev_data(padapter)->p2p_enabled == _FALSE - || padapter->mlmepriv.wps_probe_resp_ie == NULL - || padapter->mlmepriv.p2p_probe_resp_ie == NULL - ) { + if (rtw_cfg80211_get_is_roch(padapter) == _FALSE + || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel + || adapter_wdev_data(padapter)->p2p_enabled == _FALSE + || padapter->mlmepriv.wps_probe_resp_ie == NULL + || padapter->mlmepriv.p2p_probe_resp_ie == NULL + ) { #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n" - , ADPT_ARG(padapter) - , adapter_wdev_data(padapter)->p2p_enabled - , padapter->mlmepriv.wps_probe_resp_ie - , padapter->mlmepriv.p2p_probe_resp_ie); - RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n" - , ADPT_ARG(padapter) - , rtw_cfg80211_get_is_roch(padapter) - , rtw_get_oper_ch(padapter) - , padapter->wdinfo.listen_channel); -#endif - response = _FALSE; - } - } else + RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n" + , ADPT_ARG(padapter) + , adapter_wdev_data(padapter)->p2p_enabled + , padapter->mlmepriv.wps_probe_resp_ie + , padapter->mlmepriv.p2p_probe_resp_ie); + RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n" + , ADPT_ARG(padapter) + , rtw_cfg80211_get_is_roch(padapter) + , rtw_get_oper_ch(padapter) + , padapter->wdinfo.listen_channel); +#endif + response = _FALSE; + } #endif /* CONFIG_IOCTL_CFG80211 */ - if (padapter->wdinfo.driver_interface == DRIVER_WEXT) { - /* do nothing if the device name is empty */ - if (!padapter->wdinfo.device_name_len) - response = _FALSE; - } if (response == _TRUE) issue_probersp_p2p(padapter, da); @@ -1748,6 +1881,90 @@ u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) } #endif /* CONFIG_P2P */ +#ifdef ROKU_PRIVATE +static bool check_vendor_ie(_adapter *padapter, u8 *pframe, uint len, u8 ie_offset) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + unsigned int ielen; + u8 *p; + bool ret = _FALSE; + unsigned int search_len = 0, remain_len = 0, total_vendor_ie_len = 0; + int i; + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _VENDOR_SPECIFIC_IE_, (int *)&ielen, + len - WLAN_HDR_A3_LEN - ie_offset); + + while (p) { + for (i = 0; i < MAX_VENDOR_IE_NUM; i++) { + if (ielen == pmlmepriv->vendor_ie_len[i] && + _rtw_memcmp(p, *(pmlmepriv->vendor_ie_filter + i), ielen + 2)) { + ret = _TRUE; + break; + } + } + total_vendor_ie_len = ielen + 2; + search_len = p - pframe; + remain_len = len - search_len - total_vendor_ie_len; + + p = rtw_get_ie(p + total_vendor_ie_len, _VENDOR_SPECIFIC_IE_, + (int *)&ielen, remain_len); + } + return ret; +} +#ifdef CONFIG_P2P +static bool is_valid_probereq(_adapter *padapter, u8 *pframe, uint len) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur = &(pmlmeinfo->network); + struct registry_priv *pregpriv = &padapter->registrypriv; + bool ret = _FALSE; + unsigned int ielen; + u8 *p; + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if (p) { + if ((_rtw_memcmp((void *)(p + 2), "DIRECT-", P2P_WILDCARD_SSID_LEN) && + (ielen == P2P_WILDCARD_SSID_LEN || + (ielen == cur->Ssid.SsidLength && + _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)))) || + (ielen == 0 && pregpriv->go_hidden_ssid_mode != ALL_HIDE_SSID)) + ret = _TRUE; + } + return ret; +} + +static void hide_ssid_in_beacon(_adapter *padapter, u8 *pframe, uint len) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + u8 *wfd_ie; + uint wfd_ielen; + + /* check if need to unhide/hide SSID in beacon for miracast */ + wfd_ie = rtw_get_wfd_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_, + NULL, &wfd_ielen); + if (wfd_ie) { + if (pregpriv->go_hidden_ssid_mode & BIT(MIRACAST)) { + rtw_clear_bit(MIRACAST, &pregpriv->go_hidden_ssid_mode); + + /* check if there is other feature show SSID in beacon */ + if (pregpriv->go_hidden_ssid_mode == MIRACAST_UNHIDE_SSID) + issue_beacon(padapter, 0); + + ATOMIC_SET(&pregpriv->set_hide_ssid_timer, 1); + _set_timer(&pmlmeext->hide_ssid_timer, 25000); + } else { + if (ATOMIC_READ(&pregpriv->set_hide_ssid_timer)) + _set_timer(&pmlmeext->hide_ssid_timer, 25000); + } + } +} +#endif +#endif /**************************************************************************** @@ -1779,23 +1996,56 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) struct wifidirect_info *pwdinfo = &(padapter->wdinfo); struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; u8 wifi_test_chk_rate = 1; +#endif #ifdef CONFIG_IOCTL_CFG80211 - if ((pwdinfo->driver_interface == DRIVER_CFG80211) - && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) - && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE) - ) { - rtw_cfg80211_rx_probe_request(padapter, precv_frame); +#ifdef RTW_USE_CFG80211_REPORT_PROBE_REQ + if (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), + IEEE80211_STYPE_PROBE_REQ) == _TRUE) { +#ifdef ROKU_PRIVATE + if (pmlmepriv->vendor_ie_filter_enable) { + /* check vendor ie for softAP and GO */ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && + !check_vendor_ie(padapter, pframe, len, _PROBEREQ_IE_OFFSET_)) + return _FAIL; + } +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + if (!is_valid_probereq(padapter, pframe, len)) + return _FAIL; + hide_ssid_in_beacon(padapter, pframe, len); + } +#endif +#endif + rtw_cfg80211_rx_probe_request(padapter, precv_frame); + return _SUCCESS; + } else { + return _FAIL; + } +#endif + +#if !defined(RTW_WKARD_DIS_PROBE_REQ_RPT_TO_HOSTAPD) + if (MLME_IS_AP(padapter) && + (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)) { + rtw_cfg80211_rx_probe_request(padapter, precv_frame); + return _SUCCESS; + } +#endif + +#ifdef CONFIG_P2P + if ((adapter_to_dvobj(padapter)->wpas_type == RTW_WPAS_W1FI) && + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE) && + (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), + IEEE80211_STYPE_PROBE_REQ) == _TRUE)) { + rtw_cfg80211_rx_probe_request(padapter, precv_frame); return _SUCCESS; } +#endif #endif /* CONFIG_IOCTL_CFG80211 */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && - !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) && - !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && - !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) && - !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) - ) { +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || + rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { /* Commented by Albert 2011/03/17 */ /* mcs_rate = 0->CCK 1M rate */ /* mcs_rate = 1->CCK 2M rate */ @@ -1814,12 +2064,9 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len); if (is_valid_p2p_probereq == _TRUE) { if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { - /* FIXME */ - if (padapter->wdinfo.driver_interface == DRIVER_WEXT) - report_survey_event(padapter, precv_frame); - - p2p_listen_state_process(padapter, get_sa(pframe)); - + /* P2P Device only responds probe response in listen state(ROCH) */ + if (MLME_IS_ROCH(padapter)) + p2p_listen_state_process(padapter, get_sa(pframe)); return _SUCCESS; } @@ -1832,7 +2079,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) _continue: #endif /* CONFIG_P2P */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + if (MLME_IS_STA(padapter)) return _SUCCESS; if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE && @@ -1863,7 +2110,6 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_AUTO_AP_MODE if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && pmlmepriv->cur_network.join_res == _TRUE) { - _irqL irqL; struct sta_info *psta; u8 *mac_addr, *peer_addr; struct sta_priv *pstapriv = &padapter->stapriv; @@ -1900,7 +2146,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&psta->asoc_list)) { psta->expire_to = pstapriv->expire_to; rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list); @@ -1910,29 +2156,29 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) pstapriv->tbtx_asoc_list_cnt++; #endif } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); /* generate pairing ID */ mac_addr = adapter_mac_addr(padapter); - peer_addr = psta->cmn.mac_addr; + peer_addr = psta->phl_sta->mac_addr; psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5])); /* update peer stainfo */ psta->isrc = _TRUE; /* AID assignment */ - if (psta->cmn.aid > 0) - RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); + if (psta->phl_sta->aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->phl_sta->aid); else { if (!rtw_aid_alloc(padapter, psta)) { RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); return _SUCCESS; } - RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->phl_sta->aid); } psta->qos_option = 1; - psta->cmn.bw_mode = CHANNEL_WIDTH_20; + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; psta->ieee8021x_blocked = _FALSE; #ifdef CONFIG_80211N_HT if(padapter->registrypriv.ht_enable && @@ -1941,21 +2187,19 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) psta->htpriv.ampdu_enable = _FALSE; psta->htpriv.sgi_20m = _FALSE; psta->htpriv.sgi_40m = _FALSE; - psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + psta->htpriv.ch_offset = CHAN_OFFSET_NO_EXT; psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ } #endif - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); - _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); psta->state |= WIFI_ASOC_STATE; - _exit_critical_bh(&psta->lock, &irqL); + _rtw_spinunlock_bh(&psta->lock); - report_add_sta_event(padapter, psta->cmn.mac_addr); + report_add_sta_event(padapter, psta->phl_sta->mac_addr); } @@ -1980,38 +2224,56 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) } #endif +#ifdef ROKU_PRIVATE + if (pmlmepriv->vendor_ie_filter_enable) { + /* check vendor ie for softAP and GO */ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && + !check_vendor_ie(padapter, pframe, len, _PROBEREQ_IE_OFFSET_)) + goto exit; + } +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + if (is_valid_probereq(padapter, pframe, len)) { + hide_ssid_in_beacon(padapter, pframe, len); + goto _issue_probersp; + } else { + goto exit; + } + } +#endif +#endif + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + if (!p) + goto exit; + if (is_valid_p2p_probereq == _TRUE) + goto _issue_probersp; - /* check (wildcard) SSID */ - if (p != NULL) { - if (is_valid_p2p_probereq == _TRUE) - goto _issue_probersp; - - if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) - || (ielen == 0 && pmlmeinfo->hidden_ssid_mode)) - goto exit; + if ((ielen != 0 && + !_rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) || + (ielen == 0 && pmlmeinfo->hidden_ssid_mode)) + goto exit; - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen, - len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); - if (!p) - goto exit; - if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE) - goto exit; - } - #endif + if (!p) + goto exit; + if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE) + goto exit; + } +#endif _issue_probersp: - if (((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && - pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { - /* RTW_INFO("+issue_probersp during ap mode\n"); */ - issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); - } - + if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && + pmlmepriv->cur_network.join_res == _TRUE) || + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { + /* RTW_INFO("+issue_probersp during ap mode\n"); */ + issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); } exit: @@ -2027,52 +2289,8 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif - -#ifdef CONFIG_P2P - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { - if (_TRUE == pwdinfo->tx_prov_disc_info.benable) { - if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) { - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { - pwdinfo->tx_prov_disc_info.benable = _FALSE; - issue_p2p_provision_request(padapter, - pwdinfo->tx_prov_disc_info.ssid.Ssid, - pwdinfo->tx_prov_disc_info.ssid.SsidLength, - pwdinfo->tx_prov_disc_info.peerDevAddr); - } else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - pwdinfo->tx_prov_disc_info.benable = _FALSE; - issue_p2p_provision_request(padapter, - NULL, - 0, - pwdinfo->tx_prov_disc_info.peerDevAddr); - } - } - } - return _SUCCESS; - } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { - if (_TRUE == pwdinfo->nego_req_info.benable) { - RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__); - if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) { - pwdinfo->nego_req_info.benable = _FALSE; - issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr); - } - } - } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) { - if (_TRUE == pwdinfo->invitereq_info.benable) { - RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__); - if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) { - pwdinfo->invitereq_info.benable = _FALSE; - issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr); - } - } - } -#endif - - if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) || (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) - #ifdef CONFIG_RTW_REPEATER_SON - || (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) - #endif ) { struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -2104,17 +2322,18 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) } /* for 11n Logo 4.2.31/4.2.32 */ -#ifdef CONFIG_AP_MODE static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) { + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (!padapter->registrypriv.wifi_spec) return; - + if(!MLME_IS_AP(padapter)) return; + if (pmlmeext->bstart_bss == _TRUE) { int left; @@ -2142,9 +2361,9 @@ static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) ATOMIC_SET(&pmlmepriv->olbc, _TRUE); ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE); } + } } -#endif /* CONFIG_AP_MODE */ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) { @@ -2164,9 +2383,21 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; #endif #endif /* CONFIG_TDLS */ +#if defined(CONFIG_MCC_MODE) || defined(CONFIG_RTW_LPS) + struct rtw_bcn_pkt_info bcn_info = {0}; +#endif +#ifdef CONFIG_STA_MULTIPLE_BSSID + u8 is_mbssid = _FALSE; +#endif - if (validate_beacon_len(pframe, len) == _FALSE) + if (pframe == NULL) { + RTW_ERR(FUNC_ADPT_FMT" pframe == NULL\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + return _SUCCESS; + } + if (validate_beacon_len(pframe, len) == _FALSE) { return _SUCCESS; + } if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS) || (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) @@ -2174,38 +2405,32 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN) && (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ) { +#ifndef RTW_PHL_TEST_FPGA if (!rtw_check_bcn_info(padapter, pframe, len)) { RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter)); receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE); } +#endif } - rtw_mi_report_survey_event(padapter, precv_frame); return _SUCCESS; } -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) - && (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) { - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + rtw_check_legacy_ap(padapter, pframe, len); - if (pmlmeinfo->last_bcn_len != pattrib->pkt_len) { - pmlmeinfo->last_bcn_len = pattrib->pkt_len; - rtw_write_bcnlen_to_fw_cmd(padapter, pattrib->pkt_len); - } +#ifdef CONFIG_STA_MULTIPLE_BSSID + /* Multiple BSSID Byte0~Byte4 will tha same */ + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN - 1)) { + if (pmlmeinfo->network.is_mbssid) + is_mbssid = _TRUE; } #endif -#ifdef CONFIG_RTW_REPEATER_SON - if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) - rtw_mi_report_survey_event(padapter, precv_frame); -#endif - -#ifdef CONFIG_AP_MODE - rtw_check_legacy_ap(padapter, pframe, len); -#endif - +#ifdef CONFIG_STA_MULTIPLE_BSSID + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN) || is_mbssid == _TRUE) { +#else if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { +#endif if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL) && (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort) ) { @@ -2220,10 +2445,15 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { struct beacon_keys recv_beacon; - update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); /* update bcn keys */ - if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { +#ifdef RTW_PHL_TEST_FPGA + if (1) +#else + if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) +#endif + { RTW_INFO("%s: beacon keys ready\n", __func__); _rtw_memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); @@ -2235,9 +2465,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) RTW_ERR("%s: get beacon keys failed\n", __func__); _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); } - #ifdef CONFIG_BCN_CNT_CONFIRM_HDL - pmlmepriv->new_beacon_cnts = 0; - #endif } rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX)); } @@ -2289,30 +2516,41 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_RTW_80211R rtw_ft_update_bcn(padapter, precv_frame); #endif +#ifdef RTW_PHL_TEST_FPGA + ret = 1; +#else ret = rtw_check_bcn_info(padapter, pframe, len); +#endif if (!ret) { RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter)); receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE); return _SUCCESS; } + /* update WMM, ERP in the beacon */ /* todo: the timer is used instead of the number of the beacon received */ if ((sta_rx_pkts(psta) & 0xf) == 0) { /* RTW_INFO("update_bcn_info\n"); */ update_beacon_info(padapter, pframe, len, psta); } - - pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; + if (pmlmepriv->cur_network_scanned) + pmlmepriv->cur_network_scanned->network.PhyInfo.rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; pmlmeext->bcn_cnt++; #ifdef CONFIG_BCN_RECV_TIME rtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate); #endif +#if defined(CONFIG_MCC_MODE) || defined(CONFIG_RTW_LPS) + update_TSF(pmlmeext, pframe, len); + bcn_info.sta = psta->phl_sta; + bcn_info.tsf = pmlmeext->TSFValue; + rtw_phl_sta_up_rx_bcn(GET_PHL_INFO(adapter_to_dvobj(padapter)), &bcn_info); +#endif #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) { /* Send TDLS Channel Switch Request when receiving Beacon */ if ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) - && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) { + && (pmlmeext->chandef.chan == rtw_get_oper_ch(padapter))) { ptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr); if (ptdls_sta != NULL) { if (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE) @@ -2329,13 +2567,20 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) , len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_)); #endif + #ifdef CONFIG_80211D + process_country_ie(padapter + , pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_ + , len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_)); + #endif + #ifdef CONFIG_P2P_PS process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); #endif /* CONFIG_P2P_PS */ - if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf) - rtw_enable_hw_update_tsf_cmd(padapter); - + if (ATOMIC_READ(&padapter->need_tsf_sync_done) == _TRUE) { + rtw_send_tsf_sync_done_msg(padapter); + ATOMIC_SET(&padapter->need_tsf_sync_done, _FALSE); + } #if 0 /* move to validate_recv_mgnt_frame */ psta->sta_stats.rx_mgnt_pkts++; #endif @@ -2353,9 +2598,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) */ if ((sta_rx_pkts(psta) & 0xf) == 0) update_beacon_info(padapter, pframe, len, psta); - - if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf) - rtw_enable_hw_update_tsf_cmd(padapter); } else { rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num); if (rate_num == 0) { @@ -2389,16 +2631,14 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) } -#ifdef CONFIG_AP_MODE static u32 rtw_get_sta_num_by_state(_adapter *padapter, u32 state) { - _irqL irqL; _list *plist, *phead; u32 index, sta_num = 0; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &(padapter->stapriv); - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < NUM_STA; index++) { phead = &(pstapriv->sta_hash[index]); plist = get_next(phead); @@ -2409,7 +2649,7 @@ static u32 rtw_get_sta_num_by_state(_adapter *padapter, u32 state) plist = get_next(plist); } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); /* RTW_INFO("%s : waiting for %u sta under linking \n", __func__, sta_num); */ return sta_num; @@ -2434,17 +2674,16 @@ static u8 rtw_defs_attack_chk(_adapter *padapter) /* RTW_INFO("%s : current linking num=%u\n", __func__, sta_limit); */ return is_reject; } -#endif unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_AP_MODE - _irqL irqL; unsigned int auth_mode, seq, ie_len; unsigned char *sa, *p; u16 algorithm; int status; static struct sta_info stat; + static struct rtw_phl_stainfo_t phl_stat; struct sta_info *pstat = NULL; struct sta_priv *pstapriv = &padapter->stapriv; struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -2531,8 +2770,12 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) auth_mode = 0; - if ((algorithm > 0 && auth_mode == 0) || /* rx a shared-key auth but shared not enabled */ - (algorithm == 0 && auth_mode == 1)) { /* rx a open-system auth but shared-key is enabled */ + if (((algorithm > 0 && auth_mode == 0) || /* rx a shared-key auth but shared not enabled */ + (algorithm == 0 && auth_mode == 1)) + #ifdef CONFIG_RTW_80211R_AP + && (algorithm != WLAN_AUTH_FT) + #endif + ) { /* rx a open-system auth but shared-key is enabled */ RTW_INFO("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n", algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); @@ -2553,7 +2796,9 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) /* allocate a new one */ RTW_INFO("going to alloc stainfo for sa="MAC_FMT"\n", MAC_ARG(sa)); - pstat = rtw_alloc_stainfo(pstapriv, sa); + + pstat = rtw_alloc_stainfo_sw(pstapriv, sa); + if (pstat == NULL) { RTW_INFO(" Exceed the upper limit of supported clients...\n"); status = _STATS_UNABLE_HANDLE_STA_; @@ -2566,13 +2811,17 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) /* pstat->flags = 0; */ /* pstat->capability = 0; */ } else { +#ifdef ROKU_PRIVATE + RTW_INFO("STA is still connecting, disconnect it at first.\n"); + rtw_cfg80211_indicate_sta_disassoc(padapter, sa, WLAN_REASON_DISASSOC_STA_HAS_LEFT); +#endif #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) { rtw_list_delete(&pstat->asoc_list); pstapriv->asoc_list_cnt--; @@ -2583,7 +2832,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) if (pstat->expire_to > 0) ;/* TODO: STA re_auth within expire_to */ } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); if (seq == 1) ; /* TODO: STA re_auth and auth timeout */ @@ -2592,17 +2841,17 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) } #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { - _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->auth_list_lock); if (rtw_is_list_empty(&pstat->auth_list)) { rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list); pstapriv->auth_list_cnt++; } - _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->auth_list_lock); } if (pstat->auth_seq == 0) @@ -2617,6 +2866,13 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL); return _SUCCESS; } + #ifdef CONFIG_RTW_80211R_AP + pstat->authalg = algorithm; + if (algorithm == WLAN_AUTH_FT) { + rtw_cfg80211_rx_mframe(padapter, precv_frame, "FTTA"); + return _SUCCESS; + } + #endif } #endif /* CONFIG_IOCTL_CFG80211 */ @@ -2630,7 +2886,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) if (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) { if (seq == 1) { #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { @@ -2652,7 +2908,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) /* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */ _rtw_memset((void *)pstat->chg_txt, 78, 128); #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { @@ -2676,7 +2932,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) { #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { @@ -2715,18 +2971,19 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) auth_fail: if (pstat) - rtw_free_stainfo(padapter , pstat); + rtw_free_stainfo_sw(padapter , pstat); pstat = &stat; _rtw_memset((char *)pstat, '\0', sizeof(stat)); + pstat->phl_sta = &phl_stat; pstat->auth_seq = 2; - _rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN); + _rtw_memcpy(pstat->phl_sta->mac_addr, sa, ETH_ALEN); #ifdef CONFIG_NATIVEAP_MLME issue_auth(padapter, pstat, (unsigned short)status); #endif -#endif /* CONFIG_AP_MODE */ +#endif return _FAIL; } @@ -2836,19 +3093,61 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) } +static u8 rtw_deny_legacy_sta(_adapter *padapter, struct sta_info *pstat) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 res = _FALSE; + + sta_info_update(padapter, pstat); + rtw_ap_set_sta_wmode(padapter, pstat); + + if (pmlmeext->cur_wireless_mode == WLAN_MD_11BGN) { + if ((pregpriv->deny_legacy == WLAN_MD_11BG) && + !(pstat->phl_sta->wmode & WLAN_MD_11N)) + /* 2.4G N only */ + res = _TRUE; + else if ((pregpriv->deny_legacy == WLAN_MD_11B) && + (pstat->phl_sta->wmode == WLAN_MD_11B)) + /* 2.4G G+N */ + res = _TRUE; + } else if (pmlmeext->cur_wireless_mode == WLAN_MD_11BG) { + if ((pregpriv->deny_legacy == WLAN_MD_11B) && + (pstat->phl_sta->wmode == WLAN_MD_11B)) + /* 2.4G G only */ + res = _TRUE; + } else if (pmlmeext->cur_wireless_mode == WLAN_MD_11A_AC) { + if ((pregpriv->deny_legacy == WLAN_MD_11AN) && + !(pstat->phl_sta->wmode & WLAN_MD_11AC)) + /* 5G AC only */ + res = _TRUE; + else if ((pregpriv->deny_legacy == WLAN_MD_11A) && + (pstat->phl_sta->wmode == WLAN_MD_11A)) + /* 5G N+AC */ + res = _TRUE; + } else if (pmlmeext->cur_wireless_mode == WLAN_MD_11AN) { + if ((pregpriv->deny_legacy == WLAN_MD_11A) && + (pstat->phl_sta->wmode == WLAN_MD_11A)) + /* 5G N only */ + res = _TRUE; + } + + return res; +} + unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_AP_MODE - _irqL irqL; u16 listen_interval; struct rtw_ieee802_11_elems elems; - struct sta_info *pstat; + struct sta_info *pstat; unsigned char reassoc, *pos; int left; unsigned short status = _STATS_SUCCESSFUL_; unsigned short frame_type, ie_offset = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *cur = &(pmlmeinfo->network); struct sta_priv *pstapriv = &padapter->stapriv; u8 *pframe = precv_frame->u.hdr.rx_data; @@ -2862,6 +3161,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_RTW_TOKEN_BASED_XMIT u8 sta_tbtx_enable = _FALSE; #endif + struct registry_priv *pregpriv = &padapter->registrypriv; #ifdef CONFIG_CONCURRENT_MODE if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) && @@ -2902,6 +3202,15 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) goto asoc_class2_error; } +#ifdef RTW_PHL_TEST_FPGA + DBGP(" [%s][%d] force assoc \n", __FUNCTION__, __LINE__); + pstat->state = WIFI_ASOC_STATE; + pstat->state |= WIFI_FW_ASSOC_SUCCESS; + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + return _SUCCESS; +#endif + + RTW_INFO("%s\n", __FUNCTION__); if (pstat->authalg == WLAN_AUTH_SAE) { @@ -2935,7 +3244,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) goto fail; } #endif - + /*GEORGIA_TODO_MOVE_CODE_TO_DBG_SYS*/ if (rtw_ap_linking_test_force_asoc_fail()) { status = rtw_ap_linking_test_force_asoc_fail(); RTW_INFO(FUNC_ADPT_FMT" force asoc fail with status:%u\n" @@ -2948,7 +3257,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) { RTW_INFO("STA " MAC_FMT " sent invalid association request\n", - MAC_ARG(pstat->cmn.mac_addr)); + MAC_ARG(pstat->phl_sta->mac_addr)); status = _STATS_FAILURE_; goto OnAssocReqFail; } @@ -3013,18 +3322,24 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems); rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems); + rtw_ap_parse_sta_he_ie(padapter, pstat, &elems); + + if (pregpriv->deny_legacy && rtw_deny_legacy_sta(padapter, pstat)) { + RTW_INFO("Deny legacy STA " MAC_FMT " association\n", + MAC_ARG(pstat->phl_sta->mac_addr)); + status = WLAN_STATUS_UNSPECIFIED_FAILURE; + goto OnAssocReqFail; + } - if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) && + if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT) || (pstat->flags & WLAN_STA_HE)) && ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) { - RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr)); + RTW_INFO("HT/VHT/HE: " MAC_FMT " TKIP association\n", MAC_ARG(pstat->phl_sta->mac_addr)); pstat->flags &= ~WLAN_STA_HT; pstat->flags &= ~WLAN_STA_VHT; - /*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY; - * goto OnAssocReqFail; - */ + pstat->flags &= ~WLAN_STA_HE; } #ifdef CONFIG_P2P @@ -3049,9 +3364,10 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) rtw_ap_parse_sta_multi_ap_ie(padapter, pstat, pos, left); -#ifdef CONFIG_RTW_REPEATER_SON - if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset)) - goto OnAssocReqFail; +#ifdef CONFIG_RTW_MBO + rtw_mbo_process_assoc_req(padapter, + (pframe + WLAN_HDR_A3_LEN + ie_offset), + (pkt_len - WLAN_HDR_A3_LEN - ie_offset)); #endif /* TODO: identify_proprietary_vendor_ie(); */ @@ -3059,40 +3375,62 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) /* identify if this is Broadcom sta */ /* identify if this is ralink sta */ /* Customer proprietary IE */ +#ifdef ROKU_PRIVATE + if (pmlmepriv->vendor_ie_filter_enable) { + if (!check_vendor_ie(padapter, pframe, pkt_len, _ASOCREQ_IE_OFFSET_)) { + status = _STATS_UNABLE_HANDLE_STA_; + goto OnAssocReqFail; + } + } +#endif #ifdef CONFIG_RTW_80211K rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems); #endif +#ifdef CONFIG_RTW_MBO + if (pmlmepriv->mbopriv.enable == _TRUE) { + if(pmlmepriv->mbopriv.assoc_disallow != 0){ + RTW_INFO("Reject STA " MAC_FMT ":MBO association disallowed\n", + MAC_ARG(pstat->phl_sta->mac_addr)); + status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; + goto OnAssocReqFail; + } + rtw_ap_parse_sta_mbo_element(padapter, pstat, + pframe + WLAN_HDR_A3_LEN + ie_offset, + pkt_len - WLAN_HDR_A3_LEN - ie_offset); + } +#endif /*CONFIG_RTW_MBO*/ + /* AID assignment */ - if (pstat->cmn.aid > 0) - RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); + if (pstat->phl_sta->aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->phl_sta->aid); else { if (!rtw_aid_alloc(padapter, pstat)) { RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; goto OnAssocReqFail; } - RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->phl_sta->aid); } pstat->state &= (~WIFI_FW_ASSOC_STATE); pstat->state |= WIFI_FW_ASSOC_SUCCESS; /* RTW_INFO("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n" - , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */ + , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->phl_sta->mac_addr)); */ #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { - _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->auth_list_lock); if (!rtw_is_list_empty(&pstat->auth_list)) { rtw_list_delete(&pstat->auth_list); pstapriv->auth_list_cnt--; } - _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->auth_list_lock); - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&pstat->asoc_list)) { pstat->expire_to = pstapriv->expire_to; rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list); @@ -3104,14 +3442,14 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) } #endif } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); } /* now the station is qualified to join our BSS... */ if (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) { #ifdef CONFIG_NATIVEAP_MLME #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { @@ -3123,14 +3461,23 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP)) status = _STATS_REFUSED_TEMPORARILY_; #endif /* CONFIG_IEEE80211W */ - /* .2 issue assoc rsp before notify station join event. */ - if (frame_type == WIFI_ASSOCREQ) - issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); - else - issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); +#ifdef CONFIG_RTW_MBO + if (rtw_mbo_ap_assoc_disallow(padapter)) + status = _STATS_UNABLE_HANDLE_STA_; +#endif +#ifdef CONFIG_RTW_80211R_AP + if ((pstat && (pstat->authalg != WLAN_AUTH_FT))) +#endif + { + /* .2 issue assoc rsp before notify station join event. */ + if (frame_type == WIFI_ASSOCREQ) + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + else + issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); + } #ifdef CONFIG_IOCTL_CFG80211 - _enter_critical_bh(&pstat->lock, &irqL); + _rtw_spinlock_bh(&pstat->lock); if (pstat->passoc_req) { rtw_mfree(pstat->passoc_req, pstat->assoc_req_len); pstat->passoc_req = NULL; @@ -3142,20 +3489,20 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) _rtw_memcpy(pstat->passoc_req, pframe, pkt_len); pstat->assoc_req_len = pkt_len; } - _exit_critical_bh(&pstat->lock, &irqL); + _rtw_spinunlock_bh(&pstat->lock); #endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_IEEE80211W - if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) + if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) || !(pstat->flags & WLAN_STA_MFP)) #endif /* CONFIG_IEEE80211W */ { /* .3-(1) report sta add event */ - report_add_sta_event(padapter, pstat->cmn.mac_addr); + report_add_sta_event(padapter, pstat->phl_sta->mac_addr); } #ifdef CONFIG_IEEE80211W if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP)) { - RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr)); - issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); + RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->phl_sta->mac_addr)); + issue_action_SA_Query(padapter, pstat->phl_sta->mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); } #endif /* CONFIG_IEEE80211W */ #endif /* CONFIG_NATIVEAP_MLME */ @@ -3175,13 +3522,15 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_NATIVEAP_MLME - /* pstat->cmn.aid = 0; */ + /* pstat->phl_sta->aid = 0; */ if (frame_type == WIFI_ASSOCREQ) issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); else issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); #endif + if (pstat) + rtw_free_stainfo_sw(padapter , pstat); #endif /* CONFIG_AP_MODE */ @@ -3208,155 +3557,179 @@ void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce) psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); if (!psta) return; - + if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same)) nb_req_issue = _TRUE; - - if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) + + if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) rm_add_nb_req(padapter, psta); } #endif -unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) +static void rtw_ie_handler(struct _ADAPTER *padapter, u8 *ie, u32 ie_len) { - uint i; - int res; - unsigned short status; - PNDIS_802_11_VARIABLE_IEs pIE; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ - u8 *pframe = precv_frame->u.hdr.rx_data; - uint pkt_len = precv_frame->u.hdr.len; + int i; + struct _NDIS_802_11_VARIABLE_IEs *p = NULL; #ifdef CONFIG_WAPI_SUPPORT - PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; + PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; #endif - RTW_INFO("%s\n", __FUNCTION__); - - /* check A1 matches or not */ - if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) - return _SUCCESS; - - if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort) - return _SUCCESS; - - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - return _SUCCESS; - - _cancel_timer_ex(&pmlmeext->link_timer); - - /* status */ - status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2)); - if (status > 0) { - RTW_INFO("assoc reject, status code: %d\n", status); - pmlmeinfo->state = WIFI_FW_NULL_STATE; - res = -4; - goto report_assoc_result; - } - - /* get capabilities */ - pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); - - /* set slot time */ - pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20; - - /* AID */ - res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff); - - /* check aid value */ - if (res < 1 || res > 2007) { - RTW_INFO("assoc reject, aid: %d\n", res); - pmlmeinfo->state = WIFI_FW_NULL_STATE; - res = -4; - goto report_assoc_result; - } - - /* following are moved to join event callback function */ - /* to handle HT, WMM, rate adaptive, update MAC reg */ - /* for not to handle the synchronous IO in the tasklet */ - for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + if (!ie || (ie_len == 0)) + return; - switch (pIE->ElementID) { + for (i = 0; i < ie_len;) { + p = (struct _NDIS_802_11_VARIABLE_IEs *)(ie + i); + switch (p->ElementID) { case _VENDOR_SPECIFIC_IE_: - if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) /* WMM */ - WMM_param_handler(padapter, pIE); + if (_rtw_memcmp(p->data, WMM_PARA_OUI, 6)) /* WMM */ + WMM_param_handler(padapter, p); #if defined(CONFIG_P2P) && defined(CONFIG_WFD) - else if (_rtw_memcmp(pIE->data, WFD_OUI, 4)) /* WFD */ - rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__); + else if (_rtw_memcmp(p->data, WFD_OUI, 4)) /* WFD */ + rtw_process_wfd_ie(padapter, (u8 *)p, p->Length, __func__); #endif break; #ifdef CONFIG_WAPI_SUPPORT case _WAPI_IE_: - pWapiIE = pIE; + pWapiIE = p; break; #endif case _HT_CAPABILITY_IE_: /* HT caps */ - HT_caps_handler(padapter, pIE); + HT_caps_handler(padapter, p); #ifdef ROKU_PRIVATE - HT_caps_handler_infra_ap(padapter, pIE); + HT_caps_handler_infra_ap(padapter, p); #endif /* ROKU_PRIVATE */ break; case _HT_EXTRA_INFO_IE_: /* HT info */ - HT_info_handler(padapter, pIE); + HT_info_handler(padapter, p); break; #ifdef CONFIG_80211AC_VHT case EID_VHTCapability: - VHT_caps_handler(padapter, pIE); + VHT_caps_handler(padapter, p); #ifdef ROKU_PRIVATE - VHT_caps_handler_infra_ap(padapter, pIE); + VHT_caps_handler_infra_ap(padapter, p); #endif /* ROKU_PRIVATE */ break; case EID_VHTOperation: - VHT_operation_handler(padapter, pIE); + VHT_operation_handler(padapter, p); + break; +#endif + +#ifdef CONFIG_80211AX_HE + case WLAN_EID_EXTENSION: + if (p->data[0] == WLAN_EID_EXTENSION_HE_CAPABILITY) + HE_caps_handler(padapter, p); + else if (p->data[0] == WLAN_EID_EXTENSION_HE_OPERATION) + HE_operation_handler(padapter, p); + else if (p->data[0] == WLAN_EID_EXTENSION_HE_MU_EDCA) + HE_mu_edca_handler(padapter, p, _TRUE); break; #endif case _ERPINFO_IE_: - ERP_IE_handler(padapter, pIE); + ERP_IE_handler(padapter, p); break; #ifdef CONFIG_TDLS - case _EXT_CAP_IE_: - if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE) + case WLAN_EID_EXT_CAP: + if (check_ap_tdls_prohibited(p->data, p->Length) == _TRUE) padapter->tdlsinfo.ap_prohibited = _TRUE; - if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE) + if (check_ap_tdls_ch_switching_prohibited(p->data, p->Length) == _TRUE) padapter->tdlsinfo.ch_switch_prohibited = _TRUE; break; #endif /* CONFIG_TDLS */ -#ifdef CONFIG_RTW_80211K case _EID_RRM_EN_CAP_IE_: - RM_IE_handler(padapter, pIE); + RM_IE_handler(padapter, p); break; -#endif - #ifdef ROKU_PRIVATE /* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */ case _SUPPORTEDRATES_IE_: - Supported_rate_infra_ap(padapter, pIE); + Supported_rate_infra_ap(padapter, p); break; case _EXT_SUPPORTEDRATES_IE_: - Extended_Supported_rate_infra_ap(padapter, pIE); + Extended_Supported_rate_infra_ap(padapter, p); break; #endif /* ROKU_PRIVATE */ default: break; } - i += (pIE->Length + 2); + i += (p->Length + 2); } +} -#ifdef CONFIG_WAPI_SUPPORT - rtw_wapi_on_assoc_ok(padapter, pIE); -#endif +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) +{ + uint i; + int res; + unsigned short status; + PNDIS_802_11_VARIABLE_IEs pIE = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + + RTW_INFO("%s\n", __FUNCTION__); + + /* check A1 matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; + + if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort) + return _SUCCESS; + + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + return _SUCCESS; + + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ + + /* status */ + status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2)); + if (status > 0) { + RTW_INFO("assoc reject, status code: %d\n", status); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + res = -4; + goto report_assoc_result; + } + + /* get capabilities */ + pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + /* set slot time */ + pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20; + + /* AID assignment move to rtw_joinbss_update_stainfo */ + res = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff); + +#ifdef RTW_PHL_TEST_FPGA + res = 1; +#endif + + /* check aid value */ + if (res < 1 || res > 2007) { + RTW_INFO("assoc reject, aid: %d\n", res); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + res = -4; + goto report_assoc_result; + } + + /* following are moved to join event callback function */ + /* to handle HT, WMM, rate adaptive, update MAC reg */ + /* for not to handle the synchronous IO in the tasklet */ + + rtw_ie_handler(padapter, pframe + 6 + WLAN_HDR_A3_LEN, + pkt_len - 6 - WLAN_HDR_A3_LEN); + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_on_assoc_ok(padapter, pIE); +#endif pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; @@ -3385,6 +3758,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 *pframe = precv_frame->u.hdr.rx_data; + bool active = _FALSE; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ @@ -3395,24 +3769,16 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); -#ifdef CONFIG_P2P - if (pwdinfo->rx_invitereq_info.scan_op_ch_only) { - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); - _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); - } -#endif /* CONFIG_P2P */ - reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter)) { - _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ /* rtw_free_stainfo(padapter, psta); */ - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); @@ -3421,7 +3787,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) if (psta) { u8 updated = _FALSE; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -3429,10 +3795,19 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) if (psta->tbtx_enable) pstapriv->tbtx_asoc_list_cnt--; #endif - updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + +#ifdef CONFIG_IEEE80211W + /* pmf: 4.3.3.2 */ + if (psta->flags & WLAN_STA_MFP) { + psta->flags &= ~WLAN_STA_MFP; + reason = _RSON_CLS2_; + active = _TRUE; + } +#endif + updated = ap_free_sta(padapter, psta, active, reason, _TRUE, _FALSE); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } @@ -3459,6 +3834,11 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) } } +#ifdef CONFIG_RTW_WNM + if (!rtw_wnm_try_btm_roam_imnt(padapter)) + ignore_received_deauth = 1; +#endif + RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n" , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth); @@ -3477,6 +3857,7 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 *pframe = precv_frame->u.hdr.rx_data; + bool active = _FALSE; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ @@ -3487,24 +3868,16 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); -#ifdef CONFIG_P2P - if (pwdinfo->rx_invitereq_info.scan_op_ch_only) { - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); - _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); - } -#endif /* CONFIG_P2P */ - reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter)) { - _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ /* rtw_free_stainfo(padapter, psta); */ - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); @@ -3513,7 +3886,7 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) if (psta) { u8 updated = _FALSE; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -3521,10 +3894,19 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) if (psta->tbtx_enable) pstapriv->tbtx_asoc_list_cnt--; #endif - updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + +#ifdef CONFIG_IEEE80211W + /* pmf: 4.3.3.1 */ + if (psta->flags & WLAN_STA_MFP) { + psta->flags &= ~WLAN_STA_MFP; + reason = _RSON_CLS2_; + active = _TRUE; + } +#endif + updated = ap_free_sta(padapter, psta, active, reason, _TRUE, _FALSE); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } @@ -3571,7 +3953,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, struct ieee80211_info_element *ie; RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n", - FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr)); + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->phl_sta->mac_addr)); for_each_ie(ie, ies, ies_len) { if (ie->id == WLAN_EID_CHANNEL_SWITCH) { @@ -3590,12 +3972,12 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, return _SUCCESS; if (ch_offset == -1) - bwmode = mlmeext->cur_bwmode; + bwmode = mlmeext->chandef.bw; else - bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ? + bwmode = (ch_offset == CHAN_OFFSET_NO_EXT) ? CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40; - ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset; + ch_offset = (ch_offset == -1) ? mlmeext->chandef.offset : ch_offset; /* todo: * 1. the decision of channel switching @@ -3702,7 +4084,7 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) } ret = _SUCCESS; break; -#endif +#endif case RTW_WLAN_ACTION_WNM_BTM_RSP: if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) && (pmlmepriv->nb_info.features & RTW_WNM_FEATURE_BTM_REQ_EN)) { @@ -3719,13 +4101,7 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) rtw_wnm_process_btm_rsp(adapter, frame_body, frame_body_len, &rsp); /* TODO : handle candidates info in rsp.pcandidates for upper-layer services */ - #ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_nl_btm_resp_event(adapter, sta->cmn.mac_addr, - adapter_mac_addr(adapter), - rsp.status, rsp.bssid, - rsp.pcandidates, - rsp.candidates_num); - #endif + if (0 && rsp.pcandidates && (rsp.candidates_num > 0)) RTW_INFO_DUMP("pcandidates : ", rsp.pcandidates, sz); @@ -3734,6 +4110,44 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) } /* fall through */ default: + #ifdef CONFIG_RTW_MBO + if (rtw_mbo_wifi_logo_test(adapter) \ + && (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) \ + && (action == RTW_WLAN_ACTION_WNM_BTM_QUERY)) { + struct mbo_attr_info *pmbo_attr = \ + &(pmlmepriv->mbo_attr); + + RTW_INFO("%s: BSS Transition Management query" + " recv from "MAC_FMT"\n", __func__, + MAC_ARG(sta->phl_sta->mac_addr)); + pmbo_attr->user_raw.hdr.dialog_token = \ + wnm_btm_dialog_token(frame_body); + pmbo_attr->user_raw.hdr.req_mode |= \ + PREFERRED_CANDIDATE_LIST_INCLUDED; + pmbo_attr->user_raw.hdr.validity_interval = 30; + rtw_wnm_process_btm_query( + adapter, frame_body, frame_body_len); + rtw_wnm_issue_btm_req(adapter, sta->phl_sta->mac_addr, + &pmbo_attr->user_raw.hdr, NULL, 0, + (u8 *)&pmbo_attr->user_raw.btm_cants, + pmbo_attr->user_raw.candidate_cnt); + break; + } + + if (rtw_mbo_wifi_logo_test(adapter) \ + && (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) \ + && (action == RTW_WLAN_ACTION_WNM_NOTIF_REQ)) { + struct mbo_attr_info *pmbo_attr = \ + &(pmlmepriv->mbo_attr); + + RTW_INFO("%s: Notification Request" + " recv from "MAC_FMT"\n", __func__, + MAC_ARG(sta->phl_sta->mac_addr)); + rtw_wnm_process_notification_req(adapter, + frame_body, frame_body_len); + break; + } + #endif /* CONFIG_RTW_MBO */ #ifdef CONFIG_IOCTL_CFG80211 cnt += sprintf((msg + cnt), "ACT_WNM %u", action); rtw_cfg80211_rx_action(adapter, rframe, msg); @@ -3756,14 +4170,7 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) u8 rtw_rx_ampdu_size(_adapter *adapter) { u8 size; - HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; - -#ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) { - size = rtw_btcoex_GetAMPDUSize(adapter); - goto exit; - } -#endif + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = 0; /* for scan */ if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) @@ -3821,13 +4228,6 @@ bool rtw_rx_ampdu_is_accept(_adapter *adapter) goto exit; } -#ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) { - accept = _FALSE; - goto exit; - } -#endif - /* for scan */ if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE) @@ -3964,15 +4364,18 @@ u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta) struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; s8 nss = -1; - u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode); + u8 bw = rtw_min(sta->phl_sta->chandef.bw, adapter->mlmeextpriv.chandef.bw); #ifdef CONFIG_80211AC_VHT - if (is_supported_vht(sta->wireless_mode)) { + #ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ + #endif + if (is_supported_vht(sta->phl_sta->wmode)) { nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map) , rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map)); } else #endif - if (is_supported_ht(sta->wireless_mode)) { + if (is_supported_ht(sta->phl_sta->wmode)) { nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate) , rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set)); } @@ -4036,16 +4439,15 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); } /* TODO: TDLS peer */ -#ifdef CONFIG_AP_MODE + } else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { - _irqL irqL; _list *phead, *plist; u8 peer_num = 0; char peers[NUM_STA]; struct sta_priv *pstapriv = &adapter->stapriv; int i; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -4061,7 +4463,7 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) peers[peer_num++] = stainfo_offset; } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); for (i = 0; i < peer_num; i++) { sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]); @@ -4073,7 +4475,6 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); } } -#endif /* CONFIG_AP_MODE */ } /* TODO: ADHOC */ @@ -4150,7 +4551,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) status = RTW_GET_LE16(&frame_body[3]); tid = ((frame_body[5] >> 2) & 0x7); if (status == 0) { - /* successful */ + /* successful */ RTW_INFO("agg_enable for TID=%d\n", tid); psta->htpriv.agg_enable_bitmap |= 1 << tid; psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); @@ -4166,14 +4567,12 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) } else psta->htpriv.agg_enable_bitmap &= ~BIT(tid); - #ifdef CONFIG_AP_MODE if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { RTW_INFO("%s alive check - rx ADDBA response\n", __func__); psta->htpriv.agg_enable_bitmap &= ~BIT(tid); psta->expire_to = pstapriv->expire_to; psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - #endif /* RTW_INFO("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); */ break; @@ -4191,6 +4590,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) preorder_ctrl = &psta->recvreorder_ctrl[tid]; preorder_ctrl->enable = _FALSE; preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + rtw_delba_cmd(padapter, addr, tid); } RTW_INFO("%s(): DELBA: %x(%x)\n", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code); @@ -4225,1779 +4625,1588 @@ u32 rtw_build_vendor_ie(_adapter *padapter , unsigned char **pframe , u8 mgmt_fr #endif #ifdef CONFIG_P2P -int get_reg_classes_full_count(struct p2p_channels *channel_list) -{ - int cnt = 0; - int i; - - for (i = 0; i < channel_list->reg_classes; i++) - cnt += channel_list->reg_class[i].channels; - - return cnt; -} - -void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) +void issue_probersp_p2p(_adapter *padapter, unsigned char *da) { - struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_GO_NEGO_REQ; - u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u8 wpsielen = 0, p2pielen = 0; - u16 len_channellist_attr = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif - struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + unsigned char *mac; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ + u16 beacon_interval = 100; + u16 capInfo = 0; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }; + u32 wpsielen = 0, p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + /* RTW_INFO("%s\n", __FUNCTION__); */ pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) return; - RTW_INFO("[%s] In\n", __FUNCTION__); /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + } + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + mac = adapter_mac_addr(padapter); + fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + /* Use the device address for BSSID field. */ + _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pwdinfo->negotiation_dialog_token = 1; /* Initialize the dialog value */ - pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen)); - + set_frame_sub_type(fctrl, WIFI_PROBERSP); + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = pattrib->hdrlen; + pframe += pattrib->hdrlen; - /* WPS Section */ - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; + /* beacon interval: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); + pframe += 2; + pattrib->pktlen += 2; - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; + /* capability info: 2 bytes */ + /* ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */ + capInfo |= cap_ShortPremble; + capInfo |= cap_ShortSlot; - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); + pframe += 2; + pattrib->pktlen += 2; - /* Device Password ID */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); - wpsielen += 2; - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); - /* Value: */ + /* supported rates... */ + /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */ + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); - if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC); - else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN) - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); - else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC); + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); - wpsielen += 2; +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) { + /* WPS IE */ + _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); + pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len; + pframe += pmlmepriv->wps_probe_resp_ie_len; - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + /* P2P IE */ + _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); + pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len; + pframe += pmlmepriv->p2p_probe_resp_ie_len; + } + } +#endif /* CONFIG_IOCTL_CFG80211 */ +#ifdef CONFIG_WFD + wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif - /* P2P IE Section. */ +/* Vendor Specific IE */ +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBERESP_VENDOR_IE_BIT); +#endif - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + pattrib->last_txcmdsz = pattrib->pktlen; - /* Commented by Albert 20110306 */ - /* According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */ - /* 1. P2P Capability */ - /* 2. Group Owner Intent */ - /* 3. Configuration Timeout */ - /* 4. Listen Channel */ - /* 5. Extended Listen Timing */ - /* 6. Intended P2P Interface Address */ - /* 7. Channel List */ - /* 8. P2P Device Info */ - /* 9. Operating Channel */ + dump_mgntframe(padapter, pmgntframe); - /* P2P Capability */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + return; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; +} - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; +int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; + u16 wpsielen = 0, p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; - else - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - /* Group Owner Intent */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GO_INTENT; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); - /* Value: */ - /* Todo the tie breaker bit. */ - p2pie[p2pielen++] = ((pwdinfo->intent << 1) & 0xFE); + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + } - /* Configuration Timeout */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - /* Value: */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ + mac = adapter_mac_addr(padapter); + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - /* Listen Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH; + if (da) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + } else { + /* broadcast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); + } + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_PROBEREQ); - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; + pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); - /* Operating Class */ - p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ + /* Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */ + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->listen_channel; /* listening channel number */ +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + if (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) { + /* WPS IE */ + _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); + pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; + pframe += pmlmepriv->wps_probe_req_ie_len; + /* P2P IE */ + _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len); + pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len; + pframe += pmlmepriv->p2p_probe_req_ie_len; + } + } +#endif /* CONFIG_IOCTL_CFG80211 */ - /* Extended Listen Timing ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; +#ifdef CONFIG_WFD + wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); - p2pielen += 2; +/* Vendor Specific IE */ +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBEREQ_VENDOR_IE_BIT); +#endif - /* Value: */ - /* Availability Period */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; + pattrib->last_txcmdsz = pattrib->pktlen; - /* Availability Interval */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } - /* Intended P2P Interface Address */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; +exit: + return ret; +} - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); - p2pielen += 2; +inline void issue_probereq_p2p(_adapter *adapter, u8 *da) +{ + _issue_probereq_p2p(adapter, da, _FALSE); +} - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; +#endif /* CONFIG_P2P */ +s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + u8 *frame = rframe->u.hdr.rx_data; + u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf); + u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset); - /* Channel List */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + if (GetRetry(frame)) { + if ((seq_ctrl == mlmeext->action_public_rxseq) + && (token == mlmeext->action_public_dialog_token) + ) { + RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n", + FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token); + return _FAIL; + } + } - /* Length: */ - /* Country String(3) */ - /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ - /* + number of channels in all classes */ - len_channellist_attr = 3 - + (1 + 1) * (u16)(ch_list->reg_classes) - + get_reg_classes_full_count(ch_list); + /* TODO: per sta seq & token */ + mlmeext->action_public_rxseq = seq_ctrl; + mlmeext->action_public_dialog_token = token; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1); - else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); -#else + return _SUCCESS; +} - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); +unsigned int on_action_public_p2p(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; +#ifdef CONFIG_P2P +#if defined(RTW_DEDICATED_P2P_DEVICE) || !RTW_P2P_GROUP_INTERFACE + if (!adapter_wdev_data(padapter)->p2p_enabled) { + RTW_INFO(FUNC_ADPT_FMT": failed to receive p2p action frame\n", + FUNC_ADPT_ARG(padapter)); + return _FAIL; + } else #endif - p2pielen += 2; + { + rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame); + } +#endif /* CONFIG_P2P */ - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + return _SUCCESS; +} - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; +unsigned int on_action_public_vendor(union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + _adapter *adapter = precv_frame->u.hdr.adapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - /* Channel Entry List */ + int cnt = 0; + char msg[64]; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - u8 union_ch = rtw_mi_get_union_chan(padapter); + if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { + if (rtw_action_public_decache(precv_frame, 7) == _FAIL) + goto exit; - /* Operating Class */ - if (union_ch > 14) { - if (union_ch >= 149) - p2pie[p2pielen++] = 0x7c; - else - p2pie[p2pielen++] = 0x73; - } else - p2pie[p2pielen++] = 0x51; + if (!rtw_hw_chk_wl_func(dvobj, WL_FUNC_MIRACAST)) + rtw_rframe_del_wfd_ie(precv_frame, 8); + ret = on_action_public_p2p(precv_frame); + } else if (_rtw_memcmp(frame_body + 2, DPP_OUI, 4) == _TRUE) { + u8 dpp_type = frame_body[7]; - /* Number of Channels */ - /* Just support 1 channel and this channel is AP's channel */ - p2pie[p2pielen++] = 1; +#ifdef CONFIG_IOCTL_CFG80211 + cnt += sprintf((msg + cnt), "DPP(type:%u)", dpp_type); + rtw_cfg80211_rx_action(adapter, precv_frame, msg); +#endif + } - /* Channel List */ - p2pie[p2pielen++] = union_ch; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - int i, j; - for (j = 0; j < ch_list->reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; +exit: + return ret; +} - /* Number of Channels */ - p2pie[p2pielen++] = ch_list->reg_class[j].channels; +unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 token; + _adapter *adapter = precv_frame->u.hdr.adapter; + int cnt = 0; + char msg[64]; - /* Channel List */ - for (i = 0; i < ch_list->reg_class[j].channels; i++) - p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; - } - } + token = frame_body[2]; - /* Device Info */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + if (rtw_action_public_decache(precv_frame, 2) == _FAIL) + goto exit; - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); - p2pielen += 2; +#ifdef CONFIG_IOCTL_CFG80211 + cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token); + rtw_cfg80211_rx_action(adapter, precv_frame, msg); +#endif - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; + ret = _SUCCESS; - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ +exit: + return ret; +} - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm); +unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; - p2pielen += 2; + /* check RA matches or broadcast */ + if (!(_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN) || + is_broadcast_mac_addr(GetAddr1Ptr(pframe)))) + goto exit; - /* Primary Device Type */ - /* Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_PUBLIC) + goto exit; - /* OUI */ - *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); - p2pielen += 4; + action = frame_body[1]; + switch (action) { + case ACT_PUBLIC_BSSCOEXIST: +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_AP_MODE + /*20/40 BSS Coexistence Management frame is a Public Action frame*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_public_act_bsscoex(padapter, pframe, frame_len); +#endif /*CONFIG_AP_MODE*/ +#endif /*CONFIG_80211N_HT*/ + break; + case ACT_PUBLIC_VENDOR: + ret = on_action_public_vendor(precv_frame); + break; + default: + ret = on_action_public_default(precv_frame, action); + break; + } - /* Sub Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; +exit: + return ret; +} - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ +unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_RTW_80211R + u32 ret = _FAIL, frame_len = 0; + u8 action_code = 0, category = 0; + u8 *pframe = NULL, *pframe_body = NULL, *pie = NULL; + u8 tgt_addr[ETH_ALEN], msg[32] = {0}; + u32 ft_ie_len = 0; + u32 status_code = 0; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + struct mlme_priv *pmlmepriv = NULL; + struct wlan_network *proam_target = NULL; + struct ft_roam_info *pft_roam = NULL; - /* Device Name */ - /* Type: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - p2pielen += 2; + pmlmeext = &(padapter->mlmeextpriv); + pmlmeinfo = &(pmlmeext->mlmext_info); + pmlmepriv = &(padapter->mlmepriv); + pft_roam = &(pmlmepriv->ft_roam); + pframe = precv_frame->u.hdr.rx_data; + frame_len = precv_frame->u.hdr.len; + pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + category = pframe_body[0]; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); - p2pielen += 2; + if (category != RTW_WLAN_CATEGORY_FT) + goto exit; - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; + action_code = pframe_body[1]; + switch (action_code) { + case RTW_WLAN_ACTION_FT_RSP: + RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n"); + if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) { + RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2])); + goto exit; + } + status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + 14)); + if (status_code != 0) { + RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code); + goto exit; + } - /* Operating Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + _rtw_memcpy(tgt_addr, &pframe_body[8], ETH_ALEN); + if (is_zero_mac_addr(tgt_addr) || is_broadcast_mac_addr(tgt_addr)) { + RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(tgt_addr)); + goto exit; + } - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; + pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len); + if (pie) { + if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) { + RTW_ERR("FT: Invalid MDID\n"); + goto exit; + } + } - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA); + _cancel_timer_ex(&pmlmeext->ft_link_timer); - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; + /*Disconnect current AP*/ + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE); - /* Operating Class */ - if (pwdinfo->operating_channel <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; + pft_roam->ft_action_len = frame_len; + _rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ)); + ret = _SUCCESS; + break; + case RTW_WLAN_ACTION_FT_REQ: + case RTW_WLAN_ACTION_FT_CONF: + case RTW_WLAN_ACTION_FT_ACK: + #ifdef CONFIG_IOCTL_CFG80211 + sprintf(msg, "ACT_FT %u", action_code); + rtw_cfg80211_rx_action(padapter, precv_frame, msg); + #endif + break; + default: + RTW_ERR("FT: Unsupported FT Action!\n"); + break; } - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ +exit: + return ret; +#else + return _SUCCESS; +#endif +} - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *pframe = precv_frame->u.hdr.rx_data; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; -#ifdef CONFIG_WFD - wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; - pattrib->last_txcmdsz = pattrib->pktlen; + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_HT) + goto exit; - dump_mgntframe(padapter, pmgntframe); + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_HT_SM_PS: +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_AP_MODE + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]); +#endif /*CONFIG_AP_MODE*/ +#endif /*CONFIG_80211N_HT*/ + break; + case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING: +#ifdef CONFIG_BEAMFORMING + /*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/ + /*rtw_beamforming_get_report_frame(padapter, precv_frame);*/ +#endif /*CONFIG_BEAMFORMING*/ + break; + default: + break; + } - return; +exit: + return _SUCCESS; } - -void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result) +#ifdef CONFIG_IEEE80211W +unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame) { - struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_GO_NEGO_RESP; - u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u8 p2pielen = 0; - uint wpsielen = 0; - u16 wps_devicepassword_id = 0x0000; - uint wps_devicepassword_id_len = 0; - u16 len_channellist_attr = 0; - - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + u8 *pframe = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u16 tid; + /* Baron */ -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif + RTW_INFO("OnAction_sa_query\n"); - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; + switch (pframe[WLAN_HDR_A3_LEN + 1]) { + case 0: /* SA Query req */ + _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16)); + RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n" + , pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]); + issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY); + break; - RTW_INFO("[%s] In, result = %d\n", __FUNCTION__, result); - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + case 1: /* SA Query rsp */ + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta != NULL) + _cancel_timer_ex(&psta->dot11w_expire_timer); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16)); + RTW_INFO("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN + 1], tid); + break; + default: + break; + } + if (0) { + int pp; + printk("pattrib->pktlen = %d =>", pattrib->pkt_len); + for (pp = 0; pp < pattrib->pkt_len; pp++) + printk(" %02x ", pframe[pp]); + printk("\n"); + } - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + return _SUCCESS; +} +#endif /* CONFIG_IEEE80211W */ - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; +unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_RTW_80211K + return rm_on_action(padapter, precv_frame); +#else + return _SUCCESS; +#endif /* CONFIG_RTW_80211K */ +} - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); +unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_80211AC_VHT + u8 *pframe = precv_frame->u.hdr.rx_data; + struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + struct sta_info *psta = NULL; - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pwdinfo->negotiation_dialog_token = frame_body[7]; /* The Dialog Token of provisioning discovery request frame. */ - pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); - - /* Commented by Albert 20110328 */ - /* Try to get the device password ID from the WPS IE of group negotiation request frame */ - /* WiFi Direct test plan 5.1.15 */ - rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); - rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len); - wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id); - - _rtw_memset(wpsie, 0x00, 255); - wpsielen = 0; - - /* WPS Section */ - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; - - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; - - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ - - /* Device Password ID */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; - - /* Value: */ - if (wps_devicepassword_id == WPS_DPID_USER_SPEC) - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); - else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC); - else - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC); - wpsielen += 2; - - /* Commented by Kurt 20120113 */ - /* If some device wants to do p2p handshake without sending prov_disc_req */ - /* We have to get peer_req_cm from here. */ - if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) { - if (wps_devicepassword_id == WPS_DPID_USER_SPEC) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); - else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); - else - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); - } + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_VHT) + goto exit; - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING: +#ifdef CONFIG_BEAMFORMING + /*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/ + /*rtw_beamforming_get_report_frame(padapter, precv_frame);*/ +#endif /*CONFIG_BEAMFORMING*/ + break; + case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION: + /* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */ + /* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */ + psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); + if (psta) + rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta); + break; + case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT: +#ifdef CONFIG_BEAMFORMING + /*rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);*/ +#endif /* CONFIG_BEAMFORMING */ + break; + default: + break; + } +exit: +#endif /* CONFIG_80211AC_VHT */ - /* P2P IE Section. */ + return _SUCCESS; +} - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ +unsigned int OnAction_he(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ - /* Commented by Albert 20100908 */ - /* According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */ - /* 1. Status */ - /* 2. P2P Capability */ - /* 3. Group Owner Intent */ - /* 4. Configuration Timeout */ - /* 5. Operating Channel */ - /* 6. Intended P2P Interface Address */ - /* 7. Channel List */ - /* 8. Device Info */ - /* 9. Group ID ( Only GO ) */ + return _SUCCESS; +} +unsigned int OnAction_protected_he(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ - /* ToDo: */ + return _SUCCESS; +} - /* P2P Status */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_STATUS; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_P2P + u8 *frame_body; + u8 category, OUI_Subtype, dialogToken = 0; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - /* Value: */ - p2pie[p2pielen++] = result; + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + return _SUCCESS; - /* P2P Capability */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_P2P) + return _SUCCESS; - /* Value: */ - /* Device Capability Bitmap, 1 byte */ + if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI) + return _SUCCESS; - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { - /* Commented by Albert 2011/03/08 */ - /* According to the P2P specification */ - /* if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */ - p2pie[p2pielen++] = 0; - } else { - /* Be group owner or meet the error case */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + rtw_cfg80211_rx_action_p2p(padapter, precv_frame); + return _SUCCESS; } +#endif /* CONFIG_IOCTL_CFG80211 */ +#endif /* CONFIG_P2P */ - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; - else - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; - - /* Group Owner Intent */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GO_INTENT; + return _SUCCESS; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; +} - /* Value: */ - if (pwdinfo->peer_intent & 0x01) { - /* Peer's tie breaker bit is 1, our tie breaker bit should be 0 */ - p2pie[p2pielen++] = (pwdinfo->intent << 1); - } else { - /* Peer's tie breaker bit is 0, our tie breaker bit should be 1 */ - p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0)); - } +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT +unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame) +{ +#define TOKEN_REQ 0x00 +#define TOKEN_REL 0x01 + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + u32 xmit_time; + u8 *src=NULL, *pframe = precv_frame->u.hdr.rx_data; + u8 tbtx_action_code; + u8 i, nr_send; + uint tx_duration = 0; - /* Configuration Timeout */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + if (padapter->tbtx_capability == _FALSE) + goto exit; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; + tbtx_action_code = *(pframe + WLAN_HDR_A3_LEN + 1); - /* Value: */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ - /* Operating Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + switch (tbtx_action_code) + { + case TOKEN_REQ: + // parse duration + tx_duration = le32_to_cpu(*(uint *)(pframe + WLAN_HDR_A3_LEN + 2)); + padapter->tbtx_duration = tx_duration/1000; // Mirocsecond to Millisecond + ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE); + rtw_tx_control_cmd(padapter); + _set_timer(&pmlmeext->tbtx_xmit_timer, padapter->tbtx_duration); + ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE); +#if defined(CONFIG_SDIO_HCI) && !defined(CONFIG_SDIO_TX_TASKLET) + _rtw_up_sema(&pxmitpriv->SdioXmitSema); +#else + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#endif + break; +#ifdef CONFIG_AP_MODE + case TOKEN_REL: + src = get_addr2_ptr(pframe); + if (!src) + goto exit; + psta = rtw_get_stainfo(&padapter->stapriv, src); + if (!psta) + goto exit; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; + if (ATOMIC_READ(&pstapriv->nr_token_keeper) < 1) + goto exit; - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + for (i=0; i< NR_MAXSTA_INSLOT; i++) { + if (pstapriv->token_holder[i] == psta) { + pstapriv->token_holder[i] = NULL; + //RTW_INFO("macaddr1:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + ATOMIC_DEC(&pstapriv->nr_token_keeper); + break; + } + } - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; + if (ATOMIC_READ(&pstapriv->nr_token_keeper) == 0) + _set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1); - /* Operating Class */ - if (pwdinfo->operating_channel <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; + break; +#endif + default: + RTW_INFO("Undefined Action Code\n"); + goto exit; + break; } - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ +exit: + return _SUCCESS; +} - /* Intended P2P Interface Address */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; +void rtw_issue_action_token_rel(_adapter *padapter) +{ - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); - p2pielen += 2; + // Todo: + // gen token + /* Token Release Format + Category code : 1 Byte + Action code : 1 Byte */ + int ret = _FAIL; + //u16 *fctrl; + u8 val = 0x01; + u8 category = RTW_WLAN_CATEGORY_TBTX; + u8 *pframe; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + //struct sta_info *psta; + //struct sta_priv *pstapriv = &padapter->stapriv; + //struct registry_priv *pregpriv = &padapter->registrypriv; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /*update attribute */ + pattrib = &pmgntframe->attrib; + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_24MB); // issue action request using OFDM rate? 20190322 Bruce add + update_mgntframe_attrib(padapter, pattrib); - /* Channel List */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - /* Country String(3) */ - /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ - /* + number of channels in all classes */ - len_channellist_attr = 3 - + (1 + 1) * (u16)ch_list->reg_classes - + get_reg_classes_full_count(ch_list); + //fctrl = &(pwlanhdr->frame_ctl); + //*(fctrl) = 0; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1); - else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); -#else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); -#endif - p2pielen += 2; + // SetSeqNum?? + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen)); - /* Channel Entry List */ + pattrib->last_txcmdsz = pattrib->pktlen; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { + dump_mgntframe(padapter, pmgntframe); - u8 union_chan = rtw_mi_get_union_chan(padapter); + //RTW_INFO("%s\n", __func__); - /*Operating Class*/ - if (union_chan > 14) { - if (union_chan >= 149) - p2pie[p2pielen++] = 0x7c; - else - p2pie[p2pielen++] = 0x73; +} +#endif - } else - p2pie[p2pielen++] = 0x51; +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) +{ + int i; + unsigned char category; + struct action_handler *ptable; + unsigned char *frame_body; + u8 *pframe = precv_frame->u.hdr.rx_data; - /* Number of Channels - Just support 1 channel and this channel is AP's channel*/ - p2pie[p2pielen++] = 1; + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - /*Channel List*/ - p2pie[p2pielen++] = union_chan; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - int i, j; - for (j = 0; j < ch_list->reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; + category = frame_body[0]; - /* Number of Channels */ - p2pie[p2pielen++] = ch_list->reg_class[j].channels; + for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) { + ptable = &OnAction_tbl[i]; + + if (category == ptable->num) + ptable->func(padapter, precv_frame); - /* Channel List */ - for (i = 0; i < ch_list->reg_class[j].channels; i++) - p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; - } } - /* Device Info */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + return _SUCCESS; - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); - p2pielen += 2; +} - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) +{ - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ + /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */ + return _SUCCESS; +} - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm); +struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once) +{ + struct xmit_frame *pmgntframe; - p2pielen += 2; + if (once) + pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv); + else + pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv); - /* Primary Device Type */ - /* Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; + if (pmgntframe == NULL) { + RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once); + goto exit; + } +#if 0 /*CONFIG_CORE_XMITBUF*/ + struct xmit_buf *pxmitbuf; + pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv); + if (pxmitbuf == NULL) { + RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter)); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pmgntframe = NULL; + goto exit; + } - /* OUI */ - *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); - p2pielen += 4; + pmgntframe->frame_tag = MGNT_FRAMETAG; + pmgntframe->pxmitbuf = pxmitbuf; + pmgntframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pmgntframe; +#else + pmgntframe->frame_tag = MGNT_FRAMETAG; +#endif - /* Sub Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; +exit: + return pmgntframe; - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ +} - /* Device Name */ - /* Type: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - p2pielen += 2; +inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _FALSE); +} - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); - p2pielen += 2; +inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _TRUE); +} - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* Group ID Attribute */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; +/**************************************************************************** - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen); - p2pielen += 2; +Following are some TX fuctions for WiFi MLME - /* Value: */ - /* p2P Device Address */ - _rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN); - p2pielen += ETH_ALEN; +*****************************************************************************/ - /* SSID */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); - p2pielen += pwdinfo->nego_ssidlen; +void update_mgnt_tx_rate(_adapter *padapter, u8 rate) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - } + pmlmeext->tx_rate = rate; + /* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */ +} - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); -#ifdef CONFIG_WFD - wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif +void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + struct sta_info *bmc_sta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; - pattrib->last_txcmdsz = pattrib->pktlen; + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + bmc_sta = rtw_get_bcmc_stainfo(padapter); - dump_mgntframe(padapter, pmgntframe); + if (bmc_sta == NULL) { + RTW_ERR("%s bmc_sta=NULL\n", __func__); + return; + } - return; + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 7; + pattrib->mac_id = bmc_sta->phl_sta->macid; + pattrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID); -} + pattrib->pktlen = 0; -void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) -{ + if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) + wireless_mode = WLAN_MD_11B; + else + wireless_mode = WLAN_MD_11G; - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_GO_NEGO_CONF; - u8 p2pie[255] = { 0x00 }; - u8 p2pielen = 0; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#ifdef CONFIG_WFD - u32 wfdielen = 0; +#ifdef CONFIG_80211AC_VHT + pattrib->rate = MGN_VHT1SS_MCS9; +#else + pattrib->rate = MGN_MCS7; #endif - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - RTW_INFO("[%s] In\n", __FUNCTION__); - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + pattrib->qos_en = _FALSE; + pattrib->ht_en = 1; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = CHAN_OFFSET_NO_EXT; + pattrib->sgi = _FALSE; - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->seqnum = pmlmeext->mgnt_seq; - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); + pattrib->retry_ctrl = _TRUE; + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; +} - /* P2P IE Section. */ - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *bmc_sta = NULL; - /* Commented by Albert 20110306 */ - /* According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */ - /* 1. Status */ - /* 2. P2P Capability */ - /* 3. Operating Channel */ - /* 4. Channel List */ - /* 5. Group ID ( if this WiFi is GO ) */ +#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */ - /* P2P Status */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_STATUS; + /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; + bmc_sta = rtw_get_bcmc_stainfo(padapter); + if (bmc_sta == NULL) { + RTW_ERR("%s bmc_sta=NULL\n", __func__); + return; + } + pattrib->type = WIFI_MGT_TYPE; + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 8; + pattrib->mac_id = bmc_sta->phl_sta->macid; + pattrib->qsel = rtw_hal_get_qsel(padapter, QSLT_MGNT_ID); - /* Value: */ - p2pie[p2pielen++] = result; +#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE)) +#endif /* CONFIG_CONCURRENT_MODE */ + if (MLME_IS_GC(padapter)) { + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; - /* P2P Capability */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + /* use macid sleep during NoA, mgmt frame use ac queue & ap macid */ + pattrib->mac_id = psta->phl_sta->macid; + pattrib->qsel = rtw_hal_get_qsel(padapter, QSLT_VO_ID); + } else { + if (pwdinfo->p2p_ps_state != P2P_PS_DISABLE) + RTW_ERR("%s , psta was NULL\n", __func__); + } + } + } +#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */ - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + pattrib->pktlen = 0; - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + if (IS_CCK_RATE(pmlmeext->tx_rate)) + wireless_mode = WLAN_MD_11B; else - p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; + wireless_mode = WLAN_MD_11G; + pattrib->rate = pmlmeext->tx_rate; + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; - /* Operating Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + pattrib->qos_en = _FALSE; + pattrib->ht_en = _FALSE; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = CHAN_OFFSET_NO_EXT; + pattrib->sgi = _FALSE; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; + pattrib->seqnum = pmlmeext->mgnt_seq; - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + pattrib->retry_ctrl = _TRUE; - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; +} +void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + u8 *pframe; + struct pkt_attrib *pattrib = &pmgntframe->attrib; +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) + struct sta_info *sta = NULL; +#endif - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { - if (pwdinfo->peer_operating_ch <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; - } + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - p2pie[p2pielen++] = pwdinfo->peer_operating_ch; - } else { - if (pwdinfo->operating_channel <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; - } + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->operating_channel; /* Use the listen channel as the operating channel */ +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) + sta = pattrib->psta; + if (!sta) { + sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + pattrib->psta = sta; } +#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */ +} +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + #if 0 /*CONFIG_CORE_XMITBUF*/ + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + #endif + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return; + } - /* Channel List */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CH_LIST; - - *(u16 *)(p2pie + p2pielen) = 6; - p2pielen += 2; - - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; + /*rtw_hal_mgnt_xmit(padapter, pmgntframe);*/ + rtw_mgnt_xmit(padapter, pmgntframe); +} - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +{ + s32 ret = _FAIL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* Value: */ - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { - if (pwdinfo->peer_operating_ch <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; - } - p2pie[p2pielen++] = 1; - p2pie[p2pielen++] = pwdinfo->peer_operating_ch; - } else { - if (pwdinfo->operating_channel <= 14) { - /* Operating Class */ - p2pie[p2pielen++] = 0x51; - } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { - /* Operating Class */ - p2pie[p2pielen++] = 0x73; - } else { - /* Operating Class */ - p2pie[p2pielen++] = 0x7c; - } + #if 0 /*CONFIG_CORE_XMITBUF*/ + struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf; + struct submit_ctx sctx; + unsigned long sp_flags; - /* Channel Number */ - p2pie[p2pielen++] = 1; - p2pie[p2pielen++] = pwdinfo->operating_channel; /* Use the listen channel as the operating channel */ + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return ret; } - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* Group ID Attribute */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; + rtw_sctx_init(&sctx, timeout_ms); + pxmitbuf->sctx = &sctx; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen); - p2pielen += 2; + /*ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);*/ + ret = rtw_mgnt_xmit(padapter, pmgntframe); - /* Value: */ - /* p2P Device Address */ - _rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN); - p2pielen += ETH_ALEN; + if (ret == _SUCCESS) + ret = rtw_sctx_wait(&sctx, __func__); - /* SSID */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); - p2pielen += pwdinfo->nego_ssidlen; + _rtw_spinlock_irq(&pxmitpriv->lock_sctx, &sp_flags); + pxmitbuf->sctx = NULL; + _rtw_spinunlock_irq(&pxmitpriv->lock_sctx, &sp_flags); + #else + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return ret; } - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); - -#ifdef CONFIG_WFD - wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - - return; - + #endif + return ret; } -void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) +s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) { - struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_INVIT_REQ; - u8 p2pie[255] = { 0x00 }; - u8 p2pielen = 0; - u8 dialogToken = 3; - u16 len_channellist_attr = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif - - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#ifdef CONFIG_XMIT_ACK + static u8 seq_no = 0; + s32 ret = _FAIL; + struct xmit_priv *pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv; + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return -1; + } - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; + _rtw_mutex_lock_interruptible(&pxmitpriv->ack_tx_mutex); + pxmitpriv->ack_tx = _TRUE; + pxmitpriv->seq_no = seq_no++; + pmgntframe->ack_report = 1; + rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); + /*if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS)*/ + if (rtw_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) + ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + pxmitpriv->ack_tx = _FALSE; + _rtw_mutex_unlock(&pxmitpriv->ack_tx_mutex); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + return ret; +#else /* !CONFIG_XMIT_ACK */ + dump_mgntframe(padapter, pmgntframe); + rtw_msleep_os(50); + return _SUCCESS; +#endif /* !CONFIG_XMIT_ACK */ +} - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; +s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + /* In this case, use 500 ms as the default wait_ack timeout */ + return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500); +} - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; +#ifdef RTW_PHL_BCN //core ops +s32 rtw_core_issue_beacon(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct rtw_bcn_info_cmn *bcn_cmn = NULL; + struct pkt_attrib *pattrib = &pmgntframe->attrib; + u8 *pframe = (u8 *)(pmgntframe->buf_addr); + void *phl = padapter->dvobj->phl; - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + if(!wrole) + return _FAIL; - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + if(pattrib->pktlen > MAX_BCN_SIZE) + return _FAIL; - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + bcn_cmn = &wrole->bcn_cmn; - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - /* P2P IE Section. */ - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20101011 */ - /* According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */ - /* 1. Configuration Timeout */ - /* 2. Invitation Flags */ - /* 3. Operating Channel ( Only GO ) */ - /* 4. P2P Group BSSID ( Should be included if I am the GO ) */ - /* 5. Channel List */ - /* 6. P2P Group ID */ - /* 7. P2P Device Info */ - - /* Configuration Timeout */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; - - /* Value: */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ - - /* Invitation Flags */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; - - /* Value: */ - p2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT; - - - /* Operating Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; - - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Operating Class */ - if (pwdinfo->invitereq_info.operating_ch <= 14) - p2pie[p2pielen++] = 0x51; - else if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48)) - p2pie[p2pielen++] = 0x73; - else - p2pie[p2pielen++] = 0x7c; + _rtw_memcpy(bcn_cmn->bcn_buf, pframe, pattrib->pktlen); + bcn_cmn->bcn_length = pattrib->pktlen; - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch; /* operating channel number */ + { + u8 *pie_start, *pie_tim = NULL; + u32 total_ielen, tim_ielen = 0; - if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) { - /* P2P Group BSSID */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID; + pie_start = pframe + (sizeof(struct rtw_ieee80211_hdr_3addr) + _FIXED_IE_LENGTH_); + total_ielen = pattrib->pktlen - (sizeof(struct rtw_ieee80211_hdr_3addr) + _FIXED_IE_LENGTH_); - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); - p2pielen += 2; + pie_tim = rtw_get_ie(pie_start, _TIM_IE_, &tim_ielen, total_ielen); - /* Value: */ - /* P2P Device Address for GO */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN); - p2pielen += ETH_ALEN; + if(pie_tim) + bcn_cmn->ie_offset_tim = (u32)(pie_tim - pie_start) + _FIXED_IE_LENGTH_; } - /* Channel List */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + if(bcn_cmn->bcn_added) + rtw_phl_cmd_issue_beacon(phl, padapter->phl_role, bcn_cmn, PHL_CMD_DIRECTLY, 0); + else { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + _rtw_memcpy(bcn_cmn->bssid, get_my_bssid(cur_network), ETH_ALEN); + bcn_cmn->bcn_id = padapter->iface_id; + bcn_cmn->role_idx = wrole->id; + bcn_cmn->bcn_interval = pmlmeinfo->bcn_interval; + bcn_cmn->bcn_offload = (BIT(BCN_HW_SEQ) | BIT(BCN_HW_TIM)); + + if (pmlmeext->chandef.chan <= 14) + bcn_cmn->bcn_rate = RTW_DATA_RATE_CCK1; + else + bcn_cmn->bcn_rate = RTW_DATA_RATE_OFDM6; + rtw_phl_cmd_issue_beacon(phl, padapter->phl_role, bcn_cmn, PHL_CMD_DIRECTLY, 0); + bcn_cmn->bcn_added = 1; - /* Length: */ - /* Country String(3) */ - /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ - /* + number of channels in all classes */ - len_channellist_attr = 3 - + (1 + 1) * (u16)ch_list->reg_classes - + get_reg_classes_full_count(ch_list); + /* + [todo] + bcn_id: mbssid-ieee + bcn_offload: tbd + bcn_rate, 0=cck 1=ofdm, 2mac can NOT cck + */ + } -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1); - else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); -#else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + return _SUCCESS; +} #endif - p2pielen += 2; - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Channel Entry List */ -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - u8 union_ch = rtw_mi_get_union_chan(padapter); +int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) +{ + u8 *ssid_ie; + sint ssid_len_ori; + int len_diff = 0; - /* Operating Class */ - if (union_ch > 14) { - if (union_ch >= 149) - p2pie[p2pielen++] = 0x7c; - else - p2pie[p2pielen++] = 0x73; - } else - p2pie[p2pielen++] = 0x51; + ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); + /* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */ - /* Number of Channels */ - /* Just support 1 channel and this channel is AP's channel */ - p2pie[p2pielen++] = 1; + if (ssid_ie && ssid_len_ori > 0) { + switch (hidden_ssid_mode) { + case 1: { + u8 *next_ie = ssid_ie + 2 + ssid_len_ori; + u32 remain_len = 0; - /* Channel List */ - p2pie[p2pielen++] = union_ch; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - int i, j; - for (j = 0; j < ch_list->reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; + remain_len = ies_len - (next_ie - ies); - /* Number of Channels */ - p2pie[p2pielen++] = ch_list->reg_class[j].channels; + ssid_ie[1] = 0; + _rtw_memcpy(ssid_ie + 2, next_ie, remain_len); + len_diff -= ssid_len_ori; - /* Channel List */ - for (i = 0; i < ch_list->reg_class[j].channels; i++) - p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; + break; + } + case 2: + _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); + break; + default: + break; } } - - /* P2P Group ID */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen); - p2pielen += 2; - - /* Value: */ - /* P2P Device Address for GO */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN); - p2pielen += ETH_ALEN; - - /* SSID */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen); - p2pielen += pwdinfo->invitereq_info.ssidlen; - - - /* Device Info */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; - - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; - - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY); - p2pielen += 2; - - /* Primary Device Type */ - /* Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; - - /* OUI */ - *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); - p2pielen += 4; - - /* Sub Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; - - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ - - /* Device Name */ - /* Type: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - p2pielen += 2; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); - -#ifdef CONFIG_WFD - wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - - return; - + return len_diff; } -void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code) +void issue_beacon(_adapter *padapter, int timeout_ms) { - struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_INVIT_RESP; - u8 p2pie[255] = { 0x00 }; - u8 p2pielen = 0; - u16 len_channellist_attr = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif - - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int rate_len; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +#ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P */ + + /* RTW_INFO("%s\n", __FUNCTION__); */ +#if 0 /*def CONFIG_BCN_ICF*/ + pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv); + if (pmgntframe == NULL) +#else pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) +#endif + { + RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); return; + } +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + _rtw_spinlock_bh(&pmlmepriv->bcn_update_lock); +#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = rtw_hal_get_qsel(padapter,QSLT_BEACON_ID); + +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->hw_port == HW_PORT1) + pattrib->mbssid = 1; +#endif _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + /* pmlmeext->mgnt_seq++; */ + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - /* P2P IE Section. */ - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20101005 */ - /* According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */ - /* 1. Status */ - /* 2. Configuration Timeout */ - /* 3. Operating Channel ( Only GO ) */ - /* 4. P2P Group BSSID ( Only GO ) */ - /* 5. Channel List */ - - /* P2P Status */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_STATUS; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); - p2pielen += 2; - - /* Value: */ - /* When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */ - /* Sent the event receiving the P2P Invitation Req frame to DMP UI. */ - /* DMP had to compare the MAC address to find out the profile. */ - /* So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */ - /* If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */ - /* to NB to rebuild the persistent group. */ - p2pie[p2pielen++] = status_code; - - /* Configuration Timeout */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; - - /* Value: */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ - p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ - - if (status_code == P2P_STATUS_SUCCESS) { - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */ - /* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */ - /* First one is operating channel attribute. */ - /* Second one is P2P Group BSSID attribute. */ - - /* Operating Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; - - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Operating Class */ - p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ - - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ - - - /* P2P Group BSSID */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID; + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ +#ifdef CONFIG_P2P + /* for P2P : Primary Device Type & Device Name */ + u32 wpsielen = 0, insert_len = 0; + u8 *wpsie = NULL; + wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen); - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); - p2pielen += 2; + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) { + uint wps_offset, remainder_ielen; + u8 *premainder_ie, *pframe_wscie; - /* Value: */ - /* P2P Device Address for GO */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; + wps_offset = (uint)(wpsie - cur_network->IEs); - } + premainder_ie = wpsie + wpsielen; - /* Channel List */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + remainder_ielen = cur_network->IELength - wps_offset - wpsielen; - /* Length: */ - /* Country String(3) */ - /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ - /* + number of channels in all classes */ - len_channellist_attr = 3 - + (1 + 1) * (u16)ch_list->reg_classes - + get_reg_classes_full_count(ch_list); +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) { +#ifdef ROKU_PRIVATE + /* if no feature need to show ssid, hide GO ssid in beacon */ + struct registry_priv *pregpriv = &padapter->registrypriv; + int len_diff; + u8 hide_ssid = 0; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1); - else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); -#else - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && pregpriv->go_hidden_ssid_mode == ALL_HIDE_SSID) + hide_ssid = 1; #endif - p2pielen += 2; - - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Channel Entry List */ -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - - /* Operating Class */ - if (union_ch > 14) { - if (union_ch >= 149) - p2pie[p2pielen++] = 0x7c; - else - p2pie[p2pielen++] = 0x73; - } else - p2pie[p2pielen++] = 0x51; - - - /* Number of Channels */ - /* Just support 1 channel and this channel is AP's channel */ - p2pie[p2pielen++] = 1; - - /* Channel List */ - p2pie[p2pielen++] = union_ch; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - int i, j; - for (j = 0; j < ch_list->reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; + _rtw_memcpy(pframe, cur_network->IEs, wps_offset); +#ifdef ROKU_PRIVATE + len_diff = update_hidden_ssid( + pframe + _BEACON_IE_OFFSET_ + , wps_offset - _BEACON_IE_OFFSET_ + , hide_ssid); + pframe += len_diff; + pattrib->pktlen += len_diff; +#endif + pframe += wps_offset; + pattrib->pktlen += wps_offset; - /* Number of Channels */ - p2pie[p2pielen++] = ch_list->reg_class[j].channels; + _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); + pframe += pmlmepriv->wps_beacon_ie_len; + pattrib->pktlen += pmlmepriv->wps_beacon_ie_len; - /* Channel List */ - for (i = 0; i < ch_list->reg_class[j].channels; i++) - p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; + /* copy remainder_ie to pframe */ + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } else { + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pattrib->pktlen += cur_network->IELength; + } } +#endif /* CONFIG_IOCTL_CFG80211 */ + } else +#endif /* CONFIG_P2P */ + { + int len_diff; + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + len_diff = update_hidden_ssid( + pframe + _BEACON_IE_OFFSET_ + , cur_network->IELength - _BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + pframe += (cur_network->IELength + len_diff); + pattrib->pktlen += (cur_network->IELength + len_diff); } - } - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + { + u8 *wps_ie; + uint wps_ielen; + u8 sr = 0; + wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, + pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen); + if (wps_ie && wps_ielen > 0) + rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); + if (sr != 0) + set_fwstate(pmlmepriv, WIFI_UNDER_WPS); + else + _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); + } +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_beacon_ies(padapter, &pframe, pattrib); +#endif +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + u32 len = 0; +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + len = pmlmepriv->p2p_beacon_ie_len; + if (pmlmepriv->p2p_beacon_ie && len > 0) { + _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len); + pframe += len; + pattrib->pktlen += len; + } + } +#endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_WFD - wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; + len = rtw_append_beacon_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; #endif + } +#endif /* CONFIG_P2P */ - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - - return; +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_BEACON_VENDOR_IE_BIT); +#endif -} -void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr) -{ - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u8 dialogToken = 1; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_PROVISION_DISC_REQ; - u8 wpsie[100] = { 0x00 }; - u8 wpsielen = 0; - u32 p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (padapter->tbtx_capability == _TRUE) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen); #endif - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + goto _issue_bcn; + } - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; + /* below for ad-hoc mode */ - RTW_INFO("[%s] In\n", __FUNCTION__); - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + /* beacon interval: 2 bytes */ - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + pframe += 2; + pattrib->pktlen += 2; - _rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN); + /* capability info: 2 bytes */ - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += 2; + pattrib->pktlen += 2; - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); - p2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr); + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); - pframe += p2pielen; - pattrib->pktlen += p2pielen; + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; + /* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */ + { + u8 erpinfo = 0; + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; + /* ERP IE */ + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); - /* Config Method */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); - wpsielen += 2; - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; + /* todo:HT for adhoc */ - /* Value: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request); - wpsielen += 2; +_issue_bcn: - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + pmlmepriv->update_bcn = _FALSE; + _rtw_spinunlock_bh(&pmlmepriv->bcn_update_lock); +#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ -#ifdef CONFIG_WFD - wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif + if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) { + RTW_ERR("beacon frame too large ,len(%d,%d)\n", + (pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN); + rtw_warn_on(1); + return; + } pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(padapter, pmgntframe); - - return; - -} - - -u8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo) -{ - u8 i, match_result = 0; - - RTW_INFO("[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, - peermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]); + /* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */ + +#ifdef RTW_PHL_BCN + rtw_core_issue_beacon(padapter, pmgntframe); - for (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) { - RTW_INFO("[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, - profileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]); - if (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) { - match_result = 1; - RTW_INFO("[%s] Match!\n", __FUNCTION__); - break; - } - } + #if 0 /*CONFIG_CORE_XMITBUF*/ + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + #endif + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); +#else + if (timeout_ms > 0) + dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms); + else + dump_mgntframe(padapter, pmgntframe); +#endif - return match_result ; } -void issue_probersp_p2p(_adapter *padapter, unsigned char *da) +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; - unsigned char *mac; + unsigned char *mac, *bssid; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + u8 *pwps_ie; + uint wps_ielen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ - u16 beacon_interval = 100; - u16 capInfo = 0; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned int rate_len; +#ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 wpsie[255] = { 0x00 }; - u32 wpsielen = 0, p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif +#endif /* CONFIG_P2P */ /* RTW_INFO("%s\n", __FUNCTION__); */ + if (da == NULL) + return; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) + if (pmgntframe == NULL) { + RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); return; + } + /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - if (IS_CCK_RATE(pattrib->rate)) { - /* force OFDM 6M rate */ - pattrib->rate = MGN_6M; - pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); - } - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; mac = adapter_mac_addr(padapter); + bssid = cur_network->MacAddress; fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - - /* Use the device address for BSSID field. */ - _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; @@ -6007,232 +6216,196 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da) pattrib->pktlen = pattrib->hdrlen; pframe += pattrib->hdrlen; - /* timestamp will be inserted by hardware */ - pframe += 8; - pattrib->pktlen += 8; - - /* beacon interval: 2 bytes */ - _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); - pframe += 2; - pattrib->pktlen += 2; - /* capability info: 2 bytes */ - /* ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */ - capInfo |= cap_ShortPremble; - capInfo |= cap_ShortSlot; + if (cur_network->IELength > MAX_IE_SZ) + return; - _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); - pframe += 2; - pattrib->pktlen += 2; +#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen); + /* inerset & update wps_probe_resp_ie */ + if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) { + uint wps_offset, remainder_ielen; + u8 *premainder_ie; - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); + wps_offset = (uint)(pwps_ie - cur_network->IEs); - /* supported rates... */ - /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */ - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + premainder_ie = pwps_ie + wps_ielen; - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); + remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) { - /* WPS IE */ - _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); - pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len; - pframe += pmlmepriv->wps_probe_resp_ie_len; + _rtw_memcpy(pframe, cur_network->IEs, wps_offset); + pframe += wps_offset; + pattrib->pktlen += wps_offset; - /* P2P IE */ - _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); - pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len; - pframe += pmlmepriv->p2p_probe_resp_ie_len; - } - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - - /* Todo: WPS IE */ - /* Noted by Albert 20100907 */ - /* According to the WPS specification, all the WPS attribute is presented by Big Endian. */ - - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; - - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; - - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ - - /* WiFi Simple Config State */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE); - wpsielen += 2; + wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */ + if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2); + pframe += wps_ielen + 2; + pattrib->pktlen += wps_ielen + 2; + } - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; + if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + } else { + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pattrib->pktlen += cur_network->IELength; + } - /* Value: */ - wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; /* Not Configured. */ + /* retrieve SSID IE from cur_network->Ssid */ + { + u8 *ssid_ie; + sint ssid_ielen; + sint ssid_ielen_diff; + u8 buf[MAX_IE_SZ]; + u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr); - /* Response Type */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE); - wpsielen += 2; + ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, + (pframe - ies) - _FIXED_IE_LENGTH_); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; + ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; - /* Value: */ - wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X; + if (ssid_ie && cur_network->Ssid.SsidLength) { + uint remainder_ielen; + u8 *remainder_ie; + remainder_ie = ssid_ie + 2; + remainder_ielen = (pframe - remainder_ie); - /* UUID-E */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E); - wpsielen += 2; + if (remainder_ielen > MAX_IE_SZ) { + RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter)); + remainder_ielen = MAX_IE_SZ; + } - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010); - wpsielen += 2; + _rtw_memcpy(buf, remainder_ie, remainder_ielen); + _rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen); + *(ssid_ie + 1) = cur_network->Ssid.SsidLength; + _rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); - /* Value: */ - if (pwdinfo->external_uuid == 0) { - _rtw_memset(wpsie + wpsielen, 0x0, 16); - _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); - } else - _rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10); - wpsielen += 0x10; + pframe += ssid_ielen_diff; + pattrib->pktlen += ssid_ielen_diff; + } + } - /* Manufacturer */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER); - wpsielen += 2; +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBERESP_VENDOR_IE_BIT); +#endif + } else +#endif + { - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007); - wpsielen += 2; + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; - /* Value: */ - _rtw_memcpy(wpsie + wpsielen, "Realtek", 7); - wpsielen += 7; + /* beacon interval: 2 bytes */ - /* Model Name */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME); - wpsielen += 2; + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006); - wpsielen += 2; + pframe += 2; + pattrib->pktlen += 2; - /* Value: */ - _rtw_memcpy(wpsie + wpsielen, "8192CU", 6); - wpsielen += 6; + /* capability info: 2 bytes */ - /* Model Number */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER); - wpsielen += 2; + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; + pframe += 2; + pattrib->pktlen += 2; - /* Value: */ - wpsie[wpsielen++] = 0x31; /* character 1 */ + /* below for ad-hoc mode */ - /* Serial Number */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER); - wpsielen += 2; + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN); - wpsielen += 2; + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); - /* Value: */ - _rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN); - wpsielen += ETH_ALEN; + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); - /* Primary Device Type */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); - wpsielen += 2; + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u8 erpinfo = 0; + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008); - wpsielen += 2; + /* ERP IE */ + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } - /* Value: */ - /* Category ID */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - wpsielen += 2; - /* OUI */ - *(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI); - wpsielen += 4; + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); - /* Sub Category ID */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - wpsielen += 2; - /* Device Name */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - wpsielen += 2; + /* todo:HT for adhoc */ - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len); - wpsielen += 2; + } - /* Value: */ - _rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len); - wpsielen += pwdinfo->device_name_len; +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_probe_rsp_ies(padapter, &pframe, pattrib); +#endif +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) + /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ + && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) { + u32 len = 0; +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + /* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */ + len = pmlmepriv->p2p_go_probe_resp_ie_len; + if (pmlmepriv->p2p_go_probe_resp_ie && len > 0) { + _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); + pframe += len; + pattrib->pktlen += len; + } + } +#endif /* CONFIG_IOCTL_CFG80211 */ +#ifdef CONFIG_WFD + len = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; +#endif + } +#endif /* CONFIG_P2P */ - /* Config Method */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); - wpsielen += 2; - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; +#ifdef CONFIG_AUTO_AP_MODE + { + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; - /* Value: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm); - wpsielen += 2; + RTW_INFO("(%s)\n", __FUNCTION__); + /* check rc station */ + psta = rtw_get_stainfo(pstapriv, da); + if (psta && psta->isrc && psta->pid > 0) { + u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A}; + u8 RC_INFO[14] = {0}; + /* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */ + u16 cu_ch = (u16)cur_network->Configuration.DSConfig; - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__, + psta->pid, MAC_ARG(psta->phl_sta->mac_addr), cu_ch); + /* append vendor specific ie */ + _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI)); + _rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN); + _rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2); + _rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2); - p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe); - pframe += p2pielen; - pattrib->pktlen += p2pielen; + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen); + } } - -#ifdef CONFIG_WFD - wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif - -/* Vendor Specific IE */ -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBERESP_VENDOR_IE_BIT); -#endif +#endif /* CONFIG_AUTO_AP_MODE */ pattrib->last_txcmdsz = pattrib->pktlen; @@ -6243,7 +6416,7 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da) } -int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) +int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -6252,18 +6425,18 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; unsigned char *mac; + unsigned char bssrate[NumRates]; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + int bssrate_len = 0; u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u16 wpsielen = 0, p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); #endif - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -6273,304 +6446,117 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - if (IS_CCK_RATE(pattrib->rate)) { - /* force OFDM 6M rate */ - pattrib->rate = MGN_6M; - pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); - } _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (MLME_IS_STA(padapter)) + && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) + mac = pwdev_priv->pno_mac_addr; + else +#endif mac = adapter_mac_addr(padapter); fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; if (da) { + /* unicast probe request frame */ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); } else { - if ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) { - /* This two flags will be set when this is only the P2P client mode. */ - _rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); - } else { - /* broadcast probe request frame */ - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); - } + /* broadcast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); } + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (MLME_IS_STA(padapter)) + && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) { +#ifdef CONFIG_RTW_DEBUG + RTW_DBG("%s pno_scan_seq_num: %d\n", __func__, + pwdev_priv->pno_scan_seq_num); +#endif + SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num); + pattrib->seqnum = pwdev_priv->pno_scan_seq_num; + pattrib->qos_en = 1; + pwdev_priv->pno_scan_seq_num++; + } else +#endif + { + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + } set_frame_sub_type(pframe, WIFI_PROBEREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) - pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen)); + if (pssid && !MLME_IS_MESH(padapter)) + pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); else - pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); - /* Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */ - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - if (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) { - /* WPS IE */ - _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); - pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; - pframe += pmlmepriv->wps_probe_req_ie_len; + get_rate_set(padapter, bssrate, &bssrate_len); - /* P2P IE */ - _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len); - pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len; - pframe += pmlmepriv->p2p_probe_req_ie_len; - } + if (bssrate_len > 8) { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - - /* WPS IE */ - /* Noted by Albert 20110221 */ - /* According to the WPS specification, all the WPS attribute is presented by Big Endian. */ - - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; - - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; - - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ - - if (pmlmepriv->wps_probe_req_ie == NULL) { - /* UUID-E */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010); - wpsielen += 2; - - /* Value: */ - if (pwdinfo->external_uuid == 0) { - _rtw_memset(wpsie + wpsielen, 0x0, 16); - _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); - } else - _rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10); - wpsielen += 0x10; + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); - /* Config Method */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); - wpsielen += 2; + if (ch) + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (pssid) + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength); + else + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0); + } +#endif - /* Value: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm); - wpsielen += 2; + if (append_wps) { + /* add wps_ie for wps2.0 */ + if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); + pframe += pmlmepriv->wps_probe_req_ie_len; + pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; + /* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */ } + } +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBEREQ_VENDOR_IE_BIT); +#endif - /* Device Name */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len); - wpsielen += 2; - - /* Value: */ - _rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len); - wpsielen += pwdinfo->device_name_len; - - /* Primary Device Type */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008); - wpsielen += 2; - - /* Value: */ - /* Category ID */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI); - wpsielen += 2; - - /* OUI */ - *(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI); - wpsielen += 4; - - /* Sub Category ID */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP); - wpsielen += 2; - - /* Device Password ID */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; - - /* Value: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); /* Registrar-specified */ - wpsielen += 2; - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20110221 */ - /* According to the P2P Specification, the probe request frame should contain 5 P2P attributes */ - /* 1. P2P Capability */ - /* 2. P2P Device ID if this probe request wants to find the specific P2P device */ - /* 3. Listen Channel */ - /* 4. Extended Listen Timing */ - /* 5. Operating Channel if this WiFi is working as the group owner now */ - - /* P2P Capability */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; - - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; - - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; - else - p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; - - /* Listen Channel */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH; +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_probe_req_ies(padapter, &pframe, pattrib); +#endif + pattrib->last_txcmdsz = pattrib->pktlen; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Operating Class */ - p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ - - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->listen_channel; /* listen channel */ - - - /* Extended Listen Timing */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); - p2pielen += 2; - - /* Value: */ - /* Availability Period */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; - - /* Availability Interval */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* Operating Channel (if this WiFi is working as the group owner now) */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); - p2pielen += 2; - - /* Value: */ - /* Country String */ - p2pie[p2pielen++] = 'X'; - p2pie[p2pielen++] = 'X'; - - /* The third byte should be set to 0x04. */ - /* Described in the "Operating Channel Attribute" section. */ - p2pie[p2pielen++] = 0x04; - - /* Operating Class */ - p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ - - /* Channel Number */ - p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ - - } - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); - - } - -#ifdef CONFIG_WFD - wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif - -/* Vendor Specific IE */ -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBEREQ_VENDOR_IE_BIT); -#endif - - pattrib->last_txcmdsz = pattrib->pktlen; - - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } exit: return ret; } -inline void issue_probereq_p2p(_adapter *adapter, u8 *da) +inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da) { - _issue_probereq_p2p(adapter, da, _FALSE); + _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); } /* @@ -6578,18 +6564,22 @@ inline void issue_probereq_p2p(_adapter *adapter, u8 *da) * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX * try_cnt means the maximal TX count to try */ -int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) +int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, + int try_cnt, int wait_ms) { - int ret; + int ret = _FAIL; int i = 0; systime start = rtw_get_current_time(); + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + do { - ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE); + ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE); i++; - if (RTW_CANNOT_RUN(adapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) break; if (i < try_cnt && wait_ms > 0 && ret == _FAIL) @@ -6607,1952 +6597,1575 @@ int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) if (try_cnt && wait_ms) { if (da) RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter), + FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); else RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter), + FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); } exit: return ret; } -#endif /* CONFIG_P2P */ - -s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset) +/* if psta == NULL, indiate we are station(client) now... */ +void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status) { - _adapter *adapter = rframe->u.hdr.adapter; - struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); - u8 *frame = rframe->u.hdr.rx_data; - u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf); - u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset); - - if (GetRetry(frame)) { - if ((seq_ctrl == mlmeext->action_public_rxseq) - && (token == mlmeext->action_public_dialog_token) - ) { - RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n", - FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token); - return _FAIL; - } - } - - /* TODO: per sta seq & token */ - mlmeext->action_public_rxseq = seq_ctrl; - mlmeext->action_public_dialog_token = token; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int val32; + unsigned short val16; + int use_shared_key = 0; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; - return _SUCCESS; -} + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; -unsigned int on_action_public_p2p(union recv_frame *precv_frame) -{ - _adapter *padapter = precv_frame->u.hdr.adapter; - u8 *pframe = precv_frame->u.hdr.rx_data; - uint len = precv_frame->u.hdr.len; - u8 *frame_body; -#ifdef CONFIG_P2P - u8 *p2p_ie; - u32 p2p_ielen; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 result = P2P_STATUS_SUCCESS; - u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - u8 *merged_p2pie = NULL; - u32 merged_p2p_ielen = 0; -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; -#endif -#endif /* CONFIG_P2P */ + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; - frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); -#ifdef CONFIG_P2P - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) - rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame); - else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - /* Do nothing if the driver doesn't enable the P2P function. */ - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) - return _SUCCESS; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - len -= sizeof(struct rtw_ieee80211_hdr_3addr); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - switch (frame_body[6]) { /* OUI Subtype */ - case P2P_GO_NEGO_REQ: { - RTW_INFO("[%s] Got GO Nego Req Frame\n", __FUNCTION__); - _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_AUTH); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) { - /* Commented by Albert 20110526 */ - /* In this case, this means the previous nego fail doesn't be reset yet. */ - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - /* Restore the previous p2p state */ - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); - RTW_INFO("[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); - } -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE)) - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); -#endif /* CONFIG_CONCURRENT_MODE */ + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* Commented by Kurt 20110902 */ - /* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - /* Commented by Kurt 20120113 */ - /* Get peer_dev_addr here if peer doesn't issue prov_disc frame. */ - if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN)) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); + if (psta) { /* for AP mode */ +#ifdef CONFIG_NATIVEAP_MLME - result = process_p2p_group_negotation_req(pwdinfo, frame_body, len); - issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result); + _rtw_memcpy(pwlanhdr->addr1, psta->phl_sta->mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); - /* Commented by Albert 20110718 */ - /* No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */ -#ifdef CONFIG_CONCURRENT_MODE - /* Commented by Albert 20120107 */ - _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); -#else /* CONFIG_CONCURRENT_MODE */ - _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); -#endif /* CONFIG_CONCURRENT_MODE */ - break; - } - case P2P_GO_NEGO_RESP: { - RTW_INFO("[%s] Got GO Nego Resp Frame\n", __FUNCTION__); - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { - /* Commented by Albert 20110425 */ - /* The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */ - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - pwdinfo->nego_req_info.benable = _FALSE; - result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len); - issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result); - if (P2P_STATUS_SUCCESS == result) { - if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) { - pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch; -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->p2p_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ - pwdinfo->p2p_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ - pwdinfo->p2p_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->p2p_info.scan_op_ch_only = 1; - _set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH); - } - } - /* Reset the dialog token for group negotiation frames. */ - pwdinfo->negotiation_dialog_token = 1; + /* setting auth algo number */ + val16 = (u16)psta->authalg; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) - _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); - } else - RTW_INFO("[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__); + if (status != _STATS_SUCCESSFUL_) + val16 = 0; - break; - } - case P2P_GO_NEGO_CONF: { - RTW_INFO("[%s] Got GO Nego Confirm Frame\n", __FUNCTION__); - result = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len); - if (P2P_STATUS_SUCCESS == result) { - if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) { - pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch; -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->p2p_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ - pwdinfo->p2p_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ - pwdinfo->p2p_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->p2p_info.scan_op_ch_only = 1; - _set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH); - } - } - break; + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; } - case P2P_INVIT_REQ: { - /* Added by Albert 2010/10/05 */ - /* Received the P2P Invite Request frame. */ - - RTW_INFO("[%s] Got invite request frame!\n", __FUNCTION__); - p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); - if (p2p_ie) { - /* Parse the necessary information from the P2P Invitation Request frame. */ - /* For example: The MAC address of sending this P2P Invitation Request frame. */ - u32 attr_contentlen = 0; - u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - struct group_id_info group_id; - u8 invitation_flag = 0; - - merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_); - - merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2); /* 2 is for EID and Length */ - if (merged_p2pie == NULL) { - RTW_INFO("[%s] Malloc p2p ie fail\n", __FUNCTION__); - goto exit; - } - _rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen); - - merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie); - - rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen); - if (attr_contentlen) { - rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen); - /* Commented by Albert 20120510 */ - /* Copy to the pwdinfo->p2p_peer_interface_addr. */ - /* So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */ - /* #> iwpriv wlan0 p2p_get peer_ifa */ - /* After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */ + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - if (attr_contentlen) { - RTW_INFO("[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], - pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3], - pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); - } + /* setting auth seq number */ + val16 = (u16)psta->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - if (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) { - /* Re-invoke the persistent group. */ - - _rtw_memset(&group_id, 0x00, sizeof(struct group_id_info)); - rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen); - if (attr_contentlen) { - if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) { - /* The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - status_code = P2P_STATUS_SUCCESS; - } else { - /* The p2p device sending this p2p invitation request wants to be the persistent GO. */ - if (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) { - u8 operatingch_info[5] = { 0x00 }; - if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, - &attr_contentlen)) { - if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) { - /* The operating channel is acceptable for this device. */ - pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4]; -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->rx_invitereq_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ - pwdinfo->rx_invitereq_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ - pwdinfo->rx_invitereq_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->rx_invitereq_info.scan_op_ch_only = 1; - _set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - status_code = P2P_STATUS_SUCCESS; - } else { - /* The operating channel isn't supported by this device. */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - status_code = P2P_STATUS_FAIL_NO_COMMON_CH; - _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); - } - } else { - /* Commented by Albert 20121130 */ - /* Intel will use the different P2P IE to store the operating channel information */ - /* Workaround for Intel WiDi 3.5 */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - status_code = P2P_STATUS_SUCCESS; - } - } else { - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); - status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; - } - } - } else { - RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__); - status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - } - } else { - /* Received the invitation to join a P2P group. */ - - _rtw_memset(&group_id, 0x00, sizeof(struct group_id_info)); - rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen); - if (attr_contentlen) { - if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) { - /* In this case, the GO can't be myself. */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); - status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - } else { - /* The p2p device sending this p2p invitation request wants to join an existing P2P group */ - /* Commented by Albert 2012/06/28 */ - /* In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */ - /* The peer device address should be the destination address for the provisioning discovery request. */ - /* Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. */ - /* The peer interface address should be the address for WPS mac address */ - _rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN); - status_code = P2P_STATUS_SUCCESS; - } - } else { - RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__); - status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - } - } - } else { - RTW_INFO("[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__); - status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - } + /* setting status code... */ + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); - RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code); + /* added challenging text... */ + if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); +#endif + } else { + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - pwdinfo->inviteresp_info.token = frame_body[7]; - issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code); - _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter)) { + /* 2: 802.11R FTAA */ + val16 = cpu_to_le16(WLAN_AUTH_FT); + } else +#endif + { + /* setting auth algo number */ + val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */ + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; } - break; } - case P2P_INVIT_RESP: { - u8 attr_content = 0x00; - u32 attr_contentlen = 0; - RTW_INFO("[%s] Got invite response frame!\n", __FUNCTION__); - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); - if (p2p_ie) { - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + /* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */ - if (attr_contentlen == 1) { - RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); - pwdinfo->invitereq_info.benable = _FALSE; + /* setting IV for auth seq #3 */ + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { + /* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */ + val32 = ((pmlmeinfo->iv++) | (psecuritypriv->dot11PrivacyKeyIndex << 30)); + val32 = cpu_to_le32(val32); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); - if (attr_content == P2P_STATUS_SUCCESS) { - if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN)) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - else - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + pattrib->iv_len = 4; + } - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK); - } else { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); - } - } else { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); - } - } else { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); - } + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL)) - _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); - break; - } - case P2P_DEVDISC_REQ: + /* setting auth seq number */ + val16 = pmlmeinfo->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - process_p2p_devdisc_req(pwdinfo, pframe, len); - break; + /* setting status code... */ + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); - case P2P_DEVDISC_RESP: +#ifdef CONFIG_RTW_80211R + rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe); +#endif - process_p2p_devdisc_resp(pwdinfo, pframe, len); + /* then checking to see if sending challenging text... */ + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); - break; + SetPrivacy(fctrl); - case P2P_PROVISION_DISC_REQ: - RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__); - process_p2p_provdisc_req(pwdinfo, pframe, len); - _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* 20110902 Kurt */ - /* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + pattrib->encrypt = _WEP40_; - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ); - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); - break; + pattrib->icv_len = 4; - case P2P_PROVISION_DISC_RESP: - /* Commented by Albert 20110707 */ - /* Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */ - RTW_INFO("[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__); - /* Commented by Albert 20110426 */ - /* The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */ - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP); - process_p2p_provdisc_resp(pwdinfo, pframe); - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); - break; + pattrib->pktlen += pattrib->icv_len; + pattrib->bswenc = _TRUE; } + } + pattrib->last_txcmdsz = pattrib->pktlen; -exit: + rtw_wep_encrypt(padapter, (u8 *)pmgntframe); + RTW_INFO("%s\n", __FUNCTION__); + dump_mgntframe(padapter, pmgntframe); - if (merged_p2pie) - rtw_mfree(merged_p2pie, merged_p2p_ielen + 2); -#endif /* CONFIG_P2P */ - return _SUCCESS; + return; } -unsigned int on_action_public_vendor(union recv_frame *precv_frame) + +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) { - unsigned int ret = _FAIL; - u8 *pframe = precv_frame->u.hdr.rx_data; - u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - _adapter *adapter = precv_frame->u.hdr.adapter; - int cnt = 0; - char msg[64]; +#ifdef CONFIG_AP_MODE + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + unsigned char *pbuf, *pframe; + unsigned short val, ie_status; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 *ie = pnetwork->IEs; + uint ie_len = 0; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#endif /* CONFIG_P2P */ +#ifdef CONFIG_RTW_MBO + u8 WIFI_ALLIANCE_OUI[] = {0x50, 0x6f, 0x9a}; +#endif /* CONFIG_RTW_MBO */ - if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { - if (rtw_action_public_decache(precv_frame, 7) == _FAIL) - goto exit; + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; - if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST)) - rtw_rframe_del_wfd_ie(precv_frame, 8); + RTW_INFO("%s\n", __FUNCTION__); - ret = on_action_public_p2p(precv_frame); - } else if (_rtw_memcmp(frame_body + 2, DPP_OUI, 4) == _TRUE) { - u8 dpp_type = frame_body[7]; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; -#ifdef CONFIG_IOCTL_CFG80211 - cnt += sprintf((msg + cnt), "DPP(type:%u)", dpp_type); - rtw_cfg80211_rx_action(adapter, precv_frame, msg); -#endif - } + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); -exit: - return ret; -} -unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) -{ - unsigned int ret = _FAIL; - u8 *pframe = precv_frame->u.hdr.rx_data; - u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - u8 token; - _adapter *adapter = precv_frame->u.hdr.adapter; - int cnt = 0; - char msg[64]; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - token = frame_body[2]; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - if (rtw_action_public_decache(precv_frame, 2) == _FAIL) - goto exit; + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; -#ifdef CONFIG_IOCTL_CFG80211 - cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token); - rtw_cfg80211_rx_action(adapter, precv_frame, msg); -#endif + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->phl_sta->mac_addr, ETH_ALEN); + _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - ret = _SUCCESS; -exit: - return ret; -} + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) + set_frame_sub_type(pwlanhdr, pkt_type); + else + return; -unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) -{ - unsigned int ret = _FAIL; - u8 *pframe = precv_frame->u.hdr.rx_data; - uint frame_len = precv_frame->u.hdr.len; - u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - u8 category, action; + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen += pattrib->hdrlen; + pframe += pattrib->hdrlen; - /* check RA matches or broadcast */ - if (!(_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN) || - is_broadcast_mac_addr(GetAddr1Ptr(pframe)))) - goto exit; + /* capability */ + val = *(unsigned short *)rtw_get_capability_from_ie(ie); - category = frame_body[0]; - if (category != RTW_WLAN_CATEGORY_PUBLIC) - goto exit; + pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); - action = frame_body[1]; - switch (action) { - case ACT_PUBLIC_BSSCOEXIST: -#ifdef CONFIG_80211N_HT -#ifdef CONFIG_AP_MODE - /*20/40 BSS Coexistence Management frame is a Public Action frame*/ - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - rtw_process_public_act_bsscoex(padapter, pframe, frame_len); -#endif /*CONFIG_AP_MODE*/ -#endif /*CONFIG_80211N_HT*/ - break; - case ACT_PUBLIC_VENDOR: - ret = on_action_public_vendor(precv_frame); - break; - default: - ret = on_action_public_default(precv_frame, action); - break; - } + ie_status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); -exit: - return ret; -} + val = cpu_to_le16(pstat->phl_sta->aid | BIT(14) | BIT(15)); + pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); -unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) -{ -#ifdef CONFIG_RTW_80211R - u32 ret = _FAIL; - u32 frame_len = 0; - u8 action_code = 0; - u8 category = 0; - u8 *pframe = NULL; - u8 *pframe_body = NULL; - u8 tgt_addr[ETH_ALEN]; - u8 *pie = NULL; - u32 ft_ie_len = 0; - u32 status_code = 0; - struct mlme_ext_priv *pmlmeext = NULL; - struct mlme_ext_info *pmlmeinfo = NULL; - struct mlme_priv *pmlmepriv = NULL; - struct wlan_network *proam_target = NULL; - struct ft_roam_info *pft_roam = NULL; - _irqL irqL; + if (pstat->bssratelen <= 8) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); + else { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen)); + } - pmlmeext = &(padapter->mlmeextpriv); - pmlmeinfo = &(pmlmeext->mlmext_info); - pmlmepriv = &(padapter->mlmepriv); - pft_roam = &(pmlmepriv->ft_roam); - pframe = precv_frame->u.hdr.rx_data; - frame_len = precv_frame->u.hdr.len; - pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - category = pframe_body[0]; +#ifdef CONFIG_IEEE80211W + if (status == _STATS_REFUSED_TEMPORARILY_) { + u8 timeout_itvl[5]; + u32 timeout_interval = 3000; + /* Association Comeback time */ + timeout_itvl[0] = 0x03; + timeout_interval = cpu_to_le32(timeout_interval); + _rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4); + pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); + } +#endif /* CONFIG_IEEE80211W */ - if (category != RTW_WLAN_CATEGORY_FT) - goto exit; +#ifdef CONFIG_80211N_HT + if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) { + uint ie_len = 0; - action_code = pframe_body[1]; - switch (action_code) { - case RTW_WLAN_ACTION_FT_RSP: - RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n"); - if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) { - RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2])); - goto exit; + /* FILL HT CAP INFO IE */ + /* p = hostapd_eid_ht_capabilities_info(hapd, p); */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); } - status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + 14)); - if (status_code != 0) { - RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code); - goto exit; + /* FILL HT ADD INFO IE */ + /* p = hostapd_eid_ht_operation(hapd, p); */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); } - _rtw_memcpy(tgt_addr, &pframe_body[8], ETH_ALEN); - if (is_zero_mac_addr(tgt_addr) || is_broadcast_mac_addr(tgt_addr)) { - RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(tgt_addr)); - goto exit; - } + } +#endif - pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len); - if (pie) { - if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) { - RTW_ERR("FT: Invalid MDID\n"); - goto exit; - } - } + /*adding EXT_CAPAB_IE */ + if (pmlmepriv->ext_capab_ie_len > 0) { + uint ie_len = 0; - rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA); - _cancel_timer_ex(&pmlmeext->ft_link_timer); + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_EXT_CAP, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + } - /*Disconnect current AP*/ - receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE); +#ifdef CONFIG_RTW_80211K + /* Adding RM capability IE */ + if (padapter->rmpriv.enable == _TRUE) { + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EID_RRM_EN_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + } +#endif /* CONFIG_RTW_80211K */ - pft_roam->ft_action_len = frame_len; - _rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ)); - ret = _SUCCESS; - break; - case RTW_WLAN_ACTION_FT_REQ: - case RTW_WLAN_ACTION_FT_CONF: - case RTW_WLAN_ACTION_FT_ACK: - default: - RTW_ERR("FT: Unsupported FT Action!\n"); - break; +#ifdef CONFIG_RTW_MBO + if (pmlmepriv->mbopriv.enable == _TRUE) { + ie_len = 0; + for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) { + pbuf = rtw_get_ie(pbuf, _SSN_IE_1_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if ((pbuf) && (_rtw_memcmp(pbuf + 2, WIFI_ALLIANCE_OUI, 3)) && (*(pbuf+5) == MBO_OUI_TYPE)) { + /* find MBO-OCE information element */ + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + break; + } + if ((pbuf == NULL) || (ie_len == 0)) + break; + } } +#endif /* CONFIG_RTW_MBO */ -exit: - return ret; -#else - return _SUCCESS; -#endif -} +#ifdef CONFIG_80211AC_VHT + if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option) + && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP) + && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) { + u32 ie_len = 0; -unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) -{ - u8 *pframe = precv_frame->u.hdr.rx_data; - u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - u8 category, action; - - /* check RA matches or not */ - if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) - goto exit; - - category = frame_body[0]; - if (category != RTW_WLAN_CATEGORY_HT) - goto exit; + /* FILL VHT CAP IE */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } - action = frame_body[1]; - switch (action) { - case RTW_WLAN_ACTION_HT_SM_PS: -#ifdef CONFIG_80211N_HT -#ifdef CONFIG_AP_MODE - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]); -#endif /*CONFIG_AP_MODE*/ -#endif /*CONFIG_80211N_HT*/ - break; - case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING: -#ifdef CONFIG_BEAMFORMING - /*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/ - rtw_beamforming_get_report_frame(padapter, precv_frame); -#endif /*CONFIG_BEAMFORMING*/ - break; - default: - break; + /* FILL VHT OPERATION IE */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } } +#endif /* CONFIG_80211AC_VHT */ -exit: - - return _SUCCESS; -} - -#ifdef CONFIG_IEEE80211W -unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame) -{ - u8 *pframe = precv_frame->u.hdr.rx_data; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u16 tid; - /* Baron */ - - RTW_INFO("OnAction_sa_query\n"); - - switch (pframe[WLAN_HDR_A3_LEN + 1]) { - case 0: /* SA Query req */ - _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16)); - RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n" - , pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]); - issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY); - break; +#ifdef CONFIG_80211AX_HE + if ((pstat->flags & WLAN_STA_HE) && (pmlmepriv->hepriv.he_option)) { + u32 ie_len = 0; + u8 he_cap_eid_ext = WLAN_EID_EXTENSION_HE_CAPABILITY; + u8 he_op_eid_ext = WLAN_EID_EXTENSION_HE_OPERATION; - case 1: /* SA Query rsp */ - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); - if (psta != NULL) - _cancel_timer_ex(&psta->dot11w_expire_timer); + /* FILL HE CAP IE */ + pbuf = rtw_get_ie_ex(ie + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_, + WLAN_EID_EXTENSION, &he_cap_eid_ext, 1, NULL, &ie_len); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len); + pframe += ie_len; + pattrib->pktlen += ie_len; + } - _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16)); - RTW_INFO("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN + 1], tid); - break; - default: - break; - } - if (0) { - int pp; - printk("pattrib->pktlen = %d =>", pattrib->pkt_len); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", pframe[pp]); - printk("\n"); + /* FILL HE OPERATION IE */ + pbuf = rtw_get_ie_ex(ie + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_, + WLAN_EID_EXTENSION, &he_op_eid_ext, 1, NULL, &ie_len); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len); + pframe += ie_len; + pattrib->pktlen += ie_len; + } } +#endif /* CONFIG_80211AX_HE */ - return _SUCCESS; -} -#endif /* CONFIG_IEEE80211W */ -unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame) -{ -#ifdef CONFIG_RTW_80211K - return rm_on_action(padapter, precv_frame); -#else - return _SUCCESS; -#endif /* CONFIG_RTW_80211K */ -} +#ifdef CONFIG_RTW_80211R_AP + rtw_ft_build_assoc_rsp_ies(padapter, pstat, pattrib, &pframe); +#endif +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_assoc_rsp_ies(padapter, &pframe, pattrib); +#endif -unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) -{ - return _SUCCESS; -} + /* FILL WMM IE */ + if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) { + uint ie_len = 0; + unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; -unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) -{ -#ifdef CONFIG_80211AC_VHT - u8 *pframe = precv_frame->u.hdr.rx_data; - struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; - u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - u8 category, action; - struct sta_info *psta = NULL; + for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) { + pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); - /* check RA matches or not */ - if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) - goto exit; + break; + } - category = frame_body[0]; - if (category != RTW_WLAN_CATEGORY_VHT) - goto exit; + if ((pbuf == NULL) || (ie_len == 0)) + break; + } - action = frame_body[1]; - switch (action) { - case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING: -#ifdef CONFIG_BEAMFORMING - /*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/ - rtw_beamforming_get_report_frame(padapter, precv_frame); -#endif /*CONFIG_BEAMFORMING*/ - break; - case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION: - /* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */ - /* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */ - psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); - if (psta) - rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta); - break; - case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT: -#ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 - rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame); -#endif /* RTW_BEAMFORMING_VERSION_2 */ -#endif /* CONFIG_BEAMFORMING */ - break; - default: - break; } -exit: -#endif /* CONFIG_80211AC_VHT */ - - return _SUCCESS; -} -unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) -{ -#ifdef CONFIG_P2P - u8 *frame_body; - u8 category, OUI_Subtype, dialogToken = 0; - u8 *pframe = precv_frame->u.hdr.rx_data; - uint len = precv_frame->u.hdr.len; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); - /* check RA matches or not */ - if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) - return _SUCCESS; + /* add WPS IE ie for wps 2.0 */ + if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) { + _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); - frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + pframe += pmlmepriv->wps_assoc_resp_ie_len; + pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; + } - category = frame_body[0]; - if (category != RTW_WLAN_CATEGORY_P2P) - return _SUCCESS; +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) { + u32 len = 0; - if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI) - return _SUCCESS; + if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) { + len = pmlmepriv->p2p_assoc_resp_ie_len; + _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len); + } else if (pmlmepriv->assoc_rsp && pmlmepriv->assoc_rsp_len > 0) { + len = pmlmepriv->assoc_rsp_len; + _rtw_memcpy(pframe, pmlmepriv->assoc_rsp, len); + } -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled - && pwdinfo->driver_interface == DRIVER_CFG80211 - ) { - rtw_cfg80211_rx_action_p2p(padapter, precv_frame); - return _SUCCESS; - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len -= sizeof(struct rtw_ieee80211_hdr_3addr); - OUI_Subtype = frame_body[5]; - dialogToken = frame_body[6]; + pframe += len; + pattrib->pktlen += len; + } - switch (OUI_Subtype) { - case P2P_NOTICE_OF_ABSENCE: +#ifdef CONFIG_WFD + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } +#endif - break; +#endif /* CONFIG_P2P */ - case P2P_PRESENCE_REQUEST: +#ifdef CONFIG_RTW_MULTI_AP + if (padapter->multi_ap && (pstat->flags & WLAN_STA_MULTI_AP)) + pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap); +#endif - process_p2p_presence_req(pwdinfo, pframe, len); +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT); +#endif - break; +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (padapter->tbtx_capability == _TRUE) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen); +#endif - case P2P_PRESENCE_RESPONSE: + pattrib->last_txcmdsz = pattrib->pktlen; - break; + dump_mgntframe(padapter, pmgntframe); - case P2P_GO_DISC_REQUEST: +#endif +} - break; +static u32 rtw_append_assoc_req_owe_ie(_adapter *adapter, u8 *pbuf) +{ + struct security_priv *sec = &adapter->securitypriv; + u32 len = 0; - default: - break; + if (sec == NULL) + goto exit; - } + if (sec->owe_ie_len > 0) { + len = sec->owe_ie_len; + _rtw_memcpy(pbuf, sec->owe_ie, len); } -#endif /* CONFIG_P2P */ - - return _SUCCESS; +exit: + return len; } -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT -unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame) +void _issue_assocreq(_adapter *padapter, u8 is_reassoc) { -#define TOKEN_REQ 0x00 -#define TOKEN_REL 0x01 - - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; - u32 xmit_time; - u8 *src=NULL, *pframe = precv_frame->u.hdr.rx_data; - u8 tbtx_action_code; - u8 i, nr_send; - uint tx_duration = 0; - - if (padapter->tbtx_capability == _FALSE) - goto exit; - - tbtx_action_code = *(pframe + WLAN_HDR_A3_LEN + 1); - - - switch (tbtx_action_code) - { - case TOKEN_REQ: - // parse duration - tx_duration = le32_to_cpu(*(uint *)(pframe + WLAN_HDR_A3_LEN + 2)); - padapter->tbtx_duration = tx_duration/1000; // Mirocsecond to Millisecond - ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE); - rtw_tx_control_cmd(padapter); - _set_timer(&pmlmeext->tbtx_xmit_timer, padapter->tbtx_duration); - ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE); -#if defined(CONFIG_SDIO_HCI) && !defined(CONFIG_SDIO_TX_TASKLET) - _rtw_up_sema(&pxmitpriv->SdioXmitSema); -#else - tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); -#endif - break; -#ifdef CONFIG_AP_MODE - case TOKEN_REL: - src = get_addr2_ptr(pframe); - if (!src) - goto exit; - psta = rtw_get_stainfo(&padapter->stapriv, src); - if (!psta) - goto exit; - - if (ATOMIC_READ(&pstapriv->nr_token_keeper) < 1) - goto exit; - - for (i=0; i< NR_MAXSTA_INSLOT; i++) { - if (pstapriv->token_holder[i] == psta) { - pstapriv->token_holder[i] = NULL; - //RTW_INFO("macaddr1:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - ATOMIC_DEC(&pstapriv->nr_token_keeper); - break; - } - } - - if (ATOMIC_READ(&pstapriv->nr_token_keeper) == 0) - _set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1); - - break; -#endif - default: - RTW_INFO("Undefined Action Code\n"); - goto exit; - break; - } - -exit: - return _SUCCESS; -} - -void rtw_issue_action_token_rel(_adapter *padapter) -{ - - // Todo: - // gen token - /* Token Release Format - Category code : 1 Byte - Action code : 1 Byte */ int ret = _FAIL; - //u16 *fctrl; - u8 val = 0x01; - u8 category = RTW_WLAN_CATEGORY_TBTX; - u8 *pframe; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned short val16; + unsigned int i, j, index = 0; + unsigned char bssrate[NumRates], sta_bssrate[NumRates]; + PNDIS_802_11_VARIABLE_IEs pIE; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - //struct sta_info *psta; - //struct sta_priv *pstapriv = &padapter->stapriv; - //struct registry_priv *pregpriv = &padapter->registrypriv; - + int bssrate_len = 0, sta_bssrate_len = 0; + u8 vs_ie_length = 0; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 p2pie[255] = { 0x00 }; + u16 p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#endif /* CONFIG_P2P */ + +#if CONFIG_DFS + u16 cap; +#endif + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; + goto exit; pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) - return; - - /*update attribute */ + goto exit; + + /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - pattrib->rate = MGN_24M; /* issue action release using OFDM rate? 20190716 Bruce add */ + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - //fctrl = &(pwlanhdr->frame_ctl); - //*(fctrl) = 0; - + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - // SetSeqNum?? SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + if (is_reassoc == _TRUE) + set_frame_sub_type(pframe, WIFI_REASSOCREQ); + else + set_frame_sub_type(pframe, WIFI_ASSOCREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen)); - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - - //RTW_INFO("%s\n", __func__); + /* caps */ -} +#if CONFIG_DFS + _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); + cap |= cap_SpecMgmt; + _rtw_memcpy(pframe, &cap, 2); +#else + _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); #endif -unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) -{ - int i; - unsigned char category; - struct action_handler *ptable; - unsigned char *frame_body; - u8 *pframe = precv_frame->u.hdr.rx_data; + pframe += 2; + pattrib->pktlen += 2; - frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + /* listen interval */ + /* todo: listen interval for power saving */ + val16 = cpu_to_le16(3); + _rtw_memcpy(pframe , (unsigned char *)&val16, 2); + pframe += 2; + pattrib->pktlen += 2; - category = frame_body[0]; + /*Construct Current AP Field for Reassoc-Req only*/ + if (is_reassoc == _TRUE) { + _rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + pframe += ETH_ALEN; + pattrib->pktlen += ETH_ALEN; + } - for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) { - ptable = &OnAction_tbl[i]; + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); - if (category == ptable->num) - ptable->func(padapter, precv_frame); +#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS + /* Dot H */ + if (pmlmeext->chandef.chan > 14) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + u8 pow_cap_ele[2] = { 0x00 }; + u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; /* For supported channel */ - } + pow_cap_ele[0] = 13; /* Minimum transmit power capability */ + pow_cap_ele[1] = 21; /* Maximum transmit power capability */ + pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen)); - return _SUCCESS; + /* supported channels */ + while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) { + if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) { + /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ + sup_ch[0] = 1; /* First channel number */ + sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ + } else { + sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum; + sup_ch[idx_5g++] = 1; + } + sup_ch_idx++; + } + pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen)); + } +#endif /* CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS */ -} + /* supported rate & extended supported rate */ -unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) -{ +#if 1 /* Check if the AP's supported rates are also supported by STA. */ + get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); + /* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */ - /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */ - return _SUCCESS; -} + if (pmlmeext->chandef.chan == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */ + sta_bssrate_len = 4; -struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once) -{ - struct xmit_frame *pmgntframe; - struct xmit_buf *pxmitbuf; - if (once) - pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv); - else - pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv); + /* for (i = 0; i < sta_bssrate_len; i++) { */ + /* RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */ + /* } */ - if (pmgntframe == NULL) { - RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once); - goto exit; + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) + break; + RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); } - pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv); - if (pxmitbuf == NULL) { - RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter)); - rtw_free_xmitframe(pxmitpriv, pmgntframe); - pmgntframe = NULL; - goto exit; - } - pmgntframe->frame_tag = MGNT_FRAMETAG; - pmgntframe->pxmitbuf = pxmitbuf; - pmgntframe->buf_addr = pxmitbuf->pbuf; - pxmitbuf->priv_data = pmgntframe; + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) + break; -exit: - return pmgntframe; -} + /* Check if the AP's supported rates are also supported by STA. */ + for (j = 0; j < sta_bssrate_len; j++) { + /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ + if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK) + == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) { + /* RTW_INFO("match i = %d, j=%d\n", i, j); */ + break; + } else { + /* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */ + } + } -inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) -{ - return _alloc_mgtxmitframe(pxmitpriv, _FALSE); -} - -inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv) -{ - return _alloc_mgtxmitframe(pxmitpriv, _TRUE); -} - - -/**************************************************************************** - -Following are some TX fuctions for WiFi MLME - -*****************************************************************************/ - -void update_mgnt_tx_rate(_adapter *padapter, u8 rate) -{ - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + if (j == sta_bssrate_len) { + /* the rate is not supported by STA */ + RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); + } else { + /* the rate is supported by STA */ + bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; + } + } - pmlmeext->tx_rate = rate; - /* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */ -} + bssrate_len = index; + RTW_INFO("bssrate_len = %d\n", bssrate_len); +#else /* Check if the AP's supported rates are also supported by STA. */ +#if 0 + get_rate_set(padapter, bssrate, &bssrate_len); +#else + for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { + if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) + break; -void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 wireless_mode; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; + if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ + break; - psta = rtw_get_stainfo(pstapriv, pattrib->ra); + bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len]; + } +#endif +#endif /* Check if the AP's supported rates are also supported by STA. */ - pattrib->hdrlen = 24; - pattrib->nr_frags = 1; - pattrib->priority = 7; - pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; - pattrib->qsel = QSLT_MGNT; + if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) { + #if 0 /*CONFIG_CORE_XMITBUF*/ + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; /* don't connect to AP if no joint supported rate */ + } - pattrib->pktlen = 0; - if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) - wireless_mode = WIRELESS_11B; + if (bssrate_len > 8) { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } else if (bssrate_len > 0) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); else - wireless_mode = WIRELESS_11G; + RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__); - pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); -#ifdef CONFIG_80211AC_VHT - if (pHalData->rf_type == RF_1T1R) - pattrib->raid = RATEID_IDX_VHT_1SS; - else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) - pattrib->raid = RATEID_IDX_VHT_2SS; - else if (pHalData->rf_type == RF_3T3R) - pattrib->raid = RATEID_IDX_VHT_3SS; - else - pattrib->raid = RATEID_IDX_BGN_40M_1SS; +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_assoc_req_ies(padapter, &pframe, pattrib); #endif - -#ifdef CONFIG_80211AC_VHT - pattrib->rate = MGN_VHT1SS_MCS9; -#else - pattrib->rate = MGN_MCS7; +#ifdef CONFIG_RTW_80211R + rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe); #endif +#ifdef CONFIG_RTW_80211K + if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */ + | pmlmeinfo->network.PhyInfo.rm_en_cap[1] + | pmlmeinfo->network.PhyInfo.rm_en_cap[2] + | pmlmeinfo->network.PhyInfo.rm_en_cap[3] + | pmlmeinfo->network.PhyInfo.rm_en_cap[4]) + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, + (u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen)); +#endif /* CONFIG_RTW_80211K */ - pattrib->encrypt = _NO_PRIVACY_; - pattrib->bswenc = _FALSE; + /* vendor specific IE, such as WPA, WMM, WPS */ + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) || + (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || + (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { + vs_ie_length = pIE->Length; + if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { + /* Commented by Kurt 20110629 */ + /* In some older APs, WPS handshake */ + /* would be fail if we append vender extensions informations to AP */ - pattrib->qos_en = _FALSE; - pattrib->ht_en = 1; - pattrib->bwmode = CHANNEL_WIDTH_20; - pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - pattrib->sgi = _FALSE; + vs_ie_length = 14; + } - pattrib->seqnum = pmlmeext->mgnt_seq; + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen)); + } + break; - pattrib->retry_ctrl = _TRUE; + case EID_WPA2: +#ifdef CONFIG_RTW_80211R + if ((is_reassoc) && (rtw_ft_roam(padapter))) { + rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe); + } else +#endif + { +#ifdef CONFIG_IOCTL_CFG80211 + if (rtw_sec_chk_auth_alg(padapter, WLAN_AUTH_OPEN) && + rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) { + s32 entry = rtw_cached_pmkid(padapter, pmlmepriv->assoc_bssid); - pattrib->mbssid = 0; - pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; - // OpenHD added - pattrib->monitor_mode_frame = _TRUE; + rtw_rsn_sync_pmkid(padapter, (u8 *)pIE, (pIE->Length + 2), entry); + } +#endif /* CONFIG_IOCTL_CFG80211 */ -} + pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); + /* tmp: update rsn's spp related opt. */ + /*rtw_set_spp_amsdu_mode(padapter->registrypriv.amsdu_mode, pframe - (pIE->Length + 2), pIE->Length +2); */ -#ifdef CONFIG_RTW_MGMT_QUEUE -void update_mgntframe_subtype(_adapter *padapter, struct xmit_frame *pmgntframe) -{ - struct pkt_attrib *pattrib = &pmgntframe->attrib; - u8 *pframe; - u8 subtype, category ,action; + } + break; +#ifdef CONFIG_80211N_HT + case EID_HTCapability: + if (padapter->mlmepriv.htpriv.ht_option == _TRUE) { + if (!(is_ap_in_tkip(padapter))) { + _rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element)); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ - pattrib->subtype = subtype; + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); - rtw_action_frame_parse(pframe, pattrib->pktlen, &category, &action); + pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); + } + } + break; +#endif /* CONFIG_80211N_HT */ - if ((subtype == WIFI_ACTION && !(action == ACT_PUBLIC_FTM_REQ || action == ACT_PUBLIC_FTM)) || - subtype == WIFI_DISASSOC || subtype == WIFI_DEAUTH || - (subtype == WIFI_PROBERSP && MLME_IS_ADHOC(padapter))) - pattrib->ps_dontq = 0; - else - pattrib->ps_dontq = 1; -} -#endif + case WLAN_EID_EXT_CAP: + pframe = rtw_set_ie(pframe, WLAN_EID_EXT_CAP, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; -void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) -{ - u8 wireless_mode; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; +#ifdef CONFIG_80211AC_VHT + case EID_VHTCapability: + if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) + pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; -#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */ + case EID_OpModeNotification: + if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) + pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; +#endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + case WLAN_EID_EXTENSION: + if ((pIE->data[0] == WLAN_EID_EXTENSION_HE_CAPABILITY) + && (padapter->mlmepriv.hepriv.he_option == _TRUE)) + pframe = rtw_set_ie(pframe, WLAN_EID_EXTENSION, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; +#endif /* CONFIG_80211AX_HE */ + default: + break; + } - /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ + i += (pIE->Length + 2); + } +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (padapter->tbtx_capability == _TRUE) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8 , REALTEK_TBTX_IE, &(pattrib->pktlen)); +#endif - pattrib->hdrlen = 24; - pattrib->nr_frags = 1; - pattrib->priority = 7; - pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; - pattrib->qsel = QSLT_MGNT; + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); -#ifdef CONFIG_MCC_MODE - update_mcc_mgntframe_attrib(padapter, pattrib); + +#ifdef CONFIG_WAPI_SUPPORT + rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib); #endif -#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE)) -#endif /* CONFIG_CONCURRENT_MODE */ - if (MLME_IS_GC(padapter)) { - if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); +#ifdef CONFIG_P2P - psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); - if (psta) { - /* use macid sleep during NoA, mgmt frame use ac queue & ap macid */ - pattrib->mac_id = psta->cmn.mac_id; - pattrib->qsel = QSLT_VO; - } else { - if (pwdinfo->p2p_ps_state != P2P_PS_DISABLE) - RTW_ERR("%s , psta was NULL\n", __func__); - } - } +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled) { + if (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) { + _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len); + pframe += pmlmepriv->p2p_assoc_req_ie_len; + pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len; } -#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */ - - pattrib->pktlen = 0; - - if (IS_CCK_RATE(pmlmeext->tx_rate)) - wireless_mode = WIRELESS_11B; - else - wireless_mode = WIRELESS_11G; - pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); - pattrib->rate = pmlmeext->tx_rate; + } +#endif /* CONFIG_IOCTL_CFG80211 */ - pattrib->encrypt = _NO_PRIVACY_; - pattrib->bswenc = _FALSE; +#ifdef CONFIG_WFD + wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif +#endif /* CONFIG_P2P */ - pattrib->qos_en = _FALSE; - pattrib->ht_en = _FALSE; - pattrib->bwmode = CHANNEL_WIDTH_20; - pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - pattrib->sgi = _FALSE; +#ifdef CONFIG_RTW_MULTI_AP + if (padapter->multi_ap) + pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap); +#endif - pattrib->seqnum = pmlmeext->mgnt_seq; + /* OWE */ + { + u32 owe_ie_len; - pattrib->retry_ctrl = _TRUE; + owe_ie_len = rtw_append_assoc_req_owe_ie(padapter, pframe); + pframe += owe_ie_len; + pattrib->pktlen += owe_ie_len; + } - pattrib->mbssid = 0; - pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; -#ifdef CONFIG_RTW_MGMT_QUEUE - pattrib->ps_dontq = 1; +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT); #endif -} -void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe) -{ - u8 *pframe; - struct pkt_attrib *pattrib = &pmgntframe->attrib; -#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE) - struct sta_info *sta = NULL; +#ifdef CONFIG_RTW_80211R + rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe); #endif - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); - _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); -#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE) - sta = pattrib->psta; - if (!sta) { - sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - pattrib->psta = sta; - } + ret = _SUCCESS; - #ifdef CONFIG_BEAMFORMING - if (sta) - update_attrib_txbf_info(padapter, pattrib, sta); +exit: + if (ret == _SUCCESS) { + rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen); + #ifdef CONFIG_RTW_WNM + if (is_reassoc == _TRUE) + rtw_wnm_update_reassoc_req_ie(padapter); #endif -#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE) */ + } else + rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + + return; } -void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) +void issue_assocreq(_adapter *padapter) { - if (RTW_CANNOT_RUN(padapter)) { - rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); - rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); - return; - } + _issue_assocreq(padapter, _FALSE); +} - rtw_hal_mgnt_xmit(padapter, pmgntframe); +void issue_reassocreq(_adapter *padapter) +{ + _issue_assocreq(padapter, _TRUE); } -s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +/* when wait_ack is ture, this function shoule be called at process context */ +static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) { - s32 ret = _FAIL; - _irqL irqL; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf; - struct submit_ctx sctx; + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u8 a4_shift; - if (RTW_CANNOT_RUN(padapter)) { - rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); - rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); - return ret; - } + /* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */ - rtw_sctx_init(&sctx, timeout_ms); - pxmitbuf->sctx = &sctx; + if (!padapter) + goto exit; - ret = rtw_hal_mgnt_xmit(padapter, pmgntframe); + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; - if (ret == _SUCCESS -#ifdef CONFIG_RTW_MGMT_QUEUE - || ret == RTW_QUEUE_MGMT -#endif - ) - ret = rtw_sctx_wait(&sctx, __func__); + pxmitpriv = &(padapter->xmitpriv); + pmlmeext = &(padapter->mlmeextpriv); + pmlmeinfo = &(pmlmeext->mlmext_info); - _enter_critical(&pxmitpriv->lock_sctx, &irqL); - pxmitbuf->sctx = NULL; - _exit_critical(&pxmitpriv->lock_sctx, &irqL); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; - return ret; -} + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; -s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) -{ -#ifdef CONFIG_XMIT_ACK - static u8 seq_no = 0; - s32 ret = _FAIL; - struct xmit_priv *pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - if (RTW_CANNOT_RUN(padapter)) { - rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); - rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); - return -1; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (MLME_IS_AP(padapter)) + SetFrDs(fctrl); + else if (MLME_IS_STA(padapter)) + SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { + SetToDs(fctrl); + SetFrDs(fctrl); } - _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); - pxmitpriv->ack_tx = _TRUE; - pxmitpriv->seq_no = seq_no++; - pmgntframe->ack_report = 1; - rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); + if (power_mode) + SetPwrMgt(fctrl); - ret = rtw_hal_mgnt_xmit(padapter, pmgntframe); + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } - if (ret == _SUCCESS -#ifdef CONFIG_RTW_MGMT_QUEUE - || ret == RTW_QUEUE_MGMT -#endif - ) - ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_DATA_NULL); - pxmitpriv->ack_tx = _FALSE; - _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } +exit: return ret; -#else /* !CONFIG_XMIT_ACK */ - dump_mgntframe(padapter, pmgntframe); - rtw_msleep_os(50); - return _SUCCESS; -#endif /* !CONFIG_XMIT_ACK */ } -s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe) +/* + * When wait_ms > 0, this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) { - /* In this case, use 500 ms as the default wait_ack timeout */ - return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500); -} + int ret = _FAIL; + int i = 0; + systime start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; -int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) -{ - u8 *ssid_ie; - sint ssid_len_ori; - int len_diff = 0; + /* da == NULL, assum it's null data for sta to ap */ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); - ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); + do { + ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); - /* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */ + i++; - if (ssid_ie && ssid_len_ori > 0) { - switch (hidden_ssid_mode) { - case 1: { - u8 *next_ie = ssid_ie + 2 + ssid_len_ori; - u32 remain_len = 0; + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) + break; - remain_len = ies_len - (next_ie - ies); + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); - ssid_ie[1] = 0; - _rtw_memcpy(ssid_ie + 2, next_ie, remain_len); - len_diff -= ssid_len_ori; + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - break; - } - case 2: - _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); - break; - default: - break; - } + if (ret != _FAIL) { + ret = _SUCCESS; +#ifndef DBG_XMIT_ACK + goto exit; +#endif } - return len_diff; + if (try_cnt && wait_ms) { + if (da) + RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + else + RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; } -#ifdef CONFIG_AP_MODE -void issue_beacon(_adapter *padapter, int timeout_ms) +/* when wait_ack is ture, this function shoule be called at process context */ +static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack, u8 om_info) { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - unsigned int rate_len; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - _irqL irqL; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); -#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl, *qc; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ + u8 a4_shift; + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; /* RTW_INFO("%s\n", __FUNCTION__); */ -#ifdef CONFIG_BCN_ICF - pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv); - if (pmgntframe == NULL) -#else pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) -#endif - { - RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); - return; - } -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); -#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ + goto exit; /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - pattrib->qsel = QSLT_BEACON; -#if defined(CONFIG_CONCURRENT_MODE) && (!defined(CONFIG_SWTIMER_BASED_TXBCN)) - if (padapter->hw_port == HW_PORT1) - pattrib->mbssid = 1; -#endif -#ifdef CONFIG_FW_HANDLE_TXBCN - if (padapter->vap_id != CONFIG_LIMITED_AP_NUM) - pattrib->mbssid = padapter->vap_id; -#endif + pattrib->hdrlen += 2; + pattrib->qos_en = _TRUE; + pattrib->eosp = 1; + pattrib->ack_policy = 0; + pattrib->mdata = 0; _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - - SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); - /* pmlmeext->mgnt_seq++; */ - set_frame_sub_type(pframe, WIFI_BEACON); + if (MLME_IS_AP(padapter)) + SetFrDs(fctrl); + else if (MLME_IS_STA(padapter)) + SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { + SetToDs(fctrl); + SetFrDs(fctrl); + } - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + if (ps) + SetPwrMgt(fctrl); - if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { - /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ -#ifdef CONFIG_P2P - /* for P2P : Primary Device Type & Device Name */ - u32 wpsielen = 0, insert_len = 0; - u8 *wpsie = NULL; - wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen); + if (pattrib->mdata) + SetMData(fctrl); - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) { - uint wps_offset, remainder_ielen; - u8 *premainder_ie, *pframe_wscie; + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } - wps_offset = (uint)(wpsie - cur_network->IEs); + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); - premainder_ie = wpsie + wpsielen; + SetPriority(qc, tid); - remainder_ielen = cur_network->IELength - wps_offset - wpsielen; + SetEOSP(qc, pattrib->eosp); -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) { - _rtw_memcpy(pframe, cur_network->IEs, wps_offset); - pframe += wps_offset; - pattrib->pktlen += wps_offset; + SetAckpolicy(qc, pattrib->ack_policy); - _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); - pframe += pmlmepriv->wps_beacon_ie_len; - pattrib->pktlen += pmlmepriv->wps_beacon_ie_len; + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - /* copy remainder_ie to pframe */ - _rtw_memcpy(pframe, premainder_ie, remainder_ielen); - pframe += remainder_ielen; - pattrib->pktlen += remainder_ielen; - } else { - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - pframe += cur_network->IELength; - pattrib->pktlen += cur_network->IELength; - } - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - pframe_wscie = pframe + wps_offset; - _rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen); - pframe += (wps_offset + wpsielen); - pattrib->pktlen += (wps_offset + wpsielen); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; - /* now pframe is end of wsc ie, insert Primary Device Type & Device Name */ - /* Primary Device Type */ - /* Type: */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); - insert_len += 2; +#ifdef CONFIG_80211AX_HE + if (om_info) { + set_htc_order_bit(fctrl); + pattrib->rate = MGN_HE1SS_MCS0; + rtw_he_fill_htc(padapter, pattrib, (u32 *)pframe); + pframe = pframe + 4; + pattrib->pktlen = pattrib->pktlen + 4; + } +#endif - /* Length: */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008); - insert_len += 2; + pattrib->last_txcmdsz = pattrib->pktlen; - /* Value: */ - /* Category ID */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - insert_len += 2; + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } - /* OUI */ - *(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI); - insert_len += 4; +exit: + return ret; +} - /* Sub Category ID */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - insert_len += 2; +/* + * when wait_ms >0 , this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms, u8 need_om) +{ + int ret = _FAIL; + int i = 0; + systime start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; - /* Device Name */ - /* Type: */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - insert_len += 2; + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); - /* Length: */ - *(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len); - insert_len += 2; + do { + ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE, need_om); - /* Value: */ - _rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len); - insert_len += pwdinfo->device_name_len; + i++; + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) + break; - /* update wsc ie length */ - *(pframe_wscie + 1) = (wpsielen - 2) + insert_len; + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); - /* pframe move to end */ - pframe += insert_len; - pattrib->pktlen += insert_len; + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - /* copy remainder_ie to pframe */ - _rtw_memcpy(pframe, premainder_ie, remainder_ielen); - pframe += remainder_ielen; - pattrib->pktlen += remainder_ielen; - } - } else -#endif /* CONFIG_P2P */ - { - int len_diff; - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - len_diff = update_hidden_ssid( - pframe + _BEACON_IE_OFFSET_ - , cur_network->IELength - _BEACON_IE_OFFSET_ - , pmlmeinfo->hidden_ssid_mode - ); - pframe += (cur_network->IELength + len_diff); - pattrib->pktlen += (cur_network->IELength + len_diff); - } + if (ret != _FAIL) { + ret = _SUCCESS; +#ifndef DBG_XMIT_ACK + goto exit; +#endif + } - { - u8 *wps_ie; - uint wps_ielen; - u8 sr = 0; - wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, - pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen); - if (wps_ie && wps_ielen > 0) - rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); - if (sr != 0) - set_fwstate(pmlmepriv, WIFI_UNDER_WPS); - else - _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); - } + if (try_cnt && wait_ms) { + if (da) + RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + else + RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; +} +static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int ret = _FAIL; #ifdef CONFIG_P2P - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - u32 len; -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - len = pmlmepriv->p2p_beacon_ie_len; - if (pmlmepriv->p2p_beacon_ie && len > 0) - _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len); - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_beacon_p2p_ie(pwdinfo, pframe); - } - - pframe += len; - pattrib->pktlen += len; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P */ -#ifdef CONFIG_MCC_MODE - pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen); -#endif /* CONFIG_MCC_MODE*/ + /* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */ -#ifdef CONFIG_WFD - len = rtw_append_beacon_wfd_ie(padapter, pframe); - pframe += len; - pattrib->pktlen += len; -#endif - } -#endif /* CONFIG_P2P */ -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); -#endif -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_BEACON_VENDOR_IE_BIT); -#endif + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; -#ifdef CONFIG_RTL8812A - pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen ); -#endif/*CONFIG_RTL8812A*/ + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (padapter->tbtx_capability == _TRUE) - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen); -#endif + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + pattrib->key_type = key_type; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - goto _issue_bcn; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - } + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - /* below for ad-hoc mode */ + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - /* timestamp will be inserted by hardware */ - pframe += 8; - pattrib->pktlen += 8; + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_DEAUTH); - /* beacon interval: 2 bytes */ + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + reason = cpu_to_le16(reason); + pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); - pframe += 2; - pattrib->pktlen += 2; + pattrib->last_txcmdsz = pattrib->pktlen; - /* capability info: 2 bytes */ - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } - pframe += 2; - pattrib->pktlen += 2; - - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); - - /* supported rates... */ - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); - - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); +exit: + return ret; +} - /* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */ - { - u8 erpinfo = 0; - u32 ATIMWindow; - /* IBSS Parameter Set... */ - /* ATIMWindow = cur->Configuration.ATIMWindow; */ - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); +int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) +{ + RTW_INFO("%s reason(%u) to "MAC_FMT"\n", __func__, reason, MAC_ARG(da)); + return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY); +} - /* ERP IE */ - pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); - } +#ifdef CONFIG_IEEE80211W +int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type) +{ + RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); + return _issue_deauth(padapter, da, reason, _FALSE, key_type); +} +#endif /* CONFIG_IEEE80211W */ +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, + int wait_ms) +{ + int ret = _FAIL; + int i = 0; + systime start = rtw_get_current_time(); - /* EXTERNDED SUPPORTED RATE */ - if (rate_len > 8) - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + do { + ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY); - /* todo:HT for adhoc */ + i++; -_issue_bcn: + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) + break; -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - pmlmepriv->update_bcn = _FALSE; + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); - _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); -#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) { - RTW_ERR("beacon frame too large ,len(%d,%d)\n", - (pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN); - rtw_warn_on(1); - return; + if (ret != _FAIL) { + ret = _SUCCESS; +#ifndef DBG_XMIT_ACK + goto exit; +#endif } - pattrib->last_txcmdsz = pattrib->pktlen; - - /* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */ - if (timeout_ms > 0) - dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms); - else - dump_mgntframe(padapter, pmgntframe); - + if (try_cnt && wait_ms) { + if (da) + RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + else + RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; } -#endif /* CONFIG_AP_MODE */ -void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) + +static int _issue_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; - unsigned char *mac, *bssid; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - u8 *pwps_ie; - uint wps_ielen; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - unsigned int rate_len; + int ret = _FAIL; #ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ - - /* RTW_INFO("%s\n", __FUNCTION__); */ + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P */ - if (da == NULL) - return; + /* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */ if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; + goto exit; pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); - return; - } - + if (pmgntframe == NULL) + goto exit; /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - + pattrib->retry_ctrl = _FALSE; + pattrib->key_type = key_type; _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - mac = adapter_mac_addr(padapter); - bssid = cur_network->MacAddress; - fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - set_frame_sub_type(fctrl, WIFI_PROBERSP); - - pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = pattrib->hdrlen; - pframe += pattrib->hdrlen; + set_frame_sub_type(pframe, WIFI_DISASSOC); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if (cur_network->IELength > MAX_IE_SZ) - return; + reason = cpu_to_le16(reason); + pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen); + pattrib->last_txcmdsz = pattrib->pktlen; - /* inerset & update wps_probe_resp_ie */ - if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) { - uint wps_offset, remainder_ielen; - u8 *premainder_ie; - wps_offset = (uint)(pwps_ie - cur_network->IEs); + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } - premainder_ie = pwps_ie + wps_ielen; +exit: + return ret; +} - remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; +int issue_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) +{ + RTW_INFO("%s reason(%u) to "MAC_FMT"\n", __func__, reason, MAC_ARG(da)); + return _issue_disassoc(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY); +} - _rtw_memcpy(pframe, cur_network->IEs, wps_offset); - pframe += wps_offset; - pattrib->pktlen += wps_offset; +void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */ - if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2); - pframe += wps_ielen + 2; - pattrib->pktlen += wps_ielen + 2; - } + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; - if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, premainder_ie, remainder_ielen); - pframe += remainder_ielen; - pattrib->pktlen += remainder_ielen; - } - } else { - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - pframe += cur_network->IELength; - pattrib->pktlen += cur_network->IELength; - } + RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset); - /* retrieve SSID IE from cur_network->Ssid */ - { - u8 *ssid_ie; - sint ssid_ielen; - sint ssid_ielen_diff; - u8 buf[MAX_IE_SZ]; - u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; - ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, - (pframe - ies) - _FIXED_IE_LENGTH_); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); - ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - if (ssid_ie && cur_network->Ssid.SsidLength) { - uint remainder_ielen; - u8 *remainder_ie; - remainder_ie = ssid_ie + 2; - remainder_ielen = (pframe - remainder_ie); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - if (remainder_ielen > MAX_IE_SZ) { - RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter)); - remainder_ielen = MAX_IE_SZ; - } + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - _rtw_memcpy(buf, remainder_ie, remainder_ielen); - _rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen); - *(ssid_ie + 1) = cur_network->Ssid.SsidLength; - _rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */ - pframe += ssid_ielen_diff; - pattrib->pktlen += ssid_ielen_diff; - } - } -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); -#endif -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBERESP_VENDOR_IE_BIT); -#endif - } else -#endif - { + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); - /* timestamp will be inserted by hardware */ - pframe += 8; - pattrib->pktlen += 8; - - /* beacon interval: 2 bytes */ - - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pattrib->pktlen += 2; - - /* capability info: 2 bytes */ - - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pattrib->pktlen += 2; - - /* below for ad-hoc mode */ + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); + /* category, action */ + { + u8 category, action; + category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT; + action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH; - /* supported rates... */ - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + } - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); + pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0); + pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen), + hal_ch_offset_to_secondary_ch_offset(ch_offset)); - if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - u8 erpinfo = 0; - u32 ATIMWindow; - /* IBSS Parameter Set... */ - /* ATIMWindow = cur->Configuration.ATIMWindow; */ - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); + pattrib->last_txcmdsz = pattrib->pktlen; - /* ERP IE */ - pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); - } + dump_mgntframe(padapter, pmgntframe); +} - /* EXTERNDED SUPPORTED RATE */ - if (rate_len > 8) - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); +#ifdef CONFIG_IEEE80211W +void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type) +{ + u8 category = RTW_WLAN_CATEGORY_SA_QUERY; + u16 reason_code; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; - /* todo:HT for adhoc */ + RTW_INFO("%s, %04x\n", __FUNCTION__, tid); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_INFO("%s: alloc_mgtxmitframe fail\n", __FUNCTION__); + return; } -#ifdef CONFIG_P2P - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) - /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ - && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) { - u32 len; -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - /* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */ - len = pmlmepriv->p2p_go_probe_resp_ie_len; - if (pmlmepriv->p2p_go_probe_resp_ie && len > 0) - _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_probe_resp_p2p_ie(pwdinfo, pframe); - } - - pframe += len; - pattrib->pktlen += len; - -#ifdef CONFIG_MCC_MODE - pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen); -#endif /* CONFIG_MCC_MODE*/ - -#ifdef CONFIG_WFD - len = rtw_append_probe_resp_wfd_ie(padapter, pframe); - pframe += len; - pattrib->pktlen += len; -#endif - } -#endif /* CONFIG_P2P */ + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->key_type = key_type; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; -#ifdef CONFIG_AUTO_AP_MODE - { - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - RTW_INFO("(%s)\n", __FUNCTION__); + if (raddr) + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + else + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - /* check rc station */ - psta = rtw_get_stainfo(pstapriv, da); - if (psta && psta->isrc && psta->pid > 0) { - u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A}; - u8 RC_INFO[14] = {0}; - /* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */ - u16 cu_ch = (u16)cur_network->Configuration.DSConfig; + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); - RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__, - psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* append vendor specific ie */ - _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI)); - _rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN); - _rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2); - _rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2); + pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen); + pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen); - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen); + switch (action) { + case 0: /* SA Query req */ + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen); + pmlmeext->sa_query_seq++; + /* send sa query request to AP, AP should reply sa query response in 1 second */ + if (pattrib->key_type == IEEE80211W_RIGHT_KEY) { + psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1); + if (psta != NULL) { + /* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */ + _set_timer(&psta->dot11w_expire_timer, 1000); + } } - } -#endif /* CONFIG_AUTO_AP_MODE */ + break; -#ifdef CONFIG_RTL8812A - pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen); -#endif/*CONFIG_RTL8812A*/ + case 1: /* SA Query rsp */ + /* RTW_INFO("rtw_set_fixed_ie, %04x\n", tid); */ + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen); + break; + default: + break; + } pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(padapter, pmgntframe); - - return; - } +#endif /* CONFIG_IEEE80211W */ -int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack) +/** + * issue_action_ba - internal function to TX Block Ack action frame + * @padapter: the adapter to TX + * @raddr: receiver address + * @action: Block Ack Action + * @tid: tid + * @size: the announced AMPDU buffer size. used by ADDBA_RESP + * @paddba_req: used by ADDBA_RESP + * @status: status/reason code. used by ADDBA_RESP, DELBA + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @wait_ack: used xmit ack + * + * Returns: + * _SUCCESS: No xmit ack is used or acked + * _FAIL: not acked when using xmit ack + */ +static int issue_action_ba(_adapter *padapter, unsigned char *raddr, + unsigned char action, u8 tid, u8 size, + struct ADDBA_request *paddba_req, u16 status, + u8 initiator, int wait_ack) { int ret = _FAIL; + u8 category = RTW_WLAN_CATEGORY_BACK; + u16 start_seq; + u16 BA_para_set; + u16 BA_timeout_value; + u16 BA_starting_seqctrl; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; - unsigned char *pframe; + u8 *pframe; struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - unsigned char *mac; - unsigned char bssrate[NumRates]; + u16 *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - int bssrate_len = 0; - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); -#endif + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + +#ifdef CONFIG_80211N_HT if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8565,108 +8178,121 @@ int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - if ((pwdev_priv->pno_mac_addr[0] != 0xFF) - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) - mac = pwdev_priv->pno_mac_addr; - else -#endif - mac = adapter_mac_addr(padapter); - fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - if (da) { - /* unicast probe request frame */ - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); - } else { - /* broadcast probe request frame */ - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); - } - - _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + /* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */ + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - if ((pwdev_priv->pno_mac_addr[0] != 0xFF) - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) { -#ifdef CONFIG_RTW_DEBUG - RTW_DBG("%s pno_scan_seq_num: %d\n", __func__, - pwdev_priv->pno_scan_seq_num); -#endif - SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num); - pattrib->seqnum = pwdev_priv->pno_scan_seq_num; - pattrib->qos_en = 1; - pwdev_priv->pno_scan_seq_num++; - } else -#endif - { - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - } - set_frame_sub_type(pframe, WIFI_PROBEREQ); + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if (pssid && !MLME_IS_MESH(padapter)) - pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); - else - pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); - - get_rate_set(padapter, bssrate, &bssrate_len); + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - if (bssrate_len > 8) { - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); - } else - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + if (category == 3) { + switch (action) { + case RTW_WLAN_ACTION_ADDBA_REQ: + do { + pmlmeinfo->dialogToken++; + } while (pmlmeinfo->dialogToken == 0); + pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); - if (ch) - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); + BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */ -#ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - if (pssid) - pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength); - else - pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0); - } +#ifdef CONFIG_TX_AMSDU + if (padapter->tx_amsdu >= 1) /* TX AMSDU enabled */ + BA_para_set |= BIT(0); + else /* TX AMSDU disabled */ + BA_para_set &= ~BIT(0); #endif + psta = rtw_get_stainfo(pstapriv, raddr); + if (psta != NULL) { + if (psta->flags & WLAN_STA_AMSDU_DISABLE) + BA_para_set &= ~BIT(0); + } + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); - if (append_wps) { - /* add wps_ie for wps2.0 */ - if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) { - _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); - pframe += pmlmepriv->wps_probe_req_ie_len; - pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; - /* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */ - } - } -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBEREQ_VENDOR_IE_BIT); -#endif + /* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */ + BA_timeout_value = 5000;/* ~ 5ms */ + BA_timeout_value = cpu_to_le16(BA_timeout_value); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); -#ifdef CONFIG_RTL8812A - pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen ); -#endif/*CONFIG_RTL8812A*/ + /* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */ + psta = rtw_get_stainfo(pstapriv, raddr); + if (psta != NULL) { + start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1; + RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07); -#ifdef CONFIG_RTW_MBO - rtw_mbo_build_probe_req_ies( padapter, &pframe, pattrib); -#endif + psta->BA_starting_seqctrl[tid & 0x07] = start_seq; - pattrib->last_txcmdsz = pattrib->pktlen; + BA_starting_seqctrl = start_seq << 4; + BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); + } + break; + + case RTW_WLAN_ACTION_ADDBA_RESP: + pframe = rtw_set_fixed_ie(pframe, 1, &(paddba_req->dialog_token), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); + + BA_para_set = le16_to_cpu(paddba_req->BA_para_set); + + BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK; + BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK; + + BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + + if (!padapter->registrypriv.wifi_spec) { + if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */ + BA_para_set &= ~BIT(0); + else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */ + BA_para_set |= BIT(0); + } + + psta = rtw_get_stainfo(pstapriv, raddr); + if (psta != NULL) { + if (psta->flags & WLAN_STA_AMSDU_DISABLE) + BA_para_set &= ~BIT(0); + } + + BA_para_set = cpu_to_le16(BA_para_set); + + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(paddba_req->BA_timeout_value)), &(pattrib->pktlen)); + break; + + case RTW_WLAN_ACTION_DELBA: + BA_para_set = 0; + BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK; + BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK; + + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen)); + break; + default: + break; + } + } + pattrib->last_txcmdsz = pattrib->pktlen; if (wait_ack) ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); @@ -8676,35 +8302,93 @@ int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 } exit: +#endif /* CONFIG_80211N_HT */ return ret; } -inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da) +/** + * issue_addba_req - TX ADDBA_REQ + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + */ +inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid) { - _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ + , tid + , 0 /* unused */ + , NULL /* unused */ + , 0 /* unused */ + , 0 /* unused */ + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid); + } -/* - * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - * try_cnt means the maximal TX count to try +/** + * issue_addba_rsp - TX ADDBA_RESP + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + * @paddba_req: used by ADDBA_RESP */ -int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, - int try_cnt, int wait_ms) +inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, + u16 status, u8 size, + struct ADDBA_request *paddba_req) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , paddba_req + , status + , 0 /* unused */ + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size); +} + +/** + * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + * @paddba_req: used by ADDBA_RESP + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, + u16 status, u8 size, + struct ADDBA_request *paddba_req, int try_cnt, + int wait_ms) { int ret = _FAIL; int i = 0; systime start = rtw_get_current_time(); - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) goto exit; do { - ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE); + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , paddba_req + , status + , 0 /* unused */ + , _TRUE + ); i++; - if (RTW_CANNOT_RUN(padapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) break; if (i < try_cnt && wait_ms > 0 && ret == _FAIL) @@ -8715,206 +8399,132 @@ int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u if (ret != _FAIL) { ret = _SUCCESS; #ifndef DBG_XMIT_ACK - goto exit; + /* goto exit; */ #endif } if (try_cnt && wait_ms) { - if (da) - RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - else - RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size + , ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); } + exit: return ret; } -/* if psta == NULL, indiate we are station(client) now... */ -void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status) +/** + * issue_del_ba - TX DELBA + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + */ +inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator) { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - unsigned int val32; - unsigned short val16; - int use_shared_key = 0; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , NULL /* unused */ + , reason + , initiator + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator); +} - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); +/** + * issue_del_ba_ex - TX DELBA with xmit ack options + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator + , int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + systime start = rtw_get_current_time(); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) + goto exit; - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_AUTH); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - - if (psta) { /* for AP mode */ -#ifdef CONFIG_NATIVEAP_MLME - - _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); - - - /* setting auth algo number */ - val16 = (u16)psta->authalg; - - if (status != _STATS_SUCCESSFUL_) - val16 = 0; - - if (val16) { - val16 = cpu_to_le16(val16); - use_shared_key = 1; - } - - pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - - /* setting auth seq number */ - val16 = (u16)psta->auth_seq; - val16 = cpu_to_le16(val16); - pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); - - /* setting status code... */ - val16 = status; - val16 = cpu_to_le16(val16); - pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); - - /* added challenging text... */ - if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) - pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); -#endif - } else { - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter)) { - /* 2: 802.11R FTAA */ - val16 = cpu_to_le16(2); - } else -#endif - { - /* setting auth algo number */ - val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */ - if (val16) { - val16 = cpu_to_le16(val16); - use_shared_key = 1; - } - } - - /* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */ - - /* setting IV for auth seq #3 */ - if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { - /* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */ - val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30)); - val32 = cpu_to_le32(val32); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); - - pattrib->iv_len = 4; - } + do { + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , NULL /* unused */ + , reason + , initiator + , wait_ms > 0 ? _TRUE : _FALSE + ); - pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + i++; - /* setting auth seq number */ - val16 = pmlmeinfo->auth_seq; - val16 = cpu_to_le16(val16); - pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) + break; + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); - /* setting status code... */ - val16 = status; - val16 = cpu_to_le16(val16); - pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); -#ifdef CONFIG_RTW_80211R - rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe); + if (ret != _FAIL) { + ret = _SUCCESS; +#ifndef DBG_XMIT_ACK + /* goto exit; */ #endif - - /* then checking to see if sending challenging text... */ - if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { - pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); - - SetPrivacy(fctrl); - - pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pattrib->encrypt = _WEP40_; - - pattrib->icv_len = 4; - - pattrib->pktlen += pattrib->icv_len; - - } - } - pattrib->last_txcmdsz = pattrib->pktlen; - - rtw_wep_encrypt(padapter, (u8 *)pmgntframe); - RTW_INFO("%s\n", __FUNCTION__); - dump_mgntframe(padapter, pmgntframe); - - return; + if (try_cnt && wait_ms) { + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator + , ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; } - -void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) +void issue_action_BSSCoexistPacket(_adapter *padapter) { -#ifdef CONFIG_AP_MODE - struct xmit_frame *pmgntframe; + _list *plist, *phead; + unsigned char category, action; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; - struct pkt_attrib *pattrib; - unsigned char *pbuf, *pframe; - unsigned short val, ie_status; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + unsigned short *fctrl; + struct wlan_network *pnetwork = NULL; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); - u8 *ie = pnetwork->IEs, cap[5], i; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif + _queue *queue = &(pmlmepriv->scanned_queue); + u8 InfoContent[16] = {0}; + u8 ICS[8][15]; +#ifdef CONFIG_80211N_HT + if ((pmlmepriv->num_FortyMHzIntolerant == 0) && (pmlmepriv->num_sta_no_ht == 0)) + return; -#endif /* CONFIG_P2P */ + if (_TRUE == pmlmeinfo->bwmode_updated) + return; if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; RTW_INFO("%s\n", __FUNCTION__); + + category = RTW_WLAN_CATEGORY_PUBLIC; + action = ACT_PUBLIC_BSSCOEXIST; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) return; @@ -8923,7 +8533,6 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; @@ -8932,265 +8541,140 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN); - _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) - set_frame_sub_type(pwlanhdr, pkt_type); - else - return; - - pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen += pattrib->hdrlen; - pframe += pattrib->hdrlen; - - /* capability */ - val = *(unsigned short *)rtw_get_capability_from_ie(ie); -#ifdef CONFIG_RTW_80211K - val |= cap_RM; -#endif - pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); + set_frame_sub_type(pframe, WIFI_ACTION); - ie_status = cpu_to_le16(status); - pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15)); - pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - if (pstat->bssratelen <= 8) - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); - else { - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen)); - } + /* TODO calculate 40Mhz intolerant via ch and ch offset */ + /* if (pmlmepriv->num_FortyMHzIntolerant > 0) */ + { + u8 iedata = 0; -#ifdef CONFIG_IEEE80211W - if (status == _STATS_REFUSED_TEMPORARILY_) { - u8 timeout_itvl[5]; - u32 timeout_interval = 3000; - /* Association Comeback time */ - timeout_itvl[0] = 0x03; - timeout_interval = cpu_to_le32(timeout_interval); - _rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4); - pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); + iedata |= BIT(2);/* 20 MHz BSS Width Request */ + pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); } -#endif /* CONFIG_IEEE80211W */ -#ifdef CONFIG_80211N_HT - if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) { - uint ie_len = 0; + /* */ + _rtw_memset(ICS, 0, sizeof(ICS)); + if (pmlmepriv->num_sta_no_ht > 0) { + int i; - /* FILL HT CAP INFO IE */ - /* p = hostapd_eid_ht_capabilities_info(hapd, p); */ - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); - } + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); - /* FILL HT ADD INFO IE */ - /* p = hostapd_eid_ht_operation(hapd, p); */ - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); - } + phead = get_list_head(queue); + plist = get_next(phead); - } -#endif + while (1) { + int len; + u8 *p; + WLAN_BSSID_EX *pbss_network; - /*adding EXT_CAPAB_IE */ - if (pmlmepriv->ext_capab_ie_len > 0) { - uint ie_len = 0; - - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); - } - } - -#ifdef CONFIG_80211AC_VHT - if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option) - && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP) - && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) { - u32 ie_len = 0; + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; - /* FILL VHT CAP IE */ - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); - } + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - /* FILL VHT OPERATION IE */ - pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); - if (pbuf && ie_len > 0) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); - } - } -#endif /* CONFIG_80211AC_VHT */ + plist = get_next(plist); -#ifdef CONFIG_RTW_80211K - /* FILL RM Enabled Capabilities with joint capabilities */ - for (i = 0; i < 5; i++) { - cap[i] = padapter->rmpriv.rm_en_cap_def[i] - & pstat->rm_en_cap[i]; - } - if (pstat->capability & cap_RM) - pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, - (u8 *)cap, &(pattrib->pktlen)); -#endif /* CONFIG_RTW_80211K */ + pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; - /* FILL WMM IE */ - if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) { - uint ie_len = 0; - unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); + if ((p == NULL) || (len == 0)) { /* non-HT */ + if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14)) + continue; - for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) { - pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); - if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) { - _rtw_memcpy(pframe, pbuf, ie_len + 2); - pframe += (ie_len + 2); - pattrib->pktlen += (ie_len + 2); + ICS[0][pbss_network->Configuration.DSConfig] = 1; - break; + if (ICS[0][0] == 0) + ICS[0][0] = 1; } - if ((pbuf == NULL) || (ie_len == 0)) - break; } - } + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); - if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + for (i = 0; i < 8; i++) { + if (ICS[i][0] == 1) { + int j, k = 0; - /* add WPS IE ie for wps 2.0 */ - if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) { - _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + InfoContent[k] = i; + /* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */ + k++; - pframe += pmlmepriv->wps_assoc_resp_ie_len; - pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; - } + for (j = 1; j <= 14; j++) { + if (ICS[i][j] == 1) { + if (k < 16) { + InfoContent[k] = j; /* channel number */ + /* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */ + k++; + } + } + } -#ifdef CONFIG_P2P - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) { - u32 len; + pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { - len = 0; - if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) { - len = pmlmepriv->p2p_assoc_resp_ie_len; - _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len); } - } else - len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code); - pframe += len; - pattrib->pktlen += len; - } - -#ifdef CONFIG_WFD - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; - } -#endif - -#endif /* CONFIG_P2P */ - -#ifdef CONFIG_RTW_MULTI_AP - if (padapter->multi_ap && (pstat->flags & WLAN_STA_MULTI_AP)) - pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap); -#endif -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT); -#endif + } -#ifdef CONFIG_RTL8812A - pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen ); -#endif/*CONFIG_RTL8812A*/ + } -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (padapter->tbtx_capability == _TRUE) - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen); -#endif pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); - -#endif +#endif /* CONFIG_80211N_HT */ } -static u32 rtw_append_assoc_req_owe_ie(_adapter *adapter, u8 *pbuf) +/* Spatial Multiplexing Powersave (SMPS) action frame */ +int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode , u8 wait_ack) { - struct security_priv *sec = &adapter->securitypriv; - u32 len = 0; - - if (sec == NULL) - goto exit; - - if (sec->owe_ie_len > 0) { - len = sec->owe_ie_len; - _rtw_memcpy(pbuf, sec->owe_ie, len); - } - -exit: - return len; -} -void _issue_assocreq(_adapter *padapter, u8 is_reassoc) -{ int ret = _FAIL; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; + unsigned char category = RTW_WLAN_CATEGORY_HT; + u8 action = RTW_WLAN_ACTION_HT_SM_PS; + u8 sm_power_control = 0; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; + struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; - unsigned short val16; - unsigned int i, j, index = 0; - unsigned char bssrate[NumRates], sta_bssrate[NumRates]; - PNDIS_802_11_VARIABLE_IEs pIE; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - int bssrate_len = 0, sta_bssrate_len = 0; - u8 vs_ie_length = 0; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 p2pie[255] = { 0x00 }; - u16 p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif -#endif /* CONFIG_P2P */ -#if CONFIG_DFS - u16 cap; -#endif + + if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) { + sm_power_control = sm_power_control & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */ + } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) { + sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ + sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */ + } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) { + sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ + sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */ + } else + return ret; if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; + return ret; + + RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) - goto exit; + return ret; /* update attribute */ pattrib = &pmgntframe->attrib; @@ -9203,4124 +8687,1291 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - if (is_reassoc == _TRUE) - set_frame_sub_type(pframe, WIFI_REASSOCREQ); - else - set_frame_sub_type(pframe, WIFI_ASSOCREQ); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* caps */ - -#if CONFIG_DFS - _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); - cap |= cap_SpecMgmt; -#ifdef CONFIG_RTW_80211K - cap |= cap_RM; -#endif - _rtw_memcpy(pframe, &cap, 2); -#else - _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); -#endif + /* category, action */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe += 2; - pattrib->pktlen += 2; + pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen)); - /* listen interval */ - /* todo: listen interval for power saving */ - val16 = cpu_to_le16(3); - _rtw_memcpy(pframe , (unsigned char *)&val16, 2); - pframe += 2; - pattrib->pktlen += 2; + pattrib->last_txcmdsz = pattrib->pktlen; - /*Construct Current AP Field for Reassoc-Req only*/ - if (is_reassoc == _TRUE) { - _rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - pframe += ETH_ALEN; - pattrib->pktlen += ETH_ALEN; + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; } - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); + if (ret != _SUCCESS) + RTW_INFO("%s, ack to\n", __func__); -#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS - /* Dot H */ - if (pmlmeext->cur_channel > 14) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - u8 pow_cap_ele[2] = { 0x00 }; - u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; /* For supported channel */ + return ret; +} - pow_cap_ele[0] = 13; /* Minimum transmit power capability */ - pow_cap_ele[1] = 21; /* Maximum transmit power capability */ - pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen)); +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + systime start = rtw_get_current_time(); - /* supported channels */ - while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) { - if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) { - /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ - sup_ch[0] = 1; /* First channel number */ - sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ - } else { - sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum; - sup_ch[idx_5g++] = 1; - } - sup_ch_idx++; - } - pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen)); - } -#endif /* CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS */ - - /* supported rate & extended supported rate */ - -#if 1 /* Check if the AP's supported rates are also supported by STA. */ - get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); - /* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */ - - if (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */ - sta_bssrate_len = 4; + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + do { + ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE); - /* for (i = 0; i < sta_bssrate_len; i++) { */ - /* RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */ - /* } */ + i++; - for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { - if (pmlmeinfo->network.SupportedRates[i] == 0) + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) break; - RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); - } - - for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { - if (pmlmeinfo->network.SupportedRates[i] == 0) - break; + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - /* Check if the AP's supported rates are also supported by STA. */ - for (j = 0; j < sta_bssrate_len; j++) { - /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ - if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK) - == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) { - /* RTW_INFO("match i = %d, j=%d\n", i, j); */ - break; - } else { - /* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */ - } - } + if (ret != _FAIL) { + ret = _SUCCESS; +#ifndef DBG_XMIT_ACK + goto exit; +#endif + } - if (j == sta_bssrate_len) { - /* the rate is not supported by STA */ - RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); - } else { - /* the rate is supported by STA */ - bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; - } + if (try_cnt && wait_ms) { + if (raddr) + RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", %s , %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(raddr), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); + else + RTW_INFO(FUNC_ADPT_FMT", %s , %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), + ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); } +exit: - bssrate_len = index; - RTW_INFO("bssrate_len = %d\n", bssrate_len); + return ret; +} -#else /* Check if the AP's supported rates are also supported by STA. */ -#if 0 - get_rate_set(padapter, bssrate, &bssrate_len); -#else - for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { - if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) - break; +int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode) +{ + RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr)); + return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE); +} - if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ - break; +#ifdef ROKU_PRIVATE - bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len]; - } -#endif -#endif /* Check if the AP's supported rates are also supported by STA. */ +int issue_action_find_remote(_adapter *padapter) +{ + int ret = _FAIL; + u8 category = RTW_WLAN_CATEGORY_P2P; + u16 start_seq; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 ROKU_OUI[] = {0x00, 0x0d, 0x4b}; + u8 vendor_spec_subtype = 0x7f; + u8 p2p_action_subtype = 0x01; + u8 p2p_action_dialog = 0x03; + u8 reserved_1 = 0xaa; + u8 reserved_2[] = {0xab, 0x01, 0x01}; + u8 len = 0; - if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) { - rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); - rtw_free_xmitframe(pxmitpriv, pmgntframe); - goto exit; /* don't connect to AP if no joint supported rate */ - } + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; - if (bssrate_len > 8) { - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); - } else if (bssrate_len > 0) - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); - else - RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); -#ifdef CONFIG_RTW_MBO - rtw_mbo_build_assoc_req_ies(padapter, &pframe, pattrib); -#endif -#ifdef CONFIG_RTW_80211R - rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe); -#endif -#ifdef CONFIG_RTW_80211K - pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, - (u8 *)padapter->rmpriv.rm_en_cap_def, - &(pattrib->pktlen)); -#endif /* CONFIG_RTW_80211K */ + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - /* vendor specific IE, such as WPA, WMM, WPS */ - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) || - (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || - (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { - vs_ie_length = pIE->Length; - if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { - /* Commented by Kurt 20110629 */ - /* In some older APs, WPS handshake */ - /* would be fail if we append vender extensions informations to AP */ + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; - vs_ie_length = 14; - } + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen)); - } - break; + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); - case EID_WPA2: -#ifdef CONFIG_RTW_80211R - if ((is_reassoc) && (rtw_ft_roam(padapter))) { - rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe); - } else -#endif - { -#ifdef CONFIG_IOCTL_CFG80211 - if (rtw_sec_chk_auth_alg(padapter, WLAN_AUTH_OPEN) && - rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) { - s32 entry = rtw_cached_pmkid(padapter, pmlmepriv->assoc_bssid); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &category, &(pattrib->pktlen)); - rtw_rsn_sync_pmkid(padapter, (u8 *)pIE, (pIE->Length + 2), entry); - } -#endif /* CONFIG_IOCTL_CFG80211 */ + pframe = rtw_set_fixed_ie(pframe, 3, ROKU_OUI, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &vendor_spec_subtype, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &p2p_action_subtype, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &p2p_action_dialog, &(pattrib->pktlen)); - pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); - /* tmp: update rsn's spp related opt. */ - /*rtw_set_spp_amsdu_mode(padapter->registrypriv.amsdu_mode, pframe - (pIE->Length + 2), pIE->Length +2);*/ - } - break; -#ifdef CONFIG_80211N_HT - case EID_HTCapability: - if (padapter->mlmepriv.htpriv.ht_option == _TRUE) { - if (!(is_ap_in_tkip(padapter))) { - _rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element)); + /* set remote len and MAC address */ + pframe = rtw_set_fixed_ie(pframe, 1, &reserved_1, &(pattrib->pktlen)); + len = pwdinfo->num_of_remote * ETH_ALEN; + pframe = rtw_set_fixed_ie(pframe, 1, &len, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, len, pwdinfo->remote_mac_address, &(pattrib->pktlen)); - pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); + pframe = rtw_set_fixed_ie(pframe, 3, reserved_2, &(pattrib->pktlen)); - pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); - } - } - break; + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + ret = _SUCCESS; - case EID_EXTCapability: - if (padapter->mlmepriv.htpriv.ht_option == _TRUE) - pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); - break; -#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT - case EID_VHTCapability: - if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) - pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); - break; +exit: + return ret; +} +#endif - case EID_OpModeNotification: - if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) - pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen)); - break; -#endif /* CONFIG_80211AC_VHT */ - default: - break; - } +/** + * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid + * @adapter: the adapter to which @sta belongs + * @initiator: if we are the initiator of AMPDU association + * @sta: the sta to be checked + * @tid: the tid to be checked + * @force: cancel and send DELBA even when no AMPDU association is setup + * @wait_ack: send delba with xmit ack (valid when initiator == 0) + * + * Returns: + * _FAIL if sta is NULL + * when initiator is 1, always _SUCCESS + * when initiator is 0, _SUCCESS if DELBA is acked + */ +static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force, int wait_ack) +{ + int ret = _SUCCESS; - i += (pIE->Length + 2); + if (sta == NULL) { + ret = _FAIL; + goto exit; } -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (padapter->tbtx_capability == _TRUE) - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8 , REALTEK_TBTX_IE, &(pattrib->pktlen)); -#endif - if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + if (initiator == 0) { + /* recipient */ + if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) { + u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size; + sta->recvreorder_ctrl[tid].enable = _FALSE; + sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID; -#ifdef CONFIG_WAPI_SUPPORT - rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib); + if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) + ret = _FAIL; + else if (wait_ack) + ret = issue_del_ba_ex(adapter, sta->phl_sta->mac_addr, tid, 37, initiator, 3, 1); + else + issue_del_ba(adapter, sta->phl_sta->mac_addr, tid, 37, initiator); + + if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) + sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; + } + } else if (initiator == 1) { + /* originator */ +#ifdef CONFIG_80211N_HT + if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { + sta->htpriv.agg_enable_bitmap &= ~BIT(tid); + sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); + issue_del_ba(adapter, sta->phl_sta->mac_addr, tid, 37, initiator); + } #endif + } +exit: + return ret; +} -#ifdef CONFIG_P2P +inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0); +} -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - if (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) { - _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len); - pframe += pmlmepriv->p2p_assoc_req_ie_len; - pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len; - } - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { - /* Should add the P2P IE in the association request frame. */ - /* P2P OUI */ - - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20101109 */ - /* According to the P2P Specification, the association request frame should contain 3 P2P attributes */ - /* 1. P2P Capability */ - /* 2. Extended Listen Timing */ - /* 3. Device Info */ - /* Commented by Albert 20110516 */ - /* 4. P2P Interface */ - - /* P2P Capability */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); - p2pielen += 2; - - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; - - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; - else - p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; - - /* Extended Listen Timing */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; - - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); - p2pielen += 2; - - /* Value: */ - /* Availability Period */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; - - /* Availability Interval */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); - p2pielen += 2; - - /* Device Info */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; - - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); - p2pielen += ETH_ALEN; - - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ - if ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) || - (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)) - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY); - else - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC); +inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1); +} + +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u16 tid; + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + return _SUCCESS; - p2pielen += 2; + psta = rtw_get_stainfo(pstapriv, addr); + if (psta == NULL) + return _SUCCESS; - /* Primary Device Type */ - /* Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; +#if 0 + RTW_INFO("%s:%s\n", __func__, (initiator == 0) ? "RX_DIR" : "TX_DIR"); + if (initiator == 1) /* originator */ + RTW_INFO("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap); +#endif - /* OUI */ - *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); - p2pielen += 4; + for (tid = 0; tid < TID_NUM; tid++) + send_delba_sta_tid(padapter, initiator, psta, tid, 0); - /* Sub Category ID */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; + return _SUCCESS; +} - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ +unsigned int send_beacon(_adapter *padapter) +{ +#ifdef RTW_PHL_BCN - /* Device Name */ - /* Type: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); - p2pielen += 2; + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + || IS_CH_WAITING(adapter_to_rfctl(padapter)) + ) + return _SUCCESS; - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); - p2pielen += 2; + issue_beacon(padapter, 0); - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; + /* maybe need some mechanism to check bcn ready here */ - /* P2P Interface */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTERFACE; + return _SUCCESS; +#else +#if defined(CONFIG_PCI_HCI) && !defined(CONFIG_PCI_BCN_POLLING) - /* Length: */ - *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D); - p2pielen += 2; + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + || IS_CH_WAITING(adapter_to_rfctl(padapter)) + ) + return _SUCCESS; - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); /* P2P Device Address */ - p2pielen += ETH_ALEN; + /* RTW_INFO("%s\n", __FUNCTION__); */ - p2pie[p2pielen++] = 1; /* P2P Interface Address Count */ + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); /* P2P Interface Address List */ - p2pielen += ETH_ALEN; - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); - } - } + issue_beacon(padapter, 0); -#ifdef CONFIG_WFD - wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; + return _SUCCESS; #endif -#endif /* CONFIG_P2P */ -#ifdef CONFIG_RTW_MULTI_AP - if (padapter->multi_ap) - pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap); -#endif +/* CONFIG_PCI_BCN_POLLING is for pci interface beacon polling mode */ +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)|| defined(CONFIG_PCI_BCN_POLLING) + u8 bxmitok = _FALSE; + int issue = 0; + int poll = 0; + systime start = rtw_get_current_time(); - /* OWE */ - { - u32 owe_ie_len; - - owe_ie_len = rtw_append_assoc_req_owe_ie(padapter, pframe); - pframe += owe_ie_len; - pattrib->pktlen += owe_ie_len; - } + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + || IS_CH_WAITING(adapter_to_rfctl(padapter)) + ) + return _SUCCESS; -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); -#endif -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT); -#endif + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + do { + #if defined(CONFIG_PCI_BCN_POLLING) + issue_beacon(padapter, 0); + #else + issue_beacon(padapter, 100); + #endif + issue++; + do { + #if defined(CONFIG_PCI_BCN_POLLING) + rtw_msleep_os(1); + #else + rtw_yield_os(); + #endif + rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); + poll++; + } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(adapter_to_dvobj(padapter))); + #if defined(CONFIG_PCI_BCN_POLLING) + rtw_hal_unmap_beacon_icf(padapter); + #endif + } while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(adapter_to_dvobj(padapter))); -#ifdef CONFIG_RTL8812A - pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen ); -#endif/*CONFIG_RTL8812A*/ + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) + return _FAIL; - pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; + if (_FALSE == bxmitok) { + RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); + return _FAIL; + } else { + u32 passing_time = rtw_get_passing_time_ms(start); -exit: - if (ret == _SUCCESS) { - rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen); - #ifdef CONFIG_RTW_WNM - if (is_reassoc == _TRUE) - rtw_wnm_update_reassoc_req_ie(padapter); - #endif - } else - rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + if (passing_time > 100 || issue > 3) + RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); + else if (0) + RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); - return; -} + return _SUCCESS; + } -void issue_assocreq(_adapter *padapter) -{ - _issue_assocreq(padapter, _FALSE); +#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/ +#endif /* RTW_PHL_BCN */ } -void issue_reassocreq(_adapter *padapter) +/**************************************************************************** + +Following are some utitity fuctions for WiFi MLME + +*****************************************************************************/ + +BOOLEAN IsLegal5GChannel( + _adapter *adapter, + u8 channel) { - _issue_assocreq(padapter, _TRUE); + + int i = 0; + u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, + 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, + 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, + 161, 163, 165 + }; + for (i = 0; i < sizeof(Channel_5G); i++) + if (channel == Channel_5G[i]) + return _TRUE; + return _FALSE; } -/* when wait_ack is ture, this function shoule be called at process context */ -static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +/* collect bss info from Beacon and Probe request/response frames. */ +u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) { - int ret = _FAIL; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u8 a4_shift; + int i; + sint len; + u8 *p; + u8 rf_path; + u16 val16, subtype; + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 packet_len = precv_frame->u.hdr.len; + u8 ie_offset; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */ - if (!padapter) - goto exit; + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; + if (len > MAX_IE_SZ) { + /* RTW_INFO("IE too long for survey event\n"); */ + return _FAIL; + } - pxmitpriv = &(padapter->xmitpriv); - pmlmeext = &(padapter->mlmeextpriv); - pmlmeinfo = &(pmlmeext->mlmext_info); + _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; + subtype = get_frame_sub_type(pframe); - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; + if (subtype == WIFI_BEACON) { + bssid->Reserved[0] = BSS_TYPE_BCN; + ie_offset = _BEACON_IE_OFFSET_; + } else { + /* FIXME : more type */ + if (subtype == WIFI_PROBERSP) { + ie_offset = _PROBERSP_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_RSP; + } else if (subtype == WIFI_PROBEREQ) { + ie_offset = _PROBEREQ_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_REQ; + } else { + bssid->Reserved[0] = BSS_TYPE_UNDEF; + ie_offset = _FIXED_IE_LENGTH_; + } + } - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + /* below is to copy the information element */ + bssid->IELength = len; + _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + /*RTW_WKARD_CORE_RSSI_V1 - GEORGIA MUST REFINE*/ + /* bssid->PhyInfo.rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */ + bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */ + bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */ + bssid->PhyInfo.rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;/*dbm*/ - if (MLME_IS_AP(padapter)) - SetFrDs(fctrl); - else if (MLME_IS_STA(padapter)) - SetToDs(fctrl); - else if (MLME_IS_MESH(padapter)) { - SetToDs(fctrl); - SetFrDs(fctrl); - } - - if (power_mode) - SetPwrMgt(fctrl); - - if (get_tofr_ds(fctrl) == 3) { - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); - a4_shift = ETH_ALEN; - pattrib->hdrlen += ETH_ALEN; - } else { - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - a4_shift = 0; - } - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_DATA_NULL); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; - - pattrib->last_txcmdsz = pattrib->pktlen; - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } - -exit: - return ret; -} - -/* - * When wait_ms > 0, this function should be called at process context - * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - * try_cnt means the maximal TX count to try - * da == NULL for station mode - */ -int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - /* da == NULL, assum it's null data for sta to ap */ - if (da == NULL) - da = get_my_bssid(&(pmlmeinfo->network)); - - do { - ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); - - i++; - - if (RTW_CANNOT_RUN(padapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - goto exit; -#endif - } - - if (try_cnt && wait_ms) { - if (da) - RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - else - RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } -exit: - return ret; -} - -/* when wait_ack is ture, this function shoule be called at process context */ -static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack) -{ - int ret = _FAIL; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl, *qc; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 a4_shift; - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - /* RTW_INFO("%s\n", __FUNCTION__); */ - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - pattrib->hdrlen += 2; - pattrib->qos_en = _TRUE; - pattrib->eosp = 1; - pattrib->ack_policy = 0; - pattrib->mdata = 0; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - if (MLME_IS_AP(padapter)) - SetFrDs(fctrl); - else if (MLME_IS_STA(padapter)) - SetToDs(fctrl); - else if (MLME_IS_MESH(padapter)) { - SetToDs(fctrl); - SetFrDs(fctrl); - } - - if (ps) - SetPwrMgt(fctrl); - - if (pattrib->mdata) - SetMData(fctrl); - - if (get_tofr_ds(fctrl) == 3) { - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); - a4_shift = ETH_ALEN; - pattrib->hdrlen += ETH_ALEN; - } else { - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - a4_shift = 0; - } - - qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); - - SetPriority(qc, tid); - - SetEOSP(qc, pattrib->eosp); - - SetAckpolicy(qc, pattrib->ack_policy); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; - - pattrib->last_txcmdsz = pattrib->pktlen; - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } - -exit: - return ret; -} - -/* - * when wait_ms >0 , this function should be called at process context - * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - * try_cnt means the maximal TX count to try - * da == NULL for station mode - */ -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - /* da == NULL, assum it's null data for sta to ap*/ - if (da == NULL) - da = get_my_bssid(&(pmlmeinfo->network)); - - do { - ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE); - - i++; - - if (RTW_CANNOT_RUN(padapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - goto exit; -#endif - } - - if (try_cnt && wait_ms) { - if (da) - RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - else - RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } -exit: - return ret; -} - -static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type) -{ - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - int ret = _FAIL; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ - - /* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */ - -#ifdef CONFIG_P2P - if (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) { - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); - _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); - } -#endif /* CONFIG_P2P */ - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; - pattrib->key_type = key_type; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_DEAUTH); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - reason = cpu_to_le16(reason); - pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); - - pattrib->last_txcmdsz = pattrib->pktlen; - - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } - -exit: - return ret; -} - -int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) -{ - RTW_INFO("%s reason(%u) to "MAC_FMT"\n", __func__, reason, MAC_ARG(da)); - return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY); -} - -#ifdef CONFIG_IEEE80211W -int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type) -{ - RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); - return _issue_deauth(padapter, da, reason, _FALSE, key_type); -} -#endif /* CONFIG_IEEE80211W */ - -/* - * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - * try_cnt means the maximal TX count to try - */ -int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, - int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - do { - ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY); - - i++; - - if (RTW_CANNOT_RUN(padapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - goto exit; -#endif - } - - if (try_cnt && wait_ms) { - if (da) - RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - else - RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } -exit: - return ret; -} - -void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset) -{ - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; - - RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n", - FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */ - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ - _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */ - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* category, action */ - { - u8 category, action; - category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT; - action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH; - - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - } - - pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0); - pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen), - hal_ch_offset_to_secondary_ch_offset(ch_offset)); - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - -} - -#ifdef CONFIG_IEEE80211W -void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type) -{ - u8 category = RTW_WLAN_CATEGORY_SA_QUERY; - u16 reason_code; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - u8 *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; - struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; - - RTW_INFO("%s, %04x\n", __FUNCTION__, tid); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - RTW_INFO("%s: alloc_mgtxmitframe fail\n", __FUNCTION__); - return; - } - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - pattrib->key_type = key_type; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - if (raddr) - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - else - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen); - pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen); - - switch (action) { - case 0: /* SA Query req */ - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen); - pmlmeext->sa_query_seq++; - /* send sa query request to AP, AP should reply sa query response in 1 second */ - if (pattrib->key_type == IEEE80211W_RIGHT_KEY) { - psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1); - if (psta != NULL) { - /* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */ - _set_timer(&psta->dot11w_expire_timer, 1000); - } - } - break; - - case 1: /* SA Query rsp */ - tid = cpu_to_le16(tid); - /* RTW_INFO("rtw_set_fixed_ie, %04x\n", tid); */ - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen); - break; - default: - break; - } - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); -} -#endif /* CONFIG_IEEE80211W */ - -/** - * issue_action_ba - internal function to TX Block Ack action frame - * @padapter: the adapter to TX - * @raddr: receiver address - * @action: Block Ack Action - * @tid: tid - * @size: the announced AMPDU buffer size. used by ADDBA_RESP - * @status: status/reason code. used by ADDBA_RESP, DELBA - * @initiator: if we are the initiator of AMPDU association. used by DELBA - * @wait_ack: used xmit ack - * - * Returns: - * _SUCCESS: No xmit ack is used or acked - * _FAIL: not acked when using xmit ack - */ -static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action - , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack) -{ - int ret = _FAIL; - u8 category = RTW_WLAN_CATEGORY_BACK; - u16 start_seq; - u16 BA_para_set; - u16 BA_timeout_value; - u16 BA_starting_seqctrl = 0; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - u8 *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; - struct registry_priv *pregpriv = &padapter->registrypriv; - -#ifdef CONFIG_80211N_HT - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - /* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */ - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - - if (category == 3) { - switch (action) { - case RTW_WLAN_ACTION_ADDBA_REQ: - do { - pmlmeinfo->dialogToken++; - } while (pmlmeinfo->dialogToken == 0); - pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); - -#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI) - BA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */ -#else - BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */ -#endif - -#ifdef CONFIG_TX_AMSDU - if (padapter->tx_amsdu >= 1) /* TX AMSDU enabled */ - BA_para_set |= BIT(0); - else /* TX AMSDU disabled */ - BA_para_set &= ~BIT(0); -#endif - - psta = rtw_get_stainfo(pstapriv, raddr); - if (psta != NULL) { - if (psta->flags & WLAN_STA_AMSDU_DISABLE) - BA_para_set &= ~BIT(0); - } - BA_para_set = cpu_to_le16(BA_para_set); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); - - /* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */ - BA_timeout_value = 5000;/* ~ 5ms */ - BA_timeout_value = cpu_to_le16(BA_timeout_value); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); - - /* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */ - psta = rtw_get_stainfo(pstapriv, raddr); - if (psta != NULL) { - start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1; - - RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07); - - psta->BA_starting_seqctrl[tid & 0x07] = start_seq; - - BA_starting_seqctrl = start_seq << 4; - } - - BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); - break; - - case RTW_WLAN_ACTION_ADDBA_RESP: - pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen)); - status = cpu_to_le16(status); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); - - BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set); - - BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK; - BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK; - - BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; - BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; - - if (!padapter->registrypriv.wifi_spec) { - if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */ - BA_para_set &= ~BIT(0); - else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */ - BA_para_set |= BIT(0); - } - - psta = rtw_get_stainfo(pstapriv, raddr); - if (psta != NULL) { - if (psta->flags & WLAN_STA_AMSDU_DISABLE) - BA_para_set &= ~BIT(0); - } - - BA_para_set = cpu_to_le16(BA_para_set); - - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen)); - break; - - case RTW_WLAN_ACTION_DELBA: - BA_para_set = 0; - BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK; - BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK; - - BA_para_set = cpu_to_le16(BA_para_set); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); - status = cpu_to_le16(status); - pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen)); - break; - default: - break; - } - } - - pattrib->last_txcmdsz = pattrib->pktlen; - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } - -exit: -#endif /* CONFIG_80211N_HT */ - return ret; -} - -/** - * issue_addba_req - TX ADDBA_REQ - * @adapter: the adapter to TX - * @ra: receiver address - * @tid: tid - */ -inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid) -{ - issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ - , tid - , 0 /* unused */ - , 0 /* unused */ - , 0 /* unused */ - , _FALSE - ); - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid); - -} - -/** - * issue_addba_rsp - TX ADDBA_RESP - * @adapter: the adapter to TX - * @ra: receiver address - * @tid: tid - * @status: status code - * @size: the announced AMPDU buffer size - */ -inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size) -{ - issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP - , tid - , size - , status - , 0 /* unused */ - , _FALSE - ); - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size); -} - -/** - * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack - * @adapter: the adapter to TX - * @ra: receiver address - * @tid: tid - * @status: status code - * @size: the announced AMPDU buffer size - * @try_cnt: the maximal TX count to try - * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - */ -inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) - goto exit; - - do { - ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP - , tid - , size - , status - , 0 /* unused */ - , _TRUE - ); - - i++; - - if (RTW_CANNOT_RUN(adapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - /* goto exit; */ -#endif - } - - if (try_cnt && wait_ms) { - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size - , ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } - -exit: - return ret; -} - -/** - * issue_del_ba - TX DELBA - * @adapter: the adapter to TX - * @ra: receiver address - * @tid: tid - * @reason: reason code - * @initiator: if we are the initiator of AMPDU association. used by DELBA - */ -inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator) -{ - issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA - , tid - , 0 /* unused */ - , reason - , initiator - , _FALSE - ); - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator); -} - -/** - * issue_del_ba_ex - TX DELBA with xmit ack options - * @adapter: the adapter to TX - * @ra: receiver address - * @tid: tid - * @reason: reason code - * @initiator: if we are the initiator of AMPDU association. used by DELBA - * @try_cnt: the maximal TX count to try - * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - */ -int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator - , int try_cnt, int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) - goto exit; - - do { - ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA - , tid - , 0 /* unused */ - , reason - , initiator - , wait_ms > 0 ? _TRUE : _FALSE - ); - - i++; - - if (RTW_CANNOT_RUN(adapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - /* goto exit; */ -#endif - } - - if (try_cnt && wait_ms) { - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator - , ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } -exit: - return ret; -} - -void issue_action_BSSCoexistPacket(_adapter *padapter) -{ - _irqL irqL; - _list *plist, *phead; - unsigned char category, action; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct wlan_network *pnetwork = NULL; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - _queue *queue = &(pmlmepriv->scanned_queue); - u8 InfoContent[16] = {0}; - u8 ICS[8][15]; -#ifdef CONFIG_80211N_HT - if ((pmlmepriv->num_FortyMHzIntolerant == 0) && (pmlmepriv->num_sta_no_ht == 0)) - return; - - if (_TRUE == pmlmeinfo->bwmode_updated) - return; - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return; - - RTW_INFO("%s\n", __FUNCTION__); - - - category = RTW_WLAN_CATEGORY_PUBLIC; - action = ACT_PUBLIC_BSSCOEXIST; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - - /* TODO calculate 40Mhz intolerant via ch and ch offset */ - /* if (pmlmepriv->num_FortyMHzIntolerant > 0) */ - { - u8 iedata = 0; - - iedata |= BIT(2);/* 20 MHz BSS Width Request */ - pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); - } - - /* */ - _rtw_memset(ICS, 0, sizeof(ICS)); - if (pmlmepriv->num_sta_no_ht > 0) { - int i; - - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - phead = get_list_head(queue); - plist = get_next(phead); - - while (1) { - int len; - u8 *p; - WLAN_BSSID_EX *pbss_network; - - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; - - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - - plist = get_next(plist); - - pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; - - p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); - if ((p == NULL) || (len == 0)) { /* non-HT */ - if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14)) - continue; - - ICS[0][pbss_network->Configuration.DSConfig] = 1; - - if (ICS[0][0] == 0) - ICS[0][0] = 1; - } - - } - - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - - for (i = 0; i < 8; i++) { - if (ICS[i][0] == 1) { - int j, k = 0; - - InfoContent[k] = i; - /* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */ - k++; - - for (j = 1; j <= 14; j++) { - if (ICS[i][j] == 1) { - if (k < 16) { - InfoContent[k] = j; /* channel number */ - /* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */ - k++; - } - } - } - - pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); - - } - - } - - - } - - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); -#endif /* CONFIG_80211N_HT */ -} - -/* Spatial Multiplexing Powersave (SMPS) action frame */ -int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode , u8 wait_ack) -{ - - int ret = _FAIL; - unsigned char category = RTW_WLAN_CATEGORY_HT; - u8 action = RTW_WLAN_ACTION_HT_SM_PS; - u8 sm_power_control = 0; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - - if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) { - sm_power_control = sm_power_control & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */ - } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) { - sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ - sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */ - } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) { - sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ - sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */ - } else - return ret; - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - return ret; - - RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return ret; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */ - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */ - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* category, action */ - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - - pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen)); - - pattrib->last_txcmdsz = pattrib->pktlen; - - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); - else { - dump_mgntframe(padapter, pmgntframe); - ret = _SUCCESS; - } - - if (ret != _SUCCESS) - RTW_INFO("%s, ack to\n", __func__); - - return ret; -} - -/* - * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT - * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX - * try_cnt means the maximal TX count to try - */ -int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms) -{ - int ret = _FAIL; - int i = 0; - systime start = rtw_get_current_time(); - - if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) - goto exit; - - do { - ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE); - - i++; - - if (RTW_CANNOT_RUN(padapter)) - break; - - if (i < try_cnt && wait_ms > 0 && ret == _FAIL) - rtw_msleep_os(wait_ms); - - } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); - - if (ret != _FAIL) { - ret = _SUCCESS; -#ifndef DBG_XMIT_ACK - goto exit; -#endif - } - - if (try_cnt && wait_ms) { - if (raddr) - RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", %s , %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(raddr), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - else - RTW_INFO(FUNC_ADPT_FMT", %s , %d/%d in %u ms\n", - FUNC_ADPT_ARG(padapter), - ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); - } -exit: - - return ret; -} - -int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode) -{ - RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr)); - return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE); -} - -/** - * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid - * @adapter: the adapter to which @sta belongs - * @initiator: if we are the initiator of AMPDU association - * @sta: the sta to be checked - * @tid: the tid to be checked - * @force: cancel and send DELBA even when no AMPDU association is setup - * @wait_ack: send delba with xmit ack (valid when initiator == 0) - * - * Returns: - * _FAIL if sta is NULL - * when initiator is 1, always _SUCCESS - * when initiator is 0, _SUCCESS if DELBA is acked - */ -static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid - , u8 force, int wait_ack) -{ - int ret = _SUCCESS; - - if (sta == NULL) { - ret = _FAIL; - goto exit; - } - - if (initiator == 0) { - /* recipient */ - if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) { - u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size; - - sta->recvreorder_ctrl[tid].enable = _FALSE; - sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID; - - if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) - ret = _FAIL; - else if (wait_ack) - ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1); - else - issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); - - if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) - sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; - } - } else if (initiator == 1) { - /* originator */ -#ifdef CONFIG_80211N_HT - if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { - sta->htpriv.agg_enable_bitmap &= ~BIT(tid); - sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); - issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); - } -#endif - } - -exit: - return ret; -} - -inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid - , u8 force) -{ - return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0); -} - -inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid - , u8 force) -{ - return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1); -} - -unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) -{ - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u16 tid; - - if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) - if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) - return _SUCCESS; - - psta = rtw_get_stainfo(pstapriv, addr); - if (psta == NULL) - return _SUCCESS; - -#if 0 - RTW_INFO("%s:%s\n", __func__, (initiator == 0) ? "RX_DIR" : "TX_DIR"); - if (initiator == 1) /* originator */ - RTW_INFO("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap); -#endif - - for (tid = 0; tid < TID_NUM; tid++) - send_delba_sta_tid(padapter, initiator, psta, tid, 0); - - return _SUCCESS; -} - -#ifdef CONFIG_AP_MODE -unsigned int send_beacon(_adapter *padapter) -{ -#if defined(CONFIG_PCI_HCI) && !defined(CONFIG_PCI_BCN_POLLING) - #ifdef CONFIG_FW_HANDLE_TXBCN - u8 vap_id = padapter->vap_id; - - /* bypass TX BCN because vap_id is invalid*/ - if (vap_id == CONFIG_LIMITED_AP_NUM) - return _SUCCESS; - #endif - - /* bypass TX BCN queue because op ch is switching/waiting */ - if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - || IS_CH_WAITING(adapter_to_rfctl(padapter)) - ) - return _SUCCESS; - - /* RTW_INFO("%s\n", __FUNCTION__); */ - - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); - - /* 8192EE Port select for Beacon DL */ - rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); - #ifdef CONFIG_FW_HANDLE_TXBCN - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); - #endif - - issue_beacon(padapter, 0); - - #ifdef CONFIG_FW_HANDLE_TXBCN - vap_id = 0xFF; - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); - #endif - - #ifdef RTL8814AE_SW_BCN - if (GET_HAL_DATA(padapter)->bCorrectBCN != 0) - RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__); - GET_HAL_DATA(padapter)->bCorrectBCN = 1; - #endif - - return _SUCCESS; -#endif - -/* CONFIG_PCI_BCN_POLLING is for pci interface beacon polling mode */ -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)|| defined(CONFIG_PCI_BCN_POLLING) - u8 bxmitok = _FALSE; - int issue = 0; - int poll = 0; - systime start = rtw_get_current_time(); - #ifdef CONFIG_FW_HANDLE_TXBCN - u8 vap_id = padapter->vap_id; - - /* bypass TX BCN because vap_id is invalid*/ - if (vap_id == CONFIG_LIMITED_AP_NUM) - return _SUCCESS; - #endif - - /* bypass TX BCN queue because op ch is switching/waiting */ - if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - || IS_CH_WAITING(adapter_to_rfctl(padapter)) - ) - return _SUCCESS; - - #if defined(CONFIG_USB_HCI) - #if defined(CONFIG_RTL8812A) - if (IS_FULL_SPEED_USB(padapter)) { - issue_beacon(padapter, 300); - bxmitok = _TRUE; - } else - #endif - #endif - { - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); - rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); - #ifdef CONFIG_FW_HANDLE_TXBCN - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); - #endif - do { - #if defined(CONFIG_PCI_BCN_POLLING) - issue_beacon(padapter, 0); - #else - issue_beacon(padapter, 100); - #endif - issue++; - do { - #if defined(CONFIG_PCI_BCN_POLLING) - rtw_msleep_os(1); - #else - rtw_yield_os(); - #endif - rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); - poll++; - } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter)); - #if defined(CONFIG_PCI_BCN_POLLING) - rtw_hal_unmap_beacon_icf(padapter); - #endif - } while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter)); - #ifdef CONFIG_FW_HANDLE_TXBCN - vap_id = 0xFF; - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); - #endif - } - if (RTW_CANNOT_RUN(padapter)) - return _FAIL; - - - if (_FALSE == bxmitok) { - RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); - #ifdef CONFIG_BCN_RECOVERY - GET_HAL_DATA(padapter)->issue_bcn_fail++; - #endif /*CONFIG_BCN_RECOVERY*/ - return _FAIL; - } else { - u32 passing_time = rtw_get_passing_time_ms(start); - - if (passing_time > 100 || issue > 3) - RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); - else if (0) - RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); - - #ifdef CONFIG_FW_CORRECT_BCN - rtw_hal_fw_correct_bcn(padapter); - #endif - return _SUCCESS; - } - -#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/ - -} -#endif /* CONFIG_AP_MODE */ - -/**************************************************************************** - -Following are some utitity fuctions for WiFi MLME - -*****************************************************************************/ - -BOOLEAN IsLegal5GChannel( - PADAPTER Adapter, - u8 channel) -{ - - int i = 0; - u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, - 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, - 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, - 161, 163, 165 - }; - for (i = 0; i < sizeof(Channel_5G); i++) - if (channel == Channel_5G[i]) - return _TRUE; - return _FALSE; -} - -/* collect bss info from Beacon and Probe request/response frames. */ -u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) -{ - int i; - sint len; - u8 *p; - u8 rf_path; - u16 val16, subtype; - u8 *pframe = precv_frame->u.hdr.rx_data; - u32 packet_len = precv_frame->u.hdr.len; - u8 ie_offset; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); - struct registry_priv *pregistrypriv = &padapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef CONFIG_LAYER2_ROAMING - u32 *pbuf; -#endif - - len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); - - if (len > MAX_IE_SZ) { - /* RTW_INFO("IE too long for survey event\n"); */ - return _FAIL; - } - - _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); - - subtype = get_frame_sub_type(pframe); - - if (subtype == WIFI_BEACON) { - bssid->Reserved[0] = BSS_TYPE_BCN; - ie_offset = _BEACON_IE_OFFSET_; - } else { - /* FIXME : more type */ - if (subtype == WIFI_PROBERSP) { - ie_offset = _PROBERSP_IE_OFFSET_; - bssid->Reserved[0] = BSS_TYPE_PROB_RSP; - } else if (subtype == WIFI_PROBEREQ) { - ie_offset = _PROBEREQ_IE_OFFSET_; - bssid->Reserved[0] = BSS_TYPE_PROB_REQ; - } else { - bssid->Reserved[0] = BSS_TYPE_UNDEF; - ie_offset = _FIXED_IE_LENGTH_; - } - } - - bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; - - /* below is to copy the information element */ - bssid->IELength = len; - _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); - - /* get the signal strength */ - /* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */ - bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */ - bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */ - bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */ - - /* get rx_snr */ - if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) { - bssid->PhyInfo.is_cck_rate = 0; - for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) - bssid->PhyInfo.rx_snr[rf_path] = - precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path]; - } else - bssid->PhyInfo.is_cck_rate = 1; - -#ifdef CONFIG_ANTENNA_DIVERSITY - rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL); -#endif - - /* checking SSID */ - p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset); - if (p == NULL) { - RTW_INFO("marc: cannot find SSID for survey event\n"); - return _FAIL; - } - - if (*(p + 1)) { - if (len > NDIS_802_11_LENGTH_SSID) { - RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); - return _FAIL; - } - _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); - bssid->Ssid.SsidLength = *(p + 1); - } else - bssid->Ssid.SsidLength = 0; - - _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); - - /* checking rate info... */ - i = 0; - p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); - if (p != NULL) { - if (len > NDIS_802_11_LENGTH_RATES_EX) { - RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); - return _FAIL; - } -#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT - if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { - rtw_absorb_ssid_ifneed(padapter, bssid, pframe); - RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2); - return _FAIL; - } -#endif /* #ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT */ - _rtw_memcpy(bssid->SupportedRates, (p + 2), len); - i = len; - } - - p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); - if (p != NULL) { - if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) { - RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); - return _FAIL; - } -#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT - if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { - rtw_absorb_ssid_ifneed(padapter, bssid, pframe); - RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2); - return _FAIL; - } -#endif /* #ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT */ - _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); - } - -#ifdef CONFIG_P2P - if (subtype == WIFI_PROBEREQ) { - u8 *p2p_ie; - u32 p2p_ielen; - /* Set Listion Channel */ - p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen); - if (p2p_ie) { - u32 attr_contentlen = 0; - u8 listen_ch[5] = { 0x00 }; - - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen); - bssid->Configuration.DSConfig = listen_ch[4]; - } else { - /* use current channel */ - bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel; - RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig); - } - - /* FIXME */ - bssid->InfrastructureMode = Ndis802_11Infrastructure; - _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); - bssid->Privacy = 1; - return _SUCCESS; - } -#endif /* CONFIG_P2P */ - - if (bssid->IELength < 12) - return _FAIL; - - /* Checking for DSConfig */ - p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset); - - bssid->Configuration.DSConfig = 0; - bssid->Configuration.Length = 0; - - if (p) - bssid->Configuration.DSConfig = *(p + 2); - else { - /* In 5G, some ap do not have DSSET IE */ - /* checking HT info for channel */ - p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset); - if (p) { - struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); - bssid->Configuration.DSConfig = HT_info->primary_channel; - } else { - /* use current channel */ - bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); - } - } - - _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); - bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); - - val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); - - if ((val16 & 0x03) == cap_ESS) { - bssid->InfrastructureMode = Ndis802_11Infrastructure; - _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); - } else if ((val16 & 0x03) == cap_IBSS){ - bssid->InfrastructureMode = Ndis802_11IBSS; - _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); - } else if ((val16 & 0x03) == 0x00){ - u8 *mesh_id_ie, *mesh_conf_ie; - sint mesh_id_ie_len, mesh_conf_ie_len; - - mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset); - mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset); - if (mesh_id_ie || mesh_conf_ie) { - if (!mesh_id_ie) { - RTW_INFO("cannot find Mesh ID for survey event\n"); - return _FAIL; - } - if (mesh_id_ie_len) { - if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) { - RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len); - return _FAIL; - } - _rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len); - bssid->mesh_id.SsidLength = mesh_id_ie_len; - } else - bssid->mesh_id.SsidLength = 0; - - if (!mesh_conf_ie) { - RTW_INFO("cannot find Mesh config for survey event\n"); - return _FAIL; - } - if (mesh_conf_ie_len != 7) { - RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len); - return _FAIL; - } - - bssid->InfrastructureMode = Ndis802_11_mesh; - _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); - } else { - /* default cases */ - bssid->InfrastructureMode = Ndis802_11IBSS; - _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); - } - } - - if (val16 & BIT(4)) - bssid->Privacy = 1; - else - bssid->Privacy = 0; - - bssid->Configuration.ATIMWindow = 0; - - /* 20/40 BSS Coexistence check */ - if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_80211N_HT - p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset); - if (p && len > 0) { - struct HT_caps_element *pHT_caps; - pHT_caps = (struct HT_caps_element *)(p + 2); - - if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14)) - pmlmepriv->num_FortyMHzIntolerant++; - } else - pmlmepriv->num_sta_no_ht++; -#endif /* CONFIG_80211N_HT */ - - } - -#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1 - if (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { - RTW_INFO("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n" - , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig - , rtw_get_oper_ch(padapter) - , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi - ); - } -#endif - - /* mark bss info receving from nearby channel as SignalQuality 101 */ - if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) - bssid->PhyInfo.SignalQuality = 101; - -#ifdef CONFIG_RTW_80211K - p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset); - if (p) - _rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1)); - - /* save freerun counter */ - bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt; -#endif -#ifdef CONFIG_LAYER2_ROAMING - pbuf = (u32 *)((u8 *)pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - bssid->tsf = le32_to_cpu(*(pbuf + 1)); - bssid->tsf = bssid->tsf << 32; - bssid->tsf |= le32_to_cpu(*pbuf); -#endif - return _SUCCESS; -} - -#ifdef CONFIG_AP_MODE -void start_create_ibss(_adapter *padapter) -{ - unsigned short caps; - u8 val8; - u8 join_type; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); - u8 doiqk = _FALSE; - pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; - pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); - - /* update wireless mode */ - update_wireless_mode(padapter); - - /* udpate capability */ - caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); - update_capinfo(padapter, caps); - if (caps & cap_IBSS) { /* adhoc master */ - /* set_opmode_cmd(padapter, adhoc); */ /* removed */ - - val8 = 0xcf; - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); - - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); - - /* switch channel */ - set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); - - beacon_timing_control(padapter); - - /* set msr to WIFI_FW_ADHOC_STATE */ - pmlmeinfo->state = WIFI_FW_ADHOC_STATE; - Set_MSR(padapter, (pmlmeinfo->state & 0x3)); - - /* issue beacon */ - if (send_beacon(padapter) == _FAIL) { - - report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); - pmlmeinfo->state = WIFI_FW_NULL_STATE; - } else { - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); - rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); - join_type = 0; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - rtw_btcoex_connect_notify(padapter, join_type); - - report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); - pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; - rtw_indicate_connect(padapter); - } - } else { - RTW_INFO("start_create_ibss, invalid cap:%x\n", caps); - return; - } - /* update bc/mc sta_info */ - update_bmc_sta(padapter); - -} -#endif /* CONFIG_AP_MODE */ - -void start_clnt_join(_adapter *padapter) -{ - unsigned short caps; - u8 val8; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); - int beacon_timeout; - u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; - - /* update wireless mode */ - update_wireless_mode(padapter); - - /* udpate capability */ - caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); - update_capinfo(padapter, caps); - - /* check if sta is ASIX peer and fix IOT issue if it is. */ - if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { - u8 iot_flag = _TRUE; - rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); - } - - if (caps & cap_ESS) { - Set_MSR(padapter, WIFI_FW_STATION_STATE); - - val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf; - -#ifdef CONFIG_WAPI_SUPPORT - if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) { - /* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */ - val8 = 0x4c; - } -#endif - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); - -#ifdef CONFIG_DEAUTH_BEFORE_CONNECT - /* Because of AP's not receiving deauth before */ - /* AP may: 1)not response auth or 2)deauth us after link is complete */ - /* issue deauth before issuing auth to deal with the situation */ - - /* Commented by Albert 2012/07/21 */ - /* For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */ - { -#ifdef CONFIG_P2P - _queue *queue = &(padapter->mlmepriv.scanned_queue); - _list *head = get_list_head(queue); - _list *pos = get_next(head); - struct wlan_network *scanned = NULL; - u8 ie_offset = 0; - _irqL irqL; - bool has_p2p_ie = _FALSE; - - _enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); - - for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) { - - scanned = LIST_CONTAINOR(pos, struct wlan_network, list); - - if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE - && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE - ) { - ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); - if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL)) - has_p2p_ie = _TRUE; - break; - } - } - - _exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); - - if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE) -#endif /* CONFIG_P2P */ - /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); - } -#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */ - - /* here wait for receiving the beacon to start auth */ - /* and enable a timer */ - beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval); - set_link_timer(pmlmeext, beacon_timeout); - _set_timer(&padapter->mlmepriv.assoc_timer, - (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); - -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter)) { - rtw_ft_start_clnt_join(padapter); - } else -#endif - { - rtw_sta_linking_test_set_start(); - pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; - } - } else if (caps & cap_IBSS) { /* adhoc client */ - Set_MSR(padapter, WIFI_FW_ADHOC_STATE); - - val8 = 0xcf; - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); - - beacon_timing_control(padapter); - - pmlmeinfo->state = WIFI_FW_ADHOC_STATE; - - report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); - } else { - /* RTW_INFO("marc: invalid cap:%x\n", caps); */ - return; - } - -} - -void start_clnt_auth(_adapter *padapter) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - _cancel_timer_ex(&pmlmeext->link_timer); - - pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); - pmlmeinfo->state |= WIFI_FW_AUTH_STATE; - - pmlmeinfo->auth_seq = 1; - pmlmeinfo->reauth_count = 0; - pmlmeinfo->reassoc_count = 0; - pmlmeinfo->link_count = 0; - pmlmeext->retry = 0; - -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter)) { - rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA); - RTW_PRINT("start ft auth\n"); - } else -#endif - RTW_PRINT("start auth\n"); - -#ifdef CONFIG_IOCTL_CFG80211 - if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) { - if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) { - RTW_INFO("SAE: PMKSA cache entry found\n"); - padapter->securitypriv.auth_alg = WLAN_AUTH_OPEN; - goto no_external_auth; - } - - RTW_PRINT("SAE: start external auth\n"); - rtw_cfg80211_external_auth_request(padapter, NULL); - return; - } -no_external_auth: -#endif /* CONFIG_IOCTL_CFG80211 */ - - issue_auth(padapter, NULL, 0); - - set_link_timer(pmlmeext, REAUTH_TO); - -} - - -void start_clnt_assoc(_adapter *padapter) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - _cancel_timer_ex(&pmlmeext->link_timer); - - pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); - pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); - -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter) - #ifdef CONFIG_RTW_WNM - || rtw_wnm_btm_reassoc_req(padapter) - #endif - ) - issue_reassocreq(padapter); - else -#endif - issue_assocreq(padapter); - - set_link_timer(pmlmeext, REASSOC_TO); -} - -unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) - return _SUCCESS; - - RTW_INFO("%s\n", __FUNCTION__); - -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_do_disconnect(padapter); -#endif - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { - if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) - pmlmeinfo->state = WIFI_FW_NULL_STATE; - } else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) { - if (report_join_res(padapter, -2, reason) != _FAIL) - pmlmeinfo->state = WIFI_FW_NULL_STATE; - } else - RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); -#ifdef CONFIG_RTW_80211R - rtw_ft_roam_status_reset(padapter); -#endif -#ifdef CONFIG_RTW_WNM - rtw_wnm_reset_btm_state(padapter); -#endif - } - - return _SUCCESS; -} - -static void rtw_hidden_ssid_bss_count(_adapter *adapter, WLAN_BSSID_EX *bss) -{ - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - RT_CHANNEL_INFO *chset = rfctl->channel_set; - int chset_idx; - - if (bss->InfrastructureMode != Ndis802_11Infrastructure) - return; - - if (!hidden_ssid_ap(bss)) - return; - - chset_idx = rtw_chset_search_ch(chset, bss->Configuration.DSConfig); - if (chset_idx < 0) - return; - - chset[chset_idx].hidden_bss_cnt++; -} - -/**************************************************************************** - -Following are the functions to report events - -*****************************************************************************/ - -void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct survey_event *psurvey_evt; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext; - struct cmd_priv *pcmdpriv; - /* u8 *pframe = precv_frame->u.hdr.rx_data; */ - /* uint len = precv_frame->u.hdr.len; */ - - if (!padapter) - return; - - pmlmeext = &padapter->mlmeextpriv; - pcmdpriv = &padapter->cmdpriv; - - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) - return; - - cmdsz = (sizeof(struct survey_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - return; - } - - _rtw_init_listhead(&pcmd_obj->list); - - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct survey_event); - evt_hdr->id = EVT_SURVEY; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - - if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - rtw_mfree((u8 *)pevtcmd, cmdsz); - return; - } - - rtw_hidden_ssid_bss_count(padapter, &psurvey_evt->bss); - - rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - - pmlmeext->sitesurvey_res.bss_cnt++; - - return; - -} - -/* -* @acs: aim to trigger channel selection -*/ -void report_surveydone_event(_adapter *padapter, bool acs) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct surveydone_event *psurveydone_evt; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) - return; - - cmdsz = (sizeof(struct surveydone_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - return; - } - - _rtw_init_listhead(&pcmd_obj->list); - - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct surveydone_event); - evt_hdr->id = EVT_SURVEY_DONE; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; - psurveydone_evt->activate_ch_cnt = pmlmeext->sitesurvey_res.activate_ch_cnt; - psurveydone_evt->acs = acs; - - RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter)); - - rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - - return; - -} - -u32 report_join_res(_adapter *padapter, int aid_res, u16 status) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct joinbss_event *pjoinbss_evt; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u32 ret = _FAIL; - - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) - goto exit; - - cmdsz = (sizeof(struct joinbss_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - goto exit; - } - - _rtw_init_listhead(&pcmd_obj->list); - - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct joinbss_event); - evt_hdr->id = EVT_JOINBSS; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); - pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = aid_res; - - RTW_INFO("report_join_res(%d, %u)\n", aid_res, status); - - - rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status); - - - ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - -exit: - return ret; -} - -void report_wmm_edca_update(_adapter *padapter) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct wmm_event *pwmm_event; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) - return; - - cmdsz = (sizeof(struct wmm_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - return; - } - - _rtw_init_listhead(&pcmd_obj->list); - - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct wmm_event); - evt_hdr->id = EVT_WMM_UPDATE; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - pwmm_event->wmm = 0; - - rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - - return; - -} - -u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct sta_info *psta; - int mac_id = -1; - struct stadel_event *pdel_sta_evt; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - /* prepare cmd parameter */ - cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - res = _FAIL; - goto exit; - } - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct stadel_event); - evt_hdr->id = EVT_DEL_STA; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); - _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); - psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); - if (psta) - mac_id = (int)psta->cmn.mac_id; - else - mac_id = (-1); - pdel_sta_evt->mac_id = mac_id; - pdel_sta_evt->locally_generated = locally_generated; - - if (!enqueue) { - /* do directly */ - rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt); - rtw_mfree(pevtcmd, cmdsz); - } else { - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) { - rtw_mfree(pevtcmd, cmdsz); - res = _FAIL; - goto exit; - } - - _rtw_init_listhead(&pcmd_obj->list); - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - } - -exit: - - RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res); - - return res; -} - -void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr) -{ - struct cmd_obj *pcmd_obj; - u8 *pevtcmd; - u32 cmdsz; - struct stassoc_event *padd_sta_evt; - struct rtw_evt_header *evt_hdr; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - - pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmd_obj == NULL) - return; - - cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header)); - pevtcmd = (u8 *)rtw_zmalloc(cmdsz); - if (pevtcmd == NULL) { - rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); - return; - } - - _rtw_init_listhead(&pcmd_obj->list); - - pcmd_obj->cmdcode = CMD_SET_MLME_EVT; - pcmd_obj->cmdsz = cmdsz; - pcmd_obj->parmbuf = pevtcmd; - - pcmd_obj->rsp = NULL; - pcmd_obj->rspsz = 0; - - evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct stassoc_event); - evt_hdr->id = EVT_ADD_STA; - evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - - padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); - - RTW_INFO("report_add_sta_event: add STA\n"); - - rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - - return; -} - - -bool rtw_port_switch_chk(_adapter *adapter) -{ - bool switch_needed = _FALSE; -#ifdef CONFIG_CONCURRENT_MODE -#ifdef CONFIG_RUNTIME_PORT_SWITCH - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj); - _adapter *if_port0 = NULL; - _adapter *if_port1 = NULL; - struct mlme_ext_info *if_port0_mlmeinfo = NULL; - struct mlme_ext_info *if_port1_mlmeinfo = NULL; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) { - if_port0 = dvobj->padapters[i]; - if_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info); - } else if (get_hw_port(dvobj->padapters[i]) == HW_PORT1) { - if_port1 = dvobj->padapters[i]; - if_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info); - } - } - - if (if_port0 == NULL) { - rtw_warn_on(1); - goto exit; - } - - if (if_port1 == NULL) { - rtw_warn_on(1); - goto exit; - } - -#ifdef DBG_RUNTIME_PORT_SWITCH - RTW_INFO(FUNC_ADPT_FMT" wowlan_mode:%u\n" - ADPT_FMT", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n" - ADPT_FMT", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n", - FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode, - ADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE), - ADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)); -#endif /* DBG_RUNTIME_PORT_SWITCH */ - -#ifdef CONFIG_WOWLAN - /* WOWLAN interface(primary, for now) should be port0 */ - if (pwrctl->wowlan_mode == _TRUE) { - if (!is_primary_adapter(if_port0)) { - RTW_INFO("%s "ADPT_FMT" enable WOWLAN\n", __func__, ADPT_ARG(if_port1)); - switch_needed = _TRUE; - } - goto exit; - } -#endif /* CONFIG_WOWLAN */ - - /* AP/Mesh should use port0 for ctl frame's ack */ - if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1)); - switch_needed = _TRUE; - goto exit; - } - - /* GC should use port0 for p2p ps */ - if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) - && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) -#ifdef CONFIG_P2P - && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE) -#endif - && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS) - ) { - RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1)); - switch_needed = _TRUE; - goto exit; - } - - /* port1 linked, but port0 not linked */ - if ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) - ) { - RTW_INFO("%s "ADPT_FMT" is SINGLE_LINK\n", __func__, ADPT_ARG(if_port1)); - switch_needed = _TRUE; - goto exit; - } - -exit: -#ifdef DBG_RUNTIME_PORT_SWITCH - RTW_INFO(FUNC_ADPT_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), switch_needed); -#endif /* DBG_RUNTIME_PORT_SWITCH */ -#endif /* CONFIG_RUNTIME_PORT_SWITCH */ -#endif /* CONFIG_CONCURRENT_MODE */ - return switch_needed; -} - -/**************************************************************************** - -Following are the event callback functions - -*****************************************************************************/ - -/* for sta/adhoc mode */ -void update_sta_info(_adapter *padapter, struct sta_info *psta) -{ - _irqL irqL; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - /* ERP */ - VCS_update(padapter, psta); - -#ifdef CONFIG_80211N_HT - /* HT */ - if (pmlmepriv->htpriv.ht_option) { - psta->htpriv.ht_option = _TRUE; - - psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; - - psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2; - - if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20)) - psta->htpriv.sgi_20m = _TRUE; - - if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40)) - psta->htpriv.sgi_40m = _TRUE; - - psta->qos_option = _TRUE; - - psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap; - psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap; - psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; - - _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); - #ifdef CONFIG_BEAMFORMING - psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; - psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap; - #endif + if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) { + bssid->PhyInfo.is_cck_rate = 0; + for (rf_path = 0; rf_path < GET_HAL_RFPATH_NUM(dvobj); rf_path++) + bssid->PhyInfo.rx_snr[rf_path] = + precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path]; } else -#endif /* CONFIG_80211N_HT */ - { -#ifdef CONFIG_80211N_HT - psta->htpriv.ht_option = _FALSE; - psta->htpriv.ampdu_enable = _FALSE; - psta->htpriv.tx_amsdu_enable = _FALSE; - psta->htpriv.sgi_20m = _FALSE; - psta->htpriv.sgi_40m = _FALSE; -#endif /* CONFIG_80211N_HT */ - psta->qos_option = _FALSE; - - } - -#ifdef CONFIG_80211N_HT - psta->htpriv.ch_offset = pmlmeext->cur_ch_offset; - - psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ - psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ -#endif /* CONFIG_80211N_HT */ - - psta->cmn.bw_mode = pmlmeext->cur_bwmode; + bssid->PhyInfo.is_cck_rate = 1; - /* QoS */ - if (pmlmepriv->qospriv.qos_option) - psta->qos_option = _TRUE; -#ifdef CONFIG_80211AC_VHT - _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); - if (psta->vhtpriv.vht_option) { - psta->cmn.ra_info.is_vht_enable = _TRUE; - #ifdef CONFIG_BEAMFORMING - psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap; - psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap; - #endif /*CONFIG_BEAMFORMING*/ + /* checking SSID */ + p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset); + if (p == NULL) { + RTW_INFO("marc: cannot find SSID for survey event\n"); + return _FAIL; } -#endif /* CONFIG_80211AC_VHT */ - psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); - update_ldpc_stbc_cap(psta); - - _enter_critical_bh(&psta->lock, &irqL); - psta->state = WIFI_ASOC_STATE; - _exit_critical_bh(&psta->lock, &irqL); -} - -static void rtw_mlmeext_disconnect(_adapter *padapter) -{ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 self_action = MLME_ACTION_UNKNOWN; - u8 state_backup = (pmlmeinfo->state & 0x03); - u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; + if (*(p + 1)) { + if (len > NDIS_802_11_LENGTH_SSID) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); + bssid->Ssid.SsidLength = *(p + 1); + } else + bssid->Ssid.SsidLength = 0; - if (MLME_IS_AP(padapter)) - self_action = MLME_AP_STOPPED; - else if (MLME_IS_MESH(padapter)) - self_action = MLME_MESH_STOPPED; - else if (MLME_IS_STA(padapter)) - self_action = MLME_STA_DISCONNECTED; - else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)) - self_action = MLME_ADHOC_STOPPED; - else { - RTW_INFO("state:0x%x\n", MLME_STATE(padapter)); - rtw_warn_on(1); - } + _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); - /* set_opmode_cmd(padapter, infra_client_with_mlme); */ -#ifdef CONFIG_HW_P0_TSF_SYNC - if (self_action == MLME_STA_DISCONNECTED) - correct_TSF(padapter, self_action); + /* checking rate info... */ + i = 0; + p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) { + if (len > NDIS_802_11_LENGTH_RATES_EX) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } +#ifndef RTW_PHL_TEST_FPGA + if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { + rtw_absorb_ssid_ifneed(padapter, bssid, pframe); + RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2); + return _FAIL; + } #endif - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); - if (self_action == MLME_STA_DISCONNECTED) - rtw_hal_rcr_set_chk_bssid(padapter, self_action); - - /* set MSR to no link state->infra. mode */ - Set_MSR(padapter, _HW_STATE_STATION_); - - /* check if sta is ASIX peer and fix IOT issue if it is. */ - if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { - u8 iot_flag = _FALSE; - rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + _rtw_memcpy(bssid->SupportedRates, (p + 2), len); + i = len; } - pmlmeinfo->state = WIFI_FW_NULL_STATE; -#ifdef CONFIG_MCC_MODE - /* mcc disconnect setting before download LPS rsvd page */ - rtw_hal_set_mcc_setting_disconnect(padapter); -#endif /* CONFIG_MCC_MODE */ - - if (state_backup == WIFI_FW_STATION_STATE) { - if (rtw_port_switch_chk(padapter) == _TRUE) { - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); -#ifdef CONFIG_LPS - { - _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); - if (port0_iface) - rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY); - } -#endif + p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) { + if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } +#ifndef RTW_PHL_TEST_FPGA + if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { + rtw_absorb_ssid_ifneed(padapter, bssid, pframe); + RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2); + return _FAIL; } +#endif + _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); } - /* switch to the 20M Hz mode after disconnect */ - pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; -#ifdef CONFIG_CTRL_TXSS_BY_TP - pmlmeext->txss_1ss = _FALSE; -#endif +#ifdef CONFIG_P2P + if (subtype == WIFI_PROBEREQ) { + u8 *p2p_ie; + u32 p2p_ielen; + /* Set Listion Channel */ + p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen); + if (p2p_ie) { + u32 attr_contentlen = 0; + u8 listen_ch[5] = { 0x00 }; -#ifdef CONFIG_FCS_MODE - if (EN_FCS(padapter)) - rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL); -#endif + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen); + bssid->Configuration.DSConfig = listen_ch[4]; + } else { + /* use current channel */ + bssid->Configuration.DSConfig = padapter->mlmeextpriv.chandef.chan; + RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig); + } - if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) { - /* DFS and channel status no need to check here for STA under OPCH_SW */ - u8 ch, bw, offset; + /* FIXME */ + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); + bssid->Privacy = 1; + return _SUCCESS; + } +#endif /* CONFIG_P2P */ - #ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(padapter, self_action, 0); - #endif + if (bssid->IELength < 12) + return _FAIL; - if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) - set_channel_bwmode(padapter, ch, offset, bw); - rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); - rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), BIT(padapter->iface_id), 0); - } + /* Checking for DSConfig */ + p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset); - flush_all_cam_entry(padapter); + bssid->Configuration.DSConfig = 0; + bssid->Configuration.Length = 0; - _cancel_timer_ex(&pmlmeext->link_timer); + if (p) + bssid->Configuration.DSConfig = *(p + 2); + else { + /* In 5G, some ap do not have DSSET IE */ + /* checking HT info for channel */ + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset); + if (p) { + struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); + bssid->Configuration.DSConfig = HT_info->primary_channel; + } else { + /* use current channel */ + bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); + } + } - /* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */ - pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; - pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); + bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); -#ifdef CONFIG_TDLS - padapter->tdlsinfo.ap_prohibited = _FALSE; + val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); - /* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */ - if (padapter->registrypriv.wifi_spec == 1) - padapter->tdlsinfo.ch_switch_prohibited = _FALSE; -#endif /* CONFIG_TDLS */ + if ((val16 & 0x03) == cap_ESS) { + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); + } else if ((val16 & 0x03) == cap_IBSS){ + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else if ((val16 & 0x03) == 0x00){ + u8 *mesh_id_ie, *mesh_conf_ie; + sint mesh_id_ie_len, mesh_conf_ie_len; -#ifdef CONFIG_WMMPS_STA - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - /* reset currently related uapsd setting when the connection has broken */ - pmlmepriv->qospriv.uapsd_max_sp_len = 0; - pmlmepriv->qospriv.uapsd_tid = 0; - pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0; - pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0; - pmlmepriv->qospriv.uapsd_ap_supported = 0; - } -#endif /* CONFIG_WMMPS_STA */ -#ifdef CONFIG_RTS_FULL_BW - rtw_set_rts_bw(padapter); -#endif/*CONFIG_RTS_FULL_BW*/ + mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset); + mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset); + if (mesh_id_ie || mesh_conf_ie) { + if (!mesh_id_ie) { + RTW_INFO("cannot find Mesh ID for survey event\n"); + return _FAIL; + } + if (mesh_id_ie_len) { + if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) { + RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len); + return _FAIL; + } + _rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len); + bssid->mesh_id.SsidLength = mesh_id_ie_len; + } else + bssid->mesh_id.SsidLength = 0; -} + if (!mesh_conf_ie) { + RTW_INFO("cannot find Mesh config for survey event\n"); + return _FAIL; + } + if (mesh_conf_ie_len != 7) { + RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len); + return _FAIL; + } -void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) -{ - struct sta_info *psta; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - struct sta_priv *pstapriv = &padapter->stapriv; - u8 join_type; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + bssid->InfrastructureMode = Ndis802_11_mesh; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else { + /* default cases */ + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } + } -#if (!defined(CONFIG_IOCTL_CFG80211)) || defined(CONFIG_LAYER2_ROAMING) - struct security_priv *psecuritypriv = &padapter->securitypriv; -#endif + if (val16 & BIT(4)) + bssid->Privacy = 1; + else + bssid->Privacy = 0; - if (pmlmepriv->wpa_phase == _TRUE) - pmlmepriv->wpa_phase = _FALSE; + bssid->Configuration.ATIMWindow = 0; - if (join_res < 0) { - join_type = 1; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) - rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED); + /* 20/40 BSS Coexistence check */ + if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_80211N_HT + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset); + if (p && len > 0) { + struct HT_caps_element *pHT_caps; + pHT_caps = (struct HT_caps_element *)(p + 2); - rtw_btcoex_connect_notify(padapter, join_type); + if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14)) + pmlmepriv->num_FortyMHzIntolerant++; + } else + pmlmepriv->num_sta_no_ht++; +#endif /* CONFIG_80211N_HT */ - goto exit_mlmeext_joinbss_event_callback; } -#ifdef CONFIG_ARP_KEEP_ALIVE - pmlmepriv->bGetGateway = 1; - pmlmepriv->GetGatewayTryCnt = 0; -#endif - -#ifdef CONFIG_AP_MODE - if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - /* update bc/mc sta_info */ - update_bmc_sta(padapter); +#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1 + if (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { + RTW_INFO("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%d\n" + , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig + , rtw_get_oper_ch(padapter) + , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->PhyInfo.rssi + ); } #endif - /* turn on dynamic functions */ - /* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */ + /* mark bss info receving from nearby channel as SignalQuality 101 */ + if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) + bssid->PhyInfo.SignalQuality = 101; - /* update IOT-releated issue */ - update_IOT_info(padapter); +#ifdef CONFIG_RTW_80211K + p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset); + if (p) + _rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1)); - #ifdef CONFIG_RTS_FULL_BW - rtw_set_rts_bw(padapter); - #endif/*CONFIG_RTS_FULL_BW*/ + /* save freerun counter */ + bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt; +#endif + return _SUCCESS; +} - rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates); +void start_create_ibss(_adapter *padapter) +{ + unsigned short caps; + u8 val8; + u8 join_type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 do_rfk = _FALSE; + pmlmeext->chandef.chan = (u8)pnetwork->Configuration.DSConfig; + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); - /* BCN interval */ - rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval)); + /* update wireless mode */ + update_wireless_mode(padapter); /* udpate capability */ - update_capinfo(padapter, pmlmeinfo->capability); + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); + if (caps & cap_IBSS) { /* adhoc master */ + /* set_opmode_cmd(padapter, adhoc); */ /* removed */ - /* WMM, Update EDCA param */ - WMMOnAssocRsp(padapter); -#ifdef CONFIG_80211N_HT - /* HT */ - HTOnAssocRsp(padapter); -#endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT - /* VHT */ - VHTOnAssocRsp(padapter); -#endif + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); - psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); - if (psta) { /* only for infra. mode */ - psta->wireless_mode = pmlmeext->cur_wireless_mode; + do_rfk = _TRUE; + /* switch channel */ + set_channel_bwmode(padapter, + pmlmeext->chandef.chan, + CHAN_OFFSET_NO_EXT, + CHANNEL_WIDTH_20, + do_rfk); - /* set per sta rate after updating HT cap. */ - set_sta_rate(padapter, psta); + beacon_timing_control(padapter); - rtw_sta_media_status_rpt(padapter, psta, 1); + /* issue beacon */ + if (send_beacon(padapter) == _FAIL) { - /* wakeup macid after join bss successfully to ensure - the subsequent data frames can be sent out normally */ - rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); + report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else { + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - rtw_xmit_queue_clear(psta); + report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + rtw_indicate_connect(padapter); + } + } else { + RTW_INFO("start_create_ibss, invalid cap:%x\n", caps); + return; } +} -#ifndef CONFIG_IOCTL_CFG80211 - if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) - rtw_sec_restore_wep_key(padapter); -#endif /* CONFIG_IOCTL_CFG80211 */ - - if (rtw_port_switch_chk(padapter) == _TRUE) - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); - - join_type = 2; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); +void start_clnt_join(_adapter *padapter) +{ + unsigned short caps; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + int beacon_timeout; + u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { - rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED); + /* update wireless mode */ + update_wireless_mode(padapter); - /* correcting TSF */ - correct_TSF(padapter, MLME_STA_CONNECTED); + /* udpate capability */ + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); - /* set_link_timer(pmlmeext, DISCONNECT_TO); */ + /* check if sta is ASIX peer and fix IOT issue if it is. */ + /*GEORGIA_TODO_FIXIT_HAL_DEP*/ + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { + u8 iot_flag = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); } -#ifdef CONFIG_LPS - #ifndef CONFIG_FW_MULTI_PORT_SUPPORT - if (get_hw_port(padapter) == HW_PORT0) - #endif - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY); -#endif - - rtw_btcoex_connect_notify(padapter, join_type); + if (caps & cap_ESS) { + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); -#ifdef CONFIG_BEAMFORMING - if (psta) - beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0); -#endif/*CONFIG_BEAMFORMING*/ +#ifdef CONFIG_DEAUTH_BEFORE_CONNECT + /* Because of AP's not receiving deauth before */ + /* AP may: 1)not response auth or 2)deauth us after link is complete */ + /* issue deauth before issuing auth to deal with the situation */ -exit_mlmeext_joinbss_event_callback: + /* Commented by Albert 2012/07/21 */ + /* For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */ + { +#ifdef CONFIG_P2P + _queue *queue = &(padapter->mlmepriv.scanned_queue); + _list *head = get_list_head(queue); + _list *pos = get_next(head); + struct wlan_network *scanned = NULL; + u8 ie_offset = 0; + bool has_p2p_ie = _FALSE; - rtw_join_done_chk_ch(padapter, join_res); -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_join_done(padapter); -#endif + _rtw_spinlock_bh(&(padapter->mlmepriv.scanned_queue.lock)); -#ifdef CONFIG_LAYER2_ROAMING - if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) && - (pmlmepriv->roam_network)) { - struct xmit_frame *rframe; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _list *plist, *phead; - _irqL irqL; - _pkt *pkt; - - padapter->mlmepriv.roam_network = NULL; - _enter_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); - phead = get_list_head(&pxmitpriv->rpkt_queue); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - rframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - plist = get_next(plist); - rtw_list_delete(&rframe->list); - pkt = rframe->pkt; - rframe->pkt = NULL; - rtw_xmit_posthandle(padapter, rframe, pkt); - } - _exit_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); - } -#endif - RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__); -} + for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) { -/* currently only adhoc mode will go here */ -void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) -{ - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 join_type; + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); - RTW_INFO("%s\n", __FUNCTION__); + if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + ) { + ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); + if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL)) + has_p2p_ie = _TRUE; + break; + } + } - if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */ - /* nothing to do */ - } else { /* adhoc client */ - #ifdef CONFIG_AP_MODE - /* update TSF Value */ - /* update_TSF(pmlmeext, pframe, len); */ + _rtw_spinunlock_bh(&(padapter->mlmepriv.scanned_queue.lock)); - /* correcting TSF */ - correct_TSF(padapter, MLME_ADHOC_STARTED); + if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE) +#endif /* CONFIG_P2P */ + /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + } +#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */ - /* start beacon */ - if (send_beacon(padapter) == _FAIL) - rtw_warn_on(1); + /* here wait for receiving the beacon to start auth */ + /* and enable a timer */ + beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval); + set_link_timer(pmlmeext, beacon_timeout); + /*_set_timer(&padapter->mlmepriv.assoc_timer, + (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);*/ + set_assoc_timer(&padapter->mlmepriv, + (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); - pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; - #endif +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter)) { + rtw_ft_start_clnt_join(padapter); + } else +#endif + { + rtw_sta_linking_test_set_start(); + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; } - join_type = 2; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - rtw_btcoex_connect_notify(padapter, join_type); - } +#ifdef CONFIG_DRV_FAKE_AP + _set_timer(&adapter_to_dvobj(padapter)->fakeap.bcn_timer, 5); +#endif /* CONFIG_DRV_FAKE_AP */ + } else if (caps & cap_IBSS) { /* adhoc client */ + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); - /* update adhoc sta_info */ - update_sta_info(padapter, psta); + beacon_timing_control(padapter); - rtw_hal_update_sta_ra_info(padapter, psta); + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; - /* ToDo: HT for Ad-hoc */ - psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel); - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); + report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); + } else { + /* RTW_INFO("marc: invalid cap:%x\n", caps); */ + return; + } - /* rate radaptive */ - Update_RA_Entry(padapter, psta); } -void mlmeext_sta_del_event_callback(_adapter *padapter) +void start_clnt_auth(_adapter *padapter) { - if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) - rtw_mlmeext_disconnect(padapter); -} + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -/**************************************************************************** + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ -Following are the functions for the timer handlers + pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); + pmlmeinfo->state |= WIFI_FW_AUTH_STATE; -*****************************************************************************/ -void _linked_info_dump(_adapter *padapter) -{ - if (padapter->bLinkInfoDump) { - rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); - rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE); - } -} -/******************************************************************** + pmlmeinfo->auth_seq = 1; + pmlmeinfo->reauth_count = 0; + pmlmeinfo->reassoc_count = 0; + pmlmeinfo->link_count = 0; + pmlmeext->retry = 0; + +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter)) { + rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA); + RTW_PRINT("start ft auth\n"); + } else +#endif + RTW_PRINT("start auth\n"); + +#ifdef CONFIG_IOCTL_CFG80211 + if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) { + if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) { + RTW_INFO("SAE: PMKSA cache entry found\n"); + padapter->securitypriv.auth_alg = WLAN_AUTH_OPEN; + goto no_external_auth; + } -When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds, -recipient station will teardown the block ack by issuing DELBA frame. + RTW_PRINT("SAE: start external auth\n"); + rtw_cfg80211_external_auth_request(padapter, NULL); + return; + } +no_external_auth: +#endif /* CONFIG_IOCTL_CFG80211 */ -*********************************************************************/ -void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) -{ - int i = 0; - int ret = _SUCCESS; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + issue_auth(padapter, NULL, 0); - /* - IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300). - AP is originator.AP does not transmit unicast packets when STA response its BAR. - This case probably occur ap issue BAR after AP builds BA. + set_link_timer(pmlmeext, REAUTH_TO); - Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup. - The inactivity timer is not reset when MPDUs corresponding to other TIDs are received. - */ - if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) { - for (i = 0; i < TID_NUM ; i++) { - if ((psta->recvreorder_ctrl[i].enable) && - (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) { - if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { - /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ - if (!from_timer) - ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1); - else - issue_del_ba(padapter, psta->cmn.mac_addr, i, 39, 0); - psta->recvreorder_ctrl[i].enable = _FALSE; - if (ret != _FAIL) - psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; - rtw_reset_continual_no_rx_packet(psta, i); - } - } else { - /* The inactivity timer is reset when MPDUs to the TID is received. */ - rtw_reset_continual_no_rx_packet(psta, i); - } - } - } } -u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) +void start_clnt_assoc(_adapter *padapter) { - u8 ret = _FALSE; -#ifdef DBG_EXPIRATION_CHK struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" - /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ - ", retry:%u\n" - , FUNC_ADPT_ARG(padapter) - , STA_RX_PKTS_DIFF_ARG(psta) - , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts - , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts - /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts - , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts - , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts - , pmlmeinfo->bcn_interval*/ - , pmlmeext->retry - ); + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ - RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) - , sta_tx_pkts(psta) - , pmlmeinfo->link_count - ); -#endif + pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); + pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); - if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)) - && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) - && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta) - ) - ret = _FALSE; +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter) + #ifdef CONFIG_RTW_WNM + || rtw_wnm_btm_reassoc_req(padapter) + #endif + ) + issue_reassocreq(padapter); else - ret = _TRUE; - - sta_update_last_rx_pkts(psta); +#endif + issue_assocreq(padapter); - return ret; + set_link_timer(pmlmeext, REASSOC_TO); } -u8 chk_adhoc_peer_is_alive(struct sta_info *psta) +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated) { - u8 ret = _TRUE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef DBG_EXPIRATION_CHK - RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" - /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ - ", expire_to:%u\n" - , MAC_ARG(psta->cmn.mac_addr) - , psta->cmn.rssi_stat.rssi - , STA_RX_PKTS_DIFF_ARG(psta) - , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts - , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts - /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts - , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts - , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts - , pmlmeinfo->bcn_interval*/ - , psta->expire_to - ); -#endif + if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; - if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta) - && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) - && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)) - ret = _FALSE; + RTW_INFO("%s\n", __FUNCTION__); - sta_update_last_rx_pkts(psta); + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) { + if (report_join_res(padapter, -2, reason) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else + RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); +#ifdef CONFIG_RTW_80211R + rtw_ft_roam_status_reset(padapter); +#endif +#ifdef CONFIG_RTW_WNM + rtw_wnm_reset_btm_state(padapter); +#endif + } - return ret; + return _SUCCESS; } -#ifdef CONFIG_TDLS -u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta) +/* + * Return channel index of struct dvobj_priv.rf_ctl.channel_set[] == + * bss->Configuration.DSConfig, or -1 if not found. + */ +static int rtw_hidden_ssid_bss_count(_adapter *adapter, WLAN_BSSID_EX *bss) { - if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts) - && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts)) - return _FALSE; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; + int chset_idx; - return _TRUE; -} + if (bss->InfrastructureMode != Ndis802_11Infrastructure) + return -1; -void linked_status_chk_tdls(_adapter *padapter) -{ - struct candidate_pool { - struct sta_info *psta; - u8 addr[ETH_ALEN]; - }; - struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; - u8 ack_chk; - struct sta_info *psta; - int i, num_teardown = 0, num_checkalive = 0; - _list *plist, *phead; - struct tdls_txmgmt txmgmt; - struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM]; - struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM]; - u8 tdls_sta_max = _FALSE; + if (!hidden_ssid_ap(bss)) + return -1; -#define ALIVE_MIN 2 -#define ALIVE_MAX 5 + chset_idx = rtw_chset_search_ch(chset, bss->Configuration.DSConfig); + if (chset_idx < 0) + return chset_idx; - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memset(checkalive, 0x00, sizeof(checkalive)); - _rtw_memset(teardown, 0x00, sizeof(teardown)); + chset[chset_idx].hidden_bss_cnt++; + return chset_idx; +} - if ((padapter->tdlsinfo.link_established == _TRUE)) { - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (i = 0; i < NUM_STA; i++) { - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); +/**************************************************************************** - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); +Following are the functions to report events - if (psta->tdls_sta_state & TDLS_LINKED_STATE) { - psta->alive_count++; - if (psta->alive_count >= ALIVE_MIN) { - if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) { - if (psta->alive_count < ALIVE_MAX) { - _rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN); - checkalive[num_checkalive].psta = psta; - num_checkalive++; - } else { - _rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN); - teardown[num_teardown].psta = psta; - num_teardown++; - } - } else - psta->alive_count = 0; - } - psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts; - psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts; +*****************************************************************************/ - if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) { - tdls_sta_max = _TRUE; - break; - } - } - } +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct survey_event *psurvey_evt; + struct rtw_evt_header *evt_hdr; + struct mlme_ext_priv *pmlmeext; + struct cmd_priv *pcmdpriv; + /* u8 *pframe = precv_frame->u.hdr.rx_data; */ + /* uint len = precv_frame->u.hdr.len; */ +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + RT_CHANNEL_INFO *chset; + int ch_set_idx = -1; +#endif /* RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ - if (tdls_sta_max == _TRUE) - break; - } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - if (num_checkalive > 0) { - for (i = 0; i < num_checkalive; i++) { - _rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN); - issue_tdls_dis_req(padapter, &txmgmt); - issue_tdls_dis_req(padapter, &txmgmt); - issue_tdls_dis_req(padapter, &txmgmt); - } - } + if (!padapter) + return; - if (num_teardown > 0) { - for (i = 0; i < num_teardown; i++) { - RTW_INFO("[%s %d] Send teardown to "MAC_FMT"\n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr)); - txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; - _rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN); - issue_tdls_teardown(padapter, &txmgmt, _FALSE); - } - } + pmlmeext = &padapter->mlmeextpriv; + pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + pcmd_obj->padapter = padapter; + + cmdsz = (sizeof(struct survey_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; } -} -#endif /* CONFIG_TDLS */ + _rtw_init_listhead(&pcmd_obj->list); -inline int rtw_get_rx_chk_limit(_adapter *adapter) -{ - return adapter->stapriv.rx_chk_limit; -} + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; -inline void rtw_set_rx_chk_limit(_adapter *adapter, int limit) -{ - adapter->stapriv.rx_chk_limit = limit; -} + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; -/* from_timer == 1 means driver is in LPS */ -void linked_status_chk(_adapter *padapter, u8 from_timer) -{ - u32 i; - struct sta_info *psta; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_LAYER2_ROAMING - struct recv_priv *precvpriv = &padapter->recvpriv; -#endif + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct survey_event); + evt_hdr->id = EVT_SURVEY; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); -#ifdef CONFIG_RTW_WDS - rtw_wds_gptr_expire(padapter); -#endif + psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - if (padapter->registrypriv.mp_mode == _TRUE) - return; - - if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) + if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pevtcmd, cmdsz); return; + } - if (is_client_associated_to_ap(padapter)) { - /* linked infrastructure client mode */ - - int tx_chk = _SUCCESS, rx_chk = _SUCCESS; - int rx_chk_limit; - int link_count_limit; +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + ch_set_idx = rtw_hidden_ssid_bss_count(padapter, &psurvey_evt->bss); -#if defined(CONFIG_RTW_REPEATER_SON) - rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS); -#elif defined(CONFIG_LAYER2_ROAMING) - if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { - RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val); - if ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) - && (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) { -#ifdef CONFIG_RTW_80211K - rtw_roam_nb_discover(padapter, _FALSE); -#endif - pmlmepriv->need_to_roam = _TRUE; - rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); - pmlmepriv->last_roaming = rtw_get_current_time(); - } else - pmlmepriv->need_to_roam = _FALSE; - } -#endif -#ifdef CONFIG_MCC_MODE - /* - * due to tx ps null date to ao, so ap doest not tx pkt to driver - * we may check chk_ap_is_alive fail, and may issue_probereq to wrong channel under sitesurvey - * don't keep alive check under MCC - */ - if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE) - return; -#endif + chset = adapter_to_chset(padapter); + if ((ch_set_idx >= 0) && (chset[ch_set_idx].hidden_bss_cnt == 1) + && pmlmeext->sitesurvey_res.scan_param) { + struct rtw_phl_scan_param *phl_scan; + struct phl_module_op_info op_info = {0}; + u8 ch; + int i; - rx_chk_limit = rtw_get_rx_chk_limit(padapter); + phl_scan = pmlmeext->sitesurvey_res.scan_param; + ch = chset[ch_set_idx].ChannelNum; + for (i = 0; i < phl_scan->ch_num; i++) { + if (phl_scan->ch[i].channel != ch) + continue; + if (phl_scan->ch[i].type != RTW_PHL_SCAN_PASSIVE) + break; -#ifdef CONFIG_ARP_KEEP_ALIVE - if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) { - RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt); - pmlmepriv->GetGatewayTryCnt++; - if (rtw_gw_addr_query(padapter) == 0) - pmlmepriv->bGetGateway = 0; - else { - _rtw_memset(pmlmepriv->gw_ip, 0, 4); - _rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN); - } - } -#endif -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) { - if (!from_timer) - link_count_limit = 3; /* 8 sec */ - else - link_count_limit = 15; /* 32 sec */ - } else -#endif /* CONFIG_P2P */ - { - if (!from_timer) - link_count_limit = 7; /* 16 sec */ - else - link_count_limit = 29; /* 60 sec */ + op_info.op_code = FG_REQ_OP_NOTIFY_BCN_RCV; + op_info.inbuf = &ch; + op_info.inlen = 1; + rtw_phl_set_cur_cmd_info(GET_PHL_INFO(adapter_to_dvobj(padapter)), + padapter->phl_role->hw_band, + &op_info); + break; } + } +#else /* !RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ + rtw_hidden_ssid_bss_count(padapter, &psurvey_evt->bss); +#endif /* !RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ -#ifdef CONFIG_TDLS -#ifdef CONFIG_TDLS_CH_SW - if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE) - return; -#endif /* CONFIG_TDLS_CH_SW */ + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); -#ifdef CONFIG_TDLS_AUTOCHECKALIVE - linked_status_chk_tdls(padapter); -#endif /* CONFIG_TDLS_AUTOCHECKALIVE */ -#endif /* CONFIG_TDLS */ + pmlmeext->sitesurvey_res.bss_cnt++; - psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); - if (psta != NULL) { - bool is_p2p_enable = _FALSE; -#ifdef CONFIG_P2P - is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE); -#endif + return; -#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC - /*issue delba when ap does not tx data packet that is Broadcom ap */ - rtw_delba_check(padapter, psta, from_timer); -#endif - if (chk_ap_is_alive(padapter, psta) == _FALSE) - rx_chk = _FAIL; +} - if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta)) - tx_chk = _FAIL; +/* +* @acs: aim to trigger channel selection +*/ +void report_surveydone_event(_adapter *padapter, bool acs, u8 flags) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK - if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) - ) { - u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; - u8 union_ch = 0, union_bw = 0, union_offset = 0; - u8 switch_channel_by_drv = _TRUE; + if (flags & RTW_CMDF_DIRECTLY) { + struct surveydone_event survey_done; - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't switch channel under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - switch_channel_by_drv = _FALSE; - } -#endif - if (switch_channel_by_drv) { - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) - goto bypass_active_keep_alive; + survey_done.bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; + survey_done.activate_ch_cnt = pmlmeext->sitesurvey_res.activate_ch_cnt; + survey_done.acs = acs; + RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", + survey_done.bss_cnt, padapter->setband, ADPT_ARG(padapter)); + rtw_surveydone_event_callback(padapter, (u8 *)&survey_done); + } else { - /* switch to correct channel of current network before issue keep-alive frames */ - if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_ch = rtw_get_oper_ch(padapter); - backup_bw = rtw_get_oper_bw(padapter); - backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - } - } + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct surveydone_event *psurveydone_evt; + struct rtw_evt_header *evt_hdr; - if (rx_chk != _SUCCESS) - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1); + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; - if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { - if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) - tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1); - else - tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1); - /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ - if (tx_chk == _SUCCESS && !is_p2p_enable) - rx_chk = _SUCCESS; - } + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + pcmd_obj->padapter = padapter; - /* back to the original operation channel */ - if (backup_ch > 0 && switch_channel_by_drv) - set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + cmdsz = (sizeof(struct surveydone_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } -bypass_active_keep_alive: - ; - } else -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - { - if (rx_chk != _SUCCESS) { - if (pmlmeext->retry == 0) { -#ifdef DBG_EXPIRATION_CHK - RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); -#endif - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); - } - } + _rtw_init_listhead(&pcmd_obj->list); - if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit -#ifdef CONFIG_MCC_MODE - /* FW tx nulldata under MCC mode, we just check ap is alive */ - && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) -#endif /* CONFIG_MCC_MODE */ - ) { - #ifdef DBG_EXPIRATION_CHK - RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0); - #endif - if (from_timer || rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) - tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0); - else - tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1); - } - } + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; - if (rx_chk == _FAIL) { - pmlmeext->retry++; - if (pmlmeext->retry > rx_chk_limit) { - RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n", - FUNC_ADPT_ARG(padapter)); - receive_disconnect(padapter, pmlmeinfo->network.MacAddress - , WLAN_REASON_EXPIRATION_CHK, _FALSE); - return; - } - } else - pmlmeext->retry = 0; + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; - if (tx_chk == _FAIL) - pmlmeinfo->link_count %= (link_count_limit + 1); - else { - psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts; - pmlmeinfo->link_count = 0; - } + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct surveydone_event); + evt_hdr->id = EVT_SURVEY_DONE; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - } /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */ + psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; + psurveydone_evt->activate_ch_cnt = pmlmeext->sitesurvey_res.activate_ch_cnt; + psurveydone_evt->acs = acs; - } else if (is_client_associated_to_ibss(padapter)) { - _irqL irqL; - _list *phead, *plist, dlist; + RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", + psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter)); - _rtw_init_listhead(&dlist); + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + } - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + return; +} - for (i = 0; i < NUM_STA; i++) { +u32 report_join_res(_adapter *padapter, int aid_res, u16 status) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct joinbss_event *pjoinbss_evt; + struct rtw_evt_header *evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u32 ret = _FAIL; - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - plist = get_next(plist); + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + goto exit; + pcmd_obj->padapter = padapter; - if (is_broadcast_mac_addr(psta->cmn.mac_addr)) - continue; + cmdsz = (sizeof(struct joinbss_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + goto exit; + } - if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) - psta->expire_to = pstapriv->adhoc_expire_to; - else - psta->expire_to--; + _rtw_init_listhead(&pcmd_obj->list); - if (psta->expire_to <= 0) { - rtw_list_delete(&psta->list); - rtw_list_insert_tail(&psta->list, &dlist); - } - } - } + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; - plist = get_next(&dlist); - while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, list); - plist = get_next(plist); - rtw_list_delete(&psta->list); - RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); - report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); - } - } + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct joinbss_event); + evt_hdr->id = EVT_JOINBSS; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); -} + pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = aid_res; -void survey_timer_hdl(void *ctx) -{ - _adapter *padapter = (_adapter *)ctx; - struct cmd_obj *cmd; - struct sitesurvey_parm *psurveyPara; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + RTW_INFO("report_join_res(%d, %u)\n", aid_res, status); - if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) { - cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (cmd == NULL) { - rtw_warn_on(1); - goto exit; - } - psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); - if (psurveyPara == NULL) { - rtw_warn_on(1); - rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); - goto exit; - } + rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status); - init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, CMD_SITE_SURVEY); - rtw_enqueue_cmd(pcmdpriv, cmd); - } + + ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); exit: - return; + return ret; } -#ifdef CONFIG_RTW_REPEATER_SON -/* 100ms pass, stop rson_scan */ -void rson_timer_hdl(void *ctx) +void report_wmm_edca_update(_adapter *padapter) { - _adapter *padapter = (_adapter *)ctx; - - rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE); -} - -#endif + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct wmm_event *pwmm_event; + struct rtw_evt_header *evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT -void rtw_tbtx_xmit_timer_hdl(void *ctx) -{ - _adapter *padapter = (_adapter *)ctx; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + pcmd_obj->padapter = padapter; - if (ATOMIC_READ(&padapter->tbtx_remove_tx_pause) == _TRUE){ - ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE); - rtw_tx_control_cmd(padapter); - }else { - rtw_issue_action_token_rel(padapter); - ATOMIC_SET(&padapter->tbtx_tx_pause, _TRUE); - rtw_tx_control_cmd(padapter); - _set_timer(&pmlmeext->tbtx_xmit_timer, MAX_TXPAUSE_DURATION); - ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _TRUE); + cmdsz = (sizeof(struct wmm_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; } -} -#ifdef CONFIG_AP_MODE -void rtw_tbtx_token_dispatch_timer_hdl(void *ctx) -{ - _adapter *padapter = (_adapter *)ctx; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - _irqL irqL; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - _list *phead, *plist; - int i, found = _FALSE; - u8 nr_send, th_idx = 0; + _rtw_init_listhead(&pcmd_obj->list); - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - RTW_DBG("%s:asoc_cnt: %d\n",__func__, pstapriv->tbtx_asoc_list_cnt); + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; - // check number of TBTX sta - if (padapter->stapriv.tbtx_asoc_list_cnt < 2) - goto exit; + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; - // dispatch token - - nr_send = RTW_DIV_ROUND_UP(pstapriv->tbtx_asoc_list_cnt, NR_TBTX_SLOT); + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct wmm_event); + evt_hdr->id = EVT_WMM_UPDATE; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - phead = &pstapriv->asoc_list; - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - /* psta is supporting TBTX */ - if ((!psta) || (!psta->tbtx_enable)) - RTW_DBG("sta tbtx_enable is false\n"); - else { - for (i = 0; i < nr_send; i++) { - if (pstapriv->last_token_holder == psta) { - found = _TRUE; - goto outof_loop; - } - } - } - plist = get_next(plist); - } -outof_loop: - - RTW_DBG("rtw_tbtx_token_dispatch_timer_hdl() th_idx=%d, nr_send=%d, phead=%p, plist=%p, found=%d\n ", th_idx , nr_send, phead, plist, found); - if (!found) { - plist = get_next(phead); - while(rtw_end_of_queue_search(phead, plist) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - if ((!psta) || (!psta->tbtx_enable)) - RTW_DBG("sta tbtx_enable is false\n"); - else { - pstapriv->token_holder[th_idx] = psta; - rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]); - break; - } - plist = get_next(plist); - } - } + pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + pwmm_event->wmm = 0; - for (i=th_idx; itbtx_enable)) - RTW_DBG("sta tbtx_enable is false\n"); - else { - pstapriv->token_holder[th_idx] = psta; - rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]); - i++; - } - } - ATOMIC_SET(&pstapriv->nr_token_keeper, nr_send); - + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; -exit: - // set_timer - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - _set_timer(&pmlmeext->tbtx_token_dispatch_timer, TBTX_TX_DURATION); } -#endif /* CONFIG_AP_MODE */ -#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */ -void link_timer_hdl(void *ctx) +u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated) { - _adapter *padapter = (_adapter *)ctx; - /* static unsigned int rx_pkt = 0; */ - /* static u64 tx_cnt = 0; */ - /* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* struct sta_priv *pstapriv = &padapter->stapriv; */ -#ifdef CONFIG_RTW_80211R - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); -#endif - - if (rtw_sta_linking_test_force_fail()) - RTW_INFO("rtw_sta_linking_test_force_fail\n"); + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct sta_info *psta; + int mac_id = -1; + struct stadel_event *pdel_sta_evt; + struct rtw_evt_header *evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u8 res = _SUCCESS; - if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) { - RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter)); - pmlmeinfo->state = WIFI_FW_NULL_STATE; - report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE); + /* prepare cmd parameter */ + cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + res = _FAIL; goto exit; } - if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { - RTW_INFO("link_timer_hdl:no beacon while connecting\n"); - pmlmeinfo->state = WIFI_FW_NULL_STATE; - report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE); - } else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) { - -#ifdef CONFIG_IOCTL_CFG80211 - if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) - return; -#endif /* CONFIG_IOCTL_CFG80211 */ - - /* re-auth timer */ - if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) { - /* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */ - /* { */ - pmlmeinfo->state = 0; - if (pmlmeinfo->auth_status) { - report_join_res(padapter, -1, pmlmeinfo->auth_status); - pmlmeinfo->auth_status = 0; /* reset */ - } else - report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); - return; - /* } */ - /* else */ - /* { */ - /* pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */ - /* pmlmeinfo->reauth_count = 0; */ - /* } */ - } + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct stadel_event); + evt_hdr->id = EVT_DEL_STA; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - RTW_INFO("link_timer_hdl: auth timeout and try again\n"); - pmlmeinfo->auth_seq = 1; - issue_auth(padapter, NULL, 0); - set_link_timer(pmlmeext, REAUTH_TO); - } else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) { - /* re-assoc timer */ - if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { - pmlmeinfo->state = WIFI_FW_NULL_STATE; -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter)) { - psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); - if (psta) - rtw_free_stainfo(padapter, psta); - } -#endif - report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE); - return; - } + pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); + _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); + psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); + if (psta) + mac_id = (int)psta->phl_sta->macid; + else + mac_id = (-1); + pdel_sta_evt->mac_id = mac_id; + pdel_sta_evt->locally_generated = locally_generated; -#ifdef CONFIG_RTW_80211R - if (rtw_ft_roam(padapter)) { - RTW_INFO("link_timer_hdl: reassoc timeout and try again\n"); - issue_reassocreq(padapter); - } else -#endif - { - RTW_INFO("link_timer_hdl: assoc timeout and try again\n"); - issue_assocreq(padapter); + if (!enqueue) { + /* do directly */ + rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt); + rtw_mfree(pevtcmd, cmdsz); + } else { + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) { + rtw_mfree(pevtcmd, cmdsz); + res = _FAIL; + goto exit; } + pcmd_obj->padapter = padapter; - set_link_timer(pmlmeext, REASSOC_TO); - } - -exit: - return; -} - -void addba_timer_hdl(void *ctx) -{ - struct sta_info *psta = (struct sta_info *)ctx; + _rtw_init_listhead(&pcmd_obj->list); + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; -#ifdef CONFIG_80211N_HT - struct ht_priv *phtpriv; + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; - if (!psta) - return; + res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + } - phtpriv = &psta->htpriv; +exit: - if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { - if (phtpriv->candidate_tid_bitmap) - phtpriv->candidate_tid_bitmap = 0x0; + RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res); - } -#endif /* CONFIG_80211N_HT */ + return res; } -#ifdef CONFIG_IEEE80211W -void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason) +void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr) { struct cmd_obj *pcmd_obj; u8 *pevtcmd; u32 cmdsz; - struct sta_info *psta; - int mac_id; - struct stadel_event *pdel_sta_evt; + struct stassoc_event *padd_sta_evt; struct rtw_evt_header *evt_hdr; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmd_obj == NULL) return; + pcmd_obj->padapter = padapter; - cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header)); + cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header)); pevtcmd = (u8 *)rtw_zmalloc(cmdsz); if (pevtcmd == NULL) { rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); @@ -13337,2925 +9988,3117 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re pcmd_obj->rspsz = 0; evt_hdr = (struct rtw_evt_header *)(pevtcmd); - evt_hdr->len = sizeof(struct stadel_event); - evt_hdr->id = EVT_TIMEOUT_STA; + evt_hdr->len = sizeof(struct stassoc_event); + evt_hdr->id = EVT_ADD_STA; evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header)); - _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); - _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); + padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); + RTW_INFO("report_add_sta_event: add STA\n"); - psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); - if (psta) - mac_id = (int)psta->cmn.mac_id; - else - mac_id = (-1); + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - pdel_sta_evt->mac_id = mac_id; + return; +} - RTW_INFO("report_del_sta_event: delete STA, mac_id=%d\n", mac_id); +/**************************************************************************** - rtw_enqueue_cmd(pcmdpriv, pcmd_obj); +Following are the event callback functions - return; +*****************************************************************************/ + +/* for sta/adhoc mode */ +void update_sta_info(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* ERP */ + VCS_update(padapter, psta); + +#ifdef CONFIG_80211N_HT + /* HT */ + if (pmlmepriv->htpriv.ht_option) { + psta->htpriv.ht_option = _TRUE; + + psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; + + psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20)) + psta->htpriv.sgi_20m = _TRUE; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40)) + psta->htpriv.sgi_40m = _TRUE; + + psta->qos_option = _TRUE; + + psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap; + psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap; + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + + _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); + #ifdef CONFIG_BEAMFORMING + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + #endif + } else +#endif /* CONFIG_80211N_HT */ + { +#ifdef CONFIG_80211N_HT + psta->htpriv.ht_option = _FALSE; + psta->htpriv.ampdu_enable = _FALSE; + psta->htpriv.tx_amsdu_enable = _FALSE; + psta->htpriv.sgi_20m = _FALSE; + psta->htpriv.sgi_40m = _FALSE; +#endif /* CONFIG_80211N_HT */ + psta->qos_option = _FALSE; + + } + +#ifdef CONFIG_80211N_HT + psta->htpriv.ch_offset = pmlmeext->chandef.offset; + + psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ + psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ +#endif /* CONFIG_80211N_HT */ + + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; + + /* QoS */ + if (pmlmepriv->qospriv.qos_option) + psta->qos_option = _TRUE; + +#ifdef CONFIG_80211AC_VHT + _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + if (psta->vhtpriv.vht_option) { + /* ToDo: need to API to inform hal_sta->ra_info.is_vht_enable */ + /* psta->phl_sta->ra_info.is_vht_enable = _TRUE; */ + #ifdef CONFIG_BEAMFORMING + psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap; + #endif /*CONFIG_BEAMFORMING*/ + } +#endif /* CONFIG_80211AC_VHT */ + +#ifdef CONFIG_80211AX_HE + _rtw_memcpy(&psta->hepriv, &pmlmepriv->hepriv, sizeof(struct he_priv)); +#endif /* CONFIG_80211AX_HE */ + + /* ToDo: need to API to inform hal_sta->ra_info.is_support_sgi */ + /* psta->phl_sta->ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); */ + + _rtw_spinlock_bh(&psta->lock); + psta->state = WIFI_ASOC_STATE; + _rtw_spinunlock_bh(&psta->lock); + +} + +void update_sta_trx_nss(_adapter *adapter, struct sta_info *psta) +{ + s8 tx_nss, rx_nss; + + /* get adapter tx nss */ + tx_nss = rtw_get_sta_tx_nss(adapter, psta); + /* get adapter rx nss */ + rx_nss = rtw_get_sta_rx_nss(adapter, psta); + + /* peer sta tx should referece adapter rx_nss */ + psta->phl_sta->asoc_cap.nss_tx = rx_nss; + /* peer sta rx should referece adapter tx_nss */ + psta->phl_sta->asoc_cap.nss_rx = tx_nss; + +#ifdef CONFIG_CTRL_TXSS_BY_TP + rtw_ctrl_txss_update(adapter, psta); +#endif + + RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n", + psta->phl_sta->macid, tx_nss, rx_nss); +} + +void update_sta_smps_cap(_adapter *adapter, struct sta_info *psta) +{ + /*Spatial Multiplexing Power Save*/ + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + #ifdef CONFIG_80211N_HT + if (psta->htpriv.ht_option) { + if (psta->htpriv.smps_cap == 0) + psta->phl_sta->asoc_cap.sm_ps = SM_PS_STATIC; + else if (psta->htpriv.smps_cap == 1) + psta->phl_sta->asoc_cap.sm_ps = SM_PS_DYNAMIC; + else + psta->phl_sta->asoc_cap.sm_ps = SM_PS_DISABLE; + } + #endif /* CONFIG_80211N_HT */ + } else { + psta->phl_sta->asoc_cap.sm_ps = SM_PS_DISABLE; + } + + RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n", + psta->phl_sta->macid, psta->phl_sta->asoc_cap.sm_ps); +} + +void update_sta_rate_mask(_adapter *padapter, struct sta_info *psta) +{ + u8 i, tx_nss; + u64 tx_ra_bitmap = 0, tmp64=0; + + if (psta == NULL) + return; + + /* b/g mode ra_bitmap */ + for (i = 0; i < sizeof(psta->bssrateset); i++) { + if (psta->bssrateset[i]) + tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f); + } + +#ifdef CONFIG_80211N_HT + if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) { + tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); +#ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) { + /* AC mode ra_bitmap */ + tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12); + } else +#endif /* CONFIG_80211AC_VHT */ + { + if (psta->htpriv.ht_option) { + /* n mode ra_bitmap */ + + /* Handling SMPS mode for AP MODE only*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) + /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/ + tx_nss = rtw_min(tx_nss, 1); + } + + tmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss); + tx_ra_bitmap |= (tmp64 << 12); + } + } + } +#endif /* CONFIG_80211N_HT */ + /* ToDo: Need API to inform hal_sta->ra_info.ramask */ + /* psta->phl_sta->ra_info.ramask = tx_ra_bitmap;*/ + psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f; +} + +void update_sta_ra_info(_adapter *padapter, struct sta_info *psta) +{ + update_sta_trx_nss(padapter, psta); + update_sta_smps_cap(padapter, psta); + update_sta_rate_mask(padapter, psta); +} + +#ifdef CONFIG_80211D +void rtw_joinbss_update_regulatory(_adapter *adapter, const WLAN_BSSID_EX *network) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + if (rfctl->regd_src == REGD_SRC_RTK_PRIV + && !rtw_rfctl_is_disable_sw_channel_plan(rfctl_to_dvobj(rfctl)) + ) { + struct mlme_priv *mlme = &adapter->mlmepriv; + const u8 *country_ie = NULL; + sint country_ie_len = 0; + + if (network) { + if (rtw_iface_accept_country_ie(adapter)) { + country_ie = rtw_get_ie(BSS_EX_TLV_IES(network) + , WLAN_EID_COUNTRY, &country_ie_len, BSS_EX_TLV_IES_LEN(network)); + if (country_ie) { + if (country_ie_len < 6) { + country_ie = NULL; + country_ie_len = 0; + } else + country_ie_len += 2; + } + } + } + + if (country_ie) { + rtw_buf_update(&mlme->recv_country_ie, &mlme->recv_country_ie_len, country_ie, country_ie_len); + if (rtw_apply_recv_country_ie_cmd(adapter, RTW_CMDF_DIRECTLY + , network->Configuration.DSConfig > 14 ? BAND_ON_5G : BAND_ON_24G + , network->Configuration.DSConfig, country_ie) != _SUCCESS + ) + RTW_WARN(FUNC_ADPT_FMT" rtw_apply_recv_country_ie_cmd() fail\n", FUNC_ADPT_ARG(adapter)); + } else + rtw_buf_free(&mlme->recv_country_ie, &mlme->recv_country_ie_len); + } +} + +static void rtw_leavebss_update_regulatory(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + + if (rfctl->regd_src == REGD_SRC_RTK_PRIV + && !rtw_rfctl_is_disable_sw_channel_plan(dvobj) + ) { + if (rtw_apply_recv_country_ie_cmd(adapter, RTW_CMDF_DIRECTLY, 0, 0, NULL) != _SUCCESS) + RTW_WARN(FUNC_ADPT_FMT" rtw_apply_recv_country_ie_cmd() fail\n", FUNC_ADPT_ARG(adapter)); + } } +#endif /* CONFIG_80211D */ + +void rtw_mlmeext_disconnect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 self_action = MLME_ACTION_UNKNOWN; + u8 state_backup = (pmlmeinfo->state & 0x03); + u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; + u8 *mac; + struct sta_info *sta; + + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STOPPED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STOPPED; + else if (MLME_IS_STA(padapter)) + self_action = MLME_STA_DISCONNECTED; + else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)) + self_action = MLME_ADHOC_STOPPED; + else { + RTW_INFO("state:0x%x\n", MLME_STATE(padapter)); + rtw_warn_on(1); + } + + /* check if sta is ASIX peer and fix IOT issue if it is. */ + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { + u8 iot_flag = _FALSE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + } + pmlmeinfo->state = WIFI_FW_NULL_STATE; + + /* switch to the 20M Hz mode after disconnect */ + pmlmeext->chandef.bw = CHANNEL_WIDTH_20; + pmlmeext->chandef.offset = CHAN_OFFSET_NO_EXT; +#ifdef CONFIG_CTRL_TXSS_BY_TP + pmlmeext->txss_1ss = _FALSE; +#endif + +#ifdef CONFIG_LAYER2_ROAMING +#define RTW_ROAM_DICONNECT_DELAY 20 + if (pmlmepriv->roam_network) + rtw_msleep_os(RTW_ROAM_DICONNECT_DELAY); +#endif + +#ifdef CONFIG_80211D + if (self_action == MLME_STA_DISCONNECTED) + rtw_leavebss_update_regulatory(padapter); +#endif + + /* before chanctx_del */ + mac = pmlmeinfo->network.MacAddress; + sta = rtw_get_stainfo(&padapter->stapriv, mac); + if (sta) + rtw_hw_disconnect(padapter, sta); + else + RTW_ERR(FUNC_ADPT_FMT ": can't find drv sta info for " + MAC_FMT " !\n", FUNC_ADPT_ARG(padapter), MAC_ARG(mac)); + + #ifdef CONFIG_DFS_MASTER + if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) { + /* DFS no need to check here for STA under OPCH_SW */ + rtw_dfs_rd_en_decision(padapter, self_action, 0); + } + #endif + + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ + + /* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */ + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + +#ifdef CONFIG_TDLS + padapter->tdlsinfo.ap_prohibited = _FALSE; -void clnt_sa_query_timeout(_adapter *padapter) -{ - struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + /* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */ + if (padapter->registrypriv.wifi_spec == 1) + padapter->tdlsinfo.ch_switch_prohibited = _FALSE; +#endif /* CONFIG_TDLS */ - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); - receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE); +#ifdef CONFIG_WMMPS_STA + if (MLME_IS_STA(padapter)) { + /* reset currently related uapsd setting when the connection has broken */ + pmlmepriv->qospriv.uapsd_max_sp_len = 0; + pmlmepriv->qospriv.uapsd_tid = 0; + pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0; + pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0; + pmlmepriv->qospriv.uapsd_ap_supported = 0; + } +#endif /* CONFIG_WMMPS_STA */ +#ifdef CONFIG_RTS_FULL_BW + rtw_set_rts_bw(padapter); +#endif/*CONFIG_RTS_FULL_BW*/ } -void sa_query_timer_hdl(void *ctx) +/* Return 0 for success, otherwise fail. */ +int rtw_set_hw_after_join(struct _ADAPTER *a, int join_res) { - struct sta_info *psta = (struct sta_info *)ctx; - _adapter *padapter = psta->padapter; - _irqL irqL; - struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_priv *mlme = &a->mlmepriv; + struct sta_info *sta; + u8 *mac; + int err; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE && - check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - clnt_sa_query_timeout(padapter); - else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID); -} -#endif /* CONFIG_IEEE80211W */ + if (mlme->wpa_phase == _TRUE) + mlme->wpa_phase = _FALSE; -#ifdef CONFIG_AUTO_AP_MODE -void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos) -{ - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_info *psta = precv_frame->u.hdr.psta; - struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; + mac = (u8*)a->mlmeextpriv.mlmext_info.network.MacAddress; + sta = rtw_get_stainfo(&a->stapriv, mac); + if (!sta) { + RTW_ERR(FUNC_ADPT_FMT ": drv sta_info(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(a), MAC_ARG(mac)); + return -1; + } - RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto)); + if (join_res < 0) { + err = rtw_hw_connect_abort(a, sta); + return err; + } - if (psta && psta->isrc && psta->pid > 0) { - u16 rx_pid; +#ifdef CONFIG_ARP_KEEP_ALIVE + mlme->bGetGateway = 1; + mlme->GetGatewayTryCnt = 0; +#endif - rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN); + sta->phl_sta->wmode = a->mlmeextpriv.cur_wireless_mode; + err = rtw_hw_connected(a, sta); +#ifndef CONFIG_STA_CMD_DISPR /* Run in MSG_EVT_CONNECT_END@PHL_FG_MDL_CONNECT */ + rtw_xmit_queue_clear(sta); +#endif /* CONFIG_STA_CMD_DISPR */ - RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", - rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid); + return err; +} - if (rx_pid == psta->pid) { - int i; - u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2); - /* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */ +/* currently only adhoc mode will go here */ +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 join_type; - /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ - RTW_INFO("eth, RC: len=0x%x\n", len); + RTW_INFO("%s\n", __FUNCTION__); - for (i = 0; i < len; i++) - RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i)); - /* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */ + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */ + /* nothing to do */ + } else { /* adhoc client */ - RTW_INFO("eth, RC-end\n"); + /* start beacon */ + if (send_beacon(padapter) == _FAIL) + rtw_warn_on(1); + + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; } - } -} + join_type = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + } -void rtw_start_auto_ap(_adapter *adapter) -{ - RTW_INFO("%s\n", __FUNCTION__); + /* update adhoc sta_info */ + update_sta_info(padapter, psta); - rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode, 0); + update_sta_ra_info(padapter, psta); - rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK); + /* ToDo: HT for Ad-hoc */ + psta->phl_sta->wmode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->chandef.chan); } -static int rtw_auto_ap_start_beacon(_adapter *adapter) +void mlmeext_sta_del_event_callback(_adapter *padapter) { - int ret = 0; - u8 *pbuf = NULL; - uint len; - u8 supportRate[16]; - int sz = 0, rateLen; - u8 *ie; - u8 wireless_mode, oper_channel; - u8 ssid[3] = {0}; /* hidden ssid */ - u32 ssid_len = sizeof(ssid); - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; + if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) + rtw_mlmeext_disconnect(padapter); +} +/**************************************************************************** - len = 128; - pbuf = rtw_zmalloc(len); - if (!pbuf) - return -ENOMEM; +Following are the functions for the timer handlers +*****************************************************************************/ +void _linked_info_dump(_adapter *padapter) +{ + if (padapter->bLinkInfoDump) { + rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); + /*rtw_hal_set_phydm_var(padapter, HAL_PHYDM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);*/ + } +} +/******************************************************************** - /* generate beacon */ - ie = pbuf; +When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds, +recipient station will teardown the block ack by issuing DELBA frame. - /* timestamp will be inserted by hardware */ - sz += 8; - ie += sz; +*********************************************************************/ +void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) +{ + int i = 0; + int ret = _SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* beacon interval : 2bytes */ - *(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */ - sz += 2; - ie += 2; + /* + IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300). + AP is originator.AP does not transmit unicast packets when STA response its BAR. + This case probably occur ap issue BAR after AP builds BA. - /* capability info */ - *(u16 *)ie = 0; - *(u16 *)ie |= cpu_to_le16(cap_ESS); - *(u16 *)ie |= cpu_to_le16(cap_ShortPremble); - /* *(u16*)ie |= cpu_to_le16(cap_Privacy); */ - sz += 2; - ie += 2; + Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup. + The inactivity timer is not reset when MPDUs corresponding to other TIDs are received. + */ + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) { + for (i = 0; i < TID_NUM ; i++) { + if ((psta->recvreorder_ctrl[i].enable) && + (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) { + if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { + /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ + if (!from_timer) + ret = issue_del_ba_ex(padapter, psta->phl_sta->mac_addr, i, 39, 0, 3, 1); + else + issue_del_ba(padapter, psta->phl_sta->mac_addr, i, 39, 0); + psta->recvreorder_ctrl[i].enable = _FALSE; + if (ret != _FAIL) + psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; + rtw_reset_continual_no_rx_packet(psta, i); + } + } else { + /* The inactivity timer is reset when MPDUs to the TID is received. */ + rtw_reset_continual_no_rx_packet(psta, i); + } + } + } +} - /* SSID */ - ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz); +u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) +{ + u8 ret = _FALSE; +#ifdef DBG_EXPIRATION_CHK + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* supported rates */ - wireless_mode = (WIRELESS_11BG_24N & padapter->registrypriv.wireless_mode); - rtw_set_supported_rate(supportRate, wireless_mode); - rateLen = rtw_get_rateset_len(supportRate); - if (rateLen > 8) - ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz); - else - ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz); + RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" + /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ + ", retry:%u\n" + , FUNC_ADPT_ARG(padapter) + , STA_RX_PKTS_DIFF_ARG(psta) + , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts + , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts + /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts + , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts + , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts + , pmlmeinfo->bcn_interval*/ + , pmlmeext->retry + ); + RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) + , sta_tx_pkts(psta) + , pmlmeinfo->link_count + ); +#endif - /* DS parameter set */ - if (rtw_mi_check_status(adapter, MI_LINKED)) - oper_channel = rtw_mi_get_union_chan(adapter); + if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta) + ) + ret = _FALSE; else - oper_channel = adapter_to_dvobj(adapter)->oper_channel; - - ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz); + ret = _TRUE; - /* ext supported rates */ - if (rateLen > 8) - ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz); + sta_update_last_rx_pkts(psta); - RTW_INFO("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz); + return ret; +} - /* lunch ap mode & start to issue beacon */ - if (rtw_check_beacon_data(adapter, pbuf, sz) == _SUCCESS) { +u8 chk_adhoc_peer_is_alive(struct sta_info *psta) +{ + u8 ret = _TRUE; - } else - ret = -EINVAL; +#ifdef DBG_EXPIRATION_CHK + RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" + /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ + ", expire_to:%u\n" + , MAC_ARG(psta->phl_sta->mac_addr) + , 0 /* TODO: psta->phl_sta->hal_sta->rssi_stat.rssi */ + , STA_RX_PKTS_DIFF_ARG(psta) + , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts + , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts + /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts + , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts + , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts + , pmlmeinfo->bcn_interval*/ + , psta->expire_to + ); +#endif + if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)) + ret = _FALSE; - rtw_mfree(pbuf, len); + sta_update_last_rx_pkts(psta); return ret; - } -#endif/* CONFIG_AUTO_AP_MODE */ -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT -u8 tx_control_hdl(_adapter *adapter) +#ifdef CONFIG_TDLS +u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta) { - u8 val; - - if(ATOMIC_READ(&adapter->tbtx_tx_pause)) - val = 0xff; - else - val = 0x00; - - rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &val); + if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts) + && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts)) + return _FALSE; - return H2C_SUCCESS; + return _TRUE; } -#endif -#ifdef CONFIG_AP_MODE -u8 stop_ap_hdl(_adapter *adapter) +void linked_status_chk_tdls(_adapter *padapter) { - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + struct candidate_pool { + struct sta_info *psta; + u8 addr[ETH_ALEN]; + }; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 ack_chk; + struct sta_info *psta; + int i, num_teardown = 0, num_checkalive = 0; + _list *plist, *phead; + struct tdls_txmgmt txmgmt; + struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM]; + struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM]; + u8 tdls_sta_max = _FALSE; - rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); - rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); +#define ALIVE_MIN 2 +#define ALIVE_MAX 5 - return H2C_SUCCESS; -} -#endif + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + _rtw_memset(checkalive, 0x00, sizeof(checkalive)); + _rtw_memset(teardown, 0x00, sizeof(teardown)); -u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) -{ - u8 type; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; + if ((padapter->tdlsinfo.link_established == _TRUE)) { + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); - if (psetop->mode == Ndis802_11APMode - || psetop->mode == Ndis802_11_mesh - ) { - pmlmeinfo->state = WIFI_FW_AP_STATE; - type = _HW_STATE_AP_; - } else if (psetop->mode == Ndis802_11Infrastructure) { - pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */ - pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */ - type = _HW_STATE_STATION_; - } else if (psetop->mode == Ndis802_11IBSS) - type = _HW_STATE_ADHOC_; - else if (psetop->mode == Ndis802_11Monitor) - type = _HW_STATE_MONITOR_; - else - type = _HW_STATE_NOLINK_; + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); -#ifdef CONFIG_AP_PORT_SWAP - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type)); -#endif + if (psta->tdls_sta_state & TDLS_LINKED_STATE) { + psta->alive_count++; + if (psta->alive_count >= ALIVE_MIN) { + if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) { + if (psta->alive_count < ALIVE_MAX) { + _rtw_memcpy(checkalive[num_checkalive].addr, psta->phl_sta->mac_addr, ETH_ALEN); + checkalive[num_checkalive].psta = psta; + num_checkalive++; + } else { + _rtw_memcpy(teardown[num_teardown].addr, psta->phl_sta->mac_addr, ETH_ALEN); + teardown[num_teardown].psta = psta; + num_teardown++; + } + } else + psta->alive_count = 0; + } + psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts; + psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts; - rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); + if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) { + tdls_sta_max = _TRUE; + break; + } + } + } -#ifdef CONFIG_AUTO_AP_MODE - if (psetop->mode == Ndis802_11APMode) - rtw_auto_ap_start_beacon(padapter); -#endif + if (tdls_sta_max == _TRUE) + break; + } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); - if (rtw_port_switch_chk(padapter) == _TRUE) { - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + if (num_checkalive > 0) { + for (i = 0; i < num_checkalive; i++) { + _rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN); + issue_tdls_dis_req(padapter, &txmgmt); + issue_tdls_dis_req(padapter, &txmgmt); + issue_tdls_dis_req(padapter, &txmgmt); + } + } - if (psetop->mode == Ndis802_11APMode) - adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */ - else if (psetop->mode == Ndis802_11Infrastructure) { -#ifdef CONFIG_LPS - _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); - if (port0_iface) - rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY); -#endif + if (num_teardown > 0) { + for (i = 0; i < num_teardown; i++) { + RTW_INFO("[%s %d] Send teardown to "MAC_FMT"\n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr)); + txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; + _rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN); + issue_tdls_teardown(padapter, &txmgmt, _FALSE); + } } } -#ifdef CONFIG_BT_COEXIST - if (psetop->mode == Ndis802_11APMode - || psetop->mode == Ndis802_11_mesh - || psetop->mode == Ndis802_11Monitor - ) { - /* Do this after port switch to */ - /* prevent from downloading rsvd page to wrong port */ - rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */ - } -#endif /* CONFIG_BT_COEXIST */ +} +#endif /* CONFIG_TDLS */ - return H2C_SUCCESS; +inline int rtw_get_rx_chk_limit(_adapter *adapter) +{ + return adapter->stapriv.rx_chk_limit; +} +inline void rtw_set_rx_chk_limit(_adapter *adapter, int limit) +{ + adapter->stapriv.rx_chk_limit = limit; } -u8 createbss_hdl(_adapter *padapter, u8 *pbuf) +/* from_timer == 1 means driver is in LPS */ +void linked_status_chk(_adapter *padapter, u8 from_timer) { -#ifdef CONFIG_AP_MODE + u32 i; + struct sta_info *psta; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); - WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; - struct createbss_parm *parm = (struct createbss_parm *)pbuf; - u8 ret = H2C_SUCCESS; - /* u8 initialgain; */ - - if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE) - || parm->req_ch != 0 - ) { - start_bss_network(padapter, parm); - goto exit; - } + struct sta_priv *pstapriv = &padapter->stapriv; +#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING) + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif +#ifdef CONFIG_LAYER2_ROAMING + struct recv_info *precvinfo = &padapter->recvinfo; +#endif - /* below is for ad-hoc master */ - if (parm->adhoc) { - rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS); - rtw_joinbss_reset(padapter); +#ifdef CONFIG_RTW_WDS + rtw_wds_gptr_expire(padapter); +#endif + bool is_p2p_gc = _FALSE; - pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - pmlmeinfo->ERP_enable = 0; - pmlmeinfo->WMM_enable = 0; - pmlmeinfo->HT_enable = 0; - pmlmeinfo->HT_caps_enable = 0; - pmlmeinfo->HT_info_enable = 0; - pmlmeinfo->agg_enable_bitmap = 0; - pmlmeinfo->candidate_tid_bitmap = 0; + if (padapter->registrypriv.mp_mode == _TRUE) + return; - /* cancel link timer */ - _cancel_timer_ex(&pmlmeext->link_timer); + if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) + return; - /* clear CAM */ - flush_all_cam_entry(padapter); + if (is_client_associated_to_ap(padapter)) { + /* linked infrastructure client mode */ - pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); - _rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); - pnetwork->IELength = pdev_network->IELength; + int tx_chk = _SUCCESS, rx_chk = _SUCCESS; + int rx_chk_limit; + int link_count_limit; - if (pnetwork->IELength > MAX_IE_SZ) { - ret = H2C_PARAMETERS_ERROR; - goto ibss_post_hdl; +#if defined(CONFIG_LAYER2_ROAMING) + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { + RTW_INFO("signal_strength_data.avg_val = %d\n", precvinfo->signal_strength_data.avg_val); + if ((precvinfo->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) + && (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) { +#ifdef CONFIG_RTW_80211K + rtw_roam_nb_discover(padapter, _FALSE); +#endif + pmlmepriv->need_to_roam = _TRUE; + rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); + pmlmepriv->last_roaming = rtw_get_current_time(); + } else + pmlmepriv->need_to_roam = _FALSE; } +#endif + rx_chk_limit = rtw_get_rx_chk_limit(padapter); - _rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength); - start_create_ibss(padapter); - } else { - rtw_warn_on(1); - ret = H2C_PARAMETERS_ERROR; - } - -ibss_post_hdl: - rtw_create_ibss_post_hdl(padapter, ret); - -exit: - return ret; -#else - return H2C_SUCCESS; -#endif /* CONFIG_AP_MODE */ -} +#ifdef CONFIG_ARP_KEEP_ALIVE + if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) { + RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt); + pmlmepriv->GetGatewayTryCnt++; + if (rtw_gw_addr_query(padapter) == 0) + pmlmepriv->bGetGateway = 0; + else { + _rtw_memset(pmlmepriv->gw_ip, 0, 4); + _rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN); + } + } +#endif +#ifdef CONFIG_P2P + is_p2p_gc = rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_CLIENT); + if (is_p2p_gc) { + if (!from_timer) + link_count_limit = 3; /* 8 sec */ + else + link_count_limit = 15; /* 32 sec */ + } else +#endif /* CONFIG_P2P */ + { + if (!from_timer) + link_count_limit = 7; /* 16 sec */ + else + link_count_limit = 29; /* 60 sec */ + } -u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) -{ - u8 join_type; - PNDIS_802_11_VARIABLE_IEs pIE; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); -#ifdef CONFIG_ANTENNA_DIVERSITY - struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; -#endif /* CONFIG_ANTENNA_DIVERSITY */ -#ifdef CONFIG_LAYER2_ROAMING - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *rnetwork = pmlmepriv->roam_network; - struct beacon_keys bcn_keys; - u32 roam_ielen; +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE) + return; +#endif /* CONFIG_TDLS_CH_SW */ + +#ifdef CONFIG_TDLS_AUTOCHECKALIVE + linked_status_chk_tdls(padapter); +#endif /* CONFIG_TDLS_AUTOCHECKALIVE */ +#endif /* CONFIG_TDLS */ + + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (psta != NULL) { +#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC + /*issue delba when ap does not tx data packet that is Broadcom ap */ + rtw_delba_check(padapter, psta, from_timer); #endif - u32 i; - /* u8 initialgain; */ - /* u32 acparm; */ - u8 u_ch, u_bw, u_offset; - u8 doiqk = _FALSE; + if (chk_ap_is_alive(padapter, psta) == _FALSE) + rx_chk = _FAIL; - /* check already connecting to AP or not */ - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { - if (pmlmeinfo->state & WIFI_FW_STATION_STATE) - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); - pmlmeinfo->state = WIFI_FW_NULL_STATE; + if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta)) + tx_chk = _FAIL; - /* clear CAM */ - flush_all_cam_entry(padapter); +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) + ) { + u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; + u8 union_ch = 0, union_bw = 0, union_offset = 0; + u8 switch_channel_by_drv = _TRUE; - _cancel_timer_ex(&pmlmeext->link_timer); + if (switch_channel_by_drv) { + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->chandef.chan != union_ch) + goto bypass_active_keep_alive; - /* set MSR to nolink->infra. mode */ - /* Set_MSR(padapter, _HW_STATE_NOLINK_); */ - Set_MSR(padapter, _HW_STATE_STATION_); + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->chandef.chan) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw, _FALSE); + } + } + if (rx_chk != _SUCCESS) + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->phl_sta->mac_addr, 0, 0, 3, 1); - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); - if (pmlmeinfo->state & WIFI_FW_STATION_STATE) - rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED); - } + if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { + if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) + tx_chk = issue_nulldata(padapter, psta->phl_sta->mac_addr, 1, 3, 1); + else + tx_chk = issue_nulldata(padapter, psta->phl_sta->mac_addr, 0, 3, 1); + /* If tx acked, set rx_chk _SUCCESS to reset the retry count + * unless it is a P2P GC. If the P2P GO is no longer a P2P GO, + * P2P GC tx may still receive acks, but no beacon. + */ + if (tx_chk == _SUCCESS && !is_p2p_gc) + rx_chk = _SUCCESS; + } -#ifdef CONFIG_ANTENNA_DIVERSITY - rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE); -#endif + /* back to the original operation channel */ + if (backup_ch > 0 && switch_channel_by_drv) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw, _FALSE); -#ifdef CONFIG_WAPI_SUPPORT - rtw_wapi_clear_all_cam_entry(padapter); +bypass_active_keep_alive: + ; + } else +#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + { + if (rx_chk != _SUCCESS) { + if (pmlmeext->retry == 0) { +#ifdef DBG_EXPIRATION_CHK + RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); #endif + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + } + } - rtw_joinbss_reset(padapter); + if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) { + #ifdef DBG_EXPIRATION_CHK + RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0); + #endif + if (from_timer || rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) + tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0); + else + tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1); + } + } - pmlmeinfo->ERP_enable = 0; - pmlmeinfo->WMM_enable = 0; - pmlmeinfo->HT_enable = 0; - pmlmeinfo->HT_caps_enable = 0; - pmlmeinfo->HT_info_enable = 0; - pmlmeinfo->agg_enable_bitmap = 0; - pmlmeinfo->candidate_tid_bitmap = 0; - pmlmeinfo->bwmode_updated = _FALSE; - /* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */ - pmlmeinfo->VHT_enable = 0; -#ifdef ROKU_PRIVATE - pmlmeinfo->ht_vht_received = 0; - _rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX); -#endif /* ROKU_PRIVATE */ - _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); - pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; + if (rx_chk == _FAIL) { + pmlmeext->retry++; + if (pmlmeext->retry > rx_chk_limit) { + RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n", + FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, pmlmeinfo->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + return; + } + } else + pmlmeext->retry = 0; - if (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */ - return H2C_PARAMETERS_ERROR; + if (tx_chk == _FAIL) + pmlmeinfo->link_count %= (link_count_limit + 1); + else { + psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts; + pmlmeinfo->link_count = 0; + } - if (pnetwork->IELength < 2) { - report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); - return H2C_SUCCESS; - } - _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); + } /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */ - pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); + } else if (is_client_associated_to_ibss(padapter)) { + _list *phead, *plist, dlist; - /* Check AP vendor to move rtw_joinbss_cmd() */ - /* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */ + _rtw_init_listhead(&dlist); - /* sizeof(NDIS_802_11_FIXED_IEs) */ - for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */ - if (_rtw_memcmp(pIE->data, WMM_OUI, 4)) - WMM_param_handler(padapter, pIE); - break; + for (i = 0; i < NUM_STA; i++) { -#ifdef CONFIG_80211N_HT - case _HT_CAPABILITY_IE_: /* Get HT Cap IE. */ - pmlmeinfo->HT_caps_enable = 1; - break; + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); - case _HT_EXTRA_INFO_IE_: /* Get HT Info IE. */ - pmlmeinfo->HT_info_enable = 1; - break; -#endif /* CONFIG_80211N_HT */ + if (is_broadcast_mac_addr(psta->phl_sta->mac_addr)) + continue; -#ifdef CONFIG_80211AC_VHT - case EID_VHTCapability: /* Get VHT Cap IE. */ - pmlmeinfo->VHT_enable = 1; - break; + if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) + psta->expire_to = pstapriv->adhoc_expire_to; + else + psta->expire_to--; - case EID_VHTOperation: /* Get VHT Operation IE. */ - break; -#endif /* CONFIG_80211AC_VHT */ - default: - break; + if (psta->expire_to <= 0) { + rtw_list_delete(&psta->list); + rtw_list_insert_tail(&psta->list, &dlist); + } + } } - i += (pIE->Length + 2); - } - - rtw_bss_get_chbw(pnetwork - , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); - rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); - -#if 0 - if (padapter->registrypriv.wifi_spec) { - /* for WiFi test, follow WMM test plan spec */ - acparm = 0x002F431C; /* VO */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); - acparm = 0x005E541C; /* VI */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); - acparm = 0x0000A525; /* BE */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); - acparm = 0x0000A549; /* BK */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); - - /* for WiFi test, mixed mode with intel STA under bg mode throughput issue */ - if (padapter->mlmepriv.htpriv.ht_option == _FALSE) { - acparm = 0x00004320; - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + plist = get_next(&dlist); + while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, list); + plist = get_next(plist); + rtw_list_delete(&psta->list); + RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); + report_del_sta_event(padapter, psta->phl_sta->mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); } - } else { - acparm = 0x002F3217; /* VO */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); - acparm = 0x005E4317; /* VI */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); - acparm = 0x00105320; /* BE */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); - acparm = 0x0000A444; /* BK */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); - } -#endif - - /* check channel, bandwidth, offset and switch */ - if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) { - report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); - return H2C_SUCCESS; } - /* disable dynamic functions, such as high power, DIG */ - /*rtw_phydm_func_disable_all(padapter);*/ - - /* config the initial gain under linking, need to write the BB registers */ - /* initialgain = 0x1E; */ - /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ - - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); - if (MLME_IS_STA(padapter)) - rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); - else - rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); - - join_type = 0; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - rtw_btcoex_connect_notify(padapter, join_type); +} - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT +void rtw_tbtx_xmit_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + if (ATOMIC_READ(&padapter->tbtx_remove_tx_pause) == _TRUE){ + ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE); + rtw_tx_control_cmd(padapter); + }else { + rtw_issue_action_token_rel(padapter); + ATOMIC_SET(&padapter->tbtx_tx_pause, _TRUE); + rtw_tx_control_cmd(padapter); + _set_timer(&pmlmeext->tbtx_xmit_timer, MAX_TXPAUSE_DURATION); + ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _TRUE); + } +} - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); +#ifdef CONFIG_AP_MODE +void rtw_tbtx_token_dispatch_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + _irqL irqL; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + _list *phead, *plist; + int i, found = _FALSE; + u8 nr_send, th_idx = 0; - /* cancel link timer */ - _cancel_timer_ex(&pmlmeext->link_timer); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock, &irqL); + RTW_DBG("%s:asoc_cnt: %d\n",__func__, pstapriv->tbtx_asoc_list_cnt); - start_clnt_join(padapter); + // check number of TBTX sta + if (padapter->stapriv.tbtx_asoc_list_cnt < 2) + goto exit; -#ifdef CONFIG_LAYER2_ROAMING - rtw_msleep_os(2); - if (rnetwork && (pmlmeinfo->state & (WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE))) { - struct beacon_keys bcn_keys; - u32 roam_ielen; + // dispatch token + + nr_send = RTW_DIV_ROUND_UP(pstapriv->tbtx_asoc_list_cnt, NR_TBTX_SLOT); - if (!rnetwork) { - RTW_INFO("%s: pmlmepriv->roam_network is NULL. roaming fail!!\n", __func__); - return H2C_SUCCESS; + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + /* psta is supporting TBTX */ + if ((!psta) || (!psta->tbtx_enable)) + RTW_DBG("sta tbtx_enable is false\n"); + else { + for (i = 0; i < nr_send; i++) { + if (pstapriv->last_token_holder == psta) { + found = _TRUE; + goto outof_loop; + } + } } - roam_ielen = rnetwork->network.IELength; - update_network(&(pmlmepriv->cur_network.network), &(rnetwork->network), padapter, _TRUE); - - /* update bcn keys */ - if (rtw_get_bcn_keys_from_bss(&rnetwork->network, &bcn_keys) == _TRUE) { - _rtw_memcpy(&pmlmepriv->cur_beacon_keys, &bcn_keys, sizeof(bcn_keys)); - if (is_hidden_ssid(bcn_keys.ssid, bcn_keys.ssid_len)) { - _rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE); - pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength; + plist = get_next(plist); + } +outof_loop: + + RTW_DBG("rtw_tbtx_token_dispatch_timer_hdl() th_idx=%d, nr_send=%d, phead=%p, plist=%p, found=%d\n ", th_idx , nr_send, phead, plist, found); + if (!found) { + plist = get_next(phead); + while(rtw_end_of_queue_search(phead, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + if ((!psta) || (!psta->tbtx_enable)) + RTW_DBG("sta tbtx_enable is false\n"); + else { + pstapriv->token_holder[th_idx] = psta; + rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]); + break; } - } else { - RTW_ERR("%s: get beacon keys failed\n", __func__); - _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(bcn_keys)); + plist = get_next(plist); + } + } + + for (i=th_idx; itbtx_enable)) + RTW_DBG("sta tbtx_enable is false\n"); + else { + pstapriv->token_holder[th_idx] = psta; + rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]); + i++; } - #ifdef CONFIG_BCN_CNT_CONFIRM_HDL - pmlmepriv->new_beacon_cnts = 0; - #endif - - /* check the vendor of the assoc AP */ - pmlmeinfo->assoc_AP_vendor = check_assoc_AP(rnetwork->network.IEs, rnetwork->network.IELength); - - /* update TSF Value */ - pmlmeext->TSFValue = rnetwork->network.tsf + rtw_get_passing_time_ms(rnetwork->last_scanned)*1000; - pmlmeext->bcn_cnt = 0; - pmlmeext->last_bcn_cnt = 0; - /* start auth */ - start_clnt_auth(padapter); } -#endif - return H2C_SUCCESS; + ATOMIC_SET(&pstapriv->nr_token_keeper, nr_send); + +exit: + // set_timer + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock, &irqL); + _set_timer(&pmlmeext->tbtx_token_dispatch_timer, TBTX_TX_DURATION); } +#endif /* CONFIG_AP_MODE */ +#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */ -u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) +void link_timer_hdl(void *ctx) { -#if CONFIG_DFS - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); -#endif - struct disconnect_parm *param = (struct disconnect_parm *)pbuf; + _adapter *padapter = (_adapter *)ctx; + /* static unsigned int rx_pkt = 0; */ + /* static u64 tx_cnt = 0; */ + /* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + /* struct sta_priv *pstapriv = &padapter->stapriv; */ +#ifdef CONFIG_RTW_80211R + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); - u8 val8; - - if (is_client_associated_to_ap(padapter) - #if CONFIG_DFS - && !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch - #endif - ) { - #ifdef CONFIG_PLATFORM_ROCKCHIPS - /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); - #else - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100); - #endif /* CONFIG_PLATFORM_ROCKCHIPS */ - } - -#ifndef CONFIG_SUPPORT_MULTI_BCN - if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - /* Stop BCN */ - val8 = 0; - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); - } #endif - rtw_sta_mstatus_report(padapter); - - rtw_mlmeext_disconnect(padapter); + if (rtw_sta_linking_test_force_fail()) + RTW_INFO("rtw_sta_linking_test_force_fail\n"); - rtw_free_uc_swdec_pending_queue(padapter); + if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) { + RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter)); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE); + goto exit; + } - return H2C_SUCCESS; -} + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { + RTW_INFO("link_timer_hdl:no beacon while connecting\n"); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE); + } else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) { -static const char *const _scan_state_str[] = { - "SCAN_DISABLE", - "SCAN_START", - "SCAN_PS_ANNC_WAIT", - "SCAN_ENTER", - "SCAN_PROCESS", - "SCAN_BACKING_OP", - "SCAN_BACK_OP", - "SCAN_LEAVING_OP", - "SCAN_LEAVE_OP", - "SCAN_SW_ANTDIV_BL", - "SCAN_TO_P2P_LISTEN", - "SCAN_P2P_LISTEN", - "SCAN_COMPLETE", - "SCAN_STATE_MAX", -}; +#ifdef CONFIG_IOCTL_CFG80211 + if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) + return; +#endif /* CONFIG_IOCTL_CFG80211 */ -const char *scan_state_str(u8 state) -{ - state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state; - return _scan_state_str[state]; -} + /* re-auth timer */ + if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) { + /* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */ + /* { */ + pmlmeinfo->state = 0; + if (pmlmeinfo->auth_status) { + report_join_res(padapter, -1, pmlmeinfo->auth_status); + pmlmeinfo->auth_status = 0; /* reset */ + } else + report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); + return; + /* } */ + /* else */ + /* { */ + /* pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */ + /* pmlmeinfo->reauth_count = 0; */ + /* } */ + } -static bool scan_abort_hdl(_adapter *adapter) -{ - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &adapter->wdinfo; + RTW_INFO("link_timer_hdl: auth timeout and try again\n"); + pmlmeinfo->auth_seq = 1; + issue_auth(padapter, NULL, 0); + set_link_timer(pmlmeext, REAUTH_TO); + } else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) { + /* re-assoc timer */ + if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { + pmlmeinfo->state = WIFI_FW_NULL_STATE; +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter)) { + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (psta) + rtw_free_stainfo(padapter, psta); + } #endif - bool ret = _FALSE; + report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE); + return; + } - if (pmlmeext->scan_abort == _TRUE) { -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); - ss->channel_idx = 3; - RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__ - , ss->channel_idx - , pwdinfo->find_phase_state_exchange_cnt - ); +#ifdef CONFIG_RTW_80211R + if (rtw_ft_roam(padapter)) { + RTW_INFO("link_timer_hdl: reassoc timeout and try again\n"); + issue_reassocreq(padapter); } else #endif { - ss->channel_idx = ss->ch_num; - RTW_INFO("%s idx:%d\n", __FUNCTION__ - , ss->channel_idx - ); + RTW_INFO("link_timer_hdl: assoc timeout and try again\n"); + issue_assocreq(padapter); } - ret = _TRUE; + + set_link_timer(pmlmeext, REASSOC_TO); } - return ret; +exit: + return; } -u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num) +void addba_timer_hdl(void *ctx) { - /* interval larger than this is treated as backgroud scan */ -#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS -#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000 -#endif + struct sta_info *psta = (struct sta_info *)ctx; -#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST -#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1 -#endif -#ifndef RTW_SCAN_SPARSE_CH_NUM_BG -#define RTW_SCAN_SPARSE_CH_NUM_BG 4 -#endif +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv; -#define SCAN_SPARSE_CH_NUM_INVALID 255 + if (!psta) + return; - static u8 token = 255; - u32 interval; - bool busy_traffic = _FALSE; - bool miracast_enabled = _FALSE; - bool bg_scan = _FALSE; - u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID; - u8 scan_division_num; - u8 ret_num = ch_num; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + phtpriv = &psta->htpriv; - if (mlmeext->last_scan_time == 0) - mlmeext->last_scan_time = rtw_get_current_time(); + if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { + if (phtpriv->candidate_tid_bitmap) + phtpriv->candidate_tid_bitmap = 0x0; - interval = rtw_get_passing_time_ms(mlmeext->last_scan_time); + } +#endif /* CONFIG_80211N_HT */ +} +#ifdef CONFIG_IEEE80211W +void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct sta_info *psta; + int mac_id; + struct stadel_event *pdel_sta_evt; + struct rtw_evt_header *evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; - if (rtw_mi_busy_traffic_check(adapter)) - busy_traffic = _TRUE; + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + pcmd_obj->padapter = padapter; - if (rtw_mi_check_miracast_enabled(adapter)) - miracast_enabled = _TRUE; + cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } - if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS) - bg_scan = _TRUE; + _rtw_init_listhead(&pcmd_obj->list); - /* max_allow_ch by conditions*/ + pcmd_obj->cmdcode = CMD_SET_MLME_EVT; + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; -#if RTW_SCAN_SPARSE_MIRACAST - if (miracast_enabled == _TRUE && busy_traffic == _TRUE) - max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST); -#endif + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; -#if RTW_SCAN_SPARSE_BG - if (bg_scan == _TRUE) - max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG); -#endif + evt_hdr = (struct rtw_evt_header *)(pevtcmd); + evt_hdr->len = sizeof(struct stadel_event); + evt_hdr->id = EVT_TIMEOUT_STA; + evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); - if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) { - int i; - int k = 0; + pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header)); + _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); + _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); - scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0); - token = (token + 1) % scan_division_num; - if (0) - RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token); + psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); + if (psta) + mac_id = (int)psta->phl_sta->macid; + else + mac_id = (-1); - for (i = 0; i < ch_num; i++) { - if (ch[i].hw_value && (i % scan_division_num) == token - ) { - if (i != k) - _rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel)); - k++; - } - } + pdel_sta_evt->mac_id = mac_id; - _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + RTW_INFO("report_del_sta_event: delete STA, mac_id=%d\n", mac_id); - ret_num = k; - mlmeext->last_scan_time = rtw_get_current_time(); - } + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); - return ret_num; + return; } -#ifdef CONFIG_SCAN_BACKOP -u8 rtw_scan_backop_decision(_adapter *adapter) +void clnt_sa_query_timeout(_adapter *padapter) { - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct mi_state mstate; - u8 backop_flags = 0; - - rtw_mi_status(adapter, &mstate); - - if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN)) - || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL))) - backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext); - -#ifdef CONFIG_AP_MODE - if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN)) - || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL))) - backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext); -#endif - -#ifdef CONFIG_RTW_MESH - if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN)) - || (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL))) - backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext); -#endif + struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); - return backop_flags; + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE); } -#endif -#define SCANNING_TIMEOUT_EX 2000 -u32 rtw_scan_timeout_decision(_adapter *padapter) +void sa_query_timer_hdl(void *ctx) { - u32 back_op_times= 0; - u8 max_chan_num; - u16 scan_ms; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; + struct sta_info *psta = (struct sta_info *)ctx; + _adapter *padapter = psta->padapter; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (is_supported_5g(padapter->registrypriv.wireless_mode) - && IsSupported24G(padapter->registrypriv.wireless_mode)) - max_chan_num = MAX_CHANNEL_NUM;/* dual band */ - else - max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/ + if (MLME_IS_STA(padapter) && + check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + clnt_sa_query_timeout(padapter); + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + report_sta_timeout_event(padapter, psta->phl_sta->mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID); +} - #ifdef CONFIG_SCAN_BACKOP - if (rtw_scan_backop_decision(padapter)) - back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms; - #endif +#endif /* CONFIG_IEEE80211W */ - if (ss->duration) - scan_ms = ss->duration; - else - #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) - if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) - scan_ms = rtw_acs_get_adv_st(padapter); - else - #endif /*CONFIG_RTW_ACS*/ - scan_ms = ss->scan_ch_ms; - - ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX; - #ifdef DBG_SITESURVEY - RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms); - #endif /*DBG_SITESURVEY*/ - return ss->scan_timeout_ms; +#ifdef ROKU_PRIVATE +void find_remote_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + rtw_find_remote_wk_cmd(padapter); + set_find_remote_timer(pmlmeext, 1); } -static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, - u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num, bool no_sparse, int reason) +#ifdef CONFIG_P2P +void hide_ssid_hdl(void *ctx) { - int i, j; - int set_idx; - u8 chan; - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(padapter)); -#ifdef CONFIG_RTW_ROAM_QUICKSCAN - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#endif + _adapter *padapter = (_adapter *)ctx; + struct registry_priv *pregpriv = &padapter->registrypriv; - /* clear first */ - _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num); + rtw_set_bit(MIRACAST, &pregpriv->go_hidden_ssid_mode); + ATOMIC_SET(&pregpriv->set_hide_ssid_timer, 0); -#ifdef CONFIG_RTW_ROAM_QUICKSCAN - if ((reason == RTW_AUTO_SCAN_REASON_ROAM) && (pmlmeext->quickscan_next)) { - pmlmeext->quickscan_next = _FALSE; - _rtw_memcpy(out, pmlmeext->roam_ch, sizeof(struct rtw_ieee80211_channel)*RTW_CHANNEL_SCAN_AMOUNT); - return pmlmeext->roam_ch_num; - } + /* check if there is other feature show SSID in beacon */ + if (pregpriv->go_hidden_ssid_mode == ALL_HIDE_SSID) + rtw_hide_ssid_wk_cmd(padapter); +} +#endif #endif - /* acquire channels from in */ - j = 0; - for (i = 0; i < in_num; i++) { - - if (0) - RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i])); - - if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED)) - continue; - if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE) - continue; - - set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value); - if (set_idx >= 0) { - if (j >= out_num) { - RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", - FUNC_ADPT_ARG(padapter), out_num); - break; - } - - _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); - - if (rfctl->channel_set[set_idx].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS)) - out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; +#ifdef CONFIG_AUTO_AP_MODE +void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; - j++; - } - if (j >= out_num) - break; - } + RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto)); - /* if out is empty, use channel_set as default */ - if (j == 0) { - for (i = 0; i < rfctl->max_chan_nums; i++) { - chan = rfctl->channel_set[i].ChannelNum; - if (rtw_mlme_band_check(padapter, chan) == _TRUE) { - if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE) - continue; + if (psta && psta->isrc && psta->pid > 0) { + u16 rx_pid; - if (0) - RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan); + rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN); - if (j >= out_num) { - RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", - FUNC_ADPT_ARG(padapter), out_num); - break; - } + RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", + rx_pid, MAC_ARG(psta->phl_sta->mac_addr), psta->pid); - out[j].hw_value = chan; + if (rx_pid == psta->pid) { + int i; + u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2); + /* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */ - if (rfctl->channel_set[i].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS)) - out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ + RTW_INFO("eth, RC: len=0x%x\n", len); - j++; - } - } - } + for (i = 0; i < len; i++) + RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i)); + /* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */ - if (!no_sparse - && !regsty->wifi_spec - && j > 6 /* assume ch_num > 6 is normal scan */ - ) { - /* scan_sparse */ - j = rtw_scan_sparse(padapter, out, j); + RTW_INFO("eth, RC-end\n"); + } } - return j; } -static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) +void rtw_start_auto_ap(_adapter *adapter) { - struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; - RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); - int i, reason = 0; - - ss->bss_cnt = 0; - ss->activate_ch_cnt = 0; - ss->channel_idx = 0; - ss->force_ssid_scan = 0; - ss->igi_scan = 0; - ss->igi_before_scan = 0; -#ifdef CONFIG_SCAN_BACKOP - ss->scan_cnt = 0; -#endif -#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) - ss->is_sw_antdiv_bl_scan = 0; -#endif - ss->ssid_num = 0; - for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { - if (parm->ssid[i].SsidLength) { - _rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); - ss->ssid[i].SsidLength = parm->ssid[i].SsidLength; - ss->ssid_num++; - } else - ss->ssid[i].SsidLength = 0; - } - reason = parm->reason; - ss->ch_num = rtw_scan_ch_decision(adapter - , ss->ch, RTW_CHANNEL_SCAN_AMOUNT - , parm->ch, parm->ch_num - , parm->acs - , reason - ); - - for (i = 0; i < MAX_CHANNEL_NUM; i++) - chset[i].hidden_bss_cnt = 0; - - ss->bw = parm->bw; - ss->igi = parm->igi; - ss->token = parm->token; - ss->duration = parm->duration; - ss->scan_mode = parm->scan_mode; - ss->token = parm->token; - ss->acs = parm->acs; + RTW_INFO("%s\n", __FUNCTION__); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode, 0); + + rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK); } -static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type) +static int rtw_auto_ap_start_beacon(_adapter *adapter) { - u8 next_state; - u8 scan_ch = 0; - RT_SCAN_TYPE scan_type = SCAN_PASSIVE; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - int ch_set_idx; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#endif -#ifdef CONFIG_SCAN_BACKOP - u8 backop_flags = 0; -#endif + int ret = 0; + u8 *pbuf = NULL; + uint len; + u8 supportRate[16]; + int sz = 0, rateLen; + u8 *ie; + u8 wireless_mode, oper_channel; + u8 ssid[3] = {0}; /* hidden ssid */ + u32 ssid_len = sizeof(ssid); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - /* handle scan abort request */ - scan_abort_hdl(padapter); + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; -#ifdef CONFIG_P2P - if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) { - if (pwdinfo->rx_invitereq_info.scan_op_ch_only) - scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx]; - else - scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx]; - scan_type = SCAN_ACTIVE; - } else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) { - /* - * Commented by Albert 2011/06/03 - * The driver is in the find phase, it should go through the social channel. - */ - scan_ch = pwdinfo->social_chan[ss->channel_idx]; - ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch); - if (ch_set_idx >= 0) - scan_type = rfctl->channel_set[ch_set_idx].flags & RTW_CHF_NO_IR ? SCAN_PASSIVE : SCAN_ACTIVE; - else - scan_type = SCAN_ACTIVE; - } else -#endif /* CONFIG_P2P */ - { - struct rtw_ieee80211_channel *ch; - #ifdef CONFIG_SCAN_BACKOP - backop_flags = rtw_scan_backop_decision(padapter); - #endif + len = 128; + pbuf = rtw_zmalloc(len); + if (!pbuf) + return -ENOMEM; - #ifdef CONFIG_SCAN_BACKOP - if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max)) - #endif - { - #ifdef CONFIG_RTW_WIFI_HAL - if (adapter_to_dvobj(padapter)->nodfs) { - while (ss->channel_idx < ss->ch_num && rtw_chset_is_dfs_ch(rfctl->channel_set, ss->ch[ss->channel_idx].hw_value)) - ss->channel_idx++; - } else - #endif - if (ss->channel_idx != 0 && ss->force_ssid_scan == 0 - && pmlmeext->sitesurvey_res.ssid_num - && (ss->ch[ss->channel_idx - 1].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) - ) { - ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value); - if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt - && (!IS_DFS_SLAVE_WITH_RD(rfctl) - || rtw_rfctl_dfs_domain_unknown(rfctl) - || !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])) - ) { - ss->channel_idx--; - ss->force_ssid_scan = 1; - } - } else - ss->force_ssid_scan = 0; - } - if (ss->channel_idx < ss->ch_num) { - ch = &ss->ch[ss->channel_idx]; - scan_ch = ch->hw_value; + /* generate beacon */ + ie = pbuf; - #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) - if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter)) - scan_type = SCAN_PASSIVE; - else - #endif /*CONFIG_RTW_ACS*/ - scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; - } - } + /* timestamp will be inserted by hardware */ + sz += 8; + ie += sz; - if (scan_ch != 0) { - next_state = SCAN_PROCESS; + /* beacon interval : 2bytes */ + *(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */ + sz += 2; + ie += 2; - #ifdef CONFIG_SCAN_BACKOP - if (backop_flags) { - if (ss->scan_cnt < ss->scan_cnt_max) - ss->scan_cnt++; - else { - mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags); - next_state = SCAN_BACKING_OP; - } - } - #endif + /* capability info */ + *(u16 *)ie = 0; + *(u16 *)ie |= cpu_to_le16(cap_ESS); + *(u16 *)ie |= cpu_to_le16(cap_ShortPremble); + /* *(u16*)ie |= cpu_to_le16(cap_Privacy); */ + sz += 2; + ie += 2; - } else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) { - /* go p2p listen */ - next_state = SCAN_TO_P2P_LISTEN; + /* SSID */ + ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz); -#ifdef CONFIG_ANTENNA_DIVERSITY - } else if (rtw_hal_antdiv_before_linked(padapter)) { - /* go sw antdiv before link */ - next_state = SCAN_SW_ANTDIV_BL; -#endif - } else { - next_state = SCAN_COMPLETE; + /* Get OP ch */ + if (rtw_mi_check_status(adapter, MI_LINKED)) + oper_channel = rtw_mi_get_union_chan(adapter); + else + oper_channel = adapter_to_dvobj(adapter)->chandef.chan; -#if defined(DBG_SCAN_SW_ANTDIV_BL) - { - /* for SCAN_SW_ANTDIV_BL state testing */ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - int i; - bool is_linked = _FALSE; + /* supported rates */ + wireless_mode = (WIRELESS_11BG_24N & adapter->registrypriv.wireless_mode); + rtw_set_supported_rate(supportRate, wireless_mode, oper_channel); + rateLen = rtw_get_rateset_len(supportRate); + if (rateLen > 8) + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz); + else + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz); - for (i = 0; i < dvobj->iface_nums; i++) { - if (rtw_linked_check(dvobj->padapters[i])) - is_linked = _TRUE; - } + /* DS parameter set */ + ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz); - if (!is_linked) { - static bool fake_sw_antdiv_bl_state = 0; + /* ext supported rates */ + if (rateLen > 8) + ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz); - if (fake_sw_antdiv_bl_state == 0) { - next_state = SCAN_SW_ANTDIV_BL; - fake_sw_antdiv_bl_state = 1; - } else - fake_sw_antdiv_bl_state = 0; - } - } -#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */ - } + RTW_INFO("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz); -#ifdef CONFIG_SCAN_BACKOP - if (next_state != SCAN_PROCESS) - ss->scan_cnt = 0; -#endif + /* lunch ap mode & start to issue beacon */ + if (rtw_check_beacon_data(adapter, pbuf, sz) == _SUCCESS) { + } else + ret = -EINVAL; -#ifdef DBG_FIXED_CHAN - if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS) - scan_ch = pmlmeext->fixed_chan; -#endif - if (ch) - *ch = scan_ch; - if (type) - *type = scan_type; + rtw_mfree(pbuf, len); + + return ret; - return next_state; } +#endif/* CONFIG_AUTO_AP_MODE */ -void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT +u8 tx_control_hdl(_adapter *adapter) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; - u8 ssid_scan = 0; - -#ifdef CONFIG_P2P -#ifndef CONFIG_IOCTL_CFG80211 - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif -#endif - - if (survey_channel != 0) { - set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - - if (ScanType == SCAN_PASSIVE && ss->force_ssid_scan) - ssid_scan = 1; - else if (ScanType == SCAN_ACTIVE) { -#ifdef CONFIG_P2P - #ifdef CONFIG_IOCTL_CFG80211 - if (rtw_cfg80211_is_p2p_scan(padapter)) - #else - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) - #endif - { - issue_probereq_p2p(padapter, NULL); - issue_probereq_p2p(padapter, NULL); - issue_probereq_p2p(padapter, NULL); - } else -#endif /* CONFIG_P2P */ - { - if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { - /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ - if (padapter->registrypriv.wifi_spec) - issue_probereq(padapter, NULL, NULL); - else - issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); - issue_probereq(padapter, NULL, NULL); - } - - ssid_scan = 1; - } - } + u8 val; - if (ssid_scan) { - int i; + if(ATOMIC_READ(&adapter->tbtx_tx_pause)) + val = 0xff; + else + val = 0x00; - for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { - if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { - /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ - if (padapter->registrypriv.wifi_spec) - issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); - else - issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); - issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); - } - } - } - } else { - /* channel number is 0 or this channel is not valid. */ - rtw_warn_on(1); - } + rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &val); - return; + return H2C_SUCCESS; } - -void survey_done_set_ch_bw(_adapter *padapter) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - u8 cur_channel = 0; - u8 cur_bwmode; - u8 cur_ch_offset; - -#ifdef CONFIG_MCC_MODE - if (!rtw_hal_mcc_change_scan_flag(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset)) { - if (0) - RTW_INFO(FUNC_ADPT_FMT" back to AP channel - ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); - goto exit; - } #endif +void rtw_disconnect_ch_switch(_adapter *adapter) +{ + u8 ch, bw, offset; + void *phl = adapter_to_dvobj(adapter)->phl; + int chanctx_num = 0; + struct rtw_chan_def chan_def = {0}; - if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) { - if (0) - RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); - } else { -#ifdef CONFIG_P2P - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface; - int i; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; + if (!(MLME_IS_STA(adapter) && MLME_IS_OPCH_SW(adapter))) { + /* channel status no need to check here for STA under OPCH_SW */ + rtw_mi_get_ch_setting_union_no_self(adapter, &ch, &bw, &offset); + RTW_INFO("Core - CH:%d, BW:%d OFF:%d\n", ch, bw, offset); -#ifdef CONFIG_IOCTL_CFG80211 - if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled) - continue; -#endif + chanctx_num = rtw_phl_chanctx_del(phl, adapter->phl_role, &chan_def); + RTW_INFO("PHL - CH:%d, BW:%d OFF:%d\n", chan_def.chan, chan_def.bw, chan_def.offset); - if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) { - cur_channel = iface->wdinfo.listen_channel; - cur_bwmode = CHANNEL_WIDTH_20; - cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - if (0) - RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset); - break; - } + if (chanctx_num && (ch != chan_def.chan)) { + RTW_WARN("%s chandef->chan != ch\n", __func__); + rtw_warn_on(1); } -#endif /* CONFIG_P2P */ - if (cur_channel == 0) { - cur_channel = pmlmeext->cur_channel; - cur_bwmode = pmlmeext->cur_bwmode; - cur_ch_offset = pmlmeext->cur_ch_offset; - if (0) - RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + if (chanctx_num && chan_def.chan != 0) { + set_channel_bwmode(adapter, chan_def.chan, chan_def.offset, chan_def.bw, _FALSE); + rtw_mi_update_union_chan_inf(adapter, chan_def.chan, chan_def.offset, chan_def.bw); } + + rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), BIT(adapter->iface_id), 0); } -#ifdef CONFIG_MCC_MODE -exit: -#endif - set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); } - -/** - * rtw_ps_annc - check and doing ps announcement for all the adapters - * @adapter: the requesting adapter - * @ps: power saving or not - * - * Returns: 0: no ps announcement is doing. 1: ps announcement is doing - */ -u8 rtw_ps_annc(_adapter *adapter, bool ps) +#ifdef CONFIG_AP_MODE +u8 stop_ap_hdl(_adapter *adapter) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - _adapter *iface; - int i; - u8 ps_anc = 0; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - if (MLME_IS_STA(iface)) { - if (is_client_associated_to_ap(iface) == _TRUE) { - /* TODO: TDLS peers */ - #ifdef CONFIG_MCC_MODE - /* for two station case */ - if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) { - u8 ch = iface->mlmeextpriv.cur_channel; - u8 offset = iface->mlmeextpriv.cur_ch_offset; - u8 bw = iface->mlmeextpriv.cur_bwmode; - - set_channel_bwmode(iface, ch, offset, bw); - } - #endif /* CONFIG_MCC_MODE */ - issue_nulldata(iface, NULL, ps, 3, 500); - ps_anc = 1; - } - #ifdef CONFIG_RTW_MESH - } else if (MLME_IS_MESH(iface)) { - if (rtw_mesh_ps_annc(iface, ps)) - ps_anc = 1; - #endif - } - } - return ps_anc; + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); +#ifdef CONFIG_AP_CMD_DISPR + rtw_free_bcn_entry(adapter); +#else + rtw_phl_ap_stop(adapter_to_dvobj(adapter)->phl, adapter->phl_role); +#endif + rtw_disconnect_ch_switch(adapter); + return H2C_SUCCESS; } +#endif -void rtw_leave_opch(_adapter *adapter) +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) - return; -#endif + u8 type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; - _enter_critical_mutex(&rfctl->offch_mutex, NULL); + if (psetop->mode == Ndis802_11APMode + || psetop->mode == Ndis802_11_mesh + ) { + pmlmeinfo->state = WIFI_FW_AP_STATE; + type = _HW_STATE_AP_; + } else if (psetop->mode == Ndis802_11Infrastructure) { + pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */ + pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */ + type = _HW_STATE_STATION_; + } else if (psetop->mode == Ndis802_11IBSS) + type = _HW_STATE_ADHOC_; + else if (psetop->mode == Ndis802_11Monitor) + type = _HW_STATE_MONITOR_; + else + type = _HW_STATE_NOLINK_; - if (rfctl->offch_state == OFFCHS_NONE) { - /* prepare to leave operating channel */ - rfctl->offch_state = OFFCHS_LEAVING_OP; + if (_FAIL == rtw_hw_iface_type_change(padapter, type)) { + RTW_ERR("%s - change iface type fails !\n", __func__); + return H2C_CMD_FAIL; + } - /* clear HW TX queue */ - rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0); +#ifdef CONFIG_AP_PORT_SWAP + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type)); +#endif - rtw_hal_macid_sleep_all_used(adapter); + rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); - rtw_ps_annc(adapter, 1); +#ifdef CONFIG_AUTO_AP_MODE + if (psetop->mode == Ndis802_11APMode) + rtw_auto_ap_start_beacon(padapter); +#endif - rfctl->offch_state = OFFCHS_LEAVE_OP; - } + return H2C_SUCCESS; - _exit_critical_mutex(&rfctl->offch_mutex, NULL); } -void rtw_back_opch(_adapter *adapter) +u8 createbss_hdl(_adapter *padapter, u8 *pbuf) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; + struct createbss_parm *parm = (struct createbss_parm *)pbuf; + u8 ret = H2C_SUCCESS; + /* u8 initialgain; */ -#ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) - return; +#ifdef CONFIG_AP_MODE + if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE) + || parm->req_ch != 0 + ) { + start_bss_network(padapter, parm); + rtw_core_ap_swch_start(padapter, parm); + rtw_core_ap_start(padapter, parm); + goto exit; + } #endif - _enter_critical_mutex(&rfctl->offch_mutex, NULL); - - if (rfctl->offch_state != OFFCHS_NONE) { - rfctl->offch_state = OFFCHS_BACKING_OP; - rtw_hal_macid_wakeup_all_used(adapter); - rtw_ps_annc(adapter, 0); - - rfctl->offch_state = OFFCHS_NONE; - rtw_mi_os_xmit_schedule(adapter); - } + /* below is for ad-hoc master */ + if (parm->adhoc) { + rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS); + rtw_joinbss_reset(padapter); - _exit_critical_mutex(&rfctl->offch_mutex, NULL); -} + pmlmeext->chandef.bw = CHANNEL_WIDTH_20; + pmlmeext->chandef.offset = CHAN_OFFSET_NO_EXT; + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; -void sitesurvey_set_igi(_adapter *adapter) -{ - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct ss_res *ss = &mlmeext->sitesurvey_res; - u8 igi; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &adapter->wdinfo; -#endif + /* cancel link timer */ + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ - switch (mlmeext_scan_state(mlmeext)) { - case SCAN_ENTER: - #ifdef CONFIG_P2P - #ifdef CONFIG_IOCTL_CFG80211 - if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter)) - igi = 0x30; - else - #endif /* CONFIG_IOCTL_CFG80211 */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - igi = 0x28; - else - #endif /* CONFIG_P2P */ + /* clear CAM */ + flush_all_cam_entry(padapter, PHL_CMD_DIRECTLY, 0); - if (ss->igi) - igi = ss->igi; - else - #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) - if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter)) - igi = rtw_acs_get_adv_igi(adapter); - else - #endif /*CONFIG_RTW_ACS*/ - igi = 0x1e; + pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); + _rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = pdev_network->IELength; - /* record IGI status */ - ss->igi_scan = igi; - rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL); + if (pnetwork->IELength > MAX_IE_SZ) { + ret = H2C_PARAMETERS_ERROR; + goto ibss_post_hdl; + } - /* disable DIG and set IGI for scan */ - rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); - break; - case SCAN_COMPLETE: - case SCAN_TO_P2P_LISTEN: - /* enable DIG and restore IGI */ - igi = 0xff; - rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); - break; -#ifdef CONFIG_SCAN_BACKOP - case SCAN_BACKING_OP: - /* write IGI for op channel when DIG is not enabled */ - odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan); - break; - case SCAN_LEAVE_OP: - /* write IGI for scan when DIG is not enabled */ - odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan); - break; -#endif /* CONFIG_SCAN_BACKOP */ - default: + _rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength); + start_create_ibss(padapter); + } else { rtw_warn_on(1); - break; + ret = H2C_PARAMETERS_ERROR; } -} -void sitesurvey_set_msr(_adapter *adapter, bool enter) -{ - u8 network_type; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (enter) { -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_hal_get_hwreg(adapter, HW_VAR_MEDIA_STATUS, (u8 *)(&pmlmeinfo->hw_media_state)); -#endif - /* set MSR to no link state */ - network_type = _HW_STATE_NOLINK_; - } else { -#ifdef CONFIG_MI_WITH_MBSSID_CAM - network_type = pmlmeinfo->hw_media_state; -#else - network_type = pmlmeinfo->state & 0x3; -#endif - } - Set_MSR(adapter, network_type); +ibss_post_hdl: + rtw_create_ibss_post_hdl(padapter, ret); + +exit: + return ret; } -void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state) +static void set_hw_before_join(struct _ADAPTER *a) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct mlme_ext_priv *pmlmeext = &a->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct _WLAN_BSSID_EX *pnetwork = &pmlmeinfo->network; + struct sta_info *sta; - _enter_critical_mutex(&rfctl->offch_mutex, NULL); + /* check already connecting to AP or not */ + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + if (pmlmeinfo->state & WIFI_FW_STATION_STATE) + issue_deauth_ex(a, pnetwork->MacAddress, + WLAN_REASON_DEAUTH_LEAVING, 1, 100); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ - switch (scan_state) { - case SCAN_DISABLE: - case SCAN_BACK_OP: - rfctl->offch_state = OFFCHS_NONE; - break; - case SCAN_START: - case SCAN_LEAVING_OP: - rfctl->offch_state = OFFCHS_LEAVING_OP; - break; - case SCAN_ENTER: - case SCAN_LEAVE_OP: - rfctl->offch_state = OFFCHS_LEAVE_OP; - break; - case SCAN_COMPLETE: - case SCAN_BACKING_OP: - rfctl->offch_state = OFFCHS_BACKING_OP; - break; - default: - break; + sta = rtw_get_stainfo(&a->stapriv, pnetwork->MacAddress); + if (sta) + rtw_hw_disconnect(a, sta); + else + RTW_ERR(FUNC_ADPT_FMT ": can't find drv sta info for " + MAC_FMT " !\n", + FUNC_ADPT_ARG(a), + MAC_ARG(pnetwork->MacAddress)); } - _exit_critical_mutex(&rfctl->offch_mutex, NULL); + /*reset hw before connection if necessary*/ + } -#ifdef CONFIG_RTW_ROAM_QUICKSCAN -extern inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b); -extern int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); -void generate_quickss(_adapter *padapter) +void update_join_info(struct _ADAPTER *a, struct _WLAN_BSSID_EX *pbuf) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *pnetwork = NULL; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct rtw_ieee80211_channel *roam_ch = pmlmeext->roam_ch; - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - int chan; - _irqL irqL; - _list *plist, *phead; - u8 *target_ssid=NULL, *ssid=NULL, ds_cfg, j, ch_num; - u32 target_ssid_len=0, ssid_len=0; - u8 mark[166]; - - target_ssid = pmlmepriv->cur_network.network.Ssid.Ssid; - target_ssid_len = pmlmepriv->cur_network.network.Ssid.SsidLength; - _rtw_memset(mark, 0, sizeof(u8)*166); - - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - phead = get_list_head(&(pmlmepriv->scanned_queue)); - if (!phead) { - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - return; - } - plist = get_next(phead); - if (!plist) { - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - return; - } - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; - - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (!pnetwork) - break; - - ds_cfg = pnetwork->network.Configuration.DSConfig; - if (is_same_ess(&pnetwork->network, &pmlmepriv->cur_network.network) && - rtw_is_desired_network(padapter, pnetwork)) - mark[ds_cfg] = 1; - - plist = get_next(plist); - } - /* ex: assume roaming channel=1/6/40/165, then mark[1]/[6]/[40]/[165] are 1. */ - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + struct mlme_ext_priv *pmlmeext = &a->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct _WLAN_BSSID_EX *pnetwork = &pmlmeinfo->network; + struct _NDIS_802_11_VARIABLE_IEs *pIE; + u32 i; + u8 join_type; - ch_num = 0; - for (j = 0; j < rfctl->max_chan_nums; j++) { - chan = rfctl->channel_set[j].ChannelNum; - if (mark[chan]) { - roam_ch[ch_num].hw_value = chan; - roam_ch[ch_num++].flags = rfctl->channel_set[j].flags; - } - } - pmlmeext->roam_ch_num = ch_num; -} -#endif + a->mlmepriv.num_FortyMHzIntolerant = 0; + a->mlmepriv.num_sta_no_ht = 0; + a->mlmepriv.htpriv.ampdu_enable = _FALSE;/* reset to disabled */ -u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) -{ - struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; -#ifdef DBG_CHECK_FW_PS_STATE - struct dvobj_priv *dvobj = padapter->dvobj; - struct debug_priv *pdbgpriv = &dvobj->drv_dbg; -#endif - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct ss_res *ss = &pmlmeext->sitesurvey_res; -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); -#endif - u8 val8; + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; + pmlmeinfo->bwmode_updated = _FALSE; + /* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */ + pmlmeinfo->VHT_enable = 0; + pmlmeinfo->HE_enable = 0; +#ifdef ROKU_PRIVATE + pmlmeinfo->ht_vht_received = 0; + _rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX); +#endif /* ROKU_PRIVATE */ + _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = pbuf->IELength; + _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; -#endif -#endif + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); -#ifdef DBG_CHECK_FW_PS_STATE - if (rtw_fw_ps_state(padapter) == _FAIL) { - RTW_INFO("scan without leave 32k\n"); - pdbgpriv->dbg_scan_pwr_state_cnt++; - } -#endif /* DBG_CHECK_FW_PS_STATE */ + /* sizeof(NDIS_802_11_FIXED_IEs) */ + for (i = _FIXED_IE_LENGTH_; i < (pnetwork->IELength - 2);) { + pIE = (struct _NDIS_802_11_VARIABLE_IEs*)(pnetwork->IEs + i); - /* increase channel idx */ - if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) - ss->channel_idx++; + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */ + if (_rtw_memcmp(pIE->data, WMM_OUI, 4)) + WMM_param_handler(a, pIE); + break; - /* update scan state to next state (assigned by previous cmd hdl) */ - if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext)) - mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext)); +#ifdef CONFIG_80211N_HT + case _HT_CAPABILITY_IE_: /* Get HT Cap IE. */ + pmlmeinfo->HT_caps_enable = 1; + break; -operation_by_state: - switch (mlmeext_scan_state(pmlmeext)) { + case _HT_EXTRA_INFO_IE_: /* Get HT Info IE. */ + pmlmeinfo->HT_info_enable = 1; + break; +#endif /* CONFIG_80211N_HT */ - case SCAN_DISABLE: - /* - * SW parameter initialization - */ +#ifdef CONFIG_80211AC_VHT + case EID_VHTCapability: /* Get VHT Cap IE. */ + pmlmeinfo->VHT_enable = 1; + break; - sitesurvey_res_reset(padapter, pparm); - mlmeext_set_scan_state(pmlmeext, SCAN_START); - goto operation_by_state; + case EID_VHTOperation: /* Get VHT Operation IE. */ + break; +#endif /* CONFIG_80211AC_VHT */ - case SCAN_START: -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - if ((pwdev_priv->pno_mac_addr[0] != 0xFF) - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) { - u16 seq_num; +#ifdef CONFIG_80211AX_HE + case WLAN_EID_EXTENSION: + if (pIE->data[0] == WLAN_EID_EXTENSION_HE_CAPABILITY) + pmlmeinfo->HE_enable = 1; + break; +#endif /* CONFIG_80211AX_HE */ -#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI - rtw_hal_pno_random_gen_mac_addr(padapter); -#endif - rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr); - get_random_bytes(&seq_num, 2); - pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF; - RTW_INFO("%s pno_scan_seq_num %d\n", __func__, - pwdev_priv->pno_scan_seq_num); + default: + break; } -#endif - /* - * prepare to leave operating channel - */ + i += (pIE->Length + 2); + } -#ifdef CONFIG_MCC_MODE - rtw_hal_set_mcc_setting_scan_start(padapter); -#endif /* CONFIG_MCC_MODE */ + /*get chan/bw/offset info from IEs*/ + rtw_bss_get_chbw(pnetwork, + &pmlmeext->chandef.chan, (u8 *)&pmlmeext->chandef.bw, + (u8 *)&pmlmeext->chandef.offset, 1, 1); - /* apply rx ampdu setting */ - if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID - || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID) - rtw_rx_ampdu_apply(padapter); + /*adjust chan/bw/offset with registary and hw cap*/ + rtw_adjust_chbw(a, pmlmeext->chandef.chan, (u8 *)&pmlmeext->chandef.bw, + (u8 *)&pmlmeext->chandef.offset); - /* clear HW TX queue before scan */ - rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); +} +static void set_hw_prepare_connect(_adapter *padapter, struct sta_info *sta) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + WLAN_BSSID_EX *pnetwork = &pmlmeinfo->network; - rtw_hal_macid_sleep_all_used(padapter); +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_antenna_select_cmd(padapter, pnetwork->PhyInfo.Optimum_antenna, _FALSE); +#endif + rtw_hw_prepare_connect(padapter, sta, pnetwork->MacAddress); +} - /* power save state announcement */ - if (rtw_ps_annc(padapter, 1)) { - mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); - mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); - set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ - } else { - mlmeext_set_scan_state(pmlmeext, SCAN_ENTER); - goto operation_by_state; - } +#define CONFIG_PHL_MI - break; +#ifdef CONFIG_PHL_MI +/* +join_res = -1 caller is rtw_hw_connect_abort +join_res = 1 caller is rtw_hw_connected +*/ +void rtw_join_done_chk_ch(_adapter *adapter, int join_res) +{ +#define DUMP_ADAPTERS_STATUS 0 - case SCAN_ENTER: - /* - * HW register and DM setting for enter scan - */ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; - rtw_phydm_ability_backup(padapter); + int chanctx_num = 0; + #if 1 + struct rtw_chan_def chandef = {0}; + #else + struct rtw_chan_def *chandef; + #endif + u8 u_ch = 0; + enum channel_width u_bw = 0; + enum chan_offset u_offset = 0; + int i, ret; + bool is_chctx_add = false; - sitesurvey_set_igi(padapter); + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } - /* config dynamic functions for off channel */ - rtw_phydm_func_for_offchannel(padapter); - /* set MSR to no link state */ - sitesurvey_set_msr(padapter, _TRUE); + chanctx_num = rtw_phl_mr_get_chanctx_num(dvobj->phl, adapter->phl_role); + if (join_res >= 0 && chanctx_num <= 0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + RTW_ERR("%s join_res:%d, chanctx_num:%d failed\n", __func__, join_res, chanctx_num); + join_res = -1; + rtw_warn_on(1); + } + #if 1 + rtw_phl_mr_get_chandef(dvobj->phl, adapter->phl_role, &chandef); + if (chandef.chan == 0) { + RTW_ERR("%s chandef.chan == 0\n", __func__); + rtw_warn_on(1); + return; + } + #else + if (adapter->phl_role->chanctx) { + chandef = &adapter->phl_role->chanctx->chan_def; + if (chandef.chan == 0) { + RTW_ERR("%s chandef.chan == 0\n", __func__); + rtw_warn_on(1); + return; + } + } + #endif + u_ch = chandef.chan; + u_bw = chandef.bw; + u_offset = chandef.offset; - val8 = 1; /* under site survey */ - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + if (join_res >= 0) { /*client join success - restart all ap*/ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; - mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); - goto operation_by_state; + if (!iface || iface == adapter || !rtw_is_adapter_up(iface)) + continue; - case SCAN_PROCESS: { - u8 scan_ch; - RT_SCAN_TYPE scan_type; - u8 next_state; - u32 scan_ms; + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + && check_fwstate(mlme, WIFI_OP_CH_SWITCHING) + ) { + u8 ori_ch, ori_bw, ori_offset; -#ifdef CONFIG_RTW_ACS - if (IS_ACS_ENABLE(padapter)) - rtw_acs_get_rst(padapter); -#endif + /* handle AP which need to switch ch setting */ + ori_ch = mlmeext->chandef.chan; + ori_bw = mlmeext->chandef.bw; + ori_offset = mlmeext->chandef.offset; - next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); + /* restore original bw, adjust bw by registry setting on target ch */ + mlmeext->chandef.bw = mlme->ori_chandef.bw; + #if 1 + mlmeext->chandef.chan = chandef.chan; + #else + mlmeext->chandef.chan = chandef->chan; + #endif - if (next_state != SCAN_PROCESS) { - mlmeext_set_scan_state(pmlmeext, next_state); - goto operation_by_state; - } + /*adjust offset according to union chan and bw*/ + rtw_adjust_chbw(iface, mlmeext->chandef.chan, + (u8 *)&mlmeext->chandef.bw, + (u8 *)&mlmeext->chandef.offset); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(mlmeext->chandef.chan, + &mlmeext->chandef.bw, + &mlmeext->chandef.offset); + #endif - /* still SCAN_PROCESS state */ - #ifdef DBG_SITESURVEY - #ifdef CONFIG_P2P - RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - , scan_ch - , pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx - , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) - , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' - , ss->ssid[0].SsidLength ? 'S' : ' ' - , ss->force_ssid_scan ? 'F' : ' ' - ); - #else - RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - , scan_ch - , ss->channel_idx - , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) - , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' - , ss->ssid[0].SsidLength ? 'S' : ' ' - , ss->force_ssid_scan ? 'F' : ' ' - ); - #endif /* CONFIG_P2P */ - #endif /*DBG_SITESURVEY*/ -#ifdef DBG_FIXED_CHAN - if (pmlmeext->fixed_chan != 0xff) - RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); -#endif + #if 0 + rtw_chset_sync_chbw(adapter_to_chset(adapter) + , &mlmeext->chandef.chan, &mlmeext->chandef.bw, &mlmeext->chandef.offset + , &u_ch, &u_bw, &u_offset, 1, 0); + #endif - site_survey(padapter, scan_ch, scan_type); + rtw_hw_update_chan_def(iface); + is_chctx_add = rtw_phl_chanctx_add(dvobj->phl, iface->phl_role, + &u_ch, &u_bw, &u_offset); + + RTW_INFO(FUNC_ADPT_FMT" ori:%u,%u,%u => cur:%u,%u,%u => grp:%u,%u,%u - chctx_add:%s\n", + FUNC_ADPT_ARG(iface), + ori_ch, ori_bw, ori_offset, + mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset, + u_ch, u_bw, u_offset, + (is_chctx_add) ? "Y" : "N"); + if (is_chctx_add == false) { + RTW_ERR(FUNC_ADPT_FMT" chctx_add failed\n", FUNC_ADPT_ARG(iface)); + rtw_warn_on(1); + } -#if defined(CONFIG_ATMEL_RC_PATCH) - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - scan_ms = 20; - else - scan_ms = 40; -#else - #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) - if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) - scan_ms = rtw_acs_get_adv_st(padapter); - else - #endif /*CONFIG_RTW_ACS*/ - scan_ms = ss->scan_ch_ms; -#endif + rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset); -#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) - if (ss->is_sw_antdiv_bl_scan) - scan_ms = scan_ms / 2; -#endif + _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); -#ifdef CONFIG_RTW_ACS - if (IS_ACS_ENABLE(padapter)) { - if (pparm->token) - rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH); - else - rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS); - } -#endif + rtw_start_bss_hdl_after_chbw_decided(iface); -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - if (IS_NM_ENABLE(padapter)) - rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2); -#endif - set_survey_timer(pmlmeext, scan_ms); - break; - } + { + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + u8 ht_option = 0; -#ifdef CONFIG_SCAN_BACKOP - case SCAN_BACKING_OP: { - u8 back_ch = 0, back_bw = 0, back_ch_offset = 0; - u8 need_ch_setting_union = _TRUE; + #ifdef CONFIG_80211N_HT + ht_option = mlme->htpriv.ht_option; + #endif -#ifdef CONFIG_MCC_MODE - need_ch_setting_union = rtw_hal_mcc_change_scan_flag(padapter, - &back_ch, &back_bw, &back_ch_offset); -#endif /* CONFIG_MCC_MODE */ + rtw_cfg80211_ch_switch_notify(iface + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset + , ht_option, 0); + #endif + } - if (need_ch_setting_union) { - if (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0) { - rtw_warn_on(1); - back_ch = pmlmeext->cur_channel; - back_bw = pmlmeext->cur_bwmode; - back_ch_offset = pmlmeext->cur_ch_offset; + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + rtw_update_beacon(iface, 0xFF, NULL, _TRUE, 0); + rtw_phl_cmd_stop_beacon(adapter_to_dvobj(adapter)->phl, iface->phl_role, _FALSE, PHL_CMD_DIRECTLY, 0); } } + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0); + #endif - #ifdef DBG_SITESURVEY - RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - , back_ch, back_bw, back_ch_offset - , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) - ); - #endif /*DBG_SITESURVEY*/ - set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw); - - sitesurvey_set_msr(padapter, _FALSE); - - val8 = 0; /* survey done */ - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); - - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { - sitesurvey_set_igi(padapter); - rtw_hal_macid_wakeup_all_used(padapter); - rtw_ps_annc(padapter, 0); - } - - mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP); - ss->backop_time = rtw_get_current_time(); - - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME)) - rtw_mi_os_xmit_schedule(padapter); - - - goto operation_by_state; - } - - case SCAN_BACK_OP: - if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms - || pmlmeext->scan_abort - ) { - mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP); - goto operation_by_state; + #if 1 + if (chandef.chan != u_ch) + #else + if (chandef->chan != u_ch) + #endif + { + RTW_ERR("[MI] chandef->chan != u_ch\n"); + rtw_warn_on(1); } - set_survey_timer(pmlmeext, 50); - break; - - case SCAN_LEAVING_OP: - /* - * prepare to leave operating channel - */ + } else { /*client join failed - restart all ap on ori-chan*/ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; - /* clear HW TX queue before scan */ - rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + if (!iface || iface == adapter || !rtw_is_adapter_up(iface)) + continue; - rtw_hal_macid_sleep_all_used(padapter); - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC) - && rtw_ps_annc(padapter, 1) - ) { - mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); - mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP); - set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ - } else { - mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP); - goto operation_by_state; + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + && check_fwstate(mlme, WIFI_OP_CH_SWITCHING) + ) { + u_ch = mlmeext->chandef.chan; + u_bw = mlmeext->chandef.bw; + u_offset = mlmeext->chandef.offset; + + is_chctx_add = rtw_phl_chanctx_add(dvobj->phl, iface->phl_role, + &u_ch, &u_bw, &u_offset); + if (is_chctx_add == _FALSE) { + RTW_ERR(FUNC_ADPT_FMT "chctx_add failed\n", FUNC_ADPT_ARG(iface)); + rtw_warn_on(1); + } + RTW_INFO(FUNC_ADPT_FMT" cur:%u,%u,%u => grp:%u,%u,%u chctx_add:%s\n", + FUNC_ADPT_ARG(iface), + mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset, + u_ch, u_bw, u_offset, + (is_chctx_add) ? "Y" : "N"); + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + rtw_update_beacon(iface, 0xFF, NULL, _TRUE, 0); + rtw_phl_cmd_stop_beacon(adapter_to_dvobj(adapter)->phl, iface->phl_role, _FALSE, PHL_CMD_DIRECTLY, 0); + } } - break; - - case SCAN_LEAVE_OP: - /* - * HW register and DM setting for enter scan - */ + #ifdef CONFIG_80211D + rtw_leavebss_update_regulatory(adapter); + #endif - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) - sitesurvey_set_igi(padapter); + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0); + #endif + } - sitesurvey_set_msr(padapter, _TRUE); + RTW_INFO("[MI] union:%u,%u,%u\n", u_ch, u_bw, u_offset); + #if 1 + RTW_INFO("[MI] chandef:%u,%u,%u\n", chandef.chan, chandef.bw, chandef.offset); + #else + RTW_INFO("[MI] chandef:%u,%u,%u\n", chandef->chan, chandef->bw, chandef->offset); + #endif + set_channel_bwmode(adapter, u_ch, u_offset, u_bw, _FALSE); + rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); - val8 = 1; /* under site survey */ - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + if (join_res >= 0) + rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), BIT(adapter->iface_id), 1); - mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); - goto operation_by_state; + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } +} -#endif /* CONFIG_SCAN_BACKOP */ +int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 u_ch = 0, cur_ch = 0; + enum channel_width u_bw = 0, cur_bw = 0; + enum chan_offset u_offset = 0, cur_offset = 0; + bool is_chctx_add = false; + struct mi_state mstate; + bool connect_allow = _TRUE; -#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) - case SCAN_SW_ANTDIV_BL: - /* - * 20100721 - * For SW antenna diversity before link, it needs to switch to another antenna and scan again. - * It compares the scan result and select better one to do connection. - */ - ss->bss_cnt = 0; - ss->channel_idx = 0; - ss->is_sw_antdiv_bl_scan = 1; + if (!ch || !bw || !offset) { + connect_allow = _FALSE; + rtw_warn_on(1); + goto _exit; + } - mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS); - set_survey_timer(pmlmeext, ss->scan_ch_ms); - break; -#endif + u_ch = cur_ch = pmlmeext->chandef.chan; + u_bw = cur_bw = pmlmeext->chandef.bw; + u_offset = cur_offset = pmlmeext->chandef.offset; -#ifdef CONFIG_P2P - case SCAN_TO_P2P_LISTEN: - /* - * Set the P2P State to the listen state of find phase - * and set the current channel to the listen channel - */ - set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); + RTW_INFO(FUNC_ADPT_FMT" CONT - CH:%d, BW:%d OFF:%d\n", + FUNC_ADPT_ARG(adapter),cur_ch, cur_bw, cur_offset); - /* turn on phy-dynamic functions */ - rtw_phydm_ability_restore(padapter); + is_chctx_add = rtw_phl_chanctx_add(dvobj->phl, adapter->phl_role, + &u_ch, &u_bw, &u_offset); - sitesurvey_set_igi(padapter); + if (is_chctx_add == false) { + rtw_mi_status_no_self(adapter, &mstate); + RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); - mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN); - _set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100)); - break; + if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4) + connect_allow = _FALSE; - case SCAN_P2P_LISTEN: - mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); - ss->channel_idx = 0; - goto operation_by_state; -#endif /* CONFIG_P2P */ + #if 0 /*def CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT*/ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; - case SCAN_COMPLETE: -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) - rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter)); -#endif -#ifdef CONFIG_P2P - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) - ) { -#ifdef CONFIG_CONCURRENT_MODE - if (pwdinfo->driver_interface == DRIVER_WEXT) { - if (rtw_mi_check_status(padapter, MI_LINKED)) - _set_timer(&prochinfo->ap_roch_ch_switch_timer, 500); + if (MLME_IS_STA(iface) + && check_fwstate(mlme, WIFI_ASOC_STATE) + #if defined(CONFIG_P2P) + && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE) + #endif + ) { + connect_allow = _FALSE; + break; } -#endif - - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); } - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); -#endif /* CONFIG_P2P */ + #endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ - /* switch channel */ - survey_done_set_ch_bw(padapter); + if (connect_allow == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT" connect_allow = _FALSE\n", FUNC_ADPT_ARG(adapter)); + goto _exit; + } - sitesurvey_set_msr(padapter, _FALSE); + rtw_mi_buddy_disconnect(adapter); + rtw_phl_chanctx_del_no_self(dvobj->phl, adapter->phl_role); - val8 = 0; /* survey done */ - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + u_ch = cur_ch; + u_bw = cur_bw; + u_offset = cur_offset; + is_chctx_add = rtw_phl_chanctx_add(dvobj->phl, adapter->phl_role, + &u_ch, &u_bw, &u_offset); + if (is_chctx_add == false) { + RTW_ERR("%s - %d chanctx_add failed\n", __FUNCTION__, __LINE__); + rtw_warn_on(1); + connect_allow = _FALSE; + goto _exit; + } + } - /* turn on phy-dynamic functions */ - rtw_phydm_ability_restore(padapter); + #ifdef CONFIG_80211D + rtw_joinbss_update_regulatory(adapter, &adapter->mlmeextpriv.mlmext_info.network); + #endif - sitesurvey_set_igi(padapter); + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0); + #endif -#ifdef CONFIG_MCC_MODE - /* start MCC fail, then tx null data */ - if (!rtw_hal_set_mcc_setting_scan_complete(padapter)) -#endif - { - rtw_hal_macid_wakeup_all_used(padapter); - rtw_ps_annc(padapter, 0); - } + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; +_exit: + RTW_INFO(FUNC_ADPT_FMT" chctx_add:%s\n", FUNC_ADPT_ARG(adapter), (is_chctx_add) ? "Y" : "N"); + RTW_INFO("Grouped - CH:%d, BW:%d OFF:%d\n",u_ch, u_bw, u_offset); + return connect_allow; +} - /* apply rx ampdu setting */ - rtw_rx_ampdu_apply(padapter); +#else +void rtw_join_done_chk_ch(_adapter *adapter, int join_res) +{ +#define DUMP_ADAPTERS_STATUS 0 - mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + struct dvobj_priv *dvobj; + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; + u8 u_ch, u_offset, u_bw; + int i, ret; - report_surveydone_event(padapter, ss->acs); -#ifdef CONFIG_RTW_ACS - if (IS_ACS_ENABLE(padapter)) - rtw_acs_select_best_chan(padapter); -#endif + dvobj = adapter_to_dvobj(adapter); -#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR) - if (IS_NM_ENABLE(padapter)) - rtw_noise_info_dump(RTW_DBGDUMP, padapter); -#endif - issue_action_BSSCoexistPacket(padapter); - issue_action_BSSCoexistPacket(padapter); - issue_action_BSSCoexistPacket(padapter); + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } -#ifdef CONFIG_RTW_80211K - if (ss->token) - rm_post_event(padapter, ss->token, RM_EV_survey_done); -#endif /* CONFIG_RTW_80211K */ -#ifdef CONFIG_RTW_ROAM_QUICKSCAN - if (padapter->mlmepriv.need_to_roam == _TRUE) - generate_quickss(padapter); -#endif - break; + ret = rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset); + if (join_res >= 0 && ret <= 0) { + join_res = -1; + dump_adapters_status(RTW_DBGDUMP , dvobj); + rtw_warn_on(1); } - return H2C_SUCCESS; -} + if (join_res >= 0) { -u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) -{ - struct setauth_parm *pparm = (struct setauth_parm *)pbuf; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; - if (pparm->mode < 4) - pmlmeinfo->auth_algo = pparm->mode; + if (!iface || iface == adapter) + continue; - return H2C_SUCCESS; -} + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + u8 ori_ch, ori_bw, ori_offset; + bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset); -static u8 amsdu_spp_enable(_adapter *pdapter, enum security_type type) -{ - u8 ret = _FALSE; + if (is_grouped == _FALSE) { + /* handle AP which need to switch ch setting */ - if (pdapter->registrypriv.amsdu_mode == RTW_AMSDU_MODE_SPP) { - if ( type == _AES_ || type == _CCMP_256_ - || type == _GCMP_ || type == _GCMP_256_ ) - ret = _SUCCESS; - } + ori_ch = mlmeext->chandef.chan; + ori_bw = mlmeext->chandef.bw; + ori_offset = mlmeext->chandef.offset; - return ret; -} + /* restore original bw, adjust bw by registry setting on target ch */ + mlmeext->chandef.bw = mlme->ori_chandef.bw; + mlmeext->chandef.chan = u_ch; + rtw_adjust_chbw(iface, mlmeext->chandef.chan, + (u8 *)&mlmeext->chandef.bw, + (u8 *)&mlmeext->chandef.offset); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(mlmeext->chandef.chan, + &mlmeext->chandef.bw, + &mlmeext->chandef.offset); + #endif -/* -SEC CAM Entry format (32 bytes) -DW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7] | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] -DW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7] | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A) -DW1 - MAC_ADDR[47:16] -DW2 - KEY[31:0] -DW3 - KEY[63:32] -DW4 - KEY[95:64] -DW5 - KEY[127:96] -DW6 - RSVD -DW7 - RSVD -*/ + rtw_chset_sync_chbw(adapter_to_chset(adapter) + , &mlmeext->chandef.chan, &mlmeext->chandef.bw, &mlmeext->chandef.offset + , &u_ch, &u_bw, &u_offset, 1, 0); -/*Set WEP key or Group Key*/ -u8 setkey_hdl(_adapter *padapter, u8 *pbuf) -{ - u16 ctrl = 0; - s16 cam_id = 0; - struct setkey_parm *pparm = (struct setkey_parm *)pbuf; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - u8 *addr; - bool used = _FALSE; + RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface) + , ori_ch, ori_bw, ori_offset + , mlmeext->chandef.chan, mlmeext->mlmeext->chandef.bw, mlmeext->chandef.offset); - /* main tx key for wep. */ - if (pparm->set_tx) - pmlmeinfo->key_index = pparm->keyid; + rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset); -#ifndef SEC_DEFAULT_KEY_SEARCH - if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) - cam_id = rtw_iface_bcmc_id_get(padapter); - else -#endif - cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, - !!(pparm->algorithm & _SEC_TYPE_256_), &used); + _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); - if (cam_id < 0) - goto enable_mc; + rtw_start_bss_hdl_after_chbw_decided(iface); -#ifdef SEC_DEFAULT_KEY_SEARCH - if (cam_id >= 0 && cam_id <= 3) { - /* default key camid */ - addr = null_addr; - } else -#endif - { - /* not default key camid */ - if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) { - /* group TX, force sec cam entry_id */ - addr = adapter_mac_addr(padapter); - } else { - /* group RX, searched by A2 (TA) */ - addr = get_bssid(&padapter->mlmepriv); - } - } + { + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + u8 ht_option = 0; -#ifdef CONFIG_LPS_PG - if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG) - LPS_Leave(padapter, "SET_KEY"); -#endif + #ifdef CONFIG_80211N_HT + ht_option = mlme->htpriv.ht_option; + #endif + + rtw_cfg80211_ch_switch_notify(iface + , mlmeext->chandef.chan, mlmeext->chandef.bw, mlmeext->chandef.offset + , ht_option, 0); + #endif + } + } - /* cam entry searched is pairwise key */ - if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) { - s16 camid_clr; + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + rtw_update_beacon(iface, 0xFF, NULL, _TRUE, 0); + } + } - RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid); +#ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0); +#endif + } else { + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; - /* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */ - rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + if (!iface || iface == adapter) + continue; - /* clear group key */ - while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) { - RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr); - clear_cam_entry(padapter, camid_clr); - rtw_camid_free(padapter, camid_clr); + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + rtw_update_beacon(iface, 0xFF, NULL, _TRUE, 0); + } } - goto enable_mc; - } - - ctrl = BIT(15) | BIT(6) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid; - - RTW_PRINT("set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" - , cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm)); + #ifdef CONFIG_80211D + rtw_leavebss_update_regulatory(adapter); + #endif - if (pparm->algorithm & _SEC_TYPE_256_) { - RTW_INFO_DUMP("GTK : ", pparm->key, sizeof(pparm->key)); - ctrl |= BIT(9); +#ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0); +#endif } - if (amsdu_spp_enable(padapter, pparm->algorithm) == _SUCCESS) - ctrl |= BIT(7); - write_cam(padapter, cam_id, ctrl, addr, pparm->key); + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) { + RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + set_channel_bwmode(adapter, u_ch, u_offset, u_bw, _FALSE); + rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); + } - /* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/ -#ifndef SEC_DEFAULT_KEY_SEARCH - if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) { - if (is_wep_enc(pparm->algorithm)) { - padapter->securitypriv.dot11Def_camid[pparm->keyid] = cam_id; - padapter->securitypriv.dot118021x_bmc_cam_id = - padapter->securitypriv.dot11Def_camid[padapter->securitypriv.dot11PrivacyKeyIndex]; - RTW_PRINT("wep group key - force camid:%d\n", padapter->securitypriv.dot118021x_bmc_cam_id); - } else { - /*u8 org_cam_id = padapter->securitypriv.dot118021x_bmc_cam_id;*/ - - /*force GK's cam id*/ - padapter->securitypriv.dot118021x_bmc_cam_id = cam_id; - - /* for GTK rekey - if ((org_cam_id != INVALID_SEC_MAC_CAM_ID) && - (org_cam_id != cam_id)) { - RTW_PRINT("clear group key for addr:"MAC_FMT", org_camid:%d new_camid:%d\n", MAC_ARG(addr), org_cam_id, cam_id); - clear_cam_entry(padapter, org_cam_id); - rtw_camid_free(padapter, org_cam_id); - }*/ - } + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); } -#else - if (cam_id >= 0 && cam_id <= 3) - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE); +} +int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ +#ifdef CONFIG_CONCURRENT_MODE + bool chbw_allow = _TRUE; #endif + bool connect_allow = _TRUE; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 cur_ch, cur_bw, cur_ch_offset; + u8 u_ch, u_offset, u_bw; - /* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */ - if (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) && - _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) { - struct set_stakey_parm sta_pparm; + u_ch = cur_ch = pmlmeext->chandef.chan; + u_bw = cur_bw = pmlmeext->chandef.bw; + u_offset = cur_ch_offset = pmlmeext->chandef.offset; - _rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm)); - sta_pparm.algorithm = pparm->algorithm; - sta_pparm.keyid = pparm->keyid; - _rtw_memcpy(sta_pparm.key, pparm->key, 16); - _rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN); - set_stakey_hdl(padapter, (u8 *)&sta_pparm); + if (!ch || !bw || !offset) { + connect_allow = _FALSE; + rtw_warn_on(1); + goto exit; } -enable_mc: - /* allow multicast packets to driver */ - rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr); -#ifdef CONFIG_LAYER2_ROAMING - if (padapter->mlmepriv.roam_network) { - struct xmit_frame *rframe; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _list *plist, *phead; - _irqL irqL; - _pkt *pkt; - - padapter->mlmepriv.roam_network = NULL; - _enter_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); - phead = get_list_head(&pxmitpriv->rpkt_queue); - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - rframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - plist = get_next(plist); - rtw_list_delete(&rframe->list); - pkt = rframe->pkt; - rframe->pkt = NULL; - rtw_xmit_posthandle(padapter, rframe, pkt); - } - _exit_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); + if (cur_ch == 0) { + connect_allow = _FALSE; + RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n" + , FUNC_ADPT_ARG(adapter), cur_ch); + rtw_warn_on(1); + goto exit; } -#endif - return H2C_SUCCESS; -} - -void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta) -{ - struct security_priv *psecuritypriv = &(adapter->securitypriv); - struct set_stakey_parm sta_pparm; - sint keyid; + RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) - return; +#ifdef CONFIG_CONCURRENT_MODE + { + struct dvobj_priv *dvobj; + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; + struct mi_state mstate; + int i; - for (keyid = 0; keyid < 4; keyid++) { - if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) { - sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm; - sta_pparm.keyid = keyid; - sta_pparm.gk = 0; - _rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16); - _rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN); + dvobj = adapter_to_dvobj(adapter); - RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid); + rtw_mi_status_no_self(adapter, &mstate); + RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); - set_stakey_hdl(adapter, (u8 *)&sta_pparm); + if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { + /* consider linking STA? */ + goto connect_allow_hdl; } - } -} -u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) -{ - u16 ctrl = 0; - s16 cam_id = 0; - bool used; - u8 ret = H2C_SUCCESS; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; + if (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + rtw_warn_on(1); + } + RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n" + , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - if (pparm->algorithm == _NO_PRIVACY_) - goto write_to_cam; + /* chbw_allow? */ + chbw_allow = rtw_is_chbw_grouped(pmlmeext->chandef.chan, pmlmeext->chandef.bw, pmlmeext->chandef.offset + , u_ch, u_bw, u_offset); - psta = rtw_get_stainfo(pstapriv, pparm->addr); - if (!psta) { - RTW_PRINT("%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr)); - ret = H2C_REJECTED; - goto exit; - } + RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n" + , FUNC_ADPT_ARG(adapter), chbw_allow); - pmlmeinfo->enc_algo = pparm->algorithm; + if (chbw_allow == _TRUE) { + rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset); + rtw_warn_on(cur_ch != pmlmeext->chandef.chan); + rtw_warn_on(cur_bw != pmlmeext->chandef.bw); + rtw_warn_on(cur_ch_offset != pmlmeext->chandef.offset); + goto connect_allow_hdl; + } - cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, - !!(pparm->algorithm & _SEC_TYPE_256_), &used); - if (cam_id < 0) - goto exit; +#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT + /* chbw_allow is _FALSE, connect allow? */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; -#ifdef CONFIG_LPS_PG - if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG) - LPS_Leave(padapter, "SET_KEY"); + if (MLME_IS_STA(iface) && +#if defined(CONFIG_P2P) + !rtw_p2p_chk_role(&(iface->wdinfo), P2P_ROLE_CLIENT) && + !rtw_p2p_chk_role(&(iface->wdinfo), P2P_ROLE_GO) && #endif + check_fwstate(mlme, WIFI_ASOC_STATE)) { + connect_allow = _FALSE; + break; + } + } +#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ - /* cam entry searched is group key when setting pariwise key */ - if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { - s16 camid_clr; + if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4) + connect_allow = _FALSE; - RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid); + RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n" + , FUNC_ADPT_ARG(adapter), connect_allow); - /* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */ - rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + if (connect_allow == _FALSE) + goto exit; - /* clear group key */ - while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) { - RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr); - clear_cam_entry(padapter, camid_clr); - rtw_camid_free(padapter, camid_clr); - } - } +connect_allow_hdl: + /* connect_allow == _TRUE */ -write_to_cam: - if (pparm->algorithm == _NO_PRIVACY_) { - while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) { - RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id); - clear_cam_entry(padapter, cam_id); - rtw_camid_free(padapter, cam_id); - } - } else { - RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" - , pparm->gk ? "group" : "pairwise" - , cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); - ctrl = BIT(15) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid; - if (pparm->gk) - ctrl |= BIT(6); - if (pparm->algorithm & _SEC_TYPE_256_) { - RTW_INFO_DUMP("PTK : ", pparm->key, sizeof(pparm->key)); - ctrl |= BIT(9); - } - if (amsdu_spp_enable(padapter, pparm->algorithm) == _SUCCESS) - ctrl |= BIT(7); - write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); - if (!(pparm->gk)) - ATOMIC_INC(&psta->keytrack); /*CVE-2020-24587*/ - } - ret = H2C_SUCCESS_RSP; + if (chbw_allow == _FALSE) { + u_ch = cur_ch; + u_bw = cur_bw; + u_offset = cur_ch_offset; -exit: - return ret; -} + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; -u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) -{ - struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + if (!iface || iface == adapter) + continue; - struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(iface, pmlmeext->chandef.chan , pmlmeext->chandef.offset); + else + #endif + rtw_sta_flush(iface, _FALSE); - if (!psta) - return H2C_SUCCESS; + rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0); + set_fwstate(mlme, WIFI_OP_CH_SWITCHING); -#ifdef CONFIG_80211N_HT - if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || - ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - /* pmlmeinfo->ADDBA_retry_count = 0; */ - /* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); */ - /* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */ - issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); - _set_timer(&psta->addba_retry_timer, ADDBA_TO); - } -#ifdef CONFIG_TDLS - else if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && - (psta->htpriv.ht_option == _TRUE) && - (psta->htpriv.ampdu_enable == _TRUE)) { - issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); - _set_timer(&psta->addba_retry_timer, ADDBA_TO); + } else if (MLME_IS_STA(iface) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY); +#ifndef CONFIG_STA_CMD_DISPR + rtw_free_assoc_resources(iface, _TRUE); +#endif /* !CONFIG_STA_CMD_DISPR */ + rtw_indicate_disconnect(iface, 0, _FALSE); + } + } + } } -#endif /* CONFIG */ - else - psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); -#endif /* CONFIG_80211N_HT */ - return H2C_SUCCESS; -} +#endif /* CONFIG_CONCURRENT_MODE */ + #ifdef CONFIG_80211D + rtw_joinbss_update_regulatory(adapter, &adapter->mlmeextpriv.mlmext_info.network); + #endif -u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) -{ - struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf; - struct recv_reorder_ctrl *preorder_ctrl; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; - u8 ret = _TRUE; + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0); + #endif - psta = rtw_get_stainfo(pstapriv, pparm->addr); - if (!psta) - goto exit; +exit: - preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid]; - ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50); + if (connect_allow == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; -#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ - /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ - if (pparm->status == 0) { - preorder_ctrl->indicate_seq = pparm->start_seq; - #ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n" - , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); - #endif - } -#else - rtw_set_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack); - #ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d preorder_ctrl->rec_abba_rsp_ack =%lu \n" - , FUNC_ADPT_ARG(padapter) - , preorder_ctrl->tid - , preorder_ctrl->indicate_seq - , pparm->start_seq - ,preorder_ctrl->rec_abba_rsp_ack - ); - #endif +#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + { + u8 ht_option = 0; + + #ifdef CONFIG_80211N_HT + ht_option = adapter->mlmepriv.htpriv.ht_option; + #endif /* CONFIG_80211N_HT */ + + /* + when supplicant send the mlme frame, + the bss freq is updated by channel switch event. + */ + rtw_cfg80211_ch_switch_notify(adapter, + cur_ch, cur_bw, cur_ch_offset, ht_option, 1); + } #endif + } - /* - * status = 0 means accept this addba req - * status = 37 means reject this addba req - */ - if (pparm->status == 0) { - preorder_ctrl->enable = _TRUE; - preorder_ctrl->ampdu_size = pparm->size; - } else if (pparm->status == 37) - preorder_ctrl->enable = _FALSE; - -exit: - return H2C_SUCCESS; + return connect_allow == _TRUE ? _SUCCESS : _FAIL; } +#endif -u8 chk_bmc_sleepq_cmd(_adapter *padapter) +u8 rtw_join_cmd_hdl(_adapter *padapter, u8 *pbuf) { - struct cmd_obj *ph2c; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); - u8 res = _SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + WLAN_BSSID_EX *pnetwork = &pmlmeinfo->network; + struct sta_info *sta = NULL; + u8 u_ch, u_bw, u_offset; + /* Check pbuf->IELength */ + if (((struct _WLAN_BSSID_EX*)pbuf)->IELength > MAX_IE_SZ) + return H2C_PARAMETERS_ERROR; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; + if (((struct _WLAN_BSSID_EX*)pbuf)->IELength < 2) { + report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); + return H2C_SUCCESS; } - init_h2fwcmd_w_parm_no_parm_rsp(ph2c, CMD_CHK_BMCSLEEPQ); + set_hw_before_join(padapter); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + /*update HT/VHT/HE CAP and chan/bw/offset from join_info-pbuf*/ + update_join_info(padapter, (struct _WLAN_BSSID_EX *)pbuf); -exit: + sta = rtw_get_stainfo(&padapter->stapriv, padapter->phl_role->mac_addr); + rtw_free_stainfo(padapter, sta); + sta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); + if (sta == NULL) { + RTW_ERR("alloc sta "MAC_FMT" fail\n", MAC_ARG(pnetwork->MacAddress)); + return H2C_CMD_FAIL; + } + + /* check channel, bandwidth, offset and switch */ + if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) { + report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); + return H2C_SUCCESS; + } + /*allow for connection*/ + set_hw_prepare_connect(padapter, sta); - return res; + rtw_hw_update_chan_def(padapter); + set_channel_bwmode(padapter, u_ch, u_offset, u_bw, _TRUE); + rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw); + rtw_phl_mr_dump_cur_chandef(adapter_to_dvobj(padapter)->phl, padapter->phl_role); + + /* cancel link timer */ + cancel_link_timer(pmlmeext); /*_cancel_timer_ex(&pmlmeext->link_timer);*/ + + /*Client and AD-Hoc client*/ + start_clnt_join(padapter); + + return H2C_SUCCESS; } -u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags) +u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) { - struct cmd_obj *ph2c; - struct Tx_Beacon_param *ptxBeacon_parm; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); +#if CONFIG_DFS + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); +#endif + struct disconnect_parm *param = (struct disconnect_parm *)pbuf; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct submit_ctx sctx; - u8 res = _SUCCESS; - int len_diff = 0; + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 val8; - /*prepare cmd parameter*/ - ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param)); - if (ptxBeacon_parm == NULL) { - res = _FAIL; + /* For STA, disconnect flow only for conneted case */ + if (MLME_IS_STA(padapter) && !MLME_IS_ASOC(padapter)) goto exit; + + if (is_client_associated_to_ap(padapter) + #if CONFIG_DFS + && !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_chandef.chan + #endif + ) { + #ifdef CONFIG_PLATFORM_ROCKCHIPS + /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + #else + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100); + #endif /* CONFIG_PLATFORM_ROCKCHIPS */ } - _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { + /* Stop BCN */ + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); + } - len_diff = update_hidden_ssid( - ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_ - , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_ - , pmlmeinfo->hidden_ssid_mode - ); - ptxBeacon_parm->network.IELength += len_diff; + rtw_mlmeext_disconnect(padapter); + #if 0 + rtw_free_uc_swdec_pending_queue(adapter_to_dvobj(padapter)); + #endif +exit: + return H2C_SUCCESS; +} - /* need enqueue, prepare cmd_obj and enqueue */ - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - rtw_mfree((u8 *)ptxBeacon_parm, sizeof(*ptxBeacon_parm)); - goto exit; +/** + * rtw_ps_annc - check and doing ps announcement for all the adapters + * @adapter: the requesting adapter + * @ps: power saving or not + * + * Returns: 0: no ps announcement is doing. 1: ps announcement is doing + */ +u8 rtw_ps_annc(_adapter *adapter, bool ps) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + int i; + u8 ps_anc = 0; + +#ifdef CONFIG_MCC_MODE + if (rtw_hw_mcc_chk_inprogress(adapter)) { + RTW_WARN("under mcc, skip ps_anc\n"); + return ps_anc; } +#endif - init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, CMD_TX_BEACON); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; - if (flags & RTW_CMDF_WAIT_ACK) { - ph2c->sctx = &sctx; - rtw_sctx_init(&sctx, 10 * 1000); + if (MLME_IS_STA(iface)) { + if (is_client_associated_to_ap(iface) == _TRUE) { + /* TODO: TDLS peers */ + issue_nulldata(iface, NULL, ps, 3, 500); + ps_anc = 1; + } + #ifdef CONFIG_RTW_MESH + } else if (MLME_IS_MESH(iface)) { + if (rtw_mesh_ps_annc(iface, ps)) + ps_anc = 1; + #endif + } } + return ps_anc; +} + +void rtw_back_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + _rtw_mutex_lock_interruptible(&rfctl->offch_mutex); - if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { - rtw_sctx_wait(&sctx, __func__); - _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); - if (sctx.status == RTW_SCTX_SUBMITTED) - ph2c->sctx = NULL; - _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (rfctl->offch_state != OFFCHS_NONE) { + rfctl->offch_state = OFFCHS_BACKING_OP; + rtw_hal_macid_wakeup_all_used(adapter); + rtw_ps_annc(adapter, 0); + + rfctl->offch_state = OFFCHS_NONE; + rtw_mi_os_xmit_schedule(adapter); } - -exit: + _rtw_mutex_unlock(&rfctl->offch_mutex); +} +void rtw_leave_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - return res; -} + _rtw_mutex_lock_interruptible(&rfctl->offch_mutex); + if (rfctl->offch_state == OFFCHS_NONE) { + /* prepare to leave operating channel */ + rfctl->offch_state = OFFCHS_LEAVING_OP; -u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) -{ - struct rtw_evt_header *evt_hdr; - u8 *peventbuf; - void (*event_callback)(_adapter *dev, u8 *pbuf); - struct evt_priv *pevt_priv = &(padapter->evtpriv); + /* clear HW TX queue */ + rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0); - if (pbuf == NULL) - goto _abort_event_; + rtw_hal_macid_sleep_all_used(adapter); - evt_hdr = (struct rtw_evt_header *)pbuf; - peventbuf = pbuf + sizeof(struct rtw_evt_header); + rtw_ps_annc(adapter, 1); -#ifdef CHECK_EVENT_SEQ - /* checking event sequence... */ - if (evt_hdr->seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) { - pevt_priv->event_seq = (evt_hdr->seq + 1) & 0x7f; - goto _abort_event_; + rfctl->offch_state = OFFCHS_LEAVE_OP; } -#endif - /* checking if event code is valid */ - if (evt_hdr->id >= EVT_ID_MAX) { - goto _abort_event_; - } + _rtw_mutex_unlock(&rfctl->offch_mutex); +} - /* checking if event size match the event parm size */ - if ((wlanevents[evt_hdr->id].parmsize != 0) && - (wlanevents[evt_hdr->id].parmsize != evt_hdr->len)) { +u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct setauth_parm *pparm = (struct setauth_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - goto _abort_event_; + if (pparm->mode < 4) + pmlmeinfo->auth_algo = pparm->mode; + + return H2C_SUCCESS; +} +static u8 amsdu_spp_enable(_adapter *pdapter, enum security_type type) +{ + u8 ret = _FALSE; + if (pdapter->registrypriv.amsdu_mode == RTW_AMSDU_MODE_SPP) { + if ( type == _AES_ || type == _CCMP_256_ + || type == _GCMP_ || type == _GCMP_256_ ) + ret = _SUCCESS; } + return ret; +} + +#ifdef CONFIG_CMD_DISP +/*Set WEP key or Group Key*/ +u8 setkey_hdl(struct _ADAPTER *a, struct setkey_parm *key, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct mlme_ext_info *info = &a->mlmeextpriv.mlmext_info; + u8 keytype = 1; /* 1 for Group Key */ + u8 *mac; + struct sta_info *sta; + u8 spp = 0; - ATOMIC_INC(&pevt_priv->event_seq); - if (peventbuf) { - event_callback = wlanevents[evt_hdr->id].event_callback; - event_callback(padapter, (u8 *)peventbuf); - pevt_priv->evt_done_cnt++; + if (((info->state & 0x03) == WIFI_FW_AP_STATE) + || ((info->state & 0x03) == WIFI_FW_ADHOC_STATE)) + mac = adapter_mac_addr(a); + else + mac = get_bssid(&a->mlmepriv); + sta = rtw_get_stainfo(&a->stapriv, mac); + if (!sta) { + RTW_ERR("%s: sta %pM not found\n", __func__, mac); + goto exit; } -_abort_event_: - return H2C_SUCCESS; + /* main tx key for wep. */ + if (key->set_tx) + a->mlmeextpriv.mlmext_info.key_index = key->keyid; -} + /* Change to Unicast for WEP */ + if (is_wep_enc(key->algorithm)) + keytype = 0; -u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) -{ -#ifdef CONFIG_AP_MODE - _irqL irqL; - struct sta_info *psta_bmc; - _list *xmitframe_plist, *xmitframe_phead; - struct xmit_frame *pxmitframe = NULL; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_priv *pstapriv = &padapter->stapriv; + #ifdef CONFIG_IEEE80211W + if (key->algorithm == _BIP_CMAC_128_) + keytype = 2; + #endif - /* for BC/MC Frames */ - psta_bmc = rtw_get_bcmc_stainfo(padapter); - if (!psta_bmc) - return H2C_SUCCESS; + if (amsdu_spp_enable(a, key->algorithm) == _SUCCESS) + spp = 1; - if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { -#ifndef CONFIG_PCI_HCI - rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */ -#endif - /* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ - _enter_critical_bh(&pxmitpriv->lock, &irqL); + RTW_PRINT("%s: set %s key for %pM, kid:%d type:%u algo:%s\n", + __func__, is_wep_enc(key->algorithm)?"WEP":"group", mac, + key->keyid, keytype, security_type_str(key->algorithm)); - xmitframe_phead = get_list_head(&psta_bmc->sleep_q); - xmitframe_plist = get_next(xmitframe_phead); + rtw_hw_add_key(a, sta, key->keyid, key->algorithm, keytype, key->key, spp, cmd_type, cmd_timeout); - while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { - pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); +#ifdef CONFIG_LAYER2_ROAMING + dequeuq_roam_pkt(a); +#endif - xmitframe_plist = get_next(xmitframe_plist); +exit: + return H2C_SUCCESS; +} +#else +/*Set WEP key or Group Key*/ +u8 setkey_hdl(struct _ADAPTER *a, u8 *pbuf) +{ + struct setkey_parm *key = (struct setkey_parm *)pbuf; + struct mlme_ext_info *info = &a->mlmeextpriv.mlmext_info; + u8 keytype = 1; /* 1 for Group Key */ + u8 *mac; + struct sta_info *sta; + u8 spp = 0; - rtw_list_delete(&pxmitframe->list); + if (((info->state & 0x03) == WIFI_FW_AP_STATE) + || ((info->state & 0x03) == WIFI_FW_ADHOC_STATE)) + mac = adapter_mac_addr(a); + else + mac = get_bssid(&a->mlmepriv); + sta = rtw_get_stainfo(&a->stapriv, mac); + if (!sta) { + RTW_ERR("%s: sta %pM not found\n", __func__, mac); + goto exit; + } - psta_bmc->sleepq_len--; - if (psta_bmc->sleepq_len > 0) - pxmitframe->attrib.mdata = 1; - else - pxmitframe->attrib.mdata = 0; + /* main tx key for wep. */ + if (key->set_tx) + a->mlmeextpriv.mlmext_info.key_index = key->keyid; + +#ifdef CONFIG_LPS_PG + if (adapter_to_pwrctl(a)->lps_level == LPS_PG) + LPS_Leave(a, "SET_KEY"); +#endif - pxmitframe->attrib.triggered = 1; + /* Change to Unicast for WEP */ + if (is_wep_enc(key->algorithm)) + keytype = 0; - if (xmitframe_hiq_filter(pxmitframe) == _TRUE) - pxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */ + #ifdef CONFIG_IEEE80211W + if (key->algorithm == _BIP_CMAC_128_) + keytype = 2; + #endif -#if 0 - _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); - if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE) - rtw_os_xmit_complete(padapter, pxmitframe); - _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); -#endif - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); - } + if (amsdu_spp_enable(a, key->algorithm) == _SUCCESS) + spp = 1; - /* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ - _exit_critical_bh(&pxmitpriv->lock, &irqL); + RTW_PRINT("%s: set %s key for %pM, kid:%d type:%u algo:%s\n", + __func__, is_wep_enc(key->algorithm)?"WEP":"group", mac, + key->keyid, keytype, security_type_str(key->algorithm)); - if (rtw_get_intf_type(padapter) != RTW_PCIE) { - /* check hi queue and bmc_sleepq */ - rtw_chk_hi_queue_cmd(padapter); - } - } + rtw_hw_add_key(a, sta, key->keyid, key->algorithm, keytype, key->key, spp, PHL_CMD_DIRECTLY, 0); +#ifdef CONFIG_LAYER2_ROAMING + dequeuq_roam_pkt(a); #endif +exit: return H2C_SUCCESS; } +#endif -u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) +void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta) { -#ifdef CONFIG_AP_MODE - /*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/ -#ifdef CONFIG_SWTIMER_BASED_TXBCN - - tx_beacon_handlder(padapter->dvobj); + struct security_priv *psecuritypriv = &(adapter->securitypriv); + struct set_stakey_parm sta_pparm; + sint keyid; -#else + if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) + return; - if (send_beacon(padapter) == _FAIL) { - RTW_INFO("issue_beacon, fail!\n"); - return H2C_PARAMETERS_ERROR; - } + for (keyid = 0; keyid < 4; keyid++) { + if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) { + sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm; + sta_pparm.keyid = keyid; + sta_pparm.gk = 0; + _rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16); + _rtw_memcpy(sta_pparm.addr, psta->phl_sta->mac_addr, ETH_ALEN); - /* tx bc/mc frames after update TIM */ - chk_bmc_sleepq_hdl(padapter, NULL); + RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->phl_sta->mac_addr), keyid); +#ifdef CONFIG_CMD_DISP + set_stakey_hdl(adapter, &sta_pparm, PHL_CMD_DIRECTLY, 0); +#else /* CONFIG_FSM */ + set_stakey_hdl(adapter, (u8 *)&sta_pparm); #endif -#endif /* CONFIG_AP_MODE */ - return H2C_SUCCESS; + } + } } -/* -* according to channel -* add/remove WLAN_BSSID_EX.IEs's ERP ie -* set WLAN_BSSID_EX.SupportedRates -* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie -*/ -#ifdef CONFIG_AP_MODE -void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) +#ifdef CONFIG_CMD_DISP +u8 set_stakey_hdl(struct _ADAPTER *a, struct set_stakey_parm *key, + enum phl_cmd_type cmd_type, u32 cmd_timeout) { - u8 network_type, rate_len, total_rate_len, remainder_rate_len; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - u8 erpinfo = 0x4; + struct sta_priv *pstapriv = &a->stapriv; + struct sta_info *sta; + int err = 0; + u8 ret = H2C_SUCCESS; + u8 spp = 0; - if (ch >= 36) { - network_type = WIRELESS_11A; - total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; - rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); - #ifdef CONFIG_80211AC_VHT - /* if channel in 5G band, then add vht ie . */ - if ((pmlmepriv->htpriv.ht_option == _TRUE) - && REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) - && is_supported_vht(padapter->registrypriv.wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { - if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv) - || pmlmepriv->ori_vht_en) - rtw_vht_ies_attach(padapter, pnetwork); - } - #endif + + sta = rtw_get_stainfo(pstapriv, key->addr); + if (!sta) { + RTW_ERR("%s: sta %pM not found\n", __func__, key->addr); + ret = H2C_REJECTED; + goto exit; + } + + a->mlmeextpriv.mlmext_info.enc_algo = key->algorithm; + + if (key->algorithm == _NO_PRIVACY_) { + RTW_INFO("%s: del all key for %pM for _NO_PRIVACY_\n", + __func__, key->addr); + err = rtw_hw_del_all_key(a, sta, PHL_CMD_DIRECTLY, 0); } else { - network_type = 0; - total_rate_len = 0; - if (padapter->registrypriv.wireless_mode & WIRELESS_11B) { - network_type |= WIRELESS_11B; - total_rate_len += IEEE80211_CCK_RATE_LEN; - } - if (padapter->registrypriv.wireless_mode & WIRELESS_11G) { - network_type |= WIRELESS_11G; - total_rate_len += IEEE80211_NUM_OFDM_RATESLEN; - } - rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); - #ifdef CONFIG_80211AC_VHT - rtw_vht_ies_detach(padapter, pnetwork); - #endif + RTW_INFO("%s: set %s key for %pM, kid:%d algo:%s\n", + __func__, key->gk?"group":"pairwise", + key->addr, key->keyid, + security_type_str(key->algorithm)); + if (amsdu_spp_enable(a, key->algorithm) == _SUCCESS) + spp = 1; +#ifdef CONFIG_WAPI_SUPPORT + if(key->algorithm == _SMS4_) + sta->phl_sta->wapi = true; +#endif + err = rtw_hw_add_key(a, sta, key->keyid, key->algorithm, + key->gk, key->key, spp, PHL_CMD_DIRECTLY, 0); } + if (!(key->gk)) + ATOMIC_INC(&sta->keytrack); /*CVE-2020-24587*/ + if (err) + RTW_ERR("%s: FAIL to set %s key for %pM, kid:%d algo:%s !\n", + __func__, key->gk?"group":"pairwise", + key->addr, key->keyid, + security_type_str(key->algorithm)); - rtw_set_supported_rate(pnetwork->SupportedRates, network_type); + ret = H2C_SUCCESS_RSP; - UpdateBrateTbl(padapter, pnetwork->SupportedRates); +exit: + return ret; +} +#else /* CONFIG_FSM */ +u8 set_stakey_hdl(struct _ADAPTER *a, u8 *pbuf) +{ + struct set_stakey_parm *key = (struct set_stakey_parm *)pbuf; + struct sta_priv *pstapriv = &a->stapriv; + struct sta_info *sta; + int err = 0; + u8 ret = H2C_SUCCESS; + u8 spp = 0; - if (total_rate_len > 8) { - rate_len = 8; - remainder_rate_len = total_rate_len - 8; - } else { - rate_len = total_rate_len; - remainder_rate_len = 0; + + sta = rtw_get_stainfo(pstapriv, key->addr); + if (!sta) { + RTW_ERR("%s: sta %pM not found\n", __func__, key->addr); + ret = H2C_REJECTED; + goto exit; } - rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len); + a->mlmeextpriv.mlmext_info.enc_algo = key->algorithm; - if (remainder_rate_len) - rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len); - else - rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_); +#ifdef CONFIG_LPS_PG + if (adapter_to_pwrctl(a)->lps_level == LPS_PG) + LPS_Leave(a, "SET_KEY"); +#endif - pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); + if (key->algorithm == _NO_PRIVACY_) { + RTW_INFO("%s: del all key for %pM for _NO_PRIVACY_\n", + __func__, key->addr); + err = rtw_hw_del_all_key(a, sta, PHL_CMD_DIRECTLY, 0); + } else { + RTW_INFO("%s: set %s key for %pM, kid:%d algo:%s\n", + __func__, key->gk?"group":"pairwise", + key->addr, key->keyid, + security_type_str(key->algorithm)); + if (amsdu_spp_enable(a, key->algorithm) == _SUCCESS) + spp = 1; + err = rtw_hw_add_key(a, sta, key->keyid, key->algorithm, + key->gk, key->key, spp, PHL_CMD_DIRECTLY, 0); + } + if (!(key->gk)) + ATOMIC_INC(&sta->keytrack); /*CVE-2020-24587*/ + + if (err) + RTW_ERR("%s: FAIL to set %s key for %pM, kid:%d algo:%s !\n", + __func__, key->gk?"group":"pairwise", + key->addr, key->keyid, + security_type_str(key->algorithm)); + + ret = H2C_SUCCESS_RSP; + +exit: + return ret; } -#endif /* CONFIG_AP_MODE */ +#endif -void rtw_join_done_chk_ch(_adapter *adapter, int join_res) +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) { -#define DUMP_ADAPTERS_STATUS 0 + struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct dvobj_priv *dvobj; - _adapter *iface; - struct mlme_priv *mlme; - struct mlme_ext_priv *mlmeext; - u8 u_ch, u_offset, u_bw; - int i, ret; + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); - dvobj = adapter_to_dvobj(adapter); + if (!psta) + return H2C_SUCCESS; - if (DUMP_ADAPTERS_STATUS) { - RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); - dump_adapters_status(RTW_DBGDUMP , dvobj); +#ifdef CONFIG_80211N_HT + if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || + ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { + /* pmlmeinfo->ADDBA_retry_count = 0; */ + /* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); */ + /* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */ + issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); + _set_timer(&psta->addba_retry_timer, ADDBA_TO); } +#ifdef CONFIG_TDLS + else if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && + (psta->htpriv.ht_option == _TRUE) && + (psta->htpriv.ampdu_enable == _TRUE)) { + issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); + _set_timer(&psta->addba_retry_timer, ADDBA_TO); + } +#endif /* CONFIG */ + else + psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); +#endif /* CONFIG_80211N_HT */ + return H2C_SUCCESS; +} - ret = rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset); - if (join_res >= 0 && ret <= 0) { - join_res = -1; - dump_adapters_status(RTW_DBGDUMP , dvobj); - rtw_warn_on(1); + +u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + u8 ret = _TRUE; + + psta = rtw_get_stainfo(pstapriv, pparm->addr); + if (!psta) + goto exit; + + if (pparm->status == 0) { + rtw_phl_start_rx_ba_session(padapter->dvobj->phl, psta->phl_sta, + pparm->preq.dialog_token, 3, + pparm->start_seq, 0, pparm->tid, + pparm->size); } - if (join_res >= 0) { -#ifdef CONFIG_MCC_MODE - /* MCC setting success, don't go to ch union process */ - if (rtw_hal_set_mcc_setting_join_done_chk_ch(adapter)) - return; -#endif /* CONFIG_MCC_MODE */ + preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid]; + ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, + pparm->status, pparm->size, + &(pparm->preq), 3, 50); - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - mlme = &iface->mlmepriv; - mlmeext = &iface->mlmeextpriv; +#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ + /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ + if (pparm->status == 0) { + preorder_ctrl->indicate_seq = pparm->start_seq; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); + #endif + } +#else + rtw_set_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack); + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, " + "start_seq:%d preorder_ctrl->rec_abba_rsp_ack =%lu " + "pparm->preq.dialog_token=%d pparm->preq.ba_p_set=%d\n" + , FUNC_ADPT_ARG(padapter) + , preorder_ctrl->tid + , preorder_ctrl->indicate_seq + , pparm->start_seq + , preorder_ctrl->rec_abba_rsp_ack + , pparm->preq.dialog_token + , pparm->preq.ba_p_set + ); + #endif +#endif - if (!iface || iface == adapter) - continue; + /* + * status = 0 means accept this addba req + * status = 37 means reject this addba req + */ + if (pparm->status == 0) { + preorder_ctrl->enable = _TRUE; + preorder_ctrl->ampdu_size = pparm->size; + } else if (pparm->status == 37) + preorder_ctrl->enable = _FALSE; -#ifdef CONFIG_AP_MODE - if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { - u8 ori_ch, ori_bw, ori_offset; - bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); +exit: + return H2C_SUCCESS; +} - if (is_grouped == _FALSE) { - /* handle AP which need to switch ch setting */ +u8 delba_hdl(struct _ADAPTER *a, unsigned char *pbuf) +{ + struct addBaReq_parm *parm = (struct addBaReq_parm *)pbuf; + struct sta_info *sta; - ori_ch = mlmeext->cur_channel; - ori_bw = mlmeext->cur_bwmode; - ori_offset = mlmeext->cur_ch_offset; - /* restore original bw, adjust bw by registry setting on target ch */ - mlmeext->cur_bwmode = mlme->ori_bw; - mlmeext->cur_channel = u_ch; - rtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(iface)) - rtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); - #endif + sta = rtw_get_stainfo(&a->stapriv, parm->addr); + if (!sta) { + RTW_WARN(FUNC_ADPT_FMT ": No STA(" MAC_FMT ") for DELBA!\n", + FUNC_ADPT_ARG(a), MAC_ARG(parm->addr)); + return H2C_SUCCESS; + } - rtw_chset_sync_chbw(adapter_to_chset(adapter) - , &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset - , &u_ch, &u_bw, &u_offset, 1, 0); + rtw_phl_stop_rx_ba_session(a->dvobj->phl, sta->phl_sta, parm->tid); - RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface) - , ori_ch, ori_bw, ori_offset - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + return H2C_SUCCESS; +} + +u8 chk_bmc_sleepq_cmd(_adapter *padapter) +{ + struct cmd_obj *cmd; + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(padapter)->cmdpriv); + u8 res = _SUCCESS; + + + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + res = _FAIL; + goto exit; + } + cmd->padapter = padapter; - rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + init_h2fwcmd_w_parm_no_parm_rsp(cmd, CMD_CHK_BMCSLEEPQ); - _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); + res = rtw_enqueue_cmd(pcmdpriv, cmd); - rtw_start_bss_hdl_after_chbw_decided(iface); +exit: + return res; +} - { - #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - u8 ht_option = 0; +u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags) +{ + struct cmd_obj *cmd; + struct Tx_Beacon_param *ptxBeacon_parm; + struct cmd_priv *pcmdpriv = &(adapter_to_dvobj(padapter)->cmdpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct submit_ctx sctx; + u8 res = _SUCCESS; + int len_diff = 0; - #ifdef CONFIG_80211N_HT - ht_option = mlme->htpriv.ht_option; - #endif + /*prepare cmd parameter*/ + ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param)); + if (ptxBeacon_parm == NULL) { + res = _FAIL; + goto exit; + } - rtw_cfg80211_ch_switch_notify(iface - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset - , ht_option, 0); - #endif - } - } + _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); - clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0xFF, NULL, _TRUE, 0); - } -#endif /* CONFIG_AP_MODE */ - } + len_diff = update_hidden_ssid( + ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_ + , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + ptxBeacon_parm->network.IELength += len_diff; -#ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0); -#endif - } else { - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - mlme = &iface->mlmepriv; - mlmeext = &iface->mlmeextpriv; - if (!iface || iface == adapter) - continue; -#ifdef CONFIG_AP_MODE - if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { - clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0xFF, NULL, _TRUE, 0); - } -#endif - } -#ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0); -#endif + /* need enqueue, prepare cmd_obj and enqueue */ + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + res = _FAIL; + rtw_mfree((u8 *)ptxBeacon_parm, sizeof(*ptxBeacon_parm)); + goto exit; } + cmd->padapter = padapter; - if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) { - RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - set_channel_bwmode(adapter, u_ch, u_offset, u_bw); - } + init_h2fwcmd_w_parm_no_rsp(cmd, ptxBeacon_parm, CMD_TX_BEACON); - rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); + if (flags & RTW_CMDF_WAIT_ACK) { + cmd->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } - if (join_res >= 0) - rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), BIT(adapter->iface_id), 1); + res = rtw_enqueue_cmd(pcmdpriv, cmd); - if (DUMP_ADAPTERS_STATUS) { - RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); - dump_adapters_status(RTW_DBGDUMP , dvobj); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _rtw_mutex_lock_interruptible(&pcmdpriv->sctx_mutex); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmd->sctx = NULL; + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); } +exit: + return res; } -int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) { -#ifdef CONFIG_CONCURRENT_MODE - bool chbw_allow = _TRUE; -#endif - bool connect_allow = _TRUE; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - u8 cur_ch, cur_bw, cur_ch_offset; - u8 u_ch, u_offset, u_bw; + struct rtw_evt_header *evt_hdr; + u8 *peventbuf; + void (*event_callback)(_adapter *dev, u8 *pbuf); + struct cmd_priv *pcmd_priv = &adapter_to_dvobj(padapter)->cmdpriv; - u_ch = cur_ch = pmlmeext->cur_channel; - u_bw = cur_bw = pmlmeext->cur_bwmode; - u_offset = cur_ch_offset = pmlmeext->cur_ch_offset; + if (pbuf == NULL) + goto _abort_event_; - if (!ch || !bw || !offset) { - connect_allow = _FALSE; - rtw_warn_on(1); - goto exit; + evt_hdr = (struct rtw_evt_header *)pbuf; + peventbuf = pbuf + sizeof(struct rtw_evt_header); + +#ifdef CHECK_EVENT_SEQ + /* checking event sequence... */ + if (evt_hdr->seq != (ATOMIC_READ(&pcmd_priv->event_seq) & 0x7f)) { + pcmd_priv->event_seq = (evt_hdr->seq + 1) & 0x7f; + goto _abort_event_; } +#endif - if (cur_ch == 0) { - connect_allow = _FALSE; - RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n" - , FUNC_ADPT_ARG(adapter), cur_ch); - rtw_warn_on(1); - goto exit; + /* checking if event code is valid */ + if (evt_hdr->id >= EVT_ID_MAX) { + goto _abort_event_; } - RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); -#ifdef CONFIG_CONCURRENT_MODE - { - struct dvobj_priv *dvobj; - _adapter *iface; - struct mlme_priv *mlme; - struct mlme_ext_priv *mlmeext; - struct mi_state mstate; - int i; + /* checking if event size match the event parm size */ + if ((wlanevents[evt_hdr->id].parmsize != 0) && + (wlanevents[evt_hdr->id].parmsize != evt_hdr->len)) { - dvobj = adapter_to_dvobj(adapter); + goto _abort_event_; - rtw_mi_status_no_self(adapter, &mstate); - RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate) - , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); + } - if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { - /* consider linking STA? */ - goto connect_allow_hdl; - } + ATOMIC_INC(&pcmd_priv->event_seq); - if (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) { - dump_adapters_status(RTW_DBGDUMP , dvobj); - rtw_warn_on(1); - } - RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n" - , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + if (peventbuf) { + event_callback = wlanevents[evt_hdr->id].event_callback; + event_callback(padapter, (u8 *)peventbuf); + pcmd_priv->evt_done_cnt++; + } - /* chbw_allow? */ - chbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset - , u_ch, u_bw, u_offset); +_abort_event_: + return H2C_SUCCESS; - RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n" - , FUNC_ADPT_ARG(adapter), chbw_allow); +} -#ifdef CONFIG_MCC_MODE - /* check setting success, don't go to ch union process */ - if (rtw_hal_set_mcc_setting_chk_start_clnt_join(adapter, &u_ch, &u_bw, &u_offset, chbw_allow)) - goto exit; +u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) +{ +#ifdef CONFIG_AP_MODE + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + + /* for BC/MC Frames */ + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if (!psta_bmc) + return H2C_SUCCESS; + + if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { +#ifndef CONFIG_PCI_HCI + rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */ #endif + /* _rtw_spinlock_bh(&psta_bmc->sleep_q.lock); */ + _rtw_spinlock_bh(&pxmitpriv->lock); - if (chbw_allow == _TRUE) { - rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset); - rtw_warn_on(cur_ch != pmlmeext->cur_channel); - rtw_warn_on(cur_bw != pmlmeext->cur_bwmode); - rtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset); - goto connect_allow_hdl; - } + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); -#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT - /* chbw_allow is _FALSE, connect allow? */ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - mlme = &iface->mlmepriv; - mlmeext = &iface->mlmeextpriv; + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - if (check_fwstate(mlme, WIFI_STATION_STATE) - && check_fwstate(mlme, WIFI_ASOC_STATE) -#if defined(CONFIG_P2P) - && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE) -#endif - ) { - connect_allow = _FALSE; - break; - } - } -#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ + xmitframe_plist = get_next(xmitframe_plist); - if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4) - connect_allow = _FALSE; + rtw_list_delete(&pxmitframe->list); - RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n" - , FUNC_ADPT_ARG(adapter), connect_allow); + psta_bmc->sleepq_len--; + if (psta_bmc->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; - if (connect_allow == _FALSE) - goto exit; + pxmitframe->attrib.triggered = 1; -connect_allow_hdl: - /* connect_allow == _TRUE */ + if (xmitframe_hiq_filter(pxmitframe) == _TRUE) + pxmitframe->attrib.qsel = rtw_hal_get_qsel(padapter,QSLT_HIGH_ID);/* HIQ */ - if (chbw_allow == _FALSE) { - u_ch = cur_ch; - u_bw = cur_bw; - u_offset = cur_ch_offset; +#if 0 + _rtw_spinunlock_bh(&psta_bmc->sleep_q.lock); + if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + rtw_os_xmit_complete(padapter, pxmitframe); + _rtw_spinlock_bh(&psta_bmc->sleep_q.lock); +#endif + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); + } - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - mlme = &iface->mlmepriv; - mlmeext = &iface->mlmeextpriv; + /* _rtw_spinunlock_bh(&psta_bmc->sleep_q.lock); */ + _rtw_spinunlock_bh(&pxmitpriv->lock); - if (!iface || iface == adapter) - continue; + if (rtw_get_intf_type(padapter) != RTW_HCI_PCIE) { + /* check hi queue and bmc_sleepq */ + rtw_chk_hi_queue_cmd(padapter); + } + } +#endif - #ifdef CONFIG_AP_MODE - if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { - #ifdef CONFIG_SPCT_CH_SWITCH - if (1) - rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset); - else - #endif - rtw_sta_flush(iface, _FALSE); + return H2C_SUCCESS; +} + +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) +{ + /*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/ + if (send_beacon(padapter) == _FAIL) { + RTW_INFO("issue_beacon, fail!\n"); + return H2C_PARAMETERS_ERROR; + } + + /* tx bc/mc frames after update TIM */ + chk_bmc_sleepq_hdl(padapter, NULL); + return H2C_SUCCESS; +} - rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0); - set_fwstate(mlme, WIFI_OP_CH_SWITCHING); - } else - #endif /* CONFIG_AP_MODE */ - if (check_fwstate(mlme, WIFI_STATION_STATE) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { - rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY); - rtw_indicate_disconnect(iface, 0, _FALSE); - rtw_free_assoc_resources(iface, _TRUE); - } - } - } +/* +* according to channel +* add/remove WLAN_BSSID_EX.IEs's ERP ie +* set WLAN_BSSID_EX.SupportedRates +* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie +*/ +void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) +{ + u8 network_type, rate_len, total_rate_len, remainder_rate_len; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + u8 erpinfo = 0x4; - #ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0); + if (ch >= 36) { + network_type = WLAN_MD_11A; + total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; + rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); + #ifdef CONFIG_80211AC_VHT + /* if channel in 5G band, then add vht ie . */ + if ((pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) + && is_supported_vht(padapter->registrypriv.wireless_mode) + && RFCTL_REG_EN_11AC(rfctl) + ) { + if (pmlmepriv->vhtpriv.upper_layer_setting) + rtw_reattach_vht_ies(padapter, pnetwork); + else if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)) + rtw_vht_ies_attach(padapter, pnetwork); + } + #endif + #ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ + #endif + } else { + network_type = 0; + total_rate_len = 0; + if (padapter->registrypriv.wireless_mode & WLAN_MD_11B) { + network_type |= WLAN_MD_11B; + total_rate_len += IEEE80211_CCK_RATE_LEN; + } + if (padapter->registrypriv.wireless_mode & WLAN_MD_11G) { + network_type |= WLAN_MD_11G; + total_rate_len += IEEE80211_NUM_OFDM_RATESLEN; + } + rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); + #ifdef CONFIG_80211AC_VHT + rtw_vht_ies_detach(padapter, pnetwork); + #endif + #ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ #endif } -#endif /* CONFIG_CONCURRENT_MODE */ -exit: + rtw_set_supported_rate(pnetwork->SupportedRates, network_type, ch); - if (connect_allow == _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); - *ch = u_ch; - *bw = u_bw; - *offset = u_offset; + UpdateBrateTbl(padapter, pnetwork->SupportedRates); -#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - { - u8 ht_option = 0; + if (total_rate_len > 8) { + rate_len = 8; + remainder_rate_len = total_rate_len - 8; + } else { + rate_len = total_rate_len; + remainder_rate_len = 0; + } -#ifdef CONFIG_80211N_HT - ht_option = adapter->mlmepriv.htpriv.ht_option; -#endif /* CONFIG_80211N_HT */ + rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len); - /* - when supplicant send the mlme frame, - the bss freq is updated by channel switch event. - */ - rtw_cfg80211_ch_switch_notify(adapter, - cur_ch, cur_bw, cur_ch_offset, ht_option, 1); - } -#endif - } + if (remainder_rate_len) + rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len); + else + rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_); - return connect_allow == _TRUE ? _SUCCESS : _FAIL; + pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); } void rtw_set_external_auth_status(_adapter *padapter, @@ -16279,19 +13122,11 @@ void rtw_set_external_auth_status(_adapter *padapter, #endif /* CONFIG_IOCTL_CFG80211 */ } -u8 rtw_iqk_hdl(_adapter *padapter, unsigned char *pbuf) -{ - rtw_hal_phydm_cal_trigger(padapter); - return H2C_SUCCESS; -} - u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf) { struct set_ch_parm *set_ch_parm; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(padapter); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - u8 u_ch, u_bw, u_offset; if (!pbuf) return H2C_PARAMETERS_ERROR; @@ -16302,85 +13137,368 @@ u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf) FUNC_NDEV_ARG(padapter->pnetdev), set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset); - /* update ch, bw, offset for all asoc STA ifaces */ - if (ifbmp_s) { - _adapter *iface; - int i; + pmlmeext->chandef.chan = set_ch_parm->ch; + pmlmeext->chandef.offset = set_ch_parm->ch_offset; + pmlmeext->chandef.bw = set_ch_parm->bw; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface || !(ifbmp_s & BIT(iface->iface_id))) + set_channel_bwmode(padapter, + set_ch_parm->ch, + set_ch_parm->ch_offset, + set_ch_parm->bw, + set_ch_parm->do_rfk); + rtw_rfctl_update_op_mode(dvobj_to_rfctl(dvobj), 0, 0); + + return H2C_SUCCESS; +} + +static void get_str_of_set_chplan_keys(char *buf, u8 buf_len, struct SetChannelPlan_param *param) +{ + char *pos = buf; + +#ifdef CONFIG_80211D + if (param->has_cisr) { + pos += snprintf(pos, buf_len - (pos - buf), "alpha2:"ALPHA2_FMT" %s" + , ALPHA2_ARG(param->cisr.alpha2), cis_status_str(param->cisr.status)); + } else +#endif + if (param->has_country) + pos += snprintf(pos, buf_len - (pos - buf), "alpha2:"ALPHA2_FMT, ALPHA2_ARG(param->country_ent.alpha2)); + else { + if (param->channel_plan == RTW_CHPLAN_UNSPECIFIED) + pos += snprintf(pos, buf_len - (pos - buf), "chplan:NA"); + else + pos += snprintf(pos, buf_len - (pos - buf), "chplan:0x%02X", param->channel_plan); + + #if CONFIG_IEEE80211_BAND_6GHZ + if (param->channel_plan_6g == RTW_CHPLAN_6G_UNSPECIFIED) + pos += snprintf(pos, buf_len - (pos - buf), " chplan_6g:NA"); + else + pos += snprintf(pos, buf_len - (pos - buf), " chplan_6g:0x%02X", param->channel_plan_6g); + #endif + } +} + +#ifdef CONFIG_80211D +static bool rtw_chplan_rtk_priv_req_prehdl_country_ie(_adapter *adapter, struct SetChannelPlan_param *param, const char *caller) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + int i; + bool effected = 1; + +#ifdef CONFIG_RTW_DEBUG + if (rtw_drv_log_level >= _DRV_DEBUG_) { + RTW_PRINT("%s cisr before\n", caller); + dump_country_ie_slave_records(RTW_DBGDUMP, rfctl, 0); + } +#endif + + if (param->inr == RTW_REGD_SET_BY_USER + && rfctl->effected_cisr_id != CONFIG_IFACE_NUMBER + ) { + /* country IE setting is applied, user setting is only recorded but not applied */ + effected = 0; + goto exit; + } + + if (param->inr == RTW_REGD_SET_BY_COUNTRY_IE) { + struct country_ie_slave_record ori_cisr = rfctl->cisr[adapter->iface_id]; + struct country_ie_slave_record ori_ecisr; + u8 ori_ecisr_id = rfctl->effected_cisr_id; + u8 new_ecisr_id = CONFIG_IFACE_NUMBER; + u8 status_score[] = { /* conservative policy */ + [COUNTRY_IE_SLAVE_UNKNOWN] = 3, + [COUNTRY_IE_SLAVE_OPCH_NOEXIST] = 2, + [COUNTRY_IE_SLAVE_APPLICABLE] = 1, + }; + char buf[32]; + + if (_rtw_memcmp(&rfctl->cisr[adapter->iface_id], ¶m->cisr, sizeof(param->cisr)) == _TRUE) { + /* record no change */ + effected = 0; + goto exit; + } + + if (ori_ecisr_id != CONFIG_IFACE_NUMBER) + _rtw_memcpy(&ori_ecisr, &rfctl->cisr[ori_ecisr_id], sizeof(ori_ecisr)); + + _rtw_memcpy(&rfctl->cisr[adapter->iface_id], ¶m->cisr, sizeof(param->cisr)); + if ((ori_cisr.status == COUNTRY_IE_SLAVE_NOCOUNTRY + && rfctl->cisr[adapter->iface_id].status == COUNTRY_IE_SLAVE_NOCOUNTRY) + || (ori_cisr.status == COUNTRY_IE_SLAVE_UNKNOWN + && rfctl->cisr[adapter->iface_id].status == COUNTRY_IE_SLAVE_UNKNOWN) + ) { + /* will take no effect */ + effected = 0; + goto exit; + } + + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rfctl->cisr[i].status == COUNTRY_IE_SLAVE_NOCOUNTRY) continue; - - /* update STA mode ch/bw/offset */ - iface->mlmeextpriv.cur_channel = set_ch_parm->ch; - iface->mlmeextpriv.cur_bwmode = set_ch_parm->bw; - iface->mlmeextpriv.cur_ch_offset = set_ch_parm->ch_offset; - /* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */ - iface->mlmepriv.cur_network.network.Configuration.DSConfig = set_ch_parm->ch; + if (new_ecisr_id == CONFIG_IFACE_NUMBER + /* high score */ + || status_score[rfctl->cisr[i].status] > status_score[rfctl->cisr[new_ecisr_id].status] + /* same score, prefer the same alpha2 as current effected(same score) one */ + || (status_score[rfctl->cisr[i].status] == status_score[rfctl->cisr[new_ecisr_id].status] + && ori_ecisr_id != CONFIG_IFACE_NUMBER + && rfctl->cisr[ori_ecisr_id].status == rfctl->cisr[new_ecisr_id].status + && _rtw_memcmp(rfctl->cisr[ori_ecisr_id].alpha2, rfctl->cisr[new_ecisr_id].alpha2, 2) == _FALSE + && _rtw_memcmp(rfctl->cisr[ori_ecisr_id].alpha2, rfctl->cisr[i].alpha2, 2) == _TRUE) + ) + new_ecisr_id = i; + } + + rfctl->effected_cisr_id = new_ecisr_id; + + if (rfctl->effected_cisr_id == CONFIG_IFACE_NUMBER) { + /* no country IE setting */ + const char *alpha2; + + if (strncmp(rfctl->user_alpha2, "\x00\x00", 2) != 0) { + /* restore to user setting */ + param->inr = RTW_REGD_SET_BY_USER; + alpha2 = rfctl->user_alpha2; + param->channel_plan = rfctl->user_ChannelPlan; + #if CONFIG_IEEE80211_BAND_6GHZ + param->channel_plan_6g = rfctl->user_chplan_6g; + #endif + } else { + /* restore to init setting */ + param->inr = RTW_REGD_SET_BY_INIT; + alpha2 = rfctl->init_alpha2; + param->channel_plan = rfctl->init_ChannelPlan; + #if CONFIG_IEEE80211_BAND_6GHZ + param->channel_plan_6g = rfctl->init_chplan_6g; + #endif + } + + if (IS_ALPHA2_UNSPEC(alpha2) || IS_ALPHA2_WORLDWIDE(alpha2)) + param->has_country = 0; + else if (rtw_get_chplan_from_country(alpha2, ¶m->country_ent)) { + param->channel_plan = param->country_ent.chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + param->channel_plan_6g = param->country_ent.chplan_6g; + #endif + param->has_country = 1; + } else { + RTW_WARN("%s unexpected country_code:\"%c%c\", set to \"00\"\n", caller, alpha2[0], alpha2[1]); + rtw_warn_on(1); + rtw_get_chplan_worldwide(¶m->country_ent); + param->channel_plan = param->country_ent.chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + param->channel_plan_6g = param->country_ent.chplan_6g; + #endif + param->has_country = 1; + } + param->has_cisr = 0; + + get_str_of_set_chplan_keys(buf, 32, param); + RTW_INFO("%s restore inr:%s %s\n", caller, regd_inr_str(param->inr), buf); + } + else { + /* has country IE setting */ + if (ori_ecisr_id != CONFIG_IFACE_NUMBER) { + /* has country IE setting originally */ + if (_rtw_memcmp(&ori_ecisr, &rfctl->cisr[new_ecisr_id], sizeof(ori_ecisr)) == _TRUE) { + /* same record content, no effect */ + effected = 0; + goto exit; + } + } + rtw_get_chplan_from_cisrs(rfctl, ¶m->country_ent, caller); + param->channel_plan = param->country_ent.chplan; + #if CONFIG_IEEE80211_BAND_6GHZ + param->channel_plan_6g = param->country_ent.chplan_6g; + #endif + param->has_country = 1; + param->has_cisr = 0; + + get_str_of_set_chplan_keys(buf, 32, param); + RTW_INFO("%s trigger inr:%s %s\n", caller, regd_inr_str(param->inr), buf); } } - - LeaveAllPowerSaveModeDirect(padapter); - - set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw); - rtw_mi_get_ch_setting_union(padapter, &u_ch, &u_bw, &u_offset); - rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw); - rtw_rfctl_update_op_mode(dvobj_to_rfctl(dvobj), 0, 0); - - return H2C_SUCCESS; +exit: +#ifdef CONFIG_RTW_DEBUG + if (rtw_drv_log_level >= _DRV_DEBUG_) { + RTW_PRINT("%s cisr after\n", caller); + dump_country_ie_slave_records(RTW_DBGDUMP, rfctl, 0); + } +#endif + + return effected; +} +#endif /* CONFIG_80211D */ + +static bool rtw_chplan_rtk_priv_req_prehdl_domain_code(_adapter *adapter, struct SetChannelPlan_param *param, const char *caller) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + /* disallow invalid input */ + if ((param->channel_plan != RTW_CHPLAN_UNSPECIFIED + && !rtw_is_channel_plan_valid(param->channel_plan)) + ) { + RTW_WARN("%s invalid chplan:0x%02X\n", caller, param->channel_plan); + return _FAIL; + } + + #if CONFIG_IEEE80211_BAND_6GHZ + if (param->channel_plan_6g != RTW_CHPLAN_6G_UNSPECIFIED + && !rtw_is_channel_plan_6g_valid(param->channel_plan_6g) + ) { + RTW_WARN("%s invalid chplan_6g:0x%02X\n", caller, param->channel_plan_6g); + return _FAIL; + } + #endif + + /* use original value when unspecified */ + if (param->channel_plan == RTW_CHPLAN_UNSPECIFIED) + param->channel_plan = rfctl->ChannelPlan; + #if CONFIG_IEEE80211_BAND_6GHZ + if (param->channel_plan_6g == RTW_CHPLAN_6G_UNSPECIFIED) + param->channel_plan_6g = rfctl->chplan_6g; + #endif + + return _SUCCESS; +} + +static void rtw_chplan_rtk_priv_req_prehdl_country_ent(struct SetChannelPlan_param *param) +{ + if (!param->has_country) { + u8 chplan_6g = RTW_CHPLAN_6G_NULL; + + #if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = param->channel_plan_6g; + #endif + + if (rtw_chplan_ids_is_world_wide(param->channel_plan, chplan_6g)) + rtw_get_chplan_worldwide(¶m->country_ent); + else { + SET_UNSPEC_ALPHA2(param->country_ent.alpha2); + param->country_ent.edcca_mode_2g_override = RTW_EDCCA_DEF; + #if CONFIG_IEEE80211_BAND_5GHZ + param->country_ent.edcca_mode_5g_override = RTW_EDCCA_DEF; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + param->country_ent.edcca_mode_6g_override = RTW_EDCCA_DEF; + #endif + param->country_ent.txpwr_lmt_override = TXPWR_LMT_DEF; + #if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + param->country_ent.proto_en = CHPLAN_PROTO_EN_ALL; + #endif + } + param->has_country = 1; + } } u8 rtw_set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) { struct SetChannelPlan_param *param; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + bool effected = 1; + char buf[32]; + enum rtw_regd_inr ori_inr; +#ifdef CONFIG_IOCTL_CFG80211 + struct get_chplan_resp *chplan; +#endif if (!pbuf) return H2C_PARAMETERS_ERROR; param = (struct SetChannelPlan_param *)pbuf; + ori_inr = param->inr; - if (param->regd_src == REGD_SRC_RTK_PRIV - && !rtw_is_channel_plan_valid(param->channel_plan)) - return H2C_PARAMETERS_ERROR; + get_str_of_set_chplan_keys(buf, 32, param); + RTW_INFO("%s iface_id:%u src:%s inr:%s %s\n", __func__, padapter->iface_id + , regd_src_str(param->regd_src), regd_inr_str(param->inr), buf); -#ifdef CONFIG_REGD_SRC_FROM_OS - if (rfctl->regd_src == REGD_SRC_OS) - rtw_mfree((void *)rfctl->country_ent, sizeof(struct country_chplan)); -#endif + /* check input parameter */ + if (param->regd_src == REGD_SRC_RTK_PRIV) { + #ifdef CONFIG_80211D + effected = rtw_chplan_rtk_priv_req_prehdl_country_ie(padapter, param, __func__); + #endif - rfctl->regd_src = param->regd_src; - rfctl->country_ent = param->country_ent; - rfctl->ChannelPlan = param->channel_plan; + if (rtw_chplan_rtk_priv_req_prehdl_domain_code(padapter, param, __func__) != _SUCCESS) + return H2C_PARAMETERS_ERROR; + + rtw_chplan_rtk_priv_req_prehdl_country_ent(param); + } + + rtw_warn_on(!param->has_country); + + if (param->inr == RTW_REGD_SET_BY_USER) { + rfctl->user_alpha2[0] = param->country_ent.alpha2[0]; + rfctl->user_alpha2[1] = param->country_ent.alpha2[1]; + rfctl->user_ChannelPlan = param->channel_plan; + #if CONFIG_IEEE80211_BAND_6GHZ + rfctl->user_chplan_6g = param->channel_plan_6g; + #endif + } + + if (!effected) + goto exit; + rfctl->regd_src = param->regd_src; + rfctl->regd_inr = param->inr; + rfctl->alpha2[0] = param->country_ent.alpha2[0]; + rfctl->alpha2[1] = param->country_ent.alpha2[1]; + rfctl->edcca_mode_2g_override = param->country_ent.edcca_mode_2g_override; +#if CONFIG_IEEE80211_BAND_5GHZ + rfctl->edcca_mode_5g_override = param->country_ent.edcca_mode_5g_override; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + rfctl->edcca_mode_6g_override = param->country_ent.edcca_mode_6g_override; +#endif #if CONFIG_TXPWR_LIMIT - rtw_txpwr_init_regd(rfctl); + rfctl->txpwr_lmt_override = param->country_ent.txpwr_lmt_override; +#endif +#if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + rfctl->proto_en = param->country_ent.proto_en; +#endif + rfctl->ChannelPlan = param->channel_plan; +#if CONFIG_IEEE80211_BAND_6GHZ + rfctl->chplan_6g = param->channel_plan_6g; #endif - rtw_rfctl_chplan_init(padapter); + rtw_edcca_mode_update(rfctl_to_dvobj(rfctl)); + rtw_update_phl_edcca_mode(padapter); - rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE); + rtw_rfctl_chplan_init(dvobj); #ifdef CONFIG_IOCTL_CFG80211 - rtw_regd_apply_flags(adapter_to_wiphy(padapter)); + if (rfctl->regd_src != REGD_SRC_OS) + rtw_chset_hook_os_channels(rfctl); + + if (rtw_get_chplan_cmd(padapter, RTW_CMDF_DIRECTLY, &chplan) == _SUCCESS) { + if (!param->rtnl_lock_needed) + rtw_regd_change_complete_sync(adapter_to_wiphy(padapter), chplan, 0); + else + rtw_warn_on(rtw_regd_change_complete_async(adapter_to_wiphy(padapter), chplan) != _SUCCESS); + } else + rtw_warn_on(1); #endif rtw_nlrtw_reg_change_event(padapter); - if (GET_HAL_DATA(padapter)->txpwr_limit_loaded - && rtw_get_hw_init_completed(padapter)) - rtw_hal_update_txpwr_level(padapter); + #ifdef CONFIG_LPS + LPS_Leave(padapter, "SET_CHPLAN"); + #endif + + if (rtw_phl_get_pwr_lmt_en(GET_PHL_INFO(rfctl_to_dvobj(rfctl)), padapter->phl_role->hw_band) + && rtw_hw_is_init_completed(dvobj)) + rtw_update_phl_txpwr_level(padapter); +exit: return H2C_SUCCESS; } u8 rtw_get_chplan_hdl(_adapter *padapter, unsigned char *pbuf) { struct get_channel_plan_param *param; - struct get_chplan_resp *resp; + struct get_chplan_resp *chplan; struct rf_ctl_t *rfctl; + int i; if (!pbuf) return H2C_PARAMETERS_ERROR; @@ -16388,29 +13506,44 @@ u8 rtw_get_chplan_hdl(_adapter *padapter, unsigned char *pbuf) rfctl = adapter_to_rfctl(padapter); param = (struct get_channel_plan_param *)pbuf; - resp = rtw_vmalloc(sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums); - if (!resp) + chplan = rtw_vmalloc(sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums); + if (!chplan) return H2C_CMD_FAIL; - resp->regd_src = rfctl->regd_src; + chplan->regd_src = rfctl->regd_src; + chplan->regd_inr = rfctl->regd_inr; - if (rfctl->country_ent) { - _rtw_memcpy(&resp->country_ent, rfctl->country_ent, sizeof(struct country_chplan)); - resp->has_country = 1; - } else - resp->has_country = 0; - - resp->channel_plan = rfctl->ChannelPlan; + chplan->alpha2[0] = rfctl->alpha2[0]; + chplan->alpha2[1] = rfctl->alpha2[1]; + + chplan->channel_plan = rfctl->ChannelPlan; +#if CONFIG_IEEE80211_BAND_6GHZ + chplan->chplan_6g = rfctl->chplan_6g; +#endif #if CONFIG_TXPWR_LIMIT - resp->regd_name = rfctl->regd_name; + for (i = 0; i < BAND_MAX; i++) + chplan->txpwr_lmt_name[i] = rtw_phl_get_pw_lmt_regu_type_str(GET_PHL_INFO(rfctl_to_dvobj(rfctl)), i); +#endif + chplan->edcca_mode_2g = rfctl->edcca_mode_2g; +#if CONFIG_IEEE80211_BAND_5GHZ + chplan->edcca_mode_5g = rfctl->edcca_mode_5g; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + chplan->edcca_mode_6g = rfctl->edcca_mode_6g; #endif #ifdef CONFIG_DFS_MASTER - resp->dfs_domain = rtw_rfctl_get_dfs_domain(rfctl); + chplan->dfs_domain = rtw_rfctl_get_dfs_domain(rfctl); #endif - resp->chset_num = rfctl->max_chan_nums; - _rtw_memcpy(resp->chset, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums); - *param->resp = resp; + chplan->proto_en = 0 + #if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + | rfctl->proto_en + #endif + ; + + chplan->chset_num = rfctl->max_chan_nums; + _rtw_memcpy(chplan->chset, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums); + *param->chplan = chplan; return H2C_SUCCESS; } @@ -16433,54 +13566,44 @@ u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) void csa_timer_hdl(void *FunctionContext) { +#if CONFIG_DFS _adapter *padapter = (_adapter *)FunctionContext; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 i, update_beacon = _FALSE; + u8 i; for (i = 0; i < dvobj->iface_nums; i++) { _adapter *iface; iface = dvobj->padapters[i]; if (!iface) continue; - if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) { - clr_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON); - update_beacon = _TRUE; + if (check_fwstate(&(iface->mlmepriv), WIFI_CSA_UPDATE_BEACON)) { + clr_fwstate(&(iface->mlmepriv), WIFI_CSA_UPDATE_BEACON); + RTW_INFO(FUNC_ADPT_FMT" wait beacons more than 70 seconds\n", FUNC_ADPT_ARG(iface)); + return; } } - - /* wait beacons more than 70 seconds */ - if(update_beacon == _TRUE) { - RTW_INFO("wait beacons more than 70 seconds\n"); - return ; - } - - if(rfctl->csa_ch == 0) { + + if (rfctl->csa_chandef.chan == 0) { RTW_INFO("channel switch done\n"); return ; } - + /* channel switch */ - if (rtw_set_csa_cmd(padapter) != _SUCCESS) { - rfctl->csa_ch = 0; - rfctl->csa_switch_cnt = 0; - rfctl->csa_ch_offset = 0; - rfctl->csa_ch_width = 0; - rfctl->csa_ch_freq_seg0 = 0; - rfctl->csa_ch_freq_seg1 = 0; - } + if (rtw_set_csa_cmd(padapter) != _SUCCESS) + reset_csa_param(rfctl); +#endif } u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf) { #if CONFIG_DFS +#ifndef RTW_PHL_TEST_FPGA struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - if (rfctl->csa_ch) - rtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter)); + if (rfctl->csa_chandef.chan) + rtw_dfs_ch_switch_hdl(adapter); +#endif #endif return H2C_SUCCESS; } @@ -16488,8 +13611,6 @@ u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf) u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) { #ifdef CONFIG_TDLS - _irqL irqL; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; #ifdef CONFIG_TDLS_CH_SW struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info; @@ -16504,7 +13625,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) u32 setchtime, resp_sleep = 0, wait_time; u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; u8 ret; - u8 doiqk; + u8 do_rfk; u64 tx_ra_bitmap = 0; if (!pbuf) @@ -16522,7 +13643,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) return H2C_REJECTED; } - /* _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */ + /* _rtw_spinlock_bh(&(ptdlsinfo->hdl_lock)); */ /* RTW_INFO("[%s] option:%d\n", __FUNCTION__, option); */ switch (option) { @@ -16535,14 +13656,14 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) rtw_pwr_wakeup(padapter); rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED); - RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); + RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->phl_sta->mac_addr)); /* Set TDLS sta rate. */ /* Update station supportRate */ - rtw_hal_update_sta_ra_info(padapter, ptdls_sta); - tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask; + update_sta_ra_info(padapter, ptdls_sta); + tx_ra_bitmap = ptdls_sta->phl_sta->ra_info.ramask; - if (pmlmeext->cur_channel > 14) { + if (pmlmeext->chandef.chan > 14) { if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_5N ; @@ -16565,12 +13686,9 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) if (tx_ra_bitmap & 0x0f) sta_band |= WIRELESS_11B; } - ptdls_sta->wireless_mode = sta_band; - rtw_hal_update_sta_wset(padapter, ptdls_sta); - /* Sta mode */ - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE); + ptdls_sta->phl_sta->wmode = sta_band; + - set_sta_rate(padapter, ptdls_sta); rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); break; } @@ -16583,10 +13701,10 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) case TDLS_CH_SW_RESP: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); if (ap_sta) - rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); + rtw_hal_macid_sleep(padapter, ap_sta->phl_sta->macid); issue_nulldata(padapter, NULL, 1, 3, 3); RTW_INFO("[TDLS ] issue tdls channel switch response\n"); @@ -16594,13 +13712,13 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */ /* then we just switch to AP's channel*/ - if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) { - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); + if (padapter->mlmeextpriv.chandef.chan == pchsw_info->off_ch_num) { + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); break; } if (ret == _SUCCESS) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_TO_OFF_CHNL); else RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n"); @@ -16609,20 +13727,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) pchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE; /* to collect IQK info of off-chnl */ - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); - set_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20); - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); - + do_rfk = _TRUE; + set_channel_bwmode(padapter, + pchsw_info->off_ch_num, + pchsw_info->ch_offset, + (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, + do_rfk); + + do_rfk = _FALSE; /* switch back to base-chnl */ - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); - set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); + set_channel_bwmode(padapter, + pmlmeext->chandef.chan, + pmlmeext->chandef.offset, + pmlmeext->chandef.bw, + do_rfk); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_START); pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE); @@ -16632,7 +13752,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) break; case TDLS_CH_SW_TO_OFF_CHNL: if (ap_sta) - rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); + rtw_hal_macid_sleep(padapter, ap_sta->phl_sta->macid); issue_nulldata(padapter, NULL, 1, 3, 3); if (padapter->registrypriv.wifi_spec == 0) { @@ -16644,9 +13764,9 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) { pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE); if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) { - if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, + if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->phl_sta->mac_addr, 0, 1, (padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_TO_BASE_CHNL); } } else { if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -16667,7 +13787,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) #endif if (option == TDLS_CH_SW_END_TO_BASE_CHNL) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_TO_BASE_CHNL); break; case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED: @@ -16679,15 +13799,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* Send unsolicited channel switch rsp. to peer */ _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE); } } - if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel, - pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) { + if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->chandef.chan, + pmlmeext->chandef.offset, pmlmeext->chandef.bw, ptdls_sta->ch_switch_time) == _SUCCESS) { if (ap_sta) - rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id); + rtw_hal_macid_wakeup(padapter, ap_sta->phl_sta->macid); issue_nulldata(padapter, NULL, 0, 3, 3); /* set ch sw monitor timer for responder */ if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -16703,7 +13823,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) case TDLS_TEARDOWN_STA_NO_WAIT: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE); @@ -16731,7 +13851,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) break; } - /* _exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */ + /* _rtw_spinunlock_bh(&(ptdlsinfo->hdl_lock)); */ return H2C_SUCCESS; #else @@ -16784,15 +13904,14 @@ int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx) } #endif - if (tx && (seq == 2) && (status == 0)) { - /* quere commit frame until external auth statue update */ + if (tx && (seq == 2) && (status == 0) && MLME_IS_AP(adapter)) { + /* queue confirm frame until external auth status update */ struct sta_priv *pstapriv = &adapter->stapriv; struct sta_info *psta = NULL; - _irqL irqL; psta = rtw_get_stainfo(pstapriv, GetAddr1Ptr(buf)); if (psta) { - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); if (psta->pauth_frame) { rtw_mfree(psta->pauth_frame, psta->auth_len); psta->pauth_frame = NULL; @@ -16804,7 +13923,7 @@ int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx) _rtw_memcpy(psta->pauth_frame, buf, len); psta->auth_len = len; } - _exit_critical_bh(&psta->lock, &irqL); + _rtw_spinunlock_bh(&psta->lock); ret = 2; } @@ -16816,14 +13935,12 @@ int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx) #endif /* CONFIG_IOCTL_CFG80211 */ } -/* Needs to confirm with FW the value of REG_RX_BEACON_LENGTH */ -u8 rtw_write_bcnlen_hdl(_adapter *padapter, u8 *pbuf) +char UNKNOWN_EVT[16] = "UNKNOWN_EVT"; +char *rtw_evt_name(struct rtw_evt_header *pev) { -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW - struct write_bcnlen_param *parm = (struct write_bcnlen_param *)pbuf; - u16 bcn_len = parm->bcn_len; + if (pev->id >= EVT_ID_MAX) + return UNKNOWN_EVT; - rtw_write16(padapter, REG_RX_BEACON_LENGTH + 2, bcn_len); -#endif - return H2C_SUCCESS; + return wlanevents[pev->id].name; } + diff --git a/core/rtw_mp.c b/core/rtw_mp.c index c092680..0a6435e 100644 --- a/core/rtw_mp.c +++ b/core/rtw_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,10 +18,6 @@ #include /* for RFHIGHPID */ #endif -#include "../hal/phydm/phydm_precomp.h" -#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A) - #include -#endif #ifdef CONFIG_MP_VHT_HW_TX_MODE #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X)) @@ -39,75 +35,9 @@ int rtfloor(float x) #endif #ifdef CONFIG_MP_INCLUDED -u32 read_macreg(_adapter *padapter, u32 addr, u32 sz) -{ - u32 val = 0; - - switch (sz) { - case 1: - val = rtw_read8(padapter, addr); - break; - case 2: - val = rtw_read16(padapter, addr); - break; - case 4: - val = rtw_read32(padapter, addr); - break; - default: - val = 0xffffffff; - break; - } - - return val; - -} - -void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz) -{ - switch (sz) { - case 1: - rtw_write8(padapter, addr, (u8)val); - break; - case 2: - rtw_write16(padapter, addr, (u16)val); - break; - case 4: - rtw_write32(padapter, addr, val); - break; - default: - break; - } - -} - -u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask) -{ - return rtw_hal_read_bbreg(padapter, addr, bitmask); -} - -void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val) -{ - rtw_hal_write_bbreg(padapter, addr, bitmask, val); -} - -u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask) -{ - return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask); -} - -void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val) +bool rtw_mp_is_cck_rate(u16 rate) { - rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val); -} - -u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr) -{ - return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask); -} - -void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val) -{ - _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val); + return ((rate & 0x1ff) <= _11M_RATE_) ? true : false; } static void _init_mp_priv_(struct mp_priv *pmp_priv) @@ -120,12 +50,12 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->channel = 1; pmp_priv->bandwidth = CHANNEL_WIDTH_20; - pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - pmp_priv->rateidx = RATE_1M; - pmp_priv->txpoweridx = 0x2A; - - pmp_priv->antenna_tx = ANTENNA_A; - pmp_priv->antenna_rx = ANTENNA_AB; + pmp_priv->prime_channel_offset = CHAN_OFFSET_NO_EXT; + //pmp_priv->rateidx = RATE_1M; + pmp_priv->txpoweridx = 0; + pmp_priv->antenna_tx = MP_ANTENNA_A; + pmp_priv->antenna_rx = MP_ANTENNA_A; + pmp_priv->antenna_trx = MP_ANTENNA_A; pmp_priv->check_mp_pkt = 0; @@ -149,6 +79,7 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->bloadefusemap = _FALSE; pmp_priv->brx_filter_beacon = _FALSE; pmp_priv->mplink_brx = _FALSE; + pmp_priv->mp_keep_btc_mode = BTC_MODE_MAX; pnetwork = &pmp_priv->mp_network.network; _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); @@ -166,10 +97,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) } -static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) +static void mp_init_xmit_attrib(struct mp_tx *pmptx, _adapter *padapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct pkt_attrib *pattrib; /* init xmitframe attribute */ @@ -199,34 +128,15 @@ static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) pattrib->qos_en = _FALSE; pattrib->pktlen = 1500; - - if (pHalData->rf_type == RF_2T2R) - pattrib->raid = RATEID_IDX_BGN_40M_2SS; - else - pattrib->raid = RATEID_IDX_BGN_40M_1SS; - -#ifdef CONFIG_80211AC_VHT - if (pHalData->rf_type == RF_1T1R) - pattrib->raid = RATEID_IDX_VHT_1SS; - else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) - pattrib->raid = RATEID_IDX_VHT_2SS; - else if (pHalData->rf_type == RF_3T3R) - pattrib->raid = RATEID_IDX_VHT_3SS; - else - pattrib->raid = RATEID_IDX_BGN_40M_1SS; -#endif } -s32 init_mp_priv(PADAPTER padapter) +s32 init_mp_priv(_adapter *padapter) { struct mp_priv *pmppriv = &padapter->mppriv; - PHAL_DATA_TYPE pHalData; - - pHalData = GET_HAL_DATA(padapter); _init_mp_priv_(pmppriv); pmppriv->papdater = padapter; - if (IS_HARDWARE_TYPE_8822C(padapter)) + if (0) //(IS_HARDWARE_TYPE_8822C(padapter)) pmppriv->mp_dm = 1;/* default enable dpk tracking */ else pmppriv->mp_dm = 0; @@ -234,13 +144,48 @@ s32 init_mp_priv(PADAPTER padapter) pmppriv->tx.stop = 1; pmppriv->bSetTxPower = 0; /*for manually set tx power*/ pmppriv->bTxBufCkFail = _FALSE; - pmppriv->pktInterval = 0; + pmppriv->pktInterval = 100; pmppriv->pktLength = 1000; pmppriv->bprocess_mp_mode = _FALSE; - pmppriv->efuse_update_file= _FALSE; + pmppriv->rtw_mp_tx_method = RTW_MP_PMACT_TX; + pmppriv->rtw_mp_cur_phy = 0; + pmppriv->rtw_mp_pmact_patt_idx = 0; + pmppriv->rtw_mp_pmact_ppdu_type = 0; + pmppriv->rtw_mp_dbcc = 0; + pmppriv->pre_refcw_cck_pwridxa = 0; + pmppriv->pre_refcw_cck_pwridxb = 0; + pmppriv->pre_refcw_ofdm_pwridxa = 0; + pmppriv->pre_refcw_ofdm_pwridxb = 0; + pmppriv->rtw_mp_data_bandwidth = CHANNEL_WIDTH_20; + + pmppriv->rtw_mp_trxsc = 0; + pmppriv->rtw_mp_stbc = 0; + pmppriv->rtw_mp_he_sigb = 0; + pmppriv->rtw_mp_he_sigb_dcm = 0; + pmppriv->rtw_mp_plcp_gi = 1; + pmppriv->rtw_mp_plcp_ltf = 0; + pmppriv->rtw_mp_plcp_tx_time = 0; + pmppriv->rtw_mp_plcp_tx_mode = 0; + pmppriv->rtw_mp_plcp_tx_user = 1; + pmppriv->rtw_mp_he_er_su_ru_106_en = 0; + pmppriv->rtw_mp_ru_tone = MP_RU_TONE_26; + + pmppriv->mp_plcp_useridx = 0; + pmppriv->mp_plcp_user[0].plcp_mcs = 0; + pmppriv->mp_plcp_user[0].aid = 0; + pmppriv->mp_plcp_user[0].coding = 0; + pmppriv->mp_plcp_user[0].dcm = 0; + pmppriv->mp_plcp_user[0].plcp_txlen = 1000; + pmppriv->mp_plcp_user[0].ru_alloc = 0; + pmppriv->mp_plcp_user[0].txbf = 0; + pmppriv->mp_plcp_user[0].pwr_boost_db = 0; + + pmppriv->btc_path = BTC_MODE_WL; + + _rtw_memset(pmppriv->st_giltf, 0, sizeof(struct rtw_mp_giltf_data)*5); mp_init_xmit_attrib(&pmppriv->tx, padapter); - +#if 0 switch (GET_HAL_RFPATH(padapter)) { case RF_1T1R: pmppriv->antenna_tx = ANTENNA_A; @@ -260,9 +205,7 @@ s32 init_mp_priv(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_ABCD; break; } - - pHalData->AntennaRxPath = pmppriv->antenna_rx; - pHalData->antenna_tx_path = pmppriv->antenna_tx; +#endif return _SUCCESS; } @@ -278,7 +221,7 @@ void free_mp_priv(struct mp_priv *pmp_priv) #if 0 static void PHY_IQCalibrate_default( - PADAPTER pAdapter, + _adapter *adapter, BOOLEAN bReCovery ) { @@ -286,14 +229,14 @@ static void PHY_IQCalibrate_default( } static void PHY_LCCalibrate_default( - PADAPTER pAdapter + _adapter *adapter ) { RTW_INFO("%s\n", __func__); } static void PHY_SetRFPathSwitch_default( - PADAPTER pAdapter, + _adapter *adapter, BOOLEAN bMain ) { @@ -301,246 +244,75 @@ static void PHY_SetRFPathSwitch_default( } #endif -void mpt_InitHWConfig(PADAPTER Adapter) -{ - PHAL_DATA_TYPE hal; - - hal = GET_HAL_DATA(Adapter); - - if (IS_HARDWARE_TYPE_8723B(Adapter)) { - /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ - /* TODO: A better solution is configure it according EFUSE during the run-time. */ - - phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */ - phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */ - phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */ - phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */ - phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */ - phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */ - phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */ - phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */ - phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */ - - /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */ - phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */ - phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */ - phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */ - - /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */ - phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/ - } else if (IS_HARDWARE_TYPE_8821(Adapter)) { - /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock) - <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/ - phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/ - phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/ - } else if (IS_HARDWARE_TYPE_8188ES(Adapter)) - phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ -#ifdef CONFIG_RTL8814A - else if (IS_HARDWARE_TYPE_8814A(Adapter)) - PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000); -#endif - -#ifdef CONFIG_RTL8812A - else if (IS_HARDWARE_TYPE_8812(Adapter)) { - rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000); - rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800)); - } -#endif - - +void mpt_InitHWConfig(_adapter *adapter) +{ #ifdef CONFIG_RTL8822B - else if (IS_HARDWARE_TYPE_8822B(Adapter)) { + if (IS_HARDWARE_TYPE_8822B(adapter)) { u32 tmp_reg = 0; - PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000); + rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0x2000); /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */ - phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e); - RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3)); - phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00); - RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord)); - phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038); - RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord)); + phy_set_bb_reg(adapter, 0x70, bMaskByte3, 0x0e); + RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(adapter, 0x70, bMaskByte3)); + phy_set_bb_reg(adapter, 0x1704, bMaskDWord, 0x0000ff00); + RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(adapter, 0x1704, bMaskDWord)); + phy_set_bb_reg(adapter, 0x1700, bMaskDWord, 0xc00f0038); + RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(adapter, 0x1700, bMaskDWord)); } #endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8821C - else if (IS_HARDWARE_TYPE_8821C(Adapter)) - PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000); + if (IS_HARDWARE_TYPE_8821C(adapter)) + rtw_write16(adapter, REG_RXFLTMAP1_8821C, 0x2000); #endif /* CONFIG_RTL8821C */ -#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) - else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) { - if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) { - RTW_INFO("%s() Active large power detection\n", __func__); - phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv)); - } - } -#endif #if defined(CONFIG_RTL8822C) - else if( IS_HARDWARE_TYPE_8822C(Adapter)) { - rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000); + if( IS_HARDWARE_TYPE_8822C(adapter)) { + rtw_write16(adapter, REG_RXFLTMAP1_8822C, 0x2000); /* 0x7D8[31] : time out enable when cca is not assert 0x60D[7:0] : time out value (Unit : us)*/ - rtw_write8(Adapter, 0x7db, 0xc0); - RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8)); - rtw_write8(Adapter, 0x60d, 0x0c); - RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d)); - phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1); - RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord)); + rtw_write8(adapter, 0x7db, 0xc0); + RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(adapter, 0x7d8)); + rtw_write8(adapter, 0x60d, 0x0c); + RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(adapter, 0x60d)); + phy_set_bb_reg(adapter, 0x1c44, BIT10, 0x1); + RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(adapter, 0x1c44, bMaskDWord)); } #endif #if defined(CONFIG_RTL8814B) - else if(IS_HARDWARE_TYPE_8814B(Adapter)) - { - PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000); - } -#endif -#if defined(CONFIG_RTL8723F) - /* todo: 8723F not verify yet */ - else if (IS_HARDWARE_TYPE_8723F(Adapter)) { - /* 8723F mac is similar with 8723D, - * but can't find 8723D here. - */ - } + if(IS_HARDWARE_TYPE_8814B(adapter)) + rtw_write16(adapter, REG_RXFLTMAP1_8814B, 0x2000); #endif + } -static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) +static void PHY_IQCalibrate(_adapter *padapter, u8 bReCovery) { - halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); + //halrf_iqk_trigger(adapter_to_phydm(padapter), bReCovery); } -static void PHY_LCCalibrate(PADAPTER padapter) +static void PHY_LCCalibrate(_adapter *padapter) { - halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv)); + //halrf_lck_trigger(adapter_to_phydm(padapter)); } -static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) +static u8 PHY_QueryRFPathSwitch(_adapter *padapter) { u8 bmain = 0; -/* - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - bmain = PHY_QueryRFPathSwitch_8723B(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - bmain = PHY_QueryRFPathSwitch_8188E(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - bmain = PHY_QueryRFPathSwitch_8814A(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - bmain = PHY_QueryRFPathSwitch_8812A(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - bmain = PHY_QueryRFPathSwitch_8192E(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - bmain = PHY_QueryRFPathSwitch_8703B(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - bmain = PHY_QueryRFPathSwitch_8188F(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) { -#ifdef CONFIG_RTL8188GTV - bmain = PHY_QueryRFPathSwitch_8188GTV(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - bmain = PHY_QueryRFPathSwitch_8822B(padapter); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - bmain = PHY_QueryRFPathSwitch_8723D(padapter); -#endif - } else -*/ - if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - bmain = phy_query_rf_path_switch_8821c(padapter); -#endif - } return bmain; } -static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) { - - PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); - struct dm_struct *phydm = &hal->odmpriv; +static void PHY_SetRFPathSwitch(_adapter *padapter , BOOLEAN bMain) { - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - phy_set_rf_path_switch_8723b(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - phy_set_rf_path_switch_8188e(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - phy_set_rf_path_switch_8814a(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - phy_set_rf_path_switch_8812a(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - phy_set_rf_path_switch_8192e(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - phy_set_rf_path_switch_8703b(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) { -#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) - phy_set_rf_path_switch_8188f(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8192F(padapter)) { -#ifdef CONFIG_RTL8192F - phy_set_rf_path_switch_8192f(padapter, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - phy_set_rf_path_switch_8822b(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - phy_set_rf_path_switch_8723d(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - phy_set_rf_path_switch_8821c(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8822C(padapter)) { -#ifdef CONFIG_RTL8822C - phy_set_rf_path_switch_8822c(phydm, bMain); -#endif - } else if (IS_HARDWARE_TYPE_8814B(padapter)) { -#ifdef CONFIG_RTL8814B - /* phy_set_rf_path_switch_8814b(phydm, bMain); */ -#endif - } else if (IS_HARDWARE_TYPE_8723F(padapter)) { -#ifdef CONFIG_RTL8723F - phy_set_rf_path_switch_8723f(phydm, bMain); -#endif - } } -static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) { +static void phy_switch_rf_path_set(_adapter *padapter , u8 *prf_set_State) { #ifdef CONFIG_RTL8821C - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *p_dm = &pHalData->odmpriv; + struct dm_struct *phydm = adapter_to_phydm(padapter); if (IS_HARDWARE_TYPE_8821C(padapter)) { - config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c); + config_phydm_set_ant_path(phydm, *prf_set_State, phydm->current_ant_num_8821c); /* Do IQK when switching to BTG/WLG, requested by RF Binson */ if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG) PHY_IQCalibrate(padapter, FALSE); @@ -550,106 +322,49 @@ static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) { } -#ifdef CONFIG_ANTENNA_DIVERSITY -u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 cur_ant, change_ant; - - if (!pHalData->AntDivCfg) - return _FALSE; - /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/ - change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT; - - RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); - rtw_antenna_select_cmd(padapter, change_ant, _FALSE); - - return _TRUE; -} -#endif - s32 MPT_InitializeAdapter( - PADAPTER pAdapter, + _adapter *adapter, u8 Channel ) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); s32 rtStatus = _SUCCESS; - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; - u32 ledsetting; + PMPT_CONTEXT pMptCtx = &adapter->mppriv.mpt_ctx; + /*u32 ledsetting;*/ pMptCtx->bMptDrvUnload = _FALSE; pMptCtx->bMassProdTest = _FALSE; pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */ pMptCtx->h2cReqNum = 0x0; /* init for BT MP */ -#if defined(CONFIG_RTL8723B) - pMptCtx->bMPh2c_timeout = _FALSE; - pMptCtx->MptH2cRspEvent = _FALSE; - pMptCtx->MptBtC2hEvent = _FALSE; - _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0); - rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter); -#endif - - mpt_InitHWConfig(pAdapter); - -#ifdef CONFIG_RTL8723B - rtl8723b_InitAntenna_Selection(pAdapter); - if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - - /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/ - phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0); - PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/ - - if (pHalData->PackageType == PACKAGE_DEFAULT) - phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); - else - phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E); - - } - /*set ant to wifi side in mp mode*/ - rtw_write16(pAdapter, 0x870, 0x300); - rtw_write16(pAdapter, 0x860, 0x110); -#endif + mpt_InitHWConfig(adapter); pMptCtx->bMptWorkItemInProgress = _FALSE; pMptCtx->CurrMptAct = NULL; pMptCtx->mpt_rf_path = RF_PATH_A; /* ------------------------------------------------------------------------- */ /* Don't accept any packets */ - rtw_write32(pAdapter, REG_RCR, 0); - - /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */ - /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */ + //rtw_write32(adapter, REG_RCR, 0); - /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */ - ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); + /* ledsetting = rtw_read32(adapter, REG_LEDCFG0); */ + /* rtw_write32(adapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */ + /* rtw_write32(adapter, REG_LEDCFG0, 0x08080); */ + /*ledsetting = rtw_read32(adapter, REG_LEDCFG0);*/ - PHY_LCCalibrate(pAdapter); - PHY_IQCalibrate(pAdapter, _FALSE); - /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */ - PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */ + PHY_LCCalibrate(adapter); + PHY_IQCalibrate(adapter, _FALSE); + /* dm_check_txpowertracking(adapter_to_phydm(adapter)); */ /* trigger thermal meter */ - pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); - pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); - pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); - pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); - pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); -#ifdef CONFIG_RTL8188E - rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0); - rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0); -#endif -#ifdef CONFIG_RTL8814A - if (IS_HARDWARE_TYPE_8814A(pAdapter)) { - pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0); - } -#endif + PHY_SetRFPathSwitch(adapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */ +#if 0 + pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(adapter, rOFDM0_XAAGCCore1, bMaskByte0); + pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(adapter, rOFDM0_XBAGCCore1, bMaskByte0); + pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(adapter, rOFDM0_RxDetector1, bMaskByte0); + pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(adapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(adapter, RF_PATH_B, RF_0x52, 0x000F0); +#endif return rtStatus; } @@ -658,7 +373,7 @@ MPT_InitializeAdapter( * * Overview: Extra DeInitialization for Mass Production Test. * - * Input: PADAPTER pAdapter + * Input: _adapter *adapter * * Output: NONE * @@ -672,31 +387,14 @@ MPT_InitializeAdapter( *---------------------------------------------------------------------------*/ void MPT_DeInitAdapter( - PADAPTER pAdapter + _adapter *adapter ) { - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; - + PMPT_CONTEXT pMptCtx = &adapter->mppriv.mpt_ctx; pMptCtx->bMptDrvUnload = _TRUE; -#if defined(CONFIG_RTL8723B) - _rtw_free_sema(&(pMptCtx->MPh2c_Sema)); - _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer); -#endif -#if defined(CONFIG_RTL8723B) - phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */ -#endif -#if 0 /* for Windows */ - PlatformFreeWorkItem(&(pMptCtx->MptWorkItem)); - - while (pMptCtx->bMptWorkItemInProgress) { - if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50)) - break; - } - NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock)); -#endif } -static u8 mpt_ProStartTest(PADAPTER padapter) +static u8 mpt_ProStartTest(_adapter *padapter) { PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx; @@ -712,127 +410,141 @@ static u8 mpt_ProStartTest(PADAPTER padapter) return _SUCCESS; } +void rtw_mp_cal_trigger(_adapter *padapter, u8 cal_tye) +{ + struct rtw_mp_cal_arg *mp_cal_arg = NULL; + struct mp_priv *pmppriv = &padapter->mppriv; + + mp_cal_arg = _rtw_malloc(sizeof(struct rtw_mp_cal_arg)); + if (mp_cal_arg) + _rtw_memset((void *)mp_cal_arg, 0, sizeof(struct rtw_mp_cal_arg)); + else { + RTW_ERR("%s,malloc fail ! ", __func__); + return; + } + mp_cal_arg->cal_type = cal_tye; + + if (cal_tye == RTW_MP_CAL_DPK_TRACK) { + if (rtw_mp_phl_calibration(padapter, + mp_cal_arg, + RTW_MP_CAL_CMD_TRIGGER_DPK_TRACKING)) + RTW_INFO("%s ok\n", __func__); + else + RTW_INFO("%s fail\n", __func__); + } else { + if (rtw_mp_phl_calibration(padapter, + mp_cal_arg, + RTW_MP_CAL_CMD_TRIGGER_CAL)) + RTW_INFO("%s ok\n", __func__); + else + RTW_INFO("%s fail\n", __func__); + } + if (mp_cal_arg) + _rtw_mfree(mp_cal_arg, sizeof(struct rtw_mp_cal_arg)); + + return; +} + +void rtw_mp_cal_capab(_adapter *padapter, u8 cal_tye, u8 benable) +{ + struct rtw_mp_cal_arg *mp_cal_arg = NULL; + struct mp_priv *pmppriv = &padapter->mppriv; + + mp_cal_arg = _rtw_malloc(sizeof(struct rtw_mp_cal_arg)); + if (mp_cal_arg) + _rtw_memset((void *)mp_cal_arg, 0, sizeof(struct rtw_mp_cal_arg)); + else { + RTW_ERR("%s,malloc fail ! ", __func__); + return; + } + + mp_cal_arg->cal_type = cal_tye; + mp_cal_arg->enable = benable; + + if (rtw_mp_phl_calibration(padapter, mp_cal_arg, RTW_MP_CAL_CMD_SET_CAPABILITY_CAL)) + RTW_INFO("%s ok\n", __func__); + else + RTW_INFO("%s fail\n", __func__); + + if (mp_cal_arg) + _rtw_mfree(mp_cal_arg, sizeof(struct rtw_mp_cal_arg)); + + return; +} + /* * General use */ -s32 SetPowerTracking(PADAPTER padapter, u8 enable) +s32 SetPowerTracking(_adapter *padapter, u8 enable) { - hal_mpt_SetPowerTracking(padapter, enable); + //hal_mpt_SetPowerTracking(padapter, enable); return 0; } -void GetPowerTracking(PADAPTER padapter, u8 *enable) +void GetPowerTracking(_adapter *padapter, u8 *enable) { - hal_mpt_GetPowerTracking(padapter, enable); + //hal_mpt_GetPowerTracking(padapter, enable); + return; } -void rtw_mp_trigger_iqk(PADAPTER padapter) +void rtw_mp_trigger_iqk(_adapter *padapter) { - PHY_IQCalibrate(padapter, _FALSE); + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_IQK); } -void rtw_mp_trigger_lck(PADAPTER padapter) +void rtw_mp_trigger_lck(_adapter *padapter) { - PHY_LCCalibrate(padapter); + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_LCK); } -void rtw_mp_trigger_dpk(PADAPTER padapter) +void rtw_mp_trigger_dpk(_adapter *padapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; - - halrf_dpk_trigger(pDM_Odm); + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_DPK); } -static void init_mp_data(PADAPTER padapter) +void rtw_mp_trigger_tssi(_adapter *padapter) { - u8 v8; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; - - /*disable BCN*/ -#ifdef CONFIG_PROTSEL_PORT - rtw_hal_hw_port_disable(padapter); -#else - v8 = rtw_read8(padapter, REG_BCN_CTRL); - v8 &= ~EN_BCN_FUNCTION; - rtw_write8(padapter, REG_BCN_CTRL, v8); -#endif - - pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_TSSI); } - -void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type) +void rtw_mp_trigger_ch_rfk(_adapter *padapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; - u32 rf_ability; - - padapter->mppriv.tssitrk_on = trk_type == 3; + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_CHL_RFK); +} - if (trk_type == 0) { /* thermal PwrTrk off*/ - struct txpwrtrack_cfg c; - u8 chnl = 0 ; +void rtw_mp_trigger_dack(_adapter *padapter) +{ + rtw_mp_cal_trigger(padapter, RTW_MP_CAL_DACK); +} - RTW_INFO("in Thermal tracking off\n"); - rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK; - halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); - halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type); - halrf_set_pwr_track(pDM_Odm, FALSE); - pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type; - if (IS_HARDWARE_TYPE_8822C(padapter)) - padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */ - else - padapter->mppriv.mp_dm = 0; - - _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg)); - configure_txpower_track(pDM_Odm, &c); - odm_clear_txpowertracking_state(pDM_Odm); - if (*c.odm_tx_pwr_track_set_pwr) { - if (pDM_Odm->support_ic_type == ODM_RTL8188F) - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl); - else if (pDM_Odm->support_ic_type == ODM_RTL8723D) { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); - SetTxPower(padapter); - } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl); - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl); - } else { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl); - } - } - return ; - } +static void init_mp_data(_adapter *padapter) +{ +#if 0 + struct dm_struct *phydm = adapter_to_phydm(padapter); - rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK; - halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); - halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type); - if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */ - halrf_set_pwr_track(pDM_Odm, TRUE); - else - halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */ - pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type; - padapter->mppriv.mp_dm = 1; + /*disable BCN*/ + v8 = rtw_read8(padapter, REG_BCN_CTRL); + v8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, v8); + phydm->rf_calibrate_info.txpowertrack_control = _FALSE; +#endif } - -u32 mp_join(PADAPTER padapter, u8 mode) +u32 mp_join(_adapter *padapter, u8 mode) { WLAN_BSSID_EX bssid; struct sta_info *psta; u32 length; - _irqL irqL; s32 res = _SUCCESS; - + u8 i = 0; struct mp_priv *pmppriv = &padapter->mppriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *tgt_network = &pmlmepriv->cur_network; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); /* 1. initialize a new WLAN_BSSID_EX */ @@ -862,21 +574,37 @@ u32 mp_join(PADAPTER padapter, u8 mode) else bssid.Length = length; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) goto end_of_mp_start_test; /* init mp_start_test status */ - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { - rtw_disassoc_cmd(padapter, 500, 0); - rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); + for (i = 0; i < dvobj->iface_nums; i++) { + _adapter *iface = NULL; + struct mlme_priv *buddy_mlmepriv; + + iface = dvobj->padapters[i]; + buddy_mlmepriv = &iface->mlmepriv; + + if (iface == NULL) + continue; + if (rtw_is_adapter_up(iface) == _FALSE) + continue; + if (check_fwstate(buddy_mlmepriv, WIFI_ASOC_STATE) == _TRUE) { +#ifdef CONFIG_STA_CMD_DISPR + rtw_disassoc_cmd(iface, 500, RTW_CMDF_WAIT_ACK); +#else /* !CONFIG_STA_CMD_DISPR */ + rtw_disassoc_cmd(iface, 500, 0); + rtw_free_assoc_resources_cmd(iface, _TRUE, RTW_CMDF_WAIT_ACK); +#endif /* !CONFIG_STA_CMD_DISPR */ + rtw_indicate_disconnect(iface, 0, _FALSE); + } } + pmppriv->prev_fw_state = get_fwstate(pmlmepriv); /*pmlmepriv->fw_state = WIFI_MP_STATE;*/ init_fwstate(pmlmepriv, WIFI_MP_STATE); - set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); /* 3 2. create a new psta for mp driver */ @@ -893,12 +621,12 @@ u32 mp_join(PADAPTER padapter, u8 mode) goto end_of_mp_start_test; } if (mode == WIFI_FW_ADHOC_STATE) - set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); else set_fwstate(pmlmepriv, WIFI_STATION_STATE); /* 3 3. join psudo AdHoc */ tgt_network->join_res = 1; - tgt_network->aid = psta->cmn.aid = 1; + tgt_network->aid = psta->phl_sta->aid = 1; _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length); rtw_update_registrypriv_dev_network(padapter); @@ -911,23 +639,20 @@ u32 mp_join(PADAPTER padapter, u8 mode) end_of_mp_start_test: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); if (1) { /* (res == _SUCCESS) */ /* set MSR to WIFI_FW_ADHOC_STATE */ if (mode == WIFI_FW_ADHOC_STATE) { /* set msr to WIFI_FW_ADHOC_STATE */ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; - Set_MSR(padapter, (pmlmeinfo->state & 0x3)); rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; } else { - Set_MSR(padapter, WIFI_FW_STATION_STATE); - RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__, pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4], - pmppriv->network_macaddr[5]); + pmppriv->network_macaddr[5]); rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr); } @@ -936,47 +661,18 @@ u32 mp_join(PADAPTER padapter, u8 mode) return res; } /* This function initializes the DUT to the MP test mode */ -s32 mp_start_test(PADAPTER padapter) +s32 mp_start_test(_adapter *padapter) { struct mp_priv *pmppriv = &padapter->mppriv; -#ifdef CONFIG_PCI_HCI - PHAL_DATA_TYPE hal; -#endif s32 res = _SUCCESS; padapter->registrypriv.mp_mode = 1; + init_mp_priv(padapter); init_mp_data(padapter); -#ifdef CONFIG_RTL8814A - rtl8814_InitHalDm(padapter); -#endif /* CONFIG_RTL8814A */ -#ifdef CONFIG_RTL8812A - rtl8812_InitHalDm(padapter); -#endif /* CONFIG_RTL8812A */ -#ifdef CONFIG_RTL8723B - rtl8723b_InitHalDm(padapter); -#endif /* CONFIG_RTL8723B */ -#ifdef CONFIG_RTL8703B - rtl8703b_InitHalDm(padapter); -#endif /* CONFIG_RTL8703B */ -#ifdef CONFIG_RTL8192E - rtl8192e_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8188F - rtl8188f_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8188GTV - rtl8188gtv_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8188E - rtl8188e_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8723D - rtl8723d_InitHalDm(padapter); -#endif /* CONFIG_RTL8723D */ - +#if 0 #ifdef CONFIG_PCI_HCI - hal = GET_HAL_DATA(padapter); + hal = GET_PHL_COM(adapter_to_dvobj(padapter)); hal->pci_backdoor_ctrl = 0; rtw_pci_aspm_config(padapter); #endif @@ -1002,7 +698,7 @@ s32 mp_start_test(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_ABCD; break; } - +#endif mpt_ProStartTest(padapter); mp_join(padapter, WIFI_FW_ADHOC_STATE); @@ -1011,7 +707,7 @@ s32 mp_start_test(PADAPTER padapter) } /* ------------------------------------------------------------------------------ * This function change the DUT from the MP test mode into normal mode */ -void mp_stop_test(PADAPTER padapter) +void mp_stop_test(_adapter *padapter) { struct mp_priv *pmppriv = &padapter->mppriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -1019,14 +715,11 @@ void mp_stop_test(PADAPTER padapter) struct sta_info *psta; #ifdef CONFIG_PCI_HCI struct registry_priv *registry_par = &padapter->registrypriv; - PHAL_DATA_TYPE hal; #endif - _irqL irqL; - if (pmppriv->mode == MP_ON) { pmppriv->bSetTxPower = 0; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE) goto end_of_mp_stop_test; @@ -1050,251 +743,363 @@ void mp_stop_test(PADAPTER padapter) end_of_mp_stop_test: - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); -#ifdef CONFIG_PCI_HCI - hal = GET_HAL_DATA(padapter); +#if 0//def CONFIG_PCI_HCI + hal = GET_PHL_COM(adapter_to_dvobj(padapter)); hal->pci_backdoor_ctrl = registry_par->pci_aspm_config; rtw_pci_aspm_config(padapter); #endif - -#ifdef CONFIG_RTL8812A - rtl8812_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8723B - rtl8723b_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8703B - rtl8703b_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8192E - rtl8192e_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8188F - rtl8188f_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8188GTV - rtl8188gtv_InitHalDm(padapter); -#endif -#ifdef CONFIG_RTL8723D - rtl8723d_InitHalDm(padapter); -#endif } } -/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ -#if 0 -/* #ifdef CONFIG_USB_HCI */ -static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID) -{ - u8 eRFPath; - u32 rfReg0x26; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); - - - if (RateIdx < MPT_RATE_6M) /* CCK rate,for 88cu */ - rfReg0x26 = 0xf400; - else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */ - if ((4 == Channel) || (8 == Channel) || (12 == Channel)) - rfReg0x26 = 0xf000; - else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) - rfReg0x26 = 0xf400; - else - rfReg0x26 = 0x4f200; - } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) { - /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */ - - if (CHANNEL_WIDTH_20 == BandWidthID) { - if ((4 == Channel) || (8 == Channel)) - rfReg0x26 = 0xf000; - else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) - rfReg0x26 = 0xf400; - else - rfReg0x26 = 0x4f200; - } else { - if ((4 == Channel) || (8 == Channel)) - rfReg0x26 = 0xf000; - else if ((5 == Channel) || (7 == Channel)) - rfReg0x26 = 0xf400; - else - rfReg0x26 = 0x4f200; - } - } - for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++) - write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26); -} -#endif -/*----------------------------------------------------------------------------- - * Function: mpt_SwitchRfSetting - * - * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. - * - * Input: PADAPTER pAdapter - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. - * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. - * - *---------------------------------------------------------------------------*/ -#if 0 -static void mpt_SwitchRfSetting(PADAPTER pAdapter) +void SetChannel(_adapter *padapter) { - hal_mpt_SwitchRfSetting(pAdapter); +#ifdef CONFIG_MP_INCLUDED + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_CH_BW); +#else + //hal_mpt_SetChannel(adapter); +#endif } -/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ -/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ -static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) +void SetBandwidth(_adapter *padapter) { - hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14); -} +#ifdef CONFIG_MP_INCLUDED + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_CH_BW); +#else + //hal_mpt_SetBandwidth(adapter); #endif - -/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ - -/* - * SetChannel - * Description - * Use H2C command to change channel, - * not only modify rf register, but also other setting need to be done. - */ -void SetChannel(PADAPTER pAdapter) -{ - hal_mpt_SetChannel(pAdapter); -} - -/* - * Notice - * Switch bandwitdth may change center frequency(channel) - */ -void SetBandwidth(PADAPTER pAdapter) -{ - hal_mpt_SetBandwidth(pAdapter); - } -void SetAntenna(PADAPTER pAdapter) +void SetAntenna(_adapter *padapter) { - hal_mpt_SetAntenna(pAdapter); -} + mp_ant_path mp_trx_path = padapter->mppriv.antenna_trx; + u8 cfg_rf_path = RF_PATH_A; -int SetTxPower(PADAPTER pAdapter) + switch (mp_trx_path) { + case MP_ANTENNA_A: + cfg_rf_path = RF_PATH_A; + break; + case MP_ANTENNA_B: + cfg_rf_path = RF_PATH_B; + break; + case MP_ANTENNA_C: + cfg_rf_path = RF_PATH_C; + break; + case MP_ANTENNA_D: + cfg_rf_path = RF_PATH_D; + break; + case MP_ANTENNA_AB: + cfg_rf_path = RF_PATH_AB; + break; + case MP_ANTENNA_AC: + cfg_rf_path = RF_PATH_AC; + break; + case MP_ANTENNA_AD: + cfg_rf_path = RF_PATH_AD; + break; + case MP_ANTENNA_BC: + cfg_rf_path = RF_PATH_BC; + break; + case MP_ANTENNA_BD: + cfg_rf_path = RF_PATH_BD; + break; + case MP_ANTENNA_CD: + cfg_rf_path = RF_PATH_CD; + break; + case MP_ANTENNA_ABC: + cfg_rf_path = RF_PATH_ABC; + break; + case MP_ANTENNA_BCD: + cfg_rf_path = RF_PATH_BCD; + break; + case MP_ANTENNA_ABD: + cfg_rf_path = RF_PATH_ABD; + break; + case MP_ANTENNA_ACD: + cfg_rf_path = RF_PATH_ACD; + break; + case MP_ANTENNA_ABCD: + cfg_rf_path = RF_PATH_ABCD; + break; + default: + RTW_INFO("%s ,default Antenna Path A\n", __func__); + break; + } + + padapter->mppriv.antenna_trx = cfg_rf_path; + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_RF_TXRX_PATH); +} + +int rtw_mp_txpoweridx(_adapter *adapter) { + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &adapter->mppriv; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(adapter)); + u8 i = 0; - hal_mpt_SetTxPower(pAdapter); + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.txpwr_index = pmppriv->txpoweridx * TX_POWER_CODE_WORD_BASE; + + for (i = 0; i < tx_nss; i++) { + ptxpwr_arg.rfpath = i; + ptxpwr_arg.is_cck = rtw_mp_is_cck_rate(pmppriv->rateidx); + + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_TXPWR_INDEX); + } return _TRUE; } -void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) +s16 rtw_mp_get_pwr_refcw(_adapter *adapter, u8 rfpath, u8 is_cck) { - u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC; + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &adapter->mppriv; + s16 txpwr_refcw_idx; - TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff); - TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8); - TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16); + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + ptxpwr_arg.rfpath = rfpath; + ptxpwr_arg.is_cck = is_cck; - tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B); - write_bbreg(pAdapter, rFPGA0_TxGainStage, - (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC); + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_GET_TXPWR_REF_CW); + txpwr_refcw_idx = ptxpwr_arg.txpwr_index / TX_POWER_CODE_WORD_BASE; + + RTW_INFO("%s ,pwr ref cw: %d\n", __func__, txpwr_refcw_idx); + return txpwr_refcw_idx; } -void SetDataRate(PADAPTER pAdapter) +u16 rtw_mp_get_pwr_ref(_adapter *adapter, u8 rfpath) { - hal_mpt_SetDataRate(pAdapter); + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &adapter->mppriv; + s16 txpwr_ref; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + ptxpwr_arg.rfpath = rfpath; + ptxpwr_arg.is_cck = rtw_mp_is_cck_rate(pmppriv->rateidx); + + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_GET_TXPWR_REF); + txpwr_ref = ptxpwr_arg.txpwr_ref / TX_POWER_BASE; + + RTW_INFO("%s ,pwr ref: %d\n", __func__, txpwr_ref); + return txpwr_ref; } -void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain) +u16 rtw_mp_get_pwrtab_dbm(_adapter *adapter, u8 rfpath) { + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &adapter->mppriv; + s16 txpwr_dbm; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + ptxpwr_arg.rfpath = rfpath; + ptxpwr_arg.is_cck = rtw_mp_is_cck_rate(pmppriv->rateidx); + ptxpwr_arg.rate = pmppriv->rateidx; + ptxpwr_arg.dcm = 0; + ptxpwr_arg.offset = 0; + ptxpwr_arg.bandwidth = pmppriv->bandwidth; + ptxpwr_arg.beamforming = 0; + ptxpwr_arg.channel = pmppriv->channel; - PHY_SetRFPathSwitch(pAdapter, bMain); + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_READ_PWR_TABLE); + txpwr_dbm = ptxpwr_arg.table_item / TX_POWER_BASE; + RTW_INFO("%s ,read PwrTab dbm: %d\n", __func__, txpwr_dbm); + return txpwr_dbm; } -void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate) + +u16 rtw_mp_txpower_dbm(_adapter *adapter, u8 rf_path) { + struct mp_priv *pmppriv = &adapter->mppriv; + struct rtw_mp_txpwr_arg ptxpwr_arg; + u16 tmp_power_ref = 0; + u16 agc_cw_val = 0; + s16 pre_pwr_refcw_idx = 0; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.txpwr = pmppriv->txpowerdbm; + ptxpwr_arg.is_cck = rtw_mp_is_cck_rate(pmppriv->rateidx); + ptxpwr_arg.rfpath = rf_path; + + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_TXPWR); + + if (pmppriv->pre_refcw_cck_pwridxa == 0 || pmppriv->pre_refcw_cck_pwridxb == 0) { + pmppriv->pre_refcw_cck_pwridxa = rtw_mp_get_pwr_refcw(adapter, RF_PATH_A, 1); + pmppriv->pre_refcw_cck_pwridxb = rtw_mp_get_pwr_refcw(adapter, RF_PATH_B, 1); + } + if (pmppriv->pre_refcw_ofdm_pwridxa == 0 || pmppriv->pre_refcw_ofdm_pwridxb == 0) { + pmppriv->pre_refcw_ofdm_pwridxa = rtw_mp_get_pwr_refcw(adapter, RF_PATH_A, 0); + pmppriv->pre_refcw_ofdm_pwridxb = rtw_mp_get_pwr_refcw(adapter, RF_PATH_B, 0); + } - phy_switch_rf_path_set(pAdapter, pstate); + if (rf_path == RF_PATH_A && ptxpwr_arg.is_cck == true) + pre_pwr_refcw_idx = pmppriv->pre_refcw_cck_pwridxa; + else if (rf_path == RF_PATH_B && ptxpwr_arg.is_cck == true) + pre_pwr_refcw_idx = pmppriv->pre_refcw_cck_pwridxb; + else if (rf_path == RF_PATH_A && ptxpwr_arg.is_cck == false) + pre_pwr_refcw_idx = pmppriv->pre_refcw_ofdm_pwridxa; + else if (rf_path == RF_PATH_B && ptxpwr_arg.is_cck == false) + pre_pwr_refcw_idx = pmppriv->pre_refcw_ofdm_pwridxb; + tmp_power_ref = rtw_mp_get_pwr_ref(adapter, rf_path); + RTW_INFO("%s () tmp_power_ref: %d !! pre_pwr_refcw_idx:%d, pwr offset %d\n", + __func__, tmp_power_ref, pre_pwr_refcw_idx , pmppriv->txpoweridx); + agc_cw_val = pmppriv->txpowerdbm - tmp_power_ref + pre_pwr_refcw_idx + pmppriv->txpoweridx; + + ptxpwr_arg.txpwr_index = (pre_pwr_refcw_idx + pmppriv->txpoweridx) * TX_POWER_CODE_WORD_BASE; + rtw_mp_phl_txpower(adapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_TXPWR_INDEX); + + return agc_cw_val; } -u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter) +void SetDataRate(_adapter *padapter) { - return PHY_QueryRFPathSwitch(pAdapter); + + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_RATE_IDX); + + return; } -s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) +void SetTxAGCOffset(_adapter *adapter, u32 ulTxAGCOffset) { - return hal_mpt_SetThermalMeter(pAdapter, target_ther); + u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC; + + TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff); + TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8); + TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16); + + tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B); +// write_bbreg(adapter, rFPGA0_TxGainStage, +// (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC); } -#if 0 -static void TriggerRFThermalMeter(PADAPTER pAdapter) +void MP_PHY_SetRFPathSwitch(_adapter *adapter , BOOLEAN bMain) { - hal_mpt_TriggerRFThermalMeter(pAdapter); + //PHY_SetRFPathSwitch(adapter, bMain); + return; } -static u8 ReadRFThermalMeter(PADAPTER pAdapter) +void mp_phy_switch_rf_path_set(_adapter *adapter , u8 *pstate) { - return hal_mpt_ReadRFThermalMeter(pAdapter); + + //phy_switch_rf_path_set(adapter, pstate); + return; + +} + +u8 MP_PHY_QueryRFPathSwitch(_adapter *adapter) +{ + //return PHY_QueryRFPathSwitch(adapter); + return 0; } -#endif -void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value) +s32 SetThermalMeter(_adapter *adapter, u8 target_ther) { - hal_mpt_GetThermalMeter(pAdapter, rfpath, value); + //return hal_mpt_SetThermalMeter(adapter, target_ther); + return 0; } -void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) +#if 0 +static void TriggerRFThermalMeter(_adapter *adapter) { - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetSingleCarrierTx(pAdapter, bStart); + hal_mpt_TriggerRFThermalMeter(adapter); } -void SetSingleToneTx(PADAPTER pAdapter, u8 bStart) +static u8 ReadRFThermalMeter(_adapter *adapter) +{ + return hal_mpt_ReadRFThermalMeter(adapter); +} +#endif + +void GetThermalMeter(_adapter *adapter, u8 rfpath ,u8 *value) { - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetSingleToneTx(pAdapter, bStart); + struct mp_priv *pmppriv = &adapter->mppriv; + struct rtw_mp_txpwr_arg ptxpwr_arg; + u16 i = 0; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.mp_class = RTW_MP_CLASS_TXPWR; + ptxpwr_arg.cmd = RTW_MP_TXPWR_CMD_GET_THERMAL; + ptxpwr_arg.rfpath = rfpath; + + rtw_mp_set_phl_cmd(adapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + + while (i != 100) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(adapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + + if (ptxpwr_arg.cmd_ok && ptxpwr_arg.status == RTW_PHL_STATUS_SUCCESS) { + *value = ptxpwr_arg.thermal; + RTW_INFO("%s, SET CMD OK, thermal = %d\n", __func__, ptxpwr_arg.thermal); + break; + } else { + if (i > 100) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__, ptxpwr_arg.status); + break; + } + i++; + rtw_msleep_os(10); + } + } } -void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) +void rtw_mp_singlecarrier_tx(_adapter *adapter, u8 bstart) { - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart); + RTW_INFO("Not Supported SetSingleCarrierTx \n"); } -void SetContinuousTx(PADAPTER pAdapter, u8 bStart) +void rtw_mp_singletone_tx(_adapter *adapter, u8 bstart) { - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetContinuousTx(pAdapter, bStart); + struct mp_priv *pmp_priv = &adapter->mppriv; + + rtw_mp_txpwr_level(adapter); + rtw_phl_mp_tx_cmd(adapter, RTW_MP_TX_SINGLE_TONE, pmp_priv->rtw_mp_tx_method, bstart); } +void rtw_mp_carriersuppr_tx(_adapter *adapter, u8 bstart) +{ + struct mp_priv *pmp_priv = &adapter->mppriv; + + rtw_mp_txpwr_level(adapter); + rtw_phl_mp_tx_cmd(adapter, RTW_MP_TX_CCK_Carrier_Suppression, pmp_priv->rtw_mp_tx_method, bstart); +} -void PhySetTxPowerLevel(PADAPTER pAdapter) +void rtw_mp_continuous_tx(_adapter *adapter, u8 bstart) { - struct mp_priv *pmp_priv = &pAdapter->mppriv; + struct mp_priv *pmp_priv = &adapter->mppriv; + rtw_mp_txpwr_level(adapter); + rtw_phl_mp_tx_cmd(adapter, RTW_MP_TX_CONTINUOUS, pmp_priv->rtw_mp_tx_method, bstart); +} - if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */ - rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel); +void rtw_mp_txpwr_level(_adapter *adapter) +{ + struct mp_priv *pmp_priv = &adapter->mppriv; +/* + if (pmp_priv->bSetTxPower == 0) + rtw_hal_set_tx_power_level(adapter, pmp_priv->channel); +*/ + + return; } /* ------------------------------------------------------------------------------ */ -static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe) +static void dump_mpframe(_adapter *padapter, struct xmit_frame *pmpframe) { - rtw_hal_mgnt_xmit(padapter, pmpframe); + /*rtw_hal_mgnt_xmit(padapter, pmpframe);*/ + rtw_mgnt_xmit(padapter, pmpframe); } static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) { +#if 0 /*CONFIG_CORE_XMITBUF*/ struct xmit_frame *pmpframe; struct xmit_buf *pxmitbuf; - pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0); + pmpframe = rtw_alloc_xmitframe(pxmitpriv); if (pmpframe == NULL) return NULL; @@ -1311,52 +1116,19 @@ static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) pmpframe->buf_addr = pxmitbuf->pbuf; pxmitbuf->priv_data = pmpframe; +#else + struct xmit_frame *pmpframe; - return pmpframe; - -} - -#ifdef CONFIG_PCI_HCI -static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) -{ - u32 prio; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct rtw_tx_ring *ring; + pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0); + if (pmpframe == NULL) + return NULL; - switch (pattrib->qsel) { - case 0: - case 3: - prio = BE_QUEUE_INX; - break; - case 1: - case 2: - prio = BK_QUEUE_INX; - break; - case 4: - case 5: - prio = VI_QUEUE_INX; - break; - case 6: - case 7: - prio = VO_QUEUE_INX; - break; - default: - prio = BE_QUEUE_INX; - break; - } + pmpframe->frame_tag = MP_FRAMETAG; +#endif - ring = &pxmitpriv->tx_ring[prio]; + return pmpframe; - /* - * for now we reserve two free descriptor as a safety boundary - * between the tail and the head - */ - if ((ring->entries - ring->qlen) >= 2) - return _TRUE; - else - return _FALSE; } -#endif static thread_return mp_xmit_packet_thread(thread_context context) { @@ -1364,27 +1136,22 @@ static thread_return mp_xmit_packet_thread(thread_context context) struct mp_tx *pmptx; struct mp_priv *pmp_priv; struct xmit_priv *pxmitpriv; - PADAPTER padapter; + _adapter *padapter; pmp_priv = (struct mp_priv *)context; pmptx = &pmp_priv->tx; padapter = pmp_priv->papdater; pxmitpriv = &(padapter->xmitpriv); - thread_enter("RTW_MP_THREAD"); + rtw_thread_enter("RTW_MP_THREAD"); RTW_INFO("%s:pkTx Start\n", __func__); while (1) { pxmitframe = alloc_mp_xmitframe(pxmitpriv); -#ifdef CONFIG_PCI_HCI - if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) { - rtw_usleep_os(1000); - continue; - } -#endif + if (pxmitframe == NULL) { if (pmptx->stop || - RTW_CANNOT_RUN(padapter)) + RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) goto exit; else { rtw_usleep_os(10); @@ -1402,7 +1169,7 @@ static thread_return mp_xmit_packet_thread(thread_context context) pmp_priv->tx_pktcount++; if (pmptx->stop || - RTW_CANNOT_RUN(padapter)) + RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) goto exit; if ((pmptx->count != 0) && (pmptx->count == pmptx->sended)) @@ -1417,476 +1184,297 @@ static thread_return mp_xmit_packet_thread(thread_context context) pmptx->pallocated_buf = NULL; pmptx->stop = 1; - thread_exit(NULL); + rtw_thread_exit(NULL); return 0; } -void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc) +void fill_txdesc_for_mp(_adapter *padapter, u8 *ptxdesc) { struct mp_priv *pmp_priv = &padapter->mppriv; _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE); } -#if defined(CONFIG_RTL8188E) -void fill_tx_desc_8188e(PADAPTER padapter) +static void Rtw_MPSetMacTxEDCA(_adapter *padapter) { - struct mp_priv *pmp_priv = &padapter->mppriv; - struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc); - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u32 pkt_size = pattrib->last_txcmdsz; - s32 bmcast = IS_MCAST(pattrib->ra); - /* offset 0 */ -#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI) - desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); - desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */ - desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */ - if (bmcast) - desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */ - - desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000); +#if 0 + rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */ + /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */ + phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0); + /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/ + phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/ + RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord)); #endif - - desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */ - desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */ - desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */ - /* offset 8 */ - /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */ - - desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000); - desc->txdw4 |= cpu_to_le32(HW_SSN); - - desc->txdw4 |= cpu_to_le32(USERATE); - desc->txdw4 |= cpu_to_le32(DISDATAFB); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */ - } - - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - desc->txdw4 |= cpu_to_le32(DATA_BW); - - /* offset 20 */ - desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M) - desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */ - } - - desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */ - desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit */ - - } -#endif -#if defined(CONFIG_RTL8814A) -void fill_tx_desc_8814a(PADAPTER padapter) +u8 rtw_phl_mp_tx_cmd(_adapter *padapter, enum rtw_mp_tx_cmd cmdid, + enum rtw_mp_tx_method tx_method, boolean bstart) { - struct mp_priv *pmp_priv = &padapter->mppriv; - u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - - u32 pkt_size = pattrib->last_txcmdsz; - s32 bmcast = IS_MCAST(pattrib->ra); - u8 offset; - - /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */ - SET_TX_DESC_LAST_SEG_8814A(pDesc, 1); - /* SET_TX_DESC_OWN_(pDesc, 1); */ - - SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size); - - offset = TXDESC_SIZE + OFFSET_SZ; - - SET_TX_DESC_OFFSET_8814A(pDesc, offset); -#if defined(CONFIG_PCI_HCI) - SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */ -#else - SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1); -#endif - - if (bmcast) - SET_TX_DESC_BMC_8814A(pDesc, 1); - - SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id); - SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid); - - /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */ - SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel); - /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */ - - if (pmp_priv->preamble) - SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1); - - if (!pattrib->qos_en) { - SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */ - } else - SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum); - - if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) - SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth); - else { - RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth); - SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20); - } - - SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1); - SET_TX_DESC_USE_RATE_8814A(pDesc, 1); - SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx); - -} -#endif - -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) -void fill_tx_desc_8812a(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - - u32 pkt_size = pattrib->last_txcmdsz; - s32 bmcast = IS_MCAST(pattrib->ra); - u8 data_rate, pwr_status, offset; - - SET_TX_DESC_FIRST_SEG_8812(pDesc, 1); - SET_TX_DESC_LAST_SEG_8812(pDesc, 1); - SET_TX_DESC_OWN_8812(pDesc, 1); - - SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size); - - offset = TXDESC_SIZE + OFFSET_SZ; - - SET_TX_DESC_OFFSET_8812(pDesc, offset); - -#if defined(CONFIG_PCI_HCI) - SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0); -#else - SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1); -#endif - if (bmcast) - SET_TX_DESC_BMC_8812(pDesc, 1); - - SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id); - SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid); - - /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */ - SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel); - /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */ - - if (!pattrib->qos_en) { - SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */ - } else - SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum); - - if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) - SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth); - else { - RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth); - SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20); - } - - SET_TX_DESC_DISABLE_FB_8812(pDesc, 1); - SET_TX_DESC_USE_RATE_8812(pDesc, 1); - SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx); - -} -#endif -#if defined(CONFIG_RTL8192E) -void fill_tx_desc_8192e(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - - u32 pkt_size = pattrib->last_txcmdsz; - s32 bmcast = IS_MCAST(pattrib->ra); - u8 data_rate, pwr_status, offset; - - - SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size); - - offset = TXDESC_SIZE + OFFSET_SZ; - - SET_TX_DESC_OFFSET_92E(pDesc, offset); -#if defined(CONFIG_PCI_HCI) /* 8192EE */ - - SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */ -#else /* 8192EU 8192ES */ - SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1); -#endif - - if (bmcast) - SET_TX_DESC_BMC_92E(pDesc, 1); - - SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id); - SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid); - - - SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel); - /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */ - - if (!pattrib->qos_en) { - SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */ - SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel); - } else - SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum); - - if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40)) - SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth); - else { - RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth); - SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20); - } - - /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */ - - SET_TX_DESC_DISABLE_FB_92E(pDesc, 1); - SET_TX_DESC_USE_RATE_92E(pDesc, 1); - SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx); - -} -#endif + struct mp_priv *pmppriv = &padapter->mppriv; + struct pkt_attrib *pattrib = &pmppriv->tx.attrib; + struct rtw_mp_tx_arg tx_arg; + u16 i = 0; + u8 user_idx = pmppriv->mp_plcp_useridx; + + _rtw_memset((void *)&tx_arg, 0, sizeof(struct rtw_mp_tx_arg)); + tx_arg.mp_class = RTW_MP_CLASS_TX; + tx_arg.tx_method = tx_method; + tx_arg.cmd = cmdid; + tx_arg.cmd_ok = 0; + tx_arg.tx_ok = 0; + tx_arg.data_rate = pmppriv->rateidx; + tx_arg.is_cck = rtw_mp_is_cck_rate(pmppriv->rateidx); + tx_arg.start_tx = bstart; + tx_arg.tx_path = pmppriv->antenna_trx; + tx_arg.gi = pmppriv->rtw_mp_plcp_gi; + tx_arg.period = pmppriv->pktInterval; + tx_arg.plcp_usr_idx = user_idx; + tx_arg.stbc = pmppriv->rtw_mp_stbc; + + switch (cmdid) { + case RTW_MP_TX_PACKETS: + RTW_INFO("%s,SET MP_TX_PACKETS tx_method %d\n", __func__, tx_arg.tx_method); + if (tx_method == RTW_MP_PMACT_TX) { + tx_arg.tx_mode = RTW_MP_PMAC_PKTS_TX; + tx_arg.tx_cnt = pmppriv->tx.count; + + } else if (tx_method == RTW_MP_FW_PMACT_TX) { + tx_arg.tx_mode = RTW_MP_PMAC_FW_TRIG_TX; + tx_arg.tx_cnt = 0; + tx_arg.tx_time = 60; + } -#if defined(CONFIG_RTL8723B) -void fill_tx_desc_8723b(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1); - SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1); + break; + case RTW_MP_TX_CONTINUOUS: + RTW_INFO("%s,SET MP_TX_CONTINUOUS\n", __func__); + tx_arg.tx_mode = RTW_MP_PMAC_CONT_TX; + break; + case RTW_MP_TX_SINGLE_TONE: + RTW_INFO("%s,SET TX_OFDM_Single_Tone\n", __func__); + tx_arg.tx_mode = RTW_MP_PMAC_OFDM_SINGLE_TONE_TX; + break; + case RTW_MP_TX_CCK_Carrier_Suppression: + RTW_INFO("%s,SET TX_CCK_Carrier_Suppression\n", __func__); + tx_arg.tx_mode = RTW_MP_PMAC_CCK_CARRIER_SIPPRESSION_TX; + break; + case RTW_MP_TX_CONFIG_PLCP_PATTERN: + RTW_INFO("%s,SET MP_TX_CONFIG_PLCP_PATTERN\n", __func__); + tx_arg.plcp_case_id = pmppriv->rtw_mp_pmact_patt_idx; + tx_arg.plcp_ppdu_type = pmppriv->rtw_mp_pmact_ppdu_type; + break; + case RTW_MP_TX_CONFIG_PLCP_COMMON_INFO: + tx_arg.dbw = pmppriv->rtw_mp_data_bandwidth; + tx_arg.long_preamble_en = pmppriv->preamble; + tx_arg.stbc = pmppriv->rtw_mp_stbc; + tx_arg.gi = pmppriv->rtw_mp_plcp_gi; + tx_arg.he_ltf_type = pmppriv->rtw_mp_plcp_ltf; + tx_arg.he_mcs_sigb = pmppriv->rtw_mp_he_sigb; + tx_arg.he_dcm_sigb = pmppriv->rtw_mp_he_sigb_dcm; + tx_arg.bss_color = 0; + tx_arg.he_er_u106ru_en = pmppriv->rtw_mp_he_er_su_ru_106_en; + if (pmppriv->rtw_mp_tx_method == RTW_MP_FW_PMACT_TX) { + pmppriv->rtw_mp_plcp_tx_time = 5484; + pmppriv->rtw_mp_plcp_tx_mode = 1; + } + tx_arg.max_tx_time_0p4us = pmppriv->rtw_mp_plcp_tx_time; + tx_arg.mode = pmppriv->rtw_mp_plcp_tx_mode; + tx_arg.ppdu_type = pmppriv->rtw_mp_pmact_ppdu_type; + tx_arg.cbw = pmppriv->bandwidth; + tx_arg.txsc = pmppriv->rtw_mp_trxsc; + tx_arg.n_user = pmppriv->rtw_mp_plcp_tx_user; + + RTW_INFO("%s,SET TX_CONFIG_PLCP_COMMON_INFO\n", __func__); + RTW_INFO("%s=============================\n", __func__); + RTW_INFO("%s dbw = %d\n", __func__, tx_arg.dbw); + RTW_INFO("%s long_preamble_en = %d\n", __func__, tx_arg.long_preamble_en); + RTW_INFO("%s stbc = %d\n", __func__, tx_arg.stbc); + RTW_INFO("%s gi = %d\n", __func__, tx_arg.gi); + RTW_INFO("%s tb_l_len = %d\n", __func__, tx_arg.tb_l_len); + RTW_INFO("%s he_ltf_type = %d\n", __func__, tx_arg.he_ltf_type); + RTW_INFO("%s he_mcs_sigb = %d\n", __func__, tx_arg.he_mcs_sigb); + RTW_INFO("%s he_dcm_sigb = %d\n", __func__, tx_arg.he_dcm_sigb); + RTW_INFO("%s max_tx_time_0p4us = %d\n", __func__, tx_arg.max_tx_time_0p4us); + RTW_INFO("%s bss_color = %d\n", __func__, tx_arg.bss_color); + RTW_INFO("%s he_er_u106ru_en = %d\n", __func__, tx_arg.he_er_u106ru_en); + RTW_INFO("%s mode = %d\n", __func__, tx_arg.mode); + RTW_INFO("%s ppdu_type = %d\n", __func__, tx_arg.ppdu_type); + RTW_INFO("%s cbw = %d\n", __func__, tx_arg.cbw); + RTW_INFO("%s txsc = %d\n", __func__, tx_arg.txsc); + RTW_INFO("%s n_user = %d\n", __func__, tx_arg.n_user); + RTW_INFO("%s=============================\n", __func__); + break; + case RTW_MP_TX_CMD_PHY_OK: + /*TBD. API not ready*/ + RTW_INFO("%s,SET MP_TX_CMD_PHY_OK\n", __func__); + break; + case RTW_MP_TX_CONFIG_PLCP_USER_INFO: + tx_arg.plcp_usr_idx = user_idx; + tx_arg.mcs = pmppriv->mp_plcp_user[user_idx].plcp_mcs; + tx_arg.fec = pmppriv->mp_plcp_user[user_idx].coding; + tx_arg.dcm = pmppriv->mp_plcp_user[user_idx].dcm; + tx_arg.aid = pmppriv->mp_plcp_user[user_idx].aid; + tx_arg.scrambler_seed = (rtw_random32() % 127) + 1; + tx_arg.random_init_seed = (rtw_random32() % 127) + 1; + tx_arg.apep = pmppriv->mp_plcp_user[user_idx].plcp_txlen; + tx_arg.ru_alloc = pmppriv->mp_plcp_user[user_idx].ru_alloc; + tx_arg.nss = pmppriv->mp_plcp_user[user_idx].plcp_nss + 1; + tx_arg.pwr_boost_db = pmppriv->mp_plcp_user[user_idx].pwr_boost_db; + tx_arg.fec = pmppriv->mp_plcp_user[user_idx].coding; + + RTW_INFO("%s,SET MP_TX_CONFIG_PLCP_USER_INFO\n", __func__); + RTW_INFO("%s plcp_usr_idx = %d\n", __func__, tx_arg.plcp_usr_idx); + RTW_INFO("%s mcs = %d\n", __func__, tx_arg.mcs); + RTW_INFO("%s fec = %d\n", __func__, tx_arg.fec); + RTW_INFO("%s dcm = %d\n", __func__, tx_arg.dcm); + RTW_INFO("%s ascrambler_seed = %d\n", __func__, tx_arg.scrambler_seed); + RTW_INFO("%s random_init_seed = %d\n", __func__, tx_arg.random_init_seed); + RTW_INFO("%s apep = %d\n", __func__, tx_arg.apep); + RTW_INFO("%s ru_alloc = %d\n", __func__, tx_arg.ru_alloc); + RTW_INFO("%s nss = %d\n", __func__, tx_arg.nss); + break; + case RTW_MP_TX_MODE_SWITCH: + if (pmppriv->rtw_mp_tx_method == RTW_MP_TMACT_TX) + tx_arg.tx_mode = 0;/* mode: 0 = tmac, 1 = pmac */ + else + tx_arg.tx_mode = 1;/* mode: 0 = tmac, 1 = pmac */ + RTW_INFO("%s,SET MP_TX_MODE_SWITCH\n", __func__); + break; + default: + RTW_INFO("%s,SET MP_TX_MODE None\n", __func__); + return 0; } - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1); - - SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx); - - SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF); -} -#endif - -#if defined(CONFIG_RTL8703B) -void fill_tx_desc_8703b(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1); - SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1); + rtw_mp_set_phl_cmd(padapter, (void*)&tx_arg, sizeof(struct rtw_mp_tx_arg)); + while (i != 100) { + rtw_mp_get_phl_cmd(padapter, (void*)&tx_arg, sizeof(struct rtw_mp_tx_arg)); + if (tx_arg.cmd_ok && tx_arg.status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD OK\n", __func__); + if (cmdid == RTW_MP_TX_CMD_PHY_OK) { + RTW_INFO("%s, Get Tx Rpt OK CNT:%d\n", __func__, tx_arg.tx_ok); + padapter->mppriv.tx.sended = tx_arg.tx_ok; + } + break; + } else { + if (i > 100) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__, tx_arg.status); + break; + } + i++; + rtw_msleep_os(10); + } } - - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1); - - SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx); - - SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF); + return (tx_arg.cmd_ok); } -#endif - -#if defined(CONFIG_RTL8188F) -void fill_tx_desc_8188f(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1); - SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1); - if (pmp_priv->preamble) - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1); - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1); - - SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx); - - SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF); -} -#endif - -#if defined(CONFIG_RTL8188GTV) -void fill_tx_desc_8188gtv(PADAPTER padapter) +static thread_return mp_xmit_phl_packet_thread(thread_context context) { - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1); - SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel); - SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1); - - if (pmp_priv->preamble) - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1); - - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1); + struct mp_priv *pmppriv = (struct mp_priv *)context; + struct mp_tx *pmptx = &pmppriv->tx; + _adapter *padapter = pmppriv->papdater; + struct pkt_attrib *pattrib = &pmppriv->tx.attrib; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_trx_test_param test_param = {0}; + u16 i = 0; - SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx); + RTW_INFO("%s: Start !!\n", __func__); + rtw_phl_trx_default_param(GET_PHL_INFO(dvobj), &test_param); - SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF); -} -#endif + test_param.tx_cap.f_rate = (u16)pmppriv->rateidx; + test_param.tx_payload_size = pattrib->pktlen; + test_param.tx_cap.f_gi_ltf = 0; + test_param.tx_cap.f_stbc = 0; + test_param.tx_cap.f_ldpc = 0; + RTW_INFO("%s: Start !! tx method %d\n", __func__, pmppriv->rtw_mp_tx_method); + while (1) { + if (pmppriv->rtw_mp_tx_method == RTW_MP_TMACT_TX) { + /*/if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_PACKETS, pmppriv->rtw_mp_tx_method, _TRUE)) {*/ + if (rtw_phl_trx_testsuite(GET_PHL_INFO(dvobj), &test_param) == 0) + RTW_DBG("%s: rtw_phl_trx_testsuite!!\n", __func__); + else + rtw_usleep_os(10); + } + pmptx->sended++; + pmppriv->tx_pktcount++; + rtw_usleep_os(padapter->mppriv.pktInterval); -#if defined(CONFIG_RTL8723D) -void fill_tx_desc_8723d(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_BK_8723D(ptxdesc, 1); - SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1); + if (pmptx->stop || RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) + goto exit; + if ((pmptx->count != 0) && (pmptx->count == pmptx->sended)) + goto exit; + flush_signals_thread(); } +exit: + pmptx->stop = 1; - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1); - - SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx); - - SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF); + RTW_INFO("%s: Exit !!\n", __func__); + rtw_thread_exit(NULL); + return 0; } -#endif -#if defined(CONFIG_RTL8710B) -void fill_tx_desc_8710b(PADAPTER padapter) +void rtw_set_phl_packet_tx(_adapter *padapter, u8 bStart) { - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_BK_8710B(ptxdesc, 1); - SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1); - } - - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1); + struct mp_priv *pmp_priv; + u8 rfpath_i = 0; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + pmp_priv = &padapter->mppriv; - SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx); - SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF); -} -#endif + for (rfpath_i = 0 ; rfpath_i < tx_nss; rfpath_i ++) + rtw_mp_txpower_dbm(padapter, rfpath_i); + + RTW_INFO("%s: PACKET TX tx method %d!!\n", __func__, pmp_priv->rtw_mp_tx_method); + + if (bStart) { + RTW_INFO("%s: !! tx method %d\n", __func__, pmp_priv->rtw_mp_tx_method); + pmp_priv->tx.sended = 0; + pmp_priv->tx.stop = 0; + pmp_priv->tx_pktcount = 0; + if (pmp_priv->rtw_mp_tx_method == RTW_MP_PMACT_TX || + pmp_priv->rtw_mp_tx_method == RTW_MP_FW_PMACT_TX) { + RTW_INFO("%s: PLCP_USER_INFO & PLCP_COMMON_INFO!!\n", __func__); + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_CONFIG_PLCP_USER_INFO, pmp_priv->rtw_mp_tx_method, _TRUE) == true) + RTW_INFO("%s: PLCP_USER_INFO done!!\n", __func__); + rtw_msleep_os(100); + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_CONFIG_PLCP_COMMON_INFO, pmp_priv->rtw_mp_tx_method, _TRUE) == true) + RTW_INFO("%s: RTW_MP_TX_CONFIG_PLCP_COMMON_INFO done!!\n", __func__); + rtw_msleep_os(100); + } -#if defined(CONFIG_RTL8192F) -void fill_tx_desc_8192f(PADAPTER padapter) -{ - struct mp_priv *pmp_priv = &padapter->mppriv; - struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); - u8 *ptxdesc = pmp_priv->tx.desc; - - SET_TX_DESC_BK_8192F(ptxdesc, 1); - SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id); - SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel); - - SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid); - SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum); - SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1); - SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1); - SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1); - - if (pmp_priv->preamble) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) - SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1); + if (pmp_priv->rtw_mp_tx_method == RTW_MP_FW_PMACT_TX) { + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_PACKETS, pmp_priv->rtw_mp_tx_method, _TRUE)) + RTW_INFO("%s: RTW_MP_FW_PMACT_TX!!\n", __func__); + else + RTW_INFO("%s: RTW_MP_FW_PMACT_TX fail!!\n", __func__); + } else if (pmp_priv->rtw_mp_tx_method == RTW_MP_PMACT_TX) { + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_PACKETS, pmp_priv->rtw_mp_tx_method, _TRUE)) + RTW_DBG("%s: RTW_MP_TX_PACKETS!!\n", __func__); + } else { + pmp_priv->tx.PktTxThread = rtw_thread_start( + mp_xmit_phl_packet_thread, pmp_priv, "RTW_MP_Tx_THREAD"); + if (pmp_priv->tx.PktTxThread == NULL) + RTW_ERR("Create PktTx Thread Fail !!!!!\n"); + } } - - if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) - SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1); - - SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx); - - SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF); -} - -#endif -static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) -{ - - rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */ - /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */ - phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0); - /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/ - phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/ - /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/ - /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/ - /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/ - RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord)); - + if (!bStart) { + if (pmp_priv->rtw_mp_tx_method == RTW_MP_FW_PMACT_TX) { + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_PACKETS, pmp_priv->rtw_mp_tx_method, false)) { + RTW_INFO("%s: RTW_MP_FW_TMACT_TX Stop TX!!\n", __func__); + return; + } + } else if (pmp_priv->rtw_mp_tx_method == RTW_MP_PMACT_TX) { + if (rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_PACKETS, pmp_priv->rtw_mp_tx_method, false)) { + RTW_INFO("%s: RTW_MP_PMACT_TX Stop TX!!\n", __func__); + return; + } + } + } } -void SetPacketTx(PADAPTER padapter) +void rtw_mp_set_packet_tx(_adapter *padapter) { u8 *ptr, *pkt_start, *pkt_end; u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0; @@ -1920,7 +1508,7 @@ void SetPacketTx(PADAPTER padapter) return; } - pattrib->mac_id = pattrib->psta->cmn.mac_id; + pattrib->mac_id = pattrib->psta->phl_sta->macid; pattrib->mbssid = 0; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -1931,13 +1519,13 @@ void SetPacketTx(PADAPTER padapter) if (pmp_priv->tx.pallocated_buf) rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size); pmp_priv->tx.write_size = pkt_size; - pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ; + pmp_priv->tx.buf_size = pkt_size + SZ_ALIGN_XMITFRAME_EXT; pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size); if (pmp_priv->tx.pallocated_buf == NULL) { RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size); return; } - pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ); + pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), SZ_ALIGN_XMITFRAME_EXT); ptr = pmp_priv->tx.buf; _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE); @@ -1945,16 +1533,6 @@ void SetPacketTx(PADAPTER padapter) pkt_end = pkt_start + pkt_size; /* 3 3. init TX descriptor */ -#if defined(CONFIG_RTL8188E) - if (IS_HARDWARE_TYPE_8188E(padapter)) - fill_tx_desc_8188e(padapter); -#endif - -#if defined(CONFIG_RTL8814A) - if (IS_HARDWARE_TYPE_8814A(padapter)) - fill_tx_desc_8814a(padapter); -#endif /* defined(CONFIG_RTL8814A) */ - #if defined(CONFIG_RTL8822B) if (IS_HARDWARE_TYPE_8822B(padapter)) rtl8822b_prepare_mp_txdesc(padapter, pmp_priv); @@ -1970,58 +1548,11 @@ void SetPacketTx(PADAPTER padapter) rtl8821c_prepare_mp_txdesc(padapter, pmp_priv); #endif /* CONFIG_RTL8821C */ -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) - fill_tx_desc_8812a(padapter); -#endif - -#if defined(CONFIG_RTL8192E) - if (IS_HARDWARE_TYPE_8192E(padapter)) - fill_tx_desc_8192e(padapter); -#endif -#if defined(CONFIG_RTL8723B) - if (IS_HARDWARE_TYPE_8723B(padapter)) - fill_tx_desc_8723b(padapter); -#endif -#if defined(CONFIG_RTL8703B) - if (IS_HARDWARE_TYPE_8703B(padapter)) - fill_tx_desc_8703b(padapter); -#endif - -#if defined(CONFIG_RTL8188F) - if (IS_HARDWARE_TYPE_8188F(padapter)) - fill_tx_desc_8188f(padapter); -#endif - -#if defined(CONFIG_RTL8188GTV) - if (IS_HARDWARE_TYPE_8188GTV(padapter)) - fill_tx_desc_8188gtv(padapter); -#endif - -#if defined(CONFIG_RTL8723D) - if (IS_HARDWARE_TYPE_8723D(padapter)) - fill_tx_desc_8723d(padapter); -#endif -#if defined(CONFIG_RTL8192F) - if (IS_HARDWARE_TYPE_8192F(padapter)) - fill_tx_desc_8192f(padapter); -#endif - -#if defined(CONFIG_RTL8710B) - if (IS_HARDWARE_TYPE_8710B(padapter)) - fill_tx_desc_8710b(padapter); -#endif - #if defined(CONFIG_RTL8814B) if (IS_HARDWARE_TYPE_8814B(padapter)) rtl8814b_prepare_mp_txdesc(padapter, pmp_priv); #endif /* CONFIG_RTL8814B */ -#if defined(CONFIG_RTL8723F) - if (IS_HARDWARE_TYPE_8723F(padapter)) - rtl8723f_prepare_mp_txdesc(padapter, pmp_priv); -#endif /* CONFIG_RTL8723F */ - /* 3 4. make wlan header, make_wlanhdr() */ hdr = (struct rtw_ieee80211_hdr *)pkt_start; set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype); @@ -2096,11 +1627,9 @@ void SetPacketTx(PADAPTER padapter) } /* 3 6. start thread */ #ifdef PLATFORM_LINUX - pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); - if (IS_ERR(pmp_priv->tx.PktTxThread)) { + pmp_priv->tx.PktTxThread = rtw_thread_start(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); + if (pmp_priv->tx.PktTxThread == NULL) RTW_ERR("Create PktTx Thread Fail !!!!!\n"); - pmp_priv->tx.PktTxThread = NULL; - } #endif #ifdef PLATFORM_FREEBSD { @@ -2118,101 +1647,12 @@ void SetPacketTx(PADAPTER padapter) return; } -void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) +void rtw_mp_reset_phy_count(_adapter *adapter) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - struct mp_priv *pmppriv = &pAdapter->mppriv; - - - if (bStartRx) { -#ifdef CONFIG_RTL8723B - phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */ - write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */ -#endif - pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL; - pHalData->ReceiveConfig |= RCR_ACRC32; - pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; - - if (pmppriv->bSetRxBssid == _TRUE) { - RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__, - MAC_ARG(pmppriv->network_macaddr)); - pHalData->ReceiveConfig = 0; - pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF; - pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF; - -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) -/* todo: 8723F */ - write_bbreg(pAdapter, 0x550, BIT3, bEnable); -#endif - rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ - pmppriv->brx_filter_beacon = _TRUE; - - } else { - pHalData->ReceiveConfig |= RCR_ADF; - /* Accept all data frames */ - rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF); - } - - if (bAB) - pHalData->ReceiveConfig |= RCR_AB; - } else { -#ifdef CONFIG_RTL8723B - phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/ - write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */ -#endif - pHalData->ReceiveConfig = 0; - rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ - } - - rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); -} - -void ResetPhyRxPktCount(PADAPTER pAdapter) -{ - u32 i, phyrx_set = 0; - - for (i = 0; i <= 0xF; i++) { - phyrx_set = 0; - phyrx_set |= _RXERR_RPT_SEL(i); /* select */ - phyrx_set |= RXERR_RPT_RST; /* set counter to zero */ - rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); - } -} - -static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit) -{ - /* selection */ - u32 phyrx_set = 0, count = 0; - - phyrx_set = _RXERR_RPT_SEL(selbit & 0xF); - rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); - - /* Read packet count */ - count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK; - - return count; -} - -u32 GetPhyRxPktReceived(PADAPTER pAdapter) -{ - u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; - - OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK); - CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK); - HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK); - - return OFDM_cnt + CCK_cnt + HT_cnt; -} - -u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter) -{ - u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; - - OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL); - CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL); - HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL); - - return OFDM_cnt + CCK_cnt + HT_cnt; + RTW_INFO("%s()!!!\n", __func__); + rtw_mp_phl_config_arg(adapter, RTW_MP_CONFIG_CMD_SET_RESET_PHY_COUNT); + rtw_mp_phl_config_arg(adapter, RTW_MP_CONFIG_CMD_SET_RESET_MAC_COUNT); + rtw_mp_phl_config_arg(adapter, RTW_MP_CONFIG_CMD_SET_RESET_DRV_COUNT); } struct psd_init_regs { @@ -2227,14 +1667,14 @@ struct psd_init_regs { int reg_808; }; -static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) +static int rtw_mp_psd_init(_adapter *padapter, struct psd_init_regs *regs) { - HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); - - switch (phal_data->rf_type) { + u8 rf_type = GET_HAL_RFPATH(adapter_to_dvobj(padapter)); +#if 0 + switch (rf_type) { /* 1R */ case RF_1T1R: - if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + if (rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) { /* 11AC 1R PSD Setting 3wire & cck off */ regs->reg_c00 = rtw_read32(padapter, 0xC00); phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00); @@ -2253,7 +1693,7 @@ static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) /* 2R */ case RF_1T2R: case RF_2T2R: - if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + if (rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) { /* 11AC 2R PSD Setting 3wire & cck off */ regs->reg_c00 = rtw_read32(padapter, 0xC00); regs->reg_e00 = rtw_read32(padapter, 0xE00); @@ -2274,7 +1714,7 @@ static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) /* 3R */ case RF_2T3R: case RF_3T3R: - if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + if (rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) { /* 11AC 3R PSD Setting 3wire & cck off */ regs->reg_c00 = rtw_read32(padapter, 0xC00); regs->reg_e00 = rtw_read32(padapter, 0xE00); @@ -2294,7 +1734,7 @@ static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) case RF_2T4R: case RF_3T4R: case RF_4T4R: - if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + if (rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) { /* 11AC 4R PSD Setting 3wire & cck off */ regs->reg_c00 = rtw_read32(padapter, 0xC00); regs->reg_e00 = rtw_read32(padapter, 0xE00); @@ -2313,36 +1753,38 @@ static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) break; default: - RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type); + RTW_ERR("%s: unknown %d rf type\n", __func__, + GET_HAL_RFPATH(adapter_to_dvobj(padapter))); return -1; } /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */ - if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) + if (rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) phy_set_bb_reg(padapter, 0x910, 0xC000, 3); else phy_set_bb_reg(padapter, 0x808, 0xC000, 3); - - RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type); +#endif + RTW_INFO("%s: set %d rf type done\n", __func__, + GET_HAL_RFPATH(adapter_to_dvobj(padapter))); return 0; } -static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs) +static int rtw_mp_psd_close(_adapter *padapter, struct psd_init_regs *regs) { - HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); + u8 rf_type = GET_HAL_RFPATH(adapter_to_dvobj(padapter)); - - if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { +#if 0 + if (!rtw_hw_chk_proto_cap(padapter, PROTO_CAP_11AC)) { /* 11n 3wire restore */ rtw_write32(padapter, 0x88C, regs->reg_88c); /* 11n cck restore */ rtw_write32(padapter, 0x800, regs->reg_800); - RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type); + RTW_INFO("%s: restore %d rf type\n", __func__, rf_type); return 0; } /* 11ac 3wire restore */ - switch (phal_data->rf_type) { + switch (rf_type) { case RF_1T1R: rtw_write32(padapter, 0xC00, regs->reg_c00); break; @@ -2366,26 +1808,25 @@ static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs) rtw_write32(padapter, 0x1A00, regs->reg_1a00); break; default: - RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type); + RTW_WARN("%s: unknown %d rf type\n", __func__, rf_type); break; } /* 11ac cck restore */ rtw_write32(padapter, 0x808, regs->reg_808); - RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type); +#endif + RTW_INFO("%s: restore %d rf type done\n", __func__, rf_type); return 0; } /* reg 0x808[9:0]: FFT data x * reg 0x808[22]: 0 --> 1 to get 1 FFT data y * reg 0x8B4[15:0]: FFT data y report */ -static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) +static u32 rtw_GetPSDData(_adapter *adapter, u32 point) { u32 psd_val = 0; - -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) \ - || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - +#if 0 +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) u16 psd_reg = 0x910; u16 psd_regL = 0xF44; #else @@ -2393,28 +1834,55 @@ static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) u16 psd_regL = 0x8B4; #endif - psd_val = rtw_read32(pAdapter, psd_reg); + psd_val = rtw_read32(adapter, psd_reg); psd_val &= 0xFFBFFC00; psd_val |= point; - rtw_write32(pAdapter, psd_reg, psd_val); + rtw_write32(adapter, psd_reg, psd_val); rtw_mdelay_os(1); psd_val |= 0x00400000; - rtw_write32(pAdapter, psd_reg, psd_val); + rtw_write32(adapter, psd_reg, psd_val); rtw_mdelay_os(1); - psd_val = rtw_read32(pAdapter, psd_regL); + psd_val = rtw_read32(adapter, psd_regL); #if defined(CONFIG_RTL8821C) psd_val = (psd_val & 0x00FFFFFF) / 32; #else psd_val &= 0x0000FFFF; #endif - +#endif return psd_val; } +u8 rtw_mp_phl_psd_cmd(_adapter *padapter, struct rtw_mp_cal_arg *psd_arg, u8 cmdid) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u16 i = 0; + u32 cmd_size = sizeof(struct rtw_mp_cal_arg); + + psd_arg->mp_class = RTW_MP_CLASS_CAL; + psd_arg->cmd = cmdid; + + rtw_mp_set_phl_cmd(padapter, (void*)psd_arg, cmd_size); + while (i <= 100) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)psd_arg, cmd_size); + if (psd_arg->cmd_ok && psd_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD OK\n", __func__); + return psd_arg->cmd_ok; + } else { + if (i > 100) { + RTW_DBG("%s,GET CMD FAIL !!! status %d\n", __func__, psd_arg->status); + break; + } + i++; + } + } + return 0; +} + /* * pts start_point_min stop_point_max * 128 64 64 + 128 = 192 @@ -2423,190 +1891,77 @@ static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) * 1024 512 512 + 1024 = 1536 * */ -u32 mp_query_psd(PADAPTER pAdapter, u8 *data) +u32 mp_query_psd(_adapter *adapter, u8 *data) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct dm_struct *p_dm = adapter_to_phydm(pAdapter); - - u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0; - u32 psd_data = 0; - struct psd_init_regs regs = {}; - int psd_analysis = 0; - char *pdata = NULL; - - -#ifdef PLATFORM_LINUX - if (!netif_running(pAdapter->pnetdev)) { - return 0; - } -#endif - - if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - return 0; - } - - if (strlen(data) == 0) { /* default value */ - psd_pts = 128; - psd_start = 64; - psd_stop = 128; - } else if (strncmp(data, "analysis,", 9) == 0) { - if (rtw_mp_psd_init(pAdapter, ®s) != 0) - return 0; - psd_analysis = 1; - sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); - } else - sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); - - data[0] = '\0'; - pdata = data; - - if (psd_stop > 1920 || psd_stop < 1) { - rtw_warn_on(1); - psd_stop = 1920; - } - - if (IS_HARDWARE_TYPE_8822C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) { - u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256); - - if (psdbuf == NULL) { - RTW_INFO("%s: psd buf malloc fail!!\n", __func__); - return 0; - } - - halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts); - halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start); - halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop); - halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000); - - halrf_psd_init(p_dm); -#ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(100); -#else - rtw_mdelay_os(10); -#endif - halrf_psd_query(p_dm, psdbuf, 256); - - i = 0; - while (i < 256) { - pdata += sprintf(pdata, "%x ", (psdbuf[i])); - i++; - } - - if (psdbuf) - rtw_mfree(psdbuf, sizeof(u32)*256); - - } else { - i = psd_start; - - while (i < psd_stop) { - if (i >= psd_pts) - psd_data = rtw_GetPSDData(pAdapter, i - psd_pts); - else - psd_data = rtw_GetPSDData(pAdapter, i); - - pdata += sprintf(pdata, "%x ", psd_data); - i++; - } - - } - -#ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(100); -#else - rtw_mdelay_os(100); -#endif - - if (psd_analysis) - rtw_mp_psd_close(pAdapter, ®s); - - return strlen(data) + 1; -} - - -#if 0 -void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv) -{ - int i, res; - _adapter *padapter = pxmitpriv->adapter; - struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; - struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; - - u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; - u32 num_xmit_extbuf = NR_XMIT_EXTBUFF; - if (padapter->registrypriv.mp_mode == 0) { - max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; - num_xmit_extbuf = NR_XMIT_EXTBUFF; - } else { - max_xmit_extbuf_size = 6000; - num_xmit_extbuf = 8; - } - - pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; - for (i = 0; i < num_xmit_extbuf; i++) { - rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE); - - pxmitbuf++; - } - - if (pxmitpriv->pallocated_xmit_extbuf) - rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4); - - if (padapter->registrypriv.mp_mode == 0) { - max_xmit_extbuf_size = 6000; - num_xmit_extbuf = 8; - } else { - max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; - num_xmit_extbuf = NR_XMIT_EXTBUFF; - } + struct mp_priv *pmppriv = &adapter->mppriv; + struct rtw_mp_cal_arg *my_psd_arg = NULL; - /* Init xmit extension buff */ - _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); + u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0; + u32 fft = 0, avg = 0, iq_path = 0; + u32 psd_data = 0; - pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4); + my_psd_arg = _rtw_malloc(sizeof(struct rtw_mp_cal_arg)); - if (pxmitpriv->pallocated_xmit_extbuf == NULL) { - res = _FAIL; - goto exit; + if (my_psd_arg) + _rtw_memset((void *)my_psd_arg, 0, sizeof(struct rtw_mp_cal_arg)); + else { + RTW_ERR("%s() psd_arg malloc fail !\n", __func__); + return 0; } - pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); + if (sscanf(data, "fft=%d,avg=%d,iq=%d", &fft, &avg, &iq_path) == 3) { - pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + my_psd_arg->path = pmppriv->antenna_trx; + my_psd_arg->iq_path = iq_path; + my_psd_arg->avg = avg; + my_psd_arg->fft = fft; - for (i = 0; i < num_xmit_extbuf; i++) { - _rtw_init_listhead(&pxmitbuf->list); + RTW_INFO("%s: PSD RF_Path:%d fft=%d,avg=%d,iq_path=%d !\n", + __func__, pmppriv->antenna_trx, fft, avg, iq_path); - pxmitbuf->priv_data = NULL; - pxmitbuf->padapter = padapter; - pxmitbuf->buf_tag = XMITBUF_MGNT; + if (rtw_mp_phl_psd_cmd(adapter, my_psd_arg, RTW_MP_CAL_CMD_PSD_INIT)) + RTW_INFO("PSD_INIT CMD OK!\n"); + else + RTW_INFO("PSD_INIT CMD FAIL!\n"); + } else if (strncmp(data, "restore", 7) == 0) { - res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE); - if (res == _FAIL) { - res = _FAIL; - goto exit; - } + my_psd_arg->path = pmppriv->antenna_trx; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pxmitbuf->phead = pxmitbuf->pbuf; - pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size; - pxmitbuf->len = 0; - pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; -#endif + if (rtw_mp_phl_psd_cmd(adapter, my_psd_arg, RTW_MP_CAL_CMD_PSD_RESTORE)) + RTW_INFO("PSD_RESTORE CMD OK!\n"); + else + RTW_INFO("PSD_RESTORE CMD FAIL!\n"); + } else { + if (sscanf(data, "pts=%d,start=%d,stop=%d", + &psd_pts, &psd_start, &psd_stop) == 3) { + my_psd_arg->upoint = psd_pts; + my_psd_arg->start_point = psd_start; + my_psd_arg->stop_point = psd_stop; + } else { + my_psd_arg->upoint = 1280; + my_psd_arg->start_point = 640; + my_psd_arg->stop_point = 960; + RTW_INFO("Default PSD setting!\n"); + } - rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); -#ifdef DBG_XMIT_BUF_EXT - pxmitbuf->no = i; -#endif - pxmitbuf++; + if (rtw_mp_phl_psd_cmd(adapter, my_psd_arg, RTW_MP_CAL_CMD_PSD_QUERY)) + RTW_INFO("PSD_QUERY CMD OK!\n"); + else + RTW_INFO("PSD_QUERY CMD FAIL!\n"); + data[0] = '\0'; + i = 0; + while (i < 320) { + sprintf(data, "%s%x ", data, (my_psd_arg->outbuf[i])); + i++; + } } - pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf; + if (my_psd_arg) + _rtw_mfree(my_psd_arg, sizeof(struct rtw_mp_cal_arg)); -exit: - ; + return strlen(data) + 1; } -#endif u8 mpt_to_mgnt_rate( @@ -2799,7 +2154,7 @@ mpt_to_mgnt_rate( } -u8 HwRateToMPTRate(u8 rate) +u8 rtw_mp_hwrate2mptrate(u8 rate) { u8 ret_rate = MGN_1M; @@ -3058,45 +2413,273 @@ u8 HwRateToMPTRate(u8 rate) break; default: - RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate); + RTW_INFO("hwrate_to_mrate(): Non supported Rate [%x]!!!\n", rate); break; } return ret_rate; } -u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr) -{ - u16 i = 0; - u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", - "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7", - "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15", - "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23", - "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31", - "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9", - "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9", - "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9", - "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9" - }; - - for (i = 0; i <= 83; i++) { - if (strcmp(targetStr, rateindex_Array[i]) == 0) { +static u16 srate2herate(u8 *str) +{ + + RTW_INFO("%s(): %s!!!\n", __func__, str); + if (!strcmp(str, "1M")) return HRATE_CCK1; + else if (!strcmp(str, "2M")) return HRATE_CCK2; + else if (!strcmp(str, "5.5M")) return HRATE_CCK5_5; + else if (!strcmp(str, "11M")) return HRATE_CCK11; + else if (!strcmp(str, "6M")) return HRATE_OFDM6; + else if (!strcmp(str, "9M")) return HRATE_OFDM9; + else if (!strcmp(str, "12M")) return HRATE_OFDM12; + else if (!strcmp(str, "18M")) return HRATE_OFDM18; + else if (!strcmp(str, "24M")) return HRATE_OFDM24; + else if (!strcmp(str, "36M")) return HRATE_OFDM36; + else if (!strcmp(str, "48M")) return HRATE_OFDM48; + else if (!strcmp(str, "54M")) return HRATE_OFDM54; + else if (!strcmp(str, "HTMCS0")) return HRATE_MCS0; + else if (!strcmp(str, "HTMCS1")) return HRATE_MCS1; + else if (!strcmp(str, "HTMCS2")) return HRATE_MCS2; + else if (!strcmp(str, "HTMCS3")) return HRATE_MCS3; + else if (!strcmp(str, "HTMCS4")) return HRATE_MCS4; + else if (!strcmp(str, "HTMCS5")) return HRATE_MCS5; + else if (!strcmp(str, "HTMCS6")) return HRATE_MCS6; + else if (!strcmp(str, "HTMCS7")) return HRATE_MCS7; + else if (!strcmp(str, "HTMCS8")) return HRATE_MCS8; + else if (!strcmp(str, "HTMCS9")) return HRATE_MCS9; + else if (!strcmp(str, "HTMCS10")) return HRATE_MCS10; + else if (!strcmp(str, "HTMCS11")) return HRATE_MCS11; + else if (!strcmp(str, "HTMCS12")) return HRATE_MCS12; + else if (!strcmp(str, "HTMCS13")) return HRATE_MCS13; + else if (!strcmp(str, "HTMCS14")) return HRATE_MCS14; + else if (!strcmp(str, "HTMCS15")) return HRATE_MCS15; + else if (!strcmp(str, "HTMCS16")) return HRATE_MCS16; + else if (!strcmp(str, "HTMCS17")) return HRATE_MCS17; + else if (!strcmp(str, "HTMCS18")) return HRATE_MCS18; + else if (!strcmp(str, "HTMCS19")) return HRATE_MCS19; + else if (!strcmp(str, "HTMCS20")) return HRATE_MCS20; + else if (!strcmp(str, "HTMCS21")) return HRATE_MCS21; + else if (!strcmp(str, "HTMCS22")) return HRATE_MCS22; + else if (!strcmp(str, "HTMCS23")) return HRATE_MCS23; + else if (!strcmp(str, "HTMCS24")) return HRATE_MCS24; + else if (!strcmp(str, "HTMCS25")) return HRATE_MCS25; + else if (!strcmp(str, "HTMCS26")) return HRATE_MCS26; + else if (!strcmp(str, "HTMCS27")) return HRATE_MCS27; + else if (!strcmp(str, "HTMCS28")) return HRATE_MCS28; + else if (!strcmp(str, "HTMCS29")) return HRATE_MCS29; + else if (!strcmp(str, "HTMCS30")) return HRATE_MCS30; + else if (!strcmp(str, "HTMCS31")) return HRATE_MCS31; + else if (!strcmp(str, "VHT1MCS0")) return HRATE_VHT_NSS1_MCS0; + else if (!strcmp(str, "VHT1MCS1")) return HRATE_VHT_NSS1_MCS1; + else if (!strcmp(str, "VHT1MCS2")) return HRATE_VHT_NSS1_MCS2; + else if (!strcmp(str, "VHT1MCS3")) return HRATE_VHT_NSS1_MCS3; + else if (!strcmp(str, "VHT1MCS4")) return HRATE_VHT_NSS1_MCS4; + else if (!strcmp(str, "VHT1MCS5")) return HRATE_VHT_NSS1_MCS5; + else if (!strcmp(str, "VHT1MCS6")) return HRATE_VHT_NSS1_MCS6; + else if (!strcmp(str, "VHT1MCS7")) return HRATE_VHT_NSS1_MCS7; + else if (!strcmp(str, "VHT1MCS8")) return HRATE_VHT_NSS1_MCS8; + else if (!strcmp(str, "VHT1MCS9")) return HRATE_VHT_NSS1_MCS9; + else if (!strcmp(str, "VHT2MCS0")) return HRATE_VHT_NSS2_MCS0; + else if (!strcmp(str, "VHT2MCS1")) return HRATE_VHT_NSS2_MCS1; + else if (!strcmp(str, "VHT2MCS2")) return HRATE_VHT_NSS2_MCS2; + else if (!strcmp(str, "VHT2MCS3")) return HRATE_VHT_NSS2_MCS3; + else if (!strcmp(str, "VHT2MCS4")) return HRATE_VHT_NSS2_MCS4; + else if (!strcmp(str, "VHT2MCS5")) return HRATE_VHT_NSS2_MCS5; + else if (!strcmp(str, "VHT2MCS6")) return HRATE_VHT_NSS2_MCS6; + else if (!strcmp(str, "VHT2MCS7")) return HRATE_VHT_NSS2_MCS7; + else if (!strcmp(str, "VHT2MCS8")) return HRATE_VHT_NSS2_MCS8; + else if (!strcmp(str, "VHT2MCS9")) return HRATE_VHT_NSS2_MCS9; + else if (!strcmp(str, "VHT3MCS0")) return HRATE_VHT_NSS3_MCS0; + else if (!strcmp(str, "VHT3MCS1")) return HRATE_VHT_NSS3_MCS1; + else if (!strcmp(str, "VHT3MCS2")) return HRATE_VHT_NSS3_MCS2; + else if (!strcmp(str, "VHT3MCS3")) return HRATE_VHT_NSS3_MCS3; + else if (!strcmp(str, "VHT3MCS4")) return HRATE_VHT_NSS3_MCS4; + else if (!strcmp(str, "VHT3MCS5")) return HRATE_VHT_NSS3_MCS5; + else if (!strcmp(str, "VHT3MCS6")) return HRATE_VHT_NSS3_MCS6; + else if (!strcmp(str, "VHT3MCS7")) return HRATE_VHT_NSS3_MCS7; + else if (!strcmp(str, "VHT3MCS8")) return HRATE_VHT_NSS3_MCS8; + else if (!strcmp(str, "VHT3MCS9")) return HRATE_VHT_NSS3_MCS9; + else if (!strcmp(str, "VHT4MCS0")) return HRATE_VHT_NSS4_MCS0; + else if (!strcmp(str, "VHT4MCS1")) return HRATE_VHT_NSS4_MCS1; + else if (!strcmp(str, "VHT4MCS2")) return HRATE_VHT_NSS4_MCS2; + else if (!strcmp(str, "VHT4MCS3")) return HRATE_VHT_NSS4_MCS3; + else if (!strcmp(str, "VHT4MCS4")) return HRATE_VHT_NSS4_MCS4; + else if (!strcmp(str, "VHT4MCS5")) return HRATE_VHT_NSS4_MCS5; + else if (!strcmp(str, "VHT4MCS6")) return HRATE_VHT_NSS4_MCS6; + else if (!strcmp(str, "VHT4MCS7")) return HRATE_VHT_NSS4_MCS7; + else if (!strcmp(str, "VHT4MCS8")) return HRATE_VHT_NSS4_MCS8; + else if (!strcmp(str, "VHT4MCS9")) return HRATE_VHT_NSS4_MCS9; + else if (!strcmp(str, "HE1MCS0")) return HRATE_HE_NSS1_MCS0; + else if (!strcmp(str, "HE1MCS1")) return HRATE_HE_NSS1_MCS1; + else if (!strcmp(str, "HE1MCS2")) return HRATE_HE_NSS1_MCS2; + else if (!strcmp(str, "HE1MCS3")) return HRATE_HE_NSS1_MCS3; + else if (!strcmp(str, "HE1MCS4")) return HRATE_HE_NSS1_MCS4; + else if (!strcmp(str, "HE1MCS5")) return HRATE_HE_NSS1_MCS5; + else if (!strcmp(str, "HE1MCS6")) return HRATE_HE_NSS1_MCS6; + else if (!strcmp(str, "HE1MCS7")) return HRATE_HE_NSS1_MCS7; + else if (!strcmp(str, "HE1MCS8")) return HRATE_HE_NSS1_MCS8; + else if (!strcmp(str, "HE1MCS9")) return HRATE_HE_NSS1_MCS9; + else if (!strcmp(str, "HE1MCS10")) return HRATE_HE_NSS1_MCS10; + else if (!strcmp(str, "HE1MCS11")) return HRATE_HE_NSS1_MCS11; + else if (!strcmp(str, "HE2MCS0")) return HRATE_HE_NSS2_MCS0; + else if (!strcmp(str, "HE2MCS1")) return HRATE_HE_NSS2_MCS1; + else if (!strcmp(str, "HE2MCS2")) return HRATE_HE_NSS2_MCS2; + else if (!strcmp(str, "HE2MCS3")) return HRATE_HE_NSS2_MCS3; + else if (!strcmp(str, "HE2MCS4")) return HRATE_HE_NSS2_MCS4; + else if (!strcmp(str, "HE2MCS5")) return HRATE_HE_NSS2_MCS5; + else if (!strcmp(str, "HE2MCS6")) return HRATE_HE_NSS2_MCS6; + else if (!strcmp(str, "HE2MCS7")) return HRATE_HE_NSS2_MCS7; + else if (!strcmp(str, "HE2MCS8")) return HRATE_HE_NSS2_MCS8; + else if (!strcmp(str, "HE2MCS9")) return HRATE_HE_NSS2_MCS9; + else if (!strcmp(str, "HE2MCS10")) return HRATE_HE_NSS2_MCS10; + else if (!strcmp(str, "HE2MCS11")) return HRATE_HE_NSS2_MCS11; + else if (!strcmp(str, "HE3MCS0")) return HRATE_HE_NSS3_MCS0; + else if (!strcmp(str, "HE3MCS1")) return HRATE_HE_NSS3_MCS1; + else if (!strcmp(str, "HE3MCS2")) return HRATE_HE_NSS3_MCS2; + else if (!strcmp(str, "HE3MCS3")) return HRATE_HE_NSS3_MCS3; + else if (!strcmp(str, "HE3MCS4")) return HRATE_HE_NSS3_MCS4; + else if (!strcmp(str, "HE3MCS5")) return HRATE_HE_NSS3_MCS5; + else if (!strcmp(str, "HE3MCS6")) return HRATE_HE_NSS3_MCS6; + else if (!strcmp(str, "HE3MCS7")) return HRATE_HE_NSS3_MCS7; + else if (!strcmp(str, "HE3MCS8")) return HRATE_HE_NSS3_MCS8; + else if (!strcmp(str, "HE3MCS9")) return HRATE_HE_NSS3_MCS9; + else if (!strcmp(str, "HE3MCS10")) return HRATE_HE_NSS3_MCS10; + else if (!strcmp(str, "HE3MCS11")) return HRATE_HE_NSS3_MCS11; + else if (!strcmp(str, "HE4MCS0")) return HRATE_HE_NSS4_MCS0; + else if (!strcmp(str, "HE4MCS1")) return HRATE_HE_NSS4_MCS1; + else if (!strcmp(str, "HE4MCS2")) return HRATE_HE_NSS4_MCS2; + else if (!strcmp(str, "HE4MCS3")) return HRATE_HE_NSS4_MCS3; + else if (!strcmp(str, "HE4MCS4")) return HRATE_HE_NSS4_MCS4; + else if (!strcmp(str, "HE4MCS5")) return HRATE_HE_NSS4_MCS5; + else if (!strcmp(str, "HE4MCS6")) return HRATE_HE_NSS4_MCS6; + else if (!strcmp(str, "HE4MCS7")) return HRATE_HE_NSS4_MCS7; + else if (!strcmp(str, "HE4MCS8")) return HRATE_HE_NSS4_MCS8; + else if (!strcmp(str, "HE4MCS9")) return HRATE_HE_NSS4_MCS9; + else if (!strcmp(str, "HE4MCS10")) return HRATE_HE_NSS4_MCS10; + else if (!strcmp(str, "HE4MCS11")) return HRATE_HE_NSS4_MCS11; + return 0; +} + +#define MP_RATE_STR_NUM 132 +#define MP_RATE_STR_LEN 12 +const char rtw_mp_rateidx_arrdef[MP_RATE_STR_NUM][MP_RATE_STR_LEN] = { + "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", + "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7", + "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15", + "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23", + "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31", + "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", + "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9", + "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", + "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9", + "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", + "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9", + "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", + "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9", + "HE1MCS0", "HE1MCS1", "HE1MCS2", "HE1MCS3", "HE1MCS4", "HE1MCS5", + "HE1MCS6", "HE1MCS7", "HE1MCS8", "HE1MCS9", "HE1MCS10", "HE1MCS11", + "HE2MCS0", "HE2MCS1", "HE2MCS2", "HE2MCS3", "HE2MCS4", "HE2MCS5", + "HE2MCS6", "HE2MCS7", "HE2MCS8", "HE2MCS9", "HE2MCS10", "HE2MCS11", + "HE3MCS0", "HE3MCS1", "HE3MCS2", "HE3MCS3", "HE3MCS4", "HE3MCS5", + "HE3MCS6", "HE3MCS7", "HE3MCS8", "HE3MCS9", "HE3MCS10", "HE3MCS11", + "HE4MCS0", "HE4MCS1", "HE4MCS2", "HE4MCS3", "HE4MCS4", "HE4MCS5", + "HE4MCS6", "HE4MCS7", "HE4MCS8", "HE4MCS9", "HE4MCS10", "HE4MCS11"}; + +u16 rtw_mp_rate_parse(_adapter *adapter, u8 *target_str) +{ + struct mp_priv *pmppriv = &adapter->mppriv; + + u16 i = 0, mcs_idx_base = 0; + u16 hrateidx = 0; + u8 plcp_nss = 0, ppdu_type = 0; + u8 user_idx = pmppriv->mp_plcp_useridx; + +#if 1/*def CONFIG_80211AX_HE*/ + hrateidx = srate2herate(target_str); + + if (MP_IS_1T_HRATE(hrateidx)) + plcp_nss = MP_NSS1; + else if (MP_IS_2T_HRATE(hrateidx)) + plcp_nss = MP_NSS2; + else if (MP_IS_3T_HRATE(hrateidx)) + plcp_nss = MP_NSS3; + else if (MP_IS_4T_HRATE(hrateidx)) + plcp_nss = MP_NSS4; + RTW_INFO("%s , PLCP NSS idx = %d\n", __func__ , plcp_nss); + + if (MP_IS_CCK_HRATE(hrateidx)) + ppdu_type = RTW_MP_TYPE_CCK; + else if (MP_IS_OFDM_HRATE(hrateidx)) { + ppdu_type = RTW_MP_TYPE_LEGACY; + mcs_idx_base = 4; + } else if (MP_IS_HT_HRATE(hrateidx)) { + ppdu_type = RTW_MP_TYPE_HT_MF; + mcs_idx_base = 12; + } else if (MP_IS_VHT_HRATE(hrateidx)) { + if (plcp_nss == MP_NSS1) + mcs_idx_base = 44; + else if (plcp_nss == MP_NSS2) + mcs_idx_base = 44 + 10; + else if (plcp_nss == MP_NSS3) + mcs_idx_base = 44 + 20; + else if (plcp_nss == MP_NSS4) + mcs_idx_base = 44 + 30; + + ppdu_type = RTW_MP_TYPE_VHT; + } else if (MP_IS_HE_HRATE(hrateidx)) { + if (plcp_nss == MP_NSS1) + mcs_idx_base = 84; + else if (plcp_nss == MP_NSS2) + mcs_idx_base = 84 + 12; + else if (plcp_nss == MP_NSS3) + mcs_idx_base = 84 + 24; + else if (plcp_nss == MP_NSS4) + mcs_idx_base = 84+ 36; + + ppdu_type = RTW_MP_TYPE_HE_SU; + } + + pmppriv->mp_plcp_user[user_idx].plcp_nss = plcp_nss; + pmppriv->rtw_mp_pmact_ppdu_type = ppdu_type; + rtw_update_giltf(adapter); + rtw_mp_update_coding(adapter); + + for (i = 0; i <= MP_RATE_STR_NUM; i++) { + if (strcmp(target_str, rtw_mp_rateidx_arrdef[i+ mcs_idx_base]) == 0) { + pmppriv->mp_plcp_user[user_idx].plcp_mcs = i; + RTW_INFO("%s , PLCP MCS = %d\n", __func__ , pmppriv->mp_plcp_user[user_idx].plcp_mcs); + break; + } + } + + if (1) { + printk("%s ,please input a Data RATE String as:", __func__); + for (i = 0; i <= MP_RATE_STR_NUM; i++) { + printk("%s ", rtw_mp_rateidx_arrdef[i]); + if (i % 10 == 0) + printk("\n"); + } + } + return hrateidx; +#else + for (i = 0; i <= MP_RATE_STR_NUM; i++) { + if (strcmp(targetStr, rtw_mp_rateidx_arrdef[i]) == 0) { RTW_INFO("%s , index = %d\n", __func__ , i); return i; } } printk("%s ,please input a Data RATE String as:", __func__); - for (i = 0; i <= 83; i++) { - printk("%s ", rateindex_Array[i]); + for (i = 0; i <= MP_RATE_STR_NUM; i++) { + printk("%s ", rtw_mp_rateidx_arrdef[i]); if (i % 10 == 0) printk("\n"); } return _FAIL; +#endif } -u8 rtw_mp_mode_check(PADAPTER pAdapter) +u8 rtw_mp_mode_check(_adapter *adapter) { - PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter); + _adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter); if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE) return _TRUE; @@ -3112,27 +2695,25 @@ bool rtw_is_mp_tssitrk_on(_adapter *adapter) } u32 mpt_ProQueryCalTxPower( - PADAPTER pAdapter, + _adapter *adapter, u8 RfPath ) { - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - + PMPT_CONTEXT pMptCtx = &(adapter->mppriv.mpt_ctx); +#if 0 u32 TxPower = 1; struct txpwr_idx_comp tic; u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); RATE_SECTION rs = mgn_rate_to_rs(mgn_rate); - TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate - , pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic); + TxPower = rtw_hal_get_tx_power_index(adapter, RfPath, rs, mgn_rate + , pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, &tic); - dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath + dump_tx_power_index_inline(RTW_DBGDUMP, RfPath , pHalData->current_channel_bw, pHalData->current_channel , mgn_rate, TxPower, &tic); - pAdapter->mppriv.txpoweridx = (u8)TxPower; + adapter->mppriv.txpoweridx = (u8)TxPower; if (RfPath == RF_PATH_A) pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower; else if (RfPath == RF_PATH_B) @@ -3141,851 +2722,764 @@ u32 mpt_ProQueryCalTxPower( pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower; else if (RfPath == RF_PATH_D) pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower; - hal_mpt_SetTxPower(pAdapter); - - return TxPower; + hal_mpt_SetTxPower(adapter); + return TxPower; +#endif + return 0; } -u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path) +u32 mpt_get_tx_power_finalabs_val(_adapter *padapter, u8 rf_path) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); u32 powerdbm = 0; +#ifdef CONFIG_80211AX_HE + struct mp_priv *pmppriv = &padapter->mppriv; + struct rtw_mp_txpwr_arg ptxpwr_arg; + u16 i = 0; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.mp_class = RTW_MP_CLASS_TXPWR; + ptxpwr_arg.cmd = RTW_MP_TXPWR_CMD_READ_PWR_TABLE; + + ptxpwr_arg.channel = pmppriv->channel; + ptxpwr_arg.bandwidth = pmppriv->bandwidth; + ptxpwr_arg.rate = pmppriv->rateidx; + ptxpwr_arg.rfpath = pmppriv->antenna_tx; + ptxpwr_arg.beamforming = 0; + ptxpwr_arg.dcm = 0; + ptxpwr_arg.offset = 0; + + rtw_mp_set_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + + while (i != 100) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + if (ptxpwr_arg.cmd_ok && ptxpwr_arg.status == RTW_PHL_STATUS_SUCCESS) { + powerdbm = ptxpwr_arg.table_item; + RTW_INFO("%s,SET CMD OK\n", __func__); + break; + } else { + if (i > 100) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__, ptxpwr_arg.status); + break; + } + i++; + } + } +#else +/* powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel); - RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n", pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm); - +*/ +#endif return powerdbm; } -#ifdef CONFIG_MP_VHT_HW_TX_MODE -static inline void dump_buf(u8 *buf, u32 len) +u8 rtw_mpt_set_power_limit_en(_adapter *padapter, bool en_val) { - u32 i; + struct rtw_mp_txpwr_arg ptxpwr_arg; + u16 i = 0; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.mp_class = RTW_MP_CLASS_TXPWR; + ptxpwr_arg.cmd = RTW_MP_TXPWR_CMD_SET_PWR_LMT_EN; + + ptxpwr_arg.pwr_lmt_en = en_val; + + rtw_mp_set_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + + while (i != 10) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + if (ptxpwr_arg.cmd_ok && ptxpwr_arg.status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD OK\n", __func__); + return ptxpwr_arg.cmd_ok; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__, ptxpwr_arg.status); + break; + } + i++; + } + } - RTW_INFO("-----------------Len %d----------------\n", len); - for (i = 0; i < len; i++) - RTW_INFO("%2.2x-", *(buf + i)); - RTW_INFO("\n"); + return 0; } -void ByteToBit( - u8 *out, - bool *in, - u8 in_size) +bool rtw_mpt_get_power_limit_en(_adapter *padapter) { - u8 i = 0, j = 0; + struct rtw_mp_txpwr_arg ptxpwr_arg; + u16 i = 0; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); - for (i = 0; i < in_size; i++) { - for (j = 0; j < 8; j++) { - if (in[8 * i + j]) - out[i] |= (1 << j); + ptxpwr_arg.mp_class = RTW_MP_CLASS_TXPWR; + ptxpwr_arg.cmd = RTW_MP_TXPWR_CMD_GET_PWR_LMT_EN; + ptxpwr_arg.pwr_lmt_en = _FALSE; + + rtw_mp_set_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + + while (i != 10) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)&ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + if (ptxpwr_arg.cmd_ok && ptxpwr_arg.status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s, CMD OK\n", __func__); + return ptxpwr_arg.pwr_lmt_en; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", + __func__, ptxpwr_arg.status); + break; + } + i++; } } -} + return ptxpwr_arg.pwr_lmt_en; +} -void CRC16_generator( - bool *out, - bool *in, - u8 in_size -) +void rtw_mp_get_phl_cmd(_adapter *padapter, void* buf, u32 buflen) { - u8 i = 0; - bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; - - for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/ - temp = in[i] ^ reg[15]; - reg[15] = reg[14]; - reg[14] = reg[13]; - reg[13] = reg[12]; - reg[12] = reg[11]; - reg[11] = reg[10]; - reg[10] = reg[9]; - reg[9] = reg[8]; - reg[8] = reg[7]; - - reg[7] = reg[6]; - reg[6] = reg[5]; - reg[5] = reg[4]; - reg[4] = reg[3]; - reg[3] = reg[2]; - reg[2] = reg[1]; - reg[1] = reg[0]; - reg[12] = reg[12] ^ temp; - reg[5] = reg[5] ^ temp; - reg[0] = temp; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct phl_info_t *phl_info = (struct phl_info_t *)(dvobj->phl); + struct rtw_mp_test_cmdbuf *cmdbuf = NULL; + + if (buflen > RTW_MAX_TEST_CMD_BUF) { + RTW_ERR("%s, buflen %d over CMD BUF Size !\n", __func__, buflen); + return; } - for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/ - out[i] = 1 - reg[15 - i]; -} + cmdbuf = _rtw_malloc(sizeof(struct rtw_mp_test_cmdbuf)); + if (cmdbuf) { + _rtw_memset((void *)cmdbuf, 0, sizeof(struct rtw_mp_test_cmdbuf)); + cmdbuf->type = 0; + cmdbuf->len = buflen; + _rtw_memcpy((void *)cmdbuf->buf, buf, buflen); + rtw_phl_test_submodule_get_rpt(rtw_phl_get_com(phl_info), (void *)cmdbuf, sizeof(struct rtw_mp_test_cmdbuf)); + _rtw_memcpy((void *)buf, (void *)cmdbuf->buf, buflen); + } + if (cmdbuf) + _rtw_mfree(cmdbuf, sizeof(struct rtw_mp_test_cmdbuf)); +} -/*======================================== - SFD SIGNAL SERVICE LENGTH CRC - 16 bit 8 bit 8 bit 16 bit 16 bit -========================================*/ -void CCK_generator( - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo -) +void rtw_mp_set_phl_cmd(_adapter *padapter, void* buf, u32 buflen) { - double ratio = 0; - bool crc16_in[32] = {0}, crc16_out[16] = {0}; - bool LengthExtBit; - double LengthExact; - double LengthPSDU; - u8 i; - u32 PacketLength = pPMacTxInfo->PacketLength; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct phl_info_t *phl_info = (struct phl_info_t *)(dvobj->phl); + struct rtw_mp_test_cmdbuf *cmdbuf = NULL; - if (pPMacTxInfo->bSPreamble) - pPMacTxInfo->SFD = 0x05CF; - else - pPMacTxInfo->SFD = 0xF3A0; - - switch (pPMacPktInfo->MCS) { - case 0: - pPMacTxInfo->SignalField = 0xA; - ratio = 8; - /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/ - crc16_in[1] = crc16_in[3] = 1; - break; - case 1: - pPMacTxInfo->SignalField = 0x14; - ratio = 4; - /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/ - crc16_in[2] = crc16_in[4] = 1; - break; - case 2: - pPMacTxInfo->SignalField = 0x37; - ratio = 8.0 / 5.5; - /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/ - crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1; - break; - case 3: - pPMacTxInfo->SignalField = 0x6E; - ratio = 8.0 / 11.0; - /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/ - crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1; - break; + if (buflen > RTW_MAX_TEST_CMD_BUF) { + RTW_ERR("%s, buflen %d over CMD BUF Size !\n", __func__, buflen); + return; } - LengthExact = PacketLength * ratio; - LengthPSDU = ceil(LengthExact); + cmdbuf = _rtw_malloc(sizeof(struct rtw_mp_test_cmdbuf)); - if ((pPMacPktInfo->MCS == 3) && - ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727)) - LengthExtBit = 1; - else - LengthExtBit = 0; + if (cmdbuf) { + _rtw_memset((void *)cmdbuf, 0, sizeof(struct rtw_mp_test_cmdbuf)); + cmdbuf->type = 0; + cmdbuf->len = buflen; + _rtw_memcpy((void *)cmdbuf->buf, buf, buflen); + rtw_phl_test_submodule_cmd_process(rtw_phl_get_com(phl_info), (void*)cmdbuf, sizeof(struct rtw_mp_test_cmdbuf)); + } + if (cmdbuf) + _rtw_mfree(cmdbuf, sizeof(struct rtw_mp_test_cmdbuf)); +} - pPMacTxInfo->LENGTH = (u32)LengthPSDU; - /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/ - for (i = 0; i < 16; i++) - crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1; +u8 rtw_mp_phl_txpower(_adapter *padapter, struct rtw_mp_txpwr_arg *ptxpwr_arg, u8 cmdid) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u16 i = 0; - if (LengthExtBit == 0) { - pPMacTxInfo->ServiceField = 0x0; - /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/ - } else { - pPMacTxInfo->ServiceField = 0x80; - /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/ - crc16_in[15] = 1; - } + ptxpwr_arg->mp_class = RTW_MP_CLASS_TXPWR; + ptxpwr_arg->cmd = cmdid; - CRC16_generator(crc16_out, crc16_in, 32); + rtw_mp_set_phl_cmd(padapter, (void*)ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); - _rtw_memset(pPMacTxInfo->CRC16, 0, 2); - ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2); + while (i <= 10) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)ptxpwr_arg, sizeof(struct rtw_mp_txpwr_arg)); + if (ptxpwr_arg->cmd_ok && ptxpwr_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD OK\n", __func__); + break; + } else { + if (i > 10) { + RTW_DBG("%s,GET CMD FAIL !!! status %d\n", __func__, ptxpwr_arg->status); + break; + } + i++; + } + } + return ptxpwr_arg->cmd_ok; } - -void PMAC_Get_Pkt_Param( - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo) +bool rtw_mp_phl_config_arg(_adapter *padapter, enum rtw_mp_config_cmdid cmdid) { + struct mp_priv *pmppriv = &padapter->mppriv; + struct rtw_mp_config_arg pmp_arg; + u16 i = 0; - u8 TX_RATE_HEX = 0, MCS = 0; - u8 TX_RATE = pPMacTxInfo->TX_RATE; + _rtw_memset((void *)&pmp_arg, 0, sizeof(struct rtw_mp_config_arg)); - /* TX_RATE & Nss */ - if (MPT_IS_2SS_RATE(TX_RATE)) - pPMacPktInfo->Nss = 2; - else if (MPT_IS_3SS_RATE(TX_RATE)) - pPMacPktInfo->Nss = 3; - else if (MPT_IS_4SS_RATE(TX_RATE)) - pPMacPktInfo->Nss = 4; - else - pPMacPktInfo->Nss = 1; + pmp_arg.mp_class = RTW_MP_CLASS_CONFIG; + pmp_arg.cmd = cmdid; + RTW_INFO("%s, id: %d !!!\n", __func__, cmdid); - RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss); + switch (cmdid) { + case RTW_MP_CONFIG_CMD_SET_CH_BW: + pmp_arg.channel = pmppriv->channel; + pmp_arg.bandwidth = pmppriv->bandwidth; + pmp_arg.sc_idx = pmppriv->prime_channel_offset; + break; + case RTW_MP_CONFIG_CMD_SET_RATE_IDX: + pmp_arg.rate_idx= pmppriv->rateidx; + break; + case RTW_MP_CONFIG_CMD_SET_RF_TXRX_PATH: + pmp_arg.ant_tx = pmppriv->antenna_trx; + pmp_arg.ant_rx = pmppriv->antenna_trx; + break; + case RTW_MP_CONFIG_CMD_STOP_DUT: + case RTW_MP_CONFIG_CMD_START_DUT: + case RTW_MP_CONFIG_CMD_SET_PHY_INDEX: + pmp_arg.cur_phy = pmppriv->rtw_mp_cur_phy; + break; + case RTW_MP_CONFIG_CMD_SET_RESET_PHY_COUNT: + case RTW_MP_CONFIG_CMD_SET_RESET_MAC_COUNT: + case RTW_MP_CONFIG_CMD_SET_RESET_DRV_COUNT: + pmp_arg.cur_phy = pmppriv->rtw_mp_cur_phy; + break; + case RTW_MP_CONFIG_CMD_SWITCH_BT_PATH: + pmp_arg.btc_mode = pmppriv->btc_path; + break; + default: + RTW_INFO("%s, No CMD case match !!!\n", __func__); + return _FALSE; + } - /* MCS & TX_RATE_HEX*/ - if (MPT_IS_CCK_RATE(TX_RATE)) { - switch (TX_RATE) { - case MPT_RATE_1M: - TX_RATE_HEX = MCS = 0; - break; - case MPT_RATE_2M: - TX_RATE_HEX = MCS = 1; - break; - case MPT_RATE_55M: - TX_RATE_HEX = MCS = 2; - break; - case MPT_RATE_11M: - TX_RATE_HEX = MCS = 3; + rtw_mp_set_phl_cmd(padapter, (void*)&pmp_arg, sizeof(struct rtw_mp_config_arg)); + while (1) { + rtw_mp_get_phl_cmd(padapter, (void*)&pmp_arg, sizeof(struct rtw_mp_config_arg)); + if (pmp_arg.cmd_ok && pmp_arg.status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s, %d GET CMD OK !!!\n", __func__, cmdid); break; + } else { + i++; + rtw_msleep_os(10); + if (i == 100) { + RTW_INFO("%s, %d GET CMD FAIL !!!\n", __func__, cmdid); + break; + } } - } else if (MPT_IS_OFDM_RATE(TX_RATE)) { - MCS = TX_RATE - MPT_RATE_6M; - TX_RATE_HEX = MCS + 4; - } else if (MPT_IS_HT_RATE(TX_RATE)) { - MCS = TX_RATE - MPT_RATE_MCS0; - TX_RATE_HEX = MCS + 12; - } else if (MPT_IS_VHT_RATE(TX_RATE)) { - TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44; - - if (MPT_IS_VHT_2S_RATE(TX_RATE)) - MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0; - else if (MPT_IS_VHT_3S_RATE(TX_RATE)) - MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0; - else if (MPT_IS_VHT_4S_RATE(TX_RATE)) - MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0; - else - MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0; } + return pmp_arg.cmd_ok; +} - pPMacPktInfo->MCS = MCS; - pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX; - - RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX); - /* mSTBC & Nsts*/ - pPMacPktInfo->Nsts = pPMacPktInfo->Nss; - if (pPMacTxInfo->bSTBC) { - if (pPMacPktInfo->Nss == 1) { - pPMacTxInfo->m_STBC = 2; - pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2; - } else - pPMacTxInfo->m_STBC = 1; - } else - pPMacTxInfo->m_STBC = 1; +void rtw_mp_phl_rx_physts(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, bool bstart) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u8 i = 0; + + rx_arg->mp_class = RTW_MP_CLASS_RX; + rx_arg->cmd = RTW_MP_RX_CMD_GET_PHYSTS; + rx_arg->enable = bstart; + + rx_arg->cmd_ok = _FALSE; + rtw_mp_set_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + + while (i != 10) { + rtw_msleep_os(100); + rtw_mp_get_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + if (rx_arg->cmd_ok && rx_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,GET CMD RX OK\n", __func__); + break; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__,rx_arg->status); + break; + } + i++; + } + } } +void rtw_mp_phl_rx_rssi(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u8 i = 0; + + rx_arg->mp_class = RTW_MP_CLASS_RX; + rx_arg->cmd = RTW_MP_RX_CMD_GET_RSSI; -u32 LDPC_parameter_generator( - u32 N_pld_int, - u32 N_CBPSS, - u32 N_SS, - u32 R, - u32 m_STBC, - u32 N_TCB_int -) + rx_arg->cmd_ok = _FALSE; + rtw_mp_set_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + + while (i != 10) { + rtw_msleep_os(100); + rtw_mp_get_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + if (rx_arg->cmd_ok && rx_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,Path%d rssi:%d GET CMD RX OK\n", __func__, rx_arg->rf_path, rx_arg->rssi); + break; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__,rx_arg->status); + break; + } + i++; + } + } +} + +void rtw_mp_phl_rx_gain_offset(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, u8 path_num) { - double CR = 0.; - double N_pld = (double)N_pld_int; - double N_TCB = (double)N_TCB_int; - double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.; - double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.; - double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.; - double R_eff = 0.; - u32 VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/ - - if (R == 0) - CR = 0.5; - else if (R == 1) - CR = 2. / 3.; - else if (R == 2) - CR = 3. / 4.; - else if (R == 3) - CR = 5. / 6.; - - if (N_TCB <= 648.) { - N_CW = 1.; - if (N_TCB >= N_pld + 912.*(1. - CR)) - L_LDPC = 1296.; - else - L_LDPC = 648.; - } else if (N_TCB <= 1296.) { - N_CW = 1.; - if (N_TCB >= (double)N_pld + 1464.*(1. - CR)) - L_LDPC = 1944.; - else - L_LDPC = 1296.; - } else if (N_TCB <= 1944.) { - N_CW = 1.; - L_LDPC = 1944.; - } else if (N_TCB <= 2592.) { - N_CW = 2.; - if (N_TCB >= N_pld + 2916.*(1. - CR)) - L_LDPC = 1944.; - else - L_LDPC = 1296.; - } else { - N_CW = ceil(N_pld / 1944. / CR); - L_LDPC = 1944.; + struct mp_priv *pmppriv = &padapter->mppriv; + u8 all_path_num = path_num; + u8 rf_path = 0; + + rx_arg->mp_class = RTW_MP_CLASS_RX; + rx_arg->cmd = RTW_MP_RX_CMD_SET_GAIN_OFFSET; + + if (path_num > 1) { + path_num = 0; + all_path_num -= 1; + } + + for (rf_path = path_num; rf_path <= all_path_num; rf_path++) { + u16 i = 0; + + rx_arg->rf_path = rf_path; + rx_arg->cmd_ok = _FALSE; + rtw_mp_set_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + + while (i != 10) { + rtw_msleep_os(100); + rtw_mp_get_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + if (rx_arg->cmd_ok && rx_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,rf path %d GET CMD RX OK\n", __func__, rx_arg->rf_path); + break; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__,rx_arg->status); + break; + } + i++; + } + } } - /* Number of information bits per CW*/ - K_LDPC = L_LDPC * CR; - /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/ - N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.; - /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/ - N_spcw = rtfloor(N_shrt / N_CW); - /* The first N_fshrt CWs shorten 1 bit more*/ - N_fshrt = (double)((int)N_shrt % (int)N_CW); - /* Number of data bits for the last N_CW-N_fshrt CWs*/ - L_LDPC_info = K_LDPC - N_spcw; - /* Number of puncturing bits*/ - N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.; - if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) || - (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) { - /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/ - VHTSIGA2B3 = 1; - N_TCB += (double)N_CBPSS * N_SS * m_STBC; - N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.; - } else - VHTSIGA2B3 = 0; - - return VHTSIGA2B3; -} /* function end of LDPC_parameter_generator */ - -/*======================================== - Data field of PPDU - Get N_sym and SIGA2BB3 -========================================*/ -void PMAC_Nsym_generator( - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo) -{ - u32 SIGA2B3 = 0; - u8 TX_RATE = pPMacTxInfo->TX_RATE; - - u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3}; - double CR = 0; - u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8}; - u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0; - int D_R = 0; - - RTW_INFO("TX_RATE = %d\n", TX_RATE); - /* N_SD*/ - if (pPMacTxInfo->BandWidth == 0) - N_SD = 52; - else if (pPMacTxInfo->BandWidth == 1) - N_SD = 108; - else - N_SD = 234; +} - if (MPT_IS_HT_RATE(TX_RATE)) { - u8 MCS_temp; - if (pPMacPktInfo->MCS > 23) - MCS_temp = pPMacPktInfo->MCS - 24; - else if (pPMacPktInfo->MCS > 15) - MCS_temp = pPMacPktInfo->MCS - 16; - else if (pPMacPktInfo->MCS > 7) - MCS_temp = pPMacPktInfo->MCS - 8; - else - MCS_temp = pPMacPktInfo->MCS; +void rtw_mp_phl_query_rx(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg ,u8 rx_qurey_type) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u8 rxcmd[2] = {0, 0}; + u8 cmd_idx = 0; + + rx_arg->mp_class = RTW_MP_CLASS_RX; + rx_arg->rx_ok = 0; + rx_arg->rx_err = 0; + + if (rx_qurey_type == 0) { + rxcmd[0] = RTW_MP_RX_CMD_PHY_CRC_OK; + rxcmd[1] = RTW_MP_RX_CMD_PHY_CRC_ERR; + } else if (rx_qurey_type == 1) { + rxcmd[0] = RTW_MP_RX_CMD_MAC_CRC_OK; + rxcmd[1] = RTW_MP_RX_CMD_MAC_CRC_ERR; + } else if (rx_qurey_type == 2) { + rxcmd[0] = RTW_MP_RX_CMD_DRV_CRC_OK; + rxcmd[1] = RTW_MP_RX_CMD_DRV_CRC_ERR; + } + + for (cmd_idx = 0; cmd_idx < 2 ; cmd_idx++) { + u16 i = 0; + + rx_arg->cmd = rxcmd[cmd_idx]; + rx_arg->cmd_ok = _FALSE; + rtw_mp_set_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + + while (i != 10) { + rtw_msleep_os(100); + rtw_mp_get_phl_cmd(padapter, (void*)rx_arg, sizeof(struct rtw_mp_rx_arg)); + if (rx_arg->cmd_ok && rx_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,GET CMD RX OK:%d ,RX ERR:%d\n", __func__, rx_arg->rx_ok, rx_arg->rx_err); + break; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__,rx_arg->status); + break; + } + i++; + } + } + } +} - R = R_list[MCS_temp]; +void rtw_mp_set_crystal_cap(_adapter *padapter, u32 xcapvalue) +{ + struct rtw_mp_reg_arg cfg_arg; + u8 sc_xo_idx = 1; + u8 i = 0; - switch (R) { - case 0: - CR = .5; - break; - case 1: - CR = 2. / 3.; - break; - case 2: - CR = 3. / 4.; - break; - case 3: - CR = 5. / 6.; - break; + cfg_arg.mp_class = RTW_MP_CLASS_REG; + cfg_arg.cmd = RTW_MP_REG_CMD_SET_XCAP; + + for (i <=0 ; i <= sc_xo_idx; i++) { + cfg_arg.cmd_ok = 0; + cfg_arg.sc_xo = i; + cfg_arg.io_value = xcapvalue; + rtw_mp_set_phl_cmd(padapter, (void*)&cfg_arg, sizeof(struct rtw_mp_reg_arg)); + + while (i != 10) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)&cfg_arg, sizeof(struct rtw_mp_reg_arg)); + if (cfg_arg.cmd_ok && cfg_arg.status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD TX OK\n", __func__); + break; + } else { + if (i > 10) { + RTW_INFO("%s,GET CMD FAIL !!! status %d\n", __func__, cfg_arg.status); + break; + } + i++; + } } + } - N_BPSC = N_BPSC_list[MCS_temp]; - N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss; - N_DBPS = (u32)((double)N_CBPS * CR); +} - if (pPMacTxInfo->bLDPC == FALSE) { - N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.); - RTW_INFO("N_ES = %d\n", N_ES); +u8 rtw_mp_phl_calibration(_adapter *padapter, struct rtw_mp_cal_arg *pcal_arg, u8 cmdid) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + u16 i = 0; + u32 cmd_size = sizeof(struct rtw_mp_cal_arg); - /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/ - N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / - (double)(N_DBPS * pPMacTxInfo->m_STBC)); + pcal_arg->mp_class = RTW_MP_CLASS_CAL; + pcal_arg->cmd = cmdid; - } else { - N_ES = 1; - /* N_pld = length * 8 + 16*/ - N_pld = pPMacTxInfo->PacketLength * 8 + 16; - RTW_INFO("N_pld = %d\n", N_pld); - N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) / - (double)(N_DBPS * pPMacTxInfo->m_STBC)); - RTW_INFO("N_SYM = %d\n", N_SYM); - /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/ - N_TCB = N_CBPS * N_SYM; - RTW_INFO("N_TCB = %d\n", N_TCB); - SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB); - RTW_INFO("SIGA2B3 = %d\n", SIGA2B3); - N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC; - RTW_INFO("N_SYM = %d\n", N_SYM); - } - } else if (MPT_IS_VHT_RATE(TX_RATE)) { - R = R_list[pPMacPktInfo->MCS]; + rtw_mp_set_phl_cmd(padapter, (void*)pcal_arg, cmd_size); - switch (R) { - case 0: - CR = .5; - break; - case 1: - CR = 2. / 3.; - break; - case 2: - CR = 3. / 4.; + while (i <= 10) { + rtw_msleep_os(10); + rtw_mp_get_phl_cmd(padapter, (void*)pcal_arg, cmd_size); + if (pcal_arg->cmd_ok && pcal_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,SET CMD OK\n", __func__); break; - case 3: - CR = 5. / 6.; - break; - } - N_BPSC = N_BPSC_list[pPMacPktInfo->MCS]; - N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss; - N_DBPS = (u32)((double)N_CBPS * CR); - if (pPMacTxInfo->bLDPC == FALSE) { - if (pPMacTxInfo->bSGI) - N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.); - else - N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.); - /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/ - N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC)); - SIGA2B3 = 0; } else { - N_ES = 1; - /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/ - N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC)); - /* N_avbits = N_sys_init * N_CBPS*/ - N_TCB = N_CBPS * N_SYM; - /* N_pld = N_sys_init * N_DBPS*/ - N_pld = N_SYM * N_DBPS; - SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB); - N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC; + if (i > 10) { + RTW_DBG("%s,GET CMD FAIL !!! status %d\n", __func__, pcal_arg->status); + break; + } + i++; } + } - switch (R) { - case 0: - D_R = 2; - break; - case 1: - D_R = 3; - break; - case 2: - D_R = 4; - break; - case 3: - D_R = 6; - break; + return pcal_arg->cmd_ok; +} + + +u8 rtw_update_giltf(_adapter *padapter) +{ + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 idx = 0; + u8 ppdu_type = pmp_priv->rtw_mp_pmact_ppdu_type; + u8 user_idx = pmp_priv->mp_plcp_useridx; + + RTW_INFO("%s: ppdu_type=%s\n", __func__ , PPDU_TYPE_STR(pmp_priv->rtw_mp_pmact_ppdu_type)); + if (ppdu_type == RTW_MP_TYPE_HT_MF || ppdu_type == RTW_MP_TYPE_HT_GF + || ppdu_type == RTW_MP_TYPE_VHT) { + pmp_priv->st_giltf[0].gi = 0; + pmp_priv->st_giltf[0].ltf = 0; + strcpy(pmp_priv->st_giltf[0].type_str, "0.4"); + pmp_priv->st_giltf[1].gi = 1; + pmp_priv->st_giltf[1].ltf = 0; + strcpy(pmp_priv->st_giltf[1].type_str, "0.8"); + idx = 1; + } else if (ppdu_type > RTW_MP_TYPE_VHT) { + if (ppdu_type == RTW_MP_TYPE_HE_SU || ppdu_type == RTW_MP_TYPE_HE_ER_SU) { + + if (!pmp_priv->mp_plcp_user[user_idx].dcm && !pmp_priv->rtw_mp_stbc) { + pmp_priv->st_giltf[0].gi = 1; + pmp_priv->st_giltf[0].ltf = 0; + strcpy(pmp_priv->st_giltf[0].type_str, "1x 0.8"); + pmp_priv->st_giltf[1].gi = 1; + pmp_priv->st_giltf[1].ltf = 1; + strcpy(pmp_priv->st_giltf[1].type_str, "2x 0.8"); + pmp_priv->st_giltf[2].gi = 2; + pmp_priv->st_giltf[2].ltf = 1; + strcpy(pmp_priv->st_giltf[2].type_str, "2x 1.6"); + pmp_priv->st_giltf[3].gi = 3; + pmp_priv->st_giltf[3].ltf = 2; + strcpy(pmp_priv->st_giltf[3].type_str, "4x 3.2"); + pmp_priv->st_giltf[4].gi = 1; + pmp_priv->st_giltf[4].ltf = 2; + strcpy(pmp_priv->st_giltf[4].type_str, "4x 0.8"); + idx = 4; + } else { + pmp_priv->st_giltf[0].gi = 1; + pmp_priv->st_giltf[0].ltf = 0; + strcpy(pmp_priv->st_giltf[0].type_str, "1x 0.8"); + pmp_priv->st_giltf[1].gi = 1; + pmp_priv->st_giltf[1].ltf = 1; + strcpy(pmp_priv->st_giltf[1].type_str, "2x 0.8"); + pmp_priv->st_giltf[2].gi = 2; + pmp_priv->st_giltf[2].ltf = 1; + strcpy(pmp_priv->st_giltf[2].type_str, "2x 1.6"); + pmp_priv->st_giltf[3].gi = 3; + pmp_priv->st_giltf[3].ltf = 2; + strcpy(pmp_priv->st_giltf[3].type_str, "4x 3.2"); + idx = 3; + } + }else if (ppdu_type == RTW_MP_TYPE_HE_MU_OFDMA) { + pmp_priv->st_giltf[0].gi = 1; + pmp_priv->st_giltf[0].ltf = 1; + strcpy(pmp_priv->st_giltf[0].type_str, "2x 0.8"); + pmp_priv->st_giltf[1].gi = 2; + pmp_priv->st_giltf[1].ltf = 1; + strcpy(pmp_priv->st_giltf[1].type_str, "2x 1.6"); + pmp_priv->st_giltf[2].gi = 1; + pmp_priv->st_giltf[2].ltf = 2; + strcpy(pmp_priv->st_giltf[2].type_str, "4x 0.8"); + pmp_priv->st_giltf[3].gi = 3; + pmp_priv->st_giltf[3].ltf = 2; + strcpy(pmp_priv->st_giltf[3].type_str, "4x 3.2"); + idx = 3; + } else if (ppdu_type == RTW_MP_TYPE_HE_TB) { + pmp_priv->st_giltf[0].gi = 2; + pmp_priv->st_giltf[0].ltf = 0; + strcpy(pmp_priv->st_giltf[0].type_str, "1x 1.6"); + pmp_priv->st_giltf[1].gi = 2; + pmp_priv->st_giltf[1].ltf = 1; + strcpy(pmp_priv->st_giltf[1].type_str, "2x 1.6"); + pmp_priv->st_giltf[2].gi = 3; + pmp_priv->st_giltf[2].ltf = 2; + strcpy(pmp_priv->st_giltf[2].type_str, "4x 3.2"); + idx = 2; + } } + return idx; +} - if (((N_CBPS / N_ES) % D_R) != 0) { - RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth); - return; - } +void rtw_mp_update_coding(_adapter *padapter) +{ + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 ppdu_type = pmp_priv->rtw_mp_pmact_ppdu_type; + u8 user_idx = pmp_priv->mp_plcp_useridx; + + if (ppdu_type == RTW_MP_TYPE_HE_SU || pmp_priv->bandwidth >= CHANNEL_WIDTH_40 || + pmp_priv->rtw_mp_ru_tone >= MP_RU_TONE_484) { - RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth); + RTW_INFO("%s, PPDU HE SU , over 40M, RU Tone over 484\n", __func__); + pmp_priv->mp_plcp_user[user_idx].coding = 1;/* 1 LDPC, 0 BCC */ + } else if (ppdu_type == RTW_MP_TYPE_HE_MU_OFDMA) { + + RTW_INFO("%s, PPDU HE MU\n", __func__); + pmp_priv->mp_plcp_user[user_idx].coding = 0;/* 1 LDPC, 0 BCC */ } - pPMacPktInfo->N_sym = N_SYM; - pPMacPktInfo->SIGA2B3 = SIGA2B3; + RTW_INFO("%s, coding: %s\n", __func__, (pmp_priv->mp_plcp_user[user_idx].coding?"LDPC":"BCC")); } -/*======================================== - L-SIG Rate R Length P Tail - 4b 1b 12b 1b 6b -========================================*/ - -void L_SIG_generator( - u32 N_SYM, /* Max: 750*/ - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo) +u8 rtw_mp_update_ru_tone(_adapter *padapter) { - u8 sig_bi[24] = {0}; /* 24 BIT*/ - u32 mode, LENGTH; - int i; + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 user_idx = pmp_priv->mp_plcp_useridx; + u8 cur_coding = pmp_priv->mp_plcp_user[user_idx].coding; + u8 ruidx = MP_RU_TONE_26; + u8 i = 0 , j = 0; - if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) { - mode = pPMacPktInfo->MCS; - LENGTH = pPMacTxInfo->PacketLength; + if (cur_coding == 0) {/* 1 LDPC, 0 BCC */ + ruidx = MP_RU_TONE_242; + if (pmp_priv->rtw_mp_ru_tone < MP_RU_TONE_242) + pmp_priv->rtw_mp_ru_tone = MP_RU_TONE_242; } else { - u8 N_LTF; - double T_data; - u32 OFDM_symbol; + ruidx = MP_RU_TONE_26; + } - mode = 0; + for (i = 0; i <= 5; i++) { + pmp_priv->ru_tone_sel_list[i] = ruidx++; + if (ruidx > MP_RU_TONE_966) + break; + } + return i; +} - /* Table 20-13 Num of HT-DLTFs request*/ - if (pPMacPktInfo->Nsts <= 2) - N_LTF = pPMacPktInfo->Nsts; - else - N_LTF = 4; +u8 rtw_mp_update_ru_alloc(_adapter *padapter) +{ + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 cur_tone = pmp_priv->rtw_mp_ru_tone; + u8 i = 0; + u8 alloc_start = 0, alloc_end = 0; + u8 user_idx = pmp_priv->mp_plcp_useridx; + + switch (cur_tone) { + case MP_RU_TONE_26: + alloc_start = 0; + alloc_end = 9; + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + alloc_end = 18; + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_80) + alloc_end = 37; + break; + case MP_RU_TONE_52: + alloc_start = 37; + alloc_end = 41; + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + alloc_end = 45; + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_80) + alloc_end = 53; + + break; + case MP_RU_TONE_106: + alloc_start = 53; + alloc_end = 55; + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + alloc_end = 57; + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_80) + alloc_end = 61; + + break; + case MP_RU_TONE_242: + alloc_start = 61; + alloc_end = 61; + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + alloc_end = 62; + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_80) + alloc_end = 64; + + break; + case MP_RU_TONE_484: + alloc_start = 65; + alloc_end = 66; + break; + case MP_RU_TONE_966: + alloc_start = 67; + alloc_end = 67; + break; + }; + + if (pmp_priv->mp_plcp_user[user_idx].ru_alloc < alloc_start || + pmp_priv->mp_plcp_user[user_idx].ru_alloc > alloc_end) + pmp_priv->mp_plcp_user[user_idx].ru_alloc = alloc_start; + + for (i = 0; i < 68; i++) { + if (alloc_start + i > alloc_end) + break; + pmp_priv->ru_alloc_list[i] = alloc_start + i; + RTW_INFO("%s, Ru alloc:%d\n", __func__, pmp_priv->ru_alloc_list[i]); - if (pPMacTxInfo->bSGI) - T_data = 3.6; - else - T_data = 4.0; + } + return i; +} - /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/ - if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE)) - OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.); - else - OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.); +u32 rtw_mp_get_tssi_de(_adapter *padapter, u8 rf_path) +{ + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &padapter->mppriv; - RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol); - LENGTH = OFDM_symbol * 3 - 3; - RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH); + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); - } - /* Rate Field*/ - switch (mode) { - case 0: - sig_bi[0] = 1; - sig_bi[1] = 1; - sig_bi[2] = 0; - sig_bi[3] = 1; - break; - case 1: - sig_bi[0] = 1; - sig_bi[1] = 1; - sig_bi[2] = 1; - sig_bi[3] = 1; - break; - case 2: - sig_bi[0] = 0; - sig_bi[1] = 1; - sig_bi[2] = 0; - sig_bi[3] = 1; - break; - case 3: - sig_bi[0] = 0; - sig_bi[1] = 1; - sig_bi[2] = 1; - sig_bi[3] = 1; - break; - case 4: - sig_bi[0] = 1; - sig_bi[1] = 0; - sig_bi[2] = 0; - sig_bi[3] = 1; - break; - case 5: - sig_bi[0] = 1; - sig_bi[1] = 0; - sig_bi[2] = 1; - sig_bi[3] = 1; - break; - case 6: - sig_bi[0] = 0; - sig_bi[1] = 0; - sig_bi[2] = 0; - sig_bi[3] = 1; - break; - case 7: - sig_bi[0] = 0; - sig_bi[1] = 0; - sig_bi[2] = 1; - sig_bi[3] = 1; - break; - } - /*Reserved bit*/ - sig_bi[4] = 0; + ptxpwr_arg.rfpath = rf_path; - /* Length Field*/ - for (i = 0; i < 12; i++) - sig_bi[i + 5] = (LENGTH >> i) & 1; + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_GET_TSSI)) + return ptxpwr_arg.tssi; + else + return 0; +} - /* Parity Bit*/ - sig_bi[17] = 0; - for (i = 0; i < 17; i++) - sig_bi[17] = sig_bi[17] + sig_bi[i]; +s32 rtw_mp_get_online_tssi_de(_adapter *padapter, s32 out_pwr, s32 tgdbm, u8 rf_path) +{ + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &padapter->mppriv; - sig_bi[17] %= 2; + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); - /* Tail Field*/ - for (i = 18; i < 24; i++) - sig_bi[i] = 0; + ptxpwr_arg.dbm = tgdbm; + ptxpwr_arg.pout = out_pwr; + ptxpwr_arg.rfpath = rf_path; - /* dump_buf(sig_bi,24);*/ - _rtw_memset(pPMacTxInfo->LSIG, 0, 3); - ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3); + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_GET_ONLINE_TSSI_DE)) + return ptxpwr_arg.online_tssi_de; + else + return 0; } - -void CRC8_generator( - bool *out, - bool *in, - u8 in_size -) +u8 rtw_mp_set_tsside2verify(_adapter *padapter, u32 tssi_de, u8 rf_path) { + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &padapter->mppriv; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); u8 i = 0; - bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1}; - - for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/ - temp = in[i] ^ reg[7]; - reg[7] = reg[6]; - reg[6] = reg[5]; - reg[5] = reg[4]; - reg[4] = reg[3]; - reg[3] = reg[2]; - reg[2] = reg[1] ^ temp; - reg[1] = reg[0] ^ temp; - reg[0] = temp; - } - for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/ - out[i] = reg[7 - i] ^ 1; -} - -/*/================================================================================ - HT-SIG1 MCS CW Length 24BIT + 24BIT - 7b 1b 16b - HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail - 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b -================================================================================*/ -void HT_SIG_generator( - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo -) + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.tssi = tssi_de; + ptxpwr_arg.rfpath = rf_path; + + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_TSSI)) + return true; + else + return false; +} + +u8 rtw_mp_set_tssi_offset(_adapter *padapter, u32 tssi_offset, u8 rf_path) { - u32 i; - bool sig_bi[48] = {0}, crc8[8] = {0}; - /* MCS Field*/ - for (i = 0; i < 7; i++) - sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1; - /* Packet BW Setting*/ - sig_bi[7] = pPMacTxInfo->BandWidth; - /* HT-Length Field*/ - for (i = 0; i < 16; i++) - sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1; - /* Smoothing; 1->allow smoothing*/ - sig_bi[24] = 1; - /*Not Sounding*/ - sig_bi[25] = 1 - pPMacTxInfo->NDP_sound; - /*Reserved bit*/ - sig_bi[26] = 1; - /*/Aggregate*/ - sig_bi[27] = 0; - /*STBC Field*/ - if (pPMacTxInfo->bSTBC) { - sig_bi[28] = 1; - sig_bi[29] = 0; - } else { - sig_bi[28] = 0; - sig_bi[29] = 0; - } - /*Advance Coding, 0: BCC, 1: LDPC*/ - sig_bi[30] = pPMacTxInfo->bLDPC; - /* Short GI*/ - sig_bi[31] = pPMacTxInfo->bSGI; - /* N_ELTFs*/ - if (pPMacTxInfo->NDP_sound == FALSE) { - sig_bi[32] = 0; - sig_bi[33] = 0; - } else { - int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss; + struct rtw_mp_txpwr_arg ptxpwr_arg; + struct mp_priv *pmppriv = &padapter->mppriv; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + u8 i = 0; - for (i = 0; i < 2; i++) - sig_bi[32 + i] = (N_ELTF >> i) % 2; - } - /* CRC-8*/ - CRC8_generator(crc8, sig_bi, 34); - - for (i = 0; i < 8; i++) - sig_bi[34 + i] = crc8[i]; - - /*Tail*/ - for (i = 42; i < 48; i++) - sig_bi[i] = 0; - - _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6); - ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6); -} - - -/*====================================================================================== - VHT-SIG-A1 - BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved - 2b 1b 1b 6b 3b 9b 1b 2b 1b - VHT-SIG-A2 - SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail - 1b 1b 1b 1b 4b 1b 1b 8b 6b -======================================================================================*/ -void VHT_SIG_A_generator( - PRT_PMAC_TX_INFO pPMacTxInfo, - PRT_PMAC_PKT_INFO pPMacPktInfo) -{ - u32 i; - bool sig_bi[48], crc8[8]; - - _rtw_memset(sig_bi, 0, 48); - _rtw_memset(crc8, 0, 8); - - /* BW Setting*/ - for (i = 0; i < 2; i++) - sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1; - /* Reserved Bit*/ - sig_bi[2] = 1; - /*STBC Field*/ - sig_bi[3] = pPMacTxInfo->bSTBC; - /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */ - for (i = 0; i < 6; i++) - sig_bi[4 + i] = 0; - /* N_STS/Partial AID*/ - for (i = 0; i < 12; i++) { - if (i < 3) - sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1; - else - sig_bi[10 + i] = 0; - } - /*TXOP_PS_NOT_ALLPWED*/ - sig_bi[22] = 0; - /*Reserved Bits*/ - sig_bi[23] = 1; - /*Short GI*/ - sig_bi[24] = pPMacTxInfo->bSGI; - if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9) - sig_bi[25] = 1; + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + ptxpwr_arg.tssi_de_offset = tssi_offset; + ptxpwr_arg.rfpath = rf_path; + + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_TSSI_OFFSET)) + return true; else - sig_bi[25] = 0; - /* SU/MU[0] Coding*/ - sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */ - sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/ - /*SU MCS/MU[1-3] Coding*/ - for (i = 0; i < 4; i++) - sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1; - /*SU Beamform */ - sig_bi[32] = 0; /*packet.TXBF_en;*/ - /*Reserved Bit*/ - sig_bi[33] = 1; - /*CRC-8*/ - CRC8_generator(crc8, sig_bi, 34); - for (i = 0; i < 8; i++) - sig_bi[34 + i] = crc8[i]; - /*Tail*/ - for (i = 42; i < 48; i++) - sig_bi[i] = 0; - - _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6); - ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6); -} - -/*====================================================================================== - VHT-SIG-B - Length Resesrved Trail - 17/19/21 BIT 3/2/2 BIT 6b -======================================================================================*/ -void VHT_SIG_B_generator( - PRT_PMAC_TX_INFO pPMacTxInfo) -{ - bool sig_bi[32], crc8_bi[8]; - u32 i, len, res, tail = 6, total_len, crc8_in_len; - u32 sigb_len; - - _rtw_memset(sig_bi, 0, 32); - _rtw_memset(crc8_bi, 0, 8); - - /*Sounding Packet*/ - if (pPMacTxInfo->NDP_sound == 1) { - if (pPMacTxInfo->BandWidth == 0) { - bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}; - - _rtw_memcpy(sig_bi, sigb_temp, 26); - } else if (pPMacTxInfo->BandWidth == 1) { - bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0}; - - _rtw_memcpy(sig_bi, sigb_temp, 27); - } else if (pPMacTxInfo->BandWidth == 2) { - bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}; - - _rtw_memcpy(sig_bi, sigb_temp, 29); - } - } else { /* Not NDP Sounding*/ - bool *sigb_temp[29] = {0}; - - if (pPMacTxInfo->BandWidth == 0) { - len = 17; - res = 3; - } else if (pPMacTxInfo->BandWidth == 1) { - len = 19; - res = 2; - } else if (pPMacTxInfo->BandWidth == 2) { - len = 21; - res = 2; - } else { - len = 21; - res = 2; - } - total_len = len + res + tail; - crc8_in_len = len + res; - - /*Length Field*/ - sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2; - - for (i = 0; i < len; i++) - sig_bi[i] = (sigb_len >> i) & 0x1; - /*Reserved Field*/ - for (i = 0; i < res; i++) - sig_bi[len + i] = 1; - /* CRC-8*/ - CRC8_generator(crc8_bi, sig_bi, crc8_in_len); - - /* Tail */ - for (i = 0; i < tail; i++) - sig_bi[len + res + i] = 0; - } + return false; +} + +u8 rtw_mp_set_tssi_pwrtrk(_adapter *padapter, u8 tssi_state) +{ + struct rtw_mp_txpwr_arg ptxpwr_arg; - _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4); - ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4); + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); - pPMacTxInfo->VHT_SIG_B_CRC = 0; - ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1); + ptxpwr_arg.txpwr_track_status = tssi_state; + + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_SET_PWR_TRACK_STATUS)) + return true; + else + return false; } -/*======================= - VHT Delimiter -=======================*/ -void VHT_Delimiter_generator( - PRT_PMAC_TX_INFO pPMacTxInfo -) +u8 rtw_mp_get_tssi_pwrtrk(_adapter *padapter) { - bool sig_bi[32] = {0}, crc8[8] = {0}; - u32 crc8_in_len = 16; - u32 PacketLength = pPMacTxInfo->PacketLength; - int j; - - /* Delimiter[0]: EOF*/ - sig_bi[0] = 1; - /* Delimiter[1]: Reserved*/ - sig_bi[1] = 0; - /* Delimiter[3:2]: MPDU Length High*/ - sig_bi[2] = ((PacketLength - 4) >> 12) % 2; - sig_bi[3] = ((PacketLength - 4) >> 13) % 2; - /* Delimiter[15:4]: MPDU Length Low*/ - for (j = 4; j < 16; j++) - sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2; - CRC8_generator(crc8, sig_bi, crc8_in_len); - for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/ - sig_bi[j] = crc8[j - 16]; - for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/ - sig_bi[j] = (78 >> (j - 24)) % 2; - - _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4); - ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4); + struct rtw_mp_txpwr_arg ptxpwr_arg; + u8 tssi_state = RTW_MP_TSSI_OFF; + + _rtw_memset((void *)&ptxpwr_arg, 0, sizeof(struct rtw_mp_txpwr_arg)); + + if (rtw_mp_phl_txpower(padapter, &ptxpwr_arg, RTW_MP_TXPWR_CMD_GET_PWR_TRACK_STATUS)) { + tssi_state = ptxpwr_arg.txpwr_track_status; + RTW_INFO("%s, get tssi_state = %d\n", __func__, tssi_state); + } else + RTW_INFO("%s, rtw_mp_phl_txpower fail\n", __func__); + + return tssi_state; } #endif -#endif diff --git a/core/rtw_p2p.c b/core/rtw_p2p.c index 24372de..f4452a7 100644 --- a/core/rtw_p2p.c +++ b/core/rtw_p2p.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,503 +18,16 @@ #ifdef CONFIG_P2P -int rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt) -{ - int found = 0, i = 0; - - for (i = 0; i < ch_cnt; i++) { - if (ch_list[i] == desired_ch) { - found = 1; - break; - } - } - return found ; -} - -int is_any_client_associated(_adapter *padapter) -{ - return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE; -} - -static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) -{ - _irqL irqL; - _list *phead, *plist; - u32 len = 0; - u16 attr_len = 0; - u8 tmplen, *pdata_attr, *pstart, *pcur; - struct sta_info *psta = NULL; - _adapter *padapter = pwdinfo->padapter; - struct sta_priv *pstapriv = &padapter->stapriv; - - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); - - pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); - - if (NULL == pdata_attr) { - RTW_INFO("%s pdata_attr malloc failed\n", __FUNCTION__); - goto _exit; - } - - pstart = pdata_attr; - pcur = pdata_attr; - - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - phead = &pstapriv->asoc_list; - plist = get_next(phead); - - /* look up sta asoc_queue */ - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - - plist = get_next(plist); - - - if (psta->is_p2p_device) { - tmplen = 0; - - pcur++; - - /* P2P device address */ - _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN); - pcur += ETH_ALEN; - - /* P2P interface address */ - _rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN); - pcur += ETH_ALEN; - - *pcur = psta->dev_cap; - pcur++; - - /* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */ - RTW_PUT_BE16(pcur, psta->config_methods); - pcur += 2; - - _rtw_memcpy(pcur, psta->primary_dev_type, 8); - pcur += 8; - - *pcur = psta->num_of_secdev_type; - pcur++; - - _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8); - pcur += psta->num_of_secdev_type * 8; - - if (psta->dev_name_len > 0) { - /* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ - RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME); - pcur += 2; - - /* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */ - RTW_PUT_BE16(pcur, psta->dev_name_len); - pcur += 2; - - _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len); - pcur += psta->dev_name_len; - } - - - tmplen = (u8)(pcur - pstart); - - *pstart = (tmplen - 1); - - attr_len += tmplen; - - /* pstart += tmplen; */ - pstart = pcur; - - } - - - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - if (attr_len > 0) - len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr); - - rtw_mfree(pdata_attr, MAX_P2P_IE_LEN); - -_exit: - return len; - -} - -static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) -{ - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - _adapter *padapter = pwdinfo->padapter; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame */ - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_GO_DISC_REQUEST; - u8 dialogToken = 0; - - RTW_INFO("[%s]\n", __FUNCTION__); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* Build P2P action frame header */ - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - /* there is no IE in this P2P action frame */ - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - -} - -static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) -{ - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - _adapter *padapter = pwdinfo->padapter; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_DEVDISC_RESP; - u8 p2pie[8] = { 0x00 }; - u32 p2pielen = 0; - - RTW_INFO("[%s]\n", __FUNCTION__); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* Build P2P public action frame header */ - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - - /* Build P2P IE */ - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* P2P_ATTR_STATUS */ - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen); - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - -} - -static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method) -{ - _adapter *padapter = pwdinfo->padapter; - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u8 dialogToken = frame_body[7]; /* The Dialog Token of provisioning discovery request frame. */ - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_PROVISION_DISC_RESP; - u8 wpsie[100] = { 0x00 }; - u8 wpsielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) + #error "Linux kernel version is too old to enable CONFIG_P2P" #endif - - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - wpsielen = 0; - /* WPS OUI */ - /* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */ - RTW_PUT_BE32(wpsie, WPSOUI); - wpsielen += 4; - -#if 0 - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; - - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; - - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ -#endif - - /* Config Method */ - /* Type: */ - /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */ - RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD); - wpsielen += 2; - - /* Length: */ - /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */ - RTW_PUT_BE16(wpsie + wpsielen, 0x0002); - wpsielen += 2; - - /* Value: */ - /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */ - RTW_PUT_BE16(wpsie + wpsielen, config_method); - wpsielen += 2; - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); - -#ifdef CONFIG_WFD - wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; +#ifndef CONFIG_IOCTL_CFG80211 + #error "Enable CONFIG_P2P without CONFIG_IOCTL_CFG80211" #endif - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - - return; - -} - -static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) -{ - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - _adapter *padapter = pwdinfo->padapter; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame */ - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_PRESENCE_RESPONSE; - u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; - u8 noa_attr_content[32] = { 0x00 }; - u32 p2pielen = 0; - - RTW_INFO("[%s]\n", __FUNCTION__); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; - - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); - - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* Build P2P action frame header */ - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); - - - /* Add P2P IE header */ - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Add Status attribute in P2P IE */ - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); - - /* Add NoA attribute in P2P IE */ - noa_attr_content[0] = 0x1;/* index */ - noa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */ - - /* todo: Notice of Absence Descriptor(s) */ - - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content); - - - - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen)); - - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - -} - -u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +int is_any_client_associated(_adapter *padapter) { - u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; - u16 capability = 0; - u32 len = 0, p2pielen = 0; - - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - - /* According to the P2P Specification, the beacon frame should contain 3 P2P attributes */ - /* 1. P2P Capability */ - /* 2. P2P Device ID */ - /* 3. Notice of Absence ( NOA ) */ - - /* P2P Capability ATTR */ - /* Type: */ - /* Length: */ - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - /* Be able to participate in additional P2P Groups and */ - /* support the P2P Invitation Procedure */ - /* Group Capability Bitmap, 1 byte */ - capability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY; - capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) - capability |= (P2P_GRPCAP_GROUP_FORMATION << 8); - - capability = cpu_to_le16(capability); - - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability); - - - /* P2P Device ID ATTR */ - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr); - - - /* Notice of Absence ATTR */ - /* Type: */ - /* Length: */ - /* Value: */ - - /* go_add_noa_attr(pwdinfo); */ - - - pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); - - - return len; - + return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE; } #ifdef CONFIG_WFD @@ -527,7 +40,7 @@ u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -641,7 +154,7 @@ u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -753,7 +266,7 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; u16 v16 = 0; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -784,46 +297,36 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel /* WFD device information */ /* WFD primary sink + available for WFD session + WiFi Direct mode */ - if (_TRUE == pwdinfo->session_available) { - if (P2P_ROLE_GO == pwdinfo->role) { - if (is_any_client_associated(pwdinfo->padapter)) { - if (pwdinfo->wfd_tdls_enable) { - /* TDLS mode + WSD ( WFD Service Discovery ) */ - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; - RTW_PUT_BE16(wfdie + wfdielen, v16); - } else { - /* WiFi Direct mode + WSD ( WFD Service Discovery ) */ - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; - RTW_PUT_BE16(wfdie + wfdielen, v16); - } + if (P2P_ROLE_GO == pwdinfo->role) { + if (is_any_client_associated(pwdinfo->padapter)) { + if (pwdinfo->wfd_tdls_enable) { + /* TDLS mode + WSD ( WFD Service Discovery ) */ + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { - if (pwdinfo->wfd_tdls_enable) { - /* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */ - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; - RTW_PUT_BE16(wfdie + wfdielen, v16); - } else { - /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; - RTW_PUT_BE16(wfdie + wfdielen, v16); - } + /* WiFi Direct mode + WSD ( WFD Service Discovery ) */ + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } else { if (pwdinfo->wfd_tdls_enable) { - /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + /* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; RTW_PUT_BE16(wfdie + wfdielen, v16); } else { /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; RTW_PUT_BE16(wfdie + wfdielen, v16); } } } else { if (pwdinfo->wfd_tdls_enable) { - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; RTW_PUT_BE16(wfdie + wfdielen, v16); } else { - v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; RTW_PUT_BE16(wfdie + wfdielen, v16); } } @@ -940,7 +443,7 @@ u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; u16 val16 = 0; u32 len = 0, wfdielen = 0; - _adapter *padapter = NULL; + _adapter *padapter = NULL; struct mlme_priv *pmlmepriv = NULL; struct wifi_display_info *pwfd_info = NULL; @@ -948,10 +451,11 @@ u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) pmlmepriv = &padapter->mlmepriv; pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + /* Only P2P GC need to include the WFD IE in the association request */ + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) goto exit; /* WFD OUI */ @@ -1050,7 +554,7 @@ u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1149,7 +653,7 @@ u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1248,7 +752,7 @@ u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1348,7 +852,7 @@ u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1448,7 +952,7 @@ u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1561,7 +1065,7 @@ u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1674,7 +1178,7 @@ u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1774,7 +1278,7 @@ u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) goto exit; /* WFD OUI */ @@ -1865,391 +1369,70 @@ u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) } #endif /* CONFIG_WFD */ -u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) { - u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; - u32 len = 0, p2pielen = 0; - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20100907 */ - /* According to the P2P Specification, the probe response frame should contain 5 P2P attributes */ - /* 1. P2P Capability */ - /* 2. Extended Listen Timing */ - /* 3. Notice of Absence ( NOA ) ( Only GO needs this ) */ - /* 4. Device Info */ - /* 5. Group Info ( Only GO need this ) */ - - /* P2P Capability ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */ - RTW_PUT_LE16(p2pie + p2pielen, 0x0002); - p2pielen += 2; + u8 *p; + u32 ret = _FALSE; + u8 *p2pie; + u32 p2pielen = 0; + int ssid_len = 0, rate_cnt = 0; - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); - /* Group Capability Bitmap, 1 byte */ - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - p2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS); + if (rate_cnt <= 4) { + int i, g_rate = 0; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) - p2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION; + for (i = 0; i < rate_cnt; i++) { + if (((*(p + 2 + i) & 0xff) != 0x02) && + ((*(p + 2 + i) & 0xff) != 0x04) && + ((*(p + 2 + i) & 0xff) != 0x0B) && + ((*(p + 2 + i) & 0xff) != 0x16)) + g_rate = 1; + } - p2pielen++; - } else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; - else - p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; + if (g_rate == 0) { + /* There is no OFDM rate included in SupportedRates IE of this probe request frame */ + /* The driver should response this probe request. */ + return ret; + } + } else { + /* rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */ + /* We should proceed the following check for this probe request. */ } - /* Extended Listen Timing ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */ - RTW_PUT_LE16(p2pie + p2pielen, 0x0004); - p2pielen += 2; + /* Added comments by Albert 20100906 */ + /* There are several items we should check here. */ + /* 1. This probe request frame must contain the P2P IE. (Done) */ + /* 2. This probe request frame must contain the wildcard SSID. (Done) */ + /* 3. Wildcard BSSID. (Todo) */ + /* 4. Destination Address. ( Done in mgt_dispatcher function ) */ + /* 5. Requested Device Type in WSC IE. (Todo) */ + /* 6. Device ID attribute in P2P IE. (Todo) */ - /* Value: */ - /* Availability Period */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */ - RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); - p2pielen += 2; + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); - /* Availability Interval */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */ - RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); - p2pielen += 2; + ssid_len &= 0xff; /* Just last 1 byte is valid for ssid len of the probe request */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen); + if (p2pie) { + if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) { + /* todo: */ + /* Check Requested Device Type attributes in WSC IE. */ + /* Check Device ID attribute in P2P IE */ + ret = _TRUE; + } else if ((p != NULL) && (ssid_len == 0)) + ret = _TRUE; + } else { + /* non -p2p device */ + } - /* Notice of Absence ATTR */ - /* Type: */ - /* Length: */ - /* Value: */ - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* go_add_noa_attr(pwdinfo); */ } - /* Device Info ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */ - RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); - p2pielen += ETH_ALEN; - - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */ - RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm); - p2pielen += 2; - - { - /* Primary Device Type */ - /* Category ID */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; - - /* OUI */ - /* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */ - RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); - p2pielen += 4; - - /* Sub Category ID */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; - } - - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ - - /* Device Name */ - /* Type: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); - p2pielen += 2; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */ - RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; - - /* Group Info ATTR */ - /* Type: */ - /* Length: */ - /* Value: */ - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) - p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen); - - - pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); - - - return len; - -} - -u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr) -{ - u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; - u32 len = 0, p2pielen = 0; - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* Commented by Albert 20110301 */ - /* According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */ - /* 1. P2P Capability */ - /* 2. Device Info */ - /* 3. Group ID ( When joining an operating P2P Group ) */ - - /* P2P Capability ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */ - RTW_PUT_LE16(p2pie + p2pielen, 0x0002); - p2pielen += 2; - - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; - - /* Group Capability Bitmap, 1 byte */ - if (pwdinfo->persistent_supported) - p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; - else - p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; - - - /* Device Info ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; - - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */ - RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - /* P2P Device Address */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); - p2pielen += ETH_ALEN; - - /* Config Method */ - /* This field should be big endian. Noted by P2P specification. */ - if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) { - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC); - } else { - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY); - } - - p2pielen += 2; - - /* Primary Device Type */ - /* Category ID */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); - p2pielen += 2; - - /* OUI */ - /* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */ - RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); - p2pielen += 4; - - /* Sub Category ID */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); - p2pielen += 2; - - /* Number of Secondary Device Types */ - p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ - - /* Device Name */ - /* Type: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ - RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); - p2pielen += 2; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */ - RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); - p2pielen += 2; - - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); - p2pielen += pwdinfo->device_name_len; - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { - /* Added by Albert 2011/05/19 */ - /* In this case, the pdev_raddr is the device address of the group owner. */ - - /* P2P Group ID ATTR */ - /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; - - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */ - RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen); - p2pielen += 2; - - /* Value: */ - _rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN); - p2pielen += ETH_ALEN; - - _rtw_memcpy(p2pie + p2pielen, pssid, ussidlen); - p2pielen += ussidlen; - - } - - pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); - - - return len; - -} - - -u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code) -{ - u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; - u32 len = 0, p2pielen = 0; - - /* P2P OUI */ - p2pielen = 0; - p2pie[p2pielen++] = 0x50; - p2pie[p2pielen++] = 0x6F; - p2pie[p2pielen++] = 0x9A; - p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ - - /* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */ - /* 1. Status */ - /* 2. Extended Listen Timing (optional) */ - - - /* Status ATTR */ - p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code); - - - /* Extended Listen Timing ATTR */ - /* Type: */ - /* Length: */ - /* Value: */ - - - pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); - - return len; - -} - -u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) -{ - u32 len = 0; - - return len; -} - -u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - u8 *p; - u32 ret = _FALSE; - u8 *p2pie; - u32 p2pielen = 0; - int ssid_len = 0, rate_cnt = 0; - - p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, - len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); - - if (rate_cnt <= 4) { - int i, g_rate = 0; - - for (i = 0; i < rate_cnt; i++) { - if (((*(p + 2 + i) & 0xff) != 0x02) && - ((*(p + 2 + i) & 0xff) != 0x04) && - ((*(p + 2 + i) & 0xff) != 0x0B) && - ((*(p + 2 + i) & 0xff) != 0x16)) - g_rate = 1; - } - - if (g_rate == 0) { - /* There is no OFDM rate included in SupportedRates IE of this probe request frame */ - /* The driver should response this probe request. */ - return ret; - } - } else { - /* rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */ - /* We should proceed the following check for this probe request. */ - } - - /* Added comments by Albert 20100906 */ - /* There are several items we should check here. */ - /* 1. This probe request frame must contain the P2P IE. (Done) */ - /* 2. This probe request frame must contain the wildcard SSID. (Done) */ - /* 3. Wildcard BSSID. (Todo) */ - /* 4. Destination Address. ( Done in mgt_dispatcher function ) */ - /* 5. Requested Device Type in WSC IE. (Todo) */ - /* 6. Device ID attribute in P2P IE. (Todo) */ - - p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, - len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); - - ssid_len &= 0xff; /* Just last 1 byte is valid for ssid len of the probe request */ - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen); - if (p2pie) { - if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) { - /* todo: */ - /* Check Requested Device Type attributes in WSC IE. */ - /* Check Device ID attribute in P2P IE */ - - ret = _TRUE; - } else if ((p != NULL) && (ssid_len == 0)) - ret = _TRUE; - } else { - /* non -p2p device */ - } - - } - - - return ret; + return ret; } @@ -2275,845 +1458,101 @@ u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint l ie_offset = _REASOCREQ_IE_OFFSET_; ies = pframe + WLAN_HDR_A3_LEN + ie_offset; - ies_len = len - WLAN_HDR_A3_LEN - ie_offset; - - p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); - - if (!p2p_ie) { - RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__); - status_code = P2P_STATUS_FAIL_INVALID_PARAM; - } else - RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__); - - while (p2p_ie) { - /* Check P2P Capability ATTR */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { - RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__); - cap_attr = le16_to_cpu(cap_attr); - psta->dev_cap = cap_attr & 0xff; - } - - /* Check Extended Listen Timing ATTR */ - - - /* Check P2P Device Info ATTR */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) { - RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__); - pattr_content = pbuf = rtw_zmalloc(attr_contentlen); - if (pattr_content) { - u8 num_of_secdev_type; - u16 dev_name_len; - - - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen); - - _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);/* P2P Device Address */ - - pattr_content += ETH_ALEN; - - _rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */ - psta->config_methods = be16_to_cpu(psta->config_methods); - - pattr_content += 2; - - _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); - - pattr_content += 8; - - num_of_secdev_type = *pattr_content; - pattr_content += 1; - - if (num_of_secdev_type == 0) - psta->num_of_secdev_type = 0; - else { - u32 len; - - psta->num_of_secdev_type = num_of_secdev_type; - - len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8); - - _rtw_memcpy(psta->secdev_types_list, pattr_content, len); - - pattr_content += (num_of_secdev_type * 8); - } - - - /* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */ - psta->dev_name_len = 0; - if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) { - dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2)); - - psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len; - - _rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len); - } - - rtw_mfree(pbuf, attr_contentlen); - - } - - } - - /* Get the next P2P IE */ - p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); - - } - - return status_code; - -} - -u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - u8 *frame_body; - u8 status, dialogToken; - struct sta_info *psta = NULL; - _adapter *padapter = pwdinfo->padapter; - struct sta_priv *pstapriv = &padapter->stapriv; - u8 *p2p_ie; - u32 p2p_ielen = 0; - - frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - - dialogToken = frame_body[7]; - status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; - - p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); - if (p2p_ie) { - u8 groupid[38] = { 0x00 }; - u8 dev_addr[ETH_ALEN] = { 0x00 }; - u32 attr_contentlen = 0; - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { - if (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) && - _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) { - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) { - _irqL irqL; - _list *phead, *plist; - - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - phead = &pstapriv->asoc_list; - plist = get_next(phead); - - /* look up sta asoc_queue */ - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - - plist = get_next(plist); - - if (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) && - _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) { - - /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ - /* issue GO Discoverability Request */ - issue_group_disc_req(pwdinfo, psta->cmn.mac_addr); - /* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ - - status = P2P_STATUS_SUCCESS; - - break; - } else - status = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - } else - status = P2P_STATUS_FAIL_INVALID_PARAM; - - } else - status = P2P_STATUS_FAIL_INVALID_PARAM; - - } - - } - - - /* issue Device Discoverability Response */ - issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); - - - return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE; - -} - -u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - return _TRUE; -} - -u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - u8 *frame_body; - u8 *wpsie; - uint wps_ielen = 0, attr_contentlen = 0; - u16 uconfig_method = 0; - - - frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - - wpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen); - if (wpsie) { - if (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) { - uconfig_method = be16_to_cpu(uconfig_method); - switch (uconfig_method) { - case WPS_CM_DISPLYA: { - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); - break; - } - case WPS_CM_LABEL: { - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3); - break; - } - case WPS_CM_PUSH_BUTTON: { - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); - break; - } - case WPS_CM_KEYPAD: { - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); - break; - } - } - issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method); - } - } - RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); - return _TRUE; - -} - -u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe) -{ - - return _TRUE; -} - -u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list) -{ - u8 i = 0, j = 0; - u8 temp = 0; - u8 ch_no = 0; - ch_content += 3; - ch_cnt -= 3; - - while (ch_cnt > 0) { - ch_content += 1; - ch_cnt -= 1; - temp = *ch_content; - for (i = 0 ; i < temp ; i++, j++) - peer_ch_list[j] = *(ch_content + 1 + i); - ch_content += (temp + 1); - ch_cnt -= (temp + 1); - ch_no += temp ; - } - - return ch_no; -} - -u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) -{ - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - int i = 0, j = 0, temp = 0; - u8 ch_no = 0; - - for (i = 0; i < peer_ch_num; i++) { - for (j = temp; j < rfctl->max_chan_nums; j++) { - if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) { - ch_list_inclusioned[ch_no++] = *(peer_ch_list + i); - temp = j; - break; - } - } - } - - return ch_no; -} - -u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - _adapter *padapter = pwdinfo->padapter; - u8 result = P2P_STATUS_SUCCESS; - u32 p2p_ielen = 0, wps_ielen = 0; - u8 *ies; - u32 ies_len; - u8 *p2p_ie; - u8 *wpsie; - u16 wps_devicepassword_id = 0x0000; - uint wps_devicepassword_id_len = 0; -#ifdef CONFIG_WFD -#ifdef CONFIG_TDLS - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; -#endif /* CONFIG_TDLS */ -#endif /* CONFIG_WFD */ - wpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen); - if (wpsie) { - /* Commented by Kurt 20120113 */ - /* If some device wants to do p2p handshake without sending prov_disc_req */ - /* We have to get peer_req_cm from here. */ - if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) { - rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len); - wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id); - - if (wps_devicepassword_id == WPS_DPID_USER_SPEC) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); - else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); - else - _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); - } - } else { - RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - return result ; - } - - ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; - ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; - - p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); - - if (!p2p_ie) { - RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - } - - while (p2p_ie) { - u8 attr_content = 0x00; - u32 attr_contentlen = 0; - u8 ch_content[100] = { 0x00 }; - uint ch_cnt = 0; - u8 peer_ch_list[100] = { 0x00 }; - u8 peer_ch_num = 0; - u8 ch_list_inclusioned[100] = { 0x00 }; - u8 ch_num_inclusioned = 0; - u16 cap_attr; - u8 listen_ch_attr[5] = { 0x00 }; - - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); - - /* Check P2P Capability ATTR */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) { - cap_attr = le16_to_cpu(cap_attr); - -#if defined(CONFIG_WFD) && defined(CONFIG_TDLS) - if (!(cap_attr & P2P_GRPCAP_INTRABSS)) - ptdlsinfo->ap_prohibited = _TRUE; -#endif /* defined(CONFIG_WFD) && defined(CONFIG_TDLS) */ - } - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) { - RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01); - pwdinfo->peer_intent = attr_content; /* include both intent and tie breaker values. */ - - if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) { - /* Try to match the tie breaker value */ - if (pwdinfo->intent == P2P_MAX_INTENT) { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; - } else { - if (attr_content & 0x01) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - else - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - } - } else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - else - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* Store the group id information. */ - _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN); - _rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); - } - } - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5) - pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4]; - - RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch); - - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { - if (attr_contentlen != ETH_ALEN) - _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); - } - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) { - peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); - - if (ch_num_inclusioned == 0) { - RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_NO_COMMON_CH; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - break; - } - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel, - ch_list_inclusioned, ch_num_inclusioned)) { -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) - && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_NO_COMMON_CH; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - break; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; - attr_contentlen = 0; - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) - peer_operating_ch = operatingch_info[4]; - - if (rtw_p2p_is_channel_list_ok(peer_operating_ch, - ch_list_inclusioned, ch_num_inclusioned)) { - /** - * Change our operating channel as peer's for compatibility. - */ - pwdinfo->operating_channel = peer_operating_ch; - RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); - } else { - /* Take first channel of ch_list_inclusioned as operating channel */ - pwdinfo->operating_channel = ch_list_inclusioned[0]; - RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); - } - } - - } - } - } - - /* Get the next P2P IE */ - p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); - } - - if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) { - result = P2P_STATUS_FAIL_INFO_UNAVAILABLE; - rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY); - return result; - } - -#ifdef CONFIG_WFD - rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); -#endif - - return result ; -} - -u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - _adapter *padapter = pwdinfo->padapter; - u8 result = P2P_STATUS_SUCCESS; - u32 p2p_ielen, wps_ielen; - u8 *ies; - u32 ies_len; - u8 *p2p_ie; -#ifdef CONFIG_WFD -#ifdef CONFIG_TDLS - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; -#endif /* CONFIG_TDLS */ -#endif /* CONFIG_WFD */ - - ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; - ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; - - /* Be able to know which one is the P2P GO and which one is P2P client. */ - - if (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) { - - } else { - RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - } - - p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); - if (!p2p_ie) { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; - } else { - - u8 attr_content = 0x00; - u32 attr_contentlen = 0; - u8 operatingch_info[5] = { 0x00 }; - u8 groupid[38]; - u16 cap_attr; - u8 peer_ch_list[100] = { 0x00 }; - u8 peer_ch_num = 0; - u8 ch_list_inclusioned[100] = { 0x00 }; - u8 ch_num_inclusioned = 0; - - while (p2p_ie) { /* Found the P2P IE. */ - - /* Check P2P Capability ATTR */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) { - cap_attr = le16_to_cpu(cap_attr); -#ifdef CONFIG_TDLS - if (!(cap_attr & P2P_GRPCAP_INTRABSS)) - ptdlsinfo->ap_prohibited = _TRUE; -#endif /* CONFIG_TDLS */ - } - - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); - if (attr_contentlen == 1) { - RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); - if (attr_content == P2P_STATUS_SUCCESS) { - /* Do nothing. */ - } else { - if (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content) - rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY); - else - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - result = attr_content; - break; - } - } - - /* Try to get the peer's interface address */ - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { - if (attr_contentlen != ETH_ALEN) - _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); - } - - /* Try to get the peer's intent and tie breaker value. */ - attr_content = 0x00; - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) { - RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01); - pwdinfo->peer_intent = attr_content; /* include both intent and tie breaker values. */ - - if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) { - /* Try to match the tie breaker value */ - if (pwdinfo->intent == P2P_MAX_INTENT) { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - } else { - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - if (attr_content & 0x01) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - else - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - } - } else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) { - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - } else { - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - } - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* Store the group id information. */ - _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN); - _rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); - - } - } - - /* Try to get the operation channel information */ - - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { - RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]); - pwdinfo->peer_operating_ch = operatingch_info[4]; - } - - /* Try to get the channel list information */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) { - RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len); - - peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); - - if (ch_num_inclusioned == 0) { - RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_NO_COMMON_CH; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - break; - } - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel, - ch_list_inclusioned, ch_num_inclusioned)) { -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) - && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__); - result = P2P_STATUS_FAIL_NO_COMMON_CH; - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - break; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; - attr_contentlen = 0; - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) - peer_operating_ch = operatingch_info[4]; - - if (rtw_p2p_is_channel_list_ok(peer_operating_ch, - ch_list_inclusioned, ch_num_inclusioned)) { - /** - * Change our operating channel as peer's for compatibility. - */ - pwdinfo->operating_channel = peer_operating_ch; - RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); - } else { - /* Take first channel of ch_list_inclusioned as operating channel */ - pwdinfo->operating_channel = ch_list_inclusioned[0]; - RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); - } - } - - } - } - - } else - RTW_INFO("[%s] channel list attribute not found!\n", __FUNCTION__); - - /* Try to get the group id information if peer is GO */ - attr_contentlen = 0; - _rtw_memset(groupid, 0x00, 38); - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { - _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN); - _rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN); - } - - /* Get the next P2P IE */ - p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); - } - - } - -#ifdef CONFIG_WFD - rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); -#endif - - return result ; - -} - -u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ -#ifdef CONFIG_CONCURRENT_MODE - _adapter *padapter = pwdinfo->padapter; - struct roch_info *prochinfo = &padapter->rochinfo; -#endif - u8 *ies; - u32 ies_len; - u8 *p2p_ie; - u32 p2p_ielen = 0; - u8 result = P2P_STATUS_SUCCESS; - ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; - ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; - - p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); - while (p2p_ie) { /* Found the P2P IE. */ - u8 attr_content = 0x00, operatingch_info[5] = { 0x00 }; - u8 groupid[38] = { 0x00 }; - u32 attr_contentlen = 0; - - pwdinfo->negotiation_dialog_token = 1; - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); - if (attr_contentlen == 1) { - RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); - result = attr_content; - - if (attr_content == P2P_STATUS_SUCCESS) { - - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - - /* Commented by Albert 20100911 */ - /* Todo: Need to handle the case which both Intents are the same. */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - if ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1)) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - else if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1)) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - else { - /* Have to compare the Tie Breaker */ - if (pwdinfo->peer_intent & 0x01) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - else - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - } - -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) - && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { - /* Switch back to the AP channel soon. */ - _set_timer(&prochinfo->ap_roch_ch_switch_timer, 100); - } -#endif - } else { - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); - break; - } - } - - /* Try to get the group id information */ - attr_contentlen = 0; - _rtw_memset(groupid, 0x00, 38); - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { - RTW_INFO("[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN])); - _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN); - _rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN); - } + ies_len = len - WLAN_HDR_A3_LEN - ie_offset; - attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { - RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]); - pwdinfo->peer_operating_ch = operatingch_info[4]; - } + p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); - /* Get the next P2P IE */ - p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + if (!p2p_ie) { + RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__); + status_code = P2P_STATUS_FAIL_INVALID_PARAM; + } else + RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__); - } + while (p2p_ie) { + /* Check P2P Capability ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { + RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__); + cap_attr = le16_to_cpu(cap_attr); + psta->dev_cap = cap_attr & 0xff; + } - return result ; -} + /* Check Extended Listen Timing ATTR */ -u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) -{ - u8 *frame_body; - u8 dialogToken = 0; - u8 status = P2P_STATUS_SUCCESS; - frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + /* Check P2P Device Info ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) { + RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__); + pattr_content = pbuf = rtw_zmalloc(attr_contentlen); + if (pattr_content) { + u8 num_of_secdev_type; + u16 dev_name_len; - dialogToken = frame_body[6]; - /* todo: check NoA attribute */ + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen); - issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); + _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);/* P2P Device Address */ - return _TRUE; -} + pattr_content += ETH_ALEN; -void find_phase_handler(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct sitesurvey_parm parm; - _irqL irqL; - u8 _status = 0; + _rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */ + psta->config_methods = be16_to_cpu(psta->config_methods); + pattr_content += 2; - rtw_init_sitesurvey_parm(padapter, &parm); - _rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); - parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN; - parm.ssid_num = 1; + _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); - rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + pattr_content += 8; - _enter_critical_bh(&pmlmepriv->lock, &irqL); - _status = rtw_sitesurvey_cmd(padapter, &parm); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + num_of_secdev_type = *pattr_content; + pattr_content += 1; + if (num_of_secdev_type == 0) + psta->num_of_secdev_type = 0; + else { + u32 len; -} + psta->num_of_secdev_type = num_of_secdev_type; -void restore_p2p_state_handler(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; + len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + _rtw_memcpy(psta->secdev_types_list, pattr_content, len); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 union_bw = rtw_mi_get_union_bw(padapter); - u8 union_offset = rtw_mi_get_union_offset(padapter); - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) { - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_back_opch(padapter); - } - } -#endif + pattr_content += (num_of_secdev_type * 8); + } - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { -#ifdef CONFIG_CONCURRENT_MODE - rtw_concurrent_handler(padapter); -#else - /* In the P2P client mode, the driver should not switch back to its listen channel */ - /* because this P2P client should stay at the operating channel of P2P GO. */ - set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#endif - } -} + /* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */ + psta->dev_name_len = 0; + if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) { + dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2)); -void pre_tx_invitereq_handler(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - u8 val8 = 1; + psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len; - set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); - issue_probereq_p2p(padapter, NULL); - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + _rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len); + } -} + rtw_mfree(pbuf, attr_contentlen); -void pre_tx_provdisc_handler(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - u8 val8 = 1; + } - set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); - issue_probereq_p2p(padapter, NULL); - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + } -} + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); -void pre_tx_negoreq_handler(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - u8 val8 = 1; + } - set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); - issue_probereq_p2p(padapter , NULL); - /* WIN Phone only accept unicast probe request when nego back */ - issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr); - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + return status_code; } #ifdef CONFIG_IOCTL_CFG80211 - #if 0 static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) { u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) - return; -#endif /* CONFIG_MCC_MODE */ - ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3142,11 +1581,6 @@ static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) - return; -#endif /* CONFIG_MCC_MODE */ - ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3274,11 +1708,6 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram u32 ies_len, p2p_ielen; u8 union_ch = rtw_mi_get_union_chan(padapter); -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) - return; -#endif /* CONFIG_MCC_MODE */ - ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3302,9 +1731,7 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram for (i = 0; i < num_of_ch; i++) { if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) { - #ifdef RTW_SINGLE_WIPHY RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch); - #endif *(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/ } } @@ -3320,9 +1747,7 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen); if (pattr != NULL) { if (*(pattr + 4) && *(pattr + 4) != union_ch) { - #ifdef RTW_SINGLE_WIPHY RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch); - #endif *(pattr + 4) = union_ch; /*forcing to the same channel */ } } @@ -3469,7 +1894,7 @@ void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe) u8 build = 0; u8 del = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) del = 1; #ifdef CONFIG_IOCTL_CFG80211 @@ -3593,13 +2018,6 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info; if (tx) { - #ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */ - if (pwdev_priv->provdisc_req_issued == _FALSE) - rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); - #endif /* CONFIG_DRV_ISSUE_PROV_REQ */ - - /* pwdev_priv->provdisc_req_issued = _FALSE; */ - #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); @@ -3696,7 +2114,6 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) _RTW_INFO("\n"); if (!tx) { - pwdev_priv->provdisc_req_issued = _FALSE; #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE @@ -3866,34 +2283,9 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len); RTW_INFO("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken, cont ? *cont : -1); break; - case P2P_PROVISION_DISC_REQ: { - size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); - u8 *p2p_ie; - uint p2p_ielen = 0; - uint contentlen = 0; - + case P2P_PROVISION_DISC_REQ: RTW_INFO("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); - - /* if(tx) */ - { - pwdev_priv->provdisc_req_issued = _FALSE; - - p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); - if (p2p_ie) { - - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) { - pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */ - } else { - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("provdisc_req_issued is _TRUE\n"); - #endif /*CONFIG_DEBUG_CFG80211*/ - pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */ - } - - } - } - } - break; + break; case P2P_PROVISION_DISC_RESP: RTW_INFO("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; @@ -3939,61 +2331,7 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) } #endif /* CONFIG_IOCTL_CFG80211 */ -s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf) -{ - int ret = H2C_SUCCESS; - - switch (intCmdType) { - case P2P_FIND_PHASE_WK: - find_phase_handler(padapter); - break; - - case P2P_RESTORE_STATE_WK: - restore_p2p_state_handler(padapter); - break; - - case P2P_PRE_TX_PROVDISC_PROCESS_WK: -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - rtw_concurrent_handler(padapter); - else - pre_tx_provdisc_handler(padapter); -#else - pre_tx_provdisc_handler(padapter); -#endif - break; - - case P2P_PRE_TX_INVITEREQ_PROCESS_WK: -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - rtw_concurrent_handler(padapter); - else - pre_tx_invitereq_handler(padapter); -#else - pre_tx_invitereq_handler(padapter); -#endif - break; - - case P2P_PRE_TX_NEGOREQ_PROCESS_WK: -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - rtw_concurrent_handler(padapter); - else - pre_tx_negoreq_handler(padapter); -#else - pre_tx_negoreq_handler(padapter); -#endif - break; - - default: - rtw_warn_on(1); - break; - } - - return ret; -} - -int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +int process_p2p_cross_connect_ie(_adapter *padapter, u8 *IEs, u32 IELength) { int ret = _TRUE; u8 *ies; @@ -4028,7 +2366,7 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) } #ifdef CONFIG_P2P_PS -void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +void process_p2p_ps_ie(_adapter *padapter, u8 *IEs, u32 IELength) { u8 *ies; u32 ies_len; @@ -4042,7 +2380,8 @@ void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) u8 noa_offset, noa_num, noa_index; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE) || + rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) return; #ifdef CONFIG_CONCURRENT_MODE #ifndef CONFIG_FW_MULTI_PORT_SUPPORT @@ -4137,16 +2476,13 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); -#ifdef CONFIG_LPS if (pwdinfo->opp_ps == 1) { if (pwrpriv->smart_ps == 0) { pwrpriv->smart_ps = 2; - if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) - rtw_exec_lps(padapter, pwrpriv->pwr_mode); + if (pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); } } -#endif /* CONFIG_LPS */ - pwdinfo->noa_index = 0; pwdinfo->ctwindow = 0; pwdinfo->opp_ps = 0; @@ -4166,28 +2502,16 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) return; } if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - RTW_INFO("P2P PS enble under MCC\n"); - rtw_warn_on(1); - } - - } -#endif /* CONFIG_MCC_MODE */ pwdinfo->p2p_ps_state = p2p_ps_state; -#ifdef CONFIG_LPS if (pwdinfo->ctwindow > 0) { if (pwrpriv->smart_ps != 0) { pwrpriv->smart_ps = 0; RTW_INFO("%s(): Enter CTW, change SmartPS\n", __FUNCTION__); - if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) - rtw_exec_lps(padapter, pwrpriv->pwr_mode); + if (pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); } } -#endif /* CONFIG_LPS */ - rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); } break; @@ -4202,40 +2526,38 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) default: break; } - -#ifdef CONFIG_MCC_MODE - rtw_hal_mcc_process_noa(padapter); -#endif /* CONFIG_MCC_MODE */ } u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_obj *cmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + u8 res = _SUCCESS; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE) || + rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || #ifdef CONFIG_CONCURRENT_MODE #ifndef CONFIG_FW_MULTI_PORT_SUPPORT - || (padapter->hw_port != HW_PORT0) + (padapter->hw_port != HW_PORT0) || #endif #endif - ) + 0) return res; if (enqueue) { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } + cmd->padapter = padapter; pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } @@ -4245,120 +2567,21 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) pdrvextra_cmd_parm->size = 0; pdrvextra_cmd_parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); } else p2p_ps_wk_hdl(padapter, p2p_ps_state); - exit: - - return res; - } #endif /* CONFIG_P2P_PS */ -static void reset_ch_sitesurvey_timer_process(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; - - RTW_INFO("[%s] In\n", __FUNCTION__); - /* Reset the operation channel information */ - pwdinfo->rx_invitereq_info.operation_ch[0] = 0; -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->rx_invitereq_info.operation_ch[1] = 0; - pwdinfo->rx_invitereq_info.operation_ch[2] = 0; - pwdinfo->rx_invitereq_info.operation_ch[3] = 0; -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; -} - -static void reset_ch_sitesurvey_timer_process2(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; - - RTW_INFO("[%s] In\n", __FUNCTION__); - /* Reset the operation channel information */ - pwdinfo->p2p_info.operation_ch[0] = 0; -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->p2p_info.operation_ch[1] = 0; - pwdinfo->p2p_info.operation_ch[2] = 0; - pwdinfo->p2p_info.operation_ch[3] = 0; -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->p2p_info.scan_op_ch_only = 0; -} - -static void restore_p2p_state_timer_process(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; - - p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK); -} - -static void pre_tx_scan_timer_process(void *FunctionContext) -{ - _adapter *adapter = (_adapter *) FunctionContext; - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - _irqL irqL; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { - if (_TRUE == pwdinfo->tx_prov_disc_info.benable) { /* the provision discovery request frame is trigger to send or not */ - p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK); - /* issue_probereq_p2p(adapter, NULL); */ - /* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */ - } - } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { - if (_TRUE == pwdinfo->nego_req_info.benable) - p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK); - } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) { - if (_TRUE == pwdinfo->invitereq_info.benable) - p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK); - } else - RTW_INFO("[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); - - _exit_critical_bh(&pmlmepriv->lock, &irqL); -} - -static void find_phase_timer_process(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; - - adapter->wdinfo.find_phase_state_exchange_cnt++; - - p2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK); -} - void reset_global_wifidirect_info(_adapter *padapter) { struct wifidirect_info *pwdinfo; pwdinfo = &padapter->wdinfo; - pwdinfo->persistent_supported = 0; - pwdinfo->session_available = _TRUE; rtw_tdls_wfd_enable(padapter, 0); pwdinfo->wfd_tdls_weaksec = _TRUE; } @@ -4439,7 +2662,7 @@ u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf) u8 build_ie_by_self = 0; u32 len = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto exit; #ifdef CONFIG_IOCTL_CFG80211 @@ -4467,7 +2690,7 @@ u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf) u8 build_ie_by_self = 0; u32 len = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto exit; #ifdef CONFIG_IOCTL_CFG80211 @@ -4495,7 +2718,7 @@ u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf) u8 build_ie_by_self = 0; u32 len = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto exit; #ifdef CONFIG_IOCTL_CFG80211 @@ -4523,7 +2746,7 @@ u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf) u8 build_ie_by_self = 0; u32 len = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto exit; #ifdef CONFIG_IOCTL_CFG80211 @@ -4551,7 +2774,7 @@ u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf) u8 build_ie_by_self = 0; u32 len = 0; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) goto exit; #ifdef CONFIG_IOCTL_CFG80211 @@ -4574,30 +2797,6 @@ u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf) #endif /* CONFIG_WFD */ -void rtw_init_wifidirect_timers(_adapter *padapter) -{ - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - - rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter); - rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter); - rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter); - rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter); - rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter); -} - -void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr) -{ -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - - /*init device&interface address */ - if (dev_addr) - _rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN); - if (iface_addr) - _rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN); -#endif -} - void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) { struct wifidirect_info *pwdinfo; @@ -4608,57 +2807,12 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) pwdinfo->padapter = padapter; - /* 1, 6, 11 are the social channel defined in the WiFi Direct specification. */ - pwdinfo->social_chan[0] = 1; - pwdinfo->social_chan[1] = 6; - pwdinfo->social_chan[2] = 11; - pwdinfo->social_chan[3] = 0; /* channel 0 for scanning ending in site survey function. */ - - if (role != P2P_ROLE_DISABLE - && pwdinfo->driver_interface != DRIVER_CFG80211 - ) { - #ifdef CONFIG_CONCURRENT_MODE - u8 union_ch = 0; - - if (rtw_mi_check_status(padapter, MI_LINKED)) - union_ch = rtw_mi_get_union_chan(padapter); - - if (union_ch != 0 && - (union_ch == 1 || union_ch == 6 || union_ch == 11) - ) { - /* Use the AP's channel as the listen channel */ - /* This will avoid the channel switch between AP's channel and listen channel */ - pwdinfo->listen_channel = union_ch; - } else - #endif /* CONFIG_CONCURRENT_MODE */ - { - /* Use the channel 11 as the listen channel */ - pwdinfo->listen_channel = 11; - } - } - - if (role == P2P_ROLE_DEVICE) { + if (role == P2P_ROLE_DEVICE) rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); - else -#endif - rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); - - pwdinfo->intent = 1; - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN); - } else if (role == P2P_ROLE_CLIENT) { + else if (role == P2P_ROLE_CLIENT) rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - pwdinfo->intent = 1; - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - } else if (role == P2P_ROLE_GO) { + else if (role == P2P_ROLE_GO) rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - pwdinfo->intent = 15; - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); - } /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */ pwdinfo->support_rate[0] = 0x8c; /* 6(B) */ @@ -4672,87 +2826,11 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) _rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7); - _rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN); - pwdinfo->device_name_len = 0; - - _rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info)); - pwdinfo->invitereq_info.token = 3; /* Token used for P2P invitation request frame. */ - - _rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info)); - pwdinfo->inviteresp_info.token = 0; - - pwdinfo->profileindex = 0; - _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); - - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); - - pwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1); - /* RTW_INFO( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); */ - - _rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info)); - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE; - - _rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info)); - - pwdinfo->device_password_id_for_nego = WPS_DPID_PBC; - pwdinfo->negotiation_dialog_token = 1; - - _rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN); - pwdinfo->nego_ssidlen = 0; - - pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; #ifdef CONFIG_WFD - pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC; pwdinfo->wfd_info = pwfd_info; -#else - pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD; #endif /* CONFIG_WFD */ - pwdinfo->channel_list_attr_len = 0; - _rtw_memset(pwdinfo->channel_list_attr, 0x00, 100); - - _rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4); - _rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3); - _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); -#ifdef CONFIG_CONCURRENT_MODE -#ifdef CONFIG_IOCTL_CFG80211 - pwdinfo->ext_listen_interval = 1000; /* The interval to be available with legacy AP during p2p0-find/scan */ - pwdinfo->ext_listen_period = 3000; /* The time period to be available for P2P during nego */ -#else /* !CONFIG_IOCTL_CFG80211 */ - /* pwdinfo->ext_listen_interval = 3000; */ - /* pwdinfo->ext_listen_period = 400; */ - pwdinfo->ext_listen_interval = 1000; - pwdinfo->ext_listen_period = 1000; -#endif /* !CONFIG_IOCTL_CFG80211 */ -#endif - - /* Commented by Kurt 20130319 - * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */ -#ifdef CONFIG_IOCTL_CFG80211 - pwdinfo->driver_interface = DRIVER_CFG80211; -#else - pwdinfo->driver_interface = DRIVER_WEXT; -#endif /* CONFIG_IOCTL_CFG80211 */ pwdinfo->wfd_tdls_enable = 0; - _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); - _rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN); - - pwdinfo->rx_invitereq_info.operation_ch[0] = 0; - pwdinfo->rx_invitereq_info.operation_ch[1] = 0; /* Used to indicate the scan end in site survey function */ -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->rx_invitereq_info.operation_ch[2] = 0; - pwdinfo->rx_invitereq_info.operation_ch[3] = 0; - pwdinfo->rx_invitereq_info.operation_ch[4] = 0; -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; - pwdinfo->p2p_info.operation_ch[0] = 0; - pwdinfo->p2p_info.operation_ch[1] = 0; /* Used to indicate the scan end in site survey function */ -#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH - pwdinfo->p2p_info.operation_ch[2] = 0; - pwdinfo->p2p_info.operation_ch[3] = 0; - pwdinfo->p2p_info.operation_ch[4] = 0; -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ - pwdinfo->p2p_info.scan_op_ch_only = 0; } void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) @@ -4800,79 +2878,15 @@ const char *rtw_p2p_state_txt(enum P2P_STATE state) return "P2P_STATE_IDLE"; case P2P_STATE_LISTEN: return "P2P_STATE_LISTEN"; - case P2P_STATE_SCAN: - return "P2P_STATE_SCAN"; - case P2P_STATE_FIND_PHASE_LISTEN: - return "P2P_STATE_FIND_PHASE_LISTEN"; case P2P_STATE_FIND_PHASE_SEARCH: return "P2P_STATE_FIND_PHASE_SEARCH"; - case P2P_STATE_TX_PROVISION_DIS_REQ: - return "P2P_STATE_TX_PROVISION_DIS_REQ"; - case P2P_STATE_RX_PROVISION_DIS_RSP: - return "P2P_STATE_RX_PROVISION_DIS_RSP"; - case P2P_STATE_RX_PROVISION_DIS_REQ: - return "P2P_STATE_RX_PROVISION_DIS_REQ"; - case P2P_STATE_GONEGO_ING: - return "P2P_STATE_GONEGO_ING"; case P2P_STATE_GONEGO_OK: return "P2P_STATE_GONEGO_OK"; - case P2P_STATE_GONEGO_FAIL: - return "P2P_STATE_GONEGO_FAIL"; - case P2P_STATE_RECV_INVITE_REQ_MATCH: - return "P2P_STATE_RECV_INVITE_REQ_MATCH"; - case P2P_STATE_PROVISIONING_ING: - return "P2P_STATE_PROVISIONING_ING"; - case P2P_STATE_PROVISIONING_DONE: - return "P2P_STATE_PROVISIONING_DONE"; - case P2P_STATE_TX_INVITE_REQ: - return "P2P_STATE_TX_INVITE_REQ"; - case P2P_STATE_RX_INVITE_RESP_OK: - return "P2P_STATE_RX_INVITE_RESP_OK"; - case P2P_STATE_RECV_INVITE_REQ_DISMATCH: - return "P2P_STATE_RECV_INVITE_REQ_DISMATCH"; - case P2P_STATE_RECV_INVITE_REQ_GO: - return "P2P_STATE_RECV_INVITE_REQ_GO"; - case P2P_STATE_RECV_INVITE_REQ_JOIN: - return "P2P_STATE_RECV_INVITE_REQ_JOIN"; - case P2P_STATE_RX_INVITE_RESP_FAIL: - return "P2P_STATE_RX_INVITE_RESP_FAIL"; - case P2P_STATE_RX_INFOR_NOREADY: - return "P2P_STATE_RX_INFOR_NOREADY"; - case P2P_STATE_TX_INFOR_NOREADY: - return "P2P_STATE_TX_INFOR_NOREADY"; default: return "UNKNOWN"; } } -void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) -{ - if (!_rtw_p2p_chk_state(wdinfo, state)) { - enum P2P_STATE old_state = _rtw_p2p_state(wdinfo); - _rtw_p2p_set_state(wdinfo, state); - RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line - , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) - ); - } else { - RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line - , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) - ); - } -} -void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) -{ - if (_rtw_p2p_pre_state(wdinfo) != state) { - enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo); - _rtw_p2p_set_pre_state(wdinfo, state); - RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line - , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) - ); - } else { - RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line - , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) - ); - } -} #if 0 void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line) { @@ -4909,12 +2923,10 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) { int ret = _SUCCESS; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; -#endif if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) { -#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE) +#ifndef RTW_USE_CFG80211_REPORT_PROBE_REQ +#if defined(CONFIG_CONCURRENT_MODE) && !RTW_P2P_GROUP_INTERFACE /* Commented by Albert 2011/12/30 */ /* The driver just supports 1 P2P group operation. */ /* So, this function will do nothing if the buddy adapter had enabled the P2P function. */ @@ -4926,73 +2938,55 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) ret = _FAIL; return ret; } -#endif /* CONFIG_CONCURRENT_MODE */ - +#endif +#endif /* leave IPS/Autosuspend */ if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = _FAIL; goto exit; } - /* Added by Albert 2011/03/22 */ - /* In the P2P mode, the driver should not support the b mode. */ - /* So, the Tx packet shouldn't use the CCK rate */ - #ifdef CONFIG_IOCTL_CFG80211 - if (rtw_cfg80211_iface_has_p2p_group_cap(padapter)) - #endif - update_tx_basic_rate(padapter, WIRELESS_11AGN); + /* The P2P device does not need to remove the CCK rate of the + * adapter as it can act as an STA. + */ + if (role != P2P_ROLE_DEVICE) + update_tx_basic_rate(padapter, WLAN_MD_11AGN); /* Enable P2P function */ init_wifidirect_info(padapter, role); #ifdef CONFIG_IOCTL_CFG80211 - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - adapter_wdev_data(padapter)->p2p_enabled = _TRUE; + adapter_wdev_data(padapter)->p2p_enabled = _TRUE; #endif - rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE); +#if 0 + rtw_hal_set_phydm_var(padapter, HAL_PHYDM_P2P_STATE, NULL, _TRUE); #ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) - rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE); + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) + rtw_hal_set_phydm_var(padapter, HAL_PHYDM_WIFI_DISPLAY_STATE, NULL, _TRUE); +#endif #endif - } else if (role == P2P_ROLE_DISABLE) { #ifdef CONFIG_IOCTL_CFG80211 - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - adapter_wdev_data(padapter)->p2p_enabled = _FALSE; + adapter_wdev_data(padapter)->p2p_enabled = _FALSE; #endif pwdinfo->listen_channel = 0; /* Disable P2P function */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - _cancel_timer_ex(&pwdinfo->find_phase_timer); - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); - _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2); - reset_ch_sitesurvey_timer_process(padapter); - reset_ch_sitesurvey_timer_process2(padapter); -#ifdef CONFIG_CONCURRENT_MODE - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); -#endif - rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); - rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE); + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); - _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info)); - - /* Remove profiles in wifidirect_info structure. */ - _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); - pwdinfo->profileindex = 0; - } + else + RTW_ERR("%s, disable P2P when p2p role is P2P_ROLE_DISABLE!\n", __func__); - rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE); +#if 0 + rtw_hal_set_phydm_var(padapter, HAL_PHYDM_P2P_STATE, NULL, _FALSE); #ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) - rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE); + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) + rtw_hal_set_phydm_var(padapter, HAL_PHYDM_WIFI_DISPLAY_STATE, NULL, _FALSE); +#endif #endif - if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = _FAIL; goto exit; @@ -5000,18 +2994,10 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) /* Restore to initial setting. */ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); - - /* For WiDi purpose. */ -#ifdef CONFIG_IOCTL_CFG80211 - pwdinfo->driver_interface = DRIVER_CFG80211; -#else - pwdinfo->driver_interface = DRIVER_WEXT; -#endif /* CONFIG_IOCTL_CFG80211 */ - } exit: return ret; } -#endif /* CONFIG_P2P */ +#endif /* CONFIG_P2P */ \ No newline at end of file diff --git a/core/rtw_phl.c b/core/rtw_phl.c new file mode 100644 index 0000000..e2415e7 --- /dev/null +++ b/core/rtw_phl.c @@ -0,0 +1,2755 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_PHL_C_ +#include + + +/***************** export API to osdep/core*****************/ + +static const char *const _band_cap_str[] = { + /* BIT0 */"2G", + /* BIT1 */"5G", + /* BIT2 */"6G", +}; + +static const char *const _bw_cap_str[] = { + /* BIT0 */"20M", + /* BIT1 */"40M", + /* BIT2 */"80M", + /* BIT3 */"160M", + /* BIT4 */"80_80M", + /* BIT5 */"5M", + /* BIT6 */"10M", +}; + +static const char *const _proto_cap_str[] = { + /* BIT0 */"b", + /* BIT1 */"g", + /* BIT2 */"n", + /* BIT3 */"ac", +}; + +static const char *const _wl_func_str[] = { + /* BIT0 */"P2P", + /* BIT1 */"MIRACAST", + /* BIT2 */"TDLS", + /* BIT3 */"FTM", +}; + +static const char *const hw_cap_str = "[HW-CAP]"; +void rtw_hw_dump_hal_spec(void *sel, struct dvobj_priv *dvobj) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj); + int i; + + RTW_PRINT_SEL(sel, "%s ic_name:%s\n", hw_cap_str, hal_spec->ic_name); + RTW_PRINT_SEL(sel, "%s macid_num:%u\n", hw_cap_str, hal_spec->macid_num); + RTW_PRINT_SEL(sel, "%s sec_cap:0x%02x\n", hw_cap_str, hal_spec->sec_cap); + RTW_PRINT_SEL(sel, "%s sec_cam_ent_num:%u\n", hw_cap_str, hal_spec->sec_cam_ent_num); + + RTW_PRINT_SEL(sel, "%s rfpath_num_2g:%u\n", hw_cap_str, hal_spec->rfpath_num_2g); + RTW_PRINT_SEL(sel, "%s rfpath_num_5g:%u\n", hw_cap_str, hal_spec->rfpath_num_5g); + RTW_PRINT_SEL(sel, "%s rf_reg_path_num:%u\n", hw_cap_str, hal_spec->rf_reg_path_num); + RTW_PRINT_SEL(sel, "%s max_tx_cnt:%u\n", hw_cap_str, hal_spec->max_tx_cnt); + + RTW_PRINT_SEL(sel, "%s tx_nss_num:%u\n", hw_cap_str, hal_spec->tx_nss_num); + RTW_PRINT_SEL(sel, "%s rx_nss_num:%u\n", hw_cap_str, hal_spec->rx_nss_num); + + RTW_PRINT_SEL(sel, "%s band_cap:", hw_cap_str); + for (i = 0; i < BAND_CAP_BIT_NUM; i++) { + if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i]) + _RTW_PRINT_SEL(sel, "%s ", _band_cap_str[i]); + } + _RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "%s bw_cap:", hw_cap_str); + for (i = 0; i < BW_CAP_BIT_NUM; i++) { + if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i]) + _RTW_PRINT_SEL(sel, "%s ", _bw_cap_str[i]); + } + _RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "%s proto_cap:", hw_cap_str); + for (i = 0; i < PROTO_CAP_BIT_NUM; i++) { + if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i]) + _RTW_PRINT_SEL(sel, "%s ", _proto_cap_str[i]); + } + _RTW_PRINT_SEL(sel, "\n"); + +#if 0 /*GEORGIA_TODO_FIXIT*/ + RTW_PRINT_SEL(sel, "%s txgi_max:%u\n", hw_cap_str, hal_spec->txgi_max); + RTW_PRINT_SEL(sel, "%s txgi_pdbm:%u\n", hw_cap_str, hal_spec->txgi_pdbm); +#endif + RTW_PRINT_SEL(sel, "%s wl_func:", hw_cap_str); + for (i = 0; i < WL_FUNC_BIT_NUM; i++) { + if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i]) + _RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]); + } + _RTW_PRINT_SEL(sel, "\n"); + +#if 0 /*GEORGIA_TODO_FIXIT*/ + + RTW_PRINT_SEL(sel, "%s pg_txpwr_saddr:0x%X\n", hw_cap_str, hal_spec->pg_txpwr_saddr); + RTW_PRINT_SEL(sel, "%s pg_txgi_diff_factor:%u\n", hw_cap_str, hal_spec->pg_txgi_diff_factor); +#endif +} + +void rtw_dump_phl_sta_info(void *sel, struct sta_info *sta) +{ + struct rtw_phl_stainfo_t *phl_sta = sta->phl_sta; + + RTW_PRINT_SEL(sel, "[PHL STA]- role-idx: %d\n", phl_sta->wrole->id); + + RTW_PRINT_SEL(sel, "[PHL STA]- mac_addr:"MAC_FMT"\n", MAC_ARG(phl_sta->mac_addr)); + RTW_PRINT_SEL(sel, "[PHL STA]- aid: %d\n", phl_sta->aid); + RTW_PRINT_SEL(sel, "[PHL STA]- macid: %d\n", phl_sta->macid); + + RTW_PRINT_SEL(sel, "[PHL STA]- wifi_band: %d\n", phl_sta->chandef.band); + RTW_PRINT_SEL(sel, "[PHL STA]- bw: %d\n", phl_sta->chandef.bw); + RTW_PRINT_SEL(sel, "[PHL STA]- chan: %d\n", phl_sta->chandef.chan); + RTW_PRINT_SEL(sel, "[PHL STA]- offset: %d\n", phl_sta->chandef.offset); +} + +inline bool rtw_hw_chk_band_cap(struct dvobj_priv *dvobj, u8 cap) +{ + return GET_HAL_SPEC(dvobj)->band_cap & cap; +} + +inline bool rtw_hw_chk_bw_cap(struct dvobj_priv *dvobj, u8 cap) +{ + return GET_HAL_SPEC(dvobj)->bw_cap & cap; +} + +inline bool rtw_hw_chk_proto_cap(struct dvobj_priv *dvobj, u8 cap) +{ + return GET_HAL_SPEC(dvobj)->proto_cap & cap; +} + +inline bool rtw_hw_chk_wl_func(struct dvobj_priv *dvobj, u8 func) +{ + return GET_HAL_SPEC(dvobj)->wl_func & func; +} + +inline bool rtw_hw_is_band_support(struct dvobj_priv *dvobj, u8 band) +{ + return GET_HAL_SPEC(dvobj)->band_cap & band_to_band_cap(band); +} + +inline bool rtw_hw_is_bw_support(struct dvobj_priv *dvobj, u8 bw) +{ + return GET_HAL_SPEC(dvobj)->bw_cap & ch_width_to_bw_cap(bw); +} + +inline bool rtw_hw_is_wireless_mode_support(struct dvobj_priv *dvobj, u8 mode) +{ + u8 proto_cap = GET_HAL_SPEC(dvobj)->proto_cap; + + if (mode == WLAN_MD_11B) + if ((proto_cap & PROTO_CAP_11B) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_2G)) + return 1; + + if (mode == WLAN_MD_11G) + if ((proto_cap & PROTO_CAP_11G) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_2G)) + return 1; + + if (mode == WLAN_MD_11A) + if ((proto_cap & PROTO_CAP_11G) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_5G)) + return 1; + + #ifdef CONFIG_80211N_HT + if (mode == WLAN_MD_11N) + if (proto_cap & PROTO_CAP_11N) + return 1; + #endif + + #ifdef CONFIG_80211AC_VHT + if (mode == WLAN_MD_11AC) + if ((proto_cap & PROTO_CAP_11AC) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_5G)) + return 1; + #endif + + #ifdef CONFIG_80211AX_HE + if (mode == WLAN_MD_11AX) + if (proto_cap & PROTO_CAP_11AX) + return 1; + #endif + return 0; +} + + +inline u8 rtw_hw_get_wireless_mode(struct dvobj_priv *dvobj) +{ + u8 proto_cap = GET_HAL_SPEC(dvobj)->proto_cap; + u8 band_cap = GET_HAL_SPEC(dvobj)->band_cap; + u8 wireless_mode = 0; + + if(proto_cap & PROTO_CAP_11B) + wireless_mode |= WLAN_MD_11B; + + if(proto_cap & PROTO_CAP_11G) + wireless_mode |= WLAN_MD_11G; + + if(band_cap & BAND_CAP_5G) + wireless_mode |= WLAN_MD_11A; + + #ifdef CONFIG_80211N_HT + if(proto_cap & PROTO_CAP_11N) + wireless_mode |= WLAN_MD_11N; + #endif + + #ifdef CONFIG_80211AC_VHT + if(proto_cap & PROTO_CAP_11AC) + wireless_mode |= WLAN_MD_11AC; + #endif + + #ifdef CONFIG_80211AX_HE + if(proto_cap & PROTO_CAP_11AX) { + wireless_mode |= WLAN_MD_11AX; + } + #endif + + return wireless_mode; +} + +inline u8 rtw_hw_get_band_type(struct dvobj_priv *dvobj) +{ + u8 band_cap = GET_HAL_SPEC(dvobj)->band_cap; + u8 band_type = 0; + + if(band_cap & BAND_CAP_2G) + band_type |= BAND_CAP_2G; + +#if CONFIG_IEEE80211_BAND_5GHZ + if(band_cap & BAND_CAP_5G) + band_type |= BAND_CAP_5G; +#endif + +#if CONFIG_IEEE80211_BAND_6GHZ + if(band_cap & BAND_CAP_6G) + band_type |= BAND_CAP_6G; +#endif + + return band_type; +} + +inline bool rtw_hw_is_mimo_support(struct dvobj_priv *dvobj) +{ + if ((GET_HAL_TX_NSS(dvobj) == 1) && + (GET_HAL_RX_NSS(dvobj) == 1)) + return 0; + return 1; +} + +/* +* rtw_hw_largest_bw - starting from in_bw, get largest bw supported by HAL +* @adapter: +* @in_bw: starting bw, value of enum channel_width +* +* Returns: value of enum channel_width +*/ +u8 rtw_hw_largest_bw(struct dvobj_priv *dvobj, u8 in_bw) +{ + for (; in_bw > CHANNEL_WIDTH_20; in_bw--) { + if (rtw_hw_is_bw_support(dvobj, in_bw)) + break; + } + + if (!rtw_hw_is_bw_support(dvobj, in_bw)) + rtw_warn_on(1); + + return in_bw; +} + +u8 rtw_hw_get_mac_addr(struct dvobj_priv *dvobj, u8 *hw_mac_addr) +{ + if (rtw_phl_get_mac_addr_efuse(dvobj->phl, hw_mac_addr) != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s failed\n", __func__); + return _FAIL; + } + return _SUCCESS; +} + + +/***************** register hw *****************/ +#if 0 /*GEORGIA_TODO_ADDIT*/ + +#define hal_trx_error_msg(ops_fun) \ + RTW_PRINT("### %s - Error : Please hook hal_trx_ops.%s ###\n", __FUNCTION__, ops_fun) +static u8 rtw_hw_trx_ops_check(struct hal_com_t *hal_com) +{ + u8 rst = _SUCCESS; + + if (!hal_com->trx_ops.intf_hal_configure) { + hal_trx_error_msg("intf_hal_configure"); + rst = _FAIL; + } + + if (!hal_com->trx_ops.get_txdesc_len) { + hal_trx_error_msg("get_txdesc_len"); + rst = _FAIL; + } + if (!hal_com->trx_ops.fill_txdesc_h2c) { + hal_trx_error_msg("fill_txdesc_h2c"); + rst = _FAIL; + } + if (!hal_com->trx_ops.fill_txdesc_fwdl) { + hal_trx_error_msg("fill_txdesc_fwdl"); + rst = _FAIL; + } + if (!hal_com->trx_ops.fill_txdesc_pkt) { + hal_trx_error_msg("fill_txdesc_pkt"); + rst = _FAIL; + } + +#if defined(CONFIG_USB_HCI) + if (!hal_com->trx_ops.get_bulkout_id) { + hal_trx_error_msg("get_bulkout_id"); + rst = _FAIL; + } +#endif + +#if 0 /*GEORGIA_TODO_ADDIT*/ + if (!hal_com->trx_ops.init_xmit) { + hal_trx_error_msg("init_xmit"); + rst = _FAIL; + } + + if (!hal_com->trx_ops.init_recv) { + hal_trx_error_msg("init_recv"); + rst = _FAIL; + } + + #if defined(CONFIG_PCI_HCI) + if (!hal_com->trx_ops.check_enough_txdesc) { + hal_trx_error_msg("check_enough_txdesc"); + rst = _FAIL; + } + if (!hal_com->trx_ops.trxbd_init) { + hal_trx_error_msg("trxbd_init"); + rst = _FAIL; + } + if (!hal_com->trx_ops.trxbd_deinit) { + hal_trx_error_msg("trxbd_deinit"); + rst = _FAIL; + } + if (!hal_com->trx_ops.trxbd_reset) { + hal_trx_error_msg("trxbd_reset"); + rst = _FAIL; + } + if (!hal_com->trx_ops.interrupt_handler) { + hal_trx_error_msg("interrupt_handler"); + rst = _FAIL; + } + #endif + + #if defined(CONFIG_USB_HCI) + #ifdef CONFIG_SUPPORT_USB_INT + if (!hal_com->trx_ops.interrupt_handler) { + hal_trx_error_msg("interrupt_handler"); + rst = _FAIL; + } + #endif + #endif + + if (!hal_com->trx_ops.enable_interrupt) { + hal_trx_error_msg("enable_interrupt"); + rst = _FAIL; + } + if (!hal_com->trx_ops.disable_interrupt) { + hal_trx_error_msg("disable_interrupt"); + rst = _FAIL; + } + + #if defined(CONFIG_SDIO_HCI) + if (!hal_com->trx_ops.interrupt_handler) { + hal_trx_error_msg("interrupt_handler"); + rst = _FAIL; + } + if (!hal_com->trx_ops.get_tx_addr) { + hal_trx_error_msg("get_tx_addr"); + rst = _FAIL; + } + #endif +#endif + return rst; +} +#endif + +u8 rtw_core_deregister_phl_msg(struct dvobj_priv *dvobj) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + + psts = rtw_phl_msg_hub_deregister_recver(dvobj->phl, MSG_RECV_CORE); + if(psts == RTW_PHL_STATUS_FAILURE) { + RTW_ERR("%s failed\n", __func__); + return _FAIL; + } + return _SUCCESS; +} + +void rtw_hw_deinit(struct dvobj_priv *dvobj) +{ + if (dvobj->phl) { + rtw_phl_trx_free(dvobj->phl); + rtw_core_deregister_phl_msg(dvobj); + rtw_phl_watchdog_deinit(dvobj->phl); + rtw_clear_phl_regulation_ctx(dvobj); + rtw_phl_deinit(dvobj->phl); + } + + #ifdef DBG_PHL_MEM_ALLOC + RTW_INFO("[PHL-MEM] %s PHL memory :%d\n", __func__, + ATOMIC_READ(&(dvobj->phl_mem))); + #endif +} + +#if 0 +void dump_ic_spec(struct dvobj_priv *dvobj) +{ + struct hal_com_t *hal_com = dvobj->hal_com; + struct hal_spec_t *hal_spec = &hal_com->hal_spec; + + RTW_INFO("dvobj:%p,hal:%p(size:%d), hal_com:%p, hal_spec:%p\n", + dvobj, dvobj->hal_info, dvobj->hal_info_sz, hal_com, hal_spec); + RTW_INFO("dvobj:%p, hal_com:%p, hal_spec:%p\n", dvobj, GET_PHL_COM(dvobj), GET_HAL_SPEC(dvobj)); + + RTW_INFO("[IC-SPEC]- band_cap: %x\n", GET_HAL_SPEC(dvobj)->band_cap); +} +#endif + +#if 0 /*GEORGIA_TODO_FIXIT*/ +void rtw_hw_intf_cfg(struct dvobj_priv *dvobj, struct hal_com_t *hal_com) +{ + struct hci_info_st hci_info; + + #ifdef CONFIG_PCI_HCI + if (dvobj->interface_type == RTW_HCI_PCIE) { + PPCI_DATA pci = dvobj_to_pci(dvobj); + //hci_info. + } + #endif + + #ifdef CONFIG_USB_HCI + if (dvobj->interface_type == RTW_HCI_USB) { + PUSB_DATA usb = dvobj_to_usb(dvobj); + #if 0 + u8 usb_speed; /* 1.1, 2.0 or 3.0 */ + u16 usb_bulkout_size; + u8 nr_endpoint; /*MAX_ENDPOINT_NUM*/ + + /* Bulk In , Out Pipe information */ + int RtInPipe[MAX_BULKIN_NUM]; + u8 RtNumInPipes; + int RtOutPipe[MAX_BULKOUT_NUM]; + u8 RtNumOutPipes; + #endif + //hci_info + } + #endif + + #ifdef CONFIG_SDIO_HCI + if (dvobj->interface_type == RTW_HCI_SDIO) { + PSDIO_DATA sdio = dvobj_to_sdio(dvobj); + + hci_info.clock = sdio->clock; + hci_info.timing = sdio->timing; + hci_info.sd3_bus_mode = sdio->sd3_bus_mode; + hci_info.block_sz = sdio->block_transfer_len; + hci_info.align_sz = sdio->block_transfer_len; + } + #endif + + rtw_hal_intf_config(hal_com, &hci_info); +} +#endif + +static void _hw_ic_info_cfg(struct dvobj_priv *dvobj, struct rtw_ic_info *ic_info) +{ + _rtw_memset(ic_info, 0,sizeof(struct rtw_ic_info)); + + ic_info->ic_id = dvobj->ic_id; + ic_info->hci_type = dvobj->interface_type; + + #ifdef CONFIG_PCI_HCI + if (dvobj->interface_type == RTW_HCI_PCIE) { + PPCI_DATA pci = dvobj_to_pci(dvobj); + + } + #endif + + #ifdef CONFIG_USB_HCI + if (dvobj->interface_type == RTW_HCI_USB) { + PUSB_DATA usb = dvobj_to_usb(dvobj); + + ic_info->usb_info.usb_speed = usb->usb_speed; + ic_info->usb_info.usb_bulkout_size = usb->usb_bulkout_size; + ic_info->usb_info.inep_num = usb->RtNumInPipes; + ic_info->usb_info.outep_num = usb->RtNumOutPipes; + } + #endif + + #ifdef CONFIG_SDIO_HCI + if (dvobj->interface_type == RTW_HCI_SDIO) { + PSDIO_DATA sdio = dvobj_to_sdio(dvobj); + + ic_info->sdio_info.clock = sdio->clock; + ic_info->sdio_info.timing = sdio->timing; + ic_info->sdio_info.sd3_bus_mode = sdio->sd3_bus_mode; + ic_info->sdio_info.io_align_sz = 4; + ic_info->sdio_info.block_sz = sdio->block_transfer_len; + ic_info->sdio_info.tx_align_sz = sdio->block_transfer_len; + ic_info->sdio_info.tx_512_by_byte_mode = + (sdio->max_byte_size >= 512) ? true : false; + } + #endif +} +static void core_hdl_phl_evt(struct dvobj_priv *dvobj, u16 evt_id) +{ + _adapter *iface; + u8 i = 0; + + if(evt_id == MSG_EVT_BCN_RESEND) { + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if(!rtw_is_adapter_up(iface)) + continue; + + if(MLME_IS_MESH(iface) + || MLME_IS_AP(iface) + || MLME_IS_ADHOC_MASTER(iface)) { + if (send_beacon(iface) == _FAIL) + RTW_ERR(ADPT_FMT" issue_beacon, fail!\n", + ADPT_ARG(iface)); + } + } + } + else if (evt_id == MSG_EVT_SER_L2) { + RTW_INFO("RECV PHL MSG_EVT_SER_L2\n"); + } +#ifdef CONFIG_XMIT_ACK + else if (evt_id == MSG_EVT_CCX_REPORT_TX_OK) { + iface = dvobj_get_primary_adapter(dvobj); + rtw_ack_tx_done(&iface->xmitpriv, RTW_SCTX_DONE_SUCCESS); + } + else if (evt_id == MSG_EVT_CCX_REPORT_TX_FAIL) { + iface = dvobj_get_primary_adapter(dvobj); + rtw_ack_tx_done(&iface->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); + } +#endif + else { + RTW_INFO("%s evt_id :%d\n", __func__, evt_id); + } +} + +void core_handler_phl_msg(void *drv_priv, struct phl_msg *msg) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)drv_priv; + u8 mdl_id = MSG_MDL_ID_FIELD(msg->msg_id); + u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + switch(mdl_id) { + case PHL_MDL_RX: + case PHL_MDL_SER: + case PHL_MDL_WOW: + core_hdl_phl_evt(dvobj, evt_id); + break; + default: + RTW_ERR("%s mdl_id :%d not support\n", __func__, mdl_id); + break; + } +} + +u8 rtw_core_register_phl_msg(struct dvobj_priv *dvobj) +{ + struct phl_msg_receiver ctx = {0}; + u8 imr[] = {PHL_MDL_RX, PHL_MDL_SER, PHL_MDL_WOW}; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + + ctx.incoming_evt_notify = core_handler_phl_msg; + ctx.priv = (void*)dvobj; + + psts = rtw_phl_msg_hub_register_recver(dvobj->phl, &ctx, MSG_RECV_CORE); + if(psts == RTW_PHL_STATUS_FAILURE) { + RTW_ERR("phl_msg_hub_register failed\n"); + return _FAIL; + } + + psts = rtw_phl_msg_hub_update_recver_mask(dvobj->phl, + MSG_RECV_CORE, imr, sizeof(imr), false); + if(psts == RTW_PHL_STATUS_FAILURE) { + RTW_ERR("phl_msg_hub_update_recver_mask failed\n"); + return _FAIL; + } + return _SUCCESS; +} + +/*RTW_WKARD_CORE_RSSI_V1*/ +s8 rtw_phl_rssi_to_dbm(u8 rssi) +{ + return rssi - PHL_MAX_RSSI; +} + + +#ifdef CONFIG_MCC_MODE +u8 rtw_hw_mcc_chk_inprogress(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + void *phl; + u8 ret = _FALSE; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + goto exit; + + ret = rtw_phl_mr_query_mcc_inprogress(phl, a->phl_role, RTW_PHL_MCC_CHK_INPROGRESS); + +exit: + return ret; +} + +#ifdef CONFIG_P2P_PS +static int _mcc_update_noa(void *priv, struct rtw_phl_mcc_noa *param) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *) priv; + struct rtw_wifi_role_t *wrole = NULL; + struct _ADAPTER *a = NULL; + struct wifidirect_info *wdinfo; + u8 id = 0; + u8 ret = _SUCCESS; +#ifdef CONFIG_PHL_P2PPS + struct rtw_phl_noa_desc desc= {0}; +#endif + wrole = param->wrole; + if (wrole == NULL) { + RTW_ERR("%s wrole is NULL\n", __func__); + ret = _FAIL; + goto exit; + } + + id = wrole->id; + if (id >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s error id (%d)\n", __func__, id); + ret = _FAIL; + goto exit; + } + + a = dvobj->padapters[id]; + if (a == NULL) { + RTW_ERR("%s adapter(%d) is NULL\n", __func__, id); + ret = _FAIL; + goto exit; + } + + /* by pass non-GO case */ + if (!MLME_IS_GO(a)) + goto exit; + + wdinfo = &a->wdinfo; + RTW_INFO(FUNC_ADPT_FMT":(%d)\n", FUNC_ADPT_ARG(a), id); + RTW_INFO("start_t_h=0x%02x,start_t_l=0x%02x\n", param->start_t_h, param->start_t_l); + RTW_INFO("dur=0x%d,cnt=0x%d,interval=0x%d\n", param->dur, param->cnt, param->interval); + +#ifdef CONFIG_PHL_P2PPS + /* enable TSF32 toggle */ + desc.tag = P2PPS_TRIG_MCC; + desc.enable = true; + desc.duration = param->dur * NET80211_TU_TO_US; + desc.interval = param->interval * NET80211_TU_TO_US; + desc.start_t_h = param->start_t_h; + desc.start_t_l = param->start_t_l; + desc.count = param->cnt; + desc.w_role = param->wrole; + if (rtw_phl_p2pps_noa_update(dvobj->phl, &desc) != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s rtw_phl_p2pps_noa_update fail\n", __func__); + ret = _FAIL; + goto exit; + } +#endif + + /* update NoA IE */ + wdinfo->noa_index = wdinfo->noa_index + 1; + wdinfo->noa_num = 1; + wdinfo->noa_count[0] = param->cnt; + wdinfo->noa_duration[0] =param->dur * NET80211_TU_TO_US; + wdinfo->noa_interval[0] = param->interval * NET80211_TU_TO_US; + wdinfo->noa_start_time[0] = param->start_t_l; + + rtw_update_beacon(a, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, RTW_CMDF_DIRECTLY); +exit: + return ret; +} +#endif + +/* default setting */ +static int _mcc_get_setting(void *priv, struct rtw_phl_mcc_setting_info *param) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *) priv; + struct rtw_wifi_role_t *wrole = NULL; + struct _ADAPTER *a = NULL; + struct wifidirect_info *wdinfo; + u8 id = 0; + u8 ret = _SUCCESS; + + wrole = param->wrole; + if (wrole == NULL) { + RTW_ERR("%s wrole is NULL\n", __func__); + ret = _FAIL; + goto exit; + } + + id = wrole->id; + if (id >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s error id (%d)\n", __func__, id); + ret = _FAIL; + goto exit; + } + + a = dvobj->padapters[id]; + if (a == NULL) { + RTW_ERR("%s adapter(%d) is NULL\n", __func__, id); + ret = _FAIL; + goto exit; + } + + if (MLME_IS_GO(a) || MLME_IS_GC(a)) + param->dur = 50; + else + param->dur = 50; + + if (MLME_IS_STA(a) || MLME_IS_GC(a)) + param->tx_null_early = 5; + else + param->tx_null_early = NONSPECIFIC_SETTING; + + RTW_INFO("%s: adapter(%d) dur=%d, tx_null_early=%d\n", __func__, id, param->dur, param->tx_null_early); + +exit: + return ret; +} + +struct rtw_phl_mcc_ops rtw_mcc_ops = { + .priv = NULL, + .mcc_update_noa = _mcc_update_noa, + .mcc_get_setting = _mcc_get_setting, +}; +#endif + +struct rtw_phl_mr_ops rtw_mr_ops = { +#ifdef CONFIG_MCC_MODE + .mcc_ops = &rtw_mcc_ops, +#endif +}; + +void rtw_core_register_mr_config(struct dvobj_priv *dvobj) +{ +#ifdef CONFIG_MCC_MODE + rtw_mr_ops.mcc_ops->priv = (void *)dvobj; +#endif + rtw_phl_mr_ops_init(dvobj->phl, &rtw_mr_ops); +} + +#if CONFIG_DFS +#ifdef CONFIG_ECSA_PHL +static void rtw_core_set_ecsa_ops(struct dvobj_priv *d) +{ + struct rtw_phl_ecsa_ops ops = {0}; + + ops.priv = (void *)d; + ops.update_beacon = rtw_ecsa_update_beacon; + ops.update_chan_info = rtw_ecsa_mr_update_chan_info_by_role; + ops.check_ecsa_allow = rtw_ap_check_ecsa_allow; + ops.ecsa_complete = rtw_ecsa_complete; + ops.check_tx_resume_allow = rtw_ecsa_check_tx_resume_allow; + rtw_phl_ecsa_init_ops(GET_PHL_INFO(d), &ops); +} +#endif +#endif + +u8 rtw_hw_init(struct dvobj_priv *dvobj) +{ + u8 rst = _FAIL; + enum rtw_phl_status phl_status; + struct rtw_ic_info ic_info; + struct rtw_phl_evt_ops *evt_ops; + +#ifdef DBG_PHL_MEM_ALLOC + ATOMIC_SET(&dvobj->phl_mem, 0); +#endif + + _hw_ic_info_cfg(dvobj, &ic_info); + phl_status = rtw_phl_init(dvobj, &(dvobj->phl), &ic_info); + + if ((phl_status != RTW_PHL_STATUS_SUCCESS) || (dvobj->phl == NULL)) { + RTW_ERR("%s - rtw_phl_init failed status(%d), dvobj->phl(%p)\n", + __func__, phl_status, dvobj->phl); + goto _free_hal; + } + + dvobj->phl_com = rtw_phl_get_com(dvobj->phl); + + /*init sw cap from registary*/ + rtw_core_update_default_setting(dvobj); + + /* sw & hw cap*/ + rtw_phl_cap_pre_config(dvobj->phl); + + #ifdef CONFIG_RX_PSTS_PER_PKT + rtw_phl_init_ppdu_sts_para(dvobj->phl_com, + _TRUE, _FALSE, + RTW_PHL_PSTS_FLTR_MGNT | RTW_PHL_PSTS_FLTR_DATA /*| RTW_PHL_PSTS_FLTR_CTRL*/ + ); + #endif + /*init datapath section*/ + rtw_phl_trx_alloc(dvobj->phl); + evt_ops = &(dvobj->phl_com->evt_ops); + evt_ops->rx_process = rtw_core_rx_process; + evt_ops->tx_recycle = rtw_core_tx_recycle; +#ifdef CONFIG_RTW_IPS + evt_ops->set_rf_state = rtw_core_set_ips_state; +#endif +#ifdef CONFIG_GTK_OL + evt_ops->wow_handle_sec_info_update = rtw_update_gtk_ofld_info; +#endif + + rtw_core_register_phl_msg(dvobj); + + /* load wifi feature or capability from efuse*/ + rtw_phl_preload(dvobj->phl); + + rtw_phl_final_cap_decision(dvobj->phl); + + /* after final cap decision */ + rtw_core_register_mr_config(dvobj); + + #if CONFIG_DFS + #ifdef CONFIG_ECSA_PHL + rtw_core_set_ecsa_ops(dvobj); + #endif + #endif + + rtw_hw_dump_hal_spec(RTW_DBGDUMP, dvobj); + + #ifdef CONFIG_CMD_GENERAL + rtw_phl_watchdog_init(dvobj->phl, + 0, + rtw_core_watchdog_sw_hdlr, + rtw_core_watchdog_hw_hdlr); + #else + rtw_phl_job_reg_wdog(dvobj->phl, + rtw_dynamic_check_handlder, + dvobj, NULL, 0, "rtw_dm", PWR_BASIC_IO); + #endif + + rtw_set_phl_regulation_ctx(dvobj); + + rst = _SUCCESS; + return rst; + +_free_hal : + rtw_hw_deinit(dvobj); + return rst; +} + +u8 rtw_hw_start(struct dvobj_priv *dvobj) +{ + if (dev_is_hw_start(dvobj)) + return _FAIL; + + if (rtw_phl_start(GET_PHL_INFO(dvobj)) != RTW_PHL_STATUS_SUCCESS) + return _FAIL; + + #ifdef CONFIG_PCI_HCI + //intr init flag + dvobj_to_pci(dvobj)->irq_enabled = 1; + #endif + #ifdef CONFIG_CMD_GENERAL + rtw_phl_watchdog_start(dvobj->phl); + #endif + + dev_set_hw_start(dvobj); + + return _SUCCESS; +} +void rtw_hw_stop(struct dvobj_priv *dvobj) +{ + if (!dev_is_hw_start(dvobj)) + return; + + #ifdef CONFIG_CMD_GENERAL + rtw_phl_watchdog_stop(dvobj->phl); + #endif + rtw_phl_stop(GET_PHL_INFO(dvobj)); + + #ifdef CONFIG_PCI_HCI + //intr init flag + dvobj_to_pci(dvobj)->irq_enabled = 0; + #endif + + dev_clr_hw_start(dvobj); +} + +bool rtw_hw_get_init_completed(struct dvobj_priv *dvobj) +{ + return rtw_phl_is_init_completed(GET_PHL_INFO(dvobj)); +} + +bool rtw_hw_is_init_completed(struct dvobj_priv *dvobj) +{ + return (rtw_phl_is_init_completed(GET_PHL_INFO(dvobj))) ? _TRUE : _FALSE; +} + +#define NSS_VALID(nss) (nss > 0) +void rtw_hw_cap_init(struct dvobj_priv *dvobj) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj); + struct registry_priv *regpriv = + &(dvobj_get_primary_adapter(dvobj)->registrypriv); + +#ifdef DIRTY_FOR_WORK + dvobj->phl_com->tx_nss = hal_spec->tx_nss_num; /*GET_HAL_TX_NSS*/ + if (NSS_VALID(regpriv->tx_nss)) + dvobj->phl_com->tx_nss = + rtw_min(dvobj->phl_com->tx_nss, regpriv->tx_nss); + + dvobj->phl_com->rx_nss = hal_spec->rx_nss_num; /*GET_HAL_RX_NSS*/ + if (NSS_VALID(regpriv->rx_nss)) + dvobj->phl_com->rx_nss = + rtw_min(dvobj->phl_com->rx_nss, regpriv->rx_nss); + + dvobj->phl_com->rf_path_num = hal_spec->rf_reg_path_num; /*GET_HAL_RFPATH_NUM*/ + dvobj->phl_com->rf_type = RF_2T2R; /*GET_HAL_RFPATH*/ + + /* GEORGIA_TODO move related control module to phl layer*/ + /* macid_ctl moved to phl */ + /* dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT); */ + // Freddie ToDo: check macid_number from PHL? + dvobj->wow_ctl.wow_cap = hal_spec->wow_cap; + + dvobj->cam_ctl.sec_cap = hal_spec->sec_cap; + dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT); +#endif +} + + +/* + * _ch_offset_drv2phl() - Convert driver channel offset to PHL type + * @ch_offset: channel offset, ref: HAL_PRIME_CHNL_OFFSET_* + * + * Return PHL channel offset type "enum chan_offset" + */ +static enum chan_offset _ch_offset_drv2phl(u8 ch_offset) +{ + if (ch_offset == CHAN_OFFSET_UPPER) + return CHAN_OFFSET_UPPER; + if (ch_offset == CHAN_OFFSET_LOWER) + return CHAN_OFFSET_LOWER; + + return CHAN_OFFSET_NO_EXT; +} + +/* + * rtw_hw_set_ch_bw() - Set channel, bandwidth and channel offset + * @a: pointer of struct _ADAPTER + * @ch: channel + * @bw: bandwidth + * @offset: channel offset, ref: HAL_PRIME_CHNL_OFFSET_* + * + * Set channel, bandwidth and channel offset. + * + * Return 0 for success, otherwise fail + */ +int rtw_hw_set_ch_bw(struct _ADAPTER *a, u8 ch, enum channel_width bw, + u8 offset, u8 do_rfk) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + int err = 0; + struct rtw_chan_def chdef = {0}; + enum phl_cmd_type cmd_type = PHL_CMD_DIRECTLY; + u32 cmd_timeout = 0; + +#ifdef CONFIG_MCC_MODE + if (rtw_hw_mcc_chk_inprogress(a)) { + RTW_WARN("under mcc, skip ch setting\n"); + return err; + } +#endif + + chdef.chan = ch; + chdef.bw = bw; + chdef.offset = offset; + chdef.band = (ch > 14) ? BAND_ON_5G : BAND_ON_24G; + + _rtw_mutex_lock_interruptible(&dvobj->setch_mutex); +#ifdef DBG_CONFIG_CMD_DISP + if (a->cmd_type == 0xFF) { + cmd_type = PHL_CMD_DIRECTLY; + cmd_timeout = 0; + } + else { + cmd_type = a->cmd_type; + cmd_timeout = a->cmd_timeout; + } +#endif + status = rtw_phl_cmd_set_ch_bw(a->phl_role, + &chdef, do_rfk, + cmd_type, cmd_timeout); + + if (status == RTW_PHL_STATUS_SUCCESS) { + if (a->bNotifyChannelChange) + RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d, success\n", + __FUNCTION__, ch, offset, bw); + + } else { + err = -1; + RTW_ERR("%s: set ch(%u) bw(%u) offset(%u) FAIL!\n", + __func__, ch, bw, offset); + } + + _rtw_mutex_unlock(&dvobj->setch_mutex); + + return err; +} + +void rtw_hw_update_chan_def(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + struct rtw_phl_stainfo_t *phl_sta_self = NULL; + + /*update chan_def*/ + adapter->phl_role->chandef.band = + (mlmeext->chandef.chan > 14) ? BAND_ON_5G : BAND_ON_24G; + adapter->phl_role->chandef.chan = mlmeext->chandef.chan; + adapter->phl_role->chandef.bw = mlmeext->chandef.bw; + adapter->phl_role->chandef.offset = mlmeext->chandef.offset; + adapter->phl_role->chandef.center_ch = rtw_phl_get_center_ch(mlmeext->chandef.chan, + mlmeext->chandef.bw, mlmeext->chandef.offset); + /* ToDo: 80+80 BW & 160 BW */ + + phl_sta_self = rtw_phl_get_stainfo_self(adapter_to_dvobj(adapter)->phl, adapter->phl_role); + _rtw_memcpy(&phl_sta_self->chandef, &adapter->phl_role->chandef, sizeof(struct rtw_chan_def)); +} + +static void _dump_phl_role_info(struct rtw_wifi_role_t *wrole) +{ + RTW_INFO("[WROLE]- role-idx: %d\n", wrole->id); + + RTW_INFO("[WROLE]- type: %d\n", wrole->type); + RTW_INFO("[WROLE]- mstate: %d\n", wrole->mstate); + RTW_INFO("[WROLE]- mac_addr:"MAC_FMT"\n", MAC_ARG(wrole->mac_addr)); + RTW_INFO("[WROLE]- hw_band: %d\n", wrole->hw_band); + RTW_INFO("[WROLE]- hw_port: %d\n", wrole->hw_port); + RTW_INFO("[WROLE]- hw_wmm: %d\n", wrole->hw_wmm); + + RTW_INFO("[WROLE]- band: %d\n", wrole->chandef.band); + RTW_INFO("[WROLE]- chan: %d\n", wrole->chandef.chan); + RTW_INFO("[WROLE]- bw: %d\n", wrole->chandef.bw); + RTW_INFO("[WROLE]- offset: %d\n", wrole->chandef.offset); + // Freddie ToDo: MBSSID +} +u8 rtw_hw_iface_init(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 phl_role_idx = INVALID_WIFI_ROLE_IDX; + u8 rst = _FAIL; + int chctx_num = 0; +#if defined(CONFIG_RTW_IPS) || defined(CONFIG_RTW_LPS) + bool ps_allow = _FALSE; + + rtw_phl_ps_set_rt_cap(GET_PHL_INFO(dvobj), HW_BAND_0, ps_allow, PS_RT_CORE_INIT); +#endif + // Freddie ToDo: For AP mode, net type should be set to net device already. + + /* will allocate phl self sta info */ + phl_role_idx = rtw_phl_wifi_role_alloc(GET_PHL_INFO(dvobj), + adapter_mac_addr(adapter), PHL_RTYPE_STATION, + adapter->iface_id, &(adapter->phl_role), _FALSE); + + if ((phl_role_idx == INVALID_WIFI_ROLE_IDX) || + (adapter->phl_role == NULL)) { + RTW_ERR("rtw_phl_wifi_role_alloc failed\n"); + rtw_warn_on(1); + goto _error; + } + + /*init default value*/ + #ifdef DBG_CONFIG_CMD_DISP + adapter->cmd_type = 0xFF; + adapter->cmd_timeout = 0; + #endif + rtw_hw_update_chan_def(adapter); + chctx_num = rtw_phl_mr_get_chanctx_num(GET_PHL_INFO(dvobj), adapter->phl_role); + + if (chctx_num == 0) { + if (rtw_phl_cmd_set_ch_bw(adapter->phl_role, + &(adapter->phl_role->chandef), + _FALSE, + PHL_CMD_WAIT, 0) != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s init ch failed\n", __func__); + } + } + + _dump_phl_role_info(adapter->phl_role); + + /* init self staion info after wifi role alloc */ + rst = rtw_init_self_stainfo(adapter); + + #if defined (CONFIG_PCI_HCI) && defined (CONFIG_PCIE_TRX_MIT) + rtw_pcie_trx_mit_cmd(adapter, 0, 0, + PCIE_RX_INT_MIT_TIMER, 0, 1); + #endif +#if defined(CONFIG_RTW_IPS) || defined(CONFIG_RTW_LPS) + ps_allow = _TRUE; + rtw_phl_ps_set_rt_cap(GET_PHL_INFO(dvobj), HW_BAND_0, ps_allow, PS_RT_CORE_INIT); +#endif + + return rst; + +_error: + return rst; +} + +u8 rtw_hw_iface_type_change(_adapter *adapter, u8 iface_type) +{ + void *phl = GET_PHL_INFO(adapter_to_dvobj(adapter)); +#ifdef CONFIG_WIFI_MONITOR + struct rtw_phl_com_t *phl_com = GET_PHL_COM(adapter_to_dvobj(adapter)); +#endif + struct rtw_wifi_role_t *wrole = adapter->phl_role; + enum role_type rtype = PHL_RTYPE_NONE; + enum rtw_phl_status status; + struct sta_info *sta = NULL; + + if (wrole == NULL) { + RTW_ERR("%s - wrole = NULL\n", __func__); + rtw_warn_on(1); + return _FAIL; + } + + switch (iface_type) { + case _HW_STATE_ADHOC_: + rtype = PHL_RTYPE_ADHOC; + break; + case _HW_STATE_STATION_: + rtype = PHL_RTYPE_STATION; + break; + case _HW_STATE_AP_: + rtype = PHL_RTYPE_AP; + break; + case _HW_STATE_MONITOR_: + rtype = PHL_RTYPE_MONITOR; + break; + case _HW_STATE_NOLINK_: + default: + /* TBD */ + break; + } + + status = rtw_phl_cmd_wrole_change(phl, wrole, + WR_CHG_TYPE, (u8*)&rtype, sizeof(enum role_type), + PHL_CMD_DIRECTLY, 0); + + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s - change to phl role type = %d fail with error = %d\n", + __func__, rtype, status); + rtw_warn_on(1); + return _FAIL; + } + +#ifdef CONFIG_WIFI_MONITOR + if (rtype == PHL_RTYPE_MONITOR) { + phl_com->append_fcs = false; /* This need to check again by yiwei*/ + rtw_phl_enter_mon_mode(phl, wrole); + } else { + phl_com->append_fcs = true; /* This need to check again by yiwei*/ + rtw_phl_leave_mon_mode(phl, wrole); + } +#endif + + /* AP allocates self-station and changes broadcast-station before hostapd adds key */ + if (rtype == PHL_RTYPE_AP) { + sta = rtw_get_stainfo(&adapter->stapriv, adapter_mac_addr(adapter)); + if (sta == NULL) { + sta = rtw_alloc_stainfo(&adapter->stapriv, adapter_mac_addr(adapter)); + if (sta == NULL) { + RTW_ERR("%s - allocate AP self-station failed\n", __func__); + rtw_warn_on(1); + return _FAIL; + } + } + } + + RTW_INFO("%s - change to type = %d success !\n", __func__, iface_type); + + return _SUCCESS; +} + +void rtw_hw_iface_deinit(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); +#if defined(CONFIG_RTW_IPS) || defined(CONFIG_RTW_LPS) + bool ps_allow = _FALSE; + + rtw_phl_ps_set_rt_cap(GET_PHL_INFO(dvobj), HW_BAND_0, ps_allow, PS_RT_CORE_INIT); +#endif + if (adapter->phl_role) { + rtw_free_self_stainfo(adapter); + rtw_phl_wifi_role_free(GET_PHL_INFO(dvobj), adapter->phl_role->id); + adapter->phl_role = NULL; + } +#if defined(CONFIG_RTW_IPS) || defined(CONFIG_RTW_LPS) + ps_allow = _TRUE; + rtw_phl_ps_set_rt_cap(GET_PHL_INFO(dvobj), HW_BAND_0, ps_allow, PS_RT_CORE_INIT); +#endif +} + +/* + * _sec_algo_drv2phl() - Convert security algorithm to PHL's definition + * @drv_algo: security algorithm + * @phl_algo: security algorithm for PHL, ref to enum rtw_enc_algo + * @phl_key_len: key length + * + * Convert driver's security algorithm defintion to PHL's type. + * + */ +static void _sec_algo_drv2phl(enum security_type drv_algo, + u8 *algo, u8 *key_len) +{ + u8 phl_algo = RTW_ENC_NONE; + u8 phl_key_len = 0; + + switch(drv_algo) { + case _NO_PRIVACY_: + phl_algo = RTW_ENC_NONE; + phl_key_len = 0; + break; + case _WEP40_: + phl_algo = RTW_ENC_WEP40; + phl_key_len = 5; + break; + case _TKIP_: + case _TKIP_WTMIC_: + phl_algo = RTW_ENC_TKIP; + phl_key_len = 16; + break; + case _AES_: + phl_algo = RTW_ENC_CCMP; + phl_key_len = 16; + break; + case _WEP104_: + phl_algo = RTW_ENC_WEP104; + phl_key_len = 13; + break; + case _SMS4_: + phl_algo = RTW_ENC_WAPI; + phl_key_len = 32; + break; + case _GCMP_: + phl_algo = RTW_ENC_GCMP; + phl_key_len = 16; + break; + case _CCMP_256_: + phl_algo = RTW_ENC_CCMP256; + phl_key_len = 32; + break; + case _GCMP_256_: + phl_algo = RTW_ENC_GCMP256; + phl_key_len = 32; + break; +#ifdef CONFIG_IEEE80211W + case _BIP_CMAC_128_: + phl_algo = RTW_ENC_BIP_CCMP128; + phl_key_len = 16; + break; +#endif /* CONFIG_IEEE80211W */ + default: + RTW_ERR("%s: No rule to covert drv algo(0x%x) to phl!!\n", + __func__, drv_algo); + phl_algo = RTW_ENC_MAX; + phl_key_len = 0; + break; + } + + if(algo) + *algo = phl_algo; + if(key_len) + *key_len = phl_key_len; +} + +/* + * _sec_algo_phl2drv() - Convert security algorithm to core layer definition + * @drv_algo: security algorithm for core layer, ref to enum security_type + * @phl_algo: security algorithm for PHL, ref to enum rtw_enc_algo + * @drv_key_len: key length + * + * Convert PHL's security algorithm defintion to core layer definition. + * + */ +static void _sec_algo_phl2drv(enum rtw_enc_algo phl_algo, + u8 *algo, u8 *key_len) +{ + u8 drv_algo = RTW_ENC_NONE; + u8 drv_key_len = 0; + + switch(phl_algo) { + case RTW_ENC_NONE: + drv_algo = _NO_PRIVACY_; + drv_key_len = 0; + break; + case RTW_ENC_WEP40: + drv_algo = _WEP40_; + drv_key_len = 5; + break; + case RTW_ENC_TKIP: + /* drv_algo = _TKIP_WTMIC_ */ + drv_algo = _TKIP_; + drv_key_len = 16; + break; + case RTW_ENC_CCMP: + drv_algo = _AES_; + drv_key_len = 16; + break; + case RTW_ENC_WEP104: + drv_algo = _WEP104_; + drv_key_len = 13; + break; + case RTW_ENC_WAPI: + drv_algo = _SMS4_; + drv_key_len = 32; + break; + case RTW_ENC_GCMP: + drv_algo = _GCMP_; + drv_key_len = 16; + break; + case RTW_ENC_CCMP256: + drv_algo = _CCMP_256_; + drv_key_len = 32; + break; + case RTW_ENC_GCMP256: + drv_algo = _GCMP_256_; + drv_key_len = 32; + break; +#ifdef CONFIG_IEEE80211W + case RTW_ENC_BIP_CCMP128: + drv_algo = _BIP_CMAC_128_; + drv_key_len = 16; + break; +#endif /* CONFIG_IEEE80211W */ + default: + RTW_ERR("%s: No rule to covert phl algo(0x%x) to drv!!\n", + __func__, phl_algo); + drv_algo = _SEC_TYPE_MAX_; + drv_key_len = 0; + break; + } + + if(algo) + *algo = drv_algo; + if(key_len) + *key_len = drv_key_len; +} + +u8 rtw_sec_algo_drv2phl(enum security_type drv_algo) +{ + u8 algo = 0; + + _sec_algo_drv2phl(drv_algo, &algo, NULL); + return algo; +} + +u8 rtw_sec_algo_phl2drv(enum rtw_enc_algo phl_algo) +{ + u8 algo = 0; + + _sec_algo_phl2drv(phl_algo, &algo, NULL); + return algo; +} + +static int rtw_hw_chk_sec_mode(struct _ADAPTER *a, struct sta_info *sta, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + u8 sec_mode = 0; + struct security_priv *psecuritypriv = &a->securitypriv; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + if (!phl) + return _FAIL; + + sec_mode = rtw_phl_trans_sec_mode( + rtw_sec_algo_drv2phl(psecuritypriv->dot11PrivacyAlgrthm), + rtw_sec_algo_drv2phl(psecuritypriv->dot118021XGrpPrivacy)); + + RTW_INFO("After phl trans_sec_mode = %d\n", sec_mode); + + if (sec_mode != sta->phl_sta->sec_mode) { + RTW_INFO("%s: original sec_mode =%d update sec mode to %d.\n", + __func__, sta->phl_sta->sec_mode, sec_mode); + status = rtw_phl_cmd_change_stainfo(phl, sta->phl_sta, STA_CHG_SEC_MODE, + &sec_mode, sizeof(u8), cmd_type, cmd_timeout); + /* To Do: check the return status */ + } else { + RTW_INFO("%s: sec mode remains the same. skip update.\n", __func__); + } + return _SUCCESS; +} + +/* + * rtw_hw_add_key() - Add security key + * @a: pointer of struct _ADAPTER + * @sta: pointer of struct sta_info + * @keyid: key index + * @keyalgo: key algorithm + * @keytype: 0: unicast / 1: multicast / 2: bip (ref: enum SEC_CAM_KEY_TYPE) + * @key: key content + * @spp: spp mode + * + * Add security key. + * + * Return 0 for success, otherwise fail. + */ +int rtw_hw_add_key(struct _ADAPTER *a, struct sta_info *sta, + u8 keyid, enum security_type keyalgo, u8 keytype, u8 *key, + u8 spp, enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct dvobj_priv *d; + void *phl; + struct phl_sec_param_h crypt = {0}; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + if (rtw_hw_chk_sec_mode(a, sta, cmd_type, cmd_timeout) == _FAIL) + return -1; + + crypt.keyid = keyid; + crypt.key_type= keytype; + crypt.spp = spp; + _sec_algo_drv2phl(keyalgo, &crypt.enc_type, &crypt.key_len); + + /* delete key before adding key */ + rtw_phl_cmd_del_key(phl, sta->phl_sta, &crypt, cmd_type, cmd_timeout); + status = rtw_phl_cmd_add_key(phl, sta->phl_sta, &crypt, key, cmd_type, cmd_timeout); + if (status != RTW_PHL_STATUS_SUCCESS) + return -1; + + return 0; +} + +/* + * rtw_hw_del_key() - Delete security key + * @a: pointer of struct _ADAPTER + * @sta: pointer of struct sta_info + * @keyid: key index + * @keytype: 0: unicast / 1: multicast / 2: bip (ref: enum SEC_CAM_KEY_TYPE) + * + * Delete security key by macid, keyid and keytype. + * + * Return 0 for success, otherwise fail. + */ +int rtw_hw_del_key(struct _ADAPTER *a, struct sta_info *sta, + u8 keyid, u8 keytype, enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct dvobj_priv *d; + void *phl; + struct phl_sec_param_h crypt = {0}; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + crypt.keyid = keyid; + crypt.key_type= keytype; + + status = rtw_phl_cmd_del_key(phl, sta->phl_sta, &crypt, cmd_type, cmd_timeout); + if (status != RTW_PHL_STATUS_SUCCESS) + return -1; + + return 0; +} + +/* + * rtw_hw_del_all_key() - Delete all security key for this STA + * @a: pointer of struct _ADAPTER + * @sta: pointer of struct sta_info + * + * Delete all security keys belong to this STA. + * + * Return 0 for success, otherwise fail. + */ +int rtw_hw_del_all_key(struct _ADAPTER *a, struct sta_info *sta, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct dvobj_priv *d; + void *phl; + u8 keyid; + u8 keytype; + struct phl_sec_param_h crypt = {0}; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + /* Delete Group and Pairwise key */ + for (keytype = 0; keytype < 2; keytype++) { + for (keyid = 0; keyid < 4; keyid++) { + crypt.keyid = keyid; + crypt.key_type = keytype; + rtw_phl_cmd_del_key(phl, sta->phl_sta, &crypt, cmd_type, cmd_timeout); + } + } + + /* Delete BIP key */ + crypt.key_type = 2; + for (keyid = 4; keyid <= BIP_MAX_KEYID; keyid++) { + crypt.keyid = keyid; + rtw_phl_cmd_del_key(phl, sta->phl_sta, &crypt, cmd_type, cmd_timeout); + } + + return 0; +} + +int rtw_hw_start_bss_network(struct _ADAPTER *a) +{ + /* some hw related ap settings */ + if (rtw_phl_ap_started(adapter_to_dvobj(a)->phl, a->phl_role) != + RTW_PHL_STATUS_SUCCESS) + return _FAIL; + + return _SUCCESS; +} + +/* connect */ +int rtw_hw_prepare_connect(struct _ADAPTER *a, struct sta_info *sta, u8 *target_addr) +{ + /*adapter->phl_role.mac_addr*/ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + status = rtw_phl_connect_prepare(phl, a->phl_role, target_addr); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s: Fail to setup hardware for connecting!(%d)\n", + __func__, status); + return -1; + } + /* Todo: Enable TSF update */ + /* Todo: Set support short preamble or not by beacon capability */ + /* Todo: Set slot time */ + + return 0; +} + +/* Handle connect fail case */ +int rtw_hw_connect_abort(struct _ADAPTER *a, struct sta_info *sta) +{ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + rtw_hw_del_all_key(a, sta, PHL_CMD_DIRECTLY, 0); + + status = rtw_phl_cmd_update_media_status(phl, sta->phl_sta, NULL, false, + PHL_CMD_DIRECTLY, 0); + if (status != RTW_PHL_STATUS_SUCCESS) + return -1; + +#ifndef CONFIG_STA_CMD_DISPR + /* + * In CONFIG_STA_CMD_DISPR case, connect abort hw setting has been moved + * to MSG_EVT_DISCONNECT@PHL_FG_MDL_CONNECT . + */ + + /* disconnect hw setting */ + rtw_phl_disconnect(phl, a->phl_role); + + /* delete sta channel ctx */ + rtw_phl_chanctx_del(adapter_to_dvobj(a)->phl, a->phl_role, NULL); + /* restore orig union ch */ + rtw_join_done_chk_ch(a, -1); + + /* free connecting AP sta info */ + rtw_free_stainfo(a, sta); + rtw_init_self_stainfo(a); +#endif /* !CONFIG_STA_CMD_DISPR */ + + return 0; +} + +#ifdef RTW_WKARD_UPDATE_PHL_ROLE_CAP +/** + * rtw_update_phl_cap_by_rgstry() - Update cap & proto_role_cap of phl_role + * @a: struct _ADAPTER* + * + * Update cap & proto_role_cap of a->phl_role by registry/driver parameters. + * + */ +void rtw_update_phl_cap_by_rgstry(struct _ADAPTER *a) +{ + struct registry_priv *rgstry; + struct role_cap_t *cap; + struct protocol_cap_t *prtcl; + + rgstry = &a->registrypriv; + cap = &a->phl_role->cap; + prtcl = &a->phl_role->proto_role_cap; + + /* LDPC */ + prtcl->ht_ldpc &= (TEST_FLAG(rgstry->ldpc_cap, BIT4) ? 1 : 0); + cap->tx_ht_ldpc &= (TEST_FLAG(rgstry->ldpc_cap, BIT5) ? 1 : 0); + prtcl->vht_ldpc &= (TEST_FLAG(rgstry->ldpc_cap, BIT0) ? 1 : 0); + cap->tx_vht_ldpc &= (TEST_FLAG(rgstry->ldpc_cap, BIT1) ? 1 : 0); + /* no HE LDPC control setting in registry, follow PHL default */ +} +#endif /* RTW_WKARD_UPDATE_PHL_ROLE_CAP */ + +static void _dump_phl_sta_asoc_cap(struct sta_info *sta) +{ + struct rtw_phl_stainfo_t *phl_sta = sta->phl_sta; + struct protocol_cap_t *asoc_cap = &phl_sta->asoc_cap; +#define _loc_dbg_func RTW_DBG +#define _loc_dbg(f) _loc_dbg_func(#f ": %u\n", asoc_cap->f) + + + _loc_dbg_func("[PHL STA ASOC CAP]- mac_addr: " MAC_FMT "\n", + MAC_ARG(phl_sta->mac_addr)); + _loc_dbg(ht_ldpc); + _loc_dbg(vht_ldpc); + _loc_dbg(he_ldpc); + _loc_dbg(stbc_ht_rx); + _loc_dbg(stbc_vht_rx); + _loc_dbg(stbc_he_rx); + _loc_dbg(vht_su_bfmr); + _loc_dbg(vht_su_bfme); + _loc_dbg(vht_mu_bfmr); + _loc_dbg(vht_mu_bfme); + _loc_dbg(bfme_sts); + _loc_dbg(num_snd_dim); + _loc_dbg_func("[PHL STA ASOC CAP]- end\n"); +} + +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT +static void update_phl_sta_cap_vht(struct _ADAPTER *a, struct sta_info *sta, + struct protocol_cap_t *cap) +{ + struct vht_priv *vht; + + + vht = &sta->vhtpriv; + + if (cap->ampdu_len_exp < vht->ampdu_len) + cap->ampdu_len_exp = vht->ampdu_len; + if (cap->max_amsdu_len < vht->max_mpdu_len) + cap->max_amsdu_len = vht->max_mpdu_len; + + cap->sgi_80 = (vht->sgi_80m == _TRUE) ? 1 : 0; + + _rtw_memcpy(cap->vht_rx_mcs, vht->vht_mcs_map, 2); + /* Todo: cap->vht_tx_mcs[2]; */ + if (vht->op_present) + _rtw_memcpy(cap->vht_basic_mcs, &vht->vht_op[3], 2); +} +#endif /* CONFIG_80211AC_VHT */ +static void update_phl_sta_cap_ht(struct _ADAPTER *a, struct sta_info *sta, + struct protocol_cap_t *cap) +{ + struct mlme_ext_info *info; + struct ht_priv *ht; + + + info = &a->mlmeextpriv.mlmext_info; + ht = &sta->htpriv; + + cap->num_ampdu = 0xFF; /* Set to MAX */ + + cap->ampdu_density = ht->rx_ampdu_min_spacing; + cap->ampdu_len_exp = GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(&ht->ht_cap); + cap->amsdu_in_ampdu = 1; + cap->max_amsdu_len = GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(&ht->ht_cap); + + /*GET_HT_CAP_ELE_SM_PS(&info->HT_caps.u.HT_cap_element.HT_caps_info);*/ + cap->sm_ps = info->SM_PS; + + cap->sgi_20 = (ht->sgi_20m == _TRUE) ? 1 : 0; + cap->sgi_40 = (ht->sgi_40m == _TRUE) ? 1 : 0; + + _rtw_memcpy(cap->ht_rx_mcs, ht->ht_cap.supp_mcs_set, 4); + /* Todo: cap->ht_tx_mcs[4]; */ + if (info->HT_info_enable) + _rtw_memcpy(cap->ht_basic_mcs, info->HT_info.MCS_rate, 4); +} +#endif /* CONFIG_80211N_HT */ + +void rtw_update_phl_sta_cap(struct _ADAPTER *a, struct sta_info *sta, + struct protocol_cap_t *cap) +{ + struct mlme_ext_info *info; + + + info = &a->mlmeextpriv.mlmext_info; + + /* MAC related */ + /* update beacon interval */ + cap->bcn_interval = info->bcn_interval; +#if 0 + cap->num_ampdu; /* HT, VHT, HE */ + cap->ampdu_density:3; /* HT, VHT, HE */ + cap->ampdu_len_exp; /* HT, VHT, HE */ + cap->amsdu_in_ampdu:1; /* HT, VHT, HE */ + cap->max_amsdu_len:2; /* HT, VHT, HE */ + cap->htc_rx:1; + cap->sm_ps:2; /* HT */ + cap->trig_padding:2; + cap->twt:6; + cap->all_ack:1; + cap->a_ctrl:3; + cap->ops:1; + cap->ht_vht_trig_rx:1; +#endif + cap->short_slot = (info->slotTime == SHORT_SLOT_TIME) ? 1 : 0; + cap->preamble = (info->preamble_mode == PREAMBLE_SHORT) ? 1 : 0; +#if 0 + cap->sgi_20:1; /* HT */ + cap->sgi_40:1; /* HT */ + cap->sgi_80:1; /* VHT */ + cap->sgi_160:1 /* VHT, HE */ + + /* BB related */ + cap->ht_ldpc:1; /* HT, HT_caps_handler() */ + cap->vht_ldpc:1; /* VHT, VHT_caps_handler() */ + cap->he_ldpc:1; /* HE, HE_phy_caps_handler() */ + cap->sgi:1; + cap->su_bfmr:1; + cap->su_bfme:1; + cap->mu_bfmr:1; + cap->mu_bfme:1; + cap->bfme_sts:3; + cap->num_snd_dim:3; +#endif + _rtw_memset(cap->supported_rates, 0, 12); + _rtw_memcpy(cap->supported_rates, sta->bssrateset, + sta->bssratelen < 12 ? sta->bssratelen : 12); +#if 0 + cap->ht_rx_mcs[4]; /* HT */ + cap->ht_tx_mcs[4]; /* HT */ + cap->ht_basic_mcs[4]; /* Basic rate of HT */ + cap->vht_rx_mcs[2]; /* VHT */ + cap->vht_tx_mcs[2]; /* VHT */ + cap->vht_basic_mcs[2]; /* Basic rate of VHT */ +#endif +#if 0 + /* HE done */ + cap->he_rx_mcs[2]; + cap->he_tx_mcs[2]; + cap->he_basic_mcs[2]; /* Basic rate of HE */ + cap->stbc_ht_rx:2; /* HT_caps_handler() */ + cap->stbc_vht_rx:3; /* VHT_caps_handler() */ + cap->stbc_he_rx:1; /* HE_phy_caps_handler() */ + cap->stbc_tx:1; + cap->ltf_gi; + cap->doppler_tx:1; + cap->doppler_rx:1; + cap->dcm_max_const_tx:2; + cap->dcm_max_nss_tx:1; + cap->dcm_max_const_rx:2; + cap->dcm_max_nss_rx:1; + cap->partial_bw_su_in_mu:1; + cap->bfme_sts_greater_80mhz:3; + cap->num_snd_dim_greater_80mhz:3; + cap->stbc_tx_greater_80mhz:1; + cap->stbc_rx_greater_80mhz:1; + cap->ng_16_su_fb:1; + cap->ng_16_mu_fb:1; + cap->cb_sz_su_fb:1; + cap->cb_sz_mu_fb:1; + cap->trig_su_bfm_fb:1; + cap->trig_mu_bfm_fb:1; + cap->trig_cqi_fb:1; + cap->partial_bw_su_er:1; + cap->pkt_padding:2; + cap->ppe_th[24]; + cap->pwr_bst_factor:1; + cap->max_nc:3; + cap->dcm_max_ru:2; + cap->long_sigb_symbol:1; + cap->non_trig_cqi_fb:1; + cap->tx_1024q_ru:1; + cap->rx_1024q_ru:1; + cap->fbw_su_using_mu_cmprs_sigb:1; + cap->fbw_su_using_mu_non_cmprs_sigb:1; + cap->er_su:1; + cap->tb_pe:3; + cap->txop_du_rts_th; +#endif + +#ifdef CONFIG_80211N_HT + if (sta->htpriv.ht_option) { + update_phl_sta_cap_ht(a, sta, cap); +#ifdef CONFIG_80211AC_VHT + if (sta->vhtpriv.vht_option) + update_phl_sta_cap_vht(a, sta, cap);; +#endif /* CONFIG_80211AC_VHT */ + } +#endif /* CONFIG_80211N_HT */ +} + +/** + * rtw_hw_set_edca() - setup WMM EDCA parameter + * @a: struct _ADAPTER * + * @ac: Access Category, 0:BE, 1:BK, 2:VI, 3:VO + * @param: AIFS:BIT[7:0], CWMIN:BIT[11:8], CWMAX:BIT[15:12], + * TXOP:BIT[31:16] + * + * Setup WMM EDCA parameter set. + * + * Return 0 for SUCCESS, otherwise fail. + */ +int rtw_hw_set_edca(struct _ADAPTER *a, u8 ac, u32 param) +{ + struct dvobj_priv *d; + void *phl; + struct rtw_edca_param edca = {0}; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + edca.ac = ac; + edca.param = param; + + status = rtw_phl_cmd_wrole_change(phl, a->phl_role, + WR_CHG_EDCA_PARAM, (u8*)&edca, sizeof(struct rtw_edca_param), + PHL_CMD_DIRECTLY, 0); + + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s: fail to set edca parameter, ac(%u), " + "param(0x%08x)\n", + __func__, ac, param); + return -1; + } + + return 0; +} + +int rtw_hw_connected(struct _ADAPTER *a, struct sta_info *sta) +{ + + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + struct security_priv *psecuritypriv = &a->securitypriv; +#ifdef CONFIG_STA_MULTIPLE_BSSID + struct mlme_ext_priv *pmlmeext = &a->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#endif + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + rtw_update_phl_sta_cap(a, sta, &sta->phl_sta->asoc_cap); + _dump_phl_sta_asoc_cap(sta); + +#ifdef CONFIG_STA_MULTIPLE_BSSID + /*use addr cam mask 0x1F to receive byte0~byte4 the same BSSID address == STA_CHG_MBSSID*/ + if (pmlmeinfo->network.is_mbssid) { + sta->phl_sta->addr_sel = 3; /*MAC_AX_BSSID_MSK*/ + sta->phl_sta->addr_msk = 0x1F; /*MAC_AX_BYTE5*/ + } +#endif + + status = rtw_phl_cmd_update_media_status(phl, sta->phl_sta, + sta->phl_sta->mac_addr, true, + PHL_CMD_DIRECTLY, 0); + if (status != RTW_PHL_STATUS_SUCCESS) + return -1; + rtw_dump_phl_sta_info(RTW_DBGDUMP, sta); + + /* Todo: update IOT-releated issue */ +#if 0 + update_IOT_info(a); +#endif + /* Todo: RTS full bandwidth setting */ +#if 0 +#ifdef CONFIG_RTS_FULL_BW + rtw_set_rts_bw(a); +#endif /* CONFIG_RTS_FULL_BW */ +#endif + /* Todo: Basic rate setting */ +#if 0 + rtw_hal_set_hwreg(a, HW_VAR_BASIC_RATE, cur_network->SupportedRates); +#endif + /* Todo: udpate capability: short preamble, slot time */ + update_capinfo(a, a->mlmeextpriv.mlmext_info.capability); + + WMMOnAssocRsp(a); + + /* Todo: HT: AMPDU factor, min space, max time and related parameters */ +#if 0 +#ifdef CONFIG_80211N_HT + HTOnAssocRsp(a); +#endif /* CONFIG_80211N_HT */ +#endif + /* Todo: VHT */ +#if 0 +#ifdef CONFIG_80211AC_VHT + VHTOnAssocRsp(a); +#endif +#endif + /* Todo: Set Data rate and RA */ +#if 0 + set_sta_rate(a, psta); +#endif + /* Todo: Firmware media status report */ +#if 0 + rtw_sta_media_status_rpt(a, psta, 1); +#endif + /* Todo: IC specific hardware setting */ +#if 0 + join_type = 2; + rtw_hal_set_hwreg(a, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); +#endif + if ((a->mlmeextpriv.mlmext_info.state & 0x03) == WIFI_FW_STATION_STATE) { + /* Todo: Correct TSF */ +#if 0 + correct_TSF(a, MLME_STA_CONNECTED); +#endif + } + + /* Todo: btcoex connect event notify */ +#if 0 + rtw_btcoex_connect_notify(a, join_type); +#endif + /* Todo: Beamforming setting */ +#if 0 + beamforming_wk_cmd(a, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0); +#endif + + rtw_join_done_chk_ch(a, 1); + rtw_phl_connected(phl, a->phl_role, sta->phl_sta); +#ifdef CONFIG_80211AX_HE + rtw_he_init_om_info(a); +#endif + ATOMIC_SET(&a->need_tsf_sync_done, _TRUE); + return 0; +} + +int rtw_hw_disconnect(struct _ADAPTER *a, struct sta_info *sta) +{ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + int tid; + u8 is_ap_self = _FALSE; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + if (MLME_IS_AP(a) && + _rtw_memcmp(a->phl_role->mac_addr, sta->phl_sta->mac_addr, ETH_ALEN)) + is_ap_self = _TRUE; + + /* Check and reset setting related to rx ampdu resources of PHL. */ + for (tid = 0; tid < TID_NUM; tid++) { + if(sta->recvreorder_ctrl[tid].enable == _TRUE) { + sta->recvreorder_ctrl[tid].enable =_FALSE; + rtw_phl_stop_rx_ba_session(phl, sta->phl_sta, tid); + RTW_INFO(FUNC_ADPT_FMT"stop process tid %d \n", + FUNC_ADPT_ARG(a), tid); + } + } + + /*reset sec setting and clean all connection setting*/ + rtw_hw_del_all_key(a, sta, PHL_CMD_DIRECTLY, 0); + + if (is_ap_self == _FALSE) { + status = rtw_phl_cmd_update_media_status(phl, sta->phl_sta, NULL, false, + PHL_CMD_DIRECTLY, 0); + if (status != RTW_PHL_STATUS_SUCCESS) + return -1; + + rtw_dump_phl_sta_info(RTW_DBGDUMP, sta); + } + + if (MLME_IS_STA(a)) { + /* + * the following flow only for STA + * bypass client disconnect from softAP + */ +#ifndef CONFIG_STA_CMD_DISPR + rtw_phl_disconnect(phl, a->phl_role); +#endif /* !CONFIG_STA_CMD_DISPR */ + rtw_disconnect_ch_switch(a); + } + + return 0; +} + +int rtw_hw_connected_apmode(struct _ADAPTER *a, struct sta_info *sta) +{ + struct dvobj_priv *d; + void *phl; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + if (!phl) + return -1; + + rtw_ap_set_sta_wmode(a, sta); + update_sta_ra_info(a, sta); + rtw_update_phl_sta_cap(a, sta, &sta->phl_sta->asoc_cap); + + if (RTW_PHL_STATUS_SUCCESS != rtw_phl_cmd_update_media_status( + phl, sta->phl_sta, sta->phl_sta->mac_addr, true, + PHL_CMD_DIRECTLY, 0)) + return -1; + + rtw_dump_phl_sta_info(RTW_DBGDUMP, sta); + + return 0; +} + +u8 rtw_hal_get_def_var(struct _ADAPTER *a, + enum _HAL_DEF_VARIABLE def_var, void *val) +{ + switch (def_var) { + case HAL_DEF_IS_SUPPORT_ANT_DIV: + *(u8*)val = _FALSE; + break; + case HAL_DEF_DBG_DUMP_RXPKT: + *(u8*)val = 0; + break; + case HAL_DEF_BEAMFORMER_CAP: + *(u8*)val = a->phl_role->proto_role_cap.num_snd_dim; + break; + case HAL_DEF_BEAMFORMEE_CAP: + *(u8*)val = a->phl_role->proto_role_cap.bfme_sts; + break; + case HW_VAR_MAX_RX_AMPDU_FACTOR: + /* HT only */ + *(enum _HT_CAP_AMPDU_FACTOR*)val = MAX_AMPDU_FACTOR_64K; + break; + case HW_DEF_RA_INFO_DUMP: + /* do nothing */ + break; + case HAL_DEF_DBG_DUMP_TXPKT: + *(u8*)val = 0; + break; + case HAL_DEF_TX_PAGE_SIZE: + /* would be removed later */ + break; + case HW_VAR_BEST_AMPDU_DENSITY: + *(u8*)val = 0; + break; + default: + break; + } + + return 0; +} + +#ifdef RTW_DETECT_HANG +#define HANG_DETECT_THR 3 +void rtw_is_rxff_hang(_adapter *padapter, struct rxff_hang_info *prxff_hang_info) +{ + struct dvobj_priv *pdvobjpriv = padapter->dvobj; + void *phl = GET_PHL_INFO(pdvobjpriv); + enum rtw_rx_status rx_sts; + + rx_sts = rtw_phl_get_rx_status(phl); + if (rx_sts == RTW_STATUS_RXDMA_HANG || + rx_sts == RTW_STATUS_RXFIFO_HANG) { + if (prxff_hang_info->rx_ff_hang_cnt < HANG_DETECT_THR) + prxff_hang_info->rx_ff_hang_cnt++; + } else { + prxff_hang_info->rx_ff_hang_cnt = 0; + } + + if (prxff_hang_info->rx_ff_hang_cnt == HANG_DETECT_THR) + prxff_hang_info->dbg_is_rxff_hang = _TRUE; + else + prxff_hang_info->dbg_is_rxff_hang = _FALSE; +} + +void rtw_is_fw_hang(_adapter *padapter, struct fw_hang_info *pfw_hang_info) +{ + struct dvobj_priv *pdvobjpriv = padapter->dvobj; + void *phl = GET_PHL_INFO(pdvobjpriv); + enum rtw_fw_status fw_sts; + + fw_sts = rtw_phl_get_fw_status(phl); + + if (fw_sts == RTW_FW_STATUS_NOFW) { + pfw_hang_info->dbg_is_fw_gone = _TRUE; + pfw_hang_info->dbg_is_fw_hang = _FALSE; + } else { + pfw_hang_info->dbg_is_fw_gone = _FALSE; + + if (fw_sts == RTW_FW_STATUS_ASSERT || + fw_sts == RTW_FW_STATUS_EXCEP || + fw_sts == RTW_FW_STATUS_RXI300 || + fw_sts == RTW_FW_STATUS_HANG) + pfw_hang_info->dbg_is_fw_hang = _TRUE; + else + pfw_hang_info->dbg_is_fw_hang = _FALSE; + } +} + +void rtw_is_hang_check(_adapter *padapter) +{ + u32 start_time = rtw_get_current_time(); + struct dvobj_priv *pdvobjpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &pdvobjpriv->drv_dbg; + struct hang_info *phang_info = &pdbgpriv->dbg_hang_info; + /* struct fw_hang_info *pfw_hang_info = &phang_info->dbg_fw_hang_info; */ + struct rxff_hang_info *prxff_hang_info = &phang_info->dbg_rxff_hang_info; + struct fw_hang_info *pfw_hang_info = &phang_info->dbg_fw_hang_info; + u8 is_fw_in_ps_mode = _FALSE; + u8 is_fw_ps_awake = _TRUE; + + if (rtw_hw_get_init_completed(pdvobjpriv) && (!is_fw_in_ps_mode) && + is_fw_ps_awake) { + phang_info->enter_cnt++; + + rtw_is_rxff_hang(padapter, prxff_hang_info); + rtw_is_fw_hang(padapter, pfw_hang_info); + } +} +#endif /* RTW_DETECT_HANG */ + +#ifdef CONFIG_RTW_ACS +u16 rtw_acs_get_channel_by_idx(struct _ADAPTER *a, u8 idx) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + void *phl = GET_PHL_INFO(d); + + if (phl) + return rtw_phl_acs_get_channel_by_idx(phl, idx); + else + return 0; +} + +u8 rtw_acs_get_clm_ratio_by_idx(struct _ADAPTER *a, u8 idx) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + void *phl = GET_PHL_INFO(d); + + if (phl) + return rtw_phl_acs_get_clm_ratio_by_idx(phl, idx); + else + return 0; +} + +s8 rtw_noise_query_by_idx(struct _ADAPTER *a, u8 idx) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + void *phl = GET_PHL_INFO(d); + + if (phl) + return rtw_phl_noise_query_by_idx(phl, idx); + else + return 0; +} +#endif /* CONFIG_RTW_ACS */ + +void rtw_dump_env_rpt(struct _ADAPTER *a, void *sel) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(d); + void *phl = GET_PHL_INFO(d); + struct rtw_env_report rpt; + + rtw_phl_get_env_rpt(phl, &rpt, a->phl_role); + + RTW_PRINT_SEL(sel, "clm_ratio:%d (%%)\n", rpt.nhm_cca_ratio); + RTW_PRINT_SEL(sel, "nhm_ratio:%d (%%)\n", rpt.nhm_ratio); +} + +#ifdef CONFIG_WOWLAN +static u8 _cfg_keep_alive_info(struct _ADAPTER *a, u8 enable) +{ + struct rtw_keep_alive_info info; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + u8 check_period = 5; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + _rtw_memset(&info, 0, sizeof(struct rtw_keep_alive_info)); + + info.keep_alive_en = enable; + info.keep_alive_period = check_period; + + RTW_INFO("%s: keep_alive_en=%d, keep_alive_period=%d\n", + __func__, info.keep_alive_en, info.keep_alive_period); + + status = rtw_phl_cfg_keep_alive_info(phl, &info); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } + + return _SUCCESS; +} + +static u8 _cfg_disc_det_info(struct _ADAPTER *a, u8 enable) +{ + struct wow_priv *wowpriv = adapter_to_wowlan(a); + struct rtw_disc_det_info *wow_disc = &wowpriv->wow_disc; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + struct registry_priv *registry_par; + u8 check_period = 100, trypkt_num = 5; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + registry_par = &a->registrypriv; + + wow_disc->disc_det_en = enable; + + /* wake up event includes deauth wake up */ + if (registry_par->wakeup_event & BIT(2)) + wow_disc->disc_wake_en = _TRUE; + else + wow_disc->disc_wake_en = _FALSE; + wow_disc->try_pkt_count = trypkt_num; + wow_disc->check_period = check_period; + + wow_disc->cnt_bcn_lost_en = 0; + wow_disc->cnt_bcn_lost_limit = 0; + + status = rtw_phl_cfg_disc_det_info(phl, wow_disc); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } + + return _SUCCESS; +} + +static u8 _cfg_nlo_info(struct _ADAPTER *a) +{ + struct rtw_nlo_info info; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + _rtw_memset(&info, 0, sizeof(struct rtw_nlo_info)); + status = rtw_phl_cfg_nlo_info(phl, &info); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } + + return _SUCCESS; +} + +static u8 _cfg_arp_ofld_info(struct _ADAPTER *a) +{ + struct rtw_arp_ofld_info info; + struct dvobj_priv *d; + struct registry_priv *registry_par; + void *phl; + struct mlme_ext_priv *pmlmeext = &(a->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + /* struct mlme_priv *pmlmepriv = &(a->mlmepriv); */ + /* u8 *target_ip = NULL, *target_mac = NULL; */ + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + registry_par = &a->registrypriv; + _rtw_memset(&info, 0, sizeof(struct rtw_arp_ofld_info)); + + if (registry_par->wakeup_event) + info.arp_en = 1; + else + info.arp_en = 0; + + if (info.arp_en) { + /* Sender IP address */ + _rtw_memcpy(info.arp_ofld_content.host_ipv4_addr, + pmlmeinfo->ip_addr, + IPV4_ADDRESS_LENGTH); + +/* TODO : FW doesn't support arp keep alive */ +/* #ifdef CONFIG_ARP_KEEP_ALIVE */ +#if 0 + if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) { + target_ip = pmlmepriv->gw_ip; + target_mac = pmlmepriv->gw_mac_addr; + RTW_INFO("Enabel CONFIG_ARP_KEEP_ALIVE\n"); + } else +#endif + +/* No need to fill Target IP & Target MAC address. + * FW will fill correct Target IP & Target MAC address. */ +#if 0 + { + target_ip = pmlmeinfo->ip_addr; + target_mac = get_my_bssid(&(pmlmeinfo->network)); + } + + /* Targe IP address */ + _rtw_memcpy(info.arp_ofld_content.remote_ipv4_addr, target_ip, + IPV4_ADDRESS_LENGTH); + + /* PHL doesn't use this variable */ + _rtw_memcpy(&(info.arp_ofld_content.mac_addr[0]), target_mac, + MAC_ADDRESS_LENGTH); +#endif + } + + rtw_phl_cfg_arp_ofld_info(phl, &info); + + return _SUCCESS; +} + +static u8 _cfg_ndp_ofld_info(struct _ADAPTER *a) +{ + struct rtw_ndp_ofld_info info; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + _rtw_memset(&info, 0, sizeof(struct rtw_ndp_ofld_info)); + + rtw_phl_cfg_ndp_ofld_info(phl, &info); + + return _SUCCESS; +} + +#ifdef CONFIG_GTK_OL +static u8 _cfg_gtk_ofld_info(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + struct rtw_gtk_ofld_info gtk_ofld_info = {0}; + struct rtw_gtk_ofld_content *gtk_ofld_content = NULL; + struct security_priv *securitypriv = &a->securitypriv; + struct sta_info *sta = NULL; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + sta = rtw_get_stainfo(&a->stapriv, get_bssid(&a->mlmepriv)); + gtk_ofld_content = >k_ofld_info.gtk_ofld_content; + + if (securitypriv->binstallKCK_KEK) { + gtk_ofld_info.gtk_en = _TRUE; + + gtk_ofld_info.akmtype_byte3 = securitypriv->rsn_akm_suite_type; + + gtk_ofld_content->kck_len = RTW_KCK_LEN; + _rtw_memcpy(gtk_ofld_content->kck, sta->kck, RTW_KCK_LEN); + + gtk_ofld_content->kek_len = RTW_KEK_LEN; + _rtw_memcpy(gtk_ofld_content->kek, sta->kek, RTW_KEK_LEN); + + if (securitypriv->dot11PrivacyAlgrthm == _TKIP_) { + gtk_ofld_info.tkip_en = _TRUE; + /* The driver offloads the Tx MIC key here, which is + * actually the Rx MIC key, but the driver definition is + * the opposite of the correct definition. + */ + _rtw_memcpy(gtk_ofld_content->rxmickey, + sta->dot11tkiptxmickey.skey, RTW_TKIP_MIC_LEN); + } + + _rtw_memcpy(gtk_ofld_content->replay_cnt, sta->replay_ctr, + RTW_REPLAY_CTR_LEN); + } + +#ifdef CONFIG_IEEE80211W + if (SEC_IS_BIP_KEY_INSTALLED(securitypriv)) { + gtk_ofld_info.ieee80211w_en = 1; + RTW_PUT_LE32(gtk_ofld_content->igtk_keyid, + securitypriv->dot11wBIPKeyid); + RTW_PUT_LE64(gtk_ofld_content->ipn, + securitypriv->dot11wBIPrxpn.val); + _rtw_memcpy(gtk_ofld_content->igtk[0], + securitypriv->dot11wBIPKey[4].skey, RTW_IGTK_LEN); + _rtw_memcpy(gtk_ofld_content->igtk[1], + securitypriv->dot11wBIPKey[5].skey, RTW_IGTK_LEN); + gtk_ofld_content->igtk_len = RTW_IGTK_LEN; + + _rtw_memcpy(gtk_ofld_content->psk, + sta->dot118021x_UncstKey.skey, RTW_PTK_LEN); + gtk_ofld_content->psk_len = RTW_PTK_LEN; + } +#endif + + rtw_phl_cfg_gtk_ofld_info(phl, >k_ofld_info); + + return _SUCCESS; +} +#endif + +static u8 _cfg_realwow_info(struct _ADAPTER *a) +{ + struct rtw_realwow_info info; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + /* default disable */ + _rtw_memset(&info, 0, sizeof(struct rtw_realwow_info)); + status = rtw_phl_cfg_realwow_info(phl, &info); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } + + return _SUCCESS; +} + +static u8 _cfg_wow_wake(struct _ADAPTER *a, u8 wow_en) +{ + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + struct wow_priv *wowpriv = adapter_to_wowlan(a); + struct rtw_wow_wake_info *wow_wake_event = &wowpriv->wow_wake_event; + struct security_priv *securitypriv; + struct registry_priv *registry_par = &a->registrypriv; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + securitypriv = &a->securitypriv; + + wow_wake_event->wow_en = _TRUE; + /* wake up by magic packet */ + if (registry_par->wakeup_event & BIT(0)) + wow_wake_event->magic_pkt_en = _TRUE; + else + wow_wake_event->magic_pkt_en = _FALSE; + /* wake up by deauth packet */ + if (registry_par->wakeup_event & BIT(2)) + wow_wake_event->deauth_wakeup = _TRUE; + else + wow_wake_event->deauth_wakeup = _FALSE; + /* wake up by pattern match packet */ + if (registry_par->wakeup_event & (BIT(1) | BIT(3))) { + wow_wake_event->pattern_match_en = _TRUE; + + rtw_wow_pattern_clean(a, RTW_DEFAULT_PATTERN); + + if (registry_par->wakeup_event & BIT(1)) + rtw_set_default_pattern(a); + + if (!(registry_par->wakeup_event & BIT(3))) + rtw_wow_pattern_clean(a, RTW_CUSTOMIZED_PATTERN); + } else { + wow_wake_event->pattern_match_en = _FALSE; + } + /* wake up by ptk rekey */ + if (registry_par->wakeup_event & BIT(4)) + wow_wake_event->rekey_wakeup = _TRUE; + else + wow_wake_event->rekey_wakeup = _FALSE; + + wow_wake_event->pairwise_sec_algo = rtw_sec_algo_drv2phl(securitypriv->dot11PrivacyAlgrthm); + wow_wake_event->group_sec_algo = rtw_sec_algo_drv2phl(securitypriv->dot118021XGrpPrivacy); +#ifdef CONFIG_IEEE80211W + if (SEC_IS_BIP_KEY_INSTALLED(securitypriv)) + wow_wake_event->bip_sec_algo = rtw_sec_algo_drv2phl(securitypriv->dot11wCipher); +#endif + + rtw_construct_remote_control_info(a, &wow_wake_event->remote_wake_ctrl_info); + + status = rtw_phl_cfg_wow_wake(phl, wow_wake_event); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } + + return _SUCCESS; +} + +static u8 _cfg_wow_gpio(struct _ADAPTER *a) +{ + struct rtw_wow_wake_info info; + struct dvobj_priv *d; + void *phl; + enum rtw_phl_status status; + struct wow_priv *wowpriv = adapter_to_wowlan(a); + struct rtw_wow_gpio_info *wow_gpio = &wowpriv->wow_gpio; + struct registry_priv *registry_par = &a->registrypriv; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); +#ifdef CONFIG_GPIO_WAKEUP + wow_gpio->dev2hst_gpio_en = _TRUE; + + /* ToDo: fw/halmac do not support so far + pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV; + */ +#ifdef CONFIG_RTW_ONE_PIN_GPIO + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_INPUT; + status = rtw_phl_cfg_wow_set_sw_gpio_mode(phl, gpio); +#else + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_OUTPUT_OD; + wow_gpio->gpio_output_input = _TRUE; + #else + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_OUTPUT_PP; + wow_gpio->gpio_output_input = _FALSE; + #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ + /* switch GPIO to open-drain or push-pull */ + status = rtw_phl_cfg_wow_set_sw_gpio_mode(phl, wow_gpio); + /*default low active, gpio_active and dev2hst_high is the same thing + , but two halmac implementation. FW and halmac need to refine */ + status = rtw_phl_cfg_wow_sw_gpio_ctrl(phl, wow_gpio); + RTW_INFO("%s: set GPIO_%d %d as default. status=%d\n", + __func__, WAKEUP_GPIO_IDX, wow_gpio->dev2hst_high, status); +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ + + /* SDIO inband wake sdio_wakeup_enable + wow_gpio->data_pin_wakeup = info->data_pin_wakeup; + */ + /* two halmac implementation. FW and halmac need to refine */ + wow_gpio->dev2hst_gpio = WAKEUP_GPIO_IDX; + wow_gpio->gpio_num = WAKEUP_GPIO_IDX; + + status = rtw_phl_cfg_gpio_wake_pulse(phl, wow_gpio); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s fail(%d)\n", __func__, status); + return _FAIL; + } +#endif /* CONFIG_GPIO_WAKEUP */ + return _SUCCESS; +} + +static u8 _wow_cfg(struct _ADAPTER *a, u8 wow_en) +{ + struct dvobj_priv *d; + void *phl; + struct rtw_phl_stainfo_t *phl_sta; + enum rtw_phl_status status; + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + if (!_cfg_keep_alive_info(a, wow_en)) + return _FAIL; + + if(!_cfg_disc_det_info(a, wow_en)) + return _FAIL; + + if (!_cfg_nlo_info(a)) + return _FAIL; + + if (!_cfg_arp_ofld_info(a)) + return _FAIL; + + if (!_cfg_ndp_ofld_info(a)) + return _FAIL; + +#ifdef CONFIG_GTK_OL + if (!_cfg_gtk_ofld_info(a)) + return _FAIL; +#endif + + if (!_cfg_realwow_info(a)) + return _FAIL; + + if (!_cfg_wow_wake(a, wow_en)) + return _FAIL; + + if(!_cfg_wow_gpio(a)) + return _FAIL; + + return _SUCCESS; +} + +u8 rtw_hw_wow(struct _ADAPTER *a, u8 wow_en) +{ + struct dvobj_priv *d; + void *phl; + struct rtw_phl_stainfo_t *phl_sta; + enum rtw_phl_status status; + + + d = adapter_to_dvobj(a); + phl = GET_PHL_INFO(d); + + rtw_wow_lps_level_decide(a, _TRUE); + + + if (!_wow_cfg(a, wow_en)) + return _FAIL; + + phl_sta = rtw_phl_get_stainfo_by_addr(phl, a->phl_role, get_bssid(&a->mlmepriv)); + + if (wow_en) + status = rtw_phl_suspend(phl, phl_sta, wow_en); + else + status = rtw_phl_resume(phl, phl_sta, &wow_en); + + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s wow %s fail(status: %d)\n", __func__, wow_en ? "enable" : "disable", status); + return _FAIL; + } + + return _SUCCESS; +} +#endif + +static enum rtw_edcca_mode rtw_edcca_mode_to_phl(enum rtw_edcca_mode_t mode) +{ + switch (mode) { + case RTW_EDCCA_NORM: + return RTW_EDCCA_NORMAL; + case RTW_EDCCA_ADAPT: + return RTW_EDCCA_ETSI; + case RTW_EDCCA_CS: + return RTW_EDCCA_JP; + default: + return RTW_EDCCA_MAX; + } +} + +void rtw_update_phl_edcca_mode(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + void *phl = GET_PHL_INFO(d); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(d); + struct rtw_chan_def chdef; + enum band_type band; + u8 mode = RTW_EDCCA_NORM; + enum rtw_edcca_mode phl_mode = rtw_edcca_mode_to_phl(mode); + + if (!a->phl_role) + goto exit; + + if (rtw_phl_mr_get_chandef(phl, a->phl_role, &chdef) != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s get union chandef failed\n", __func__); + rtw_warn_on(1); + goto exit; + } + + if (chdef.chan != 0 && rtw_mi_check_fwstate(a, WIFI_ASOC_STATE)) { + band = chdef.band; + rfctl->last_edcca_mode_op_band = band; + } else if (rfctl->last_edcca_mode_op_band != BAND_MAX) + band = rfctl->last_edcca_mode_op_band; + else { + rtw_phl_get_cur_hal_chdef(a->phl_role, &chdef); + band = chdef.band; + } + + mode = rtw_get_edcca_mode(d, band); + /* + * may get band not existing in current channel plan + * then edcca mode RTW_EDCCA_MODE_NUM is got + * this is not a real problem because this band is not used for TX + * change to RTW_EDCCA_NORM to avoid warning calltrace below + */ + if (mode == RTW_EDCCA_MODE_NUM) + mode = RTW_EDCCA_NORM; + + phl_mode = rtw_edcca_mode_to_phl(mode); + if (phl_mode == RTW_EDCCA_MAX) { + RTW_WARN("%s can't get valid phl mode from %s(%d)\n", __func__, rtw_edcca_mode_str(mode), mode); + rtw_warn_on(1); + return; + } + +exit: + if (rtw_phl_get_edcca_mode(phl) != phl_mode) + rtw_phl_set_edcca_mode(phl, phl_mode); +} + +void rtw_dump_phl_tx_power_ext_info(void *sel, _adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + void *phl_info = GET_PHL_INFO(dvobj); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + u8 band_idx; + + if (!adapter->phl_role) + return; + + band_idx = adapter->phl_role->hw_band; + + RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n" + , phl_com->dev_cap.pwrbyrate_off == RTW_PW_BY_RATE_ON ? "enabled" : "disabled" + , phl_com->dev_cap.pwrbyrate_off == RTW_PW_BY_RATE_ON ? "loaded" : "unloaded" + , phl_com->phy_sw_cap[0].rf_txpwr_byrate_info.para_src == RTW_PARA_SRC_EXTNAL ? "file" : "default" + ); + + RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n" + , rtw_phl_get_pwr_lmt_en(phl_info, band_idx) ? "enabled" : "disabled" + , rtw_phl_get_pwr_lmt_en(phl_info, band_idx) ? "loaded" : "unloaded" + , phl_com->phy_sw_cap[0].rf_txpwrlmt_info.para_src == RTW_PARA_SRC_EXTNAL ? "file" : "default" + ); + + RTW_PRINT_SEL(sel, "tx_power_limit_ru: %s, %s, %s\n" + , rtw_phl_get_pwr_lmt_en(phl_info, band_idx) ? "enabled" : "disabled" + , rtw_phl_get_pwr_lmt_en(phl_info, band_idx) ? "loaded" : "unloaded" + , phl_com->phy_sw_cap[0].rf_txpwrlmt_ru_info.para_src == RTW_PARA_SRC_EXTNAL ? "file" : "default" + ); +} + +void rtw_update_phl_txpwr_level(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + rtw_phl_set_tx_power(GET_PHL_INFO(dvobj), adapter->phl_role->hw_band); + rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), 0, 0); +} \ No newline at end of file diff --git a/core/rtw_phl_cmd.c b/core/rtw_phl_cmd.c new file mode 100644 index 0000000..a8748d6 --- /dev/null +++ b/core/rtw_phl_cmd.c @@ -0,0 +1,396 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include + +#if defined(CONFIG_CMD_GENERAL) || defined(CONFIG_STA_CMD_DISPR) || defined(CONFIG_CMD_TSF_SYNC) +#ifdef CONFIG_CMD_GENERAL/*for warkaround*/ +static void +phl_run_core_cmd(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)drv_priv; + struct cmd_obj *pcmd = (struct cmd_obj *)cmd; + _adapter *padapter = pcmd->padapter; + struct cmd_priv *pcmdpriv = &dvobj->cmdpriv; + + if (status == RTW_PHL_STATUS_CANNOT_IO || + status == RTW_PHL_STATUS_CMD_ERROR || + RTW_CANNOT_RUN(dvobj)) { + RTW_INFO(FUNC_ADPT_FMT "%s FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n" + , FUNC_ADPT_ARG(padapter) + , rtw_cmd_name(pcmd) + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False"); + + if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) { + struct drvextra_cmd_parm *extra_parm = + (struct drvextra_cmd_parm *)pcmd->parmbuf; + + if (extra_parm->pbuf && (extra_parm->size > 0)) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + + _rtw_mutex_lock(&pcmdpriv->sctx_mutex); + if (pcmd->sctx) { + if (0) + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP); + } + _rtw_mutex_unlock(&pcmdpriv->sctx_mutex); + rtw_free_cmd_obj(pcmd); + return; + } + + if (status == RTW_PHL_STATUS_CMD_TIMEOUT) + RTW_ERR("%s %s cmd timeout\n", __func__, rtw_cmd_name(pcmd)); + else if (status == RTW_PHL_STATUS_FAILURE) /*PHL fail due to 1. CMD_DROP:cmd abort or cancel 2.CMD_FAIL*/ + RTW_ERR("%s %s cmd failure\n", __func__, rtw_cmd_name(pcmd)); + + rtw_run_cmd(padapter, pcmd, false); +} +#endif /* CONFIG_CMD_GENERAL */ + +#ifdef CONFIG_STA_CMD_DISPR +static u32 _evt_joinbss_hdl(struct _ADAPTER *a, struct wlan_network *network) +{ + struct dvobj_priv *d; + u8 *mac; + struct sta_info *sta; + enum rtw_phl_status status; + u32 res = _FAIL; + + + d = adapter_to_dvobj(a); + mac = network->network.MacAddress; + sta = rtw_get_stainfo(&a->stapriv, mac); + if (!sta) { + RTW_ERR(FUNC_ADPT_FMT ": sta(" MAC_FMT ") not found!\n", + FUNC_ADPT_ARG(a), MAC_ARG(mac)); + goto disconnect; + } + + if (network->join_res < 0) + goto disconnect; + + status = rtw_phl_connect_linked(d->phl, a->phl_role, sta->phl_sta, mac); + if (status == RTW_PHL_STATUS_SUCCESS) + return _SUCCESS; + + RTW_ERR(FUNC_ADPT_FMT ": rtw_phl_connect_linked FAIL(%u)!\n", + FUNC_ADPT_ARG(a), status); + +disconnect: + RTW_INFO(FUNC_ADPT_FMT ": something may go wrong, run disconnect! " + "join_res=%d for " MAC_FMT "\n", + FUNC_ADPT_ARG(a), network->join_res, MAC_ARG(mac)); + + status = rtw_connect_disconnect_prepare(a); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR(FUNC_ADPT_FMT ": rtw_connect_disconnect_prepare FAIL(%u)!\n", + FUNC_ADPT_ARG(a), status); + goto exit; + } + res = _SUCCESS; + +exit: + return res; +} +#endif /* CONFIG_STA_CMD_DISPR */ + +#ifdef CONFIG_CMD_TSF_SYNC +enum rtw_phl_status rtw_send_tsf_sync_done_msg(struct _ADAPTER *a) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_wifi_role_t *role = a->phl_role; + enum rtw_phl_status status; + + + RTW_DBG(FUNC_ADPT_FMT ": +\n", FUNC_ADPT_ARG(a)); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_MRC); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_TSF_SYNC_DONE); + msg.band_idx = role->hw_band; + msg.inbuf = (u8 *)role; + + status = rtw_phl_send_msg_to_dispr(GET_PHL_INFO(d), + &msg, &attr, NULL); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR(FUNC_ADPT_FMT ": Send tsf sync done event fail(0x%02x)!\n", + FUNC_ADPT_ARG(a), status); + } + + return status; +} +#endif /* CONFIG_CMD_TSF_SYNC */ + +#ifdef CONFIG_PCIE_TRX_MIT +static void rtw_pcie_trx_mit_cb(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + /* cmd point to mit_info. */ + struct rtw_pcie_trx_mit_info_t *mit_info = (struct rtw_pcie_trx_mit_info_t *)cmd; + + RTW_DBG("%s: mit_info pointer=%p\n", __func__, mit_info); + rtw_mfree(mit_info, sizeof(struct rtw_pcie_trx_mit_info_t)); +} + +u8 rtw_pcie_trx_mit_cmd(_adapter *padapter, u32 tx_timer, u8 tx_counter, + u32 rx_timer, u8 rx_counter, u8 fixed_mit) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_pcie_trx_mit_info_t *mit_info; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + u8 res = _FAIL; + + mit_info = (struct rtw_pcie_trx_mit_info_t *)rtw_zmalloc(sizeof(struct rtw_pcie_trx_mit_info_t)); + if (mit_info == NULL) + goto exit; + + mit_info->tx_timer = tx_timer; + mit_info->tx_counter = tx_counter; + mit_info->rx_timer = rx_timer; + mit_info->rx_counter = rx_counter; + mit_info->fixed_mitigation = fixed_mit; + + RTW_DBG("%s: mit_info pointer=%p\n", __func__, mit_info); + + psts = rtw_phl_cmd_enqueue(dvobj->phl, + padapter->phl_role->hw_band, + MSG_EVT_PCIE_TRX_MIT, + (u8 *)mit_info, sizeof(mit_info), + rtw_pcie_trx_mit_cb, + PHL_CMD_NO_WAIT, 0); + + /* Send cmd fail */ + if (psts != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s: cmd failed!\n", __func__); + rtw_mfree(mit_info, sizeof(struct rtw_pcie_trx_mit_info_t)); + goto exit; + } + + res = _SUCCESS; + +exit: + return res; +} +#endif /* CONFIG_PCIE_TRX_MIT */ + +u32 rtw_enqueue_phl_cmd(struct cmd_obj *pcmd) +{ + u32 res = _FAIL; + _adapter *padapter = pcmd->padapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + + if (rtw_is_adapter_up(padapter) == _FALSE) + goto free_cmd; + +#if defined(CONFIG_STA_CMD_DISPR) || defined(CONFIG_CMD_TSF_SYNC) || defined(CONFIG_CMD_AP_DISPR) + switch (pcmd->cmdcode) { +#ifdef CONFIG_STA_CMD_DISPR + case CMD_JOINBSS: + { + struct _WLAN_BSSID_EX *network; + + network = (struct _WLAN_BSSID_EX*)pcmd->parmbuf; + psts = rtw_connect_cmd(padapter, network); + if (psts == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + /* pcmd & pcmd->parmbuf should be freed here */ + goto free_cmd; + } + + case CMD_DISCONNECT: + /* + * Disconnect for STA wouldn't come to here, + * because it would be handled in rtw_disassoc_cmd() directly. + */ + break; + + case CMD_SET_MLME_EVT: + { + struct rtw_evt_header *hdr; + struct wlan_network *network; + + hdr = (struct rtw_evt_header*)pcmd->parmbuf; + switch (hdr->id) { + case EVT_JOINBSS: + network = (struct wlan_network *)(pcmd->parmbuf + sizeof(*hdr)); + res = _evt_joinbss_hdl(padapter, network); + goto free_cmd; + + case EVT_DEL_STA: + if (MLME_IS_STA(padapter)) { + psts = rtw_disconnect_cmd(padapter, pcmd); + if (psts != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; + /* pcmd & pcmd->parmbuf would be freed in framework */ + res = _SUCCESS; + goto exit; + } + break; + + default: + break; + } + /* not handled event would be processed later */ + break; + } +#endif /* CONFIG_STA_CMD_DISPR */ +#ifdef CONFIG_AP_CMD_DISPR + case CMD_CREATE_BSS: + { + psts = rtw_ap_start_cmd(pcmd); + if (psts != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; + /* pcmd & pcmd->parmbuf should be freed here */ + res = _SUCCESS; + goto exit; + } +#endif /* CONFIG_AP_CMD_DISPR */ + + +#ifdef CONFIG_AP_CMD_DISPR + case CMD_SET_DRV_EXTRA: + { + struct drvextra_cmd_parm *parm; + + parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + if (parm->ec_id == STOP_AP_WK_CID) { + psts = rtw_ap_stop_cmd(pcmd); + if (psts != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; + res = _SUCCESS; + goto exit; + } + break; + } +#endif /* CONFIG_CMD_TSF_SYNC || CONFIG_AP_CMD_DISPR */ + + default: + break; + } +#endif /* CONFIG_STA_CMD_DISPR || CONFIG_CMD_TSF_SYNC || CONFIG_CMD_AP_DISPR */ + +#ifdef CONFIG_CMD_GENERAL + psts = rtw_phl_cmd_enqueue(dvobj->phl, + padapter->phl_role->hw_band, + MSG_EVT_LINUX_CMD_WRK, + (u8 *)pcmd, sizeof(struct cmd_obj), + phl_run_core_cmd, + PHL_CMD_NO_WAIT, 0); + /* Send cmd fail */ + if (psts != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; /* keep res == _FAIL */ +#endif /* CONFIG_CMD_GENERAL */ + + res = _SUCCESS; + goto exit; + +free_cmd: + if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) { + struct drvextra_cmd_parm *extra_parm = + (struct drvextra_cmd_parm *)pcmd->parmbuf; + + if (extra_parm->pbuf && (extra_parm->size > 0)) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + rtw_free_cmd_obj(pcmd); + +exit: + return res; +} + +#else /*CONFIG_FSM*/ +static void phl_run_core_cmd(void *priv, void *parm, bool discard) +{ + _adapter *padapter = (_adapter *)priv; + struct cmd_obj *pcmd = (struct cmd_obj *)parm; + + rtw_run_cmd(padapter, pcmd, discard); +} + +#define PHL_RES2RES(a) (a == RTW_PHL_STATUS_SUCCESS) ? _SUCCESS : _FAIL +u32 rtw_enqueue_phl_cmd(struct cmd_obj *pcmd) +{ + u32 res = RTW_PHL_STATUS_FAILURE; + _adapter *padapter = pcmd->padapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct phl_cmd_job job; + void *msg; + + _rtw_memset(&job, 0, sizeof(job)); + + switch (pcmd->cmdcode) { + #ifndef CONFIG_CMD_SCAN + case CMD_SITE_SURVEY: + { + res = rtw_site_survey_fsm(padapter, pcmd); + } + break; + #endif /*CONFIG_CMD_SCAN*/ + case CMD_SET_DRV_EXTRA: + { + struct drvextra_cmd_parm *parm; + + parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + + if ((parm->ec_id == MGNT_TX_WK_CID) && + (rtw_cfg80211_get_is_roch(padapter))) { + + rtw_phl_job_fill_fptr(dvobj->phl, &job, + phl_run_core_cmd, padapter, + pcmd, rtw_cmd_name(pcmd), + (pcmd->no_io) ? PWR_NO_IO : PWR_BASIC_IO); + + res = rtw_phl_scan_off_ch_tx( + dvobj->phl, &job, sizeof(job)); + + if (res != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; + + return PHL_RES2RES(res); + } + } + + /* fall through */ + default: + rtw_phl_job_fill_fptr(dvobj->phl, &job, + phl_run_core_cmd, padapter, + pcmd, rtw_cmd_name(pcmd), + (pcmd->no_io) ? PWR_NO_IO : PWR_BASIC_IO); + + res = phl_cmd_complete_job(dvobj->phl, &job); + if (res != RTW_PHL_STATUS_SUCCESS) + goto free_cmd; + + return PHL_RES2RES(res); + } + +free_cmd: + + if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) { + struct drvextra_cmd_parm *extra_parm = + (struct drvextra_cmd_parm *)pcmd->parmbuf; + + if (extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + rtw_free_cmd_obj(pcmd); + + return PHL_RES2RES(res); +} +#endif /*CONFIG_FSM*/ + diff --git a/core/rtw_pwrctrl.c b/core/rtw_pwrctrl.c index 03dfaf9..35eafd3 100644 --- a/core/rtw_pwrctrl.c +++ b/core/rtw_pwrctrl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,16 +15,31 @@ #define _RTW_PWRCTRL_C_ #include -#include -#include +#ifdef CONFIG_RTW_IPS +bool rtw_core_set_ips_state(void *drv_priv, enum rtw_rf_state state) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)drv_priv; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + + if (state == RTW_RF_ON) { + pstatus = rtw_phl_rf_on(dvobj->phl); + } else if (state == RTW_RF_OFF) { + pstatus = rtw_phl_rf_off(dvobj->phl); + } + if (RTW_PHL_STATUS_SUCCESS == pstatus) + return true; + else + return false; +} +#endif #ifdef DBG_CHECK_FW_PS_STATE -int rtw_fw_ps_state(PADAPTER padapter) +int rtw_fw_ps_state(_adapter *padapter) { struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; int ret = _FAIL, dont_care = 0; - u16 fw_ps_state = 0; + u8 ps_state = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct registry_priv *registry_par = &padapter->registrypriv; @@ -33,41 +48,20 @@ int rtw_fw_ps_state(PADAPTER padapter) _enter_pwrlock(&pwrpriv->check_32k_lock); - if (RTW_CANNOT_RUN(padapter)) { + if (RTW_CANNOT_RUN(psdpriv)) { RTW_INFO("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__ - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , rtw_get_hw_init_completed(padapter) - , rtw_is_drv_stopped(padapter) ? "True" : "False"); + , dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False" + , rtw_hw_get_init_completed(adapter_to_dvobj(padapter)) + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False"); goto exit_fw_ps_state; } - #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) - rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state); - if ((fw_ps_state & BIT_LPS_STATUS) == 0) + rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&ps_state); + if (ps_state == PS_ACTIVE) { ret = _SUCCESS; - else { + } else { pdbgpriv->dbg_poll_fail_cnt++; - RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state); + RTW_INFO("%s: fw_ps_state=%04x\n", __func__, ps_state); } - #else - rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care); - { - /* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */ - /* Else, hw will keep in active mode. */ - /* debug info: */ - /* 0x88[7] = 32kpermission, */ - /* 0x88[6:0] = current_ps_state */ - /* 0x89[7:0] = last_rpwm */ - - rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state); - - if ((fw_ps_state & 0x80) == 0) - ret = _SUCCESS; - else { - pdbgpriv->dbg_poll_fail_cnt++; - RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state); - } - } - #endif exit_fw_ps_state: _exit_pwrlock(&pwrpriv->check_32k_lock); @@ -109,11 +103,6 @@ void ips_enter(_adapter *padapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); -#endif /* CONFIG_BT_COEXIST */ - _enter_pwrlock(&pwrpriv->lock); _ips_enter(padapter); _exit_pwrlock(&pwrpriv->lock); @@ -143,8 +132,9 @@ int _ips_leave(_adapter *padapter) #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */ RTW_PRINT("nolinked power save leave\n"); - +#if 0 /*GEORGIA_TODO_REDEFINE_IO*/ RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); +#endif pwrpriv->bips_processing = _FALSE; pwrpriv->bkeepfwalive = _FALSE; @@ -179,24 +169,11 @@ int ips_leave(_adapter *padapter) #ifdef CONFIG_PCI_DYNAMIC_ASPM rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF); #endif - - if (_SUCCESS == ret) - odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv); - -#ifdef CONFIG_BT_COEXIST - if (_SUCCESS == ret) - rtw_btcoex_IpsNotify(padapter, IPS_NONE); -#endif /* CONFIG_BT_COEXIST */ - return ret; } #endif /* CONFIG_IPS */ -#ifdef SUPPORT_HW_RFOFF_DETECTED - int rtw_hw_suspend(_adapter *padapter); - int rtw_hw_resume(_adapter *padapter); -#endif - +#ifdef CONFIG_POWER_SAVING bool rtw_pwr_unassociated_idle(_adapter *adapter) { u8 i; @@ -207,6 +184,8 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo; #endif + u8 xmitbuf_nr = GET_HAL_XMITBUF_NR(dvobj); + u8 xmitbuf_ext_nr = GET_HAL_XMITBUF_EXT_NR(dvobj); bool ret = _FALSE; @@ -232,13 +211,10 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) || MLME_IS_AP(iface) || MLME_IS_MESH(iface) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) - #if defined(CONFIG_IOCTL_CFG80211) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) || rtw_cfg80211_get_is_roch(iface) == _TRUE || (rtw_cfg80211_is_ro_ch_once(adapter) && rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000) - #elif defined(CONFIG_P2P) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) #endif ) goto exit; @@ -251,8 +227,8 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) goto exit; #endif - if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF || - pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) { + if (pxmit_priv->free_xmitbuf_cnt != xmitbuf_nr || + pxmit_priv->free_xmit_extbuf_cnt != xmitbuf_ext_nr) { RTW_PRINT("There are some pkts to transmit\n"); RTW_PRINT("free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n", pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt); @@ -270,15 +246,13 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) * ATTENTION: * rtw_ps_processor() doesn't handle LPS. */ + void rtw_ps_processor(_adapter *padapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; -#ifdef SUPPORT_HW_RFOFF_DETECTED - rt_rf_power_state rfpwrstate; -#endif /* SUPPORT_HW_RFOFF_DETECTED */ u32 ps_deny = 0; _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock); @@ -300,32 +274,6 @@ void rtw_ps_processor(_adapter *padapter) pwrpriv->ps_processing = _TRUE; -#ifdef SUPPORT_HW_RFOFF_DETECTED - if (pwrpriv->bips_processing == _TRUE) - goto exit; - - /* RTW_INFO("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca)); */ - if (pwrpriv->bHWPwrPindetect) { - - rfpwrstate = RfOnOffDetect(padapter); - RTW_INFO("@@@@- #2 %s==> rfstate:%s\n", __FUNCTION__, (rfpwrstate == rf_on) ? "rf_on" : "rf_off"); - - if (rfpwrstate != pwrpriv->rf_pwrstate) { - if (rfpwrstate == rf_off) { - pwrpriv->change_rfpwrstate = rf_off; - pwrpriv->brfoffbyhw = _TRUE; - rtw_hw_suspend(padapter); - } else { - pwrpriv->change_rfpwrstate = rf_on; - rtw_hw_resume(padapter); - } - RTW_INFO("current rf_pwrstate(%s)\n", (pwrpriv->rf_pwrstate == rf_off) ? "rf_off" : "rf_on"); - } - - pwrpriv->pwr_state_check_cnts++; - } -#endif /* SUPPORT_HW_RFOFF_DETECTED */ - if (pwrpriv->ips_mode_req == IPS_NONE) goto exit; @@ -334,7 +282,7 @@ void rtw_ps_processor(_adapter *padapter) if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) { RTW_INFO("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv)); - pwrpriv->change_rfpwrstate = rf_off; + pwrpriv->change_rfpwrstate = rf_off; #ifdef CONFIG_IPS ips_enter(padapter); @@ -348,17 +296,18 @@ void rtw_ps_processor(_adapter *padapter) pwrpriv->ps_processing = _FALSE; return; } - +#endif +#ifdef CONFIG_POWER_SAVING void pwr_state_check_handler(void *ctx) { _adapter *padapter = (_adapter *)ctx; rtw_ps_cmd(padapter); } - +#endif #ifdef CONFIG_LPS #ifdef CONFIG_CHECK_LEAVE_LPS #ifdef CONFIG_LPS_CHK_BY_TP -void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta) +void traffic_check_for_leave_lps_by_tp(_adapter *padapter, u8 tx, struct sta_info *sta) { struct stainfo_stats *pstats = &sta->sta_stats; u64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0; @@ -375,10 +324,7 @@ void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info if (tx_tp_kbyte >= tx_tp_th || padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){ if (pwrpriv->bLeisurePs - && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) - #ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) - #endif + && (pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) ) { leave_lps = _TRUE; } @@ -392,10 +338,7 @@ void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info if (rx_tp_kbyte>= rx_tp_th || padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) { if (pwrpriv->bLeisurePs - && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) - #ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) - #endif + && (pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) ) { leave_lps = _TRUE; } @@ -417,7 +360,7 @@ void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info } #endif /*CONFIG_LPS_CHK_BY_TP*/ -void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) +void traffic_check_for_leave_lps(_adapter *padapter, u8 tx, u32 tx_packets) { static systime start_time = 0; static u32 xmit_cnt = 0; @@ -435,10 +378,7 @@ void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) if (rtw_get_passing_time_ms(start_time) > 2000) { /* 2 sec == watch dog timer */ if (xmit_cnt > 8) { if ((adapter_to_pwrctl(padapter)->bLeisurePs) - && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE) -#ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) -#endif + && (adapter_to_pwrctl(padapter)->pwr_mode != PM_PS_MODE_ACTIVE) ) { /* RTW_INFO("leave lps via Tx = %d\n", xmit_cnt); */ bLeaveLPS = _TRUE; @@ -452,10 +392,7 @@ void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) } else { /* from rx path */ if (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) { if ((adapter_to_pwrctl(padapter)->bLeisurePs) - && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE) -#ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) -#endif + && (adapter_to_pwrctl(padapter)->pwr_mode != PM_PS_MODE_ACTIVE) ) { /* RTW_INFO("leave lps via Rx = %d\n", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); */ bLeaveLPS = _TRUE; @@ -499,7 +436,7 @@ u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig) rst = _SUCCESS; break; } - } while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter)); + } while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter_to_dvobj(adapter))); if (rst == _SUCCESS) break; @@ -511,7 +448,7 @@ u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig) rtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); pwrpriv->tog += 0x80; } - } while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter)); + } while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter_to_dvobj(adapter))); if (rst == _SUCCESS) { #ifdef DBG_CHECK_FW_PS_STATE @@ -549,13 +486,14 @@ u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig) * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 * */ -u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv) +u8 rtw_set_rpwm(_adapter *padapter, u8 pslv) { u8 rpwm = 0xFF; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); #ifdef CONFIG_LPS_LCLK u8 cpwm_orig; #endif + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); pslv = PS_STATE(pslv); @@ -575,15 +513,15 @@ u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv) } } - if (rtw_is_surprise_removed(padapter) || - (!rtw_is_hw_init_completed(padapter))) { + if (dev_is_surprise_removed(dvobj) || + (!rtw_hw_is_init_completed(dvobj))) { pwrpriv->cpwm = PS_STATE_S4; return rpwm; } - if (rtw_is_drv_stopped(padapter)) + if (dev_is_drv_stopped(dvobj)) if (pslv < PS_STATE_S2) return rpwm; @@ -665,7 +603,7 @@ u8 PS_RDY_CHECK(_adapter *padapter) || MLME_IS_MESH(padapter) || MLME_IS_MONITOR(padapter) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) - #if defined(CONFIG_IOCTL_CFG80211) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) || rtw_cfg80211_get_is_roch(padapter) == _TRUE #endif || rtw_is_scan_deny(padapter) @@ -692,245 +630,24 @@ u8 PS_RDY_CHECK(_adapter *padapter) return _TRUE; } -#if defined(CONFIG_FWLPS_IN_IPS) -void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) -{ - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - int cnt = 0; - systime start_time; - u8 val8 = 0; - u8 cpwm_orig = 0, cpwm_now = 0; - u8 parm[H2C_INACTIVE_PS_LEN] = {0}; - - if (padapter->netif_up == _FALSE) { - RTW_INFO("%s: ERROR, netif is down\n", __func__); - return; - } - - /* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */ - if (enable) { -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); -#endif - /* Enter IPS */ - RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__); - - parm[0] = 0x1;/* suggest by Isaac.Hsu*/ -#ifdef CONFIG_PNO_SUPPORT - if (pwrpriv->pno_inited) { - parm[1] = pwrpriv->pnlo_info->fast_scan_iterations; - parm[2] = pwrpriv->pnlo_info->slow_scan_period; - } -#endif - - rtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */ - H2C_INACTIVE_PS_, - H2C_INACTIVE_PS_LEN, parm); - /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */ - do { - val8 = rtw_read8(padapter, REG_HMETFR); - cnt++; - RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", - __func__, val8, cnt); - rtw_mdelay_os(10); - } while (cnt < 100 && (val8 != 0)); - -#ifdef CONFIG_LPS_LCLK - /* H2C done, enter 32k */ - if (val8 == 0) { - /* ser rpwm to enter 32k */ - rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8); - RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8); - val8 += 0x80; - val8 |= BIT(0); - rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8)); - RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8); - adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; - cnt = val8 = 0; - if (parm[1] == 0 || parm[2] == 0) { - do { - val8 = rtw_read8(padapter, REG_CR); - cnt++; - RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", - __func__, val8, cnt); - RTW_INFO("%s 0x08:%02x, 0x03:%02x\n", - __func__, - rtw_read8(padapter, 0x08), - rtw_read8(padapter, 0x03)); - rtw_mdelay_os(10); - } while (cnt < 20 && (val8 != 0xEA)); - } - } -#endif - } else { - /* Leave IPS */ - RTW_INFO("%s: Leaving IPS in FWLPS state\n", __func__); - -#ifdef CONFIG_LPS_LCLK - /* for polling cpwm */ - cpwm_orig = 0; - rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); - - /* ser rpwm */ - rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8); - val8 += 0x80; - val8 |= BIT(6); - rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8)); - RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8); - adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; - - /* do polling cpwm */ - start_time = rtw_get_current_time(); - do { - - rtw_mdelay_os(1); - - rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); - if ((cpwm_orig ^ cpwm_now) & 0x80) - break; - - if (rtw_get_passing_time_ms(start_time) > 100) { - RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__); - break; - } - } while (1); - -#endif - parm[0] = 0x0; - parm[1] = 0x0; - parm[2] = 0x0; - rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_, - H2C_INACTIVE_PS_LEN, parm); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_IpsNotify(padapter, IPS_NONE); -#endif - } -} -#endif /* CONFIG_PNO_SUPPORT */ - -void rtw_exec_lps(_adapter *padapter, u8 ps_mode) -{ - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - - if (ps_mode == PS_MODE_ACTIVE) { -#ifdef CONFIG_LPS_ACK - _enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL); - rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100); -#endif /* CONFIG_LPS_ACK */ - - rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); - rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode)); - -#ifdef CONFIG_LPS_ACK - _exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL); -#endif /* CONFIG_LPS_ACK */ - } else { - if (MLME_IS_ASOC(padapter)) - rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); - else - RTW_INFO(FUNC_ADPT_FMT": It can't execute LPS without Wi-Fi connection!\n", - FUNC_ADPT_ARG(padapter)); - } -} - -void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl) +void rtw_leave_lps_and_chk(_adapter *padapter, u8 ps_mode) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 rpwm = 0; - - if (pwrpriv->bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE) { - if (rfon_ctrl == rf_on) { -#ifdef CONFIG_LPS_LCLK - if (pwrpriv->lps_level >= LPS_LCLK) { - s32 ready = _FAIL; - systime stime; - s32 utime; - u32 timeout; /* unit: ms */ - -#ifdef LPS_RPWM_WAIT_MS - timeout = LPS_RPWM_WAIT_MS; -#else - timeout = 30; -#endif /* !LPS_RPWM_WAIT_MS */ - - stime = rtw_get_current_time(); - do { - ready = rtw_register_task_alive(padapter, LPS_ALIVE); - if (ready == _SUCCESS) - break; - - utime = rtw_get_passing_time_ms(stime); - if (utime > timeout) - break; - - rtw_msleep_os(1); - } while (1); - - if (ready == _FAIL) - RTW_INFO(FUNC_ADPT_FMT": It is not ready to leave 32K !!!\n", - FUNC_ADPT_ARG(padapter)); - } -#endif /* CONFIG_LPS_LCLK */ #ifdef CONFIG_LPS_ACK - _enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL); + _rtw_mutex_lock_interruptible(&pwrpriv->lps_ack_mutex); rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100); #endif /* CONFIG_LPS_ACK */ - - rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl)); - rtw_hal_set_hwreg(padapter, HW_VAR_LPS_RFON_CHK, (u8 *)(&rfon_ctrl)); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode)); #ifdef CONFIG_LPS_ACK - _exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL); + _rtw_mutex_unlock(&pwrpriv->lps_ack_mutex); #endif /* CONFIG_LPS_ACK */ - } else { - if (MLME_IS_ASOC(padapter)) { -#ifdef CONFIG_LPS_PG - if (pwrpriv->lps_level == LPS_PG) { - if (rtw_hal_set_lps_pg_info_cmd(padapter) == _FAIL) - RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n", - FUNC_ADPT_ARG(padapter)); - } -#endif /* CONFIG_LPS_PG */ - rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl)); - } else { - RTW_INFO(FUNC_ADPT_FMT": It can't execute RFON without Wi-Fi connection!\n", - FUNC_ADPT_ARG(padapter)); - } -#ifdef CONFIG_LPS_LCLK - if (pwrpriv->lps_level >= LPS_LCLK) { - rtw_unregister_task_alive(padapter, LPS_ALIVE); - - if (pwrpriv->alives == 0) { - u8 polling_cnt = 0; - u8 reg_val8 = 0; - u8 result = _FAIL; - - do { - rtw_msleep_os(1); - reg_val8 = rtw_read8(padapter, REG_CR); - if (reg_val8 == 0xEA) { - result= _SUCCESS; - break; - } - polling_cnt++; - } while (polling_cnt < 100); - - if (result == _FAIL ) - RTW_INFO(FUNC_ADPT_FMT": It is not finished to enter 32K !!!\n", - FUNC_ADPT_ARG(padapter)); - } - } -#endif /* CONFIG_LPS_LCLK */ - } - } else { - RTW_INFO(FUNC_ADPT_FMT": RFON can't work due to ps state is not in LPS !\n", - FUNC_ADPT_ARG(padapter)); - } } -void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg) +void rtw_set_ps_mode(_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -946,7 +663,6 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode #endif /* CONFIG_P2P */ #ifdef CONFIG_TDLS struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; int i, j; _list *plist, *phead; struct sta_info *ptdls_sta; @@ -957,33 +673,33 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode - if (ps_mode > PM_Card_Disable) { + if (ps_mode > PM_CARD_DISABLE) { return; } if (pwrpriv->pwr_mode == ps_mode) { - if (PS_MODE_ACTIVE == ps_mode) + if (PM_PS_MODE_ACTIVE == ps_mode) return; -#ifndef CONFIG_BT_COEXIST +#ifndef CONFIG_BTC #ifdef CONFIG_WMMPS_STA if (!rtw_is_wmmps_mode(padapter)) #endif /* CONFIG_WMMPS_STA */ if ((pwrpriv->smart_ps == smart_ps) && (pwrpriv->bcn_ant_mode == bcn_ant_mode)) return; -#endif /* !CONFIG_BT_COEXIST */ +#endif /* !CONFIG_BTC */ } #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - if (PS_MODE_ACTIVE != ps_mode) { + if (PM_PS_MODE_ACTIVE != ps_mode) { rtw_set_ps_rsvd_page(padapter); rtw_set_default_port_id(padapter); } #endif #ifdef CONFIG_LPS_PG - if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->lps_level == LPS_PG)) { + if ((PM_PS_MODE_ACTIVE != ps_mode) && (pwrpriv->lps_level == LPS_PG)) { if (pwrpriv->wowlan_mode != _TRUE) { /*rtw_hal_set_lps_pg_info(padapter);*/ lps_pg_hdl_id = LPS_PG_INFO_CFG; @@ -996,23 +712,12 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode _enter_pwrlock(&pwrpriv->lock); #endif - /* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */ - if (ps_mode == PS_MODE_ACTIVE) { + /* if(pwrpriv->pwr_mode == PM_PS_MODE_ACTIVE) */ + if (ps_mode == PM_PS_MODE_ACTIVE) { if (1 -#ifdef CONFIG_BT_COEXIST - && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE) #ifdef CONFIG_P2P_PS && (pwdinfo->opp_ps == 0) #endif /* CONFIG_P2P_PS */ - ) - || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) - && (rtw_btcoex_IsLpsOn(padapter) == _FALSE)) - ) -#else /* !CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P_PS - && (pwdinfo->opp_ps == 0) -#endif /* CONFIG_P2P_PS */ -#endif /* !CONFIG_BT_COEXIST */ ) { RTW_INFO(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n", FUNC_ADPT_ARG(padapter), msg); @@ -1030,7 +735,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->phl_sta->mac_addr, 0, 0, 0); plist = get_next(plist); } } @@ -1075,7 +780,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode)); #endif /* CONFIG_WOWLAN */ - rtw_exec_lps(padapter, ps_mode); + rtw_leave_lps_and_chk(padapter, ps_mode); #ifdef CONFIG_LPS_PG if (pwrpriv->lps_level == LPS_PG) { @@ -1084,23 +789,10 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode } #endif -#ifdef CONFIG_LPS_POFF - rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE, - (u8 *)(&ps_mode)); -#endif /*CONFIG_LPS_POFF*/ - pwrpriv->bFwCurrentInPSMode = _FALSE; - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_LpsNotify(padapter, ps_mode); -#endif /* CONFIG_BT_COEXIST */ } } else { if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) -#ifdef CONFIG_BT_COEXIST - || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) - && (rtw_btcoex_IsLpsOn(padapter) == _TRUE)) -#endif #ifdef CONFIG_P2P_WOWLAN || (_TRUE == pwrpriv->wowlan_p2p_mode) #endif /* CONFIG_P2P_WOWLAN */ @@ -1126,21 +818,12 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->phl_sta->mac_addr, 1, 0, 0); plist = get_next(plist); } } #endif /* CONFIG_TDLS */ -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_LpsNotify(padapter, ps_mode); -#endif /* CONFIG_BT_COEXIST */ - -#ifdef CONFIG_LPS_POFF - rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE, - (u8 *)(&ps_mode)); -#endif /*CONFIG_LPS_POFF*/ - pwrpriv->bFwCurrentInPSMode = _TRUE; pwrpriv->pwr_mode = ps_mode; pwrpriv->smart_ps = smart_ps; @@ -1156,8 +839,9 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps; #endif /* CONFIG_WMMPS_STA */ - rtw_exec_lps(padapter, ps_mode); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); #ifdef CONFIG_WOWLAN if (pwrpriv->wowlan_mode == _TRUE) rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode)); @@ -1175,18 +859,6 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode pslv = PS_STATE_S0; #endif /* CONFIG_LPS_LCLK */ -#ifdef CONFIG_BT_COEXIST - if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) - && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) { - u8 val8; - - val8 = rtw_btcoex_LpsVal(padapter); - if (val8 & BIT(4)) - pslv = PS_STATE_S2; - - } -#endif /* CONFIG_BT_COEXIST */ - rtw_set_rpwm(padapter, pslv); } } @@ -1203,7 +875,7 @@ const char * const LPS_CTRL_PHYDM = "LPS_CTRL_PHYDM"; * Description: * Enter the leisure power save mode. * */ -void LPS_Enter(PADAPTER padapter, const char *msg) +void LPS_Enter(_adapter *padapter, const char *msg) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); @@ -1214,11 +886,8 @@ void LPS_Enter(PADAPTER padapter, const char *msg) #endif /* RTW_INFO("+LeisurePSEnter\n"); */ - if (GET_HAL_DATA(padapter)->bFWReady == _FALSE) - return; - -#ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) +#if 0 /*GEORGIA_TODO_FIXIT*/ + if (GET_PHL_COM(dvobj)->fw_ready == _FALSE) return; #endif @@ -1243,13 +912,6 @@ void LPS_Enter(PADAPTER padapter, const char *msg) return; } -#ifdef CONFIG_CLIENT_PORT_CFG - if ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) || - get_clt_num(padapter) > MAX_CLIENT_PORT_NUM){ - RTW_ERR(ADPT_FMT" cannot get client port or clt num(%d) over than 4\n", ADPT_ARG(padapter), get_clt_num(padapter)); - return; - } -#endif #ifdef CONFIG_P2P_PS if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) { @@ -1260,7 +922,7 @@ void LPS_Enter(PADAPTER padapter, const char *msg) if (pwrpriv->bLeisurePs) { /* Idle for a while if we connect to AP a while ago. */ if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */ - if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + if (pwrpriv->pwr_mode == PM_PS_MODE_ACTIVE) { #ifdef CONFIG_WMMPS_STA if (rtw_is_wmmps_mode(padapter)) @@ -1293,7 +955,7 @@ void LPS_Enter(PADAPTER padapter, const char *msg) * Description: * Leave the leisure power save mode. * */ -void LPS_Leave(PADAPTER padapter, const char *msg) +void LPS_Leave(_adapter *padapter, const char *msg) { #define LPS_LEAVE_TIMEOUT_MS 100 @@ -1307,13 +969,8 @@ void LPS_Leave(PADAPTER padapter, const char *msg) /* RTW_INFO("+LeisurePSLeave\n"); */ -#ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) - return; -#endif - if (pwrpriv->bLeisurePs) { - if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + if (pwrpriv->pwr_mode != PM_PS_MODE_ACTIVE) { #ifdef CONFIG_PCI_DYNAMIC_ASPM if (msg != LPS_CTRL_PHYDM) rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF); @@ -1324,7 +981,7 @@ void LPS_Leave(PADAPTER padapter, const char *msg) #endif /* CONFIG_WMMPS_STA */ sprintf(buf, "WIFI-%s", msg); - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf); + rtw_set_ps_mode(padapter, PM_PS_MODE_ACTIVE, 0, 0, buf); #ifdef CONFIG_RTW_CFGVENDOR_LLSTATS pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); @@ -1343,34 +1000,14 @@ void LPS_Leave(PADAPTER padapter, const char *msg) } -#ifdef CONFIG_WOWLAN -void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - - if (wow_en) { - pwrpriv->lps_level_bk = pwrpriv->lps_level; - pwrpriv->lps_level = pwrpriv->wowlan_lps_level; - #ifdef CONFIG_LPS_1T1R - pwrpriv->lps_1t1r_bk = pwrpriv->lps_1t1r; - pwrpriv->lps_1t1r = pwrpriv->wowlan_lps_1t1r; - #endif - } else { - pwrpriv->lps_level = pwrpriv->lps_level_bk; - #ifdef CONFIG_LPS_1T1R - pwrpriv->lps_1t1r = pwrpriv->lps_1t1r_bk; - #endif - } -} -#endif /* CONFIG_WOWLAN */ #endif /* CONFIG_LPS */ -void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) +void LeaveAllPowerSaveModeDirect(_adapter *adapter) { - struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); - PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *pri_padapter = GET_PRIMARY_ADAPTER(adapter); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + #ifdef CONFIG_LPS_LCLK #ifndef CONFIG_DETECT_CPWM_BY_POLLING u8 cpwm_orig; @@ -1381,14 +1018,14 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) RTW_INFO("%s.....\n", __FUNCTION__); - if (rtw_is_surprise_removed(Adapter)) { - RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + if (dev_is_surprise_removed(adapter_to_dvobj(adapter))) { + RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(adapter)); return; } - if (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/ + if (rtw_mi_check_status(adapter, MI_LINKED)) { /*connect*/ - if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + if (pwrpriv->pwr_mode == PM_PS_MODE_ACTIVE) { RTW_INFO("%s: Driver Already Leave LPS\n", __FUNCTION__); return; } @@ -1398,13 +1035,13 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) #ifndef CONFIG_DETECT_CPWM_BY_POLLING cpwm_orig = 0; - rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig); + rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_orig); #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - rpwm = rtw_set_rpwm(Adapter, PS_STATE_S4); + rpwm = rtw_set_rpwm(adapter, PS_STATE_S4); #ifndef CONFIG_DETECT_CPWM_BY_POLLING if (rpwm != 0xFF && rpwm & PS_ACK) - rtw_cpwm_polling(Adapter, rpwm, cpwm_orig); + rtw_cpwm_polling(adapter, rpwm, cpwm_orig); #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ _exit_pwrlock(&pwrpriv->lock); @@ -1426,12 +1063,12 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) } else { if (pwrpriv->rf_pwrstate == rf_off) { -#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E) +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) #ifdef CONFIG_IPS if (_FALSE == ips_leave(pri_padapter)) RTW_INFO("======> ips_leave fail.............\n"); #endif -#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */ +#endif /* defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) */ } } @@ -1442,28 +1079,21 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) * Description: Leave all power save mode: LPS, FwLPS, IPS if needed. * Move code to function by tynli. 2010.03.26. * */ -void LeaveAllPowerSaveMode(PADAPTER Adapter) +void LeaveAllPowerSaveMode(_adapter *adapter) { - struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); u8 enqueue = 0; int i; - #ifndef CONFIG_NEW_NETDEV_HDL - if (_FALSE == Adapter->bup) { - RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n", - FUNC_ADPT_ARG(Adapter), Adapter->bup); - return; - } - #endif -/* RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(Adapter));*/ +/* RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(adapter));*/ - if (rtw_is_surprise_removed(Adapter)) { - RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + if (dev_is_surprise_removed(adapter_to_dvobj(adapter))) { + RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(adapter)); return; } - if (rtw_mi_get_assoc_if_num(Adapter)) { + if (rtw_mi_get_assoc_if_num(adapter)) { /* connect */ #ifdef CONFIG_LPS_LCLK enqueue = 1; @@ -1480,22 +1110,22 @@ void LeaveAllPowerSaveMode(PADAPTER Adapter) #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_LPS - rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue ? 0 : RTW_CMDF_DIRECTLY); + rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE, enqueue ? 0 : RTW_CMDF_DIRECTLY); #endif #ifdef CONFIG_LPS_LCLK - LPS_Leave_check(Adapter); + LPS_Leave_check(adapter); #endif } else { - if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) { - -#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E)) + if (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off) { + +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) #ifdef CONFIG_IPS - if (_FALSE == ips_leave(Adapter)) + if (_FALSE == ips_leave(adapter)) RTW_INFO("======> ips_leave fail.............\n"); #endif -#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */ - +#endif /* defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) */ + } } @@ -1503,15 +1133,13 @@ void LeaveAllPowerSaveMode(PADAPTER Adapter) #ifdef CONFIG_LPS_LCLK void LPS_Leave_check( - PADAPTER padapter) + _adapter *padapter) { - struct pwrctrl_priv *pwrpriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); systime start_time; u8 bReady; - - pwrpriv = adapter_to_pwrctl(padapter); - bReady = _FALSE; start_time = rtw_get_current_time(); @@ -1520,12 +1148,12 @@ void LPS_Leave_check( while (1) { _enter_pwrlock(&pwrpriv->lock); - if (rtw_is_surprise_removed(padapter) - || (!rtw_is_hw_init_completed(padapter)) + if (dev_is_surprise_removed(dvobj) + || (!rtw_hw_is_init_completed(dvobj)) #ifdef CONFIG_USB_HCI - || rtw_is_drv_stopped(padapter) + || dev_is_drv_stopped(dvobj) #endif - || (pwrpriv->pwr_mode == PS_MODE_ACTIVE) + || (pwrpriv->pwr_mode == PM_PS_MODE_ACTIVE) ) bReady = _TRUE; @@ -1551,7 +1179,7 @@ void LPS_Leave_check( * using to update cpwn of drv; and drv willl make a decision to up or down pwr level */ void cpwm_int_hdl( - PADAPTER padapter, + _adapter *padapter, struct reportpwrstate_parm *preportpwrstate) { struct pwrctrl_priv *pwrpriv; @@ -1559,7 +1187,7 @@ void cpwm_int_hdl( if (!padapter) goto exit; - if (RTW_CANNOT_RUN(padapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) goto exit; pwrpriv = adapter_to_pwrctl(padapter); @@ -1583,11 +1211,14 @@ void cpwm_int_hdl( pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE; if (pwrpriv->cpwm >= PS_STATE_S2) { + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ if (pwrpriv->alives & CMD_ALIVE) _rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema); - + #endif + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ if (pwrpriv->alives & XMIT_ALIVE) _rtw_up_sema(&padapter->xmitpriv.xmit_sema); + #endif } _exit_pwrlock(&pwrpriv->lock); @@ -1620,44 +1251,13 @@ static void dma_event_callback(struct work_struct *work) #ifdef CONFIG_LPS_RPWM_TIMER -#define DBG_CPWM_CHK_FAIL -#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) \ - || defined(CONFIG_RTL8723F)) -#define CPU_EXCEPTION_CODE 0xFAFAFAFA -static void rtw_cpwm_chk_fail_debug(_adapter *padapter) -{ - u32 cpu_state; - - cpu_state = rtw_read32(padapter, 0x10FC); - - RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state); - RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8)); - RTW_INFO("[PS-DBG] Reg_11F8 =0x%08x\n", rtw_read32(padapter, 0x11F8)); - RTW_INFO("[PS-DBG] Reg_4A4 =0x%08x\n", rtw_read32(padapter, 0x4A4)); - RTW_INFO("[PS-DBG] Reg_4A8 =0x%08x\n", rtw_read32(padapter, 0x4A8)); - - if (cpu_state == CPU_EXCEPTION_CODE) { - RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C)); - RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490)); - RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494)); - RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498)); - RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C)); - RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0)); - RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC)); - - RTW_INFO("[PS-DBG] Reg_008 =0x%08x\n", rtw_read32(padapter, 0x08)); - RTW_INFO("[PS-DBG] Reg_2F0 =0x%08x\n", rtw_read32(padapter, 0x2F0)); - RTW_INFO("[PS-DBG] Reg_2F4 =0x%08x\n", rtw_read32(padapter, 0x2F4)); - RTW_INFO("[PS-DBG] Reg_2F8 =0x%08x\n", rtw_read32(padapter, 0x2F8)); - RTW_INFO("[PS-DBG] Reg_2FC =0x%08x\n", rtw_read32(padapter, 0x2FC)); - - rtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072); - } -} +#if defined(DBG_CPWM_CHK_FAIL) +extern void rtw_cpwm_chk_fail_debug(_adapter *padapter, struct pwrctrl_priv *pwrpriv); #endif + static void rpwmtimeout_workitem_callback(struct work_struct *work) { - PADAPTER padapter; + _adapter *padapter; struct dvobj_priv *dvobj; struct pwrctrl_priv *pwrpriv; @@ -1669,7 +1269,7 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) if (!padapter) return; - if (RTW_CANNOT_RUN(padapter)) + if (RTW_CANNOT_RUN(dvobj)) return; _enter_pwrlock(&pwrpriv->lock); @@ -1691,13 +1291,17 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) pwrpriv->rpwm_retry = 0; _exit_pwrlock(&pwrpriv->lock); -#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) \ - || defined(CONFIG_RTL8723F)) - RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); - rtw_cpwm_chk_fail_debug(padapter); +#if defined(DBG_CPWM_CHK_FAIL) + rtw_cpwm_chk_fail_debug(padapter, pwrpriv); +#endif + +#if 0 /*GEORGIA_TODO_REDEFINE_IO*/ + if (rtw_read8(padapter, 0x100) != 0xEA) +#else + if (!rtw_hal_is_leave_ps(padapter)) #endif - if (rtw_read8(padapter, 0x100) != 0xEA) { + { #if 1 struct reportpwrstate_parm report; @@ -1730,16 +1334,16 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) */ static void pwr_rpwm_timeout_handler(void *FunctionContext) { - PADAPTER padapter; + _adapter *padapter; struct pwrctrl_priv *pwrpriv; - - padapter = (PADAPTER)FunctionContext; - pwrpriv = adapter_to_pwrctl(padapter); + padapter = (_adapter *)FunctionContext; if (!padapter) return; - if (RTW_CANNOT_RUN(padapter)) + pwrpriv = adapter_to_pwrctl(padapter); + + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) return; RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); @@ -1779,7 +1383,7 @@ __inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag * _SUCCESS hardware is ready for I/O * _FAIL can't I/O right now */ -s32 rtw_register_task_alive(PADAPTER padapter, u32 task) +s32 rtw_register_task_alive(_adapter *padapter, u32 task) { s32 res; struct pwrctrl_priv *pwrctrl; @@ -1827,7 +1431,7 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task) * Return Value: * none */ -void rtw_unregister_task_alive(PADAPTER padapter, u32 task) +void rtw_unregister_task_alive(_adapter *padapter, u32 task) { struct pwrctrl_priv *pwrctrl; u8 pslv; @@ -1836,23 +1440,11 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task) pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; -#ifdef CONFIG_BT_COEXIST - if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) - && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) { - u8 val8; - - val8 = rtw_btcoex_LpsVal(padapter); - if (val8 & BIT(4)) - pslv = PS_STATE_S2; - - } -#endif /* CONFIG_BT_COEXIST */ - _enter_pwrlock(&pwrctrl->lock); unregister_task_alive(pwrctrl, task); - if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + if ((pwrctrl->pwr_mode != PM_PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { if (pwrctrl->cpwm > pslv) { @@ -1878,7 +1470,7 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task) * _SUCCESS rtw_xmit_thread can write fifo/txcmd afterwards. * _FAIL rtw_xmit_thread can not do anything. */ -s32 rtw_register_tx_alive(PADAPTER padapter) +s32 rtw_register_tx_alive(_adapter *padapter) { s32 res; struct pwrctrl_priv *pwrctrl; @@ -1929,7 +1521,8 @@ s32 rtw_register_tx_alive(PADAPTER padapter) * _SUCCESS rtw_cmd_thread can issue cmds to firmware afterwards. * _FAIL rtw_cmd_thread can not do anything. */ -s32 rtw_register_cmd_alive(PADAPTER padapter) +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ +s32 rtw_register_cmd_alive(_adapter *padapter) { s32 res; struct pwrctrl_priv *pwrctrl; @@ -1966,7 +1559,7 @@ s32 rtw_register_cmd_alive(PADAPTER padapter) return res; } - +#endif /* * Caller: rx_isr * @@ -1976,7 +1569,7 @@ s32 rtw_register_cmd_alive(PADAPTER padapter) * _SUCCESS * _FAIL */ -s32 rtw_register_rx_alive(PADAPTER padapter) +s32 rtw_register_rx_alive(_adapter *padapter) { struct pwrctrl_priv *pwrctrl; @@ -1993,32 +1586,6 @@ s32 rtw_register_rx_alive(PADAPTER padapter) return _SUCCESS; } -/* - * Caller: evt_isr or evt_thread - * - * Calling Context: Dispatch/ISR or Passive - * - * Return Value: - * _SUCCESS - * _FAIL - */ -s32 rtw_register_evt_alive(PADAPTER padapter) -{ - struct pwrctrl_priv *pwrctrl; - - - pwrctrl = adapter_to_pwrctl(padapter); - - _enter_pwrlock(&pwrctrl->lock); - - register_task_alive(pwrctrl, EVT_ALIVE); - - _exit_pwrlock(&pwrctrl->lock); - - - return _SUCCESS; -} - /* * Caller: ISR * @@ -2026,7 +1593,7 @@ s32 rtw_register_evt_alive(PADAPTER padapter) * No more pkts for TX, * Then driver shall call this fun. to power down firmware again. */ -void rtw_unregister_tx_alive(PADAPTER padapter) +void rtw_unregister_tx_alive(_adapter *padapter) { struct pwrctrl_priv *pwrctrl; _adapter *iface; @@ -2037,18 +1604,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter) pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; -#ifdef CONFIG_BT_COEXIST - if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) - && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) { - u8 val8; - - val8 = rtw_btcoex_LpsVal(padapter); - if (val8 & BIT(4)) - pslv = PS_STATE_S2; - - } -#endif /* CONFIG_BT_COEXIST */ - #ifdef CONFIG_P2P_PS for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -2064,7 +1619,7 @@ void rtw_unregister_tx_alive(PADAPTER padapter) unregister_task_alive(pwrctrl, XMIT_ALIVE); - if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + if ((pwrctrl->pwr_mode != PM_PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { if (pwrctrl->cpwm > pslv) { @@ -2084,7 +1639,8 @@ void rtw_unregister_tx_alive(PADAPTER padapter) * and no more command to do, * then driver shall call this fun. to power down firmware again. */ -void rtw_unregister_cmd_alive(PADAPTER padapter) +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ +void rtw_unregister_cmd_alive(_adapter *padapter) { _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); @@ -2095,18 +1651,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; -#ifdef CONFIG_BT_COEXIST - if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) - && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) { - u8 val8; - - val8 = rtw_btcoex_LpsVal(padapter); - if (val8 & BIT(4)) - pslv = PS_STATE_S2; - - } -#endif /* CONFIG_BT_COEXIST */ - #ifdef CONFIG_P2P_PS for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -2123,7 +1667,7 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) unregister_task_alive(pwrctrl, CMD_ALIVE); - if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + if ((pwrctrl->pwr_mode != PM_PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { if (pwrctrl->cpwm > pslv) { @@ -2135,11 +1679,11 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) _exit_pwrlock(&pwrctrl->lock); } - +#endif /* * Caller: ISR */ -void rtw_unregister_rx_alive(PADAPTER padapter) +void rtw_unregister_rx_alive(_adapter *padapter) { struct pwrctrl_priv *pwrctrl; @@ -2151,20 +1695,6 @@ void rtw_unregister_rx_alive(PADAPTER padapter) unregister_task_alive(pwrctrl, RECV_ALIVE); - _exit_pwrlock(&pwrctrl->lock); - -} - -void rtw_unregister_evt_alive(PADAPTER padapter) -{ - struct pwrctrl_priv *pwrctrl; - - - pwrctrl = adapter_to_pwrctl(padapter); - - unregister_task_alive(pwrctrl, EVT_ALIVE); - - _exit_pwrlock(&pwrctrl->lock); } @@ -2174,7 +1704,7 @@ void rtw_unregister_evt_alive(PADAPTER padapter) static void resume_workitem_callback(struct work_struct *work); #endif /* CONFIG_RESUME_IN_WORKQUEUE */ -void rtw_init_pwrctrl_priv(PADAPTER padapter) +void rtw_init_pwrctrl_priv(_adapter *padapter) { #ifdef CONFIG_LPS_1T1R #define LPS_1T1R_FMT ", LPS_1T1R=%d" @@ -2185,12 +1715,6 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #endif struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); -#ifdef CONFIG_WOWLAN - struct registry_priv *registry_par = &padapter->registrypriv; -#endif -#ifdef CONFIG_GPIO_WAKEUP - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); -#endif #if defined(CONFIG_CONCURRENT_MODE) if (!is_primary_adapter(padapter)) @@ -2229,12 +1753,12 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->bkeepfwalive = _FALSE; pwrctrlpriv->LpsIdleCount = 0; - /* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */ + /* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PM_PS_MODE_MIN; */ if (padapter->registrypriv.mp_mode == 1) - pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ; + pwrctrlpriv->power_mgnt = PM_PS_MODE_ACTIVE ; else - pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */ - pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; + pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PM_PS_MODE_MIN; */ + pwrctrlpriv->bLeisurePs = (PM_PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; pwrctrlpriv->bFwCurrentInPSMode = _FALSE; pwrctrlpriv->lps_deny_time = rtw_get_current_time(); @@ -2242,7 +1766,7 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->rpwm = 0; pwrctrlpriv->cpwm = PS_STATE_S4; - pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE; + pwrctrlpriv->pwr_mode = PM_PS_MODE_ACTIVE; pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps; pwrctrlpriv->bcn_ant_mode = 0; pwrctrlpriv->dtim = 0; @@ -2265,7 +1789,7 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #ifdef CONFIG_LPS_RPWM_TIMER pwrctrlpriv->brpwmtimeout = _FALSE; _init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL); - rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter); + rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, pwr_rpwm_timeout_handler, padapter); #endif /* CONFIG_LPS_RPWM_TIMER */ #endif /* CONFIG_LPS_LCLK */ @@ -2276,114 +1800,15 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->lpspg_iqk_info.name = "LPSPG_IQK_INFO"; #endif #endif - - rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter); - - pwrctrlpriv->wowlan_mode = _FALSE; - pwrctrlpriv->wowlan_ap_mode = _FALSE; - pwrctrlpriv->wowlan_p2p_mode = _FALSE; - pwrctrlpriv->wowlan_in_resume = _FALSE; - pwrctrlpriv->wowlan_last_wake_reason = 0; +#ifdef CONFIG_POWER_SAVING + rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, pwr_state_check_handler, padapter); +#endif #ifdef CONFIG_RESUME_IN_WORKQUEUE _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL); pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue"); #endif /* CONFIG_RESUME_IN_WORKQUEUE */ -#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) - pwrctrlpriv->early_suspend.suspend = NULL; - rtw_register_early_suspend(pwrctrlpriv); -#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ - -#ifdef CONFIG_GPIO_WAKEUP - pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX; - /* set output low state in initial */ - pwrctrlpriv->wowlan_gpio_output_state = GPIO_OUTPUT_LOW; - /*default low active*/ - pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST; - pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV; - -#if (defined(CONFIG_RTL8192F) && defined(CONFIG_USB_HCI) && defined(CONFIG_BT_COEXIST)) - if (pHalData->EEPROMBluetoothCoexist == _TRUE) { - /* for 8725AU case */ - pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX_8725AU; - pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST_8725AU; - } -#endif -#ifdef CONFIG_RTW_ONE_PIN_GPIO - rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE); - rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index); -#else - #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE - if (pwrctrlpriv->is_high_active == 0) - rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index); - else - rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index, - GPIO_OUTPUT_LOW); - #else - rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index - , pwrctrlpriv->wowlan_gpio_output_state); - rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE); - RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in initial and %s_ACTIVE.\n", - __func__, pwrctrlpriv->wowlan_gpio_index, - pwrctrlpriv->wowlan_gpio_output_state ? "HIGH" : "LOW", - pwrctrlpriv->is_high_active ? "HIGI" : "LOW"); - #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ -#endif /* CONFIG_RTW_ONE_PIN_GPIO */ -#endif /* CONFIG_GPIO_WAKEUP */ - -#ifdef CONFIG_WOWLAN -#ifdef CONFIG_LPS_1T1R -#define WOW_LPS_1T1R_FMT ", WOW_LPS_1T1R=%d" -#define WOW_LPS_1T1R_ARG , pwrctrlpriv->wowlan_lps_1t1r -#else -#define WOW_LPS_1T1R_FMT "" -#define WOW_LPS_1T1R_ARG -#endif - - pwrctrlpriv->wowlan_power_mgmt = padapter->registrypriv.wow_power_mgnt; - pwrctrlpriv->wowlan_lps_level = padapter->registrypriv.wow_lps_level; -#ifdef CONFIG_LPS_1T1R - pwrctrlpriv->wowlan_lps_1t1r = padapter->registrypriv.wow_lps_1t1r; -#endif - - RTW_INFO("%s: WOW_LPS_mode=%d, WOW_LPS_level=%d"WOW_LPS_1T1R_FMT"\n", - __func__, pwrctrlpriv->wowlan_power_mgmt, pwrctrlpriv->wowlan_lps_level - WOW_LPS_1T1R_ARG - ); - - if (registry_par->wakeup_event & BIT(1)) - pwrctrlpriv->default_patterns_en = _TRUE; - else - pwrctrlpriv->default_patterns_en = _FALSE; - - rtw_wow_pattern_sw_reset(padapter); -#ifdef CONFIG_PNO_SUPPORT - pwrctrlpriv->pno_inited = _FALSE; - pwrctrlpriv->pnlo_info = NULL; - pwrctrlpriv->pscan_info = NULL; - pwrctrlpriv->pno_ssid_list = NULL; -#endif /* CONFIG_PNO_SUPPORT */ -#ifdef CONFIG_WOW_PATTERN_HW_CAM - _rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex); -#endif - -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - pwrctrlpriv->wowlan_keep_alive_ack_index = 0xFF; - pwrctrlpriv->wowlan_wake_pattern_index = 0xFF; -#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - pwrctrlpriv->wowlan_aoac_rpt_loc = 0; -#ifdef CONFIG_WAR_OFFLOAD -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) - rtw_wow_war_mdns_parms_reset(padapter, _TRUE); -#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */ -#endif /* CONFIG_WAR_OFFLOAD */ -#endif /* CONFIG_WOWLAN */ - -#ifdef CONFIG_LPS_POFF - rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0); -#endif - #ifdef CONFIG_LPS_ACK _rtw_mutex_init(&pwrctrlpriv->lps_ack_mutex); pwrctrlpriv->lps_ack_status = -1; @@ -2391,7 +1816,7 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) } -void rtw_free_pwrctrl_priv(PADAPTER adapter) +void rtw_free_pwrctrl_priv(_adapter *adapter) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); @@ -2411,10 +1836,6 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) } #endif -#ifdef CONFIG_LPS_POFF - rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0); -#endif - #ifdef CONFIG_LPS_LCLK _cancel_workitem_sync(&pwrctrlpriv->cpwm_event); _cancel_workitem_sync(&pwrctrlpriv->dma_event); @@ -2431,27 +1852,6 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) #endif #endif -#ifdef CONFIG_WOWLAN -#ifdef CONFIG_PNO_SUPPORT - if (pwrctrlpriv->pnlo_info != NULL) - printk("****** pnlo_info memory leak********\n"); - - if (pwrctrlpriv->pscan_info != NULL) - printk("****** pscan_info memory leak********\n"); - - if (pwrctrlpriv->pno_ssid_list != NULL) - printk("****** pno_ssid_list memory leak********\n"); -#endif -#ifdef CONFIG_WOW_PATTERN_HW_CAM - _rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex); -#endif - -#endif /* CONFIG_WOWLAN */ - -#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) - rtw_unregister_early_suspend(pwrctrlpriv); -#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ - _free_pwrlock(&pwrctrlpriv->lock); _free_pwrlock(&pwrctrlpriv->check_32k_lock); @@ -2561,7 +1961,7 @@ void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) #ifdef CONFIG_ANDROID_POWER #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - extern int rtw_resume_process(PADAPTER padapter); + extern int rtw_resume_process(_adapter *padapter); #endif static void rtw_early_suspend(android_early_suspend_t *h) { @@ -2611,14 +2011,6 @@ void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) } #endif /* CONFIG_ANDROID_POWER */ -u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val) -{ - u8 bResult = _TRUE; - rtw_hal_intf_ps_func(padapter, efunc_id, val); - - return bResult; -} - inline void rtw_set_ips_deny(_adapter *padapter, u32 ms) { @@ -2635,10 +2027,13 @@ inline void rtw_set_ips_deny(_adapter *padapter, u32 ms) int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) { + int ret = _SUCCESS; + +#ifdef CONFIG_POWER_SAVING struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); struct mlme_priv *pmlmepriv; - int ret = _SUCCESS; + systime start = rtw_get_current_time(); /*RTW_INFO(FUNC_ADPT_FMT "===>\n", FUNC_ADPT_ARG(padapter));*/ @@ -2700,7 +2095,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } if (rf_off == pwrpriv->rf_pwrstate) { - + #ifdef CONFIG_IPS RTW_INFO("%s call ips_leave....\n", __FUNCTION__); if (_FAIL == ips_leave(padapter)) { @@ -2709,19 +2104,19 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) goto exit; } #endif - + } /* TODO: the following checking need to be merged... */ - if (rtw_is_drv_stopped(padapter) - || !padapter->bup - || !rtw_is_hw_init_completed(padapter) + if (dev_is_drv_stopped(dvobj) + || !padapter->netif_up + || !rtw_hw_is_init_completed(dvobj) ) { - RTW_INFO("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n" + RTW_INFO("%s: bDriverStopped=%s, netif_up=%d, hw_init_completed=%u\n" , caller - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , padapter->bup - , rtw_get_hw_init_completed(padapter)); + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , padapter->netif_up + , rtw_hw_get_init_completed(dvobj)); ret = _FALSE; goto exit; } @@ -2730,8 +2125,8 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time)) pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); /*RTW_INFO(FUNC_ADPT_FMT "<===\n", FUNC_ADPT_ARG(padapter));*/ +#endif return ret; - } int rtw_pm_set_lps(_adapter *padapter, u8 mode) @@ -2739,14 +2134,14 @@ int rtw_pm_set_lps(_adapter *padapter, u8 mode) int ret = 0; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - if (mode < PS_MODE_NUM) { + if (mode < PM_PS_MODE_NUM) { if (pwrctrlpriv->power_mgnt != mode) { - if (PS_MODE_ACTIVE == mode) + if (PM_PS_MODE_ACTIVE == mode) LeaveAllPowerSaveMode(padapter); else pwrctrlpriv->LpsIdleCount = 2; pwrctrlpriv->power_mgnt = mode; - pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; + pwrctrlpriv->bLeisurePs = (PM_PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; } } else ret = -EINVAL; @@ -2794,47 +2189,6 @@ inline void rtw_set_lps_deny(_adapter *adapter, u32 ms) pwrpriv->lps_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms); } -#ifdef CONFIG_WOWLAN -int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode) -{ - int ret = 0; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - - if (mode < PS_MODE_NUM) { - if (pwrctrlpriv->wowlan_power_mgmt != mode) - pwrctrlpriv->wowlan_power_mgmt = mode; - } else - ret = -EINVAL; - - return ret; -} -int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level) -{ - int ret = 0; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - - if (level < LPS_LEVEL_MAX) - pwrctrlpriv->wowlan_lps_level = level; - else - ret = -EINVAL; - - return ret; -} - -#ifdef CONFIG_LPS_1T1R -int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en) -{ - int ret = 0; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - - en = en ? 1 : 0; - pwrctrlpriv->wowlan_lps_1t1r = en; - - return ret; -} -#endif /* CONFIG_LPS_1T1R */ -#endif /* CONFIG_WOWLAN */ - int rtw_pm_set_ips(_adapter *padapter, u8 mode) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -2846,7 +2200,7 @@ int rtw_pm_set_ips(_adapter *padapter, u8 mode) } else if (mode == IPS_NONE) { rtw_ips_mode_req(pwrctrlpriv, mode); RTW_INFO("%s %s\n", __FUNCTION__, "IPS_NONE"); - if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter))) + if (!dev_is_surprise_removed(adapter_to_dvobj(padapter)) && (_FAIL == rtw_pwr_wakeup(padapter))) return -EFAULT; } else return -EINVAL; @@ -2857,7 +2211,7 @@ int rtw_pm_set_ips(_adapter *padapter, u8 mode) * ATTENTION: * This function will request pwrctrl LOCK! */ -void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason) +void rtw_ps_deny(_adapter *padapter, PS_DENY_REASON reason) { struct pwrctrl_priv *pwrpriv; @@ -2882,7 +2236,7 @@ void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason) * ATTENTION: * This function will request pwrctrl LOCK! */ -void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason) +void rtw_ps_deny_cancel(_adapter *padapter, PS_DENY_REASON reason) { struct pwrctrl_priv *pwrpriv; @@ -2909,7 +2263,7 @@ void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason) * Before calling this function pwrctrl lock should be occupied already, * otherwise it may return incorrect value. */ -u32 rtw_ps_deny_get(PADAPTER padapter) +u32 rtw_ps_deny_get(_adapter *padapter) { u32 deny; @@ -2924,32 +2278,47 @@ static void _rtw_ssmps(_adapter *adapter, struct sta_info *sta) struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (MLME_IS_STA(adapter)) { - issue_action_SM_PS_wait_ack(adapter , get_my_bssid(&(pmlmeinfo->network)), - sta->cmn.sm_ps, 3 , 1); - } - else if (MLME_IS_AP(adapter)) { + issue_action_SM_PS_wait_ack(adapter , get_my_bssid(&(pmlmeinfo->network)), + sta->phl_sta->asoc_cap.sm_ps, 3 , 1); + if (sta->phl_sta->asoc_cap.sm_ps == SM_PS_STATIC) { + pmlmeext->txss_bk = sta->phl_sta->asoc_cap.nss_rx; + sta->phl_sta->asoc_cap.nss_rx = 1; + } else { + sta->phl_sta->asoc_cap.nss_rx = pmlmeext->txss_bk; } - rtw_phydm_ra_registed(adapter, sta); + + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(adapter)->phl, + sta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_DIRECTLY, + 0); } void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta) { - if (sta->cmn.sm_ps == SM_PS_STATIC) + if (MLME_IS_AP(adapter)) + return; + + if (sta->phl_sta->asoc_cap.sm_ps == SM_PS_STATIC) return; - RTW_INFO(ADPT_FMT" STA [" MAC_FMT "]\n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + RTW_INFO(ADPT_FMT" STA [" MAC_FMT "]\n", ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); - sta->cmn.sm_ps = SM_PS_STATIC; + sta->phl_sta->asoc_cap.sm_ps = SM_PS_STATIC; _rtw_ssmps(adapter, sta); } void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta) { - if (sta->cmn.sm_ps == SM_PS_DISABLE) + if (MLME_IS_AP(adapter)) + return; + + if (sta->phl_sta->asoc_cap.sm_ps == SM_PS_DISABLE) return; - RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] \n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); - sta->cmn.sm_ps = SM_PS_DISABLE; + RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] \n", ADPT_ARG(adapter), MAC_ARG(sta->phl_sta->mac_addr)); + sta->phl_sta->asoc_cap.sm_ps = SM_PS_DISABLE; _rtw_ssmps(adapter, sta); } diff --git a/core/rtw_recv.c b/core/rtw_recv.c index e524d6d..32ea4cb 100644 --- a/core/rtw_recv.c +++ b/core/rtw_recv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,30 +15,24 @@ #define _RTW_RECV_C_ #include -#include -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS static void rtw_signal_stat_timer_hdl(void *ctx); enum { SIGNAL_STAT_CALC_PROFILE_0 = 0, SIGNAL_STAT_CALC_PROFILE_1, - SIGNAL_STAT_CALC_PROFILE_2, SIGNAL_STAT_CALC_PROFILE_MAX }; -u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][3] = { +u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = { {4, 1}, /* Profile 0 => pre_stat : curr_stat = 4 : 1 */ - {3, 7}, /* Profile 1 => pre_stat : curr_stat = 3 : 7 */ - {0, 10} /* Profile 2 => pre_stat : curr_stat = 0 : 10 */ + {3, 7} /* Profile 1 => pre_stat : curr_stat = 3 : 7 */ }; #ifndef RTW_SIGNAL_STATE_CALC_PROFILE #define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1 #endif -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37}; @@ -50,8 +44,6 @@ static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d}; void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) { - - _rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv)); _rtw_spinlock_init(&psta_recvpriv->lock); @@ -64,43 +56,59 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) } -sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) +u8 rtw_init_recv_info(_adapter *adapter) { - sint i; + u8 ret = _SUCCESS; + struct recv_info *recvinfo = &adapter->recvinfo; - union recv_frame *precvframe; - sint res = _SUCCESS; + recvinfo->sink_udpport = 0; + recvinfo->pre_rtp_rxseq = 0; + recvinfo->cur_rtp_rxseq = 0; + #ifdef CONFIG_SIGNAL_STAT_PROCESS + rtw_init_timer(&recvinfo->signal_stat_timer, rtw_signal_stat_timer_hdl, adapter); + recvinfo->signal_stat_sampling_interval = 2000; /* ms */ + /* recvinfo->signal_stat_converging_constant = 5000; */ /* ms */ - /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ - /* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); */ + rtw_set_signal_stat_timer(recvinfo); + #endif + return ret; +} - _rtw_spinlock_init(&precvpriv->lock); +/*#define DBG_RECV_FRAME*/ +#ifdef DBG_RECV_FRAME +void _dump_recv_priv(struct dvobj_priv *dvobj, _queue *pfree_recv_queue) +{ + struct recv_priv *precvpriv = &dvobj->recvpriv; -#ifdef CONFIG_RECV_THREAD_MODE - _rtw_init_sema(&precvpriv->recv_sema, 0); + RTW_INFO("%s free_recvframe_cnt:%d\n", __func__, precvpriv->free_recvframe_cnt); + RTW_INFO("%s dvobj:%p pfree_recv_queue:%p : %p\n", + __func__, dvobj, &(precvpriv->free_recv_queue), pfree_recv_queue); +} #endif +sint rtw_init_recv_priv(struct dvobj_priv *dvobj) +{ + sint i; + union recv_frame *precvframe; + sint res = _SUCCESS; + struct recv_priv *precvpriv = &dvobj->recvpriv; + + #ifdef CONFIG_RECV_THREAD_MODE + _rtw_init_sema(&precvpriv->recv_sema, 0); + #endif + _rtw_init_queue(&precvpriv->free_recv_queue); - _rtw_init_queue(&precvpriv->recv_pending_queue); + #if 0 _rtw_init_queue(&precvpriv->uc_swdec_pending_queue); + #endif - precvpriv->adapter = padapter; + precvpriv->dvobj = dvobj; precvpriv->free_recvframe_cnt = NR_RECVFRAME; - precvpriv->sink_udpport = 0; - precvpriv->pre_rtp_rxseq = 0; - precvpriv->cur_rtp_rxseq = 0; - -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - precvpriv->store_law_data_flag = 1; -#else - precvpriv->store_law_data_flag = 0; -#endif - - rtw_os_recv_resource_init(precvpriv, padapter); + rtw_os_recv_resource_init(precvpriv); precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); @@ -122,137 +130,110 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue)); - rtw_os_recv_resource_alloc(padapter, precvframe); + rtw_os_recv_resource_alloc(precvframe); precvframe->u.hdr.len = 0; - precvframe->u.hdr.adapter = padapter; - precvframe++; + precvframe->u.hdr.dvobj = dvobj; + precvframe->u.hdr.adapter = NULL; + precvframe->u.hdr.rx_req = NULL; + precvframe++; } + #ifdef DBG_RECV_FRAME + RTW_INFO("%s =>precvpriv->free_recvframe_cnt:%d\n", __func__, precvpriv->free_recvframe_cnt); + #endif -#ifdef CONFIG_USB_HCI - - ATOMIC_SET(&(precvpriv->rx_pending_cnt), 1); - - _rtw_init_sema(&precvpriv->allrxreturnevt, 0); - -#endif - - res = rtw_hal_init_recv_priv(padapter); - -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter); - - precvpriv->signal_stat_sampling_interval = 2000; /* ms */ - /* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */ - - rtw_set_signal_stat_timer(precvpriv); -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - + res = rtw_intf_init_recv_priv(dvobj); + #ifdef DBG_RECV_FRAME + _dump_recv_priv(dvobj, &dvobj->recvpriv.free_recv_queue); + #endif exit: - - return res; } -void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv); -void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) +void rtw_free_recv_priv(struct dvobj_priv *dvobj) { - _rtw_spinlock_free(&precvpriv->lock); + struct recv_priv *precvpriv = &dvobj->recvpriv; + + #if 0 + rtw_free_uc_swdec_pending_queue(dvobj); + #endif + #ifdef CONFIG_RECV_THREAD_MODE _rtw_free_sema(&precvpriv->recv_sema); #endif - _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); - _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock); - - _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock); - -#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX - _rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock); -#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ -} - -void _rtw_free_recv_priv(struct recv_priv *precvpriv) -{ - _adapter *padapter = precvpriv->adapter; - - - rtw_free_uc_swdec_pending_queue(padapter); - - rtw_mfree_recv_priv_lock(precvpriv); - rtw_os_recv_resource_free(precvpriv); if (precvpriv->pallocated_frame_buf) rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); - rtw_hal_free_recv_priv(padapter); - - -} - -bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset) -{ -#define DBG_RFRAME_DEL_WFD_IE 0 - u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset; - uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data); - uint ies_len; - - ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL); - rframe->u.hdr.len -= ies_len_ori - ies_len; + _rtw_deinit_queue(&precvpriv->free_recv_queue); - return ies_len_ori != ies_len; + rtw_intf_free_recv_priv(dvobj); } union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue) { - union recv_frame *precvframe; _list *plist, *phead; - _adapter *padapter; struct recv_priv *precvpriv; + struct dvobj_priv *dvobj; + +#ifdef DBG_RECV_FRAME + RTW_INFO("%s =>pfree_recv_queue:%p\n", __func__, pfree_recv_queue); +#endif - if (_rtw_queue_empty(pfree_recv_queue) == _TRUE) + if (_rtw_queue_empty(pfree_recv_queue) == _TRUE) { precvframe = NULL; + } else { phead = get_list_head(pfree_recv_queue); plist = get_next(phead); precvframe = LIST_CONTAINOR(plist, union recv_frame, u); - rtw_list_delete(&precvframe->u.hdr.list); - padapter = precvframe->u.hdr.adapter; - if (padapter != NULL) { - precvpriv = &padapter->recvpriv; - if (pfree_recv_queue == &precvpriv->free_recv_queue) - precvpriv->free_recvframe_cnt--; - } + dvobj = precvframe->u.hdr.dvobj; + precvpriv = &dvobj->recvpriv; + precvpriv->free_recvframe_cnt--; } - return precvframe; } - union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue) { - _irqL irqL; - union recv_frame *precvframe; + union recv_frame *precvframe = NULL; + #ifdef DBG_RECV_FRAME + struct recv_priv *precvpriv; + struct dvobj_priv *dvobj; - _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + RTW_INFO("%s =>pfree_recv_queue:%p\n", __func__, pfree_recv_queue); + #endif + _rtw_spinlock_bh(&pfree_recv_queue->lock); precvframe = _rtw_alloc_recvframe(pfree_recv_queue); - _exit_critical_bh(&pfree_recv_queue->lock, &irqL); - + _rtw_spinunlock_bh(&pfree_recv_queue->lock); + + if(precvframe) { + precvframe->u.hdr.rx_req = NULL; + #ifdef DBG_RECV_FRAME + dvobj = precvframe->u.hdr.dvobj; + precvpriv = &dvobj->recvpriv; + RTW_INFO("%s =>dvobj:%p precvpriv->free_recvframe_cnt:%d\n", + __func__, + dvobj, + precvpriv->free_recvframe_cnt); + #endif + } return precvframe; } -void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv) +void rtw_init_recvframe(union recv_frame *precvframe) { /* Perry: This can be removed */ _rtw_init_listhead(&precvframe->u.hdr.list); @@ -260,48 +241,65 @@ void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpri precvframe->u.hdr.len = 0; } -int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) +int rtw_free_recvframe(union recv_frame *precvframe) { - _irqL irqL; - _adapter *padapter = precvframe->u.hdr.adapter; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct dvobj_priv *dvobj; + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + if(!precvframe) { + RTW_ERR("%s precvframe is NULL\n", __func__); + rtw_warn_on(1); + return _FAIL; + } -#ifdef CONFIG_CONCURRENT_MODE - padapter = GET_PRIMARY_ADAPTER(padapter); - precvpriv = &padapter->recvpriv; - pfree_recv_queue = &precvpriv->free_recv_queue; - precvframe->u.hdr.adapter = padapter; + dvobj = precvframe->u.hdr.dvobj; + precvpriv = &dvobj->recvpriv; + pfree_recv_queue = &(precvpriv->free_recv_queue); +#ifdef DBG_RECV_FRAME + RTW_INFO("%s dvobj:%p, phl:%p\n", __func__,dvobj, dvobj->phl); #endif +#ifdef RTW_PHL_RX + if(precvframe->u.hdr.rx_req) + rtw_phl_return_rxbuf(GET_PHL_INFO(dvobj), (u8*)precvframe->u.hdr.rx_req); +#endif rtw_os_free_recvframe(precvframe); - - _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + _rtw_spinlock_bh(&pfree_recv_queue->lock); rtw_list_delete(&(precvframe->u.hdr.list)); precvframe->u.hdr.len = 0; - precvframe->u.hdr.attrib.phy_info.physts_rpt_valid = _FALSE; rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue)); + precvpriv->free_recvframe_cnt++; - if (padapter != NULL) { - if (pfree_recv_queue == &precvpriv->free_recv_queue) - precvpriv->free_recvframe_cnt++; - } - - _exit_critical_bh(&pfree_recv_queue->lock, &irqL); - + _rtw_spinunlock_bh(&pfree_recv_queue->lock); +#ifdef DBG_RECV_FRAME + RTW_INFO("%s =>precvpriv->free_recvframe_cnt:%d\n", __func__, precvpriv->free_recvframe_cnt); +#endif return _SUCCESS; } +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset) +{ +#define DBG_RFRAME_DEL_WFD_IE 0 + u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset; + uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL); + rframe->u.hdr.len -= ies_len_ori - ies_len; + return ies_len_ori != ies_len; +} +#if 0 sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) { @@ -327,26 +325,16 @@ sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) { sint ret; - _irqL irqL; /* _spinlock(&pfree_recv_queue->lock); */ - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); ret = _rtw_enqueue_recvframe(precvframe, queue); /* _rtw_spinunlock(&pfree_recv_queue->lock); */ - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); return ret; } - -/* -sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) -{ - return rtw_free_recvframe(precvframe, queue); -} -*/ - - - +#endif /* caller : defrag ; recvframe_chk_defrag in recv_thread (passive) @@ -356,7 +344,7 @@ using spinlock to protect */ -void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) +void rtw_free_recvframe_queue(_queue *pframequeue) { union recv_frame *precvframe; _list *plist, *phead; @@ -373,7 +361,7 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) /* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */ - rtw_free_recvframe(precvframe, pfree_recv_queue); + rtw_free_recvframe(precvframe); } _rtw_spinunlock(&pframequeue->lock); @@ -381,112 +369,23 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) } -u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter) +#if 0 +u32 rtw_free_uc_swdec_pending_queue(struct dvobj_priv *dvobj) { u32 cnt = 0; union recv_frame *pending_frame; - while ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) { - rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue); + while ((pending_frame = rtw_alloc_recvframe(&dvobj->recvpriv.uc_swdec_pending_queue))) { + rtw_free_recvframe(pending_frame); cnt++; } if (cnt) - RTW_INFO(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt); + RTW_INFO("dequeue %d\n", cnt); return cnt; } - - -#ifndef CONFIG_RECVBUF_QUEUE_LOCK_BH -#ifdef CONFIG_SDIO_HCI -#define CONFIG_RECVBUF_QUEUE_LOCK_BH 1 -#else -#define CONFIG_RECVBUF_QUEUE_LOCK_BH 0 -#endif -#endif /* CONFIG_RECVBUF_QUEUE_LOCK_BH */ - -sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue) -{ - _irqL irqL; - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _enter_critical_bh(&queue->lock, &irqL); -#else - _enter_critical_ex(&queue->lock, &irqL); -#endif - - rtw_list_delete(&precvbuf->list); - rtw_list_insert_head(&precvbuf->list, get_list_head(queue)); - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _exit_critical_bh(&queue->lock, &irqL); -#else - _exit_critical_ex(&queue->lock, &irqL); -#endif - - return _SUCCESS; -} - -sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue) -{ - _irqL irqL; - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _enter_critical_bh(&queue->lock, &irqL); -#else - _enter_critical_ex(&queue->lock, &irqL); -#endif - - rtw_list_delete(&precvbuf->list); - - rtw_list_insert_tail(&precvbuf->list, get_list_head(queue)); - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _exit_critical_bh(&queue->lock, &irqL); -#else - _exit_critical_ex(&queue->lock, &irqL); -#endif - - return _SUCCESS; - -} - -struct recv_buf *rtw_dequeue_recvbuf(_queue *queue) -{ - _irqL irqL; - struct recv_buf *precvbuf; - _list *plist, *phead; - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _enter_critical_bh(&queue->lock, &irqL); -#else - _enter_critical_ex(&queue->lock, &irqL); -#endif - - if (_rtw_queue_empty(queue) == _TRUE) - precvbuf = NULL; - else { - phead = get_list_head(queue); - - plist = get_next(phead); - - precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list); - - rtw_list_delete(&precvbuf->list); - - } - -#if CONFIG_RECVBUF_QUEUE_LOCK_BH - _exit_critical_bh(&queue->lock, &irqL); -#else - _exit_critical_ex(&queue->lock, &irqL); #endif - return precvbuf; - -} - -sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe); sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) { @@ -589,14 +488,14 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) /*#define DBG_RX_SW_DECRYPTOR*/ /* decrypt and set the ivlen,icvlen of the recv_frame */ -union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame); union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) { struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; union recv_frame *return_packet = precv_frame; - u32 res = _SUCCESS; + struct sta_info *psta = precv_frame->u.hdr.psta; + u32 res = _SUCCESS; DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt); @@ -631,8 +530,12 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_CONCURRENT_MODE && !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */ #endif - ) - psecuritypriv->hw_decrypted = _FALSE; + ) { + if (IS_MCAST(prxattrib->ra)) + psecuritypriv->hw_decrypted = _FALSE; + else + psta->hw_decrypted = _FALSE; + } #ifdef DBG_RX_SW_DECRYPTOR RTW_INFO(ADPT_FMT" - sec_type:%s DO SW decryption\n", @@ -640,12 +543,13 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) #endif #ifdef DBG_RX_DECRYPTOR - RTW_INFO("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", + RTW_INFO("[%s] %d: PKT decrypted(%d), PKT encrypt(%d), Set %pM hw_decrypted(%d)\n", __FUNCTION__, __LINE__, prxattrib->bdecrypted, prxattrib->encrypt, - psecuritypriv->hw_decrypted); + psta->phl_sta->mac_addr, + psta->hw_decrypted); #endif switch (prxattrib->encrypt) { @@ -686,7 +590,7 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) psecuritypriv->hw_decrypted = _FALSE; - rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue); + rtw_free_recvframe(precv_frame); return_packet = NULL; @@ -696,25 +600,27 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw); psecuritypriv->hw_decrypted = _TRUE; + psta->hw_decrypted = _TRUE; #ifdef DBG_RX_DECRYPTOR - RTW_INFO("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", - __FUNCTION__, - __LINE__, - prxattrib->bdecrypted, - prxattrib->encrypt, - psecuritypriv->hw_decrypted); - + RTW_INFO("[%s] %d: PKT decrypted(%d), PKT encrypt(%d), Set %pM hw_decrypted(%d)\n", + __FUNCTION__, + __LINE__, + prxattrib->bdecrypted, + prxattrib->encrypt, + psta->phl_sta->mac_addr, + psta->hw_decrypted); #endif } } else { DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown); #ifdef DBG_RX_DECRYPTOR - RTW_INFO("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", + RTW_INFO("[%s] %d: PKT decrypted(%d), PKT encrypt(%d), Set %pM hw_decrypted(%d)\n", __FUNCTION__, __LINE__, prxattrib->bdecrypted, prxattrib->encrypt, - psecuritypriv->hw_decrypted); + psta->phl_sta->mac_addr, + psta->hw_decrypted); #endif } @@ -726,7 +632,9 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) #endif if (res == _FAIL) { - rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue); + /* Let rtw_core_rx_process or rtw_mi_buddy_clone_bcmc_packet */ + /* to handle it.*/ + /* rtw_free_recvframe(return_packet); */ return_packet = NULL; } else prxattrib->bdecrypted = _TRUE; @@ -736,8 +644,8 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) return return_packet; } + /* ###set the security information in the recv_frame */ -union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame); union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) { u8 *psta_addr = NULL; @@ -781,8 +689,8 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) if (ether_type == eapol_type) prtnframe = precv_frame; else { - /* free this frame */ - rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue); + /* Let rtw_core_rx_process to handle it */ + /* rtw_free_recvframe(precv_frame); */ prtnframe = NULL; } } else { @@ -814,8 +722,7 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) */ #define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0) #define VALID_PN_CHK(new, old) (((old) == 0) || PN_LESS_CHK(old, new)) -#define CCMPH_2_KEYID(ch) (((ch) & 0x00000000c0000000) >> 30) -sint recv_ucast_pn_decache(union recv_frame *precv_frame); + sint recv_ucast_pn_decache(union recv_frame *precv_frame) { struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; @@ -823,17 +730,20 @@ sint recv_ucast_pn_decache(union recv_frame *precv_frame) struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache; u8 *pdata = precv_frame->u.hdr.rx_data; sint tid = precv_frame->u.hdr.attrib.priority; - u64 tmp_iv_hdr = 0; u64 curr_pn = 0, pkt_pn = 0; + u8 pn[8] = {0}; if (tid > 15) return _FAIL; - if (pattrib->encrypt == _AES_) { - tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); - pkt_pn = CCMPH_2_PN(tmp_iv_hdr); - tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]); - curr_pn = CCMPH_2_PN(tmp_iv_hdr); + if (pattrib->encrypt == _TKIP_ || pattrib->encrypt == _AES_ || + pattrib->encrypt == _GCMP_ || pattrib->encrypt == _CCMP_256_ || + pattrib->encrypt == _GCMP_256_) { + rtw_iv_to_pn((pdata + pattrib->hdrlen), pn, NULL, pattrib->encrypt); + pkt_pn = RTW_GET_LE64(pn); + + rtw_iv_to_pn(prxcache->iv[tid], pn, NULL, pattrib->encrypt); + curr_pn = RTW_GET_LE64(pn); if (!VALID_PN_CHK(pkt_pn, curr_pn)) { /* return _FAIL; */ @@ -848,27 +758,24 @@ sint recv_ucast_pn_decache(union recv_frame *precv_frame) return _SUCCESS; } -sint recv_bcast_pn_decache(union recv_frame *precv_frame); sint recv_bcast_pn_decache(union recv_frame *precv_frame) { _adapter *padapter = precv_frame->u.hdr.adapter; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; u8 *pdata = precv_frame->u.hdr.rx_data; - u64 tmp_iv_hdr = 0; u64 curr_pn = 0, pkt_pn = 0; + u8 pn[8] = {0}; u8 key_id; - if ((pattrib->encrypt == _AES_) && - (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { - - tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); - key_id = CCMPH_2_KEYID(tmp_iv_hdr); - pkt_pn = CCMPH_2_PN(tmp_iv_hdr); - + if ((pattrib->encrypt == _TKIP_ || pattrib->encrypt == _AES_ || + pattrib->encrypt == _GCMP_ || pattrib->encrypt == _CCMP_256_ || + pattrib->encrypt == _GCMP_256_) && + (MLME_IS_STA(padapter))) { + rtw_iv_to_pn((pdata + pattrib->hdrlen), pn, &key_id, + pattrib->encrypt); + pkt_pn = RTW_GET_LE64(pn); curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]); - curr_pn &= 0x0000ffffffffffff; if (!VALID_PN_CHK(pkt_pn, curr_pn)) return _FAIL; @@ -925,7 +832,7 @@ sint recv_decache(union recv_frame *precv_frame) #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache _FAIL for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->phl_sta->mac_addr)); #endif return _FAIL; } @@ -945,7 +852,7 @@ void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, stru if (pwrbit) { if (!(psta->state & WIFI_SLEEP_STATE)) { /* psta->state |= WIFI_SLEEP_STATE; */ - /* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ + /* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->phl_sta->aid)); */ stop_sta_xmit(padapter, psta); /* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ @@ -953,7 +860,7 @@ void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, stru } else { if (psta->state & WIFI_SLEEP_STATE) { /* psta->state ^= WIFI_SLEEP_STATE; */ - /* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ + /* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->phl_sta->aid)); */ wakeup_sta_to_xmit(padapter, psta); /* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ @@ -1010,7 +917,7 @@ void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struc xmit_delivery_enabled_frames(padapter, psta); } else { /* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */ - issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0); + issue_qos_nulldata(padapter, psta->phl_sta->mac_addr, (u16)pattrib->priority, 0, 0, 0, _FALSE); } } @@ -1046,7 +953,7 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) RTW_INFO("[TDLS] Recv %s from "MAC_FMT" with SeqNum = %d\n", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame))); - if (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) { + if (rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_TDLS) == _FALSE) { RTW_INFO("Ignore tdls frame since hal doesn't support tdls\n"); ret = _FAIL; return ret; @@ -1142,13 +1049,12 @@ sint rtw_tdls_rx_data_validate_hdr( u8 *ptr = precv_frame->u.hdr.rx_data; sint ret = _SUCCESS; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &adapter->stapriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; u8 *mybssid = get_bssid(pmlmepriv); u8 *myhwaddr = adapter_mac_addr(adapter); u8 *sta_addr = pattrib->ta; sint bmcast = IS_MCAST(pattrib->dst); - struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; #ifdef CONFIG_TDLS_CH_SW struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info; @@ -1157,7 +1063,6 @@ sint rtw_tdls_rx_data_validate_hdr( u8 *psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; /* frame body located after [+2]: ether-type, [+1]: payload type */ u8 *pframe_body = psnap_type + 2 + 1; - *psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta); if (ptdls_sta == NULL) { ret = _FAIL; @@ -1183,7 +1088,7 @@ sint rtw_tdls_rx_data_validate_hdr( #ifdef CONFIG_TDLS_CH_SW if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { - if (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) { + if (adapter->mlmeextpriv.chandef.chan != rtw_get_oper_ch(adapter)) { pchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE; if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _cancel_timer_ex(&ptdls_sta->ch_sw_timer); @@ -1204,7 +1109,6 @@ sint rtw_tdls_rx_data_validate_hdr( RTW_INFO("TDLS: recv peer null frame with pwr bit 1\n"); /* ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; */ } - /* TODO: Updated BSSID's seq. */ /* RTW_INFO("drop Null Data\n"); */ ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); @@ -1236,10 +1140,10 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in struct sta_info *psta = NULL; struct stainfo_stats *pstats = NULL; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; sz = get_recvframe_len(prframe); - precvpriv->rx_bytes += sz; + precvinfo->rx_bytes += sz; padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++; @@ -1272,9 +1176,7 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in /*record rx packets for every tid*/ pstats->rx_data_qos_pkts[pattrib->priority]++; } -#ifdef CONFIG_DYNAMIC_SOML - rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz); -#endif + #if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP) if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) traffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta); @@ -1291,188 +1193,37 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in } -int rtw_sta_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta) +sint sta2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta +) { - struct sta_priv *stapriv = &adapter->stapriv; - u8 *mybssid = get_bssid(&adapter->mlmepriv); + u8 *ptr = precv_frame->u.hdr.rx_data; + sint ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 *mybssid = get_bssid(pmlmepriv); u8 *myhwaddr = adapter_mac_addr(adapter); - struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; - u8 *whdr = get_recvframe_data(rframe); - u8 is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0; - sint ret = _FAIL; + u8 *sta_addr = pattrib->ta; + sint bmcast = IS_MCAST(pattrib->dst); - if (rattrib->to_fr_ds == 0) { - _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->bssid, GetAddr3Ptr(whdr), ETH_ALEN); + /* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */ - #ifdef CONFIG_TDLS - if (adapter->tdlsinfo.link_established == _TRUE) - ret = rtw_tdls_rx_data_validate_hdr(adapter, rframe, sta); - else - #endif - { - /* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */ - if (!_rtw_memcmp(rattrib->bssid, rattrib->src, ETH_ALEN)) - goto exit; + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { - *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); - if (*sta) - ret = _SUCCESS; + /* filter packets that SA is myself or multicast or broadcast */ + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { + ret = _FAIL; + goto exit; } - goto exit; - } - if (!(MLME_STATE(adapter) & (WIFI_ASOC_STATE | WIFI_UNDER_LINKING))) { - if (!is_ra_bmc) { - /* for AP multicast issue , modify by yiwei */ - static systime send_issue_deauth_time = 0; - - /* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */ - if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) { - send_issue_deauth_time = rtw_get_current_time(); - RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), mlme_state:0x%x\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(get_addr2_ptr(whdr)), MLME_STATE(adapter)); - issue_deauth(adapter, get_addr2_ptr(whdr), WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); - } - } - #ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n" - , FUNC_ADPT_ARG(adapter), MLME_STATE(adapter)); - #endif - goto exit; - } - - _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); - - switch (rattrib->to_fr_ds) { - case 2: - _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); - _rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ - _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); - break; - case 3: - _rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ - _rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ - _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); - break; - default: - ret = RTW_RX_HANDLED; /* don't count for drop */ - goto exit; - } - - /* filter packets that SA is myself */ - if (!rattrib->amsdu && _rtw_memcmp(myhwaddr, rattrib->src, ETH_ALEN)) { - #ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->src), MAC_ARG(myhwaddr)); - #endif - goto exit; - } - - *sta = rtw_get_stainfo(stapriv, rattrib->ta); - if (*sta == NULL) { - #ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL - if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) { - RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta)); - issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); - } - #endif - #ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n" - , FUNC_ADPT_ARG(adapter)); - #endif - goto exit; - } - -#ifdef CONFIG_RTW_WDS_AUTO_EN - if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS)) - sta->flags |= WLAN_STA_WDS; -#endif - - /*if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { - } - */ - - if (get_frame_sub_type(whdr) & BIT(6)) { - /* No data, will not indicate to upper layer, temporily count it here */ - count_rx_stats(adapter, rframe, *sta); - ret = RTW_RX_HANDLED; - goto exit; - } - -#ifdef CONFIG_RTW_WDS - if (adapter_use_wds(adapter) - && !rattrib->amsdu && IS_MCAST(rattrib->dst) - && rtw_rx_wds_gptr_check(adapter, rattrib->src) - ) { - /* will not indicate to upper layer, temporily count it here */ - count_rx_stats(adapter, rframe, *sta); - ret = RTW_RX_HANDLED; - goto exit; - } -#endif - - ret = _SUCCESS; - -exit: - return ret; -} - -int rtw_sta_rx_amsdu_act_check(union recv_frame *rframe - , const u8 *da, const u8 *sa) -{ - int act = RTW_RX_MSDU_ACT_INDICATE; - -#ifdef CONFIG_RTW_WDS - _adapter *adapter = rframe->u.hdr.adapter; - - if (adapter_use_wds(adapter) - && IS_MCAST(da) - && rtw_rx_wds_gptr_check(adapter, sa) - ) { - act = 0; - } -#endif - - return act; -} - -sint sta2sta_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta -) -{ - u8 *ptr = precv_frame->u.hdr.rx_data; - sint ret = _SUCCESS; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &adapter->stapriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - u8 *mybssid = get_bssid(pmlmepriv); - u8 *myhwaddr = adapter_mac_addr(adapter); - u8 *sta_addr = pattrib->ta; - sint bmcast = IS_MCAST(pattrib->dst); - - /* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */ - - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || - (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { - - /* filter packets that SA is myself or multicast or broadcast */ - if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { - ret = _FAIL; - goto exit; - } - - if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { - ret = _FAIL; - goto exit; - } + if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { + ret = _FAIL; + goto exit; + } if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || @@ -1506,6 +1257,7 @@ sint sta2sta_data_frame( exit: return ret; + } sint ap2sta_data_frame( @@ -1581,7 +1333,6 @@ sint sta2ap_data_frame( struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct sta_priv *pstapriv = &adapter->stapriv; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - unsigned char *mybssid = get_bssid(pmlmepriv); sint ret = _SUCCESS; if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && @@ -1625,159 +1376,310 @@ sint sta2ap_data_frame( } -sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame); -sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) +int rtw_sta_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta) { - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &padapter->stapriv; - u8 *pframe = precv_frame->u.hdr.rx_data; - struct sta_info *psta = NULL; - /* uint len = precv_frame->u.hdr.len; */ - - /* RTW_INFO("+validate_recv_ctrl_frame\n"); */ - - if (GetFrameType(pframe) != WIFI_CTRL_TYPE) - return _FAIL; - - /* receive the frames that ra(a1) is my address */ - if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN)) - return _FAIL; - - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); - if (psta == NULL) - return _FAIL; - - /* for rx pkt statistics */ - psta->sta_stats.last_rx_time = rtw_get_current_time(); - psta->sta_stats.rx_ctrl_pkts++; + struct sta_priv *stapriv = &adapter->stapriv; + u8 *myhwaddr = adapter_mac_addr(adapter); + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + u8 *whdr = get_recvframe_data(rframe); + u8 is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0; + sint ret = _FAIL; - /* only handle ps-poll */ - if (get_frame_sub_type(pframe) == WIFI_PSPOLL) { -#ifdef CONFIG_AP_MODE - u16 aid; - u8 wmmps_ac = 0; + if (rattrib->to_fr_ds == 0) { + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->bssid, GetAddr3Ptr(whdr), ETH_ALEN); - aid = GetAid(pframe); - if (psta->cmn.aid != aid) - return _FAIL; + #ifdef CONFIG_TDLS + if (adapter->tdlsinfo.link_established == _TRUE) + ret = rtw_tdls_rx_data_validate_hdr(adapter, rframe, sta); + else + #endif + { + /* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */ + if (!_rtw_memcmp(rattrib->bssid, rattrib->src, ETH_ALEN)) + goto exit; - switch (pattrib->priority) { - case 1: - case 2: - wmmps_ac = psta->uapsd_bk & BIT(0); - break; - case 4: - case 5: - wmmps_ac = psta->uapsd_vi & BIT(0); - break; - case 6: - case 7: - wmmps_ac = psta->uapsd_vo & BIT(0); - break; - case 0: - case 3: - default: - wmmps_ac = psta->uapsd_be & BIT(0); - break; + *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); + if (*sta) + ret = _SUCCESS; } + goto exit; + } - if (wmmps_ac) - return _FAIL; + if (!(MLME_STATE(adapter) & (WIFI_ASOC_STATE | WIFI_UNDER_LINKING))) { + if (!is_ra_bmc) { + /* for AP multicast issue , modify by yiwei */ + static systime send_issue_deauth_time = 0; - #ifdef CONFIG_AP_MODE - if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { - RTW_INFO("%s alive check-rx ps-poll\n", __func__); - psta->expire_to = pstapriv->expire_to; - psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + /* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */ + if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) { + send_issue_deauth_time = rtw_get_current_time(); + RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), mlme_state:0x%x\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(get_addr2_ptr(whdr)), MLME_STATE(adapter)); + issue_deauth(adapter, get_addr2_ptr(whdr), WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } } + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n" + , FUNC_ADPT_ARG(adapter), MLME_STATE(adapter)); #endif + goto exit; + } - if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) { - _irqL irqL; - _list *xmitframe_plist, *xmitframe_phead; - struct xmit_frame *pxmitframe = NULL; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - - /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ - _enter_critical_bh(&pxmitpriv->lock, &irqL); - - xmitframe_phead = get_list_head(&psta->sleep_q); - xmitframe_plist = get_next(xmitframe_phead); - - if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { - pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - - xmitframe_plist = get_next(xmitframe_plist); - - rtw_list_delete(&pxmitframe->list); + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); - psta->sleepq_len--; + switch (rattrib->to_fr_ds) { + case 1: + _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + break; + case 3: + _rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + break; + default: + ret = RTW_RX_HANDLED; /* don't count for drop */ + goto exit; + } - if (psta->sleepq_len > 0) - pxmitframe->attrib.mdata = 1; - else - pxmitframe->attrib.mdata = 0; + /* filter packets that SA is myself */ + if (!rattrib->amsdu && _rtw_memcmp(myhwaddr, rattrib->src, ETH_ALEN)) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->src), MAC_ARG(myhwaddr)); + #endif + goto exit; + } - pxmitframe->attrib.triggered = 1; + *sta = rtw_get_stainfo(stapriv, rattrib->ta); + if (*sta == NULL) { + #ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL + if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) { + RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta)); + issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } + #endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } + +#ifdef CONFIG_RTW_WDS_AUTO_EN + if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS)) + sta->flags |= WLAN_STA_WDS; +#endif - /* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */ - /* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ + /*if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + } + */ -#if 0 - _exit_critical_bh(&psta->sleep_q.lock, &irqL); - if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE) - rtw_os_xmit_complete(padapter, pxmitframe); - _enter_critical_bh(&psta->sleep_q.lock, &irqL); + if (get_frame_sub_type(whdr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, rframe, *sta); + ret = RTW_RX_HANDLED; + goto exit; + } + +#ifdef CONFIG_RTW_WDS + if (adapter_use_wds(adapter) + && !rattrib->amsdu && IS_MCAST(rattrib->dst) + && rtw_rx_wds_gptr_check(adapter, rattrib->src) + ) { + /* will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, rframe, *sta); + ret = RTW_RX_HANDLED; + goto exit; + } #endif - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); - if (psta->sleepq_len == 0) { - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + ret = _SUCCESS; - /* RTW_INFO("after handling ps-poll\n"); */ - /* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ +exit: + return ret; +} - /* upate BCN for TIM IE */ - /* update_BCNTIM(padapter); */ - update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); - } +int rtw_sta_rx_amsdu_act_check(union recv_frame *rframe + , const u8 *da, const u8 *sa) +{ + int act = RTW_RX_MSDU_ACT_INDICATE; - /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ - _exit_critical_bh(&pxmitpriv->lock, &irqL); +#ifdef CONFIG_RTW_WDS + _adapter *adapter = rframe->u.hdr.adapter; - } else { - /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ - _exit_critical_bh(&pxmitpriv->lock, &irqL); - - /* RTW_INFO("no buffered packets to xmit\n"); */ - if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { - if (psta->sleepq_len == 0) { - RTW_INFO("no buffered packets to xmit\n"); - - /* issue nulldata with More data bit = 0 to indicate we have no buffered packets */ - issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0); - } else { - RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len); - psta->sleepq_len = 0; - } + if (adapter_use_wds(adapter) + && IS_MCAST(da) + && rtw_rx_wds_gptr_check(adapter, sa) + ) { + act = 0; + } +#endif + + return act; +} + +#ifdef CONFIG_AP_MODE +sint rtw_proccess_pspoll(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *psta) +{ + u8 *pframe = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + u16 aid; + u8 wmmps_ac = 0; + + aid = GetAid(pframe); + if (psta->phl_sta->aid != aid) + return _FAIL; + + switch (pattrib->priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(0); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(0); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(0); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(0); + break; + } + + if (wmmps_ac) + return _FAIL; + + if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { + RTW_INFO("%s alive check-rx ps-poll\n", __func__); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(adapter, pstapriv->sta_dz_bitmap, psta->phl_sta->aid))) { + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + /* _rtw_spinlock_bh(&psta->sleep_q.lock); */ + _rtw_spinlock_bh(&pxmitpriv->lock); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + rtw_list_delete(&pxmitframe->list); + + psta->sleepq_len--; + + if (psta->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + + /* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ +#if 0 + _rtw_spinunlock_bh(&psta->sleep_q.lock); + if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + rtw_os_xmit_complete(padapter, pxmitframe); + _rtw_spinlock_bh(&psta->sleep_q.lock); +#endif + rtw_intf_xmitframe_enqueue(adapter, pxmitframe); - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + if (psta->sleepq_len == 0) { + rtw_tim_map_clear(adapter, pstapriv->tim_bitmap, psta->phl_sta->aid); + /* RTW_INFO("after handling ps-poll\n"); */ + /* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ - /* upate BCN for TIM IE */ - /* update_BCNTIM(padapter); */ - update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + rtw_update_beacon(adapter, _TIM_IE_, NULL, _TRUE, 0); + } + /* _rtw_spinunlock_bh(&psta->sleep_q.lock); */ + _rtw_spinunlock_bh(&pxmitpriv->lock); + } else { + /* _rtw_spinunlock_bh(&psta->sleep_q.lock); */ + _rtw_spinunlock_bh(&pxmitpriv->lock); + /* RTW_INFO("no buffered packets to xmit\n"); */ + if (rtw_tim_map_is_set(adapter, pstapriv->tim_bitmap, psta->phl_sta->aid)) { + if (psta->sleepq_len == 0) { + RTW_INFO("no buffered packets to xmit\n"); + /* issue nulldata with More data bit = 0 to indicate we have no buffered packets */ + issue_nulldata(adapter, psta->phl_sta->mac_addr, 0, 0, 0); + } else { + RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len); + psta->sleepq_len = 0; } + rtw_tim_map_clear(adapter, pstapriv->tim_bitmap, psta->phl_sta->aid); + + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + rtw_update_beacon(adapter, _TIM_IE_, NULL, _TRUE, 0); } } -#endif /* CONFIG_AP_MODE */ - } else if (get_frame_sub_type(pframe) == WIFI_NDPA) { -#ifdef CONFIG_BEAMFORMING - rtw_beamforming_get_ndpa_frame(padapter, precv_frame); -#endif/*CONFIG_BEAMFORMING*/ - } else if (get_frame_sub_type(pframe) == WIFI_BAR) { - rtw_process_bar_frame(padapter, precv_frame); } + return _SUCCESS; +} +#endif /*CONFIG_AP_MODE*/ +sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = NULL; + /* uint len = precv_frame->u.hdr.len; */ + + /* RTW_INFO("+validate_recv_ctrl_frame\n"); */ + + if (GetFrameType(pframe) != WIFI_CTRL_TYPE) + return _FAIL; + + /* receive the frames that ra(a1) is my address */ + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN)) + return _FAIL; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + return _FAIL; + + /* for rx pkt statistics */ + psta->sta_stats.last_rx_time = rtw_get_current_time(); + psta->sta_stats.rx_ctrl_pkts++; + + switch (get_frame_sub_type(pframe)) { + #ifdef CONFIG_AP_MODE + case WIFI_PSPOLL : + { + sint rst; + rst = rtw_proccess_pspoll(padapter, precv_frame, psta); + /*RTW_INFO(FUNC_ADPT_FMT" pspoll handle %d\n", FUNC_ADPT_ARG(padapter), rst);*/ + } + break; + #endif + case WIFI_BAR : + rtw_process_bar_frame(padapter, precv_frame); + break; + default : + break; + } return _FAIL; } @@ -1881,7 +1783,11 @@ static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_fra /* unicast cases */ #ifdef CONFIG_IEEE80211W if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { - if (!MLME_IS_MESH(adapter)) { + if (!MLME_IS_MESH(adapter) + #ifdef CONFIG_RTW_WNM + && (rtw_wnm_try_btm_roam_imnt(adapter) > 0) + #endif + ) { unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); #if DBG_VALIDATE_MGMT_PROTECT @@ -1890,7 +1796,7 @@ static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_fra #endif if (reason == 6 || reason == 7) { /* issue sa query request */ - issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); + issue_action_SA_Query(adapter, psta->phl_sta->mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); } } goto fail; @@ -1935,7 +1841,7 @@ static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_fra ret = rtw_bip_verify(bip_cipher, pattrib->pkt_len, get_recvframe_data(precv_frame), get_recvframe_len(precv_frame), - igtk, igtk_id, ipn); + igtk, igtk_id, ipn, (u8 *)precv_frame); if (ret == _FAIL) { /* RTW_INFO("802.11w BIP verify fail\n"); */ @@ -1957,7 +1863,9 @@ static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_fra } /* cases to decrypt mgmt frame */ +#if 0 pattrib->bdecrypted = 0; +#endif #ifdef CONFIG_RTW_MESH if (is_bmc) pattrib->encrypt = psta->group_privacy; @@ -2028,9 +1936,9 @@ static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_fra } #endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ -union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); +s32 recvframe_chk_defrag(_adapter *padapter, union recv_frame **pprecv_frame); -sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +sint validate_recv_mgnt_frame(_adapter *padapter, union recv_frame *precv_frame) { struct sta_info *psta = precv_frame->u.hdr.psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); @@ -2042,8 +1950,7 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) } #endif - precv_frame = recvframe_chk_defrag(padapter, precv_frame); - if (precv_frame == NULL) + if (recvframe_chk_defrag(padapter, &precv_frame) != CORE_RX_CONTINUE) return _SUCCESS; /* for rx pkt statistics */ @@ -2082,6 +1989,9 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct security_priv *psecuritypriv = &adapter->securitypriv; sint ret = _SUCCESS; +#ifdef ROKU_PRIVATE + struct stainfo_stats *pstats = NULL; +#endif bretry = GetRetry(ptr); a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0; @@ -2122,19 +2032,19 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) case 1: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN); - ret = sta2ap_data_frame(adapter, precv_frame, &psta); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN); + ret = ap2sta_data_frame(adapter, precv_frame, &psta); break; case 2: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN); - ret = ap2sta_data_frame(adapter, precv_frame, &psta); + _rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN); + ret = sta2ap_data_frame(adapter, precv_frame, &psta); break; case 3: @@ -2146,6 +2056,13 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) pre_validate_status_chk: +#ifdef ROKU_PRIVATE + if(psta!=NULL && bretry){ + pstats = &psta->sta_stats; + ATOMIC_ADD((ATOMIC_T *)&pstats->rx_retry_cnt, 1); + } +#endif + if (ret == _FAIL) { #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n" @@ -2166,17 +2083,19 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) } if ((psta->flags & WLAN_STA_AMSDU_DISABLE) && pattrib->amsdu) { - #ifdef DBG_RX_DROP_FRAME + #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu not allowed"MAC_FMT"\n" , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); - #endif + #endif ret = _FAIL; goto exit; } precv_frame->u.hdr.psta = psta; +#ifdef CONFIG_RECV_REORDERING_CTRL precv_frame->u.hdr.preorder_ctrl = NULL; +#endif pattrib->ack_policy = 0; /* parsing QC field */ @@ -2184,10 +2103,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/ pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift)); pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift; - if (pattrib->priority != 0 && pattrib->priority != 3) - adapter->recvpriv.is_any_non_be_pkts = _TRUE; - else - adapter->recvpriv.is_any_non_be_pkts = _FALSE; } else { pattrib->priority = 0; pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift; @@ -2202,14 +2117,14 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) goto exit; if (!IS_MCAST(pattrib->ra)) { - +#ifdef CONFIG_RECV_REORDERING_CTRL if (pattrib->qos) precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; - +#endif if (recv_ucast_pn_decache(precv_frame) == _FAIL) { #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->phl_sta->mac_addr)); #endif ret = _FAIL; goto exit; @@ -2218,7 +2133,7 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) if (recv_bcast_pn_decache(precv_frame) == _FAIL) { #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->phl_sta->mac_addr)); #endif ret = _FAIL; goto exit; @@ -2261,11 +2176,11 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) ether_type = ntohs((unsigned short)ether_type); if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { - /* CVE-2020-26140, CVE-2020-26143, CVE-2020-26147, let eapol packet go through*/ + /* CVE-2020-26140, CVE-2020-26143, CVE-2020-26147, let eapol packet go through*/ if (!pattrib->privacy && ether_type != eapol_type ) { #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT"recv plaintext unicast packet for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); #endif ret = _FAIL; goto exit; @@ -2275,7 +2190,7 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) if (!pattrib->privacy && pattrib->amsdu) { #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT"recv plaintext A-MSDU for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); #endif ret = _FAIL; goto exit; @@ -2295,14 +2210,14 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) } else { /* CVE-2020-26140, CVE-2020-26143, CVE-2020-26147 */ if (!pattrib->privacy) { - #ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT"recv plaintext packet for sta="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); - #endif - ret = _FAIL; - goto exit; + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT"recv plaintext packet for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; } - } + } } } @@ -2314,6 +2229,10 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) #endif exit: + +#ifdef RTW_PHL_TEST_FPGA + return _SUCCESS; +#endif return ret; } @@ -2328,7 +2247,6 @@ static inline void dump_rx_packet(u8 *ptr) RTW_INFO("#############################\n"); } -sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame); sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) { /* shall check frame subtype, to / from ds, da, bssid */ @@ -2340,7 +2258,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) sint retval = _SUCCESS; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct recv_priv *precvpriv = &adapter->recvpriv; + struct recv_info *precvinfo = &adapter->recvinfo; u8 *ptr = precv_frame->u.hdr.rx_data; u8 ver = (unsigned char)(*ptr) & 0x3 ; @@ -2357,7 +2275,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) struct recv_frame_hdr *phdr = &precv_frame->u.hdr; u8 wai_pkt = 0; u16 sc; - u8 external_len = 0; + u8 external_len = 0; #endif @@ -2412,6 +2330,17 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) sc = (pattrib->seq_num << 4) | pattrib->frag_num; #endif +#ifdef RTW_PHL_DBG_CMD + pattrib->wl_type = type; + pattrib->wl_subtype = subtype; + + if(type == WIFI_DATA_TYPE) + core_add_record(adapter, REC_RX_DATA, precv_frame); + else + core_add_record(adapter, REC_RX_MGMT, precv_frame); +#endif + + #if 1 /* Dump rx packets */ { u8 bDumpRxPkt = 0; @@ -2425,6 +2354,10 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) dump_rx_packet(ptr); } #endif +#ifdef RTW_WKARD_CORE_RSSI_V1 + rx_process_phy_info(precv_frame); +#endif + switch (type) { case WIFI_MGT_TYPE: /* mgnt */ DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt); @@ -2477,7 +2410,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->qos = (subtype & BIT(7)) ? 1 : 0; retval = validate_recv_data_frame(adapter, precv_frame); if (retval == _FAIL) { - precvpriv->dbg_rx_drop_count++; + precvinfo->dbg_rx_drop_count++; DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); } else if (retval == _SUCCESS) { #ifdef DBG_RX_DUMP_EAP @@ -2536,14 +2469,20 @@ enum rtw_rx_llc_hdl rtw_recv_llc_parse(u8 *msdu, u16 msdu_len) /* TODO: VLAN tagged */ } + /* remove the wlanhdr and add the eth_hdr */ sint wlanhdr_to_ethhdr(union recv_frame *precvframe, enum rtw_rx_llc_hdl llc_hdl) { - u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ + u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; sint rmv_len; - u16 eth_type, len; + u16 len; sint ret = _SUCCESS; +#ifdef CONFIG_RTW_CORE_RXSC + _adapter *adapter = precvframe->u.hdr.adapter; + struct core_rxsc_entry *rxsc_entry = NULL; + u16 eth_type; +#endif if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); @@ -2551,12 +2490,38 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe, enum rtw_rx_llc_hdl llc_hdl rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (llc_hdl ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; +#ifdef CONFIG_RTW_CORE_RXSC + _rtw_memcpy(ð_type, ptr + rmv_len, 2); + eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ + pattrib->eth_type = eth_type; + if (llc_hdl == RTW_RX_LLC_REMOVE) + pattrib->bsnaphdr = _TRUE; + else if (llc_hdl == RTW_RX_LLC_KEEP) + pattrib->bsnaphdr = _FALSE; + + rxsc_entry = core_rxsc_alloc_entry(adapter, precvframe); + + if (rxsc_entry) { + /* cache offset of payload */ + rxsc_entry->rxsc_payload_offset = (rmv_len - sizeof(struct ethhdr) + (pattrib->bsnaphdr ? 2 : 0)); + + /* cache padding size of tail */ + if (pattrib->encrypt) + rxsc_entry->rxsc_trim_pad = pattrib->icv_len; + else + rxsc_entry->rxsc_trim_pad = 0; + + /* cache WLAN header */ + _rtw_memcpy((void *)&rxsc_entry->rxsc_wlanhdr, ptr, pattrib->hdrlen); + } +#endif ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0))); if (!ptr) { ret = _FAIL; goto exiting; } + _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); _rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN); @@ -2567,19 +2532,33 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe, enum rtw_rx_llc_hdl llc_hdl rtw_rframe_set_os_pkt(precvframe); +#ifdef CONFIG_RTW_CORE_RXSC + if (rxsc_entry) { + /* Cache ETH header */ + memcpy((void *)&rxsc_entry->rxsc_ethhdr, ptr, sizeof(rxsc_entry->rxsc_ethhdr)); + + /* Cache Rx Attribute */ + memcpy((void *)&rxsc_entry->rxsc_attrib, pattrib, sizeof(rxsc_entry->rxsc_attrib)); + } +#ifdef RTW_PHL_DBG_CMD + adapter->core_logs.rxCnt_data_orig++; +#endif +#endif + exiting: return ret; + } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_RX_COPY #ifdef PLATFORM_LINUX static void recvframe_expand_pkt( - PADAPTER padapter, + _adapter *padapter, union recv_frame *prframe) { struct recv_frame_hdr *pfhdr; - _pkt *ppkt; + struct sk_buff *ppkt; u8 shift_sz; u32 alloc_sz; u8 *ptr; @@ -2633,7 +2612,6 @@ static void recvframe_expand_pkt( #endif /* perform defrag */ -union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q); union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) { _list *plist, *phead; @@ -2641,15 +2619,12 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) u8 curfragnum; struct recv_frame_hdr *pfhdr, *pnfhdr; union recv_frame *prframe, *pnextrframe; - _queue *pfree_recv_queue; u8 *pdata = NULL; u64 tmp_iv_hdr = 0; u64 pkt_pn = 0, cur_pn = 0; struct rx_pkt_attrib *pattrib = NULL; curfragnum = 0; - pfree_recv_queue = &adapter->recvpriv.free_recv_queue; - phead = get_list_head(defrag_q); plist = get_next(phead); prframe = LIST_CONTAINOR(plist, union recv_frame, u); @@ -2662,14 +2637,15 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) /* get the first frame's PN. */ cur_pn = CCMPH_2_PN(tmp_iv_hdr); } + pfhdr = &prframe->u.hdr; rtw_list_delete(&(prframe->u.list)); if (curfragnum != pfhdr->attrib.frag_num) { /* the first fragment number must be 0 */ /* free the whole queue */ - rtw_free_recvframe(prframe, pfree_recv_queue); - rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + rtw_free_recvframe(prframe); + rtw_free_recvframe_queue(defrag_q); return NULL; } @@ -2703,8 +2679,8 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) __func__, cur_pn, pkt_pn); /* PN must be consecutive */ /* release the defrag_q & prframe */ - rtw_free_recvframe(prframe, pfree_recv_queue); - rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + rtw_free_recvframe(prframe); + rtw_free_recvframe_queue(defrag_q); return NULL; } else { cur_pn = pkt_pn; @@ -2714,8 +2690,8 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) /* CVE-2020-24587, The keytrack of the fragment is supposed to be the same with other's */ if (pfhdr->keytrack != pnfhdr->keytrack) { RTW_INFO("Inconsistent key track, drop fragmented frame!\n"); - rtw_free_recvframe(prframe, pfree_recv_queue); - rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + rtw_free_recvframe(prframe); + rtw_free_recvframe_queue(defrag_q); return NULL; } @@ -2724,8 +2700,8 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) if (curfragnum != pnfhdr->attrib.frag_num) { /* the fragment number must be increasing (after decache) */ /* release the defrag_q & prframe */ - rtw_free_recvframe(prframe, pfree_recv_queue); - rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + rtw_free_recvframe(prframe); + rtw_free_recvframe_queue(defrag_q); return NULL; } @@ -2741,7 +2717,7 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) /* append to first fragment frame's tail (if privacy frame, pull the ICV) */ recvframe_pull_tail(prframe, pfhdr->attrib.icv_len); - /* memcpy */ + /* _rtw_memcpy */ _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len); recvframe_put(prframe, pnfhdr->len); @@ -2752,7 +2728,7 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) }; /* free the defrag_q queue and return the prframe */ - rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + rtw_free_recvframe_queue(defrag_q); @@ -2760,7 +2736,7 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) } /* check if need to defrag, if needed queue the frame to defrag_q */ -union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame) +s32 recvframe_chk_defrag(_adapter *padapter, union recv_frame **pprecv_frame) { u8 ismfrag; u8 fragnum; @@ -2770,15 +2746,15 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec struct sta_priv *pstapriv; _list *phead; union recv_frame *prtnframe = NULL; - _queue *pfree_recv_queue, *pdefrag_q = NULL; + _queue *pdefrag_q = NULL; + union recv_frame *precv_frame = *pprecv_frame; + s32 ret = CORE_RX_CONTINUE; pstapriv = &padapter->stapriv; pfhdr = &precv_frame->u.hdr; - pfree_recv_queue = &padapter->recvpriv.free_recv_queue; - /* need to define struct of wlan header frame ctrl */ ismfrag = pfhdr->attrib.mfrag; fragnum = pfhdr->attrib.frag_num; @@ -2797,13 +2773,12 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec pdefrag_q = &psta->sta_recvpriv.defrag_q; if ((ismfrag == 0) && (fragnum == 0)) { - prtnframe = precv_frame;/* isn't a fragment frame */ + ret = CORE_RX_CONTINUE; } else { /* CVE-2020-26145, group addressed frame cannot use fragmentation!! */ if (IS_MCAST(pfhdr->attrib.ra)) { RTW_INFO("DROP group addressed fragment!\n"); - rtw_free_recvframe(precv_frame, pfree_recv_queue); - return NULL; + ret = CORE_RX_DROP; } /* CVE-2020-24587 */ if ((psta) && (pdefrag_q)) @@ -2818,7 +2793,7 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* the first fragment */ if (_rtw_queue_empty(pdefrag_q) == _FALSE) { /* free current defrag_q */ - rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue); + rtw_free_recvframe_queue(pdefrag_q); } } @@ -2831,12 +2806,10 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* _rtw_spinunlock(&pdefrag_q->lock); */ - prtnframe = NULL; - + ret = CORE_RX_DEFRAG; } else { /* can't find this ta's defrag_queue, so free this recv_frame */ - rtw_free_recvframe(precv_frame, pfree_recv_queue); - prtnframe = NULL; + ret = CORE_RX_DROP; } } @@ -2851,35 +2824,27 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* _rtw_spinunlock(&pdefrag_q->lock); */ /* call recvframe_defrag to defrag */ - precv_frame = recvframe_defrag(padapter, pdefrag_q); - prtnframe = precv_frame; - + *pprecv_frame = recvframe_defrag(padapter, pdefrag_q); + if (*pprecv_frame == NULL) + ret = CORE_RX_DROP; + else { + ret = CORE_RX_CONTINUE; + } } else { /* can't find this ta's defrag_queue, so free this recv_frame */ - rtw_free_recvframe(precv_frame, pfree_recv_queue); - prtnframe = NULL; + ret = CORE_RX_DROP; } } - - if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) { - /* after defrag we must check tkip mic code */ - if (recvframe_chkmic(padapter, prtnframe) == _FAIL) { - rtw_free_recvframe(prtnframe, pfree_recv_queue); - prtnframe = NULL; - } - } - - - return prtnframe; + return ret; } static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len) { _adapter *adapter = rframe->u.hdr.adapter; - struct recv_priv *recvpriv = &adapter->recvpriv; + struct recv_info *recvinfo = &adapter->recvinfo; struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; #ifdef DBG_IP_R_MONITOR @@ -2916,7 +2881,7 @@ static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u3 dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0); #endif - if (recvpriv->sink_udpport > 0) + if (recvinfo->sink_udpport > 0) rtw_sink_rtp_seq_dbg(adapter, ehdr_pos); #ifdef DBG_UDP_PKT_LOSE_11AC @@ -2966,73 +2931,73 @@ static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u3 } #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) -static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list) +static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *f_list) { struct xmit_priv *xmitpriv = &adapter->xmitpriv; if (fwd_frame) - rtw_free_xmitframe(xmitpriv, fwd_frame); + core_tx_free_xmitframe(adapter, fwd_frame); -#if CONFIG_RTW_DATA_BMC_TO_UC - if (!rtw_is_list_empty(b2u_list)) { - struct xmit_frame *b2uframe; +#if defined(CONFIG_RTW_WDS) || CONFIG_RTW_DATA_BMC_TO_UC + if (!rtw_is_list_empty(f_list)) { + struct xmit_frame *fframe; _list *list; - list = get_next(b2u_list); - while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { - b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(f_list); + while (rtw_end_of_queue_search(f_list, list) == _FALSE) { + fframe = LIST_CONTAINOR(list, struct xmit_frame, list); list = get_next(list); - rtw_list_delete(&b2uframe->list); - rtw_free_xmitframe(xmitpriv, b2uframe); + rtw_list_delete(&fframe->list); + core_tx_free_xmitframe(adapter, fframe); } } #endif } -static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt - , u8 act, struct xmit_frame *fwd_frame, _list *b2u_list) +static void recv_fwd_pkt_hdl(_adapter *adapter, struct sk_buff *pkt + , u8 act, struct xmit_frame *fwd_frame, _list *f_list) { struct xmit_priv *xmitpriv = &adapter->xmitpriv; - _pkt *fwd_pkt = pkt; + struct sk_buff *fwd_pkt = pkt; if (act & RTW_RX_MSDU_ACT_INDICATE) { - fwd_pkt = rtw_os_pkt_copy(pkt); + fwd_pkt = rtw_skb_copy(pkt); if (!fwd_pkt) { #ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__); + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_skb_copy fail\n", __func__); #endif - recv_free_fwd_resource(adapter, fwd_frame, b2u_list); + recv_free_fwd_resource(adapter, fwd_frame, f_list); goto exit; } } -#if CONFIG_RTW_DATA_BMC_TO_UC - if (!rtw_is_list_empty(b2u_list)) { - _list *list = get_next(b2u_list); - struct xmit_frame *b2uframe; +#if defined(CONFIG_RTW_WDS) || CONFIG_RTW_DATA_BMC_TO_UC + if (!rtw_is_list_empty(f_list)) { + _list *list = get_next(f_list); + struct xmit_frame *fframe; - while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { - b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + while (rtw_end_of_queue_search(f_list, list) == _FALSE) { + fframe = LIST_CONTAINOR(list, struct xmit_frame, list); list = get_next(list); - rtw_list_delete(&b2uframe->list); + rtw_list_delete(&fframe->list); - if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */ - b2uframe->pkt = fwd_pkt; + if (!fwd_frame && rtw_is_list_empty(f_list)) /* the last fwd_pkt */ + fframe->pkt = fwd_pkt; else - b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt); - if (!b2uframe->pkt) { - rtw_free_xmitframe(xmitpriv, b2uframe); + fframe->pkt = rtw_skb_copy(fwd_pkt); + if (!fframe->pkt) { + core_tx_free_xmitframe(adapter, fframe); continue; } - rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt); + core_tx_per_packet(adapter, fframe, &fframe->pkt, NULL); } } #endif if (fwd_frame) { fwd_frame->pkt = fwd_pkt; - if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) { + if (core_tx_per_packet(adapter, fwd_frame, &fwd_pkt, NULL) < 0) { #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__); #endif @@ -3065,13 +3030,13 @@ static u8 validate_amsdu_content(_adapter *padapter, union recv_frame *prframe, padapter->securitypriv.dot11PrivacyAlgrthm != _NO_PRIVACY_) { /* 1.check From DS */ - if (pattrib->to_fr_ds == 2) { + if (pattrib->to_fr_ds == 1) { if (_rtw_memcmp(da, pattrib->ra, ETH_ALEN) == _FALSE) ret = _FAIL; } /* 2.check To DS */ - if (pattrib->to_fr_ds == 1) { + if (pattrib->to_fr_ds == 2) { if (_rtw_memcmp(sa, pattrib->ta, ETH_ALEN) == _FALSE) ret = _FAIL; } @@ -3093,14 +3058,12 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) u16 nSubframe_Length; u8 nr_subframes, i; u8 *pdata; - _pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT]; - struct recv_priv *precvpriv = &padapter->recvpriv; - _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); + struct sk_buff *sub_pkt, *subframes[MAX_SUBFRAME_COUNT]; const u8 *da, *sa; int act; #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) struct xmit_frame *fwd_frame; - _list b2u_list; + _list f_list; #endif enum rtw_rx_llc_hdl llc_hdl; u8 mctrl_len = 0; @@ -3112,6 +3075,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) if (rattrib->iv_len > 0) recvframe_pull(prframe, rattrib->iv_len); + if (rattrib->encrypt) recvframe_pull_tail(prframe, rattrib->icv_len); @@ -3127,6 +3091,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) } act = RTW_RX_MSDU_ACT_INDICATE; + #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) fwd_frame = NULL; #endif @@ -3139,20 +3104,19 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe , mctrl, mda, msa, &mctrl_len, &da, &sa); + if (v_ret != _SUCCESS) + goto move_to_next; if (validate_amsdu_content(padapter, prframe, da, sa) == _FAIL) { RTW_INFO("%s check subframe content fail!\n", __func__); break; } - if (v_ret != _SUCCESS) - goto move_to_next; - llc_hdl = rtw_recv_llc_parse(pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len); act = rtw_mesh_rx_msdu_act_check(prframe , mda, msa, da, sa, mctrl , pdata + ETH_HLEN + mctrl_len, llc_hdl - , &fwd_frame, &b2u_list); + , &fwd_frame, &f_list); } else #endif { @@ -3168,7 +3132,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter)) { act = rtw_ap_rx_msdu_act_check(prframe, da, sa - , pdata + ETH_HLEN, llc_hdl, &fwd_frame, &b2u_list); + , pdata + ETH_HLEN, llc_hdl, &fwd_frame, &f_list); } else #endif if (MLME_IS_STA(padapter)) @@ -3193,7 +3157,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__); #endif - recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + recv_free_fwd_resource(padapter, fwd_frame, &f_list); } #endif break; @@ -3201,18 +3165,20 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) if (act & RTW_RX_MSDU_ACT_FORWARD) { - recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list); + recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &f_list); if (!(act & RTW_RX_MSDU_ACT_INDICATE)) goto move_to_next; } #endif - if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS) + if (rtw_recv_indicatepkt_check(prframe, rtw_skb_data(sub_pkt), rtw_skb_len(sub_pkt)) == _SUCCESS) subframes[nr_subframes++] = sub_pkt; else - rtw_os_pkt_free(sub_pkt); + rtw_skb_free(sub_pkt); +#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) move_to_next: +#endif /* move the data point to data content */ pdata += ETH_HLEN; a_len -= ETH_HLEN; @@ -3247,14 +3213,13 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) } prframe->u.hdr.len = 0; - rtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */ + rtw_free_recvframe(prframe);/* free this recv_frame */ return ret; } static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) { - _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; int ret; @@ -3265,41 +3230,28 @@ static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n" , FUNC_ADPT_ARG(padapter)); #endif - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); goto exit; } } else { - u8 *msdu = get_recvframe_data(prframe) - + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib); - u16 msdu_len = prframe->u.hdr.len - - pattrib->hdrlen - pattrib->iv_len - RATTRIB_GET_MCTRL_LEN(pattrib) - - (pattrib->encrypt ? pattrib->icv_len : 0); - enum rtw_rx_llc_hdl llc_hdl = rtw_recv_llc_parse(msdu, msdu_len); int act = RTW_RX_MSDU_ACT_INDICATE; - #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) + #ifdef CONFIG_RTW_MESH /* TODO: move AP mode forward & b2u logic here */ struct xmit_frame *fwd_frame = NULL; - _list b2u_list; + _list f_list; - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - if (pattrib->mesh_ctrl_present) - act = rtw_mesh_rx_msdu_act_check(prframe - , pattrib->mda, pattrib->msa - , pattrib->dst, pattrib->src - , (struct rtw_ieee80211s_hdr *)(msdu - RATTRIB_GET_MCTRL_LEN(pattrib)) - , msdu, llc_hdl - , &fwd_frame, &b2u_list); - } else - #endif - if (MLME_IS_AP(padapter)) - act = rtw_ap_rx_msdu_act_check(prframe, pattrib->dst, pattrib->src - , msdu, llc_hdl, &fwd_frame, &b2u_list); + if (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) { + act = rtw_mesh_rx_msdu_act_check(prframe + , pattrib->mda, pattrib->msa + , pattrib->dst, pattrib->src + , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len) + , &fwd_frame, &f_list); + } #endif - #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) + #ifdef CONFIG_RTW_MESH if (!act) { - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); ret = _FAIL; goto exit; } @@ -3307,7 +3259,7 @@ static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) rtw_led_rx_control(padapter, pattrib->dst); - ret = wlanhdr_to_ethhdr(prframe, llc_hdl); + ret = wlanhdr_to_ethhdr(prframe, 0); if (ret != _SUCCESS) { if (act & RTW_RX_MSDU_ACT_INDICATE) { #ifdef DBG_RX_DROP_FRAME @@ -3315,34 +3267,34 @@ static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) , FUNC_ADPT_ARG(padapter)); #endif } - #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) + #ifdef CONFIG_RTW_MESH if (act & RTW_RX_MSDU_ACT_FORWARD) { #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__); #endif - recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + recv_free_fwd_resource(padapter, fwd_frame, &f_list); } #endif - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); goto exit; } - #if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) + #ifdef CONFIG_RTW_MESH if (act & RTW_RX_MSDU_ACT_FORWARD) { - recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list); + recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &f_list); if (!(act & RTW_RX_MSDU_ACT_INDICATE)) { prframe->u.hdr.pkt = NULL; - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); goto exit; } } #endif - if (!RTW_CANNOT_RUN(padapter)) { + if (!RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { ret = rtw_recv_indicatepkt_check(prframe , get_recvframe_data(prframe), get_recvframe_len(prframe)); if (ret != _SUCCESS) { - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); goto exit; } @@ -3359,11 +3311,11 @@ static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n" , FUNC_ADPT_ARG(padapter) - , rtw_is_drv_stopped(padapter) - , rtw_is_surprise_removed(padapter)); + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) + , dev_is_surprise_removed(adapter_to_dvobj(padapter))); #endif ret = _SUCCESS; /* don't count as packet drop */ - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); } } @@ -3374,8 +3326,8 @@ static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) #if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) { - PADAPTER padapter = preorder_ctrl->padapter; - struct recv_priv *precvpriv = &padapter->recvpriv; + _adapter *padapter = preorder_ctrl->padapter; + struct recv_info *precvinfo = &padapter->recvinfo; u8 wsize = preorder_ctrl->wsize_b; u16 wend; @@ -3417,7 +3369,7 @@ static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_n else preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; - precvpriv->dbg_rx_ampdu_window_shift_cnt++; + precvinfo->dbg_rx_ampdu_window_shift_cnt++; #ifdef DBG_RX_SEQ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n" , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); @@ -3437,9 +3389,7 @@ static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, un /* DbgPrint("+enqueue_reorder_recvframe()\n"); */ - /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ - /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ - + /* _rtw_spinlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ phead = get_list_head(ppending_recvframe_queue); plist = get_next(phead); @@ -3453,7 +3403,7 @@ static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, un else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) { /* Duplicate entry is found!! Do not insert current entry. */ - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ return _FALSE; } else @@ -3464,15 +3414,13 @@ static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, un } - /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ - /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ + /* _rtw_spinlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ rtw_list_delete(&(prframe->u.hdr.list)); rtw_list_insert_tail(&(prframe->u.hdr.list), plist); - /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ return _TRUE; @@ -3481,34 +3429,32 @@ static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, un static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq) { - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; if (current_seq < prev_seq) { - precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); - precvpriv->rx_drop += (4096 + current_seq - prev_seq); + precvinfo->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + precvinfo->rx_drop += (4096 + current_seq - prev_seq); } else { - precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); - precvpriv->rx_drop += (current_seq - prev_seq); + precvinfo->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); + precvinfo->rx_drop += (current_seq - prev_seq); } } static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) { - /* _irqL irql; */ _list *phead, *plist; union recv_frame *prframe; struct rx_pkt_attrib *pattrib; /* u8 index = 0; */ int bPktInBuf = _FALSE; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder); /* DbgPrint("+recv_indicatepkts_in_order\n"); */ - /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ - /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ + /* _rtw_spinlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ phead = get_list_head(ppending_recvframe_queue); plist = get_next(phead); @@ -3521,10 +3467,9 @@ static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ct /* Handling some condition for forced indicate case. */ if (bforced == _TRUE) { - precvpriv->dbg_rx_ampdu_forced_indicate_count++; + precvinfo->dbg_rx_ampdu_forced_indicate_count++; if (rtw_is_list_empty(phead)) { - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ - /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, &sp_flags); */ return _TRUE; } @@ -3572,7 +3517,7 @@ static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ct index++; if (index == 1) { /* Cancel previous pending timer. */ - /* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */ + /* PlatformCancelTimer(adapter, &pTS->RxPktPendingTimer); */ if (bforced != _TRUE) { /* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); @@ -3590,7 +3535,7 @@ static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ct /* indicate this recv_frame */ /* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */ if (recv_process_mpdu(padapter, prframe) != _SUCCESS) - precvpriv->dbg_rx_drop_count++; + precvinfo->dbg_rx_drop_count++; /* Update local variables. */ bPktInBuf = _FALSE; @@ -3604,22 +3549,21 @@ static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ct } - /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, sp_flags); */ #if 0 /* Release the indication lock and set to new indication step. */ if (bPktInBuf) { /* Set new pending timer. */ /* pTS->RxIndicateState = RXTS_INDICATE_REORDER; */ - /* PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */ + /* PlatformSetTimer(adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); } else { /* pTS->RxIndicateState = RXTS_INDICATE_IDLE; */ } #endif - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, sp_flags); */ /* return _TRUE; */ return bPktInBuf; @@ -3628,20 +3572,17 @@ static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ct static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) { - _irqL irql; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; _queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE) goto _success_exit; - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); - _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); - + _rtw_spinlock_bh(&ppending_recvframe_queue->lock); if(rtw_test_and_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack)) preorder_ctrl->indicate_seq = 0xFFFF; @@ -3654,10 +3595,10 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram /* s2. check if winstart_b(indicate_seq) needs to been updated */ if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) { - precvpriv->dbg_rx_ampdu_drop_count++; + precvinfo->dbg_rx_ampdu_drop_count++; /* pHTInfo->RxReorderDropCounter++; */ - /* ReturnRFDList(Adapter, pRfd); */ - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* ReturnRFDList(adapter, pRfd); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, sp_flags); */ /* return _FAIL; */ #ifdef DBG_RX_DROP_FRAME @@ -3667,7 +3608,7 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram #if 0 rtw_recv_indicatepkt(padapter, prframe); - _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); goto _success_exit; #else @@ -3679,7 +3620,7 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram /* s3. Insert all packet into Reorder Queue to maintain its ordering. */ if (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) { /* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */ - /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_irq(&ppending_recvframe_queue->lock, sp_flags); */ /* return _FAIL; */ #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n" @@ -3705,10 +3646,10 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram preorder_ctrl->bReorderWaiting = _TRUE; _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); } - _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); } else { preorder_ctrl->bReorderWaiting = _FALSE; - _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); } @@ -3720,7 +3661,7 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram _err_exit: - _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); return _FAIL; } @@ -3728,7 +3669,6 @@ static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prfram void rtw_reordering_ctrl_timeout_handler(void *pcontext) { - _irqL irql; struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; _adapter *padapter = NULL; _queue *ppending_recvframe_queue = NULL; @@ -3738,25 +3678,73 @@ void rtw_reordering_ctrl_timeout_handler(void *pcontext) return; padapter = preorder_ctrl->padapter; - if (RTW_CANNOT_RUN(padapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) return; ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; /* RTW_INFO("+rtw_reordering_ctrl_timeout_handler()=>\n"); */ - _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinlock_bh(&ppending_recvframe_queue->lock); preorder_ctrl->bReorderWaiting = _FALSE; if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE) _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); - _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); } #endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) +int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe, struct rtw_recv_pkt *rx_req) +{ + int ret = _SUCCESS; + +#ifdef CONFIG_WIFI_MONITOR + struct net_device *ndev = padapter->pnetdev; + struct sk_buff *pskb = NULL; + + if (rframe == NULL) + goto exit; + + /* read skb information from recv frame */ + pskb = rframe->u.hdr.pkt; + pskb->len = rframe->u.hdr.len; + pskb->data = rframe->u.hdr.rx_data; + skb_set_tail_pointer(pskb, rframe->u.hdr.len); + + if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) { + /* fill radiotap header */ + if (rtw_fill_radiotap_hdr(padapter, &rframe->u.hdr.attrib, rx_req, (u8 *)pskb) == _FAIL) { + ret = _FAIL; + goto exit; + } + } + + /* write skb information to recv frame */ + skb_reset_mac_header(pskb); + rframe->u.hdr.len = pskb->len; + rframe->u.hdr.rx_data = pskb->data; + rframe->u.hdr.rx_head = pskb->head; + rframe->u.hdr.rx_tail = skb_tail_pointer(pskb); + rframe->u.hdr.rx_end = skb_end_pointer(pskb); + + if (!RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { + /* indicate this recv_frame */ + ret = rtw_recv_monitor(padapter, rframe); + } else + ret = _FAIL; + +exit: +#endif /* CONFIG_WIFI_MONITOR */ + + return ret; +} +#endif + +#if 0 static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller) { #if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) @@ -3789,6 +3777,7 @@ static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_n #endif } + #ifdef CONFIG_MP_INCLUDED int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) { @@ -3811,7 +3800,7 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) type = GetFrameType(ptr); subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ - RTW_DBG("hdr len = %d iv_len=%d \n", pattrib->hdrlen , pattrib->iv_len); + RTW_INFO("hdr len = %d iv_len=%d \n", pattrib->hdrlen , pattrib->iv_len); prx_data = ptr + pattrib->hdrlen + pattrib->iv_len; for (i = 0; i < precv_frame->u.hdr.len; i++) { @@ -3835,11 +3824,11 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) for (i = 0; i < precv_frame->u.hdr.len; i = i + 8) RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i), *(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7)); - RTW_INFO("#############################\n"); - _rtw_memset(pmppriv->mplink_buf, '\0' , sizeof(pmppriv->mplink_buf)); - _rtw_memcpy(pmppriv->mplink_buf, ptr, precv_frame->u.hdr.len); - pmppriv->mplink_rx_len = precv_frame->u.hdr.len; - pmppriv->mplink_brx =_TRUE; + RTW_INFO("#############################\n"); + _rtw_memset(pmppriv->mplink_buf, '\0' , sizeof(pmppriv->mplink_buf)); + _rtw_memcpy(pmppriv->mplink_buf, ptr, precv_frame->u.hdr.len); + pmppriv->mplink_rx_len = precv_frame->u.hdr.len; + pmppriv->mplink_brx =_TRUE; } } if (pmppriv->bloopback) { @@ -3877,31 +3866,55 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) { sint rmv_len; - u16 len; + u16 eth_type, len; + u8 bsnaphdr; + u8 *psnap_type; u8 mcastheadermac[] = {0x01, 0x00, 0x5e}; + + struct ieee80211_snap_hdr *psnap; + sint ret = _SUCCESS; - _adapter *adapter = precvframe->u.hdr.adapter; + _adapter *adapter = precvframe->u.hdr.adapter; u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; - enum rtw_rx_llc_hdl llc_hdl; if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); - llc_hdl = rtw_recv_llc_parse(ptr + pattrib->hdrlen + pattrib->iv_len - , precvframe->u.hdr.len - pattrib->hdrlen - pattrib->iv_len); + psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); + psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; + /* convert hdr + possible LLC headers into Ethernet header */ + /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ + if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) || + /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */ + _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + bsnaphdr = _TRUE; + } else { + /* Leave Ethernet header part of hdr and full payload */ + bsnaphdr = _FALSE; + } - rmv_len = pattrib->hdrlen + pattrib->iv_len + (llc_hdl ? SNAP_SIZE : 0); + rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; - ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0))); + + _rtw_memcpy(ð_type, ptr + rmv_len, 2); + eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ + pattrib->eth_type = eth_type; + + { + ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0))); + } _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); _rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN); - if (!llc_hdl) { + if (!bsnaphdr) { len = htons(len); _rtw_memcpy(ptr + 12, &len, 2); } @@ -3924,12 +3937,10 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) } - int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; - _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; #ifdef CONFIG_MP_INCLUDED struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mp_priv *pmppriv = &padapter->mppriv; @@ -3952,7 +3963,7 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) if (pmppriv->rx_bindicatePkt == _FALSE) { ret = _FAIL; - rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + rtw_free_recvframe(rframe);/* free this recv_frame */ goto exit; } else { type = GetFrameType(ptr); @@ -3980,16 +3991,18 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ret = sta2sta_data_frame(padapter, rframe, &psta); break; + case 1: - _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); - _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); - ret = sta2ap_data_frame(padapter, rframe, &psta); - break; - case 2: _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); ret = ap2sta_data_frame(padapter, rframe, &psta); break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2ap_data_frame(padapter, rframe, &psta); + break; case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); @@ -4019,7 +4032,7 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) ret = _FAIL; goto exit; } - if (!RTW_CANNOT_RUN(padapter)) { + if (!RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { /* indicate this recv_frame */ ret = rtw_recv_indicatepkt(padapter, rframe); if (ret != _SUCCESS) { @@ -4034,8 +4047,8 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" , FUNC_ADPT_ARG(padapter) - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False" + , dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False"); #endif ret = _FAIL; goto exit; @@ -4045,453 +4058,13 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) } } exit: - rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + rtw_free_recvframe(rframee);/* free this recv_frame */ ret = _FAIL; return ret; } #endif -static sint rtl8812au_fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe) -{ -#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a)) - -#if 0 - #define RTW_RX_RADIOTAP_PRESENT (\ - (1 << IEEE80211_RADIOTAP_TSFT) | \ - (1 << IEEE80211_RADIOTAP_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RATE) | \ - (1 << IEEE80211_RADIOTAP_CHANNEL) | \ - (0 << IEEE80211_RADIOTAP_FHSS) | \ - (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ - (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ - (0 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ - (0 << IEEE80211_RADIOTAP_TX_ATTENUATION) | \ - (0 << IEEE80211_RADIOTAP_DB_TX_ATTENUATION) | \ - (0 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ - (1 << IEEE80211_RADIOTAP_ANTENNA) | \ - (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ - (0 << IEEE80211_RADIOTAP_DB_ANTNOISE) | \ - (0 << IEEE80211_RADIOTAP_RX_FLAGS) | \ - (0 << IEEE80211_RADIOTAP_TX_FLAGS) | \ - (0 << IEEE80211_RADIOTAP_RTS_RETRIES) | \ - (0 << IEEE80211_RADIOTAP_DATA_RETRIES) | \ - (0 << IEEE80211_RADIOTAP_MCS) | \ - (0 << IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE)| \ - (0 << IEEE80211_RADIOTAP_VENDOR_NAMESPACE) | \ - (0 << IEEE80211_RADIOTAP_EXT) | \ - 0) - - /* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS) | \ */ - /* (0 << IEEE80211_RADIOTAP_VHT) | \ */ -#endif - -#ifndef IEEE80211_RADIOTAP_RX_FLAGS -#define IEEE80211_RADIOTAP_RX_FLAGS 14 -#endif - -#ifndef IEEE80211_RADIOTAP_MCS -#define IEEE80211_RADIOTAP_MCS 19 -#endif -#ifndef IEEE80211_RADIOTAP_VHT -#define IEEE80211_RADIOTAP_VHT 21 -#endif - -#ifndef IEEE80211_RADIOTAP_F_BADFCS -#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */ -#endif - - sint ret = _SUCCESS; - _adapter *adapter = precvframe->u.hdr.adapter; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - u16 tmp_16bit = 0; - - static u8 data_rate[] = { - 2, 4, 11, 22, /* CCK */ - 12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 2 */ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 3 */ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 4 */ - }; - - _pkt *pskb = NULL; - - struct ieee80211_radiotap_header *rtap_hdr = NULL; - u8 *ptr = NULL; - -#ifdef CONFIG_RADIOTAP_WITH_RXDESC - u8 hdr_buf[128] = {0}; -#else - u8 hdr_buf[64] = {0}; -#endif - u16 rt_len = 8; - u32 tmp_32bit; - int i; - - /* create header */ - rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0]; - rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION; - - if(pHalData->NumTotalRFPath>0 && pattrib->physt) { - rtap_hdr->it_present |= (1<NumTotalRFPath>1) { - tmp_32bit = (1<NumTotalRFPath-1; i++) { - memcpy(&hdr_buf[rt_len], &tmp_32bit, 4); - rt_len += 4; - } - } - tmp_32bit = (1<it_present |= (1 << IEEE80211_RADIOTAP_VENDOR_NAMESPACE); -#endif - } - - /* tsft */ - /*if (pattrib->tsfl) { - u64 tmp_64bit; - - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_TSFT); - tmp_64bit = cpu_to_le64(pattrib->tsfl); - memcpy(&hdr_buf[rt_len], &tmp_64bit, 8); - rt_len += 8; - }*/ - - /* flags */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_FLAGS); - if (0) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_CFP; - - if (0) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_SHORTPRE; - - if ((pattrib->encrypt == 1) || (pattrib->encrypt == 5)) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_WEP; - - if (pattrib->mfrag) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FRAG; - - /* always append FCS */ - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FCS; - - - if (0) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_DATAPAD; - - if (pattrib->crc_err) - hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_BADFCS; - - if (pattrib->sgi) { - /* Currently unspecified but used */ - hdr_buf[rt_len] |= 0x80; - } - rt_len += 1; - - /* rate */ - if (pattrib->data_rate < 12) { - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE); - if (pattrib->data_rate < 4) { - /* CCK */ - hdr_buf[rt_len] = data_rate[pattrib->data_rate]; - } else { - /* OFDM */ - hdr_buf[rt_len] = data_rate[pattrib->data_rate]; - } - } - rt_len += 1; /* force padding 1 byte for aligned */ - - /* channel */ - tmp_16bit = 0; - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL); - tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter)); - /*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/ - memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); - rt_len += 2; - - /* channel flags */ - tmp_16bit = 0; - if (pHalData->current_band_type == 0) - tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ); - else - tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); - - if (pattrib->data_rate < 12) { - if (pattrib->data_rate < 4) { - /* CCK */ - tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK); - } else { - /* OFDM */ - tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM); - } - } else - tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_DYN); - memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); - rt_len += 2; - - if(pattrib->physt) { - /* dBm Antenna Signal */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL); - hdr_buf[rt_len] = pattrib->phy_info.recv_signal_power; - rt_len += 1; - -#if 0 - /* dBm Antenna Noise */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE); - hdr_buf[rt_len] = 0; - rt_len += 1; -#endif - - rt_len++; // alignment - } - - /* Signal Quality */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY); - tmp_16bit = cpu_to_le16(pattrib->phy_info.signal_quality); - memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); - rt_len += 2; -#if 0 - /* Antenna */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_ANTENNA); - hdr_buf[rt_len] = pHalData->rf_type; - rt_len += 1; - - rt_len++; // alignment -#endif - /* RX flags */ - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RX_FLAGS); -#if 0 - tmp_16bit = cpu_to_le16(0); - memcpy(ptr, &tmp_16bit, 1); -#endif - rt_len += 2; - - /* MCS information */ - if (pattrib->data_rate >= 12 && pattrib->data_rate < 44) { - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS); - /* known, flag */ - hdr_buf[rt_len] |= BIT1; /* MCS index known */ - - /* bandwidth */ - hdr_buf[rt_len] |= BIT0; - hdr_buf[rt_len + 1] |= (pattrib->bw & 0x03); - - /* guard interval */ - hdr_buf[rt_len] |= BIT2; - hdr_buf[rt_len + 1] |= (pattrib->sgi & 0x01) << 2; - - /* STBC */ - hdr_buf[rt_len] |= BIT5; - hdr_buf[rt_len + 1] |= (pattrib->stbc & 0x03) << 5; - - rt_len += 2; - - /* MCS rate index */ - hdr_buf[rt_len] = data_rate[pattrib->data_rate]; - rt_len += 1; - } - - /* VHT */ - if (pattrib->data_rate >= 44 && pattrib->data_rate < 84) { - rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT); - - /* known 16 bit, flag 8 bit */ - tmp_16bit = 0; - - /* Bandwidth */ - tmp_16bit |= BIT6; - - /* Group ID */ - tmp_16bit |= BIT7; - - /* Partial AID */ - tmp_16bit |= BIT8; - - /* STBC */ - tmp_16bit |= BIT0; - hdr_buf[rt_len + 2] |= (pattrib->stbc & 0x01); - - /* Guard interval */ - tmp_16bit |= BIT2; - hdr_buf[rt_len + 2] |= (pattrib->sgi & 0x01) << 2; - - /* LDPC extra OFDM symbol */ - tmp_16bit |= BIT4; - hdr_buf[rt_len + 2] |= (pattrib->ldpc & 0x01) << 4; - - memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); - rt_len += 3; - - /* bandwidth */ - if (pattrib->bw == 0) - hdr_buf[rt_len] |= 0; - else if (pattrib->bw == 1) - hdr_buf[rt_len] |= 1; - else if (pattrib->bw == 2) - hdr_buf[rt_len] |= 4; - else if (pattrib->bw == 3) - hdr_buf[rt_len] |= 11; - rt_len += 1; - - /* mcs_nss */ - if (pattrib->data_rate >= 44 && pattrib->data_rate < 54) { - hdr_buf[rt_len] |= 1; - hdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 54 && pattrib->data_rate < 64) { - hdr_buf[rt_len + 1] |= 2; - hdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 64 && pattrib->data_rate < 74) { - hdr_buf[rt_len + 2] |= 3; - hdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 74 && pattrib->data_rate < 84) { - hdr_buf[rt_len + 3] |= 4; - hdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4; - } - rt_len += 4; - - /* coding */ - hdr_buf[rt_len] = 0; - rt_len += 1; - - /* group_id */ - hdr_buf[rt_len] = 0; - rt_len += 1; - - /* partial_aid */ - tmp_16bit = 0; - memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); - rt_len += 2; - } - - if (pattrib->physt) { - for(i=0; iNumTotalRFPath; i++) { - hdr_buf[rt_len] = pattrib->phy_info.rx_pwr[i]; - rt_len ++; - hdr_buf[rt_len] = i; - rt_len ++; - } - } - -#ifdef CONFIG_RADIOTAP_WITH_RXDESC - rt_len += rt_len&1; - hdr_buf[rt_len++] = 0xde; - hdr_buf[rt_len++] = 0xab; - hdr_buf[rt_len++] = 0xbe; - hdr_buf[rt_len++] = 0xaf; - hdr_buf[rt_len++] = 24; - hdr_buf[rt_len++] = 0; - _rtw_memcpy(hdr_buf + rt_len, pattrib->rxdesc, RXDESC_SIZE); - rt_len += RXDESC_SIZE; -#endif - - /* push to skb */ - /* read skb information from recv frame */ - pskb = precvframe->u.hdr.pkt; - pskb->len = precvframe->u.hdr.len; - pskb->data = precvframe->u.hdr.rx_data; - skb_set_tail_pointer(pskb, precvframe->u.hdr.len); - - if (skb_headroom(pskb) < rt_len) { - pskb = skb_realloc_headroom(pskb, rt_len); - if(pskb == NULL) { - RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__); - ret = _FAIL; - return ret; - } - precvframe->u.hdr.pkt = pskb; - } - - ptr = skb_push(pskb, rt_len); - if (ptr) { - rtap_hdr->it_len = cpu_to_le16(rt_len); - _rtw_memcpy(ptr, rtap_hdr, rt_len); - } else { - ret = _FAIL; - return ret; - } - out: - /* write skb information to recv frame */ - skb_reset_mac_header(pskb); - precvframe->u.hdr.len = pskb->len; - precvframe->u.hdr.rx_data = pskb->data; - precvframe->u.hdr.rx_head = pskb->head; - precvframe->u.hdr.rx_tail = skb_tail_pointer(pskb); - precvframe->u.hdr.rx_end = skb_end_pointer(pskb); - - return ret; -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) -int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) -{ - int ret = _SUCCESS; - _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; - -#ifdef CONFIG_WIFI_MONITOR - struct net_device *ndev = padapter->pnetdev; - _pkt *pskb = NULL; - - if (rframe == NULL) - goto exit; - - /* read skb information from recv frame */ - pskb = rframe->u.hdr.pkt; - pskb->len = rframe->u.hdr.len; - pskb->data = rframe->u.hdr.rx_data; - skb_set_tail_pointer(pskb, rframe->u.hdr.len); - - if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) { - /* fill radiotap header */ - /*if (rtw_fill_radiotap_hdr(padapter, &rframe->u.hdr.attrib, (u8 *)pskb) == _FAIL) { - ret = _FAIL; - goto exit; - }*/ - if (rtl8812au_fill_radiotap_hdr(padapter, rframe) == _FAIL) { - ret = _FAIL; - goto exit; - } - } - - /* write skb information to recv frame */ - skb_reset_mac_header(pskb); - rframe->u.hdr.len = pskb->len; - rframe->u.hdr.rx_data = pskb->data; - rframe->u.hdr.rx_head = pskb->head; - rframe->u.hdr.rx_tail = skb_tail_pointer(pskb); - rframe->u.hdr.rx_end = skb_end_pointer(pskb); - - if (!RTW_CANNOT_RUN(padapter)) { - /* indicate this recv_frame */ - ret = rtw_recv_monitor(padapter, rframe); - } else - ret = _FAIL; - -exit: -#endif /* CONFIG_WIFI_MONITOR */ - - if (rframe) /* free this recv_frame */ - rtw_free_recvframe(rframe, pfree_recv_queue); - - return ret; -} -#endif int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; @@ -4520,7 +4093,7 @@ int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) /* check the frame crtl field and decache */ ret = validate_recv_frame(padapter, rframe); if (ret != _SUCCESS) { - rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + rtw_free_recvframe(rframee);/* free this recv_frame */ goto exit; } } @@ -4534,7 +4107,7 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) int ret = _SUCCESS; union recv_frame *orig_prframe = prframe; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; #ifdef CONFIG_TDLS u8 *psnap_type, *pcategory; @@ -4617,7 +4190,7 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) /* including perform A-MPDU Rx Ordering Buffer Control */ ret = recv_indicatepkt_reorder(padapter, prframe); if (ret == _FAIL) { - rtw_free_recvframe(orig_prframe, pfree_recv_queue); + rtw_free_recvframe(orig_prframe); goto _recv_data_drop; } else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */ goto _exit_recv_func; @@ -4633,7 +4206,7 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) return ret; _recv_data_drop: - precvpriv->dbg_rx_drop_count++; + precvinfo->dbg_rx_drop_count++; return ret; } @@ -4644,16 +4217,12 @@ int recv_func(_adapter *padapter, union recv_frame *rframe) struct recv_priv *recvpriv = &padapter->recvpriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *mlmepriv = &padapter->mlmepriv; - u8 *ptr = rframe->u.hdr.rx_data; #ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL u8 type; + u8 *ptr = rframe->u.hdr.rx_data; #endif - if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE) -#ifdef RTW_SIMPLE_CONFIG - || (check_fwstate(mlmepriv, WIFI_AP_STATE) && padapter->rtw_simple_config == _TRUE && IS_MCAST(get_ra(ptr))) -#endif - ) { + if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) recv_frame_monitor(padapter, rframe); #endif @@ -4663,7 +4232,7 @@ int recv_func(_adapter *padapter, union recv_frame *rframe) #ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL type = GetFrameType(ptr); - if ((type == WIFI_DATA_TYPE)&& check_fwstate(mlmepriv, WIFI_STATION_STATE)) { + if ((type == WIFI_DATA_TYPE)&& MLME_IS_STA(padapter)) { struct wlan_network *cur_network = &(mlmepriv->cur_network); if ( _rtw_memcmp(get_addr2_ptr(ptr), cur_network->network.MacAddress, ETH_ALEN)==0) { recv_frame_monitor(padapter, rframe); @@ -4672,35 +4241,35 @@ int recv_func(_adapter *padapter, union recv_frame *rframe) } } #endif - /* check if need to handle uc_swdec_pending_queue*/ - if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) { - union recv_frame *pending_frame; - int cnt = 0; - - while ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) { - cnt++; - DBG_COUNTER(padapter->rx_logs.core_rx_dequeue); - recv_func_posthandle(padapter, pending_frame); - } - - if (cnt) - RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n", - FUNC_ADPT_ARG(padapter), cnt); + /* check if need to handle uc_swdec_pending_queue*/ + if (MLME_IS_STA(padapter) && psecuritypriv->busetkipkey) { + union recv_frame *pending_frame; + int cnt = 0; + + while ((pending_frame = rtw_alloc_recvframe(&recvpriv->uc_swdec_pending_queue))) { + cnt++; + DBG_COUNTER(padapter->rx_logs.core_rx_dequeue); + recv_func_posthandle(padapter, pending_frame); } + if (cnt) + RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n", + FUNC_ADPT_ARG(padapter), cnt); + } + DBG_COUNTER(padapter->rx_logs.core_rx); ret = recv_func_prehandle(padapter, rframe); if (ret == _SUCCESS) { /* check if need to enqueue into uc_swdec_pending_queue*/ - if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && + if (MLME_IS_STA(padapter) && !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 && (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) && psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK && !psecuritypriv->busetkipkey) { DBG_COUNTER(padapter->rx_logs.core_rx_enqueue); - rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue); + rtw_enqueue_recvframe(rframe, &recvpriv->uc_swdec_pending_queue); /* RTW_INFO("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); */ if (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) { @@ -4720,18 +4289,17 @@ int recv_func(_adapter *padapter, union recv_frame *rframe) return ret; } - s32 rtw_recv_entry(union recv_frame *precvframe) { _adapter *padapter; - struct recv_priv *precvpriv; + struct recv_info *precvinfo; s32 ret = _SUCCESS; padapter = precvframe->u.hdr.adapter; - precvpriv = &padapter->recvpriv; + precvinfo = &padapter->recvinfo; ret = recv_func(padapter, precvframe); @@ -4740,7 +4308,7 @@ s32 rtw_recv_entry(union recv_frame *precvframe) } - precvpriv->rx_pkts++; + precvinfo->rx_pkts++; return ret; @@ -4749,19 +4317,20 @@ s32 rtw_recv_entry(union recv_frame *precvframe) #ifdef CONFIG_MP_INCLUDED if (padapter->registrypriv.mp_mode == 1) - padapter->mppriv.rx_pktloss = precvpriv->rx_drop; + padapter->mppriv.rx_pktloss = precvinfo->rx_drop; #endif return ret; } +#endif -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS +#ifdef CONFIG_SIGNAL_STAT_PROCESS static void rtw_signal_stat_timer_hdl(void *ctx) { _adapter *adapter = (_adapter *)ctx; - struct recv_priv *recvpriv = &adapter->recvpriv; + struct recv_info *recvinfo = &adapter->recvinfo; u32 tmp_s, tmp_q; u8 avg_signal_strength = 0; @@ -4770,24 +4339,24 @@ static void rtw_signal_stat_timer_hdl(void *ctx) u32 num_signal_qual = 0; u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0; - if (adapter->recvpriv.is_signal_dbg) { + if (recvinfo->is_signal_dbg) { /* update the user specific value, signal_strength_dbg, to signal_strength, rssi */ - adapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg; - adapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg); + recvinfo->signal_strength = recvinfo->signal_strength_dbg; + recvinfo->rssi = (s8)rtw_phl_rssi_to_dbm((u8)recvinfo->signal_strength_dbg); } else { - if (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */ - avg_signal_strength = recvpriv->signal_strength_data.avg_val; - num_signal_strength = recvpriv->signal_strength_data.total_num; + if (recvinfo->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */ + avg_signal_strength = recvinfo->signal_strength_data.avg_val; + num_signal_strength = recvinfo->signal_strength_data.total_num; /* after avg_vals are accquired, we can re-stat the signal values */ - recvpriv->signal_strength_data.update_req = 1; + recvinfo->signal_strength_data.update_req = 1; } - if (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */ - avg_signal_qual = recvpriv->signal_qual_data.avg_val; - num_signal_qual = recvpriv->signal_qual_data.total_num; + if (recvinfo->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */ + avg_signal_qual = recvinfo->signal_qual_data.avg_val; + num_signal_qual = recvinfo->signal_qual_data.total_num; /* after avg_vals are accquired, we can re-stat the signal values */ - recvpriv->signal_qual_data.update_req = 1; + recvinfo->signal_qual_data.update_req = 1; } if (num_signal_strength == 0) { @@ -4806,9 +4375,8 @@ static void rtw_signal_stat_timer_hdl(void *ctx) if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY) == _TRUE) goto set_timer; #endif - if (adapter->registrypriv.mp_mode == 1) - ratio_profile = SIGNAL_STAT_CALC_PROFILE_2; - else if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX) + + if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX) ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE; ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0]; @@ -4816,25 +4384,25 @@ static void rtw_signal_stat_timer_hdl(void *ctx) ratio_total = ratio_pre_stat + ratio_curr_stat; /* update value of signal_strength, rssi, signal_qual */ - tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength); + tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvinfo->signal_strength); if (tmp_s % ratio_total) tmp_s = tmp_s / ratio_total + 1; else tmp_s = tmp_s / ratio_total; - if (tmp_s > 100) - tmp_s = 100; + if (tmp_s > PHL_MAX_RSSI) + tmp_s = PHL_MAX_RSSI; - tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual); + tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvinfo->signal_qual); if (tmp_q % ratio_total) tmp_q = tmp_q / ratio_total + 1; else tmp_q = tmp_q / ratio_total; - if (tmp_q > 100) - tmp_q = 100; + if (tmp_q > PHL_MAX_RSSI) + tmp_q = PHL_MAX_RSSI; - recvpriv->signal_strength = tmp_s; - recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s); - recvpriv->signal_qual = tmp_q; + recvinfo->signal_strength = tmp_s; + recvinfo->rssi = (s8)rtw_phl_rssi_to_dbm(tmp_s); + recvinfo->signal_qual = tmp_q; #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" @@ -4842,9 +4410,9 @@ static void rtw_signal_stat_timer_hdl(void *ctx) ", on_cur_ch_ms:%d" "\n" , FUNC_ADPT_ARG(adapter) - , recvpriv->signal_strength - , recvpriv->rssi - , recvpriv->signal_qual + , recvinfo->signal_strength + , recvinfo->rssi + , recvinfo->signal_qual , num_signal_strength, num_signal_qual , rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0 ); @@ -4852,157 +4420,550 @@ static void rtw_signal_stat_timer_hdl(void *ctx) } set_timer: - rtw_set_signal_stat_timer(recvpriv); + rtw_set_signal_stat_timer(recvinfo); } -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ +#endif/*CONFIG_SIGNAL_STAT_PROCESS*/ -static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) +/* +* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT +* @return _TRUE: +* @return _FALSE: +*/ +int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index) { - struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data; -#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - u32 last_rssi, tmp_val; -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - - /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */ - /* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */ - { -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - if (signal_stat->update_req) { - signal_stat->total_num = 0; - signal_stat->total_val = 0; - signal_stat->update_req = 0; - } - signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.signal_strength; - signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; -#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ + int ret = _FALSE; + int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]); - /* Adapter->RxStats.RssiCalculateCnt++; */ /* For antenna Test */ - if (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) { - padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX; - last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; - padapter->recvpriv.signal_strength_data.total_val -= last_rssi; - } - padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.signal_strength; + if (value >= MAX_CONTINUAL_NORXPACKET_COUNT) + ret = _TRUE; + + return ret; +} - padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength; - if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) - padapter->recvpriv.signal_strength_data.index = 0; +/* +* Set the continual_no_rx_packet of this @param pmlmepriv to 0 +*/ +void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) +{ + ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); +} +u8 adapter_allow_bmc_data_rx(_adapter *adapter) +{ + if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE) + return 1; - tmp_val = padapter->recvpriv.signal_strength_data.total_val / padapter->recvpriv.signal_strength_data.total_num; + if (MLME_IS_AP(adapter)) + return 0; - if (padapter->recvpriv.is_signal_dbg) { - padapter->recvpriv.signal_strength = padapter->recvpriv.signal_strength_dbg; - padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg); - } else { - padapter->recvpriv.signal_strength = tmp_val; - padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val); - } + if (rtw_linked_check(adapter) == _FALSE) + return 0; -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - } + return 1; } - -static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) +#if 0 +s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) { - struct rx_pkt_attrib *pattrib; -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - struct signal_stat *signal_stat; -#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - u32 last_evm = 0, tmpVal; -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ + s32 ret = _SUCCESS; + u8 *pbuf = precvframe->u.hdr.rx_data; + u8 *pda = get_ra(pbuf); + u8 ra_is_bmc = IS_MCAST(pda); + _adapter *primary_padapter = precvframe->u.hdr.adapter; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *iface = NULL; - if (prframe == NULL || padapter == NULL) - return; + #ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(primary_padapter)) + goto bypass_concurrent_hdl; + #endif - pattrib = &prframe->u.hdr.attrib; -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - signal_stat = &padapter->recvpriv.signal_qual_data; -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - - /* RTW_INFO("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */ - -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - if (signal_stat->update_req) { - signal_stat->total_num = 0; - signal_stat->total_val = 0; - signal_stat->update_req = 0; - } - - signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.signal_quality; - signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; - -#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - if (pattrib->phy_info.signal_quality != 0) { - /* */ - /* 1. Record the general EVM to the sliding window. */ - /* */ - if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) { - padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; - last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; - padapter->recvpriv.signal_qual_data.total_val -= last_evm; + if (ra_is_bmc == _FALSE) { /*unicast packets*/ + iface = rtw_get_iface_by_macddr(primary_padapter , pda); + if (NULL == iface) { + #ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if (_rtw_memcmp(pda, adapter_pno_mac_addr(primary_padapter), + ETH_ALEN) != _TRUE) + #endif + RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda)); + /*rtw_warn_on(1);*/ + } else { + precvframe->u.hdr.adapter = iface; } - padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality; - - padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality; - if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) - padapter->recvpriv.signal_qual_data.index = 0; - + } else { /* Handle BC/MC Packets*/ + rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status); + } +#ifdef CONFIG_MP_INCLUDED +bypass_concurrent_hdl: +#endif +#endif /* CONFIG_CONCURRENT_MODE */ + if (primary_padapter->registrypriv.mp_mode != 1) { + /* skip unnecessary bmc data frame for primary adapter */ + if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE + && !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter) + ) { + rtw_free_recvframe(precvframe); + goto exit; + } + } - /* <1> Showed on UI for user, in percentage. */ - tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num; - padapter->recvpriv.signal_qual = (u8)tmpVal; + if (pphy_status) { + rx_query_phy_status(precvframe, pphy_status); +#ifdef CONFIG_WIFI_MONITOR + rx_query_moinfo(&precvframe->u.hdr.attrib, pphy_status); +#endif } -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ + ret = rtw_recv_entry(precvframe); + +exit: + return ret; } +#endif + -void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe) +#ifdef CONFIG_RECV_THREAD_MODE +thread_return rtw_recv_thread(thread_context context) { - /* Check RSSI */ - rx_process_rssi(padapter, rframe); + _adapter *adapter = (_adapter *)context; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct recv_priv *recvpriv = &dvobj->recvpriv; + s32 err = _SUCCESS; +#ifdef RTW_RECV_THREAD_HIGH_PRIORITY +#ifdef PLATFORM_LINUX + struct sched_param param = { .sched_priority = 1 }; - /* Check PWDB */ - /* process_PWDB(padapter, rframe); */ + sched_setscheduler(current, SCHED_FIFO, ¶m); +#endif /* PLATFORM_LINUX */ +#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/ + rtw_thread_enter("RTW_RECV_THREAD"); - /* UpdateRxSignalStatistics8192C(Adapter, pRfd); */ + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); - /* Check EVM */ - rx_process_link_qual(padapter, rframe); - rtw_store_phy_info(padapter, rframe); -} + do { + err = _rtw_down_sema(&recvpriv->recv_sema); + if (_FAIL == err) { + RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter)); + goto exit; + } + + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) { + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(adapter), + dev_is_drv_stopped(adapter_to_dvobj(adapter)) ? "True" : "False", + dev_is_surprise_removed(adapter_to_dvobj(adapter)) ? "True" : "False"); + goto exit; + } + + err = rtw_intf_recv_hdl(adapter); + + if (err == RTW_RFRAME_UNAVAIL + || err == RTW_RFRAME_PKT_UNAVAIL + ) { + rtw_msleep_os(1); + _rtw_up_sema(&recvpriv->recv_sema); + } + + flush_signals_thread(); + + } while (err != _FAIL); + +exit: + + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); + + rtw_thread_wait_stop(); + + return 0; +} +#endif /* CONFIG_RECV_THREAD_MODE */ + +u8 rtw_init_lite_recv_resource(struct dvobj_priv *dvobj) +{ + u8 ret = _SUCCESS; + u32 literecvbuf_nr = RTW_LITERECVBUF_NR; + struct lite_data_buf *literecvbuf; + struct trx_data_buf_q *literecvbuf_q = &dvobj->literecvbuf_q; + int i; +#ifdef CONFIG_USB_HCI + struct data_urb *recvurb; + struct trx_urb_buf_q *recv_urb_q = &dvobj->recv_urb_q; + u32 recvurb_nr = RTW_RECVURB_NR; +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + struct lite_data_buf *intinbuf; + struct trx_data_buf_q *intin_buf_q = &dvobj->intin_buf_q; + u32 intin_buf_nr = RTW_INTINBUF_NR; + struct data_urb *intin_urb; + struct trx_urb_buf_q *intin_urb_q = &dvobj->intin_urb_q; + u32 intin_urb_nr = RTW_INTINURB_NR; +#endif +#endif + + /* init lite_recv_buf */ + _rtw_init_queue(&literecvbuf_q->free_data_buf_queue); + + literecvbuf_q->alloc_data_buf = + rtw_zvmalloc(literecvbuf_nr * sizeof(struct lite_data_buf) + 4); + + if (literecvbuf_q->alloc_data_buf == NULL) { + ret = _FAIL; + goto exit; + } + + literecvbuf_q->data_buf= + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(literecvbuf_q->alloc_data_buf), 4); + + literecvbuf = (struct lite_data_buf *)literecvbuf_q->data_buf; + + for (i = 0; i < literecvbuf_nr; i++) { + _rtw_init_listhead(&literecvbuf->list); + rtw_list_insert_tail(&literecvbuf->list, + &(literecvbuf_q->free_data_buf_queue.queue)); + literecvbuf++; + } + literecvbuf_q->free_data_buf_cnt = literecvbuf_nr; + + +#ifdef CONFIG_USB_HCI + /* init recv_urb */ + _rtw_init_queue(&recv_urb_q->free_urb_buf_queue); + recv_urb_q->alloc_urb_buf= + rtw_zvmalloc(recvurb_nr * sizeof(struct data_urb) + 4); + if (recv_urb_q->alloc_urb_buf== NULL) { + ret = _FAIL; + goto exit; + } + + recv_urb_q->urb_buf = + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(recv_urb_q->alloc_urb_buf), 4); + + recvurb = (struct data_urb *)recv_urb_q->urb_buf; + for (i = 0; i < recvurb_nr; i++) { + _rtw_init_listhead(&recvurb->list); + ret = rtw_os_urb_resource_alloc(recvurb); + rtw_list_insert_tail(&recvurb->list, + &(recv_urb_q->free_urb_buf_queue.queue)); + recvurb++; + } + recv_urb_q->free_urb_buf_cnt = recvurb_nr; + ATOMIC_SET(&(dvobj->rx_pending_cnt), 0); + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + + /* init int_in_buf */ + _rtw_init_queue(&intin_buf_q->free_data_buf_queue); + + intin_buf_q->alloc_data_buf = + rtw_zvmalloc(intin_buf_nr * sizeof(struct lite_data_buf) + 4); + + if (intin_buf_q->alloc_data_buf == NULL) { + ret = _FAIL; + goto exit; + } + + intin_buf_q->data_buf= + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(intin_buf_q->alloc_data_buf), 4); + + intinbuf = (struct lite_data_buf *)intin_buf_q->data_buf; + + for (i = 0; i < intin_buf_nr; i++) { + _rtw_init_listhead(&intinbuf->list); + rtw_list_insert_tail(&intinbuf->list, + &(intin_buf_q->free_data_buf_queue.queue)); + intinbuf++; + } + intin_buf_q->free_data_buf_cnt = intin_buf_nr; + + /* init int_in_urb */ + _rtw_init_queue(&intin_urb_q->free_urb_buf_queue); + intin_urb_q->alloc_urb_buf= + rtw_zvmalloc(intin_urb_nr * sizeof(struct data_urb) + 4); + if (intin_urb_q->alloc_urb_buf== NULL) { + ret = _FAIL; + goto exit; + } + + intin_urb_q->urb_buf = + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(intin_urb_q->alloc_urb_buf), 4); + + intin_urb = (struct data_urb *)intin_urb_q->urb_buf; + for (i = 0; i < intin_urb_nr; i++) { + _rtw_init_listhead(&intin_urb->list); + ret = rtw_os_urb_resource_alloc(intin_urb); + rtw_list_insert_tail(&intin_urb->list, + &(intin_urb_q->free_urb_buf_queue.queue)); + intin_urb++; + } + intin_urb_q->free_urb_buf_cnt = intin_urb_nr; +#endif +#endif + +exit: + return ret; +} + +void rtw_free_lite_recv_resource(struct dvobj_priv *dvobj) +{ + u8 ret = _SUCCESS; + u32 literecvbuf_nr = RTW_LITERECVBUF_NR; + struct lite_data_buf *literecvbuf; + struct trx_data_buf_q *literecvbuf_q = &dvobj->literecvbuf_q; + int i; +#ifdef CONFIG_USB_HCI + struct data_urb *recvurb; + struct trx_urb_buf_q *recv_urb_q = &dvobj->recv_urb_q; + u32 recvurb_nr = RTW_RECVURB_NR; +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + struct lite_data_buf *intinbuf; + struct trx_data_buf_q *intin_buf_q = &dvobj->intin_buf_q; + u32 intin_buf_nr = RTW_INTINBUF_NR; + struct data_urb *intin_urb; + struct trx_urb_buf_q *intin_urb_q = &dvobj->intin_urb_q; + u32 intin_urb_nr = RTW_INTINURB_NR; +#endif +#endif + + if (literecvbuf_q->alloc_data_buf) + rtw_vmfree(literecvbuf_q->alloc_data_buf, + literecvbuf_nr * sizeof(struct lite_data_buf) + 4); + +#ifdef CONFIG_USB_HCI + recvurb = (struct data_urb *)recv_urb_q->urb_buf; + for (i = 0; i < recvurb_nr; i++) { + rtw_os_urb_resource_free(recvurb); + recvurb++; + } + + if (recv_urb_q->alloc_urb_buf) + rtw_vmfree(recv_urb_q->alloc_urb_buf, + recvurb_nr * sizeof(struct data_urb) + 4); + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + + if (intin_buf_q->alloc_data_buf) + rtw_vmfree(intin_buf_q->alloc_data_buf, + intin_buf_nr * sizeof(struct lite_data_buf) + 4); + + intin_urb = (struct data_urb *)intin_urb_q->urb_buf; + for (i = 0; i < intin_urb_nr; i++) { + rtw_os_urb_resource_free(intin_urb); + intin_urb++; + } + + if (intin_urb_q->alloc_urb_buf) + rtw_vmfree(intin_urb_q->alloc_urb_buf, + intin_urb_nr * sizeof(struct data_urb) + 4); +#endif +#endif -void rx_query_phy_status( - union recv_frame *precvframe, - u8 *pphy_status) +} + +#ifdef RTW_PHL_RX +void rx_dump_skb(struct sk_buff *skb) +{ + int idx=0; + u8 *tmp=skb->data; + printk("==="); + printk("[%s]skb=%p len=%d\n", __FUNCTION__, skb, skb->len); + +#if 0 + printk("data-tail=0x%x-0x%x(%d)\n", + skb->data, skb->tail, (skb->tail - skb->data)); + printk("head-end=0x%x-0x%x(%d)\n", + skb->head, skb->end, (skb->end - skb->head)); +#endif + + for(idx=0; idxlen; idx++){ + printk("%02x ", tmp[idx]); + if(idx%20==19) + printk("\n"); + } + printk("\n===\n"); +} + +void dump_rxreq(_adapter *adapter, union recv_frame *prframe) +{ + + +} + +void dump_recv_frame(_adapter *adapter, union recv_frame *prframe) +{ + struct recv_frame_hdr *hdr = &(prframe->u.hdr); + struct rx_pkt_attrib *rxattr = &(prframe->u.hdr.attrib); + + printk("[%s]prframe=0x%p len=%d\n", __FUNCTION__, prframe, hdr->len); + + printk("head-tail=0x%p-0x%p\n", hdr->rx_head, hdr->rx_tail); + printk("data-end=0x%p-0x%p\n", hdr->rx_data, hdr->rx_end); + + printk("dst=%pM\n", rxattr->dst); + printk("src=%pM\n", rxattr->src); + printk("ra=%pM\n", rxattr->ra); + printk("ta=%pM\n", rxattr->ta); + printk("bssid=%pM\n", rxattr->bssid); +} + +void core_update_recvframe_pkt( union recv_frame *prframe, struct rtw_recv_pkt *rx_req) +{ + struct rtw_pkt_buf_list *pkt = rx_req->pkt_list; + struct sk_buff *skb = prframe->u.hdr.pkt; + + skb_reserve(skb, pkt->vir_addr - skb->data); + skb_put(skb, pkt->length); + + prframe->u.hdr.rx_data = skb->data; + prframe->u.hdr.rx_tail = skb_tail_pointer(skb); + prframe->u.hdr.len = skb->len; + prframe->u.hdr.rx_head = skb->head; + prframe->u.hdr.rx_end = skb_end_pointer(skb); + + return; +} + +static int core_alloc_recvframe_pkt(union recv_frame *prframe, + struct rtw_recv_pkt *phlrx) +{ + struct rtw_pkt_buf_list *pktbuf; + u8 shift_sz; + u32 alloc_sz; + struct sk_buff *pkt = NULL; + u8 *pbuf = NULL; + + + rtw_warn_on(phlrx->pkt_cnt > 1); + pktbuf = phlrx->pkt_list; /* &phlrx->pkt_list[0] */ + + /* For 8 bytes IP header alignment. */ + if (phlrx->mdata.qos) + /* Qos data, wireless lan header length is 26 */ + shift_sz = 6; + else + shift_sz = 0; + + /* + * For first fragment packet, driver need allocate 1536 to + * defrag packet. + * And need 8 is for skb->data 8 bytes alignment. + * Round (1536 + shift_sz + 8) to 128 bytes alignment, + * and finally get 1664. + */ + alloc_sz = pktbuf->length; + if ((phlrx->mdata.more_frag == 1) && (phlrx->mdata.frag_num == 0)) { + if (alloc_sz <= 1650) + alloc_sz = 1664; + else + alloc_sz += 14; + } else { + /* + * 6 is for IP header 8 bytes alignment in QoS packet case. + * 8 is for skb->data 4 bytes alignment. + */ + alloc_sz += 14; + } + + pkt = rtw_skb_alloc(alloc_sz); + if (!pkt) { + RTW_ERR("%s: alloc skb fail! sz=%u (mfrag=%u, frag_num=%u)\n", + __FUNCTION__, alloc_sz, phlrx->mdata.more_frag, + phlrx->mdata.frag_num); + return -1; + } + + /* force pkt->data at 8-byte alignment address */ + skb_reserve(pkt, 8 - ((SIZE_PTR)pkt->data & 7)); + /* force ip_hdr at 8-byte alignment address according to shift_sz. */ + skb_reserve(pkt, shift_sz); + pbuf = skb_put(pkt, pktbuf->length); + _rtw_memcpy(pbuf, pktbuf->vir_addr, pktbuf->length); + + prframe->u.hdr.pkt = pkt; + prframe->u.hdr.rx_data = pkt->data; + prframe->u.hdr.rx_tail = skb_tail_pointer(pkt); + prframe->u.hdr.len = pkt->len; + prframe->u.hdr.rx_head = pkt->head; + prframe->u.hdr.rx_end = skb_end_pointer(pkt); + + return 0; +} + +void core_update_recvframe_mdata(union recv_frame *prframe, struct rtw_recv_pkt *rx_req) +{ + struct rx_pkt_attrib *prxattrib = &prframe->u.hdr.attrib; + struct rtw_r_meta_data *mdata = &rx_req->mdata; + + prxattrib->bdecrypted = !(mdata->sw_dec); + prxattrib->pkt_len = mdata->pktlen; + prxattrib->icv_err = mdata->icverr; + prxattrib->crc_err = mdata->crc32; +#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX + prxattrib->csum_valid = mdata->chksum_ofld_en; + prxattrib->csum_err = mdata->chksum_status; +#endif + /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ + prxattrib->encrypt = rtw_sec_algo_phl2drv((enum rtw_enc_algo)mdata->sec_type); + +#if 0 //todo +//Security (sw-decrypt & calculate payload offset) + u8 bdecrypted; + u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ + u8 iv_len; + u8 icv_len; + u8 crc_err; + u8 icv_err; +#endif + + + return; +} + +#ifdef RTW_WKARD_CORE_RSSI_V1 +static inline void _rx_process_ss_sq(_adapter *padapter, union recv_frame *prframe) { - PADAPTER padapter = precvframe->u.hdr.adapter; - struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info; - u8 *wlanhdr; - struct phydm_perpkt_info_struct pkt_info; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct signal_stat *ss = &padapter->recvinfo.signal_strength_data; + struct signal_stat *sq = &padapter->recvinfo.signal_qual_data; + + if (ss->update_req) { + ss->total_num = 0; + ss->total_val = 0; + ss->update_req = 0; + } + + ss->total_num++; + ss->total_val += pattrib->phy_info.signal_strength; + ss->avg_val = ss->total_val / ss->total_num; + + if (sq->update_req) { + sq->total_num = 0; + sq->total_val = 0; + sq->update_req = 0; + } + + sq->total_num++; + sq->total_val += pattrib->phy_info.signal_quality; + sq->avg_val = sq->total_val / sq->total_num; +} + +/*#define DBG_RECV_INFO*/ +void rx_process_phy_info(union recv_frame *precvframe) +{ + _adapter *padapter = precvframe->u.hdr.adapter; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + struct phydm_phyinfo_struct *phy_info = &pattrib->phy_info; + u8 *wlanhdr = NULL; u8 *ta, *ra; u8 is_ra_bmc; struct sta_priv *pstapriv; struct sta_info *psta = NULL; - struct recv_priv *precvpriv = &padapter->recvpriv; - /* _irqL irqL; */ - - pkt_info.is_packet_match_bssid = _FALSE; - pkt_info.is_packet_to_self = _FALSE; - pkt_info.is_packet_beacon = _FALSE; - pkt_info.ppdu_cnt = pattrib->ppdu_cnt; - pkt_info.station_id = 0xFF; + struct recv_info *precvinfo = &padapter->recvinfo; - wlanhdr = get_recvframe_data(precvframe); + bool is_packet_match_bssid = _FALSE; + bool is_packet_to_self = _FALSE; + bool is_packet_beacon = _FALSE; + wlanhdr = precvframe->u.hdr.rx_data; ta = get_ta(wlanhdr); ra = get_ra(wlanhdr); is_ra_bmc = IS_MCAST(ra); @@ -5010,7 +4971,7 @@ void rx_query_phy_status( if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) { static systime start_time = 0; -#if 0 /*For debug */ + #if 0 /*For debug */ if (IsFrameTypeCtrl(wlanhdr)) { RTW_INFO("-->Control frame: Y\n"); RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len); @@ -5024,325 +4985,497 @@ void rx_query_phy_status( RTW_INFO("%d: %X\n", i, *((u8 *)wlanhdr + i)); RTW_INFO("\n"); -#endif + #endif if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) { - RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__); + RTW_ERR("Warning!!! %s: Confilc mac addr!!\n", __func__); start_time = rtw_get_current_time(); } - precvpriv->dbg_rx_conflic_mac_addr_cnt++; - } else { - pstapriv = &padapter->stapriv; - psta = rtw_get_stainfo(pstapriv, ta); - if (psta) - pkt_info.station_id = psta->cmn.mac_id; + precvinfo->dbg_rx_conflic_mac_addr_cnt++; + return; } - pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) - && (!pattrib->icv_err) && (!pattrib->crc_err) - && ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN)) - || (MLME_IS_MESH(padapter) && psta)); + pstapriv = &padapter->stapriv; + psta = rtw_get_stainfo(pstapriv, ta); - pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) - && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) + && (!pattrib->icv_err) && (!pattrib->crc_err) + && ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN)) + || (MLME_IS_MESH(padapter) && psta)); - pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid - && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + /*is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);*/ - pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid - && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); + is_packet_to_self = is_packet_match_bssid + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); - if (psta && IsFrameTypeData(wlanhdr) - && !(get_frame_sub_type(wlanhdr) & BIT(6)) /* don't count NULL data */ - ) { + is_packet_beacon = is_packet_match_bssid + && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); + + if (psta && IsFrameTypeData(wlanhdr)) { if (is_ra_bmc) psta->curr_rx_rate_bmc = pattrib->data_rate; else psta->curr_rx_rate = pattrib->data_rate; } - pkt_info.data_rate = pattrib->data_rate; - - odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info); + #if 0 /* If bw is initial value, get from phy status */ if (pattrib->bw == CHANNEL_WIDTH_MAX) pattrib->bw = p_phy_info->band_width; + #endif +#ifdef DBG_RECV_INFO + RTW_INFO("%s match_bssid:%d, to_self:%d, is_beacon:%d", + __func__, is_packet_match_bssid, is_packet_to_self, is_packet_beacon); - if (p_phy_info->physts_rpt_valid == _TRUE) { - precvframe->u.hdr.psta = NULL; - if (padapter->registrypriv.mp_mode != 1) { - if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid) - || (MLME_IS_MESH(padapter) && psta)) { - if (psta) { - precvframe->u.hdr.psta = psta; - rx_process_phy_info(padapter, precvframe); - } - } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) { + RTW_INFO("hdr_bssid:"MAC_FMT" my_bssid:"MAC_FMT"\n", + MAC_ARG(get_hdr_bssid(wlanhdr)), + MAC_ARG(get_bssid(&padapter->mlmepriv))); + + RTW_INFO("ra:"MAC_FMT" my_addr:"MAC_FMT"\n", + MAC_ARG(ra), + MAC_ARG(adapter_mac_addr(padapter))); + +#endif + precvframe->u.hdr.psta = NULL; + if (padapter->registrypriv.mp_mode != 1) { + if ((!MLME_IS_MESH(padapter) && is_packet_match_bssid) + || (MLME_IS_MESH(padapter) && psta)) { + if (psta) + precvframe->u.hdr.psta = psta; + if (phy_info->is_valid) + _rx_process_ss_sq(padapter, precvframe);/*signal_strength & signal_quality*/ + } else if (is_packet_to_self || is_packet_beacon) { + if (psta) + precvframe->u.hdr.psta = psta; + if (phy_info->is_valid) + _rx_process_ss_sq(padapter, precvframe);/*signal_strength & signal_quality*/ + } + } + #if 0 + #ifdef CONFIG_MP_INCLUDED + else { + #ifdef CONFIG_MP_INCLUDED + if (padapter->mppriv.brx_filter_beacon == _TRUE) { + if (is_packet_beacon) { + RTW_INFO("in MP Rx is_packet_beacon\n"); if (psta) precvframe->u.hdr.psta = psta; - rx_process_phy_info(padapter, precvframe); - } - } else { -#ifdef CONFIG_MP_INCLUDED - if (padapter->mppriv.brx_filter_beacon == _TRUE) { - if (pkt_info.is_packet_beacon) { - RTW_INFO("in MP Rx is_packet_beacon\n"); - if (psta) - precvframe->u.hdr.psta = psta; - rx_process_phy_info(padapter, precvframe); - } - } else -#endif - { - if (psta) - precvframe->u.hdr.psta = psta; - rx_process_phy_info(padapter, precvframe); + _rx_process_ss_sq(padapter, precvframe); } + } else + #endif + { + if (psta) + precvframe->u.hdr.psta = psta; + _rx_process_ss_sq(padapter, precvframe); } } - - rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status); + #endif + #endif } -/* -* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT -* @return _TRUE: -* @return _FALSE: -*/ -int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index) + + +/*#define DBG_PHY_INFO*/ +void core_update_recvframe_phyinfo(union recv_frame *prframe, struct rtw_recv_pkt *rx_req) { + struct rx_pkt_attrib *attrib = &prframe->u.hdr.attrib; + struct rtw_phl_ppdu_phy_info *phy_info = &rx_req->phy_info; + u8 ptype, pstype; - int ret = _FALSE; - int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]); + _rtw_memset(&attrib->phy_info, 0, sizeof(struct phydm_phyinfo_struct)); - if (value >= MAX_CONTINUAL_NORXPACKET_COUNT) - ret = _TRUE; + ptype = phy_info->frame_type & 0x03; + pstype = phy_info->frame_type >> 2; - return ret; + #ifdef DBG_PHY_INFO + { + u8 type, subtype; + u8 *ptr = prframe->u.hdr.rx_data; + + type = GetFrameType(ptr) >> 2; + subtype = get_frame_sub_type(ptr) >> 4; /* bit(7)~bit(2) */ + if ((type != WIFI_CTRL_TYPE) && (ptype != type || pstype != subtype)) { + RTW_INFO("[DBG-PHY-INFO]- FT:0x%02x, FST:0x%02x\t", type, subtype); + RTW_INFO("A1:"MAC_FMT" A2:"MAC_FMT" A3:"MAC_FMT"\n", + MAC_ARG(GetAddr1Ptr(ptr)), + MAC_ARG(get_addr2_ptr(ptr)), + MAC_ARG(GetAddr3Ptr(ptr))); + } + } + #endif + + if (phy_info->is_valid) { + attrib->phy_info.is_valid = true; + attrib->phy_info.signal_strength = phy_info->rssi; + attrib->phy_info.signal_quality = phy_info->rssi; + attrib->phy_info.recv_signal_power = rtw_phl_rssi_to_dbm(phy_info->rssi); + attrib->ch = phy_info->ch_idx; + + #ifdef DBG_PHY_INFO + RTW_INFO("[PHY-INFO] ft:0x%02x-0x%02x rssi:%d, ch_idx:%d, tx_bf:%d\n", + ptype, pstype, phy_info->rssi, phy_info->ch_idx, phy_info->tx_bf); + + RTW_INFO("[PHY-INFO] ss:%d sq:%d rssi:%d\n", + attrib->phy_info.signal_strength, + attrib->phy_info.signal_quality, + attrib->phy_info.recv_signal_power); + #endif + + } else { + #ifdef DBG_PHY_INFO + RTW_INFO("[PHY-INFO-INVALID] ftype:0x%02x-0x%02x rssi:%d, ch_idx:%d, tx_bf:%d\n", + ptype, pstype, phy_info->rssi, phy_info->ch_idx, phy_info->tx_bf); + #endif + } } +#endif /*RTW_WKARD_CORE_RSSI_V1*/ -/* -* Set the continual_no_rx_packet of this @param pmlmepriv to 0 -*/ -void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) +s32 core_rx_process_amsdu(_adapter *adapter, union recv_frame *prframe) { - ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); + if(amsdu_to_msdu(adapter, prframe) != _SUCCESS) + return CORE_RX_DROP; + + return CORE_RX_DONE; } -u8 adapter_allow_bmc_data_rx(_adapter *adapter) +s32 core_rx_process_msdu(_adapter *adapter, union recv_frame *prframe) { - if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE) - return 1; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + u8 *msdu = get_recvframe_data(prframe) + + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib); + u16 msdu_len = prframe->u.hdr.len + - pattrib->hdrlen - pattrib->iv_len - RATTRIB_GET_MCTRL_LEN(pattrib) + - (pattrib->encrypt ? pattrib->icv_len : 0); + enum rtw_rx_llc_hdl llc_hdl = rtw_recv_llc_parse(msdu, msdu_len); + int act = RTW_RX_MSDU_ACT_INDICATE; -#ifdef RTW_SIMPLE_CONFIG - /* allow AP to receive multicast packet for RtwSimpleConfigV4 */ - if (MLME_IS_AP(adapter) && adapter->rtw_simple_config) - return 1; -#endif +#if defined(CONFIG_AP_MODE) + struct xmit_frame *fwd_frame = NULL; + _list f_list; if (MLME_IS_AP(adapter)) - return 0; + act = rtw_ap_rx_msdu_act_check(prframe, pattrib->dst, pattrib->src + , msdu, llc_hdl, &fwd_frame, &f_list); + if (!act) + return CORE_RX_DROP; +#endif - if (rtw_linked_check(adapter) == _FALSE) - return 0; + if(wlanhdr_to_ethhdr(prframe, llc_hdl) != _SUCCESS) { + if (act & RTW_RX_MSDU_ACT_INDICATE) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif + } - return 1; + #if defined(CONFIG_AP_MODE) + if (act & RTW_RX_MSDU_ACT_FORWARD) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__); + #endif + recv_free_fwd_resource(adapter, fwd_frame, &f_list); + } + #endif + return CORE_RX_DROP; + } + + #if defined(CONFIG_AP_MODE) + if (act & RTW_RX_MSDU_ACT_FORWARD) { + recv_fwd_pkt_hdl(adapter, prframe->u.hdr.pkt, act, fwd_frame, &f_list); + if (!(act & RTW_RX_MSDU_ACT_INDICATE)) { + prframe->u.hdr.pkt = NULL; + rtw_free_recvframe(prframe); + return CORE_RX_DONE; + } + } + #endif + + if(rtw_recv_indicatepkt_check(prframe, + get_recvframe_data(prframe), get_recvframe_len(prframe)) != _SUCCESS) + return CORE_RX_DROP; + + if(rtw_recv_indicatepkt(adapter, prframe) != _SUCCESS) + return CORE_RX_DROP; + + return CORE_RX_DONE; } -s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) + +s32 rtw_core_rx_data_post_process(_adapter *adapter, union recv_frame *prframe) { - s32 ret = _SUCCESS; - u8 *pbuf = precvframe->u.hdr.rx_data; - u8 *ra = get_ra(pbuf); - u8 ra_is_bmc = IS_MCAST(ra); - bool phy_queried = 0; - _adapter *primary_padapter = precvframe->u.hdr.adapter; - _adapter *iface = NULL; + //amsdu + //make eth hdr + //forward -#ifdef CONFIG_MP_INCLUDED - if (rtw_mp_mode_check(primary_padapter)) - goto query_phy_status; + //recv_process_mpdu + //amsdu_to_msdu + //wlanhdr_to_ethhdr + //rtw_recv_indicatepkt_check + //rtw_recv_indicatepkt + + +//todo hw amsdu + if (prframe->u.hdr.attrib.amsdu) + return core_rx_process_amsdu(adapter, prframe); + else + return core_rx_process_msdu(adapter, prframe); + +} + + +s32 rtw_core_rx_data_pre_process(_adapter *adapter, union recv_frame **prframe) +{ + //recv_func_posthandle + //decryptor + //portctrl + //count_rx_stats +#ifdef CONFIG_TDLS #endif -#ifdef CONFIG_WIFI_MONITOR - if (MLME_IS_MONITOR(primary_padapter)) - goto query_phy_status; +#ifdef DBG_RX_BMC_FRAME +#endif +#ifdef CONFIG_WAPI_SUPPORT #endif - if (ra_is_bmc == _FALSE) { - /* UC frame */ - iface = rtw_get_iface_by_macddr(primary_padapter , ra); - if (!iface) { - #if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) + union recv_frame * ret_frame = NULL; + + s32 ret = CORE_RX_CONTINUE; + + ret_frame = decryptor(adapter, *prframe); + if (ret_frame == NULL) + return CORE_RX_DROP; + else + *prframe = ret_frame; + + ret = recvframe_chk_defrag(adapter, prframe); + if (ret != CORE_RX_CONTINUE) { + if (ret == CORE_RX_DROP) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif + DBG_COUNTER(adapter->rx_logs.core_rx_post_defrag_err); + } + return ret; + } + + /* Rx TKIP MIC */ + if ((*prframe)->u.hdr.attrib.privacy) { + if (recvframe_chkmic(adapter, *prframe) == _FAIL) { + return CORE_RX_DROP; + } + } + + ret_frame = portctrl(adapter, *prframe); + if (ret_frame == NULL) + return CORE_RX_DROP; + else + *prframe = ret_frame; + + count_rx_stats(adapter, *prframe, NULL); + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_update_info(adapter, *prframe); +#endif + + return CORE_RX_CONTINUE; +} + +s32 rtw_core_update_recvframe(struct dvobj_priv *dvobj, + union recv_frame *prframe, struct rtw_recv_pkt *rx_req) +{ + u8 *pbuf = NULL; + u8 *pda = NULL; + _adapter *iface = NULL; + u8 is_bmc = _FALSE; + enum rtw_core_rx_state rx_state = CORE_RX_CONTINUE; + _adapter *primary_padapter = dvobj_get_primary_adapter(dvobj); + int err; + struct mlme_priv *pmlmepriv = NULL; + + if (rx_req->mdata.bc || rx_req->mdata.mc) + is_bmc = _TRUE; + + //pre_recv_entry + //rtw_get_iface_by_macddr + if (rx_req->os_priv) { + prframe->u.hdr.pkt = rx_req->os_priv; /*skb*/ + core_update_recvframe_pkt(prframe, rx_req); + } else { + err = core_alloc_recvframe_pkt(prframe, rx_req); + if (err) { + rx_state = CORE_RX_FAIL; + goto exit; + } + } + + core_update_recvframe_mdata(prframe, rx_req); + #ifdef RTW_WKARD_CORE_RSSI_V1 + core_update_recvframe_phyinfo(prframe, rx_req); + #endif + + prframe->u.hdr.adapter = primary_padapter; + prframe->u.hdr.pkt->dev = primary_padapter->pnetdev; + + if (!is_bmc) { + pbuf = prframe->u.hdr.rx_data; + pda = get_ra(pbuf); + iface = rtw_get_iface_by_macddr(primary_padapter, pda); + if(iface) { + prframe->u.hdr.adapter = iface; + prframe->u.hdr.pkt->dev = iface->pnetdev; + } + else { + #if 0 /*#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI - TODO*/ if (_rtw_memcmp(ra, adapter_pno_mac_addr(primary_padapter), ETH_ALEN)) - goto query_phy_status; + goto query_phy_status; #endif #ifdef CONFIG_RTW_MULTI_AP /* unasoc STA RCPI */ - if (rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC)) { - if (pphy_status) { - rx_query_phy_status(precvframe, pphy_status); - rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC, get_ta(pbuf) - , precvframe->u.hdr.attrib.phy_info.recv_signal_power); - } + if (rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC) && + prframe->u.hdr.attrib.phy_info.recv_signal_power != 0) { + rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC, + get_ta(pbuf), prframe->u.hdr.attrib.phy_info.recv_signal_power); } else #endif - RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n" - , __func__, MAC_ARG(ra)); - - rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue); - goto exit; + RTW_DBG("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n" + , __func__, MAC_ARG(pda)); + rx_state = CORE_RX_FAIL; } - #ifdef CONFIG_CONCURRENT_MODE - else - precvframe->u.hdr.adapter = iface; - #endif - - } else { - /* BMC frame */ - #ifdef CONFIG_CONCURRENT_MODE - rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status); - #endif + } + else { + /*clone bcmc frame for all active adapter*/ + rtw_mi_buddy_clone_bcmc_packet(primary_padapter, prframe); #ifdef CONFIG_RTW_MULTI_AP + pbuf = prframe->u.hdr.rx_data; /* unasoc STA RCPI */ - if (pphy_status - && rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_BMC) - ) { - phy_queried = 1; - rx_query_phy_status(precvframe, pphy_status); - rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_BMC, get_ta(pbuf) - , precvframe->u.hdr.attrib.phy_info.recv_signal_power); + if (rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_BMC) && + prframe->u.hdr.attrib.phy_info.recv_signal_power != 0) { + rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_BMC, + get_ta(pbuf), prframe->u.hdr.attrib.phy_info.recv_signal_power); } #endif - - /* skip unnecessary BMC data frame for primary adapter */ - if (GetFrameType(pbuf) == WIFI_DATA_TYPE - && !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter) - ) { - rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue); - goto exit; - } } -#if defined(CONFIG_MP_INCLUDED) || defined(CONFIG_WIFI_MONITOR) || defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) -query_phy_status: + +exit: + prframe->u.hdr.rx_req = rx_req; + + pmlmepriv = &(prframe->u.hdr.adapter)->mlmepriv; + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) + recv_frame_monitor(prframe->u.hdr.adapter, prframe, rx_req); #endif - if (pphy_status) { - if (!phy_queried) - rx_query_phy_status(precvframe, pphy_status); - #ifdef CONFIG_WIFI_MONITOR - if (MLME_IS_MONITOR(primary_padapter)) - rx_query_moinfo(&precvframe->u.hdr.attrib, pphy_status); - #endif + rx_state = CORE_RX_FAIL; } - ret = rtw_recv_entry(precvframe); - -exit: - return ret; + return rx_state; } -#ifdef CONFIG_RECV_THREAD_MODE -thread_return rtw_recv_thread(thread_context context) +#ifdef CONFIG_RTW_NAPI +#ifdef CONFIG_RTW_NAPI_V2 +static void rtw_core_rx_napi_v2(struct dvobj_priv *dvobj) { - _adapter *adapter = (_adapter *)context; - struct recv_priv *recvpriv = &adapter->recvpriv; - s32 err = _SUCCESS; -#ifdef RTW_RECV_THREAD_HIGH_PRIORITY -#ifdef PLATFORM_LINUX - struct sched_param param = { .sched_priority = 1 }; - - sched_setscheduler(current, SCHED_FIFO, ¶m); -#endif /* PLATFORM_LINUX */ -#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/ - thread_enter("RTW_RECV_THREAD"); - - RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); - - do { - err = _rtw_down_sema(&recvpriv->recv_sema); - if (_FAIL == err) { - RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter)); - goto exit; - } - - if (RTW_CANNOT_RUN(adapter)) { - RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", - FUNC_ADPT_ARG(adapter), - rtw_is_drv_stopped(adapter) ? "True" : "False", - rtw_is_surprise_removed(adapter) ? "True" : "False"); - goto exit; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + struct recv_priv *recvpriv = &dvobj->recvpriv; + + if (adapter->registrypriv.en_napi) { + _adapter *a; + u8 i; + + for (i = 0; i < dvobj->iface_nums; i++) { + a = dvobj->padapters[i]; + if ((rtw_if_up(a) == _TRUE) + && skb_queue_len(&recvpriv->rx_napi_skb_queue)) + napi_schedule(&a->napi); } + } +} +#endif +#endif - err = rtw_hal_recv_hdl(adapter); +enum rtw_phl_status rtw_core_rx_process(void *drv_priv) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)drv_priv; + _adapter *adapter = NULL; + struct rtw_recv_pkt *rx_req = NULL; + struct rtw_pkt_buf_list *pkt = NULL; + union recv_frame *prframe = NULL; + struct rx_pkt_attrib *prxattrib = NULL; + u16 rx_pkt_num = 0; + struct recv_priv *precvpriv = &dvobj->recvpriv; + s32 pre_process_ret = CORE_RX_CONTINUE; + + rx_pkt_num = rtw_phl_query_new_rx_num(GET_PHL_INFO(dvobj)); + +#ifdef DBG_RECV_FRAME + RTW_INFO("%s dvobj:%p, phl:%p rx_pkt_num:%d, free_recv_queue:%p\n", + __func__, dvobj, dvobj->phl, rx_pkt_num, &precvpriv->free_recv_queue); +#endif - if (err == RTW_RFRAME_UNAVAIL - || err == RTW_RFRAME_PKT_UNAVAIL - ) { - rtw_msleep_os(1); - _rtw_up_sema(&recvpriv->recv_sema); + while (rx_pkt_num--) { + prframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue); + if (prframe == NULL) { + RTW_ERR("F-%s L-%d rtw_alloc_recvframe failed\n", __FUNCTION__, __LINE__); + goto rx_error; } - flush_signals_thread(); - - } while (err != _FAIL); + //_rtw_init_listhead -exit: + rx_req = rtw_phl_query_rx_pkt(GET_PHL_INFO(dvobj)); + if(rx_req == NULL) + goto rx_stop; - RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); + if(rtw_core_update_recvframe(dvobj, prframe, rx_req) != CORE_RX_CONTINUE) + goto rx_next; - rtw_thread_wait_stop(); + prxattrib = &prframe->u.hdr.attrib; + if (prxattrib->icv_err || prxattrib->crc_err) + goto rx_next; - return 0; -} -#endif /* CONFIG_RECV_THREAD_MODE */ + adapter = prframe->u.hdr.adapter; -#if DBG_RX_BH_TRACKING -void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s) -{ - recv->rx_bh_stage = s; -} + if (!rtw_is_adapter_up(adapter)) + goto rx_next; -void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen) -{ - if (recv->rx_bh_cbuf) - recv->rx_bh_lbuf = recv->rx_bh_cbuf; - recv->rx_bh_cbuf = buf; - if (buf) { - recv->rx_bh_cbuf_data = data; - recv->rx_bh_cbuf_dlen = dlen; - recv->rx_bh_buf_dq_cnt++; - } else { - recv->rx_bh_cbuf_data = NULL; - recv->rx_bh_cbuf_dlen = 0; - } -} +#ifdef CONFIG_RTW_CORE_RXSC + if (core_rxsc_apply_check(adapter, prframe) == CORE_RX_GO_SHORTCUT && + core_rxsc_apply_shortcut(adapter, prframe) == CORE_RX_DONE) + continue; +#endif -void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos) -{ - if (recv->rx_bh_cbuf) { - recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data; - } else { - rtw_warn_on(1); - recv->rx_bh_cbuf_pos = 0; + //recv_func_prehandle + //mgt_dispatcher exist here && sw decrypt mgmt + //?? todo power save + if(validate_recv_frame(adapter, prframe) != CORE_RX_CONTINUE) + goto rx_next; + + pre_process_ret = rtw_core_rx_data_pre_process(adapter, &prframe); + if (pre_process_ret == CORE_RX_DEFRAG) + continue; + if (pre_process_ret != CORE_RX_CONTINUE) + goto rx_next; + + if(rtw_core_rx_data_post_process(adapter, prframe) == CORE_RX_DONE) + continue; + +rx_next: + rtw_free_recvframe(prframe); + continue; +rx_stop: + rtw_free_recvframe(prframe); + break; +rx_error: + break; } -} -void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame) -{ - recv->rx_bh_cframe = frame; -} +#ifdef CONFIG_RTW_NAPI +#ifdef CONFIG_RTW_NAPI_V2 + rtw_core_rx_napi_v2(dvobj); +#endif +#endif -void dump_rx_bh_tk(void *sel, struct recv_priv *recv) -{ - RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n" - , recv->rx_bh_stage - , recv->rx_bh_buf_dq_cnt - , recv->rx_bh_lbuf - , recv->rx_bh_cbuf - , recv->rx_bh_cbuf_dlen - , recv->rx_bh_cbuf_pos - , recv->rx_bh_cframe - ); + return RTW_PHL_STATUS_SUCCESS; } -#endif /* DBG_RX_BH_TRACKING */ - +#endif /*RTW_PHL_RX*/ diff --git a/core/rtw_recv_shortcut.c b/core/rtw_recv_shortcut.c new file mode 100644 index 0000000..d8b4d1b --- /dev/null +++ b/core/rtw_recv_shortcut.c @@ -0,0 +1,247 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_RTW_CORE_RXSC +#define is_equal_mac_addr(lhs,rhs) ((((unsigned long)(lhs)|(unsigned long)(rhs)) & 0x01) ? \ + ((*(unsigned char*)(lhs) ^ (*(unsigned char*)(rhs))) | (*(unsigned char*)(lhs + 1) ^ (*(unsigned char*)(rhs + 1))) | (*(unsigned char*)(lhs + 2) ^ (*(unsigned char*)(rhs + 2)))|\ + (*(unsigned char*)(lhs + 3) ^ (*(unsigned char*)(rhs + 3))) | (*(unsigned char*)(lhs + 4) ^ (*(unsigned char*)(rhs + 4))) | (*(unsigned char*)(lhs + 5) ^ (*(unsigned char*)(rhs + 5))))==0 :\ + ((*(unsigned short*)(lhs) ^ (*(unsigned short*)(rhs))) | (*(unsigned short*)(lhs + 2) ^ (*(unsigned short*)(rhs + 2))) | (*(unsigned short*)(lhs + 4) ^ (*(unsigned short*)(rhs + 4))))==0 \ + ) + +u8 core_rxsc_check_alloc(_adapter *adapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + + if (!adapter->enable_rxsc) + return _FAIL; + + if (pattrib->amsdu || + !pattrib->bdecrypted || + pattrib->mfrag || + pattrib->to_fr_ds == 3 || + !pattrib->bsnaphdr) + return _FAIL; + + if (pattrib->eth_type == ETH_P_ARP || + pattrib->eth_type == 0x888e || + pattrib->eth_type == 0x8899) + return _FAIL; + + if (!prframe->u.hdr.psta) + return _FAIL; + + if (IS_MCAST(pattrib->ra) || IS_MCAST(pattrib->dst)) + return _FAIL; + +#ifdef CONFIG_RTW_MESH + if (pattrib->mesh_ctrl_present) + return _FAIL; +#endif + +#ifdef CONFIG_WAPI_SUPPORT + if (prframe->u.hdr.bIsWaiPacket) + return _FAIL; +#endif + + return _SUCCESS; +} + +struct core_rxsc_entry *core_rxsc_alloc_entry(_adapter *adapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct sta_info *psta = prframe->u.hdr.psta; + struct core_rxsc_entry *rxsc_entry = NULL; + u8 rxsc_idx, cnt = 0; + + if (core_rxsc_check_alloc(adapter, prframe)!=_SUCCESS) + return NULL; + + rxsc_idx = psta->rxsc_idx_new; + + for (cnt=0; cntrxsc_entry[rxsc_idx].status != RXSC_ENTRY_APPLYING) + break; + rxsc_idx++; + } + + rxsc_entry = &psta->rxsc_entry[rxsc_idx]; + + if (rxsc_entry->status == RXSC_ENTRY_APPLYING) + return NULL; + + rxsc_entry->status = RXSC_ENTRY_VALID; + psta->rxsc_idx_new = (rxsc_idx + 1) % NUM_RXSC_ENTRY; + + return rxsc_entry; +} + +sint core_rxsc_get_entry(_adapter *adapter, union recv_frame *prframe) +{ + struct sta_info *psta = NULL; + u8 *pframe = prframe->u.hdr.rx_data; + u8 *lhs, *rhs = NULL; + u8 idx = 0; + struct core_rxsc_entry *rxsc_entry = NULL; + + if (GetFrameType(pframe)!=WIFI_DATA_TYPE) + return _FAIL; + + psta = rtw_get_stainfo(&adapter->stapriv, get_addr2_ptr(pframe)); + + if (!psta) + return _FAIL; + + lhs = GetAddr1Ptr(pframe); + + for (idx = 0; idx < NUM_RXSC_ENTRY; idx++) { + rxsc_entry = &psta->rxsc_entry[(psta->rxsc_idx_cached + idx) % NUM_RXSC_ENTRY]; + + if (rxsc_entry->status == RXSC_ENTRY_INVALID) + continue; + + rhs = (u8*)rxsc_entry->rxsc_wlanhdr.addr1; +#if 0 + DBGP("(A1)lhs=%pM rhs=%pM isEqual=%d %d\n", lhs, rhs, is_equal_mac_addr(lhs,rhs), is_equal_mac_addr(lhs+1,rhs)); + DBGP("(A2)lhs=%pM rhs=%pM\n", lhs+6, rhs+6); + DBGP("(A3)lhs=%pM rhs=%pM\n", lhs+12, rhs+12); + DBGP("rxsc_payload_offset=%d \n", rxsc_entry->rxsc_payload_offset); + DBGP("(LLC)lhs=%pM rhs=%pM\n", + &pframe[rxsc_entry->rxsc_payload_offset+(sizeof(struct ethhdr))-SNAP_SIZE-2], &rtw_rfc1042_header); + DBGP("(eth_type)lhs=0x%x rhs=0x%x\n", + *(unsigned short *)(&pframe[rxsc_entry->rxsc_payload_offset+(ETH_ALEN*2)]), *(unsigned short *)(&rxsc_entry->rxsc_ethhdr.h_proto)); + + DBGP("%d %d %d %d %d \n", + is_equal_mac_addr(lhs,rhs), + is_equal_mac_addr(lhs+6,rhs+6), + is_equal_mac_addr(lhs+12,rhs+12), + !memcmp(&pframe[rxsc_entry->rxsc_payload_offset+(sizeof(struct ethhdr))-SNAP_SIZE-2], &rtw_rfc1042_header, ETH_ALEN), + (*(unsigned short *)(&pframe[rxsc_entry->rxsc_payload_offset+(ETH_ALEN*2)]) == *(unsigned short *)(&rxsc_entry->rxsc_ethhdr.h_proto)) + ); +#endif + if (is_equal_mac_addr(lhs,rhs) && + is_equal_mac_addr(lhs + 6, rhs + 6) && + is_equal_mac_addr(lhs + 12, rhs + 12) && + !memcmp(&pframe[rxsc_entry->rxsc_payload_offset+(sizeof(struct ethhdr)) - SNAP_SIZE - 2], &rtw_rfc1042_header, ETH_ALEN) && + (*(unsigned short *)(&pframe[rxsc_entry->rxsc_payload_offset+(ETH_ALEN * 2)]) == *(unsigned short *)(&rxsc_entry->rxsc_ethhdr.h_proto))) { + prframe->u.hdr.psta = psta; + prframe->u.hdr.rxsc_entry = rxsc_entry; + psta->rxsc_idx_cached = idx; + return _SUCCESS; + } + } + + return _FAIL; +} + +s32 core_rxsc_apply_check(_adapter *adapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct core_rxsc_entry *rxsc_entry = NULL; + + if (!adapter->enable_rxsc) + return CORE_RX_CONTINUE; + + if (core_rxsc_get_entry(adapter, prframe) != _SUCCESS) + return CORE_RX_CONTINUE; + + rxsc_entry = prframe->u.hdr.rxsc_entry; + + rxsc_entry->status = RXSC_ENTRY_APPLYING; + wmb(); + _rtw_memcpy(pattrib, &rxsc_entry->rxsc_attrib, sizeof(rxsc_entry->rxsc_attrib)); + wmb(); + rxsc_entry->status = RXSC_ENTRY_VALID; + + return CORE_RX_GO_SHORTCUT; +} + +s32 core_rxsc_apply_shortcut(_adapter *adapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct core_rxsc_entry *rxsc_entry = prframe->u.hdr.rxsc_entry; + struct sta_info *psta = prframe->u.hdr.psta; + u8 *pframe = prframe->u.hdr.rx_data; + u8 *ptr = NULL; + + /* Shortcut of validate_recv_frame */ + if (pattrib->encrypt == _AES_) { + if (pattrib->qos) + pattrib->priority = GetPriority((pframe + WLAN_HDR_A3_LEN)); + else + pattrib->priority = 0; + + if (!IS_MCAST(pattrib->ra)) { + +#ifdef CONFIG_RECV_REORDERING_CTRL + if (pattrib->qos) + prframe->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; +#endif + + if (recv_ucast_pn_decache(prframe) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + return CORE_RX_DROP; + } + } else { + if (recv_bcast_pn_decache(prframe) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + return CORE_RX_DROP; + } + } + } + + process_pwrbit_data(adapter, prframe, psta); + + if ((get_frame_sub_type(pframe) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) + process_wmmps_data(adapter, prframe, psta); + + /* Shortcut of rtw_core_rx_data_pre_process */ + count_rx_stats(adapter, prframe, NULL); + + /* Shortcut of rtw_core_rx_data_post_process */ + /* 802.11 -> 802.3 */ + if (rxsc_entry->rxsc_trim_pad) + recvframe_pull_tail(prframe, rxsc_entry->rxsc_trim_pad); + + ptr = recvframe_pull(prframe, rxsc_entry->rxsc_payload_offset); + _rtw_memcpy(ptr, (u8 *)(&rxsc_entry->rxsc_ethhdr), sizeof(rxsc_entry->rxsc_ethhdr)); + rtw_rframe_set_os_pkt(prframe); + + /* Packet forward to OS */ + rtw_os_recv_indicate_pkt(adapter, prframe->u.hdr.pkt, prframe); + prframe->u.hdr.pkt = NULL; + rtw_free_recvframe(prframe); +#ifdef RTW_PHL_DBG_CMD + adapter->core_logs.rxCnt_data_shortcut++; +#endif + return CORE_RX_DONE; +} + +void core_rxsc_clear_entry(_adapter *adapter, struct sta_info *psta) +{ + u32 idx = 0; + for (idx=0; idxrxsc_entry[idx].status = RXSC_ENTRY_INVALID; +} +#endif /* CONFIG_RTW_CORE_RXSC */ + diff --git a/core/rtw_rf.c b/core/rtw_rf.c index 9f805b2..dc913b8 100644 --- a/core/rtw_rf.c +++ b/core/rtw_rf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_RF_C_ #include -#include u8 center_ch_2g[CENTER_CH_2G_NUM] = { /* G00 */1, 2, @@ -220,32 +219,30 @@ u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset) goto exit; } - if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + if (offset == CHAN_OFFSET_NO_EXT) { rtw_warn_on(1); goto exit; } /* 2.4G, 40MHz */ - //if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) { - if (cch >= 3 && cch <= 14 && bw == CHANNEL_WIDTH_40) { // OpenHD fix: - t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == CHAN_OFFSET_LOWER) ? cch + 2 : cch - 2; goto exit; } /* 5G, 160MHz */ if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) { - t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; + t_cch = (offset == CHAN_OFFSET_LOWER) ? cch + 8 : cch - 8; goto exit; /* 5G, 80MHz */ } else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) { - t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; + t_cch = (offset == CHAN_OFFSET_LOWER) ? cch + 4 : cch - 4; goto exit; /* 5G, 40MHz */ - //} else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) { - } else if (cch >= 32 && cch <= 177 && bw == CHANNEL_WIDTH_40) { //OpenHD fix: - t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + } else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == CHAN_OFFSET_LOWER) ? cch + 2 : cch - 2; goto exit; } else { @@ -257,26 +254,6 @@ u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset) return t_cch; } -/* - * Get center channel of smaller bandwidth by @param cch, @param bw, @param opch - * @cch: the given center channel - * @bw: the given bandwidth - * @opch: the given operating channel - * - * return center channel of smaller bandiwdth if valid, or 0 - */ -u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch) -{ - u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - - if (opch > cch) - offset = HAL_PRIME_CHNL_OFFSET_UPPER; - else if (opch < cch) - offset = HAL_PRIME_CHNL_OFFSET_LOWER; - - return rtw_get_scch_by_cch_offset(cch, bw, offset); -} - struct op_chs_ent_t { u8 ch_num; u8 *chs; @@ -382,7 +359,7 @@ u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) { u8 valid = 1; - u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 offset = CHAN_OFFSET_NO_EXT; if (bw == CHANNEL_WIDTH_20) goto exit; @@ -393,14 +370,14 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) } if (ch >= 1 && ch <= 4) - offset = HAL_PRIME_CHNL_OFFSET_LOWER; + offset = CHAN_OFFSET_UPPER; else if (ch >= 5 && ch <= 9) { - if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + if (*r_offset == CHAN_OFFSET_UPPER || *r_offset == CHAN_OFFSET_LOWER) offset = *r_offset; /* both lower and upper is valid, obey input value */ else - offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */ + offset = CHAN_OFFSET_LOWER; /* default use upper */ } else if (ch >= 10 && ch <= 13) - offset = HAL_PRIME_CHNL_OFFSET_UPPER; + offset = CHAN_OFFSET_LOWER; else if (ch == 14) { valid = 0; /* ch14 doesn't support 40MHz bandwidth */ goto exit; @@ -420,7 +397,7 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) case 157: case 165: case 173: - offset = HAL_PRIME_CHNL_OFFSET_LOWER; + offset = CHAN_OFFSET_UPPER; break; case 40: case 48: @@ -436,7 +413,7 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) case 161: case 169: case 177: - offset = HAL_PRIME_CHNL_OFFSET_UPPER; + offset = CHAN_OFFSET_LOWER; break; default: valid = 0; @@ -453,64 +430,16 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset) { - u8 cch = ch; - - if (bw == CHANNEL_WIDTH_160) { - if (ch % 4 == 0) { - if (ch >= 36 && ch <= 64) - cch = 50; - else if (ch >= 100 && ch <= 128) - cch = 114; - } else if (ch % 4 == 1) { - if (ch >= 149 && ch <= 177) - cch = 163; - } - - } else if (bw == CHANNEL_WIDTH_80) { - if (ch <= 14) - cch = 7; /* special case for 2.4G */ - else if (ch % 4 == 0) { - if (ch >= 36 && ch <= 48) - cch = 42; - else if (ch >= 52 && ch <= 64) - cch = 58; - else if (ch >= 100 && ch <= 112) - cch = 106; - else if (ch >= 116 && ch <= 128) - cch = 122; - else if (ch >= 132 && ch <= 144) - cch = 138; - } else if (ch % 4 == 1) { - if (ch >= 149 && ch <= 161) - cch = 155; - else if (ch >= 165 && ch <= 177) - cch = 171; - } - - } else if (bw == CHANNEL_WIDTH_40) { - if (offset == HAL_PRIME_CHNL_OFFSET_LOWER) - cch = ch + 2; - else if (offset == HAL_PRIME_CHNL_OFFSET_UPPER) - cch = ch - 2; - - } else if (bw == CHANNEL_WIDTH_20 - || bw == CHANNEL_WIDTH_10 - || bw == CHANNEL_WIDTH_5 - ) - ; /* same as ch */ - else - rtw_warn_on(1); - - return cch; + return rtw_phl_get_center_ch(ch, bw, offset); } u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group) { - BAND_TYPE band = BAND_MAX; + enum band_type band = BAND_MAX; s8 gp = -1, cck_gp = -1; if (ch <= 14) { - band = BAND_ON_2_4G; + band = BAND_ON_24G; if (1 <= ch && ch <= 2) gp = 0; @@ -565,7 +494,7 @@ u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group) } if (band == BAND_MAX - || (band == BAND_ON_2_4G && cck_gp == -1) + || (band == BAND_ON_24G && cck_gp == -1) || gp == -1 ) { RTW_WARN("%s invalid channel:%u", __func__, ch); @@ -575,13 +504,23 @@ u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group) if (group) *group = gp; - if (cck_group && band == BAND_ON_2_4G) + if (cck_group && band == BAND_ON_24G) *cck_group = cck_gp; exit: return band; } +#if CONFIG_IEEE80211_BAND_6GHZ +int rtw_6gch2freq(int chan) +{ + if (chan >= 1 && chan <= 253) + return 5950 + chan * 5; + + return 0; /* not supported */ +} +#endif + int rtw_ch2freq(int chan) { /* see 802.11 17.3.8.3.2 and Annex J @@ -603,6 +542,16 @@ int rtw_ch2freq(int chan) return 0; /* not supported */ } +int rtw_ch2freq_by_band(enum band_type band, int ch) +{ +#if CONFIG_IEEE80211_BAND_6GHZ + if (band == BAND_ON_6G) + return rtw_6gch2freq(ch); + else +#endif + return rtw_ch2freq(ch); +} + int rtw_freq2ch(int freq) { /* see 802.11 17.3.8.3.2 and Annex J */ @@ -612,14 +561,54 @@ int rtw_freq2ch(int freq) return (freq - 2407) / 5; else if (freq >= 4910 && freq <= 4980) return (freq - 4000) / 5; - else if (freq <= 45000) /* DMG band lower limit */ + else if (freq >= 5000 && freq < 5950) return (freq - 5000) / 5; + else if (freq >= 5950 && freq <= 7215) + return (freq - 5950) / 5; else if (freq >= 58320 && freq <= 64800) return (freq - 56160) / 2160; else return 0; } +enum band_type rtw_freq2band(int freq) +{ + if (freq <= 2484) + return BAND_ON_24G; + else if (freq >= 5000 && freq < 5950) + return BAND_ON_5G; +#if CONFIG_IEEE80211_BAND_6GHZ + else if (freq >= 5950 && freq <= 7215) + return BAND_ON_6G; +#endif + else + return BAND_MAX; +} + +bool rtw_freq_consecutive(int a, int b) +{ + enum band_type band_a, band_b; + + band_a = rtw_freq2band(a); + if (band_a == BAND_MAX) + return 0; + band_b = rtw_freq2band(b); + if (band_b == BAND_MAX || band_a != band_b) + return 0; + + switch (band_a) { + case BAND_ON_24G: + return rtw_abs(a - b) == 5; + case BAND_ON_5G: +#if CONFIG_IEEE80211_BAND_6GHZ + case BAND_ON_6G: +#endif + return rtw_abs(a - b) == 20; + default: + return 0; + } +} + bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) { u8 c_ch; @@ -632,7 +621,7 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) if (lo) *lo = 0; - c_ch = rtw_get_center_ch(ch, bw, offset); + c_ch = rtw_phl_get_center_ch(ch, bw, offset); freq = rtw_ch2freq(c_ch); if (!freq) { @@ -667,35 +656,37 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) } const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = { - [CHANNEL_WIDTH_20] = "20MHz", - [CHANNEL_WIDTH_40] = "40MHz", - [CHANNEL_WIDTH_80] = "80MHz", - [CHANNEL_WIDTH_160] = "160MHz", - [CHANNEL_WIDTH_80_80] = "80_80MHz", - [CHANNEL_WIDTH_5] = "5MHz", - [CHANNEL_WIDTH_10] = "10MHz", + "20MHz", + "40MHz", + "80MHz", + "160MHz", + "80_80MHz", + "5MHz", + "10MHz", }; const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = { - [CHANNEL_WIDTH_20] = BW_CAP_20M, - [CHANNEL_WIDTH_40] = BW_CAP_40M, - [CHANNEL_WIDTH_80] = BW_CAP_80M, - [CHANNEL_WIDTH_160] = BW_CAP_160M, - [CHANNEL_WIDTH_80_80] = BW_CAP_80_80M, - [CHANNEL_WIDTH_5] = BW_CAP_5M, - [CHANNEL_WIDTH_10] = BW_CAP_10M, + BW_CAP_20M, + BW_CAP_40M, + BW_CAP_80M, + BW_CAP_160M, + BW_CAP_80_80M, + BW_CAP_5M, + BW_CAP_10M, }; -const char *const _band_str[] = { - "2.4G", - "5G", - "BAND_MAX", +const char *const _rtw_band_str[] = { + [BAND_ON_24G] = "2.4G", + [BAND_ON_5G] = "5G", + [BAND_ON_6G] = "6G", + [BAND_MAX] = "BAND_MAX", }; const u8 _band_to_band_cap[] = { - BAND_CAP_2G, - BAND_CAP_5G, - 0, + [BAND_ON_24G] = BAND_CAP_2G, + [BAND_ON_5G] = BAND_CAP_5G, + [BAND_ON_6G] = BAND_CAP_6G, + [BAND_MAX] = 0, }; const char *const _opc_bw_str[OPC_BW_NUM] = { @@ -720,7 +711,7 @@ const u8 _opc_bw_to_ch_width[OPC_BW_NUM] = { struct op_class_t { u8 class_id; - BAND_TYPE band; + enum band_type band; enum opc_bw bw; u8 *len_ch_attr; }; @@ -731,15 +722,15 @@ struct op_class_t { #define OP_CLASS_ENT(_class, _band, _bw, _len, arg...) \ {.class_id = _class, .band = _band, .bw = _bw, .len_ch_attr = (uint8_t[_len + 1]) {_len, ##arg},} -/* 802.11-2016 Table E-4, partial */ +/* 802.11-2020, 802.11ax-2021 Table E-4, partial */ static const struct op_class_t global_op_class[] = { /* 2G ch1~13, 20M */ - OP_CLASS_ENT(81, BAND_ON_2_4G, OPC_BW20, 13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + OP_CLASS_ENT(81, BAND_ON_24G, OPC_BW20, 13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), /* 2G ch14, 20M */ - OP_CLASS_ENT(82, BAND_ON_2_4G, OPC_BW20, 1, 14), + OP_CLASS_ENT(82, BAND_ON_24G, OPC_BW20, 1, 14), /* 2G, 40M */ - OP_CLASS_ENT(83, BAND_ON_2_4G, OPC_BW40PLUS, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9), - OP_CLASS_ENT(84, BAND_ON_2_4G, OPC_BW40MINUS, 9, 5, 6, 7, 8, 9, 10, 11, 12, 13), + OP_CLASS_ENT(83, BAND_ON_24G, OPC_BW40PLUS, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9), + OP_CLASS_ENT(84, BAND_ON_24G, OPC_BW40MINUS, 9, 5, 6, 7, 8, 9, 10, 11, 12, 13), /* 5G band 1, 20M & 40M */ OP_CLASS_ENT(115, BAND_ON_5G, OPC_BW20, 4, 36, 40, 44, 48), OP_CLASS_ENT(116, BAND_ON_5G, OPC_BW40PLUS, 2, 36, 44), @@ -754,15 +745,15 @@ static const struct op_class_t global_op_class[] = { OP_CLASS_ENT(123, BAND_ON_5G, OPC_BW40MINUS, 6, 104, 112, 120, 128, 136, 144), /* 5G band 4, 20M & 40M */ OP_CLASS_ENT(124, BAND_ON_5G, OPC_BW20, 4, 149, 153, 157, 161), - OP_CLASS_ENT(125, BAND_ON_5G, OPC_BW20, 6, 149, 153, 157, 161, 165, 169), - OP_CLASS_ENT(126, BAND_ON_5G, OPC_BW40PLUS, 2, 149, 157), - OP_CLASS_ENT(127, BAND_ON_5G, OPC_BW40MINUS, 2, 153, 161), + OP_CLASS_ENT(125, BAND_ON_5G, OPC_BW20, 8, 149, 153, 157, 161, 165, 169, 173, 177), + OP_CLASS_ENT(126, BAND_ON_5G, OPC_BW40PLUS, 4, 149, 157, 165, 173), + OP_CLASS_ENT(127, BAND_ON_5G, OPC_BW40MINUS, 4, 153, 161, 169, 177), /* 5G, 80M & 160M */ - OP_CLASS_ENT(128, BAND_ON_5G, OPC_BW80, 24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161), - OP_CLASS_ENT(129, BAND_ON_5G, OPC_BW160, 16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128), + OP_CLASS_ENT(128, BAND_ON_5G, OPC_BW80, 28, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, 169, 173, 177), + OP_CLASS_ENT(129, BAND_ON_5G, OPC_BW160, 24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, 169, 173, 177), #if 0 /* TODO */ /* 5G, 80+80M */ - {130, BAND_ON_5G, OPC_BW80P80, 0x0FFFFFF}, + OP_CLASS_ENT(130, BAND_ON_5G, OPC_BW80P80, 28, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, 169, 173, 177), #endif }; @@ -822,7 +813,7 @@ s16 get_sub_op_class(u8 gid, u8 ch) { const struct op_class_t *opc = get_global_op_class_by_id(gid); int i; - enum channel_width bw; + enum channel_width bw; if (!opc) return -1; @@ -877,23 +868,23 @@ static bool dbg_global_op_class_validate(u8 gid) switch (global_op_class[gid].bw) { case OPC_BW20: bw = CHANNEL_WIDTH_20; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW40PLUS: bw = CHANNEL_WIDTH_40; - offset = HAL_PRIME_CHNL_OFFSET_LOWER; + offset = CHAN_OFFSET_UPPER; break; case OPC_BW40MINUS: bw = CHANNEL_WIDTH_40; - offset = HAL_PRIME_CHNL_OFFSET_UPPER; + offset = CHAN_OFFSET_LOWER; break; case OPC_BW80: bw = CHANNEL_WIDTH_80; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW160: bw = CHANNEL_WIDTH_160; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW80P80: /* TODO */ default: @@ -952,12 +943,12 @@ void dump_global_op_class(void *sel) u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset) { - BAND_TYPE band = BAND_MAX; + enum band_type band = BAND_MAX; int i; u8 gid = 0; /* invalid */ if (rtw_is_2g_ch(ch)) - band = BAND_ON_2_4G; + band = BAND_ON_24G; else if (rtw_is_5g_ch(ch)) band = BAND_ON_5G; else @@ -984,9 +975,9 @@ u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset) continue; if ((global_op_class[i].bw == OPC_BW40PLUS - && offset != HAL_PRIME_CHNL_OFFSET_LOWER) + && offset != CHAN_OFFSET_UPPER) || (global_op_class[i].bw == OPC_BW40MINUS - && offset != HAL_PRIME_CHNL_OFFSET_UPPER) + && offset != CHAN_OFFSET_LOWER) ) continue; @@ -1024,9 +1015,9 @@ u8 rtw_get_bw_offset_by_op_class_ch(u8 gid, u8 ch, u8 *bw, u8 *offset) *bw = opc_bw_to_ch_width(opc_bw); if (opc_bw == OPC_BW40PLUS) - *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + *offset = CHAN_OFFSET_UPPER; else if (opc_bw == OPC_BW40MINUS) - *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + *offset = CHAN_OFFSET_LOWER; if (rtw_get_offset_by_chbw(ch, *bw, offset)) valid = 1; @@ -1074,8 +1065,9 @@ static void opc_pref_free(struct op_class_pref_t *opc_pref) int op_class_pref_init(_adapter *adapter) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct registry_priv *regsty = adapter_to_regsty(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); u8 bw; struct op_class_pref_t *opc_pref; int i; @@ -1090,13 +1082,13 @@ int op_class_pref_init(_adapter *adapter) goto exit; } - if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_2G)) + if (is_supported_24g(regsty->wireless_mode) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_2G)) band_bmp |= BAND_CAP_2G; - if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_5G)) + if (is_supported_5g(regsty->wireless_mode) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_5G)) band_bmp |= BAND_CAP_5G; - bw_bmp[BAND_ON_2_4G] = (ch_width_to_bw_cap(REGSTY_BW_2G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap); - bw_bmp[BAND_ON_5G] = (ch_width_to_bw_cap(REGSTY_BW_5G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap); + bw_bmp[BAND_ON_24G] = (ch_width_to_bw_cap(REGSTY_BW_2G(regsty) + 1) - 1) & (GET_HAL_SPEC(dvobj)->bw_cap); + bw_bmp[BAND_ON_5G] = (ch_width_to_bw_cap(REGSTY_BW_5G(regsty) + 1) - 1) & (GET_HAL_SPEC(dvobj)->bw_cap); if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode) ) @@ -1105,9 +1097,9 @@ int op_class_pref_init(_adapter *adapter) if (0) { RTW_INFO("REGSTY_BW_2G(regsty):%u\n", REGSTY_BW_2G(regsty)); RTW_INFO("REGSTY_BW_5G(regsty):%u\n", REGSTY_BW_5G(regsty)); - RTW_INFO("GET_HAL_SPEC(adapter)->bw_cap:0x%x\n", GET_HAL_SPEC(adapter)->bw_cap); + RTW_INFO("GET_HAL_SPEC(adapter)->bw_cap:0x%x\n", GET_HAL_SPEC(dvobj)->bw_cap); RTW_INFO("band_bmp:0x%x\n", band_bmp); - RTW_INFO("bw_bmp[2G]:0x%x\n", bw_bmp[BAND_ON_2_4G]); + RTW_INFO("bw_bmp[2G]:0x%x\n", bw_bmp[BAND_ON_24G]); RTW_INFO("bw_bmp[5G]:0x%x\n", bw_bmp[BAND_ON_5G]); } @@ -1184,7 +1176,7 @@ void op_class_pref_apply_regulatory(_adapter *adapter, u8 reason) opc_pref = rfctl->spt_op_class_ch[i]; /* reset all channel */ - for (j = 0; opc_pref->chs[j].ch != 0; j++) { + for (j = 0; j < MAX_CHANNEL_NUM_OF_BAND && opc_pref->chs[j].ch != 0; j++) { if (reason >= REG_CHANGE) opc_pref->chs[j].static_non_op = 1; if (reason != REG_TXPWR_CHANGE) @@ -1200,34 +1192,34 @@ void op_class_pref_apply_regulatory(_adapter *adapter, u8 reason) switch (opc_pref->bw) { case OPC_BW20: bw = CHANNEL_WIDTH_20; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW40PLUS: bw = CHANNEL_WIDTH_40; - offset = HAL_PRIME_CHNL_OFFSET_LOWER; + offset = CHAN_OFFSET_UPPER; break; case OPC_BW40MINUS: bw = CHANNEL_WIDTH_40; - offset = HAL_PRIME_CHNL_OFFSET_UPPER; + offset = CHAN_OFFSET_LOWER; break; case OPC_BW80: bw = CHANNEL_WIDTH_80; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW160: bw = CHANNEL_WIDTH_160; - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + offset = CHAN_OFFSET_NO_EXT; break; case OPC_BW80P80: /* TODO */ default: continue; } - if (rfctl->country_ent && !COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent) + if (!RFCTL_REG_EN_11AC(rfctl) && (bw == CHANNEL_WIDTH_80 || bw == CHANNEL_WIDTH_160)) continue; - for (j = 0; opc_pref->chs[j].ch != 0; j++) { + for (j = 0; j < MAX_CHANNEL_NUM_OF_BAND && opc_pref->chs[j].ch != 0; j++) { u8 *op_chs; u8 op_ch_num; u8 k, l; @@ -1304,7 +1296,7 @@ static void dump_opc_pref_single(void *sel, struct op_class_pref_t *opc_pref, bo if (!show_no_ir && !opc_pref->ir_ch_num) return; - for (i = 0; opc_pref->chs[i].ch != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM_OF_BAND && opc_pref->chs[i].ch != 0; i++) { if ((show_snon_ocp || !opc_pref->chs[i].static_non_op) && (show_no_ir || !opc_pref->chs[i].no_ir) ) { @@ -1324,7 +1316,7 @@ static void dump_opc_pref_single(void *sel, struct op_class_pref_t *opc_pref, bo return; pos = buf; - for (i = 0; opc_pref->chs[i].ch != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM_OF_BAND && opc_pref->chs[i].ch != 0; i++) { if ((show_snon_ocp || !opc_pref->chs[i].static_non_op) && (show_no_ir || !opc_pref->chs[i].no_ir) ) { @@ -1337,7 +1329,7 @@ static void dump_opc_pref_single(void *sel, struct op_class_pref_t *opc_pref, bo RTW_PRINT_SEL(sel, " %s\n", buf); pos = buf; - for (i = 0; opc_pref->chs[i].ch != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM_OF_BAND && opc_pref->chs[i].ch != 0; i++) { if ((show_snon_ocp || !opc_pref->chs[i].static_non_op) && (show_no_ir || !opc_pref->chs[i].no_ir) ) { @@ -1395,82 +1387,47 @@ void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail) RTW_PRINT_SEL(sel, "op_class number:%d\n", rfctl->cur_spt_op_class_num); } -const u8 _rf_type_to_rf_tx_cnt[RF_TYPE_MAX] = { - [RF_1T1R] = 1, - [RF_1T2R] = 1, - [RF_1T3R] = 1, - [RF_1T4R] = 1, - [RF_2T1R] = 2, - [RF_2T2R] = 2, - [RF_2T3R] = 2, - [RF_2T4R] = 2, - [RF_3T1R] = 3, - [RF_3T2R] = 3, - [RF_3T3R] = 3, - [RF_3T4R] = 3, - [RF_4T1R] = 4, - [RF_4T2R] = 4, - [RF_4T3R] = 4, - [RF_4T4R] = 4, +const u8 _rf_type_to_rf_tx_cnt[] = { + 1, /*RF_1T1R*/ + 1, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 2, /*RF_2T3R*/ + 2, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 3, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; -const u8 _rf_type_to_rf_rx_cnt[RF_TYPE_MAX] = { - [RF_1T1R] = 1, - [RF_1T2R] = 2, - [RF_1T3R] = 3, - [RF_1T4R] = 4, - [RF_2T1R] = 1, - [RF_2T2R] = 2, - [RF_2T3R] = 3, - [RF_2T4R] = 4, - [RF_3T1R] = 1, - [RF_3T2R] = 2, - [RF_3T3R] = 3, - [RF_3T4R] = 4, - [RF_4T1R] = 1, - [RF_4T2R] = 2, - [RF_4T3R] = 3, - [RF_4T4R] = 4, +const u8 _rf_type_to_rf_rx_cnt[] = { + 1, /*RF_1T1R*/ + 2, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 3, /*RF_2T3R*/ + 4, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 4, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; -const char *const _rf_type_to_rfpath_str[RF_TYPE_MAX] = { - [RF_1T1R] = "RF_1T1R", - [RF_1T2R] = "RF_1T2R", - [RF_1T3R] = "RF_1T3R", - [RF_1T4R] = "RF_1T4R", - [RF_2T1R] = "RF_2T1R", - [RF_2T2R] = "RF_2T2R", - [RF_2T3R] = "RF_2T3R", - [RF_2T4R] = "RF_2T4R", - [RF_3T1R] = "RF_3T1R", - [RF_3T2R] = "RF_3T2R", - [RF_3T3R] = "RF_3T3R", - [RF_3T4R] = "RF_3T4R", - [RF_4T1R] = "RF_4T1R", - [RF_4T2R] = "RF_4T2R", - [RF_4T3R] = "RF_4T3R", - [RF_4T4R] = "RF_4T4R", +const char *const _rf_type_to_rfpath_str[] = { + "RF_1T1R", + "RF_1T2R", + "RF_2T2R", + "RF_2T3R", + "RF_2T4R", + "RF_3T3R", + "RF_3T4R", + "RF_4T4R", + "RF_TYPE_MAX" }; -void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx) -{ - u8 tx_num = rf_type_to_rf_tx_cnt(rf); - u8 rx_num = rf_type_to_rf_rx_cnt(rf); - int i; - - *tx = *rx = 0; - - for (i = 0; i < tx_num; i++) - *tx |= BIT(i); - for (i = 0; i < rx_num; i++) - *rx |= BIT(i); -} - static const u8 _trx_num_to_rf_type[RF_PATH_MAX][RF_PATH_MAX] = { - {RF_1T1R, RF_1T2R, RF_1T3R, RF_1T4R}, - {RF_2T1R, RF_2T2R, RF_2T3R, RF_2T4R}, - {RF_3T1R, RF_3T2R, RF_3T3R, RF_3T4R}, - {RF_4T1R, RF_4T2R, RF_4T3R, RF_4T4R}, + {RF_1T1R, RF_1T2R, RF_TYPE_MAX, RF_TYPE_MAX}, + {RF_TYPE_MAX, RF_2T2R, RF_2T3R, RF_2T4R}, + {RF_TYPE_MAX, RF_TYPE_MAX, RF_3T3R, RF_3T4R}, + {RF_TYPE_MAX, RF_TYPE_MAX, RF_TYPE_MAX, RF_4T4R}, }; enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num) @@ -1514,11 +1471,12 @@ static void rtw_path_bmp_limit_from_higher(u8 *bmp, u8 *bmp_bit_cnt, u8 bit_cnt_ } } -u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num) +u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num) { u8 bmp_tx = (trx_path_bmp & 0xF0) >> 4; u8 bmp_rx = trx_path_bmp & 0x0F; u8 bmp_tx_num = 0, bmp_rx_num = 0; + u8 tx_num_lmt, rx_num_lmt; enum rf_type ret_type = RF_TYPE_MAX; int i, j; @@ -1530,10 +1488,10 @@ u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 r } /* limit higher bit first according to input type */ - if (tx_num_lmt) - rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, tx_num_lmt); - if (rx_num_lmt) - rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, rx_num_lmt); + tx_num_lmt = rf_type_to_rf_tx_cnt(type); + rx_num_lmt = rf_type_to_rf_rx_cnt(type); + rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, tx_num_lmt); + rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, rx_num_lmt); /* search for valid rf_type (larger RX prefer) */ for (j = bmp_rx_num; j > 0; j--) { @@ -1555,64 +1513,6 @@ u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 r return RF_TYPE_VALID(ret_type) ? ((bmp_tx << 4) | bmp_rx) : 0x00; } -u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num) -{ - return rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp - , rf_type_to_rf_tx_cnt(type), rf_type_to_rf_rx_cnt(type), tx_num, rx_num); -} - -/* config to non N-TX value, path with lower index prefer */ -void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath) -{ - int i, j; - u8 cnt; - - for (i = 4; i > 0; i--) { - cnt = 0; - txpath_nss[i - 1] = 0; - for (j = 0; j < RF_PATH_MAX; j++) { - if (txpath & BIT(j)) { - txpath_nss[i - 1] |= BIT(j); - if (++cnt == i) - break; - } - } - txpath_num_nss[i - 1] = i; - } -} - -/* config to full N-TX value */ -void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath) -{ - u8 tx_num = 0; - int i; - - for (i = 0; i < RF_PATH_MAX; i++) - if (txpath & BIT(i)) - tx_num++; - - for (i = 4; i > 0; i--) { - txpath_nss[i - 1] = txpath; - txpath_num_nss[i - 1] = tx_num; - } -} - -const char *const _regd_str[] = { - "NONE", - "FCC", - "MKK", - "ETSI", - "IC", - "KCC", - "NCC", - "ACMA", - "CHILE", - "UKRAINE", - "MEXICO", - "CN", - "WW", -}; - /* * input with txpwr value in unit of txpwr index * return string in length 6 at least (for -xx.xx) @@ -1682,747 +1582,17 @@ s16 mb_of_ntx(u8 ntx) } #if CONFIG_TXPWR_LIMIT -void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) -{ - struct regd_exc_ent *ent; - _list *cur, *head; - - RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num); - - if (!rfctl->regd_exc_num) - goto exit; - - RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name"); - - head = &rfctl->reg_exc_list; - cur = get_next(head); - - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - u8 has_country; - - ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); - cur = get_next(cur); - has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; - - RTW_PRINT_SEL(sel, " %c%c 0x%02x %s\n" - , has_country ? ent->country[0] : '0' - , has_country ? ent->country[1] : '0' - , ent->domain - , ent->regd_name - ); - } - -exit: - return; -} - -inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) -{ - _irqL irqL; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - _dump_regd_exc_list(sel, rfctl); - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); -} - -void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen) -{ - struct regd_exc_ent *ent; - _irqL irqL; - - if (!regd_name || !nlen) { - rtw_warn_on(1); - goto exit; - } - - ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1); - if (!ent) - goto exit; - - _rtw_init_listhead(&ent->list); - if (country) - _rtw_memcpy(ent->country, country, 2); - ent->domain = domain; - _rtw_memcpy(ent->regd_name, regd_name, nlen); - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list); - rfctl->regd_exc_num++; - - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - -exit: - return; -} - -inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name) -{ - rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name)); -} - -struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) -{ - struct regd_exc_ent *ent; - _list *cur, *head; - u8 match = 0; - - head = &rfctl->reg_exc_list; - cur = get_next(head); - - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - u8 has_country; - - ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); - cur = get_next(cur); - has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; - - /* entry has country condition to match */ - if (has_country) { - if (!country) - continue; - if (ent->country[0] != country[0] - || ent->country[1] != country[1]) - continue; - } - - /* entry has domain condition to match */ - if (ent->domain != 0xFF) { - if (domain == 0xFF) - continue; - if (ent->domain != domain) - continue; - } - - match = 1; - break; - } - - if (match) - return ent; - else - return NULL; -} - -inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) +void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) { - struct regd_exc_ent *ent; - _irqL irqL; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - ent = _rtw_regd_exc_search(rfctl, country, domain); - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - return ent; -} - -void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl) -{ - struct regd_exc_ent *ent; - _irqL irqL; - _list *cur, *head; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - head = &rfctl->reg_exc_list; - cur = get_next(head); - - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); - cur = get_next(cur); - rtw_list_delete(&ent->list); - rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1); - } - rfctl->regd_exc_num = 0; - - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + /* TODO: get from phl */ } void dump_txpwr_lmt(void *sel, _adapter *adapter) { -#define TMP_STR_LEN 16 - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - _irqL irqL; - char fmt[16]; - char tmp_str[TMP_STR_LEN]; - s8 *lmt_idx = NULL; - int bw, band, ch_num, tlrs, ntx_idx, rs, i, path; - u8 ch, n, rfpath_num; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - _dump_regd_exc_list(sel, rfctl); - RTW_PRINT_SEL(sel, "\n"); - - if (!rfctl->txpwr_regd_num) - goto release_lock; - - lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); - if (!lmt_idx) { - RTW_ERR("%s alloc fail\n", __func__); - goto release_lock; - } - - RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state); - #if CONFIG_IEEE80211_BAND_5GHZ - if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) { - RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state); - RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref); - } - #endif - RTW_PRINT_SEL(sel, "\n"); - - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { - if (!hal_is_band_support(adapter, band)) - continue; - - rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g); - - for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { - - if (bw >= CHANNEL_WIDTH_160) - break; - if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) - break; - - if (band == BAND_ON_2_4G) - ch_num = CENTER_CH_2G_NUM; - else - ch_num = center_chs_5g_num(bw); - - if (ch_num == 0) { - rtw_warn_on(1); - break; - } - - for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) { - - if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT) - continue; - if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) - continue; - if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)) - continue; - if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT) - continue; - if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) - continue; - - for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { - struct txpwr_lmt_ent *ent; - _list *cur, *head; - - if (ntx_idx + 1 > hal_data->max_tx_cnt) - continue; - - /* bypass CCK multi-TX is not defined */ - if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) { - if (band == BAND_ON_2_4G - && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx))) - continue; - } - - /* bypass OFDM multi-TX is not defined */ - if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) { - if (band == BAND_ON_2_4G - && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) - continue; - #if CONFIG_IEEE80211_BAND_5GHZ - if (band == BAND_ON_5G - && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) - continue; - #endif - } - - /* bypass 5G 20M, 40M pure reference */ - #if CONFIG_IEEE80211_BAND_5GHZ - if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { - if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) { - if (tlrs == TXPWR_LMT_RS_HT) - continue; - } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) { - if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40) - continue; - } - } - #endif - - /* choose n-SS mapping rate section to get lmt diff value */ - if (tlrs == TXPWR_LMT_RS_CCK) - rs = CCK; - else if (tlrs == TXPWR_LMT_RS_OFDM) - rs = OFDM; - else if (tlrs == TXPWR_LMT_RS_HT) - rs = HT_1SS + ntx_idx; - else if (tlrs == TXPWR_LMT_RS_VHT) - rs = VHT_1SS + ntx_idx; - else { - RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs); - continue; - } - - RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n" - , band_str(band) - , ch_width_str(bw) - , txpwr_lmt_rs_str(tlrs) - , ntx_idx + 1 - ); - - /* header for limit in db */ - RTW_PRINT_SEL(sel, "%3s ", "ch"); - - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - - sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name)); - snprintf(tmp_str, TMP_STR_LEN, fmt - , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : "" - , ent->regd_name); - _RTW_PRINT_SEL(sel, "%s", tmp_str); - } - sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW))); - snprintf(tmp_str, TMP_STR_LEN, fmt - , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : "" - , regd_str(TXPWR_LMT_WW)); - _RTW_PRINT_SEL(sel, "%s", tmp_str); - - /* header for limit offset */ - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - _RTW_PRINT_SEL(sel, "|"); - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - _RTW_PRINT_SEL(sel, "%3c " - , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' '); - } - _RTW_PRINT_SEL(sel, "%3c " - , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' '); - } - _RTW_PRINT_SEL(sel, "\n"); - - for (n = 0; n < ch_num; n++) { - s8 lmt; - s8 lmt_offset; - u8 base; - - if (band == BAND_ON_2_4G) - ch = n + 1; - else - ch = center_chs_5g(bw, n); - - if (ch == 0) { - rtw_warn_on(1); - break; - } - - /* dump limit in dBm */ - RTW_PRINT_SEL(sel, "%3u ", ch); - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - lmt = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0); - txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(ent->regd_name), tmp_str, TMP_STR_LEN); - _RTW_PRINT_SEL(sel, "%s ", tmp_str); - } - lmt = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0); - txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(regd_str(TXPWR_LMT_WW)), tmp_str, TMP_STR_LEN); - _RTW_PRINT_SEL(sel, "%s ", tmp_str); - - /* dump limit offset of each path */ - for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - - base = phy_get_target_txpwr(adapter, band, path, rs); - - _RTW_PRINT_SEL(sel, "|"); - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - i = 0; - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - lmt_offset = phy_get_txpwr_lmt_diff(adapter, ent->regd_name, band, bw, path, rs, tlrs, ntx_idx, ch, 0); - if (lmt_offset == hal_spec->txgi_max) { - *(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max; - _RTW_PRINT_SEL(sel, "%3s ", "NA"); - } else { - *(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base; - _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); - } - i++; - } - lmt_offset = phy_get_txpwr_lmt_diff(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, tlrs, ntx_idx, ch, 0); - if (lmt_offset == hal_spec->txgi_max) - _RTW_PRINT_SEL(sel, "%3s ", "NA"); - else - _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); - - } - - /* compare limit_idx of each path, print 'x' when mismatch */ - if (rfpath_num > 1) { - for (i = 0; i < rfctl->txpwr_regd_num; i++) { - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num))) - break; - } - if (path >= rfpath_num) - _RTW_PRINT_SEL(sel, " "); - else - _RTW_PRINT_SEL(sel, "x"); - } - } - _RTW_PRINT_SEL(sel, "\n"); - - } - RTW_PRINT_SEL(sel, "\n"); - } - } /* loop for rate sections */ - } /* loop for bandwidths */ - } /* loop for bands */ - - if (lmt_idx) - rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); - -release_lock: - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); -} - -/* search matcing first, if not found, alloc one */ -void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen - , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) -{ - struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl))); - struct txpwr_lmt_ent *ent; - _irqL irqL; - _list *cur, *head; - s8 pre_lmt; - - if (!regd_name || !nlen) { - rtw_warn_on(1); - goto exit; - } - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - /* search for existed entry */ - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - - if (strlen(ent->regd_name) == nlen - && _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE) - goto chk_lmt_val; - } - - /* alloc new one */ - ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1); - if (!ent) - goto release_lock; - - _rtw_init_listhead(&ent->list); - _rtw_memcpy(ent->regd_name, regd_name, nlen); - { - u8 j, k, l, m; - - for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) - for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k) - for (m = 0; m < CENTER_CH_2G_NUM; ++m) - for (l = 0; l < MAX_TX_COUNT; ++l) - ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max; - #if CONFIG_IEEE80211_BAND_5GHZ - for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) - for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k) - for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) - for (l = 0; l < MAX_TX_COUNT; ++l) - ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max; - #endif - } - - rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list); - rfctl->txpwr_regd_num++; - -chk_lmt_val: - if (band == BAND_ON_2_4G) - pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; - #if CONFIG_IEEE80211_BAND_5GHZ - else if (band == BAND_ON_5G) - pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; - #endif - else - goto release_lock; - - if (pre_lmt != hal_spec->txgi_max) - RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n" - , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 - , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]); - - lmt = rtw_min(pre_lmt, lmt); - if (band == BAND_ON_2_4G) - ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt; - #if CONFIG_IEEE80211_BAND_5GHZ - else if (band == BAND_ON_5G) - ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt; - #endif - - if (0) - RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n" - , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 - , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx] - , lmt); - -release_lock: - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - -exit: - return; -} - -inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name - , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) -{ - rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name) - , band, bw, tlrs, ntx_idx, ch_idx, lmt); -} - -struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) -{ - struct txpwr_lmt_ent *ent; - _list *cur, *head; - u8 found = 0; - - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - - if (strcmp(ent->regd_name, regd_name) == 0) { - found = 1; - break; - } - } - - if (found) - return ent; - return NULL; -} - -inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) -{ - struct txpwr_lmt_ent *ent; - _irqL irqL; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name); - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - return ent; -} - -void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl) -{ - struct txpwr_lmt_ent *ent; - _irqL irqL; - _list *cur, *head; - - _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - if (ent->regd_name == rfctl->regd_name) - rfctl->regd_name = regd_str(TXPWR_LMT_NONE); - rtw_list_delete(&ent->list); - rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1); - } - rfctl->txpwr_regd_num = 0; - - _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + /* TODO: get from phl */ } #endif /* CONFIG_TXPWR_LIMIT */ -int rtw_ch_to_bb_gain_sel(int ch) -{ - int sel = -1; - - if (ch >= 1 && ch <= 14) - sel = BB_GAIN_2G; -#if CONFIG_IEEE80211_BAND_5GHZ - else if (ch >= 36 && ch < 48) - sel = BB_GAIN_5GLB1; - else if (ch >= 52 && ch <= 64) - sel = BB_GAIN_5GLB2; - else if (ch >= 100 && ch <= 120) - sel = BB_GAIN_5GMB1; - else if (ch >= 124 && ch <= 144) - sel = BB_GAIN_5GMB2; - else if (ch >= 149 && ch <= 177) - sel = BB_GAIN_5GHB; -#endif - - return sel; -} - -s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) -{ - s8 kfree_offset = 0; - -#ifdef CONFIG_RF_POWER_TRIM - struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter); - s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch); - - if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) { - rtw_warn_on(1); - goto exit; - } - - if (kfree_data->flag & KFREE_FLAG_ON) { - kfree_offset = kfree_data->bb_gain[bb_gain_sel][path]; - if (IS_HARDWARE_TYPE_8723D(padapter)) - RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n" - , __func__, (path == 0)?"S1":"S0", - ch, bb_gain_sel, kfree_offset); - else - RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n" - , __func__, path, ch, bb_gain_sel, kfree_offset); - } -exit: -#endif /* CONFIG_RF_POWER_TRIM */ - return kfree_offset; -} - -void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) -{ -#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) && !defined(CONFIG_RTL8822C) \ - && !defined(CONFIG_RTL8723F) - u8 write_value; -#endif - u8 target_path = 0; - u32 val32 = 0; - - if (IS_HARDWARE_TYPE_8723D(adapter)) { - target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/ - if (path == PPG_8723D_S1) - RTW_INFO("kfree gain_offset 0x55:0x%x ", - rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); - else if (path == PPG_8723D_S0) - RTW_INFO("kfree gain_offset 0x65:0x%x ", - rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff)); - } else { - target_path = path; - RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); - } - - switch (rtw_get_chip_type(adapter)) { -#ifdef CONFIG_RTL8723D - case RTL8723D: - write_value = RF_TX_GAIN_OFFSET_8723D(offset); - if (path == PPG_8723D_S1) - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); - else if (path == PPG_8723D_S0) - rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value); - break; -#endif /* CONFIG_RTL8723D */ -#ifdef CONFIG_RTL8703B - case RTL8703B: - write_value = RF_TX_GAIN_OFFSET_8703B(offset); - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); - break; -#endif /* CONFIG_RTL8703B */ -#ifdef CONFIG_RTL8188F - case RTL8188F: - write_value = RF_TX_GAIN_OFFSET_8188F(offset); - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); - break; -#endif /* CONFIG_RTL8188F */ -#ifdef CONFIG_RTL8188GTV - case RTL8188GTV: - write_value = RF_TX_GAIN_OFFSET_8188GTV(offset); - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); - break; -#endif /* CONFIG_RTL8188GTV */ -#ifdef CONFIG_RTL8192E - case RTL8192E: - write_value = RF_TX_GAIN_OFFSET_8192E(offset); - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); - break; -#endif /* CONFIG_RTL8188F */ - -#ifdef CONFIG_RTL8821A - case RTL8821: - write_value = RF_TX_GAIN_OFFSET_8821A(offset); - rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); - break; -#endif /* CONFIG_RTL8821A */ -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C) \ - || defined(CONFIG_RTL8723F) - case RTL8814A: - case RTL8822B: - case RTL8822C: - case RTL8821C: - case RTL8192F: - case RTL8723F: - RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path); - break; -#endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C || CONFIG_RTL8723F */ - - default: - rtw_warn_on(1); - break; - } - - if (IS_HARDWARE_TYPE_8723D(adapter)) { - if (path == PPG_8723D_S1) - val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); - else if (path == PPG_8723D_S0) - val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff); - } else { - val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); - } - RTW_INFO(" after :0x%x\n", val32); -} - -void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) -{ - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - s8 kfree_offset = 0; - s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */ - s8 total_offset; - int i, total = 0; - - if (IS_HARDWARE_TYPE_8723D(adapter)) - total = 2; /* S1 and S0 */ - else - total = hal_spec->rf_reg_path_num; - - for (i = 0; i < total; i++) { - kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch); - total_offset = kfree_offset + tx_pwr_track_offset; - rtw_rf_set_tx_gain_offset(adapter, i, total_offset); - } -} - bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) { return (dfs_region == RTW_DFS_REGD_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE; diff --git a/core/rtw_rm.c b/core/rtw_rm.c index 38ceb2e..880ca98 100644 --- a/core/rtw_rm.c +++ b/core/rtw_rm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -14,7 +14,6 @@ *****************************************************************************/ #include -#include #ifdef CONFIG_RTW_80211K #include "rtw_rm_fsm.h" #include "rtw_rm_util.h" @@ -196,7 +195,6 @@ u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta) { struct rm_obj *prm; - prm = rm_alloc_rmobj(padapter); if (prm == NULL) { @@ -209,7 +207,6 @@ u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta) prm->q.diag_token = rm_gen_dialog_token(padapter); prm->q.m_token = rm_gen_meas_token(padapter); prm->rmid = rm_gen_rmid(padapter, prm, RM_MASTER); - prm->q.action_code = RM_ACT_NB_REP_REQ; #if 0 @@ -227,7 +224,7 @@ u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta) rm_enqueue_rmobj(padapter, prm, _FALSE); RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n", - prm->rmid, MAC_ARG(psta->cmn.mac_addr)); + prm->rmid, MAC_ARG(psta->phl_sta->mac_addr)); return _SUCCESS; } @@ -255,7 +252,7 @@ static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe, fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, psta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN); @@ -362,15 +359,11 @@ int ready_for_scan(struct rm_obj *prm) return _FALSE; } -int rm_sitesurvey(struct rm_obj *prm) +int rm_get_chset(struct rm_obj *prm) { - int meas_ch_amount=0; + int i,meas_ch_amount=0; u8 op_class=0, val8; struct rtw_ieee80211_channel *pch_set; - struct sitesurvey_parm parm; - - - RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__); pch_set = &prm->q.ch_set[0]; @@ -398,20 +391,34 @@ int rm_sitesurvey(struct rm_obj *prm) #if (RM_MORE_DBG_MSG) RTW_INFO("survey (%d) chaannels\n", meas_ch_amount); #endif + return 0; +} +int rm_sitesurvey(struct rm_obj *prm) +{ + int meas_ch_amount=0; + u8 op_class=0, val8; + struct rtw_ieee80211_channel *pch_set; + struct sitesurvey_parm parm; + + + RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__); + + rm_get_chset(prm); + pch_set = &prm->q.ch_set[0]; + + meas_ch_amount = MIN(prm->q.ch_set_ch_amount, RTW_CHANNEL_SCAN_AMOUNT); _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm)); - _rtw_memcpy(parm.ch, pch_set, - sizeof(struct rtw_ieee80211_channel) * - MIN(meas_ch_amount, RTW_CHANNEL_SCAN_AMOUNT)); + _rtw_memcpy(parm.ch, pch_set, sizeof(struct rtw_ieee80211_channel) * meas_ch_amount); _rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE); parm.ssid_num = 1; parm.scan_mode = prm->q.m_mode; parm.ch_num = meas_ch_amount; - parm.igi = 0; - parm.token = prm->rmid; + parm.rrm_token = prm->rmid; parm.duration = prm->q.meas_dur; + parm.scan_type = RTW_SCAN_RRM; /* parm.bw = BW_20M; */ rtw_sitesurvey_cmd(prm->psta->padapter, &parm); @@ -537,6 +544,7 @@ static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) &pbody[p+2], pbody[p+1]); #endif #endif + RTW_INFO("RM: bcn_req_ssid=%s\n", prm->q.opt.bcn.ssid.Ssid); @@ -597,8 +605,8 @@ static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) RTW_ERR("RM: bcn_req_ap_ch_rep over size\n"); break; } - popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + /* get channel list * EID:len:op-class:ch-list */ @@ -700,7 +708,7 @@ int rm_recv_radio_mens_req(_adapter *padapter, #if 0 /* search existing rm_obj */ - rmid = psta->cmn.aid << 16 + rmid = psta->phl_sta->aid << 16 | pdiag_body[2] << 8 | RM_SLAVE; @@ -729,7 +737,7 @@ int rm_recv_radio_mens_req(_adapter *padapter, prm->rmid = rm_gen_rmid(padapter, prm, RM_SLAVE); RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, - MAC_ARG(prm->psta->cmn.mac_addr)); + MAC_ARG(prm->psta->phl_sta->mac_addr)); #if (RM_MORE_DBG_MSG) RTW_INFO("RM: element_id = %d\n", prm->q.e_id); @@ -786,15 +794,15 @@ int rm_recv_radio_mens_req(_adapter *padapter, int rm_recv_radio_mens_rep(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta) { - int len, ret = _FALSE; + int ret = _FALSE; struct rm_obj *prm; - u32 rmid; + u32 rmid, len; u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr)); u8 *pmeas_body = &pdiag_body[3]; - rmid = psta->cmn.aid << 16 + rmid = psta->phl_sta->aid << 16 | pdiag_body[2] << 8 | RM_MASTER; @@ -815,7 +823,7 @@ int rm_recv_radio_mens_rep(_adapter *padapter, prm->p.m_type = pmeas_body[4]; RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, - MAC_ARG(prm->psta->cmn.mac_addr)); + MAC_ARG(prm->psta->phl_sta->mac_addr)); #if (RM_MORE_DBG_MSG) RTW_INFO("RM: element_id = %d\n", prm->p.e_id); @@ -834,9 +842,10 @@ int rm_recv_radio_mens_rep(_adapter *padapter, if ((prm->from_ioctl == true) && prm->q.m_type == bcn_req) { len = pmeas_body[1] + 2; /* 2 : EID(1B) length(1B) */ - indicate_beacon_report(prm->psta->cmn.mac_addr, + indicate_beacon_report(prm->psta->phl_sta->mac_addr, 1, len, pmeas_body); } + return ret; } @@ -867,13 +876,13 @@ int rm_recv_link_mens_req(_adapter *padapter, prm->q.tx_pwr_used = pmeas_body[0]; prm->q.tx_pwr_max = pmeas_body[1]; prm->q.rx_pwr = precv_frame->u.hdr.attrib.phy_info.rx_power; - prm->q.rx_rate = hw_rate_to_m_rate(precv_frame->u.hdr.attrib.data_rate); + prm->q.rx_rate = precv_frame->u.hdr.attrib.data_rate; prm->q.rx_bw = precv_frame->u.hdr.attrib.bw; prm->q.rx_rsni = rm_get_frame_rsni(prm, precv_frame); prm->rmid = rm_gen_rmid(padapter, prm, RM_SLAVE); RTW_INFO("RM: rmid=%x, bssid" MAC_FMT " rx_pwr=%ddBm, rate=%s\n", - prm->rmid, MAC_ARG(prm->psta->cmn.mac_addr), prm->q.rx_pwr, + prm->rmid, MAC_ARG(prm->psta->phl_sta->mac_addr), prm->q.rx_pwr, MGN_RATE_STR(prm->q.rx_rate)); #if (RM_MORE_DBG_MSG) @@ -900,7 +909,7 @@ int rm_recv_link_mens_rep(_adapter *padapter, s8 val; - rmid = psta->cmn.aid << 16 + rmid = psta->phl_sta->aid << 16 | pdiag_body[2] << 8 | RM_MASTER; @@ -912,7 +921,7 @@ int rm_recv_link_mens_rep(_adapter *padapter, } RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, - MAC_ARG(prm->psta->cmn.mac_addr)); + MAC_ARG(prm->psta->phl_sta->mac_addr)); prm->p.action_code = pdiag_body[1]; prm->p.diag_token = pdiag_body[2]; @@ -945,7 +954,7 @@ int rm_radio_mens_nb_rep(_adapter *padapter, struct rm_obj *prm; - rmid = psta->cmn.aid << 16 + rmid = psta->phl_sta->aid << 16 | pdiag_body[2] << 8 | RM_MASTER; @@ -962,7 +971,7 @@ int rm_radio_mens_nb_rep(_adapter *padapter, prm->p.e_id = pmeas_body[0]; RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, - MAC_ARG(prm->psta->cmn.mac_addr)); + MAC_ARG(prm->psta->phl_sta->mac_addr)); #if (RM_MORE_DBG_MSG) RTW_INFO("RM: element_id = %d\n", prm->p.e_id); @@ -970,12 +979,14 @@ int rm_radio_mens_nb_rep(_adapter *padapter, #endif rm_post_event(padapter, prm->rmid, RM_EV_recv_rep); +#ifdef CONFIG_RTW_MBO #ifdef CONFIG_LAYER2_ROAMING if (rtw_wnm_btm_candidates_survey(padapter ,(pdiag_body + 3) ,(len - sizeof(struct rtw_ieee80211_hdr_3addr)) ,_FALSE) == _FAIL) return _FALSE; +#endif #endif rtw_cfg80211_rx_rrm_action(padapter, precv_frame); @@ -1161,7 +1172,7 @@ static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe, } #endif pframe = rtw_set_ie(pframe, eid, - len, ptr+2, &my_len); + len, ptr + 2, &my_len); } /* for() */ break; case bcn_req_rep_detail: @@ -1279,10 +1290,7 @@ static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm, pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); /* ParentTSF */ - val32 = pnetwork->network.PhyInfo.free_cnt; - if (prm->free_run_counter_valid) - val32 += prm->meas_start_time; - + val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt; pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len); /* Generate Beacon detail */ @@ -1301,116 +1309,23 @@ static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm, return pframe; } -#if 0 /* check MBO logo */ -static int rm_match_sub_elem(_adapter *padapter, - struct rm_obj *prm, struct wlan_network *pnetwork) -{ - WLAN_BSSID_EX *pbss = &pnetwork->network; - unsigned int my_len; - int j, k, len; - u8 *plen; - u8 *ptr; - u8 val8, eid; - - - my_len = 0; - /* Reporting Detail values - * 0: No fixed length fields or elements - * 1: All fixed length fields and any requested elements - * in the Request info element if present - * 2: All fixed length fields and elements - * 3-255: Reserved - */ - - /* report_detail != 1 */ - if (prm->q.opt.bcn.rep_detail != 1) - return _TRUE; - - /* report_detail = 1 */ - - for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) { - switch (prm->q.opt.bcn.opt_id[j]) { - case bcn_req_ssid: - /* SSID */ -#if (RM_MORE_DBG_MSG) - RTW_INFO("RM: bcn_req_ssid\n"); -#endif - if (pbss->Ssid.SsidLength == 0) - return _FALSE; - break; - case bcn_req_req: - if (prm->q.opt.bcn.req_start == NULL) - break; -#if (RM_MORE_DBG_MSG) - RTW_INFO("RM: bcn_req_req"); -#endif - for (k=0; kq.opt.bcn.req_len; k++) { - eid = prm->q.opt.bcn.req_start[k]; - - val8 = pbss->IELength - _FIXED_IE_LENGTH_; - ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_, - eid, &len, val8); - -#if (RM_MORE_DBG_MSG) - switch (eid) { - case EID_SsId: - RTW_INFO("RM: EID_SSID\n"); - break; - case EID_QBSSLoad: - RTW_INFO("RM: EID_QBSSLoad\n"); - break; - case EID_HTCapability: - RTW_INFO("RM: EID_HTCapability\n"); - break; - case _MDIE_: - RTW_INFO("RM: EID_MobilityDomain\n"); - break; - case EID_Vendor: - RTW_INFO("RM: EID_Vendor\n"); - break; - default: - RTW_INFO("RM: EID %d todo\n",eid); - break; - } -#endif - if (!ptr) { - RTW_INFO("RM: EID %d not found\n",eid); - return _FALSE; - } - } /* for() */ - break; - case bcn_req_rep_detail: - RTW_INFO("RM: bcn_req_rep_detail\n"); - break; - case bcn_req_ap_ch_rep: - RTW_INFO("RM: bcn_req_ap_ch_rep\n"); - break; - default: - RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]); - break; - } - } - return _TRUE; -} -#endif - static int retrieve_scan_result(struct rm_obj *prm) { - _irqL irqL; _list *plist, *phead; _queue *queue; _adapter *padapter = prm->psta->padapter; struct rtw_ieee80211_channel *pch_set; struct wlan_network *pnetwork = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - int i; + int i, meas_ch_num=0; PWLAN_BSSID_EX pbss; unsigned int matched_network; int len, my_len; u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u16 xframe_ext_sz = SZ_XMITFRAME_EXT; - - tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + tmp_buf = rtw_malloc(xframe_ext_sz); if (tmp_buf == NULL) return 0; @@ -1419,13 +1334,14 @@ static int retrieve_scan_result(struct rm_obj *prm) matched_network = 0; queue = &(pmlmepriv->scanned_queue); - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); /* get requested measurement channel set */ pch_set = prm->q.ch_set; + meas_ch_num = prm->q.ch_set_ch_amount; /* search scan queue to find requested SSID */ while (1) { @@ -1435,17 +1351,13 @@ static int retrieve_scan_result(struct rm_obj *prm) pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); pbss = &pnetwork->network; - #if 0 - RTW_INFO("RM: ooo ch %u ssid %s bssid "MAC_FMT"\n", - pbss->Configuration.DSConfig, pbss->Ssid.Ssid, - MAC_ARG(pbss->MacAddress)); /* * report network if requested channel set contains * the channel matchs selected network */ if (rtw_chset_search_ch(adapter_to_chset(padapter), - pbss->Configuration.DSConfig) < 0) /* not match */ + pbss->Configuration.DSConfig) == 0) goto next; if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig) @@ -1456,10 +1368,9 @@ static int retrieve_scan_result(struct rm_obj *prm) goto next; /* match bssid */ - if (is_wildcard_bssid(prm->q.bssid) == FALSE) + if (is_wildcard_bssid(prm->q.bssid) == _FALSE) if (_rtw_memcmp(prm->q.bssid, pbss->MacAddress, 6) == _FALSE) - //continue; goto next; /* * default wildcard SSID. wildcard SSID: @@ -1485,38 +1396,33 @@ static int retrieve_scan_result(struct rm_obj *prm) /* match condition */ if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) { RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n", - pbss->Configuration.DSConfig, pbss->Ssid.Ssid, + pch_set[i].hw_value, pbss->Ssid.Ssid, MAC_ARG(pbss->MacAddress)); RTW_INFO("RM: condition %u:%u\n", prm->q.opt.bcn.rep_cond.cond, prm->q.opt.bcn.rep_cond.threshold); goto next; - //continue; } -#if 0 /* check MBO logo */ - /* match subelement */ - if (rm_match_sub_elem(padapter, prm, pnetwork) == _FALSE) - goto next; -#endif + /* Found a matched SSID */ matched_network++; RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n", - pbss->Configuration.DSConfig, pbss->Ssid.Ssid, + pch_set[i].hw_value, pbss->Ssid.Ssid, MAC_ARG(pbss->MacAddress)); len = 0; - _rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ); + _rtw_memset(tmp_buf, 0, xframe_ext_sz); rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len); new_packet: if (my_len == 0) { - pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + pbuf = rtw_malloc(xframe_ext_sz); if (pbuf == NULL) goto fail; prm->buf[buf_idx].pbuf = pbuf; } - if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) { + if ((xframe_ext_sz - (my_len + len + 24 + 4)) > 0) { pbuf = rtw_set_fixed_ie(pbuf, len, tmp_buf, &my_len); prm->buf[buf_idx].len = my_len; @@ -1532,16 +1438,16 @@ static int retrieve_scan_result(struct rm_obj *prm) plist = get_next(plist); } /* while() */ fail: - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); if (tmp_buf) - rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ); + rtw_mfree(tmp_buf, xframe_ext_sz); RTW_INFO("RM: Found %d matched %s\n", matched_network, prm->q.opt.bcn.ssid.Ssid); if (prm->buf[buf_idx].pbuf) - return buf_idx+1; + return buf_idx + 1; return 0; } @@ -1555,7 +1461,8 @@ int issue_beacon_rep(struct rm_obj *prm) struct xmit_frame *pmgntframe; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); int pkt_num; - + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u16 xframe_ext_sz = SZ_XMITFRAME_EXT; pkt_num = retrieve_scan_result(prm); @@ -1586,9 +1493,10 @@ int issue_beacon_rep(struct rm_obj *prm) dump_mgntframe(padapter, pmgntframe); } fail: - for (i=0;ibuf[i].pbuf) { - rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ); + rtw_mfree(prm->buf[i].pbuf, xframe_ext_sz); prm->buf[i].pbuf = NULL; prm->buf[i].len = 0; } @@ -1802,7 +1710,7 @@ static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter, unsigned int my_len = 0; struct _RT_OPERATING_CLASS *op; - /* meas mode */ + val8 = bcn_req_active; /* measurement mode T8-64 */ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); @@ -1976,6 +1884,7 @@ int issue_radio_meas_req(struct rm_obj *prm) my_len = 0; plen = pframe + 1; + /* Element ID, Length, Meas token, Meas Mode, Meas type, op class, ch */ pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len); @@ -2019,23 +1928,23 @@ int issue_radio_meas_req(struct rm_obj *prm) int rm_radio_meas_report_cond(struct rm_obj *prm) { u8 val8; - int i; + int i, ret = _FAIL; switch (prm->q.m_type) { case ch_load_req: - val8 = prm->p.ch_load; switch (prm->q.opt.clm.rep_cond.cond) { case ch_load_cond_immediately: - return _SUCCESS; + ret = _SUCCESS; + break; case ch_load_cond_anpi_equal_greater: if (val8 >= prm->q.opt.clm.rep_cond.threshold) - return _SUCCESS; + ret = _SUCCESS; break; case ch_load_cond_anpi_equal_less: if (val8 <= prm->q.opt.clm.rep_cond.threshold) - return _SUCCESS; + ret = _SUCCESS; break; default: break; @@ -2045,14 +1954,15 @@ int rm_radio_meas_report_cond(struct rm_obj *prm) val8 = prm->p.anpi; switch (prm->q.opt.nhm.rep_cond.cond) { case noise_histo_cond_immediately: - return _SUCCESS; + ret = _SUCCESS; + break; case noise_histo_cond_anpi_equal_greater: if (val8 >= prm->q.opt.nhm.rep_cond.threshold) - return _SUCCESS; + ret = _SUCCESS; break; case noise_histo_cond_anpi_equal_less: if (val8 <= prm->q.opt.nhm.rep_cond.threshold) - return _SUCCESS; + ret = _SUCCESS; break; default: break; @@ -2061,12 +1971,14 @@ int rm_radio_meas_report_cond(struct rm_obj *prm) default: break; } - return _FAIL; + return ret; } int retrieve_radio_meas_result(struct rm_obj *prm) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter); +#ifdef CONFIG_RTW_ACS + struct dvobj_priv *dvobj = adapter_to_dvobj(prm->psta->padapter); +#endif int i, ch = -1; u8 val8; @@ -2081,7 +1993,7 @@ int retrieve_radio_meas_result(struct rm_obj *prm) switch (prm->q.m_type) { case ch_load_req: -#ifdef CONFIG_RTW_ACS +#if 0 /* def CONFIG_RTW_ACS */ val8 = hal_data->acs.clm_ratio[ch]; #else val8 = 0; @@ -2089,14 +2001,13 @@ int retrieve_radio_meas_result(struct rm_obj *prm) prm->p.ch_load = val8; break; case noise_histo_req: -#ifdef CONFIG_RTW_ACS +#if 0 /* def CONFIG_RTW_ACS */ /* ANPI */ prm->p.anpi = hal_data->acs.nhm_ratio[ch]; /* IPI 0~10 */ for (i=0;i<11;i++) prm->p.ipi[i] = hal_data->acs.nhm[ch][i]; - #else val8 = 0; prm->p.anpi = val8; @@ -2207,6 +2118,17 @@ void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data)); } +void update_rm_cap(u8 *frame_head, _adapter *pa, u32 pktlen, int offset) +{ + u8 *res; + sint len; + + res = rtw_get_ie(frame_head + offset, _EID_RRM_EN_CAP_IE_, &len, + pktlen - offset); + if (res != NULL) + _rtw_memcpy((void *)pa->rmpriv.rm_en_cap_def, (res + 2), len); +} + /* Debug command */ #if (RM_SUPPORT_IWPRIV_DBG) @@ -2254,14 +2176,13 @@ static char * hwaddr_parse(char *txt, u8 *addr) void rm_dbg_list_sta(_adapter *padapter, char *s) { int i; - _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; _list *plist, *phead; sprintf(pstr(s), "\n"); - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(pstapriv->sta_hash[i]); plist = get_next(phead); @@ -2274,15 +2195,15 @@ void rm_dbg_list_sta(_adapter *padapter, char *s) sprintf(pstr(s), "=========================================\n"); sprintf(pstr(s), "mac=" MAC_FMT "\n", - MAC_ARG(psta->cmn.mac_addr)); + MAC_ARG(psta->phl_sta->mac_addr)); sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n", - psta->state, psta->cmn.aid, psta->cmn.mac_id); + psta->state, psta->phl_sta->aid, psta->phl_sta->macid); sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap)); } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); sprintf(pstr(s), "=========================================\n"); } @@ -2310,13 +2231,12 @@ void rm_dbg_help(_adapter *padapter, char *s) struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid) { int i; - _irqL irqL; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; _list *plist, *phead; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(pstapriv->sta_hash[i]); @@ -2328,10 +2248,10 @@ struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid) plist = get_next(plist); - if (psta->cmn.aid == aid) + if (psta->phl_sta->aid == aid) goto done; - if (pbssid && _rtw_memcmp(psta->cmn.mac_addr, + if (pbssid && _rtw_memcmp(psta->phl_sta->mac_addr, pbssid, 6)) goto done; } @@ -2339,19 +2259,20 @@ struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid) } psta = NULL; done: - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); return psta; } static int rm_dbg_modify_meas(_adapter *padapter, char *s) { struct rm_priv *prmpriv = &padapter->rmpriv; + struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; struct rm_obj *prm; struct sta_info *psta; char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn, *plnk; unsigned val; u8 bssid[ETH_ALEN]; - + int i; /* example : * rrm add_meas ,m=, @@ -2379,6 +2300,8 @@ static int rm_dbg_modify_meas(_adapter *padapter, char *s) prm->q.m_token = rm_gen_meas_token(padapter); psta = prm->psta; + for (i=0;i<6;i++) + prm->q.bssid[i] = 0xff; /* wildcard bssid */ if (paid) { /* find sta_info according to aid */ paid += 4; /* skip aid= */ sscanf(paid, "%u", &val); /* aid=x */ @@ -2395,6 +2318,7 @@ static int rm_dbg_modify_meas(_adapter *padapter, char *s) if (psta) { prm->psta = psta; + prm->q.diag_token = rm_gen_dialog_token(padapter); prm->rmid = rm_gen_rmid(padapter, prm, RM_MASTER); } else @@ -2444,7 +2368,7 @@ static void rm_dbg_activate_meas(_adapter *padapter, char *s) } /* measure current channel */ - prm->q.ch_num = padapter->mlmeextpriv.cur_channel; + prm->q.ch_num = padapter->mlmeextpriv.chandef.chan; prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num); /* enquee rmobj */ @@ -2455,7 +2379,7 @@ static void rm_dbg_activate_meas(_adapter *padapter, char *s) rm_type_req_name(prm->q.m_type)); sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n", - prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr)); + prm->psta->phl_sta->aid, MAC_ARG(prm->psta->phl_sta->mac_addr)); /* clearn inActivate prm info */ prmpriv->prm_sel = NULL; @@ -2467,7 +2391,6 @@ int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch, u8 reporting_detail, u8 n_ap_ch_rpt, struct _RT_OPERATING_CLASS *rpt, u8 n_elem_id, u8 *elem_id_list) - { struct rm_obj *prm; char *pact; @@ -2543,6 +2466,7 @@ int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch, prm->q.opt.bcn.req_id_num = n_elem_id; _rtw_memcpy(prm->q.opt.bcn.req_id, elem_id_list, n_elem_id); } + /* enquee rmobj */ rm_enqueue_rmobj(padapter, prm, _FALSE); @@ -2550,7 +2474,7 @@ int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch, prm->rmid, rm_type_req_name(prm->q.m_type)); if (prm->psta) - RTW_INFO("mac="MAC_FMT"\n", MAC_ARG(prm->psta->cmn.mac_addr)); + RTW_INFO("mac="MAC_FMT"\n", MAC_ARG(prm->psta->phl_sta->mac_addr)); return 0; } @@ -2558,9 +2482,6 @@ void indicate_beacon_report(u8 *sta_addr, u8 n_measure_rpt, u32 elem_len, u8 *elem) { RTW_INFO("RM: recv bcn reprot from mac="MAC_FMT"\n", MAC_ARG(sta_addr)); -#ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_nl_beacon_report_event(sta_addr, n_measure_rpt, elem_len, elem); -#endif } static void rm_dbg_add_meas(_adapter *padapter, char *s) @@ -2601,7 +2522,7 @@ static void rm_dbg_add_meas(_adapter *padapter, char *s) if (prm->psta) sprintf(pstr(s), "mac="MAC_FMT"\n", - MAC_ARG(prm->psta->cmn.mac_addr)); + MAC_ARG(prm->psta->phl_sta->mac_addr)); if (pact) rm_dbg_activate_meas(padapter, pstr(s)); @@ -2681,7 +2602,7 @@ static void rm_dbg_show_meas(struct rm_obj *prm, char *s) if (psta) sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n", - psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr)); + psta->phl_sta->aid, MAC_ARG(psta->phl_sta->mac_addr)); sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n", (int)ATOMIC_READ(&prm->pclock->counter), @@ -2691,16 +2612,15 @@ static void rm_dbg_show_meas(struct rm_obj *prm, char *s) static void rm_dbg_list_meas(_adapter *padapter, char *s) { int meas_amount; - _irqL irqL; struct rm_obj *prm; struct sta_info *psta; struct rm_priv *prmpriv = &padapter->rmpriv; _queue *queue = &prmpriv->rm_queue; _list *plist, *phead; - + unsigned long sp_flags; sprintf(pstr(s), "\n"); - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); phead = get_list_head(queue); plist = get_next(phead); meas_amount = 0; @@ -2714,7 +2634,7 @@ static void rm_dbg_list_meas(_adapter *padapter, char *s) rm_dbg_show_meas(prm, s); } - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); sprintf(pstr(s), "=========================================\n"); @@ -2757,7 +2677,7 @@ int verify_bcn_req(_adapter *padapter, struct sta_info *psta) /* 6, OP_CLASS_12 */ { 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}} }; - rm_send_bcn_reqs(padapter, psta->cmn.mac_addr, op_class, ch, + rm_send_bcn_reqs(padapter, psta->phl_sta->mac_addr, op_class, ch, measure_duration, measure_mode, bssid, ssid, reporting_detaial, n_ap_ch_rpt, US, req_len, req); return 0; diff --git a/core/rtw_rm_fsm.c b/core/rtw_rm_fsm.c index 244b799..aabe7ac 100644 --- a/core/rtw_rm_fsm.c +++ b/core/rtw_rm_fsm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -14,7 +14,6 @@ *****************************************************************************/ #include -#include #ifdef CONFIG_RTW_80211K #include "rtw_rm_fsm.h" #include "rtw_rm_util.h" @@ -116,13 +115,13 @@ int rtw_init_rm(_adapter *padapter) /*| BIT(RM_ANT_CAP_EN - 32)*/; prmpriv->enable = _TRUE; + prmpriv->meas_token = 1; /* clock timer */ rtw_init_timer(&prmpriv->rm_timer, - padapter, rm_timer_callback, padapter); + rm_timer_callback, padapter); _set_timer(&prmpriv->rm_timer, CLOCK_UNIT); - prmpriv->meas_token = 1; return _SUCCESS; } @@ -157,20 +156,19 @@ int rtw_free_rm_priv(_adapter *padapter) static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head) { - _irqL irqL; - + unsigned long sp_flags; if (obj == NULL) return _FAIL; - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); if (to_head) rtw_list_insert_head(&obj->list, &queue->queue); else rtw_list_insert_tail(&obj->list, &queue->queue); - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return _SUCCESS; } @@ -258,20 +256,19 @@ struct rm_obj *rm_alloc_rmobj(_adapter *padapter) int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head) { - _irqL irqL; struct rm_priv *prmpriv = &padapter->rmpriv; _queue *queue = &prmpriv->rm_queue; - + unsigned long sp_flags; if (prm == NULL) return _FAIL; - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); if (to_head) rtw_list_insert_head(&prm->list, &queue->queue); else rtw_list_insert_tail(&prm->list, &queue->queue); - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); rm_state_initial(prm); @@ -280,11 +277,10 @@ int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head) static struct rm_obj *rm_dequeue_rm(_queue *queue) { - _irqL irqL; struct rm_obj *prm; + unsigned long sp_flags; - - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); if (rtw_is_list_empty(&(queue->queue))) prm = NULL; else { @@ -292,18 +288,17 @@ static struct rm_obj *rm_dequeue_rm(_queue *queue) struct rm_obj, list); /* rtw_list_delete(&prm->list); */ } - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return prm; } static struct rm_event *rm_dequeue_ev(_queue *queue) { - _irqL irqL; struct rm_event *ev; + unsigned long sp_flags; - - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); if (rtw_is_list_empty(&(queue->queue))) ev = NULL; else { @@ -311,22 +306,21 @@ static struct rm_event *rm_dequeue_ev(_queue *queue) struct rm_event, list); rtw_list_delete(&ev->list); } - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return ev; } static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid) { - _irqL irqL; _list *phead, *plist; struct rm_obj *prm = NULL; - + unsigned long sp_flags; if (rmid == 0) return NULL; - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); phead = get_list_head(queue); plist = get_next(phead); @@ -334,12 +328,12 @@ static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid) prm = LIST_CONTAINOR(plist, struct rm_obj, list); if (rmid == (prm->rmid)) { - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return prm; } plist = get_next(plist); } - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return NULL; } @@ -369,7 +363,7 @@ u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid) { struct cmd_obj *pcmd; struct rm_event *pev; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; u8 res = _SUCCESS; @@ -378,6 +372,8 @@ u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid) res = _FAIL; goto exit; } + pcmd->padapter = padapter; + pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event)); if (pev == NULL) { @@ -420,20 +416,19 @@ int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid) pev->evid = evid; RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid); - rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE); + rm_enqueue_ev(&prmpriv->ev_queue, pev, _FALSE); return _SUCCESS; } static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev) { - _irqL irqL; _list *phead, *plist; _queue *queue = &padapter->rmpriv.rm_queue; struct rm_obj *prm; + unsigned long sp_flags; - - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); phead = get_list_head(queue); plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { @@ -441,12 +436,12 @@ static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev) prm = LIST_CONTAINOR(plist, struct rm_obj, list); plist = get_next(plist); if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) { - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); rm_state_run(prm, pev->evid); - _enter_critical(&queue->lock, &irqL); + _rtw_spinlock_irq(&queue->lock, &sp_flags); } } - _exit_critical(&queue->lock, &irqL); + _rtw_spinunlock_irq(&queue->lock, &sp_flags); return; } @@ -544,7 +539,7 @@ static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid) * phydm measure current ch periodically * scan current ch is not necessary */ - val8 = padapter->mlmeextpriv.cur_channel; + val8 = padapter->mlmeextpriv.chandef.chan; if (prm->q.ch_num == val8) prm->poll_mode = 1; } @@ -588,8 +583,11 @@ static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid) return _SUCCESS; } if (prm->q.rand_intvl) { + #if 0 /*GEORGIA_TODO_REDEFINE_IO*/ /* get low tsf to generate random interval */ val32 = rtw_read32(padapter, REG_TSFTR); + #endif + val32 = rtw_hal_get_ltsf(padapter); val32 = val32 % prm->q.rand_intvl; RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n", prm->rmid, (int)prm->q.rand_intvl,val32); @@ -629,6 +627,7 @@ static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid) if (prm->q.m_mode == bcn_req_bcn_table) { RTW_INFO("RM: rmid=%x Beacon table\n", prm->rmid); + rm_get_chset(prm); _rm_post_event(padapter, prm->rmid, RM_EV_survey_done); return _SUCCESS; @@ -669,9 +668,8 @@ static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid) switch (prm->q.m_type) { case bcn_req: val8 = 1; /* Enable free run counter */ - prm->free_run_counter_valid = rtw_hal_set_hwreg( - padapter, HW_VAR_FREECNT, &val8); - + rtw_hal_set_hwreg(padapter, + HW_VAR_FREECNT, &val8); rm_sitesurvey(prm); break; case ch_load_req: diff --git a/core/rtw_rm_util.c b/core/rtw_rm_util.c index b0c2428..e53169f 100644 --- a/core/rtw_rm_util.c +++ b/core/rtw_rm_util.c @@ -14,7 +14,6 @@ *****************************************************************************/ #include -#include #ifdef CONFIG_RTW_80211K #include "rtw_rm_fsm.h" #include "rtw_rm_util.h" @@ -147,54 +146,54 @@ u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork) u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe) { int i; - u8 val8, snr, rx_num; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter); - + u8 val8 = 0, snr; + struct dvobj_priv *dvobj = adapter_to_dvobj(prm->psta->padapter); + u8 rf_path = GET_HAL_RFPATH_NUM(dvobj); +#if 0 if (IS_CCK_RATE((hw_rate_to_m_rate(pframe->u.hdr.attrib.data_rate)))) val8 = 255; else { - snr = rx_num = 0; - for (i = 0; i < hal_spec->rf_reg_path_num; i++) { - if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) { - snr += pframe->u.hdr.attrib.phy_info.rx_snr[i]; - rx_num++; - } - } - snr = snr / rx_num; + snr = 0; + for (i = 0; i < rf_path; i++) + snr += pframe->u.hdr.attrib.phy_info.rx_snr[i]; + snr = snr / rf_path; val8 = (u8)(snr + 10)*2; } +#endif return val8; } u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork) { int i; - u8 val8, snr, rx_num; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter); + u8 val8, snr; + struct dvobj_priv *dvobj = adapter_to_dvobj(prm->psta->padapter); + u8 rf_path = GET_HAL_RFPATH_NUM(dvobj); + if (pnetwork->network.PhyInfo.is_cck_rate) { /* current HW doesn't have CCK RSNI */ /* 255 indicates RSNI is unavailable */ val8 = 255; } else { - snr = rx_num = 0; - for (i = 0; i < hal_spec->rf_reg_path_num; i++) { - if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) { - snr += pnetwork->network.PhyInfo.rx_snr[i]; - rx_num++; - } + snr = 0; + for (i = 0; i < rf_path; i++) { + snr += pnetwork->network.PhyInfo.rx_snr[i]; } - snr = snr / rx_num; + snr = snr / rf_path; val8 = (u8)(snr + 10)*2; } return val8; } /* output: pwr (unit dBm) */ -int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr) +int rm_get_tx_power(_adapter *adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr) { - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); +#if 0 /*GEORGIA_TODO_FIXIT*/ + + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj); + HAL_DATA_TYPE *hal_data = GET_PHL_COM(dvobj); int tx_num, band, bw, ch, n, rs; u8 base; s8 limt_offset = 127; /* max value of s8 */ @@ -216,11 +215,55 @@ int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 } *pwr = phy_get_tx_power_final_absolute_value(adapter, path, rate, bw, ch); +#endif + return 0; +} + +u8 rm_gen_dialog_token(_adapter *padapter) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + do { + pmlmeinfo->dialogToken++; + } while (pmlmeinfo->dialogToken == 0); + + return pmlmeinfo->dialogToken; +} + +u8 rm_gen_meas_token(_adapter *padapter) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + + do { + prmpriv->meas_token++; + } while (prmpriv->meas_token == 0); + + return prmpriv->meas_token; +} + +u32 rm_gen_rmid(_adapter *padapter, struct rm_obj *prm, u8 role) +{ + u32 rmid; + + if (prm->psta == NULL) + goto err; + + if (prm->q.diag_token == 0) + goto err; + + rmid = prm->psta->phl_sta->aid << 16 + | prm->q.diag_token << 8 + | role; + return rmid; +err: + RTW_ERR("RM: unable to gen rmid\n"); return 0; } -int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr) +int rm_get_rx_sensitivity(_adapter *adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr) { s8 rx_sensitivity = -110; @@ -403,8 +446,11 @@ int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE /* output: path_a max tx power in dBm */ int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a) { - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); +#if 0 /*GEORGIA_TODO_FIXIT*/ + + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj); + HAL_DATA_TYPE *hal_data = GET_PHL_COM(dvobj); int path, tx_num, band, bw, ch, n, rs; u8 rate_num; s8 max_pwr[RF_PATH_MAX], pwr; @@ -451,50 +497,7 @@ int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a) RTW_INFO("RM: path_a max_pwr=%ddBm\n", max_pwr[0]); #endif *path_a = max_pwr[0]; - return 0; -} - -u8 rm_gen_dialog_token(_adapter *padapter) -{ - struct rm_priv *prmpriv = &(padapter->rmpriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - - do { - pmlmeinfo->dialogToken++; - } while (pmlmeinfo->dialogToken == 0); - - return pmlmeinfo->dialogToken; -} - -u8 rm_gen_meas_token(_adapter *padapter) -{ - struct rm_priv *prmpriv = &(padapter->rmpriv); - - do { - prmpriv->meas_token++; - } while (prmpriv->meas_token == 0); - - return prmpriv->meas_token; -} - -u32 rm_gen_rmid(_adapter *padapter, struct rm_obj *prm, u8 role) -{ - u32 rmid; - - if (prm->psta == NULL) - goto err; - - if (prm->q.diag_token == 0) - goto err; - - rmid = prm->psta->cmn.aid << 16 - | prm->q.diag_token << 8 - | role; - - return rmid; -err: - RTW_ERR("RM: unable to gen rmid\n"); +#endif return 0; } diff --git a/core/rtw_scan.c b/core/rtw_scan.c new file mode 100644 index 0000000..6634e11 --- /dev/null +++ b/core/rtw_scan.c @@ -0,0 +1,3435 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include + +/*rtw_mlme.c*/ +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm)); + pparm->scan_mode = pmlmepriv->scan_mode; +} + +#ifdef CONFIG_SET_SCAN_DENY_TIMER +inline bool rtw_is_scan_deny(_adapter *adapter) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE; +} +inline void rtw_clear_scan_deny(_adapter *adapter) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + ATOMIC_SET(&mlmepriv->set_scan_deny, 0); + if (0) + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); +} + +void rtw_set_scan_deny_timer_hdl(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + + rtw_clear_scan_deny(adapter); +} +void rtw_set_scan_deny(_adapter *adapter, u32 ms) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + if (0) + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + ATOMIC_SET(&mlmepriv->set_scan_deny, 1); + _set_timer(&mlmepriv->set_scan_deny_timer, ms); +} +#endif + +void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) +{ + struct sitesurvey_parm parm; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + int i; +#if 1 + u8 ssc_chk; + + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + if( ssc_chk == SS_DENY_BUSY_TRAFFIC) { + #ifdef CONFIG_LAYER2_ROAMING + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + } else + #endif + { + RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + } else if (ssc_chk != SS_ALLOW) { + goto exit; + } + + if (!rtw_is_adapter_up(padapter)) + goto exit; +#else + if (rtw_is_scan_deny(padapter)) + goto exit; + + if (!rtw_is_adapter_up(padapter)) + goto exit; + + if (rtw_mi_busy_traffic_check(padapter)) { +#ifdef CONFIG_LAYER2_ROAMING + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) { + RTW_INFO("need to roam, don't care BusyTraffic\n"); + } else +#endif + { + RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + } + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + if (check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" WIFI_UNDER_SURVEY|WIFI_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS))) { + RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } +#endif +#endif + + RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason); + + /* only for 20/40 BSS */ + if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) { + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;i<14;i++) { + parm.ch[i].hw_value = i + 1; + parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + } + parm.ch_num = 14; + rtw_sitesurvey_cmd(padapter, &parm); + goto exit; + } + +#ifdef CONFIG_RTW_MBO +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + if ((reason == RTW_AUTO_SCAN_REASON_ROAM) + && (rtw_roam_nb_scan_list_set(padapter, &parm))) + goto exit; +#endif +#endif + + rtw_sitesurvey_cmd(padapter, NULL); +exit: + return; +} + +#ifdef CONFIG_RTW_ACS +u8 rtw_set_acs_sitesurvey(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct sitesurvey_parm parm; + u8 uch; + u8 ch_num = 0; + int i; + enum band_type band; + u8 (*center_chs_num)(u8) = NULL; + u8 (*center_chs)(u8, u8) = NULL; + u8 ret = _FAIL; + + if (!rtw_mi_get_ch_setting_union(adapter, &uch, NULL, NULL)) + goto exit; + + _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm)); + parm.scan_mode = RTW_PHL_SCAN_PASSIVE; + parm.bw = CHANNEL_WIDTH_20; + parm.acs = 1; + + for (band = BAND_ON_24G; band < BAND_MAX; band++) { + if (band == BAND_ON_24G) { + center_chs_num = center_chs_2g_num; + center_chs = center_chs_2g; + } else + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G) { + center_chs_num = center_chs_5g_num; + center_chs = center_chs_5g; + } else + #endif + { + center_chs_num = NULL; + center_chs = NULL; + } + + if (!center_chs_num || !center_chs) + continue; + + if (rfctl->ch_sel_within_same_band) { + if (rtw_is_2g_ch(uch) && band != BAND_ON_24G) + continue; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (rtw_is_5g_ch(uch) && band != BAND_ON_5G) + continue; + #endif + } + + ch_num = center_chs_num(CHANNEL_WIDTH_20); + for (i = 0; i < ch_num && parm.ch_num < RTW_CHANNEL_SCAN_AMOUNT; i++) { + parm.ch[parm.ch_num].hw_value = center_chs(CHANNEL_WIDTH_20, i); + parm.ch[parm.ch_num].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + parm.ch_num++; + } + } + + ret = rtw_sitesurvey_cmd(adapter, &parm); + +exit: + return ret; +} +#endif /* CONFIG_RTW_ACS */ + +static u32 _rtw_wait_scan_done(_adapter *adapter, u32 timeout_ms) +{ + systime start; + u32 pass_ms; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + u8 abort_timeout = false; + + start = rtw_get_current_time(); + + while ((rtw_cfg80211_get_is_roch(adapter) == _TRUE || check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) + && rtw_get_passing_time_ms(start) <= timeout_ms) { + + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) + break; + + RTW_INFO(FUNC_NDEV_FMT"fw_state=WIFI_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev)); + rtw_msleep_os(20); + abort_timeout = true; + } + + if (_TRUE == abort_timeout && check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) { + if (!RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) + RTW_ERR(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", + FUNC_NDEV_ARG(adapter->pnetdev)); + pmlmeext->scan_abort_to = _TRUE; + #ifdef CONFIG_PLATFORM_MSTAR + /*_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);*/ + /*set_survey_timer(pmlmeext, 0);*/ + mlme_set_scan_to_timer(pmlmepriv, 50); + #endif + rtw_indicate_scan_done(adapter, _TRUE); + } + + pmlmeext->scan_abort = _FALSE; + RTW_INFO(FUNC_ADPT_FMT "- %s....scan_abort:%d\n", + FUNC_ADPT_ARG(adapter), __func__, pmlmeext->scan_abort); + pass_ms = rtw_get_passing_time_ms(start); + + RTW_INFO("%s scan timeout value:%d ms, total take:%d ms\n", + __func__, timeout_ms, pass_ms); + return pass_ms; +} + +/* +* timeout_ms > 0:rtw_scan_abort_timeout , = 0:rtw_scan_wait_completed +*/ +u32 rtw_scan_abort(_adapter *adapter, u32 timeout_ms) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + u32 pass_ms = 0; + + if (rtw_cfg80211_get_is_roch(adapter) == _TRUE || check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) { + pmlmeext->scan_abort = _TRUE; + RTW_INFO(FUNC_ADPT_FMT "- %s....scan_abort:%d\n", + FUNC_ADPT_ARG(adapter), __func__, pmlmeext->scan_abort); + rtw_sctx_init(&pmlmeext->sitesurvey_res.sctx, timeout_ms); + + #ifdef CONFIG_CMD_SCAN + if (pmlmeext->sitesurvey_res.scan_param) + psts = rtw_phl_cmd_scan_cancel(adapter_to_dvobj(adapter)->phl, + pmlmeext->sitesurvey_res.scan_param); + #else + psts = rtw_phl_scan_cancel(adapter_to_dvobj(adapter)->phl); + #endif + + if (psts == RTW_PHL_STATUS_SUCCESS) + rtw_sctx_wait(&pmlmeext->sitesurvey_res.sctx, __func__); + pass_ms = _rtw_wait_scan_done(adapter, timeout_ms); + } + return pass_ms; +} + +void rtw_scan_abort_no_wait(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + #ifdef CONFIG_CMD_SCAN + if (pmlmeext->sitesurvey_res.scan_param) + rtw_phl_cmd_scan_cancel(adapter_to_dvobj(adapter)->phl, + pmlmeext->sitesurvey_res.scan_param); + #else + rtw_phl_scan_cancel(adapter_to_dvobj(adapter)->phl); + #endif +} + +/* +* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey +* @adapter: pointer to _adapter structure +*/ +void rtw_scan_timeout_handler(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + + rtw_scan_abort_no_wait(adapter); +#if 0 + _rtw_spinlock_bh(&pmlmepriv->lock); + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + _rtw_spinunlock_bh(&pmlmepriv->lock); + + #ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_surveydone_event_callback(adapter); + #endif /* CONFIG_IOCTL_CFG80211 */ + rtw_indicate_scan_done(adapter, _TRUE); +#endif +} + +static inline bool _rtw_scan_abort_check(_adapter *adapter, const char *caller) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct submit_ctx *sctx = &pmlmeext->sitesurvey_res.sctx; + + RTW_INFO(FUNC_ADPT_FMT "- %s....scan_abort:%d\n", + FUNC_ADPT_ARG(adapter), __func__, pmlmeext->scan_abort); + + if (pmlmeext->scan_abort == _FALSE) + return _FALSE; + + if (pmlmeext->scan_abort_to) { + RTW_ERR("%s scan abort timeout\n", caller); + rtw_warn_on(1); + } + _cancel_timer_ex(&pmlmepriv->scan_to_timer); + pmlmeext->scan_abort = _FALSE; + pmlmeext->scan_abort_to = _FALSE; + if (sctx) { + RTW_INFO("%s scan abort .....(%d ms)\n", caller, rtw_get_passing_time_ms(sctx->submit_time)); + rtw_sctx_done(&sctx); + } + return _TRUE; +} +static struct wlan_network *alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ +{ + struct wlan_network *pnetwork; + pnetwork = _rtw_alloc_network(pmlmepriv); + return pnetwork; +} + +static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork))) { + + /* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */ + { + rtw_update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE); + rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs), + pmlmepriv->cur_network.network.IELength); + } + } +} + +/*Caller must hold pmlmepriv->lock first.*/ +static bool update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +{ + _list *plist, *phead; + u32 bssid_ex_sz; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(adapter->wdinfo); +#endif /* CONFIG_P2P */ + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *choice = NULL; + int target_find = 0; + bool update_ie = _FALSE; + + _rtw_spinlock_bh(&queue->lock); + phead = get_list_head(queue); + plist = get_next(phead); + +#if 0 + RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n", + __func__, target->Ssid.Ssid, target->PhyInfo.rssi, target->PhyInfo.SignalStrength); +#endif + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + +#ifdef CONFIG_P2P + if (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) && + _rtw_memcmp(pnetwork->network.Ssid.Ssid, "DIRECT-", 7) && + rtw_get_p2p_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, + pnetwork->network.IELength - _FIXED_IE_LENGTH_, + NULL, NULL)) { + target_find = 1; + break; + } +#endif + + if (is_same_network(&(pnetwork->network), target)) { + target_find = 1; + break; + } + + if (rtw_roam_flags(adapter)) { + /* TODO: don't select netowrk in the same ess as choice if it's new enough*/ + } + if (pnetwork->fixed) { + plist = get_next(plist); + continue; + } + +#ifdef CONFIG_RSSI_PRIORITY + if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength)) + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + choice = pnetwork; +#else + if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned)) + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + choice = pnetwork; +#endif + plist = get_next(plist); + + } + + + /* If we didn't find a match, then get a new network slot to initialize + * with this beacon's information */ + /* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */ + if (!target_find) { + if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { + /* If there are no more slots, expire the choice */ + /* list_del_init(&choice->list); */ + pnetwork = choice; + if (pnetwork == NULL) + goto unlock_scan_queue; + +#ifdef CONFIG_RSSI_PRIORITY + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%d , ss:%d)\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.PhyInfo.rssi, pnetwork->network.PhyInfo.SignalStrength); +#else + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); +#endif + + _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); + pnetwork->bcn_keys_valid = 0; + if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) + rtw_update_bcn_keys_of_network(pnetwork); + /* variable initialize */ + pnetwork->fixed = _FALSE; + pnetwork->last_scanned = rtw_get_current_time(); + pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned; + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + pnetwork->acnode_stime = 0; + pnetwork->acnode_notify_etime = 0; + #endif + + pnetwork->network_type = 0; + pnetwork->aid = 0; + pnetwork->join_res = 0; + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + } else { + /* Otherwise just pull from the free list */ + + pnetwork = alloc_network(pmlmepriv); /* will update scan_time */ + if (pnetwork == NULL) + goto unlock_scan_queue; + + bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); + target->Length = bssid_ex_sz; + + _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz); + pnetwork->bcn_keys_valid = 0; + if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) + rtw_update_bcn_keys_of_network(pnetwork); + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + + rtw_list_insert_tail(&(pnetwork->list), &(queue->queue)); + + } + } else { + /* we have an entry and we are going to update it. But this entry may + * be already expired. In this case we do the same as we found a new + * net and call the new_net handler + */ + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + systime last_scanned = pnetwork->last_scanned; + #endif + struct beacon_keys bcn_keys; + bool bcn_keys_valid = 0; + bool is_hidden_ssid_ap = 0; + + pnetwork->last_scanned = rtw_get_current_time(); + + if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) { + if (target->InfrastructureMode == Ndis802_11Infrastructure) { + is_hidden_ssid_ap = hidden_ssid_ap(target); + if (!is_hidden_ssid_ap) /* update last time it's non hidden ssid AP */ + pnetwork->last_non_hidden_ssid_ap = rtw_get_current_time(); + } + bcn_keys_valid = rtw_get_bcn_keys_from_bss(target, &bcn_keys); + } + + if (target->InfrastructureMode == Ndis802_11_mesh + || target->Reserved[0] >= pnetwork->network.Reserved[0]) + update_ie = _TRUE; + else if (target->InfrastructureMode == Ndis802_11Infrastructure && !pnetwork->fixed + && rtw_get_passing_time_ms(pnetwork->last_non_hidden_ssid_ap) > SCANQUEUE_LIFETIME) + update_ie = _TRUE; + else if (bcn_keys_valid) { + if (is_hidden_ssid(bcn_keys.ssid, bcn_keys.ssid_len)) { + /* hidden ssid, replace with current beacon ssid directly */ + _rtw_memcpy(bcn_keys.ssid, pnetwork->bcn_keys.ssid, pnetwork->bcn_keys.ssid_len); + bcn_keys.ssid_len = pnetwork->bcn_keys.ssid_len; + } + if (rtw_bcn_key_compare(&pnetwork->bcn_keys, &bcn_keys) == _FALSE) + update_ie = _TRUE; + } + + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig + || rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms + || !rtw_bss_is_same_mbss(&pnetwork->network, target) + ) { + pnetwork->acnode_stime = 0; + pnetwork->acnode_notify_etime = 0; + } + #endif + + if (bcn_keys_valid) { + _rtw_memcpy(&pnetwork->bcn_keys, &bcn_keys, sizeof(bcn_keys)); + pnetwork->bcn_keys_valid = 1; + } else if (update_ie) + pnetwork->bcn_keys_valid = 0; + + rtw_update_network(&(pnetwork->network), target, adapter, update_ie); + } + + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) + rtw_mesh_update_scanned_acnode_status(adapter, pnetwork); + #endif + +unlock_scan_queue: + _rtw_spinunlock_bh(&queue->lock); + +#ifdef CONFIG_RTW_MESH + if (pnetwork && MLME_IS_MESH(adapter) + && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) + && !check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) + ) + rtw_chk_candidate_peer_notify(adapter, pnetwork); +#endif + + return update_ie; +} + +static void add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + bool update_ie; + /* _queue *queue = &(pmlmepriv->scanned_queue); */ + /* _rtw_spinlock_bh(&queue->lock); */ + +#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) + if (adapter->registrypriv.wifi_spec == 0) + rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); +#endif + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST + if (adapter->registrypriv.ignore_go_in_scan) { + if(rtw_chk_p2p_wildcard_ssid(pnetwork) == _SUCCESS || + rtw_chk_p2p_ie(pnetwork) == _SUCCESS) + return; + } + /*100 was follow n & ac IC setting SignalStrength rang was 0~100*/ + if(adapter->registrypriv->ignore_low_rssi_in_scan != 0xff && + pnetwork->PhyInfo.rssi < (adapter->registrypriv->ignore_low_rssi_in_scan - 100)) + return; +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) + rtw_bss_ex_del_wfd_ie(pnetwork); + + /* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */ + update_ie = update_scanned_network(adapter, pnetwork); + + if (update_ie) + update_current_network(adapter, pnetwork); + + /* _rtw_spinunlock_bh(&queue->lock); */ + +} + +#ifdef CONFIG_STA_MULTIPLE_BSSID +static inline void rtw_gen_new_bssid(const u8 *bssid, u8 max_bssid_ind, + u8 mbssid_index, u8 *new_bssid) +{ + u8 i = 0; + u8 max_num = 1; + u8 B; + u8 new_a5; + + for (i = 0; i < max_bssid_ind; i++) + max_num = max_num * 2; + /*RTW_INFO("%s, max_num=%d\n", __func__, max_num);*/ + /*RTW_INFO("%s, %02x,%02x,%02x,%02x,%02x,%02x \n", __func__, bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);*/ + + B = bssid[5] % max_num; + + new_a5 = bssid[5] - B + ((B + mbssid_index) % max_num); + + new_bssid[0] = bssid[0]; + new_bssid[1] = bssid[1]; + new_bssid[2] = bssid[2]; + new_bssid[3] = bssid[3]; + new_bssid[4] = bssid[4]; + new_bssid[5] = new_a5; + + /*RTW_INFO("%s, %02x,%02x,%02x,%02x,%02x,%02x \n", __func__, new_bssid[0], new_bssid[1], new_bssid[2], new_bssid[3], new_bssid[4], new_bssid[5]);*/ +} + +void add_mbssid_network(_adapter *padapter, WLAN_BSSID_EX *ref_bss) +{ + WLAN_BSSID_EX *pbss; + u32 sub_ies_len; + u8 *mbssid_ie_ptr = NULL; + PNDIS_802_11_VARIABLE_IEs pIE, sub_pie; + u8 max_bssid_indicator; + int i,j; + u8* mbssid_ie; + sint mbssid_len; + u8 mbssid_index; + u8 copy_ie_offset; + u32 copy_ie_len = 0; + + mbssid_ie = rtw_get_ie(ref_bss->IEs + _BEACON_IE_OFFSET_ + , WLAN_EID_MULTIPLE_BSSID + , &mbssid_len + , (ref_bss->IELength- _BEACON_IE_OFFSET_)); + if (!mbssid_ie) + return; +#if 0 + else + RTW_PRINT_DUMP("mbssid_ie: ", (const u8 *)mbssid_ie, mbssid_len); +#endif + + mbssid_ie_ptr = mbssid_ie; + max_bssid_indicator = GET_MBSSID_MAX_BSSID_INDOCATOR(mbssid_ie_ptr); + /*RTW_INFO("%s, max_bssid_indicator=%d\n", __func__, max_bssid_indicator);*/ + mbssid_ie_ptr = mbssid_ie_ptr + MBSSID_MAX_BSSID_INDICATOR_OFFSET; + + for (i = 0; i + 1 < mbssid_len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(mbssid_ie_ptr + i); + + switch (pIE->ElementID) { + case MBSSID_NONTRANSMITTED_BSSID_PROFILE_ID: + sub_ies_len = pIE->Length; + pbss = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); + if (pbss) { + _rtw_memcpy(pbss, ref_bss, sizeof(WLAN_BSSID_EX)); + _rtw_memset(pbss->IEs, 0, MAX_IE_SZ); + copy_ie_len = _TIMESTAMP_ + _BEACON_ITERVAL_; + _rtw_memcpy(pbss->IEs, ref_bss->IEs, copy_ie_len); + } else { + return; + } + + for (j = 0; j + 1 < sub_ies_len;) { + sub_pie = (PNDIS_802_11_VARIABLE_IEs)(pIE->data + j); + switch (sub_pie->ElementID) { + case WLAN_EID_NON_TX_BSSID_CAP: + /*RTW_INFO("%s, sub_pie->Length=%d\n", __func__, sub_pie->Length);*/ + /*RTW_PRINT_DUMP("WLAN_EID_NON_TX_BSSID_CAP: ", (const u8 *)sub_pie->data, sub_pie->Length);*/ + copy_ie_offset = _TIMESTAMP_ + _BEACON_ITERVAL_; + _rtw_memcpy(pbss->IEs + copy_ie_offset, sub_pie->data, sub_pie->Length); + break; + case WLAN_EID_SSID: + /*RTW_PRINT_DUMP("WLAN_EID_SSID: ", (const u8 *)sub_pie->data, sub_pie->Length);*/ + /*RTW_INFO("%s, ref_bss->IELength=%d\n", __func__, ref_bss->IELength);*/ + /*RTW_PRINT_DUMP("A ref_bss->IEs: ", (const u8 *)ref_bss->IEs, ref_bss->IELength);*/ + copy_ie_offset = _TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_; + copy_ie_len = WLAN_IE_ID_LEN + WLAN_IE_LEN_LEN; + _rtw_memcpy(pbss->IEs + copy_ie_offset, sub_pie, copy_ie_len); + + copy_ie_offset = copy_ie_offset + WLAN_IE_ID_LEN + WLAN_IE_LEN_LEN; + _rtw_memcpy(pbss->IEs + copy_ie_offset, sub_pie->data, sub_pie->Length); + _rtw_memcpy(pbss->IEs + copy_ie_offset + sub_pie->Length + , ref_bss->IEs + copy_ie_offset + ref_bss->Ssid.SsidLength + , ref_bss->IELength - (copy_ie_offset + ref_bss->Ssid.SsidLength)); + + pbss->IELength = ref_bss->IELength + (sub_pie->Length - ref_bss->Ssid.SsidLength); + /*RTW_INFO("%s, ref_bss->Ssid.SsidLength=%d\n", __func__, ref_bss->Ssid.SsidLength);*/ + /*RTW_INFO("%s, sub_pie->Length=%d\n", __func__, sub_pie->Length);*/ + /*RTW_INFO("%s, pbss->IELength=%d\n", __func__, pbss->IELength);*/ + /*RTW_PRINT_DUMP("B pbss->IEs: ", (const u8 *)pbss->IEs, pbss->IELength);*/ + + _rtw_memset(pbss->Ssid.Ssid, 0, pbss->Ssid.SsidLength); + _rtw_memcpy(pbss->Ssid.Ssid, sub_pie->data, sub_pie->Length); + pbss->Ssid.SsidLength = sub_pie->Length; + break; + case WLAN_EID_MULTI_BSSID_IDX: + /*RTW_INFO("%s, sub_pie->Length=%d\n", __func__, sub_pie->Length);*/ + /*RTW_PRINT_DUMP("WLAN_EID_MULTI_BSSID_IDX: ", (const u8 *)sub_pie->data, sub_pie->Length);*/ + _rtw_memcpy(&mbssid_index, sub_pie->data, sub_pie->Length); + /*RTW_INFO("%s,mbssid_index=%d\n", __func__, mbssid_index);*/ + rtw_gen_new_bssid(ref_bss->MacAddress, max_bssid_indicator + , mbssid_index, pbss->MacAddress); + pbss->mbssid_index = mbssid_index; + break; + default: + break; + } + + j += (sub_pie->Length + WLAN_IE_ID_LEN + WLAN_IE_LEN_LEN); + /*RTW_INFO("%s, j=%d\n", __func__, j);*/ + } + pbss->is_mbssid = _TRUE; + add_network(padapter, pbss); + rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX)); + break; + case MBSSID_VENDOR_SPECIFIC_ID: + break; + default: + break; + } + + i += (pIE->Length + WLAN_IE_ID_LEN + WLAN_IE_LEN_LEN); + /*RTW_INFO("%s, i=%d\n", __func__, i);*/ + } +} +#endif + +void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) +{ + u32 len; + u8 val8; + WLAN_BSSID_EX *pnetwork; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + pnetwork = (WLAN_BSSID_EX *)pbuf; + + len = get_WLAN_BSSID_EX_sz(pnetwork); + if (len > (sizeof(WLAN_BSSID_EX))) { + return; + } + +#ifdef CONFIG_RTW_80211K + val8 = 0; + rtw_hal_get_hwreg(adapter, HW_VAR_FREECNT, &val8); + + /* use TSF if no free run counter */ + if (val8==0) + pnetwork->PhyInfo.free_cnt = (u32)rtw_hal_get_tsftr_by_port( + adapter, rtw_hal_get_port(adapter)); +#endif + + if (pnetwork->InfrastructureMode == Ndis802_11Infrastructure) { + if (MLME_IS_SCAN(adapter)) { + adapter->mlmeextpriv.sitesurvey_res.activate_ch_cnt + += rtw_process_beacon_hint(adapter, pnetwork); + } + } + + _rtw_spinlock_bh(&pmlmepriv->lock); + + /* update IBSS_network 's timestamp */ + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) { + if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) { + struct wlan_network *ibss_wlan = NULL; + + _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); + ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); + if (ibss_wlan) { + _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); + goto exit; + } + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); + } + } + + /* lock pmlmepriv->lock when you accessing network_q */ + if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _FALSE) { + if (pnetwork->Ssid.Ssid[0] == 0) + pnetwork->Ssid.SsidLength = 0; + add_network(adapter, pnetwork); +#ifdef CONFIG_STA_MULTIPLE_BSSID + add_mbssid_network(adapter, pnetwork); +#endif + } + +exit: + _rtw_spinunlock_bh(&pmlmepriv->lock); + + + return; +} + +void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) +{ + struct surveydone_event *parm = (struct surveydone_event *)pbuf; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + _rtw_spinlock_bh(&pmlmepriv->lock); + if (pmlmepriv->wps_probe_req_ie) { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + /* rtw_warn_on(1); */ + } + + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + _rtw_spinunlock_bh(&pmlmepriv->lock); + + _cancel_timer_ex(&pmlmepriv->scan_to_timer); + + _rtw_spinlock_bh(&pmlmepriv->lock); + #ifdef CONFIG_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&adapter->recvinfo); + #endif + if (pmlmepriv->to_join == _TRUE) { + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) { + set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); + + if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS) { + /*_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);*/ + set_assoc_timer(pmlmepriv, MAX_JOIN_TIMEOUT); + } + else { + WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); + u8 *pibss = adapter->registrypriv.dev_network.MacAddress; + + /* pmlmepriv->fw_state ^= WIFI_UNDER_SURVEY; */ /* because don't set assoc_timer */ + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(adapter); + rtw_generate_random_ibss(pibss); + + /*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/ + init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + + if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) + RTW_ERR("rtw_create_ibss_cmd FAIL\n"); + + pmlmepriv->to_join = _FALSE; + } + } + } else { + int s_ret; + set_fwstate(pmlmepriv, WIFI_UNDER_LINKING); + pmlmepriv->to_join = _FALSE; + s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); + if (_SUCCESS == s_ret) { + /*_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);*/ + set_assoc_timer(pmlmepriv, MAX_JOIN_TIMEOUT); + } else if (s_ret == 2) { /* there is no need to wait for join */ + _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); + rtw_indicate_connect(adapter); + } else { + RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); + + if (rtw_to_roam(adapter) != 0) { + struct sitesurvey_parm scan_parm; + u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE); + + rtw_init_sitesurvey_parm(adapter, &scan_parm); + _rtw_memcpy(&scan_parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + scan_parm.ssid_num = 1; + + if (rtw_dec_to_roam(adapter) == 0 + || (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC) + || _SUCCESS != rtw_sitesurvey_cmd(adapter, &scan_parm) + ) { + rtw_set_to_roam(adapter, 0); + if (MLME_IS_ASOC(adapter) == _TRUE) + rtw_free_assoc_resources(adapter, _TRUE); + rtw_indicate_disconnect(adapter, 0, _FALSE); + } else + pmlmepriv->to_join = _TRUE; + } else + rtw_indicate_disconnect(adapter, 0, _FALSE); + _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING); + } + } + } else { + if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE) + #if (defined(CONFIG_RTW_WNM) && defined(CONFIG_RTW_80211R)) + || rtw_wnm_btm_roam_triggered(adapter) + #endif + ) { + if (MLME_IS_STA(adapter) + && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { + if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { +#ifdef CONFIG_RTW_80211R + rtw_ft_start_roam(adapter, + (u8 *)pmlmepriv->roam_network->network.MacAddress); +#else + receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +#endif + } + } + } + } + + RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); + + _rtw_spinunlock_bh(&pmlmepriv->lock); + +#ifdef CONFIG_P2P_PS + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); +#endif /* CONFIG_P2P_PS */ + + rtw_mi_os_xmit_schedule(adapter); +#ifdef CONFIG_DRVEXT_MODULE_WSC + drvext_surveydone_callback(&adapter->drvextpriv); +#endif + +#ifdef DBG_CONFIG_ERROR_DETECT + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + if (pmlmeext->sitesurvey_res.bss_cnt == 0) { + /* rtw_hal_sreset_reset(adapter); */ + } + } +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_surveydone_event_callback(adapter); +#endif /* CONFIG_IOCTL_CFG80211 */ + + rtw_indicate_scan_done(adapter, pmlmeext->scan_abort); + +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE); +#endif + + if (parm->activate_ch_cnt) { + #ifdef CONFIG_IOCTL_CFG80211 + struct get_chplan_resp *chplan; + + if (rtw_get_chplan_cmd(adapter, RTW_CMDF_DIRECTLY, &chplan) != _SUCCESS + || rtw_regd_change_complete_async(adapter_to_wiphy(adapter), chplan) != _SUCCESS) + rtw_warn_on(1); + #endif + + op_class_pref_apply_regulatory(adapter, REG_BEACON_HINT); + rtw_nlrtw_reg_beacon_hint_event(adapter); + } + +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + if (rtw_mesh_offch_candidate_accepted(adapter)) { + u8 ch; + + ch = rtw_mesh_select_operating_ch(adapter); + if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) { + u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter); + + if (ifbmp) { + /* switch to selected channel */ + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE); + issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0); + } else + rtw_warn_on(1); + } + } + #endif +#endif /* CONFIG_RTW_MESH */ + +#ifdef CONFIG_RTW_ACS + if (parm->acs) { + u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter); + + if (ifbmp) + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, REQ_CH_INT_INFO, REQ_BW_ORI, REQ_OFFSET_NONE); + } +#endif +} + +u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval) +{ + u8 ss_condition = SS_ALLOW; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct registry_priv *registry_par = &adapter->registrypriv; + + +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(adapter)) { + RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_MP_MODE; + goto _exit; + } +#endif + +#ifdef DBG_LA_MODE + if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) { + RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_LA_MODE; + goto _exit; + } +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(adapter)->block_scan == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BLOCK_SCAN; + goto _exit; + } +#endif + + if (adapter_to_dvobj(adapter)->scan_deny == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") tpt mode, scan deny!\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BLOCK_SCAN; + goto _exit; + } + + if (rtw_is_scan_deny(adapter)) { + RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BY_DRV; + goto _exit; + } + + #if 0 /*GEORGIA_TODO_FIXIT*/ + if (adapter_to_rfctl(adapter)->adaptivity_en + && rtw_hal_get_phy_edcca_flag(adapter) + && rtw_is_2g_ch(GET_PHL_COM(adapter_to_dvobj(adapter))->current_channel)) { + RTW_WARN(FUNC_ADPT_FMT": Adaptivity block scan! (ch=%u)\n", + FUNC_ADPT_ARG(adapter), + GET_PHL_COM(adapter_to_dvobj(adapter))->current_channel); + ss_condition = SS_DENY_ADAPTIVITY; + goto _exit; + } + #endif + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){ + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_SELF_AP_UNDER_WPS; + goto _exit; + } else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_AP_UNDER_LINKING; + goto _exit; + } else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY; + goto _exit; + } + } else { + if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_STA_UNDER_LINKING; + goto _exit; + } else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY; + goto _exit; + } + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS; + goto _exit; + + } else if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUDDY_UNDER_SURVEY; + goto _exit; + } +#endif /* CONFIG_CONCURRENT_MODE */ + +#ifdef RTW_BUSY_DENY_SCAN + /* + * busy traffic check + * Rules: + * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow + * scan, otherwise goto rule 2. + * 2. Deny scan if any interface is busy, otherwise allow scan. + */ + if (pmlmepriv->lastscantime + && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) > + registry_par->scan_interval_thr) + && rtw_mi_busy_traffic_check(adapter)) { + RTW_WARN("%s ("ADPT_FMT") : scan abort!! BusyTraffic\n", + caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUSY_TRAFFIC; + goto _exit; + } +#endif /* RTW_BUSY_DENY_SCAN */ + +_exit: + return ss_condition; +} + + +/*rtw_mlme_ext.c*/ +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + _rtw_mutex_lock_interruptible(&rfctl->offch_mutex); + + switch (scan_state) { + case SCAN_DISABLE: + case SCAN_BACK_OP: + rfctl->offch_state = OFFCHS_NONE; + break; + case SCAN_START: + case SCAN_LEAVING_OP: + rfctl->offch_state = OFFCHS_LEAVING_OP; + break; + case SCAN_ENTER: + case SCAN_LEAVE_OP: + rfctl->offch_state = OFFCHS_LEAVE_OP; + break; + case SCAN_COMPLETE: + case SCAN_BACKING_OP: + rfctl->offch_state = OFFCHS_BACKING_OP; + break; + default: + break; + } + + _rtw_mutex_unlock(&rfctl->offch_mutex); +} +static u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num) +{ + /* interval larger than this is treated as backgroud scan */ +#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS +#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000 +#endif + +#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST +#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1 +#endif +#ifndef RTW_SCAN_SPARSE_CH_NUM_BG +#define RTW_SCAN_SPARSE_CH_NUM_BG 4 +#endif + +#define SCAN_SPARSE_CH_NUM_INVALID 255 + + static u8 token = 255; + u32 interval; + bool busy_traffic = _FALSE; + bool miracast_enabled = _FALSE; + bool bg_scan = _FALSE; + u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID; + u8 scan_division_num; + u8 ret_num = ch_num; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + if (mlmeext->last_scan_time == 0) + mlmeext->last_scan_time = rtw_get_current_time(); + + interval = rtw_get_passing_time_ms(mlmeext->last_scan_time); + + + if (rtw_mi_busy_traffic_check(adapter)) + busy_traffic = _TRUE; + + if (rtw_mi_check_miracast_enabled(adapter)) + miracast_enabled = _TRUE; + + if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS) + bg_scan = _TRUE; + + /* max_allow_ch by conditions*/ + +#if RTW_SCAN_SPARSE_MIRACAST + if (miracast_enabled == _TRUE && busy_traffic == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST); +#endif + +#if RTW_SCAN_SPARSE_BG + if (bg_scan == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG); +#endif + + + if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) { + int i; + int k = 0; + + scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0); + token = (token + 1) % scan_division_num; + + if (0) + RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token); + + for (i = 0; i < ch_num; i++) { + if (ch[i].hw_value && (i % scan_division_num) == token + ) { + if (i != k) + _rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel)); + k++; + } + } + + _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + + ret_num = k; + mlmeext->last_scan_time = rtw_get_current_time(); + } + + return ret_num; +} + +static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, + u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num, bool no_sparse) +{ + int i, j; + int set_idx; + u8 chan; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(padapter)); + + /* clear first */ + _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num); + + /* acquire channels from in */ + j = 0; + for (i = 0; i < in_num; i++) { + + if (0) + RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i])); + + if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED)) + continue; + if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE) + continue; + + set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value); + if (set_idx >= 0) { + if (j >= out_num) { + RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); + + if (rfctl->channel_set[set_idx].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS)) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + if (j >= out_num) + break; + } + + /* if out is empty, use channel_set as default */ + if (j == 0) { + for (i = 0; i < rfctl->max_chan_nums; i++) { + chan = rfctl->channel_set[i].ChannelNum; + if (rtw_mlme_band_check(padapter, chan) == _TRUE) { + if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE) + continue; + + if (0) + RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan); + + if (j >= out_num) { + RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + out[j].hw_value = chan; + + if (rfctl->channel_set[i].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS)) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + } + } + + if (!no_sparse + && !regsty->wifi_spec + && j > 6 /* assume ch_num > 6 is normal scan */ + ) { + /* scan_sparse */ + j = rtw_scan_sparse(padapter, out, j); + } + + return j; +} +#ifdef CONFIG_SCAN_BACKOP +u8 rtw_scan_backop_decision(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mi_state mstate; + u8 backop_flags = 0; + + rtw_mi_status(adapter, &mstate); + + if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN)) + || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext); + +#ifdef CONFIG_AP_MODE + if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN)) + || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext); +#endif + +#ifdef CONFIG_RTW_MESH + if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN)) + || (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext); +#endif + + return backop_flags; +} +#endif + +#if 0 /*#ifndef CONFIG_PHL_ARCH*/ +void survey_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct cmd_obj *cmd; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + rtw_warn_on(1); + goto exit; + } + cmd->padapter = padapter; + + psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_warn_on(1); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, CMD_SITE_SURVEY); + rtw_enqueue_cmd(pcmdpriv, cmd); + } + +exit: + return; +} + +static const char *const _scan_state_str[] = { + "SCAN_DISABLE", + "SCAN_START", + "SCAN_PS_ANNC_WAIT", + "SCAN_ENTER", + "SCAN_PROCESS", + "SCAN_BACKING_OP", + "SCAN_BACK_OP", + "SCAN_LEAVING_OP", + "SCAN_LEAVE_OP", + "SCAN_SW_ANTDIV_BL", + "SCAN_TO_P2P_LISTEN", + "SCAN_P2P_LISTEN", + "SCAN_COMPLETE", + "SCAN_STATE_MAX", +}; + +void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + if (pcmd->res == H2C_DROPPED) { + /* TODO: cancel timer and do timeout handler directly... */ + /* need to make timeout handlerOS independent */ + mlme_set_scan_to_timer(pmlmepriv, 1); + } else if (pcmd->res != H2C_SUCCESS) { + mlme_set_scan_to_timer(pmlmepriv, 1); + } + + /* free cmd */ + rtw_free_cmd_obj(pcmd); + +} + +const char *scan_state_str(u8 state) +{ + state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state; + return _scan_state_str[state]; +} + +static bool scan_abort_hdl(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#endif + bool ret = _FALSE; + + if (pmlmeext->scan_abort == _TRUE) { +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); + ss->channel_idx = 3; + RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__ + , ss->channel_idx + , pwdinfo->find_phase_state_exchange_cnt + ); + } else +#endif + { + ss->channel_idx = ss->ch_num; + RTW_INFO("%s idx:%d\n", __FUNCTION__ + , ss->channel_idx + ); + } + pmlmeext->scan_abort = _FALSE; + ret = _TRUE; + } + + return ret; +} + +static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) +{ + struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); + int i; + + ss->bss_cnt = 0; + ss->activate_ch_cnt = 0; + ss->channel_idx = 0; + ss->force_ssid_scan = 0; + ss->igi_scan = 0; + ss->igi_before_scan = 0; +#ifdef CONFIG_SCAN_BACKOP + ss->scan_cnt = 0; +#endif +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + ss->is_sw_antdiv_bl_scan = 0; +#endif + ss->ssid_num = 0; + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (parm->ssid[i].SsidLength) { + _rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); + ss->ssid[i].SsidLength = parm->ssid[i].SsidLength; + ss->ssid_num++; + } else + ss->ssid[i].SsidLength = 0; + } + + ss->ch_num = rtw_scan_ch_decision(adapter + , ss->ch, RTW_CHANNEL_SCAN_AMOUNT + , parm->ch, parm->ch_num + , parm->acs + ); + + for (i = 0; i < MAX_CHANNEL_NUM; i++) + chset[i].hidden_bss_cnt = 0; + + ss->bw = parm->bw; + ss->igi = parm->igi; + ss->token = parm->token; + ss->duration = parm->duration; + ss->scan_mode = parm->scan_mode; + ss->token = parm->token; + ss->acs = parm->acs; +} + +static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, + enum rtw_phl_scan_type *type) +{ + u8 next_state; + u8 scan_ch = 0; + enum rtw_phl_scan_type stype = RTW_PHL_SCAN_PASSIVE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + int ch_set_idx; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif +#ifdef CONFIG_SCAN_BACKOP + u8 backop_flags = 0; +#endif + + /* handle scan abort request */ + scan_abort_hdl(padapter); + +#ifdef CONFIG_P2P + if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) { + if (pwdinfo->rx_invitereq_info.scan_op_ch_only) + scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx]; + else + scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx]; + stype = RTW_PHL_SCAN_ACTIVE; + } else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) { + /* + * Commented by Albert 2011/06/03 + * The driver is in the find phase, it should go through the social channel. + */ + scan_ch = pwdinfo->social_chan[ss->channel_idx]; + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch); + if (ch_set_idx >= 0) + stype = rfctl->channel_set[ch_set_idx].flags & RTW_CHF_NO_IR ? RTW_PHL_SCAN_PASSIVE : RTW_PHL_SCAN_ACTIVE; + else + stype = RTW_PHL_SCAN_ACTIVE; + } else +#endif /* CONFIG_P2P */ + { + struct rtw_ieee80211_channel *ch; + + #ifdef CONFIG_SCAN_BACKOP + backop_flags = rtw_scan_backop_decision(padapter); + #endif + + #ifdef CONFIG_SCAN_BACKOP + if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max)) + #endif + { + #ifdef CONFIG_RTW_WIFI_HAL + if (adapter_to_dvobj(padapter)->nodfs) { + while (ss->channel_idx < ss->ch_num && rtw_chset_is_dfs_ch(rfctl->channel_set, ss->ch[ss->channel_idx].hw_value)) + ss->channel_idx++; + } else + #endif + if (ss->channel_idx != 0 && ss->force_ssid_scan == 0 + && pmlmeext->sitesurvey_res.ssid_num + && (ss->ch[ss->channel_idx - 1].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) + ) { + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value); + if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt + && (!IS_DFS_SLAVE_WITH_RD(rfctl) + || rtw_rfctl_dfs_domain_unknown(rfctl) + || !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])) + ) { + ss->channel_idx--; + ss->force_ssid_scan = 1; + } + } else + ss->force_ssid_scan = 0; + } + + if (ss->channel_idx < ss->ch_num) { + ch = &ss->ch[ss->channel_idx]; + scan_ch = ch->hw_value; + + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter)) + stype = RTW_PHL_SCAN_PASSIVE; + else + #endif /*CONFIG_RTW_ACS*/ + stype = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? RTW_PHL_SCAN_PASSIVE : RTW_PHL_SCAN_ACTIVE; + } + } + + if (scan_ch != 0) { + next_state = SCAN_PROCESS; + + #ifdef CONFIG_SCAN_BACKOP + if (backop_flags) { + if (ss->scan_cnt < ss->scan_cnt_max) + ss->scan_cnt++; + else { + mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags); + next_state = SCAN_BACKING_OP; + } + } + #endif + + } else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) { + /* go p2p listen */ + next_state = SCAN_TO_P2P_LISTEN; + +#ifdef CONFIG_ANTENNA_DIVERSITY + } else if (rtw_hal_antdiv_before_linked(padapter)) { + /* go sw antdiv before link */ + next_state = SCAN_SW_ANTDIV_BL; +#endif + } else { + next_state = SCAN_COMPLETE; + +#if defined(DBG_SCAN_SW_ANTDIV_BL) + { + /* for SCAN_SW_ANTDIV_BL state testing */ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int i; + bool is_linked = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (rtw_linked_check(dvobj->padapters[i])) + is_linked = _TRUE; + } + + if (!is_linked) { + static bool fake_sw_antdiv_bl_state = 0; + + if (fake_sw_antdiv_bl_state == 0) { + next_state = SCAN_SW_ANTDIV_BL; + fake_sw_antdiv_bl_state = 1; + } else + fake_sw_antdiv_bl_state = 0; + } + } +#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */ + } + +#ifdef CONFIG_SCAN_BACKOP + if (next_state != SCAN_PROCESS) + ss->scan_cnt = 0; +#endif + + +#ifdef DBG_FIXED_CHAN + if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS) + scan_ch = pmlmeext->fixed_chan; +#endif + + if (ch) + *ch = scan_ch; + if (type) + *type = stype; + + return next_state; +} + +void site_survey(_adapter *padapter, u8 survey_channel, + enum rtw_phl_scan_type ScanType) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + u8 ssid_scan = 0; + +#ifdef CONFIG_P2P +#ifndef CONFIG_IOCTL_CFG80211 + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif +#endif + + if (survey_channel != 0) { + set_channel_bwmode(padapter, + survey_channel, + CHAN_OFFSET_NO_EXT, + CHANNEL_WIDTH_20, + _FALSE); + + if (ScanType == RTW_PHL_SCAN_PASSIVE && ss->force_ssid_scan) + ssid_scan = 1; + else if (ScanType == RTW_PHL_SCAN_ACTIVE) { +#ifdef CONFIG_P2P + #ifdef CONFIG_IOCTL_CFG80211 + if (rtw_cfg80211_is_p2p_scan(padapter)) + #else + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) + #endif + { + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + } else +#endif /* CONFIG_P2P */ + { + if (pmlmeext->sitesurvey_res.scan_mode == RTW_PHL_SCAN_ACTIVE) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, NULL, NULL); + else + issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); + issue_probereq(padapter, NULL, NULL); + } + + ssid_scan = 1; + } + } + + if (ssid_scan) { + int i; + + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + else + issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + } + } + } + } else { + /* channel number is 0 or this channel is not valid. */ + rtw_warn_on(1); + } + + return; +} + +void survey_done_set_ch_bw(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 cur_channel = 0; + u8 cur_bwmode; + u8 cur_ch_offset; + + if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) { + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } else { +#ifdef CONFIG_P2P + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + +#ifdef CONFIG_IOCTL_CFG80211 + if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled) + continue; +#endif + + if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) { + cur_channel = iface->wdinfo.listen_channel; + cur_bwmode = CHANNEL_WIDTH_20; + cur_ch_offset = CHAN_OFFSET_NO_EXT; + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset); + break; + } + } +#endif /* CONFIG_P2P */ + + if (cur_channel == 0) { + cur_channel = pmlmeext->chandef.chan; + cur_bwmode = pmlmeext->chandef.bw; + cur_ch_offset = pmlmeext->chandef.offset; + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } + } + set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode, _FALSE); +} + +void sitesurvey_set_igi(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + u8 igi; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#endif + + switch (mlmeext_scan_state(mlmeext)) { + case SCAN_ENTER: + #ifdef CONFIG_P2P + #ifdef CONFIG_IOCTL_CFG80211 + if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter)) + igi = 0x30; + else + #endif /* CONFIG_IOCTL_CFG80211 */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + igi = 0x28; + else + #endif /* CONFIG_P2P */ + + if (ss->igi) + igi = ss->igi; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter)) + igi = rtw_acs_get_adv_igi(adapter); + else + #endif /*CONFIG_RTW_ACS*/ + igi = 0x1e; + + /* record IGI status */ + ss->igi_scan = igi; + rtw_hal_get_phydm_var(adapter, HAL_PHYDM_IGI, &ss->igi_before_scan, NULL); + + /* disable DIG and set IGI for scan */ + rtw_hal_set_phydm_var(adapter, HAL_PHYDM_IGI, &igi, _FALSE); + break; + case SCAN_COMPLETE: + case SCAN_TO_P2P_LISTEN: + /* enable DIG and restore IGI */ + igi = 0xff; + rtw_hal_set_phydm_var(adapter, HAL_PHYDM_IGI, &igi, _FALSE); + break; +#ifdef CONFIG_SCAN_BACKOP + case SCAN_BACKING_OP: + /* write IGI for op channel when DIG is not enabled */ + rtw_hal_set_phydm_var(adapter, HAL_PHYDM_IGI_W, &ss->igi_before_scan, _FALSE); + break; + case SCAN_LEAVE_OP: + /* write IGI for scan when DIG is not enabled */ + rtw_hal_set_phydm_var(adapter, HAL_PHYDM_IGI_W, &ss->igi_scan, _FALSE); + break; +#endif /* CONFIG_SCAN_BACKOP */ + default: + rtw_warn_on(1); + break; + } +} +void sitesurvey_set_msr(_adapter *adapter, bool enter) +{ + u8 network_type; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (enter) { + /* set MSR to no link state */ + network_type = _HW_STATE_NOLINK_; + } else { + network_type = pmlmeinfo->state & 0x3; + } +} + +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; +#ifdef DBG_CHECK_FW_PS_STATE + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; +#endif + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif + u8 val8; + +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif + +#ifdef DBG_CHECK_FW_PS_STATE + if (rtw_fw_ps_state(padapter) == _FAIL) { + RTW_INFO("scan without leave 32k\n"); + pdbgpriv->dbg_scan_pwr_state_cnt++; + } +#endif /* DBG_CHECK_FW_PS_STATE */ + + /* increase channel idx */ + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) + ss->channel_idx++; + + /* update scan state to next state (assigned by previous cmd hdl) */ + if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext)) + mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext)); + +operation_by_state: + switch (mlmeext_scan_state(pmlmeext)) { + + case SCAN_DISABLE: + /* + * SW parameter initialization + */ + + sitesurvey_res_reset(padapter, pparm); + mlmeext_set_scan_state(pmlmeext, SCAN_START); + goto operation_by_state; + + case SCAN_START: +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (MLME_IS_STA(padapter)) + && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) { + u16 seq_num; + + rtw_hal_pno_random_gen_mac_addr(padapter); + rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr); + get_random_bytes(&seq_num, 2); + pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF; + RTW_INFO("%s pno_scan_seq_num %d\n", __func__, + pwdev_priv->pno_scan_seq_num); + } +#endif + + /* + * prepare to leave operating channel + */ + + /* apply rx ampdu setting */ + if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID + || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + rtw_rx_ampdu_apply(padapter); + + /* clear HW TX queue before scan */ + rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + + rtw_hal_macid_sleep_all_used(padapter); + + /* power save state announcement */ + if (rtw_ps_annc(padapter, 1)) { + mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); + mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); + set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ + } else { + mlmeext_set_scan_state(pmlmeext, SCAN_ENTER); + goto operation_by_state; + } + + break; + + case SCAN_ENTER: + /* + * HW register and DM setting for enter scan + */ + + rtw_phydm_ability_backup(padapter); + + sitesurvey_set_igi(padapter); + + /* config dynamic functions for off channel */ + rtw_phydm_func_for_offchannel(padapter); + /* set network type to no link state */ + sitesurvey_set_msr(padapter, _TRUE); + + val8 = 1; /* under site survey */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + goto operation_by_state; + + case SCAN_PROCESS: { + u8 scan_ch; + enum rtw_phl_scan_type stype; + u8 next_state; + u32 scan_ms; + +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_get_rst(padapter); +#endif + + next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &stype); + + if (next_state != SCAN_PROCESS) { + mlmeext_set_scan_state(pmlmeext, next_state); + goto operation_by_state; + } + + /* still SCAN_PROCESS state */ + #ifdef DBG_SITESURVEY + #ifdef CONFIG_P2P + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + , stype ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' + , ss->ssid[0].SsidLength ? 'S' : ' ' + , ss->force_ssid_scan ? 'F' : ' ' + ); + #else + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , ss->channel_idx + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + , stype ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' + , ss->ssid[0].SsidLength ? 'S' : ' ' + , ss->force_ssid_scan ? 'F' : ' ' + ); + #endif /* CONFIG_P2P */ + #endif /*DBG_SITESURVEY*/ +#ifdef DBG_FIXED_CHAN + if (pmlmeext->fixed_chan != 0xff) + RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); +#endif + + site_survey(padapter, scan_ch, stype); + +#if defined(CONFIG_ATMEL_RC_PATCH) + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + scan_ms = 20; + else + scan_ms = 40; +#else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; +#endif + +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + if (ss->is_sw_antdiv_bl_scan) + scan_ms = scan_ms / 2; +#endif + +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) { + if (pparm->token) + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH); + else + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS); + } +#endif + + set_survey_timer(pmlmeext, scan_ms); + break; + } + +#ifdef CONFIG_SCAN_BACKOP + case SCAN_BACKING_OP: { + u8 back_ch, back_bw, back_ch_offset; + u8 need_ch_setting_union = _TRUE; + + if (need_ch_setting_union) { + if (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0) { + rtw_warn_on(1); + back_ch = pmlmeext->chandef.chan; + back_bw = pmlmeext->chandef.bw; + back_ch_offset = pmlmeext->chandef.offset; + } + } + + #ifdef DBG_SITESURVEY + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , back_ch, back_bw, back_ch_offset + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + ); + #endif /*DBG_SITESURVEY*/ + set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw, _FALSE); + + sitesurvey_set_msr(padapter, _FALSE); + + val8 = 0; /* survey done */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { + sitesurvey_set_igi(padapter); + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); + } + + mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP); + ss->backop_time = rtw_get_current_time(); + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME)) + rtw_mi_os_xmit_schedule(padapter); + + goto operation_by_state; + } + + case SCAN_BACK_OP: + if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms + || pmlmeext->scan_abort + ) { + mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP); + goto operation_by_state; + } + set_survey_timer(pmlmeext, 50); + break; + + case SCAN_LEAVING_OP: + /* + * prepare to leave operating channel + */ + + /* clear HW TX queue before scan */ + rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + + rtw_hal_macid_sleep_all_used(padapter); + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC) + && rtw_ps_annc(padapter, 1) + ) { + mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); + mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP); + set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ + } else { + mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP); + goto operation_by_state; + } + + break; + + case SCAN_LEAVE_OP: + /* + * HW register and DM setting for enter scan + */ + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) + sitesurvey_set_igi(padapter); + + sitesurvey_set_msr(padapter, _TRUE); + + val8 = 1; /* under site survey */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + goto operation_by_state; + +#endif /* CONFIG_SCAN_BACKOP */ + +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + case SCAN_SW_ANTDIV_BL: + /* + * 20100721 + * For SW antenna diversity before link, it needs to switch to another antenna and scan again. + * It compares the scan result and select better one to do connection. + */ + ss->bss_cnt = 0; + ss->channel_idx = 0; + ss->is_sw_antdiv_bl_scan = 1; + + mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS); + set_survey_timer(pmlmeext, ss->scan_ch_ms); + break; +#endif + +#ifdef CONFIG_P2P + case SCAN_TO_P2P_LISTEN: + /* + * Set the P2P State to the listen state of find phase + * and set the current channel to the listen channel + */ + set_channel_bwmode(padapter, + pwdinfo->listen_channel, + CHAN_OFFSET_NO_EXT, + CHANNEL_WIDTH_20, + _FALSE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN); + _set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100)); + break; + + case SCAN_P2P_LISTEN: + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + ss->channel_idx = 0; + goto operation_by_state; +#endif /* CONFIG_P2P */ + + case SCAN_COMPLETE: +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter)); +#endif +#ifdef CONFIG_P2P + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) + ) { +#ifdef CONFIG_CONCURRENT_MODE + if (pwdinfo->driver_interface == DRIVER_WEXT) { + if (rtw_mi_check_status(padapter, MI_LINKED)) + _set_timer(&pwdinfo->ap_p2p_switch_timer, 500); + } +#endif + + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + } + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); +#endif /* CONFIG_P2P */ + + /* switch channel */ + survey_done_set_ch_bw(padapter); + + sitesurvey_set_msr(padapter, _FALSE); + + val8 = 0; /* survey done */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); + + /* apply rx ampdu setting */ + rtw_rx_ampdu_apply(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + + report_surveydone_event(padapter, ss->acs); +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_select_best_chan(padapter); +#endif + + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + +#ifdef CONFIG_RTW_80211K + if (ss->token) + rm_post_event(padapter, ss->token, RM_EV_survey_done); +#endif /* CONFIG_RTW_80211K */ + + break; + } + + return H2C_SUCCESS; +} +#else +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + RTW_ERR("%s executed??\n", __func__); + rtw_warn_on(1); + return 0; +} +void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + RTW_ERR("%s executed??\n", __func__); + rtw_warn_on(1); +} + +/* remain on channel priv */ +#define ROCH_CH_READY 0x1 + +struct scan_priv { + _adapter *padapter; + + /* for remain on channel callback */ + struct wireless_dev *wdev; + struct ieee80211_channel channel; + u8 channel_type; + unsigned int duration; + u64 cookie; + + u8 restore_ch; + + u8 roch_step; +#ifdef CONFIG_RTW_80211K + u32 rrm_token; /* 80211k use it to identify caller */ +#endif +}; + +#ifdef CONFIG_CMD_SCAN +static struct rtw_phl_scan_param *_alloc_phl_param(_adapter *adapter, u8 scan_ch_num) +{ + struct rtw_phl_scan_param *phl_param = NULL; + struct scan_priv *scan_priv = NULL; + + if (scan_ch_num == 0) { + RTW_ERR("%s scan_ch_num = 0\n", __func__); + goto _err_exit; + } + /*create mem of PHL Scan parameter*/ + phl_param = rtw_zmalloc(sizeof(*phl_param)); + if (phl_param == NULL) { + RTW_ERR("%s alloc phl_param fail\n", __func__); + goto _err_exit; + } + + scan_priv = rtw_zmalloc(sizeof(*scan_priv)); + if (scan_priv == NULL) { + RTW_ERR("%s alloc scan_priv fail\n", __func__); + goto _err_scanpriv; + } + scan_priv->padapter = adapter; + phl_param->priv = scan_priv; + phl_param->wifi_role = adapter->phl_role; + phl_param->back_op_mode = SCAN_BKOP_NONE; + + phl_param->ch_sz = sizeof(struct phl_scan_channel) * (scan_ch_num + 1); + phl_param->ch = rtw_zmalloc(phl_param->ch_sz); + if (phl_param->ch == NULL) { + RTW_ERR("%s: alloc phl scan ch fail\n", __func__); + goto _err_param_ch; + } + + return phl_param; + +_err_param_ch: + if (scan_priv) + rtw_mfree(scan_priv, sizeof(*scan_priv)); +_err_scanpriv: + if (phl_param) + rtw_mfree(phl_param, sizeof(*phl_param)); +_err_exit: + rtw_warn_on(1); + return phl_param; +} + +static u8 _free_phl_param(_adapter *adapter, struct rtw_phl_scan_param *phl_param) +{ + u8 res = _FAIL; + + if (!phl_param) + return res; + + if (phl_param->ch) + rtw_mfree(phl_param->ch, phl_param->ch_sz); + if (phl_param->priv) + rtw_mfree(phl_param->priv, sizeof(struct scan_priv)); + rtw_mfree(phl_param, sizeof(struct rtw_phl_scan_param)); + + res = _SUCCESS; + return res; +} +#endif /*CONFIG_CMD_SCAN*/ +static int scan_issue_pbreq_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + NDIS_802_11_SSID ssid; + int i; + + + /* active scan behavior */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, NULL, NULL); + else + issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); + + issue_probereq(padapter, NULL, NULL); + + for (i = 0; i < param->ssid_num; i++) { + if (param->ssid[i].ssid_len == 0) + continue; + + ssid.SsidLength = param->ssid[i].ssid_len; + _rtw_memcpy(ssid.Ssid, ¶m->ssid[i].ssid, ssid.SsidLength); + /* IOT issue, + * Send one probe req without WPS IE, + * when not wifi_spec + */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, &ssid, NULL); + else + issue_probereq_ex(padapter, &ssid, NULL, 0, 0, 0, 0); + + issue_probereq(padapter, &ssid, NULL); + } + return 0; +} + +static int scan_complete_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + bool acs = _FALSE; + int ret = _FAIL; + + if (!rtw_is_adapter_up(padapter)) + goto _exit; + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + + report_surveydone_event(padapter, acs, RTW_CMDF_DIRECTLY); + ret = _SUCCESS; + +_exit: + RTW_INFO(FUNC_ADPT_FMT" takes %d ms to scan %d/%d channels\n", + FUNC_ADPT_ARG(padapter), param->total_scan_time, + #ifdef CONFIG_CMD_SCAN + param->ch_idx, + #else + param->ch_idx + 1, + #endif + param->ch_num); + _rtw_scan_abort_check(padapter, __func__); + +#ifdef CONFIG_CMD_SCAN + _free_phl_param(padapter, param); + pmlmeext->sitesurvey_res.scan_param = NULL; +#else + rtw_mfree(scan_priv, sizeof(*scan_priv)); +#endif + + return ret; +} + +static int scan_start_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + pmlmeext->sitesurvey_res.bss_cnt = 0; + pmlmeext->sitesurvey_res.activate_ch_cnt = 0; + //TODO remove + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + #ifdef CONFIG_CMD_SCAN + pmlmeext->sitesurvey_res.scan_param = param; + #endif + return 0; +} + +#ifdef CONFIG_P2P +static int scan_issue_p2p_pbreq_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + return 0; +} +#endif + +static int scan_ch_ready_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + + RTW_INFO("%s ch:%d\n", __func__, param->scan_ch->channel); + return 0; +} + +static inline void _ps_announce(_adapter *adapter, bool ps) +{ + RTW_INFO(FUNC_ADPT_FMT" issue_null(%d)\n", FUNC_ADPT_ARG(adapter), ps); + if (MLME_IS_STA(adapter)) { + if (is_client_associated_to_ap(adapter) == _TRUE) { + /*issue_nulldata(adapter, NULL, ps, 3, 500);*/ + issue_nulldata(adapter, NULL, ps, 1, 0); + } + } + #ifdef CONFIG_RTW_MESH + else if (MLME_IS_MESH(adapter)) { + rtw_mesh_ps_annc(adapter, ps); + } + #endif +} + +u8 scan_issu_null_data_cb(void *priv, u8 ridx, bool ps) +{ + #ifdef CONFIG_CMD_SCAN + struct dvobj_priv *obj = (struct dvobj_priv *)priv; + #else + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct dvobj_priv *obj = adapter_to_dvobj(padapter); + #endif + _adapter *iface = NULL; + + if (ridx >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s ridx:%d invalid\n", __func__, ridx); + rtw_warn_on(1); + goto _error; + } + + iface = obj->padapters[ridx]; + if (!rtw_is_adapter_up(iface)) + goto _error; + + _ps_announce(iface, ps); + + return _SUCCESS; +_error: + return _FAIL; +} + +static struct rtw_phl_scan_ops scan_ops_cb = { + .scan_start = scan_start_cb, + .scan_ch_ready = scan_ch_ready_cb, + .scan_complete = scan_complete_cb, + .scan_issue_pbreq = scan_issue_pbreq_cb, + .scan_issue_null_data = scan_issu_null_data_cb +}; + +#ifdef CONFIG_P2P +static struct rtw_phl_scan_ops scan_ops_p2p_cb = { + .scan_start = scan_start_cb, + .scan_ch_ready = scan_ch_ready_cb, + .scan_complete = scan_complete_cb, + .scan_issue_pbreq = scan_issue_p2p_pbreq_cb, + .scan_issue_null_data = scan_issu_null_data_cb +}; +#endif + +#ifdef CONFIG_RTW_80211K +static int scan_complete_rrm_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + int ret = _FAIL; + + if (!rtw_is_adapter_up(padapter)) + goto _exit; + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + _rtw_spinlock_bh(&pmlmepriv->lock); + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + _rtw_spinunlock_bh(&pmlmepriv->lock); + + /* inform RRM scan complete */ + rm_post_event(padapter, scan_priv->rrm_token, RM_EV_survey_done); + ret = _SUCCESS; + +_exit: + RTW_INFO(FUNC_ADPT_FMT" takes %d ms to scan %d/%d channels\n", + FUNC_ADPT_ARG(padapter), param->total_scan_time, + param->ch_idx + 1, param->ch_num); + _rtw_scan_abort_check(padapter, __func__); + +#ifdef CONFIG_CMD_SCAN + _free_phl_param(padapter, param); + pmlmeext->sitesurvey_res.scan_param = NULL; +#else + rtw_mfree(scan_priv, sizeof(*scan_priv)); +#endif + return ret; +} + +static struct rtw_phl_scan_ops scan_ops_rrm_cb = { + .scan_start = scan_start_cb, + .scan_ch_ready = scan_ch_ready_cb, + .scan_complete = scan_complete_rrm_cb, + .scan_issue_pbreq = scan_issue_pbreq_cb, + .scan_issue_null_data = scan_issu_null_data_cb +}; +#endif /* CONFIG_RTW_80211K */ + +#define SCANNING_TIMEOUT_EX 2000 +static u32 rtw_scan_timeout_decision(_adapter *padapter) +{ + u32 back_op_times= 0; + u8 max_chan_num; + u16 scan_ms; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + + if (is_supported_5g(padapter->registrypriv.band_type) + && is_supported_24g(padapter->registrypriv.band_type)) + max_chan_num = MAX_CHANNEL_NUM_2G_5G;/* dual band */ + else + max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/ + + #ifdef CONFIG_SCAN_BACKOP + /* delay 50ms to protect nulldata(1) */ + if (rtw_scan_backop_decision(padapter)) + back_op_times = (max_chan_num / ss->scan_cnt_max) * (ss->backop_ms + 50); + #endif + + if (ss->duration) + scan_ms = ss->duration; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; + + ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX; + #ifdef DBG_SITESURVEY + RTW_INFO("%s , scan_timeout_ms = %d (ms), scan_ms=%d (ms), \ + back_op_times=%d (ms), ss->duration=%d (ms)\n" \ + , __func__, ss->scan_timeout_ms, scan_ms, back_op_times, ss->duration); + #endif /*DBG_SITESURVEY*/ + + return ss->scan_timeout_ms; +} + +/* +rtw_sitesurvey_cmd(~) + ### NOTE:#### (!!!!) + MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock +*/ +#ifdef CONFIG_CMD_SCAN +static void scan_channel_list_filled(_adapter *padapter, + struct rtw_phl_scan_param *phl_param, struct sitesurvey_parm *param) +{ + struct phl_scan_channel *phl_ch = phl_param->ch; + u8 i = 0; + + for (i = 0; i < param->ch_num; i++) { + phl_ch[i].channel = param->ch[i].hw_value; + phl_ch[i].scan_mode = NORMAL_SCAN_MODE; + phl_ch[i].bw = param->bw; + phl_ch[i].duration = param->duration; + + if (param->ch[i].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) + phl_ch[i].type = RTW_PHL_SCAN_PASSIVE; + else + phl_ch[i].type = RTW_PHL_SCAN_ACTIVE; + } + phl_param->ch_num = param->ch_num; +} + +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN +/* + * Count extended active scan time(ms) and add time to + * struct mlme_ext_priv.sitesurvey_res.scan_timeout_ms. + * + * Return extended active scan time which unit is ms. + */ +static u32 _scan_ext_act_time_count(struct _ADAPTER *a, + struct rtw_phl_scan_param *scan) +{ + struct ss_res *ss = &a->mlmeextpriv.sitesurvey_res; + u16 ext_time = 0; + int i; + + + for (i = 0; i < scan->ch_num; i++) { + if (scan->ch[i].ext_act_scan == EXT_ACT_SCAN_ENABLE) + ext_time += scan->ext_act_scan_period; + } +#ifdef DBG_SITESURVEY + RTW_PRINT(FUNC_ADPT_FMT ": Add extend active scan time %u ms to total " + "scan time (from %u to %u)\n", + FUNC_ADPT_ARG(a), ext_time, ss->scan_timeout_ms, + ext_time + ss->scan_timeout_ms); +#endif /* DBG_SITESURVEY */ + ss->scan_timeout_ms += ext_time; + + return ext_time; +} +#endif /* RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ + +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm) +{ + u8 res = _FAIL; + u8 i; + u32 scan_timeout_ms; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rtw_phl_scan_param *phl_param = NULL; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT] = {0}; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct sitesurvey_parm *tmp_parm = NULL; + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); +#ifdef CONFIG_RTW_80211K + struct scan_priv *scan_priv = NULL; +#endif + + if (pparm == NULL) { + tmp_parm = rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (tmp_parm == NULL) { + RTW_ERR("%s alloc tmp_parm fail\n", __func__); + goto _err_exit; + } + rtw_init_sitesurvey_parm(padapter, tmp_parm); + pparm = tmp_parm; + } + + /* backup original ch list */ + _rtw_memcpy(ch, pparm->ch, + sizeof(struct rtw_ieee80211_channel) * pparm->ch_num); + + /* modify ch list according to chanel plan */ + pparm->ch_num = rtw_scan_ch_decision(padapter, + pparm->ch, RTW_CHANNEL_SCAN_AMOUNT, + ch, pparm->ch_num, pparm->acs); + + if (pparm->duration == 0) + pparm->duration = ss->scan_ch_ms; /* ms */ + + /*create mem of PHL Scan parameter*/ + phl_param = _alloc_phl_param(padapter, pparm->ch_num); + if (phl_param == NULL) { + RTW_ERR("%s alloc phl_param fail\n", __func__); + goto _err_param; + } + + /* STEP_1 transfer to rtw channel list to phl channel list */ + scan_channel_list_filled(padapter, phl_param, pparm); + + /* STEP_2 copy the ssid info to phl param */ + phl_param->ssid_num = rtw_min(pparm->ssid_num, SCAN_SSID_AMOUNT); + for (i = 0; i < phl_param->ssid_num; ++i) { + phl_param->ssid[i].ssid_len = pparm->ssid[i].SsidLength; + _rtw_memcpy(&phl_param->ssid[i].ssid, &pparm->ssid[i].Ssid, phl_param->ssid[i].ssid_len); + } +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + /* STEP_2.1 set EXT_ACT_SCAN_ENABLE for hidden AP scan */ + if (phl_param->ssid[0].ssid_len) { + phl_param->ext_act_scan_period = RTW_EXTEND_ACTIVE_SCAN_PERIOD; + for (i = 0; i < phl_param->ch_num; i++) { + int chset_idx; + chset_idx = rtw_chset_search_ch(rfctl->channel_set, + phl_param->ch[i].channel); + if (chset_idx < 0) { + RTW_ERR(FUNC_ADPT_FMT ": cann't find ch %u in chset!\n", + FUNC_ADPT_ARG(padapter), phl_param->ch[i].channel); + continue; + } + + if ((phl_param->ch[i].type == RTW_PHL_SCAN_PASSIVE) + && (!IS_DFS_SLAVE_WITH_RD(rfctl) + || rtw_rfctl_dfs_domain_unknown(rfctl) + || !CH_IS_NON_OCP(&rfctl->channel_set[chset_idx]))) + phl_param->ch[i].ext_act_scan = EXT_ACT_SCAN_ENABLE; + } + } +#endif /* RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ + + /* STEP_3 set ops according to scan_type */ + switch (pparm->scan_type) { + #ifdef CONFIG_P2P + case RTW_SCAN_P2P: + phl_param->ops = &scan_ops_p2p_cb; + break; + #endif + + #ifdef CONFIG_RTW_80211K + case RTW_SCAN_RRM: + phl_param->ops = &scan_ops_rrm_cb; + scan_priv = (struct scan_priv *)phl_param->priv; + scan_priv->rrm_token = pparm->rrm_token; + ss->token = pparm->rrm_token; + break; + #endif + + case RTW_SCAN_NORMAL: + default: + phl_param->ops = &scan_ops_cb; +#ifdef CONFIG_SCAN_BACKOP + if (rtw_scan_backop_decision(padapter)) { + phl_param->back_op_ch_dur_ms = ss->backop_ms; + phl_param->back_op_mode = SCAN_BKOP_CNT; + phl_param->back_op_ch_cnt = ss->scan_cnt_max; + } else { + phl_param->back_op_mode = SCAN_BKOP_NONE; + } +#else + phl_param->back_op_mode = SCAN_BKOP_NONE; +#endif /* CONFIG_SCAN_BACKOP */ + break; + } + + /* STEP_4 reset variables for each scan */ + for (i = 0; i < MAX_CHANNEL_NUM; i++) + rfctl->channel_set[i].hidden_bss_cnt = 0; + + set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY); + + if(rtw_phl_cmd_scan_request(dvobj->phl, phl_param, true) != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("%s request scam_cmd failed\n", __func__); + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + goto _err_req_param; + } + + pmlmeext->sitesurvey_res.scan_param = phl_param; + rtw_free_network_queue(padapter, _FALSE); + + pmlmepriv->scan_start_time = rtw_get_current_time(); + scan_timeout_ms = rtw_scan_timeout_decision(padapter); +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + scan_timeout_ms += _scan_ext_act_time_count(padapter, phl_param); +#endif /* RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN */ + mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms); + + rtw_led_control(padapter, LED_CTL_SITE_SURVEY); + if (tmp_parm) + rtw_mfree(tmp_parm, sizeof(*tmp_parm)); + res = _SUCCESS; + return res; + +_err_req_param: + _free_phl_param(padapter, phl_param); +_err_param: + if (tmp_parm) + rtw_mfree(tmp_parm, sizeof(*tmp_parm)); +_err_exit: + rtw_warn_on(1); + return res; +} + +#else /*!CONFIG_CMD_SCAN*/ + +/** + * prepare phl_channel list according to SCAN type + * + */ +static int scan_channel_list_preparation(_adapter *padapter, + struct rtw_phl_scan_param *dst, struct sitesurvey_parm *src) +{ + struct phl_scan_channel *phl_ch = NULL; + int phl_ch_sz = 0; + int i; + + phl_ch_sz = sizeof(struct phl_scan_channel) * (src->ch_num + 1); + + phl_ch = rtw_malloc(phl_ch_sz); + if (phl_ch == NULL) { + RTW_ERR("scan: alloc phl scan ch fail\n"); + return -1; + } + _rtw_memset(phl_ch, 0, phl_ch_sz); + + i = 0; + while (i < src->ch_num) { + + phl_ch[i].channel = src->ch[i].hw_value; + phl_ch[i].scan_mode = NORMAL_SCAN_MODE; + phl_ch[i].bw = src->bw; + phl_ch[i].duration = src->duration; + + if (src->ch[i].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) { + phl_ch[i].type = RTW_PHL_SCAN_PASSIVE; + + } else { + phl_ch[i].type = RTW_PHL_SCAN_ACTIVE; + + /* reduce scan time in active channel */ + if (src->scan_type == RTW_SCAN_NORMAL) + phl_ch[i].duration = src->duration >> 1; + } + i++; + } + + dst->ch = phl_ch; + dst->ch_sz = phl_ch_sz; + dst->ch_num = src->ch_num; + + return 0; +} + +u32 rtw_site_survey_fsm(_adapter *padapter, struct cmd_obj *pcmd) +{ + u32 res = RTW_PHL_STATUS_FAILURE; + struct scan_priv *scan_priv; + struct rtw_phl_scan_param *phl_param; + struct sitesurvey_parm *rtw_param; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + u8 i; + + scan_priv = rtw_malloc(sizeof(*scan_priv)); + if (scan_priv == NULL) { + RTW_ERR("scan: %s alloc scan_priv fail\n", __func__); + return RTW_PHL_STATUS_FAILURE; + } + _rtw_memset(scan_priv, 0, sizeof(*scan_priv)); + scan_priv->padapter = padapter; + rtw_param = (struct sitesurvey_parm *)pcmd->parmbuf; + + if (rtw_param->duration == 0) + rtw_param->duration = SURVEY_TO; /* ms */ + + /* backup original ch list */ + _rtw_memcpy(ch, rtw_param->ch, + sizeof(struct rtw_ieee80211_channel) * + rtw_param->ch_num); + + /* modify ch list according to chanel plan */ + rtw_param->ch_num = rtw_scan_ch_decision(padapter, + rtw_param->ch, RTW_CHANNEL_SCAN_AMOUNT, + ch, rtw_param->ch_num, rtw_param->acs); + + phl_param = rtw_malloc(sizeof(*phl_param)); + if (phl_param == NULL) { + RTW_ERR("scan: %s alloc param fail\n", __func__); + if (scan_priv) + rtw_mfree(scan_priv, sizeof(*scan_priv)); + return RTW_PHL_STATUS_FAILURE; + } + _rtw_memset(phl_param, 0, sizeof(*phl_param)); + + /* transfer to rtw channel list to phl channel list */ + scan_channel_list_preparation(padapter, phl_param, rtw_param); + + /* copy the ssid info to phl param */ + phl_param->ssid_num = rtw_min(rtw_param->ssid_num, SCAN_SSID_AMOUNT); + for (i = 0; i < phl_param->ssid_num; ++i) { + phl_param->ssid[i].ssid_len = rtw_param->ssid[i].SsidLength; + _rtw_memcpy(&phl_param->ssid[i].ssid, &rtw_param->ssid[i].Ssid, phl_param->ssid[i].ssid_len); + } + + switch (rtw_param->scan_type) { +#ifdef CONFIG_P2P + case RTW_SCAN_P2P: + phl_param->ops = &scan_ops_p2p_cb; + break; +#endif +#ifdef CONFIG_RTW_80211K + case RTW_SCAN_RRM: + phl_param->ops = &scan_ops_rrm_cb; + if (rtw_param->ch_num > 13) { + phl_param->back_op_mode = SCAN_BKOP_CNT; + phl_param->back_op_ch_cnt = 3; + } + break; +#endif + case RTW_SCAN_NORMAL: + default: + phl_param->ops = &scan_ops_cb; + phl_param->back_op_mode = SCAN_BKOP_CNT; + phl_param->back_op_ch_cnt = 3; + break; + } + phl_param->priv = scan_priv; + phl_param->wifi_role = padapter->phl_role; + + res = rtw_phl_scan_request(adapter_to_dvobj(padapter)->phl, phl_param, TO_TAIL); + rtw_mfree(phl_param->ch, phl_param->ch_sz); + rtw_mfree(phl_param, sizeof(*phl_param)); + + return res; +} + +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm) +{ + u8 res = _FAIL; + struct cmd_obj *cmd; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &adapter_to_dvobj(padapter)->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +#ifdef CONFIG_LPS + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 0); +#endif + +#ifdef CONFIG_P2P_PS + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); +#endif /* CONFIG_P2P_PS */ + + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) + return _FAIL; + cmd->padapter = padapter; + + psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_mfree((unsigned char *) cmd, sizeof(struct cmd_obj)); + return _FAIL; + } + + if (pparm) + _rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm)); + else + psurveyPara->scan_mode = pmlmepriv->scan_mode; + + rtw_free_network_queue(padapter, _FALSE); + + init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, CMD_SITE_SURVEY); + + set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY); + + + res = rtw_enqueue_cmd(pcmdpriv, cmd); + + if (res == _SUCCESS) { + u32 scan_timeout_ms; + + pmlmepriv->scan_start_time = rtw_get_current_time(); + scan_timeout_ms = rtw_scan_timeout_decision(padapter); + mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms); + + rtw_led_control(padapter, LED_CTL_SITE_SURVEY); + } else { + _clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY); + } + + + return res; +} +#endif/*CONFIG_CMD_SCAN*/ + + +/* inform caller phl_scan are ready on remain channel */ +static int roch_ready_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct cfg80211_roch_info *pcfg80211_rochinfo = + &padapter->cfg80211_rochinfo; + + RTW_INFO("%s cookie:0x%llx\n", __func__, + pcfg80211_rochinfo->remain_on_ch_cookie); + + if ((scan_priv->roch_step & ROCH_CH_READY)) + return 0; + + scan_priv->roch_step |= ROCH_CH_READY; + + rtw_cfg80211_ready_on_channel( + scan_priv->wdev, + scan_priv->cookie, + &scan_priv->channel, + scan_priv->channel_type, + scan_priv->duration, + GFP_KERNEL); + return 0; +} + +static int roch_off_ch_tx_cb(void *priv, + struct rtw_phl_scan_param *param, void *data) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + struct dvobj_priv *dvobj = adapter_to_dvobj(scan_priv->padapter); + +#ifdef CONFIG_CMD_SCAN + RTW_ERR("CMD_SCAN call %s\n", __func__); + rtw_warn_on(1); +#else + phl_cmd_complete_job(dvobj->phl, (struct phl_cmd_job *)data); +#endif + return 0; +} + +#ifdef CONFIG_P2P +static int p2p_roch_complete_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + int ret = _FAIL; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct cfg80211_roch_info *pcfg80211_rochinfo = + &padapter->cfg80211_rochinfo; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + if (!rtw_is_adapter_up(padapter)) + goto _exit; + + mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE); + + /* roch_ready() and roch_complete() MUST be a PAIR + * otherwise will caurse wpa_supplicant hang!!! + * This case may happen when someone cancel remain on ch + * before it really start. (called roch_ready()). + */ + if (!(scan_priv->roch_step & ROCH_CH_READY)) + roch_ready_cb(priv, param); + +#ifndef CONFIG_CMD_SCAN + rtw_back_opch(padapter); +#endif +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("%s, role=%d\n", __func__, rtw_p2p_role(pwdinfo)); +#endif + + rtw_cfg80211_set_is_roch(padapter, _FALSE); + pcfg80211_rochinfo->ro_ch_wdev = NULL; + rtw_cfg80211_set_last_ro_ch_time(padapter); + + ret = _SUCCESS; +_exit: + /* callback to cfg80211 */ + rtw_cfg80211_remain_on_channel_expired(scan_priv->wdev + , scan_priv->cookie + , &scan_priv->channel + , scan_priv->channel_type, GFP_KERNEL); + + RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n" + , pcfg80211_rochinfo->remain_on_ch_cookie); + + RTW_INFO(FUNC_ADPT_FMT" takes %d ms to scan %d/%d channels\n", + FUNC_ADPT_ARG(padapter), param->total_scan_time, + #ifdef CONFIG_CMD_SCAN + param->ch_idx, + #else + param->ch_idx + 1, + #endif + param->ch_num); + _rtw_scan_abort_check(padapter, __func__); + +#ifdef CONFIG_CMD_SCAN + _free_phl_param(padapter, param); + padapter->mlmeextpriv.sitesurvey_res.scan_param = NULL; +#else + rtw_mfree(scan_priv, sizeof(*scan_priv)); +#endif + return ret; +} + +static int p2p_roch_start_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct cfg80211_roch_info *pcfg80211_rochinfo; + + pcfg80211_rochinfo = &padapter->cfg80211_rochinfo; + + //TODO remove + mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_PROCESS); + + rtw_cfg80211_set_is_roch(padapter, _TRUE); + pcfg80211_rochinfo->ro_ch_wdev = scan_priv->wdev; + pcfg80211_rochinfo->remain_on_ch_cookie = scan_priv->cookie; + pcfg80211_rochinfo->duration = scan_priv->duration; + rtw_cfg80211_set_last_ro_ch_time(padapter); + _rtw_memcpy(&pcfg80211_rochinfo->remain_on_ch_channel, + &scan_priv->channel, sizeof(struct ieee80211_channel)); + #if (KERNEL_VERSION(3, 8, 0) > LINUX_VERSION_CODE) + pcfg80211_rochinfo->remain_on_ch_type = scan_priv->channel_type; + #endif + pcfg80211_rochinfo->restore_channel = scan_priv->restore_ch; + + #ifdef CONFIG_CMD_SCAN + padapter->mlmeextpriv.sitesurvey_res.scan_param = param; + #endif + + return 0; +} +#endif + +static int roch_start_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + + mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_PROCESS); + rtw_cfg80211_set_is_roch(padapter, _TRUE); + #ifdef CONFIG_CMD_SCAN + padapter->mlmeextpriv.sitesurvey_res.scan_param = param; + #endif + + return 0; +} + +static int roch_complete_cb(void *priv, struct rtw_phl_scan_param *param) +{ + struct scan_priv *scan_priv = (struct scan_priv *)priv; + _adapter *padapter = scan_priv->padapter; + struct cfg80211_roch_info *pcfg80211_rochinfo = + &padapter->cfg80211_rochinfo; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + int ret = _FAIL; + + if (!rtw_is_adapter_up(padapter)) + goto _exit; + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + + /* roch_ready() and roch_complete() MUST be a PAIR + * otherwise will caurse wpa_supplicant hang!!! + * This case may happen when someone cancel remain on ch + * before it really start. (called roch_ready()). + */ + if (!(scan_priv->roch_step & ROCH_CH_READY)) + roch_ready_cb(priv, param); + + rtw_cfg80211_set_is_roch(padapter, _FALSE); + + ret = _SUCCESS; + +_exit: + /* callback to cfg80211 */ + rtw_cfg80211_remain_on_channel_expired(scan_priv->wdev + , scan_priv->cookie + , &scan_priv->channel + , scan_priv->channel_type, GFP_KERNEL); + + RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n" + , pcfg80211_rochinfo->remain_on_ch_cookie); + + RTW_INFO(FUNC_ADPT_FMT" takes %d ms to scan %d/%d channels\n", + FUNC_ADPT_ARG(padapter), param->total_scan_time, + #ifdef CONFIG_CMD_SCAN + param->ch_idx, + #else + param->ch_idx + 1, + #endif + param->ch_num); + _rtw_scan_abort_check(padapter, __func__); + +#ifdef CONFIG_CMD_SCAN + _free_phl_param(padapter, param); + pmlmeext->sitesurvey_res.scan_param = NULL; +#else + rtw_mfree(scan_priv, sizeof(*scan_priv)); +#endif + return ret; +} + +#ifdef CONFIG_P2P +/* p2p remain on channel */ +static struct rtw_phl_scan_ops p2p_remain_ops_cb = { + .scan_start = p2p_roch_start_cb, + .scan_ch_ready = roch_ready_cb, + .scan_off_ch_tx = roch_off_ch_tx_cb, + .scan_complete = p2p_roch_complete_cb, + .scan_issue_null_data = scan_issu_null_data_cb +}; +#endif + +/* normal remain on channel */ +static struct rtw_phl_scan_ops remain_ops_cb = { + .scan_start = roch_start_cb, + .scan_ch_ready = roch_ready_cb, + .scan_off_ch_tx = roch_off_ch_tx_cb, + .scan_complete = roch_complete_cb, + .scan_issue_null_data = scan_issu_null_data_cb +}; + +#ifdef CONFIG_IOCTL_CFG80211 +static u8 roch_stay_in_cur_chan(_adapter *padapter) +{ + int i; + _adapter *iface; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 rst = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + pmlmepriv = &iface->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) { + RTW_INFO(ADPT_FMT"- WIFI_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\n", + ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); + rst = _TRUE; + break; + } + #ifdef CONFIG_AP_MODE + if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + if (rtw_ap_sta_states_check(iface) == _TRUE) { + rst = _TRUE; + break; + } + } + #endif + } + } + + return rst; +} + +#ifdef CONFIG_CMD_SCAN +u8 rtw_phl_remain_on_ch_cmd(_adapter *padapter, + u64 cookie, struct wireless_dev *wdev, + struct ieee80211_channel *ch, u8 ch_type, + unsigned int duration, struct back_op_param *bkop_parm, + u8 is_p2p) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_scan_param *phl_param = NULL; + struct scan_priv *scan_priv = NULL; + u16 remain_ch; + u8 chan_num; + u8 res = _FAIL; + + /* prepare remain channel - check channel */ + remain_ch = (u16)ieee80211_frequency_to_channel(ch->center_freq); + if (roch_stay_in_cur_chan(padapter) == _TRUE) { /*???*/ + remain_ch = rtw_mi_get_union_chan(padapter); + RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", + FUNC_ADPT_ARG(padapter), remain_ch); + } + chan_num = 1; + + phl_param = _alloc_phl_param(padapter, chan_num); + if (phl_param == NULL) { + RTW_ERR("%s alloc phl_param fail\n", __func__); + goto _err_exit; + } + + /*** fill phl parameter - scan_priv ***/ + scan_priv = (struct scan_priv *)phl_param->priv; + scan_priv->padapter = padapter; + scan_priv->wdev = wdev; + _rtw_memcpy(&scan_priv->channel, ch, sizeof(*ch)); + scan_priv->channel_type = ch_type; + scan_priv->cookie = cookie; + scan_priv->duration = duration; + scan_priv->restore_ch = rtw_get_oper_ch(padapter); + + /* fill phl param - chan */ + phl_param->ch->channel = remain_ch; + phl_param->ch->duration = duration; + phl_param->ch->scan_mode = P2P_LISTEN_MODE; + phl_param->ch->bw = CHANNEL_WIDTH_20; + phl_param->ch_num = chan_num; + + /* fill back op param */ + phl_param->back_op_mode = SCAN_BKOP_TIMER; + phl_param->back_op_ch_cnt = 1; + phl_param->back_op_ch_dur_ms = bkop_parm->on_ch_dur;/*op_ch time*/ + phl_param->back_op_off_ch_dur_ms = bkop_parm->off_ch_dur;/*ro_ch time*/ + phl_param->back_op_off_ch_ext_dur_ms = bkop_parm->off_ch_ext_dur; + +#ifdef CONFIG_P2P + /* set ops according to is_p2p */ + if (is_p2p) + phl_param->ops = &p2p_remain_ops_cb; + else +#endif + phl_param->ops = &remain_ops_cb; + + if(rtw_phl_cmd_scan_request(dvobj->phl, phl_param, true) == RTW_PHL_STATUS_FAILURE) { + RTW_ERR("%s request scam_cmd failed\n", __func__); + goto _err_req_param; + } + + + RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), remain_ch, duration, cookie); + res = _SUCCESS; + return res; + +_err_req_param: + _free_phl_param(padapter, phl_param); +_err_exit: + rtw_warn_on(1); + return res; +} + +#else +u8 rtw_phl_remain_on_ch_cmd(_adapter *padapter, + u64 cookie, struct wireless_dev *wdev, + struct ieee80211_channel *ch, u8 ch_type, + unsigned int duration, struct back_op_param *bkop_parm, + u8 is_p2p) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_scan_param phl_param; + struct scan_priv *scan_priv; + struct phl_scan_channel phl_ch; + int phl_ch_sz = 0; + u16 remain_ch; + u8 res = _FAIL; + + _rtw_memset(&phl_param, 0, sizeof(phl_param)); + + scan_priv = rtw_malloc(sizeof(*scan_priv)); + if (scan_priv == NULL) { + RTW_ERR("scan: %s alloc scan_priv fail\n", __func__); + return res; + } + _rtw_memset(scan_priv, 0, sizeof(*scan_priv)); + + scan_priv->padapter = padapter; + scan_priv->wdev = wdev; + _rtw_memcpy(&scan_priv->channel, ch, sizeof(*ch)); + scan_priv->channel_type = ch_type; + + scan_priv->cookie = cookie; + scan_priv->duration = duration; + scan_priv->restore_ch = rtw_get_oper_ch(padapter); + + phl_param.priv = scan_priv; + + /* check channel */ + remain_ch = (u16)ieee80211_frequency_to_channel(ch->center_freq); + + if (roch_stay_in_cur_chan(padapter) == _TRUE) { + remain_ch = rtw_mi_get_union_chan(padapter); + RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", + FUNC_ADPT_ARG(padapter), remain_ch); + } + + /* prepare remain channel */ + phl_ch_sz = sizeof(struct phl_scan_channel); + _rtw_memset(&phl_ch, 0, phl_ch_sz); + + phl_ch.channel = remain_ch; + phl_ch.duration = scan_priv->duration; + phl_ch.scan_mode = NORMAL_SCAN_MODE; + phl_ch.bw = CHANNEL_WIDTH_20; + + phl_param.ch = &phl_ch; + phl_param.ch_sz = phl_ch_sz; + phl_param.ch_num = 1; + phl_param.wifi_role = padapter->phl_role; + + phl_param.back_op_mode = SCAN_BKOP_TIMER; + phl_param.back_op_ch_dur_ms = bkop_parm->on_ch_dur; + phl_param.back_op_off_ch_dur_ms = bkop_parm->off_ch_dur; + phl_param.back_op_off_ch_ext_dur_ms = bkop_parm->off_ch_ext_dur; + +#ifdef CONFIG_P2P + if (is_p2p) + phl_param.ops = &p2p_remain_ops_cb; + else +#endif + phl_param.ops = &remain_ops_cb; + + RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), phl_ch.channel, + scan_priv->duration, cookie); + + /* sent message to request phl scan + * IMMEDIATE imply cancelling previous scan request if has + */ + rtw_phl_scan_request(dvobj->phl, &phl_param, IMMEDIATE); + + /* scan_priv will be cancelled in roch_complete_cb */ + res = _SUCCESS; + return res; +} +#endif +#endif /*CONFIG_IOCTL_CFG80211*/ + +#endif /*CONFIG_PHL_ARCH*/ diff --git a/core/rtw_sdio.c b/core/rtw_sdio.c index cdadbaf..f616723 100644 --- a/core/rtw_sdio.c +++ b/core/rtw_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2019 Realtek Corporation. + * Copyright(c) 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -37,7 +37,7 @@ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 writ { #ifdef DBG_SDIO #if (DBG_SDIO >= 3) - struct sdio_data *sdio; + struct sdio_data *sdio = dvobj_to_sdio(d); #endif /* DBG_SDIO >= 3 */ #endif /* DBG_SDIO */ u32 addr_drv; /* address with driver defined bit */ @@ -45,14 +45,7 @@ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 writ u8 retry = 0; u8 stop_retry = _FALSE; /* flag for stopping retry or not */ - -#ifdef DBG_SDIO -#if (DBG_SDIO >= 3) - sdio = &d->intf_data; -#endif /* DBG_SDIO >= 3 */ -#endif /* DBG_SDIO */ - - if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) { + if (dev_is_surprise_removed(d)) { RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n", __FUNCTION__, write?"write":"read", addr, len); return _FAIL; @@ -90,7 +83,7 @@ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 writ if (sdio->err_stop) { RTW_ERR("%s: I/O error! Set surprise remove flag ON!\n", __FUNCTION__); - rtw_set_surprise_removed(dvobj_get_primary_adapter(d)); + dev_set_surprise_removed(d); return _FAIL; } } @@ -103,7 +96,7 @@ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 writ /* critical error, unrecoverable */ RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n", __FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error)); - rtw_set_surprise_removed(dvobj_get_primary_adapter(d)); + dev_set_surprise_removed(d); return _FAIL; } @@ -155,3 +148,27 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len) return ret; } + +/** + * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete + * @d struct dvobj_priv* + * @len length to align + * + * Adjust len to align block size, and the new size could be transfered by one + * CMD53. + * If len < block size, it would keep original value, otherwise the value + * would be rounded up by block size. + * + * Return adjusted length. + */ +size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len) +{ + u32 blk_sz; + + + blk_sz = rtw_sdio_get_block_size(d); + if (len <= blk_sz) + return len; + + return _RND(len, blk_sz); +} diff --git a/core/rtw_sec_cam.c b/core/rtw_sec_cam.c new file mode 100644 index 0000000..dce450a --- /dev/null +++ b/core/rtw_sec_cam.c @@ -0,0 +1,1059 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_SEC_CAM_C_ + +#include +#include + +void invalidate_cam_all(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + u8 val8 = 0; + + rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8); + + _rtw_spinlock_bh(&cam_ctl->lock); + rtw_sec_cam_map_clr_all(&cam_ctl->used); + _rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT); + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +void _clear_cam_entry(_adapter *padapter, u8 entry) +{ + unsigned char null_sta[6] = {0}; + unsigned char null_key[32] = {0}; + + rtw_hal_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key); +} + +inline void _write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ +#ifdef CONFIG_WRITE_CACHE_ONLY + write_cam_cache(adapter, id , ctrl, mac, key); +#else + rtw_hal_sec_write_cam_ent(adapter, id, ctrl, mac, key); + write_cam_cache(adapter, id , ctrl, mac, key); +#endif +} + +inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + if (ctrl & BIT(9)) { + _write_cam(adapter, id, ctrl, mac, key); + _write_cam(adapter, (id + 1), ctrl | BIT(5), mac, (key + 16)); + RTW_INFO_DUMP("key-0: ", key, 16); + RTW_INFO_DUMP("key-1: ", (key + 16), 16); + } else + _write_cam(adapter, id, ctrl, mac, key); +} + +inline void clear_cam_entry(_adapter *adapter, u8 id) +{ + _clear_cam_entry(adapter, id); + clear_cam_cache(adapter, id); +} + +inline void write_cam_from_cache(_adapter *adapter, u8 id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + struct sec_cam_ent cache; + + _rtw_spinlock_bh(&cam_ctl->lock); + _rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent)); + _rtw_spinunlock_bh(&cam_ctl->lock); + + rtw_hal_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key); +} +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + + dvobj->cam_cache[id].ctrl = ctrl; + _rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN); + _rtw_memcpy(dvobj->cam_cache[id].key, key, 16); + + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +void clear_cam_cache(_adapter *adapter, u8 id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + + _rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent)); + + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->sec_cap & cap) + return _TRUE; + return _FALSE; +} + +inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags |= flags; +} + +inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + _rtw_camctl_set_flags(adapter, flags); + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags &= ~flags; +} + +inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + _rtw_camctl_clr_flags(adapter, flags); + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->flags & flags) + return _TRUE; + return _FALSE; +} + +void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num) +{ + RTW_PRINT_SEL(sel, "0x%08x\n", map->m0); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + if (max_num && max_num > 32) + RTW_PRINT_SEL(sel, "0x%08x\n", map->m1); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + if (max_num && max_num > 64) + RTW_PRINT_SEL(sel, "0x%08x\n", map->m2); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + if (max_num && max_num > 96) + RTW_PRINT_SEL(sel, "0x%08x\n", map->m3); +#endif +} + +inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + return map->m0 & BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + return map->m1 & BIT(id - 32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + return map->m2 & BIT(id - 64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + return map->m3 & BIT(id - 96); +#endif + else + rtw_warn_on(1); + + return 0; +} + +inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 |= BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 |= BIT(id - 32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 |= BIT(id - 64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 |= BIT(id - 96); +#endif + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 &= ~BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 &= ~BIT(id - 32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 &= ~BIT(id - 64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 &= ~BIT(id - 96); +#endif + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map) +{ + map->m0 = 0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + map->m1 = 0; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + map->m2 = 0; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + map->m3 = 0; +#endif +} + +inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id) +{ + struct sec_cam_bmp forbid_map; + + forbid_map.m0 = 0x00000ff0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + forbid_map.m1 = 0x00000000; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + forbid_map.m2 = 0x00000000; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + forbid_map.m3 = 0x00000000; +#endif + + if (id < 32) + return forbid_map.m0 & BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + return forbid_map.m1 & BIT(id - 32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + return forbid_map.m2 & BIT(id - 64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + return forbid_map.m3 & BIT(id - 96); +#endif + else + rtw_warn_on(1); + + return 1; +} + +bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + bool ret = _FALSE; + + if (id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + +#if 0 /* for testing */ + if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) { + ret = _TRUE; + goto exit; + } +#endif + + ret = rtw_sec_camid_is_set(&cam_ctl->used, id); + +exit: + return ret; +} + +inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + bool ret; + + _rtw_spinlock_bh(&cam_ctl->lock); + ret = _rtw_sec_camid_is_used(cam_ctl, id); + _rtw_spinunlock_bh(&cam_ctl->lock); + + return ret; +} +u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + + u8 sec_cam_num = 0; + + _rtw_spinlock_bh(&cam_ctl->lock); + for (i = 0; i < cam_ctl->num; i++) { + if (_rtw_sec_camid_is_used(cam_ctl, i)) { + sec_key_id[sec_cam_num++] = i; + if (sec_cam_num == max_bk_key_num) + break; + } + } + _rtw_spinunlock_bh(&cam_ctl->lock); + + return sec_cam_num; +} + +inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + bool ret = _FALSE; + + if (cam_id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + + if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE) + goto exit; + + ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE; + +exit: + return ret; +} + +inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + bool ret; + + _rtw_spinlock_bh(&cam_ctl->lock); + ret = _rtw_camid_is_gk(adapter, cam_id); + _rtw_spinunlock_bh(&cam_ctl->lock); + + return ret; +} + +bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + bool ret = _FALSE; + + if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE) + goto exit; + if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03)) + goto exit; + if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id)) + goto exit; + + ret = _TRUE; + +exit: + return ret; +} + +s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + s16 cam_id = -1; + + for (i = 0; i < cam_ctl->num; i++) { + if (cam_cache_chk(adapter, i, addr, kid, gk)) { + cam_id = i; + break; + } + } + + if (0) { + if (addr) + RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id); + else + RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id); + } + + return cam_id; +} + +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + s16 cam_id = -1; + + _rtw_spinlock_bh(&cam_ctl->lock); + cam_id = _rtw_camid_search(adapter, addr, kid, gk); + _rtw_spinunlock_bh(&cam_ctl->lock); + + return cam_id; +} + +s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk, bool ext_sec) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; +#if 0 /* for testing */ + static u8 start_id = 0; +#else + u8 start_id = 0; +#endif + s16 cam_id = -1; + + if (addr == NULL) { + RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n" + , FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + goto _exit; + } + + /* find cam entry which has the same addr, kid (, gk bit) */ + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) + i = _rtw_camid_search(adapter, addr, kid, gk); + else + i = _rtw_camid_search(adapter, addr, kid, -1); + + if (i >= 0) { + cam_id = i; + goto _exit; + } + + for (i = 0; i < cam_ctl->num; i++) { + /* bypass default key which is allocated statically */ +#if 0//ndef CONFIG_CONCURRENT_MODE + if (((i + start_id) % cam_ctl->num) < 4) + continue; +#endif + if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) { + if (ext_sec) { + /* look out continue slot */ + if (((i + 1) < cam_ctl->num) && + (_rtw_sec_camid_is_used(cam_ctl, (((i + 1) + start_id) % cam_ctl->num)) == _FALSE)) + break; + else + continue; + } else + break; + } + } + + if (i == cam_ctl->num) { + RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid); + rtw_warn_on(1); + goto _exit; + } + + cam_id = ((i + start_id) % cam_ctl->num); + start_id = ((i + start_id + 1) % cam_ctl->num); + +_exit: + return cam_id; +} + +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used) +{ + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + s16 cam_id = -1; + + *used = _FALSE; + + _rtw_spinlock_bh(&cam_ctl->lock); + + if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) + && !sta) { + /* + * 1. non-STA mode WEP key + * 2. group TX key + */ +#if 0//ndef CONFIG_CONCURRENT_MODE + /* static alloction to default key by key ID when concurrent is not defined */ + if (kid > 3) { + RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n" + , FUNC_ADPT_ARG(adapter), kid); + rtw_warn_on(1); + goto bitmap_handle; + } + cam_id = kid; +#else + u8 *addr = adapter_mac_addr(adapter); + + cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec); + if (1) + RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id); +#endif + } else { + /* + * 1. STA mode WEP key + * 2. STA mode group RX key + * 3. sta key (pairwise, group RX) + */ + u8 *addr = sta ? sta->phl_sta->mac_addr : NULL; + + if (!sta) { + if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + /* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */ + goto bitmap_handle; + } + addr = get_bssid(&adapter->mlmepriv);/*A2*/ + } + cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec); + } + + +bitmap_handle: + if (cam_id >= 0) { + *used = _rtw_sec_camid_is_used(cam_ctl, cam_id); + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + if (ext_sec) + rtw_sec_cam_map_set(&cam_ctl->used, cam_id + 1); + } + + _rtw_spinunlock_bh(&cam_ctl->lock); + + return cam_id; +} + +void rtw_camid_set(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + + if (cam_id < cam_ctl->num) + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +void rtw_camid_free(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + _rtw_spinlock_bh(&cam_ctl->lock); + + if (cam_id < cam_ctl->num) + rtw_sec_cam_map_clr(&cam_ctl->used, cam_id); + + _rtw_spinunlock_bh(&cam_ctl->lock); +} + +/*Must pause TX/RX before use this API*/ +inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + struct sec_cam_ent cache_a, cache_b; + bool cam_a_used, cam_b_used; + + if (1) + RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b); + + if (cam_id_a == cam_id_b) + return; + + /*setp-1. backup org cam_info*/ + _rtw_spinlock_bh(&cam_ctl->lock); + + cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a); + cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b); + + if (cam_a_used) + _rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent)); + + if (cam_b_used) + _rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent)); + + _rtw_spinunlock_bh(&cam_ctl->lock); + + /*setp-2. clean cam_info*/ + if (cam_a_used) { + rtw_camid_free(adapter, cam_id_a); + clear_cam_entry(adapter, cam_id_a); + } + if (cam_b_used) { + rtw_camid_free(adapter, cam_id_b); + clear_cam_entry(adapter, cam_id_b); + } + + /*setp-3. set cam_info*/ + if (cam_a_used) { + write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key); + rtw_camid_set(adapter, cam_id_b); + } + + if (cam_b_used) { + write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key); + rtw_camid_set(adapter, cam_id_a); + } +} + +s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + s16 cam_id = -1; + + _rtw_spinlock_bh(&cam_ctl->lock); + for (i = start_camid; i < cam_ctl->num; i++) { + if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) { + cam_id = i; + break; + } + } + _rtw_spinunlock_bh(&cam_ctl->lock); + + return cam_id; +} +void rtw_clean_dk_section(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + s16 ept_cam_id; + int i; + + for (i = 0; i < 4; i++) { + if (rtw_sec_camid_is_used(cam_ctl, i)) { + ept_cam_id = rtw_get_empty_cam_entry(adapter, 4); + if (ept_cam_id > 0) + rtw_sec_cam_swap(adapter, i, ept_cam_id); + } + } +} +void rtw_clean_hw_dk_cam(_adapter *adapter) +{ + int i; + + for (i = 0; i < 4; i++) + rtw_hal_sec_clr_cam_ent(adapter, i); + /*_clear_cam_entry(adapter, i);*/ +} + +void flush_all_cam_entry(struct _ADAPTER *a, enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct mlme_ext_info *pmlmeinfo = &a->mlmeextpriv.mlmext_info; + struct sta_priv *stapriv = &a->stapriv; + u8 *mac; + struct sta_info *sta; + + + if (MLME_IS_STA(a)) { + mac = pmlmeinfo->network.MacAddress; + sta = rtw_get_stainfo(stapriv, mac); + if (sta) { + if (sta->state & WIFI_AP_STATE) + /*clear cam when ap free per sta_info*/ + RTW_INFO("%s: sta->state(0x%x) is AP, " + "do nothing\n", + __func__, sta->state); + else + rtw_hw_del_all_key(a, sta, cmd_type, cmd_timeout); + } else { + RTW_WARN("%s: cann't find sta for %pM\n", __func__, mac); + rtw_warn_on(1); + } + } else if (MLME_IS_AP(a) || MLME_IS_MESH(a)) { + mac = adapter_mac_addr(a); + sta = rtw_get_stainfo(stapriv, mac); + if (sta) + rtw_hw_del_all_key(a, sta, cmd_type, cmd_timeout); + } +} + +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + int cam_id = -1; + + cam_id = rtw_phl_wrole_bcmc_id_get(GET_PHL_INFO(dvobj), adapter->phl_role); + if (cam_id != INVALID_SEC_MAC_CAM_ID) + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); +} +#endif + +#ifdef CONFIG_DBG_AX_CAM +/* +1. Mode 0 : no key +2. Mode 1 : unicast 0 - 6 +3. Mode 2 : unicast 0 - 1 Group: 2 - 4 BIP: 5 - 6 +4. Mode 3 : unicast 0 - 1 Group: 2 - 5 BIP: 6 +*/ +static enum CAM_KEY_TYPE search_keytype_by_mode(u8 mode, u8 entry_num) +{ + enum CAM_KEY_TYPE key_type = KEY_TYPE_NONE; + + switch (mode) { + case 0: + key_type = KEY_TYPE_NONE; + break; + case 1: + key_type = KEY_TYPE_UNI; + break; + case 2: + if (entry_num < 2) + key_type = KEY_TYPE_UNI; + else if (entry_num < 5) + key_type = KEY_TYPE_GROUP; + else if (entry_num < 7) + key_type = KEY_TYPE_BIP; + else + key_type = KEY_TYPE_NONE; + break; + case 3: + if (entry_num < 2) + key_type = KEY_TYPE_UNI; + else if (entry_num < 6) + key_type = KEY_TYPE_GROUP; + else if (entry_num < 7) + key_type = KEY_TYPE_BIP; + else + key_type = KEY_TYPE_NONE; + break; + default: + key_type = KEY_TYPE_NONE; + break; + } + return key_type; +} + +static const char* enc_algo_to_string[] = { + "RTW_ENC_NONE", + "RTW_ENC_WEP40", + "RTW_ENC_WEP104", + "RTW_ENC_TKIP", + "RTW_ENC_WAPI", + "RTW_ENC_GCMSMS4", + "RTW_ENC_CCMP", + "RTW_ENC_CCMP256", + "RTW_ENC_GCMP", + "RTW_ENC_GCMP256", + "RTW_ENC_BIP_CCMP128", + "RTW_ENC_MAX" +}; + +static const char* type_to_string[] = { + "unicast", + "multicast", + "BIP", + "NONE" +}; + +static const char* nettype_to_string[] = { + "NoLink", + "Ad-hoc", + "Infra", + "AP" +}; + +static u8 get_keyid(u8 num, u8* addr_cam) +{ + u8 keyid = 0; + + switch (num) { + case 0: + keyid = GET_AX_ADDR_CAM_SEC_ENT0_KEYID(addr_cam); + break; + case 1: + keyid = GET_AX_ADDR_CAM_SEC_ENT1_KEYID(addr_cam); + break; + case 2: + keyid = GET_AX_ADDR_CAM_SEC_ENT2_KEYID(addr_cam); + break; + case 3: + keyid = GET_AX_ADDR_CAM_SEC_ENT3_KEYID(addr_cam); + break; + case 4: + keyid = GET_AX_ADDR_CAM_SEC_ENT4_KEYID(addr_cam); + break; + case 5: + keyid = GET_AX_ADDR_CAM_SEC_ENT5_KEYID(addr_cam); + break; + case 6: + keyid = GET_AX_ADDR_CAM_SEC_ENT6_KEYID(addr_cam); + break; + default: + keyid = 0; + break; + } + return keyid; +} + +static u8 get_sec_entry(u8 num, u8* addr_cam) +{ + u8 entry = 0; + + switch (num) { + case 0: + entry = GET_AX_ADDR_CAM_SEC_ENT0(addr_cam); + break; + case 1: + entry = GET_AX_ADDR_CAM_SEC_ENT1(addr_cam); + break; + case 2: + entry = GET_AX_ADDR_CAM_SEC_ENT2(addr_cam); + break; + case 3: + entry = GET_AX_ADDR_CAM_SEC_ENT3(addr_cam); + break; + case 4: + entry = GET_AX_ADDR_CAM_SEC_ENT4(addr_cam); + break; + case 5: + entry = GET_AX_ADDR_CAM_SEC_ENT5(addr_cam); + break; + case 6: + entry = GET_AX_ADDR_CAM_SEC_ENT6(addr_cam); + break; + default: + entry = 0; + break; + } + return entry; +} + +static void dump_cam_info(void* sel, u8 *buf, u32 start, u32 end) +{ + int i, j = 1; + + for (i = start; i < end; i += 1) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel,"0x%04x", i); + RTW_PRINT_SEL(sel," 0x%08x ", *(u32 *)(buf+ (i*4))); + if ((j++) % 4 == 0) + RTW_PRINT_SEL(sel,"\n"); + } +} + +static void search_sec_cam_by_entry(struct _ADAPTER *a, u8 num, u8* target_entry) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + void *phl; + u32 sec_tmp_buf = 0; + int i; + + phl = GET_PHL_INFO(dvobj); + rtw_phl_write32(phl, INDIRECT_ACCESS_ADDR, (SEC_CAM_BASE_ADDR + num*32)); + + for (i = 0; i < 5; i++) { + sec_tmp_buf = rtw_phl_read32(phl,INDIRECT_ACCESS_VALUE + i*4); + _rtw_memcpy((target_entry + i*4), &sec_tmp_buf, 4); + } +} + +static void search_bssid_cam_by_entry(struct _ADAPTER *a, u8 num, u8* target_entry) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + void *phl; + u32 BSSID_tmp_buf = 0; + int i; + + phl = GET_PHL_INFO(dvobj); + rtw_phl_write32(phl, INDIRECT_ACCESS_ADDR, (BSSID_CAM_BASE_ADDR+ num*8)); + + for (i = 0 ; i < 2; i++) { + BSSID_tmp_buf = rtw_phl_read32(phl,INDIRECT_ACCESS_VALUE + i*4); + _rtw_memcpy((target_entry + i*4), &BSSID_tmp_buf, 4); + } +} + +static u8 varify_256_len(u8 enc) +{ + u8 hit = _FALSE; + + if (enc == 4|| enc == 7|| enc == 9) + hit = _TRUE; + return hit; +} + +int get_ax_address_cam(void* sel, struct _ADAPTER *a) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + void *phl; + /*addr cam: 128 entries*/ + int loop_num = 128; + /*addr cam: 11 DW but the last one all rsvd*/ + u32 addr_tmp_buf = 0; + u8 addr_map[40] = {0}; + int i, j; + + phl = GET_PHL_INFO(dvobj); + + for (i = 0; i < loop_num; i++) { + _rtw_memset(addr_map,0,sizeof(addr_map)); + rtw_phl_write32(phl, INDIRECT_ACCESS_ADDR, (ADDR_CAM_BASE_ADDR + i*64)); + + for (j = 0; j < 10; j++) { + addr_tmp_buf = rtw_phl_read32(phl,INDIRECT_ACCESS_VALUE + j*4); + _rtw_memcpy(&addr_map[j*4], &addr_tmp_buf, 4); + } + RTW_PRINT_SEL(sel, "======= ADDR CAM (%d)DUMP =======\n", i); + dump_cam_info(sel,addr_map,0,10); + RTW_PRINT_SEL(sel, "\n"); + } + return 0; +} + +int get_ax_sec_cam(void* sel, struct _ADAPTER *a) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + void *phl; + /*security cam: 128 entries*/ + int loop_num = 128; + /*security cam: 5 DW*/ + u32 sec_tmp_buf = 0; + u8 sec_map[20] = {0}; + int i, j; + + phl = GET_PHL_INFO(dvobj); + + for (i = 0; i < loop_num; i++) { + _rtw_memset(sec_map,0,sizeof(sec_map)); + rtw_phl_write32(phl, INDIRECT_ACCESS_ADDR, (SEC_CAM_BASE_ADDR + i*32)); + + for (j = 0; j < 5; j++) { + sec_tmp_buf = rtw_phl_read32(phl,INDIRECT_ACCESS_VALUE + j*4); + _rtw_memcpy(&sec_map[j*4], &sec_tmp_buf, 4); + } + + RTW_PRINT_SEL(sel, "======= sec CAM (%d)DUMP =======\n", i); + dump_cam_info(sel, sec_map, 0, 5); + RTW_PRINT_SEL(sel, "\n"); + } + return 0; +} + +static void dump_valid_key(void* sel, u8* addr_map, u8* sec_map, u8* bssid_map\ + , u8 sec_entry, u8 key_type, u8 keyid) +{ + u8 SMA[ETH_ALEN] = {0}, TMA[ETH_ALEN] = {0}; + u8 macid = 0, nettype = 0; + + macid = GET_AX_ADDR_CAM_MACID(addr_map); + nettype = GET_AX_ADDR_CAM_NET_TYPE(addr_map); + + _rtw_memcpy(SMA, &addr_map[8], ETH_ALEN); + _rtw_memcpy(TMA,&addr_map[14], ETH_ALEN); + RTW_PRINT_SEL(sel, "%-5u %s "MAC_FMT" " MAC_FMT" " MAC_FMT\ + " %-5u %-5u %s %-7u %-3u %s "KEY_FMT"\n", macid\ + , nettype_to_string[nettype], MAC_ARG(SMA), MAC_ARG(TMA)\ + , MAC_ARG(&bssid_map[2]), keyid, sec_entry\ + , enc_algo_to_string[GET_AX_SEC_CAM_TYPE(sec_map)] \ + , GET_AX_SEC_CAM_EXT_KEY(sec_map), GET_AX_SEC_SPP_MODE_(sec_map)\ + , type_to_string[key_type], KEY_ARG(&sec_map[4])); +} + +static void prepare_to_dump_valid_key(void* sel, struct _ADAPTER *a, u8* addr_map, u8 ent) +{ + u8 sec_map[20] = {0}; + u8 keyid = 0, sec_entry = 0, key_type = KEY_TYPE_NONE; + u8 bssid_entry; + u8 bssid_map[8] = {0}; + u8 enc_algor = 0; + + key_type = search_keytype_by_mode(GET_AX_ADDR_CAM_SEC_ENT_MODE(addr_map) ,ent); + sec_entry = get_sec_entry(ent, addr_map); + bssid_entry = GET_AX_ADDR_CAM_BSSID_CAM_IDX(addr_map); + keyid = get_keyid(ent,addr_map); + search_sec_cam_by_entry(a, sec_entry, sec_map); + search_bssid_cam_by_entry(a, bssid_entry, bssid_map); + enc_algor = GET_AX_SEC_CAM_TYPE(sec_map); + + if (varify_256_len(enc_algor) == _TRUE) { + dump_valid_key(sel, addr_map, sec_map, bssid_map, sec_entry, key_type, keyid); + search_sec_cam_by_entry(a, sec_entry + 1, sec_map); + dump_valid_key(sel, addr_map, sec_map, bssid_map, sec_entry + 1, key_type, keyid); + } else { + dump_valid_key(sel, addr_map, sec_map, bssid_map, sec_entry, key_type, keyid); + } +} + +int get_ax_valid_key(void* sel, struct _ADAPTER *a) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(a); + void *phl; + /*addr cam: 128 entries*/ + int loop_num = 128; + /*addr cam: 11 DW but the last one all rsvd*/ + u32 addr_tmp_buf = 0; + u8 addr_map[40]= {0}; + u8 sec_ent_valid = 0; + u8 macid = 0; + int i, j; + + phl = GET_PHL_INFO(dvobj); + + RTW_PRINT_SEL(sel, "Dump valid KEY\n"); + RTW_PRINT_SEL(sel, "%-5s %-7s %-17s %-17s %-17s %-5s %-5s %-8s %-3s"\ + " %-3s %s %s\n", "macid", "NETTYPE", "SMA", "TMA", "BSSID", "keyid"\ + , "sec_entry", "enc_algor", "ext_key", "ssp", "key_type", "key"); + + for (i = 0; i < loop_num; i++) { + _rtw_memset(addr_map,0,sizeof(addr_map)); + rtw_phl_write32(phl, INDIRECT_ACCESS_ADDR, (ADDR_CAM_BASE_ADDR + i*64)); + + for (j = 0; j < 10; j++) { + addr_tmp_buf = rtw_phl_read32(phl,INDIRECT_ACCESS_VALUE + j*4); + _rtw_memcpy(&addr_map[j*4], &addr_tmp_buf, 4); + } + sec_ent_valid = GET_AX_ADDR_CAM_SEC_ENT_VALID(addr_map); + + for (j = 0 ;j< 7; j++) { + if (sec_ent_valid & BIT(j)) + prepare_to_dump_valid_key(sel, a, addr_map, j); + } + } + return 0; +} +#endif /* CONFIG_DBG_AX_CAM */ + diff --git a/core/rtw_security.c b/core/rtw_security.c index 639e1e5..3a85090 100644 --- a/core/rtw_security.c +++ b/core/rtw_security.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -271,84 +271,61 @@ static u32 getcrc32(u8 *buf, sint len) return ~crc; /* transmit complement, per CRC-32 spec */ } - /* Need to consider the fragment situation */ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) { - /* exclude ICV */ - - unsigned char crc[4]; - struct arc4context mycontext; - - sint curfragnum, length; - u32 keylength; - - u8 *pframe, *payload, *iv; /* ,*wepkey */ - u8 wepkey[16]; - u8 hw_hdr_offset = 0; - struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - + struct xmit_frame *xf = (struct xmit_frame *)pxmitframe; + struct pkt_attrib *pattrib = &xf->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + unsigned char crc[4]; + struct arc4context mycontext; + sint curfragnum, length; + u32 keylength; + u8 *pframe, *payload, *iv, *key; + u8 wepkey[16]; - if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) + if ((pattrib->encrypt != _WEP40_) && (pattrib->encrypt != _WEP104_)) return; -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + - (((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif - - pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; - /* start to encrypt each fragment */ - if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) { - keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; - - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - iv = pframe + pattrib->hdrlen; - _rtw_memcpy(&wepkey[0], iv, 3); - _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength); - payload = pframe + pattrib->iv_len + pattrib->hdrlen; - - if ((curfragnum + 1) == pattrib->nr_frags) { - /* the last fragment */ - - length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - - *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); - - arcfour_init(&mycontext, wepkey, 3 + keylength); - arcfour_encrypt(&mycontext, payload, payload, length); - arcfour_encrypt(&mycontext, payload + length, crc, 4); - - } else { - length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; - *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); - arcfour_init(&mycontext, wepkey, 3 + keylength); - arcfour_encrypt(&mycontext, payload, payload, length); - arcfour_encrypt(&mycontext, payload + length, crc, 4); - - pframe += pxmitpriv->frag_len; - pframe = (u8 *)RND4((SIZE_PTR)(pframe)); - - } - + keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; + key = psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) { + txreq = &xf->phl_txreq[curfragnum]; + rtw_warn_on(txreq->pkt_cnt != 1); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pframe = pkt_list->vir_addr; + length = pkt_list->length - pattrib->hdrlen + - pattrib->iv_len - pattrib->icv_len; + } else { + /* special case for WEP auth */ + /* only valid when curfragnum==0 */ + rtw_warn_on(pattrib->nr_frags > 1); + pframe = xf->buf_addr + TXDESC_OFFSET; + length = pattrib->last_txcmdsz - pattrib->hdrlen + - pattrib->iv_len - pattrib->icv_len; } + iv = pframe + pattrib->hdrlen; + _rtw_memcpy(&wepkey[0], iv, 3); + _rtw_memcpy(&wepkey[3], key, keylength); + payload = pframe + pattrib->iv_len + pattrib->hdrlen; - WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); + arcfour_init(&mycontext, wepkey, 3 + keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); } - + WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); } void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) @@ -724,123 +701,65 @@ static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16) /* The hlen isn't include the IV */ -u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) { - /* exclude ICV */ - u16 pnl; - u32 pnh; - u8 rc4key[16]; - u8 ttkey[16]; - u8 crc[4]; - u8 hw_hdr_offset = 0; + struct xmit_frame *xf = (struct xmit_frame *)pxmitframe; + struct pkt_attrib *pattrib = &xf->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + u16 pnl; + u32 pnh; + u8 rc4key[16]; + u8 ttkey[16]; + u8 crc[4]; struct arc4context mycontext; - sint curfragnum, length; - u32 prwskeylen; - - u8 *pframe, *payload, *iv, *prwskey; + sint curfragnum, length; + u32 prwskeylen; + u8 *pframe, *payload, *iv, *prwskey; union pn48 dot11txpn; - /* struct sta_info *stainfo; */ - struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - u32 res = _SUCCESS; - if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) - return _FAIL; - -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + - (((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif - pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; - /* 4 start to encrypt each fragment */ - if (pattrib->encrypt == _TKIP_) { - - /* - if(pattrib->psta) - { - stainfo = pattrib->psta; - } - else - { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); - } - */ - /* if (stainfo!=NULL) */ - { - /* - if(!(stainfo->state &WIFI_ASOC_STATE)) - { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state); - return _FAIL; - } - */ - - if (IS_MCAST(pattrib->ra)) - prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; - else { - /* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */ - prwskey = pattrib->dot118021x_UncstKey.skey; - } - - prwskeylen = 16; - - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - iv = pframe + pattrib->hdrlen; - payload = pframe + pattrib->iv_len + pattrib->hdrlen; - - GET_TKIP_PN(iv, dot11txpn); - - pnl = (u16)(dot11txpn.val); - pnh = (u32)(dot11txpn.val >> 16); + if (pattrib->encrypt != _TKIP_) + return _SUCCESS; - phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh); + /* start to encrypt each fragment */ + if (IS_MCAST(pattrib->ra)) + prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + else + prwskey = pattrib->dot118021x_UncstKey.skey; + prwskeylen = 16; - phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl); + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + txreq = &xf->phl_txreq[curfragnum]; + rtw_warn_on(txreq->pkt_cnt != 1); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pframe = pkt_list->vir_addr; + length = pkt_list->length - pattrib->hdrlen + - pattrib->iv_len - pattrib->icv_len; - if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */ - length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/ + iv = pframe + pattrib->hdrlen; + payload = pframe + pattrib->iv_len + pattrib->hdrlen; - arcfour_init(&mycontext, rc4key, 16); - arcfour_encrypt(&mycontext, payload, payload, length); - arcfour_encrypt(&mycontext, payload + length, crc, 4); + GET_TKIP_PN(iv, dot11txpn); - } else { - length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; - *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/ - arcfour_init(&mycontext, rc4key, 16); - arcfour_encrypt(&mycontext, payload, payload, length); - arcfour_encrypt(&mycontext, payload + length, crc, 4); + pnl = (u16)(dot11txpn.val); + pnh = (u32)(dot11txpn.val >> 16); - pframe += pxmitpriv->frag_len; - pframe = (u8 *)RND4((SIZE_PTR)(pframe)); + phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh); + phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl); - } - } - - TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); - } - /* - else{ - RTW_INFO("%s, psta==NUL\n", __func__); - res=_FAIL; - } - */ + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); + arcfour_init(&mycontext, rc4key, 16); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); } - return res; -} + TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + return _SUCCESS; +} /* The hlen isn't include the IV */ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) @@ -860,7 +779,6 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) struct sta_info *stainfo; struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; - /* struct recv_priv *precvpriv=&padapter->recvpriv; */ u32 res = _SUCCESS; @@ -1586,16 +1504,15 @@ static sint aes_cipher(u8 *key, uint hdrlen, #endif /* (NEW_CRYPTO == 0) */ -#if NEW_CRYPTO -u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +u32 rtw_core_aes_encrypt(_adapter *padapter, u8 *pxmitframe) { - /* Intermediate Buffers */ - struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - sint curfragnum, plen; + struct xmit_frame *pxframe = (struct xmit_frame *)pxmitframe; + sint curfragnum; u32 prwskeylen; - u8 *pframe; + u8 *pwlanhdr, *payload; u8 *prwskey; u8 hw_hdr_offset = 0; @@ -1604,34 +1521,24 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) return _FAIL; -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + - (((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif - - pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; + pwlanhdr = pxframe->wlhdr[0]; + payload = pxframe->pkt->data + pxframe->attrib.pkt_hdrlen - RTW_SZ_LLC; /* start to encrypt each fragment */ - if ((pattrib->encrypt == _AES_) || - (pattrib->encrypt == _CCMP_256_)) { + if ((pxframe->attrib.encrypt == _AES_) || + (pxframe->attrib.encrypt == _CCMP_256_)) { - if (IS_MCAST(pattrib->ra)) + if (IS_MCAST(pxframe->attrib.ra)) prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; else { - prwskey = pattrib->dot118021x_UncstKey.skey; + prwskey = pxframe->attrib.psta->dot118021x_UncstKey.skey; } #ifdef CONFIG_TDLS { /* Swencryption */ struct sta_info *ptdls_sta; - ptdls_sta = rtw_get_stainfo(&padapter->stapriv, &pattrib->dst[0]); + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pxframe->attrib.dst); if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) { RTW_INFO("[%s] for tdls link\n", __FUNCTION__); prwskey = &ptdls_sta->tpk.tk[0]; @@ -1639,145 +1546,80 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) } #endif /* CONFIG_TDLS */ - prwskeylen = (pattrib->encrypt == _CCMP_256_) ? 32 : 16; - - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - - if ((curfragnum + 1) == pattrib->nr_frags) { /* the last fragment */ - plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + prwskeylen = (pxframe->attrib.encrypt == _CCMP_256_) ? 32 : 16; - _rtw_ccmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, pframe, plen); + for (curfragnum = 0; curfragnum < pxframe->attrib.nr_frags; curfragnum++) { + u8 *pdata = pxframe->pkt->data + pxframe->attrib.pkt_hdrlen - RTW_SZ_LLC + curfragnum*pxframe->attrib.frag_datalen; + + if ((curfragnum + 1) == pxframe->attrib.nr_frags) { /* the last fragment */ + u32 ls_datelen = pxframe->pkt->len - curfragnum*pxframe->attrib.frag_datalen; + _rtw_core_ccmp_encrypt(prwskey, prwskeylen, + pxframe->attrib.hdrlen, pxframe->wlhdr[curfragnum], ls_datelen, pdata); } else { - plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - - _rtw_ccmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, pframe, plen); - pframe += pxmitpriv->frag_len; - pframe = (u8 *)RND4((SIZE_PTR)(pframe)); - + _rtw_core_ccmp_encrypt(prwskey, prwskeylen, + pxframe->attrib.hdrlen, pxframe->wlhdr[curfragnum], pxframe->attrib.frag_datalen, pdata); } } - AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + AES_SW_ENC_CNT_INC(psecuritypriv, pxframe->attrib.ra); } - - return res; } -#else -u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) -{ - /* exclude ICV */ - - - /*static*/ - /* unsigned char message[MAX_MSG_SIZE]; */ - - /* Intermediate Buffers */ - sint curfragnum, length; - u32 prwskeylen; - u8 *pframe, *prwskey; /* , *payload,*iv */ - u8 hw_hdr_offset = 0; - /* struct sta_info *stainfo=NULL; */ - struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - - /* uint offset = 0; */ - u32 res = _SUCCESS; - - if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) - return _FAIL; - -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + - (((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; #endif -#endif - - pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; - - /* 4 start to encrypt each fragment */ - if ((pattrib->encrypt == _AES_)) { - /* - if(pattrib->psta) - { - stainfo = pattrib->psta; - } - else - { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); - } - */ - /* if (stainfo!=NULL) */ - { - /* - if(!(stainfo->state &WIFI_ASOC_STATE)) - { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state); - return _FAIL; - } - */ - - if (IS_MCAST(pattrib->ra)) - prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; - else { - /* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */ - prwskey = pattrib->dot118021x_UncstKey.skey; - } -#ifdef CONFIG_TDLS - { - /* Swencryption */ - struct sta_info *ptdls_sta; - ptdls_sta = rtw_get_stainfo(&padapter->stapriv , &pattrib->dst[0]); - if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) { - RTW_INFO("[%s] for tdls link\n", __FUNCTION__); - prwskey = &ptdls_sta->tpk.tk[0]; - } - } -#endif /* CONFIG_TDLS */ - - prwskeylen = 16; - - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - - if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */ - length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; +u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + struct xmit_frame *xf = (struct xmit_frame *)pxmitframe; + struct pkt_attrib *pattrib = &xf->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + sint curfragnum, plen; + u32 prwskeylen; + u8 *pframe; + u8 *prwskey; - aes_cipher(prwskey, pattrib->hdrlen, pframe, length); - } else { - length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; - aes_cipher(prwskey, pattrib->hdrlen, pframe, length); - pframe += pxmitpriv->frag_len; - pframe = (u8 *)RND4((SIZE_PTR)(pframe)); + if ((pattrib->encrypt != _AES_) && (pattrib->encrypt != _CCMP_256_)) + return _SUCCESS; - } - } + /* start to encrypt each fragment */ + if (IS_MCAST(pattrib->ra)) + prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + else + prwskey = pattrib->dot118021x_UncstKey.skey; - AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); +#ifdef CONFIG_TDLS + { + /* Swencryption */ + struct sta_info *ptdls_sta; + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, &pattrib->dst[0]); + if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) { + RTW_INFO("[%s] for tdls link\n", __FUNCTION__); + prwskey = &ptdls_sta->tpk.tk[0]; } - /* - else{ - RTW_INFO("%s, psta==NUL\n", __func__); - res=_FAIL; - } - */ } +#endif /* CONFIG_TDLS */ + prwskeylen = (pattrib->encrypt == _CCMP_256_) ? 32 : 16; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + txreq = &xf->phl_txreq[curfragnum]; + rtw_warn_on(txreq->pkt_cnt != 1); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pframe = pkt_list->vir_addr; + plen = pkt_list->length - pattrib->hdrlen + - pattrib->iv_len - pattrib->icv_len; + _rtw_ccmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, + pframe, plen); + } + AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); - return res; + return _SUCCESS; } -#endif #if (NEW_CRYPTO == 0) static sint aes_decipher(u8 *key, uint hdrlen, @@ -2150,7 +1992,6 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) struct sta_info *stainfo; struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; - /* struct recv_priv *precvpriv=&padapter->recvpriv; */ u32 res = _SUCCESS; pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; /* 4 start to encrypt each fragment */ @@ -2586,63 +2427,42 @@ u32 rtw_calc_crc32(u8 *data, size_t len) */ u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe) { - struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; + struct xmit_frame *xf = (struct xmit_frame *)pxmitframe; + struct pkt_attrib *pattrib = &xf->attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* Intermediate Buffers */ + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; sint curfragnum, plen; u32 prwskeylen; u8 *pframe = NULL; u8 *prwskey = NULL; u8 hw_hdr_offset = 0; - u32 res = _SUCCESS; - if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) - return _FAIL; -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + - (((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif - - pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; + if ((pattrib->encrypt != _GCMP_) && (pattrib->encrypt != _GCMP_256_)) + return _SUCCESS; /* start to encrypt each fragment */ - if ((pattrib->encrypt == _GCMP_) || - (pattrib->encrypt == _GCMP_256_)) { - - if (IS_MCAST(pattrib->ra)) - prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; - else - prwskey = pattrib->dot118021x_UncstKey.skey; - - prwskeylen = (pattrib->encrypt == _GCMP_256_) ? 32 : 16; - - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - if ((curfragnum + 1) == pattrib->nr_frags) { - /* the last fragment */ - plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - - _rtw_gcmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, pframe, plen); - } else { - plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - - _rtw_gcmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, pframe, plen); - pframe += pxmitpriv->frag_len; - pframe = (u8 *)RND4((SIZE_PTR)(pframe)); - } - } - - GCMP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + if (IS_MCAST(pattrib->ra)) + prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + else + prwskey = pattrib->dot118021x_UncstKey.skey; + prwskeylen = (pattrib->encrypt == _GCMP_256_) ? 32 : 16; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + txreq = &xf->phl_txreq[curfragnum]; + rtw_warn_on(txreq->pkt_cnt != 1); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pframe = pkt_list->vir_addr; + plen = pkt_list->length - pattrib->hdrlen + - pattrib->iv_len - pattrib->icv_len; + _rtw_gcmp_encrypt(padapter, prwskey, prwskeylen, pattrib->hdrlen, + pframe, plen); } - return res; + GCMP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + + return _SUCCESS; } u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe) @@ -2772,7 +2592,8 @@ u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len, u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, - u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn) + u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn, + u8 *precvframe) { u8 * BIP_AAD,*mme; u32 res = _FAIL; @@ -2782,6 +2603,7 @@ u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, struct rtw_ieee80211_hdr *pwlanhdr; u8 mic[16]; u8 mic_len, mme_offset; + struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; mic_len = (gmcs == _BIP_CMAC_128_) ? 8 : 16; @@ -2810,6 +2632,13 @@ u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, return _FAIL; } + /*HW decrtped case*/ + if (prxattrib->bdecrypted) { + /*Need to record IPN value */ + *ipn = pkt_ipn; + return _SUCCESS; + } + ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE; BIP_AAD = rtw_zmalloc(ori_len); if (BIP_AAD == NULL) { @@ -2831,7 +2660,7 @@ u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, ClearPwrMgt(BIP_AAD); ClearMData(BIP_AAD); /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, GetAddr1Ptr((u8 *)pwlanhdr), 18); + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); if (rtw_calculate_bip_mic(gmcs, whdr_pos, pkt_len, key, BIP_AAD, ori_len, mic) == _FAIL) @@ -2870,3 +2699,63 @@ u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, #endif /* CONFIG_IEEE80211W */ +u8 rtw_iv_to_pn(u8 *iv, u8 *pn, u8 *key_id, u32 enc_algo) +{ + /* iv and pn must be Little Endian format */ + switch (enc_algo) { + case _TKIP_: + *(pn) = *(iv + 2); + *(pn + 1) = *(iv); + break; + case _AES_: + case _GCMP_: + case _CCMP_256_: + case _GCMP_256_: + *(pn) = *(iv); + *(pn + 1) = *(iv + 1); + break; + default: + return _FAIL; + } + + *(pn + 2) = *(iv + 4); + *(pn + 3) = *(iv + 5); + *(pn + 4) = *(iv + 6); + *(pn + 5) = *(iv + 7); + + if (key_id) + *key_id = *(iv + 3) >> 6; + + return _SUCCESS; +} + +u8 rtw_pn_to_iv(u8 *pn, u8 *iv, u8 key_id, u32 enc_algo) +{ + /* iv and pn must be Little Endian format */ + switch (enc_algo) { + case _TKIP_: + *(iv) = *(pn + 1); + *(iv + 1) = (*(pn + 1) | 0x20) & 0x7F; + *(iv + 2) = *(pn); + break; + case _AES_: + case _GCMP_: + case _CCMP_256_: + case _GCMP_256_: + *(iv) = *(pn); + *(iv + 1) = *(pn + 1); + *(iv + 2) = 0; + break; + default: + return _FAIL; + } + + *(iv + 3) = BIT(5) | ((key_id & 0x3) << 6); + *(iv + 4) = *(pn + 2); + *(iv + 5) = *(pn + 3); + *(iv + 6) = *(pn + 4); + *(iv + 7) = *(pn + 5); + + return _SUCCESS; +} + diff --git a/core/rtw_sreset.c b/core/rtw_sreset.c index 21cc18b..fbe4765 100644 --- a/core/rtw_sreset.c +++ b/core/rtw_sreset.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -14,13 +14,13 @@ *****************************************************************************/ #include -#include #include void sreset_init_value(_adapter *padapter) { #if defined(DBG_CONFIG_ERROR_DETECT) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); struct sreset_priv *psrtpriv = &pHalData->srestpriv; _rtw_mutex_init(&psrtpriv->silentreset_mutex); @@ -33,7 +33,8 @@ void sreset_init_value(_adapter *padapter) void sreset_reset_value(_adapter *padapter) { #if defined(DBG_CONFIG_ERROR_DETECT) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); struct sreset_priv *psrtpriv = &pHalData->srestpriv; psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; @@ -45,14 +46,19 @@ void sreset_reset_value(_adapter *padapter) u8 sreset_get_wifi_status(_adapter *padapter) { #if defined(DBG_CONFIG_ERROR_DETECT) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); struct sreset_priv *psrtpriv = &pHalData->srestpriv; u8 status = WIFI_STATUS_SUCCESS; u32 val32 = 0; if (psrtpriv->silent_reset_inprogress == _TRUE) return status; + #if 0 /*GEORGIA_TODO_REDEFINE_IO*/ val32 = rtw_read32(padapter, REG_TXDMA_STATUS); + #else + val32 = rtw_hal_get_dma_statu(padapter); + #endif if (val32 == 0xeaeaeaea) psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST; else if (val32 != 0) { @@ -78,7 +84,8 @@ u8 sreset_get_wifi_status(_adapter *padapter) void sreset_set_wifi_error_status(_adapter *padapter, u32 status) { #if defined(DBG_CONFIG_ERROR_DETECT) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); pHalData->srestpriv.Wifi_Error_Status = status; #endif } @@ -86,7 +93,8 @@ void sreset_set_wifi_error_status(_adapter *padapter, u32 status) void sreset_set_trigger_point(_adapter *padapter, s32 tgp) { #if defined(DBG_CONFIG_ERROR_DETECT) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); pHalData->srestpriv.dbg_trigger_point = tgp; #endif } @@ -94,7 +102,8 @@ void sreset_set_trigger_point(_adapter *padapter, s32 tgp) bool sreset_inprogress(_adapter *padapter) { #if defined(DBG_CONFIG_ERROR_RESET) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(dvobj); return pHalData->srestpriv.silent_reset_inprogress; #else return _FALSE; @@ -108,20 +117,7 @@ void sreset_restore_security_station(_adapter *padapter) struct sta_info *psta; struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; - { - u8 val8; - - if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) { - val8 = 0xcc; -#ifdef CONFIG_WAPI_SUPPORT - } else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) { - /* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */ - val8 = 0x4c; -#endif - } else - val8 = 0xcf; - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); - } + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { @@ -142,7 +138,7 @@ void sreset_restore_network_station(_adapter *padapter) struct mlme_priv *mlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 doiqk = _FALSE; + u8 do_rfk = _FALSE; rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); @@ -166,15 +162,12 @@ void sreset_restore_network_station(_adapter *padapter) #endif } - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk); - - set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); - - doiqk = _FALSE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); - /* disable dynamic functions, such as high power, DIG */ - /*rtw_phydm_func_disable_all(padapter);*/ + do_rfk = _TRUE; + set_channel_bwmode(padapter, + pmlmeext->chandef.chan, + pmlmeext->chandef.offset, + pmlmeext->chandef.bw, + do_rfk); rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); @@ -183,13 +176,9 @@ void sreset_restore_network_station(_adapter *padapter) rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - rtw_btcoex_connect_notify(padapter, join_type); } - Set_MSR(padapter, (pmlmeinfo->state & 0x3)); - - mlmeext_joinbss_event_callback(padapter, 1); + rtw_set_hw_after_join(padapter, 1); /* restore Sequence No. */ rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0); @@ -201,17 +190,13 @@ void sreset_restore_network_status(_adapter *padapter) { struct mlme_priv *mlmepriv = &padapter->mlmepriv; - if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { + if (MLME_IS_STA(padapter)) { RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); sreset_restore_network_station(padapter); - } -#ifdef CONFIG_AP_MODE - else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH"); rtw_ap_restore_network(padapter); - } -#endif - else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) + } else if (MLME_IS_ADHOC(padapter)) RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); else RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); @@ -232,12 +217,12 @@ void sreset_stop_adapter(_adapter *padapter) rtw_cancel_all_timer(padapter); /* TODO: OS and HCI independent */ -#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) - tasklet_kill(&pxmitpriv->xmit_tasklet); +#if defined(CONFIG_USB_HCI) + rtw_tasklet_kill(&pxmitpriv->xmit_tasklet); #endif if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) - rtw_scan_abort(padapter); + rtw_scan_abort(padapter, 0); if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) { rtw_set_to_roam(padapter, 0); @@ -260,27 +245,27 @@ void sreset_start_adapter(_adapter *padapter) sreset_restore_network_status(padapter); /* TODO: OS and HCI independent */ -#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) - tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#if defined(CONFIG_USB_HCI) + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); #endif - + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ if (is_primary_adapter(padapter)) _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); - + #endif rtw_netif_wake_queue(padapter->pnetdev); } void sreset_reset(_adapter *padapter) { -#ifdef DBG_CONFIG_ERROR_RESET - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; +#ifdef DBG_CONFIG_ERROR_RESET struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _irqL irqL; systime start = rtw_get_current_time(); struct dvobj_priv *psdpriv = padapter->dvobj; + HAL_DATA_TYPE *pHalData = GET_PHL_COM(psdpriv); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; RTW_INFO("%s\n", __FUNCTION__); @@ -289,7 +274,7 @@ void sreset_reset(_adapter *padapter) #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET"); + rtw_set_ps_mode(padapter, PM_PS_MODE_ACTIVE, 0, 0, "SRESET"); #endif/* #ifdef CONFIG_LPS */ _enter_pwrlock(&pwrpriv->lock); @@ -302,7 +287,7 @@ void sreset_reset(_adapter *padapter) _ips_enter(padapter); _ips_leave(padapter); #endif -#if defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE) +#ifdef CONFIG_CONCURRENT_MODE rtw_mi_ap_info_restore(padapter); #endif rtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/ diff --git a/core/rtw_sta_mgt.c b/core/rtw_sta_mgt.c index 23d6b72..f8778f9 100644 --- a/core/rtw_sta_mgt.c +++ b/core/rtw_sta_mgt.c @@ -36,11 +36,10 @@ inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl) inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl) { - _irqL irqL; _list *plist, *phead; struct session_tracker *st; - _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinlock_bh(&st_ctl->tracker_q.lock); phead = &st_ctl->tracker_q.queue; plist = get_next(phead); while (rtw_end_of_queue_search(phead, plist) == _FALSE) { @@ -49,7 +48,7 @@ inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl) rtw_list_delete(&st->list); rtw_mfree((u8 *)st, sizeof(struct session_tracker)); } - _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinunlock_bh(&st_ctl->tracker_q.lock); } inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl) @@ -167,7 +166,6 @@ void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos) void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) { int i; - _irqL irqL; _list *plist, *phead; struct session_tracker *st; @@ -177,7 +175,7 @@ void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) RTW_PRINT_SEL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule); - _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinlock_bh(&st_ctl->tracker_q.lock); phead = &st_ctl->tracker_q.queue; plist = get_next(phead); while (rtw_end_of_queue_search(phead, plist) == _FALSE) { @@ -186,7 +184,7 @@ void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) RTW_PRINT_SEL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st)); } - _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + _rtw_spinunlock_bh(&st_ctl->tracker_q.lock); } @@ -203,9 +201,7 @@ void _rtw_init_stainfo(struct sta_info *psta) /* _rtw_init_listhead(&psta->wakeup_list); */ _rtw_init_queue(&psta->sleep_q); -#ifdef CONFIG_RTW_MGMT_QUEUE - _rtw_init_queue(&psta->mgmt_sleep_q); -#endif + _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); _rtw_init_sta_recv_priv(&psta->sta_recvpriv); @@ -214,6 +210,9 @@ void _rtw_init_stainfo(struct sta_info *psta) _rtw_init_listhead(&psta->auth_list); psta->bpairwise_key_installed = _FALSE; +#ifdef CONFIG_RTW_80211R_AP + rtw_ft_peer_info_init(psta); +#endif #ifdef CONFIG_RTW_80211R psta->ft_pairwise_key_installed = _FALSE; #endif @@ -225,7 +224,7 @@ void _rtw_init_stainfo(struct sta_info *psta) u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) { _adapter *adapter = container_of(pstapriv, _adapter, stapriv); - struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + /* struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); */ struct sta_info *psta; s32 i; u32 ret = _FAIL; @@ -267,7 +266,8 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */ #ifdef CONFIG_AP_MODE - pstapriv->max_aid = macid_ctl->num; + pstapriv->max_aid = rtw_phl_get_macid_max_num( + GET_PHL_INFO(adapter_to_dvobj(pstapriv->padapter))); pstapriv->rr_aid = 0; pstapriv->started_aid = 1; pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *)); @@ -305,17 +305,18 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) #endif pstapriv->max_num_sta = NUM_STA; +#endif + #if CONFIG_RTW_MACADDR_ACL for (i = 0; i < RTW_ACL_PERIOD_NUM; i++) rtw_macaddr_acl_init(adapter, i); #endif -#endif /* CONFIG_AP_MODE */ #if CONFIG_RTW_PRE_LINK_STA rtw_pre_link_sta_ctl_init(pstapriv); #endif -#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON) +#if defined(DBG_ROAMING_TEST) rtw_set_rx_chk_limit(adapter,1); #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) rtw_set_rx_chk_limit(adapter,4); @@ -369,9 +370,6 @@ void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); -#ifdef CONFIG_RTW_MGMT_QUEUE - _rtw_spinlock_free(&(psta_xmitpriv->mgmt_q.sta_pending.lock)); -#endif } static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) @@ -388,7 +386,7 @@ void rtw_mfree_stainfo(struct sta_info *psta); void rtw_mfree_stainfo(struct sta_info *psta) { - if (&(psta->lock) != NULL) + if (&psta->lock != NULL) _rtw_spinlock_free(&psta->lock); _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); @@ -401,12 +399,11 @@ void rtw_mfree_stainfo(struct sta_info *psta) void rtw_mfree_all_stainfo(struct sta_priv *pstapriv); void rtw_mfree_all_stainfo(struct sta_priv *pstapriv) { - _irqL irqL; _list *plist, *phead; struct sta_info *psta = NULL; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); phead = get_list_head(&pstapriv->free_sta_queue); plist = get_next(phead); @@ -418,7 +415,7 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv) rtw_mfree_stainfo(psta); } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); } @@ -443,16 +440,16 @@ void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv) u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) { - _irqL irqL; - _list *phead, *plist; - struct sta_info *psta = NULL; - struct recv_reorder_ctrl *preorder_ctrl; int index; if (pstapriv) { + #ifdef CONFIG_RECV_REORDERING_CTRL + _list *phead, *plist; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl; /* delete all reordering_ctrl_timer */ - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < NUM_STA; index++) { phead = &(pstapriv->sta_hash[index]); plist = get_next(phead); @@ -468,8 +465,9 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) } } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); /*===============================*/ + #endif rtw_mfree_sta_priv_lock(pstapriv); @@ -498,51 +496,63 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) return _SUCCESS; } - +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) { _adapter *padapter = preorder_ctrl->padapter; -#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) - rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl); -#endif + rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), rtw_reordering_ctrl_timeout_handler, preorder_ctrl); } +#endif /* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */ -struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) +static struct sta_info *_rtw_alloc_core_stainfo(struct sta_priv *pstapriv, + const u8 *hwaddr) { - _irqL irqL2; s32 index; _list *phash_list; - struct sta_info *psta; + struct sta_info *psta; _queue *pfree_sta_queue; struct recv_reorder_ctrl *preorder_ctrl; + struct rtw_wifi_role_t *phl_role = pstapriv->padapter->phl_role; int i = 0; u16 wRxSeqInitialValue = 0xffff; pfree_sta_queue = &pstapriv->free_sta_queue; - /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */ - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + /* _rtw_spinlock_bh(&(pfree_sta_queue->lock)); */ + _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) { - /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock));*/ + psta = NULL; } else { psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list); rtw_list_delete(&(psta->list)); - /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ + /* _rtw_spinunlock_bh(&(pfree_sta_queue->lock)); */ _rtw_init_stainfo(psta); psta->padapter = pstapriv->padapter; - _rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN); - - index = wifi_mac_hash(hwaddr); - + /* + for sta mode, due to self sta info & AP sta info are the same sta info + using self hash index for sta mode, or bmc sta will not found self sta + */ + switch (phl_role->type) { + case PHL_RTYPE_NONE: + case PHL_RTYPE_STATION: + case PHL_RTYPE_ADHOC: + case PHL_RTYPE_P2P_DEVICE: + case PHL_RTYPE_P2P_GC: + index = wifi_mac_hash(phl_role->mac_addr); + break; + default: + index = wifi_mac_hash(hwaddr); + break; + } if (index >= NUM_STA) { psta = NULL; @@ -550,13 +560,13 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) } phash_list = &(pstapriv->sta_hash[index]); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ rtw_list_insert_tail(&psta->hash_list, phash_list); pstapriv->asoc_sta_count++; - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ /* Commented by Albert 2009/08/13 * For the SMC router, the sequence number of first packet of WPS handshake will be 0. @@ -568,12 +578,10 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) _rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2); _rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i])); } - _rtw_memcpy(&psta->sta_recvpriv.nonqos_bmc_rxseq,&wRxSeqInitialValue,2); - _rtw_memcpy(&psta->sta_recvpriv.nonqos_rxseq,&wRxSeqInitialValue,2); - rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta); + rtw_init_timer(&psta->addba_retry_timer, addba_timer_hdl, psta); #ifdef CONFIG_IEEE80211W - rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta); + rtw_init_timer(&psta->dot11w_expire_timer, sa_query_timer_hdl, psta); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_TDLS rtw_init_tdls_timer(pstapriv->padapter, psta); @@ -590,22 +598,26 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n" , FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq); #endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* 64; */ + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + #ifdef CONFIG_RECV_REORDERING_CTRL + /* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */ + preorder_ctrl->wsize_b = 64;/* 64; */ _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue); rtw_init_recv_timer(preorder_ctrl); + #endif rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack); } ATOMIC_SET(&psta->keytrack, 0); - - /* init for DM */ - psta->cmn.rssi_stat.rssi = (-1); - psta->cmn.rssi_stat.rssi_cck = (-1); - psta->cmn.rssi_stat.rssi_ofdm = (-1); + /* ToDo: need to API to init hal_sta->ra_info->rssi_stat.rssi */ + #if 0 + psta->phl_sta->rssi_stat.rssi = (-1); + psta->phl_sta->rssi_stat.rssi_cck = (-1); + psta->phl_sta->rssi_stat.rssi_ofdm = (-1); + #endif #ifdef CONFIG_ATMEL_RC_PATCH psta->flag_atmel_rc = 0; #endif @@ -617,8 +629,6 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) psta->RxMgmtFrameSeqNum = 0xffff; _rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats)); - rtw_alloc_macid(pstapriv->padapter, psta); - psta->tx_q_enable = 0; _rtw_init_queue(&psta->tx_queue); _init_workitem(&psta->tx_q_work, rtw_xmit_dequeue_callback, NULL); @@ -626,7 +636,7 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) exit: - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); if (psta) @@ -635,13 +645,89 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) return psta; } +static void _rtw_alloc_phl_stainfo(struct sta_info *sta, struct sta_priv *stapriv, const u8 *hwaddr) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + void *phl = GET_PHL_INFO(adapter_to_dvobj(stapriv->padapter)); + struct rtw_wifi_role_t *wrole = stapriv->padapter->phl_role; + bool alloc = _TRUE, only_hw = _FALSE; + + if (sta != NULL) { + /* Do not use this function in interrupt context */ + pstatus = rtw_phl_cmd_alloc_stainfo(phl, &sta->phl_sta, + (u8 *)hwaddr, wrole, + alloc, only_hw, + PHL_CMD_DIRECTLY, 0); + + if (sta->phl_sta) { + rtw_dump_phl_sta_info(RTW_DBGDUMP, sta); + } else { + RTW_ERR(FUNC_ADPT_FMT ": fail to alloc PHL sta " + "for " MAC_FMT " (status=%d)!\n", + FUNC_ADPT_ARG(stapriv->padapter), + MAC_ARG(hwaddr), + pstatus); + } + } +} + +struct sta_info *rtw_alloc_stainfo(struct sta_priv *stapriv, const u8 *hwaddr) +{ + struct sta_info *sta; + /* can use in interrupt context */ + sta = _rtw_alloc_core_stainfo(stapriv, hwaddr); + + /* can not use in interrupt context */ + _rtw_alloc_phl_stainfo(sta, stapriv, hwaddr); + + return sta; +} + +struct sta_info *rtw_alloc_stainfo_sw(struct sta_priv *stapriv, const u8 *hwaddr) +{ + struct sta_info *sta; + /* can use in interrupt context */ + sta = _rtw_alloc_core_stainfo(stapriv, hwaddr); + + if (sta != NULL) { + sta->phl_sta = rtw_phl_alloc_stainfo_sw( + GET_PHL_INFO(adapter_to_dvobj(stapriv->padapter)), + (u8 *)hwaddr, stapriv->padapter->phl_role); + + if (sta->phl_sta) { + rtw_dump_phl_sta_info(RTW_DBGDUMP, sta); + } else { + RTW_ERR(FUNC_ADPT_FMT ": fail to alloc PHL sta " + "for " MAC_FMT " !\n", + FUNC_ADPT_ARG(stapriv->padapter), + MAC_ARG(hwaddr)); + } + } + + return sta; +} + +u32 rtw_alloc_stainfo_hw(struct sta_priv *stapriv, struct sta_info *psta) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void *phl = GET_PHL_INFO(adapter_to_dvobj(stapriv->padapter)); + struct rtw_wifi_role_t *wrole = stapriv->padapter->phl_role; + bool alloc = _TRUE, only_hw = _TRUE; + + if ((psta != NULL) && (psta->phl_sta != NULL) && (psta->phl_sta->active == _FALSE)) + status = rtw_phl_cmd_alloc_stainfo(phl, &psta->phl_sta, + (u8 *)psta->phl_sta->mac_addr, + wrole, alloc, only_hw, + PHL_CMD_DIRECTLY, 0); + + return (status == RTW_PHL_STATUS_SUCCESS) ? _SUCCESS : _FAIL; +} /* using pstapriv->sta_hash_lock to protect */ -u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) +u32 static _rtw_free_core_stainfo(_adapter *padapter , struct sta_info *psta) { int i; - _irqL irqL0; - _queue *pfree_sta_queue, *pdefrag_q = NULL; + _queue *pfree_sta_queue; struct recv_reorder_ctrl *preorder_ctrl; struct sta_xmit_priv *pstaxmitpriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -649,36 +735,52 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) struct hw_xmit *phwxmit; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int pending_qcnt[4]; u8 is_pre_link_sta = _FALSE; - _list *phead, *plist; - _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; - union recv_frame *prframe; if (psta == NULL) goto exit; -#ifdef CONFIG_RTW_80211K - rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel); +#if defined(CONFIG_CORE_TXSC) && defined(USE_ONE_WLHDR) + /* free shortcut entry wlhdr buffer */ + for (i = 0; i < CORE_TXSC_ENTRY_NUM; i++) { + if (psta->txsc_entry_cache[i].txsc_wlhdr) { + rtw_mfree(psta->txsc_entry_cache[i].txsc_wlhdr, CORE_TXSC_WLHDR_SIZE); + psta->txsc_entry_cache[i].txsc_wlhdr = NULL; + } + } #endif - is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr); +#ifdef CONFIG_RTW_80211K + rm_post_event(padapter, RM_ID_FOR_ALL(psta->phl_sta->aid), RM_EV_cancel); +#endif + #if CONFIG_RTW_PRE_LINK_STA + is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->phl_sta->mac_addr); if (is_pre_link_sta == _FALSE) { - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); rtw_list_delete(&psta->hash_list); pstapriv->asoc_sta_count--; - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); rtw_mi_update_iface_status(&(padapter->mlmepriv), 0); } else { - _enter_critical_bh(&psta->lock, &irqL0); + _rtw_spinlock_bh(&psta->lock); psta->state = WIFI_FW_PRE_LINK; - _exit_critical_bh(&psta->lock, &irqL0); + _rtw_spinunlock_bh(&psta->lock); } + #else + _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); + rtw_list_delete(&psta->hash_list); + pstapriv->asoc_sta_count--; + _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); + rtw_mi_update_iface_status(&(padapter->mlmepriv), 0); - _enter_critical_bh(&psta->lock, &irqL0); + #endif + + _rtw_spinlock_bh(&psta->lock); psta->state &= ~WIFI_ASOC_STATE; - _exit_critical_bh(&psta->lock, &irqL0); + _rtw_spinunlock_bh(&psta->lock); pfree_sta_queue = &pstapriv->free_sta_queue; @@ -692,68 +794,54 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) rtw_free_xmitframe_queue(pxmitpriv, &psta->tx_queue); _rtw_deinit_queue(&psta->tx_queue); - _enter_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinlock_bh(&pxmitpriv->lock); rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); psta->sleepq_len = 0; -#ifdef CONFIG_RTW_MGMT_QUEUE - rtw_free_mgmt_xmitframe_queue(pxmitpriv, &psta->mgmt_sleep_q); - psta->mgmt_sleepq_len = 0; -#endif - /* vo */ - /* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */ + /* _rtw_spinlock_bh(&(pxmitpriv->vo_pending.lock)); */ rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); phwxmit = pxmitpriv->hwxmits; phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt; pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt; pstaxmitpriv->vo_q.qcnt = 0; - /* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */ + /* _rtw_spinunlock_bh(&(pxmitpriv->vo_pending.lock)); */ /* vi */ - /* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */ + /* _rtw_spinlock_bh(&(pxmitpriv->vi_pending.lock)); */ rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); phwxmit = pxmitpriv->hwxmits + 1; phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt; pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt; pstaxmitpriv->vi_q.qcnt = 0; - /* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */ + /* _rtw_spinunlock_bh(&(pxmitpriv->vi_pending.lock)); */ /* be */ - /* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */ + /* _rtw_spinlock_bh(&(pxmitpriv->be_pending.lock)); */ rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); phwxmit = pxmitpriv->hwxmits + 2; phwxmit->accnt -= pstaxmitpriv->be_q.qcnt; pending_qcnt[2] = pstaxmitpriv->be_q.qcnt; pstaxmitpriv->be_q.qcnt = 0; - /* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */ + /* _rtw_spinunlock_bh(&(pxmitpriv->be_pending.lock)); */ /* bk */ - /* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */ + /* _rtw_spinlock_bh(&(pxmitpriv->bk_pending.lock)); */ rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); phwxmit = pxmitpriv->hwxmits + 3; phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt; pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt; pstaxmitpriv->bk_q.qcnt = 0; - /* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */ - -#ifdef CONFIG_RTW_MGMT_QUEUE - /* mgmt */ - rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->mgmt_q.sta_pending); - rtw_list_delete(&(pstaxmitpriv->mgmt_q.tx_pending)); - phwxmit = pxmitpriv->hwxmits + 4; - phwxmit->accnt -= pstaxmitpriv->mgmt_q.qcnt; - pstaxmitpriv->mgmt_q.qcnt = 0; -#endif + /* _rtw_spinunlock_bh(&(pxmitpriv->bk_pending.lock)); */ rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt); - _exit_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinunlock_bh(&pxmitpriv->lock); /* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */ @@ -770,18 +858,19 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) /* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */ for (i = 0; i < 16 ; i++) { - _irqL irqL; - _queue *ppending_recvframe_queue; - preorder_ctrl = &psta->recvreorder_ctrl[i]; rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack); - _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); +#ifdef CONFIG_RECV_REORDERING_CTRL + _list *phead, *plist; + union recv_frame *prframe; + _queue *ppending_recvframe_queue; + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; - _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL); + _rtw_spinlock_bh(&ppending_recvframe_queue->lock); phead = get_list_head(ppending_recvframe_queue); plist = get_next(phead); @@ -793,48 +882,44 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) rtw_list_delete(&(prframe->u.hdr.list)); - rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe(prframe); } - _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL); - + _rtw_spinunlock_bh(&ppending_recvframe_queue->lock); +#endif /*CONFIG_RECV_REORDERING_CTRL*/ } /* CVE-2020-24586, clear defrag queue */ - pdefrag_q = &psta->sta_recvpriv.defrag_q; - enter_critical_bh(&pdefrag_q->lock); - phead = get_list_head(pdefrag_q); - plist = get_next(phead); - while (!rtw_is_list_empty(phead)) { - prframe = LIST_CONTAINOR(plist, union recv_frame, u); - plist = get_next(plist); - rtw_list_delete(&(prframe->u.hdr.list)); - rtw_free_recvframe(prframe, pfree_recv_queue); - } - exit_critical_bh(&pdefrag_q->lock); - + { + _list *phead, *plist; + _queue *pfree_sta_queue, *pdefrag_q = &psta->sta_recvpriv.defrag_q; + union recv_frame *prframe; - if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE) - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); - - - /* release mac id for non-bc/mc station, */ - if (is_pre_link_sta == _FALSE) - rtw_release_macid(pstapriv->padapter, psta); + _rtw_spinlock_bh(&pdefrag_q->lock); + phead = get_list_head(pdefrag_q); + plist = get_next(phead); + while (!rtw_is_list_empty(phead)) { + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + plist = get_next(plist); + rtw_list_delete(&(prframe->u.hdr.list)); + rtw_free_recvframe(prframe); + } + _rtw_spinunlock_bh(&pdefrag_q->lock); + } #ifdef CONFIG_AP_MODE /* - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); rtw_list_delete(&psta->asoc_list); - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); */ - _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0); + _rtw_spinlock_bh(&pstapriv->auth_list_lock); if (!rtw_is_list_empty(&psta->auth_list)) { rtw_list_delete(&psta->auth_list); pstapriv->auth_list_cnt--; } - _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0); + _rtw_spinunlock_bh(&pstapriv->auth_list_lock); psta->expire_to = 0; #ifdef CONFIG_ATMEL_RC_PATCH @@ -854,14 +939,14 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) #ifdef CONFIG_NATIVEAP_MLME if (pmlmeinfo->state == _HW_STATE_AP_) { - rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->phl_sta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); /* rtw_indicate_sta_disassoc_event(padapter, psta); */ - if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) { - pstapriv->sta_aid[psta->cmn.aid - 1] = NULL; - psta->cmn.aid = 0; + if ((psta->phl_sta->aid > 0) && (pstapriv->sta_aid[psta->phl_sta->aid - 1] == psta)) { + pstapriv->sta_aid[psta->phl_sta->aid - 1] = NULL; + psta->phl_sta->aid = 0; } } @@ -871,6 +956,9 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) psta->under_exist_checking = 0; #endif +#ifdef CONFIG_RTW_80211R_AP + rtw_ft_peer_info_free(psta); +#endif #endif /* CONFIG_AP_MODE */ rtw_st_ctl_deinit(&psta->st_ctl); @@ -878,21 +966,64 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) if (is_pre_link_sta == _FALSE) { _rtw_spinlock_free(&psta->lock); - /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + /* _rtw_spinlock_bh(&(pfree_sta_queue->lock)); */ + _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); - /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); + /* _rtw_spinunlock_bh(&(pfree_sta_queue->lock)); */ } exit: return _SUCCESS; } +static void _rtw_free_phl_stainfo(_adapter *adapter, struct sta_info *sta, u8 only_free_sw) +{ + void *phl = GET_PHL_INFO(adapter_to_dvobj(adapter)); + enum rtw_phl_status pstaus = RTW_PHL_STATUS_SUCCESS; + u8 hwaddr[ETH_ALEN] = {0}; + bool alloc = _FALSE, only_hw = _FALSE; + + if (sta != NULL) { + _rtw_memcpy(hwaddr, sta->phl_sta->mac_addr, ETH_ALEN); + if (only_free_sw) + pstaus = rtw_phl_free_stainfo_sw(phl, sta->phl_sta); + else + pstaus = rtw_phl_cmd_alloc_stainfo(phl, &sta->phl_sta, + sta->phl_sta->mac_addr, + adapter->phl_role, + alloc, only_hw, + PHL_CMD_DIRECTLY, 0); + + if (pstaus != RTW_PHL_STATUS_SUCCESS) + RTW_ERR(FUNC_ADPT_FMT ": fail to free PHL sta " + "for " MAC_FMT " (status=%d)!\n", + FUNC_ADPT_ARG(adapter), + MAC_ARG(hwaddr), + pstaus); + else + /* free stainfo success, set pointer to NULL */ + sta->phl_sta = NULL; + } +} + +u32 rtw_free_stainfo(_adapter *padapter, struct sta_info *psta) +{ + _rtw_free_core_stainfo(padapter, psta); + _rtw_free_phl_stainfo(padapter, psta, _FALSE); + return _SUCCESS; +} + +u32 rtw_free_stainfo_sw(_adapter *padapter, struct sta_info *psta) +{ + _rtw_free_core_stainfo(padapter, psta); + _rtw_free_phl_stainfo(padapter, psta, _TRUE); + return _SUCCESS; +} + /* free all stainfo which in sta_hash[all] */ void rtw_free_all_stainfo(_adapter *padapter) { - _irqL irqL; _list *plist, *phead; s32 index; struct sta_info *psta = NULL; @@ -906,7 +1037,7 @@ void rtw_free_all_stainfo(_adapter *padapter) if (pstapriv->asoc_sta_count == 1) goto exit; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < NUM_STA; index++) { phead = &(pstapriv->sta_hash[index]); @@ -918,7 +1049,9 @@ void rtw_free_all_stainfo(_adapter *padapter) plist = get_next(plist); if (pbcmc_stainfo != psta) { - if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE) + #if CONFIG_RTW_PRE_LINK_STA + if (rtw_is_pre_link_sta(pstapriv, psta->phl_sta->mac_addr) == _FALSE) + #endif rtw_list_delete(&psta->hash_list); stainfo_offset = rtw_stainfo_offset(pstapriv, psta); @@ -929,7 +1062,7 @@ void rtw_free_all_stainfo(_adapter *padapter) } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < free_sta_num; index++) { @@ -944,31 +1077,59 @@ void rtw_free_all_stainfo(_adapter *padapter) /* any station allocated can be searched by hash list */ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) { - - _irqL irqL; - _list *plist, *phead; - struct sta_info *psta = NULL; + struct rtw_phl_stainfo_t *phl_sta_self = NULL; + void *phl = GET_PHL_INFO(adapter_to_dvobj(pstapriv->padapter)); + struct rtw_wifi_role_t *phl_role; + u32 index; - u32 index; + if (hwaddr == NULL) + return NULL; - const u8 *addr; + if (pstapriv->padapter->phl_role == NULL) { + RTW_ERR(FUNC_ADPT_FMT" phl_role == NULL\n", FUNC_ADPT_ARG(pstapriv->padapter)); + rtw_warn_on(1); + return NULL; + } + phl_role = pstapriv->padapter->phl_role; - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + /* if addr is bcmc addr, return self phl_sta */ + if (IS_MCAST(hwaddr)) { + phl_sta_self = rtw_phl_get_stainfo_self(phl, phl_role); + if (phl_sta_self == NULL) { + RTW_INFO("%s: get phl sta self fail", __func__); + return NULL; + } - if (hwaddr == NULL) - return NULL; + /* + due to using self sta to replace bcmc sta + change index to self hash index + */ - if (IS_MCAST(hwaddr)) - addr = bc_addr; - else - addr = hwaddr; + index = wifi_mac_hash(phl_role->mac_addr); + } else { - index = wifi_mac_hash(addr); + /* + for sta mode due to self sta info & AP sta info are the same sta info + using self hash index for sta mode, or bmc sta will not found self sta + */ + switch (phl_role->type) { + case PHL_RTYPE_NONE: + case PHL_RTYPE_STATION: + case PHL_RTYPE_ADHOC: + case PHL_RTYPE_P2P_DEVICE: + case PHL_RTYPE_P2P_GC: + index = wifi_mac_hash(phl_role->mac_addr); + break; + default: + index = wifi_mac_hash(hwaddr); + break; + } + } - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); phead = &(pstapriv->sta_hash[index]); plist = get_next(phead); @@ -978,54 +1139,67 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) { + if (psta->phl_sta == NULL) { + psta = NULL; + RTW_ERR("phl_sta of sta is NULL\n"); + plist = get_next(plist); + continue; + } + + /* if add is bcmc addr, find matched self phl_sta, and return */ + if (IS_MCAST(hwaddr) && psta->phl_sta == phl_sta_self) + break; + + /* if add is not bcmc addr, compare mac_addr */ + if ((_rtw_memcmp(psta->phl_sta->mac_addr, hwaddr, ETH_ALEN)) == _TRUE) { /* if found the matched address */ break; } + psta = NULL; plist = get_next(plist); } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); return psta; } -u32 rtw_init_bcmc_stainfo(_adapter *padapter) +u32 rtw_free_self_stainfo(_adapter *adapter) { + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; - struct sta_info *psta; - struct tx_servq *ptxservq; - u32 res = _SUCCESS; - NDIS_802_11_MAC_ADDRESS bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - struct sta_priv *pstapriv = &padapter->stapriv; - - - psta = rtw_alloc_stainfo(pstapriv, bcast_addr); + sta = rtw_get_stainfo(stapriv, adapter->phl_role->mac_addr); - if (psta == NULL) { - res = _FAIL; - goto exit; + if (sta != NULL) { + _rtw_free_core_stainfo(adapter, sta); + _rtw_free_phl_stainfo(adapter, sta, _FALSE); } -#ifdef CONFIG_BEAMFORMING - psta->cmn.bf_info.g_id = 63; - psta->cmn.bf_info.p_aid = 0; -#endif - ptxservq = &(psta->sta_xmitpriv.be_q); + return _SUCCESS; +} - /* - _enter_critical(&pstapending->lock, &irqL0); +u32 rtw_init_self_stainfo(_adapter *padapter) +{ - if (rtw_is_list_empty(&ptxservq->tx_pending)) - rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending)); + struct sta_info *psta; + struct tx_servq *ptxservq; + u32 res = _SUCCESS; + struct sta_priv *pstapriv = &padapter->stapriv; - _exit_critical(&pstapending->lock, &irqL0); - */ + psta = rtw_get_stainfo(pstapriv, padapter->phl_role->mac_addr); + if (psta == NULL) { + psta = rtw_alloc_stainfo(pstapriv, padapter->phl_role->mac_addr); + if (psta == NULL) { + RTW_ERR("%s alloc self sta fail\n", __func__); + res = _FAIL; + goto exit; + } + } exit: - return _SUCCESS; + return res; } @@ -1058,7 +1232,7 @@ u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta) if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta) aid = 0; - sta->cmn.aid = aid; + sta->phl_sta->aid = aid; if (aid) { stapriv->sta_aid[aid - 1] = sta; if (stapriv->rr_aid) @@ -1111,7 +1285,6 @@ const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = { u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr) { u8 res = _TRUE; - _irqL irqL; _list *list, *head; struct rtw_wlan_acl_node *acl_node; u8 match = _FALSE; @@ -1131,7 +1304,7 @@ u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr) && acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED) goto exit; - _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinlock_bh(&(acl_node_q->lock)); head = get_list_head(acl_node_q); list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { @@ -1145,7 +1318,7 @@ u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr) } } } - _exit_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_spinunlock_bh(&(acl_node_q->lock)); if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED) res = (match == _TRUE) ? _FALSE : _TRUE; @@ -1189,16 +1362,15 @@ void dump_macaddr_acl(void *sel, _adapter *adapter) } #endif /* CONFIG_RTW_MACADDR_ACL */ +#if CONFIG_RTW_PRE_LINK_STA bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr) { -#if CONFIG_RTW_PRE_LINK_STA struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; struct sta_info *sta = NULL; u8 exist = _FALSE; int i; - _irqL irqL; - _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinlock_bh(&(pre_link_sta_ctl->lock)); for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { if (pre_link_sta_ctl->node[i].valid == _TRUE && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE @@ -1207,13 +1379,11 @@ bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr) break; } } - _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(pre_link_sta_ctl->lock)); return exist; -#else - return _FALSE; -#endif } +#endif #if CONFIG_RTW_PRE_LINK_STA struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr) @@ -1223,12 +1393,11 @@ struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr) struct sta_info *sta = NULL; u8 exist = _FALSE; int i; - _irqL irqL; if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE) goto exit; - _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinlock_bh(&(pre_link_sta_ctl->lock)); for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { if (pre_link_sta_ctl->node[i].valid == _TRUE && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE @@ -1247,24 +1416,17 @@ struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr) node->valid = _TRUE; pre_link_sta_ctl->num++; } - _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(pre_link_sta_ctl->lock)); if (node == NULL) goto exit; - sta = rtw_get_stainfo(stapriv, hwaddr); - if (sta) - goto odm_hook; - sta = rtw_alloc_stainfo(stapriv, hwaddr); if (!sta) goto exit; sta->state = WIFI_FW_PRE_LINK; -odm_hook: - rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE); - exit: return sta; } @@ -1276,12 +1438,11 @@ void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr) struct sta_info *sta = NULL; u8 exist = _FALSE; int i; - _irqL irqL; if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE) goto exit; - _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinlock_bh(&(pre_link_sta_ctl->lock)); for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { if (pre_link_sta_ctl->node[i].valid == _TRUE && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE @@ -1296,7 +1457,7 @@ void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr) node->valid = _FALSE; pre_link_sta_ctl->num--; } - _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(pre_link_sta_ctl->lock)); if (exist == _FALSE) goto exit; @@ -1318,13 +1479,12 @@ void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv) struct pre_link_sta_node_t *node = NULL; struct sta_info *sta = NULL; int i, j = 0; - _irqL irqL; u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN]; _rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN); - _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinlock_bh(&(pre_link_sta_ctl->lock)); for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { if (pre_link_sta_ctl->node[i].valid == _FALSE) continue; @@ -1333,7 +1493,7 @@ void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv) pre_link_sta_ctl->num--; j++; } - _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(pre_link_sta_ctl->lock)); for (i = 0; i < j; i++) { sta = rtw_get_stainfo(stapriv, &(addrs[i][0])); diff --git a/core/rtw_swcrypto.c b/core/rtw_swcrypto.c index 2f1c343..1285aae 100644 --- a/core/rtw_swcrypto.c +++ b/core/rtw_swcrypto.c @@ -13,13 +13,36 @@ * *****************************************************************************/ #include -#include #include #include #include #include #include +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +int _rtw_core_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata) +{ + u8 *enc = NULL; + size_t enc_len = 0; + + if (key_len == 16) { /* 128 bits */ + core_ccmp_encrypt(key, + hdrlen, phdr, + datalen, pdata, + (hdrlen == 26) ? (phdr + hdrlen - 2) : NULL, + NULL, 0, &enc_len); + } else if (key_len == 32) { /* 256 bits */ + core_ccmp_256_encrypt(key, + hdrlen, phdr, + datalen, pdata, + (hdrlen == 26) ? (phdr + hdrlen - 2) : NULL, + NULL, 0, &enc_len); + } + + return _SUCCESS; +} +#endif + /** * rtw_ccmp_encrypt - * @key: the temporal key @@ -281,11 +304,11 @@ void _tdls_generate_tpk(void *sta, const u8 *own_addr, const u8 *bssid) * min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID) */ - if (_rtw_memcmp2(own_addr, psta->cmn.mac_addr, ETH_ALEN) < 0) { + if (_rtw_memcmp2(own_addr, psta->phl_sta->mac_addr, ETH_ALEN) < 0) { _rtw_memcpy(data, own_addr, ETH_ALEN); - _rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(data + ETH_ALEN, psta->phl_sta->mac_addr, ETH_ALEN); } else { - _rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(data, psta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(data + ETH_ALEN, own_addr, ETH_ALEN); } diff --git a/core/rtw_tdls.c b/core/rtw_tdls.c index d557234..845eeab 100644 --- a/core/rtw_tdls.c +++ b/core/rtw_tdls.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_TDLS_C_ #include -#include #ifdef CONFIG_TDLS #define ONE_SEC 1000 /* 1000 ms */ @@ -49,7 +48,7 @@ void rtw_reset_tdls_info(_adapter *padapter) ptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE; ATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE); ptdlsinfo->chsw_info.off_ch_num = 0; - ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + ptdlsinfo->chsw_info.ch_offset = CHAN_OFFSET_NO_EXT; ptdlsinfo->chsw_info.cur_time = 0; ptdlsinfo->chsw_info.delay_switch_back = _FALSE; ptdlsinfo->chsw_info.dump_stack = _FALSE; @@ -99,7 +98,6 @@ void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) { struct sta_priv *pstapriv = &padapter->stapriv; struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - _irqL irqL; _list *plist, *phead; s32 index; struct sta_info *psta = NULL; @@ -108,7 +106,7 @@ void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) _rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta)); - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < NUM_STA; index++) { phead = &(pstapriv->sta_hash[index]); plist = get_next(phead); @@ -122,7 +120,7 @@ void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) ptdls_sta[index] = psta; } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); for (index = 0; index < NUM_STA; index++) { if (ptdls_sta[index]) { @@ -130,16 +128,16 @@ void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) psta = ptdls_sta[index]; - RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd); + RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->phl_sta->mac_addr), enqueue_cmd); - _rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(&(tdls_param.addr), psta->phl_sta->mac_addr, ETH_ALEN); tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT; tdls_hdl(padapter, (unsigned char *)&(tdls_param)); rtw_tdls_teardown_pre_hdl(padapter, psta); if (enqueue_cmd == _TRUE) - rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, psta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); else { tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST; @@ -192,15 +190,6 @@ void rtw_enable_tdls_func(_adapter *padapter) { if (rtw_is_tdls_enabled(padapter) == _TRUE) return; - -#if 0 -#ifdef CONFIG_MCC_MODE - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) { - RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n"); - return; - } -#endif -#endif rtw_set_tdls_enable(padapter, _TRUE); } @@ -221,14 +210,13 @@ u8 rtw_is_tdls_sta_existed(_adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; int i = 0; - _irqL irqL; _list *plist, *phead; u8 ret = _FALSE; if (rtw_is_tdls_enabled(padapter) == _FALSE) return _FALSE; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); for (i = 0; i < NUM_STA; i++) { phead = &(pstapriv->sta_hash[i]); @@ -245,7 +233,7 @@ u8 rtw_is_tdls_sta_existed(_adapter *padapter) Exit: - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); return ret; } @@ -365,9 +353,9 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig psta = rtw_get_stainfo(&padapter->stapriv, da); if (psta) { if (power_mode) - rtw_hal_macid_sleep(padapter, psta->cmn.mac_id); + rtw_hal_macid_sleep(padapter, psta->phl_sta->macid); else - rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); + rtw_hal_macid_wakeup(padapter, psta->phl_sta->macid); } else { RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); @@ -380,7 +368,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig i++; - if (RTW_CANNOT_RUN(padapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) break; if (i < try_cnt && wait_ms > 0 && ret == _FAIL) @@ -477,9 +465,9 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 /* Bwmode would still followed AP's setting */ if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) { - if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40) - ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40; - ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset; + if (padapter->mlmeextpriv.chandef.bw >= CHANNEL_WIDTH_40) + ptdls_sta->phl_sta->chandef.bw = CHANNEL_WIDTH_40; + ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.chandef.offset; } /* Config LDPC Coding Capability */ @@ -522,7 +510,7 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr padapter->mlmepriv.htpriv.sgi_40m = _FALSE; } - rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel); + rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.chandef.chan, NULL); return pframe + pattrib->pktlen; } @@ -560,9 +548,13 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 if (ptdls_sta->flags & WLAN_STA_VHT) { if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) && is_supported_vht(padapter->registrypriv.wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) { + && RFCTL_REG_EN_11AC(rfctl) + ) { ptdls_sta->vhtpriv.vht_option = _TRUE; - ptdls_sta->cmn.ra_info.is_vht_enable = _TRUE; + /* ToDo: need to API to inform hal_sta->ra_info.is_vht_enable */ + #if 0 + ptdls_sta->phl_sta->ra_info.is_vht_enable = _TRUE; + #endif } else ptdls_sta->vhtpriv.vht_option = _FALSE; @@ -598,7 +590,10 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 GET_VHT_CAPABILITY_ELE_SU_BFER(data)) SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap; - ptdls_sta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap; + /* ToDo: need to API to inform hal_sta->bf_info.vht_beamform_cap */ + #if 0 + ptdls_sta->phl_sta->bf_info.vht_beamform_cap = cur_beamform_cap; + #endif if (cur_beamform_cap) RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); #endif /*CONFIG_BEAMFORMING*/ @@ -607,7 +602,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data); pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data); - tx_nss = GET_HAL_TX_NSS(padapter); + tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs); ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map); } @@ -623,13 +618,13 @@ void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_s operation_bw = CHANNEL_WIDTH_80; - if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw) - && (operation_bw <= pmlmeext->cur_bwmode)) - ptdls_sta->cmn.bw_mode = operation_bw; + if (rtw_hw_is_bw_support(adapter_to_dvobj(padapter), operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw) + && (operation_bw <= pmlmeext->chandef.bw)) + ptdls_sta->phl_sta->chandef.bw = operation_bw; else - ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + ptdls_sta->phl_sta->chandef.bw = pmlmeext->chandef.bw; } else - ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + ptdls_sta->phl_sta->chandef.bw = pmlmeext->chandef.bw; } void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) @@ -647,11 +642,11 @@ void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *pt target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data); target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1); - if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) - && (target_bw <= pmlmeext->cur_bwmode)) - ptdls_sta->cmn.bw_mode = target_bw; + if (rtw_hw_is_bw_support(adapter_to_dvobj(padapter), target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) + && (target_bw <= pmlmeext->chandef.bw)) + ptdls_sta->phl_sta->chandef.bw = target_bw; else - ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + ptdls_sta->phl_sta->chandef.bw = pmlmeext->chandef.bw; current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map); if (target_rxss != current_rxss) { @@ -671,7 +666,7 @@ u8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *patt { u32 ie_len = 0; - rtw_vht_use_default_setting(padapter); + rtw_vht_get_real_setting(padapter); ie_len = rtw_build_vht_cap_ie(padapter, pframe); pattrib->pktlen += ie_len; @@ -739,7 +734,7 @@ u8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attri u8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib) { - return rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen)); + return rtw_set_ie(pframe, WLAN_EID_EXT_CAP , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen)); } u8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib) @@ -863,7 +858,9 @@ u8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attri int bssrate_len = 0; u8 more_supportedrates = 0; - rtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode); + rtw_set_supported_rate(bssrate, + (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode, + GET_WIFI_ROLE_CURRENT_CH(padapter)); bssrate_len = rtw_get_rateset_len(bssrate); if (bssrate_len > 8) { @@ -929,29 +926,25 @@ u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info * void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 bcn_early_case; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); if (enable == _TRUE) { #ifdef CONFIG_TDLS_CH_SW_V2 - pHalData->ch_switch_offload = _TRUE; + phl_com->ch_switch_offload = _TRUE; #endif #ifdef CONFIG_TDLS_CH_SW_BY_DRV - pHalData->ch_switch_offload = _FALSE; + phl_com->ch_switch_offload = _FALSE; #endif - bcn_early_case = TDLS_BCN_ERLY_ON; - } - else { - pHalData->ch_switch_offload = _FALSE; - bcn_early_case = TDLS_BCN_ERLY_OFF; } - + else + phl_com->ch_switch_offload = _FALSE; + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable) ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable); - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_EARLY_C2H_RPT, &enable); - rtw_hal_set_hwreg(padapter, HW_VAR_SET_DRV_ERLY_INT, &bcn_early_case); + rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_BCN_EARLY_C2H_RPT, &enable); RTW_INFO("[TDLS] %s Bcn Early C2H Report\n", (enable == _TRUE) ? "Start" : "Stop"); } @@ -963,11 +956,10 @@ void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter) pmlmepriv = &padapter->mlmepriv; if ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) && - (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter))) + (padapter->mlmeextpriv.chandef.chan != rtw_get_oper_ch(padapter))) rtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED); } -#ifndef CONFIG_TDLS_CH_SW_V2 static void rtw_tdls_chsw_oper_init(_adapter *padapter, u32 timeout_ms) { struct submit_ctx *chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx; @@ -988,12 +980,11 @@ void rtw_tdls_chsw_oper_done(_adapter *padapter) rtw_sctx_done(&chsw_sctx); } -#endif s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 center_ch, chnl_offset80 = CHAN_OFFSET_NO_EXT; u32 ch_sw_time_start, ch_sw_time_spent, wait_time; u8 take_care_iqk; s32 ret = _FAIL; @@ -1001,25 +992,27 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time()); /* set mac_id sleep before channel switch */ - rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id); + rtw_hal_macid_sleep(padapter, ptdls_sta->phl_sta->macid); #if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2) - set_channel_bwmode(padapter, channel, channel_offset, bwmode); + set_channel_bwmode(padapter, channel, channel_offset, bwmode, _FALSE); ret = _SUCCESS; #else rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); +#if 0 /*GEORGIA_TODO_FIXIT*/ + /* channel switch IOs offload to FW */ if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) { if (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) { /* set channel and bw related variables in driver */ - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + _rtw_mutex_lock_interruptible(&(dvobj->setch_mutex)); rtw_set_oper_ch(padapter, channel); rtw_set_oper_choffset(padapter, channel_offset); rtw_set_oper_bw(padapter, bwmode); - center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); + center_ch = rtw_phl_get_center_ch(channel, bwmode, channel_offset); pHalData->current_channel = center_ch; pHalData->CurrentCenterFrequencyIndex1 = center_ch; pHalData->current_channel_bw = bwmode; @@ -1027,17 +1020,17 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty if (bwmode == CHANNEL_WIDTH_80) { if (center_ch > channel) - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + chnl_offset80 = CHAN_OFFSET_UPPER; else if (center_ch < channel) - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + chnl_offset80 = CHAN_OFFSET_LOWER; else - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + chnl_offset80 = CHAN_OFFSET_NO_EXT; } pHalData->nCur80MhzPrimeSC = chnl_offset80; pHalData->CurrentCenterFrequencyIndex1 = center_ch; - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + _rtw_mutex_unlock(&(dvobj->setch_mutex)); rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); if (take_care_iqk == _TRUE) @@ -1047,6 +1040,7 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty } else RTW_INFO("[TDLS] chsw oper wait fail !!\n"); } +#endif #endif if (ret == _SUCCESS) { @@ -1063,7 +1057,7 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty } /* set mac_id wakeup after channel switch */ - rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id); + rtw_hal_macid_wakeup(padapter, ptdls_sta->phl_sta->macid); return ret; } @@ -1091,9 +1085,11 @@ u8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *p void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length) { u8 *wfd_ie; - u32 wfd_ielen = 0; + u32 wfd_ielen = 0; + _adapter *adapter = tdls_info_to_adapter(ptdlsinfo); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - if (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(dvobj, WL_FUNC_MIRACAST)) return; /* Try to get the TCP port information when receiving the negotiation response. */ @@ -1155,7 +1151,9 @@ int issue_tunneled_probe_req(_adapter *padapter) update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1197,7 +1195,9 @@ int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame) update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1218,7 +1218,6 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *ptdls_sta = NULL; - _irqL irqL; int ret = _FAIL; /* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */ u32 timeout_interval = TDLS_TPK_RESEND_COUNT; @@ -1247,7 +1246,9 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer); if (ptdls_sta == NULL) { RTW_INFO("[%s] rtw_alloc_stainfo fail\n", __FUNCTION__); + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1280,7 +1281,9 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1304,7 +1307,6 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; int ret = _FAIL; RTW_INFO("[TDLS] %s\n", __FUNCTION__); @@ -1336,7 +1338,9 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1412,7 +1416,9 @@ int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1451,7 +1457,9 @@ int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1492,7 +1500,9 @@ int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1583,16 +1593,18 @@ int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1628,7 +1640,7 @@ int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdl pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); @@ -1639,7 +1651,9 @@ int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdl update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1681,15 +1695,17 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta) pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1735,14 +1751,16 @@ int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, in update_tdls_attrib(padapter, pattrib); pattrib->qsel = pattrib->priority; /* - _enter_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinlock_bh(&pxmitpriv->lock); if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){ - _exit_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinunlock_bh(&pxmitpriv->lock); return _FALSE; } */ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + #endif rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } @@ -1762,7 +1780,6 @@ int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, in int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) { struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv))); - struct recv_priv *precvpriv = &(padapter->recvpriv); u8 *ptr = precv_frame->u.hdr.rx_data, *psa; struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); @@ -1772,7 +1789,7 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) int ret = _SUCCESS; if (psta) - rssi = psta->cmn.rssi_stat.rssi; + rssi = psta->phl_sta->rssi_stat.rssi; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); /* WFDTDLS: for sigma test, not to setup direct link automatically */ @@ -1836,7 +1853,6 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct u8 *ptr = precv_frame->u.hdr.rx_data; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct security_priv *psecuritypriv = &padapter->securitypriv; - _irqL irqL; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; u8 *prsnie, *ppairwise_cipher; u8 i, k; @@ -1921,7 +1937,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct _rtw_memcpy(supportRate, pIE->data, pIE->Length); supportRateNum = pIE->Length; break; - case _COUNTRY_IE_: + case WLAN_EID_COUNTRY: break; case _EXT_SUPPORTEDRATES_IE_: if (supportRateNum < sizeof(supportRate)) { @@ -1948,7 +1964,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct txmgmt.status_code = _STATS_INVALID_RSNIE_; } break; - case _EXT_CAP_IE_: + case WLAN_EID_EXT_CAP: break; case _VENDOR_SPECIFIC_IE_: break; @@ -2038,7 +2054,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct _set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); else { rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); } } @@ -2053,7 +2069,6 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; - _irqL irqL; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; u8 *psa; u16 status_code = 0; @@ -2087,7 +2102,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct if (status_code != 0) { RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code); rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2103,7 +2118,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct _rtw_memcpy(supportRate, pIE->data, pIE->Length); supportRateNum = pIE->Length; break; - case _COUNTRY_IE_: + case WLAN_EID_COUNTRY: break; case _EXT_SUPPORTEDRATES_IE_: if (supportRateNum < sizeof(supportRate)) { @@ -2122,7 +2137,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE) verify_ccmp = 1; } - case _EXT_CAP_IE_: + case WLAN_EID_EXT_CAP: break; case _VENDOR_SPECIFIC_IE_: if (_rtw_memcmp((u8 *)pIE + 2, WMM_INFO_OUI, 6) == _TRUE) { @@ -2186,7 +2201,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2213,7 +2228,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct if (prx_pkt_attrib->encrypt) rtw_tdls_set_key(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_ESTABLISHED); } } @@ -2231,7 +2246,6 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; - _irqL irqL; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; u8 *psa; u16 status_code = 0; @@ -2258,7 +2272,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct if (status_code != 0) { RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code); rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2312,7 +2326,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct if (rtw_tdls_is_driver_setup(padapter) && (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) { rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2335,7 +2349,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); } - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_ESTABLISHED); } exit: @@ -2408,7 +2422,6 @@ int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct s struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; u8 reason; reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2); @@ -2416,7 +2429,7 @@ int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct s if (rtw_tdls_is_driver_setup(padapter)) { rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); } return _SUCCESS; @@ -2448,7 +2461,7 @@ int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_ txmgmt.dialog_token = *(ptr + 2); issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt); - /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */ + /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->phl_sta->mac_addr, 0, 0, 0); */ return _SUCCESS; } @@ -2475,11 +2488,10 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, /* If it's a direct link and have buffered frame */ if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { if (wmmps_ac) { - _irqL irqL; _list *xmitframe_plist, *xmitframe_phead; struct xmit_frame *pxmitframe = NULL; - _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + _rtw_spinlock_bh(&ptdls_sta->sleep_q.lock); xmitframe_phead = get_list_head(&ptdls_sta->sleep_q); xmitframe_plist = get_next(xmitframe_phead); @@ -2501,7 +2513,7 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, } pxmitframe->attrib.triggered = 1; - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); } if (ptdls_sta->sleepq_len == 0) @@ -2511,7 +2523,7 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, ptdls_sta->sleepq_len = 0; } - _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + _rtw_spinunlock_bh(&ptdls_sta->sleep_q.lock); } @@ -2555,10 +2567,10 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, st pchsw_info->off_ch_num = *(ptr + 2); - if ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G))) + if ((*(ptr + 2) == 2) && (rtw_hw_is_band_support(adapter_to_dvobj(padapter), BAND_ON_5G))) pchsw_info->off_ch_num = 44; - if (pchsw_info->off_ch_num != pmlmeext->cur_channel) + if (pchsw_info->off_ch_num != pmlmeext->chandef.chan) pchsw_info->delay_switch_back = _FALSE; /* Parsing information element */ @@ -2568,16 +2580,16 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, st switch (pIE->ElementID) { case EID_SecondaryChnlOffset: switch (*(pIE->data)) { - case EXTCHNL_OFFSET_UPPER: - pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + case IEEE80211_SCA: + pchsw_info->ch_offset = CHAN_OFFSET_UPPER; break; - case EXTCHNL_OFFSET_LOWER: - pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + case IEEE80211_SCB: + pchsw_info->ch_offset = CHAN_OFFSET_LOWER; break; - default: - pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + default:/*IEEE80211_SCN*/ + pchsw_info->ch_offset = CHAN_OFFSET_NO_EXT; break; } break; @@ -2597,34 +2609,32 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, st j += (pIE->Length + 2); } -#ifndef CONFIG_TDLS_CH_SW_V2 rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); if (take_care_iqk == _TRUE) { u8 central_chnl; u8 bw_mode; bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; - central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); + central_chnl = rtw_phl_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) { if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE)) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_PREPARE); return _FAIL; } } -#endif /* cancel ch sw monitor timer for responder */ if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE) - _rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pchsw_info->addr, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_START); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_RESP); return _SUCCESS; } @@ -2650,9 +2660,9 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, st /* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */ /* we will go back to base channel and terminate this channel switch procedure */ if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { - if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) { + if (pmlmeext->chandef.chan != rtw_get_oper_ch(padapter)) { RTW_INFO("[TDLS] Rx unsolicited channel switch response\n"); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_TO_BASE_CHNL); goto exit; } } @@ -2671,7 +2681,7 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, st if (status_code != 0) { RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_END); ret = _FAIL; goto exit; } @@ -2699,10 +2709,10 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, st j += (pIE->Length + 2); } - if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) && + if ((pmlmeext->chandef.chan == rtw_get_oper_ch(padapter)) && (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) { if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_TO_OFF_CHNL); } exit: @@ -2719,7 +2729,7 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) u32 wfdielen = 0; u16 v16 = 0; - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) return; /* WFD OUI */ @@ -2862,11 +2872,11 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_qos_cap(pframe, pattrib); #ifdef CONFIG_80211AC_VHT - if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) + if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->chandef.chan > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && is_supported_vht(pregistrypriv->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { + && RFCTL_REG_EN_11AC(rfctl) + ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); } @@ -2957,14 +2967,14 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_qos_cap(pframe, pattrib); #ifdef CONFIG_80211AC_VHT - if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) + if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->chandef.chan > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && is_supported_vht(pregistrypriv->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { + && RFCTL_REG_EN_11AC(rfctl) + ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); - pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); + pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->chandef.bw); } #endif @@ -3034,13 +3044,13 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr #ifdef CONFIG_80211AC_VHT if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) - && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14) + && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->chandef.chan > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && is_supported_vht(pregistrypriv->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { - pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel); - pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); + && RFCTL_REG_EN_11AC(rfctl) + ) { + pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->chandef.chan); + pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->chandef.bw); } #endif } @@ -3190,13 +3200,13 @@ void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxm pframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib); pframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta); - if (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + if (ptdlsinfo->chsw_info.ch_offset != CHAN_OFFSET_NO_EXT) { switch (ptdlsinfo->chsw_info.ch_offset) { - case HAL_PRIME_CHNL_OFFSET_LOWER: - pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA); + case CHAN_OFFSET_UPPER: + pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, IEEE80211_SCA); break; - case HAL_PRIME_CHNL_OFFSET_UPPER: - pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB); + case CHAN_OFFSET_LOWER: + pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, IEEE80211_SCB); break; } } @@ -3253,7 +3263,7 @@ void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxm iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { pwdinfo = &iface->wdinfo; - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + if (pwdinfo->wfd_tdls_enable) { wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe); pframe += wfdielen; pattrib->pktlen += wfdielen; @@ -3283,7 +3293,7 @@ void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxm iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { pwdinfo = &iface->wdinfo; - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + if (pwdinfo->wfd_tdls_enable) { wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1); pframe += wfdielen; pattrib->pktlen += wfdielen; @@ -3304,9 +3314,9 @@ void _tdls_tpk_timer_hdl(void *FunctionContext) /* Retry timer should set at least 301 sec. */ if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) { RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", - __FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr)); + __FUNCTION__, MAC_ARG(ptdls_sta->phl_sta->mac_addr)); ptdls_sta->TPK_count = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE); } @@ -3320,7 +3330,7 @@ void _tdls_ch_switch_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter)); } @@ -3352,7 +3362,7 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_END); RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__); } @@ -3365,7 +3375,7 @@ void _tdls_handshake_timer_hdl(void *FunctionContext) struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; if (ptdls_sta != NULL) { @@ -3373,9 +3383,9 @@ void _tdls_handshake_timer_hdl(void *FunctionContext) RTW_INFO("[TDLS] Handshake time out\n"); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA); else - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA_LOCALLY); } } @@ -3386,7 +3396,7 @@ void _tdls_pti_timer_hdl(void *FunctionContext) struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->phl_sta->mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; if (ptdls_sta != NULL) { @@ -3394,8 +3404,8 @@ void _tdls_pti_timer_hdl(void *FunctionContext) if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) { RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; " - "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); + "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->phl_sta->mac_addr)); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_TEARDOWN_STA); } } } @@ -3403,15 +3413,15 @@ void _tdls_pti_timer_hdl(void *FunctionContext) void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta) { psta->padapter = padapter; - rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta); + rtw_init_timer(&psta->TPK_timer, _tdls_tpk_timer_hdl, psta); #ifdef CONFIG_TDLS_CH_SW - rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta); - rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta); - rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta); - rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta); + rtw_init_timer(&psta->ch_sw_timer, _tdls_ch_switch_timer_hdl, psta); + rtw_init_timer(&psta->delay_timer, _tdls_delay_timer_hdl, psta); + rtw_init_timer(&psta->stay_on_base_chnl_timer, _tdls_stay_on_base_chnl_timer_hdl, psta); + rtw_init_timer(&psta->ch_sw_monitor_timer, _tdls_ch_switch_monitor_timer_hdl, psta); #endif - rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta); - rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta); + rtw_init_timer(&psta->handshake_timer, _tdls_handshake_timer_hdl, psta); + rtw_init_timer(&psta->pti_timer, _tdls_pti_timer_hdl, psta); } void rtw_cancel_tdls_timer(struct sta_info *psta) @@ -3431,14 +3441,13 @@ void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; rtw_cancel_tdls_timer(psta); - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); if (ptdlsinfo->sta_cnt != 0) ptdlsinfo->sta_cnt--; - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { ptdlsinfo->sta_maximum = _FALSE; diff --git a/core/rtw_trx.c b/core/rtw_trx.c new file mode 100644 index 0000000..af27a9f --- /dev/null +++ b/core/rtw_trx.c @@ -0,0 +1,153 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_TRX_C_ +#include /* struct dvobj_priv and etc. */ + + +#ifdef RTW_PHL_TX +s32 rtw_core_tx_mgmt(_adapter *padapter, struct xmit_frame *pxframe) +{ + + pxframe->xftype = RTW_TX_DRV_MGMT; + +#ifdef RTW_PHL_DBG_CMD + core_add_record(padapter, REC_TX_MGMT, pxframe); +#endif + + if(core_tx_prepare_phl(padapter, pxframe) == FAIL) + return _FAIL; + + if (core_tx_call_phl(padapter, pxframe, NULL) == FAIL) + return _FAIL; + + return _SUCCESS; +} +#endif + +#ifdef CONFIG_DRV_FAKE_AP +int rtw_fakeap_tx(struct _ADAPTER*, struct xmit_frame*); +#endif /* CONFIG_DRV_FAKE_AP */ +/*rtw_hal_mgnt_xmit*/ +s32 rtw_mgnt_xmit(_adapter *adapter, struct xmit_frame *pmgntframe) +{ + s32 ret = _FAIL; + + update_mgntframe_attrib_addr(adapter, pmgntframe); + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) + if ((!MLME_IS_MESH(adapter) && SEC_IS_BIP_KEY_INSTALLED(&adapter->securitypriv) == _TRUE) + #ifdef CONFIG_RTW_MESH + || (MLME_IS_MESH(adapter) && adapter->mesh_info.mesh_auth_id) + #endif + ) + rtw_mgmt_xmitframe_coalesce(adapter, pmgntframe->pkt, pmgntframe); +#endif + +#ifdef CONFIG_DRV_FAKE_AP +#ifndef RTW_PHL_TEST_FPGA + if (rtw_fakeap_tx(adapter, pmgntframe) == _SUCCESS) + return _SUCCESS; +#endif +#endif /* CONFIG_DRV_FAKE_AP */ + + ret = rtw_core_tx_mgmt(adapter, pmgntframe); + return ret; +} + + +struct lite_data_buf *rtw_alloc_litedatabuf(struct trx_data_buf_q *data_buf_q) +{ + struct lite_data_buf *litedatabuf = NULL; + _list *list, *head; + _queue *free_litedatabuf_q = &data_buf_q->free_data_buf_queue; + unsigned long sp_flags; + + /* RTW_INFO("+rtw_alloc_litexmitbuf\n"); */ + + _rtw_spinlock_irq(&free_litedatabuf_q->lock, &sp_flags); + + if (_rtw_queue_empty(free_litedatabuf_q) == _TRUE) + litedatabuf = NULL; + else { + + head = get_list_head(free_litedatabuf_q); + + list = get_next(head); + + litedatabuf = LIST_CONTAINOR(list, + struct lite_data_buf, list); + + rtw_list_delete(&(litedatabuf->list)); + } + + if (litedatabuf != NULL) { + data_buf_q->free_data_buf_cnt--; + + + if (litedatabuf->sctx) { + RTW_INFO("%s plitexmitbuf->sctx is not NULL\n", + __func__); + rtw_sctx_done_err(&litedatabuf->sctx, + RTW_SCTX_DONE_BUF_ALLOC); + } + } + + _rtw_spinunlock_irq(&free_litedatabuf_q->lock, &sp_flags); + + + return litedatabuf; +} + +s32 rtw_free_litedatabuf(struct trx_data_buf_q *data_buf_q, + struct lite_data_buf *lite_data_buf) +{ + _queue *free_litedatabuf_q = &data_buf_q->free_data_buf_queue; + unsigned long sp_flags; + + /* RTW_INFO("+rtw_free_litexmitbuf\n"); */ + + if (data_buf_q == NULL) + return _FAIL; + + if (lite_data_buf == NULL) + return _FAIL; + + lite_data_buf->pbuf = NULL; + lite_data_buf->phl_buf_ptr = NULL; +#ifdef CONFIG_USB_HCI + lite_data_buf->dataurb = NULL; +#endif + + if (lite_data_buf->sctx) { + RTW_INFO("%s lite_data_buf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&lite_data_buf->sctx, RTW_SCTX_DONE_BUF_FREE); + return _FAIL; + } + + _rtw_spinlock_irq(&free_litedatabuf_q->lock, &sp_flags); + + rtw_list_delete(&lite_data_buf->list); + + rtw_list_insert_tail(&(lite_data_buf->list), + get_list_head(free_litedatabuf_q)); + + data_buf_q->free_data_buf_cnt++; + + _rtw_spinunlock_irq(&free_litedatabuf_q->lock, &sp_flags); + + + return _SUCCESS; +} + diff --git a/core/rtw_trx_pci.c b/core/rtw_trx_pci.c new file mode 100644 index 0000000..f4ea211 --- /dev/null +++ b/core/rtw_trx_pci.c @@ -0,0 +1,309 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_TRX_PCI_C_ +#include /* struct dvobj_priv and etc. */ + +static void rtw_mi_pci_tasklets_kill(_adapter *padapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + rtw_tasklet_kill(&(padapter->xmitpriv.xmit_tasklet)); + } + } +} + +#if 0 /*def CONFIG_TX_AMSDU*/ +static s32 xmitframe_amsdu_direct(_adapter *padapter, + struct xmit_frame *pxmitframe) +{ + struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 res = _SUCCESS; + + res = rtw_xmitframe_coalesce_amsdu(padapter, pxmitframe, NULL); + + if (res == _SUCCESS) { +#ifdef CONFIG_XMIT_THREAD_MODE + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf); +#else + res = rtw_hal_dump_xframe(padapter, pxmitframe); +#endif + } else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + return res; +} +#endif + +/********************************xmit section*****************************/ +static void pci_xmit_tasklet(_adapter *padapter) +{ +#ifdef CONFIG_TX_AMSDU_SW_MODE + core_tx_amsdu_tasklet(padapter); +#endif +} + +s32 pci_init_xmit_priv(_adapter *adapter) +{ + s32 ret = _SUCCESS; + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + _rtw_spinlock_init(&dvobj_to_pci(dvobj)->irq_th_lock); + + rtw_tasklet_init(&pxmitpriv->xmit_tasklet, + (void(*)(unsigned long))pci_xmit_tasklet, + (unsigned long)adapter); + + return ret; +} + +void pci_free_xmit_priv(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + _rtw_spinlock_free(&dvobj_to_pci(dvobj)->irq_th_lock); +} + +static s32 pci_xmit_direct(_adapter *adapter, struct xmit_frame *pxmitframe) +{ + s32 res = _SUCCESS; +#if 0 + #ifdef CONFIG_XMIT_THREAD_MODE + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + #endif + + + res = rtw_xmitframe_coalesce(adapter, pxmitframe->pkt, pxmitframe); + if (res == _SUCCESS) { + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf); + #else + pci_dump_xframe(adapter, pxmitframe); + #endif + } +#endif + return res; +} + +static s32 pci_data_xmit(_adapter *adapter, struct xmit_frame *pxmitframe) +{ + s32 res; + #if 0 /*CONFIG_CORE_XMITBUF*/ + struct xmit_buf *pxmitbuf = NULL; + #endif + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); +#ifdef CONFIG_TX_AMSDU + int tx_amsdu = adapter->tx_amsdu; + u8 amsdu_timeout = 0; +#endif + + _rtw_spinlock_bh(&pxmitpriv->lock); + + if (rtw_txframes_sta_ac_pending(adapter, pattrib) > 0) + goto enqueue; + +#ifndef CONFIG_XMIT_THREAD_MODE + if (rtw_hal_pci_check_enough_txdesc(GET_PHL_COM(dvobj), pattrib->qsel) == _FALSE) + goto enqueue; + + if (rtw_xmit_ac_blocked(adapter) == _TRUE) + goto enqueue; +#endif + + if (DEV_STA_LG_NUM(adapter->dvobj)) + goto enqueue; + +#ifdef CONFIG_TX_AMSDU + if (MLME_IS_STA(adapter) && + check_amsdu_tx_support(adapter)) { + + if (IS_AMSDU_AMPDU_VALID(pattrib)) + goto enqueue; + } +#endif +#if 0 /*CONFIG_CORE_XMITBUF*/ + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) + goto enqueue; + + _rtw_spinunlock_bh(&pxmitpriv->lock); + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; +#else + _rtw_spinunlock_bh(&pxmitpriv->lock); +#endif + if (pci_xmit_direct(adapter, pxmitframe) != _SUCCESS) { + #if 0 /*CONFIG_CORE_XMITBUF*/ + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + #endif + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + return _TRUE; + +enqueue: + res = rtw_xmitframe_enqueue(adapter, pxmitframe); + +#ifdef CONFIG_TX_AMSDU + if(res == _SUCCESS && tx_amsdu == 2) + { + amsdu_timeout = rtw_amsdu_get_timer_status(adapter, pattrib->priority); + if(amsdu_timeout == RTW_AMSDU_TIMER_SETTING) + { + rtw_amsdu_cancel_timer(adapter, pattrib->priority); + rtw_amsdu_set_timer_status(adapter, pattrib->priority, + RTW_AMSDU_TIMER_UNSET); + } + } +#endif + + _rtw_spinunlock_bh(&pxmitpriv->lock); + + if (res != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitpriv->tx_drop++; + return _TRUE; + } + +#ifdef CONFIG_TX_AMSDU + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#endif + return _FALSE; +} + +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ +/* + * Description + * Transmit xmitbuf to hardware tx fifo + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +s32 pci_xmit_buf_handler(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct xmit_priv *pxmitpriv; + struct xmit_buf *pxmitbuf; + struct xmit_frame *pxmitframe; + s32 ret; + + pxmitpriv = &adapter->xmitpriv; + + ret = _rtw_down_sema(&pxmitpriv->xmit_sema); + + if (ret == _FAIL) { + RTW_ERR("%s: down XmitBufSema fail!\n", __FUNCTION__); + return _FAIL; + } + + if (RTW_CANNOT_RUN(dvobj)) { + RTW_INFO("%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\n" + , __func__ + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False"); + return _FAIL; + } + + if (check_pending_xmitbuf(pxmitpriv) == _FALSE) + return _SUCCESS; + +#ifdef CONFIG_LPS_LCLK + ret = rtw_register_tx_alive(adapter); + if (ret != _SUCCESS) { + RTW_INFO("%s: wait to leave LPS_LCLK\n", __FUNCTION__); + return _SUCCESS; + } +#endif + + do { + pxmitbuf = select_and_dequeue_pending_xmitbuf(adapter); + + if (pxmitbuf == NULL) + break; + pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; + + if (rtw_hal_pci_check_enough_txdesc(GET_PHL_COM(dvobj), + pxmitframe->attrib.qsel) == _FALSE) { + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + break; + } + pci_dump_xframe(adapter, pxmitframe); + } while (1); + + + return _SUCCESS; +} +#endif +s32 pci_xmitframe_enqueue(_adapter *adapter, + struct xmit_frame *pxmitframe) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + s32 err; + + err = rtw_xmitframe_enqueue(adapter, pxmitframe); + if (err != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + pxmitpriv->tx_drop++; + } else { + if (rtw_hal_pci_check_enough_txdesc(GET_PHL_COM(dvobj), + pxmitframe->attrib.qsel) == _TRUE) + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + } + + return err; +} +/******************************** recv section*******************************/ +s32 pci_init_recv_priv(struct dvobj_priv *dvobj) +{ + s32 ret = _SUCCESS; + + return ret; +} + +void pci_free_recv_priv(struct dvobj_priv *dvobj) +{ + +} + + +struct rtw_intf_ops pci_ops = { + .init_xmit_priv = pci_init_xmit_priv, + .free_xmit_priv = pci_free_xmit_priv, + .data_xmit = pci_data_xmit, + .xmitframe_enqueue = pci_xmitframe_enqueue, + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ + .xmit_buf_handler = pci_xmit_buf_handler + #endif + + .init_recv_priv = pci_init_recv_priv, + .free_recv_priv = pci_free_recv_priv, +}; + diff --git a/core/rtw_trx_sdio.c b/core/rtw_trx_sdio.c new file mode 100644 index 0000000..7cbf7dc --- /dev/null +++ b/core/rtw_trx_sdio.c @@ -0,0 +1,537 @@ +/****************************************************************************** + * + * Copyright(c) 2015 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_TRX_SDIO_C_ + +#include /* struct dvobj_priv and etc. */ +#include /* RTW_SDIO_ADDR_CMD52_GEN */ +#include + +#define CONFIG_NEW_SDIO_WP_FUNC +#ifdef CONFIG_NEW_SDIO_WP_FUNC +/* + * Description: + * Write to TX FIFO + * Align write size to block size, + * and check enough FIFO size to write. + * + * Parameters: + * addr not use + * cnt size to write + * mem struct xmit_buf* + * + * Return: + * _SUCCESS(1) Success + * _FAIL(0) Fail + */ +static u32 rtw_sdio_xmit(struct dvobj_priv *d, u32 txaddr, u32 cnt, u8 *mem) +{ + u32 txsize; + u32 ret = _FAIL; + + cnt = _RND4(cnt); + + /* align size to guarantee I/O would be done in one command */ + txsize = rtw_sdio_cmd53_align_size(d, cnt); + + ret = rtw_sdio_write_cmd53(d, txaddr, mem, txsize); + + /*GEORGIA_TODO_FIXIT_MOVE_TO_CALLER*/ + /*rtw_sctx_done_err(&xmitbuf->sctx, + (_FAIL == ret) ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);*/ +exit : + return ret; +} +#else +static u32 rtw_sdio_xmit(struct dvobj_priv *d, u32 txaddr, u32 cnt, u8 *mem) +{ + s32 err; + u32 txaddr; + + cnt = _RND4(cnt); + cnt = rtw_sdio_cmd53_align_size(d, cnt); + + err = sd_write(d, txaddr, cnt, mem); + + /*GEORGIA_TODO_FIXIT_MOVE_TO_CALLER*/ + /*rtw_sctx_done_err(&xmitbuf->sctx, + err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);*/ + + if (err) { + RTW_ERR("%s, error=%d\n", __func__, err); + return _FAIL; + } + return _SUCCESS; +} +#endif + + +/********************************xmit section*******************************/ +#ifdef CONFIG_TX_AMSDU_SW_MODE +static void sdio_xmit_tasklet(_adapter *padapter) +{ + core_tx_amsdu_tasklet(padapter); +} +#endif + +s32 sdio_init_xmit_priv(_adapter *adapter) +{ +#ifdef CONFIG_TX_AMSDU_SW_MODE + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + + rtw_tasklet_init(&xmitpriv->xmit_tasklet, + (void(*)(unsigned long))sdio_xmit_tasklet, + (unsigned long)adapter); +#endif + return _SUCCESS; +} + +void sdio_free_xmit_priv(_adapter *adapter) +{ +#if 0 /*CONFIG_CORE_XMITBUF*/ + struct xmit_priv *pxmitpriv; + struct xmit_buf *pxmitbuf; + _queue *pqueue; + _list *plist, *phead; + _list tmplist; + + pxmitpriv = &adapter->xmitpriv; + pqueue = &pxmitpriv->pending_xmitbuf_queue; + phead = get_list_head(pqueue); + _rtw_init_listhead(&tmplist); + + _rtw_spinlock_bh(&pqueue->lock); + if (_rtw_queue_empty(pqueue) == _FALSE) { + /* + * Insert tmplist to end of queue, and delete phead + * then tmplist become head of queue. + */ + rtw_list_insert_tail(&tmplist, phead); + rtw_list_delete(phead); + } + _rtw_spinunlock_bh(&pqueue->lock); + + phead = &tmplist; + while (rtw_is_list_empty(phead) == _FALSE) { + plist = get_next(phead); + rtw_list_delete(plist); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + rtw_free_xmitframe(pxmitpriv, (struct xmit_frame *)pxmitbuf->priv_data); + pxmitbuf->priv_data = NULL; + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + } +#endif +} + +/* + * Description: + * Handle xmitframe(packet) come from rtw_xmit() + * + * Return: + * _TRUE handle packet directly, maybe ok or drop + * _FALSE enqueue, temporary can't transmit packets to hardware + */ +s32 sdio_data_xmit(_adapter *adapter, struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv; + s32 err; + + pxmitframe->attrib.qsel = pxmitframe->attrib.priority; + pxmitpriv = &adapter->xmitpriv; + +#ifdef CONFIG_80211N_HT + if ((pxmitframe->frame_tag == DATA_FRAMETAG) + && (pxmitframe->attrib.ether_type != 0x0806) + && (pxmitframe->attrib.ether_type != 0x888e) + && (pxmitframe->attrib.dhcp_pkt != 1)) { + rtw_issue_addbareq_cmd(adapter, pxmitframe, _TRUE); + } +#endif /* CONFIG_80211N_HT */ + + _rtw_spinlock_bh(&pxmitpriv->lock); + err = rtw_xmitframe_enqueue(adapter, pxmitframe); + _rtw_spinunlock_bh(&pxmitpriv->lock); + if (err != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitpriv->tx_drop++; + return _TRUE; + } + +#ifdef CONFIG_SDIO_TX_TASKLET + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#else + _rtw_up_sema(&pxmitpriv->SdioXmitSema); +#endif + + return _FALSE; +} + +/* + * Description: + * Aggregation packets and send to hardware + * + * Return: + * 0 Success + * -1 Hardware resource(TX FIFO) not ready + * -2 Software resource(xmitbuf) not ready + */ + /*SDIO bus-agg*/ +static s32 _sdio_xmit_xmitframes(_adapter *adapter, struct xmit_priv *pxmitpriv) +{ + s32 err = 0; + + return err; +} + +/* + * Description + * Transmit xmitframe from queue + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +static s32 _sdio_xmit_frame_handler(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + s32 ret; + + ret = _rtw_down_sema(&pxmitpriv->SdioXmitSema); + if (_FAIL == ret) { + RTW_ERR("%s: down sema fail!\n", __FUNCTION__); + return _FAIL; + } + +next: + if (RTW_CANNOT_RUN(dvobj)) { + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(adapter), + dev_is_drv_stopped(dvobj) ? "True" : "False", + dev_is_surprise_removed(dvobj) ? "True" : "False"); + return _FAIL; + } + + _rtw_spinlock_bh(&pxmitpriv->lock); + ret = rtw_txframes_pending(adapter); + _rtw_spinunlock_bh(&pxmitpriv->lock); + /* All queues are empty! */ + if (ret == 0) + return _SUCCESS; + + /* Dequeue frame and agg-tx then enqueue pending xmitbuf-queue */ + ret = _sdio_xmit_xmitframes(adapter, pxmitpriv); + if (ret == -2) { + /* here sleep 1ms will cause big TP loss of TX */ + /* from 50+ to 40+ */ + if (adapter->registrypriv.wifi_spec) + rtw_msleep_os(1); + else + #ifdef CONFIG_REDUCE_TX_CPU_LOADING + rtw_msleep_os(1); + #else + rtw_yield_os(); + #endif + + goto next; + } + _rtw_spinlock_bh(&pxmitpriv->lock); + ret = rtw_txframes_pending(adapter); + _rtw_spinunlock_bh(&pxmitpriv->lock); + if (ret == 1) + goto next; + + return _SUCCESS; +} + +thread_return _sdio_xmit_frame_thread(thread_context context) +{ + s32 ret; + _adapter *adapter; + struct xmit_priv *pxmitpriv; + u8 thread_name[20] = {0}; + + + ret = _SUCCESS; + adapter = (_adapter *)context; + pxmitpriv = &adapter->xmitpriv; + + rtw_sprintf(thread_name, 20, "RTWHALXT-"ADPT_FMT, ADPT_ARG(adapter)); + rtw_thread_enter(thread_name); + + RTW_INFO("start "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + do { + ret = _sdio_xmit_frame_handler(adapter); + flush_signals_thread(); + } while (_SUCCESS == ret); + + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); + + rtw_thread_wait_stop(); + + return 0; +} +u8 sdio_start_xmit_frame_thread(_adapter *adapter) +{ + u8 _status = _SUCCESS; + +#ifndef CONFIG_SDIO_TX_TASKLET + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + + if (xmitpriv->SdioXmitThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTWHALXT\n", FUNC_ADPT_ARG(adapter)); + xmitpriv->SdioXmitThread = rtw_thread_start(_sdio_xmit_frame_thread, adapter, "RTWHALXT"); + if (xmitpriv->SdioXmitThread == NULL) { + RTW_ERR("%s: start _sdio_xmit_frame_thread FAIL!!\n", __FUNCTION__); + _status = _FAIL; + } + } +#endif /* !CONFIG_SDIO_TX_TASKLET */ + return _status; +} + +void sdio_cancel_xmit_frame_thread(_adapter *adapter) +{ +#ifndef CONFIG_SDIO_TX_TASKLET + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + + /* stop xmit_buf_thread */ + if (xmitpriv->SdioXmitThread) { + _rtw_up_sema(&xmitpriv->SdioXmitSema); + rtw_thread_stop(xmitpriv->SdioXmitThread); + xmitpriv->SdioXmitThread = NULL; + } +#endif /* !CONFIG_SDIO_TX_TASKLET */ +} + +s32 sdio_dequeue_xmit(_adapter *adapter) +{ +#if 0 + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + struct xmit_buf *pxmitbuf; + u32 polling_num = 0; + u32 txaddr = 0; + +#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT + +#endif + pxmitbuf = select_and_dequeue_pending_xmitbuf(adapter); + + if (pxmitbuf == NULL) + return _TRUE; + +#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT +query_free_page: + + /* Total number of page is NOT available, so update current FIFO status*/ + u8 bUpdatePageNum = _FALSE; + + if (!bUpdatePageNum) { + HalQueryTxBufferStatus8821CSdio(adapter); + bUpdatePageNum = _TRUE; + goto query_free_page; + } else { + bUpdatePageNum = _FALSE; + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + return _TRUE; + } +#endif + if (_TRUE == rtw_is_xmit_blocked(adapter)) { + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + /*rtw_msleep_os(1);*/ + return _FALSE; + } + + /* check if hardware tx fifo page is enough */ + while (rtw_halmac_sdio_tx_allowed(pdvobjpriv, pxmitbuf->pdata, pxmitbuf->len)) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) { + RTW_INFO("%s: bSurpriseRemoved(write port)\n", __func__); + goto free_xmitbuf; + } + + polling_num++; + /* Only polling (0x7F / 10) times here, since rtw_halmac_sdio_tx_allowed() has polled 10 times within */ + if ((polling_num % 6) == 0) { + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + rtw_msleep_os(1); + return _FALSE; + } + } + +#ifdef CONFIG_CHECK_LEAVE_LPS + #ifdef CONFIG_LPS_CHK_BY_TP + if (!adapter_to_pwrctl(adapter)->lps_chk_by_tp) + #endif + traffic_check_for_leave_lps(adapter, _TRUE, pxmitbuf->agg_num); +#endif + + if (_TRUE == rtw_is_xmit_blocked(adapter)) { + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + /*rtw_msleep_os(1);*/ + return _FALSE; + } + /*sdio_write_port(adapter, pxmitbuf->len, (u8 *)pxmitbuf);*/ + txaddr = rtw_hal_sdio_get_tx_addr(GET_PHL_COM(pdvobjpriv), + pxmitbuf->pdata, pxmitbuf->len); + rtw_sdio_xmit(adapter, txaddr, pxmitbuf->len, (u8 *)pxmitbuf); + +free_xmitbuf: + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + +#ifdef CONFIG_SDIO_TX_TASKLET + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#endif + +#endif + return _FALSE; +} + +/* + * Description + * Transmit xmitbuf to hardware tx fifo + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ +s32 sdio_xmit_buf_handler(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct xmit_priv *pxmitpriv; + u8 queue_empty, queue_pending; + s32 ret; + + + pxmitpriv = &adapter->xmitpriv; + + ret = _rtw_down_sema(&pxmitpriv->xmit_sema); + if (_FAIL == ret) { + RTW_ERR("%s: down SdioXmitBufSema fail!\n", __FUNCTION__); + return _FAIL; + } + + if (RTW_CANNOT_RUN(dvobj)) { + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(adapter), + dev_is_drv_stopped(dvobj) ? "True" : "False", + dev_is_surprise_removed(dvobj) ? "True" : "False"); + return _FAIL; + } + + if (rtw_mi_check_pending_xmitbuf(adapter) == 0) + return _SUCCESS; +#ifdef CONFIG_LPS_LCLK + ret = rtw_register_tx_alive(adapter); + if (ret != _SUCCESS) + return _SUCCESS; +#endif + + do { + queue_empty = rtw_mi_sdio_dequeue_xmit(adapter); + + } while (!queue_empty); + +#ifdef CONFIG_LPS_LCLK + rtw_unregister_tx_alive(adapter); +#endif + + return _SUCCESS; +} +#endif +/* + * Description: + * Enqueue xmitframe + * + * Return: + * _TRUE enqueue ok + * _FALSE fail + */ +s32 sdio_xmitframe_enqueue(_adapter *adapter, struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv; + s32 ret; + + + pxmitpriv = &adapter->xmitpriv; + + ret = rtw_xmitframe_enqueue(adapter, pxmitframe); + if (ret != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + pxmitpriv->tx_drop++; + return _FALSE; + } + +#ifdef CONFIG_SDIO_TX_TASKLET + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#else /* !CONFIG_SDIO_TX_TASKLET */ + _rtw_up_sema(&pxmitpriv->SdioXmitSema); +#endif /* !CONFIG_SDIO_TX_TASKLET */ + + return _TRUE; +} +/******************************** recv section******************************/ +static s32 sdio_recv_hdl(_adapter *adapter) +{ + return _SUCCESS; + +} + +s32 sdio_init_recv_priv(struct dvobj_priv *dvobj) +{ + s32 res = _SUCCESS; + return res; +} + +/* + * Free recv private variable of hardware dependent + * 1. recv buf + * 2. recv tasklet + */ +void sdio_free_recv_priv(struct dvobj_priv *dvobj) +{ + +} + + +struct rtw_intf_ops sdio_ops = { + .read = rtw_sdio_raw_read, + .write = rtw_sdio_raw_write, + + /****************** data path *****************/ + + /****************** xmit *********************/ + .init_xmit_priv = sdio_init_xmit_priv, + .free_xmit_priv = sdio_free_xmit_priv, + .data_xmit = sdio_data_xmit, + .xmitframe_enqueue = sdio_xmitframe_enqueue, + .start_xmit_frame_thread = sdio_start_xmit_frame_thread, + .cancel_xmit_frame_thread = sdio_cancel_xmit_frame_thread, + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ + .xmit_buf_handler = sdio_xmit_buf_handler, + #endif + + /****************** recv *********************/ + .init_recv_priv = sdio_init_recv_priv, + .free_recv_priv = sdio_free_recv_priv, + #ifdef CONFIG_RECV_THREAD_MODE + .recv_hdl = sdio_recv_hdl, + #endif +}; + diff --git a/core/rtw_trx_usb.c b/core/rtw_trx_usb.c new file mode 100644 index 0000000..507a748 --- /dev/null +++ b/core/rtw_trx_usb.c @@ -0,0 +1,108 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_TRX_USB_C_ +#include /* struct dvobj_priv and etc. */ + + +/********************************xmit section*******************************/ +#ifdef CONFIG_USB_TX_AGGREGATION +#define IDEA_CONDITION 1 /* check all packets before enqueue */ +static s32 usb_xmitframe_process(_adapter *padapter, + struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + return _TRUE; +} + +#else /* CONFIG_USB_TX_AGGREGATION */ + +static s32 usb_xmitframe_process(_adapter *padapter, + struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + return _TRUE; + +} +#endif + + +static void usb_xmit_tasklet(_adapter *padapter) +{ +#ifdef CONFIG_TX_AMSDU_SW_MODE + core_tx_amsdu_tasklet(padapter); +#endif +} + +s32 usb_init_xmit_priv(_adapter *adapter) +{ + s32 ret = _SUCCESS; + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + rtw_tasklet_init(&pxmitpriv->xmit_tasklet, + (void(*)(unsigned long))usb_xmit_tasklet, + (unsigned long)adapter); + + return _SUCCESS; +} + +void usb_free_xmit_priv(_adapter *adapter) +{ +} + +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ +/* + * Description + * Transmit xmitbuf to hardware tx fifo + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +s32 usb_xmit_buf_handler(_adapter *adapter) +{ + return _SUCCESS; +} +#endif /* CONFIG_XMIT_THREAD_MODE */ + +s32 usb_xmitframe_enqueue(_adapter *adapter, struct xmit_frame *pxmitframe) +{ + return _SUCCESS; +} + +/******************************** recv section*******************************/ +int usb_init_recv_priv(struct dvobj_priv *dvobj) +{ + int res = _SUCCESS; + + return res; +} + +void usb_free_recv_priv(struct dvobj_priv *dvobj) +{ + +} + +struct rtw_intf_ops usb_ops = { + .init_xmit_priv = usb_init_xmit_priv, + .free_xmit_priv = usb_free_xmit_priv, + .xmitframe_enqueue = usb_xmitframe_enqueue, + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ + .xmit_buf_handler = usb_xmit_buf_handler, + #endif + + .init_recv_priv = usb_init_recv_priv, + .free_recv_priv = usb_free_recv_priv, + +}; + diff --git a/core/rtw_vht.c b/core/rtw_vht.c index 55b1709..5093399 100644 --- a/core/rtw_vht.c +++ b/core/rtw_vht.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,6 @@ #define _RTW_VHT_C #include -#include #ifdef CONFIG_80211AC_VHT const u16 _vht_max_mpdu_len[] = { @@ -32,7 +31,6 @@ const u8 _vht_sup_ch_width_set_to_bw_cap[] = { 0, }; -#ifdef CONFIG_RTW_DEBUG const char *const _vht_sup_ch_width_set_str[] = { "80MHz", "160MHz", @@ -87,11 +85,15 @@ void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len) return; } - RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n" - , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf)) - , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf) - , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf) - ); + RTW_PRINT_SEL(sel, "\tVHT Operation Info:\n"); + RTW_PRINT_SEL(sel, "\tChannel Width: %u\n" + , GET_VHT_OPERATION_ELE_CHL_WIDTH(buf)); + RTW_PRINT_SEL(sel, "\tCenter Frequency Channel for 80 and 160 MHz Operation: %u\n" + , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)); + RTW_PRINT_SEL(sel, "\tCenter Frequency Channel for 80+80 MHz Operation: %u\n" + , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)); + RTW_PRINT_SEL(sel, "\tVHT Basic MCS Set: 0x%04x\n" + , GET_VHT_OPERATION_ELE_BASIC_MCS_SET(buf)); } void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len) @@ -105,47 +107,40 @@ void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len) dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen); } -#endif /* 20/40/80, ShortGI, MCS Rate */ -const u16 VHT_MCS_DATA_RATE[3][2][40] = { /* unit: 0.5M */ +const u16 VHT_MCS_DATA_RATE[3][2][30] = { { { 13, 26, 39, 52, 78, 104, 117, 130, 156, 156, 26, 52, 78, 104, 156, 208, 234, 260, 312, 312, - 39, 78, 117, 156, 234, 312, 351, 390, 468, 520, - 52, 104, 156, 208, 312, 416, 468, 520, 624, 624, + 39, 78, 117, 156, 234, 312, 351, 390, 468, 520 }, /* Long GI, 20MHz */ { 14, 29, 43, 58, 87, 116, 130, 144, 173, 173, 29, 58, 87, 116, 173, 231, 260, 289, 347, 347, - 43, 87, 130, 173, 260, 347, 390, 433, 520, 578, - 58, 116, 173, 231, 347, 462, 520, 578, 693, 693, + 43, 87, 130, 173, 260, 347, 390, 433, 520, 578 } }, /* Short GI, 20MHz */ { { 27, 54, 81, 108, 162, 216, 243, 270, 324, 360, 54, 108, 162, 216, 324, 432, 486, 540, 648, 720, - 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080, - 108, 216, 324, 432, 648, 864, 972, 1080, 1296, 1440, + 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080 }, /* Long GI, 40MHz */ { 30, 60, 90, 120, 180, 240, 270, 300, 360, 400, 60, 120, 180, 240, 360, 480, 540, 600, 720, 800, - 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200, - 120, 240, 360, 480, 720, 960, 1080, 1200, 1440, 1600, + 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200 } }, /* Short GI, 40MHz */ { { - 59, 117, 176, 234, 351, 468, 527, 585, 702, 780, + 59, 117, 176, 234, 351, 468, 527, 585, 702, 780, 117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560, - 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340, - 234, 468, 702, 936, 1404, 1872, 2106, 2340, 2808, 3120, + 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340 }, /* Long GI, 80MHz */ { 65, 130, 195, 260, 390, 520, 585, 650, 780, 867, 130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734, - 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600, - 260, 520, 780, 1040, 1560, 2080, 2340, 2600, 3120, 3467, + 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600 } } /* Short GI, 80MHz */ }; @@ -217,69 +212,217 @@ void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map) u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate) { - if (vht_mcs_rate > MGN_VHT4SS_MCS9) - vht_mcs_rate = MGN_VHT4SS_MCS9; + if (vht_mcs_rate > MGN_VHT3SS_MCS9) + vht_mcs_rate = MGN_VHT3SS_MCS9; /* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */ return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)]; } -void rtw_vht_use_default_setting(_adapter *padapter) +/* Initialized vhtpriv by PHL default setting */ +void rtw_vht_get_dft_setting(_adapter *padapter, + struct protocol_cap_t *dft_proto_cap, struct role_cap_t *dft_cap) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - struct registry_priv *pregistrypriv = &padapter->registrypriv; - BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + u8 stbc_rx = 0; #ifdef CONFIG_BEAMFORMING - BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; - u8 mu_bfer, mu_bfee; + BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; + u8 mu_bfer, mu_bfee; #endif /* CONFIG_BEAMFORMING */ u8 tx_nss, rx_nss; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - /* LDPC support */ - rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); - CLEAR_FLAGS(pvhtpriv->ldpc_cap); + /* Short GI */ + pvhtpriv->sgi_80m = ((dft_proto_cap->sgi_80) + && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_80M) + && TEST_FLAG(pregistrypriv->short_gi, BIT2)); + + pvhtpriv->sgi_160m = ((dft_proto_cap->sgi_160) + && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_160M) + && TEST_FLAG(pregistrypriv->short_gi, BIT3)); + + /* LDPC */ + bHwLDPCSupport = (dft_proto_cap->vht_ldpc) ? _TRUE : _FALSE; if (bHwLDPCSupport) { if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0)) SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX); } - rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + + bHwLDPCSupport = (dft_cap->tx_vht_ldpc) ? _TRUE : _FALSE; if (bHwLDPCSupport) { if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1)) SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX); } + if (pvhtpriv->ldpc_cap) RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap); /* STBC */ - rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); - CLEAR_FLAGS(pvhtpriv->stbc_cap); - if (bHwSTBCSupport) { - if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1)) - SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX); - } - rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); - if (bHwSTBCSupport) { - if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0)) - SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX); - } + if (dft_proto_cap->stbc_vht_tx) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX); + + if (dft_proto_cap->stbc_vht_rx) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX); + if (pvhtpriv->stbc_cap) RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap); /* Beamforming setting */ - CLEAR_FLAGS(pvhtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 -#ifdef CONFIG_CONCURRENT_MODE /* only enable beamforming in STA client mode */ - if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)) + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) + { + + bHwSupportBeamformer = (dft_proto_cap->vht_su_bfmr) ? _TRUE : _FALSE; + bHwSupportBeamformee = (dft_proto_cap->vht_su_bfme) ? _TRUE : _FALSE; + + mu_bfer = (dft_proto_cap->vht_mu_bfmr) ? _TRUE : _FALSE; + mu_bfee = (dft_proto_cap->vht_mu_bfme) ? _TRUE : _FALSE; + + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { +#ifdef CONFIG_CONCURRENT_MODE + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) + && (_TRUE == mu_bfer)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO AP\n"); + } + pvhtpriv->num_snd_dim = dft_proto_cap->num_snd_dim; + } else + RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); #else - if ((MLME_IS_AP(padapter) && !MLME_IS_GO(padapter)) || - (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter))) + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + RTW_INFO("[VHT] Support Beamformer\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) + && (_TRUE == mu_bfer) + && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO AP\n"); + } #endif + } + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + RTW_INFO("[VHT] Support Beamformee\n"); + pvhtpriv->bfme_sts = dft_proto_cap->bfme_sts; + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) + && (_TRUE == mu_bfee) + && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } + } + } +#endif /* CONFIG_BEAMFORMING */ + + /* We don't support these features, and PHL doesn't define */ + pvhtpriv->txop_ps = 0; + pvhtpriv->htc_vht = 1; + pvhtpriv->link_adap_cap = 0; + pvhtpriv->tx_ant_pattern= 0; + pvhtpriv->rx_ant_pattern= 0; + pvhtpriv->ext_nss_bw = 0; + + pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor; + pvhtpriv->max_mpdu_len = dft_proto_cap->max_amsdu_len; + + tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); + + /* for now, vhtpriv.vht_mcs_map comes from RX NSS */ + rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map); + pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); +} + +/* Initialized vhtpriv by adapter real setting */ +void rtw_vht_get_real_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; +#ifdef CONFIG_BEAMFORMING + BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; + u8 mu_bfer, mu_bfee; +#endif /* CONFIG_BEAMFORMING */ + u8 tx_nss, rx_nss; + u8 rf_type = 0; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_cap = &(wrole->proto_role_cap); + struct role_cap_t *cap = &(wrole->cap); + + /* Short GI */ + pvhtpriv->sgi_80m = ((proto_cap->sgi_80) + && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_80M) + && TEST_FLAG(pregistrypriv->short_gi, BIT2)); + + pvhtpriv->sgi_160m = ((proto_cap->sgi_160) + && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_160M) + && TEST_FLAG(pregistrypriv->short_gi, BIT3)); + + /* LDPC support */ + if (proto_cap->vht_ldpc) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX); + + if (cap->tx_vht_ldpc) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX); + + if (pvhtpriv->ldpc_cap) + RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap); + + /* STBC */ + if (proto_cap->stbc_vht_tx) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX); + + if (proto_cap->stbc_vht_rx) { + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX); + pvhtpriv->rx_stbc_nss = proto_cap->stbc_vht_rx; + } + + if (pvhtpriv->stbc_cap) + RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap); + + /* Beamforming setting */ + CLEAR_FLAGS(pvhtpriv->beamform_cap); +#ifdef CONFIG_BEAMFORMING + if (proto_cap->vht_su_bfmr) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + RTW_INFO("[VHT] HAL Support Beamformer\n"); + if (proto_cap->vht_mu_bfmr) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO AP\n"); + } + } + + if (proto_cap->vht_su_bfme) { + u8 bfme_sts = 0; + + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&bfme_sts); + pvhtpriv->bfme_sts = bfme_sts; + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + RTW_INFO("[VHT] HAL Support Beamformee\n"); + if (proto_cap->vht_mu_bfme) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } + } #endif + +/* ToDo: check bfee flow will move change role type and modify wifi_role->proto_role_cap */ +#if 0 +#ifdef CONFIG_BEAMFORMING + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) { rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); @@ -292,6 +435,8 @@ void rtw_vht_use_default_setting(_adapter *padapter) if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { #ifdef CONFIG_CONCURRENT_MODE if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + u8 num_snd_dim = 0; + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) @@ -299,6 +444,8 @@ void rtw_vht_use_default_setting(_adapter *padapter) SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); RTW_INFO("[VHT] Support MU-MIMO AP\n"); } + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&num_snd_dim); + pvhtpriv->num_snd_dim = num_snd_dim; } else RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); #else @@ -313,8 +460,12 @@ void rtw_vht_use_default_setting(_adapter *padapter) #endif } if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { + u8 bfme_sts = 0; + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); RTW_INFO("[VHT] Support Beamformee\n"); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&bfme_sts); + pvhtpriv->bfme_sts = bfme_sts; if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) && (_TRUE == mu_bfee) && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { @@ -324,11 +475,21 @@ void rtw_vht_use_default_setting(_adapter *padapter) } } #endif /* CONFIG_BEAMFORMING */ +#endif + + /* We don't support these features, and PHL doesn't define */ + pvhtpriv->txop_ps = 0; + pvhtpriv->htc_vht = 1; + pvhtpriv->link_adap_cap = 0; + pvhtpriv->tx_ant_pattern= 0; + pvhtpriv->rx_ant_pattern= 0; + pvhtpriv->ext_nss_bw = 0; pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor; + pvhtpriv->max_mpdu_len = proto_cap->max_amsdu_len; - tx_nss = GET_HAL_TX_NSS(padapter); - rx_nss = GET_HAL_RX_NSS(padapter); + tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); /* for now, vhtpriv.vht_mcs_map comes from RX NSS */ rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map); @@ -347,13 +508,13 @@ u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss) switch (tmp) { case 2: - bitmap = bitmap | ((u64)0x03ff << j); + bitmap = bitmap | (0x03ff << j); break; case 1: - bitmap = bitmap | ((u64)0x01ff << j); + bitmap = bitmap | (0x01ff << j); break; case 0: - bitmap = bitmap | ((u64)0x00ff << j); + bitmap = bitmap | (0x00ff << j); break; default: break; @@ -391,10 +552,14 @@ void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta } if (cur_beamform_cap) - RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap); + RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->phl_sta->aid, cur_beamform_cap); pvhtpriv_sta->beamform_cap = cur_beamform_cap; - psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap; + + /* ToDo: need to API to inform hal_sta->bf_info.vht_beamform_cap */ + #if 0 + psta->phl_sta->bf_info.vht_beamform_cap = cur_beamform_cap; + #endif } #endif @@ -405,6 +570,9 @@ void update_sta_vht_info_apmode(_adapter *padapter, void *sta) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; + struct rtw_phl_stainfo_t *phl_sta = psta->phl_sta; + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_role_cap = &(wrole->proto_role_cap); u8 cur_ldpc_cap = 0, cur_stbc_cap = 0; s8 bw_mode = -1; u8 *pcap_mcs; @@ -431,26 +599,27 @@ void update_sta_vht_info_apmode(_adapter *padapter, void *sta) } if (bw_mode != -1) - psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */ + psta->phl_sta->chandef.bw = bw_mode; /* update bw_mode only if get value from VHT IEs */ - psta->cmn.ra_info.is_vht_enable = _TRUE; + /* ToDo: need to API to inform hal_sta->ra_info.is_vht_enable */ + /* psta->phl_sta->ra_info.is_vht_enable = _TRUE; */ /* B4 Rx LDPC */ if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap); + RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->phl_sta->aid, cur_ldpc_cap); } pvhtpriv_sta->ldpc_cap = cur_ldpc_cap; - if (psta->cmn.bw_mode > pmlmeext->cur_bwmode) - psta->cmn.bw_mode = pmlmeext->cur_bwmode; + if (psta->phl_sta->chandef.bw > pmlmeext->chandef.bw) + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; - if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) { + if (psta->phl_sta->chandef.bw == CHANNEL_WIDTH_80) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */ - } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) { + } else if (psta->phl_sta->chandef.bw >= CHANNEL_WIDTH_160) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */ @@ -460,9 +629,14 @@ void update_sta_vht_info_apmode(_adapter *padapter, void *sta) if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap); + RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->phl_sta->aid, cur_stbc_cap); + phl_sta->asoc_cap.stbc_vht_rx = + proto_role_cap->stbc_vht_tx ? + GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap) : 0; } pvhtpriv_sta->stbc_cap = cur_stbc_cap; + phl_sta->asoc_cap.stbc_vht_tx = + GET_VHT_CAPABILITY_ELE_TX_STBC(pvhtpriv_sta->vht_cap); #ifdef CONFIG_BEAMFORMING update_sta_vht_info_apmode_bf_cap(padapter, psta); @@ -569,10 +743,16 @@ void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct rtw_phl_stainfo_t *phl_sta = NULL; + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_role_cap = &(wrole->proto_role_cap); u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rx_nss = 0; u16 cur_beamform_cap = 0; u8 *pcap_mcs; @@ -583,6 +763,11 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) if (pvhtpriv->vht_option == _FALSE) return; + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta == NULL) + return; + phl_sta = psta->phl_sta; + pmlmeinfo->VHT_enable = 1; /* B4 Rx LDPC */ @@ -590,6 +775,7 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) { SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap); + phl_sta->asoc_cap.vht_ldpc = 1; } pvhtpriv->ldpc_cap = cur_ldpc_cap; @@ -602,10 +788,27 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) { SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap); + phl_sta->asoc_cap.stbc_vht_rx = + proto_role_cap->stbc_vht_tx ? + GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data) : 0; } pvhtpriv->stbc_cap = cur_stbc_cap; + phl_sta->asoc_cap.stbc_vht_tx = GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data); + + phl_sta->asoc_cap.vht_su_bfmr = GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data); + phl_sta->asoc_cap.vht_su_bfme = GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data); + phl_sta->asoc_cap.vht_mu_bfmr = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data); + phl_sta->asoc_cap.bfme_sts = GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data); + phl_sta->asoc_cap.num_snd_dim = GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data); + + RTW_INFO("%s: VHT STA assoc_cap:\n", __func__); + RTW_INFO("- SU BFer: %d\n", phl_sta->asoc_cap.vht_su_bfmr); + RTW_INFO("- SU BFee: %d\n", phl_sta->asoc_cap.vht_su_bfme); + RTW_INFO("- MU BFer: %d\n", phl_sta->asoc_cap.vht_mu_bfmr); + RTW_INFO("- BFee STS: %d\n", phl_sta->asoc_cap.bfme_sts); + RTW_INFO("- BFer SND DIM number: %d\n", phl_sta->asoc_cap.num_snd_dim); + #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 /* * B11 SU Beamformer Capable, * the target supports Beamformer and we are Beamformee @@ -648,33 +851,15 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) pvhtpriv->beamform_cap = cur_beamform_cap; RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap); -#else /* !RTW_BEAMFORMING_VERSION_2 */ - /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ - if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); - /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8); - } - - /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ - if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12); - - } - pvhtpriv->beamform_cap = cur_beamform_cap; - if (cur_beamform_cap) - RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); -#endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif /* CONFIG_BEAMFORMING */ + + /* B0 B1 Maximum MPDU Length */ + pvhtpriv->max_mpdu_len = GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pIE->data); /* B23 B24 B25 Maximum A-MPDU Length Exponent */ pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data); pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data); - rx_nss = GET_HAL_RX_NSS(padapter); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pcap_mcs); pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); } @@ -689,6 +874,15 @@ void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) if (pvhtpriv->vht_option == _FALSE) return; + + if (pIE->Length != VHT_OP_IE_LEN) { + RTW_WARN("%s: unexpected IE length(%u)!\n", + __func__, pIE->Length); + } + + pvhtpriv->op_present = 1; + _rtw_memcpy(pvhtpriv->vht_op, pIE->data, + pIE->Length > VHT_OP_IE_LEN ? VHT_OP_IE_LEN : pIE->Length); } void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta) @@ -706,15 +900,15 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta) return; target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe); - tx_nss = GET_HAL_TX_NSS(padapter); + tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1)); - if (target_bw != psta->cmn.bw_mode) { - if (hal_is_bw_support(padapter, target_bw) + if (target_bw != psta->phl_sta->chandef.bw) { + if (rtw_hw_is_bw_support(adapter_to_dvobj(padapter), target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) ) { update_ra = _TRUE; - psta->cmn.bw_mode = target_bw; + psta->phl_sta->chandef.bw = target_bw; } } @@ -727,11 +921,18 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta) rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); - rtw_hal_update_sta_ra_info(padapter, psta); + update_sta_ra_info(padapter, psta); } - if (update_ra) - rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + if (update_ra) { + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(padapter)->phl, + psta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_NO_WAIT, + 0); + } } u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) @@ -748,10 +949,10 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */ - if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M) + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_80M | BW_CAP_160M) && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80 ) { - center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER); + center_freq = rtw_phl_get_center_ch(channel, get_highest_bw_cap(bw_mode), CHAN_OFFSET_UPPER); ChnlWidth = 1; } else { center_freq = 0; @@ -796,44 +997,35 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw) u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) { - u8 bw, rf_num, rx_stbc_nss = 0; - u16 HighestRate; - u8 *pcap, *pcap_mcs; - u32 len = 0; - u32 rx_packet_offset, max_recvbuf_sz; + u8 bw; + u16 HighestRate; + u8 *pcap, *pcap_mcs; + u32 len = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); pcap = pvhtpriv->vht_cap; _rtw_memset(pcap, 0, 32); + /* + * VHT Capabilities Information field : B0 to B31 + */ + /* B0 B1 Maximum MPDU Length */ - rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); - rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); - - RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset); - - if ((max_recvbuf_sz - rx_packet_offset) >= 11454) { - SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2); - RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__); - } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) { - SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1); - RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__); - } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) { - SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0); - RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__); - } else - RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__); + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, pvhtpriv->max_mpdu_len); /* B2 B3 Supported Channel Width Set */ - if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) { - if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80)) + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) { + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80)) { SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2); - else + RTW_INFO("[VHT] Declare supporting 160MHz and 80+80MHz\n"); + } else { SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1); + RTW_INFO("[VHT] Declare supporting 160MHz\n"); + } } else SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); @@ -844,12 +1036,15 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) } /* B5 ShortGI for 80MHz */ - SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */ + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); if (pvhtpriv->sgi_80m) RTW_INFO("[VHT] Declare supporting SGI 80MHz\n"); - /* B6 ShortGI for 160MHz */ - /* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */ + /* B6 Short GI for 160 and 80+80 MHz */ + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_160m ? 1 : 0); + if (pvhtpriv->sgi_160m) { + RTW_INFO("[VHT] Declare supporting SGI 160MHz and 80+80MHz\n"); + } /* B7 Tx STBC */ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) { @@ -859,62 +1054,88 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) /* B8 B9 B10 Rx STBC */ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) { - rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); - - SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); - RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss); + SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, pvhtpriv->rx_stbc_nss); + RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", pvhtpriv->rx_stbc_nss); } + #ifdef CONFIG_BEAMFORMING /* B11 SU Beamformer Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); - RTW_INFO("[VHT] Declare supporting SU Bfer\n"); + RTW_INFO("[VHT] Declare supporting SU Beamformer\n"); /* B16 17 18 Number of Sounding Dimensions */ - rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); - SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num); + SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, pvhtpriv->num_snd_dim); /* B19 MU Beamformer Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1); - RTW_INFO("[VHT] Declare supporting MU Bfer\n"); + RTW_INFO("[VHT] Declare supporting MU Beamformer\n"); } } /* B12 SU Beamformee Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { - SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); - RTW_INFO("[VHT] Declare supporting SU Bfee\n"); + u8 bfme_sts = pvhtpriv->bfme_sts; - rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); + RTW_INFO("[VHT] Declare supporting SU Beamformee\n"); /* IOT action suggested by Yu Chen 2017/3/3 */ -#ifdef CONFIG_80211AC_VHT if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && !pvhtpriv->ap_bf_cap.is_mu_bfer && pvhtpriv->ap_bf_cap.su_sound_dim == 2) - rf_num = (rf_num >= 2 ? 2 : rf_num); -#endif - /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ - SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num); - /* B20 SU Beamformee Capable */ + bfme_sts = (bfme_sts >= 2 ? 2 : bfme_sts); + + /* B13 14 15 Beamformee STS Capability */ + SET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pcap, bfme_sts); + + /* B20 MU Beamformee Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1); - RTW_INFO("[VHT] Declare supporting MU Bfee\n"); + RTW_INFO("[VHT] Declare supporting MU Beamformee\n"); } } #endif/*CONFIG_BEAMFORMING*/ /* B21 VHT TXOP PS */ - SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0); + if (pvhtpriv->txop_ps) { + SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 1); + RTW_INFO("[VHT] Declare supporting VHT TXOP power save\n"); + } + /* B22 +HTC-VHT Capable */ - SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1); + if (pvhtpriv->htc_vht) { + SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1); + RTW_INFO("[VHT] Declare supporting VHT variant HT Control\n"); + } + /* B23 24 25 Maximum A-MPDU Length Exponent */ - if (pregistrypriv->ampdu_factor != 0xFE) - SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor); - else - SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7); + SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pvhtpriv->ampdu_len); + RTW_INFO("[VHT] Declare supporting RX A-MPDU Length Exponent = %u\n", pvhtpriv->ampdu_len); + /* B26 27 VHT Link Adaptation Capable */ - SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0); + if (pvhtpriv->link_adap_cap) { + SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 1); + RTW_INFO("[VHT] Declare supporting link adaptation using VHT variant HT Control\n"); + } + + /* B28 Rx Antenna Pattern Consistency */ + if (pvhtpriv->rx_ant_pattern) { + SET_VHT_CAPABILITY_ELE_RX_ANT_PATTERN(pcap, 1); + RTW_INFO("[VHT] Declare supporting RX Antenna Pattern Consistency\n"); + } + + /* B29 Tx Antenna Pattern Consistency */ + if (pvhtpriv->tx_ant_pattern) { + SET_VHT_CAPABILITY_ELE_TX_ANT_PATTERN(pcap, 1); + RTW_INFO("[VHT] Declare supporting TX Antenna Pattern Consistency\n"); + } + /* B30 B31 Extended NSS BW Support */ + SET_VHT_CAPABILITY_ELE_EXT_NSS_BW(pcap, pvhtpriv->ext_nss_bw); + + /* + * Supported VHT-MCS and NSS Set : 8 bytes + */ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap); _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); @@ -922,7 +1143,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); /* find the largest bw supported by both registry and hal */ - bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + bw = rtw_hw_largest_bw(adapter_to_dvobj(padapter), REGSTY_BW_5G(pregistrypriv)); HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)]; HighestRate = (HighestRate + 1) >> 1; @@ -935,19 +1156,19 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) return len; } -u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan) { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); RT_CHANNEL_INFO *chset = rfctl->channel_set; u32 ielen; u8 max_bw; - u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = CHAN_OFFSET_NO_EXT; u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - rtw_vht_use_default_setting(padapter); + rtw_vht_get_real_setting(padapter); ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12); if (!ht_op_ie || ielen != HT_OP_IE_LEN) @@ -971,19 +1192,19 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2); /* find the largest bw supported by both registry and hal */ - max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + max_bw = rtw_hw_largest_bw(adapter_to_dvobj(padapter), REGSTY_BW_5G(pregistrypriv)); if (max_bw >= CHANNEL_WIDTH_40) { /* get bw offset form HT_OP_IE */ if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) { switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { - case SCA: + case IEEE80211_SCA: oper_bw = CHANNEL_WIDTH_40; - oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + oper_offset = CHAN_OFFSET_UPPER; break; - case SCB: + case IEEE80211_SCB: oper_bw = CHANNEL_WIDTH_40; - oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + oper_offset = CHAN_OFFSET_LOWER; break; } } @@ -1000,21 +1221,23 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le oper_bw = rtw_min(oper_bw, max_bw); /* try downgrage bw to fit in channel plan setting */ - while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1) + while ((req_chplan && !rtw_country_chplan_is_chbw_valid(req_chplan, BAND_ON_5G, oper_ch, oper_bw, oper_offset, 1, 1, pregistrypriv)) + || (!req_chplan && !rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1)) || (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset)) ) { oper_bw--; if (oper_bw == CHANNEL_WIDTH_20) { - oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + oper_offset = CHAN_OFFSET_NO_EXT; break; } } } } - rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1)); + rtw_warn_on(req_chplan && !rtw_country_chplan_is_chbw_valid(req_chplan, BAND_ON_5G, oper_ch, oper_bw, oper_offset, 1, 1, pregistrypriv)); + rtw_warn_on(!req_chplan && !rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1)); if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl)) rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset)); @@ -1024,7 +1247,7 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0); } else if (oper_bw == CHANNEL_WIDTH_80) { - u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset); + u8 cch = rtw_phl_get_center_ch(oper_ch, oper_bw, oper_offset); SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1); SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch); @@ -1068,7 +1291,6 @@ void VHTOnAssocRsp(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate)); } -#ifdef CONFIG_AP_MODE void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -1082,13 +1304,12 @@ void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) if (p && ie_len > 0) return; - rtw_vht_use_default_setting(padapter); + rtw_vht_get_real_setting(padapter); /* VHT Operation mode notifiy bit in Extended IE (127) */ - SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); - pmlmepriv->ext_capab_ie_len = 10; - rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); - pnetwork->IELength += pmlmepriv->ext_capab_ie_len; + rtw_add_ext_cap_info(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), OP_MODE_NOTIFICATION); + rtw_update_ext_cap_ie(pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len, pnetwork->IEs \ + , &(pnetwork->IELength), _BEACON_IE_OFFSET_); /* VHT Capabilities element */ cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength); @@ -1108,9 +1329,13 @@ void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability); + rtw_remove_ext_cap_info(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), OP_MODE_NOTIFICATION); + rtw_update_ext_cap_ie(pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len, pnetwork->IEs \ + , &(pnetwork->IELength), _BEACON_IE_OFFSET_); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability); rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTTransmitPower); pmlmepriv->vhtpriv.vht_option = _FALSE; } @@ -1137,5 +1362,76 @@ void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len) } } } -#endif /* CONFIG_AP_MODE */ + +/* We need to update the (mlmepriv->vhtpriv) */ +void rtw_update_drv_vht_cap(_adapter *padapter, u8 *vht_cap_ie) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct vht_priv *pvhtpriv = &(pmlmepriv->vhtpriv); + struct registry_priv *pregpriv = &padapter->registrypriv; + s32 ie_len = 0; + u32 rx_packet_offset, max_recvbuf_sz, available_mpdu_sz; + u8 cap_val; + u8 *pvht_cap; + + /* Initialize VHT capability element */ + rtw_vht_get_real_setting(padapter); + + RTW_INFO("Don't setting VHT capability IE from hostap, builded by driver temporarily\n"); + rtw_build_vht_cap_ie(padapter, vht_cap_ie); +} + +void rtw_check_vht_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct vht_priv *pvhtpriv = &(pmlmepriv->vhtpriv); + u32 ie_len; + u32 ies_len = pnetwork->IELength - _BEACON_IE_OFFSET_; + u8 *ies = pnetwork->IEs + _BEACON_IE_OFFSET_; + u8 *vht_cap_ie, *vht_op_ie; + + vht_cap_ie = rtw_get_ie(ies, EID_VHTCapability, &ie_len, ies_len); + + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &ie_len, ies_len); + + rtw_update_drv_vht_cap(padapter, vht_cap_ie); + + rtw_add_ext_cap_info(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), OP_MODE_NOTIFICATION); + rtw_update_ext_cap_ie(pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len, pnetwork->IEs \ + , &(pnetwork->IELength), _BEACON_IE_OFFSET_); + + /* Backup these two VHT IEs from hostapd/wpa_supplicant for restore usage */ + if (vht_cap_ie != NULL) + _rtw_memcpy(pvhtpriv->vht_cap_ie_backup, vht_cap_ie + 2, VHT_CAP_IE_LEN); + + if (vht_op_ie != NULL) + _rtw_memcpy(pvhtpriv->vht_op_ie_backup, vht_op_ie + 2, VHT_OP_IE_LEN); + + /* TODO : We don't handle this IE like before, so remove it */ + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTTransmitPower); +} + +void rtw_reattach_vht_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct vht_priv *pvhtpriv = &(pmlmepriv->vhtpriv); + u8 *vht_cap_ie = pnetwork->IEs + pnetwork->IELength; + u8 *vht_op_ie; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + if (pnetwork->IEs != NULL) { + vht_op_ie = rtw_set_ie(vht_cap_ie, EID_VHTCapability, VHT_CAP_IE_LEN, + pvhtpriv->vht_cap_ie_backup, &(pnetwork->IELength)); + + rtw_set_ie(vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, + pvhtpriv->vht_op_ie_backup, &(pnetwork->IELength)); + + rtw_add_ext_cap_info(pmlmepriv->ext_capab_ie_data, &(pmlmepriv->ext_capab_ie_len), OP_MODE_NOTIFICATION); + rtw_update_ext_cap_ie(pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len, pnetwork->IEs \ + , &(pnetwork->IELength), _BEACON_IE_OFFSET_); + } + + pmlmepriv->vhtpriv.vht_option = _TRUE; +} #endif /* CONFIG_80211AC_VHT */ diff --git a/core/rtw_wapi.c b/core/rtw_wapi.c index 94b26e7..cd8e6b1 100644 --- a/core/rtw_wapi.c +++ b/core/rtw_wapi.c @@ -70,40 +70,40 @@ void WapiSetIE(_adapter *padapter) pWapiInfo->wapiIELength = 0; /* protocol version */ - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2); pWapiInfo->wapiIELength += 2; /* akm */ - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2); pWapiInfo->wapiIELength += 2; if (pWapiInfo->bWapiPSK) { - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); pWapiInfo->wapiIELength += 3; pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2; pWapiInfo->wapiIELength += 1; } else { - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); pWapiInfo->wapiIELength += 3; pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; pWapiInfo->wapiIELength += 1; } /* usk */ - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2); pWapiInfo->wapiIELength += 2; - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); pWapiInfo->wapiIELength += 3; pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; pWapiInfo->wapiIELength += 1; /* msk */ - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3); pWapiInfo->wapiIELength += 3; pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; pWapiInfo->wapiIELength += 1; /* Capbility */ - memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2); + _rtw_memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2); pWapiInfo->wapiIELength += 2; } @@ -683,7 +683,7 @@ void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr) return; } - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + if (MLME_IS_STA(padapter)) { while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) { pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); list_del_init(&pWapiBkid->list); @@ -748,7 +748,7 @@ void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr) pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]); list_del_init(&pWapiStaInfo->list); - memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN); + _rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN); pWapiStaInfo->bSetkeyOk = 0; list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); } @@ -777,7 +777,7 @@ void rtw_wapi_return_all_sta_info(_adapter *padapter) while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) { pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list); list_del_init(&pWapiStaInfo->list); - memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN); + _rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN); pWapiStaInfo->bSetkeyOk = 0; list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); } @@ -786,18 +786,18 @@ void rtw_wapi_return_all_sta_info(_adapter *padapter) while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) { pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); list_del_init(&pWapiBkid->list); - memset(pWapiBkid->bkid, 0, 16); + _rtw_memset(pWapiBkid->bkid, 0, 16); list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList); } WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); } void CAM_empty_entry( - PADAPTER Adapter, + _adapter *adapter, u8 ucIndex ) { - rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex)); + rtw_hal_set_hwreg(adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex)); } void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr) @@ -813,19 +813,19 @@ void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr) UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0); if (UcIndex != 0xff) { - /* CAM_mark_invalid(Adapter, UcIndex); */ + /* CAM_mark_invalid(adapter, UcIndex); */ CAM_empty_entry(padapter, UcIndex); } UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0); if (UcIndex != 0xff) { - /* CAM_mark_invalid(Adapter, UcIndex); */ + /* CAM_mark_invalid(adapter, UcIndex); */ CAM_empty_entry(padapter, UcIndex); } UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1); if (UcIndex != 0xff) { - /* CAM_mark_invalid(Adapter, UcIndex); */ + /* CAM_mark_invalid(adapter, UcIndex); */ CAM_empty_entry(padapter, UcIndex); } @@ -850,16 +850,18 @@ void rtw_wapi_clear_all_cam_entry(_adapter *padapter) invalidate_cam_all(padapter); /* is this ok? */ WapiResetAllCamEntry(padapter); - WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + WAPI_TRACE(WAPI_API, "<=========== %s\n", __FUNCTION__); } -void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey) +void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey) { + struct setkey_parm *psetkeyparm; + struct set_stakey_parm *psetstakeyparm; PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; - u8 *pMacAddr = pWapiSta->PeerMacAddr; + u8 *pMacAddr = pWapiSta->PeerMacAddr; u32 EntryId = 0; BOOLEAN IsPairWise = false ; - u8 EncAlgo; + u8 keylen; WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); @@ -868,51 +870,43 @@ void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INF return; } - EncAlgo = _SMS4_; - - /* For Tx bc/mc pkt,use defualt key entry */ - if (bUseDefaultKey) { - /* when WAPI update key, keyid will be 0 or 1 by turns. */ - if (pWapiKey->keyId == 0) - EntryId = 0; - else - EntryId = 2; - } else { - /* tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr */ - EntryId = WapiGetEntryForCamWrite(padapter, pMacAddr, pWapiKey->keyId, bGroupKey); - } - - if (EntryId == 0xff) { - WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n"); + psetstakeyparm = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (NULL == psetstakeyparm) { + WAPI_TRACE(WAPI_API, "<========== new %s, could not zmalloc psetstakeyparm at line %d\n", __FUNCTION__, __LINE__); return; } + psetstakeyparm->algorithm = _SMS4_; + keylen = 16; + + _rtw_memcpy(psetstakeyparm->addr, pMacAddr, ETH_ALEN); + _rtw_memcpy(&(psetstakeyparm->key[0]), &pWapiKey->dataKey, keylen); + _rtw_memcpy(&(psetstakeyparm->key[16]), &pWapiKey->micKey, keylen); + psetstakeyparm->keyid = pWapiKey->keyId; + + if(bGroupKey) { + /* Group Key */ + psetstakeyparm->gk = 1; + WAPI_TRACE(WAPI_API, "new %s: group keyid = %d, gk = %d, algorithm = %d\n", __FUNCTION__, psetstakeyparm->keyid, psetstakeyparm->gk, psetstakeyparm->algorithm); + } else { + /* Pairwise Key */ + psetstakeyparm->gk = 0; + WAPI_TRACE(WAPI_API, "new %s: pairwise keyid = %d, gk = %d, algorithm = %d\n", __FUNCTION__, psetstakeyparm->keyid, psetstakeyparm->gk, psetstakeyparm->algorithm); + } - /* EntryId is also used to diff Sec key and Mic key */ - /* Sec Key */ - WapiWriteOneCamEntry(padapter, - pMacAddr, - pWapiKey->keyId, /* keyid */ - EntryId, /* entry */ - EncAlgo, /* type */ - bGroupKey, /* pairwise or group key */ - pWapiKey->dataKey); - /* MIC key */ - WapiWriteOneCamEntry(padapter, - pMacAddr, - pWapiKey->keyId, /* keyid */ - EntryId + 1, /* entry */ - EncAlgo, /* type */ - bGroupKey, /* pairwise or group key */ - pWapiKey->micKey); - + WAPI_DATA(WAPI_API, "new %s: ", psetstakeyparm->key, 32); +#ifdef CONFIG_CMD_DISP + set_stakey_hdl(padapter, psetstakeyparm, PHL_CMD_DIRECTLY, 0); +#else + set_stakey_hdl(padapter, (u8 *)psetstakeyparm); +#endif + rtw_mfree((u8 *) psetstakeyparm, sizeof(struct setkey_parm)); WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n", pWapiKey->keyId, EntryId, !bGroupKey); - WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); - + WAPI_TRACE(WAPI_API, "<=========== %s\n", __FUNCTION__); } #if 0 /* YJ,test,091013 */ -void wapi_test_set_key(struct _adapter *padapter, u8 *buf) +void wapi_test_set_key(_adapter *padapter, u8 *buf) { /*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; @@ -936,29 +930,29 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) bTxEnable = data[1]; bAuthenticator = data[2]; bUpdate = data[3]; - memcpy(PeerAddr, data + 4, 6); + _rtw_memcpy(PeerAddr, data + 4, 6); if (data[0] == 0x3) { if (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) { pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list); list_del_init(&pWapiBkid->list); - memcpy(pWapiBkid->bkid, data + 10, 16); + _rtw_memcpy(pWapiBkid->bkid, data + 10, 16); WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16); list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList); } } else { list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (!memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) { pWapiSta->bAuthenticatorInUpdata = false; switch (data[0]) { case 1: /* usk */ if (bAuthenticator) { /* authenticator */ - memcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16); if (!bUpdate) { /* first */ WAPI_TRACE(WAPI_INIT, "AE fisrt set usk\n"); pWapiSta->wapiUsk.bSet = true; - memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16); pWapiSta->wapiUsk.keyId = *(data + 42); pWapiSta->wapiUsk.bTxEnable = true; WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16); @@ -967,13 +961,13 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) WAPI_TRACE(WAPI_INIT, "AE update usk\n"); pWapiSta->wapiUskUpdate.bSet = true; pWapiSta->bAuthenticatorInUpdata = true; - memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16); - memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16); pWapiSta->wapiUskUpdate.keyId = *(data + 42); pWapiSta->wapiUskUpdate.bTxEnable = true; } @@ -982,11 +976,11 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) WAPI_TRACE(WAPI_INIT, "ASUE fisrt set usk\n"); if (bTxEnable) { pWapiSta->wapiUsk.bTxEnable = true; - memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); } else { pWapiSta->wapiUsk.bSet = true; - memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16); pWapiSta->wapiUsk.keyId = *(data + 42); pWapiSta->wapiUsk.bTxEnable = false; } @@ -995,22 +989,22 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) if (bTxEnable) { pWapiSta->wapiUskUpdate.bTxEnable = true; if (pWapiSta->wapiUskUpdate.bSet) { - memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); - memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId; - memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16); - memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16); pWapiSta->wapiUskUpdate.bTxEnable = false; pWapiSta->wapiUskUpdate.bSet = false; } - memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); } else { pWapiSta->wapiUskUpdate.bSet = true; - memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16); pWapiSta->wapiUskUpdate.keyId = *(data + 42); pWapiSta->wapiUskUpdate.bTxEnable = false; } @@ -1020,11 +1014,11 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) case 2: /* msk */ if (bAuthenticator) { /* authenticator */ pWapiInfo->wapiTxMsk.bSet = true; - memcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16); - memcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16); + _rtw_memcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16); + _rtw_memcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16); pWapiInfo->wapiTxMsk.keyId = *(data + 42); pWapiInfo->wapiTxMsk.bTxEnable = true; - memcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + _rtw_memcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); if (!bUpdate) { /* first */ WAPI_TRACE(WAPI_INIT, "AE fisrt set msk\n"); @@ -1040,8 +1034,8 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) if (!bUpdate) { WAPI_TRACE(WAPI_INIT, "ASUE fisrt set msk\n"); pWapiSta->wapiMsk.bSet = true; - memcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiMsk.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey, data + 26, 16); pWapiSta->wapiMsk.keyId = *(data + 42); pWapiSta->wapiMsk.bTxEnable = false; if (!pWapiSta->bSetkeyOk) @@ -1052,8 +1046,8 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) } else { WAPI_TRACE(WAPI_INIT, "ASUE update msk\n"); pWapiSta->wapiMskUpdate.bSet = true; - memcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16); - memcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16); + _rtw_memcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16); + _rtw_memcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16); pWapiSta->wapiMskUpdate.keyId = *(data + 42); pWapiSta->wapiMskUpdate.bTxEnable = false; } @@ -1070,7 +1064,7 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) } -void wapi_test_init(struct _adapter *padapter) +void wapi_test_init(_adapter *padapter) { u8 keybuf[100]; u8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70}; @@ -1093,51 +1087,51 @@ void wapi_test_init(struct _adapter *padapter) /* set usk */ WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__); - memset(keybuf, 0, 100); + _rtw_memset(keybuf, 0, 100); keybuf[0] = 1; /* set usk */ keybuf[1] = 1; /* enable tx */ keybuf[2] = 1; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, ETH_ALEN); - memcpy(keybuf + 10, UskDataKey, 16); - memcpy(keybuf + 26, UskMicKey, 16); + _rtw_memcpy(keybuf + 4, mac_addr, ETH_ALEN); + _rtw_memcpy(keybuf + 10, UskDataKey, 16); + _rtw_memcpy(keybuf + 26, UskMicKey, 16); keybuf[42] = UskId; wapi_test_set_key(padapter, keybuf); - memset(keybuf, 0, 100); + _rtw_memset(keybuf, 0, 100); keybuf[0] = 1; /* set usk */ keybuf[1] = 1; /* enable tx */ keybuf[2] = 0; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, ETH_ALEN); - memcpy(keybuf + 10, UskDataKey, 16); - memcpy(keybuf + 26, UskMicKey, 16); + _rtw_memcpy(keybuf + 4, mac_addr, ETH_ALEN); + _rtw_memcpy(keybuf + 10, UskDataKey, 16); + _rtw_memcpy(keybuf + 26, UskMicKey, 16); keybuf[42] = UskId; wapi_test_set_key(padapter, keybuf); /* set msk */ WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__); - memset(keybuf, 0, 100); + _rtw_memset(keybuf, 0, 100); keybuf[0] = 2; /* set msk */ keybuf[1] = 1; /* Enable TX */ keybuf[2] = 1; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, ETH_ALEN); - memcpy(keybuf + 10, MskDataKey, 16); - memcpy(keybuf + 26, MskMicKey, 16); + _rtw_memcpy(keybuf + 4, mac_addr, ETH_ALEN); + _rtw_memcpy(keybuf + 10, MskDataKey, 16); + _rtw_memcpy(keybuf + 26, MskMicKey, 16); keybuf[42] = MskId; wapi_test_set_key(padapter, keybuf); - memset(keybuf, 0, 100); + _rtw_memset(keybuf, 0, 100); keybuf[0] = 2; /* set msk */ keybuf[1] = 1; /* Enable TX */ keybuf[2] = 0; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, ETH_ALEN); - memcpy(keybuf + 10, MskDataKey, 16); - memcpy(keybuf + 26, MskMicKey, 16); + _rtw_memcpy(keybuf + 4, mac_addr, ETH_ALEN); + _rtw_memcpy(keybuf + 10, MskDataKey, 16); + _rtw_memcpy(keybuf + 26, MskMicKey, 16); keybuf[42] = MskId; wapi_test_set_key(padapter, keybuf); WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__); @@ -1166,7 +1160,7 @@ void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV) pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; pWapiExt->Reserved = 0; bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); - memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); + _rtw_memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); } } else { if (list_empty(&pWapiInfo->wapiSTAUsedList)) { @@ -1278,7 +1272,8 @@ void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) pWapiSta->wapiUsk.bSet = true; _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiUsk.keyId = param->u.crypt.idx; + psecuritypriv->dot11PrivacyKeyIndex = param->u.crypt.idx; pWapiSta->wapiUsk.bTxEnable = true; _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); @@ -1291,7 +1286,7 @@ void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { /* set unicast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); + rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false); } } } @@ -1301,7 +1296,8 @@ void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) pWapiSta->wapiMsk.bSet = true; _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiMsk.keyId = param->u.crypt.idx; + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; pWapiSta->wapiMsk.bTxEnable = false; if (!pWapiSta->bSetkeyOk) pWapiSta->bSetkeyOk = true; @@ -1311,7 +1307,7 @@ void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) if (psecuritypriv->sw_decrypt == false) { /* set rx broadcast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); + rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true); } } } diff --git a/core/rtw_wapi_sms4.c b/core/rtw_wapi_sms4.c index 4b7cf95..4d3a120 100644 --- a/core/rtw_wapi_sms4.c +++ b/core/rtw_wapi_sms4.c @@ -195,14 +195,14 @@ void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength, for (k = 0; k < 16; k++) tempIV[k] = IV[15 - k]; - memcpy(blockIn, tempIV, 16); + _rtw_memcpy(blockIn, tempIV, 16); SMS4KeyExt((u8 *)Key, rk, CryptFlag); for (i = 0; i < blockNum - 1; i++) { SMS4Crypt((u8 *)blockIn, blockOut, rk); xor_block(&Output[i * 16], &Input[i * 16], blockOut); - memcpy(blockIn, blockOut, 16); + _rtw_memcpy(blockIn, blockOut, 16); } *OutputLength = i * 16; @@ -242,7 +242,7 @@ void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length, for (k = 0; k < 16; k++) tempIV[k] = IV[15 - k]; - memcpy(BlockIn, tempIV, 16); + _rtw_memcpy(BlockIn, tempIV, 16); SMS4KeyExt((u8 *)Key, rk, ENCRYPT); @@ -254,8 +254,8 @@ void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length, } if (remainder != 0) { - memset(TempBlock, 0, 16); - memcpy(TempBlock, (Input1 + blockNum * 16), remainder); + _rtw_memset(TempBlock, 0, 16); + _rtw_memcpy(TempBlock, (Input1 + blockNum * 16), remainder); xor_block(BlockIn, TempBlock, BlockOut); SMS4Crypt((u8 *)BlockIn, BlockOut, rk); @@ -270,14 +270,14 @@ void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length, } if (remainder != 0) { - memset(TempBlock, 0, 16); - memcpy(TempBlock, (Input2 + blockNum * 16), remainder); + _rtw_memset(TempBlock, 0, 16); + _rtw_memcpy(TempBlock, (Input2 + blockNum * 16), remainder); xor_block(BlockIn, TempBlock, BlockOut); SMS4Crypt((u8 *)BlockIn, BlockOut, rk); } - memcpy(Output, BlockOut, 16); + _rtw_memcpy(Output, BlockOut, 16); *OutputLength = 16; } @@ -298,32 +298,32 @@ void SecCalculateMicSMS4( WAPI_TRACE(WAPI_TX | WAPI_RX, "=========>%s\n", __FUNCTION__); header = (struct ieee80211_hdr_3addr_qos *)pHeader; - memset(TempBuf, 0, 34); - memcpy(TempBuf, pHeader, 2); /* FrameCtrl */ + _rtw_memset(TempBuf, 0, 34); + _rtw_memcpy(TempBuf, pHeader, 2); /* FrameCtrl */ pTemp = (u16 *)TempBuf; *pTemp &= 0xc78f; /* bit4,5,6,11,12,13 */ - memcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */ - memcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */ + _rtw_memcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */ + _rtw_memcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */ pTemp = (u16 *)(TempBuf + 14); *pTemp &= 0x000f; - memcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */ + _rtw_memcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */ fc = le16_to_cpu(header->frame_ctl); if (GetFrDs((u16 *)&fc) && GetToDs((u16 *)&fc)) { - memcpy((TempBuf + 22), (pHeader + 24), 6); + _rtw_memcpy((TempBuf + 22), (pHeader + 24), 6); QosOffset = 30; } else { - memset((TempBuf + 22), 0, 6); + _rtw_memset((TempBuf + 22), 0, 6); QosOffset = 24; } if ((fc & 0x0088) == 0x0088) { - memcpy((TempBuf + 28), (pHeader + QosOffset), 2); + _rtw_memcpy((TempBuf + 28), (pHeader + QosOffset), 2); TempLen += 2; /* IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; */ IV = pHeader + QosOffset + 2 + 2; @@ -399,19 +399,19 @@ void WapiGetLastRxUnicastPNForQoSData( switch (UserPriority) { case 0: case 3: - memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16); + _rtw_memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16); break; case 1: case 2: - memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16); + _rtw_memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16); break; case 4: case 5: - memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16); + _rtw_memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16); break; case 6: case 7: - memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16); + _rtw_memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16); break; default: WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__); @@ -431,19 +431,19 @@ void WapiSetLastRxUnicastPNForQoSData( switch (UserPriority) { case 0: case 3: - memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16); + _rtw_memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16); break; case 1: case 2: - memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16); + _rtw_memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16); break; case 4: case 5: - memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16); + _rtw_memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16); break; case 6: case 7: - memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16); + _rtw_memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16); break; default: WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__); @@ -532,7 +532,7 @@ int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe) pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; pWapiExt->Reserved = 0; bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); - memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); + _rtw_memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); if (bPNOverflow) { /* Update MSK Notification. */ WAPI_TRACE(WAPI_ERR, "===============>%s():multicast PN overflow\n", __FUNCTION__); @@ -544,7 +544,7 @@ int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe) } } else { list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (!memcmp(pWapiSta->PeerMacAddr, pRA, 6)) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) { bFindMatchPeer = true; break; } @@ -562,7 +562,7 @@ int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe) pWapiExt->Reserved = 0; bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2); - memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); + _rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); if (bPNOverflow) { /* Update USK Notification. */ WAPI_TRACE(WAPI_ERR, "===============>%s():unicast PN overflow\n", __FUNCTION__); @@ -618,7 +618,7 @@ void SecSWSMS4Encryption( } else { if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) { list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)) { + if (_TRUE == _rtw_memcmp(pWapiSta->PeerMacAddr, pRA, 6)) { bFindMatchPeer = true; break; } @@ -653,7 +653,7 @@ void SecSWSMS4Encryption( WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len); - memcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len, + _rtw_memcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len, (u8 *)MicBuffer, padapter->wapiInfo.extra_postfix_len ); @@ -716,7 +716,7 @@ u8 SecSWSMS4Decryption( if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) { list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)) { + if (_TRUE == _rtw_memcmp(pWapiSta->PeerMacAddr, pTA, 6)) { bFindMatchPeer = true; break; } @@ -739,13 +739,13 @@ u8 SecSWSMS4Decryption( return false; } - memcpy(pLastRxPN, pRecvPN, 16); + _rtw_memcpy(pLastRxPN, pRecvPN, 16); pMicKey = pWapiSta->wapiMsk.micKey; pDataKey = pWapiSta->wapiMsk.dataKey; } else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet) { WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__); bUseUpdatedKey = true; - memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16); + _rtw_memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16); pMicKey = pWapiSta->wapiMskUpdate.micKey; pDataKey = pWapiSta->wapiMskUpdate.dataKey; } else { @@ -767,11 +767,11 @@ u8 SecSWSMS4Decryption( if (bQosData) WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); else - memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); } else - memcpy(precv_hdr->WapiTempPN, pRecvPN, 16); + _rtw_memcpy(precv_hdr->WapiTempPN, pRecvPN, 16); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) { + if (MLME_IS_STA(padapter)) { if ((pRecvPN[0] & 0x1) == 0) { WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__); return false; @@ -790,7 +790,7 @@ u8 SecSWSMS4Decryption( if (bQosData) WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); else - memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); pMicKey = pWapiSta->wapiUskUpdate.micKey; pDataKey = pWapiSta->wapiUskUpdate.dataKey; } else { @@ -817,21 +817,21 @@ u8 SecSWSMS4Decryption( WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN); WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN); - if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) { + if (_TRUE == _rtw_memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) { WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__); if (bUseUpdatedKey) { /* delete the old key */ if (IS_MCAST(pRA)) { WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__); pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId; - memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16); - memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16); + _rtw_memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16); pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false; } else { WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__); pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId; - memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); - memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false; } } @@ -892,7 +892,7 @@ u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe) /* pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; */ - if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) { + if (false == SecSWSMS4Decryption(padapter, precvframe, &adapter_to_dvobj(padapter)->recvpriv)) { WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n", __FUNCTION__); return _FAIL; } diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index 1a0dd02..0311607 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,16 +15,6 @@ #define _RTW_WLAN_UTIL_C_ #include -#include - -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - #include - #define ETH_TYPE_OFFSET 12 - #define PROTOCOL_OFFSET 23 - #define IP_OFFSET 30 - #define IPv6_OFFSET 38 - #define IPv6_PROTOCOL_OFFSET 20 -#endif unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74}; @@ -123,9 +113,6 @@ bool rtw_is_basic_rate_mix(u8 rate) return 1; return 0; } -#ifdef CONFIG_BCN_CNT_CONFIRM_HDL -int new_bcn_max = 3; -#endif int cckrates_included(unsigned char *rate, int ratelen) { int i; @@ -156,14 +143,20 @@ int cckratesonly_included(unsigned char *rate, int ratelen) s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta) { s8 nss = 1; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); if (!psta) return nss; - nss = GET_HAL_RX_NSS(adapter); + nss = GET_HAL_RX_NSS(dvobj); #ifdef CONFIG_80211N_HT #ifdef CONFIG_80211AC_VHT + #ifdef CONFIG_80211AX_HE + if (psta->hepriv.he_option) + nss = psta->phl_sta->asoc_cap.nss_tx; + else + #endif /* CONFIG_80211AX_HE */ if (psta->vhtpriv.vht_option) nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); else @@ -182,10 +175,15 @@ s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta) if (!psta) return nss; - nss = GET_HAL_TX_NSS(adapter); + nss = GET_HAL_TX_NSS(adapter_to_dvobj(adapter)); #ifdef CONFIG_80211N_HT #ifdef CONFIG_80211AC_VHT + #ifdef CONFIG_80211AX_HE + if (psta->hepriv.he_option) + nss = psta->phl_sta->asoc_cap.nss_rx; + else + #endif /* CONFIG_80211AX_HE */ if (psta->vhtpriv.vht_option) nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); else @@ -197,36 +195,6 @@ s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta) return nss; } -u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) -{ - u8 network_type = 0; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - - if (pmlmeext->cur_channel > 14) { - if (pmlmeinfo->VHT_enable) - network_type = WIRELESS_11AC; - else if (pmlmeinfo->HT_enable) - network_type = WIRELESS_11_5N; - - network_type |= WIRELESS_11A; - } else { - if (pmlmeinfo->HT_enable) - network_type = WIRELESS_11_24N; - - if ((cckratesonly_included(rate, ratelen)) == _TRUE) - network_type |= WIRELESS_11B; - else if ((cckrates_included(rate, ratelen)) == _TRUE) - network_type |= WIRELESS_11BG; - else - network_type |= WIRELESS_11G; - } - - return network_type; -} - -unsigned char ratetbl_val_2wifirate(unsigned char rate); unsigned char ratetbl_val_2wifirate(unsigned char rate) { unsigned char val = 0; @@ -286,7 +254,6 @@ unsigned char ratetbl_val_2wifirate(unsigned char rate) } -int is_basicrate(_adapter *padapter, unsigned char rate); int is_basicrate(_adapter *padapter, unsigned char rate) { int i; @@ -305,7 +272,6 @@ int is_basicrate(_adapter *padapter, unsigned char rate) return _FALSE; } -unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset); unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) { int i; @@ -363,7 +329,7 @@ void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask) } void UpdateBrateTbl( - PADAPTER Adapter, + _adapter *adapter, u8 *mBratesOS ) { @@ -406,71 +372,48 @@ void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen) } } -void Set_MSR(_adapter *padapter, u8 type) -{ - rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type)); -} +/*rtw_phl_mr_get_chandef(dvobj->phl, adapter->phl_role, &chandef); => mr union chan*/ +/*rtw_phl_get_cur_hal_chdef(adapter->phl_role, &chandef) => hal chan*/ -inline u8 rtw_get_oper_ch(_adapter *adapter) +void rtw_get_oper_chdef(_adapter *adapter, struct rtw_chan_def *chandef) { - return adapter_to_dvobj(adapter)->oper_channel; + if (!adapter->phl_role) + return; + + if (rtw_phl_get_cur_hal_chdef(adapter->phl_role, chandef) != RTW_PHL_STATUS_SUCCESS) + RTW_ERR("%s failed\n", __func__); } -inline void rtw_set_oper_ch(_adapter *adapter, u8 ch) +u8 rtw_get_oper_band(_adapter *adapter) { -#ifdef DBG_CH_SWITCH - const int len = 128; - char msg[128] = {0}; - int cnt = 0; - int i = 0; -#endif /* DBG_CH_SWITCH */ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - if (dvobj->oper_channel != ch) { - dvobj->on_oper_ch_time = rtw_get_current_time(); - -#ifdef DBG_CH_SWITCH - cnt += snprintf(msg + cnt, len - cnt, "switch to ch %3u", ch); - - for (i = 0; i < dvobj->iface_nums; i++) { - _adapter *iface = dvobj->padapters[i]; - cnt += snprintf(msg + cnt, len - cnt, " ["ADPT_FMT":", ADPT_ARG(iface)); - if (iface->mlmeextpriv.cur_channel == ch) - cnt += snprintf(msg + cnt, len - cnt, "C"); - else - cnt += snprintf(msg + cnt, len - cnt, "_"); - if (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE)) - cnt += snprintf(msg + cnt, len - cnt, "L"); - else - cnt += snprintf(msg + cnt, len - cnt, "_"); - cnt += snprintf(msg + cnt, len - cnt, "]"); - } + struct rtw_chan_def cur_chandef = {0}; - RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(adapter), msg); -#endif /* DBG_CH_SWITCH */ - } - - dvobj->oper_channel = ch; + rtw_get_oper_chdef(adapter, &cur_chandef); + return cur_chandef.band; } -inline u8 rtw_get_oper_bw(_adapter *adapter) +u8 rtw_get_oper_ch(_adapter *adapter) { - return adapter_to_dvobj(adapter)->oper_bwmode; -} + struct rtw_chan_def cur_chandef = {0}; -inline void rtw_set_oper_bw(_adapter *adapter, u8 bw) -{ - adapter_to_dvobj(adapter)->oper_bwmode = bw; + rtw_get_oper_chdef(adapter, &cur_chandef); + return cur_chandef.chan; } -inline u8 rtw_get_oper_choffset(_adapter *adapter) +u8 rtw_get_oper_bw(_adapter *adapter) { - return adapter_to_dvobj(adapter)->oper_ch_offset; + struct rtw_chan_def cur_chandef = {0}; + + rtw_get_oper_chdef(adapter, &cur_chandef); + return cur_chandef.bw; } -inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset) +u8 rtw_get_oper_choffset(_adapter *adapter) { - adapter_to_dvobj(adapter)->oper_ch_offset = offset; + struct rtw_chan_def cur_chandef = {0}; + + rtw_get_oper_chdef(adapter, &cur_chandef); + return cur_chandef.offset; } inline systime rtw_get_on_oper_ch_time(_adapter *adapter) @@ -480,93 +423,20 @@ inline systime rtw_get_on_oper_ch_time(_adapter *adapter) inline systime rtw_get_on_cur_ch_time(_adapter *adapter) { - if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) + if (adapter->mlmeextpriv.chandef.chan == rtw_get_oper_ch(adapter)) return adapter_to_dvobj(adapter)->on_oper_ch_time; else return 0; } -void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) +void set_channel_bwmode(_adapter *padapter, + unsigned char channel, + unsigned char channel_offset, + unsigned short bwmode, + u8 do_rfk) { - u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; -#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) - u8 iqk_info_backup = _FALSE; -#endif - - if (padapter->bNotifyChannelChange) - RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode); - - center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); - - if (bwmode == CHANNEL_WIDTH_80) { - if (center_ch > channel) - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; - else if (center_ch < channel) - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; - else - chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - } - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't set channel setting reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - RTW_INFO("Warning: Do not set channel setting reg MCC mode\n"); - } -#endif - -#ifdef CONFIG_DFS_MASTER - { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); - bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset); - - if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) { - u8 pause = 0xFF; - - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } -#endif /* CONFIG_DFS_MASTER */ - - /* set Channel */ - /* saved channel/bw info */ - rtw_set_oper_ch(padapter, channel); - rtw_set_oper_bw(padapter, bwmode); - rtw_set_oper_choffset(padapter, channel_offset); - -#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) - /* To check if we need to backup iqk info after switch chnl & bw */ - { - u8 take_care_iqk, do_iqk; - - rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); - rtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk); - if ((take_care_iqk == _TRUE) && (do_iqk == _TRUE)) - iqk_info_backup = _TRUE; - } -#endif - - rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */ - -#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) - if (iqk_info_backup == _TRUE) - rtw_hal_ch_sw_iqk_info_backup(padapter); -#endif - -#ifdef CONFIG_DFS_MASTER - if (new_overlap_radar_detect_ch) - rtw_odm_radar_detect_enable(padapter); - else if (ori_overlap_radar_detect_ch) { - u8 pause = 0x00; - - rtw_odm_radar_detect_disable(padapter); - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } - } -#endif /* CONFIG_DFS_MASTER */ - - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + rtw_hw_set_ch_bw(padapter, channel, (enum channel_width)bwmode, + channel_offset, do_rfk); } __inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) @@ -611,8 +481,14 @@ int is_client_associated_to_ibss(_adapter *padapter) return _FAIL; } +/*GEORGIA_TODO_FIXIT*/ +#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1) +#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4) + int is_IBSS_empty(_adapter *padapter) { +/* ToDo */ +#if 0 int i; struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; @@ -626,7 +502,7 @@ int is_IBSS_empty(_adapter *padapter) if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC) return _FAIL; } - +#endif return _TRUE; } @@ -640,4959 +516,2623 @@ unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval) return bcn_interval << 2; } -void invalidate_cam_all(_adapter *padapter) +#if defined(CONFIG_P2P) && defined(CONFIG_WFD) +void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - u8 bmc_id = rtw_iface_bcmc_id_get(padapter); - _irqL irqL; - u8 val8 = 0; - - rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8); + struct wifidirect_info *wdinfo = &adapter->wdinfo; - _enter_critical_bh(&cam_ctl->lock, &irqL); + u8 *attr_content; + u32 attr_contentlen = 0; - rtw_sec_cam_map_clr_all(&cam_ctl->used); + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) + return; -#ifndef SEC_DEFAULT_KEY_SEARCH - /* for BMC data TX with force camid */ - if (bmc_id != INVALID_SEC_MAC_CAM_ID) { - rtw_sec_cam_map_set(&cam_ctl->used, bmc_id); - if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC)) - rtw_sec_cam_map_set(&cam_ctl->used, bmc_id + 1); + RTW_INFO("[%s] Found WFD IE\n", tag); + attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2); + RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport); } -#endif - - _rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT); - _exit_critical_bh(&cam_ctl->lock, &irqL); - -#ifdef SEC_DEFAULT_KEY_SEARCH//!BMC TX force camid - /* clear default key related key search setting */ - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE); -#endif } -void _clear_cam_entry(_adapter *padapter, u8 entry) +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag) { - unsigned char null_sta[6] = {0}; - unsigned char null_key[32] = {0}; + u8 *wfd_ie; + u32 wfd_ielen; - rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key); -} + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(adapter), WL_FUNC_MIRACAST)) + return; -inline void _write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) -{ -#ifdef CONFIG_WRITE_CACHE_ONLY - write_cam_cache(adapter, id , ctrl, mac, key); -#else - rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key); - write_cam_cache(adapter, id , ctrl, mac, key); -#endif + wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen); + while (wfd_ie) { + rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag); + wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen); + } } +#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */ -inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - if (ctrl & BIT(9)) { - _write_cam(adapter, id, ctrl, mac, key); - _write_cam(adapter, (id + 1), ctrl | BIT(5), mac, (key + 16)); - RTW_INFO_DUMP("key-0: ", key, 16); - RTW_INFO_DUMP("key-1: ", (key + 16), 16); - } else - _write_cam(adapter, id, ctrl, mac, key); -} + /* struct registry_priv *pregpriv = &padapter->registrypriv; */ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -inline void clear_cam_entry(_adapter *adapter, u8 id) -{ - _clear_cam_entry(adapter, id); - clear_cam_cache(adapter, id); -} + if (pmlmepriv->qospriv.qos_option == 0) { + pmlmeinfo->WMM_enable = 0; + return _FALSE; + } -inline void write_cam_from_cache(_adapter *adapter, u8 id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - struct sec_cam_ent cache; + if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element))) + return _FALSE; + else + _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); + pmlmeinfo->WMM_enable = 1; + return _TRUE; - _enter_critical_bh(&cam_ctl->lock, &irqL); - _rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent)); - _exit_critical_bh(&cam_ctl->lock, &irqL); +#if 0 + if (pregpriv->wifi_spec == 1) { + if (pmlmeinfo->WMM_enable == 1) { + /* todo: compare the parameter set count & decide wheher to update or not */ + return _FAIL; + } else { + pmlmeinfo->WMM_enable = 1; + _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); + return _TRUE; + } + } else { + pmlmeinfo->WMM_enable = 0; + return _FAIL; + } +#endif - rtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key); } -void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - _enter_critical_bh(&cam_ctl->lock, &irqL); - - dvobj->cam_cache[id].ctrl = ctrl; - _rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN); - _rtw_memcpy(dvobj->cam_cache[id].key, key, 16); +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT +u8 rtw_is_tbtx_capabilty(u8 *p, u8 len){ + int i; + u8 tbtx_cap_ie[8] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00}; - _exit_critical_bh(&cam_ctl->lock, &irqL); + for (i = 0; i < len; i++) { + if (*(p + i) != tbtx_cap_ie[i]) + return _FALSE; + else + continue; + } + return _TRUE; } +#endif -void clear_cam_cache(_adapter *adapter, u8 id) +void WMMOnAssocRsp(_adapter *padapter) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; + u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 acm_mask; + u16 TXOP; + u32 acParm, i; + u32 edca[4], inx[4]; + u8 ac_be = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ - _enter_critical_bh(&cam_ctl->lock, &irqL); + acm_mask = 0; - _rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent)); + if (WIFI_ROLE_IS_ON_5G(padapter) || + (pmlmeext->cur_wireless_mode & WLAN_MD_11N)) + aSifsTime = 16; + else + aSifsTime = 10; - _exit_critical_bh(&cam_ctl->lock, &irqL); -} + if (pmlmeinfo->WMM_enable == 0) { + padapter->mlmepriv.acm_mask = 0; -inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); - if (cam_ctl->sec_cap & cap) - return _TRUE; - return _FALSE; -} + if (pmlmeext->cur_wireless_mode & (WLAN_MD_11G | WLAN_MD_11A)) { + ECWMin = 4; + ECWMax = 10; + } else if (pmlmeext->cur_wireless_mode & WLAN_MD_11B) { + ECWMin = 5; + ECWMax = 10; + } else { + ECWMin = 4; + ECWMax = 10; + } -inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hw_set_edca(padapter, 0, acParm); + rtw_hw_set_edca(padapter, 1, acParm); + rtw_hw_set_edca(padapter, 2, acParm); - cam_ctl->flags |= flags; -} + ECWMin = 2; + ECWMax = 3; + TXOP = 0x2f; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hw_set_edca(padapter, 3, acParm); + } else { + edca[0] = edca[1] = edca[2] = edca[3] = 0; -inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; + for (i = 0; i < 4; i++) { + ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; + ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; - _enter_critical_bh(&cam_ctl->lock, &irqL); - _rtw_camctl_set_flags(adapter, flags); - _exit_critical_bh(&cam_ctl->lock, &irqL); -} + /* AIFS = AIFSN * slot time + SIFS - r2t phy delay */ + AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; -inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); + ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; + TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); - cam_ctl->flags &= ~flags; -} + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hw_set_edca(padapter, ACI, acParm); -inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; + switch (ACI) { + case 0x0: + acm_mask |= (ACM ? BIT(1) : 0); + edca[XMIT_BE_QUEUE] = acParm; + break; - _enter_critical_bh(&cam_ctl->lock, &irqL); - _rtw_camctl_clr_flags(adapter, flags); - _exit_critical_bh(&cam_ctl->lock, &irqL); -} + case 0x1: + /* acm_mask |= (ACM? BIT(0):0); */ + edca[XMIT_BK_QUEUE] = acParm; + break; -inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + case 0x2: + acm_mask |= (ACM ? BIT(2) : 0); + edca[XMIT_VI_QUEUE] = acParm; + break; - if (cam_ctl->flags & flags) - return _TRUE; - return _FALSE; -} + case 0x3: + acm_mask |= (ACM ? BIT(3) : 0); + edca[XMIT_VO_QUEUE] = acParm; + break; + } -void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num) -{ - RTW_PRINT_SEL(sel, "0x%08x\n", map->m0); -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - if (max_num && max_num > 32) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m1); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - if (max_num && max_num > 64) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m2); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - if (max_num && max_num > 96) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m3); -#endif -} + RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm); -inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id) -{ - if (id < 32) - return map->m0 & BIT(id); -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - else if (id < 64) - return map->m1 & BIT(id - 32); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - else if (id < 96) - return map->m2 & BIT(id - 64); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - else if (id < 128) - return map->m3 & BIT(id - 96); -#endif - else - rtw_warn_on(1); + if (i == ac_be) { + padapter->last_edca = acParm; + acParm = rtw_get_turbo_edca(padapter, AIFS, ECWMin, ECWMax, TXOP); + if (acParm) { + rtw_hw_set_edca(padapter, ACI, acParm); + padapter->last_edca = acParm; + } + } - return 0; -} + } -inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id) -{ - if (id < 32) - map->m0 |= BIT(id); -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - else if (id < 64) - map->m1 |= BIT(id - 32); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - else if (id < 96) - map->m2 |= BIT(id - 64); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - else if (id < 128) - map->m3 |= BIT(id - 96); -#endif - else - rtw_warn_on(1); -} + if (padapter->registrypriv.acm_method == 1) + rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); + else + padapter->mlmepriv.acm_mask = acm_mask; -inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id) -{ - if (id < 32) - map->m0 &= ~BIT(id); -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - else if (id < 64) - map->m1 &= ~BIT(id - 32); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - else if (id < 96) - map->m2 &= ~BIT(id - 64); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - else if (id < 128) - map->m3 &= ~BIT(id - 96); -#endif - else - rtw_warn_on(1); -} + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; -inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map) -{ - map->m0 = 0; -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - map->m1 = 0; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - map->m2 = 0; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - map->m3 = 0; -#endif -} + if (pregpriv->wifi_spec == 1) { + u32 j, tmp, change_inx = _FALSE; -inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id) -{ - struct sec_cam_bmp forbid_map; + /* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */ + for (i = 0; i < 4; i++) { + for (j = i + 1; j < 4; j++) { + /* compare CW and AIFS */ + if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) + change_inx = _TRUE; + else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) { + /* compare TXOP */ + if ((edca[j] >> 16) > (edca[i] >> 16)) + change_inx = _TRUE; + } - forbid_map.m0 = 0x00000ff0; -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - forbid_map.m1 = 0x00000000; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - forbid_map.m2 = 0x00000000; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - forbid_map.m3 = 0x00000000; -#endif + if (change_inx) { + tmp = edca[i]; + edca[i] = edca[j]; + edca[j] = tmp; - if (id < 32) - return forbid_map.m0 & BIT(id); -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - else if (id < 64) - return forbid_map.m1 & BIT(id - 32); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - else if (id < 96) - return forbid_map.m2 & BIT(id - 64); -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - else if (id < 128) - return forbid_map.m3 & BIT(id - 96); -#endif - else - rtw_warn_on(1); + tmp = inx[i]; + inx[i] = inx[j]; + inx[j] = tmp; - return 1; + change_inx = _FALSE; + } + } + } + } + + for (i = 0; i < 4; i++) { + pxmitpriv->wmm_para_seq[i] = inx[i]; + RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); + } + +#ifdef CONFIG_WMMPS_STA + /* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */ + if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) { + pqospriv->uapsd_ap_supported = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL); + } +#endif /* CONFIG_WMMPS_STA */ + } } -bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - bool ret = _FALSE; - - if (id >= cam_ctl->num) { - rtw_warn_on(1); - goto exit; - } +#ifdef CONFIG_80211N_HT + unsigned char new_bwmode; + unsigned char new_ch_offset; + struct HT_info_element *pHT_info; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + u8 cbw40_enable = 0; -#if 0 /* for testing */ - if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) { - ret = _TRUE; - goto exit; - } -#endif + if (!pIE) + return; - ret = rtw_sec_camid_is_set(&cam_ctl->used, id); + if (phtpriv->ht_option == _FALSE) + return; -exit: - return ret; -} + if (pmlmeext->chandef.bw >= CHANNEL_WIDTH_80) + return; -inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) -{ - _irqL irqL; - bool ret; + if (pIE->Length > sizeof(struct HT_info_element)) + return; - _enter_critical_bh(&cam_ctl->lock, &irqL); - ret = _rtw_sec_camid_is_used(cam_ctl, id); - _exit_critical_bh(&cam_ctl->lock, &irqL); + pHT_info = (struct HT_info_element *)pIE->data; - return ret; -} -u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - int i; - _irqL irqL; - u8 sec_cam_num = 0; - - _enter_critical_bh(&cam_ctl->lock, &irqL); - for (i = 0; i < cam_ctl->num; i++) { - if (_rtw_sec_camid_is_used(cam_ctl, i)) { - sec_key_id[sec_cam_num++] = i; - if (sec_cam_num == max_bk_key_num) - break; + if (rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_40M)) { + if (pmlmeext->chandef.chan > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; } } - _exit_critical_bh(&cam_ctl->lock, &irqL); - return sec_cam_num; -} + if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) { + new_bwmode = CHANNEL_WIDTH_40; -inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - bool ret = _FALSE; + switch (pHT_info->infos[0] & 0x3) { + case 1: + new_ch_offset = CHAN_OFFSET_UPPER; + break; - if (cam_id >= cam_ctl->num) { - rtw_warn_on(1); - goto exit; - } + case 3: + new_ch_offset = CHAN_OFFSET_LOWER; + break; - if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE) - goto exit; + default: + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = CHAN_OFFSET_NO_EXT; + break; + } + } else { + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = CHAN_OFFSET_NO_EXT; + } - ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE; -exit: - return ret; -} + if ((new_bwmode != pmlmeext->chandef.bw || new_ch_offset != pmlmeext->chandef.offset) + && new_bwmode < pmlmeext->chandef.bw + ) { + pmlmeinfo->bwmode_updated = _TRUE; -inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - bool ret; + pmlmeext->chandef.bw = new_bwmode; + pmlmeext->chandef.offset = new_ch_offset; - _enter_critical_bh(&cam_ctl->lock, &irqL); - ret = _rtw_camid_is_gk(adapter, cam_id); - _exit_critical_bh(&cam_ctl->lock, &irqL); + /* update HT info also */ + HT_info_handler(padapter, pIE); + } else + pmlmeinfo->bwmode_updated = _FALSE; - return ret; -} -bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - bool ret = _FALSE; + if (_TRUE == pmlmeinfo->bwmode_updated) { + struct sta_info *psta; + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; - if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE) - goto exit; - if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03)) - goto exit; - if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id)) - goto exit; + /* set_channel_bwmode(padapter, pmlmeext->chandef.chan, pmlmeext->chandef.offset, pmlmeext->chandef.bw); */ - ret = _TRUE; -exit: - return ret; -} + /* update ap's stainfo */ + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + struct ht_priv *phtpriv_sta = &psta->htpriv; -s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - int i; - s16 cam_id = -1; + if (phtpriv_sta->ht_option) { + /* bwmode */ + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; + phtpriv_sta->ch_offset = pmlmeext->chandef.offset; + } else { + psta->phl_sta->chandef.bw = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = CHAN_OFFSET_NO_EXT; + } - for (i = 0; i < cam_ctl->num; i++) { - if (cam_cache_chk(adapter, i, addr, kid, gk)) { - cam_id = i; - break; + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(padapter)->phl, + psta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_NO_WAIT, + 0); } - } - if (0) { - if (addr) - RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id); - else - RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n" - , FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id); + /* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */ } - - return cam_id; +#endif /* CONFIG_80211N_HT */ } -s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +#ifdef ROKU_PRIVATE +void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - s16 cam_id = -1; + unsigned int i; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE == NULL) + return; - _enter_critical_bh(&cam_ctl->lock, &irqL); - cam_id = _rtw_camid_search(adapter, addr, kid, gk); - _exit_critical_bh(&cam_ctl->lock, &irqL); + for (i = 0 ; i < pIE->Length; i++) + pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]); - return cam_id; } -s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk, bool ext_sec) +void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - int i; -#if 0 /* for testing */ - static u8 start_id = 0; -#else - u8 start_id = 0; -#endif - s16 cam_id = -1; - - if (addr == NULL) { - RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n" - , FUNC_ADPT_ARG(adapter)); - rtw_warn_on(1); - goto _exit; - } - - /* find cam entry which has the same addr, kid (, gk bit) */ - if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) - i = _rtw_camid_search(adapter, addr, kid, gk); - else - i = _rtw_camid_search(adapter, addr, kid, -1); + unsigned int i, j; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (i >= 0) { - cam_id = i; - goto _exit; - } + if (pIE == NULL) + return; - for (i = 0; i < cam_ctl->num; i++) { - /* bypass default key which is allocated statically */ -#ifdef SEC_DEFAULT_KEY_SEARCH - if (((i + start_id) % cam_ctl->num) < 4) - continue; -#endif - if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) { - if (ext_sec) { - /* look out continue slot */ - if (((i + 1) < cam_ctl->num) && - (_rtw_sec_camid_is_used(cam_ctl, (((i + 1) + start_id) % cam_ctl->num)) == _FALSE)) - break; - else - continue; - } else + if (pIE->Length > 0) { + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) break; } + for (j = 0; j < pIE->Length; j++) + pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]); } - if (i == cam_ctl->num) { - RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n" - , FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid); - rtw_warn_on(1); - goto _exit; - } - - cam_id = ((i + start_id) % cam_ctl->num); - start_id = ((i + start_id + 1) % cam_ctl->num); - -_exit: - return cam_id; } -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used) +void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss) { - struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - s16 cam_id = -1; - - *used = _FALSE; - - _enter_critical_bh(&cam_ctl->lock, &irqL); - - if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) - && !sta) { - /* - * 1. non-STA mode WEP key - * 2. group TX key - */ -#ifdef SEC_DEFAULT_KEY_SEARCH - /* static alloction to default key by key ID when concurrent is not defined */ - if (kid > 3) { - RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n" - , FUNC_ADPT_ARG(adapter), kid); - rtw_warn_on(1); - goto bitmap_handle; - } - cam_id = kid; -#else - u8 *addr = adapter_mac_addr(adapter); - - cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec); - if (1) - RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id); -#endif - } else { - /* - * 1. STA mode WEP key - * 2. STA mode group RX key - * 3. sta key (pairwise, group RX) - */ - u8 *addr = sta ? sta->cmn.mac_addr : NULL; + u8 i, j; + u8 r_ss = 0, t_ss = 0; - if (!sta) { - if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { - /* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */ - goto bitmap_handle; - } - addr = get_bssid(&adapter->mlmepriv);/*A2*/ + for (i = 0; i < 4; i++) { + if ((mcs_set[3-i] & 0xff) != 0x00) { + r_ss = 4-i; + break; } - cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec); - } - - -bitmap_handle: - if (cam_id >= 0) { - *used = _rtw_sec_camid_is_used(cam_ctl, cam_id); - rtw_sec_cam_map_set(&cam_ctl->used, cam_id); - if (ext_sec) - rtw_sec_cam_map_set(&cam_ctl->used, cam_id + 1); } - _exit_critical_bh(&cam_ctl->lock, &irqL); - - return cam_id; + *Rx_ss = r_ss; } -void rtw_camid_set(_adapter *adapter, u8 cam_id) +void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - - _enter_critical_bh(&cam_ctl->lock, &irqL); - - if (cam_id < cam_ctl->num) - rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + unsigned int i; + u8 cur_stbc_cap_infra_ap = 0; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; - _exit_critical_bh(&cam_ctl->lock, &irqL); -} + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -void rtw_camid_free(_adapter *adapter, u8 cam_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; + if (pIE == NULL) + return; - _enter_critical_bh(&cam_ctl->lock, &irqL); + pmlmeinfo->ht_vht_received |= BIT(0); - if (cam_id < cam_ctl->num) - rtw_sec_cam_map_clr(&cam_ctl->used, cam_id); - - _exit_critical_bh(&cam_ctl->lock, &irqL); -} + /*copy MCS_SET*/ + for (i = 3; i < 19; i++) + phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]); -/*Must pause TX/RX before use this API*/ -inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - struct sec_cam_ent cache_a, cache_b; - _irqL irqL; - bool cam_a_used, cam_b_used; + /*get number of stream from mcs set*/ + HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap); - if (1) - RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b); + phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data)); - if (cam_id_a == cam_id_b) - return; + phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data); - rtw_mi_update_ap_bmc_camid(adapter, cam_id_a, cam_id_b); + if (GET_HT_CAP_ELE_RX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX); + if (GET_HT_CAP_ELE_TX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX); + phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap; - /*setp-1. backup org cam_info*/ - _enter_critical_bh(&cam_ctl->lock, &irqL); + /*store ap info SGI 20m 40m*/ + phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data); + phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data); - cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a); - cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b); + /*store ap info for supported channel bandwidth*/ + phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data); +} +#endif /* ROKU_PRIVATE */ - if (cam_a_used) - _rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent)); +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ +#ifdef CONFIG_80211N_HT + unsigned int i; + u8 max_AMPDU_len, min_MPDU_spacing; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rx_nss = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct sta_info *sta = NULL; + struct rtw_phl_stainfo_t *phl_sta = NULL; + struct rtw_wifi_role_t *wrole = padapter->phl_role; + struct protocol_cap_t *proto_role_cap = &(wrole->proto_role_cap); +#ifdef CONFIG_DISABLE_MCS13TO15 + struct registry_priv *pregistrypriv = &padapter->registrypriv; +#endif - if (cam_b_used) - _rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent)); + if (pIE == NULL) + return; - _exit_critical_bh(&cam_ctl->lock, &irqL); + if (phtpriv->ht_option == _FALSE) + return; - /*setp-2. clean cam_info*/ - if (cam_a_used) { - rtw_camid_free(adapter, cam_id_a); - clear_cam_entry(adapter, cam_id_a); - } - if (cam_b_used) { - rtw_camid_free(adapter, cam_id_b); - clear_cam_entry(adapter, cam_id_b); - } + pmlmeinfo->HT_caps_enable = 1; - /*setp-3. set cam_info*/ - if (cam_a_used) { - write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key); - rtw_camid_set(adapter, cam_id_b); - } + for (i = 0; i < (pIE->Length); i++) { + if (i != 2) { + /* Commented by Albert 2010/07/12 */ + /* Got the endian issue here. */ + pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]); + } else { + /* AMPDU Parameters field */ - if (cam_b_used) { - write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key); - rtw_camid_set(adapter, cam_id_a); - } -} + /* Get MIN of MAX AMPDU Length Exp */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) + max_AMPDU_len = (pIE->data[i] & 0x3); + else + max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); -s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - int i; - s16 cam_id = -1; + /* Get MAX of MIN MPDU Start Spacing */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); + else + min_MPDU_spacing = (pIE->data[i] & 0x1c); - _enter_critical_bh(&cam_ctl->lock, &irqL); - for (i = start_camid; i < cam_ctl->num; i++) { - if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) { - cam_id = i; - break; + pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; } } - _exit_critical_bh(&cam_ctl->lock, &irqL); - return cam_id; -} -void rtw_clean_dk_section(_adapter *adapter) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); - s16 ept_cam_id; - int i; + /* Commented by Albert 2010/07/12 */ + /* Have to handle the endian issue after copying. */ + /* HT_ext_caps didn't be used yet. */ + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); + pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps); - for (i = 0; i < 4; i++) { - if (rtw_sec_camid_is_used(cam_ctl, i)) { - ept_cam_id = rtw_get_empty_cam_entry(adapter, 4); - if (ept_cam_id > 0) - rtw_sec_cam_swap(adapter, i, ept_cam_id); - } - } -} -void rtw_clean_hw_dk_cam(_adapter *adapter) -{ - int i; + /* update the MCS set */ + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; - for (i = 0; i < 4; i++) { - if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_WRITE_CAM_NEW_RULE)) - _clear_cam_entry(adapter, i); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); + + switch (rx_nss) { + case 1: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); + break; + case 2: + #ifdef CONFIG_DISABLE_MCS13TO15 + if (pmlmeext->chandef.bw == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); else - rtw_sec_clr_cam_ent(adapter, i); + #endif + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or tx_nss:%u is not expected\n", GET_HAL_RFPATH(adapter_to_dvobj(padapter)), rx_nss); } -} -void flush_all_cam_entry(_adapter *padapter) -{ -#ifdef CONFIG_CONCURRENT_MODE - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /* Config STBC setting */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { + SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX); + RTW_INFO("Enable HT Tx STBC !\n"); + } + phtpriv->stbc_cap = cur_stbc_cap; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; +#ifdef CONFIG_BEAMFORMING + /* Config Tx beamforming setting */ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); + } - psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); - if (psta) { - if (psta->state & WIFI_AP_STATE) { - /*clear cam when ap free per sta_info*/ - } else - rtw_clearstakey_cmd(padapter, psta, _FALSE); + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); } - } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { -#ifdef CONFIG_AP_MODE -#ifndef SEC_DEFAULT_KEY_SEARCH - int cam_id = -1; - u8 *addr = adapter_mac_addr(padapter); - u8 bmc_id = rtw_iface_bcmc_id_get(padapter); - - while ((cam_id = rtw_camid_search(padapter, addr, -1, -1)) >= 0) { - RTW_PRINT("clear wep or group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), cam_id); - clear_cam_entry(padapter, cam_id); - /* clear cam_ctl.used bit for data BMC TX force camid in rtw_release_macid() */ - if (bmc_id == INVALID_SEC_MAC_CAM_ID || cam_id != bmc_id) - rtw_camid_free(padapter, cam_id); + phtpriv->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) + RTW_INFO("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); +#endif /*CONFIG_BEAMFORMING*/ + } else { + /*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/ + sta = rtw_get_stainfo(&padapter->stapriv, pmlmeinfo->network.MacAddress); + if (!sta) { + RTW_ERR(FUNC_ADPT_FMT ": STA(" MAC_FMT ") not found!\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(pmlmeinfo->network.MacAddress)); + return; } -#else - /* clear default key */ - int i, cam_id; - u8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; + if (!sta->phl_sta) { + RTW_ERR(FUNC_ADPT_FMT ": PHL STA(" MAC_FMT ") not exist!\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(pmlmeinfo->network.MacAddress)); + return; + } + phl_sta = sta->phl_sta; - for (i = 0; i < 4; i++) { - cam_id = rtw_camid_search(padapter, null_addr, i, -1); - if (cam_id >= 0) { - clear_cam_entry(padapter, cam_id); - rtw_camid_free(padapter, cam_id); - } + /* Config LDPC Coding Capability */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx LDPC!\n"); + phl_sta->asoc_cap.ht_ldpc = 1; } - /* clear default key related key search setting */ - rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE); -#endif -#endif /* CONFIG_AP_MODE */ - } + phtpriv->ldpc_cap = cur_ldpc_cap; -#else /*NON CONFIG_CONCURRENT_MODE*/ + /* Config STBC setting */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx STBC!\n"); + phl_sta->asoc_cap.stbc_ht_rx = + proto_role_cap->stbc_ht_tx ? GET_HT_CAP_ELE_RX_STBC(pIE->data) : 0; + } + phtpriv->stbc_cap = cur_stbc_cap; + phl_sta->asoc_cap.stbc_ht_tx = GET_HT_CAP_ELE_TX_STBC(pIE->data); - invalidate_cam_all(padapter); -#endif +#ifdef CONFIG_BEAMFORMING + /* Config beamforming setting */ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); + } + + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); + } + phtpriv->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) + RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); +#endif /*CONFIG_BEAMFORMING*/ + } + +#endif /* CONFIG_80211N_HT */ } -#if defined(CONFIG_P2P) && defined(CONFIG_WFD) -void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag) +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - struct wifidirect_info *wdinfo = &adapter->wdinfo; - - u8 *attr_content; - u32 attr_contentlen = 0; +#ifdef CONFIG_80211N_HT + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (pIE == NULL) return; - RTW_INFO("[%s] Found WFD IE\n", tag); - attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); - if (attr_content && attr_contentlen) { - wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2); - RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport); - } -} + if (phtpriv->ht_option == _FALSE) + return; -void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag) -{ - u8 *wfd_ie; - u32 wfd_ielen; - if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + if (pIE->Length > sizeof(struct HT_info_element)) return; - wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen); - while (wfd_ie) { - rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag); - wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen); - } + pmlmeinfo->HT_info_enable = 1; + _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); +#endif /* CONFIG_80211N_HT */ + return; } -#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */ -int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +void HTOnAssocRsp(_adapter *padapter) { - /* struct registry_priv *pregpriv = &padapter->registrypriv; */ - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + unsigned char max_AMPDU_len; + unsigned char min_MPDU_spacing; + /* struct registry_priv *pregpriv = &padapter->registrypriv; */ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (pmlmepriv->qospriv.qos_option == 0) { - pmlmeinfo->WMM_enable = 0; - return _FALSE; - } - - if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element))) - return _FALSE; - else - _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); - pmlmeinfo->WMM_enable = 1; - return _TRUE; + RTW_INFO("%s\n", __FUNCTION__); -#if 0 - if (pregpriv->wifi_spec == 1) { - if (pmlmeinfo->WMM_enable == 1) { - /* todo: compare the parameter set count & decide wheher to update or not */ - return _FAIL; - } else { - pmlmeinfo->WMM_enable = 1; - _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); - return _TRUE; - } - } else { - pmlmeinfo->WMM_enable = 0; - return _FAIL; + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + pmlmeinfo->HT_enable = 1; + else { + pmlmeinfo->HT_enable = 0; + /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ + return; } -#endif -} + /* handle A-MPDU parameter field */ + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT -u8 rtw_is_tbtx_capabilty(u8 *p, u8 len){ - int i; - u8 tbtx_cap_ie[8] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00}; + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; - for (i = 0; i < len; i++) { - if (*(p + i) != tbtx_cap_ie[i]) - return _FALSE; - else - continue; + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); +#ifdef CONFIG_80211N_HT + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); +#endif /* CONFIG_80211N_HT */ +#if 0 /* move to rtw_update_ht_cap() */ + if ((pregpriv->bw_mode > 0) && + (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && + (pmlmeinfo->HT_info.infos[0] & BIT(2))) { + /* switch to the 40M Hz mode accoring to the AP */ + pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; + switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) { + case IEEE80211_SCA: + pmlmeext->cur_ch_offset = CHAN_OFFSET_UPPER; + break; + + case IEEE80211_SCB: + pmlmeext->cur_ch_offset = CHAN_OFFSET_LOWER; + break; + + default: + pmlmeext->cur_ch_offset = CHAN_OFFSET_NO_EXT; + break; + } } - return _TRUE; -} #endif -void WMMOnAssocRsp(_adapter *padapter) + /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ + +#if 0 /* move to rtw_update_ht_cap() */ + /* */ + /* Config SM Power Save setting */ + /* */ + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) { +#if 0 + u8 i; + /* update the MCS rates */ + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; +#endif + RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__); + } + + /* */ + /* Config current HT Protection mode. */ + /* */ + pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; +#endif + +} + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { - u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; - u8 acm_mask; - u16 TXOP; - u32 acParm, i; - u32 edca[4], inx[4]; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct registry_priv *pregpriv = &padapter->registrypriv; -#ifdef CONFIG_WMMPS_STA - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct qos_priv *pqospriv = &pmlmepriv->qospriv; -#endif /* CONFIG_WMMPS_STA */ - acm_mask = 0; + if (pIE->Length > 1) + return; - if (is_supported_5g(pmlmeext->cur_wireless_mode) || - (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) - aSifsTime = 16; - else - aSifsTime = 10; + pmlmeinfo->ERP_enable = 1; + _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); +} - if (pmlmeinfo->WMM_enable == 0) { - padapter->mlmepriv.acm_mask = 0; +void VCS_update(_adapter *padapter, struct sta_info *psta) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); + switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */ + case 0: /* off */ + psta->rtsen = 0; + psta->cts2self = 0; + break; - if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) { - ECWMin = 4; - ECWMax = 10; - } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { - ECWMin = 5; - ECWMax = 10; + case 1: /* on */ + if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */ + psta->rtsen = 1; + psta->cts2self = 0; } else { - ECWMin = 4; - ECWMax = 10; + psta->rtsen = 0; + psta->cts2self = 1; } + break; - TXOP = 0; - acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); - - ECWMin = 2; - ECWMax = 3; - TXOP = 0x2f; - acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); - } else { - edca[0] = edca[1] = edca[2] = edca[3] = 0; - - for (i = 0; i < 4; i++) { - ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; - ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; + case 2: /* auto */ + default: + if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) + /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ + ) { + if (pregpriv->vcs_type == 1) { + psta->rtsen = 1; + psta->cts2self = 0; + } else { + psta->rtsen = 0; + psta->cts2self = 1; + } + } else { + psta->rtsen = 0; + psta->cts2self = 0; + } + break; + } - /* AIFS = AIFSN * slot time + SIFS - r2t phy delay */ - AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; + switch (pregpriv->hw_rts_en) { /* 0:disable 1:enable */ + case 0: + psta->hw_rts_en = 0; + break; + case 1: + psta->hw_rts_en = 1; + break; + default: + RTW_WARN("%s: unexpected value(%d) for hw_rts_en.\n", __func__, pregpriv->hw_rts_en); + break; + } - ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); - ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; - TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); +} - acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); +void update_ldpc_stbc_cap(struct sta_info *psta) +{ +#ifdef CONFIG_80211N_HT - switch (ACI) { - case 0x0: - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); - acm_mask |= (ACM ? BIT(1) : 0); - edca[XMIT_BE_QUEUE] = acParm; - break; +#ifdef CONFIG_80211AC_VHT +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ + if (psta->vhtpriv.vht_option) { + if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) + psta->phl_sta->asoc_cap.vht_ldpc = 1; + else + psta->phl_sta->asoc_cap.vht_ldpc = 0; + } else +#endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) { + if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) + psta->phl_sta->asoc_cap.ht_ldpc = 1; + else + psta->phl_sta->asoc_cap.ht_ldpc = 0; + } else { + psta->phl_sta->asoc_cap.vht_ldpc = 0; + psta->phl_sta->asoc_cap.ht_ldpc = 0; + } - case 0x1: - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); - /* acm_mask |= (ACM? BIT(0):0); */ - edca[XMIT_BK_QUEUE] = acParm; - break; +#endif /* CONFIG_80211N_HT */ +} - case 0x2: - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); - acm_mask |= (ACM ? BIT(2) : 0); - edca[XMIT_VI_QUEUE] = acParm; - break; +int check_ielen(u8 *start, uint len) +{ + int left = len; + u8 *pos = start; + u8 id, elen; - case 0x3: - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); - acm_mask |= (ACM ? BIT(3) : 0); - edca[XMIT_VO_QUEUE] = acParm; - break; - } + while (left >= 2) { + id = *pos++; + elen = *pos++; + left -= 2; - RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm); + if (elen > left) { + RTW_ERR("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n", + id, elen, (unsigned long) left); + return _FALSE; } + if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3)) + return _FALSE; - if (padapter->registrypriv.acm_method == 1) - rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); - else - padapter->mlmepriv.acm_mask = acm_mask; + left -= elen; + pos += elen; + } + if (left) + return _FALSE; - inx[0] = 0; - inx[1] = 1; - inx[2] = 2; - inx[3] = 3; + return _TRUE; +} - if (pregpriv->wifi_spec == 1) { - u32 j, tmp, change_inx = _FALSE; +int validate_beacon_len(u8 *pframe, u32 len) +{ + u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr); - /* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */ - for (i = 0; i < 4; i++) { - for (j = i + 1; j < 4; j++) { - /* compare CW and AIFS */ - if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) - change_inx = _TRUE; - else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) { - /* compare TXOP */ - if ((edca[j] >> 16) > (edca[i] >> 16)) - change_inx = _TRUE; - } + if (len < ie_offset) { + RTW_ERR("%s: incorrect beacon length(%d)\n", __func__, len); + rtw_warn_on(1); + return _FALSE; + } - if (change_inx) { - tmp = edca[i]; - edca[i] = edca[j]; - edca[j] = tmp; + if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE) + return _FALSE; - tmp = inx[i]; - inx[i] = inx[j]; - inx[j] = tmp; + return _TRUE; +} - change_inx = _FALSE; - } - } - } - } - for (i = 0; i < 4; i++) { - pxmitpriv->wmm_para_seq[i] = inx[i]; - RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); - } - -#ifdef CONFIG_WMMPS_STA - /* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */ - if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) { - pqospriv->uapsd_ap_supported = 1; - rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL); - } -#endif /* CONFIG_WMMPS_STA */ - } -} - -static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ -#ifdef CONFIG_80211N_HT - unsigned char new_bwmode; - unsigned char new_ch_offset; - struct HT_info_element *pHT_info; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct registry_priv *pregistrypriv = &padapter->registrypriv; - struct ht_priv *phtpriv = &pmlmepriv->htpriv; - u8 cbw40_enable = 0; - - if (!pIE) - return; - - if (phtpriv->ht_option == _FALSE) - return; - - if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80) - return; - - if (pIE->Length > sizeof(struct HT_info_element)) - return; - - pHT_info = (struct HT_info_element *)pIE->data; - - if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { - if (pmlmeext->cur_channel > 14) { - if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) - cbw40_enable = 1; - } else { - if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) - cbw40_enable = 1; - } - } - - if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) { - new_bwmode = CHANNEL_WIDTH_40; - - switch (pHT_info->infos[0] & 0x3) { - case 1: - new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; - break; - - case 3: - new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; - break; - - default: - new_bwmode = CHANNEL_WIDTH_20; - new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - } - } else { - new_bwmode = CHANNEL_WIDTH_20; - new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - } - - - if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset) - && new_bwmode < pmlmeext->cur_bwmode - ) { - pmlmeinfo->bwmode_updated = _TRUE; - - pmlmeext->cur_bwmode = new_bwmode; - pmlmeext->cur_ch_offset = new_ch_offset; - - /* update HT info also */ - HT_info_handler(padapter, pIE); - } else - pmlmeinfo->bwmode_updated = _FALSE; - - - if (_TRUE == pmlmeinfo->bwmode_updated) { - struct sta_info *psta; - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - struct sta_priv *pstapriv = &padapter->stapriv; - - /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ - - - /* update ap's stainfo */ - psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); - if (psta) { - struct ht_priv *phtpriv_sta = &psta->htpriv; - - if (phtpriv_sta->ht_option) { - /* bwmode */ - psta->cmn.bw_mode = pmlmeext->cur_bwmode; - phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; - } else { - psta->cmn.bw_mode = CHANNEL_WIDTH_20; - phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - } - - rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); - } - - /* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */ - } -#endif /* CONFIG_80211N_HT */ -} - -#ifdef ROKU_PRIVATE -void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ - unsigned int i; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (pIE == NULL) - return; - - for (i = 0 ; i < pIE->Length; i++) - pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]); - -} - -void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ - unsigned int i, j; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (pIE == NULL) - return; - - if (pIE->Length > 0) { - for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { - if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) - break; - } - for (j = 0; j < pIE->Length; j++) - pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]); - } - -} - -void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss) -{ - u8 i, j; - u8 r_ss = 0, t_ss = 0; - - for (i = 0; i < 4; i++) { - if ((mcs_set[3-i] & 0xff) != 0x00) { - r_ss = 4-i; - break; - } - } - - *Rx_ss = r_ss; -} - -void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ - unsigned int i; - u8 cur_stbc_cap_infra_ap = 0; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; - - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (pIE == NULL) - return; - - pmlmeinfo->ht_vht_received |= BIT(0); - - /*copy MCS_SET*/ - for (i = 3; i < 19; i++) - phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]); - - /*get number of stream from mcs set*/ - HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap); - - phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data)); - - phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data); - - if (GET_HT_CAP_ELE_RX_STBC(pIE->data)) - SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX); - if (GET_HT_CAP_ELE_TX_STBC(pIE->data)) - SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX); - phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap; - - /*store ap info SGI 20m 40m*/ - phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data); - phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data); - - /*store ap info for supported channel bandwidth*/ - phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data); -} -#endif /* ROKU_PRIVATE */ - -void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ -#ifdef CONFIG_80211N_HT - unsigned int i; - u8 max_AMPDU_len, min_MPDU_spacing; - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rx_nss = 0; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct ht_priv *phtpriv = &pmlmepriv->htpriv; -#ifdef CONFIG_DISABLE_MCS13TO15 - struct registry_priv *pregistrypriv = &padapter->registrypriv; -#endif - - if (pIE == NULL) - return; - - if (phtpriv->ht_option == _FALSE) - return; - - pmlmeinfo->HT_caps_enable = 1; - - for (i = 0; i < (pIE->Length); i++) { - if (i != 2) { - /* Commented by Albert 2010/07/12 */ - /* Got the endian issue here. */ - pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]); - } else { - /* AMPDU Parameters field */ - - /* Get MIN of MAX AMPDU Length Exp */ - if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) - max_AMPDU_len = (pIE->data[i] & 0x3); - else - max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); - - /* Get MAX of MIN MPDU Start Spacing */ - if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) - min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); - else - min_MPDU_spacing = (pIE->data[i] & 0x1c); - - pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; - } - } - - /* Commented by Albert 2010/07/12 */ - /* Have to handle the endian issue after copying. */ - /* HT_ext_caps didn't be used yet. */ - pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); - pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps); - - /* update the MCS set */ - for (i = 0; i < 16; i++) - pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; - - rx_nss = GET_HAL_RX_NSS(padapter); - - switch (rx_nss) { - case 1: - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); - break; - case 2: - #ifdef CONFIG_DISABLE_MCS13TO15 - if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); - else - #endif - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); - break; - case 3: - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); - break; - case 4: - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); - break; - default: - RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss); - } - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - /* Config STBC setting */ - if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { - SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX); - RTW_INFO("Enable HT Tx STBC !\n"); - } - phtpriv->stbc_cap = cur_stbc_cap; - -#ifdef CONFIG_BEAMFORMING - /* Config Tx beamforming setting */ - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); - } - - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); - } - phtpriv->beamform_cap = cur_beamform_cap; - if (cur_beamform_cap) - RTW_INFO("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); -#endif /*CONFIG_BEAMFORMING*/ - } else { - /*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/ - /* Config LDPC Coding Capability */ - if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) { - SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx LDPC!\n"); - } - phtpriv->ldpc_cap = cur_ldpc_cap; - - /* Config STBC setting */ - if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { - SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx STBC!\n"); - } - phtpriv->stbc_cap = cur_stbc_cap; - -#ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 - /* Config beamforming setting */ - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); - } - - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); - } -#else /* !RTW_BEAMFORMING_VERSION_2 */ - /* Config Tx beamforming setting */ - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); - } - - if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); - } -#endif /* !RTW_BEAMFORMING_VERSION_2 */ - phtpriv->beamform_cap = cur_beamform_cap; - if (cur_beamform_cap) - RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); -#endif /*CONFIG_BEAMFORMING*/ - } - -#endif /* CONFIG_80211N_HT */ -} - -void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ -#ifdef CONFIG_80211N_HT - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct ht_priv *phtpriv = &pmlmepriv->htpriv; - - if (pIE == NULL) - return; - - if (phtpriv->ht_option == _FALSE) - return; - - - if (pIE->Length > sizeof(struct HT_info_element)) - return; - - pmlmeinfo->HT_info_enable = 1; - _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); -#endif /* CONFIG_80211N_HT */ - return; -} - -void HTOnAssocRsp(_adapter *padapter) -{ - unsigned char max_AMPDU_len; - unsigned char min_MPDU_spacing; - /* struct registry_priv *pregpriv = &padapter->registrypriv; */ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - RTW_INFO("%s\n", __FUNCTION__); - - if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) - pmlmeinfo->HT_enable = 1; - else { - pmlmeinfo->HT_enable = 0; - /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ - return; - } - - /* handle A-MPDU parameter field */ - /* - AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k - AMPDU_para [4:2]:Min MPDU Start Spacing - */ - max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; - - min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; - - rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); -#ifdef CONFIG_80211N_HT - rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); -#endif /* CONFIG_80211N_HT */ -#if 0 /* move to rtw_update_ht_cap() */ - if ((pregpriv->bw_mode > 0) && - (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && - (pmlmeinfo->HT_info.infos[0] & BIT(2))) { - /* switch to the 40M Hz mode accoring to the AP */ - pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; - switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) { - case EXTCHNL_OFFSET_UPPER: - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; - break; - - case EXTCHNL_OFFSET_LOWER: - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; - break; - - default: - pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - } - } -#endif - - /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ - -#if 0 /* move to rtw_update_ht_cap() */ - /* */ - /* Config SM Power Save setting */ - /* */ - pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; - if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) { -#if 0 - u8 i; - /* update the MCS rates */ - for (i = 0; i < 16; i++) - pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; -#endif - RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__); - } - - /* */ - /* Config current HT Protection mode. */ - /* */ - pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; -#endif - -} - -void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (pIE->Length > 1) - return; - - pmlmeinfo->ERP_enable = 1; - _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); -} - -void VCS_update(_adapter *padapter, struct sta_info *psta) -{ - struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */ - case 0: /* off */ - psta->rtsen = 0; - psta->cts2self = 0; - break; - - case 1: /* on */ - if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */ - psta->rtsen = 1; - psta->cts2self = 0; - } else { - psta->rtsen = 0; - psta->cts2self = 1; - } - break; - - case 2: /* auto */ - default: - if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) - /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ - ) { - if (pregpriv->vcs_type == 1) { - psta->rtsen = 1; - psta->cts2self = 0; - } else { - psta->rtsen = 0; - psta->cts2self = 1; - } - } else { - psta->rtsen = 0; - psta->cts2self = 0; - } - break; - } -} - -void update_ldpc_stbc_cap(struct sta_info *psta) -{ -#ifdef CONFIG_80211N_HT - -#ifdef CONFIG_80211AC_VHT - if (psta->vhtpriv.vht_option) { - if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) - psta->cmn.ldpc_en = VHT_LDPC_EN; - else - psta->cmn.ldpc_en = 0; - - if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX)) - psta->cmn.stbc_en = VHT_STBC_EN; - else - psta->cmn.stbc_en = 0; - } else -#endif /* CONFIG_80211AC_VHT */ - if (psta->htpriv.ht_option) { - if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) - psta->cmn.ldpc_en = HT_LDPC_EN; - else - psta->cmn.ldpc_en = 0; - - if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) - psta->cmn.stbc_en = HT_STBC_EN; - else - psta->cmn.stbc_en = 0; - } else { - psta->cmn.ldpc_en = 0; - psta->cmn.stbc_en = 0; - } - -#endif /* CONFIG_80211N_HT */ -} - -int check_ielen(u8 *start, uint len) -{ - int left = len; - u8 *pos = start; - u8 id, elen; - - while (left >= 2) { - id = *pos++; - elen = *pos++; - left -= 2; - - if (elen > left) { - RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n", - id, elen, (unsigned long) left); - return _FALSE; - } - if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3)) - return _FALSE; - - left -= elen; - pos += elen; - } - if (left) - return _FALSE; - - return _TRUE; -} - -int validate_beacon_len(u8 *pframe, u32 len) -{ - u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr); - - if (len < ie_offset) { - RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len); - return _FALSE; - } - - if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE) - return _FALSE; - - return _TRUE; -} - -#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT -u8 support_rate_ranges[] = { - IEEE80211_CCK_RATE_1MB, - IEEE80211_CCK_RATE_2MB, - IEEE80211_CCK_RATE_5MB, - IEEE80211_CCK_RATE_11MB, - IEEE80211_OFDM_RATE_6MB, - IEEE80211_OFDM_RATE_9MB, - IEEE80211_OFDM_RATE_12MB, - IEEE80211_OFDM_RATE_18MB, - IEEE80211_PBCC_RATE_22MB, - IEEE80211_FREAK_RATE_22_5MB, - IEEE80211_OFDM_RATE_24MB, - IEEE80211_OFDM_RATE_36MB, - IEEE80211_OFDM_RATE_48MB, - IEEE80211_OFDM_RATE_54MB, -}; - -inline bool match_ranges(u16 EID, u32 value) -{ - int i; - int nr_range; - - switch (EID) { - case _EXT_SUPPORTEDRATES_IE_: - case _SUPPORTEDRATES_IE_: - nr_range = sizeof(support_rate_ranges)/sizeof(u8); - for (i = 0; i < nr_range; i++) { - /* clear bit7 before searching. */ - value &= ~BIT(7); - if (value == support_rate_ranges[i]) - return _TRUE; - } - break; - default: - break; - }; - return _FALSE; -} - -/* - * rtw_validate_value: validate the IE contain. - * - * Input : - * EID : Element ID - * p : IE buffer (without EID & length) - * len : IE length - * return: - * _TRUE : All Values are validated. - * _FALSE : At least one value is NOT validated. - */ -bool rtw_validate_value(u16 EID, u8 *p, u16 len) -{ - u8 rate; - u32 i, nr_val; - - switch (EID) { - case _EXT_SUPPORTEDRATES_IE_: - case _SUPPORTEDRATES_IE_: - nr_val = len; - for (i=0; iSsid.Ssid, snetwork->Ssid.SsidLength); -} - -/* - Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP. - Update the SSID to the corresponding pnetwork in scan queue. -*/ -void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe) -{ - struct wlan_network *scanned = NULL; - WLAN_BSSID_EX *snetwork; - u8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe); - sint ssid_len_ori; - u32 remain_len = 0; - u8 backupIE[MAX_IE_SZ]; - u16 subtype = get_frame_sub_type(pframe); - _irqL irqL; - - if (subtype == WIFI_BEACON) { - bssid->Reserved[0] = BSS_TYPE_BCN; - ie_offset = _BEACON_IE_OFFSET_; - } else { - /* FIXME : more type */ - if (subtype == WIFI_PROBERSP) { - ie_offset = _PROBERSP_IE_OFFSET_; - bssid->Reserved[0] = BSS_TYPE_PROB_RSP; - } else if (subtype == WIFI_PROBEREQ) { - ie_offset = _PROBEREQ_IE_OFFSET_; - bssid->Reserved[0] = BSS_TYPE_PROB_REQ; - } else { - bssid->Reserved[0] = BSS_TYPE_UNDEF; - ie_offset = _FIXED_IE_LENGTH_; - } - } - - _enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); - scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac); - if (!scanned) { - _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); - return; - } - - snetwork = &(scanned->network); - /* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID */ - if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) { - p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset); - if (!p) { - _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); - return; - } - next_ie = p + 2 + ssid_len_ori; - remain_len = snetwork->IELength - (next_ie - snetwork->IEs); - scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength; - _rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); - - //update pnetwork->ssid, pnetwork->ssidlen - _rtw_memcpy(backupIE, next_ie, remain_len); - *(p+1) = bssid->Ssid.SsidLength; - _rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); - _rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len); - snetwork->IELength += bssid->Ssid.SsidLength; - } - _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); -} - -#ifdef DBG_RX_BCN -void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len) -{ - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info); - u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4; - u64 tsf, tsf_offset; - u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit; - - update_TSF(pmlmeext, pframe, packet_len); - tsf = pmlmeext->TSFValue; - tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)); - - /*get TIM IE*/ - /*DTIM Count*/ - dtim_cnt = pmlmeext->tim[0]; - /*DTIM Period*/ - dtim_period = pmlmeext->tim[1]; - /*Bitmap*/ - tim_bmap = pmlmeext->tim[2]; - /*Partial VBitmap AID 0 ~ 7*/ - tim_pvbit = pmlmeext->tim[3]; - - RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n", - sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit); -} -#endif - -/* - * rtw_get_bcn_keys: get beacon keys from recv frame - * - * TODO: - * WLAN_EID_COUNTRY - * WLAN_EID_ERP_INFO - * WLAN_EID_CHANNEL_SWITCH - * WLAN_EID_PWR_CONSTRAINT - */ -int _rtw_get_bcn_keys(u8 *cap_info, u32 buf_len, u8 def_ch, ADAPTER *adapter - , struct beacon_keys *recv_beacon) -{ - int left; - u16 capability; - unsigned char *pos; - struct rtw_ieee802_11_elems elems; - - _rtw_memset(recv_beacon, 0, sizeof(*recv_beacon)); - - /* checking capabilities */ - capability = le16_to_cpu(*(unsigned short *)(cap_info)); - - /* checking IEs */ - left = buf_len - 2; - pos = cap_info + 2; - if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) - return _FALSE; - - if (elems.ht_capabilities) { - if (elems.ht_capabilities_len != 26) - return _FALSE; - } - - if (elems.ht_operation) { - if (elems.ht_operation_len != 22) - return _FALSE; - } - - if (elems.vht_capabilities) { - if (elems.vht_capabilities_len != 12) - return _FALSE; - } - - if (elems.vht_operation) { - if (elems.vht_operation_len != 5) - return _FALSE; - } - - if (rtw_ies_get_supported_rate(pos, left, recv_beacon->rate_set, &recv_beacon->rate_num) == _FAIL) - return _FALSE; - - if (cckratesonly_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE) - recv_beacon->proto_cap |= PROTO_CAP_11B; - else if (cckrates_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE) - recv_beacon->proto_cap |= PROTO_CAP_11B | PROTO_CAP_11G; - else - recv_beacon->proto_cap |= PROTO_CAP_11G; - - if (elems.ht_capabilities && elems.ht_operation) - recv_beacon->proto_cap |= PROTO_CAP_11N; - - if (elems.vht_capabilities && elems.vht_operation) - recv_beacon->proto_cap |= PROTO_CAP_11AC; - - /* check bw and channel offset */ - rtw_ies_get_chbw(pos, left, &recv_beacon->ch, &recv_beacon->bw, &recv_beacon->offset, 1, 1); - if (!recv_beacon->ch) - recv_beacon->ch = def_ch; - - /* checking SSID */ - if (elems.ssid) { - if (elems.ssid_len > sizeof(recv_beacon->ssid)) - return _FALSE; - - _rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len); - recv_beacon->ssid_len = elems.ssid_len; - } - - /* checking RSN first */ - if (elems.rsn_ie && elems.rsn_ie_len) { - recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2; - rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, - &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, - NULL, &recv_beacon->akm, NULL, NULL); - } - /* checking WPA secon */ - else if (elems.wpa_ie && elems.wpa_ie_len) { - recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA; - rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2, - &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, - &recv_beacon->akm); - } else if (capability & BIT(4)) - recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP; - - if (adapter) { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - - if (elems.tim && elems.tim_len) { - #ifdef DBG_RX_BCN - _rtw_memcpy(pmlmeext->tim, elems.tim, 4); - #endif - pmlmeext->dtim = elems.tim[1]; - } - - /* checking RTW TBTX */ - #ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (elems.tbtx_cap && elems.tbtx_cap_len) { - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) - RTW_DBG("AP support TBTX\n"); - } - #endif - } - - return _TRUE; -} - -int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys) -{ - return _rtw_get_bcn_keys( - whdr + WLAN_HDR_A3_LEN + 10 - , flen - WLAN_HDR_A3_LEN - 10 - , adapter->mlmeextpriv.cur_channel, adapter - , bcn_keys); -} - -int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys) -{ - return _rtw_get_bcn_keys( - bss->IEs + 10 - , bss->IELength - 10 - , bss->Configuration.DSConfig, NULL - , bcn_keys); -} - -int rtw_update_bcn_keys_of_network(struct wlan_network *network) -{ - network->bcn_keys_valid = rtw_get_bcn_keys_from_bss(&network->network, &network->bcn_keys); - return network->bcn_keys_valid; -} - -void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon) -{ -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) - u8 ssid[IW_ESSID_MAX_SIZE + 1]; - - _rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len); - ssid[recv_beacon->ssid_len] = '\0'; - - RTW_PRINT_SEL(sel, "ssid = %s (len = %u)\n", ssid, recv_beacon->ssid_len); - RTW_PRINT_SEL(sel, "ch = %u,%u,%u\n" - , recv_beacon->ch, recv_beacon->bw, recv_beacon->offset); - RTW_PRINT_SEL(sel, "proto_cap = 0x%02x\n", recv_beacon->proto_cap); - RTW_MAP_DUMP_SEL(sel, "rate_set = " - , recv_beacon->rate_set, recv_beacon->rate_num); - RTW_PRINT_SEL(sel, "sec = %d, group = 0x%x, pair = 0x%x, akm = 0x%08x\n" - , recv_beacon->encryp_protocol, recv_beacon->group_cipher - , recv_beacon->pairwise_cipher, recv_beacon->akm); -#endif -} - -void rtw_bcn_key_err_fix(struct beacon_keys *cur, struct beacon_keys *recv) -{ - if ((recv->ch == cur->ch) && (recv->bw == cur->bw) && (recv->bw > CHANNEL_WIDTH_20)) { - if ((recv->offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) - && (cur->offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { - RTW_DBG("recv_bcn offset = %d is invalid, try to use cur_bcn offset = %d to replace it !\n", recv->offset, cur->offset); - recv->offset = cur->offset; - } - } -} - -bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv) -{ -#define BCNKEY_VERIFY_PROTO_CAP 0 -#define BCNKEY_VERIFY_WHOLE_RATE_SET 0 - - struct beacon_keys tmp; - bool ret = _FALSE; - - if (!rtw_is_chbw_grouped(cur->ch, cur->bw, cur->offset - , recv->ch, recv->bw, recv->offset)) - goto exit; - - _rtw_memcpy(&tmp, cur, sizeof(tmp)); - - /* check fields excluding below */ - tmp.ch = recv->ch; - tmp.bw = recv->bw; - tmp.offset = recv->offset; - if (!BCNKEY_VERIFY_PROTO_CAP) - tmp.proto_cap = recv->proto_cap; - if (!BCNKEY_VERIFY_WHOLE_RATE_SET) { - tmp.rate_num = recv->rate_num; - _rtw_memcpy(tmp.rate_set, recv->rate_set, 12); - } - - if (_rtw_memcmp(&tmp, recv, sizeof(*recv)) == _FALSE) - goto exit; - - ret = _TRUE; - -exit: - return ret; -} - -int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) -{ - u8 *pbssid = GetAddr3Ptr(pframe); - struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); - struct beacon_keys *cur_beacon = &pmlmepriv->cur_beacon_keys; - struct beacon_keys recv_beacon; - int ret = 0; - u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(Adapter); - u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(Adapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); - _adapter *pri_adapter = dvobj_get_primary_adapter(dvobj); - struct mlme_ext_priv *pmlmeext = &pri_adapter->mlmeextpriv; - - if (is_client_associated_to_ap(Adapter) == _FALSE) - goto exit_success; - - if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE) - goto exit_success; /* parsing failed => broken IE */ - -#ifdef DBG_RX_BCN - rtw_debug_rx_bcn(Adapter, pframe, packet_len); -#endif - - /* hidden ssid, replace with current beacon ssid directly */ - if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) { - _rtw_memcpy(recv_beacon.ssid, cur_beacon->ssid, cur_beacon->ssid_len); - recv_beacon.ssid_len = cur_beacon->ssid_len; - } - - if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) { - u8 u_ch, u_offset, u_bw; - struct sta_info *psta = NULL; - _rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon)); - clr_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON); - rtw_mi_get_ch_setting_union(Adapter, &u_ch, &u_bw, &u_offset); - - /* RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d \n", u_ch, u_bw, u_offset); - RTW_INFO("recv_beacon.ch=%d, recv_beacon.bw=%d, recv_beacon.offset=%d \n", recv_beacon.ch, recv_beacon.bw, recv_beacon.offset); */ - /* rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon); */ - - /* RTW_INFO("_cancel_timer_async csa_timer\n"); */ - _cancel_timer_async(&pmlmeext->csa_timer); - - /* beacon bw/offset is different from CSA IE */ - if((recv_beacon.bw > u_bw) || - ((recv_beacon.offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) && ((u_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)) - && (recv_beacon.offset != u_offset))) { - - /* update ch, bw, offset for all asoc STA ifaces */ - if (ifbmp_s) { - _adapter *iface; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface || !(ifbmp_s & BIT(iface->iface_id))) - continue; - - iface->mlmeextpriv.cur_channel = recv_beacon.ch; - iface->mlmeextpriv.cur_bwmode = recv_beacon.bw; - iface->mlmeextpriv.cur_ch_offset = recv_beacon.offset; - iface->mlmepriv.cur_network.network.Configuration.DSConfig = recv_beacon.ch; - } - } - -#ifdef CONFIG_AP_MODE - if (ifbmp_m) { - rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), 0 - , ifbmp_m, 0, recv_beacon.ch, REQ_BW_ORI, REQ_OFFSET_NONE); - } else -#endif - { - #ifdef CONFIG_DFS_MASTER - rtw_dfs_rd_en_decision(dvobj_get_primary_adapter(dvobj), MLME_OPCH_SWITCH, 0); - #endif - rtw_set_chbw_cmd(Adapter, recv_beacon.ch, recv_beacon.bw, recv_beacon.offset, 0); - } - rtw_mi_get_ch_setting_union(Adapter, &u_ch, &u_bw, &u_offset); - - /* RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d \n", u_ch, u_bw, u_offset); */ - } else { - RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d, recv_beacon.ch=%d, recv_beacon.bw=%d, recv_beacon.offset=%d\n" - , u_ch, u_bw, u_offset, recv_beacon.ch, recv_beacon.bw, recv_beacon.offset); - } - - rtw_iqk_cmd(Adapter, 0); - psta = rtw_get_stainfo(&Adapter->stapriv, get_bssid(&Adapter->mlmepriv)); - if (psta) - rtw_dm_ra_mask_wk_cmd(Adapter, (u8 *)psta); - - } - -#ifdef CONFIG_BCN_CNT_CONFIRM_HDL - if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _TRUE) - pmlmepriv->new_beacon_cnts = 0; - else if ((pmlmepriv->new_beacon_cnts == 0) || - _rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) { - RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe)); - - if (pmlmepriv->new_beacon_cnts == 0) { - RTW_ERR("%s: cur beacon key\n", __func__); - RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon)); - } - - RTW_DBG("%s: new beacon key\n", __func__); - RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon)); - - _rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); - pmlmepriv->new_beacon_cnts = 1; - } else { - RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); - pmlmepriv->new_beacon_cnts++; - } - - /* if counter >= max, it means beacon is changed really */ - if (pmlmepriv->new_beacon_cnts >= new_bcn_max) -#else - if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _FALSE) -#endif - { - RTW_INFO(FUNC_ADPT_FMT" new beacon occur!!\n", FUNC_ADPT_ARG(Adapter)); - RTW_INFO(FUNC_ADPT_FMT" cur beacon key:\n", FUNC_ADPT_ARG(Adapter)); - rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon); - RTW_INFO(FUNC_ADPT_FMT" new beacon key:\n", FUNC_ADPT_ARG(Adapter)); - rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon); - - rtw_bcn_key_err_fix(cur_beacon, &recv_beacon); - - if (rtw_bcn_key_compare(cur_beacon, &recv_beacon) == _FALSE) - goto exit; - - _rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon)); - #ifdef CONFIG_BCN_CNT_CONFIRM_HDL - pmlmepriv->new_beacon_cnts = 0; - #endif - } - -exit_success: - ret = 1; - -exit: - return ret; -} - -void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) -{ - unsigned int i; - unsigned int len; - PNDIS_802_11_VARIABLE_IEs pIE; - -#ifdef CONFIG_TDLS - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */ -#endif /* CONFIG_TDLS */ - - len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); - - for (i = 0; i < len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); - - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - /* to update WMM paramter set while receiving beacon */ - if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN) /* WMM */ - (WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0; - - break; - - case _HT_EXTRA_INFO_IE_: /* HT info */ - /* HT_info_handler(padapter, pIE); */ - bwmode_update_check(padapter, pIE); - break; -#ifdef CONFIG_80211AC_VHT - case EID_OpModeNotification: - rtw_process_vht_op_mode_notify(padapter, pIE->data, psta); - break; -#endif /* CONFIG_80211AC_VHT */ - case _ERPINFO_IE_: - ERP_IE_handler(padapter, pIE); - VCS_update(padapter, psta); - break; - -#ifdef CONFIG_TDLS - case _EXT_CAP_IE_: - if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE) - ptdlsinfo->ap_prohibited = _TRUE; - if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE) - ptdlsinfo->ch_switch_prohibited = _TRUE; - break; -#endif /* CONFIG_TDLS */ - default: - break; - } - - i += (pIE->Length + 2); - } -} - -#if CONFIG_DFS -void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len) -{ - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - unsigned int i, j, countdown; - PNDIS_802_11_VARIABLE_IEs pIE, sub_pie; - u8 ch = 0, csa_ch_offset = 0, csa_ch_width = 0, csa_ch_freq_seg0 = 0, csa_ch_freq_seg1 = 0, csa_switch_cnt = 0; - - /* TODO: compare with scheduling CSA */ - if (rfctl->csa_ch) - return; - - for (i = 0; i + 1 < ies_len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i); - - switch (pIE->ElementID) { - case _CH_SWTICH_ANNOUNCE_: - ch = *(pIE->data + 1); - csa_switch_cnt = *(pIE->data + 2); - break; - case WLAN_EID_SECONDARY_CHANNEL_OFFSET: - csa_ch_offset = *(pIE->data); - break; - case WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH: - csa_ch_width = *(pIE->data); - csa_ch_freq_seg0 = *(pIE->data+1); - csa_ch_freq_seg1 = *(pIE->data+2); - /* RTW_INFO("bw:%02x center_freq_0:%d center_freq_1:%d, ch=%d\n" - , csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); */ - break; - case WLAN_EID_CHANNEL_SWITCH_WRAPPER: - for(j=0; j + 1 < pIE->Length;) { - sub_pie = (PNDIS_802_11_VARIABLE_IEs)(ies + i + j + 2); - if(sub_pie->ElementID == WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH) { - csa_ch_width = *(sub_pie->data); - csa_ch_freq_seg0 = *(sub_pie->data+1); - csa_ch_freq_seg1 = *(sub_pie->data+2); - /* RTW_INFO("2. sub_IE:%02x IE_length:%02x bw:%02x center_freq_0:%d center_freq_1:%d, ch=%d\n" - , sub_pie->ElementID, sub_pie->Length, csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); */ - } - j += (sub_pie->Length + 2); - } - - break; - default: - break; - } - - i += (pIE->Length + 2); - } - - if (ch != 0) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *pri_adapter = dvobj_get_primary_adapter(dvobj); - - rfctl->csa_ch = ch; - rfctl->csa_switch_cnt = csa_switch_cnt; - rfctl->csa_ch_offset = csa_ch_offset; - rfctl->csa_ch_width = csa_ch_width; - rfctl->csa_ch_freq_seg0 = csa_ch_freq_seg0; - rfctl->csa_ch_freq_seg1 = csa_ch_freq_seg1; - - countdown = pmlmeinfo->network.Configuration.BeaconPeriod * (csa_switch_cnt+1); /* ms */ - RTW_INFO("csa: set countdown timer to %d ms\n", countdown); - _set_timer(&pri_adapter->mlmeextpriv.csa_timer, countdown); - - } -} -#endif /* CONFIG_DFS */ - -enum eap_type parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type) -{ - struct security_priv *psecuritypriv = &(padapter->securitypriv); - struct ieee802_1x_hdr *hdr; - struct wpa_eapol_key *key; - u16 key_info, key_data_length; - char *trx_msg = trx_type ? "send" : "recv"; - enum eap_type eapol_type; - - hdr = (struct ieee802_1x_hdr *) key_payload; - - /* WPS - eapol start packet */ - if (hdr->type == 1 && hdr->length == 0) { - RTW_INFO("%s eapol start packet\n", trx_msg); - return EAPOL_START; - } - - if (hdr->type == 0) { /* WPS - eapol packet */ - RTW_INFO("%s eapol packet\n", trx_msg); - return EAPOL_PACKET; - } - - key = (struct wpa_eapol_key *) (hdr + 1); - key_info = be16_to_cpu(*((u16 *)(key->key_info))); - key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length))); - - if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */ - if (key_info & WPA_KEY_INFO_ACK) { - RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg); - eapol_type = EAPOL_WPA_GROUP_KEY_1_2; - } else { - RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg); - eapol_type = EAPOL_WPA_GROUP_KEY_2_2; - - /* WPA key-handshake has completed */ - if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK) - psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); - } - } else if (key_info & WPA_KEY_INFO_MIC) { - if (key_data_length == 0) { - RTW_PRINT("%s eapol packet 4/4\n", trx_msg); - eapol_type = EAPOL_4_4; - } else if (key_info & WPA_KEY_INFO_ACK) { - RTW_PRINT("%s eapol packet 3/4\n", trx_msg); - eapol_type = EAPOL_3_4; - } else { - RTW_PRINT("%s eapol packet 2/4\n", trx_msg); - eapol_type = EAPOL_2_4; - } - } else { - RTW_PRINT("%s eapol packet 1/4\n", trx_msg); - eapol_type = EAPOL_1_4; - } - - return eapol_type; -} - -unsigned int is_ap_in_tkip(_adapter *padapter) -{ - u32 i; - PNDIS_802_11_VARIABLE_IEs pIE; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - - if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); - - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) - return _TRUE; - break; - - case _RSN_IE_2_: - if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) - return _TRUE; - - default: - break; - } - - i += (pIE->Length + 2); - } - - return _FALSE; - } else - return _FALSE; - -} - -unsigned int should_forbid_n_rate(_adapter *padapter) -{ - u32 i; - PNDIS_802_11_VARIABLE_IEs pIE; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - WLAN_BSSID_EX *cur_network = &pmlmepriv->cur_network.network; - - if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i); - - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) && - ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) || - (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4)))) - return _FALSE; - break; - - case _RSN_IE_2_: - if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4)) || - (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4))) - return _FALSE; - - default: - break; - } - - i += (pIE->Length + 2); - } - - return _TRUE; - } else - return _FALSE; - -} - - -unsigned int is_ap_in_wep(_adapter *padapter) -{ - u32 i; - PNDIS_802_11_VARIABLE_IEs pIE; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - - if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); - - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) - return _FALSE; - break; - - case _RSN_IE_2_: - return _FALSE; - - default: - break; - } - - i += (pIE->Length + 2); - } - - return _TRUE; - } else - return _FALSE; - -} - -int wifirate2_ratetbl_inx(unsigned char rate); -int wifirate2_ratetbl_inx(unsigned char rate) -{ - int inx = 0; - rate = rate & 0x7f; - - switch (rate) { - case 54*2: - inx = 11; - break; - - case 48*2: - inx = 10; - break; - - case 36*2: - inx = 9; - break; - - case 24*2: - inx = 8; - break; - - case 18*2: - inx = 7; - break; - - case 12*2: - inx = 6; - break; - - case 9*2: - inx = 5; - break; - - case 6*2: - inx = 4; - break; - - case 11*2: - inx = 3; - break; - case 11: - inx = 2; - break; - - case 2*2: - inx = 1; - break; - - case 1*2: - inx = 0; - break; - - } - return inx; -} - -unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz) -{ - unsigned int i, num_of_rate; - unsigned int mask = 0; - - num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz; - - for (i = 0; i < num_of_rate; i++) { - if ((*(ptn + i)) & 0x80) - mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); - } - return mask; -} - -unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) -{ - unsigned int i, num_of_rate; - unsigned int mask = 0; - - num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz; - - for (i = 0; i < num_of_rate; i++) - mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); - - return mask; -} - -int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode) -{ - unsigned char bit_offset; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if (!(pmlmeinfo->HT_enable)) - return _FAIL; - - bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5; - - if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset)) - return _SUCCESS; - else - return _FAIL; -} - -unsigned char get_highest_rate_idx(u64 mask) -{ - int i; - unsigned char rate_idx = 0; - - for (i = 63; i >= 0; i--) { - if ((mask >> i) & 0x01) { - rate_idx = i; - break; - } - } - - return rate_idx; -} -unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit) -{ - int i; - unsigned char rate_idx = 0; - - for (i = start_bit; i < 64; i++) { - if ((mask >> i) & 0x01) { - rate_idx = i; - break; - } - } - - return rate_idx; -} - -void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) -{ - rtw_hal_update_ra_mask(psta); -} - -void set_sta_rate(_adapter *padapter, struct sta_info *psta) -{ - /* rate adaptive */ - rtw_hal_update_ra_mask(psta); -} - -/* Update RRSR and Rate for USERATE */ -void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode) -{ - NDIS_802_11_RATES_EX supported_rates; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; - - /* Added by Albert 2011/03/22 */ - /* In the P2P mode, the driver should not support the b mode. */ - /* So, the Tx packet shouldn't use the CCK rate */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - return; -#endif /* CONFIG_P2P */ - - _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX); - - /* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */ - if (pmlmeext->cur_channel > 14) - wirelessmode &= ~(WIRELESS_11B); - - if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B)) - _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4); - else if (wirelessmode & WIRELESS_11B) - _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7); - else - _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3); - - if (wirelessmode & WIRELESS_11B) - update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); - else - update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); - - rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates); -} - -unsigned char check_assoc_AP(u8 *pframe, uint len) -{ - unsigned int i; - PNDIS_802_11_VARIABLE_IEs pIE; - - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); - - switch (pIE->ElementID) { - case _VENDOR_SPECIFIC_IE_: - if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) { - RTW_INFO("link to Artheros AP\n"); - return HT_IOT_PEER_ATHEROS; - } else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) - || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) - || (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) { - RTW_INFO("link to Broadcom AP\n"); - return HT_IOT_PEER_BROADCOM; - } else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) { - RTW_INFO("link to Marvell AP\n"); - return HT_IOT_PEER_MARVELL; - } else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) { - RTW_INFO("link to Ralink AP\n"); - return HT_IOT_PEER_RALINK; - } else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) { - RTW_INFO("link to Cisco AP\n"); - return HT_IOT_PEER_CISCO; - } else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) { - u32 Vender = HT_IOT_PEER_REALTEK; - - if (pIE->Length >= 5) { - if (pIE->data[4] == 1) { - /* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */ - /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */ - - if (pIE->data[5] & RT_HT_CAP_USE_92SE) { - /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */ - Vender = HT_IOT_PEER_REALTEK_92SE; - } - } - - if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP) - Vender = HT_IOT_PEER_REALTEK_SOFTAP; - - if (pIE->data[4] == 2) { - if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) { - Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP; - RTW_INFO("link to Realtek JAGUAR_BCUTAP\n"); - } - if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) { - Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP; - RTW_INFO("link to Realtek JAGUAR_CCUTAP\n"); - } - } - } - - RTW_INFO("link to Realtek AP\n"); - return Vender; - } else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) { - RTW_INFO("link to Airgo Cap\n"); - return HT_IOT_PEER_AIRGO; - } else - break; - - default: - break; - } - - i += (pIE->Length + 2); - } - - RTW_INFO("link to new AP\n"); - return HT_IOT_PEER_UNKNOWN; -} - -void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor) -{ - switch (assoc_AP_vendor) { - - case HT_IOT_PEER_UNKNOWN: - sprintf(vendor, "%s", "unknown"); - break; - - case HT_IOT_PEER_REALTEK: - case HT_IOT_PEER_REALTEK_92SE: - case HT_IOT_PEER_REALTEK_SOFTAP: - case HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP: - case HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP: - - sprintf(vendor, "%s", "Realtek"); - break; - - case HT_IOT_PEER_BROADCOM: - sprintf(vendor, "%s", "Broadcom"); - break; - - case HT_IOT_PEER_MARVELL: - sprintf(vendor, "%s", "Marvell"); - break; - - case HT_IOT_PEER_RALINK: - sprintf(vendor, "%s", "Ralink"); - break; - - case HT_IOT_PEER_CISCO: - sprintf(vendor, "%s", "Cisco"); - break; - - case HT_IOT_PEER_AIRGO: - sprintf(vendor, "%s", "Airgo"); - break; - - case HT_IOT_PEER_ATHEROS: - sprintf(vendor, "%s", "Atheros"); - break; - - default: - sprintf(vendor, "%s", "unkown"); - break; - } - -} -#ifdef CONFIG_RTS_FULL_BW -void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) -{ - unsigned char REALTEK_OUI[] = {0x00,0xe0, 0x4c}; - u8 *p; - - p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, REALTEK_OUI, 3, NULL, NULL); - if (!p) - goto exit; - else { - if(*(p+1) > 6 ) { - - if(*(p+6) != 2) - goto exit; - - if(*(p+8) == RT_HT_CAP_USE_JAGUAR_BCUT) - sta->vendor_8812 = TRUE; - else if (*(p+8) == RT_HT_CAP_USE_JAGUAR_CCUT) - sta->vendor_8812 = TRUE; - } - } -exit: - return; -} -#endif/*CONFIG_RTS_FULL_BW*/ - -#ifdef CONFIG_80211AC_VHT -void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap) -{ - unsigned int i; - PNDIS_802_11_VARIABLE_IEs pIE; - - for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); - - switch (pIE->ElementID) { - - case EID_VHTCapability: - bf_cap->is_mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data); - bf_cap->su_sound_dim = GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data); - break; - default: - break; - } - i += (pIE->Length + 2); - } -} -#endif +u8 support_rate_ranges[] = { + IEEE80211_CCK_RATE_1MB, + IEEE80211_CCK_RATE_2MB, + IEEE80211_CCK_RATE_5MB, + IEEE80211_CCK_RATE_11MB, + IEEE80211_OFDM_RATE_6MB, + IEEE80211_OFDM_RATE_9MB, + IEEE80211_OFDM_RATE_12MB, + IEEE80211_OFDM_RATE_18MB, + IEEE80211_PBCC_RATE_22MB, + IEEE80211_FREAK_RATE_22_5MB, + IEEE80211_OFDM_RATE_24MB, + IEEE80211_OFDM_RATE_36MB, + IEEE80211_OFDM_RATE_48MB, + IEEE80211_OFDM_RATE_54MB, +}; -void update_capinfo(PADAPTER Adapter, u16 updateCap) +inline bool match_ranges(u16 EID, u32 value) { - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - BOOLEAN ShortPreamble; - - /* Check preamble mode, 2005.01.06, by rcnjko. */ - /* Mark to update preamble value forever, 2008.03.18 by lanhsin */ - /* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */ - { - - if (updateCap & cShortPreamble) { - /* Short Preamble */ - if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */ - ShortPreamble = _TRUE; - pmlmeinfo->preamble_mode = PREAMBLE_SHORT; - rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); - } - } else { - /* Long Preamble */ - if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */ - ShortPreamble = _FALSE; - pmlmeinfo->preamble_mode = PREAMBLE_LONG; - rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); - } - } - } + int i; + int nr_range; - if (updateCap & cIBSS) { - /* Filen: See 802.11-2007 p.91 */ - pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; - } else { - /* Filen: See 802.11-2007 p.90 */ - if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC)) - pmlmeinfo->slotTime = SHORT_SLOT_TIME; - else if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) { - if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) { - /* Short Slot Time */ - pmlmeinfo->slotTime = SHORT_SLOT_TIME; - } else { - /* Long Slot Time */ - pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; - } - } else { - /* B Mode */ - pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + switch (EID) { + case _EXT_SUPPORTEDRATES_IE_: + case _SUPPORTEDRATES_IE_: + nr_range = sizeof(support_rate_ranges)/sizeof(u8); + for (i = 0; i < nr_range; i++) { + /* clear bit7 before searching. */ + value &= ~BIT(7); + if (value == support_rate_ranges[i]) + return _TRUE; } - } - - rtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime); - + break; + default: + break; + }; + return _FALSE; } /* -* set adapter.mlmeextpriv.mlmext_info.HT_enable -* set adapter.mlmeextpriv.cur_wireless_mode -* set SIFS register -* set mgmt tx rate -*/ -void update_wireless_mode(_adapter *padapter) + * rtw_validate_value: validate the IE contain. + * + * Input : + * EID : Element ID + * p : IE buffer (without EID & length) + * len : IE length + * return: + * _TRUE : All Values are validated. + * _FALSE : At least one value is NOT validated. + */ +bool rtw_validate_value(u16 EID, u8 *p, u16 len) { - int ratelen, network_type = 0; - u32 SIFS_Timer; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - unsigned char *rate = cur_network->SupportedRates; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ - - ratelen = rtw_get_rateset_len(cur_network->SupportedRates); - - if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) - pmlmeinfo->HT_enable = 1; - - if (pmlmeext->cur_channel > 14) { - if (pmlmeinfo->VHT_enable) - network_type = WIRELESS_11AC; - else if (pmlmeinfo->HT_enable) - network_type = WIRELESS_11_5N; - - network_type |= WIRELESS_11A; - } else { - if (pmlmeinfo->VHT_enable) - network_type = WIRELESS_11AC; - else if (pmlmeinfo->HT_enable) - network_type = WIRELESS_11_24N; - - if ((cckratesonly_included(rate, ratelen)) == _TRUE) - network_type |= WIRELESS_11B; - else if ((cckrates_included(rate, ratelen)) == _TRUE) - network_type |= WIRELESS_11BG; - else - network_type |= WIRELESS_11G; - } - - pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; - /* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */ - -#ifndef RTW_HALMAC - /* HALMAC IC do not set HW_VAR_RESP_SIFS here */ -#if 0 - if ((pmlmeext->cur_wireless_mode == WIRELESS_11G) || - (pmlmeext->cur_wireless_mode == WIRELESS_11BG)) /* WIRELESS_MODE_G) */ - SIFS_Timer = 0x0a0a;/* CCK */ - else - SIFS_Timer = 0x0e0e;/* pHalData->SifsTime; //OFDM */ -#endif - - SIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM - * change this value if having IOT issues. */ - - rtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer); -#endif - - rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode)); + u8 rate; + u32 i, nr_val; - if ((pmlmeext->cur_wireless_mode & WIRELESS_11B) - #ifdef CONFIG_P2P - && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) - #ifdef CONFIG_IOCTL_CFG80211 - || !rtw_cfg80211_iface_has_p2p_group_cap(padapter) - #endif - ) - #endif - ) - update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); - else - update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); + switch (EID) { + case _EXT_SUPPORTEDRATES_IE_: + case _SUPPORTEDRATES_IE_: + nr_val = len; + for (i=0; icmdpriv); - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) - return; - - pwriteMacPara = (struct reg_rw_parm *)rtw_malloc(sizeof(struct reg_rw_parm)); - if (pwriteMacPara == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - return; - } - - pwriteMacPara->rw = 1; - pwriteMacPara->addr = addr; - pwriteMacPara->value = value; - - init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG)); - rtw_enqueue_cmd(pcmdpriv, ph2c); -#endif + return len == 0 || is_all_null(ssid, len) == _TRUE; } -void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode) +inline bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork) { - if (IsSupportedTxCCK(wireless_mode)) { - /* Only B, B/G, and B/G/N AP could use CCK rate */ - _rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4); - psta->bssratelen = 4; - } else { - _rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3); - psta->bssratelen = 3; - } + return ((snetwork->Ssid.SsidLength == 0) || + is_all_null(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength) == _TRUE); } -int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num) +/* + Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP. + Update the SSID to the corresponding pnetwork in scan queue. +*/ +void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe) { - u8 *ie, *p; - unsigned int ie_len; - int i, j; - - struct support_rate_handler support_rate_tbl[] = { - {IEEE80211_CCK_RATE_1MB, _FALSE, _FALSE}, - {IEEE80211_CCK_RATE_2MB, _FALSE, _FALSE}, - {IEEE80211_CCK_RATE_5MB, _FALSE, _FALSE}, - {IEEE80211_CCK_RATE_11MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_6MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_9MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_12MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_18MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_24MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_36MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_48MB, _FALSE, _FALSE}, - {IEEE80211_OFDM_RATE_54MB, _FALSE, _FALSE}, - }; - - if (!rate_set || !rate_num) - return _FALSE; + struct wlan_network *scanned = NULL; + WLAN_BSSID_EX *snetwork; + u8 ie_offset, *p=NULL, *next_ie=NULL; + u8 *mac; + sint ssid_len_ori; + u32 remain_len = 0; + u8 backupIE[MAX_IE_SZ]; + u16 subtype; - *rate_num = 0; - ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len); - if (ie == NULL) - goto ext_rate; + mac = get_addr2_ptr(pframe); + subtype = get_frame_sub_type(pframe); - /* get valid supported rates */ - for (i = 0; i < 12; i++) { - p = ie + 2; - for (j = 0; j < ie_len; j++) { - if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ - support_rate_tbl[i].existence = _TRUE; - if ((*p) & BIT(7)) - support_rate_tbl[i].basic = _TRUE; - } - p++; + if (subtype == WIFI_BEACON) { + bssid->Reserved[0] = BSS_TYPE_BCN; + ie_offset = _BEACON_IE_OFFSET_; + } else { + /* FIXME : more type */ + if (subtype == WIFI_PROBERSP) { + ie_offset = _PROBERSP_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_RSP; + } else if (subtype == WIFI_PROBEREQ) { + ie_offset = _PROBEREQ_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_REQ; + } else { + bssid->Reserved[0] = BSS_TYPE_UNDEF; + ie_offset = _FIXED_IE_LENGTH_; } } - -ext_rate: - ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len); - if (ie) { - /* get valid extended supported rates */ - for (i = 0; i < 12; i++) { - p = ie + 2; - for (j = 0; j < ie_len; j++) { - if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ - support_rate_tbl[i].existence = _TRUE; - if ((*p) & BIT(7)) - support_rate_tbl[i].basic = _TRUE; - } - p++; - } - } + + _rtw_spinlock_bh(&padapter->mlmepriv.scanned_queue.lock); + scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac); + if (!scanned) { + _rtw_spinunlock_bh(&padapter->mlmepriv.scanned_queue.lock); + return; } - for (i = 0; i < 12; i++){ - if (support_rate_tbl[i].existence){ - if (support_rate_tbl[i].basic) - rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK; - else - rate_set[*rate_num] = support_rate_tbl[i].rate; - *rate_num += 1; + snetwork = &(scanned->network); + /* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID */ + if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) { + p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset); + if (!p) { + _rtw_spinunlock_bh(&padapter->mlmepriv.scanned_queue.lock); + return; } - } - - if (*rate_num == 0) - return _FAIL; - - if (0) { - int i; + next_ie = p + 2 + ssid_len_ori; + remain_len = snetwork->IELength - (next_ie - snetwork->IEs); + scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength; + _rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); - for (i = 0; i < *rate_num; i++) - RTW_INFO("rate:0x%02x\n", *(rate_set + i)); + //update pnetwork->ssid, pnetwork->ssidlen + _rtw_memcpy(backupIE, next_ie, remain_len); + *(p+1) = bssid->Ssid.SsidLength; + _rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); + _rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len); + snetwork->IELength += bssid->Ssid.SsidLength; } - - return _SUCCESS; + _rtw_spinunlock_bh(&padapter->mlmepriv.scanned_queue.lock); } -void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) +#ifdef DBG_RX_BCN +void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len) { - struct sta_info *psta; - u16 tid, start_seq, param; - struct sta_priv *pstapriv = &padapter->stapriv; - struct ADDBA_request *preq = (struct ADDBA_request *)paddba_req; - u8 size, accept = _FALSE; - - psta = rtw_get_stainfo(pstapriv, addr); - if (!psta) - goto exit; - - start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; - - param = le16_to_cpu(preq->BA_para_set); - tid = (param >> 2) & 0x0f; - + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info); + u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4; + u64 tsf, tsf_offset; + u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit; - accept = rtw_rx_ampdu_is_accept(padapter); - if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) - size = padapter->fix_rx_ampdu_size; - else { - size = rtw_rx_ampdu_size(padapter); - size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta)); - } + update_TSF(pmlmeext, pframe, packet_len); + tsf = pmlmeext->TSFValue; + tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)); - if (accept == _TRUE) - rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq); - else - rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */ + /*get TIM IE*/ + /*DTIM Count*/ + dtim_cnt = pmlmeext->tim[0]; + /*DTIM Period*/ + dtim_period = pmlmeext->tim[1]; + /*Bitmap*/ + tim_bmap = pmlmeext->tim[2]; + /*Partial VBitmap AID 0 ~ 7*/ + tim_pvbit = pmlmeext->tim[3]; -exit: - return; + RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n", + sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit); } +#endif -void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame) +/* + * rtw_get_bcn_keys: get beacon keys from recv frame + * + * TODO: + * WLAN_EID_COUNTRY + * WLAN_EID_ERP_INFO + * WLAN_EID_CHANNEL_SWITCH + * WLAN_EID_PWR_CONSTRAINT + */ +int _rtw_get_bcn_keys(u8 *cap_info, u32 buf_len, u8 def_ch, _adapter *adapter + , struct beacon_keys *recv_beacon) { - struct sta_priv *pstapriv = &padapter->stapriv; - u8 *pframe = precv_frame->u.hdr.rx_data; - struct sta_info *psta = NULL; - struct recv_reorder_ctrl *preorder_ctrl = NULL; - u8 tid = 0; - u16 start_seq=0; + int left; + u16 capability; + unsigned char *pos; + struct rtw_ieee802_11_elems elems; - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); - if (psta == NULL) - goto exit; + _rtw_memset(recv_beacon, 0, sizeof(*recv_beacon)); - tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12); - preorder_ctrl = &psta->recvreorder_ctrl[tid]; - start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4); - preorder_ctrl->indicate_seq = start_seq; + /* checking capabilities */ + capability = le16_to_cpu(*(unsigned short *)(cap_info)); - /* for Debug use */ - if (0) - RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter), tid, start_seq); + /* checking IEs */ + left = buf_len - 2; + pos = cap_info + 2; + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) + return _FALSE; -exit: - return; -} + if (elems.ht_capabilities) { + if (elems.ht_capabilities_len != 26) + return _FALSE; + } -void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) -{ - u8 *pIE; - u32 *pbuf; + if (elems.ht_operation) { + if (elems.ht_operation_len != 22) + return _FALSE; + } - pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - pbuf = (u32 *)pIE; + if (elems.vht_capabilities) { + if (elems.vht_capabilities_len != 12) + return _FALSE; + } - pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1)); + if (elems.vht_operation) { + if (elems.vht_operation_len != 5) + return _FALSE; + } - pmlmeext->TSFValue = pmlmeext->TSFValue << 32; + if (rtw_ies_get_supported_rate(pos, left, recv_beacon->rate_set, &recv_beacon->rate_num) == _FAIL) + return _FALSE; - pmlmeext->TSFValue |= le32_to_cpu(*pbuf); -} + if (cckratesonly_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE) + recv_beacon->proto_cap |= PROTO_CAP_11B; + else if (cckrates_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE) + recv_beacon->proto_cap |= PROTO_CAP_11B | PROTO_CAP_11G; + else + recv_beacon->proto_cap |= PROTO_CAP_11G; -void correct_TSF(_adapter *padapter, u8 mlme_state) -{ - u8 m_state = mlme_state; + if (elems.ht_capabilities && elems.ht_operation) + recv_beacon->proto_cap |= PROTO_CAP_11N; - rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state); -} + if (elems.vht_capabilities && elems.vht_operation) + recv_beacon->proto_cap |= PROTO_CAP_11AC; -#ifdef CONFIG_BCN_RECV_TIME -/* calculate beacon receiving time - 1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us] - 2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us] -*/ -inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate) -{ - u16 rx_bcn_time = 0;/*us*/ + if (elems.he_capabilities && elems.he_operation) + recv_beacon->proto_cap |= PROTO_CAP_11AX; - if (data_rate == DESC_RATE1M) - rx_bcn_time = 192 + bcn_len * 8 + 10; - else if(data_rate == DESC_RATE6M) - rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10; -/* - else - RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate); -*/ - return rx_bcn_time; -} -void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate) -{ - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + /* check bw and channel offset */ + rtw_ies_get_chbw(pos, left, &recv_beacon->ch, &recv_beacon->bw, &recv_beacon->offset, 1, 1); + if (!recv_beacon->ch) + recv_beacon->ch = def_ch; - pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate); -} -#endif + /* checking SSID */ + if (elems.ssid) { + if (elems.ssid_len > sizeof(recv_beacon->ssid)) + return _FALSE; -void beacon_timing_control(_adapter *padapter) -{ - rtw_hal_bcn_related_reg_setting(padapter); -} + _rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len); + recv_beacon->ssid_len = elems.ssid_len; + } + + /* checking RSN first */ + if (elems.rsn_ie && elems.rsn_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_RSN; + rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + NULL, &recv_beacon->akm, NULL, NULL); + } + /* checking WPA secon */ + else if (elems.wpa_ie && elems.wpa_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA; + rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + &recv_beacon->akm); + } else if (capability & BIT(4)) + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP; -inline bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct macid_ctl_t *macid_ctl = &dvobj->macid_ctl; + if (adapter) { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - if (macid_ctl->macid_cap & cap) - return _TRUE; - return _FALSE; -} + if (elems.tim && elems.tim_len) { + #ifdef DBG_RX_BCN + _rtw_memcpy(pmlmeext->tim, elems.tim, 4); + #endif + pmlmeext->dtim = elems.tim[1]; + } -void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num) -{ - RTW_PRINT_SEL(sel, "0x%08x\n", map->m0); -#if (MACID_NUM_SW_LIMIT > 32) - if (max_num && max_num > 32) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m1); -#endif -#if (MACID_NUM_SW_LIMIT > 64) - if (max_num && max_num > 64) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m2); -#endif -#if (MACID_NUM_SW_LIMIT > 96) - if (max_num && max_num > 96) - RTW_PRINT_SEL(sel, "0x%08x\n", map->m3); -#endif -} + /* checking RTW TBTX */ + #ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (elems.tbtx_cap && elems.tbtx_cap_len) { + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id) -{ - if (id < 32) - return map->m0 & BIT(id); -#if (MACID_NUM_SW_LIMIT > 32) - else if (id < 64) - return map->m1 & BIT(id - 32); -#endif -#if (MACID_NUM_SW_LIMIT > 64) - else if (id < 96) - return map->m2 & BIT(id - 64); -#endif -#if (MACID_NUM_SW_LIMIT > 96) - else if (id < 128) - return map->m3 & BIT(id - 96); -#endif - else - rtw_warn_on(1); + if (rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) + RTW_DBG("AP support TBTX\n"); + } + #endif + } - return 0; + return _TRUE; } -inline void rtw_macid_map_set(struct macid_bmp *map, u8 id) +int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys) { - if (id < 32) - map->m0 |= BIT(id); -#if (MACID_NUM_SW_LIMIT > 32) - else if (id < 64) - map->m1 |= BIT(id - 32); -#endif -#if (MACID_NUM_SW_LIMIT > 64) - else if (id < 96) - map->m2 |= BIT(id - 64); -#endif -#if (MACID_NUM_SW_LIMIT > 96) - else if (id < 128) - map->m3 |= BIT(id - 96); -#endif - else - rtw_warn_on(1); -} + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; -inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id) -{ - if (id < 32) - map->m0 &= ~BIT(id); -#if (MACID_NUM_SW_LIMIT > 32) - else if (id < 64) - map->m1 &= ~BIT(id - 32); -#endif -#if (MACID_NUM_SW_LIMIT > 64) - else if (id < 96) - map->m2 &= ~BIT(id - 64); -#endif -#if (MACID_NUM_SW_LIMIT > 96) - else if (id < 128) - map->m3 &= ~BIT(id - 96); -#endif - else - rtw_warn_on(1); + return _rtw_get_bcn_keys( + whdr + WLAN_HDR_A3_LEN + 10 + , flen - WLAN_HDR_A3_LEN - 10 + , pmlmeext->chandef.chan, adapter + , bcn_keys); } -inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id) +int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys) { - return rtw_macid_is_set(&macid_ctl->used, id); + return _rtw_get_bcn_keys( + bss->IEs + 10 + , bss->IELength - 10 + , bss->Configuration.DSConfig, NULL + , bcn_keys); } -inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id) +int rtw_update_bcn_keys_of_network(struct wlan_network *network) { - return rtw_macid_is_set(&macid_ctl->bmc, id); + network->bcn_keys_valid = rtw_get_bcn_keys_from_bss(&network->network, &network->bcn_keys); + return network->bcn_keys_valid; } -inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id) +void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon) { - int i; - u8 iface_bmp = 0; + u8 ssid[IW_ESSID_MAX_SIZE + 1]; - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { - if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) - iface_bmp |= BIT(i); - } - return iface_bmp; + _rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len); + ssid[recv_beacon->ssid_len] = '\0'; + + RTW_PRINT_SEL(sel, "ssid = %s (len = %u)\n", ssid, recv_beacon->ssid_len); + RTW_PRINT_SEL(sel, "ch = %u,%u,%u\n" + , recv_beacon->ch, recv_beacon->bw, recv_beacon->offset); + RTW_PRINT_SEL(sel, "proto_cap = 0x%02x\n", recv_beacon->proto_cap); + RTW_MAP_DUMP_SEL(sel, "rate_set = " + , recv_beacon->rate_set, recv_beacon->rate_num); + RTW_PRINT_SEL(sel, "sec = %d, group = 0x%x, pair = 0x%x, akm = 0x%08x\n" + , recv_beacon->encryp_protocol, recv_beacon->group_cipher + , recv_beacon->pairwise_cipher, recv_beacon->akm); } -inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id) +bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv) { -#if CONFIG_IFACE_NUMBER >= 2 - int i; - u8 iface_bmp = 0; +#define BCNKEY_VERIFY_PROTO_CAP 0 +#define BCNKEY_VERIFY_WHOLE_RATE_SET 0 - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { - if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { - if (iface_bmp) - return 1; - iface_bmp |= BIT(i); - } - } -#endif - return 0; -} + struct beacon_keys tmp; + bool ret = _FALSE; -inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter) -{ - int i; - u8 iface_bmp = 0; + if (!rtw_is_chbw_grouped(cur->ch, cur->bw, cur->offset + , recv->ch, recv->bw, recv->offset)) + goto exit; - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { - if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { - if (iface_bmp || i != adapter->iface_id) - return 0; - iface_bmp |= BIT(i); - } + _rtw_memcpy(&tmp, cur, sizeof(tmp)); + + /* check fields excluding below */ + tmp.ch = recv->ch; + tmp.bw = recv->bw; + tmp.offset = recv->offset; + if (!BCNKEY_VERIFY_PROTO_CAP) + tmp.proto_cap = recv->proto_cap; + if (!BCNKEY_VERIFY_WHOLE_RATE_SET) { + tmp.rate_num = recv->rate_num; + _rtw_memcpy(tmp.rate_set, recv->rate_set, 12); } - return iface_bmp ? 1 : 0; -} + if (_rtw_memcmp(&tmp, recv, sizeof(*recv)) == _FALSE) + goto exit; -inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) -{ - int i; + ret = _TRUE; - for (i = 0; i < 2; i++) { - if (rtw_macid_is_set(&macid_ctl->ch_g[i], id)) - return i; - } - return -1; +exit: + return ret; } -/*Record bc's mac-id and sec-cam-id*/ -inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - macid_ctl->iface_bmc[padapter->iface_id] = mac_id; -} -inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) +int rtw_check_bcn_info(_adapter *adapter, u8 *pframe, u32 packet_len) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 *pbssid = GetAddr3Ptr(pframe); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct wlan_network *cur_network = &(adapter->mlmepriv.cur_network); + struct beacon_keys *cur_beacon = &pmlmepriv->cur_beacon_keys; + struct beacon_keys recv_beacon; + int ret = 0; + u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(adapter); + u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(adapter); + struct dvobj_priv *d = adapter_to_dvobj(adapter); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); - return macid_ctl->iface_bmc[padapter->iface_id]; -} -#if defined(DBG_CONFIG_ERROR_RESET) -void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); - int cam_id = -1; + if (is_client_associated_to_ap(adapter) == _FALSE) + goto exit_success; - cam_id = rtw_iface_bcmc_id_get(adapter); - if (cam_id != INVALID_SEC_MAC_CAM_ID) - rtw_sec_cam_map_set(&cam_ctl->used, cam_id); -} -#endif -void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) -{ - int i; - _irqL irqL; - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct macid_bmp *used_map = &macid_ctl->used; - /* static u8 last_id = 0; for testing */ - u8 last_id = 0; - u8 is_bc_sta = _FALSE; - - if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) { - psta->cmn.mac_id = macid_ctl->num; - return; - } + if (rtw_get_bcn_keys(adapter, pframe, packet_len, &recv_beacon) == _FALSE) + goto exit_success; /* parsing failed => broken IE */ - if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { - is_bc_sta = _TRUE; - rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ +#ifdef DBG_RX_BCN + rtw_debug_rx_bcn(adapter, pframe, packet_len); +#endif + /* hidden ssid, replace with current beacon ssid directly */ + if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) { + _rtw_memcpy(recv_beacon.ssid, cur_beacon->ssid, cur_beacon->ssid_len); + recv_beacon.ssid_len = cur_beacon->ssid_len; } - if (is_bc_sta - #ifndef SEC_DEFAULT_KEY_SEARCH - && (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter)) +#if CONFIG_DFS + if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) { + u8 u_ch, u_offset, u_bw; + u8 bcn_ch, bcn_bw, bcn_offset; + struct sta_info *psta = NULL; + struct rtw_chan_def mr_chdef = {0}; + struct rtw_chan_def new_chdef = {0}; + + /* get union ch/bw/offset from chan_ctx */ + rtw_phl_mr_get_chandef(d->phl, adapter->phl_role, &mr_chdef); + u_ch = mr_chdef.chan; + u_offset = (u8)mr_chdef.offset; + u_bw = (u8)mr_chdef.bw; + + #ifdef DBG_CSA + RTW_INFO("CSA : before update beacon, u_ch=%u, recv_beacon.ch=%u\n", u_ch, recv_beacon.ch); #endif - ) { - /* STA mode have no BMC data TX, shared with this macid */ - /* When non-concurrent, only one BMC data TX is used, shared with this macid */ - /* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */ - i = RTW_DEFAULT_MGMT_MACID; - goto assigned; - } - _enter_critical_bh(&macid_ctl->lock, &irqL); + if (pmlmepriv->bcn_cnts_after_csa < 5) { + if (u_ch == recv_beacon.ch) + pmlmepriv->bcn_cnts_after_csa += 1; + goto exit_success; + } else + pmlmepriv->bcn_cnts_after_csa = 0; - for (i = last_id; i < macid_ctl->num; i++) { -#ifdef CONFIG_MCC_MODE - /* macid 0/1 reserve for mcc for mgnt queue macid */ - if (MCC_EN(padapter)) { - if (i == MCC_ROLE_STA_GC_MGMT_QUEUE_MACID) - continue; - if (i == MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID) - continue; - } -#endif /* CONFIG_MCC_MODE */ + _rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon)); + clr_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON); - #ifndef SEC_DEFAULT_KEY_SEARCH - /* for BMC data TX with force camid */ - if (is_bc_sta && rtw_sec_camid_is_used(dvobj_to_sec_camctl(dvobj), i)) - continue; + bcn_ch = recv_beacon.ch; + bcn_bw = recv_beacon.bw; + bcn_offset = recv_beacon.offset; + + #ifdef DBG_CSA + RTW_INFO("CSA : after update beacon, recv_beacon.ch=%u, recv_beacon.bw=%u, recv_beacon.offset=%u\n", \ + bcn_ch, bcn_bw, bcn_offset); + rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon); #endif - if (!rtw_macid_is_used(macid_ctl, i)) - break; - } + _cancel_timer_nowait(&pmlmeext->csa_timer); - if (i < macid_ctl->num) { + /* beacon bw/offset is different from CSA IE */ + if ((bcn_bw > u_bw) || + (bcn_offset != u_offset && + u_offset != CHAN_OFFSET_NO_EXT && + bcn_offset != CHAN_OFFSET_NO_EXT)) { - rtw_macid_map_set(used_map, i); + pmlmeext->chandef.bw = bcn_bw; + pmlmeext->chandef.offset = bcn_offset; + /* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */ + pmlmepriv->cur_network.network.Configuration.DSConfig = bcn_ch; - #ifndef SEC_DEFAULT_KEY_SEARCH - /* for BMC data TX with force camid */ - if (is_bc_sta) { - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + /* update wifi role chandef */ + rtw_hw_update_chan_def(adapter); - rtw_macid_map_set(&macid_ctl->bmc, i); - rtw_iface_bcmc_id_set(padapter, i); - rtw_sec_cam_map_set(&cam_ctl->used, i); - if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC)) - rtw_sec_cam_map_set(&cam_ctl->used, i + 1); - } - #endif + /* update chanctx */ + if (rtw_phl_mr_upt_chandef(d->phl, adapter->phl_role) == RTW_PHL_STATUS_FAILURE) + RTW_ERR("CSA : update chanctx fail\n"); + + rtw_phl_mr_get_chandef(d->phl, adapter->phl_role, &new_chdef); + rtw_mi_update_union_chan_inf(adapter, new_chdef.chan, (u8)new_chdef.offset, (u8)new_chdef.bw); - rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i); - macid_ctl->sta[i] = psta; + #ifdef CONFIG_AP_MODE + if (ifbmp_m) { + rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(d), 0 + , ifbmp_m, 0, new_chdef.chan, REQ_BW_ORI, REQ_OFFSET_NONE); + } else + #endif + { + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_OPCH_SWITCH, ifbmp_s); + #endif + rtw_set_chbw_cmd(adapter, new_chdef.chan, (u8)new_chdef.bw, (u8)new_chdef.offset, 0); + } + RTW_INFO("CSA : after update bw/offset, new_bw=%d, new_offset=%d \n", \ + (u8)new_chdef.bw, (u8)new_chdef.offset); + } else { + RTW_INFO("CSA : u_ch=%d, u_bw=%d, u_offset=%d, recv_beacon.ch=%d, recv_beacon.bw=%d, recv_beacon.offset=%d\n" + , u_ch, u_bw, u_offset, bcn_ch, bcn_bw, bcn_offset); + } - /* TODO ch_g? */ + /* update RA mask */ + psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (psta) { + psta->phl_sta->chandef.bw = pmlmeext->chandef.bw; + rtw_phl_cmd_change_stainfo(GET_PHL_INFO(d), + psta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_NO_WAIT, + 0); + } - last_id++; - last_id %= macid_ctl->num; + RTW_INFO("CSA : update beacon done, WIFI_CSA_UPDATE_BEACON is clear\n"); } +#endif /* CONFIG_DFS */ - _exit_critical_bh(&macid_ctl->lock, &irqL); + if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT" new beacon occur!!\n", FUNC_ADPT_ARG(adapter)); + RTW_INFO(FUNC_ADPT_FMT" cur beacon key:\n", FUNC_ADPT_ARG(adapter)); + rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon); + RTW_INFO(FUNC_ADPT_FMT" new beacon key:\n", FUNC_ADPT_ARG(adapter)); + rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon); - if (i >= macid_ctl->num) { - psta->cmn.mac_id = macid_ctl->num; - RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr)); - rtw_warn_on(1); - goto exit; - } else - goto assigned; + if (rtw_bcn_key_compare(cur_beacon, &recv_beacon) == _FALSE) + goto exit; + + _rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon)); + } -assigned: - psta->cmn.mac_id = i; - RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); +exit_success: + ret = 1; exit: - return; + return ret; } -void rtw_release_macid(_adapter *padapter, struct sta_info *psta) +void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) { - _irqL irqL; - u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 ifbmp; - int i; + unsigned int i; + unsigned int len; + PNDIS_802_11_VARIABLE_IEs pIE; - if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) - goto exit; +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */ +#endif /* CONFIG_TDLS */ - if (psta->cmn.mac_id >= macid_ctl->num) { - RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 - , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); - rtw_warn_on(1); - goto exit; + len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); + + for (i = 0; i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + /* to update WMM paramter set while receiving beacon */ + if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN) /* WMM */ + (WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0; + + break; + + case _HT_EXTRA_INFO_IE_: /* HT info */ + /* HT_info_handler(padapter, pIE); */ + bwmode_update_check(padapter, pIE); + break; +#ifdef CONFIG_80211AC_VHT + case EID_OpModeNotification: + rtw_process_vht_op_mode_notify(padapter, pIE->data, psta); + break; +#endif /* CONFIG_80211AC_VHT */ + case _ERPINFO_IE_: + ERP_IE_handler(padapter, pIE); + VCS_update(padapter, psta); + break; + +#ifdef CONFIG_TDLS + case WLAN_EID_EXT_CAP: + if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE) + ptdlsinfo->ap_prohibited = _TRUE; + if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE) + ptdlsinfo->ch_switch_prohibited = _TRUE; + break; +#endif /* CONFIG_TDLS */ +#ifdef CONFIG_80211AX_HE + case WLAN_EID_EXTENSION: + if (pIE->data[0] == WLAN_EID_EXTENSION_HE_OPERATION) + HE_operation_handler(padapter, pIE); + else if (pIE->data[0] == WLAN_EID_EXTENSION_HE_MU_EDCA) + HE_mu_edca_handler(padapter, pIE, _FALSE); + break; +#endif + default: + break; + } + + i += (pIE->Length + 2); } +} - if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID) - goto msg; +#if CONFIG_DFS +void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len) +{ +#ifdef CONFIG_ECSA_PHL + struct core_ecsa_info *ecsa_info = &(padapter->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); +#endif + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + unsigned int i, j, countdown; + PNDIS_802_11_VARIABLE_IEs pIE, sub_pie; + u8 ch = 0, csa_ch_offset = 0, csa_ch_width = 0, csa_ch_freq_seg0 = 0, csa_ch_freq_seg1 = 0; + u8 csa_switch_cnt = 0, csa_mode = 0; + u8 is_csa_running; + +#ifdef DBG_CSA + u8 *p; + u32 ie_len = 0; + p = rtw_get_ie(ies, WLAN_EID_CHANNEL_SWITCH, &ie_len, ies_len); + if (p && ie_len > 0) + RTW_INFO("CSA : %s, CH = %u, count = %u\n",__func__, *(p+2+1), *(p+2+2)); +#endif + +#ifdef CONFIG_ECSA_PHL + is_csa_running = rtw_mr_is_ecsa_running(padapter); +#else + is_csa_running = (rfctl->csa_chandef.chan > 0) ? _TRUE : _FALSE; +#endif + + /* compare with scheduling CSA to block incoming CSA IE */ + if (is_csa_running || check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) + return; - _enter_critical_bh(&macid_ctl->lock, &irqL); + for (i = 0; i + 1 < ies_len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i); - if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) { - RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 - , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); - _exit_critical_bh(&macid_ctl->lock, &irqL); - rtw_warn_on(1); - goto exit; - } + switch (pIE->ElementID) { + case WLAN_EID_CHANNEL_SWITCH: + csa_mode = *(pIE->data); + ch = *(pIE->data + 1); + csa_switch_cnt = *(pIE->data + 2); - ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id); - if (!(ifbmp & BIT(padapter->iface_id))) { - RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 - , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); - _exit_critical_bh(&macid_ctl->lock, &irqL); - rtw_warn_on(1); - goto exit; - } + RTW_INFO("CSA : mode = %u, ch = %u, switch count = %u\n", + csa_mode, ch, csa_switch_cnt); + break; + case WLAN_EID_SECONDARY_CHANNEL_OFFSET: + csa_ch_offset = *(pIE->data); + break; + case WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH: + csa_ch_width = *(pIE->data); + csa_ch_freq_seg0 = *(pIE->data+1); + csa_ch_freq_seg1 = *(pIE->data+2); - if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); - u8 id = rtw_iface_bcmc_id_get(padapter); + RTW_INFO("CSA : bw:%02x center_freq_0:%u center_freq_1:%u, ch=%u\n" + , csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); + break; + case WLAN_EID_CHANNEL_SWITCH_WRAPPER: + for (j=0; j + 1 < pIE->Length;) { + sub_pie = (PNDIS_802_11_VARIABLE_IEs)(ies + i + j + 2); + if (sub_pie->ElementID == WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH) { + csa_ch_width = *(sub_pie->data); + csa_ch_freq_seg0 = *(sub_pie->data+1); + csa_ch_freq_seg1 = *(sub_pie->data+2); - if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) { - rtw_sec_cam_map_clr(&cam_ctl->used, id); - if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC)) - rtw_sec_cam_map_clr(&cam_ctl->used, id + 1); + RTW_INFO("CSA : sub_IE:%02x IE_length:%02x bw:%02x center_freq_0:%u center_freq_1:%u, ch=%u\n" + , sub_pie->ElementID, sub_pie->Length, csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); + } + j += (sub_pie->Length + 2); + } + break; + default: + break; } - rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); + i += (pIE->Length + 2); } - rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id); - - ifbmp &= ~BIT(padapter->iface_id); - if (!ifbmp) { /* only used by self */ - rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id); - rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id); - for (i = 0; i < 2; i++) - rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id); - macid_ctl->sta[psta->cmn.mac_id] = NULL; + /* Doesn't support switch bandwidth/offset in the same channel for now */ + if (ch == rtw_mi_get_union_chan(padapter)) { + RTW_ERR("%s : receive the same channel from CSA IE, so ignore it\n", __func__); + return; } - _exit_critical_bh(&macid_ctl->lock, &irqL); + if (ch != 0) { + #ifdef CONFIG_ECSA_PHL + ecsa_param->ecsa_type = ECSA_TYPE_STA; + ecsa_param->mode = csa_mode; + ecsa_param->count = csa_switch_cnt; + /* ecsa_param.op_class = rfctl->op_class; */ /* TODO : ECSA */ + ecsa_param->new_chan_def.band = rtw_phl_get_band_type(ch); + ecsa_param->new_chan_def.chan = ch; + /* The channel width defined in 802.11 spec */ + ecsa_info->channel_width = csa_ch_width; + ecsa_param->new_chan_def.offset = csa_ch_offset; + ecsa_param->new_chan_def.center_freq1 = csa_ch_freq_seg0; + ecsa_param->new_chan_def.center_freq2 = csa_ch_freq_seg1; + ecsa_param->flag = 0; + ecsa_param->delay_start_ms = 0; + + SET_ECSA_STATE(padapter, ECSA_ST_SW_START); + rtw_trigger_phl_ecsa_start(padapter); + #else + rfctl->csa_mode = csa_mode; + rfctl->csa_switch_cnt = csa_switch_cnt; + rfctl->csa_ch_width = csa_ch_width; -msg: - RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 - , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id - ); + rfctl->csa_chandef.band = rtw_phl_get_band_type(ch); + rfctl->csa_chandef.chan = ch; + rfctl->csa_chandef.offset = csa_ch_offset; + rfctl->csa_chandef.center_freq1= csa_ch_freq_seg0; + rfctl->csa_chandef.center_freq2 = csa_ch_freq_seg1; -exit: - psta->cmn.mac_id = macid_ctl->num; + countdown = pmlmeinfo->network.Configuration.BeaconPeriod * (csa_switch_cnt+1); /* ms */ + RTW_INFO("csa: set countdown timer to %d ms\n", countdown); + _set_timer(&pmlmeext->csa_timer, countdown); + #endif /* CONFIG_ECSA_PHL */ + } } +#endif /* CONFIG_DFS */ -/* For 8188E RA */ -u8 rtw_search_max_mac_id(_adapter *padapter) +#ifdef CONFIG_80211D +bool rtw_iface_accept_country_ie(_adapter *adapter) { - u8 max_mac_id = 0; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - int i; - _irqL irqL; - - /* TODO: Only search for connected macid? */ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - _enter_critical_bh(&macid_ctl->lock, &irqL); - for (i = (macid_ctl->num - 1); i > 0 ; i--) { - if (rtw_macid_is_used(macid_ctl, i)) - break; + if (!(BIT(adapter->iface_id) & rfctl->country_ie_slave_en_ifbmp)) + return 0; + if (!MLME_IS_STA(adapter)) + return 0; + if (!MLME_IS_GC(adapter)) { + if (!(rfctl->country_ie_slave_en_role & COUNTRY_IE_SLAVE_EN_ROLE_STA)) + return 0; + } else { + if (!(rfctl->country_ie_slave_en_role & COUNTRY_IE_SLAVE_EN_ROLE_GC)) + return 0; } - _exit_critical_bh(&macid_ctl->lock, &irqL); - max_mac_id = i; - - return max_mac_id; + return 1; } -inline u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr) +void process_country_ie(_adapter *adapter, u8 *ies, uint ies_len) { - u8 op_num_change_bmp = 0; - - if (id >= macid_ctl->num) { - rtw_warn_on(1); - goto exit; - } + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - if (GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id]) - && !GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr) + if (rfctl->regd_src == REGD_SRC_RTK_PRIV + && !rtw_rfctl_is_disable_sw_channel_plan(rfctl_to_dvobj(rfctl)) + && !rfctl->csa_chandef.chan /* don't process country ie when under CSA processing */ ) { - u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[id]); - - if (role < H2C_MSR_ROLE_MAX) { - macid_ctl->op_num[role]--; - op_num_change_bmp |= BIT(role); + struct mlme_priv *mlme = &adapter->mlmepriv; + const u8 *ie = NULL; + sint ie_len = 0; + + if (rtw_iface_accept_country_ie(adapter)) { + ie = rtw_get_ie(ies, WLAN_EID_COUNTRY, &ie_len, ies_len); + if (ie) { + if (ie_len < 6) { + ie = NULL; + ie_len = 0; + } else + ie_len += 2; + } } - } else if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id]) - && GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr) - ) { - u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&h2c_msr); - if (role < H2C_MSR_ROLE_MAX) { - macid_ctl->op_num[role]++; - op_num_change_bmp |= BIT(role); - } - } + if (!mlme->recv_country_ie && !ie) + return; + if (mlme->recv_country_ie_len == ie_len + && _rtw_memcmp(mlme->recv_country_ie, ie, ie_len) == _TRUE) + return; - macid_ctl->h2c_msr[id] = h2c_msr; - if (0) - RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id])); + if (!ie) { + rtw_buf_free(&mlme->recv_country_ie, &mlme->recv_country_ie_len); + rtw_apply_recv_country_ie_cmd(adapter, 0, 0, 0, NULL); + } else { + char ori_alpha2[2] = {0, 0}; -exit: - return op_num_change_bmp; -} + if (mlme->recv_country_ie) + _rtw_memcpy(ori_alpha2, mlme->recv_country_ie + 2, 2); -inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw) -{ - if (id >= macid_ctl->num) { - rtw_warn_on(1); - return; + rtw_buf_update(&mlme->recv_country_ie, &mlme->recv_country_ie_len, ie, ie_len); + /* for now only country code is used */ + if (_rtw_memcmp(ori_alpha2, mlme->recv_country_ie + 2, 2) == _TRUE) + return; + RTW_INFO(FUNC_ADPT_FMT" country_ie alpha2 changed\n", FUNC_ADPT_ARG(adapter)); + rtw_apply_recv_country_ie_cmd(adapter, 0 + , mlme->cur_beacon_keys.ch > 14 ? BAND_ON_5G : BAND_ON_24G + , mlme->cur_beacon_keys.ch, mlme->recv_country_ie); + } } - - macid_ctl->bw[id] = bw; - if (0) - RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id])); } +#endif /* CONFIG_80211D */ -inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en) +enum eap_type parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type) { - if (id >= macid_ctl->num) { - rtw_warn_on(1); - return; - } + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct ieee802_1x_hdr *hdr; + struct wpa_eapol_key *key; + u16 key_info, key_data_length; + char *trx_msg = trx_type ? "send" : "recv"; + enum eap_type eapol_type; - macid_ctl->vht_en[id] = en; - if (0) - RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]); -} + hdr = (struct ieee802_1x_hdr *) key_payload; -inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) -{ - if (id >= macid_ctl->num) { - rtw_warn_on(1); - return; + /* WPS - eapol start packet */ + if (hdr->type == 1 && hdr->length == 0) { + RTW_INFO("%s eapol start packet\n", trx_msg); + return EAPOL_START; } - macid_ctl->rate_bmp0[id] = bmp; - if (0) - RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]); -} - -inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) -{ - if (id >= macid_ctl->num) { - rtw_warn_on(1); - return; + if (hdr->type == 0) { /* WPS - eapol packet */ + RTW_INFO("%s eapol packet\n", trx_msg); + return EAPOL_PACKET; } - macid_ctl->rate_bmp1[id] = bmp; - if (0) - RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]); -} + key = (struct wpa_eapol_key *) (hdr + 1); + key_info = be16_to_cpu(*((u16 *)(key->key_info))); + key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length))); -#ifdef CONFIG_PROTSEL_MACSLEEP -inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info) -{ - macid_ctl->reg_sleep_ctrl = reg_ctrl; - macid_ctl->reg_sleep_info = reg_info; -} -inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info) -{ - macid_ctl->reg_drop_ctrl = reg_ctrl; - macid_ctl->reg_drop_info = reg_info; -} + if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */ + if (key_info & WPA_KEY_INFO_ACK) { + RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg); + eapol_type = EAPOL_WPA_GROUP_KEY_1_2; + } else { + RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg); + eapol_type = EAPOL_WPA_GROUP_KEY_2_2; -#else -inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3) -{ - macid_ctl->reg_sleep_m0 = m0; -#if (MACID_NUM_SW_LIMIT > 32) - macid_ctl->reg_sleep_m1 = m1; -#endif -#if (MACID_NUM_SW_LIMIT > 64) - macid_ctl->reg_sleep_m2 = m2; -#endif -#if (MACID_NUM_SW_LIMIT > 96) - macid_ctl->reg_sleep_m3 = m3; -#endif -} + /* WPA key-handshake has completed */ + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK) + psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); + } + } else if (key_info & WPA_KEY_INFO_MIC) { + if (key_data_length == 0) { + RTW_PRINT("%s eapol packet 4/4\n", trx_msg); + eapol_type = EAPOL_4_4; + } else if (key_info & WPA_KEY_INFO_ACK) { + RTW_PRINT("%s eapol packet 3/4\n", trx_msg); + eapol_type = EAPOL_3_4; + } else { + RTW_PRINT("%s eapol packet 2/4\n", trx_msg); + eapol_type = EAPOL_2_4; + } + } else { + RTW_PRINT("%s eapol packet 1/4\n", trx_msg); + eapol_type = EAPOL_1_4; + } -inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3) -{ - macid_ctl->reg_drop_m0 = m0; -#if (MACID_NUM_SW_LIMIT > 32) - macid_ctl->reg_drop_m1 = m1; -#endif -#if (MACID_NUM_SW_LIMIT > 64) - macid_ctl->reg_drop_m2 = m2; -#endif -#if (MACID_NUM_SW_LIMIT > 96) - macid_ctl->reg_drop_m3 = m3; -#endif + return eapol_type; } -#endif -inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) +unsigned int is_ap_in_tkip(_adapter *padapter) { - int i; - u8 id = RTW_DEFAULT_MGMT_MACID; + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - rtw_macid_map_set(&macid_ctl->used, id); - rtw_macid_map_set(&macid_ctl->bmc, id); - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) - rtw_macid_map_set(&macid_ctl->if_g[i], id); - macid_ctl->sta[id] = NULL; + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); - _rtw_spinlock_init(&macid_ctl->lock); -} + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) + return _TRUE; + break; -inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl) -{ - _rtw_spinlock_free(&macid_ctl->lock); -} + case _RSN_IE_2_: + if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) + return _TRUE; -inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id) -{ - if (id / 8 >= bmp_len) - return 0; + default: + break; + } - return bmp[id / 8] & BIT(id % 8); -} + i += (pIE->Length + 2); + } -inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id) -{ - if (id / 8 < bmp_len) - bmp[id / 8] |= BIT(id % 8); -} + return _FALSE; + } else + return _FALSE; -inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id) -{ - if (id / 8 < bmp_len) - bmp[id / 8] &= ~BIT(id % 8); } -inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len) +unsigned int should_forbid_n_rate(_adapter *padapter) { - int i; - - for (i = 0; i < bmp_len; i++) { - if (bmp[i]) - return 1; - } - - return 0; -} + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + WLAN_BSSID_EX *cur_network = &pmlmepriv->cur_network.network; -inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len) -{ - int i; + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i); - for (i = 0; i < bmp_len; i++) { - if (i == 0) { - if (bmp[i] & 0xFE) - return 1; - } else { - if (bmp[i]) - return 1; - } - } + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) && + ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) || + (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4)))) + return _FALSE; + break; - return 0; -} + case _RSN_IE_2_: + if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4)) || + (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4))) + return _FALSE; -#ifdef CONFIG_AP_MODE -/* Check the id be set or not in map , if yes , return a none zero value*/ -bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id) -{ - return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id); -} + default: + break; + } -/* Set the id into map array*/ -void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id) -{ - rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id); -} + i += (pIE->Length + 2); + } -/* Clear the id from map array*/ -void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id) -{ - rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id); -} + return _TRUE; + } else + return _FALSE; -/* Check have anyone bit be set , if yes return true*/ -bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map) -{ - return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len); } -/* Check have anyone bit be set exclude bit0 , if yes return true*/ -bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map) -{ - return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len); -} -#endif /* CONFIG_AP_MODE */ -#if 0 -unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) +unsigned int is_ap_in_wep(_adapter *padapter) { - unsigned short ATIMWindow; - unsigned char *pframe; - struct tx_desc *ptxdesc; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - unsigned int rate_len, len = 0; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - _rtw_memset(beacon_frame, 0, 256); + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) + return _FALSE; + break; - pframe = beacon_frame + TXDESC_SIZE; + case _RSN_IE_2_: + return _FALSE; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + default: + break; + } - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + i += (pIE->Length + 2); + } - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + return _TRUE; + } else + return _FALSE; - set_frame_sub_type(pframe, WIFI_BEACON); +} - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - len = sizeof(struct rtw_ieee80211_hdr_3addr); +int wifirate2_ratetbl_inx(unsigned char rate); +int wifirate2_ratetbl_inx(unsigned char rate) +{ + int inx = 0; + rate = rate & 0x7f; - /* timestamp will be inserted by hardware */ - pframe += 8; - len += 8; + switch (rate) { + case 54*2: + inx = 11; + break; - /* beacon interval: 2 bytes */ - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + case 48*2: + inx = 10; + break; - pframe += 2; - len += 2; + case 36*2: + inx = 9; + break; - /* capability info: 2 bytes */ - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + case 24*2: + inx = 8; + break; - pframe += 2; - len += 2; + case 18*2: + inx = 7; + break; - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len); + case 12*2: + inx = 6; + break; - /* supported rates... */ - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &len); + case 9*2: + inx = 5; + break; - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len); + case 6*2: + inx = 4; + break; - /* IBSS Parameter Set... */ - /* ATIMWindow = cur->Configuration.ATIMWindow; */ - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len); + case 11*2: + inx = 3; + break; + case 11: + inx = 2; + break; - /* todo: ERP IE */ + case 2*2: + inx = 1; + break; - /* EXTERNDED SUPPORTED RATE */ - if (rate_len > 8) - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len); + case 1*2: + inx = 0; + break; - if ((len + TXDESC_SIZE) > 256) { - /* RTW_INFO("marc: beacon frame too large\n"); */ - return 0; } + return inx; +} - /* fill the tx descriptor */ - ptxdesc = (struct tx_desc *)beacon_frame; +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz) +{ + unsigned int i, num_of_rate; + unsigned int mask = 0; - /* offset 0 */ - ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff); - ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* default = 32 bytes for TX Desc */ + num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz; - /* offset 4 */ - ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00); + for (i = 0; i < num_of_rate; i++) { + if ((*(ptn + i)) & 0x80) + mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); + } + return mask; +} - /* offset 8 */ - ptxdesc->txdw2 |= cpu_to_le32(BMC); - ptxdesc->txdw2 |= cpu_to_le32(BK); +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) +{ + unsigned int i, num_of_rate; + unsigned int mask = 0; - /* offset 16 */ - ptxdesc->txdw4 = 0x80000000; + num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz; - /* offset 20 */ - ptxdesc->txdw5 = 0x00000000; /* 1M */ + for (i = 0; i < num_of_rate; i++) + mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); - return len + TXDESC_SIZE; + return mask; } -#endif -_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj) +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode) { - _adapter *port0_iface = NULL; - int i; - for (i = 0; i < dvobj->iface_nums; i++) { - if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) - break; - } + unsigned char bit_offset; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (i < 0 || i >= dvobj->iface_nums) - rtw_warn_on(1); - else - port0_iface = dvobj->padapters[i]; + if (!(pmlmeinfo->HT_enable)) + return _FAIL; + + bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5; - return port0_iface; + if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset)) + return _SUCCESS; + else + return _FAIL; } -_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj) +unsigned char get_highest_rate_idx(u64 mask) { - _adapter *adapter = NULL; int i; + unsigned char rate_idx = 0; - for (i = 0; i < dvobj->iface_nums; i++) { - if (dvobj->padapters[i]->registered == 0) + for (i = 63; i >= 0; i--) { + if ((mask >> i) & 0x01) { + rate_idx = i; break; + } } - if (i < dvobj->iface_nums) - adapter = dvobj->padapters[i]; - - return adapter; + return rate_idx; } - -_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr) +unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit) { - _adapter *adapter = NULL; int i; + unsigned char rate_idx = 0; - for (i = 0; i < dvobj->iface_nums; i++) { - if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE) + for (i = start_bit; i < 64; i++) { + if ((mask >> i) & 0x01) { + rate_idx = i; break; + } } - if (i < dvobj->iface_nums) - adapter = dvobj->padapters[i]; - - return adapter; + return rate_idx; } -#ifdef CONFIG_WOWLAN -bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, - int *pattern_len, char *bit_mask) +u8 get_highest_bw_cap(u8 bwmode) { - char *cp = NULL; - size_t len = 0; - int pos = 0, mask_pos = 0, res = 0; - - /* To get the pattern string after "=", when we use : - * iwpriv wlanX pattern=XX:XX:..:XX - */ - cp = strchr(input, '='); - if (cp) { - *cp = 0; - cp++; - input = cp; - } + u8 hbw = CHANNEL_WIDTH_20; - /* To take off the newline character '\n'(0x0a) at the end of pattern string, - * when we use echo xxxx > /proc/xxxx - */ - cp = strchr(input, '\n'); - if (cp) - *cp = 0; + if (bwmode & BW_CAP_80_80M) + hbw = CHANNEL_WIDTH_80_80; + else if (bwmode & BW_CAP_160M) + hbw = CHANNEL_WIDTH_160; + else if (bwmode & BW_CAP_80M) + hbw = CHANNEL_WIDTH_80; + else if (bwmode & BW_CAP_40M) + hbw = CHANNEL_WIDTH_40; + else if (bwmode & BW_CAP_20M) + hbw = CHANNEL_WIDTH_20; + else if (bwmode & BW_CAP_10M) + hbw = CHANNEL_WIDTH_10; + else if (bwmode & BW_CAP_5M) + hbw = CHANNEL_WIDTH_5; - while (input) { - cp = strsep((char **)(&input), ":"); - - if (bit_mask && (strcmp(cp, "-") == 0 || - strcmp(cp, "xx") == 0 || - strcmp(cp, "--") == 0)) { - /* skip this byte and leave mask bit unset */ - } else { - u8 hex; - - if (strlen(cp) != 2) { - RTW_ERR("%s:[ERROR] hex len != 2, input=[%s]\n", - __func__, cp); - goto error; - } - - if (hexstr2bin(cp, &hex, 1) < 0) { - RTW_ERR("%s:[ERROR] pattern is invalid, input=[%s]\n", - __func__, cp); - goto error; - } - - pattern[pos] = hex; - mask_pos = pos / 8; - if (bit_mask) - bit_mask[mask_pos] |= 1 << (pos % 8); - } + return hbw; +} - pos++; - } +/* Update RRSR and Rate for USERATE */ +void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode) +{ + NDIS_802_11_RATES_EX supported_rates; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - (*pattern_len) = pos; + _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX); - return _TRUE; -error: - return _FALSE; -} + /* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */ + if (pmlmeext->chandef.chan > 14) + wirelessmode &= ~(WLAN_MD_11B); -void rtw_wow_pattern_sw_reset(_adapter *adapter) -{ - int i; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); + if ((wirelessmode & WLAN_MD_11B) && (wirelessmode == WLAN_MD_11B)) + _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4); + else if (wirelessmode & WLAN_MD_11B) + _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7); + else + _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3); - if (pwrctrlpriv->default_patterns_en == _TRUE) - pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + if (wirelessmode & WLAN_MD_11B) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); else - pwrctrlpriv->wowlan_pattern_idx = 0; + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); - for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { - _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content)); - _rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask)); - pwrctrlpriv->patterns[i].len = 0; - } + rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates); } -u8 rtw_set_default_pattern(_adapter *adapter) +unsigned char check_assoc_AP(u8 *pframe, uint len) { - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - u8 index = 0; - u8 multicast_addr[3] = {0x01, 0x00, 0x5e}; - u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a}; - - u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03}; - u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f}; - u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03}; - - u8 ip_protocol[3] = {0x08, 0x00, 0x45}; - u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60}; + unsigned int i; + PNDIS_802_11_VARIABLE_IEs pIE; - u8 *target = NULL; + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); - if (pwrpriv->default_patterns_en == _FALSE) - return 0; + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) { + RTW_INFO("link to Artheros AP\n"); + return HT_IOT_PEER_ATHEROS; + } else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) { + RTW_INFO("link to Broadcom AP\n"); + return HT_IOT_PEER_BROADCOM; + } else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) { + RTW_INFO("link to Marvell AP\n"); + return HT_IOT_PEER_MARVELL; + } else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) { + RTW_INFO("link to Ralink AP\n"); + return HT_IOT_PEER_RALINK; + } else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) { + RTW_INFO("link to Cisco AP\n"); + return HT_IOT_PEER_CISCO; + } else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) { + u32 Vender = HT_IOT_PEER_REALTEK; - for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { - _rtw_memset(pwrpriv->patterns[index].content, 0, - sizeof(pwrpriv->patterns[index].content)); - _rtw_memset(pwrpriv->patterns[index].mask, 0, - sizeof(pwrpriv->patterns[index].mask)); - pwrpriv->patterns[index].len = 0; - } + if (pIE->Length >= 5) { + if (pIE->data[4] == 1) { + /* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */ + /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */ - /*TCP/ICMP unicast*/ - for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { - switch (index) { - case 0: - target = pwrpriv->patterns[index].content; - _rtw_memcpy(target, adapter_mac_addr(adapter), - ETH_ALEN); + if (pIE->data[5] & RT_HT_CAP_USE_92SE) { + /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */ + Vender = HT_IOT_PEER_REALTEK_92SE; + } + } - target += ETH_TYPE_OFFSET; - _rtw_memcpy(target, &ip_protocol, - sizeof(ip_protocol)); + if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP) + Vender = HT_IOT_PEER_REALTEK_SOFTAP; - /* TCP */ - target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); - _rtw_memset(target, 0x06, 1); + if (pIE->data[4] == 2) { + if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CBV) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_CBVAP; + RTW_INFO("link to Realtek JAGUAR_CBVAP\n"); + } + if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCV) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCVAP; + RTW_INFO("link to Realtek JAGUAR_CCVAP\n"); + } + } + } - target += (IP_OFFSET - PROTOCOL_OFFSET); + RTW_INFO("link to Realtek AP\n"); + return Vender; + } else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) { + RTW_INFO("link to Airgo Cap\n"); + return HT_IOT_PEER_AIRGO; + } else + break; - _rtw_memcpy(target, pmlmeinfo->ip_addr, - RTW_IP_ADDR_LEN); + default: + break; + } - _rtw_memcpy(pwrpriv->patterns[index].mask, - &unicast_mask, sizeof(unicast_mask)); + i += (pIE->Length + 2); + } - pwrpriv->patterns[index].len = - IP_OFFSET + RTW_IP_ADDR_LEN; - break; - case 1: - target = pwrpriv->patterns[index].content; - _rtw_memcpy(target, adapter_mac_addr(adapter), - ETH_ALEN); + RTW_INFO("link to new AP\n"); + return HT_IOT_PEER_UNKNOWN; +} - target += ETH_TYPE_OFFSET; - _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); +void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor) +{ + switch (assoc_AP_vendor) { + + case HT_IOT_PEER_UNKNOWN: + sprintf(vendor, "%s", "unknown"); + break; - /* ICMP */ - target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); - _rtw_memset(target, 0x01, 1); + case HT_IOT_PEER_REALTEK: + case HT_IOT_PEER_REALTEK_92SE: + case HT_IOT_PEER_REALTEK_SOFTAP: + case HT_IOT_PEER_REALTEK_JAGUAR_CBVAP: + case HT_IOT_PEER_REALTEK_JAGUAR_CCVAP: - target += (IP_OFFSET - PROTOCOL_OFFSET); - _rtw_memcpy(target, pmlmeinfo->ip_addr, - RTW_IP_ADDR_LEN); + sprintf(vendor, "%s", "Realtek"); + break; - _rtw_memcpy(pwrpriv->patterns[index].mask, - &unicast_mask, sizeof(unicast_mask)); - pwrpriv->patterns[index].len = + case HT_IOT_PEER_BROADCOM: + sprintf(vendor, "%s", "Broadcom"); + break; - IP_OFFSET + RTW_IP_ADDR_LEN; - break; -#ifdef CONFIG_IPV6 - case 2: - if (pwrpriv->wowlan_ns_offload_en == _TRUE) { - target = pwrpriv->patterns[index].content; - target += ETH_TYPE_OFFSET; - - _rtw_memcpy(target, &ipv6_protocol, - sizeof(ipv6_protocol)); - - /* ICMPv6 */ - target += (IPv6_PROTOCOL_OFFSET - - ETH_TYPE_OFFSET); - _rtw_memset(target, 0x3a, 1); - - target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET); - _rtw_memcpy(target, pmlmeinfo->ip6_addr, - RTW_IPv6_ADDR_LEN); - - _rtw_memcpy(pwrpriv->patterns[index].mask, - &icmpv6_mask, sizeof(icmpv6_mask)); - pwrpriv->patterns[index].len = - IPv6_OFFSET + RTW_IPv6_ADDR_LEN; - } - break; -#endif /*CONFIG_IPV6*/ - case 3: - target = pwrpriv->patterns[index].content; - _rtw_memcpy(target, &multicast_addr, - sizeof(multicast_addr)); + case HT_IOT_PEER_MARVELL: + sprintf(vendor, "%s", "Marvell"); + break; - target += ETH_TYPE_OFFSET; - _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + case HT_IOT_PEER_RALINK: + sprintf(vendor, "%s", "Ralink"); + break; - /* UDP */ - target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); - _rtw_memset(target, 0x11, 1); + case HT_IOT_PEER_CISCO: + sprintf(vendor, "%s", "Cisco"); + break; - target += (IP_OFFSET - PROTOCOL_OFFSET); - _rtw_memcpy(target, &multicast_ip, - sizeof(multicast_ip)); + case HT_IOT_PEER_AIRGO: + sprintf(vendor, "%s", "Airgo"); + break; - _rtw_memcpy(pwrpriv->patterns[index].mask, - &multicast_mask, sizeof(multicast_mask)); + case HT_IOT_PEER_ATHEROS: + sprintf(vendor, "%s", "Atheros"); + break; - pwrpriv->patterns[index].len = - IP_OFFSET + sizeof(multicast_ip); - break; - default: - break; - } + default: + sprintf(vendor, "%s", "unkown"); + break; } - return index; -} -void rtw_dump_priv_pattern(_adapter *adapter, u8 idx) +} +#ifdef CONFIG_RTS_FULL_BW +void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) { - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - char str_1[128]; - char *p_str; - u8 val8 = 0; - int i = 0, j = 0, len = 0, max_len = 0; - - RTW_INFO("=========[%d]========\n", idx); - - RTW_INFO(">>>priv_pattern_content:\n"); - p_str = str_1; - max_len = sizeof(str_1); - for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { - _rtw_memset(p_str, 0, max_len); - len = 0; - for (j = 0 ; j < 8 ; j++) { - val8 = pwrctl->patterns[idx].content[i * 8 + j]; - len += snprintf(p_str + len, max_len - len, - "%02x ", val8); - } - RTW_INFO("%s\n", p_str); - } + unsigned char REALTEK_OUI[] = {0x00,0xe0, 0x4c}; + u8 *p; + + p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, REALTEK_OUI, 3, NULL, NULL); + if (!p) + goto exit; + else { + if(*(p+1) > 6 ) { - RTW_INFO(">>>priv_pattern_mask:\n"); - for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { - _rtw_memset(p_str, 0, max_len); - len = 0; - for (j = 0 ; j < 8 ; j++) { - val8 = pwrctl->patterns[idx].mask[i * 8 + j]; - len += snprintf(p_str + len, max_len - len, - "%02x ", val8); + if(*(p+6) != 2) + goto exit; + + if(*(p+8) == RT_HT_CAP_USE_JAGUAR_CBV) + sta->vendor_8812 = TRUE; + else if (*(p+8) == RT_HT_CAP_USE_JAGUAR_CCV) + sta->vendor_8812 = TRUE; } - RTW_INFO("%s\n", p_str); } - - RTW_INFO(">>>priv_pattern_len:\n"); - RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len); +exit: + return; } +#endif/*CONFIG_RTS_FULL_BW*/ -void rtw_wow_pattern_sw_dump(_adapter *adapter) +#ifdef CONFIG_80211AC_VHT +void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap) { - int i = 0, total = 0; - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - total = pwrpriv->wowlan_pattern_idx; + unsigned int i; + PNDIS_802_11_VARIABLE_IEs pIE; - RTW_INFO("********[RTK priv-patterns]*********\n"); - for (i = 0 ; i < total; i++) - rtw_dump_priv_pattern(adapter, i); -} + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); -void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr) -{ - struct sta_info *psta; - struct security_priv *psecpriv = &padapter->securitypriv; + switch (pIE->ElementID) { - _rtw_memset(pcur_dot11txpn, 0, 8); - if (NULL == StaAddr) - return; - psta = rtw_get_stainfo(&padapter->stapriv, StaAddr); - RTW_INFO("%s(): StaAddr: %02x %02x %02x %02x %02x %02x\n", - __func__, StaAddr[0], StaAddr[1], StaAddr[2], - StaAddr[3], StaAddr[4], StaAddr[5]); - - if (psta) { - if ((psecpriv->dot11PrivacyAlgrthm == _AES_) || - (psecpriv->dot11PrivacyAlgrthm == _CCMP_256_)) - AES_IV(pcur_dot11txpn, psta->dot11txpn, 0); - else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) - TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0); - else if ((psecpriv->dot11PrivacyAlgrthm == _GCMP_) || - (psecpriv->dot11PrivacyAlgrthm == _GCMP_256_)) - GCMP_IV(pcur_dot11txpn, psta->dot11txpn, 0); - - RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n" - , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1], - pcur_dot11txpn[2], pcur_dot11txpn[3], pcur_dot11txpn[4], - pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]); + case EID_VHTCapability: + bf_cap->is_mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data); + bf_cap->su_sound_dim = GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data); + break; + default: + break; + } + i += (pIE->Length + 2); } } +#endif -#ifdef CONFIG_WAR_OFFLOAD -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) -void rtw_wow_war_mdns_dump_buf(struct seq_file *m, u8 *title, u8 *buf, u32 len) -{ - u32 i; - - RTW_PRINT_SEL(m, "\t%s (%d)\n\t\t", title, len); - for (i = 1; i <= len; i++) - { - RTW_PRINT_SEL(m, "%2.2x-", *(buf + i - 1)); - if( (i%16 == 0) && (len != i) ) RTW_PRINT_SEL(m, "\n\t\t"); - } - RTW_PRINT_SEL(m, "\n\n"); -} - -void rtw_wow_war_mdns_dump_txt(struct seq_file *m, u8 *title, u8 *buf, u32 len) +void update_capinfo(_adapter *adapter, u16 updateCap) { - u16 idx=1, offset=0; /* offset = the location of L in the Length.Value */ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + BOOLEAN ShortPreamble; - RTW_PRINT_SEL(m, "\t%s (%d)\n\t", title, len); - for (; offset < len; idx++) + /* Check preamble mode, 2005.01.06, by rcnjko. */ + /* Mark to update preamble value forever, 2008.03.18 by lanhsin */ + /* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */ { - int item_len = buf[offset]; - u8 item_buf[256]={0}; - - _rtw_memcpy(item_buf, (buf + offset + 1), item_len); - RTW_PRINT_SEL(m, "\t[%d] => %s (%d)\n\t", idx, item_buf, item_len); - _rtw_memset(item_buf, 0, sizeof(item_buf)); - offset += (1+item_len); - } - RTW_PRINT_SEL(m, "\n\n"); -} -bool rtw_wow_war_mdns_parser_pattern(u8 *input, char *target, - u32 *target_len, u32 type) -{ - char *cp = NULL, *end = NULL; - size_t len = 0; - int pos = 0, mask_pos = 0, res = 0; - u8 member[2] = {0}; - - /* reset */ - _rtw_memset(target, '\0', type); - (*target_len) = 0; - - cp = strchr(input, '='); - if (cp) { - *cp = 0; - cp++; - input = cp; + if (updateCap & cShortPreamble) { + /* Short Preamble */ + if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */ + ShortPreamble = _TRUE; + pmlmeinfo->preamble_mode = PREAMBLE_SHORT; + rtw_hal_set_hwreg(adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); + } + } else { + /* Long Preamble */ + if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */ + ShortPreamble = _FALSE; + pmlmeinfo->preamble_mode = PREAMBLE_LONG; + rtw_hal_set_hwreg(adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); + } + } } - while (1) { - cp = strchr(input, ':'); - - if (cp) { - len = strlen(input) - strlen(cp); - *cp = 0; - cp++; - } else - len = 2; - - { - u8 hex,idx=0, pos_in_unit_as_4bit = 0; - - strncpy(member, input, len); - res = sscanf(member, "%02hhx", &hex); - - target[pos] = hex; - - /* RTW_INFO("==> in; input-member = %s, hex = %x, target[%d] = %x\n", member, hex, target[pos], pos); */ - - for(idx = 0; idx<2;idx++) - { - pos_in_unit_as_4bit = pos*2 + (1-idx); - mask_pos = (pos_in_unit_as_4bit /8); - - if(!IsHexDigit(member[idx])) - { - RTW_ERR("%s:[ERROR] pattern is invalid!!(%c)\n",__func__, member[idx]); - goto error; - } - - /* RTW_INFO("==> in; pos = %d, pos_in_unit_as_4bit = %d, mask-pos = %d \n", pos, pos_in_unit_as_4bit, mask_pos); - RTW_INFO("==> in; hex(0x%02x), member(%c%c) \n", pattern[pos], member[1], member[0]); */ + if (updateCap & cIBSS) { + /* Filen: See 802.11-2007 p.91 */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } else { + /* Filen: See 802.11-2007 p.90 */ + if (pmlmeext->cur_wireless_mode & (WLAN_MD_11N | WLAN_MD_11A | WLAN_MD_11AC)) + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + else if (pmlmeext->cur_wireless_mode & (WLAN_MD_11G)) { + if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) { + /* Short Slot Time */ + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + } else { + /* Long Slot Time */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; } - /* RTW_INFO_DUMP("Pattern Mask: ",bit_mask, 6); */ + } else { + /* B Mode */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; } - - pos++; - if (!cp) - break; - input = cp; } - (*target_len) = pos; - - return _TRUE; -error: - return _FALSE; + rtw_hal_set_hwreg(adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime); } -static struct war_mdns_service_info default_sinfo[] = { -/* example of default setting */ - RTW_MDNS_SRV_INFO("_ipp", 4, "_tcp", 4, "local", 5, 0x02, 0x77, 7200, "KM1", 3, 0), - RTW_MDNS_SRV_INFO("_ipps", 5, "_tcp", 4, "local", 5, 0x02, 0x77, 7200, "KM2", 3, 0), - RTW_MDNS_SRV_INFO("_http", 5, "_tcp", 4, "local", 5, 0x00, 0x50, 7200, "KM3", 3, 2), - RTW_MDNS_SRV_INFO("_privet", 7, "_tcp", 4, "local", 5, 0x00, 0x50, 7200, "KM4", 3, 3), - RTW_MDNS_SRV_INFO("_https", 6, "_tcp", 4, "local", 5, 0x01, 0xbb, 7200, "KM5", 3, 2), - RTW_MDNS_SRV_INFO("_uscan", 6, "_tcp", 4, "local", 5, 0x1f, 0x91, 7200, "KM6", 3, 4), - RTW_MDNS_SRV_INFO("_printer", 8, "_tcp", 4, "local", 5, 0x23, 0x8c, 7200, "KM7", 3, 1), - RTW_MDNS_SRV_INFO("_pdl-datastream", 15, "_tcp", 4, "local", 5, 0x23, 0x8c, 7200, "KM8", 3, 1) - -}; - -void rtw_wow_war_mdns_parms_reset(_adapter *adapter, u8 is_set_default) +/* +* set adapter.mlmeextpriv.mlmext_info.HT_enable +* set adapter.mlmeextpriv.cur_wireless_mode +* set SIFS register +* set mgmt tx rate +*/ +void update_wireless_mode(_adapter *padapter) { - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - u8 i =0; - u16 offset=0; - u8 default_domain_name[] = "Generic"; - //u8 default_machine_name[] = { 0x0a, 0x5f, 0x75, 0x6e, 0x69, 0x76, 0x65, 0x72, 0x73, 0x61, 0x6c, 0x04, 0x5f, 0x73, 0x75, 0x62 }; - //u8 default_machine_name_len = 16; - u8 default_machine_name[] = { 0x0a, 0x5f, 0x75, 0x6e, 0x69, 0x76, 0x65, 0x72, 0x73, 0x61, 0x6c}; /* length : 10 name : _universal */ - u8 default_machine_name_len = 11; - - /* set default txt value*/ - char *default_txt_rsp_0_for_serive[2] = { "_ipp", "_ipps" }; - char *default_txt_rsp_0[25] = { - "txtvers=1", "qtotal=1", "usb_MFG=KONICA MINOLTA", "usb_MDL=C754Series", - "rp=ipp/print","priority=54","tr=Generic 35c-4", "product=DriverName", - "pdl=application/postscript,image/urf,application/octet-stream,image/jpeg", - "adminurl=http://KM00D91C.local./wcd/a_network.xml", - "note=Copy Room", "Transparent=T", "Binary=T", "TBCP=T", - "URF=V1,4,w8,SRGB24,ADOBERGB24-48,DEVW8,DEVRGB24,DEVCMYK32,RS150000000,IS19-20-21,MT1-3,OB1,PQ4,DM1,FN3-14,CP255", - "rfo=ipp/faxout", "Fax=T", "Scan=T", "Duplex=T", "Color=T", "air=none", - "Kind=document,envelope,photo", - "PaperMax=tabloid-A3", "UUID=6c183832-69ba-541b-baf6-6d947c144325", "TLS=1.2" - }; - - char *default_txt_rsp_1_for_serive[2] = { "_printer", "_pdl-datastream" }; - char *default_txt_rsp_1[13] = { - "txtvers=1", "qtotal=1", "usb_MFG=KONICA MINOLTA", "usb_MDL=C754Series", - "rp=print","priority=51","tr=Generic 35c-4", "product=DriverName", - "pdl=application/postscript", "note=Copy Room", "Transparent=T", "Binary=T", "TBCP=F" - }; - - char *default_txt_rsp_2_for_serive[2] = { "_http", "_https" }; - char *default_txt_rsp_2[1] = { - "Path=/" - }; - - char *default_txt_rsp_3_for_serive[1] = { "_privet" }; - char *default_txt_rsp_3[5] = { - "txtvers=1", "url=https://www.google.com/cloudprint", - "type=printer", "cs=not-configured","note=Copy Room" - }; - - char *default_txt_rsp_4_for_serive[1] = { "_uscan" }; - char *default_txt_rsp_4[11] = { - "txtvers=1", "vers=2.5", "adminurl=http://KM00D91C.local./wsd/a_network_airprint.xml", - "representation=http://KM00D91C.local./wcd/DeviceIcon_1283png", - "rs=eSCL", "ty=KONICA MINOLTA bishub C287", "note=japan", - "pdl=image/jpeg,image/tiff,application/pdf", - "UUID=dd5454cc-e196-5711-aa1f-35be49a6ca9f", - "cs=color,grayscale,binary", "is=platen,adf,duplex=T" - }; - - - /* reset ===> */ + int ratelen, network_type = 0; + u32 SIFS_Timer; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned char *rate = cur_network->SupportedRates; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P */ - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_domain_name, 0, MAX_MDNS_DOMAIN_NAME_LEN); - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_mnane, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_mnane)); - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_service, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_service)); - _rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_txt_rsp)); + ratelen = rtw_get_rateset_len(cur_network->SupportedRates); - pwrpriv->wowlan_war_offload_mdns_domain_name_len = 0; - pwrpriv->wowlan_war_offload_mdns_mnane_num = 0; - pwrpriv->wowlan_war_offload_mdns_service_info_num = 0; - pwrpriv->wowlan_war_offload_mdns_txt_rsp_num = 0; - pwrpriv->wowlan_war_offload_mdns_para_cur_size = 0; - pwrpriv->wowlan_war_offload_mdns_rsp_cur_size = 0; + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + pmlmeinfo->HT_enable = 1; - /* init ===> */ + if (pmlmeext->chandef.chan > 14) { + if (pmlmeinfo->HE_enable) + network_type = WLAN_MD_11AX; + else if (pmlmeinfo->VHT_enable) + network_type = WLAN_MD_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WLAN_MD_11N; - if(is_set_default) - { - // domain_name - pwrpriv->wowlan_war_offload_mdns_domain_name_len = strlen(default_domain_name); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_domain_name, default_domain_name, sizeof(default_domain_name)); - - // machine name - pwrpriv->wowlan_war_offload_mdns_mnane_num = 1; - pwrpriv->wowlan_war_offload_mdns_mnane[0].name_len = default_machine_name_len; - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_mnane[0].name, default_machine_name, default_machine_name_len); - - // service info - pwrpriv->wowlan_war_offload_mdns_service_info_num = 8; - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_service, default_sinfo, sizeof(default_sinfo)); - - // type txt rsp 0~5 - // 0 - for(offset=0, i=0; i<25; i++) - { - pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt[offset++] = strlen(default_txt_rsp_0[i]); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt + offset, default_txt_rsp_0[i], strlen(default_txt_rsp_0[i])); - offset += strlen(default_txt_rsp_0[i]); - RTW_INFO("==> default_txt_rsp_0[%d]: [%s](%zu), offset(%d)\n", i, default_txt_rsp_0[i], strlen(default_txt_rsp_0[i]), offset); - } - pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt_len = offset; - // RTW_INFO("==> offset = %d\n\n", offset); + network_type |= WLAN_MD_11A; + } else { + if (pmlmeinfo->HE_enable) + network_type = WLAN_MD_11AX; + else if (pmlmeinfo->VHT_enable) + network_type = WLAN_MD_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WLAN_MD_11N; - - // 1 - for(offset=0, i=0; i<13; i++) - { - pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt[offset++] = strlen(default_txt_rsp_1[i]); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt + offset, default_txt_rsp_1[i], strlen(default_txt_rsp_1[i])); - offset += strlen(default_txt_rsp_1[i]); - } - pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt_len = offset; - // RTW_INFO("==> offset = %d\n\n", offset); - - // 2 - for(offset=0, i=0; i<1; i++) - { - pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt[offset++] = strlen(default_txt_rsp_2[i]); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt + offset, default_txt_rsp_2[i], strlen(default_txt_rsp_2[i])); - offset += strlen(default_txt_rsp_2[i]); - } - pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt_len = offset; - // RTW_INFO("==> offset = %d\n\n", offset); - - // 3 - for(offset=0, i=0; i<5; i++) - { - pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt[offset++] = strlen(default_txt_rsp_3[i]); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt + offset, default_txt_rsp_3[i], strlen(default_txt_rsp_3[i])); - offset += strlen(default_txt_rsp_3[i]); - } - pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt_len = offset; - // RTW_INFO("==> offset = %d\n\n", offset); - - // 4 - for(offset=0, i=0; i<11; i++) - { - pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt[offset++] = strlen(default_txt_rsp_4[i]); - _rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt + offset, default_txt_rsp_4[i], strlen(default_txt_rsp_4[i])); - offset += strlen(default_txt_rsp_4[i]); - } - pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt_len = offset; - // RTW_INFO("==> offset = %d\n\n", offset); - - /* txt_rsp_num is always as MAX_MDNS_TXT_NUM because the input mechanism(new/append) makes the entities are not in order */ - pwrpriv->wowlan_war_offload_mdns_txt_rsp_num = MAX_MDNS_TXT_NUM; + if ((cckratesonly_included(rate, ratelen)) == _TRUE) + network_type |= WLAN_MD_11B; + else if ((cckrates_included(rate, ratelen)) == _TRUE) + network_type |= WLAN_MD_11BG; + else + network_type |= WLAN_MD_11G; } -} + pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; + /* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */ -#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */ -#endif /* CONFIG_WAR_OFFLOAD */ -#endif /* CONFIG_WOWLAN */ + if ((pmlmeext->cur_wireless_mode & WLAN_MD_11B) && + #ifdef CONFIG_P2P + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && + #endif + 1) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); + else + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); +} -inline bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap) +void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct wow_ctl_t *wow_ctl = &dvobj->wow_ctl; - - if (wow_ctl->wow_cap & cap) - return _TRUE; - return _FALSE; + if (is_supported_tx_cck(wireless_mode)) { + /* Only B, B/G, and B/G/N AP could use CCK rate */ + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4); + psta->bssratelen = 4; + } else { + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3); + psta->bssratelen = 3; + } } -#ifdef CONFIG_PNO_SUPPORT -#define CSCAN_TLV_TYPE_SSID_IE 'S' -#define CIPHER_IE "key_mgmt=" -#define CIPHER_NONE "NONE" -#define CIPHER_WPA_PSK "WPA-PSK" -#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X" -/* - * SSIDs list parsing from cscan tlv list - */ -int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, - int max, int *bytes_left) +int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num) { - char *str; - - int idx = 0; + u8 *ie, *p; + unsigned int ie_len; + int i, j; - if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) { - RTW_INFO("%s error paramters\n", __func__); - return -1; - } + struct support_rate_handler support_rate_tbl[] = { + {IEEE80211_CCK_RATE_1MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_2MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_5MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_11MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_6MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_9MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_12MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_18MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_24MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_36MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_48MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_54MB, _FALSE, _FALSE}, + }; + + if (!rate_set || !rate_num) + return _FALSE; - str = *list_str; - while (*bytes_left > 0) { + *rate_num = 0; + ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie == NULL) + goto ext_rate; - if (str[0] != CSCAN_TLV_TYPE_SSID_IE) { - *list_str = str; - RTW_INFO("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]); - return idx; + /* get valid supported rates */ + for (i = 0; i < 12; i++) { + p = ie + 2; + for (j = 0; j < ie_len; j++) { + if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ + support_rate_tbl[i].existence = _TRUE; + if ((*p) & BIT(7)) + support_rate_tbl[i].basic = _TRUE; + } + p++; } + } - /* Get proper CSCAN_TLV_TYPE_SSID_IE */ - *bytes_left -= 1; - str += 1; - - if (str[0] == 0) { - /* Broadcast SSID */ - ssid[idx].SSID_len = 0; - memset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN); - *bytes_left -= 1; - str += 1; - - RTW_INFO("BROADCAST SCAN left=%d\n", *bytes_left); - } else if (str[0] <= WLAN_SSID_MAXLEN) { - /* Get proper SSID size */ - ssid[idx].SSID_len = str[0]; - *bytes_left -= 1; - str += 1; - - /* Get SSID */ - if (ssid[idx].SSID_len > *bytes_left) { - RTW_INFO("%s out of memory range len=%d but left=%d\n", - __func__, ssid[idx].SSID_len, *bytes_left); - return -1; +ext_rate: + ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie) { + /* get valid extended supported rates */ + for (i = 0; i < 12; i++) { + p = ie + 2; + for (j = 0; j < ie_len; j++) { + if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ + support_rate_tbl[i].existence = _TRUE; + if ((*p) & BIT(7)) + support_rate_tbl[i].basic = _TRUE; + } + p++; } + } + } - memcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len); + for (i = 0; i < 12; i++){ + if (support_rate_tbl[i].existence){ + if (support_rate_tbl[i].basic) + rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK; + else + rate_set[*rate_num] = support_rate_tbl[i].rate; + *rate_num += 1; + } + } - *bytes_left -= ssid[idx].SSID_len; - str += ssid[idx].SSID_len; + if (*rate_num == 0) + return _FAIL; - RTW_INFO("%s :size=%d left=%d\n", - (char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left); - } else { - RTW_INFO("### SSID size more that %d\n", str[0]); - return -1; - } + if (0) { + int i; - if (idx++ > max) { - RTW_INFO("%s number of SSIDs more that %d\n", __func__, idx); - return -1; - } + for (i = 0; i < *rate_num; i++) + RTW_INFO("rate:0x%02x\n", *(rate_set + i)); } - *list_str = str; - return idx; + return _SUCCESS; } -int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str) +void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) { + struct sta_info *psta; + u16 tid, start_seq, param; + struct sta_priv *pstapriv = &padapter->stapriv; + struct ADDBA_request *preq = (struct ADDBA_request *)paddba_req; + u8 size, accept = _FALSE; - char *pch, *pnext, *pend; - u8 key_len = 0, index = 0; + psta = rtw_get_stainfo(pstapriv, addr); + if (!psta) + goto exit; - pch = list_str; + start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; + param = le16_to_cpu(preq->BA_para_set); + tid = (param >> 2) & 0x0f; - if (nlo_info == NULL || list_str == NULL) { - RTW_INFO("%s error paramters\n", __func__); - return -1; + accept = rtw_rx_ampdu_is_accept(padapter); + if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + size = padapter->fix_rx_ampdu_size; + else { + size = rtw_rx_ampdu_size(padapter); + size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta)); } - while (strlen(pch) != 0) { - pnext = strstr(pch, "key_mgmt="); - if (pnext != NULL) { - pch = pnext + strlen(CIPHER_IE); - pend = strstr(pch, "}"); - if (strncmp(pch, CIPHER_NONE, - strlen(CIPHER_NONE)) == 0) - nlo_info->ssid_cipher_info[index] = 0x00; - else if (strncmp(pch, CIPHER_WPA_PSK, - strlen(CIPHER_WPA_PSK)) == 0) - nlo_info->ssid_cipher_info[index] = 0x66; - else if (strncmp(pch, CIPHER_WPA_EAP, - strlen(CIPHER_WPA_EAP)) == 0) - nlo_info->ssid_cipher_info[index] = 0x01; - index++; - pch = pend + 1; - } else - break; - } - return 0; + if (accept == _TRUE) + rtw_addbarsp_cmd(padapter, addr, tid, preq, 0, size, start_seq); + else + rtw_addbarsp_cmd(padapter, addr, tid, preq, 37, size, start_seq);/* reject ADDBA Req */ + +exit: + return; } -int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, - int num, int pno_time, int pno_repeat, int pno_freq_expo_max) +void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame) { + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl = NULL; + u8 tid = 0; + u16 start_seq=0; - int i = 0; - struct file *fp; - mm_segment_t fs; - loff_t pos = 0; - u8 *source = NULL; - long len = 0; - - RTW_INFO("+%s+\n", __func__); - - nlo_info->fast_scan_period = pno_time; - nlo_info->ssid_num = num & BIT_LEN_MASK_32(8); - nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8); - nlo_info->slow_scan_period = (pno_time * 2); - nlo_info->fast_scan_iterations = 5; - - if (nlo_info->hidden_ssid_num > 8) - nlo_info->hidden_ssid_num = 8; + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + goto exit; - /* TODO: channel list and probe index is all empty. */ - for (i = 0 ; i < num ; i++) { - nlo_info->ssid_length[i] - = ssid[i].SSID_len; - } + tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12); + preorder_ctrl = &psta->recvreorder_ctrl[tid]; + start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4); + preorder_ctrl->indicate_seq = start_seq; - /* cipher array */ - fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY, 0644); - if (IS_ERR(fp)) { - RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n"); - RTW_INFO("Error, cipher array using default value.\n"); - return 0; - } + rtw_phl_rx_bar(padapter->dvobj->phl, psta->phl_sta, tid, start_seq); + /* for Debug use */ + if (0) + RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter), tid, start_seq); - len = i_size_read(fp->f_path.dentry->d_inode); - if (len < 0 || len > 2048) { - RTW_INFO("Error, file size is bigger than 2048.\n"); - RTW_INFO("Error, cipher array using default value.\n"); - return 0; - } +exit: + return; +} - fs = get_fs(); - set_fs(KERNEL_DS); +void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +{ + u8 *pIE; + u32 *pbuf; - source = rtw_zmalloc(2048); + pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pbuf = (u32 *)pIE; - if (source != NULL) { - len = vfs_read(fp, source, len, &pos); - rtw_parse_cipher_list(nlo_info, source); - rtw_mfree(source, 2048); - } + pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1)); - set_fs(fs); - filp_close(fp, NULL); + pmlmeext->TSFValue = pmlmeext->TSFValue << 32; - RTW_INFO("-%s-\n", __func__); - return 0; + pmlmeext->TSFValue |= le32_to_cpu(*pbuf); } -int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list, - pno_ssid_t *ssid, u8 num) +#ifdef CONFIG_BCN_RECV_TIME +/* calculate beacon receiving time + 1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us] + 2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us] +*/ +inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate) { + u16 rx_bcn_time = 0;/*us*/ - int i = 0; - if (num > MAX_PNO_LIST_COUNT) - num = MAX_PNO_LIST_COUNT; - - for (i = 0 ; i < num ; i++) { - _rtw_memcpy(&pno_ssid_list->node[i].SSID, - ssid[i].SSID, ssid[i].SSID_len); - pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len; - } - return 0; + if (data_rate == DESC_RATE1M) + rx_bcn_time = 192 + bcn_len * 8 + 10; + else if(data_rate == DESC_RATE6M) + rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10; +/* + else + RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate); +*/ + return rx_bcn_time; } - -int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid, - unsigned char ch, unsigned char ch_offset, unsigned short bw_mode) +void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate) { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); - struct pno_scan_info *scan_info = pwrctl->pscan_info; - u8 band = ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G; - int i; - - scan_info->channel_num = MAX_SCAN_LIST_COUNT; - scan_info->orig_ch = ch; - scan_info->orig_bw = bw_mode; - scan_info->orig_40_offset = ch_offset; - - for (i = 0 ; i < scan_info->channel_num ; i++) { - if (i < 11) - scan_info->ssid_channel_info[i].active = 1; - else - scan_info->ssid_channel_info[i].active = 0; - - scan_info->ssid_channel_info[i].timeout = 100; - - scan_info->ssid_channel_info[i].tx_power = - phy_get_tx_power_index_ex(padapter, 0, CCK, MGN_1M, bw_mode, band, i + 1, i + 1); - - scan_info->ssid_channel_info[i].channel = i + 1; - } + pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate); +} +#endif - RTW_INFO("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n", - __func__, scan_info->channel_num, scan_info->orig_ch, - scan_info->orig_bw, scan_info->orig_40_offset); - return 0; +void beacon_timing_control(_adapter *padapter) +{ + rtw_hal_bcn_param_setting(padapter); } -int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, - int pno_time, int pno_repeat, int pno_freq_expo_max) +inline void rtw_collect_bcn_info(_adapter *adapter) { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - _adapter *padapter = (_adapter *)rtw_netdev_priv(net); - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + if (!is_client_associated_to_ap(adapter)) + return; - int ret = -1; + pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt; + pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt; + /*TODO get offset of bcn's timestamp*/ + /*pmlmeext->bcn_timestamp;*/ +} - if (num == 0) { - RTW_INFO("%s, nssid is zero, no need to setup pno ssid list\n", __func__); +inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 >= bmp_len) return 0; - } - - if (pwrctl == NULL) { - RTW_INFO("%s, ERROR: pwrctl is NULL\n", __func__); - return -1; - } else { - pwrctl->pnlo_info = - (pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t)); - pwrctl->pno_ssid_list = - (pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t)); - pwrctl->pscan_info = - (pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t)); - } - - if (pwrctl->pnlo_info == NULL || - pwrctl->pscan_info == NULL || - pwrctl->pno_ssid_list == NULL) { - RTW_INFO("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__); - goto failing; - } - pwrctl->wowlan_in_resume = _FALSE; - - pwrctl->pno_inited = _TRUE; - /* NLO Info */ - ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num, - pno_time, pno_repeat, pno_freq_expo_max); - - /* SSID Info */ - ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num); + return bmp[id / 8] & BIT(id % 8); +} - /* SCAN Info */ - ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel, - pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); +inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] |= BIT(id % 8); +} - RTW_INFO("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n", - __func__, num, pno_time, pno_repeat, pno_freq_expo_max); +inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] &= ~BIT(id % 8); +} - return 0; +inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len) +{ + int i; -failing: - if (pwrctl->pnlo_info) { - rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t)); - pwrctl->pnlo_info = NULL; - } - if (pwrctl->pno_ssid_list) { - rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t)); - pwrctl->pno_ssid_list = NULL; - } - if (pwrctl->pscan_info) { - rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t)); - pwrctl->pscan_info = NULL; + for (i = 0; i < bmp_len; i++) { + if (bmp[i]) + return 1; } - return -1; + return 0; } -#ifdef CONFIG_PNO_SET_DEBUG -void rtw_dev_pno_debug(struct net_device *net) +inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len) { - _adapter *padapter = (_adapter *)rtw_netdev_priv(net); - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); - int i = 0, j = 0; - - RTW_INFO("*******NLO_INFO********\n"); - RTW_INFO("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num); - RTW_INFO("fast_scan_iterations: %d\n", - pwrctl->pnlo_info->fast_scan_iterations); - RTW_INFO("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period); - RTW_INFO("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period); - - + int i; - for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { - RTW_INFO("%d SSID (%s) length (%d) cipher(%x) channel(%d)\n", - i, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i], - pwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]); + for (i = 0; i < bmp_len; i++) { + if (i == 0) { + if (bmp[i] & 0xFE) + return 1; + } else { + if (bmp[i]) + return 1; + } } - RTW_INFO("******SCAN_INFO******\n"); - RTW_INFO("ch_num: %d\n", pwrctl->pscan_info->channel_num); - RTW_INFO("orig_ch: %d\n", pwrctl->pscan_info->orig_ch); - RTW_INFO("orig bw: %d\n", pwrctl->pscan_info->orig_bw); - RTW_INFO("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset); - for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) { - RTW_INFO("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n", - i, pwrctl->pscan_info->ssid_channel_info[i].active, - pwrctl->pscan_info->ssid_channel_info[i].timeout, - pwrctl->pscan_info->ssid_channel_info[i].tx_power, - pwrctl->pscan_info->ssid_channel_info[i].channel); - } - RTW_INFO("*****************\n"); + return 0; } -#endif /* CONFIG_PNO_SET_DEBUG */ -#endif /* CONFIG_PNO_SUPPORT */ -inline void rtw_collect_bcn_info(_adapter *adapter) +#ifdef CONFIG_AP_MODE +/* Check the id be set or not in map , if yes , return a none zero value*/ +bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id) { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id); +} - if (!is_client_associated_to_ap(adapter)) - return; +/* Set the id into map array*/ +void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id); +} - pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt; - pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt; - /*TODO get offset of bcn's timestamp*/ - /*pmlmeext->bcn_timestamp;*/ +/* Clear the id from map array*/ +void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id); } -static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi) +/* Check have anyone bit be set , if yes return true*/ +bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map) { - static const u32 base[4][10] = { - { 6500000, - 13000000, - 19500000, - 26000000, - 39000000, - 52000000, - 58500000, - 65000000, - 78000000, - /* not in the spec, but some devices use this: */ - 86500000, - }, - { 13500000, - 27000000, - 40500000, - 54000000, - 81000000, - 108000000, - 121500000, - 135000000, - 162000000, - 180000000, - }, - { 29300000, - 58500000, - 87800000, - 117000000, - 175500000, - 234000000, - 263300000, - 292500000, - 351000000, - 390000000, - }, - { 58500000, - 117000000, - 175500000, - 234000000, - 351000000, - 468000000, - 526500000, - 585000000, - 702000000, - 780000000, - }, - }; - u32 bitrate; - int bw_idx; + return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len); +} - if (mcs > 9) { - RTW_INFO("Invalid mcs = %d\n", mcs); - return 0; - } +/* Check have anyone bit be set exclude bit0 , if yes return true*/ +bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map) +{ + return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len); +} +#endif /* CONFIG_AP_MODE */ - if (nss > 4 || nss < 1) { - RTW_INFO("Now only support nss = 1, 2, 3, 4\n"); - } +_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj) +{ + _adapter *adapter = NULL; + int i; - switch (bw) { - case CHANNEL_WIDTH_160: - bw_idx = 3; - break; - case CHANNEL_WIDTH_80: - bw_idx = 2; - break; - case CHANNEL_WIDTH_40: - bw_idx = 1; - break; - case CHANNEL_WIDTH_20: - bw_idx = 0; - break; - default: - RTW_INFO("bw = %d currently not supported\n", bw); - return 0; + for (i = 0; i < dvobj->iface_nums; i++) { + if (dvobj->padapters[i]->registered == 0) + break; } - bitrate = base[bw_idx][mcs]; - bitrate *= nss; - - if (sgi) - bitrate = (bitrate / 9) * 10; + if (i < dvobj->iface_nums) + adapter = dvobj->padapters[i]; - /* do NOT round down here */ - return (bitrate + 50000) / 100000; + return adapter; } -static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi) +_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr) { - int modulation, streams, bitrate; - - /* the formula below does only work for MCS values smaller than 32 */ - if (mcs >= 32) { - RTW_INFO("Invalid mcs = %d\n", mcs); - return 0; - } + _adapter *adapter = NULL; + int i; - if (bw > 1) { - RTW_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n"); - return 0; + for (i = 0; i < dvobj->iface_nums; i++) { + if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE) + break; } - modulation = mcs & 7; - streams = (mcs >> 3) + 1; - - bitrate = (bw == 1) ? 13500000 : 6500000; - - if (modulation < 4) - bitrate *= (modulation + 1); - else if (modulation == 4) - bitrate *= (modulation + 2); - else - bitrate *= (modulation + 3); - - bitrate *= streams; - - if (sgi) - bitrate = (bitrate / 9) * 10; + if (i < dvobj->iface_nums) + adapter = dvobj->padapters[i]; - return (bitrate + 50000) / 100000; + return adapter; } -/** - * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz) - * @rate_idx: DESC_RATEXXXX & 0x7f - * @sgi: DESC_RATEXXXX >> 7 - * Returns: bitrate in 100kbps - */ -u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi) +u16 rtw_get_current_tx_rate(_adapter *adapter, struct sta_info *psta) { - u32 bitrate; - - if (rate_idx <= DESC_RATE54M){ - u16 ofdm_rate[12] = {10, 20, 55, 110, - 60, 90, 120, 180, 240, 360, 480, 540}; - - bitrate = ofdm_rate[rate_idx]; - } else if ((DESC_RATEMCS0 <= rate_idx) && - (rate_idx <= DESC_RATEMCS31)) { - u8 mcs = rate_idx - DESC_RATEMCS0; + u16 rate_id = 0; + struct rtw_phl_rainfo ra_info; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - bitrate = rtw_get_ht_bitrate(mcs, bw, sgi); - } else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) && - (rate_idx <= DESC_RATEVHTSS4MCS9)) { - u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10; - u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1; + if (!psta) + return rate_id; - bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi); - } else { - /* TODO: 60Ghz */ - bitrate = 1; + if (adapter->fix_rate != NO_FIX_RATE) + rate_id = GET_FIX_RATE(adapter->fix_rate); + else { + rtw_phl_query_rainfo(dvobj->phl, psta->phl_sta, &ra_info); + rate_id = ra_info.rate; /* enum rtw_data_rate */ } - return bitrate; + return rate_id; } #ifdef CONFIG_RTW_MULTI_AP u8 rtw_get_ch_utilization(_adapter *adapter) { +#if 0 /* FIXME */ u16 clm = rtw_phydm_clm_ratio(adapter); u16 nhm = rtw_phydm_nhm_ratio(adapter); +#else + u16 clm = 55; + u16 nhm = 55; +#endif u16 ch_util; ch_util = clm / 3 + (2 * (nhm / 3)); @@ -5619,11 +3159,13 @@ void rtw_ch_util_rpt(_adapter *adapter) ch_util = rtw_zmalloc(sizeof(u8) * dvobj->iface_nums); if (!ch_util) goto err_out; - bssid = (u8 **) rtw_zmalloc(sizeof(u8 *) * dvobj->iface_nums); + + bssid = (u8 **)rtw_zmalloc(sizeof(u8 *) * dvobj->iface_nums); if (!bssid) goto err_out1; + for (j = 0; j < dvobj->iface_nums; j++) { - *(bssid + j) = (u8 *) rtw_zmalloc(sizeof(u8) * ETH_ALEN); + *(bssid + j) = (u8 *)rtw_zmalloc(sizeof(u8) * ETH_ALEN); if (!(*(bssid + j))) goto err_out2; } @@ -5633,7 +3175,6 @@ void rtw_ch_util_rpt(_adapter *adapter) if ((iface) && MLME_IS_AP(iface)) { *(ch_util + i_rpts) = rtw_get_ch_utilization(iface); _rtw_memcpy(*(bssid + i_rpts), iface->mac_addr, ETH_ALEN); - if (*(ch_util + i_rpts) > threshold) need_rpt = 1; @@ -5647,6 +3188,7 @@ void rtw_ch_util_rpt(_adapter *adapter) rtw_mfree(ch_util, sizeof(u8) * dvobj->iface_nums); for (i = 0; i < dvobj->iface_nums; i++) rtw_mfree(*(bssid + i), ETH_ALEN); + rtw_mfree(bssid, sizeof(u8 *) * dvobj->iface_nums); return; @@ -5661,4 +3203,3 @@ void rtw_ch_util_rpt(_adapter *adapter) RTW_INFO("[%s] rtw_zmalloc fail\n", __func__); } #endif - diff --git a/core/rtw_wnm.c b/core/rtw_wnm.c index 293eb86..118ce64 100644 --- a/core/rtw_wnm.c +++ b/core/rtw_wnm.c @@ -14,7 +14,6 @@ *****************************************************************************/ #include -#include #ifndef RTW_WNM_DBG #define RTW_WNM_DBG 0 @@ -38,9 +37,15 @@ static u32 wnm_disassoc_wait_time = 500; /* for wifi test, need more validity time to wait scan done */ static u32 wnm_ext_validity_time = 4000; -static void rtw_wmn_btm_cache_update(_adapter *padapter, struct btm_req_hdr *phdr) +static u8 wnm_non_pref_ch_oui[] = {0x50, 0x6F, 0x9A, 0x2}; + +#define rtw_wnm_get_non_pref_ch_oui(p) ((u8 *)(p) + 2) + +static void rtw_wmn_btm_cache_update( + _adapter *padapter, struct btm_req_hdr *phdr) { - struct btm_rpt_cache *pcache = &(padapter->mlmepriv.nb_info.btm_cache); + struct btm_rpt_cache *pcache = \ + &(padapter->mlmepriv.nb_info.btm_cache); pcache->dialog_token = phdr->dialog_token; pcache->req_mode = phdr->req_mode; @@ -57,8 +62,8 @@ static void rtw_wmn_btm_cache_update(_adapter *padapter, struct btm_req_hdr *phd RTW_WNM_INFO("%s: req_mode(0x%02x), disassoc_timer(0x%04x), " "validity_interval(0x%02x %s), tsf(0x%llx), duration(0x%02x)\n", __func__, pcache->req_mode, pcache->disassoc_timer, - pcache->validity_interval, (!phdr->validity_interval)?"default":"", - pcache->term_duration.tsf, + pcache->validity_interval, (!phdr->validity_interval)? + "default":"", pcache->term_duration.tsf, pcache->term_duration.duration); if (pcache->validity_interval > 0) { @@ -83,7 +88,8 @@ static void rtw_wmn_btm_cache_update(_adapter *padapter, struct btm_req_hdr *phd __func__, pcache->validity_time, pcache->disassoc_time); } -static u8 rtw_wnm_btm_candidate_validity(struct btm_rpt_cache *pcache, u8 flag) +static u8 rtw_wnm_btm_candidate_validity( + struct btm_rpt_cache *pcache, u8 flag) { u8 is_validity =_TRUE; u32 req_validity_time = rtw_get_passing_time_ms(pcache->req_stime); @@ -102,8 +108,8 @@ static u8 rtw_wnm_btm_candidate_validity(struct btm_rpt_cache *pcache, u8 flag) u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode) { - struct recv_priv *precvpriv = &padapter->recvpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct recv_info *recvinfo = &(padapter->recvinfo); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); u8 reason = 0; if (!rtw_wnm_btm_diff_bss(padapter)) { @@ -117,25 +123,26 @@ u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode) /* Accept */ reason = 0; goto under_survey; - } + } #endif if (((*req_mode) & DISASSOC_IMMINENT) == 0) { /* Reject - Unspecified reject reason */ reason = 1; goto candidate_remove; - } + } - if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) { + if (recvinfo->signal_strength_data.avg_val >= + pmlmepriv->roam_rssi_threshold) { reason = 1; RTW_WNM_INFO("%s : Reject - under high roam rssi(%u, %u) \n", - __func__, precvpriv->signal_strength_data.avg_val, + __func__, recvinfo->signal_strength_data.avg_val, pmlmepriv->roam_rssi_threshold); goto candidate_remove; } #ifdef CONFIG_RTW_80211R -under_survey: +under_survey: if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) { RTW_WNM_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__); reason = 1; @@ -193,14 +200,20 @@ static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr) phdr->term_duration.tsf = *((u64*)(pos + 2)); phdr->term_duration.duration= *((u16*)(pos + 10)); } else - RTW_WNM_INFO("%s : invaild BSS Termination Duration content!\n", __func__); + RTW_WNM_INFO("%s : invaild BSS Termination Duration" + " content!\n", __func__); } - RTW_WNM_INFO("WNM: req_mode(0x%02x), disassoc_timer(0x%04x), validity_interval(0x%02x)\n", - phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval); - if (wnm_btm_bss_term_inc(pframe)) + RTW_WNM_INFO("WNM: req_mode(0x%02x), disassoc_timer(0x%04x)," + " validity_interval(0x%02x)\n", + phdr->req_mode, phdr->disassoc_timer, + phdr->validity_interval); + + if (wnm_btm_bss_term_inc(pframe)) { RTW_WNM_INFO("WNM: tsf(0x%llx), duration(0x%4x)\n", - phdr->term_duration.tsf, phdr->term_duration.duration); + phdr->term_duration.tsf, + phdr->term_duration.duration); + } } u8 rtw_wnm_btm_reassoc_req(_adapter *padapter) @@ -213,10 +226,10 @@ u8 rtw_wnm_btm_reassoc_req(_adapter *padapter) if (_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), pnb->roam_target_addr, ETH_ALEN)) { - RTW_WNM_INFO("%s : bss "MAC_FMT" found in roam_target "MAC_FMT"\n", - __func__, MAC_ARG(get_my_bssid(&(pmlmeinfo->network))), + RTW_WNM_INFO("%s : bss "MAC_FMT" found in roam_target " + MAC_FMT"\n", __func__, + MAC_ARG(get_my_bssid(&(pmlmeinfo->network))), MAC_ARG(pnb->roam_target_addr)); - breassoc = _TRUE; } @@ -228,13 +241,16 @@ void rtw_wnm_roam_scan_hdl(void *ctx) _adapter *padapter = (_adapter *)ctx; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - if (rtw_is_scan_deny(padapter)) - RTW_WNM_INFO("%s: roam scan would abort by scan_deny!\n", __func__); + if (rtw_is_scan_deny(padapter)) { + RTW_WNM_INFO("%s: roam scan would abort by scan_deny!\n", + __func__); + } #ifdef CONFIG_RTW_80211R if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) { pmlmepriv->need_to_roam = _TRUE; - rtw_set_to_roam(padapter, padapter->registrypriv.max_roaming_times); + rtw_set_to_roam(padapter, + padapter->registrypriv.max_roaming_times); RTW_WNM_INFO("%s : enable roaming\n", __func__); } @@ -261,7 +277,8 @@ void rtw_wnm_disassoc_chk_hdl(void *ctx) RTW_WNM_INFO("%s : expired\n", __func__); if (pnb->disassoc_waiting <= 0 ) { - RTW_WNM_INFO("%s : btm roam is interrupted by disassoc\n", __func__); + RTW_WNM_INFO("%s : btm roam is interrupted by disassoc\n", + __func__); return; } @@ -277,7 +294,8 @@ u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter) u8 reason = 0, flag = 0; if (!rtw_wnm_btm_preference_cap(padapter)) { - RTW_WNM_INFO("%s : no btm candidate can be used!\n", __func__); + RTW_WNM_INFO("%s : no btm candidate can be used!\n", + __func__); return 1; } @@ -293,14 +311,16 @@ u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter) } #endif - RTW_WNM_INFO("%s : disassoc_waiting(%d)\n", __func__, pnb->disassoc_waiting); + RTW_WNM_INFO("%s : disassoc_waiting(%d)\n", + __func__, pnb->disassoc_waiting); if (pnb->disassoc_waiting) { _cancel_timer_ex(&pnb->disassoc_chk_timer); pnb->disassoc_waiting = _FALSE; rtw_wnm_roam_scan_hdl((void *)padapter); - } else if (!pnb->disassoc_waiting) - RTW_WNM_INFO("%s : waiting for btm roaming start/finish\n", __func__); - else + } else if (!pnb->disassoc_waiting) { + RTW_WNM_INFO("%s : waiting for btm roaming start/finish\n", + __func__); + } else reason = 1; return reason; @@ -319,8 +339,9 @@ void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len) return; if ((frame_len - offset) <= 15) { - RTW_INFO("WNM : Reject - no suitable BSS transition candidates!\n"); - rtw_wnm_issue_action(padapter, + RTW_INFO("WNM : Reject - " + "no suitable BSS transition candidates!\n"); + rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_BTM_RSP, 7, req_hdr.dialog_token); return; } @@ -335,16 +356,17 @@ void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len) #ifdef CONFIG_RTW_MBO /* for wifi-test; AP2 could power-off when BTM-req received */ if ((reason > 0) && (rtw_mbo_wifi_logo_test(padapter))) { - _rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[0].bssid, ETH_ALEN); - RTW_WNM_INFO("%s : used report 0 as roam_target_addr(reason=%u)\n", - __func__, reason); + _rtw_memcpy(pnb->roam_target_addr, + pnb->nb_rpt[0].bssid, ETH_ALEN); + RTW_WNM_INFO("%s : used report 0 as roam_target_addr" + "(reason=%u)\n", __func__, reason); reason = 0; pnb->preference_en = _TRUE; pnb->nb_rpt_valid = _FALSE; } #endif - rtw_wnm_issue_action(padapter, + rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_BTM_RSP, reason, req_hdr.dialog_token); if (reason == 0) { @@ -446,7 +468,8 @@ void rtw_wnm_process_btm_rsp(_adapter *padapter, /* STA BSS Transition Candidate List provided, and at least one NB report exist */ - if (((prsp->status == 0) || (prsp->status == 6)) && (frame_len >= 23)) { + if (((prsp->status == 0) || (prsp->status == 6)) \ + && (frame_len >= 23)) { struct wnm_btm_cant cant; u8 *ptr, *pend; u32 idx = 0; @@ -474,7 +497,8 @@ void rtw_wnm_process_btm_rsp(_adapter *padapter, ptr = ptr + cant.nb_rpt.len + 2; if (prsp->pcandidates) { prsp->candidates_num++; - _rtw_memcpy((prsp->pcandidates + sizeof(cant) * idx), &cant, sizeof(cant)); + _rtw_memcpy((prsp->pcandidates + \ + sizeof(cant) * idx), &cant, sizeof(cant)); } idx++; @@ -484,9 +508,11 @@ void rtw_wnm_process_btm_rsp(_adapter *padapter, MAC_ARG(cant.nb_rpt.bssid), cant.nb_rpt.bss_info, cant.nb_rpt.reg_class, cant.nb_rpt.ch_num, cant.nb_rpt.phy_type, cant.preference); - if ((prsp->pcandidates) && (prsp->candidates_num > 0)) + if ((prsp->pcandidates) && \ + (prsp->candidates_num > 0)) { RTW_WNM_DUMP("WNM candidates: ", prsp->pcandidates, (sizeof(struct wnm_btm_cant) * prsp->candidates_num)); + } } } @@ -505,7 +531,8 @@ void rtw_wnm_hdr_init(_adapter *padapter, pattrib = &(pactionframe->attrib); update_mgntframe_attrib(padapter, pattrib); - _rtw_memset(pactionframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET)); + _rtw_memset(pactionframe->buf_addr, 0, + (WLANHDR_OFFSET + TXDESC_OFFSET)); *pcontent = (u8 *)(pactionframe->buf_addr + TXDESC_OFFSET); pwlanhdr = (struct rtw_ieee80211_hdr *)(*pcontent); @@ -514,7 +541,8 @@ void rtw_wnm_hdr_init(_adapter *padapter, _rtw_memcpy(pwlanhdr->addr1, pmac, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&pmlmeinfo->network), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; @@ -524,8 +552,10 @@ void rtw_wnm_hdr_init(_adapter *padapter, pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); category = RTW_WLAN_CATEGORY_WNM; - *pcontent = rtw_set_fixed_ie(*pcontent, 1, &(category), &(pattrib->pktlen)); - *pcontent = rtw_set_fixed_ie(*pcontent, 1, &(action), &(pattrib->pktlen)); + *pcontent = rtw_set_fixed_ie(*pcontent, 1, + &(category), &(pattrib->pktlen)); + *pcontent = rtw_set_fixed_ie(*pcontent, 1, + &(action), &(pattrib->pktlen)); } void rtw_wnm_build_btm_req_ies(_adapter *padapter, @@ -550,9 +580,11 @@ void rtw_wnm_build_btm_req_ies(_adapter *padapter, *pframe = rtw_set_fixed_ie(*pframe, 1, &phdr->term_duration.len, &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 8, - (u8 *)&phdr->term_duration.tsf, &(pattrib->pktlen)); + (u8 *)&phdr->term_duration.tsf, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 2, - (u8 *)&phdr->term_duration.duration, &(pattrib->pktlen)); + (u8 *)&phdr->term_duration.duration, + &(pattrib->pktlen)); } if ((purl != NULL) && (url_len > 0) && @@ -570,28 +602,41 @@ void rtw_wnm_build_btm_req_ies(_adapter *padapter, struct nb_rpt_hdr *prpt = &(pcandidate->nb_rpt); *pframe = rtw_set_fixed_ie(*pframe, 1, - &pcandidate->nb_rpt.id, &(pattrib->pktlen)); + &pcandidate->nb_rpt.id, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 1, - &pcandidate->nb_rpt.len, &(pattrib->pktlen)); + &pcandidate->nb_rpt.len, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, ETH_ALEN, - pcandidate->nb_rpt.bssid, &(pattrib->pktlen)); + pcandidate->nb_rpt.bssid, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 4, - (u8 *)&pcandidate->nb_rpt.bss_info, &(pattrib->pktlen)); + (u8 *)&pcandidate->nb_rpt.bss_info, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 1, - &pcandidate->nb_rpt.reg_class, &(pattrib->pktlen)); + &pcandidate->nb_rpt.reg_class, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 1, - &pcandidate->nb_rpt.ch_num, &(pattrib->pktlen)); + &pcandidate->nb_rpt.ch_num, + &(pattrib->pktlen)); *pframe = rtw_set_fixed_ie(*pframe, 1, - &pcandidate->nb_rpt.phy_type, &(pattrib->pktlen)); - *pframe = rtw_set_ie(*pframe, WNM_BTM_CAND_PREF_SUBEID, 1, - (u8 *)&pcandidate->preference, &(pattrib->pktlen)); + &pcandidate->nb_rpt.phy_type, + &(pattrib->pktlen)); + *pframe = rtw_set_ie(*pframe, WNM_BTM_CAND_PREF_SUBEID, + 1, (u8 *)&pcandidate->preference, + &(pattrib->pktlen)); } } + +#ifdef CONFIG_RTW_MBO + rtw_mbo_build_wnm_btmreq_reason_ies(padapter, pframe, pattrib); +#endif } void rtw_wnm_issue_btm_req(_adapter *padapter, - u8 *pmac, struct btm_req_hdr *phdr, u8 *purl, u32 url_len, + u8 *pmac, struct btm_req_hdr *phdr, + u8 *purl, u32 url_len, u8 *pcandidates, u8 candidate_cnt) { struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); @@ -621,6 +666,7 @@ void rtw_wnm_issue_btm_req(_adapter *padapter, pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); + /* dump_mgntframe_and_wait_ack(padapter, pmgntframe); */ RTW_INFO("WNM: BSS Transition Management Request sent\n"); } @@ -643,7 +689,7 @@ void rtw_wnm_issue_action(_adapter *padapter, if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) return ; - + pattrib = &(pmgntframe->attrib); update_mgntframe_attrib(padapter, pattrib); _rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET)); @@ -654,9 +700,12 @@ void rtw_wnm_issue_action(_adapter *padapter, fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, + get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, + adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&pmlmeinfo->network), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; @@ -672,46 +721,71 @@ void rtw_wnm_issue_action(_adapter *padapter, switch (action) { case RTW_WLAN_ACTION_WNM_BTM_QUERY: dialog_token++; - pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(reason), &(pattrib->pktlen)); RTW_INFO("WNM: BSS Transition Management Query sent\n"); break; case RTW_WLAN_ACTION_WNM_BTM_RSP: dialog_token = dialog; termination_delay = 0; - pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen)); - if (!reason && !is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) { - pframe = rtw_set_fixed_ie(pframe, 6, - pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(reason), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(termination_delay), + &(pattrib->pktlen)); + if (!reason && !is_zero_mac_addr( + pmlmepriv->nb_info.roam_target_addr)) { + pframe = rtw_set_fixed_ie(pframe, 6, + pmlmepriv->nb_info.roam_target_addr, + &(pattrib->pktlen)); } #ifdef CONFIG_RTW_MBO - rtw_mbo_build_trans_reject_reason_attr(padapter, + rtw_mbo_build_trans_reject_reason_attr(padapter, &pframe, pattrib, &mbo_trans_rej_res); #endif - RTW_INFO("WNM: BSS Transition Management Response sent(reason:%d)\n", reason); + RTW_INFO("WNM: BSS Transition Management Response" + " sent(reason:%d)\n", reason); break; case RTW_WLAN_ACTION_WNM_NOTIF_REQ: -#ifdef CONFIG_RTW_MBO +#ifdef CONFIG_RTW_MBO dialog_token++; mbo_notif_req_type = WLAN_EID_VENDOR_SPECIFIC; - pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(mbo_notif_req_type), &(pattrib->pktlen)); - rtw_mbo_build_wnm_notification(padapter, &pframe, pattrib); + pframe = rtw_set_fixed_ie(pframe, 1, + &(dialog_token), + &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(mbo_notif_req_type), + &(pattrib->pktlen)); + rtw_mbo_build_wnm_notification(padapter, + &pframe, pattrib); RTW_INFO("WNM: Notification request sent\n"); +#endif + break; + case RTW_WLAN_ACTION_WNM_NOTIF_RSP: +#ifdef CONFIG_RTW_MBO + dialog_token = dialog; + pframe = rtw_set_fixed_ie(pframe, 1, + &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, + &(reason), &(pattrib->pktlen)); + RTW_INFO("WNM: Notification Response sent\n"); #endif break; default: goto exit; - } - + } + pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); + /* dump_mgntframe_and_wait_ack(padapter, pmgntframe); */ -exit: +exit: return; } @@ -730,14 +804,16 @@ void rtw_wnm_update_reassoc_req_ie(_adapter *padapter) /* total len is assoc req len without Current AP Field*/ dup_len = pmlmepriv->assoc_req_len - ETH_ALEN; - /* offset is a len of 80211 header + capability(2B) + listen interval(2B) */ + /* offset is a len of 80211 header + + capability(2B) + listen interval(2B) */ offset = sizeof(struct rtw_ieee80211_hdr_3addr) + 4; pdup = rtw_zmalloc(dup_len); if (pdup) { /* remove Current AP Field @reassoc req IE */ _rtw_memcpy(pdup, pmlmepriv->assoc_req, offset); - _rtw_memcpy(pdup + offset, pmlmepriv->assoc_req + offset + ETH_ALEN, + _rtw_memcpy(pdup + offset, + pmlmepriv->assoc_req + offset + ETH_ALEN, pmlmepriv->assoc_req_len - offset); rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, pdup, dup_len); @@ -751,7 +827,7 @@ void rtw_roam_nb_info_init(_adapter *padapter) { struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); struct btm_rpt_cache *pcache = &(pnb->btm_cache); - + _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt)); _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); _rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN); @@ -765,15 +841,11 @@ void rtw_roam_nb_info_init(_adapter *padapter) pnb->features = 0; /* pnb->features |= RTW_WNM_FEATURE_BTM_REQ_EN; */ -#ifdef CONFIG_PLATFORM_CMAP_INTFS - pnb->features |= RTW_WNM_FEATURE_BTM_REQ_EN; -#endif - - rtw_init_timer(&pnb->roam_scan_timer, - padapter, rtw_wnm_roam_scan_hdl, + rtw_init_timer(&pnb->roam_scan_timer, + rtw_wnm_roam_scan_hdl, padapter); rtw_init_timer(&pnb->disassoc_chk_timer, - padapter, rtw_wnm_disassoc_chk_hdl, + rtw_wnm_disassoc_chk_hdl, padapter); _rtw_memset(pcache, 0, sizeof(struct btm_rpt_cache)); @@ -808,7 +880,7 @@ u8 rtw_roam_nb_scan_list_set( rtw_init_sitesurvey_parm(padapter, pparm); if (rtw_roam_busy_scan(padapter, pnb)) { pparm->ch_num = 1; - pparm->ch[pmlmepriv->ch_cnt].hw_value = + pparm->ch[pmlmepriv->ch_cnt].hw_value = pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value; pmlmepriv->ch_cnt++; ret = _TRUE; @@ -832,16 +904,16 @@ u8 rtw_roam_nb_scan_list_set( } pmlmepriv->nb_info.nb_rpt_valid = _FALSE; - pmlmepriv->ch_cnt = 0; + pmlmepriv->ch_cnt = 0; ret = _TRUE; set_bssid_list: - rtw_set_802_11_bssid_list_scan(padapter, pparm); + rtw_sitesurvey_cmd(padapter, pparm); return ret; } static u8 rtw_wnm_nb_elem_parsing( - u8* pdata, u32 data_len, u8 from_btm, + u8* pdata, u32 data_len, u8 from_btm, u32 *nb_rpt_num, u8 *nb_rpt_is_same, struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates) { @@ -864,7 +936,7 @@ static u8 rtw_wnm_nb_elem_parsing( subelem_len = (u32)*(pdata+1); for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) { - if (((ptr + 7) > pend) || (elem_len < subelem_len)) + if (((ptr + 7) > pend) || (elem_len < subelem_len)) break; if (*ptr != RTW_WLAN_ACTION_WNM_NB_RPT_ELEM) { @@ -872,10 +944,10 @@ static u8 rtw_wnm_nb_elem_parsing( break; } - pie = (struct nb_rpt_hdr *)ptr; + pie = (struct nb_rpt_hdr *)ptr; if (from_btm) { - op = rtw_get_ie((u8 *)(ptr+15), - WNM_BTM_CAND_PREF_SUBEID, + op = rtw_get_ie((u8 *)(ptr+15), + WNM_BTM_CAND_PREF_SUBEID, &op_len, (subelem_len - 15)); } @@ -884,7 +956,8 @@ static u8 rtw_wnm_nb_elem_parsing( subelem_len = *(ptr+1); if (from_btm) { pcandidate = (pcandidates + i); - _rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr)); + _rtw_memcpy(&pcandidate->nb_rpt, pie, + sizeof(struct nb_rpt_hdr)); if (op && (op_len !=0)) { pcandidate->preference = *(op + 2); bfound = _TRUE; @@ -894,28 +967,33 @@ static u8 rtw_wnm_nb_elem_parsing( RTW_WNM_INFO("WNM: preference check bssid("MAC_FMT ") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d)," " phy_type(0x%02X), preference(0x%02X)\n", - MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, - pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, - pcandidate->nb_rpt.phy_type, pcandidate->preference); + MAC_ARG(pcandidate->nb_rpt.bssid), + pcandidate->nb_rpt.bss_info, + pcandidate->nb_rpt.reg_class, + pcandidate->nb_rpt.ch_num, + pcandidate->nb_rpt.phy_type, + pcandidate->preference); } else { - if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE) + if (_rtw_memcmp(&pnb->nb_rpt[i], pie, + sizeof(struct nb_rpt_hdr)) == _FALSE) *nb_rpt_is_same = _FALSE; - _rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)); + _rtw_memcpy(&pnb->nb_rpt[i], pie, + sizeof(struct nb_rpt_hdr)); } - nb_rpt_entries++; - } + nb_rpt_entries++; + } - if (from_btm) - pnb->preference_en = (bfound)?_TRUE:_FALSE; + if (from_btm) + pnb->preference_en = (bfound)?_TRUE:_FALSE; *nb_rpt_num = nb_rpt_entries; return ret; -} +} /* selection sorting based on preference value * IN : nb_rpt_entries - candidate num * IN/OUT : pcandidates - candidate list - * return : TRUE - means pcandidates is updated. + * return : TRUE - means pcandidates is updated. */ static u8 rtw_wnm_candidates_sorting( u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates) @@ -939,17 +1017,21 @@ static u8 rtw_wnm_candidates_sorting( if (pos != i) { updated = _TRUE; - _rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant)); - _rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant)); - _rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant)); + _rtw_memcpy(&swap, (pcandidates+i), + sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+i), (pcandidates+pos), + sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+pos), &swap, + sizeof(struct wnm_btm_cant)); } - } + } return updated; -} +} static void rtw_wnm_nb_info_update( - u32 nb_rpt_entries, u8 from_btm, - struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, + u32 nb_rpt_entries, u8 from_btm, + struct roam_nb_info *pnb, + struct wnm_btm_cant *pcandidates, u8 *nb_rpt_is_same) { u8 is_found; @@ -967,27 +1049,31 @@ static void rtw_wnm_nb_info_update( if (_rtw_memcmp(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr)) == _FALSE) *nb_rpt_is_same = _FALSE; - _rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr)); + _rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, + sizeof(struct nb_rpt_hdr)); } RTW_WNM_INFO("WNM: bssid(" MAC_FMT - ") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n", - MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, - pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, + ") , bss_info(0x%04X), reg_class(0x%02X)," + " ch_num(%d), phy_type(0x%02X)\n", + MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, + pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, pnb->nb_rpt[i].phy_type); if (pnb->nb_rpt[i].ch_num == 0) continue; for (j=0; jnb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) { + if (pnb->nb_rpt[i].ch_num == + pnb->nb_rpt_ch_list[j].hw_value) { is_found = _TRUE; break; } } - + if (!is_found) { - pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num; + pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value =\ + pnb->nb_rpt[i].ch_num; pnb->nb_rpt_ch_list_num++; } } @@ -1010,14 +1096,16 @@ static void rtw_wnm_btm_candidate_select(_adapter *padapter) for (i = 0; i < pnb->last_nb_rpt_entries; i++) { if (ignore_currrent && (_rtw_memcmp(pnb->nb_rpt[i].bssid,\ - padapter->mlmepriv.cur_network.network.MacAddress, ETH_ALEN))) { - RTW_WNM_INFO("WNM : ignore candidate "MAC_FMT" for it's connected(%u)!\n", - MAC_ARG(pnb->nb_rpt[i].bssid), i); + padapter->mlmepriv.cur_network.network.MacAddress, + ETH_ALEN))) { + RTW_WNM_INFO("WNM : ignore candidate "MAC_FMT + " for it's connected(%u)!\n", + MAC_ARG(pnb->nb_rpt[i].bssid), i); continue; } - + pnetwork = rtw_find_network( - &(pmlmepriv->scanned_queue), + &(pmlmepriv->scanned_queue), pnb->nb_rpt[i].bssid); if (pnetwork) { @@ -1027,14 +1115,16 @@ static void rtw_wnm_btm_candidate_select(_adapter *padapter) } if (bfound) { - _rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN); - RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch:%u) rssi:%d\n" + _rtw_memcpy(pnb->roam_target_addr, + pnb->nb_rpt[i].bssid, ETH_ALEN); + RTW_INFO("WNM : select btm entry(%d) -" + " %s("MAC_FMT", ch:%u) rssi:%d\n" , i , pnetwork->network.Ssid.Ssid , MAC_ARG(pnetwork->network.MacAddress) , pnetwork->network.Configuration.DSConfig - , (int)pnetwork->network.Rssi); - } else + , (int)pnetwork->network.PhyInfo.rssi); + } else _rtw_memset(pnb->roam_target_addr,0, ETH_ALEN); } @@ -1045,54 +1135,287 @@ u32 rtw_wnm_btm_candidates_survey( struct wnm_btm_cant *pcandidate_list = NULL; u8 nb_rpt_is_same = _TRUE; u32 ret = _FAIL; - u32 nb_rpt_entries = 0; + u32 nb_rpt_entries = 0; if (from_btm) { u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM; pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen); - if (pcandidate_list == NULL) - goto exit; + if (pcandidate_list == NULL) + goto exit; } /*clean the status set last time*/ _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); pnb->nb_rpt_valid = _FALSE; if (!rtw_wnm_nb_elem_parsing( - pframe, elem_len, from_btm, + pframe, elem_len, from_btm, &nb_rpt_entries, &nb_rpt_is_same, pnb, pcandidate_list)) goto exit; if (nb_rpt_entries != 0) { - if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter))) - rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list); + if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter))) { + rtw_wnm_candidates_sorting( + nb_rpt_entries, pcandidate_list); + } rtw_wnm_nb_info_update( - nb_rpt_entries, from_btm, + nb_rpt_entries, from_btm, pnb, pcandidate_list, &nb_rpt_is_same); } - RTW_WNM_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n", - nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries); - if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries)) + RTW_WNM_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d," + " last_nb_rpt_entries = %d\n", + nb_rpt_is_same, nb_rpt_entries, + pnb->last_nb_rpt_entries); + if ((nb_rpt_is_same == _TRUE) && + (nb_rpt_entries == pnb->last_nb_rpt_entries)) { pnb->nb_rpt_is_same = _TRUE; - else { + } else { pnb->nb_rpt_is_same = _FALSE; pnb->last_nb_rpt_entries = nb_rpt_entries; } if ((from_btm) && (nb_rpt_entries != 0)) rtw_wnm_btm_candidate_select(padapter); - + pnb->nb_rpt_valid = _TRUE; ret = _SUCCESS; exit: - if (from_btm && pcandidate_list) - rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM); - + if (from_btm && pcandidate_list) { + rtw_mfree((u8 *)pcandidate_list, + sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM); + } + return ret; } +void rtw_wnm_process_btm_query(_adapter *padapter, u8* pframe, u32 frame_len) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct nb_rpt_hdr *pie; + u8 *ptr, *pend, *op; + u32 elem_len, subelem_len, op_len; + u32 i, nb_rpt_entries = 0; + if (!pframe || !frame_len) + return; + + /* no preferred bss transition candidate list include */ + if (wnm_btm_query_reason(pframe) != 0x13) + return; + + ptr = pframe + 4; + elem_len = frame_len - 4; + pend = ptr + elem_len; + subelem_len = (u32)*(ptr + 1); + + RTW_WNM_DUMP("BTM QUERY :", ptr, elem_len); + for (i = 0; i < RTW_MAX_NB_RPT_NUM; i++) { + if (((ptr + 7) > pend) || (elem_len < subelem_len)) + break; + if (*ptr != RTW_WLAN_ACTION_WNM_NB_RPT_ELEM) + break; + pie = (struct nb_rpt_hdr *)ptr; + op = rtw_get_ie((u8 *)(ptr+15), WNM_BTM_CAND_PREF_SUBEID, + &op_len, (subelem_len - 15)); + +#ifdef CONFIG_RTW_MBO +/* for debug only */ +#if 0 + if (rtw_mbo_wifi_logo_test(padapter) && + check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + struct mbo_attr_info *pmbo_attr = \ + &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser = \ + &(pmbo_attr->user_raw); + struct wnm_btm_cant *puser_cant; + u8 j = 0, idx = 0, found = _FALSE; + + for (j = 0; j < RTW_MAX_NB_RPT_NUM; j++) { + puser_cant = &puser->btm_cants[j]; + if (_rtw_memcmp(pie->bssid, + puser_cant->nb_rpt.bssid, ETH_ALEN)) { + puser_cant->nb_rpt.bss_info = \ + pie->bss_info; + puser_cant->nb_rpt.reg_class = \ + pie->reg_class; + puser_cant->nb_rpt.ch_num = \ + pie->ch_num; + puser_cant->nb_rpt.phy_type = \ + pie->phy_type; + puser_cant->preference = \ + *(op + 2); + idx = j; + found = _TRUE; + break; + } + } + + if (!found) { + if (puser->candidate_cnt >= RTW_MAX_NB_RPT_NUM) + puser->candidate_cnt = 0; + puser_cant = \ + &puser->btm_cants[puser->candidate_cnt]; + puser_cant->nb_rpt.id = \ + RTW_WLAN_ACTION_WNM_NB_RPT_ELEM; + puser_cant->nb_rpt.len = 0x10; + _rtw_memcpy(puser_cant->nb_rpt.bssid, + pie->bssid, ETH_ALEN); + puser_cant->nb_rpt.bss_info = \ + pie->bss_info; + puser_cant->nb_rpt.reg_class = \ + pie->reg_class; + puser_cant->nb_rpt.ch_num = \ + pie->ch_num; + puser_cant->nb_rpt.phy_type = \ + pie->phy_type; + puser_cant->preference = \ + *(op + 2); + puser->candidate_cnt++; + } + + RTW_WNM_INFO("%s: idx=%u, bssid("MAC_FMT")," + " bss_info(0x%04X), reg_class(0x%02X)," + " ch(%d), phy_type(0x%02X), preference(0x%02X)\n", + __func__, (found)?idx:puser->candidate_cnt, + MAC_ARG(puser_cant->nb_rpt.bssid), + puser_cant->nb_rpt.bss_info, + puser_cant->nb_rpt.reg_class, + puser_cant->nb_rpt.ch_num, + puser_cant->nb_rpt.phy_type, + puser_cant->preference); + } +#endif +#endif /* end of CONFIG_RTW_MBO */ + + ptr = (u8 *)(ptr + subelem_len + 2); + elem_len -= (subelem_len +2); + subelem_len = *(ptr+1); + } /* end of for-loop RTW_MAX_NB_RPT_NUM */ + +} + +static u8 *rtw_wnm_non_pref_ch_attr_get(u8 *pie, u32 *plen, u32 limit) +{ + const u8 *p = pie; + u32 tmp, i; + + if (limit <= 1) + return NULL; + + i = 0; + *plen = 0; + while (1) { + if ((*p == _VENDOR_SPECIFIC_IE_) && + (_rtw_memcmp(rtw_wnm_get_non_pref_ch_oui(p), + wnm_non_pref_ch_oui, 4))) { + *plen = *(p + 1); + return (u8 *)p; + } else { + tmp = *(p + 1); + p += (tmp + 2); + i += (tmp + 2); + } + + if (i >= limit) + break; + } + + return NULL; +} + +void rtw_wnm_process_notification_req( + _adapter *padapter, u8 *pframe, u32 frame_len) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#ifdef CONFIG_RTW_MBO + struct mbo_attr_info *pmbo_attr = &(pmlmepriv->mbo_attr); + struct mbo_user_btm_req_pkt *puser_raw = &(pmbo_attr->user_raw); +#endif + struct wnm_btm_cant *pcant = NULL; + u8 dialog, type; + u8 *psubie; + u8 *ptr = NULL; + u32 left_len, subie_len; + + if (!pframe || (frame_len < 5)) + return; + + /* RTW_WNM_DUMP("notify-req :", pframe, frame_len); */ + dialog = *(pframe + 2); + type = *(pframe + 3); + + if (type != WLAN_EID_VENDOR_SPECIFIC) + return; + + ptr = (pframe + 4); + left_len = (frame_len - 4); + + while((psubie = rtw_wnm_non_pref_ch_attr_get( + ptr, &subie_len, left_len)) != NULL) { + + /* RTW_WNM_DUMP("notify-req subie :", (psubie + 2), subie_len); */ + + ptr += (subie_len + 2); + left_len -= (subie_len + 2); + +#ifdef CONFIG_RTW_MBO + if (rtw_mbo_wifi_spec_test(padapter) && \ + (subie_len > 7)) { + + u8 *pload = NULL, *pclass = NULL; + u8 ch_nums = 0; + u8 non_pref_ch = 0; + u8 ch_op_pref = 1, reason = 0; + u32 i, j; + + /* nums = sublen - oui_len - + (class_len - op_len - reason_len) */ + ch_nums = subie_len - 4 - 3; + if (ch_nums >= RTW_MBO_MAX_CH_LIST_NUM) + ch_nums = RTW_MBO_MAX_CH_LIST_NUM; + + /* skip sudid, len, oui */ + pclass = (psubie + 6); + ch_op_pref = *(pclass + ch_nums + 1); + reason = *(pclass + ch_nums + 2); + RTW_WNM_INFO("%s : class=0x%02x, operating=0x%02x, " + "reason=0x%02x\n", __func__, *pclass, + ch_op_pref, reason); + + for (i = 0; i < ch_nums; i++) { + non_pref_ch = *(pclass + 1 + i); + RTW_WNM_INFO("%s : non-pref ch %u " + "found in notify-req operating 0x%02x\n", + __func__, non_pref_ch, ch_op_pref); + + for (j = 0; j < RTW_MAX_NB_RPT_NUM; j++) { + pcant = &puser_raw->btm_cants[j]; + if (pcant->nb_rpt.ch_num == non_pref_ch) { + if (ch_op_pref == 0) { + RTW_WNM_INFO("%s : reset " + "preference(%u) for non-preference ch\n", + __func__, pcant->preference); + pcant->preference = 0; + } else { + if (!pcant->preference) + pcant->preference = 64; + } + } + + } /* end of for loop RTW_MAX_NB_RPT_NUM */ + + } /* end of for loop ch_nums*/ + + } +#endif /* end of CONFIG_RTW_MB*/ + + } /* end of while loop */ + + rtw_wnm_issue_action(padapter, + RTW_WLAN_ACTION_WNM_NOTIF_RSP, 0, dialog); + +} #endif /*defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */ diff --git a/core/rtw_wow.c b/core/rtw_wow.c new file mode 100644 index 0000000..1b77ea8 --- /dev/null +++ b/core/rtw_wow.c @@ -0,0 +1,1031 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_WOW_C_ + +#include + +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) + #include + #define ETH_TYPE_OFFSET 12 + #define PROTOCOL_OFFSET 23 + #define IP_OFFSET 30 + #define IPv6_OFFSET 38 + #define IPv6_PROTOCOL_OFFSET 20 +#endif + +#ifdef CONFIG_WOWLAN + +void rtw_init_wow(_adapter *padapter) +{ + struct registry_priv *registry_par = &padapter->registrypriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct wow_priv *wowpriv = adapter_to_wowlan(padapter); + +#ifdef CONFIG_GPIO_WAKEUP + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + void *phl = GET_PHL_INFO(dvobj); + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct rtw_wow_gpio_info *wow_gpio = &wowpriv->wow_gpio; + u8 toggle_pulse = DEV2HST_TOGGLE, gpio_time_unit = 1, gpio_pulse_count = 3, gpio_pulse_period = 10, gpio_pulse_dura = 5; + u8 gpio_pulse_en_a = 0, customer_id = 0, gpio_duration_unit_a = 0, gpio_pulse_count_a = 0, gpio_duration_a = 0, special_reason_a = 0; +#endif + +#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + pwrctrlpriv->early_suspend.suspend = NULL; + rtw_register_early_suspend(pwrctrlpriv); +#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ + pwrctrlpriv->wowlan_mode = _FALSE; + pwrctrlpriv->wowlan_ap_mode = _FALSE; + pwrctrlpriv->wowlan_p2p_mode = _FALSE; + pwrctrlpriv->wowlan_in_resume = _FALSE; + pwrctrlpriv->wowlan_last_wake_reason = 0; + +#ifdef CONFIG_GPIO_WAKEUP +#ifdef ROKU_PRIVATE + gpio_pulse_en_a = DEV2HST_PULSE; + customer_id = 0x3f; + gpio_duration_unit_a = 1; + gpio_pulse_count_a = 1; + gpio_duration_a = 5; + special_reason_a = 0x21; +#endif /* ROKU_PRIVATE */ + /*default low active*/ + wow_gpio->gpio_active = HIGH_ACTIVE_DEV2HST; + pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV; + wow_gpio->dev2hst_gpio = WAKEUP_GPIO_IDX; + wow_gpio->toggle_pulse = toggle_pulse; + wow_gpio->gpio_time_unit = gpio_time_unit; + wow_gpio->gpio_pulse_dura = gpio_pulse_dura; + wow_gpio->gpio_pulse_period = gpio_pulse_period; + wow_gpio->gpio_pulse_count = gpio_pulse_count; + + wow_gpio->customer_id = customer_id; + wow_gpio->gpio_pulse_en_a = gpio_pulse_en_a; + wow_gpio->gpio_duration_unit_a = gpio_duration_unit_a; + wow_gpio->gpio_duration_a = gpio_duration_a; + wow_gpio->special_reason_a = special_reason_a; + wow_gpio->gpio_pulse_count_a = gpio_pulse_count_a; + +#ifdef CONFIG_RTW_ONE_PIN_GPIO + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_INPUT; + status = rtw_phl_cfg_wow_set_sw_gpio_mode(phl, wow_gpio); +#else + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_OUTPUT_OD; + #else + wow_gpio->dev2hst_gpio_mode = RTW_AX_SW_IO_MODE_OUTPUT_PP; + #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ + /* switch GPIO to open-drain or push-pull */ + status = rtw_phl_cfg_wow_set_sw_gpio_mode(phl, wow_gpio); + wow_gpio->dev2hst_high = wow_gpio->gpio_active == 0 ? 1 : 0; + status = rtw_phl_cfg_wow_sw_gpio_ctrl(phl, wow_gpio); + RTW_INFO("%s: set GPIO_%d %d as default. status=%d\n", + __func__, WAKEUP_GPIO_IDX, wow_gpio->dev2hst_high, status); +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ +#endif /* CONFIG_GPIO_WAKEUP */ + +#ifdef CONFIG_WOWLAN +#ifdef CONFIG_LPS_1T1R +#define WOW_LPS_1T1R_FMT ", WOW_LPS_1T1R=%d" +#define WOW_LPS_1T1R_ARG , pwrctrlpriv->wowlan_lps_1t1r +#else +#define WOW_LPS_1T1R_FMT "" +#define WOW_LPS_1T1R_ARG +#endif + + pwrctrlpriv->wowlan_power_mgmt = padapter->registrypriv.wow_power_mgnt; + pwrctrlpriv->wowlan_lps_level = padapter->registrypriv.wow_lps_level; +#ifdef CONFIG_LPS_1T1R + pwrctrlpriv->wowlan_lps_1t1r = padapter->registrypriv.wow_lps_1t1r; +#endif + + RTW_INFO("%s: WOW_LPS_mode=%d, WOW_LPS_level=%d"WOW_LPS_1T1R_FMT"\n", + __func__, pwrctrlpriv->wowlan_power_mgmt, pwrctrlpriv->wowlan_lps_level + WOW_LPS_1T1R_ARG + ); + + if (!(registry_par->wakeup_event & BIT(3))) + rtw_wow_pattern_clean(padapter, RTW_CUSTOMIZED_PATTERN); + + rtw_wow_pattern_clean(padapter, RTW_DEFAULT_PATTERN); + +#ifdef CONFIG_PNO_SUPPORT + pwrctrlpriv->pno_inited = _FALSE; + pwrctrlpriv->pnlo_info = NULL; + pwrctrlpriv->pscan_info = NULL; + pwrctrlpriv->pno_ssid_list = NULL; +#endif /* CONFIG_PNO_SUPPORT */ + _rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex); + + pwrctrlpriv->wowlan_aoac_rpt_loc = 0; +#endif /* CONFIG_WOWLAN */ + +} + +void rtw_free_wow(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); +#ifdef CONFIG_PNO_SUPPORT + if (pwrctrlpriv->pnlo_info != NULL) + printk("****** pnlo_info memory leak********\n"); + + if (pwrctrlpriv->pscan_info != NULL) + printk("****** pscan_info memory leak********\n"); + + if (pwrctrlpriv->pno_ssid_list != NULL) + printk("****** pno_ssid_list memory leak********\n"); +#endif + _rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex); + +#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + rtw_unregister_early_suspend(pwrctrlpriv); +#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ +} + +void rtw_wowlan_set_pattern_cast_type(_adapter *adapter, struct rtw_wowcam_upd_info *wowcam_info) +{ + if (is_broadcast_mac_addr(wowcam_info->ptrn)) + wowcam_info->bc = 1; + else if (is_multicast_mac_addr(wowcam_info->ptrn)) + wowcam_info->mc = 1; + else if (!memcmp(wowcam_info->ptrn, adapter_mac_addr(adapter), ETH_ALEN)) + wowcam_info->uc = 1; +} + +inline bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct wow_ctl_t *wow_ctl = &dvobj->wow_ctl; + + if (wow_ctl->wow_cap & cap) + return _TRUE; + return _FALSE; +} +bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, + int *pattern_len, char *bit_mask) +{ + char *cp = NULL; + size_t len = 0; + int pos = 0, mask_pos = 0, res = 0; + u8 member[2] = {0}; + + /* To get the pattern string after "=", when we use : + * iwpriv wlanX pattern=XX:XX:..:XX + */ + cp = strchr(input, '='); + if (cp) { + *cp = 0; + cp++; + input = cp; + } + + /* To take off the newline character '\n'(0x0a) at the end of pattern string, + * when we use echo xxxx > /proc/xxxx + */ + cp = strchr(input, '\n'); + if (cp) + *cp = 0; + + while (input) { + cp = strsep((char **)(&input), ":"); + + if (bit_mask && (strcmp(cp, "-") == 0 || + strcmp(cp, "xx") == 0 || + strcmp(cp, "--") == 0)) { + /* skip this byte and leave mask bit unset */ + } else { + u8 hex; + + if (strlen(cp) != 2) { + RTW_ERR("%s:[ERROR] hex len != 2, input=[%s]\n", + __func__, cp); + goto error; + } + + if (hexstr2bin(cp, &hex, 1) < 0) { + RTW_ERR("%s:[ERROR] pattern is invalid, input=[%s]\n", + __func__, cp); + goto error; + } + + pattern[pos] = hex; + mask_pos = pos / 8; + if (bit_mask) + bit_mask[mask_pos] |= 1 << (pos % 8); + } + + pos++; + } + + (*pattern_len) = pos; + + return _TRUE; +error: + return _FALSE; +} + +u8 rtw_wow_pattern_set(_adapter *adapter, struct rtw_wowcam_upd_info *wowcam_info, + enum pattern_type set_type) +{ + struct wow_priv *wowpriv = adapter_to_wowlan(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + void *phl = GET_PHL_INFO(dvobj); + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + u8 cam_idx = MAX_WKFM_CAM_NUM; + + rtw_wowlan_set_pattern_cast_type(adapter, wowcam_info); + status = rtw_phl_add_wow_ptrn_info(phl, wowcam_info, &cam_idx); + if (status != RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("Add wow pattern fail(%d)\n", status); + return _FAIL; + } + + wowpriv->wow_ptrn_valid[cam_idx] = set_type; + + RTW_INFO("wowcam_id: %d, type: %d\n", cam_idx, set_type); + + return _SUCCESS; +} + +void rtw_wow_pattern_clean(_adapter *adapter, enum pattern_type clean_type) +{ + struct wow_priv *wowpriv = adapter_to_wowlan(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + void *phl = GET_PHL_INFO(dvobj); + u8 cam_idx; + + for (cam_idx = 0; cam_idx < MAX_WKFM_CAM_NUM; cam_idx++) { + if (wowpriv->wow_ptrn_valid[cam_idx] == clean_type) { + rtw_phl_remove_wow_ptrn_info(phl, cam_idx); + wowpriv->wow_ptrn_valid[cam_idx] = RTW_INVALID_PATTERN; + } + } +} + +void rtw_set_default_pattern(_adapter *adapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct rtw_wowcam_upd_info wowcam_info = {0}; + u8 index = 0; + u8 multicast_addr[3] = {0x01, 0x00, 0x5e}; + u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a}; + + u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03}; + u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f}; + u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03}; + + u8 ip_protocol[3] = {0x08, 0x00, 0x45}; + u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60}; + + u8 *target = NULL; + + /*TCP/ICMP unicast*/ + for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { + _rtw_memset((void *)&wowcam_info, 0, sizeof(wowcam_info)); + + switch (index) { + case 0: + target = wowcam_info.ptrn; + _rtw_memcpy(target, adapter_mac_addr(adapter), ETH_ALEN); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + + /* TCP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x06, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + + _rtw_memcpy(target, pmlmeinfo->ip_addr, RTW_IP_ADDR_LEN); + + _rtw_memcpy(wowcam_info.mask, + &unicast_mask, sizeof(unicast_mask)); + + wowcam_info.ptrn_len = IP_OFFSET + RTW_IP_ADDR_LEN; + + rtw_wow_pattern_set(adapter, &wowcam_info, RTW_DEFAULT_PATTERN); + + break; + case 1: + target = wowcam_info.ptrn; + _rtw_memcpy(target, adapter_mac_addr(adapter), ETH_ALEN); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + + /* ICMP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x01, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip_addr, RTW_IP_ADDR_LEN); + + _rtw_memcpy(wowcam_info.mask, + &unicast_mask, sizeof(unicast_mask)); + + wowcam_info.ptrn_len = IP_OFFSET + RTW_IP_ADDR_LEN; + + rtw_wow_pattern_set(adapter, &wowcam_info, RTW_DEFAULT_PATTERN); + + break; +#ifdef CONFIG_IPV6 + case 2: + if (pwrpriv->wowlan_ns_offload_en == _TRUE) { + target = wowcam_info.ptrn; + target += ETH_TYPE_OFFSET; + + _rtw_memcpy(target, &ipv6_protocol, + sizeof(ipv6_protocol)); + + /* ICMPv6 */ + target += (IPv6_PROTOCOL_OFFSET - + ETH_TYPE_OFFSET); + _rtw_memset(target, 0x3a, 1); + + target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip6_addr, + RTW_IPv6_ADDR_LEN); + + _rtw_memcpy(wowcam_info.mask, + &icmpv6_mask, sizeof(icmpv6_mask)); + + wowcam_info.ptrn_len = IPv6_OFFSET + RTW_IPv6_ADDR_LEN; + + rtw_wow_pattern_set(adapter, &wowcam_info, + RTW_DEFAULT_PATTERN); + } + break; +#endif /*CONFIG_IPV6*/ + case 3: + target = wowcam_info.ptrn; + _rtw_memcpy(target, &multicast_addr, sizeof(multicast_addr)); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + + /* UDP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x11, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, &multicast_ip, sizeof(multicast_ip)); + + _rtw_memcpy(wowcam_info.mask, + &multicast_mask, sizeof(multicast_mask)); + + wowcam_info.ptrn_len = IP_OFFSET + sizeof(multicast_ip); + + rtw_wow_pattern_set(adapter, &wowcam_info, RTW_DEFAULT_PATTERN); + + break; + default: + break; + } + } + + return; +} + +void rtw_dump_priv_pattern(_adapter *adapter, u8 idx) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + char str_1[128]; + char *p_str; + u8 val8 = 0; + int i = 0, j = 0, len = 0, max_len = 0; + + RTW_INFO("=========[%d]========\n", idx); + + RTW_INFO(">>>priv_pattern_content:\n"); + p_str = str_1; + max_len = sizeof(str_1); + for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { + _rtw_memset(p_str, 0, max_len); + len = 0; + for (j = 0 ; j < 8 ; j++) { + val8 = pwrctl->patterns[idx].content[i * 8 + j]; + len += snprintf(p_str + len, max_len - len, + "%02x ", val8); + } + RTW_INFO("%s\n", p_str); + } + + RTW_INFO(">>>priv_pattern_mask:\n"); + for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { + _rtw_memset(p_str, 0, max_len); + len = 0; + for (j = 0 ; j < 8 ; j++) { + val8 = pwrctl->patterns[idx].mask[i * 8 + j]; + len += snprintf(p_str + len, max_len - len, + "%02x ", val8); + } + RTW_INFO("%s\n", p_str); + } + + RTW_INFO(">>>priv_pattern_len:\n"); + RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len); +} + +void rtw_wow_pattern_sw_dump(_adapter *adapter) +{ + int i; + + RTW_INFO("********[RTK priv-patterns]*********\n"); + for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) + rtw_dump_priv_pattern(adapter, i); +} + +void rtw_get_sec_iv(_adapter *padapter, u8 *pcur_dot11txpn, u8 *StaAddr) +{ + struct sta_info *psta; + struct security_priv *psecpriv = &padapter->securitypriv; + + _rtw_memset(pcur_dot11txpn, 0, 8); + if (NULL == StaAddr) + return; + psta = rtw_get_stainfo(&padapter->stapriv, StaAddr); + RTW_INFO("%s(): StaAddr: %02x %02x %02x %02x %02x %02x\n", + __func__, StaAddr[0], StaAddr[1], StaAddr[2], + StaAddr[3], StaAddr[4], StaAddr[5]); + + if (psta) { + if ((psecpriv->dot11PrivacyAlgrthm == _AES_) || + (psecpriv->dot11PrivacyAlgrthm == _CCMP_256_)) + AES_IV(pcur_dot11txpn, psta->dot11txpn, 0); + else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) + TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0); + else if ((psecpriv->dot11PrivacyAlgrthm == _GCMP_) || + (psecpriv->dot11PrivacyAlgrthm == _GCMP_256_)) + GCMP_IV(pcur_dot11txpn, psta->dot11txpn, 0); + } +} + +void rtw_construct_remote_control_info(_adapter *adapter, + struct rtw_remote_wake_ctrl_info *ctrl_info) +{ + struct security_priv *securitypriv = &adapter->securitypriv; + struct stainfo_rxcache *rxcache = NULL; + struct sta_info *sta = NULL; + u8 gtk_rx_iv[4][IV_LENGTH] = {0}; + u8 tid_id = 0; + u8 i = 0; + + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + + if (!sta) { + rtw_warn_on(1); + return; + } + + rxcache = &sta->sta_recvpriv.rxcache; + + rtw_get_sec_iv(adapter, ctrl_info->ptk_tx_iv, get_bssid(&adapter->mlmepriv)); + RTW_INFO("[wow] ptk_tx_iv = " IV_FMT "\n", IV_ARG(ctrl_info->ptk_tx_iv)); + + ctrl_info->valid_check = REMOTECTRL_INFO_VALID_CHECK; + ctrl_info->symbol_check_en |= REMOTECTRL_INFO_SYMBOL_CHK_PTK | + REMOTECTRL_INFO_SYMBOL_CHK_GTK; + + ctrl_info->gtk_key_idx = securitypriv->dot118021XGrpKeyid; + RTW_INFO("[wow] gtk_key_idx = %d\n", ctrl_info->gtk_key_idx); + + tid_id = rxcache->last_tid; + _rtw_memcpy(ctrl_info->ptk_rx_iv, rxcache->iv[tid_id], IV_LENGTH); + RTW_INFO("[wow] ptk_rx_iv = " IV_FMT "\n", IV_ARG(ctrl_info->ptk_rx_iv)); + + for (i = 0; i < 4; i++) { + rtw_pn_to_iv(securitypriv->iv_seq[i], gtk_rx_iv[i], i, + securitypriv->dot118021XGrpPrivacy); + RTW_INFO("[wow] gtk_rx_iv[%u] = " IV_FMT "\n", i, IV_ARG(gtk_rx_iv[i])); + } + _rtw_memcpy(ctrl_info->gtk_rx_iv_idx0, gtk_rx_iv[0], IV_LENGTH); + _rtw_memcpy(ctrl_info->gtk_rx_iv_idx1, gtk_rx_iv[1], IV_LENGTH); + _rtw_memcpy(ctrl_info->gtk_rx_iv_idx2, gtk_rx_iv[2], IV_LENGTH); + _rtw_memcpy(ctrl_info->gtk_rx_iv_idx3, gtk_rx_iv[3], IV_LENGTH); +} + +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + if (wow_en) { + pwrpriv->lps_level_bk = pwrpriv->lps_level; + pwrpriv->lps_level = pwrpriv->wowlan_lps_level; + #ifdef CONFIG_LPS_1T1R + pwrpriv->lps_1t1r_bk = pwrpriv->lps_1t1r; + pwrpriv->lps_1t1r = pwrpriv->wowlan_lps_1t1r; + #endif + } else { + pwrpriv->lps_level = pwrpriv->lps_level_bk; + #ifdef CONFIG_LPS_1T1R + pwrpriv->lps_1t1r = pwrpriv->lps_1t1r_bk; + #endif + } +} + +int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (mode < PM_PS_MODE_NUM) { + if (pwrctrlpriv->wowlan_power_mgmt != mode) + pwrctrlpriv->wowlan_power_mgmt = mode; + } else + ret = -EINVAL; + + return ret; +} +int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (level < LPS_LEVEL_MAX) + pwrctrlpriv->wowlan_lps_level = level; + else + ret = -EINVAL; + + return ret; +} +#ifdef CONFIG_LPS_1T1R +int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + en = en ? 1 : 0; + pwrctrlpriv->wowlan_lps_1t1r = en; + + return ret; +} +#endif /* CONFIG_LPS_1T1R */ + +#ifdef CONFIG_GTK_OL +void _update_aoac_rpt_phase_0(_adapter *adapter, struct rtw_aoac_report *aoac_info) +{ + struct security_priv *securitypriv = &adapter->securitypriv; + struct stainfo_rxcache *rxcache = NULL; + struct sta_info *sta = NULL; + u8 pn[8] = {0}; + u8 gtk_key_idx = 0; + u8 i = 0; + + /* handle ptk rx iv */ + /* This Rx IV has no effect, the driver does not drop unicast packets + * due to different PNs. (Refer to recv_ucast_pn_decache) + */ + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (sta) { + if (rtw_iv_to_pn(aoac_info->ptk_rx_iv, pn, NULL, + securitypriv->dot11PrivacyAlgrthm)) { + rxcache = &sta->sta_recvpriv.rxcache; + for (i = 0; i < TID_NUM; i++) + _rtw_memcpy(rxcache->iv[i], aoac_info->ptk_rx_iv, + IV_LENGTH); + sta->dot11rxpn.val = RTW_GET_LE64(pn); + RTW_INFO("[wow] ptk_rx_pn = " PN_FMT "\n", PN_ARG(pn)); + } + } + + /* handle gtk rx iv */ + gtk_key_idx = aoac_info->key_idx; + if (rtw_iv_to_pn(aoac_info->gtk_rx_iv[gtk_key_idx], pn, NULL, + securitypriv->dot118021XGrpPrivacy)) { + _rtw_memcpy(securitypriv->iv_seq[gtk_key_idx], pn, 8); + RTW_INFO("[wow] gtk_rx_pn[%u] = " PN_FMT "\n", gtk_key_idx, PN_ARG(pn)); + } +} + +void _update_aoac_rpt_phase_1(_adapter *adapter, struct rtw_aoac_report *aoac_info) +{ + struct security_priv *securitypriv = &adapter->securitypriv; + struct sta_info *sta = NULL; + u8 pn[8] = {0}; + u8 gtk_key_idx = 0; + u8 key_len = 0; + u8 i = 0; + + /* handle ptk tx iv */ + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (sta) { + if (rtw_iv_to_pn(aoac_info->ptk_tx_iv, pn, NULL, + securitypriv->dot11PrivacyAlgrthm)) { + sta->dot11txpn.val = RTW_GET_LE64(pn); + RTW_INFO("[wow] ptk_tx_pn = " PN_FMT "\n", PN_ARG(pn)); + } + } + + if (aoac_info->rekey_ok) { + /* update gtk key */ + gtk_key_idx = aoac_info->key_idx; + securitypriv->dot118021XGrpKeyid = gtk_key_idx; + + switch (securitypriv->dot118021XGrpPrivacy) { + case _TKIP_: + case _AES_: + case _GCMP_: + key_len = 16; + break; + case _GCMP_256_: + case _CCMP_256_: + key_len = 32; + break; + default: + key_len = 0; + } + + if (key_len) + _rtw_memcpy(securitypriv->dot118021XGrpKey[gtk_key_idx].skey, + aoac_info->gtk, key_len); + /* update tkip dot118021XGrptxmickey dot118021XGrprxmickey */ + if (securitypriv->dot118021XGrpPrivacy == _TKIP_) { + /* The order of the GTK Tx/Rx mic keys in the AOAC report is + * reversed compared to the GTK Tx/Rx mic keys provided by + * wpa_supplicant. + */ + _rtw_memcpy(securitypriv->dot118021XGrptxmickey[gtk_key_idx].skey, + &aoac_info->gtk[24], 8); + _rtw_memcpy(securitypriv->dot118021XGrprxmickey[gtk_key_idx].skey, + &aoac_info->gtk[16], 8); + } + rtw_set_key(adapter, securitypriv, gtk_key_idx, 1, _TRUE); + + /* update eapol replay_counter */ + _rtw_memcpy(sta->replay_ctr, aoac_info->eapol_key_replay_count, + RTW_REPLAY_CTR_LEN); + } else { + RTW_INFO("[wow] no rekey event\n"); + } + + for (i = 0; i < 4; i++) { + if (rtw_iv_to_pn(aoac_info->gtk_rx_iv[i], pn, NULL, + securitypriv->dot118021XGrpPrivacy)) { + _rtw_memcpy(securitypriv->iv_seq[i], pn, 8); + RTW_INFO("[wow] gtk_rx_pn[%u] = " PN_FMT "\n", i, PN_ARG(pn)); + } + } +} + +void rtw_update_gtk_ofld_info(void *drv_priv, struct rtw_aoac_report *aoac_info, + u8 aoac_report_get_ok, u8 rx_ready) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)drv_priv; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + + if (!rx_ready) + _update_aoac_rpt_phase_0(adapter, aoac_info); + else + _update_aoac_rpt_phase_1(adapter, aoac_info); +} +#endif /* CONFIG_GTK_OL */ +#endif /* CONFIG_WOWLAN */ + +#ifdef CONFIG_PNO_SUPPORT +#define CSCAN_TLV_TYPE_SSID_IE 'S' +#define CIPHER_IE "key_mgmt=" +#define CIPHER_NONE "NONE" +#define CIPHER_WPA_PSK "WPA-PSK" +#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X" +/* + * SSIDs list parsing from cscan tlv list + */ +int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, + int max, int *bytes_left) +{ + char *str; + + int idx = 0; + + if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) { + RTW_INFO("%s error paramters\n", __func__); + return -1; + } + + str = *list_str; + while (*bytes_left > 0) { + + if (str[0] != CSCAN_TLV_TYPE_SSID_IE) { + *list_str = str; + RTW_INFO("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]); + return idx; + } + + /* Get proper CSCAN_TLV_TYPE_SSID_IE */ + *bytes_left -= 1; + str += 1; + + if (str[0] == 0) { + /* Broadcast SSID */ + ssid[idx].SSID_len = 0; + _rtw_memset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN); + *bytes_left -= 1; + str += 1; + + RTW_INFO("BROADCAST SCAN left=%d\n", *bytes_left); + } else if (str[0] <= WLAN_SSID_MAXLEN) { + /* Get proper SSID size */ + ssid[idx].SSID_len = str[0]; + *bytes_left -= 1; + str += 1; + + /* Get SSID */ + if (ssid[idx].SSID_len > *bytes_left) { + RTW_INFO("%s out of memory range len=%d but left=%d\n", + __func__, ssid[idx].SSID_len, *bytes_left); + return -1; + } + + _rtw_memcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len); + + *bytes_left -= ssid[idx].SSID_len; + str += ssid[idx].SSID_len; + + RTW_INFO("%s :size=%d left=%d\n", + (char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left); + } else { + RTW_INFO("### SSID size more that %d\n", str[0]); + return -1; + } + + if (idx++ > max) { + RTW_INFO("%s number of SSIDs more that %d\n", __func__, idx); + return -1; + } + } + + *list_str = str; + return idx; +} + +int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str) +{ + + char *pch, *pnext, *pend; + u8 key_len = 0, index = 0; + + pch = list_str; + + if (nlo_info == NULL || list_str == NULL) { + RTW_INFO("%s error paramters\n", __func__); + return -1; + } + + while (strlen(pch) != 0) { + pnext = strstr(pch, "key_mgmt="); + if (pnext != NULL) { + pch = pnext + strlen(CIPHER_IE); + pend = strstr(pch, "}"); + if (strncmp(pch, CIPHER_NONE, + strlen(CIPHER_NONE)) == 0) + nlo_info->ssid_cipher_info[index] = 0x00; + else if (strncmp(pch, CIPHER_WPA_PSK, + strlen(CIPHER_WPA_PSK)) == 0) + nlo_info->ssid_cipher_info[index] = 0x66; + else if (strncmp(pch, CIPHER_WPA_EAP, + strlen(CIPHER_WPA_EAP)) == 0) + nlo_info->ssid_cipher_info[index] = 0x01; + index++; + pch = pend + 1; + } else + break; + } + return 0; +} + +int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, + int num, int pno_time, int pno_repeat, int pno_freq_expo_max) +{ + + int i = 0; + struct file *fp; + mm_segment_t fs; + loff_t pos = 0; + u8 *source = NULL; + long len = 0; + + RTW_INFO("+%s+\n", __func__); + + nlo_info->fast_scan_period = pno_time; + nlo_info->ssid_num = num & BIT_LEN_MASK_32(8); + nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8); + nlo_info->slow_scan_period = (pno_time * 2); + nlo_info->fast_scan_iterations = 5; + + if (nlo_info->hidden_ssid_num > 8) + nlo_info->hidden_ssid_num = 8; + + /* TODO: channel list and probe index is all empty. */ + for (i = 0 ; i < num ; i++) { + nlo_info->ssid_length[i] + = ssid[i].SSID_len; + } + + /* cipher array */ + fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY, 0644); + if (IS_ERR(fp)) { + RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n"); + RTW_INFO("Error, cipher array using default value.\n"); + return 0; + } + + len = i_size_read(fp->f_path.dentry->d_inode); + if (len < 0 || len > 2048) { + RTW_INFO("Error, file size is bigger than 2048.\n"); + RTW_INFO("Error, cipher array using default value.\n"); + return 0; + } + + fs = get_fs(); + set_fs(KERNEL_DS); + + source = rtw_zmalloc(2048); + + if (source != NULL) { + len = vfs_read(fp, source, len, &pos); + rtw_parse_cipher_list(nlo_info, source); + rtw_mfree(source, 2048); + } + + set_fs(fs); + filp_close(fp, NULL); + + RTW_INFO("-%s-\n", __func__); + return 0; +} + +int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list, + pno_ssid_t *ssid, u8 num) +{ + + int i = 0; + if (num > MAX_PNO_LIST_COUNT) + num = MAX_PNO_LIST_COUNT; + + for (i = 0 ; i < num ; i++) { + _rtw_memcpy(&pno_ssid_list->node[i].SSID, + ssid[i].SSID, ssid[i].SSID_len); + pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len; + } + return 0; +} + +int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid, + unsigned char ch, unsigned char ch_offset, unsigned short bw_mode) +{ + + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct pno_scan_info *scan_info = pwrctl->pscan_info; + u8 band = ch <= 14 ? BAND_ON_24G : BAND_ON_5G; + int i; + + scan_info->channel_num = MAX_SCAN_LIST_COUNT; + scan_info->orig_ch = ch; + scan_info->orig_bw = bw_mode; + scan_info->orig_40_offset = ch_offset; + + for (i = 0 ; i < scan_info->channel_num ; i++) { + if (i < 11) + scan_info->ssid_channel_info[i].active = 1; + else + scan_info->ssid_channel_info[i].active = 0; + + scan_info->ssid_channel_info[i].timeout = 100; + + scan_info->ssid_channel_info[i].tx_power = + phy_get_tx_power_index_ex(padapter, 0, CCK, MGN_1M, bw_mode, band, i + 1); + + scan_info->ssid_channel_info[i].channel = i + 1; + } + + RTW_INFO("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n", + __func__, scan_info->channel_num, scan_info->orig_ch, + scan_info->orig_bw, scan_info->orig_40_offset); + return 0; +} + +int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, + int pno_time, int pno_repeat, int pno_freq_expo_max) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + int ret = -1; + + if (num == 0) { + RTW_INFO("%s, nssid is zero, no need to setup pno ssid list\n", __func__); + return 0; + } + + if (pwrctl == NULL) { + RTW_INFO("%s, ERROR: pwrctl is NULL\n", __func__); + return -1; + } else { + pwrctl->pnlo_info = + (pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t)); + pwrctl->pno_ssid_list = + (pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t)); + pwrctl->pscan_info = + (pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t)); + } + + if (pwrctl->pnlo_info == NULL || + pwrctl->pscan_info == NULL || + pwrctl->pno_ssid_list == NULL) { + RTW_INFO("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__); + goto failing; + } + + pwrctl->wowlan_in_resume = _FALSE; + + pwrctl->pno_inited = _TRUE; + /* NLO Info */ + ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num, + pno_time, pno_repeat, pno_freq_expo_max); + + /* SSID Info */ + ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num); + + /* SCAN Info */ + ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->chandef.chan, + pmlmeext->chandef.offset, pmlmeext->chandef.bw); + + RTW_INFO("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n", + __func__, num, pno_time, pno_repeat, pno_freq_expo_max); + + return 0; + +failing: + if (pwrctl->pnlo_info) { + rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t)); + pwrctl->pnlo_info = NULL; + } + if (pwrctl->pno_ssid_list) { + rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t)); + pwrctl->pno_ssid_list = NULL; + } + if (pwrctl->pscan_info) { + rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t)); + pwrctl->pscan_info = NULL; + } + + return -1; +} + +#ifdef CONFIG_PNO_SET_DEBUG +void rtw_dev_pno_debug(struct net_device *net) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + int i = 0, j = 0; + + RTW_INFO("*******NLO_INFO********\n"); + RTW_INFO("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num); + RTW_INFO("fast_scan_iterations: %d\n", + pwrctl->pnlo_info->fast_scan_iterations); + RTW_INFO("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period); + RTW_INFO("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period); + + + + for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { + RTW_INFO("%d SSID (%s) length (%d) cipher(%x) channel(%d)\n", + i, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i], + pwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]); + } + + RTW_INFO("******SCAN_INFO******\n"); + RTW_INFO("ch_num: %d\n", pwrctl->pscan_info->channel_num); + RTW_INFO("orig_ch: %d\n", pwrctl->pscan_info->orig_ch); + RTW_INFO("orig bw: %d\n", pwrctl->pscan_info->orig_bw); + RTW_INFO("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset); + for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) { + RTW_INFO("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n", + i, pwrctl->pscan_info->ssid_channel_info[i].active, + pwrctl->pscan_info->ssid_channel_info[i].timeout, + pwrctl->pscan_info->ssid_channel_info[i].tx_power, + pwrctl->pscan_info->ssid_channel_info[i].channel); + } + RTW_INFO("*****************\n"); +} +#endif /* CONFIG_PNO_SET_DEBUG */ +#endif /* CONFIG_PNO_SUPPORT */ + diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c index 7718afb..8f21cd7 100644 --- a/core/rtw_xmit.c +++ b/core/rtw_xmit.c @@ -15,14 +15,10 @@ #define _RTW_XMIT_C_ #include -#include static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; -int openhd_tx_error_count=0; -int openhd_tx_packets_cunt=0; - static void _init_txservq(struct tx_servq *ptxservq) { _rtw_init_listhead(&ptxservq->tx_pending); @@ -46,9 +42,6 @@ void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) _init_txservq(&psta_xmitpriv->bk_q); _init_txservq(&psta_xmitpriv->vi_q); _init_txservq(&psta_xmitpriv->vo_q); -#ifdef CONFIG_RTW_MGMT_QUEUE - _init_txservq(&psta_xmitpriv->mgmt_q); -#endif _rtw_init_listhead(&psta_xmitpriv->legacy_dz); _rtw_init_listhead(&psta_xmitpriv->apsd); @@ -70,20 +63,129 @@ void rtw_free_xmit_block(_adapter *padapter) _rtw_spinlock_free(&dvobj->xmit_block_lock); } -s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) +#ifdef RTW_PHL_TX +u8 alloc_txring(_adapter *padapter) +{ + struct xmit_txreq_buf *ptxreq_buf = NULL; + u32 idx, alloc_sz = 0, alloc_sz_txreq = 0; + u8 res = _SUCCESS; + + u32 offset_head = (sizeof(struct rtw_xmit_req) * RTW_MAX_FRAG_NUM); + u32 offset_tail = offset_head + (SZ_HEAD_BUF * RTW_MAX_FRAG_NUM); + u32 offset_list = offset_tail + (SZ_TAIL_BUF * RTW_MAX_FRAG_NUM); + + PHLTX_ENTER; + + alloc_sz = (SZ_TX_RING * RTW_MAX_FRAG_NUM); + alloc_sz_txreq = MAX_TX_RING_NUM * (sizeof(struct xmit_txreq_buf)); + + RTW_INFO("eric-tx [%s] alloc_sz = %d, alloc_sz_txreq = %d\n", __FUNCTION__, alloc_sz, alloc_sz_txreq); + + padapter->pxmit_txreq_buf = rtw_vmalloc(alloc_sz_txreq); + ptxreq_buf = (struct xmit_txreq_buf *)padapter->pxmit_txreq_buf; + + _rtw_init_queue(&padapter->free_txreq_queue); + + for (idx = 0; idx < MAX_TX_RING_NUM; idx++) { + + padapter->tx_pool_ring[idx] = rtw_zmalloc(alloc_sz); + if (!padapter->tx_pool_ring[idx]) { + RTW_ERR("[core] alloc txring fail, plz check.\n"); + res = _FAIL; + break; + } + _rtw_init_listhead(&ptxreq_buf->list); + ptxreq_buf->txreq = padapter->tx_pool_ring[idx]; + ptxreq_buf->head = padapter->tx_pool_ring[idx] + offset_head; + ptxreq_buf->tail = padapter->tx_pool_ring[idx] + offset_tail; + ptxreq_buf->pkt_list = padapter->tx_pool_ring[idx] + offset_list; + + #ifdef USE_PREV_WLHDR_BUF /* CONFIG_CORE_TXSC */ + ptxreq_buf->macid = 0xff; + ptxreq_buf->txsc_id = 0xff; + #endif + + rtw_list_insert_tail(&(ptxreq_buf->list), &(padapter->free_txreq_queue.queue)); + + ptxreq_buf++; + } + + padapter->free_txreq_cnt = MAX_TX_RING_NUM; + + return res; +} + +void free_txring(_adapter *padapter) +{ + u32 idx, alloc_sz = 0, alloc_sz_txreq = 0; +#ifdef CONFIG_CORE_TXSC + struct rtw_xmit_req *txreq = NULL; + struct xmit_txreq_buf *txreq_buf = NULL; + u8 j; +#endif + + PHLTX_ENTER; + + alloc_sz = (SZ_TX_RING * RTW_MAX_FRAG_NUM); + alloc_sz_txreq = MAX_TX_RING_NUM * (sizeof(struct xmit_txreq_buf)); + + RTW_INFO("eric-tx [%s] alloc_sz = %d, alloc_sz_txreq = %d\n", __func__, alloc_sz, alloc_sz_txreq); + + for (idx = 0; idx < MAX_TX_RING_NUM; idx++) { + if (padapter->tx_pool_ring[idx]) { +#ifdef CONFIG_CORE_TXSC + txreq = (struct rtw_xmit_req *)padapter->tx_pool_ring[idx]; + if (txreq->treq_type == RTW_PHL_TREQ_TYPE_CORE_TXSC) { + txreq_buf = (struct xmit_txreq_buf *)txreq->os_priv; + if (txreq_buf) { + /* CONFGI_TXSC_AMSDU */ + for (j = 0; j < txreq_buf->pkt_cnt; j++) { + if (txreq_buf->pkt[j]) + rtw_os_pkt_complete(padapter, (void *)txreq_buf->pkt[j]); + } + } + } +#endif + rtw_mfree(padapter->tx_pool_ring[idx], alloc_sz); + } + } + + _rtw_spinlock_free(&padapter->free_txreq_queue.lock); + rtw_vmfree(padapter->pxmit_txreq_buf, alloc_sz_txreq); +} + +#endif + + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) { int i; + #if 0 /*CONFIG_CORE_XMITBUF*/ struct xmit_buf *pxmitbuf; + #endif struct xmit_frame *pxframe; - sint res = _SUCCESS; + sint res = _SUCCESS; + /* MGT_TXREQ_MGT */ + u8 *txreq = NULL, *pkt_list = NULL; + + #if 0 /*CONFIG_CORE_XMITBUF*/ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + u8 xmitbuf_nr = GET_HAL_XMITBUF_NR(dvobj); + u16 xmitbuf_sz = GET_HAL_XMITBUF_SZ(dvobj); + u8 xmitbuf_ext_nr = GET_HAL_XMITBUF_EXT_NR(dvobj); + u16 xmitbuf_ext_sz = GET_HAL_XMITBUF_EXT_SZ(dvobj); + #endif /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ /* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */ _rtw_spinlock_init(&pxmitpriv->lock); _rtw_spinlock_init(&pxmitpriv->lock_sctx); + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ _rtw_init_sema(&pxmitpriv->xmit_sema, 0); + #endif /* Please insert all the queue initializaiton using _rtw_init_queue below @@ -98,15 +200,12 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) _rtw_init_queue(&pxmitpriv->bk_pending); _rtw_init_queue(&pxmitpriv->vi_pending); _rtw_init_queue(&pxmitpriv->vo_pending); - _rtw_init_queue(&pxmitpriv->mgmt_pending); + _rtw_init_queue(&pxmitpriv->bm_pending); /* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */ /* _rtw_init_queue(&pxmitpriv->apsd_queue); */ _rtw_init_queue(&pxmitpriv->free_xmit_queue); -#ifdef CONFIG_LAYER2_ROAMING - _rtw_init_queue(&pxmitpriv->rpkt_queue); -#endif /* Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, @@ -135,8 +234,13 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxframe->pkt = NULL; + #if 0 /*CONFIG_CORE_XMITBUF*/ pxframe->buf_addr = NULL; pxframe->pxmitbuf = NULL; + #else + /*alloc buf_addr*/ + /*rtw_os_xmit_resource_alloc(padapter, pxframe);*/ + #endif rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue)); @@ -147,12 +251,12 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->frag_len = MAX_FRAG_THRESHOLD; - + #if 0 /*CONFIG_CORE_XMITBUF*/ /* init xmit_buf */ _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue); _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue); - pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(xmitbuf_nr * sizeof(struct xmit_buf) + 4); if (pxmitpriv->pallocated_xmitbuf == NULL) { res = _FAIL; @@ -165,7 +269,7 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; - for (i = 0; i < NR_XMITBUFF; i++) { + for (i = 0; i < xmitbuf_nr; i++) { _rtw_init_listhead(&pxmitbuf->list); pxmitbuf->priv_data = NULL; @@ -173,17 +277,19 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitbuf->buf_tag = XMITBUF_DATA; /* Tx buf allocation may fail sometimes, so sleep and retry. */ - res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, + (xmitbuf_sz + SZ_ALIGN_XMITFRAME_EXT), _TRUE); if (res == _FAIL) { rtw_msleep_os(10); - res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, + (xmitbuf_sz + SZ_ALIGN_XMITFRAME_EXT), _TRUE); if (res == _FAIL) goto exit; } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) pxmitbuf->phead = pxmitbuf->pbuf; - pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ; + pxmitbuf->pend = pxmitbuf->pbuf + xmitbuf_sz; pxmitbuf->len = 0; pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; #endif @@ -199,12 +305,15 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) } - pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF; - + pxmitpriv->free_xmitbuf_cnt = xmitbuf_nr; + #endif /* init xframe_ext queue, the same count as extbuf */ _rtw_init_queue(&pxmitpriv->free_xframe_ext_queue); +#ifdef CONFIG_LAYER2_ROAMING + _rtw_init_queue(&pxmitpriv->rpkt_queue); +#endif - pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMITFRAME_EXT * sizeof(struct xmit_frame) + 4); if (pxmitpriv->xframe_ext_alloc_addr == NULL) { pxmitpriv->xframe_ext = NULL; @@ -214,7 +323,18 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4); pxframe = (struct xmit_frame *)pxmitpriv->xframe_ext; - for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + /* MGT_TXREQ_QMGT */ + pxmitpriv->xframe_ext_txreq_alloc_addr = rtw_zmalloc(NR_XMITFRAME_EXT * SZ_MGT_RING); + if (pxmitpriv->xframe_ext_txreq_alloc_addr == NULL) { + pxmitpriv->xframe_ext_txreq = NULL; + res = _FAIL; + goto exit; + } + pxmitpriv->xframe_ext_txreq = pxmitpriv->xframe_ext_txreq_alloc_addr; + txreq = pxmitpriv->xframe_ext_txreq; + pkt_list = pxmitpriv->xframe_ext_txreq + sizeof(struct rtw_xmit_req); + + for (i = 0; i < NR_XMITFRAME_EXT; i++) { _rtw_init_listhead(&(pxframe->list)); pxframe->padapter = padapter; @@ -222,21 +342,34 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxframe->pkt = NULL; + #if 0 /*CONFIG_CORE_XMITBUF*/ pxframe->buf_addr = NULL; pxframe->pxmitbuf = NULL; + #else + /*alloc buf_addr*/ + rtw_os_xmit_resource_alloc(padapter, pxframe); + #endif pxframe->ext_tag = 1; + /* MGT_TXREQ_QMGT */ + pxframe->phl_txreq = (struct rtw_xmit_req *)txreq; + pxframe->phl_txreq->pkt_list = pkt_list; + rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue)); pxframe++; + /* MGT_TXREQ_QMGT */ + txreq += SZ_MGT_RING; + pkt_list += SZ_MGT_RING; } - pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF; + pxmitpriv->free_xframe_ext_cnt = NR_XMITFRAME_EXT; +#if 0 /*CONFIG_CORE_XMITBUF*/ /* Init xmit extension buff */ _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); - pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(xmitbuf_ext_nr * sizeof(struct xmit_buf) + 4); if (pxmitpriv->pallocated_xmit_extbuf == NULL) { res = _FAIL; @@ -247,14 +380,15 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; - for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + for (i = 0; i < xmitbuf_ext_nr; i++) { _rtw_init_listhead(&pxmitbuf->list); pxmitbuf->priv_data = NULL; pxmitbuf->padapter = padapter; pxmitbuf->buf_tag = XMITBUF_MGNT; - res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, + xmitbuf_ext_sz + SZ_ALIGN_XMITFRAME_EXT, _TRUE); if (res == _FAIL) { res = _FAIL; goto exit; @@ -262,7 +396,7 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) pxmitbuf->phead = pxmitbuf->pbuf; - pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ; + pxmitbuf->pend = pxmitbuf->pbuf + xmitbuf_ext_sz; pxmitbuf->len = 0; pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; #endif @@ -275,8 +409,9 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) } - pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF; + pxmitpriv->free_xmit_extbuf_cnt = xmitbuf_ext_nr; + /*GEORGIA_TODO_FIXIT_IC_GEN_DEPENDENCE*/ for (i = 0; i < CMDBUF_MAX; i++) { pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i]; if (pxmitbuf) { @@ -286,7 +421,8 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitbuf->padapter = padapter; pxmitbuf->buf_tag = XMITBUF_CMD; - res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, + MAX_CMDBUF_SZ + SZ_ALIGN_XMITFRAME_EXT, _TRUE); if (res == _FAIL) { res = _FAIL; goto exit; @@ -298,10 +434,10 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitbuf->len = 0; pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; #endif - pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ; + pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + SZ_ALIGN_XMITFRAME_EXT; } } - +#endif rtw_alloc_hwxmits(padapter); rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); @@ -328,57 +464,75 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) #endif #ifdef CONFIG_TX_AMSDU - rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter, + rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), rtw_amsdu_vo_timeout_handler, padapter); pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET; - rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter, + rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), rtw_amsdu_vi_timeout_handler, padapter); pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET; - rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter, + rtw_init_timer(&(pxmitpriv->amsdu_be_timer), rtw_amsdu_be_timeout_handler, padapter); pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET; - rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter, + rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), rtw_amsdu_bk_timeout_handler, padapter); pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET; pxmitpriv->amsdu_debug_set_timer = 0; pxmitpriv->amsdu_debug_timeout = 0; - pxmitpriv->amsdu_debug_coalesce_one = 0; - pxmitpriv->amsdu_debug_coalesce_two = 0; + pxmitpriv->amsdu_debug_tasklet = 0; + pxmitpriv->amsdu_debug_enqueue = 0; + pxmitpriv->amsdu_debug_dequeue = 0; + for (i = 0; i < AMSDU_DEBUG_MAX_COUNT; i++) + pxmitpriv->amsdu_debug_coalesce[i] = 0; #endif #ifdef DBG_TXBD_DESC_DUMP pxmitpriv->dump_txbd_desc = 0; #endif rtw_init_xmit_block(padapter); - rtw_hal_init_xmit_priv(padapter); + rtw_intf_init_xmit_priv(padapter); -exit: +#ifdef RTW_PHL_TX //alloc xmit resource + printk("eric-tx CALL alloc_txring !!!!\n"); + if (alloc_txring(padapter) == _FAIL) { + RTW_ERR("[core] alloc_txring fail !!!\n"); + res = _FAIL; + goto exit; + } +#endif + +#if defined(CONFIG_CORE_TXSC) + _rtw_spinlock_init(&pxmitpriv->txsc_lock); +#endif +exit: return res; } -void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv); void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv) { _rtw_spinlock_free(&pxmitpriv->lock); + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ _rtw_free_sema(&pxmitpriv->xmit_sema); + #endif _rtw_spinlock_free(&pxmitpriv->be_pending.lock); _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); _rtw_spinlock_free(&pxmitpriv->vi_pending.lock); _rtw_spinlock_free(&pxmitpriv->vo_pending.lock); - _rtw_spinlock_free(&pxmitpriv->mgmt_pending.lock); + _rtw_spinlock_free(&pxmitpriv->bm_pending.lock); /* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */ /* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */ _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock); + #if 0 /*CONFIG_CORE_XMITBUF*/ _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock); _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock); + #endif } @@ -386,70 +540,112 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) { int i; _adapter *padapter = pxmitpriv->adapter; - struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; + struct xmit_frame *pxmitframe; + #if 0 /*CONFIG_CORE_XMITBUF*/ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; + #endif + #if 0 /*CONFIG_CORE_XMITBUF*/ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 xmitbuf_nr = GET_HAL_XMITBUF_NR(dvobj); + u16 xmitbuf_sz = GET_HAL_XMITBUF_SZ(dvobj); + + u8 xmitbuf_ext_nr = GET_HAL_XMITBUF_EXT_NR(dvobj); + u16 xmitbuf_ext_sz = GET_HAL_XMITBUF_EXT_SZ(dvobj); + #endif - rtw_hal_free_xmit_priv(padapter); + rtw_intf_free_xmit_priv(padapter); rtw_mfree_xmit_priv_lock(pxmitpriv); if (pxmitpriv->pxmit_frame_buf == NULL) goto out; + pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; + for (i = 0; i < NR_XMITFRAME; i++) { rtw_os_xmit_complete(padapter, pxmitframe); - + /*alloc buf_addr*/ + /*rtw_os_xmit_resource_free(padapter, pxmitframe);*/ pxmitframe++; } - for (i = 0; i < NR_XMITBUFF; i++) { - rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + #if 0 /*CONFIG_CORE_XMITBUF*/ + for (i = 0; i < xmitbuf_nr; i++) { + rtw_os_xmit_resource_free(padapter, pxmitbuf, + (xmitbuf_sz + SZ_ALIGN_XMITFRAME_EXT), _TRUE); pxmitbuf++; } - + #endif if (pxmitpriv->pallocated_frame_buf) - rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4); - + rtw_vmfree(pxmitpriv->pallocated_frame_buf, + NR_XMITFRAME * sizeof(struct xmit_frame) + 4); + #if 0 /*CONFIG_CORE_XMITBUF*/ if (pxmitpriv->pallocated_xmitbuf) - rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + rtw_vmfree(pxmitpriv->pallocated_xmitbuf, + xmitbuf_nr * sizeof(struct xmit_buf) + 4); + #endif /* free xframe_ext queue, the same count as extbuf */ - if ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) { - for (i = 0; i < NR_XMIT_EXTBUFF; i++) { - rtw_os_xmit_complete(padapter, pxmitframe); - pxmitframe++; - } + if (pxmitpriv->xframe_ext == NULL) + goto out; + + pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext; + for (i = 0; i < NR_XMITFRAME_EXT; i++) { + rtw_os_xmit_complete(padapter, pxmitframe); + /*free buf_addr*/ + rtw_os_xmit_resource_free(padapter, pxmitframe); + pxmitframe++; } + if (pxmitpriv->xframe_ext_alloc_addr) - rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, + NR_XMITFRAME_EXT * sizeof(struct xmit_frame) + 4); _rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock); + if (pxmitpriv->xframe_ext_txreq_alloc_addr) + rtw_mfree(pxmitpriv->xframe_ext_txreq_alloc_addr, NR_XMITFRAME_EXT * SZ_MGT_RING); + +#if 0 /*CONFIG_CORE_XMITBUF*/ + /* free xmit extension buff */ _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock); -#ifdef CONFIG_LAYER2_ROAMING - _rtw_spinlock_free(&pxmitpriv->rpkt_queue.lock); -#endif + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; - for (i = 0; i < NR_XMIT_EXTBUFF; i++) { - rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + for (i = 0; i < xmitbuf_ext_nr; i++) { + rtw_os_xmit_resource_free(padapter, pxmitbuf, + (xmitbuf_ext_sz + SZ_ALIGN_XMITFRAME_EXT), _TRUE); pxmitbuf++; } if (pxmitpriv->pallocated_xmit_extbuf) - rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, + xmitbuf_ext_nr * sizeof(struct xmit_buf) + 4); for (i = 0; i < CMDBUF_MAX; i++) { pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i]; if (pxmitbuf != NULL) - rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE); + rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + SZ_ALIGN_XMITFRAME_EXT, _TRUE); } - + #endif rtw_free_hwxmits(padapter); +#ifdef CONFIG_LAYER2_ROAMING + _rtw_spinlock_free(&pxmitpriv->rpkt_queue.lock); +#endif + +#ifdef RTW_PHL_TX + free_txring(padapter); +#endif + +#ifdef CONFIG_CORE_TXSC + txsc_clear(padapter); + _rtw_spinlock_free(&pxmitpriv->txsc_lock); +#endif + #ifdef CONFIG_XMIT_ACK _rtw_mutex_free(&pxmitpriv->ack_tx_mutex); #endif @@ -458,13 +654,145 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) return; } +u8 rtw_init_lite_xmit_resource(struct dvobj_priv *dvobj) +{ + + u8 ret = _SUCCESS; +/*YiWei_todo need use correct litexmitbuf_nr urb_nr*/ + u32 litexmitbuf_nr = RTW_LITEXMITBUF_NR; + u32 litexmitbuf_ext_nr = RTW_LITEXMITBUF_NR; + struct lite_data_buf *litexmitbuf; + struct trx_data_buf_q *litexmitbuf_q = &dvobj->litexmitbuf_q; + struct trx_data_buf_q *litexmit_extbuf_q = &dvobj->litexmit_extbuf_q; + int i; +#ifdef CONFIG_USB_HCI + struct trx_urb_buf_q *xmit_urb_q = &dvobj->xmit_urb_q; + struct data_urb *xmiturb; + u32 urb_nr = RTW_XMITURB_NR; +#endif + + /* init lite_xmit_buf */ + _rtw_init_queue(&litexmitbuf_q->free_data_buf_queue); + + litexmitbuf_q->alloc_data_buf = + rtw_zvmalloc(litexmitbuf_nr * sizeof(struct lite_data_buf) + 4); + + if (litexmitbuf_q->alloc_data_buf == NULL) { + ret = _FAIL; + goto exit; + } + + litexmitbuf_q->data_buf = + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(litexmitbuf_q->alloc_data_buf), 4); + + litexmitbuf = (struct lite_data_buf *)litexmitbuf_q->data_buf; + + for (i = 0; i < litexmitbuf_nr; i++) { + _rtw_init_listhead(&litexmitbuf->list); + rtw_list_insert_tail(&litexmitbuf->list, + &(litexmitbuf_q->free_data_buf_queue.queue)); + litexmitbuf++; + } + litexmitbuf_q->free_data_buf_cnt = litexmitbuf_nr; + + + /* Init lite xmit extension buff */ + _rtw_init_queue(&litexmit_extbuf_q->free_data_buf_queue); + + litexmit_extbuf_q->alloc_data_buf = + rtw_zvmalloc(litexmitbuf_ext_nr * sizeof(struct lite_data_buf) + 4); + + if (litexmit_extbuf_q->alloc_data_buf == NULL) { + ret = _FAIL; + goto exit; + } + + litexmit_extbuf_q->data_buf = + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(litexmit_extbuf_q->alloc_data_buf), 4); + + litexmitbuf = (struct lite_data_buf *)litexmit_extbuf_q->data_buf; + + for (i = 0; i < litexmitbuf_ext_nr; i++) { + _rtw_init_listhead(&litexmitbuf->list); + rtw_list_insert_tail(&litexmitbuf->list, + &(litexmit_extbuf_q->free_data_buf_queue.queue)); + litexmitbuf++; + } + litexmit_extbuf_q->free_data_buf_cnt = litexmitbuf_ext_nr; + +#ifdef CONFIG_USB_HCI + /* init xmit_urb */ + _rtw_init_queue(&xmit_urb_q->free_urb_buf_queue); + xmit_urb_q->alloc_urb_buf = + rtw_zvmalloc(urb_nr * sizeof(struct data_urb) + 4); + if (xmit_urb_q->alloc_urb_buf == NULL) { + ret = _FAIL; + goto exit; + } + + xmit_urb_q->urb_buf = + (u8 *)N_BYTE_ALIGNMENT((SIZE_PTR)(xmit_urb_q->alloc_urb_buf), 4); + + xmiturb = (struct data_urb *)xmit_urb_q->urb_buf; + for (i = 0; i < urb_nr; i++) { + _rtw_init_listhead(&xmiturb->list); + ret = rtw_os_urb_resource_alloc(xmiturb); + rtw_list_insert_tail(&xmiturb->list, + &(xmit_urb_q->free_urb_buf_queue.queue)); + xmiturb++; + } + xmit_urb_q->free_urb_buf_cnt = urb_nr; +#endif + +exit: + return ret; +} + +void rtw_free_lite_xmit_resource(struct dvobj_priv *dvobj) +{ + u8 ret = _SUCCESS; +/*YiWei_todo need use correct litexmitbuf_nr urb_nr*/ + u32 litexmitbuf_nr = RTW_LITEXMITBUF_NR; + u32 litexmitbuf_ext_nr = RTW_LITEXMITBUF_NR; + struct trx_data_buf_q *litexmitbuf_q = &dvobj->litexmitbuf_q; + struct trx_data_buf_q *litexmit_extbuf_q = &dvobj->litexmit_extbuf_q; +#ifdef CONFIG_USB_HCI + struct data_urb *xmiturb; + struct trx_urb_buf_q *xmit_urb_q = &dvobj->xmit_urb_q; + u32 urb_nr = RTW_XMITURB_NR; + int i; +#endif + + if (litexmitbuf_q->alloc_data_buf) + rtw_vmfree(litexmitbuf_q->alloc_data_buf, + litexmitbuf_nr * sizeof(struct lite_data_buf) + 4); + + if (litexmit_extbuf_q->alloc_data_buf) + rtw_vmfree(litexmit_extbuf_q->alloc_data_buf, + litexmitbuf_ext_nr * sizeof(struct lite_data_buf) + 4); + +#ifdef CONFIG_USB_HCI + xmiturb = (struct data_urb *)xmit_urb_q->urb_buf; + for (i = 0; i < urb_nr; i++) { + rtw_os_urb_resource_free(xmiturb); + xmiturb++; + } + + if (xmit_urb_q->alloc_urb_buf) + rtw_vmfree(xmit_urb_q->alloc_urb_buf, + urb_nr * sizeof(struct data_urb) + 4); +#endif + +} + + u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) { u8 bw; - bw = sta->cmn.bw_mode; + bw = sta->phl_sta->chandef.bw; if (MLME_STATE(adapter) & WIFI_ASOC_STATE) { - if (adapter->mlmeextpriv.cur_channel <= 14) + if (adapter->mlmeextpriv.chandef.chan <= 14) bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter)); else bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter)); @@ -475,6 +803,8 @@ u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht) { +/* ToDo */ +#if 0 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); u8 fix_bw = 0xFF; @@ -483,7 +813,7 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ u64 bmp_vht = 0; int i; - if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF) + if (adapter->fix_rate != NO_FIX_RATE && adapter->fix_bw != NO_FIX_BW) fix_bw = adapter->fix_bw; /* TODO: adapter->fix_rate */ @@ -515,10 +845,13 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ *r_bmp_ht = bmp_ht; if (r_bmp_vht) *r_bmp_vht = bmp_vht; +#endif } void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht) { +/* ToDo */ +#if 0 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); u16 bmp_cck_ofdm = 0; u32 bmp_ht = 0; @@ -550,45 +883,16 @@ void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_ht = bmp_ht; if (r_bmp_vht) *r_bmp_vht = bmp_vht; -} - -void rtw_get_adapter_tx_rate_bmp(_adapter *adapter, u16 r_bmp_cck_ofdm[], u32 r_bmp_ht[], u64 r_bmp_vht[]) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - u8 bw; - u16 bmp_cck_ofdm, tmp_cck_ofdm; - u32 bmp_ht, tmp_ht; - u64 bmp_vht, tmp_vht; - int i; - - for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { - bmp_cck_ofdm = bmp_ht = bmp_vht = 0; - if (hal_is_bw_support(adapter, bw)) { - { - rtw_get_adapter_tx_rate_bmp_by_bw(adapter, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); - bmp_cck_ofdm |= tmp_cck_ofdm; - bmp_ht |= tmp_ht; - bmp_vht |= tmp_vht; - } - rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); - bmp_cck_ofdm |= tmp_cck_ofdm; - bmp_ht |= tmp_ht; - bmp_vht |= tmp_vht; - } - if (bw == CHANNEL_WIDTH_20) - r_bmp_cck_ofdm[bw] = bmp_cck_ofdm; - if (bw <= CHANNEL_WIDTH_40) - r_bmp_ht[bw] = bmp_ht; - if (bw <= CHANNEL_WIDTH_160) - r_bmp_vht[bw] = bmp_vht; - } +#endif } void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj) { +#if 0 /*GEORGIA_TODO_FIXIT*/ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); _adapter *adapter = dvobj_get_primary_adapter(dvobj); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_PHL_COM(dvobj); u8 bw; u16 bmp_cck_ofdm, tmp_cck_ofdm; u32 bmp_ht, tmp_ht, ori_bmp_ht[2]; @@ -603,7 +907,7 @@ void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj) ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw]; bmp_cck_ofdm = bmp_ht = bmp_vht = 0; - if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) { + if (rtw_hw_is_bw_support(dvobj, bw)) { for (i = 0; i < dvobj->iface_nums; i++) { if (!dvobj->padapters[i]) continue; @@ -688,9 +992,10 @@ void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj) /* TODO: per rfpath and rate section handling? */ if (update_ht_rs == _TRUE || update_vht_rs == _TRUE) - rtw_hal_update_txpwr_level(adapter); + rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel); } #endif /* CONFIG_TXPWR_LIMIT */ +#endif } u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) @@ -747,245 +1052,60 @@ u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) return bw_bmp; } -s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp) +s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp) { - s16 mbm = -100 * MBM_PDBM; - - if (MLME_IS_ASOC(adapter)) { - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - u8 ch = mlmeext->cur_channel; - u8 bw = mlmeext->cur_bwmode; - u8 offset = mlmeext->cur_ch_offset; - u8 cch = rtw_get_center_ch(ch, bw, offset); - u8 hw_rate = MRateToHwRate(mlmeext->tx_rate); - u16 bmp_cck_ofdm_by_bw[1] = {0}; - u32 bmp_ht_by_bw[2] = {0}; - u64 bmp_vht_by_bw[4] = {0}; - u16 bmp_cck_ofdm = 0; - u32 bmp_ht = 0; - u64 bmp_vht = 0; - int i; - - rtw_get_adapter_tx_rate_bmp(adapter, bmp_cck_ofdm_by_bw, bmp_ht_by_bw, bmp_vht_by_bw); - - bmp_cck_ofdm |= bmp_cck_ofdm_by_bw[0]; - for (i = 0; i < 2; i++) - bmp_ht |= bmp_ht_by_bw[i]; - for (i = 0; i < 4; i++) - bmp_vht |= bmp_vht_by_bw[i]; - - if (IS_LEGACY_HRATE(hw_rate)) - bmp_cck_ofdm |= BIT(hw_rate); - else if (IS_HT_HRATE(hw_rate)) - bmp_ht |= BIT(hw_rate - DESC_RATEMCS0); - else if (IS_VHT_HRATE(hw_rate)) - bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0); - - mbm = phy_get_txpwr_total_max_mbm(adapter - , bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 0, eirp); - } - + /* TODO: get maximum txpower of current operating class & channel belongs to this radio */ + s16 mbm = 2000; return mbm; } -s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp) +s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp) { - struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); - _adapter *adapter = dvobj_get_primary_adapter(dvobj); - s16 mbm = -100 * MBM_PDBM; - - if (ch) { - u8 cch = rtw_get_center_ch(ch, bw, offset); - u16 bmp_cck_ofdm = 0; - u32 bmp_ht = 0; - u64 bmp_vht = 0; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - struct mlme_ext_priv *mlmeext; - u8 hw_rate; - - if (!dvobj->padapters[i]) - continue; - - if (ifbmp_mod & BIT(i)) { - if (!if_op) - continue; - } else if (!MLME_IS_ASOC(dvobj->padapters[i])) - continue; - - mlmeext = &(dvobj->padapters[i]->mlmeextpriv); - hw_rate = MRateToHwRate(mlmeext->tx_rate); - - if (IS_LEGACY_HRATE(hw_rate)) - bmp_cck_ofdm |= BIT(hw_rate); - else if (IS_HT_HRATE(hw_rate)) - bmp_ht |= BIT(hw_rate - DESC_RATEMCS0); - else if (IS_VHT_HRATE(hw_rate)) - bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0); - } - - bmp_cck_ofdm |= rfctl->rate_bmp_cck_ofdm; - for (i = 0; i < 2; i++) - bmp_ht |= rfctl->rate_bmp_ht_by_bw[i]; - for (i = 0; i < 4; i++) - bmp_vht |= rfctl->rate_bmp_vht_by_bw[i]; - - mbm = phy_get_txpwr_total_max_mbm(adapter - , bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 0, eirp); - } - + /* TODO: get maximum txpower of current operating class & channel belongs to this radio allowed by regulatory */ + s16 mbm = 1300; return mbm; } -s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool eirp) +u8 query_ra_short_GI(struct sta_info *psta, u8 bw) { - struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); - _adapter *adapter = dvobj_get_primary_adapter(dvobj); - s16 mbm = -100 * MBM_PDBM; - u8 ch = rfctl->op_ch, bw, offset; + u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE; + +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT +#ifdef CONFIG_80211AX_HE + /* CONFIG_80211AX_HE_TODO */ +#endif /* CONFIG_80211AX_HE */ + if (psta->vhtpriv.vht_option) + sgi_80m = psta->vhtpriv.sgi_80m; +#endif + sgi_20m = psta->htpriv.sgi_20m; + sgi_40m = psta->htpriv.sgi_40m; +#endif - if (rtw_get_bw_offset_by_op_class_ch(rfctl->op_class, ch, &bw, &offset)) - mbm = rtw_rfctl_get_oper_txpwr_max_mbm(rfctl, ch, bw, offset, 0, 0, eirp); + switch (bw) { + case CHANNEL_WIDTH_80: + sgi = sgi_80m; + break; + case CHANNEL_WIDTH_40: + sgi = sgi_40m; + break; + case CHANNEL_WIDTH_20: + default: + sgi = sgi_20m; + break; + } - return mbm; + return sgi; } -s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp) +static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) { - struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); - struct registry_priv *regsty = dvobj_to_regsty(dvobj); - _adapter *adapter = dvobj_get_primary_adapter(dvobj); - s16 mbm = -100 * MBM_PDBM; - u8 cch = rtw_get_center_ch(ch, bw, offset); - u16 bmp_cck_ofdm = 0; - u32 bmp_ht = 0; - u64 bmp_vht = 0; + u32 sz; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + /* struct sta_info *psta = pattrib->psta; */ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (ch <= 14) - bmp_cck_ofdm |= RATE_BMP_CCK; - - /* TODO: NO OFDM? */ - bmp_cck_ofdm |= RATE_BMP_OFDM; - -#ifdef CONFIG_80211N_HT - if (regsty->ht_enable && is_supported_ht(regsty->wireless_mode)) { - switch (GET_HAL_TX_NSS(adapter)) { - case 1: - bmp_ht |= RATE_BMP_HT_1SS; - break; - case 2: - bmp_ht |= RATE_BMP_HT_2SS | RATE_BMP_HT_1SS; - break; - case 3: - bmp_ht |= RATE_BMP_HT_3SS | RATE_BMP_HT_2SS | RATE_BMP_HT_1SS; - break; - case 4: - bmp_ht |= RATE_BMP_HT_4SS | RATE_BMP_HT_3SS | RATE_BMP_HT_2SS | RATE_BMP_HT_1SS; - break; - default: - rtw_warn_on(1); - } - } -#endif - -#ifdef CONFIG_80211AC_VHT - if (ch > 14 && REGSTY_IS_11AC_ENABLE(regsty) && is_supported_vht(regsty->wireless_mode) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { - switch (GET_HAL_TX_NSS(adapter)) { - case 1: - bmp_vht |= RATE_BMP_VHT_1SS; - break; - case 2: - bmp_vht |= RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS; - break; - case 3: - bmp_vht |= RATE_BMP_VHT_3SS | RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS; - break; - case 4: - bmp_vht |= RATE_BMP_VHT_4SS | RATE_BMP_VHT_3SS | RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS; - break; - default: - rtw_warn_on(1); - } - } -#endif - - mbm = phy_get_txpwr_total_max_mbm(adapter - , bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 1, eirp); - - return mbm; -} - -u8 query_ra_short_GI(struct sta_info *psta, u8 bw) -{ - u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE; - -#ifdef CONFIG_80211N_HT -#ifdef CONFIG_80211AC_VHT - if (psta->vhtpriv.vht_option) - sgi_80m = psta->vhtpriv.sgi_80m; -#endif - sgi_20m = psta->htpriv.sgi_20m; - sgi_40m = psta->htpriv.sgi_40m; -#endif - - switch (bw) { - case CHANNEL_WIDTH_80: - sgi = sgi_80m; - break; - case CHANNEL_WIDTH_40: - sgi = sgi_40m; - break; - case CHANNEL_WIDTH_20: - default: - sgi = sgi_20m; - break; - } - - return sgi; -} - -/* This function references driver insmond parameters to decide vcs mode. */ -/* Driver insmond parameters: rtw_vrtl_carrier_sense and rtw_vcs_type */ -static u8 validate_vcs(_adapter *padapter, u8 mode) { - - u8 vcs_mode = NONE_VCS; - - switch(padapter->registrypriv.vrtl_carrier_sense) { - - case DISABLE_VCS: - vcs_mode = NONE_VCS; - break; - - case ENABLE_VCS: - vcs_mode = padapter->registrypriv.vcs_type; - break; - - case AUTO_VCS: - vcs_mode = mode; - break; - - default: - vcs_mode = NONE_VCS; - break; - } - - return vcs_mode; - -} - -static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) -{ - u32 sz; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - #ifdef RTW_FORCE_CTS_TO_SELF_UNDER_LOW_RSSI - s8 rssi = 0; - struct sta_info *psta = pattrib->psta; - #endif /* if(pattrib->psta) { @@ -1019,7 +1139,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf /* (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. */ /* Other fragments are protected by previous fragment. */ /* So we only need to check the length of first fragment. */ - if (pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec) { + if (pmlmeext->cur_wireless_mode < WLAN_MD_11N || padapter->registrypriv.wifi_spec) { if (sz > padapter->registrypriv.rts_thresh) pattrib->vcs_mode = RTS_CTS; else { @@ -1052,6 +1172,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf break; } + /* check ERP protection */ if (pattrib->rtsen || pattrib->cts2self) { if (pattrib->rtsen) @@ -1065,8 +1186,8 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf /* check HT op mode */ if (pattrib->ht_en) { u8 HTOpMode = pmlmeinfo->HT_protection; - if ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) || - (!pmlmeext->cur_bwmode && HTOpMode == 3)) { + if ((pmlmeext->chandef.bw && (HTOpMode == 2 || HTOpMode == 3)) || + (!pmlmeext->chandef.bw && HTOpMode == 3)) { pattrib->vcs_mode = RTS_CTS; break; } @@ -1081,7 +1202,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf /* to do list: check MIMO power save condition. */ /* check AMPDU aggregation for TXOP */ - if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) { + if (pattrib->ampdu_en == _TRUE) { pattrib->vcs_mode = RTS_CTS; break; } @@ -1089,18 +1210,8 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf pattrib->vcs_mode = NONE_VCS; break; } - #ifdef RTW_FORCE_CTS_TO_SELF_UNDER_LOW_RSSI - /*RTStoCTS while let TP degree ,while enable full BW*/ - if (psta != NULL) { - rssi = psta->cmn.rssi_stat.rssi; - if ((rssi < 18) && (pattrib->vcs_mode == RTS_CTS)) - pattrib->vcs_mode = CTS_TO_SELF; - } - #endif } - pattrib->vcs_mode = validate_vcs(padapter, pattrib->vcs_mode); - /* for debug : force driver control vrtl_carrier_sense. */ if (padapter->driver_vcs_en == 1) { /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ @@ -1113,9 +1224,9 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf #ifdef CONFIG_WMMPS_STA /* * update_attrib_trigger_frame_info - * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data + * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode. - * + * * Arguments: * @padapter: _adapter pointer. * @pattrib: pkt_attrib pointer. @@ -1123,15 +1234,16 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf * Auther: Arvin Liu * Date: 2017/06/05 */ -static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) { +static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; u8 trigger_frame_en = 0; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { - if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) { - if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) { + if (MLME_IS_STA(padapter)) { + if ((pwrpriv->pwr_mode == PM_PS_MODE_MIN) || (pwrpriv->pwr_mode == PM_PS_MODE_MAX)) { + if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) { trigger_frame_en = 1; RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter)); } @@ -1149,25 +1261,42 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->rtsen = psta->rtsen; pattrib->cts2self = psta->cts2self; + pattrib->hw_rts_en = psta->hw_rts_en; pattrib->mdata = 0; pattrib->eosp = 0; +#ifdef CONFIG_80211AX_HE + if (psta->hepriv.he_option == _TRUE) + pattrib->eosp = 1; +#endif pattrib->triggered = 0; pattrib->ampdu_spacing = 0; /* ht_en, init rate, ,bw, ch_offset, sgi */ - pattrib->raid = psta->cmn.ra_info.rate_id; + /* ToDo: Need API to inform hal_sta->ra_info.rate_id */ + /* pattrib->raid = psta->phl_sta->ra_info.rate_id; */ bw = rtw_get_tx_bw_mode(padapter, psta); - pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode); + pattrib->bwmode = rtw_min(bw, mlmeext->chandef.bw); pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); - pattrib->ldpc = psta->cmn.ldpc_en; - pattrib->stbc = psta->cmn.stbc_en; + if (psta->phl_sta->wmode & WLAN_MD_11AX) { + pattrib->ldpc = psta->phl_sta->asoc_cap.he_ldpc; + pattrib->stbc = (psta->phl_sta->asoc_cap.stbc_he_rx > 0) ? 1:0; + } else if (psta->phl_sta->wmode & WLAN_MD_11AC) { + pattrib->ldpc = psta->phl_sta->asoc_cap.vht_ldpc; + pattrib->stbc = (psta->phl_sta->asoc_cap.stbc_vht_rx > 0) ? 1:0; + } else if (psta->phl_sta->wmode & WLAN_MD_11N) { + pattrib->ldpc = psta->phl_sta->asoc_cap.ht_ldpc; + pattrib->stbc = (psta->phl_sta->asoc_cap.stbc_ht_rx > 0) ? 1:0; + } else { + pattrib->ldpc = 0; + pattrib->stbc = 0; + } #ifdef CONFIG_80211N_HT - if(padapter->registrypriv.ht_enable && + if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) { pattrib->ht_en = psta->htpriv.ht_option; pattrib->ch_offset = psta->htpriv.ch_offset; @@ -1200,15 +1329,15 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri if (pattrib->direct_link == _TRUE) { psta = pattrib->ptdls_sta; - pattrib->raid = psta->cmn.ra_info.rate_id; + pattrib->raid = psta->phl_sta->ra_info.rate_id; #ifdef CONFIG_80211N_HT - if(padapter->registrypriv.ht_enable && - is_supported_ht(padapter->registrypriv.wireless_mode)) { - pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); - pattrib->ht_en = psta->htpriv.ht_option; - pattrib->ch_offset = psta->htpriv.ch_offset; - pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); - } + if (padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); + } #endif /* CONFIG_80211N_HT */ } #endif /* CONFIG_TDLS */ @@ -1216,16 +1345,75 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->retry_ctrl = _FALSE; } +static s32 update_attrib_sec_iv_info(_adapter *padapter, struct pkt_attrib *pattrib) +{ + struct sta_info *psta = pattrib->psta; + sint bmcast = IS_MCAST(pattrib->ra); + + if (!psta) + return _FAIL; + + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + + case _TKIP_: + if (bmcast) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + break; + + case _AES_: + if (bmcast) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + + break; + + case _GCMP_: + case _GCMP_256_: + if (bmcast) + GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + GCMP_IV(pattrib->iv, psta->dot11txpn, 0); + + break; + + case _CCMP_256_: + if (bmcast) + GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + GCMP_IV(pattrib->iv, psta->dot11txpn, 0); + + break; + +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv); + break; +#endif + default: + break; + } + + return _SUCCESS; +} + static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta, enum eap_type eapol_type) { sint res = _SUCCESS; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; sint bmcast = IS_MCAST(pattrib->ra); + s8 hw_decrypted = _FALSE; - _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); - _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); - pattrib->mac_id = psta->cmn.mac_id; + _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); + _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); + pattrib->mac_id = psta->phl_sta->macid; /* Comment by Owen at 2020/05/19 * Issue: RTK STA sends encrypted 4-way 4/4 when AP thinks the 4-way incomplete @@ -1296,7 +1484,6 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib case _WEP104_: pattrib->iv_len = 4; pattrib->icv_len = 4; - WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); break; case _TKIP_: @@ -1311,12 +1498,6 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib goto exit; } - if (bmcast) - TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - TKIP_IV(pattrib->iv, psta->dot11txpn, 0); - - _rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16); break; @@ -1326,11 +1507,6 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib pattrib->iv_len = 8; pattrib->icv_len = 8; - if (bmcast) - AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - AES_IV(pattrib->iv, psta->dot11txpn, 0); - break; case _GCMP_: @@ -1339,11 +1515,6 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib pattrib->iv_len = 8; pattrib->icv_len = 16; - if (bmcast) - GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - GCMP_IV(pattrib->iv, psta->dot11txpn, 0); - break; case _CCMP_256_: @@ -1351,18 +1522,12 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib pattrib->iv_len = 8; pattrib->icv_len = 16; - if (bmcast) - GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - GCMP_IV(pattrib->iv, psta->dot11txpn, 0); - break; #ifdef CONFIG_WAPI_SUPPORT case _SMS4_: pattrib->iv_len = 18; pattrib->icv_len = 16; - rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv); break; #endif default: @@ -1377,18 +1542,21 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib , (pattrib->encrypt & _SEC_TYPE_256_) ? 32 : 16); } + if (!bmcast) + hw_decrypted = psta->hw_decrypted; + else + hw_decrypted = psecuritypriv->hw_decrypted; if (pattrib->encrypt && - ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) { + (padapter->securitypriv.sw_encrypt == _TRUE || hw_decrypted == _FALSE || pattrib->encrypt == _TKIP_)) { pattrib->bswenc = _TRUE; } else { pattrib->bswenc = _FALSE; } +#if defined(CONFIG_CONCURRENT_MODE) pattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id; - - if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) - pattrib->bswenc = _TRUE; +#endif #ifdef CONFIG_WAPI_SUPPORT if (pattrib->encrypt == _SMS4_) @@ -1436,7 +1604,7 @@ u8 qos_acm(u8 acm_mask, u8 priority) } /* refer to IEEE802.11-2016 Table R-3; Comply with IETF RFC4594 */ -static u8 tos_to_up(u8 tos) +u8 tos_to_up(u8 tos) { u8 up = 0; u8 dscp; @@ -1454,27 +1622,64 @@ static u8 tos_to_up(u8 tos) */ dscp = (tos >> 2); - if ( dscp == 0 ) + if (dscp == 0) up = 0; - else if ( dscp >= 1 && dscp <= 9) + else if (dscp >= 1 && dscp <= 9) up = 1; - else if ( dscp >= 10 && dscp <= 16) + else if (dscp >= 10 && dscp <= 16) up = 2; - else if ( dscp >= 17 && dscp <= 23) + else if (dscp >= 17 && dscp <= 23) up = 3; - else if ( dscp >= 24 && dscp <= 31) + else if (dscp >= 24 && dscp <= 31) up = 4; - else if ( dscp >= 33 && dscp <= 40) + else if (dscp >= 33 && dscp <= 40) up = 5; else if ((dscp >= 41 && dscp <= 47) || (dscp == 32)) up = 6; - else if ( dscp >= 48 && dscp <= 63) + else if (dscp >= 48 && dscp <= 63) up = 7; return up; } -static void set_qos(_pkt *pkt, struct pkt_attrib *pattrib) +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +static void set_qos_core(struct xmit_frame *pxframe) +{ + s32 UserPriority = 0; + + if (!pxframe->pkt) + goto null_pkt; + + /* get UserPriority from IP hdr */ + if (pxframe->attrib.ether_type == 0x0800) { + struct pkt_file ppktfile; + struct ethhdr etherhdr; + struct iphdr ip_hdr; + + _rtw_open_pktfile(pxframe->pkt, &ppktfile); + _rtw_pktfile_read(&ppktfile, (unsigned char *)ðerhdr, ETH_HLEN); + _rtw_pktfile_read(&ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr)); + UserPriority = tos_to_up(ip_hdr.tos); + } + + + #ifdef CONFIG_ICMP_VOQ + if (pxframe->attrib.icmp_pkt == 1)/*use VO queue to send icmp packet*/ + UserPriority = 7; + #endif + #ifdef CONFIG_IP_R_MONITOR + if (pxframe->attrib.ether_type == ETH_P_ARP) + UserPriority = 7; + #endif/*CONFIG_IP_R_MONITOR*/ + +null_pkt: + pxframe->attrib.priority = UserPriority; + pxframe->attrib.hdrlen = WLAN_HDR_A3_QOS_LEN; + pxframe->attrib.subtype = WIFI_QOS_DATA_TYPE; +} +#endif + +static void set_qos(struct sk_buff *pkt, struct pkt_attrib *pattrib) { s32 UserPriority = 0; @@ -1502,7 +1707,7 @@ static void set_qos(_pkt *pkt, struct pkt_attrib *pattrib) */ #ifdef CONFIG_ICMP_VOQ - if(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/ + if (pattrib->icmp_pkt == 1)/*use VO queue to send icmp packet*/ UserPriority = 7; #endif #ifdef CONFIG_IP_R_MONITOR @@ -1566,7 +1771,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) goto exit; } - pattrib->mac_id = psta->cmn.mac_id; + pattrib->mac_id = psta->phl_sta->macid; pattrib->psta = psta; pattrib->ack_policy = 0; /* get ether_hdr_len */ @@ -1601,24 +1806,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) #endif /* CONFIG_TDLS */ -/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/ -inline u8 rtw_get_hwseq_no(_adapter *padapter) -{ - u8 hwseq_num = 0; -#ifdef CONFIG_CONCURRENT_MODE - #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \ - || defined(CONFIG_RTL8723F) - hwseq_num = padapter->iface_id; - if (hwseq_num > 3) - hwseq_num = 3; - #else - if (!is_primary_adapter(padapter)) - hwseq_num = 1; - #endif -#endif /* CONFIG_CONCURRENT_MODE */ - return hwseq_num; -} #ifdef CONFIG_LPS #define LPS_PT_NORMAL 0 #define LPS_PT_SP 1/* only DHCP packets is as SPECIAL_PACKET*/ @@ -1645,111 +1833,111 @@ static u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib) return pkt_type; } #endif -static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) + +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +static s32 update_xmitframe_from_hdr(_adapter *padapter, struct xmit_frame *pxframe) { uint i; struct pkt_file pktfile; struct sta_info *psta = NULL; struct ethhdr etherhdr; - + struct sk_buff *pkt = NULL; sint bmcast; + struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct qos_priv *pqospriv = &pmlmepriv->qospriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - sint res = _SUCCESS; - enum eap_type eapol_type = NON_EAPOL; -#ifdef CONFIG_LPS - u8 pkt_type = 0; -#endif + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); + PHLTX_LOG; + + if (pxframe->pkt) + pkt = pxframe->pkt; + else + return FAIL; + + PHLTX_LOG; _rtw_open_pktfile(pkt, &pktfile); i = _rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN); - pattrib->ether_type = ntohs(etherhdr.h_proto); + pxframe->attrib.ether_type = ntohs(etherhdr.h_proto); - if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) /* address resolve is done for ap/mesh */ + if (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */ goto get_sta_info; - _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); - _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); - _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pxframe->attrib.dst, ðerhdr.h_dest, ETH_ALEN); + _rtw_memcpy(pxframe->attrib.src, ðerhdr.h_source, ETH_ALEN); if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { - _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); - DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc); - } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - #ifdef CONFIG_TDLS + _rtw_memcpy(pxframe->attrib.ra, pxframe->attrib.dst, ETH_ALEN); + _rtw_memcpy(pxframe->attrib.ta, adapter_mac_addr(padapter), ETH_ALEN); + } else if (MLME_IS_STA(padapter)) { + +#if 0//def CONFIG_TDLS //rtw_phl_tx if (rtw_check_tdls_established(padapter, pattrib) == _TRUE) _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); /* For TDLS direct link Tx, set ra to be same to dst */ else - #endif - { - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); - #ifdef CONFIG_RTW_WDS - if (adapter_use_wds(padapter) - && _rtw_memcmp(pattrib->src, pattrib->ta, ETH_ALEN) == _FALSE - ) { - pattrib->wds = 1; - if (IS_MCAST(pattrib->dst)) - rtw_tx_wds_gptr_update(padapter, pattrib->src); - } - #endif - } +#endif + _rtw_memcpy(pxframe->attrib.ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pxframe->attrib.ta, adapter_mac_addr(padapter), ETH_ALEN); DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + _rtw_memcpy(pxframe->attrib.ra, pxframe->attrib.dst, ETH_ALEN); + _rtw_memcpy(pxframe->attrib.ta, get_bssid(pmlmepriv), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_ap); } else DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); + PHLTX_LOG; + get_sta_info: - bmcast = IS_MCAST(pattrib->ra); + bmcast = IS_MCAST(pxframe->attrib.ra); if (bmcast) { + PHLTX_LOG; psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); #ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pxframe->attrib.ra)); #endif - res = _FAIL; - goto exit; + return FAIL; } } else { - psta = rtw_get_stainfo(pstapriv, pattrib->ra); + PHLTX_LOG; + psta = rtw_get_stainfo(pstapriv, pxframe->attrib.ra); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); #ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pxframe->attrib.ra)); #endif - res = _FAIL; - goto exit; + return FAIL; } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & WIFI_ASOC_STATE)) { DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link); - res = _FAIL; - goto exit; + return FAIL; } - - #ifdef CONFIG_RTW_WDS - if (XATTRIB_GET_WDS(pattrib) && !(psta->flags & WLAN_STA_WDS)) - pattrib->wds = 0; - #endif } + PHLTX_LOG; + if (!(psta->state & WIFI_ASOC_STATE)) { DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != WIFI_ASOC_STATE\n", - __func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state); - res = _FAIL; - goto exit; + __func__, ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr), psta->state); + return FAIL; } - pattrib->pktlen = pktfile.pkt_len; + pxframe->attrib.psta = psta; + + PHLTX_LOG; + + pxframe->attrib.pktlen = pktfile.pkt_len; /* TODO: 802.1Q VLAN header */ /* TODO: IPV6 */ - if (ETH_P_IP == pattrib->ether_type) { + if (ETH_P_IP == pxframe->attrib.ether_type) { u8 ip[20]; _rtw_pktfile_read(&pktfile, ip, 20); @@ -1757,12 +1945,12 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr if (GET_IPV4_IHL(ip) * 4 > 20) _rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20); - pattrib->icmp_pkt = 0; - pattrib->dhcp_pkt = 0; - pattrib->hipriority_pkt = 0; + pxframe->attrib.icmp_pkt = 0; + pxframe->attrib.dhcp_pkt = 0; + pxframe->attrib.hipriority_pkt = 0; if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */ - pattrib->icmp_pkt = 1; + pxframe->attrib.icmp_pkt = 1; DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp); } else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */ @@ -1774,8 +1962,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) ) { /* 67 : UDP BOOTP server, 68 : UDP BOOTP client */ - if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ - pattrib->dhcp_pkt = 1; + if (pxframe->attrib.pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ + pxframe->attrib.dhcp_pkt = 1; DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp); if (0) RTW_INFO("send DHCP packet\n"); @@ -1785,7 +1973,7 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr /* WaveAgent packet, increase priority so that the system can read data in time */ if (((GET_UDP_SIG1(udp) == 0xcc) || (GET_UDP_SIG1(udp) == 0xdd)) && (GET_UDP_SIG2(udp) == 0xe2)) { - pattrib->hipriority_pkt = 1; + pxframe->attrib.hipriority_pkt = 1; } } else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ @@ -1819,10 +2007,10 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } } - } else if (0x888e == pattrib->ether_type) - eapol_type = parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1); + } else if (0x888e == pxframe->attrib.ether_type) + parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1); #if defined (DBG_ARP_DUMP) || defined (DBG_IP_R_MONITOR) - else if (pattrib->ether_type == ETH_P_ARP) { + else if (pxframe->attrib.ether_type == ETH_P_ARP) { u8 arp[28] = {0}; _rtw_pktfile_read(&pktfile, arp, 28); @@ -1830,17 +2018,274 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } #endif - if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) + PHLTX_LOG; + + if ((pxframe->attrib.ether_type == 0x888e) || (pxframe->attrib.dhcp_pkt == 1)) rtw_mi_set_scan_deny(padapter, 3000); - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && - pattrib->ether_type == ETH_P_ARP && - !IS_MCAST(pattrib->dst)) { + if (MLME_IS_STA(padapter) && + pxframe->attrib.ether_type == ETH_P_ARP && + !IS_MCAST(pxframe->attrib.dst)) { rtw_mi_set_scan_deny(padapter, 1000); rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/ } -#ifdef CONFIG_LPS + + PHLTX_LOG; + + /* get ether_hdr_len */ + pxframe->attrib.pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */ + + pxframe->attrib.hdrlen = WLAN_HDR_A3_LEN; + pxframe->attrib.type = WIFI_DATA_TYPE; + pxframe->attrib.subtype = WIFI_DATA_TYPE; + pxframe->attrib.qos_en = pxframe->attrib.psta->qos_option; + pxframe->attrib.priority = 0; + + pxframe->attrib.frag_len = pxmitpriv->frag_len; + + + + PHLTX_LOG; + + return SUCCESS; +} + + +static s32 update_xmitframe_qos(_adapter *padapter, struct xmit_frame *pxframe) +{ + + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (!pxframe->attrib.qos_en) + return SUCCESS; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE + | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) + ) { + set_qos_core(pxframe); + #if 0//rtw_phl_tx def CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib); + #endif + } else { +#if 0// def CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + if (pattrib->qos_en) + set_qos(pkt, pattrib); + } else +#endif + { + if (pqospriv->qos_option) { + set_qos_core(pxframe); + + if (pmlmepriv->acm_mask != 0) + pxframe->attrib.priority = qos_acm(pmlmepriv->acm_mask, pxframe->attrib.priority); + } + } + } + + return SUCCESS; +} + +static s32 update_xmitframe_security(_adapter *padapter, struct xmit_frame *pxframe) //rtw_phl_tx todo +{ + sint res = _SUCCESS; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + sint bmcast = IS_MCAST(pxframe->attrib.ra); + +#if 0 + _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); + _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); + pattrib->mac_id = psta->phl_sta->macid; +#endif + + if (pxframe->attrib.psta->ieee8021x_blocked == _TRUE) { + + pxframe->attrib.encrypt = 0; + + if ((pxframe->attrib.ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) { +#ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pxframe->attrib.ether_type); +#endif + res = _FAIL; + goto exit; + } + } else { + GET_ENCRY_ALGO(psecuritypriv, pxframe->attrib.psta, pxframe->attrib.encrypt, bmcast); + +#ifdef CONFIG_WAPI_SUPPORT + if (pxframe->attrib.ether_type == 0x88B4) + pxframe->attrib.encrypt = _NO_PRIVACY_; +#endif + + switch (psecuritypriv->dot11AuthAlgrthm) { + case dot11AuthAlgrthm_Open: + case dot11AuthAlgrthm_Shared: + case dot11AuthAlgrthm_Auto: + pxframe->attrib.key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; + break; + case dot11AuthAlgrthm_8021X: + if (bmcast) + pxframe->attrib.key_idx = (u8)psecuritypriv->dot118021XGrpKeyid; + else + pxframe->attrib.key_idx = 0; + break; + default: + pxframe->attrib.key_idx = 0; + break; + } + + /* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */ + if (((pxframe->attrib.encrypt == _WEP40_) || (pxframe->attrib.encrypt == _WEP104_)) && (pxframe->attrib.ether_type == 0x888e)) + pxframe->attrib.encrypt = _NO_PRIVACY_; + + } + +#if 0 //def CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + if (pxframe->attrib.encrypt > 0) + pxframe->attrib.encrypt = _AES_; + } +#endif + + switch (pxframe->attrib.encrypt) { + case _WEP40_: + case _WEP104_: + pxframe->attrib.iv_len = 4; + pxframe->attrib.icv_len = 4; + WEP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, pxframe->attrib.key_idx); + break; + + case _TKIP_: + pxframe->attrib.iv_len = 8; + pxframe->attrib.icv_len = 4; + + if (psecuritypriv->busetkipkey == _FAIL) { +#ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, psecuritypriv->busetkipkey); +#endif + res = _FAIL; + goto exit; + } + + if (bmcast) + TKIP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, pxframe->attrib.key_idx); + else + TKIP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, 0); + + + //_rtw_memcpy(pattrib->dot11tkiptxmickey.skey, pxframe->attrib.psta->dot11tkiptxmickey.skey, 16); + + break; + + case _AES_: + + pxframe->attrib.iv_len = 8; + pxframe->attrib.icv_len = 8; + + if (bmcast) + AES_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, pxframe->attrib.key_idx); + else + AES_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, 0); + + break; + + case _GCMP_: + case _GCMP_256_: + + pxframe->attrib.iv_len = 8; + pxframe->attrib.icv_len = 16; + + if (bmcast) + GCMP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, pxframe->attrib.key_idx); + else + GCMP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, 0); + + break; + + case _CCMP_256_: + + pxframe->attrib.iv_len = 8; + pxframe->attrib.icv_len = 16; + + if (bmcast) + GCMP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, pxframe->attrib.key_idx); + else + GCMP_IV(pxframe->attrib.iv, pxframe->attrib.psta->dot11txpn, 0); + + break; + +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + pxframe->attrib.iv_len = 18; + pxframe->attrib.icv_len = 16; + rtw_wapi_get_iv(padapter, pxframe->attrib.ra, pxframe->attrib.iv); + break; +#endif + default: + pxframe->attrib.iv_len = 0; + pxframe->attrib.icv_len = 0; + break; + } + +#if 0 + if (pxframe->attrib.encrypt > 0) { + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey + , pxframe->attrib.psta->dot118021x_UncstKey.skey + , (pxframe->attrib.encrypt & _SEC_TYPE_256_) ? 32 : 16); + } +#endif + + if (pxframe->attrib.encrypt && + ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) { + pxframe->attrib.bswenc = _TRUE; + } else { + pxframe->attrib.bswenc = _FALSE; + } + +#if defined(CONFIG_CONCURRENT_MODE) + //pattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id; +#endif + +#ifdef CONFIG_WAPI_SUPPORT + if (pxframe->attrib.encrypt == _SMS4_) + pxframe->attrib.bswenc = _FALSE; +#endif + +exit: + return res; + +} + +static s32 update_xmitframe_hw(_adapter *padapter, struct xmit_frame *pxframe) +{ + pxframe->phl_txreq->mdata.rts_en = pxframe->attrib.psta->rtsen; + pxframe->phl_txreq->mdata.cts2self = pxframe->attrib.psta->cts2self; + pxframe->phl_txreq->mdata.ampdu_density = 0; + return 0; +} + +#if 0 +static s32 rtw_core_update_txattrib(_adapter *padapter, struct xmit_frame *pxframe) +{ + uint i; + struct pkt_file pktfile; + struct sta_info *psta = NULL; + struct ethhdr etherhdr; + struct sk_buff *pkt = NULL; + + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + sint res = _SUCCESS; + +#if 0//rtw_phl_tx todo def CONFIG_LPS pkt_type = _rtw_lps_chk_packet_type(pattrib); if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/ @@ -1850,57 +2295,22 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); #endif /* CONFIG_LPS */ -#ifdef CONFIG_BEAMFORMING +#if 0//rtw_phl_tx todo def CONFIG_BEAMFORMING update_attrib_txbf_info(padapter, pattrib, psta); #endif +#if 0 /* TODO:_lock */ - if (update_attrib_sec_info(padapter, pattrib, psta, eapol_type) == _FAIL) { + if (update_attrib_sec_info(padapter, pattrib, psta, NON_EAPOL) == _FAIL) { DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec); res = _FAIL; goto exit; } - - /* get ether_hdr_len */ - pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */ - - pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_LEN : WLAN_HDR_A3_LEN; - pattrib->subtype = WIFI_DATA_TYPE; - pattrib->qos_en = psta->qos_option; - pattrib->priority = 0; - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE - | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) - ) { - if (pattrib->qos_en) { - set_qos(pkt, pattrib); - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) - rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib); - #endif - } - } else { -#ifdef CONFIG_TDLS - if (pattrib->direct_link == _TRUE) { - if (pattrib->qos_en) - set_qos(pkt, pattrib); - } else #endif - { - if (pqospriv->qos_option) { - set_qos(pkt, pattrib); - if (pmlmepriv->acm_mask != 0) - pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority); - } - } - } - update_attrib_phy_info(padapter, pattrib, psta); /* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */ - - pattrib->psta = psta; /* TODO:_unlock */ #ifdef CONFIG_AUTO_AP_MODE @@ -1918,3593 +2328,5879 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr #ifdef CONFIG_WMMPS_STA update_attrib_trigger_frame_info(padapter, pattrib); -#endif /* CONFIG_WMMPS_STA */ +#endif /* CONFIG_WMMPS_STA */ /* pattrib->priority = 5; */ /* force to used VI queue, for testing */ pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; - rtw_set_tx_chksum_offload(pkt, pattrib); -exit: + pattrib->wdinfo_en = 1;/*FPGA_test YiWei need modify*/ + rtw_set_tx_chksum_offload(pkt, pattrib); +exit: return res; } +#endif +#endif -static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) +static u8 rtw_chk_htc_en(_adapter *padapter, struct sta_info *psta, struct pkt_attrib *pattrib) { - sint curfragnum, length; - u8 *pframe, *payload, mic[8]; - struct mic_data micdata; - /* struct sta_info *stainfo; */ - struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; - u8 hw_hdr_offset = 0; - sint bmcst = IS_MCAST(pattrib->ra); - /* - if(pattrib->psta) - { - stainfo = pattrib->psta; - } +#ifdef CONFIG_80211AX_HE + if (psta->hepriv.he_option == _TRUE) { + /*By test, some HE AP eapol & arp & dhcp pkt can not append ht control*/ + if ((0x888e == pattrib->ether_type) || (0x0806 == pattrib->ether_type) || (pattrib->dhcp_pkt == 1)) + return 0; + else if (rtw_get_current_tx_rate(padapter, psta) < RTW_DATA_RATE_HE_NSS1_MCS0) + return 0; else - { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); - } - - if(stainfo==NULL) - { - RTW_INFO("%s, psta==NUL\n", __func__); - return _FAIL; - } - - if(!(stainfo->state &WIFI_ASOC_STATE)) - { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state); - return _FAIL; - } - */ - - -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);; -#else -#ifdef CONFIG_TX_EARLY_MODE - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif + return rtw_he_htc_en(padapter, psta); + } #endif - if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */ - /* encode mic code */ - /* if(stainfo!= NULL) */ - { - u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - - pframe = pxmitframe->buf_addr + hw_hdr_offset; - - if (bmcst) { - if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) { - /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ - /* rtw_msleep_os(10); */ - return _FAIL; - } - /* start to calculate the mic code */ - rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); - } else { - if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) { - /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ - /* rtw_msleep_os(10); */ - return _FAIL; - } - /* start to calculate the mic code */ - rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]); - } + return 0; +} - if (pframe[1] & 1) { /* ToDS==1 */ - rtw_secmicappend(&micdata, &pframe[16], 6); /* DA */ - if (pframe[1] & 2) /* From Ds==1 */ - rtw_secmicappend(&micdata, &pframe[24], 6); - else - rtw_secmicappend(&micdata, &pframe[10], 6); - } else { /* ToDS==0 */ - rtw_secmicappend(&micdata, &pframe[4], 6); /* DA */ - if (pframe[1] & 2) /* From Ds==1 */ - rtw_secmicappend(&micdata, &pframe[16], 6); - else - rtw_secmicappend(&micdata, &pframe[10], 6); +static s32 update_attrib(_adapter *padapter, struct sk_buff *pkt, struct pkt_attrib *pattrib) +{ + uint i; + struct pkt_file pktfile; + struct sta_info *psta = NULL; + struct ethhdr etherhdr; - } + sint bmcast; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + sint res = _SUCCESS; + enum eap_type eapol_type = NON_EAPOL; +#ifdef CONFIG_LPS + u8 pkt_type = 0; +#endif - if (pattrib->qos_en) - priority[0] = (u8)pxmitframe->attrib.priority; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); + _rtw_open_pktfile(pkt, &pktfile); + i = _rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN); - rtw_secmicappend(&micdata, &priority[0], 4); + pattrib->ether_type = ntohs(etherhdr.h_proto); - payload = pframe; + if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) /* address resolve is done for ap/mesh */ + goto get_sta_info; - for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { - payload = (u8 *)RND4((SIZE_PTR)(payload)); + _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); + _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); + _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); - payload = payload + pattrib->hdrlen + pattrib->iv_len; - if ((curfragnum + 1) == pattrib->nr_frags) { - length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); - rtw_secmicappend(&micdata, payload, length); - payload = payload + length; - } else { - length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); - rtw_secmicappend(&micdata, payload, length); - payload = payload + length + pattrib->icv_len; - } + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc); + } else if (MLME_IS_STA(padapter)) { + #ifdef CONFIG_TDLS + if (rtw_check_tdls_established(padapter, pattrib) == _TRUE) + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); /* For TDLS direct link Tx, set ra to be same to dst */ + else + #endif + { + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + #ifdef CONFIG_RTW_WDS + if (adapter_use_wds(padapter) + && _rtw_memcmp(pattrib->src, pattrib->ta, ETH_ALEN) == _FALSE + ) { + pattrib->wds = 1; + if (IS_MCAST(pattrib->dst)) + rtw_tx_wds_gptr_update(padapter, pattrib->src); } - rtw_secgetmic(&micdata, &(mic[0])); - /* add mic code and add the mic code length in last_txcmdsz */ - - _rtw_memcpy(payload, &(mic[0]), 8); - pattrib->last_txcmdsz += 8; + #endif + } + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta); + } else + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); - payload = payload - pattrib->last_txcmdsz + 8; +get_sta_info: + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + psta = rtw_get_bcmc_stainfo(padapter); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + #endif + res = _FAIL; + goto exit; + } + } else { + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + #endif + res = _FAIL; + goto exit; + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & WIFI_ASOC_STATE)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link); + res = _FAIL; + goto exit; } + + #ifdef CONFIG_RTW_WDS + if (XATTRIB_GET_WDS(pattrib) && !(psta->flags & WLAN_STA_WDS)) + pattrib->wds = 0; + #endif } + if (!(psta->state & WIFI_ASOC_STATE)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); + RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != WIFI_ASOC_STATE\n", + __func__, ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr), psta->state); + res = _FAIL; + goto exit; + } - return _SUCCESS; -} + pattrib->pktlen = pktfile.pkt_len; +#ifdef CONFIG_CORE_TXSC + pattrib->frag_len = pxmitpriv->frag_len; +#endif -/*#define DBG_TX_SW_ENCRYPTOR*/ + /* TODO: 802.1Q VLAN header */ + /* TODO: IPV6 */ -static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe) -{ + if (ETH_P_IP == pattrib->ether_type) { + u8 ip[20]; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - /* struct security_priv *psecuritypriv=&padapter->securitypriv; */ + _rtw_pktfile_read(&pktfile, ip, 20); + if (GET_IPV4_IHL(ip) * 4 > 20) + _rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20); - /* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) */ - if (pattrib->bswenc) { -#ifdef DBG_TX_SW_ENCRYPTOR - RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n", - ADPT_ARG(padapter), security_type_str(pattrib->encrypt)); -#endif + pattrib->icmp_pkt = 0; + pattrib->dhcp_pkt = 0; + pattrib->hipriority_pkt = 0; - switch (pattrib->encrypt) { - case _WEP40_: - case _WEP104_: - rtw_wep_encrypt(padapter, (u8 *)pxmitframe); - break; - case _TKIP_: - rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); - break; - case _AES_: - case _CCMP_256_: - rtw_aes_encrypt(padapter, (u8 *)pxmitframe); - break; - case _GCMP_: - case _GCMP_256_: - rtw_gcmp_encrypt(padapter, (u8 *)pxmitframe); - break; -#ifdef CONFIG_WAPI_SUPPORT - case _SMS4_: - rtw_sms4_encrypt(padapter, (u8 *)pxmitframe); -#endif - default: - break; - } + if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */ + pattrib->icmp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp); - } + } else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */ + u8 udp[24]; + _rtw_pktfile_read(&pktfile, udp, 24); - return _SUCCESS; -} + if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67) + || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) + ) { + /* 67 : UDP BOOTP server, 68 : UDP BOOTP client */ + if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ + pattrib->dhcp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp); + if (0) + RTW_INFO("send DHCP packet\n"); + } + } -s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) -{ - u16 *qc; + /* WaveAgent packet, increase priority so that the system can read data in time */ + if (((GET_UDP_SIG1(udp) == 0xcc) || (GET_UDP_SIG1(udp) == 0xdd)) && + (GET_UDP_SIG2(udp) == 0xe2)) { + pattrib->hipriority_pkt = 1; + } - struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct qos_priv *pqospriv = &pmlmepriv->qospriv; - u8 qos_option = _FALSE; - sint res = _SUCCESS; - u16 *fctrl = &pwlanhdr->frame_ctl; + } else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE + ) { + u8 tcp[20]; - /* struct sta_info *psta; */ + _rtw_pktfile_read(&pktfile, tcp, 20); - /* sint bmcst = IS_MCAST(pattrib->ra); */ + if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + } + } + } else if (0x888e == pattrib->ether_type) + eapol_type = parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1); +#if defined (DBG_ARP_DUMP) || defined (DBG_IP_R_MONITOR) + else if (pattrib->ether_type == ETH_P_ARP) { + u8 arp[28] = {0}; - /* - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if(pattrib->psta != psta) - { - RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); - return; - } + _rtw_pktfile_read(&pktfile, arp, 28); + dump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1); + } +#endif - if(psta==NULL) - { - RTW_INFO("%s, psta==NUL\n", __func__); - return _FAIL; - } + if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) + rtw_mi_set_scan_deny(padapter, 3000); - if(!(psta->state &WIFI_ASOC_STATE)) - { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FAIL; - } - */ + if (MLME_IS_STA(padapter) && + pattrib->ether_type == ETH_P_ARP && + !IS_MCAST(pattrib->dst)) { + rtw_mi_set_scan_deny(padapter, 1000); + rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/ + } - _rtw_memset(hdr, 0, WLANHDR_OFFSET); +#ifdef CONFIG_LPS + pkt_type = _rtw_lps_chk_packet_type(pattrib); - set_frame_sub_type(fctrl, pattrib->subtype); + if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active); + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 0); + } else if (pkt_type == LPS_PT_ICMP) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); +#endif /* CONFIG_LPS */ - if (pattrib->subtype & WIFI_DATA_TYPE) { - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { -#ifdef CONFIG_TDLS - if (pattrib->direct_link == _TRUE) { - /* TDLS data transfer, ToDS=0, FrDs=0 */ - _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + /* TODO:_lock */ + if (update_attrib_sec_info(padapter, pattrib, psta, eapol_type) == _FAIL) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec); + res = _FAIL; + goto exit; + } - if (pattrib->qos_en) - qos_option = _TRUE; - } else -#endif /* CONFIG_TDLS */ - { - #ifdef CONFIG_RTW_WDS - if (pattrib->wds) { - SetToDs(fctrl); - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN); - } else - #endif - { - /* to_ds = 1, fr_ds = 0; */ - /* 1.Data transfer to AP */ - /* 2.Arp pkt will relayed by AP */ - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); - } + /* get ether_hdr_len */ + pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */ - if (pqospriv->qos_option) - qos_option = _TRUE; - } - } else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)) { - #ifdef CONFIG_RTW_WDS - if (pattrib->wds) { - SetToDs(fctrl); - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN); - } else - #endif - { - /* to_ds = 0, fr_ds = 1; */ - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); - } + pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_LEN : WLAN_HDR_A3_LEN; + pattrib->type = WIFI_DATA_TYPE; + pattrib->subtype = WIFI_DATA_TYPE; + pattrib->qos_en = psta->qos_option; + pattrib->priority = 0; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE + | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) + ) { + if (pattrib->qos_en) { + set_qos(pkt, pattrib); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib); + #endif + } + } else { +#ifdef CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { if (pattrib->qos_en) - qos_option = _TRUE; - } else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || - (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { - _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + set_qos(pkt, pattrib); + } else +#endif + { + if (pqospriv->qos_option) { + set_qos(pkt, pattrib); - if (pattrib->qos_en) - qos_option = _TRUE; -#ifdef CONFIG_RTW_MESH - } else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) { - rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr); - if (pattrib->qos_en) - qos_option = _TRUE; - else { - RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__); - res = _FAIL; - goto exit; + if (pmlmepriv->acm_mask != 0) + pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority); } -#endif - } else { - res = _FAIL; - goto exit; } + } - if (pattrib->mdata) - SetMData(fctrl); + pattrib->order = rtw_chk_htc_en(padapter, psta, pattrib); + if (pattrib->order) { + if (pattrib->qos_en) + pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_QOS_HTC_LEN : WLAN_HDR_A3_QOS_HTC_LEN; + else + pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_HTC_LEN : WLAN_HDR_A3_HTC_LEN; + } - if (pattrib->encrypt) - SetPrivacy(fctrl); + update_attrib_phy_info(padapter, pattrib, psta); - if (qos_option) { - qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + /* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */ - if (pattrib->priority) - SetPriority(qc, pattrib->priority); + pattrib->psta = psta; + /* TODO:_unlock */ - SetEOSP(qc, pattrib->eosp); +#ifdef CONFIG_AUTO_AP_MODE + if (psta->isrc && psta->pid > 0) + pattrib->pctrl = _TRUE; + else +#endif + pattrib->pctrl = 0; - SetAckpolicy(qc, pattrib->ack_policy); + pattrib->ack_policy = 0; - if(pattrib->amsdu) - SetAMsdu(qc, pattrib->amsdu); -#ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - /* active: don't care, light sleep: 0, deep sleep: 1*/ - set_mps_lv(qc, 0); //TBD + if (bmcast) + pattrib->rate = psta->init_rate; - /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */ - set_rspi(qc, 0); - SetEOSP(qc, 1); - - set_mctrl_present(qc, 1); - } -#endif - } - /* TODO: fill HT Control Field */ +#ifdef CONFIG_WMMPS_STA + update_attrib_trigger_frame_info(padapter, pattrib); +#endif /* CONFIG_WMMPS_STA */ - /* Update Seq Num will be handled by f/w */ - { - struct sta_info *psta; - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if (pattrib->psta != psta) { - RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); - return _FAIL; - } + /* pattrib->priority = 5; */ /* force to used VI queue, for testing */ + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; - if (psta == NULL) { - RTW_INFO("%s, psta==NUL\n", __func__); - return _FAIL; - } + pattrib->wdinfo_en = 1;/*FPGA_test YiWei need modify*/ - if (!(psta->state & WIFI_ASOC_STATE)) { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FAIL; - } + rtw_set_tx_chksum_offload(pkt, pattrib); +exit: - if (psta) { - psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; - psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; - pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; - SetSeqNum(hdr, pattrib->seqnum); + return res; +} -#ifdef CONFIG_80211N_HT -#if 0 /* move into update_attrib_phy_info(). */ - /* check if enable ampdu */ - if (pattrib->ht_en && psta->htpriv.ampdu_enable) { - if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) - pattrib->ampdu_en = _TRUE; +static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + sint curfragnum, length; + u8 *pframe, *payload, mic[8]; + struct mic_data micdata; + /* struct sta_info *stainfo; */ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; + u8 hw_hdr_offset = 0; + sint bmcst = IS_MCAST(pattrib->ra); + + /* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } + + if(stainfo==NULL) + { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(stainfo->state &WIFI_ASOC_STATE)) + { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state); + return _FAIL; + } + */ + + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);; +#else +#ifdef CONFIG_TX_EARLY_MODE + hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; +#else + hw_hdr_offset = TXDESC_OFFSET; +#endif +#endif + + if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */ + /* encode mic code */ + /* if(stainfo!= NULL) */ + { + u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + + pframe = pxmitframe->buf_addr + hw_hdr_offset; + + if (bmcst) { + if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; } + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); + } else { + if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; + } + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]); + } + + if (pframe[1] & 1) { /* ToDS==1 */ + rtw_secmicappend(&micdata, &pframe[16], 6); /* DA */ + if (pframe[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pframe[24], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + } else { /* ToDS==0 */ + rtw_secmicappend(&micdata, &pframe[4], 6); /* DA */ + if (pframe[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pframe[16], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + + } + + if (pattrib->qos_en) + priority[0] = (u8)pxmitframe->attrib.priority; + + + rtw_secmicappend(&micdata, &priority[0], 4); + + payload = pframe; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + payload = (u8 *)RND4((SIZE_PTR)(payload)); + + payload = payload + pattrib->hdrlen + pattrib->iv_len; + if ((curfragnum + 1) == pattrib->nr_frags) { + length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload, length); + payload = payload + length; + } else { + length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload, length); + payload = payload + length + pattrib->icv_len; + } + } + rtw_secgetmic(&micdata, &(mic[0])); + /* add mic code and add the mic code length in last_txcmdsz */ + + _rtw_memcpy(payload, &(mic[0]), 8); + pattrib->last_txcmdsz += 8; + + payload = payload - pattrib->last_txcmdsz + 8; + } + } + + + return _SUCCESS; +} + +/*#define DBG_TX_SW_ENCRYPTOR*/ + +static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + + if (!pattrib->bswenc) + return _SUCCESS; + +#ifdef DBG_TX_SW_ENCRYPTOR + RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n", + ADPT_ARG(padapter), security_type_str(pattrib->encrypt)); #endif - /* re-check if enable ampdu by BA_starting_seqctrl */ - if (pattrib->ampdu_en == _TRUE) { - u16 tx_seq; - tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + rtw_wep_encrypt(padapter, (u8 *)pxmitframe); + break; + case _TKIP_: + rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); + break; + case _AES_: + case _CCMP_256_: + rtw_aes_encrypt(padapter, (u8 *)pxmitframe); + break; + case _GCMP_: + case _GCMP_256_: + rtw_gcmp_encrypt(padapter, (u8 *)pxmitframe); + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + rtw_sms4_encrypt(padapter, (u8 *)pxmitframe); +#endif + default: + break; + } - /* check BA_starting_seqctrl */ - if (SN_LESS(pattrib->seqnum, tx_seq)) { - /* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */ - pattrib->ampdu_en = _FALSE;/* AGG BK */ - } else if (SN_EQUAL(pattrib->seqnum, tx_seq)) { - psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff; + return _SUCCESS; +} - pattrib->ampdu_en = _TRUE;/* AGG EN */ - } else { - /* RTW_INFO("tx ampdu over run\n"); */ - psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff; - pattrib->ampdu_en = _TRUE;/* AGG EN */ - } +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +static s32 rtw_core_xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxframe) +{ + sint curfragnum, payload_length; + u8 *pwlhdr, *payload, mic[8]; + struct mic_data micdata; + /* struct sta_info *stainfo; */ + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; + u8 hw_hdr_offset = 0; + sint bmcst = IS_MCAST(pxframe->attrib.ra); + + if (pxframe->attrib.encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */ + /* encode mic code */ + /* if(stainfo!= NULL) */ + { + u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + + pwlhdr = pxframe->wlhdr[0]; + payload = pxframe->pkt->data + pxframe->attrib.pkt_hdrlen; + payload_length = pxframe->pkt->len - pxframe->attrib.pkt_hdrlen; + if (bmcst) { + if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; } -#endif /* CONFIG_80211N_HT */ + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); + } else { + if (_rtw_memcmp(&pxframe->attrib.psta->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; + } + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, &pxframe->attrib.psta->dot11tkiptxmickey.skey[0]); } + + if (pwlhdr[1] & 1) { /* ToDS==1 */ + rtw_secmicappend(&micdata, &pwlhdr[16], 6); /* DA */ + if (pwlhdr[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pwlhdr[24], 6); + else + rtw_secmicappend(&micdata, &pwlhdr[10], 6); + } else { /* ToDS==0 */ + rtw_secmicappend(&micdata, &pwlhdr[4], 6); /* DA */ + if (pwlhdr[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pwlhdr[16], 6); + else + rtw_secmicappend(&micdata, &pwlhdr[10], 6); + + } + + if (pxframe->attrib.qos_en) + priority[0] = (u8)pxframe->attrib.qos_en; + + rtw_secmicappend(&micdata, &priority[0], 4); + + payload = (u8 *)RND4((SIZE_PTR)(payload)); + rtw_secmicappend(&micdata, payload, payload_length); + + rtw_secgetmic(&micdata, &(mic[0])); + /* add mic code and add the mic code length in last_txcmdsz */ + + _rtw_memcpy(pxframe->wltail[0]+pxframe->attrib.icv_len, &(mic[0]), 8); } + } - } else { + return _SUCCESS; +} + +/*#define DBG_TX_SW_ENCRYPTOR*/ + +static s32 rtw_core_xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxframe) +{ + if (pxframe->attrib.bswenc) { +#ifdef DBG_TX_SW_ENCRYPTOR + RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n", + ADPT_ARG(padapter), security_type_str(pxframe->attrib.encrypt)); +#endif + + switch (pxframe->attrib.encrypt) { + case _WEP40_: + case _WEP104_: + //rtw_wep_encrypt(padapter, (u8 *)pxmitframe); + break; + case _TKIP_: + //rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); + break; + case _AES_: + case _CCMP_256_: + rtw_core_aes_encrypt(padapter, (u8 *)pxframe); + break; + case _GCMP_: + case _GCMP_256_: + //rtw_gcmp_encrypt(padapter, (u8 *)pxmitframe); + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + //rtw_sms4_encrypt(padapter, (u8 *)pxmitframe); +#endif + default: + break; + } } + return _SUCCESS; +} + + +s32 rtw_core_make_wlanhdr(_adapter *padapter, u8 *hdr, struct xmit_frame *pxframe) +{ + u16 *qc; + + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 qos_option = _FALSE; + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + + _rtw_memset(hdr, 0, WLANHDR_OFFSET); + + set_frame_sub_type(fctrl, pxframe->attrib.subtype); + + if (pxframe->attrib.subtype & WIFI_DATA_TYPE) { + if (MLME_IS_STA(padapter)) { +#ifdef CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + /* TDLS data transfer, ToDS=0, FrDs=0 */ + _rtw_memcpy(pwlanhdr->addr1, pxframe->attrib.dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pxframe->attrib.src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pxframe->attrib.qos_en) + qos_option = _TRUE; + } else +#endif /* CONFIG_TDLS */ + { + /* to_ds = 1, fr_ds = 0; */ + /* 1.Data transfer to AP */ + /* 2.Arp pkt will relayed by AP */ + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pxframe->attrib.ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pxframe->attrib.dst, ETH_ALEN); + + if (pqospriv->qos_option) + qos_option = _TRUE; + } + } else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)) { + /* to_ds = 0, fr_ds = 1; */ + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pxframe->attrib.dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pxframe->attrib.src, ETH_ALEN); + + if (pxframe->attrib.qos_en) + qos_option = _TRUE; + } else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pwlanhdr->addr1, pxframe->attrib.dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pxframe->attrib.ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pxframe->attrib.qos_en) + qos_option = _TRUE; +#ifdef CONFIG_RTW_MESH + } else if (MLME_IS_STA(padapter)) { + rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr); + if (pxframe->attrib.qos_en) + qos_option = _TRUE; + else { + RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__); + res = _FAIL; + goto exit; + } +#endif + } else { + res = _FAIL; + goto exit; + } + + if (pxframe->attrib.mdata) + SetMData(fctrl); + + if (pxframe->attrib.encrypt) + SetPrivacy(fctrl); + + if (qos_option) { + qc = (unsigned short *)(hdr + pxframe->attrib.hdrlen - 2); + + if (pxframe->attrib.priority) + SetPriority(qc, pxframe->attrib.priority); + + SetEOSP(qc, pxframe->attrib.eosp); + + SetAckpolicy(qc, pxframe->attrib.ack_policy); + + if (pxframe->attrib.amsdu) + SetAMsdu(qc, pxframe->attrib.amsdu); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* active: don't care, light sleep: 0, deep sleep: 1*/ + set_mps_lv(qc, 0); //TBD + + /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */ + set_rspi(qc, 0); + SetEOSP(qc, 1); + + set_mctrl_present(qc, 1); + } +#endif + } + + /* TODO: fill HT Control Field */ + + /* Update Seq Num will be handled by f/w */ + { + struct sta_info *psta; + psta = pxframe->attrib.psta; + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if (!(psta->state & WIFI_ASOC_STATE)) { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return _FAIL; + } + + if (psta) { + psta->sta_xmitpriv.txseq_tid[pxframe->attrib.priority]++; + psta->sta_xmitpriv.txseq_tid[pxframe->attrib.priority] &= 0xFFF; + pxframe->attrib.seqnum = psta->sta_xmitpriv.txseq_tid[pxframe->attrib.priority]; + + SetSeqNum(hdr, pxframe->attrib.seqnum); + +#ifdef CONFIG_80211N_HT +#if 0 /* move into update_attrib_phy_info(). */ + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) + pattrib->ampdu_en = _TRUE; + } +#endif + /* re-check if enable ampdu by BA_starting_seqctrl */ + if (pxframe->attrib.ampdu_en == _TRUE) { + u16 tx_seq; + + tx_seq = psta->BA_starting_seqctrl[pxframe->attrib.priority & 0x0f]; + + /* check BA_starting_seqctrl */ + if (SN_LESS(pxframe->attrib.seqnum, tx_seq)) { + /* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */ + pxframe->attrib.ampdu_en = _FALSE;/* AGG BK */ + } else if (SN_EQUAL(pxframe->attrib.seqnum, tx_seq)) { + psta->BA_starting_seqctrl[pxframe->attrib.priority & 0x0f] = (tx_seq + 1) & 0xfff; + + pxframe->attrib.ampdu_en = _TRUE;/* AGG EN */ + } else { + /* RTW_INFO("tx ampdu over run\n"); */ + psta->BA_starting_seqctrl[pxframe->attrib.priority & 0x0f] = (pxframe->attrib.seqnum + 1) & 0xfff; + pxframe->attrib.ampdu_en = _TRUE;/* AGG EN */ + } + + } +#endif /* CONFIG_80211N_HT */ + } + } + + } else { + + } + +exit: + + + return res; +} + + + + + +#endif + +static void rtw_fill_htc_in_wlanhdr(_adapter *padapter, struct pkt_attrib *pattrib, u32 *phtc_buf) +{ +#ifdef CONFIG_80211AX_HE + rtw_he_fill_htc(padapter, pattrib, phtc_buf); +#endif +} + +s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib) +{ + u16 *qc; + u32 *htc = NULL; + + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 qos_option = _FALSE, htc_option = _FALSE; + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + + /* struct sta_info *psta; */ + + /* sint bmcst = IS_MCAST(pattrib->ra); */ + + + /* + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return; + } + + if(psta==NULL) + { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(psta->state &WIFI_ASOC_STATE)) + { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return _FAIL; + } + */ + +#ifdef RTW_PHL_TX + _rtw_memset(hdr, 0, pattrib->hdrlen); +#else + _rtw_memset(hdr, 0, WLANHDR_OFFSET); +#endif + + set_frame_sub_type(fctrl, pattrib->subtype); + + if (pattrib->subtype & WIFI_DATA_TYPE) { + if (MLME_IS_STA(padapter)) { +#ifdef CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + /* TDLS data transfer, ToDS=0, FrDs=0 */ + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pattrib->qos_en) + qos_option = _TRUE; + } else +#endif /* CONFIG_TDLS */ + { + #ifdef CONFIG_RTW_WDS + if (pattrib->wds) { + SetToDs(fctrl); + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN); + } else + #endif + { + /* to_ds = 1, fr_ds = 0; */ + /* 1.Data transfer to AP */ + /* 2.Arp pkt will relayed by AP */ + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + } + + if (pqospriv->qos_option) + qos_option = _TRUE; + } + } else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)) { + #ifdef CONFIG_RTW_WDS + if (pattrib->wds) { + SetToDs(fctrl); + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN); + } else + #endif + { + /* to_ds = 0, fr_ds = 1; */ + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); + } + + if (pattrib->qos_en) + qos_option = _TRUE; + } else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pattrib->qos_en) + qos_option = _TRUE; +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) { + rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr); + if (pattrib->qos_en) + qos_option = _TRUE; + else { + RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__); + res = _FAIL; + goto exit; + } +#endif + } else { + res = _FAIL; + goto exit; + } + + if (pattrib->mdata) + SetMData(fctrl); + + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if (pattrib->order) + htc_option = _TRUE; + + if (qos_option) { + qc = (unsigned short *)(hdr + (XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_LEN : WLAN_HDR_A3_LEN)); + + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + + if (pattrib->amsdu) + SetAMsdu(qc, pattrib->amsdu); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* active: don't care, light sleep: 0, deep sleep: 1*/ + set_mps_lv(qc, 0); //TBD + + /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */ + set_rspi(qc, 0); + SetEOSP(qc, 1); + + set_mctrl_present(qc, 1); + } +#endif + } + + /* TODO: fill HT Control Field */ + if (htc_option == _TRUE) { + set_htc_order_bit(fctrl); + + htc = (u32 *)(hdr + pattrib->hdrlen - 4); + rtw_fill_htc_in_wlanhdr(padapter, pattrib, htc); + } + + /* Update Seq Num will be handled by f/w */ + { + struct sta_info *psta; + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if (!(psta->state & WIFI_ASOC_STATE)) { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return _FAIL; + } + + + if (psta) { + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + + SetSeqNum(hdr, pattrib->seqnum); + +#ifdef CONFIG_80211N_HT +#if 0 /* move into update_attrib_phy_info(). */ + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) + pattrib->ampdu_en = _TRUE; + } +#endif + /* re-check if enable ampdu by BA_starting_seqctrl */ + if (pattrib->ampdu_en == _TRUE) { + u16 tx_seq; + + tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; + + /* check BA_starting_seqctrl */ + if (SN_LESS(pattrib->seqnum, tx_seq)) { + /* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */ + pattrib->ampdu_en = _FALSE;/* AGG BK */ + } else if (SN_EQUAL(pattrib->seqnum, tx_seq)) { + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff; + + pattrib->ampdu_en = _TRUE;/* AGG EN */ + } else { + /* RTW_INFO("tx ampdu over run\n"); */ + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff; + pattrib->ampdu_en = _TRUE;/* AGG EN */ + } + + } +#endif /* CONFIG_80211N_HT */ + } + } + + } else { + + } + +exit: + + + return res; +} + +s32 rtw_txframes_pending(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)); +} + +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) +{ + struct sta_info *psta; + struct tx_servq *ptxservq; + int priority = pattrib->priority; + /* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } + */ + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return 0; + } + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return 0; + } + + if (!(psta->state & WIFI_ASOC_STATE)) { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return 0; + } + + switch (priority) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + break; + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + break; + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + break; + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + break; + + } + + return ptxservq->qcnt; +} + +#ifdef CONFIG_TDLS + +int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta = NULL; + int res = _SUCCESS; + + ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst); + if (ptdls_sta == NULL) { + switch (ptxmgmt->action_code) { + case TDLS_DISCOVERY_REQUEST: + case TUNNELED_PROBE_REQ: + case TUNNELED_PROBE_RSP: + break; + default: + RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code); + res = _FAIL; + goto exit; + } + } + + switch (ptxmgmt->action_code) { + case TDLS_SETUP_REQUEST: + rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; + case TDLS_SETUP_RESPONSE: + rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; + case TDLS_SETUP_CONFIRM: + rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; + case TDLS_TEARDOWN: + rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; + case TDLS_DISCOVERY_REQUEST: + rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_PEER_TRAFFIC_INDICATION: + rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; +#ifdef CONFIG_TDLS_CH_SW + case TDLS_CHANNEL_SWITCH_REQUEST: + rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; + case TDLS_CHANNEL_SWITCH_RESPONSE: + rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; +#endif + case TDLS_PEER_TRAFFIC_RESPONSE: + rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); + break; +#ifdef CONFIG_WFD + case TUNNELED_PROBE_REQ: + rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe); + break; + case TUNNELED_PROBE_RSP: + rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe); + break; +#endif /* CONFIG_WFD */ + default: + res = _FAIL; + break; + } + +exit: + return res; +} + +s32 rtw_make_tdls_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +{ + u16 *qc; + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL, *ptdls_sta = NULL; + u8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + + + _rtw_memset(hdr, 0, WLANHDR_OFFSET); + + set_frame_sub_type(fctrl, pattrib->subtype); + + switch (ptxmgmt->action_code) { + case TDLS_SETUP_REQUEST: + case TDLS_SETUP_RESPONSE: + case TDLS_SETUP_CONFIRM: + case TDLS_PEER_TRAFFIC_INDICATION: + case TDLS_PEER_PSM_REQUEST: + case TUNNELED_PROBE_REQ: + case TUNNELED_PROBE_RSP: + case TDLS_DISCOVERY_REQUEST: + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + break; + case TDLS_CHANNEL_SWITCH_REQUEST: + case TDLS_CHANNEL_SWITCH_RESPONSE: + case TDLS_PEER_PSM_RESPONSE: + case TDLS_PEER_TRAFFIC_RESPONSE: + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + tdls_seq = 1; + break; + case TDLS_TEARDOWN: + if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) { + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + tdls_seq = 1; + } else { + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + } + break; + } + + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE) + SetPwrMgt(fctrl); + + if (pqospriv->qos_option) { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + SetAckpolicy(qc, pattrib->ack_policy); + } + + psta = pattrib->psta; + + /* 1. update seq_num per link by sta_info */ + /* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */ + if (tdls_seq == 1) { + ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); + if (ptdls_sta) { + ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; + SetSeqNum(hdr, pattrib->seqnum); + + if (pattrib->encrypt) { + pattrib->encrypt = _AES_; + pattrib->iv_len = 8; + pattrib->icv_len = 8; + pattrib->bswenc = _FALSE; + } + pattrib->mac_id = ptdls_sta->phl_sta->macid; + } else { + res = _FAIL; + goto exit; + } + } else if (psta) { + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + SetSeqNum(hdr, pattrib->seqnum); + } + + +exit: + + + return res; +} + +s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt) +{ + s32 llc_sz; + + u8 *pframe, *mem_start; + + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 *pbuf_start; + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _SUCCESS; + + + if (pattrib->psta) + psta = pattrib->psta; + else { + if (bmcst) + psta = rtw_get_bcmc_stainfo(padapter); + else + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + + if (psta == NULL) { + res = _FAIL; + goto exit; + } + + if (pxmitframe->buf_addr == NULL) { + res = _FAIL; + goto exit; + } + + pbuf_start = pxmitframe->buf_addr; + mem_start = pbuf_start + TXDESC_OFFSET; + + if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) { + res = _FAIL; + goto exit; + } + + pframe = mem_start; + pframe += pattrib->hdrlen; + + /* adding icv, if necessary... */ + if (pattrib->iv_len) { + if (psta != NULL) { + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + case _TKIP_: + if (bmcst) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + break; + case _AES_: + if (bmcst) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + break; + } + } + + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + + } + + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + + /* pattrib->pktlen will be counted in rtw_build_tdls_ies */ + pattrib->pktlen = 0; + + rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt); + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + pframe += pattrib->pktlen; + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + pattrib->nr_frags = 1; + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz + + ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen; + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + update_attrib_vcs_info(padapter, pxmitframe); + +exit: + + + return res; +} +#endif /* CONFIG_TDLS */ + +/* + * Calculate wlan 802.11 packet MAX size from pkt_attrib + * This function doesn't consider fragment case + */ +u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) +{ + u32 len = 0; + + len = pattrib->hdrlen /* WLAN Header */ + + pattrib->iv_len /* IV */ + + XATTRIB_GET_MCTRL_LEN(pattrib) + + SNAP_SIZE + sizeof(u16) /* LLC */ + + pattrib->pktlen + + (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */ + + (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */ + ; + + return len; +} + +#ifdef CONFIG_TX_AMSDU +s32 check_amsdu(struct xmit_frame *pxmitframe) +{ + struct pkt_attrib *pattrib; + struct sta_info *psta = NULL; + s32 ret = _TRUE; + + if (!pxmitframe) + ret = _FALSE; + + pattrib = &pxmitframe->attrib; + + psta = rtw_get_stainfo(&pxmitframe->padapter->stapriv, &pattrib->ra[0]); + if (psta) { + if (psta->flags & WLAN_STA_AMSDU_DISABLE) + ret =_FALSE; + } + + if (IS_MCAST(pattrib->ra)) + ret = _FALSE; + + if ((pattrib->ether_type == 0x888e) || + (pattrib->ether_type == 0x0806) || + (pattrib->ether_type == 0x88b4) || + (pattrib->dhcp_pkt == 1)) + ret = _FALSE; + + if ((pattrib->encrypt == _WEP40_) || + (pattrib->encrypt == _WEP104_) || + (pattrib->encrypt == _TKIP_)) + ret = _FALSE; + + if (!pattrib->qos_en) + ret = _FALSE; + + if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) + ret = _FALSE; + + return ret; +} + +s32 check_amsdu_tx_support(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv; + int tx_amsdu; + int tx_amsdu_rate; + int current_tx_rate; + s32 ret = _FALSE; + + pdvobjpriv = adapter_to_dvobj(padapter); + tx_amsdu = padapter->tx_amsdu; + tx_amsdu_rate = padapter->tx_amsdu_rate; + current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp; + + if (tx_amsdu == 1) + ret = _TRUE; + else if (tx_amsdu >= 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate)) + ret = _TRUE; + else + ret = _FALSE; + + return ret; +} + +s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue) +{ + + struct pkt_file pktfile; + struct pkt_attrib *pattrib; + struct sk_buff *pkt; + + struct pkt_file pktfile_queue; + struct pkt_attrib *pattrib_queue; + struct sk_buff *pkt_queue; + + s32 llc_sz, mem_sz; + + s32 padding = 0; + + u8 *pframe, *mem_start; + u8 hw_hdr_offset; + + u16 *len; + u8 *pbuf_start; + s32 res = _SUCCESS; + + if (pxmitframe->buf_addr == NULL) { + RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); + return _FAIL; + } + + + pbuf_start = pxmitframe->buf_addr; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); +#else +#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */ + hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; +#else + hw_hdr_offset = TXDESC_OFFSET; +#endif +#endif + + mem_start = pbuf_start + hw_hdr_offset; //for DMA + + pattrib = &pxmitframe->attrib; + + pattrib->amsdu = 1; + + if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { + RTW_INFO("%s: rtw_make_wlanhdr fail; drop pkt\n", __func__); + res = _FAIL; + goto exit; + } + + llc_sz = 0; + + pframe = mem_start; + + //SetMFrag(mem_start); + ClearMFrag(mem_start); + + pframe += pattrib->hdrlen; + + /* adding icv, if necessary... */ + if (pattrib->iv_len) { + update_attrib_sec_iv_info(padapter, pattrib); + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new? + + RTW_DBG("%s: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", + __func__, padapter->securitypriv.dot11PrivacyKeyIndex, + pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)); + + pframe += pattrib->iv_len; + } + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len; + + if (pxmitframe_queue) { + pattrib_queue = &pxmitframe_queue->attrib; + pkt_queue = pxmitframe_queue->pkt; + + _rtw_open_pktfile(pkt_queue, &pktfile_queue); + _rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen); + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16 *)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue); + } else + #endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ + _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16 *)pframe; + pframe += 2; + } + + llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type); + pframe += llc_sz; + + mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen); + pframe += mem_sz; + + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz); + + //calc padding + padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1)); + if (padding == 4) + padding = 0; + + //_rtw_memset(pframe,0xaa, padding); + pframe += padding; + + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ; + } + + //2nd mpdu + + pkt = pxmitframe->pkt; + _rtw_open_pktfile(pkt, &pktfile); + _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16 *)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + } else +#endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2) */ + _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16 *)pframe; + pframe += 2; + } + + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + + mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); + + pframe += mem_sz; + + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz); + + //the last ampdu has no padding + padding = 0; + + pattrib->nr_frags = 1; + + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding + + ((pattrib->bswenc) ? pattrib->icv_len : 0) ; + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { + RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + update_attrib_vcs_info(padapter, pxmitframe); + +exit: + return res; +} +#endif /* CONFIG_TX_AMSDU */ + +/* + +This sub-routine will perform all the following: + +1. remove 802.3 header. +2. create wlan_header, based on the info in pxmitframe +3. append sta's iv/ext-iv +4. append LLC +5. move frag chunk from pframe to pxmitframe->mem +6. apply sw-encrypt, if necessary. + +*/ +s32 rtw_xmitframe_coalesce(_adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pkt_file pktfile; + + s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + + SIZE_PTR addr; + + u8 *pframe, *mem_start; + u8 hw_hdr_offset; + + /* struct sta_info *psta; */ + /* struct sta_priv *pstapriv = &padapter->stapriv; */ + /* struct mlme_priv *pmlmepriv = &padapter->mlmepriv; */ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + u8 *pbuf_start; + + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _SUCCESS; + + + /* + if (pattrib->psta) + { + psta = pattrib->psta; + } else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + + if(psta==NULL) + { + + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + + if(!(psta->state &WIFI_ASOC_STATE)) + { + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return _FAIL; + } + */ + if (pxmitframe->buf_addr == NULL) { + RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); + return _FAIL; + } + + pbuf_start = pxmitframe->buf_addr; + +#if 0 +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); +#else +#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */ + hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; +#else + hw_hdr_offset = TXDESC_OFFSET; +#endif +#endif +#endif + hw_hdr_offset = rtw_hal_get_txdesc_len(GET_PHL_COM(dvobj), pattrib); /*FPGA_test*/ + + mem_start = pbuf_start + hw_hdr_offset; + + if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { + RTW_INFO("%s: rtw_make_wlanhdr fail; drop pkt\n", __func__); + res = _FAIL; + goto exit; + } + + _rtw_open_pktfile(pkt, &pktfile); + _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + + frg_inx = 0; + frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */ + + while (1) { + llc_sz = 0; + + mpdu_len = frg_len; + + pframe = mem_start; + + SetMFrag(mem_start); + + pframe += pattrib->hdrlen; + mpdu_len -= pattrib->hdrlen; + + /* adding icv, if necessary... */ + if (pattrib->iv_len) { + update_attrib_sec_iv_info(padapter, pattrib); + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + + + pframe += pattrib->iv_len; + + mpdu_len -= pattrib->iv_len; + } + + if (frg_inx == 0) { + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib); + } + #endif + + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + mpdu_len -= llc_sz; + } + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) + mpdu_len -= pattrib->icv_len; + + + if (bmcst) { + /* don't do fragment to broadcat/multicast packets */ + mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); + } else + mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); + + pframe += mem_sz; + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + frg_inx++; + + if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) { + pattrib->nr_frags = frg_inx; + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + + ((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) + + ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; + + ClearMFrag(mem_start); + + break; + } + + addr = (SIZE_PTR)(pframe); + + mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset; + _rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen); + + } + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { + RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + if (bmcst == _FALSE) + update_attrib_vcs_info(padapter, pxmitframe); + else + pattrib->vcs_mode = NONE_VCS; + +exit: + + + return res; +} + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +/* + * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action + * BIP for broadcast robust mgmt frame + */ +s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe) +{ +#define DBG_MGMT_XMIT_COALESEC_DUMP 0 +#define DBG_MGMT_XMIT_BIP_DUMP 0 +#define DBG_MGMT_XMIT_ENC_DUMP 0 + + struct pkt_file pktfile; + s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + SIZE_PTR addr; + u8 *pframe, *mem_start = NULL, *tmp_buf = NULL; + u8 hw_hdr_offset, subtype ; + u8 category = 0xFF; + struct sta_info *psta = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 *pbuf_start; + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _FAIL; + u8 *BIP_AAD = NULL; + u8 *MGMT_body = NULL; + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rtw_ieee80211_hdr *pwlanhdr; + u8 mme_cont[_MME_IE_LENGTH_ - 2]; + u8 mme_clen; + + u32 ori_len; + union pn48 *pn = NULL; + enum security_type cipher = _NO_PRIVACY_; + u8 kid; + + if (pxmitframe->buf_addr == NULL) { + RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + + mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ + + /* check if robust mgmt frame */ + if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION) + return _SUCCESS; + if (subtype == WIFI_ACTION) { + category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + if (CATEGORY_IS_NON_ROBUST(category)) + return _SUCCESS; + } + if (!bmcst) { + if (pattrib->psta) + psta = pattrib->psta; + else + pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (psta == NULL) { + RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + if (!(psta->flags & WLAN_STA_MFP)) { + /* peer is not MFP capable, no need to encrypt */ + return _SUCCESS; + } + if (psta->bpairwise_key_installed != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + } + + ori_len = BIP_AAD_SIZE + pattrib->pktlen + _MME_IE_LENGTH_; + tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); + if (BIP_AAD == NULL) + return _FAIL; + + _rtw_spinlock_bh(&padapter->security_key_mutex); + + if (bmcst) { + if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) { + /* broadcast group privacy action frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); + #endif + + if (pattrib->psta) + psta = pattrib->psta; + else + pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter); + if (psta == NULL) { + RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n" + , FUNC_ADPT_ARG(padapter)); + goto xmitframe_coalesce_fail; + } + if (padapter->securitypriv.binstallGrpkey != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); + goto xmitframe_coalesce_fail; + } + + pn = &psta->dot11txpn; + cipher = padapter->securitypriv.dot118021XGrpPrivacy; + kid = padapter->securitypriv.dot118021XGrpKeyid; + } else { + #ifdef CONFIG_IEEE80211W + /* broadcast robust mgmt frame, using BIP */ + int frame_body_len; + u8 mic[16]; + + /* IGTK key is not install ex: mesh MFP without IGTK */ + if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE) + goto xmitframe_coalesce_success; + + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) + RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_DISASSOC) + RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); + } + #endif + + /*HW encrypt need to record encrypt type*/ + pattrib->encrypt = padapter->securitypriv.dot11wCipher; + + _rtw_memset(mme_cont, 0, _MME_IE_LENGTH_ - 2); + mme_clen = padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_ ? 16 : 24; + + MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pattrib->pktlen; + + /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ + mme_cont[0] = padapter->securitypriv.dot11wBIPKeyid; + /* increase PN and apply to packet */ + padapter->securitypriv.dot11wBIPtxpn.val++; + RTW_PUT_LE64(&mme_cont[2], padapter->securitypriv.dot11wBIPtxpn.val); + + /* add MME IE with MIC all zero, MME string doesn't include element id and length */ + pframe = rtw_set_ie(pframe, _MME_IE_, mme_clen, mme_cont, &(pattrib->pktlen)); + pattrib->last_txcmdsz = pattrib->pktlen; + + if (pattrib->encrypt && + (padapter->securitypriv.sw_encrypt == _TRUE || padapter->securitypriv.hw_decrypted == _FALSE)) { + pattrib->bswenc = _TRUE; + } else { + /* currently HW only support _BIP_CMAC_128_ */ + if (pattrib->encrypt == _BIP_CMAC_128_) + pattrib->bswenc = _FALSE; + else + pattrib->bswenc = _TRUE; + } + + if (!pattrib->bswenc) { + pattrib->key_idx = padapter->securitypriv.dot11wBIPKeyid; + /*Don't need to append MIC part of MME*/ + pattrib->pktlen -= (mme_clen == 16 ? 8 : 16); + pattrib->last_txcmdsz = pattrib->pktlen; + goto xmitframe_coalesce_success; + } + + /* total frame length - header length */ + frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); + + /* conscruct AAD, copy frame control field */ + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + /* conscruct AAD, copy address 1 to address 3 */ + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + /* copy management fram body */ + _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); + + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump total packet include MME with zero MIC */ + { + int i; + printk("Total packet: "); + for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) + printk(" %02x ", BIP_AAD[i]); + printk("\n"); + } + #endif + + /* calculate mic */ + if (rtw_calculate_bip_mic(padapter->securitypriv.dot11wCipher, + (u8 *)pwlanhdr, pattrib->pktlen, + padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey, + BIP_AAD, (BIP_AAD_SIZE + frame_body_len), mic) == _FAIL) + goto xmitframe_coalesce_fail; + + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump calculated mic result */ + { + int i; + printk("Calculated mic result: "); + for (i = 0; i < 16; i++) + printk(" %02x ", mic[i]); + printk("\n"); + } + #endif + + /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ + if (padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_) + _rtw_memcpy(pframe - 8, mic, 8); + else + _rtw_memcpy(pframe - 16, mic, 16); + + #if DBG_MGMT_XMIT_BIP_DUMP + /*dump all packet after mic ok */ + { + int pp; + printk("pattrib->pktlen = %d\n", pattrib->pktlen); + for (pp = 0; pp < pattrib->pktlen; pp++) + printk(" %02x ", mem_start[pp]); + printk("\n"); + } + #endif + + #endif /* CONFIG_IEEE80211W */ + + goto xmitframe_coalesce_success; + } + } else { + /* unicast robust mgmt frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) { + RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_DISASSOC) { + RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra)); + } + #endif + + pn = &psta->dot11txpn; + cipher = psta->dot118021XPrivacy; + kid = 0; + + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey + , psta->dot118021x_UncstKey.skey + , (cipher & _SEC_TYPE_256_) ? 32 : 16); + + /* To use wrong key */ + if (pattrib->key_type == IEEE80211W_WRONG_KEY) { + RTW_INFO("use wrong key\n"); + pattrib->dot118021x_UncstKey.skey[0] = 0xff; + } + } + + #if DBG_MGMT_XMIT_ENC_DUMP + /* before encrypt dump the management packet content */ + { + int i; + printk("Management pkt: "); + for (i = 0; i < pattrib->pktlen; i++) + printk(" %02x ", pframe[i]); + printk("=======\n"); + } + #endif + + /* bakeup original management packet */ + _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); + /* move to data portion */ + pframe += pattrib->hdrlen; + + if (pattrib->key_type != IEEE80211W_NO_KEY) { + pattrib->encrypt = cipher; + pattrib->bswenc = _TRUE; + } + + /* + * 802.11w encrypted management packet must be: + * _AES_, _CCMP_256_, _GCMP_, _GCMP_256_ + */ + switch (pattrib->encrypt) { + case _AES_: + pattrib->iv_len = 8; + pattrib->icv_len = 8; + AES_IV(pattrib->iv, (*pn), kid); + break; + case _CCMP_256_: + pattrib->iv_len = 8; + pattrib->icv_len = 16; + AES_IV(pattrib->iv, (*pn), kid); + break; + case _GCMP_: + case _GCMP_256_: + pattrib->iv_len = 8; + pattrib->icv_len = 16; + GCMP_IV(pattrib->iv, (*pn), kid); + break; + default: + goto xmitframe_coalesce_fail; + } + + /* insert iv header into management frame */ + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + /* copy mgmt data portion after CCMP header */ + _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); + /* move pframe to end of mgmt pkt */ + pframe += pattrib->pktlen - pattrib->hdrlen; + /* add 8 bytes CCMP IV header to length */ + pattrib->pktlen += pattrib->iv_len; + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES IV header */ + { + int i; + printk("Management pkt + IV: "); + /* for(i=0; ipktlen; i++) */ + + printk("@@@@@@@@@@@@@\n"); + } + #endif + + if (pattrib->encrypt && + (padapter->securitypriv.sw_encrypt == _TRUE || psta->hw_decrypted == _FALSE)) { + pattrib->bswenc = _TRUE; + } else { + /* only right key can use HW encrypt */ + if (pattrib->key_type == IEEE80211W_RIGHT_KEY) + pattrib->bswenc = _FALSE; + else + pattrib->bswenc = _TRUE; + } + + /* at the moment the security CAM may be cleaned already --> use SW encryption */ + if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) + pattrib->bswenc = _TRUE; + if (!pattrib->bswenc) { + pattrib->key_idx = kid; + pattrib->last_txcmdsz = pattrib->pktlen; + SetPrivacy(mem_start); + goto xmitframe_coalesce_success; + } + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + /* add 8 bytes MIC */ + pattrib->pktlen += pattrib->icv_len; + /* set final tx command size */ + pattrib->last_txcmdsz = pattrib->pktlen; + + /* set protected bit must be beofre SW encrypt */ + SetPrivacy(mem_start); + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES header */ + { + int i; + printk("prepare to enc Management pkt + IV: "); + for (i = 0; i < pattrib->pktlen; i++) + printk(" %02x ", mem_start[i]); + printk("@@@@@@@@@@@@@\n"); + } + #endif + + /* software encrypt */ + /* move to core_wlan_sw_encrypt() because of new txreq architecture */ + +xmitframe_coalesce_success: + _rtw_spinunlock_bh(&padapter->security_key_mutex); + rtw_mfree(BIP_AAD, ori_len); + return _SUCCESS; + +xmitframe_coalesce_fail: + _rtw_spinunlock_bh(&padapter->security_key_mutex); + rtw_mfree(BIP_AAD, ori_len); + + return _FAIL; +} +#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ + +/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header + * IEEE LLC/SNAP header contains 8 octets + * First 3 octets comprise the LLC portion + * SNAP portion, 5 octets, is divided into two fields: + * Organizationally Unique Identifier(OUI), 3 octets, + * type, defined by that organization, 2 octets. + */ +s32 rtw_put_snap(u8 *data, u16 h_proto) +{ + struct ieee80211_snap_hdr *snap; + u8 *oui; + + + snap = (struct ieee80211_snap_hdr *)data; + snap->dsap = 0xaa; + snap->ssap = 0xaa; + snap->ctrl = 0x03; -exit: + if (h_proto == 0x8137 || h_proto == 0x80f3) + oui = P802_1H_OUI; + else + oui = RFC1042_OUI; + snap->oui[0] = oui[0]; + snap->oui[1] = oui[1]; + snap->oui[2] = oui[2]; - return res; -} + *(u16 *)(data + SNAP_SIZE) = htons(h_proto); -s32 rtw_txframes_pending(_adapter *padapter) -{ - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || - (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || - (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || - (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE) -#ifdef CONFIG_RTW_MGMT_QUEUE - || (_rtw_queue_empty(&pxmitpriv->mgmt_pending) == _FALSE) -#endif - ); + return SNAP_SIZE + sizeof(u16); } -s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) +void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) { - struct sta_info *psta; - struct tx_servq *ptxservq; - int priority = pattrib->priority; - /* - if(pattrib->psta) - { - psta = pattrib->psta; - } - else - { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); - } - */ - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if (pattrib->psta != psta) { - RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); - return 0; - } - if (psta == NULL) { - RTW_INFO("%s, psta==NUL\n", __func__); - return 0; - } + uint protection; + u8 *perp; + sint erp_len; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; - if (!(psta->state & WIFI_ASOC_STATE)) { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return 0; - } - switch (priority) { - case 1: - case 2: - ptxservq = &(psta->sta_xmitpriv.bk_q); - break; - case 4: - case 5: - ptxservq = &(psta->sta_xmitpriv.vi_q); + switch (pxmitpriv->vcs_setting) { + case DISABLE_VCS: + pxmitpriv->vcs = NONE_VCS; break; - case 6: - case 7: - ptxservq = &(psta->sta_xmitpriv.vo_q); + + case ENABLE_VCS: break; - case 0: - case 3: + + case AUTO_VCS: default: - ptxservq = &(psta->sta_xmitpriv.be_q); + perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); + if (perp == NULL) + pxmitpriv->vcs = NONE_VCS; + else { + protection = (*(perp + 2)) & BIT(1); + if (protection) { + if (pregistrypriv->vcs_type == RTS_CTS) + pxmitpriv->vcs = RTS_CTS; + else + pxmitpriv->vcs = CTS_TO_SELF; + } else + pxmitpriv->vcs = NONE_VCS; + } + break; } - return ptxservq->qcnt; -} -#ifdef CONFIG_TDLS +} -int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +#ifdef CONFIG_CORE_TXSC +void rtw_count_tx_stats_tx_req(_adapter *padapter, struct rtw_xmit_req *txreq, struct sta_info *psta) { - struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = NULL; - int res = _SUCCESS; - - ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst); - if (ptdls_sta == NULL) { - switch (ptxmgmt->action_code) { - case TDLS_DISCOVERY_REQUEST: - case TUNNELED_PROBE_REQ: - case TUNNELED_PROBE_RSP: + struct stainfo_stats *pstats = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u32 sz = 0; + + if (txreq->mdata.type == RTW_PHL_PKT_TYPE_DATA) { + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++; + pxmitpriv->tx_pkts++; + sz = txreq->mdata.pktlen - RTW_SZ_LLC - txreq->mdata.hdr_len; + switch (txreq->mdata.sec_type) { + case RTW_ENC_WEP104: + case RTW_ENC_WEP40: + sz -= 4; + break; + case RTW_ENC_TKIP: + sz -= 8; + break; + case RTW_ENC_CCMP: + sz -= 8; + break; + case RTW_ENC_WAPI: + sz -= 18; + break; + case RTW_ENC_GCMP256: + case RTW_ENC_GCMP: + case RTW_ENC_CCMP256: + sz -= 8; break; default: - RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code); - res = _FAIL; - goto exit; + break; + } + pxmitpriv->tx_bytes += sz; + if (psta) { + pstats = &psta->sta_stats; + pstats->tx_pkts++; + pstats->tx_bytes += sz; + #if 0 + if (is_multicast_mac_addr(psta->phl_sta->mac_addr)) + pxmitpriv->tx_mc_pkts++; + else if (is_broadcast_mac_addr(psta->phl_sta->mac_addr)) + pxmitpriv->tx_bc_pkts++; + else + pxmitpriv->tx_uc_pkts++; + #endif } } - - switch (ptxmgmt->action_code) { - case TDLS_SETUP_REQUEST: - rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; - case TDLS_SETUP_RESPONSE: - rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; - case TDLS_SETUP_CONFIRM: - rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; - case TDLS_TEARDOWN: - rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; - case TDLS_DISCOVERY_REQUEST: - rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt); - break; - case TDLS_PEER_TRAFFIC_INDICATION: - rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; -#ifdef CONFIG_TDLS_CH_SW - case TDLS_CHANNEL_SWITCH_REQUEST: - rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; - case TDLS_CHANNEL_SWITCH_RESPONSE: - rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; -#endif - case TDLS_PEER_TRAFFIC_RESPONSE: - rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); - break; -#ifdef CONFIG_WFD - case TUNNELED_PROBE_REQ: - rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe); - break; - case TUNNELED_PROBE_RSP: - rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe); - break; -#endif /* CONFIG_WFD */ - default: - res = _FAIL; - break; - } - -exit: - return res; } +#endif -s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz) { - u16 *qc; - struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct qos_priv *pqospriv = &pmlmepriv->qospriv; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL, *ptdls_sta = NULL; - u8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - sint res = _SUCCESS; - u16 *fctrl = &pwlanhdr->frame_ctl; + if (pxmitframe->xftype == RTW_TX_OS) { + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++; + pxmitpriv->tx_pkts++; + pxmitpriv->tx_bytes += sz; - _rtw_memset(hdr, 0, WLANHDR_OFFSET); + psta = pxmitframe->attrib.psta; + if (psta) { + pstats = &psta->sta_stats; - set_frame_sub_type(fctrl, pattrib->subtype); + pstats->tx_pkts++; + pstats->tx_bytes += sz; + #if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP) + if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) + traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta); + #endif /* CONFIG_LPS */ + } - switch (ptxmgmt->action_code) { - case TDLS_SETUP_REQUEST: - case TDLS_SETUP_RESPONSE: - case TDLS_SETUP_CONFIRM: - case TDLS_PEER_TRAFFIC_INDICATION: - case TDLS_PEER_PSM_REQUEST: - case TUNNELED_PROBE_REQ: - case TUNNELED_PROBE_RSP: - case TDLS_DISCOVERY_REQUEST: - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); - break; - case TDLS_CHANNEL_SWITCH_REQUEST: - case TDLS_CHANNEL_SWITCH_RESPONSE: - case TDLS_PEER_PSM_RESPONSE: - case TDLS_PEER_TRAFFIC_RESPONSE: - _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); - tdls_seq = 1; - break; - case TDLS_TEARDOWN: - if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) { - _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); - tdls_seq = 1; - } else { - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); +#ifdef CONFIG_CHECK_LEAVE_LPS + /* traffic_check_for_leave_lps(padapter, _TRUE); */ +#endif /* CONFIG_CHECK_LEAVE_LPS */ + } +} + +#if 0 /*CONFIG_CORE_XMITBUF*/ +static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_buf *pxmitbuf = NULL; + + + pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type]; + if (pxmitbuf != NULL) { + pxmitbuf->priv_data = NULL; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 0; + pxmitbuf->pg_num = 0; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; +#ifdef CONFIG_TRX_BD_ARCH + /*pxmitbuf->buf_desc = NULL;*/ +#else + pxmitbuf->desc = NULL; +#endif +#endif + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); } - break; - } + } else + RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__); - if (pattrib->encrypt) - SetPrivacy(fctrl); + return pxmitbuf; +} - if (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE) - SetPwrMgt(fctrl); +struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_frame *pcmdframe; + struct xmit_buf *pxmitbuf; - if (pqospriv->qos_option) { - qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); - if (pattrib->priority) - SetPriority(qc, pattrib->priority); - SetAckpolicy(qc, pattrib->ack_policy); + pcmdframe = rtw_alloc_xmitframe(pxmitpriv); + if (pcmdframe == NULL) { + RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__); + return NULL; } - psta = pattrib->psta; + pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type); + if (pxmitbuf == NULL) { + RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__); + rtw_free_xmitframe(pxmitpriv, pcmdframe); + return NULL; + } - /* 1. update seq_num per link by sta_info */ - /* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */ - if (tdls_seq == 1) { - ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); - if (ptdls_sta) { - ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; - ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; - pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; - SetSeqNum(hdr, pattrib->seqnum); + pcmdframe->frame_tag = MGNT_FRAMETAG; - if (pattrib->encrypt) { - pattrib->encrypt = _AES_; - pattrib->iv_len = 8; - pattrib->icv_len = 8; - pattrib->bswenc = _FALSE; - } - pattrib->mac_id = ptdls_sta->cmn.mac_id; - } else { - res = _FAIL; - goto exit; - } - } else if (psta) { - psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; - psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; - pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; - SetSeqNum(hdr, pattrib->seqnum); - } + pcmdframe->pxmitbuf = pxmitbuf; + + pcmdframe->buf_addr = pxmitbuf->pbuf; + /* initial memory to zero */ + _rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ); -exit: + pxmitbuf->priv_data = pcmdframe; + return pcmdframe; - return res; } -s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt) +struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) { - s32 llc_sz; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + unsigned long sp_flags; - u8 *pframe, *mem_start; + _rtw_spinlock_irq(&pfree_queue->lock, &sp_flags); - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - u8 *pbuf_start; - s32 bmcst = IS_MCAST(pattrib->ra); - s32 res = _SUCCESS; + if (_rtw_queue_empty(pfree_queue) == _TRUE) + pxmitbuf = NULL; + else { + phead = get_list_head(pfree_queue); - if (pattrib->psta) - psta = pattrib->psta; - else { - if (bmcst) - psta = rtw_get_bcmc_stainfo(padapter); - else - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - } + plist = get_next(phead); - if (psta == NULL) { - res = _FAIL; - goto exit; - } + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); - if (pxmitframe->buf_addr == NULL) { - res = _FAIL; - goto exit; + rtw_list_delete(&(pxmitbuf->list)); } - pbuf_start = pxmitframe->buf_addr; - mem_start = pbuf_start + TXDESC_OFFSET; + if (pxmitbuf != NULL) { + pxmitpriv->free_xmit_extbuf_cnt--; +#ifdef DBG_XMIT_BUF_EXT + RTW_INFO("DBG_XMIT_BUF_EXT ALLOC no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); +#endif - if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) { - res = _FAIL; - goto exit; - } - pframe = mem_start; - pframe += pattrib->hdrlen; + pxmitbuf->priv_data = NULL; - /* adding icv, if necessary... */ - if (pattrib->iv_len) { - if (psta != NULL) { - switch (pattrib->encrypt) { - case _WEP40_: - case _WEP104_: - WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - break; - case _TKIP_: - if (bmcst) - TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - TKIP_IV(pattrib->iv, psta->dot11txpn, 0); - break; - case _AES_: - if (bmcst) - AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - AES_IV(pattrib->iv, psta->dot11txpn, 0); - break; - } - } +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 1; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; +#ifdef CONFIG_TRX_BD_ARCH + /*pxmitbuf->buf_desc = NULL;*/ +#else + pxmitbuf->desc = NULL; +#endif +#endif - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); - pframe += pattrib->iv_len; + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } } - llc_sz = rtw_put_snap(pframe, pattrib->ether_type); - pframe += llc_sz; + _rtw_spinunlock_irq(&pfree_queue->lock, &sp_flags); - /* pattrib->pktlen will be counted in rtw_build_tdls_ies */ - pattrib->pktlen = 0; - rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt); + return pxmitbuf; +} - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - pframe += pattrib->pktlen; - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } +s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + unsigned long sp_flags; - pattrib->nr_frags = 1; - pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz + - ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen; + if (pxmitbuf == NULL) + return _FAIL; - if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - res = _FAIL; - goto exit; - } + _rtw_spinlock_irq(&pfree_queue->lock, &sp_flags); - xmitframe_swencrypt(padapter, pxmitframe); + rtw_list_delete(&pxmitbuf->list); - update_attrib_vcs_info(padapter, pxmitframe); + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); + pxmitpriv->free_xmit_extbuf_cnt++; +#ifdef DBG_XMIT_BUF_EXT + RTW_INFO("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); +#endif -exit: + _rtw_spinunlock_irq(&pfree_queue->lock, &sp_flags); - return res; + return _SUCCESS; } -#endif /* CONFIG_TDLS */ -/* - * Calculate wlan 802.11 packet MAX size from pkt_attrib - * This function doesn't consider fragment case - */ -u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) +struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) { - u32 len = 0; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + unsigned long sp_flags; + + /* RTW_INFO("+rtw_alloc_xmitbuf\n"); */ + + _rtw_spinlock_irq(&pfree_xmitbuf_queue->lock, &sp_flags); + + if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) + pxmitbuf = NULL; + else { + + phead = get_list_head(pfree_xmitbuf_queue); + + plist = get_next(phead); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + rtw_list_delete(&(pxmitbuf->list)); + } + + if (pxmitbuf != NULL) { + pxmitpriv->free_xmitbuf_cnt--; +#ifdef DBG_XMIT_BUF + RTW_INFO("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); +#endif + /* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ + + pxmitbuf->priv_data = NULL; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 0; + pxmitbuf->pg_num = 0; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; +#ifdef CONFIG_TRX_BD_ARCH + /*pxmitbuf->buf_desc = NULL;*/ +#else + pxmitbuf->desc = NULL; +#endif +#endif + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + } +#ifdef DBG_XMIT_BUF + else + RTW_INFO("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n"); +#endif - len = pattrib->hdrlen /* WLAN Header */ - + pattrib->iv_len /* IV */ - + XATTRIB_GET_MCTRL_LEN(pattrib) - + SNAP_SIZE + sizeof(u16) /* LLC */ - + pattrib->pktlen - + (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */ - + (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */ - ; + _rtw_spinunlock_irq(&pfree_xmitbuf_queue->lock, &sp_flags); - return len; + + return pxmitbuf; } -#ifdef CONFIG_TX_AMSDU -s32 check_amsdu(struct xmit_frame *pxmitframe) +s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) { - struct pkt_attrib *pattrib; - struct sta_info *psta = NULL; - s32 ret = _TRUE; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + unsigned long sp_flags; - if (!pxmitframe) - ret = _FALSE; + /* RTW_INFO("+rtw_free_xmitbuf\n"); */ - pattrib = &pxmitframe->attrib; + if (pxmitbuf == NULL) + return _FAIL; - psta = rtw_get_stainfo(&pxmitframe->padapter->stapriv, &pattrib->ra[0]); - if (psta) { - if (psta->flags & WLAN_STA_AMSDU_DISABLE) - ret =_FALSE; + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE); } - if (IS_MCAST(pattrib->ra)) - ret = _FALSE; - - if ((pattrib->ether_type == 0x888e) || - (pattrib->ether_type == 0x0806) || - (pattrib->ether_type == 0x88b4) || - (pattrib->dhcp_pkt == 1)) - ret = _FALSE; - - if ((pattrib->encrypt == _WEP40_) || - (pattrib->encrypt == _WEP104_) || - (pattrib->encrypt == _TKIP_)) - ret = _FALSE; - - if (!pattrib->qos_en) - ret = _FALSE; - if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) - ret = _FALSE; + if (pxmitbuf->buf_tag == XMITBUF_CMD) { + } else if (pxmitbuf->buf_tag == XMITBUF_MGNT) + rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); + else { + _rtw_spinlock_irq(&pfree_xmitbuf_queue->lock, &sp_flags); - return ret; -} + rtw_list_delete(&pxmitbuf->list); -s32 check_amsdu_tx_support(_adapter *padapter) -{ - struct dvobj_priv *pdvobjpriv; - int tx_amsdu; - int tx_amsdu_rate; - int current_tx_rate; - s32 ret = _FALSE; + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); - pdvobjpriv = adapter_to_dvobj(padapter); - tx_amsdu = padapter->tx_amsdu; - tx_amsdu_rate = padapter->tx_amsdu_rate; - current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp; + pxmitpriv->free_xmitbuf_cnt++; + /* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ +#ifdef DBG_XMIT_BUF + RTW_INFO("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); +#endif + _rtw_spinunlock_irq(&pfree_xmitbuf_queue->lock, &sp_flags); + } - if (tx_amsdu == 1) - ret = _TRUE; - else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate)) - ret = _TRUE; - else - ret = _FALSE; - return ret; + return _SUCCESS; } +#endif -s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue) +void rtw_init_xmitframe(struct xmit_frame *pxframe) { + if (pxframe != NULL) { /* default value setting */ + #if 0 /*CONFIG_CORE_XMITBUF*/ + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + #endif - struct pkt_file pktfile; - struct pkt_attrib *pattrib; - _pkt *pkt; + _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); + /* pxframe->attrib.psta = NULL; */ - struct pkt_file pktfile_queue; - struct pkt_attrib *pattrib_queue; - _pkt *pkt_queue; + pxframe->frame_tag = DATA_FRAMETAG; - s32 llc_sz, mem_sz; +#ifdef CONFIG_USB_HCI + pxframe->pkt = NULL; +#ifdef USB_PACKET_OFFSET_SZ + pxframe->pkt_offset = (PACKET_OFFSET_SZ / 8); +#else + pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */ +#endif - s32 padding = 0; +#ifdef CONFIG_USB_TX_AGGREGATION + pxframe->agg_num = 1; +#endif - u8 *pframe, *mem_start; - u8 hw_hdr_offset; +#endif /* #ifdef CONFIG_USB_HCI */ - u16* len; - u8 *pbuf_start; - s32 res = _SUCCESS; +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxframe->pg_num = 1; + pxframe->agg_num = 1; +#endif - if (pxmitframe->buf_addr == NULL) { - RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); - return _FAIL; +#ifdef CONFIG_XMIT_ACK + pxframe->ack_report = 0; +#endif + pxframe->txfree_cnt = 0; } +} +/* +Calling context: +1. OS_TXENTRY +2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) - pbuf_start = pxmitframe->buf_addr; - -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */ - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif +If we turn on USE_RXTHREAD, then, no need for critical section. +Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... - mem_start = pbuf_start + hw_hdr_offset; //for DMA +Must be very very cautious... - pattrib = &pxmitframe->attrib; +*/ - pattrib->amsdu = 1; +#ifdef RTW_PHL_TX +void core_tx_init_xmitframe(struct xmit_frame *pxframe) +{ + if (!pxframe) + return; + #if 0 /*CONFIG_CORE_XMITBUF*/ + pxframe->pxmitbuf = NULL; + #endif + _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); + /* TXREQ_QMGT */ + pxframe->ptxreq_buf = NULL; + pxframe->phl_txreq = NULL; - if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { - RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); - res = _FAIL; - goto exit; - } + pxframe->txreq_cnt = 0; + pxframe->txfree_cnt = 0; +} - llc_sz = 0; +s32 core_tx_alloc_xmitframe(_adapter *padapter, struct xmit_frame **pxmitframe, u16 os_qid) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxframe = NULL; + _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; + _list *plist, *phead; - pframe = mem_start; + PHLTX_LOG; - //SetMFrag(mem_start); - ClearMFrag(mem_start); + _rtw_spinlock_bh(&pfree_xmit_queue->lock); - pframe += pattrib->hdrlen; + if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { + _rtw_spinunlock_bh(&pfree_xmit_queue->lock); + return FAIL; + } else { + phead = get_list_head(pfree_xmit_queue); - /* adding icv, if necessary... */ - if (pattrib->iv_len) { - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new? + plist = get_next(phead); - RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", - padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)); + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - pframe += pattrib->iv_len; + rtw_list_delete(&pxframe->list); + pxmitpriv->free_xmitframe_cnt--; + pxframe->os_qid = os_qid; } - pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len; - - if(pxmitframe_queue) - { - pattrib_queue = &pxmitframe_queue->attrib; - pkt_queue = pxmitframe_queue->pkt; + _rtw_spinunlock_bh(&pfree_xmit_queue->lock); + rtw_os_check_stop_queue(pxmitpriv->adapter, os_qid); + core_tx_init_xmitframe(pxframe); - _rtw_open_pktfile(pkt_queue, &pktfile_queue); - _rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen); + *pxmitframe = pxframe; + return SUCCESS; +} - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - /* mDA(6), mSA(6), len(2), mctrl */ - _rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN); - pframe += ETH_ALEN; - _rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN); - pframe += ETH_ALEN; - len = (u16*)pframe; - pframe += 2; - rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe); - pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue); - } else - #endif - { - /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ - _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); - pframe += ETH_ALEN; - _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); - pframe += ETH_ALEN; - len = (u16*)pframe; - pframe += 2; - } +s32 core_tx_free_xmitframe(_adapter *padapter, struct xmit_frame *pxframe) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _queue *queue = NULL; + /* TXREQ_QMGT */ + struct xmit_txreq_buf *ptxreq_buf = NULL; + int i; + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; - llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type); - pframe += llc_sz; + PHLTX_LOG; - mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen); - pframe += mem_sz; + if (pxframe == NULL) + goto exit; - *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz); + /* TXREQ_QMGT */ + ptxreq_buf = pxframe->ptxreq_buf; - //calc padding - padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1)); - if(padding == 4) - padding = 0; + pxframe->txfree_cnt++; - //_rtw_memset(pframe,0xaa, padding); - pframe += padding; + /* ?? shall detail check, like free 1 2 3, not free 2 2 3 */ + /* ?? rtw_alloc_xmitframe_once case, seems no one use*/ - pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ; - } + if (pxframe->txfree_cnt < pxframe->txreq_cnt) + goto exit; - //2nd mpdu + #if 0 /*CONFIG_CORE_XMITBUF*/ + if (pxframe->pxmitbuf) + rtw_free_xmitbuf(pxmitpriv, pxframe->pxmitbuf); + #endif - pkt = pxmitframe->pkt; - _rtw_open_pktfile(pkt, &pktfile); - _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + for (i = 0; i < pxframe->txreq_cnt; i++) { + if (!pxframe->buf_need_free) + break; + if (!(pxframe->buf_need_free & BIT(i))) + continue; + pxframe->buf_need_free &= ~BIT(i); -#ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - /* mDA(6), mSA(6), len(2), mctrl */ - _rtw_memcpy(pframe, pattrib->mda, ETH_ALEN); - pframe += ETH_ALEN; - _rtw_memcpy(pframe, pattrib->msa, ETH_ALEN); - pframe += ETH_ALEN; - len = (u16*)pframe; - pframe += 2; - rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); - pframe += XATTRIB_GET_MCTRL_LEN(pattrib); - } else -#endif - { - /* 802.3 MAC Header DA(6) SA(6) Len(2) */ - _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); - pframe += ETH_ALEN; - _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); - pframe += ETH_ALEN; - len = (u16*)pframe; - pframe += 2; + txreq = &pxframe->phl_txreq[i]; + rtw_warn_on(txreq->pkt_cnt != 1); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + if (pkt_list->vir_addr && pkt_list->length) + rtw_mfree(pkt_list->vir_addr, pkt_list->length); } - llc_sz = rtw_put_snap(pframe, pattrib->ether_type); - pframe += llc_sz; - - mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); + if (ptxreq_buf) { + queue = &padapter->free_txreq_queue; + _rtw_spinlock_bh(&queue->lock); - pframe += mem_sz; + rtw_list_delete(&ptxreq_buf->list); + rtw_list_insert_tail(&ptxreq_buf->list, get_list_head(queue)); - *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz); + padapter->free_txreq_cnt++; + _rtw_spinunlock_bh(&queue->lock); + } else { + if (pxframe->ext_tag == 0) + ;//printk("%s:tx recyele: ptxreq_buf=NULL\n", __FUNCTION__); + } - //the last ampdu has no padding - padding = 0; + rtw_os_xmit_complete(padapter, pxframe); - pattrib->nr_frags = 1; + if (pxframe->ext_tag == 0) + queue = &pxmitpriv->free_xmit_queue; + else if (pxframe->ext_tag == 1) + queue = &pxmitpriv->free_xframe_ext_queue; + else + rtw_warn_on(1); - pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding + - ((pattrib->bswenc) ? pattrib->icv_len : 0) ; + _rtw_spinlock_bh(&queue->lock); - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } + rtw_list_delete(&pxframe->list); + rtw_list_insert_tail(&pxframe->list, get_list_head(queue)); - if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); - res = _FAIL; - goto exit; - } + if (pxframe->ext_tag == 0) + pxmitpriv->free_xmitframe_cnt++; + else if (pxframe->ext_tag == 1) + pxmitpriv->free_xframe_ext_cnt++; - xmitframe_swencrypt(padapter, pxmitframe); + _rtw_spinunlock_bh(&queue->lock); - update_attrib_vcs_info(padapter, pxmitframe); + if (queue == &pxmitpriv->free_xmit_queue) + rtw_os_check_wakup_queue(padapter, pxframe->os_qid); exit: - return res; + return _SUCCESS; } -#endif /* CONFIG_TX_AMSDU */ -/* +#endif -This sub-routine will perform all the following: +struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid)/* (_queue *pfree_xmit_queue) */ +{ + /* + Please remember to use all the osdep_service api, + and lock/unlock or _enter/_exit critical to protect + pfree_xmit_queue + */ -1. remove 802.3 header. -2. create wlan_header, based on the info in pxmitframe -3. append sta's iv/ext-iv -4. append LLC -5. move frag chunk from pframe to pxmitframe->mem -6. apply sw-encrypt, if necessary. + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; -*/ -s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) -{ - struct pkt_file pktfile; - s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + _rtw_spinlock_bh(&pfree_xmit_queue->lock); - SIZE_PTR addr; + if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { + pxframe = NULL; + } else { + phead = get_list_head(pfree_xmit_queue); - u8 *pframe, *mem_start; - u8 hw_hdr_offset; + plist = get_next(phead); - /* struct sta_info *psta; */ - /* struct sta_priv *pstapriv = &padapter->stapriv; */ - /* struct mlme_priv *pmlmepriv = &padapter->mlmepriv; */ - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - struct pkt_attrib *pattrib = &pxmitframe->attrib; + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xmitframe_cnt--; + pxframe->os_qid = os_qid; + } - u8 *pbuf_start; + _rtw_spinunlock_bh(&pfree_xmit_queue->lock); - s32 bmcst = IS_MCAST(pattrib->ra); - s32 res = _SUCCESS; + if (pxframe) + rtw_os_check_stop_queue(pxmitpriv->adapter, os_qid); + rtw_init_xmitframe(pxframe); - /* - if (pattrib->psta) - { - psta = pattrib->psta; - } else - { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - } - if(psta==NULL) - { + return pxframe; +} - RTW_INFO("%s, psta==NUL\n", __func__); - return _FAIL; - } +struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *queue = &pxmitpriv->free_xframe_ext_queue; - if(!(psta->state &WIFI_ASOC_STATE)) - { - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FAIL; - } - */ - if (pxmitframe->buf_addr == NULL) { - RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); - return _FAIL; + _rtw_spinlock_bh(&queue->lock); + + if (_rtw_queue_empty(queue) == _TRUE) { + pxframe = NULL; + } else { + phead = get_list_head(queue); + plist = get_next(phead); + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xframe_ext_cnt--; } - pbuf_start = pxmitframe->buf_addr; + _rtw_spinunlock_bh(&queue->lock); -#ifdef CONFIG_USB_TX_AGGREGATION - hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); -#else -#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */ - hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; -#else - hw_hdr_offset = TXDESC_OFFSET; -#endif -#endif + rtw_init_xmitframe(pxframe); - mem_start = pbuf_start + hw_hdr_offset; - if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { - RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); - res = _FAIL; + return pxframe; +} + +struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pxframe = NULL; + u8 *alloc_addr; + + alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4); + + if (alloc_addr == NULL) goto exit; - } - _rtw_open_pktfile(pkt, &pktfile); - _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4); + pxframe->alloc_addr = alloc_addr; - frg_inx = 0; - frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */ + pxframe->padapter = pxmitpriv->adapter; + pxframe->frame_tag = NULL_FRAMETAG; - while (1) { - llc_sz = 0; + pxframe->pkt = NULL; + #if 0 /*CONFIG_CORE_XMITBUF*/ + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + #endif - mpdu_len = frg_len; + rtw_init_xmitframe(pxframe); - pframe = mem_start; + RTW_INFO("################## %s ##################\n", __func__); - SetMFrag(mem_start); +exit: + return pxframe; +} - pframe += pattrib->hdrlen; - mpdu_len -= pattrib->hdrlen; +s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) +{ + _queue *queue = NULL; + _adapter *padapter = pxmitpriv->adapter; + struct sk_buff *pndis_pkt = NULL; - /* adding icv, if necessary... */ - if (pattrib->iv_len) { -#if 0 - /* if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) */ - /* psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); */ - /* else */ - /* psta = rtw_get_stainfo(pstapriv, pattrib->ra); */ - - if (psta != NULL) { - switch (pattrib->encrypt) { - case _WEP40_: - case _WEP104_: - WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - break; - case _TKIP_: - if (bmcst) - TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - TKIP_IV(pattrib->iv, psta->dot11txpn, 0); - break; - case _AES_: - if (bmcst) - AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - AES_IV(pattrib->iv, psta->dot11txpn, 0); - break; -#ifdef CONFIG_WAPI_SUPPORT - case _SMS4_: - rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv); - break; -#endif - } - } -#endif - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + if (pxmitframe == NULL) { + goto exit; + } - pframe += pattrib->iv_len; + if (pxmitframe->pkt) { + pndis_pkt = pxmitframe->pkt; + pxmitframe->pkt = NULL; + } - mpdu_len -= pattrib->iv_len; - } + if (pxmitframe->alloc_addr) { + RTW_INFO("################## %s with alloc_addr ##################\n", __func__); + rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4); + goto check_pkt_complete; + } - if (frg_inx == 0) { - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) { - rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); - pframe += XATTRIB_GET_MCTRL_LEN(pattrib); - mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib); - } - #endif + if (pxmitframe->ext_tag == 0) + queue = &pxmitpriv->free_xmit_queue; + else if (pxmitframe->ext_tag == 1) + queue = &pxmitpriv->free_xframe_ext_queue; + else + rtw_warn_on(1); - llc_sz = rtw_put_snap(pframe, pattrib->ether_type); - pframe += llc_sz; - mpdu_len -= llc_sz; - } + _rtw_spinlock_bh(&queue->lock); - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) - mpdu_len -= pattrib->icv_len; + rtw_list_delete(&pxmitframe->list); + rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); + if (pxmitframe->ext_tag == 0) { + pxmitpriv->free_xmitframe_cnt++; + } else if (pxmitframe->ext_tag == 1) { + pxmitpriv->free_xframe_ext_cnt++; + } else { + } + _rtw_spinunlock_bh(&queue->lock); + if (queue == &pxmitpriv->free_xmit_queue) + rtw_os_check_wakup_queue(padapter, pxmitframe->os_qid); - if (bmcst) { - /* don't do fragment to broadcat/multicast packets */ - mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); - } else - mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); +check_pkt_complete: - pframe += mem_sz; + if (pndis_pkt) + rtw_os_pkt_complete(padapter, pndis_pkt); - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } +exit: - frg_inx++; - if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) { - pattrib->nr_frags = frg_inx; + return _SUCCESS; +} - pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + - ((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) + - ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; +void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) +{ + _list *plist, *phead; + struct xmit_frame *pxmitframe; - ClearMFrag(mem_start); - break; - } + _rtw_spinlock_bh(&(pframequeue->lock)); - addr = (SIZE_PTR)(pframe); + phead = get_list_head(pframequeue); + plist = get_next(phead); - mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset; - _rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { - } + pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); - res = _FAIL; - goto exit; - } + plist = get_next(plist); - xmitframe_swencrypt(padapter, pxmitframe); + rtw_free_xmitframe(pxmitpriv, pxmitframe); - if (bmcst == _FALSE) - update_attrib_vcs_info(padapter, pxmitframe); - else - pattrib->vcs_mode = NONE_VCS; + } + _rtw_spinunlock_bh(&(pframequeue->lock)); -exit: +} +s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue); + if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) { + /* pxmitframe->pkt = NULL; */ + return _FAIL; + } - return res; + return _SUCCESS; } -#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) -/* - * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action - * BIP for broadcast robust mgmt frame - */ -s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) +static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) { -#define DBG_MGMT_XMIT_COALESEC_DUMP 0 -#define DBG_MGMT_XMIT_BIP_DUMP 0 -#define DBG_MGMT_XMIT_ENC_DUMP 0 + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; - struct pkt_file pktfile; - s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; - SIZE_PTR addr; - u8 *pframe, *mem_start = NULL, *tmp_buf = NULL; - u8 hw_hdr_offset, subtype ; - u8 category = 0xFF; - struct sta_info *psta = NULL; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - u8 *pbuf_start; - s32 bmcst = IS_MCAST(pattrib->ra); - s32 res = _FAIL; - u8 *BIP_AAD = NULL; - u8 *MGMT_body = NULL; + xmitframe_phead = get_list_head(pframe_queue); + xmitframe_plist = get_next(xmitframe_phead); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct rtw_ieee80211_hdr *pwlanhdr; - u8 mme_cont[_MME_IE_LENGTH_ - 2]; - u8 mme_clen; + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - _irqL irqL; - u32 ori_len; - union pn48 *pn = NULL; - enum security_type cipher = _NO_PRIVACY_; - u8 kid; + /* xmitframe_plist = get_next(xmitframe_plist); */ - if (pxmitframe->buf_addr == NULL) { - RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n" - , FUNC_ADPT_ARG(padapter)); - return _FAIL; - } + /*#ifdef RTK_DMP_PLATFORM + #ifdef CONFIG_USB_TX_AGGREGATION + if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2)) + { + pxmitframe = NULL; - mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ + rtw_tasklet_schedule(&pxmitpriv->xmit_tasklet); - /* check if robust mgmt frame */ - if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION) - return _SUCCESS; - if (subtype == WIFI_ACTION) { - category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); - if (CATEGORY_IS_NON_ROBUST(category)) - return _SUCCESS; - } - if (!bmcst) { - if (pattrib->psta) - psta = pattrib->psta; - else - pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if (psta == NULL) { - RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter)); - return _FAIL; - } - if (!(psta->flags & WLAN_STA_MFP)) { - /* peer is not MFP capable, no need to encrypt */ - return _SUCCESS; - } - if (psta->bpairwise_key_installed != _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n" - , FUNC_ADPT_ARG(padapter)); - return _FAIL; - } - } + break; + } + #endif + #endif*/ + rtw_list_delete(&pxmitframe->list); - ori_len = BIP_AAD_SIZE + pattrib->pktlen + _MME_IE_LENGTH_; - tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); - if (BIP_AAD == NULL) - return _FAIL; + ptxservq->qcnt--; - _enter_critical_bh(&padapter->security_key_mutex, &irqL); + /* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */ - if (bmcst) { - if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) { - /* broadcast group privacy action frame */ - #if DBG_MGMT_XMIT_COALESEC_DUMP - RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n" - , FUNC_ADPT_ARG(padapter), category); - #endif + /* ptxservq->qcnt--; */ - if (pattrib->psta) - psta = pattrib->psta; - else - pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter); - if (psta == NULL) { - RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n" - , FUNC_ADPT_ARG(padapter)); - goto xmitframe_coalesce_fail; - } - if (padapter->securitypriv.binstallGrpkey != _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n" - , FUNC_ADPT_ARG(padapter)); - goto xmitframe_coalesce_fail; - } + break; - pn = &psta->dot11txpn; - cipher = padapter->securitypriv.dot118021XGrpPrivacy; - kid = padapter->securitypriv.dot118021XGrpKeyid; - } else { - #ifdef CONFIG_IEEE80211W - /* broadcast robust mgmt frame, using BIP */ - int frame_body_len; - u8 mic[16]; + /* pxmitframe = NULL; */ - /* IGTK key is not install ex: mesh MFP without IGTK */ - if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE) - goto xmitframe_coalesce_success; + } - #if DBG_MGMT_XMIT_COALESEC_DUMP - if (subtype == WIFI_DEAUTH) - RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter)); - else if (subtype == WIFI_DISASSOC) - RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter)); - else if (subtype == WIFI_ACTION) { - RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n" - , FUNC_ADPT_ARG(padapter), category); - } - #endif + return pxmitframe; +} - _rtw_memset(mme_cont, 0, _MME_IE_LENGTH_ - 2); - mme_clen = padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_ ? 16 : 24; +static struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) +{ + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; - MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pattrib->pktlen; + xmitframe_phead = get_list_head(pframe_queue); + xmitframe_plist = get_next(xmitframe_phead); - /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ - mme_cont[0] = padapter->securitypriv.dot11wBIPKeyid; - /* increase PN and apply to packet */ - padapter->securitypriv.dot11wBIPtxpn.val++; - RTW_PUT_LE64(&mme_cont[2], padapter->securitypriv.dot11wBIPtxpn.val); + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + break; + } - /* add MME IE with MIC all zero, MME string doesn't include element id and length */ - pframe = rtw_set_ie(pframe, _MME_IE_ , mme_clen , mme_cont, &(pattrib->pktlen)); - pattrib->last_txcmdsz = pattrib->pktlen; - /* total frame length - header length */ - frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); + return pxmitframe; +} - /* conscruct AAD, copy frame control field */ - _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); - ClearRetry(BIP_AAD); - ClearPwrMgt(BIP_AAD); - ClearMData(BIP_AAD); - /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, GetAddr1Ptr((u8 *)pwlanhdr), 18); - /* copy management fram body */ - _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); +struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame) +{ + _list *sta_plist, *sta_phead; + struct hw_xmit *phwxmit_i = pxmitpriv->hwxmits; + sint entry = pxmitpriv->hwxmit_entry; - #if DBG_MGMT_XMIT_BIP_DUMP - /* dump total packet include MME with zero MIC */ - { - int i; - printk("Total packet: "); - for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) - printk(" %02x ", BIP_AAD[i]); - printk("\n"); - } - #endif + struct hw_xmit *phwxmit; + struct tx_servq *ptxservq = NULL; + _queue *pframe_queue = NULL; + struct xmit_frame *pxmitframe = NULL; + _adapter *padapter = pxmitpriv->adapter; + int i, inx[4]; - /* calculate mic */ - if (rtw_calculate_bip_mic(padapter->securitypriv.dot11wCipher, - (u8 *)pwlanhdr, pattrib->pktlen, - padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey, - BIP_AAD, (BIP_AAD_SIZE + frame_body_len), mic) == _FAIL) - goto xmitframe_coalesce_fail; + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; - #if DBG_MGMT_XMIT_BIP_DUMP - /* dump calculated mic result */ - { - int i; - printk("Calculated mic result: "); - for (i = 0; i < 16; i++) - printk(" %02x ", mic[i]); - printk("\n"); - } - #endif + *num_frame = 0; - /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ - if (padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_) - _rtw_memcpy(pframe - 8, mic, 8); - else - _rtw_memcpy(pframe - 16, mic, 16); + _rtw_spinlock_bh(&pxmitpriv->lock); - #if DBG_MGMT_XMIT_BIP_DUMP - /*dump all packet after mic ok */ - { - int pp; - printk("pattrib->pktlen = %d\n", pattrib->pktlen); - for(pp=0;pp< pattrib->pktlen; pp++) - printk(" %02x ", mem_start[pp]); - printk("\n"); - } - #endif + for (i = 0; i < entry; i++) { + phwxmit = phwxmit_i + inx[i]; + + sta_phead = get_list_head(phwxmit->sta_queue); + sta_plist = get_next(sta_phead); - #endif /* CONFIG_IEEE80211W */ + while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { - goto xmitframe_coalesce_success; + ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); + pframe_queue = &ptxservq->sta_pending; + + if (ptxservq->qcnt) { + *num_frame = ptxservq->qcnt; + pxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); + goto exit; + } + sta_plist = get_next(sta_plist); } } - else { - /* unicast robust mgmt frame */ - #if DBG_MGMT_XMIT_COALESEC_DUMP - if (subtype == WIFI_DEAUTH) { - RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); - } else if (subtype == WIFI_DISASSOC) { - RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); - } else if (subtype == WIFI_ACTION) { - RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra)); - } - #endif - pn = &psta->dot11txpn; - cipher = psta->dot118021XPrivacy; - kid = 0; +exit: - _rtw_memcpy(pattrib->dot118021x_UncstKey.skey - , psta->dot118021x_UncstKey.skey - , (cipher & _SEC_TYPE_256_) ? 32 : 16); + _rtw_spinunlock_bh(&pxmitpriv->lock); - /* To use wrong key */ - if (pattrib->key_type == IEEE80211W_WRONG_KEY) { - RTW_INFO("use wrong key\n"); - pattrib->dot118021x_UncstKey.skey[0] = 0xff; - } - } + return pxmitframe; +} - #if DBG_MGMT_XMIT_ENC_DUMP - /* before encrypt dump the management packet content */ - { - int i; - printk("Management pkt: "); - for(i=0; ipktlen; i++) - printk(" %02x ", pframe[i]); - printk("=======\n"); - } - #endif - /* bakeup original management packet */ - _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); - /* move to data portion */ - pframe += pattrib->hdrlen; +struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) +{ + _list *sta_plist, *sta_phead; + struct hw_xmit *phwxmit; + struct tx_servq *ptxservq = NULL; + _queue *pframe_queue = NULL; + struct xmit_frame *pxmitframe = NULL; + _adapter *padapter = pxmitpriv->adapter; + struct registry_priv *pregpriv = &padapter->registrypriv; + int i, inx[4]; - if (pattrib->key_type != IEEE80211W_NO_KEY) { - pattrib->encrypt = cipher; - pattrib->bswenc = _TRUE; - } + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; - /* - * 802.11w encrypted management packet must be: - * _AES_, _CCMP_256_, _GCMP_, _GCMP_256_ - */ - switch (pattrib->encrypt) { - case _AES_: - pattrib->iv_len = 8; - pattrib->icv_len = 8; - AES_IV(pattrib->iv, (*pn), kid); - break; - case _CCMP_256_: - pattrib->iv_len = 8; - pattrib->icv_len = 16; - AES_IV(pattrib->iv, (*pn), kid); - break; - case _GCMP_: - case _GCMP_256_: - pattrib->iv_len = 8; - pattrib->icv_len = 16; - GCMP_IV(pattrib->iv, (*pn), kid); - break; - default: - goto xmitframe_coalesce_fail; + if (pregpriv->wifi_spec == 1) { + int j; +#if 0 + if (flags < XMIT_QUEUE_ENTRY) { + /* priority exchange according to the completed xmitbuf flags. */ + inx[flags] = 0; + inx[0] = flags; + } +#endif + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) + for (j = 0; j < 4; j++) + inx[j] = pxmitpriv->wmm_para_seq[j]; +#endif } - /* insert iv header into management frame */ - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); - pframe += pattrib->iv_len; - /* copy mgmt data portion after CCMP header */ - _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); - /* move pframe to end of mgmt pkt */ - pframe += pattrib->pktlen - pattrib->hdrlen; - /* add 8 bytes CCMP IV header to length */ - pattrib->pktlen += pattrib->iv_len; + _rtw_spinlock_bh(&pxmitpriv->lock); - #if DBG_MGMT_XMIT_ENC_DUMP - /* dump management packet include AES IV header */ - { - int i; - printk("Management pkt + IV: "); - /* for(i=0; ipktlen; i++) */ + for (i = 0; i < entry; i++) { + phwxmit = phwxmit_i + inx[i]; - printk("@@@@@@@@@@@@@\n"); - } - #endif + /* _rtw_spinlock_irq(&phwxmit->sta_queue->lock, &sp_flags); */ - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } - /* add 8 bytes MIC */ - pattrib->pktlen += pattrib->icv_len; - /* set final tx command size */ - pattrib->last_txcmdsz = pattrib->pktlen; + sta_phead = get_list_head(phwxmit->sta_queue); + sta_plist = get_next(sta_phead); - /* set protected bit must be beofre SW encrypt */ - SetPrivacy(mem_start); + while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { - #if DBG_MGMT_XMIT_ENC_DUMP - /* dump management packet include AES header */ - { - int i; - printk("prepare to enc Management pkt + IV: "); - for (i = 0; i < pattrib->pktlen; i++) - printk(" %02x ", mem_start[i]); - printk("@@@@@@@@@@@@@\n"); - } - #endif + ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); - /* software encrypt */ - xmitframe_swencrypt(padapter, pxmitframe); + pframe_queue = &ptxservq->sta_pending; -xmitframe_coalesce_success: - _exit_critical_bh(&padapter->security_key_mutex, &irqL); - rtw_mfree(BIP_AAD, ori_len); - return _SUCCESS; + pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); -xmitframe_coalesce_fail: - _exit_critical_bh(&padapter->security_key_mutex, &irqL); - rtw_mfree(BIP_AAD, ori_len); + if (pxmitframe) { + phwxmit->accnt--; - return _FAIL; -} -#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ + /* Remove sta node when there is no pending packets. */ + if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */ + rtw_list_delete(&ptxservq->tx_pending); -/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header - * IEEE LLC/SNAP header contains 8 octets - * First 3 octets comprise the LLC portion - * SNAP portion, 5 octets, is divided into two fields: - * Organizationally Unique Identifier(OUI), 3 octets, - * type, defined by that organization, 2 octets. - */ -s32 rtw_put_snap(u8 *data, u16 h_proto) -{ - struct ieee80211_snap_hdr *snap; - u8 *oui; + /* _rtw_spinunlock_irq(&phwxmit->sta_queue->lock, sp_flags); */ + goto exit; + } - snap = (struct ieee80211_snap_hdr *)data; - snap->dsap = 0xaa; - snap->ssap = 0xaa; - snap->ctrl = 0x03; + sta_plist = get_next(sta_plist); - if (h_proto == 0x8137 || h_proto == 0x80f3) - oui = P802_1H_OUI; - else - oui = RFC1042_OUI; + } - snap->oui[0] = oui[0]; - snap->oui[1] = oui[1]; - snap->oui[2] = oui[2]; + /* _rtw_spinunlock_irq(&phwxmit->sta_queue->lock, sp_flags); */ - *(u16 *)(data + SNAP_SIZE) = htons(h_proto); + } + +exit: + _rtw_spinunlock_bh(&pxmitpriv->lock); - return SNAP_SIZE + sizeof(u16); + return pxmitframe; } -void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) +#if 1 +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) { + struct tx_servq *ptxservq = NULL; - uint protection; - u8 *perp; - sint erp_len; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct registry_priv *pregistrypriv = &padapter->registrypriv; + switch (up) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + *(ac) = 3; + break; - switch (pxmitpriv->vcs_setting) { - case DISABLE_VCS: - pxmitpriv->vcs = NONE_VCS; + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + *(ac) = 1; break; - case ENABLE_VCS: + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + *(ac) = 0; break; - case AUTO_VCS: + case 0: + case 3: default: - perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); - if (perp == NULL) - pxmitpriv->vcs = NONE_VCS; - else { - protection = (*(perp + 2)) & BIT(1); - if (protection) { - if (pregistrypriv->vcs_type == RTS_CTS) - pxmitpriv->vcs = RTS_CTS; - else - pxmitpriv->vcs = CTS_TO_SELF; - } else - pxmitpriv->vcs = NONE_VCS; - } - + ptxservq = &(psta->sta_xmitpriv.be_q); + *(ac) = 2; break; } + return ptxservq; } +#else +__inline static struct tx_servq *rtw_get_sta_pending +(_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up) { + struct tx_servq *ptxservq; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; -void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz) -{ - struct sta_info *psta = NULL; - struct stainfo_stats *pstats = NULL; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - u8 pkt_num = 1; - - if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { -#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pkt_num = pxmitframe->agg_num; -#endif - pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num; - pxmitpriv->tx_pkts += pkt_num; +#ifdef CONFIG_RTL8711 - pxmitpriv->tx_bytes += sz; + if (IS_MCAST(psta->phl_sta->mac_addr)) { + ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */ + *ppstapending = &padapter->xmitpriv.bm_pending; + } else +#endif + { + switch (up) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + *ppstapending = &padapter->xmitpriv.bk_pending; + (phwxmits + 3)->accnt++; + break; - psta = pxmitframe->attrib.psta; - if (psta) { - pstats = &psta->sta_stats; + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + *ppstapending = &padapter->xmitpriv.vi_pending; + (phwxmits + 1)->accnt++; + break; + + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + *ppstapending = &padapter->xmitpriv.vo_pending; + (phwxmits + 0)->accnt++; + break; - pstats->tx_pkts += pkt_num; + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + *ppstapending = &padapter->xmitpriv.be_pending; + (phwxmits + 2)->accnt++; + break; - pstats->tx_bytes += sz; - #if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP) - if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) - traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta); - #endif /* CONFIG_LPS */ } -#ifdef CONFIG_CHECK_LEAVE_LPS - /* traffic_check_for_leave_lps(padapter, _TRUE); */ -#endif /* CONFIG_CHECK_LEAVE_LPS */ - } + + + return ptxservq; } +#endif -static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type) +/* + * Will enqueue pxmitframe to the proper queue, + * and indicate it to xx_pending list..... + */ +s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) { - struct xmit_buf *pxmitbuf = NULL; - + u8 ac_index; + struct sta_info *psta; + struct tx_servq *ptxservq; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + sint res = _SUCCESS; - pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type]; - if (pxmitbuf != NULL) { - pxmitbuf->priv_data = NULL; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pxmitbuf->len = 0; - pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; - pxmitbuf->agg_num = 0; - pxmitbuf->pg_num = 0; -#endif -#ifdef CONFIG_PCI_HCI - pxmitbuf->len = 0; -#ifdef CONFIG_TRX_BD_ARCH - /*pxmitbuf->buf_desc = NULL;*/ -#else - pxmitbuf->desc = NULL; -#endif -#endif + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); - if (pxmitbuf->sctx) { - RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + /* + if (pattrib->psta) { + psta = pattrib->psta; + } else { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(pstapriv, pattrib->ra); } - } else - RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__); - - return pxmitbuf; -} + */ -struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type) -{ - struct xmit_frame *pcmdframe; - struct xmit_buf *pxmitbuf; + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta); + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } - pcmdframe = rtw_alloc_xmitframe(pxmitpriv, 0); - if (pcmdframe == NULL) { - RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__); - return NULL; + if (psta == NULL) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); + res = _FAIL; + RTW_INFO("rtw_xmit_classifier: psta == NULL\n"); + goto exit; } - pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type); - if (pxmitbuf == NULL) { - RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__); - rtw_free_xmitframe(pxmitpriv, pcmdframe); - return NULL; + if (!(psta->state & WIFI_ASOC_STATE)) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink); + RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); + return _FAIL; } - pcmdframe->frame_tag = MGNT_FRAMETAG; + ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); - pcmdframe->pxmitbuf = pxmitbuf; + /* _rtw_spinlock_irq(&pstapending->lock, &flags); */ - pcmdframe->buf_addr = pxmitbuf->pbuf; + if (rtw_is_list_empty(&ptxservq->tx_pending)) + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); - /* initial memory to zero */ - _rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ); + /* _rtw_spinlock_irq(&ptxservq->sta_pending.lock, &sp_flags); */ - pxmitbuf->priv_data = pcmdframe; + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); + ptxservq->qcnt++; + phwxmits[ac_index].accnt++; - return pcmdframe; + /* _rtw_spinunlock_irq(&ptxservq->sta_pending.lock, &sp_flags); */ + + /* _rtw_spinunlock_irq(&pstapending->lock, &flags); */ + +exit: + + return res; } -struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) +void rtw_alloc_hwxmits(_adapter *padapter) { - _irqL irqL; - struct xmit_buf *pxmitbuf = NULL; - _list *plist, *phead; - _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; - _enter_critical(&pfree_queue->lock, &irqL); + pxmitpriv->hwxmits = NULL; - if (_rtw_queue_empty(pfree_queue) == _TRUE) - pxmitbuf = NULL; - else { + pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry); - phead = get_list_head(pfree_queue); + if (pxmitpriv->hwxmits == NULL) { + RTW_INFO("alloc hwxmits fail!...\n"); + return; + } - plist = get_next(phead); + hwxmits = pxmitpriv->hwxmits; - pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + if (pxmitpriv->hwxmit_entry == 5) { + /* pxmitpriv->bmc_txqueue.head = 0; */ + /* hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; */ + hwxmits[0] .sta_queue = &pxmitpriv->bm_pending; - rtw_list_delete(&(pxmitbuf->list)); - } + /* pxmitpriv->vo_txqueue.head = 0; */ + /* hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; */ + hwxmits[1] .sta_queue = &pxmitpriv->vo_pending; - if (pxmitbuf != NULL) { - pxmitpriv->free_xmit_extbuf_cnt--; -#ifdef DBG_XMIT_BUF_EXT - RTW_INFO("DBG_XMIT_BUF_EXT ALLOC no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); -#endif + /* pxmitpriv->vi_txqueue.head = 0; */ + /* hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; */ + hwxmits[2] .sta_queue = &pxmitpriv->vi_pending; + /* pxmitpriv->bk_txqueue.head = 0; */ + /* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */ + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; - pxmitbuf->priv_data = NULL; + /* pxmitpriv->be_txqueue.head = 0; */ + /* hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; */ + hwxmits[4] .sta_queue = &pxmitpriv->be_pending; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pxmitbuf->len = 0; - pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; - pxmitbuf->agg_num = 1; -#endif -#ifdef CONFIG_PCI_HCI - pxmitbuf->len = 0; -#ifdef CONFIG_TRX_BD_ARCH - /*pxmitbuf->buf_desc = NULL;*/ -#else - pxmitbuf->desc = NULL; -#endif -#endif + } else if (pxmitpriv->hwxmit_entry == 4) { - if (pxmitbuf->sctx) { - RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); - } + /* pxmitpriv->vo_txqueue.head = 0; */ + /* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */ + hwxmits[0] .sta_queue = &pxmitpriv->vo_pending; - } + /* pxmitpriv->vi_txqueue.head = 0; */ + /* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */ + hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; + + /* pxmitpriv->be_txqueue.head = 0; */ + /* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */ + hwxmits[2] .sta_queue = &pxmitpriv->be_pending; - _exit_critical(&pfree_queue->lock, &irqL); + /* pxmitpriv->bk_txqueue.head = 0; */ + /* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */ + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; + } else { + + + } - return pxmitbuf; } -s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +void rtw_free_hwxmits(_adapter *padapter) { - _irqL irqL; - _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; - + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - if (pxmitbuf == NULL) - return _FAIL; + hwxmits = pxmitpriv->hwxmits; + if (hwxmits) + rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry)); +} - _enter_critical(&pfree_queue->lock, &irqL); +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) +{ + sint i; + for (i = 0; i < entry; i++, phwxmit++) { + /* _rtw_spinlock_init(&phwxmit->xmit_lock); */ + /* _rtw_init_listhead(&phwxmit->pending); */ + /* phwxmit->txcmdcnt = 0; */ + phwxmit->accnt = 0; + } +} - rtw_list_delete(&pxmitbuf->list); +#ifdef CONFIG_BR_EXT +int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) +{ + struct sk_buff *skb = *pskb; + /* if(MLME_IS_STA(adapter) */ + { + void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); + int res, is_vlan_tag = 0, i, do_nat25 = 1; + unsigned short vlan_hdr = 0; + void *br_port = NULL; - rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); - pxmitpriv->free_xmit_extbuf_cnt++; -#ifdef DBG_XMIT_BUF_EXT - RTW_INFO("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmit_extbuf_cnt); -#endif + /* mac_clone_handle_frame(priv, skb); */ - _exit_critical(&pfree_queue->lock, &irqL); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; +#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); +#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + _rtw_spinlock_bh(&padapter->br_ext_lock); + if (!(skb->data[0] & 1) && + br_port && + _rtw_memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && + *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) && + *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) && + !_rtw_memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { + _rtw_memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + padapter->scdb_entry->ageing_timer = jiffies; + _rtw_spinunlock_bh(&padapter->br_ext_lock); + } else + /* if (!priv->pmib->ethBrExtInfo.nat25_disable) */ + { + /* if (priv->dev->br_port && + * !_rtw_memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */ +#if 1 + if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); + skb_pull(skb, 4); + } + /* if SA == br_mac && skb== IP => copy SIP to br_ip ?? why */ + if (!_rtw_memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && + (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP))) + _rtw_memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); + if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) { + if (_rtw_memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) { + void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); - return _SUCCESS; -} + padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, + skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12); + if (padapter->scdb_entry != NULL) { + _rtw_memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN); + _rtw_memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } + } else { + if (padapter->scdb_entry) { + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } else { + _rtw_memset(padapter->scdb_mac, 0, MACADDRLEN); + _rtw_memset(padapter->scdb_ip, 0, 4); + } + } + } + _rtw_spinunlock_bh(&padapter->br_ext_lock); +#endif /* 1 */ + if (do_nat25) { + int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); + if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { + struct sk_buff *newskb; -struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) -{ - _irqL irqL; - struct xmit_buf *pxmitbuf = NULL; - _list *plist, *phead; - _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + if (is_vlan_tag) { + skb_push(skb, 4); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); + *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; + } + newskb = rtw_skb_copy(skb); + if (newskb == NULL) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n"); + /* goto stop_proc; */ + return -1; + } + rtw_skb_free(skb); - /* RTW_INFO("+rtw_alloc_xmitbuf\n"); */ + *pskb = skb = newskb; + if (is_vlan_tag) { + vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); + skb_pull(skb, 4); + } + } - _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); + if (skb_is_nonlinear(skb)) + DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); - if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) - pxmitbuf = NULL; - else { - phead = get_list_head(pfree_xmitbuf_queue); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + res = skb_linearize(skb, GFP_ATOMIC); +#else /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */ + res = skb_linearize(skb); +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */ + if (res < 0) { + DEBUG_ERR("TX DROP: skb_linearize fail!\n"); + /* goto free_and_stop; */ + return -1; + } - plist = get_next(phead); + res = nat25_db_handle(padapter, skb, NAT25_INSERT); + if (res < 0) { + if (res == -2) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); + /* goto free_and_stop; */ + return -1; - pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + } + /* we just print warning message and let it go */ + /* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */ + /* return -1; */ /* return -1 will cause system crash on 2011/08/30! */ + return 0; + } + } - rtw_list_delete(&(pxmitbuf->list)); - } + _rtw_memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); - if (pxmitbuf != NULL) { - pxmitpriv->free_xmitbuf_cnt--; -#ifdef DBG_XMIT_BUF - RTW_INFO("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); -#endif - /* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ + dhcp_flag_bcast(padapter, skb); - pxmitbuf->priv_data = NULL; + if (is_vlan_tag) { + skb_push(skb, 4); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); + *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; + } + } +#if 0 + else { + if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) + is_vlan_tag = 1; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pxmitbuf->len = 0; - pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; - pxmitbuf->agg_num = 0; - pxmitbuf->pg_num = 0; -#endif -#ifdef CONFIG_PCI_HCI - pxmitbuf->len = 0; -#ifdef CONFIG_TRX_BD_ARCH - /*pxmitbuf->buf_desc = NULL;*/ -#else - pxmitbuf->desc = NULL; -#endif -#endif + if (is_vlan_tag) { + if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)) + _rtw_memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + } else { + if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)) + _rtw_memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + } + } +#endif /* 0 */ - if (pxmitbuf->sctx) { - RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + /* check if SA is equal to our MAC */ + if (_rtw_memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", + skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]); + /* goto free_and_stop; */ + return -1; } } -#ifdef DBG_XMIT_BUF - else - RTW_INFO("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n"); -#endif + return 0; +} +#endif /* CONFIG_BR_EXT */ - _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); +static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 qsel; + qsel = pattrib->priority; - return pxmitbuf; + /* high priority packet */ + if (pattrib->hipriority_pkt) { + pattrib->qsel = rtw_hal_get_qsel(padapter, QSLT_VO_ID); + pattrib->priority = rtw_hal_get_qsel(padapter, QSLT_VO_ID); + } } -s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) +s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) { - _irqL irqL; - _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; - - - /* RTW_INFO("+rtw_free_xmitbuf\n"); */ + u16 frame_ctl; + struct ieee80211_radiotap_header rtap_hdr; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct pkt_file pktfile; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + struct xmit_frame *pmgntframe; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + unsigned char *pframe; + u8 dummybuf[32]; + int len = skb->len, rtap_len; - if (pxmitbuf == NULL) - return _FAIL; - if (pxmitbuf->sctx) { - RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE); - } + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); - if (pxmitbuf->buf_tag == XMITBUF_CMD) { - } else if (pxmitbuf->buf_tag == XMITBUF_MGNT) - rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); - else { - _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); +#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) + goto fail; - rtw_list_delete(&pxmitbuf->list); + _rtw_open_pktfile((struct sk_buff *)skb, &pktfile); + _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header)); + rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr)); + if (unlikely(rtap_hdr.it_version)) + goto fail; - rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); + if (unlikely(skb->len < rtap_len)) + goto fail; - pxmitpriv->free_xmitbuf_cnt++; - /* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ -#ifdef DBG_XMIT_BUF - RTW_INFO("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmitbuf_cnt); + if (rtap_len != 12) { + RTW_INFO("radiotap len (should be 14): %d\n", rtap_len); + goto fail; + } + _rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header)); + len = len - rtap_len; #endif - _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtw_udelay_os(500); + goto fail; } + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; +// _rtw_memcpy(pframe, (void *)checking, len); + _rtw_pktfile_read(&pktfile, pframe, len); - return _SUCCESS; -} - -void rtw_init_xmitframe(struct xmit_frame *pxframe) -{ - if (pxframe != NULL) { /* default value setting */ - pxframe->buf_addr = NULL; - pxframe->pxmitbuf = NULL; - - _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); - /* pxframe->attrib.psta = NULL; */ - - pxframe->frame_tag = DATA_FRAMETAG; -#ifdef CONFIG_USB_HCI - pxframe->pkt = NULL; -#ifdef USB_PACKET_OFFSET_SZ - pxframe->pkt_offset = (PACKET_OFFSET_SZ / 8); -#else - pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */ -#endif + /* Check DATA/MGNT frames */ + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl); + if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { -#ifdef CONFIG_USB_TX_AGGREGATION - pxframe->agg_num = 1; -#endif + pattrib = &pmgntframe->attrib; + update_monitor_frame_attrib(padapter, pattrib); -#endif /* #ifdef CONFIG_USB_HCI */ + if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) + pattrib->rate = MGN_24M; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - pxframe->pg_num = 1; - pxframe->agg_num = 1; -#endif + } else { -#ifdef CONFIG_XMIT_ACK - pxframe->ack_report = 0; -#endif + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); } -} - -/* -Calling context: -1. OS_TXENTRY -2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) + pattrib->retry_ctrl = _FALSE; + pattrib->pktlen = len; + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + pattrib->last_txcmdsz = pattrib->pktlen; -If we turn on USE_RXTHREAD, then, no need for critical section. -Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... + dump_mgntframe(padapter, pmgntframe); -Must be very very cautious... +fail: + rtw_skb_free(skb); + return 0; +} +#endif -*/ -struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid) +/* + * + * Return _TRUE when frame has been put to queue, otherwise return _FALSE. + */ +static u8 xmit_enqueue(_adapter *a, struct xmit_frame *frame) { - /* - Please remember to use all the osdep_service api, - and lock/unlock or _enter/_exit critical to protect - pfree_xmit_queue - */ - - _irqL irqL; - struct xmit_frame *pxframe = NULL; - _list *plist, *phead; - _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; + struct sta_info *sta = NULL; + struct pkt_attrib *attrib = NULL; + _list *head; + u8 ret = _TRUE; - _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); - if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { - pxframe = NULL; - } else { - phead = get_list_head(pfree_xmit_queue); + attrib = &frame->attrib; + sta = attrib->psta; + if (!sta) + return _FALSE; - plist = get_next(phead); + _rtw_spinlock_bh(&sta->tx_queue.lock); - pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + head = get_list_head(&sta->tx_queue); - rtw_list_delete(&(pxframe->list)); - pxmitpriv->free_xmitframe_cnt--; - pxframe->os_qid = os_qid; + if ((rtw_is_list_empty(head) == _TRUE) && (!sta->tx_q_enable)) { + ret = _FALSE; + goto exit; } - _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); - - if (pxframe) - rtw_os_check_stop_queue(pxmitpriv->adapter, os_qid); - - rtw_init_xmitframe(pxframe); + rtw_list_insert_tail(&frame->list, head); + RTW_INFO(FUNC_ADPT_FMT ": en-queue tx pkt for macid=%d\n", + FUNC_ADPT_ARG(a), sta->phl_sta->macid); +exit: + _rtw_spinunlock_bh(&sta->tx_queue.lock); - return pxframe; + return ret; } -struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) +static void xmit_dequeue(struct sta_info *sta) { - _irqL irqL; - struct xmit_frame *pxframe = NULL; - _list *plist, *phead; - _queue *queue = &pxmitpriv->free_xframe_ext_queue; + _adapter *a; + _list *head, *list; + struct xmit_frame *frame; - _enter_critical_bh(&queue->lock, &irqL); + a = sta->padapter; - if (_rtw_queue_empty(queue) == _TRUE) { - pxframe = NULL; - } else { - phead = get_list_head(queue); - plist = get_next(phead); - pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + _rtw_spinlock_bh(&sta->tx_queue.lock); - rtw_list_delete(&(pxframe->list)); - pxmitpriv->free_xframe_ext_cnt--; - } + head = get_list_head(&sta->tx_queue); - _exit_critical_bh(&queue->lock, &irqL); + do { + if (rtw_is_list_empty(head) == _TRUE) + break; - rtw_init_xmitframe(pxframe); + list = get_next(head); + rtw_list_delete(list); + frame = LIST_CONTAINOR(list, struct xmit_frame, list); + RTW_INFO(FUNC_ADPT_FMT ": de-queue tx frame of macid=%d\n", + FUNC_ADPT_ARG(a), sta->phl_sta->macid); + /*rtw_hal_xmit(a, frame);*/ + rtw_intf_data_xmit(a, frame); + } while (1); - return pxframe; + _rtw_spinunlock_bh(&sta->tx_queue.lock); } -struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv) +void rtw_xmit_dequeue_callback(_workitem *work) { - struct xmit_frame *pxframe = NULL; - u8 *alloc_addr; + struct sta_info *sta; - alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4); - if (alloc_addr == NULL) - goto exit; + sta = container_of(work, struct sta_info, tx_q_work); + xmit_dequeue(sta); +} - pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4); - pxframe->alloc_addr = alloc_addr; +void rtw_xmit_queue_set(struct sta_info *sta) +{ + _rtw_spinlock_bh(&sta->tx_queue.lock); - pxframe->padapter = pxmitpriv->adapter; - pxframe->frame_tag = NULL_FRAMETAG; + if (sta->tx_q_enable) { + RTW_WARN(FUNC_ADPT_FMT ": duplicated set!\n", + FUNC_ADPT_ARG(sta->padapter)); + goto exit; + } + sta->tx_q_enable = 1; + RTW_INFO(FUNC_ADPT_FMT ": enable queue TX for macid=%d\n", + FUNC_ADPT_ARG(sta->padapter), sta->phl_sta->macid); - pxframe->pkt = NULL; +exit: + _rtw_spinunlock_bh(&sta->tx_queue.lock); +} - pxframe->buf_addr = NULL; - pxframe->pxmitbuf = NULL; +void rtw_xmit_queue_clear(struct sta_info *sta) +{ + _rtw_spinlock_bh(&sta->tx_queue.lock); - rtw_init_xmitframe(pxframe); + if (!sta->tx_q_enable) { + RTW_WARN(FUNC_ADPT_FMT ": tx queue for macid=%d " + "not be enabled!\n", + FUNC_ADPT_ARG(sta->padapter), sta->phl_sta->macid); + goto exit; + } - RTW_INFO("################## %s ##################\n", __func__); + sta->tx_q_enable = 0; + RTW_INFO(FUNC_ADPT_FMT ": disable queue TX for macid=%d\n", + FUNC_ADPT_ARG(sta->padapter), sta->phl_sta->macid); + + _set_workitem(&sta->tx_q_work); exit: - return pxframe; + _rtw_spinunlock_bh(&sta->tx_queue.lock); } -s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) +/* + * The main transmit(tx) entry post handle + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, + struct sk_buff *pkt) { - _irqL irqL; - _queue *queue = NULL; - _adapter *padapter = pxmitpriv->adapter; - _pkt *pndis_pkt = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 res; + res = update_attrib(padapter, pkt, &pxmitframe->attrib); - if (pxmitframe == NULL) { - goto exit; +#ifdef CONFIG_WAPI_SUPPORT + if (pxmitframe->attrib.ether_type != 0x88B4) { + if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { + WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); + res = _FAIL; + } } - - if (pxmitframe->pkt) { - pndis_pkt = pxmitframe->pkt; - pxmitframe->pkt = NULL; +#endif + if (res == _FAIL) { + /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ +#ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); +#endif + rtw_free_xmitframe(pxmitpriv, pxmitframe); + return -1; } + pxmitframe->pkt = pkt; - if (pxmitframe->alloc_addr) { - RTW_INFO("################## %s with alloc_addr ##################\n", __func__); - rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4); - goto check_pkt_complete; + rtw_led_tx_control(padapter, pxmitframe->attrib.dst); + + do_queue_select(padapter, &pxmitframe->attrib); + +#ifdef CONFIG_AP_MODE + _rtw_spinlock_bh(&pxmitpriv->lock); + if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { + _rtw_spinunlock_bh(&pxmitpriv->lock); + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); + return 1; } + _rtw_spinunlock_bh(&pxmitpriv->lock); +#endif - if (pxmitframe->ext_tag == 0) - queue = &pxmitpriv->free_xmit_queue; - else if (pxmitframe->ext_tag == 1) - queue = &pxmitpriv->free_xframe_ext_queue; - else - rtw_warn_on(1); + /*if (xmit_enqueue(padapter, pxmitframe) == _TRUE)*/ + /* return 1;*/ - _enter_critical_bh(&queue->lock, &irqL); + /* pre_xmitframe */ + /*if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)*/ + if (rtw_intf_data_xmit(padapter, pxmitframe) == _FALSE) + return 1; - rtw_list_delete(&pxmitframe->list); - rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); - if (pxmitframe->ext_tag == 0) { - pxmitpriv->free_xmitframe_cnt++; - } else if (pxmitframe->ext_tag == 1) { - pxmitpriv->free_xframe_ext_cnt++; - } else { - } + return 0; +} - _exit_critical_bh(&queue->lock, &irqL); +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit(_adapter *padapter, struct sk_buff **ppkt, u16 os_qid) +{ + static systime start = 0; + static u32 drop_cnt = 0; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxmitframe = NULL; + s32 res; - if (queue == &pxmitpriv->free_xmit_queue) - rtw_os_check_wakup_queue(padapter, pxmitframe->os_qid); + DBG_COUNTER(padapter->tx_logs.core_tx); -check_pkt_complete: + if (IS_CH_WAITING(adapter_to_rfctl(padapter))) + return -1; - if (pndis_pkt) - rtw_os_pkt_complete(padapter, pndis_pkt); + if (rtw_linked_check(padapter) == _FALSE) + return -1; -exit: + if (start == 0) + start = rtw_get_current_time(); + pxmitframe = rtw_alloc_xmitframe(pxmitpriv, os_qid); - return _SUCCESS; -} + if (rtw_get_passing_time_ms(start) > 2000) { + if (drop_cnt) + RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt); + start = rtw_get_current_time(); + drop_cnt = 0; + } -#ifdef CONFIG_RTW_MGMT_QUEUE -void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue) -{ - _irqL irqL; - _list *plist, *phead; - struct xmit_frame *pxmitframe; + if (pxmitframe == NULL) { + drop_cnt++; + /*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/ + DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe); + return -1; + } - _enter_critical_bh(&(mgmt_queue->lock), &irqL); +#ifdef CONFIG_BR_EXT + if (MLME_IS_STA(padapter) || MLME_IS_ADHOC(padapter)) { + void *br_port = NULL; - phead = get_list_head(mgmt_queue); - plist = get_next(phead); + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif - while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + if (br_port) { + res = rtw_br_client_tx(padapter, ppkt); + if (res == -1) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return -1; + } + } + } +#endif /* CONFIG_BR_EXT */ - pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - plist = get_next(plist); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + _list f_list; - #ifdef DBG_MGMT_QUEUE - RTW_INFO("%s seq_num = %u\n", __func__, pxmitframe->attrib.seqnum); - #endif + res = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &f_list); + if (res == RTW_RA_RESOLVING) + return 1; + if (res == _FAIL) + return -1; - rtw_free_xmitbuf_ext(pxmitpriv, pxmitframe->pxmitbuf); - rtw_free_xmitframe(pxmitpriv, pxmitframe); - } - _exit_critical_bh(&(mgmt_queue->lock), &irqL); -} + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(&f_list)) { + _list *list = get_next(&f_list); + struct xmit_frame *fframe; -u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) -{ - struct sta_info *psta; - struct tx_servq *ptxservq; - struct pkt_attrib *pattrib = &(pxmitframe->attrib); - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct hw_xmit *phwxmits = pxmitpriv->hwxmits; - u8 mgmt_idx = pxmitpriv->hwxmit_entry - 1; + while ((rtw_end_of_queue_search(&f_list, list)) == _FALSE) { + fframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&fframe->list); - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); + fframe->pkt = rtw_skb_copy(*ppkt); + if (!fframe->pkt) { + if (res == RTW_ORI_NO_NEED) + res = _SUCCESS; + rtw_free_xmitframe(pxmitpriv, fframe); + continue; + } - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if (pattrib->psta != psta) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta); - RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); - return _FAIL; - } + rtw_xmit_posthandle(padapter, fframe, fframe->pkt); + } + } + #endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ - if (psta == NULL) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); - RTW_INFO("rtw_xmit_classifier: psta == NULL\n"); - return _FAIL; + if (res == RTW_ORI_NO_NEED) { + rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe); + return 0; + } } +#endif /* CONFIG_RTW_MESH */ - if (!(psta->state & WIFI_ASOC_STATE)) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink); - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FAIL; - } + pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */ + res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt); - ptxservq = &(psta->sta_xmitpriv.mgmt_q); + return res; +} - if (rtw_is_list_empty(&ptxservq->tx_pending)) - rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[mgmt_idx].sta_queue)); +#ifdef RTW_PHL_TX - rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); - ptxservq->qcnt++; - phwxmits[mgmt_idx].accnt++; +#ifdef RTW_PHL_TEST_FPGA +u32 test_seq; +#endif - return _SUCCESS; +u8 *get_head_from_txreq(_adapter *padapter, struct xmit_frame *pxframe, u8 frag_idx) +{ + return 0; } -#endif -void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) +u8 *get_tail_from_txreq(_adapter *padapter, struct xmit_frame *pxframe, u8 frag_idx) { - _irqL irqL; - _list *plist, *phead; - struct xmit_frame *pxmitframe; + return 0; +} +void dump_pkt(u8 *start, u32 len) +{ + u32 idx = 0; + for (idx = 0; idx < len; idx++) { + printk("%02x ", start[idx]); + if ((idx % 20) == 19) + printk("\n"); + } + printk("\n"); +} - _enter_critical_bh(&(pframequeue->lock), &irqL); +/* TXREQ_QMGT */ +u8 *get_txreq_buffer(_adapter *padapter, u8 **txreq, u8 **pkt_list, u8 **head, u8 **tail) +{ + struct xmit_txreq_buf *ptxreq_buf = NULL; + _list *plist, *phead; + _queue *pfree_txreq_queue = &padapter->free_txreq_queue; +#ifdef CONFIG_CORE_TXSC + u8 i = 0; +#endif - phead = get_list_head(pframequeue); - plist = get_next(phead); + _rtw_spinlock_bh(&pfree_txreq_queue->lock); + if (_rtw_queue_empty(pfree_txreq_queue) == _TRUE) { + padapter->txreq_full_cnt++; + } else { + phead = get_list_head(pfree_txreq_queue); + plist = get_next(phead); + ptxreq_buf = LIST_CONTAINOR(plist, struct xmit_txreq_buf, list); + rtw_list_delete(&ptxreq_buf->list); - while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + padapter->free_txreq_cnt--; + } + _rtw_spinunlock_bh(&pfree_txreq_queue->lock); - pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + if (ptxreq_buf) { - plist = get_next(plist); + if (txreq) + *txreq = ptxreq_buf->txreq; - rtw_free_xmitframe(pxmitpriv, pxmitframe); + if (head) + *head = ptxreq_buf->head; - } - _exit_critical_bh(&(pframequeue->lock), &irqL); + if (tail) + *tail = ptxreq_buf->tail; -} + if (pkt_list) + *pkt_list = ptxreq_buf->pkt_list; -s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) -{ - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue); - if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) { - /* pxmitframe->pkt = NULL; */ - return _FAIL; +#ifdef CONFIG_CORE_TXSC + for (i = 0; i < MAX_TXSC_SKB_NUM; i++) + ptxreq_buf->pkt[i] = NULL; + ptxreq_buf->pkt_cnt = 0; +#endif } - return _SUCCESS; + return (u8 *)ptxreq_buf; } -static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) +void get_txreq_resources(_adapter *padapter, struct xmit_frame *pxframe, + u8 **txreq, u8 **pkt_list, u8 **head, u8 **tail) { - _list *xmitframe_plist, *xmitframe_phead; - struct xmit_frame *pxmitframe = NULL; + u32 offset_head = (sizeof(struct rtw_xmit_req) * RTW_MAX_FRAG_NUM); + u32 offset_tail = offset_head + (SZ_HEAD_BUF * RTW_MAX_FRAG_NUM); + u32 offset_list = offset_tail + (SZ_TAIL_BUF * RTW_MAX_FRAG_NUM); + u8 *pbuf = NULL; - xmitframe_phead = get_list_head(pframe_queue); - xmitframe_plist = get_next(xmitframe_phead); - - while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { - pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - - /* xmitframe_plist = get_next(xmitframe_plist); */ + PHLTX_ENTER; - /*#ifdef RTK_DMP_PLATFORM - #ifdef CONFIG_USB_TX_AGGREGATION - if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2)) - { - pxmitframe = NULL; + //rtw_phl_tx todo: error handle, max tx req limit + padapter->tx_ring_idx++; + padapter->tx_ring_idx = (padapter->tx_ring_idx % MAX_TX_RING_NUM); - tasklet_schedule(&pxmitpriv->xmit_tasklet); + pbuf = padapter->tx_pool_ring[padapter->tx_ring_idx]; + //memset(pbuf, 0, (SZ_TX_RING*RTW_MAX_FRAG_NUM)); - break; - } - #endif - #endif*/ - rtw_list_delete(&pxmitframe->list); + if (txreq) + *txreq = pbuf; - ptxservq->qcnt--; + if (head) + *head = pbuf + offset_head; - /* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */ + if (tail) + *tail = pbuf + offset_tail; - /* ptxservq->qcnt--; */ + if (pkt_list) + *pkt_list = pbuf + offset_list; +} - break; +void dump_xmitframe_txreq(_adapter *padapter, struct xmit_frame *pxframe) +{ + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + u32 idx, idx1 = 0; - /* pxmitframe = NULL; */ + PHLTX_ENTER; + printk("total txreq=%d \n", pxframe->txreq_cnt); + for (idx = 0; idx < pxframe->txreq_cnt; idx++) { + struct rtw_pkt_buf_list *pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + printk("txreq[%d] with %d pkts =====\n", idx, txreq->pkt_cnt); + for (idx1 = 0; idx1 < txreq->pkt_cnt; idx1++) { + printk("pkt[%d] 0x%p len=%d\n", idx1, (void *)pkt_list->vir_addr, pkt_list->length); + dump_pkt(pkt_list->vir_addr, pkt_list->length); + pkt_list++; + } + txreq++; } - - return pxmitframe; + printk("\n"); } -static struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) +#ifdef CONFIG_PCI_HCI +void core_recycle_txreq_phyaddr(_adapter *padapter, struct rtw_xmit_req *txreq) { - _list *xmitframe_plist, *xmitframe_phead; - struct xmit_frame *pxmitframe = NULL; + PPCI_DATA pci_data = dvobj_to_pci(padapter->dvobj); + struct pci_dev *pdev = pci_data->ppcidev; + struct rtw_pkt_buf_list *pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + u32 idx = 0; - xmitframe_phead = get_list_head(pframe_queue); - xmitframe_plist = get_next(xmitframe_phead); + for (idx = 0; idx < txreq->pkt_cnt; idx++) { + dma_addr_t phy_addr = (pkt_list->phy_addr_l); - while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { - pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - break; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + { + u64 phy_addr_h = pkt_list->phy_addr_h; + phy_addr |= (phy_addr_h << 32); + } +#endif + pci_unmap_bus_addr(pdev, &phy_addr, pkt_list->length, PCI_DMA_TODEVICE); + pkt_list++; } - - return pxmitframe; } -struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame) +void fill_txreq_phyaddr(_adapter *padapter, struct xmit_frame *pxframe) { - _irqL irqL0; - _list *sta_plist, *sta_phead; - struct hw_xmit *phwxmit_i = pxmitpriv->hwxmits; -#ifdef CONFIG_RTW_MGMT_QUEUE - /* This function gets xmit_frame from AC queue. */ - /* When mgmt queue is used, AC queue index is (hwxmit_entry - 1) */ - sint entry = pxmitpriv->hwxmit_entry - 1; -#else - sint entry = pxmitpriv->hwxmit_entry; -#endif - struct hw_xmit *phwxmit; - struct tx_servq *ptxservq = NULL; - _queue *pframe_queue = NULL; - struct xmit_frame *pxmitframe = NULL; - _adapter *padapter = pxmitpriv->adapter; - struct registry_priv *pregpriv = &padapter->registrypriv; - int i, inx[4]; + PPCI_DATA pci_data = dvobj_to_pci(padapter->dvobj); + struct pci_dev *pdev = pci_data->ppcidev; + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + u32 idx, idx1 = 0; - inx[0] = 0; - inx[1] = 1; - inx[2] = 2; - inx[3] = 3; + PHLTX_ENTER; - *num_frame = 0; + for (idx = 0; idx < pxframe->txreq_cnt; idx++) { + struct rtw_pkt_buf_list *pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; - /*No amsdu when wifi_spec on*/ - if (pregpriv->wifi_spec == 1) { - return NULL; + for (idx1 = 0; idx1 < txreq->pkt_cnt; idx1++) { + dma_addr_t phy_addr = 0; + pci_get_bus_addr(pdev, pkt_list->vir_addr, &phy_addr, pkt_list->length, PCI_DMA_TODEVICE); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pkt_list->phy_addr_h = phy_addr >> 32; +#else + pkt_list->phy_addr_h = 0x0; +#endif + pkt_list->phy_addr_l = phy_addr & 0xFFFFFFFF; + pkt_list++; + } + txreq++; } +} +#endif - _enter_critical_bh(&pxmitpriv->lock, &irqL0); +static void _fill_txreq_list_skb(_adapter *padapter, + struct rtw_xmit_req *txreq, struct rtw_pkt_buf_list **pkt_list, + struct sk_buff *skb, u32 *req_sz, s32 *req_offset) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + #define skb_frag_off(f) ((f)->page_offset) +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) + #define skb_frag_page(f) ((f)->page) + #define skb_frag_size(f) ((f)->size) +#endif +#define PKT_LIST_APPEND(_addr, _len) do { \ + u32 __len = _len; \ + if (__len == 0) \ + break; \ + list->vir_addr = _addr; \ + list->length = __len; \ + txreq->pkt_cnt++; \ + txreq->total_len += __len; \ + list++; \ + *pkt_list = list; \ + } while (0) + + struct rtw_pkt_buf_list *list = *pkt_list; + u8 nr_frags = skb_shinfo(skb)->nr_frags; + s32 offset = *req_offset; + u32 rem_sz = *req_sz; + u32 cur_frag_total, cur_frag_rem; + int i; - for (i = 0; i < entry; i++) { - phwxmit = phwxmit_i + inx[i]; + /* skb head frag */ + cur_frag_total = skb_headlen(skb); - sta_phead = get_list_head(phwxmit->sta_queue); - sta_plist = get_next(sta_phead); + if (cur_frag_total > offset) { + cur_frag_rem = rtw_min(cur_frag_total - offset, rem_sz); + PKT_LIST_APPEND(skb->data + offset, cur_frag_rem); + rem_sz -= cur_frag_rem; + offset = 0; + } else { + offset -= cur_frag_total; + } - while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; + u8 *addr; - ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); - pframe_queue = &ptxservq->sta_pending; + addr = ((void *)page_address(skb_frag_page(frag))) + skb_frag_off(frag); + cur_frag_total = skb_frag_size(frag); - if(ptxservq->qcnt) - { - *num_frame = ptxservq->qcnt; - pxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); - goto exit; + if (offset < cur_frag_total) { + cur_frag_rem = cur_frag_total - offset; + + if (rem_sz < cur_frag_rem) { + PKT_LIST_APPEND(addr + offset, rem_sz); + RTW_WARN("%s:%d, size(rem_sz)=%d cur_frag_rem=%d txreq->total_length = %d\n", + __func__, __LINE__, rem_sz, cur_frag_rem, txreq->total_len); + rem_sz = 0; + break; + } else { + PKT_LIST_APPEND(addr + offset, cur_frag_rem); + RTW_DBG("%s:%d, size=%d txreq->total_length = %d\n", + __func__, __LINE__, cur_frag_rem, txreq->total_len); + rem_sz -= cur_frag_rem; } - sta_plist = get_next(sta_plist); + + offset = 0; + } else { + offset -= cur_frag_total; } } -exit: + *req_sz = rem_sz; + *req_offset = offset; + +#undef PKT_LIST_APPEND +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + #undef skb_frag_off +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) + #undef skb_frag_page + #undef skb_frag_size +#endif +} - _exit_critical_bh(&pxmitpriv->lock, &irqL0); +static int skb_total_frag_nr(struct sk_buff *head_skb) +{ + struct sk_buff *skb; + int nr; - return pxmitframe; + nr = 1 + skb_shinfo(head_skb)->nr_frags; + + skb_walk_frags(head_skb, skb) + nr += 1 + skb_shinfo(skb)->nr_frags; + + return nr; } -#ifdef CONFIG_RTW_MGMT_QUEUE -struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv) +static void fill_txreq_list_skb(_adapter *padapter, + struct rtw_xmit_req *txreq, struct rtw_pkt_buf_list **pkt_list, + struct sk_buff *head_skb, u32 req_sz, s32 offset) { - _irqL irqL0; - _list *sta_plist, *sta_phead; - struct hw_xmit *mgmt_hwxmit; - struct tx_servq *ptxservq = NULL; - _queue *pframe_queue = NULL; - struct xmit_frame *pxmitframe = NULL; - u8 mgmt_entry = pxmitpriv->hwxmit_entry - 1; + struct sk_buff *skb; + + if (skb_total_frag_nr(head_skb) > NUM_PKT_LIST_PER_TXREQ - 2) { + rtw_skb_linearize(head_skb); + RTW_WARN("skb total frag nr over %d\n", NUM_PKT_LIST_PER_TXREQ - 2); + } - _enter_critical_bh(&pxmitpriv->lock, &irqL0); + _fill_txreq_list_skb(padapter, txreq, pkt_list, head_skb, &req_sz, &offset); - /* management queue */ - mgmt_hwxmit = (pxmitpriv->hwxmits) + mgmt_entry; + skb_walk_frags(head_skb, skb) + _fill_txreq_list_skb(padapter, txreq, pkt_list, skb, &req_sz, &offset); - sta_phead = get_list_head(mgmt_hwxmit->sta_queue); - sta_plist = get_next(sta_phead); + if (req_sz != 0) + RTW_WARN("remain req_sz=%d should be zero\n", req_sz); +} - while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { +s32 rtw_core_replace_skb(struct sk_buff **pskb, u32 need_head, u32 need_tail) +{ + struct sk_buff *newskb; + struct sk_buff *skb = *pskb; - ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); + newskb = rtw_skb_copy(skb); - pframe_queue = &ptxservq->sta_pending; + if (newskb == NULL) + return FAIL; - pxmitframe = dequeue_one_xmitframe(pxmitpriv, mgmt_hwxmit, ptxservq, pframe_queue); + rtw_skb_free(skb); + *pskb = newskb; - #ifdef DBG_MGMT_QUEUE - RTW_INFO("%s dequeue mgmt frame (seq_num = %u) to TX\n", __func__, pxmitframe->attrib.seqnum); - #endif + return SUCCESS; +} - if (pxmitframe) { - mgmt_hwxmit->accnt--; +#ifdef CONFIG_BR_EXT +s32 core_br_client_tx(_adapter *padapter, struct xmit_frame *pxframe, struct sk_buff **pskb) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* Remove sta node when there is no pending packets. */ - if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */ - rtw_list_delete(&ptxservq->tx_pending); + if (!adapter_use_wds(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + void *br_port = NULL; - goto exit; + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif + + if (br_port) { + if (rtw_br_client_tx(padapter, pskb) == FAIL) { + core_tx_free_xmitframe(padapter, pxframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return FAIL; + } } - sta_plist = get_next(sta_plist); } -exit: - _exit_critical_bh(&pxmitpriv->lock, &irqL0); - - return pxmitframe; + return SUCCESS; } #endif -struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) +s32 core_tx_update_pkt(_adapter *padapter, struct xmit_frame *pxframe, struct sk_buff **pskb) { - _irqL irqL0; - _list *sta_plist, *sta_phead; - struct hw_xmit *phwxmit; - struct tx_servq *ptxservq = NULL; - _queue *pframe_queue = NULL; - struct xmit_frame *pxmitframe = NULL; - _adapter *padapter = pxmitpriv->adapter; - struct registry_priv *pregpriv = &padapter->registrypriv; - int i, inx[4]; -#ifdef CONFIG_RTW_MGMT_QUEUE - /* This function gets xmit_frame from AC queue. */ - /* When mgmt queue is used, AC queue index is (hwxmit_entry - 1) */ - entry--; -#endif - inx[0] = 0; - inx[1] = 1; - inx[2] = 2; - inx[3] = 3; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sk_buff *skb_orig = *pskb; - if (pregpriv->wifi_spec == 1) { - int j; -#if 0 - if (flags < XMIT_QUEUE_ENTRY) { - /* priority exchange according to the completed xmitbuf flags. */ - inx[flags] = 0; - inx[0] = flags; - } -#endif + PHLTX_LOG; -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) - for (j = 0; j < 4; j++) - inx[j] = pxmitpriv->wmm_para_seq[j]; -#endif +//rtw_phl_tx todo, BR EXT + if (core_br_client_tx(padapter, pxframe, pskb) == FAIL) + return FAIL; + + return SUCCESS; +} + +s32 core_tx_update_xmitframe(_adapter *padapter, + struct xmit_frame *pxframe, struct sk_buff **pskb, struct sta_info *psta, u8 type) +{ + pxframe->xftype = type; + pxframe->pkt = *pskb; + + PHLTX_LOG; + +#if 1 + if (pxframe->xftype == RTW_TX_OS) { + if (update_attrib(padapter, *pskb, &pxframe->attrib) != _SUCCESS) + return FAIL; } +#else + pxframe->pkt = *pskb; - _enter_critical_bh(&pxmitpriv->lock, &irqL0); + if (update_xmitframe_from_hdr(padapter, pxframe) == FAIL) + return FAIL; - for (i = 0; i < entry; i++) { - phwxmit = phwxmit_i + inx[i]; + PHLTX_LOG; - /* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + if (update_xmitframe_qos(padapter, pxframe) == FAIL) + return FAIL; - sta_phead = get_list_head(phwxmit->sta_queue); - sta_plist = get_next(sta_phead); + PHLTX_LOG; - while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { + if (update_xmitframe_security(padapter, pxframe) == FAIL) + return FAIL; - ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); + PHLTX_LOG; - pframe_queue = &ptxservq->sta_pending; + //if (update_xmitframe_hw(padapter, pxframe) == FAIL) + //return FAIL; - pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); + PHLTX_LOG; - if (pxmitframe) { - phwxmit->accnt--; + if (pxframe->xftype == RTW_TX_OS) { + if (pxframe->attrib.bswenc + && (skb_shared(*pskb) || skb_cloned(*pskb)) + && (rtw_core_replace_skb(pskb, RTW_MAX_WL_HEAD, RTW_MAX_WL_TAIL) == FAIL)) + return FAIL; + } +#endif - /* Remove sta node when there is no pending packets. */ - if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */ - rtw_list_delete(&ptxservq->tx_pending); + PHLTX_LOG; - /* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + return SUCCESS; +} - goto exit; - } - sta_plist = get_next(sta_plist); - } +void get_wl_frag_paras(_adapter *padapter, struct xmit_frame *pxframe, + u32 *frag_perfr, u32 *wl_frags) +{ + u32 wl_head, wl_tail, payload_totalsz, payload_fragsz, wl_frag_num; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + wl_head = wl_tail = payload_totalsz = 0; + wl_head += pxframe->attrib.hdrlen; + wl_tail += RTW_SZ_FCS; + if (pxframe->attrib.encrypt) { + wl_head += pxframe->attrib.iv_len; + wl_tail += pxframe->attrib.icv_len; } -exit: + payload_fragsz = pxmitpriv->frag_len - wl_head - wl_tail; - _exit_critical_bh(&pxmitpriv->lock, &irqL0); + payload_totalsz = pxframe->attrib.pktlen; + if (pxframe->xftype == RTW_TX_OS) + payload_totalsz += RTW_SZ_LLC; + if (pxframe->attrib.encrypt == _TKIP_) + payload_totalsz += RTW_TKIP_MIC_LEN; - return pxmitframe; + if (pxframe->attrib.amsdu) + wl_frag_num = 1; + else if (payload_fragsz < payload_totalsz) + wl_frag_num = RTW_DIV_ROUND_UP(payload_totalsz, payload_fragsz); + else + wl_frag_num = 1; + + pxframe->attrib.frag_datalen = *frag_perfr = payload_fragsz; + pxframe->attrib.nr_frags = *wl_frags = wl_frag_num; +#ifdef CONFIG_CORE_TXSC + pxframe->attrib.frag_len_txsc = payload_fragsz - (payload_totalsz - pxframe->attrib.pktlen); +#endif } -struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) +u8 fill_txreq_pkt_perfrag_txos(struct _ADAPTER *padapter, + struct xmit_frame *pxframe, + u32 frag_perfr, u32 wl_frags) { - struct tx_servq *ptxservq = NULL; + struct rtw_xmit_req *xf_txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + struct sk_buff *skb = pxframe->pkt; + u8 *txreq, *head, *tail, *list; + u32 head_sz, tail_sz, wlan_tail; + u32 payload_sz, payload_offset; + u8 idx; + u8 *wlhdr[RTW_MAX_FRAG_NUM] = {NULL}; + u8 *wltail[RTW_MAX_FRAG_NUM] = {NULL}; + /* TXREQ_QMGT */ + struct xmit_txreq_buf *txreq_buf = NULL; + PHLTX_ENTER; - switch (up) { - case 1: - case 2: - ptxservq = &(psta->sta_xmitpriv.bk_q); - *(ac) = 3; - break; + //printk("pxframe->attrib.pkt_hdrlen=%d pxframe->attrib.hdrlen=%d pxframe->attrib.iv_len=%d \n", pxframe->attrib.pkt_hdrlen, pxframe->attrib.hdrlen, pxframe->attrib.iv_len); - case 4: - case 5: - ptxservq = &(psta->sta_xmitpriv.vi_q); - *(ac) = 1; - break; + pxframe->txreq_cnt = wl_frags; - case 6: - case 7: - ptxservq = &(psta->sta_xmitpriv.vo_q); - *(ac) = 0; - break; + head_sz = pxframe->attrib.hdrlen + (pxframe->attrib.amsdu ? 0 : RTW_SZ_LLC); + tail_sz = 0; + if (pxframe->attrib.encrypt) { + head_sz += pxframe->attrib.iv_len; + if (pxframe->attrib.encrypt == _TKIP_) + tail_sz += RTW_TKIP_MIC_LEN; + if (pxframe->attrib.bswenc) + tail_sz += pxframe->attrib.icv_len; + } - case 0: - case 3: - default: - ptxservq = &(psta->sta_xmitpriv.be_q); - *(ac) = 2; - break; + PHLTX_LOG; + //get_txreq_resources(padapter, pxframe, &txreq, &list, &head, &tail); + /* TXREQ_QMGT */ + txreq_buf = (struct xmit_txreq_buf *)get_txreq_buffer(padapter, &txreq, &list, &head, &tail); + if (txreq_buf == NULL) { + //do this in core_tx_init_xmitframe + //pxframe->phl_txreq = NULL; + //pxframe->ptxreq_buf = NULL; + + //free in rtw_core_tx + //pxframe->pkt = NULL;//for not recycle in abort_core_tx + goto fail; } +#ifdef USE_PREV_WLHDR_BUF /* CONFIG_CORE_TXSC */ + txreq_buf->macid = 0xff; + txreq_buf->txsc_id = 0xff; +#endif + pxframe->ptxreq_buf = txreq_buf; + PHLTX_LOG; - return ptxservq; -} +#if 0 + payload = skb->data+pxframe->attrib.pkt_hdrlen; + printk("num_txreq=%d, hw_head=%d, hw_tail=%d, list=0x%p\n", + num_txreq, hw_head, hw_tail, (void *)list); -/* - * Will enqueue pxmitframe to the proper queue, - * and indicate it to xx_pending list..... - */ -s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) -{ - /* _irqL irqL0; */ - u8 ac_index; - struct sta_info *psta; - struct tx_servq *ptxservq; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; - sint res = _SUCCESS; + printk("p:txreq=0x%p, head=0x%p, tail=0x%p, payload=0x%p\n", + (void *)txreq, (void *)head, (void *)tail, (void *)payload); +#endif + pxframe->phl_txreq = xf_txreq = (struct rtw_xmit_req *)txreq; + pkt_list = (struct rtw_pkt_buf_list *)list; +#ifdef CONFIG_CORE_TXSC + xf_txreq->shortcut_id = 0; + xf_txreq->treq_type = RTW_PHL_TREQ_TYPE_NORMAL; +#endif - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); + PHLTX_LOG; - /* - if (pattrib->psta) { - psta = pattrib->psta; + /* move to first payload position */ + payload_offset = pxframe->attrib.pkt_hdrlen; + + for (idx = 0; idx < wl_frags; idx++) { + /* for no memset */ + xf_txreq->pkt_cnt = 0; + xf_txreq->total_len = 0; + xf_txreq->pkt_list = (u8 *)pkt_list; + + /* fill head into txreq */ + wlhdr[idx] = head; + pkt_list->vir_addr = head; + pkt_list->length = head_sz; + if (idx) { + /* deduct LLC size if not first fragment */ + pkt_list->length -= RTW_SZ_LLC; + } + head += pkt_list->length; + xf_txreq->pkt_cnt++; + xf_txreq->total_len += pkt_list->length; + pkt_list++; + + /* fill payload into txreq */ + if (idx == (wl_frags - 1)) { + /* last payload size */ + payload_sz = skb->len - payload_offset; + } else if (idx == 0) { + /* first payload size should deduct LLC size */ + payload_sz = frag_perfr - RTW_SZ_LLC; } else { - RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); - psta = rtw_get_stainfo(pstapriv, pattrib->ra); + payload_sz = frag_perfr; + } + /* xf_txreq would be update and pkt_list++ inside */ + fill_txreq_list_skb(padapter, xf_txreq, &pkt_list, skb, + payload_sz, payload_offset); + payload_offset += payload_sz; + + /* fill tail(if alloc) into txreq */ + if (tail_sz) { + wlan_tail = tail_sz; + if ((pxframe->attrib.encrypt == _TKIP_) && (idx != (wl_frags - 1))) { + /* deduct MIC size if not last fragment with TKIP */ + wlan_tail -= RTW_TKIP_MIC_LEN; + } + if (wlan_tail) { + wltail[idx] = tail; + pkt_list->vir_addr = tail; + pkt_list->length = wlan_tail; + tail += pkt_list->length; + xf_txreq->pkt_cnt++; + xf_txreq->total_len += pkt_list->length; + pkt_list++; + } } - */ - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - if (pattrib->psta != psta) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta); - RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); - return _FAIL; - } + if (xf_txreq->pkt_cnt > NUM_PKT_LIST_PER_TXREQ) + RTW_WARN("xf_txreq->pkt_cnt=%d > NUM_PKT_LIST_PER_TXREQ\n", + xf_txreq->pkt_cnt); - if (psta == NULL) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); - res = _FAIL; - RTW_INFO("rtw_xmit_classifier: psta == NULL\n"); - goto exit; + xf_txreq++; } - if (!(psta->state & WIFI_ASOC_STATE)) { - DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink); - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FAIL; - } + _rtw_memcpy(pxframe->wlhdr, wlhdr, sizeof(wlhdr)); + _rtw_memcpy(pxframe->wltail, wltail, sizeof(wltail)); + PHLTX_EXIT; + return _SUCCESS; - ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); +fail: + return _FAIL; +} - /* _enter_critical(&pstapending->lock, &irqL0); */ +/* TXREQ_QMGT, MGT_TXREQ_QMGT */ +u8 fill_txreq_pkt_mgmt(_adapter *padapter, struct xmit_frame *pxframe) +{ + struct rtw_xmit_req *xf_txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + //u8 *txreq, *head, *tail, *list, *mgmt = NULL; - if (rtw_is_list_empty(&ptxservq->tx_pending)) - rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); + PHLTX_ENTER; + + if (!pxframe->phl_txreq) + goto fail; - /* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */ + xf_txreq = pxframe->phl_txreq; + pkt_list = (struct rtw_pkt_buf_list *)xf_txreq->pkt_list; - rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); - ptxservq->qcnt++; - phwxmits[ac_index].accnt++; + //get_txreq_resources(padapter, pxframe, + // (u8 **)&xf_txreq, (u8 **)&pkt_list, NULL, NULL); + //printk("p:txreq=0x%p, pkt_list=0x%p \n", (void *)xf_txreq, (void *)pkt_list); - /* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */ + //for no memset + xf_txreq->pkt_cnt = 0; + xf_txreq->total_len = 0; +#ifdef CONFIG_CORE_TXSC + xf_txreq->shortcut_id = 0; +#endif - /* _exit_critical(&pstapending->lock, &irqL0); */ + pkt_list->vir_addr = pxframe->buf_addr; + pkt_list->length = pxframe->attrib.pktlen; -exit: + xf_txreq->pkt_cnt = 1; + //xf_txreq->pkt_list = (u8 *)pkt_list; + xf_txreq->treq_type = RTW_PHL_TREQ_TYPE_NORMAL; + pxframe->txreq_cnt = 1; + //pxframe->phl_txreq = xf_txreq; - return res; -} + xf_txreq->total_len = xf_txreq->total_len + pxframe->attrib.pktlen; + //RTW_INFO("%s,%d, xf_txreq->total_length = %d\n", __func__, __LINE__, xf_txreq->total_len); -void rtw_alloc_hwxmits(_adapter *padapter) +#ifdef RTW_PHL_TEST_FPGA { - struct hw_xmit *hwxmits; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_ieee80211_hdr *p = (struct rtw_ieee80211_hdr *)pxframe->buf_addr; - pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; + test_seq++; + test_seq = test_seq%0xFFF; + SetSeqNum(p, test_seq); +} +#endif - pxmitpriv->hwxmits = NULL; +exit: + return _SUCCESS; - pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry); +fail: + return _FAIL; +} - if (pxmitpriv->hwxmits == NULL) { - RTW_INFO("alloc hwxmits fail!...\n"); - return; +static u8 merge_txreq_to_one_piece(struct _ADAPTER *a, + struct xmit_frame *xf) +{ + struct rtw_xmit_req *txreq = NULL; + struct rtw_pkt_buf_list *pkt_list = NULL; + int i, j; + u32 total_sz; + u8 *buf, *ptr; + + + for (i = 0; i < xf->txreq_cnt; i++) { + txreq = &xf->phl_txreq[i]; + total_sz = txreq->total_len; + buf = rtw_zmalloc(total_sz); + if (!buf) + return _FAIL; + xf->buf_need_free |= BIT(i); + + ptr = buf; + for (j = 0; j < txreq->pkt_cnt; j++) { + pkt_list = &((struct rtw_pkt_buf_list *)txreq->pkt_list)[j]; + _rtw_memcpy(ptr, pkt_list->vir_addr, pkt_list->length); + ptr += pkt_list->length; + } + txreq->pkt_cnt = 1; + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pkt_list->vir_addr = buf; + pkt_list->length = total_sz; } - hwxmits = pxmitpriv->hwxmits; + return _SUCCESS; +} - rtw_warn_on(pxmitpriv->hwxmit_entry < 4); +#ifdef RTW_PHL_TEST_FPGA +#define F_TX_MACID (0) +#define F_TX_TID (1) +#define F_TX_TYPE RTW_PHL_PKT_TYPE_DATA +#define F_TX_RATE (0x8F) //HRATE_MCS15 +#define F_TX_BW (1) +#define F_TX_DMACH (0) +#endif - /* pxmitpriv->vo_txqueue.head = 0; */ - /* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */ - hwxmits[0].sta_queue = &pxmitpriv->vo_pending; +static u8 get_security_cam_id(struct _ADAPTER *padapter, struct xmit_frame *pxframe, u8 keyid) +{ + struct dvobj_priv *d; + void *phl; + u8 sec_cam_id = 0; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *sta; + sint bmcast = IS_MCAST(pxframe->attrib.ra); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; - /* pxmitpriv->vi_txqueue.head = 0; */ - /* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */ - hwxmits[1].sta_queue = &pxmitpriv->vi_pending; + if (bmcast == _TRUE) { + /* WEP: use unicast key type to match halmac rule (see: setkey_hdl) */ + if (pxframe->attrib.encrypt == _WEP40_ || pxframe->attrib.encrypt == _WEP104_) + bmcast = _FALSE; - /* pxmitpriv->be_txqueue.head = 0; */ - /* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */ - hwxmits[2].sta_queue = &pxmitpriv->be_pending; + sta = rtw_get_stainfo(pstapriv, pbss_network->MacAddress); + } else { + sta = rtw_get_stainfo(pstapriv, pxframe->attrib.ra); + } - /* pxmitpriv->bk_txqueue.head = 0; */ - /* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */ - hwxmits[3].sta_queue = &pxmitpriv->bk_pending; + if (!sta) { + RTW_ERR("%s sta not found\n", __func__); + rtw_warn_on(1); + return sec_cam_id; + } -#ifdef CONFIG_RTW_MGMT_QUEUE - hwxmits[4].sta_queue = &pxmitpriv->mgmt_pending; -#endif + d = adapter_to_dvobj(padapter); + phl = GET_PHL_INFO(d); -} + if (keyid >= 4) + sec_cam_id = rtw_phl_get_sec_cam_idx(phl, sta->phl_sta, keyid, + RTW_SEC_KEY_BIP); + else + sec_cam_id = rtw_phl_get_sec_cam_idx(phl, sta->phl_sta, keyid, + bmcast ? RTW_SEC_KEY_MULTICAST : RTW_SEC_KEY_UNICAST); + + return sec_cam_id; +} + +/* Todo: HE rate mapping not ready */ +static const enum rtw_data_rate mrate2phlrate_tbl[] = { + [MGN_1M] = RTW_DATA_RATE_CCK1, + [MGN_2M] = RTW_DATA_RATE_CCK2, + [MGN_5_5M] = RTW_DATA_RATE_CCK5_5, + [MGN_11M] = RTW_DATA_RATE_CCK11, + [MGN_6M] = RTW_DATA_RATE_OFDM6, + [MGN_9M] = RTW_DATA_RATE_OFDM9, + [MGN_12M] = RTW_DATA_RATE_OFDM12, + [MGN_18M] = RTW_DATA_RATE_OFDM18, + [MGN_24M] = RTW_DATA_RATE_OFDM24, + [MGN_36M] = RTW_DATA_RATE_OFDM36, + [MGN_48M] = RTW_DATA_RATE_OFDM48, + [MGN_54M] = RTW_DATA_RATE_OFDM54, + [MGN_MCS0] = RTW_DATA_RATE_MCS0, + [MGN_MCS1] = RTW_DATA_RATE_MCS1, + [MGN_MCS2] = RTW_DATA_RATE_MCS2, + [MGN_MCS3] = RTW_DATA_RATE_MCS3, + [MGN_MCS4] = RTW_DATA_RATE_MCS4, + [MGN_MCS5] = RTW_DATA_RATE_MCS5, + [MGN_MCS6] = RTW_DATA_RATE_MCS6, + [MGN_MCS7] = RTW_DATA_RATE_MCS7, + [MGN_MCS8] = RTW_DATA_RATE_MCS8, + [MGN_MCS9] = RTW_DATA_RATE_MCS9, + [MGN_MCS10] = RTW_DATA_RATE_MCS10, + [MGN_MCS11] = RTW_DATA_RATE_MCS11, + [MGN_MCS12] = RTW_DATA_RATE_MCS12, + [MGN_MCS13] = RTW_DATA_RATE_MCS13, + [MGN_MCS14] = RTW_DATA_RATE_MCS14, + [MGN_MCS15] = RTW_DATA_RATE_MCS15, + [MGN_MCS16] = RTW_DATA_RATE_MCS16, + [MGN_MCS17] = RTW_DATA_RATE_MCS17, + [MGN_MCS18] = RTW_DATA_RATE_MCS18, + [MGN_MCS19] = RTW_DATA_RATE_MCS19, + [MGN_MCS20] = RTW_DATA_RATE_MCS20, + [MGN_MCS21] = RTW_DATA_RATE_MCS21, + [MGN_MCS22] = RTW_DATA_RATE_MCS22, + [MGN_MCS23] = RTW_DATA_RATE_MCS23, + [MGN_MCS24] = RTW_DATA_RATE_MCS24, + [MGN_MCS25] = RTW_DATA_RATE_MCS25, + [MGN_MCS26] = RTW_DATA_RATE_MCS26, + [MGN_MCS27] = RTW_DATA_RATE_MCS27, + [MGN_MCS28] = RTW_DATA_RATE_MCS28, + [MGN_MCS29] = RTW_DATA_RATE_MCS29, + [MGN_MCS30] = RTW_DATA_RATE_MCS30, + [MGN_MCS31] = RTW_DATA_RATE_MCS31, + [MGN_VHT1SS_MCS0] = RTW_DATA_RATE_VHT_NSS1_MCS0, + [MGN_VHT1SS_MCS1] = RTW_DATA_RATE_VHT_NSS1_MCS1, + [MGN_VHT1SS_MCS2] = RTW_DATA_RATE_VHT_NSS1_MCS2, + [MGN_VHT1SS_MCS3] = RTW_DATA_RATE_VHT_NSS1_MCS3, + [MGN_VHT1SS_MCS4] = RTW_DATA_RATE_VHT_NSS1_MCS4, + [MGN_VHT1SS_MCS5] = RTW_DATA_RATE_VHT_NSS1_MCS5, + [MGN_VHT1SS_MCS6] = RTW_DATA_RATE_VHT_NSS1_MCS6, + [MGN_VHT1SS_MCS7] = RTW_DATA_RATE_VHT_NSS1_MCS7, + [MGN_VHT1SS_MCS8] = RTW_DATA_RATE_VHT_NSS1_MCS8, + [MGN_VHT1SS_MCS9] = RTW_DATA_RATE_VHT_NSS1_MCS9, + [MGN_VHT2SS_MCS0] = RTW_DATA_RATE_VHT_NSS2_MCS0, + [MGN_VHT2SS_MCS1] = RTW_DATA_RATE_VHT_NSS2_MCS1, + [MGN_VHT2SS_MCS2] = RTW_DATA_RATE_VHT_NSS2_MCS2, + [MGN_VHT2SS_MCS3] = RTW_DATA_RATE_VHT_NSS2_MCS3, + [MGN_VHT2SS_MCS4] = RTW_DATA_RATE_VHT_NSS2_MCS4, + [MGN_VHT2SS_MCS5] = RTW_DATA_RATE_VHT_NSS2_MCS5, + [MGN_VHT2SS_MCS6] = RTW_DATA_RATE_VHT_NSS2_MCS6, + [MGN_VHT2SS_MCS7] = RTW_DATA_RATE_VHT_NSS2_MCS7, + [MGN_VHT2SS_MCS8] = RTW_DATA_RATE_VHT_NSS2_MCS8, + [MGN_VHT2SS_MCS9] = RTW_DATA_RATE_VHT_NSS2_MCS9, + [MGN_VHT3SS_MCS0] = RTW_DATA_RATE_VHT_NSS3_MCS0, + [MGN_VHT3SS_MCS1] = RTW_DATA_RATE_VHT_NSS3_MCS1, + [MGN_VHT3SS_MCS2] = RTW_DATA_RATE_VHT_NSS3_MCS2, + [MGN_VHT3SS_MCS3] = RTW_DATA_RATE_VHT_NSS3_MCS3, + [MGN_VHT3SS_MCS4] = RTW_DATA_RATE_VHT_NSS3_MCS4, + [MGN_VHT3SS_MCS5] = RTW_DATA_RATE_VHT_NSS3_MCS5, + [MGN_VHT3SS_MCS6] = RTW_DATA_RATE_VHT_NSS3_MCS6, + [MGN_VHT3SS_MCS7] = RTW_DATA_RATE_VHT_NSS3_MCS7, + [MGN_VHT3SS_MCS8] = RTW_DATA_RATE_VHT_NSS3_MCS8, + [MGN_VHT3SS_MCS9] = RTW_DATA_RATE_VHT_NSS3_MCS9, + [MGN_VHT4SS_MCS0] = RTW_DATA_RATE_VHT_NSS4_MCS0, + [MGN_VHT4SS_MCS1] = RTW_DATA_RATE_VHT_NSS4_MCS1, + [MGN_VHT4SS_MCS2] = RTW_DATA_RATE_VHT_NSS4_MCS2, + [MGN_VHT4SS_MCS3] = RTW_DATA_RATE_VHT_NSS4_MCS3, + [MGN_VHT4SS_MCS4] = RTW_DATA_RATE_VHT_NSS4_MCS4, + [MGN_VHT4SS_MCS5] = RTW_DATA_RATE_VHT_NSS4_MCS5, + [MGN_VHT4SS_MCS6] = RTW_DATA_RATE_VHT_NSS4_MCS6, + [MGN_VHT4SS_MCS7] = RTW_DATA_RATE_VHT_NSS4_MCS7, + [MGN_VHT4SS_MCS8] = RTW_DATA_RATE_VHT_NSS4_MCS8, + [MGN_VHT4SS_MCS9] = RTW_DATA_RATE_VHT_NSS4_MCS9, + [MGN_HE1SS_MCS0] = RTW_DATA_RATE_HE_NSS1_MCS0, + [MGN_HE1SS_MCS1] = RTW_DATA_RATE_HE_NSS1_MCS1, + [MGN_HE1SS_MCS2] = RTW_DATA_RATE_HE_NSS1_MCS2, + [MGN_HE1SS_MCS3] = RTW_DATA_RATE_HE_NSS1_MCS3, + [MGN_HE1SS_MCS4] = RTW_DATA_RATE_HE_NSS1_MCS4, + [MGN_HE1SS_MCS5] = RTW_DATA_RATE_HE_NSS1_MCS5, + [MGN_HE1SS_MCS6] = RTW_DATA_RATE_HE_NSS1_MCS6, + [MGN_HE1SS_MCS7] = RTW_DATA_RATE_HE_NSS1_MCS7, + [MGN_HE1SS_MCS8] = RTW_DATA_RATE_HE_NSS1_MCS8, + [MGN_HE1SS_MCS9] = RTW_DATA_RATE_HE_NSS1_MCS9, + [MGN_HE1SS_MCS10] = RTW_DATA_RATE_HE_NSS1_MCS10, + [MGN_HE1SS_MCS11] = RTW_DATA_RATE_HE_NSS1_MCS11, + [MGN_HE2SS_MCS0] = RTW_DATA_RATE_HE_NSS2_MCS0, + [MGN_HE2SS_MCS1] = RTW_DATA_RATE_HE_NSS2_MCS1, + [MGN_HE2SS_MCS2] = RTW_DATA_RATE_HE_NSS2_MCS2, + [MGN_HE2SS_MCS3] = RTW_DATA_RATE_HE_NSS2_MCS3, + [MGN_HE2SS_MCS4] = RTW_DATA_RATE_HE_NSS2_MCS4, + [MGN_HE2SS_MCS5] = RTW_DATA_RATE_HE_NSS2_MCS5, + [MGN_HE2SS_MCS6] = RTW_DATA_RATE_HE_NSS2_MCS6, + [MGN_HE2SS_MCS7] = RTW_DATA_RATE_HE_NSS2_MCS7, + [MGN_HE2SS_MCS8] = RTW_DATA_RATE_HE_NSS2_MCS8, + [MGN_HE2SS_MCS9] = RTW_DATA_RATE_HE_NSS2_MCS9, + [MGN_HE2SS_MCS10] = RTW_DATA_RATE_HE_NSS2_MCS10, + [MGN_HE2SS_MCS11] = RTW_DATA_RATE_HE_NSS2_MCS11, + [MGN_HE3SS_MCS0] = RTW_DATA_RATE_HE_NSS3_MCS0, + [MGN_HE3SS_MCS1] = RTW_DATA_RATE_HE_NSS3_MCS1, + [MGN_HE3SS_MCS2] = RTW_DATA_RATE_HE_NSS3_MCS2, + [MGN_HE3SS_MCS3] = RTW_DATA_RATE_HE_NSS3_MCS3, + [MGN_HE3SS_MCS4] = RTW_DATA_RATE_HE_NSS3_MCS4, + [MGN_HE3SS_MCS5] = RTW_DATA_RATE_HE_NSS3_MCS5, + [MGN_HE3SS_MCS6] = RTW_DATA_RATE_HE_NSS3_MCS6, + [MGN_HE3SS_MCS7] = RTW_DATA_RATE_HE_NSS3_MCS7, + [MGN_HE3SS_MCS8] = RTW_DATA_RATE_HE_NSS3_MCS8, + [MGN_HE3SS_MCS9] = RTW_DATA_RATE_HE_NSS3_MCS9, + [MGN_HE3SS_MCS10] = RTW_DATA_RATE_HE_NSS3_MCS10, + [MGN_HE3SS_MCS11] = RTW_DATA_RATE_HE_NSS3_MCS11, + [MGN_HE4SS_MCS0] = RTW_DATA_RATE_HE_NSS4_MCS0, + [MGN_HE4SS_MCS1] = RTW_DATA_RATE_HE_NSS4_MCS1, + [MGN_HE4SS_MCS2] = RTW_DATA_RATE_HE_NSS4_MCS2, + [MGN_HE4SS_MCS3] = RTW_DATA_RATE_HE_NSS4_MCS3, + [MGN_HE4SS_MCS4] = RTW_DATA_RATE_HE_NSS4_MCS4, + [MGN_HE4SS_MCS5] = RTW_DATA_RATE_HE_NSS4_MCS5, + [MGN_HE4SS_MCS6] = RTW_DATA_RATE_HE_NSS4_MCS6, + [MGN_HE4SS_MCS7] = RTW_DATA_RATE_HE_NSS4_MCS7, + [MGN_HE4SS_MCS8] = RTW_DATA_RATE_HE_NSS4_MCS8, + [MGN_HE4SS_MCS9] = RTW_DATA_RATE_HE_NSS4_MCS9, + [MGN_HE4SS_MCS10] = RTW_DATA_RATE_HE_NSS4_MCS10, + [MGN_HE4SS_MCS11] = RTW_DATA_RATE_HE_NSS4_MCS11, +}; -void rtw_free_hwxmits(_adapter *padapter) +/* + * _rate_mrate2phl() - convert data rate from mrate to PHL(MAC) + * @sta: struct sta_info * + * @mrate: date rate of mrate type, enum MGN_RATE + * + * Convert data rate from MGN_RATE definition to PHL's definition. + * + * Return PHL's data rate definition "enum rtw_data_rate". + * 0x0~0xB: CCK 1M ~ OFDM 54M + * 0x80~0x9F: HT MCS0~MCS31 + * 0x100~0x109: VHT 1SS MCS0~MCS9 + * 0x110~0x119: VHT 2SS MCS0~MCS9 + * 0x120~0x129: VHT 3SS MCS0~MCS9 + * 0x130~0x139: VHT 4SS MCS0~MCS9 + * 0x180~0x18B: HE 1SS MCS0~MCS11 + * 0x190~0x19B: HE 2SS MCS0~MCS11 + * 0x1A0~0x1AB: HE 3SS MCS0~MCS11 + * 0x1B0~0x1BB: HE 4SS MCS0~MCS11 + */ +static enum rtw_data_rate _rate_mrate2phl(enum MGN_RATE mrate) { - struct hw_xmit *hwxmits; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + enum rtw_data_rate phl = RTW_DATA_RATE_CCK1; - hwxmits = pxmitpriv->hwxmits; - if (hwxmits) - rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry)); + + if (mrate < ARRAY_SIZE(mrate2phlrate_tbl)) + phl = mrate2phlrate_tbl[mrate]; + + if ((mrate != MGN_1M) && (phl == RTW_DATA_RATE_CCK1)) + RTW_WARN("%s: Invalid rate 0x%x\n", __func__, mrate); + + return phl; } -void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) +/* + * _rate_drv2phl() - convert data rate from drive to PHL(MAC) + * @sta: struct sta_info * + * @rate: date rate of driver + * 0x0~0xB: CCK 1M ~ OFDM 54M + * >0xB: HT/VHT/HE use the same bits field to represent each + * data rate, so these bits's real definition depended on + * sta's wireless mode. + * + * Convert driver's data rate definition to PHL's definition. + * + * Return PHL's data rate definition "enum rtw_data_rate". + */ +static enum rtw_data_rate _rate_drv2phl(struct sta_info *sta, u8 rate) { - sint i; - for (i = 0; i < entry; i++, phwxmit++) { - /* _rtw_spinlock_init(&phwxmit->xmit_lock); */ - /* _rtw_init_listhead(&phwxmit->pending); */ - /* phwxmit->txcmdcnt = 0; */ - phwxmit->accnt = 0; + enum rtw_data_rate phl = RTW_DATA_RATE_CCK1; + u8 ht_support = 0, vht_support = 0, he_support = 0; + + + if (rate < 12) { + /* B/G mode, CCK/OFDM rate */ + return (enum rtw_data_rate)rate; } -} -#ifdef CONFIG_BR_EXT -int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) -{ - struct sk_buff *skb = *pskb; - _irqL irqL; - /* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */ - { - void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); - int res, is_vlan_tag = 0, i, do_nat25 = 1; - unsigned short vlan_hdr = 0; - void *br_port = NULL; +#ifdef CONFIG_80211N_HT + if (sta->htpriv.ht_option == _TRUE) + ht_support = 1; +#ifdef CONFIG_80211AC_VHT + if (sta->vhtpriv.vht_option == _TRUE) + vht_support = 1; +#ifdef CONFIG_80211AX_HE + if (sta->hepriv.he_option == _TRUE) + he_support = 1; +#endif /* CONFIG_80211AX_HE */ +#endif /* CONFIG_80211AC_VHT */ +#endif /* CONFIG_80211N_HT */ - /* mac_clone_handle_frame(priv, skb); */ + rate -= 12; + if (he_support) { + if (rate < 12) + phl = RTW_DATA_RATE_HE_NSS1_MCS0 + rate; + else if (rate < 24) + phl = RTW_DATA_RATE_HE_NSS2_MCS0 + (rate - 12); + else if (rate < 36) + phl = RTW_DATA_RATE_HE_NSS3_MCS0 + (rate - 24); + else + phl = RTW_DATA_RATE_HE_NSS4_MCS0 + (rate - 36); + } else if (vht_support) { + if (rate < 10) + phl = RTW_DATA_RATE_VHT_NSS1_MCS0 + rate; + else if (rate < 20) + phl = RTW_DATA_RATE_VHT_NSS2_MCS0 + (rate - 10); + else if (rate < 30) + phl = RTW_DATA_RATE_VHT_NSS3_MCS0 + (rate - 20); + else + phl = RTW_DATA_RATE_VHT_NSS4_MCS0 + (rate - 30); + } else if (ht_support) { + phl = RTW_DATA_RATE_MCS0 + rate; + } -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - _enter_critical_bh(&padapter->br_ext_lock, &irqL); - if (!(skb->data[0] & 1) && - br_port && - memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && - *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) && - *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) && - !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { - memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); - padapter->scdb_entry->ageing_timer = jiffies; - _exit_critical_bh(&padapter->br_ext_lock, &irqL); - } else - /* if (!priv->pmib->ethBrExtInfo.nat25_disable) */ - { - /* if (priv->dev->br_port && - * !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */ -#if 1 - if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) { - is_vlan_tag = 1; - vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); - for (i = 0; i < 6; i++) - *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); - skb_pull(skb, 4); - } - /* if SA == br_mac && skb== IP => copy SIP to br_ip ?? why */ - if (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && - (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP))) - memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); + return phl; +} - if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) { - if (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) { - void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); +void fill_txreq_mdata(_adapter *padapter, struct xmit_frame *pxframe) +{ + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + struct sta_info *psta = pxframe->attrib.psta; + struct rtw_phl_stainfo_t *phl_sta = NULL; + struct rtw_t_meta_data *mdata = &(txreq->mdata); +#ifdef BMC_ON_HIQ + struct sta_priv *pstapriv = &padapter->stapriv; +#endif + u32 idx = 0; + u8 htc_option = _FALSE; +#ifdef CONFIG_XMIT_ACK + struct xmit_priv *pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv; +#endif - padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, - skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12); - if (padapter->scdb_entry != NULL) { - memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN); - memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); - padapter->scdb_entry->ageing_timer = jiffies; - do_nat25 = 0; - } - } else { - if (padapter->scdb_entry) { - padapter->scdb_entry->ageing_timer = jiffies; - do_nat25 = 0; - } else { - memset(padapter->scdb_mac, 0, MACADDRLEN); - memset(padapter->scdb_ip, 0, 4); - } - } - } - _exit_critical_bh(&padapter->br_ext_lock, &irqL); -#endif /* 1 */ - if (do_nat25) { - int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); - if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { - struct sk_buff *newskb; + PHLTX_LOG; - if (is_vlan_tag) { - skb_push(skb, 4); - for (i = 0; i < 6; i++) - *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); - *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); - *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; - } + if (pxframe->attrib.order) + htc_option = _TRUE; + + /* packet identify */ + if (pxframe->xftype == RTW_TX_DRV_MGMT) + mdata->type = RTW_PHL_PKT_TYPE_MGNT; + else + mdata->type = RTW_PHL_PKT_TYPE_DATA; - newskb = rtw_skb_copy(skb); - if (newskb == NULL) { - /* priv->ext_stats.tx_drops++; */ - DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n"); - /* goto stop_proc; */ - return -1; - } - rtw_skb_free(skb); + mdata->macid = pxframe->attrib.mac_id; - *pskb = skb = newskb; - if (is_vlan_tag) { - vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); - for (i = 0; i < 6; i++) - *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); - skb_pull(skb, 4); - } - } + /* enable wd info by default */ + mdata->wdinfo_en = 1; - if (skb_is_nonlinear(skb)) - DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); + /* packet content */ + mdata->hdr_len = pxframe->attrib.hdrlen; + mdata->hw_seq_mode = 0; + mdata->sw_seq = pxframe->attrib.seqnum; + mdata->hw_sec_iv = 0; + mdata->nav_use_hdr = 0; + /* packet security */ + if (pxframe->attrib.encrypt == _NO_PRIVACY_ || pxframe->attrib.bswenc == _TRUE) { + mdata->sec_hw_enc = _FALSE; + mdata->sec_type = RTW_ENC_NONE; + } else { + mdata->sec_hw_enc = _TRUE; + mdata->sec_type = rtw_sec_algo_drv2phl(pxframe->attrib.encrypt); + mdata->sec_cam_idx = get_security_cam_id(padapter, pxframe, pxframe->attrib.key_idx); + } + /* Currently dump secrity settings for dbg */ + RTW_DBG("sec_type= %d sec_hw_enc= %d sec_cam_idx= %d \n", + mdata->sec_type, mdata->sec_hw_enc, mdata->sec_cam_idx); + + /* packet capability */ + if (pxframe->attrib.ampdu_en == _TRUE) { + mdata->ampdu_en = 1; + mdata->bk = 0; + mdata->ampdu_density = pxframe->attrib.ampdu_spacing; +// mdata->max_agg_num = 0x3F; /* temporally fix to 64 */ +// mdata->max_agg_num = 0x25; /* temporally fix to 37 for 192k */ + mdata->max_agg_num = 0x11; /* temporally fix to 17 for 128k */ + } else { + mdata->ampdu_en = 0; + mdata->bk = 1; + } + mdata->dis_data_rate_fb = 0; + mdata->dis_rts_rate_fb = 0; + mdata->data_tx_cnt_lmt_en = 0; + mdata->data_tx_cnt_lmt = 0; + + /* Set DATA_RTY_LOWEST_RATE: 2.4G to CCK1M & 5G to OFDM6M */ + if (rtw_get_oper_band(padapter) == BAND_ON_24G) + mdata->data_rty_lowest_rate = RTW_DATA_RATE_CCK1; + else if (rtw_get_oper_band(padapter) == BAND_ON_5G) + mdata->data_rty_lowest_rate = RTW_DATA_RATE_OFDM6; + else + RTW_WARN("%s: mdata->data_rty_lowest_rate is not set.\n", __func__); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) - res = skb_linearize(skb, GFP_ATOMIC); -#else /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */ - res = skb_linearize(skb); -#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */ - if (res < 0) { - DEBUG_ERR("TX DROP: skb_linearize fail!\n"); - /* goto free_and_stop; */ - return -1; - } + mdata->life_time_sel = 0; + mdata->rts_en = pxframe->attrib.rtsen; + mdata->cts2self = pxframe->attrib.cts2self; + mdata->hw_rts_en = pxframe->attrib.hw_rts_en; + mdata->rts_cca_mode = 0; - res = nat25_db_handle(padapter, skb, NAT25_INSERT); - if (res < 0) { - if (res == -2) { - /* priv->ext_stats.tx_drops++; */ - DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); - /* goto free_and_stop; */ - return -1; + mdata->f_bw = pxframe->attrib.bwmode; + /* Todo: GI and LTF not ready for HE */ + mdata->f_gi_ltf = pxframe->attrib.sgi; - } - /* we just print warning message and let it go */ - /* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */ - /* return -1; */ /* return -1 will cause system crash on 2011/08/30! */ - return 0; - } - } + mdata->mc = IS_MCAST(pxframe->attrib.ra) ? 1 : 0; + mdata->bc = MacAddr_isBcst(pxframe->attrib.ra) ? 1 : 0; - memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); +#ifdef CONFIG_80211AX_HE + if (psta && htc_option) + mdata->a_ctrl_bsr = 1; +#endif + mdata->raw = 0; + +#ifdef BMC_ON_HIQ + if ((pxframe->xftype != RTW_TX_DRV_MGMT) + && (mdata->mc || mdata->bc) + && (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap))) { + mdata->tid = RTW_PHL_RING_CAT_HIQ; /* HIQ */ + mdata->mbssid = 0; /* ToDo: Consider MBSSID */ + mdata->hal_port = padapter->phl_role->hw_port; + } else +#endif + { + mdata->tid = pxframe->attrib.priority; + } - dhcp_flag_bcast(padapter, skb); +#ifdef CONFIG_CORE_TXSC + mdata->ampdu_density = 0; + mdata->userate_sel = 0; +#endif - if (is_vlan_tag) { - skb_push(skb, 4); - for (i = 0; i < 6; i++) - *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); - *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); - *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; + if (pxframe->xftype == RTW_TX_DRV_MGMT) { + mdata->userate_sel = 1; + mdata->f_rate = _rate_mrate2phl(pxframe->attrib.rate); + } else { + /* low rate for EAPOL/ARP/DHCP */ + if ((pxframe->attrib.ether_type == 0x888e) || + (pxframe->attrib.ether_type == 0x0806) || + (pxframe->attrib.dhcp_pkt == 1)) { + + mdata->userate_sel = 1; + if (IS_CCK_RATE(padapter->mlmeextpriv.tx_rate)) + mdata->f_rate = RTW_DATA_RATE_CCK1; + else + mdata->f_rate = RTW_DATA_RATE_OFDM6; + } else { + /* fix rate for non specail packet */ + if (padapter->fix_rate != NO_FIX_RATE) { + mdata->userate_sel = 1; + mdata->f_rate = GET_FIX_RATE(padapter->fix_rate); + mdata->f_gi_ltf = GET_FIX_RATE_SGI(padapter->fix_rate); + if (!padapter->data_fb) + mdata->dis_data_rate_fb = 1; + } else { + mdata->userate_sel = 0; } + + if (padapter->fix_bw != NO_FIX_BW) + mdata->f_bw = padapter->fix_bw; } -#if 0 - else { - if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) - is_vlan_tag = 1; + } + mdata->f_er = 0; + mdata->f_dcm = 0; + mdata->f_stbc = pxframe->attrib.stbc; + mdata->f_ldpc = pxframe->attrib.ldpc; - if (is_vlan_tag) { - if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)) - memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); - } else { - if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)) - memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); - } + mdata->band = 0; + mdata->dma_ch = 0; + mdata->spe_rpt = 0; + mdata->sw_define = 0; + +#ifdef CONFIG_XMIT_ACK + if (pxframe->ack_report) { + mdata->spe_rpt = 1; + mdata->sw_define = pxmitpriv->seq_no; +#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL + mdata->data_tx_cnt_lmt_en = 1; + mdata->data_tx_cnt_lmt = 8; +#endif + } +#endif + +#ifdef CONFIG_CORE_TXSC + mdata->pktlen = txreq->total_len; +#endif + +#ifdef RTW_PHL_TEST_FPGA + mdata->type = F_TX_TYPE; + mdata->macid = F_TX_MACID; + mdata->tid = F_TX_TID; + mdata->dma_ch = F_TX_DMACH; + //mdata->band = cap->band; + mdata->f_rate = F_TX_RATE; + mdata->f_bw = F_TX_BW; + mdata->f_gi_ltf = 0; + mdata->f_stbc = 0; + mdata->f_ldpc = 0; + + mdata->userate_sel = 1; + mdata->dis_data_rate_fb = 1; + mdata->dis_rts_rate_fb = 1; +#endif + +#ifdef RTW_PHL_DBG_CMD + if (pxframe->xftype != RTW_TX_DRV_MGMT) { + if (padapter->txForce_enable) { + if (padapter->txForce_rate != INV_TXFORCE_VAL) + mdata->f_rate = padapter->txForce_rate; + if (padapter->txForce_agg != INV_TXFORCE_VAL) + mdata->ampdu_en = padapter->txForce_agg; + if (padapter->txForce_aggnum != INV_TXFORCE_VAL) + mdata->max_agg_num = padapter->txForce_aggnum; + if (padapter->txForce_gi != INV_TXFORCE_VAL) + mdata->f_gi_ltf = padapter->txForce_gi; } -#endif /* 0 */ + } +#endif - /* check if SA is equal to our MAC */ - if (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { - /* priv->ext_stats.tx_drops++; */ - DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", - skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]); - /* goto free_and_stop; */ - return -1; +#ifdef CONFIG_CORE_TXSC + _print_txreq_mdata(mdata, __func__); +#endif + + if (pxframe->txreq_cnt > 1) { + struct rtw_t_meta_data *mdata_tmp; + txreq++; + for (idx = 1; idx < pxframe->txreq_cnt; idx++) { +#ifdef CONFIG_CORE_TXSC + mdata->pktlen = txreq->total_len; +#endif + mdata_tmp = &(txreq->mdata); + memcpy(mdata_tmp, mdata, sizeof(struct rtw_t_meta_data)); + txreq++; } } - return 0; + } -#endif /* CONFIG_BR_EXT */ -u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) + +void fill_txreq_others(_adapter *padapter, struct xmit_frame *pxframe) { - u32 addr; - struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + u32 idx = 0; - switch (pattrib->qsel) { - case 0: - case 3: - addr = BE_QUEUE_INX; - break; - case 1: - case 2: - addr = BK_QUEUE_INX; - break; - case 4: - case 5: - addr = VI_QUEUE_INX; - break; - case 6: - case 7: - addr = VO_QUEUE_INX; - break; - case 0x10: - addr = BCN_QUEUE_INX; - break; - case 0x11: /* BC/MC in PS (HIQ) */ - addr = HIGH_QUEUE_INX; - break; - case 0x13: - addr = TXCMD_QUEUE_INX; - break; - case 0x12: - default: - addr = MGT_QUEUE_INX; - break; + PHLTX_ENTER; + for (idx = 0; idx < pxframe->txreq_cnt; idx++) { + txreq->os_priv = pxframe; + txreq++; } +} - return addr; +u8 core_wlan_fill_txreq_pre(_adapter *padapter, struct xmit_frame *pxframe) +{ + u32 frag_perfr, wl_frags = 0; + + if (pxframe->xftype == RTW_TX_OS) { + get_wl_frag_paras(padapter, pxframe, &frag_perfr, &wl_frags); + if (fill_txreq_pkt_perfrag_txos(padapter, pxframe, frag_perfr, wl_frags) == _FAIL) + return _FAIL; + } else if (pxframe->xftype == RTW_TX_DRV_MGMT) { + if (fill_txreq_pkt_mgmt(padapter, pxframe) == _FAIL) + return _FAIL; + } + return _SUCCESS; } -static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) +void core_wlan_fill_txreq_post(_adapter *padapter, struct xmit_frame *pxframe) { - u8 qsel; + fill_txreq_mdata(padapter, pxframe); + fill_txreq_others(padapter, pxframe); - qsel = pattrib->priority; - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* Under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) { - if (padapter->mcc_adapterpriv.role == MCC_ROLE_GO - || padapter->mcc_adapterpriv.role == MCC_ROLE_AP) { - pattrib->qsel = QSLT_VO; /* AP interface VO queue */ - pattrib->priority = QSLT_VO; - } else { - pattrib->qsel = QSLT_BE; /* STA interface BE queue */ - pattrib->priority = QSLT_BE; - } - } else - /* Not Under MCC */ - pattrib->qsel = qsel; - } else - /* Not enable MCC */ - pattrib->qsel = qsel; -#else /* !CONFIG_MCC_MODE */ - pattrib->qsel = qsel; -#endif /* CONFIG_MCC_MODE */ +#ifdef CONFIG_PCI_HCI + /*must be called after all pkt contents modified (cache sync)*/ + fill_txreq_phyaddr(padapter, pxframe); +#endif - /* high priority packet */ - if (pattrib->hipriority_pkt) { - pattrib->qsel = QSLT_VO; - pattrib->priority = QSLT_VO; - } } -/* - * The main transmit(tx) entry - * - * Return - * 1 enqueue - * 0 success, hardware will handle this xmit frame(packet) - * <0 fail - */ - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) -// OpenHD added -static struct xmit_frame* rtl8812au_monitor_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) { - int tries; - int delay = 300; - struct xmit_frame *pmgntframe = NULL; - int n_needed_tries=0; - //RTW_WARN("OpenHD rtl8812au_monitor_alloc_mgtxmitframe begin %d\n",openhd_tx_packets_cunt); - - // OpenHD: Here a method that returns a frame if place is in the queue - // Is called 4 times with a (increasing) sleep until there is space in the queue - // If no space is in the queue after 4 calls, NULL is returned - for(tries = 30; tries >= 0; tries--) { - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - n_needed_tries++; - if(pmgntframe != NULL){ - //RTW_WARN("OpenHD rtl8812au_monitor_alloc_mgtxmitframe success %d tries:%d\n",openhd_tx_packets_cunt,n_needed_tries); - return pmgntframe; - } - //RTW_WARN("OpenHD rtl8812au_monitor_alloc_mgtxmitframe %d didn't get %d\n",openhd_tx_packets_cunt,tries); - /*if(tries==1){ - // last try, sleep long, then try again - RTW_WARN("Performing long sleep\n"); - usleep_range(3*1000,3*1000); - }else{ - rtw_udelay_os(delay); - }*/ - rtw_udelay_os(delay); - delay += delay/2; - } - //RTW_WARN("OpenHD rtl8812au_monitor_alloc_mgtxmitframe fail %d tries:%d\n",openhd_tx_packets_cunt,n_needed_tries); - return NULL; -} -s32 rtl8812au_rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) -{ - int ret = 0; - int rtap_len; - int qos_len = 0; - int dot11_hdr_len = 24; - int snap_len = 6; - unsigned char *pdata; - u16 frame_ctl; - unsigned char src_mac_addr[6]; - unsigned char dst_mac_addr[6]; - struct rtw_ieee80211_hdr *dot11_hdr; - struct ieee80211_radiotap_header *rtap_hdr; - struct ieee80211_radiotap_iterator iterator; - u8 fixed_rate = MGN_1M, sgi = 0, bwidth = 0, ldpc = 0, stbc = 0; - u16 txflags = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); +void core_wlan_fill_head(_adapter *padapter, struct xmit_frame *pxframe) +{ + u32 idx = 0; + if (pxframe->xftype == RTW_TX_OS) { + for (idx = 0; idx < pxframe->attrib.nr_frags; idx++) { + u8 *pwlanhdr = pxframe->wlhdr[idx]; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u8 *buf = skb->data; - u32 len = skb->len; - u8 category, action; - int type = -1; - openhd_tx_packets_cunt++; - //RTW_WARN("OpenHD rtl8812au_rtw_monitor_xmit_entry %d\n",openhd_tx_packets_cunt); + if (!pwlanhdr) { + PHLTX_ERR; + continue; + } - if (skb) - rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + rtw_make_wlanhdr(padapter, pwlanhdr, &pxframe->attrib); //rtw_core_make_wlanhdr(padapter, pwlanhdr, pxframe); - if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) - goto fail; + if (idx == (pxframe->attrib.nr_frags - 1)) + ClearMFrag(pwlanhdr); + else + SetMFrag(pwlanhdr); - rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; - if (unlikely(rtap_hdr->it_version)) - goto fail; + if (pxframe->attrib.iv_len) { + update_attrib_sec_iv_info(padapter, &pxframe->attrib); + _rtw_memcpy((pwlanhdr+pxframe->attrib.hdrlen), pxframe->attrib.iv, pxframe->attrib.iv_len); + } - rtap_len = ieee80211_get_radiotap_len(skb->data); - if (unlikely(skb->len < rtap_len)) - goto fail; + if (idx == 0 && !pxframe->attrib.amsdu) { + /* Add LLC/SNAP to first fragment */ + rtw_put_snap(pwlanhdr+pxframe->attrib.hdrlen+pxframe->attrib.iv_len, + pxframe->attrib.ether_type); + } - //RTW_WARN("OpenHD rtl8812au_rtw_monitor_xmit_entry hmX %d\n",openhd_tx_packets_cunt); - //RTW_WARN("OpenHD: calling monitor_alloc_mgtxmitframe X"); - if ((pmgntframe = rtl8812au_monitor_alloc_mgtxmitframe(pxmitpriv)) == NULL) { - DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe); - openhd_tx_error_count++; - RTW_WARN("OpenHD: monitor_alloc_mgtxmitframe - tx busy %d",openhd_tx_error_count); - goto fail; - //return NETDEV_TX_BUSY; - } - //RTW_WARN("OpenHD rtl8812au_rtw_monitor_xmit_entry hmY %d\n",openhd_tx_packets_cunt); +#ifdef RTW_PHL_TEST_FPGA +{ + struct rtw_ieee80211_hdr *p = (struct rtw_ieee80211_hdr *)pwlanhdr; + unsigned short *fctrl; + unsigned int pktlen = 0; + u16 *qc; - //ret = rtw_ieee80211_radiotap_iterator_init(&iterator, rtap_hdr, skb->len, NULL); - ret = ieee80211_radiotap_iterator_init(&iterator, rtap_hdr, skb->len, NULL); - while (!ret) { - //ret = rtw_ieee80211_radiotap_iterator_next(&iterator); - ret = ieee80211_radiotap_iterator_next(&iterator); + test_seq++; + test_seq = test_seq%0xFFF; + SetSeqNum(p, test_seq); +} +#endif - if (ret) - continue; + } + } +} - /* see if this argument is something we can use */ - switch (iterator.this_arg_index) { - case IEEE80211_RADIOTAP_RATE: /* u8 */ - fixed_rate = *iterator.this_arg; - break; +void core_wlan_fill_tail(_adapter *padapter, struct xmit_frame *pxframe) +{ + ; - case IEEE80211_RADIOTAP_TX_FLAGS: - txflags = get_unaligned_le16(iterator.this_arg); - break; +} - case IEEE80211_RADIOTAP_MCS: { /* u8,u8,u8 */ - u8 mcs_have = iterator.this_arg[0]; - if (mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_MCS) { - fixed_rate = iterator.this_arg[2] & 0x7f; - if(fixed_rate > 31) - fixed_rate = 0; - fixed_rate += MGN_MCS0; - } - if ((mcs_have & 4) && - (iterator.this_arg[1] & 4)) - sgi = 1; - if ((mcs_have & 1) && - (iterator.this_arg[1] & 1)) - bwidth = 1; - if ((mcs_have & 0x10) && - (iterator.this_arg[1] & 0x10)) - ldpc = 1; - if ((mcs_have & 0x20)) - stbc = (iterator.this_arg[1] >> 5) & 3; - } - break; - case IEEE80211_RADIOTAP_VHT: { - /* u16 known, u8 flags, u8 bandwidth, u8 mcs_nss[4], u8 coding, u8 group_id, u16 partial_aid */ - u8 known = iterator.this_arg[0]; - u8 flags = iterator.this_arg[2]; - unsigned int mcs, nss; - if((known & 4) && (flags & 4)) - sgi = 1; - if((known & 1) && (flags & 1)) - stbc = 1; - if(known & 0x40) { - bwidth = iterator.this_arg[3] & 0x1f; - if(bwidth>=1 && bwidth<=3) - bwidth = 1; // 40 MHz - else if(bwidth>=4 && bwidth<=10) - bwidth = 2; // 80 MHz - else - bwidth = 0; // 20 MHz - } - if(iterator.this_arg[8] & 1) - ldpc = 1; - mcs = (iterator.this_arg[4]>>4) & 0x0f; - nss = iterator.this_arg[4] & 0x0f; - if(nss > 0) { - if(nss > 4) nss = 4; - if(mcs > 9) mcs = 9; - fixed_rate = MGN_VHT1SS_MCS0 + ((nss-1)*10 + mcs); - } - } - break; +u8 core_wlan_fill_tkip_mic(_adapter *padapter, struct xmit_frame *pxframe) +{ + u8 *llc = NULL; + u8 *payload = NULL; + u8 mic[8] = {0x0}; + struct mic_data micdata; + struct pkt_attrib *pattrib = &pxframe->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + s8 bmcst = IS_MCAST(pattrib->ra); + u8 priority[4] = {0x0}; + int i = 0; + struct rtw_xmit_req *xf_txreq = pxframe->phl_txreq; + struct rtw_pkt_buf_list *pkt_list = NULL; - default: - break; - } - } - /* Skip the ratio tap header */ - skb_pull(skb, rtap_len); + if (pattrib->encrypt == _TKIP_) { + u8 null_key[16] = {0x0}; -// dot11_hdr = (struct ieee80211_hdr *)skb->data; -// frame_ctl = le16_to_cpu(dot11_hdr->frame_control); - /* Check if the QoS bit is set */ + /* set TKIP MIC key */ + if (bmcst) { + if (_rtw_memcmp( + psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, + null_key, 16) == _TRUE) + return _FAIL; - pattrib = &pmgntframe->attrib; - update_monitor_frame_attrib(padapter, pattrib); + rtw_secmicsetkey(&micdata, + psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); + } else { + if (_rtw_memcmp( + &pattrib->dot11tkiptxmickey.skey[0], + null_key, 16) == _TRUE) + return _FAIL; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]); + } - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + /* set DA, SA */ + rtw_secmicappend(&micdata, &pattrib->dst[0], 6); + rtw_secmicappend(&micdata, &pattrib->src[0], 6); - _rtw_memcpy(pframe, (void*)skb->data, skb->len); + if (pattrib->qos_en) + priority[0] = pattrib->priority; - pattrib->pktlen = skb->len; + /* set priority */ + rtw_secmicappend(&micdata, &priority[0], 4); - //printk("**** rt mcs %x rate %x raid %d sgi %d bwidth %d ldpc %d stbc %d txflags %x\n", fixed_rate, pattrib->rate, pattrib->raid, sgi, bwidth, ldpc, stbc, txflags); - pattrib->rate = fixed_rate; - pattrib->sgi = sgi; - pattrib->bwmode = bwidth; // 0-20 MHz, 1-40 MHz, 2-80 MHz - pattrib->ldpc = ldpc; - pattrib->stbc = stbc; - pattrib->retry_ctrl = (txflags & 0x08)?_FALSE:_TRUE; + /* set LLC; TBD: should check if LLC is existed or not */ + llc = pxframe->wlhdr[0] + pxframe->attrib.hdrlen + pxframe->attrib.iv_len; + rtw_secmicappend(&micdata, llc, SNAP_SIZE + sizeof(u16)); + /* set MSDU payload */ + pkt_list = (struct rtw_pkt_buf_list *) xf_txreq->pkt_list; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + /*ignore hdr move to payload*/ + pkt_list ++; + /*for loop ignore tail*/ + for (i = 1; i < xf_txreq->pkt_cnt - 1; i++) { + rtw_secmicappend(&micdata, pkt_list->vir_addr, pkt_list->length); + pkt_list ++; + } - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; + /* calculate MIC */ + rtw_secgetmic(&micdata, &mic[0]); - pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(padapter, pmgntframe); - DBG_COUNTER(padapter->tx_logs.core_tx); - pxmitpriv->tx_pkts++; - pxmitpriv->tx_bytes += skb->len; + /* append MIC to the last tail */ + _rtw_memcpy(pxframe->wltail[pxframe->attrib.nr_frags-1], &(mic[0]), 8); + } -fail: - rtw_skb_free(skb); - return NETDEV_TX_OK; + return _SUCCESS; } -// OpenHD: ioctl_cfg80211 rtw_cfg80211_monitor_if_xmit_entry goes - over some hoops - all the way to here -s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) + +static void core_wlan_sw_encrypt(_adapter *padapter, struct xmit_frame *pxframe) { - return rtl8812au_rtw_monitor_xmit_entry(skb,ndev); - /*u16 frame_ctl; - struct ieee80211_radiotap_header rtap_hdr; - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct pkt_file pktfile; - struct rtw_ieee80211_hdr *pwlanhdr; - struct pkt_attrib *pattrib; - struct xmit_frame *pmgntframe; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - unsigned char *pframe; - u8 dummybuf[32]; - int len = skb->len, rtap_len; -#ifdef CONFIG_MONITOR_MODE_XMIT - int consume; -#endif // CONFIG_MONITOR_MODE_XMIT - if (likely(skb)) - rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + struct pkt_attrib *attrib; + u8 res; -#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL - if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) - goto fail; - _rtw_open_pktfile((_pkt *)skb, &pktfile); - _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header)); - rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr)); - if (unlikely(rtap_hdr.it_version)) - goto fail; + attrib = &pxframe->attrib; + if (!attrib->encrypt) + return; + if (!attrib->bswenc) + return; - if (unlikely(skb->len < rtap_len)) - goto fail; + /* convert txreq to one piece */ + res = merge_txreq_to_one_piece(padapter, pxframe); + if (res != _SUCCESS) { + RTW_ERR("%s: fail alloc buffer for sw enc!\n", __func__); + return; + } + xmitframe_swencrypt(padapter, pxframe); +} -#ifdef CONFIG_MONITOR_MODE_XMIT - len -= sizeof(struct ieee80211_radiotap_header); - rtap_len -= sizeof(struct ieee80211_radiotap_header); +#ifdef CONFIG_TX_AMSDU_SW_MODE +static bool core_tx_amsdu_timeout(_adapter *padapter, struct pkt_attrib *pattrib) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u8 amsdu_timeout; - while(rtap_len) { - consume = rtap_len > sizeof(dummybuf) ? sizeof(dummybuf) : rtap_len; - _rtw_pktfile_read(&pktfile, dummybuf, consume); - rtap_len -= consume; - len -= consume; - } -#else // CONFIG_MONITOR_MODE_XMIT - if (rtap_len != 12) { - RTW_INFO("radiotap len (should be 14): %d\n", rtap_len); - goto fail; - } - _rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header)); - len = len - rtap_len; -#endif // CONFIG_MONITOR_MODE_XMIT -#endif // CONFIG_CUSTOMER_ALIBABA_GENERAL - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - rtw_udelay_os(500); - goto fail; - } + amsdu_timeout = rtw_amsdu_get_timer_status(padapter, pattrib->priority); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; -// _rtw_memcpy(pframe, (void *)checking, len); - _rtw_pktfile_read(&pktfile, pframe, len); + if (amsdu_timeout == RTW_AMSDU_TIMER_UNSET) { + rtw_amsdu_set_timer_status(padapter, + pattrib->priority, RTW_AMSDU_TIMER_SETTING); + rtw_amsdu_set_timer(padapter, pattrib->priority); + pxmitpriv->amsdu_debug_set_timer++; + return false; + } else if (amsdu_timeout == RTW_AMSDU_TIMER_SETTING) { + return false; + } else if (amsdu_timeout == RTW_AMSDU_TIMER_TIMEOUT) { + rtw_amsdu_set_timer_status(padapter, + pattrib->priority, RTW_AMSDU_TIMER_UNSET); + pxmitpriv->amsdu_debug_timeout++; + return true; + } + return false; +} - // Check DATA/MGNT frames - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl); - if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { +/* 'pxframes[]' is array to store xframe to do AMSDU whose size is 'max_xf_nr', + * and return value is real used size. If return size is 1, then set 'amsdu' to + * decide normal frame or AMSDU one. + */ +static int core_tx_amsdu_dequeue(_adapter *padapter, struct xmit_frame *pxframes[], + int max_xf_nr, bool *amsdu) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct xmit_frame *pxframe; + int tx_amsdu = rtw_min(padapter->tx_amsdu, max_xf_nr); + int tx_amsdu_rate = padapter->tx_amsdu_rate; + int current_tx_rate = dvobj->traffic_stat.cur_tx_tp; + int num_frame; + int nr_xf; - pattrib = &pmgntframe->attrib; - update_monitor_frame_attrib(padapter, pattrib); + if (tx_amsdu == 0) + goto dequeue_normal_pkt; - if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) - pattrib->rate = MGN_24M; + if (!MLME_IS_STA(padapter)) + goto dequeue_normal_pkt; - } else { + if (tx_amsdu >= 2 && tx_amsdu_rate && current_tx_rate < tx_amsdu_rate) + goto dequeue_normal_pkt; - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + /*No amsdu when wifi_spec on*/ + if (pregpriv->wifi_spec == 1) + goto dequeue_normal_pkt; - } - pattrib->retry_ctrl = _FALSE; - pattrib->pktlen = len; - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; - pattrib->last_txcmdsz = pattrib->pktlen; + pxframe = rtw_get_xframe(pxmitpriv, &num_frame); + if (num_frame == 0 || !pxframe) + return 0; - dump_mgntframe(padapter, pmgntframe); + if (num_frame < tx_amsdu) { /* Not enough MSDU for specific A-MSDU */ + if (!core_tx_amsdu_timeout(padapter, &pxframe->attrib)) + return 0; /* Not timeout yet */ + } -fail: -#ifdef CONFIG_MONITOR_MODE_XMIT - rtw_endofpktfile(&pktfile); -#endif // CONFIG_MONITOR_MODE_XMIT - rtw_skb_free(skb); - return 0;*/ -} -#endif + for (nr_xf = 0; nr_xf < tx_amsdu; nr_xf++) { + pxframe = rtw_get_xframe(pxmitpriv, &num_frame); -/* - * - * Return _TRUE when frame has been put to queue, otherwise return _FALSE. - */ -static u8 xmit_enqueue(struct _ADAPTER *a, struct xmit_frame *frame) -{ - struct sta_info *sta = NULL; - struct pkt_attrib *attrib = NULL; - _irqL irqL; - _list *head; - u8 ret = _TRUE; + if (num_frame == 0 || !pxframe) + break; + if (!check_amsdu(pxframe)) + break; - attrib = &frame->attrib; - sta = attrib->psta; - if (!sta) - return _FALSE; + /* TODO: check if size is over peer's capability */ - _enter_critical_bh(&sta->tx_queue.lock, &irqL); + pxframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, + pxmitpriv->hwxmit_entry); - head = get_list_head(&sta->tx_queue); + pxframes[nr_xf] = pxframe; + } - if ((rtw_is_list_empty(head) == _TRUE) && (!sta->tx_q_enable)) { - ret = _FALSE; - goto exit; + if (nr_xf == 0) { + if (num_frame > 0) + goto dequeue_normal_pkt; + RTW_WARN("%s: nr_xf=0, num_frame=%d\n", __func__, num_frame); + return 0; } - rtw_list_insert_tail(&frame->list, head); - RTW_INFO(FUNC_ADPT_FMT ": en-queue tx pkt for macid=%d\n", - FUNC_ADPT_ARG(a), sta->cmn.mac_id); + if (nr_xf < AMSDU_DEBUG_MAX_COUNT) + pxmitpriv->amsdu_debug_coalesce[nr_xf-1]++; + else + pxmitpriv->amsdu_debug_coalesce[AMSDU_DEBUG_MAX_COUNT-1]++; -exit: - _exit_critical_bh(&sta->tx_queue.lock, &irqL); + *amsdu = (nr_xf == 1 && tx_amsdu >= 2) ? false : true; - return ret; + return nr_xf; + +dequeue_normal_pkt: + pxframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, + pxmitpriv->hwxmit_entry); + if (!pxframe) + return 0; + + pxframes[0] = pxframe; + *amsdu = false; + + return 1; } -static void xmit_dequeue(struct sta_info *sta) +static bool core_tx_amsdu_dump(_adapter *padapter, struct xmit_frame *pxframes[], + int xf_nr, bool amsdu) { - struct _ADAPTER *a; - _irqL irqL; - _list *head, *list; - struct xmit_frame *frame; + struct xmit_frame *head_xframe; + struct pkt_attrib *head_attrib; + u32 pktlen; + /* prepare head xmitframe */ + head_xframe = pxframes[0]; + head_attrib = &head_xframe->attrib; - a = sta->padapter; + if (xf_nr == 1 && !amsdu) + goto dump_pkt; - _enter_critical_bh(&sta->tx_queue.lock, &irqL); + rtw_coalesce_tx_amsdu(padapter, pxframes, xf_nr, amsdu, &pktlen); - head = get_list_head(&sta->tx_queue); + /* update proper attribute */ + head_attrib->amsdu = 1; + head_attrib->pkt_hdrlen = 0; + head_attrib->pktlen = pktlen; - do { - if (rtw_is_list_empty(head) == _TRUE) - break; +dump_pkt: + if (core_tx_prepare_phl(padapter, head_xframe) == FAIL) + goto abort_core_tx; - list = get_next(head); - rtw_list_delete(list); - frame = LIST_CONTAINOR(list, struct xmit_frame, list); - RTW_INFO(FUNC_ADPT_FMT ": de-queue tx frame of macid=%d\n", - FUNC_ADPT_ARG(a), sta->cmn.mac_id); + if (core_tx_call_phl(padapter, head_xframe, NULL) == FAIL) + goto abort_core_tx; - rtw_hal_xmit(a, frame); - } while (1); + return true; + +abort_core_tx: + core_tx_free_xmitframe(padapter, head_xframe); - _exit_critical_bh(&sta->tx_queue.lock, &irqL); + return true; } -void rtw_xmit_dequeue_callback(_workitem *work) +void core_tx_amsdu_tasklet(_adapter *padapter) { - struct sta_info *sta; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxframes[5]; + int xf_nr; + bool amsdu; + pxmitpriv->amsdu_debug_tasklet++; - sta = container_of(work, struct sta_info, tx_q_work); - xmit_dequeue(sta); + while (1) { + xf_nr = core_tx_amsdu_dequeue(padapter, pxframes, ARRAY_SIZE(pxframes), + &amsdu); + if (xf_nr == 0) + break; + + pxmitpriv->amsdu_debug_dequeue++; + + core_tx_amsdu_dump(padapter, pxframes, xf_nr, amsdu); + } } -void rtw_xmit_queue_set(struct sta_info *sta) +static s32 core_tx_amsdu_enqueue(_adapter *padapter, struct xmit_frame *pxframe) { - _irqL irqL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxframe->attrib; + int tx_amsdu = padapter->tx_amsdu; + u8 amsdu_timeout; + s32 res; - _enter_critical_bh(&sta->tx_queue.lock, &irqL); + if (MLME_IS_STA(padapter) && check_amsdu_tx_support(padapter)) { + if (IS_AMSDU_AMPDU_VALID(pattrib)) + goto enqueue; + } - if (sta->tx_q_enable) { - RTW_WARN(FUNC_ADPT_FMT ": duplicated set!\n", - FUNC_ADPT_ARG(sta->padapter)); - goto exit; + return FAIL; + +enqueue: + _rtw_spinlock_bh(&pxmitpriv->lock); + + res = rtw_xmitframe_enqueue(padapter, pxframe); + if (res == _FAIL) { + _rtw_spinunlock_bh(&pxmitpriv->lock); + return FAIL; } - sta->tx_q_enable = 1; - RTW_INFO(FUNC_ADPT_FMT ": enable queue TX for macid=%d\n", - FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id); -exit: - _exit_critical_bh(&sta->tx_queue.lock, &irqL); + pxmitpriv->amsdu_debug_enqueue++; + + if (tx_amsdu >= 2) { + amsdu_timeout = rtw_amsdu_get_timer_status(padapter, pattrib->priority); + if (amsdu_timeout == RTW_AMSDU_TIMER_SETTING) { + rtw_amsdu_cancel_timer(padapter, pattrib->priority); + rtw_amsdu_set_timer_status(padapter, pattrib->priority, + RTW_AMSDU_TIMER_UNSET); + } + } + + _rtw_spinunlock_bh(&pxmitpriv->lock); + + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + + return _TRUE; } +#endif /* CONFIG_TX_AMSDU_SW_MODE */ -void rtw_xmit_queue_clear(struct sta_info *sta) +s32 core_tx_prepare_phl(_adapter *padapter, struct xmit_frame *pxframe) { - _irqL irqL; - - _enter_critical_bh(&sta->tx_queue.lock, &irqL); + if (core_wlan_fill_txreq_pre(padapter, pxframe) == _FAIL) + return FAIL; - if (!sta->tx_q_enable) { - RTW_WARN(FUNC_ADPT_FMT ": tx queue for macid=%d " - "not be enabled!\n", - FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id); - goto exit; + if (pxframe->xftype == RTW_TX_OS) { + core_wlan_fill_head(padapter, pxframe); + if (core_wlan_fill_tkip_mic(padapter, pxframe) == _FAIL) { + RTW_ERR("core_wlan_fill_tkip_mic FAIL\n"); + return FAIL; + } } + core_wlan_fill_tail(padapter, pxframe); + core_wlan_sw_encrypt(padapter, pxframe); - sta->tx_q_enable = 0; - RTW_INFO(FUNC_ADPT_FMT ": disable queue TX for macid=%d\n", - FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id); - - _set_workitem(&sta->tx_q_work); + core_wlan_fill_txreq_post(padapter, pxframe); -exit: - _exit_critical_bh(&sta->tx_queue.lock, &irqL); + return SUCCESS; } -/* - * The main transmit(tx) entry post handle - * - * Return - * 1 enqueue - * 0 success, hardware will handle this xmit frame(packet) - * <0 fail - */ -s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt) + +s32 core_tx_call_phl(_adapter *padapter, struct xmit_frame *pxframe, void *txsc_pkt) { -#ifdef CONFIG_AP_MODE - _irqL irqL0; -#endif + struct rtw_xmit_req *txreq = NULL; + void *phl = padapter->dvobj->phl; + u32 idx = 0; + u8 txreq_cnt = 0; +#ifdef CONFIG_CORE_TXSC + struct rtw_xmit_req *ptxsc_txreq = NULL; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - s32 res; +#endif - res = update_attrib(padapter, pkt, &pxmitframe->attrib); +#ifdef CONFIG_CORE_TXSC + struct txsc_pkt_entry *ptxsc_pkt = (struct txsc_pkt_entry *)txsc_pkt; + if (ptxsc_pkt) + ptxsc_txreq = ptxsc_pkt->ptxreq; -#ifdef CONFIG_MCC_MODE - /* record data kernel TX to driver to check MCC concurrent TX */ - rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen); -#endif /* CONFIG_MCC_MODE */ + txreq = pxframe ? pxframe->phl_txreq : ptxsc_txreq; + txreq_cnt = pxframe ? pxframe->txreq_cnt : 1; +#else + txreq = pxframe->phl_txreq; + txreq_cnt = pxframe->txreq_cnt; +#endif -#ifdef CONFIG_WAPI_SUPPORT - if (pxmitframe->attrib.ether_type != 0x88B4) { - if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { - WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); - res = _FAIL; - } + for (idx = 0; idx < txreq_cnt; idx++) { + +#ifdef RTW_PHL_TEST_FPGA + core_add_record(padapter, REC_TX_PHL, txreq); +#endif + + if (rtw_phl_add_tx_req(phl, txreq) != RTW_PHL_STATUS_SUCCESS) + return FAIL; + + rtw_phl_tx_req_notify(phl); + + + txreq++; } + + /* should count tx status after add tx req is success */ +#ifdef CONFIG_CORE_TXSC + if (ptxsc_txreq != NULL) + rtw_count_tx_stats_tx_req(padapter, ptxsc_txreq, ptxsc_pkt->psta); + else #endif - if (res == _FAIL) { - /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ -#ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); + rtw_count_tx_stats(padapter, pxframe, pxframe->attrib.pktlen); + + return SUCCESS; +} + +s32 core_tx_per_packet(_adapter *padapter, struct xmit_frame *pxframe, + struct sk_buff **pskb, struct sta_info *psta) +{ +#if defined(CONFIG_AP_MODE) || defined(CONFIG_CORE_TXSC) + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; #endif - rtw_free_xmitframe(pxmitpriv, pxmitframe); - return -1; - } - pxmitframe->pkt = pkt; - rtw_led_tx_control(padapter, pxmitframe->attrib.dst); + if (core_tx_update_xmitframe(padapter, pxframe, pskb, psta, RTW_TX_OS) == FAIL) + goto abort_tx_per_packet; - do_queue_select(padapter, &pxmitframe->attrib); +#ifdef CONFIG_80211N_HT + if ((pxframe->attrib.ether_type != 0x0806) + && (pxframe->attrib.ether_type != 0x888e) + && (pxframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(padapter, pxframe, _TRUE); +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_TX_AMSDU_SW_MODE + if (core_tx_amsdu_enqueue(padapter, pxframe) == _TRUE) + return SUCCESS; /* queued to do AMSDU */ +#endif + + if (core_tx_prepare_phl(padapter, pxframe) == FAIL) + goto abort_tx_per_packet; #ifdef CONFIG_AP_MODE - _enter_critical_bh(&pxmitpriv->lock, &irqL0); - if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { - _exit_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinlock_bh(&pxmitpriv->lock); + if (xmitframe_enqueue_for_sleeping_sta(padapter, pxframe) == _TRUE) { + _rtw_spinunlock_bh(&pxmitpriv->lock); DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); - return 1; + return SUCCESS; } - _exit_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinunlock_bh(&pxmitpriv->lock); #endif - if (xmit_enqueue(padapter, pxmitframe) == _TRUE) - return 1; +#if !defined(CONFIG_CORE_TXSC) || defined(CONFIG_RTW_DATA_BMC_TO_UC) + if (core_tx_call_phl(padapter, pxframe, NULL) == SUCCESS) +#endif + return SUCCESS; - /* pre_xmitframe */ - if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) - return 1; - return 0; +abort_tx_per_packet: + if (pxframe == NULL) { + rtw_os_pkt_complete(padapter, *pskb); + } else { + if (pxframe->pkt == NULL) + rtw_os_pkt_complete(padapter, *pskb); + core_tx_free_xmitframe(padapter, pxframe); + } + + return FAIL; } -/* - * The main transmit(tx) entry - * - * Return - * 1 enqueue - * 0 success, hardware will handle this xmit frame(packet) - * <0 fail - */ -s32 rtw_xmit(_adapter *padapter, _pkt **ppkt, u16 os_qid) +s32 rtw_core_tx(_adapter *padapter, struct sk_buff **pskb, struct sta_info *psta, u16 os_qid) { - static systime start = 0; - static u32 drop_cnt = 0; + struct xmit_frame *pxframe = NULL; +#if defined(CONFIG_AP_MODE) || defined(CONFIG_CORE_TXSC) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct xmit_frame *pxmitframe = NULL; - s32 res; -#ifdef CONFIG_LAYER2_ROAMING - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sk_buff *skb = (struct sk_buff *)(*ppkt); - _irqL irqL; +#endif + s32 res = 0; +#ifdef CONFIG_CORE_TXSC + struct txsc_pkt_entry txsc_pkt; #endif - DBG_COUNTER(padapter->tx_logs.core_tx); +#ifdef CONFIG_CORE_TXSC + if (txsc_get_sc_cached_entry(padapter, *pskb, &txsc_pkt) == _SUCCESS) + goto core_txsc; +#endif - if (IS_CH_WAITING(adapter_to_rfctl(padapter))) - return -1; + if (core_tx_alloc_xmitframe(padapter, &pxframe, os_qid) == FAIL) + goto abort_core_tx; - if ((rtw_linked_check(padapter) == _FALSE) -#ifdef CONFIG_LAYER2_ROAMING - &&(!padapter->mlmepriv.roam_network) -#endif - ) - return -1; + if (core_tx_update_pkt(padapter, pxframe, pskb) == FAIL) + goto abort_core_tx; - if (start == 0) - start = rtw_get_current_time(); +#if defined(CONFIG_AP_MODE) + if (MLME_STATE(padapter) & WIFI_AP_STATE) { + _list f_list; - pxmitframe = rtw_alloc_xmitframe(pxmitpriv, os_qid); + res = rtw_ap_addr_resolve(padapter, os_qid, pxframe, *pskb, &f_list); + if (res == _FAIL) + goto abort_core_tx; - if (rtw_get_passing_time_ms(start) > 2000) { - if (drop_cnt) - RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt); - start = rtw_get_current_time(); - drop_cnt = 0; - } + #if defined(CONFIG_RTW_WDS) || CONFIG_RTW_DATA_BMC_TO_UC + if (!rtw_is_list_empty(&f_list)) { + _list *list = get_next(&f_list); + struct xmit_frame *fframe; - if (pxmitframe == NULL) { - drop_cnt++; - /*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/ - DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe); - return -1; - } + while ((rtw_end_of_queue_search(&f_list, list)) == _FALSE) { + fframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&fframe->list); -#ifdef CONFIG_BR_EXT - if (!adapter_use_wds(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { - void *br_port = NULL; + if (res == RTW_ORI_NO_NEED && rtw_is_list_empty(&f_list)) { + fframe->pkt = pxframe->pkt; /*last frame */ + pxframe->pkt = NULL; + } else { + fframe->pkt = rtw_skb_copy(*pskb); + } - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; - #else - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); - #endif + if (!fframe->pkt) { + if (res == RTW_ORI_NO_NEED && IS_MCAST(pxframe->attrib.dst)) + res = _SUCCESS; - if (br_port) { - res = rtw_br_client_tx(padapter, ppkt); - if (res == -1) { - rtw_free_xmitframe(pxmitpriv, pxmitframe); - DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); - return -1; + core_tx_free_xmitframe(padapter, fframe); + continue; + } + + core_tx_per_packet(padapter, fframe, &fframe->pkt, NULL); } } + #endif + + if (res == RTW_ORI_NO_NEED) { + core_tx_free_xmitframe(padapter, pxframe); + return SUCCESS; + } } -#endif /* CONFIG_BR_EXT */ +#endif /* defined(CONFIG_AP_MODE) */ #ifdef CONFIG_LAYER2_ROAMING - if ((pmlmepriv->roam_network) && (skb->protocol != htons(0x888e))) { /* eapol never enqueue.*/ - pxmitframe->pkt = *ppkt; - rtw_list_delete(&pxmitframe->list); - _enter_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); - rtw_list_insert_tail(&(pxmitframe->list), get_list_head(&(pxmitpriv->rpkt_queue))); - _exit_critical_bh(&pxmitpriv->rpkt_queue.lock, &irqL); - return 1; + if ((padapter->mlmepriv.roam_network) && ((*pskb)->protocol != htons(0x888e))) { /* eapol never enqueue.*/ + pxframe->pkt = *pskb; + rtw_list_delete(&pxframe->list); + _rtw_spinlock_bh(&pxmitpriv->rpkt_queue.lock); + rtw_list_insert_tail(&(pxframe->list), get_list_head(&(pxmitpriv->rpkt_queue))); + _rtw_spinunlock_bh(&pxmitpriv->rpkt_queue.lock); + return SUCCESS; } #endif -#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) - if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) { - _list b2u_list; + res = core_tx_per_packet(padapter, pxframe, pskb, psta); + if (res == FAIL) + return FAIL; - #ifdef CONFIG_RTW_MESH - if (MLME_IS_MESH(padapter)) - res = rtw_mesh_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list); - else - #endif - res = rtw_ap_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list); - if (res == RTW_RA_RESOLVING) - return 1; - if (res == _FAIL) - return -1; +#ifdef CONFIG_CORE_TXSC + txsc_add_sc_cache_entry(padapter, pxframe, &txsc_pkt); + +core_txsc: + + if (txsc_apply_sc_cached_entry(padapter, &txsc_pkt) == _FAIL) + goto abort_core_tx; + + if (core_tx_call_phl(padapter, pxframe, &txsc_pkt) == FAIL) + goto abort_core_tx; +#endif - #if CONFIG_RTW_DATA_BMC_TO_UC - if (!rtw_is_list_empty(&b2u_list)) { - _list *list = get_next(&b2u_list); - struct xmit_frame *b2uframe; + return SUCCESS; - while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) { - b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); - list = get_next(list); - rtw_list_delete(&b2uframe->list); +abort_core_tx: + if (pxframe == NULL) { +#ifdef CONFIG_CORE_TXSC + if (txsc_pkt.ptxreq) + txsc_free_txreq(padapter, txsc_pkt.ptxreq); + else +#endif + rtw_os_pkt_complete(padapter, *pskb); + } else { + if (pxframe->pkt == NULL) + rtw_os_pkt_complete(padapter, *pskb); - b2uframe->pkt = rtw_os_pkt_copy(*ppkt); - if (!b2uframe->pkt) { - if (res == RTW_BMC_NO_NEED) - res = _SUCCESS; - rtw_free_xmitframe(pxmitpriv, b2uframe); - continue; - } + core_tx_free_xmitframe(padapter, pxframe); + } - rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt); - } - } + return FAIL; +} + +enum rtw_phl_status +rtw_core_tx_recycle(void *drv_priv, struct rtw_xmit_req *txreq) +{ + _adapter *padapter = NULL; + struct xmit_frame *pxframe = NULL; +#ifdef CONFIG_CORE_TXSC + struct xmit_txreq_buf *ptxreq_buf = NULL; +#endif + + if (txreq->os_priv == NULL) { + RTW_ERR("NULL txreq!\n"); + return RTW_PHL_STATUS_FAILURE; + } + +#ifdef CONFIG_CORE_TXSC + if (txreq->treq_type == RTW_PHL_TREQ_TYPE_CORE_TXSC) { + ptxreq_buf = (struct xmit_txreq_buf *)txreq->os_priv; + padapter = ptxreq_buf->adapter; + #ifdef RTW_PHL_DBG_CMD + core_add_record(padapter, REC_TX_PHL_RCC, txreq); #endif + txsc_free_txreq(padapter, txreq); + return RTW_PHL_STATUS_SUCCESS; + } +#endif /* CONFIG_CORE_TXSC */ - if (res == RTW_BMC_NO_NEED) { - rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe); - return 0; - } + pxframe = (struct xmit_frame *)txreq->os_priv; + if (pxframe == NULL) { + RTW_ERR("%s: NULL xmitframe !!\n", __func__); + rtw_warn_on(1); + return RTW_PHL_STATUS_FAILURE; } -#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) */ - pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */ - res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt); + padapter = pxframe->padapter; - return res; + #ifdef RTW_PHL_DBG_CMD + core_add_record(padapter, REC_TX_PHL_RCC, txreq); + #endif + + #ifdef CONFIG_PCI_HCI + core_recycle_txreq_phyaddr(padapter, txreq); + #endif + core_tx_free_xmitframe(padapter, pxframe); + + return RTW_PHL_STATUS_SUCCESS; } +#endif + #ifdef CONFIG_TDLS sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) { sint ret = _FALSE; - _irqL irqL; struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -5521,12 +8217,12 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra return ret; } - _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + _rtw_spinlock_bh(&ptdls_sta->sleep_q.lock); if (ptdls_sta->state & WIFI_SLEEP_STATE) { rtw_list_delete(&pxmitframe->list); - /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + /* _rtw_spinlock_bh(&psta->sleep_q.lock); */ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q)); @@ -5556,12 +8252,12 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra /* Transmit TDLS PTI via AP */ if (ptdls_sta->sleepq_len == 1) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_ISSUE_PTI); ret = _TRUE; } - _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + _rtw_spinunlock_bh(&ptdls_sta->sleep_q.lock); } return ret; @@ -5608,100 +8304,9 @@ inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe) } #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) -#ifdef CONFIG_RTW_MGMT_QUEUE -u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) -{ - _irqL irqL; - struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *psta = pattrib->psta; - struct sta_priv *pstapriv = &padapter->stapriv; - bool update_tim = _FALSE; - u8 ret = _TRUE; - - if (is_broadcast_mac_addr(pattrib->ra) || pattrib->ps_dontq) - return _FALSE; - - if (psta == NULL) { - RTW_INFO("%s, psta==NUL, pattrib->ra:"MAC_FMT"\n", - __func__, MAC_ARG(pattrib->ra)); - return _FALSE; - } - - if (!(psta->state & WIFI_ASOC_STATE)) { - DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link); - RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state); - return _FALSE; - } - - _enter_critical_bh(&psta->mgmt_sleep_q.lock, &irqL); - - if (psta->state & WIFI_SLEEP_STATE && - rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) { - - rtw_list_delete(&pxmitframe->list); - rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->mgmt_sleep_q)); - psta->mgmt_sleepq_len++; - - #ifdef DBG_MGMT_QUEUE - RTW_INFO("%s attrib->ra:"MAC_FMT" seq_num = %u, subtype = 0x%x\n", - __func__, MAC_ARG(pattrib->ra), pattrib->seqnum, pattrib->subtype); - #endif - - if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid))) - update_tim = _TRUE; - - rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - - /* upate BCN for TIM IE */ - if (update_tim == _TRUE) - _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer mgmt frame"); - - ret = RTW_QUEUE_MGMT; - DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast); - } - - _exit_critical_bh(&psta->mgmt_sleep_q.lock, &irqL); - - return ret; -} - -static void dequeue_mgmt_xmitframe_to_sleepq(_adapter *padapter, struct sta_info *psta, _queue *pframequeue) -{ - sint ret; - _list *plist, *phead; - struct tx_servq *ptxservq; - struct pkt_attrib *pattrib; - struct xmit_frame *pxmitframe; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct hw_xmit *phwxmits = pxmitpriv->hwxmits; - u8 mgmt_idx = pxmitpriv->hwxmit_entry - 1; - - phead = get_list_head(pframequeue); - plist = get_next(phead); - - while (rtw_end_of_queue_search(phead, plist) == _FALSE) { - pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); - plist = get_next(plist); - - pattrib = &pxmitframe->attrib; - pattrib->triggered = 0; - - ret = mgmt_xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe); - - if (ret == RTW_QUEUE_MGMT) { - ptxservq = &(psta->sta_xmitpriv.mgmt_q); - ptxservq->qcnt--; - phwxmits[mgmt_idx].accnt--; - } else { - /* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */ - } - } -} -#endif sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) { - _irqL irqL; sint ret = _FALSE; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; @@ -5754,21 +8359,22 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p /* pattrib->triggered=0; */ if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE) - pattrib->qsel = QSLT_HIGH;/* HIQ */ + pattrib->qsel = rtw_hal_get_qsel(padapter, QSLT_HIGH_ID);/* HIQ */ return ret; } if (bmcst) { - _enter_critical_bh(&psta->sleep_q.lock, &irqL); +#ifndef BMC_ON_HIQ + _rtw_spinlock_bh(&psta->sleep_q.lock); if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */ - /* pattrib->qsel = QSLT_HIGH; */ /* HIQ */ + /* pattrib->qsel = rtw_hal_get_qsel(padapter,QSLT_HIGH_ID);*/ /* HIQ */ rtw_list_delete(&pxmitframe->list); - /*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/ + /*_rtw_spinlock_bh(&psta->sleep_q.lock);*/ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); @@ -5790,29 +8396,29 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p } else chk_bmc_sleepq_cmd(padapter); - /*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/ + /*_rtw_spinunlock_bh(&psta->sleep_q.lock);*/ ret = _TRUE; DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast); } - _exit_critical_bh(&psta->sleep_q.lock, &irqL); - + _rtw_spinunlock_bh(&psta->sleep_q.lock); +#endif return ret; } - _enter_critical_bh(&psta->sleep_q.lock, &irqL); + _rtw_spinlock_bh(&psta->sleep_q.lock); if (psta->state & WIFI_SLEEP_STATE) { u8 wmmps_ac = 0; - if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->phl_sta->aid)) { rtw_list_delete(&pxmitframe->list); - /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + /* _rtw_spinlock_bh(&psta->sleep_q.lock); */ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); @@ -5842,10 +8448,10 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p psta->sleepq_ac_len++; if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) { - if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid))) + if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid))) update_tim = _TRUE; - rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */ /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ @@ -5857,7 +8463,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p } } - /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ + /* _rtw_spinunlock_bh(&psta->sleep_q.lock); */ /* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */ /* { */ @@ -5871,7 +8477,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p } - _exit_critical_bh(&psta->sleep_q.lock, &irqL); + _rtw_spinunlock_bh(&psta->sleep_q.lock); return ret; @@ -5916,7 +8522,6 @@ static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) { - _irqL irqL0; struct sta_info *psta_bmc; struct sta_xmit_priv *pstaxmitpriv; struct sta_priv *pstapriv = &padapter->stapriv; @@ -5929,19 +8534,14 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) if (!psta_bmc) rtw_warn_on(1); - _enter_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinlock_bh(&pxmitpriv->lock); psta->state |= WIFI_SLEEP_STATE; #ifdef CONFIG_TDLS if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) #endif /* CONFIG_TDLS */ - rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); - -#ifdef CONFIG_RTW_MGMT_QUEUE - dequeue_mgmt_xmitframe_to_sleepq(padapter, psta, &pstaxmitpriv->mgmt_q.sta_pending); - rtw_list_delete(&(pstaxmitpriv->mgmt_q.tx_pending)); -#endif + rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->phl_sta->aid); dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); @@ -5956,9 +8556,9 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_TDLS && !(psta->tdls_sta_state & TDLS_LINKED_STATE) #endif - ) - { + ) { /* for BC/MC Frames */ +#ifndef BMC_ON_HIQ pstaxmitpriv = &psta_bmc->sta_xmitpriv; dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); @@ -5968,15 +8568,15 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); +#endif } - _exit_critical_bh(&pxmitpriv->lock, &irqL0); + _rtw_spinunlock_bh(&pxmitpriv->lock); } void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) { - _irqL irqL; u8 update_mask = 0, wmmps_ac = 0; struct sta_info *psta_bmc; _list *xmitframe_plist, *xmitframe_phead; @@ -5987,35 +8587,9 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) psta_bmc = rtw_get_bcmc_stainfo(padapter); - /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ - _enter_critical_bh(&pxmitpriv->lock, &irqL); - -#ifdef CONFIG_RTW_MGMT_QUEUE - /* management queue */ - xmitframe_phead = get_list_head(&psta->mgmt_sleep_q); - xmitframe_plist = get_next(xmitframe_phead); - - while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { - pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); - - xmitframe_plist = get_next(xmitframe_plist); - - rtw_list_delete(&pxmitframe->list); - - #ifdef DBG_MGMT_QUEUE - RTW_INFO("%s seq_num = %u, subtype = 0x%x\n", - __func__, pxmitframe->attrib.seqnum, pxmitframe->attrib.subtype); - #endif - - psta->mgmt_sleepq_len--; - - pxmitframe->attrib.triggered = 1; - - rtw_hal_mgmt_xmitframe_enqueue(padapter, pxmitframe); - } -#endif /* CONFIG_RTW_MGMT_QUEUE */ + /* _rtw_spinlock_bh(&psta->sleep_q.lock); */ + _rtw_spinlock_bh(&pxmitpriv->lock); - /* AC queue */ xmitframe_phead = get_list_head(&psta->sleep_q); xmitframe_plist = get_next(xmitframe_phead); @@ -6066,34 +8640,31 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) pxmitframe->attrib.triggered = 1; /* - _exit_critical_bh(&psta->sleep_q.lock, &irqL); + _rtw_spinunlock_bh(&psta->sleep_q.lock); + //rtw_intf_data_xmit if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) { rtw_os_xmit_complete(padapter, pxmitframe); } - _enter_critical_bh(&psta->sleep_q.lock, &irqL); + _rtw_spinlock_bh(&psta->sleep_q.lock); */ - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); } - if (psta->sleepq_len == 0 -#ifdef CONFIG_RTW_MGMT_QUEUE - && psta->mgmt_sleepq_len == 0 -#endif - ) { + if (psta->sleepq_len == 0) { #ifdef CONFIG_TDLS if (psta->tdls_sta_state & TDLS_LINKED_STATE) { if (psta->state & WIFI_SLEEP_STATE) psta->state ^= WIFI_SLEEP_STATE; - _exit_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinunlock_bh(&pxmitpriv->lock); return; } #endif /* CONFIG_TDLS */ - if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid)) { /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ @@ -6101,7 +8672,7 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) update_mask = BIT(0); } - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); if (psta->state & WIFI_SLEEP_STATE) psta->state ^= WIFI_SLEEP_STATE; @@ -6112,7 +8683,7 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->phl_sta->aid); } /* for BC/MC Frames */ @@ -6139,15 +8710,16 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) pxmitframe->attrib.triggered = 1; /* - _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + _rtw_spinunlock_bh(&psta_bmc->sleep_q.lock); + //rtw_intf_data_xmit if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) { rtw_os_xmit_complete(padapter, pxmitframe); } - _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + _rtw_spinlock_bh(&psta_bmc->sleep_q.lock); */ - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); } @@ -6167,8 +8739,8 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) _exit: - /* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ - _exit_critical_bh(&pxmitpriv->lock, &irqL); + /* _rtw_spinunlock_bh(&psta_bmc->sleep_q.lock); */ + _rtw_spinunlock_bh(&pxmitpriv->lock); if (update_mask) { /* update_BCNTIM(padapter); */ @@ -6179,11 +8751,11 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) else _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear UC"); } + } void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) { - _irqL irqL; u8 wmmps_ac = 0; _list *xmitframe_plist, *xmitframe_phead; struct xmit_frame *pxmitframe = NULL; @@ -6191,8 +8763,8 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ - _enter_critical_bh(&pxmitpriv->lock, &irqL); + /* _rtw_spinlock_bh(&psta->sleep_q.lock); */ + _rtw_spinlock_bh(&pxmitpriv->lock); xmitframe_phead = get_list_head(&psta->sleep_q); xmitframe_plist = get_next(xmitframe_phead); @@ -6239,22 +8811,22 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) } pxmitframe->attrib.triggered = 1; - rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + rtw_intf_xmitframe_enqueue(padapter, pxmitframe); if ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) { #ifdef CONFIG_TDLS if (psta->tdls_sta_state & TDLS_LINKED_STATE) { - /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ + /* _rtw_spinunlock_bh(&psta->sleep_q.lock); */ goto exit; } #endif /* CONFIG_TDLS */ - rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->phl_sta->aid); /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ - update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); + rtw_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0); /* update_mask = BIT(0); */ } @@ -6263,29 +8835,28 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_TDLS exit: #endif - /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ - _exit_critical_bh(&pxmitpriv->lock, &irqL); + /* _rtw_spinunlock_bh(&psta->sleep_q.lock); */ + _rtw_spinunlock_bh(&pxmitpriv->lock); return; } #endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */ -#ifdef CONFIG_XMIT_THREAD_MODE +#if 0 /*#ifdef CONFIG_XMIT_THREAD_MODE*/ void enqueue_pending_xmitbuf( struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) { - _irqL irql; _queue *pqueue; _adapter *pri_adapter = pxmitpriv->adapter; pqueue = &pxmitpriv->pending_xmitbuf_queue; - _enter_critical_bh(&pqueue->lock, &irql); + _rtw_spinlock_bh(&pqueue->lock); rtw_list_delete(&pxmitbuf->list); rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue)); - _exit_critical_bh(&pqueue->lock, &irql); + _rtw_spinunlock_bh(&pqueue->lock); #if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) pri_adapter = GET_PRIMARY_ADAPTER(pri_adapter); @@ -6297,19 +8868,17 @@ void enqueue_pending_xmitbuf_to_head( struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) { - _irqL irql; _queue *pqueue = &pxmitpriv->pending_xmitbuf_queue; - _enter_critical_bh(&pqueue->lock, &irql); + _rtw_spinlock_bh(&pqueue->lock); rtw_list_delete(&pxmitbuf->list); rtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue)); - _exit_critical_bh(&pqueue->lock, &irql); + _rtw_spinunlock_bh(&pqueue->lock); } struct xmit_buf *dequeue_pending_xmitbuf( struct xmit_priv *pxmitpriv) { - _irqL irql; struct xmit_buf *pxmitbuf; _queue *pqueue; @@ -6317,7 +8886,7 @@ struct xmit_buf *dequeue_pending_xmitbuf( pxmitbuf = NULL; pqueue = &pxmitpriv->pending_xmitbuf_queue; - _enter_critical_bh(&pqueue->lock, &irql); + _rtw_spinlock_bh(&pqueue->lock); if (_rtw_queue_empty(pqueue) == _FALSE) { _list *plist, *phead; @@ -6328,7 +8897,7 @@ struct xmit_buf *dequeue_pending_xmitbuf( rtw_list_delete(&pxmitbuf->list); } - _exit_critical_bh(&pqueue->lock, &irql); + _rtw_spinunlock_bh(&pqueue->lock); return pxmitbuf; } @@ -6336,14 +8905,13 @@ struct xmit_buf *dequeue_pending_xmitbuf( static struct xmit_buf *dequeue_pending_xmitbuf_ext( struct xmit_priv *pxmitpriv) { - _irqL irql; struct xmit_buf *pxmitbuf; _queue *pqueue; pxmitbuf = NULL; pqueue = &pxmitpriv->pending_xmitbuf_queue; - _enter_critical_bh(&pqueue->lock, &irql); + _rtw_spinlock_bh(&pqueue->lock); if (_rtw_queue_empty(pqueue) == _FALSE) { _list *plist, *phead; @@ -6365,7 +8933,7 @@ static struct xmit_buf *dequeue_pending_xmitbuf_ext( } while (1); } - _exit_critical_bh(&pqueue->lock, &irql); + _rtw_spinunlock_bh(&pqueue->lock); return pxmitbuf; } @@ -6388,18 +8956,17 @@ struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter) sint check_pending_xmitbuf( struct xmit_priv *pxmitpriv) { - _irqL irql; _queue *pqueue; sint ret = _FALSE; pqueue = &pxmitpriv->pending_xmitbuf_queue; - _enter_critical_bh(&pqueue->lock, &irql); + _rtw_spinlock_bh(&pqueue->lock); if (_rtw_queue_empty(pqueue) == _FALSE) ret = _TRUE; - _exit_critical_bh(&pqueue->lock, &irql); + _rtw_spinunlock_bh(&pqueue->lock); return ret; } @@ -6407,7 +8974,7 @@ sint check_pending_xmitbuf( thread_return rtw_xmit_thread(thread_context context) { s32 err; - PADAPTER padapter; + _adapter *adapter; #ifdef RTW_XMIT_THREAD_HIGH_PRIORITY #ifdef PLATFORM_LINUX struct sched_param param = { .sched_priority = 1 }; @@ -6417,16 +8984,16 @@ thread_return rtw_xmit_thread(thread_context context) #endif /* RTW_XMIT_THREAD_HIGH_PRIORITY */ err = _SUCCESS; - padapter = (PADAPTER)context; + adapter = (_adapter *)context; - thread_enter("RTW_XMIT_THREAD"); + rtw_thread_enter("RTW_XMIT_THREAD"); do { - err = rtw_hal_xmit_thread_handler(padapter); + err = rtw_intf_xmit_buf_handler(adapter); flush_signals_thread(); } while (_SUCCESS == err); - RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); rtw_thread_wait_stop(); @@ -6459,12 +9026,11 @@ void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter) void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason) { - _irqL irqL; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _enter_critical_bh(&dvobj->xmit_block_lock, &irqL); + _rtw_spinlock_bh(&dvobj->xmit_block_lock); dvobj->xmit_block |= reason; - _exit_critical_bh(&dvobj->xmit_block_lock, &irqL); + _rtw_spinunlock_bh(&dvobj->xmit_block_lock); #ifdef DBG_XMIT_BLOCK DBG_XMIT_BLOCK_DUMP(padapter); @@ -6473,12 +9039,11 @@ void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason) void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason) { - _irqL irqL; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _enter_critical_bh(&dvobj->xmit_block_lock, &irqL); + _rtw_spinlock_bh(&dvobj->xmit_block_lock); dvobj->xmit_block &= ~reason; - _exit_critical_bh(&dvobj->xmit_block_lock, &irqL); + _rtw_spinunlock_bh(&dvobj->xmit_block_lock); #ifdef DBG_XMIT_BLOCK DBG_XMIT_BLOCK_DUMP(padapter); @@ -6515,7 +9080,7 @@ bool rtw_xmit_ac_blocked(_adapter *adapter) if (rfctl->offch_state != OFFCHS_NONE #if CONFIG_DFS - || IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch + || IS_RADAR_DETECTED(rfctl) || rfctl->csa_chandef.chan #endif ) { blocked = _TRUE; @@ -6542,21 +9107,34 @@ bool rtw_xmit_ac_blocked(_adapter *adapter) } } -#ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter)) { - if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) { - if (MCC_STOP(adapter)) { - blocked = _TRUE; - goto exit; - } - } - } -#endif /* CONFIG_MCC_MODE */ - exit: return blocked; } +#ifdef CONFIG_LAYER2_ROAMING +/* dequeuq + xmit the cache skb during the roam procedure */ +void dequeuq_roam_pkt(_adapter *padapter) +{ + struct xmit_frame *rframe; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _list *plist = NULL, *phead = NULL; + + if (padapter->mlmepriv.roam_network) { + padapter->mlmepriv.roam_network = NULL; + _rtw_spinlock_bh(&pxmitpriv->rpkt_queue.lock); + phead = get_list_head(&pxmitpriv->rpkt_queue); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + rframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + plist = get_next(plist); + rtw_list_delete(&rframe->list); + core_tx_per_packet(padapter, rframe, &rframe->pkt, NULL); + } + _rtw_spinunlock_bh(&pxmitpriv->rpkt_queue.lock); + } +} +#endif + #ifdef CONFIG_TX_AMSDU void rtw_amsdu_vo_timeout_handler(void *FunctionContext) { @@ -6564,7 +9142,7 @@ void rtw_amsdu_vo_timeout_handler(void *FunctionContext) adapter->xmitpriv.amsdu_vo_timeout = RTW_AMSDU_TIMER_TIMEOUT; - tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); + rtw_tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } void rtw_amsdu_vi_timeout_handler(void *FunctionContext) @@ -6573,7 +9151,7 @@ void rtw_amsdu_vi_timeout_handler(void *FunctionContext) adapter->xmitpriv.amsdu_vi_timeout = RTW_AMSDU_TIMER_TIMEOUT; - tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); + rtw_tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } void rtw_amsdu_be_timeout_handler(void *FunctionContext) @@ -6582,10 +9160,7 @@ void rtw_amsdu_be_timeout_handler(void *FunctionContext) adapter->xmitpriv.amsdu_be_timeout = RTW_AMSDU_TIMER_TIMEOUT; - if (printk_ratelimit()) - RTW_INFO("%s Timeout!\n",__FUNCTION__); - - tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); + rtw_tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } void rtw_amsdu_bk_timeout_handler(void *FunctionContext) @@ -6594,123 +9169,117 @@ void rtw_amsdu_bk_timeout_handler(void *FunctionContext) adapter->xmitpriv.amsdu_bk_timeout = RTW_AMSDU_TIMER_TIMEOUT; - tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); + rtw_tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority) { - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; u8 status = RTW_AMSDU_TIMER_UNSET; - switch(priority) - { - case 1: - case 2: - status = pxmitpriv->amsdu_bk_timeout; - break; - case 4: - case 5: - status = pxmitpriv->amsdu_vi_timeout; - break; - case 6: - case 7: - status = pxmitpriv->amsdu_vo_timeout; - break; - case 0: - case 3: - default: - status = pxmitpriv->amsdu_be_timeout; - break; + switch (priority) { + case 1: + case 2: + status = pxmitpriv->amsdu_bk_timeout; + break; + case 4: + case 5: + status = pxmitpriv->amsdu_vi_timeout; + break; + case 6: + case 7: + status = pxmitpriv->amsdu_vo_timeout; + break; + case 0: + case 3: + default: + status = pxmitpriv->amsdu_be_timeout; + break; } return status; } void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status) { - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - switch(priority) - { - case 1: - case 2: - pxmitpriv->amsdu_bk_timeout = status; - break; - case 4: - case 5: - pxmitpriv->amsdu_vi_timeout = status; - break; - case 6: - case 7: - pxmitpriv->amsdu_vo_timeout = status; - break; - case 0: - case 3: - default: - pxmitpriv->amsdu_be_timeout = status; - break; + switch (priority) { + case 1: + case 2: + pxmitpriv->amsdu_bk_timeout = status; + break; + case 4: + case 5: + pxmitpriv->amsdu_vi_timeout = status; + break; + case 6: + case 7: + pxmitpriv->amsdu_vo_timeout = status; + break; + case 0: + case 3: + default: + pxmitpriv->amsdu_be_timeout = status; + break; } } void rtw_amsdu_set_timer(_adapter *padapter, u8 priority) { - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - - _timer* amsdu_timer = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _timer *amsdu_timer = NULL; - switch(priority) - { - case 1: - case 2: - amsdu_timer = &pxmitpriv->amsdu_bk_timer; - break; - case 4: - case 5: - amsdu_timer = &pxmitpriv->amsdu_vi_timer; - break; - case 6: - case 7: - amsdu_timer = &pxmitpriv->amsdu_vo_timer; - break; - case 0: - case 3: - default: - amsdu_timer = &pxmitpriv->amsdu_be_timer; - break; + switch (priority) { + case 1: + case 2: + amsdu_timer = &pxmitpriv->amsdu_bk_timer; + break; + case 4: + case 5: + amsdu_timer = &pxmitpriv->amsdu_vi_timer; + break; + case 6: + case 7: + amsdu_timer = &pxmitpriv->amsdu_vo_timer; + break; + case 0: + case 3: + default: + amsdu_timer = &pxmitpriv->amsdu_be_timer; + break; } _set_timer(amsdu_timer, 1); } void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority) { - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _timer* amsdu_timer = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _timer *amsdu_timer = NULL; - switch(priority) - { - case 1: - case 2: - amsdu_timer = &pxmitpriv->amsdu_bk_timer; - break; - case 4: - case 5: - amsdu_timer = &pxmitpriv->amsdu_vi_timer; - break; - case 6: - case 7: - amsdu_timer = &pxmitpriv->amsdu_vo_timer; - break; - case 0: - case 3: - default: - amsdu_timer = &pxmitpriv->amsdu_be_timer; - break; + switch (priority) { + case 1: + case 2: + amsdu_timer = &pxmitpriv->amsdu_bk_timer; + break; + case 4: + case 5: + amsdu_timer = &pxmitpriv->amsdu_vi_timer; + break; + case 6: + case 7: + amsdu_timer = &pxmitpriv->amsdu_vo_timer; + break; + case 0: + case 3: + default: + amsdu_timer = &pxmitpriv->amsdu_be_timer; + break; } _cancel_timer_ex(amsdu_timer); } #endif /* CONFIG_TX_AMSDU */ -#ifdef DBG_TXBD_DESC_DUMP +#if 0 /*def DBG_TXBD_DESC_DUMP*/ static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT]; static u8 backup_idx[HW_QUEUE_ENTRY]; @@ -6719,7 +9288,7 @@ void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 de u32 tmp32; u8 *pxmit_buf; - if (rtw_get_hw_init_completed(padapter) == _FALSE) + if (rtw_hw_get_init_completed(adapter_to_dvobj(padapter)) == _FALSE) return; pxmit_buf = pxmitframe->pxmitbuf->pbuf; @@ -6727,7 +9296,11 @@ void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 de _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size); _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN); + #if 0 /*GEORGIA_TODO_REDEFINE_IO*/ tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq)); + #else + tmp32 = rtw_hal_get_txbd_rwreg(padapter); + #endif tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff; tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff; @@ -6761,7 +9334,7 @@ u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup void rtw_tx_poll_init(_adapter *padapter) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _timer* timer = &pxmitpriv->tx_poll_timer; + _timer *timer = &pxmitpriv->tx_poll_timer; if (!is_primary_adapter(padapter)) return; @@ -6771,7 +9344,7 @@ void rtw_tx_poll_init(_adapter *padapter) return; } - rtw_init_timer(timer, padapter, rtw_tx_poll_timeout_handler, padapter); + rtw_init_timer(timer, rtw_tx_poll_timeout_handler, padapter); rtw_tx_poll_timer_set(padapter, 1); RTW_INFO("Tx poll timer init!\n"); } @@ -6782,8 +9355,8 @@ void rtw_tx_poll_timeout_handler(void *FunctionContext) rtw_tx_poll_timer_set(adapter, 1); - if (adapter->hal_func.tx_poll_handler) - adapter->hal_func.tx_poll_handler(adapter); + if (adapter->dvobj->hal_func.tx_poll_handler) + adapter->dvobj->hal_func.tx_poll_handler(adapter); else RTW_WARN("hal ops: tx_poll_handler is NULL\n"); } @@ -6791,7 +9364,7 @@ void rtw_tx_poll_timeout_handler(void *FunctionContext) void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _timer* timer = NULL; + _timer *timer = NULL; timer = &pxmitpriv->tx_poll_timer; _set_timer(timer, delay); @@ -6800,7 +9373,7 @@ void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay) void rtw_tx_poll_timer_cancel(_adapter *padapter) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _timer* timer = NULL; + _timer *timer = NULL; if (!is_primary_adapter(padapter)) return; @@ -6816,9 +9389,7 @@ void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) { sctx->timeout_ms = timeout_ms; sctx->submit_time = rtw_get_current_time(); -#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */ - init_completion(&sctx->done); -#endif + _rtw_init_completion(&sctx->done); sctx->status = RTW_SCTX_SUBMITTED; } @@ -6830,7 +9401,7 @@ int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg) #ifdef PLATFORM_LINUX expire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT; - if (!wait_for_completion_timeout(&sctx->done, expire)) { + if (!_rtw_wait_for_comp_timeout(&sctx->done, expire)) { /* timeout, do something?? */ status = RTW_SCTX_DONE_TIMEOUT; RTW_INFO("%s timeout: %s\n", __func__, msg); diff --git a/core/rtw_xmit_shortcut.c b/core/rtw_xmit_shortcut.c new file mode 100644 index 0000000..ccf795a --- /dev/null +++ b/core/rtw_xmit_shortcut.c @@ -0,0 +1,917 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_CORE_TXSC +u8 DBG_PRINT_MDATA_ONCE; +void _print_txreq_mdata(struct rtw_t_meta_data *mdata, const char *func) +{ + if (DBG_PRINT_MDATA_ONCE == 1) { + RTW_PRINT("[%s]\n", func); + + RTW_PRINT("da: %02x%02x%02x%02x%02x%02x\n", + mdata->da[0], mdata->da[1], mdata->da[2], mdata->da[3], mdata->da[4], mdata->da[5]); + RTW_PRINT("sa: %02x%02x%02x%02x%02x%02x\n", + mdata->sa[0], mdata->sa[1], mdata->sa[2], mdata->sa[3], mdata->sa[4], mdata->sa[5]); + RTW_PRINT("to_ds: %d\n", mdata->to_ds); + RTW_PRINT("from_ds: %d\n", mdata->from_ds); + RTW_PRINT("band: %d\n", mdata->band); + RTW_PRINT("type: %d\n", mdata->type); + + RTW_PRINT("hw_seq_mode: %d\n", mdata->hw_seq_mode); + RTW_PRINT("hw_ssn_sel: %d\n", mdata->hw_ssn_sel); + RTW_PRINT("smh_en: %d\n", mdata->smh_en); + RTW_PRINT("hw_amsdu: %d\n", mdata->hw_amsdu); + RTW_PRINT("hw_sec_iv: %d\n", mdata->hw_sec_iv); + RTW_PRINT("wd_page_size: %d\n", mdata->wd_page_size); + RTW_PRINT("hdr_len: %d\n", mdata->hdr_len); + RTW_PRINT("dma_ch: %d\n", mdata->dma_ch); + RTW_PRINT("usb_pkt_ofst: %d\n", mdata->usb_pkt_ofst); + RTW_PRINT("wdinfo_en: %d\n", mdata->wdinfo_en); + RTW_PRINT("wp_offset: %d\n", mdata->wp_offset); + RTW_PRINT("shcut_camid: %d\n", mdata->shcut_camid); + RTW_PRINT("usb_txagg_num: %d\n", mdata->usb_txagg_num); + RTW_PRINT("pktlen: %d\n", mdata->pktlen); + RTW_PRINT("tid: %d\n", mdata->tid); + RTW_PRINT("macid: %d\n", mdata->macid); + RTW_PRINT("sw_seq: %d\n", mdata->sw_seq); + RTW_PRINT("ampdu_en: %d\n", mdata->ampdu_en); + RTW_PRINT("bk: %d\n", mdata->bk); + RTW_PRINT("mbssid: %d\n", mdata->mbssid); + RTW_PRINT("hal_port: %d\n", mdata->hal_port); + RTW_PRINT("data_bw_er: %d\n", mdata->data_bw_er); + RTW_PRINT("dis_rts_rate_fb: %d\n", mdata->dis_rts_rate_fb); + RTW_PRINT("dis_data_rate_fb: %d\n", mdata->dis_data_rate_fb); + RTW_PRINT("f_ldpc: %d\n", mdata->f_ldpc); + RTW_PRINT("f_stbc: %d\n", mdata->f_stbc); + RTW_PRINT("f_dcm: %d\n", mdata->f_dcm); + RTW_PRINT("f_er: %d\n", mdata->f_er); + RTW_PRINT("f_rate: %d\n", mdata->f_rate); + RTW_PRINT("f_gi_ltf: %d\n", mdata->f_gi_ltf); + RTW_PRINT("f_bw: %d\n", mdata->f_bw); + RTW_PRINT("userate_sel: %d\n", mdata->userate_sel); + RTW_PRINT("ack_ch_info: %d\n", mdata->ack_ch_info); + RTW_PRINT("max_agg_num: %d\n", mdata->max_agg_num); + RTW_PRINT("nav_use_hdr: %d\n", mdata->nav_use_hdr); + RTW_PRINT("bc: %d\n", mdata->bc); + RTW_PRINT("mc: %d\n", mdata->mc); + RTW_PRINT("a_ctrl_bqr: %d\n", mdata->a_ctrl_bqr); + RTW_PRINT("a_ctrl_uph: %d\n", mdata->a_ctrl_uph); + RTW_PRINT("a_ctrl_bsr: %d\n", mdata->a_ctrl_bsr); + RTW_PRINT("a_ctrl_cas: %d\n", mdata->a_ctrl_cas); + RTW_PRINT("data_rty_lowest_rate: %d\n", mdata->data_rty_lowest_rate); + RTW_PRINT("data_tx_cnt_lmt: %d\n", mdata->data_tx_cnt_lmt); + RTW_PRINT("data_tx_cnt_lmt_en: %d\n", mdata->data_tx_cnt_lmt_en); + RTW_PRINT("sec_cam_idx: %d\n", mdata->sec_cam_idx); + RTW_PRINT("sec_hw_enc: %d\n", mdata->sec_hw_enc); + RTW_PRINT("sec_type: %d\n", mdata->sec_type); + RTW_PRINT("life_time_sel: %d\n", mdata->life_time_sel); + RTW_PRINT("ampdu_density: %d\n", mdata->ampdu_density); + RTW_PRINT("no_ack: %d\n", mdata->no_ack); + RTW_PRINT("ndpa: %d\n", mdata->ndpa); + RTW_PRINT("snd_pkt_sel: %d\n", mdata->snd_pkt_sel); + RTW_PRINT("sifs_tx: %d\n", mdata->sifs_tx); + RTW_PRINT("rtt_en: %d\n", mdata->rtt_en); + RTW_PRINT("spe_rpt: %d\n", mdata->spe_rpt); + RTW_PRINT("raw: %d\n", mdata->raw); + RTW_PRINT("sw_define: %d\n", mdata->sw_define); + RTW_PRINT("rts_en: %d\n", mdata->rts_en); + RTW_PRINT("cts2self: %d\n", mdata->cts2self); + RTW_PRINT("rts_cca_mode: %d\n", mdata->rts_cca_mode); + RTW_PRINT("hw_rts_en: %d\n", mdata->hw_rts_en); + + DBG_PRINT_MDATA_ONCE = 0; + } +} + +u8 DBG_PRINT_TXREQ_ONCE; +void _print_txreq_pklist(struct xmit_frame *pxframe, struct rtw_xmit_req *ptxreq, struct sk_buff *pskb, const char *func) +{ + struct rtw_pkt_buf_list *pkt_list = NULL; + struct rtw_xmit_req *txreq = NULL; + u8 pkt_cnt = 0, i; + + if (DBG_PRINT_TXREQ_ONCE == 1) { + RTW_PRINT("%s\n", func); + RTW_PRINT("[%s] pxframe=%p txreq=%p\n", func, pxframe, ptxreq); + + if (pskb) + txsc_dump_data(pskb->data, ETH_HLEN, "ETHHDR"); + + if (ptxreq != NULL) + txreq = ptxreq; + else + txreq = pxframe->phl_txreq; + + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + pkt_cnt = txreq->pkt_cnt; + + RTW_PRINT("os_priv:%p, treq_type:%d, pkt_cnt:%d, total_len:%d, shortcut_id:%d\n\n", + txreq->os_priv, txreq->treq_type, txreq->pkt_cnt, txreq->total_len, txreq->shortcut_id); + + for (i = 0; i < pkt_cnt; i++) { + RTW_PRINT("pkt_list[%d]\n", i); + txsc_dump_data(pkt_list->vir_addr, pkt_list->length, "pkt_list"); + pkt_list++; + } + DBG_PRINT_TXREQ_ONCE = 0; + } +} + +void txsc_init(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pxmitpriv->txsc_enable = 1; /* default TXSC on */ + pxmitpriv->txsc_debug_mode = 0; + pxmitpriv->txsc_debug_mask = 0x3; +} + +void txsc_clear(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + int i; + u8 tmp = 0; + + RTW_PRINT("[TXSC] clear txsc entry\n"); + + _rtw_spinlock_bh(&pxmitpriv->txsc_lock); + + if (pxmitpriv->txsc_enable) { + tmp = pxmitpriv->txsc_enable; + pxmitpriv->txsc_enable = 0; + } + + pxmitpriv->ptxsc_sta_cached = NULL; + + for (i = 0; i < pstapriv->max_num_sta; i++) { + psta = pstapriv->sta_aid[i]; + + if (!psta) + continue; + + psta->txsc_cache_num = 0; + psta->txsc_cur_idx = 0; + psta->txsc_cache_idx = 0; + psta->txsc_cache_hit = 0; + psta->txsc_cache_miss = 0; + psta->txsc_path_slow = 0; + _rtw_memset(psta->txsc_entry_cache, 0x0, sizeof(struct txsc_entry) * CORE_TXSC_ENTRY_NUM); + + } + + pxmitpriv->txsc_enable = tmp; + + _rtw_spinunlock_bh(&pxmitpriv->txsc_lock); +} + +void txsc_dump(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + int i, j; + + RTW_PRINT("[txsc][core] (txsc,enable) txsc_enable:%x\n", pxmitpriv->txsc_enable); + RTW_PRINT("[txsc][core] (txsc,debug) txsc_debug_mode:%x\n", pxmitpriv->txsc_debug_mode); + + RTW_PRINT("[txsc][core] txsc_phl_err_cnt1:%d\n", pxmitpriv->txsc_phl_err_cnt1); + RTW_PRINT("[txsc][core] txsc_phl_err_cnt2:%d\n", pxmitpriv->txsc_phl_err_cnt2); + RTW_PRINT("\n"); + for (i = 0; i < pstapriv->max_num_sta; i++) { + psta = pstapriv->sta_aid[i]; + if (!psta) + continue; + + RTW_PRINT("[%d] STA[%02x:%02x:%02x:%02x:%02x:%02x]\n", i, + psta->phl_sta->mac_addr[0], psta->phl_sta->mac_addr[1], psta->phl_sta->mac_addr[2], + psta->phl_sta->mac_addr[3], psta->phl_sta->mac_addr[4], psta->phl_sta->mac_addr[5]); + RTW_PRINT("[txsc] cur_idx:%d\n", psta->txsc_cur_idx); + RTW_PRINT("[txsc][core] txsc_path_slow:%d\n", psta->txsc_path_slow); + RTW_PRINT("[txsc][core] txsc_path_ps:%d\n", psta->txsc_path_ps); + RTW_PRINT("[txsc][core] txsc_cache_hit:%d\n", psta->txsc_cache_hit); + RTW_PRINT("[txsc][core] txsc_cache_miss:%d\n", psta->txsc_cache_miss); + RTW_PRINT("\n"); + for (j = 0 ; j < CORE_TXSC_ENTRY_NUM; j++) { + if (!psta->txsc_entry_cache[j].txsc_is_used) + continue; + + RTW_PRINT(" [%d][txsc][core] txsc_core_hit:%d\n", j, psta->txsc_entry_cache[j].txsc_cache_hit); + #ifdef CONFIG_PHL_TXSC + RTW_PRINT(" [%d][txsc][phl] txsc_phl_hit:%d\n", j, psta->phl_sta->phl_txsc[j].txsc_cache_hit); + #endif + RTW_PRINT("\n"); + } + } +} + +void txsc_dump_data(u8 *buf, u16 buf_len, const char *prefix) +{ + int i = 0, j; + + RTW_PRINT("[txsc_dump] [%s (%uB)]@%p:\n", prefix, buf_len, buf); + + if (buf == NULL) { + RTW_PRINT("[txsc_dump] NULL!\n"); + return; + } + + while (i < buf_len) { + RTW_PRINT("[txsc_dump] %04X -", i); + for (j = 0; (j < 4) && (i < buf_len); j++, i += 4) + RTW_PRINT(" %02X %02X %02X %02X", buf[i], buf[i+1], buf[i+2], buf[i+3]); + RTW_PRINT("\n"); + } +} + +#ifdef CONFIG_PCI_HCI +void txsc_recycle_txreq_phyaddr(_adapter *padapter, struct rtw_xmit_req *txreq) +{ + PPCI_DATA pci_data = dvobj_to_pci(padapter->dvobj); + struct pci_dev *pdev = pci_data->ppcidev; + struct rtw_pkt_buf_list *pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + dma_addr_t phy_addr = 0; + + /* only recycle pkt_list[1] = skb->data for SW TXSC */ + pkt_list++; + + phy_addr = (pkt_list->phy_addr_l); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + phy_addr |= ((u64)pkt_list->phy_addr_h << 32); +#endif + pci_unmap_bus_addr(pdev, &phy_addr, pkt_list->length, PCI_DMA_TODEVICE); +} + +void txsc_fill_txreq_phyaddr(_adapter *padapter, struct rtw_pkt_buf_list *pkt_list) +{ + PPCI_DATA pci_data = dvobj_to_pci(padapter->dvobj); + struct pci_dev *pdev = pci_data->ppcidev; + dma_addr_t phy_addr = 0; + + pci_get_bus_addr(pdev, pkt_list->vir_addr, &phy_addr, pkt_list->length, PCI_DMA_TODEVICE); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pkt_list->phy_addr_h = phy_addr >> 32; +#else + pkt_list->phy_addr_h = 0x0; +#endif + pkt_list->phy_addr_l = phy_addr & 0xFFFFFFFF; +} +#endif + +static void txsc_init_pkt_entry(_adapter *padapter, struct sk_buff *pskb, struct txsc_pkt_entry *txsc_pkt) +{ + u8 priority = 0, i; + + txsc_pkt->step = TXSC_NONE; + txsc_pkt->txsc_id = 0xff; + txsc_pkt->ptxreq = NULL; + + for (i = 0; i < MAX_TXSC_SKB_NUM; i++) + txsc_pkt->xmit_skb[i] = NULL; + + txsc_pkt->psta = NULL; + txsc_pkt->xmit_skb[0] = pskb; + txsc_pkt->skb_cnt = 1; + + priority = *(pskb->data + ETH_HLEN + 1); + txsc_pkt->priority = tos_to_up(priority); +} + +static void txsc_add_sc_check(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxframe->attrib; + struct sta_info *psta = pxframe->attrib.psta; + + if (!pxmitpriv->txsc_enable) { + if (psta->txsc_cache_num > 0) + txsc_pkt->step = TXSC_SKIP; + else + txsc_pkt->step = TXSC_NONE; + goto exit; + } + + if (pxframe->attrib.nr_frags > 1 || pxframe->attrib.bswenc == 1) + goto exit; + + if (txsc_pkt->step != TXSC_NONE) + goto exit; + + if (pattrib->qos_en && + pattrib->ampdu_en == 1 && + pattrib->ether_type == ETH_P_IP && + !IS_MCAST(pattrib->ra) && + !pattrib->icmp_pkt && + !pattrib->dhcp_pkt) { + + RTW_PRINT("[%s] sta[%02x] add eth_type=0x%x pkt to txsc\n", + __func__, pattrib->psta->phl_sta->mac_addr[5], pattrib->ether_type); + + txsc_pkt->step = TXSC_ADD; + } + +exit: + return; +} + +static u8 txsc_get_sc_entry(_adapter *padapter, struct sk_buff *pskb, struct txsc_pkt_entry *txsc_pkt) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + u8 *ptxsc_ethdr = NULL; + u8 i, res, da[6], offset, res2 = 0, sta_hit = 0; + + res = _FAIL; + offset = 6; + + if (!pxmitpriv->txsc_enable) + return res; + + if (pxmitpriv->ptxsc_sta_cached) { + if (pxmitpriv->ptxsc_sta_cached->phl_sta) + sta_hit = _rtw_memcmp(pxmitpriv->ptxsc_sta_cached->phl_sta->mac_addr, pskb->data, 6); + + if (sta_hit) + psta = pxmitpriv->ptxsc_sta_cached; + } + + if (!sta_hit) { + _rtw_memcpy(da, pskb->data, 6); + if (IS_MCAST(da)) { + res = _FAIL; + } else { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + psta = rtw_get_stainfo(pstapriv, da); + else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + + if (!psta) + res = _FAIL; + } + } + + if (!psta) { + res = _FAIL; + goto exit; + } + + /* skip power saving mode */ + if (psta->state & WIFI_SLEEP_STATE) { + res = _FAIL; + txsc_pkt->step = TXSC_SKIP; + psta->txsc_path_ps++; + goto exit; + } + + + if (psta->txsc_cache_num == 0) { + res = _FAIL; + goto exit; + } + + pxmitpriv->ptxsc_sta_cached = psta; + txsc_pkt->step = TXSC_NONE; + ptxsc_ethdr = (u8 *)&psta->txsc_entry_cache[psta->txsc_cache_idx].txsc_ethdr; + res2 = _rtw_memcmp((pskb->data + offset), (ptxsc_ethdr + offset), (ETH_HLEN - offset)); + + if (res2 && + (pskb->len <= psta->txsc_entry_cache[psta->txsc_cache_idx].txsc_frag_len)) { + + txsc_pkt->step = TXSC_APPLY; + txsc_pkt->psta = psta; + txsc_pkt->txsc_id = psta->txsc_cache_idx; + + res = _SUCCESS; + } else { + + for (i = 0; i < CORE_TXSC_ENTRY_NUM; i++) { + if (i != psta->txsc_cache_idx && psta->txsc_entry_cache[i].txsc_is_used) { + + ptxsc_ethdr = (u8 *)&(psta->txsc_entry_cache[i].txsc_ethdr); + if (_rtw_memcmp((pskb->data + offset), (ptxsc_ethdr + offset), (ETH_HLEN - offset)) && + (pskb->len <= psta->txsc_entry_cache[i].txsc_frag_len)) { + + txsc_pkt->step = TXSC_APPLY; + txsc_pkt->txsc_id = i; + txsc_pkt->psta = psta; + psta->txsc_cache_idx = i; + res = _SUCCESS; + + break; + } + } + } + } + + if ((res == _SUCCESS) && (pxmitpriv->txsc_debug_mode == 1)) { + txsc_pkt->step = TXSC_DEBUG; + res = _FAIL; + } + +exit: + return res; +} + +static void txsc_prepare_sc_entry(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = pxframe->attrib.psta; + struct pkt_attrib *pattrib = &pxframe->attrib; + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + struct rtw_pkt_buf_list *pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + struct rtw_pkt_buf_list *ptxsc_pkt_list0 = NULL; + struct rtw_t_meta_data *ptxsc_mdata = NULL; + struct sk_buff *pskb = txsc_pkt->xmit_skb[0]; + u8 i, idx; + u8 *ptxsc_ethdr = NULL; + u8 *ptxsc_wlhdr = NULL; + u8 *ptxsc_wlhdr_len = NULL; + + if (!psta) { + RTW_ERR("%s: fetal err, XF_STA = NULL, please check.\n", __func__); + return; + } + + if (txsc_pkt->step == TXSC_SKIP) { + if (pxmitpriv->txsc_enable && psta->txsc_cache_num > 0) + psta->txsc_cache_miss++; + else + psta->txsc_path_slow++; + } else if (txsc_pkt->step == TXSC_NONE) { + psta->txsc_path_slow++; + } + + if (txsc_pkt->step != TXSC_ADD) + return; + + idx = psta->txsc_cur_idx; + + ptxsc_ethdr = (u8 *)&psta->txsc_entry_cache[idx].txsc_ethdr; + #ifdef USE_ONE_WLHDR + ptxsc_wlhdr = psta->txsc_entry_cache[idx].txsc_wlhdr; + #else + ptxsc_wlhdr = (u8 *)&psta->txsc_entry_cache[idx].txsc_wlhdr; + #endif + ptxsc_pkt_list0 = &psta->txsc_entry_cache[idx].txsc_pkt_list0; + ptxsc_mdata = &psta->txsc_entry_cache[idx].txsc_mdata; + ptxsc_wlhdr_len = &psta->txsc_entry_cache[idx].txsc_wlhdr_len; + + _rtw_spinlock_bh(&pxmitpriv->txsc_lock); + + if (psta->txsc_entry_cache[idx].txsc_is_used == 1) + RTW_PRINT("[CORE_TXSC] txsc entry is full, replace rentry[%d]\n", idx); + + /* ALLOC WLHDR in DMA addr */ + #ifdef USE_ONE_WLHDR + if (!ptxsc_wlhdr) { + ptxsc_wlhdr = rtw_zmalloc(CORE_TXSC_WLHDR_SIZE); + psta->txsc_entry_cache[idx].txsc_wlhdr = ptxsc_wlhdr; + } + #endif + + /* ETH HDR */ + _rtw_memcpy(ptxsc_ethdr, pskb->data, ETH_HLEN); + + /* WLAN HDR + LLC */ + _rtw_memcpy(ptxsc_wlhdr, pkt_list->vir_addr, pkt_list->length); + *ptxsc_wlhdr_len = pkt_list->length; + + /* pkt_list[0] */ + ptxsc_pkt_list0->vir_addr = ptxsc_wlhdr; + ptxsc_pkt_list0->length = pkt_list->length; + #ifdef CONFIG_PCI_HCI + txsc_fill_txreq_phyaddr(padapter, ptxsc_pkt_list0); + #endif + + /* META DATA */ + _rtw_memcpy(ptxsc_mdata, &txreq->mdata, sizeof(*ptxsc_mdata)); + + /* FRAGE_LEN */ + psta->txsc_entry_cache[idx].txsc_frag_len = pxframe->attrib.frag_len_txsc; + + psta->txsc_entry_cache[idx].txsc_is_used = 1; + psta->txsc_cache_idx = idx; + psta->txsc_cur_idx = (psta->txsc_cur_idx + 1) % CORE_TXSC_ENTRY_NUM; + if (psta->txsc_cache_num < CORE_TXSC_ENTRY_NUM) + psta->txsc_cache_num++; + + psta->txsc_path_slow++; + + pxmitpriv->ptxsc_sta_cached = psta; + + txreq->treq_type = RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC | RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC; + + /* set shortcut id */ + txreq->shortcut_id = idx; + psta->txsc_entry_cache[idx].txsc_phl_id = idx; + + /* disable phl txsc */ + if (!(pxmitpriv->txsc_debug_mask&BIT1)) + txreq->shortcut_id = 0; + + RTW_PRINT("[CORE_TXSC][ADD] core_txsc_idx:%d(cur_idx:%d), txreq_sc_id:%d, txsc_frag_len:%d\n", + idx, psta->txsc_cur_idx, txreq->shortcut_id, psta->txsc_entry_cache[idx].txsc_frag_len); + + /* for debug */ + _print_txreq_mdata(ptxsc_mdata, __func__); + + _rtw_spinunlock_bh(&pxmitpriv->txsc_lock); +} + +u8 txsc_get_sc_cached_entry(_adapter *padapter, struct sk_buff *pskb, struct txsc_pkt_entry *txsc_pkt) +{ + txsc_init_pkt_entry(padapter, pskb, txsc_pkt); + return txsc_get_sc_entry(padapter, pskb, txsc_pkt); +} + +void txsc_add_sc_cache_entry(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt) +{ + txsc_add_sc_check(padapter, pxframe, txsc_pkt); + txsc_prepare_sc_entry(padapter, pxframe, txsc_pkt); +} + +u8 txsc_apply_sc_cached_entry(_adapter *padapter, struct txsc_pkt_entry *txsc_pkt) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_pkt_buf_list *pkt_list = NULL; + struct rtw_pkt_buf_list *pkt_list0 = NULL; + struct rtw_t_meta_data *mdata = NULL; + struct rtw_xmit_req *txreq = NULL; + struct xmit_txreq_buf *txreq_buf = NULL; + struct txsc_entry *txsc; + struct sta_info *psta = txsc_pkt->psta; + struct sk_buff *xmit_skb[MAX_TXSC_SKB_NUM]; + u8 *hdr = NULL; + u16 *qc; + int wlhdr_copy_len, payload_offset = ETH_HLEN; + u8 idx, priority = 0, res = _SUCCESS; + u8 i, skb_cnt = 0, is_hdr_need_update = 0, txsc_wlhdr_len; + #ifndef USE_ONE_WLHDR + u8 *head, *ptxsc_wlhdr; + #endif + + if (!pxmitpriv->txsc_enable || !psta) + return _SUCCESS; + + if (txsc_pkt->step != TXSC_APPLY && + txsc_pkt->step != TXSC_AMSDU_APPLY && + txsc_pkt->step != TXSC_DEBUG) + return _SUCCESS; + + _rtw_memset(xmit_skb, 0x0, sizeof(xmit_skb)); + + /* get cached entry */ + idx = txsc_pkt->txsc_id; + txsc = &psta->txsc_entry_cache[idx]; + + pkt_list0 = &txsc->txsc_pkt_list0; + mdata = &txsc->txsc_mdata; + #ifdef USE_ONE_WLHDR + txsc_wlhdr_len = pkt_list0->length; + #else + ptxsc_wlhdr = (u8 *)txsc->txsc_wlhdr; + txsc_wlhdr_len = txsc->txsc_wlhdr_len; + #endif + + if (txsc_pkt->step == TXSC_DEBUG) { + _rtw_memset(psta->debug_buf, 0x0, (sizeof(struct rtw_xmit_req)+sizeof(struct rtw_pkt_buf_list)*2)); + txreq = (struct rtw_xmit_req *)psta->debug_buf; + pkt_list = (struct rtw_pkt_buf_list *)psta->debug_buf + sizeof(struct rtw_xmit_req); + } else { + #ifdef USE_ONE_WLHDR + txreq_buf = (struct xmit_txreq_buf *)get_txreq_buffer(padapter, (u8 **)&txreq, (u8 **)&pkt_list, NULL, NULL); + #else + txreq_buf = (struct xmit_txreq_buf *)get_txreq_buffer(padapter, (u8 **)&txreq, (u8 **)&pkt_list, (u8 **)&head, NULL); + #endif + + if (txreq_buf == NULL) { + res = _FAIL; + goto exit; + } + } + + /* init txreq buf */ + txreq_buf->adapter = padapter; + + /* fill txreq other */ + txreq->os_priv = (void *)txreq_buf; + txreq->pkt_list = (u8 *)pkt_list; + txreq->pkt_cnt = 0; + txreq->total_len = 0; + + /* fill txsc pkt entry */ + txsc_pkt->ptxreq = txreq; + + { + /* for no tx_amsdu case */ + xmit_skb[0] = txsc_pkt->xmit_skb[0]; + skb_cnt = txsc_pkt->skb_cnt; + } + + if (skb_cnt == 0) + RTW_PRINT("[ERR][%s:%d] skb_cnt = 0 is a fatel error, plz check\n", __func__, __LINE__); + + /* fill_txreq_mdata */ + _rtw_memcpy(&txreq->mdata, mdata, sizeof(txreq->mdata)); + + /* Update TID from IP header */ + /* priority = *(xmit_skb[0]->data + ETH_HLEN + 1); */ + /*txreq->mdata.tid = tos_to_up(priority); */ + priority = txreq->mdata.tid = txsc_pkt->priority; + + /* SW shortcut --- */ + /* rtw_core_wlan_fill_head */ + /* use swseq in amsdu */ + if (txreq->mdata.hw_seq_mode == 0) { + /* generate sw seq */ + //priority = txreq->mdata.tid; + psta->sta_xmitpriv.txseq_tid[priority]++; + psta->sta_xmitpriv.txseq_tid[priority] &= 0xFFF; + txreq->mdata.sw_seq = psta->sta_xmitpriv.txseq_tid[priority]; + + hdr = txsc->txsc_wlhdr; + SetSeqNum(hdr, txreq->mdata.sw_seq); + + is_hdr_need_update = 1; + } + + wlhdr_copy_len = txsc_wlhdr_len; + + /* WLAN header from cache */ + #ifdef USE_ONE_WLHDR + _rtw_memcpy(pkt_list, pkt_list0, sizeof(struct rtw_pkt_buf_list)); + #else + #ifdef USE_PREV_WLHDR_BUF + if (txreq_buf->macid == txreq->mdata.macid && txreq_buf->txsc_id == idx) { + if (is_hdr_need_update) + SetSeqNum(head, txreq->mdata.sw_seq);/* set sw seq */ + } else + #endif /* USE_PREV_WLHDR_BUF */ + { + _rtw_memcpy(head, ptxsc_wlhdr, wlhdr_copy_len); + } + + /* fill wlhdr in pkt_list[0] */ + pkt_list->vir_addr = head; + pkt_list->length = wlhdr_copy_len; + #ifdef CONFIG_PCI_HCI + txsc_fill_txreq_phyaddr(padapter, pkt_list); + #endif + #endif/* USE_ONE_WLHDR */ + + txreq->total_len += pkt_list->length; + txreq->pkt_cnt++; + + #ifdef USE_PREV_WLHDR_BUF + txreq_buf->macid = txreq->mdata.macid; + txreq_buf->txsc_id = idx; + #endif/* USE_PREV_WLHDR_BUF */ + + /* Payload w.o. ether header */ /* CONFIG_TXSC_AMSDU for multiple skb */ + for (i = 0; i < skb_cnt; i++) { + pkt_list++; + + pkt_list->vir_addr = xmit_skb[i]->data + payload_offset; + pkt_list->length = xmit_skb[i]->len - payload_offset; + + txreq->total_len += pkt_list->length; + txreq->pkt_cnt++; + #ifdef CONFIG_PCI_HCI + txsc_fill_txreq_phyaddr(padapter, pkt_list); + #endif + + txreq_buf->pkt[i] = (u8 *)xmit_skb[i]; + } + + txreq->treq_type = RTW_PHL_TREQ_TYPE_CORE_TXSC; + + if (txsc_pkt->step == TXSC_APPLY) { + psta->txsc_cache_hit++; + txsc->txsc_cache_hit++; + } else + psta->txsc_path_slow++; + /* SW shortcut --- */ + + txreq_buf->pkt_cnt = skb_cnt;/* for recycle multiple skb */ + txreq->mdata.pktlen = txreq->total_len; + txreq->shortcut_id = psta->txsc_entry_cache[idx].txsc_phl_id; + + if (!(pxmitpriv->txsc_debug_mask&BIT1)) + txreq->shortcut_id = 0; + + /* send addbareq */ + txsc_issue_addbareq_cmd(padapter, priority, psta, _TRUE); + +#ifdef RTW_PHL_DBG_CMD + /* Update force rate settings so force rate takes effects + * after shortcut cached + */ + if (padapter->txForce_enable) { + if (padapter->txForce_rate != INV_TXFORCE_VAL) { + txreq->mdata.f_rate = padapter->txForce_rate; + txreq->mdata.userate_sel = 1; + txreq->mdata.dis_data_rate_fb = 1; + txreq->mdata.dis_rts_rate_fb = 1; + } + if (padapter->txForce_agg != INV_TXFORCE_VAL) + txreq->mdata.ampdu_en = padapter->txForce_agg; + if (padapter->txForce_aggnum != INV_TXFORCE_VAL) + txreq->mdata.max_agg_num = padapter->txForce_aggnum; + if (padapter->txForce_gi != INV_TXFORCE_VAL) + txreq->mdata.f_gi_ltf = padapter->txForce_gi; + if (padapter->txForce_ampdu_density != INV_TXFORCE_VAL) + txreq->mdata.ampdu_density = padapter->txForce_ampdu_density; + if (padapter->txForce_bw != INV_TXFORCE_VAL) + txreq->mdata.f_bw = padapter->txForce_bw; + } +#endif /* RTW_PHL_DBG_CMD */ + + /* for tx debug */ + _print_txreq_mdata(&txreq->mdata, __func__); + _print_txreq_pklist(NULL, txsc_pkt->ptxreq, xmit_skb[0], __func__); + +exit: + return res; +} + +void txsc_free_txreq(_adapter *padapter, struct rtw_xmit_req *txreq) +{ + struct xmit_txreq_buf *ptxreq_buf = NULL; + struct sk_buff *tx_skb = NULL; + _queue *queue = NULL; + u8 i; + + if (txreq != NULL) + ptxreq_buf = txreq->os_priv; + else + return; + + #ifdef CONFIG_PCI_HCI + #ifdef USE_ONE_WLHDR + txsc_recycle_txreq_phyaddr(padapter, txreq); + #else + core_recycle_txreq_phyaddr(padapter, txreq); + #endif + #endif + + if (!ptxreq_buf) { + RTW_ERR("%s: NULL ptxreq_buf !!\n", __func__); + rtw_warn_on(1); + return; + } + + queue = &padapter->free_txreq_queue; + _rtw_spinlock_bh(&queue->lock); + + rtw_list_delete(&ptxreq_buf->list); + rtw_list_insert_tail(&ptxreq_buf->list, get_list_head(queue)); + + txreq->os_priv = NULL; + txreq->pkt_list = NULL; + txreq->treq_type = RTW_PHL_TREQ_TYPE_NORMAL; + + /* this must be protected in spinlock section */ + if (ptxreq_buf->pkt_cnt == 0) + RTW_PRINT("[ERR][%s:%d] pkt_cnt = 0 is a fatel error, plz check\n", __func__, __LINE__); + + for (i = 0; i < ptxreq_buf->pkt_cnt; i++) { + tx_skb = (struct sk_buff *)ptxreq_buf->pkt[i]; + if (tx_skb) + rtw_os_pkt_complete(padapter, tx_skb); + else + RTW_DBG("%s:tx recyele: tx_skb=NULL\n", __func__); + ptxreq_buf->pkt[i] = NULL; + } + padapter->free_txreq_cnt++; + + _rtw_spinunlock_bh(&queue->lock); +} + +void txsc_debug_sc_entry(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_pkt_buf_list *pkt_list = NULL; + struct rtw_pkt_buf_list *txsc_pkt_list = NULL; + struct rtw_xmit_req *txreq = pxframe->phl_txreq; + struct rtw_xmit_req *ptxsc_txreq = txsc_pkt->ptxreq; + u8 i; + + if (txsc_pkt->step != TXSC_DEBUG) + return; + + if (pxmitpriv->txsc_debug_mask&BIT2) { + + RTW_PRINT("\n\nNormal Path TXREQ: %p\n\n", txreq); + txsc_dump_data((u8 *)txreq, sizeof(struct rtw_xmit_req), "txreq:"); + RTW_PRINT("os_priv=%p\n", txreq->os_priv); + RTW_PRINT("treq_type=%d shortcut_id=%d\n", txreq->treq_type, txreq->shortcut_id); + RTW_PRINT("total_len=%d pkt_cnt=%d\n", txreq->total_len, txreq->pkt_cnt); + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + for (i = 0; i < txreq->pkt_cnt; i++) { + RTW_PRINT("[%d]", i); + txsc_dump_data((u8 *)pkt_list, sizeof(struct rtw_pkt_buf_list), "pklist"); + txsc_dump_data((u8 *)pkt_list->vir_addr, pkt_list->length, "pkt_list->vir_addr"); + pkt_list++; + } + RTW_PRINT("mdata: pktlen=%d sw_seq=%d\n", txreq->mdata.pktlen, txreq->mdata.sw_seq); + + RTW_PRINT("\n\nShortcut Path TXREQ: %p\n\n", ptxsc_txreq); + txsc_dump_data((u8 *)ptxsc_txreq, sizeof(struct rtw_xmit_req), "ptxsc_txreq:"); + RTW_PRINT("os_priv=%p\n", ptxsc_txreq->os_priv); + RTW_PRINT("treq_type=%d shortcut_id=%d\n", ptxsc_txreq->treq_type, ptxsc_txreq->shortcut_id); + RTW_PRINT("total_len=%d pkt_cnt=%d\n", ptxsc_txreq->total_len, ptxsc_txreq->pkt_cnt); + txsc_pkt_list = (struct rtw_pkt_buf_list *)ptxsc_txreq->pkt_list; + for (i = 0; i < txreq->pkt_cnt; i++) { + RTW_PRINT("[%d]", i); + txsc_dump_data((u8 *)txsc_pkt_list, sizeof(struct rtw_pkt_buf_list), "pklist"); + txsc_dump_data((u8 *)txsc_pkt_list->vir_addr, txsc_pkt_list->length, "pkt_list->vir_addr"); + txsc_pkt_list++; + } + RTW_PRINT("mdata: pktlen=%d sw_seq=%d\n", ptxsc_txreq->mdata.pktlen, ptxsc_txreq->mdata.sw_seq); + + } else { + if (!_rtw_memcmp(&txreq->mdata, &ptxsc_txreq->mdata, sizeof(struct rtw_t_meta_data))) { + txsc_dump_data((u8 *)&txreq->mdata, sizeof(struct rtw_t_meta_data), "txreq->mdata"); + txsc_dump_data((u8 *)&ptxsc_txreq->mdata, sizeof(struct rtw_t_meta_data), "ptxsc_txreq->mdata"); + } + + pkt_list = (struct rtw_pkt_buf_list *)txreq->pkt_list; + txsc_pkt_list = (struct rtw_pkt_buf_list *)ptxsc_txreq->pkt_list; + if (pkt_list->length != txsc_pkt_list->length) { + txsc_dump_data((u8 *)pkt_list, sizeof(struct rtw_pkt_buf_list), "pkt_list[0]"); + txsc_dump_data((u8 *)txsc_pkt_list, sizeof(struct rtw_pkt_buf_list), "txsc_pkt_list[0]"); + txsc_dump_data((u8 *)pkt_list->vir_addr, pkt_list->length, "pkt_list[0]->vir_addr"); + txsc_dump_data(txsc_pkt_list->vir_addr, pkt_list->length, "txsc_pkt_list[0]->vir_addr"); + } else if (pkt_list->length == txsc_pkt_list->length) { + if (!_rtw_memcmp(pkt_list->vir_addr, txsc_pkt_list->vir_addr, pkt_list->length)) { + txsc_dump_data((u8 *)pkt_list->vir_addr, pkt_list->length, "pkt_list[0]->vir_addr"); + txsc_dump_data((u8 *)txsc_pkt_list->vir_addr, pkt_list->length, "txsc_pkt_list[0]->vir_addr"); + } + } + } + + /* DO NOT WD CACHE */ + txreq->shortcut_id = 0; + txreq->treq_type = RTW_PHL_TREQ_TYPE_NORMAL; +} + +#ifdef CONFIG_80211N_HT +static u8 txsc_issue_addbareq_check(_adapter *padapter, u8 issue_when_busy) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct registry_priv *pregistry = &padapter->registrypriv; + + if (pregistry->tx_quick_addba_req == 0) { + if ((issue_when_busy == _TRUE) && (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE)) + return _FALSE; + + if (pmlmepriv->LinkDetectInfo.NumTxOkInPeriod < 100) + return _FALSE; + } + + return _TRUE; +} + +void txsc_issue_addbareq_cmd(_adapter *padapter, u8 priority, struct sta_info *psta, u8 issue_when_busy) +{ + u8 issued; + struct ht_priv *phtpriv; + + if (txsc_issue_addbareq_check(padapter, issue_when_busy) == _FALSE) + return; + + phtpriv = &psta->htpriv; + + if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { + issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1; + issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1; + + if (issued == 0) { + RTW_INFO("rtw_issue_addbareq_cmd, p=%d\n", priority); + psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); + rtw_addbareq_cmd(padapter, (u8) priority, psta->phl_sta->mac_addr); + } + } + +} +#endif /* CONFIG_80211N_HT */ +#endif /* CONFIG_CORE_TXSC */ + diff --git a/core/wds/rtw_wds.c b/core/wds/rtw_wds.c index fd88b1c..929b1bc 100644 --- a/core/wds/rtw_wds.c +++ b/core/wds/rtw_wds.c @@ -173,7 +173,7 @@ void dump_wpath(void *sel, _adapter *adapter) wpath = rtw_wds_path_lookup_by_idx(adapter, idx); if (wpath) { _rtw_memcpy(dst, wpath->dst, ETH_ALEN); - _rtw_memcpy(next_hop, wpath->next_hop->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(next_hop, wpath->next_hop->phl_sta->mac_addr, ETH_ALEN); age_ms = rtw_get_passing_time_ms(wpath->last_update); } @@ -321,7 +321,7 @@ static void rtw_wds_table_flush_by_iface(struct rtw_wds_table *tbl) if (!tbl) return; - + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); if (ret) return; @@ -452,7 +452,7 @@ int rtw_wds_nexthop_lookup(_adapter *adapter, const u8 *da, u8 *ra) next_hop = rtw_rcu_dereference(wpath->next_hop); if (next_hop) { - _rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(ra, next_hop->phl_sta->mac_addr, ETH_ALEN); err = 0; } diff --git a/include/_hal_api_tmp.h b/include/_hal_api_tmp.h new file mode 100644 index 0000000..f1aacb9 --- /dev/null +++ b/include/_hal_api_tmp.h @@ -0,0 +1,483 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_TMP_H_ +#define _HAL_API_TMP_H_ + + +/**** may be get from hal_com **********************************/ + +#define H2C_MSR_ROLE_RSVD 0 +#define H2C_MSR_ROLE_STA 1 +#define H2C_MSR_ROLE_AP 2 +#define H2C_MSR_ROLE_GC 3 +#define H2C_MSR_ROLE_GO 4 +#define H2C_MSR_ROLE_TDLS 5 +#define H2C_MSR_ROLE_ADHOC 6 +#define H2C_MSR_ROLE_MESH 7 +#define H2C_MSR_ROLE_MAX 8 + +/*************************************************************************************/ +typedef enum _HW_VARIABLES { + HW_VAR_NET_TYPE, + HW_VAR_SET_OPMODE, + HW_VAR_MAC_ADDR, + HW_VAR_BSSID, + HW_VAR_BASIC_RATE, + HW_VAR_TXPAUSE, + HW_VAR_BCN_FUNC, + HW_VAR_CORRECT_TSF, + HW_VAR_RCR, + HW_VAR_MLME_DISCONNECT, + HW_VAR_MLME_SITESURVEY, + HW_VAR_MLME_JOIN, + HW_VAR_ON_RCR_AM, + HW_VAR_OFF_RCR_AM, + HW_VAR_BEACON_INTERVAL, + HW_VAR_SLOT_TIME, + HW_VAR_RESP_SIFS, + HW_VAR_ACK_PREAMBLE, + HW_VAR_SEC_CFG, + HW_VAR_SEC_DK_CFG, + HW_VAR_BCN_VALID, + HW_VAR_FREECNT, + HW_VAR_STOP_BCN, + HW_VAR_RESUME_BCN, + + /* PHYDM odm->SupportAbility */ + HW_VAR_CAM_EMPTY_ENTRY, + HW_VAR_CAM_INVALID_ALL, + HW_VAR_AC_PARAM_VO, + HW_VAR_AC_PARAM_VI, + HW_VAR_AC_PARAM_BE, + HW_VAR_AC_PARAM_BK, + HW_VAR_ACM_CTRL, +#ifdef CONFIG_WMMPS_STA + HW_VAR_UAPSD_TID, +#endif /* CONFIG_WMMPS_STA */ + HW_VAR_AMPDU_MIN_SPACE, +#ifdef CONFIG_80211N_HT + HW_VAR_AMPDU_FACTOR, +#endif /* CONFIG_80211N_HT */ + HW_VAR_RXDMA_AGG_PG_TH, + HW_VAR_SET_RPWM, + HW_VAR_CPWM, + HW_VAR_H2C_FW_PWRMODE, + HW_VAR_H2C_INACTIVE_IPS, + HW_VAR_H2C_FW_JOINBSSRPT, + HW_VAR_FWLPS_RF_ON, + HW_VAR_H2C_FW_P2P_PS_OFFLOAD, +#ifdef CONFIG_LPS_PG + HW_VAR_LPS_PG_HANDLE, +#endif + HW_VAR_TRIGGER_GPIO_0, + HW_VAR_BT_SET_COEXIST, + HW_VAR_BT_ISSUE_DELBA, + HW_VAR_FIFO_CLEARN_UP, + HW_VAR_RESTORE_HW_SEQ, + HW_VAR_CHECK_TXBUF, + HW_VAR_PCIE_STOP_TX_DMA, + HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ + /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */ + /* Unit in microsecond. 0 means disable this function. */ +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) + HW_VAR_WOWLAN, + HW_VAR_WAKEUP_REASON, +#endif + HW_VAR_RPWM_TOG, +#ifdef CONFIG_GPIO_WAKEUP + HW_VAR_WOW_OUTPUT_GPIO, + HW_VAR_WOW_INPUT_GPIO, + HW_SET_GPIO_WL_CTRL, +#endif + HW_VAR_SYS_CLKR, + HW_VAR_NAV_UPPER, + HW_VAR_CHK_HI_QUEUE_EMPTY, + HW_VAR_CHK_MGQ_CPU_EMPTY, + HW_VAR_DL_BCN_SEL, + HW_VAR_AMPDU_MAX_TIME, + HW_VAR_WIRELESS_MODE, + HW_VAR_USB_MODE, + HW_VAR_PORT_SWITCH, + HW_VAR_PORT_CFG, + HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/ + #ifdef DBG_CHECK_FW_PS_STATE + HW_VAR_FW_PS_STATE, + #endif + HW_VAR_SOUNDING_ENTER, + HW_VAR_SOUNDING_LEAVE, + HW_VAR_SOUNDING_RATE, + HW_VAR_SOUNDING_STATUS, + HW_VAR_SOUNDING_FW_NDPA, + HW_VAR_SOUNDING_CLK, + HW_VAR_SOUNDING_SET_GID_TABLE, + HW_VAR_SOUNDING_CSI_REPORT, + HW_VAR_DL_RSVD_PAGE, + HW_VAR_DUMP_MAC_QUEUE_INFO, + HW_VAR_ASIX_IOT, + HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, + HW_VAR_CH_SW_IQK_INFO_BACKUP, + HW_VAR_CH_SW_IQK_INFO_RESTORE, + + HW_VAR_DBI, + HW_VAR_MDIO, + HW_VAR_L1OFF_CAPABILITY, + HW_VAR_L1OFF_NIC_SUPPORT, +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + HW_VAR_TDLS_BCN_EARLY_C2H_RPT, +#endif +#endif + HW_VAR_DUMP_MAC_TXFIFO, + HW_VAR_PWR_CMD, + + HW_VAR_SET_SOML_PARAM, + HW_VAR_ENABLE_RX_BAR, + HW_VAR_TSF_AUTO_SYNC, + HW_VAR_LPS_STATE_CHK, + #ifdef CONFIG_RTS_FULL_BW + HW_VAR_SET_RTS_BW, + #endif +#if defined(CONFIG_PCI_HCI) + HW_VAR_ENSWBCN, +#endif + HW_VAR_ACKTO, + HW_VAR_ACKTO_CCK, +} HW_VARIABLES; + +static inline u8 rtw_hal_set_hwreg(_adapter *padapter, u8 var, u8 *val) +{ + return 0; +} +static inline void rtw_hal_get_hwreg(_adapter *padapter, u8 var, u8 *val) +{} +typedef enum _HAL_DEF_VARIABLE { + HAL_DEF_IS_SUPPORT_ANT_DIV, + HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ + HAL_DEF_BEAMFORMER_CAP, + HAL_DEF_BEAMFORMEE_CAP, + HW_VAR_MAX_RX_AMPDU_FACTOR, + HW_DEF_RA_INFO_DUMP, + HAL_DEF_DBG_DUMP_TXPKT, + HAL_DEF_TX_PAGE_SIZE, + HW_VAR_BEST_AMPDU_DENSITY, +} HAL_DEF_VARIABLE; + +static inline u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE def_var, void *val) +{ + return 0; +} + +u8 rtw_hal_get_def_var(struct _ADAPTER *a, + enum _HAL_DEF_VARIABLE def_var, void *val); + +static inline u8 rtw_hal_check_ips_status(_adapter *padapter) +{ + return 0; +} + + +static inline void rtw_hal_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key) +{} +static inline void rtw_hal_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{} +static inline void rtw_hal_sec_clr_cam_ent(_adapter *adapter, u8 id) +{} +static inline bool rtw_hal_sec_read_cam_is_gk(_adapter *adapter, u8 id) +{ + return _TRUE; +} + +static inline u8 rtw_hal_get_current_tx_rate(_adapter *adapter, struct sta_info *psta) +{ + return 0; +} +static u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta) +{ + return 0; +} + +static inline void rtw_hal_linked_info_dump(_adapter *padapter, u8 benable) +{} + +static inline bool rtw_hal_get_phy_edcca_flag(_adapter *adapter) +{ + return _TRUE; +} + +static inline u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port) +{ + return 1; +} + +static inline void rtw_hal_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num) +{} + + +/*u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);*/ +static inline u8 rtw_hal_get_htndp_tx_rate(_adapter *adapter, u8 bfer_str_num) +{ + return 0; +} +/*u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);*/ +static inline u8 rtw_hal_get_vht_ndp_tx_rate(_adapter *adapter, u8 bfer_str_num) +{ + return 0; +} + +static inline u8 rtw_hal_get_sounding_info(_adapter *adapter,u16 *throughput, + u8 total_bfee_num, u8 *tx_rate) +{ + return 0; +} + +static inline void rtw_hal_dump_target_tx_power(void *sel, _adapter *adapter) +{} + +static inline void rtw_hal_dump_tx_power_by_rate(void *sel, _adapter *adapter) +{} + +static inline void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) +{} + +static inline void rtw_hal_dump_trx_mode(void *sel, _adapter *adapter) +{} + +static inline void rtw_hal_phy_adaptivity_parm_msg(void *sel, _adapter *adapter) +{} + +static inline void rtw_hal_phy_adaptivity_parm_set(_adapter *adapter, + s8 th_l2h_ini, s8 th_edcca_hl_diff) +{} + + + +#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) +#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0 +#endif + +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +void rtw_sw_led_blink_uc_trx_only(LED_DATA *led); +void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl); +#endif +void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl); +void rtw_led_tx_control(_adapter *adapter, const u8 *da); +void rtw_led_rx_control(_adapter *adapter, const u8 *da); +void rtw_led_set_iface_en(_adapter *adapter, u8 en); +void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask); +void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask); +void rtw_led_set_ctl_en_mask_primary(_adapter *adapter); +void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter); +#else +#define rtw_led_control(adapter, ctl) do {} while (0) +#define rtw_led_tx_control(adapter, da) do {} while (0) +#define rtw_led_rx_control(adapter, da) do {} while (0) +#define rtw_led_set_iface_en(adapter, en) do {} while (0) +#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0) +#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0) +#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0) +#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0) +#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */ + +#ifdef CONFIG_PCI_HCI +static inline void rtw_hal_irp_reset(_adapter *padapter) +{} +static inline void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data) +{} +static inline u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr) +{ return 0;} +static inline void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data) +{} +static inline u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr) +{ return 0;} +static inline u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter) +{ return 0;} + +static inline u8 rtw_hal_pci_l1off_capability(_adapter *padapter) +{ return 0;} + +static inline void rtw_hal_unmap_beacon_icf(_adapter *padapter) +{ + //hal->hal_ops.unmap_beacon_icf(padapter); +} +#endif + +#if defined(CONFIG_PCI_HCI) +static inline u8 rtw_hal_check_nic_enough_desc_all(_adapter *padapter) +{ return _SUCCESS;} +static s32 rtw_hal_dump_xframe(_adapter *adapter, struct xmit_frame *pxmitframe) +{ return _SUCCESS;} + + +#endif + +static inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid) +{ return 0;} +static inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid) +{ return 0;} +static inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter) +{ return 0;} +static inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter) +{ return 0;} + +static void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len) +{ + //adapter->dvobj->hal_func.hal_mac_c2h_handler(adapter, buf, len); +} +static inline s32 rtw_hal_fill_h2c_cmd(_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ +/* + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); + + if (GET_PHL_COM(pri_adapter)->fw_ready == _TRUE) + return hal->hal_ops.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); + else if (padapter->registrypriv.mp_mode == 0) + RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" + , FUNC_ADPT_ARG(padapter), ElementID); +*/ + return 0; +} + +#ifdef CONFIG_DFS_MASTER +static inline void rtw_odm_radar_detect_reset(_adapter *adapter) +{ + //phydm_radar_detect_reset(adapter_to_phydm(adapter)); +} + +static inline void rtw_odm_radar_detect_disable(_adapter *adapter) +{ + //phydm_radar_detect_disable(adapter_to_phydm(adapter)); +} + +/* called after ch, bw is set */ +static inline void rtw_odm_radar_detect_enable(_adapter *adapter) +{ + //phydm_radar_detect_enable(adapter_to_phydm(adapter)); +} + +static inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter) +{ + return 0;//phydm_radar_detect(adapter_to_phydm(adapter)); +} + +static inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj) +{ + return 0;//phydm_dfs_polling_time(dvobj_to_phydm(dvobj)); +} +#endif /* CONFIG_DFS_MASTER */ + +static inline void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid) +{ + //if (hal->hal_ops.reqtxrpt) + //hal->hal_ops.reqtxrpt(padapter, macid); +} +static inline u8 rtw_hal_get_port(_adapter *adapter) +{ return 0;} + +static inline void rtw_hal_read_edca(_adapter *adapter, u16 *vo_params, u16 *vi_params, + u16 *be_params, u16 *bk_params) +{ + //hal->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params); +} + +static inline void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter) +{} + +static inline void rtw_hal_dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta) +{} +static inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd + (_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid) +{ return 0;} + +static inline void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action) +{} + +enum QSEL_ID { + QSLT_BK_ID, + QSLT_BE_ID, + QSLT_VI_ID, + QSLT_VO_ID, + QSLT_BEACON_ID, + QSLT_HIGH_ID, + QSLT_MGNT_ID, + QSLT_CMD_ID +}; + +static inline u8 rtw_hal_get_qsel(_adapter *adapter, enum QSEL_ID qsel) +{ + /*QSLT_HIGH*/ + return 0; +} +/************************ xmit *******************/ +static inline void rtw_hal_bcn_param_setting(_adapter *padapter) +{ + //hal->hal_ops.set_beacon_param_handler(padapter); +} + +static inline void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel) +{} + + +/****************** GEORGIA_TODO_REDEFINE_IO ************************/ +static inline u32 rtw_hal_get_htsf(_adapter *adapter)/*get tst high 4 bytes */ +{ + return 0; +} +static inline u32 rtw_hal_get_ltsf(_adapter *adapter)/*get tst low 4 bytes */ +{ + return 0; +} + +static inline u32 rtw_hal_get_dma_statu(_adapter *adapter) +{ + return 0; +} +#ifdef DBG_TXBD_DESC_DUMP +static inline u32 rtw_hal_get_txbd_rwreg(_adapter *adapter) +{ + return 0; +} +#endif + +#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN +static inline u8 rtw_hal_sdio_leave_suspend(_adapter *adapter) +{ + return 0; +} +#endif + +#if defined(CONFIG_FWLPS_IN_IPS) +static inline void rtw_hal_set_fw_in_ips_mode(_adapter *padapter, u8 enable) +{} +#endif +#ifdef CONFIG_LPS_RPWM_TIMER +static inline bool rtw_hal_is_leave_ps(_adapter *padapter) +{ + return _FALSE; +} +#endif + + +static inline void rtw_hal_get_version(char *str, u32 len) +{ + //get hal version + //rtw_halmac_get_version(str, 30); + // get fw version + // get phy (bb/rf) version + // get btc version +} + + +#endif /*_HAL_API_TMP_H_*/ diff --git a/include/_hal_rate.h b/include/_hal_rate.h new file mode 100644 index 0000000..5a7f117 --- /dev/null +++ b/include/_hal_rate.h @@ -0,0 +1,1154 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HAL_RATE_H__ +#define __HAL_RATE_H__ + +/*----------------------------------------------------------- + * HW Rate def + * ----------------------------------------------------------- + * CCK Rates, TxHT = 0 */ +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0A +#define DESC_RATE54M 0x0B + +/* MCS Rates, TxHT = 1 */ +#define DESC_RATEMCS0 0x0C +#define DESC_RATEMCS1 0x0D +#define DESC_RATEMCS2 0x0E +#define DESC_RATEMCS3 0x0F +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1A +#define DESC_RATEMCS15 0x1B +#define DESC_RATEMCS16 0x1C +#define DESC_RATEMCS17 0x1D +#define DESC_RATEMCS18 0x1E +#define DESC_RATEMCS19 0x1F +#define DESC_RATEMCS20 0x20 +#define DESC_RATEMCS21 0x21 +#define DESC_RATEMCS22 0x22 +#define DESC_RATEMCS23 0x23 +#define DESC_RATEMCS24 0x24 +#define DESC_RATEMCS25 0x25 +#define DESC_RATEMCS26 0x26 +#define DESC_RATEMCS27 0x27 +#define DESC_RATEMCS28 0x28 +#define DESC_RATEMCS29 0x29 +#define DESC_RATEMCS30 0x2A +#define DESC_RATEMCS31 0x2B +#define DESC_RATEVHTSS1MCS0 0x2C +#define DESC_RATEVHTSS1MCS1 0x2D +#define DESC_RATEVHTSS1MCS2 0x2E +#define DESC_RATEVHTSS1MCS3 0x2F +#define DESC_RATEVHTSS1MCS4 0x30 +#define DESC_RATEVHTSS1MCS5 0x31 +#define DESC_RATEVHTSS1MCS6 0x32 +#define DESC_RATEVHTSS1MCS7 0x33 +#define DESC_RATEVHTSS1MCS8 0x34 +#define DESC_RATEVHTSS1MCS9 0x35 +#define DESC_RATEVHTSS2MCS0 0x36 +#define DESC_RATEVHTSS2MCS1 0x37 +#define DESC_RATEVHTSS2MCS2 0x38 +#define DESC_RATEVHTSS2MCS3 0x39 +#define DESC_RATEVHTSS2MCS4 0x3A +#define DESC_RATEVHTSS2MCS5 0x3B +#define DESC_RATEVHTSS2MCS6 0x3C +#define DESC_RATEVHTSS2MCS7 0x3D +#define DESC_RATEVHTSS2MCS8 0x3E +#define DESC_RATEVHTSS2MCS9 0x3F +#define DESC_RATEVHTSS3MCS0 0x40 +#define DESC_RATEVHTSS3MCS1 0x41 +#define DESC_RATEVHTSS3MCS2 0x42 +#define DESC_RATEVHTSS3MCS3 0x43 +#define DESC_RATEVHTSS3MCS4 0x44 +#define DESC_RATEVHTSS3MCS5 0x45 +#define DESC_RATEVHTSS3MCS6 0x46 +#define DESC_RATEVHTSS3MCS7 0x47 +#define DESC_RATEVHTSS3MCS8 0x48 +#define DESC_RATEVHTSS3MCS9 0x49 +#define DESC_RATEVHTSS4MCS0 0x4A +#define DESC_RATEVHTSS4MCS1 0x4B +#define DESC_RATEVHTSS4MCS2 0x4C +#define DESC_RATEVHTSS4MCS3 0x4D +#define DESC_RATEVHTSS4MCS4 0x4E +#define DESC_RATEVHTSS4MCS5 0x4F +#define DESC_RATEVHTSS4MCS6 0x50 +#define DESC_RATEVHTSS4MCS7 0x51 +#define DESC_RATEVHTSS4MCS8 0x52 +#define DESC_RATEVHTSS4MCS9 0x53 + +#define HDATA_RATE(rate)\ + (rate == DESC_RATE1M) ? "CCK_1M" :\ + (rate == DESC_RATE2M) ? "CCK_2M" :\ + (rate == DESC_RATE5_5M) ? "CCK5_5M" :\ + (rate == DESC_RATE11M) ? "CCK_11M" :\ + (rate == DESC_RATE6M) ? "OFDM_6M" :\ + (rate == DESC_RATE9M) ? "OFDM_9M" :\ + (rate == DESC_RATE12M) ? "OFDM_12M" :\ + (rate == DESC_RATE18M) ? "OFDM_18M" :\ + (rate == DESC_RATE24M) ? "OFDM_24M" :\ + (rate == DESC_RATE36M) ? "OFDM_36M" :\ + (rate == DESC_RATE48M) ? "OFDM_48M" :\ + (rate == DESC_RATE54M) ? "OFDM_54M" :\ + (rate == DESC_RATEMCS0) ? "MCS0" :\ + (rate == DESC_RATEMCS1) ? "MCS1" :\ + (rate == DESC_RATEMCS2) ? "MCS2" :\ + (rate == DESC_RATEMCS3) ? "MCS3" :\ + (rate == DESC_RATEMCS4) ? "MCS4" :\ + (rate == DESC_RATEMCS5) ? "MCS5" :\ + (rate == DESC_RATEMCS6) ? "MCS6" :\ + (rate == DESC_RATEMCS7) ? "MCS7" :\ + (rate == DESC_RATEMCS8) ? "MCS8" :\ + (rate == DESC_RATEMCS9) ? "MCS9" :\ + (rate == DESC_RATEMCS10) ? "MCS10" :\ + (rate == DESC_RATEMCS11) ? "MCS11" :\ + (rate == DESC_RATEMCS12) ? "MCS12" :\ + (rate == DESC_RATEMCS13) ? "MCS13" :\ + (rate == DESC_RATEMCS14) ? "MCS14" :\ + (rate == DESC_RATEMCS15) ? "MCS15" :\ + (rate == DESC_RATEMCS16) ? "MCS16" :\ + (rate == DESC_RATEMCS17) ? "MCS17" :\ + (rate == DESC_RATEMCS18) ? "MCS18" :\ + (rate == DESC_RATEMCS19) ? "MCS19" :\ + (rate == DESC_RATEMCS20) ? "MCS20" :\ + (rate == DESC_RATEMCS21) ? "MCS21" :\ + (rate == DESC_RATEMCS22) ? "MCS22" :\ + (rate == DESC_RATEMCS23) ? "MCS23" :\ + (rate == DESC_RATEMCS24) ? "MCS24" :\ + (rate == DESC_RATEMCS25) ? "MCS25" :\ + (rate == DESC_RATEMCS26) ? "MCS26" :\ + (rate == DESC_RATEMCS27) ? "MCS27" :\ + (rate == DESC_RATEMCS28) ? "MCS28" :\ + (rate == DESC_RATEMCS29) ? "MCS29" :\ + (rate == DESC_RATEMCS30) ? "MCS30" :\ + (rate == DESC_RATEMCS31) ? "MCS31" :\ + (rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\ + (rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\ + (rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\ + (rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\ + (rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\ + (rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\ + (rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\ + (rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\ + (rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\ + (rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\ + (rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\ + (rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\ + (rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\ + (rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\ + (rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\ + (rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\ + (rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\ + (rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\ + (rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\ + (rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\ + (rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\ + (rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\ + (rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\ + (rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\ + (rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\ + (rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\ + (rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\ + (rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\ + (rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\ + (rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" :\ + (rate == DESC_RATEVHTSS4MCS0) ? "VHTSS4MCS0" :\ + (rate == DESC_RATEVHTSS4MCS1) ? "VHTSS4MCS1" :\ + (rate == DESC_RATEVHTSS4MCS2) ? "VHTSS4MCS2" :\ + (rate == DESC_RATEVHTSS4MCS3) ? "VHTSS4MCS3" :\ + (rate == DESC_RATEVHTSS4MCS4) ? "VHTSS4MCS4" :\ + (rate == DESC_RATEVHTSS4MCS5) ? "VHTSS4MCS5" :\ + (rate == DESC_RATEVHTSS4MCS6) ? "VHTSS4MCS6" :\ + (rate == DESC_RATEVHTSS4MCS7) ? "VHTSS4MCS7" :\ + (rate == DESC_RATEVHTSS4MCS8) ? "VHTSS4MCS8" :\ + (rate == DESC_RATEVHTSS4MCS9) ? "VHTSS4MCS9" :\ + "UNKNOWN" + +enum hw_data_rate { + HRATE_CCK1 = 0x0, + HRATE_CCK2 = 0x1, + HRATE_CCK5_5 = 0x2, + HRATE_CCK11 = 0x3, + HRATE_OFDM6 = 0x4, + HRATE_OFDM9 = 0x5, + HRATE_OFDM12 = 0x6, + HRATE_OFDM18 = 0x7, + HRATE_OFDM24 = 0x8, + HRATE_OFDM36 = 0x9, + HRATE_OFDM48 = 0xA, + HRATE_OFDM54 = 0xB, + HRATE_MCS0 = 0x80, + HRATE_MCS1 = 0x81, + HRATE_MCS2 = 0x82, + HRATE_MCS3 = 0x83, + HRATE_MCS4 = 0x84, + HRATE_MCS5 = 0x85, + HRATE_MCS6 = 0x86, + HRATE_MCS7 = 0x87, + HRATE_MCS8 = 0x88, + HRATE_MCS9 = 0x89, + HRATE_MCS10 = 0x8A, + HRATE_MCS11 = 0x8B, + HRATE_MCS12 = 0x8C, + HRATE_MCS13 = 0x8D, + HRATE_MCS14 = 0x8E, + HRATE_MCS15 = 0x8F, + HRATE_MCS16 = 0x90, + HRATE_MCS17 = 0x91, + HRATE_MCS18 = 0x92, + HRATE_MCS19 = 0x93, + HRATE_MCS20 = 0x94, + HRATE_MCS21 = 0x95, + HRATE_MCS22 = 0x96, + HRATE_MCS23 = 0x97, + HRATE_MCS24 = 0x98, + HRATE_MCS25 = 0x99, + HRATE_MCS26 = 0x9A, + HRATE_MCS27 = 0x9B, + HRATE_MCS28 = 0x9C, + HRATE_MCS29 = 0x9D, + HRATE_MCS30 = 0x9E, + HRATE_MCS31 = 0x9F, + HRATE_VHT_NSS1_MCS0 = 0x100, + HRATE_VHT_NSS1_MCS1 = 0x101, + HRATE_VHT_NSS1_MCS2 = 0x102, + HRATE_VHT_NSS1_MCS3 = 0x103, + HRATE_VHT_NSS1_MCS4 = 0x104, + HRATE_VHT_NSS1_MCS5 = 0x105, + HRATE_VHT_NSS1_MCS6 = 0x106, + HRATE_VHT_NSS1_MCS7 = 0x107, + HRATE_VHT_NSS1_MCS8 = 0x108, + HRATE_VHT_NSS1_MCS9 = 0x109, + HRATE_VHT_NSS2_MCS0 = 0x110, + HRATE_VHT_NSS2_MCS1 = 0x111, + HRATE_VHT_NSS2_MCS2 = 0x112, + HRATE_VHT_NSS2_MCS3 = 0x113, + HRATE_VHT_NSS2_MCS4 = 0x114, + HRATE_VHT_NSS2_MCS5 = 0x115, + HRATE_VHT_NSS2_MCS6 = 0x116, + HRATE_VHT_NSS2_MCS7 = 0x117, + HRATE_VHT_NSS2_MCS8 = 0x118, + HRATE_VHT_NSS2_MCS9 = 0x119, + HRATE_VHT_NSS3_MCS0 = 0x120, + HRATE_VHT_NSS3_MCS1 = 0x121, + HRATE_VHT_NSS3_MCS2 = 0x122, + HRATE_VHT_NSS3_MCS3 = 0x123, + HRATE_VHT_NSS3_MCS4 = 0x124, + HRATE_VHT_NSS3_MCS5 = 0x125, + HRATE_VHT_NSS3_MCS6 = 0x126, + HRATE_VHT_NSS3_MCS7 = 0x127, + HRATE_VHT_NSS3_MCS8 = 0x128, + HRATE_VHT_NSS3_MCS9 = 0x129, + HRATE_VHT_NSS4_MCS0 = 0x130, + HRATE_VHT_NSS4_MCS1 = 0x131, + HRATE_VHT_NSS4_MCS2 = 0x132, + HRATE_VHT_NSS4_MCS3 = 0x133, + HRATE_VHT_NSS4_MCS4 = 0x134, + HRATE_VHT_NSS4_MCS5 = 0x135, + HRATE_VHT_NSS4_MCS6 = 0x136, + HRATE_VHT_NSS4_MCS7 = 0x137, + HRATE_VHT_NSS4_MCS8 = 0x138, + HRATE_VHT_NSS4_MCS9 = 0x139, + HRATE_HE_NSS1_MCS0 = 0x180, + HRATE_HE_NSS1_MCS1 = 0x181, + HRATE_HE_NSS1_MCS2 = 0x182, + HRATE_HE_NSS1_MCS3 = 0x183, + HRATE_HE_NSS1_MCS4 = 0x184, + HRATE_HE_NSS1_MCS5 = 0x185, + HRATE_HE_NSS1_MCS6 = 0x186, + HRATE_HE_NSS1_MCS7 = 0x187, + HRATE_HE_NSS1_MCS8 = 0x188, + HRATE_HE_NSS1_MCS9 = 0x189, + HRATE_HE_NSS1_MCS10 = 0x18A, + HRATE_HE_NSS1_MCS11 = 0x18B, + HRATE_HE_NSS2_MCS0 = 0x190, + HRATE_HE_NSS2_MCS1 = 0x191, + HRATE_HE_NSS2_MCS2 = 0x192, + HRATE_HE_NSS2_MCS3 = 0x193, + HRATE_HE_NSS2_MCS4 = 0x194, + HRATE_HE_NSS2_MCS5 = 0x195, + HRATE_HE_NSS2_MCS6 = 0x196, + HRATE_HE_NSS2_MCS7 = 0x197, + HRATE_HE_NSS2_MCS8 = 0x198, + HRATE_HE_NSS2_MCS9 = 0x199, + HRATE_HE_NSS2_MCS10 = 0x19A, + HRATE_HE_NSS2_MCS11 = 0x19B, + HRATE_HE_NSS3_MCS0 = 0x1A0, + HRATE_HE_NSS3_MCS1 = 0x1A1, + HRATE_HE_NSS3_MCS2 = 0x1A2, + HRATE_HE_NSS3_MCS3 = 0x1A3, + HRATE_HE_NSS3_MCS4 = 0x1A4, + HRATE_HE_NSS3_MCS5 = 0x1A5, + HRATE_HE_NSS3_MCS6 = 0x1A6, + HRATE_HE_NSS3_MCS7 = 0x1A7, + HRATE_HE_NSS3_MCS8 = 0x1A8, + HRATE_HE_NSS3_MCS9 = 0x1A9, + HRATE_HE_NSS3_MCS10 = 0x1AA, + HRATE_HE_NSS3_MCS11 = 0x1AB, + HRATE_HE_NSS4_MCS0 = 0x1B0, + HRATE_HE_NSS4_MCS1 = 0x1B1, + HRATE_HE_NSS4_MCS2 = 0x1B2, + HRATE_HE_NSS4_MCS3 = 0x1B3, + HRATE_HE_NSS4_MCS4 = 0x1B4, + HRATE_HE_NSS4_MCS5 = 0x1B5, + HRATE_HE_NSS4_MCS6 = 0x1B6, + HRATE_HE_NSS4_MCS7 = 0x1B7, + HRATE_HE_NSS4_MCS8 = 0x1B8, + HRATE_HE_NSS4_MCS9 = 0x1B9, + HRATE_HE_NSS4_MCS10 = 0x1BA, + HRATE_HE_NSS4_MCS11 = 0x1BB +}; + +static inline u16 mrate_to_hwrate(u16 rate) +{ + u16 ret = DESC_RATE1M; + + switch (rate) { + case MGN_1M: + ret = RTW_DATA_RATE_CCK1; + break; + case MGN_2M: + ret = RTW_DATA_RATE_CCK2; + break; + case MGN_5_5M: + ret = RTW_DATA_RATE_CCK5_5; + break; + case MGN_11M: + ret = RTW_DATA_RATE_CCK11; + break; + case MGN_6M: + ret = RTW_DATA_RATE_OFDM6; + break; + case MGN_9M: + ret = RTW_DATA_RATE_OFDM9; + break; + case MGN_12M: + ret = RTW_DATA_RATE_OFDM12; + break; + case MGN_18M: + ret = RTW_DATA_RATE_OFDM18; + break; + case MGN_24M: + ret = RTW_DATA_RATE_OFDM24; + break; + case MGN_36M: + ret = RTW_DATA_RATE_OFDM36; + break; + case MGN_48M: + ret = RTW_DATA_RATE_OFDM48; + break; + case MGN_54M: + ret = RTW_DATA_RATE_OFDM54; + break; + + case MGN_MCS0: + ret = RTW_DATA_RATE_MCS0; + break; + case MGN_MCS1: + ret = RTW_DATA_RATE_MCS1; + break; + case MGN_MCS2: + ret = RTW_DATA_RATE_MCS2; + break; + case MGN_MCS3: + ret = RTW_DATA_RATE_MCS3; + break; + case MGN_MCS4: + ret = RTW_DATA_RATE_MCS4; + break; + case MGN_MCS5: + ret = RTW_DATA_RATE_MCS5; + break; + case MGN_MCS6: + ret = RTW_DATA_RATE_MCS6; + break; + case MGN_MCS7: + ret = RTW_DATA_RATE_MCS7; + break; + case MGN_MCS8: + ret = RTW_DATA_RATE_MCS8; + break; + case MGN_MCS9: + ret = RTW_DATA_RATE_MCS9; + break; + case MGN_MCS10: + ret = RTW_DATA_RATE_MCS10; + break; + case MGN_MCS11: + ret = RTW_DATA_RATE_MCS11; + break; + case MGN_MCS12: + ret = RTW_DATA_RATE_MCS12; + break; + case MGN_MCS13: + ret = RTW_DATA_RATE_MCS13; + break; + case MGN_MCS14: + ret = RTW_DATA_RATE_MCS14; + break; + case MGN_MCS15: + ret = RTW_DATA_RATE_MCS15; + break; + case MGN_MCS16: + ret = RTW_DATA_RATE_MCS16; + break; + case MGN_MCS17: + ret = RTW_DATA_RATE_MCS17; + break; + case MGN_MCS18: + ret = RTW_DATA_RATE_MCS18; + break; + case MGN_MCS19: + ret = RTW_DATA_RATE_MCS19; + break; + case MGN_MCS20: + ret = RTW_DATA_RATE_MCS20; + break; + case MGN_MCS21: + ret = RTW_DATA_RATE_MCS21; + break; + case MGN_MCS22: + ret = RTW_DATA_RATE_MCS22; + break; + case MGN_MCS23: + ret = RTW_DATA_RATE_MCS23; + break; + case MGN_MCS24: + ret = RTW_DATA_RATE_MCS24; + break; + case MGN_MCS25: + ret = RTW_DATA_RATE_MCS25; + break; + case MGN_MCS26: + ret = RTW_DATA_RATE_MCS26; + break; + case MGN_MCS27: + ret = RTW_DATA_RATE_MCS27; + break; + case MGN_MCS28: + ret = RTW_DATA_RATE_MCS28; + break; + case MGN_MCS29: + ret = RTW_DATA_RATE_MCS29; + break; + case MGN_MCS30: + ret = RTW_DATA_RATE_MCS30; + break; + case MGN_MCS31: + ret = RTW_DATA_RATE_MCS31; + break; + + case MGN_VHT1SS_MCS0: + ret = RTW_DATA_RATE_VHT_NSS1_MCS0; + break; + case MGN_VHT1SS_MCS1: + ret = RTW_DATA_RATE_VHT_NSS1_MCS1; + break; + case MGN_VHT1SS_MCS2: + ret = RTW_DATA_RATE_VHT_NSS1_MCS2; + break; + case MGN_VHT1SS_MCS3: + ret = RTW_DATA_RATE_VHT_NSS1_MCS3; + break; + case MGN_VHT1SS_MCS4: + ret = RTW_DATA_RATE_VHT_NSS1_MCS4; + break; + case MGN_VHT1SS_MCS5: + ret = RTW_DATA_RATE_VHT_NSS1_MCS5; + break; + case MGN_VHT1SS_MCS6: + ret = RTW_DATA_RATE_VHT_NSS1_MCS6; + break; + case MGN_VHT1SS_MCS7: + ret = RTW_DATA_RATE_VHT_NSS1_MCS7; + break; + case MGN_VHT1SS_MCS8: + ret = RTW_DATA_RATE_VHT_NSS1_MCS8; + break; + case MGN_VHT1SS_MCS9: + ret = RTW_DATA_RATE_VHT_NSS1_MCS9; + break; + case MGN_VHT2SS_MCS0: + ret = RTW_DATA_RATE_VHT_NSS2_MCS0; + break; + case MGN_VHT2SS_MCS1: + ret = RTW_DATA_RATE_VHT_NSS2_MCS1; + break; + case MGN_VHT2SS_MCS2: + ret = RTW_DATA_RATE_VHT_NSS2_MCS2; + break; + case MGN_VHT2SS_MCS3: + ret = RTW_DATA_RATE_VHT_NSS2_MCS3; + break; + case MGN_VHT2SS_MCS4: + ret = RTW_DATA_RATE_VHT_NSS2_MCS4; + break; + case MGN_VHT2SS_MCS5: + ret = RTW_DATA_RATE_VHT_NSS2_MCS5; + break; + case MGN_VHT2SS_MCS6: + ret = RTW_DATA_RATE_VHT_NSS2_MCS6; + break; + case MGN_VHT2SS_MCS7: + ret = RTW_DATA_RATE_VHT_NSS2_MCS7; + break; + case MGN_VHT2SS_MCS8: + ret = RTW_DATA_RATE_VHT_NSS2_MCS8; + break; + case MGN_VHT2SS_MCS9: + ret = RTW_DATA_RATE_VHT_NSS2_MCS9; + break; + case MGN_VHT3SS_MCS0: + ret = RTW_DATA_RATE_VHT_NSS3_MCS0; + break; + case MGN_VHT3SS_MCS1: + ret = RTW_DATA_RATE_VHT_NSS3_MCS1; + break; + case MGN_VHT3SS_MCS2: + ret = RTW_DATA_RATE_VHT_NSS3_MCS2; + break; + case MGN_VHT3SS_MCS3: + ret = RTW_DATA_RATE_VHT_NSS3_MCS3; + break; + case MGN_VHT3SS_MCS4: + ret = RTW_DATA_RATE_VHT_NSS3_MCS4; + break; + case MGN_VHT3SS_MCS5: + ret = RTW_DATA_RATE_VHT_NSS3_MCS5; + break; + case MGN_VHT3SS_MCS6: + ret = RTW_DATA_RATE_VHT_NSS3_MCS6; + break; + case MGN_VHT3SS_MCS7: + ret = RTW_DATA_RATE_VHT_NSS3_MCS7; + break; + case MGN_VHT3SS_MCS8: + ret = RTW_DATA_RATE_VHT_NSS3_MCS8; + break; + case MGN_VHT3SS_MCS9: + ret = RTW_DATA_RATE_VHT_NSS3_MCS9; + break; + case MGN_VHT4SS_MCS0: + ret = RTW_DATA_RATE_VHT_NSS4_MCS0; + break; + case MGN_VHT4SS_MCS1: + ret = RTW_DATA_RATE_VHT_NSS4_MCS1; + break; + case MGN_VHT4SS_MCS2: + ret = RTW_DATA_RATE_VHT_NSS4_MCS2; + break; + case MGN_VHT4SS_MCS3: + ret = RTW_DATA_RATE_VHT_NSS4_MCS3; + break; + case MGN_VHT4SS_MCS4: + ret = RTW_DATA_RATE_VHT_NSS4_MCS4; + break; + case MGN_VHT4SS_MCS5: + ret = RTW_DATA_RATE_VHT_NSS4_MCS5; + break; + case MGN_VHT4SS_MCS6: + ret = RTW_DATA_RATE_VHT_NSS4_MCS6; + break; + case MGN_VHT4SS_MCS7: + ret = RTW_DATA_RATE_VHT_NSS4_MCS7; + break; + case MGN_VHT4SS_MCS8: + ret = RTW_DATA_RATE_VHT_NSS4_MCS8; + break; + case MGN_VHT4SS_MCS9: + ret = RTW_DATA_RATE_VHT_NSS4_MCS9; + break; + + case MGN_HE1SS_MCS0: + ret = RTW_DATA_RATE_HE_NSS1_MCS0; + break; + case MGN_HE1SS_MCS1: + ret = RTW_DATA_RATE_HE_NSS1_MCS1; + break; + case MGN_HE1SS_MCS2: + ret = RTW_DATA_RATE_HE_NSS1_MCS2; + break; + case MGN_HE1SS_MCS3: + ret = RTW_DATA_RATE_HE_NSS1_MCS3; + break; + case MGN_HE1SS_MCS4: + ret = RTW_DATA_RATE_HE_NSS1_MCS4; + break; + case MGN_HE1SS_MCS5: + ret = RTW_DATA_RATE_HE_NSS1_MCS5; + break; + case MGN_HE1SS_MCS6: + ret = RTW_DATA_RATE_HE_NSS1_MCS6; + break; + case MGN_HE1SS_MCS7: + ret = RTW_DATA_RATE_HE_NSS1_MCS7; + break; + case MGN_HE1SS_MCS8: + ret = RTW_DATA_RATE_HE_NSS1_MCS8; + break; + case MGN_HE1SS_MCS9: + ret = RTW_DATA_RATE_HE_NSS1_MCS9; + break; + case MGN_HE1SS_MCS10: + ret = RTW_DATA_RATE_HE_NSS1_MCS10; + break; + case MGN_HE1SS_MCS11: + ret = RTW_DATA_RATE_HE_NSS1_MCS11; + break; + case MGN_HE2SS_MCS0: + ret = RTW_DATA_RATE_HE_NSS2_MCS0; + break; + case MGN_HE2SS_MCS1: + ret = RTW_DATA_RATE_HE_NSS2_MCS1; + break; + case MGN_HE2SS_MCS2: + ret = RTW_DATA_RATE_HE_NSS2_MCS2; + break; + case MGN_HE2SS_MCS3: + ret = RTW_DATA_RATE_HE_NSS2_MCS3; + break; + case MGN_HE2SS_MCS4: + ret = RTW_DATA_RATE_HE_NSS2_MCS4; + break; + case MGN_HE2SS_MCS5: + ret = RTW_DATA_RATE_HE_NSS2_MCS5; + break; + case MGN_HE2SS_MCS6: + ret = RTW_DATA_RATE_HE_NSS2_MCS6; + break; + case MGN_HE2SS_MCS7: + ret = RTW_DATA_RATE_HE_NSS2_MCS7; + break; + case MGN_HE2SS_MCS8: + ret = RTW_DATA_RATE_HE_NSS2_MCS8; + break; + case MGN_HE2SS_MCS9: + ret = RTW_DATA_RATE_HE_NSS2_MCS9; + break; + case MGN_HE2SS_MCS10: + ret = RTW_DATA_RATE_HE_NSS2_MCS10; + break; + case MGN_HE2SS_MCS11: + ret = RTW_DATA_RATE_HE_NSS2_MCS11; + break; + case MGN_HE3SS_MCS0: + ret = RTW_DATA_RATE_HE_NSS3_MCS0; + break; + case MGN_HE3SS_MCS1: + ret = RTW_DATA_RATE_HE_NSS3_MCS1; + break; + case MGN_HE3SS_MCS2: + ret = RTW_DATA_RATE_HE_NSS3_MCS2; + break; + case MGN_HE3SS_MCS3: + ret = RTW_DATA_RATE_HE_NSS3_MCS3; + break; + case MGN_HE3SS_MCS4: + ret = RTW_DATA_RATE_HE_NSS3_MCS4; + break; + case MGN_HE3SS_MCS5: + ret = RTW_DATA_RATE_HE_NSS3_MCS5; + break; + case MGN_HE3SS_MCS6: + ret = RTW_DATA_RATE_HE_NSS3_MCS6; + break; + case MGN_HE3SS_MCS7: + ret = RTW_DATA_RATE_HE_NSS3_MCS7; + break; + case MGN_HE3SS_MCS8: + ret = RTW_DATA_RATE_HE_NSS3_MCS8; + break; + case MGN_HE3SS_MCS9: + ret = RTW_DATA_RATE_HE_NSS3_MCS9; + break; + case MGN_HE3SS_MCS10: + ret = RTW_DATA_RATE_HE_NSS3_MCS10; + break; + case MGN_HE3SS_MCS11: + ret = RTW_DATA_RATE_HE_NSS3_MCS11; + break; + case MGN_HE4SS_MCS0: + ret = RTW_DATA_RATE_HE_NSS4_MCS0; + break; + case MGN_HE4SS_MCS1: + ret = RTW_DATA_RATE_HE_NSS4_MCS1; + break; + case MGN_HE4SS_MCS2: + ret = RTW_DATA_RATE_HE_NSS4_MCS2; + break; + case MGN_HE4SS_MCS3: + ret = RTW_DATA_RATE_HE_NSS4_MCS3; + break; + case MGN_HE4SS_MCS4: + ret = RTW_DATA_RATE_HE_NSS4_MCS4; + break; + case MGN_HE4SS_MCS5: + ret = RTW_DATA_RATE_HE_NSS4_MCS5; + break; + case MGN_HE4SS_MCS6: + ret = RTW_DATA_RATE_HE_NSS4_MCS6; + break; + case MGN_HE4SS_MCS7: + ret = RTW_DATA_RATE_HE_NSS4_MCS7; + break; + case MGN_HE4SS_MCS8: + ret = RTW_DATA_RATE_HE_NSS4_MCS8; + break; + case MGN_HE4SS_MCS9: + ret = RTW_DATA_RATE_HE_NSS4_MCS9; + break; + case MGN_HE4SS_MCS10: + ret = RTW_DATA_RATE_HE_NSS4_MCS10; + break; + case MGN_HE4SS_MCS11: + ret = RTW_DATA_RATE_HE_NSS4_MCS11; + break; + default: + break; + } + + return ret; +} + +static inline u8 hwrate_to_mrate(u16 rate) +{ + u16 ret_rate = MGN_1M; + + switch (rate) { + + case RTW_DATA_RATE_CCK1: + ret_rate = MGN_1M; + break; + case RTW_DATA_RATE_CCK2: + ret_rate = MGN_2M; + break; + case RTW_DATA_RATE_CCK5_5: + ret_rate = MGN_5_5M; + break; + case RTW_DATA_RATE_CCK11: + ret_rate = MGN_11M; + break; + case RTW_DATA_RATE_OFDM6: + ret_rate = MGN_6M; + break; + case RTW_DATA_RATE_OFDM9: + ret_rate = MGN_9M; + break; + case RTW_DATA_RATE_OFDM12: + ret_rate = MGN_12M; + break; + case RTW_DATA_RATE_OFDM18: + ret_rate = MGN_18M; + break; + case RTW_DATA_RATE_OFDM24: + ret_rate = MGN_24M; + break; + case RTW_DATA_RATE_OFDM36: + ret_rate = MGN_36M; + break; + case RTW_DATA_RATE_OFDM48: + ret_rate = MGN_48M; + break; + case RTW_DATA_RATE_OFDM54: + ret_rate = MGN_54M; + break; + case RTW_DATA_RATE_MCS0: + ret_rate = MGN_MCS0; + break; + case RTW_DATA_RATE_MCS1: + ret_rate = MGN_MCS1; + break; + case RTW_DATA_RATE_MCS2: + ret_rate = MGN_MCS2; + break; + case RTW_DATA_RATE_MCS3: + ret_rate = MGN_MCS3; + break; + case RTW_DATA_RATE_MCS4: + ret_rate = MGN_MCS4; + break; + case RTW_DATA_RATE_MCS5: + ret_rate = MGN_MCS5; + break; + case RTW_DATA_RATE_MCS6: + ret_rate = MGN_MCS6; + break; + case RTW_DATA_RATE_MCS7: + ret_rate = MGN_MCS7; + break; + case RTW_DATA_RATE_MCS8: + ret_rate = MGN_MCS8; + break; + case RTW_DATA_RATE_MCS9: + ret_rate = MGN_MCS9; + break; + case RTW_DATA_RATE_MCS10: + ret_rate = MGN_MCS10; + break; + case RTW_DATA_RATE_MCS11: + ret_rate = MGN_MCS11; + break; + case RTW_DATA_RATE_MCS12: + ret_rate = MGN_MCS12; + break; + case RTW_DATA_RATE_MCS13: + ret_rate = MGN_MCS13; + break; + case RTW_DATA_RATE_MCS14: + ret_rate = MGN_MCS14; + break; + case RTW_DATA_RATE_MCS15: + ret_rate = MGN_MCS15; + break; + case RTW_DATA_RATE_MCS16: + ret_rate = MGN_MCS16; + break; + case RTW_DATA_RATE_MCS17: + ret_rate = MGN_MCS17; + break; + case RTW_DATA_RATE_MCS18: + ret_rate = MGN_MCS18; + break; + case RTW_DATA_RATE_MCS19: + ret_rate = MGN_MCS19; + break; + case RTW_DATA_RATE_MCS20: + ret_rate = MGN_MCS20; + break; + case RTW_DATA_RATE_MCS21: + ret_rate = MGN_MCS21; + break; + case RTW_DATA_RATE_MCS22: + ret_rate = MGN_MCS22; + break; + case RTW_DATA_RATE_MCS23: + ret_rate = MGN_MCS23; + break; + case RTW_DATA_RATE_MCS24: + ret_rate = MGN_MCS24; + break; + case RTW_DATA_RATE_MCS25: + ret_rate = MGN_MCS25; + break; + case RTW_DATA_RATE_MCS26: + ret_rate = MGN_MCS26; + break; + case RTW_DATA_RATE_MCS27: + ret_rate = MGN_MCS27; + break; + case RTW_DATA_RATE_MCS28: + ret_rate = MGN_MCS28; + break; + case RTW_DATA_RATE_MCS29: + ret_rate = MGN_MCS29; + break; + case RTW_DATA_RATE_MCS30: + ret_rate = MGN_MCS30; + break; + case RTW_DATA_RATE_MCS31: + ret_rate = MGN_MCS31; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS0: + ret_rate = MGN_VHT1SS_MCS0; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS1: + ret_rate = MGN_VHT1SS_MCS1; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS2: + ret_rate = MGN_VHT1SS_MCS2; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS3: + ret_rate = MGN_VHT1SS_MCS3; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS4: + ret_rate = MGN_VHT1SS_MCS4; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS5: + ret_rate = MGN_VHT1SS_MCS5; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS6: + ret_rate = MGN_VHT1SS_MCS6; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS7: + ret_rate = MGN_VHT1SS_MCS7; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS8: + ret_rate = MGN_VHT1SS_MCS8; + break; + case RTW_DATA_RATE_VHT_NSS1_MCS9: + ret_rate = MGN_VHT1SS_MCS9; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS0: + ret_rate = MGN_VHT2SS_MCS0; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS1: + ret_rate = MGN_VHT2SS_MCS1; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS2: + ret_rate = MGN_VHT2SS_MCS2; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS3: + ret_rate = MGN_VHT2SS_MCS3; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS4: + ret_rate = MGN_VHT2SS_MCS4; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS5: + ret_rate = MGN_VHT2SS_MCS5; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS6: + ret_rate = MGN_VHT2SS_MCS6; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS7: + ret_rate = MGN_VHT2SS_MCS7; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS8: + ret_rate = MGN_VHT2SS_MCS8; + break; + case RTW_DATA_RATE_VHT_NSS2_MCS9: + ret_rate = MGN_VHT2SS_MCS9; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS0: + ret_rate = MGN_VHT3SS_MCS0; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS1: + ret_rate = MGN_VHT3SS_MCS1; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS2: + ret_rate = MGN_VHT3SS_MCS2; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS3: + ret_rate = MGN_VHT3SS_MCS3; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS4: + ret_rate = MGN_VHT3SS_MCS4; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS5: + ret_rate = MGN_VHT3SS_MCS5; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS6: + ret_rate = MGN_VHT3SS_MCS6; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS7: + ret_rate = MGN_VHT3SS_MCS7; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS8: + ret_rate = MGN_VHT3SS_MCS8; + break; + case RTW_DATA_RATE_VHT_NSS3_MCS9: + ret_rate = MGN_VHT3SS_MCS9; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS0: + ret_rate = MGN_VHT4SS_MCS0; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS1: + ret_rate = MGN_VHT4SS_MCS1; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS2: + ret_rate = MGN_VHT4SS_MCS2; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS3: + ret_rate = MGN_VHT4SS_MCS3; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS4: + ret_rate = MGN_VHT4SS_MCS4; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS5: + ret_rate = MGN_VHT4SS_MCS5; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS6: + ret_rate = MGN_VHT4SS_MCS6; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS7: + ret_rate = MGN_VHT4SS_MCS7; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS8: + ret_rate = MGN_VHT4SS_MCS8; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS9: + ret_rate = MGN_VHT4SS_MCS9; + break; + case RTW_DATA_RATE_HE_NSS1_MCS0: + ret_rate = MGN_HE1SS_MCS0; + break; + case RTW_DATA_RATE_HE_NSS1_MCS1: + ret_rate = MGN_HE1SS_MCS1; + break; + case RTW_DATA_RATE_HE_NSS1_MCS2: + ret_rate = MGN_HE1SS_MCS2; + break; + case RTW_DATA_RATE_HE_NSS1_MCS3: + ret_rate = MGN_HE1SS_MCS3; + break; + case RTW_DATA_RATE_HE_NSS1_MCS4: + ret_rate = MGN_HE1SS_MCS4; + break; + case RTW_DATA_RATE_HE_NSS1_MCS5: + ret_rate = MGN_HE1SS_MCS5; + break; + case RTW_DATA_RATE_HE_NSS1_MCS6: + ret_rate = MGN_HE1SS_MCS6; + break; + case RTW_DATA_RATE_HE_NSS1_MCS7: + ret_rate = MGN_HE1SS_MCS7; + break; + case RTW_DATA_RATE_HE_NSS1_MCS8: + ret_rate = MGN_HE1SS_MCS8; + break; + case RTW_DATA_RATE_HE_NSS1_MCS9: + ret_rate = MGN_HE1SS_MCS9; + break; + case RTW_DATA_RATE_HE_NSS1_MCS10: + ret_rate = MGN_HE1SS_MCS10; + break; + case RTW_DATA_RATE_HE_NSS1_MCS11: + ret_rate = MGN_HE1SS_MCS11; + break; + case RTW_DATA_RATE_HE_NSS2_MCS0: + ret_rate = MGN_HE2SS_MCS0; + break; + case RTW_DATA_RATE_HE_NSS2_MCS1: + ret_rate = MGN_HE2SS_MCS1; + break; + case RTW_DATA_RATE_HE_NSS2_MCS2: + ret_rate = MGN_HE2SS_MCS2; + break; + case RTW_DATA_RATE_HE_NSS2_MCS3: + ret_rate = MGN_HE2SS_MCS3; + break; + case RTW_DATA_RATE_HE_NSS2_MCS4: + ret_rate = MGN_HE2SS_MCS4; + break; + case RTW_DATA_RATE_HE_NSS2_MCS5: + ret_rate = MGN_HE2SS_MCS5; + break; + case RTW_DATA_RATE_HE_NSS2_MCS6: + ret_rate = MGN_HE2SS_MCS6; + break; + case RTW_DATA_RATE_HE_NSS2_MCS7: + ret_rate = MGN_HE2SS_MCS7; + break; + case RTW_DATA_RATE_HE_NSS2_MCS8: + ret_rate = MGN_HE2SS_MCS8; + break; + case RTW_DATA_RATE_HE_NSS2_MCS9: + ret_rate = MGN_HE2SS_MCS9; + break; + case RTW_DATA_RATE_HE_NSS2_MCS10: + ret_rate = MGN_HE2SS_MCS10; + break; + case RTW_DATA_RATE_HE_NSS2_MCS11: + ret_rate = MGN_HE2SS_MCS11; + break; + case RTW_DATA_RATE_HE_NSS3_MCS0: + ret_rate = MGN_HE3SS_MCS0; + break; + case RTW_DATA_RATE_HE_NSS3_MCS1: + ret_rate = MGN_HE3SS_MCS1; + break; + case RTW_DATA_RATE_HE_NSS3_MCS2: + ret_rate = MGN_HE3SS_MCS2; + break; + case RTW_DATA_RATE_HE_NSS3_MCS3: + ret_rate = MGN_HE3SS_MCS3; + break; + case RTW_DATA_RATE_HE_NSS3_MCS4: + ret_rate = MGN_HE3SS_MCS4; + break; + case RTW_DATA_RATE_HE_NSS3_MCS5: + ret_rate = MGN_HE3SS_MCS5; + break; + case RTW_DATA_RATE_HE_NSS3_MCS6: + ret_rate = MGN_HE3SS_MCS6; + break; + case RTW_DATA_RATE_HE_NSS3_MCS7: + ret_rate = MGN_HE3SS_MCS7; + break; + case RTW_DATA_RATE_HE_NSS3_MCS8: + ret_rate = MGN_HE3SS_MCS8; + break; + case RTW_DATA_RATE_HE_NSS3_MCS9: + ret_rate = MGN_HE3SS_MCS9; + break; + case RTW_DATA_RATE_HE_NSS3_MCS10: + ret_rate = MGN_HE3SS_MCS10; + break; + case RTW_DATA_RATE_HE_NSS3_MCS11: + ret_rate = MGN_HE3SS_MCS11; + break; + case RTW_DATA_RATE_HE_NSS4_MCS0: + ret_rate = MGN_HE4SS_MCS0; + break; + case RTW_DATA_RATE_HE_NSS4_MCS1: + ret_rate = MGN_HE4SS_MCS1; + break; + case RTW_DATA_RATE_HE_NSS4_MCS2: + ret_rate = MGN_HE4SS_MCS2; + break; + case RTW_DATA_RATE_HE_NSS4_MCS3: + ret_rate = MGN_HE4SS_MCS3; + break; + case RTW_DATA_RATE_HE_NSS4_MCS4: + ret_rate = MGN_HE4SS_MCS4; + break; + case RTW_DATA_RATE_HE_NSS4_MCS5: + ret_rate = MGN_HE4SS_MCS5; + break; + case RTW_DATA_RATE_HE_NSS4_MCS6: + ret_rate = MGN_HE4SS_MCS6; + break; + case RTW_DATA_RATE_HE_NSS4_MCS7: + ret_rate = MGN_HE4SS_MCS7; + break; + case RTW_DATA_RATE_HE_NSS4_MCS8: + ret_rate = MGN_HE4SS_MCS8; + break; + case RTW_DATA_RATE_HE_NSS4_MCS9: + ret_rate = MGN_HE4SS_MCS9; + break; + case RTW_DATA_RATE_HE_NSS4_MCS10: + ret_rate = MGN_HE4SS_MCS10; + break; + case RTW_DATA_RATE_HE_NSS4_MCS11: + ret_rate = MGN_HE4SS_MCS11; + break; + + default: + break; + } + + return ret_rate; +} + +#endif /* __HAL_RATE_H__ */ diff --git a/include/autoconf.h b/include/autoconf.h index 993a028..3fb590f 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2017 Realtek Corporation. + * Copyright(c) 2015 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -13,36 +13,66 @@ * *****************************************************************************/ #define CONFIG_SINGLE_IMG -/* #define CONFIG_DISABLE_ODM */ +/***** temporarily flag *******/ +/*#define CONFIG_NO_FW*/ +/*#define CONFIG_DISABLE_ODM*/ + +#define RTW_WKARD_CORE_RSSI_V1 +#ifdef RTW_WKARD_CORE_RSSI_V1 +#define CONFIG_RX_PSTS_PER_PKT +#define CONFIG_SIGNAL_STAT_PROCESS +/*#define DBG_RX_SIGNAL_DISPLAY_PROCESSING*/ +#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "rtw_ap" +#endif + + +#ifndef DBG_MEM_ALLOC +#define DBG_MEM_ALLOC + +#define DBG_PHL_MEM_ALLOC +#define DBG_HAL_MAC_MEM_MOINTOR +#define DBG_HAL_MEM_MOINTOR +#endif +/*#define CONFIG_PHL_USE_KMEM_ALLOC*/ + +/* + * Work around Config + */ +#define RTW_WKARD_DIS_PROBE_REQ_RPT_TO_HOSTAPD /* * Public General Config */ #define AUTOCONF_INCLUDED -#define RTL871X_MODULE_NAME "88x2BU" -#define DRV_NAME "rtl88x2bu_ohd" +#define DRV_NAME "rtl8852bu" -/* Set CONFIG_RTL8822B from Makefile */ -#ifndef CONFIG_RTL8822B -#define CONFIG_RTL8822B -#endif -#define CONFIG_USB_HCI 1 -#define PLATFORM_LINUX 1 +#define CONFIG_USB_HCI /* * Wi-Fi Functions Config */ + #define CONFIG_80211N_HT #define CONFIG_80211AC_VHT +#define CONFIG_80211AX_HE #ifdef CONFIG_80211AC_VHT #ifndef CONFIG_80211N_HT #define CONFIG_80211N_HT #endif #endif +#ifdef CONFIG_80211AX_HE + #ifndef CONFIG_80211N_HT + #define CONFIG_80211N_HT + #endif + #ifndef CONFIG_80211AC_VHT + #define CONFIG_80211AC_VHT + #endif +#endif -#ifdef CONFIG_80211AC_VHT - #define CONFIG_BEAMFORMING +#define CONFIG_BEAMFORMING +#ifdef CONFIG_BEAMFORMING +/*#define RTW_WKARD_TX_DISABLE_BFEE*/ #endif /* set CONFIG_IOCTL_CFG80211 from Makefile */ @@ -57,46 +87,46 @@ /* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */ #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER /* #define CONFIG_DEBUG_CFG80211 */ - /* #define CONFIG_DRV_ISSUE_PROV_REQ */ /* IOT FOR S2 */ #define CONFIG_SET_SCAN_DENY_TIMER #endif +/* #define CONFIG_TX_AMSDU */ +#ifdef CONFIG_TX_AMSDU + #define CONFIG_TX_AMSDU_SW_MODE 1 +#endif + +#define CONFIG_HW_RTS + /* * Internal General Config */ -/* #define CONFIG_H2CLBK */ - -#define RTW_HALMAC /* Use HALMAC architecture, necessary for 8822B */ -#define CONFIG_EMBEDDED_FWIMG 1 -#if (CONFIG_EMBEDDED_FWIMG==1) +#define CONFIG_EMBEDDED_FWIMG +#ifdef CONFIG_EMBEDDED_FWIMG #define LOAD_FW_HEADER_FROM_DRIVER #endif /* #define CONFIG_FILE_FWIMG */ -#define CONFIG_XMIT_ACK +/*#define CONFIG_XMIT_ACK*/ #ifdef CONFIG_XMIT_ACK #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK #endif -#define CONFIG_RECV_REORDERING_CTRL 1 +/*#define CONFIG_RECV_REORDERING_CTRL*/ + +#define CONFIG_USB_INTERRUPT_IN_PIPE -/* #define CONFIG_SUPPORT_USB_INT */ -#ifdef CONFIG_SUPPORT_USB_INT - /* #define CONFIG_USB_INTERRUPT_IN_PIPE 1 */ -#endif /* CONFIG_SUPPORT_USB_INT */ +/* #define CONFIG_SIGNAL_STAT_PROCESS */ #ifdef CONFIG_POWER_SAVING - #define CONFIG_IPS 1 + #define CONFIG_IPS #ifdef CONFIG_IPS - /* #define CONFIG_IPS_LEVEL_2 1*/ /*enable this to set default IPS mode to IPS_LEVEL_2*/ #define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */ /* #define CONFIG_FWLPS_IN_IPS */ #endif - /* #define SUPPORT_HW_RFOFF_DETECTED 1 */ - #define CONFIG_LPS 1 + #define CONFIG_LPS #if defined(CONFIG_LPS) - #define CONFIG_LPS_LCLK 1 + #define CONFIG_LPS_LCLK #endif #ifdef CONFIG_LPS_LCLK @@ -111,9 +141,27 @@ #endif /* CONFIG_LPS_LCLK */ #ifdef CONFIG_LPS - #define CONFIG_WMMPS_STA 1 + /*#define CONFIG_WMMPS_STA*/ #endif /* CONFIG_LPS */ + #endif /*CONFIG_POWER_SAVING*/ + +#ifdef CONFIG_POWER_SAVE + /*#define CONFIG_RTW_IPS*/ + /*#define CONFIG_RTW_LPS*/ +#endif + +#ifdef CONFIG_WOWLAN + #define CONFIG_GTK_OL + /* #define CONFIG_ARP_KEEP_ALIVE */ +#endif /* CONFIG_WOWLAN */ + +#ifdef CONFIG_GPIO_WAKEUP + #ifndef WAKEUP_GPIO_IDX + #define WAKEUP_GPIO_IDX 10 /* WIFI Chip Side */ + #endif /*!WAKEUP_GPIO_IDX*/ +#endif /* CONFIG_GPIO_WAKEUP */ + /* before link */ /* #define CONFIG_ANTENNA_DIVERSITY */ @@ -127,6 +175,7 @@ /*#endif*/ /* CONFIG_MP_INCLUDED */ +#define CONFIG_AP_MODE #ifdef CONFIG_AP_MODE /* #define CONFIG_INTERRUPT_BASED_TXBCN */ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) @@ -139,11 +188,12 @@ #define CONFIG_NATIVEAP_MLME #ifndef CONFIG_NATIVEAP_MLME - #define CONFIG_HOSTAPD_MLME 1 + #define CONFIG_HOSTAPD_MLME #endif - #define CONFIG_FIND_BEST_CHANNEL 1 + /*#define CONFIG_FIND_BEST_CHANNEL*/ #endif +#define CONFIG_P2P #ifdef CONFIG_P2P /* The CONFIG_WFD is for supporting the Wi-Fi display */ #define CONFIG_WFD @@ -173,9 +223,9 @@ #endif -#define CONFIG_SKB_COPY 1 /* amsdu */ +#define CONFIG_SKB_COPY /* amsdu */ -#define CONFIG_RTW_LED +/*#define CONFIG_RTW_LED*/ #ifdef CONFIG_RTW_LED #define CONFIG_RTW_SW_LED #ifdef CONFIG_RTW_SW_LED @@ -183,7 +233,6 @@ #endif #endif /* CONFIG_RTW_LED */ -#define USB_INTERFERENCE_ISSUE /* this should be checked in all usb interface */ #define CONFIG_GLOBAL_UI_PID /*#define CONFIG_RTW_80211K*/ @@ -192,39 +241,33 @@ /*#define CONFIG_RESUME_IN_WORKQUEUE */ /*#define CONFIG_SET_SCAN_DENY_TIMER */ #define CONFIG_LONG_DELAY_ISSUE -#define CONFIG_NEW_SIGNAL_STAT_PROCESS /* #define CONFIG_SIGNAL_DISPLAY_DBM */ /*display RX signal with dbm */ #ifdef CONFIG_SIGNAL_DISPLAY_DBM /* #define CONFIG_BACKGROUND_NOISE_MONITOR */ #endif -#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */ -#define RTW_FORCE_CTS_TO_SELF_UNDER_LOW_RSSI + + /* * Interface Related Config */ #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #define CONFIG_USB_TX_AGGREGATION 1 - #define CONFIG_USB_RX_AGGREGATION 1 + #define CONFIG_USB_TX_AGGREGATION + #define CONFIG_USB_RX_AGGREGATION +#endif + +#ifndef CONFIG_DYNAMIC_RX_BUF +#define CONFIG_DYNAMIC_RX_BUF #endif -/* #define CONFIG_REDUCE_USB_TX_INT 1 */ /* Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. */ -/* #define CONFIG_EASY_REPLACEMENT 1 */ +/* #define CONFIG_REDUCE_USB_TX_INT*/ /* Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. */ /* * CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now! */ -/* #define CONFIG_USE_USB_BUFFER_ALLOC_TX 1 */ /* Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. */ -/* #define CONFIG_USE_USB_BUFFER_ALLOC_RX 1 */ /* For RX path */ -#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX - -#else - #define CONFIG_PREALLOC_RECV_SKB - #ifdef CONFIG_PREALLOC_RECV_SKB - /* #define CONFIG_FIX_NR_BULKIN_BUFFER */ /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */ - #endif -#endif +/* #define CONFIG_USE_USB_BUFFER_ALLOC_TX*/ /* Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. */ +/* #define CONFIG_USE_USB_BUFFER_ALLOC_RX*/ /* For RX path */ /* * USB VENDOR REQ BUFFER ALLOCATION METHOD @@ -236,30 +279,23 @@ #define CONFIG_USB_VENDOR_REQ_MUTEX #define CONFIG_VENDOR_REQ_RETRY -/* #define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ 1 */ +/* #define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ*/ /* - * HAL Related Config + * If bus rate is lower than Wi-Fi phy rate, it probably causes unstable + * throughput for rx. So disable AMSDU may be suggested by SD1. */ -#define RTL8812A_RX_PACKET_INCLUDE_CRC 0 +/* #define CONFIG_DISBALE_RX_AMSDU_FOR_BUS_LOW_SPEED */ +/* + * HAL Related Config + */ #define CONFIG_RX_PACKET_APPEND_FCS -/* #define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0 */ - -#define CONFIG_OUT_EP_WIFI_MODE 0 - -#define ENABLE_USB_DROP_INCORRECT_OUT - -#define CONFIG_ADHOC_WORKAROUND_SETTING 1 - -#define ENABLE_NEW_RFE_TYPE 0 - #define DISABLE_BB_RF 0 #ifdef CONFIG_MP_INCLUDED #define MP_DRIVER 1 - #define CONFIG_MP_IWPRIV_SUPPORT 1 /* #undef CONFIG_USB_TX_AGGREGATION #undef CONFIG_USB_RX_AGGREGATION @@ -283,28 +319,25 @@ #endif #endif -#ifdef CONFIG_BT_COEXIST - /* for ODM and outsrc BT-Coex */ - #ifndef CONFIG_LPS - #define CONFIG_LPS /* download reserved page to FW */ - #endif -#endif /* !CONFIG_BT_COEXIST */ - - - #ifdef CONFIG_USB_TX_AGGREGATION /* #define CONFIG_TX_EARLY_MODE */ #endif -#define RTL8188E_EARLY_MODE_PKT_NUM_10 0 -/*#define CONFIG_CUSTOMER01_SMART_ANTENNA */ +#define MAX_XMITBUF_SZ 20480 +#define NR_XMITBUFF 4 +#define MAX_MGNT_XMITBUF_SZ 1536 +#define NR_MGNT_XMITBUFF 32 +#define MAX_RECVBUF_SZ 32768 +#define NR_RECVBUFF 128 +#define NR_RECV_URB 8 /* * Debug Related Config */ +#define RTW_DETECT_HANG #define DBG 1 -#define DBG_CONFIG_ERROR_DETECT +/*#define DBG_CONFIG_ERROR_DETECT*/ /* #define CONFIG_DIS_UPHY */ /* @@ -327,13 +360,11 @@ #define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap" - -#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE #define DBG_ROAMING_TEST #define DBG_HAL_INIT_PROFILING -#define DBG_MEMORY_LEAK 1 +#define DBG_MEMORY_LEAK */ /*#define DBG_FW_DEBUG_MSG_PKT*/ /* FW use this feature to tx debug broadcast pkt. This pkt include FW debug message*/ diff --git a/include/basic_types.h b/include/basic_types.h index 45e5131..90f4217 100644 --- a/include/basic_types.h +++ b/include/basic_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -31,44 +31,6 @@ #define _FALSE FALSE #endif -#ifdef PLATFORM_WINDOWS - - typedef signed char s8; - typedef unsigned char u8; - - typedef signed short s16; - typedef unsigned short u16; - - typedef signed long s32; - typedef unsigned long u32; - - typedef unsigned int uint; - typedef signed int sint; - - - typedef signed long long s64; - typedef unsigned long long u64; - - #ifdef NDIS50_MINIPORT - - #define NDIS_MAJOR_VERSION 5 - #define NDIS_MINOR_VERSION 0 - - #endif - - #ifdef NDIS51_MINIPORT - - #define NDIS_MAJOR_VERSION 5 - #define NDIS_MINOR_VERSION 1 - - #endif - - typedef NDIS_PROC proc_t; - - typedef LONG atomic_t; - -#endif - #ifdef PLATFORM_LINUX #include @@ -95,7 +57,6 @@ enum { typedef __kernel_ssize_t SSIZE_T; #define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field) -#define NDIS_OID uint #endif /*PLATFORM_LINUX*/ @@ -112,12 +73,12 @@ enum { typedef unsigned int uint; typedef signed int sint; - typedef long atomic_t; typedef signed long long s64; typedef unsigned long long u64; typedef u32 dma_addr_t; + typedef long atomic_t; typedef void (*proc_t)(void *); @@ -345,9 +306,21 @@ enum { /* Get the N-bytes aligment offset from the current length */ #define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) +#define N_BYTE_ALIGNMENT(__Value, __Alignment) ((__Alignment == 1)\ +? (__Value) : (((__Value + __Alignment - 1) / __Alignment) * __Alignment)) typedef unsigned char BOOLEAN, *PBOOLEAN, boolean; +#define _FAIL 0 +#define _SUCCESS 1 + +#undef _TRUE +#define _TRUE 1 + +#undef _FALSE +#define _FALSE 0 + + #define TEST_FLAG(__Flag, __testFlag) (((__Flag) & (__testFlag)) != 0) #define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) #define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) diff --git a/include/byteorder/big_endian.h b/include/byteorder/big_endian.h index 6b1dc44..d2336a5 100644 --- a/include/byteorder/big_endian.h +++ b/include/byteorder/big_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/byteorder/generic.h b/include/byteorder/generic.h index f85114b..35d0737 100644 --- a/include/byteorder/generic.h +++ b/include/byteorder/generic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -93,7 +93,7 @@ */ -#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) +#if defined(PLATFORM_LINUX) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) /* * inside the kernel, we can use nicknames; * outside of it, we must avoid POSIX namespace pollution... @@ -164,15 +164,11 @@ extern __u32 ntohl(__u32); extern __u32 htonl(__u32); #else /* defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) */ - #ifndef PLATFORM_FREEBSD - extern unsigned long int ntohl(unsigned long int); - extern unsigned long int htonl(unsigned long int); - #endif + extern unsigned long int ntohl(unsigned long int); + extern unsigned long int htonl(unsigned long int); #endif -#ifndef PLATFORM_FREEBSD extern unsigned short int ntohs(unsigned short int); extern unsigned short int htons(unsigned short int); -#endif #if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) @@ -192,16 +188,4 @@ #define ntohs(x) ___ntohs(x) #endif /* OPTIMIZE */ - - -#if defined(PLATFORM_WINDOWS) - - #define htonl(x) __cpu_to_be32(x) - #define ntohl(x) __be32_to_cpu(x) - #define htons(x) __cpu_to_be16(x) - #define ntohs(x) __be16_to_cpu(x) - - -#endif - #endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/include/byteorder/little_endian.h b/include/byteorder/little_endian.h index c4b6451..a08e8d7 100644 --- a/include/byteorder/little_endian.h +++ b/include/byteorder/little_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/byteorder/swab.h b/include/byteorder/swab.h index a8dd46b..ee97520 100644 --- a/include/byteorder/swab.h +++ b/include/byteorder/swab.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -121,7 +121,7 @@ __inline static __u64 __arch__swab64(__u64 x) return __arch__swab32(x); } -#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) +#if defined(PLATFORM_LINUX) #define swab16 __swab16 #define swab32 __swab32 #define swab64 __swab64 diff --git a/include/byteorder/swabb.h b/include/byteorder/swabb.h index 634519a..6be7617 100644 --- a/include/byteorder/swabb.h +++ b/include/byteorder/swabb.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/circ_buf.h b/include/circ_buf.h index 7a5b8ef..8d83cb8 100644 --- a/include/circ_buf.h +++ b/include/circ_buf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/drv_conf.h b/include/drv_conf.h index d53c1be..7a6db45 100644 --- a/include/drv_conf.h +++ b/include/drv_conf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,11 +15,10 @@ #ifndef __DRV_CONF_H__ #define __DRV_CONF_H__ #include "autoconf.h" -#include "hal_ic_cfg.h" #define CONFIG_RSSI_PRIORITY -/* +/* * RTW_BUSY_DENY_SCAN control if scan would be denied by busy traffic. * When this defined, BUSY_TRAFFIC_SCAN_DENY_PERIOD would be used to judge if * scan request coming from scan UI. Scan request from scan UI would be @@ -27,34 +26,13 @@ */ #define RTW_BUSY_DENY_SCAN -#ifdef CONFIG_RTW_REPEATER_SON - #ifndef CONFIG_AP - #define CONFIG_AP - #endif - #ifndef CONFIG_CONCURRENT_MODE - #define CONFIG_CONCURRENT_MODE - #endif - #ifndef CONFIG_BR_EXT - #define CONFIG_BR_EXT - #endif - #ifndef CONFIG_RTW_REPEATER_SON_ID - #define CONFIG_RTW_REPEATER_SON_ID 0x02040608 - #endif - //#define CONFIG_RTW_REPEATER_SON_ROOT - #ifndef CONFIG_RTW_REPEATER_SON_ROOT - #undef CONFIG_ROAMING_FLAG - #define CONFIG_ROAMING_FLAG 0x7 - #endif - #undef CONFIG_POWER_SAVING -#endif - #if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE)) #error "Enable CONCURRENT_MODE before enable MCC MODE\n" #endif -#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST) +#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BTC) #error "Disable BT COEXIST before enable MCC MODE\n" @@ -72,14 +50,6 @@ #endif -#ifdef CONFIG_LAYER2_ROAMING -/*#define CONFIG_RTW_ROAM_QUICKSCAN */ /* active_roaming is required. i.e CONFIG_ROAMING_FLAG[bit2] MUST be enabled */ -/*#define CONFIG_RTW_ROAM_QUICKSCAN_TH 60*/ -#endif - -/* Default enable single wiphy if driver ver >= 5.9 */ -#define RTW_SINGLE_WIPHY - #ifdef CONFIG_RTW_ANDROID #include @@ -98,12 +68,6 @@ #endif #endif - #if (CONFIG_RTW_ANDROID <= 7) - #ifdef RTW_SINGLE_WIPHY - #undef RTW_SINGLE_WIPHY - #endif - #endif - #if (CONFIG_RTW_ANDROID >= 8) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0)) #ifndef CONFIG_RTW_WIFI_HAL @@ -118,18 +82,14 @@ #ifndef CONFIG_RTW_WIFI_HAL_DEBUG //#define CONFIG_RTW_WIFI_HAL_DEBUG #endif + #if (CONFIG_RTW_ANDROID < 11) #ifndef CONFIG_RTW_CFGVENDOR_LLSTATS #define CONFIG_RTW_CFGVENDOR_LLSTATS #endif - #if (CONFIG_RTW_ANDROID < 11) + #endif #ifndef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI #define CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI #endif - #else - #ifndef CONFIG_RTW_SCAN_RAND - #define CONFIG_RTW_SCAN_RAND - #endif - #endif #ifndef CONFIG_RTW_CFGVENDOR_RSSIMONITOR #define CONFIG_RTW_CFGVENDOR_RSSIMONITOR #endif @@ -140,15 +100,9 @@ #ifndef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD //#define CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD #endif - #ifndef CONFIG_RTW_HOSTAPD_ACS - #define CONFIG_RTW_HOSTAPD_ACS - #endif #ifndef CONFIG_KERNEL_PATCH_EXTERNAL_AUTH #define CONFIG_KERNEL_PATCH_EXTERNAL_AUTH #endif - #ifndef CONFIG_RTW_ABORT_SCAN - #define CONFIG_RTW_ABORT_SCAN - #endif #endif #endif // CONFIG_RTW_WIFI_HAL @@ -193,25 +147,19 @@ #endif #ifdef CONFIG_WIFI_MONITOR - #define CONFIG_MONITOR_MODE_XMIT + /* #define CONFIG_MONITOR_MODE_XMIT */ #endif #ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL #ifndef CONFIG_WIFI_MONITOR #define CONFIG_WIFI_MONITOR #endif - #ifdef CONFIG_POWER_SAVING - #undef CONFIG_POWER_SAVING + #ifndef CONFIG_MONITOR_MODE_XMIT + #define CONFIG_MONITOR_MODE_XMIT #endif -#endif - -#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA #ifdef CONFIG_POWER_SAVING #undef CONFIG_POWER_SAVING #endif - #ifdef CONFIG_BEAMFORMING - #undef CONFIG_BEAMFORMING - #endif #endif #ifndef CONFIG_RTW_DATA_BMC_TO_UC @@ -220,6 +168,7 @@ #ifdef CONFIG_AP_MODE #define CONFIG_LIMITED_AP_NUM 1 + #define BMC_ON_HIQ #ifndef CONFIG_RTW_AP_DATA_BMC_TO_UC #define CONFIG_RTW_AP_DATA_BMC_TO_UC 1 @@ -308,22 +257,6 @@ #define RTW_SCAN_SPARSE_MIRACAST 1 #define RTW_SCAN_SPARSE_BG 0 -#ifndef CONFIG_TX_AC_LIFETIME -#define CONFIG_TX_AC_LIFETIME 1 -#endif -#ifndef CONFIG_TX_ACLT_FLAGS -#define CONFIG_TX_ACLT_FLAGS 0x00 -#endif -#ifndef CONFIG_TX_ACLT_CONF_DEFAULT -#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000} -#endif -#ifndef CONFIG_TX_ACLT_CONF_AP_M2U -#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000} -#endif -#ifndef CONFIG_TX_ACLT_CONF_MESH -#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000} -#endif - #ifndef CONFIG_RTW_HIQ_FILTER #define CONFIG_RTW_HIQ_FILTER 1 #endif @@ -348,20 +281,35 @@ #define CONFIG_RTW_EXCL_CHS {0} #endif -#ifndef CONFIG_IEEE80211_BAND_5GHZ - #if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8821C) \ - || defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \ - || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F) - #define CONFIG_IEEE80211_BAND_5GHZ 1 - #else - #define CONFIG_IEEE80211_BAND_5GHZ 0 - #endif +#ifndef CONFIG_RTW_EXCL_CHS_6G + #define CONFIG_RTW_EXCL_CHS_6G {0} +#endif + +#ifndef CONFIG_RTW_COUNTRY_IE_SLAVE_EN_ROLE +#define CONFIG_RTW_COUNTRY_IE_SLAVE_EN_ROLE 0x03 /* BIT0 for pure STA mode, BIT1 for P2P group client */ +#endif + +#ifndef CONFIG_RTW_COUNTRY_IE_SLAVE_EN_IFBMP +#define CONFIG_RTW_COUNTRY_IE_SLAVE_EN_IFBMP 0xFF /* all iface */ +#endif + +#define CONFIG_IEEE80211_BAND_5GHZ 1 + +#ifndef CONFIG_IEEE80211_BAND_6GHZ +#define CONFIG_IEEE80211_BAND_6GHZ 0 #endif #ifndef CONFIG_DFS #define CONFIG_DFS 1 #endif +#if CONFIG_DFS +#define CONFIG_ECSA_PHL /* Process ECSA by PHL cmd dispatcher */ +#ifdef CONFIG_ECSA_PHL + #define CONFIG_ECSA +#endif +#endif + #if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS && defined(CONFIG_AP_MODE) #if !defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) #define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0 @@ -388,7 +336,11 @@ #endif #ifndef CONFIG_RTW_CHPLAN -#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */ +#define CONFIG_RTW_CHPLAN 0xFFFF /* RTW_CHPLAN_IOCTL_UNSPECIFIED */ +#endif + +#ifndef CONFIG_RTW_CHPLAN_6G +#define CONFIG_RTW_CHPLAN_6G 0xFFFF /* RTW_CHPLAN_IOCTL_UNSPECIFIED */ #endif /* compatible with old fashion configuration */ @@ -428,20 +380,14 @@ #define CONFIG_RTW_REGD_SRC 1 /* 0:RTK_PRIV, 1:OS */ #endif -#define CONFIG_IOCTL_WEXT - #ifdef CONFIG_RTW_IPCAM_APPLICATION #undef CONFIG_TXPWR_BY_RATE_EN #define CONFIG_TXPWR_BY_RATE_EN 1 #define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C #define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00 - #define CONFIG_RTW_CUSTOMIZE_RLSTA 0x30 - #define CONFIG_CHECK_SPECIFIC_IE_CONTENT - #ifdef CONFIG_CUSTOMER_EZVIZ_CHIME2 - #undef CONFIG_ACTIVE_KEEP_ALIVE_CHECK - #endif -#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) - #define CONFIG_RTW_TX_NPATH_EN /* mutually incompatible with STBC_TX & Beamformer */ + #define CONFIG_RTW_CUSTOMIZE_RLSTA 0x7 +#if defined(CONFIG_RTL8822B) + #define CONFIG_RTW_TX_NPATH_EN /*mutually incompatible with STBC_TX & Beamformer */ #endif #endif /* #define CONFIG_RTW_TOKEN_BASED_XMIT */ @@ -500,10 +446,6 @@ #define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1} #endif -#ifndef CONFIG_RTW_ANTENNA_GAIN -#define CONFIG_RTW_ANTENNA_GAIN 0x7FFF /* == UNSPECIFIED_MBM */ -#endif - #ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G #define CONFIG_RTW_AMPLIFIER_TYPE_2G 0 #endif @@ -513,7 +455,7 @@ #endif #ifndef CONFIG_RTW_RFE_TYPE - #define CONFIG_RTW_RFE_TYPE 64 + #define CONFIG_RTW_RFE_TYPE 0xFF #endif #ifndef CONFIG_RTW_GLNA_TYPE @@ -532,7 +474,11 @@ #endif #endif -#ifndef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_CONCURRENT_MODE + #if (CONFIG_IFACE_NUMBER < 2) + #error "CONFIG_IFACE_NUMBER less 2,but CONFIG_CONCURRENT_MODE defined" + #endif +#else #if (CONFIG_IFACE_NUMBER > 1) #error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined" #endif @@ -542,32 +488,6 @@ #error "CONFIG_IFACE_NUMBER cound not be 0 !!" #endif -#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \ -defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \ -defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \ -defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) -#define CONFIG_HWMPCAP_GEN1 -#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || \ -defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ -#define CONFIG_HWMPCAP_GEN2 -#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/ -#define CONFIG_HWMPCAP_GEN3 -#endif - -#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2) - #ifdef CONFIG_POWER_SAVING - /*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/ - #undef CONFIG_POWER_SAVING - #endif - - #ifdef CONFIG_WOWLAN - #error "This IC can't support MI and WoWLan at the same time" - #endif -#endif - -#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 3) - #error " This IC can't support over 3 interfaces !!" -#endif #if (CONFIG_IFACE_NUMBER > 4) #error "Not support over 4 interfaces yet !!" @@ -578,99 +498,29 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ #endif #if (CONFIG_IFACE_NUMBER > 2) - #ifndef CONFIG_HWMPCAP_GEN3 - #define CONFIG_MI_WITH_MBSSID_CAM - #endif - - #ifdef CONFIG_MI_WITH_MBSSID_CAM - #define CONFIG_MBSSID_CAM - #if defined(CONFIG_RUNTIME_PORT_SWITCH) - #undef CONFIG_RUNTIME_PORT_SWITCH - #endif - #endif - #ifdef CONFIG_AP_MODE #undef CONFIG_LIMITED_AP_NUM #define CONFIG_LIMITED_AP_NUM 2 - - #define CONFIG_SUPPORT_MULTI_BCN - - #define CONFIG_SWTIMER_BASED_TXBCN - - #ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/ - #define CONFIG_FW_HANDLE_TXBCN - - #ifdef CONFIG_FW_HANDLE_TXBCN - #ifdef CONFIG_SWTIMER_BASED_TXBCN - #undef CONFIG_SWTIMER_BASED_TXBCN - #endif - #undef CONFIG_LIMITED_AP_NUM - #define CONFIG_LIMITED_AP_NUM 4 - #endif - - #endif /*CONFIG_HWMPCAP_GEN2*/ - - #ifdef CONFIG_HWMPCAP_GEN3 - #define CONFIG_PORT_BASED_TXBCN - #undef CONFIG_SUPPORT_MULTI_BCN - #undef CONFIG_SWTIMER_BASED_TXBCN - #undef CONFIG_LIMITED_AP_NUM - #define CONFIG_LIMITED_AP_NUM 4 - #ifdef CONFIG_PCI_HCI - #define CONFIG_PORT_BASED_HIQ /* 8814BU doesn't support */ - #endif - #endif #endif /*CONFIG_AP_MODE*/ - #ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/ - #define CONFIG_CLIENT_PORT_CFG - #define CONFIG_NEW_NETDEV_HDL - #endif/*CONFIG_HWMPCAP_GEN2*/ #endif/*(CONFIG_IFACE_NUMBER > 2)*/ -#if defined(CONFIG_MI_UNIQUE_MACADDR_BIT) - #if !defined(CONFIG_MI_WITH_MBSSID_CAM) - #error "CONFIG_MI_UNIQUE_MACADDR_BIT should not be used without multiple interface !!" - #endif - #if (CONFIG_MI_UNIQUE_MACADDR_BIT < 24) || ( 47 < CONFIG_MI_UNIQUE_MACADDR_BIT) - #error "CONFIG_MI_UNIQUE_MACADDR_BIT should be the bit in NIC specific mac address(BIT[24:47] !!" - #endif -#endif - #define MACID_NUM_SW_LIMIT 32 #define SEC_CAM_ENT_NUM_SW_LIMIT 32 -#ifdef SEC_DEFAULT_KEY_SEARCH - #if (CONFIG_IFACE_NUMBER >= 2) - #error "Default Key Search only work with only one interface case!" - #endif -#endif - -#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)) - #define CONFIG_WOW_PATTERN_HW_CAM -#endif - -#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR -#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200 -#endif - -#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR -#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5 -#endif /* - Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20 - If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle, - power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP. +Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20 +If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle, +power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP. */ /*#define CONFIG_DEAUTH_BEFORE_CONNECT */ /*#define CONFIG_WEXT_DONT_JOIN_BYSSID */ -/* #include */ +/* #include */ /*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */ -/*#define CONFIG_PHDYM_FW_FIXRATE */ /* Another way to fix tx rate */ /*Don't release SDIO irq in suspend/resume procedure*/ #define CONFIG_RTW_SDIO_KEEP_IRQ 0 @@ -684,16 +534,14 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ #endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */ #ifdef CONFIG_RTW_HOSTAPD_ACS + #ifdef CONFIG_FIND_BEST_CHANNEL + #undef CONFIG_FIND_BEST_CHANNEL + #endif #ifndef CONFIG_RTW_ACS #define CONFIG_RTW_ACS #endif #endif -#ifdef CONFIG_RTW_80211K - #ifndef CONFIG_RTW_ACS - #define CONFIG_RTW_ACS - #endif -#endif /*CONFIG_RTW_80211K*/ #ifdef DBG_CONFIG_ERROR_RESET #ifndef CONFIG_IPS @@ -716,7 +564,7 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ /* LPS */ #ifndef RTW_LPS_MODE - #if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA) + #if defined(CONFIG_LPS_PG) #define RTW_LPS_MODE 3 #elif defined(CONFIG_LPS_LCLK) #define RTW_LPS_MODE 2 @@ -741,7 +589,7 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ /* WOW LPS */ #ifndef RTW_WOW_LPS_MODE - #if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA) + #if defined(CONFIG_LPS_PG) #define RTW_WOW_LPS_MODE 3 #elif defined(CONFIG_LPS_LCLK) #define RTW_WOW_LPS_MODE 2 @@ -765,31 +613,10 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ #endif #endif -#ifdef CONFIG_WAR_OFFLOAD -#ifndef CONFIG_WOWLAN - #error "WAR OFFLOAD is part of WOWLAN" -#endif -#endif - -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) -#ifndef CONFIG_WOWLAN - #error "mDNS OFFLOAD is part of WOWLAN" -#endif -#ifndef CONFIG_WAR_OFFLOAD - #define CONFIG_WAR_OFFLOAD -#endif -#endif - -#define CONFIG_RTW_TPT_MODE - #ifdef CONFIG_PCI_BCN_POLLING #define CONFIG_BCN_ICF #endif -#ifndef CONFIG_RTW_MGMT_QUEUE - #define CONFIG_RTW_MGMT_QUEUE -#endif - #ifndef CONFIG_PCI_MSI #define CONFIG_RTW_PCI_MSI_DISABLE #endif @@ -805,4 +632,53 @@ defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/ #define DBG_CPU_INFO /* Add CPU info to debug message prefix */ #endif +#ifdef CONFIG_TX_AMSDU_HW_MODE +#define CONFIG_HW_HDR_CONVERSION +#elif defined(CONFIG_TX_AMSDU_SW_MODE) +#else +#define CONFIG_HW_HDR_CONVERSION /* TODO: should be 'unchange' */ +#endif + +/* for phl illegal mac io access check*/ +#define CONFIG_MAC_REG_RW_CHK + +#ifdef CONFIG_CMD_DISP + /*#define DBG_CONFIG_CMD_DISP*/ + + #define CONFIG_CMD_SCAN + #ifdef CONFIG_CMD_SCAN + #ifdef CONFIG_IOCTL_CFG80211 + #define CONFIG_PHL_CMD_SCAN_BKOP_TIME + #endif + /* Scan hidden AP in passive channel */ + #define RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + #define RTW_EXTEND_ACTIVE_SCAN_PERIOD 30 /* unit: ms */ + #endif /* CONFIG_CMD_SCAN */ + + #define CONFIG_CMD_GENERAL + #define CONFIG_CMD_SER + #define CONFIG_STA_CMD_DISPR + #define CONFIG_AP_CMD_DISPR + /*#define CONFIG_IBSS_CMD_DISPR*/ + #define CONFIG_CMD_TSF_SYNC +#endif + +#ifdef ROKU_PRIVATE + #define CONFIG_USB_RELEASE_RPT + #define CONFIG_RA_TXSTS_DBG +#endif + +#ifdef CONFIG_80211AX_HE + #define CONFIG_STA_MULTIPLE_BSSID +#endif + +/* + * Work around Config + */ +/* + * RTW_WKARD_UPDATE_PHL_ROLE_CAP + * Update adapter->phl_role.cap & proto_role_cap by driver parameters(registry). + */ +#define RTW_WKARD_UPDATE_PHL_ROLE_CAP + #endif /* __DRV_CONF_H__ */ diff --git a/include/drv_types.h b/include/drv_types.h index 5d729fd..53bce5f 100644 --- a/include/drv_types.h +++ b/include/drv_types.h @@ -17,8 +17,6 @@ For type defines and data structure defines --------------------------------------------------------------------------------*/ - - #ifndef __DRV_TYPES_H__ #define __DRV_TYPES_H__ @@ -34,31 +32,11 @@ #include #endif -#ifdef PLATFORM_OS_XP - #include -#endif - -#ifdef PLATFORM_OS_CE - #include -#endif - -#ifdef PLATFORM_LINUX - #include -#endif - -enum _NIC_VERSION { - - RTL8711_NIC, - RTL8712_NIC, - RTL8713_NIC, - RTL8716_NIC - -}; - -typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; +typedef struct _ADAPTER _adapter; +/* connection interface of drv and hal */ +#include "../phl/rtw_general_def.h" #include -#include #include #include "../core/rtw_chplan.h" @@ -70,28 +48,37 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #endif -#include -#include + #include #include #include #include #include +#ifdef CONFIG_80211AX_HE + #include +#endif + #ifdef CONFIG_BEAMFORMING #include #endif #include -#include #include -#include -#include -#include -#include -#include "../hal/hal_dm.h" -#include -#include + +/*CONFIG_PHL_ARCH*/ +#include "rtw_cmd.h" +#include "rtw_phl_cmd.h" +#include "../phl/phl_headers_core.h" +#include "phl_api_tmp.h" +#include "rtw_phl.h" + +/*GEORGIA_TODO_FIXIT*/ +#include "_hal_rate.h" +#include "_hal_api_tmp.h" + +#include "platform_ops.h" +#include "rtw_scan.h" #ifdef CONFIG_RTW_80211R #include #endif @@ -101,19 +88,32 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #ifdef CONFIG_RTW_MBO #include #endif +#include +#include +#include #include #include #include + +#ifdef CONFIG_RTW_CORE_RXSC +#include +#endif +#ifdef CONFIG_CORE_TXSC +#include +#endif + #include #include #include +#include "rtw_cfg.h" #include -#include #include #include #include +#include #include #include +#include #ifdef CONFIG_RTW_WDS #include "../core/wds/rtw_wds.h" #endif @@ -123,9 +123,8 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #ifdef CONFIG_WIFI_MONITOR #include "../core/monitor/rtw_radiotap.h" #endif -#include + #include -#include #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER #include @@ -143,16 +142,13 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #ifdef CONFIG_MP_INCLUDED #include + #include #endif /* CONFIG_MP_INCLUDED */ #ifdef CONFIG_BR_EXT #include #endif /* CONFIG_BR_EXT */ -#ifdef CONFIG_IOL - #include -#endif /* CONFIG_IOL */ - #include #include #include @@ -160,18 +156,7 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include -#include -#include - -#ifdef CONFIG_MCC_MODE - #include -#endif /*CONFIG_MCC_MODE */ - -#ifdef CONFIG_RTW_REPEATER_SON - #include -#endif /*CONFIG_RTW_REPEATER_SON */ - -#include +#include #define SPEC_DEV_ID_NONE BIT(0) #define SPEC_DEV_ID_DISABLE_HT BIT(1) @@ -180,6 +165,13 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) #define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) +#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) +//#define PHLRX_LOG(fmt, args...) printk("phl-rx [%s][%d]"fmt, __FUNCTION__,__LINE__, ## args) +#define PHLRX_LOG printk("phl-rx [%s][%d] \n", __FUNCTION__, __LINE__); +#define PHLRX_ENTER printk("phl-rx [%s][%d] ++\n", __FUNCTION__, __LINE__); +#define PHLRX_EXIT printk("phl-rx [%s][%d] --\n", __FUNCTION__, __LINE__); +#endif + struct specific_device_id { u32 flags; @@ -198,12 +190,14 @@ struct registry_priv { u8 network_mode; /* infra, ad-hoc, auto */ u8 channel;/* ad-hoc support requirement */ u8 wireless_mode;/* A, B, G, auto */ - u8 scan_mode;/* active, passive */ + u8 band_type; + enum rtw_phl_scan_type scan_mode;/*scan methods - active, passive */ u8 radio_enable; u8 preamble;/* long, short, auto */ u8 vrtl_carrier_sense;/* Enable, Disable, Auto */ u8 vcs_type;/* RTS/CTS, CTS-to-self */ u16 rts_thresh; + u8 hw_rts_en; u16 frag_thresh; u8 adhoc_tx_pwr; u8 soft_ap; @@ -257,11 +251,6 @@ struct registry_priv { WLAN_BSSID_EX dev_network; -#if CONFIG_TX_AC_LIFETIME - u8 tx_aclt_flags; - struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM]; -#endif - u8 tx_bw_mode; #ifdef CONFIG_AP_MODE u8 bmc_tx_rate; @@ -285,7 +274,6 @@ struct registry_priv { /* 0x21 means enable 2.4G 40MHz & 5G 80MHz */ u8 bw_mode; u8 ampdu_enable;/* for tx */ - u8 rx_stbc; u8 rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */ u8 tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */ u8 tx_quick_addba_req; @@ -298,8 +286,13 @@ struct registry_priv { u8 short_gi; /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ u8 ldpc_cap; - /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ - u8 stbc_cap; + /* + * BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx + * BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx + * BIT8: Enable HE STBC Rx, BIT9: Enable HE STBC Rx(greater than 80M) + * BIT10: Enable HE STBC Tx, BIT11: Enable HE STBC Tx(greater than 80M) + */ + u16 stbc_cap; #if defined(CONFIG_RTW_TX_NPATH_EN) u8 tx_npath; #endif @@ -315,6 +308,7 @@ struct registry_priv { * BIT5: Enable HT Beamformee */ u8 beamform_cap; + u8 dyn_txbf; u8 beamformer_rf_num; u8 beamformee_rf_num; #endif /* CONFIG_80211N_HT */ @@ -326,13 +320,17 @@ struct registry_priv { u8 vht_rx_mcs_map[2]; #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211AX_HE + u8 he_enable; /* 0:disable, 1:enable, 2:auto */ +#endif + + u8 lowrate_two_xmit; + u8 low_power ; u8 wifi_spec;/* !turbo_mode */ - u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */ - u8 tx_path_lmt; /* limit of TX path number, 0: not specified */ - u8 rx_path_lmt; /* limit of TX path number, 0: not specified */ + u8 rf_path; /*rf_config*/ u8 tx_nss; u8 rx_nss; @@ -341,10 +339,14 @@ struct registry_priv { #endif char alpha2[2]; u8 channel_plan; - u8 excl_chs[MAX_CHANNEL_NUM]; + u8 excl_chs[MAX_CHANNEL_NUM_2G_5G]; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 channel_plan_6g; + u8 excl_chs_6g[MAX_CHANNEL_NUM_6G]; +#endif u8 full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/ -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC u8 btcoex; u8 bt_iso; u8 bt_sco; @@ -360,10 +362,6 @@ struct registry_priv { u8 switch_usb_mode; - u8 usbss_enable;/* 0:disable,1:enable */ - u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */ - u8 hwpwrp_detect;/* 0:disable,1:enable */ - u8 hw_wps_pbc;/* 0:disable,1:enable */ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE @@ -374,37 +372,22 @@ struct registry_priv { u8 max_roaming_times; /* the max number driver will try to roaming */ #endif -#ifdef CONFIG_IOL - u8 fw_iol; /* enable iol without other concern */ -#endif - #ifdef CONFIG_80211D - u8 enable80211d; + u8 country_ie_slave_en_role; + u8 country_ie_slave_en_ifbmp; #endif u8 ifname[16]; u8 if2name[16]; - u8 notch_filter; - /* for pll reference clock selction */ u8 pll_ref_clk_sel; - /* define for tx power adjust */ -#if CONFIG_TXPWR_LIMIT - u8 RegEnableTxPowerLimit; -#endif - u8 RegEnableTxPowerByRate; - u8 target_tx_pwr_valid; s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM]; #if CONFIG_IEEE80211_BAND_5GHZ s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1]; #endif - s16 antenna_gain; - - u8 tsf_update_pause_factor; - u8 tsf_update_restore_factor; s8 TxBBSwing_2G; s8 TxBBSwing_5G; @@ -421,12 +404,18 @@ struct registry_priv { u8 load_phy_file; u8 RegDecryptCustomFile; #endif -#ifdef CONFIG_CONCURRENT_MODE - u8 virtual_iface_num; +#if defined(CONFIG_CONCURRENT_MODE) && !RTW_P2P_GROUP_INTERFACE #ifdef CONFIG_P2P u8 sel_p2p_iface; #endif #endif + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST + u8 ignore_go_in_scan; + u8 ignore_low_rssi_in_scan; +#endif + u32 vo_edca; + u8 qos_opt_enable; u8 hiq_filter; @@ -443,9 +432,6 @@ struct registry_priv { u8 acs_mode; #endif -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - u8 nm_mode; -#endif u32 reg_rxgain_offset_2g; u32 reg_rxgain_offset_5gl; u32 reg_rxgain_offset_5gm; @@ -454,21 +440,6 @@ struct registry_priv { #ifdef CONFIG_DFS_MASTER u8 dfs_region_domain; #endif - u8 amsdu_mode; -#ifdef CONFIG_MCC_MODE - u8 en_mcc; - u32 rtw_mcc_single_tx_cri; - u32 rtw_mcc_ap_bw20_target_tx_tp; - u32 rtw_mcc_ap_bw40_target_tx_tp; - u32 rtw_mcc_ap_bw80_target_tx_tp; - u32 rtw_mcc_sta_bw20_target_tx_tp; - u32 rtw_mcc_sta_bw40_target_tx_tp; - u32 rtw_mcc_sta_bw80_target_tx_tp; - s8 rtw_mcc_policy_table_idx; - u8 rtw_mcc_duration; - u8 rtw_mcc_enable_runtime_duration; - u8 rtw_mcc_phydm_offload; -#endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI u8 en_napi; @@ -486,11 +457,6 @@ struct registry_priv { u8 suspend_type; #endif - u8 recvbuf_nr; - -#ifdef CONFIG_SUPPORT_TRX_SHARED - u8 trx_share_mode; -#endif u8 check_hw_status; u8 wowlan_sta_mix_mode; @@ -506,23 +472,9 @@ struct registry_priv { u8 en_tdls; #endif -#ifdef CONFIG_ADVANCE_OTA - u8 adv_ota; -#endif - #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT u8 fw_param_init; #endif -#ifdef CONFIG_DYNAMIC_SOML - u8 dyn_soml_en; - u8 dyn_soml_train_num; - u8 dyn_soml_interval; - u8 dyn_soml_period; - u8 dyn_soml_delay; -#endif -#ifdef CONFIG_FW_HANDLE_TXBCN - u8 fw_tbtt_rpt; -#endif #ifdef DBG_LA_MODE u8 la_mode_en; @@ -551,31 +503,29 @@ struct registry_priv { */ u32 scan_interval_thr; #endif - -#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY - u8 rtw_8822c_xcap_overwrite; -#endif + u8 deny_legacy; #ifdef CONFIG_RTW_MULTI_AP u8 unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM]; u16 max_unassoc_sta_cnt; #endif + +#ifdef CONFIG_IOCTL_CFG80211 + u16 roch_min_home_dur; /* min duration for op channel */ + u16 roch_max_away_dur; /* max acceptable away duration for remain on channel */ + u16 roch_extend_dur; /* minimum duration to stay in roch when mgnt tx */ +#endif + +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) + unsigned long go_hidden_ssid_mode; + ATOMIC_T set_hide_ssid_timer; +#endif + u8 amsdu_mode; }; /* For registry parameters */ #define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field)) #define RGTRY_SZ(field) sizeof(((struct registry_priv *) 0)->field) -#define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G) -#define GetRegAmplifierType5G(_Adapter) (_Adapter->registrypriv.AmplifierType_5G) - -#define GetRegTxBBSwing_2G(_Adapter) (_Adapter->registrypriv.TxBBSwing_2G) -#define GetRegTxBBSwing_5G(_Adapter) (_Adapter->registrypriv.TxBBSwing_5G) - -#define GetRegbENRFEType(_Adapter) (_Adapter->registrypriv.bEn_RFE) -#define GetRegRFEType(_Adapter) (_Adapter->registrypriv.RFE_Type) -#define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type) -#define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type) - #define WOWLAN_IS_STA_MIX_MODE(_Adapter) (_Adapter->registrypriv.wowlan_sta_mix_mode) #define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field)) #define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) @@ -602,32 +552,31 @@ struct registry_priv { #define REGSTY_IS_11AC_24G_ENABLE(regsty) 0 #endif +#define REGSTY_IS_11AX_ENABLE(regsty) ((regsty)->he_enable != 0) +#define REGSTY_IS_11AX_AUTO(regsty) ((regsty)->he_enable == 2) + #ifdef CONFIG_REGD_SRC_FROM_OS #define REGSTY_REGD_SRC_FROM_OS(regsty) ((regsty)->regd_src == REGD_SRC_OS) #else #define REGSTY_REGD_SRC_FROM_OS(regsty) 0 #endif -typedef struct rtw_if_operations { - int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf, - size_t len, bool fixed); - int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf, - size_t len, bool fixed); -} RTW_IF_OPS, *PRTW_IF_OPS; - #ifdef CONFIG_SDIO_HCI #include - #define INTF_DATA SDIO_DATA - #define INTF_OPS PRTW_IF_OPS -#elif defined(CONFIG_GSPI_HCI) +#endif +#ifdef CONFIG_GSPI_HCI #include - #define INTF_DATA GSPI_DATA -#elif defined(CONFIG_PCI_HCI) +#endif +#ifdef CONFIG_PCI_HCI #include #endif +#ifdef CONFIG_USB_HCI + #include +#endif -#define get_hw_port(adapter) (adapter->hw_port) +#include +#define get_hw_port(adapter) (adapter->hw_port) #ifdef CONFIG_CONCURRENT_MODE #define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) #define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER) @@ -639,7 +588,37 @@ typedef struct rtw_if_operations { #define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums) #define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id]) -#define GetDefaultAdapter(padapter) padapter + +#ifdef RTW_PHL_TX + +#if 1 +#define PHLTX_ENTER //printk("eric-tx [%s][%d] ++\n", __FUNCTION__, __LINE__) +#define PHLTX_LOG //printk("eric-tx [%s][%d]\n", __FUNCTION__, __LINE__) +#define PHLTX_EXIT //printk("eric-tx [%s][%d] --\n", __FUNCTION__, __LINE__) +#define PHLTX_ERR //printk("PHLTX_ERR [%s][%d]\n", __FUNCTION__, __LINE__) +#else +#define PHLTX_ENTER printk("eric-tx [%s][%d] ++\n", __FUNCTION__, __LINE__) +#define PHLTX_LOG printk("eric-tx [%s][%d]\n", __FUNCTION__, __LINE__) +#define PHLTX_EXIT printk("eric-tx [%s][%d] --\n", __FUNCTION__, __LINE__) + +#define PHLTX_ERR printk("PHLTX_ERR [%s][%d]\n", __FUNCTION__, __LINE__) +#endif + + +#define SZ_TXREQ (sizeof(struct rtw_xmit_req)) +#define SZ_HEAD_BUF 100 +#define SZ_TAIL_BUF 30 + +#define NUM_PKT_LIST_PER_TXREQ 8 +#define SZ_PKT_LIST (sizeof(struct rtw_pkt_buf_list)) + + +#define SZ_TX_RING (SZ_TXREQ+SZ_HEAD_BUF+SZ_TAIL_BUF+(SZ_PKT_LIST*NUM_PKT_LIST_PER_TXREQ)) +#define SZ_MGT_RING (SZ_TXREQ + SZ_PKT_LIST)/* MGT_TXREQ_QMGT */ + +#define MAX_TX_RING_NUM 4096 +#endif + enum _IFACE_ID { IFACE_ID0, /*PRIMARY_ADAPTER*/ @@ -656,7 +635,6 @@ enum _IFACE_ID { #define VIF_START_ID 1 #ifdef CONFIG_DBG_COUNTER - struct rx_logs { u32 intf_rx; u32 intf_rx_err_recvframe; @@ -781,6 +759,24 @@ struct int_logs { #endif /* CONFIG_DBG_COUNTER */ +#ifdef RTW_DETECT_HANG +struct fw_hang_info { + u8 dbg_is_fw_hang; + u8 dbg_is_fw_gone; +}; + +struct rxff_hang_info { + u8 dbg_is_rxff_hang; + u8 rx_ff_hang_cnt; +}; + +struct hang_info { + u32 enter_cnt; + struct rxff_hang_info dbg_rxff_hang_info; + struct fw_hang_info dbg_fw_hang_info; +}; +#endif /* RTW_DETECT_HANG */ + struct debug_priv { u32 dbg_sdio_free_irq_error_cnt; u32 dbg_sdio_alloc_irq_error_cnt; @@ -796,7 +792,7 @@ struct debug_priv { u32 dbg_carddisable_cnt; u32 dbg_carddisable_error_cnt; u32 dbg_ps_insuspend_cnt; - u32 dbg_dev_unload_inIPS_cnt; + u32 dbg_dev_unload_inIPS_cnt; u32 dbg_wow_leave_ps_fail_cnt; u32 dbg_scan_pwr_state_cnt; u32 dbg_downloadfw_pwr_state_cnt; @@ -815,6 +811,9 @@ struct debug_priv { u64 dbg_rx_fifo_last_overflow; u64 dbg_rx_fifo_curr_overflow; u64 dbg_rx_fifo_diff_overflow; +#ifdef RTW_DETECT_HANG + struct hang_info dbg_hang_info; +#endif }; struct rtw_traffic_statistics { @@ -835,119 +834,14 @@ struct rtw_traffic_statistics { u32 cur_rx_tp; /* Rx throughput in Mbps. */ }; -#define SEC_CAP_CHK_BMC BIT0 #define SEC_CAP_CHK_EXTRA_SEC BIT1 /* 256 bit */ -#define SEC_CAP_CHK_WRITE_CAM_NEW_RULE BIT2 - -#define MACID_DROP BIT0 -#define MACID_DROP_INDIRECT BIT1 - -#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0 - -struct sec_cam_bmp { - u32 m0; -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) - u32 m1; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) - u32 m2; -#endif -#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) - u32 m3; -#endif -}; - -struct cam_ctl_t { - _lock lock; - - u8 sec_cap; - u32 flags; - - u8 num; - struct sec_cam_bmp used; - - _mutex sec_cam_access_mutex; -}; - -struct sec_cam_ent { - u16 ctrl; - u8 mac[ETH_ALEN]; - u8 key[16]; -}; #define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" #define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] -#define RTW_DEFAULT_MGMT_MACID 1 - -struct macid_bmp { - u32 m0; -#if (MACID_NUM_SW_LIMIT > 32) - u32 m1; -#endif -#if (MACID_NUM_SW_LIMIT > 64) - u32 m2; -#endif -#if (MACID_NUM_SW_LIMIT > 96) - u32 m3; -#endif -}; -#ifdef CONFIG_CLIENT_PORT_CFG -struct clt_port_t{ - _lock lock; - u8 bmp; - s8 num; -}; -#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num) -#endif - -struct macid_ctl_t { - _lock lock; - u8 num; - struct macid_bmp used; - struct macid_bmp bmc; - struct macid_bmp if_g[CONFIG_IFACE_NUMBER]; - struct macid_bmp ch_g[2]; /* 2 ch concurrency */ - - u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/ - - u8 h2c_msr[MACID_NUM_SW_LIMIT]; - u8 bw[MACID_NUM_SW_LIMIT]; - u8 vht_en[MACID_NUM_SW_LIMIT]; - u32 rate_bmp0[MACID_NUM_SW_LIMIT]; - u32 rate_bmp1[MACID_NUM_SW_LIMIT]; - u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */ - - struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */ - u8 macid_cap; - /* macid sleep registers */ -#ifdef CONFIG_PROTSEL_MACSLEEP - u16 reg_sleep_ctrl; - u16 reg_sleep_info; - u16 reg_drop_ctrl; - u16 reg_drop_info; -#else - u16 reg_sleep_m0; - u16 reg_drop_m0; -#if (MACID_NUM_SW_LIMIT > 32) - u16 reg_sleep_m1; - u16 reg_drop_m1; -#endif -#if (MACID_NUM_SW_LIMIT > 64) - u16 reg_sleep_m2; - u16 reg_drop_m2; -#endif -#if (MACID_NUM_SW_LIMIT > 96) - u16 reg_sleep_m3; - u16 reg_drop_m3; -#endif -#endif - u16 macid_txrpt; - u8 macid_txrpt_pgsz; -}; /* used for rf_ctl_t.rate_bmp_cck_ofdm */ #define RATE_BMP_CCK 0x000F @@ -1002,16 +896,55 @@ struct macid_ctl_t { #define OFFCHS_LEAVE_OP 2 #define OFFCHS_BACKING_OP 3 -#define TPC_MODE_DISABLE 0 -#define TPC_MODE_MANUAL 1 -#define TPC_MODE_INVALID 2 /* keep last */ - -#define TPC_MANUAL_CONSTRAINT_MAX 600 /* mB */ +#define COUNTRY_IE_SLAVE_EN_ROLE_STA BIT0 /* pure STA mode */ +#define COUNTRY_IE_SLAVE_EN_ROLE_GC BIT1 /* P2P group client */ struct rf_ctl_t { + bool disable_sw_chplan; enum regd_src_t regd_src; - const struct country_chplan *country_ent; + enum rtw_regd_inr regd_inr; + char alpha2[2]; u8 ChannelPlan; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 chplan_6g; +#endif + u8 edcca_mode_2g_override; +#if CONFIG_IEEE80211_BAND_5GHZ + u8 edcca_mode_5g_override; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + u8 edcca_mode_6g_override; +#endif +#if CONFIG_TXPWR_LIMIT + u8 txpwr_lmt_override; +#endif + +#if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT) + u8 proto_en; +#endif + + /* initial channel plan selectors */ + char init_alpha2[2]; + u8 init_ChannelPlan; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 init_chplan_6g; +#endif + + /* channel plan selectors by user */ + char user_alpha2[2]; /* "\x00\x00" is not set */ + u8 user_ChannelPlan; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 user_chplan_6g; +#endif + +#ifdef CONFIG_80211D + u8 country_ie_slave_en_role; + u8 country_ie_slave_en_ifbmp; + + struct country_ie_slave_record cisr[CONFIG_IFACE_NUMBER]; + u8 effected_cisr_id; +#endif + u8 max_chan_nums; RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; struct op_class_pref_t **spt_op_class_ch; @@ -1019,15 +952,10 @@ struct rf_ctl_t { u8 reg_spt_op_class_num; u8 cur_spt_op_class_num; struct p2p_channels channel_list; -#ifdef CONFIG_RTW_MBO - struct npref_ch_rtp ch_rtp; -#endif - - s16 antenna_gain; /* mBi */ u8 op_class; u8 op_ch; - s16 op_txpwr_max; /* EIRP in mBm */ + s16 op_txpwr_max; /* mBm */ u8 if_op_class[CONFIG_IFACE_NUMBER]; u8 if_op_ch[CONFIG_IFACE_NUMBER]; @@ -1042,32 +970,31 @@ struct rf_ctl_t { #if CONFIG_TXPWR_LIMIT u8 highest_ht_rate_bw_bmp; u8 highest_vht_rate_bw_bmp; - - _mutex txpwr_lmt_mutex; - _list reg_exc_list; - u8 regd_exc_num; - _list txpwr_lmt_list; - u8 txpwr_regd_num; - const char *regd_name; - - u8 txpwr_lmt_2g_cck_ofdm_state; - #if CONFIG_IEEE80211_BAND_5GHZ - u8 txpwr_lmt_5g_cck_ofdm_state; - u8 txpwr_lmt_5g_20_40_ref; - #endif #endif - u8 tpc_mode; - u16 tpc_manual_constraint; /* mB */ bool ch_sel_within_same_band; + u8 edcca_mode_2g; +#if CONFIG_IEEE80211_BAND_5GHZ + u8 edcca_mode_5g; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + u8 edcca_mode_6g; +#endif + enum band_type last_edcca_mode_op_band; + #if CONFIG_DFS - u8 csa_ch; + u8 csa_mode; u8 csa_switch_cnt; - u8 csa_ch_offset; + + /* @csa_ch_width definition from 802.11 spec + * 0 for 20 MHz or 40 MHz + * 1 for 80 MHz, 160 MHz or 80+80 MHz + * 2 for 160 MHz + * 3 for non-contiguous 80+80 MHz + */ u8 csa_ch_width; - u8 csa_ch_freq_seg0; /* Channel Center Frequency Segment 0 */ - u8 csa_ch_freq_seg1; /* Channel Center Frequency Segment 1 */ + struct rtw_chan_def csa_chandef; #ifdef CONFIG_DFS_MASTER u8 dfs_region_domain; @@ -1095,6 +1022,9 @@ struct rf_ctl_t { u8 dbg_dfs_choose_dfs_ch_first; #endif /* CONFIG_DFS_MASTER */ #endif /* CONFIG_DFS */ +#ifdef CONFIG_RTW_MBO + struct npref_ch_rtp ch_rtp; +#endif }; struct wow_ctl_t { @@ -1102,7 +1032,21 @@ struct wow_ctl_t { }; #define WOW_CAP_TKIP_OL BIT0 -#define WOW_CAP_HALMAC_ACCESS_PATTERN_IN_TXFIFO BIT1 + +#define RFCTL_REG_WORLDWIDE(rfctl) (IS_ALPHA2_WORLDWIDE(rfctl->alpha2)) +#define RFCTL_REG_ALPHA2_UNSPEC(rfctl) (IS_ALPHA2_UNSPEC(rfctl->alpha2)) /* ex: only domain code is specified */ + +#ifdef CONFIG_80211AC_VHT +#define RFCTL_REG_EN_11AC(rfctl) (((rfctl)->proto_en & CHPLAN_PROTO_EN_AC) ? 1 : 0) +#else +#define RFCTL_REG_EN_11AC(rfctl) 0 +#endif + +#ifdef CONFIG_80211AX_HE +#define RFCTL_REG_EN_11AX(rfctl) (((rfctl)->proto_en & CHPLAN_PROTO_EN_AX) ? 1 : 0) +#else +#define RFCTL_REG_EN_11AX(rfctl) 0 +#endif #define RTW_CAC_STOPPED 0 #ifdef CONFIG_DFS_MASTER @@ -1123,351 +1067,203 @@ struct wow_ctl_t { #define IS_DFS_SLAVE_WITH_RD(rfctl) 0 #endif -#ifdef CONFIG_MBSSID_CAM -#define TOTAL_MBID_CAM_NUM 8 -#define INVALID_CAM_ID 0xFF -struct mbid_cam_ctl_t { - _lock lock; - u8 bitmap; - ATOMIC_T mbid_entry_num; -}; -struct mbid_cam_cache { - u8 iface_id; - /*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/ - u8 mac_addr[ETH_ALEN]; -}; -#endif /*CONFIG_MBSSID_CAM*/ - -#ifdef RTW_HALMAC -struct halmac_indicator { - struct submit_ctx *sctx; - u8 *buffer; - u32 buf_size; - u32 ret_size; - u32 status; -}; - -struct halmacpriv { - /* flags */ -#ifdef CONFIG_SDIO_HCI - /* - * Indirect Access for SDIO, - * 0:default, 1:enable, 2:disable - */ - u8 sdio_io_indir; -#endif /* CONFIG_SDIO_HCI */ - /* For asynchronous functions */ - struct halmac_indicator *indicator; +#ifdef CONFIG_USB_HCI - /* Hardware parameters */ -#ifdef CONFIG_SDIO_HCI - /* Store hardware tx queue page number setting */ - u16 txpage[HW_QUEUE_ENTRY]; -#endif /* CONFIG_SDIO_HCI */ +struct trx_urb_buf_q { + _queue free_urb_buf_queue; + u8 *alloc_urb_buf; + u8 *urb_buf; + uint free_urb_buf_cnt; }; -#endif /* RTW_HALMAC */ -#ifdef CONFIG_FW_MULTI_PORT_SUPPORT -/*info for H2C-0x2C*/ -struct dft_info { - u8 port_id; - u8 mac_id; +struct data_urb { + _list list; + struct urb *urb; + u8 bulk_id; + u8 minlen; }; -#endif -#ifdef CONFIG_HW_P0_TSF_SYNC -struct tsf_info { - u8 sync_port;/*port_x's tsf sync to port_0*/ - u8 offset; /*tsf timer offset*/ -}; #endif -struct protsel { - _mutex mutex; /* protect this structure */ - ATOMIC_T refcnt; /* reference count */ - u32 sel; /* save the last sel port */ +struct trx_data_buf_q { + _queue free_data_buf_queue; + u8 *alloc_data_buf; + u8 *data_buf; + uint free_data_buf_cnt; }; -#ifdef CONFIG_RTL8814B -#define MAX_BULKOUT_NUM 7 -#ifdef CONFIG_USB_HCI -#define MAX_ENDPOINT_NUM 8 -#endif -#else -#define MAX_BULKOUT_NUM 4 + +struct lite_data_buf { + _list list; + struct dvobj_priv *dvobj; + u16 buf_tag; + u8 *pbuf; + u8 *phl_buf_ptr; /*point to phl rtw_usb_buf from phl*/ #ifdef CONFIG_USB_HCI -#define MAX_ENDPOINT_NUM 6 -#endif + struct data_urb *dataurb; #endif + struct submit_ctx *sctx; -struct dvobj_priv { - /*-------- below is common data --------*/ - u8 chip_type; - u8 HardwareType; - u8 interface_type;/*USB,SDIO,SPI,PCI*/ +}; - ATOMIC_T bSurpriseRemoved; - ATOMIC_T bDriverStopped; +#ifdef CONFIG_DRV_FAKE_AP +struct fake_ap { + struct sk_buff_head rxq; /* RX queue */ + _workitem work; + struct rtw_timer_list bcn_timer; +}; +#endif /* CONFIG_DRV_FAKE_AP */ +/*device object*/ +struct dvobj_priv { + /*-------- below is common data --------*/ + ATOMIC_T bSurpriseRemoved; + ATOMIC_T bDriverStopped; + ATOMIC_T hw_start; s32 processing_dev_remove; - struct debug_priv drv_dbg; - _mutex hw_init_mutex; - _mutex h2c_fwcmd_mutex; - _mutex ioctrl_mutex; - -#ifdef CONFIG_RTW_CUSTOMER_STR - _mutex customer_str_mutex; - struct submit_ctx *customer_str_sctx; - u8 customer_str[RTW_CUSTOMER_STR_LEN]; -#endif - _mutex setch_mutex; _mutex setbw_mutex; _mutex rf_read_reg_mutex; -#ifdef CONFIG_SDIO_INDIRECT_ACCESS - _mutex sd_indirect_access_mutex; -#endif - -#ifdef CONFIG_SYSON_INDIRECT_ACCESS - _mutex syson_indirect_access_mutex; /* System On Reg R/W */ -#endif - - unsigned char oper_channel; /* saved channel info when call set_channel_bw */ - unsigned char oper_bwmode; - unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ - systime on_oper_ch_time; - - u8 union_ch; - u8 union_bw; - u8 union_offset; - /* backup values when union_ch is set to 0 */ - u8 union_ch_bak; - u8 union_bw_bak; - u8 union_offset_bak; _adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/ + u8 virtual_iface_num;/*from registary*/ u8 iface_nums; /* total number of ifaces used runtime */ struct mi_state iface_state; -#ifdef CONFIG_AP_MODE - #ifdef CONFIG_SUPPORT_MULTI_BCN - u8 nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */ - u16 inter_bcn_space; /* unit:ms */ - _queue ap_if_q; - u8 vap_map; - u8 fw_bcn_offload; - u8 vap_tbtt_rpt_map; - #endif /*CONFIG_SUPPORT_MULTI_BCN*/ - #ifdef CONFIG_RTW_REPEATER_SON - struct rtw_rson_struct rson_data; - #endif -#endif -#ifdef CONFIG_CLIENT_PORT_CFG - struct clt_port_t clt_port; -#endif + enum rtl_ic_id ic_id; + enum rtw_hci_type interface_type;/*USB,SDIO,SPI,PCI*/ -#ifdef CONFIG_HW_P0_TSF_SYNC - struct tsf_info p0_tsf; -#endif - systime periodic_tsf_update_etime; - _timer periodic_tsf_update_end_timer; - - struct macid_ctl_t macid_ctl; + /*CONFIG_PHL_ARCH*/ + void *phl; + struct rtw_phl_com_t *phl_com; + #ifdef DBG_PHL_MEM_ALLOC + ATOMIC_T phl_mem; + #endif - struct cam_ctl_t cam_ctl; + struct rf_ctl_t rf_ctl; + /* move to phl */ + /* struct macid_ctl_t macid_ctl; *//*shared HW resource*/ + struct cam_ctl_t cam_ctl;/*sec-cam shared HW resource*/ struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT]; - struct wow_ctl_t wow_ctl; -#ifdef CONFIG_MBSSID_CAM - struct mbid_cam_ctl_t mbid_cam_ctl; - struct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM]; -#endif - struct rf_ctl_t rf_ctl; + /****** Band info may be x 2*********/ + /* saved channel info when call set_channel_bw */ + systime on_oper_ch_time; -#if CONFIG_TX_AC_LIFETIME - struct tx_aclt_conf_t tx_aclt_force_val; - u8 tx_aclt_flags; - struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM]; -#endif + /****** hal dep info*********/ - /* In /Out Pipe information */ - int RtInPipe[2]; - int RtOutPipe[MAX_BULKOUT_NUM]; - u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ - u8 irq_alloc; ATOMIC_T continual_io_error; - ATOMIC_T disable_func; u8 xmit_block; _lock xmit_block_lock; struct pwrctrl_priv pwrctl_priv; + struct cmd_priv cmdpriv; + struct recv_priv recvpriv; +#ifdef CONFIG_WOWLAN + struct wow_priv wowlan_priv; +#endif /* CONFIG_WOWLAN */ struct rtw_traffic_statistics traffic_stat; -#ifdef PLATFORM_LINUX + #ifdef PLATFORM_LINUX _thread_hdl_ rtnl_lock_holder; - #if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) + #if defined(CONFIG_IOCTL_CFG80211) struct wiphy *wiphy; #endif -#endif /* PLATFORM_LINUX */ + #endif /* PLATFORM_LINUX */ -#ifdef CONFIG_SWTIMER_BASED_TXBCN - _timer txbcn_timer; -#endif + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ _timer dynamic_chk_timer; /* dynamic/periodic check timer */ - -#ifdef CONFIG_RTW_NAPI_DYNAMIC - u8 en_napi_dynamic; -#endif /* CONFIG_RTW_NAPI_DYNAMIC */ - -#ifdef RTW_HALMAC - void *halmac; - struct halmacpriv hmpriv; -#endif /* RTW_HALMAC */ + #endif -#ifdef CONFIG_FW_MULTI_PORT_SUPPORT - /*info for H2C-0x2C*/ - struct dft_info dft; -#endif + #ifdef CONFIG_RTW_NAPI_DYNAMIC + u8 en_napi_dynamic; + #endif /* CONFIG_RTW_NAPI_DYNAMIC */ -#ifdef CONFIG_RTW_WIFI_HAL + #ifdef CONFIG_RTW_WIFI_HAL u32 nodfs; -#endif + #endif - /*-------- below is for SDIO INTERFACE --------*/ + /*-------- below is for PCIE/USB/SDIO INTERFACE --------*/ + #ifdef CONFIG_SDIO_HCI + SDIO_DATA sdio_data; + #endif + #ifdef CONFIG_GSPI_HCI + GSPI_DATA gspi_data; + #endif + #ifdef CONFIG_PCI_HCI + PCI_DATA pci_data; + #endif + #ifdef CONFIG_USB_HCI + USB_DATA usb_data; + #endif -#ifdef INTF_DATA - INTF_DATA intf_data; -#endif -#ifdef INTF_OPS - INTF_OPS intf_ops; -#endif + struct rtw_intf_ops *intf_ops; -#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT - u8 tx_aval_int_thr_mode;/* if 0=>threhold set by reques(default) ;if 1=>fixed by proc; if 2: fixed by sdio_tx_max_len */ - u8 tx_aval_int_thr_value; -#endif/*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/ + struct trx_data_buf_q litexmitbuf_q; + struct trx_data_buf_q litexmit_extbuf_q; + struct trx_data_buf_q literecvbuf_q; /*-------- below is for USB INTERFACE --------*/ + #ifdef CONFIG_USB_HCI + u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ + struct trx_urb_buf_q xmit_urb_q; + struct trx_urb_buf_q recv_urb_q; + #ifdef CONFIG_USB_INTERRUPT_IN_PIPE + struct trx_data_buf_q intin_buf_q; + struct trx_urb_buf_q intin_urb_q; + ATOMIC_T rx_pending_cnt;/* urb counts for sumit to host */ + #endif + #endif/* CONFIG_USB_HCI */ -#ifdef CONFIG_USB_HCI + /*-------- below is for PCIE INTERFACE --------*/ + #ifdef CONFIG_PCI_HCI - u8 usb_speed; /* 1.1, 2.0 or 3.0 */ - u8 nr_endpoint; - u8 RtNumInPipes; - u8 RtNumOutPipes; - int ep_num[MAX_ENDPOINT_NUM]; /* endpoint number */ - int RegUsbSS; + #endif/* CONFIG_PCI_HCI */ - _sema usb_suspend_sema; + /* also for RTK T/P Testing Mode */ + u8 scan_deny; -#ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _mutex usb_vendor_req_mutex; -#endif -#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC - u8 *usb_alloc_vendor_req_buf; - u8 *usb_vendor_req_buf; -#endif - -#ifdef PLATFORM_LINUX - struct usb_interface *pusbintf; - struct usb_device *pusbdev; -#endif/* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - struct usb_interface *pusbintf; - struct usb_device *pusbdev; -#endif/* PLATFORM_FREEBSD */ - -#endif/* CONFIG_USB_HCI */ - - /*-------- below is for PCIE INTERFACE --------*/ - -#ifdef CONFIG_PCI_HCI - -#ifdef PLATFORM_LINUX - struct pci_dev *ppcidev; - - /* PCI MEM map */ - unsigned long pci_mem_end; /* shared mem end */ - unsigned long pci_mem_start; /* shared mem start */ - - /* PCI IO map */ - unsigned long pci_base_addr; /* device I/O address */ - -#ifdef CONFIG_PLATFORM_RTK129X - unsigned long ctrl_start; - /* PCI MASK addr */ - unsigned long mask_addr; - - /* PCI TRANSLATE addr */ - unsigned long tran_addr; - - _lock io_reg_lock; -#endif - - /* PciBridge */ - struct pci_priv pcipriv; - - unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */ - u16 irqline; - u8 irq_enabled; - RT_ISR_CONTENT isr_content; - _lock irq_th_lock; - - u8 bdma64; -#endif/* PLATFORM_LINUX */ + #ifdef CONFIG_RTW_CUSTOMER_STR + _mutex customer_str_mutex; + struct submit_ctx *customer_str_sctx; + u8 customer_str[RTW_CUSTOMER_STR_LEN]; + #endif -#endif/* CONFIG_PCI_HCI */ + struct debug_priv drv_dbg; -#ifdef CONFIG_MCC_MODE - struct mcc_obj_priv mcc_objpriv; -#endif /*CONFIG_MCC_MODE */ +#ifdef CONFIG_DRV_FAKE_AP + struct fake_ap fakeap; +#endif /* CONFIG_DRV_FAKE_AP */ -#ifdef CONFIG_RTW_TPT_MODE - u8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */ - u32 edca_be_ul; - u32 edca_be_dl; -#endif - /* also for RTK T/P Testing Mode */ - u8 scan_deny; + #ifdef CONFIG_FILE_FWIMG + /* Placeholder for per physical adapter firmware file name. + * Freddie ToDo: Move to phl_com as PHL/HAL common feature + * should be placed there. + */ + char fw_file[PATH_LENGTH_MAX]; + #endif - /* protect sel to safely access */ -#ifdef CONFIG_PROTSEL_PORT - struct protsel protsel_port; -#endif -#ifdef CONFIG_PROTSEL_ATIMDTIM - struct protsel protsel_atimdtim; -#endif -#ifdef CONFIG_PROTSEL_MACSLEEP - struct protsel protsel_macsleep; -#endif -#ifdef CONFIG_WOWLAN - u8 bcn_ctrl_clint3_bf_suspend; - u16 rxfltmap2_bf_suspend; - u8 lifetime_en; - u32 pkt_lifetime; - u32 rcr_bf_suspend; - u32 cr_ext_bf_suspend; -#endif /* CONFIG_WOWLAN */ -#if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC) - u16 sync_tsfr_counter; -#endif + /* WPAS maintain from w1.fi */ +#define RTW_WPAS_W1FI 0x00 + /* WPAS maintain from android */ +#define RTW_WPAS_ANDROID 0x01 + u8 wpas_type; }; -#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) +#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state)) #define DEV_TDLS_LD_NUM(_dvobj) MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state)) @@ -1485,40 +1281,49 @@ struct dvobj_priv { #define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state)) #define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state)) #define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state)) - -#define DEV_U_CH(_dvobj) ((_dvobj)->union_ch) -#define DEV_U_BW(_dvobj) ((_dvobj)->union_bw) -#define DEV_U_OFFSET(_dvobj) ((_dvobj)->union_offset) +#define DEV_U_CH(_dvobj) MSTATE_U_CH(&((_dvobj)->iface_state)) +#define DEV_U_BW(_dvobj) MSTATE_U_BW(&((_dvobj)->iface_state)) +#define DEV_U_OFFSET(_dvobj) MSTATE_U_OFFSET(&((_dvobj)->iface_state)) #define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv)) +#ifdef CONFIG_WOWLAN +#define dvobj_to_wowlan(dvobj) (&(dvobj->wowlan_priv)) +#endif /* CONFIG_WOWLAN */ #define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv) #define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl)) #define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl)) #define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv)) -#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) +#if defined(CONFIG_IOCTL_CFG80211) #define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy) #endif #define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl)) #define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl) -static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj) +#ifdef CONFIG_PCI_HCI +static inline PCI_DATA *dvobj_to_pci(struct dvobj_priv *dvobj) { - ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE); + return &dvobj->pci_data; } -static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj) +#endif +#ifdef CONFIG_USB_HCI +static inline USB_DATA *dvobj_to_usb(struct dvobj_priv *dvobj) { - ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE); + return &dvobj->usb_data; } -static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj) +#endif +#ifdef CONFIG_SDIO_HCI +static inline SDIO_DATA *dvobj_to_sdio(struct dvobj_priv *dvobj) { - ATOMIC_SET(&dvobj->bDriverStopped, _TRUE); + return &dvobj->sdio_data; } -static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj) +#endif +#ifdef CONFIG_GSPI_HCI +static inline GSPI_DATA *dvobj_to_gspi(struct dvobj_priv *dvobj) { - ATOMIC_SET(&dvobj->bDriverStopped, _FALSE); + return &dvobj->gspi_data; } -#define dev_is_surprise_removed(dvobj) (ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE) -#define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE) +#endif + #ifdef PLATFORM_LINUX static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj) @@ -1528,46 +1333,24 @@ static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj) #endif #ifdef CONFIG_USB_HCI - return &dvobj->pusbintf->dev; + return &dvobj->usb_data.pusbintf->dev; #endif #ifdef CONFIG_SDIO_HCI - return &dvobj->intf_data.func->dev; + return &dvobj->sdio_data.func->dev; #endif #ifdef CONFIG_GSPI_HCI - return &dvobj->intf_data.func->dev; + return &dvobj->gspi_data.func->dev; #endif #ifdef CONFIG_PCI_HCI - return &dvobj->ppcidev->dev; + return &dvobj->pci_data.ppcidev->dev; #endif } #endif -_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj); _adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj); _adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr); #define dvobj_get_primary_adapter(dvobj) ((dvobj)->padapters[IFACE_ID0]) -enum _hw_port { - HW_PORT0, - HW_PORT1, - HW_PORT2, - HW_PORT3, - HW_PORT4, - MAX_HW_PORT, -}; - -#ifdef CONFIG_CLIENT_PORT_CFG -enum _client_port { - CLT_PORT0 = HW_PORT1, - CLT_PORT1 = HW_PORT2, - CLT_PORT2 = HW_PORT3, - CLT_PORT3 = HW_PORT4, - CLT_PORT_INVALID = HW_PORT0, -}; - -#define MAX_CLIENT_PORT_NUM 4 -#define get_clt_port(adapter) (adapter->client_port) -#endif enum _ADAPTER_TYPE { PRIMARY_ADAPTER, @@ -1575,12 +1358,6 @@ enum _ADAPTER_TYPE { MAX_ADAPTER = 0xFF, }; -typedef enum _DRIVER_STATE { - DRIVER_NORMAL = 0, - DRIVER_DISAPPEAR = 1, - DRIVER_REPLACE_DONGLE = 2, -} DRIVER_STATE; - #ifdef CONFIG_RTW_NAPI enum _NAPI_STATE { NAPI_DISABLE = 0, @@ -1588,7 +1365,7 @@ enum _NAPI_STATE { }; #endif -#ifdef CONFIG_MAC_LOOPBACK_DRIVER +#if 0 /*#ifdef CONFIG_MAC_LOOPBACK_DRIVER*/ typedef struct loopbackdata { _sema sema; _thread_hdl_ lbkthread; @@ -1607,186 +1384,327 @@ typedef struct loopbackdata { #define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode) #define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode) -struct _ADAPTER { - int DriverState;/* for disable driver using module, use dongle to replace module. */ - int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */ - int bDongle;/* build-in module or external dongle */ +#ifdef RTW_PHL_DBG_CMD +#define CORE_LOG_NUM (100) +#define MAX_FRAG (4) +#define INV_TXFORCE_VAL (0xFFFF) - #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) - _list list; - u8 vap_id; - #endif - struct dvobj_priv *dvobj; - struct mlme_priv mlmepriv; - struct mlme_ext_priv mlmeextpriv; - struct cmd_priv cmdpriv; - struct evt_priv evtpriv; - -#ifdef CONFIG_RTW_80211K - struct rm_priv rmpriv; -#endif - /* struct io_queue *pio_queue; */ - struct io_priv iopriv; - struct xmit_priv xmitpriv; - struct recv_priv recvpriv; - struct sta_priv stapriv; - struct security_priv securitypriv; - _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */ - struct registry_priv registrypriv; +enum _CORE_REC_DUMP { + REC_DUMP_NO = 0, + REC_DUMP_ALL, + REC_DUMP_TX, + REC_DUMP_RX, +}; -#ifdef CONFIG_RTW_NAPI - struct napi_struct napi; - u8 napi_state; -#endif +enum _CORE_REC_TYPE { + REC_TX_MGMT = 0, + REC_TX_DATA, + REC_TX_PHL, + REC_TX_PHL_RCC, + + REC_RX_PHL, + REC_RX_PHL_RCC, + REC_RX_MGMT, + REC_RX_DATA, + REC_RX_DATA_RETRY, +}; -#ifdef CONFIG_MP_INCLUDED - struct mp_priv mppriv; -#endif +struct core_record { + u32 type; + u32 totalSz; -#ifdef CONFIG_AP_MODE - struct hostapd_priv *phostapdpriv; -#endif + u32 wl_seq; + u32 wl_type; + u32 wl_subtype; + + u8 fragNum; + u32 fragLen[MAX_FRAG]; + void* virtAddr[MAX_FRAG]; + void* phyAddrL[MAX_FRAG]; + void* phyAddrH[MAX_FRAG]; +}; -#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_IOCTL_CFG80211) - struct roch_info rochinfo; +struct core_logs { + u32 txCnt_all; + u32 txCnt_data; + u32 txCnt_mgmt; + u32 txCnt_phl; + u32 txSize_phl; + u32 txCnt_recycle; + u32 txSize_recycle; + struct core_record drvTx[CORE_LOG_NUM]; + struct core_record phlTx[CORE_LOG_NUM]; + struct core_record txRcycle[CORE_LOG_NUM]; + + u32 rxCnt_phl; + u32 rxSize_phl; + u32 rxCnt_recycle; + u32 rxSize_recycle; + u32 rxCnt_data; + u32 rxCnt_data_retry; + u32 rxCnt_mgmt; + u32 rxCnt_all; + struct core_record drvRx[CORE_LOG_NUM]; + struct core_record phlRx[CORE_LOG_NUM]; + struct core_record rxRcycle[CORE_LOG_NUM]; +#ifdef CONFIG_RTW_CORE_RXSC + u32 rxCnt_data_orig; + u32 rxCnt_data_shortcut; #endif +}; - u32 setband; - ATOMIC_T bandskip; +#define MAX_TXBD_SIZE 40 +#define MAX_TXWD_SIZE 128 +#define MAX_RXWD_SIZE 32 -#ifdef CONFIG_P2P - struct wifidirect_info wdinfo; -#endif /* CONFIG_P2P */ -#ifdef CONFIG_TDLS - struct tdls_info tdlsinfo; -#endif /* CONFIG_TDLS */ +enum _PHL_REC_TYPE { + REC_TXBD = 0, + REC_TXWD, + REC_RXWD, + REC_WP_RCC, + REC_RX_MAP, + REC_RX_UNMAP, + REC_RX_AMPDU, +}; + +struct record_txbd { + u32 bd_len; + u8 bd_buf[MAX_TXBD_SIZE]; +}; + +struct record_txwd { + u32 wp_seq; + u32 wd_len; + u8 wd_buf[MAX_TXWD_SIZE]; +}; + +struct record_rxwd { + u32 wd_len; + u8 wd_buf[MAX_RXWD_SIZE]; +}; + +struct record_pci { + u32 map_len; + void *virtAddr; + void* phyAddrL; + void* phyAddrH; +}; + +struct record_wp_rcc { + u32 wp_seq; +}; + +struct phl_logs { + u32 txCnt_bd; + u32 txCnt_wd; + u32 txCnt_recycle; + + struct record_txbd txBd[CORE_LOG_NUM]; + struct record_txwd txWd[CORE_LOG_NUM]; + struct record_wp_rcc wpRecycle[CORE_LOG_NUM]; + + u32 rxCnt_map; + u32 rxSize_map; + u32 rxCnt_unmap; + u32 rxSize_unmap; + struct record_pci rxPciMap[CORE_LOG_NUM]; + struct record_pci rxPciUnmap[CORE_LOG_NUM]; + + u32 rxCnt_wd; + struct record_rxwd rxWd[CORE_LOG_NUM]; + + u32 rxCnt_ampdu; + u32 rxAmpdu[CORE_LOG_NUM]; +}; -#ifdef CONFIG_WAPI_SUPPORT - u8 WapiSupport; - RT_WAPI_T wapiInfo; #endif -#ifdef CONFIG_RTW_REPEATER_SON - u8 rtw_rson_scanstage; +enum _DIS_TURBO_EDCA { + EN_TURBO = 0, + DIS_TURBO, + DIS_TURBO_USE_MANUAL, +}; + +struct _ADAPTER { + int pid[3];/*process id from UI, 0:wpa_supplicant, 1:hostapd, 2:dhcpcd*/ + + /*extend to support multi interface*/ + u8 iface_id; + u8 isprimary; /* is primary adapter or not */ + /* notes: + ** if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER + ** if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER + ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/ + u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/ + u8 hw_port; /*interface port type, it depends on HW port */ + + u8 mac_addr[ETH_ALEN]; + /*CONFIG_PHL_ARCH*/ + struct rtw_wifi_role_t *phl_role; + ATOMIC_T need_tsf_sync_done; + +#ifdef CONFIG_HWSIM + int bup_hwsim; #endif -#ifdef CONFIG_WFD - struct wifi_display_info wfd_info; -#endif /* CONFIG_WFD */ + u8 netif_up; + + u8 registered; + u8 ndev_unregistering; + + + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct xmit_priv xmitpriv; + struct recv_info recvinfo;/*rssi*/ + struct sta_priv stapriv; + struct security_priv securitypriv; + _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */ + struct registry_priv registrypriv; + + #ifdef CONFIG_RTW_80211K + struct rm_priv rmpriv; + #endif + + #ifdef CONFIG_MP_INCLUDED + struct mp_priv mppriv; + #endif + + #ifdef CONFIG_AP_MODE + struct hostapd_priv *phostapdpriv; + u8 bmc_tx_rate; + #ifdef CONFIG_AP_CMD_DISPR + struct ap_cmd_dispr_priv *apcmd_dipsr_priv; + u32 ap_start_cmd_token; + u32 ap_stop_cmd_token; + u8 ap_start_cmd_state; + u8 ap_stop_cmd_state; + #endif + #if CONFIG_RTW_AP_DATA_BMC_TO_UC + u8 b2u_flags_ap_src; + u8 b2u_flags_ap_fwd; + #endif + #endif/*CONFIG_AP_MODE*/ -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - struct bt_coex_info coex_info; -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ + u32 setband; + ATOMIC_T bandskip; - ERROR_CODE LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */ + #ifdef CONFIG_P2P + struct wifidirect_info wdinfo; + #endif /* CONFIG_P2P */ - void *HalData; - u32 hal_data_sz; - struct hal_ops hal_func; + #ifdef CONFIG_TDLS + struct tdls_info tdlsinfo; + #endif /* CONFIG_TDLS */ - u32 IsrContent; - u32 ImrContent; + #ifdef CONFIG_WFD + struct wifi_display_info wfd_info; + #endif /* CONFIG_WFD */ - u8 EepromAddressSize; - u8 bDriverIsGoingToUnload; - u8 init_adpt_in_progress; - u8 bHaltInProgress; -#ifdef CONFIG_GPIO_API + #ifdef CONFIG_RTW_NAPI + struct napi_struct napi; + u8 napi_state; + #endif + + #ifdef CONFIG_GPIO_API u8 pre_gpio_pin; struct gpio_int_priv { u8 interrupt_mode; u8 interrupt_enable_mask; void (*callback[8])(u8 level); } gpiointpriv; -#endif + #endif + + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ _thread_hdl_ cmdThread; -#ifdef CONFIG_EVENT_THREAD_MODE - _thread_hdl_ evtThread; -#endif -#ifdef CONFIG_XMIT_THREAD_MODE + #endif + + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ _thread_hdl_ xmitThread; -#endif -#ifdef CONFIG_RECV_THREAD_MODE + #endif + #ifdef CONFIG_RECV_THREAD_MODE _thread_hdl_ recvThread; -#endif - u8 registered; + #endif - void (*intf_start)(_adapter *adapter); - void (*intf_stop)(_adapter *adapter); + #ifdef PLATFORM_LINUX + #ifdef CONFIG_IOCTL_CFG80211 + struct cfg80211_roch_info cfg80211_rochinfo; + #endif /* CONFIG_IOCTL_CFG80211 */ -#ifdef PLATFORM_LINUX _nic_hdl pnetdev; char old_ifname[IFNAMSIZ]; - u8 ndev_unregistering; - int bup; + + /* used by rtw_rereg_nd_name related function */ + struct rereg_nd_name_data { + _nic_hdl old_pnetdev; + char old_ifname[IFNAMSIZ]; + u8 old_ips_mode; + u8 old_bRegUseLed; + } rereg_nd_name_priv; + struct net_device_stats stats; struct iw_statistics iwstats; struct proc_dir_entry *dir_dev;/* for proc directory */ struct proc_dir_entry *dir_odm; -#ifdef CONFIG_MCC_MODE - struct proc_dir_entry *dir_mcc; -#endif /* CONFIG_MCC_MODE */ - -#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_IOCTL_CFG80211 struct wireless_dev *rtw_wdev; struct rtw_wdev_priv wdev_data; -#if !defined(RTW_SINGLE_WIPHY) - struct wiphy *wiphy; -#endif + #endif /* CONFIG_IOCTL_CFG80211 */ -#endif /* CONFIG_IOCTL_CFG80211 */ + #endif /* PLATFORM_LINUX */ -#ifdef CONFIG_PLATFORM_CMAP_INTFS - void *cmap_bss_status_evt; - u32 cmap_bss_status_evt_len; - u8 cmap_unassoc_sta_measure_en; -#endif + #ifdef CONFIG_TX_AMSDU + u8 tx_amsdu; + u16 tx_amsdu_rate; + #endif -#endif /* PLATFORM_LINUX */ + #ifdef CONFIG_RTW_WDS + bool use_wds; /* for STA, AP mode */ -#ifdef PLATFORM_FREEBSD - _nic_hdl pifp; - int bup; - _lock glock; -#endif /* PLATFORM_FREEBSD */ - u8 mac_addr[ETH_ALEN]; - int net_closed; + /* for STA mode */ + struct rtw_wds_gptr_table *wds_gpt_records; + ATOMIC_T wds_gpt_record_num; - u8 netif_up; + /* for AP mode */ + #ifdef CONFIG_AP_MODE + struct rtw_wds_table *wds_paths; + ATOMIC_T wds_path_num; + #endif + #endif /* CONFIG_RTW_WDS */ - u8 bLinkInfoDump; - /* Added by Albert 2012/10/26 */ - /* The driver will show up the desired channel number when this flag is 1. */ - u8 bNotifyChannelChange; - u8 bsta_tp_dump; -#ifdef CONFIG_P2P - /* Added by Albert 2012/12/06 */ - /* The driver will show the current P2P status when the upper application reads it. */ - u8 bShowGetP2PState; -#endif + #ifdef CONFIG_RTW_MULTI_AP + u8 multi_ap; + u8 ch_util_threshold; + #endif - u8 isprimary; /* is primary adapter or not */ - /* notes: - ** if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER - ** if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER - ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/ - u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/ - u8 hw_port; /*interface port type, it depends on HW port */ + #ifdef CONFIG_RTW_MESH + struct rtw_mesh_cfg mesh_cfg; + struct rtw_mesh_info mesh_info; + _timer mesh_path_timer; + _timer mesh_path_root_timer; + _timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */ + _workitem mesh_work; + unsigned long wrkq_flags; + #endif /* CONFIG_RTW_MESH */ - #ifdef CONFIG_CLIENT_PORT_CFG - u8 client_id; - u8 client_port; - #endif - /*struct tsf_info tsf;*//*reserve define for 8814B*/ + #ifdef CONFIG_RTW_TOKEN_BASED_XMIT + ATOMIC_T tbtx_tx_pause; + ATOMIC_T tbtx_remove_tx_pause; + u8 tbtx_capability; + u32 tbtx_duration; + #endif /* CONFIG_RTW_TOKEN_BASED_XMIT */ - /*extend to support multi interface*/ - u8 iface_id; + #ifdef CONFIG_WAPI_SUPPORT + u8 WapiSupport; + RT_WAPI_T wapiInfo; + #endif -#ifdef CONFIG_BR_EXT - _lock br_ext_lock; + #ifdef CONFIG_BR_EXT + _lock br_ext_lock; /* unsigned int macclone_completed; */ struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; int pppoe_connection_in_progress; @@ -1797,36 +1715,48 @@ struct _ADAPTER { unsigned char br_mac[MACADDRLEN]; unsigned char br_ip[4]; - struct br_ext_info ethBrExtInfo; -#endif /* CONFIG_BR_EXT */ + struct br_ext_info ethBrExtInfo; + #endif /* CONFIG_BR_EXT */ -#ifdef CONFIG_MAC_LOOPBACK_DRIVER + #if 0 /*#ifdef CONFIG_MAC_LOOPBACK_DRIVER*/ PLOOPBACKDATA ploopback; -#endif -#ifdef CONFIG_AP_MODE - u8 bmc_tx_rate; - #if CONFIG_RTW_AP_DATA_BMC_TO_UC - u8 b2u_flags_ap_src; - u8 b2u_flags_ap_fwd; #endif -#endif + + #ifdef PLATFORM_FREEBSD + _nic_hdl pifp; + _lock glock; + #endif /* PLATFORM_FREEBSD */ /* for debug purpose */ - u8 fix_rate; +#define NO_FIX_RATE 0xFFFF +#define GET_FIX_RATE(v) ((v) & 0x0FFF) +#define GET_FIX_RATE_SGI(v) (((v) & 0x7000) >> 12) + u16 fix_rate; +#define NO_FIX_BW 0xFF u8 fix_bw; - u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */ + u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xffff */ u8 power_offset; u8 driver_tx_bw_mode; u8 rsvd_page_offset; u8 rsvd_page_num; u8 ch_clm_ratio; u8 ch_nhm_ratio; -#ifdef CONFIG_SUPPORT_FIFO_DUMP + #ifdef CONFIG_SUPPORT_FIFO_DUMP u8 fifo_sel; u32 fifo_addr; u32 fifo_size; -#endif + #endif + u8 bLinkInfoDump; + /* Added by Albert 2012/10/26 */ + /* The driver will show up the desired channel number when this flag is 1. */ + u8 bNotifyChannelChange; + u8 bsta_tp_dump; + #ifdef CONFIG_P2P + /* Added by Albert 2012/12/06 */ + /* The driver will show the current P2P status when the upper application reads it. */ + u8 bShowGetP2PState; + #endif u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */ u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */ @@ -1834,78 +1764,87 @@ struct _ADAPTER { u8 driver_rx_ampdu_spacing; /* driver control Rx AMPDU Density */ u8 fix_rx_ampdu_accept; u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */ -#ifdef CONFIG_TX_AMSDU - u8 tx_amsdu; - u16 tx_amsdu_rate; -#endif u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/ -#ifdef DBG_RX_COUNTER_DUMP + + #ifdef DBG_RX_COUNTER_DUMP u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/ u32 drv_rx_cnt_ok; u32 drv_rx_cnt_crcerror; u32 drv_rx_cnt_drop; -#endif + #endif -#ifdef CONFIG_DBG_COUNTER + #ifdef CONFIG_DBG_COUNTER struct rx_logs rx_logs; struct tx_logs tx_logs; struct int_logs int_logs; -#endif - -#ifdef CONFIG_MCC_MODE - struct mcc_adapter_priv mcc_adapterpriv; -#endif /* CONFIG_MCC_MODE */ - -#ifdef CONFIG_RTW_WDS - bool use_wds; /* for STA, AP mode */ - - /* for STA mode */ - struct rtw_wds_gptr_table *wds_gpt_records; - ATOMIC_T wds_gpt_record_num; - - /* for AP mode */ - #ifdef CONFIG_AP_MODE - struct rtw_wds_table *wds_paths; - ATOMIC_T wds_path_num; #endif -#endif /* CONFIG_RTW_WDS */ - -#ifdef CONFIG_RTW_MULTI_AP - u8 multi_ap; - u8 ch_util_threshold; -#endif -#ifdef CONFIG_RTW_MESH - struct rtw_mesh_cfg mesh_cfg; - struct rtw_mesh_info mesh_info; - _timer mesh_path_timer; - _timer mesh_path_root_timer; - _timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */ - _workitem mesh_work; - unsigned long wrkq_flags; -#endif /* CONFIG_RTW_MESH */ - -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT - ATOMIC_T tbtx_tx_pause; - ATOMIC_T tbtx_remove_tx_pause; - u8 tbtx_capability; - u32 tbtx_duration; -#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */ - -#ifdef RTW_SIMPLE_CONFIG - u8 rtw_simple_config; +#ifdef RTW_PHL_DBG_CMD + + struct core_logs core_logs; + struct phl_logs phl_logs; + + u32 txForce_enable; + u32 txForce_rate; + u32 txForce_agg; + u32 txForce_aggnum; + u32 txForce_gi; + + u32 sniffer_enable; + u8 record_enable; +#endif +#ifdef RTW_PHL_TX + u8 *pxmit_txreq_buf; + _queue free_txreq_queue; + u32 free_txreq_cnt; + u32 txreq_full_cnt; + + u32 tx_ring_idx; + u8 *tx_pool_ring [MAX_TX_RING_NUM]; +#endif +#ifdef CONFIG_RTW_CORE_RXSC + u8 enable_rxsc; +#endif +#ifdef DBG_CONFIG_CMD_DISP + enum phl_cmd_type cmd_type; + u32 cmd_timeout; +#endif + u8 dis_turboedca;/* 1: disable turboedca, + 2. disable turboedca,and setting EDCA parameter based on the input parameter*/ + u32 edca_param_mode; + u32 last_edca; + +#ifdef CONFIG_STA_CMD_DISPR + _lock connect_st_lock; + u8 connect_state; +#define CONNECT_ST_NOT_READY 0 +#define CONNECT_ST_IDLE 1 +#define CONNECT_ST_REQUESTING 2 +#define CONNECT_ST_ACQUIRED 3 + bool connect_abort; + struct phl_cmd_token_req connect_req; + u32 connect_token; + + _lock disconnect_lock; + struct phl_cmd_token_req disconnect_req; + u32 disconnect_token; + struct cmd_obj *discon_cmd; +#endif /* CONFIG_STA_CMD_DISPR */ + +#ifdef CONFIG_ECSA_PHL + struct core_ecsa_info ecsa_info; #endif }; #define adapter_to_dvobj(adapter) ((adapter)->dvobj) #define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter))) #define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter))) +#ifdef CONFIG_WOWLAN +#define adapter_to_wowlan(adapter) dvobj_to_wowlan(adapter_to_dvobj((adapter))) +#endif /* CONFIG_WOWLAN */ + #define adapter_wdev_data(adapter) (&((adapter)->wdev_data)) -#if defined(RTW_SINGLE_WIPHY) #define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter)) -#else -#define adapter_to_wiphy(adapter) ((adapter)->wiphy) -#endif #define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) #define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter))) @@ -1921,124 +1860,114 @@ struct _ADAPTER { #endif #define adapter_mac_addr(adapter) (adapter->mac_addr) -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) + +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI #define adapter_pno_mac_addr(adapter) \ ((adapter_wdev_data(adapter))->pno_mac_addr) #endif #define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set) -#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv) -#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo) +#define mlme_to_adapter(mlme) container_of((mlme), _adapter, mlmepriv) +#define tdls_info_to_adapter(tdls) container_of((tdls), _adapter, tdlsinfo) -#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type) -#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType) -#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type) +#define rtw_get_chip_id(adapter) (((_adapter *)adapter)->dvobj->chip_id) +#define rtw_get_intf_type(adapter) (((_adapter *)adapter)->dvobj->interface_type) -#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums) +#define rtw_get_mi_nums(adapter) (((_adapter *)adapter)->dvobj->iface_nums) -static inline void rtw_set_surprise_removed(_adapter *padapter) +static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj) { - dev_set_surprise_removed(adapter_to_dvobj(padapter)); + ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE); + if (dvobj->phl) + rtw_phl_dev_terminate_ntf(dvobj->phl); } -static inline void rtw_clr_surprise_removed(_adapter *padapter) +static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj) { - dev_clr_surprise_removed(adapter_to_dvobj(padapter)); + ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE); + if (dvobj->phl_com) + CLEAR_STATUS_FLAG(dvobj->phl_com->dev_state, RTW_DEV_SURPRISE_REMOVAL); } -static inline void rtw_set_drv_stopped(_adapter *padapter) +static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj) { - dev_set_drv_stopped(adapter_to_dvobj(padapter)); + ATOMIC_SET(&dvobj->bDriverStopped, _TRUE); } -static inline void rtw_clr_drv_stopped(_adapter *padapter) +static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj) { - dev_clr_drv_stopped(adapter_to_dvobj(padapter)); + ATOMIC_SET(&dvobj->bDriverStopped, _FALSE); +} +static inline void dev_set_hw_start(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->hw_start, _TRUE); +} +static inline void dev_clr_hw_start(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->hw_start, _FALSE); } -#define rtw_is_surprise_removed(padapter) (dev_is_surprise_removed(adapter_to_dvobj(padapter))) -#define rtw_is_drv_stopped(padapter) (dev_is_drv_stopped(adapter_to_dvobj(padapter))) +#define dev_is_surprise_removed(dvobj) (ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE) +#define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE) +#define dev_is_hw_start(dvobj) (ATOMIC_READ(&dvobj->hw_start) == _TRUE) /* * Function disabled. * */ -#define DF_TX_BIT BIT0 /*write_port_cancel*/ -#define DF_RX_BIT BIT1 /*read_port_cancel*/ +#define DF_TX_BIT BIT0 /*rtw_usb_write_port_cancel*/ +#define DF_RX_BIT BIT1 /*rtw_usb_read_port_cancel*/ #define DF_IO_BIT BIT2 -/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */ -/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */ -__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit) +/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&dvobj->disable_func, (func))) */ +/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&dvobj->disable_func, (func))) */ +__inline static void RTW_DISABLE_FUNC(struct dvobj_priv *dvobj, int func_bit) { - int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + int df = ATOMIC_READ(&dvobj->disable_func); df |= func_bit; - ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); + ATOMIC_SET(&dvobj->disable_func, df); } -__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit) +__inline static void RTW_ENABLE_FUNC(struct dvobj_priv *dvobj, int func_bit) { - int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + int df = ATOMIC_READ(&dvobj->disable_func); df &= ~(func_bit); - ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); + ATOMIC_SET(&dvobj->disable_func, df); } -#define RTW_CANNOT_RUN(padapter) \ - (rtw_is_surprise_removed(padapter) || \ - rtw_is_drv_stopped(padapter)) - -#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit)) +#define RTW_CANNOT_RUN(dvobj) \ + (dev_is_surprise_removed(dvobj) || \ + dev_is_drv_stopped(dvobj)) -#define RTW_CANNOT_IO(padapter) \ - (rtw_is_surprise_removed(padapter) || \ - RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT)) +#define RTW_IS_FUNC_DISABLED(dvobj, func_bit) \ + (ATOMIC_READ(&dvobj->disable_func) & (func_bit)) -#define RTW_CANNOT_RX(padapter) \ - (RTW_CANNOT_RUN(padapter) || \ - RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT)) +#define RTW_CANNOT_IO(dvobj) \ + (dev_is_surprise_removed(dvobj) || \ + RTW_IS_FUNC_DISABLED((dvobj), DF_IO_BIT)) -#define RTW_CANNOT_TX(padapter) \ - (RTW_CANNOT_RUN(padapter) || \ - RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT)) +#define RTW_CANNOT_RX(dvobj) \ + (RTW_CANNOT_RUN(dvobj) || \ + RTW_IS_FUNC_DISABLED((dvobj), DF_RX_BIT)) -#ifdef CONFIG_PNO_SUPPORT -int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left); -int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, - int pno_time, int pno_repeat, int pno_freq_expo_max); -#ifdef CONFIG_PNO_SET_DEBUG - void rtw_dev_pno_debug(struct net_device *net); -#endif /* CONFIG_PNO_SET_DEBUG */ -#endif /* CONFIG_PNO_SUPPORT */ +#define RTW_CANNOT_TX(dvobj) \ + (RTW_CANNOT_RUN(dvobj) || \ + RTW_IS_FUNC_DISABLED((dvobj), DF_TX_BIT)) -int rtw_suspend_free_assoc_resource(_adapter *padapter); -#ifdef CONFIG_WOWLAN - int rtw_suspend_wow(_adapter *padapter); - int rtw_resume_process_wow(_adapter *padapter); -#endif /* HCI Related header file */ #ifdef CONFIG_USB_HCI - #include #include - #include #endif #ifdef CONFIG_SDIO_HCI - #include #include - #include #endif #ifdef CONFIG_GSPI_HCI - #include #include - #include #endif #ifdef CONFIG_PCI_HCI - #include #include - #include #endif +#include -// OpenHD crda workaround -int get_openhd_override_channel(void); -int get_openhd_override_tx_power_mbm(void); #endif /* __DRV_TYPES_H__ */ diff --git a/include/drv_types_pci.h b/include/drv_types_pci.h index 2c550ec..c824372 100644 --- a/include/drv_types_pci.h +++ b/include/drv_types_pci.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -57,4 +57,40 @@ typedef struct _RT_ISR_CONTENT { }; } RT_ISR_CONTENT, *PRT_ISR_CONTENT; +typedef struct pci_data { +#ifdef PLATFORM_LINUX + struct pci_dev *ppcidev; + + /* PCI MEM map */ + unsigned long pci_mem_end; /* shared mem end */ + unsigned long pci_mem_start; /* shared mem start */ + + /* PCI IO map */ + unsigned long pci_base_addr; /* device I/O address */ + + #ifdef RTK_129X_PLATFORM + unsigned long ctrl_start; + /* PCI MASK addr */ + unsigned long mask_addr; + + /* PCI TRANSLATE addr */ + unsigned long tran_addr; + + _lock io_reg_lock; + #endif + + /* PciBridge */ + struct pci_priv pcipriv; + + u8 irq_alloc; + unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */ + u16 irqline; + u8 irq_enabled; + RT_ISR_CONTENT isr_content; + _lock irq_th_lock; + + u8 bdma64; +#endif/* PLATFORM_LINUX */ +} PCI_DATA, *PPCI_DATA; + #endif diff --git a/include/drv_types_sdio.h b/include/drv_types_sdio.h index 29006d9..a0a6b5f 100644 --- a/include/drv_types_sdio.h +++ b/include/drv_types_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -39,15 +39,19 @@ typedef struct sdio_data { u8 tx_block_mode; u8 rx_block_mode; u32 block_transfer_len; + u16 max_byte_size; /* MAX size for cmd53 byte mode */ + u8 irq_alloc; #ifdef PLATFORM_LINUX struct mmc_card *card; - struct sdio_func *func; + struct sdio_func *func; + u8 *tmpbuf; /* buffer for register access */ + u8 tmpbuf_sz; +#endif _thread_hdl_ sys_sdio_irq_thd; unsigned int clock; unsigned int timing; u8 sd3_bus_mode; -#endif #ifdef DBG_SDIO #ifdef PLATFORM_LINUX @@ -79,16 +83,17 @@ typedef struct sdio_data { #endif /* DBG_SDIO */ } SDIO_DATA, *PSDIO_DATA; -#define dvobj_to_sdio_func(d) ((d)->intf_data.func) +#define dvobj_to_sdio_func(d) ((d)->sdio_data.func) -#define RTW_SDIO_ADDR_CMD52_BIT (1<<17) +#define RTW_SDIO_ADDR_CMD52_BIT (1<<17) #define RTW_SDIO_ADDR_CMD52_GEN(a) (a | RTW_SDIO_ADDR_CMD52_BIT) #define RTW_SDIO_ADDR_CMD52_CLR(a) (a&~RTW_SDIO_ADDR_CMD52_BIT) #define RTW_SDIO_ADDR_CMD52_CHK(a) (a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0) #define RTW_SDIO_ADDR_F0_BIT (1<<18) -#define RTW_SDIO_ADDR_F0_GEN(a) (a | RTW_SDIO_ADDR_F0_BIT) -#define RTW_SDIO_ADDR_F0_CLR(a) (a&~RTW_SDIO_ADDR_F0_BIT) -#define RTW_SDIO_ADDR_F0_CHK(a) (a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0) +#define RTW_SDIO_ADDR_F0_GEN(a) (a | RTW_SDIO_ADDR_F0_BIT) +#define RTW_SDIO_ADDR_F0_CLR(a) (a&~RTW_SDIO_ADDR_F0_BIT) +#define RTW_SDIO_ADDR_F0_CHK(a) (a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0) + #endif diff --git a/include/drv_types_usb.h b/include/drv_types_usb.h new file mode 100644 index 0000000..3fe3bd1 --- /dev/null +++ b/include/drv_types_usb.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __DRV_TYPES_USB_H__ +#define __DRV_TYPES_USB_H__ + +/*FOR 8852AU*/ +#define MAX_ENDPOINT_NUM 9 /* 2 x Bulk-IN + 7 x Bulk-OUT */ +#define MAX_BULKOUT_NUM 7 +#define MAX_BULKIN_NUM 2 /*EP4 for Bulk-IN, EP8 for Bulk-IN interrupt or Bulk-INT*/ + +typedef struct usb_data { + u8 usb_intf_start; + + u8 usb_speed; /* 1.1, 2.0 or 3.0 */ + u16 usb_bulkout_size; + u8 nr_endpoint; /*MAX_ENDPOINT_NUM*/ + + /* Bulk In , Out Pipe information */ + int RtInPipe[MAX_BULKIN_NUM]; + u8 inpipe_type[MAX_BULKIN_NUM]; + u8 RtNumInPipes; + int RtOutPipe[MAX_BULKOUT_NUM]; + u8 RtNumOutPipes; + +#ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _mutex usb_vendor_req_mutex; +#endif + +#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + u8 *usb_alloc_vendor_req_buf; + u8 *usb_vendor_req_buf; +#endif + +#ifdef PLATFORM_LINUX + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +#endif/* PLATFORM_LINUX */ +} USB_DATA, *PUSB_DATA; +#endif /*__DRV_TYPES_USB_H__*/ diff --git a/include/ethernet.h b/include/ethernet.h index ef518cc..141512e 100644 --- a/include/ethernet.h +++ b/include/ethernet.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/gspi_hal.h b/include/gspi_hal.h index 6da0f07..6b0561c 100644 --- a/include/gspi_hal.h +++ b/include/gspi_hal.h @@ -16,15 +16,6 @@ #define __GSPI_HAL_H__ -void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr); -u8 rtw_set_hal_ops(_adapter *padapter); - -#ifdef CONFIG_RTL8188E - void rtl8188es_set_hal_ops(PADAPTER padapter); -#endif - -#ifdef CONFIG_RTL8723B - void rtl8723bs_set_hal_ops(PADAPTER padapter); -#endif +void spi_int_dpc(_adapter *padapter, u32 sdio_hisr); #endif /* __GSPI_HAL_H__ */ diff --git a/include/gspi_ops.h b/include/gspi_ops.h index bcfaad2..92d0413 100644 --- a/include/gspi_ops.h +++ b/include/gspi_ops.h @@ -141,40 +141,4 @@ struct spi_more_data { unsigned long len; }; -#ifdef CONFIG_RTL8188E - void rtl8188es_set_hal_ops(PADAPTER padapter); - #define set_hal_ops rtl8188es_set_hal_ops -#endif -extern void spi_set_chip_endian(PADAPTER padapter); -extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big); -extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops); -extern void spi_set_chip_endian(PADAPTER padapter); -extern void InitInterrupt8723ASdio(PADAPTER padapter); -extern void InitSysInterrupt8723ASdio(PADAPTER padapter); -extern void EnableInterrupt8723ASdio(PADAPTER padapter); -extern void DisableInterrupt8723ASdio(PADAPTER padapter); -extern void spi_int_hdl(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); -#ifdef CONFIG_RTL8723B - extern void InitInterrupt8723BSdio(PADAPTER padapter); - extern void InitSysInterrupt8723BSdio(PADAPTER padapter); - extern void EnableInterrupt8723BSdio(PADAPTER padapter); - extern void DisableInterrupt8723BSdio(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); -#endif - -#ifdef CONFIG_RTL8188E - extern void InitInterrupt8188EGspi(PADAPTER padapter); - extern void EnableInterrupt8188EGspi(PADAPTER padapter); - extern void DisableInterrupt8188EGspi(PADAPTER padapter); - extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); - extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter); - extern void ClearInterrupt8188EGspi(PADAPTER padapter); - extern u8 CheckIPSStatus(PADAPTER padapter); -#endif /* CONFIG_RTL8188E */ -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern u8 RecvOnePkt(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ - #endif /* __GSPI_OPS_H__ */ diff --git a/include/ieee80211.h b/include/ieee80211.h index 62d0f66..4414857 100644 --- a/include/ieee80211.h +++ b/include/ieee80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,6 +16,8 @@ #define __IEEE80211_H #define MGMT_QUEUE_NUM 5 +#define MAX_RF_PATH 4 +#define RF_PATH_MAX MAX_RF_PATH #define ETH_ALEN 6 #define ETH_TYPE_LEN 2 @@ -26,7 +28,7 @@ #ifdef CONFIG_AP_MODE -#define RTL_IOCTL_HOSTAPD (SIOCDEVPRIVATE + 2) +#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) /* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ enum { @@ -55,7 +57,6 @@ enum { RTL871X_HOSTAPD_ACL_ADD_STA = 22, RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, }; -#endif /* CONFIG_AP_MODE */ /* STA flags */ #define WLAN_STA_AUTH BIT(0) @@ -73,11 +74,14 @@ enum { #define WLAN_STA_WPS BIT(12) #define WLAN_STA_MAYBE_WPS BIT(13) #define WLAN_STA_VHT BIT(14) -#define WLAN_STA_WDS BIT(15) -#define WLAN_STA_MULTI_AP BIT(16) -#define WLAN_STA_AMSDU_DISABLE BIT(17) +#define WLAN_STA_HE BIT(15) +#define WLAN_STA_WDS BIT(16) +#define WLAN_STA_MULTI_AP BIT(17) +#define WLAN_STA_AMSDU_DISABLE BIT(18) #define WLAN_STA_NONERP BIT(31) +#endif + #define IEEE_CMD_SET_WPA_PARAM 1 #define IEEE_CMD_SET_WPA_IE 2 #define IEEE_CMD_SET_ENCRYPTION 3 @@ -141,6 +145,7 @@ extern u8 WPA_CIPHER_SUITE_WEP104[]; #define RSN_HEADER_LEN 4 #define RSN_SELECTOR_LEN 4 +#define RSN_PMKID_LEN 16 extern u16 RSN_VERSION_BSD; extern u8 RSN_CIPHER_SUITE_NONE[]; @@ -236,91 +241,15 @@ struct wpa_eapol_key { /* followed by key_data_length bytes of key_data */ }; -typedef enum _RATEID_IDX_ { - RATEID_IDX_BGN_40M_2SS = 0, - RATEID_IDX_BGN_40M_1SS = 1, - RATEID_IDX_BGN_20M_2SS_BN = 2, - RATEID_IDX_BGN_20M_1SS_BN = 3, - RATEID_IDX_GN_N2SS = 4, - RATEID_IDX_GN_N1SS = 5, - RATEID_IDX_BG = 6, - RATEID_IDX_G = 7, - RATEID_IDX_B = 8, - RATEID_IDX_VHT_2SS = 9, - RATEID_IDX_VHT_1SS = 10, - RATEID_IDX_MIX1 = 11, - RATEID_IDX_MIX2 = 12, - RATEID_IDX_VHT_3SS = 13, - RATEID_IDX_BGN_3SS = 14, - RATEID_IDX_BGN_4SS = 15, - RATEID_IDX_VHT_4SS = 16, -} RATEID_IDX, *PRATEID_IDX; - -typedef enum _RATR_TABLE_MODE { - RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ - RATR_INX_WIRELESS_NG = 1, /* GN or N */ - RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ - RATR_INX_WIRELESS_N = 3, - RATR_INX_WIRELESS_GB = 4, - RATR_INX_WIRELESS_G = 5, - RATR_INX_WIRELESS_B = 6, - RATR_INX_WIRELESS_MC = 7, - RATR_INX_WIRELESS_AC_N = 8, -} RATR_TABLE_MODE, *PRATR_TABLE_MODE; - - -enum NETWORK_TYPE { - WIRELESS_INVALID = 0, - /* Sub-Element */ - WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */ - WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */ - WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */ - WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */ - WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */ - WIRELESS_AUTO = BIT(5), - WIRELESS_11AC = BIT(6), - - /* Combination */ - /* Type for current wireless mode */ - WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ - WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ - WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ - WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ - WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ - WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC), - WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC), - - - /* Type for registry default wireless mode */ - WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ - WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), - WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), - WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC), - WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC), -}; - -#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G -#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G - -#define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A))) - -#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) -#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) - -#define IsEnableHWCCK(NetType) IsSupported24G(NetType) -#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) - -#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) -#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) -#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType) - -#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) -#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE) -#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE) - -#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) - - +#define is_legacy_only(net_type) ((net_type) == ((net_type) & (WLAN_MD_11BG | WLAN_MD_11A))) +#define is_supported_24g(band_type) ((band_type) & BAND_CAP_2G ? _TRUE : _FALSE) +#define is_supported_5g(band_type) ((band_type) & BAND_CAP_5G ? _TRUE : _FALSE) +#define is_supported_6g(band_type) ((band_type) & BAND_CAP_6G ? _TRUE : _FALSE) +#define is_supported_tx_cck(net_type) ((net_type) & (WLAN_MD_11B) ? _TRUE : _FALSE) +#define is_suuported_tx_ofdm(net_type) ((net_type) & (WLAN_MD_11G | WLAN_MD_11A) ? _TRUE : _FALSE) +#define is_supported_ht(net_type) ((net_type) & (WLAN_MD_11N) ? _TRUE : _FALSE) +#define is_supported_vht(net_type) ((net_type) & (WLAN_MD_11AC) ? _TRUE : _FALSE) +#define is_supported_he(net_type) ((net_type) & (WLAN_MD_11AX) ? _TRUE : _FALSE) @@ -632,6 +561,9 @@ struct ieee80211_snap_hdr { #endif #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) +#ifdef CONFIG_CORE_TXSC +#define WLHDR_SIZE sizeof(struct rtw_ieee80211_hdr) +#endif #define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) #define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) @@ -644,6 +576,7 @@ struct ieee80211_snap_hdr { /* Authentication algorithms */ #define WLAN_AUTH_OPEN 0 #define WLAN_AUTH_SHARED_KEY 1 +#define WLAN_AUTH_FT 2 #define WLAN_AUTH_SAE 3 #define WLAN_AUTH_CHALLENGE_LEN 128 @@ -690,7 +623,7 @@ struct ieee80211_snap_hdr { #define WLAN_REASON_MESH_MAX_PEERS 53 #define WLAN_REASON_MESH_CONFIG 54 #define WLAN_REASON_MESH_CLOSE 55 -#define WLAN_REASON_MESH_MAX_RETRIES 56 +#define WLAN_REASON_MESH_MAX_RETRIES 56 #define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57 #define WLAN_REASON_MESH_INVALID_GTK 58 #define WLAN_REASON_MESH_INCONSISTENT_PARAM 59 @@ -721,6 +654,7 @@ struct ieee80211_snap_hdr { #define WLAN_EID_CF_PARAMS 4 #define WLAN_EID_TIM 5 #define WLAN_EID_IBSS_PARAMS 6 +#define WLAN_EID_COUNTRY 7 #define WLAN_EID_CHALLENGE 16 /* EIDs defined by IEEE 802.11h - START */ #define WLAN_EID_PWR_CONSTRAINT 32 @@ -744,17 +678,21 @@ struct ieee80211_snap_hdr { #define WLAN_EID_RIC_DATA 57 #define WLAN_EID_HT_OPERATION 61 #define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 +#define WLAN_EID_MULTIPLE_BSSID 71 #define WLAN_EID_20_40_BSS_COEXISTENCE 72 #define WLAN_EID_20_40_BSS_INTOLERANT 73 #define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 #define WLAN_EID_MMIE 76 +#define WLAN_EID_NON_TX_BSSID_CAP 83 +#define WLAN_EID_MULTI_BSSID_IDX 85 #define WLAN_EID_MESH_CONFIG 113 #define WLAN_EID_MESH_ID 114 #define WLAN_EID_MPM 117 -#define WLAN_EID_RANN 126 -#define WLAN_EID_PREQ 130 -#define WLAN_EID_PREP 131 -#define WLAN_EID_PERR 132 +#define WLAN_EID_RANN 126 +#define WLAN_EID_EXT_CAP 127 +#define WLAN_EID_PREQ 130 +#define WLAN_EID_PREP 131 +#define WLAN_EID_PERR 132 #define WLAN_EID_AMPE 139 #define WLAN_EID_MIC 140 #define WLAN_EID_VENDOR_SPECIFIC 221 @@ -767,6 +705,13 @@ struct ieee80211_snap_hdr { #define WLAN_EID_EXTENSION 255 #define WLAN_EID_EXT_OWE_DH_PARAM 32 +/* EID Extension */ +#define WLAN_EID_EXTENSION_HE_CAPABILITY 35 +#define WLAN_EID_EXTENSION_HE_OPERATION 36 +#define WLAN_EID_EXTENSION_HE_MU_EDCA 38 + +#define WLAN_EID_EXT_CAP_MAX_LEN 10 + #define IEEE80211_MGMT_HDR_LEN 24 #define IEEE80211_DATA_HDR3_LEN 24 #define IEEE80211_DATA_HDR4_LEN 30 @@ -844,6 +789,10 @@ struct ieee80211_snap_hdr { #define IEEE80211_NUM_CCK_RATES 4 #define IEEE80211_OFDM_SHIFT_MASK_A 4 +enum subelement_of_multiple_bssid_id { + MBSSID_NONTRANSMITTED_BSSID_PROFILE_ID = 0, + MBSSID_VENDOR_SPECIFIC_ID = 221 +}; enum MGN_RATE { MGN_1M = 0x02, @@ -931,7 +880,55 @@ enum MGN_RATE { MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9, - MGN_UNKNOWN + MGN_HE1SS_MCS0 = 0xd0, + MGN_HE1SS_MCS1, + MGN_HE1SS_MCS2, + MGN_HE1SS_MCS3, + MGN_HE1SS_MCS4, + MGN_HE1SS_MCS5, + MGN_HE1SS_MCS6, + MGN_HE1SS_MCS7, + MGN_HE1SS_MCS8, + MGN_HE1SS_MCS9, + MGN_HE1SS_MCS10, + MGN_HE1SS_MCS11, + MGN_HE2SS_MCS0, + MGN_HE2SS_MCS1, + MGN_HE2SS_MCS2, + MGN_HE2SS_MCS3, + MGN_HE2SS_MCS4, + MGN_HE2SS_MCS5, + MGN_HE2SS_MCS6, + MGN_HE2SS_MCS7, + MGN_HE2SS_MCS8, + MGN_HE2SS_MCS9, + MGN_HE2SS_MCS10, + MGN_HE2SS_MCS11, + MGN_HE3SS_MCS0, + MGN_HE3SS_MCS1, + MGN_HE3SS_MCS2, + MGN_HE3SS_MCS3, + MGN_HE3SS_MCS4, + MGN_HE3SS_MCS5, + MGN_HE3SS_MCS6, + MGN_HE3SS_MCS7, + MGN_HE3SS_MCS8, + MGN_HE3SS_MCS9, + MGN_HE3SS_MCS10, + MGN_HE3SS_MCS11, + MGN_HE4SS_MCS0, + MGN_HE4SS_MCS1, + MGN_HE4SS_MCS2, + MGN_HE4SS_MCS3, + MGN_HE4SS_MCS4, + MGN_HE4SS_MCS5, + MGN_HE4SS_MCS6, + MGN_HE4SS_MCS7, + MGN_HE4SS_MCS8, + MGN_HE4SS_MCS9, + MGN_HE4SS_MCS10, + MGN_HE4SS_MCS11 = 0xff, + MGN_UNKNOWN = 0xcc }; #define IS_HT_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31) @@ -954,7 +951,92 @@ enum MGN_RATE { #define IS_3T_RATE(_rate) (IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate))) #define IS_4T_RATE(_rate) (IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate))) -const char *MGN_RATE_STR(enum MGN_RATE rate); +#define MGN_RATE_STR(_rate) \ + (_rate == MGN_1M) ? "CCK_1M" : \ + (_rate == MGN_2M) ? "CCK_2M" : \ + (_rate == MGN_5_5M) ? "CCK_5.5M" : \ + (_rate == MGN_11M) ? "CCK_11M" : \ + (_rate == MGN_6M) ? "OFDM_6M" : \ + (_rate == MGN_9M) ? "OFDM_9M" : \ + (_rate == MGN_12M) ? "OFDM_12M" : \ + (_rate == MGN_18M) ? "OFDM_18M" : \ + (_rate == MGN_24M) ? "OFDM_24M" : \ + (_rate == MGN_36M) ? "OFDM_36M" : \ + (_rate == MGN_48M) ? "OFDM_48M" : \ + (_rate == MGN_54M) ? "OFDM_54M" : \ + (_rate == MGN_MCS32) ? "MCS32" : \ + (_rate == MGN_MCS0) ? "MCS0" : \ + (_rate == MGN_MCS1) ? "MCS1" : \ + (_rate == MGN_MCS2) ? "MCS2" : \ + (_rate == MGN_MCS3) ? "MCS3" : \ + (_rate == MGN_MCS4) ? "MCS4" : \ + (_rate == MGN_MCS5) ? "MCS5" : \ + (_rate == MGN_MCS6) ? "MCS6" : \ + (_rate == MGN_MCS7) ? "MCS7" : \ + (_rate == MGN_MCS8) ? "MCS8" : \ + (_rate == MGN_MCS9) ? "MCS9" : \ + (_rate == MGN_MCS10) ? "MCS10" : \ + (_rate == MGN_MCS11) ? "MCS11" : \ + (_rate == MGN_MCS12) ? "MCS12" : \ + (_rate == MGN_MCS13) ? "MCS13" : \ + (_rate == MGN_MCS14) ? "MCS14" : \ + (_rate == MGN_MCS15) ? "MCS15" : \ + (_rate == MGN_MCS16) ? "MCS16" : \ + (_rate == MGN_MCS17) ? "MCS17" : \ + (_rate == MGN_MCS18) ? "MCS18" : \ + (_rate == MGN_MCS19) ? "MCS19" : \ + (_rate == MGN_MCS20) ? "MCS20" : \ + (_rate == MGN_MCS21) ? "MCS21" : \ + (_rate == MGN_MCS22) ? "MCS22" : \ + (_rate == MGN_MCS23) ? "MCS23" : \ + (_rate == MGN_MCS24) ? "MCS24" : \ + (_rate == MGN_MCS25) ? "MCS25" : \ + (_rate == MGN_MCS26) ? "MCS26" : \ + (_rate == MGN_MCS27) ? "MCS27" : \ + (_rate == MGN_MCS28) ? "MCS28" : \ + (_rate == MGN_MCS29) ? "MCS29" : \ + (_rate == MGN_MCS30) ? "MCS30" : \ + (_rate == MGN_MCS31) ? "MCS31" : \ + (_rate == MGN_VHT1SS_MCS0) ? "VHT1SMCS0" : \ + (_rate == MGN_VHT1SS_MCS1) ? "VHT1SMCS1" : \ + (_rate == MGN_VHT1SS_MCS2) ? "VHT1SMCS2" : \ + (_rate == MGN_VHT1SS_MCS3) ? "VHT1SMCS3" : \ + (_rate == MGN_VHT1SS_MCS4) ? "VHT1SMCS4" : \ + (_rate == MGN_VHT1SS_MCS5) ? "VHT1SMCS5" : \ + (_rate == MGN_VHT1SS_MCS6) ? "VHT1SMCS6" : \ + (_rate == MGN_VHT1SS_MCS7) ? "VHT1SMCS7" : \ + (_rate == MGN_VHT1SS_MCS8) ? "VHT1SMCS8" : \ + (_rate == MGN_VHT1SS_MCS9) ? "VHT1SMCS9" : \ + (_rate == MGN_VHT2SS_MCS0) ? "VHT2SMCS0" : \ + (_rate == MGN_VHT2SS_MCS1) ? "VHT2SMCS1" : \ + (_rate == MGN_VHT2SS_MCS2) ? "VHT2SMCS2" : \ + (_rate == MGN_VHT2SS_MCS3) ? "VHT2SMCS3" : \ + (_rate == MGN_VHT2SS_MCS4) ? "VHT2SMCS4" : \ + (_rate == MGN_VHT2SS_MCS5) ? "VHT2SMCS5" : \ + (_rate == MGN_VHT2SS_MCS6) ? "VHT2SMCS6" : \ + (_rate == MGN_VHT2SS_MCS7) ? "VHT2SMCS7" : \ + (_rate == MGN_VHT2SS_MCS8) ? "VHT2SMCS8" : \ + (_rate == MGN_VHT2SS_MCS9) ? "VHT2SMCS9" : \ + (_rate == MGN_VHT3SS_MCS0) ? "VHT3SMCS0" : \ + (_rate == MGN_VHT3SS_MCS1) ? "VHT3SMCS1" : \ + (_rate == MGN_VHT3SS_MCS2) ? "VHT3SMCS2" : \ + (_rate == MGN_VHT3SS_MCS3) ? "VHT3SMCS3" : \ + (_rate == MGN_VHT3SS_MCS4) ? "VHT3SMCS4" : \ + (_rate == MGN_VHT3SS_MCS5) ? "VHT3SMCS5" : \ + (_rate == MGN_VHT3SS_MCS6) ? "VHT3SMCS6" : \ + (_rate == MGN_VHT3SS_MCS7) ? "VHT3SMCS7" : \ + (_rate == MGN_VHT3SS_MCS8) ? "VHT3SMCS8" : \ + (_rate == MGN_VHT3SS_MCS9) ? "VHT3SMCS9" : \ + (_rate == MGN_VHT4SS_MCS0) ? "VHT4SMCS0" : \ + (_rate == MGN_VHT4SS_MCS1) ? "VHT4SMCS1" : \ + (_rate == MGN_VHT4SS_MCS2) ? "VHT4SMCS2" : \ + (_rate == MGN_VHT4SS_MCS3) ? "VHT4SMCS3" : \ + (_rate == MGN_VHT4SS_MCS4) ? "VHT4SMCS4" : \ + (_rate == MGN_VHT4SS_MCS5) ? "VHT4SMCS5" : \ + (_rate == MGN_VHT4SS_MCS6) ? "VHT4SMCS6" : \ + (_rate == MGN_VHT4SS_MCS7) ? "VHT4SMCS7" : \ + (_rate == MGN_VHT4SS_MCS8) ? "VHT4SMCS8" : \ + (_rate == MGN_VHT4SS_MCS9) ? "VHT4SMCS9" : "UNKNOWN" typedef enum _RATE_SECTION { CCK = 0, @@ -1047,51 +1129,6 @@ struct ieee80211_frag_entry { u8 dst_addr[ETH_ALEN]; }; -#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */ -struct ieee80211_stats { - uint tx_unicast_frames; - uint tx_multicast_frames; - uint tx_fragments; - uint tx_unicast_octets; - uint tx_multicast_octets; - uint tx_deferred_transmissions; - uint tx_single_retry_frames; - uint tx_multiple_retry_frames; - uint tx_retry_limit_exceeded; - uint tx_discards; - uint rx_unicast_frames; - uint rx_multicast_frames; - uint rx_fragments; - uint rx_unicast_octets; - uint rx_multicast_octets; - uint rx_fcs_errors; - uint rx_discards_no_buffer; - uint tx_discards_wrong_sa; - uint rx_discards_undecryptable; - uint rx_message_in_msg_fragments; - uint rx_message_in_bad_msg_fragments; -}; -#endif /* PLATFORM_FREEBSD */ -struct ieee80211_softmac_stats { - uint rx_ass_ok; - uint rx_ass_err; - uint rx_probe_rq; - uint tx_probe_rs; - uint tx_beacons; - uint rx_auth_rq; - uint rx_auth_rs_ok; - uint rx_auth_rs_err; - uint tx_auth_rq; - uint no_auth_rs; - uint no_ass_rs; - uint tx_ass_rq; - uint rx_ass_rq; - uint tx_probe_rq; - uint reassoc; - uint swtxstop; - uint swtxawake; -}; - #define SEC_KEY_1 (1<<0) #define SEC_KEY_2 (1<<1) #define SEC_KEY_3 (1<<2) @@ -1288,97 +1325,7 @@ struct ieee80211_txb { #define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST #define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST #define IW_ESSID_MAX_SIZE 32 -#if 0 -struct ieee80211_network { - /* These entries are used to identify a unique network */ - u8 bssid[ETH_ALEN]; - u8 channel; - /* Ensure null-terminated for any debug msgs */ - u8 ssid[IW_ESSID_MAX_SIZE + 1]; - u8 ssid_len; - u8 rssi; /* relative signal strength */ - u8 sq; /* signal quality */ - - /* These are network statistics */ - /* struct ieee80211_rx_stats stats; */ - u16 capability; - u16 aid; - u8 rates[MAX_RATES_LENGTH]; - u8 rates_len; - u8 rates_ex[MAX_RATES_EX_LENGTH]; - u8 rates_ex_len; - - u8 edca_parmsets[18]; - u8 mode; - u8 flags; - u8 time_stamp[8]; - u16 beacon_interval; - u16 listen_interval; - u16 atim_window; - u8 wpa_ie[MAX_WPA_IE_LEN]; - size_t wpa_ie_len; - u8 rsn_ie[MAX_WPA_IE_LEN]; - size_t rsn_ie_len; - u8 country[6]; - u8 dtim_period; - u8 dtim_data; - u8 power_constraint; - u8 qosinfo; - u8 qbssload[5]; - u8 network_type; - int join_res; - unsigned long last_scanned; -}; -#endif -/* -join_res: --1: authentication fail --2: association fail -> 0: TID -*/ - -#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */ - -enum ieee80211_state { - - /* the card is not linked at all */ - IEEE80211_NOLINK = 0, - - /* IEEE80211_ASSOCIATING* are for BSS client mode - * the driver shall not perform RX filtering unless - * the state is LINKED. - * The driver shall just check for the state LINKED and - * defaults to NOLINK for ALL the other states (including - * LINKED_SCANNING) - */ - - /* the association procedure will start (wq scheduling)*/ - IEEE80211_ASSOCIATING, - IEEE80211_ASSOCIATING_RETRY, - - /* the association procedure is sending AUTH request*/ - IEEE80211_ASSOCIATING_AUTHENTICATING, - - /* the association procedure has successfully authentcated - * and is sending association request - */ - IEEE80211_ASSOCIATING_AUTHENTICATED, - - /* the link is ok. the card associated to a BSS or linked - * to a ibss cell or acting as an AP and creating the bss - */ - IEEE80211_LINKED, - - /* same as LINKED, but the driver shall apply RX filter - * rules as we are in NO_LINK mode. As the card is still - * logically linked, but it is doing a syncro site survey - * then it will be back to LINKED state. - */ - IEEE80211_LINKED_SCANNING, - -}; -#endif /* PLATFORM_FREEBSD */ #define DEFAULT_MAX_SCAN_AGE (15 * HZ) #define DEFAULT_FTS 2346 @@ -1455,6 +1402,8 @@ enum rtw_ieee80211_category { #ifdef CONFIG_RTW_TOKEN_BASED_XMIT RTW_WLAN_CATEGORY_TBTX = 25, #endif + RTW_WLAN_CATEGORY_HE = 30, + RTW_WLAN_CATEGORY_PROTECTED_HE = 31, RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */ }; @@ -1524,24 +1473,6 @@ enum _PUBLIC_ACTION { ACT_PUBLIC_GAS_COMEBACK_RSP = 13, ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, ACT_PUBLIC_LOCATION_TRACK = 15, - ACT_PUBLIC_QAB_REQ, - ACT_PUBLIC_QAB_RSP, - ACT_PUBLIC_QMF_POLICY, - ACT_PUBLIC_QMF_POLICY_CHANGE, - ACT_PUBLIC_QLOAD_REQ, - ACT_PUBLIC_QLOAD_REPORT, - ACT_PUBLIC_HCCA_TXOP_ADV, - ACT_PUBLIC_HCCA_TXOP_RSP, - ACT_PUBLIC_PUBLIC_KEY, - ACT_PUBLIC_CH_AVAILABILITY_QUERY, - ACT_PUBLIC_CH_SCHEDULE_MGMT, - ACT_PUBLIC_CONTACT_VERI_SIGNAL, - ACT_PUBLIC_GDD_ENABLE_REQ, - ACT_PUBLIC_GDD_ENABLE_RSP, - ACT_PUBLIC_NETWORK_CH_CONTROL, - ACT_PUBLIC_WHITE_SPACE_MAP_ANN, - ACT_PUBLIC_FTM_REQ, - ACT_PUBLIC_FTM, ACT_PUBLIC_MAX }; @@ -1605,11 +1536,27 @@ enum rtw_ieee80211_vht_actioncode { RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2, }; +enum EXT_CAP_INFO{ + BSS_COEXT = 0, /* 20/40 BSS Coexistence Management Support */ + EXT_CH_SWITCH = 2, /* Extended Channel Switching */ + WNM_SLEEP_MODE = 17, /* WNM Sleep Mode */ + BSS_TRANSITION = 19, /* BSS Transition */ + MULTI_BSSID = 22, /* Multiple BSSID */ + TIME_MEASUREMENT = 23, /* Timing Measurement */ + SSID_LIST = 25, /* SSID List */ + TDLS_PSM = 29, /* TDLS Peer PSM Support */ + TDLS_CH_SWITCH = 30, /* TDLS channel switching */ + INTERWORKING = 31, /* Interworking */ + TDLS_SUPPORT = 37, /* TDLS Support */ + WNM_NOTIFICATION = 46, /* WNM Notification */ + OP_MODE_NOTIFICATION = 62, /* Operating Mode Notification */ + FTM_RESPONDER = 70, /* Fine Timing Measurement Responder */ + FTM_INITIATOR = 71, /* Fine Timing Measurement Initiator */ +}; + #define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) * 00:50:F2 */ -#ifndef PLATFORM_FREEBSD /* Baron BSD has defined */ - #define WME_OUI_TYPE 2 -#endif /* PLATFORM_FREEBSD */ +#define WME_OUI_TYPE 2 #define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 #define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 #define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 @@ -1635,6 +1582,8 @@ enum rtw_ieee80211_vht_actioncode { #endif #define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ +#define MBO_OUI_TYPE 0x16 + enum rtw_ieee80211_rann_flags { RTW_RANN_FLAG_IS_GATE = 1 << 0, }; @@ -1806,6 +1755,10 @@ struct rtw_ieee802_11_elems { u8 vht_operation_len; u8 *vht_op_mode_notify; u8 vht_op_mode_notify_len; + u8 *he_capabilities; + u8 he_capabilities_len; + u8 *he_operation; + u8 he_operation_len; u8 *rm_en_cap; u8 rm_en_cap_len; #ifdef CONFIG_RTW_MESH @@ -1833,10 +1786,24 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen); +/* + * Represent Extention Channel Offset in HT Capabilities + * This is available only in 40Mhz mode. + * */ +#if 0 +typedef enum _EXTCHNL_OFFSET { + EXTCHNL_OFFSET_NO_EXT = 0, + EXTCHNL_OFFSET_UPPER = 1, + EXTCHNL_OFFSET_NO_DEF = 2, + EXTCHNL_OFFSET_LOWER = 3, +} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET; +#endif + +/*enum chan_offset*/ enum secondary_ch_offset { - SCN = 0, /* no secondary channel */ - SCA = 1, /* secondary channel above */ - SCB = 3, /* secondary channel below */ + IEEE80211_SCN = 0, /* no secondary channel */ + IEEE80211_SCA = 1, /* the secondary channel is above the primary channel */ + IEEE80211_SCB = 3, /* the secondary channel is below the primary channel */ }; u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset); u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset); @@ -1848,9 +1815,10 @@ u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit); u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode); u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +u8 rtw_ies_update_ie(u8 *ies, uint *ies_len, uint ies_offset, u8 eid, const u8 *content, u8 content_len); int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); -void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ; +void rtw_set_supported_rate(u8 *SupportedRates, uint mode, u8 ch) ; #define GET_RSN_CAP_MFP_OPTION(cap) LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2) @@ -1860,8 +1828,8 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ; #define MFP_REQUIRED 3 /*For amsdu mode */ -#define GET_RSN_CAP_SPP_OPT(cap) LE_BITS_TO_2BYTE(((u8 *)(cap)), 10, 2) -#define SET_RSN_CAP_SPP(cap, spp) SET_BITS_TO_LE_2BYTE(((u8 *)(cap)), 10, 2, spp) +#define GET_RSN_CAP_SPP_OPT(cap) LE_BITS_TO_2BYTE(((u8 *)(cap)), 10, 2) +#define SET_RSN_CAP_SPP(cap, spp) SET_BITS_TO_LE_2BYTE(((u8 *)(cap)), 10, 2, spp) #define SPP_CAP BIT(0) #define SPP_REQ BIT(1) @@ -1869,7 +1837,8 @@ enum rtw_amsdu_mode { RTW_AMSDU_MODE_NON_SPP = 0, RTW_AMSDU_MODE_SPP = 1, RTW_AMSDU_MODE_ALL_DROP = 2, -}; + }; + struct rsne_info { u8 *gcs; @@ -1904,6 +1873,11 @@ u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen); +void rtw_add_ext_cap_info(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 cap_info); +void rtw_remove_ext_cap_info(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 cap_info); +u8 rtw_update_ext_cap_ie(u8 *ext_cap_data, u8 ext_cap_data_len, u8 *ies, u32 *ies_len, u8 ies_offset); +void rtw_parse_ext_cap_ie(u8 *ext_cap_data, u8 *ext_cap_data_len, u8 *ies, u32 ies_len, u8 ies_offset); + /** * for_each_ie - iterate over continuous IEs * @ie: @@ -1914,7 +1888,6 @@ u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen); for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2)) void dump_ies(void *sel, const u8 *buf, u32 buf_len); -#ifdef CONFIG_RTW_DEBUG #ifdef CONFIG_80211N_HT #define HT_SC_OFFSET_MAX 4 @@ -1925,7 +1898,6 @@ void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len); #endif void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len); -#endif /* CONFIG_RTW_DEBUG */ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht); @@ -1936,12 +1908,9 @@ bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset , u8 *g_ch, u8 *g_bw, u8 *g_offset); -#ifdef CONFIG_P2P u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); -#ifdef CONFIG_RTW_DEBUG void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len); -#endif u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); @@ -1951,21 +1920,21 @@ uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id); u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen); void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex); void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); -#endif /* CONFIG_P2P */ -uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); -void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex); -#ifdef CONFIG_WFD -#ifdef CONFIG_RTW_DEBUG +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST +int rtw_chk_p2p_wildcard_ssid(WLAN_BSSID_EX *bss_ex); +int rtw_chk_p2p_ie(WLAN_BSSID_EX *bss_ex); +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len); -#endif u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id); u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen); +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex); void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); -#endif #define MULTI_AP_SUB_ELEM_TYPE 0x06 #define MULTI_AP_TEAR_DOWN BIT(4) @@ -1997,8 +1966,6 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr); u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate); u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set); u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss); -u8 rtw_ht_cap_get_rx_nss(u8 *ht_cap); -u8 rtw_ht_cap_get_tx_nss(u8 *ht_cap); int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action); const char *action_public_str(u8 action); @@ -2010,7 +1977,8 @@ u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); int wifirate2_ratetbl_inx(unsigned char rate); /* For amsdu mode. */ -/*void rtw_set_spp_amsdu_mode(u8 mode, u8 *rsn_ie, int rsn_ie_len); */ +/*void rtw_set_spp_amsdu_mode(u8 mode, u8 *rsn_ie, int rsn_ie_len);*/ u8 rtw_check_amsdu_disable(u8 mode, u8 spp_opt); + #endif /* IEEE80211_H */ diff --git a/include/ieee80211_ext.h b/include/ieee80211_ext.h index 4965863..77ccf83 100644 --- a/include/ieee80211_ext.h +++ b/include/ieee80211_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/if_ether.h b/include/if_ether.h index a3007c4..0778cbd 100644 --- a/include/if_ether.h +++ b/include/if_ether.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/ip.h b/include/ip.h index 4feb98f..6b609a2 100644 --- a/include/ip.h +++ b/include/ip.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/linux/wireless.h b/include/linux/wireless.h index c7f4a6c..37a6061 100644 --- a/include/linux/wireless.h +++ b/include/linux/wireless.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/mlme_osdep.h b/include/mlme_osdep.h index 131eb09..b9f9545 100644 --- a/include/mlme_osdep.h +++ b/include/mlme_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/osdep_intf.h b/include/osdep_intf.h index 63e535e..7b123c1 100644 --- a/include/osdep_intf.h +++ b/include/osdep_intf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,69 +12,31 @@ * more details. * *****************************************************************************/ - #ifndef __OSDEP_INTF_H_ #define __OSDEP_INTF_H_ - -struct intf_priv { - - u8 *intf_dev; - u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */ - u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */ - u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */ - - volatile u8 *io_rwmem; - volatile u8 *allocated_io_rwmem; - u32 io_wsz; /* unit: 4bytes */ - u32 io_rsz;/* unit: 4bytes */ - u8 intf_status; - - void (*_bus_io)(u8 *priv); - - /* - Under Sync. IRP (SDIO/USB) - A protection mechanism is necessary for the io_rwmem(read/write protocol) - - Under Async. IRP (SDIO/USB) - The protection mechanism is through the pending queue. - */ - - _mutex ioctl_mutex; - - -#ifdef PLATFORM_LINUX -#ifdef CONFIG_USB_HCI - /* when in USB, IO is through interrupt in/out endpoints */ - struct usb_device *udev; - PURB piorw_urb; - u8 io_irp_cnt; - u8 bio_irp_pending; - _sema io_retevt; - _timer io_timer; - u8 bio_irp_timeout; - u8 bio_timer_cancel; -#endif -#endif - -}; - struct dvobj_priv *devobj_init(void); void devobj_deinit(struct dvobj_priv *pdvobj); +u8 devobj_data_init(struct dvobj_priv *dvobj); +void devobj_data_deinit(struct dvobj_priv *dvobj); +u8 devobj_trx_resource_init(struct dvobj_priv *dvobj); +void devobj_trx_resource_deinit(struct dvobj_priv *dvobj); u8 rtw_init_drv_sw(_adapter *padapter); u8 rtw_free_drv_sw(_adapter *padapter); u8 rtw_reset_drv_sw(_adapter *padapter); -void rtw_dev_unload(PADAPTER padapter); +void rtw_drv_stop_prim_iface(_adapter *adapter); +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ u32 rtw_start_drv_threads(_adapter *padapter); void rtw_stop_drv_threads(_adapter *padapter); +#endif + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) void rtw_cancel_dynamic_chk_timer(_adapter *padapter); #endif void rtw_cancel_all_timer(_adapter *padapter); -uint loadparam(_adapter *adapter); #ifdef PLATFORM_LINUX int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); @@ -99,9 +61,6 @@ void rtw_inetaddr_notifier_unregister(void); #include "../os_dep/linux/rtw_proc.h" #include "../os_dep/linux/nlrtw.h" -#ifdef CONFIG_PLATFORM_CMAP_INTFS -#include "../os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.h" -#endif #ifdef CONFIG_IOCTL_CFG80211 #include "../os_dep/linux/ioctl_cfg80211.h" @@ -127,7 +86,7 @@ void rtw_ips_pwr_down(_adapter *padapter); #ifdef CONFIG_CONCURRENT_MODE struct _io_ops; struct dvobj_priv; -_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)); +u8 rtw_drv_add_vir_ifaces(struct dvobj_priv *dvobj); void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj); void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj); #endif @@ -139,5 +98,6 @@ int rtw_gw_addr_query(_adapter *padapter); int rtw_suspend_common(_adapter *padapter); int rtw_resume_common(_adapter *padapter); +int rtw_suspend_free_assoc_resource(_adapter *padapter); #endif /* _OSDEP_INTF_H_ */ diff --git a/include/osdep_service.h b/include/osdep_service.h index 4ec16b5..955cc61 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,30 +15,18 @@ #ifndef __OSDEP_SERVICE_H_ #define __OSDEP_SERVICE_H_ - -#define _FAIL 0 -#define _SUCCESS 1 #define RTW_RX_HANDLED 2 #define RTW_RFRAME_UNAVAIL 3 -#define RTW_RFRAME_PKT_UNAVAIL 4 +#define RTW_RFRAME_PKT_UNAVAIL 4 #define RTW_RBUF_UNAVAIL 5 -#define RTW_RBUF_PKT_UNAVAIL 6 -#define RTW_SDIO_READ_PORT_FAIL 7 -#define RTW_ALREADY 8 +#define RTW_RBUF_PKT_UNAVAIL 6 +#define RTW_SDIO_RECV_FAIL 7 +#define RTW_ALREADY 8 #define RTW_RA_RESOLVING 9 -#define RTW_BMC_NO_NEED 10 -#define RTW_XBUF_UNAVAIL 11 -#define RTW_TX_BALANCE 12 -#define RTW_TX_WAIT_MORE_FRAME 13 -#define RTW_QUEUE_MGMT 14 +#define RTW_ORI_NO_NEED 10 /* #define RTW_STATUS_TIMEDOUT -110 */ -#undef _TRUE -#define _TRUE 1 - -#undef _FALSE -#define _FALSE 0 #ifdef PLATFORM_FREEBSD @@ -52,17 +40,6 @@ #include #endif #include - #include -#endif - -#ifdef PLATFORM_OS_XP - #include - #include -#endif - -#ifdef PLATFORM_OS_CE - #include - #include #endif /* #include */ @@ -154,6 +131,7 @@ typedef enum mstat_status { MSTAT_FREE } MSTAT_STATUS; + #ifdef DBG_MEM_ALLOC void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); void rtw_mstat_dump(void *sel); @@ -169,6 +147,7 @@ struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, c void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +int dbg_rtw_skb_linearize(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); #ifdef CONFIG_RTW_NAPI int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); @@ -185,41 +164,42 @@ void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dm #ifdef CONFIG_USE_VMALLOC #define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) #define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) -#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) -#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) #define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) #define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) #else /* CONFIG_USE_VMALLOC */ #define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) #define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) #define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) #define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) #endif /* CONFIG_USE_VMALLOC */ -#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) #define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) -#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) -#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_linearize(skb) dbg_rtw_skb_linearize((skb), MSTAT_TYPE_SKB, __func__, __LINE__) +#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #ifdef CONFIG_RTW_NAPI -#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #ifdef CONFIG_RTW_GRO -#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #endif #endif /* CONFIG_RTW_NAPI */ -#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #ifdef CONFIG_USB_HCI #define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) #define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) @@ -240,9 +220,6 @@ void _rtw_mfree(void *pbuf, u32 sz); struct sk_buff *_rtw_skb_alloc(u32 sz); void _rtw_skb_free(struct sk_buff *skb); -struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); -struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); -int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); #ifdef CONFIG_RTW_NAPI int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb); #ifdef CONFIG_RTW_GRO @@ -251,42 +228,38 @@ gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb #endif /* CONFIG_RTW_NAPI */ void _rtw_skb_queue_purge(struct sk_buff_head *list); -#ifdef CONFIG_USB_HCI -void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma); -void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); -#endif /* CONFIG_USB_HCI */ - #ifdef CONFIG_USE_VMALLOC #define rtw_vmalloc(sz) _rtw_vmalloc((sz)) #define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) -#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) -#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) #define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) #define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) #else /* CONFIG_USE_VMALLOC */ #define rtw_vmalloc(sz) _rtw_malloc((sz)) #define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) -#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) -#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) #define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) #define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) #endif /* CONFIG_USE_VMALLOC */ -#define rtw_malloc(sz) _rtw_malloc((sz)) +#define rtw_malloc(sz) _rtw_malloc((sz)) #define rtw_zmalloc(sz) _rtw_zmalloc((sz)) -#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) -#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) -#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) -#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) +#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) -#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) -#define rtw_skb_free(skb) _rtw_skb_free((skb)) +#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) +#define rtw_skb_free(skb) _rtw_skb_free((skb)) #define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) -#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) -#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) -#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) -#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) -#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) -#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) +#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) +#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) +#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) +#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) +#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) +#define rtw_skb_linearize(skb) _rtw_skb_linearize(skb) +#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) #ifdef CONFIG_RTW_NAPI #define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb) #ifdef CONFIG_RTW_GRO @@ -302,31 +275,24 @@ void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_a #endif /* CONFIG_USB_HCI */ #endif /* DBG_MEM_ALLOC */ -extern void *rtw_malloc2d(int h, int w, size_t size); -extern void rtw_mfree2d(void *pbuf, int h, int w, int size); -void rtw_os_pkt_free(_pkt *pkt); -_pkt *rtw_os_pkt_copy(_pkt *pkt); -void *rtw_os_pkt_data(_pkt *pkt); -u32 rtw_os_pkt_len(_pkt *pkt); +void *rtw_malloc2d(int h, int w, size_t size); +void rtw_mfree2d(void *pbuf, int h, int w, int size); +void _rtw_memcpy(void *dec, const void *sour, u32 sz); +void _rtw_memmove(void *dst, const void *src, u32 sz); +int _rtw_memcmp(const void *dst, const void *src, u32 sz); +int _rtw_memcmp2(const void *dst, const void *src, u32 sz); +void _rtw_memset(void *pbuf, int c, u32 sz); -extern void _rtw_memcpy(void *dec, const void *sour, u32 sz); -extern void _rtw_memmove(void *dst, const void *src, u32 sz); -extern int _rtw_memcmp(const void *dst, const void *src, u32 sz); -extern int _rtw_memcmp2(const void *dst, const void *src, u32 sz); -extern void _rtw_memset(void *pbuf, int c, u32 sz); - -extern void _rtw_init_listhead(_list *list); -extern u32 rtw_is_list_empty(_list *phead); -extern void rtw_list_insert_head(_list *plist, _list *phead); -extern void rtw_list_insert_tail(_list *plist, _list *phead); +void _rtw_init_listhead(_list *list); +u32 rtw_is_list_empty(_list *phead); +void rtw_list_insert_head(_list *plist, _list *phead); +void rtw_list_insert_tail(_list *plist, _list *phead); void rtw_list_splice(_list *list, _list *head); void rtw_list_splice_init(_list *list, _list *head); void rtw_list_splice_tail(_list *list, _list *head); -#ifndef PLATFORM_FREEBSD -extern void rtw_list_delete(_list *plist); -#endif /* PLATFORM_FREEBSD */ +void rtw_list_delete(_list *plist); void rtw_hlist_head_init(rtw_hlist_head *h); void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h); @@ -334,37 +300,24 @@ void rtw_hlist_del(rtw_hlist_node *n); void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h); void rtw_hlist_del_rcu(rtw_hlist_node *n); -extern void _rtw_init_sema(_sema *sema, int init_val); -extern void _rtw_free_sema(_sema *sema); -extern void _rtw_up_sema(_sema *sema); -extern u32 _rtw_down_sema(_sema *sema); -extern void _rtw_mutex_init(_mutex *pmutex); -extern void _rtw_mutex_free(_mutex *pmutex); -#ifndef PLATFORM_FREEBSD -extern void _rtw_spinlock_init(_lock *plock); -#endif /* PLATFORM_FREEBSD */ -extern void _rtw_spinlock_free(_lock *plock); -extern void _rtw_spinlock(_lock *plock); -extern void _rtw_spinunlock(_lock *plock); -extern void _rtw_spinlock_ex(_lock *plock); -extern void _rtw_spinunlock_ex(_lock *plock); - -extern void _rtw_init_queue(_queue *pqueue); -extern void _rtw_deinit_queue(_queue *pqueue); -extern u32 _rtw_queue_empty(_queue *pqueue); -extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); - -extern systime _rtw_get_current_time(void); -extern u32 _rtw_systime_to_ms(systime stime); -extern systime _rtw_ms_to_systime(u32 ms); -extern systime _rtw_us_to_systime(u32 us); -extern s32 _rtw_get_passing_time_ms(systime start); -extern s32 _rtw_get_remaining_time_ms(systime end); -extern s32 _rtw_get_time_interval_ms(systime start, systime end); -extern bool _rtw_time_after(systime a, systime b); +void _rtw_init_queue(_queue *pqueue); +void _rtw_deinit_queue(_queue *pqueue); +u32 _rtw_queue_empty(_queue *pqueue); +u32 rtw_end_of_queue_search(_list *queue, _list *pelement); + +systime _rtw_get_current_time(void); +u32 _rtw_systime_to_us(systime stime); +u32 _rtw_systime_to_ms(systime stime); +systime _rtw_ms_to_systime(u32 ms); +systime _rtw_us_to_systime(u32 us); +s32 _rtw_get_passing_time_ms(systime start); +s32 _rtw_get_remaining_time_ms(systime end); +s32 _rtw_get_time_interval_ms(systime start, systime end); +bool _rtw_time_after(systime a, systime b); #ifdef DBG_SYSTIME #define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;}) +#define rtw_systime_to_us(stime) ({u32 __us = _rtw_systime_to_us(stime); typecheck(systime, stime); __us;}) #define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;}) #define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;}) #define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;}) @@ -375,6 +328,7 @@ extern bool _rtw_time_after(systime a, systime b); #define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;}) #else #define rtw_get_current_time() _rtw_get_current_time() +#define rtw_systime_to_us(stime) _rtw_systime_to_us(stime) #define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime) #define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms) #define rtw_us_to_systime(us) _rtw_us_to_systime(us) @@ -385,86 +339,26 @@ extern bool _rtw_time_after(systime a, systime b); #define rtw_time_before(a,b) _rtw_time_after(b,a) #endif -sysptime rtw_sptime_get(void); -sysptime rtw_sptime_set(s64 secs, const u32 nsecs); -sysptime rtw_sptime_zero(void); - -int rtw_sptime_cmp(const sysptime cmp1, const sysptime cmp2); -bool rtw_sptime_eql(const sysptime cmp1, const sysptime cmp2); -bool rtw_sptime_is_zero(const sysptime sptime); -sysptime rtw_sptime_sub(const sysptime lhs, const sysptime rhs); -sysptime rtw_sptime_add(const sysptime lhs, const sysptime rhs); - -s64 rtw_sptime_to_ms(const sysptime sptime); -sysptime rtw_ms_to_sptime(u64 ms); -s64 rtw_sptime_to_us(const sysptime sptime); -sysptime rtw_us_to_sptime(u64 us); -s64 rtw_sptime_to_ns(const sysptime sptime); -sysptime rtw_ns_to_sptime(u64 ns); - -s64 rtw_sptime_diff_ms(const sysptime start, const sysptime end); -s64 rtw_sptime_pass_ms(const sysptime start); -s64 rtw_sptime_diff_us(const sysptime start, const sysptime end); -s64 rtw_sptime_pass_us(const sysptime start); -s64 rtw_sptime_diff_ns(const sysptime start, const sysptime end); -s64 rtw_sptime_pass_ns(const sysptime start); - -extern void rtw_sleep_schedulable(int ms); +void rtw_sleep_schedulable(int ms); -extern void rtw_msleep_os(int ms); -extern void rtw_usleep_os(int us); +void rtw_msleep_os(int ms); +void rtw_usleep_os(int us); -extern u32 rtw_atoi(u8 *s); +u32 rtw_atoi(u8 *s); #ifdef DBG_DELAY_OS #define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) #define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) -extern void _rtw_mdelay_os(int ms, const char *func, const int line); -extern void _rtw_udelay_os(int us, const char *func, const int line); +void _rtw_mdelay_os(int ms, const char *func, const int line); +void _rtw_udelay_os(int us, const char *func, const int line); #else -extern void rtw_mdelay_os(int ms); -extern void rtw_udelay_os(int us); +void rtw_mdelay_os(int ms); +void rtw_udelay_os(int us); #endif -extern void rtw_yield_os(void); - -enum rtw_pwait_type { - RTW_PWAIT_TYPE_MSLEEP, - RTW_PWAIT_TYPE_USLEEP, - RTW_PWAIT_TYPE_YIELD, - RTW_PWAIT_TYPE_MDELAY, - RTW_PWAIT_TYPE_UDELAY, - - RTW_PWAIT_TYPE_NUM, -}; - -#define RTW_PWAIT_TYPE_VALID(type) (type < RTW_PWAIT_TYPE_NUM) - -struct rtw_pwait_conf { - enum rtw_pwait_type type; - s32 wait_time; - s32 wait_cnt_lmt; -}; - -struct rtw_pwait_ctx { - struct rtw_pwait_conf conf; - s32 wait_cnt; - void (*wait_hdl)(int us); -}; - -extern const char *_rtw_pwait_type_str[]; -#define rtw_pwait_type_str(type) (RTW_PWAIT_TYPE_VALID(type) ? _rtw_pwait_type_str[type] : _rtw_pwait_type_str[RTW_PWAIT_TYPE_NUM]) - -#define rtw_pwctx_reset(pwctx) (pwctx)->wait_cnt = 0 -#define rtw_pwctx_wait(pwctx) do { (pwctx)->wait_hdl((pwctx)->conf.wait_time); (pwctx)->wait_cnt++; } while(0) -#define rtw_pwctx_waited(pwctx) ((pwctx)->wait_cnt) -#define rtw_pwctx_exceed(pwctx) ((pwctx)->conf.wait_cnt_lmt >= 0 && (pwctx)->wait_cnt >= (pwctx)->conf.wait_cnt_lmt) - -int rtw_pwctx_config(struct rtw_pwait_ctx *pwctx, enum rtw_pwait_type type, s32 time, s32 cnt_lmt); - -extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); - +void rtw_yield_os(void); +void rtw_init_timer(_timer *ptimer, void *pfunc, void *ctx); __inline static unsigned char _cancel_timer_ex(_timer *ptimer) { u8 bcancelled; @@ -474,104 +368,10 @@ __inline static unsigned char _cancel_timer_ex(_timer *ptimer) return bcancelled; } -static __inline void thread_enter(char *name) +__inline static void _cancel_timer_nowait(_timer *ptimer) { -#ifdef PLATFORM_LINUX - allow_signal(SIGTERM); -#endif -#ifdef PLATFORM_FREEBSD - printf("%s", "RTKTHREAD_enter"); -#endif + _cancel_timer_async(ptimer); } -void thread_exit(_completion *comp); -void _rtw_init_completion(_completion *comp); -void _rtw_wait_for_comp_timeout(_completion *comp); -void _rtw_wait_for_comp(_completion *comp); - -static inline bool rtw_thread_stop(_thread_hdl_ th) -{ -#ifdef PLATFORM_LINUX - return kthread_stop(th); -#endif -} -static inline void rtw_thread_wait_stop(void) -{ -#ifdef PLATFORM_LINUX - #if 0 - while (!kthread_should_stop()) - rtw_msleep_os(10); - #else - set_current_state(TASK_INTERRUPTIBLE); - while (!kthread_should_stop()) { - schedule(); - set_current_state(TASK_INTERRUPTIBLE); - } - __set_current_state(TASK_RUNNING); - #endif -#endif -} - -__inline static void flush_signals_thread(void) -{ -#ifdef PLATFORM_LINUX - if (signal_pending(current)) - flush_signals(current); -#endif -} - -__inline static _OS_STATUS res_to_status(sint res) -{ - -#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD) - return res; -#endif - -#ifdef PLATFORM_WINDOWS - - if (res == _SUCCESS) - return NDIS_STATUS_SUCCESS; - else - return NDIS_STATUS_FAILURE; - -#endif - -} - -__inline static void rtw_dump_stack(void) -{ -#ifdef PLATFORM_LINUX - dump_stack(); -#endif -} - -#ifdef PLATFORM_LINUX -#define rtw_warn_on(condition) WARN_ON(condition) -#else -#define rtw_warn_on(condition) do {} while (0) -#endif - -__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4) -{ - int ret = _TRUE; - -#ifdef PLATFORM_WINDOWS - if (((uint)parg1) <= 0x7fffffff || - ((uint)parg2) <= 0x7fffffff || - ((uint)parg3) <= 0x7fffffff || - ((uint)parg4) <= 0x7fffffff) { - ret = _FALSE; - KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4); - } -#endif - - return ret; - -} -#ifdef PLATFORM_LINUX -#define RTW_DIV_ROUND_UP(n, d) DIV_ROUND_UP(n, d) -#else /* !PLATFORM_LINUX */ -#define RTW_DIV_ROUND_UP(n, d) (((n) + (d - 1)) / d) -#endif /* !PLATFORM_LINUX */ #define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) #define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2) @@ -664,9 +464,9 @@ static inline int largest_bit_64(u64 bitmask) return i; } -#define rtw_abs(a) (a < 0 ? -a : a) -#define rtw_min(a, b) ((a > b) ? b : a) -#define rtw_max(a, b) ((a > b) ? a : b) +#define rtw_abs(a) ((a) < 0 ? -(a) : (a)) +#define rtw_min(a, b) (((a) > (b)) ? (b) : (a)) +#define rtw_max(a, b) (((a) > (b)) ? (a) : (b)) #define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b))) #define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b))) @@ -679,52 +479,38 @@ static inline int largest_bit_64(u64 bitmask) bool rtw_macaddr_is_larger(const u8 *a, const u8 *b); -extern void rtw_suspend_lock_init(void); -extern void rtw_suspend_lock_uninit(void); -extern void rtw_lock_suspend(void); -extern void rtw_unlock_suspend(void); -extern void rtw_lock_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); -extern void rtw_resume_lock_suspend(void); -extern void rtw_resume_unlock_suspend(void); +void rtw_suspend_lock_init(void); +void rtw_suspend_lock_uninit(void); +void rtw_lock_suspend(void); +void rtw_unlock_suspend(void); +void rtw_lock_suspend_timeout(u32 timeout_ms); +void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); +void rtw_resume_lock_suspend(void); +void rtw_resume_unlock_suspend(void); #ifdef CONFIG_AP_WOWLAN -extern void rtw_softap_lock_suspend(void); -extern void rtw_softap_unlock_suspend(void); +void rtw_softap_lock_suspend(void); +void rtw_softap_unlock_suspend(void); #endif -extern void rtw_set_bit(int nr, unsigned long *addr); -extern void rtw_clear_bit(int nr, unsigned long *addr); -extern int rtw_test_and_clear_bit(int nr, unsigned long *addr); - -extern void ATOMIC_SET(ATOMIC_T *v, int i); -extern int ATOMIC_READ(ATOMIC_T *v); -extern void ATOMIC_ADD(ATOMIC_T *v, int i); -extern void ATOMIC_SUB(ATOMIC_T *v, int i); -extern void ATOMIC_INC(ATOMIC_T *v); -extern void ATOMIC_DEC(ATOMIC_T *v); -extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); -extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); -extern int ATOMIC_INC_RETURN(ATOMIC_T *v); -extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); -extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u); +void rtw_set_bit(int nr, unsigned long *addr); +void rtw_clear_bit(int nr, unsigned long *addr); +int rtw_test_and_clear_bit(int nr, unsigned long *addr); +int rtw_test_and_set_bit(int nr, unsigned long *addr); /* File operation APIs, just for linux now */ -extern int rtw_is_dir_readable(const char *path); -extern int rtw_is_file_readable(const char *path); -extern int rtw_is_file_readable_with_size(const char *path, u32 *sz); -extern int rtw_readable_file_sz_chk(const char *path, u32 sz); -extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz); -extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz); - - -#ifndef PLATFORM_FREEBSD -extern void rtw_free_netdev(struct net_device *netdev); -#endif /* PLATFORM_FREEBSD */ - - -extern u64 rtw_modular64(u64 x, u64 y); -extern u64 rtw_division64(u64 x, u64 y); -extern u32 rtw_random32(void); +#ifndef CONFIG_RTW_ANDROID +int rtw_is_dir_readable(const char *path); +int rtw_store_to_file(const char *path, u8 *buf, u32 sz); +#endif /* CONFIG_RTW_ANDROID */ +int rtw_is_file_readable(const char *path); +int rtw_is_file_readable_with_size(const char *path, u32 *sz); +int rtw_readable_file_sz_chk(const char *path, u32 sz); +int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz); +void rtw_free_netdev(struct net_device *netdev); + +u64 rtw_modular64(u64 x, u64 y); +u64 rtw_division64(u64 x, u64 y); + u32 rtw_random32(void); /* Macros for handling unaligned memory accesses */ @@ -804,7 +590,7 @@ extern u32 rtw_random32(void); } while (0) void rtw_buf_free(u8 **buf, u32 *buf_len); -void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); +void rtw_buf_update(u8 **buf, u32 *buf_len, const u8 *src, u32 src_len); struct rtw_cbuf { u32 write; @@ -851,13 +637,11 @@ struct blacklist_ent { systime exp_time; }; -#ifdef CONFIG_RTW_MESH int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms); int rtw_blacklist_del(_queue *blist, const u8 *addr); int rtw_blacklist_search(_queue *blist, const u8 *addr); void rtw_blacklist_flush(_queue *blist); void dump_blacklist(void *sel, _queue *blist, const char *title); -#endif /* String handler */ @@ -865,6 +649,7 @@ BOOLEAN is_null(char c); BOOLEAN is_all_null(char *c, int len); BOOLEAN is_eol(char c); BOOLEAN is_space(char c); +BOOLEAN is_decimal(char chTmp); BOOLEAN IsHexDigit(char chTmp); BOOLEAN is_alpha(char chTmp); char alpha_to_upper(char c); @@ -873,15 +658,8 @@ int hex2num_i(char c); int hex2byte_i(const char *hex); int hexstr2bin(const char *hex, u8 *buf, size_t len); -int hwaddr_aton_i(const char *txt, u8 *addr); - /* * Write formatted output to sized buffer */ -#ifdef PLATFORM_LINUX -#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) -#else /* !PLATFORM_LINUX */ -#error "NOT DEFINE \"rtw_sprintf\"!!" -#endif /* !PLATFORM_LINUX */ #endif diff --git a/include/osdep_service_bsd.h b/include/osdep_service_bsd.h index f8f15d6..bf89773 100644 --- a/include/osdep_service_bsd.h +++ b/include/osdep_service_bsd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -86,14 +86,11 @@ _lock lock; }; - typedef struct mbuf _pkt; typedef struct mbuf _buffer; typedef struct __queue _queue; typedef struct list_head _list; - typedef int _OS_STATUS; - //typedef u32 _irqL; - typedef unsigned long _irqL; + typedef struct ifnet * _nic_hdl; typedef pid_t _thread_hdl_; @@ -112,14 +109,198 @@ #define WIRELESS_EXT -1 #define HZ hz -#define spin_lock_irqsave mtx_lock_irqsave -#define spin_lock_bh mtx_lock_irqsave -#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} + //#define IFT_RTW 0xf9 //ifnet allocate type for RTW #define free_netdev if_free #define LIST_CONTAINOR(ptr, type, member) \ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) #define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) + +/*lock - spinlock*/ +static inline void _rtw_spinlock_init(_lock *plock) +{ + mtx_init(plock, "", NULL, MTX_DEF | MTX_RECURSE); +} + +static inline void _rtw_spinlock_free(_lock *plock) +{ + mtx_destroy(plock); +} + +static inline void _rtw_spinlock(_lock *plock) +{ + mtx_lock(plock); +} + +static inline void _rtw_spinunlock(_lock *plock) +{ + mtx_unlock(plock); +} + +#if 0 +static inline void _rtw_spinlock_ex(_lock *plock) +{ + mtx_lock(plock); +} + +static inline void _rtw_spinunlock_ex(_lock *plock) +{ + mtx_unlock(plock); +} +#endif + +__inline static void _rtw_spinlock_irq(_lock *plock, unsigned long *flags) +{ + mtx_lock(plock); /*{local_irq_save((x)); mtx_lock_spin((lock));}*/ +} + +__inline static void _rtw_spinunlock_irq(_lock *plock, unsigned long *flags) +{ + mtx_unlock(plock); +} + +__inline static void _rtw_spinlock_bh(_lock *plock) +{ + mtx_lock(plock);/*{local_irq_save((x)); mtx_lock_spin((lock));}*/ +} + +__inline static void _rtw_spinunlock_bh(_lock *plock) +{ + mtx_unlock(plock); +} + +/*lock - semaphore*/ +static inline void _rtw_init_sema(_sema *sema, int init_val) +{ + sema_init(sema, init_val, "rtw_drv"); +} + +static inline void _rtw_free_sema(_sema *sema) +{ + sema_destroy(sema); +} + +static inline void _rtw_up_sema(_sema *sema) +{ + sema_post(sema); +} + +static inline u32 _rtw_down_sema(_sema *sema) +{ + sema_wait(sema); + return _SUCCESS; +} + +/*lock - mutex*/ +static inline void _rtw_mutex_init(_mutex *pmutex) +{ + mtx_init(pmutex, "", NULL, MTX_DEF | MTX_RECURSE); +} + +static inline void _rtw_mutex_free(_mutex *pmutex) +{ + sema_destroy(pmutex); +} + +__inline static void _rtw_mutex_lock_interruptible(_mutex *pmutex) +{ + + mtx_lock(pmutex); + +} +__inline static void _rtw_mutex_lock(_mutex *pmutex) +{ + + mtx_lock(pmutex); + +} + +__inline static void _rtw_mutex_unlock(_mutex *pmutex) +{ + mtx_unlock(pmutex); +} + +static inline void *_rtw_vmalloc(u32 sz) +{ + void *pbuf; + pbuf = malloc(sz, M_DEVBUF, M_NOWAIT); + + return pbuf; +} + +static inline void *_rtw_zvmalloc(u32 sz) +{ + void *pbuf; + + pbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); + return pbuf; +} + +static inline void _rtw_vmfree(void *pbuf, u32 sz) +{ + free(pbuf, M_DEVBUF); +} + +static inline void *_rtw_malloc(u32 sz) +{ + void *pbuf = NULL; + + pbuf = malloc(sz, M_DEVBUF, M_NOWAIT); + return pbuf; +} +static inline void *_rtw_zmalloc(u32 sz) +{ + return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); +} +static inline void _rtw_mfree(void *pbuf, u32 sz) +{ + free(pbuf, M_DEVBUF); +} +#ifdef CONFIG_USB_HCI +static inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma) +{ + return malloc(size, M_USBDEV, M_NOWAIT | M_ZERO); +} +static inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma) +{ + free(addr, M_USBDEV); +} +#endif /* CONFIG_USB_HCI */ + +struct sk_buff *_rtw_skb_alloc(u32 sz); +void _rtw_skb_free(struct sk_buff *skb); +static inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) +{ + return NULL; +} + +static inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) +{ + return skb_clone(skb); +} + +static inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) +{ + return (*ndev->if_input)(ndev, skb); +} + +#ifdef CONFIG_RTW_NAPI +static inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb) +{ + rtw_warn_on(1); + return -1; +} + +#ifdef CONFIG_RTW_GRO +static inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb) +{ + rtw_warn_on(1); + return -1; +} +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + + /* * Linux timers are emulated using FreeBSD callout functions * (and taskqueue functionality). @@ -151,10 +332,6 @@ struct work_struct { work_state_t state; /* the pending or otherwise state of work. */ work_func_t func; }; -#define spin_unlock_irqrestore mtx_unlock_irqrestore -#define spin_unlock_bh mtx_unlock_irqrestore -#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); -extern void _rtw_spinlock_init(_lock *plock); //modify private structure to match freebsd #define BITS_PER_LONG 32 @@ -338,7 +515,7 @@ struct sk_buff { unsigned char *head, *data; unsigned int truesize; - atomic_t users; + ATOMIC_T users; }; struct sk_buff_head { /* These two members must be first. */ @@ -367,11 +544,7 @@ static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) } static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) { - #ifdef PLATFORM_FREEBSD return __skb_pull(skb, len); - #else - return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); - #endif //PLATFORM_FREEBSD } static inline u32 skb_queue_len(const struct sk_buff_head *list_) { @@ -453,6 +626,16 @@ static inline void skb_queue_head_init(struct sk_buff_head *list) _rtw_spinlock_init(&list->lock); __skb_queue_head_init(list); } +static inline u8 *rtw_skb_data(struct sk_buff *pkt) +{ + return pkt->data; +} + +static inline u32 rtw_skb_len(struct sk_buff *pkt) +{ + return pkt->len; +} + unsigned long copy_from_user(void *to, const void *from, unsigned long n); unsigned long copy_to_user(void *to, const void *from, unsigned long n); struct sk_buff * dev_alloc_skb(unsigned int size); @@ -535,7 +718,7 @@ struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); -void *rtw_usbd_get_intfdata(struct usb_interface *intf); +void *rtw_usb_get_intfdata(struct usb_interface *intf); void rtw_usb_linux_register(void *arg); void rtw_usb_linux_deregister(void *arg); void rtw_usb_linux_free_device(struct usb_device *dev); @@ -600,50 +783,6 @@ __inline static _list *get_list_head(_queue *queue) ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_lock_bh(plock, *pirqL); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_unlock_bh(plock, *pirqL); -} - -__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_lock(pmutex); - -} - - -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_unlock(pmutex); - -} static inline void __list_del(struct list_head * prev, struct list_head * next) { next->prev = prev; @@ -684,7 +823,7 @@ static inline void timer_hdl(void *ctx) rtw_mtx_unlock(NULL); } -static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx) +static inline void _init_timer(_timer *ptimer, void *pfunc, void *cntx) { ptimer->function = pfunc; ptimer->arg = cntx; @@ -731,17 +870,153 @@ __inline static void _set_workitem(_workitem *pwork) { \ } +/* Atomic integer operations */ +#define ATOMIC_T atomic_t + #define ATOMIC_INIT(i) { (i) } +static inline void ATOMIC_SET(ATOMIC_T *v, int i) +{ + atomic_set_int(v, i); +} + +static inline int ATOMIC_READ(ATOMIC_T *v) +{ + return atomic_load_acq_32(v); +} + +static inline void ATOMIC_ADD(ATOMIC_T *v, int i) +{ + atomic_add_int(v, i); +} +static inline void ATOMIC_SUB(ATOMIC_T *v, int i) +{ + atomic_subtract_int(v, i); +} -static __inline void thread_enter(char *name); +static inline void ATOMIC_INC(ATOMIC_T *v) +{ + atomic_add_int(v, 1); +} -//Atomic integer operations -typedef uint32_t ATOMIC_T ; +static inline void ATOMIC_DEC(ATOMIC_T *v) +{ + atomic_subtract_int(v, 1); +} -#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) +static inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) +{ + atomic_add_int(v, i); + return atomic_load_acq_32(v); +} + +static inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) +{ + atomic_subtract_int(v, i); + return atomic_load_acq_32(v); +} +static inline int ATOMIC_INC_RETURN(ATOMIC_T *v) +{ + atomic_add_int(v, 1); + return atomic_load_acq_32(v); +} + +static inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) +{ + atomic_subtract_int(v, 1); + return atomic_load_acq_32(v); +} + +static inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u) +{ + #error "TBD\n" +} + +/*task*/ +typedef void (*task_fn_t)(void *context, int pending); +#if 0 /*taskqueue -- asynchronous task execution*/ + +TASK_INIT(struct task *task, int priority, task_fn_t func, + void *context); + +TASK_INITIALIZER(int priority, task_fn_t func, void *context); + +TASKQUEUE_DECLARE(name); + +TASKQUEUE_DEFINE(name, taskqueue_enqueue_fn enqueue, void *context, + init); + +#endif +static inline void rtw_tasklet_init(_tasklet *t,task_fn_t func, + unsigned long data) +{ + TASK_INIT(t, 0, func, padapter); +} +static inline void rtw_tasklet_kill(_tasklet *t) + + +} + +static inline void rtw_tasklet_schedule(_tasklet *t) +{ + +} +static inline void rtw_tasklet_hi_schedule(_tasklet *t) +{ + +} + + +/*thread*/ +static inline void rtw_thread_enter(char *name) +{ + printf("%s", "RTKTHREAD_enter"); +} + +static inline void rtw_thread_exit(_completion *comp) +{ + printf("%s", "RTKTHREAD_exit"); +} + +#include /* for RFHIGHPID */ +static inline _thread_hdl_ rtw_thread_start(int (*threadfn)(void *data), + void *data, const char namefmt[]) +{ + _thread_hdl_ _rtw_thread = NULL; + struct proc *p; + struct thread *td; + + _rtw_thread = kproc_kthread_add(mp_xmit_packet_thread, data, + &p, &td, RFHIGHPID, 0, namefmt, namefmt); + + if (_rtw_thread < 0) + _rtw_thread = NULL; + return _rtw_thread; +} + +static inline bool rtw_thread_stop(_thread_hdl_ th) +{ + return _FALSE; +} +static inline void rtw_thread_wait_stop(void) +{ + +} +__inline static void flush_signals_thread(void) +{ + +} + +#define rtw_dump_stack(void) do {} while (0) +#define rtw_bug_on(condition) do {} while (0) +#define rtw_warn_on(condition) do {} while (0) +#define rtw_sprintf(buf, size, format, arg...) do {} while (0) + +#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) #define rtw_free_netdev(netdev) if_free((netdev)) +#define RTW_DIV_ROUND_UP(n, d) (((n) + (d - 1)) / d) + #define NDEV_FMT "%s" #define NDEV_ARG(ndev) "" #define ADPT_FMT "%s" diff --git a/include/osdep_service_linux.h b/include/osdep_service_linux.h index fca4cf6..56ca96c 100644 --- a/include/osdep_service_linux.h +++ b/include/osdep_service_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -25,7 +25,7 @@ #include #include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5)) - #include +#include #endif /* #include */ #include @@ -37,9 +37,9 @@ #include #include #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) - #include +#include #else - #include +#include #endif #include #include @@ -56,41 +56,43 @@ #include #include +#ifdef CONFIG_RECV_THREAD_MODE #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) - #include +#include /* struct sched_param */ +#endif #endif #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41)) - #include +#include #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) - #include +#include #else - #include +#include #endif #ifdef RTK_DMP_PLATFORM - #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) - #include - #endif - #include +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) +#include +#endif +#include #endif #ifdef CONFIG_NET_RADIO - #define CONFIG_WIRELESS_EXT +#define CONFIG_WIRELESS_EXT #endif /* Monitor mode */ #include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) - #include +#include #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \ LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) - #define CONFIG_IEEE80211_HT_ADDT_INFO +#define CONFIG_IEEE80211_HT_ADDT_INFO #endif #ifdef CONFIG_IOCTL_CFG80211 @@ -104,34 +106,23 @@ #ifdef CONFIG_HAS_EARLYSUSPEND - #include +#include #endif /* CONFIG_HAS_EARLYSUSPEND */ #ifdef CONFIG_EFUSE_CONFIG_FILE - #include +#include #endif #ifdef CONFIG_USB_HCI - #include - #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) - #include - #else - #include - #endif +#include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) +#include +#else +#include #endif - -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - #include - #include - #include - #include - #include -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - -#ifdef CONFIG_USB_HCI - typedef struct urb *PURB; #endif + #if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI)) #error "Enable NAPI before enable GRO\n" @@ -153,36 +144,309 @@ #endif +#define ATOMIC_T atomic_t + +#ifdef DBG_MEMORY_LEAK +extern ATOMIC_T _malloc_cnt; +extern ATOMIC_T _malloc_size; +#endif + +static inline void *_rtw_vmalloc(u32 sz) +{ + void *pbuf; + + pbuf = vmalloc(sz); + +#ifdef DBG_MEMORY_LEAK + if (pbuf != NULL) { + atomic_inc(&_malloc_cnt); + atomic_add(sz, &_malloc_size); + } +#endif /* DBG_MEMORY_LEAK */ + + return pbuf; +} + +static inline void *_rtw_zvmalloc(u32 sz) +{ + void *pbuf; + + pbuf = _rtw_vmalloc(sz); + if (pbuf != NULL) + memset(pbuf, 0, sz); + + return pbuf; +} + +static inline void _rtw_vmfree(void *pbuf, u32 sz) +{ + vfree(pbuf); + +#ifdef DBG_MEMORY_LEAK + atomic_dec(&_malloc_cnt); + atomic_sub(sz, &_malloc_size); +#endif /* DBG_MEMORY_LEAK */ +} + +static inline void *_rtw_malloc(u32 sz) +{ + void *pbuf = NULL; + + #ifdef RTK_DMP_PLATFORM + if (sz > 0x4000) + pbuf = dvr_malloc(sz); + else + #endif + pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +#ifdef DBG_MEMORY_LEAK + if (pbuf != NULL) { + atomic_inc(&_malloc_cnt); + atomic_add(sz, &_malloc_size); + } +#endif /* DBG_MEMORY_LEAK */ + + return pbuf; + +} + +static inline void *_rtw_zmalloc(u32 sz) +{ +#if 0 + void *pbuf = _rtw_malloc(sz); + + if (pbuf != NULL) + memset(pbuf, 0, sz); +#else + /*kzalloc in KERNEL_VERSION(2, 6, 14)*/ + void *pbuf = kzalloc( sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +#endif + return pbuf; +} + +static inline void _rtw_mfree(void *pbuf, u32 sz) +{ + #ifdef RTK_DMP_PLATFORM + if (sz > 0x4000) + dvr_free(pbuf); + else + #endif + kfree(pbuf); + +#ifdef DBG_MEMORY_LEAK + atomic_dec(&_malloc_cnt); + atomic_sub(sz, &_malloc_size); +#endif /* DBG_MEMORY_LEAK */ + +} + +#ifdef CONFIG_USB_HCI +typedef struct urb *PURB; + +static inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma) +{ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); + #else + return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); + #endif +} +static inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma) +{ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + usb_free_coherent(dev, size, addr, dma); + #else + usb_buffer_free(dev, size, addr, dma); + #endif +} +#endif /* CONFIG_USB_HCI */ + + +/*lock - spinlock*/ +typedef spinlock_t _lock; +static inline void _rtw_spinlock_init(_lock *plock) +{ + spin_lock_init(plock); +} +static inline void _rtw_spinlock_free(_lock *plock) +{ +} +static inline void _rtw_spinlock(_lock *plock) +{ + spin_lock(plock); +} +static inline void _rtw_spinunlock(_lock *plock) +{ + spin_unlock(plock); +} + +#if 0 +static inline void _rtw_spinlock_ex(_lock *plock) +{ + spin_lock(plock); +} + +static inline void _rtw_spinunlock_ex(_lock *plock) +{ + + spin_unlock(plock); +} +#endif +__inline static void _rtw_spinlock_irq(_lock *plock, unsigned long *flags) +{ + spin_lock_irqsave(plock, *flags); +} +__inline static void _rtw_spinunlock_irq(_lock *plock, unsigned long *flags) +{ + spin_unlock_irqrestore(plock, *flags); +} +__inline static void _rtw_spinlock_bh(_lock *plock) +{ + spin_lock_bh(plock); +} +__inline static void _rtw_spinunlock_bh(_lock *plock) +{ + spin_unlock_bh(plock); +} + + +/*lock - semaphore*/ typedef struct semaphore _sema; -typedef spinlock_t _lock; +static inline void _rtw_init_sema(_sema *sema, int init_val) +{ + sema_init(sema, init_val); +} +static inline void _rtw_free_sema(_sema *sema) +{ +} +static inline void _rtw_up_sema(_sema *sema) +{ + up(sema); +} +static inline u32 _rtw_down_sema(_sema *sema) +{ + if (down_interruptible(sema)) + return _FAIL; + else + return _SUCCESS; +} + +/*lock - mutex*/ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) typedef struct mutex _mutex; #else typedef struct semaphore _mutex; #endif -struct rtw_timer_list { - struct timer_list timer; - void (*function)(void *); - void *arg; -}; +static inline void _rtw_mutex_init(_mutex *pmutex) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_init(pmutex); +#else + init_MUTEX(pmutex); +#endif +} -typedef struct rtw_timer_list _timer; +static inline void _rtw_mutex_free(_mutex *pmutex) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_destroy(pmutex); +#else +#endif +} +__inline static int _rtw_mutex_lock_interruptible(_mutex *pmutex) +{ + int ret = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + /* mutex_lock(pmutex); */ + ret = mutex_lock_interruptible(pmutex); +#else + ret = down_interruptible(pmutex); +#endif + return ret; +} + +__inline static int _rtw_mutex_lock(_mutex *pmutex) +{ + int ret = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_lock(pmutex); +#else + down(pmutex); +#endif + return ret; +} + +__inline static void _rtw_mutex_unlock(_mutex *pmutex) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_unlock(pmutex); +#else + up(pmutex); +#endif +} + + +/*completion*/ typedef struct completion _completion; +static inline void _rtw_init_completion(_completion *comp) +{ + init_completion(comp); +} +static inline unsigned long _rtw_wait_for_comp_timeout(_completion *comp, unsigned long timeout) +{ + return wait_for_completion_timeout(comp, timeout); +} +static inline void _rtw_wait_for_comp(_completion *comp) +{ + return wait_for_completion(comp); +} struct __queue { struct list_head queue; _lock lock; }; -typedef struct sk_buff _pkt; typedef unsigned char _buffer; typedef struct __queue _queue; + + +/*list*/ +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + typedef struct list_head _list; +/* Caller must check if the list is empty before calling rtw_list_delete*/ +__inline static void rtw_list_delete(_list *plist) +{ + list_del_init(plist); +} + +__inline static _list *get_next(_list *list) +{ + return list->next; +} +__inline static _list *get_list_head(_queue *queue) +{ + return &(queue->queue); +} +#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member) /* hlist */ typedef struct hlist_head rtw_hlist_head; typedef struct hlist_node rtw_hlist_node; +#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member) +#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head) +#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member) +#else +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member) +#endif /* RCU */ typedef struct rcu_head rtw_rcu_head; @@ -198,174 +462,215 @@ typedef struct rcu_head rtw_rcu_head; /* rhashtable */ #include "../os_dep/linux/rtw_rhashtable.h" -typedef int _OS_STATUS; -/* typedef u32 _irqL; */ -typedef unsigned long _irqL; -typedef struct net_device *_nic_hdl; -typedef void *_thread_hdl_; -typedef int thread_return; -typedef void *thread_context; +/*thread*/ +typedef void *_thread_hdl_; +typedef int thread_return; +typedef void *thread_context; +struct thread_hdl{ + _thread_hdl_ thread_handler; + u8 thread_status; +}; +#define THREAD_STATUS_STARTED BIT(0) +#define THREAD_STATUS_STOPPED BIT(1) +#define RST_THREAD_STATUS(t) (t->thread_status = 0) +#define SET_THREAD_STATUS(t, s) (t->thread_status |= s) +#define CLR_THREAD_STATUS(t, cl) (t->thread_status &= ~(cl)) +#define CHK_THREAD_STATUS(t, ck) (t->thread_status & ck) typedef void timer_hdl_return; typedef void *timer_hdl_context; -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) - typedef struct work_struct _workitem; -#else - typedef struct tq_struct _workitem; -#endif +static inline void rtw_thread_enter(char *name) +{ + allow_signal(SIGTERM); +} + +static inline void rtw_thread_exit(_completion *comp) +{ + complete_and_exit(comp, 0); +} + +static inline _thread_hdl_ rtw_thread_start(int (*threadfn)(void *data), + void *data, const char namefmt[]) +{ + _thread_hdl_ _rtw_thread = NULL; + + _rtw_thread = kthread_run(threadfn, data, namefmt); + if (IS_ERR(_rtw_thread)) { + WARN_ON(!_rtw_thread); + _rtw_thread = NULL; + } + return _rtw_thread; +} +static inline bool rtw_thread_stop(_thread_hdl_ th) +{ + + return kthread_stop(th); +} +static inline void rtw_thread_wait_stop(void) +{ + #if 0 + while (!kthread_should_stop()) + rtw_msleep_os(10); + #else + set_current_state(TASK_INTERRUPTIBLE); + while (!kthread_should_stop()) { + schedule(); + set_current_state(TASK_INTERRUPTIBLE); + } + __set_current_state(TASK_RUNNING); + #endif +} + +static inline void flush_signals_thread(void) +{ + if (signal_pending(current)) + flush_signals(current); +} + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #endif typedef unsigned long systime; -typedef ktime_t sysptime; + +/*tasklet*/ typedef struct tasklet_struct _tasklet; +typedef void (*tasklet_fn_t)(unsigned long); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) -/* Porting from linux kernel, for compatible with old kernel. */ -static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) +#if 1 +static inline void rtw_tasklet_init(_tasklet *t, tasklet_fn_t func, + unsigned long data) { - return skb->tail; + tasklet_init(t, func, data); } - -static inline void skb_reset_tail_pointer(struct sk_buff *skb) +static inline void rtw_tasklet_kill(_tasklet *t) { - skb->tail = skb->data; + tasklet_kill(t); } -static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) +static inline void rtw_tasklet_schedule(_tasklet *t) { - skb->tail = skb->data + offset; + tasklet_schedule(t); } - -static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) +static inline void rtw_tasklet_hi_schedule(_tasklet *t) { - return skb->end; + tasklet_hi_schedule(t); } +#else +#define rtw_tasklet_init tasklet_init +#define rtw_tasklet_kill tasklet_kill +#define rtw_tasklet_schedule tasklet_schedule +#define rtw_tasklet_hi_schedule tasklet_hi_schedule #endif -__inline static void rtw_list_delete(_list *plist) +/*skb_buffer*/ +static inline struct sk_buff *_rtw_skb_alloc(u32 sz) { - list_del_init(plist); + return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); } -__inline static _list *get_next(_list *list) +static inline void _rtw_skb_free(struct sk_buff *skb) { - return list->next; + dev_kfree_skb_any(skb); } -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) - -#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member) - -#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member) -#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head) -#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) -#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member) -#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member) -#else -#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member) -#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member) -#endif - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +static inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) { - spin_lock_irqsave(plock, *pirqL); + return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); } -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +static inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) { - spin_unlock_irqrestore(plock, *pirqL); + return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); } -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +static inline int _rtw_skb_linearize(struct sk_buff *skb) { - spin_lock_irqsave(plock, *pirqL); + return skb_linearize(skb); } -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +static inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb) { - spin_unlock_irqrestore(plock, *pirqL); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) + return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +#else + return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +#endif } -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) +/* Porting from linux kernel, for compatible with old kernel. */ +static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) { - spin_lock_bh(plock); + return skb->tail; } -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +static inline void skb_reset_tail_pointer(struct sk_buff *skb) { - spin_unlock_bh(plock); + skb->tail = skb->data; } -__inline static void enter_critical_bh(_lock *plock) +static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) { - spin_lock_bh(plock); + skb->tail = skb->data + offset; } -__inline static void exit_critical_bh(_lock *plock) +static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) { - spin_unlock_bh(plock); + return skb->end; } - -__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - int ret = 0; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) - /* mutex_lock(pmutex); */ - ret = mutex_lock_interruptible(pmutex); -#else - ret = down_interruptible(pmutex); #endif - return ret; +static inline u8 *rtw_skb_data(struct sk_buff *pkt) +{ + return pkt->data; } - -__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL) +static inline u32 rtw_skb_len(struct sk_buff *pkt) { - int ret = 0; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) - mutex_lock(pmutex); -#else - down(pmutex); -#endif - return ret; + return pkt->len; } -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +static inline void *rtw_skb_put_zero(struct sk_buff *skb, unsigned int len) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) - mutex_unlock(pmutex); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0) + return skb_put_zero(skb, len); #else - up(pmutex); + void *tmp = skb_put(skb, len); + + memset(tmp, 0, len); + + return tmp; #endif } -__inline static _list *get_list_head(_queue *queue) -{ - return &(queue->queue); -} +/*timer*/ +typedef struct rtw_timer_list _timer; +struct rtw_timer_list { + struct timer_list timer; + void (*function)(void *); + void *arg; +}; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) static inline void timer_hdl(struct timer_list *in_timer) -#else -static inline void timer_hdl(unsigned long cntx) -#endif { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) _timer *ptimer = from_timer(ptimer, in_timer, timer); + + ptimer->function(ptimer->arg); +} #else +static inline void timer_hdl(unsigned long cntx) +{ _timer *ptimer = (_timer *)cntx; -#endif + ptimer->function(ptimer->arg); } +#endif -__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) +__inline static void _init_timer(_timer *ptimer, void *pfunc, void *cntx) { ptimer->function = pfunc; ptimer->arg = cntx; @@ -395,6 +700,13 @@ __inline static void _cancel_timer_async(_timer *ptimer) del_timer(&ptimer->timer); } +/*work*/ +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) +typedef struct work_struct _workitem; +#else +typedef struct tq_struct _workitem; +#endif + static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)) @@ -428,7 +740,6 @@ __inline static void _cancel_workitem_sync(_workitem *pwork) /* * Global Mutex: can only be used at PASSIVE level. * */ - #define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ { \ while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \ @@ -442,6 +753,8 @@ __inline static void _cancel_workitem_sync(_workitem *pwork) atomic_dec((atomic_t *)&(_MutexCounter)); \ } + +typedef struct net_device *_nic_hdl; static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) @@ -454,6 +767,61 @@ static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) #endif } +#ifdef CONFIG_HWSIM +int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); +#else +static inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) +{ +#if defined(CONFIG_RTW_FC_FASTFWD) +extern int fwdEngine_wifi_rx(struct sk_buff *skb); +enum { + RE8670_RX_STOP=0, + RE8670_RX_CONTINUE, + RE8670_RX_STOP_SKBNOFREE, + RE8670_RX_END +}; +int ret = 0; + + skb->dev = ndev; + skb->data-=14; + skb->len+=14; + + ret = fwdEngine_wifi_rx(skb); + + if(ret==RE8670_RX_CONTINUE) + { + skb->data+=14; + skb->len-=14; + return netif_rx(skb); +} + else if(ret==RE8670_RX_STOP) + { + kfree_skb(skb); + } + + return 0; +#else + skb->dev = ndev; + return netif_rx(skb); +#endif +} +#endif + +#ifdef CONFIG_RTW_NAPI +static inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb) +{ + skb->dev = ndev; + return netif_receive_skb(skb); +} + +#ifdef CONFIG_RTW_GRO +static inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb) +{ + return napi_gro_receive(napi, skb); +} +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + static inline void rtw_netif_wake_queue(struct net_device *pnetdev) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) @@ -524,9 +892,68 @@ static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, con #define PATH_LENGTH_MAX PATH_MAX /* Atomic integer operations */ -#define ATOMIC_T atomic_t +static inline void ATOMIC_SET(ATOMIC_T *v, int i) +{ + atomic_set(v, i); +} -#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) +static inline int ATOMIC_READ(ATOMIC_T *v) +{ + return atomic_read(v); +} + +static inline void ATOMIC_ADD(ATOMIC_T *v, int i) +{ + atomic_add(i, v); +} +static inline void ATOMIC_SUB(ATOMIC_T *v, int i) +{ + atomic_sub(i, v); +} + +static inline void ATOMIC_INC(ATOMIC_T *v) +{ + atomic_inc(v); +} + +static inline void ATOMIC_DEC(ATOMIC_T *v) +{ + atomic_dec(v); +} + +static inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) +{ + return atomic_add_return(i, v); +} + +static inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) +{ + return atomic_sub_return(i, v); +} + +static inline int ATOMIC_INC_RETURN(ATOMIC_T *v) +{ + return atomic_inc_return(v); +} + +static inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) +{ + return atomic_dec_return(v); +} + +static inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) + return atomic_add_unless(v, 1, u); +#else + /* only make sure not exceed after this function */ + if (ATOMIC_INC_RETURN(v) > u) { + ATOMIC_DEC(v); + return 0; + } + return 1; +#endif +} #define NDEV_FMT "%s" #define NDEV_ARG(ndev) ndev->name @@ -537,6 +964,7 @@ static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, con #define FUNC_ADPT_FMT "%s(%s)" #define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL) +#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) struct rtw_netdev_priv_indicator { void *priv; u32 sizeof_priv; @@ -558,6 +986,15 @@ extern struct net_device *rtw_alloc_etherdev(int sizeof_priv); #define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name) #endif +static inline void rtw_dump_stack(void) +{ + dump_stack(); +} +#define rtw_bug_on(condition) BUG_ON(condition) +#define rtw_warn_on(condition) WARN_ON(condition) +#define RTW_DIV_ROUND_UP(n, d) DIV_ROUND_UP(n, d) +#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) + #define STRUCT_PACKED __attribute__ ((packed)) diff --git a/include/pci_ops.h b/include/pci_ops.h index 7b95fde..bc25d99 100644 --- a/include/pci_ops.h +++ b/include/pci_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,102 +15,55 @@ #ifndef __PCI_OPS_H_ #define __PCI_OPS_H_ +#ifdef RTK_129X_PLATFORM +#define PCIE_SLOT1_MEM_START 0x9804F000 +#define PCIE_SLOT1_MEM_LEN 0x1000 +#define PCIE_SLOT1_CTRL_START 0x9804EC00 -#ifdef CONFIG_RTL8188E - u32 rtl8188ee_init_desc_ring(_adapter *padapter); - u32 rtl8188ee_free_desc_ring(_adapter *padapter); - void rtl8188ee_reset_desc_ring(_adapter *padapter); - int rtl8188ee_interrupt(PADAPTER Adapter); - void rtl8188ee_xmit_tasklet(void *priv); - void rtl8188ee_recv_tasklet(void *priv); - void rtl8188ee_prepare_bcn_tasklet(void *priv); - void rtl8188ee_set_intf_ops(struct _io_ops *pops); - void rtw8188ee_unmap_beacon_icf(_adapter *padapter); -#endif +#define PCIE_SLOT2_MEM_START 0x9803C000 +#define PCIE_SLOT2_MEM_LEN 0x1000 +#define PCIE_SLOT2_CTRL_START 0x9803BC00 -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - u32 rtl8812ae_init_desc_ring(_adapter *padapter); - u32 rtl8812ae_free_desc_ring(_adapter *padapter); - void rtl8812ae_reset_desc_ring(_adapter *padapter); - int rtl8812ae_interrupt(PADAPTER Adapter); - void rtl8812ae_xmit_tasklet(void *priv); - void rtl8812ae_recv_tasklet(void *priv); - void rtl8812ae_prepare_bcn_tasklet(void *priv); - void rtl8812ae_set_intf_ops(struct _io_ops *pops); - void rtw8812ae_unmap_beacon_icf(_adapter *padapter); +#define PCIE_MASK_OFFSET 0x100 /* mask offset from CTRL_START */ +#define PCIE_TRANSLATE_OFFSET 0x104 /* translate offset from CTRL_START */ #endif -#ifdef CONFIG_RTL8192E - u32 rtl8192ee_init_desc_ring(_adapter *padapter); - u32 rtl8192ee_free_desc_ring(_adapter *padapter); - void rtl8192ee_reset_desc_ring(_adapter *padapter); - void rtl8192ee_recv_tasklet(void *priv); - void rtl8192ee_prepare_bcn_tasklet(void *priv); - int rtl8192ee_interrupt(PADAPTER Adapter); - void rtl8192ee_set_intf_ops(struct _io_ops *pops); - void rtw8192ee_unmap_beacon_icf(_adapter *padapter); -#endif +#define PCI_BC_CLK_REQ BIT0 +#define PCI_BC_ASPM_L0s BIT1 +#define PCI_BC_ASPM_L1 BIT2 +#define PCI_BC_ASPM_L1Off BIT3 +//#define PCI_BC_ASPM_LTR BIT4 +//#define PCI_BC_ASPM_OBFF BIT5 -#ifdef CONFIG_RTL8192F - u32 rtl8192fe_init_desc_ring(_adapter *padapter); - u32 rtl8192fe_free_desc_ring(_adapter *padapter); - void rtl8192fe_reset_desc_ring(_adapter *padapter); - int rtl8192fe_interrupt(PADAPTER Adapter); - void rtl8192fe_recv_tasklet(void *priv); - void rtl8192fe_prepare_bcn_tasklet(void *priv); - void rtl8192fe_set_intf_ops(struct _io_ops *pops); - u8 check_tx_desc_resource(_adapter *padapter, int prio); - void rtl8192fe_unmap_beacon_icf(PADAPTER Adapter); -#endif +void PlatformClearPciPMEStatus(_adapter *adapter); -#ifdef CONFIG_RTL8723B - u32 rtl8723be_init_desc_ring(_adapter *padapter); - u32 rtl8723be_free_desc_ring(_adapter *padapter); - void rtl8723be_reset_desc_ring(_adapter *padapter); - int rtl8723be_interrupt(PADAPTER Adapter); - void rtl8723be_recv_tasklet(void *priv); - void rtl8723be_prepare_bcn_tasklet(void *priv); - void rtl8723be_set_intf_ops(struct _io_ops *pops); - void rtl8723be_unmap_beacon_icf(PADAPTER Adapter); +#ifdef CONFIG_64BIT_DMA + u8 PlatformEnableDMA64(_adapter *adapter); #endif +#ifdef CONFIG_PCI_DYNAMIC_ASPM +void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode); +void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode); -#ifdef CONFIG_RTL8723D - u32 rtl8723de_init_desc_ring(_adapter *padapter); - u32 rtl8723de_free_desc_ring(_adapter *padapter); - void rtl8723de_reset_desc_ring(_adapter *padapter); - int rtl8723de_interrupt(PADAPTER Adapter); - void rtl8723de_recv_tasklet(void *priv); - void rtl8723de_prepare_bcn_tasklet(void *priv); - void rtl8723de_set_intf_ops(struct _io_ops *pops); - u8 check_tx_desc_resource(_adapter *padapter, int prio); - void rtl8723de_unmap_beacon_icf(PADAPTER Adapter); -#endif +static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); -#ifdef CONFIG_RTL8814A - u32 rtl8814ae_init_desc_ring(_adapter *padapter); - u32 rtl8814ae_free_desc_ring(_adapter *padapter); - void rtl8814ae_reset_desc_ring(_adapter *padapter); - int rtl8814ae_interrupt(PADAPTER Adapter); - void rtl8814ae_xmit_tasklet(void *priv); - void rtl8814ae_recv_tasklet(void *priv); - void rtl8814ae_prepare_bcn_tasklet(void *priv); - void rtl8814ae_set_intf_ops(struct _io_ops *pops); - void rtl8814ae_unmap_beacon_icf(PADAPTER Adapter); -#endif + if (mode == pcipriv->aspm_mode) + return; -#ifdef CONFIG_RTL8822B - void rtl8822be_set_intf_ops(struct _io_ops *pops); -#endif + pcipriv->aspm_mode = mode; -#ifdef CONFIG_RTL8821C - void rtl8821ce_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL + rtw_pci_set_aspm_lnkctl(padapter, mode); #endif - -#ifdef CONFIG_RTL8822C - void rtl8822ce_set_intf_ops(struct _io_ops *pops); -#endif - -#ifdef CONFIG_RTL8814B - void rtl8814be_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY + rtw_pci_set_l1_latency(padapter, mode); #endif +} +#else +#define rtw_pci_dynamic_aspm_set_mode(adapter, mode) #endif + + +#endif /*__PCI_OPS_H_*/ diff --git a/include/pci_ops_linux.h b/include/pci_ops_linux.h new file mode 100644 index 0000000..37f7c12 --- /dev/null +++ b/include/pci_ops_linux.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PCI_OPS_LINUX_H__ +#define __PCI_OPS_LINUX_H__ + +u8 os_pci_read8(struct dvobj_priv *dvobj, u32 addr); +u16 os_pci_read16(struct dvobj_priv *dvobj, u32 addr); +u32 os_pci_read32(struct dvobj_priv *dvobj, u32 addr); +int os_pci_write8(struct dvobj_priv *dvobj, u32 addr, u8 val); +int os_pci_write16(struct dvobj_priv *dvobj, u32 addr, u16 val); +int os_pci_write32(struct dvobj_priv *dvobj, u32 addr, u32 val); +#endif /*__PCI_OPS_LINUX_H__*/ diff --git a/include/phl_api_tmp.h b/include/phl_api_tmp.h new file mode 100644 index 0000000..52893c4 --- /dev/null +++ b/include/phl_api_tmp.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_API_TMP_H_ +#define __PHL_API_TMP_H_ + + +#ifdef CONFIG_SDIO_HCI +static inline void rtw_hal_sd_f0_reg_dump(void *sel, void *h){ }; +static inline void rtw_hal_sdio_local_reg_dump(void *sel, void *h){ }; +#endif + +static inline u32 rtw_hal_get_txdesc_len(void *h, + struct pkt_attrib *attrib){return 0;}; + + + +#ifdef CONFIG_PCI_HCI +static inline u8 rtw_hal_pci_check_enough_txdesc(void *h, u8 queue_id) +{ + return 0; +} +#endif + +#endif /*__PHL_API_TMP_H_*/ diff --git a/include/recv_osdep.h b/include/recv_osdep.h index 4521c00..df8b086 100644 --- a/include/recv_osdep.h +++ b/include/recv_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,15 +15,16 @@ #ifndef __RECV_OSDEP_H_ #define __RECV_OSDEP_H_ +u8 rtw_init_recv_info(_adapter *adapter); +sint rtw_init_recv_priv(struct dvobj_priv *dvobj); +void rtw_free_recv_priv(struct dvobj_priv *dvobj); -extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); -extern void _rtw_free_recv_priv(struct recv_priv *precvpriv); - - +#if 0 extern s32 rtw_recv_entry(union recv_frame *precv_frame); +#endif void rtw_rframe_set_os_pkt(union recv_frame *rframe); extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); -extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt); +extern void rtw_recv_returnpacket(_nic_hdl cnxt, struct sk_buff *preturnedpkt); #ifdef CONFIG_WIFI_MONITOR extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame); @@ -37,24 +38,27 @@ struct sta_info; extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup); -int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); -int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); +int rtw_os_recv_resource_init(struct recv_priv *precvpriv); +int rtw_os_recv_resource_alloc(union recv_frame *precvframe); void rtw_os_recv_resource_free(struct recv_priv *precvpriv); -int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb); -int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb); +int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, + u8 *pdata, struct sk_buff *pskb); +int rtw_os_recvframe_duplicate_skb(_adapter *padapter, + union recv_frame *pcloneframe, struct sk_buff *pskb); void rtw_os_free_recvframe(union recv_frame *precvframe); -int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, u32 size); +#if 0 +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); +#endif -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa +struct sk_buff *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa , u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl); -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe); - -void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); +void rtw_os_recv_indicate_pkt(_adapter *padapter, struct sk_buff *pkt, + union recv_frame *rframe); #ifdef PLATFORM_LINUX #ifdef CONFIG_RTW_NAPI diff --git a/include/rtw_android.h b/include/rtw_android.h index 9bb8e32..80dcac3 100644 --- a/include/rtw_android.h +++ b/include/rtw_android.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -73,6 +73,9 @@ enum ANDROID_WIFI_CMD { ANDROID_WIFI_CMD_SET_AEK, ANDROID_WIFI_CMD_EXT_AUTH_STATUS, ANDROID_WIFI_CMD_DRIVERVERSION, +#ifdef ROKU_PRIVATE + ANDROID_WIFI_CMD_ROKU_FIND_REMOTE, +#endif ANDROID_WIFI_CMD_MAX }; @@ -106,12 +109,5 @@ static inline int rtw_android_wifictrl_func_add(void) static inline void rtw_android_wifictrl_func_del(void) {} #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ -#ifdef CONFIG_GPIO_WAKEUP -#ifdef CONFIG_PLATFORM_INTEL_BYT -int wifi_configure_gpio(void); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ -void wifi_free_gpio(unsigned int gpio); -#endif /* CONFIG_GPIO_WAKEUP */ - #endif /* __RTW_ANDROID_H__ */ diff --git a/include/rtw_ap.h b/include/rtw_ap.h index 64cb1a8..e4644ad 100644 --- a/include/rtw_ap.h +++ b/include/rtw_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -30,13 +30,12 @@ u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period /* void update_BCNTIM(_adapter *padapter); */ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); +void rtw_remove_bcn_ie_ex(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8* pindex_ex, u8 index_ex_len); void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag); -#define update_beacon(adapter, ie_id, oui, tx, flags) _update_beacon((adapter), (ie_id), (oui), (tx), (flags), __func__) -/*update_beacon - (flags) can set to normal enqueue (0) and RTW_CMDF_WAIT_ACK enqueue. +#define rtw_update_beacon(adapter, ie_id, oui, tx, flags) _update_beacon((adapter), (ie_id), (oui), (tx), (flags), __func__) +/*rtw_update_beacon - (flags) can set to normal enqueue (0) and RTW_CMDF_WAIT_ACK enqueue. (flags) = RTW_CMDF_DIRECTLY is not currently implemented, it will do normal enqueue.*/ -void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta); - void expire_timeout_chk(_adapter *padapter); void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); @@ -63,17 +62,17 @@ void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); void sta_info_update(_adapter *padapter, struct sta_info *psta); -void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); -u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue); +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue, u8 disassoc); int rtw_sta_flush(_adapter *padapter, bool enqueue); int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); void start_ap_mode(_adapter *padapter); void stop_ap_mode(_adapter *padapter); #endif +void rtw_ap_update_clients_rainfo(struct _ADAPTER *a, enum phl_cmd_type flag); void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp - , s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow, bool *set_u_ch); + , s16 req_ch, s8 req_bw, s8 req_offset, struct rtw_chan_def *chdef); #ifdef CONFIG_AUTO_AP_MODE void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos); @@ -86,8 +85,13 @@ u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len); void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); +void rtw_ap_parse_sta_he_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len); + +void rtw_core_ap_start(_adapter *padapter, struct createbss_parm *parm); +void rtw_core_ap_swch_start(_adapter *padapter, struct createbss_parm *parm); + /* b2u flags */ #define RTW_AP_B2U_ALL BIT0 #define RTW_AP_B2U_GA_UCAST BIT1 /* WDS group addressed unicast frame, forward only */ @@ -109,14 +113,12 @@ void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *i void dump_ap_b2u_flags(void *sel, _adapter *adapter); -int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list); +int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, struct sk_buff *pkt, _list *f_list); int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta); int rtw_ap_rx_msdu_act_check(union recv_frame *rframe , const u8 *da, const u8 *sa , u8 *msdu, enum rtw_rx_llc_hdl llc_hdl - , struct xmit_frame **fwd_frame, _list *b2u_list); - -void update_bmc_sta(_adapter *padapter); + , struct xmit_frame **fwd_frame, _list *f_list); #ifdef CONFIG_BMC_TX_RATE_SELECT void rtw_update_bmc_sta_tx_rate(_adapter *adapter); @@ -129,15 +131,24 @@ int rtw_ht_operation_update(_adapter *padapter); #endif /* CONFIG_80211N_HT */ u8 rtw_ap_sta_states_check(_adapter *adapter); -#ifdef CONFIG_FW_HANDLE_TXBCN -#define rtw_ap_get_nums(adapter) (adapter_to_dvobj(adapter)->nr_ap_if) -bool rtw_ap_nums_check(_adapter *adapter); -#endif +void rtw_ap_set_sta_wmode(_adapter *padapter, struct sta_info *sta); -#ifdef CONFIG_SWTIMER_BASED_TXBCN -void tx_beacon_handlder(struct dvobj_priv *pdvobj); -void tx_beacon_timer_handlder(void *ctx); -#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ +#if defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) +void rtw_acs_start(_adapter *padapter); +void rtw_acs_stop(_adapter *padapter); +#endif /* defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) */ +void rtw_ap_set_edca(_adapter *padapter, enum rtw_ac ac, u32 param); +#ifdef CONFIG_AP_CMD_DISPR + +#define CMD_APSTART_ACQUIRE BIT0 +#define CMD_APSTOP_ACQUIRE BIT1 +#define CMD_APSTOP_STARTED BIT2 + +enum rtw_phl_status rtw_ap_start_cmd(struct cmd_obj *p); +enum rtw_phl_status rtw_ap_stop_cmd(struct cmd_obj *p); +enum rtw_phl_status rtw_free_bcn_entry(struct _ADAPTER *padapter); + +#endif #endif /* end of CONFIG_AP_MODE */ #endif /*__RTW_AP_H_*/ diff --git a/include/rtw_beamforming.h b/include/rtw_beamforming.h index 4c7f006..a5b0ecd 100644 --- a/include/rtw_beamforming.h +++ b/include/rtw_beamforming.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,281 +17,29 @@ #ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 -#define MAX_NUM_BEAMFORMEE_SU 2 -#define MAX_NUM_BEAMFORMER_SU 2 -#define MAX_NUM_BEAMFORMEE_MU 6 -#define MAX_NUM_BEAMFORMER_MU 1 - -#define MAX_BEAMFORMEE_ENTRY_NUM (MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU) -#define MAX_BEAMFORMER_ENTRY_NUM (MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU) - -/* Need to be defined by IC */ -#define SU_SOUNDING_TIMEOUT 5 /* unit: ms */ -#define MU_SOUNDING_TIMEOUT 8 /* unit: ms */ - -#define GET_BEAMFORM_INFO(adapter) (&GET_HAL_DATA(adapter)->beamforming_info) -#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod) ((_SoundPeriod)/(_MinSoundPeriod)) - -enum BEAMFORMING_CTRL_TYPE { - BEAMFORMING_CTRL_ENTER = 0, - BEAMFORMING_CTRL_LEAVE = 1, - BEAMFORMING_CTRL_START_PERIOD = 2, - BEAMFORMING_CTRL_END_PERIOD = 3, - BEAMFORMING_CTRL_SOUNDING_FAIL = 4, - BEAMFORMING_CTRL_SOUNDING_CLK = 5, - BEAMFORMING_CTRL_SET_GID_TABLE = 6, - BEAMFORMING_CTRL_SET_CSI_REPORT = 7, -}; - -enum _BEAMFORMING_STATE { - BEAMFORMING_STATE_IDLE, - BEAMFORMING_STATE_START, - BEAMFORMING_STATE_END, -}; - -/* - * typedef BEAMFORMING_CAP for phydm - */ -typedef enum beamforming_cap { - BEAMFORMING_CAP_NONE = 0x0, - BEAMFORMER_CAP_HT_EXPLICIT = 0x1, - BEAMFORMEE_CAP_HT_EXPLICIT = 0x2, - BEAMFORMER_CAP_VHT_SU = 0x4, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_SU = 0x8, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP_VHT_MU = 0x10, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_MU = 0x20, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP = 0x40, - BEAMFORMEE_CAP = 0x80, -} BEAMFORMING_CAP; - -enum _BEAMFORM_ENTRY_HW_STATE { - BEAMFORM_ENTRY_HW_STATE_NONE, - BEAMFORM_ENTRY_HW_STATE_ADD_INIT, - BEAMFORM_ENTRY_HW_STATE_ADDING, - BEAMFORM_ENTRY_HW_STATE_ADDED, - BEAMFORM_ENTRY_HW_STATE_DELETE_INIT, - BEAMFORM_ENTRY_HW_STATE_DELETING, - BEAMFORM_ENTRY_HW_STATE_MAX -}; - -/* The sounding state is recorded by BFer. */ -enum _SOUNDING_STATE { - SOUNDING_STATE_NONE = 0, - SOUNDING_STATE_INIT = 1, - SOUNDING_STATE_SU_START = 2, - SOUNDING_STATE_SU_SOUNDDOWN = 3, - SOUNDING_STATE_MU_START = 4, - SOUNDING_STATE_MU_SOUNDDOWN = 5, - SOUNDING_STATE_SOUNDING_TIMEOUT = 6, - SOUNDING_STATE_MAX -}; - -struct beamformee_entry { - u8 used; /* _TRUE/_FALSE */ - u8 txbf; - u8 sounding; - /* Used to construct AID field of NDPA packet */ - u16 aid; - /* Used to Set Reg42C in IBSS mode */ - u16 mac_id; - /* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */ - u16 p_aid; - u8 g_id; - /* Used to fill Reg6E4 to fill Mac address of CSI report frame */ - u8 mac_addr[ETH_ALEN]; - /* Sounding BandWidth */ - enum channel_width sound_bw; - u16 sound_period; - - enum beamforming_cap cap; - enum _BEAMFORM_ENTRY_HW_STATE state; - - /* The BFee need to be sounded when count to zero */ - u8 SoundCnt; - u8 bCandidateSoundingPeer; - u8 bSoundingTimeout; - u8 bDeleteSounding; - /* Get the result through throughput and Tx rate from BB API */ - u8 bApplySounding; - - /* information for sounding judgement */ - systime tx_timestamp; - u64 tx_bytes; - - u16 LogStatusFailCnt:5; /* 0~21 */ - u16 DefaultCSICnt:5; /* 0~21 */ - u8 CSIMatrix[327]; - u16 CSIMatrixLen; - - u8 NumofSoundingDim; - - u8 comp_steering_num_of_bfer; - - - /* SU-MIMO */ - u8 su_reg_index; - - /* MU-MIMO */ - u8 mu_reg_index; - u8 gid_valid[8]; - u8 user_position[16]; - - /* For 8822B C-cut workaround */ - /* If the flag set to _TRUE, do not sound this STA */ - u8 bSuspendSUCap; -}; - -struct beamformer_entry { - u8 used; - /* p_aid of BFer entry is probably not used */ - /* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */ - u16 p_aid; - u8 g_id; - u8 mac_addr[ETH_ALEN]; - - enum beamforming_cap cap; - enum _BEAMFORM_ENTRY_HW_STATE state; - - u8 NumofSoundingDim; - - /* SU-MIMO */ - u8 su_reg_index; - - /* MU-MIMO */ - u8 gid_valid[8]; - u8 user_position[16]; - u16 aid; -}; - -struct sounding_info { - u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU]; - u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU]; - - enum _SOUNDING_STATE state; - /* - * su_bfee_curidx is index for beamforming_info.bfee_entry[] - * range: 0~MAX_BEAMFORMEE_ENTRY_NUM - */ - u8 su_bfee_curidx; - u8 candidate_mu_bfee_cnt; - - /* For sounding schedule maintenance */ - u16 min_sounding_period; - /* Get from sounding list */ - /* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */ - u8 sound_remain_cnt_per_period; -}; - -struct _RT_CSI_INFO{ - u8 Nc; - u8 Nr; - u8 Ng; - u8 CodeBook; - u8 ChnlWidth; - u8 bVHT; -}; - -struct beamforming_info { - enum beamforming_cap beamforming_cap; - enum _BEAMFORMING_STATE beamforming_state; - struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM]; - struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM]; - u8 sounding_sequence; - u8 beamformee_su_cnt; - u8 beamformer_su_cnt; - u32 beamformee_su_reg_maping; - u32 beamformer_su_reg_maping; - /* For MU-MINO */ - u8 beamformee_mu_cnt; - u8 beamformer_mu_cnt; - u32 beamformee_mu_reg_maping; - u8 first_mu_bfee_index; - u8 mu_bfer_curidx; - u8 cur_csi_rpt_rate; - - struct sounding_info sounding_info; - /* schedule regular timer for sounding */ - _timer sounding_timer; - /* moniter if soudning too long */ - _timer sounding_timeout_timer; - - /* For HW configuration */ - u8 SetHalBFEnterOnDemandCnt; - u8 SetHalBFLeaveOnDemandCnt; - u8 SetHalSoundownOnDemandCnt; - u8 bSetBFHwConfigInProgess; - - /* - * Target CSI report info. - * Keep the first SU CSI report info for 8822B HW bug workaround. - */ - u8 bEnableSUTxBFWorkAround; - struct _RT_CSI_INFO TargetCSIInfo; - /* Only peform sounding to the first SU BFee */ - struct beamformee_entry *TargetSUBFee; - - /* For debug */ - s8 sounding_running; -}; - -enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id); -struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra); -struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra); -void rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *); -u32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *); -u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position); -void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *); -void rtw_bf_init(PADAPTER); -void rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf); -u8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue); -void rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *); -void rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len); -void rtw_bf_update_traffic(PADAPTER); - -/* Compatible with old function name, only for using outside rtw_beamforming.c */ -#define beamforming_get_entry_beam_cap_by_mac_id rtw_bf_bfee_get_entry_cap_by_macid -#define rtw_beamforming_get_ndpa_frame rtw_bf_get_ndpa_packet -#define rtw_beamforming_get_report_frame rtw_bf_get_report_packet -#define rtw_beamforming_get_vht_gid_mgnt_frame rtw_bf_get_vht_gid_mgnt_packet -#define beamforming_wk_hdl rtw_bf_cmd_hdl -#define beamforming_wk_cmd rtw_bf_cmd -#define update_attrib_txbf_info rtw_bf_update_attrib - -#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap) -#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap) - -#define IS_HT_BEAMFORMEE(adapter) \ - (HT_BF_CAP(adapter) & \ - (BEAMFORMING_HT_BEAMFORMEE_ENABLE)) - -#define IS_VHT_BEAMFORMEE(adapter) \ - (VHT_BF_CAP(adapter) & \ - (BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \ - BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) - -#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \ - IS_VHT_BEAMFORMEE(adapter)) - -#else /* !RTW_BEAMFORMING_VERSION_2 */ -/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/ -enum BEAMFORMING_CTRL_TYPE { - BEAMFORMING_CTRL_ENTER = 0, - BEAMFORMING_CTRL_LEAVE = 1, - BEAMFORMING_CTRL_START_PERIOD = 2, - BEAMFORMING_CTRL_END_PERIOD = 3, - BEAMFORMING_CTRL_SOUNDING_FAIL = 4, - BEAMFORMING_CTRL_SOUNDING_CLK = 5, -}; -u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame); -void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame); - -void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf); -u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue); -void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); - -#endif /* !RTW_BEAMFORMING_VERSION_2 */ - -#endif /*#ifdef CONFIG_BEAMFORMING */ - +#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_HT_BEAMFORMER_TEST BIT(2) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT(4)|BIT(5)) /*Sta Bfer's capability*/ +#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT(6)|BIT(7)) /*Sta BFee's capability*/ + +#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT(2) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT(3) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT(4) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT(8)|BIT(9)|BIT(10)) /*Sta BFee's capability*/ +#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT(12)|BIT(13)|BIT(14)) /*Sta Bfer's capability*/ + +#define BEAMFORMING_HE_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_HE_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_HE_MU_MIMO_AP_ENABLE BIT(2) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_HE_MU_MIMO_STA_ENABLE BIT(3) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_HE_BEAMFORMER_TEST BIT(4) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_HE_BEAMFORMER_STS_CAP (BIT(8)|BIT(9)|BIT(10)) /*Sta BFee's capability*/ +#define BEAMFORMING_HE_BEAMFORMEE_SOUND_DIM (BIT(12)|BIT(13)|BIT(14)) /*Sta Bfer's capability*/ + +void rtw_core_bf_watchdog(_adapter *padapter); + +#endif #endif /*__RTW_BEAMFORMING_H_*/ diff --git a/include/rtw_br_ext.h b/include/rtw_br_ext.h index 54ba75e..177b270 100644 --- a/include/rtw_br_ext.h +++ b/include/rtw_br_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -40,7 +40,7 @@ struct nat25_network_db_entry { struct nat25_network_db_entry *next_hash; struct nat25_network_db_entry **pprev_hash; - atomic_t use_count; + ATOMIC_T use_count; unsigned char macAddr[6]; unsigned long ageing_timer; unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; diff --git a/include/rtw_btc.h b/include/rtw_btc.h new file mode 100644 index 0000000..6d6bf35 --- /dev/null +++ b/include/rtw_btc.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2013 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifdef CONFIG_BTC + +#ifndef __RTW_BTC_H__ +#define __RTW_BTC_H__ + +#include + +#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) (RetCode & 0x0F) +#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode) (GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode) + +void rtw_btc_disp_btc_info(_adapter *, void* p_msgprn_hdl, u8 info_type); +void rtw_btc_set_dbg(_adapter *, u32 *pDbgModule); +u32 rtw_btc_get_dbg(_adapter *, u8 *pStrBuf, u32 bufSize); + +#if 0 +u16 rtw_btc_btreg_read(_adapter *padapter, u8 type, u16 addr, u32 *data); +u16 rtw_btc_btreg_write(_adapter *padapter, u8 type, u16 addr, u16 val); +#endif + +#endif /* __RTW_BTC_H__ */ +#endif /* CONFIG_BTC */ + diff --git a/include/rtw_byteorder.h b/include/rtw_byteorder.h index 8e6bb7a..8ac3b92 100644 --- a/include/rtw_byteorder.h +++ b/include/rtw_byteorder.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtw_cfg.h b/include/rtw_cfg.h new file mode 100644 index 0000000..3ade0c8 --- /dev/null +++ b/include/rtw_cfg.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_CFG_H_ +#define _RTW_CFG_H_ + +enum rtw_pwr_by_rate_setting { + RTW_PW_BY_RATE_ON = 0, + RTW_PW_BY_RATE_ALL_SAME = 1 +}; + +enum rtw_pwr_limit_type { + RTW_PWLMT_BY_EFUSE = 0, + RTW_PWLMT_DISABLE = 1, + RTW_PWBYRATE_AND_PWLMT = 2 +}; + +u8 rtw_load_dvobj_registry(struct dvobj_priv *dvobj); +uint rtw_load_registry(_adapter *adapter); + +void rtw_core_update_default_setting (struct dvobj_priv *dvobj); + +#define RTW_ADAPTIVITY_EN_DISABLE 0 +#define RTW_ADAPTIVITY_EN_ENABLE 1 +#define RTW_ADAPTIVITY_EN_AUTO 2 + +#define RTW_ADAPTIVITY_MODE_NORMAL 0 +#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1 + +void rtw_cfg_adaptivity_config_msg(void *sel, _adapter *adapter); +bool rtw_cfg_adaptivity_needed(_adapter *adapter); + +#endif /*_RTW_CFG_H_*/ diff --git a/include/rtw_cmd.h b/include/rtw_cmd.h index 4f49d92..f5c8d30 100644 --- a/include/rtw_cmd.h +++ b/include/rtw_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,7 +18,6 @@ #define C2H_MEM_SZ (16*1024) -#define FREE_CMDOBJ_SZ 128 #define MAX_CMDSZ 1536 #define MAX_RSPSZ 512 @@ -47,69 +46,30 @@ enum { }; struct cmd_priv { - _sema cmd_queue_sema; - /* _sema cmd_done_sema; */ - _sema start_cmdthread_sema; - - _queue cmd_queue; u8 cmd_seq; u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ u8 *cmd_allocated_buf; - u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ + u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ u8 *rsp_allocated_buf; u32 cmd_issued_cnt; - u32 cmd_done_cnt; - u32 rsp_cnt; - ATOMIC_T cmdthd_running; - /* u8 cmdthd_running; */ - _adapter *padapter; + struct dvobj_priv *dvobj; _mutex sctx_mutex; -}; + ATOMIC_T event_seq; + u32 evt_done_cnt; -#ifdef CONFIG_EVENT_THREAD_MODE -struct evt_obj { - u16 evtcode; - u8 res; - u8 *parmbuf; - u32 evtsz; - _list list; + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ + _queue cmd_queue; + _sema cmd_queue_sema; + _sema start_cmdthread_sema; + ATOMIC_T cmdthd_running; + #endif }; -#endif - -struct evt_priv { -#ifdef CONFIG_EVENT_THREAD_MODE - _sema evt_notify; - - _queue evt_queue; -#endif - -#ifdef CONFIG_FW_C2H_REG - #define CONFIG_C2H_WK -#endif - -#ifdef CONFIG_C2H_WK - _workitem c2h_wk; - bool c2h_wk_alive; - struct rtw_cbuf *c2h_queue; - #define C2H_QUEUE_MAX_LEN 10 -#endif - -#ifdef CONFIG_H2CLBK - _sema lbkevt_done; - u8 lbkevt_limit; - u8 lbkevt_num; - u8 *cmdevt_parm; -#endif - ATOMIC_T event_seq; - u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */ - u8 *evt_allocated_buf; - u32 evt_done_cnt; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - u8 *c2h_mem; - u8 *allocated_c2h_mem; -#endif +struct back_op_param { + unsigned int off_ch_dur; + unsigned int off_ch_ext_dur; /* extend when MGNT_TX */ + unsigned int on_ch_dur; }; #define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ @@ -162,47 +122,18 @@ struct P2P_WoWlan_Offload_t { #endif /* CONFIG_P2P_WOWLAN */ extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); -extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); -extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); -#ifdef CONFIG_EVENT_THREAD_MODE -extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); -extern struct evt_obj *rtw_dequeue_evt(_queue *queue); -extern void rtw_free_evt_obj(struct evt_obj *pcmd); -#endif +extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ void rtw_stop_cmd_thread(_adapter *adapter); thread_return rtw_cmd_thread(thread_context context); +#endif -extern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv); -extern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv); - -extern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv); -extern void rtw_free_evt_priv(struct evt_priv *pevtpriv); -extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); -extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); -#ifdef CONFIG_P2P -u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType); -#endif /* CONFIG_P2P */ - -#ifdef CONFIG_IOCTL_CFG80211 -struct rtw_roch_parm { - u64 cookie; - struct wireless_dev *wdev; - struct ieee80211_channel ch; - enum nl80211_channel_type ch_type; - unsigned int duration; -}; - -u8 rtw_roch_cmd(_adapter *adapter - , u64 cookie, struct wireless_dev *wdev - , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type - , unsigned int duration - , u8 flags -); - -u8 rtw_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags); +u32 rtw_init_cmd_priv(struct dvobj_priv *dvobj); +void rtw_free_cmd_priv(struct dvobj_priv *dvobj); +#ifdef CONFIG_IOCTL_CFG80211 u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags); struct mgnt_tx_parm { u8 tx_ch; @@ -214,39 +145,31 @@ struct mgnt_tx_parm { #endif enum rtw_drvextra_cmd_id { - NONE_WK_CID, + NONE_WK_CID, /*MCC_CMD_WK_CID*/ STA_MSTATUS_RPT_WK_CID, + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ DYNAMIC_CHK_WK_CID, + #endif DM_CTRL_WK_CID, PBC_POLLING_WK_CID, + #ifdef CONFIG_POWER_SAVING POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */ + #endif LPS_CTRL_WK_CID, ANT_SELECT_WK_CID, P2P_PS_WK_CID, - P2P_PROTO_WK_CID, CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */ C2H_WK_CID, - RTP_TIMER_CFG_WK_CID, RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */ FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */ DM_IN_LPS_WK_CID, - DM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */ - BEAMFORMING_WK_CID, LPS_CHANGE_DTIM_CID, - BTINFO_WK_CID, - BTC_REDUCE_WL_TXPWR_CID, DFS_RADAR_DETECT_WK_CID, DFS_RADAR_DETECT_EN_DEC_WK_CID, SESSION_TRACKER_WK_CID, - EN_HW_UPDATE_TSF_WK_CID, - PERIOD_TSF_UPDATE_END_WK_CID, TEST_H2C_CID, MP_CMD_WK_CID, CUSTOMER_STR_WK_CID, -#ifdef CONFIG_RTW_REPEATER_SON - RSON_SCAN_WK_CID, -#endif - ROCH_WK_CID, MGNT_TX_WK_CID, REQ_PER_CMD_WK_CID, SSMPS_WK_CID, @@ -259,6 +182,13 @@ enum rtw_drvextra_cmd_id { #endif #ifdef CONFIG_RTW_TOKEN_BASED_XMIT TBTX_CONTROL_TX_WK_CID, +#endif + TSF_SYNC_DONE_WK_CID, +#ifdef ROKU_PRIVATE + FIND_REMOTE_WK_CID, +#ifdef CONFIG_P2P + HIDE_SSID_WK_CID, +#endif #endif MAX_WK_CID }; @@ -291,18 +221,6 @@ enum RFINTFS { }; -/* -Caller Mode: Infra, Ad-Hoc - -Notes: To join the specified bss - -Command Event Mode - -*/ -struct joinbss_parm { - WLAN_BSSID_EX network; -}; - /* Caller Mode: Infra, Ad-HoC(C) @@ -331,6 +249,12 @@ struct createbss_parm { s16 req_ch; s8 req_bw; s8 req_offset; + u8 ifbmp_ch_changed; + u8 ch_to_set; + u8 offset_to_set; + u8 bw_to_set; + u8 do_rfk; + }; @@ -339,33 +263,6 @@ struct setopmode_parm { u8 rsvd[3]; }; -/* -Caller Mode: AP, Ad-HoC, Infra - -Notes: To ask RTL8711 performing site-survey - -Command-Event Mode - -*/ - -#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */ -#define RTW_CHANNEL_SCAN_AMOUNT (14+37) -struct sitesurvey_parm { - sint scan_mode; /* active: 1, passive: 0 */ - /* sint bsslimit; // 1 ~ 48 */ - u8 ssid_num; - u8 ch_num; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; - - u32 token; /* 80211k use it to identify caller */ - u16 duration; /* 0: use default, otherwise: channel scan time */ - u8 igi; /* 0: use defalut */ - u8 bw; /* 0: use default */ - - bool acs; /* aim to trigger channel selection when scan done */ - u8 reason; -}; /* Caller Mode: Any @@ -481,36 +378,6 @@ struct Tx_Beacon_param { */ -#ifdef CONFIG_H2CLBK - -struct seth2clbk_parm { - u8 mac[6]; - u16 s0; - u16 s1; - u32 w0; - u8 b0; - u16 s2; - u8 b1; - u32 w1; -}; - -struct geth2clbk_parm { - u32 rsv; -}; - -struct geth2clbk_rsp { - u8 mac[6]; - u16 s0; - u16 s1; - u32 w0; - u8 b0; - u16 s2; - u8 b1; - u32 w1; -}; - -#endif /* CONFIG_H2CLBK */ - /* CMD param Formart for driver extra cmd handler */ struct drvextra_cmd_parm { int ec_id; /* extra cmd id */ @@ -531,22 +398,39 @@ struct addBaRsp_parm { u8 addr[ETH_ALEN]; u8 status; u8 size; + struct ADDBA_request preq; }; struct set_ch_parm { u8 ch; u8 bw; u8 ch_offset; + u8 do_rfk; }; struct SetChannelPlan_param { enum regd_src_t regd_src; - const struct country_chplan *country_ent; + enum rtw_regd_inr inr; + struct country_chplan country_ent; + bool has_country; u8 channel_plan; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 channel_plan_6g; +#endif + +#ifdef CONFIG_80211D + /* used for regd_src == RTK_PRIV and inr == COUNTRY_IE */ + struct country_ie_slave_record cisr; + bool has_cisr; +#endif + +#ifdef PLATFORM_LINUX + bool rtnl_lock_needed; +#endif }; struct get_channel_plan_param { - struct get_chplan_resp **resp; + struct get_chplan_resp **chplan; }; struct LedBlink_param { @@ -563,11 +447,6 @@ struct RunInThread_param { void *context; }; -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW -struct write_bcnlen_param { - u16 bcn_len; -}; -#endif #define GEN_CMD_CODE(cmd) cmd ## _CMD_ @@ -597,12 +476,9 @@ struct write_bcnlen_param { #define H2C_ENQ_HEAD_FAIL 0x09 #define H2C_CMD_FAIL 0x0A -void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm); -u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm); -#ifdef CONFIG_AP_MODE + u8 rtw_create_ibss_cmd(_adapter *adapter, int flags); u8 rtw_startbss_cmd(_adapter *adapter, int flags); -#endif #define REQ_CH_NONE -1 #define REQ_CH_INT_INFO -2 @@ -610,6 +486,9 @@ u8 rtw_startbss_cmd(_adapter *adapter, int flags); #define REQ_BW_ORI -2 #define REQ_OFFSET_NONE -1 +u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags + , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset); + struct sta_info; extern u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue); extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue); @@ -617,8 +496,6 @@ extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enque extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork); u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags); #ifdef CONFIG_AP_MODE -u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags - , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset); u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags); #endif #ifdef CONFIG_RTW_TOKEN_BASED_XMIT @@ -627,12 +504,22 @@ u8 rtw_tx_control_cmd(_adapter *adapter); extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags); extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr); -extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq); +extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, + struct ADDBA_request *paddba_req, u8 status, u8 size, + u16 start_seq); +extern u8 rtw_delba_cmd(struct _ADAPTER *a, u8 *addr, u16 tid); /* add for CONFIG_IEEE80211W, none 11w also can use */ extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter); extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags); +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); - +#endif +#ifdef ROKU_PRIVATE +extern u8 rtw_find_remote_wk_cmd(_adapter *adapter); +#ifdef CONFIG_P2P +extern u8 rtw_hide_ssid_wk_cmd(_adapter *adapter); +#endif +#endif u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 flags); u8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags); #ifdef CONFIG_LPS_1T1R @@ -641,20 +528,15 @@ u8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags); u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter); u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim); -#if (RATE_ADAPTIVE_SUPPORT == 1) -u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime); -#endif - #ifdef CONFIG_ANTENNA_DIVERSITY extern u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue); #endif -u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta); - +#ifdef CONFIG_POWER_SAVING extern u8 rtw_ps_cmd(_adapter *padapter); - +#endif #if CONFIG_DFS -void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj); +void rtw_dfs_ch_switch_hdl(_adapter *adapter); #endif #ifdef CONFIG_AP_MODE @@ -667,27 +549,34 @@ u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter); #endif /* CONFIG_DFS_MASTER */ #endif /* CONFIG_AP_MODE */ -#ifdef CONFIG_BT_COEXIST -u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +#ifdef CONFIG_BTC +u8 rtw_btinfo_cmd(_adapter *padapter, u8 *pbuf, u16 length); u8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val); #endif u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len); - -u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter); -u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter); +#if defined(RTW_PHL_DBG_CMD) +void core_cmd_phl_handler(_adapter *adapter, char *extra); +void core_add_record(_adapter *adapter, u8 type, void *p); +void phl_add_record(void *d, u8 type, void *p, u32 size); +#endif u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags); -u8 rtw_iqk_cmd(_adapter *padapter, u8 flags); -u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig); -u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig); +u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 chplan_6g, enum rtw_regd_inr inr); +u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, enum rtw_regd_inr inr); #ifdef CONFIG_REGD_SRC_FROM_OS -u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region); +u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region, enum rtw_regd_inr inr); +#endif +u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **chplan); + +#ifdef CONFIG_80211D +u8 rtw_apply_recv_country_ie_cmd(_adapter *adapter, int flags, enum band_type band,u8 opch, const u8 *country_ie); #endif -u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **resp); -extern u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed); +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD +u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed); +#endif extern u8 rtw_set_csa_cmd(_adapter *adapter); extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option); @@ -698,18 +587,7 @@ u8 rtw_customer_str_req_cmd(_adapter *adapter); u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr); #endif -#ifdef CONFIG_FW_C2H_REG -u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt); -#endif -#ifdef CONFIG_FW_C2H_PKT u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length); -#endif - -#ifdef CONFIG_RTW_REPEATER_SON -#define RSON_SCAN_PROCESS 10 -#define RSON_SCAN_DISABLE 11 -u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op); -#endif u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context); u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms); @@ -733,18 +611,13 @@ u8 rtw_req_per_cmd(_adapter * adapter); u8 rtw_tbtx_chk_cmd(_adapter *adapter); u8 rtw_tbtx_token_dispatch_cmd(_adapter *adapter); #endif - -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW -u8 rtw_write_bcnlen_to_fw_cmd(_adapter *padapter, u16 bcn_len); -#endif - #ifdef CONFIG_CTRL_TXSS_BY_TP struct txss_cmd_parm { struct sta_info *sta; bool tx_1ss; }; -void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta); +void rtw_ctrl_txss_update(_adapter *adapter, struct sta_info *sta); u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss); void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer); @@ -755,7 +628,6 @@ void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss); u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); -extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); void rtw_create_ibss_post_hdl(_adapter *padapter, int status); @@ -763,6 +635,8 @@ extern void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pc extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +void rtw_run_cmd(_adapter *padapter, struct cmd_obj *pcmd, bool discard); +u32 rtw_get_turbo_edca(_adapter *padapter, u8 aifs, u8 ecwmin, u8 ecwmax, u8 txop); enum rtw_cmd_id { CMD_JOINBSS, /*0*/ @@ -771,8 +645,10 @@ enum rtw_cmd_id { CMD_SET_OPMODE, /*3*/ CMD_SITE_SURVEY, /*4*/ CMD_SET_AUTH, /*5*/ +#ifndef CONFIG_CMD_DISP CMD_SET_KEY, /*6*/ CMD_SET_STAKEY, /*7*/ +#endif CMD_ADD_BAREQ, /*8*/ CMD_SET_CHANNEL, /*9*/ CMD_TX_BEACON, /*10*/ @@ -787,9 +663,8 @@ enum rtw_cmd_id { CMD_ADD_BARSP, /*19*/ CMD_RM_POST_EVENT, /*20*/ CMD_SET_MESH_PLINK_STATE, /* 21 */ - CMD_DO_IQK, /* 22 */ + CMD_DELBA, /* 22 */ CMD_GET_CHANPLAN, /*23*/ - CMD_WRITE_BCN_LEN, /*24 */ CMD_ID_MAX }; @@ -799,4 +674,10 @@ enum rtw_cmd_id { (cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == CMD_SET_MLME_EVT ? ((struct rtw_evt_header *)(cmd)->parmbuf)->id : 0), \ (cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0 +#ifdef CONFIG_CMD_GENERAL +void rtw_dynamic_chk_wk_sw_hdl(_adapter *padapter); +void rtw_dynamic_chk_wk_hw_hdl(_adapter *padapter); +#else +void rtw_dynamic_chk_wk_hdl(_adapter *padapter); +#endif #endif /* _CMD_H_ */ diff --git a/include/rtw_csa.h b/include/rtw_csa.h new file mode 100644 index 0000000..72b4bc5 --- /dev/null +++ b/include/rtw_csa.h @@ -0,0 +1,91 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_CSA_H_ +#define __RTW_CSA_H_ + +#if CONFIG_DFS +#define CSA_IE_LEN 3 /* Length of Channel Switch element */ +#define CSA_SWITCH_MODE 0 +#define CSA_NEW_CH 1 +#define CSA_SWITCH_COUNT 2 +#define MAX_CSA_CNT 10 + +#define CS_WR_DATA_LEN 5 /* Length of Channel Switch Wrapper element */ + +void reset_csa_param(struct rf_ctl_t *rfctl); +bool rtw_get_csa_setting(struct dvobj_priv *d, s16 *req_ch, u8 *req_bw, u8 *req_offset); + +#ifdef CONFIG_ECSA_PHL +#define MCC_ECSA_DELAY_START_TIME 30000 /* ms */ + +enum ecsa_state_t { + ECSA_ST_NONE, + ECSA_ST_SW_START, /* ready to switch */ + ECSA_ST_SW_DONE /* switch done */ +}; + +struct core_ecsa_info { + enum ecsa_state_t state; + u32 ecsa_allow_case; + u32 ecsa_delay_time; + + /* @channel_width defined in 802.11-2016, Table 9-252 VHT operation information subfields + * 0 for 20 MHz or 40 MHz + * 1 for 80 MHz, 160 MHz or 80+80 MHz + * 2 for 160 MHz (deprecated) + * 3 for non-contiguous 80+80 MHz (deprecated) + */ + u8 channel_width; + struct createbss_parm *bss_param; + struct rtw_phl_ecsa_param phl_ecsa_param; +}; + +__inline static void set_ecsa_state(struct core_ecsa_info *ecsa_info, enum ecsa_state_t state) +{ + ecsa_info->state = state; +} + +__inline static bool check_ecsa_state(struct core_ecsa_info *ecsa_info, enum ecsa_state_t state) +{ + if (ecsa_info->state == state) + return _TRUE; + return _FALSE; +} + +#define SET_ECSA_STATE(adapter, state) set_ecsa_state(&((adapter)->ecsa_info), (state)) +#define CHK_ECSA_STATE(adapter, state) check_ecsa_state(&((adapter)->ecsa_info), (state)) + +bool rtw_mr_is_ecsa_running(struct _ADAPTER *a); +void rtw_ecsa_update_probe_resp(struct xmit_frame *xframe); +void rtw_ecsa_update_beacon(void *priv, struct rtw_wifi_role_t *role); +bool rtw_ap_check_ecsa_allow( + void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def, + enum phl_ecsa_start_reason reason, + u32 *delay_start_ms +); +void rtw_ecsa_mr_update_chan_info_by_role( + void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def new_chan_def +); +bool rtw_ecsa_check_tx_resume_allow(void *priv, struct rtw_wifi_role_t *role); +void rtw_ecsa_complete(void *priv, struct rtw_wifi_role_t *role); +void rtw_trigger_phl_ecsa_start(struct _ADAPTER *a); +#endif /* CONFIG_ECSA_PHL */ +#endif /* CONFIG_DFS */ + +#endif diff --git a/include/rtw_debug.h b/include/rtw_debug.h index 1ce9af3..2825736 100644 --- a/include/rtw_debug.h +++ b/include/rtw_debug.h @@ -28,37 +28,18 @@ enum { #define DRIVER_PREFIX "RTW: " -#ifdef PLATFORM_OS_CE -extern void rtl871x_cedbg(const char *fmt, ...); -#endif - -#ifdef PLATFORM_WINDOWS - #define RTW_PRINT do {} while (0) - #define RTW_ERR do {} while (0) - #define RTW_WARN do {} while (0) - #define RTW_INFO do {} while (0) - #define RTW_DBG do {} while (0) - #define RTW_PRINT_SEL do {} while (0) - #define _RTW_PRINT do {} while (0) - #define _RTW_ERR do {} while (0) - #define _RTW_WARN do {} while (0) - #define _RTW_INFO do {} while (0) - #define _RTW_DBG do {} while (0) - #define _RTW_PRINT_SEL do {} while (0) -#else - #define RTW_PRINT(x, ...) do {} while (0) - #define RTW_ERR(x, ...) do {} while (0) - #define RTW_WARN(x,...) do {} while (0) - #define RTW_INFO(x,...) do {} while (0) - #define RTW_DBG(x,...) do {} while (0) - #define RTW_PRINT_SEL(x,...) do {} while (0) - #define _RTW_PRINT(x, ...) do {} while (0) - #define _RTW_ERR(x, ...) do {} while (0) - #define _RTW_WARN(x,...) do {} while (0) - #define _RTW_INFO(x,...) do {} while (0) - #define _RTW_DBG(x,...) do {} while (0) - #define _RTW_PRINT_SEL(x,...) do {} while (0) -#endif +#define RTW_PRINT(x, ...) do {} while (0) +#define RTW_ERR(x, ...) do {} while (0) +#define RTW_WARN(x,...) do {} while (0) +#define RTW_INFO(x,...) do {} while (0) +#define RTW_DBG(x,...) do {} while (0) +#define RTW_PRINT_SEL(x,...) do {} while (0) +#define _RTW_PRINT(x, ...) do {} while (0) +#define _RTW_ERR(x, ...) do {} while (0) +#define _RTW_WARN(x,...) do {} while (0) +#define _RTW_INFO(x,...) do {} while (0) +#define _RTW_DBG(x,...) do {} while (0) +#define _RTW_PRINT_SEL(x,...) do {} while (0) #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) @@ -73,21 +54,13 @@ extern void rtl871x_cedbg(const char *fmt, ...); #undef _dbgdump #undef _seqdump -#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP) - #define _dbgdump DbgPrint - #define KERN_CONT - #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) -#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE) - #define _dbgdump rtl871x_cedbg - #define KERN_CONT - #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) -#elif defined PLATFORM_LINUX +#if defined(PLATFORM_LINUX) #define _dbgdump printk #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) #define KERN_CONT #endif #define _seqdump seq_printf -#elif defined PLATFORM_FREEBSD +#elif defined(PLATFORM_FREEBSD) #define _dbgdump printf #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) #define KERN_CONT @@ -96,13 +69,15 @@ extern void rtl871x_cedbg(const char *fmt, ...); #endif void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, - bool _idx_show, const u8 *_hexdata, int _hexdatalen); + bool _idx_show, const u8 *_hexdata, int _hexdatalen); +void RTW_BUF_DUMP_SEL_ALWAYS(void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen); #ifdef CONFIG_RTW_DEBUG -#ifndef _OS_INTFS_C_ +/*#ifndef _OS_INTFS_C_*/ extern uint rtw_drv_log_level; -#endif +/*#endif*/ #if defined(_dbgdump) @@ -273,6 +248,10 @@ extern uint rtw_drv_log_level; #define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \ RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen) + +#define RTW_MAP_DUMP_SEL_ALWAYS(sel, _TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL_ALWAYS(sel, _TitleString, _TRUE, _HexData, _HexDataLen) + #endif /* defined(_seqdump) */ @@ -284,36 +263,24 @@ extern uint rtw_drv_log_level; void dump_drv_version(void *sel); void dump_log_level(void *sel); - -#ifdef CONFIG_SDIO_HCI -void sd_f0_reg_dump(void *sel, _adapter *adapter); -void sdio_local_reg_dump(void *sel, _adapter *adapter); -#endif /* CONFIG_SDIO_HCI */ - -void mac_reg_dump(void *sel, _adapter *adapter); -void bb_reg_dump(void *sel, _adapter *adapter); -void bb_reg_dump_ex(void *sel, _adapter *adapter); -void rf_reg_dump(void *sel, _adapter *adapter); +void dump_drv_cfg(void *sel); void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos); +#ifdef CONFIG_RECV_REORDERING_CTRL struct sta_info; void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); - +#endif struct dvobj_priv; void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj); void dump_adapters_status(void *sel, struct dvobj_priv *dvobj); struct sec_cam_ent; -#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG) void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id); void dump_sec_cam_ent_title(void *sel, u8 has_id); -#endif void dump_sec_cam(void *sel, _adapter *adapter); void dump_sec_cam_cache(void *sel, _adapter *adapter); -bool rtw_fwdl_test_trigger_chksum_fail(void); -bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); u32 rtw_get_wait_hiq_empty_ms(void); void rtw_sta_linking_test_set_start(void); @@ -328,7 +295,15 @@ u16 rtw_ap_linking_test_force_asoc_fail(void); ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_read_reg(struct seq_file *m, void *v); ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -void dump_drv_cfg(void *sel); + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST +int proc_get_ignore_go_and_low_rssi_in_scan(struct seq_file *m, void *v); +ssize_t proc_set_ignore_go_and_low_rssi_in_scan(struct file *file, + const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + +ssize_t proc_set_mac_dbg_status_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + int proc_get_fwstate(struct seq_file *m, void *v); int proc_get_sec_info(struct seq_file *m, void *v); int proc_get_mlmext_state(struct seq_file *m, void *v); @@ -345,10 +320,8 @@ int proc_get_rf_info(struct seq_file *m, void *v); int proc_get_scan_param(struct seq_file *m, void *v); ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_scan_abort(struct seq_file *m, void *v); -#ifdef CONFIG_RTW_REPEATER_SON -int proc_get_rson_data(struct seq_file *m, void *v); -ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif +ssize_t proc_set_scan_abort(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + int proc_get_survey_info(struct seq_file *m, void *v); ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_ap_info(struct seq_file *m, void *v); @@ -377,7 +350,6 @@ ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_ int proc_get_ps_dbg_info(struct seq_file *m, void *v); ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -440,10 +412,6 @@ ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t c int proc_get_txbf_cap(struct seq_file *m, void *v); ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif -#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT -int proc_get_tx_aval_th(struct seq_file *m, void *v); -ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/ int proc_get_rx_ampdu_factor(struct seq_file *m, void *v); ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -468,7 +436,8 @@ ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, siz #ifdef CONFIG_80211AC_VHT int proc_get_vht_24g_enable(struct seq_file *m, void *v); -ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data); #endif ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -483,23 +452,19 @@ int proc_get_rssi_disp(struct seq_file *m, void *v); ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif -#ifdef CONFIG_BT_COEXIST -int proc_get_btcoex_dbg(struct seq_file *m, void *v); -ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_btcoex_info(struct seq_file *m, void *v); -#ifdef CONFIG_RF4CE_COEXIST -int proc_get_rf4ce_state(struct seq_file *m, void *v); -ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif -#endif /* CONFIG_BT_COEXIST */ +#ifdef CONFIG_BTC +int proc_get_btc_dbg(struct seq_file *m, void *v); +ssize_t proc_set_btc_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_btc_info(struct seq_file *m, void *v); +#endif /* CONFIG_BTC */ #if defined(DBG_CONFIG_ERROR_DETECT) int proc_get_sreset(struct seq_file *m, void *v); ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* DBG_CONFIG_ERROR_DETECT */ -int proc_get_odm_adaptivity(struct seq_file *m, void *v); -ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_phy_adaptivity(struct seq_file *m, void *v); +ssize_t proc_set_phy_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_DBG_COUNTER int proc_get_rx_logs(struct seq_file *m, void *v); @@ -535,29 +500,8 @@ int proc_get_wakeup_event(struct seq_file *m, void *v); ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_wakeup_reason(struct seq_file *m, void *v); -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN -int proc_dump_wow_keep_alive_info(struct seq_file *m, void *v); -#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ #endif -#ifdef CONFIG_WAR_OFFLOAD -int proc_get_war_offload_enable(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_ipv4_addr(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_ipv4_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_ipv6_addr(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_ipv6_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_mdns_domain_name(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_mdns_domain_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_mdns_machine_name(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_mdns_machine_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_mdns_txt_rsp(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_mdns_txt_rsp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_war_offload_mdns_service_info(struct seq_file *m, void *v); -ssize_t proc_set_war_offload_mdns_service_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif /* CONFIG_WAR_OFFLOAD */ - - #ifdef CONFIG_GPIO_WAKEUP int proc_get_wowlan_gpio_info(struct seq_file *m, void *v); ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, @@ -589,11 +533,6 @@ int proc_get_tdls_info(struct seq_file *m, void *v); int proc_get_monitor(struct seq_file *m, void *v); ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef RTW_SIMPLE_CONFIG -int proc_get_simple_config(struct seq_file *m, void *v); -ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif - #ifdef DBG_XMIT_BLOCK int proc_get_xmit_block(struct seq_file *m, void *v); ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -617,38 +556,12 @@ int proc_get_tx_auth(struct seq_file *m, void *v); int proc_get_efuse_map(struct seq_file *m, void *v); ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA -int proc_get_pathb_phase(struct seq_file *m, void *v); -ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif - -#ifdef CONFIG_MCC_MODE -int proc_get_mcc_info(struct seq_file *m, void *v); -ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef CONFIG_MCC_PHYDM_OFFLOAD -ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif -ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_mcc_policy_table(struct seq_file *m, void *v); -#endif /* CONFIG_MCC_MODE */ - int proc_get_ack_timeout(struct seq_file *m, void *v); ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_fw_offload(struct seq_file *m, void *v); ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef CONFIG_FW_HANDLE_TXBCN -ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v); -#endif #ifdef CONFIG_DBG_RF_CAL int proc_get_iqk_info(struct seq_file *m, void *v); @@ -679,6 +592,21 @@ int proc_get_smps(struct seq_file *m, void *v); int proc_get_defs_param(struct seq_file *m, void *v); ssize_t proc_set_defs_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef RTW_DETECT_HANG +int proc_get_hang_info(struct seq_file *m, void *v); +#endif + +int proc_get_chan(struct seq_file *m, void *v); +ssize_t proc_set_chan(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data); + +int proc_get_mr_test(struct seq_file *m, void *v); +ssize_t proc_set_mr_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_deny_legacy(struct seq_file *m, void *v); +ssize_t proc_set_deny_legacy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_ul_mu_disable(struct seq_file *m, void *v); +ssize_t proc_set_tx_ul_mu_disable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + #define _drv_always_ 1 #define _drv_emerg_ 2 #define _drv_alert_ 3 diff --git a/include/rtw_efuse.h b/include/rtw_efuse.h index 9a07d27..c1842b3 100644 --- a/include/rtw_efuse.h +++ b/include/rtw_efuse.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2020 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,274 +12,124 @@ * more details. * *****************************************************************************/ +#if defined(CONFIG_MP_INCLUDED) #ifndef __RTW_EFUSE_H__ #define __RTW_EFUSE_H__ +#include +#include +#define RTW_MAX_EFUSE_MAP_LEN 2048 -#define EFUSE_ERROE_HANDLE 1 - -#define PG_STATE_HEADER 0x01 -#define PG_STATE_WORD_0 0x02 -#define PG_STATE_WORD_1 0x04 -#define PG_STATE_WORD_2 0x08 -#define PG_STATE_WORD_3 0x10 -#define PG_STATE_DATA 0x20 - -#define PG_SWBYTE_H 0x01 -#define PG_SWBYTE_L 0x02 - -#define PGPKT_DATA_SIZE 8 - -#define EFUSE_WIFI 0 -#define EFUSE_BT 1 - -enum _EFUSE_DEF_TYPE { - TYPE_EFUSE_MAX_SECTION = 0, - TYPE_EFUSE_REAL_CONTENT_LEN = 1, - TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, - TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, - TYPE_EFUSE_MAP_LEN = 4, - TYPE_EFUSE_PROTECT_BYTES_BANK = 5, - TYPE_EFUSE_CONTENT_LEN_BANK = 6, +enum rtw_efuse_type { + RTW_EFUSE_WIFI = 0, + RTW_EFUSE_BT, + RTW_EFUSE_NONE, }; -#define EFUSE_MAX_MAP_LEN 1024 - -#define EFUSE_MAX_HW_SIZE 1024 -#define EFUSE_MAX_SECTION_BASE 16 -#define EFUSE_MAX_SECTION_NUM 128 -#define EFUSE_MAX_BANK_SIZE 512 - -/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/ -#ifdef RTW_HALMAC -#define BANK_NUM 1 -#if defined(CONFIG_RTL8723F) -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 -#else -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128 -#endif - -#define EFUSE_BT_REAL_CONTENT_LEN (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) - -#if defined(CONFIG_RTL8822C) -#define EFUSE_PROTECT_BYTES_BANK 54 -#elif defined(CONFIG_RTL8723F) -#define EFUSE_PROTECT_BYTES_BANK 40 -#else -#define EFUSE_PROTECT_BYTES_BANK 16 -#endif -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK) -#endif /* #ifdef RTW_HALMAC */ - -#define EXT_HEADER(header) ((header & 0x1F) == 0x0F) -#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) -#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5) - -#define EFUSE_REPEAT_THRESHOLD_ 3 - -#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset)) -#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset)) -#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt()) -#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt()) -#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset)) -#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset)) - - -#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset)) -#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt)) -#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0) - -#ifdef CONFIG_BT_EFUSE_MASK -#define IS_BT_MASKED_MP(ic, txt, offset) (EFUSE_IsBTAddressMasked_MP_##ic##txt(offset)) -#define GET_BT_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetBTArrayLen_MP_##ic##txt()) -#define GET_BT_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetBTArrayLen_TC_##ic##txt()) -#define GET_BT_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetBTMaskArray_MP_##ic##txt(offset)) - -#define IS_BT_MASKED(ic, txt, offset) (IS_BT_MASKED_MP(ic,txt, offset)) -#define GET_BT_MASK_ARRAY(ic, txt, out) do { GET_BT_MASK_ARRAY_MP(ic,txt, out); } while(0) -#define GET_BT_MASK_ARRAY_LEN(ic, txt) (GET_BT_MASK_ARRAY_LEN_MP(ic,txt)) -#endif +/* PHL efuse command */ +enum rtw_efuse_phl_cmdid { + RTW_EFUSE_CMD_WIFI_READ = 0, + RTW_EFUSE_CMD_WIFI_WRITE = 1, + RTW_EFUSE_CMD_WIFI_UPDATE = 2, + RTW_EFUSE_CMD_WIFI_UPDATE_MAP = 3, + RTW_EFUSE_CMD_WIFI_GET_OFFSET_MASK = 4, + RTW_EFUSE_CMD_WIFI_GET_USAGE = 5, + RTW_EFUSE_CMD_BT_READ = 6, + RTW_EFUSE_CMD_BT_WRITE = 7, + RTW_EFUSE_CMD_BT_UPDATE = 8, + RTW_EFUSE_CMD_BT_UPDATE_MAP = 9, + RTW_EFUSE_CMD_BT_GET_OFFSET_MASK = 10, + RTW_EFUSE_CMD_BT_GET_USAGE = 11, + RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE = 12, + RTW_EFUSE_CMD_WIFI_GET_SIZE = 13, + RTW_EFUSE_CMD_WIFI_GET_AVL_SIZE = 14, + RTW_EFUSE_CMD_AUTOLOAD_STATUS = 15, + RTW_EFUSE_CMD_SHADOW_MAP2BUF = 16, + RTW_EFUSE_CMD_FILE_MAP_LOAD = 17, + RTW_EFUSE_CMD_FILE_MASK_LOAD = 18, + RTW_MP_EFUSE_CMD_GET_INFO = 19, + /* BT */ + RTW_EFUSE_CMD_BT_GET_LOG_SIZE = 20, + RTW_EFUSE_CMD_BT_GET_SIZE = 21, + RTW_EFUSE_CMD_BT_GET_AVL_SIZE = 22, + RTW_EFUSE_CMD_BT_SHADOW_MAP2BUF = 23, + RTW_EFUSE_CMD_BT_FILE_MAP_LOAD = 24, + RTW_EFUSE_CMD_BT_FILE_MASK_LOAD = 25, + RTW_EFUSE_CMD_BT_READ_HIDDEN = 26, + RTW_EFUSE_CMD_BT_WRITE_HIDDEN = 27, + RTW_MP_EFUSE_CMD_WIFI_GET_MAP_FROM =28, + RTW_EFUSE_CMD_WIFI_GET_PHY_MAP = 29, + RTW_EFUSE_CMD_BT_GET_PHY_MAP = 30, + RTW_MP_EFUSE_CMD_WIFI_SET_RENEW = 31, + RTW_EFUSE_CMD_MAX, +}; -/* ********************************************* - * The following is for BT Efuse definition - * ********************************************* */ -#define EFUSE_BT_MAX_MAP_LEN 1024 -#define EFUSE_MAX_BANK 4 -#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) -/* ********************************************* - *--------------------------Define Parameters-------------------------------*/ -#define EFUSE_MAX_WORD_UNIT 4 +struct rtw_efuse_phl_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u8 io_type; + u16 io_offset; + u32 io_value; + u8 autoload; + u8 pfile_path[200]; + u16 buf_len; + u8 poutbuf[1536]; +}; -/*------------------------------Define structure----------------------------*/ -typedef struct PG_PKT_STRUCT_A { - u8 offset; - u8 word_en; - u8 data[8]; - u8 word_cnts; -} PGPKT_STRUCT, *PPGPKT_STRUCT; +enum RTW_EFUSE_MAP_STATUS { + RTW_DEFAULT_MAP = 0, + RTW_HW_LOG_MAP = 1, + RTW_FILE_MAP = 2, + RTW_EFUSE_UNKNOWN, +}; -typedef enum { - ERR_SUCCESS = 0, - ERR_DRIVER_FAILURE, - ERR_IO_FAILURE, - ERR_WI_TIMEOUT, - ERR_WI_BUSY, - ERR_BAD_FORMAT, - ERR_INVALID_DATA, - ERR_NOT_ENOUGH_SPACE, - ERR_WRITE_PROTECT, - ERR_READ_BACK_FAIL, - ERR_OUT_OF_RANGE -} ERROR_CODE; +#define RTW_EFUSE_FROM2STR(status)\ +(status == RTW_DEFAULT_MAP) ? "DEFAULT" :\ +(status == RTW_HW_LOG_MAP) ? "HW_LOG_EFUSE" :\ +(status == RTW_FILE_MAP) ? "FILE_EFUSE" :\ +"UNknow" -/*------------------------------Define structure----------------------------*/ -typedef struct _EFUSE_HAL { - u8 fakeEfuseBank; - u32 fakeEfuseUsedBytes; - u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; - u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; - u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; - u32 EfuseUsedBytes; - u8 EfuseUsedPercentage; +s8 rtw_efuse_get_map_from(_adapter *padapter); - u16 BTEfuseUsedBytes; - u8 BTEfuseUsedPercentage; - u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; - u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; - u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; +u32 rtw_efuse_get_map_size(_adapter *padapter , u16 *size , enum rtw_efuse_phl_cmdid cmdid); - u16 fakeBTEfuseUsedBytes; - u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; - u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; - u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; +u32 rtw_efuse_get_available_size(_adapter *padapter , u16 *size, u8 efuse_type); - /* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */ - const u16 MaxSecNum_WiFi; - const u16 MaxSecNum_BT; - const u16 WordUnit; - const u16 PhysicalLen_WiFi; - const u16 PhysicalLen_BT; - const u16 LogicalLen_WiFi; - const u16 LogicalLen_BT; - const u16 BankSize; - const u16 TotalBankNum; - const u16 BankNum_WiFi; - const u16 BankNum_BT; - const u16 OOBProtectBytes; - const u16 ProtectBytes; - const u16 BankAvailBytes; - const u16 TotalAvailBytes_WiFi; - const u16 TotalAvailBytes_BT; - const u16 HeaderRetry; - const u16 DataRetry; +u8 rtw_efuse_map_read(_adapter * adapter, u16 addr, u16 cnts, u8 *data, u8 efuse_type); - ERROR_CODE Status; +u8 rtw_efuse_map_write(_adapter * adapter, u16 addr, u16 cnts, u8 *data, u8 efuse_type, u8 bpg); -} EFUSE_HAL, *PEFUSE_HAL; +int rtw_ioctl_efuse_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); -extern u8 maskfileBuffer[64]; -extern u8 btmaskfileBuffer[64]; +int rtw_ioctl_efuse_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra); -/*------------------------Export global variable----------------------------*/ -extern u8 fakeEfuseBank; -extern u32 fakeEfuseUsedBytes; -extern u8 fakeEfuseContent[]; -extern u8 fakeEfuseInitMap[]; -extern u8 fakeEfuseModifiedMap[]; +int rtw_ioctl_efuse_file_map_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); -extern u32 BTEfuseUsedBytes; -extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; -extern u8 BTEfuseInitMap[]; -extern u8 BTEfuseModifiedMap[]; +int rtw_ioctl_efuse_file_mask_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); -extern u32 fakeBTEfuseUsedBytes; -extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; -extern u8 fakeBTEfuseInitMap[]; -extern u8 fakeBTEfuseModifiedMap[]; -/*------------------------Export global variable----------------------------*/ -#define MAX_SEGMENT_SIZE 200 -#define MAX_SEGMENT_NUM 200 -#define MAX_BUF_SIZE (MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM) -#define TMP_BUF_SIZE 100 -#define rtprintf dcmd_Store_Return_Buf +int rtw_ioctl_efuse_bt_file_map_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); -u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size); -u16 efuse_bt_GetMaxSize(PADAPTER padapter); -u16 efuse_GetavailableSize(PADAPTER adapter); +int rtw_ioctl_efuse_bt_file_mask_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); -u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); -u16 efuse_GetMaxSize(PADAPTER padapter); -u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); -u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_raw_map_read(_adapter * adapter, u16 addr, + u16 cnts, u8 *data, u8 efuse_type); -u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); -u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); -u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); -u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); -u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); -#ifdef CONFIG_RTL8822C -void rtw_pre_bt_efuse(PADAPTER padapter); +u8 rtw_efuse_bt_write_raw_hidden(_adapter * adapter, u16 addr, + u16 cnts, u8 *data); #endif -u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); -u8 Efuse_CalculateWordCnts(u8 word_en); -void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; -void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); -u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); -#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test)) - -u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); - -void BTEfuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); -void Efuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); -int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); -int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); -void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); -u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); -void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); -void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); -#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value)) -BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf); -BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset); - -void hal_ReadEFuse_BT_logic_map( - PADAPTER padapter, - u16 _offset, - u16 _size_byte, - u8 *pbuf -); -u8 EfusePgPacketWrite_BT( - PADAPTER pAdapter, - u8 offset, - u8 word_en, - u8 *pData, - u8 bPseudoTest); - -u16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter); -void rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray); -u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter); -void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray); -void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake); - -#define MAC_HIDDEN_MAX_BW_NUM 8 -extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[]; -#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)]) - -#define MAC_HIDDEN_PROTOCOL_NUM 4 -extern const u8 _mac_hidden_proto_to_hal_proto_cap[]; -#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)]) - -u8 mac_hidden_wl_func_to_hal_wl_func(u8 func); - -#ifdef PLATFORM_LINUX -u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len); -u8 rtw_efuse_file_store(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len); -#ifdef CONFIG_EFUSE_CONFIG_FILE -u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size); -u32 rtw_read_macaddr_from_file(const char *path, u8 *buf); -#endif /* CONFIG_EFUSE_CONFIG_FILE */ -#endif /* PLATFORM_LINUX */ - -#endif +#endif /*#if defined(CONFIG_MP_INCLUDED)*/ diff --git a/include/rtw_event.h b/include/rtw_event.h index 13e3f52..4991cd5 100644 --- a/include/rtw_event.h +++ b/include/rtw_event.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,10 +15,6 @@ #ifndef _RTW_EVENT_H_ #define _RTW_EVENT_H_ -#ifdef CONFIG_H2CLBK - #include -#endif - /* Used to report a bss has been scanned @@ -75,21 +71,5 @@ struct wmm_event { unsigned char wmm; }; -#ifdef CONFIG_H2CLBK -struct c2hlbk_event { - unsigned char mac[6]; - unsigned short s0; - unsigned short s1; - unsigned int w0; - unsigned char b0; - unsigned short s2; - unsigned char b1; - unsigned int w1; -}; -#endif/* CONFIG_H2CLBK */ -struct rtw_event { - u32 parmsize; - void (*event_callback)(_adapter *dev, u8 *pbuf); -}; #endif /* _WLANEVENT_H_ */ diff --git a/include/rtw_ft.h b/include/rtw_ft.h index 025f19e..7599af3 100644 --- a/include/rtw_ft.h +++ b/include/rtw_ft.h @@ -57,11 +57,11 @@ enum _rtw_ft_sta_status { ((a)->mlmepriv.ft_roam.ft_status = (s)); \ } while (0) -#define rtw_ft_lock_set_status(a, s, irq) \ +#define rtw_ft_lock_set_status(a, s) \ do { \ - _enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ + _rtw_spinlock_bh(&(a)->mlmepriv.lock); \ ((a)->mlmepriv.ft_roam.ft_status = (s)); \ - _exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ + _rtw_spinunlock_bh(&(a)->mlmepriv.lock); \ } while (0) #define rtw_ft_reset_status(a) \ @@ -93,7 +93,7 @@ enum rtw_ft_capability { #define rtw_ft_roam(a) \ ((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN)) - + #define rtw_ft_valid_akm(a, t) \ ((rtw_ft_chk_flags(a, RTW_FT_EN)) && \ (((t) == 3) || ((t) == 4))) @@ -102,11 +102,18 @@ enum rtw_ft_capability { ((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \ && (r == WLAN_REASON_ACTIVE_ROAM)) +/* allow OTD while driver disconnect with current AP */ +#if 1 +#define rtw_ft_otd_roam_en(a) \ + ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ + && ((a)->mlmepriv.ft_roam.ft_cap & 0x01)) +#else #define rtw_ft_otd_roam_en(a) \ ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ && ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE) \ && ((a)->mlmepriv.ft_roam.ft_cap & 0x01)) - +#endif + #define rtw_ft_otd_roam(a) \ rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) @@ -119,7 +126,7 @@ enum rtw_ft_capability { struct ft_roam_info { u16 mdid; - u8 ft_cap; + u8 ft_cap; /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ u8 updated_ft_ies[RTW_FT_MAX_IE_SZ]; u16 updated_ft_ies_len; @@ -130,7 +137,16 @@ struct ft_roam_info { u8 ft_flags; u32 ft_status; u32 ft_req_retry_cnt; - bool ft_updated_bcn; + bool ft_updated_bcn; +}; + +struct rtw_sta_ft_info_t { + u8 *rsn_ie; + u32 rsn_len; + u8 *md_ie; + u32 md_len; + u8 *ft_ie; + u32 ft_len; }; void rtw_ft_info_init(struct ft_roam_info *pft); @@ -155,13 +171,13 @@ void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame); void rtw_ft_start_clnt_join(_adapter *padapter); u8 rtw_ft_update_rsnie( - _adapter *padapter, u8 bwrite, + _adapter *padapter, u8 bwrite, struct pkt_attrib *pattrib, u8 **pframe); -void rtw_ft_build_auth_req_ies(_adapter *padapter, +void rtw_ft_build_auth_req_ies(_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe); -void rtw_ft_build_assoc_req_ies(_adapter *padapter, +void rtw_ft_build_assoc_req_ies(_adapter *padapter, u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe); u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len); @@ -180,4 +196,19 @@ void rtw_ft_roam_timer_hdl(void *ctx); void rtw_ft_roam_status_reset(_adapter *padapter); +void rtw_ft_peer_info_init(struct sta_info *psta); + +void rtw_ft_peer_info_free(struct sta_info *psta); + +int rtw_ft_update_sta_ies(_adapter *padapter, + struct cfg80211_update_ft_ies_params *pie); + +void rtw_ft_update_assocresp_ies(struct net_device *net, + struct cfg80211_ap_settings *settings); + +void rtw_ft_process_ft_auth_rsp(_adapter *padapter, u8 *pframe, u32 len); + +void rtw_ft_build_assoc_rsp_ies(_adapter *padapter, + struct sta_info *psta, struct pkt_attrib *pattrib, u8 **pframe); + #endif /* __RTW_FT_H_ */ diff --git a/include/rtw_he.h b/include/rtw_he.h new file mode 100644 index 0000000..6b62ec0 --- /dev/null +++ b/include/rtw_he.h @@ -0,0 +1,975 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_HE_H_ +#define _RTW_HE_H_ + +/* Set HE MAC Capabilities Information */ +#define SET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 1, _val) +#define SET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 1, _val) +#define SET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 1, _val) +#define SET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 2, _val) +#define SET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 3, _val) + +#define SET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) +#define SET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) +#define SET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 3, _val) +#define SET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) + +#define SET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) +#define SET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) +#define SET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) +#define SET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) +#define SET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) +#define SET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) +#define SET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) + +#define SET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 1, 1, _val) +#define SET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) +#define SET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) +#define SET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) +#define SET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) +#define SET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) + +#define SET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) +#define SET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) +#define SET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 1, _val) +#define SET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 3, 1, _val) +#define SET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 4, 1, _val) +#define SET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 1, _val) +#define SET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 6, 1, _val) +#define SET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_2BYTE((_pEleStart) + 4, 7, 3, _val) + +#define SET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 2, 1, _val) +#define SET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 1, _val) +#define SET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 4, 1, _val) +#define SET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 5, 1, _val) +#define SET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) +#define SET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) + +/* Set HE PHY Capabilities Information */ +#define SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 7, _val) + +#define SET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 4, _val) +#define SET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 1, _val) +#define SET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 5, 1, _val) +#define SET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) +#define SET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart, _val) \ + SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) + +#define SET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) +#define SET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) +#define SET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) +#define SET_HE_PHY_CAP_DOPPLER_TX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) +#define SET_HE_PHY_CAP_DOPPLER_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) +#define SET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) +#define SET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) + +#define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 0, 2, _val) +#define SET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) +#define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) +#define SET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) +#define SET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) +#define SET_HE_PHY_CAP_SU_BFER(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) + +#define SET_HE_PHY_CAP_SU_BFEE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) +#define SET_HE_PHY_CAP_MU_BFER(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) +#define SET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 3, _val) +#define SET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 3, _val) + +#define SET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 0, 3, _val) +#define SET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 3, _val) +#define SET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) +#define SET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) + +#define SET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 0, 1, _val) +#define SET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 1, 1, _val) +#define SET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 2, 1, _val) +#define SET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 3, 1, _val) +#define SET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 4, 1, _val) +#define SET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 5, 1, _val) +#define SET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 6, 1, _val) +#define SET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 7, 1, _val) + +#define SET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 0, 1, _val) +#define SET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 1, 1, _val) +#define SET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 2, 1, _val) +#define SET_HE_PHY_CAP_MAX_NC(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 3, 3, _val) +#define SET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 6, 1, _val) +#define SET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 7, 1, _val) + +#define SET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 0, 1, _val) +#define SET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 1, 1, _val) +#define SET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 2, 1, _val) +#define SET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 3, 1, _val) +#define SET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 4, 1, _val) +#define SET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 5, 1, _val) +#define SET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 6, 2, _val) + +#define SET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 0, 1, _val) +#define SET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 1, 1, _val) +#define SET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 2, 1, _val) +#define SET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 3, 1, _val) +#define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 4, 1, _val) +#define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 5, 1, _val) +#define SET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 6, 2, _val) + +/* Set Supported HE-MCS And NSS Set Information */ +#define SET_HE_CAP_MCS_1SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_HE_CAP_MCS_2SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) +#define SET_HE_CAP_MCS_3SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) +#define SET_HE_CAP_MCS_4SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) +#define SET_HE_CAP_MCS_5SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) +#define SET_HE_CAP_MCS_6SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) +#define SET_HE_CAP_MCS_7SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) +#define SET_HE_CAP_MCS_8SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) + +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart, _val) +#define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart, _val) + +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart + 2, _val) +#define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart + 2, _val) + +#define SET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart + 4, _val) +#define SET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart + 4, _val) + +#define SET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart + 6, _val) +#define SET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart + 6, _val) + +#define SET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart + 8, _val) +#define SET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart + 8, _val) + +#define SET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_1SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_2SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_3SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_4SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_5SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_6SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_7SS(_pEleStart + 10, _val) +#define SET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ + SET_HE_CAP_MCS_8SS(_pEleStart + 10, _val) + +/* Set PPE Threshold */ +#define SET_HE_CAP_PPE_NSTS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) +#define SET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 4, _val) + +/* Get HE MAC Capabilities Information */ +#define GET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 1) +#define GET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 1, 1) +#define GET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 2, 1) +#define GET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 3, 2) +#define GET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 5, 3) + +#define GET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) +#define GET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) +#define GET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 3) +#define GET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart) \ + LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) + +#define GET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) +#define GET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) +#define GET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) +#define GET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) +#define GET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) +#define GET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) +#define GET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) + +#define GET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 1, 1) +#define GET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) +#define GET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) +#define GET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) +#define GET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) +#define GET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) + +#define GET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) +#define GET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) +#define GET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 1) +#define GET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 3, 1) +#define GET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 4, 1) +#define GET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 1) +#define GET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 6, 1) +#define GET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart) \ + LE_BITS_TO_2BYTE((_pEleStart) + 4, 7, 3) + +#define GET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 2, 1) +#define GET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 1) +#define GET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 4, 1) +#define GET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 5, 1) +#define GET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) +#define GET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) + +/* Get HE PHY Capabilities Information */ +#define GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 1, 7) + +#define GET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) +#define GET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 1) +#define GET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 1) +#define GET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) +#define GET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart) \ + LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) + +#define GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) +#define GET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) +#define GET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) +#define GET_HE_PHY_CAP_DOPPLER_TX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) +#define GET_HE_PHY_CAP_DOPPLER_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) +#define GET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) +#define GET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) + +#define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 2) +#define GET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) +#define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) +#define GET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) +#define GET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) +#define GET_HE_PHY_CAP_SU_BFER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) + +#define GET_HE_PHY_CAP_SU_BFEE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) +#define GET_HE_PHY_CAP_MU_BFER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) +#define GET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 3) +#define GET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 3) + +#define GET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 3) +#define GET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 3) +#define GET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) +#define GET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) + +#define GET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 1) +#define GET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 1, 1) +#define GET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 2, 1) +#define GET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 3, 1) +#define GET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 4, 1) +#define GET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 5, 1) +#define GET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 6, 1) +#define GET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 7, 1) + +#define GET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 1) +#define GET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 1, 1) +#define GET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 2, 1) +#define GET_HE_PHY_CAP_MAX_NC(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 3, 3) +#define GET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 6, 1) +#define GET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 7, 1) + +#define GET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 1) +#define GET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 1, 1) +#define GET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 2, 1) +#define GET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 3, 1) +#define GET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 4, 1) +#define GET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 5, 1) +#define GET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 6, 2) + +#define GET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 1) +#define GET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 1, 1) +#define GET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 2, 1) +#define GET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 3, 1) +#define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 4, 1) +#define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 5, 1) +#define GET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 6, 2) + +/* Get Supported HE-MCS And NSS Set Information */ +#define GET_HE_CAP_MCS_1SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_HE_CAP_MCS_2SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 2, 2) +#define GET_HE_CAP_MCS_3SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 4, 2) +#define GET_HE_CAP_MCS_4SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 6, 2) +#define GET_HE_CAP_MCS_5SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) +#define GET_HE_CAP_MCS_6SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) +#define GET_HE_CAP_MCS_7SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) +#define GET_HE_CAP_MCS_8SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) + +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart) +#define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart) + +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart + 2) +#define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart + 2) + +#define GET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart + 4) +#define GET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart + 4) + +#define GET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart + 6) +#define GET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart + 6) + +#define GET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart + 8) +#define GET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart + 8) + +#define GET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart) \ + GET_HE_CAP_MCS_1SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart) \ + GET_HE_CAP_MCS_2SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart) \ + GET_HE_CAP_MCS_3SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart) \ + GET_HE_CAP_MCS_4SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart) \ + GET_HE_CAP_MCS_5SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart) \ + GET_HE_CAP_MCS_6SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart) \ + GET_HE_CAP_MCS_7SS(_pEleStart + 10) +#define GET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart) \ + GET_HE_CAP_MCS_8SS(_pEleStart + 10) + +/* Get PPE Threshold */ +#define GET_HE_CAP_PPE_NSTS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 3) +#define GET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 3, 4) + +/* Set HE Operation element */ +#define SET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) +#define SET_HE_OP_PARA_TWT_REQUIRED(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 1, _val) +#define SET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart, _val) \ + SET_BITS_TO_LE_2BYTE(_pEleStart, 4, 10, _val) + +#define SET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) +#define SET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 7, 1, _val) + +#define SET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 0, 1, _val) +#define SET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) + +#define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 6, _val) +#define SET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val) +#define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) + +#define SET_HE_OP_BASIC_MCS_1SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_HE_OP_BASIC_MCS_2SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) +#define SET_HE_OP_BASIC_MCS_3SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) +#define SET_HE_OP_BASIC_MCS_4SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) +#define SET_HE_OP_BASIC_MCS_5SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) +#define SET_HE_OP_BASIC_MCS_6SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) +#define SET_HE_OP_BASIC_MCS_7SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) +#define SET_HE_OP_BASIC_MCS_8SS(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) + +/* Values in HE spec */ +#define TXOP_DUR_RTS_TH_DISABLED 1023 + +/* Get HE Operation element */ +#define GET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 3) +#define GET_HE_OP_PARA_TWT_REQUIRED(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 3, 1) +#define GET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart) \ + LE_BITS_TO_2BYTE(_pEleStart, 4, 10) + +#define GET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) +#define GET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 7, 1) + +#define GET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 1) +#define GET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) + +#define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 6) +#define GET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) +#define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) + +#define GET_HE_OP_BASIC_MCS_1SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_HE_OP_BASIC_MCS_2SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 2, 2) +#define GET_HE_OP_BASIC_MCS_3SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 4, 2) +#define GET_HE_OP_BASIC_MCS_4SS(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 6, 2) +#define GET_HE_OP_BASIC_MCS_5SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) +#define GET_HE_OP_BASIC_MCS_6SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) +#define GET_HE_OP_BASIC_MCS_7SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) +#define GET_HE_OP_BASIC_MCS_8SS(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) + +/* Get MU EDCA Parameter Set element */ +#define GET_HE_MU_EDCA_QOS_INFO(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 8) +#define GET_HE_MU_EDCA_QOS_INFO_UPDATE_CNT(_pEleStart) \ + LE_BITS_TO_1BYTE(_pEleStart, 0, 4) +#define GET_HE_MU_EDCA_BE_AIFSN(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) +#define GET_HE_MU_EDCA_BE_ACI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 2) +#define GET_HE_MU_EDCA_BE_ECW_MIN_MAX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 8) +#define GET_HE_MU_EDCA_BE_TIMER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 8) +#define GET_HE_MU_EDCA_BK_AIFSN(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 4) +#define GET_HE_MU_EDCA_BK_ACI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 2) +#define GET_HE_MU_EDCA_BK_ECW_MIN_MAX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 8) +#define GET_HE_MU_EDCA_BK_TIMER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 8) +#define GET_HE_MU_EDCA_VI_AIFSN(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 4) +#define GET_HE_MU_EDCA_VI_ACI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 7, 5, 2) +#define GET_HE_MU_EDCA_VI_ECW_MIN_MAX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 8) +#define GET_HE_MU_EDCA_VI_TIMER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 8) +#define GET_HE_MU_EDCA_VO_AIFSN(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 10, 0, 4) +#define GET_HE_MU_EDCA_VO_ACI(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 10, 5, 2) +#define GET_HE_MU_EDCA_VO_ECW_MIN_MAX(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 11, 0, 8) +#define GET_HE_MU_EDCA_VO_TIMER(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 12, 0, 8) + + +/* HE variant HT Control */ +#define HE_VAR_HTC 3 + +#define HE_VAR_HTC_CID_TRS 0 +#define HE_VAR_HTC_CID_OM 1 +#define HE_VAR_HTC_CID_HLA 2 +#define HE_VAR_HTC_CID_BSR 3 +#define HE_VAR_HTC_CID_UPH 4 +#define HE_VAR_HTC_CID_BQR 5 +#define HE_VAR_HTC_CID_CAS 6 + +/* Set HE variant HT Control field */ +#define SET_HE_VAR_HTC(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 0, 2, HE_VAR_HTC) + +#define SET_HE_VAR_HTC_CID_TRS(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_TRS) +#define SET_HE_VAR_HTC_CID_OM(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_OM) +#define SET_HE_VAR_HTC_CID_HLA(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_HLA) +#define SET_HE_VAR_HTC_CID_BSR(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BSR) +#define SET_HE_VAR_HTC_CID_UPH(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_UPH) +#define SET_HE_VAR_HTC_CID_BQR(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BQR) +#define SET_HE_VAR_HTC_CID_CAS(_pStart) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_CAS) + +#define SET_HE_VAR_HTC_OM_RX_NSS(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6, 3, _val) +#define SET_HE_VAR_HTC_OM_CH_WIDTH(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 3, 2, _val) +#define SET_HE_VAR_HTC_OM_UL_MU_DIS(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 5, 1, _val) +#define SET_HE_VAR_HTC_OM_TX_NSTS(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 6, 3, _val) +#define SET_HE_VAR_HTC_OM_ER_SU_DIS(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 9, 1, _val) +#define SET_HE_VAR_HTC_OM_DL_MU_MIMO_RR(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 10, 1, _val) +#define SET_HE_VAR_HTC_OM_UL_MU_DATA_DIS(_pStart, _val) \ + SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 11, 1, _val) + +/* Get HE variant HT Control field */ +#define GET_VAR_HTC(_pStart) \ + LE_BITS_TO_1BYTE(_pStart, 0, 2) +#define GET_HE_VAR_HTC_CID(_pStart) \ + LE_BITS_TO_1BYTE(_pStart, 2, 4) + +#define HE_MCS_SUPP_MSC0_TO_MSC7 0x0 /* 2b00 */ +#define HE_MCS_SUPP_MSC0_TO_MSC9 0x1 /* 2b01 */ +#define HE_MCS_SUPP_MSC0_TO_MSC11 0x2 /* 2b10 */ +#define HE_MSC_NOT_SUPP 0x3 /* 2b11 */ +#define HE_MSC_NOT_SUPP_BYTE ((HE_MSC_NOT_SUPP << 6) | (HE_MSC_NOT_SUPP << 4) \ + | (HE_MSC_NOT_SUPP << 2) | HE_MSC_NOT_SUPP) + +#define HE_DEV_CLASS_A 1 +#define HE_DEV_CLASS_B 0 + +/* + * HE_MAC_Cap (6) + * HE_PHY_Cap (11) + * HE_Support_MCS (4, 8 or 12) + * PPE_Thres (variable, max = 25) + */ +#define HE_CAP_ELE_MAC_CAP_LEN 6 +#define HE_CAP_ELE_PHY_CAP_LEN 11 + +#define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M 2 +#define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M 2 +#define HE_CAP_ELE_SUPP_MCS_LEN_RX_160M 2 +#define HE_CAP_ELE_SUPP_MCS_LEN_TX_160M 2 +#define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M 2 +#define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M 2 +#define HE_CAP_ELE_SUPP_MCS_MAX_LEN (HE_CAP_ELE_SUPP_MCS_LEN_RX_80M \ + + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M + HE_CAP_ELE_SUPP_MCS_LEN_RX_160M \ + + HE_CAP_ELE_SUPP_MCS_LEN_TX_160M + HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M \ + + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M) + +#define HE_CAP_ELE_PPE_THRE_MAX_LEN 25 + +#define HE_CAP_ELE_MAX_LEN (1 + HE_CAP_ELE_MAC_CAP_LEN + HE_CAP_ELE_PHY_CAP_LEN \ + + HE_CAP_ELE_SUPP_MCS_MAX_LEN + HE_CAP_ELE_PPE_THRE_MAX_LEN) +/* #define HE_CAP_MAC_CAP_OFFSET 0 +#define HE_CAP_PHY_CAP_OFFSET 6 +#define HE_CAP_SUPPORT_MCS_OFFSET 17 +*/ + +/* + * HE_Ope_Para (3) + * BSS_Color (1) + * Basic_MCS (2) + * VHT_Op (0 or 3) + * CoHosted_Bssid_Ind (0 or 1) + * 6Ghz_Ope_Info (0 or 5) + */ +#define HE_OPER_PARAMS_LEN 3 +#define HE_OPER_BSS_COLOR_INFO_LEN 1 +#define HE_OPER_BASIC_MCS_LEN 2 +#define HE_OPER_VHT_OPER_INFO_LEN 3 +#define HE_OPER_MAX_COHOST_BSSID_LEN 1 +#define HE_OPER_6G_OPER_INFO_LEN 5 + +#define HE_OPER_ELE_MAX_LEN (1 + HE_OPER_PARAMS_LEN + HE_OPER_BSS_COLOR_INFO_LEN \ + + HE_OPER_BASIC_MCS_LEN + HE_OPER_VHT_OPER_INFO_LEN \ + + HE_OPER_MAX_COHOST_BSSID_LEN + HE_OPER_6G_OPER_INFO_LEN) +/* #define HE_OPER_PARAS_OFFSET 0 +#define HE_OPER_BSS_COLOR_OFFSET 3 +#define HE_OPER_BASIC_MCS_OFFSET 4 +*/ + +#define MAX_HE_GI_TYPE 3 +#define MAX_HE_MCS_INDEX 12 * 2 /* 1SS + 2SS */ + +enum rtw_he_actrl_om_mask { + OM_RX_NSS = BIT0, + OM_CH_BW = BIT1, + OM_UL_MU_DIS = BIT2, + OM_TX_NSTS = BIT3, + OM_ER_SU_DIS = BIT4, + OM_DL_MU_RR = BIT5, + OM_UL_MU_DATA_DIS = BIT6 +}; + +struct rtw_he_actrl_om_ele { + u8 rx_nss; + u8 channel_width; + u8 ul_mu_disable; + u8 tx_nsts; + u8 er_su_disable; + u8 dl_mu_mimo_rr; + u8 ul_mu_data_disable; +}; + + +struct rtw_he_actrl_om { + /* om ctrl flag for normal tx pkt */ + u8 actrl_om_normal_tx; + u8 actrl_om_normal_tx_cnt; + /* current om ctrl element content */ + struct rtw_he_actrl_om_ele om_actrl_ele; +}; + +struct he_priv { + u8 he_option; + u8 he_cap[HE_CAP_ELE_MAX_LEN]; + u8 he_op[HE_OPER_ELE_MAX_LEN]; + u8 op_present; + u8 he_highest_rate; + u8 pre_he_muedca_cnt; + struct rtw_he_actrl_om om_info; +}; + +u16 rtw_he_mcs_to_data_rate(u8 bw, u8 gi, u8 he_mcs_rate); +void rtw_he_use_default_setting(_adapter *padapter); +void update_sta_he_info_apmode(_adapter *padapter, void *sta); +void update_hw_he_param(_adapter *padapter); +void HE_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HE_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HE_mu_edca_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE, u8 first); +u32 rtw_build_he_cap_ie(_adapter *padapter, u8 *pbuf); + +struct protocol_cap_t; +struct phy_cap_t; +u32 rtw_get_dft_he_cap_ie(_adapter *padapter, struct phy_cap_t *phy_cap, + struct protocol_cap_t *proto_cap, u8 *pbuf); + +u32 rtw_restructure_he_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan); +void HEOnAssocRsp(_adapter *padapter); +void rtw_he_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +void rtw_he_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +u8 rtw_he_htc_en(_adapter *padapter, struct sta_info *psta); +void rtw_he_fill_htc(_adapter *padapter, struct pkt_attrib *pattrib, u32 *phtc_buf); +void rtw_he_set_om_info(_adapter *padapter, u8 om_mask, struct rtw_he_actrl_om *om_info); +void rtw_he_init_om_info(_adapter *padapter); + +#endif /* _RTW_HE_H_ */ + diff --git a/include/rtw_ht.h b/include/rtw_ht.h index 8237bbe..5d538c7 100644 --- a/include/rtw_ht.h +++ b/include/rtw_ht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtw_hwsim_intf.h b/include/rtw_hwsim_intf.h new file mode 100644 index 0000000..608f548 --- /dev/null +++ b/include/rtw_hwsim_intf.h @@ -0,0 +1,31 @@ +/* + * Copyright(c) 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + */ + +#ifndef __RTW_HWSIM_INTF_H_ +#define __RTW_HWSIM_INTF_H_ + +#include + +#include + +int rtw_hwsim_medium_tx(struct _ADAPTER *adapter, const void *tx_ctx, + u8 *buf, size_t buflen); + +void rtw_hwsim_medium_pre_netif_rx(struct sk_buff *skb); + + +#endif /* __RTW_HWSIM_INTF_H__ */ diff --git a/include/rtw_io.h b/include/rtw_io.h index 50291e1..cf4cbb2 100644 --- a/include/rtw_io.h +++ b/include/rtw_io.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,252 +12,9 @@ * more details. * *****************************************************************************/ - #ifndef _RTW_IO_H_ #define _RTW_IO_H_ -#define NUM_IOREQ 8 - -#ifdef PLATFORM_LINUX - #define MAX_PROT_SZ (64-16) -#endif - -#define _IOREADY 0 -#define _IO_WAIT_COMPLETE 1 -#define _IO_WAIT_RSP 2 - -/* IO COMMAND TYPE */ -#define _IOSZ_MASK_ (0x7F) -#define _IO_WRITE_ BIT(7) -#define _IO_FIXED_ BIT(8) -#define _IO_BURST_ BIT(9) -#define _IO_BYTE_ BIT(10) -#define _IO_HW_ BIT(11) -#define _IO_WORD_ BIT(12) -#define _IO_SYNC_ BIT(13) -#define _IO_CMDMASK_ (0x1F80) - - -/* - For prompt mode accessing, caller shall free io_req - Otherwise, io_handler will free io_req -*/ - - - -/* IO STATUS TYPE */ -#define _IO_ERR_ BIT(2) -#define _IO_SUCCESS_ BIT(1) -#define _IO_DONE_ BIT(0) - - -#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) -#define IO_RD16 (_IO_SYNC_ | _IO_HW_) -#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) - -#define IO_RD32_ASYNC (_IO_WORD_) -#define IO_RD16_ASYNC (_IO_HW_) -#define IO_RD8_ASYNC (_IO_BYTE_) - -#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) -#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) -#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) - -#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) -#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) -#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) - -/* - - Only Sync. burst accessing is provided. - -*/ - -#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) -#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) - - - -/* below is for the intf_option bit defition... */ - -#define _INTF_ASYNC_ BIT(0) /* support async io */ - -struct intf_priv; -struct intf_hdl; -struct io_queue; - -struct _io_ops { - u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr); - u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr); - u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr); - - int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); - int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); - - int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); - - void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - - void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); - - u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); - - u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); - - u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem); - - void (*_read_port_cancel)(struct intf_hdl *pintfhdl); - void (*_write_port_cancel)(struct intf_hdl *pintfhdl); - -#ifdef CONFIG_SDIO_HCI - u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr); -#ifdef CONFIG_SDIO_INDIRECT_ACCESS - u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr); - u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr); - u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr); - int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ -#endif - -}; - -struct io_req { - _list list; - u32 addr; - volatile u32 val; - u32 command; - u32 status; - u8 *pbuf; - _sema sema; - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt); - u8 *cnxt; -}; - -struct intf_hdl { - _adapter *padapter; - struct dvobj_priv *pintf_dev;/* pointer to &(padapter->dvobjpriv); */ - struct _io_ops io_ops; -}; - -struct reg_protocol_rd { - -#ifdef CONFIG_LITTLE_ENDIAN - - /* DW1 */ - u32 NumOfTrans:4; - u32 Reserved1:4; - u32 Reserved2:24; - /* DW2 */ - u32 ByteCount:7; - u32 WriteEnable:1; /* 0:read, 1:write */ - u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ - u32 BurstMode:1; - u32 Byte1Access:1; - u32 Byte2Access:1; - u32 Byte4Access:1; - u32 Reserved3:3; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - /* DW4 */ - /* u32 Value; */ -#else - - - /* DW1 */ - u32 Reserved1:4; - u32 NumOfTrans:4; - - u32 Reserved2:24; - - /* DW2 */ - u32 WriteEnable:1; - u32 ByteCount:7; - - - u32 Reserved3:3; - u32 Byte4Access:1; - - u32 Byte2Access:1; - u32 Byte1Access:1; - u32 BurstMode:1; - u32 FixOrContinuous:1; - - u32 Reserved4:16; - - /* DW3 */ - u32 BusAddress; - - /* DW4 */ - /* u32 Value; */ - -#endif - -}; - - -struct reg_protocol_wt { - - -#ifdef CONFIG_LITTLE_ENDIAN - - /* DW1 */ - u32 NumOfTrans:4; - u32 Reserved1:4; - u32 Reserved2:24; - /* DW2 */ - u32 ByteCount:7; - u32 WriteEnable:1; /* 0:read, 1:write */ - u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ - u32 BurstMode:1; - u32 Byte1Access:1; - u32 Byte2Access:1; - u32 Byte4Access:1; - u32 Reserved3:3; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - /* DW4 */ - u32 Value; - -#else - /* DW1 */ - u32 Reserved1:4; - u32 NumOfTrans:4; - - u32 Reserved2:24; - - /* DW2 */ - u32 WriteEnable:1; - u32 ByteCount:7; - - u32 Reserved3:3; - u32 Byte4Access:1; - - u32 Byte2Access:1; - u32 Byte1Access:1; - u32 BurstMode:1; - u32 FixOrContinuous:1; - - u32 Reserved4:16; - - /* DW3 */ - u32 BusAddress; - - /* DW4 */ - u32 Value; - -#endif - -}; #ifdef CONFIG_PCI_HCI #define MAX_CONTINUAL_IO_ERR 4 #endif @@ -280,247 +37,4 @@ struct reg_protocol_wt { int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj); void rtw_reset_continual_io_error(struct dvobj_priv *dvobj); -/* -Below is the data structure used by _io_handler - -*/ - -struct io_queue { - _lock lock; - _list free_ioreqs; - _list pending; /* The io_req list that will be served in the single protocol read/write. */ - _list processing; - u8 *free_ioreqs_buf; /* 4-byte aligned */ - u8 *pallocated_free_ioreqs_buf; - struct intf_hdl intf; -}; - -struct io_priv { - - _adapter *padapter; - - struct intf_hdl intf; - -}; - -extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); -extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue); -extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); - - -extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); -extern struct io_req *alloc_ioreq(struct io_queue *pio_q); - -extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); -extern void unregister_intf_hdl(struct intf_hdl *pintfhdl); - -extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - -extern u8 _rtw_read8(_adapter *adapter, u32 addr); -extern u16 _rtw_read16(_adapter *adapter, u32 addr); -extern u32 _rtw_read32(_adapter *adapter, u32 addr); -extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern void _rtw_read_port_cancel(_adapter *adapter); - - -extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val); -extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val); -extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); -extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); - -#ifdef CONFIG_SDIO_HCI -u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr); -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -u8 _rtw_sd_iread8(_adapter *adapter, u32 addr); -u16 _rtw_sd_iread16(_adapter *adapter, u32 addr); -u32 _rtw_sd_iread32(_adapter *adapter, u32 addr); -int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val); -int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val); -int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val); -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ -#endif /* CONFIG_SDIO_HCI */ - -extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); -extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val); -extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val); - -extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms); -extern void _rtw_write_port_cancel(_adapter *adapter); - -#ifdef DBG_IO -u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val); -u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val); -bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask); -bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask); - -void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line); -void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line); - -extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); -extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); -extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line); - -extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); -extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); -extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); -extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line); - -#ifdef CONFIG_SDIO_HCI -u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line); -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line); -u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line); -u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line); -int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); -int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); -int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ -#endif /* CONFIG_SDIO_HCI */ - -#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__) -#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__) -#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__) -#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) -#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) -#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) - -#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) -#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) -#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) -#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) - -#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) -#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) -#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) - -#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) -#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) -#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) -#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) - -#ifdef CONFIG_SDIO_HCI -#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__) -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__) -#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__) -#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__) -#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__) -#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__) -#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__) -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ -#endif /* CONFIG_SDIO_HCI */ - -#else /* DBG_IO */ -#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) -#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) -#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) -#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) -#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) -#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) - -#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) -#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) -#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) -#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) - -#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) -#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) -#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) - -#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) -#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) -#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) -#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) - -#ifdef CONFIG_SDIO_HCI -#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr)) -#ifdef CONFIG_SDIO_INDIRECT_ACCESS -#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr)) -#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr)) -#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr)) -#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val)) -#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val)) -#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val)) -#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ -#endif /* CONFIG_SDIO_HCI */ - -#endif /* DBG_IO */ - -extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem); - -/* ioreq */ -extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval); -extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval); -extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval); -extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val); -extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val); -extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val); - - -extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); -extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); -extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); - -extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - -extern void async_write8(_adapter *adapter, u32 addr, u8 val, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); -extern void async_write16(_adapter *adapter, u32 addr, u16 val, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); -extern void async_write32(_adapter *adapter, u32 addr, u32 val, - void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); - -extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - - -int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops)); - - -extern uint alloc_io_queue(_adapter *adapter); -extern void free_io_queue(_adapter *adapter); -extern void async_bus_io(struct io_queue *pio_q); -extern void bus_sync_io(struct io_queue *pio_q); -extern u32 _ioreq2rwmem(struct io_queue *pio_q); - -/* -#define RTL_R8(reg) rtw_read8(padapter, reg) -#define RTL_R16(reg) rtw_read16(padapter, reg) -#define RTL_R32(reg) rtw_read32(padapter, reg) -#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8) -#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16) -#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32) -*/ - -/* -#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8) -#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16) -#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32) - -#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32) -#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg) -*/ - -#define PlatformEFIOWrite1Byte(_a, _b, _c) \ - rtw_write8(_a, _b, _c) -#define PlatformEFIOWrite2Byte(_a, _b, _c) \ - rtw_write16(_a, _b, _c) -#define PlatformEFIOWrite4Byte(_a, _b, _c) \ - rtw_write32(_a, _b, _c) - -#define PlatformEFIORead1Byte(_a, _b) \ - rtw_read8(_a, _b) -#define PlatformEFIORead2Byte(_a, _b) \ - rtw_read16(_a, _b) -#define PlatformEFIORead4Byte(_a, _b) \ - rtw_read32(_a, _b) - -#endif /* _RTL8711_IO_H_ */ +#endif /* _RTW_IO_H_ */ diff --git a/include/rtw_ioctl.h b/include/rtw_ioctl.h index 1143d97..a4a2866 100644 --- a/include/rtw_ioctl.h +++ b/include/rtw_ioctl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -22,7 +22,7 @@ enum oid_type { struct oid_par_priv { void *adapter_context; - NDIS_OID oid; + uint oid; void *information_buf; u32 information_buf_len; u32 *bytes_rw; diff --git a/include/rtw_ioctl_query.h b/include/rtw_ioctl_query.h index 7badcdd..db3ac9b 100644 --- a/include/rtw_ioctl_query.h +++ b/include/rtw_ioctl_query.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtw_ioctl_set.h b/include/rtw_ioctl_set.h index 82b4c18..2086ee1 100644 --- a/include/rtw_ioctl_set.h +++ b/include/rtw_ioctl_set.h @@ -19,10 +19,6 @@ u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICAT u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid); u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep); u8 rtw_set_802_11_disassociate(_adapter *padapter); -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm); -#ifdef CONFIG_RTW_ACS -u8 rtw_set_acs_sitesurvey(_adapter *adapter); -#endif u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags); u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid); u8 rtw_set_802_11_connect(_adapter *padapter, @@ -32,9 +28,9 @@ u8 rtw_validate_bssid(u8 *bssid); u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); u16 rtw_get_cur_max_rate(_adapter *adapter); -int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); -int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); -int rtw_set_country(_adapter *adapter, const char *country_code); +int rtw_set_scan_mode(_adapter *adapter, enum rtw_phl_scan_type scan_mode); +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan, u8 chplan_6g, enum rtw_regd_inr inr); +int rtw_set_country(_adapter *adapter, const char *country_code, enum rtw_regd_inr inr); int rtw_set_band(_adapter *adapter, u8 band); #endif diff --git a/include/rtw_mbo.h b/include/rtw_mbo.h index 9524cb6..1e960e5 100644 --- a/include/rtw_mbo.h +++ b/include/rtw_mbo.h @@ -12,14 +12,27 @@ * more details. * *****************************************************************************/ +#ifndef _RTW_MBO_H_ +#define _RTW_MBO_H_ -#ifndef __RTW_MBO_H_ -#define __RTW_MBO_H_ +#define MBO_CH_LIST_MAX_NUM 247 +#define MBO_OCE_ELEMENT_MAX_LEN 255 -#define rtw_mbo_wifi_logo_test(a) ((a->registrypriv.wifi_spec) == 1) +#define MBO_CH_PREFER_NON_OP 0 +#define MBO_CH_PREFER_NOT 1 +#define MBO_CH_PREFER_OK 255 -#define rtw_mbo_set_ext_cap_internw(_pEleStart, _val) \ - SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 7, 1, _val) +#define rtw_mbo_wifi_logo_test(a) \ + (((a)->registrypriv.wifi_spec) == 1) + +#define rtw_mbo_wifi_spec_test(a) \ + (((a)->mlmepriv.mbo_attr.mbo_spec_test) == 1) + +#define rtw_mbo_ap_assoc_disallow(a) \ + (((a)->mlmepriv.mbo_attr.assoc_disallow) > 0) + +#define rtw_mbo_add_internw_ext_cap(d, l) \ + rtw_add_ext_cap_info(d, l, INTERWORKING) #define rtw_mbo_wnm_notification_req(c, a) \ (((c) == RTW_WLAN_CATEGORY_WNM) && \ @@ -34,6 +47,8 @@ #define RTW_MBO_OUI 0x506F9A #define RTW_MBO_OUI_TYPE 0x16 +/* MBO AP Capability Indication */ +#define RTW_MBO_ATTR_AP_CAP_ID 0x1 /* Non-preferred Channel Report */ #define RTW_MBO_ATTR_NPREF_CH_RPT_ID 0x2 /* Cellular Data Capabilities */ @@ -45,12 +60,61 @@ /* Transition Rejection Reason Code */ #define RTW_MBO_ATTR_TRANS_REJ_ID 0x7 /* Association Retry Delay */ -#define RTW_MBO_ATTR_TASSOC_RETRY_ID 0x8 +#define RTW_MBO_ATTR_ASSOC_RETRY_DELAY_ID 0x8 #define RTW_MBO_MAX_CH_LIST_NUM MAX_CHANNEL_NUM #define RTW_MBO_MAX_CH_RPT_NUM 32 +#define RTW_MBO_TEST_CMD_REST 0x00 +#define RTW_MBO_TEST_CMD_BTM_REQ_SEND 0xfd +#define RTW_MBO_TEST_CMD_BTM_REQ_SET 0xfe +#define RTW_MBO_TEST_CMD_NB_BSS_ADD 0xff + +enum rtw_mbo_attri_type { + MBO_AP_CAPABILITY = 1, + NON_PREFER_CHANNEL_RPT = 2, + CELLULAR_DATA_CAPABILITY = 3, + ASSOCIATION_DISALLOW = 4, + CELLULAR_DATA_CONNECT_PREFER = 5, + TRANS_REASON_CODE = 6, + TRANS_REJECT_REASON_CODE = 7, + ASSOCIATION_RETRY_DELAY = 8 +}; + +struct rtw_mbo_ch_list { + u8 op_class; + u8 channel; + u8 preference; +}; + +struct mbo_priv { + u8 enable; + u8 assoc_disallow; + u8 cellular_aware; + struct rtw_mbo_ch_list ch_list[MBO_CH_LIST_MAX_NUM]; + u8 ch_list_num; + u8 mbo_oce_element[MBO_OCE_ELEMENT_MAX_LEN]; + u8 mbo_oce_element_len; +}; + +struct mbo_user_btm_req_pkt { + struct btm_req_hdr hdr; + u32 candidate_cnt; + struct wnm_btm_cant btm_cants[RTW_MAX_NB_RPT_NUM]; + u8 append_mbo_ie; +}; + +struct mbo_attr_info { + u8 mbo_spec_test; + u8 ap_cap_ind; + u8 assoc_disallow; + u8 cell_data_cap; + u8 reason; + u16 delay; + struct mbo_user_btm_req_pkt user_raw; +}; + struct npref_ch { u8 op_class; u8 chs[RTW_MBO_MAX_CH_LIST_NUM]; @@ -64,12 +128,23 @@ struct npref_ch_rtp { size_t nm_of_rpt; }; + +void rtw_mbo_ie_handler(_adapter *padapter, struct mbo_priv *mbopriv, + const u8 *pbuf, uint limit_len); +struct sta_info; +void rtw_ap_parse_sta_mbo_element(_adapter *padapter, + struct sta_info *psta, u8 *ies_buf, u16 ies_len); +void rtw_mbo_fill_non_prefer_channel_list(_adapter *padapter, struct mbo_priv *mbopriv, + const u8 *pbuf, u8 len); + + + void rtw_mbo_build_cell_data_cap_attr( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); void rtw_mbo_update_ie_data( _adapter *padapter, u8 *pie, u32 ie_len); - + void rtw_mbo_build_supp_op_class_elem( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); @@ -81,11 +156,11 @@ void rtw_mbo_build_trans_reject_reason_attr( u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork); -void rtw_mbo_build_exented_cap( +void rtw_mbo_build_extended_cap( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); ssize_t rtw_mbo_proc_non_pref_chans_set( - struct file *pfile, const char __user *buffer, + struct file *pfile, const char __user *buffer, size_t count, loff_t *pos, void *pdata); int rtw_mbo_proc_non_pref_chans_get( @@ -98,6 +173,13 @@ ssize_t rtw_mbo_proc_cell_data_set( int rtw_mbo_proc_cell_data_get( struct seq_file *m, void *v); +ssize_t rtw_mbo_proc_attr_set( + struct file *pfile, const char __user *buffer, + size_t count, loff_t *pos, void *pdata); + +int rtw_mbo_proc_attr_get( + struct seq_file *m, void *v); + void rtw_mbo_wnm_notification_parsing( _adapter *padapter, const u8 *pdata, size_t data_len); @@ -110,5 +192,22 @@ void rtw_mbo_build_probe_req_ies( void rtw_mbo_build_assoc_req_ies( _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); -#endif /* __RTW_MBO_H_ */ +void rtw_mbo_attr_info_init(_adapter *padapter); + +void rtw_mbo_process_assoc_req( + _adapter *padapter, u8 *pie, int ie_len); + +void rtw_mbo_build_beacon_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); + +void rtw_mbo_build_probe_rsp_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); + +void rtw_mbo_build_assoc_rsp_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); + +void rtw_mbo_build_wnm_btmreq_reason_ies( + _adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib); + +#endif /* _RTW_MBO_H_ */ diff --git a/include/rtw_mcc.h b/include/rtw_mcc.h index 5d2198b..d7e3403 100644 --- a/include/rtw_mcc.h +++ b/include/rtw_mcc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2017 Realtek Corporation. + * Copyright(c) 2015 - 2020 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,304 +12,3 @@ * more details. * *****************************************************************************/ -#ifdef CONFIG_MCC_MODE - -#ifndef _RTW_MCC_H_ -#define _RTW_MCC_H_ - -#include /* PADAPTER */ - -#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0 -#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1 -#define MCC_STATUS_NEED_MCC BIT2 -#define MCC_STATUS_DOING_MCC BIT3 - - -#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ -#define MCC_EXPIRE_TIME 50 /* ms */ -#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ -#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */ - -#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0 -#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1 - -/* Lower for stop, Higher for start */ -#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0 -#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1 -#define MCC_SETCMD_STATUS_START_CONNECT 0x80 -#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81 - -/* -* depenad platform or customer requirement(TP unit:Mbps), -* must be provided by PM or sales or product document -* too large value means not to limit tx bytes (current for ap mode) -* NOTE: following values ref from test results -*/ -#define MCC_AP_BW20_TARGET_TX_TP (300) -#define MCC_AP_BW40_TARGET_TX_TP (300) -#define MCC_AP_BW80_TARGET_TX_TP (300) -#define MCC_STA_BW20_TARGET_TX_TP (35) -#define MCC_STA_BW40_TARGET_TX_TP (70) -#define MCC_STA_BW80_TARGET_TX_TP (140) -#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */ - -#define MAX_MCC_NUM 2 -#ifdef CONFIG_RTL8822C -#define DBG_MCC_REG_NUM 3 -#else -#define DBG_MCC_REG_NUM 4 -#endif -#define DBG_MCC_RF_REG_NUM 1 - -#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop) -#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc) -#define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv)) -#define SET_MCC_EN_FLAG(adapter, flag)\ - do { \ - adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \ - } while (0) -#define SET_MCC_DURATION(adapter, val)\ - do { \ - adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \ - } while (0) -#define SET_MCC_RUNTIME_DURATION(adapter, flag)\ - do { \ - adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \ - } while (0) - -#define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\ - do { \ - adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \ - } while (0) - -#ifdef CONFIG_MCC_PHYDM_OFFLOAD -enum mcc_cfg_phydm_ops { - MCC_CFG_PHYDM_OFFLOAD = 0, - MCC_CFG_PHYDM_RF_CH, - MCC_CFG_PHYDM_ADD_CLIENT, - MCC_CFG_PHYDM_REMOVE_CLIENT, - MCC_CFG_PHYDM_START, - MCC_CFG_PHYDM_STOP, - MCC_CFG_PHYDM_DUMP, - MCC_CFG_PHYDM_MAX, -}; -#endif - -enum rtw_mcc_cmd_id { - MCC_CMD_WK_CID = 0, - MCC_SET_DURATION_WK_CID, - MCC_GET_DBG_REG_WK_CID, - #ifdef CONFIG_MCC_PHYDM_OFFLOAD - MCC_SET_PHYDM_OFFLOAD_WK_CID, - #endif -}; - -/* Represent Channel Tx Null setting */ -enum mcc_channel_tx_null { - MCC_ENABLE_TX_NULL = 0, - MCC_DISABLE_TX_NULL = 1, -}; - -/* Represent C2H Report setting */ -enum mcc_c2h_report { - MCC_C2H_REPORT_DISABLE = 0, - MCC_C2H_REPORT_FAIL_STATUS = 1, - MCC_C2H_REPORT_ALL_STATUS = 2, -}; - -/* Represent Channel Scan */ -enum mcc_channel_scan { - MCC_CHIDX = 0, - MCC_SCANCH_RSVD_LOC = 1, -}; - -/* Represent FW status report of channel switch */ -enum mcc_status_rpt { - MCC_RPT_SUCCESS = 0, - MCC_RPT_TXNULL_FAIL = 1, - MCC_RPT_STOPMCC = 2, - MCC_RPT_READY = 3, - MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, - MCC_RPT_UPDATE_NOA_START_TIME = 8, - MCC_RPT_TSF = 9, - MCC_RPT_MAX, -}; - -enum mcc_role { - MCC_ROLE_STA = 0, - MCC_ROLE_AP = 1, - MCC_ROLE_GC = 2, - MCC_ROLE_GO = 3, - MCC_ROLE_MAX, -}; - -struct mcc_iqk_backup { - u16 TX_X; - u16 TX_Y; - u16 RX_X; - u16 RX_Y; -}; - -enum mcc_duration_setting { - MCC_DURATION_MAPPING = 0, - MCC_DURATION_DIRECET = 1, -}; - -enum mcc_sched_mode { - MCC_FAIR_SCHEDULE = 0, - MCC_FAVOR_STA = 1, - MCC_FAVOR_P2P = 2, -}; - -/* mcc data for adapter */ -struct mcc_adapter_priv { - u8 order; /* FW document, softap/AP must be 0 */ - enum mcc_role role; /* MCC role(AP,STA,GO,GC) */ - u8 mcc_duration; /* channel stay period, UNIT:1TU */ - - /* flow control */ - u8 mcc_tx_stop; /* check if tp stop or not */ - u8 mcc_tp_limit; /* check if tp limit or not */ - u32 mcc_target_tx_bytes_to_port; /* customer require */ - u32 mcc_tx_bytes_to_port; /* already tx to tx fifo (write port) */ - - /* data from kernel to check if enqueue data or netif stop queue */ - u32 mcc_tp; - u64 mcc_tx_bytes_from_kernel; - u64 mcc_last_tx_bytes_from_kernel; - - /* Backup IQK value for MCC */ - struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH]; - - /* mgmt queue macid to avoid RA issue */ - u8 mgmt_queue_macid; - - /* set macid bitmap to let fw know which macid should be tx pause */ - /* all interface share total 16 macid */ - u16 mcc_macid_bitmap; - - /* use for NoA start time (unit: mircoseconds) */ - u32 noa_start_time; - - u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; - u32 p2p_go_noa_ie_len; - u64 tsf; -#ifdef CONFIG_TDLS - u8 backup_tdls_en; -#endif /* CONFIG_TDLS */ - - u8 null_early; - u8 null_rty_num; -}; - -struct mcc_obj_priv { - u8 en_mcc; /* enable MCC or not */ - u8 duration; /* store duration(%) from registry, for primary adapter */ - u8 interval; - u8 start_time; - u8 mcc_c2h_status; - u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */ - u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */ - u8 mcc_tolerance_time; /* used for detect mcc switch channel success */ - u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ - u8 mcc_status; /* mcc status stop or start .... */ - u8 policy_index; - u8 mcc_stop_threshold; - u8 current_order; - u8 last_tsfdiff; - systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ - _mutex mcc_mutex; - _lock mcc_lock; - PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */ - struct submit_ctx mcc_sctx; - struct submit_ctx mcc_tsf_req_sctx; - _mutex mcc_tsf_req_mutex; - u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */ -#ifdef CONFIG_MCC_MODE_V2 - u8 mcc_iqk_value_rsvd_page[3]; -#endif /* CONFIG_MCC_MODE_V2 */ - u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM]; - u8 enable_runtime_duration; - /* for LG */ - u8 mchan_sched_mode; - - _mutex mcc_dbg_reg_mutex; - u32 dbg_reg[DBG_MCC_REG_NUM]; - u32 dbg_reg_val[DBG_MCC_REG_NUM]; - u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM]; - u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH]; - u8 mcc_phydm_offload; -}; - -/* backup IQK val */ -void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter); - -/* check mcc status */ -u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status); - -/* set mcc status */ -void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status); - -/* clear mcc status */ -void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status); - -/* dl mcc rsvd page */ -u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index - , u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num); - -/* handle C2H */ -void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf); - -/* switch channel successfully or not */ -void rtw_hal_mcc_sw_status_check(PADAPTER padapter); - -/* change some scan flags under site survey */ -u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset); - -/* record data kernel TX to driver to check MCC concurrent TX */ -void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len); - -/* record data to port to let driver do flow ctrl */ -void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len); - -/* check stop write port or not */ -u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter); - -u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter); - -u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter); - -u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped); - -u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter); - -u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter); - -u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow); - -void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj); - -void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); - -u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg); - -void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); - -u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); - -void rtw_hal_dump_mcc_policy_table(void *sel); - -void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add); - -void rtw_hal_mcc_process_noa(PADAPTER padapter); - -void rtw_hal_mcc_parameter_init(PADAPTER padapter); - -u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val); - -u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val); -#ifdef CONFIG_MCC_PHYDM_OFFLOAD -u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue); -#endif /* CONFIG_MCC_PHYDM_OFFLOAD */ -#endif /* _RTW_MCC_H_ */ -#endif /* CONFIG_MCC_MODE */ diff --git a/include/rtw_mem.h b/include/rtw_mem.h index 9e33ed5..5b61fb1 100644 --- a/include/rtw_mem.h +++ b/include/rtw_mem.h @@ -19,6 +19,18 @@ #include #include +#ifdef CONFIG_SDIO_HCI +#define MAX_RTKM_RECVBUF_SZ MAX_RECVBUF_SZ +#define MAX_RTKM_NR_PREALLOC_RECV_SKB NR_RECVBUFF +#else /* !CONFIG_SDIO_HCI */ +#ifdef CONFIG_PLATFORM_MSTAR_HIGH + #define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */ +#else + #define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */ +#endif /* CONFIG_PLATFORM_MSTAR_HIGH */ +#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16 +#endif /* !CONFIG_SDIO_HCI */ + u16 rtw_rtkm_get_buff_size(void); u8 rtw_rtkm_get_nr_recv_skb(void); struct u8 *rtw_alloc_revcbuf_premem(void); diff --git a/include/rtw_mi.h b/include/rtw_mi.h index 0eb8b53..bc44c4f 100644 --- a/include/rtw_mi.h +++ b/include/rtw_mi.h @@ -45,7 +45,9 @@ struct mi_state { u8 scan_enter_num; /* WIFI_UNDER_SURVEY && !SCAN_DISABLE && !SCAN_BACK_OP */ u8 uwps_num; /* WIFI_UNDER_WPS */ #ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_P2P u8 roch_num; + #endif u8 mgmt_tx_num; #endif #ifdef CONFIG_P2P @@ -53,6 +55,9 @@ struct mi_state { u8 p2p_gc; u8 p2p_go; #endif + u8 union_ch; + u8 union_bw; + u8 union_offset; }; #define MSTATE_STA_NUM(_mstate) ((_mstate)->sta_num) @@ -90,7 +95,7 @@ struct mi_state { #define MSTATE_SCAN_ENTER_NUM(_mstate) ((_mstate)->scan_enter_num) #define MSTATE_WPS_NUM(_mstate) ((_mstate)->uwps_num) -#if defined(CONFIG_IOCTL_CFG80211) +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) #define MSTATE_ROCH_NUM(_mstate) ((_mstate)->roch_num) #else #define MSTATE_ROCH_NUM(_mstate) 0 @@ -112,9 +117,13 @@ struct mi_state { #define MSTATE_MGMT_TX_NUM(_mstate) 0 #endif -#define rtw_mi_get_union_chan(adapter) ((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_ch) : (adapter_to_dvobj(adapter)->union_ch_bak)) -#define rtw_mi_get_union_bw(adapter) ((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_bw) : (adapter_to_dvobj(adapter)->union_bw_bak)) -#define rtw_mi_get_union_offset(adapter) ((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_offset) : (adapter_to_dvobj(adapter)->union_offset_bak)) +#define MSTATE_U_CH(_mstate) ((_mstate)->union_ch) +#define MSTATE_U_BW(_mstate) ((_mstate)->union_bw) +#define MSTATE_U_OFFSET(_mstate) ((_mstate)->union_offset) + +#define rtw_mi_get_union_chan(adapter) adapter_to_dvobj(adapter)->iface_state.union_ch +#define rtw_mi_get_union_bw(adapter) adapter_to_dvobj(adapter)->iface_state.union_bw +#define rtw_mi_get_union_offset(adapter) adapter_to_dvobj(adapter)->iface_state.union_offset #define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) #define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter)) @@ -150,25 +159,19 @@ u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter); void rtw_mi_scan_abort(_adapter *adapter, bool bwait); void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait); +#if 0 u32 rtw_mi_start_drv_threads(_adapter *adapter); u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter); void rtw_mi_stop_drv_threads(_adapter *adapter); void rtw_mi_buddy_stop_drv_threads(_adapter *adapter); +#endif + void rtw_mi_cancel_all_timer(_adapter *adapter); void rtw_mi_buddy_cancel_all_timer(_adapter *adapter); void rtw_mi_reset_drv_sw(_adapter *adapter); void rtw_mi_buddy_reset_drv_sw(_adapter *adapter); -extern void rtw_intf_start(_adapter *adapter); -extern void rtw_intf_stop(_adapter *adapter); -void rtw_mi_intf_start(_adapter *adapter); -void rtw_mi_buddy_intf_start(_adapter *adapter); -void rtw_mi_intf_stop(_adapter *adapter); -void rtw_mi_buddy_intf_stop(_adapter *adapter); - -#ifdef CONFIG_NEW_NETDEV_HDL u8 rtw_mi_hal_iface_init(_adapter *padapter); -#endif void rtw_mi_suspend_free_assoc_resource(_adapter *adapter); void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter); @@ -186,15 +189,6 @@ u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter); void rtw_mi_beacon_update(_adapter *padapter); void rtw_mi_buddy_beacon_update(_adapter *padapter); -#ifndef CONFIG_MI_WITH_MBSSID_CAM -void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter); -void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter); -#endif - -#ifdef CONFIG_PCI_HCI -void rtw_mi_xmit_tasklet_schedule(_adapter *padapter); -void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter); -#endif u8 rtw_mi_busy_traffic_check(_adapter *padapter); u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter); @@ -235,24 +229,18 @@ u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter); #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -#ifdef CONFIG_RTL8822B - #include -#elif defined(CONFIG_RTL8822C) - #include -#elif defined(CONFIG_RTL8723F) - #include -#else - extern s32 _dequeue_writeport(PADAPTER padapter); -#endif -u8 rtw_mi_dequeue_writeport(_adapter *padapter); -u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter); +u8 rtw_mi_sdio_dequeue_xmit(_adapter *padapter); +u8 rtw_mi_sdio_buddy_dequeue_xmit(_adapter *padapter); #endif void rtw_mi_adapter_reset(_adapter *padapter); void rtw_mi_buddy_adapter_reset(_adapter *padapter); +u8 rtw_mi_dynamic_check_handlder(struct _ADAPTER *padapter); +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter); u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter); +#endif extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter); u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter); @@ -268,21 +256,17 @@ extern void sreset_start_adapter(_adapter *padapter); extern void sreset_stop_adapter(_adapter *padapter); u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart); u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart); - -#ifdef CONFIG_AP_MODE #if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) void rtw_mi_ap_info_restore(_adapter *adapter); #endif + u8 rtw_mi_tx_beacon_hdl(_adapter *padapter); u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter); u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter); u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter); -#endif /* CONFIG_AP_MODE */ #ifdef CONFIG_P2P -u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); -u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter); u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter); #endif @@ -291,7 +275,8 @@ _adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id); _adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr); _adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port); -void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status); +void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe); + #ifdef CONFIG_PCI_HCI /*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/ @@ -300,6 +285,9 @@ _adapter *rtw_mi_get_ap_adapter(_adapter *padapter); u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter); u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter); -void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b); + + +u8 rtw_mi_disconnect(_adapter *adapter); +u8 rtw_mi_buddy_disconnect(_adapter *adapter); #endif /*__RTW_MI_H_*/ diff --git a/include/rtw_mlme.h b/include/rtw_mlme.h index e3095a5..cb567d2 100644 --- a/include/rtw_mlme.h +++ b/include/rtw_mlme.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -29,8 +29,8 @@ #define UNASSOC_STA_LIFETIME_MS 60000 /*pmlmepriv->fw_state*/ -#define WIFI_NULL_STATE 0x00000000 -#define WIFI_ASOC_STATE 0x00000001 /* Linked */ +#define WIFI_NULL_STATE 0x00000000 +#define WIFI_ASOC_STATE 0x00000001 /* Linked */ #define WIFI_REASOC_STATE 0x00000002 #define WIFI_SLEEP_STATE 0x00000004 #define WIFI_STATION_STATE 0x00000008 @@ -39,7 +39,7 @@ #define WIFI_ADHOC_MASTER_STATE 0x00000040 #define WIFI_UNDER_LINKING 0x00000080 #define WIFI_UNDER_WPS 0x00000100 -#define WIFI_MESH_STATE 0x00000200 +#define WIFI_MESH_STATE 0x00000200 #define WIFI_STA_ALIVE_CHK_STATE 0x00000400 #define WIFI_UNDER_SURVEY 0x00000800 /* under site surveying */ /*#define WIFI_UNDEFINED_STATE 0x00001000*/ @@ -51,7 +51,7 @@ /*#define WIFI_UNDEFINED_STATE 0x00040000*/ /*#define WIFI_UNDEFINED_STATE 0x00080000*/ /*#define WIFI_UNDEFINED_STATE 0x00100000*/ -/*#define WIFI_UNDEFINED_STATE 0x00200000*/ +/*#define WIFI_UNDEFINED_STATE 0x00200000*/ /*#define WIFI_UNDEFINED_STATE 0x00400000*/ #define WIFI_OP_CH_SWITCHING 0x00800000 #define WIFI_UNDER_KEY_HANDSHAKE 0x01000000 @@ -106,7 +106,7 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING) #define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS) -#ifdef CONFIG_IOCTL_CFG80211 +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) #define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE) #else #define MLME_IS_ROCH(adapter) 0 @@ -159,14 +159,7 @@ enum { MLME_MESH_STOPPED, MLME_OPCH_SWITCH, }; -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN -enum MODE_WOW_KEEP_ALIVE_PATTERN { - wow_keep_alive_pattern_disable = 0, - wow_keep_alive_pattern_tx, - wow_keep_alive_pattern_trx, - wow_keep_alive_pattern_trx_with_ack -}; -#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ + enum dot11AuthAlgrthmNum { dot11AuthAlgrthm_Open = 0, dot11AuthAlgrthm_Shared, @@ -209,12 +202,6 @@ enum mlme_auth_type { MLME_AUTHTYPE_AUTOMATIC }; -/* Scan type including active and passive scan. */ -typedef enum _RT_SCAN_TYPE { - SCAN_PASSIVE, - SCAN_ACTIVE, - SCAN_MIX, -} RT_SCAN_TYPE, *PRT_SCAN_TYPE; #define WIFI_FREQUENCY_BAND_AUTO 0 #define WIFI_FREQUENCY_BAND_5GHZ 1 @@ -222,11 +209,6 @@ typedef enum _RT_SCAN_TYPE { #define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ) -enum DriverInterface { - DRIVER_WEXT = 1, - DRIVER_CFG80211 = 2 -}; - enum SCAN_RESULT_TYPE { SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */ SCAN_RESULT_ALL = 1, /* Will return all the scanned device, include AP. */ @@ -268,28 +250,6 @@ typedef struct _RT_LINK_DETECT_T { u32 LowPowerTransitionCount; } RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; -struct profile_info { - u8 ssidlen; - u8 ssid[WLAN_SSID_MAXLEN]; - u8 peermac[ETH_ALEN]; -}; - -struct tx_invite_req_info { - u8 token; - u8 benable; - u8 go_ssid[WLAN_SSID_MAXLEN]; - u8 ssidlen; - u8 go_bssid[ETH_ALEN]; - u8 peer_macaddr[ETH_ALEN]; - u8 operating_ch; /* This information will be set by using the p2p_set op_ch=x */ - u8 peer_ch; /* The listen channel for peer P2P device */ - -}; - -struct tx_invite_resp_info { - u8 token; /* Used to record the dialog token of p2p invitation request frame. */ -}; - #ifdef CONFIG_WFD struct wifi_display_info { @@ -318,41 +278,19 @@ struct wifi_display_info { }; #endif /* CONFIG_WFD */ -struct tx_provdisc_req_info { - u16 wps_config_method_request; /* Used when sending the provisioning request frame */ - u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ - NDIS_802_11_SSID ssid; - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ - u8 peerIFAddr[ETH_ALEN]; /* Peer interface address */ - u8 benable; /* This provision discovery request frame is trigger to send or not */ -}; - -struct rx_provdisc_req_info { /* When peer device issue prov_disc_req first, we should store the following informations */ - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ - u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */ - /* The UI must know this information to know which config method the remote p2p device is requiring. */ -}; - -struct tx_nego_req_info { - u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ - u8 benable; /* This negoitation request frame is trigger to send or not */ - u8 peer_ch; /* The listen channel for peer P2P device */ -}; - -struct group_id_info { - u8 go_device_addr[ETH_ALEN]; /* The GO's device address of this P2P group */ - u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */ -}; - -struct scan_limit_info { - u8 scan_op_ch_only; /* When this flag is set, the driver should just scan the operation channel */ -#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH - u8 operation_ch[2]; /* Store the operation channel of invitation request frame */ -#else - u8 operation_ch[5]; /* Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 */ -#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */ +#ifdef CONFIG_IOCTL_CFG80211 +struct cfg80211_roch_info { + u8 restore_channel; + struct ieee80211_channel remain_on_ch_channel; + enum nl80211_channel_type remain_on_ch_type; + unsigned int duration; + ATOMIC_T ro_ch_cookie_gen; + u64 remain_on_ch_cookie; + bool is_ro_ch; + struct wireless_dev *ro_ch_wdev; + systime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ }; +#endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_P2P_WOWLAN @@ -376,23 +314,7 @@ struct p2p_wowlan_info { struct wifidirect_info { _adapter *padapter; - _timer find_phase_timer; - _timer restore_p2p_state_timer; - - /* Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */ - _timer pre_tx_scan_timer; - _timer reset_ch_sitesurvey; - _timer reset_ch_sitesurvey2; /* Just for resetting the scan limit function by using p2p nego */ - - struct tx_provdisc_req_info tx_prov_disc_info; - struct rx_provdisc_req_info rx_prov_disc_info; - struct tx_invite_req_info invitereq_info; - struct profile_info profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM]; /* Store the profile information of persistent group */ - struct tx_invite_resp_info inviteresp_info; - struct tx_nego_req_info nego_req_info; - struct group_id_info groupid_info; /* Store the group id information when doing the group negotiation handshake. */ - struct scan_limit_info rx_invitereq_info; /* Used for get the limit scan channel from the Invitation procedure */ - struct scan_limit_info p2p_info; /* Used for get the limit scan channel from the P2P negotiation handshake */ + #ifdef CONFIG_WFD struct wifi_display_info *wfd_info; #endif @@ -402,40 +324,9 @@ struct wifidirect_info { #endif /* CONFIG_P2P_WOWLAN */ enum P2P_ROLE role; - enum P2P_STATE pre_p2p_state; - enum P2P_STATE p2p_state; - u8 device_addr[ETH_ALEN]; /* The device address should be the mac address of this device. */ - u8 interface_addr[ETH_ALEN]; - u8 social_chan[4]; u8 listen_channel; - u8 operating_channel; - u8 listen_dwell; /* This value should be between 1 and 3 */ u8 support_rate[8]; u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; - u8 intent; /* should only include the intent value. */ - u8 p2p_peer_interface_addr[ETH_ALEN]; - u8 p2p_peer_device_addr[ETH_ALEN]; - u8 peer_intent; /* Included the intent value and tie breaker value. */ - u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ - u16 device_name_len; - u8 profileindex; /* Used to point to the index of profileinfo array */ - u8 peer_operating_ch; - u8 find_phase_state_exchange_cnt; - u16 device_password_id_for_nego; /* The device password ID for group negotation */ - u8 negotiation_dialog_token; - u8 nego_ssid[WLAN_SSID_MAXLEN]; /* SSID information for group negotitation */ - u8 nego_ssidlen; - u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; - u8 p2p_group_ssid_len; - u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */ - /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ - /* 0: disable */ - /* 1: enable */ - u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */ - /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ - /* 0: disable */ - /* 1: enable */ - u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */ /* 0: disable */ /* 1: enable */ @@ -446,20 +337,6 @@ struct wifidirect_info { /* In this case, the driver can issue the tdls setup request frame */ /* even the current security is weak security. */ - enum P2P_WPSINFO ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */ - u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */ - /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ - u8 external_uuid; /* UUID flag */ - u8 uuid[16]; /* UUID */ - uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ - u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */ - /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ - u8 driver_interface; /* Indicate DRIVER_WEXT or DRIVER_CFG80211 */ - -#ifdef CONFIG_CONCURRENT_MODE - u16 ext_listen_interval; /* The interval to be available with legacy AP (ms) */ - u16 ext_listen_period; /* The time period to be available for P2P listen state (ms) */ -#endif #ifdef CONFIG_P2P_PS enum P2P_PS_MODE p2p_ps_mode; /* indicate p2p ps mode */ enum P2P_PS_STATE p2p_ps_state; /* indicate p2p ps state */ @@ -472,6 +349,10 @@ struct wifidirect_info { u32 noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */ u32 noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */ #endif /* CONFIG_P2P_PS */ +#ifdef ROKU_PRIVATE + u8 remote_mac_address[48]; /* For Roku find remote function */ + u32 num_of_remote; +#endif }; struct tdls_ss_record { /* signal strength record */ @@ -492,7 +373,6 @@ struct tdls_ch_switch { u8 addr[ETH_ALEN]; u8 off_ch_num; u8 ch_offset; - u8 bcn_early_reg_bkp; u32 cur_time; u8 delay_switch_back; u8 dump_stack; @@ -567,6 +447,11 @@ struct unassoc_sta_info { }; #endif +#ifdef ROKU_PRIVATE +#define MAX_VENDOR_IE_NUM 10 +#define MAX_VENDOR_IE_LEN 255 +#define MAX_VENDOR_IE_PARAM_LEN MAX_VENDOR_IE_LEN + 2 /* vendor ie filter index + content maximum length */ +#endif struct mlme_priv { _lock lock; @@ -606,9 +491,8 @@ struct mlme_priv { /* bcn check info */ struct beacon_keys cur_beacon_keys; /* save current beacon keys */ -#ifdef CONFIG_BCN_CNT_CONFIRM_HDL - struct beacon_keys new_beacon_keys; /* save new beacon keys */ - u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */ +#if CONFIG_DFS + u8 bcn_cnts_after_csa; #endif #ifdef CONFIG_ARP_KEEP_ALIVE @@ -639,6 +523,11 @@ struct mlme_priv { struct qos_priv qospriv; +#ifdef CONFIG_80211D + u8 *recv_country_ie; + u32 recv_country_ie_len; +#endif + #ifdef CONFIG_80211N_HT /* Number of non-HT AP/stations */ @@ -662,6 +551,14 @@ struct mlme_priv { #endif /* ROKU_PRIVATE */ #endif +#ifdef CONFIG_80211AX_HE + struct he_priv hepriv; +#endif + +#ifdef CONFIG_RTW_MBO + struct mbo_priv mbopriv; +#endif + #ifdef ROKU_PRIVATE struct ht_priv_infra_ap htpriv_infra_ap; #endif /* ROKU_PRIVATE */ @@ -677,12 +574,12 @@ struct mlme_priv { RT_LINK_DETECT_T LinkDetectInfo; u8 acm_mask; /* for wmm acm mask */ - RT_SCAN_TYPE scan_mode; /* active: 1, passive: 0 */ + enum rtw_phl_scan_type scan_mode; /* active: 1, passive: 0 */ u8 *wps_probe_req_ie; u32 wps_probe_req_ie_len; - u8 ext_capab_ie_data[8];/*currently for ap mode only*/ + u8 ext_capab_ie_data[WLAN_EID_EXT_CAP_MAX_LEN];/*currently for ap mode only*/ u8 ext_capab_ie_len; #if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) @@ -724,14 +621,12 @@ struct mlme_priv { u8 *auth_rsp; u32 auth_rsp_len; #endif -#endif /* CONFIG_AP_MODE and CONFIG_NATIVEAP_MLME */ - u8 *assoc_req; u32 assoc_req_len; + u8 *assoc_rsp; u32 assoc_rsp_len; -#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) /* u8 *wps_probe_req_ie; */ /* u32 wps_probe_req_ie_len; */ @@ -763,16 +658,12 @@ struct mlme_priv { u32 p2p_assoc_resp_ie_len; _lock bcn_update_lock; - u8 update_bcn; + u8 update_bcn; - u8 ori_ch; - u8 ori_bw; - u8 ori_offset; + struct rtw_chan_def ori_chandef; #ifdef CONFIG_80211AC_VHT u8 ori_vht_en; #endif - - u8 ap_isolate; #endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) @@ -798,6 +689,7 @@ struct mlme_priv { #ifdef CONFIG_RTW_MBO u8 *pcell_data_cap_ie; u32 cell_data_cap_len; + struct mbo_attr_info mbo_attr; #endif #ifdef RTK_DMP_PLATFORM @@ -826,11 +718,11 @@ struct mlme_priv { u8 *free_unassoc_sta_buf; u32 interested_unassoc_sta_cnt; u32 max_unassoc_sta_cnt; -#ifdef CONFIG_PLATFORM_CMAP_INTFS - struct unassoc_sta_info cmap_unassoc_sta[CMAP_UNASSOC_METRICS_STA_MAX]; - u8 cmap_unassoc_sta_cnt; - _timer cmap_unassoc_sta_timer; #endif +#ifdef ROKU_PRIVATE + u8 vendor_ie_filter[MAX_VENDOR_IE_NUM][MAX_VENDOR_IE_LEN]; + u8 vendor_ie_len[MAX_VENDOR_IE_NUM]; + u8 vendor_ie_filter_enable; #endif }; @@ -845,6 +737,17 @@ struct mlme_priv { adapter->mlmepriv.auto_scan_int_ms = ms; \ } while (0) +#define set_assoc_timer(mlme, ms) \ + do { \ + /*RTW_INFO("%s set_assoc_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms));*/ \ + _set_timer(&(mlme)->assoc_timer, (ms)); \ + } while (0) +#define cancel_assoc_timer(mlme) \ + do { \ + /*RTW_INFO("%s cancel_assoc_timer(%p)\n", __FUNCTION__, (mlme));*/ \ + _cancel_timer_ex(&(mlme)->assoc_timer); \ + } while (0) + #define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 #define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 #define RTW_AUTO_SCAN_REASON_ACS BIT1 @@ -871,18 +774,13 @@ extern void hostapd_mode_unload(_adapter *padapter); extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status); -extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); -extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); -void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id); -void rtw_sta_mstatus_report(_adapter *adapter); -extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); +extern void rtw_wmm_event_callback(_adapter *padapter, u8 *pbuf); #ifdef CONFIG_IEEE80211W void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); #endif /* CONFIG_IEEE80211W */ -thread_return event_thread(thread_context context); extern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall); extern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */ @@ -950,43 +848,34 @@ static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) */ static inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) { - _irqL irqL; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); _clr_fwstate_(pmlmepriv, state); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } static inline void up_scanned_network(struct mlme_priv *pmlmepriv) { - _irqL irqL; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); pmlmepriv->num_of_scanned++; - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } u8 rtw_is_adapter_up(_adapter *padapter); __inline static void down_scanned_network(struct mlme_priv *pmlmepriv) { - _irqL irqL; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); pmlmepriv->num_of_scanned--; - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } __inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) { - _irqL irqL; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); pmlmepriv->num_of_scanned = val; - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); } extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); -extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc); extern void rtw_generate_random_ibss(u8 *pibss); struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr); @@ -1000,14 +889,9 @@ extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_ge extern void rtw_indicate_connect(_adapter *adapter); void rtw_indicate_scan_done(_adapter *padapter, bool aborted); -void rtw_drv_scan_by_self(_adapter *padapter, u8 reason); -void rtw_scan_wait_completed(_adapter *adapter); -u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms); -void rtw_scan_abort_no_wait(_adapter *adapter); -void rtw_scan_abort(_adapter *adapter); u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms); -int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid); +int rtw_cached_pmkid(_adapter *adapter, u8 *bssid); int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent); extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie); @@ -1023,45 +907,19 @@ extern void rtw_update_registrypriv_dev_network(_adapter *adapter); extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); extern void rtw_join_timeout_handler(void *ctx); -extern void rtw_scan_timeout_handler(void *ctx); +extern void rtw_iface_dynamic_check_handlder(struct _ADAPTER *a); +#ifdef CONFIG_CMD_GENERAL +void rtw_core_watchdog_sw_hdlr(void *drv_priv); +void rtw_core_watchdog_hw_hdlr(void *drv_priv); +#else +extern int rtw_dynamic_check_handlder(void *ctx, void* param, bool discard); +#endif +#if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ extern void rtw_dynamic_check_timer_handlder(void *ctx); extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter); - -enum { - SS_DENY_MP_MODE, - SS_DENY_RSON_SCANING, - SS_DENY_BLOCK_SCAN, - SS_DENY_BY_DRV, - SS_DENY_SELF_AP_UNDER_WPS, - SS_DENY_SELF_AP_UNDER_LINKING, - SS_DENY_SELF_AP_UNDER_SURVEY, - /*SS_DENY_SELF_STA_UNDER_WPS,*/ - SS_DENY_SELF_STA_UNDER_LINKING, - SS_DENY_SELF_STA_UNDER_SURVEY, - SS_DENY_BUDDY_UNDER_LINK_WPS, - SS_DENY_BUDDY_UNDER_SURVEY, - SS_DENY_BUSY_TRAFFIC, - SS_ALLOW, -#ifdef DBG_LA_MODE - SS_DENY_LA_MODE, #endif - SS_DENY_ADAPTIVITY, -}; - -u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval); -#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval) -#ifdef CONFIG_SET_SCAN_DENY_TIMER -bool rtw_is_scan_deny(_adapter *adapter); -void rtw_clear_scan_deny(_adapter *adapter); -void rtw_set_scan_deny_timer_hdl(void *ctx); -void rtw_set_scan_deny(_adapter *adapter, u32 ms); -#else -#define rtw_is_scan_deny(adapter) _FALSE -#define rtw_clear_scan_deny(adapter) do {} while (0) -#define rtw_set_scan_deny(adapter, ms) do {} while (0) -#endif void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); @@ -1099,16 +957,19 @@ u8 *rtw_get_beacon_interval_from_ie(u8 *ie); void rtw_joinbss_reset(_adapter *padapter); #ifdef CONFIG_80211N_HT +void rtw_ht_get_dft_setting(_adapter *padapter, + struct protocol_cap_t *dft_proto_cap, struct role_cap_t *dft_cap); void rtw_ht_use_default_setting(_adapter *padapter); void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len); -unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel); +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel, struct country_chplan *req_chplan); void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel); void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy); -void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); #endif +void rtw_append_extended_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); + int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); -int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature); +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst); #ifdef CONFIG_LAYER2_ROAMING #define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags) @@ -1156,6 +1017,8 @@ struct sta_media_status_rpt_cmd_parm { }; #ifdef CONFIG_RTW_MULTI_AP +void rtw_map_config_monitor_act_non(_adapter *adapter); +void rtw_map_config_monitor(_adapter *adapter, u8 self_act); void rtw_unassoc_sta_set_mode(_adapter *adapter, u8 stype, u8 mode); bool rtw_unassoc_sta_src_chk(_adapter *adapter, u8 stype); void dump_unassoc_sta(void *sel, _adapter *adapter); @@ -1235,4 +1098,19 @@ void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx); #define GET_TCP_ECE(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1) #define GET_TCP_CWR(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1) +#ifdef CONFIG_STA_CMD_DISPR +enum rtw_phl_status rtw_connect_cmd(struct _ADAPTER *a, + struct _WLAN_BSSID_EX *network); +void rtw_connect_abort(struct _ADAPTER *a); +int rtw_connect_abort_wait(struct _ADAPTER *a); +void rtw_connect_req_free(struct _ADAPTER *a); +void rtw_connect_req_init(struct _ADAPTER *a); +enum rtw_phl_status rtw_connect_disconnect_prepare(struct _ADAPTER *a); + +enum rtw_phl_status rtw_disconnect_cmd(struct _ADAPTER *a, + struct cmd_obj *pcmd); +int rtw_disconnect_abort_wait(struct _ADAPTER *a); +void rtw_disconnect_req_free(struct _ADAPTER *a); +void rtw_disconnect_req_init(struct _ADAPTER *a); +#endif /* CONFIG_STA_CMD_DISPR */ #endif /* __RTL871X_MLME_H_ */ diff --git a/include/rtw_mlme_ext.h b/include/rtw_mlme_ext.h index b574a1f..473c6e8 100644 --- a/include/rtw_mlme_ext.h +++ b/include/rtw_mlme_ext.h @@ -21,7 +21,7 @@ * The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. * So, this driver tried to extend the dwell time for each scanning channel. * This will increase the chance to receive the probe response from SoftAP. */ -#define SURVEY_TO (100) +#define SURVEY_TO (100) /*scan_ch_ms - ms*/ #define REAUTH_TO (300) /* (50) */ #define REASSOC_TO (300) /* (50) */ @@ -40,19 +40,19 @@ #define ROAMING_LIMIT 8 #endif -/*net_type, pmlmeinfo->state*/ -#define _HW_STATE_NOLINK_ 0x00 -#define _HW_STATE_ADHOC_ 0x01 -#define _HW_STATE_STATION_ 0x02 -#define _HW_STATE_AP_ 0x03 -#define _HW_STATE_MONITOR_ 0x04 +/*net_type, pmlmeinfo->state, pstat->state*/ +#define _HW_STATE_NOLINK_ 0x00 +#define _HW_STATE_ADHOC_ 0x01 +#define _HW_STATE_STATION_ 0x02 +#define _HW_STATE_AP_ 0x03 +#define _HW_STATE_MONITOR_ 0x04 #define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_ #define WIFI_FW_STATION_STATE _HW_STATE_STATION_ #define WIFI_FW_AP_STATE _HW_STATE_AP_ #define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ -#define WIFI_FW_PRE_LINK 0x00000800 +#define WIFI_FW_PRE_LINK 0x00000800 #define WIFI_FW_AUTH_NULL 0x00000100 #define WIFI_FW_AUTH_STATE 0x00000200 #define WIFI_FW_AUTH_SUCCESS 0x00000400 @@ -96,6 +96,17 @@ extern unsigned char MULTI_AP_OUI[]; extern unsigned char WMM_INFO_OUI[]; extern unsigned char WMM_PARA_OUI[]; +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) +extern int rtw_go_hidden_ssid_mode; +enum { + MIRACAST = 0, + PAIRING_MODE = 1, + CAPTIVE_PORTAL = 2, +}; +#define ALL_HIDE_SSID 0xff +#define MIRACAST_UNHIDE_SSID 0xfe +#endif + typedef struct _RT_CHANNEL_PLAN { unsigned char Channel[MAX_CHANNEL_NUM]; unsigned char Len; @@ -118,8 +129,8 @@ typedef enum _HT_IOT_PEER { HT_IOT_PEER_RTK_APCLIENT = 13, HT_IOT_PEER_REALTEK_81XX = 14, HT_IOT_PEER_REALTEK_WOW = 15, - HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, - HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + HT_IOT_PEER_REALTEK_JAGUAR_CBVAP = 16, + HT_IOT_PEER_REALTEK_JAGUAR_CCVAP = 17, HT_IOT_PEER_MAX = 18 } HT_IOT_PEER_E, *PHTIOT_PEER_E; @@ -137,8 +148,8 @@ typedef enum _RT_HT_INF0_CAP { typedef enum _RT_HT_INF1_CAP { RT_HT_CAP_USE_VIDEO_CLIENT = 0x01, - RT_HT_CAP_USE_JAGUAR_BCUT = 0x02, - RT_HT_CAP_USE_JAGUAR_CCUT = 0x04, + RT_HT_CAP_USE_JAGUAR_CBV = 0x02, + RT_HT_CAP_USE_JAGUAR_CCV = 0x04, } RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY; struct mlme_handler { @@ -153,84 +164,6 @@ struct action_handler { unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame); }; -enum SCAN_STATE { - SCAN_DISABLE = 0, - SCAN_START = 1, - SCAN_PS_ANNC_WAIT = 2, - SCAN_ENTER = 3, - SCAN_PROCESS = 4, - - /* backop */ - SCAN_BACKING_OP = 5, - SCAN_BACK_OP = 6, - SCAN_LEAVING_OP = 7, - SCAN_LEAVE_OP = 8, - - /* SW antenna diversity (before linked) */ - SCAN_SW_ANTDIV_BL = 9, - - /* legacy p2p */ - SCAN_TO_P2P_LISTEN = 10, - SCAN_P2P_LISTEN = 11, - - SCAN_COMPLETE = 12, - SCAN_STATE_MAX, -}; - -const char *scan_state_str(u8 state); - -enum ss_backop_flag { - SS_BACKOP_EN = BIT0, /* backop when linked */ - SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */ - - SS_BACKOP_PS_ANNC = BIT4, - SS_BACKOP_TX_RESUME = BIT5, -}; - -struct ss_res { - u8 state; - u8 next_state; /* will set to state on next cmd hdl */ - int bss_cnt; - u8 activate_ch_cnt; - int channel_idx; - u8 force_ssid_scan; - int scan_mode; - u16 scan_ch_ms; - u32 scan_timeout_ms; - u8 rx_ampdu_accept; - u8 rx_ampdu_size; - u8 igi_scan; - u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ -#ifdef CONFIG_SCAN_BACKOP - u8 backop_flags_sta; /* policy for station mode*/ - #ifdef CONFIG_AP_MODE - u8 backop_flags_ap; /* policy for ap mode */ - #endif - #ifdef CONFIG_RTW_MESH - u8 backop_flags_mesh; /* policy for mesh mode */ - #endif - u8 backop_flags; /* per backop runtime decision */ - u8 scan_cnt; - u8 scan_cnt_max; - systime backop_time; /* the start time of backop */ - u16 backop_ms; -#endif -#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) - u8 is_sw_antdiv_bl_scan; -#endif - u8 ssid_num; - u8 ch_num; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; - - u32 token; /* 0: use to identify caller */ - u16 duration; /* 0: use default */ - u8 igi; /* 0: use defalut */ - u8 bw; /* 0: use default */ - - bool acs; /* aim to trigger channel selection when scan done */ -}; - #ifdef CONFIG_TDLS enum TDLS_option { TDLS_ESTABLISHED = 1, @@ -274,9 +207,6 @@ enum TDLS_option { #if defined(CONFIG_ATMEL_RC_PATCH) #define RTW_SCAN_NUM_OF_CH 2 #define RTW_BACK_OP_CH_MS 200 -#elif defined(CONFIG_CUSTOMER_EZVIZ_CHIME2) - #define RTW_SCAN_NUM_OF_CH 1 - #define RTW_BACK_OP_CH_MS 200 #else #define RTW_SCAN_NUM_OF_CH 3 #define RTW_BACK_OP_CH_MS 400 @@ -287,9 +217,6 @@ enum TDLS_option { struct mlme_ext_info { u32 state; -#ifdef CONFIG_MI_WITH_MBSSID_CAM - u8 hw_media_state; -#endif u32 reauth_count; u32 reassoc_count; u32 link_count; @@ -301,7 +228,6 @@ struct mlme_ext_info { u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */ u32 iv; u8 chg_txt[128]; - u16 aid; u16 bcn_interval; u16 capability; u8 assoc_AP_vendor; @@ -314,8 +240,6 @@ struct mlme_ext_info { u8 HT_caps_enable; u8 HT_info_enable; u8 HT_protection; - u8 turboMode_cts2self; - u8 turboMode_rtsen; u8 SM_PS; u8 agg_enable_bitmap; u8 ADDBA_retry_count; @@ -327,6 +251,8 @@ struct mlme_ext_info { u8 hidden_ssid_mode; u8 VHT_enable; + u8 HE_enable; + u8 ip_addr[RTW_IP_ADDR_LEN]; u8 ip6_addr[RTW_IPv6_ADDR_LEN]; @@ -340,10 +266,6 @@ struct mlme_ext_info { NDIS_802_11_RATES_EX SupportedRates_infra_ap; u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */ #endif /* ROKU_PRIVATE */ - -#ifdef CONFIG_WRITE_BCN_LEN_TO_FW - u16 last_bcn_len; -#endif }; enum { @@ -359,7 +281,8 @@ enum { /* The channel information about this channel including joining, scanning, and power constraints. */ typedef struct _RT_CHANNEL_INFO { - u8 ChannelNum; /* The channel number. */ + u8 band; /* enum band_type */ + u8 ChannelNum; /* The channel number. */ /* * Bitmap and its usage: @@ -391,13 +314,18 @@ typedef struct _RT_CHANNEL_INFO { #define NON_OCP_TIME_MS (30*60*1000) #if CONFIG_TXPWR_LIMIT -void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl); +bool rtw_rfctl_is_current_txpwr_lmt(struct rf_ctl_t *rfctl, const char *name); #endif -int rtw_rfctl_init(_adapter *adapter); -void rtw_rfctl_deinit(_adapter *adapter); -void rtw_rfctl_chplan_init(_adapter *adapter); +int rtw_rfctl_init(struct dvobj_priv *dvobj); +void rtw_rfctl_deinit(struct dvobj_priv *dvobj); +void rtw_rfctl_decide_init_chplan(struct rf_ctl_t *rfctl, + const char *hw_alpha2, u8 hw_chplan, u8 hw_chplan_6g, u8 hw_force_chplan); +void rtw_rfctl_chplan_init(struct dvobj_priv *dvobj); +bool rtw_rfctl_is_disable_sw_channel_plan(struct dvobj_priv *dvobj); void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op); +bool rtw_rfctl_reg_allow_beacon_hint(struct rf_ctl_t *rfctl); + u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl); u8 rtw_rfctl_dfs_domain_unknown(struct rf_ctl_t *rfctl); @@ -429,25 +357,36 @@ bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw struct get_chplan_resp { enum regd_src_t regd_src; - bool has_country; - struct country_chplan country_ent; + enum rtw_regd_inr regd_inr; + char alpha2[2]; u8 channel_plan; +#if CONFIG_IEEE80211_BAND_6GHZ + u8 chplan_6g; +#endif + #if CONFIG_TXPWR_LIMIT - const char *regd_name; + const char *txpwr_lmt_name[BAND_MAX]; +#endif + u8 edcca_mode_2g; +#if CONFIG_IEEE80211_BAND_5GHZ + u8 edcca_mode_5g; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + u8 edcca_mode_6g; #endif #ifdef CONFIG_DFS_MASTER u8 dfs_domain; #endif + u8 proto_en; u8 chset_num; RT_CHANNEL_INFO chset[0]; }; -#ifdef CONFIG_PROC_DEBUG -void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num); +void dump_cur_country(void *sel, struct rf_ctl_t *rfctl); void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl); -#endif int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); +int rtw_chset_search_ch_by_band(RT_CHANNEL_INFO *ch_set, enum band_type band, const u32 ch); u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset , bool allow_primary_passive, bool allow_passive); void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset @@ -501,7 +440,6 @@ struct p2p_oper_class_map { struct mlme_ext_priv { _adapter *padapter; - u8 mlmeext_init; ATOMIC_T event_seq; u16 mgnt_seq; #ifdef CONFIG_IEEE80211W @@ -509,9 +447,7 @@ struct mlme_ext_priv { #endif /* struct fw_priv fwpriv; */ - unsigned char cur_channel; - unsigned char cur_bwmode; - unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ + struct rtw_chan_def chandef; unsigned char cur_wireless_mode; /* NETWORK_TYPE */ unsigned char basicrate[NumRates]; @@ -521,19 +457,11 @@ struct mlme_ext_priv { #endif struct ss_res sitesurvey_res; -#ifdef CONFIG_RTW_ROAM_QUICKSCAN - u8 quickscan_next; - u8 roam_ch_num; - struct rtw_ieee80211_channel roam_ch[RTW_CHANNEL_SCAN_AMOUNT]; -#endif struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info. * for ap mode, network includes ap's cap_info */ - _timer survey_timer; + /*_timer survey_timer;*/ _timer link_timer; -#ifdef CONFIG_RTW_REPEATER_SON - _timer rson_scan_timer; -#endif #ifdef CONFIG_RTW_80211R _timer ft_link_timer; _timer ft_roam_timer; @@ -541,10 +469,17 @@ struct mlme_ext_priv { #ifdef CONFIG_RTW_TOKEN_BASED_XMIT _timer tbtx_xmit_timer; _timer tbtx_token_dispatch_timer; +#endif +#ifdef ROKU_PRIVATE + _timer find_remote_timer; +#ifdef CONFIG_P2P + _timer hide_ssid_timer; +#endif #endif systime last_scan_time; - u8 scan_abort; + u8 scan_abort; + bool scan_abort_to; u8 join_abort; u8 tx_rate; /* TXRATE when USERATE is set. */ @@ -565,9 +500,6 @@ struct mlme_ext_priv { unsigned char bstart_bss; #endif -#ifdef CONFIG_80211D - u8 update_channel_plan_by_ap_done; -#endif /* recv_decache check for Action_public frame */ u8 action_public_dialog_token; u16 action_public_rxseq; @@ -579,11 +511,6 @@ struct mlme_ext_priv { u8 fixed_chan; #endif - u8 tsf_update_required:1; - u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */ - systime tsf_update_pause_stime; - u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */ - u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */ #ifdef CONFIG_SUPPORT_STATIC_SMPS u8 ssmps_en; u16 ssmps_tx_tp_th;/*Mbps*/ @@ -598,11 +525,11 @@ struct mlme_ext_priv { u16 txss_tp_th;/*Mbps*/ u8 txss_tp_chk_cnt;/*unit 2s*/ bool txss_1ss; - u8 txss_momi_type_bk; #endif -#ifdef CONFIG_DFS + u8 txss_bk; +#if CONFIG_DFS _timer csa_timer; -#endif /* CONFIG_DFS */ +#endif }; struct support_rate_handler { @@ -619,80 +546,7 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) return _FALSE; } -void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state); - #define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03) -#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) -#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state) -#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state)) -#define mlmeext_set_scan_state(mlmeext, _state) \ - do { \ - ((mlmeext)->sitesurvey_res.state = (_state)); \ - ((mlmeext)->sitesurvey_res.next_state = (_state)); \ - rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \ - /* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \ - sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \ - } while (0) - -#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) -#define mlmeext_set_scan_next_state(mlmeext, _state) \ - do { \ - ((mlmeext)->sitesurvey_res.next_state = (_state)); \ - /* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \ - } while (0) - -#ifdef CONFIG_SCAN_BACKOP -#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags) -#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags)) -#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \ - do { \ - ((mlmeext)->sitesurvey_res.backop_flags = (flags)); \ - RTW_INFO("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \ - } while (0) - -#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta) -#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags)) -#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \ - do { \ - ((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \ - } while (0) -#else -#define mlmeext_scan_backop_flags(mlmeext) (0) -#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0) -#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0) - -#define mlmeext_scan_backop_flags_sta(mlmeext) (0) -#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0) -#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0) -#endif /* CONFIG_SCAN_BACKOP */ - -#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) -#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap) -#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags)) -#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \ - do { \ - ((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \ - } while (0) -#else -#define mlmeext_scan_backop_flags_ap(mlmeext) (0) -#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) -#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) -#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */ - -#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) -#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh) -#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags)) -#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \ - do { \ - ((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \ - } while (0) -#else -#define mlmeext_scan_backop_flags_mesh(mlmeext) (0) -#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0) -#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0) -#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */ - -u32 rtw_scan_timeout_decision(_adapter *padapter); void init_mlme_default_rate_set(_adapter *padapter); int init_mlme_ext_priv(_adapter *padapter); @@ -701,57 +555,37 @@ void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext); extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); -/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */ -u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); void UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS); void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen); void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch); -void Set_MSR(_adapter *padapter, u8 type); - - void rtw_set_external_auth_status(_adapter *padapter, const void *data, int len); +void rtw_get_oper_chdef(_adapter *adapter, struct rtw_chan_def *chandef); +u8 rtw_get_oper_band(_adapter *adapter); u8 rtw_get_oper_ch(_adapter *adapter); -void rtw_set_oper_ch(_adapter *adapter, u8 ch); u8 rtw_get_oper_bw(_adapter *adapter); -void rtw_set_oper_bw(_adapter *adapter, u8 bw); u8 rtw_get_oper_choffset(_adapter *adapter); -void rtw_set_oper_choffset(_adapter *adapter, u8 offset); + systime rtw_get_on_oper_ch_time(_adapter *adapter); systime rtw_get_on_cur_ch_time(_adapter *adapter); -void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); +void set_channel_bwmode(_adapter *padapter, + unsigned char channel, + unsigned char channel_offset, + unsigned short bwmode, + u8 do_rfk); void csa_timer_hdl(void *FunctionContext); unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); -void _clear_cam_entry(_adapter *padapter, u8 entry); -void write_cam_from_cache(_adapter *adapter, u8 id); -void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b); -void rtw_clean_dk_section(_adapter *adapter); -void rtw_clean_hw_dk_cam(_adapter *adapter); - -/* modify both HW and cache */ -void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key); -void clear_cam_entry(_adapter *padapter, u8 id); - -/* modify cache only */ -void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); -void clear_cam_cache(_adapter *adapter, u8 id); +BOOLEAN IsLegal5GChannel(_adapter *adapter, u8 channel); -void invalidate_cam_all(_adapter *padapter); - -void flush_all_cam_entry(_adapter *padapter); - -BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel); - -void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType); u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); -void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie); +void rtw_update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie); u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork); u16 get_beacon_interval(WLAN_BSSID_EX *bss); @@ -795,10 +629,7 @@ void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); void VCS_update(_adapter *padapter, struct sta_info *psta); void update_ldpc_stbc_cap(struct sta_info *psta); -#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT bool rtw_validate_value(u16 EID, u8 *p, u16 len); -#endif /* CONFIG_CHECK_SPECIFIC_IE_CONTENT */ - bool is_hidden_ssid(char *ssid, int len); bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork); void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe); @@ -809,14 +640,17 @@ int rtw_update_bcn_keys_of_network(struct wlan_network *network); int validate_beacon_len(u8 *pframe, uint len); void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon); -void rtw_bcn_key_err_fix(struct beacon_keys *cur, struct beacon_keys *recv); bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv); -int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); +int rtw_check_bcn_info(_adapter *adapter, u8 *pframe, u32 packet_len); void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); #if CONFIG_DFS void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len); #endif -void update_capinfo(PADAPTER Adapter, u16 updateCap); +#ifdef CONFIG_80211D +bool rtw_iface_accept_country_ie(_adapter *adapter); +void process_country_ie(_adapter *adapter, u8 *ies, uint ies_len); +#endif +void update_capinfo(_adapter *adapter, u16 updateCap); void update_wireless_mode(_adapter *padapter); void update_tx_basic_rate(_adapter *padapter, u8 modulation); void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode); @@ -824,10 +658,14 @@ int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num /* for sta/adhoc mode */ void update_sta_info(_adapter *padapter, struct sta_info *psta); +void update_sta_ra_info(_adapter *padapter, struct sta_info *psta); + +s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta); +s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta); + + unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); -void Update_RA_Entry(_adapter *padapter, struct sta_info *psta); -void set_sta_rate(_adapter *padapter, struct sta_info *psta); unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated); @@ -835,6 +673,8 @@ unsigned char get_highest_rate_idx(u64 mask); unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit); #define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0) +u8 get_highest_bw_cap(u8 bwmode); + int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode); unsigned int is_ap_in_tkip(_adapter *padapter); unsigned int is_ap_in_wep(_adapter *padapter); @@ -842,59 +682,6 @@ unsigned int should_forbid_n_rate(_adapter *padapter); enum eap_type parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type); -bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap); -void _rtw_camctl_set_flags(_adapter *adapter, u32 flags); -void rtw_camctl_set_flags(_adapter *adapter, u32 flags); -void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags); -void rtw_camctl_clr_flags(_adapter *adapter, u32 flags); -bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags); - -struct sec_cam_bmp; -void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num); -void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id); -void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); - -bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); -bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); -s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used); -void rtw_camid_free(_adapter *adapter, u8 cam_id); -u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id); - -struct macid_bmp; -struct macid_ctl_t; -bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap); -void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num); -bool rtw_macid_is_set(struct macid_bmp *map, u8 id); -void rtw_macid_map_clr(struct macid_bmp *map, u8 id); -bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id); -bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id); -u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id); -bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id); -bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter); -s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id); -void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); -void rtw_release_macid(_adapter *padapter, struct sta_info *psta); -u8 rtw_search_max_mac_id(_adapter *padapter); -u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr); -void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw); -void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en); -void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); -void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); -#ifdef CONFIG_PROTSEL_MACSLEEP -void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info); -void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info); -#else -void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3); -void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3); -#endif -void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); -void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); -u8 rtw_iface_bcmc_id_get(_adapter *padapter); -void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id); -#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) -void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter); -#endif bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id); void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id); void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id); @@ -911,10 +698,9 @@ bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map); u32 report_join_res(_adapter *padapter, int aid_res, u16 status); void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); -void report_surveydone_event(_adapter *padapter, bool acs); +void report_surveydone_event(_adapter *padapter, bool acs, u8 flags); u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated); void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr); -bool rtw_port_switch_chk(_adapter *adapter); void report_wmm_edca_update(_adapter *padapter); void beacon_timing_control(_adapter *padapter); @@ -923,9 +709,6 @@ extern u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags); unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame); void update_mgnt_tx_rate(_adapter *padapter, u8 rate); void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib); -#ifdef CONFIG_RTW_MGMT_QUEUE -void update_mgntframe_subtype(_adapter *padapter, struct xmit_frame *pmgntframe); -#endif void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe); void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe); @@ -934,14 +717,8 @@ s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntfram s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); #ifdef CONFIG_P2P -int get_reg_classes_full_count(struct p2p_channels *channel_list); void issue_probersp_p2p(_adapter *padapter, unsigned char *da); -void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); -void issue_p2p_GO_request(_adapter *padapter, u8 *raddr); void issue_probereq_p2p(_adapter *padapter, u8 *da); -int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms); -void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success); -void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr); #endif /* CONFIG_P2P */ void issue_beacon(_adapter *padapter, int timeout_ms); void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); @@ -953,13 +730,17 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da); s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms); +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms, u8 need_om); int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms); +int issue_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid); -void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size); -u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms); +void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, + u8 size, struct ADDBA_request *paddba_req); +u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, + u16 status, u8 size, struct ADDBA_request *paddba_req, + int try_cnt, int wait_ms); void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator); int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); void issue_action_BSSCoexistPacket(_adapter *padapter); @@ -970,14 +751,16 @@ int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reaso #endif /* CONFIG_IEEE80211W */ int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode); int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms); +#ifdef ROKU_PRIVATE +int issue_action_find_remote(_adapter *padapter); +#endif unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr); -#ifdef CONFIG_AP_MODE unsigned int send_beacon(_adapter *padapter); -#endif + void start_clnt_assoc(_adapter *padapter); void start_clnt_auth(_adapter *padapter); void start_clnt_join(_adapter *padapter); @@ -1030,6 +813,8 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_he(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_protected_he(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_RTW_TOKEN_BASED_XMIT unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame); @@ -1040,7 +825,12 @@ void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat); void rtw_issue_action_token_rel(_adapter *padapter); #endif -void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); +#ifdef CONFIG_80211D +void rtw_joinbss_update_regulatory(_adapter *adapter, const WLAN_BSSID_EX *network); +#endif + +void rtw_mlmeext_disconnect(_adapter *padapter); +int rtw_set_hw_after_join(struct _ADAPTER *a, int join_res); void mlmeext_sta_del_event_callback(_adapter *padapter); void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); @@ -1054,10 +844,6 @@ void rtw_collect_bcn_info(_adapter *adapter); void _linked_info_dump(_adapter *padapter); -void survey_timer_hdl(void *ctx); -#ifdef CONFIG_RTW_REPEATER_SON -void rson_timer_hdl(void *ctx); -#endif void link_timer_hdl(void *ctx); void addba_timer_hdl(void *ctx); #ifdef CONFIG_RTW_TOKEN_BASED_XMIT @@ -1071,18 +857,30 @@ void sa_query_timer_hdl(void *ctx); void reauth_timer_hdl(_adapter *padapter); void reassoc_timer_hdl(_adapter *padapter); #endif - -#define set_survey_timer(mlmeext, ms) \ - do { \ - /*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ - _set_timer(&(mlmeext)->survey_timer, (ms)); \ - } while (0) +#ifdef ROKU_PRIVATE +void find_remote_timer_hdl(void *ctx); +#ifdef CONFIG_P2P +void hide_ssid_hdl(void *ctx); +#endif +#endif #define set_link_timer(mlmeext, ms) \ do { \ /*RTW_INFO("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ _set_timer(&(mlmeext)->link_timer, (ms)); \ } while (0) +#define cancel_link_timer(mlmeext) \ + do { \ + /*RTW_INFO("%s cancel_link_timer(%p)\n", __FUNCTION__, (mlmeext));*/ \ + _cancel_timer_ex(&(mlmeext)->link_timer); \ + } while (0) +#ifdef ROKU_PRIVATE +#define set_find_remote_timer(mlmeext, ms) \ + do { \ + /*RTW_INFO("%s set_find_remote_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->find_remote_timer, (ms)); \ + } while (0) +#endif bool rtw_is_cck_rate(u8 rate); bool rtw_is_ofdm_rate(u8 rate); @@ -1096,7 +894,7 @@ extern int cckratesonly_included(unsigned char *rate, int ratelen); extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); -extern void correct_TSF(_adapter *padapter, u8 mlme_state); + #ifdef CONFIG_BCN_RECV_TIME void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate); #endif @@ -1105,7 +903,7 @@ extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer); void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame); void rtw_join_done_chk_ch(_adapter *padapter, int join_res); -int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); +void survey_done_set_ch_bw(_adapter *padapter); #ifdef RTW_BUSY_DENY_SCAN #ifndef BUSY_TRAFFIC_SCAN_DENY_PERIOD @@ -1124,9 +922,15 @@ int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); void rtw_leave_opch(_adapter *adapter); void rtw_back_opch(_adapter *adapter); -u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); +#ifdef CONFIG_STA_CMD_DISPR +void update_join_info(struct _ADAPTER *a, struct _WLAN_BSSID_EX *pbuf); +int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); +#endif /* CONFIG_STA_CMD_DISPR */ + +u8 rtw_join_cmd_hdl(_adapter *padapter, u8 *pbuf); u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); u8 createbss_hdl(_adapter *padapter, u8 *pbuf); +void rtw_disconnect_ch_switch(_adapter *adapter); #ifdef CONFIG_AP_MODE u8 stop_ap_hdl(_adapter *adapter); #endif @@ -1134,14 +938,23 @@ u8 stop_ap_hdl(_adapter *adapter); u8 tx_control_hdl(_adapter *adapter); #endif u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); -u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); + u8 setauth_hdl(_adapter *padapter, u8 *pbuf); +#ifdef CONFIG_CMD_DISP +u8 setkey_hdl(struct _ADAPTER *a, struct setkey_parm *key, + enum phl_cmd_type cmd_type, u32 cmd_timeout); +u8 set_stakey_hdl(_adapter *padapter, struct set_stakey_parm *key, + enum phl_cmd_type cmd_type, u32 cmd_timeout); +#else +/* CONFIG_FSM */ u8 setkey_hdl(_adapter *padapter, u8 *pbuf); u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); +#endif u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf); +u8 delba_hdl(struct _ADAPTER *a, unsigned char *pbuf); void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta); @@ -1149,67 +962,84 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf); u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf); -u8 rtw_iqk_hdl(_adapter *padapter, unsigned char *pbuf); u8 rtw_set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); u8 rtw_get_chplan_hdl(_adapter *padapter, unsigned char *pbuf); u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf); -u8 rtw_write_bcnlen_hdl(_adapter *padapter, u8 *pbuf); + int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx); -u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi); +u16 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta); + +#ifdef CONFIG_RTW_MESH +extern u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf); +#else +static inline u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf) { return H2C_CMD_FAIL; }; +#endif /*CONFIG_RTW_MESH*/ + +#if defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) +#define IS_ACS_ENABLE(dvobj) (_FALSE) + +enum rtw_nhm_pid { + NHM_PID_IEEE_11K_HIGH, + NHM_PID_ACS, +}; +void rtw_acs_select_best_chan(_adapter *adapter); +void rtw_acs_trigger(_adapter *padapter, u32 scan_ms, u8 scan_ch, u8 pid); +void rtw_acs_get_rst(_adapter *adapter); +#endif /* defined(CONFIG_RTW_ACS) && defined(WKARD_ACS) */ #ifdef CONFIG_RTW_MULTI_AP u8 rtw_get_ch_utilization(_adapter *adapter); void rtw_ch_util_rpt(_adapter *adapter); #endif -#define GEN_MLME_EXT_HANDLER(cmd, callback_func) {.cmd_hdl = cmd, .callback = callback_func}, +#define GEN_MLME_EXT_HANDLER(name, cmd, callback) {name, cmd, callback}, struct rtw_cmd { + char name[32]; u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); void (*callback)(_adapter *padapter, struct cmd_obj *cmd); }; #ifdef _RTW_CMD_C_ -#ifdef CONFIG_RTW_MESH -extern u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf); -#else -u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf) { return H2C_CMD_FAIL; }; -#endif - struct rtw_cmd wlancmds[] = { - GEN_MLME_EXT_HANDLER(join_cmd_hdl, rtw_joinbss_cmd_callback) /*CMD_JOINBSS*/ - GEN_MLME_EXT_HANDLER(disconnect_hdl, rtw_disassoc_cmd_callback) /*CMD_DISCONNECT*/ - GEN_MLME_EXT_HANDLER(createbss_hdl, NULL) /*CMD_CREATE_BSS*/ - GEN_MLME_EXT_HANDLER(setopmode_hdl, NULL) /*CMD_SET_OPMODE*/ - GEN_MLME_EXT_HANDLER(sitesurvey_cmd_hdl, rtw_survey_cmd_callback) /*CMD_SITE_SURVEY*/ - GEN_MLME_EXT_HANDLER(setauth_hdl, NULL) /*CMD_SET_AUTH*/ - GEN_MLME_EXT_HANDLER(setkey_hdl, NULL) /*CMD_SET_KEY*/ - GEN_MLME_EXT_HANDLER(set_stakey_hdl, rtw_setstaKey_cmdrsp_callback) /*CMD_SET_STAKEY*/ - GEN_MLME_EXT_HANDLER(add_ba_hdl, NULL) /*CMD_ADD_BAREQ*/ - GEN_MLME_EXT_HANDLER(rtw_set_chbw_hdl, NULL) /*CMD_SET_CHANNEL*/ - GEN_MLME_EXT_HANDLER(tx_beacon_hdl, NULL) /*CMD_TX_BEACON*/ - GEN_MLME_EXT_HANDLER(mlme_evt_hdl, NULL) /*CMD_SET_MLME_EVT*/ - GEN_MLME_EXT_HANDLER(rtw_drvextra_cmd_hdl, NULL) /*CMD_SET_DRV_EXTRA*/ - GEN_MLME_EXT_HANDLER(rtw_set_chplan_hdl, NULL) /*CMD_SET_CHANPLAN*/ - GEN_MLME_EXT_HANDLER(led_blink_hdl, NULL) /*CMD_LEDBLINK*/ - GEN_MLME_EXT_HANDLER(set_csa_hdl, NULL) /*CMD_SET_CHANSWITCH*/ - GEN_MLME_EXT_HANDLER(tdls_hdl, NULL) /*CMD_TDLS*/ - GEN_MLME_EXT_HANDLER(chk_bmc_sleepq_hdl, NULL) /*CMD_CHK_BMCSLEEPQ*/ - GEN_MLME_EXT_HANDLER(run_in_thread_hdl, NULL) /*CMD_RUN_INTHREAD*/ - GEN_MLME_EXT_HANDLER(add_ba_rsp_hdl, NULL) /*CMD_ADD_BARSP*/ - GEN_MLME_EXT_HANDLER(rm_post_event_hdl, NULL) /*CMD_RM_POST_EVENT*/ - GEN_MLME_EXT_HANDLER(rtw_mesh_set_plink_state_cmd_hdl, NULL) /*CMD_SET_MESH_PLINK_STATE*/ - GEN_MLME_EXT_HANDLER(rtw_iqk_hdl, NULL) /*CMD_DO_IQK*/ - GEN_MLME_EXT_HANDLER(rtw_get_chplan_hdl, NULL) /* CMD_GET_CHANPLAN */ - GEN_MLME_EXT_HANDLER(rtw_write_bcnlen_hdl, NULL) /* CMD_WRITE_BCN_LEN */ -}; + GEN_MLME_EXT_HANDLER("CMD_JOINBSS", rtw_join_cmd_hdl, rtw_joinbss_cmd_callback) /*CMD_JOINBSS*/ + GEN_MLME_EXT_HANDLER("CMD_DISCONNECT", disconnect_hdl, rtw_disassoc_cmd_callback) /*CMD_DISCONNECT*/ + GEN_MLME_EXT_HANDLER("CMD_CREATE_BSS", createbss_hdl, NULL) /*CMD_CREATE_BSS*/ + GEN_MLME_EXT_HANDLER("CMD_SET_OPMODE", setopmode_hdl, NULL) /*CMD_SET_OPMODE*/ + #if 1 /*#ifndef CONFIG_PHL_ARCH*/ + GEN_MLME_EXT_HANDLER("CMD_SITE_SURVEY", sitesurvey_cmd_hdl, rtw_survey_cmd_callback) /*CMD_SITE_SURVEY*/ + #endif + GEN_MLME_EXT_HANDLER("CMD_SET_AUTH", setauth_hdl, NULL) /*CMD_SET_AUTH*/ +#ifndef CONFIG_CMD_DISP + GEN_MLME_EXT_HANDLER("CMD_SET_KEY", setkey_hdl, NULL) /*CMD_SET_KEY*/ + GEN_MLME_EXT_HANDLER("CMD_SET_STAKEY", set_stakey_hdl, rtw_setstaKey_cmdrsp_callback) /*CMD_SET_STAKEY*/ #endif + GEN_MLME_EXT_HANDLER("CMD_ADD_BAREQ", add_ba_hdl, NULL) /*CMD_ADD_BAREQ*/ + GEN_MLME_EXT_HANDLER("CMD_SET_CHANNEL", rtw_set_chbw_hdl, NULL) /*CMD_SET_CHANNEL*/ + GEN_MLME_EXT_HANDLER("CMD_TX_BEACON", tx_beacon_hdl, NULL) /*CMD_TX_BEACON*/ + GEN_MLME_EXT_HANDLER("CMD_SET_MLME_EVT", mlme_evt_hdl, NULL) /*CMD_SET_MLME_EVT*/ + GEN_MLME_EXT_HANDLER("CMD_SET_DRV_EXTRA", rtw_drvextra_cmd_hdl, NULL) /*CMD_SET_DRV_EXTRA*/ + GEN_MLME_EXT_HANDLER("CMD_SET_CHANPLAN", rtw_set_chplan_hdl, NULL) /*CMD_SET_CHANPLAN*/ + GEN_MLME_EXT_HANDLER("CMD_LEDBLINK", led_blink_hdl, NULL) /*CMD_LEDBLINK*/ + GEN_MLME_EXT_HANDLER("CMD_SET_CHANSWITCH", set_csa_hdl, NULL) /*CMD_SET_CHANSWITCH*/ + GEN_MLME_EXT_HANDLER("CMD_TDLS", tdls_hdl, NULL) /*CMD_TDLS*/ + GEN_MLME_EXT_HANDLER("CMD_CHK_BMCSLEEPQ", chk_bmc_sleepq_hdl, NULL) /*CMD_CHK_BMCSLEEPQ*/ + GEN_MLME_EXT_HANDLER("CMD_RUN_INTHREAD", run_in_thread_hdl, NULL) /*CMD_RUN_INTHREAD*/ + GEN_MLME_EXT_HANDLER("CMD_ADD_BARSP", add_ba_rsp_hdl, NULL) /*CMD_ADD_BARSP*/ + GEN_MLME_EXT_HANDLER("CMD_RM_POST_EVENT", rm_post_event_hdl, NULL) /*CMD_RM_POST_EVENT*/ + GEN_MLME_EXT_HANDLER("CMD_SET_MESH_PLINK_STATE", rtw_mesh_set_plink_state_cmd_hdl, NULL) /*CMD_SET_MESH_PLINK_STATE*/ + GEN_MLME_EXT_HANDLER("CMD_DELBA", delba_hdl, NULL) /*CMD_DELBA*/ + GEN_MLME_EXT_HANDLER("CMD_GET_CHANPLAN", rtw_get_chplan_hdl, NULL) /* CMD_GET_CHANPLAN */ +}; +#endif /*_RTW_CMD_C_*/ +char *rtw_cmd_name(struct cmd_obj *pcmd); +/*rtw_event*/ struct rtw_evt_header { u8 id; u8 seq; @@ -1231,20 +1061,28 @@ enum rtw_event_id { #endif EVT_ID_MAX }; + +struct rtw_event { + char name[32]; + u32 parmsize; + void (*event_callback)(_adapter *dev, u8 *pbuf); +}; #ifdef _RTW_MLME_EXT_C_ static struct rtw_event wlanevents[] = { - {sizeof(struct survey_event), &rtw_survey_event_callback}, /*EVT_SURVEY*/ - {sizeof(struct surveydone_event), &rtw_surveydone_event_callback}, /*EVT_SURVEY_DONE*/ - {sizeof(struct joinbss_event), &rtw_joinbss_event_callback}, /*EVT_JOINBSS*/ - {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, /*EVT_ADD_STA*/ - {sizeof(struct stadel_event), &rtw_stadel_event_callback}, /*EVT_DEL_STA*/ - {sizeof(struct wmm_event), &rtw_wmm_event_callback}, /*EVT_WMM_UPDATE*/ + {"EVT_SURVEY", sizeof(struct survey_event), &rtw_survey_event_callback}, /*EVT_SURVEY*/ + {"EVT_SURVEY_DONE", sizeof(struct surveydone_event), &rtw_surveydone_event_callback}, /*EVT_SURVEY_DONE*/ + {"EVT_JOINBSS", sizeof(struct joinbss_event), &rtw_joinbss_event_callback}, /*EVT_JOINBSS*/ + {"EVT_ADD_STA", sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, /*EVT_ADD_STA*/ + {"EVT_DEL_STA", sizeof(struct stadel_event), &rtw_stadel_event_callback}, /*EVT_DEL_STA*/ + {"EVT_WMM_UPDATE", sizeof(struct wmm_event), &rtw_wmm_event_callback}, /*EVT_WMM_UPDATE*/ #ifdef CONFIG_IEEE80211W - {sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, /*EVT_TIMEOUT_STA*/ + {"EVT_TIMEOUT_STA", sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, /*EVT_TIMEOUT_STA*/ #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R - {sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback}, /*EVT_FT_REASSOC*/ + {"EVT_FT_REASSOC", sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback}, /*EVT_FT_REASSOC*/ #endif }; -#endif/* _RTW_MLME_EXT_C_ */ +#endif/*_RTW_MLME_EXT_C_*/ +char *rtw_evt_name(struct rtw_evt_header *pev); + #endif diff --git a/include/rtw_mp.h b/include/rtw_mp.h index c2a6ca4..68427b0 100644 --- a/include/rtw_mp.h +++ b/include/rtw_mp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,18 +15,23 @@ #ifndef _RTW_MP_H_ #define _RTW_MP_H_ +#include + #define RTWPRIV_VER_INFO 1 #define MAX_MP_XMITBUF_SZ 2048 #define NR_MP_XMITFRAME 8 #define MP_READ_REG_MAX_OFFSET 0x4FFF +#define TX_POWER_BASE 4 /* dbm * 4 */ +#define TX_POWER_CODE_WORD_BASE 8 /* dbm * 8 */ + struct mp_xmit_frame { _list list; struct pkt_attrib attrib; - _pkt *pkt; + struct sk_buff *pkt; int frame_tag; @@ -115,8 +120,13 @@ typedef struct _RT_PMAC_TX_INFO { u8 MacAddress[6]; } RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO; +struct rtw_mp_giltf_data { + u8 gi; + u8 ltf; + char type_str[8]; +}; -typedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter); +typedef void (*MPT_WORK_ITEM_HANDLER)(void *adapter); typedef struct _MPT_CONTEXT { /* Indicate if we have started Mass Production Test. */ BOOLEAN bMassProdTest; @@ -159,8 +169,6 @@ typedef struct _MPT_CONTEXT { u32 mpt_rf_path; - - WIRELESS_MODE MptWirelessModeToSw; /* Wireless mode to switch. */ u8 MptChannelToSw; /* Channel to switch. */ u8 MptInitGainToSet; /* Initial gain to set. */ /* u32 bMptAntennaA; */ /* TRUE if we want to use antenna A. */ @@ -247,7 +255,7 @@ enum { MP_STOP, MP_RATE, MP_CHANNEL, - MP_CHL_OFFSET, + MP_TRXSC_OFFSET, MP_BANDWIDTH, MP_TXPOWER, MP_ANT_TX, @@ -285,25 +293,34 @@ enum { MP_PWRLMT, MP_PWRBYRATE, BT_EFUSE_FILE, - MP_SetBT, MP_SWRFPath, MP_LINK, MP_DPK_TRK, MP_DPK, MP_GET_TSSIDE, MP_SET_TSSIDE, + MP_GET_PHL_TEST, + MP_SET_PHL_TEST, + MP_SET_PHL_TX_PATTERN, + MP_SET_PHL_PLCP_TX_DATA, + MP_SET_PHL_PLCP_TX_USER, + MP_SET_PHL_TX_METHOD, + MP_SET_PHL_CONIFG_PHY_NUM, + MP_PHL_RFK, + MP_PHL_BTC_PATH, + MP_GET_HE, MP_NULL, #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE VENDOR_IE_SET , VENDOR_IE_GET , #endif +#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE) + PHL_TEST_SET, + PHL_TEST_GET, +#endif #ifdef CONFIG_WOWLAN MP_WOW_ENABLE, MP_WOW_SET_PATTERN, -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - MP_WOW_SET_KEEP_ALIVE_PATTERN, -#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - #endif #ifdef CONFIG_AP_WOWLAN MP_AP_WOW_ENABLE, @@ -312,6 +329,19 @@ enum { MP_SD_IWRITE, }; +struct rtw_plcp_user { + u8 plcp_usr_idx; + u16 plcp_mcs; + u8 coding; + u8 dcm; + u8 aid; + u32 plcp_txlen; /*apep*/ + u32 ru_alloc; + u8 plcp_nss; + u8 txbf; + u8 pwr_boost_db; +}; + struct mp_priv { _adapter *papdater; @@ -346,14 +376,21 @@ struct mp_priv { u8 bandwidth; u8 prime_channel_offset; u8 txpoweridx; - u8 rateidx; + s16 txpowerdbm; + u16 rateidx; + s16 pre_refcw_cck_pwridxa; + s16 pre_refcw_cck_pwridxb; + s16 pre_refcw_ofdm_pwridxa; + s16 pre_refcw_ofdm_pwridxb; + u32 preamble; /* u8 modem; */ u32 CrystalCap; /* u32 curr_crystalcap; */ - u16 antenna_tx; - u16 antenna_rx; + u8 antenna_tx; + u8 antenna_rx; + u8 antenna_trx; /* u8 curr_rfpath; */ u8 check_mp_pkt; @@ -366,6 +403,7 @@ struct mp_priv { /* RF PATH Setting for WLG WLA BTG BT */ u8 rf_path_cfg; + u8 btc_path; /* BTC_MODE_NORMAL, BTC_MODE_WL,BTC_MODE_BT */ struct wlan_network mp_network; NDIS_802_11_MAC_ADDRESS network_macaddr; @@ -385,17 +423,57 @@ struct mp_priv { MPT_CONTEXT mpt_ctx; u8 *TXradomBuffer; - u8 CureFuseBTCoex; - u8 mplink_buf[2048]; - u32 mplink_rx_len; + u8 mp_keep_btc_mode; + u8 mplink_buf[2048]; + u32 mplink_rx_len; BOOLEAN mplink_brx; BOOLEAN mplink_btx; bool tssitrk_on; - bool efuse_update_file; - char efuse_file_path[128]; + u8 rtw_mp_cur_phy; + u8 rtw_mp_dbcc; + s16 path_pwr_offset[4]; /* rf-A, rf-B*/ + u8 rtw_mp_tx_method; + u8 rtw_mp_pmact_patt_idx; + u8 rtw_mp_pmact_ppdu_type; + u8 rtw_mp_data_bandwidth; + u8 rtw_mp_stbc; + u8 rtw_mp_plcp_gi; + u8 rtw_mp_plcp_ltf; + u8 rtw_mp_he_sigb; + u8 rtw_mp_he_sigb_dcm; + u32 rtw_mp_plcp_tx_time; + u8 rtw_mp_plcp_tx_mode; + + u8 rtw_mp_he_er_su_ru_106_en; + u8 rtw_mp_trxsc; + u16 rtw_mp_plcp_rualloc; + u8 rtw_mp_plcp_tx_user; + u32 rtw_mp_ru_tone; + u8 ru_tone_sel_list[6]; + u8 ru_alloc_list[68]; + + struct rtw_mp_giltf_data st_giltf[5]; + struct rtw_plcp_user mp_plcp_user[4]; + u8 mp_plcp_useridx; + + u8 keep_ips_status; + u8 keep_lps_status; }; +#define PPDU_TYPE_STR(idx)\ + (idx == RTW_MP_TYPE_CCK) ? "CCK" :\ + (idx == RTW_MP_TYPE_LEGACY) ? "LEGACY" :\ + (idx == RTW_MP_TYPE_HT_MF) ? "HT_MF" :\ + (idx == RTW_MP_TYPE_HT_GF) ? "HT_GF" :\ + (idx == RTW_MP_TYPE_VHT) ? "VHT" :\ + (idx == RTW_MP_TYPE_HE_SU) ? "HE_SU" :\ + (idx == RTW_MP_TYPE_HE_ER_SU) ? "HE_ER_SU" :\ + (idx == RTW_MP_TYPE_HE_MU_OFDMA) ? "HE_MU" :\ + (idx == RTW_MP_TYPE_HE_TB) ? "HE_TB" :\ + "UNknow" + + typedef struct _IOCMD_STRUCT_ { u8 cmdclass; u16 value; @@ -413,19 +491,6 @@ struct bb_reg_param { u32 value; }; -typedef struct _MP_FIRMWARE { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[0x8000]; -#endif - u32 ulFwLength; -} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE; - - - - /* *********************************************************************** */ #define LOWER _TRUE @@ -456,6 +521,7 @@ typedef struct _MP_FIRMWARE { #define _2MAC_MODE_ 0 #define _LOOPBOOK_MODE_ 1 #endif + typedef enum _MP_MODE_ { MP_OFF, MP_ON, @@ -477,7 +543,6 @@ typedef enum _TEST_MODE { CCK_Carrier_Suppression_TX } TEST_MODE; - typedef enum _MPT_BANDWIDTH { MPT_BW_20MHZ = 0, MPT_BW_40MHZ_DUPLICATE = 1, @@ -669,84 +734,832 @@ typedef enum _mp_tx_pkt_payload{ extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); #endif +enum rtw_mp_tx_method { + RTW_MP_SW_TX = 0, + RTW_MP_PMACT_TX, + RTW_MP_TMACT_TX, + RTW_MP_FW_PMACT_TX, +}; + +enum rtw_mp_tx_cmd { + RTW_MP_TX_NONE = 0, + RTW_MP_TX_PACKETS, + RTW_MP_TX_CONTINUOUS, + RTW_MP_TX_SINGLE_TONE, + RTW_MP_TX_CCK_Carrier_Suppression, + RTW_MP_TX_CONFIG_PLCP_COMMON_INFO, + RTW_MP_TX_CMD_PHY_OK, + RTW_MP_TX_CONFIG_PLCP_PATTERN, + RTW_MP_TX_CONFIG_PLCP_USER_INFO, + RTW_MP_TX_MODE_SWITCH, + RTW_MP_TX_F2P, + RTW_MP_TX_TB_TEST, + RTW_MP_TX_DPD_BYPASS, + RTW_MP_TX_CHECK_TX_IDLE, + RTW_MP_TX_CMD_MAX, +}; + +enum rtw_mp_pmac_mode { + RTW_MP_PMAC_NONE_TEST, + RTW_MP_PMAC_PKTS_TX, + RTW_MP_PMAC_PKTS_RX, + RTW_MP_PMAC_CONT_TX, + RTW_MP_PMAC_FW_TRIG_TX, + RTW_MP_PMAC_OFDM_SINGLE_TONE_TX, + RTW_MP_PMAC_CCK_CARRIER_SIPPRESSION_TX +}; + +enum rtw_mp_ppdu_type { + RTW_MP_TYPE_CCK = 0, + RTW_MP_TYPE_LEGACY, + RTW_MP_TYPE_HT_MF, + RTW_MP_TYPE_HT_GF, + RTW_MP_TYPE_VHT, + RTW_MP_TYPE_HE_SU, + RTW_MP_TYPE_HE_ER_SU, + RTW_MP_TYPE_HE_MU_OFDMA, + RTW_MP_TYPE_HE_TB +}; + +/* mp command class */ +enum rtw_mp_class { + RTW_MP_CLASS_CONFIG = 0, + RTW_MP_CLASS_TX = 1, + RTW_MP_CLASS_RX = 2, + RTW_MP_CLASS_EFUSE = 3, + RTW_MP_CLASS_REG = 4, + RTW_MP_CLASS_TXPWR = 5, + RTW_MP_CLASS_CAL = 6, + RTW_MP_CLASS_FLASH = 7, + RTW_MP_CLASS_MAX, +}; + +/* mp rx command */ +enum rtw_mp_rx_cmd { + RTW_MP_RX_CMD_PHY_CRC_OK = 0, + RTW_MP_RX_CMD_PHY_CRC_ERR = 1, + RTW_MP_RX_CMD_MAC_CRC_OK = 2, + RTW_MP_RX_CMD_MAC_CRC_ERR = 3, + RTW_MP_RX_CMD_DRV_CRC_OK = 4, + RTW_MP_RX_CMD_DRV_CRC_ERR = 5, + RTW_MP_RX_CMD_GET_RSSI = 6, + RTW_MP_RX_CMD_GET_RXEVM = 7, + RTW_MP_RX_CMD_GET_PHYSTS = 8, + RTW_MP_RX_CMD_TRIGGER_RXEVM = 9, + RTW_MP_RX_CMD_SET_GAIN_OFFSET = 10, + RTW_MP_RX_CMD_MAX, + +}; + +/* mp config command */ +enum rtw_mp_config_cmdid { + RTW_MP_CONFIG_CMD_GET_BW, + RTW_MP_CONFIG_CMD_GET_RF_STATUS, + RTW_MP_CONFIG_CMD_SET_RATE_IDX, + RTW_MP_CONFIG_CMD_SET_RF_TXRX_PATH, + RTW_MP_CONFIG_CMD_SET_RESET_PHY_COUNT, + RTW_MP_CONFIG_CMD_SET_RESET_MAC_COUNT, + RTW_MP_CONFIG_CMD_SET_RESET_DRV_COUNT, + RTW_MP_CONFIG_CMD_PBC, + RTW_MP_CONFIG_CMD_START_DUT, + RTW_MP_CONFIG_CMD_STOP_DUT, + RTW_MP_CONFIG_CMD_GET_MIMPO_RSSI, + RTW_MP_CONFIG_CMD_GET_BOARD_TYPE, + RTW_MP_CONFIG_CMD_GET_MODULATION, + RTW_MP_CONFIG_CMD_GET_RF_MODE, + RTW_MP_CONFIG_CMD_GET_RF_PATH, + RTW_MP_CONFIG_CMD_SET_MODULATION, + RTW_MP_CONFIG_CMD_GET_DEVICE_INFO, + RTW_MP_CONFIG_CMD_SET_PHY_INDEX, + RTW_MP_CONFIG_CMD_GET_MAC_ADDR, + RTW_MP_CONFIG_CMD_SET_MAC_ADDR, + RTW_MP_CONFIG_CMD_SET_CH_BW, + RTW_MP_CONFIG_CMD_GET_TX_NSS, + RTW_MP_CONFIG_CMD_GET_RX_NSS, + RTW_MP_CONFIG_CMD_SWITCH_BT_PATH, + RTW_MP_CONFIG_CMD_GET_RFE_TYPE, + RTW_MP_CONFIG_CMD_GET_DEV_IDX, + RTW_MP_CONFIG_CMD_TRIGGER_FW_CONFLICT, + RTW_MP_CONFIG_CMD_MAX, +}; + +typedef enum _mp_ant_path { + MP_ANTENNA_NONE = 0, + MP_ANTENNA_D = 1, + MP_ANTENNA_C = 2, + MP_ANTENNA_CD = 3, + MP_ANTENNA_B = 4, + MP_ANTENNA_BD = 5, + MP_ANTENNA_BC = 6, + MP_ANTENNA_BCD = 7, + MP_ANTENNA_A = 8, + MP_ANTENNA_AD = 9, + MP_ANTENNA_AC = 10, + MP_ANTENNA_ACD = 11, + MP_ANTENNA_AB = 12, + MP_ANTENNA_ABD = 13, + MP_ANTENNA_ABC = 14, + MP_ANTENNA_ABCD = 15 +} mp_ant_path; + +#define RTW_MP_TEST_NAME_LEN 32 +#define RTW_MP_TEST_RPT_RSN_LEN 32 + +struct rtw_mp_test_rpt { + char name[RTW_MP_TEST_NAME_LEN]; + u8 status; + char rsn[RTW_MP_TEST_RPT_RSN_LEN]; + u32 total_time; // in ms +}; + +struct rtw_mp_cmd_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; +}; + +struct rtw_mp_config_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u8 channel; + u8 bandwidth; + u8 rate_idx; + u8 ant_tx; + u8 ant_rx; + u8 rf_path; + u8 get_rfstats; + u8 modulation; + u8 bustype; + u32 chipid; + u8 cur_phy; + u8 mac_addr[6]; + u8 sc_idx; + u8 dbcc_en; + u8 btc_mode; + u8 rfe_type; + u8 dev_id; + u32 offset; + u8 voltag; +}; + +struct rtw_mp_tx_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u8 tx_method; + u8 plcp_ppdu_type; /*offline gen*/ + u16 plcp_case_id; /*offline gen*/ + u8 bCarrierSuppression; + u8 is_cck; + u8 start_tx; + u16 tx_cnt; + u16 period; /* us */ + u16 tx_time; /* us */ + u32 tx_ok; + u8 tx_path; + u8 tx_mode; /* mode: 0 = tmac, 1 = pmac */ + u8 tx_concurrent_en; /* concurrent tx */ + u8 dpd_bypass; + /* plcp info */ + u32 dbw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/ + u32 source_gen_mode; + u32 locked_clk; + u32 dyn_bw; + u32 ndp_en; + u32 long_preamble_en; /*bmode*/ + u32 stbc; + u32 gi; /*0:0.4,1:0.8,2:1.6,3:3.2*/ + u32 tb_l_len; + u32 tb_ru_tot_sts_max; + u32 vht_txop_not_allowed; + u32 tb_disam; + u32 doppler; + u32 he_ltf_type; /*0:1x,1:2x,2:4x*/ + u32 ht_l_len; + u32 preamble_puncture; + u32 he_mcs_sigb;/*0~5*/ + u32 he_dcm_sigb; + u32 he_sigb_compress_en; + u32 max_tx_time_0p4us; + u32 ul_flag; + u32 tb_ldpc_extra; + u32 bss_color; + u32 sr; + u32 beamchange_en; + u32 he_er_u106ru_en; + u32 ul_srp1; + u32 ul_srp2; + u32 ul_srp3; + u32 ul_srp4; + u32 mode; + u32 group_id; + u32 ppdu_type;/*0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB*/ + u32 txop; + u32 tb_strt_sts; + u32 tb_pre_fec_padding_factor; + u32 cbw; + u32 txsc; + u32 tb_mumimo_mode_en; + u32 nominal_t_pe; /* def = 2*/ + u32 ness; /* def = 0*/ + u32 n_user; + u32 tb_rsvd;/*def = 0*/ + /* plcp user info */ + u32 plcp_usr_idx; + u32 mcs; + u32 mpdu_len; + u32 n_mpdu; + u32 fec; + u32 dcm; + u32 aid; + u32 scrambler_seed; /* rand (1~255)*/ + u32 random_init_seed; /* rand (1~255)*/ + u32 apep; + u32 ru_alloc; + u32 nss; + u32 txbf; + u32 pwr_boost_db; + //struct mp_plcp_param_t plcp_param; /*online gen*/ + u32 data_rate; + u8 plcp_sts; + + /*HE-TB Test*/ + u8 bSS_id_addr0; + u8 bSS_id_addr1; + u8 bSS_id_addr2; + u8 bSS_id_addr3; + u8 bSS_id_addr4; + u8 bSS_id_addr5; + u8 is_link_mode; + + /* f2p cmd */ + u32 pref_AC_0; + u32 aid12_0; + u32 ul_mcs_0; + u32 macid_0; + u32 ru_pos_0; + u32 ul_fec_code_0; + u32 ul_dcm_0; + u32 ss_alloc_0; + u32 ul_tgt_rssi_0; + u32 pref_AC_1; + u32 aid12_1; + u32 ul_mcs_1; + u32 macid_1; + u32 ru_pos_1; + u32 ul_fec_code_1; + u32 ul_dcm_1; + u32 ss_alloc_1; + u32 ul_tgt_rssi_1; + u32 pref_AC_2; + u32 aid12_2; + u32 ul_mcs_2; + u32 macid_2; + u32 ru_pos_2; + u32 ul_fec_code_2; + u32 ul_dcm_2; + u32 ss_alloc_2; + u32 ul_tgt_rssi_2; + u32 pref_AC_3; + u32 aid12_3; + u32 ul_mcs_3; + u32 macid_3; + u32 ru_pos_3; + u32 ul_fec_code_3; + u32 ul_dcm_3; + u32 ss_alloc_3; + u32 ul_tgt_rssi_3; + u32 ul_bw; + u32 gi_ltf; + u32 num_he_ltf; + u32 ul_stbc; + u32 pkt_doppler; + u32 ap_tx_power; + u32 user_num; + u32 pktnum; + u32 pri20_bitmap; + u32 datarate; + u32 mulport_id; + u32 pwr_ofset; + u32 f2p_mode; + u32 frexch_type; + u32 sigb_len; + /* dword 0 */ + u32 cmd_qsel; + u32 ls; + u32 fs; + u32 total_number; + u32 seq; + u32 length; + /* dword 1 */ + /* dword 0 */ + u32 cmd_type; + u32 cmd_sub_type; + u32 dl_user_num; + u32 bw; + u32 tx_power; + /* dword 1 */ + u32 fw_define; + u32 ss_sel_mode; + u32 next_qsel; + u32 twt_group; + u32 dis_chk_slp; + u32 ru_mu_2_su; + u32 dl_t_pe; + /* dword 2 */ + u32 sigb_ch1_len; + u32 sigb_ch2_len; + u32 sigb_sym_num; + u32 sigb_ch2_ofs; + u32 dis_htp_ack; + u32 tx_time_ref; + u32 pri_user_idx; + /* dword 3 */ + u32 ampdu_max_txtime; + u32 d3_group_id; + u32 twt_chk_en; + u32 twt_port_id; + /* dword 4 */ + u32 twt_start_time; + /* dword 5 */ + u32 twt_end_time; + /* dword 6 */ + u32 apep_len; + u32 tri_pad; + u32 ul_t_pe; + u32 rf_gain_idx; + u32 fixed_gain_en; + u32 ul_gi_ltf; + u32 ul_doppler; + u32 d6_ul_stbc; + /* dword 7 */ + u32 ul_mid_per; + u32 ul_cqi_rrp_tri; + u32 sigb_dcm; + u32 sigb_comp; + u32 d7_doppler; + u32 d7_stbc; + u32 mid_per; + u32 gi_ltf_size; + u32 sigb_mcs; + /* dword 8 */ + u32 macid_u0; + u32 ac_type_u0; + u32 mu_sta_pos_u0; + u32 dl_rate_idx_u0; + u32 dl_dcm_en_u0; + u32 ru_alo_idx_u0; + /* dword 9 */ + u32 pwr_boost_u0; + u32 agg_bmp_alo_u0; + u32 ampdu_max_txnum_u0; + u32 user_define_u0; + u32 user_define_ext_u0; + /* dword 10 */ + u32 ul_addr_idx_u0; + u32 ul_dcm_u0; + u32 ul_fec_cod_u0; + u32 ul_ru_rate_u0; + u32 ul_ru_alo_idx_u0; + /* dword 11 */ + /* dword 12 */ + u32 macid_u1; + u32 ac_type_u1; + u32 mu_sta_pos_u1; + u32 dl_rate_idx_u1; + u32 dl_dcm_en_u1; + u32 ru_alo_idx_u1; + /* dword 13 */ + u32 pwr_boost_u1; + u32 agg_bmp_alo_u1; + u32 ampdu_max_txnum_u1; + u32 user_define_u1; + u32 user_define_ext_u1; + /* dword 14 */ + u32 ul_addr_idx_u1; + u32 ul_dcm_u1; + u32 ul_fec_cod_u1; + u32 ul_ru_rate_u1; + u32 ul_ru_alo_idx_u1; + /* dword 15 */ + /* dword 16 */ + u32 macid_u2; + u32 ac_type_u2; + u32 mu_sta_pos_u2; + u32 dl_rate_idx_u2; + u32 dl_dcm_en_u2; + u32 ru_alo_idx_u2; + /* dword 17 */ + u32 pwr_boost_u2; + u32 agg_bmp_alo_u2; + u32 ampdu_max_txnum_u2; + u32 user_define_u2; + u32 user_define_ext_u2; + /* dword 18 */ + u32 ul_addr_idx_u2; + u32 ul_dcm_u2; + u32 ul_fec_cod_u2; + u32 ul_ru_rate_u2; + u32 ul_ru_alo_idx_u2; + /* dword 19 */ + /* dword 20 */ + u32 macid_u3; + u32 ac_type_u3; + u32 mu_sta_pos_u3; + u32 dl_rate_idx_u3; + u32 dl_dcm_en_u3; + u32 ru_alo_idx_u3; + /* dword 21 */ + u32 pwr_boost_u3; + u32 agg_bmp_alo_u3; + u32 ampdu_max_txnum_u3; + u32 user_define_u3; + u32 user_define_ext_u3; + /* dword 22 */ + u32 ul_addr_idx_u3; + u32 ul_dcm_u3; + u32 ul_fec_cod_u3; + u32 ul_ru_rate_u3; + u32 ul_ru_alo_idx_u3; + /* dword 23 */ + /* dword 24 */ + u32 pkt_id_0; + u32 valid_0; + u32 ul_user_num_0; + /* dword 25 */ + u32 pkt_id_1; + u32 valid_1; + u32 ul_user_num_1; + /* dword 26 */ + u32 pkt_id_2; + u32 valid_2; + u32 ul_user_num_2; + /* dword 27 */ + u32 pkt_id_3; + u32 valid_3; + u32 ul_user_num_3; + /* dword 28 */ + u32 pkt_id_4; + u32 valid_4; + u32 ul_user_num_4; + /* dword 29 */ + u32 pkt_id_5; + u32 valid_5; + u32 ul_user_num_5; + /* tx state*/ + u8 tx_state; +}; + + +struct rtw_mp_rx_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u32 rx_ok; + u32 rx_err; + u8 rssi; + u8 rx_path; + u8 rx_evm; + u8 user; + u8 strm; + u8 rxevm_table; + u8 enable; + u32 phy0_user0_rxevm; + u32 phy0_user1_rxevm; + u32 phy0_user2_rxevm; + u32 phy0_user3_rxevm; + u32 phy1_user0_rxevm; + u32 phy1_user1_rxevm; + u32 phy1_user2_rxevm; + u32 phy1_user3_rxevm; + s8 offset; + u8 rf_path; + u8 iscck; + s16 rssi_ex; +}; + +/* mp tx power command */ +enum rtw_mp_txpwr_cmd { + RTW_MP_TXPWR_CMD_READ_PWR_TABLE = 0, + RTW_MP_TXPWR_CMD_GET_PWR_TRACK_STATUS = 1, + RTW_MP_TXPWR_CMD_SET_PWR_TRACK_STATUS = 2, + RTW_MP_TXPWR_CMD_SET_TXPWR = 3, + RTW_MP_TXPWR_CMD_GET_TXPWR = 4, + RTW_MP_TXPWR_CMD_GET_TXPWR_INDEX = 5, + RTW_MP_TXPWR_CMD_GET_THERMAL = 6, + RTW_MP_TXPWR_CMD_GET_TSSI = 7, + RTW_MP_TXPWR_CMD_SET_TSSI = 8, + RTW_MP_TXPWR_CMD_GET_TXPWR_REF = 9, + RTW_MP_TXPWR_CMD_GET_TXPWR_REF_CW = 10, + RTW_MP_TXPWR_CMD_SET_TXPWR_INDEX = 11, + RTW_MP_TXPWR_CMD_GET_TXINFOPWR = 12, + RTW_MP_TXPWR_CMD_SET_RFMODE = 13, + RTW_MP_TXPWR_CMD_SET_TSSI_OFFSET = 14, + RTW_MP_TXPWR_CMD_GET_ONLINE_TSSI_DE = 15, + RTW_MP_TXPWR_CMD_SET_PWR_LMT_EN = 16, + RTW_MP_TXPWR_CMD_GET_PWR_LMT_EN = 17, + RTW_MP_TXPWR_CMD_MAX, +}; + +enum rtw_mp_tssi_pwrtrk_type{ + RTW_MP_TSSI_OFF = 0, + RTW_MP_TSSI_ON, + RTW_MP_TSSI_CAL +}; + +struct rtw_mp_txpwr_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + s16 txpwr; + u16 txpwr_index; + u8 txpwr_track_status; + u8 txpwr_status; + u32 tssi; + u8 thermal; + u8 rfpath; + u8 ofdm; + u8 tx_path; + u16 rate; + u8 bandwidth; + u8 channel; + s16 table_item; /*get an element of power table*/ + u8 dcm; + u8 beamforming; + u8 offset; + s16 txpwr_ref; + u8 is_cck; + u8 rf_mode; + u32 tssi_de_offset; + s32 dbm; + s32 pout; + s32 online_tssi_de; + bool pwr_lmt_en; + u8 sharp_id; +}; + +/* mp reg command */ +enum rtw_mp_reg_cmd { + RTW_MP_REG_CMD_READ_MAC = 0, + RTW_MP_REG_CMD_WRITE_MAC = 1, + RTW_MP_REG_CMD_READ_RF = 2, + RTW_MP_REG_CMD_WRITE_RF = 3, + RTW_MP_REG_CMD_READ_SYN = 4, + RTW_MP_REG_CMD_WRITE_SYN = 5, + RTW_MP_REG_CMD_READ_BB = 6, + RTW_MP_REG_CMD_WRITE_BB = 7, + RTW_MP_REG_CMD_SET_XCAP = 8, + RTW_MP_REG_CMD_GET_XCAP = 9, + RTW_MP_REG_CMD_MAX, +}; -extern s32 init_mp_priv(PADAPTER padapter); +struct rtw_mp_reg_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u32 io_offset; + u32 io_value; + u8 io_type; + u8 ofdm; + u8 rfpath; + u8 sc_xo; + u8 xsi_offset; + u8 xsi_value; +}; + +struct rtw_mp_cal_arg { + u8 mp_class; + u8 cmd; + u8 cmd_ok; + u8 status; + u8 cal_type; + u8 enable; + u8 rfpath; + u16 io_value; + u8 channel; + u8 bandwidth; + s32 xdbm; + u8 path; + u8 iq_path; + u32 avg; + u32 fft; + s32 point; + u32 upoint; + u32 start_point; + u32 stop_point; + u32 buf; + u32 outbuf[450]; +}; + +enum rtw_mp_cal_cmd { + RTW_MP_CAL_CMD_TRIGGER_CAL = 0, + RTW_MP_CAL_CMD_SET_CAPABILITY_CAL = 1, + RTW_MP_CAL_CMD_GET_CAPABILITY_CAL = 2, + RTW_MP_CAL_CMD_GET_TSSI_DE_VALUE = 3, + RTW_MP_CAL_CMD_SET_TSSI_DE_TX_VERIFY = 4, + RTW_MP_CAL_CMD_GET_TXPWR_FINAL_ABS = 5, + RTW_MP_CAL_CMD_TRIGGER_DPK_TRACKING = 6, + RTW_MP_CAL_CMD_SET_TSSI_AVG = 7, + RTW_MP_CAL_CMD_PSD_INIT = 8, + RTW_MP_CAL_CMD_PSD_RESTORE = 9, + RTW_MP_CAL_CMD_PSD_GET_POINT_DATA = 10, + RTW_MP_CAL_CMD_PSD_QUERY = 11, + RTW_MP_CAL_CMD_MAX, +}; + +enum rtw_mp_calibration_type { + RTW_MP_CAL_CHL_RFK = 0, + RTW_MP_CAL_DACK = 1, + RTW_MP_CAL_IQK = 2, + RTW_MP_CAL_LCK = 3, + RTW_MP_CAL_DPK = 4, + RTW_MP_CAL_DPK_TRACK = 5, + RTW_MP_CAL_TSSI = 6, + RTW_MP_CAL_GAPK = 7, + RTW_MP_CAL_MAX, +}; + +enum RTW_TEST_SUB_MODULE { + RTW_TEST_SUB_MODULE_MP = 0, + RTW_TEST_SUB_MODULE_FPGA = 1, + RTW_TEST_SUB_MODULE_VERIFY = 2, + RTW_TEST_SUB_MODULE_TOOL = 3, + RTW_TEST_SUB_MODULE_TRX = 4, + RTW_TEST_SUB_MODULE_UNKNOWN, +}; + +struct rtw_test_module_info { + u8 tm_type; + u8 tm_mode; +}; + +#define RTW_MAX_TEST_CMD_BUF 2000 +struct rtw_mp_test_cmdbuf { + u8 type; + u8 buf[RTW_MAX_TEST_CMD_BUF]; + u16 len; +}; + +enum rtw_mp_nss + { + MP_NSS1, + MP_NSS2, + MP_NSS3, + MP_NSS4 + }; + +#define RU_TONE_STR(idx)\ + (idx == MP_RU_TONE_26) ? "26-Tone" :\ + (idx == MP_RU_TONE_52) ? "52-Tone" :\ + (idx == MP_RU_TONE_106) ? "106-Tone" :\ + (idx == MP_RU_TONE_242) ? "242-Tone" :\ + (idx == MP_RU_TONE_484) ? "484-Tone" :\ + (idx == MP_RU_TONE_966) ? "966-Tone" :\ + "UNknow" + +enum rtw_mp_resourceUnit +{ + MP_RU_TONE_26 = 0, + MP_RU_TONE_52, + MP_RU_TONE_106, + MP_RU_TONE_242, + MP_RU_TONE_484, + MP_RU_TONE_966 +}; + +#define MP_IS_HT_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS31) +#define MP_IS_VHT_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9) +#define MP_IS_CCK_HRATE(_rate) ((_rate) == HRATE_CCK1 || (_rate) == HRATE_CCK2 || \ + (_rate) == HRATE_CCK5_5 || (_rate) == HRATE_CCK11) + +#define MP_IS_OFDM_HRATE(_rate) ((_rate) >= HRATE_OFDM6 && (_rate) <= HRATE_OFDM54) +#define MP_IS_HE_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11) + +#define MP_IS_HT1SS_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS7) +#define MP_IS_HT2SS_HRATE(_rate) ((_rate) >= HRATE_MCS8 && (_rate) <= HRATE_MCS15) +#define MP_IS_HT3SS_HRATE(_rate) ((_rate) >= HRATE_MCS16 && (_rate) <= HRATE_MCS23) +#define MP_IS_HT4SS_HRATE(_rate) ((_rate) >= HRATE_MCS24 && (_rate) <= HRATE_MCS31) + +#define MP_IS_VHT1SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS1_MCS9) +#define MP_IS_VHT2SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS2_MCS0 && (_rate) <= HRATE_VHT_NSS2_MCS9) +#define MP_IS_VHT3SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS3_MCS0 && (_rate) <= HRATE_VHT_NSS3_MCS9) +#define MP_IS_VHT4SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS4_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9) + +#define MP_IS_HE1SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS1_MCS11) +#define MP_IS_HE2SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS2_MCS0 && (_rate) <= HRATE_HE_NSS2_MCS11) +#define MP_IS_HE3SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS3_MCS0 && (_rate) <= HRATE_HE_NSS3_MCS11) +#define MP_IS_HE4SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS4_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11) + +#define MP_IS_1T_HRATE(_rate) (MP_IS_CCK_HRATE((_rate)) || MP_IS_OFDM_HRATE((_rate)) \ + || MP_IS_HT1SS_HRATE((_rate)) || MP_IS_VHT1SS_HRATE((_rate)) \ + || MP_IS_HE1SS_HRATE((_rate))) + +#define MP_IS_2T_HRATE(_rate) (MP_IS_HT2SS_HRATE((_rate)) || MP_IS_VHT2SS_HRATE((_rate)) \ + || MP_IS_HE2SS_HRATE((_rate))) + +#define MP_IS_3T_HRATE(_rate) (MP_IS_HT3SS_HRATE((_rate)) || MP_IS_VHT3SS_HRATE((_rate)) \ + || MP_IS_HE3SS_HRATE((_rate))) + +#define MP_IS_4T_HRATE(_rate) (MP_IS_HT4SS_HRATE((_rate)) || MP_IS_VHT4SS_HRATE((_rate)) \ + || MP_IS_HE4SS_HRATE((_rate))) + + + +void rtw_mp_get_phl_cmd(_adapter *padapter, void* buf, u32 buflen); +void rtw_mp_set_phl_cmd(_adapter *padapter, void* buf, u32 buflen); + +bool rtw_mp_phl_config_arg(_adapter *padapter, enum rtw_mp_config_cmdid cmdid); +void rtw_mp_phl_rx_physts(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, bool bstart); +void rtw_mp_phl_rx_rssi(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg); +void rtw_mp_phl_rx_gain_offset(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, u8 path_num); +void rtw_mp_phl_query_rx(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg ,u8 rx_qurey_type); +u8 rtw_mp_phl_txpower(_adapter *padapter, struct rtw_mp_txpwr_arg *ptxpwr_arg, u8 cmdid); +void rtw_mp_set_crystal_cap(_adapter *padapter, u32 xcapvalue); +u8 rtw_mp_phl_calibration(_adapter *padapter, struct rtw_mp_cal_arg *pcal_arg, u8 cmdid); + + +u8 rtw_update_giltf(_adapter *padapter); +void rtw_mp_update_coding(_adapter *padapter); +u8 rtw_mp_update_ru_tone(_adapter *padapter); +u8 rtw_mp_update_ru_alloc(_adapter *padapter); + +bool rtw_mp_is_cck_rate(u16 rate); + +extern s32 init_mp_priv(_adapter *padapter); extern void free_mp_priv(struct mp_priv *pmp_priv); -extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); -extern void MPT_DeInitAdapter(PADAPTER padapter); -extern s32 mp_start_test(PADAPTER padapter); -extern void mp_stop_test(PADAPTER padapter); +extern s32 MPT_InitializeAdapter(_adapter *padapter, u8 Channel); +extern void MPT_DeInitAdapter(_adapter *padapter); +extern s32 mp_start_test(_adapter *padapter); +extern void mp_stop_test(_adapter *padapter); -extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); -extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); -extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); -extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); -extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); -extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); -extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); +extern u32 read_rfreg(_adapter *padapter, u8 rfpath, u32 addr); +extern void write_rfreg(_adapter *padapter, u8 rfpath, u32 addr, u32 val); #ifdef CONFIG_ANTENNA_DIVERSITY -u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain); +u8 rtw_mp_set_antdiv(_adapter *padapter, BOOLEAN bMain); #endif -void SetChannel(PADAPTER pAdapter); -void SetBandwidth(PADAPTER pAdapter); -int SetTxPower(PADAPTER pAdapter); -void SetAntenna(PADAPTER pAdapter); -void SetDataRate(PADAPTER pAdapter); -void SetAntenna(PADAPTER pAdapter); -s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); -void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value); -void SetContinuousTx(PADAPTER pAdapter, u8 bStart); -void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); -void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); -void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); -void PhySetTxPowerLevel(PADAPTER pAdapter); -void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc); -void SetPacketTx(PADAPTER padapter); -void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB); -void ResetPhyRxPktCount(PADAPTER pAdapter); -u32 GetPhyRxPktReceived(PADAPTER pAdapter); -u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); -s32 SetPowerTracking(PADAPTER padapter, u8 enable); -void GetPowerTracking(PADAPTER padapter, u8 *enable); -u32 mp_query_psd(PADAPTER pAdapter, u8 *data); -void rtw_mp_trigger_iqk(PADAPTER padapter); -void rtw_mp_trigger_lck(PADAPTER padapter); -void rtw_mp_trigger_dpk(PADAPTER padapter); -u8 rtw_mp_mode_check(PADAPTER padapter); +void SetChannel(_adapter *adapter); +void SetBandwidth(_adapter *adapter); +int rtw_mp_txpoweridx(_adapter *adapter); +u16 rtw_mp_txpower_dbm(_adapter *adapter, u8 rf_path); +u16 rtw_mp_get_pwrtab_dbm(_adapter *adapter, u8 rfpath); + +void SetAntenna(_adapter *adapter); +void SetDataRate(_adapter *adapter); +s32 SetThermalMeter(_adapter *adapter, u8 target_ther); +void GetThermalMeter(_adapter *adapter, u8 rfpath ,u8 *value); +void rtw_mp_continuous_tx(_adapter *adapter, u8 bstart); +void rtw_mp_singlecarrier_tx(_adapter *adapter, u8 bstart); +void rtw_mp_singletone_tx(_adapter *adapter, u8 bstart); +void rtw_mp_carriersuppr_tx(_adapter *adapter, u8 bstart); +void rtw_mp_txpwr_level(_adapter *adapter); +void fill_txdesc_for_mp(_adapter *padapter, u8 *ptxdesc); +void rtw_set_phl_packet_tx(_adapter *padapter, u8 bStart); +u8 rtw_phl_mp_tx_cmd(_adapter *padapter, enum rtw_mp_tx_cmd cmdid, + enum rtw_mp_tx_method tx_method, boolean bstart); + +void rtw_mp_set_packet_tx(_adapter *padapter); +void rtw_mp_reset_phy_count(_adapter *adapter); + +s32 SetPowerTracking(_adapter *padapter, u8 enable); +void GetPowerTracking(_adapter *padapter, u8 *enable); +u32 mp_query_psd(_adapter *adapter, u8 *data); +void rtw_mp_trigger_iqk(_adapter *padapter); +void rtw_mp_trigger_lck(_adapter *padapter); +void rtw_mp_trigger_dpk(_adapter *padapter); +u8 rtw_mp_mode_check(_adapter *padapter); bool rtw_is_mp_tssitrk_on(_adapter *adapter); -void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); -s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable); -void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable); -void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); -void hal_mpt_SetChannel(PADAPTER pAdapter); -void hal_mpt_SetBandwidth(PADAPTER pAdapter); -void hal_mpt_SetTxPower(PADAPTER pAdapter); -void hal_mpt_SetDataRate(PADAPTER pAdapter); -void hal_mpt_SetAntenna(PADAPTER pAdapter); -s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); -void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter); -u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path); -void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value); -void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart); -void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); -void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); -void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); -u8 mpt_ProSetPMacTx(PADAPTER Adapter); -void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); -void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate); -u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); -u32 mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); -void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type); +void mpt_ProSetPMacTx(_adapter *adapter); +void MP_PHY_SetRFPathSwitch(_adapter *adapter , BOOLEAN bMain); +void mp_phy_switch_rf_path_set(_adapter *adapter , u8 *pstate); +u8 MP_PHY_QueryRFPathSwitch(_adapter *adapter); +u32 mpt_ProQueryCalTxPower(_adapter *adapter, u8 RfPath); u8 mpt_to_mgnt_rate(u32 MptRateIdx); -u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr); -u32 mp_join(PADAPTER padapter, u8 mode); -u32 hal_mpt_query_phytxok(PADAPTER pAdapter); -u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path); -void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path); - +u16 rtw_mp_rate_parse(_adapter *adapter, u8 *target_str); +u32 mp_join(_adapter *padapter, u8 mode); +u32 hal_mpt_query_phytxok(_adapter *adapter); +u32 mpt_get_tx_power_finalabs_val(_adapter *padapter, u8 rf_path); +void mpt_trigger_tssi_tracking(_adapter *adapter, u8 rf_path); +u8 rtw_mpt_set_power_limit_en(_adapter *padapter, bool en_val); +bool rtw_mpt_get_power_limit_en(_adapter *padapter); + +u32 rtw_mp_get_tssi_de(_adapter *padapter, u8 rf_path); +s32 rtw_mp_get_online_tssi_de(_adapter *padapter, s32 out_pwr, s32 tgdbm, u8 rf_path); +u8 rtw_mp_set_tsside2verify(_adapter *padapter, u32 tssi_de, u8 rf_path); +u8 rtw_mp_set_tssi_offset(_adapter *padapter, u32 tssi_offset, u8 rf_path); +u8 rtw_mp_set_tssi_pwrtrk(_adapter *padapter, u8 tssi_state); +u8 rtw_mp_get_tssi_pwrtrk(_adapter *padapter); + +void rtw_mp_cal_trigger(_adapter *padapter, u8 cal_tye); +void rtw_mp_cal_capab(_adapter *padapter, u8 cal_tye, u8 benable); void PMAC_Get_Pkt_Param( @@ -809,7 +1622,7 @@ int rtw_mp_rate(struct net_device *dev, int rtw_mp_channel(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); -int rtw_mp_ch_offset(struct net_device *dev, +int rtw_mp_trxsc_offset(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); int rtw_mp_bandwidth(struct net_device *dev, @@ -821,9 +1634,6 @@ int rtw_mp_txpower_index(struct net_device *dev, int rtw_mp_txpower(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); -int rtw_mp_txpower(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); int rtw_mp_ant_tx(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); @@ -890,21 +1700,20 @@ int rtw_mp_mon(struct net_device *dev, int rtw_mp_pwrlmt(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); -int rtw_mp_pwrbyrate(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); int rtw_mp_dpk_track(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); int rtw_mp_dpk(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +#if 0 int rtw_efuse_mask_file(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); int rtw_bt_efuse_mask_file(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtw_efuse_file_map(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -914,10 +1723,12 @@ int rtw_efuse_file_map_store(struct net_device *dev, int rtw_bt_efuse_file_map(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +#endif + int rtw_mp_SetBT(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); -int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra); +int rtw_mp_pretx_proc(_adapter *padapter, u8 bStartTest, char *extra); int rtw_mp_tx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -927,7 +1738,7 @@ int rtw_mp_rx(struct net_device *dev, int rtw_mp_hwtx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); -u8 HwRateToMPTRate(u8 rate); +u8 rtw_mp_hwrate2mptrate(u8 rate); int rtw_mp_iqk(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); @@ -940,4 +1751,51 @@ int rtw_mp_get_tsside(struct net_device *dev, int rtw_mp_set_tsside(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); + +int rtw_priv_mp_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra); + +int rtw_priv_mp_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra); + +int rtw_mp_set_phl_io(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); + +int rtw_mp_get_phl_io(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); + +int rtw_mp_tx_pattern_idx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +int rtw_mp_tx_plcp_tx_data(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +int rtw_mp_tx_plcp_tx_user(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +int rtw_mp_tx_method(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +int rtw_mp_config_phy(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +int rtw_mp_phl_rfk(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_phl_btc_path(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_get_he(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + #endif /* _RTW_MP_H_ */ diff --git a/include/rtw_p2p.h b/include/rtw_p2p.h index 8d929ad..da43753 100644 --- a/include/rtw_p2p.h +++ b/include/rtw_p2p.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,11 +16,7 @@ #define __RTW_P2P_H_ -u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); -u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); -u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); -u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); #ifdef CONFIG_WFD int rtw_init_wifi_display_info(_adapter *padapter); void rtw_wfd_enable(_adapter *adapter, bool on); @@ -51,20 +47,11 @@ void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe); u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); -u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe); -u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); -int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength); - -s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf); +int process_p2p_cross_connect_ie(_adapter *padapter, u8 *IEs, u32 IELength); #ifdef CONFIG_P2P_PS -void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); +void process_p2p_ps_ie(_adapter *padapter, u8 *IEs, u32 IELength); void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); #endif /* CONFIG_P2P_PS */ @@ -74,94 +61,28 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); #endif /* CONFIG_IOCTL_CFG80211 */ void reset_global_wifidirect_info(_adapter *padapter); -void rtw_init_wifidirect_timers(_adapter *padapter); -void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr); void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role); int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role); -static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) -{ - if (wdinfo->p2p_state != state) { - /* wdinfo->pre_p2p_state = wdinfo->p2p_state; */ - wdinfo->p2p_state = state; - } -} -static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) -{ - if (wdinfo->pre_p2p_state != state) - wdinfo->pre_p2p_state = state; -} -#if 0 -static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo) -{ - if (wdinfo->pre_p2p_state != -1) { - wdinfo->p2p_state = wdinfo->pre_p2p_state; - wdinfo->pre_p2p_state = -1; - } -} -#endif void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role); -static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) -{ - return wdinfo->p2p_state; -} -static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) -{ - return wdinfo->pre_p2p_state; -} static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) { return wdinfo->role; } -static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) -{ - return wdinfo->p2p_state == state; -} static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) { return wdinfo->role == role; } #ifdef CONFIG_DBG_P2P -void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); -void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); -/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */ void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); -#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) -#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) #define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) -/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */ #else /* CONFIG_DBG_P2P */ -#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) -#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) #define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) -/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */ #endif /* CONFIG_DBG_P2P */ -#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) -#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) #define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) -#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) #define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) -#define rtw_p2p_findphase_ex_set(wdinfo, value) \ - (wdinfo)->find_phase_state_exchange_cnt = (value) - -#ifdef CONFIG_P2P -/* is this find phase exchange for social channel scan? */ -#define rtw_p2p_findphase_ex_is_social(wdinfo) \ - (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST - -/* should we need find phase exchange anymore? */ -#define rtw_p2p_findphase_ex_is_needed(wdinfo) \ - ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ - (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \ - !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \ - !(wdinfo)->p2p_info.scan_op_ch_only) -#else -#define rtw_p2p_findphase_ex_is_social(wdinfo) 0 -#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0 -#endif /* CONFIG_P2P */ - #endif diff --git a/include/rtw_phl.h b/include/rtw_phl.h new file mode 100644 index 0000000..fb92e21 --- /dev/null +++ b/include/rtw_phl.h @@ -0,0 +1,133 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_PHL_H_ +#define _RTW_PHL_H_ + +typedef struct rtw_phl_com_t HAL_DATA_TYPE; /*, *PHAL_DATA_TYPE;*/ + +#define GET_PHL_INFO(_dvobj) (_dvobj->phl) +#define GET_PHL_COM(_dvobj) (_dvobj->phl_com) +#define GET_HAL_SPEC(_dvobj) (&(GET_PHL_COM(_dvobj)->hal_spec)) + + +/* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/ +#define GET_HAL_TX_NSS(_dvobj) ((GET_PHL_COM(_dvobj))->tx_nss) +#define GET_HAL_RX_NSS(_dvobj) ((GET_PHL_COM(_dvobj))->rx_nss) +#define GET_HAL_RFPATH_NUM(_dvobj) ((GET_PHL_COM(_dvobj))->rf_path_num) +/* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/ +#define GET_HAL_RFPATH(_dvobj) ((GET_PHL_COM(_dvobj))->rf_type) + +#define GET_WIFI_ROLE_CURRENT_CH(_adapter) (_adapter->phl_role->chandef.ch) +#define WIFI_ROLE_IS_ON_24G(_adapter) (_adapter->phl_role->chandef.band == BAND_ON_24G) +#define WIFI_ROLE_IS_ON_5G(_adapter) (_adapter->phl_role->chandef.band == BAND_ON_5G) +#define WIFI_ROLE_IS_ON_6G(_adapter) (_adapter->phl_role->chandef.band == BAND_ON_6G) + +#define RTW_LITEXMITBUF_NR 256 +#define RTW_XMITURB_NR 256 +#define RTW_LITERECVBUF_NR 8 +#define RTW_RECVURB_NR 8 +#define RTW_INTINBUF_NR 1 +#define RTW_INTINURB_NR 1 + +s8 rtw_phl_rssi_to_dbm(u8 rssi); + +void rtw_hw_dump_hal_spec(void *sel, struct dvobj_priv *dvobj); +void rtw_dump_phl_sta_info(void *sel, struct sta_info *sta); + +bool rtw_hw_chk_band_cap(struct dvobj_priv *dvobj, u8 cap); +bool rtw_hw_chk_bw_cap(struct dvobj_priv *dvobj, u8 cap); +bool rtw_hw_chk_proto_cap(struct dvobj_priv *dvobj, u8 cap); +bool rtw_hw_chk_wl_func(struct dvobj_priv *dvobj, u8 func); +bool rtw_hw_is_band_support(struct dvobj_priv *dvobj, u8 band); +bool rtw_hw_is_bw_support(struct dvobj_priv *dvobj, u8 bw); +bool rtw_hw_is_wireless_mode_support(struct dvobj_priv *dvobj, u8 mode); +u8 rtw_hw_get_wireless_mode(struct dvobj_priv *dvobj); +u8 rtw_hw_get_band_type(struct dvobj_priv *dvobj); +u8 rtw_hw_get_mac_addr(struct dvobj_priv *dvobj, u8 *hw_mac_addr); + +bool rtw_hw_is_mimo_support(struct dvobj_priv *dvobj); +u8 rtw_hw_largest_bw(struct dvobj_priv *dvobj, u8 in_bw); +u8 rtw_hw_init(struct dvobj_priv *dvobj); +void rtw_hw_deinit(struct dvobj_priv *dvobj); + + +u8 rtw_hw_start(struct dvobj_priv *dvobj); +void rtw_hw_stop(struct dvobj_priv *dvobj); +bool rtw_hw_get_init_completed(struct dvobj_priv *dvobj); +bool rtw_hw_is_init_completed(struct dvobj_priv *dvobj); +void rtw_hw_cap_init(struct dvobj_priv *dvobj); + +u8 rtw_hw_iface_init(_adapter *adapter); +u8 rtw_hw_iface_type_change(_adapter *adapter, u8 iface_type); +void rtw_hw_iface_deinit(_adapter *adapter); + +/* security */ +u8 rtw_sec_algo_drv2phl(enum security_type drv_algo); +u8 rtw_sec_algo_phl2drv(enum rtw_enc_algo phl_algo); +int rtw_hw_add_key(struct _ADAPTER *a, struct sta_info *sta, + u8 keyid, enum security_type keyalgo, u8 keytype, u8 *key, + u8 spp, enum phl_cmd_type cmd_type, u32 cmd_timeout); +int rtw_hw_del_key(struct _ADAPTER *a, struct sta_info *sta, + u8 keyid, u8 keytype, enum phl_cmd_type cmd_type, u32 cmd_timeout); +int rtw_hw_del_all_key(struct _ADAPTER *a, struct sta_info *sta, + enum phl_cmd_type cmd_type, u32 cmd_timeout); + +/* settting */ +int rtw_hw_set_ch_bw(struct _ADAPTER *a, + u8 ch, enum channel_width bw, u8 offset, u8 do_rfk); +int rtw_hw_set_edca(struct _ADAPTER *a, u8 ac, u32 param); + +/* connect */ +#ifdef RTW_WKARD_UPDATE_PHL_ROLE_CAP +void rtw_update_phl_cap_by_rgstry(struct _ADAPTER *a); +#endif +void rtw_update_phl_sta_cap(struct _ADAPTER *a, struct sta_info *sta, + struct protocol_cap_t *cap); +int rtw_hw_prepare_connect(struct _ADAPTER *a, struct sta_info *sta, u8 *target_addr); +int rtw_hw_start_bss_network(struct _ADAPTER *a); +int rtw_hw_connect_abort(struct _ADAPTER *a, struct sta_info *sta); +int rtw_hw_connected(struct _ADAPTER *a, struct sta_info *sta); +int rtw_hw_connected_apmode(struct _ADAPTER *a, struct sta_info *sta); +int rtw_hw_disconnect(struct _ADAPTER *a, struct sta_info *sta); + +void rtw_hw_update_chan_def(_adapter *adapter); + +#ifdef RTW_DETECT_HANG +void rtw_is_hang_check(struct _ADAPTER *a); +#endif + +#ifdef CONFIG_RTW_ACS +u16 rtw_acs_get_channel_by_idx(struct _ADAPTER *a, u8 idx); +u8 rtw_acs_get_clm_ratio_by_idx(struct _ADAPTER *a, u8 idx); +s8 rtw_noise_query_by_idx(struct _ADAPTER *a, u8 idx); +#endif /* CONFIG_RTW_ACS */ + +void rtw_dump_env_rpt(struct _ADAPTER *a, void *sel); + +#ifdef CONFIG_WOWLAN +u8 rtw_hw_wow(struct _ADAPTER *a, u8 wow_en); +#endif + +#ifdef CONFIG_MCC_MODE +u8 rtw_hw_mcc_chk_inprogress(struct _ADAPTER *a); +#endif + +void rtw_update_phl_edcca_mode(struct _ADAPTER *a); + +void rtw_dump_phl_tx_power_ext_info(void *sel, _adapter *adapter); + +void rtw_update_phl_txpwr_level(_adapter *adapter); + +#endif /* _RTW_HW_H_ */ diff --git a/include/rtw_phl_cmd.h b/include/rtw_phl_cmd.h new file mode 100644 index 0000000..972172d --- /dev/null +++ b/include/rtw_phl_cmd.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_PHL_CMD__ +#define __RTW_PHL_CMD__ +u32 rtw_enqueue_phl_cmd(struct cmd_obj *pcmd); +#ifdef CONFIG_CMD_TSF_SYNC +enum rtw_phl_status rtw_send_tsf_sync_done_msg(struct _ADAPTER *a); +#endif +#if defined (CONFIG_CMD_GENERAL) && defined (CONFIG_PCIE_TRX_MIT) +u8 rtw_pcie_trx_mit_cmd(_adapter *padapter, u32 tx_timer, u8 tx_counter, + u32 rx_timer, u8 rx_counter, u8 fixed_mit); +#endif +#endif /* __RTW_PHL_CMD__ */ + diff --git a/include/rtw_pwrctrl.h b/include/rtw_pwrctrl.h index e17c50b..5067450 100644 --- a/include/rtw_pwrctrl.h +++ b/include/rtw_pwrctrl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,6 +15,8 @@ #ifndef __RTW_PWRCTRL_H_ #define __RTW_PWRCTRL_H_ +#define PS_ACTIVE 0 +#define PS_LPS 1 #define FW_PWR0 0 #define FW_PWR1 1 @@ -35,71 +37,20 @@ #define RECV_ALIVE BIT(1) #define CMD_ALIVE BIT(2) #define EVT_ALIVE BIT(3) -#ifdef CONFIG_BT_COEXIST -#define BTCOEX_ALIVE BIT(4) -#endif /* CONFIG_BT_COEXIST */ -#define LPS_ALIVE BIT(5) -#ifdef CONFIG_WOWLAN - #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86 - /* TCP/ICMP/UDP multicast with specific IP addr */ - #define DEFAULT_PATTERN_NUM 4 - #else - /* TCP/ICMP */ - #define DEFAULT_PATTERN_NUM 3 - #endif - -#ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */ -#define MAX_WKFM_CAM_NUM 12 -#else -#define MAX_WKFM_CAM_NUM 10 -#endif - -#define MAX_WKFM_SIZE 16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */ -#define MAX_WKFM_PATTERN_SIZE 128 -#define MAX_IN_PATTERN_SIZE 512 - -/* - * MAX_WKFM_PATTERN_STR_LEN : the max. length of wow pattern string - * e.g. echo 00:01:02:...:7f > /proc/net/rtl88x2bu/wlan0/wow_pattern_info - * - each byte of pattern is represented as 2-bytes ascii : MAX_WKFM_PATTERN_SIZE * 2 - * - the number of common ':' in pattern string : MAX_WKFM_PATTERN_SIZE - 1 - * - 1 byte '\n'(0x0a) is generated at the end when we use echo command - * so total max. length is (MAX_WKFM_PATTERN_SIZE * 3) - */ -#define MAX_WKFM_PATTERN_STR_LEN (MAX_WKFM_PATTERN_SIZE * 3) - -#define WKFMCAM_ADDR_NUM 6 -#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */ -enum pattern_type { - PATTERN_BROADCAST = 0, - PATTERN_MULTICAST, - PATTERN_UNICAST, - PATTERN_VALID, - PATTERN_INVALID, -}; - -typedef struct rtl_priv_pattern { - int len; - char content[MAX_WKFM_PATTERN_SIZE]; - char mask[MAX_WKFM_SIZE]; -} rtl_priv_pattern_t; - -#endif /* CONFIG_WOWLAN */ - -enum Power_Mgnt { - PS_MODE_ACTIVE = 0 , - PS_MODE_MIN , - PS_MODE_MAX , - PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */ - PS_MODE_VOIP , - PS_MODE_UAPSD_WMM , - PS_MODE_UAPSD , - PS_MODE_IBSS , - PS_MODE_WWLAN , - PM_Radio_Off , - PM_Card_Disable , - PS_MODE_NUM, +enum power_mgnt { + PM_PS_MODE_ACTIVE = 0 , + PM_PS_MODE_MIN , + PM_PS_MODE_MAX , + PM_PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */ + PM_PS_MODE_VOIP , + PM_PS_MODE_UAPSD_WMM , + PM_PS_MODE_UAPSD , + PM_PS_MODE_IBSS , + PM_PS_MODE_WWLAN , + PM_RADIO_OFF , + PM_CARD_DISABLE , + PM_PS_MODE_NUM, }; enum lps_level { @@ -109,11 +60,6 @@ enum lps_level { LPS_LEVEL_MAX, }; -#ifdef CONFIG_PNO_SUPPORT -#define MAX_PNO_LIST_COUNT 16 -#define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */ -#define MAX_HIDDEN_AP 8 /* 8 hidden AP */ -#endif /* BIT[2:0] = HW state @@ -235,179 +181,6 @@ typedef enum _PS_DENY_REASON { PS_DENY_OTHERS = 31 } PS_DENY_REASON; -#ifdef CONFIG_WAR_OFFLOAD -/* only support mDNS V4/V6 rsp now */ -enum { - WAR_ARP_RSP_EN = 0x0000001, - WAR_ICMPV6_NS_RSP_EN = 0x00000002, - WAR_ICMPV4_ECHO_RSP_EN = 0x00000004, - WAR_ICMPV6_ECHO_RSP_EN = 0x00000008, - WAR_NETBIOS_RSP_EN = 0x00000010, - WAR_LLMNR_V4_RSP_EN = 0x00000020, - WAR_LLMNR_V6_RSP_EN = 0x00000040, - WAR_SNMP_V4_RSP_EN = 0x00000080, - WAR_SNMP_V6_RSP_EN = 0x00000100, - WAR_SNMP_V4_WAKEUP_EN = 0x00000200, - WAR_SNMP_V6_WAKEUP_EN = 0x00000400, - WAR_SSDP_V4_WAKEUP_EN = 0x00000800, - WAR_SSDP_V6_WAKEUP_EN = 0x00001000, - WAR_WSD_V4_WAKEUP_EN = 0x00002000, - WAR_WSD_V6_WAKEUP_EN = 0x00004000, - WAR_SLP_V4_WAKEUP_EN = 0x00008000, - WAR_SLP_V6_WAKEUP_EN = 0x00010000, - WAR_MDNS_V4_RSP_EN = 0x00020000, - WAR_MDNS_V6_RSP_EN = 0x00040000, - WAR_DESIGNATED_MAC_EN = 0x00080000, - WAR_LLTD_WAKEUP_EN = 0x00100000, - WAR_ARP_WAKEUP_EN = 0x00200000, - WAR_MAGIC_WAKEUP_EN = 0x00400000, - WAR_MDNS_V4_WAKEUP_EN = 0x000800000, - WAR_MDNS_V6_WAKEUP_EN = 0x001000000 -}; - -#endif /* CONFIG_WAR_OFFLOAD */ - -#ifdef CONFIG_PNO_SUPPORT -typedef struct pno_nlo_info { - u32 fast_scan_period; /* Fast scan period */ - u8 ssid_num; /* number of entry */ - u8 hidden_ssid_num; - u32 slow_scan_period; /* slow scan period */ - u32 fast_scan_iterations; /* Fast scan iterations */ - u8 ssid_length[MAX_PNO_LIST_COUNT]; /* SSID Length Array */ - u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; /* Cipher information for security */ - u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; /* channel information */ - u8 loc_probe_req[MAX_HIDDEN_AP]; /* loc_probeReq */ -} pno_nlo_info_t; - -typedef struct pno_ssid { - u32 SSID_len; - u8 SSID[32]; -} pno_ssid_t; - -typedef struct pno_ssid_list { - pno_ssid_t node[MAX_PNO_LIST_COUNT]; -} pno_ssid_list_t; - -typedef struct pno_scan_channel_info { - u8 channel; - u8 tx_power; - u8 timeout; - u8 active; /* set 1 means active scan, or pasivite scan. */ -} pno_scan_channel_info_t; - -typedef struct pno_scan_info { - u8 enableRFE; /* Enable RFE */ - u8 period_scan_time; /* exclusive with fast_scan_period and slow_scan_period */ - u8 periodScan; /* exclusive with fast_scan_period and slow_scan_period */ - u8 orig_80_offset; /* original channel 80 offset */ - u8 orig_40_offset; /* original channel 40 offset */ - u8 orig_bw; /* original bandwidth */ - u8 orig_ch; /* original channel */ - u8 channel_num; /* number of channel */ - u64 rfe_type; /* rfe_type && 0x00000000000000ff */ - pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT]; -} pno_scan_info_t; -#endif /* CONFIG_PNO_SUPPORT */ - -#ifdef CONFIG_LPS_POFF -/* Driver context for LPS 32K Close IO Power */ -typedef struct lps_poff_info { - bool bEn; - u8 *pStaticFile; - u8 *pDynamicFile; - u32 ConfFileOffset; - u32 tx_bndy_static; - u32 tx_bndy_dynamic; - u16 ConfLenForPTK; - u16 ConfLenForGTK; - ATOMIC_T bEnterPOFF; - ATOMIC_T bTxBoundInProgress; - ATOMIC_T bSetPOFFParm; -} lps_poff_info_t; -#endif /*CONFIG_LPS_POFF*/ - -struct aoac_report { - u8 iv[8]; - u8 replay_counter_eapol_key[8]; - u8 group_key[32]; - u8 key_index; - u8 security_type; - u8 wow_pattern_idx; - u8 version_info; - u8 rekey_ok:1; - u8 dummy:7; - u8 reserved[3]; - u8 rxptk_iv[8]; - u8 rxgtk_iv[4][8]; -}; - -#ifdef CONFIG_WAR_OFFLOAD - -struct war_ipv4_fmt { - u32 ip_addr[4]; - u32 ip_subnet[4]; - u32 ip_gateway[4]; -}; - -struct war_ipv6_fmt { - u8 ipv6_addr[8][16]; -}; - -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) -/* limitation of mDNS parameter : length and number */ -#define MAX_MDNS_SERVICE_NAME_LEN 15 -#define MAX_MDNS_TRANS_LEN 4 /* _tcp or _udp */ -#define MAX_MDNS_DOMAIN_LEN 5 /* local only for mdns */ -#define MAX_MDNS_MACHINE_NAME_LEN (63+1) /* +1 for the length byte used by the DNS format */ -#define MAX_MDNS_TARGET_LEN 63 -#define MAX_MDNS_DOMAIN_NAME_LEN 63 -#define MAX_MDNS_TXT_LEN 1536 -#define MAX_MDNS_TXT_SINGLE_LEN 255 - - -#define MAX_MDNS_SERVICE_NUM 10 -#define MAX_MDNS_TXT_NUM 8 -#define MAX_MDNS_MACHINE_NAME_NUM 3 - -/* for monitor rsvd page using */ -#define MAX_MDNS_PARA_SIZE 1700 // 14*128 = 1792 -#define MAX_MDNS_TXT_TOTAL_SIZE 10*MAX_MDNS_TXT_LEN -#define MAX_MDNS_RSP_PKT_SIZE 760 // 6*128 = 768 - -#define RTW_MDNS_SRV_INFO(sname, sname_len, tname, tname_len, dname, dname_len, port0, port1, ttlv, tar, tar_len, idx) \ - { .service=sname, .service_len=sname_len, .transport=tname, .transport_len=tname_len, \ - .domain=dname , .domain_len=dname_len , .port[0]=port0, .port[1]=port1, .ttl=ttlv, \ - .target=tar, .target_len=tar_len, .txt_rsp_idx=idx } - - -struct war_mdns_service_info { - u8 service[MAX_MDNS_SERVICE_NAME_LEN+1]; - u8 service_len; - u8 transport[MAX_MDNS_TRANS_LEN+1]; - u8 transport_len; - u8 domain[MAX_MDNS_DOMAIN_LEN+1]; - u8 domain_len; - u8 port[2]; - u32 ttl; - u8 target[MAX_MDNS_TARGET_LEN+1]; - u8 target_len; - s8 txt_rsp_idx; -}; - -struct war_mdns_machine_name { - u8 name[MAX_MDNS_MACHINE_NAME_LEN]; - u8 name_len; -}; - -struct war_mdns_txt_rsp { - u8 txt[MAX_MDNS_TXT_LEN]; - u16 txt_len; -}; -#endif -#endif /* CONFIG_WAR_OFFLOAD */ - - struct rsvd_page_cache_t; struct pwrctrl_priv { @@ -484,7 +257,7 @@ struct pwrctrl_priv { s32 pnp_current_pwr_state; u8 pnp_bstop_trx; u8 bInSuspend; -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC u8 bAutoResume; u8 autopm_cnt; #endif @@ -498,13 +271,9 @@ struct pwrctrl_priv { u8 wowlan_in_resume; #ifdef CONFIG_GPIO_WAKEUP - u8 is_high_active; - u8 wowlan_gpio_index; - u8 wowlan_gpio_output_state; #endif /* CONFIG_GPIO_WAKEUP */ u8 hst2dev_high_active; #ifdef CONFIG_WOWLAN - bool default_patterns_en; #ifdef CONFIG_IPV6 u8 wowlan_ns_offload_en; #endif /*CONFIG_IPV6*/ @@ -512,18 +281,13 @@ struct pwrctrl_priv { u8 wowlan_pattern_idx; u64 wowlan_fw_iv; struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM]; -#ifdef CONFIG_WOW_PATTERN_IN_TXFIFO - u8 pattern_rsvd_page_loc; -#endif #ifdef CONFIG_PNO_SUPPORT u8 pno_inited; pno_nlo_info_t *pnlo_info; pno_scan_info_t *pscan_info; pno_ssid_list_t *pno_ssid_list; #endif /* CONFIG_PNO_SUPPORT */ -#ifdef CONFIG_WOW_PATTERN_HW_CAM _mutex wowlan_pattern_cam_mutex; -#endif u8 wowlan_aoac_rpt_loc; struct aoac_report wowlan_aoac_rpt; u8 wowlan_power_mgmt; @@ -531,45 +295,6 @@ struct pwrctrl_priv { #ifdef CONFIG_LPS_1T1R u8 wowlan_lps_1t1r; #endif - - #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - /*data 0,rsv page location*/ - u8 wowlan_keep_alive_mode; - u8 keep_alive_pattern_loc; - /*data 1 ,cam id, rx udp packet*/ - u8 wowlan_keep_alive_ack_index; - /*data 2 ,cam id, pattern match packet*/ - u8 wowlan_wake_pattern_index; - /*data3,unit: TBTT*/ - u16 wowlan_keep_alive_period; - /*data4,unit: TBTT*/ - u8 wowlan_keep_alive_retry_interval; - /*data5*/ - u8 wowlan_keep_alive_retry_counter; - /*from echo*/ - u8 keep_alive_pattern[WLAN_MAX_KEEP_ALIVE_IE_LEN]; - u32 keep_alive_pattern_len; - #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - -#ifdef CONFIG_WAR_OFFLOAD - u8 wowlan_war_offload_mode; - u32 wowlan_war_offload_ctrl; - struct war_ipv4_fmt wowlan_war_offload_ipv4; - struct war_ipv6_fmt wowlan_war_offload_ipv6; - u8 wowlan_war_offload_mac[6]; -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) - struct war_mdns_machine_name wowlan_war_offload_mdns_mnane[MAX_MDNS_MACHINE_NAME_NUM]; - struct war_mdns_service_info wowlan_war_offload_mdns_service[MAX_MDNS_SERVICE_NUM]; - struct war_mdns_txt_rsp wowlan_war_offload_mdns_txt_rsp[MAX_MDNS_TXT_NUM]; - u8 wowlan_war_offload_mdns_mnane_num; - u8 wowlan_war_offload_mdns_service_info_num; - u8 wowlan_war_offload_mdns_txt_rsp_num; - u8 wowlan_war_offload_mdns_domain_name[MAX_MDNS_DOMAIN_NAME_LEN+1]; - u8 wowlan_war_offload_mdns_domain_name_len; - u32 wowlan_war_offload_mdns_para_cur_size; - u32 wowlan_war_offload_mdns_rsp_cur_size; -#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */ -#endif /* CONFIG_WAR_OFFLOAD */ #endif /* CONFIG_WOWLAN */ _timer pwr_state_check_timer; int pwr_state_check_interval; @@ -579,9 +304,6 @@ struct pwrctrl_priv { rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */ /* rt_rf_power_state current_rfpwrstate; */ rt_rf_power_state change_rfpwrstate; - - u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */ - u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */ u8 bkeepfwalive; u8 brfoffbyhw; unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; @@ -601,9 +323,6 @@ struct pwrctrl_priv { u8 do_late_resume; #endif -#ifdef CONFIG_LPS_POFF - lps_poff_info_t *plps_poff_info; -#endif u8 lps_level_bk; u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/ #ifdef CONFIG_LPS_1T1R @@ -642,7 +361,10 @@ struct pwrctrl_priv { (pwrctl)->ips_mode_req = (ips_mode) #define RTW_PWR_STATE_CHK_INTERVAL 2000 - +#ifdef CONFIG_RTW_IPS +bool rtw_core_set_ips_state(void *drv_priv, enum rtw_rf_state state); +#endif +#ifdef CONFIG_POWER_SAVING #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \ do { \ /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \ @@ -651,27 +373,29 @@ struct pwrctrl_priv { #define rtw_set_pwr_state_check_timer(pwrctl) \ _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval) - +#endif extern void rtw_init_pwrctrl_priv(_adapter *adapter); extern void rtw_free_pwrctrl_priv(_adapter *adapter); #ifdef CONFIG_LPS_LCLK -s32 rtw_register_task_alive(PADAPTER, u32 task); -void rtw_unregister_task_alive(PADAPTER, u32 task); -extern s32 rtw_register_tx_alive(PADAPTER padapter); -extern void rtw_unregister_tx_alive(PADAPTER padapter); -extern s32 rtw_register_rx_alive(PADAPTER padapter); -extern void rtw_unregister_rx_alive(PADAPTER padapter); -extern s32 rtw_register_cmd_alive(PADAPTER padapter); -extern void rtw_unregister_cmd_alive(PADAPTER padapter); -extern s32 rtw_register_evt_alive(PADAPTER padapter); -extern void rtw_unregister_evt_alive(PADAPTER padapter); -extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); -extern void LPS_Leave_check(PADAPTER padapter); +s32 rtw_register_task_alive(_adapter *, u32 task); +void rtw_unregister_task_alive(_adapter *, u32 task); +extern s32 rtw_register_tx_alive(_adapter *padapter); +extern void rtw_unregister_tx_alive(_adapter *padapter); +extern s32 rtw_register_rx_alive(_adapter *padapter); +extern void rtw_unregister_rx_alive(_adapter *padapter); + +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ +extern s32 rtw_register_cmd_alive(_adapter *padapter); +extern void rtw_unregister_cmd_alive(_adapter *padapter); +#endif + +extern void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate); +extern void LPS_Leave_check(_adapter *padapter); #endif -extern void LeaveAllPowerSaveMode(PADAPTER Adapter); -extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter); +extern void LeaveAllPowerSaveMode(_adapter *adapter); +extern void LeaveAllPowerSaveModeDirect(_adapter *adapter); #ifdef CONFIG_IPS void _ips_enter(_adapter *padapter); void ips_enter(_adapter *padapter); @@ -679,35 +403,28 @@ int _ips_leave(_adapter *padapter); int ips_leave(_adapter *padapter); #endif +#ifdef CONFIG_POWER_SAVING void rtw_ps_processor(_adapter *padapter); - -#ifdef SUPPORT_HW_RFOFF_DETECTED -rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter); #endif - #ifdef DBG_CHECK_FW_PS_STATE -int rtw_fw_ps_state(PADAPTER padapter); +int rtw_fw_ps_state(_adapter *padapter); #endif #ifdef CONFIG_LPS extern const char * const LPS_CTRL_PHYDM; -void LPS_Enter(PADAPTER padapter, const char *msg); -void LPS_Leave(PADAPTER padapter, const char *msg); -void rtw_exec_lps(_adapter *padapter, u8 ps_mode); -void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl); +void LPS_Enter(_adapter *padapter, const char *msg); +void LPS_Leave(_adapter *padapter, const char *msg); +void rtw_leave_lps_and_chk(_adapter *padapter, u8 ps_mode); #ifdef CONFIG_CHECK_LEAVE_LPS #ifdef CONFIG_LPS_CHK_BY_TP -void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta); +void traffic_check_for_leave_lps_by_tp(_adapter *padapter, u8 tx, struct sta_info *sta); #endif -void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); +void traffic_check_for_leave_lps(_adapter *padapter, u8 tx, u32 tx_packets); #endif /*CONFIG_CHECK_LEAVE_LPS*/ -void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); -void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); +void rtw_set_ps_mode(_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); + u8 rtw_set_rpwm(_adapter *padapter, u8 val8); -#ifdef CONFIG_WOWLAN -void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en); -#endif /* CONFIG_WOWLAN */ #endif /* CONFIG_LPS */ #ifdef CONFIG_RESUME_IN_WORKQUEUE @@ -728,7 +445,6 @@ void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); #define rtw_unregister_early_suspend(pwrpriv) do {} while (0) #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ -u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); void rtw_set_ips_deny(_adapter *padapter, u32 ms); int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__) @@ -740,36 +456,11 @@ int rtw_pm_set_lps_level(_adapter *padapter, u8 level); int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en); #endif void rtw_set_lps_deny(_adapter *adapter, u32 ms); -#ifdef CONFIG_WOWLAN -int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode); -int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level); -#ifdef CONFIG_LPS_1T1R -int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en); -#endif -#endif /* CONFIG_WOWLAN */ -void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason); -void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason); -u32 rtw_ps_deny_get(PADAPTER padapter); - -#if defined(CONFIG_WOWLAN) -void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip); -void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr); -bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, - int *pattern_len, char *bit_mask); -void rtw_wow_pattern_sw_reset(_adapter *adapter); -u8 rtw_set_default_pattern(_adapter *adapter); -void rtw_wow_pattern_sw_dump(_adapter *adapter); -#ifdef CONFIG_WAR_OFFLOAD -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) -void rtw_wow_war_mdns_dump_buf(struct seq_file *m, u8 *title, u8 *buf, u32 len); -void rtw_wow_war_mdns_dump_txt(struct seq_file *m, u8 *title, u8 *buf, u32 len); -bool rtw_wow_war_mdns_parser_pattern(u8 *input, char *target, u32 *target_len, u32 max_len); -void rtw_wow_war_mdns_parms_reset(_adapter *adapter, u8 is_set_default); -#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */ -#endif /* CONFIG_WAR_OFFLOAD */ +void rtw_ps_deny(_adapter *padapter, PS_DENY_REASON reason); +void rtw_ps_deny_cancel(_adapter *padapter, PS_DENY_REASON reason); +u32 rtw_ps_deny_get(_adapter *padapter); -#endif /* CONFIG_WOWLAN */ void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta); void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta); #endif /* __RTL871X_PWRCTRL_H_ */ diff --git a/include/rtw_qos.h b/include/rtw_qos.h index 8e1d013..4dfe956 100644 --- a/include/rtw_qos.h +++ b/include/rtw_qos.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -63,4 +63,4 @@ struct qos_priv { }; -#endif /* _RTL871X_QOS_H_ */ \ No newline at end of file +#endif /* _RTL871X_QOS_H_ */ diff --git a/include/rtw_recv.h b/include/rtw_recv.h index 6433d8e..f5132e8 100644 --- a/include/rtw_recv.h +++ b/include/rtw_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -19,35 +19,11 @@ #define RTW_RX_MSDU_ACT_INDICATE BIT0 #define RTW_RX_MSDU_ACT_FORWARD BIT1 -#ifdef CONFIG_SINGLE_RECV_BUF - #define NR_RECVBUFF (1) -#else - #if defined(CONFIG_GSPI_HCI) - #define NR_RECVBUFF (32) - #elif defined(CONFIG_SDIO_HCI) - #define NR_RECVBUFF (8) - #else - #define NR_RECVBUFF (8) - #endif -#endif /* CONFIG_SINGLE_RECV_BUF */ -#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - #define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1) -#else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */ - #define NR_PREALLOC_RECV_SKB 8 -#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ - #ifdef CONFIG_RTW_NAPI #define RTL_NAPI_WEIGHT (32) #endif -#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE) - #ifdef NR_RECVBUFF - #undef NR_RECVBUFF - #define NR_RECVBUFF (32) - #endif -#endif - #define NR_RECVFRAME 256 #define RXFRAME_ALIGN 8 @@ -66,10 +42,6 @@ #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) -#define RX_MPDU_QUEUE 0 -#define RX_CMD_QUEUE 1 -#define RX_MAX_QUEUE 2 - #define MAX_SUBFRAME_COUNT 64 /* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */ extern u8 rtw_bridge_tunnel_header[]; @@ -79,43 +51,40 @@ enum addba_rsp_ack_state { RTW_RECV_ACK_OR_TIMEOUT, }; +#ifdef RTW_PHL_RX +enum rtw_core_rx_state { + CORE_RX_CONTINUE = _SUCCESS, + CORE_RX_DONE, + CORE_RX_DROP, + CORE_RX_FAIL, +#ifdef CONFIG_RTW_CORE_RXSC + CORE_RX_GO_SHORTCUT, +#endif + CORE_RX_DEFRAG, +}; +#endif + /* for Rx reordering buffer control */ struct recv_reorder_ctrl { _adapter *padapter; u8 tid; u8 enable; u16 indicate_seq;/* =wstart_b, init_value=0xffff */ - u16 wend_b; - u8 wsize_b; u8 ampdu_size; + unsigned long rec_abba_rsp_ack; + + #ifdef CONFIG_RECV_REORDERING_CTRL _queue pending_recvframe_queue; + u8 wsize_b; _timer reordering_ctrl_timer; u8 bReorderWaiting; - unsigned long rec_abba_rsp_ack; + #endif }; struct stainfo_rxcache { u16 tid_rxseq[16]; u8 iv[16][8]; u8 last_tid; -#if 0 - unsigned short tid0_rxseq; - unsigned short tid1_rxseq; - unsigned short tid2_rxseq; - unsigned short tid3_rxseq; - unsigned short tid4_rxseq; - unsigned short tid5_rxseq; - unsigned short tid6_rxseq; - unsigned short tid7_rxseq; - unsigned short tid8_rxseq; - unsigned short tid9_rxseq; - unsigned short tid10_rxseq; - unsigned short tid11_rxseq; - unsigned short tid12_rxseq; - unsigned short tid13_rxseq; - unsigned short tid14_rxseq; - unsigned short tid15_rxseq; -#endif }; @@ -133,22 +102,22 @@ struct signal_stat { u32 total_val; /* sum of valid elements */ }; -struct rx_raw_rssi { - u8 data_rate; - u8 pwdball; - s8 pwr_all; - - u8 mimo_signal_strength[4];/* in 0~100 index */ - u8 mimo_signal_quality[4]; - - s8 ofdm_pwr[4]; - u8 ofdm_snr[4]; +/*TODO get phyinfo from PHL PPDU status - RTW_WKARD_CORE_RSSI_V1*/ +struct phydm_phyinfo_struct { + bool is_valid; + u8 rx_pwdb_all; + u8 signal_quality; /* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */ + + s8 rx_power; /* in dBm Translate from PWdB */ + s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 signal_strength; /* in 0-100 index. */ + s8 rx_pwr[4]; /* per-path's pwdb */ + s8 rx_snr[4]; /* per-path's SNR */ + u8 rx_count:2; /* RX path counter---*/ }; -#include "cmn_info/rtw_sta_info.h" - -struct rx_pkt_attrib { +struct rx_pkt_attrib { u16 pkt_len; u8 physt; u8 drvinfo_sz; @@ -172,6 +141,10 @@ struct rx_pkt_attrib { u8 crc_err; u8 icv_err; +#ifdef CONFIG_RTW_CORE_RXSC + u16 eth_type; +#endif + u8 dst[ETH_ALEN]; u8 src[ETH_ALEN]; u8 ta[ETH_ALEN]; @@ -195,7 +168,6 @@ struct rx_pkt_attrib { u8 ldpc; u8 sgi; u8 pkt_rpt_type; - u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ u8 ampdu; u8 ppdu_cnt; u8 ampdu_eof; @@ -210,6 +182,15 @@ struct rx_pkt_attrib { u8 csum_valid; /* Checksum valid, 0: not check, 1: checked */ u8 csum_err; /* Checksum Error occurs */ #endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */ + +#ifdef RTW_PHL_DBG_CMD + u8 wl_type; + u8 wl_subtype; +#endif +#ifdef CONFIG_RTW_CORE_RXSC + u8 bsnaphdr; +#endif + }; #ifdef CONFIG_RTW_MESH @@ -231,12 +212,7 @@ struct rx_pkt_attrib { #define RECVBUFF_ALIGN_SZ 8 #endif -#ifdef CONFIG_TRX_BD_ARCH - #define RX_WIFI_INFO_SIZE 24 -#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI) - #define RXBD_SIZE sizeof(struct recv_stat) -#endif - +/*GEORGIA_TODO_FIXIT_IC_DEPENDENCE*/ #define RXDESC_SIZE 24 #define RXDESC_OFFSET RXDESC_SIZE @@ -259,7 +235,7 @@ struct recv_stat { unsigned int rxdw1; -#if !((defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI)) /* exclude 8192ee, 8814ae, 8822be, 8821ce */ +#if !(defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* exclude 8822be, 8821ce ,8822ce*/ unsigned int rxdw2; unsigned int rxdw3; @@ -281,26 +257,6 @@ struct recv_stat { #define EOR BIT(30) -#ifdef CONFIG_PCI_HCI -#define PCI_MAX_RX_QUEUE 1/* MSDU packet queue, Rx Command Queue */ -#define PCI_MAX_RX_COUNT 128 -#ifdef CONFIG_TRX_BD_ARCH -#define RX_BD_NUM PCI_MAX_RX_COUNT /* alias */ -#endif - -struct rtw_rx_ring { -#ifdef CONFIG_TRX_BD_ARCH - struct rx_buf_desc *buf_desc; -#else - struct recv_stat *desc; -#endif - dma_addr_t dma; - unsigned int idx; - struct sk_buff *rx_buf[PCI_MAX_RX_COUNT]; -}; -#endif - - /* accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch) @@ -309,47 +265,10 @@ accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(pas using enter_critical section to protect */ -#ifndef DBG_RX_BH_TRACKING -#define DBG_RX_BH_TRACKING 0 -#endif - -struct recv_priv { - _lock lock; - -#ifdef CONFIG_RECV_THREAD_MODE - _sema recv_sema; - -#endif - - /* _queue blk_strms[MAX_RX_NUMBLKS]; */ /* keeping the block ack frame until return ack */ - _queue free_recv_queue; - _queue recv_pending_queue; - _queue uc_swdec_pending_queue; - - - u8 *pallocated_frame_buf; - u8 *precv_frame_buf; - - uint free_recvframe_cnt; - - #if DBG_RX_BH_TRACKING - u32 rx_bh_stage; - u32 rx_bh_buf_dq_cnt; - void *rx_bh_lbuf; - void *rx_bh_cbuf; - void *rx_bh_cbuf_data; - u32 rx_bh_cbuf_dlen; - u32 rx_bh_cbuf_pos; - void *rx_bh_cframe; - #endif - - _adapter *adapter; - - u32 is_any_non_be_pkts; - - u64 rx_bytes; - u64 rx_pkts; - u64 rx_drop; +struct recv_info { + u64 rx_bytes; + u64 rx_pkts; + u64 rx_drop; u64 dbg_rx_drop_count; u64 dbg_rx_ampdu_drop_count; @@ -359,133 +278,32 @@ struct recv_priv { u64 dbg_rx_ampdu_window_shift_cnt; u64 dbg_rx_conflic_mac_addr_cnt; - uint rx_icv_err; - uint rx_largepacket_crcerr; - uint rx_smallpacket_crcerr; - uint rx_middlepacket_crcerr; - -#ifdef CONFIG_USB_HCI - /* u8 *pallocated_urb_buf; */ - _sema allrxreturnevt; - uint ff_hwaddr; - ATOMIC_T rx_pending_cnt; - -#ifdef CONFIG_USB_INTERRUPT_IN_PIPE -#ifdef PLATFORM_LINUX - PURB int_in_urb; -#endif - - u8 *int_in_buf; -#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ - -#endif -#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) - _tasklet irq_prepare_beacon_tasklet; - _tasklet recv_tasklet; - - struct sk_buff_head free_recv_skb_queue; - struct sk_buff_head rx_skb_queue; -#ifdef CONFIG_RTW_NAPI - struct sk_buff_head rx_napi_skb_queue; -#endif -#ifdef CONFIG_RX_INDICATE_QUEUE - _tasklet rx_indicate_tasklet; - struct ifqueue rx_indicate_queue; -#endif /* CONFIG_RX_INDICATE_QUEUE */ - -#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */ - - u8 *pallocated_recv_buf; - u8 *precv_buf; /* 4 alignment */ - _queue free_recv_buf_queue; - u32 free_recv_buf_queue_cnt; - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_USB_HCI) - _queue recv_buf_pending_queue; -#endif - -#if defined(CONFIG_SDIO_HCI) -#ifdef CONFIG_SDIO_RECVBUF_PWAIT - struct rtw_pwait_ctx recvbuf_pwait; -#endif -#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION - bool recvbuf_agg; -#endif -#endif /* CONFIG_SDIO_HCI */ - -#ifdef CONFIG_PCI_HCI - /* Rx */ - struct rtw_rx_ring rx_ring[PCI_MAX_RX_QUEUE]; - int rxringcount; /* size should be PCI_MAX_RX_QUEUE */ - u32 rxbuffersize; -#endif - /* For display the phy informatiom */ u8 is_signal_dbg; /* for debug */ u8 signal_strength_dbg; /* for debug */ + /*RTW_WKARD_CORE_RSSI_V1 - GEORGIA MUST REFINE*/ u8 signal_strength; u8 signal_qual; - s8 rssi; /* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */ - struct rx_raw_rssi raw_rssi_info; - /* s8 rxpwdb; */ - /* int RxSNRdB[2]; */ - /* s8 RxRssi[2]; */ - /* int FalseAlmCnt_all; */ + s8 rssi; /* rtw_phl_rssi_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */ -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + #ifdef CONFIG_SIGNAL_STAT_PROCESS _timer signal_stat_timer; u32 signal_stat_sampling_interval; + #endif + /* u32 signal_stat_converging_constant; */ struct signal_stat signal_qual_data; struct signal_stat signal_strength_data; -#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - struct smooth_rssi_data signal_qual_data; - struct smooth_rssi_data signal_strength_data; -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq; - - BOOLEAN store_law_data_flag; -}; -#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION -#define recv_buf_agg(recvpriv) recvpriv->recvbuf_agg -#ifndef CONFIG_SDIO_RECVBUF_AGGREGATION_EN -#define CONFIG_SDIO_RECVBUF_AGGREGATION_EN 1 -#endif -#else -#define recv_buf_agg(recvpriv) 0 -#endif -#define RX_BH_STG_UNKNOWN 0 -#define RX_BH_STG_HDL_ENTER 1 -#define RX_BH_STG_HDL_EXIT 2 -#define RX_BH_STG_NEW_BUF 3 -#define RX_BH_STG_NEW_FRAME 4 -#define RX_BH_STG_NORMAL_RX 5 -#define RX_BH_STG_NORMAL_RX_END 6 -#define RX_BH_STG_C2H 7 -#define RX_BH_STG_C2H_END 8 - -#if DBG_RX_BH_TRACKING -void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s); -void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen); -void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos); -void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame); -void dump_rx_bh_tk(void *sel, struct recv_priv *recv); -#else -#define rx_bh_tk_set_stage(recv, s) do {} while (0) -#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0) -#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0) -#define rx_bh_tk_set_frame(recv, frame) do {} while (0) -#define dump_rx_bh_tk(sel, recv) do {} while (0) + u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq; +}; +#ifdef CONFIG_SIGNAL_STAT_PROCESS +#define rtw_set_signal_stat_timer(recvinfo) _set_timer(&(recvinfo)->signal_stat_timer, (recvinfo)->signal_stat_sampling_interval) #endif -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS -#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) -#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - struct sta_recv_priv { _lock lock; @@ -505,25 +323,15 @@ struct sta_recv_priv { }; - -#define RBUF_TYPE_PREALLOC 0 -#define RBUF_TYPE_TMP 1 -#define RBUF_TYPE_PWAIT_ADJ 2 - +#if 0 struct recv_buf { _list list; -#ifdef PLATFORM_WINDOWS _lock recvbuf_lock; -#endif - -#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST - u8 type; -#endif u32 ref_cnt; - PADAPTER adapter; + _adapter *adapter; u8 *pbuf; u8 *pallocated_buf; @@ -542,40 +350,16 @@ struct recv_buf { u8 irp_pending; int transfer_len; #endif - -#if defined(PLATFORM_LINUX) - _pkt *pskb; -#elif defined(PLATFORM_FREEBSD) /* skb solution */ struct sk_buff *pskb; -#endif }; - -#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST -#define RBUF_IS_PREALLOC(rbuf) ((rbuf)->type == RBUF_TYPE_PREALLOC) -#else -#define RBUF_IS_PREALLOC(rbuf) 1 #endif -/* - head -----> - - data -----> - - payload - - tail -----> - - - end -----> - - len = (unsigned int )(tail - data); - -*/ struct recv_frame_hdr { _list list; - _pkt *pkt; + struct sk_buff *pkt; _adapter *adapter; + struct dvobj_priv *dvobj; u8 fragcnt; @@ -594,9 +378,16 @@ struct recv_frame_hdr { /* */ struct sta_info *psta; - +#ifdef CONFIG_RECV_REORDERING_CTRL /* for A-MPDU Rx reordering buffer control */ struct recv_reorder_ctrl *preorder_ctrl; +#endif +#ifdef RTW_PHL_RX + void *rx_req; +#endif +#ifdef CONFIG_RTW_CORE_RXSC + struct core_rxsc_entry *rxsc_entry; +#endif #ifdef CONFIG_WAPI_SUPPORT u8 UserPriority; @@ -610,15 +401,12 @@ struct recv_frame_hdr { union recv_frame { - union { _list list; struct recv_frame_hdr hdr; uint mem[RECVFRAME_HDR_ALIGN >> 2]; } u; - /* uint mem[MAX_RXSZ>>2]; */ - }; enum rtw_rx_llc_hdl { @@ -627,47 +415,71 @@ enum rtw_rx_llc_hdl { RTW_RX_LLC_VLAN = 2, }; -bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset); +struct recv_priv { + struct dvobj_priv *dvobj; -typedef enum _RX_PACKET_TYPE { - NORMAL_RX,/* Normal rx packet */ - TX_REPORT1,/* CCX */ - TX_REPORT2,/* TX RPT */ - HIS_REPORT,/* USB HISR RPT */ - C2H_PACKET -} RX_PACKET_TYPE, *PRX_PACKET_TYPE; + #ifdef CONFIG_RECV_THREAD_MODE + _sema recv_sema; + #endif + _queue free_recv_queue; /*recv_frame*/ + #if 0 + _queue uc_swdec_pending_queue; + #endif -extern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */ -extern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */ -extern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv); -extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); + u8 *pallocated_frame_buf; + u8 *precv_frame_buf; -#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) -extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); -extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); + uint free_recvframe_cnt; + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) +#ifdef CONFIG_RTW_NAPI + struct sk_buff_head rx_napi_skb_queue; +#endif +#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */ -extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); -u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter); +}; -sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); -sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); -struct recv_buf *rtw_dequeue_recvbuf(_queue *queue); +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset); +#ifdef RTW_PHL_RX +extern void dump_recv_frame(_adapter *adapter, union recv_frame *prframe); +extern sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame); +extern s32 rtw_core_rx_data_pre_process(_adapter *adapter, union recv_frame **prframe); +extern s32 rtw_core_rx_data_post_process(_adapter *adapter, union recv_frame *prframe); +enum rtw_phl_status rtw_core_rx_process(void *drv_priv); void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta); void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta); +#ifdef CONFIG_RTW_CORE_RXSC +sint recv_ucast_pn_decache(union recv_frame *precv_frame); +sint recv_bcast_pn_decache(union recv_frame *precv_frame); +#endif /* CONFIG_RTW_CORE_RXSC */ +#endif + +extern void rtw_init_recvframe(union recv_frame *precvframe); +extern int rtw_free_recvframe(union recv_frame *precvframe); +union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue); + +#if 0 +u32 rtw_free_uc_swdec_pending_queue(struct dvobj_priv *dvobj); +#endif #if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) void rtw_reordering_ctrl_timeout_handler(void *pcontext); #endif +#if 0 void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); +#endif + int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index); #ifdef CONFIG_RECV_THREAD_MODE thread_return rtw_recv_thread(thread_context context); #endif - +#ifdef RTW_WKARD_CORE_RSSI_V1 +void rx_process_phy_info(union recv_frame *precvframe); +#endif __inline static u8 *get_rxmem(union recv_frame *precvframe) { /* always return rx_head... */ @@ -799,70 +611,22 @@ __inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) } -__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) -{ - /* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */ - /* from any given member of recv_frame. */ - /* rxmem indicates the any member/address in recv_frame */ - - return (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); - -} - -__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt) -{ - - u8 *buf_star = NULL; - union recv_frame *precv_frame; - precv_frame = rxmem_to_recvframe((unsigned char *)buf_star); - - return precv_frame; -} - -__inline static u8 *pkt_to_recvmem(_pkt *pkt) -{ - /* return the rx_head */ - - union recv_frame *precv_frame = pkt_to_recvframe(pkt); - - return precv_frame->u.hdr.rx_head; - -} - -__inline static u8 *pkt_to_recvdata(_pkt *pkt) -{ - /* return the rx_data */ - - union recv_frame *precv_frame = pkt_to_recvframe(pkt); - - return precv_frame->u.hdr.rx_data; - -} - - __inline static sint get_recvframe_len(union recv_frame *precvframe) { return precvframe->u.hdr.len; } -__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) -{ - s32 SignalPower; /* in dBm. */ - - /* Translate to dBm (x=y-100) */ - SignalPower = SignalStrengthIndex - 100; - return SignalPower; -} - struct sta_info; - extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); u8 adapter_allow_bmc_data_rx(_adapter *adapter); +#if 0 s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status); +#endif void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta); - +u8 rtw_init_lite_recv_resource(struct dvobj_priv *dvobj); +void rtw_free_lite_recv_resource(struct dvobj_priv *dvobj); #endif diff --git a/include/rtw_recv_shortcut.h b/include/rtw_recv_shortcut.h new file mode 100644 index 0000000..2dc9886 --- /dev/null +++ b/include/rtw_recv_shortcut.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef _RTW_RECV_SHORTCUT_H_ +#define _RTW_RECV_SHORTCUT_H_ + +#ifdef CONFIG_RTW_CORE_RXSC + +#define NUM_RXSC_ENTRY 4 + +enum rxsc_entry_status { + RXSC_ENTRY_INVALID = 0, + RXSC_ENTRY_VALID, + RXSC_ENTRY_APPLYING, +}; + +struct rxsc_wlan_hdr { + unsigned short fmctrl; + unsigned short duration; + unsigned char addr1[ETH_ALEN]; + unsigned char addr2[ETH_ALEN]; + unsigned char addr3[ETH_ALEN]; + unsigned short sequence; + unsigned char addr4[ETH_ALEN]; + unsigned short qosctrl; + unsigned char iv[8]; +}; + +struct core_rxsc_entry { + u8 status; + u32 rxsc_payload_offset; + u32 rxsc_trim_pad; + + struct rxsc_wlan_hdr rxsc_wlanhdr; + struct ethhdr rxsc_ethhdr; + struct rx_pkt_attrib rxsc_attrib; + + u8 rxsc_wd[64]; +}; + +struct core_rxsc_entry *core_rxsc_alloc_entry(_adapter *adapter, union recv_frame *prframe); +s32 core_rxsc_apply_check(_adapter *adapter, union recv_frame *prframe); +s32 core_rxsc_apply_shortcut(_adapter *adapter, union recv_frame *prframe); +void core_rxsc_clear_entry(_adapter *adapter, struct sta_info *psta); + +#endif /* CONFIG_RTW_CORE_RXSC */ +#endif /* _RTW_RECV_SHORTCUT_H_ */ + diff --git a/include/rtw_rf.h b/include/rtw_rf.h index 3a24929..d721003 100644 --- a/include/rtw_rf.h +++ b/include/rtw_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -23,17 +23,35 @@ #define SHORT_SLOT_TIME 9 #define NON_SHORT_SLOT_TIME 20 -#define CENTER_CH_2G_40M_NUM 9 #define CENTER_CH_2G_NUM 14 +#define CENTER_CH_2G_40M_NUM 9 + #define CENTER_CH_5G_20M_NUM 28 /* 20M center channels */ #define CENTER_CH_5G_40M_NUM 14 /* 40M center channels */ #define CENTER_CH_5G_80M_NUM 7 /* 80M center channels */ #define CENTER_CH_5G_160M_NUM 3 /* 160M center channels */ #define CENTER_CH_5G_ALL_NUM (CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM) -#define MAX_CHANNEL_NUM_2G CENTER_CH_2G_NUM -#define MAX_CHANNEL_NUM_5G CENTER_CH_5G_20M_NUM -#define MAX_CHANNEL_NUM (MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G) +#define CENTER_CH_6G_20M_NUM 64 /* 20M center channels */ +#define CENTER_CH_6G_40M_NUM 32 /* 40M center channels */ +#define CENTER_CH_6G_80M_NUM 16 /* 80M center channels */ +#define CENTER_CH_6G_160M_NUM 8 /* 160M center channels */ + +#define MAX_CHANNEL_NUM_2G CENTER_CH_2G_NUM +#define MAX_CHANNEL_NUM_5G CENTER_CH_5G_20M_NUM +#define MAX_CHANNEL_NUM_6G CENTER_CH_6G_20M_NUM +#define MAX_CHANNEL_NUM_2G_5G (MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G) + +#define MAX_CHANNEL_NUM ( \ + MAX_CHANNEL_NUM_2G \ + + (CONFIG_IEEE80211_BAND_5GHZ ? MAX_CHANNEL_NUM_5G : 0) \ + + (CONFIG_IEEE80211_BAND_6GHZ ? MAX_CHANNEL_NUM_6G : 0) \ + ) + +/* +* MAX_CHANNEL_NUM_OF_BAND is used by op_class_pref_t only. +* TODO: consider 6G band or remove this after allocate op_class_pref_t dynamically +*/ #define MAX_CHANNEL_NUM_OF_BAND rtw_max(MAX_CHANNEL_NUM_2G, MAX_CHANNEL_NUM_5G) extern u8 center_ch_2g[CENTER_CH_2G_NUM]; @@ -52,7 +70,6 @@ u8 center_chs_5g_num(u8 bw); u8 center_chs_5g(u8 bw, u8 id); u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset); -u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch); u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num); @@ -88,17 +105,6 @@ enum _REG_PREAMBLE_MODE { #define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path)) -/* Bandwidth Offset */ -#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 -#define HAL_PRIME_CHNL_OFFSET_LOWER 1 -#define HAL_PRIME_CHNL_OFFSET_UPPER 2 - -typedef enum _BAND_TYPE { - BAND_ON_2_4G = 0, - BAND_ON_5G = 1, - BAND_MAX, -} BAND_TYPE, *PBAND_TYPE; - #ifdef CONFIG_NARROWBAND_SUPPORTING enum nb_config { RTW_NB_CONFIG_NONE = 0, @@ -107,8 +113,8 @@ enum nb_config { }; #endif -extern const char *const _band_str[]; -#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)]) +extern const char *const _rtw_band_str[]; +#define band_str(band) (((band) >= BAND_MAX) ? _rtw_band_str[BAND_MAX] : _rtw_band_str[(band)]) extern const u8 _band_to_band_cap[]; #define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)]) @@ -152,7 +158,7 @@ struct op_ch_t { struct op_class_pref_t { u8 class_id; - BAND_TYPE band; + enum band_type band; enum opc_bw bw; u8 ch_num; /* number of chs */ u8 op_ch_num; /* channel number which is not static non operable */ @@ -174,17 +180,6 @@ void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail); void dump_reg_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail); void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail); -/* - * Represent Extention Channel Offset in HT Capabilities - * This is available only in 40Mhz mode. - * */ -typedef enum _EXTCHNL_OFFSET { - EXTCHNL_OFFSET_NO_EXT = 0, - EXTCHNL_OFFSET_UPPER = 1, - EXTCHNL_OFFSET_NO_DEF = 2, - EXTCHNL_OFFSET_LOWER = 3, -} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET; - typedef enum _VHT_DATA_SC { VHT_DATA_SC_DONOT_CARE = 0, VHT_DATA_SC_20_UPPER_OF_80MHZ = 1, @@ -205,6 +200,15 @@ typedef enum _PROTECTION_MODE { PROTECTION_MODE_FORCE_DISABLE = 2, } PROTECTION_MODE, *PPROTECTION_MODE; +typedef enum _RF_TX_NUM { + RF_1TX = 0, + RF_2TX, + RF_3TX, + RF_4TX, + RF_MAX_TX_NUM, + RF_TX_NUM_NONIMPLEMENT, +} RF_TX_NUM; + #define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX) extern const u8 _rf_type_to_rf_tx_cnt[]; @@ -216,41 +220,24 @@ extern const u8 _rf_type_to_rf_rx_cnt[]; extern const char *const _rf_type_to_rfpath_str[]; #define rf_type_to_rfpath_str(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rfpath_str[rf_type] : "UNKNOWN") -void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx); - enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num); enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp); bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b); -u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num); u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num); -void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath); -void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath); + +#if CONFIG_IEEE80211_BAND_6GHZ +int rtw_6gch2freq(int chan); +#endif int rtw_ch2freq(int chan); +int rtw_ch2freq_by_band(enum band_type band, int ch); int rtw_freq2ch(int freq); +enum band_type rtw_freq2band(int freq); +bool rtw_freq_consecutive(int a, int b); bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); struct rf_ctl_t; -typedef enum _REGULATION_TXPWR_LMT { - TXPWR_LMT_NONE = 0, /* no limit */ - TXPWR_LMT_FCC = 1, - TXPWR_LMT_MKK = 2, - TXPWR_LMT_ETSI = 3, - TXPWR_LMT_IC = 4, - TXPWR_LMT_KCC = 5, - TXPWR_LMT_NCC = 6, - TXPWR_LMT_ACMA = 7, - TXPWR_LMT_CHILE = 8, - TXPWR_LMT_UKRAINE = 9, - TXPWR_LMT_MEXICO = 10, - TXPWR_LMT_CN = 11, - TXPWR_LMT_WW, /* smallest of all available limit, keep last */ -} REGULATION_TXPWR_LMT; - -extern const char *const _regd_str[]; -#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)]) - void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len); #define MBM_PDBM 100 @@ -260,49 +247,10 @@ void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_le s16 mb_of_ntx(u8 ntx); #if CONFIG_TXPWR_LIMIT -struct regd_exc_ent { - _list list; - char country[2]; - u8 domain; - char regd_name[0]; -}; - void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl); -void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen); -void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name); -struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); -struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); -void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl); - void dump_txpwr_lmt(void *sel, _adapter *adapter); -void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen - , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); -void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name - , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); -struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); -struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); -void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl); -#endif /* CONFIG_TXPWR_LIMIT */ - -#define BB_GAIN_2G 0 -#if CONFIG_IEEE80211_BAND_5GHZ -#define BB_GAIN_5GLB1 1 -#define BB_GAIN_5GLB2 2 -#define BB_GAIN_5GMB1 3 -#define BB_GAIN_5GMB2 4 -#define BB_GAIN_5GHB 5 -#endif - -#if CONFIG_IEEE80211_BAND_5GHZ -#define BB_GAIN_NUM 6 -#else -#define BB_GAIN_NUM 1 #endif -int rtw_ch_to_bb_gain_sel(int ch); -void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); -void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); - /* only check channel ranges */ #define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14) #define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177) @@ -320,6 +268,11 @@ void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); || (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \ || (rtw_is_5g_band4(a) && rtw_is_5g_band4(b))) +#define rtw_is_6g_band1(ch) ((ch) >= 1 && (ch) <= 93) +#define rtw_is_6g_band2(ch) ((ch) >= 97 && (ch) <= 117) +#define rtw_is_6g_band3(ch) ((ch) >= 121 && (ch) <= 189) +#define rtw_is_6g_band4(ch) ((ch) >= 193 && (ch) <= 237) + bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region); bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region); diff --git a/include/rtw_rm.h b/include/rtw_rm.h index 8aa2b9d..39f6012 100644 --- a/include/rtw_rm.h +++ b/include/rtw_rm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -66,8 +66,8 @@ struct rm_priv { struct rm_clock clock[RM_TIMER_NUM]; u8 rm_en_cap_def[5]; u8 rm_en_cap_assoc[5]; - u8 meas_token; + /* rm debug */ void *prm_sel; }; @@ -84,14 +84,15 @@ int rtw_free_rm_priv(_adapter *padapter); unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame); void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void update_rm_cap(u8 *frame_head, _adapter *pa, u32 pktlen, int offset); void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter, struct sta_info *psta, struct rtw_ieee802_11_elems *elems); int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid); void rm_handler(_adapter *padapter, struct rm_event *pev); +int rm_get_chset(struct rm_obj *prm); u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta); - /* from ioctl */ int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch, u16 measure_duration, u8 measure_mode, u8 *bssid, u8 *ssid, @@ -100,6 +101,9 @@ int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch, u8 n_elem_id, u8 *elem_id_list); void indicate_beacon_report(u8 *sta_addr, u8 n_measure_rpt, u32 elem_len, u8 *elem); +#else +#define RM_IE_handler(a, b) do{} while (0) +#define update_rm_cap(a, b, c, d) do{} while(0) #endif /*CONFIG_RTW_80211K */ #endif /* __RTW_RM_H_ */ diff --git a/include/rtw_rm_fsm.h b/include/rtw_rm_fsm.h index bbbb3d9..f58950a 100644 --- a/include/rtw_rm_fsm.h +++ b/include/rtw_rm_fsm.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -284,7 +284,6 @@ struct rm_obj { u64 meas_end_time; int wait_busy; u8 poll_mode; - u8 free_run_counter_valid; /* valid:_SUCCESS/invalid:_FAIL */ struct data_buf buf[MAX_BUF_NUM]; bool from_ioctl; diff --git a/include/rtw_rm_util.h b/include/rtw_rm_util.h index 932cfb9..6fd532e 100644 --- a/include/rtw_rm_util.h +++ b/include/rtw_rm_util.h @@ -28,8 +28,8 @@ u8 rm_get_oper_class_via_ch(u8 ch); u8 rm_get_ch_set( struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num); -u8 rm_get_ch_set_from_bcn_req_opt( - struct rtw_ieee80211_channel *pch_set, struct bcn_req_opt *opt); +u8 rm_get_ch_set_from_bcn_req_opt( struct rtw_ieee80211_channel *pch_set, + struct bcn_req_opt *opt); u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork); u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork); u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe); @@ -41,7 +41,7 @@ u32 rm_gen_rmid(_adapter *padapter, struct rm_obj *prm, u8 role); int is_wildcard_bssid(u8 *bssid); int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a); -int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr); -int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr); +int rm_get_tx_power(_adapter *adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr); +int rm_get_rx_sensitivity(_adapter *adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr); #endif /* _RTW_RM_UTIL_H_ */ diff --git a/include/rtw_scan.h b/include/rtw_scan.h new file mode 100644 index 0000000..20d6478 --- /dev/null +++ b/include/rtw_scan.h @@ -0,0 +1,288 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_SCAN_H_ +#define __RTW_SCAN_H_ + +/*rtw_mlme.h*/ +void rtw_drv_scan_by_self(_adapter *padapter, u8 reason); +void rtw_scan_abort_no_wait(_adapter *adapter); +u32 rtw_scan_abort(_adapter *adapter, u32 timeout_ms); +void rtw_scan_timeout_handler(void *ctx); +void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); + +enum { + SS_DENY_MP_MODE, + SS_DENY_RSON_SCANING, + SS_DENY_BLOCK_SCAN, + SS_DENY_BY_DRV, + SS_DENY_SELF_AP_UNDER_WPS, + SS_DENY_SELF_AP_UNDER_LINKING, + SS_DENY_SELF_AP_UNDER_SURVEY, + /*SS_DENY_SELF_STA_UNDER_WPS,*/ + SS_DENY_SELF_STA_UNDER_LINKING, + SS_DENY_SELF_STA_UNDER_SURVEY, + SS_DENY_BUDDY_UNDER_LINK_WPS, + SS_DENY_BUDDY_UNDER_SURVEY, + SS_DENY_BUSY_TRAFFIC, + SS_ALLOW, +#ifdef DBG_LA_MODE + SS_DENY_LA_MODE, +#endif + SS_DENY_ADAPTIVITY, +}; +u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval); +#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval) + +#ifdef CONFIG_SET_SCAN_DENY_TIMER +bool rtw_is_scan_deny(_adapter *adapter); +void rtw_clear_scan_deny(_adapter *adapter); +void rtw_set_scan_deny_timer_hdl(void *ctx); +void rtw_set_scan_deny(_adapter *adapter, u32 ms); +#else +#define rtw_is_scan_deny(adapter) _FALSE +#define rtw_clear_scan_deny(adapter) do {} while (0) +#define rtw_set_scan_deny(adapter, ms) do {} while (0) +#endif + +#ifdef CONFIG_RTW_ACS +u8 rtw_set_acs_sitesurvey(_adapter *adapter); +#endif + +/*rtw_mlme_ext.h*/ +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state); + +/*const char *scan_state_str(u8 state);*/ +#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) +/*#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state)*/ +#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state)) +#define mlmeext_set_scan_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.state = (_state)); \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \ + /* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \ + sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \ + } while (0) + +#if 0 +#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) +#define mlmeext_set_scan_next_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + /* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \ + } while (0) +#endif +#ifdef CONFIG_SCAN_BACKOP +#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags) +#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags)) +#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags = (flags)); \ + RTW_INFO("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \ + } while (0) + +#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta) +#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags)) +#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \ + } while (0) +#else +#define mlmeext_scan_backop_flags(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0) + +#define mlmeext_scan_backop_flags_sta(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0) +#endif /* CONFIG_SCAN_BACKOP */ + +#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) +#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags)) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \ + } while (0) +#else +#define mlmeext_scan_backop_flags_ap(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) +#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */ + +#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) +#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh) +#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags)) +#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \ + } while (0) +#else +#define mlmeext_scan_backop_flags_mesh(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0) +#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */ + +#if 0 +void survey_timer_hdl(void *ctx); +#define set_survey_timer(mlmeext, ms) \ + do { \ + /*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->survey_timer, (ms)); \ + } while (0) +#define cancel_survey_timer(mlmeext) \ + do { \ + /*RTW_INFO("%s cancel_survey_timer(%p)\n", __FUNCTION__, (mlmeext));*/ \ + _cancel_timer_ex(&(mlmeext)->survey_timer); \ + } while (0) +#endif + +enum SCAN_STATE { + SCAN_DISABLE = 0, + SCAN_START = 1, + SCAN_PS_ANNC_WAIT = 2, + SCAN_ENTER = 3, + SCAN_PROCESS = 4, + + /* backop */ + SCAN_BACKING_OP = 5, + SCAN_BACK_OP = 6, + SCAN_LEAVING_OP = 7, + SCAN_LEAVE_OP = 8, + + /* SW antenna diversity (before linked) */ + SCAN_SW_ANTDIV_BL = 9, + + /* legacy p2p */ + SCAN_TO_P2P_LISTEN = 10, + SCAN_P2P_LISTEN = 11, + + SCAN_COMPLETE = 12, + SCAN_STATE_MAX, +}; + + +enum ss_backop_flag { + SS_BACKOP_EN = BIT0, /* backop when linked */ + SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */ + + SS_BACKOP_PS_ANNC = BIT4, + SS_BACKOP_TX_RESUME = BIT5, +}; + +#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */ +#define RTW_CHANNEL_SCAN_AMOUNT (14+37) + +struct ss_res { + u8 state; + u8 next_state; /* will set to state on next cmd hdl */ + int bss_cnt; + u8 activate_ch_cnt; + #ifdef CONFIG_CMD_SCAN + struct rtw_phl_scan_param *scan_param; + #endif + struct submit_ctx sctx; + + u16 scan_ch_ms; + u32 scan_timeout_ms; + u8 rx_ampdu_accept; + u8 rx_ampdu_size; +#if 0 + int channel_idx; + u8 force_ssid_scan; + int scan_mode; + u8 igi_scan; + u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ +#endif + +#ifdef CONFIG_SCAN_BACKOP + u8 backop_flags_sta; /* policy for station mode*/ + #ifdef CONFIG_AP_MODE + u8 backop_flags_ap; /* policy for ap mode */ + #endif + #ifdef CONFIG_RTW_MESH + u8 backop_flags_mesh; /* policy for mesh mode */ + #endif + u8 backop_flags; /* per backop runtime decision */ + #if 0 + u8 scan_cnt; + #endif + u8 scan_cnt_max; + systime backop_time; /* the start time of backop */ + u16 backop_ms; +#endif +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + u8 is_sw_antdiv_bl_scan; +#endif + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 token; /* 0: use to identify caller */ + u16 duration; /* 0: use default */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ + + bool acs; /* aim to trigger channel selection when scan done */ +}; + +enum rtw_scan_type { + RTW_SCAN_NORMAL, + RTW_SCAN_P2P, + RTW_SCAN_RRM +}; + +struct sitesurvey_parm { + enum rtw_phl_scan_type scan_mode; /* active: 1, passive: 0 */ + /* sint bsslimit; // 1 ~ 48 */ + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 rrm_token; /* 80211k use it to identify caller */ + u16 duration; /* 0: use default, otherwise: channel scan time */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ + + bool acs; /* aim to trigger channel selection when scan done */ + + enum rtw_scan_type scan_type; +}; + +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm); +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm); +#ifndef CONFIG_CMD_SCAN +u32 rtw_site_survey_fsm(_adapter *padapter, struct cmd_obj *pcmd); +#endif + +#if 1 /*#ifndef CONFIG_PHL_ARCH*/ +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); +void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +#endif + +#ifdef CONFIG_IOCTL_CFG80211 +u8 rtw_phl_remain_on_ch_cmd(_adapter *padapter, u64 cookie, struct wireless_dev *wdev, + struct ieee80211_channel *ch, u8 ch_type, unsigned int duration, + struct back_op_param *bkop_parm, u8 is_p2p); +#endif + +#ifdef CONFIG_STA_CMD_DISPR +u8 scan_issu_null_data_cb(void *priv, u8 ridx, bool ps); +#endif + +#endif /* __RTW_SCAN_H_ */ diff --git a/include/rtw_sdio.h b/include/rtw_sdio.h index 7490b54..917424f 100644 --- a/include/rtw_sdio.h +++ b/include/rtw_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2017 Realtek Corporation. + * Copyright(c) 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -22,5 +22,7 @@ u8 rtw_sdio_read_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len); u8 rtw_sdio_write_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len); u8 rtw_sdio_write_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len); u8 rtw_sdio_f0_read(struct dvobj_priv *, u32 addr, void *buf, size_t len); +size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len); + #endif /* _RTW_SDIO_H_ */ diff --git a/include/rtw_sec_cam.h b/include/rtw_sec_cam.h new file mode 100644 index 0000000..1d3defe --- /dev/null +++ b/include/rtw_sec_cam.h @@ -0,0 +1,203 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_SEC_CAM_H__ +#define __RTW_SEC_CAM_H__ + +#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0 + +struct sec_cam_bmp { + u32 m0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + u32 m1; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + u32 m2; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + u32 m3; +#endif +}; + +struct cam_ctl_t { + _lock lock; + + u8 sec_cap; + u32 flags; + + u8 num; + struct sec_cam_bmp used; + + _mutex sec_cam_access_mutex; +}; + +struct sec_cam_ent { + u16 ctrl; + u8 mac[ETH_ALEN]; + u8 key[16]; +}; + +bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap); +void _rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +void rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags); + +void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num); +void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id); +void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id); +void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); + +bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id); + +bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used); +void rtw_camid_free(_adapter *adapter, u8 cam_id); +u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id); + +void _clear_cam_entry(_adapter *padapter, u8 entry); +void write_cam_from_cache(_adapter *adapter, u8 id); +void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b); +void rtw_clean_dk_section(_adapter *adapter); +void rtw_clean_hw_dk_cam(_adapter *adapter); + +/* modify both HW and cache */ +void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_entry(_adapter *padapter, u8 id); + +/* modify cache only */ +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_cache(_adapter *adapter, u8 id); + +void invalidate_cam_all(_adapter *padapter); + +void flush_all_cam_entry(_adapter *padapter, enum phl_cmd_type cmd_type, u32 cmd_timeout); + +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter); +#endif + +#ifdef CONFIG_DBG_AX_CAM + +#define INDIRECT_ACCESS_ADDR 0xC04 +#define INDIRECT_ACCESS_VALUE 0x40000 +#define SEC_CAM_BASE_ADDR 0x18814000 +#define BSSID_CAM_BASE_ADDR 0x18853000 +#define ADDR_CAM_BASE_ADDR 0x18850000 + +enum CAM_KEY_TYPE { + KEY_TYPE_UNI = 0, + KEY_TYPE_GROUP = 1, + KEY_TYPE_BIP = 2, + KEY_TYPE_NONE = 3 +}; + +/*Address cam field info DW0 - DW9*/ + +/* DWORD 0 ; Offset 00h */ +#define GET_AX_ADDR_CAM_VALID(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 0, 1) +#define GET_AX_ADDR_CAM_NET_TYPE(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 1, 2) +#define GET_AX_ADDR_CAM_BCN_HD_COND(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 3, 2) +#define GET_AX_ADDR_CAM_HIT_RULE(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 5, 2) +#define GET_AX_ADDR_CAM_BB_SEL(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 7, 1) +#define GET_AX_ADDR_CAM_ADDR_MASK(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 8, 6) +#define GET_AX_ADDR_CAM_MASK_SEL(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 14, 2) +#define GET_AX_ADDR_CAM_SMA_HASH(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 16, 8) +#define GET_AX_ADDR_CAM_TMA_HASH(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 24, 8) + +/* DWORD 1 ; Offset 04h */ +#define GET_AX_ADDR_CAM_BSSID_CAM_IDX(__pCAM) LE_BITS_TO_4BYTE(__pCAM+4, 0, 6) +/* DWORD 2 ; Offset 08h */ +#define GET_AX_ADDR_CAM_SMA_0(__pCAM) LE_BITS_TO_4BYTE(__pCAM+8, 0, 8) +#define GET_AX_ADDR_CAM_SMA_1(__pCAM) LE_BITS_TO_4BYTE(__pCAM+8, 8, 8) +#define GET_AX_ADDR_CAM_SMA_2(__pCAM) LE_BITS_TO_4BYTE(__pCAM+8, 16, 8) +#define GET_AX_ADDR_CAM_SMA_3(__pCAM) LE_BITS_TO_4BYTE(__pCAM+8, 24, 8) +/* DWORD 3 ; Offset 0Ch */ +#define GET_AX_ADDR_CAM_SMA_4(__pCAM) LE_BITS_TO_4BYTE(__pCAM+12, 8, 6) +#define GET_AX_ADDR_CAM_SMA_5(__pCAM) LE_BITS_TO_4BYTE(__pCAM+12, 14, 2) +#define GET_AX_ADDR_CAM_TMA_0(__pCAM) LE_BITS_TO_4BYTE(__pCAM+12, 16, 8) +#define GET_AX_ADDR_CAM_TMA_1(__pCAM) LE_BITS_TO_4BYTE(__pCAM+12, 24, 8) +/* DWORD 4 ; Offset 10h */ +#define GET_AX_ADDR_CAM_TMA_2(__pCAM) LE_BITS_TO_4BYTE(__pCAM+16, 0, 8) +#define GET_AX_ADDR_CAM_TMA_3(__pCAM) LE_BITS_TO_4BYTE(__pCAM+16, 8, 8) +#define GET_AX_ADDR_CAM_TMA_4(__pCAM) LE_BITS_TO_4BYTE(__pCAM+16, 16, 8) +#define GET_AX_ADDR_CAM_TMA_5(__pCAM) LE_BITS_TO_4BYTE(__pCAM+16, 24, 8) +/* DWORD 5 ; Offset 14h : RSVD ALL*/ +/* DWORD 6 ; Offset 18h */ + +#define GET_AX_ADDR_CAM_MACID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 0, 8) +#define GET_AX_ADDR_CAM_PORT_INT(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 8, 3) +#define GET_AX_ADDR_CAM_TSF_SYNC(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 11, 3) +#define GET_AX_ADDR_CAM_TF(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 14, 2) +#define GET_AX_ADDR_CAM_LSIG_TXOP(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 16, 2) +#define GET_AX_ADDR_CAM_CTRLCNT_IDX(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 18, 4) +#define GET_AX_ADDR_CAM_CTRLCNT_VALID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 20, 1) +#define GET_AX_ADDR_CAM_TARGET_IND(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 24, 3) +#define GET_AX_ADDR_CAM_FRM_TARGET_IND(__pCAM) LE_BITS_TO_4BYTE(__pCAM+24, 27, 3) + +/* DWORD 7 ; Offset 1Ch */ +#define GET_AX_ADDR_CAM_AID12_0(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 0, 8) +#define GET_AX_ADDR_CAM_AID12_1(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 8, 4) +#define GET_AX_ADDR_CAM_WOL_PATTERN(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 12, 1) +#define GET_AX_ADDR_CAM_WOL_UC(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 13, 1) +#define GET_AX_ADDR_CAM_WOL_MAGIC(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 14, 1) +#define GET_AX_ADDR_CAM_WAPI(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 15, 1) +#define GET_AX_ADDR_CAM_SEC_ENT_MODE(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 16, 2) +#define GET_AX_ADDR_CAM_SEC_ENT0_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 18, 2) +#define GET_AX_ADDR_CAM_SEC_ENT1_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 20, 2) +#define GET_AX_ADDR_CAM_SEC_ENT2_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 22, 2) +#define GET_AX_ADDR_CAM_SEC_ENT3_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 24, 2) +#define GET_AX_ADDR_CAM_SEC_ENT4_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 26, 2) +#define GET_AX_ADDR_CAM_SEC_ENT5_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 28, 2) +#define GET_AX_ADDR_CAM_SEC_ENT6_KEYID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+28, 30, 2) +/* DWORD 8 ; Offset 20h */ +#define GET_AX_ADDR_CAM_SEC_ENT_VALID(__pCAM) LE_BITS_TO_4BYTE(__pCAM+32, 0, 8) +#define GET_AX_ADDR_CAM_SEC_ENT0(__pCAM) LE_BITS_TO_4BYTE(__pCAM+32, 8, 8) +#define GET_AX_ADDR_CAM_SEC_ENT1(__pCAM) LE_BITS_TO_4BYTE(__pCAM+32, 16, 8) +#define GET_AX_ADDR_CAM_SEC_ENT2(__pCAM) LE_BITS_TO_4BYTE(__pCAM+32, 24, 8) +/* DWORD 9 ; Offset 24h */ +#define GET_AX_ADDR_CAM_SEC_ENT3(__pCAM) LE_BITS_TO_4BYTE(__pCAM+36, 0, 8) +#define GET_AX_ADDR_CAM_SEC_ENT4(__pCAM) LE_BITS_TO_4BYTE(__pCAM+36, 8, 8) +#define GET_AX_ADDR_CAM_SEC_ENT5(__pCAM) LE_BITS_TO_4BYTE(__pCAM+36, 16, 8) +#define GET_AX_ADDR_CAM_SEC_ENT6(__pCAM) LE_BITS_TO_4BYTE(__pCAM+36, 24, 8) + +/* Security cam */ +/*DWORD 0 ; offset 00h*/ +#define GET_AX_SEC_CAM_TYPE(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 0, 4) +#define GET_AX_SEC_CAM_EXT_KEY(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 4, 1) +#define GET_AX_SEC_SPP_MODE_(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 5, 1) + +/*BSSID cam*/ +/*DWORD 0 ; offset 00h*/ +#define GET_AX_BSSID_CAM_VALID(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 0, 1) +#define GET_AX_BSSID_CAM_BB_SEL(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 1, 1) +#define GET_AX_BSSID_CAM_COLOR_(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 8, 6) +#define GET_AX_BSSID_CAM_BSSID_0(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 16, 8) +#define GET_AX_BSSID_CAM_BSSID_1(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 24, 8) +/*DWORD 1 ; offset 04h*/ +#define GET_AX_BSSID_CAM_BSSID_2(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 0, 8) +#define GET_AX_BSSID_CAM_BSSID_3(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 8, 8) +#define GET_AX_BSSID_CAM_BSSID_4(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 16, 8) +#define GET_AX_BSSID_CAM_BSSID_5(__pCAM) LE_BITS_TO_4BYTE(__pCAM, 24, 8) + +int get_ax_sec_cam(void* sel, struct _ADAPTER *a); +int get_ax_address_cam(void* sel, struct _ADAPTER *a); +int get_ax_valid_key(void* sel, struct _ADAPTER *a); + +#endif /* CONFIG_DBG_AX_CAM */ + +#endif /* __RTW_SEC_CAM_H__ */ diff --git a/include/rtw_security.h b/include/rtw_security.h index 9cceed6..0eda696 100644 --- a/include/rtw_security.h +++ b/include/rtw_security.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -44,6 +44,7 @@ enum security_type { #endif }; + /* 802.11W use wrong key */ #define IEEE80211W_RIGHT_KEY 0x0 #define IEEE80211W_WRONG_KEY 0x1 @@ -66,6 +67,10 @@ u32 security_type_bip_to_gmcs(enum security_type type); #define RTW_KCK_LEN 16 #define RTW_TKIP_MIC_LEN 8 #define RTW_REPLAY_CTR_LEN 8 +/* For CCMP-128 only */ +#define RTW_PTK_LEN 16 +/* For BIP-CMAC-128 only */ +#define RTW_IGTK_LEN 16 #define INVALID_SEC_MAC_CAM_ID 0xFF @@ -73,7 +78,7 @@ typedef enum { ENCRYP_PROTOCOL_OPENSYS, /* open system */ ENCRYP_PROTOCOL_WEP, /* WEP */ ENCRYP_PROTOCOL_WPA, /* WPA */ - ENCRYP_PROTOCOL_WPA2, /* WPA2 */ + ENCRYP_PROTOCOL_RSN, /* RSN(WPA2/WPA3) */ ENCRYP_PROTOCOL_WAPI, /* WAPI: Not support in this version */ ENCRYP_PROTOCOL_MAX } ENCRYP_PROTOCOL_E; @@ -170,9 +175,11 @@ struct security_priv { unsigned int wpa_pairwise_cipher; unsigned int wpa2_pairwise_cipher; unsigned int akmp; /* An authentication and key management protocol */ -#endif u8 mfp_opt; +#endif +#ifdef CONFIG_CONCURRENT_MODE u8 dot118021x_bmc_cam_id; +#endif /*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/ u32 rsn_akm_suite_type; @@ -201,7 +208,7 @@ struct security_priv { s32 sw_encrypt;/* from registry_priv */ s32 sw_decrypt;/* from registry_priv */ - s32 hw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */ + s32 hw_decrypted; /* Broadcast HW security is ready or not */ /* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */ @@ -210,9 +217,6 @@ struct security_priv { NDIS_802_11_WEP ndiswep; - u8 assoc_info[600]; - u8 szofcapability[256]; /* for wpa2 usage */ - u8 oidassociation[512]; /* for wpa/wpa2 usage */ u8 authenticator_ie[256]; /* store ap security information element */ u8 supplicant_ie[256]; /* store sta security information element */ @@ -377,6 +381,10 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe); u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe); +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +u32 rtw_core_aes_encrypt(_adapter *padapter, u8 *pxframe); +#endif + #ifdef CONFIG_RTW_MESH_AEK int rtw_aes_siv_encrypt(const u8 *key, size_t key_len, const u8 *pw, size_t pwlen, size_t num_elem, @@ -390,7 +398,8 @@ int rtw_aes_siv_decrypt(const u8 *key, size_t key_len, u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len, const u8 *key, const u8 *data, size_t data_len, u8 *mic); u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len, - u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn); + u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn, + u8 *precvframe); #endif #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, void *sta); @@ -416,6 +425,12 @@ u16 rtw_calc_crc(u8 *pdata, int length); #define rtw_sec_chk_auth_type(a, s) \ ((a)->securitypriv.auth_type == (s)) +#define IV_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" +#define IV_ARG(iv) iv[7], iv[6], iv[5], iv[4], iv[3], iv[2], iv[1], iv[0] +#define PN_FMT "0x%02x%02x%02x%02x%02x%02x" +#define PN_ARG(pn) pn[5], pn[4], pn[3], pn[2], pn[1], pn[0] +u8 rtw_iv_to_pn(u8 *iv, u8 *pn, u8 *key_id, u32 enc_algo); +u8 rtw_pn_to_iv(u8 *pn, u8 *iv, u8 key_id, u32 enc_algo); #endif /* __RTL871X_SECURITY_H_ */ u32 rtw_calc_crc32(u8 *data, size_t len); diff --git a/include/rtw_sreset.h b/include/rtw_sreset.h index 1fd999a..e479144 100644 --- a/include/rtw_sreset.h +++ b/include/rtw_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtw_swcrypto.h b/include/rtw_swcrypto.h index d35ad7d..aa578fe 100644 --- a/include/rtw_swcrypto.h +++ b/include/rtw_swcrypto.h @@ -18,6 +18,11 @@ #define NEW_CRYPTO 1 +#if 0 //RTW_PHL_TX: mark un-finished codes for reading +int _rtw_core_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *phdr, uint datalen, u8 *pdata); +#endif + + int _rtw_ccmp_encrypt(_adapter *padapter, u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen); int _rtw_ccmp_decrypt(_adapter *padapter, u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen); diff --git a/include/rtw_tdls.h b/include/rtw_tdls.h index 5c23e4e..0bd89bd 100644 --- a/include/rtw_tdls.h +++ b/include/rtw_tdls.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtw_trx.h b/include/rtw_trx.h new file mode 100644 index 0000000..1e8187c --- /dev/null +++ b/include/rtw_trx.h @@ -0,0 +1,71 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_TRX_H_ +#define _RTW_TRX_H_ + +struct dvobj_priv; +struct rtw_intf_ops { + #ifdef CONFIG_SDIO_HCI + int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); + int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); + #endif /*CONFIG_SDIO_HCI*/ + + /*** xmit section ***/ + s32(*init_xmit_priv)(_adapter *adapter); + void(*free_xmit_priv)(_adapter *adapter); + + s32(*data_xmit)(_adapter *adapter, struct xmit_frame *pxmitframe); + s32(*xmitframe_enqueue)(_adapter *adapter, struct xmit_frame *pxmitframe); + + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ + s32(*xmit_buf_handler)(_adapter *adapter); + #endif + #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + #ifndef CONFIG_SDIO_TX_TASKLET + u8(*start_xmit_frame_thread)(_adapter *adapter); + void(*cancel_xmit_frame_thread)(_adapter *adapter); + #endif + #endif + /*** recv section ***/ + s32(*init_recv_priv)(struct dvobj_priv *dvobj); + void(*free_recv_priv)(struct dvobj_priv *dvobj); + #ifdef CONFIG_RECV_THREAD_MODE + s32 (*recv_hdl)(_adapter *adapter); + #endif + + #if defined(CONFIG_PCI_HCI) + u32(*trxbd_init)(_adapter *adapter); + u32(*trxbd_deinit)(_adapter *adapter); + void(*trxbd_reset)(_adapter *adapter); + s32(*interrupt_handler)(_adapter *adapter); + #endif + + #if defined(CONFIG_USB_HCI) + #ifdef CONFIG_SUPPORT_USB_INT + void(*interrupt_handler)(_adapter *adapter, u16 pkt_len, u8 *pbuf); + #endif + #endif + + #ifdef CONFIG_HOSTAPD_MLME + s32(*hostap_mgnt_xmit_entry)(_adapter *adapter, struct sk_buff *pkt); + #endif +}; + +s32 rtw_mgnt_xmit(_adapter *adapter, struct xmit_frame *pmgntframe); + + +#endif /* _RTW_TRX_H_ */ diff --git a/include/rtw_trx_ops.h b/include/rtw_trx_ops.h new file mode 100644 index 0000000..5d68e5a --- /dev/null +++ b/include/rtw_trx_ops.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_TRX_OPS_H_ +#define _RTW_TRX_OPS_H_ +#include + +static inline s32 rtw_intf_init_xmit_priv(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->intf_ops->init_xmit_priv(adapter); +} + +static inline void rtw_intf_free_xmit_priv(_adapter *adapter) +{ + + adapter_to_dvobj(adapter)->intf_ops->free_xmit_priv(adapter); +} +static inline s32 rtw_intf_data_xmit(_adapter *adapter, + struct xmit_frame *pxmitframe) +{ + return adapter_to_dvobj(adapter)->intf_ops->data_xmit(adapter, pxmitframe); +} + +static inline s32 rtw_intf_xmitframe_enqueue(_adapter *adapter, + struct xmit_frame *pxmitframe) +{ + u32 rtn; + + /* enqueue is not necessary, casuse phl use sw queue to save xmitframe */ + rtn = core_tx_call_phl(adapter, pxmitframe, NULL); + + if (rtn == FAIL) + core_tx_free_xmitframe(adapter, pxmitframe); + + return rtn; +} + +static inline u8 rtw_intf_start_xmit_frame_thread(_adapter *adapter) +{ + u8 rst = _SUCCESS; +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + if (adapter_to_dvobj(adapter)->intf_ops->start_xmit_frame_thread) + rst = adapter_to_dvobj(adapter)->intf_ops->start_xmit_frame_thread(adapter); +#endif +#endif + return rst; +} +static inline void rtw_intf_cancel_xmit_frame_thread(_adapter *adapter) +{ +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + if (adapter_to_dvobj(adapter)->intf_ops->cancel_xmit_frame_thread) + adapter_to_dvobj(adapter)->intf_ops->cancel_xmit_frame_thread(adapter); +#endif +#endif +} + +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ +static inline s32 rtw_intf_xmit_buf_handler(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->intf_ops->xmit_buf_handler(adapter); +} +#endif + + +/************************ recv *******************/ +static inline s32 rtw_intf_init_recv_priv(struct dvobj_priv *dvobj) +{ + return dvobj->intf_ops->init_recv_priv(dvobj); +} +static inline void rtw_intf_free_recv_priv(struct dvobj_priv *dvobj) +{ + return dvobj->intf_ops->free_recv_priv(dvobj); +} + +#ifdef CONFIG_RECV_THREAD_MODE +static inline s32 rtw_intf_recv_hdl(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->intf_ops->recv_hdl(adapter); +} +#endif + +struct lite_data_buf *rtw_alloc_litedatabuf(struct trx_data_buf_q *data_buf_q); +s32 rtw_free_litedatabuf(struct trx_data_buf_q *data_buf_q, + struct lite_data_buf *lite_data_buf); + +#endif /* _RTW_TRX_OPS_H_ */ diff --git a/include/rtw_trx_pci.h b/include/rtw_trx_pci.h new file mode 100644 index 0000000..e78bfe8 --- /dev/null +++ b/include/rtw_trx_pci.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_TRX_PCI_H_ +#define _RTW_TRX_PCI_H_ + +extern struct rtw_intf_ops pci_ops; + +static inline u8 is_pci_support_dma64(struct dvobj_priv *dvobj) +{ + PPCI_DATA pci_data = dvobj_to_pci(dvobj); + + return (pci_data->bdma64 == _TRUE) ? _TRUE : _FALSE; +} +#endif /* _RTW_TRX_PCI_H_ */ diff --git a/include/rtw_trx_sdio.h b/include/rtw_trx_sdio.h new file mode 100644 index 0000000..813b46a --- /dev/null +++ b/include/rtw_trx_sdio.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_TRX_SDIO_H_ +#define _RTW_TRX_SDIO_H_ + +#include /* struct dvobj_priv and etc. */ + +s32 sdio_dequeue_xmit(_adapter *adapter); + +extern struct rtw_intf_ops sdio_ops; + +#endif /* _RTW_SDIO_H_ */ diff --git a/include/rtw_trx_usb.h b/include/rtw_trx_usb.h new file mode 100644 index 0000000..3f0e101 --- /dev/null +++ b/include/rtw_trx_usb.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_TRX_USB_H_ +#define _RTW_TRX_USB_H_ +#include /* struct dvobj_priv and etc. */ + +extern struct rtw_intf_ops usb_ops; + +#endif /* _RTW_TRX_USB_H_ */ diff --git a/include/rtw_version.h b/include/rtw_version.h index 8fb51be..eb1d433 100644 --- a/include/rtw_version.h +++ b/include/rtw_version.h @@ -1 +1 @@ -#define DRIVERVERSION "v5.13.1_ohd_THIS_IS_DIRTY" +#define DRIVERVERSION "v1.15.7-112-g1d36f2f7.20211227" diff --git a/include/rtw_vht.h b/include/rtw_vht.h index f08ac4f..8476908 100644 --- a/include/rtw_vht.h +++ b/include/rtw_vht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -38,20 +38,23 @@ #define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val) #define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val) #define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val) -#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val) -#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val) +/* #define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val) */ +#define SET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val) +#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val) /* B16~B18 */ #define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val) #define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val) #define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val) #define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val) #define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */ -#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 2, 2, _val) +#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val) #define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val) /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */ #define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val) #define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val) /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */ #define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val) - +#define SET_VHT_CAPABILITY_ELE_RX_ANT_PATTERN(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_TX_ANT_PATTERN(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 5, 1, _val) +#define SET_VHT_CAPABILITY_ELE_EXT_NSS_BW(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 6, 2, _val) #define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 2) #define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 2, 2) @@ -63,12 +66,17 @@ #define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1) #define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1) /*phydm-beamforming*/ -#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3) +#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 5, 3) #define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3) #define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1) #define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1) #define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1) +#define GET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 6, 1) #define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3) +#define GET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 2, 2) +#define GET_VHT_CAPABILITY_ELE_RX_ANT_PATTERN(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 4, 1) +#define GET_VHT_CAPABILITY_ELE_TX_ANT_PATTERN(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 5, 1) +#define GET_VHT_CAPABILITY_ELE_EXT_NSS_BW(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 6, 2) #define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart) ((_pEleStart)+4) #define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13) #define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart) ((_pEleStart)+8) @@ -84,6 +92,7 @@ #define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 8) #define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8) #define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8) +#define GET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+3, 0, 16) /* VHT Operating Mode */ #define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) @@ -103,12 +112,10 @@ extern const u16 _vht_max_mpdu_len[]; #define VHT_SUP_CH_WIDTH_SET_MAX 3 extern const u8 _vht_sup_ch_width_set_to_bw_cap[]; #define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)]) -#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1) - -#ifdef CONFIG_RTW_DEBUG extern const char *const _vht_sup_ch_width_set_str[]; #define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)]) +#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1) void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len); #define VHT_OP_CH_WIDTH_MAX 4 @@ -116,7 +123,6 @@ extern const char *const _vht_op_ch_width_str[]; #define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)]) void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len); -#endif struct vht_bf_cap { u8 is_mu_bfer; @@ -124,18 +130,39 @@ struct vht_bf_cap { }; struct vht_priv { - u8 vht_option; - - u8 ldpc_cap; - u8 stbc_cap; - u16 beamform_cap; - struct vht_bf_cap ap_bf_cap; - - u8 sgi_80m;/* short GI */ - u8 ampdu_len; - - u8 vht_highest_rate; - u8 vht_mcs_map[2]; + /* VHT IE is configured by upper layer or not (hostapd or wpa_supplicant) */ + u8 upper_layer_setting; + + u8 vht_option; + + u8 ldpc_cap; + u8 stbc_cap; + u8 rx_stbc_nss; /* Support nss spatial stream */ + u16 beamform_cap; + struct vht_bf_cap ap_bf_cap; + u8 num_snd_dim; + u8 bfme_sts; + u8 sgi_80m; + u8 sgi_160m; + u8 ampdu_len;/* A-MPDU length exponent : 0 to 7 */ + + /* + * max_amsdu_len + * 0: 3895 bytes + * 1: 7991 bytes + * 2: 11454 bytes + */ + u8 max_mpdu_len; + + u8 vht_highest_rate; + u8 vht_mcs_map[2]; + + u8 txop_ps; /* TXOP power save mode*/ + u8 htc_vht; /* VHT variant HT Control*/ + u8 link_adap_cap; /* VHT Link Adaptation Capable */ + u8 tx_ant_pattern; /* Tx Antenna Pattern Consistency */ + u8 rx_ant_pattern; /* Rx Antenna Pattern Consistency */ + u8 ext_nss_bw; /* Extended NSS BW Support */ u8 op_present:1; /* vht_op is present */ u8 notify_present:1; /* vht_op_mode_notify is present */ @@ -143,6 +170,10 @@ struct vht_priv { u8 vht_cap[32]; u8 vht_op[VHT_OP_IE_LEN]; u8 vht_op_mode_notify; + + /* Backup these two VHT IEs from hostapd/wpa_supplicant for restore usage */ + u8 vht_cap_ie_backup[VHT_CAP_IE_LEN]; + u8 vht_op_ie_backup[VHT_OP_IE_LEN]; }; #ifdef ROKU_PRIVATE @@ -162,7 +193,11 @@ struct vht_priv_infra_ap { u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate); u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss); -void rtw_vht_use_default_setting(_adapter *padapter); +struct protocol_cap_t; +struct role_cap_t; +void rtw_vht_get_dft_setting(_adapter *padapter, + struct protocol_cap_t *dft_proto_cap, struct role_cap_t *dft_cap); +void rtw_vht_get_real_setting(_adapter *padapter); u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel); u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw); u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf); @@ -174,11 +209,14 @@ void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE #endif /* ROKU_PRIVATE */ void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta); -u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan); void VHTOnAssocRsp(_adapter *padapter); u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map); void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len); +void rtw_update_drv_vht_cap(_adapter *padapter, u8 *vht_cap_ie); +void rtw_check_vht_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +void rtw_reattach_vht_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork); #endif /* _RTW_VHT_H_ */ diff --git a/include/rtw_wapi.h b/include/rtw_wapi.h index 512bb7f..4b53bd1 100644 --- a/include/rtw_wapi.h +++ b/include/rtw_wapi.h @@ -29,12 +29,12 @@ /* WAPI trace debug */ extern u32 wapi_debug_component; -static inline void dump_buf(u8 *buf, u32 len) +static inline void wapi_dump_buf(u8 *buf, u32 len) { u32 i; printk("-----------------Len %d----------------\n", len); for (i = 0; i < len; i++) - printk("%2.2x-", *(buf + i)); + printk(KERN_CONT"%2.2x-", *(buf + i)); printk("\n"); } @@ -47,7 +47,7 @@ static inline void dump_buf(u8 *buf, u32 len) #define WAPI_DATA(component, x, buf, len) \ do { if (wapi_debug_component & (component)) { \ printk("%s:\n", x);\ - dump_buf((buf), (len)); } \ + wapi_dump_buf((buf), (len)); } \ } while (0); #define RT_ASSERT_RET(_Exp) \ @@ -211,7 +211,7 @@ void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr); void rtw_wapi_clear_all_cam_entry(_adapter *padapter); -void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey); +void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey); int rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen); diff --git a/include/rtw_wnm.h b/include/rtw_wnm.h index 8d6bcb5..51cbb58 100644 --- a/include/rtw_wnm.h +++ b/include/rtw_wnm.h @@ -45,8 +45,7 @@ (_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\ (c)->network.MacAddress, ETH_ALEN))) -#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \ - SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val) +#define rtw_wnm_add_btm_ext_cap(d, l) rtw_add_ext_cap_info(d, l, BSS_TRANSITION) #define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED) @@ -54,6 +53,8 @@ #define wnm_btm_dialog_token(p) (*((u8 *)((p)+2))) +#define wnm_btm_query_reason(p) (*((u8 *)((p)+3))) + #define wnm_btm_req_mode(p) (*((u8 *)((p)+3))) #define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4))) @@ -73,7 +74,7 @@ enum rtw_ieee80211_wnm_actioncode { RTW_WLAN_ACTION_WNM_BTM_REQ = 7, RTW_WLAN_ACTION_WNM_BTM_RSP = 8, RTW_WLAN_ACTION_WNM_NOTIF_REQ = 26, - RTW_WLAN_ACTION_WNM_NOTIF_RSP = 27, + RTW_WLAN_ACTION_WNM_NOTIF_RSP = 27, }; /*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/ @@ -84,7 +85,7 @@ struct nb_rpt_hdr { u32 bss_info; u8 reg_class; u8 ch_num; - u8 phy_type; + u8 phy_type; }; /*IEEE Std 80211v, Figure 7-9 BSS Termination Duration subelement field format */ @@ -163,7 +164,7 @@ struct roam_nb_info { u8 nb_rpt_is_same; s8 disassoc_waiting; _timer roam_scan_timer; - _timer disassoc_chk_timer; + _timer disassoc_chk_timer; u32 features; }; @@ -176,7 +177,14 @@ void rtw_wnm_disassoc_chk_hdl(void *ctx); u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter); -void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len); +void rtw_wnm_process_btm_query(_adapter *padapter, + u8* pframe, u32 frame_len); + +void rtw_wnm_process_btm_req(_adapter *padapter, + u8* pframe, u32 frame_len); + +void rtw_wnm_process_notification_req( + _adapter *padapter, u8* pframe, u32 frame_len); void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb); @@ -203,7 +211,7 @@ void rtw_roam_nb_info_init(_adapter *padapter); u8 rtw_roam_nb_scan_list_set(_adapter *padapter, struct sitesurvey_parm *pparm); -u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, +u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, u8* pframe, u32 elem_len, u8 is_preference); #endif /* __RTW_WNM_H_ */ diff --git a/include/rtw_wow.h b/include/rtw_wow.h new file mode 100644 index 0000000..500ce43 --- /dev/null +++ b/include/rtw_wow.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_WOW_H_ +#define __RTW_WOW_H_ + +#ifdef CONFIG_WOWLAN +/* WoWLAN Info define */ +/*=========================== Remote Control Info =========================== */ +#define REMOTECTRL_INFO_VALID_CHECK 0xdd +#define REMOTECTRL_INFO_SYMBOL_CHK_PTK BIT0 +#define REMOTECTRL_INFO_SYMBOL_CHK_GTK BIT1 +/*============================================================================*/ + #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86 + /* TCP/ICMP/UDP multicast with specific IP addr */ + #define DEFAULT_PATTERN_NUM 4 + #else + /* TCP/ICMP */ + #define DEFAULT_PATTERN_NUM 3 + #endif + +#define MAX_WKFM_CAM_NUM 18 /* same as MAX_WOW_CAM_NUM */ + +#define MAX_WKFM_SIZE 16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */ +#define MAX_WKFM_PATTERN_SIZE 128 + +/* + * MAX_WKFM_PATTERN_STR_LEN : the max. length of wow pattern string + * e.g. echo 00:01:02:...:7f > /proc/net/rtl88x2bu/wlan0/wow_pattern_info + * - each byte of pattern is represented as 2-bytes ascii : MAX_WKFM_PATTERN_SIZE * 2 + * - the number of common ':' in pattern string : MAX_WKFM_PATTERN_SIZE - 1 + * - 1 byte '\n'(0x0a) is generated at the end when we use echo command + * so total max. length is (MAX_WKFM_PATTERN_SIZE * 3) + */ +#define MAX_WKFM_PATTERN_STR_LEN (MAX_WKFM_PATTERN_SIZE * 3) + +#define WKFMCAM_ADDR_NUM 6 +#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */ + +struct aoac_report { + u8 iv[8]; + u8 replay_counter_eapol_key[8]; + u8 group_key[32]; + u8 key_index; + u8 security_type; + u8 wow_pattern_idx; + u8 version_info; + u8 rekey_ok:1; + u8 dummy:7; + u8 reserved[3]; + u8 rxptk_iv[8]; + u8 rxgtk_iv[4][8]; +}; + +enum pattern_type { + RTW_INVALID_PATTERN, + RTW_DEFAULT_PATTERN, + RTW_CUSTOMIZED_PATTERN, +}; + +enum rtw_wow_dev2hst_gpio { + DEV2HST_GPIO_OUTPUT = 0, + DEV2HST_GPIO_INPUT = 1 +}; + +enum rtw_wow_dev2hst_active { + DEV2HST_LOW_ACTIVE = 0, + DEV2HST_HIGH_ACTIVE = 1 +}; + +enum rtw_wow_dev2hst_toggle_pulse { + DEV2HST_TOGGLE = 0, + DEV2HST_PULSE = 1 +}; + +enum rtw_wow_dev2hst_time_unit { + DEV2HST_32US = 0, + DEV2HST_4MS = 1 +}; + +typedef struct rtl_priv_pattern { + int len; + char content[MAX_WKFM_PATTERN_SIZE]; + char mask[MAX_WKFM_SIZE]; +} rtl_priv_pattern_t; + +struct wow_priv { + struct rtw_wow_wake_info wow_wake_event; + struct rtw_wow_gpio_info wow_gpio; + struct rtw_disc_det_info wow_disc; + enum pattern_type wow_ptrn_valid[MAX_WKFM_CAM_NUM]; +}; + +void rtw_init_wow(_adapter *padapter); +void rtw_free_wow(_adapter *adapter); +void rtw_get_sec_iv(_adapter *padapter, u8 *pcur_dot11txpn, u8 *StaAddr); +bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, + int *pattern_len, char *bit_mask); +u8 rtw_wow_pattern_set(_adapter *adapter, + struct rtw_wowcam_upd_info * wowcam_info, + enum pattern_type set_type); +void rtw_wow_pattern_clean(_adapter *adapter, enum pattern_type clean_type); +void rtw_set_default_pattern(_adapter *adapter); +void rtw_wow_pattern_sw_dump(_adapter *adapter); +void rtw_construct_remote_control_info(_adapter *adapter, + struct rtw_remote_wake_ctrl_info *ctrl_info); +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en); +int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode); +int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level); +#ifdef CONFIG_LPS_1T1R +int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en); +#endif +#ifdef CONFIG_GTK_OL +void rtw_update_gtk_ofld_info(void *drv_priv, struct rtw_aoac_report *aoac_info, + u8 aoac_report_get_ok, u8 phase); +#endif +bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap); +void rtw_wowlan_set_pattern_cast_type(_adapter *adapter, struct rtw_wowcam_upd_info *wowcam_info); +#endif /* CONFIG_WOWLAN */ + +#ifdef CONFIG_PNO_SUPPORT +#define MAX_PNO_LIST_COUNT 16 +#define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */ +#define MAX_HIDDEN_AP 8 /* 8 hidden AP */ + +typedef struct pno_nlo_info { + u32 fast_scan_period; /* Fast scan period */ + u8 ssid_num; /* number of entry */ + u8 hidden_ssid_num; + u32 slow_scan_period; /* slow scan period */ + u32 fast_scan_iterations; /* Fast scan iterations */ + u8 ssid_length[MAX_PNO_LIST_COUNT]; /* SSID Length Array */ + u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; /* Cipher information for security */ + u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; /* channel information */ + u8 loc_probe_req[MAX_HIDDEN_AP]; /* loc_probeReq */ +} pno_nlo_info_t; + +typedef struct pno_ssid { + u32 SSID_len; + u8 SSID[32]; +} pno_ssid_t; + +typedef struct pno_ssid_list { + pno_ssid_t node[MAX_PNO_LIST_COUNT]; +} pno_ssid_list_t; + +typedef struct pno_scan_channel_info { + u8 channel; + u8 tx_power; + u8 timeout; + u8 active; /* set 1 means active scan, or pasivite scan. */ +} pno_scan_channel_info_t; + +typedef struct pno_scan_info { + u8 enableRFE; /* Enable RFE */ + u8 period_scan_time; /* exclusive with fast_scan_period and slow_scan_period */ + u8 periodScan; /* exclusive with fast_scan_period and slow_scan_period */ + u8 orig_80_offset; /* original channel 80 offset */ + u8 orig_40_offset; /* original channel 40 offset */ + u8 orig_bw; /* original bandwidth */ + u8 orig_ch; /* original channel */ + u8 channel_num; /* number of channel */ + u64 rfe_type; /* rfe_type && 0x00000000000000ff */ + pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT]; +} pno_scan_info_t; + +int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left); +int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, + int pno_time, int pno_repeat, int pno_freq_expo_max); +#ifdef CONFIG_PNO_SET_DEBUG + void rtw_dev_pno_debug(struct net_device *net); +#endif /* CONFIG_PNO_SET_DEBUG */ +#endif /* CONFIG_PNO_SUPPORT */ + +#endif /* __RTW_WOW_H_ */ diff --git a/include/rtw_xmit.h b/include/rtw_xmit.h index bdbd9d3..5562710 100644 --- a/include/rtw_xmit.h +++ b/include/rtw_xmit.h @@ -15,65 +15,19 @@ #ifndef _RTW_XMIT_H_ #define _RTW_XMIT_H_ - #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifdef CONFIG_TX_AGGREGATION - #ifdef CONFIG_RTL8822C - #ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO - #define MAX_XMITBUF_SZ (51200) - #else - #define MAX_XMITBUF_SZ (32764) - #endif - #else - #define MAX_XMITBUF_SZ (20480) /* 20k */ - #endif /* #define SDIO_TX_AGG_MAX 5 */ #else - #define MAX_XMITBUF_SZ (1664) #define SDIO_TX_AGG_MAX 1 #endif #if defined CONFIG_SDIO_HCI - #define NR_XMITBUFF (16) #define SDIO_TX_DIV_NUM (2) #endif - #if defined(CONFIG_GSPI_HCI) - #define NR_XMITBUFF (128) - #endif - -#elif defined (CONFIG_USB_HCI) - - #ifdef CONFIG_USB_TX_AGGREGATION - #if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1) - #define MAX_XMITBUF_SZ (12288) /* 12k 1536*8 */ - #elif defined (CONFIG_PLATFORM_MSTAR) - #define MAX_XMITBUF_SZ 7680 /* 7.5k */ - #else - #define MAX_XMITBUF_SZ (20480) /* 20k */ - #endif - #else - #define MAX_XMITBUF_SZ (2048) - #endif - - #ifdef CONFIG_SINGLE_XMIT_BUF - #define NR_XMITBUFF (1) - #else - #define NR_XMITBUFF (4) - #endif /* CONFIG_SINGLE_XMIT_BUF */ -#elif defined (CONFIG_PCI_HCI) -#ifdef CONFIG_TX_AMSDU - #define MAX_XMITBUF_SZ (3500) -#else - #define MAX_XMITBUF_SZ (1664) #endif -#ifdef CONFIG_PCI_TX_POLLING - #define NR_XMITBUFF (256) -#else - #define NR_XMITBUFF (128) -#endif -#endif - +#if 0 /*CONFIG_CORE_XMITBUF*/ #ifdef CONFIG_PCI_HCI #define XMITBUF_ALIGN_SZ 4 #else @@ -84,26 +38,7 @@ #endif #endif - -/* xmit extension buff defination */ -#define MAX_XMIT_EXTBUF_SZ (1536) - -#ifdef CONFIG_SINGLE_XMIT_BUF - #define NR_XMIT_EXTBUFF (1) -#else - //#define NR_XMIT_EXTBUFF (32) - // OpenHD: changed to same value like rtl812au - #define NR_XMIT_EXTBUFF (64) -#endif - -#ifdef CONFIG_RTL8812A - #define MAX_CMDBUF_SZ (512 * 18) -#elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF) - #define MAX_CMDBUF_SZ (128*70) /*(8960)*/ -#elif defined(CONFIG_RTL8822C) && defined(CONFIG_WAR_OFFLOAD) - #define MAX_CMDBUF_SZ (128*128) /*(16k) */ -#else - #define MAX_CMDBUF_SZ (5120) /* (4096) */ +#define MAX_CMDBUF_SZ (5120) /* (4096) */ #endif #define MAX_BEACON_LEN 512 @@ -121,23 +56,18 @@ #define BK_QUEUE_INX 3 #define BCN_QUEUE_INX 4 #define MGT_QUEUE_INX 5 -#define TXCMD_QUEUE_INX 6 -#define HIGH_QUEUE_INX 7 -/* keep high queue to be the last one, so we can extend HIQ to port 1, 2, ... */ +#define HIGH_QUEUE_INX 6 +#define TXCMD_QUEUE_INX 7 -#ifndef CONFIG_PORT_BASED_HIQ #define HW_QUEUE_ENTRY 8 -#else -#define HI_QUEUE_INX(n) (HIGH_QUEUE_INX + (n)) -#define HW_QUEUE_ENTRY (8 + CONFIG_IFACE_NUMBER - 1) -#endif -#ifdef CONFIG_PCI_HCI - #ifdef CONFIG_TRX_BD_ARCH - #define TX_BD_NUM (128+1) /* +1 result from ring buffer */ - #else - #define TXDESC_NUM 128 - #endif + +#ifdef RTW_PHL_TX +#define RTW_MAX_FRAG_NUM 10 //max scatter number of a packet to xmit +#define RTW_MAX_WL_HEAD 100 +#define RTW_MAX_WL_TAIL 100 +#define RTW_SZ_LLC (SNAP_SIZE + sizeof(u16)) +#define RTW_SZ_FCS 4 #endif #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ @@ -191,31 +121,15 @@ #define IS_AMSDU_AMPDU_VALID(pattrib)\ !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) -#ifdef CONFIG_RTW_MGMT_QUEUE -#define HWXMIT_ENTRY 5 -#else -#define HWXMIT_ENTRY 4 -#endif +#define HWXMIT_ENTRY 4 /* For Buffer Descriptor ring architecture */ #if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH) - #if defined(CONFIG_RTL8192E) - #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ - #elif defined(CONFIG_RTL8814A) - #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ - #else - #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ - #endif + #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ #endif -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\ - defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\ - defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\ - defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\ - defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F) ||\ - defined(CONFIG_RTL8723F) - #define TXDESC_SIZE 40 -#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) +/*GEORGIA_TODO_FIXIT_MOVE_TO_HAL*/ +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8822B */ #elif defined(CONFIG_RTL8821C) #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8821C */ @@ -244,7 +158,7 @@ #endif #ifdef CONFIG_PCI_HCI - #if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH) + #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH) /* this section is defined for buffer descriptor ring architecture */ #define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */ /* tx desc and payload are in the same buf */ @@ -253,10 +167,24 @@ /* tx desc and payload are NOT in the same buf */ #define TXDESC_OFFSET (0) /* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */ - #define TX_DESC_NEXT_DESC_OFFSET (TXDESC_SIZE + 8) #endif #endif /* CONFIG_PCI_HCI */ +#ifdef RTW_PHL_TX +#ifdef TXDESC_OFFSET +#undef TXDESC_OFFSET +#endif +#define TXDESC_OFFSET (0) +#endif + +#ifdef RTW_PHL_TX +enum CORE_TX_TYPE { + RTW_TX_OS = 0, + RTW_TX_OS_MAC80211, + RTW_TX_DRV_MGMT, +}; +#endif + enum TXDESC_SC { SC_DONT_CARE = 0x00, SC_UPPER = 0x01, @@ -268,12 +196,9 @@ enum TXDESC_SC { #ifndef CONFIG_TRX_BD_ARCH /* CONFIG_TRX_BD_ARCH doesn't need this */ #define TXDESC_64_BYTES #endif -#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \ - || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \ - || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F) - #define TXDESC_40_BYTES #endif +/*GEORGIA_TODO_FIXIT_IC_DEPENDENCE*/ #ifdef CONFIG_TRX_BD_ARCH struct tx_buf_desc { #ifdef CONFIG_64BIT_DMA @@ -283,7 +208,7 @@ struct tx_buf_desc { #endif unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)]; } __packed; -#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */ +#elif (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */ /* 8192EE_TODO */ struct tx_desc { unsigned int txdw0; @@ -335,7 +260,7 @@ union txdesc { #endif #ifdef CONFIG_PCI_HCI -#define PCI_MAX_TX_QUEUE_COUNT HW_QUEUE_ENTRY +#define PCI_MAX_TX_QUEUE_COUNT 8 /* == HW_QUEUE_ENTRY */ struct rtw_tx_ring { unsigned char qid; @@ -379,6 +304,156 @@ struct hw_xmit { int accnt; }; + +#if 1 //def RTW_PHL_TX +struct pkt_attrib { +//updated by rtw_core_update_xmitframe + u32 sz_payload_per_frag; + + u32 sz_wlan_head; + u32 sz_wlan_tail; + + u32 sz_phl_head; + u32 sz_phl_tail; + + u8 nr_frags; + u32 frag_len; + u32 frag_datalen; +#ifdef CONFIG_CORE_TXSC + u32 frag_len_txsc; +#endif + +//updated by + u16 ether_type; + + u8 src[ETH_ALEN]; + u8 dst[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + + u16 pkt_hdrlen; /* the original 802.3 pkt header len */ + u32 sz_payload; + + u8 dhcp_pkt; + u8 icmp_pkt; + u8 hipriority_pkt; /* high priority packet */ + +//WLAN HDR + u16 hdrlen; /* the WLAN Header Len */ + u8 type; + u8 subtype; + u8 qos_en; + u16 seqnum; + u8 ampdu_en;/* tx ampdu enable */ + u8 ack_policy; + u8 amsdu; + u8 mdata;/* more data bit */ + u8 eosp; + u8 priority; + +//Security + u8 bswenc; + /* + * encrypt + * indicate the encrypt algorithm, ref: enum security_type. + * 0: indicate no encrypt. + */ + u8 encrypt; + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; + u8 key_idx; + union Keytype dot11tkiptxmickey; + /* union Keytype dot11tkiprxmickey; */ + union Keytype dot118021x_UncstKey; + +//updated by rtw_core_update_xmitframe + u8 hw_ssn_sel; /* for HW_SEQ0,1,2,3 */ + u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */ + u32 last_txcmdsz; + +#if defined(CONFIG_CONCURRENT_MODE) + u8 bmc_camid; +#endif + + + + u8 mac_id; + u8 vcs_mode; /* virtual carrier sense method */ +#ifdef CONFIG_RTW_WDS + u8 wds; +#endif +#ifdef CONFIG_RTW_MESH + u8 mda[ETH_ALEN]; /* mesh da */ + u8 msa[ETH_ALEN]; /* mesh sa */ + u8 meshctrl_len; /* Length of Mesh Control field */ + u8 mesh_frame_mode; + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + u8 mb2u; + #endif + u8 mfwd_ttl; + u32 mseq; +#endif +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + u8 hw_csum; +#endif + + + u8 ht_en; + u8 raid;/* rate adpative id */ + u8 bwmode; + u8 ch_offset;/* PRIME_CHNL_OFFSET */ + u8 sgi;/* short GI */ + u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ + u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ + u8 pctrl;/* per packet txdesc control enable */ + u8 triggered;/* for ap mode handling Power Saving sta */ + u8 qsel; + u8 order;/* order bit */ + u8 rate; + u8 intel_proxim; + u8 retry_ctrl; + u8 mbssid; + u8 ldpc; + u8 stbc; +#ifdef CONFIG_WMMPS_STA + u8 trigger_frame; +#endif /* CONFIG_WMMPS_STA */ + + struct sta_info *psta; + + u8 rtsen; + u8 cts2self; + u8 hw_rts_en; + +#ifdef CONFIG_TDLS + u8 direct_link; + struct sta_info *ptdls_sta; +#endif /* CONFIG_TDLS */ + u8 key_type; + + + +#ifdef CONFIG_BEAMFORMING + u16 txbf_p_aid;/*beamforming Partial_AID*/ + u16 txbf_g_id;/*beamforming Group ID*/ + + /* + * 2'b00: Unicast NDPA + * 2'b01: Broadcast NDPA + * 2'b10: Beamforming Report Poll + * 2'b11: Final Beamforming Report Poll + */ + u8 bf_pkt_type; +#endif + u8 wdinfo_en;/*FPGA_test*/ + u8 dma_ch;/*FPGA_test*/ +}; +#endif + +#if 0 //ndef RTW_PHL_TX +/* reduce size */ struct pkt_attrib { u8 type; u8 subtype; @@ -393,7 +468,9 @@ struct pkt_attrib { u32 last_txcmdsz; u8 nr_frags; u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ +#if defined(CONFIG_CONCURRENT_MODE) u8 bmc_camid; +#endif u8 iv_len; u8 icv_len; u8 iv[18]; @@ -406,9 +483,6 @@ struct pkt_attrib { u8 src[ETH_ALEN]; u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; -#ifdef CONFIG_RTW_WDS - u8 wds; -#endif #ifdef CONFIG_RTW_MESH u8 mda[ETH_ALEN]; /* mesh da */ u8 msa[ETH_ALEN]; /* mesh sa */ @@ -446,11 +520,10 @@ struct pkt_attrib { u8 mbssid; u8 ldpc; u8 stbc; - u8 monitor_mode_frame; #ifdef CONFIG_WMMPS_STA u8 trigger_frame; #endif /* CONFIG_WMMPS_STA */ - + struct sta_info *psta; u8 rtsen; @@ -480,11 +553,10 @@ struct pkt_attrib { */ u8 bf_pkt_type; #endif - -#ifdef CONFIG_RTW_MGMT_QUEUE - u8 ps_dontq; /* 1: this frame can't be queued at PS state */ -#endif + u8 wdinfo_en;/*FPGA_test*/ + u8 dma_ch;/*FPGA_test*/ }; +#endif #ifdef CONFIG_RTW_WDS #define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds) @@ -533,9 +605,7 @@ struct submit_ctx { systime submit_time; /* */ u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ int status; /* status for operation */ -#ifdef PLATFORM_LINUX - struct completion done; -#endif + _completion done; }; enum { @@ -562,6 +632,7 @@ int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg); void rtw_sctx_done_err(struct submit_ctx **sctx, int status); void rtw_sctx_done(struct submit_ctx **sctx); +#if 0 /*CONFIG_CORE_XMITBUF*/ struct xmit_buf { _list list; @@ -585,9 +656,7 @@ struct xmit_buf { /* u32 sz[8]; */ u32 ff_hwaddr; -#ifdef RTW_HALMAC u8 bulkout_id; /* for halmac */ -#endif /* RTW_HALMAC */ PURB pxmit_urb[8]; dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ @@ -621,7 +690,26 @@ struct xmit_buf { #endif }; +#endif +#ifdef CONFIG_CORE_TXSC +#define MAX_TXSC_SKB_NUM 6 +#endif + +struct xmit_txreq_buf { + _list list; + u8 *txreq; + u8 *head; + u8 *tail; + u8 *pkt_list; +#ifdef CONFIG_CORE_TXSC + u8 *pkt[MAX_TXSC_SKB_NUM]; + u8 pkt_cnt; + _adapter *adapter; + u8 macid; + u8 txsc_id; +#endif +}; struct xmit_frame { _list list; @@ -629,15 +717,22 @@ struct xmit_frame { struct pkt_attrib attrib; u16 os_qid; - _pkt *pkt; + + struct sk_buff *pkt; int frame_tag; _adapter *padapter; - u8 *buf_addr; - + /*Only for MGNT Frame*/ + u8 *prealloc_buf_addr; + #ifdef CONFIG_USB_HCI + dma_addr_t dma_transfer_addr; + #endif + u8 *buf_addr; + #if 0 /*CONFIG_CORE_XMITBUF*/ struct xmit_buf *pxmitbuf; + #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) u8 pg_num; @@ -658,6 +753,28 @@ struct xmit_frame { u8 *alloc_addr; /* the actual address this xmitframe allocated */ u8 ext_tag; /* 0:data, 1:mgmt */ +#ifdef RTW_PHL_TX + u8 xftype; + + //struct sk_buff *skb; + //struct sta_info *psta; + //struct pkt_attrib tx_attrib; + + u8 alloc_hdr; + u8 alloc_tail; + u8 *wlhdr[RTW_MAX_FRAG_NUM]; + u8 *wltail[RTW_MAX_FRAG_NUM]; + + u32 txring_idx; + u32 txreq_cnt; + struct rtw_xmit_req *phl_txreq; + u32 txfree_cnt; + + struct xmit_txreq_buf *ptxreq_buf;/* TXREQ_QMGT for recycle*/ + + u16 buf_need_free; /* size is realted to RTW_MAX_FRAG_NUM */ +#endif + }; struct tx_servq { @@ -678,10 +795,6 @@ struct sta_xmit_priv { struct tx_servq bk_q; /* priority == 1,2 */ struct tx_servq vi_q; /* priority == 4,5 */ struct tx_servq vo_q; /* priority == 6,7 */ -#ifdef CONFIG_RTW_MGMT_QUEUE - struct tx_servq mgmt_q; -#endif - _list legacy_dz; _list apsd; @@ -710,27 +823,26 @@ struct agg_pkt_info { u16 offset; u16 pkt_len; }; - +#if 0 /*CONFIG_CORE_XMITBUF*/ enum cmdbuf_type { CMDBUF_BEACON = 0x00, CMDBUF_RSVD, CMDBUF_MAX }; - -u8 rtw_get_hwseq_no(_adapter *padapter); - +#endif struct xmit_priv { _lock lock; - + #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ _sema xmit_sema; + #endif /* _queue blk_strms[MAX_NUMBLKS]; */ _queue be_pending; _queue bk_pending; _queue vi_pending; _queue vo_pending; - _queue mgmt_pending; + _queue bm_pending; /* _queue legacy_dz_queue; */ /* _queue apsd_queue; */ @@ -748,6 +860,10 @@ struct xmit_priv { uint free_xframe_ext_cnt; _queue free_xframe_ext_queue; + /* MGT_TXREQ_QMGT */ + u8 *xframe_ext_txreq_alloc_addr; + u8 *xframe_ext_txreq; + /* struct hw_txqueue be_txqueue; */ /* struct hw_txqueue bk_txqueue; */ /* struct hw_txqueue vi_txqueue; */ @@ -796,17 +912,16 @@ struct xmit_priv { #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -#ifdef CONFIG_SDIO_TX_TASKLET +#ifdef CONFIG_TX_AMSDU_SW_MODE _tasklet xmit_tasklet; -#else +#endif +#ifndef CONFIG_SDIO_TX_TASKLET _thread_hdl_ SdioXmitThread; _sema SdioXmitSema; - #ifdef SDIO_FREE_XMIT_BUF_SEMA - _sema sdio_free_xmitbuf_sema; - #endif -#endif /* CONFIG_SDIO_TX_TASKLET */ +#endif #endif /* CONFIG_SDIO_HCI */ +#if 0 /*CONFIG_CORE_XMITBUF*/ _queue free_xmitbuf_queue; _queue pending_xmitbuf_queue; u8 *pallocated_xmitbuf; @@ -819,6 +934,7 @@ struct xmit_priv { uint free_xmit_extbuf_cnt; struct xmit_buf pcmd_xmitbuf[CMDBUF_MAX]; +#endif u8 hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */ u16 nqos_ssn; #ifdef CONFIG_TX_EARLY_MODE @@ -837,9 +953,6 @@ struct xmit_priv { _mutex ack_tx_mutex; struct submit_ctx ack_tx_ops; u8 seq_no; -#ifdef CONFIG_REMOVE_DUP_TX_STATE - u8 retry_count; -#endif #endif #ifdef CONFIG_TX_AMSDU @@ -857,9 +970,14 @@ struct xmit_priv { u32 amsdu_debug_set_timer; u32 amsdu_debug_timeout; - u32 amsdu_debug_coalesce_one; - u32 amsdu_debug_coalesce_two; +#ifndef AMSDU_DEBUG_MAX_COUNT +#define AMSDU_DEBUG_MAX_COUNT 5 +#endif + u32 amsdu_debug_coalesce[AMSDU_DEBUG_MAX_COUNT]; + u32 amsdu_debug_tasklet; + u32 amsdu_debug_enqueue; + u32 amsdu_debug_dequeue; #endif #ifdef DBG_TXBD_DESC_DUMP BOOLEAN dump_txbd_desc; @@ -871,62 +989,32 @@ struct xmit_priv { _queue rpkt_queue; #endif _lock lock_sctx; - +#ifdef CONFIG_CORE_TXSC + _lock txsc_lock; + u8 txsc_enable; + u8 txsc_debug_mode; + u8 txsc_debug_mask;/* BIT0:core txsc(no use), BIT1: phl txsc enable, BIT2: debug_print */ + + struct sta_info *ptxsc_sta_cached; + + /* for debug */ + u32 txsc_phl_err_cnt1; + u32 txsc_phl_err_cnt2; +#endif /* CONFIG_CORE_TXSC */ }; +#if 0 /*CONFIG_CORE_XMITBUF*/ extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, enum cmdbuf_type buf_type); #define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD) -#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON) -#elif defined(CONFIG_RTL8814B) && defined(CONFIG_PCI_HCI) -extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814be(struct xmit_priv *pxmitpriv, - enum cmdbuf_type buf_type); -#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814be(p, CMDBUF_BEACON) -#else #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON) -#endif extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - +#endif void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); @@ -938,23 +1026,19 @@ struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); +s32 core_tx_free_xmitframe(_adapter *padapter, struct xmit_frame *pxframe); struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - -#ifdef CONFIG_RTW_MGMT_QUEUE -void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue); -u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv); -#endif /* CONFIG_RTW_MGMT_QUEUE */ - extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) -extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +extern s32 rtw_xmitframe_coalesce(_adapter *padapter, struct sk_buff *pkt, + struct xmit_frame *pxmitframe); #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) -extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, + struct sk_buff *pkt, struct xmit_frame *pxmitframe); #endif #ifdef CONFIG_TDLS extern struct tdls_txmgmt *ptxmgmt; @@ -973,6 +1057,8 @@ void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); +u8 rtw_init_lite_xmit_resource(struct dvobj_priv *dvobj); +void rtw_free_lite_xmit_resource(struct dvobj_priv *dvobj); void rtw_alloc_hwxmits(_adapter *padapter); void rtw_free_hwxmits(_adapter *padapter); @@ -982,34 +1068,47 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); void rtw_xmit_dequeue_callback(_workitem *work); void rtw_xmit_queue_set(struct sta_info *sta); void rtw_xmit_queue_clear(struct sta_info *sta); -s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt); -s32 rtw_xmit(_adapter *padapter, _pkt **pkt, u16 os_qid); +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, struct sk_buff *pkt); +s32 rtw_xmit(_adapter *padapter, struct sk_buff **pkt, u16 os_qid); bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) -#ifdef CONFIG_RTW_MGMT_QUEUE -u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); -#endif sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); #endif +#ifdef RTW_PHL_TX +s32 core_tx_prepare_phl(_adapter *padapter, struct xmit_frame *pxframe); +s32 core_tx_call_phl(_adapter *padapter, struct xmit_frame *pxframe, void *txsc_pkt); +s32 core_tx_per_packet(_adapter *padapter, struct xmit_frame *pxframe, + struct sk_buff **pskb, struct sta_info *psta); +s32 rtw_core_tx(_adapter *padapter, struct sk_buff **ppkt, struct sta_info *psta, u16 os_qid); +enum rtw_phl_status rtw_core_tx_recycle(void *drv_priv, struct rtw_xmit_req *txreq); +s32 core_tx_alloc_xmitframe(_adapter *padapter, struct xmit_frame **pxmitframe, u16 os_qid); +#ifdef CONFIG_CORE_TXSC +void core_recycle_txreq_phyaddr(_adapter *padapter, struct rtw_xmit_req *txreq); +s32 core_tx_free_xmitframe(_adapter *padapter, struct xmit_frame *pxframe); +u8 *get_txreq_buffer(_adapter *padapter, u8 **txreq, u8 **pkt_list, u8 **head, u8 **tail); +u8 tos_to_up(u8 tos); +#endif +#endif + +void core_tx_amsdu_tasklet(_adapter *padapter); + u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta); void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj); u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); -s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp); s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp); -s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool erip); s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp); u8 query_ra_short_GI(struct sta_info *psta, u8 bw); u8 qos_acm(u8 acm_mask, u8 priority); -#ifdef CONFIG_XMIT_THREAD_MODE +#if 0 /*def CONFIG_XMIT_THREAD_MODE*/ void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); struct xmit_buf *dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); @@ -1029,7 +1128,7 @@ extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 statu extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority); extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority); -extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); +extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); extern s32 check_amsdu(struct xmit_frame *pxmitframe); extern s32 check_amsdu_tx_support(_adapter *padapter); extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); @@ -1048,8 +1147,6 @@ void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay); void rtw_tx_poll_timer_cancel(_adapter *padapter); #endif -u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); - #ifdef CONFIG_XMIT_ACK int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); @@ -1070,7 +1167,9 @@ void dump_xmit_block(void *sel, _adapter *padapter); void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); bool rtw_is_xmit_blocked(_adapter *padapter); - +#ifdef CONFIG_LAYER2_ROAMING +void dequeuq_roam_pkt(_adapter *padapter); +#endif /* include after declaring struct xmit_buf, in order to avoid warning */ #include diff --git a/include/rtw_xmit_shortcut.h b/include/rtw_xmit_shortcut.h new file mode 100644 index 0000000..e02e205 --- /dev/null +++ b/include/rtw_xmit_shortcut.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTW_XMIT_SHORTCUT_H_ +#define _RTW_XMIT_SHORTCUT_H_ + +#ifdef CONFIG_CORE_TXSC + +#ifndef USE_ONE_WLHDR +#define USE_PREV_WLHDR_BUF +#endif + +#define CORE_TXSC_ENTRY_NUM 8 +#define CORE_TXSC_WLHDR_SIZE (WLHDR_SIZE + SNAP_SIZE + 2 + _AES_IV_LEN_) +#define CORE_TXSC_DEBUG_BUF_SIZE (sizeof(struct rtw_xmit_req) + sizeof(struct rtw_pkt_buf_list)*2) + +enum txsc_action_type { + TXSC_NONE, + TXSC_SKIP, + TXSC_ADD, + TXSC_APPLY, + TXSC_AMSDU_APPLY, + TXSC_DEBUG, +}; + +enum full_cnt_type { + PHL_WD_EMPTY, + PHL_BD_FULL, + PHL_WD_RECYCLE_NOTHING, + PHL_WD_RECYCLE_OK, +}; + +struct txsc_pkt_entry { + enum txsc_action_type step; + struct sta_info *psta; + struct rtw_xmit_req *ptxreq; + + u8 txsc_id; + u8 priority; + + struct sk_buff *xmit_skb[MAX_TXSC_SKB_NUM]; + u8 skb_cnt; +}; + +struct txsc_entry { + u8 txsc_is_used; + u8 txsc_ethdr[ETH_HLEN]; + + /* wlhdr --- */ + #ifdef USE_ONE_WLHDR + u8 *txsc_wlhdr; + #else + u8 txsc_wlhdr[CORE_TXSC_WLHDR_SIZE]; + #endif + u8 txsc_wlhdr_len; + struct rtw_pkt_buf_list txsc_pkt_list0; + /* wlhdr --- */ + + struct rtw_t_meta_data txsc_mdata; + u32 txsc_frag_len;/* for pkt frag check */ + + u8 txsc_phl_id; /* CONFIG_PHL_TXSC */ + u32 txsc_cache_hit; +}; + +void _print_txreq_mdata(struct rtw_t_meta_data *mdata, const char *func); +void _print_txreq_pklist(struct xmit_frame *pxframe, struct rtw_xmit_req *ptxsc_txreq, struct sk_buff *pskb, const char *func); +void txsc_init(_adapter *padapter); +void txsc_clear(_adapter *padapter); +void txsc_dump(_adapter *padapter); +void txsc_dump_data(u8 *buf, u16 buf_len, const char *prefix); +u8 txsc_get_sc_cached_entry(_adapter *padapter, struct sk_buff *pskb, struct txsc_pkt_entry *txsc_pkt); +void txsc_add_sc_cache_entry(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt); +u8 txsc_apply_sc_cached_entry(_adapter *padapter, struct txsc_pkt_entry *txsc_pkt); +#ifdef CONFIG_PCI_HCI +void txsc_fill_txreq_phyaddr(_adapter *padapter, struct rtw_pkt_buf_list *pkt_list); +void txsc_recycle_txreq_phyaddr(_adapter *padapter, struct rtw_xmit_req *txreq); +#endif +void txsc_free_txreq(_adapter *padapter, struct rtw_xmit_req *txreq); +void txsc_debug_sc_entry(_adapter *padapter, struct xmit_frame *pxframe, struct txsc_pkt_entry *txsc_pkt); +void txsc_issue_addbareq_cmd(_adapter *padapter, u8 priority, struct sta_info *psta, u8 issue_when_busy); +#endif /* CONFIG_CORE_TXSC */ +#endif /* _RTW_XMIT_SHORTCUT_H_ */ + diff --git a/include/sdio_ops.h b/include/sdio_ops.h index 74ddeca..467dbca 100644 --- a/include/sdio_ops.h +++ b/include/sdio_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,158 +16,18 @@ #define __SDIO_OPS_H__ -/* Follow mac team suggestion, default I/O fail return value is 0xFF */ -#define SDIO_ERR_VAL8 0xFF -#define SDIO_ERR_VAL16 0xFFFF -#define SDIO_ERR_VAL32 0xFFFFFFFF - #ifdef PLATFORM_LINUX #include #endif -extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops); void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj); -u32 sdio_init(struct dvobj_priv *dvobj); -void sdio_deinit(struct dvobj_priv *dvobj); -int sdio_alloc_irq(struct dvobj_priv *dvobj); -void sdio_free_irq(struct dvobj_priv *dvobj); -u8 sdio_get_num_of_func(struct dvobj_priv *dvobj); - -#if 0 -extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); -extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); -#endif -extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr); -extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v); -extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); -extern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); -extern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); -extern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); - -u32 _sdio_read32(PADAPTER padapter, u32 addr); -s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val); - -extern void sd_int_hdl(PADAPTER padapter); -extern u8 CheckIPSStatus(PADAPTER padapter); +u32 rtw_sdio_init(struct dvobj_priv *dvobj); +void rtw_sdio_deinit(struct dvobj_priv *dvobj); +int rtw_sdio_alloc_irq(struct dvobj_priv *dvobj); +void rtw_sdio_free_irq(struct dvobj_priv *dvobj); +u8 rtw_sdio_get_num_of_func(struct dvobj_priv *dvobj); -#ifdef CONFIG_RTL8188E -extern void InitInterrupt8188ESdio(PADAPTER padapter); -extern void EnableInterrupt8188ESdio(PADAPTER padapter); -extern void DisableInterrupt8188ESdio(PADAPTER padapter); -extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); -extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter); -extern void ClearInterrupt8188ESdio(PADAPTER padapter); -#endif /* CONFIG_RTL8188E */ - -#ifdef CONFIG_RTL8821A -extern void InitInterrupt8821AS(PADAPTER padapter); -extern void EnableInterrupt8821AS(PADAPTER padapter); -extern void DisableInterrupt8821AS(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -void ClearInterrupt8821AS(PADAPTER padapter); -#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ -#endif /* CONFIG_RTL8821A */ - -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \ - || defined(CONFIG_RTL8723F) -u8 rtw_hal_enable_cpwm2(_adapter *adapter); -#endif -extern u8 RecvOnePkt(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ -#ifdef CONFIG_RTL8723B -extern void InitInterrupt8723BSdio(PADAPTER padapter); -extern void InitSysInterrupt8723BSdio(PADAPTER padapter); -extern void EnableInterrupt8723BSdio(PADAPTER padapter); -extern void DisableInterrupt8723BSdio(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter); -extern void ClearInterrupt8723BSdio(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ -#endif - - -#ifdef CONFIG_RTL8192E -extern void InitInterrupt8192ESdio(PADAPTER padapter); -extern void EnableInterrupt8192ESdio(PADAPTER padapter); -extern void DisableInterrupt8192ESdio(PADAPTER padapter); -extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); -extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter); -extern void ClearInterrupt8192ESdio(PADAPTER padapter); -#endif /* CONFIG_RTL8192E */ - -#ifdef CONFIG_RTL8703B -extern void InitInterrupt8703BSdio(PADAPTER padapter); -extern void InitSysInterrupt8703BSdio(PADAPTER padapter); -extern void EnableInterrupt8703BSdio(PADAPTER padapter); -extern void DisableInterrupt8703BSdio(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter); -extern void ClearInterrupt8703BSdio(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ -#endif - -#ifdef CONFIG_RTL8723D -extern void InitInterrupt8723DSdio(PADAPTER padapter); -extern void InitSysInterrupt8723DSdio(PADAPTER padapter); -extern void EnableInterrupt8723DSdio(PADAPTER padapter); -extern void DisableInterrupt8723DSdio(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter); -extern void ClearInterrupt8723DSdio(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ -#endif - -#ifdef CONFIG_RTL8192F -extern void InitInterrupt8192FSdio(PADAPTER padapter); -extern void InitSysInterrupt8192FSdio(PADAPTER padapter); -extern void EnableInterrupt8192FSdio(PADAPTER padapter); -extern void DisableInterrupt8192FSdio(PADAPTER padapter); -extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); -extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter); -extern void ClearInterrupt8192FSdio(PADAPTER padapter); -#endif /* CONFIG_WOWLAN */ -#endif - -#ifdef CONFIG_RTL8188F -extern void InitInterrupt8188FSdio(PADAPTER padapter); -extern void InitSysInterrupt8188FSdio(PADAPTER padapter); -extern void EnableInterrupt8188FSdio(PADAPTER padapter); -extern void DisableInterrupt8188FSdio(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter); -extern void ClearInterrupt8188FSdio(PADAPTER padapter); -#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ -#endif - -#ifdef CONFIG_RTL8188GTV -extern void InitInterrupt8188GTVSdio(PADAPTER padapter); -extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter); -extern void EnableInterrupt8188GTVSdio(PADAPTER padapter); -extern void DisableInterrupt8188GTVSdio(PADAPTER padapter); -extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter); -extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter); -extern void ClearInterrupt8188GTVSdio(PADAPTER padapter); -#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ -#endif /** * rtw_sdio_get_block_size() - Get block size of SDIO transfer @@ -177,31 +37,6 @@ extern void ClearInterrupt8188GTVSdio(PADAPTER padapter); */ static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d) { - return d->intf_data.block_transfer_len; -} - -/** - * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete - * @d struct dvobj_priv* - * @len length to align - * - * Adjust len to align block size, and the new size could be transfered by one - * CMD53. - * If len < block size, it would keep original value, otherwise the value - * would be rounded up by block size. - * - * Return adjusted length. - */ -static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len) -{ - u32 blk_sz; - - - blk_sz = rtw_sdio_get_block_size(d); - if (len <= blk_sz) - return len; - - return _RND(len, blk_sz); + return dvobj_to_sdio(d)->block_transfer_len; } - #endif /* !__SDIO_OPS_H__ */ diff --git a/include/sdio_ops_linux.h b/include/sdio_ops_linux.h index 4bbd8fe..755ce69 100644 --- a/include/sdio_ops_linux.h +++ b/include/sdio_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,40 +15,21 @@ #ifndef __SDIO_OPS_LINUX_H__ #define __SDIO_OPS_LINUX_H__ -#ifndef RTW_HALMAC -u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); - -s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); -s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); -s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); -s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); - -u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); -void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); -void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err); -void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); -void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); -#endif /* RTW_HALMAC */ - -bool rtw_is_sdio30(_adapter *adapter); - -/* The unit of return value is Hz */ -static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d) -{ - return d->intf_data.clock; -} - -s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); -s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); -s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); -s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); - -void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl); +#define SDIO_ERR_VAL8 0xFF +#define SDIO_ERR_VAL16 0xFFFF +#define SDIO_ERR_VAL32 0xFFFFFFFF + + +bool rtw_is_sdio30(struct dvobj_priv *d); +u32 rtw_sdio_get_clock(struct dvobj_priv *d); + + +s32 _sd_read(struct dvobj_priv *d, u32 addr, u32 cnt, void *pdata); +s32 sd_read(struct dvobj_priv *d, u32 addr, u32 cnt, void *pdata); +s32 _sd_write(struct dvobj_priv *d, u32 addr, u32 cnt, void *pdata); +s32 sd_write(struct dvobj_priv *d, u32 addr, u32 cnt, void *pdata); + +void rtw_sdio_set_irq_thd(struct dvobj_priv *d, _thread_hdl_ thd_hdl); int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr, void *buf, size_t len, bool fixed); int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr, diff --git a/include/sta_info.h b/include/sta_info.h index f3c8f36..a15d31a 100644 --- a/include/sta_info.h +++ b/include/sta_info.h @@ -15,17 +15,19 @@ #ifndef __STA_INFO_H_ #define __STA_INFO_H_ -#include +#ifdef CONFIG_CORE_TXSC +#include +#endif + +#ifdef CONFIG_RTW_CORE_RXSC +#include +#endif #define IBSS_START_MAC_ID 2 #define NUM_STA MACID_NUM_SW_LIMIT #ifndef CONFIG_RTW_MACADDR_ACL - #ifdef CONFIG_AP_MODE #define CONFIG_RTW_MACADDR_ACL 1 - #else - #define CONFIG_RTW_MACADDR_ACL 0 - #endif #endif #ifndef CONFIG_RTW_PRE_LINK_STA @@ -162,6 +164,10 @@ struct stainfo_stats { u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */ u32 tx_fail_cnt; /* Read & Clear, in proc_get_tx_stat() */ u32 tx_retry_cnt; /* Read & Clear, in proc_get_tx_stat() */ + #ifdef ROKU_PRIVATE + u64 total_tx_retry_cnt; + u32 rx_retry_cnt; + #endif /* ROKU_PRIVATE */ #ifdef CONFIG_RTW_MESH u32 rx_hwmp_pkts; u32 last_rx_hwmp_pkts; @@ -271,7 +277,11 @@ struct sta_info { /* _list sleep_list; */ /* sleep_q */ /* _list wakeup_list; */ /* wakeup_q */ _adapter *padapter; - struct cmn_sta_info cmn; + + struct rtw_phl_stainfo_t *phl_sta; + + /* move to phl station info */ + /* struct cmn_sta_info cmn; */ struct sta_xmit_priv sta_xmitpriv; struct sta_recv_priv sta_recvpriv; @@ -282,10 +292,6 @@ struct sta_info { #endif _queue sleep_q; unsigned int sleepq_len; -#ifdef CONFIG_RTW_MGMT_QUEUE - _queue mgmt_sleep_q; - unsigned int mgmt_sleepq_len; -#endif uint state; uint qos_option; @@ -304,6 +310,20 @@ struct sta_info { union Keytype dot118021x_UncstKey; union pn48 dot11txpn; /* PN48 used for Unicast xmit */ union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ + s8 hw_decrypted; /* STA HW security is ready or not */ + +#ifdef RTW_PHL_TX + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; +#endif + +#ifdef CONFIG_RTW_CORE_RXSC + u32 rxsc_idx_new; + u32 rxsc_idx_cached; + struct core_rxsc_entry rxsc_entry[NUM_RXSC_ENTRY]; +#endif ATOMIC_T keytrack; #ifdef CONFIG_RTW_MESH /* peer's GTK, RX only */ @@ -334,9 +354,9 @@ struct sta_info { u8 cts2self; u8 rtsen; + u8 hw_rts_en; u8 init_rate; - u8 wireless_mode; /* NETWORK_TYPE */ struct stainfo_stats sta_stats; @@ -382,6 +402,14 @@ struct sta_info { struct vht_priv vhtpriv; #endif +#ifdef CONFIG_80211AX_HE + struct he_priv hepriv; +#endif + +#ifdef CONFIG_RTW_MBO + struct mbo_priv mbopriv; +#endif /* CONFIG_RTW_MBO */ + /* Notes: */ /* STA_Mode: */ /* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO */ @@ -393,10 +421,6 @@ struct sta_info { unsigned int expire_to; - int flags; - - u8 bpairwise_key_installed; - #ifdef CONFIG_AP_MODE _list asoc_list; @@ -407,6 +431,7 @@ struct sta_info { unsigned char chg_txt[128]; u16 capability; + int flags; int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ @@ -417,7 +442,9 @@ struct sta_info { u32 akm_suite_type; + u8 bpairwise_key_installed; #ifdef CONFIG_RTW_80211R + struct rtw_sta_ft_info_t ft_peer; u8 ft_pairwise_key_installed; #endif @@ -529,6 +556,18 @@ struct sta_info { u8 tx_q_enable; struct __queue tx_queue; _workitem tx_q_work; + +#ifdef CONFIG_CORE_TXSC + u32 txsc_cache_hit; + u32 txsc_cache_miss; + u32 txsc_path_slow; + u32 txsc_path_ps; + u8 txsc_cur_idx; /* next entry to add */ + u8 txsc_cache_idx; /* latest cache idx */ + u8 txsc_cache_num; /* num of txsc entry */ + struct txsc_entry txsc_entry_cache[CORE_TXSC_ENTRY_NUM]; + u8 debug_buf[CORE_TXSC_DEBUG_BUF_SIZE]; +#endif /* CONFIG_CORE_TXSC */ }; #ifdef CONFIG_RTW_MESH @@ -754,12 +793,19 @@ int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); -extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); + +extern struct sta_info *rtw_alloc_stainfo_sw(struct sta_priv *stapriv, const u8 *hwaddr); +extern u32 rtw_alloc_stainfo_hw(struct sta_priv *stapriv, struct sta_info *psta); + +extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); +u32 rtw_free_stainfo_sw(_adapter *padapter, struct sta_info *psta); extern void rtw_free_all_stainfo(_adapter *padapter); extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); -extern u32 rtw_init_bcmc_stainfo(_adapter *padapter); extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter); +u32 rtw_free_self_stainfo(_adapter *adapter); +u32 rtw_init_self_stainfo(_adapter *adapter); + #ifdef CONFIG_AP_MODE u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta); void dump_aid_status(void *sel, _adapter *adapter); @@ -770,8 +816,8 @@ extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr); void dump_macaddr_acl(void *sel, _adapter *adapter); #endif -bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr); #if CONFIG_RTW_PRE_LINK_STA +bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr); struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr); void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr); void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv); diff --git a/include/usb_ops.h b/include/usb_ops.h index 6d5435d..6558d38 100644 --- a/include/usb_ops.h +++ b/include/usb_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -20,6 +20,7 @@ #define REALTEK_USB_VENQT_WRITE 0x40 #define REALTEK_USB_VENQT_CMD_REQ 0x05 #define REALTEK_USB_VENQT_CMD_IDX 0x00 +#define REALTEK_USB_BULK_IN_EP_IDX 0 #define REALTEK_USB_IN_INT_EP_IDX 1 enum { @@ -34,115 +35,28 @@ enum { #include #endif /* PLATFORM_LINUX */ -#ifdef CONFIG_RTL8188E -void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif +#define IS_FULL_SPEED_USB(_dvobj) (dvobj_to_usb(_dvobj)->usb_speed == RTW_USB_SPEED_FULL) +#define IS_HIGH_SPEED_USB(_dvobj) (dvobj_to_usb(_dvobj)->usb_speed == RTW_USB_SPEED_HIGH) +#define IS_SUPER_SPEED_USB(_dvobj) (dvobj_to_usb(_dvobj)->usb_speed == RTW_USB_SPEED_SUPER) +#define IS_SUPER_PLUS_SPEED_USB(_dvobj) (dvobj_to_usb(_dvobj)->usb_speed == RTW_USB_SPEED_SUPER_10G) -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) -void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif - -#ifdef CONFIG_RTL8814A -void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif /* CONFIG_RTL8814 */ - -#ifdef CONFIG_RTL8192E -void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif - -#endif - -#ifdef CONFIG_RTL8188F -void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif - -#ifdef CONFIG_RTL8188GTV -void rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif - -#ifdef CONFIG_RTL8723B -void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif -#endif - -#ifdef CONFIG_RTL8703B -void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif /* CONFIG_SUPPORT_USB_INT */ -#endif /* CONFIG_RTL8703B */ - -void usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops); - -#ifdef CONFIG_RTL8723D -void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj); -void rtl8723du_set_intf_ops(struct _io_ops *pops); -void rtl8723du_recv_tasklet(void *priv); -void rtl8723du_xmit_tasklet(void *priv); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif /* CONFIG_SUPPORT_USB_INT */ -#endif /* CONFIG_RTL8723D */ - -#ifdef CONFIG_RTL8710B -void rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj); -void rtl8710bu_set_intf_ops(struct _io_ops *pops); -void rtl8710bu_recv_tasklet(void *priv); -void rtl8710bu_xmit_tasklet(void *priv); -#ifdef CONFIG_SUPPORT_USB_INT -void interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif /* CONFIG_SUPPORT_USB_INT */ -#endif /* CONFIG_RTL8710B */ - -#ifdef CONFIG_RTL8192F -void rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj); -void rtl8192fu_xmit_tasklet(void *priv); -#ifdef CONFIG_SUPPORT_USB_INT -void rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); -#endif /* CONFIG_SUPPORT_USB_INT */ -#endif /* CONFIG_RTL8192F */ - -enum RTW_USB_SPEED { - RTW_USB_SPEED_UNKNOWN = 0, - RTW_USB_SPEED_1_1 = 1, - RTW_USB_SPEED_2 = 2, - RTW_USB_SPEED_3 = 3, -}; - -#define IS_FULL_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1) -#define IS_HIGH_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2) -#define IS_SUPER_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3) - -#define USB_SUPER_SPEED_BULK_SIZE 1024 /* usb 3.0 */ -#define USB_HIGH_SPEED_BULK_SIZE 512 /* usb 2.0 */ -#define USB_FULL_SPEED_BULK_SIZE 64 /* usb 1.1 */ +static inline u16 rtw_usb_bulkout_size(struct dvobj_priv *dvobj) +{ + if (IS_SUPER_SPEED_USB(dvobj)) + return USB_SUPER_SPEED_BULK_SIZE; + else if (IS_HIGH_SPEED_USB(dvobj)) + return USB_HIGH_SPEED_BULK_SIZE; + else + return USB_FULL_SPEED_BULK_SIZE; +} -static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len) +static inline u8 rtw_usb_bulkout_size_boundary(struct dvobj_priv *dvobj, int buf_len) { u8 rst = _TRUE; - if (IS_SUPER_SPEED_USB(padapter)) + if (IS_SUPER_SPEED_USB(dvobj)) rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE; - else if (IS_HIGH_SPEED_USB(padapter)) + else if (IS_HIGH_SPEED_USB(dvobj)) rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE; else rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE; diff --git a/include/usb_ops_linux.h b/include/usb_ops_linux.h index 2c2050d..5b57022 100644 --- a/include/usb_ops_linux.h +++ b/include/usb_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,9 +15,6 @@ #ifndef __USB_OPS_LINUX_H__ #define __USB_OPS_LINUX_H__ -#define VENDOR_CMD_MAX_DATA_LEN 254 -#define FW_START_ADDRESS 0x1000 - #define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10/* ms */ #define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */ @@ -35,15 +32,6 @@ #define RTW_USB_BULKOUT_TIMEOUT 5000/* ms */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) -#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) -#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) -#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) -#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) -#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) -#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) -#endif - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12)) #define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms)) @@ -59,40 +47,20 @@ #endif -#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ -int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); -int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); -int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); -#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ +int rtw_os_urb_resource_alloc(struct data_urb *dataurb); +void rtw_os_urb_resource_free(struct data_urb *dataurb); -unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr); +int usbctrl_vendorreq(struct dvobj_priv *pdvobjpriv, u8 request, u16 value, u16 index, + void *pdata, u16 len, u8 requesttype); -void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); -void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); +u32 rtw_usb_write_port(void *d, u8 *phl_tx_buf_ptr, + u8 bulk_id, u32 len, u8 *pkt_data_buf); -void usb_read_port_cancel(struct intf_hdl *pintfhdl); +void rtw_usb_write_port_cancel(void *d); -u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); -void usb_write_port_cancel(struct intf_hdl *pintfhdl); +u32 rtw_usb_read_port(void *d, void *rxobj, + u8 *inbuf, u32 inbuf_len, u8 bulk_id, u8 minlen); -int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype); -#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ -int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, - u16 value, u16 index, void *pdata, u16 len, u8 requesttype); -#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ +void rtw_usb_read_port_cancel(void *d); -u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr); -u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr); -u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr); -int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); -int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); -int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); -int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); -u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); -void usb_recv_tasklet(unsigned long data); - -#ifdef CONFIG_USB_INTERRUPT_IN_PIPE -void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs); -u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr); -#endif #endif diff --git a/include/wifi.h b/include/wifi.h index d07b349..caaf92d 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -34,6 +34,12 @@ #define WLAN_HDR_A3_LEN 24 #define WLAN_HDR_A4_LEN 30 #define WLAN_HDR_A3_QOS_LEN 26 + +#define WLAN_HDR_A3_HTC_LEN 28 +#define WLAN_HDR_A3_QOS_HTC_LEN 30 +#define WLAN_HDR_A4_HTC_LEN 34 +#define WLAN_HDR_A4_QOS_HTC_LEN 36 + #define WLAN_HDR_A4_QOS_LEN 32 #define WLAN_SSID_MAXLEN 32 #define WLAN_DATA_MAXLEN 2312 @@ -46,6 +52,8 @@ #define WLAN_ETHHDR_LEN 14 #define WLAN_WMM_LEN 24 #define VENDOR_NAME_LEN 20 +#define WLAN_IE_ID_LEN 1 +#define WLAN_IE_LEN_LEN 1 #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE #define WLAN_MAX_VENDOR_IE_LEN 255 @@ -64,10 +72,6 @@ #endif #endif -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN -#define WLAN_MAX_KEEP_ALIVE_IE_LEN 256 -#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - #define P80211CAPTURE_VERSION 0x80211001 /* This value is tested by WiFi 11n Test Plan 5.2.3. @@ -304,7 +308,7 @@ enum WIFI_REG_DOMAIN { *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ } while (0) -#define get_tofr_ds(pframe) ((GetFrDs(pframe) << 1) | GetToDs(pframe)) +#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) #define SetMFrag(pbuf) \ @@ -480,18 +484,18 @@ __inline static unsigned char *get_ta(unsigned char *pframe) __inline static unsigned char *get_da(unsigned char *pframe) { unsigned char *da; - unsigned int to_fr_ds = (GetFrDs(pframe) << 1) | GetToDs(pframe); + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); switch (to_fr_ds) { case 0x00: /* ToDs=0, FromDs=0 */ da = GetAddr1Ptr(pframe); break; - case 0x01: /* ToDs=1, FromDs=0 */ - da = GetAddr3Ptr(pframe); - break; - case 0x02: /* ToDs=0, FromDs=1 */ + case 0x01: /* ToDs=0, FromDs=1 */ da = GetAddr1Ptr(pframe); break; + case 0x02: /* ToDs=1, FromDs=0 */ + da = GetAddr3Ptr(pframe); + break; default: /* ToDs=1, FromDs=1 */ da = GetAddr3Ptr(pframe); break; @@ -504,18 +508,18 @@ __inline static unsigned char *get_da(unsigned char *pframe) __inline static unsigned char *get_sa(unsigned char *pframe) { unsigned char *sa; - unsigned int to_fr_ds = (GetFrDs(pframe) << 1) | GetToDs(pframe); + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); switch (to_fr_ds) { case 0x00: /* ToDs=0, FromDs=0 */ sa = get_addr2_ptr(pframe); break; - case 0x01: /* ToDs=1, FromDs=0 */ - sa = get_addr2_ptr(pframe); - break; - case 0x02: /* ToDs=0, FromDs=1 */ + case 0x01: /* ToDs=0, FromDs=1 */ sa = GetAddr3Ptr(pframe); break; + case 0x02: /* ToDs=1, FromDs=0 */ + sa = get_addr2_ptr(pframe); + break; default: /* ToDs=1, FromDs=1 */ sa = GetAddr4Ptr(pframe); break; @@ -527,25 +531,25 @@ __inline static unsigned char *get_sa(unsigned char *pframe) /* can't apply to mesh mode */ __inline static unsigned char *get_hdr_bssid(unsigned char *pframe) { - unsigned char *bssid= NULL; - unsigned int to_fr_ds = (GetFrDs(pframe) << 1) | GetToDs(pframe); + unsigned char *sa = NULL; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); switch (to_fr_ds) { case 0x00: /* ToDs=0, FromDs=0 */ - bssid = GetAddr3Ptr(pframe); + sa = GetAddr3Ptr(pframe); break; - case 0x01: /* ToDs=1, FromDs=0 */ - bssid = GetAddr1Ptr(pframe); + case 0x01: /* ToDs=0, FromDs=1 */ + sa = get_addr2_ptr(pframe); break; - case 0x02: /* ToDs=0, FromDs=1 */ - bssid = get_addr2_ptr(pframe); + case 0x02: /* ToDs=1, FromDs=0 */ + sa = GetAddr1Ptr(pframe); break; case 0x03: /* ToDs=1, FromDs=1 */ - bssid = GetAddr1Ptr(pframe); + sa = GetAddr1Ptr(pframe); break; } - return bssid; + return sa; } @@ -573,20 +577,8 @@ static inline int IsFrameTypeData(unsigned char *pframe) /*----------------------------------------------------------------------------- - Below is for the security related definition + Below is for common definition ------------------------------------------------------------------------------*/ -#define _RESERVED_FRAME_TYPE_ 0 -#define _SKB_FRAME_TYPE_ 2 -#define _PRE_ALLOCMEM_ 1 -#define _PRE_ALLOCHDR_ 3 -#define _PRE_ALLOCLLCHDR_ 4 -#define _PRE_ALLOCICVHDR_ 5 -#define _PRE_ALLOCMICHDR_ 6 - -#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10) -#define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */ -#define _CRCLNG_ 4 - #define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */ #define _ASOCRSP_IE_OFFSET_ 6 #define _REASOCREQ_IE_OFFSET_ 10 @@ -605,10 +597,8 @@ static inline int IsFrameTypeData(unsigned char *pframe) #define _DSSET_IE_ 3 #define _TIM_IE_ 5 #define _IBSS_PARA_IE_ 6 -#define _COUNTRY_IE_ 7 #define _CHLGETXT_IE_ 16 #define _SUPPORTED_CH_IE_ 36 -#define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ #define _MEAS_REQ_IE_ 38 #define _MEAS_RSP_IE_ 39 #define _RSN_IE_2_ 48 @@ -617,14 +607,16 @@ static inline int IsFrameTypeData(unsigned char *pframe) #define _EXT_SUPPORTEDRATES_IE_ 50 #define _HT_CAPABILITY_IE_ 45 +#define _NEIGHBOR_REPORT_IE_ 52 #define _MDIE_ 54 #define _FTIE_ 55 #define _TIMEOUT_ITVL_IE_ 56 #define _SRC_IE_ 59 -#define _HT_EXTRA_INFO_IE_ 61 +#define _HT_EXTRA_INFO_IE_ 61 /*HT Operation Information*/ #define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ #define _WAPI_IE_ 68 #define _EID_RRM_EN_CAP_IE_ 70 +#define _EID_MULTIPLEBSSID_IE_ 71 /* #define EID_BSSCoexistence 72 */ /* 20/40 BSS Coexistence @@ -636,7 +628,6 @@ static inline int IsFrameTypeData(unsigned char *pframe) #define _LINK_ID_IE_ 101 #define _CH_SWITCH_TIMING_ 104 #define _PTI_BUFFER_STATUS_ 106 -#define _EXT_CAP_IE_ 127 #define _VENDOR_SPECIFIC_IE_ 221 #define _RESERVED47_ 47 @@ -683,6 +674,7 @@ typedef enum _ELEMENT_ID { EID_WPA2 = 48, EID_ExtSupRates = 50, + EID_NEIGHBOR_REPORT = 52, EID_FTIE = 55, /* Defined in 802.11r */ EID_Timeout = 56, /* Defined in 802.11r */ @@ -691,6 +683,8 @@ typedef enum _ELEMENT_ID { EID_HTInfo = 61, EID_SecondaryChnlOffset = 62, + EID_RMEnabledCapability = 70, /* RM Enabled Capability */ + EID_BSSCoexistence = 72, /* 20/40 BSS Coexistence */ EID_BSSIntolerantChlReport = 73, EID_OBSS = 74, /* Overlapping BSS Scan Parameters */ @@ -701,7 +695,6 @@ typedef enum _ELEMENT_ID { EID_PTIControl = 105, /* Defined in 802.11z */ EID_PUBufferStatus = 106, /* Defined in 802.11z */ - EID_EXTCapability = 127, /* Extended Capabilities */ /* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */ EID_Aironet = 133, /* 0x85: Aironet Element for Cisco CCX */ EID_CiscoIP = 149, /* 0x95: IP Address IE for Cisco CCX */ @@ -715,6 +708,7 @@ typedef enum _ELEMENT_ID { EID_WAPI = 68, EID_VHTCapability = 191, /* Based on 802.11ac D2.0 */ EID_VHTOperation = 192, /* Based on 802.11ac D2.0 */ + EID_VHTTransmitPower = 195, EID_AID = 197, /* Based on 802.11ac D4.0 */ EID_OpModeNotification = 199, /* Based on 802.11ac D3.0 */ } ELEMENT_ID, *PELEMENT_ID; @@ -738,24 +732,19 @@ typedef enum _ELEMENT_ID { #define WLAN_ETHCONV_ENCAP 1 #define WLAN_ETHCONV_RFC1042 2 -#define WLAN_ETHCONV_8021h 3 - -#define cap_ESS BIT(0) -#define cap_IBSS BIT(1) -#define cap_CFPollable BIT(2) -#define cap_CFRequest BIT(3) -#define cap_Privacy BIT(4) -#define cap_ShortPremble BIT(5) -#define cap_PBCC BIT(6) -#define cap_ChAgility BIT(7) -#define cap_SpecMgmt BIT(8) -#define cap_QoS BIT(9) -#define cap_ShortSlot BIT(10) -#define cap_APSD BIT(11) -#define cap_RM BIT(12) -#define cap_DSSSOFDM BIT(13) -#define cap_DelayedBACK BIT(14) -#define cap_ImmediateBACK BIT(15) +#define WLAN_ETHCONV_8021h 3 + +#define cap_ESS BIT(0) +#define cap_IBSS BIT(1) +#define cap_CFPollable BIT(2) +#define cap_CFRequest BIT(3) +#define cap_Privacy BIT(4) +#define cap_ShortPremble BIT(5) +#define cap_PBCC BIT(6) +#define cap_ChAgility BIT(7) +#define cap_SpecMgmt BIT(8) +#define cap_QoS BIT(9) +#define cap_ShortSlot BIT(10) /*----------------------------------------------------------------------------- Below is the definition for 802.11i / 802.1x @@ -787,7 +776,7 @@ typedef enum _ELEMENT_ID { /* #ifdef CONFIG_80211N_HT */ -#define set_order_bit(pbuf) \ +#define set_htc_order_bit(pbuf) \ do { \ *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ } while (0) @@ -975,14 +964,6 @@ typedef enum _HT_CAP_AMPDU_DENSITY { #define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 #define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 -/* - * A-PMDU buffer sizes - * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) - */ -#define IEEE80211_MIN_AMPDU_BUF 0x8 -#define IEEE80211_MAX_AMPDU_BUF_HT 0x40 - - /* Spatial Multiplexing Power Save Modes */ #define WLAN_HT_CAP_SM_PS_STATIC 0 #define WLAN_HT_CAP_SM_PS_DYNAMIC 1 @@ -1242,32 +1223,6 @@ enum P2P_ROLE { P2P_ROLE_GO = 3 }; -enum P2P_STATE { - P2P_STATE_NONE = 0, /* P2P disable */ - P2P_STATE_IDLE = 1, /* P2P had enabled and do nothing , buddy adapters is linked */ - P2P_STATE_LISTEN = 2, /* In pure listen state */ - P2P_STATE_SCAN = 3, /* In scan phase */ - P2P_STATE_FIND_PHASE_LISTEN = 4, /* In the listen state of find phase */ - P2P_STATE_FIND_PHASE_SEARCH = 5, /* In the search state of find phase */ - P2P_STATE_TX_PROVISION_DIS_REQ = 6, /* In P2P provisioning discovery */ - P2P_STATE_RX_PROVISION_DIS_RSP = 7, - P2P_STATE_RX_PROVISION_DIS_REQ = 8, - P2P_STATE_GONEGO_ING = 9, /* Doing the group owner negoitation handshake */ - P2P_STATE_GONEGO_OK = 10, /* finish the group negoitation handshake with success */ - P2P_STATE_GONEGO_FAIL = 11, /* finish the group negoitation handshake with failure */ - P2P_STATE_RECV_INVITE_REQ_MATCH = 12, /* receiving the P2P Inviation request and match with the profile. */ - P2P_STATE_PROVISIONING_ING = 13, /* Doing the P2P WPS */ - P2P_STATE_PROVISIONING_DONE = 14, /* Finish the P2P WPS */ - P2P_STATE_TX_INVITE_REQ = 15, /* Transmit the P2P Invitation request */ - P2P_STATE_RX_INVITE_RESP_OK = 16, /* Receiving the P2P Invitation response */ - P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, /* receiving the P2P Inviation request and dismatch with the profile. */ - P2P_STATE_RECV_INVITE_REQ_GO = 18, /* receiving the P2P Inviation request and this wifi is GO. */ - P2P_STATE_RECV_INVITE_REQ_JOIN = 19, /* receiving the P2P Inviation request to join an existing P2P Group. */ - P2P_STATE_RX_INVITE_RESP_FAIL = 20, /* recveing the P2P Inviation response with failure */ - P2P_STATE_RX_INFOR_NOREADY = 21, /* receiving p2p negoitation response with information is not available */ - P2P_STATE_TX_INFOR_NOREADY = 22, /* sending p2p negoitation response with information is not available */ -}; - enum P2P_WPSINFO { P2P_NO_WPSINFO = 0, P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, @@ -1277,14 +1232,6 @@ enum P2P_WPSINFO { #define P2P_PRIVATE_IOCTL_SET_LEN 64 -enum P2P_PROTO_WK_ID { - P2P_FIND_PHASE_WK = 0, - P2P_RESTORE_STATE_WK = 1, - P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, - P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, - P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, -}; - #ifdef CONFIG_P2P_PS enum P2P_PS_STATE { P2P_PS_DISABLE = 0, @@ -1325,12 +1272,6 @@ enum P2P_PS_MODE { #define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) #define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) -enum RTW_ROCH_WK_ID{ - ROCH_RO_CH_WK, - ROCH_CANCEL_RO_CH_WK, - ROCH_AP_ROCH_CH_SWITCH_PROCESS_WK, -}; - #ifdef CONFIG_IOCTL_CFG80211 /* Regulatroy Domain */ struct regd_pair_mapping { @@ -1366,4 +1307,9 @@ struct rtw_regulatory { #endif #endif +#define GET_MBSSID_MAX_BSSID_INDOCATOR(_pEleStart) \ + LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 8) + +#define MBSSID_MAX_BSSID_INDICATOR_OFFSET 3 + #endif /* _WIFI_H_ */ diff --git a/include/wlan_bssdef.h b/include/wlan_bssdef.h index 38de05c..1741942 100644 --- a/include/wlan_bssdef.h +++ b/include/wlan_bssdef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -193,9 +193,11 @@ typedef struct _NDIS_802_11_WEP { #define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) #endif +/*RTW_WKARD_CORE_RSSI_V1 - GEORGIA MUST REFINE*/ typedef struct _WLAN_PHY_INFO { u8 SignalStrength;/* (in percentage) */ u8 SignalQuality;/* (in percentage) */ + s8 rssi; /*dbm*/ u8 Optimum_antenna; /* for Antenna diversity */ u8 is_cck_rate; /* 1:cck_rate */ s8 rx_snr[4]; @@ -235,16 +237,16 @@ typedef struct _WLAN_BSSID_EX { NDIS_802_11_SSID Ssid; NDIS_802_11_SSID mesh_id; u32 Privacy; - NDIS_802_11_RSSI Rssi;/* (in dBM,raw data ,get from PHY) */ NDIS_802_11_CONFIGURATION Configuration; NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; NDIS_802_11_RATES_EX SupportedRates; WLAN_PHY_INFO PhyInfo; +#ifdef CONFIG_STA_MULTIPLE_BSSID + u8 is_mbssid; + u8 mbssid_index; +#endif u32 IELength; u8 IEs[MAX_IE_SZ]; /* (timestamp, beacon interval, and capability information) */ -#ifdef CONFIG_LAYER2_ROAMING - u64 tsf; -#endif } __attribute__((packed)) WLAN_BSSID_EX, *PWLAN_BSSID_EX; diff --git a/include/xmit_osdep.h b/include/xmit_osdep.h index 9bf9c93..2ac4205 100644 --- a/include/xmit_osdep.h +++ b/include/xmit_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,7 +17,7 @@ struct pkt_file { - _pkt *pkt; + struct sk_buff *pkt; SIZE_T pkt_len; /* the remainder length of the open_file */ _buffer *cur_buffer; u8 *buf_start; @@ -25,72 +25,73 @@ struct pkt_file { SIZE_T buf_len; }; -#ifdef PLATFORM_WINDOWS +#define NR_XMITFRAME 1256 +#define NR_XMITFRAME_EXT 32 +#define SZ_XMITFRAME_EXT 1536 /*MGNT frame*/ -#ifdef PLATFORM_OS_XP -#ifdef CONFIG_USB_HCI -#include -#include -#include -#endif -#endif - -#ifdef CONFIG_GSPI_HCI - #define NR_XMITFRAME 64 +#ifdef CONFIG_PCI_HCI + #define SZ_ALIGN_XMITFRAME_EXT 4 #else - #define NR_XMITFRAME 128 + #ifdef USB_XMITBUF_ALIGN_SZ + #define SZ_ALIGN_XMITFRAME_EXT (USB_XMITBUF_ALIGN_SZ) + #else + #define SZ_ALIGN_XMITFRAME_EXT 512 + #endif #endif -#define ETH_ALEN 6 -extern NDIS_STATUS rtw_xmit_entry( - _nic_hdl cnxt, - NDIS_PACKET *pkt, - u32 flags -); +struct xmit_priv; +struct pkt_attrib; +struct sta_xmit_priv; +struct xmit_frame; +struct xmit_buf; -#endif /* PLATFORM_WINDOWS */ #ifdef PLATFORM_FREEBSD -#define NR_XMITFRAME 256 -extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); -extern void rtw_xmit_entry_wrap(struct ifnet *pifp); +extern int rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev); +extern void rtw_xmit_entry_wrap(_nic_hdl pifp); #endif /* PLATFORM_FREEBSD */ #ifdef PLATFORM_LINUX +extern int _rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev); -#define NR_XMITFRAME 256 - -struct xmit_priv; -struct pkt_attrib; -struct sta_xmit_priv; -struct xmit_frame; -struct xmit_buf; - -extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); -extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) +extern netdev_tx_t rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev); +#else +extern int rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev); +#endif +#ifdef RTW_PHL_TX +extern int rtw_os_tx(struct sk_buff *pkt, _nic_hdl pnetdev); +#endif #endif /* PLATFORM_LINUX */ void rtw_os_xmit_schedule(_adapter *padapter); +#if 0 /*CONFIG_CORE_XMITBUF*/ int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag); void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag); - -extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); +#else +u8 rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_frame *pxframe); +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_frame *pxframe); +#endif +extern void rtw_set_tx_chksum_offload(struct sk_buff *pkt, struct pkt_attrib *pattrib); extern uint rtw_remainder_len(struct pkt_file *pfile); -extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); +extern void _rtw_open_pktfile(struct sk_buff *pkt, struct pkt_file *pfile); extern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen); extern sint rtw_endofpktfile(struct pkt_file *pfile); -extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); +extern void rtw_os_pkt_complete(_adapter *padapter, struct sk_buff *pkt); extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); -void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid); -bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid); +void rtw_os_check_wakup_queue(_adapter *padapter, u16 os_qid); +bool rtw_os_check_stop_queue(_adapter *padapter, u16 os_qid); void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed); void dump_os_queue(void *sel, _adapter *padapter); +void rtw_coalesce_tx_amsdu(_adapter *padapter, struct xmit_frame *pxframes[], + int xf_nr, bool amsdu, u32 *pktlen); + #endif /* __XMIT_OSDEP_H_ */ diff --git a/os_dep/linux/custom_gpio_linux.c b/os_dep/linux/custom_gpio_linux.c index 23401b7..c95bbed 100644 --- a/os_dep/linux/custom_gpio_linux.c +++ b/os_dep/linux/custom_gpio_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -22,11 +22,6 @@ #if !(defined ANDROID_2X) -#ifdef CONFIG_RTL8188E -#include -#include -#endif /* CONFIG_RTL8188E */ - #ifndef GPIO_WIFI_POWER #define GPIO_WIFI_POWER -1 #endif /* !GPIO_WIFI_POWER */ @@ -64,15 +59,6 @@ int rtw_wifi_gpio_init(void) if (GPIO_WIFI_POWER > 0) gpio_request(GPIO_WIFI_POWER, "wifi_power"); -#ifdef CONFIG_SDIO_HCI -#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) - if (rtw_mp_mode == 1) { - RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__); - if (GPIO_BT_RESET > 0) - gpio_request(GPIO_BT_RESET , "bt_rst"); - } -#endif -#endif return 0; } @@ -86,16 +72,6 @@ int rtw_wifi_gpio_deinit(void) gpio_free(GPIO_WIFI_RESET); if (GPIO_WIFI_POWER > 0) gpio_free(GPIO_WIFI_POWER); - -#ifdef CONFIG_SDIO_HCI -#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) - if (rtw_mp_mode == 1) { - RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__); - if (GPIO_BT_RESET > 0) - gpio_free(GPIO_BT_RESET); - } -#endif -#endif return 0; } @@ -126,28 +102,6 @@ void rtw_wifi_gpio_wlan_ctrl(int onoff) case WLAN_POWER_ON: break; -#ifdef CONFIG_SDIO_HCI -#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) - case WLAN_BT_PWDN_OFF: - if (rtw_mp_mode == 1) { - RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n", - __FUNCTION__); - if (GPIO_BT_RESET > 0) - gpio_direction_output(GPIO_BT_RESET , 0); - } - break; - - case WLAN_BT_PWDN_ON: - if (rtw_mp_mode == 1) { - RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1 %x\n", - __FUNCTION__, GPIO_BT_RESET); - - if (GPIO_BT_RESET > 0) - gpio_direction_output(GPIO_BT_RESET , 1); - } - break; -#endif -#endif } } @@ -155,21 +109,10 @@ void rtw_wifi_gpio_wlan_ctrl(int onoff) #include -#ifdef CONFIG_RTL8188E -extern int sprd_3rdparty_gpio_wifi_power; -#endif extern int sprd_3rdparty_gpio_wifi_pwd; -#if defined(CONFIG_RTL8723B) -extern int sprd_3rdparty_gpio_bt_reset; -#endif int rtw_wifi_gpio_init(void) { -#if defined(CONFIG_RTL8723B) - if (sprd_3rdparty_gpio_bt_reset > 0) - gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1); -#endif - return 0; } @@ -207,57 +150,19 @@ void rtw_wifi_gpio_wlan_ctrl(int onoff) break; case WLAN_POWER_OFF: -#ifdef CONFIG_RTL8188E -#ifdef CONFIG_WIF1_LDO - RTW_INFO("%s: turn off VDD-WIFI0 1.2V\n", __FUNCTION__); - LDO_TurnOffLDO(LDO_LDO_WIF1); -#endif /* CONFIG_WIF1_LDO */ - - RTW_INFO("%s: turn off VDD-WIFI0 3.3V\n", __FUNCTION__); - LDO_TurnOffLDO(LDO_LDO_WIF0); - - RTW_INFO("%s: call customer specific GPIO(%d) to turn off wifi power\n", - __FUNCTION__, sprd_3rdparty_gpio_wifi_power); - if (sprd_3rdparty_gpio_wifi_power != 65535) - gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0); -#endif break; case WLAN_POWER_ON: -#ifdef CONFIG_RTL8188E - RTW_INFO("%s: call customer specific GPIO(%d) to turn on wifi power\n", - __FUNCTION__, sprd_3rdparty_gpio_wifi_power); - if (sprd_3rdparty_gpio_wifi_power != 65535) - gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1); - - RTW_INFO("%s: turn on VDD-WIFI0 3.3V\n", __FUNCTION__); - LDO_TurnOnLDO(LDO_LDO_WIF0); - LDO_SetVoltLevel(LDO_LDO_WIF0, LDO_VOLT_LEVEL1); - -#ifdef CONFIG_WIF1_LDO - RTW_INFO("%s: turn on VDD-WIFI1 1.2V\n", __func__); - LDO_TurnOnLDO(LDO_LDO_WIF1); - LDO_SetVoltLevel(LDO_LDO_WIF1, LDO_VOLT_LEVEL3); -#endif /* CONFIG_WIF1_LDO */ -#endif break; case WLAN_BT_PWDN_OFF: RTW_INFO("%s: call customer specific GPIO to set bt power down pin to 0\n", __FUNCTION__); -#if defined(CONFIG_RTL8723B) - if (sprd_3rdparty_gpio_bt_reset > 0) - gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0); -#endif break; case WLAN_BT_PWDN_ON: RTW_INFO("%s: callc customer specific GPIO to set bt power down pin to 1\n", __FUNCTION__); -#if defined(CONFIG_RTL8723B) - if (sprd_3rdparty_gpio_bt_reset > 0) - gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1); -#endif break; } } diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 30b1f66..0bc3100 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -15,7 +15,6 @@ #define _IOCTL_CFG80211_C_ #include -#include #ifdef CONFIG_IOCTL_CFG80211 @@ -124,7 +123,7 @@ static const u32 rtw_cipher_suites[] = { .hw_value = (_channel), \ .flags = (_flags), \ .max_antenna_gain = 0, \ - .max_power = 0, \ + .max_power = 30, \ } #define CHAN5G(_channel, _flags) { \ @@ -133,7 +132,7 @@ static const u32 rtw_cipher_suites[] = { .hw_value = (_channel), \ .flags = (_flags), \ .max_antenna_gain = 0, \ - .max_power = 0, \ + .max_power = 30, \ } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) @@ -153,7 +152,7 @@ static const struct wiphy_wowlan_support wowlan_stub = { }; #endif -static struct ieee80211_rate rtw_rates[] = { +static const struct ieee80211_rate rtw_rates[] = { RATETAB_ENT(10, 0x1, 0), RATETAB_ENT(20, 0x2, 0), RATETAB_ENT(55, 0x4, 0), @@ -174,7 +173,7 @@ static struct ieee80211_rate rtw_rates[] = { #define RTW_G_RATES_NUM 12 /* from center_ch_2g */ -static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = { +static const struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = { CHAN2G(1, 2412, 0), CHAN2G(2, 2417, 0), CHAN2G(3, 2422, 0), @@ -192,7 +191,7 @@ static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = { }; /* from center_ch_5g_20m */ -static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { +static const struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { CHAN5G(36, 0), CHAN5G(40, 0), CHAN5G(44, 0), CHAN5G(48, 0), CHAN5G(52, 0), CHAN5G(56, 0), CHAN5G(60, 0), CHAN5G(64, 0), @@ -205,6 +204,33 @@ static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { CHAN5G(165, 0), CHAN5G(169, 0), CHAN5G(173, 0), CHAN5G(177, 0), }; +enum nl80211_band _rtw_band_to_nl80211_band[] = { + [BAND_ON_24G] = NL80211_BAND_2GHZ, + [BAND_ON_5G] = NL80211_BAND_5GHZ, +#if CONFIG_IEEE80211_BAND_6GHZ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) + [BAND_ON_6G] = NL80211_BAND_6GHZ, + #else + [BAND_ON_6G] = NUM_NL80211_BANDS, + #endif +#endif +}; + +enum band_type _nl80211_band_to_rtw_band[] = { + [NL80211_BAND_2GHZ] = BAND_ON_24G, + [NL80211_BAND_5GHZ] = BAND_ON_5G, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + [NL80211_BAND_60GHZ] = BAND_MAX, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) + #if CONFIG_IEEE80211_BAND_6GHZ + [NL80211_BAND_6GHZ] = BAND_ON_6G, + #else + [NL80211_BAND_6GHZ] = BAND_MAX, + #endif +#endif +}; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht) { @@ -218,7 +244,7 @@ static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_cha if (!freq) goto exit; - cfreq = rtw_get_center_ch(ch, bw, offset); + cfreq = rtw_phl_get_center_ch(ch, bw, offset); if (!cfreq) goto exit; cfreq = rtw_ch2freq(cfreq); @@ -257,7 +283,6 @@ static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_cha return ret; } -#ifdef CONFIG_RTW_MESH static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth) { switch (cwidth) { @@ -301,19 +326,21 @@ static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, case NL80211_CHAN_WIDTH_20_NOHT: *ht = 0; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; *ch = chan->hw_value; break; case NL80211_CHAN_WIDTH_20: *ht = 1; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; *ch = chan->hw_value; break; case NL80211_CHAN_WIDTH_40: *ht = 1; *bw = CHANNEL_WIDTH_40; - *offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER; + *offset = (pri_freq > chdef->center_freq1) + ? CHAN_OFFSET_LOWER + : CHAN_OFFSET_UPPER; if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) *ch = chan->hw_value; break; @@ -337,12 +364,12 @@ static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, default: *ht = 0; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width)); rtw_warn_on(1); }; } -#endif /* CONFIG_RTW_MESH */ + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype) { @@ -362,14 +389,14 @@ static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype) static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht) { - rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)); + rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != CHAN_OFFSET_NO_EXT)); if (!ht) return NL80211_CHAN_NO_HT; if (bw >= CHANNEL_WIDTH_40) { - if (offset == HAL_PRIME_CHNL_OFFSET_UPPER) + if (offset == CHAN_OFFSET_LOWER) return NL80211_CHAN_HT40MINUS; - else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER) + else if (offset == CHAN_OFFSET_UPPER) return NL80211_CHAN_HT40PLUS; else rtw_warn_on(1); @@ -394,27 +421,27 @@ static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *cha case NL80211_CHAN_NO_HT: *ht = 0; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; break; case NL80211_CHAN_HT20: *ht = 1; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; break; case NL80211_CHAN_HT40MINUS: *ht = 1; *bw = CHANNEL_WIDTH_40; - *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + *offset = CHAN_OFFSET_LOWER; break; case NL80211_CHAN_HT40PLUS: *ht = 1; *bw = CHANNEL_WIDTH_40; - *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + *offset = CHAN_OFFSET_UPPER; break; default: *ht = 0; *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *offset = CHAN_OFFSET_NO_EXT; RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype)); rtw_warn_on(1); }; @@ -454,11 +481,7 @@ u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) if (started) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0)) - cfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0, 0); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - cfg80211_ch_switch_started_notify(adapter->pnetdev, &chdef, 0, 0, false); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)) /* --- cfg80211_ch_switch_started_notfiy() --- * A new parameter, bool quiet, is added from Linux kernel v5.11, @@ -479,13 +502,7 @@ u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, if (!rtw_cfg80211_allow_ch_switch_notify(adapter)) goto exit; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0)) - cfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0, 0); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2)) - cfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0); -#else cfg80211_ch_switch_notify(adapter->pnetdev, &chdef); -#endif #else int freq = rtw_ch2freq(ch); @@ -532,12 +549,15 @@ void rtw_5g_rates_init(struct ieee80211_rate *rates) ); } -struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band) +struct ieee80211_supported_band *rtw_spt_band_alloc(enum band_type band) { struct ieee80211_supported_band *spt_band = NULL; int n_channels, n_bitrates; - if (band == BAND_ON_2_4G) { + if (rtw_band_to_nl80211_band(band) == NUM_NL80211_BANDS) + goto exit; + + if (band == BAND_ON_24G) { n_channels = MAX_CHANNEL_NUM_2G; n_bitrates = RTW_G_RATES_NUM; } else if (band == BAND_ON_5G) { @@ -550,6 +570,9 @@ struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band) sizeof(struct ieee80211_supported_band) + sizeof(struct ieee80211_channel) * n_channels + sizeof(struct ieee80211_rate) * n_bitrates +#if defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))) + + sizeof(struct ieee80211_sband_iftype_data) * 2 +#endif /* defined(CONFIG_80211AX_HE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) */ ); if (!spt_band) goto exit; @@ -559,8 +582,24 @@ struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band) spt_band->band = rtw_band_to_nl80211_band(band); spt_band->n_channels = n_channels; spt_band->n_bitrates = n_bitrates; +#if defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))) + spt_band->iftype_data = (struct ieee80211_sband_iftype_data *)(((u8 *)spt_band->bitrates) + + sizeof(struct ieee80211_rate) * n_bitrates); + spt_band->n_iftype_data = 0; +#endif /* defined(CONFIG_80211AX_HE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) */ + + if (band == BAND_ON_24G) { + rtw_2g_channels_init(spt_band->channels); + rtw_2g_rates_init(spt_band->bitrates); + } else if (band == BAND_ON_5G) { + rtw_5g_channels_init(spt_band->channels); + rtw_5g_rates_init(spt_band->bitrates); + } + + /* spt_band.ht_cap */ exit: + return spt_band; } @@ -582,6 +621,11 @@ void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) } else { } + +#if defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))) + size += sizeof(struct ieee80211_sband_iftype_data) * 2; +#endif /* defined(CONFIG_80211AX_HE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) */ + rtw_mfree((u8 *)spt_band, size); } @@ -861,14 +905,21 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net notify_ie = pnetwork->network.IEs + _FIXED_IE_LENGTH_; notify_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; + /*RTW_WKARD_CORE_RSSI_V1*/ /* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */ if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { - notify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */ + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) { + notify_signal = 100 * rtw_phl_rssi_to_dbm(padapter->recvinfo.signal_strength); /* dbm */ } else { - notify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */ + notify_signal = 100 * rtw_phl_rssi_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* pnetwork->network.PhyInfo.rssi -dbm */ } - +#if 0 + RTW_INFO("bssid: "MAC_FMT", rssi:%d\t", MAC_ARG(pnetwork->network.MacAddress),notify_signal); + RTW_INFO("ss:%d, sq:%d, orssi:%d\n", + pnetwork->network.PhyInfo.SignalStrength, + pnetwork->network.PhyInfo.SignalQuality, + pnetwork->network.PhyInfo.rssi); +#endif #if 0 RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress)); RTW_INFO("Channel: %d(%d)\n", channel, freq); @@ -1039,9 +1090,9 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ) { - if (!rtw_cfg80211_inform_bss(padapter, scanned)) + if (!rtw_cfg80211_inform_bss(padapter, scanned)){ RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); - else { + } else { /* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */ } } else { @@ -1071,11 +1122,10 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wireless_dev *pwdev = padapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - _irqL irqL; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) +#if defined(CPTCFG_VERSION) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) struct cfg80211_roam_info roam_info ={}; #endif @@ -1090,19 +1140,6 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) if (!MLME_IS_STA(padapter)) return; -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - #if !RTW_P2P_GROUP_INTERFACE - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); - } - #endif - } -#endif /* CONFIG_P2P */ - if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) { WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); struct wlan_network *scanned = pmlmepriv->cur_network_scanned; @@ -1135,7 +1172,7 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) if (!rtw_cfg80211_check_bss(padapter)) RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); - _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->connect_req_lock); if (rtw_to_roam(padapter) > 0) { #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) @@ -1148,12 +1185,8 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) notify_channel = ieee80211_get_channel(wiphy, freq); #endif - #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) - #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) - roam_info.links[0].bssid = cur_network->network.MacAddress; - #else + #if defined(CPTCFG_VERSION) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) roam_info.bssid = cur_network->network.MacAddress; - #endif roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2; roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; roam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6; @@ -1198,14 +1231,13 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) rtw_wdev_free_connect_req(pwdev_priv); - _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->connect_req_lock); } void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) { struct wireless_dev *pwdev = padapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - _irqL irqL; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif @@ -1226,24 +1258,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally if (!MLME_IS_STA(padapter)) return; -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); - - #if RTW_P2P_GROUP_INTERFACE - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT) - #endif - #endif - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - - RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); - } - } -#endif /* CONFIG_P2P */ - - _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->connect_req_lock); if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) { #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) @@ -1275,7 +1290,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally rtw_wdev_free_connect_req(pwdev_priv); - _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->connect_req_lock); } @@ -1311,6 +1326,16 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa , FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr)); goto exit; } + #ifdef CONFIG_RTW_80211R_AP + if ((psta->authalg == WLAN_AUTH_FT) && + !(psta->state & WIFI_FW_ASSOC_SUCCESS)) { + ret = -EINVAL; + RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT + " not ready to setkey before assoc success!\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr)); + goto exit; + } + #endif } if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) { @@ -1336,7 +1361,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } if (wep_key_len > 0) - wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_key_len = wep_key_len <= WLAN_KEY_LEN_WEP40 ? WLAN_KEY_LEN_WEP40 : WLAN_KEY_LEN_WEP104; if (psecuritypriv->bWepDefaultKeyIdxSet == 0) { /* wep default key has not been set, so use this key index as default key. */ @@ -1346,7 +1371,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (wep_key_len == 13) { + if (wep_key_len == WLAN_KEY_LEN_WEP104) { psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } @@ -1423,6 +1448,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); padapter->securitypriv.binstallBIPkey = _TRUE; + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot11wCipher, param->u.crypt.idx); goto exit; } else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) { RTW_INFO(FUNC_ADPT_FMT" set TX GMAC-128 IGTK idx:%u, len:%u\n" @@ -1497,7 +1523,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa if (strcmp(param->u.crypt.alg, "WEP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) @@ -1505,7 +1531,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _TKIP_; /* set mic key */ @@ -1515,36 +1541,36 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _AES_; } else if (strcmp(param->u.crypt.alg, "GCMP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GCMP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _GCMP_; } else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _GCMP_256_; } else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _CCMP_256_; } else if (strcmp(param->u.crypt.alg, "none") == 0) { RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx); psta->dot118021XPrivacy = _NO_PRIVACY_; } else { RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); goto exit; } @@ -1566,7 +1592,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa #ifdef CONFIG_RTW_MESH if (strcmp(param->u.crypt.alg, "CCMP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->group_privacy = _AES_; _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); @@ -1575,7 +1601,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "GCMP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GCMP GTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->group_privacy = _GCMP_; _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); @@ -1584,7 +1610,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->group_privacy = _CCMP_256_; _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len)); @@ -1593,7 +1619,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->group_privacy = _GCMP_256_; _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len)); @@ -1603,7 +1629,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa #ifdef CONFIG_IEEE80211W } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot11wCipher = _BIP_CMAC_128_; _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); @@ -1614,7 +1640,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot11wCipher = _BIP_GMAC_128_; _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); @@ -1625,7 +1651,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set CMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot11wCipher = _BIP_CMAC_256_; _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len)); @@ -1636,7 +1662,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) { RTW_INFO(FUNC_ADPT_FMT" set GMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx, param->u.crypt.key_len); psta->dot11wCipher = _BIP_GMAC_256_; _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len)); @@ -1648,7 +1674,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else if (strcmp(param->u.crypt.alg, "none") == 0) { RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) , param->u.crypt.idx); psta->group_privacy = _NO_PRIVACY_; psta->gtk_bmp &= ~BIT(param->u.crypt.idx); @@ -1656,12 +1682,12 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa #endif /* CONFIG_RTW_MESH */ { RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); goto exit; } #ifdef CONFIG_RTW_MESH - rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy + rtw_ap_set_sta_key(padapter, psta->phl_sta->mac_addr, psta->group_privacy , param->u.crypt.key, param->u.crypt.idx, 1); #endif } @@ -1751,7 +1777,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param /* RTW_INFO("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\n", __func__); */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ + if (MLME_IS_STA(padapter) || MLME_IS_MP(padapter)) {/* sta mode */ #ifdef CONFIG_RTW_80211R if (rtw_ft_roam(padapter)) psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid); @@ -1837,6 +1863,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); psecuritypriv->binstallBIPkey = _TRUE; + rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); } else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) { psecuritypriv->dot11wCipher = _BIP_GMAC_128_; RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK idx:%u, len:%u\n" @@ -1870,13 +1897,6 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) - rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); - } -#endif /* CONFIG_P2P */ - /* WPA/WPA2 key-handshake has completed */ clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE); @@ -1913,9 +1933,6 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - , int link_id -#endif , u8 key_index #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) , bool pairwise @@ -2041,7 +2058,7 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev _rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len); } - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (MLME_IS_STA(padapter)) { #ifdef CONFIG_TDLS if (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) { ptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr); @@ -2078,9 +2095,6 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev } static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - , int link_id -#endif , u8 keyid #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) , bool pairwise @@ -2269,9 +2283,6 @@ static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev } static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - int link_id, -#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) u8 key_index, bool pairwise, const u8 *mac_addr) #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ @@ -2291,11 +2302,8 @@ static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, return 0; } -static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - int link_id, -#endif - u8 key_index +static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, + struct net_device *ndev, u8 key_index #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) , bool unicast, bool multicast #endif @@ -2329,7 +2337,7 @@ static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, struct net_device * psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (psecuritypriv->dot11DefKeylen[key_index] == 13) { + if (psecuritypriv->dot11DefKeylen[key_index] == WLAN_KEY_LEN_WEP104) { psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } @@ -2342,11 +2350,8 @@ static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, struct net_device * } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) -int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy, struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - int link_id, -#endif - u8 key_index) +int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy, + struct net_device *ndev, u8 key_index) { #define SET_DEF_KEY_PARAM_FMT " key_index=%d" #define SET_DEF_KEY_PARAM_ARG , key_index @@ -2471,7 +2476,7 @@ static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, s sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state); if (!sta && plink->scanned) { sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength); + sinfo->signal = rtw_phl_rssi_to_dbm(plink->scanned->network.PhyInfo.SignalStrength); sinfo->filled |= STATION_INFO_INACTIVE_TIME; if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN) sinfo->inactive_time = 0 - 1; @@ -2543,9 +2548,8 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, #endif /* for infra./P2PClient mode */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) - ) { + if (MLME_IS_STA(padapter) + && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { struct wlan_network *cur_network = &(pmlmepriv->cur_network); if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) { @@ -2555,18 +2559,19 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, } sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); + sinfo->signal = rtw_phl_rssi_to_dbm(padapter->recvinfo.signal_strength); sinfo->filled |= STATION_INFO_TX_BITRATE; sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter); } if (psta) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE + if (!MLME_IS_STA(padapter) || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE ) { sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + /* ToDo: need API to query hal_sta->rssi_stat.rssi */ + /* sinfo->signal = rtw_phl_rssi_to_dbm(psta->phl_sta->rssi_stat.rssi); */ } sinfo->filled |= STATION_INFO_INACTIVE_TIME; sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); @@ -2609,7 +2614,7 @@ enum nl80211_iftype { static int cfg80211_rtw_change_iface(struct wiphy *wiphy, struct net_device *ndev, enum nl80211_iftype type, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) && !defined(CPTCFG_VERSION) u32 *flags, #endif struct vif_params *params) @@ -2660,6 +2665,17 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, pmlmeext->action_public_dialog_token = 0xff; } +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + if (type != NL80211_IFTYPE_P2P_CLIENT && type != NL80211_IFTYPE_P2P_GO) { + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) { + if (!rtw_p2p_enable(padapter, P2P_ROLE_DISABLE)) { + ret = -EOPNOTSUPP; + goto exit; + } + } + } +#endif + /* initial default type */ ndev->type = ARPHRD_ETHER; @@ -2682,38 +2698,16 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; - #ifdef CONFIG_P2P - if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { - #if !RTW_P2P_GROUP_INTERFACE - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) - || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) - ) { - /* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */ - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - } - #endif - } - #endif /* CONFIG_P2P */ break; case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; - #ifdef CONFIG_P2P - if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { - #if !RTW_P2P_GROUP_INTERFACE - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - /* it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO) */ - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - } - #endif - } - #endif /* CONFIG_P2P */ break; #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: networkType = Ndis802_11Infrastructure; - if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { + if (change) { if (!rtw_p2p_enable(padapter, P2P_ROLE_CLIENT)) { ret = -EOPNOTSUPP; goto exit; @@ -2723,7 +2717,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, case NL80211_IFTYPE_P2P_GO: networkType = Ndis802_11APMode; - if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { + if (change) { if (!rtw_p2p_enable(padapter, P2P_ROLE_GO)) { ret = -EOPNOTSUPP; goto exit; @@ -2761,8 +2755,12 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, ret = -EPERM; goto exit; } - +#ifdef CONFIG_HWSIM + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY); +#else rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); +#endif + #ifdef CONFIG_MONITOR_MODE_XMIT if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) rtw_indicate_connect(padapter); @@ -2770,8 +2768,8 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_RTW_WDS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) if (params->use_4addr != -1) { - RTW_INFO(FUNC_NDEV_FMT" use_4addr=%d\n" - , FUNC_NDEV_ARG(ndev), params->use_4addr); + RTW_INFO(FUNC_NDEV_FMT" use_4addr=%d\n", + FUNC_NDEV_ARG(ndev), params->use_4addr); adapter_set_use_wds(padapter, params->use_4addr); } #endif @@ -2785,16 +2783,15 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) { struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); - _irqL irqL; -#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE) +#if defined(CPTCFG_VERSION) || (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE) struct cfg80211_scan_info info; memset(&info, 0, sizeof(info)); info.aborted = aborted; #endif - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->scan_req_lock); if (pwdev_priv->scan_request != NULL) { #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s with scan req\n", __FUNCTION__); @@ -2804,7 +2801,7 @@ void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) if (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy) RTW_INFO("error wiphy compare\n"); else -#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE) +#if defined(CPTCFG_VERSION) || (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE) cfg80211_scan_done(pwdev_priv->scan_request, &info); #else cfg80211_scan_done(pwdev_priv->scan_request, aborted); @@ -2816,7 +2813,7 @@ void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) RTW_INFO("%s without scan req\n", __FUNCTION__); #endif } - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->scan_req_lock); } u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) @@ -2830,7 +2827,7 @@ u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) while (rtw_get_passing_time_ms(start) <= timeout_ms) { - if (RTW_CANNOT_RUN(adapter)) + if (RTW_CANNOT_RUN(adapter_to_dvobj(adapter))) break; if (!wdev_priv->scan_request) { @@ -2903,7 +2900,6 @@ static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct c { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); RT_CHANNEL_INFO *chset = rfctl->channel_set; - _irqL irqL; _list *plist, *phead; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); _queue *queue = &(pmlmepriv->scanned_queue); @@ -2920,13 +2916,13 @@ static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct c if (scan_req) target_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid); else { - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->scan_req_lock); if (pwdev_priv->scan_request != NULL) target_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid); - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->scan_req_lock); } - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); @@ -2965,7 +2961,7 @@ static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct c } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); } inline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) @@ -3081,7 +3077,6 @@ u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request int i; u8 ret = _FALSE; _adapter *iface = NULL; - _irqL irqL; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -3105,18 +3100,18 @@ u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request continue; buddy_wdev_priv = adapter_wdev_data(iface); - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); - _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->scan_req_lock); + _rtw_spinlock_bh(&buddy_wdev_priv->scan_req_lock); if (buddy_wdev_priv->scan_request) { pmlmepriv->scanning_via_buddy_intf = _TRUE; - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); pwdev_priv->scan_request = request; ret = _TRUE; } - _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinunlock_bh(&buddy_wdev_priv->scan_req_lock); + _rtw_spinunlock_bh(&pwdev_priv->scan_req_lock); if (ret == _TRUE) goto exit; @@ -3130,7 +3125,6 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab { int i; _adapter *iface = NULL; - _irqL irqL; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mlme_priv *mlmepriv; struct rtw_wdev_priv *wdev_priv; @@ -3147,14 +3141,14 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab wdev_priv = adapter_wdev_data(iface); indicate_buddy_scan = _FALSE; - _enter_critical_bh(&wdev_priv->scan_req_lock, &irqL); + _rtw_spinlock_bh(&wdev_priv->scan_req_lock); if (mlmepriv->scanning_via_buddy_intf == _TRUE) { mlmepriv->scanning_via_buddy_intf = _FALSE; clr_fwstate(mlmepriv, WIFI_UNDER_SURVEY); if (wdev_priv->scan_request) indicate_buddy_scan = _TRUE; } - _exit_critical_bh(&wdev_priv->scan_req_lock, &irqL); + _rtw_spinunlock_bh(&wdev_priv->scan_req_lock); if (indicate_buddy_scan == _TRUE) { rtw_cfg80211_surveydone_event_callback(iface); @@ -3176,7 +3170,6 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy u8 _status = _FALSE; int ret = 0; struct sitesurvey_parm parm; - _irqL irqL; u8 survey_times = 3; u8 survey_times_for_one_ch = 6; struct cfg80211_ssid *ssids = request->ssids; @@ -3223,22 +3216,7 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter) , wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""); -#ifdef CONFIG_RTW_SCAN_RAND -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) - if (request->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { - get_random_mask_addr(pwdev_priv->pno_mac_addr, request->mac_addr, - request->mac_addr_mask); - print_hex_dump(KERN_DEBUG, "random mac_addr: ", - DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr, ETH_ALEN, 1); - } - else - memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN); - -#endif -#endif - - -#if 1 + rtw_init_sitesurvey_parm(padapter, &parm); ssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE); if (ssc_chk == SS_DENY_MP_MODE) @@ -3248,31 +3226,28 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy goto bypass_p2p_chk; #endif #ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (request->n_ssids && ssids - && _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7) - && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) - ) { - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - if (!rtw_p2p_enable(padapter, P2P_ROLE_DEVICE)) { - ret = -EOPNOTSUPP; - goto exit; - } - } else { - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); - #endif + if (request->n_ssids && ssids + && _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) + ) { + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) { + if (!rtw_p2p_enable(padapter, P2P_ROLE_DEVICE)) { + ret = -EOPNOTSUPP; + goto exit; } - rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); - - if (request->n_channels == 3 && - request->channels[0]->hw_value == 1 && - request->channels[1]->hw_value == 6 && - request->channels[2]->hw_value == 11 - ) - social_channel = 1; + } else { + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("%s, role=%d\n", __func__, rtw_p2p_role(pwdinfo)); + #endif } + + if (request->n_channels == 3 && + request->channels[0]->hw_value == 1 && + request->channels[1]->hw_value == 6 && + request->channels[2]->hw_value == 11 + ) + social_channel = 1; + parm.scan_type = RTW_SCAN_P2P; } #endif /*CONFIG_P2P*/ @@ -3293,9 +3268,6 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy ret = -EPERM; goto exit; #endif - #ifdef CONFIG_RTW_REPEATER_SON - case SS_DENY_RSON_SCANING : - #endif case SS_DENY_BLOCK_SCAN : case SS_DENY_SELF_AP_UNDER_WPS : case SS_DENY_SELF_AP_UNDER_LINKING : @@ -3348,155 +3320,6 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy goto check_need_indicate_scan_done; } -#else - - -#ifdef CONFIG_MP_INCLUDED - if (rtw_mp_mode_check(padapter)) { - RTW_INFO("MP mode block Scan request\n"); - ret = -EPERM; - goto exit; - } -#endif - -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (request->n_ssids && ssids - && _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7) - && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) - ) { - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); - else { - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); - #endif - } - rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); - - if (request->n_channels == 3 && - request->channels[0]->hw_value == 1 && - request->channels[1]->hw_value == 6 && - request->channels[2]->hw_value == 11 - ) - social_channel = 1; - } - } -#endif /*CONFIG_P2P*/ - - if (request->ie && request->ie_len > 0) - rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len); - -#ifdef CONFIG_RTW_REPEATER_SON - if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { - RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } -#endif - - if (adapter_wdev_data(padapter)->block_scan == _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } - - rtw_ps_deny(padapter, PS_DENY_SCAN); - ps_denied = _TRUE; - if (_FAIL == rtw_pwr_wakeup(padapter)) { - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } - - if (rtw_is_scan_deny(padapter)) { - RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); -#ifdef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY - ret = -EBUSY; - goto exit; -#else - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; -#endif - } - - /* check fw state*/ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { - -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter)); -#endif - - if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); - - if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) - RTW_INFO("AP mode process WPS\n"); - - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } - } - - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) { - RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); - ret = -EBUSY; - goto check_need_indicate_scan_done; - } - -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) { - RTW_INFO("%s exit due to buddy_intf's mlme state under linking or wps\n", __func__); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - - } else if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY)) { - bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request); - - if (scan_via_buddy == _FALSE) - need_indicate_scan_done = _TRUE; - - goto check_need_indicate_scan_done; - } -#endif /* CONFIG_CONCURRENT_MODE */ - -#ifdef RTW_BUSY_DENY_SCAN - /* - * busy traffic check - * Rules: - * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow - * scan, otherwise goto rule 2. - * 2. Deny scan if any interface is busy, otherwise allow scan. - */ - if (pmlmepriv->lastscantime - && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) > - registry_par->scan_interval_thr) - && rtw_mi_busy_traffic_check(padapter)) { - RTW_WARN(FUNC_ADPT_FMT ": scan abort!! BusyTraffic\n", - FUNC_ADPT_ARG(padapter)); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } -#endif /* RTW_BUSY_DENY_SCAN */ -#endif - -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { - rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); - - if (social_channel == 0) - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); - else - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST); - } -#endif /* CONFIG_P2P */ - - rtw_init_sitesurvey_parm(padapter, &parm); - /* parsing request ssids, n_ssids */ for (i = 0; i < request->n_ssids && ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { #ifdef CONFIG_DEBUG_CFG80211 @@ -3509,7 +3332,7 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy /* no ssid entry, set the scan type as passvie */ if (request->n_ssids == 0) - parm.scan_mode = SCAN_PASSIVE; + parm.scan_mode = RTW_PHL_SCAN_PASSIVE; /* parsing channels, n_channels */ for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { @@ -3521,6 +3344,7 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy } parm.ch_num = i; +#if 0 if (request->n_channels == 1) { for (i = 1; i < survey_times_for_one_ch; i++) _rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel)); @@ -3531,16 +3355,17 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy _rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel)); parm.ch_num = survey_times * request->n_channels; } +#endif - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->scan_req_lock); + _rtw_spinlock_bh(&pmlmepriv->lock); _status = rtw_sitesurvey_cmd(padapter, &parm); if (_status == _SUCCESS) pwdev_priv->scan_request = request; else ret = -1; - _exit_critical_bh(&pmlmepriv->lock, &irqL); - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); + _rtw_spinunlock_bh(&pwdev_priv->scan_req_lock); check_need_indicate_scan_done: if (_TRUE == need_indicate_scan_done) { @@ -3551,7 +3376,7 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy info.aborted = 0; #endif /* the process time of scan results must be over at least 1ms in the newly Android */ - rtw_msleep_os(1); + rtw_msleep_os(1); _rtw_cfg80211_surveydone_event_callback(padapter, request); #if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE) @@ -3573,21 +3398,20 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy return ret; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) && \ - defined(CONFIG_RTW_ABORT_SCAN) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) static void cfg80211_rtw_abort_scan(struct wiphy *wiphy, struct wireless_dev *wdev) { _adapter *padapter = wiphy_to_adapter(wiphy); - RTW_INFO("=>"FUNC_ADPT_FMT" - Abort Scan\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO("=>"FUNC_NDEV_FMT" - Abort Scan\n", FUNC_ADPT_ARG(padapter)); if (wdev->iftype != NL80211_IFTYPE_STATION) { RTW_ERR("abort scan ignored, iftype(%d)\n", wdev->iftype); return; } - rtw_scan_abort(padapter); + rtw_scan_abort(padapter, 0); } -#endif +#endif /* LINUX_VERSION_CODE >= 4.5.0 */ static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) { @@ -3795,6 +3619,8 @@ static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key } else if (key_mgt == WLAN_AKM_SUITE_PSK) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; psecuritypriv->rsn_akm_suite_type = 2; + } else if (key_mgt == WLAN_AKM_SUITE_SAE) { + psecuritypriv->rsn_akm_suite_type = 8; } #ifdef CONFIG_WAPI_SUPPORT else if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK) @@ -3811,9 +3637,7 @@ static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key psecuritypriv->rsn_akm_suite_type = 4; } #endif - else if (key_mgt == WLAN_AKM_SUITE_SAE) { - psecuritypriv->rsn_akm_suite_type = 8; - } else { + else { RTW_INFO("Invalid key mgt: 0x%x\n", key_mgt); /* return -EINVAL; */ } @@ -4044,18 +3868,6 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) adapter_set_use_wds(padapter, 1); #endif - /* TKIP and AES disallow multicast packets until installing group key */ - if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_256_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _CCMP_256_) - /* WPS open need to enable multicast */ - /* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */ - rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); - - exit: if (buf) rtw_mfree(buf, ielen); @@ -4127,7 +3939,7 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype); RTW_INFO("%s: center_freq = %d\n", __func__, pch->center_freq); - pmlmeext->cur_channel = rtw_freq2ch(pch->center_freq); + pmlmeext->chandef.chan = rtw_freq2ch(pch->center_freq); if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ret = -1; @@ -4158,7 +3970,7 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) rtw_set_to_roam(padapter, 0); if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) { - rtw_scan_abort(padapter); + rtw_scan_abort(padapter, 0); LeaveAllPowerSaveMode(padapter); rtw_wdev->iftype = NL80211_IFTYPE_STATION; @@ -4182,12 +3994,11 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) bool rtw_cfg80211_is_connect_requested(_adapter *adapter) { struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); - _irqL irqL; bool requested; - _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->connect_req_lock); requested = pwdev_priv->connect_req ? 1 : 0; - _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->connect_req_lock); return requested; } @@ -4199,17 +4010,18 @@ static int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev) /* if(check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) */ { - rtw_scan_abort(padapter); + rtw_scan_abort(padapter, 0); rtw_join_abort_timeout(padapter, 300); LeaveAllPowerSaveMode(padapter); rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_do_disconnect(padapter); -#endif - RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); - - rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); + if ((MLME_IS_ASOC(padapter) == _TRUE) +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); + RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); /* indicate locally_generated = 0 when suspend */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE); @@ -4233,7 +4045,7 @@ static bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme) { struct rtw_ieee802_11_elems elems; struct rsne_info info; - u8 AKM_SUITE_SAE[] = { 0x00, 0x0f, 0xac, 8 }; + u8 AKM_SUITE_SAE[] = {0x00, 0x0f, 0xac, 8}; int i; if (sme->auth_type != (int)MLME_AUTHTYPE_SHARED_KEY) @@ -4250,8 +4062,8 @@ static bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme) return false; for (i = 0; i < info.akm_cnt; i++) - if (memcmp(info.akm_list + i * RSN_SELECTOR_LEN, - AKM_SUITE_SAE, RSN_SELECTOR_LEN) == 0) + if (_rtw_memcmp(info.akm_list + i * RSN_SELECTOR_LEN, + AKM_SUITE_SAE, RSN_SELECTOR_LEN) == _TRUE) return true; return false; @@ -4260,145 +4072,49 @@ static bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme) #define rtw_check_connect_sae_compat(sme) false #endif -static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_connect_params *sme) +/* todo: move to rtw_security.c ? */ +static int rtw_set_security(struct _ADAPTER *a, + struct cfg80211_connect_params *sme) { + struct security_priv *sec = &a->securitypriv; int ret = 0; - NDIS_802_11_AUTHENTICATION_MODE authmode; - NDIS_802_11_SSID ndis_ssid; - /* u8 matched_by_bssid=_FALSE; */ - /* u8 matched_by_ssid=_FALSE; */ - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - _irqL irqL; -#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT) - rtw_wdev_set_not_indic_disco(pwdev_priv, 1); -#endif - RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev)); - RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n", - sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); + sec->ndisencryptstatus = Ndis802_11EncryptionDisabled; + sec->dot11PrivacyAlgrthm = _NO_PRIVACY_; + sec->dot118021XGrpPrivacy = _NO_PRIVACY_; + sec->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + sec->ndisauthtype = Ndis802_11AuthModeOpen; + sec->auth_alg = WLAN_AUTH_OPEN; + sec->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE; - if (rtw_check_connect_sae_compat(sme)) { - sme->auth_type = (int)MLME_AUTHTYPE_SAE; - psecuritypriv->auth_type = MLME_AUTHTYPE_SAE; - psecuritypriv->auth_alg = WLAN_AUTH_SAE; - RTW_INFO("%s set sme->auth_type for SAE compat\n", __FUNCTION__); - } + ret = rtw_cfg80211_set_wpa_version(sec, sme->crypto.wpa_versions); + if (ret < 0) + return -1; - if (pwdev_priv->block == _TRUE) { - ret = -EBUSY; - RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__); - goto exit; +#ifdef CONFIG_WAPI_SUPPORT + if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) { + a->wapiInfo.bWapiEnable = true; + a->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; + a->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; + } else { + a->wapiInfo.bWapiEnable = false; } +#endif - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _TRUE) { - - _rtw_disconnect(wiphy, ndev); - RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n", - __FUNCTION__, pmlmepriv->fw_state); - } - -#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT - printk("MStar Android!\n"); - if (pwdev_priv->bandroid_scan == _FALSE) { -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) -#endif /* CONFIG_P2P */ - { - ret = -EBUSY; - printk("Android hasn't attached yet!\n"); - goto exit; - } - } -#endif - - if (!sme->ssid || !sme->ssid_len) { - ret = -EINVAL; - goto exit; - } - - if (sme->ssid_len > IW_ESSID_MAX_SIZE) { - ret = -E2BIG; - goto exit; - } - - rtw_ps_deny(padapter, PS_DENY_JOIN); - if (_FAIL == rtw_pwr_wakeup(padapter)) { - ret = -EPERM; - goto cancel_ps_deny; - } - - rtw_mi_scan_abort(padapter, _TRUE); - - rtw_join_abort_timeout(padapter, 300); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) { - ret = -EINVAL; - goto cancel_ps_deny; - } -#endif - - _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); - ndis_ssid.SsidLength = sme->ssid_len; - _rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len); - - RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len); - - - if (sme->bssid) - RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid)); - - - psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; - psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ - psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; - psecuritypriv->auth_alg = WLAN_AUTH_OPEN; - psecuritypriv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE; - -#ifdef CONFIG_WAPI_SUPPORT - padapter->wapiInfo.bWapiEnable = false; -#endif - - ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions); - if (ret < 0) - goto cancel_ps_deny; - -#ifdef CONFIG_WAPI_SUPPORT - if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) { - padapter->wapiInfo.bWapiEnable = true; - padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; - padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; - } -#endif - - ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type); + ret = rtw_cfg80211_set_auth_type(sec, sme->auth_type); #ifdef CONFIG_WAPI_SUPPORT - if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI) - padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm; + if (sec->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI) + a->mlmeextpriv.mlmext_info.auth_algo = sec->dot11AuthAlgrthm; #endif - - - if (ret < 0) - goto cancel_ps_deny; - - RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len); - - ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len); if (ret < 0) - goto cancel_ps_deny; + return -1; if (sme->crypto.n_ciphers_pairwise) { - ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE); + ret = rtw_cfg80211_set_cipher(sec, sme->crypto.ciphers_pairwise[0], _TRUE); if (ret < 0) - goto cancel_ps_deny; + return -1; } /* For WEP Shared auth */ @@ -4410,33 +4126,27 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, wep_key_idx = sme->key_idx; wep_key_len = sme->key_len; - if (sme->key_idx > WEP_KEYS) { - ret = -EINVAL; - goto cancel_ps_deny; - } + if (sme->key_idx > WEP_KEYS) + return -EINVAL; - if (wep_key_len > 0) { - wep_key_len = wep_key_len <= 5 ? 5 : 13; - wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); - pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len); - if (pwep == NULL) { - RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n"); - ret = -ENOMEM; - goto cancel_ps_deny; - } + if (!wep_key_len) + return -EINVAL; + wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len); + if (pwep == NULL) { + RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n"); + return -ENOMEM; + } - _rtw_memset(pwep, 0, wep_total_len); + _rtw_memset(pwep, 0, wep_total_len); - pwep->KeyLength = wep_key_len; - pwep->Length = wep_total_len; + pwep->KeyLength = wep_key_len; + pwep->Length = wep_total_len; - if (wep_key_len == 13) { - padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; - padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_; - } - } else { - ret = -EINVAL; - goto cancel_ps_deny; + if (wep_key_len == 13) { + a->securitypriv.dot11PrivacyAlgrthm = _WEP104_; + a->securitypriv.dot118021XGrpPrivacy = _WEP104_; } pwep->KeyIndex = wep_key_idx; @@ -4444,48 +4154,160 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, _rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength); - if (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) + if (rtw_set_802_11_add_wep(a, pwep) == (u8)_FAIL) ret = -EOPNOTSUPP ; if (pwep) rtw_mfree((u8 *)pwep, wep_total_len); if (ret < 0) - goto cancel_ps_deny; + return ret; } - ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE); + ret = rtw_cfg80211_set_cipher(sec, sme->crypto.cipher_group, _FALSE); if (ret < 0) return ret; if (sme->crypto.n_akm_suites) { - ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]); + ret = rtw_cfg80211_set_key_mgt(sec, sme->crypto.akm_suites[0]); if (ret < 0) - goto cancel_ps_deny; + return ret; } #ifdef CONFIG_8011R else { /*It could be a connection without RSN IEs*/ - psecuritypriv->rsn_akm_suite_type = 0; + sec->rsn_akm_suite_type = 0; } #endif #ifdef CONFIG_WAPI_SUPPORT if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK) - padapter->wapiInfo.bWapiPSK = true; + a->wapiInfo.bWapiPSK = true; else if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT) - padapter->wapiInfo.bWapiPSK = false; + a->wapiInfo.bWapiPSK = false; +#endif + + rtw_set_802_11_authentication_mode(a, sec->ndisauthtype); + + /* rtw_set_802_11_encryption_mode(a, a->securitypriv.ndisencryptstatus); */ + + return 0; +} + +static int rtw_set_wpa_ie(struct _ADAPTER *a, + struct cfg80211_connect_params *sme) +{ + return rtw_cfg80211_set_wpa_ie(a, (u8 *)sme->ie, sme->ie_len); +} + +static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_connect_params *sme) +{ + int ret = 0; + NDIS_802_11_SSID ndis_ssid; + /* u8 matched_by_bssid=_FALSE; */ + /* u8 matched_by_ssid=_FALSE; */ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT) + rtw_wdev_set_not_indic_disco(pwdev_priv, 1); +#endif + + RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev)); + RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n", + sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); + + if (rtw_check_connect_sae_compat(sme)) { + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + sme->auth_type = NL80211_AUTHTYPE_SAE; +#else /* LINUX_VERSION_CODE < 3.8 */ + /* + * When the linux kernel version is less than v3.8, there is no + * NL80211_AUTHTYPE_SAE, also the driver checks psecuritypriv->auth_type + * in rtw_cfg80211_set_auth_type() instead of sme's auth_type in this + * case already. So NL80211_AUTHTYPE_AUTOMATIC is set here when there + * is no NL80211_AUTHTYPE_SAE in this case. + * + * PS: NL80211_AUTHTYPE_AUTOMATIC is NL80211_AUTHTYPE_MAX + 1 + * So it won't conflicts with other defined type in this case. + * + * PS: The driver supports from Linux Kernel 2.6.35. and there is + * NL80211_AUTHTYPE_MAX / NL80211_AUTHTYPE_AUTOMATIC defined + * in linux kernel 2.6.35 already. + */ + sme->auth_type = NL80211_AUTHTYPE_AUTOMATIC; +#endif /* LINUX_VERSION_CODE */ + + psecuritypriv->auth_type = MLME_AUTHTYPE_SAE; + psecuritypriv->auth_alg = WLAN_AUTH_SAE; + RTW_INFO("%s set sme->auth_type for SAE compat\n", __FUNCTION__); + } + + if (pwdev_priv->block == _TRUE) { + ret = -EBUSY; + RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__); + goto exit; + } + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _TRUE) { + + _rtw_disconnect(wiphy, ndev); + RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n", + __FUNCTION__, pmlmepriv->fw_state); + } + + if (!sme->ssid || !sme->ssid_len) { + ret = -EINVAL; + goto exit; + } + + if (sme->ssid_len > IW_ESSID_MAX_SIZE) { + ret = -E2BIG; + goto exit; + } + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -EPERM; + goto cancel_ps_deny; + } + + rtw_mi_scan_abort(padapter, _TRUE); + + rtw_join_abort_timeout(padapter, 300); +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) { + ret = -EINVAL; + goto cancel_ps_deny; + } #endif - authmode = psecuritypriv->ndisauthtype; - rtw_set_802_11_authentication_mode(padapter, authmode); + _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); + ndis_ssid.SsidLength = sme->ssid_len; + _rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len); + + RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len); + + + if (sme->bssid) + RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid)); - /* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ + ret = rtw_set_security(padapter, sme); + if (ret < 0) + goto cancel_ps_deny; + if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm) && (psecuritypriv->dot11PrivacyAlgrthm != _SMS4_)) { + ret = rtw_set_wpa_ie(padapter, sme); + if (ret < 0) + goto cancel_ps_deny; + } #ifdef CONFIG_RTW_MBO rtw_mbo_update_ie_data(padapter, (u8 *)sme->ie, sme->ie_len); #endif - if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid, \ sme->channel ? sme->channel->hw_value : 0) == _FALSE) { ret = -1; @@ -4493,7 +4315,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, } - _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_bh(&pwdev_priv->connect_req_lock); if (pwdev_priv->connect_req) { rtw_wdev_free_connect_req(pwdev_priv); @@ -4506,7 +4328,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, else RTW_WARN(FUNC_NDEV_FMT" alloc connect_req fail\n", FUNC_NDEV_ARG(ndev)); - _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + _rtw_spinunlock_bh(&pwdev_priv->connect_req_lock); RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->dot118021XGrpPrivacy); @@ -4553,23 +4375,6 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, return 0; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) -#ifdef CONFIG_RTW_DEBUG -static const char *nl80211_tx_power_setting_str(int type) -{ - switch (type) { - case NL80211_TX_POWER_AUTOMATIC: - return "AUTO"; - case NL80211_TX_POWER_LIMITED: - return "LIMIT"; - case NL80211_TX_POWER_FIXED: - return "FIX"; - default: - return "UNKNOWN"; - }; -} -#endif /* CONFIG_RTW_DEBUG */ - static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) struct wireless_dev *wdev, @@ -4580,68 +4385,34 @@ static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, enum tx_power_setting type, int dbm) #endif { -#if !((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE)) - int mbm = dbm * 100; -#endif - struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); - _adapter *adapter = wiphy_to_adapter(wiphy); - int ret = -EOPNOTSUPP; - int openhd_override_tx_power_mbm=0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - if (wdev) { - RTW_WARN(FUNC_WIPHY_FMT" wdev specific control is not supported\n", FUNC_WIPHY_ARG(wiphy)); - goto exit; - } -#endif - - RTW_INFO(FUNC_WIPHY_FMT" type:%s(%u) mbm:%d\n", FUNC_WIPHY_ARG(wiphy) - , nl80211_tx_power_setting_str(type), type, mbm); +#if 0 + struct iwm_priv *iwm = wiphy_to_iwm(wiphy); + int ret; switch (type) { case NL80211_TX_POWER_AUTOMATIC: - wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM; - wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM; - ret = 0; - break; - case NL80211_TX_POWER_LIMITED: - if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) { - RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm); - goto exit; - } - wiphy_data->txpwr_total_lmt_mbm = mbm; - wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM; - ret = 0; - break; + return 0; case NL80211_TX_POWER_FIXED: - if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) { - RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm); - goto exit; - } - wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM; - wiphy_data->txpwr_total_target_mbm = mbm; - ret = 0; - break; - default: - RTW_WARN(FUNC_WIPHY_FMT" unknown type:%d\n", FUNC_WIPHY_ARG(wiphy), type); - } - // OpenHD - openhd_override_tx_power_mbm=get_openhd_override_tx_power_mbm(); - if(openhd_override_tx_power_mbm){ - wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM; - wiphy_data->txpwr_total_target_mbm= openhd_override_tx_power_mbm; - // If the chip cannot do the requested tx power, the driver just seems to set tx power index 63" - RTW_WARN("Using openhd_override_tx_power_mbm %d",openhd_override_tx_power_mbm); - } - RTW_WARN(FUNC_WIPHY_FMT" OpenHD cf80211 tx power %s txpwr_total_lmt_mbm:%d txpwr_total_target_mbm%d openhd_override_tx_power_mbm:%d\n", FUNC_WIPHY_ARG(wiphy) - , nl80211_tx_power_setting_str(type), wiphy_data->txpwr_total_lmt_mbm,wiphy_data->txpwr_total_target_mbm, - openhd_override_tx_power_mbm); - - if (ret == 0) - rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000); + if (mbm < 0 || (mbm % 100)) + return -EOPNOTSUPP; -exit: - return ret; + if (!test_bit(IWM_STATUS_READY, &iwm->status)) + return 0; + + ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, + CFG_TX_PWR_LIMIT_USR, + MBM_TO_DBM(mbm) * 2); + if (ret < 0) + return ret; + + return iwm_tx_power_trigger(iwm); + default: + IWM_ERR(iwm, "Unsupported power type: %d\n", type); + return -EOPNOTSUPP; + } +#endif + RTW_INFO("%s\n", __func__); + return 0; } static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, @@ -4650,33 +4421,17 @@ static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, #endif int *dbm) { - struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - s16 mbm; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - if (wdev && wdev_to_ndev(wdev)) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); - mbm = rtw_adapter_get_oper_txpwr_max_mbm(adapter, 1); - RTW_INFO(FUNC_ADPT_FMT" total max: %d mbm\n", FUNC_ADPT_ARG(adapter), mbm); - } else -#endif - { - mbm = rtw_get_oper_txpwr_max_mbm(dvobj, 1); - RTW_INFO(FUNC_WIPHY_FMT" total max: %d mbm\n", FUNC_WIPHY_ARG(wiphy), mbm); - } + RTW_INFO("%s\n", __func__); - *dbm = mbm / MBM_PDBM; + *dbm = (12); return 0; } -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) */ inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter) { struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter); - struct wireless_dev *wdev = rtw_wdev_priv->rtw_wdev; - - return wdev->ps; + return rtw_wdev_priv->power_mgmt; } static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, @@ -4684,10 +4439,13 @@ static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, bool enabled, int timeout) { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter); RTW_INFO(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev), enabled, timeout); + rtw_wdev_priv->power_mgmt = enabled; + #ifdef CONFIG_LPS if (!enabled) rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 0); @@ -4805,14 +4563,122 @@ static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, return 0; } -static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) +#ifdef CONFIG_AP_MODE +void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) { - int ret = 0; - - RTW_INFO("%s\n", __func__); +#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) + s32 freq; + int channel; + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#endif + struct net_device *ndev = padapter->pnetdev; - return ret; -} + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) + { + struct station_info sinfo; + u8 ie_offset; + if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ) + ie_offset = _ASOCREQ_IE_OFFSET_; + else /* WIFI_REASSOCREQ */ + ie_offset = _REASOCREQ_IE_OFFSET_; + + memset(&sinfo, 0, sizeof(sinfo)); + sinfo.filled = STATION_INFO_ASSOC_REQ_IES; + sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset; + sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset; + cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); + } +#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ + channel = pmlmeext->chandef.chan; + freq = rtw_ch2freq(channel); + + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #else /* COMPAT_KERNEL_RELEASE */ + { + /* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() */ + #ifndef CONFIG_PLATFORM_MSTAR + pwdev->iftype = NL80211_IFTYPE_STATION; + #endif /* CONFIG_PLATFORM_MSTAR */ + RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype); + rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len); + RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype); + pwdev->iftype = NL80211_IFTYPE_AP; + /* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */ + } + #endif /* COMPAT_KERNEL_RELEASE */ +#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ + +} + +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason) +{ +#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) + s32 freq; + int channel; + u8 *pmgmt_frame; + uint frame_len; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + u8 mgmt_buf[128] = {0}; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wireless_dev *wdev = padapter->rtw_wdev; +#endif + struct net_device *ndev = padapter->pnetdev; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) + cfg80211_del_sta(ndev, da, GFP_ATOMIC); +#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ + channel = pmlmeext->chandef.chan; + freq = rtw_ch2freq(channel); + + pmgmt_frame = mgmt_buf; + pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH); + + pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); + frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); + + reason = cpu_to_le16(reason); + pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); + + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #else /* COMPAT_KERNEL_RELEASE */ + cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); + /* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */ + #endif /* COMPAT_KERNEL_RELEASE */ +#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ +} + +static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) +{ + int ret = 0; + + RTW_INFO("%s\n", __func__); + + return ret; +} static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) { @@ -4883,16 +4749,16 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de if ((dot11_hdr->frame_ctl & 0x0300) == 0x0300) dot11_hdr_len += 6; - memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr)); - memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr)); + _rtw_memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr)); + _rtw_memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr)); /* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for * for two MAC addresses */ skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2); pdata = (unsigned char *)skb->data; - memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); - memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); + _rtw_memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); + _rtw_memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); RTW_INFO("should be eapol packet\n"); @@ -4966,6 +4832,7 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de pattrib->seqnum = pmlmeext->mgnt_seq; pmlmeext->mgnt_seq++; + pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); @@ -5093,112 +4960,170 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne return ret; } -#ifdef CONFIG_AP_MODE -void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) -{ -#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) - s32 freq; - int channel; - struct wireless_dev *pwdev = padapter->rtw_wdev; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +static struct wireless_dev * +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) +static struct net_device * +#else +static int #endif - struct net_device *ndev = padapter->pnetdev; + cfg80211_rtw_add_virtual_intf( + struct wiphy *wiphy, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) + const char *name, + #else + char *name, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + unsigned char name_assign_type, + #endif + enum nl80211_iftype type, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) && !defined(CPTCFG_VERSION) + u32 *flags, + #endif + struct vif_params *params) +{ + int ret = 0; + struct wireless_dev *wdev = NULL; + struct net_device *ndev = NULL; + _adapter *padapter; + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + rtw_set_rtnl_lock_holder(dvobj, current); -#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) - { - struct station_info sinfo; - u8 ie_offset; - if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ) - ie_offset = _ASOCREQ_IE_OFFSET_; - else /* WIFI_REASSOCREQ */ - ie_offset = _REASOCREQ_IE_OFFSET_; + RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type); - memset(&sinfo, 0, sizeof(sinfo)); - sinfo.filled = STATION_INFO_ASSOC_REQ_IES; - sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset; - sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset; - cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); - } -#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ - channel = pmlmeext->cur_channel; - freq = rtw_ch2freq(channel); + switch (type) { + case NL80211_IFTYPE_MONITOR: + padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */ + ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev); + if (ret == 0) + wdev = ndev->ieee80211_ptr; + break; - #ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); - #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); - #else /* COMPAT_KERNEL_RELEASE */ - { - /* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() */ - #ifndef CONFIG_PLATFORM_MSTAR - pwdev->iftype = NL80211_IFTYPE_STATION; - #endif /* CONFIG_PLATFORM_MSTAR */ - RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype); - rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len); - RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype); - pwdev->iftype = NL80211_IFTYPE_AP; - /* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */ - } - #endif /* COMPAT_KERNEL_RELEASE */ -#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: + case NL80211_IFTYPE_P2P_GO: +#if !RTW_P2P_GROUP_INTERFACE + RTW_ERR("%s, can't add GO/GC interface when RTW_P2P_GROUP_INTERFACE is not defined\n", __func__); + ret = -EOPNOTSUPP; + break; +#endif +#endif + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_AP: +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: +#endif + padapter = dvobj_get_unregisterd_adapter(dvobj); + if (!padapter) { + RTW_WARN("adapter pool empty!\n"); + ret = -ENODEV; + break; + } -} + if (rtw_os_ndev_init(padapter, name) != _SUCCESS) { + RTW_WARN("ndev init fail!\n"); + ret = -ENODEV; + break; + } -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason) -{ -#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) - s32 freq; - int channel; - u8 *pmgmt_frame; - uint frame_len; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - u8 mgmt_buf[128] = {0}; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct wireless_dev *wdev = padapter->rtw_wdev; -#endif - struct net_device *ndev = padapter->pnetdev; + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + if (type == NL80211_IFTYPE_P2P_CLIENT) + rtw_p2p_enable(padapter, P2P_ROLE_CLIENT); + else if (type == NL80211_IFTYPE_P2P_GO) + rtw_p2p_enable(padapter, P2P_ROLE_GO); + #endif - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + ndev = padapter->pnetdev; + wdev = ndev->ieee80211_ptr; + break; -#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) - cfg80211_del_sta(ndev, da, GFP_ATOMIC); -#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ - channel = pmlmeext->cur_channel; - freq = rtw_ch2freq(channel); +#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) + case NL80211_IFTYPE_P2P_DEVICE: + ret = rtw_pd_iface_alloc(wiphy, name, &wdev); + break; +#endif - pmgmt_frame = mgmt_buf; - pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame; + case NL80211_IFTYPE_ADHOC: + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_WDS: + default: + ret = -ENODEV; + RTW_INFO("Unsupported interface type\n"); + break; + } - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + if (ndev) + RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret); + else + RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret); - _rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + rtw_set_rtnl_lock_holder(dvobj, NULL); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + return wdev ? wdev : ERR_PTR(ret); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) + return ndev ? ndev : ERR_PTR(ret); +#else + return ret; +#endif +} - pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); - frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); +static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + struct wireless_dev *wdev +#else + struct net_device *ndev +#endif +) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif + int ret = 0; + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); + _adapter *adapter; + struct rtw_wdev_priv *pwdev_priv; - reason = cpu_to_le16(reason); - pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); + rtw_set_rtnl_lock_holder(dvobj, current); - #ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); - #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); - #else /* COMPAT_KERNEL_RELEASE */ - cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); - /* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */ - #endif /* COMPAT_KERNEL_RELEASE */ -#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ + if (ndev) { + adapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(adapter); + + if (ndev == pwdev_priv->pmon_ndev) { + unregister_netdevice(ndev); + pwdev_priv->pmon_ndev = NULL; + pwdev_priv->ifname_mon[0] = '\0'; + RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev)); + } else { + RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev)); + rtw_os_ndev_unregister(adapter); + } +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_role(&adapter->wdinfo, P2P_ROLE_DISABLE)) + rtw_p2p_enable(adapter, P2P_ROLE_DISABLE); +#endif + } else +#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) { + if (wdev == wiphy_to_pd_wdev(wiphy)) + rtw_pd_iface_free(wiphy); + else { + RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev); + rtw_warn_on(1); + } + } else +#endif + { + ret = -EINVAL; + goto exit; + } + +exit: + rtw_set_rtnl_lock_holder(dvobj, NULL); + return ret; } static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len) @@ -5207,7 +5132,6 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co u8 *pbuf = NULL; uint len, wps_ielen = 0; uint p2p_ielen = 0; - u8 got_p2p_ie = _FALSE; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); /* struct sta_priv *pstapriv = &padapter->stapriv; */ @@ -5221,13 +5145,6 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co if (head_len < 24) return -EINVAL; - #ifdef CONFIG_FW_HANDLE_TXBCN - if (!rtw_ap_nums_check(adapter)) { - RTW_ERR(FUNC_ADPT_FMT"failed, con't support over %d BCN\n", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM); - return -EINVAL; - } - #endif /*CONFIG_FW_HANDLE_TXBCN*/ - pbuf = rtw_zmalloc(head_len + tail_len); if (!pbuf) { ret = -ENOMEM; @@ -5251,48 +5168,28 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co RTW_INFO("add bcn, wps_ielen=%d\n", wps_ielen); #ifdef CONFIG_P2P - if (adapter->wdinfo.driver_interface == DRIVER_CFG80211) { - /* check p2p if enable */ - if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) { - struct wifidirect_info *pwdinfo = &(adapter->wdinfo); - - RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen); - - got_p2p_ie = _TRUE; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + /* check p2p if enable */ + if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) { + struct wifidirect_info *pwdinfo = &(adapter->wdinfo); - if (rtw_p2p_enable(adapter, P2P_ROLE_GO)) { - RTW_INFO("Enable P2P function for the first time\n"); - adapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */ - } else { - ret = -EOPNOTSUPP; - goto exit; - } - } else { - RTW_INFO("enter GO Mode, p2p_ielen=%d\n", p2p_ielen); + RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen); - rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); - pwdinfo->intent = 15; - } + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + RTW_INFO("add p2p beacon whitout GO mode, p2p_role=%d\n", + rtw_p2p_role(pwdinfo)); + ret = -EOPNOTSUPP; + goto exit; } } #endif /* CONFIG_P2P */ - /* pbss_network->IEs will not include p2p_ie, wfd ie */ - rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4); - rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4); + if (adapter_to_dvobj(adapter)->wpas_type == RTW_WPAS_ANDROID) { + /* pbss_network->IEs will not include p2p_ie, wfd ie */ + rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4); + rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4); + } if (rtw_check_beacon_data(adapter, pbuf, len) == _SUCCESS) { -#ifdef CONFIG_P2P - /* check p2p if enable */ - if (got_p2p_ie == _TRUE) { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct wifidirect_info *pwdinfo = &(adapter->wdinfo); - pwdinfo->operating_channel = pmlmeext->cur_channel; - } -#endif /* CONFIG_P2P */ ret = 0; } else ret = -EINVAL; @@ -5346,6 +5243,8 @@ static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + rtw_mi_buddy_set_scan_deny(adapter, 300); + rtw_mi_scan_abort(adapter, _TRUE); rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK); return 0; } @@ -5356,6 +5255,13 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, int ret = 0; _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + if (adapter_to_dvobj(adapter)->wpas_type == RTW_WPAS_W1FI) { + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + /* turn on the beacon send */ + pmlmeext->bstart_bss = _TRUE; + } + RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), settings->hidden_ssid, settings->auth_type); @@ -5364,6 +5270,15 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, goto exit; } +#ifdef RTW_PHL_BCN + { + struct rtw_wifi_role_t *wrole = adapter->phl_role; + + if(wrole) + wrole->bcn_cmn.bcn_added = 0; + } +#endif + /* Kernel < v5.x, the auth_type set as NL80211_AUTHTYPE_AUTOMATIC. if * the AKM SAE in the RSN IE, we have to update the auth_type for SAE in * rtw_check_beacon_data(). @@ -5374,11 +5289,15 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, rtw_mi_scan_abort(adapter, _TRUE); rtw_mi_buddy_set_scan_deny(adapter, 300); - - adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid; ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, settings->beacon.tail, settings->beacon.tail_len); + adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid; + +#ifdef CONFIG_RTW_80211R_AP + rtw_ft_update_assocresp_ies(ndev, settings); +#endif + if (settings->ssid && settings->ssid_len) { WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network; WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network; @@ -5403,6 +5322,37 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, return ret; } +static int rtw_cfg80211_set_assocresp_ies(struct net_device *net, const u8 *buf, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + RTW_INFO("%s, ielen=%d\n", __func__, len); + + if (len <= 0) + goto exit; + + if (pmlmepriv->assoc_rsp) { + u32 free_len = pmlmepriv->assoc_rsp_len; + + pmlmepriv->assoc_rsp_len = 0; + rtw_mfree(pmlmepriv->assoc_rsp, free_len); + pmlmepriv->assoc_rsp = NULL; + } + + pmlmepriv->assoc_rsp = rtw_malloc(len); + if (pmlmepriv->assoc_rsp == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->assoc_rsp, buf, len); + pmlmepriv->assoc_rsp_len = len; + +exit: + return ret; +} + static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev, struct cfg80211_beacon_data *info) { @@ -5411,21 +5361,32 @@ static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *nd RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); +#ifdef not_yet + /* + * @proberesp_ies: extra information element(s) to add into Probe Response + * frames or %NULL + * @proberesp_ies_len: length of proberesp_ies in octets + */ + if (info->proberesp_ies_len > 0) + rtw_cfg80211_set_proberesp_ies(ndev, info->proberesp_ies, info->proberesp_ies_len); +#endif /* not_yet */ + + if (info->assocresp_ies_len > 0) + rtw_cfg80211_set_assocresp_ies(ndev, info->assocresp_ies, info->assocresp_ies_len); + ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); return ret; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2)) -static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev, unsigned int link_id) -#else static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) -#endif { _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + rtw_mi_buddy_set_scan_deny(adapter, 300); + rtw_mi_scan_abort(adapter, _TRUE); rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK); return 0; } @@ -5683,7 +5644,6 @@ static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev struct wlan_network *scanned = NULL; bool acnode = 0; u8 add_new_sta = 0, probe_req = 0; - _irqL irqL; if (params->plink_state != NL80211_PLINK_LISTEN) { RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state)); @@ -5696,7 +5656,7 @@ static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev goto exit; } - _enter_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinlock_bh(&(plink_ctl->lock)); plink = _rtw_mesh_plink_get(padapter, mac); if (plink) @@ -5776,7 +5736,7 @@ static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev ret = -EINVAL; } release_plink_ctl: - _exit_critical_bh(&(plink_ctl->lock), &irqL); + _rtw_spinunlock_bh(&(plink_ctl->lock)); if (probe_req) issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac); @@ -5824,7 +5784,6 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev ) { int ret = 0; - _irqL irqL; _list *phead, *plist; u8 updated = _FALSE; const u8 *target_mac; @@ -5832,11 +5791,18 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct sta_priv *pstapriv = &padapter->stapriv; + bool is_ucast = 1; + u8 use_disassoc = _FALSE; + u16 reason_code = WLAN_REASON_DEAUTH_LEAVING; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) target_mac = mac; #else target_mac = params->mac; + reason_code = params->reason_code; + if (params->subtype == (WIFI_DISASSOC >> 4)) + use_disassoc = _TRUE; #endif RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac); @@ -5850,7 +5816,7 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev if (!target_mac) { RTW_INFO("flush all sta, and cam_entry\n"); - flush_all_cam_entry(padapter); /* clear CAM */ + flush_all_cam_entry(padapter, PHL_CMD_WAIT, 50); /* clear CAM */ #ifdef CONFIG_AP_MODE ret = rtw_sta_flush(padapter, _TRUE); @@ -5861,13 +5827,18 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev RTW_INFO("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac)); - if (target_mac[0] == 0xff && target_mac[1] == 0xff && - target_mac[2] == 0xff && target_mac[3] == 0xff && - target_mac[4] == 0xff && target_mac[5] == 0xff) - return -EINVAL; - + /* broadcast deauth */ + if (is_broadcast_mac_addr(target_mac)) { + if (MLME_IS_AP(padapter)) { + is_ucast = 0; + issue_deauth(padapter, (u8 *)target_mac, WLAN_REASON_PREV_AUTH_NOT_VALID); + } + else { + return -EINVAL; + } + } - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); phead = &pstapriv->asoc_list; plist = get_next(phead); @@ -5878,11 +5849,12 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev plist = get_next(plist); - if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) { + if ((_rtw_memcmp((u8 *)target_mac, psta->phl_sta->mac_addr, ETH_ALEN) || is_ucast == 0) + && !_rtw_memcmp((u8 *)target_mac, padapter->mac_addr, ETH_ALEN) + && !is_broadcast_mac_addr(psta->phl_sta->mac_addr)) { if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) { RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); - #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter)) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -5892,13 +5864,14 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev #endif STA_SET_MESH_PLINK(psta, NULL); - ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_IEEE_802_1X_AUTH_FAILED, _TRUE); + ap_free_sta(padapter, psta, is_ucast, WLAN_REASON_IEEE_802_1X_AUTH_FAILED, _TRUE, _FALSE); psta = NULL; - break; + + if (is_ucast) + break; } - #endif } else { - RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); + RTW_INFO("free psta=%p, aid=%d\n", psta, psta->phl_sta->aid); rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; @@ -5908,23 +5881,22 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev #endif STA_SET_MESH_PLINK(psta, NULL); - /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ + /* _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); */ if (MLME_IS_AP(padapter)) - updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + updated |= ap_free_sta(padapter, psta, is_ucast, reason_code, _TRUE, use_disassoc); else - updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); - /* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ + updated |= ap_free_sta(padapter, psta, is_ucast, WLAN_REASON_DEAUTH_LEAVING, _TRUE, _FALSE); + /* _rtw_spinlock_bh(&pstapriv->asoc_list_lock); */ psta = NULL; - break; + if (is_ucast) + break; } - } - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); @@ -5939,7 +5911,8 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev } -static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev, +static int cfg80211_rtw_change_station(struct wiphy *wiphy, + struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) u8 *mac, #else @@ -5978,7 +5951,8 @@ static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *n #endif /* CONFIG_RTW_MESH */ if (ret) - RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), MAC_ARG(mac), ret); + RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT" ret:%d\n", + FUNC_ADPT_ARG(adapter), MAC_ARG(mac), ret); return ret; } @@ -6011,7 +5985,6 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde #define DBG_DUMP_STATION 0 int ret = 0; - _irqL irqL; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta = NULL; @@ -6023,9 +5996,9 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde if (DBG_DUMP_STATION) RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num); - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); #ifdef CONFIG_RTW_MESH if (MLME_IS_MESH(padapter)) { @@ -6048,7 +6021,7 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde } if (psta) - _rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(mac, psta->phl_sta->mac_addr, ETH_ALEN); #ifdef CONFIG_RTW_MESH else _rtw_memcpy(mac, plink->addr, ETH_ALEN); @@ -6058,7 +6031,8 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde if (psta) { sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + /* ToDo: need API to query hal_sta->rssi_stat.rssi */ + /* sinfo->signal = rtw_phl_rssi_to_dbm(psta->phl_sta->rssi_stat.rssi); */ sinfo->filled |= STATION_INFO_INACTIVE_TIME; sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); } @@ -6072,52 +6046,23 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde return ret; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, struct bss_parameters *params) { - _adapter *adapter = rtw_netdev_priv(ndev); - - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - -if (0) { - if (params->use_cts_prot != -1) - RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot); - if (params->use_short_preamble != -1) - RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble); - if (params->use_short_slot_time != -1) - RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time); - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) - if (params->basic_rates && params->basic_rates_len) { - RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len); - RTW_INFO_DUMP("basic_rates=", params->basic_rates, params->basic_rates_len); - } -#endif -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - if (params->ap_isolate != -1) { - RTW_INFO("ap_isolate=%d\n", params->ap_isolate); - adapter->mlmepriv.ap_isolate = params->ap_isolate ? 1 : 0; - } -#endif - -if (0) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) - if (params->ht_opmode != -1) - RTW_INFO("ht_opmode=0x%04x\n", params->ht_opmode); -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - if (params->p2p_ctwindow != -1) - RTW_INFO("p2p_ctwindow=%d\n", params->p2p_ctwindow); - if (params->p2p_opp_ps != -1) - RTW_INFO("p2p_opp_ps=%d\n", params->p2p_opp_ps); -#endif -} + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); +/* + RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot); + RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble); + RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time); + RTW_INFO("ap_isolate=%d\n", params->ap_isolate); + + RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len); + for(i = 0; i < params->basic_rates_len; i++) + RTW_INFO("basic_rates=%d\n", params->basic_rates[i]); +*/ return 0; + } -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy @@ -6133,10 +6078,11 @@ static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy #endif struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 ac, AIFS, ECWMin, ECWMax, aSifsTime; + u8 ac, AIFS, ECWMin, ECWMax, aSifsTime, vo_cw; u16 TXOP; u8 shift_count = 0; u32 acParm; + struct registry_priv *pregpriv = &padapter->registrypriv; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) ac = params->ac; @@ -6147,6 +6093,12 @@ static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy switch (ac) { case NL80211_TXQ_Q_VO: ac = XMIT_VO_QUEUE; + vo_cw = (pregpriv->vo_edca >> 8) & 0xff; + if(vo_cw) { + /* change vo contention window */ + params->cwmin = vo_cw & 0xf; + params->cwmax = vo_cw >> 4; + } break; case NL80211_TXQ_Q_VI: @@ -6173,8 +6125,8 @@ static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy RTW_INFO("aifs=%u\n", params->aifs); #endif - if (is_supported_5g(pmlmeext->cur_wireless_mode) || - (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + if (WIFI_ROLE_IS_ON_5G(padapter) || + (pmlmeext->cur_wireless_mode & WLAN_MD_11N)) aSifsTime = 16; else aSifsTime = 10; @@ -6198,10 +6150,19 @@ static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy ECWMax = shift_count; - TXOP = le16_to_cpu(params->txop); + TXOP = params->txop; acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + if (ac == XMIT_BE_QUEUE) { + padapter->last_edca = acParm; + acParm = rtw_get_turbo_edca(padapter, AIFS, ECWMin, ECWMax, TXOP); + if (acParm) + padapter->last_edca = acParm; + else + acParm = padapter->last_edca; + } + set_txq_params_cmd(padapter, acParm, ac); return 0; @@ -6221,7 +6182,7 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy _adapter *padapter = wiphy_to_adapter(wiphy); #endif int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq); - int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int chan_offset = CHAN_OFFSET_NO_EXT; int chan_width = CHANNEL_WIDTH_20; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) @@ -6232,19 +6193,19 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy case NL80211_CHAN_NO_HT: case NL80211_CHAN_HT20: chan_width = CHANNEL_WIDTH_20; - chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + chan_offset = CHAN_OFFSET_NO_EXT; break; case NL80211_CHAN_HT40MINUS: chan_width = CHANNEL_WIDTH_40; - chan_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + chan_offset = CHAN_OFFSET_LOWER; break; case NL80211_CHAN_HT40PLUS: chan_width = CHANNEL_WIDTH_40; - chan_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + chan_offset = CHAN_OFFSET_UPPER; break; default: chan_width = CHANNEL_WIDTH_20; - chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + chan_offset = CHAN_OFFSET_NO_EXT; break; } @@ -6257,774 +6218,265 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy } #endif /*#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))*/ -/* -static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_auth_request *req) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +static void rtw_get_chbwoff_from_cfg80211_chan_def( + struct cfg80211_chan_def *chandef, + u8 *ht, u8 *ch, u8 *bw, u8 *offset) { - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - - return 0; -} + struct ieee80211_channel *chan = chandef->chan; -static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_assoc_request *req) -{ - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + *ch = chan->hw_value; + *ht = 1; - return 0; + switch (chandef->width) { + case NL80211_CHAN_WIDTH_20_NOHT: + *ht = 0; + /* fall through */ + case NL80211_CHAN_WIDTH_20: + *bw = CHANNEL_WIDTH_20; + *offset = CHAN_OFFSET_NO_EXT; + break; + case NL80211_CHAN_WIDTH_40: + *bw = CHANNEL_WIDTH_40; + *offset = (chandef->center_freq1 > chan->center_freq) + ? CHAN_OFFSET_UPPER + : CHAN_OFFSET_LOWER; + break; + case NL80211_CHAN_WIDTH_80: + *bw = CHANNEL_WIDTH_80; + *offset = (chandef->center_freq1 > chan->center_freq) + ? CHAN_OFFSET_UPPER + : CHAN_OFFSET_LOWER; + break; + case NL80211_CHAN_WIDTH_160: + *bw = CHANNEL_WIDTH_160; + *offset = (chandef->center_freq1 > chan->center_freq) + ? CHAN_OFFSET_UPPER + : CHAN_OFFSET_LOWER; + break; + case NL80211_CHAN_WIDTH_80P80: + *bw = CHANNEL_WIDTH_80_80; + *offset = (chandef->center_freq1 > chan->center_freq) + ? CHAN_OFFSET_UPPER + : CHAN_OFFSET_LOWER; + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + *bw = CHANNEL_WIDTH_5; + *offset = CHAN_OFFSET_NO_EXT; + break; + case NL80211_CHAN_WIDTH_10: + *bw = CHANNEL_WIDTH_10; + *offset = CHAN_OFFSET_NO_EXT; + break; +#endif + default: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = CHAN_OFFSET_NO_EXT; + RTW_INFO("unsupported cwidth:%u\n", chandef->width); + rtw_warn_on(1); + }; } -*/ +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */ -static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) +static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + , struct cfg80211_chan_def *chandef +#else + , struct ieee80211_channel *chan + , enum nl80211_channel_type channel_type +#endif + ) { - int ret = 0; - uint wps_ielen = 0; - u8 *wps_ie; - u32 p2p_ielen = 0; - u8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04}; - u8 *p2p_ie; - u32 wfd_ielen = 0; - u8 *wfd_ie; - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + _adapter *padapter = wiphy_to_adapter(wiphy); + u8 target_channal, target_offset, target_width, ht_option; - RTW_INFO(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n" + , chandef->chan->center_freq + , chandef->chan->hw_value + , chandef->width + , chandef->center_freq1 + , chandef->center_freq2); +#endif /* CONFIG_DEBUG_CFG80211 */ - if (len > 0) { - wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); - if (wps_ie) { - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen); - #endif + rtw_get_chbwoff_from_cfg80211_chan_def(chandef, + &ht_option, &target_channal, &target_width, &target_offset); +#else +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n" + , chan->center_freq + , chan->hw_value + , channel_type); +#endif /* CONFIG_DEBUG_CFG80211 */ - if (pmlmepriv->wps_beacon_ie) { - u32 free_len = pmlmepriv->wps_beacon_ie_len; - pmlmepriv->wps_beacon_ie_len = 0; - rtw_mfree(pmlmepriv->wps_beacon_ie, free_len); - pmlmepriv->wps_beacon_ie = NULL; - } + rtw_get_chbw_from_nl80211_channel_type(chan, channel_type, + &ht_option, &target_channal, &target_width, &target_offset); +#endif + RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n", + FUNC_ADPT_ARG(padapter), target_channal, + target_width, target_offset); - pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen); - if (pmlmepriv->wps_beacon_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; + rtw_set_chbw_cmd(padapter, target_channal, target_width, + target_offset, RTW_CMDF_WAIT_ACK); - } + return 0; +} - _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen); - pmlmepriv->wps_beacon_ie_len = wps_ielen; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +static int cfg80211_rtw_get_channel(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct cfg80211_chan_def *chandef) +{ + _adapter *padapter = wiphy_to_adapter(wiphy); + struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); + u8 ht_option = 0; + u8 report = 0; + int retval = 1; - update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, RTW_CMDF_WAIT_ACK); + if (MLME_IS_ASOC(padapter)) { +#ifdef CONFIG_80211N_HT + ht_option = padapter->mlmepriv.htpriv.ht_option; +#endif /* CONFIG_80211N_HT */ + report = 1; + } else if (MLME_IS_MONITOR(padapter)) { + /* monitor mode always set to HT + we don't support sniffer No HT */ + ht_option = 1; + report = 1; + } - } + if (report) { + rtw_chbw_to_cfg80211_chan_def(wiphy, chandef, + mlmeext->chandef.chan, mlmeext->chandef.bw, + mlmeext->chandef.offset, ht_option); + retval = 0; + } - /* buf += wps_ielen; */ - /* len -= wps_ielen; */ + return retval; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */ - #ifdef CONFIG_P2P - p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); - if (p2p_ie) { - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen); - #endif +/* +static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_auth_request *req) +{ + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - if (pmlmepriv->p2p_beacon_ie) { - u32 free_len = pmlmepriv->p2p_beacon_ie_len; - pmlmepriv->p2p_beacon_ie_len = 0; - rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len); - pmlmepriv->p2p_beacon_ie = NULL; - } + return 0; +} - pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen); - if (pmlmepriv->p2p_beacon_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; +static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_assoc_request *req) +{ + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - } + return 0; +} +*/ +#endif /* CONFIG_AP_MODE */ - _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen); - pmlmepriv->p2p_beacon_ie_len = p2p_ielen; +void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe) +{ + struct rtw_external_auth_params params; + struct wireless_dev *wdev = padapter->rtw_wdev; + struct net_device *netdev = wdev_to_ndev(wdev); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - } - #endif /* CONFIG_P2P */ + u8 frame[256] = { 0 }; + uint frame_len = 24; + s32 freq = 0; + /* rframe, in this case is null point */ - #ifdef CONFIG_WFD - wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); - if (wfd_ie) { - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen); - #endif + freq = rtw_ch2freq(pmlmeext->chandef.chan); - if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS) - return -EINVAL; - } - #endif /* CONFIG_WFD */ +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO(FUNC_ADPT_FMT": freq(%d, %d)\n", FUNC_ADPT_ARG(padapter), freq); +#endif - pmlmeext->bstart_bss = _TRUE; +#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ + || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH) + params.action = EXTERNAL_AUTH_START; + _rtw_memcpy(params.bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + params.ssid.ssid_len = pmlmeinfo->network.Ssid.SsidLength; + _rtw_memcpy(params.ssid.ssid, pmlmeinfo->network.Ssid.Ssid, + pmlmeinfo->network.Ssid.SsidLength); + params.key_mgmt_suite = 0x8ac0f00; - } + RTW_INFO("external auth: use kernel API: cfg80211_external_auth_request()\n"); + cfg80211_external_auth_request(netdev, + (struct cfg80211_external_auth_params *)¶ms, GFP_ATOMIC); +#elif (KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE) + set_frame_sub_type(frame, WIFI_AUTH); - return ret; + _rtw_memcpy(frame + 4, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(frame + 10, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(frame + 16, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + RTW_PUT_LE32((frame + 18), 0x8ac0f00); + RTW_PUT_LE32((frame + 24), 0x0003); + + if (pmlmeinfo->network.Ssid.SsidLength) { + *(frame + 26) = pmlmeinfo->network.Ssid.SsidLength; + _rtw_memcpy(frame + 27, pmlmeinfo->network.Ssid.Ssid, + pmlmeinfo->network.Ssid.SsidLength); + frame_len = 27 + pmlmeinfo->network.Ssid.SsidLength; + } + RTW_INFO("external auth: with wpa_supplicant patch\n"); + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#endif } -static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) +void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) { - int ret = 0; - uint wps_ielen = 0; - u8 *wps_ie; - u32 p2p_ielen = 0; - u8 *p2p_ie; - u32 wfd_ielen = 0; - u8 *wfd_ie; - _adapter *padapter = (_adapter *)rtw_netdev_priv(net); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wireless_dev *wdev = NULL; + struct wiphy *wiphy = NULL; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("%s, ielen=%d\n", __func__, len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + wiphy = adapter->rtw_wdev->wiphy; +#if defined(RTW_DEDICATED_P2P_DEVICE) + wdev = wiphy_to_pd_wdev(wiphy); +#endif #endif - if (len > 0) { - wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); - if (wps_ie) { - uint attr_contentlen = 0; - u16 uconfig_method, *puconfig_method = NULL; - - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen); - #endif - - if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - u8 sr = 0; - rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); - - if (sr != 0) - RTW_INFO("%s, got sr\n", __func__); - else { - RTW_INFO("GO mode process WPS under site-survey, sr no set\n"); - return ret; - } - } + if (wdev == NULL) + wdev = adapter->rtw_wdev; - if (pmlmepriv->wps_probe_resp_ie) { - u32 free_len = pmlmepriv->wps_probe_resp_ie_len; - pmlmepriv->wps_probe_resp_ie_len = 0; - rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len); - pmlmepriv->wps_probe_resp_ie = NULL; - } + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); - pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen); - if (pmlmepriv->wps_probe_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); +#endif - } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif +} - /* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */ - puconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen); - if (puconfig_method != NULL) { - /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */ - struct wireless_dev *wdev = padapter->rtw_wdev; +void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); + u8 category, action; + int type; - #ifdef CONFIG_DEBUG_CFG80211 - /* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */ - #endif - - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - /* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */ - if (wdev->iftype == NL80211_IFTYPE_P2P_GO) { - uconfig_method = WPS_CM_PUSH_BUTTON; - uconfig_method = cpu_to_be16(uconfig_method); - - *puconfig_method &= ~uconfig_method; - } - #endif - } - - _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); - pmlmepriv->wps_probe_resp_ie_len = wps_ielen; - - } - - /* buf += wps_ielen; */ - /* len -= wps_ielen; */ - - #ifdef CONFIG_P2P - p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); - if (p2p_ie) { - u8 is_GO = _FALSE; - u32 attr_contentlen = 0; - u16 cap_attr = 0; - - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen); - #endif - - /* Check P2P Capability ATTR */ - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { - u8 grp_cap = 0; - /* RTW_INFO( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); */ - cap_attr = le16_to_cpu(cap_attr); - grp_cap = (u8)((cap_attr >> 8) & 0xff); - - is_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE; - - if (is_GO) - RTW_INFO("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap); - } - - - if (is_GO == _FALSE) { - if (pmlmepriv->p2p_probe_resp_ie) { - u32 free_len = pmlmepriv->p2p_probe_resp_ie_len; - pmlmepriv->p2p_probe_resp_ie_len = 0; - rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len); - pmlmepriv->p2p_probe_resp_ie = NULL; - } - - pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen); - if (pmlmepriv->p2p_probe_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - - } - _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen); - pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen; - } else { - if (pmlmepriv->p2p_go_probe_resp_ie) { - u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len; - pmlmepriv->p2p_go_probe_resp_ie_len = 0; - rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len); - pmlmepriv->p2p_go_probe_resp_ie = NULL; - } - - pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen); - if (pmlmepriv->p2p_go_probe_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - - } - _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen); - pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen; - } - - } - #endif /* CONFIG_P2P */ - - - #ifdef CONFIG_WFD - wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); - #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen); - #endif - - if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS) - return -EINVAL; - #endif /* CONFIG_WFD */ - - } - - return ret; - -} - -static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(net); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u8 *ie; - u32 ie_len; - - RTW_INFO("%s, ielen=%d\n", __func__, len); - - if (len <= 0) - goto exit; - - ie = rtw_get_wps_ie(buf, len, NULL, &ie_len); - if (ie && ie_len) { - if (pmlmepriv->wps_assoc_resp_ie) { - u32 free_len = pmlmepriv->wps_assoc_resp_ie_len; - - pmlmepriv->wps_assoc_resp_ie_len = 0; - rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len); - pmlmepriv->wps_assoc_resp_ie = NULL; - } - - pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); - if (pmlmepriv->wps_assoc_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - } - _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len); - pmlmepriv->wps_assoc_resp_ie_len = ie_len; - } -#ifdef CONFIG_P2P - ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len); - if (ie && ie_len) { - if (pmlmepriv->p2p_assoc_resp_ie) { - u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len; - - pmlmepriv->p2p_assoc_resp_ie_len = 0; - rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len); - pmlmepriv->p2p_assoc_resp_ie = NULL; - } - - pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len); - if (pmlmepriv->p2p_assoc_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - } - _rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len); - pmlmepriv->p2p_assoc_resp_ie_len = ie_len; - } -#endif -#ifdef CONFIG_WFD - ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len); - if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS) - return -EINVAL; -#endif - -exit: - return ret; -} - -int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, - int type) -{ - int ret = 0; - uint wps_ielen = 0; - u32 p2p_ielen = 0; - -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("%s, ielen=%d\n", __func__, len); -#endif - - if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0)) - #ifdef CONFIG_P2P - || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0)) - #endif - ) { - if (net != NULL) { - switch (type) { - case 0x1: /* BEACON */ - ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len); - break; - case 0x2: /* PROBE_RESP */ - ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); - #ifdef CONFIG_P2P - if (ret == 0) - adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time(); - #endif - break; - case 0x4: /* ASSOC_RESP */ - ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); - break; - } - } - } - - return ret; - -} -#endif /* CONFIG_AP_MODE */ - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) -static struct wireless_dev * -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) -static struct net_device * -#else -static int -#endif - cfg80211_rtw_add_virtual_intf( - struct wiphy *wiphy, - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) - const char *name, - #else - char *name, - #endif - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - unsigned char name_assign_type, - #endif - enum nl80211_iftype type, - #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) - u32 *flags, - #endif - struct vif_params *params) -{ - int ret = 0; - struct wireless_dev *wdev = NULL; - struct net_device *ndev = NULL; - _adapter *padapter; - struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - - rtw_set_rtnl_lock_holder(dvobj, current); - - RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type); - - switch (type) { - case NL80211_IFTYPE_MONITOR: - padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */ - ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev); - if (ret == 0) - wdev = ndev->ieee80211_ptr; - break; - -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - case NL80211_IFTYPE_P2P_CLIENT: - case NL80211_IFTYPE_P2P_GO: -#endif - case NL80211_IFTYPE_STATION: - case NL80211_IFTYPE_AP: -#ifdef CONFIG_RTW_MESH - case NL80211_IFTYPE_MESH_POINT: -#endif - padapter = dvobj_get_unregisterd_adapter(dvobj); - if (!padapter) { - RTW_WARN("adapter pool empty!\n"); - ret = -ENODEV; - break; - } - - #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) - #if defined(CONFIG_P2P) && ((KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE) || defined(COMPAT_KERNEL_RELEASE)) - if ((type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO) && (padapter->iface_id != padapter->registrypriv.sel_p2p_iface)) { - RTW_ERR("%s, iface_id:%d is not P2P interface!\n", __func__, padapter->iface_id); - ret = -EOPNOTSUPP; - break; - } - #endif - #endif - - if (rtw_os_ndev_init(padapter, name) != _SUCCESS) { - RTW_WARN("ndev init fail!\n"); - ret = -ENODEV; - break; - } - #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - if (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO) - rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); - #endif - ndev = padapter->pnetdev; - wdev = ndev->ieee80211_ptr; - break; - -#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) - case NL80211_IFTYPE_P2P_DEVICE: - ret = rtw_pd_iface_alloc(wiphy, name, &wdev); - break; -#endif - - case NL80211_IFTYPE_ADHOC: - case NL80211_IFTYPE_AP_VLAN: - case NL80211_IFTYPE_WDS: - default: - ret = -ENODEV; - RTW_INFO("Unsupported interface type\n"); - break; - } - - if (ndev) - RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret); - else - RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret); - - rtw_set_rtnl_lock_holder(dvobj, NULL); - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - return wdev ? wdev : ERR_PTR(ret); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) - return ndev ? ndev : ERR_PTR(ret); -#else - return ret; -#endif -} - -static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev -#else - struct net_device *ndev -#endif -) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct net_device *ndev = wdev_to_ndev(wdev); -#endif - int ret = 0; - struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - _adapter *adapter; - struct rtw_wdev_priv *pwdev_priv; - - rtw_set_rtnl_lock_holder(dvobj, current); - - if (ndev) { - adapter = (_adapter *)rtw_netdev_priv(ndev); - pwdev_priv = adapter_wdev_data(adapter); - - if (ndev == pwdev_priv->pmon_ndev) { - unregister_netdevice(ndev); - pwdev_priv->pmon_ndev = NULL; - pwdev_priv->ifname_mon[0] = '\0'; - RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev)); - } else { - RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev)); - rtw_os_ndev_unregister(adapter); - } - } else -#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) - if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) { - if (wdev == wiphy_to_pd_wdev(wiphy)) - rtw_pd_iface_free(wiphy); - else { - RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev); - rtw_warn_on(1); - } - } else -#endif - { - ret = -EINVAL; - goto exit; - } - -exit: - rtw_set_rtnl_lock_holder(dvobj, NULL); - return ret; -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) -static int cfg80211_rtw_get_channel(struct wiphy *wiphy, - struct wireless_dev *wdev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2)) - unsigned int link_id, -#endif - struct cfg80211_chan_def *chandef) -{ - _adapter *padapter = wiphy_to_adapter(wiphy); - struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); - u8 ht_option = 0; - u8 report = 0; - int retval = 1; - - if (MLME_IS_ASOC(padapter)) { -#ifdef CONFIG_80211N_HT - ht_option = padapter->mlmepriv.htpriv.ht_option; -#endif /* CONFIG_80211N_HT */ - report = 1; - } else if (MLME_IS_MONITOR(padapter)) { - /* monitor mode always set to HT - we don't support sniffer No HT */ - ht_option = 1; - report = 1; - } - - if (report) { - rtw_chbw_to_cfg80211_chan_def(wiphy, chandef, - mlmeext->cur_channel, mlmeext->cur_bwmode, - mlmeext->cur_ch_offset, ht_option); - retval = 0; - } - - return retval; -} - -static void rtw_get_chbwoff_from_cfg80211_chan_def( - struct cfg80211_chan_def *chandef, - u8 *ht, u8 *ch, u8 *bw, u8 *offset) -{ - struct ieee80211_channel *chan = chandef->chan; - - *ch = chan->hw_value; - *ht = 1; - - switch (chandef->width) { - case NL80211_CHAN_WIDTH_20_NOHT: - *ht = 0; - /* fall through */ - case NL80211_CHAN_WIDTH_20: - *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - case NL80211_CHAN_WIDTH_40: - *bw = CHANNEL_WIDTH_40; - *offset = (chandef->center_freq1 > chan->center_freq) ? - HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER; - break; - case NL80211_CHAN_WIDTH_80: - *bw = CHANNEL_WIDTH_80; - *offset = (chandef->center_freq1 > chan->center_freq) ? - HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER; - break; - case NL80211_CHAN_WIDTH_160: - *bw = CHANNEL_WIDTH_160; - *offset = (chandef->center_freq1 > chan->center_freq) ? - HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER; - break; - case NL80211_CHAN_WIDTH_80P80: - *bw = CHANNEL_WIDTH_80_80; - *offset = (chandef->center_freq1 > chan->center_freq) ? - HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER; - break; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - case NL80211_CHAN_WIDTH_5: - *bw = CHANNEL_WIDTH_5; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - case NL80211_CHAN_WIDTH_10: - *bw = CHANNEL_WIDTH_10; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; -#endif - default: - *ht = 0; - *bw = CHANNEL_WIDTH_20; - *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - RTW_INFO("unsupported cwidth:%u\n", chandef->width); - rtw_warn_on(1); - }; -} -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */ - -static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - , struct cfg80211_chan_def *chandef -#else - , struct ieee80211_channel *chan - , enum nl80211_channel_type channel_type -#endif - ) -{ - _adapter *padapter = wiphy_to_adapter(wiphy); - u8 target_channal, target_offset, target_width, ht_option; - int openhd_override_channel=0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n" - , chandef->chan->center_freq - , chandef->chan->hw_value - , chandef->width - , chandef->center_freq1 - , chandef->center_freq2); -#endif /* CONFIG_DEBUG_CFG80211 */ - - rtw_get_chbwoff_from_cfg80211_chan_def(chandef, - &ht_option, &target_channal, &target_width, &target_offset); -#else -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n" - , chan->center_freq - , chan->hw_value - , channel_type); -#endif /* CONFIG_DEBUG_CFG80211 */ - - rtw_get_chbw_from_nl80211_channel_type(chan, channel_type, - &ht_option, &target_channal, &target_width, &target_offset); -#endif - openhd_override_channel=get_openhd_override_channel(); - if(openhd_override_channel){ - target_channal=openhd_override_channel; - RTW_WARN("OpenHD: using openhd_override_channel"); - } - - RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n", - FUNC_ADPT_ARG(padapter), target_channal, - target_width, target_offset); - if(true){ - RTW_WARN(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d OpenHD channel debug override:%d\n", - FUNC_ADPT_ARG(padapter), target_channal, - target_width, target_offset,openhd_override_channel); - } - - rtw_set_chbw_cmd(padapter, target_channal, target_width, - target_offset, RTW_CMDF_WAIT_ACK); - - return 0; -} - -void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe) -{ - struct rtw_external_auth_params params; - struct wireless_dev *wdev = padapter->rtw_wdev; - struct net_device *netdev = wdev_to_ndev(wdev); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - u8 frame[256] = { 0 }; - uint frame_len = 24; - s32 freq = 0; - - /* rframe, in this case is null point */ - - freq = rtw_ch2freq(pmlmeext->cur_channel); - -#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ - || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH) - params.action = EXTERNAL_AUTH_START; - _rtw_memcpy(params.bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - params.ssid.ssid_len = pmlmeinfo->network.Ssid.SsidLength; - _rtw_memcpy(params.ssid.ssid, pmlmeinfo->network.Ssid.Ssid, - pmlmeinfo->network.Ssid.SsidLength); - params.key_mgmt_suite = 0x8ac0f00; - - cfg80211_external_auth_request(netdev, - (struct cfg80211_external_auth_params *)¶ms, GFP_ATOMIC); -#elif (KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE) - set_frame_sub_type(frame, WIFI_AUTH); - - _rtw_memcpy(frame + 4, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - _rtw_memcpy(frame + 10, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(frame + 16, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - RTW_PUT_LE32((frame + 18), 0x8ac0f00); - RTW_PUT_LE32((frame + 24), 0x0003); - - if (pmlmeinfo->network.Ssid.SsidLength) { - *(frame + 26) = pmlmeinfo->network.Ssid.SsidLength; - _rtw_memcpy(frame + 27, pmlmeinfo->network.Ssid.Ssid, - pmlmeinfo->network.Ssid.SsidLength); - frame_len = 27 + pmlmeinfo->network.Ssid.SsidLength; - } - rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); -#endif -} - -void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) -{ - struct wireless_dev *wdev = adapter->rtw_wdev; - u8 *frame = get_recvframe_data(rframe); - uint frame_len = rframe->u.hdr.len; - s32 freq; - u8 ch, sch = rtw_get_oper_ch(adapter); - - ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; - freq = rtw_ch2freq(ch); - -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n" - , ch, sch, MAC_ARG(get_addr2_ptr(frame))); -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) - rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); -#else - cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); -#endif -} - -void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe) -{ - struct wireless_dev *wdev = adapter->rtw_wdev; - u8 *frame = get_recvframe_data(rframe); - uint frame_len = rframe->u.hdr.len; - s32 freq; - u8 ch, sch = rtw_get_oper_ch(adapter); - u8 category, action; - int type; - - ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; - freq = rtw_ch2freq(ch); + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" , ch, sch, MAC_ARG(get_addr2_ptr(frame))); @@ -7213,298 +6665,358 @@ void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const c } #ifdef CONFIG_P2P -void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) -{ - u16 wps_devicepassword_id = 0x0000; - uint wps_devicepassword_id_len = 0; - u8 wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 }; - uint p2p_ielen = 0; - uint wpsielen = 0; - u32 devinfo_contentlen = 0; - u8 devinfo_content[64] = { 0x00 }; - u16 capability = 0; - uint capability_len = 0; - - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u8 dialogToken = 1; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_PROVISION_DISC_REQ; - u32 p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif - - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - unsigned short *fctrl; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); - size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); - - - RTW_INFO("[%s] In\n", __FUNCTION__); +#ifdef CONFIG_RTW_80211R +static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, + struct net_device *ndev, + struct cfg80211_update_ft_ies_params *ftie) +{ + _adapter *padapter = NULL; + struct mlme_priv *pmlmepriv = NULL; + struct ft_roam_info *pft_roam = NULL; - /* prepare for building provision_request frame */ - _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN); - _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN); + if (ndev == NULL) + return -EINVAL; - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; + padapter = (_adapter *)rtw_netdev_priv(ndev); + pmlmepriv = &(padapter->mlmepriv); + pft_roam = &(pmlmepriv->ft_roam); - rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); - rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len); - wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id); +#ifdef CONFIG_RTW_80211R_AP + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + return rtw_ft_update_sta_ies(padapter, ftie); +#endif - switch (wps_devicepassword_id) { - case WPS_DPID_PIN: - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; - break; - case WPS_DPID_USER_SPEC: - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; - break; - case WPS_DPID_MACHINE_SPEC: - break; - case WPS_DPID_REKEY: - break; - case WPS_DPID_PBC: - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; - break; - case WPS_DPID_REGISTRAR_SPEC: - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; - break; - default: - break; + if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) { + _rtw_spinlock_bh(&pmlmepriv->lock); + _rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len); + pft_roam->updated_ft_ies_len = ftie->ie_len; + _rtw_spinunlock_bh(&pmlmepriv->lock); + } else { + RTW_ERR("FTIEs parsing fail!\n"); + return -EINVAL; } + if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) { + RTW_PRINT("auth success, start reassoc\n"); + rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA); + start_clnt_assoc(padapter); + } - if (rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen)) { + return 0; +} +#endif - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen); - rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&capability, &capability_len); +inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter) +{ +#if RTW_P2P_GROUP_INTERFACE + if (is_primary_adapter(adapter)) + return 0; +#endif + return 1; +} - } +inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter) +{ + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */ + return rtw_cfg80211_is_scan_by_pd_wdev(adapter); + #endif + { + /* Here are 2 cases: + * 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or + * 2. RTW_DEDICATED_P2P_DEVICE not defined + * Both cases check whether the contents of scan_request is p2p scan. + */ + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); + int is_p2p_scan = 0; + _rtw_spinlock_bh(&wdev_data->scan_req_lock); + if (wdev_data->scan_request + && wdev_data->scan_request->n_ssids + && wdev_data->scan_request->ssids + && wdev_data->scan_request->ie + ) { + if (_rtw_memcmp(wdev_data->scan_request->ssids[0].ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL)) + is_p2p_scan = 1; + } + _rtw_spinunlock_bh(&wdev_data->scan_req_lock); - /* start to build provision_request frame */ - _rtw_memset(wpsie, 0, sizeof(wpsie)); - _rtw_memset(p2p_ie, 0, sizeof(p2p_ie)); - p2p_ielen = 0; + return is_p2p_scan; + } +} - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; +#if defined(RTW_DEDICATED_P2P_DEVICE) +int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev) +{ + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + struct wireless_dev *wdev = NULL; + struct rtw_netdev_priv_indicator *npi; + _adapter *primary_adpt = wiphy_to_adapter(wiphy); + int ret = 0; + if (wiphy_data->pd_wdev) { + RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy)); + ret = -EBUSY; + goto exit; + } - /* update attribute */ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); + wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); + if (!wdev) { + RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy)); + ret = -ENOMEM; + goto exit; + } - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + wdev->wiphy = wiphy; + wdev->iftype = NL80211_IFTYPE_P2P_DEVICE; + _rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + wiphy_data->pd_wdev = wdev; + *pd_wdev = wdev; - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n" + , FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev))); - _rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); +exit: + if (ret && wdev) { + rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev)); + wdev = NULL; + } - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - set_frame_sub_type(pframe, WIFI_ACTION); + return ret; +} - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); +void rtw_pd_iface_free(struct wiphy *wiphy) +{ + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + u8 rtnl_lock_needed; - pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + if (!wiphy_data->pd_wdev) + goto exit; + RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n" + , FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev + , MAC_ARG(wdev_address(wiphy_data->pd_wdev))); - /* build_prov_disc_request_p2p_ie */ - /* P2P OUI */ - p2pielen = 0; - p2p_ie[p2pielen++] = 0x50; - p2p_ie[p2pielen++] = 0x6F; - p2p_ie[p2pielen++] = 0x9A; - p2p_ie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + if (rtnl_lock_needed) + rtnl_lock(); + cfg80211_unregister_wdev(wiphy_data->pd_wdev); + if (rtnl_lock_needed) + rtnl_unlock(); - /* Commented by Albert 20110301 */ - /* According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */ - /* 1. P2P Capability */ - /* 2. Device Info */ - /* 3. Group ID ( When joining an operating P2P Group ) */ + rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev)); + wiphy_data->pd_wdev = NULL; - /* P2P Capability ATTR */ - /* Type: */ - p2p_ie[p2pielen++] = P2P_ATTR_CAPABILITY; +exit: + return; +} - /* Length: */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */ - RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002); - p2pielen += 2; +static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) +{ + _adapter *adapter = wiphy_to_adapter(wiphy); - /* Value: */ - /* Device Capability Bitmap, 1 byte */ - /* Group Capability Bitmap, 1 byte */ - _rtw_memcpy(p2p_ie + p2pielen, &capability, 2); - p2pielen += 2; + RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); + rtw_p2p_enable(adapter, P2P_ROLE_DEVICE); + return 0; +} - /* Device Info ATTR */ - /* Type: */ - p2p_ie[p2pielen++] = P2P_ATTR_DEVICE_INFO; +static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) +{ + _adapter *adapter = wiphy_to_adapter(wiphy); - /* Length: */ - /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ - /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ - /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */ - RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen); - p2pielen += 2; + RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); - /* Value: */ - _rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen); - p2pielen += devinfo_contentlen; + if (rtw_cfg80211_is_p2p_scan(adapter)) + rtw_scan_abort(adapter, 0); + rtw_p2p_enable(adapter, P2P_ROLE_DISABLE); +} - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen); - /* p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); */ - /* pframe += p2pielen; */ - pattrib->pktlen += p2p_ielen; +inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev) +{ + struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy); - wpsielen = 0; - /* WPS OUI */ - *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); - wpsielen += 4; + if (pd_wdev && pd_wdev != *wdev + && _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE + ) { + *wdev = pd_wdev; + return 1; + } + return 0; +} - /* WPS version */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); - wpsielen += 2; +inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); + struct wireless_dev *wdev = NULL; - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); - wpsielen += 2; + _rtw_spinlock_bh(&wdev_data->scan_req_lock); + if (wdev_data->scan_request) + wdev = wdev_data->scan_request->wdev; + _rtw_spinunlock_bh(&wdev_data->scan_req_lock); - /* Value: */ - wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + if (wdev && wdev == wiphy_to_pd_wdev(wiphy)) + return 1; - /* Config Method */ - /* Type: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); - wpsielen += 2; + return 0; +} +#endif /* RTW_DEDICATED_P2P_DEVICE */ +#endif /* CONFIG_P2P */ - /* Length: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); - wpsielen += 2; +inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val) +{ + adapter->cfg80211_rochinfo.is_ro_ch = val; + rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); +} - /* Value: */ - *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request); - wpsielen += 2; +inline bool rtw_cfg80211_get_is_roch(_adapter *adapter) +{ + return adapter->cfg80211_rochinfo.is_ro_ch; +} - pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); +inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter) +{ + return adapter->cfg80211_rochinfo.last_ro_ch_time ? 1 : 0; +} +inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter) +{ + adapter->cfg80211_rochinfo.last_ro_ch_time = rtw_get_current_time(); -#ifdef CONFIG_WFD - wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); - pframe += wfdielen; - pattrib->pktlen += wfdielen; -#endif + if (!adapter->cfg80211_rochinfo.last_ro_ch_time) + adapter->cfg80211_rochinfo.last_ro_ch_time++; +} - pattrib->last_txcmdsz = pattrib->pktlen; +inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter) +{ + return rtw_get_passing_time_ms(adapter->cfg80211_rochinfo.last_ro_ch_time); +} - /* dump_mgntframe(padapter, pmgntframe); */ - if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) - RTW_INFO("%s, ack to\n", __func__); +#ifndef RTW_USE_CFG80211_REPORT_PROBE_REQ +static inline bool chk_is_p2p_device(_adapter *adapter, struct wireless_dev *wdev) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); - #if 0 - if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) { - RTW_INFO("waiting for p2p peer key-in PIN CODE\n"); - rtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */ - } +#if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + return _TRUE; +#else + #if defined(CONFIG_CONCURRENT_MODE) && !RTW_P2P_GROUP_INTERFACE + if (adapter->iface_id == adapter->registrypriv.sel_p2p_iface) #endif - + return _TRUE; +#endif + return _FALSE; } +#endif -#ifdef CONFIG_RTW_80211R -static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, +#if 1 /*CONFIG_PHL_ARCH*/ +static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + struct wireless_dev *wdev, +#else struct net_device *ndev, - struct cfg80211_update_ft_ies_params *ftie) +#endif + struct ieee80211_channel *channel, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + enum nl80211_channel_type channel_type, +#endif + unsigned int duration, u64 *cookie) { + s32 err = 0; + u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); _adapter *padapter = NULL; - struct mlme_priv *pmlmepriv = NULL; - struct ft_roam_info *pft_roam = NULL; - _irqL irqL; - u8 *p; - u8 *pie = NULL; - u32 ie_len = 0; + struct registry_priv *pregistrypriv = NULL; + //struct rtw_wdev_priv *pwdev_priv; + struct cfg80211_roch_info *pcfg80211_rochinfo; + struct back_op_param bkop_parm; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + u8 channel_type = 0; +#endif + u8 is_p2p = _FALSE; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + padapter = wiphy_to_adapter(wiphy); + else +#endif + if (wdev_to_ndev(wdev)) + padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + else + return -EINVAL; +#else + struct wireless_dev *wdev; if (ndev == NULL) - return -EINVAL; + return -EINVAL; padapter = (_adapter *)rtw_netdev_priv(ndev); - pmlmepriv = &(padapter->mlmepriv); - pft_roam = &(pmlmepriv->ft_roam); + wdev = ndev_to_wdev(ndev); +#endif + pregistrypriv = &padapter->registrypriv; + pcfg80211_rochinfo = &padapter->cfg80211_rochinfo; - p = (u8 *)ftie->ie; - if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) { - _enter_critical_bh(&pmlmepriv->lock, &irqL); - _rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len); - pft_roam->updated_ft_ies_len = ftie->ie_len; - _exit_critical_bh(&pmlmepriv->lock, &irqL); - } else { - RTW_ERR("FTIEs parsing fail!\n"); - return -EINVAL; +#ifndef RTW_USE_CFG80211_REPORT_PROBE_REQ +#ifdef CONFIG_P2P + is_p2p = chk_is_p2p_device(padapter, wdev); + + if (is_p2p) { + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) + rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); + + pwdinfo->listen_channel = remain_ch; + RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n", + FUNC_ADPT_ARG(padapter), + padapter->wdinfo.listen_channel); } +#endif +#endif - if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) { - RTW_PRINT("auth success, start reassoc\n"); - rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL); - start_clnt_assoc(padapter); + *cookie = ATOMIC_INC_RETURN(&pcfg80211_rochinfo->ro_ch_cookie_gen); + + RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" + , remain_ch, duration, *cookie); + + if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) { + RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch); + return -EFAULT; } - return 0; -} +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(padapter)) { + RTW_INFO("MP mode block remain_on_channel request\n"); + return -EFAULT; + } #endif -#endif /* CONFIG_P2P */ + if (_FAIL == rtw_pwr_wakeup(padapter)) + return -EFAULT; -inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val) -{ - adapter->rochinfo.is_ro_ch = val; - rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); -} + rtw_scan_abort(padapter, 0); -inline bool rtw_cfg80211_get_is_roch(_adapter *adapter) -{ - return adapter->rochinfo.is_ro_ch; -} + bkop_parm.off_ch_dur = pregistrypriv->roch_max_away_dur; + bkop_parm.on_ch_dur = pregistrypriv->roch_min_home_dur; -inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter) -{ - return adapter->rochinfo.last_ro_ch_time ? 1 : 0; -} + if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) + bkop_parm.off_ch_ext_dur = pregistrypriv->roch_extend_dur; + else + bkop_parm.off_ch_ext_dur = pregistrypriv->roch_extend_dur * 6; -inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter) -{ - adapter->rochinfo.last_ro_ch_time = rtw_get_current_time(); + rtw_phl_remain_on_ch_cmd(padapter, *cookie, wdev, + channel, channel_type, duration, &bkop_parm, is_p2p); - if (!adapter->rochinfo.last_ro_ch_time) - adapter->rochinfo.last_ro_ch_time++; + return 0; } -inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter) -{ - return rtw_get_passing_time_ms(adapter->rochinfo.last_ro_ch_time); -} +#else /* !CONFIG_PHL_ARCH */ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) @@ -7522,13 +7034,11 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); _adapter *padapter = NULL; struct rtw_wdev_priv *pwdev_priv; - struct roch_info *prochinfo; -#ifdef CONFIG_P2P struct wifidirect_info *pwdinfo; + struct cfg80211_wifidirect_info *pcfg80211_wdinfo; #ifdef CONFIG_CONCURRENT_MODE u8 is_p2p_find = _FALSE; #endif -#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if defined(RTW_DEDICATED_P2P_DEVICE) @@ -7554,15 +7064,13 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, #endif pwdev_priv = adapter_wdev_data(padapter); - prochinfo = &padapter->rochinfo; -#ifdef CONFIG_P2P pwdinfo = &padapter->wdinfo; + pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; #ifdef CONFIG_CONCURRENT_MODE is_p2p_find = (duration < (pwdinfo->ext_listen_interval)) ? _TRUE : _FALSE; -#endif #endif - *cookie = ATOMIC_INC_RETURN(&prochinfo->ro_ch_cookie_gen); + *cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen); RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n" , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" @@ -7588,18 +7096,17 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, } rtw_scan_abort(padapter); -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) +#ifdef CONFIG_CONCURRENT_MODE /*don't scan_abort during p2p_listen.*/ if (is_p2p_find) rtw_mi_buddy_scan_abort(padapter, _TRUE); -#endif /* defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) */ +#endif /*CONFIG_CONCURRENT_MODE*/ if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { - _cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer); - rtw_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK); + _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); + p2p_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK); } -#ifdef CONFIG_P2P /* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */ if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) @@ -7627,37 +7134,40 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, } rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); -#endif /* CONFIG_P2P */ #ifdef RTW_ROCH_DURATION_ENLARGE if (duration < 400) duration = duration * 3; /* extend from exper */ #endif -#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) +#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) if (rtw_mi_check_status(padapter, MI_LINKED)) { if (is_p2p_find) /* p2p_find , duration<1000 */ duration = duration + pwdinfo->ext_listen_interval; + else /* p2p_listen, duration=5000 */ + duration = pwdinfo->ext_listen_interval + (pwdinfo->ext_listen_interval / 4); } -#endif /* defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) */ +#endif /*defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) */ rtw_cfg80211_set_is_roch(padapter, _TRUE); - prochinfo->ro_ch_wdev = wdev; - prochinfo->remain_on_ch_cookie = *cookie; + pcfg80211_wdinfo->ro_ch_wdev = wdev; + pcfg80211_wdinfo->remain_on_ch_cookie = *cookie; + pcfg80211_wdinfo->duration = duration; rtw_cfg80211_set_last_ro_ch_time(padapter); - _rtw_memcpy(&prochinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); + _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - prochinfo->remain_on_ch_type = channel_type; + pcfg80211_wdinfo->remain_on_ch_type = channel_type; #endif - prochinfo->restore_channel = rtw_get_oper_ch(padapter); + pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); - rtw_roch_cmd(padapter, *cookie, wdev, channel, prochinfo->remain_on_ch_type, + p2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type, duration, RTW_CMDF_WAIT_ACK); rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL); exit: return err; } +#endif /* CONFIG_PHL_ARCH */ static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) @@ -7670,10 +7180,7 @@ static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, s32 err = 0; _adapter *padapter; struct rtw_wdev_priv *pwdev_priv; - struct roch_info *prochinfo; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo; -#endif + struct cfg80211_roch_info *pcfg80211_rochinfo; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if defined(RTW_DEDICATED_P2P_DEVICE) @@ -7699,201 +7206,20 @@ static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, #endif pwdev_priv = adapter_wdev_data(padapter); - prochinfo = &padapter->rochinfo; -#ifdef CONFIG_P2P - pwdinfo = &padapter->wdinfo; -#endif + pcfg80211_rochinfo = &padapter->cfg80211_rochinfo; RTW_INFO(FUNC_ADPT_FMT"%s cookie:0x%llx\n" , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" , cookie); if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { - _cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer); - rtw_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK); + rtw_scan_abort(padapter, 0); } exit: return err; } -#ifdef CONFIG_P2P -inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter) -{ -#if RTW_P2P_GROUP_INTERFACE - if (is_primary_adapter(adapter)) - return 0; -#endif - return 1; -} - -inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter) -{ -#if RTW_P2P_GROUP_INTERFACE - if (rtw_cfg80211_iface_has_p2p_group_cap(adapter)) -#endif - { - struct wifidirect_info *wdinfo = &adapter->wdinfo; - - return rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN) - || rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH); - } - -#if RTW_P2P_GROUP_INTERFACE - #if defined(RTW_DEDICATED_P2P_DEVICE) - if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */ - return rtw_cfg80211_is_scan_by_pd_wdev(adapter); - #endif - { - /* - * For 2 RTW_P2P_GROUP_INTERFACE cases: - * 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or - * 2. RTW_DEDICATED_P2P_DEVICE not defined - */ - struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); - _irqL irqL; - int is_p2p_scan = 0; - - _enter_critical_bh(&wdev_data->scan_req_lock, &irqL); - if (wdev_data->scan_request - && wdev_data->scan_request->n_ssids - && wdev_data->scan_request->ssids - && wdev_data->scan_request->ie - ) { - if (_rtw_memcmp(wdev_data->scan_request->ssids[0].ssid, "DIRECT-", 7) - && rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL)) - is_p2p_scan = 1; - } - _exit_critical_bh(&wdev_data->scan_req_lock, &irqL); - - return is_p2p_scan; - } -#endif -} - -#if defined(RTW_DEDICATED_P2P_DEVICE) -int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev) -{ - struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); - struct wireless_dev *wdev = NULL; - struct rtw_netdev_priv_indicator *npi; - _adapter *primary_adpt = wiphy_to_adapter(wiphy); - int ret = 0; - - if (wiphy_data->pd_wdev) { - RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy)); - ret = -EBUSY; - goto exit; - } - - wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); - if (!wdev) { - RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy)); - ret = -ENOMEM; - goto exit; - } - - wdev->wiphy = wiphy; - wdev->iftype = NL80211_IFTYPE_P2P_DEVICE; - _rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN); - - wiphy_data->pd_wdev = wdev; - *pd_wdev = wdev; - - RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n" - , FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev))); - -exit: - if (ret && wdev) { - rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev)); - wdev = NULL; - } - - return ret; -} - -void rtw_pd_iface_free(struct wiphy *wiphy) -{ - struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); - u8 rtnl_lock_needed; - - if (!wiphy_data->pd_wdev) - goto exit; - - RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n" - , FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev - , MAC_ARG(wdev_address(wiphy_data->pd_wdev))); - - rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); - if (rtnl_lock_needed) - rtnl_lock(); - cfg80211_unregister_wdev(wiphy_data->pd_wdev); - if (rtnl_lock_needed) - rtnl_unlock(); - - rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev)); - wiphy_data->pd_wdev = NULL; - -exit: - return; -} - -static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) -{ - _adapter *adapter = wiphy_to_adapter(wiphy); - - RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); - - rtw_p2p_enable(adapter, P2P_ROLE_DEVICE); - return 0; -} - -static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) -{ - _adapter *adapter = wiphy_to_adapter(wiphy); - - RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); - - if (rtw_cfg80211_is_p2p_scan(adapter)) - rtw_scan_abort(adapter); - - rtw_p2p_enable(adapter, P2P_ROLE_DISABLE); -} - -inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev) -{ - struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy); - - if (pd_wdev && pd_wdev != *wdev - && _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE - ) { - *wdev = pd_wdev; - return 1; - } - return 0; -} - -inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter) -{ - struct wiphy *wiphy = adapter_to_wiphy(adapter); - struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); - struct wireless_dev *wdev = NULL; - _irqL irqL; - - _enter_critical_bh(&wdev_data->scan_req_lock, &irqL); - if (wdev_data->scan_request) - wdev = wdev_data->scan_request->wdev; - _exit_critical_bh(&wdev_data->scan_req_lock, &irqL); - - if (wdev && wdev == wiphy_to_pd_wdev(wiphy)) - return 1; - - return 0; -} -#endif /* RTW_DEDICATED_P2P_DEVICE */ -#endif /* CONFIG_P2P */ - inline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val) { struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); @@ -7924,48 +7250,52 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); u8 u_ch = rtw_mi_get_union_chan(padapter); u8 leave_op = 0; - struct roch_info *prochinfo = &padapter->rochinfo; -#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) +#ifdef CONFIG_P2P + struct cfg80211_roch_info *pcfg80211_rochinfo = &padapter->cfg80211_rochinfo; + #ifdef CONFIG_CONCURRENT_MODE struct wifidirect_info *pwdinfo = &padapter->wdinfo; + #endif #endif + u8 frame_styp; rtw_cfg80211_set_is_mgmt_tx(padapter, 1); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_ScanNotify(padapter, _TRUE); -#endif - +#if 0 +/* phl_scan + * Enable ext period when WIFI_ASOC_STATE + * cancel roch when ext_listen_period is up + * remove it, because phl_sacn will do extend + */ #ifdef CONFIG_P2P if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { #ifdef CONFIG_CONCURRENT_MODE if (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) { RTW_INFO("%s, extend ro ch time\n", __func__); - _set_timer(&padapter->rochinfo.remain_on_ch_timer, pwdinfo->ext_listen_period); + _set_timer(&padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period); } #endif /* CONFIG_CONCURRENT_MODE */ } #endif /* CONFIG_P2P */ - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - /* don't set channel, issue frame directly */ - goto issue_mgmt_frame; - } -#endif /* CONFIG_MCC_MODE */ +#endif if (rtw_mi_check_status(padapter, MI_LINKED) && tx_ch != u_ch ) { - rtw_leave_opch(padapter); - leave_op = 1; + + /* phl_scan will self leave opch */ + if (!rtw_cfg80211_get_is_roch(padapter)) { + rtw_leave_opch(padapter); + leave_op = 1; + } + } + + /* phl_scan will self remain on ch */ + if (!rtw_cfg80211_get_is_roch(padapter)) { + if (tx_ch != rtw_get_oper_ch(padapter)) + set_channel_bwmode(padapter, + tx_ch, CHAN_OFFSET_NO_EXT, CHANNEL_WIDTH_20, _FALSE); } - if (tx_ch != rtw_get_oper_ch(padapter)) - set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#ifdef CONFIG_MCC_MODE -issue_mgmt_frame: -#endif /* starting alloc mgmt frame to dump it */ pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { @@ -7981,7 +7311,6 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const if (no_cck && IS_CCK_RATE(pattrib->rate)) { /* force OFDM 6M rate*/ pattrib->rate = MGN_6M; - pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); } pattrib->retry_ctrl = _FALSE; @@ -7995,7 +7324,7 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; /* update seq number */ - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pattrib->seqnum = pmlmeext->mgnt_seq; pmlmeext->mgnt_seq++; @@ -8003,6 +7332,13 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const rtw_xframe_chk_wfd_ie(pmgntframe); #endif /* CONFIG_P2P */ +#ifdef CONFIG_ECSA_PHL + /* Update channel switch count of CSA/ECSA IE in probe response */ + frame_styp = (le16_to_cpu(pwlanhdr->frame_ctl)) & IEEE80211_FCTL_STYPE; + if (frame_styp == IEEE80211_STYPE_PROBE_RESP) + rtw_ecsa_update_probe_resp(pmgntframe); +#endif + pattrib->last_txcmdsz = pattrib->pktlen; if (wait_ack) { @@ -8030,30 +7366,35 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } exit: + +/* phl_scan will self return opch */ +#if 0 + #ifdef CONFIG_P2P if (rtw_cfg80211_get_is_roch(padapter) - && !rtw_roch_stay_in_cur_chan(padapter) - && prochinfo->remain_on_ch_channel.hw_value != u_ch + && !roch_stay_in_cur_chan(padapter) + && pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch ) { /* roch is ongoing, switch back to rch */ - if (prochinfo->remain_on_ch_channel.hw_value != tx_ch) - set_channel_bwmode(padapter, prochinfo->remain_on_ch_channel.hw_value - , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } else if (leave_op) { + if (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch) + set_channel_bwmode(padapter, + pcfg80211_wdinfo->remain_on_ch_channel.hw_value, + CHAN_OFFSET_NO_EXT, + CHANNEL_WIDTH_20, + _FALSE); + } else + #endif +#endif + if (leave_op) { if (rtw_mi_check_status(padapter, MI_LINKED)) { u8 u_bw = rtw_mi_get_union_bw(padapter); u8 u_offset = rtw_mi_get_union_offset(padapter); - set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + set_channel_bwmode(padapter, u_ch, u_offset, u_bw, _FALSE); } rtw_back_opch(padapter); } - rtw_cfg80211_set_is_mgmt_tx(padapter, 0); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_ScanNotify(padapter, _FALSE); -#endif - #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, ret=%d\n", __func__, ret); #endif @@ -8170,7 +7511,7 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); if (IS_CH_WAITING(rfctl)) { #ifdef CONFIG_DFS_MASTER - if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { + if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, CHAN_OFFSET_NO_EXT)) { ret = -EINVAL; goto exit; } @@ -8211,6 +7552,19 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE; if (IEEE80211_STYPE_PROBE_RESP == frame_styp) { +#ifdef CONFIG_P2P + /* 36 = IEEE80211_3ADDR_LEN + _TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_ */ + if(rtw_get_p2p_ie(dump_buf + 36, dump_len - 36, NULL, NULL)) { + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) { + if (!rtw_p2p_enable(padapter, P2P_ROLE_DEVICE)) { + ret = -EOPNOTSUPP; + goto exit; + } + } + no_cck = 1; + } +#endif #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); #endif /* CONFIG_DEBUG_CFG80211 */ @@ -8222,6 +7576,10 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); +#ifdef CONFIG_RTW_80211R_AP + rtw_ft_process_ft_auth_rsp(padapter, (u8 *)buf, len); +#endif + retval = rtw_sae_preprocess(padapter, buf, len, _TRUE); if (retval == 2) goto exit; @@ -8283,8 +7641,12 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, while (1) { dump_cnt++; - rtw_mi_set_scan_deny(padapter, 1000); - rtw_mi_scan_abort(padapter, _TRUE); + /* ROCH uses phl scan to handle, cancel scan is not necessary */ + if (!rtw_cfg80211_get_is_roch(padapter)) { + rtw_mi_set_scan_deny(padapter, 1000); + rtw_mi_scan_abort(padapter, _TRUE); + } + tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK); if (tx_ret == _SUCCESS || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) @@ -8364,10 +7726,16 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, _adapter *adapter; struct rtw_wdev_priv *pwdev_priv; - if (ndev == NULL) - goto exit; - - adapter = (_adapter *)rtw_netdev_priv(ndev); +#if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) { + adapter = wiphy_to_adapter(wiphy); + } else +#endif + { + if (ndev == NULL) + goto exit; + adapter = (_adapter *)rtw_netdev_priv(ndev); + } pwdev_priv = adapter_wdev_data(adapter); #ifdef CONFIG_DEBUG_CFG80211 @@ -8382,13 +7750,13 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, else CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH); break; -#ifdef not_yet case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */ if (reg > 0) SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ); else CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ); break; +#ifdef not_yet case IEEE80211_STYPE_ACTION: /* 0x00D0 */ if (reg > 0) SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION); @@ -8423,7 +7791,9 @@ static void cfg80211_rtw_update_mgmt_frame_register( padapter = (_adapter *)rtw_netdev_priv(ndev); pwdev_priv = adapter_wdev_data(padapter); - rtw_stypes_mask = BIT(IEEE80211_STYPE_AUTH >> 4); + /* Driver only supports Auth and Probe request */ + rtw_stypes_mask = BIT(IEEE80211_STYPE_AUTH >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4); #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT " global_stypes:0x%08x interface_stypes:0x%08x\n", @@ -8465,12 +7835,13 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, size_t len) { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; int ret = 0; struct tdls_txmgmt txmgmt; - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + if (rtw_hw_chk_wl_func(dvobj, WL_FUNC_TDLS) == _FALSE) { RTW_INFO("Discard tdls action:%d, since hal doesn't support tdls\n", action_code); goto discard; } @@ -8551,13 +7922,14 @@ static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, enum nl80211_tdls_operation oper) { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct tdls_txmgmt txmgmt; struct sta_info *ptdls_sta = NULL; RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + if (rtw_hw_chk_wl_func(dvobj, WL_FUNC_TDLS) == _FALSE) { RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); return 0; } @@ -8629,36 +8001,372 @@ static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, } #endif /* CONFIG_TDLS */ -#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) +#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) + +#if DBG_RTW_CFG80211_MESH_CONF +#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1) +int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf) +{ + int i; + int cnt = 0; + + for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) { + if (mask & BIT(i)) { + cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d " + , wiphy->bands[band]->bitrates[i].bitrate / 10 + , wiphy->bands[band]->bitrates[i].bitrate % 10); + if (cnt >= LEGACY_RATES_STR_LEN - 1) + break; + } + } + + return cnt; +} + +void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); +#endif + struct ieee80211_channel *chan; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + chan = (struct ieee80211_channel *)chdef->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + chan = (struct ieee80211_channel *)setup->channel; +#endif + + RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method); +#endif + RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + if (setup->ie && setup->ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len); + dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len); + } +#else + if (setup->vendor_ie && setup->vendor_ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len); + dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len); + } +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n" + , chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2); +#else + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n" + , chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (setup->mcast_rate[chan->band]) { + RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n" + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10 + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10 + ); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf); + RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) + if (setup->beacon_rate.control[chan->band].legacy) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf); + RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf); + } + if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0])) + || *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4])) + || *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8])) + ) { + RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n" + , HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs)); + } + + if (setup->beacon_rate.control[chan->band].vht_mcs[0] + || setup->beacon_rate.control[chan->band].vht_mcs[1] + || setup->beacon_rate.control[chan->band].vht_mcs[2] + || setup->beacon_rate.control[chan->band].vht_mcs[3] + ) { + int i; + + for (i = 0; i < 4; i++) {/* parsing up to 4SS */ + u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i]; + + RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i + , mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid"); + } + } + + if (setup->beacon_rate.control[chan->band].gi) { + RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n" + , setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" : + setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid" + ); + } +#endif +} + +void dump_mesh_config(void *sel, const struct mesh_config *conf) +{ + RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout); + RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout); + RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks); + RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries); + RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL); + RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl); + RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor); +#endif + + RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries); + RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time); + RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval); +#endif + RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime); + RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval); + RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding); + RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval); + RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode)); + RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout); +#endif +} +#endif /* DBG_RTW_CFG80211_MESH_CONF */ + +static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup) +{ + _rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len); + minfo->mesh_id_len = setup->mesh_id_len; + minfo->mesh_pp_id = setup->path_sel_proto; + minfo->mesh_pm_id = setup->path_metric; + minfo->mesh_cc_id = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + minfo->mesh_sp_id = setup->sync_method; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + minfo->mesh_auth_id = setup->auth_id; +#else + if (setup->is_authenticated) { + u8 *rsn_ie; + sint rsn_ie_len; + struct rsne_info info; + u8 *akm; + u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08}; + + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (!rsn_ie || !rsn_ie_len) { + rtw_warn_on(1); + return; + } + + if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) { + rtw_warn_on(1); + return; + } + + if (!info.akm_list || !info.akm_cnt) { + rtw_warn_on(1); + return; + } + + akm = info.akm_list; + while (akm < info.akm_list + info.akm_cnt * 4) { + if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) { + minfo->mesh_auth_id = 0x01; + break; + } + } + + if (!minfo->mesh_auth_id) { + rtw_warn_on(1); + return; + } + } +#endif +} + +static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask) +{ + return (mask >> (parm - 1)) & 0x1; +} -#if DBG_RTW_CFG80211_MESH_CONF -#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1) -int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf) +static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask) { - int i; - int cnt = 0; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; - for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) { - if (mask & BIT(i)) { - cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d " - , wiphy->bands[band]->bitrates[i].bitrate / 10 - , wiphy->bands[band]->bitrates[i].bitrate % 10); - if (cnt >= LEGACY_RATES_STR_LEN - 1) - break; - } +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask)); +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask)) + mcfg->dot11MeshTTL = conf->dot11MeshTTL; + if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask)) + mcfg->element_ttl = conf->element_ttl; + +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask)); +#endif + +#if 0 /* TBD: synchronization */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask)); +#endif +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask)) + mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries; + if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask)) + mcfg->path_refresh_time = conf->path_refresh_time; + if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask)) + mcfg->min_discovery_timeout = conf->min_discovery_timeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval; +#endif + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask)) + mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime; + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask)) + mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask)) + mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol; + /* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */ + if (mcfg->dot11MeshGateAnnouncementProtocol + && mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT + ) { + mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN; + RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter)); } + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask)) + mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask)) + mcfg->dot11MeshForwarding = conf->dot11MeshForwarding; - return cnt; + if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask)) + mcfg->rssi_threshold = conf->rssi_threshold; +#endif + +#if 0 /* controlled by driver */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask)) + mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask)) + mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval; +#endif + +#if 0 /* TBD */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask)); +#endif +#endif + +#if 0 /* driver MPM */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask)); +#endif +#endif } -void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup) +u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter + , const struct mesh_config *conf, const struct mesh_setup *setup + , uint *ies_len) { + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); #endif struct ieee80211_channel *chan; + u8 ch, bw, offset; #endif + uint len; + u8 n_bitrates; + u8 ht = 0; + u8 vht = 0; + u8 *rsn_ie = NULL; + sint rsn_ie_len = 0; + u8 *ies = NULL, *c; + u8 supported_rates[RTW_G_RATES_NUM] = {0}; + int i; + + *ies_len = 0; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) chan = (struct ieee80211_channel *)chdef->chan; @@ -8666,1092 +8374,1108 @@ void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *se chan = (struct ieee80211_channel *)setup->channel; #endif - RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method); -#endif - RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id); -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) - if (setup->ie && setup->ie_len) { - RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len); - dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len); - } -#else - if (setup->vendor_ie && setup->vendor_ie_len) { - RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len); - dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len); - } -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) - RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure); -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) - RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm); -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) - RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval); -#endif + n_bitrates = wiphy->bands[chan->band]->n_bitrates; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n" - , chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2); + rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset); #else - RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n" - , chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type)); + rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset); #endif + if (!ch) + goto exit; + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */ #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) - if (setup->mcast_rate[chan->band]) { - RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n" - , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10 - , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10 - ); - } + RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n" + , FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht); #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - if (setup->basic_rates) { - char buf[LEGACY_RATES_STR_LEN] = {0}; - - get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf); - RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf); + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (rsn_ie && !rsn_ie_len) { + rtw_warn_on(1); + rsn_ie = NULL; } -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) - if (setup->beacon_rate.control[chan->band].legacy) { - char buf[LEGACY_RATES_STR_LEN] = {0}; + len = _BEACON_IE_OFFSET_ + + 2 /* 0-length SSID */ + + (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */ + + 3 /* DS parameter set */ + + 6 /* TIM */ + + (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */ + + (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */ + #if defined(CONFIG_80211N_HT) + + (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */ + #endif + #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + + (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */ + #endif + + minfo->mesh_id_len + 2 /* Mesh ID */ + + 9 /* Mesh configuration */ + ; - get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf); - RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf); - } - if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0])) - || *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4])) - || *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8])) - ) { - RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n" - , HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs)); - } + ies = rtw_zmalloc(len); + if (!ies) + goto exit; - if (setup->beacon_rate.control[chan->band].vht_mcs[0] - || setup->beacon_rate.control[chan->band].vht_mcs[1] - || setup->beacon_rate.control[chan->band].vht_mcs[2] - || setup->beacon_rate.control[chan->band].vht_mcs[3] - ) { - int i; + /* timestamp */ + c = ies + 8; - for (i = 0; i < 4; i++) {/* parsing up to 4SS */ - u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i]; + /* beacon interval */ + RTW_PUT_LE16(c , setup->beacon_interval); + c += 2; - RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i - , mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid"); - } - } + /* capability */ + if (rsn_ie) + *((u16 *)c) |= cpu_to_le16(cap_Privacy); + c += 2; - if (setup->beacon_rate.control[chan->band].gi) { - RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n" - , setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" : - setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid" - ); + /* SSID */ + c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL); + + /* Supported Rates */ + for (i = 0; i < n_bitrates; i++) { + supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates & BIT(i)) + #else + if (rtw_is_basic_rate_mix(supported_rates[i])) + #endif + supported_rates[i] |= IEEE80211_BASIC_RATE_MASK; } -#endif -} + c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL); -void dump_mesh_config(void *sel, const struct mesh_config *conf) -{ - RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout); - RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout); - RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout); - RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks); - RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries); - RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL); - RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl); - RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks); + /* DS parameter set */ + c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor); -#endif + /* TIM */ + *c = WLAN_EID_TIM; + *(c + 1) = 4; + c += 6; + //c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL); - RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries); - RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time); - RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout); - RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout); - RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) - RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval); -#endif - RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime); - RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) - RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval); - RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol); -#endif + /* Extended Supported Rates */ + if (n_bitrates > 8) + c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) - RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding); - RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold); -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode); -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout); - RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval); - RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval); -#endif + /* RSN */ + if (rsn_ie) + c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) - RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode)); - RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration); -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout); -#endif -} -#endif /* DBG_RTW_CFG80211_MESH_CONF */ +#if defined(CONFIG_80211N_HT) + if (ht) { + struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap; + u8 ht_cap[HT_CAP_IE_LEN]; + u8 ht_op[HT_OP_IE_LEN]; -static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup) -{ - _rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len); - minfo->mesh_id_len = setup->mesh_id_len; - minfo->mesh_pp_id = setup->path_sel_proto; - minfo->mesh_pm_id = setup->path_metric; - minfo->mesh_cc_id = 0; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - minfo->mesh_sp_id = setup->sync_method; -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - minfo->mesh_auth_id = setup->auth_id; -#else - if (setup->is_authenticated) { - u8 *rsn_ie; - sint rsn_ie_len; - struct rsne_info info; - u8 *akm; - u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08}; + _rtw_memset(ht_cap, 0, HT_CAP_IE_LEN); + _rtw_memset(ht_op, 0, HT_OP_IE_LEN); - rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); - if (!rsn_ie || !rsn_ie_len) { - rtw_warn_on(1); - return; - } + /* WLAN_EID_HT_CAP */ + RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap); + SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor); + SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density); + _rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16); + c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL); - if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) { - rtw_warn_on(1); - return; + /* WLAN_EID_HT_OPERATION */ + SET_HT_OP_ELE_PRI_CHL(ht_op, ch); + switch (offset) { + case CHAN_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, IEEE80211_SCA); + break; + case CHAN_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, IEEE80211_SCB); + break; + case CHAN_OFFSET_NO_EXT: + default: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, IEEE80211_SCN); + break; } + if (bw >= CHANNEL_WIDTH_40) + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1); + else + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0); + c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL); + } +#endif /* defined(CONFIG_80211N_HT) */ - if (!info.akm_list || !info.akm_cnt) { - rtw_warn_on(1); - return; - } +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (vht) { + struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap; + u8 vht_cap[VHT_CAP_IE_LEN]; + u8 vht_op[VHT_OP_IE_LEN]; + u8 cch = rtw_phl_get_center_ch(ch, bw, offset); - akm = info.akm_list; - while (akm < info.akm_list + info.akm_cnt * 4) { - if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) { - minfo->mesh_auth_id = 0x01; - break; - } - } + _rtw_memset(vht_op, 0, VHT_OP_IE_LEN); - if (!minfo->mesh_auth_id) { + /* WLAN_EID_VHT_CAPABILITY */ + _rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4); + _rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8); + c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL); + + /* WLAN_EID_VHT_OPERATION */ + if (bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else if (bw == CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); rtw_warn_on(1); - return; + rtw_mfree(ies, len); + goto exit; } + + /* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */ + vht_op[3] = 0xfc; + vht_op[4] = 0xff; + c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL); } +#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ + + /* Mesh ID */ + c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len); + + /* Mesh configuration */ + c = rtw_set_ie_mesh_config(c, NULL + , minfo->mesh_pp_id + , minfo->mesh_pm_id + , minfo->mesh_cc_id + , minfo->mesh_sp_id + , minfo->mesh_auth_id + , 0, 0, 0 + , 1 + , 0, 0 + , mcfg->dot11MeshForwarding + , 0, 0, 0 + ); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len); + dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_); #endif -} -static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask) -{ - return (mask >> (parm - 1)) & 0x1; +exit: + if (ies) + *ies_len = len; + return ies; } -static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask) +static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev + , struct mesh_config *conf) { - struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg; + int ret = 0; -#if 0 /* driver MPM */ - if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask)); - if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask)); - if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask)); - if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask)); - if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask)); -#endif + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask)) - mcfg->dot11MeshTTL = conf->dot11MeshTTL; - if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask)) - mcfg->element_ttl = conf->element_ttl; + /* driver MPM */ + conf->dot11MeshRetryTimeout = 0; + conf->dot11MeshConfirmTimeout = 0; + conf->dot11MeshHoldingTimeout = 0; + conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links; + conf->dot11MeshMaxRetries = 0; -#if 0 /* driver MPM */ - if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask)); -#endif + conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL; + conf->element_ttl = mesh_cfg->element_ttl; -#if 0 /* TBD: synchronization */ + /* driver MPM */ + conf->auto_open_plinks = 0; + + /* TBD: synchronization */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask)); -#endif + conf->dot11MeshNbrOffsetMaxNeighbor = 0; #endif - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask)) - mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries; - if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask)) - mcfg->path_refresh_time = conf->path_refresh_time; - if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask)) - mcfg->min_discovery_timeout = conf->min_discovery_timeout; - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask)) - mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout; - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask)) - mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval; + conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries; + conf->path_refresh_time = mesh_cfg->path_refresh_time; + conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout; + conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout; + conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask)) - mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval; + conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval; #endif - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask)) - mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime; - - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask)) - mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode; + conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime; + conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask)) - mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol; - /* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */ - if (mcfg->dot11MeshGateAnnouncementProtocol - && mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT - ) { - mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN; - RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter)); - } - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask)) - mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval; + conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval; #endif + conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask)) - mcfg->dot11MeshForwarding = conf->dot11MeshForwarding; - - if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask)) - mcfg->rssi_threshold = conf->rssi_threshold; + conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding; + conf->rssi_threshold = mesh_cfg->rssi_threshold; #endif -#if 0 /* controlled by driver */ + /* TBD */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask)); -#endif + conf->ht_opmode = 0xffff; #endif - + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask)) - mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout; - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask)) - mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval; - if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask)) - mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval; + conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout; + conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval; + conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval; #endif -#if 0 /* TBD */ + /* TBD: power save */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask)); - if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask)); -#endif + conf->power_mode = NL80211_MESH_POWER_ACTIVE; + conf->dot11MeshAwakeWindowDuration = 0; #endif -#if 0 /* driver MPM */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask)); -#endif + conf->plink_timeout = mesh_cfg->plink_timeout; #endif + + return ret; } -u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter - , const struct mesh_config *conf, const struct mesh_setup *setup - , uint *ies_len) +static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work) { - struct rtw_mesh_info *minfo = &adapter->mesh_info; - struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); -#endif - struct ieee80211_channel *chan; - u8 ch, bw, offset; -#endif - uint len; - u8 n_bitrates; - u8 ht = 0; - u8 vht = 0; - u8 *rsn_ie = NULL; - sint rsn_ie_len = 0; - u8 *ies = NULL, *c; - u8 supported_rates[RTW_G_RATES_NUM] = {0}; - int i; + if (need_work) + rtw_mesh_work(&adapter->mesh_work); +} - *ies_len = 0; +static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev + , u32 mask, const struct mesh_config *nconf) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + bool minfo_changed = _FALSE, need_work = _FALSE; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - chan = (struct ieee80211_channel *)chdef->chan; -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - chan = (struct ieee80211_channel *)setup->channel; + RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask); + + rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask); + rtw_update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); +#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (rtw_mesh_cto_mgate_required(adapter)) + rtw_netif_carrier_off(adapter->pnetdev); + else + rtw_netif_carrier_on(adapter->pnetdev); #endif + need_work = rtw_ieee80211_mesh_root_setup(adapter); - n_bitrates = wiphy->bands[chan->band]->n_bitrates; + rtw_mbss_info_change_notify(adapter, minfo_changed, need_work); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset); -#else - rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset); -#endif - if (!ch) - goto exit; - -#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */ -#endif + return ret; +} - RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n" - , FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht); +static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev, + const struct mesh_config *conf, const struct mesh_setup *setup) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 *ies = NULL; + uint ies_len; + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_setup(RTW_DBGDUMP, wiphy, setup); + RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_config(RTW_DBGDUMP, conf); #endif - rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); - if (rsn_ie && !rsn_ie_len) { - rtw_warn_on(1); - rsn_ie = NULL; + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; } - len = _BEACON_IE_OFFSET_ - + 2 /* 0-length SSID */ - + (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */ - + 3 /* DS parameter set */ - + 6 /* TIM */ - + (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */ - + (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */ - #if defined(CONFIG_80211N_HT) - + (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */ - #endif - #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - + (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */ - #endif - + minfo->mesh_id_len + 2 /* Mesh ID */ - + 9 /* Mesh configuration */ - ; + /* initialization */ + rtw_mesh_init_mesh_info(adapter); - ies = rtw_zmalloc(len); - if (!ies) + /* apply cfg80211 settings*/ + rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup); + rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF); + + /* apply cfg80211 settings (join only) */ + rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout); + #endif + + rtw_ieee80211_mesh_root_setup(adapter); + + ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len); + if (!ies) { + ret = -EINVAL; goto exit; + } - /* timestamp */ - c = ies + 8; + /* start mbss */ + if (rtw_check_beacon_data(adapter, ies, ies_len) != _SUCCESS) { + ret = -EINVAL; + goto exit; + } + + rtw_mesh_work(&adapter->mesh_work); - /* beacon interval */ - RTW_PUT_LE16(c , setup->beacon_interval); - c += 2; +exit: + if (ies) + rtw_mfree(ies, ies_len); + if (ret) + rtw_mesh_deinit_mesh_info(adapter); - /* capability */ - if (rsn_ie) - *((u16 *)c) |= cpu_to_le16(cap_Privacy); - c += 2; + return ret; +} - /* SSID */ - c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL); +static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; - /* Supported Rates */ - for (i = 0; i < n_bitrates; i++) { - supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - if (setup->basic_rates & BIT(i)) - #else - if (rtw_is_basic_rate_mix(supported_rates[i])) - #endif - supported_rates[i] |= IEEE80211_BASIC_RATE_MASK; + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + rtw_mesh_deinit_mesh_info(adapter); + + rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK); + + return ret; +} + +static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; } - c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL); - /* DS parameter set */ - c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL); + mpath = rtw_mesh_path_add(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } - /* TIM */ - *c = WLAN_EID_TIM; - *(c + 1) = 4; - c += 6; - //c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL); + rtw_mesh_path_fix_nexthop(mpath, sta); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} - /* Extended Supported Rates */ - if (n_bitrates > 8) - c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL); +static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst + #else + , u8 *dst + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; - /* RSN */ - if (rsn_ie) - c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL); + if (dst) { + if (rtw_mesh_path_del(adapter, dst)) { + ret = -ENOENT; + goto exit; + } + } else { + rtw_mesh_path_flush_by_iface(adapter); + } -#if defined(CONFIG_80211N_HT) - if (ht) { - struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap; - u8 ht_cap[HT_CAP_IE_LEN]; - u8 ht_op[HT_OP_IE_LEN]; +exit: + return ret; +} - _rtw_memset(ht_cap, 0, HT_CAP_IE_LEN); - _rtw_memset(ht_op, 0, HT_OP_IE_LEN); +static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; - /* WLAN_EID_HT_CAP */ - RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap); - SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor); - SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density); - _rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16); - c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL); + rtw_rcu_read_lock(); - /* WLAN_EID_HT_OPERATION */ - SET_HT_OP_ELE_PRI_CHL(ht_op, ch); - switch (offset) { - case HAL_PRIME_CHNL_OFFSET_LOWER: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA); - break; - case HAL_PRIME_CHNL_OFFSET_UPPER: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB); - break; - case HAL_PRIME_CHNL_OFFSET_DONT_CARE: - default: - SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN); - break; - } - if (bw >= CHANNEL_WIDTH_40) - SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1); - else - SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0); - c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL); + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; } -#endif /* defined(CONFIG_80211N_HT) */ -#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - if (vht) { - struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap; - u8 vht_cap[VHT_CAP_IE_LEN]; - u8 vht_op[VHT_OP_IE_LEN]; - u8 cch = rtw_get_center_ch(ch, bw, offset); + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } - _rtw_memset(vht_op, 0, VHT_OP_IE_LEN); + rtw_mesh_path_fix_nexthop(mpath, sta); - /* WLAN_EID_VHT_CAPABILITY */ - _rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4); - _rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8); - c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL); +exit: + rtw_rcu_read_unlock(); - /* WLAN_EID_VHT_OPERATION */ - if (bw < CHANNEL_WIDTH_80) { - SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); - } else if (bw == CHANNEL_WIDTH_80) { - SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); - } else { - RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); - rtw_warn_on(1); - rtw_mfree(ies, len); - goto exit; - } + return ret; +} - /* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */ - vht_op[3] = 0xfc; - vht_op[4] = 0xff; - c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL); - } -#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ +static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo) +{ + struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop); - /* Mesh ID */ - c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len); + if (next_hop_sta) + _rtw_memcpy(next_hop, next_hop_sta->phl_sta->mac_addr, ETH_ALEN); + else + _rtw_memset(next_hop, 0, ETH_ALEN); - /* Mesh configuration */ - c = rtw_set_ie_mesh_config(c, NULL - , minfo->mesh_pp_id - , minfo->mesh_pm_id - , minfo->mesh_cc_id - , minfo->mesh_sp_id - , minfo->mesh_auth_id - , 0, 0, 0 - , 1 - , 0, 0 - , mcfg->dot11MeshForwarding - , 0, 0, 0 - ); + _rtw_memset(pinfo, 0, sizeof(*pinfo)); -#if DBG_RTW_CFG80211_MESH_CONF - RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len); - dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_); -#endif + pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation; -exit: - if (ies) - *ies_len = len; - return ies; + pinfo->filled = 0 + | MPATH_INFO_FRAME_QLEN + | MPATH_INFO_SN + | MPATH_INFO_METRIC + | MPATH_INFO_EXPTIME + | MPATH_INFO_DISCOVERY_TIMEOUT + | MPATH_INFO_DISCOVERY_RETRIES + | MPATH_INFO_FLAGS + ; + + pinfo->frame_qlen = mpath->frame_queue_len; + pinfo->sn = mpath->sn; + pinfo->metric = mpath->metric; + if (rtw_time_after(mpath->exp_time, rtw_get_current_time())) + pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time); + pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout); + pinfo->discovery_retries = mpath->discovery_retries; + if (mpath->flags & RTW_MESH_PATH_ACTIVE) + pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE; + if (mpath->flags & RTW_MESH_PATH_RESOLVING) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING; + if (mpath->flags & RTW_MESH_PATH_SN_VALID) + pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID; + if (mpath->flags & RTW_MESH_PATH_FIXED) + pinfo->flags |= NL80211_MPATH_FLAG_FIXED; + if (mpath->flags & RTW_MESH_PATH_RESOLVED) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED; } -static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev - , struct mesh_config *conf) +static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) { _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg; + struct rtw_mesh_path *mpath; int ret = 0; - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + rtw_rcu_read_lock(); - /* driver MPM */ - conf->dot11MeshRetryTimeout = 0; - conf->dot11MeshConfirmTimeout = 0; - conf->dot11MeshHoldingTimeout = 0; - conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links; - conf->dot11MeshMaxRetries = 0; + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } - conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL; - conf->element_ttl = mesh_cfg->element_ttl; + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); - /* driver MPM */ - conf->auto_open_plinks = 0; +exit: + rtw_rcu_read_unlock(); - /* TBD: synchronization */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - conf->dot11MeshNbrOffsetMaxNeighbor = 0; -#endif + return ret; +} - conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries; - conf->path_refresh_time = mesh_cfg->path_refresh_time; - conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout; - conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout; - conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) - conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval; -#endif - conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime; - conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) - conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval; -#endif - conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) - conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding; - conf->rssi_threshold = mesh_cfg->rssi_threshold; -#endif +static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; - /* TBD */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) - conf->ht_opmode = 0xffff; -#endif + rtw_rcu_read_lock(); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout; - conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval; - conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval; -#endif + mpath = rtw_mesh_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; + goto exit; + } - /* TBD: power save */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) - conf->power_mode = NL80211_MESH_POWER_ACTIVE; - conf->dot11MeshAwakeWindowDuration = 0; -#endif + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - conf->plink_timeout = mesh_cfg->plink_timeout; -#endif +exit: + rtw_rcu_read_unlock(); return ret; } -static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) +static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo) { - if (need_work) - rtw_mesh_work(&adapter->mesh_work); + _rtw_memcpy(mpp, mpath->mpp, ETH_ALEN); + + _rtw_memset(pinfo, 0, sizeof(*pinfo)); + pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation; } -static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev - , u32 mask, const struct mesh_config *nconf) +static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo) { _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; int ret = 0; - bool minfo_changed = _FALSE, need_work = _FALSE; - RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask); + rtw_rcu_read_lock(); - rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask); - update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0); -#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER - if (rtw_mesh_cto_mgate_required(adapter)) - rtw_netif_carrier_off(adapter->pnetdev); - else - rtw_netif_carrier_on(adapter->pnetdev); -#endif - need_work = rtw_ieee80211_mesh_root_setup(adapter); + mpath = rtw_mpp_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } - rtw_mbss_info_change_notify(adapter, minfo_changed, need_work); + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); + +exit: + rtw_rcu_read_unlock(); return ret; } -static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev, - const struct mesh_config *conf, const struct mesh_setup *setup) +static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo) { _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 *ies = NULL; - uint ies_len; + struct rtw_mesh_path *mpath; int ret = 0; - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - -#if DBG_RTW_CFG80211_MESH_CONF - RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter)); - dump_mesh_setup(RTW_DBGDUMP, wiphy, setup); - RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter)); - dump_mesh_config(RTW_DBGDUMP, conf); -#endif + rtw_rcu_read_lock(); - if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { - ret = -ENOTSUPP; + mpath = rtw_mpp_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; goto exit; } - /* initialization */ - rtw_mesh_init_mesh_info(adapter); + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); - /* apply cfg80211 settings*/ - rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup); - rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF); +exit: + rtw_rcu_read_unlock(); - /* apply cfg80211 settings (join only) */ - rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout); - #endif + return ret; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */ - rtw_ieee80211_mesh_root_setup(adapter); +#endif /* defined(CONFIG_RTW_MESH) */ - ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len); - if (!ies) { - ret = -EINVAL; - goto exit; +#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_sched_scan_request *request) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct cfg80211_ssid *ssids; + int n_ssids = 0; + int interval = 0; + int i = 0; + u8 ret; + + if (padapter->netif_up == _FALSE) { + RTW_INFO("%s: net device is down.\n", __func__); + return -EIO; } - /* start mbss */ - if (rtw_check_beacon_data(adapter, ies, ies_len) != _SUCCESS) { - ret = -EINVAL; + if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE || + check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE || + check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { + RTW_INFO("%s: device is busy.\n", __func__); + rtw_scan_abort(padapter, 0); + } + + if (request == NULL) { + RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__); + return -EINVAL; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) + interval = request->scan_plans->interval; +#else + interval = request->interval; +#endif + n_ssids = request->n_match_sets; + ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid)); + if(ssids == NULL) { + RTW_ERR("Fail to allocate ssids for PNO\n"); + return -ENOMEM; + } + for (i=0;in_match_sets;i++) { + ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len; + _rtw_memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid, + request->match_sets[i].ssid.ssid_len); + } +#else + interval = request->interval; + n_ssids = request->n_ssids; + ssids = request->ssids; +#endif +ret = rtw_android_cfg80211_pno_setup(dev, ssids, + n_ssids, interval); + if (ret < 0) { + RTW_INFO("%s ret: %d\n", __func__, ret); goto exit; } - - rtw_mesh_work(&adapter->mesh_work); + ret = rtw_android_pno_enable(dev, _TRUE); + if (ret < 0) { + RTW_INFO("%s ret: %d\n", __func__, ret); + goto exit; + } exit: - if (ies) - rtw_mfree(ies, ies_len); - if (ret) - rtw_mesh_deinit_mesh_info(adapter); - return ret; } -static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev) +static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, + struct net_device *dev) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - int ret = 0; + return rtw_android_pno_enable(dev, _FALSE); +} - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); +int cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) { + RTW_DBG("==> %s\n",__func__); + RTW_DBG("<== %s\n",__func__); + return 0; +} - rtw_mesh_deinit_mesh_info(adapter); +int cfg80211_rtw_resume(struct wiphy *wiphy) { - rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK); + _adapter *padapter = wiphy_to_adapter(wiphy); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sitesurvey_parm parm; + int i, len; - return ret; + + RTW_DBG("==> %s\n",__func__); + if (pwrpriv->wowlan_last_wake_reason == RX_PNO) { + + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + int PNOWakeupScanWaitCnt = 0; + + rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); + + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;ipnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { + len = pwrpriv->pno_ssid_list->node[i].SSID_len; + _rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len); + parm.ssid[i].SsidLength = len; + } + parm.ssid_num = pwrpriv->pnlo_info->ssid_num; + + _rtw_spinlock_bh(&pmlmepriv->lock); + //This modification fix PNO wakeup reconnect issue with hidden SSID AP. + //rtw_sitesurvey_cmd(padapter, NULL); + rtw_sitesurvey_cmd(padapter, &parm); + _rtw_spinunlock_bh(&pmlmepriv->lock); + + for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) { + if(check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) + break; + rtw_msleep_os(1000); + } + + _rtw_spinlock_bh(&pmlmepriv->lock); + cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy); + _rtw_spinunlock_bh(&pmlmepriv->lock); + + } + RTW_DBG("<== %s\n",__func__); + return 0; + } +#endif /* CONFIG_PNO_SUPPORT */ -static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - , const u8 *dst, const u8 *next_hop - #else - , u8 *dst, u8 *next_hop - #endif -) +static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_priv *stapriv = &adapter->stapriv; - struct sta_info *sta; - struct rtw_mesh_path *mpath; int ret = 0; + uint wps_ielen = 0; + u8 *wps_ie; + u32 p2p_ielen = 0; + u8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04}; + u8 *p2p_ie; + u32 wfd_ielen = 0; + u8 *wfd_ie; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + RTW_INFO(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len); + + if (len > 0) { + wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); + if (wps_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen); + #endif + + if (pmlmepriv->wps_beacon_ie) { + u32 free_len = pmlmepriv->wps_beacon_ie_len; + pmlmepriv->wps_beacon_ie_len = 0; + rtw_mfree(pmlmepriv->wps_beacon_ie, free_len); + pmlmepriv->wps_beacon_ie = NULL; + } + + pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen); + if (pmlmepriv->wps_beacon_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + + _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen); + pmlmepriv->wps_beacon_ie_len = wps_ielen; + + rtw_update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, RTW_CMDF_WAIT_ACK); + + } + + /* buf += wps_ielen; */ + /* len -= wps_ielen; */ + + #ifdef CONFIG_P2P + p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); + if (p2p_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen); + #endif - rtw_rcu_read_lock(); + if (pmlmepriv->p2p_beacon_ie) { + u32 free_len = pmlmepriv->p2p_beacon_ie_len; + pmlmepriv->p2p_beacon_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len); + pmlmepriv->p2p_beacon_ie = NULL; + } - sta = rtw_get_stainfo(stapriv, next_hop); - if (!sta) { - ret = -ENOENT; - goto exit; - } + pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen); + if (pmlmepriv->p2p_beacon_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; - mpath = rtw_mesh_path_add(adapter, dst); - if (!mpath) { - ret = -ENOENT; - goto exit; - } + } - rtw_mesh_path_fix_nexthop(mpath, sta); + _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_beacon_ie_len = p2p_ielen; -exit: - rtw_rcu_read_unlock(); + } + #endif /* CONFIG_P2P */ - return ret; -} -static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - , const u8 *dst - #else - , u8 *dst - #endif -) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - int ret = 0; + #ifdef CONFIG_WFD + wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); + if (wfd_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen); + #endif - if (dst) { - if (rtw_mesh_path_del(adapter, dst)) { - ret = -ENOENT; - goto exit; + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS) + return -EINVAL; } - } else { - rtw_mesh_path_flush_by_iface(adapter); - } + #endif /* CONFIG_WFD */ + + pmlmeext->bstart_bss = _TRUE; + + } -exit: return ret; + } -static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - , const u8 *dst, const u8 *next_hop - #else - , u8 *dst, u8 *next_hop - #endif -) +static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_priv *stapriv = &adapter->stapriv; - struct sta_info *sta; - struct rtw_mesh_path *mpath; int ret = 0; + uint wps_ielen = 0; + u8 *wps_ie; + u32 p2p_ielen = 0; + u8 *p2p_ie; + u32 wfd_ielen = 0; + u8 *wfd_ie; + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - rtw_rcu_read_lock(); +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("%s, ielen=%d\n", __func__, len); +#endif - sta = rtw_get_stainfo(stapriv, next_hop); - if (!sta) { - ret = -ENOENT; - goto exit; - } + if (len > 0) { + wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); + if (wps_ie) { + uint attr_contentlen = 0; + u16 uconfig_method, *puconfig_method = NULL; - mpath = rtw_mesh_path_lookup(adapter, dst); - if (!mpath) { - ret = -ENOENT; - goto exit; - } + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen); + #endif - rtw_mesh_path_fix_nexthop(mpath, sta); + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + u8 sr = 0; + rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); -exit: - rtw_rcu_read_unlock(); + if (sr != 0) + RTW_INFO("%s, got sr\n", __func__); + else { + RTW_INFO("GO mode process WPS under site-survey, sr no set\n"); + return ret; + } + } - return ret; -} + if (pmlmepriv->wps_probe_resp_ie) { + u32 free_len = pmlmepriv->wps_probe_resp_ie_len; + pmlmepriv->wps_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len); + pmlmepriv->wps_probe_resp_ie = NULL; + } -static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo) -{ - struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop); + pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen); + if (pmlmepriv->wps_probe_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; - if (next_hop_sta) - _rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN); - else - _rtw_memset(next_hop, 0, ETH_ALEN); + } - _rtw_memset(pinfo, 0, sizeof(*pinfo)); + /* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */ + puconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen); + if (puconfig_method != NULL) { + /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */ + struct wireless_dev *wdev = padapter->rtw_wdev; - pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation; + #ifdef CONFIG_DEBUG_CFG80211 + /* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */ + #endif - pinfo->filled = 0 - | MPATH_INFO_FRAME_QLEN - | MPATH_INFO_SN - | MPATH_INFO_METRIC - | MPATH_INFO_EXPTIME - | MPATH_INFO_DISCOVERY_TIMEOUT - | MPATH_INFO_DISCOVERY_RETRIES - | MPATH_INFO_FLAGS - ; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + /* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */ + if (wdev->iftype == NL80211_IFTYPE_P2P_GO) { + uconfig_method = WPS_CM_PUSH_BUTTON; + uconfig_method = cpu_to_be16(uconfig_method); - pinfo->frame_qlen = mpath->frame_queue_len; - pinfo->sn = mpath->sn; - pinfo->metric = mpath->metric; - if (rtw_time_after(mpath->exp_time, rtw_get_current_time())) - pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time); - pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout); - pinfo->discovery_retries = mpath->discovery_retries; - if (mpath->flags & RTW_MESH_PATH_ACTIVE) - pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE; - if (mpath->flags & RTW_MESH_PATH_RESOLVING) - pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING; - if (mpath->flags & RTW_MESH_PATH_SN_VALID) - pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID; - if (mpath->flags & RTW_MESH_PATH_FIXED) - pinfo->flags |= NL80211_MPATH_FLAG_FIXED; - if (mpath->flags & RTW_MESH_PATH_RESOLVED) - pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED; -} + *puconfig_method &= ~uconfig_method; + } + #endif + } -static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rtw_mesh_path *mpath; - int ret = 0; + _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); + pmlmepriv->wps_probe_resp_ie_len = wps_ielen; - rtw_rcu_read_lock(); + } - mpath = rtw_mesh_path_lookup(adapter, dst); - if (!mpath) { - ret = -ENOENT; - goto exit; - } + /* buf += wps_ielen; */ + /* len -= wps_ielen; */ - rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + #ifdef CONFIG_P2P + p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); + if (p2p_ie) { + u8 is_GO = _FALSE; + u32 attr_contentlen = 0; + u16 cap_attr = 0; -exit: - rtw_rcu_read_unlock(); + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen); + #endif - return ret; -} + /* Check P2P Capability ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { + u8 grp_cap = 0; + /* RTW_INFO( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); */ + cap_attr = le16_to_cpu(cap_attr); + grp_cap = (u8)((cap_attr >> 8) & 0xff); -static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rtw_mesh_path *mpath; - int ret = 0; + is_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE; - rtw_rcu_read_lock(); + if (is_GO) + RTW_INFO("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap); + } - mpath = rtw_mesh_path_lookup_by_idx(adapter, idx); - if (!mpath) { - ret = -ENOENT; - goto exit; - } - _rtw_memcpy(dst, mpath->dst, ETH_ALEN); - rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + if (is_GO == _FALSE) { + if (pmlmepriv->p2p_probe_resp_ie) { + u32 free_len = pmlmepriv->p2p_probe_resp_ie_len; + pmlmepriv->p2p_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len); + pmlmepriv->p2p_probe_resp_ie = NULL; + } + + pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen); + if (pmlmepriv->p2p_probe_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen; + } else { + if (pmlmepriv->p2p_go_probe_resp_ie) { + u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len; + pmlmepriv->p2p_go_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len); + pmlmepriv->p2p_go_probe_resp_ie = NULL; + } -exit: - rtw_rcu_read_unlock(); + pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen); + if (pmlmepriv->p2p_go_probe_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; - return ret; -} + } + _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen; + } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) -static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo) -{ - _rtw_memcpy(mpp, mpath->mpp, ETH_ALEN); + } + #endif /* CONFIG_P2P */ - _rtw_memset(pinfo, 0, sizeof(*pinfo)); - pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation; -} -static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rtw_mesh_path *mpath; - int ret = 0; + #ifdef CONFIG_WFD + wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen); + #endif - rtw_rcu_read_lock(); + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS) + return -EINVAL; + #endif /* CONFIG_WFD */ - mpath = rtw_mpp_path_lookup(adapter, dst); - if (!mpath) { - ret = -ENOENT; - goto exit; } - rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); - -exit: - rtw_rcu_read_unlock(); - return ret; + } -static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo) +static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rtw_mesh_path *mpath; int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *ie; + u32 ie_len; - rtw_rcu_read_lock(); + RTW_INFO("%s, ielen=%d\n", __func__, len); - mpath = rtw_mpp_path_lookup_by_idx(adapter, idx); - if (!mpath) { - ret = -ENOENT; + if (len <= 0) goto exit; - } - - _rtw_memcpy(dst, mpath->dst, ETH_ALEN); - rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); -exit: - rtw_rcu_read_unlock(); - - return ret; -} -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */ + ie = rtw_get_wps_ie(buf, len, NULL, &ie_len); + if (ie && ie_len) { + if (pmlmepriv->wps_assoc_resp_ie) { + u32 free_len = pmlmepriv->wps_assoc_resp_ie_len; -#endif /* defined(CONFIG_RTW_MESH) */ + pmlmepriv->wps_assoc_resp_ie_len = 0; + rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len); + pmlmepriv->wps_assoc_resp_ie = NULL; + } -#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) -static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, - struct net_device *dev, - struct cfg80211_sched_scan_request *request) -{ + pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); + if (pmlmepriv->wps_assoc_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len); + pmlmepriv->wps_assoc_resp_ie_len = ie_len; + } - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct cfg80211_ssid *ssids; - int n_ssids = 0; - int interval = 0; - int i = 0; - u8 ret; + ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len); + if (ie && ie_len) { + if (pmlmepriv->p2p_assoc_resp_ie) { + u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len; - if (padapter->bup == _FALSE) { - RTW_INFO("%s: net device is down.\n", __func__); - return -EIO; - } + pmlmepriv->p2p_assoc_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len); + pmlmepriv->p2p_assoc_resp_ie = NULL; + } - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE || - check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE || - check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) { - RTW_INFO("%s: device is busy.\n", __func__); - rtw_scan_abort(padapter); + pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len); + if (pmlmepriv->p2p_assoc_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len); + pmlmepriv->p2p_assoc_resp_ie_len = ie_len; } - if (request == NULL) { - RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__); +#ifdef CONFIG_WFD + ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len); + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS) return -EINVAL; - } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) - interval = request->scan_plans->interval; -#else - interval = request->interval; -#endif - n_ssids = request->n_match_sets; - ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid)); - if(ssids == NULL) { - RTW_ERR("Fail to allocate ssids for PNO\n"); - return -ENOMEM; - } - for (i=0;in_match_sets;i++) { - ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len; - memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid, - request->match_sets[i].ssid.ssid_len); - } -#else - interval = request->interval; - n_ssids = request->n_ssids; - ssids = request->ssids; #endif -ret = rtw_android_cfg80211_pno_setup(dev, ssids, - n_ssids, interval); - if (ret < 0) { - RTW_INFO("%s ret: %d\n", __func__, ret); - goto exit; - } - ret = rtw_android_pno_enable(dev, _TRUE); - if (ret < 0) { - RTW_INFO("%s ret: %d\n", __func__, ret); - goto exit; - } exit: return ret; } -static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, - struct net_device *dev) +int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, + int type) { - return rtw_android_pno_enable(dev, _FALSE); -} - -int cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) { - RTW_DBG("==> %s\n",__func__); - RTW_DBG("<== %s\n",__func__); - return 0; -} - -int cfg80211_rtw_resume(struct wiphy *wiphy) { - - _adapter *padapter; - struct pwrctrl_priv *pwrpriv; - struct mlme_priv *pmlmepriv; - padapter = wiphy_to_adapter(wiphy); - pwrpriv = adapter_to_pwrctl(padapter); - pmlmepriv = &padapter->mlmepriv; - struct sitesurvey_parm parm; - int i, len; - - - RTW_DBG("==> %s\n",__func__); - if (pwrpriv->wowlan_last_wake_reason == RX_PNO) { - - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - _irqL irqL; - int PNOWakeupScanWaitCnt = 0; - - rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); + int ret = 0; + uint wps_ielen = 0; + u32 p2p_ielen = 0; - rtw_init_sitesurvey_parm(padapter, &parm); - for (i=0;ipnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { - len = pwrpriv->pno_ssid_list->node[i].SSID_len; - _rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len); - parm.ssid[i].SsidLength = len; - } - parm.ssid_num = pwrpriv->pnlo_info->ssid_num; +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("%s, ielen=%d\n", __func__, len); +#endif - _enter_critical_bh(&pmlmepriv->lock, &irqL); - //This modification fix PNO wakeup reconnect issue with hidden SSID AP. - //rtw_sitesurvey_cmd(padapter, NULL); - rtw_sitesurvey_cmd(padapter, &parm); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - - for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) { - if(check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) + if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0)) + #ifdef CONFIG_P2P + || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0)) + #endif + ) { + if (net != NULL) { + switch (type) { + case 0x1: /* BEACON */ + ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len); break; - rtw_msleep_os(1000); + case 0x2: /* PROBE_RESP */ + ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); + #ifdef CONFIG_P2P + if (ret == 0) + adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time(); + #endif + break; + case 0x4: /* ASSOC_RESP */ + ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); + break; + } } - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - } - RTW_DBG("<== %s\n",__func__); - return 0; - + + return ret; + } -#endif /* CONFIG_PNO_SUPPORT */ #ifdef CONFIG_80211N_HT -static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter - , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) +static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, + struct ieee80211_sta_ht_cap *ht_cap, enum band_type band, u8 rf_type, + struct protocol_cap_t *dft_proto_cap, struct role_cap_t *dft_cap) { struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; u8 stbc_rx_enable = _FALSE; - rtw_ht_use_default_setting(padapter); + rtw_ht_get_dft_setting(padapter, dft_proto_cap, dft_cap); /* RX LDPC */ if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) @@ -9763,37 +9487,29 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter /* RX STBC */ if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { - /*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/ - if (band == BAND_ON_2_4G) - stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE; - if (band == BAND_ON_5G) - stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE; - - if (stbc_rx_enable) { - switch (rf_type) { - case RF_1T1R: - ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/ - break; - - case RF_2T2R: - case RF_1T2R: - ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ - break; - case RF_3T3R: - case RF_3T4R: - case RF_4T4R: - ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ - break; - default: - RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); - break; - } + switch (rf_type) { + case RF_1T1R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/ + break; + case RF_2T2R: + case RF_1T2R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ + break; + case RF_3T3R: + case RF_3T4R: + case RF_4T4R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ + break; + default: + RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); + break; } } } -static void rtw_cfg80211_init_ht_capab(_adapter *padapter - , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) +static void rtw_cfg80211_init_ht_capab(_adapter *padapter, + struct ieee80211_sta_ht_cap *ht_cap, enum band_type band, u8 rf_type, + struct protocol_cap_t *dft_proto_cap, struct role_cap_t *dft_cap) { struct registry_priv *regsty = &padapter->registrypriv; u8 rx_nss = 0; @@ -9801,24 +9517,13 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter if (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode)) return; - ht_cap->ht_supported = 1; - - ht_cap->cap = IEEE80211_HT_CAP_MAX_AMSDU; - - if (TEST_FLAG(regsty->short_gi, BIT0)) - ht_cap->cap |= IEEE80211_HT_CAP_SGI_20; - if (hal_is_bw_support(padapter, CHANNEL_WIDTH_40) - && ((band == BAND_ON_2_4G && REGSTY_IS_BW_2G_SUPPORT(regsty, CHANNEL_WIDTH_40)) - || (band == BAND_ON_5G && REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40))) - ) { - ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; - if (band == BAND_ON_2_4G) - ht_cap->cap |= IEEE80211_HT_CAP_DSSSCCK40; - if (TEST_FLAG(regsty->short_gi, BIT1)) - ht_cap->cap |= IEEE80211_HT_CAP_SGI_40; - } + ht_cap->ht_supported = 1; - rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type); + ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | + IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | + IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; + rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type, + dft_proto_cap, dft_cap); /* *Maximum length of AMPDU that the STA can receive. @@ -9831,7 +9536,7 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; - rx_nss = GET_HAL_RX_NSS(padapter); + rx_nss = GET_HAL_RX_NSS(adapter_to_dvobj(padapter)); switch (rx_nss) { case 1: ht_cap->mcs.rx_mask[0] = 0xFF; @@ -9852,20 +9557,22 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter ht_cap->mcs.rx_mask[3] = 0xFF; break; default: + RTW_ERR("%s, error rf_type=%d, rx_nss=%d\n", __func__, rf_type, rx_nss); rtw_warn_on(1); - RTW_INFO("%s, error rf_type=%d, rx_nss=%d\n", __func__, rf_type, rx_nss); }; ht_cap->mcs.rx_highest = cpu_to_le16( - rtw_ht_mcs_rate(hal_is_bw_support(padapter, CHANNEL_WIDTH_40) - , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 + rtw_ht_mcs_rate(rtw_hw_is_bw_support(adapter_to_dvobj(padapter), CHANNEL_WIDTH_40) + , rtw_hw_is_bw_support(adapter_to_dvobj(padapter), CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 , ht_cap->mcs.rx_mask) / 10); } #endif /* CONFIG_80211N_HT */ #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) -static void rtw_cfg80211_init_vht_capab(_adapter *padapter - , struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type) +static void rtw_cfg80211_init_vht_capab(_adapter *padapter, + struct ieee80211_sta_vht_cap *sta_vht_cap, + enum band_type band, u8 rf_type, struct protocol_cap_t *dft_proto_cap, + struct role_cap_t *dft_cap) { struct registry_priv *regsty = &padapter->registrypriv; u8 vht_cap_ie[2 + 12] = {0}; @@ -9873,7 +9580,8 @@ static void rtw_cfg80211_init_vht_capab(_adapter *padapter if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode)) return; - rtw_vht_use_default_setting(padapter); + rtw_vht_get_dft_setting(padapter, dft_proto_cap, dft_cap); + rtw_build_vht_cap_ie(padapter, vht_cap_ie); sta_vht_cap->vht_supported = 1; @@ -9883,36 +9591,153 @@ static void rtw_cfg80211_init_vht_capab(_adapter *padapter } #endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ -void rtw_cfg80211_init_wdev_data(_adapter *padapter) +#if defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))) +static int rtw_cfg80211_init_he_capab(_adapter *padapter, + struct ieee80211_sband_iftype_data *sta_iface_data, + enum nl80211_iftype iftype, struct phy_cap_t *phy_cap, + struct protocol_cap_t *dft_proto_cap) { -#ifdef CONFIG_CONCURRENT_MODE - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct ieee80211_sta_he_cap *sta_he_cap = &(sta_iface_data->he_cap); + void *phl = GET_PHL_INFO(adapter_to_dvobj(padapter)); + struct registry_priv *regsty = &padapter->registrypriv; + u8 cap_len = 0; + u8 he_mcs_set_ext_len = 0; + u8 he_cap_ie[HE_CAP_ELE_MAX_LEN] = {0}; + u8 ofst_80m = 3 + HE_CAP_ELE_MAC_CAP_LEN + HE_CAP_ELE_PHY_CAP_LEN; + u8 ofst_160m = ofst_80m + 4; + u8 ofst_80p80m = ofst_80m + 4; + + if (!REGSTY_IS_11AX_ENABLE(regsty) || !is_supported_he(regsty->wireless_mode)) + return _FAIL; + + + sta_iface_data->types_mask = BIT(iftype); + cap_len = rtw_get_dft_he_cap_ie(padapter, phy_cap, dft_proto_cap, he_cap_ie); + + sta_he_cap->has_he = 1; + + /* mac & phy capability info */ + _rtw_memcpy(&sta_he_cap->he_cap_elem.mac_cap_info, he_cap_ie + 3, HE_CAP_ELE_MAC_CAP_LEN); + _rtw_memcpy(&sta_he_cap->he_cap_elem.phy_cap_info, + he_cap_ie + 3 + HE_CAP_ELE_MAC_CAP_LEN, + HE_CAP_ELE_PHY_CAP_LEN); + + /* Supported HE-MCS And NSS Set */ + /* HE supports 80M BW */ + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.rx_mcs_80, he_cap_ie + ofst_80m, 2); + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.tx_mcs_80, he_cap_ie + ofst_80m + 2, 2); + + /* HE supports 160M BW */ + if(GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(he_cap_ie + 3 + HE_CAP_ELE_MAC_CAP_LEN) & BIT2) { + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.rx_mcs_160, he_cap_ie + ofst_160m, 2); + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.tx_mcs_160, he_cap_ie + ofst_160m + 2, 2); + ofst_80p80m += 4; + } else { + _rtw_memset(&sta_he_cap->he_mcs_nss_supp.rx_mcs_160, HE_MSC_NOT_SUPP_BYTE, 2); + _rtw_memset(&sta_he_cap->he_mcs_nss_supp.tx_mcs_160, HE_MSC_NOT_SUPP_BYTE, 2); + } - ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); -#endif + /* HE supports 80M+80M BW */ + if(GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(he_cap_ie + 3 + HE_CAP_ELE_MAC_CAP_LEN) & BIT3) { + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.rx_mcs_80p80, he_cap_ie + ofst_80p80m, 2); + _rtw_memcpy(&sta_he_cap->he_mcs_nss_supp.tx_mcs_80p80, he_cap_ie + ofst_80p80m + 2, 2); + } else { + _rtw_memset(&sta_he_cap->he_mcs_nss_supp.rx_mcs_80p80, HE_MSC_NOT_SUPP_BYTE, 2); + _rtw_memset(&sta_he_cap->he_mcs_nss_supp.tx_mcs_80p80, HE_MSC_NOT_SUPP_BYTE, 2); + } + + return _SUCCESS; +} + + +static void rtw_cfg80211_init_sband_iftype_data(_adapter *padapter, + struct ieee80211_supported_band *band, struct phy_cap_t *phy_cap, + struct role_cap_t *dft_cap, + struct protocol_cap_t *dft_sta_proto_cap, + struct protocol_cap_t *dft_ap_proto_cap) +{ + struct ieee80211_sband_iftype_data *he_iftype = NULL; + void *phl = GET_PHL_INFO(adapter_to_dvobj(padapter)); + int ret = _FAIL; + + he_iftype = (struct ieee80211_sband_iftype_data *)(((u8 *)band->bitrates) + + sizeof(struct ieee80211_rate) * band->n_bitrates); + + ret = rtw_cfg80211_init_he_capab(padapter, he_iftype, + NL80211_IFTYPE_AP, phy_cap, dft_ap_proto_cap); + if (ret == _SUCCESS) + band->n_iftype_data += 1; + + he_iftype += 1; + ret = rtw_cfg80211_init_he_capab(padapter, he_iftype, + NL80211_IFTYPE_STATION, phy_cap, dft_sta_proto_cap); + + if (ret == _SUCCESS) + band->n_iftype_data += 1; } +#endif /* defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) */ static int rtw_cfg80211_init_wiphy_band(_adapter *padapter, struct wiphy *wiphy) { u8 rf_type; struct ieee80211_supported_band *band; int ret = _FAIL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - rf_type = GET_HAL_RFPATH(padapter); + struct protocol_cap_t dft_sta_proto_cap = {0}; + struct protocol_cap_t dft_ap_proto_cap = {0}; + struct role_cap_t dft_cap = {0}; + struct phy_cap_t *phy_cap; + u8 hw_band = HW_BAND_0; + + /*init wiphy0 for band0*/ + rtw_phl_get_dft_cap(dvobj->phl, hw_band, &dft_cap); + + rtw_phl_get_dft_proto_cap(dvobj->phl, hw_band, + PHL_RTYPE_STATION, &dft_sta_proto_cap); + rtw_phl_get_dft_proto_cap(dvobj->phl, hw_band, + PHL_RTYPE_AP, &dft_ap_proto_cap); + phy_cap = &(dvobj->phl_com->phy_cap[hw_band]); + + /*TODO init wiphy1 for band1*/ + #if 0 /*#ifdef CONFIG_DBCC_SUPPORT*/ + /*if (dvobj->phl_com->dev_cap.hw_sup_flags & HW_SUP_DBCC)*/ + if (dvobj->phl_com->dev_cap.dbcc_sup) { + hw_band = HW_BAND_1; + rtw_phl_get_dft_cap(dvobj->phl, hw_band, &dft_cap); + + rtw_phl_get_dft_proto_cap(dvobj->phl, hw_band, + PHL_RTYPE_STATION, &dft_sta_proto_cap); + rtw_phl_get_dft_proto_cap(dvobj->phl, hw_band, + PHL_RTYPE_AP, &dft_ap_proto_cap); + phy_cap = &(dvobj->phl_com->phy_cap[hw_band]); + } + #endif + + rf_type = GET_HAL_RFPATH(dvobj); RTW_INFO("%s:rf_type=%d\n", __func__, rf_type); - if (IsSupported24G(padapter->registrypriv.wireless_mode)) { - band = wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G); + + if (is_supported_24g(padapter->registrypriv.band_type)) { + + band = wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_24G); if (!band) goto exit; rtw_2g_channels_init(band->channels); rtw_2g_rates_init(band->bitrates); #if defined(CONFIG_80211N_HT) - rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type); + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, + BAND_ON_24G, rf_type, &dft_sta_proto_cap, &dft_cap); #endif + #if defined(CONFIG_80211AX_HE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) + rtw_cfg80211_init_sband_iftype_data(padapter, band, phy_cap, + &dft_cap, &dft_sta_proto_cap, &dft_ap_proto_cap); + #endif /* defined(CONFIG_80211AX_HE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) */ } -#if CONFIG_IEEE80211_BAND_5GHZ - if (is_supported_5g(padapter->registrypriv.wireless_mode)) { + + #if CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(padapter->registrypriv.band_type)) { + band = wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G); if (!band) { if (wiphy->bands[NL80211_BAND_2GHZ]) { @@ -9924,58 +9749,27 @@ static int rtw_cfg80211_init_wiphy_band(_adapter *padapter, struct wiphy *wiphy) rtw_5g_channels_init(band->channels); rtw_5g_rates_init(band->bitrates); #if defined(CONFIG_80211N_HT) - rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type); + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, + BAND_ON_5G, rf_type, &dft_sta_proto_cap, &dft_cap); #endif #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type); + rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, + BAND_ON_5G, rf_type, &dft_sta_proto_cap, &dft_cap); #endif + #if defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))) + rtw_cfg80211_init_sband_iftype_data(padapter, band, phy_cap, + &dft_cap, &dft_sta_proto_cap, &dft_ap_proto_cap); + #endif /* defined(CONFIG_80211AX_HE) && (defined(CPTCFG_VERSION) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) */ } -#endif - + #endif ret = _SUCCESS; exit: return ret; -} - -#if !defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) -void rtw_cfg80211_update_wiphy_max_txpower(_adapter *adapter, struct wiphy *wiphy) -{ - struct ieee80211_supported_band *band; - struct ieee80211_channel *channel; - s16 max_txpwr; - int i; - if (IsSupported24G(adapter->registrypriv.wireless_mode)) { - band = wiphy->bands[NL80211_BAND_2GHZ]; - if (band) { - max_txpwr = phy_get_txpwr_by_rate_total_max_mbm(adapter, BAND_ON_2_4G, 1, 1); - if (max_txpwr != UNSPECIFIED_MBM) { - for (i = 0; i < band->n_channels; i++) { - channel = &band->channels[i]; - channel->max_power = max_txpwr / MBM_PDBM; - } - } - } - } -#if CONFIG_IEEE80211_BAND_5GHZ - if (is_supported_5g(adapter->registrypriv.wireless_mode)) { - band = wiphy->bands[NL80211_BAND_5GHZ]; - if (band) { - max_txpwr = phy_get_txpwr_by_rate_total_max_mbm(adapter, BAND_ON_5G, 1, 1); - if (max_txpwr != UNSPECIFIED_MBM) { - for (i = 0; i < band->n_channels; i++) { - channel = &band->channels[i]; - channel->max_power = max_txpwr / MBM_PDBM; - } - } - } - } -#endif } -#endif /* defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && (CONFIG_IFACE_NUMBER >= 2) struct ieee80211_iface_limit rtw_limits[] = { { .max = CONFIG_IFACE_NUMBER, @@ -10044,35 +9838,31 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION; #endif - wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) - #ifdef CONFIG_AP_MODE - | BIT(NL80211_IFTYPE_ADHOC) /* todo : AD-HOC task group will refine it */ - | BIT(NL80211_IFTYPE_AP) - #endif - #ifdef CONFIG_WIFI_MONITOR - | BIT(NL80211_IFTYPE_MONITOR) - #endif -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - | BIT(NL80211_IFTYPE_P2P_CLIENT) - | BIT(NL80211_IFTYPE_P2P_GO) - #if defined(RTW_DEDICATED_P2P_DEVICE) - | BIT(NL80211_IFTYPE_P2P_DEVICE) - #endif -#endif -#ifdef CONFIG_RTW_MESH - | BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */ -#endif - ; + wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) + | BIT(NL80211_IFTYPE_ADHOC) + #ifdef CONFIG_AP_MODE + | BIT(NL80211_IFTYPE_AP) + #ifdef CONFIG_WIFI_MONITOR + | BIT(NL80211_IFTYPE_MONITOR) + #endif + #endif + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_CLIENT) + | BIT(NL80211_IFTYPE_P2P_GO) + #if defined(RTW_DEDICATED_P2P_DEVICE) + | BIT(NL80211_IFTYPE_P2P_DEVICE) + #endif + #endif -#if !defined(RTW_SINGLE_WIPHY) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) - if (adapter->iface_id != adapter->registrypriv.sel_p2p_iface) { - wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT)); - RTW_INFO("%s iface_id:%d- don't set p2p capability\n", __func__, adapter->iface_id); - } -#endif + #ifdef CONFIG_RTW_MESH + | BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */ + #endif + ; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) +#ifdef CONFIG_AP_MODE wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; +#endif /* CONFIG_AP_MODE */ #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) @@ -10081,32 +9871,18 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) #endif #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && (CONFIG_IFACE_NUMBER >= 2) wiphy->iface_combinations = rtw_combinations; wiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations); #endif wiphy->cipher_suites = rtw_cipher_suites; - - /* Todo refine */ - if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_EXTRA_SEC)) - wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); - else { -#ifdef CONFIG_IEEE80211W - /* remove hardware not support cipher */ - wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites) - 6; -#else - wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); -#endif - } + wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); if (rtw_cfg80211_init_wiphy_band(adapter, wiphy) != _SUCCESS) { RTW_ERR("rtw_cfg80211_init_wiphy_band fail\n"); goto exit; } - #if !defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) - rtw_cfg80211_update_wiphy_max_txpower(adapter, wiphy); - #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0)) wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS; @@ -10115,11 +9891,15 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME; - /* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */ - /* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */ + /* OFFCHAN_TX not ready, Mgmt tx depend on REMAIN_ON_CHANNEL */ + /* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX; */ #endif -#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \ +#if (KERNEL_VERSION(3, 2, 0) <= LINUX_VERSION_CODE) + wiphy->flags |= WIPHY_FLAG_AP_UAPSD; +#endif + +#if !defined(CPTCFG_VERSION) && defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \ LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; #ifdef CONFIG_PNO_SUPPORT @@ -10146,11 +9926,10 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) #endif /* CONFIG_TDLS_DRIVER_SETUP */ #endif /* CONFIG_TDLS */ -#ifdef CONFIG_LPS + if (regsty->power_mgnt != PM_PS_MODE_ACTIVE) wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT; -#else + else wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; -#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) /* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */ @@ -10186,20 +9965,10 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_RRM); #endif -#ifdef CONFIG_NET_NS - wiphy->flags |= WIPHY_FLAG_NETNS_OK; -#endif // NETNS - #if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE) wiphy->features |= NL80211_FEATURE_SAE; #endif -#ifdef CONFIG_RTW_SCAN_RAND - #if (KERNEL_VERSION(3, 19, 0) <= LINUX_VERSION_CODE) - wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; - #endif -#endif - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) #ifdef CONFIG_WIFI_MONITOR /* Currently only for Monitor debugging */ @@ -10207,6 +9976,13 @@ static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy) #endif #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) + wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + wiphy->max_num_csa_counters = MAX_CSA_CNT; +#endif + ret = _SUCCESS; exit: @@ -10257,13 +10033,58 @@ static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy) #define SURVEY_INFO_TIME_TX SURVEY_INFO_CHANNEL_TIME_TX #endif -#ifdef CONFIG_RTW_ACS -static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo) +#ifdef CONFIG_FIND_BEST_CHANNEL +static void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy + , struct net_device *netdev, int idx, struct survey_info *info) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *ch_set = rfctl->channel_set; + u8 ch_num = rfctl->max_chan_nums; + u32 total_rx_cnt = 0; + int i; + + s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ + u64 time = 100; /*amount of time in ms the radio was turn on (on the channel)*/ + u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ + + info->filled = SURVEY_INFO_NOISE_DBM + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY + #endif + ; + + for (i = 0; i < ch_num; i++) + total_rx_cnt += ch_set[i].rx_count; + + time_busy = ch_set[idx].rx_count * time / total_rx_cnt; + noise += ch_set[idx].rx_count * 50 / total_rx_cnt; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) + info->channel_time = time; + info->channel_time_busy = time_busy; + #else + info->time = time; + info->time_busy = time_busy; + #endif +#endif + info->noise = noise; + + /* reset if final channel is got */ + if (idx == ch_num - 1) { + for (i = 0; i < ch_num; i++) + ch_set[i].rx_count = 0; + } +} +#endif /* CONFIG_FIND_BEST_CHANNEL */ + +#if defined(CONFIG_RTW_ACS) /*&& defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/ +static void rtw_cfg80211_set_survey_info_with_clm(_adapter *padapter, int idx, struct survey_info *pinfo) { s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ - u64 time = SURVEY_TO; /*amount of time in ms the radio was turn on (on the channel)*/ - u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ - u8 chan = (u8)idx; + u8 time = SURVEY_TO; /*amount of time in ms the radio was turn on (on the channel)*/ + u8 time_busy = 0; /*amount of time the primary channel was sensed busy*/ if ((idx < 0) || (pinfo == NULL)) return; @@ -10274,9 +10095,10 @@ static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, st #endif ; - time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan); - noise = rtw_acs_get_nhm_noise_pwr_by_ch_idx(padapter, chan); - /* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */ + time_busy = rtw_acs_get_clm_ratio_by_idx(padapter, idx); + noise = rtw_noise_query_by_idx(padapter, idx); + RTW_INFO("[%d] ch=%d, time=%d(ms), time_busy=%d(ms), noise=%d(dbm)\n", + idx, pinfo->channel->hw_value, time, time_busy, noise); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) @@ -10289,14 +10111,11 @@ static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, st #endif pinfo->noise = noise; } -#endif /* CONFIG_RTW_ACS */ +#endif -static int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info) +int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info) { - PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - RT_CHANNEL_INFO *pch_set = rfctl->channel_set; - u8 max_chan_nums = rfctl->max_chan_nums; + _adapter *padapter = (_adapter *)rtw_netdev_priv(netdev); u32 freq = 0; u8 ret = 0; u16 channel = 0; @@ -10307,15 +10126,15 @@ static int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *n } _rtw_memset(info, 0, sizeof(struct survey_info)); - if (padapter->bup == _FALSE) { + if (padapter->netif_up == _FALSE) { RTW_INFO("%s: net device is down.\n", __func__); return -EIO; } - if (idx >= max_chan_nums) + if (idx >= MAX_CHANNEL_NUM) return -ENOENT; - channel = pch_set[idx].ChannelNum; + channel = rtw_acs_get_channel_by_idx(padapter, idx); freq = rtw_ch2freq(channel); info->channel = ieee80211_get_channel(wiphy, freq); /* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */ @@ -10326,22 +10145,18 @@ static int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *n if (info->channel->flags == IEEE80211_CHAN_DISABLED) return ret; -#ifdef CONFIG_RTW_ACS rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info); -#else - RTW_ERR("%s: unknown acs operation!\n", __func__); -#endif return ret; } #endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */ -#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ +#if defined(CPTCFG_VERSION) || (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH) int cfg80211_rtw_external_auth(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_external_auth_params *params) { - PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev)); @@ -10355,13 +10170,12 @@ int cfg80211_rtw_external_auth(struct wiphy *wiphy, struct net_device *dev, void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev, struct rtw_external_auth_params *params) { - PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct security_priv *psecuritypriv = &padapter->securitypriv; struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta = NULL; u8 *buf = NULL; u32 len = 0; - _irqL irqL; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev)); @@ -10374,8 +10188,8 @@ void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *d } psta = rtw_get_stainfo(pstapriv, params->bssid); - if (psta && (params->status == WLAN_STATUS_SUCCESS)) { -#ifdef CONFIG_AP_MODE + if (psta && (params->status == WLAN_STATUS_SUCCESS)\ + && MLME_IS_AP(padapter)) { /* AP mode */ RTW_INFO("station match\n"); @@ -10387,7 +10201,7 @@ void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *d /* RTW_INFO_DUMP("PMKID:", params->pmkid, PMKID_LEN); */ _rtw_set_pmksa(dev, params->bssid, params->pmkid); - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); if ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) { buf = rtw_zmalloc(psta->auth_len); if (buf) { @@ -10399,7 +10213,7 @@ void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *d psta->pauth_frame = NULL; psta->auth_len = 0; } - _exit_critical_bh(&psta->lock, &irqL); + _rtw_spinunlock_bh(&psta->lock); if (buf) { struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); @@ -10411,7 +10225,7 @@ void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *d rtw_mi_scan_abort(padapter, _TRUE); RTW_INFO("SAE: Tx auth Confirm\n"); - rtw_mgnt_tx_cmd(padapter, pmlmeext->cur_channel, 1, buf, len, 0, RTW_CMDF_DIRECTLY); + rtw_mgnt_tx_cmd(padapter, pmlmeext->chandef.chan, 1, buf, len, 0, RTW_CMDF_DIRECTLY); } rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX); @@ -10420,14 +10234,122 @@ void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *d buf = NULL; len = 0; } -#endif } else { /* STA mode */ psecuritypriv->extauth_status = params->status; } } -static struct cfg80211_ops rtw_cfg80211_ops = { +#ifdef CONFIG_AP_MODE +static bool rtw_ap_check_csa_setting(_adapter* a, u8 new_ch, u8 new_bw, u8 new_offset) +{ + struct dvobj_priv *d = adapter_to_dvobj(a); + struct rf_ctl_t *rfctl = adapter_to_rfctl(a); + struct mlme_ext_priv *pmlmeext = &(a->mlmeextpriv); + struct rtw_chan_def u_chdef = {0}; + u8 c_ch, c_bw, c_offset, u_ch, u_bw, u_offset; +#ifdef CONFIG_MCC_MODE + struct rtw_phl_com_t *phl_com = GET_PHL_COM(d); + u8 mcc_sup = phl_com->dev_cap.mcc_sup; +#else + u8 mcc_sup = _FALSE; +#endif + + if (rtw_phl_mr_get_chandef(d->phl, a->phl_role, &u_chdef) + != RTW_PHL_STATUS_SUCCESS) { + RTW_ERR("CSA : "FUNC_ADPT_FMT" get union chandef failed\n", FUNC_ADPT_ARG(a)); + rtw_warn_on(1); + return _FALSE; + } + + u_ch = u_chdef.chan; + u_bw = u_chdef.bw; + u_offset = u_chdef.offset; + c_ch = pmlmeext->chandef.chan; + c_bw = pmlmeext->chandef.bw; + c_offset = pmlmeext->chandef.offset; + + if (rtw_chset_search_ch(rfctl->channel_set, new_ch) < 0 + || rtw_chset_is_ch_non_ocp(rfctl->channel_set, new_ch)) { + RTW_INFO("CSA : reject, channel not legal csa_setting:%u,%u,%u\n", new_ch, new_bw, new_offset); + return _FALSE; + } + + /* Need to group with chanctx if not support MCC */ + if (mcc_sup == _FALSE && + rtw_mi_get_ld_sta_ifbmp(a) && + rtw_is_chbw_grouped(new_ch, new_bw, new_offset, u_ch, u_bw, u_offset) == _FALSE) { + RTW_INFO("CSA : reject, can't group with STA mode, csa_setting:%u,%u,%u, union:%u,%u,%u\n", + new_ch, new_bw, new_offset, u_ch, u_bw, u_offset); + return _FALSE; + } + + RTW_INFO("CSA : channel switch. %u,%u,%u ==> %u,%u,%u (union:%u,%u,%u)\n", + c_ch, c_bw, c_offset, new_ch, new_bw, new_offset, u_ch, u_bw, u_offset); + + return _TRUE; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) +static int cfg80211_rtw_channel_switch(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_csa_settings *params) +{ +#ifdef CONFIG_ECSA_PHL + _adapter *a = (_adapter *)rtw_netdev_priv(dev); + struct core_ecsa_info *ecsa_info = &(a->ecsa_info); + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_info->phl_ecsa_param); + struct rf_ctl_t *rfctl = adapter_to_rfctl(a); + u8 csa_ch = 0, csa_bw = CHANNEL_WIDTH_20, csa_offset = CHAN_OFFSET_NO_EXT; + u8 mode = 0, count = 0, ht = 0; + + if (!(CHK_MLME_STATE(a, WIFI_AP_STATE | WIFI_MESH_STATE) + && MLME_IS_ASOC(a))) { + RTW_ERR("CSA : "FUNC_ADPT_FMT" not AP/Mesh, so return -ENOTCONN\n", FUNC_ADPT_ARG(a)); + return -ENOTCONN; + } + + if (IS_UNDER_CAC(rfctl)) { + RTW_INFO("CSA : "FUNC_ADPT_FMT" is under CAC, so return -EBUSY\n", FUNC_ADPT_ARG(a)); + return -EBUSY; + } + + if (rtw_mr_is_ecsa_running(a)) { + RTW_INFO("CSA : "FUNC_ADPT_FMT" someone is switching channel, so return -EBUSY\n", FUNC_ADPT_ARG(a)); + return -EBUSY; + } + + rtw_get_chbw_from_cfg80211_chan_def(¶ms->chandef, &ht, &csa_ch, &csa_bw, &csa_offset); + + if (rtw_ap_check_csa_setting(a, csa_ch, csa_bw, csa_offset) == _FALSE) + return -EINVAL; + + mode = params->block_tx; + count = params->count; + RTW_INFO("CSA : Get from cfg80211_csa_settings, block_tx = %s, switch count = %u\n", + mode ? "True" : "Flase", count); + + SET_ECSA_STATE(a, ECSA_ST_SW_START); + ecsa_param->ecsa_type = ECSA_TYPE_AP; + ecsa_param->mode = mode; + ecsa_param->count = count; + /* ecsa_param.op_class = rfctl->op_class; */ /* TODO : ECSA */ + ecsa_param->new_chan_def.band = rtw_phl_get_band_type(csa_ch); + ecsa_param->new_chan_def.chan = csa_ch; + ecsa_param->new_chan_def.bw = csa_bw; + ecsa_param->new_chan_def.offset = csa_offset; + ecsa_param->flag = 0; + ecsa_param->delay_start_ms = 0; + + rtw_trigger_phl_ecsa_start(a); + +#endif /* CONFIG_ECSA_PHL */ + return 0; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) */ +#endif /* CONFIG_AP_MODE */ + +struct cfg80211_ops rtw_cfg80211_ops = { .change_virtual_intf = cfg80211_rtw_change_iface, .add_key = cfg80211_rtw_add_key, .get_key = cfg80211_rtw_get_key, @@ -10441,28 +10363,25 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #endif /*CONFIG_GTK_OL*/ .get_station = cfg80211_rtw_get_station, .scan = cfg80211_rtw_scan, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) && \ - defined(CONFIG_RTW_ABORT_SCAN) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) .abort_scan = cfg80211_rtw_abort_scan, -#endif +#endif /* LINUX_VERSION_CODE 4.5.0 */ .set_wiphy_params = cfg80211_rtw_set_wiphy_params, .connect = cfg80211_rtw_connect, .disconnect = cfg80211_rtw_disconnect, .join_ibss = cfg80211_rtw_join_ibss, .leave_ibss = cfg80211_rtw_leave_ibss, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) .set_tx_power = cfg80211_rtw_set_txpower, .get_tx_power = cfg80211_rtw_get_txpower, -#endif .set_power_mgmt = cfg80211_rtw_set_power_mgmt, .set_pmksa = cfg80211_rtw_set_pmksa, .del_pmksa = cfg80211_rtw_del_pmksa, .flush_pmksa = cfg80211_rtw_flush_pmksa, +#ifdef CONFIG_AP_MODE .add_virtual_intf = cfg80211_rtw_add_virtual_intf, .del_virtual_intf = cfg80211_rtw_del_virtual_intf, -#ifdef CONFIG_AP_MODE #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) .add_beacon = cfg80211_rtw_add_beacon, .set_beacon = cfg80211_rtw_set_beacon, @@ -10481,9 +10400,7 @@ static struct cfg80211_ops rtw_cfg80211_ops = { .del_station = cfg80211_rtw_del_station, .change_station = cfg80211_rtw_change_station, .dump_station = cfg80211_rtw_dump_station, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) .change_bss = cfg80211_rtw_change_bss, -#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) .set_txq_params = cfg80211_rtw_set_txq_params, #endif @@ -10519,11 +10436,12 @@ static struct cfg80211_ops rtw_cfg80211_ops = { .remain_on_channel = cfg80211_rtw_remain_on_channel, .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel, - -#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) +#ifdef CONFIG_P2P + #if defined(RTW_DEDICATED_P2P_DEVICE) .start_p2p_device = cfg80211_rtw_start_p2p_device, .stop_p2p_device = cfg80211_rtw_stop_p2p_device, -#endif + #endif +#endif /* CONFIG_P2P */ #ifdef CONFIG_RTW_80211R .update_ft_ies = cfg80211_rtw_update_ft_ies, @@ -10531,11 +10449,13 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) .mgmt_tx = cfg80211_rtw_mgmt_tx, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register, #else .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_register, #endif + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) .action = cfg80211_rtw_mgmt_tx, #endif @@ -10557,10 +10477,15 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) .dump_survey = rtw_hostapd_acs_dump_survey, #endif -#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ +#if defined(CPTCFG_VERSION) || (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \ || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH) .external_auth = cfg80211_rtw_external_auth, #endif +#ifdef CONFIG_AP_MODE +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) + .channel_switch = cfg80211_rtw_channel_switch, +#endif +#endif /* #ifdef CONFIG_AP_MODE */ }; struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) @@ -10579,11 +10504,11 @@ struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) /* wiphy_data */ wiphy_data = rtw_wiphy_priv(wiphy); wiphy_data->dvobj = adapter_to_dvobj(padapter); -#ifndef RTW_SINGLE_WIPHY - wiphy_data->adapter = padapter; -#endif - wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM; - wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM; + + /*wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;*/ + /*wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;*/ + + rtw_regd_init(wiphy); if (rtw_cfg80211_init_wiphy(padapter, wiphy) != _SUCCESS) { rtw_wiphy_free(wiphy); @@ -10604,6 +10529,8 @@ void rtw_wiphy_free(struct wiphy *wiphy) RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); + rtw_regd_deinit(wiphy); + if (wiphy->bands[NL80211_BAND_2GHZ]) { rtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]); wiphy->bands[NL80211_BAND_2GHZ] = NULL; @@ -10618,24 +10545,37 @@ void rtw_wiphy_free(struct wiphy *wiphy) int rtw_wiphy_register(struct wiphy *wiphy) { + struct get_chplan_resp *chplan; + int ret; + RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); -#if ( (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \ - || defined(RTW_VENDOR_EXT_SUPPORT) ) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) rtw_cfgvendor_attach(wiphy); #endif - rtw_regd_init(wiphy); + ret = wiphy_register(wiphy); + if (ret != 0) { + RTW_INFO(FUNC_WIPHY_FMT" wiphy_register() return %d\n", FUNC_WIPHY_ARG(wiphy), ret); + goto exit; + } + + rtw_chset_hook_os_channels(dvobj_to_rfctl(wiphy_to_dvobj(wiphy))); + + if (rtw_get_chplan_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_DIRECTLY, &chplan) == _SUCCESS) + rtw_regd_change_complete_sync(wiphy, chplan, 1); + else + rtw_warn_on(1); - return wiphy_register(wiphy); +exit: + return ret; } void rtw_wiphy_unregister(struct wiphy *wiphy) { RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); -#if ( (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \ - || defined(RTW_VENDOR_EXT_SUPPORT) ) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) rtw_cfgvendor_detach(wiphy); #endif @@ -10681,18 +10621,16 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) pwdev_priv->p2p_enabled = _FALSE; pwdev_priv->probe_resp_ie_update_time = rtw_get_current_time(); - pwdev_priv->provdisc_req_issued = _FALSE; rtw_wdev_invit_info_init(&pwdev_priv->invit_info); rtw_wdev_nego_info_init(&pwdev_priv->nego_info); - pwdev_priv->bandroid_scan = _FALSE; + if (padapter->registrypriv.power_mgnt != PM_PS_MODE_ACTIVE) + pwdev_priv->power_mgmt = _TRUE; + else + pwdev_priv->power_mgmt = _FALSE; _rtw_mutex_init(&pwdev_priv->roch_mutex); -#ifdef CONFIG_CONCURRENT_MODE - ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); -#endif - #ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR pwdev_priv->rssi_monitor_enable = 0; pwdev_priv->rssi_monitor_max = 0; @@ -10714,13 +10652,12 @@ void rtw_wdev_free(struct wireless_dev *wdev) if (wdev_to_ndev(wdev)) { _adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); - _irqL irqL; _rtw_spinlock_free(&wdev_priv->scan_req_lock); - _enter_critical_bh(&wdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_bh(&wdev_priv->connect_req_lock); rtw_wdev_free_connect_req(wdev_priv); - _exit_critical_bh(&wdev_priv->connect_req_lock, &irqL); + _rtw_spinunlock_bh(&wdev_priv->connect_req_lock); _rtw_spinlock_free(&wdev_priv->connect_req_lock); _rtw_mutex_free(&wdev_priv->roch_mutex); @@ -10750,11 +10687,7 @@ void rtw_wdev_unregister(struct wireless_dev *wdev) rtw_cfg80211_indicate_scan_done(adapter, _TRUE); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE) - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2)) - if (wdev->links[0].client.current_bss) { - #else if (wdev->current_bss) { - #endif RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter)); rtw_cfg80211_indicate_disconnect(adapter, 0, 1); } @@ -10770,29 +10703,9 @@ int rtw_cfg80211_ndev_res_alloc(_adapter *adapter) { int ret = _FAIL; -#if !defined(RTW_SINGLE_WIPHY) - struct wiphy *wiphy; - struct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter)); - - wiphy = rtw_wiphy_alloc(adapter, dev); - if (wiphy == NULL) - goto exit; - - adapter->wiphy = wiphy; -#endif - if (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0) ret = _SUCCESS; -#if !defined(RTW_SINGLE_WIPHY) - if (ret != _SUCCESS) { - rtw_wiphy_free(wiphy); - adapter->wiphy = NULL; - } - -exit: -#endif - return ret; } @@ -10800,34 +10713,11 @@ void rtw_cfg80211_ndev_res_free(_adapter *adapter) { rtw_wdev_free(adapter->rtw_wdev); adapter->rtw_wdev = NULL; -#if !defined(RTW_SINGLE_WIPHY) - rtw_wiphy_free(adapter_to_wiphy(adapter)); - adapter->wiphy = NULL; -#endif } - int rtw_cfg80211_ndev_res_register(_adapter *adapter) { -#if !defined(RTW_SINGLE_WIPHY) - int ret = _FAIL; - - if (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) { - RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1)); - goto exit; - } - - #ifdef CONFIG_RFKILL_POLL - rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter)); - #endif - - ret = _SUCCESS; - -exit: - return ret; -#else return _SUCCESS; -#endif } void rtw_cfg80211_ndev_res_unregister(_adapter *adapter) @@ -10838,8 +10728,6 @@ void rtw_cfg80211_ndev_res_unregister(_adapter *adapter) int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) { int ret = _FAIL; - -#if defined(RTW_SINGLE_WIPHY) struct wiphy *wiphy; struct device *dev = dvobj_to_dev(dvobj); @@ -10848,7 +10736,6 @@ int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) return ret; dvobj->wiphy = wiphy; -#endif ret = _SUCCESS; return ret; @@ -10856,23 +10743,19 @@ int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj) { -#if defined(RTW_SINGLE_WIPHY) rtw_wiphy_free(dvobj_to_wiphy(dvobj)); dvobj->wiphy = NULL; -#endif } int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) { int ret = _FAIL; -#if defined(RTW_SINGLE_WIPHY) if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0) return ret; #ifdef CONFIG_RFKILL_POLL rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj)); -#endif #endif ret = _SUCCESS; @@ -10882,73 +10765,10 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) { -#if defined(RTW_SINGLE_WIPHY) #ifdef CONFIG_RFKILL_POLL rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj)); #endif rtw_wiphy_unregister(dvobj_to_wiphy(dvobj)); -#endif -} - -s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj) -{ - struct rtw_wiphy_data *wiphy_data; - s16 mbm = UNSPECIFIED_MBM; - - /* TODO: input radio index to choose corresponding wiphy(s) */ - -#if defined(RTW_SINGLE_WIPHY) - wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj)); - mbm = wiphy_data->txpwr_total_lmt_mbm; -#else - struct wiphy *wiphy; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - wiphy = dvobj->padapters[i]->wiphy; - if (!wiphy) - continue; - wiphy_data = rtw_wiphy_priv(wiphy); - if (wiphy_data->txpwr_total_lmt_mbm == UNSPECIFIED_MBM) - continue; - if (mbm > wiphy_data->txpwr_total_lmt_mbm) - mbm = wiphy_data->txpwr_total_lmt_mbm; - } -#endif - - return mbm; } -s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj) -{ - struct rtw_wiphy_data *wiphy_data; - s16 mbm = UNSPECIFIED_MBM; - - /* TODO: input radio index to choose corresponding wiphy(s) */ - -#if defined(RTW_SINGLE_WIPHY) - wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj)); - mbm = wiphy_data->txpwr_total_target_mbm; -#else - struct wiphy *wiphy; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - wiphy = dvobj->padapters[i]->wiphy; - if (!wiphy) - continue; - wiphy_data = rtw_wiphy_priv(wiphy); - if (wiphy_data->txpwr_total_target_mbm == UNSPECIFIED_MBM) - continue; - if (mbm > wiphy_data->txpwr_total_target_mbm) - mbm = wiphy_data->txpwr_total_target_mbm; - } -#endif - - return mbm; -} #endif /* CONFIG_IOCTL_CFG80211 */ diff --git a/os_dep/linux/ioctl_cfg80211.h b/os_dep/linux/ioctl_cfg80211.h index 7c50e32..b5422cb 100644 --- a/os_dep/linux/ioctl_cfg80211.h +++ b/os_dep/linux/ioctl_cfg80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -45,17 +45,42 @@ #ifndef CONFIG_RTW_DYNAMIC_NDEV #define CONFIG_RTW_DYNAMIC_NDEV #endif - #ifndef RTW_SINGLE_WIPHY - #define RTW_SINGLE_WIPHY - #endif + #ifndef CONFIG_RADIO_WORK #define CONFIG_RADIO_WORK #endif - #ifndef RTW_DEDICATED_P2P_DEVICE - #define RTW_DEDICATED_P2P_DEVICE +#endif + +#ifdef CONFIG_RTW_DYNAMIC_NDEV + #ifdef RTW_DEDICATED_P2P_DEVICE + #ifdef CONFIG_RTW_STATIC_NDEV_NUM + #undef CONFIG_RTW_STATIC_NDEV_NUM + #endif + #endif + + #ifndef CONFIG_RTW_STATIC_NDEV_NUM + #define CONFIG_RTW_STATIC_NDEV_NUM 1 + #endif +#else + #ifdef CONFIG_RTW_STATIC_NDEV_NUM + #undef CONFIG_RTW_STATIC_NDEV_NUM #endif #endif +#ifndef CONFIG_RTW_STATIC_NDEV_NUM + #define CONFIG_RTW_STATIC_NDEV_NUM CONFIG_IFACE_NUMBER +#endif + +#if !((CONFIG_RTW_STATIC_NDEV_NUM > 0) && \ + (CONFIG_RTW_STATIC_NDEV_NUM <= CONFIG_IFACE_NUMBER)) + #error "CONFIG_RTW_STATIC_NDEV_NUM our of range" +#endif + +#if defined(CONFIG_P2P) && defined(CONFIG_SEL_P2P_IFACE) && \ + !((CONFIG_SEL_P2P_IFACE >= 0) && (CONFIG_SEL_P2P_IFACE < CONFIG_RTW_STATIC_NDEV_NUM)) + #error "CONFIG_SEL_P2P_IFACE our of range" +#endif + #ifndef CONFIG_RADIO_WORK #define RTW_ROCH_DURATION_ENLARGE #define RTW_ROCH_BACK_OP @@ -65,6 +90,15 @@ #error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n" #endif +#ifdef CONFIG_SEL_P2P_IFACE + #if RTW_P2P_GROUP_INTERFACE + #error "CONFIG_SEL_P2P_IFACE has no effect when RTW_P2P_GROUP_INTERFACE is enabled" + #endif + #ifdef RTW_USE_CFG80211_REPORT_PROBE_REQ + #error "CONFIG_SEL_P2P_IFACE has no effect when RTW_USE_CFG80211_REPORT_PROBE_REQ is enabled" + #endif +#endif + #if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE) #error "RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\n" #endif @@ -158,14 +192,12 @@ struct rtw_wdev_priv { u8 p2p_enabled; systime probe_resp_ie_update_time; - u8 provdisc_req_issued; - struct rtw_wdev_invit_info invit_info; struct rtw_wdev_nego_info nego_info; - u8 bandroid_scan; bool block; bool block_scan; + bool power_mgmt; /** * mgmt_regs: bitmap of management frame subtypes registered for the @@ -181,11 +213,7 @@ struct rtw_wdev_priv { _mutex roch_mutex; -#ifdef CONFIG_CONCURRENT_MODE - ATOMIC_T switch_ch_to; -#endif - -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI u8 pno_mac_addr[ETH_ALEN]; u16 pno_scan_seq_num; #endif @@ -237,25 +265,19 @@ bool rtw_cfg80211_is_connect_requested(_adapter *adapter); struct rtw_wiphy_data { struct dvobj_priv *dvobj; -#ifndef RTW_SINGLE_WIPHY - _adapter *adapter; -#endif - #if defined(RTW_DEDICATED_P2P_DEVICE) struct wireless_dev *pd_wdev; /* P2P device wdev */ #endif - s16 txpwr_total_lmt_mbm; /* EIRP */ - s16 txpwr_total_target_mbm; /* EIRP */ + _list async_regd_change_list; + _mutex async_regd_change_mutex; + _workitem async_regd_change_work; }; #define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy)) #define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj) -#ifdef RTW_SINGLE_WIPHY #define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy))) -#else -#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter) -#endif + #if defined(RTW_DEDICATED_P2P_DEVICE) #define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev) @@ -294,10 +316,6 @@ int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj); void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj); int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj); void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj); -s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj); -s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj); - -void rtw_cfg80211_init_wdev_data(_adapter *padapter); void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork); void rtw_cfg80211_surveydone_event_callback(_adapter *padapter); @@ -317,7 +335,6 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab #ifdef CONFIG_AP_MODE void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason); -int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); #endif /* CONFIG_AP_MODE */ void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val); @@ -337,12 +354,11 @@ void rtw_pd_iface_free(struct wiphy *wiphy); #endif #endif /* CONFIG_P2P */ + void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val); u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter); u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf); -void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); - void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg); @@ -353,6 +369,8 @@ void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rf void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev, struct rtw_external_auth_params *params); +int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); + bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #ifdef CONFIG_RTW_80211K void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe); @@ -429,7 +447,7 @@ u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 #define IEEE80211_CHAN_NO_HT40MINUS IEEE80211_CHAN_NO_FAT_BELOW #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)) +#if !defined(CPTCFG_VERSION) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)) #define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ #define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) @@ -438,15 +456,11 @@ u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 #define NUM_NL80211_BANDS IEEE80211_NUM_BANDS #endif -#define rtw_band_to_nl80211_band(band) \ - (band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \ - (band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS +extern enum nl80211_band _rtw_band_to_nl80211_band[]; +#define rtw_band_to_nl80211_band(band) (((band) < BAND_MAX) ? _rtw_band_to_nl80211_band[(band)] : NUM_NL80211_BANDS) -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)) -#define NL80211_TX_POWER_AUTOMATIC TX_POWER_AUTOMATIC -#define NL80211_TX_POWER_LIMITED TX_POWER_LIMITED -#define NL80211_TX_POWER_FIXED TX_POWER_FIXED -#endif +extern enum band_type _nl80211_band_to_rtw_band[]; +#define nl80211_band_to_rtw_band(band) (((band) < NUM_NL80211_BANDS) ? _nl80211_band_to_rtw_band[(band)] : BAND_MAX) #include "wifi_regd.h" #include "rtw_cfgvendor.h" diff --git a/os_dep/linux/ioctl_efuse.c b/os_dep/linux/ioctl_efuse.c new file mode 100644 index 0000000..7e31ab6 --- /dev/null +++ b/os_dep/linux/ioctl_efuse.c @@ -0,0 +1,1538 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#if defined(CONFIG_MP_INCLUDED) +#include + +void rtw_efuse_cmd(_adapter *padapter, + struct rtw_efuse_phl_arg *pefuse_arg , + enum rtw_efuse_phl_cmdid cmdid) +{ + u32 i = 0; + pefuse_arg->mp_class = RTW_MP_CLASS_EFUSE; + pefuse_arg->cmd = cmdid; + pefuse_arg->cmd_ok = 0; + + rtw_mp_set_phl_cmd(padapter, (void*)pefuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + while (i <= 10) { + rtw_msleep_os(50); + rtw_mp_get_phl_cmd(padapter, (void*)pefuse_arg, sizeof(struct rtw_efuse_phl_arg)); + if (pefuse_arg->cmd_ok && pefuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + RTW_INFO("%s,eFuse GET CMD OK !!!\n", __func__); + break; + } else { + rtw_msleep_os(10); + if (i > 10) { + RTW_INFO("%s, eFuse GET CMD FAIL !!!\n", __func__); + break; + } + i++; + } + } +} + +u32 rtw_efuse_get_map_size(_adapter *padapter , u16 *size , enum rtw_efuse_phl_cmdid cmdid) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + rtw_efuse_cmd(padapter, efuse_arg, cmdid); + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + *size = efuse_arg->io_value; + res = _SUCCESS; + } else { + *size = 0; + res = _FAIL; + } + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +u32 rtw_efuse_get_available_size(_adapter *padapter , u16 *size, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_WIFI_GET_AVL_SIZE); + else + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_GET_AVL_SIZE); + + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + *size = efuse_arg->io_value; + res = _SUCCESS; + } else { + *size = 0; + res = _FAIL; + } + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +static u8 rtw_efuse_fake2map(_adapter *padapter, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _SUCCESS; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_WIFI_UPDATE); + else if (efuse_type == RTW_EFUSE_BT) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_UPDATE); + + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + else + res = _FAIL; + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +static u8 rtw_efuse_read_map2shadow(_adapter *padapter, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _SUCCESS; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_WIFI_UPDATE_MAP); + else if (efuse_type == RTW_EFUSE_BT) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_UPDATE_MAP); + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + else + res = _FAIL; + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +static u8 rtw_efuse_get_shadow_map(_adapter *padapter, u8 *map, u16 size, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + + efuse_arg->buf_len = size; + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_SHADOW_MAP2BUF); + else if (efuse_type == RTW_EFUSE_BT) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_SHADOW_MAP2BUF); + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + _rtw_memcpy((void *)map, efuse_arg->poutbuf, size); + res = _SUCCESS; + } else + res = _FAIL; + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +static u8 rtw_efuse_renew_update(_adapter *padapter, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _SUCCESS; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_MP_EFUSE_CMD_WIFI_SET_RENEW); + else if (efuse_type == RTW_EFUSE_BT) + RTW_INFO("halmac_get_logical_efuse_size fail\n"); + + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + else + res = _FAIL; + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + + +u8 rtw_efuse_map_read(_adapter * adapter, u16 addr, u16 cnts, u8 *data, u8 efuse_type) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u16 size, i; + int err = _FAIL; + u8 status = _SUCCESS; + + if (efuse_type == RTW_EFUSE_WIFI) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + else if (efuse_type == RTW_EFUSE_BT) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + + if (err == _FAIL) { + status = _FAIL; + RTW_INFO("halmac_get_logical_efuse_size fail\n"); + goto exit; + } + /* size error handle */ + if ((addr + cnts) > size) { + if (addr < size) + cnts = size - addr; + else { + status = _FAIL; + RTW_INFO(" %s() ,addr + cnts) > size fail\n", __func__); + goto exit; + } + } + + efuse = rtw_zmalloc(size); + if (efuse) { + if (rtw_efuse_read_map2shadow(adapter, efuse_type) == _SUCCESS) { + err = rtw_efuse_get_shadow_map(adapter, efuse, size, efuse_type); + if (err == _FAIL) { + rtw_mfree(efuse, size); + status = _FAIL; + RTW_INFO(" %s() ,halmac_read_logical_efus map fail\n", __func__); + goto exit; + } + } else { + RTW_INFO(" %s() ,rtw_efuse_read_map2shadow FAIL !!!\n", __func__); + rtw_mfree(efuse, size); + status = _FAIL; + goto exit; + } + if (efuse) { + RTW_INFO(" %s() ,cp efuse to data\n", __func__); + _rtw_memcpy(data, efuse + addr, cnts); + rtw_mfree(efuse, size); + } + } else { + RTW_INFO(" %s() ,alloc efuse fail\n", __func__); + goto exit; + } + status = _SUCCESS; +exit: + + return status; +} + +u8 rtw_efuse_map_write(_adapter * adapter, u16 addr, u16 cnts, u8 *data, u8 efuse_type, u8 bpg) +{ + struct dvobj_priv *d; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u16 size; + int err = _FAIL; + u8 mask_buf[64] = ""; + u32 backupRegs[4] = {0}; + u8 status = _SUCCESS; + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u16 i = 0; + + efuse_arg = rtw_zmalloc(sizeof(struct rtw_efuse_phl_arg)); + + if (efuse_type == RTW_EFUSE_WIFI) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + else if (efuse_type == RTW_EFUSE_BT) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + + if (err == _FAIL) { + status = _FAIL; + goto exit; + } + + if ((addr + cnts) > size) { + status = _FAIL; + goto exit; + } + + if (efuse_type == RTW_EFUSE_WIFI) { + while (i != cnts) { + efuse_arg->io_type = 1; + efuse_arg->io_offset = addr + i; + efuse_arg->io_value = data[i]; + rtw_efuse_cmd(adapter, efuse_arg, RTW_EFUSE_CMD_WIFI_WRITE); + if (i > cnts) + break; + i++; + } + } else if (efuse_type == RTW_EFUSE_BT) { + while (i != cnts) { + efuse_arg->io_type = 1; + efuse_arg->io_offset = addr + i; + efuse_arg->io_value = data[i]; + rtw_efuse_cmd(adapter, efuse_arg, RTW_EFUSE_CMD_BT_WRITE); + if (i > cnts) + break; + i++; + } + } + + if (bpg) { + RTW_INFO(" in PG state !!!\n"); + if (efuse_type == RTW_EFUSE_WIFI) + err = rtw_efuse_fake2map(adapter, efuse_type); + else if (efuse_type == RTW_EFUSE_BT) { + u8 reg2chkbt = 0; + + rtw_phl_write8(dvobj->phl, 0xa3, 0x05); + rtw_msleep_os(10); + reg2chkbt = rtw_phl_read8(dvobj->phl, 0xa0); + + if (reg2chkbt != 0x04) { + RTW_ERR("BT State not Active:0x%x ,can't Write \n", reg2chkbt); + goto exit; + } + + err = rtw_efuse_fake2map(adapter, efuse_type); + } + + if (err == _FAIL) { + status = _FAIL; + goto exit; + } + } + status = _SUCCESS; +exit : + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return status; +} + +static u8 rtw_efuse_map_file_load(_adapter *padapter, u8 *filepath, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + if (filepath) { + RTW_INFO("efuse file path %s len %zu", filepath, strlen(filepath)); + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + _rtw_memcpy(efuse_arg->pfile_path, filepath, strlen(filepath)); + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_FILE_MAP_LOAD); + else + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_FILE_MAP_LOAD); + } + } + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + else + res = _FAIL; + + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +static u8 rtw_efuse_mask_file_load(_adapter *padapter, u8 *filepath, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + if (filepath) { + RTW_INFO("efuse file path %s len %zu", filepath, strlen(filepath)); + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, 0, sizeof(struct rtw_efuse_phl_arg)); + _rtw_memcpy(efuse_arg->pfile_path, filepath, strlen(filepath)); + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_FILE_MASK_LOAD); + else + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_FILE_MASK_LOAD); + } + } + + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + res = _SUCCESS; + else + res = _FAIL; + + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +int rtw_ioctl_efuse_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; + u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0; + int err = 0; + char *pextra = NULL; + u8 *pre_efuse_map = NULL; + u16 max_available_len = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) { + err = -EFAULT; + goto exit; + } + + *(extra + wrqu->data.length) = '\0'; + pch = extra; + RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + /* mac 16 "00e04c871200" rmap,00,2 */ + while ((token = strsep(&pch, ",")) != NULL) { + if (i > 2) + break; + tmp[i] = token; + i++; + } + pre_efuse_map = rtw_zmalloc(RTW_MAX_EFUSE_MAP_LEN); + if (pre_efuse_map == NULL) + goto exit; + + if (strcmp(tmp[0], "status") == 0) { + //sprintf(extra, "Load File efuse=%s,Load File MAC=%s" + // , efuse->file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" + // , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" + // ); + goto exit; + } else if (strcmp(tmp[0], "drvmap") == 0) { + static u8 drvmaporder = 0; + u8 *efuse_data = NULL; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + //EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); + + //efuse_data = efuse->data; + + shift = blksz * drvmaporder; + efuse_data += shift; + cnt = mapLen - shift; + + if (cnt > blksz) { + cnt = blksz; + drvmaporder++; + } else + drvmaporder = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\n"); + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); + + } else if (strcmp(tmp[0], "realmap") == 0) { + static u8 order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *efuse_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_map_read(padapter, 0, mapLen, pre_efuse_map, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + efuse_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * order; + efuse_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + order++; + } else + order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else if (strcmp(tmp[0], "rmap") == 0) { + u8 *data = NULL; + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + + if ((addr + cnts) > mapLen) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) over mapLen %d parameter error!\n", __FUNCTION__, addr, cnts, mapLen); + err = -EINVAL; + goto exit; + } + + if (pre_efuse_map) { + if (rtw_efuse_map_read(padapter, addr, cnts, pre_efuse_map, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + data = pre_efuse_map; + *extra = 0; + pextra = extra; + for (i = 0; i < cnts; i++) { + pextra += sprintf(pextra, "0x%02X ", data[i]); + } + } + } + } else if (strcmp(tmp[0], "wlrfkmap") == 0) { + static u8 order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *efuse_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_get_shadow_map(padapter, pre_efuse_map, mapLen, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: read wifi fake map Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + efuse_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * order; + efuse_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + order++; + } else + order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else if (strcmp(tmp[0], "wlrfkrmap") == 0) { + u8 *data = NULL; + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + + if ((addr + cnts) > mapLen) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) over mapLen %d parameter error!\n", __FUNCTION__, addr, cnts, mapLen); + err = -EINVAL; + goto exit; + } + + if (pre_efuse_map) { + if (rtw_efuse_get_shadow_map(padapter, pre_efuse_map, mapLen, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: read wifi fake map Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + data = pre_efuse_map; + *extra = 0; + pextra = extra; + for (i = addr; i < addr + cnts; i++) + pextra += sprintf(pextra, "0x%02X ", data[i]); + } + } + } else if (strcmp(tmp[0], "btrealmap") == 0) { + static u8 order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *efuse_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_map_read(padapter, 0, mapLen, pre_efuse_map, RTW_EFUSE_BT) == _FAIL) { + RTW_INFO("%s: read BT realmap Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + efuse_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * order; + efuse_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + order++; + } else + order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else if (strcmp(tmp[0], "btrmap") == 0) { + u8 *data = NULL; + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: btrmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + + if ((addr + cnts) > mapLen) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) over mapLen %d parameter error!\n", __FUNCTION__, addr, cnts, mapLen); + err = -EINVAL; + goto exit; + } + + if (pre_efuse_map) { + if (rtw_efuse_map_read(padapter, addr, cnts, pre_efuse_map, RTW_EFUSE_BT) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + data = pre_efuse_map; + *extra = 0; + pextra = extra; + for (i = 0; i < cnts; i++) + pextra += sprintf(pextra, "0x%02X ", data[i]); + } + } + } else if (strcmp(tmp[0], "btrfkmap") == 0) { + static u8 order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *efuse_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_get_shadow_map(padapter, pre_efuse_map, mapLen, RTW_EFUSE_BT) == _FAIL) { + RTW_INFO("%s: read BT fake map Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + efuse_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * order; + efuse_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + order++; + } else + order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else if (strcmp(tmp[0], "ableraw") == 0) { + rtw_efuse_get_available_size(padapter, &max_available_len, RTW_EFUSE_WIFI); + sprintf(extra, "[WIFI available raw size]= %d bytes\n", max_available_len); + } else if (strcmp(tmp[0], "btableraw") == 0) { + rtw_efuse_get_available_size(padapter, &max_available_len, RTW_EFUSE_BT); + sprintf(extra, "[BT available raw size]= %d bytes\n", max_available_len); + } else if (strcmp(tmp[0], "realraw") == 0) { + static u8 raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *realraw_map_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_WIFI_GET_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_raw_map_read (padapter, 0, mapLen, pre_efuse_map, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: read wifi raw map Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + realraw_map_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * raw_order; + realraw_map_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + raw_order++; + } else + raw_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", realraw_map_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", realraw_map_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else if (strcmp(tmp[0], "btrealraw")== 0) { + static u8 raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + u8 *realraw_map_data = NULL; + + rtw_efuse_get_map_size(padapter, &mapLen, RTW_EFUSE_CMD_BT_GET_SIZE); + + if (pre_efuse_map) { + if (rtw_efuse_raw_map_read (padapter, 0, mapLen, pre_efuse_map, RTW_EFUSE_BT) == _FAIL) { + RTW_INFO("%s: read bt raw map Fail!!\n", __FUNCTION__); + err = -EFAULT; + } else { + realraw_map_data = pre_efuse_map; + + _rtw_memset(extra, '\0', strlen(extra)); + shift = blksz * raw_order; + realraw_map_data += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + raw_order++; + } else + raw_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", realraw_map_data[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", realraw_map_data[i + j]); + pextra += sprintf(pextra, "\n"); + + if (strlen(extra) > 0x7FF) + break; + } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen - (shift + cnt), mapLen); + } + } + } else + sprintf(extra, "Command not found!"); + +exit: + if (pre_efuse_map) + rtw_mfree(pre_efuse_map, RTW_MAX_EFUSE_MAP_LEN); + if (!err) + wrqu->data.length = strlen(extra); + RTW_INFO("%s: strlen(extra) =%zu\n", __FUNCTION__, strlen(extra)); + if (copy_to_user(wrqu->data.pointer, extra, wrqu->data.length)) + err = -EFAULT; + + return err; +} + + +int rtw_ioctl_efuse_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu; + struct pwrctrl_priv *pwrctrlpriv ; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + u8 ips_mode = IPS_NUM; /* init invalid value */ + u8 lps_mode = PM_PS_MODE_NUM; /* init invalid value */ + u32 i = 0, j = 0, jj = 0, kk = 0; + u8 *setdata = NULL; + u8 *shadowmap = NULL; + u8 *setrawdata = NULL; + char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; + u16 addr = 0xFF, cnts = 0, max_available_len = 0; + u16 wifimaplen; + int err = 0; + boolean bcmpchk = _TRUE; + u8 status = _SUCCESS; + u16 size; + u8 bpg = true; + + wrqu = (struct iw_point *)wdata; + pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + *(extra + wrqu->length) = '\0'; + + setdata = rtw_zmalloc(RTW_MAX_EFUSE_MAP_LEN); + if (setdata == NULL) { + err = -ENOMEM; + goto exit; + } + +#ifdef CONFIG_LPS + lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ + rtw_pm_set_lps(padapter, PM_PS_MODE_ACTIVE); +#endif + +#ifdef CONFIG_IPS + ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ + rtw_pm_set_ips(padapter, IPS_NONE); +#endif + + pch = extra; + RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + while ((token = strsep(&pch, ",")) != NULL) { + if (i > 2) + break; + tmp[i] = token; + i++; + } + + /* tmp[0],[1],[2] */ + /* wmap,addr,00e04c871200 */ + if ((strcmp(tmp[0], "wmap") == 0) || (strcmp(tmp[0], "wlwfake") == 0)) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + + err = rtw_efuse_get_map_size(padapter, &size, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + max_available_len = size; + + if (err == _FAIL) { + status = _FAIL; + goto exit; + } + + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (strcmp(tmp[0], "wlwfake") == 0) + bpg = false; + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata, RTW_EFUSE_WIFI, bpg) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + *extra = 0; + if (bpg) { + RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__); + shadowmap = rtw_zmalloc(size); + if (shadowmap == NULL) { + RTW_INFO("%s: ShadowMapWiFi rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + if (rtw_efuse_get_shadow_map(padapter, shadowmap, size,RTW_EFUSE_WIFI) == _SUCCESS) { + if (_rtw_memcmp((void *)shadowmap + addr , (void *)setdata, cnts)) { + RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } else { + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "shadowmap :", shadowmap + addr, cnts); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "map_pged :", setdata, cnts); + sprintf(extra, "WiFi write map compare FAIL\n"); + RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } + } + } else { + sprintf(extra, "WiFi write fake map OK\n"); + RTW_INFO("%s: WiFi write fake map OK\n", __FUNCTION__); + err = 0; + goto exit; + } + } else if ((strcmp(tmp[0], "btwmap") == 0) || (strcmp(tmp[0], "btwfake") == 0)) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + + err = rtw_efuse_get_map_size(padapter, &size, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + max_available_len = size; + + if (err == _FAIL) { + status = _FAIL; + goto exit; + } + + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (strcmp(tmp[0], "btwfake") == 0) + bpg = false; + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata, RTW_EFUSE_BT, bpg) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + *extra = 0; + RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__); + if (bpg) { + shadowmap = rtw_zmalloc(size); + if (shadowmap == NULL) { + RTW_INFO("%s: shadowmap rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + if (rtw_efuse_get_shadow_map(padapter, shadowmap, size,RTW_EFUSE_BT) == _SUCCESS) { + if (_rtw_memcmp((void *)shadowmap + addr , (void *)setdata, cnts)) { + RTW_INFO("%s: BT write map afterf compare success\n", __func__); + sprintf(extra, "BT write map compare OK\n"); + err = 0; + goto exit; + } else { + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "shadowmap :", shadowmap, cnts); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "map_pged :", setdata, cnts); + sprintf(extra, "BT write map compare FAIL\n"); + RTW_INFO("%s: BT write map compare Fail\n", __func__); + err = 0; + goto exit; + } + } + } else { + sprintf(extra, "BT write fake map OK\n"); + RTW_INFO("%s: BT write fake map OK\n", __FUNCTION__); + err = 0; + goto exit; + } + } else if (strcmp(tmp[0], "btwraw") == 0) { + u8 reg2chkbt = 0; + + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]); + + rtw_phl_write8(dvobj->phl, 0xa3, 0x05); + rtw_msleep_os(10); + reg2chkbt = rtw_phl_read8(dvobj->phl, 0xa0); + RTW_INFO("%s: btfk2map before read 0xa0 BT Status =0x%x\n", __func__, + rtw_phl_read32(dvobj->phl, 0xa0)); + + if (reg2chkbt != 0x04) { + sprintf(extra, "Error ! BT State not Active:0x%x ,can't Write \n" , reg2chkbt); + goto exit; + } + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + + if (rtw_efuse_bt_write_raw_hidden(padapter, addr, cnts, setdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_bt_write_hidden error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } else if (strcmp(tmp[0], "wlfk2map") == 0) { + u16 mapsize = 0; + u8 *map_pged = NULL; + + RTW_INFO("%s:do rtw_efuse_fake2map\n", __func__); + rtw_efuse_get_map_size(padapter, &mapsize, RTW_EFUSE_CMD_WIFI_GET_LOG_SIZE); + shadowmap = rtw_zmalloc(mapsize); + if (shadowmap == NULL) { + RTW_INFO("%s: shadowmap rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + if (rtw_efuse_get_shadow_map(padapter, shadowmap, mapsize, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s:rtw_efuse_get_shadow_map Fail\n", __func__); + err = 0; + goto exit; + } + + status = rtw_efuse_fake2map(padapter, RTW_EFUSE_WIFI); + if (status == _SUCCESS) + RTW_INFO("WIFI write map OK\n"); + else + RTW_INFO("WIFI write map FAIL\n"); + + map_pged = rtw_zmalloc(mapsize); + if (map_pged == NULL) { + RTW_INFO("%s: map_pged rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + if (rtw_efuse_map_read(padapter, 0x00, mapsize, map_pged, RTW_EFUSE_WIFI) == _SUCCESS) { + if (_rtw_memcmp((void *)map_pged , (void *)shadowmap, mapsize)) { + RTW_INFO("%s: WiFi write map afterf compare success\n", __func__); + sprintf(extra, "WiFi write map compare OK\n"); + } else { + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "shadowmap :", shadowmap, mapsize); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "map_pged :", map_pged, mapsize); + sprintf(extra, "WiFi write map compare FAIL\n"); + RTW_INFO("%s: WiFi write map compare Fail\n", __func__); + } + } + + if (map_pged) + rtw_mfree(map_pged, mapsize); + err = 0; + goto exit; + } else if (strcmp(tmp[0], "btfk2map") == 0) { + u8 reg2chkbt = 0; + u16 mapsize = 0; + u8 *map_pged = NULL; + + RTW_INFO("%s:do rtw_efuse_fake2map\n", __func__); + rtw_efuse_get_map_size(padapter, &mapsize, RTW_EFUSE_CMD_BT_GET_LOG_SIZE); + shadowmap = rtw_zmalloc(mapsize); + if (shadowmap == NULL) { + RTW_INFO("%s: shadowmap rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + if (rtw_efuse_get_shadow_map(padapter, shadowmap, mapsize, RTW_EFUSE_BT) == _FAIL) { + RTW_INFO("%s:rtw_efuse_get_shadow_map Fail\n", __func__); + err = 0; + goto exit; + } + + rtw_phl_write8(dvobj->phl, 0xa3, 0x05); + rtw_msleep_os(10); + reg2chkbt = rtw_phl_read8(dvobj->phl, 0xa0); + RTW_INFO("%s: btfk2map before read 0xa0 BT Status =0x%x\n", __func__, + rtw_phl_read32(dvobj->phl, 0xa0)); + + if (reg2chkbt != 0x04) { + sprintf(extra, "Error ! BT State not Active:0x%x ,can't Write \n" , reg2chkbt); + goto exit; + } + + status = rtw_efuse_fake2map(padapter, RTW_EFUSE_BT); + if (status == _SUCCESS) + RTW_INFO("BT write map OK\n"); + else + RTW_INFO("BT write map FAIL\n"); + + map_pged = rtw_zmalloc(mapsize); + if (map_pged == NULL) { + RTW_INFO("%s: map_pged rtw_zmalloc Fail\n", __func__); + err = 0; + goto exit; + } + + if (rtw_efuse_map_read(padapter, 0x00, mapsize, map_pged, RTW_EFUSE_BT) == _SUCCESS) { + if (_rtw_memcmp((void *)map_pged , (void *)shadowmap, mapsize)) { + RTW_INFO("%s: BT write map afterf compare success\n", __func__); + sprintf(extra, "BT write map compare OK\n"); + } else { + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "shadowmap :", shadowmap, mapsize); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "map_pged :", map_pged, mapsize); + sprintf(extra, "BT write map compare FAIL\n"); + RTW_INFO("%s: BT write map compare Fail\n", __func__); + } + } + + if (map_pged) + rtw_mfree(map_pged, mapsize); + + err = 0; + goto exit; + } else if (strcmp(tmp[0], "update") == 0) { + if (rtw_efuse_renew_update(padapter, RTW_EFUSE_WIFI) == _FAIL) { + RTW_INFO("%s: rtw_efuse_renew_update error!!\n", __FUNCTION__); + sprintf(extra, "WIFI update FAIL\n"); + err = -EFAULT; + goto exit; + } else + sprintf(extra, "WIFI update OK\n"); + + } +exit: + if (setdata) + rtw_mfree(setdata, RTW_MAX_EFUSE_MAP_LEN); + if (shadowmap) + rtw_mfree(shadowmap, size); + + wrqu->length = strlen(extra); + + if (padapter->registrypriv.mp_mode == 0) { +#ifdef CONFIG_IPS + rtw_pm_set_ips(padapter, ips_mode); +#endif /* CONFIG_IPS */ + +#ifdef CONFIG_LPS + rtw_pm_set_lps(padapter, lps_mode); +#endif /* CONFIG_LPS */ + } + + return err; +} + +int rtw_ioctl_efuse_file_map_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status = 0; + _adapter *padapter= rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_map_file_load(padapter, rtw_efuse_file_map_path, RTW_EFUSE_WIFI); + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; + sprintf(extra, "efuse Map file file_read OK\n"); + } else { + pmp_priv->bloadefusemap = _FALSE; + sprintf(extra, "efuse Map file file_read FAIL\n"); + } + } else { + sprintf(extra, "efuse file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_ioctl_efuse_file_mask_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status = 0; + _adapter *padapter= rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_mask_file_load(padapter, rtw_efuse_file_map_path, RTW_EFUSE_WIFI); + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; + sprintf(extra, "efuse Mask file file_read OK\n"); + } else { + pmp_priv->bloadefusemap = _FALSE; + sprintf(extra, "efuse Mask file file_read FAIL\n"); + } + } else { + sprintf(extra, "efuse file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + + wrqu->data.length = strlen(extra); + return 0; +} + + +int rtw_ioctl_efuse_bt_file_map_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status = 0; + _adapter *padapter= rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s BT do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_map_file_load(padapter, rtw_efuse_file_map_path, RTW_EFUSE_BT); + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; + sprintf(extra, "BT efuse Map file file_read OK\n"); + } else { + pmp_priv->bloadefusemap = _FALSE; + sprintf(extra, "BT efuse Map file file_read FAIL\n"); + } + } else { + sprintf(extra, "BT efuse file readable FAIL\n"); + RTW_INFO("%s BT rtw_is_file_readable fail!\n", __func__); + } + + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_ioctl_efuse_bt_file_mask_load(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status = 0; + _adapter *padapter= rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s BT mask do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_mask_file_load(padapter, rtw_efuse_file_map_path, RTW_EFUSE_BT); + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; + sprintf(extra, "BT efuse Mask file file_read OK\n"); + } else { + pmp_priv->bloadefusemap = _FALSE; + sprintf(extra, "BT efuse Mask file file_read FAIL\n"); + } + } else { + sprintf(extra, "BT efuse file readable FAIL\n"); + RTW_INFO("%s BT rtw_is_file_readable fail!\n", __func__); + } + + wrqu->data.length = strlen(extra); + return 0; +} + +s8 rtw_efuse_get_map_from(_adapter *padapter) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 map_status = -1; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + _rtw_memset((void *)efuse_arg, + 0, + sizeof(struct rtw_efuse_phl_arg)); + rtw_efuse_cmd(padapter, + efuse_arg, + RTW_MP_EFUSE_CMD_WIFI_GET_MAP_FROM); + + if (efuse_arg->cmd_ok && + efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + map_status = efuse_arg->io_value; + RTW_INFO("%s: OK value:%d\n", + __func__, map_status); + } else { + map_status = -1; + RTW_INFO("%s: fail !\n", __func__); + } + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return map_status; +} + +static u8 rtw_efuse_get_realraw(_adapter *padapter, u8 *map, u16 addr, u16 size, u8 efuse_type) +{ + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u8 res = _FAIL; + + efuse_arg = _rtw_malloc(sizeof(struct rtw_efuse_phl_arg)); + if (efuse_arg) { + efuse_arg->io_offset = addr; + efuse_arg->buf_len = size; + if (efuse_type == RTW_EFUSE_WIFI) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_WIFI_GET_PHY_MAP); + else if (efuse_type == RTW_EFUSE_BT) + rtw_efuse_cmd(padapter, efuse_arg, RTW_EFUSE_CMD_BT_GET_PHY_MAP); + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { + _rtw_memcpy((void *)map, efuse_arg->poutbuf, size); + res = _SUCCESS; + } else + res = _FAIL; + } + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return res; +} + +u8 rtw_efuse_raw_map_read(_adapter * adapter, u16 addr, u16 cnts, u8 *data, u8 efuse_type) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u16 size, i; + int err = _FAIL; + u8 status = _SUCCESS; + + if (efuse_type == RTW_EFUSE_WIFI) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_WIFI_GET_SIZE); + else if (efuse_type == RTW_EFUSE_BT) + err = rtw_efuse_get_map_size(adapter, &size, RTW_EFUSE_CMD_BT_GET_SIZE); + + if (err == _FAIL) { + status = _FAIL; + RTW_INFO("get_efuse_size fail\n"); + goto exit; + } + /* size error handle */ + if ((addr + cnts) > size) { + if (addr < size) + cnts = size - addr; + else { + status = _FAIL; + RTW_INFO(" %s() ,addr + cnts) > size fail\n", __func__); + goto exit; + } + } + + efuse = rtw_zmalloc(size); + if (efuse) { + err = rtw_efuse_get_realraw (adapter, efuse, addr, size, efuse_type); + if (err == _FAIL) { + rtw_mfree(efuse, size); + status = _FAIL; + RTW_INFO(" %s() , phl get realraw fail\n", __func__); + goto exit; + } + if (efuse) { + RTW_INFO(" %s() ,cp efuse to data\n", __func__); + _rtw_memcpy(data, efuse + addr, cnts); + rtw_mfree(efuse, size); + } + } else { + RTW_INFO(" %s() ,alloc efuse fail\n", __func__); + goto exit; + } + status = _SUCCESS; +exit: + + return status; +} + +u8 rtw_efuse_bt_write_raw_hidden(_adapter * adapter, u16 addr, u16 cnts, u8 *data) +{ + u8 status = _SUCCESS; + struct rtw_efuse_phl_arg *efuse_arg = NULL; + u16 i = 0; + + efuse_arg = _rtw_zmalloc(sizeof(struct rtw_efuse_phl_arg)); + + while (i < cnts) { + efuse_arg->io_type = 1; + efuse_arg->io_offset = addr + i; + efuse_arg->io_value = data[i]; + rtw_efuse_cmd(adapter, efuse_arg, RTW_EFUSE_CMD_BT_WRITE_HIDDEN); + if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) + status = _SUCCESS; + else{ + status = _FAIL; + break; + } + i++; + } +exit : + if (efuse_arg) + _rtw_mfree(efuse_arg, sizeof(struct rtw_efuse_phl_arg)); + + return status; +} + +#endif /*#if defined(CONFIG_MP_INCLUDED)*/ + diff --git a/os_dep/linux/ioctl_linux.c b/os_dep/linux/ioctl_linux.c index be2891e..87b8a5d 100644 --- a/os_dep/linux/ioctl_linux.c +++ b/os_dep/linux/ioctl_linux.c @@ -16,10 +16,7 @@ #include #include -#include "../../hal/phydm/phydm_precomp.h" -#ifdef RTW_HALMAC -#include "../../hal/hal_halmac.h" -#endif + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) #define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e) @@ -31,7 +28,6 @@ extern int rtw_ht_enable; #endif - #define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV+30) #define SCAN_ITEM_SIZE 768 @@ -65,6 +61,32 @@ extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000, 6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000}; +/** + * hwaddr_aton - Convert ASCII string to MAC address + * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") + * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) + * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) + */ +static int hwaddr_aton_i(const char *txt, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) { + int a, b; + + a = hex2num_i(*txt++); + if (a < 0) + return -1; + b = hex2num_i(*txt++); + if (b < 0) + return -1; + *addr++ = (a << 4) | b; + if (i < 5 && *txt++ != ':') + return -1; + } + + return 0; +} #ifdef CONFIG_RTW_ANDROID static void indicate_wx_custom_event(_adapter *padapter, char *msg) { @@ -237,80 +259,6 @@ uint rtw_is_cckratesonly_included(u8 *rate) } */ -#ifdef CONFIG_IOCTL_WEXT -static int search_p2p_wfd_ie(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) -{ -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#ifdef CONFIG_WFD - if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) { - - } else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) || - (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type)) -#endif /* CONFIG_WFD */ - { - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - u32 blnGotP2PIE = _FALSE; - - /* User is doing the P2P device discovery */ - /* The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. */ - /* If not, the driver should ignore this AP and go to the next AP. */ - - /* Verifying the SSID */ - if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) { - u32 p2pielen = 0; - - /* Verifying the P2P IE */ - if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen)) - blnGotP2PIE = _TRUE; - } - - if (blnGotP2PIE == _FALSE) - return _FALSE; - - } - } - -#ifdef CONFIG_WFD - if (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) { - u32 blnGotWFD = _FALSE; - u8 *wfd_ie; - uint wfd_ielen = 0; - - wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); - if (wfd_ie) { - u8 *wfd_devinfo; - uint wfd_devlen; - - wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); - if (wfd_devinfo) { - if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) { - /* the first two bits will indicate the WFD device type */ - if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) { - /* If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */ - blnGotWFD = _TRUE; - } - } else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) { - /* the first two bits will indicate the WFD device type */ - if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) { - /* If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */ - /* Todo: How about the SSink?! */ - blnGotWFD = _TRUE; - } - } - } - } - - if (blnGotWFD == _FALSE) - return _FALSE; - } -#endif /* CONFIG_WFD */ - -#endif /* CONFIG_P2P */ - return _TRUE; -} static inline char *iwe_stream_mac_addr_proess(_adapter *padapter, struct iw_request_info *info, struct wlan_network *pnetwork, char *start, char *stop, struct iw_event *iwe) @@ -404,7 +352,7 @@ static inline char *iwe_stream_protocol_process(_adapter *padapter, #ifdef CONFIG_80211AC_VHT /* parsing VHT_CAP_IE */ - if(padapter->registrypriv.wireless_mode & WIRELESS_11AC) { + if(is_supported_vht(padapter->registrypriv.wireless_mode)) { p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); if (p && vht_ielen > 0) vht_cap = _TRUE; @@ -473,7 +421,7 @@ static inline char *iwe_stream_rate_process(_adapter *padapter, } #ifdef CONFIG_80211AC_VHT /* parsing VHT_CAP_IE */ - if(padapter->registrypriv.wireless_mode & WIRELESS_11AC){ + if(is_supported_vht(padapter->registrypriv.wireless_mode)){ p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); if (p && vht_ielen > 0) { u8 mcs_map[2]; @@ -680,14 +628,11 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, { u8 ss, sq; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - s16 noise = 0; -#endif /* Add quality statistics */ iwe->cmd = IWEVQUAL; iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +#if 0 /*def CONFIG_BACKGROUND_NOISE_MONITOR*/ | IW_QUAL_NOISE_UPDATED #else | IW_QUAL_NOISE_INVALID @@ -698,9 +643,9 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, ; if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { - ss = padapter->recvpriv.signal_strength; - sq = padapter->recvpriv.signal_qual; + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) { + ss = padapter->recvinfo.signal_strength; + sq = padapter->recvinfo.signal_qual; } else { ss = pnetwork->network.PhyInfo.SignalStrength; sq = pnetwork->network.PhyInfo.SignalQuality; @@ -708,7 +653,7 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, #ifdef CONFIG_SIGNAL_DISPLAY_DBM - iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ + iwe->u.qual.level = (u8) rtw_phl_rssi_to_dbm(ss); /* dbm */ #else iwe->u.qual.level = (u8)ss; /* % */ #endif @@ -717,18 +662,8 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, #ifdef CONFIG_PLATFORM_ROCKCHIPS iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */ -#else -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - if (IS_NM_ENABLE(padapter)) { - noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); - #ifndef CONFIG_SIGNAL_DISPLAY_DBM - noise = translate_dbm_to_percentage(noise);/*percentage*/ - #endif - iwe->u.qual.noise = noise; - } #else iwe->u.qual.noise = 0; /* noise level */ -#endif #endif /* CONFIG_PLATFORM_ROCKCHIPS */ /* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */ @@ -762,9 +697,6 @@ static char *translate_scan(_adapter *padapter, u16 cap = 0; _rtw_memset(&iwe, 0, sizeof(iwe)); - if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop)) - return start; - start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe); @@ -917,7 +849,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, struct sta_info *psta, *pbcmc_sta; struct sta_priv *pstapriv = &padapter->stapriv; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ + if (MLME_IS_STA(padapter) || MLME_IS_MP(padapter)) { /* sta mode */ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); if (psta == NULL) { /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ @@ -970,15 +902,11 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); psecuritypriv->binstallBIPkey = _TRUE; + rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); #endif /* CONFIG_IEEE80211W */ } -#ifdef CONFIG_P2P - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) - rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); -#endif /* CONFIG_P2P */ - /* WPA/WPA2 key-handshake has completed */ clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE); } @@ -1140,10 +1068,6 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); -#ifdef CONFIG_P2P - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) - rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); -#endif /* CONFIG_P2P */ cnt += buf[cnt + 1] + 2; break; @@ -1184,7 +1108,7 @@ static int rtw_wx_get_name(struct net_device *dev, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u32 ht_ielen = 0; char *p; - u8 ht_cap = _FALSE, vht_cap = _FALSE; + u8 ht_cap = _FALSE, vht_cap = _FALSE, he_cap = _FALSE; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; NDIS_802_11_RATES_EX *prates = NULL; @@ -1199,12 +1123,22 @@ static int rtw_wx_get_name(struct net_device *dev, ht_cap = _TRUE; } #ifdef CONFIG_80211AC_VHT - if ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) && + if (is_supported_vht(padapter->registrypriv.wireless_mode) && (pmlmepriv->vhtpriv.vht_option == _TRUE)) vht_cap = _TRUE; #endif +#ifdef CONFIG_80211AX_HE + if (is_supported_he(padapter->registrypriv.wireless_mode) && + (pmlmepriv->hepriv.he_option == _TRUE)) + he_cap = _TRUE; +#endif prates = &pcur_bss->SupportedRates; +#ifdef CONFIG_80211AX_HE + if (he_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AX"); + else +#endif if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) { if (ht_cap == _TRUE) snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); @@ -1214,7 +1148,7 @@ static int rtw_wx_get_name(struct net_device *dev, if (ht_cap == _TRUE) snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); else { - if(padapter->registrypriv.wireless_mode & WIRELESS_11G) + if(padapter->registrypriv.wireless_mode & WLAN_MD_11G) snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); else snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); @@ -1263,15 +1197,15 @@ static int rtw_wx_set_freq(struct net_device *dev, if (wrqu->freq.m <= 1000) { if (wrqu->freq.flags == IW_FREQ_AUTO) { if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) { - padapter->mlmeextpriv.cur_channel = wrqu->freq.m; + padapter->mlmeextpriv.chandef.chan = wrqu->freq.m; RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m); } else { - padapter->mlmeextpriv.cur_channel = 1; + padapter->mlmeextpriv.chandef.chan = 1; RTW_INFO("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__); } } else { - padapter->mlmeextpriv.cur_channel = wrqu->freq.m; - RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); + padapter->mlmeextpriv.chandef.chan = wrqu->freq.m; + RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.chandef.chan); } } else { while (wrqu->freq.e) { @@ -1297,10 +1231,14 @@ static int rtw_wx_set_freq(struct net_device *dev, } /* If freq is invalid, rtw_freq2ch() will return channel 1 */ - padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); - RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); - } - set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + padapter->mlmeextpriv.chandef.chan = rtw_freq2ch(freq); + RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.chandef.chan); + } + set_channel_bwmode(padapter, + padapter->mlmeextpriv.chandef.chan, + CHAN_OFFSET_NO_EXT, + CHANNEL_WIDTH_20, + _FALSE); exit: rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); @@ -1322,14 +1260,41 @@ static int rtw_wx_get_freq(struct net_device *dev, wrqu->freq.i = pcur_bss->Configuration.DSConfig; } else { - wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000; + wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.chandef.chan) * 100000; wrqu->freq.e = 1; - wrqu->freq.i = padapter->mlmeextpriv.cur_channel; + wrqu->freq.i = padapter->mlmeextpriv.chandef.chan; } return 0; } +u32 wext_mode_to_rtw_mlme_state(union iwreq_data *wrqu) +{ + switch (wrqu->mode) { + #ifdef CONFIG_WIFI_MONITOR + case IW_MODE_MONITOR: + return WIFI_MONITOR_STATE; + #endif + case IW_MODE_ADHOC: + return WIFI_ADHOC_STATE; + #ifdef CONFIG_AP_MODE + case IW_MODE_MASTER: + return WIFI_AP_STATE; + #endif + case IW_MODE_INFRA: + return WIFI_STATION_STATE; + + #ifdef CONFIG_RTW_MESH + case IW_MODE_MESH: + return WIFI_MESH_STATE; + #endif + + case IW_MODE_AUTO: + default: + return WIFI_STATION_STATE; + } +} + static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { @@ -1344,7 +1309,7 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, goto exit; } - if (!rtw_is_hw_init_completed(padapter)) { + if (!rtw_hw_is_init_completed(adapter_to_dvobj(padapter))) { ret = -EPERM; goto exit; } @@ -1421,19 +1386,15 @@ static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + if (MLME_IS_STA(padapter)) wrqu->mode = IW_MODE_INFRA; - else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || - (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) - + else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)) wrqu->mode = IW_MODE_ADHOC; - else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + else if (MLME_IS_AP(padapter)) wrqu->mode = IW_MODE_MASTER; - else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + else if (MLME_IS_MONITOR(padapter)) wrqu->mode = IW_MODE_MONITOR; else wrqu->mode = IW_MODE_AUTO; @@ -1537,8 +1498,8 @@ static int rtw_wx_get_sens(struct net_device *dev, * For rockchip platform's wpa_driver_wext_get_rssi */ if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { - /* wrqu->sens.value=-padapter->recvpriv.signal_strength; */ - wrqu->sens.value = -padapter->recvpriv.rssi; + /* wrqu->sens.value=-padapter->recvinfo.signal_strength; */ + wrqu->sens.value = -padapter->recvinfo.rssi; /* RTW_INFO("%s: %d\n", __FUNCTION__, wrqu->sens.value); */ wrqu->sens.fixed = 0; /* no auto select */ } else @@ -1715,7 +1676,6 @@ static int rtw_wx_set_wap(struct net_device *dev, union iwreq_data *awrq, char *extra) { - _irqL irqL; uint ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct sockaddr *temp = (struct sockaddr *)awrq; @@ -1752,7 +1712,7 @@ static int rtw_wx_set_wap(struct net_device *dev, goto cancel_ps_deny; } - if (!padapter->bup) { + if (!padapter->netif_up) { ret = -1; goto cancel_ps_deny; } @@ -1764,7 +1724,7 @@ static int rtw_wx_set_wap(struct net_device *dev, } authmode = padapter->securitypriv.ndisauthtype; - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); phead = get_list_head(queue); pmlmepriv->pscanned = get_next(phead); @@ -1798,7 +1758,7 @@ static int rtw_wx_set_wap(struct net_device *dev, if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) { if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0)) { ret = -1; - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); goto cancel_ps_deny; } @@ -1806,7 +1766,7 @@ static int rtw_wx_set_wap(struct net_device *dev, } } - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); rtw_set_802_11_authentication_mode(padapter, authmode); /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ @@ -1897,9 +1857,6 @@ static int rtw_wx_set_mlme(struct net_device *dev, default: return -EOPNOTSUPP; } -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_do_disconnect(padapter); -#endif return ret; } @@ -1987,13 +1944,6 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, indicate_wx_scan_complete_event(padapter); goto cancel_ps_deny; } -#endif -#ifdef CONFIG_RTW_REPEATER_SON - if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { - RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); - indicate_wx_scan_complete_event(padapter); - goto cancel_ps_deny; - } #endif if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO("AP mode process WPS\n"); @@ -2016,15 +1966,6 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, #endif #endif -#ifdef CONFIG_P2P - if (pwdinfo->p2p_state != P2P_STATE_NONE) { - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); - rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL); - rtw_free_network_queue(padapter, _TRUE); - } -#endif /* CONFIG_P2P */ - #if WIRELESS_EXT >= 17 if (wrqu->data.length == sizeof(struct iw_scan_req)) { struct iw_scan_req *req = (struct iw_scan_req *)extra; @@ -2039,7 +1980,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); - _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); + _status = rtw_sitesurvey_cmd(padapter, &parm); } else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); @@ -2130,11 +2071,11 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, parm.ssid_num = ssid_index; /* jeff: it has still some scan paramater to parse, we only do this now... */ - _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); + _status = rtw_sitesurvey_cmd(padapter, &parm); } else - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); + _status = rtw_sitesurvey_cmd(padapter, NULL); if (_status == _FALSE) ret = -1; @@ -2153,7 +2094,6 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *extra) { - _irqL irqL; _list *plist, *phead; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); @@ -2177,23 +2117,12 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__); #endif - if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) { + if (adapter_to_pwrctl(padapter)->brfoffbyhw && dev_is_drv_stopped(adapter_to_dvobj(padapter))) { ret = -EINVAL; goto exit; } -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - wait_for_surveydone = 200; - else { - /* P2P is disabled */ - wait_for_surveydone = 100; - } -#else - { - wait_for_surveydone = 100; - } -#endif /* CONFIG_P2P */ + wait_for_surveydone = 100; #if 1 /* Wireless Extension use EAGAIN to try */ wait_status = WIFI_UNDER_SURVEY @@ -2218,7 +2147,7 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, break; } #endif - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); @@ -2254,7 +2183,7 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); wrqu->data.length = ev - extra; wrqu->data.flags = 0; @@ -2279,7 +2208,6 @@ static int rtw_wx_set_essid(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *extra) { - _irqL irqL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _queue *queue = &pmlmepriv->scanned_queue; @@ -2317,7 +2245,7 @@ static int rtw_wx_set_essid(struct net_device *dev, goto cancel_ps_deny; } - if (!padapter->bup) { + if (!padapter->netif_up) { ret = -1; goto cancel_ps_deny; } @@ -2359,7 +2287,7 @@ static int rtw_wx_set_essid(struct net_device *dev, _rtw_memcpy(ndis_ssid.Ssid, extra, len); src_ssid = ndis_ssid.Ssid; - _enter_critical_bh(&queue->lock, &irqL); + _rtw_spinlock_bh(&queue->lock); phead = get_list_head(queue); pmlmepriv->pscanned = get_next(phead); @@ -2396,14 +2324,14 @@ static int rtw_wx_set_essid(struct net_device *dev, if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0) == _FALSE) { ret = -1; - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); goto cancel_ps_deny; } break; } } - _exit_critical_bh(&queue->lock, &irqL); + _rtw_spinunlock_bh(&queue->lock); rtw_set_802_11_authentication_mode(padapter, authmode); /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { @@ -3024,9 +2952,15 @@ static int rtw_wx_set_auth(struct net_device *dev, if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) { LeaveAllPowerSaveMode(padapter); rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); + if (1 +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__); rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); + } #endif @@ -3185,9 +3119,9 @@ static int rtw_wx_get_nick(struct net_device *dev, /* struct security_priv *psecuritypriv = &padapter->securitypriv; */ if (extra) { - wrqu->data.length = 16; + wrqu->data.length = 14; wrqu->data.flags = 1; - _rtw_memcpy(extra, "rtl88x2bu_ohd", 16); + _rtw_memcpy(extra, "", 14); } /* rtw_signal_process(pid, SIGUSR1); */ /* for test */ @@ -3209,44 +3143,17 @@ static int rtw_wx_get_nick(struct net_device *dev, /* RTW_INFO("auth_type=0x%x\n", psecuritypriv->ndisauthtype); */ /* RTW_INFO("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); */ -#if 0 - RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); - RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); - RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); - RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); - RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); - - RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); - - - RTW_INFO("\n"); - - RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); - RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); - - RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); - - RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); - - RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); - RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); - - RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); - RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); - RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); - RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); -#endif - return 0; } -#endif static int rtw_wx_read32(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter; + + _adapter *padapter; + struct dvobj_priv *dvobj; struct iw_point *p; u16 len; u32 addr; @@ -3257,7 +3164,8 @@ static int rtw_wx_read32(struct net_device *dev, ret = 0; - padapter = (PADAPTER)rtw_netdev_priv(dev); + padapter = (_adapter *)rtw_netdev_priv(dev); + dvobj = adapter_to_dvobj(padapter); p = &wrqu->data; len = p->length; if (0 == len) @@ -3278,18 +3186,18 @@ static int rtw_wx_read32(struct net_device *dev, switch (bytes) { case 1: - data32 = rtw_read8(padapter, addr); + data32 = rtw_phl_read8(dvobj->phl, addr); sprintf(extra, "0x%02X", data32); break; case 2: - data32 = rtw_read16(padapter, addr); + data32 = rtw_phl_read16(dvobj->phl, addr); sprintf(extra, "0x%04X", data32); break; case 4: - data32 = rtw_read32(padapter, addr); + data32 = rtw_phl_read32(dvobj->phl, addr); sprintf(extra, "0x%08X", data32); break; - +#if 0 #if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS) case 11: data32 = rtw_sd_iread8(padapter, addr); @@ -3304,6 +3212,7 @@ static int rtw_wx_read32(struct net_device *dev, sprintf(extra, "0x%08X", data32); break; #endif +#endif default: RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__); ret = -EINVAL; @@ -3313,7 +3222,6 @@ static int rtw_wx_read32(struct net_device *dev, exit: rtw_mfree(ptmp, len); - return 0; } @@ -3321,7 +3229,10 @@ static int rtw_wx_write32(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); u32 addr; u32 data32; @@ -3335,15 +3246,15 @@ static int rtw_wx_write32(struct net_device *dev, switch (bytes) { case 1: - rtw_write8(padapter, addr, (u8)data32); + rtw_phl_write8(dvobj->phl, addr, (u8)data32); RTW_INFO("%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32); break; case 2: - rtw_write16(padapter, addr, (u16)data32); + rtw_phl_write16(dvobj->phl, addr, (u16)data32); RTW_INFO("%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32); break; case 4: - rtw_write32(padapter, addr, data32); + rtw_phl_write32(dvobj->phl, addr, data32); RTW_INFO("%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32); break; default: @@ -3359,12 +3270,13 @@ static int rtw_wx_read_rf(struct net_device *dev, union iwreq_data *wrqu, char *extra) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); u32 path, addr, data32; path = *(u32 *)extra; addr = *((u32 *)extra + 1); - data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF); + data32 = rtw_phl_read_rfreg(GET_PHL_INFO(dvobj), path, addr, 0xFFFFF); /* RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */ /* * IMPORTANT!! @@ -3381,6 +3293,7 @@ static int rtw_wx_write_rf(struct net_device *dev, union iwreq_data *wrqu, char *extra) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); u32 path, addr, data32; @@ -3388,7 +3301,7 @@ static int rtw_wx_write_rf(struct net_device *dev, addr = *((u32 *)extra + 1); data32 = *((u32 *)extra + 2); /* RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */ - rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32); + rtw_phl_write_rfreg(GET_PHL_INFO(dvobj), path, addr, 0xFFFFF, data32); return 0; } @@ -3415,7 +3328,6 @@ static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a, } #endif -#ifdef CONFIG_IOCTL_WEXT static int dummy(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { @@ -3427,16 +3339,17 @@ static int dummy(struct net_device *dev, struct iw_request_info *a, return -1; } -#endif static int rtw_wx_set_channel_plan(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 channel_plan_req = (u8)(*((int *)wrqu)); + u16 channel_plan_req = (u16)(*((int *)wrqu)); - if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req)) + rtw_chplan_ioctl_input_mapping(&channel_plan_req, NULL); + + if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req, RTW_CHPLAN_6G_UNSPECIFIED, RTW_REGD_SET_BY_USER)) return -EPERM; return 0; @@ -3463,7 +3376,7 @@ static int rtw_wx_get_sensitivity(struct net_device *dev, /* Modified by Albert 20110914 */ /* This is in dbm format for MTK platform. */ - wrqu->qual.level = padapter->recvpriv.rssi; + wrqu->qual.level = padapter->recvinfo.rssi; RTW_INFO(" level = %u\n", wrqu->qual.level); #endif return 0; @@ -3487,6 +3400,7 @@ static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) { pRW_Reg RegRWStruct; struct rf_reg_param *prfreg; + struct dvobj_priv dvobj = adapter_to_dvobj(padapter); u8 path; u8 offset; u32 value; @@ -3538,7 +3452,7 @@ static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) path = (u8)prfreg->path; offset = (u8)prfreg->offset; - value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff); + value = rtw_phl_read_rfreg(GET_PHL_INFO(dvobj), path, offset, 0xffffffff); prfreg->value = value; @@ -3551,14 +3465,14 @@ static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) offset = (u8)prfreg->offset; value = prfreg->value; - rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value); + rtw_phl_write_rfreg(GET_PHL_INFO(dvobj), path, offset, 0xffffffff, value); break; case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO): RTW_INFO("==> trigger gpio 0\n"); rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0); break; -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC case GEN_MP_IOCTL_SUBCODE(SET_DM_BT): RTW_INFO("==> set dm_bt_coexist:%x\n", *(u8 *)pdata); rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata); @@ -3590,7 +3504,7 @@ static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info uint status = 0; u16 len; u8 *pparmbuf = NULL, bset; - PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_point *p = &wrqu->data; /* RTW_INFO("+rtw_mp_ioctl_hdl\n"); */ @@ -3694,7 +3608,6 @@ static int rtw_get_ap_info(struct net_device *dev, { int ret = 0; u32 cnt = 0, wpa_ielen; - _irqL irqL; _list *plist, *phead; unsigned char *pbuf; u8 bssid[ETH_ALEN]; @@ -3707,7 +3620,7 @@ static int rtw_get_ap_info(struct net_device *dev, RTW_INFO("+rtw_get_aplist_info\n"); - if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + if (dev_is_drv_stopped(adapter_to_dvobj(padapter)) || (pdata == NULL)) { ret = -EINVAL; goto exit; } @@ -3732,7 +3645,7 @@ static int rtw_get_ap_info(struct net_device *dev, goto exit; } - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinlock_bh(&(pmlmepriv->scanned_queue.lock)); phead = get_list_head(queue); plist = get_next(phead); @@ -3744,9 +3657,10 @@ static int rtw_get_ap_info(struct net_device *dev, pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + /* if(hwaddr_aton_i(pdata->pointer, bssid)) */ if (hwaddr_aton_i(data, bssid)) { RTW_INFO("Invalid BSSID '%s'.\n", (u8 *)data); - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); return -EINVAL; } @@ -3772,7 +3686,7 @@ static int rtw_get_ap_info(struct net_device *dev, } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _rtw_spinunlock_bh(&(pmlmepriv->scanned_queue.lock)); if (pdata->length >= 34) { if (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) { @@ -3797,7 +3711,7 @@ static int rtw_set_pid(struct net_device *dev, int *pdata = (int *)wrqu; int selector; - if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + if (dev_is_drv_stopped(adapter_to_dvobj(padapter)) || (pdata == NULL)) { ret = -EINVAL; goto exit; } @@ -3829,7 +3743,7 @@ static int rtw_wps_start(struct net_device *dev, u32 u32wps_start = 0; unsigned int uintRet = 0; - if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter)) || (NULL == pdata)) { ret = -EINVAL; goto exit; } @@ -3853,6070 +3767,2499 @@ static int rtw_wps_start(struct net_device *dev, } -#ifdef CONFIG_P2P -static int rtw_wext_p2p_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +extern int rtw_change_ifname(_adapter *padapter, const char *ifname); +static int rtw_rereg_nd_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - enum P2P_ROLE init_role = P2P_ROLE_DISABLE; + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; + char new_ifname[IFNAMSIZ]; + + if (rereg_priv->old_ifname[0] == 0) { + char *reg_ifname; #ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; + if (padapter->isprimary) + reg_ifname = padapter->registrypriv.ifname; + else #endif + reg_ifname = padapter->registrypriv.if2name; - if (*extra == '0') - init_role = P2P_ROLE_DISABLE; - else if (*extra == '1') - init_role = P2P_ROLE_DEVICE; - else if (*extra == '2') - init_role = P2P_ROLE_CLIENT; - else if (*extra == '3') - init_role = P2P_ROLE_GO; - - if (_FAIL == rtw_p2p_enable(padapter, init_role)) { - ret = -EFAULT; - goto exit; + strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; } - /* set channel/bandwidth */ - if (init_role != P2P_ROLE_DISABLE) { - u8 channel, ch_offset; - u16 bwmode; - - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) { - /* Stay at the listen state and wait for discovery. */ - channel = pwdinfo->listen_channel; - pwdinfo->operating_channel = pwdinfo->listen_channel; - ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - bwmode = CHANNEL_WIDTH_20; - } -#ifdef CONFIG_CONCURRENT_MODE - else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { - - _set_timer(&prochinfo->ap_roch_ch_switch_timer, pwdinfo->ext_listen_interval); + /* RTW_INFO("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); */ + if (wrqu->data.length > IFNAMSIZ) + return -EFAULT; - channel = rtw_mi_get_union_chan(padapter); - ch_offset = rtw_mi_get_union_offset(padapter); - bwmode = rtw_mi_get_union_bw(padapter); + if (copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ)) + return -EFAULT; - pwdinfo->operating_channel = channel; - } -#endif - else { - pwdinfo->operating_channel = pmlmeext->cur_channel; + if (0 == strcmp(rereg_priv->old_ifname, new_ifname)) + return ret; - channel = pwdinfo->operating_channel; - ch_offset = pmlmeext->cur_ch_offset; - bwmode = pmlmeext->cur_bwmode; - } + RTW_INFO("%s new_ifname:%s\n", __FUNCTION__, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, current); + ret = rtw_change_ifname(padapter, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, NULL); + if (0 != ret) + goto exit; - set_channel_bwmode(padapter, channel, ch_offset, bwmode); + if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { + /* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */ } -exit: - return ret; - -} - -static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + if (_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) { - RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra)); - _rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra)); - pwdinfo->nego_ssidlen = strlen(extra); + RTW_INFO("%s disable\n", __FUNCTION__); + /* free network queue for Android's timming issue */ + rtw_free_network_queue(padapter, _TRUE); + /* the interface is being "disabled", we can do deeper IPS */ + /* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */ + /* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */ + } +exit: return ret; } +#ifdef DBG_CMD_QUEUE +u8 dump_cmd_id = 0; +#endif -static int rtw_p2p_set_intent(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 intent = pwdinfo->intent; - - extra[wrqu->data.length] = 0x00; - - intent = rtw_atoi(extra); - - if (intent <= 15) - pwdinfo->intent = intent; - else - ret = -1; - - RTW_INFO("[%s] intent = %d\n", __FUNCTION__, intent); - - return ret; - -} - -static int rtw_p2p_set_listen_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +#if 1 +static int rtw_dbg_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 listen_ch = pwdinfo->listen_channel; /* Listen channel number */ - - extra[wrqu->data.length] = 0x00; - listen_ch = rtw_atoi(extra); - - if ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) { - pwdinfo->listen_channel = listen_ch; - set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } else - ret = -1; - - RTW_INFO("[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel); return ret; - } - -static int rtw_p2p_set_op_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +#else +static int rtw_dbg_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - /* Commented by Albert 20110524 - * This function is used to set the operating channel if the driver will become the group owner */ - int ret = 0; + u8 major_cmd, minor_cmd; + u16 arg; + u32 extra_arg, *pdata, val32; + struct sta_info *psta; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 op_ch = pwdinfo->operating_channel; /* Operating channel number */ - - extra[wrqu->data.length] = 0x00; - - op_ch = (u8) rtw_atoi(extra); - if (op_ch > 0) - pwdinfo->operating_channel = op_ch; - else - ret = -1; - - RTW_INFO("[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel); - - return ret; - -} - + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; -static int rtw_p2p_profilefound(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + pdata = (u32 *)&wrqu->data; - /* Comment by Albert 2010/10/13 */ - /* Input data format: */ - /* Ex: 0 */ - /* Ex: 1XX:XX:XX:XX:XX:XXYYSSID */ - /* 0 => Reflush the profile record list. */ - /* 1 => Add the profile list */ - /* XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */ - /* YY => SSID Length */ - /* SSID => SSID for persistence group */ - - RTW_INFO("[%s] In value = %s, len = %d\n", __FUNCTION__, extra, wrqu->data.length - 1); - - - /* The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - if (extra[0] == '0') { - /* Remove all the profile information of wifidirect_info structure. */ - _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); - pwdinfo->profileindex = 0; - } else { - if (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM) - ret = -1; - else { - int jj, kk; + val32 = *pdata; + arg = (u16)(val32 & 0x0000ffff); + major_cmd = (u8)(val32 >> 24); + minor_cmd = (u8)((val32 >> 16) & 0x00ff); - /* Add this profile information into pwdinfo->profileinfo */ - /* Ex: 1XX:XX:XX:XX:XX:XXYYSSID */ - for (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3) - pwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]); + extra_arg = *(pdata + 1); - /* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */ - /* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */ - pwdinfo->profileindex++; - } + switch (major_cmd) { + case 0x70: /* read_reg */ + switch (minor_cmd) { + case 1: + RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; } - } - - return ret; - -} + break; + case 0x71: /* write_reg */ + switch (minor_cmd) { + case 1: + rtw_write8(padapter, arg, extra_arg); + RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + rtw_write16(padapter, arg, extra_arg); + RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + rtw_write32(padapter, arg, extra_arg); + RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; + } + break; + case 0x72: /* read_bb */ + RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_phl_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x73: /* write_bb */ + rtw_phl_write_bbreg(padapter, arg, 0xffffffff, extra_arg); + RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_phl_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x74: /* read_rf */ + RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; + case 0x75: /* write_rf */ + rtw_phl_write_rfreg(GET_PHL_INFO(dvobj), minor_cmd, arg, 0xffffffff, extra_arg); + RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; -static int rtw_p2p_setDN(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + case 0x76: + switch (minor_cmd) { + case 0x00: /* normal mode, */ + padapter->recvinfo.is_signal_dbg = 0; + break; + case 0x01: /* dbg mode */ + padapter->recvinfo.is_signal_dbg = 1; + extra_arg = extra_arg > 100 ? 100 : extra_arg; + padapter->recvinfo.signal_strength_dbg = extra_arg; + break; + } + break; + case 0x78: + break; + case 0x79: { + /* + * dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15 + * dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15 + */ + u8 value = extra_arg & 0x0f; + u8 sign = minor_cmd; + u16 write_value = 0; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value); + if (sign) + value = value | 0x10; - RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1); - _rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN); - _rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1); - pwdinfo->device_name_len = wrqu->data.length - 1; + write_value = value | (value << 5); + rtw_write16(padapter, 0x6d9, write_value); + } + break; + case 0x7a: + receive_disconnect(padapter, pmlmeinfo->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + break; + case 0x7F: + switch (minor_cmd) { + case 0x0: + RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv)); + break; + case 0x01: + RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", + psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); + break; + case 0x03: + RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option); +#ifdef CONFIG_80211N_HT + RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option); +#endif /* CONFIG_80211N_HT */ + break; + case 0x04: + RTW_INFO("cur_ch=%d\n", pmlmeext->chandef.chan); + RTW_INFO("cur_bw=%d\n", pmlmeext->chandef.bw); + RTW_INFO("cur_ch_off=%d\n", pmlmeext->chandef.offset); - return ret; + RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter)); + RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter)); + RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter)); -} + break; + case 0x05: + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid); + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", + pmlmeext->chandef.chan, pmlmeext->chandef.bw, pmlmeext->chandef.offset); + RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid, psta->phl_sta->ra_info.rate_id); +#ifdef CONFIG_80211N_HT + RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->phl_sta->chandef.bw, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif /* CONFIG_80211N_HT */ + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } else + RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + break; + case 0x06: { + u64 tsf = 0; -static int rtw_p2p_get_status(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg); + RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf); + } + break; + case 0x07: + RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n" + , dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False" + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False"); + break; + case 0x08: { + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct recv_priv *precvpriv = &adapter_to_dvobj(padapter)->recvpriv; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" + ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" + ", free_recvframe_cnt=%d\n", + pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, + pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, + precvpriv->free_recvframe_cnt); + } + break; + case 0x09: { + int i; + _list *plist, *phead; - if (padapter->bShowGetP2PState) { - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); - } +#ifdef CONFIG_AP_MODE + RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); +#endif + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); - /* Commented by Albert 2010/10/12 */ - /* Because of the output size limitation, I had removed the "Role" information. */ - /* About the "Role" information, we will use the new private IOCTL to get the "Role" information. */ - sprintf(extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo)); - wrqu->data.length = strlen(extra); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); - return ret; + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); -} + plist = get_next(plist); -/* Commented by Albert 20110520 - * This function will return the config method description - * This config method description will show us which config method the remote P2P device is intented to use - * by sending the provisioning discovery request frame. */ + if (extra_arg == psta->phl_sta->aid) { + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->phl_sta->mac_addr)); + RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->phl_sta->aid, psta->phl_sta->macid, psta->phl_sta->ra_info.rate_id); +#ifdef CONFIG_80211N_HT + RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", + psta->phl_sta->chandef.bw, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, + psta->htpriv.sgi_40m); + RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif /* CONFIG_80211N_HT */ -static int rtw_p2p_get_req_cm(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ +#ifdef CONFIG_AP_MODE + RTW_INFO("capability=0x%x\n", psta->capability); + RTW_INFO("flags=0x%x\n", psta->flags); + RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk); + RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); + RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); + RTW_INFO("qos_info=0x%x\n", psta->qos_info); +#endif + RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } - sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); - wrqu->data.length = strlen(extra); - return ret; + } + } -} + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); + } + break; -static int rtw_p2p_get_role(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ + /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ + /* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + if (arg == 0) { + RTW_INFO("disable driver ctrl vcs\n"); + padapter->driver_vcs_en = 0; + } else if (arg == 1) { + RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg); + padapter->driver_vcs_en = 1; - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + if (extra_arg > 2) + padapter->driver_vcs_type = 1; + else + padapter->driver_vcs_type = extra_arg; + } + } + break; + case 0x0c: { /* dump rx/tx packet */ + if (arg == 0) { + RTW_INFO("dump rx packet (%d)\n", extra_arg); + /* pHalData->bDumpRxPkt =extra_arg; */ + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); + } else if (arg == 1) { + RTW_INFO("dump tx packet (%d)\n", extra_arg); + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); + } + } + break; + case 0x0e: { + if (arg == 0) { + RTW_INFO("disable driver ctrl rx_ampdu_factor\n"); + padapter->driver_rx_ampdu_factor = 0xFF; + } else if (arg == 1) { - sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo)); - wrqu->data.length = strlen(extra); - return ret; + RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg); -} + if (extra_arg > 0x03) + padapter->driver_rx_ampdu_factor = 0xFF; + else + padapter->driver_rx_ampdu_factor = extra_arg; + } + } + break; + #ifdef DBG_CONFIG_ERROR_DETECT + case 0x0f: { + if (extra_arg == 0) { + RTW_INFO("###### silent reset test.......#####\n"); + rtw_hal_sreset_reset(padapter); + } else { + struct rtw_phl_com_t *phl_com = GET_PHL_COM(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + psrtpriv->dbg_trigger_point = extra_arg; + } + } + break; + case 0x15: { + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts); + } + break; -static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + #endif - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + case 0x10: /* driver version display */ + dump_drv_version(RTW_DBGDUMP); + break; + case 0x11: { /* dump linked status */ + int pre_mode; + pre_mode = padapter->bLinkInfoDump; + /* rtw_hal_linked_info_dump(padapter,extra_arg); */ + if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */ + padapter->bLinkInfoDump = extra_arg; + else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */ + /* RTW_INFO("rtw_hal_linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */ + rtw_hal_linked_info_dump(padapter, extra_arg); + } - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); - sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); - wrqu->data.length = strlen(extra); - return ret; - -} - -static int rtw_p2p_get_peer_devaddr(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], - pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], - pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); - sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", - pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], - pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], - pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); - wrqu->data.length = strlen(extra); - return ret; + } + break; +#ifdef CONFIG_80211N_HT + case 0x12: { /* set rx_stbc */ + struct registry_priv *pregpriv = &padapter->registrypriv; + /* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */ + /* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ + if (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3) { + pregpriv->rx_stbc = extra_arg; + RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc); + } else { + RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc); + } + } + break; + case 0x13: { /* set ampdu_enable */ + struct registry_priv *pregpriv = &padapter->registrypriv; + /* 0: disable, 0x1:enable */ + if (extra_arg < 2) { + pregpriv->ampdu_enable = extra_arg; + RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable); + } else { + RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable); + } + } + break; +#endif + case 0x14: { /* get wifi_spec */ + struct registry_priv *pregpriv = &padapter->registrypriv; + RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec); -} + } + break; -static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +#ifdef DBG_FIXED_CHAN + case 0x17: { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + printk("===> Fixed channel to %d\n", extra_arg); + pmlmeext->fixed_chan = extra_arg; -{ + } + break; +#endif +#ifdef CONFIG_80211N_HT + case 0x19: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + /* extra_arg : */ + /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */ + /* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ + if (arg == 0) { + RTW_INFO("driver disable LDPC\n"); + pregistrypriv->ldpc_cap = 0x00; + } else if (arg == 1) { + RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg); + pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33); + } + } + break; + case 0x1a: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + /* extra_arg : */ + /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */ + /* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ + if (arg == 0) { + RTW_INFO("driver disable STBC\n"); + pregistrypriv->stbc_cap = 0x00; + } else if (arg == 1) { + RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg); + pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33); + } + } + break; +#endif /* CONFIG_80211N_HT */ + case 0x1b: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], - pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], - pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); - sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], - pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], - pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); - wrqu->data.length = strlen(extra); - return ret; + if (arg == 0) { + RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n"); + init_mlme_default_rate_set(padapter); +#ifdef CONFIG_80211N_HT + pregistrypriv->ht_enable = (u8)rtw_ht_enable; +#endif /* CONFIG_80211N_HT */ + } else if (arg == 1) { -} + int i; + u8 max_rx_rate; -static int rtw_p2p_get_groupid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg); -{ + max_rx_rate = (u8)extra_arg; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */ +#ifdef CONFIG_80211N_HT + pregistrypriv->ht_enable = 0; +#endif /* CONFIG_80211N_HT */ + for (i = 0; i < NumRates; i++) { + if (pmlmeext->datarate[i] > max_rx_rate) + pmlmeext->datarate[i] = 0xff; + } - sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", - pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1], - pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3], - pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5], - pwdinfo->groupid_info.ssid); - wrqu->data.length = strlen(extra); - return ret; + } +#ifdef CONFIG_80211N_HT + else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */ + u32 mcs_bitmap = 0x0; -} + for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++) + mcs_bitmap |= BIT(i); -static int rtw_p2p_get_op_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap); + } +#endif /* CONFIG_80211N_HT */ + } + } + break; + case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */ + if (arg == 0) { + RTW_INFO("disable driver ctrl ampdu density\n"); + padapter->driver_ampdu_spacing = 0xFF; + } else if (arg == 1) { -{ + RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg); - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + if (extra_arg > 0x07) + padapter->driver_ampdu_spacing = 0xFF; + else + padapter->driver_ampdu_spacing = extra_arg; + } + } + break; - RTW_INFO("[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel); +#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS) + case 0x1f: + { + int i, j = 0, test_cnts = 0; + static u8 test_code = 0x5A; + static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0; - sprintf(extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel); - wrqu->data.length = strlen(extra); - return ret; + u32 d_data, i_data; + u32 imr; -} + test_cnts = extra_arg; + for (i = 0; i < test_cnts; i++) { + if (RTW_CANNOT_IO(adapter_to_dvobj(padapter))) + break; -static int rtw_p2p_get_wps_configmethod(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) -{ + rtw_write8(padapter, 0x07, test_code); - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 blnMatch = 0; - u16 attr_content = 0; - uint attr_contentlen = 0; - u8 attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + d_data = rtw_read32(padapter, 0x04); + imr = rtw_read32(padapter, 0x10250014); + rtw_write32(padapter, 0x10250014, 0); + rtw_msleep_os(50); - /* Commented by Albert 20110727 */ - /* The input data is the MAC address which the application wants to know its WPS config method. */ - /* After knowing its WPS config method, the application can decide the config method for provisioning discovery. */ - /* Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */ + i_data = rtw_sd_iread32(padapter, 0x04); - RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + rtw_write32(padapter, 0x10250014, imr); - macstr2num(peerMAC, subcmd); + if (d_data != i_data) { + data_misatch_cnt++; + RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data); + } - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + if (test_code != (i_data >> 24)) { + d_acc_err_cnt++; + rtw_write8(padapter, 0x07, 0xAA); + RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data); + } + if ((j++) == 100) { + rtw_msleep_os(2000); + RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts); + j = 0; + } - phead = get_list_head(queue); - plist = get_next(phead); + test_code = ~test_code; + rtw_msleep_os(50); + } + RTW_INFO("========Indirect access test=========\n"); + RTW_INFO(" test_cnts = %d\n", test_cnts); + RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt); + RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt); + RTW_INFO("========Indirect access test=========\n\n"); + data_misatch_cnt = d_acc_err_cnt = 0; - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) + } break; +#endif + case 0x20: + { + if (arg == 0xAA) { + u8 page_offset, page_num; - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - u8 *wpsie; - uint wpsie_len = 0; - - /* The mac address is matched. */ - - wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); - if (wpsie) { - rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen); - if (attr_contentlen) { - attr_content = be16_to_cpu(attr_content); - sprintf(attr_content_str, "\n\nM=%.4d", attr_content); - blnMatch = 1; + page_offset = (u8)(extra_arg >> 16); + page_num = (u8)(extra_arg & 0xFF); + rtw_hal_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num); + } +#ifdef CONFIG_SUPPORT_FIFO_DUMP + else { + u8 fifo_sel; + u32 addr, size; + + fifo_sel = (u8)(arg & 0x0F); + addr = (extra_arg >> 16) & 0xFFFF; + size = extra_arg & 0xFFFF; + rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size); } +#endif } + break; + case 0x23: { + RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bNotifyChannelChange = extra_arg; break; } + case 0x24: { +#ifdef CONFIG_P2P + RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bShowGetP2PState = extra_arg; +#endif /* CONFIG_P2P */ + break; + } +#ifdef CONFIG_GPIO_API + case 0x25: { /* Get GPIO register */ + /* + * dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7 + */ - plist = get_next(plist); - - } - - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - if (!blnMatch) - sprintf(attr_content_str, "\n\nM=0000"); - - wrqu->data.length = strlen(attr_content_str); - _rtw_memcpy(extra, attr_content_str, wrqu->data.length); - - return ret; - -} + u8 value; + RTW_INFO("Read GPIO Value extra_arg = %d\n", extra_arg); + value = rtw_hal_get_gpio(padapter, extra_arg); + RTW_INFO("Read GPIO Value = %d\n", value); + break; + } + case 0x26: { /* Set GPIO direction */ -#ifdef CONFIG_WFD -static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + /* dbg 0x7f26000x [y], Set gpio direction, + * x: gpio_num,4~7 y: indicate direction, 0~1 + */ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + int value; + RTW_INFO("Set GPIO Direction! arg = %d ,extra_arg=%d\n", arg , extra_arg); + value = rtw_hal_config_gpio(padapter, arg, extra_arg); + RTW_INFO("Set GPIO Direction %s\n", (value == -1) ? "Fail!!!" : "Success"); + break; + } + case 0x27: { /* Set GPIO output direction value */ + /* + * dbg 0x7f27000x [y], Set gpio output direction value, + * x: gpio_num,4~7 y: indicate direction, 0~1 + */ - RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); + int value; + RTW_INFO("Set GPIO Value! arg = %d ,extra_arg=%d\n", arg , extra_arg); + value = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg); + RTW_INFO("Set GPIO Value %s\n", (value == -1) ? "Fail!!!" : "Success"); + break; + } +#endif +#ifdef DBG_CMD_QUEUE + case 0x28: { + dump_cmd_id = extra_arg; + RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id); + } + break; +#endif /* DBG_CMD_QUEUE */ + case 0xaa: { + if ((extra_arg & 0x7F) > 0x3F) + extra_arg = 0xFF; + RTW_INFO("chang data rate to :0x%02x\n", extra_arg); + padapter->fix_rate = extra_arg; + } + break; + case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */ + if (extra_arg == 0) + mac_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 1) + bb_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 2) + rf_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 11) + bb_reg_dump_ex(RTW_DBGDUMP, padapter); + } + break; - sprintf(extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport); - RTW_INFO("[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport); + case 0xee: { + RTW_INFO(" === please control /proc to trun on/off PHYDM func ===\n"); + } + break; - wrqu->data.length = strlen(extra); - return ret; + case 0xfd: + rtw_write8(padapter, 0xc50, arg); + RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + rtw_write8(padapter, 0xc58, arg); + RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xfe: + RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xff: { + RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); + RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); + RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); + RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); + RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); -} + RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); -static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + RTW_INFO("\n"); - sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc); - RTW_INFO("[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc); + RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); + RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); - wrqu->data.length = strlen(extra); - pwdinfo->wfd_info->wfd_pc = _FALSE; /* Reset the WFD preferred connection to P2P */ - return ret; + RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); -} + RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); -static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); + RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); + RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); + RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); + RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); + } + break; + } + break; + default: + RTW_INFO("error dbg cmd!\n"); + break; + } - sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail); - RTW_INFO("[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail); - wrqu->data.length = strlen(extra); - pwdinfo->wfd_info->peer_session_avail = _TRUE; /* Reset the WFD session available */ return ret; } -#endif /* CONFIG_WFD */ +#endif -static int rtw_p2p_get_go_device_address(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) +static int wpa_set_param(struct net_device *dev, u8 name, u32 value) { - - int ret = 0; + uint ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 blnMatch = 0; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - u8 attr_content[100] = { 0x00 }; - u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; - /* Commented by Albert 20121209 */ - /* The input data is the GO's interface address which the application wants to know its device address. */ - /* Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */ + switch (name) { + case IEEE_PARAM_WPA_ENABLED: - RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */ - macstr2num(peerMAC, subcmd); + /* ret = ieee80211_wpa_enable(ieee, value); */ - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + switch ((value) & 0xff) { + case 1: /* WPA */ + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */ + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case 2: /* WPA2 */ + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */ + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + } - phead = get_list_head(queue); - plist = get_next(phead); - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + break; - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - /* Commented by Albert 2011/05/18 */ - /* Match the device address located in the P2P IE */ - /* This is for the case that the P2P device address is not the same as the P2P interface address. */ - - p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); - if (p2pie) { - while (p2pie) { - /* The P2P Device ID attribute is included in the Beacon frame. */ - /* The P2P Device Info attribute is included in the probe response frame. */ - - _rtw_memset(attr_content, 0x00, 100); - if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { - /* Handle the P2P Device ID attribute of Beacon first */ - blnMatch = 1; - break; + case IEEE_PARAM_TKIP_COUNTERMEASURES: + /* ieee->tkip_countermeasures=value; */ + break; - } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { - /* Handle the P2P Device Info attribute of probe response */ - blnMatch = 1; - break; - } + case IEEE_PARAM_DROP_UNENCRYPTED: { + /* HACK: + * + * wpa_supplicant calls set_wpa_enabled when the driver + * is loaded and unloaded, regardless of if WPA is being + * used. No other calls are made which can be used to + * determine if encryption will be used or not prior to + * association being expected. If encryption is not being + * used, drop_unencrypted is set to false, else true -- we + * can use this to determine if the CAP_PRIVACY_ON bit should + * be set. + */ - /* Get the next P2P IE */ - p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); - } - } +#if 0 + struct ieee80211_security sec = { + .flags = SEC_ENABLED, + .enabled = value, + }; + ieee->drop_unencrypted = value; + /* We only change SEC_LEVEL for open mode. Others + * are set by ipw_wpa_set_encryption. + */ + if (!value) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_0; + } else { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; } - - plist = get_next(plist); + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); +#endif + break; } + case IEEE_PARAM_PRIVACY_INVOKED: - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - if (!blnMatch) - sprintf(go_devadd_str, "\n\ndev_add=NULL"); - else { - sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); - } + /* ieee->privacy_invoked=value; */ - wrqu->data.length = strlen(go_devadd_str); - _rtw_memcpy(extra, go_devadd_str, wrqu->data.length); + break; - return ret; + case IEEE_PARAM_AUTH_ALGS: -} + ret = wpa_set_auth_algs(dev, value); -static int rtw_p2p_get_device_type(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) -{ + break; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 blnMatch = 0; - u8 dev_type[8] = { 0x00 }; - uint dev_type_len = 0; - u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; /* +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer */ + case IEEE_PARAM_IEEE_802_1X: - /* Commented by Albert 20121209 */ - /* The input data is the MAC address which the application wants to know its device type. */ - /* Such user interface could know the device type. */ - /* Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */ + /* ieee->ieee802_1x=value; */ - RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + break; - macstr2num(peerMAC, subcmd); + case IEEE_PARAM_WPAX_SELECT: - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* added for WPA2 mixed mode */ + /*RTW_WARN("------------------------>wpax value = %x\n", value);*/ + /* + spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); + ieee->wpax_type_set = 1; + ieee->wpax_type_notify = value; + spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); + */ - phead = get_list_head(queue); - plist = get_next(phead); + break; - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + default: - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - u8 *wpsie; - uint wpsie_len = 0; - - /* The mac address is matched. */ - - wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); - if (wpsie) { - rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len); - if (dev_type_len) { - u16 type = 0; - - _rtw_memcpy(&type, dev_type, 2); - type = be16_to_cpu(type); - sprintf(dev_type_str, "\n\nN=%.2d", type); - blnMatch = 1; - } - } - break; - } - plist = get_next(plist); - } + ret = -EOPNOTSUPP; - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - if (!blnMatch) - sprintf(dev_type_str, "\n\nN=00"); + break; - wrqu->data.length = strlen(dev_type_str); - _rtw_memcpy(extra, dev_type_str, wrqu->data.length); + } return ret; } -static int rtw_p2p_get_device_name(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) +static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) { - int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 blnMatch = 0; - u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 }; - uint dev_len = 0; - u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; - - /* Commented by Albert 20121225 */ - /* The input data is the MAC address which the application wants to know its device name. */ - /* Such user interface could show peer device's device name instead of ssid. */ - /* Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */ - RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); - - macstr2num(peerMAC, subcmd); + switch (command) { + case IEEE_MLME_STA_DEAUTH: - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; - phead = get_list_head(queue); - plist = get_next(phead); + break; - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + case IEEE_MLME_STA_DISASSOC: - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - u8 *wpsie; - uint wpsie_len = 0; - - /* The mac address is matched. */ - - wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); - if (wpsie) { - rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len); - if (dev_len) { - sprintf(dev_name_str, "\n\nN=%s", dev_name); - blnMatch = 1; - } - } - break; - } + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; - plist = get_next(plist); + break; + default: + ret = -EOPNOTSUPP; + break; } - - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - if (!blnMatch) - sprintf(dev_name_str, "\n\nN=0000"); - - wrqu->data.length = strlen(dev_name_str); - _rtw_memcpy(extra, dev_name_str, wrqu->data.length); - return ret; } -static int rtw_p2p_get_invitation_procedure(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) +static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) { + struct ieee_param *param; + uint ret = 0; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 blnMatch = 0; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - u8 attr_content[2] = { 0x00 }; - u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; - - /* Commented by Ouden 20121226 */ - /* The application wants to know P2P initation procedure is support or not. */ - /* Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */ - - RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); - - macstr2num(peerMAC, subcmd); - - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - phead = get_list_head(queue); - plist = get_next(phead); - - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; - - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - /* Commented by Albert 20121226 */ - /* Match the device address located in the P2P IE */ - /* This is for the case that the P2P device address is not the same as the P2P interface address. */ - - p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); - if (p2pie) { - while (p2pie) { - /* _rtw_memset( attr_content, 0x00, 2); */ - if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) { - /* Handle the P2P capability attribute */ - blnMatch = 1; - break; - - } - - /* Get the next P2P IE */ - p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); - } - } - } - - plist = get_next(plist); + /* down(&ieee->wx_sem); */ + if (p->length < sizeof(struct ieee_param) || !p->pointer) { + ret = -EINVAL; + goto out; } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - if (!blnMatch) - sprintf(inv_proc_str, "\nIP=-1"); - else { - if ((attr_content[0] & 0x20) == 0x20) - sprintf(inv_proc_str, "\nIP=1"); - else - sprintf(inv_proc_str, "\nIP=0"); + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) { + ret = -ENOMEM; + goto out; } - wrqu->data.length = strlen(inv_proc_str); - _rtw_memcpy(extra, inv_proc_str, wrqu->data.length); - - return ret; - -} - -static int rtw_p2p_connect(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - int jj, kk; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _irqL irqL; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - uint uintPeerChannel = 0; -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; -#endif - - /* Commented by Albert 20110304 */ - /* The input data contains two informations. */ - /* 1. First information is the MAC address which wants to formate with */ - /* 2. Second information is the WPS PINCode or "pbc" string for push button method */ - /* Format: 00:E0:4C:00:00:05 */ - /* Format: 00:E0:4C:00:00:05 */ - - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); - - if (pwdinfo->p2p_state == P2P_STATE_NONE) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; + if (copy_from_user(param, p->pointer, p->length)) { + rtw_mfree((u8 *)param, p->length); + ret = -EFAULT; + goto out; } - if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) - return -1; - - for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) - peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); + switch (param->cmd) { - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + case IEEE_CMD_SET_WPA_PARAM: + ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); + break; - phead = get_list_head(queue); - plist = get_next(phead); + case IEEE_CMD_SET_WPA_IE: + /* ret = wpa_set_wpa_ie(dev, param, p->length); */ + ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); + break; - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + case IEEE_CMD_SET_ENCRYPTION: + ret = wpa_set_encryption(dev, param, p->length); + break; - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { - if (pnetwork->network.Configuration.DSConfig != 0) - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - else if (pwdinfo->nego_req_info.peer_ch != 0) - uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch; - else { - /* Unexpected case */ - uintPeerChannel = 0; - RTW_INFO("%s uintPeerChannel = 0\n", __func__); - } - break; - } + case IEEE_CMD_MLME: + ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); + break; - plist = get_next(plist); + default: + RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - - if (uintPeerChannel) { -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); -#endif /* CONFIG_CONCURRENT_MODE */ - - _rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info)); - _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); - - pwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel; - _rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN); - pwdinfo->nego_req_info.benable = _TRUE; - - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - if (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) { - /* Restore to the listen state if the current p2p state is not nego OK */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); - } - - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); - -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 union_bw = rtw_mi_get_union_bw(padapter); - u8 union_offset = rtw_mi_get_union_offset(padapter); + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_leave_opch(padapter); - } -#endif /* CONFIG_CONCURRENT_MODE */ + rtw_mfree((u8 *)param, p->length); - RTW_INFO("[%s] Start PreTx Procedure!\n", __FUNCTION__); - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT); - else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT); -#else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT); -#endif /* CONFIG_CONCURRENT_MODE */ +out: - } else { - RTW_INFO("[%s] Not Found in Scanning Queue~\n", __FUNCTION__); - ret = -1; - } + /* up(&ieee->wx_sem); */ return ret; + } -static int rtw_p2p_invite_req(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +#ifdef CONFIG_AP_MODE +static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - int jj, kk; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - uint uintPeerChannel = 0; - u8 attr_content[50] = { 0x00 }; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - _irqL irqL; - struct tx_invite_req_info *pinvite_req_info = &pwdinfo->invitereq_info; -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; -#endif + u32 wep_key_idx, wep_key_len, wep_total_len = 0; + NDIS_802_11_WEP *pwep = NULL; + struct sta_info *psta = NULL, *pbcmc_sta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct sta_priv *pstapriv = &padapter->stapriv; - /* Commented by Albert 20120321 */ - /* The input data contains two informations. */ - /* 1. First information is the P2P device address which you want to send to. */ - /* 2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */ - /* Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" */ - /* Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */ + RTW_INFO("%s\n", __FUNCTION__); - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - if (wrqu->data.length <= 37) { - RTW_INFO("[%s] Wrong format!\n", __FUNCTION__); - return ret; + /* sizeof(struct ieee_param) = 64 bytes; */ + /* if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */ + if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) { + ret = -EINVAL; + goto exit; } - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (param->u.crypt.idx >= WEP_KEYS +#ifdef CONFIG_IEEE80211W + && param->u.crypt.idx > BIP_MAX_KEYID +#endif /* CONFIG_IEEE80211W */ + ) { + ret = -EINVAL; + goto exit; + } } else { - /* Reset the content of struct tx_invite_req_info */ - pinvite_req_info->benable = _FALSE; - _rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN); - _rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN); - pinvite_req_info->ssidlen = 0x00; - pinvite_req_info->operating_ch = pwdinfo->operating_channel; - _rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN); - pinvite_req_info->token = 3; + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (!psta) { + /* ret = -EINVAL; */ + RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n"); + goto exit; + } } - for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) - pinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]); + if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) { + /* todo:clear default encryption keys */ - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - phead = get_list_head(queue); - plist = get_next(phead); + RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + goto exit; + } - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - /* Commented by Albert 2011/05/18 */ - /* Match the device address located in the P2P IE */ - /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) { + RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n"); - p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); - if (p2pie) { - /* The P2P Device ID attribute is included in the Beacon frame. */ - /* The P2P Device Info attribute is included in the probe response frame. */ + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; - if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { - /* Handle the P2P Device ID attribute of Beacon first */ - if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; - } - } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { - /* Handle the P2P Device Info attribute of probe response */ - if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; - } - } + RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { + ret = -EINVAL; + goto exit; } - plist = get_next(plist); - - } - - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); -#ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) { - struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; - u8 *wfd_ie; - uint wfd_ielen = 0; - - wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); - if (wfd_ie) { - u8 *wfd_devinfo; - uint wfd_devlen; - - RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); - wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); - if (wfd_devinfo) { - u16 wfd_devinfo_field = 0; - - /* Commented by Albert 20120319 */ - /* The first two bytes are the WFD device information field of WFD device information subelement. */ - /* In big endian format. */ - wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); - if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL) - pwfd_info->peer_session_avail = _TRUE; - else - pwfd_info->peer_session_avail = _FALSE; + if (wep_key_len > 0) { + wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len); + if (pwep == NULL) { + RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n"); + goto exit; } - } - if (_FALSE == pwfd_info->peer_session_avail) { - RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__); - goto exit; - } - } -#endif /* CONFIG_WFD */ + _rtw_memset(pwep, 0, wep_total_len); - if (uintPeerChannel) { -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); -#endif /* CONFIG_CONCURRENT_MODE */ + pwep->KeyLength = wep_key_len; + pwep->Length = wep_total_len; - /* Store the GO's bssid */ - for (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3) - pinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]); + } - /* Store the GO's ssid */ - pinvite_req_info->ssidlen = wrqu->data.length - 36; - _rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen); - pinvite_req_info->benable = _TRUE; - pinvite_req_info->peer_ch = uintPeerChannel; + pwep->KeyIndex = wep_key_idx; - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ); + _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 union_bw = rtw_mi_get_union_bw(padapter); - u8 union_offset = rtw_mi_get_union_offset(padapter); + if (param->u.crypt.set_tx) { + RTW_INFO("wep, set_tx=1\n"); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_leave_opch(padapter); + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - } else - set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#else - set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#endif/*CONFIG_CONCURRENT_MODE*/ + if (pwep->KeyLength == 13) { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT); - else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT); -#else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT); -#endif /* CONFIG_CONCURRENT_MODE */ + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); - } else - RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); -exit: + psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; - return ret; + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1); + } else { + RTW_INFO("wep, set_tx=0\n"); -} + /* don't update "psecuritypriv->dot11PrivacyAlgrthm" and */ + /* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */ -static int rtw_p2p_set_persistent(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; - /* Commented by Albert 20120328 */ - /* The input data is 0 or 1 */ - /* 0: disable persistent group functionality */ - /* 1: enable persistent group founctionality */ + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0); + } - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + goto exit; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; - } else { - if (extra[0] == '0') /* Disable the persistent group function. */ - pwdinfo->persistent_supported = _FALSE; - else if (extra[0] == '1') /* Enable the persistent group function. */ - pwdinfo->persistent_supported = _TRUE; - else - pwdinfo->persistent_supported = _FALSE; } - printk("[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported); - - return ret; -} -static int uuid_str2bin(const char *str, u8 *bin) -{ - const char *pos; - u8 *opos; + if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ + if (param->u.crypt.set_tx == 1) { + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - pos = str; - opos = bin; - - if (hexstr2bin(pos, opos, 4)) - return -1; - pos += 8; - opos += 4; - - if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) - return -1; - pos += 4; - opos += 2; - - if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) - return -1; - pos += 4; - opos += 2; + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + /* set mic key */ + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + psecuritypriv->busetkipkey = _TRUE; - if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) - return -1; - pos += 4; - opos += 2; + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); + psecuritypriv->dot118021XGrpPrivacy = _AES_; + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - if (*pos++ != '-' || hexstr2bin(pos, opos, 6)) - return -1; + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); + _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; + goto exit; + #endif /* CONFIG_IEEE80211W */ - return 0; -} + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" + , FUNC_ADPT_ARG(padapter)); + goto exit; + } -static int rtw_p2p_set_wps_uuid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + if (pbcmc_sta) { + pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ + } + psecuritypriv->binstallGrpkey = _TRUE; + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + } - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + goto exit; - if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0)) - pwdinfo->external_uuid = 1; - else { - pwdinfo->external_uuid = 0; - ret = -EINVAL; } - return ret; - -} -#ifdef CONFIG_WFD -static int rtw_p2p_set_pc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - int jj, kk; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - u8 attr_content[50] = { 0x00 }; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - _irqL irqL; - uint uintPeerChannel = 0; - - struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; - - /* Commented by Albert 20120512 */ - /* 1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */ - /* Format: 00:E0:4C:00:00:05 */ + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (param->u.crypt.set_tx == 1) { + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psta->dot118021XPrivacy = _WEP104_; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; - } + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _TKIP_; + /* set mic key */ + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + psecuritypriv->busetkipkey = _TRUE; - for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) - peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _AES_; - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr) + , param->u.crypt.idx); + psta->dot118021XPrivacy = _NO_PRIVACY_; - phead = get_list_head(queue); - plist = get_next(phead); + } else { + RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); + goto exit; + } - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->ieee8021x_blocked = _FALSE; - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (psta->dot118021XPrivacy != _NO_PRIVACY_) { + psta->bpairwise_key_installed = _TRUE; - /* Commented by Albert 2011/05/18 */ - /* Match the device address located in the P2P IE */ - /* This is for the case that the P2P device address is not the same as the P2P interface address. */ - - p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); - if (p2pie) { - /* The P2P Device ID attribute is included in the Beacon frame. */ - /* The P2P Device Info attribute is included in the probe response frame. */ - printk("[%s] Got P2P IE\n", __FUNCTION__); - if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { - /* Handle the P2P Device ID attribute of Beacon first */ - printk("[%s] P2P_ATTR_DEVICE_ID\n", __FUNCTION__); - if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; - } - } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { - /* Handle the P2P Device Info attribute of probe response */ - printk("[%s] P2P_ATTR_DEVICE_INFO\n", __FUNCTION__); - if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; + /* WPA2 key-handshake has completed */ + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); } + + rtw_ap_set_pairwise_key(padapter, psta); + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->phl_sta->mac_addr)); + goto exit; } } - plist = get_next(plist); - } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - printk("[%s] channel = %d\n", __FUNCTION__, uintPeerChannel); - - if (uintPeerChannel) { - u8 *wfd_ie; - uint wfd_ielen = 0; - - wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); - if (wfd_ie) { - u8 *wfd_devinfo; - uint wfd_devlen; - - RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); - wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); - if (wfd_devinfo) { - u16 wfd_devinfo_field = 0; +exit: - /* Commented by Albert 20120319 */ - /* The first two bytes are the WFD device information field of WFD device information subelement. */ - /* In big endian format. */ - wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); - if (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS) - pwfd_info->wfd_pc = _TRUE; - else - pwfd_info->wfd_pc = _FALSE; - } - } - } else - RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); + if (pwep) + rtw_mfree((u8 *)pwep, wep_total_len); return ret; } -static int rtw_p2p_set_wfd_device_type(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; - - /* Commented by Albert 20120328 */ - /* The input data is 0 or 1 */ - /* 0: specify to Miracast source device */ - /* 1 or others: specify to Miracast sink device (display device) */ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + unsigned char *pbuf = param->u.bcn_ie.buf; - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); - if (extra[0] == '0') /* Set to Miracast source device. */ - pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE; - else /* Set to Miracast sink device. */ - pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - return ret; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; -} + _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); -static int rtw_p2p_set_wfd_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - /* Commented by Kurt 20121206 - * This function is used to set wfd enabled */ + if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0)) + pstapriv->max_num_sta = NUM_STA; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - if (*extra == '0') - rtw_wfd_enable(padapter, 0); - else if (*extra == '1') - rtw_wfd_enable(padapter, 1); + if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */ + ret = 0; + else + ret = -EINVAL; - RTW_INFO("[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable); return ret; } -static int rtw_p2p_set_driver_iface(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_hostapd_sta_flush(struct net_device *dev) { - /* Commented by Kurt 20121206 - * This function is used to set driver iface is WEXT or CFG80211 */ + /* _list *phead, *plist; */ int ret = 0; + /* struct sta_info *psta = NULL; */ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + /* struct sta_priv *pstapriv = &padapter->stapriv; */ - if (*extra == '1') { - pwdinfo->driver_interface = DRIVER_WEXT; - RTW_INFO("[%s] driver_interface = WEXT\n", __FUNCTION__); - } else if (*extra == '2') { - pwdinfo->driver_interface = DRIVER_CFG80211; - RTW_INFO("[%s] driver_interface = CFG80211\n", __FUNCTION__); - } + RTW_INFO("%s\n", __FUNCTION__); + flush_all_cam_entry(padapter, PHL_CMD_WAIT, 50); /* clear CAM */ +#ifdef CONFIG_AP_MODE + ret = rtw_sta_flush(padapter, _TRUE); +#endif return ret; } -/* To set the WFD session available to enable or disable */ -static int rtw_p2p_set_sa(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); - if (0) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; - } else { - if (extra[0] == '0') /* Disable the session available. */ - pwdinfo->session_available = _FALSE; - else if (extra[0] == '1') /* Enable the session available. */ - pwdinfo->session_available = _TRUE; - else - pwdinfo->session_available = _FALSE; - } - printk("[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available); + if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; - return ret; + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; -} -#endif /* CONFIG_WFD */ +#if 0 + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + RTW_INFO("rtw_add_sta(), free has been added psta=%p\n", psta); + /* _rtw_spinlock_bh(&(pstapriv->sta_hash_lock)); */ + rtw_free_stainfo(padapter, psta); + /* _rtw_spinunlock_bh(&(pstapriv->sta_hash_lock)); */ -static int rtw_p2p_prov_disc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - u8 peerMAC[ETH_ALEN] = { 0x00 }; - int jj, kk; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - uint uintPeerChannel = 0; - u8 attr_content[100] = { 0x00 }; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - _irqL irqL; -#ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; + psta = NULL; + } #endif + /* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */ + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + int flags = param->u.add_sta.flags; - /* Commented by Albert 20110301 */ - /* The input data contains two informations. */ - /* 1. First information is the MAC address which wants to issue the provisioning discovery request frame. */ - /* 2. Second information is the WPS configuration method which wants to discovery */ - /* Format: 00:E0:4C:00:00:05_display */ - /* Format: 00:E0:4C:00:00:05_keypad */ - /* Format: 00:E0:4C:00:00:05_pbc */ - /* Format: 00:E0:4C:00:00:05_label */ + /* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */ - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + psta->phl_sta->aid = param->u.add_sta.aid;/* aid=1~2007 */ - if (pwdinfo->p2p_state == P2P_STATE_NONE) { - RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); - return ret; - } else { - /* Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */ - _rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN); - _rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN); - _rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID)); - pwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0; - pwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0; - pwdinfo->tx_prov_disc_info.benable = _FALSE; - } - - for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) - peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); - - if (_rtw_memcmp(&extra[18], "display", 7)) - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; - else if (_rtw_memcmp(&extra[18], "keypad", 7)) - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; - else if (_rtw_memcmp(&extra[18], "pbc", 3)) - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; - else if (_rtw_memcmp(&extra[18], "label", 5)) - pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; - else { - RTW_INFO("[%s] Unknown WPS config methodn", __FUNCTION__); - return ret ; - } + _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - phead = get_list_head(queue); - plist = get_next(phead); + /* check wmm cap. */ + if (WLAN_STA_WME & flags) + psta->qos_option = 1; + else + psta->qos_option = 0; - while (1) { - if (rtw_end_of_queue_search(phead, plist) == _TRUE) - break; + if (pmlmepriv->qospriv.qos_option == 0) + psta->qos_option = 0; - if (uintPeerChannel != 0) - break; - pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); +#ifdef CONFIG_80211N_HT + /* chec 802.11n ht cap. */ + if (padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode) && + (WLAN_STA_HT & flags)) { + psta->htpriv.ht_option = _TRUE; + psta->qos_option = 1; + _rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); + } else + psta->htpriv.ht_option = _FALSE; - /* Commented by Albert 2011/05/18 */ - /* Match the device address located in the P2P IE */ - /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + if (pmlmepriv->htpriv.ht_option == _FALSE) + psta->htpriv.ht_option = _FALSE; - p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); - if (p2pie) { - while (p2pie) { - /* The P2P Device ID attribute is included in the Beacon frame. */ - /* The P2P Device Info attribute is included in the probe response frame. */ +#endif - if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { - /* Handle the P2P Device ID attribute of Beacon first */ - if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; - } - } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { - /* Handle the P2P Device Info attribute of probe response */ - if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { - uintPeerChannel = pnetwork->network.Configuration.DSConfig; - break; - } - } - /* Get the next P2P IE */ - p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); - } + update_sta_info_apmode(padapter, psta); - } - plist = get_next(plist); + } else + ret = -ENOMEM; - } + return ret; - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); +} - if (uintPeerChannel) { -#ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { - struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; - u8 *wfd_ie; - uint wfd_ielen = 0; - - wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); - if (wfd_ie) { - u8 *wfd_devinfo; - uint wfd_devlen; - - RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); - wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); - if (wfd_devinfo) { - u16 wfd_devinfo_field = 0; - - /* Commented by Albert 20120319 */ - /* The first two bytes are the WFD device information field of WFD device information subelement. */ - /* In big endian format. */ - wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); - if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL) - pwfd_info->peer_session_avail = _TRUE; - else - pwfd_info->peer_session_avail = _FALSE; - } - } +static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) +{ + int ret = 0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; - if (_FALSE == pwfd_info->peer_session_avail) { - RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__); - goto exit; - } - } -#endif /* CONFIG_WFD */ + RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); - RTW_INFO("[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); -#endif /* CONFIG_CONCURRENT_MODE */ - _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN); - _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN); - pwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel; - pwdinfo->tx_prov_disc_info.benable = _TRUE; - rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ); - - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) - _rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID)); - else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - _rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); - pwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN; - } + if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 union_bw = rtw_mi_get_union_bw(padapter); - u8 union_offset = rtw_mi_get_union_offset(padapter); + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_leave_opch(padapter); + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + u8 updated = _FALSE; - } else - set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#else - set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#endif + /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->phl_sta->aid); */ - _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + _rtw_spinlock_bh(&pstapriv->asoc_list_lock); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + #ifdef CONFIG_RTW_TOKEN_BASED_XMIT + if (psta->tbtx_enable) + pstapriv->tbtx_asoc_list_cnt--; + #endif + updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE, _FALSE); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT); - else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); -#else - _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); -#endif /* CONFIG_CONCURRENT_MODE */ + } + _rtw_spinunlock_bh(&pstapriv->asoc_list_lock); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + + psta = NULL; } else { - RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); + RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n"); + + /* ret = -1; */ } -exit: + return ret; } -/* Added by Albert 20110328 - * This function is used to inform the driver the user had specified the pin code value or pbc - * to application. */ - -static int rtw_p2p_got_wpsinfo(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) { - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - - - RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); - /* Added by Albert 20110328 */ - /* if the input data is P2P_NO_WPSINFO -> reset the wpsinfo */ - /* if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */ - /* if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */ - /* if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */ - - if (*extra == '0') - pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; - else if (*extra == '1') - pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN; - else if (*extra == '2') - pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN; - else if (*extra == '3') - pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC; - else - pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; + struct sta_data *psta_data = (struct sta_data *)param_ex->data; - return ret; + RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr)); -} + if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; -#endif /* CONFIG_P2P */ + if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && + param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && + param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) + return -EINVAL; -static int rtw_p2p_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; -#ifdef CONFIG_P2P - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); + if (psta) { +#if 0 + struct { + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct rtw_ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; + } get_sta; +#endif + psta_data->aid = (u16)psta->phl_sta->aid; + psta_data->capability = psta->capability; + psta_data->flags = psta->flags; - RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); + /* + nonerp_set : BIT(0) + no_short_slot_time_set : BIT(1) + no_short_preamble_set : BIT(2) + no_ht_gf_set : BIT(3) + no_ht_set : BIT(4) + ht_20mhz_set : BIT(5) + */ - if (_rtw_memcmp(extra, "enable=", 7)) - rtw_wext_p2p_enable(dev, info, wrqu, &extra[7]); - else if (_rtw_memcmp(extra, "setDN=", 6)) { - wrqu->data.length -= 6; - rtw_p2p_setDN(dev, info, wrqu, &extra[6]); - } else if (_rtw_memcmp(extra, "profilefound=", 13)) { - wrqu->data.length -= 13; - rtw_p2p_profilefound(dev, info, wrqu, &extra[13]); - } else if (_rtw_memcmp(extra, "prov_disc=", 10)) { - wrqu->data.length -= 10; - rtw_p2p_prov_disc(dev, info, wrqu, &extra[10]); - } else if (_rtw_memcmp(extra, "nego=", 5)) { - wrqu->data.length -= 5; - rtw_p2p_connect(dev, info, wrqu, &extra[5]); - } else if (_rtw_memcmp(extra, "intent=", 7)) { - /* Commented by Albert 2011/03/23 */ - /* The wrqu->data.length will include the null character */ - /* So, we will decrease 7 + 1 */ - wrqu->data.length -= 8; - rtw_p2p_set_intent(dev, info, wrqu, &extra[7]); - } else if (_rtw_memcmp(extra, "ssid=", 5)) { - wrqu->data.length -= 5; - rtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]); - } else if (_rtw_memcmp(extra, "got_wpsinfo=", 12)) { - wrqu->data.length -= 12; - rtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]); - } else if (_rtw_memcmp(extra, "listen_ch=", 10)) { - /* Commented by Albert 2011/05/24 */ - /* The wrqu->data.length will include the null character */ - /* So, we will decrease (10 + 1) */ - wrqu->data.length -= 11; - rtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]); - } else if (_rtw_memcmp(extra, "op_ch=", 6)) { - /* Commented by Albert 2011/05/24 */ - /* The wrqu->data.length will include the null character */ - /* So, we will decrease (6 + 1) */ - wrqu->data.length -= 7; - rtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]); - } else if (_rtw_memcmp(extra, "invite=", 7)) { - wrqu->data.length -= 8; - rtw_p2p_invite_req(dev, info, wrqu, &extra[7]); - } else if (_rtw_memcmp(extra, "persistent=", 11)) { - wrqu->data.length -= 11; - rtw_p2p_set_persistent(dev, info, wrqu, &extra[11]); - } else if (_rtw_memcmp(extra, "uuid=", 5)) { - wrqu->data.length -= 5; - ret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]); - } + psta_data->sta_set = ((psta->nonerp_set) | + (psta->no_short_slot_time_set << 1) | + (psta->no_short_preamble_set << 2) | + (psta->no_ht_gf_set << 3) | + (psta->no_ht_set << 4) | + (psta->ht_20mhz_set << 5)); -#ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { - if (_rtw_memcmp(extra, "sa=", 3)) { - /* sa: WFD Session Available information */ - wrqu->data.length -= 3; - rtw_p2p_set_sa(dev, info, wrqu, &extra[3]); - } else if (_rtw_memcmp(extra, "pc=", 3)) { - /* pc: WFD Preferred Connection */ - wrqu->data.length -= 3; - rtw_p2p_set_pc(dev, info, wrqu, &extra[3]); - } else if (_rtw_memcmp(extra, "wfd_type=", 9)) { - wrqu->data.length -= 9; - rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]); - } else if (_rtw_memcmp(extra, "wfd_enable=", 11)) { - wrqu->data.length -= 11; - rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]); - } else if (_rtw_memcmp(extra, "driver_iface=", 13)) { - wrqu->data.length -= 13; - rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]); - } - } -#endif /* CONFIG_WFD */ + psta_data->tx_supp_rates_len = psta->bssratelen; + _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); +#ifdef CONFIG_80211N_HT + if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) + _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); +#endif /* CONFIG_80211N_HT */ + psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; + psta_data->rx_bytes = psta->sta_stats.rx_bytes; + psta_data->rx_drops = psta->sta_stats.rx_drops; -#endif /* CONFIG_P2P */ + psta_data->tx_pkts = psta->sta_stats.tx_pkts; + psta_data->tx_bytes = psta->sta_stats.tx_bytes; + psta_data->tx_drops = psta->sta_stats.tx_drops; + + + } else + ret = -1; return ret; } -static int rtw_p2p_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) { int ret = 0; -#ifdef CONFIG_P2P + struct sta_info *psta = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; - if (padapter->bShowGetP2PState) - RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer); - - if (_rtw_memcmp(wrqu->data.pointer, "status", 6)) - rtw_p2p_get_status(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "role", 4)) - rtw_p2p_get_role(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "peer_ifa", 8)) - rtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "req_cm", 6)) - rtw_p2p_get_req_cm(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "peer_deva", 9)) { - /* Get the P2P device address when receiving the provision discovery request frame. */ - rtw_p2p_get_peer_devaddr(dev, info, wrqu, extra); - } else if (_rtw_memcmp(wrqu->data.pointer, "group_id", 8)) - rtw_p2p_get_groupid(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "inv_peer_deva", 13)) { - /* Get the P2P device address when receiving the P2P Invitation request frame. */ - rtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra); - } else if (_rtw_memcmp(wrqu->data.pointer, "op_ch", 5)) - rtw_p2p_get_op_ch(dev, info, wrqu, extra); + RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); -#ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { - if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9)) - rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6)) - rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra); - else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6)) - rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra); - } -#endif /* CONFIG_WFD */ + if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; -#endif /* CONFIG_P2P */ + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) { + int wpa_ie_len; + int copy_len; + + wpa_ie_len = psta->wpa_ie[1]; + + copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2); + + param->u.wpa_ie.len = copy_len; + + _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); + } else { + /* ret = -1; */ + RTW_INFO("sta's wpa_ie is NONE\n"); + } + } else + ret = -1; return ret; } -static int rtw_p2p_get2(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) { - int ret = 0; + unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + int ie_len; -#ifdef CONFIG_P2P + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - int length = wrqu->data.length; - char *buffer = (u8 *)rtw_malloc(length); + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - if (buffer == NULL) { - ret = -ENOMEM; - goto bad; - } + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) { - ret = -EFAULT; - goto bad; + + if (pmlmepriv->wps_beacon_ie) { + rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); + pmlmepriv->wps_beacon_ie = NULL; } - RTW_INFO("[%s] buffer = %s\n", __FUNCTION__, buffer); + if (ie_len > 0) { + pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); + pmlmepriv->wps_beacon_ie_len = ie_len; + if (pmlmepriv->wps_beacon_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } - if (_rtw_memcmp(buffer, "wpsCM=", 6)) - ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]); - else if (_rtw_memcmp(buffer, "devN=", 5)) - ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]); - else if (_rtw_memcmp(buffer, "dev_type=", 9)) - ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]); - else if (_rtw_memcmp(buffer, "go_devadd=", 10)) - ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]); - else if (_rtw_memcmp(buffer, "InvProc=", 8)) - ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]); - else { - snprintf(extra, sizeof("Command not found."), "Command not found."); - wrqu->data.length = strlen(extra); - } + _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); -bad: - if (buffer) - rtw_mfree(buffer, length); + rtw_update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, 0); + + pmlmeext->bstart_bss = _TRUE; + + } -#endif /* CONFIG_P2P */ return ret; } -#ifdef CONFIG_MP_INCLUDED -static int rtw_cta_test_start(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) { int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ie_len; - RTW_INFO("%s %s\n", __func__, extra); - if (!strcmp(extra, "1")) - hal_data->in_cta_test = 1; - else - hal_data->in_cta_test = 0; + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE); + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - return ret; -} -#endif + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ -#ifdef CONFIG_IOL -#include -#endif -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR -#include "../../hal/hal_dm_acs.h" -#endif -#ifdef DBG_CMD_QUEUE -u8 dump_cmd_id = 0; -#endif -static int rtw_dbg_port(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + if (pmlmepriv->wps_probe_resp_ie) { + rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); + pmlmepriv->wps_probe_resp_ie = NULL; + } + + if (ie_len > 0) { + pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_probe_resp_ie_len = ie_len; + if (pmlmepriv->wps_probe_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); + } + + + return ret; + +} + +static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) { int ret = 0; -#ifdef CONFIG_RTW_DEBUG - _irqL irqL; - u8 major_cmd, minor_cmd; - u16 arg; - u32 extra_arg, *pdata, val32; - struct sta_info *psta; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct security_priv *psecuritypriv = &padapter->securitypriv; - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct sta_priv *pstapriv = &padapter->stapriv; + int ie_len; + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - pdata = (u32 *)&wrqu->data; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - val32 = *pdata; - arg = (u16)(val32 & 0x0000ffff); - major_cmd = (u8)(val32 >> 24); - minor_cmd = (u8)((val32 >> 16) & 0x00ff); + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - extra_arg = *(pdata + 1); - switch (major_cmd) { - case 0x70: /* read_reg */ - switch (minor_cmd) { - case 1: - RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); - break; - case 2: - RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); - break; - case 4: - RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); - break; - } - break; - case 0x71: /* write_reg */ - switch (minor_cmd) { - case 1: - rtw_write8(padapter, arg, extra_arg); - RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); - break; - case 2: - rtw_write16(padapter, arg, extra_arg); - RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); - break; - case 4: - rtw_write32(padapter, arg, extra_arg); - RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); - break; - } - break; - case 0x72: /* read_bb */ - RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); - break; - case 0x73: /* write_bb */ - rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg); - RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); - break; - case 0x74: /* read_rf */ - RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); - break; - case 0x75: /* write_rf */ - rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg); - RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); - break; + if (pmlmepriv->wps_assoc_resp_ie) { + rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + pmlmepriv->wps_assoc_resp_ie = NULL; + } - case 0x76: - switch (minor_cmd) { - case 0x00: /* normal mode, */ - padapter->recvpriv.is_signal_dbg = 0; - break; - case 0x01: /* dbg mode */ - padapter->recvpriv.is_signal_dbg = 1; - extra_arg = extra_arg > 100 ? 100 : extra_arg; - padapter->recvpriv.signal_strength_dbg = extra_arg; - break; + if (ie_len > 0) { + pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_assoc_resp_ie_len = ie_len; + if (pmlmepriv->wps_assoc_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; } - break; - case 0x78: /* IOL test */ - switch (minor_cmd) { - #ifdef CONFIG_IOL - case 0x04: { /* LLT table initialization test */ - u8 page_boundary = 0xf9; - { - struct xmit_frame *xmit_frame; - xmit_frame = rtw_IOL_accquire_xmit_frame(padapter); - if (xmit_frame == NULL) { - ret = -ENOMEM; - break; - } + _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); + } - rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary); + return ret; - if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500, 0)) - ret = -EPERM; - } - } - break; - case 0x05: { /* blink LED test */ - u16 reg = 0x4c; - u32 blink_num = 50; - u32 blink_delay_ms = 200; - int i; +} - { - struct xmit_frame *xmit_frame; +static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + int ie_len; + u8 *ssid_ie; + char ssid[NDIS_802_11_LENGTH_SSID + 1]; + sint ssid_len = 0; + u8 ignore_broadcast_ssid; - xmit_frame = rtw_IOL_accquire_xmit_frame(padapter); - if (xmit_frame == NULL) { - ret = -ENOMEM; - break; - } + if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE) + return -EPERM; - for (i = 0; i < blink_num; i++) { - #ifdef CONFIG_IOL_NEW_GENERATION - rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff); - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); - rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff); - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); - #else - rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00); - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); - rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08); - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); - #endif - } - if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0)) - ret = -EPERM; - } - } - break; + if (param->u.bcn_ie.reserved[0] != 0xea) + return -EINVAL; - case 0x06: { /* continuous wirte byte test */ - u16 reg = arg; - u16 start_value = 0; - u32 write_num = extra_arg; - int i; - u8 final; + mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1]; - { - struct xmit_frame *xmit_frame; + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ + ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len); - xmit_frame = rtw_IOL_accquire_xmit_frame(padapter); - if (xmit_frame == NULL) { - ret = -ENOMEM; - break; - } + if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) { + WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network; + WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network; - for (i = 0; i < write_num; i++) { - #ifdef CONFIG_IOL_NEW_GENERATION - rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF); - #else - rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value); - #endif - } - if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) - ret = -EPERM; - } + _rtw_memcpy(ssid, ssid_ie + 2, ssid_len); + ssid[ssid_len] = 0x0; - final = rtw_read8(padapter, reg); - if (start_value + write_num - 1 == final) - RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final); - else - RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); - } - break; + if (0) + RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + ssid, ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); - case 0x07: { /* continuous wirte word test */ - u16 reg = arg; - u16 start_value = 200; - u32 write_num = extra_arg; + _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network->Ssid.SsidLength = ssid_len; + _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network_ext->Ssid.SsidLength = ssid_len; - int i; - u16 final; + if (0) + RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + } - { - struct xmit_frame *xmit_frame; + RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), + ignore_broadcast_ssid, ssid, ssid_len); - xmit_frame = rtw_IOL_accquire_xmit_frame(padapter); - if (xmit_frame == NULL) { - ret = -ENOMEM; - break; - } + return ret; +} - for (i = 0; i < write_num; i++) { - #ifdef CONFIG_IOL_NEW_GENERATION - rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF); - #else - rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value); - #endif - } - if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) - ret = -EPERM; - } +#if CONFIG_RTW_MACADDR_ACL +static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - final = rtw_read16(padapter, reg); - if (start_value + write_num - 1 == final) - RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final); - else - RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); - } - break; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - case 0x08: { /* continuous wirte dword test */ - u16 reg = arg; - u32 start_value = 0x110000c7; - u32 write_num = extra_arg; + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; - int i; - u32 final; + ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); - { - struct xmit_frame *xmit_frame; + return ret; - xmit_frame = rtw_IOL_accquire_xmit_frame(padapter); - if (xmit_frame == NULL) { - ret = -ENOMEM; - break; - } +} - for (i = 0; i < write_num; i++) { - #ifdef CONFIG_IOL_NEW_GENERATION - rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF); - #else - rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value); - #endif - } - if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) - ret = -EPERM; +static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - } + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - final = rtw_read32(padapter, reg); - if (start_value + write_num - 1 == final) - RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final); - else - RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); - } - break; - #endif /* CONFIG_IOL */ - } - break; - case 0x79: { - /* - * dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15 - * dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15 - */ - u8 value = extra_arg & 0x0f; - u8 sign = minor_cmd; - u16 write_value = 0; + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; - RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value); + ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); - if (sign) - value = value | 0x10; + return ret; - write_value = value | (value << 5); - rtw_write16(padapter, 0x6d9, write_value); - } - break; - case 0x7a: - receive_disconnect(padapter, pmlmeinfo->network.MacAddress - , WLAN_REASON_EXPIRATION_CHK, _FALSE); - break; - case 0x7F: - switch (minor_cmd) { - case 0x0: - RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv)); - break; - case 0x01: - RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", - psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, - psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); - break; - case 0x03: - RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option); -#ifdef CONFIG_80211N_HT - RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option); -#endif /* CONFIG_80211N_HT */ - break; - case 0x04: - RTW_INFO("cur_ch=%d\n", pmlmeext->cur_channel); - RTW_INFO("cur_bw=%d\n", pmlmeext->cur_bwmode); - RTW_INFO("cur_ch_off=%d\n", pmlmeext->cur_ch_offset); +} - RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter)); - RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter)); - RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter)); +static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - break; - case 0x05: - psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); - if (psta) { - RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); - RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", - psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); -#ifdef CONFIG_80211N_HT - RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" - , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); - RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); - RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); -#endif /* CONFIG_80211N_HT */ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; - sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); - } else - RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); - break; - case 0x06: { - u64 tsf = 0; + rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command); - tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg); - RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf); - } - break; - case 0x07: - RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , rtw_is_drv_stopped(padapter) ? "True" : "False"); - break; - case 0x08: { - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct recv_priv *precvpriv = &padapter->recvpriv; + return ret; +} +#endif /* CONFIG_RTW_MACADDR_ACL */ - RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" - ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" - ", free_recvframe_cnt=%d\n", - pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, - pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, - precvpriv->free_recvframe_cnt); -#ifdef CONFIG_USB_HCI - RTW_INFO("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); -#endif - } - break; - case 0x09: { - int i; - _list *plist, *phead; +static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) +{ + struct ieee_param *param; + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); -#ifdef CONFIG_AP_MODE - RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); - RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); -#endif - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + /* RTW_INFO("%s\n", __FUNCTION__); */ - for (i = 0; i < NUM_STA; i++) { - phead = &(pstapriv->sta_hash[i]); - plist = get_next(phead); + /* + * this function is expect to call in master mode, which allows no power saving + * so, we just check hw_init_completed + */ - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + if (!rtw_hw_is_init_completed(dvobj)) { + ret = -EPERM; + goto out; + } - plist = get_next(plist); - if (extra_arg == psta->cmn.aid) { - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); - RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", - psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); -#ifdef CONFIG_80211N_HT - RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", - psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, - psta->htpriv.sgi_40m); - RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); - RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); -#endif /* CONFIG_80211N_HT */ + /* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */ + if (!p->pointer) { + ret = -EINVAL; + goto out; + } -#ifdef CONFIG_AP_MODE - RTW_INFO("capability=0x%x\n", psta->capability); - RTW_INFO("flags=0x%x\n", psta->flags); - RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk); - RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); - RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); - RTW_INFO("qos_info=0x%x\n", psta->qos_info); -#endif - RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) { + ret = -ENOMEM; + goto out; + } - sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); - } + if (copy_from_user(param, p->pointer, p->length)) { + rtw_mfree((u8 *)param, p->length); + ret = -EFAULT; + goto out; + } - } - } + /* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */ - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + switch (param->cmd) { + case RTL871X_HOSTAPD_FLUSH: - } - break; + ret = rtw_hostapd_sta_flush(dev); - case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ - /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ - /* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ + break; - if (arg == 0) { - RTW_INFO("disable driver ctrl vcs\n"); - padapter->driver_vcs_en = 0; - } else if (arg == 1) { - RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg); - padapter->driver_vcs_en = 1; + case RTL871X_HOSTAPD_ADD_STA: - if (extra_arg > 2) - padapter->driver_vcs_type = 1; - else - padapter->driver_vcs_type = extra_arg; - } - } - break; - case 0x0c: { /* dump rx/tx packet */ - if (arg == 0) { - RTW_INFO("dump rx packet (%d)\n", extra_arg); - /* pHalData->bDumpRxPkt =extra_arg; */ - rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); - } else if (arg == 1) { - RTW_INFO("dump tx packet (%d)\n", extra_arg); - rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); - } - } - break; - case 0x0e: { - if (arg == 0) { - RTW_INFO("disable driver ctrl rx_ampdu_factor\n"); - padapter->driver_rx_ampdu_factor = 0xFF; - } else if (arg == 1) { + ret = rtw_add_sta(dev, param); - RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg); + break; - if (extra_arg > 0x03) - padapter->driver_rx_ampdu_factor = 0xFF; - else - padapter->driver_rx_ampdu_factor = extra_arg; - } - } - break; - #ifdef DBG_CONFIG_ERROR_DETECT - case 0x0f: { - if (extra_arg == 0) { - RTW_INFO("###### silent reset test.......#####\n"); - rtw_hal_sreset_reset(padapter); - } else { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; - psrtpriv->dbg_trigger_point = extra_arg; - } + case RTL871X_HOSTAPD_REMOVE_STA: - } - break; - case 0x15: { - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts); - } - break; + ret = rtw_del_sta(dev, param); - #endif + break; - case 0x10: /* driver version display */ - dump_drv_version(RTW_DBGDUMP); - break; - case 0x11: { /* dump linked status */ - int pre_mode; - pre_mode = padapter->bLinkInfoDump; - /* linked_info_dump(padapter,extra_arg); */ - if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */ - padapter->bLinkInfoDump = extra_arg; + case RTL871X_HOSTAPD_SET_BEACON: - else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */ - /* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */ - linked_info_dump(padapter, extra_arg); - } + ret = rtw_set_beacon(dev, param, p->length); + break; + case RTL871X_SET_ENCRYPTION: - } - break; -#ifdef CONFIG_80211N_HT - case 0x12: { /* set rx_stbc */ - struct registry_priv *pregpriv = &padapter->registrypriv; - /* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */ - /* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ - if (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) { - pregpriv->rx_stbc = extra_arg; - RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc); - } else - RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc); + ret = rtw_set_encryption(dev, param, p->length); - } - break; - case 0x13: { /* set ampdu_enable */ - struct registry_priv *pregpriv = &padapter->registrypriv; - /* 0: disable, 0x1:enable */ - if (pregpriv && extra_arg < 2) { - pregpriv->ampdu_enable = extra_arg; - RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable); - } else - RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable); + break; - } - break; -#endif - case 0x14: { /* get wifi_spec */ - struct registry_priv *pregpriv = &padapter->registrypriv; - RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec); + case RTL871X_HOSTAPD_GET_WPAIE_STA: - } - break; + ret = rtw_get_sta_wpaie(dev, param); -#ifdef DBG_FIXED_CHAN - case 0x17: { - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - printk("===> Fixed channel to %d\n", extra_arg); - pmlmeext->fixed_chan = extra_arg; + break; - } - break; -#endif -#ifdef CONFIG_80211N_HT - case 0x19: { - struct registry_priv *pregistrypriv = &padapter->registrypriv; - /* extra_arg : */ - /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */ - /* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ - if (arg == 0) { - RTW_INFO("driver disable LDPC\n"); - pregistrypriv->ldpc_cap = 0x00; - } else if (arg == 1) { - RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg); - pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33); - } - } - break; - case 0x1a: { - struct registry_priv *pregistrypriv = &padapter->registrypriv; - /* extra_arg : */ - /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */ - /* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ - if (arg == 0) { - RTW_INFO("driver disable STBC\n"); - pregistrypriv->stbc_cap = 0x00; - } else if (arg == 1) { - RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg); - pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33); - } - } - break; -#endif /* CONFIG_80211N_HT */ - case 0x1b: { - struct registry_priv *pregistrypriv = &padapter->registrypriv; + case RTL871X_HOSTAPD_SET_WPS_BEACON: - if (arg == 0) { - RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n"); - init_mlme_default_rate_set(padapter); -#ifdef CONFIG_80211N_HT - pregistrypriv->ht_enable = (u8)rtw_ht_enable; -#endif /* CONFIG_80211N_HT */ - } else if (arg == 1) { + ret = rtw_set_wps_beacon(dev, param, p->length); - int i; - u8 max_rx_rate; + break; - RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg); + case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: - max_rx_rate = (u8)extra_arg; + ret = rtw_set_wps_probe_resp(dev, param, p->length); - if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */ -#ifdef CONFIG_80211N_HT - pregistrypriv->ht_enable = 0; -#endif /* CONFIG_80211N_HT */ - for (i = 0; i < NumRates; i++) { - if (pmlmeext->datarate[i] > max_rx_rate) - pmlmeext->datarate[i] = 0xff; - } + break; - } -#ifdef CONFIG_80211N_HT - else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */ - u32 mcs_bitmap = 0x0; + case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: - for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++) - mcs_bitmap |= BIT(i); + ret = rtw_set_wps_assoc_resp(dev, param, p->length); - set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap); - } -#endif /* CONFIG_80211N_HT */ - } - } - break; - case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */ - if (arg == 0) { - RTW_INFO("disable driver ctrl ampdu density\n"); - padapter->driver_ampdu_spacing = 0xFF; - } else if (arg == 1) { + break; - RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg); + case RTL871X_HOSTAPD_SET_HIDDEN_SSID: - if (extra_arg > 0x07) - padapter->driver_ampdu_spacing = 0xFF; - else - padapter->driver_ampdu_spacing = extra_arg; - } - } - break; -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - case 0x1e: { - RTW_INFO("===========================================\n"); - rtw_noise_measure_curchan(padapter); - RTW_INFO("===========================================\n"); - } - break; -#endif + ret = rtw_set_hidden_ssid(dev, param, p->length); + break; -#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS) - case 0x1f: - { - int i, j = 0, test_cnts = 0; - static u8 test_code = 0x5A; - static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0; + case RTL871X_HOSTAPD_GET_INFO_STA: - u32 d_data, i_data; - u32 imr; + ret = rtw_ioctl_get_sta_data(dev, param, p->length); - test_cnts = extra_arg; - for (i = 0; i < test_cnts; i++) { - if (RTW_CANNOT_IO(padapter)) - break; + break; - rtw_write8(padapter, 0x07, test_code); +#if CONFIG_RTW_MACADDR_ACL + case RTL871X_HOSTAPD_SET_MACADDR_ACL: + ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length); + break; + case RTL871X_HOSTAPD_ACL_ADD_STA: + ret = rtw_ioctl_acl_add_sta(dev, param, p->length); + break; + case RTL871X_HOSTAPD_ACL_REMOVE_STA: + ret = rtw_ioctl_acl_remove_sta(dev, param, p->length); + break; +#endif /* CONFIG_RTW_MACADDR_ACL */ - d_data = rtw_read32(padapter, 0x04); - imr = rtw_read32(padapter, 0x10250014); - rtw_write32(padapter, 0x10250014, 0); - rtw_msleep_os(50); + default: + RTW_INFO("Unknown hostapd request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; - i_data = rtw_sd_iread32(padapter, 0x04); + } - rtw_write32(padapter, 0x10250014, imr); + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; - if (d_data != i_data) { - data_misatch_cnt++; - RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data); - } - if (test_code != (i_data >> 24)) { - d_acc_err_cnt++; - rtw_write8(padapter, 0x07, 0xAA); - RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data); - } - if ((j++) == 100) { - rtw_msleep_os(2000); - RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts); - j = 0; - } + rtw_mfree((u8 *)param, p->length); - test_code = ~test_code; - rtw_msleep_os(50); - } - RTW_INFO("========Indirect access test=========\n"); - RTW_INFO(" test_cnts = %d\n", test_cnts); - RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt); - RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt); - RTW_INFO("========Indirect access test=========\n\n"); - data_misatch_cnt = d_acc_err_cnt = 0; +out: - } - break; + return ret; + +} #endif - case 0x20: - { - if (arg == 0xAA) { - u8 page_offset, page_num; - page_offset = (u8)(extra_arg >> 16); - page_num = (u8)(extra_arg & 0xFF); - rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num); - } -#ifdef CONFIG_SUPPORT_FIFO_DUMP - else { - u8 fifo_sel; - u32 addr, size; +static int rtw_wx_set_priv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ - fifo_sel = (u8)(arg & 0x0F); - addr = (extra_arg >> 16) & 0xFFFF; - size = extra_arg & 0xFFFF; - rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size); - } +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + char *ext_dbg; #endif - } - break; - case 0x23: { - RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off"); - padapter->bNotifyChannelChange = extra_arg; - break; - } - case 0x24: { -#ifdef CONFIG_P2P - RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off"); - padapter->bShowGetP2PState = extra_arg; -#endif /* CONFIG_P2P */ - break; - } -#ifdef CONFIG_GPIO_API - case 0x25: { /* Get GPIO register */ - /* - * dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7 - */ + int ret = 0; + int len = 0; + char *ext; +#ifdef CONFIG_RTW_ANDROID + int i; +#endif - u8 value; - RTW_INFO("Read GPIO Value extra_arg = %d\n", extra_arg); - value = rtw_hal_get_gpio(padapter, extra_arg); - RTW_INFO("Read GPIO Value = %d\n", value); - break; - } - case 0x26: { /* Set GPIO direction */ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *dwrq = (struct iw_point *)awrq; - /* dbg 0x7f26000x [y], Set gpio direction, - * x: gpio_num,4~7 y: indicate direction, 0~1 - */ + if (dwrq->length == 0) + return -EFAULT; - int value; - RTW_INFO("Set GPIO Direction! arg = %d ,extra_arg=%d\n", arg , extra_arg); - value = rtw_hal_config_gpio(padapter, arg, extra_arg); - RTW_INFO("Set GPIO Direction %s\n", (value == -1) ? "Fail!!!" : "Success"); - break; - } - case 0x27: { /* Set GPIO output direction value */ - /* - * dbg 0x7f27000x [y], Set gpio output direction value, - * x: gpio_num,4~7 y: indicate direction, 0~1 - */ + len = dwrq->length; + ext = rtw_vmalloc(len); + if (!ext) + return -ENOMEM; - int value; - RTW_INFO("Set GPIO Value! arg = %d ,extra_arg=%d\n", arg , extra_arg); - value = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg); - RTW_INFO("Set GPIO Value %s\n", (value == -1) ? "Fail!!!" : "Success"); - break; - } + if (copy_from_user(ext, dwrq->pointer, len)) { + rtw_vmfree(ext, len); + return -EFAULT; + } + + + +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + ext_dbg = rtw_vmalloc(len); + if (!ext_dbg) { + rtw_vmfree(ext, len); + return -ENOMEM; + } + + _rtw_memcpy(ext_dbg, ext, len); #endif -#ifdef DBG_CMD_QUEUE - case 0x28: { - dump_cmd_id = extra_arg; - RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id); - } - break; -#endif /* DBG_CMD_QUEUE */ - case 0xaa: { - if ((extra_arg & 0x7F) > 0x3F) - extra_arg = 0xFF; - RTW_INFO("chang data rate to :0x%02x\n", extra_arg); - padapter->fix_rate = extra_arg; - } - break; - case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */ - if (extra_arg == 0) - mac_reg_dump(RTW_DBGDUMP, padapter); - else if (extra_arg == 1) - bb_reg_dump(RTW_DBGDUMP, padapter); - else if (extra_arg == 2) - rf_reg_dump(RTW_DBGDUMP, padapter); - else if (extra_arg == 11) - bb_reg_dump_ex(RTW_DBGDUMP, padapter); - } - break; - - case 0xee: { - RTW_INFO(" === please control /proc to trun on/off PHYDM func ===\n"); - } - break; - - case 0xfd: - rtw_write8(padapter, 0xc50, arg); - RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); - rtw_write8(padapter, 0xc58, arg); - RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); - break; - case 0xfe: - RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); - RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); - break; - case 0xff: { - RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); - RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); - RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); - RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); - RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); - - RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); + /* added for wps2.0 @20110524 */ + if (dwrq->flags == 0x8766 && len > 8) { + u32 cp_sz; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *probereq_wpsie = ext; + int probereq_wpsie_len = len; + u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; - RTW_INFO("\n"); + if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && + (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) { + cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len; - RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); - RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); + if (pmlmepriv->wps_probe_req_ie) { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } - RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); + pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz); + if (pmlmepriv->wps_probe_req_ie == NULL) { + printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto FREE_EXT; - RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); + } - RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); - RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); + _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz); + pmlmepriv->wps_probe_req_ie_len = cp_sz; - RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); - RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); - RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); - RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); - } - break; } - break; - default: - RTW_INFO("error dbg cmd!\n"); - break; - } - -#endif - return ret; - -} - -#ifdef CONFIG_IOCTL_WEXT -static int wpa_set_param(struct net_device *dev, u8 name, u32 value) -{ - uint ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - switch (name) { - case IEEE_PARAM_WPA_ENABLED: + goto FREE_EXT; - padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */ + } - /* ret = ieee80211_wpa_enable(ieee, value); */ + if (len >= WEXT_CSCAN_HEADER_SIZE + && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ) { + ret = rtw_wx_set_scan(dev, info, awrq, ext); + goto FREE_EXT; + } - switch ((value) & 0xff) { - case 1: /* WPA */ - padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */ - padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; - break; - case 2: /* WPA2 */ - padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */ - padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; - break; - } +#ifdef CONFIG_RTW_ANDROID + /* RTW_INFO("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); */ + i = rtw_android_cmdstr_to_num(ext); + switch (i) { + case ANDROID_WIFI_CMD_START: + indicate_wx_custom_event(padapter, "START"); break; - - case IEEE_PARAM_TKIP_COUNTERMEASURES: - /* ieee->tkip_countermeasures=value; */ + case ANDROID_WIFI_CMD_STOP: + indicate_wx_custom_event(padapter, "STOP"); break; + case ANDROID_WIFI_CMD_RSSI: { + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *pcur_network = &pmlmepriv->cur_network; - case IEEE_PARAM_DROP_UNENCRYPTED: { - /* HACK: - * - * wpa_supplicant calls set_wpa_enabled when the driver - * is loaded and unloaded, regardless of if WPA is being - * used. No other calls are made which can be used to - * determine if encryption will be used or not prior to - * association being expected. If encryption is not being - * used, drop_unencrypted is set to false, else true -- we - * can use this to determine if the CAP_PRIVACY_ON bit should - * be set. - */ - -#if 0 - struct ieee80211_security sec = { - .flags = SEC_ENABLED, - .enabled = value, - }; - ieee->drop_unencrypted = value; - /* We only change SEC_LEVEL for open mode. Others - * are set by ipw_wpa_set_encryption. - */ - if (!value) { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_0; - } else { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_1; - } - if (ieee->set_security) - ieee->set_security(ieee->dev, &sec); -#endif + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvinfo.rssi); + else + sprintf(ext, "OK"); + } break; - + case ANDROID_WIFI_CMD_LINKSPEED: { + u16 mbps = rtw_get_cur_max_rate(padapter) / 10; + sprintf(ext, "LINKSPEED %d", mbps); } - case IEEE_PARAM_PRIVACY_INVOKED: - - /* ieee->privacy_invoked=value; */ - break; - - case IEEE_PARAM_AUTH_ALGS: - - ret = wpa_set_auth_algs(dev, value); - + case ANDROID_WIFI_CMD_MACADDR: + sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr)); break; - - case IEEE_PARAM_IEEE_802_1X: - - /* ieee->ieee802_1x=value; */ - + case ANDROID_WIFI_CMD_SCAN_ACTIVE: { + /* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */ + sprintf(ext, "OK"); + } break; - - case IEEE_PARAM_WPAX_SELECT: - - /* added for WPA2 mixed mode */ - /*RTW_WARN("------------------------>wpax value = %x\n", value);*/ - /* - spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); - ieee->wpax_type_set = 1; - ieee->wpax_type_notify = value; - spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); - */ - + case ANDROID_WIFI_CMD_SCAN_PASSIVE: { + /* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */ + sprintf(ext, "OK"); + } break; + case ANDROID_WIFI_CMD_COUNTRY: { + char country_code[10]; + sscanf(ext, "%*s %s", country_code); + rtw_set_country(padapter, country_code, RTW_REGD_SET_BY_USER); + sprintf(ext, "OK"); + } + break; default: + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__, + dev->name, ext_dbg); + #endif + + sprintf(ext, "OK"); + } + if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1)))) + ret = -EFAULT; - ret = -EOPNOTSUPP; +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__, + dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1)); +#endif +#endif /* end of CONFIG_ANDROID */ - break; +FREE_EXT: - } + rtw_vmfree(ext, len); + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + rtw_vmfree(ext_dbg, len); + #endif + + /* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", */ + /* dev->name, ret); */ return ret; } - -static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) +#ifdef CONFIG_WOWLAN +static int rtw_wowlan_ctrl(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + int ret = 0; + systime start_time = rtw_get_current_time(); - switch (command) { - case IEEE_MLME_STA_DEAUTH: + RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra); - if (!rtw_set_802_11_disassociate(padapter)) - ret = -1; + if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && + MLME_IS_STA(padapter) && + !WOWLAN_IS_STA_MIX_MODE(padapter)) { +#ifdef CONFIG_PNO_SUPPORT + pwrctrlpriv->wowlan_pno_enable = _TRUE; +#else + RTW_INFO("[%s] WARNING: Please Connect With AP First!!\n", __func__); + goto _rtw_wowlan_ctrl_exit_free; +#endif /* CONFIG_PNO_SUPPORT */ + } - break; + if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) + rtw_scan_abort(padapter, 0); - case IEEE_MLME_STA_DISASSOC: + if (_rtw_memcmp(extra, "enable", 6)) - if (!rtw_set_802_11_disassociate(padapter)) - ret = -1; - break; + rtw_suspend_common(padapter); - default: - ret = -EOPNOTSUPP; - break; - } -#ifdef CONFIG_RTW_REPEATER_SON - rtw_rson_do_disconnect(padapter); + else if (_rtw_memcmp(extra, "disable", 7)) { +#ifdef CONFIG_USB_HCI + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_RX_BIT); + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_TX_BIT); #endif - return ret; + rtw_resume_common(padapter); +#ifdef CONFIG_PNO_SUPPORT + pwrctrlpriv->wowlan_pno_enable = _FALSE; +#endif /* CONFIG_PNO_SUPPORT */ + + } else { + RTW_INFO("[%s] Invalid Parameter.\n", __func__); + goto _rtw_wowlan_ctrl_exit_free; + } + /* mutex_lock(&ioctl_mutex); */ +_rtw_wowlan_ctrl_exit_free: + RTW_PRINT("%s in %d ms\n", __func__, + rtw_get_passing_time_ms(start_time)); + return ret; } -static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) -{ - struct ieee_param *param; - uint ret = 0; +/* + * IP filter This pattern if for a frame containing a ip packet: + * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II + * + * A: Ethernet destination address + * B: Ethernet source address + * C: Ethernet protocol type + * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20) + * E: IP protocol + * F: IP source address ( 192.168.0.4: C0:A8:00:2C ) + * G: IP destination address ( 192.168.0.4: C0:A8:00:2C ) + * H: Source port (1024: 04:00) + * I: Destination port (1024: 04:00) + */ - /* down(&ieee->wx_sem); */ +static int rtw_wowlan_set_pattern(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct registry_priv *registry_par = &padapter->registrypriv; + struct wow_priv *wowpriv = adapter_to_wowlan(padapter); + struct rtw_wowcam_upd_info wowcam_info = {0}; + u8 input[wrqu->data.length]; + int ret = 0; - if (p->length < sizeof(struct ieee_param) || !p->pointer) { - ret = -EINVAL; - goto out; + if (!(registry_par->wakeup_event & BIT(3))) { + ret = -EOPNOTSUPP; + RTW_INFO("%s: customized pattern disabled, wakeup_event: %#2x\n", + __func__, registry_par->wakeup_event); + goto _rtw_wowlan_set_pattern_exit; } - param = (struct ieee_param *)rtw_malloc(p->length); - if (param == NULL) { - ret = -ENOMEM; - goto out; + if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && + MLME_IS_STA(padapter)) { + ret = -EOPNOTSUPP; + RTW_INFO("Please Connect With AP First!!\n"); + goto _rtw_wowlan_set_pattern_exit; } - if (copy_from_user(param, p->pointer, p->length)) { - rtw_mfree((u8 *)param, p->length); - ret = -EFAULT; - goto out; + if (wrqu->data.length <= 0) { + ret = -EINVAL; + RTW_INFO("ERROR: parameter length <= 0\n"); + goto _rtw_wowlan_set_pattern_exit; + } else { + /* set pattern */ + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) { + ret -EFAULT; + goto _rtw_wowlan_set_pattern_exit; + } + + if (strncmp(input, "pattern=", 8) == 0) { + if (rtw_wowlan_parser_pattern_cmd(input, + wowcam_info.ptrn, + &wowcam_info.ptrn_len, + wowcam_info.mask)) { + if (_FAIL == rtw_wow_pattern_set(padapter, + &wowcam_info, + RTW_CUSTOMIZED_PATTERN)) + ret = -EFAULT; + } else { + ret = -EINVAL; + } + } else if (strncmp(input, "clean", 5) == 0) { + rtw_wow_pattern_clean(padapter, RTW_CUSTOMIZED_PATTERN); + } else if (strncmp(input, "show", 4) == 0) { + /* leave PS first */ + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + #if 0 /* WOW_ToDo */ + rtw_wow_pattern_cam_dump(padapter); + rtw_wow_pattern_sw_dump(padapter); + #endif + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + } else { + RTW_INFO("ERROR: incorrect parameter!\n"); + ret = -EINVAL; + } } +_rtw_wowlan_set_pattern_exit: + return ret; +} +#endif /* CONFIG_WOWLAN */ - switch (param->cmd) { - - case IEEE_CMD_SET_WPA_PARAM: - ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); - break; - - case IEEE_CMD_SET_WPA_IE: - /* ret = wpa_set_wpa_ie(dev, param, p->length); */ - ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); - break; - - case IEEE_CMD_SET_ENCRYPTION: - ret = wpa_set_encryption(dev, param, p->length); - break; - - case IEEE_CMD_MLME: - ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); - break; +#ifdef CONFIG_AP_WOWLAN +static int rtw_ap_wowlan_ctrl(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wowlan_ioctl_param poidparam; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_info *psta = NULL; + int ret = 0; + systime start_time = rtw_get_current_time(); + poidparam.subcode = 0; - default: - RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd); - ret = -EOPNOTSUPP; - break; + RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra); + if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + RTW_INFO("[%s] It is not AP mode!!\n", __func__); + goto _rtw_ap_wowlan_ctrl_exit_free; } - if (ret == 0 && copy_to_user(p->pointer, param, p->length)) - ret = -EFAULT; - - rtw_mfree((u8 *)param, p->length); - -out: + if (_rtw_memcmp(extra, "enable", 6)) { - /* up(&ieee->wx_sem); */ + pwrctrlpriv->wowlan_ap_mode = _TRUE; + rtw_suspend_common(padapter); + } else if (_rtw_memcmp(extra, "disable", 7)) { +#ifdef CONFIG_USB_HCI + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_RX_BIT); + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_TX_BIT); +#endif + rtw_resume_common(padapter); + } else { + RTW_INFO("[%s] Invalid Parameter.\n", __func__); + goto _rtw_ap_wowlan_ctrl_exit_free; + } + /* mutex_lock(&ioctl_mutex); */ +_rtw_ap_wowlan_ctrl_exit_free: + RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); + RTW_PRINT("%s in %d ms\n", __func__, + rtw_get_passing_time_ms(start_time)); return ret; - } +#endif /* CONFIG_AP_WOWLAN */ -#ifdef CONFIG_AP_MODE -static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +static int rtw_pm_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { int ret = 0; - u32 wep_key_idx, wep_key_len, wep_total_len; - NDIS_802_11_WEP *pwep = NULL; - struct sta_info *psta = NULL, *pbcmc_sta = NULL; + unsigned mode = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &(padapter->securitypriv); - struct sta_priv *pstapriv = &padapter->stapriv; - - RTW_INFO("%s\n", __FUNCTION__); - param->u.crypt.err = 0; - param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); - /* sizeof(struct ieee_param) = 64 bytes; */ - /* if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */ - if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) { - ret = -EINVAL; - goto exit; + if (_rtw_memcmp(extra, "lps=", 4)) { + sscanf(extra + 4, "%u", &mode); + ret = rtw_pm_set_lps(padapter, mode); + } else if (_rtw_memcmp(extra, "ips=", 4)) { + sscanf(extra + 4, "%u", &mode); + ret = rtw_pm_set_ips(padapter, mode); + } else if (_rtw_memcmp(extra, "lps_level=", 10)) { + if (sscanf(extra + 10, "%u", &mode) > 0) + ret = rtw_pm_set_lps_level(padapter, mode); +#ifdef CONFIG_LPS_1T1R + } else if (_rtw_memcmp(extra, "lps_1t1r=", 9)) { + if (sscanf(extra + 9, "%u", &mode) > 0) + ret = rtw_pm_set_lps_1t1r(padapter, mode); +#endif } - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { - if (param->u.crypt.idx >= WEP_KEYS -#ifdef CONFIG_IEEE80211W - && param->u.crypt.idx > BIP_MAX_KEYID -#endif /* CONFIG_IEEE80211W */ - ) { - ret = -EINVAL; - goto exit; - } - } else { - psta = rtw_get_stainfo(pstapriv, param->sta_addr); - if (!psta) { - /* ret = -EINVAL; */ - RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n"); - goto exit; - } +#ifdef CONFIG_WOWLAN + else if (_rtw_memcmp(extra, "wow_lps=", 8)) { + sscanf(extra + 8, "%u", &mode); + ret = rtw_pm_set_wow_lps(padapter, mode); + } else if (_rtw_memcmp(extra, "wow_lps_level=", 14)) { + if (sscanf(extra + 14, "%u", &mode) > 0) + ret = rtw_pm_set_wow_lps_level(padapter, mode); + #ifdef CONFIG_LPS_1T1R + } else if (_rtw_memcmp(extra, "wow_lps_1t1r=", 13)) { + if (sscanf(extra + 13, "%u", &mode) > 0) + ret = rtw_pm_set_wow_lps_1t1r(padapter, mode); + #endif } +#endif /* CONFIG_WOWLAN */ + else + ret = -EINVAL; - if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) { - /* todo:clear default encryption keys */ - - psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; - psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; - psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + return ret; +} +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); +int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num, + char *extra, u32 length) +{ + int j; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u32 vendor_ie_mask = 0; + char *pstring; - goto exit; + if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) { + RTW_INFO("[%s] only support %d vendor ie\n", __func__ , + WLAN_MAX_VENDOR_IE_NUM); + return -EFAULT; } + if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) { + RTW_INFO("[%s] Fail, vendor_ie_num: %d is not set\n", __func__, + vendor_ie_num); + return -EFAULT; + } - if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) { - RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n"); - - wep_key_idx = param->u.crypt.idx; - wep_key_len = param->u.crypt.key_len; - - RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); - - if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { - ret = -EINVAL; - goto exit; - } - - - if (wep_key_len > 0) { - wep_key_len = wep_key_len <= 5 ? 5 : 13; - wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); - pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len); - if (pwep == NULL) { - RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n"); - goto exit; - } - - _rtw_memset(pwep, 0, wep_total_len); - - pwep->KeyLength = wep_key_len; - pwep->Length = wep_total_len; - - } - - pwep->KeyIndex = wep_key_idx; + if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) { + RTW_INFO("[%s] Fail, buffer size is too small\n", __func__); + return -EFAULT; + } - _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); + vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; + _rtw_memset(extra, 0, length); - if (param->u.crypt.set_tx) { - RTW_INFO("wep, set_tx=1\n"); + pstring = extra; + pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask); - psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; - psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; - psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++) + pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]); - if (pwep->KeyLength == 13) { - psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - } + length = pstring - extra; + return length; +} +int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra) +{ + int j; + char *pstring; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u32 vendor_ie_mask = 0; + __u16 length = 0; - psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; + pstring = extra; + pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask); - _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[Beacon]"); + if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[Probe Req]"); + if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[Probe Resp]"); + if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[Assoc Req]"); + if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[Assoc Resp]"); +#ifdef CONFIG_P2P + if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[P2P_Probe Req]"); + if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT) + pstring += sprintf(pstring , "[P2P_Probe Resp]"); +#endif - psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; + pstring += sprintf(pstring , "\nVendor IE:\n"); + for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num] ; j++) + pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]); - rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1); - } else { - RTW_INFO("wep, set_tx=0\n"); + length = pstring - extra; + return length; - /* don't update "psecuritypriv->dot11PrivacyAlgrthm" and */ - /* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */ +} - _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); +int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + int ret = 0, vendor_ie_num = 0, cmdlen; + struct iw_point *p; + u8 *ptmp; - psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; + p = &wrqu->data; + cmdlen = p->length; + if (0 == cmdlen) + return -EINVAL; - rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0); - } + ptmp = (u8 *)rtw_malloc(cmdlen); + if (NULL == ptmp) + return -ENOMEM; + if (copy_from_user(ptmp, p->pointer, cmdlen)) { + ret = -EFAULT; goto exit; - } - - - if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ - if (param->u.crypt.set_tx == 1) { - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); - psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /* set mic key */ - _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); - psecuritypriv->dot118021XGrpPrivacy = _AES_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - #ifdef CONFIG_IEEE80211W - } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); - _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; - psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); - psecuritypriv->binstallBIPkey = _TRUE; - goto exit; - #endif /* CONFIG_IEEE80211W */ - - } else if (strcmp(param->u.crypt.alg, "none") == 0) { - RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" - , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - } else { - RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" - , FUNC_ADPT_ARG(padapter)); - goto exit; - } - - psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - if (pbcmc_sta) { - pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); - pbcmc_sta->ieee8021x_blocked = _FALSE; - pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ - } - psecuritypriv->binstallGrpkey = _TRUE; - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - } - + ret = sscanf(ptmp , "%d", &vendor_ie_num); + if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { + ret = -EFAULT; goto exit; - } - if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - if (param->u.crypt.set_tx == 1) { - _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) - , param->u.crypt.idx, param->u.crypt.key_len); - psta->dot118021XPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psta->dot118021XPrivacy = _WEP104_; - - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) - , param->u.crypt.idx, param->u.crypt.key_len); - psta->dot118021XPrivacy = _TKIP_; - /* set mic key */ - _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) - , param->u.crypt.idx, param->u.crypt.key_len); - psta->dot118021XPrivacy = _AES_; - - } else if (strcmp(param->u.crypt.alg, "none") == 0) { - RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) - , param->u.crypt.idx); - psta->dot118021XPrivacy = _NO_PRIVACY_; - - } else { - RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); - goto exit; - } - - psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); - psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); - psta->ieee8021x_blocked = _FALSE; - - if (psta->dot118021XPrivacy != _NO_PRIVACY_) { - psta->bpairwise_key_installed = _TRUE; - - /* WPA2 key-handshake has completed */ - if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) - psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); - } - - rtw_ap_set_pairwise_key(padapter, psta); - } else { - RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); - goto exit; - } - - } - - } + wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra); exit: + rtw_mfree(ptmp, cmdlen); - if (pwep) - rtw_mfree((u8 *)pwep, wep_total_len); - - return ret; - + return 0; } -static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) +int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - int ret = 0; + int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - unsigned char *pbuf = param->u.bcn_ie.buf; - + u32 vendor_ie_mask = 0; + u32 vendor_ie_num = 0; + u32 vendor_ie_mask_max = BIT(WLAN_MAX_VENDOR_IE_MASK_MAX) - 1; + u32 id, elen; - RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); - - if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0)) - pstapriv->max_num_sta = NUM_STA; - - - if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */ - ret = 0; + ret = sscanf(extra, "%d,%x,%*s", &vendor_ie_num , &vendor_ie_mask); + if (strrchr(extra , ',')) + extra = strrchr(extra , ',') + 1; else - ret = -EINVAL; - - - return ret; - -} - -static int rtw_hostapd_sta_flush(struct net_device *dev) -{ - /* _irqL irqL; */ - /* _list *phead, *plist; */ - int ret = 0; - /* struct sta_info *psta = NULL; */ - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - /* struct sta_priv *pstapriv = &padapter->stapriv; */ - - RTW_INFO("%s\n", __FUNCTION__); - - flush_all_cam_entry(padapter); /* clear CAM */ -#ifdef CONFIG_AP_MODE - ret = rtw_sta_flush(padapter, _TRUE); -#endif - return ret; - -} - -static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) -{ - int ret = 0; - struct sta_info *psta = NULL; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - - RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); - - if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) - return -EINVAL; - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; + totoal_ie_len = strlen(extra); + RTW_INFO("[%s] vendor_ie_num = %d , vendor_ie_mask = 0x%x , vendor_ie = %s , len = %d\n", __func__ , vendor_ie_num , vendor_ie_mask , extra , totoal_ie_len); -#if 0 - psta = rtw_get_stainfo(pstapriv, param->sta_addr); - if (psta) { - RTW_INFO("rtw_add_sta(), free has been added psta=%p\n", psta); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(padapter, psta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - - psta = NULL; + if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { + RTW_INFO("[%s] Fail, only support %d vendor ie\n", __func__ , WLAN_MAX_VENDOR_IE_NUM); + return -EFAULT; } -#endif - /* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */ - psta = rtw_get_stainfo(pstapriv, param->sta_addr); - if (psta) { - int flags = param->u.add_sta.flags; - - /* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */ - - psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */ - - _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); - - - /* check wmm cap. */ - if (WLAN_STA_WME & flags) - psta->qos_option = 1; - else - psta->qos_option = 0; - - if (pmlmepriv->qospriv.qos_option == 0) - psta->qos_option = 0; - - -#ifdef CONFIG_80211N_HT - /* chec 802.11n ht cap. */ - if (padapter->registrypriv.ht_enable && - is_supported_ht(padapter->registrypriv.wireless_mode) && - (WLAN_STA_HT & flags)) { - psta->htpriv.ht_option = _TRUE; - psta->qos_option = 1; - _rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); - } else - psta->htpriv.ht_option = _FALSE; - - if (pmlmepriv->htpriv.ht_option == _FALSE) - psta->htpriv.ht_option = _FALSE; - -#endif - - - update_sta_info_apmode(padapter, psta); - - - } else - ret = -ENOMEM; - - return ret; - -} - -static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) -{ - _irqL irqL; - int ret = 0; - struct sta_info *psta = NULL; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - - RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); - - if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) - return -EINVAL; - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) - return -EINVAL; - - psta = rtw_get_stainfo(pstapriv, param->sta_addr); - if (psta) { - u8 updated = _FALSE; - - /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */ - - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { - rtw_list_delete(&psta->asoc_list); - pstapriv->asoc_list_cnt--; - #ifdef CONFIG_RTW_TOKEN_BASED_XMIT - if (psta->tbtx_enable) - pstapriv->tbtx_asoc_list_cnt--; - #endif - updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); - - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); - - psta = NULL; - - } else { - RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n"); - - /* ret = -1; */ + if (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) { + RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_VENDOR_IE_LEN); + return -EFAULT; } + if (vendor_ie_mask > vendor_ie_mask_max) { + RTW_INFO("[%s] Fail, not support vendor_ie_mask more than 0x%x\n", __func__ , vendor_ie_mask_max); + return -EFAULT; + } - return ret; - -} - -static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - struct sta_info *psta = NULL; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; - struct sta_data *psta_data = (struct sta_data *)param_ex->data; - - RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr)); - - if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) - return -EINVAL; - - if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && - param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && - param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) - return -EINVAL; - - psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); - if (psta) { -#if 0 - struct { - u16 aid; - u16 capability; - int flags; - u32 sta_set; - u8 tx_supp_rates[16]; - u32 tx_supp_rates_len; - struct rtw_ieee80211_ht_cap ht_cap; - u64 rx_pkts; - u64 rx_bytes; - u64 rx_drops; - u64 tx_pkts; - u64 tx_bytes; - u64 tx_drops; - } get_sta; -#endif - psta_data->aid = (u16)psta->cmn.aid; - psta_data->capability = psta->capability; - psta_data->flags = psta->flags; - - /* - nonerp_set : BIT(0) - no_short_slot_time_set : BIT(1) - no_short_preamble_set : BIT(2) - no_ht_gf_set : BIT(3) - no_ht_set : BIT(4) - ht_20mhz_set : BIT(5) - */ - - psta_data->sta_set = ((psta->nonerp_set) | - (psta->no_short_slot_time_set << 1) | - (psta->no_short_preamble_set << 2) | - (psta->no_ht_gf_set << 3) | - (psta->no_ht_set << 4) | - (psta->ht_20mhz_set << 5)); - - psta_data->tx_supp_rates_len = psta->bssratelen; - _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); -#ifdef CONFIG_80211N_HT - if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) - _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); -#endif /* CONFIG_80211N_HT */ - psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; - psta_data->rx_bytes = psta->sta_stats.rx_bytes; - psta_data->rx_drops = psta->sta_stats.rx_drops; - - psta_data->tx_pkts = psta->sta_stats.tx_pkts; - psta_data->tx_bytes = psta->sta_stats.tx_bytes; - psta_data->tx_drops = psta->sta_stats.tx_drops; - - - } else - ret = -1; - - return ret; + if (vendor_ie_mask == 0) { + RTW_INFO("[%s] Clear vendor_ie_num %d group\n", __func__ , vendor_ie_num); + goto _clear_path; + } -} + if (totoal_ie_len % 2 != 0) { + RTW_INFO("[%s] Fail , IE length = %zu is odd\n" , __func__ , strlen(extra)); + return -EFAULT; + } -static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) -{ - int ret = 0; - struct sta_info *psta = NULL; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct sta_priv *pstapriv = &padapter->stapriv; - - RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); - - if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE) - return -EINVAL; - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) - return -EINVAL; - - psta = rtw_get_stainfo(pstapriv, param->sta_addr); - if (psta) { - if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) { - int wpa_ie_len; - int copy_len; - - wpa_ie_len = psta->wpa_ie[1]; - - copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2); - - param->u.wpa_ie.len = copy_len; - - _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); - } else { - /* ret = -1; */ - RTW_INFO("sta's wpa_ie is NONE\n"); - } - } else - ret = -1; - - return ret; - -} - -static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - int ie_len; - - RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - - - if (pmlmepriv->wps_beacon_ie) { - rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); - pmlmepriv->wps_beacon_ie = NULL; - } - - if (ie_len > 0) { - pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); - pmlmepriv->wps_beacon_ie_len = ie_len; - if (pmlmepriv->wps_beacon_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - } - - _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); - - update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, 0); - - pmlmeext->bstart_bss = _TRUE; - - } - - - return ret; - -} - -static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - int ie_len; - - RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - - - if (pmlmepriv->wps_probe_resp_ie) { - rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); - pmlmepriv->wps_probe_resp_ie = NULL; - } - - if (ie_len > 0) { - pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); - pmlmepriv->wps_probe_resp_ie_len = ie_len; - if (pmlmepriv->wps_probe_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - } - _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); - } - - - return ret; - -} - -static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - int ie_len; - - RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - - - if (pmlmepriv->wps_assoc_resp_ie) { - rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); - pmlmepriv->wps_assoc_resp_ie = NULL; - } - - if (ie_len > 0) { - pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); - pmlmepriv->wps_assoc_resp_ie_len = ie_len; - if (pmlmepriv->wps_assoc_resp_ie == NULL) { - RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - return -EINVAL; - } - - _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); - } - - - return ret; - -} - -static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *mlmepriv = &(adapter->mlmepriv); - struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); - struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); - int ie_len; - u8 *ssid_ie; - char ssid[NDIS_802_11_LENGTH_SSID + 1]; - sint ssid_len = 0; - u8 ignore_broadcast_ssid; - - if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE) - return -EPERM; - - if (param->u.bcn_ie.reserved[0] != 0xea) - return -EINVAL; - - mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1]; - - ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ - ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len); - - if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) { - WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network; - WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network; - - _rtw_memcpy(ssid, ssid_ie + 2, ssid_len); - ssid[ssid_len] = 0x0; - - if (0) - RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), - ssid, ssid_len, - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, - pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); - - _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); - pbss_network->Ssid.SsidLength = ssid_len; - _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len); - pbss_network_ext->Ssid.SsidLength = ssid_len; - - if (0) - RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, - pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); - } - - RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), - ignore_broadcast_ssid, ssid, ssid_len); - - return ret; -} - -#if CONFIG_RTW_MACADDR_ACL -static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) - return -EINVAL; - - ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); - - return ret; - -} - -static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) - return -EINVAL; - - ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); - - return ret; - -} - -static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) -{ - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) - return -EINVAL; - - rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command); - - return ret; -} -#endif /* CONFIG_RTW_MACADDR_ACL */ - -static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) -{ - struct ieee_param *param; - int ret = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - /* RTW_INFO("%s\n", __FUNCTION__); */ - - /* - * this function is expect to call in master mode, which allows no power saving - * so, we just check hw_init_completed - */ - - if (!rtw_is_hw_init_completed(padapter)) { - ret = -EPERM; - goto out; - } - - - /* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */ - if (!p->pointer) { - ret = -EINVAL; - goto out; - } - - param = (struct ieee_param *)rtw_malloc(p->length); - if (param == NULL) { - ret = -ENOMEM; - goto out; - } - - if (copy_from_user(param, p->pointer, p->length)) { - rtw_mfree((u8 *)param, p->length); - ret = -EFAULT; - goto out; - } - - /* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */ - - switch (param->cmd) { - case RTL871X_HOSTAPD_FLUSH: - - ret = rtw_hostapd_sta_flush(dev); - - break; - - case RTL871X_HOSTAPD_ADD_STA: - - ret = rtw_add_sta(dev, param); - - break; - - case RTL871X_HOSTAPD_REMOVE_STA: - - ret = rtw_del_sta(dev, param); - - break; - - case RTL871X_HOSTAPD_SET_BEACON: - - ret = rtw_set_beacon(dev, param, p->length); - - break; - - case RTL871X_SET_ENCRYPTION: - - ret = rtw_set_encryption(dev, param, p->length); - - break; - - case RTL871X_HOSTAPD_GET_WPAIE_STA: - - ret = rtw_get_sta_wpaie(dev, param); - - break; - - case RTL871X_HOSTAPD_SET_WPS_BEACON: - - ret = rtw_set_wps_beacon(dev, param, p->length); - - break; - - case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: - - ret = rtw_set_wps_probe_resp(dev, param, p->length); - - break; - - case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: - - ret = rtw_set_wps_assoc_resp(dev, param, p->length); - - break; - - case RTL871X_HOSTAPD_SET_HIDDEN_SSID: - - ret = rtw_set_hidden_ssid(dev, param, p->length); - - break; - - case RTL871X_HOSTAPD_GET_INFO_STA: - - ret = rtw_ioctl_get_sta_data(dev, param, p->length); - - break; - -#if CONFIG_RTW_MACADDR_ACL - case RTL871X_HOSTAPD_SET_MACADDR_ACL: - ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length); - break; - case RTL871X_HOSTAPD_ACL_ADD_STA: - ret = rtw_ioctl_acl_add_sta(dev, param, p->length); - break; - case RTL871X_HOSTAPD_ACL_REMOVE_STA: - ret = rtw_ioctl_acl_remove_sta(dev, param, p->length); - break; -#endif /* CONFIG_RTW_MACADDR_ACL */ - - default: - RTW_INFO("Unknown hostapd request: %d\n", param->cmd); - ret = -EOPNOTSUPP; - break; - - } - - if (ret == 0 && copy_to_user(p->pointer, param, p->length)) - ret = -EFAULT; - - - rtw_mfree((u8 *)param, p->length); - -out: - - return ret; - -} -#endif /* CONFIG_AP_MODE */ - -static int rtw_wx_set_priv(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *awrq, - char *extra) -{ - -#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV - char *ext_dbg; -#endif - - int ret = 0; - int len = 0; - char *ext; -#ifdef CONFIG_RTW_ANDROID - int i; -#endif - - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *dwrq = (struct iw_point *)awrq; - - if (dwrq->length == 0) - return -EFAULT; - - len = dwrq->length; - ext = rtw_vmalloc(len); - if (!ext) - return -ENOMEM; - - if (copy_from_user(ext, dwrq->pointer, len)) { - rtw_vmfree(ext, len); - return -EFAULT; - } - - - -#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV - ext_dbg = rtw_vmalloc(len); - if (!ext_dbg) { - rtw_vmfree(ext, len); - return -ENOMEM; - } - - _rtw_memcpy(ext_dbg, ext, len); -#endif - - /* added for wps2.0 @20110524 */ - if (dwrq->flags == 0x8766 && len > 8) { - u32 cp_sz; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u8 *probereq_wpsie = ext; - int probereq_wpsie_len = len; - u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; - - if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && - (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) { - cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len; - - if (pmlmepriv->wps_probe_req_ie) { - u32 free_len = pmlmepriv->wps_probe_req_ie_len; - pmlmepriv->wps_probe_req_ie_len = 0; - rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); - pmlmepriv->wps_probe_req_ie = NULL; - } - - pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz); - if (pmlmepriv->wps_probe_req_ie == NULL) { - printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); - ret = -EINVAL; - goto FREE_EXT; - - } - - _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz); - pmlmepriv->wps_probe_req_ie_len = cp_sz; - - } - - goto FREE_EXT; - - } - - if (len >= WEXT_CSCAN_HEADER_SIZE - && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE - ) { - ret = rtw_wx_set_scan(dev, info, awrq, ext); - goto FREE_EXT; - } - -#ifdef CONFIG_RTW_ANDROID - /* RTW_INFO("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); */ - - i = rtw_android_cmdstr_to_num(ext); - - switch (i) { - case ANDROID_WIFI_CMD_START: - indicate_wx_custom_event(padapter, "START"); - break; - case ANDROID_WIFI_CMD_STOP: - indicate_wx_custom_event(padapter, "STOP"); - break; - case ANDROID_WIFI_CMD_RSSI: { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *pcur_network = &pmlmepriv->cur_network; - - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) - sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); - else - sprintf(ext, "OK"); - } - break; - case ANDROID_WIFI_CMD_LINKSPEED: { - u16 mbps = rtw_get_cur_max_rate(padapter) / 10; - sprintf(ext, "LINKSPEED %d", mbps); - } - break; - case ANDROID_WIFI_CMD_MACADDR: - sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr)); - break; - case ANDROID_WIFI_CMD_SCAN_ACTIVE: { - /* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */ - sprintf(ext, "OK"); - } - break; - case ANDROID_WIFI_CMD_SCAN_PASSIVE: { - /* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */ - sprintf(ext, "OK"); - } - break; - - case ANDROID_WIFI_CMD_COUNTRY: { - char country_code[10]; - sscanf(ext, "%*s %s", country_code); - rtw_set_country(padapter, country_code); - sprintf(ext, "OK"); - } - break; - default: - #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV - RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__, - dev->name, ext_dbg); - #endif - - sprintf(ext, "OK"); - - } - - if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1)))) - ret = -EFAULT; - -#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV - RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__, - dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1)); -#endif -#endif /* end of CONFIG_ANDROID */ - - -FREE_EXT: - - rtw_vmfree(ext, len); - #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV - rtw_vmfree(ext_dbg, len); - #endif - - /* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", */ - /* dev->name, ret); */ - - return ret; - -} -#endif /*CONFIG_IOCTL_WEXT*/ - -#ifdef CONFIG_WOWLAN -static int rtw_wowlan_ctrl(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wowlan_ioctl_param poidparam; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - int ret = 0; - systime start_time = rtw_get_current_time(); - poidparam.subcode = 0; - - RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra); - - if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE) && - !WOWLAN_IS_STA_MIX_MODE(padapter)) { -#ifdef CONFIG_PNO_SUPPORT - pwrctrlpriv->wowlan_pno_enable = _TRUE; -#else - RTW_INFO("[%s] WARNING: Please Connect With AP First!!\n", __func__); - goto _rtw_wowlan_ctrl_exit_free; -#endif /* CONFIG_PNO_SUPPORT */ - } - - if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) - rtw_scan_abort(padapter); - - if (_rtw_memcmp(extra, "enable", 6)) - - - rtw_suspend_common(padapter); - - else if (_rtw_memcmp(extra, "disable", 7)) { -#ifdef CONFIG_USB_HCI - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); -#endif - rtw_resume_common(padapter); - -#ifdef CONFIG_PNO_SUPPORT - pwrctrlpriv->wowlan_pno_enable = _FALSE; -#endif /* CONFIG_PNO_SUPPORT */ - - } else { - RTW_INFO("[%s] Invalid Parameter.\n", __func__); - goto _rtw_wowlan_ctrl_exit_free; - } - /* mutex_lock(&ioctl_mutex); */ -_rtw_wowlan_ctrl_exit_free: - RTW_INFO("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); - RTW_PRINT("%s in %d ms\n", __func__, - rtw_get_passing_time_ms(start_time)); - return ret; -} - -/* - * IP filter This pattern if for a frame containing a ip packet: - * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II - * - * A: Ethernet destination address - * B: Ethernet source address - * C: Ethernet protocol type - * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20) - * E: IP protocol - * F: IP source address ( 192.168.0.4: C0:A8:00:2C ) - * G: IP destination address ( 192.168.0.4: C0:A8:00:2C ) - * H: Source port (1024: 04:00) - * I: Destination port (1024: 04:00) - */ - -static int rtw_wowlan_set_pattern(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct wowlan_ioctl_param poidparam; - int ret = 0; - u8 input[MAX_IN_PATTERN_SIZE]; - u8 index = 0; - - poidparam.subcode = 0; - - if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - ret = -EFAULT; - RTW_INFO("Please Connect With AP First!!\n"); - goto _rtw_wowlan_set_pattern_exit; - } - - if ((wrqu->data.length <= 0) || (wrqu->data.length > MAX_IN_PATTERN_SIZE)) { - ret = -EFAULT; - RTW_INFO("ERROR: parameter length error, len=%d\n", wrqu->data.length); - goto _rtw_wowlan_set_pattern_exit; - } else { - /* set pattern */ - if (copy_from_user(input, - wrqu->data.pointer, wrqu->data.length)) - return -EFAULT; - /* leave PS first */ - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); - if ((strncmp(input, "pattern=", 8) == 0) ||(strncmp(input, "ack_pattern=", 12) == 0)) { - if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) { - RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n", - pwrpriv->wowlan_pattern_idx); - RTW_INFO("WARNING: please clean priv-pattern first\n"); - ret = -EINVAL; - goto _rtw_wowlan_set_pattern_exit; - } else { - index = pwrpriv->wowlan_pattern_idx; - ret = rtw_wowlan_parser_pattern_cmd(input, - pwrpriv->patterns[index].content, - &pwrpriv->patterns[index].len, - pwrpriv->patterns[index].mask); - - if (ret == _TRUE) { - #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - if(strncmp(input, "ack_pattern=", 12) == 0) - pwrpriv->wowlan_keep_alive_ack_index = index; - else - pwrpriv->wowlan_wake_pattern_index = index; - RTW_INFO("pwrpriv->wowlan_keep_alive_ack_index =%d\n",pwrpriv->wowlan_keep_alive_ack_index); - RTW_INFO("pwrpriv->wowlan_wake_pattern_index =%d\n",pwrpriv->wowlan_wake_pattern_index); - #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - pwrpriv->wowlan_pattern_idx++; - } - } - } else if (strncmp(input, "clean", 5) == 0) { - poidparam.subcode = WOWLAN_PATTERN_CLEAN; - #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - pwrpriv->wowlan_wake_pattern_index = 0xFF; - pwrpriv->wowlan_keep_alive_ack_index = 0xFF; - #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - - rtw_hal_set_hwreg(padapter, - HW_VAR_WOWLAN, (u8 *)&poidparam); - } else if (strncmp(input, "show", 4) == 0) { - rtw_wow_pattern_cam_dump(padapter); - rtw_wow_pattern_sw_dump(padapter); - } else { - RTW_INFO("ERROR: incorrect parameter!\n"); - ret = -EINVAL; - } - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); - } -_rtw_wowlan_set_pattern_exit: - return ret; -} - -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN -static int rtw_wowlan_set_keep_alive_pattern(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - - int ret = 0,totoal_len=0,i=0,len=0; - char *cp = NULL; - u32 mode = 0xFF; /*para1*/ - u16 period = 15*10; /* para2;units:100ms,default 15s*/ - char tx_pattern[512]; /*para3*/ - u32 retry_intervel = 2*10; /* para4;units:100ms,default 2s*/ - u32 retry_limit_count = 5; /*para5*/ - - ret = sscanf(extra, "%d %hu %s %d %d", &mode , &period, tx_pattern, &retry_intervel, &retry_limit_count); - pwrpriv->wowlan_keep_alive_mode = mode; - - RTW_INFO("[%s] ret =%d \n", __func__ ,ret); - totoal_len = strlen(tx_pattern); - RTW_INFO("[%s] totoal_len=%d \n", __func__ ,totoal_len); - - if (mode && (ret < 3)) - return -EINVAL; - - if (((mode ==2) ||(mode ==3)) && ((retry_intervel*retry_limit_count) > period)) { - RTW_INFO("[%s] retry_intervel*retry_limit_count need smaller than period\n", __func__ ); - return -EINVAL; - } - - switch(mode){ - case wow_keep_alive_pattern_disable: - /*disable this feature*/ - pwrpriv->keep_alive_pattern_loc = 0; - pwrpriv->keep_alive_pattern_len = 0; - pwrpriv->wowlan_keep_alive_period = 0; - pwrpriv->wowlan_keep_alive_ack_index = 0xFF; - pwrpriv->wowlan_wake_pattern_index = 0xFF; - pwrpriv->wowlan_keep_alive_retry_interval = 0; - pwrpriv->wowlan_keep_alive_retry_counter = 0; - _rtw_memset(pwrpriv->keep_alive_pattern,0,WLAN_MAX_KEEP_ALIVE_IE_LEN); - RTW_INFO("[%s] clear pattern \n", __func__ ); - ret = _SUCCESS; - break; - case wow_keep_alive_pattern_tx: - /*only tx udp packet*/ - pwrpriv->wowlan_keep_alive_period = period; - pwrpriv->wowlan_keep_alive_retry_interval = 0; - pwrpriv->wowlan_keep_alive_retry_counter = 0; - RTW_INFO("[%s] wow_keep_alive_pattern_tx \n", __func__ ); - break; - case wow_keep_alive_pattern_trx: - /*trx+no need wakeup*/ - pwrpriv->wowlan_keep_alive_period = period; - pwrpriv->wowlan_keep_alive_retry_interval = retry_intervel; - pwrpriv->wowlan_keep_alive_retry_counter = retry_limit_count; - RTW_INFO("[%s] wow_keep_alive_pattern_trx \n", __func__ ); - break; - case wow_keep_alive_pattern_trx_with_ack: - /*trx+need wakeup*/ - pwrpriv->wowlan_keep_alive_period = period; - pwrpriv->wowlan_keep_alive_retry_interval = retry_intervel; - pwrpriv->wowlan_keep_alive_retry_counter = retry_limit_count; - RTW_INFO("[%s] wow_keep_alive_pattern_trx_with_ack \n", __func__ ); - break; - default: - RTW_INFO("[%s] please setting valid mode \n", __func__ ); - ret = -EINVAL; - break; - - } - - if((mode == 0) || (mode > 4)) - return ret; - - totoal_len = strlen(tx_pattern); - RTW_INFO("[%s] totoal_len=%d \n", __func__ ,totoal_len); - if (totoal_len > WLAN_MAX_KEEP_ALIVE_IE_LEN*2) { - RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_KEEP_ALIVE_IE_LEN); - return -EFAULT; - } - RTW_INFO("[%s] period = %hu ,ie = %s , len = %d\n", __func__ , period , tx_pattern , totoal_len); - - - if (totoal_len > 0) { - RTW_INFO("[%s] pwrpriv->keep_alive_pattern==========> \n", __func__ ); - for (i = 0 ; i keep_alive_pattern[len] = key_2char2num(tx_pattern[i], tx_pattern[i + 1]); - RTW_INFO("[0x%x] ",pwrpriv->keep_alive_pattern[len]); - len++; - } - RTW_INFO(" \n" ); - pwrpriv->keep_alive_pattern_len = len; - } - - return ret; -} -#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - -#endif /* CONFIG_WOWLAN */ - -#ifdef CONFIG_AP_WOWLAN -static int rtw_ap_wowlan_ctrl(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct wowlan_ioctl_param poidparam; - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct sta_info *psta = NULL; - int ret = 0; - systime start_time = rtw_get_current_time(); - poidparam.subcode = 0; - - RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra); - - if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - RTW_INFO("[%s] It is not AP mode!!\n", __func__); - goto _rtw_ap_wowlan_ctrl_exit_free; - } - - if (_rtw_memcmp(extra, "enable", 6)) { - - pwrctrlpriv->wowlan_ap_mode = _TRUE; - - rtw_suspend_common(padapter); - } else if (_rtw_memcmp(extra, "disable", 7)) { -#ifdef CONFIG_USB_HCI - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); -#endif - rtw_resume_common(padapter); - } else { - RTW_INFO("[%s] Invalid Parameter.\n", __func__); - goto _rtw_ap_wowlan_ctrl_exit_free; - } - /* mutex_lock(&ioctl_mutex); */ -_rtw_ap_wowlan_ctrl_exit_free: - RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); - RTW_PRINT("%s in %d ms\n", __func__, - rtw_get_passing_time_ms(start_time)); -_rtw_ap_wowlan_ctrl_exit: - return ret; -} -#endif /* CONFIG_AP_WOWLAN */ - -static int rtw_pm_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - unsigned mode = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); - - if (_rtw_memcmp(extra, "lps=", 4)) { - sscanf(extra + 4, "%u", &mode); - ret = rtw_pm_set_lps(padapter, mode); - } else if (_rtw_memcmp(extra, "ips=", 4)) { - sscanf(extra + 4, "%u", &mode); - ret = rtw_pm_set_ips(padapter, mode); - } else if (_rtw_memcmp(extra, "lps_level=", 10)) { - if (sscanf(extra + 10, "%u", &mode) > 0) - ret = rtw_pm_set_lps_level(padapter, mode); -#ifdef CONFIG_LPS_1T1R - } else if (_rtw_memcmp(extra, "lps_1t1r=", 9)) { - if (sscanf(extra + 9, "%u", &mode) > 0) - ret = rtw_pm_set_lps_1t1r(padapter, mode); -#endif - } -#ifdef CONFIG_WOWLAN - else if (_rtw_memcmp(extra, "wow_lps=", 8)) { - sscanf(extra + 8, "%u", &mode); - ret = rtw_pm_set_wow_lps(padapter, mode); - } else if (_rtw_memcmp(extra, "wow_lps_level=", 14)) { - if (sscanf(extra + 14, "%u", &mode) > 0) - ret = rtw_pm_set_wow_lps_level(padapter, mode); - #ifdef CONFIG_LPS_1T1R - } else if (_rtw_memcmp(extra, "wow_lps_1t1r=", 13)) { - if (sscanf(extra + 13, "%u", &mode) > 0) - ret = rtw_pm_set_wow_lps_1t1r(padapter, mode); - #endif - } -#endif /* CONFIG_WOWLAN */ - else - ret = -EINVAL; - - return ret; -} -#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - -int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num, - char *extra, u32 length) -{ - int j; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u32 vendor_ie_mask = 0; - char *pstring; - - if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) { - RTW_INFO("[%s] only support %d vendor ie\n", __func__ , - WLAN_MAX_VENDOR_IE_NUM); - return -EFAULT; - } - - if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) { - RTW_INFO("[%s] Fail, vendor_ie_num: %d is not set\n", __func__, - vendor_ie_num); - return -EFAULT; - } - - if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) { - RTW_INFO("[%s] Fail, buffer size is too small\n", __func__); - return -EFAULT; - } - - vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; - _rtw_memset(extra, 0, length); - - pstring = extra; - pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask); - - for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++) - pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]); - - length = pstring - extra; - return length; -} - -int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra) -{ - int j; - char *pstring; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u32 vendor_ie_mask = 0; - __u16 length = 0; - - vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; - pstring = extra; - pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask); - - if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[Beacon]"); - if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[Probe Req]"); - if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[Probe Resp]"); - if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[Assoc Req]"); - if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[Assoc Resp]"); -#ifdef CONFIG_P2P - if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[P2P_Probe Req]"); - if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT) - pstring += sprintf(pstring , "[P2P_Probe Resp]"); -#endif - - pstring += sprintf(pstring , "\nVendor IE:\n"); - for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num] ; j++) - pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]); - - length = pstring - extra; - return length; - -} - -int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - int ret = 0, vendor_ie_num = 0, cmdlen; - struct iw_point *p; - u8 *ptmp; - - p = &wrqu->data; - cmdlen = p->length; - if (0 == cmdlen) - return -EINVAL; - - ptmp = (u8 *)rtw_malloc(cmdlen); - if (NULL == ptmp) - return -ENOMEM; - - if (copy_from_user(ptmp, p->pointer, cmdlen)) { - ret = -EFAULT; - goto exit; - } - ret = sscanf(ptmp , "%d", &vendor_ie_num); - if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { - ret = -EFAULT; - goto exit; - } - - wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra); - -exit: - rtw_mfree(ptmp, cmdlen); - - return 0; -} - -int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u32 vendor_ie_mask = 0; - u32 vendor_ie_num = 0; - u32 vendor_ie_mask_max = BIT(WLAN_MAX_VENDOR_IE_MASK_MAX) - 1; - u32 id, elen; - - ret = sscanf(extra, "%d,%x,%*s", &vendor_ie_num , &vendor_ie_mask); - if (strrchr(extra , ',')) - extra = strrchr(extra , ',') + 1; - else - return -EINVAL; - totoal_ie_len = strlen(extra); - RTW_INFO("[%s] vendor_ie_num = %d , vendor_ie_mask = 0x%x , vendor_ie = %s , len = %d\n", __func__ , vendor_ie_num , vendor_ie_mask , extra , totoal_ie_len); - - if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { - RTW_INFO("[%s] Fail, only support %d vendor ie\n", __func__ , WLAN_MAX_VENDOR_IE_NUM); - return -EFAULT; - } - - if (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) { - RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_VENDOR_IE_LEN); - return -EFAULT; - } - - if (vendor_ie_mask > vendor_ie_mask_max) { - RTW_INFO("[%s] Fail, not support vendor_ie_mask more than 0x%x\n", __func__ , vendor_ie_mask_max); - return -EFAULT; - } - - if (vendor_ie_mask == 0) { - RTW_INFO("[%s] Clear vendor_ie_num %d group\n", __func__ , vendor_ie_num); - goto _clear_path; - } - - if (totoal_ie_len % 2 != 0) { - RTW_INFO("[%s] Fail , IE length = %zu is odd\n" , __func__ , strlen(extra)); - return -EFAULT; - } - - if (totoal_ie_len > 0) { - for (i = 0 ; i < strlen(extra) ; i += 2) { - pmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]); - if (len == 0) { - id = pmlmepriv->vendor_ie[vendor_ie_num][len]; - if (id != WLAN_EID_VENDOR_SPECIFIC) { - RTW_INFO("[%s] Fail , VENDOR SPECIFIC IE ID \"%x\" was not correct\n", __func__ , id); - goto _clear_path; - } - } else if (len == 1) { - total_ie_len_byte = (totoal_ie_len / 2) - 2; - elen = pmlmepriv->vendor_ie[vendor_ie_num][len]; - if (elen != total_ie_len_byte) { - RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen , - total_ie_len_byte); - goto _clear_path; - } - } - len++; - } - pmlmepriv->vendor_ielen[vendor_ie_num] = len; - } else - pmlmepriv->vendor_ielen[vendor_ie_num] = 0; - - - - if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT) - RTW_INFO("[%s] Beacon append vendor ie\n", __func__); - if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT) - RTW_INFO("[%s] Probe Req append vendor ie\n", __func__); - if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT) - RTW_INFO("[%s] Probe Resp append vendor ie\n", __func__); - if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT) - RTW_INFO("[%s] Assoc Req append vendor ie\n", __func__); - if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT) - RTW_INFO("[%s] Assoc Resp append vendor ie\n", __func__); -#ifdef CONFIG_P2P - if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT) - RTW_INFO("[%s] P2P Probe Req append vendor ie\n", __func__); - if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT) - RTW_INFO("[%s] P2P Probe Resp append vendor ie\n", __func__); -#endif - - pmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask; - - return ret; - -_clear_path: - _rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN); - pmlmepriv->vendor_ielen[vendor_ie_num] = 0; - pmlmepriv->vendor_ie_mask[vendor_ie_num] = 0; - return -EFAULT; -} -#endif - -static int rtw_mp_efuse_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) -{ - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - PEFUSE_HAL pEfuseHal; - struct iw_point *wrqu; - - u8 ips_mode = IPS_NUM; /* init invalid value */ - u8 lps_mode = PS_MODE_NUM; /* init invalid value */ - struct pwrctrl_priv *pwrctrlpriv ; - u8 *data = NULL; - u8 *rawdata = NULL; - char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; - u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0; - u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0; - u16 mask_len; - u8 mask_buf[64] = ""; - int err; - char *pextra = NULL; -#ifdef CONFIG_IOL - u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */ -#endif - - wrqu = (struct iw_point *)wdata; - pwrctrlpriv = adapter_to_pwrctl(padapter); - pEfuseHal = &pHalData->EfuseHal; - - err = 0; - data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); - if (data == NULL) { - err = -ENOMEM; - goto exit; - } - rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); - if (rawdata == NULL) { - err = -ENOMEM; - goto exit; - } - - if (copy_from_user(extra, wrqu->pointer, wrqu->length)) { - err = -EFAULT; - goto exit; - } - - *(extra + wrqu->length) = '\0'; - -#ifdef CONFIG_LPS - lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ - rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); -#endif - -#ifdef CONFIG_IPS - ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ - rtw_pm_set_ips(padapter, IPS_NONE); -#endif - - pch = extra; - RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); - - i = 0; - /* mac 16 "00e04c871200" rmap,00,2 */ - while ((token = strsep(&pch, ",")) != NULL) { - if (i > 2) - break; - tmp[i] = token; - i++; - } -#ifdef CONFIG_IOL - padapter->registrypriv.fw_iol = 0;/* 0:Disable, 1:enable, 2:by usb speed */ -#endif - - if (strcmp(tmp[0], "status") == 0) { - sprintf(extra, "Load File efuse=%s,Load File MAC=%s" - , pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" - , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" - ); - goto exit; - } else if (strcmp(tmp[0], "drvmap") == 0) { - static u8 drvmaporder = 0; - u8 *efuse; - u32 shift, cnt; - u32 blksz = 0x200; /* The size of one time show, default 512 */ - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); - - efuse = pHalData->efuse_eeprom_data; - - shift = blksz * drvmaporder; - efuse += shift; - cnt = mapLen - shift; - - if (cnt > blksz) { - cnt = blksz; - drvmaporder++; - } else - drvmaporder = 0; - - sprintf(extra, "\n"); - for (i = 0; i < cnt; i += 16) { - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%02x\t", shift + i); - for (j = 0; j < 8; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\n"); - } - if ((shift + cnt) < mapLen) - pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); - - } else if (strcmp(tmp[0], "realmap") == 0) { - static u8 order = 0; - u8 *efuse; - u32 shift, cnt; - u32 blksz = 0x200; /* The size of one time show, default 512 */ - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE); - efuse = pEfuseHal->fakeEfuseInitMap; - if (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) { - RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - -#if 0 - RTW_INFO("OFFSET\tVALUE(hex)\n"); - for (i = 0; i < mapLen; i += 16) { - RTW_INFO("0x%02x\t", i); - for (j = 0; j < 8; j++) - RTW_INFO("%02X ", efuse[i + j]); - RTW_INFO("\t"); - for (; j < 16; j++) - RTW_INFO("%02X ", efuse[i + j]); - RTW_INFO("\n"); - } - RTW_INFO("\n"); -#endif - - shift = blksz * order; - efuse += shift; - cnt = mapLen - shift; - if (cnt > blksz) { - cnt = blksz; - order++; - } else - order = 0; - - sprintf(extra, "\n"); - for (i = 0; i < cnt; i += 16) { - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%02x\t", shift + i); - for (j = 0; j < 8; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\n"); - } - if ((shift + cnt) < mapLen) - pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); - } else if (strcmp(tmp[0], "rmap") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - - /* rmap addr cnts */ - addr = simple_strtoul(tmp[1], &ptmp, 16); - RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); - - cnts = simple_strtoul(tmp[2], &ptmp, 10); - if (cnts == 0) { - RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EINVAL; - goto exit; - } - - if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { - RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__); - err = -EFAULT; - goto exit; - } - - /* RTW_INFO("%s: data={", __FUNCTION__); */ - *extra = 0; - pextra = extra; - for (i = 0; i < cnts; i++) { - /* RTW_INFO("0x%02x ", data[i]); */ - pextra += sprintf(pextra, "0x%02X ", data[i]); - } - /* RTW_INFO("}\n"); */ - } else if (strcmp(tmp[0], "realraw") == 0) { - static u8 raw_order = 0; - u32 shift, cnt; - u32 blksz = 0x200; /* The size of one time show, default 512 */ - - addr = 0; - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (void *)&mapLen, _FALSE); - RTW_INFO("Real content len = %d\n",mapLen ); - - if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); - err = -EFAULT; - goto exit; - } - - _rtw_memset(extra, '\0', strlen(extra)); - - shift = blksz * raw_order; - rawdata += shift; - cnt = mapLen - shift; - if (cnt > blksz) { - cnt = blksz; - raw_order++; - } else - raw_order = 0; - - sprintf(extra, "\n"); - for (i = 0; i < cnt; i += 16) { - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%02x\t", shift + i); - for (j = 0; j < 8; j++) - pextra += sprintf(pextra, "%02X ", rawdata[i + j]); - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) - pextra += sprintf(pextra, "%02X ", rawdata[i + j]); - pextra += sprintf(pextra, "\n"); - } - if ((shift + cnt) < mapLen) - pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); - - } else if (strcmp(tmp[0], "btrealraw") == 0) { - static u8 bt_raw_order = 0; - u32 shift, cnt; - u32 blksz = 0x200; /* The size of one time show, default 512 */ - - addr = 0; - EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&mapLen, _FALSE); - RTW_INFO("Real content len = %d\n", mapLen); -#ifdef RTW_HALMAC - if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); - err = -EFAULT; - goto exit; - } -#else - rtw_write8(padapter, 0x35, 0x1); - - if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); - err = -EFAULT; - goto exit; - } -#endif - _rtw_memset(extra, '\0', strlen(extra)); - - shift = blksz * bt_raw_order; - rawdata += shift; - cnt = mapLen - shift; - if (cnt > blksz) { - cnt = blksz; - bt_raw_order++; - } else - bt_raw_order = 0; - - sprintf(extra, "\n"); - for (i = 0; i < cnt; i += 16) { - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%02x\t", shift + i); - for (j = 0; j < 8; j++) - pextra += sprintf(pextra, "%02X ", rawdata[i + j]); - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) - pextra += sprintf(pextra, "%02X ", rawdata[i + j]); - pextra += sprintf(pextra, "\n"); - } - if ((shift + cnt) < mapLen) - pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); - - } else if (strcmp(tmp[0], "mac") == 0) { - if (hal_efuse_macaddr_offset(padapter) == -1) { - err = -EFAULT; - goto exit; - } - - addr = hal_efuse_macaddr_offset(padapter); - cnts = 6; - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } - - if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { - RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__); - err = -EFAULT; - goto exit; - } - - /* RTW_INFO("%s: MAC address={", __FUNCTION__); */ - *extra = 0; - pextra = extra; - for (i = 0; i < cnts; i++) { - /* RTW_INFO("%02X", data[i]); */ - pextra += sprintf(pextra, "%02X", data[i]); - if (i != (cnts - 1)) { - /* RTW_INFO(":"); */ - pextra += sprintf(pextra, ":"); - } - } - /* RTW_INFO("}\n"); */ - } else if (strcmp(tmp[0], "vidpid") == 0) { -#ifdef CONFIG_RTL8188E -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_88EU; -#endif -#ifdef CONFIG_PCI_HCI - addr = EEPROM_VID_88EE; -#endif -#endif /* CONFIG_RTL8188E */ - -#ifdef CONFIG_RTL8192E -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8192EU; -#endif -#ifdef CONFIG_PCI_HCI - addr = EEPROM_VID_8192EE; -#endif -#endif /* CONFIG_RTL8192E */ -#ifdef CONFIG_RTL8723B - addr = EEPROM_VID_8723BU; -#endif /* CONFIG_RTL8192E */ - -#ifdef CONFIG_RTL8188F - addr = EEPROM_VID_8188FU; -#endif /* CONFIG_RTL8188F */ - -#ifdef CONFIG_RTL8188GTV - addr = EEPROM_VID_8188GTVU; -#endif - -#ifdef CONFIG_RTL8703B -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8703BU; -#endif -#endif /* CONFIG_RTL8703B */ - -#ifdef CONFIG_RTL8723D -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8723DU; -#endif /* CONFIG_USB_HCI */ -#endif /* CONFIG_RTL8723D */ - - cnts = 4; - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } - if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - - /* RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */ - *extra = 0; - pextra = extra; - for (i = 0; i < cnts; i++) { - /* RTW_INFO("0x%02x", data[i]); */ - pextra += sprintf(pextra, "0x%02X", data[i]); - if (i != (cnts - 1)) { - /* RTW_INFO(","); */ - pextra += sprintf(pextra, ","); - } - } - /* RTW_INFO("}\n"); */ - } else if (strcmp(tmp[0], "ableraw") == 0) { -#ifdef RTW_HALMAC - raw_maxsize = efuse_GetavailableSize(padapter); -#else - efuse_GetCurrentSize(padapter, &raw_cursize); - raw_maxsize = efuse_GetMaxSize(padapter); -#endif - sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize); - } else if (strcmp(tmp[0], "btableraw") == 0) { - efuse_bt_GetCurrentSize(padapter, &raw_cursize); - raw_maxsize = efuse_bt_GetMaxSize(padapter); - sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize); - } else if (strcmp(tmp[0], "btfmap") == 0) { - - BTEfuse_PowerSwitch(padapter, 1, _TRUE); - - mapLen = EFUSE_BT_MAX_MAP_LEN; - if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) { - RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - - /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ - sprintf(extra, "\n"); - for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ - /* RTW_INFO("0x%03x\t", i); */ - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%03x\t", i); - for (j = 0; j < 8; j++) { - /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); - } - /* RTW_INFO("\t"); */ - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) { - /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); - } - /* RTW_INFO("\n"); */ - pextra += sprintf(pextra, "\n"); - } - /* RTW_INFO("\n"); */ - } else if (strcmp(tmp[0], "btbmap") == 0) { - BTEfuse_PowerSwitch(padapter, 1, _TRUE); - - mapLen = EFUSE_BT_MAX_MAP_LEN; - if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) { - RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - - /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ - sprintf(extra, "\n"); - for (i = 512; i < 1024 ; i += 16) { - /* RTW_INFO("0x%03x\t", i); */ - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%03x\t", i); - for (j = 0; j < 8; j++) { - /* RTW_INFO("%02X ", data[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); - } - /* RTW_INFO("\t"); */ - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) { - /* RTW_INFO("%02X ", data[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); - } - /* RTW_INFO("\n"); */ - pextra += sprintf(pextra, "\n"); - } - /* RTW_INFO("\n"); */ - } else if (strcmp(tmp[0], "btrmap") == 0) { - u8 BTStatus; - - rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */ - BTStatus = rtw_read8(padapter, 0xa0); - - RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); - if (BTStatus != 0x04) { - sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n"); - goto exit; - } - - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - - BTEfuse_PowerSwitch(padapter, 1, _TRUE); - - /* rmap addr cnts */ - addr = simple_strtoul(tmp[1], &ptmp, 16); - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - - cnts = simple_strtoul(tmp[2], &ptmp, 10); - if (cnts == 0) { - RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); -#ifndef RTW_HALMAC - EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } -#endif - if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) { - RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - - *extra = 0; - pextra = extra; - /* RTW_INFO("%s: bt efuse data={", __FUNCTION__); */ - for (i = 0; i < cnts; i++) { - /* RTW_INFO("0x%02x ", data[i]); */ - pextra += sprintf(pextra, " 0x%02X ", data[i]); - } - /* RTW_INFO("}\n"); */ - RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra); - } else if (strcmp(tmp[0], "btffake") == 0) { - /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ - sprintf(extra, "\n"); - for (i = 0; i < 512; i += 16) { - /* RTW_INFO("0x%03x\t", i); */ - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%03x\t", i); - for (j = 0; j < 8; j++) { - /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); - } - /* RTW_INFO("\t"); */ - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) { - /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); - } - /* RTW_INFO("\n"); */ - pextra += sprintf(pextra, "\n"); - } - /* RTW_INFO("\n"); */ - } else if (strcmp(tmp[0], "btbfake") == 0) { - /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ - sprintf(extra, "\n"); - for (i = 512; i < 1024; i += 16) { - /* RTW_INFO("0x%03x\t", i); */ - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%03x\t", i); - for (j = 0; j < 8; j++) { - /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); - } - /* RTW_INFO("\t"); */ - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) { - /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); - } - /* RTW_INFO("\n"); */ - pextra += sprintf(pextra, "\n"); - } - /* RTW_INFO("\n"); */ - } else if (strcmp(tmp[0], "wlrfkmap") == 0) { - static u8 fk_order = 0; - u8 *efuse; - u32 shift, cnt; - u32 blksz = 0x200; /* The size of one time show, default 512 */ - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE); - efuse = pEfuseHal->fakeEfuseModifiedMap; - - shift = blksz * fk_order; - efuse += shift; - cnt = mapLen - shift; - if (cnt > blksz) { - cnt = blksz; - fk_order++; - } else - fk_order = 0; - - sprintf(extra, "\n"); - for (i = 0; i < cnt; i += 16) { - pextra = extra + strlen(extra); - pextra += sprintf(pextra, "0x%02x\t", shift + i); - for (j = 0; j < 8; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\t"); - for (; j < 16; j++) - pextra += sprintf(pextra, "%02X ", efuse[i + j]); - pextra += sprintf(pextra, "\n"); - } - if ((shift + cnt) < mapLen) - pextra += sprintf(pextra, "\t...more\n"); - - } else if (strcmp(tmp[0], "wlrfkrmap") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - /* rmap addr cnts */ - addr = simple_strtoul(tmp[1], &ptmp, 16); - RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); - - cnts = simple_strtoul(tmp[2], &ptmp, 10); - if (cnts == 0) { - RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - - /* RTW_INFO("%s: data={", __FUNCTION__); */ - *extra = 0; - pextra = extra; - for (i = 0; i < cnts; i++) { - RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]); - pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]); - } - } else if (strcmp(tmp[0], "btrfkrmap") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - /* rmap addr cnts */ - addr = simple_strtoul(tmp[1], &ptmp, 16); - RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); - - cnts = simple_strtoul(tmp[2], &ptmp, 10); - if (cnts == 0) { - RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); - err = -EINVAL; - goto exit; - } - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - - /* RTW_INFO("%s: data={", __FUNCTION__); */ - *extra = 0; - pextra = extra; - for (i = 0; i < cnts; i++) { - RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); - pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]); - } - } else if (strcmp(tmp[0], "mask") == 0) { - *extra = 0; - mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter); - rtw_efuse_mask_array(padapter, mask_buf); - - if (padapter->registrypriv.bFileMaskEfuse == _TRUE) - _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); - - sprintf(extra, "\n"); - pextra = extra + strlen(extra); - for (i = 0; i < mask_len; i++) - pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]); - - } else if (strcmp(tmp[0], "btmask") == 0) { - *extra = 0; - mask_len = sizeof(u8) * rtw_get_bt_efuse_mask_arraylen(padapter); - rtw_bt_efuse_mask_array(padapter, mask_buf); - - if (padapter->registrypriv.bBTFileMaskEfuse == _TRUE) - _rtw_memcpy(mask_buf, btmaskfileBuffer, mask_len); - - sprintf(extra, "\n"); - pextra = extra + strlen(extra); - for (i = 0; i < mask_len; i++) - pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]); - - } else - sprintf(extra, "Command not found!"); - -exit: - if (data) - rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN); - if (rawdata) - rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN); - if (!err) - wrqu->length = strlen(extra); - - if (padapter->registrypriv.mp_mode == 0) { -#ifdef CONFIG_IPS - rtw_pm_set_ips(padapter, ips_mode); -#endif /* CONFIG_IPS */ - -#ifdef CONFIG_LPS - rtw_pm_set_lps(padapter, lps_mode); -#endif /* CONFIG_LPS */ - } - -#ifdef CONFIG_IOL - padapter->registrypriv.fw_iol = org_fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */ -#endif - return err; -} - - -#ifdef CONFIG_MP_INCLUDED -static int rtw_mp_efuse_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) -{ - struct iw_point *wrqu; - PADAPTER padapter; - struct pwrctrl_priv *pwrctrlpriv ; - PHAL_DATA_TYPE pHalData; - PEFUSE_HAL pEfuseHal; - struct hal_ops *pHalFunc; - struct mp_priv *pmp_priv; - - u8 ips_mode = IPS_NUM; /* init invalid value */ - u8 lps_mode = PS_MODE_NUM; /* init invalid value */ - u32 i = 0, j = 0, jj, kk; - u8 *setdata = NULL; - u8 *ShadowMapBT = NULL; - u8 *ShadowMapWiFi = NULL; - u8 *setrawdata = NULL; - char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; - u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0; - u16 wifimaplen; - int err; - boolean bcmpchk = _TRUE; - - - wrqu = (struct iw_point *)wdata; - padapter = rtw_netdev_priv(dev); - pwrctrlpriv = adapter_to_pwrctl(padapter); - pHalData = GET_HAL_DATA(padapter); - pEfuseHal = &pHalData->EfuseHal; - pHalFunc = &padapter->hal_func; - pmp_priv = &padapter->mppriv; - - err = 0; - - if (copy_from_user(extra, wrqu->pointer, wrqu->length)) - return -EFAULT; -#ifdef CONFIG_RTL8822C - rtw_pre_bt_efuse(padapter); -#endif - *(extra + wrqu->length) = '\0'; - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE); - - setdata = rtw_zmalloc(1024); - if (setdata == NULL) { - err = -ENOMEM; - goto exit; - } - ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN); - if (ShadowMapBT == NULL) { - err = -ENOMEM; - goto exit; - } - ShadowMapWiFi = rtw_malloc(wifimaplen); - if (ShadowMapWiFi == NULL) { - err = -ENOMEM; - goto exit; - } - setrawdata = rtw_malloc(EFUSE_MAX_SIZE); - if (setrawdata == NULL) { - err = -ENOMEM; - goto exit; - } - -#ifdef CONFIG_LPS - lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ - rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); -#endif - -#ifdef CONFIG_IPS - ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ - rtw_pm_set_ips(padapter, IPS_NONE); -#endif - - pch = extra; - RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); - - i = 0; - while ((token = strsep(&pch, ",")) != NULL) { - if (i > 2) - break; - tmp[i] = token; - i++; - } - - /* tmp[0],[1],[2] */ - /* wmap,addr,00e04c871200 */ - if (strcmp(tmp[0], "wmap") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - -#ifndef RTW_HALMAC - /* unknown bug workaround, need to fix later */ - addr = 0x1ff; - rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 3, 0x72); - rtw_msleep_os(10); - rtw_read8(padapter, EFUSE_CTRL); -#endif /* RTW_HALMAC */ - - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } - - if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - *extra = 0; - RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__); - if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) { - if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) { - RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__); - sprintf(extra, "WiFi write map compare OK\n"); - err = 0; - goto exit; - } else { - sprintf(extra, "WiFi write map compare FAIL\n"); - RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); - err = 0; - goto exit; - } - } - } else if (strcmp(tmp[0], "wraw") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); - - if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - } else if (strcmp(tmp[0], "btwraw") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); -#ifdef RTW_HALMAC - if (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } -#else - rtw_write8(padapter, 0x35, 1); /* switch bank 1 (BT)*/ - if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); - rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/ - err = -EFAULT; - goto exit; - } - rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/ -#endif - } else if (strcmp(tmp[0], "mac") == 0) { - if (tmp[1] == NULL) { - err = -EINVAL; - goto exit; - } - - /* mac,00e04c871200 */ - - if (hal_efuse_macaddr_offset(padapter) == -1) { - err = -EFAULT; - goto exit; - } - - addr = hal_efuse_macaddr_offset(padapter); - cnts = strlen(tmp[1]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - if (cnts > 6) { - RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); - err = -EFAULT; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } - - if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - } else if (strcmp(tmp[0], "vidpid") == 0) { - if (tmp[1] == NULL) { - err = -EINVAL; - goto exit; - } - - /* pidvid,da0b7881 */ -#ifdef CONFIG_RTL8188E -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_88EU; -#endif -#ifdef CONFIG_PCI_HCI - addr = EEPROM_VID_88EE; -#endif -#endif /* CONFIG_RTL8188E */ - -#ifdef CONFIG_RTL8192E -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8192EU; -#endif -#ifdef CONFIG_PCI_HCI - addr = EEPROM_VID_8192EE; -#endif -#endif /* CONFIG_RTL8188E */ - -#ifdef CONFIG_RTL8723B - addr = EEPROM_VID_8723BU; -#endif - -#ifdef CONFIG_RTL8188F - addr = EEPROM_VID_8188FU; -#endif - -#ifdef CONFIG_RTL8188GTV - addr = EEPROM_VID_8188GTVU; -#endif - -#ifdef CONFIG_RTL8703B -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8703BU; -#endif /* CONFIG_USB_HCI */ -#endif /* CONFIG_RTL8703B */ - -#ifdef CONFIG_RTL8723D -#ifdef CONFIG_USB_HCI - addr = EEPROM_VID_8723DU; -#endif /* CONFIG_USB_HCI */ -#endif /* CONFIG_RTL8723D */ - - cnts = strlen(tmp[1]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } - - if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - } else if (strcmp(tmp[0], "wldumpfake") == 0) { - if (wifimaplen > EFUSE_MAX_MAP_LEN) - cnts = EFUSE_MAX_MAP_LEN; - else - cnts = wifimaplen; - if (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS) - RTW_INFO("%s: WiFi hw efuse dump to Fake map success\n", __func__); - else { - RTW_INFO("%s: WiFi hw efuse dump to Fake map Fail\n", __func__); - err = -EFAULT; - } - } else if (strcmp(tmp[0], "btwmap") == 0) { - rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */ - BTStatus = rtw_read8(padapter, 0xa0); - RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); - if (BTStatus != 0x04) { - sprintf(extra, "BT Status not Active ,can't do Write\n"); - goto exit; - } - - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - -#ifndef RTW_HALMAC - BTEfuse_PowerSwitch(padapter, 1, _TRUE); - addr = 0x1ff; - rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 3, 0x72); - rtw_msleep_os(10); - rtw_read8(padapter, EFUSE_CTRL); - BTEfuse_PowerSwitch(padapter, 1, _FALSE); -#endif /* RTW_HALMAC */ - - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: BT data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); -#ifndef RTW_HALMAC - EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE); - if ((addr + cnts) > max_available_len) { - RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); - err = -EFAULT; - goto exit; - } -#endif - if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { - RTW_INFO("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__); - sprintf(extra, "BT write FAIL !!!\n"); - err = -EFAULT; - goto exit; - } - *extra = 0; - RTW_INFO("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __FUNCTION__); - if ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) { - if (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) { - RTW_INFO("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__, BTStatus); - sprintf(extra, "BT write map compare OK"); - err = 0; - goto exit; - } else { - sprintf(extra, "BT write map compare FAIL"); - RTW_INFO("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__, BTStatus); - err = 0; - goto exit; - } - } - } else if (strcmp(tmp[0], "btwfake") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - if (pmp_priv->bprocess_mp_mode != _TRUE) { - RTW_INFO("%s: btwfake not to be exec, please first to mp_start\n", __FUNCTION__); - sprintf(extra, "Error, btwfake cant to be exec, please first to mp_start !!!!\n"); - err = 0; - goto exit; - } - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - pEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); - } else if (strcmp(tmp[0], "btdumpfake") == 0) { - if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS) - RTW_INFO("%s: BT read all map success\n", __FUNCTION__); - else { - RTW_INFO("%s: BT read all map Fail!\n", __FUNCTION__); - err = -EFAULT; - } - } else if (strcmp(tmp[0], "btfk2map") == 0) { -#ifdef CONFIG_BT_EFUSE_MASK - if (padapter->registrypriv.bBTFileMaskEfuse != _TRUE && pmp_priv->bloadBTefusemap == _TRUE) { - RTW_INFO("%s: File BT eFuse mask file not to be loaded\n", __FUNCTION__); - sprintf(extra, "Not load BT eFuse mask file yet, Please advance to use [ efuse_bt_mask ], now remove the Adapter.!!!!\n"); - rtw_set_surprise_removed(padapter); - err = 0; - goto exit; - } -#endif - rtw_write8(padapter, 0xa3, 0x05); - BTStatus = rtw_read8(padapter, 0xa0); - RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); - if (BTStatus != 0x04) { - sprintf(extra, "BT Status not Active Write FAIL\n"); - goto exit; - } - if (pmp_priv->bprocess_mp_mode != _TRUE) { - RTW_INFO("%s: btfk2map not to be exec, please first to mp_start\n", __FUNCTION__); - sprintf(extra, "Error, btfk2map cant to be exec, please first to mp_start !!!!\n"); - err = 0; - goto exit; - } -#ifndef RTW_HALMAC - BTEfuse_PowerSwitch(padapter, 1, _TRUE); - addr = 0x1ff; - rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03)); - rtw_msleep_os(10); - rtw_write8(padapter, EFUSE_CTRL + 3, 0x72); - rtw_msleep_os(10); - rtw_read8(padapter, EFUSE_CTRL); - BTEfuse_PowerSwitch(padapter, 1, _FALSE); -#endif /* RTW_HALMAC */ - - if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) { - RTW_INFO("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__); - sprintf(extra, "BT write FAIL !!!\n"); - err = -EFAULT; - goto exit; - } - - RTW_INFO("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n"); - for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) { - printk("0x%02x\t", i); - for (j = 0; j < 8; j++) - printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]); - printk("\t"); - - for (; j < 16; j++) - printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]); - printk("\n"); - } - printk("\n"); -#if 1 - err = -EFAULT; - RTW_INFO("%s: rtw_BT_efuse_map_read _rtw_memcmp\n", __FUNCTION__); - if ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) { - if (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) { - sprintf(extra, "BT write map compare OK"); - RTW_INFO("%s: BT write map afterf compare success BTStatus=0x%x\n", __FUNCTION__, BTStatus); - err = 0; - goto exit; - } else { - sprintf(extra, "BT write map compare FAIL"); - if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) - RTW_INFO("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__, i); - - if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) { - RTW_INFO("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n"); - - for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) { - printk("0x%02x\t", i); - for (j = 0; j < 8; j++) - printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]); - printk("\t"); - for (; j < 16; j++) - printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]); - printk("\n"); - } - printk("\n"); - } - RTW_INFO("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__, BTStatus); - goto exit; - } - } -#endif - - } else if (strcmp(tmp[0], "wlfk2map") == 0) { - *extra = 0; - - if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) { - RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__); - sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n"); - rtw_set_surprise_removed(padapter); - err = 0; - goto exit; - } - - if (pmp_priv->bprocess_mp_mode != _TRUE) { - RTW_INFO("%s: wlfk2map not to be exec, please first to mp_start\n", __FUNCTION__); - sprintf(extra, "Error, wlfk2map cant to be exec, please first to mp_start !!!!\n"); - err = 0; - goto exit; - } - if (wifimaplen > EFUSE_MAX_MAP_LEN) - cnts = EFUSE_MAX_MAP_LEN; - else - cnts = wifimaplen; - if (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) { - RTW_INFO("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__); - err = -EFAULT; - goto exit; - } - - if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) { - addr = 0x00; - err = _TRUE; - - for (i = 0; i < cnts; i++) { - if (padapter->registrypriv.boffefusemask == 0) { - if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { - if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer) == _TRUE) /*use file efuse mask. */ - bcmpchk = _FALSE; - } else { - if (efuse_IsMasked(padapter, addr + i) == _TRUE) - bcmpchk = _FALSE; - } - } - - if (bcmpchk == _TRUE) { - RTW_INFO("compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\n", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]); - if (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){ - err = _FALSE; - break; - } - } - bcmpchk = _TRUE; - } - } - - if (err) { - RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__); - sprintf(extra, "WiFi write map compare OK\n"); - err = 0; - goto exit; - } else { - sprintf(extra, "WiFi write map compare FAIL\n"); - RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); - err = 0; - goto exit; - } - } else if (strcmp(tmp[0], "wlwfake") == 0) { - if ((tmp[1] == NULL) || (tmp[2] == NULL)) { - err = -EINVAL; - goto exit; - } - if (pmp_priv->bprocess_mp_mode != _TRUE) { - RTW_INFO("%s: wlwfake not to be exec, please first to mp_start\n", __FUNCTION__); - sprintf(extra, "Error, wlwfake cant to be exec, please first to mp_start !!!!\n"); - err = 0; - goto exit; - } - addr = simple_strtoul(tmp[1], &ptmp, 16); - addr &= 0xFFF; - - cnts = strlen(tmp[2]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; + if (totoal_ie_len > 0) { + for (i = 0 ; i < strlen(extra) ; i += 2) { + pmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]); + if (len == 0) { + id = pmlmepriv->vendor_ie[vendor_ie_num][len]; + if (id != WLAN_EID_VENDOR_SPECIFIC) { + RTW_INFO("[%s] Fail , VENDOR SPECIFIC IE ID \"%x\" was not correct\n", __func__ , id); + goto _clear_path; + } + } else if (len == 1) { + total_ie_len_byte = (totoal_ie_len / 2) - 2; + elen = pmlmepriv->vendor_ie[vendor_ie_num][len]; + if (elen != total_ie_len_byte) { + RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen , + total_ie_len_byte); + goto _clear_path; + } + } + len++; } + pmlmepriv->vendor_ielen[vendor_ie_num] = len; + } else + pmlmepriv->vendor_ielen[vendor_ie_num] = 0; - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "wlwfake OK\n"); - } - else if (strcmp(tmp[0], "wfakemac") == 0) { - if (tmp[1] == NULL) { - err = -EINVAL; - goto exit; - } - if (pmp_priv->bprocess_mp_mode != _TRUE) { - RTW_INFO("%s: wfakemac not to be exec, please first to mp_start\n", __FUNCTION__); - sprintf(extra, "Error, wfakemac cant to be exec, please first to mp_start !!!!\n"); - err = 0; - goto exit; - } - /* wfakemac,00e04c871200 */ - if (hal_efuse_macaddr_offset(padapter) == -1) { - err = -EFAULT; - goto exit; - } - addr = hal_efuse_macaddr_offset(padapter); - cnts = strlen(tmp[1]); - if (cnts % 2) { - err = -EINVAL; - goto exit; - } - cnts /= 2; - if (cnts == 0) { - err = -EINVAL; - goto exit; - } - if (cnts > 6) { - RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); - err = -EFAULT; - goto exit; - } + if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT) + RTW_INFO("[%s] Beacon append vendor ie\n", __func__); + if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT) + RTW_INFO("[%s] Probe Req append vendor ie\n", __func__); + if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT) + RTW_INFO("[%s] Probe Resp append vendor ie\n", __func__); + if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT) + RTW_INFO("[%s] Assoc Req append vendor ie\n", __func__); + if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT) + RTW_INFO("[%s] Assoc Resp append vendor ie\n", __func__); +#ifdef CONFIG_P2P + if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT) + RTW_INFO("[%s] P2P Probe Req append vendor ie\n", __func__); + if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT) + RTW_INFO("[%s] P2P Probe Resp append vendor ie\n", __func__); +#endif - RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); - RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) - if ((addr + jj) < EFUSE_MAX_MAP_LEN) - pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); - - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "write mac addr to fake map OK\n"); - } else if(strcmp(tmp[0], "update") == 0) { - RTW_INFO("To Use new eFuse map ver3\n"); - if (tmp[1] != 0x00) { - pmp_priv->efuse_update_file = _TRUE; - strcpy(pmp_priv->efuse_file_path , tmp[1]); - RTW_INFO("Got file path %s\n", pmp_priv->efuse_file_path); - } - /*step read efuse/eeprom data and get mac_addr*/ - if (padapter->hal_func.read_adapter_info(padapter)) { - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "eFuse Update OK\n"); - RTW_INFO("eFuse Update OK\n"); - } else { - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "eFuse Update FAIL\n"); - RTW_INFO("eFuse Update FAIL\n"); - } - pmp_priv->efuse_update_file = _FALSE; - RTW_INFO("To Use new eFuse map done ver3\n"); - } else if (strcmp(tmp[0], "analyze") == 0) { + pmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask; - rtw_efuse_analyze(padapter, EFUSE_WIFI, 0); - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "eFuse Analyze OK,please to check kernel log\n"); - } -exit: - if (setdata) - rtw_mfree(setdata, 1024); - if (ShadowMapBT) - rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN); - if (ShadowMapWiFi) - rtw_mfree(ShadowMapWiFi, wifimaplen); - if (setrawdata) - rtw_mfree(setrawdata, EFUSE_MAX_SIZE); + return ret; - wrqu->length = strlen(extra); +_clear_path: + _rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN); + pmlmepriv->vendor_ielen[vendor_ie_num] = 0; + pmlmepriv->vendor_ie_mask[vendor_ie_num] = 0; + return -EFAULT; +} +#endif - if (padapter->registrypriv.mp_mode == 0) { -#ifdef CONFIG_IPS - rtw_pm_set_ips(padapter, ips_mode); -#endif /* CONFIG_IPS */ +#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE) +int rtw_phl_test_set(struct net_device *dev, + struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 mode = 0; + u32 bytes = 0; + int ret = 0; -#ifdef CONFIG_LPS - rtw_pm_set_lps(padapter, lps_mode); -#endif /* CONFIG_LPS */ - } +#if defined(RTW_PHL_DBG_CMD) + core_cmd_phl_handler(padapter, extra); +#endif - return err; +exit: + return 0; } +#endif + #ifdef CONFIG_RTW_CUSTOMER_STR static int rtw_mp_customer_str( @@ -10015,271 +6358,25 @@ static int rtw_mp_customer_str( return 0; } #endif /* CONFIG_RTW_CUSTOMER_STR */ - -static int rtw_priv_mp_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) -{ - - struct iw_point *wrqu = (struct iw_point *)wdata; - u32 subcmd = wrqu->flags; - PADAPTER padapter = rtw_netdev_priv(dev); - int status = 0; - -#ifdef CONFIG_CONCURRENT_MODE - if (!is_primary_adapter(padapter)) { - RTW_INFO("MP mode only primary Adapter support\n"); - return -EIO; - } -#endif - - RTW_INFO("%s mutx in %d\n", __func__, subcmd); - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); - switch (subcmd) { - case CTA_TEST: - RTW_INFO("set CTA_TEST\n"); - status = rtw_cta_test_start(dev, info, wdata, extra); - break; - case MP_DISABLE_BT_COEXIST: - RTW_INFO("set case MP_DISABLE_BT_COEXIST\n"); - status = rtw_mp_disable_bt_coexist(dev, info, wdata, extra); - break; - case MP_IQK: - RTW_INFO("set MP_IQK\n"); - status = rtw_mp_iqk(dev, info, wrqu, extra); - break; - case MP_LCK: - RTW_INFO("set MP_LCK\n"); - status = rtw_mp_lck(dev, info, wrqu, extra); - break; - - default: - status = -EIO; - } - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); - RTW_INFO("%s mutx done %d\n", __func__, subcmd); - - return status; -} - -static int rtw_priv_mp_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) +#if 0 /*defined(CONFIG_MP_INCLUDED)*/ +static int rtw_cta_test_start(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_phl_com_t *phl_com = GET_PHL_COM(adapter_to_dvobj(padapter)); - struct iw_point *wrqu = (struct iw_point *)wdata; - u32 subcmd = wrqu->flags; - PADAPTER padapter = rtw_netdev_priv(dev); - int status = 0; - -#ifdef CONFIG_CONCURRENT_MODE - if (!is_primary_adapter(padapter)) { - RTW_INFO("MP mode only primary Adapter support\n"); - return -EIO; - } -#endif - - RTW_INFO("%s mutx in %d\n", __func__, subcmd); - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); - - switch (subcmd) { - case MP_START: - RTW_INFO("set case mp_start\n"); - status = rtw_mp_start(dev, info, wrqu, extra); - break; - case MP_STOP: - RTW_INFO("set case mp_stop\n"); - status = rtw_mp_stop(dev, info, wrqu, extra); - break; - case MP_BANDWIDTH: - RTW_INFO("set case mp_bandwidth\n"); - status = rtw_mp_bandwidth(dev, info, wrqu, extra); - break; - case MP_RESET_STATS: - RTW_INFO("set case MP_RESET_STATS\n"); - status = rtw_mp_reset_stats(dev, info, wrqu, extra); - break; - case MP_SetRFPathSwh: - RTW_INFO("set MP_SetRFPathSwitch\n"); - status = rtw_mp_SetRFPath(dev, info, wrqu, extra); - break; - case WRITE_REG: - status = rtw_mp_write_reg(dev, info, wrqu, extra); - break; - case WRITE_RF: - status = rtw_mp_write_rf(dev, info, wrqu, extra); - break; - case MP_PHYPARA: - RTW_INFO("mp_get MP_PHYPARA\n"); - status = rtw_mp_phypara(dev, info, wrqu, extra); - break; - case MP_CHANNEL: - RTW_INFO("set case mp_channel\n"); - status = rtw_mp_channel(dev , info, wrqu, extra); - break; - case MP_CHL_OFFSET: - RTW_INFO("set case mp_ch_offset\n"); - status = rtw_mp_ch_offset(dev , info, wrqu, extra); - break; - case READ_REG: - RTW_INFO("mp_get READ_REG\n"); - status = rtw_mp_read_reg(dev, info, wrqu, extra); - break; - case READ_RF: - RTW_INFO("mp_get READ_RF\n"); - status = rtw_mp_read_rf(dev, info, wrqu, extra); - break; - case MP_RATE: - RTW_INFO("set case mp_rate\n"); - status = rtw_mp_rate(dev, info, wrqu, extra); - break; - case MP_TXPOWER: - RTW_INFO("set case MP_TXPOWER\n"); - status = rtw_mp_txpower(dev, info, wrqu, extra); - break; - case MP_ANT_TX: - RTW_INFO("set case MP_ANT_TX\n"); - status = rtw_mp_ant_tx(dev, info, wrqu, extra); - break; - case MP_ANT_RX: - RTW_INFO("set case MP_ANT_RX\n"); - status = rtw_mp_ant_rx(dev, info, wrqu, extra); - break; - case MP_QUERY: - status = rtw_mp_trx_query(dev, info, wrqu, extra); - break; - case MP_CTX: - RTW_INFO("set case MP_CTX\n"); - status = rtw_mp_ctx(dev, info, wrqu, extra); - break; - case MP_ARX: - RTW_INFO("set case MP_ARX\n"); - status = rtw_mp_arx(dev, info, wrqu, extra); - break; - case MP_DUMP: - RTW_INFO("set case MP_DUMP\n"); - status = rtw_mp_dump(dev, info, wrqu, extra); - break; - case MP_PSD: - RTW_INFO("set case MP_PSD\n"); - status = rtw_mp_psd(dev, info, wrqu, extra); - break; - case MP_THER: - RTW_INFO("set case MP_THER\n"); - status = rtw_mp_thermal(dev, info, wrqu, extra); - break; - case MP_PwrCtlDM: - RTW_INFO("set MP_PwrCtlDM\n"); - status = rtw_mp_PwrCtlDM(dev, info, wrqu, extra); - break; - case MP_QueryDrvStats: - RTW_INFO("mp_get MP_QueryDrvStats\n"); - status = rtw_mp_QueryDrv(dev, info, wdata, extra); - break; - case MP_PWRTRK: - RTW_INFO("set case MP_PWRTRK\n"); - status = rtw_mp_pwrtrk(dev, info, wrqu, extra); - break; - case MP_SET_TSSIDE: - RTW_INFO("set case MP_TSSI_DE\n"); - status = rtw_mp_set_tsside(dev, info, wrqu, extra); - break; -#ifdef CONFIG_MP_INCLUDED - case EFUSE_SET: - RTW_INFO("set case efuse set\n"); - status = rtw_mp_efuse_set(dev, info, wdata, extra); - break; -#endif - case EFUSE_GET: - RTW_INFO("efuse get EFUSE_GET\n"); - status = rtw_mp_efuse_get(dev, info, wdata, extra); - break; - case MP_GET_TXPOWER_INX: - RTW_INFO("mp_get MP_GET_TXPOWER_INX\n"); - status = rtw_mp_txpower_index(dev, info, wrqu, extra); - break; - case MP_GETVER: - RTW_INFO("mp_get MP_GETVER\n"); - status = rtw_mp_getver(dev, info, wdata, extra); - break; - case MP_MON: - RTW_INFO("mp_get MP_MON\n"); - status = rtw_mp_mon(dev, info, wdata, extra); - break; - case EFUSE_BT_MASK: - RTW_INFO("mp_get EFUSE_BT_MASK\n"); - status = rtw_bt_efuse_mask_file(dev, info, wdata, extra); - break; - case EFUSE_MASK: - RTW_INFO("mp_get EFUSE_MASK\n"); - status = rtw_efuse_mask_file(dev, info, wdata, extra); - break; - case EFUSE_FILE: - RTW_INFO("mp_get EFUSE_FILE\n"); - status = rtw_efuse_file_map(dev, info, wdata, extra); - break; - case EFUSE_FILE_STORE: - RTW_INFO("mp_get EFUSE_FILE_STORE\n"); - status = rtw_efuse_file_map_store(dev, info, wdata, extra); - break; - case MP_TX: - RTW_INFO("mp_get MP_TX\n"); - status = rtw_mp_tx(dev, info, wdata, extra); - break; - case MP_RX: - RTW_INFO("mp_get MP_RX\n"); - status = rtw_mp_rx(dev, info, wdata, extra); - break; - case MP_HW_TX_MODE: - RTW_INFO("mp_get MP_HW_TX_MODE\n"); - status = rtw_mp_hwtx(dev, info, wdata, extra); - break; - case MP_GET_TSSIDE: - RTW_INFO("mp_get TSSI_DE\n"); - status = rtw_mp_get_tsside(dev, info, wrqu, extra); - break; -#ifdef CONFIG_RTW_CUSTOMER_STR - case MP_CUSTOMER_STR: - RTW_INFO("customer str\n"); - status = rtw_mp_customer_str(dev, info, wdata, extra); - break; + RTW_INFO("%s %s\n", __func__, extra); +#if 0 + if (!strcmp(extra, "1")) + hal_data->in_cta_test = 1; + else + hal_data->in_cta_test = 0; #endif - case MP_PWRLMT: - RTW_INFO("mp_get MP_SETPWRLMT\n"); - status = rtw_mp_pwrlmt(dev, info, wdata, extra); - break; - case MP_PWRBYRATE: - RTW_INFO("mp_get MP_SETPWRBYRATE\n"); - status = rtw_mp_pwrbyrate(dev, info, wdata, extra); - break; - case BT_EFUSE_FILE: - RTW_INFO("mp_get BT EFUSE_FILE\n"); - status = rtw_bt_efuse_file_map(dev, info, wdata, extra); - break; - case MP_SWRFPath: - RTW_INFO("mp_get MP_SWRFPath\n"); - status = rtw_mp_switch_rf_path(dev, info, wrqu, extra); - break; - case MP_LINK: - RTW_INFO("mp_get MP_LINK\n"); - status = rtw_mp_link(dev, info, wrqu, extra); - break; - case MP_DPK_TRK: - RTW_INFO("mp_get MP_DPK_TRK\n"); - status = rtw_mp_dpk_track(dev, info, wdata, extra); - break; - case MP_DPK: - RTW_INFO("set MP_DPK\n"); - status = rtw_mp_dpk(dev, info, wdata, extra); - break; - default: - status = -EIO; - } - - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); - RTW_INFO("%s mutx done_%d\n", __func__, subcmd); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE); - return status; + return ret; } #endif /*#if defined(CONFIG_MP_INCLUDED)*/ @@ -10295,7 +6392,7 @@ static int rtw_mp_sd_iread(struct net_device *dev u8 width; unsigned long addr; u32 ret = 0; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); if (wrqu->length > 16) { RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length); @@ -10357,7 +6454,7 @@ static int rtw_mp_sd_iwrite(struct net_device *dev char width; unsigned long addr, data; int ret = 0; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); char input[32]; if (wrqu->length > 32) { @@ -10424,17 +6521,17 @@ static int rtw_priv_set(struct net_device *dev, { struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); if (padapter == NULL) return -ENETDOWN; - if (padapter->bup == _FALSE) { - RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__); + if (padapter->netif_up == _FALSE) { + RTW_INFO(" %s fail =>(padapter->netif_up == _FALSE )\n", __FUNCTION__); return -ENETDOWN; } - if (RTW_CANNOT_RUN(padapter)) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { RTW_INFO("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__); return -ENETDOWN; } @@ -10462,13 +6559,6 @@ static int rtw_priv_set(struct net_device *dev, RTW_INFO("set case MP_WOW_SET_PATTERN: %s\n", extra); rtw_wowlan_set_pattern(dev, info, wdata, extra); break; - #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - case MP_WOW_SET_KEEP_ALIVE_PATTERN: - RTW_INFO("set case MP_WOW_SET_KEEP_ALIVE_PATTERN: %s\n", extra); - rtw_wowlan_set_keep_alive_pattern(dev, info, wdata, extra); - break; - #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - #endif #ifdef CONFIG_AP_WOWLAN case MP_AP_WOW_ENABLE: @@ -10481,6 +6571,12 @@ static int rtw_priv_set(struct net_device *dev, RTW_INFO("set case VENDOR_IE_SET\n"); rtw_vendor_ie_set(dev , info , wdata , extra); break; +#endif +#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE) + case PHL_TEST_SET: + RTW_INFO("set case PHL_TEST_SET\n"); + rtw_phl_test_set(dev , info , wdata , extra); + break; #endif default: return -EIO; @@ -10489,27 +6585,25 @@ static int rtw_priv_set(struct net_device *dev, return 0; } - static int rtw_priv_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wdata, char *extra) { struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *p_dm = &pHalData->odmpriv; - struct dm_rf_calibration_struct *p_rf_calibrate_info = &(p_dm->rf_calibrate_info); - struct dm_iqk_info *p_iqk_info = &p_dm->IQK_info; - u32 i = 100; + _adapter *padapter = rtw_netdev_priv(dev); + int status = 0 ; +#ifndef CONFIG_MP_INCLUDED + if (padapter == NULL) + return -ENETDOWN; - if (padapter->bup == _FALSE) { - RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__); + if (padapter->netif_up == _FALSE) { + RTW_INFO(" %s fail =>(padapter->netif_up == _FALSE )\n", __FUNCTION__); return -ENETDOWN; } - if (RTW_CANNOT_RUN(padapter)) { + if (RTW_CANNOT_RUN(adapter_to_dvobj(padapter))) { RTW_INFO("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__); return -ENETDOWN; } @@ -10518,44 +6612,27 @@ static int rtw_priv_get(struct net_device *dev, wrqu->length = 0; return -EIO; } - +#endif if (subcmd < MP_NULL) { #ifdef CONFIG_MP_INCLUDED - while (i > 1) { - if (p_rf_calibrate_info->is_iqk_in_progress) { - rtw_msleep_os(10); - } else { - p_iqk_info->rfk_forbidden = _TRUE; - break; - } - i--; - } - if (subcmd == MP_CHANNEL || subcmd == MP_BANDWIDTH || subcmd == MP_START || subcmd == MP_DPK) - p_iqk_info->rfk_forbidden = _FALSE; - rtw_priv_mp_get(dev, info, wdata, extra); + status = rtw_priv_mp_get(dev, info, wdata, extra); rtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */ - p_iqk_info->rfk_forbidden = _FALSE; #endif + } else { switch (subcmd) { -#if defined(CONFIG_RTL8723B) - case MP_SetBT: - RTW_INFO("set MP_SetBT\n"); - rtw_mp_SetBT(dev, info, wdata, extra); - break; -#endif #ifdef CONFIG_SDIO_INDIRECT_ACCESS case MP_SD_IREAD: - rtw_mp_sd_iread(dev, info, wrqu, extra); + status = rtw_mp_sd_iread(dev, info, wrqu, extra); break; case MP_SD_IWRITE: - rtw_mp_sd_iwrite(dev, info, wrqu, extra); + status = rtw_mp_sd_iwrite(dev, info, wrqu, extra); break; #endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE case VENDOR_IE_GET: RTW_INFO("get case VENDOR_IE_GET\n"); - rtw_vendor_ie_get(dev , info , wdata , extra); + status = rtw_vendor_ie_get(dev , info , wdata , extra); break; #endif default: @@ -10563,7 +6640,7 @@ static int rtw_priv_get(struct net_device *dev, } } - return 0; + return status; } @@ -10778,25 +6855,21 @@ static int rtw_tdls_ch_switch(struct net_device *dev, } else RTW_INFO("TDLS peer not found\n"); - rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + rtw_pm_set_lps(padapter, PM_PS_MODE_ACTIVE); rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); if (take_care_iqk == _TRUE) { -#ifdef CONFIG_TDLS_CH_SW_V2 - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); -#else u8 central_chnl; u8 bw_mode; bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; - central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); + central_chnl = rtw_phl_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0) - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_START); else - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); -#endif + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_PREPARE); } else - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_START); /* issue_tdls_ch_switch_req(padapter, ptdls_sta); */ /* RTW_INFO("issue tdls ch switch req\n"); */ @@ -10840,7 +6913,7 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, if (ptdls_sta == NULL) return ret; - rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->phl_sta->mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | TDLS_CH_SWITCH_ON_STATE | @@ -10854,7 +6927,7 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, _cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer); _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); - rtw_pm_set_lps(padapter, PS_MODE_MAX); + rtw_pm_set_lps(padapter, PM_PS_MODE_MAX); #endif /* CONFIG_TDLS_CH_SW */ #endif /* CONFIG_TDLS */ @@ -10924,16 +6997,16 @@ static int rtw_tdls_ch_offset(struct net_device *dev, extra[wrqu->data.length] = 0x00; switch (rtw_atoi(extra)) { - case SCA: - ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + case IEEE80211_SCA: + ptdlsinfo->chsw_info.ch_offset = CHAN_OFFSET_UPPER; break; - case SCB: - ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + case IEEE80211_SCB: + ptdlsinfo->chsw_info.ch_offset = CHAN_OFFSET_LOWER; break; default: - ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + ptdlsinfo->chsw_info.ch_offset = CHAN_OFFSET_NO_EXT; break; } @@ -10964,7 +7037,7 @@ static int rtw_tdls_pson(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->phl_sta->mac_addr, 1, 3, 500); #endif /* CONFIG_TDLS */ @@ -10991,7 +7064,7 @@ static int rtw_tdls_psoff(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); if (ptdls_sta) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->phl_sta->mac_addr, 0, 3, 500); #endif /* CONFIG_TDLS */ @@ -11307,7 +7380,7 @@ static int rtw_tdls(struct net_device *dev, RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_TDLS) == _FALSE) { RTW_INFO("Discard tdls oper since hal doesn't support tdls\n"); return 0; } @@ -11319,7 +7392,7 @@ static int rtw_tdls(struct net_device *dev, /* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */ - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) { if (_rtw_memcmp(extra, "wfdenable=", 10)) { wrqu->data.length -= 10; rtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]); @@ -11370,7 +7443,7 @@ static int rtw_tdls(struct net_device *dev, } #ifdef CONFIG_WFD - if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) { if (_rtw_memcmp(extra, "setip=", 6)) { wrqu->data.length -= 6; rtw_tdls_setip(dev, info, wrqu, &extra[6]); @@ -11413,94 +7486,12 @@ static int rtw_tdls_get(struct net_device *dev, return ret; } -#ifdef CONFIG_MAC_LOOPBACK_DRIVER - -#if defined(CONFIG_RTL8188E) -#include -extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc); -#define cal_txdesc_chksum(padapter, desc) rtl8188e_cal_txdesc_chksum(desc) -#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI) -extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); -#define fill_default_txdesc rtl8188es_fill_default_txdesc -#endif /* CONFIG_SDIO_HCI */ -#endif /* CONFIG_RTL8188E */ -#if defined(CONFIG_RTL8723B) -extern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc); -#define cal_txdesc_chksum(padapter, desc) rtl8723b_cal_txdesc_chksum(desc) -extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); -#define fill_default_txdesc rtl8723b_fill_default_txdesc -#endif /* CONFIG_RTL8723B */ - -#if defined(CONFIG_RTL8703B) -/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */ -#define cal_txdesc_chksum(padapter, desc) rtl8703b_cal_txdesc_chksum(desc) -/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */ -#define fill_default_txdesc rtl8703b_fill_default_txdesc -#endif /* CONFIG_RTL8703B */ - -#if defined(CONFIG_RTL8723D) -/* extern void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); */ -#define cal_txdesc_chksum(padapter, desc) rtl8723d_cal_txdesc_chksum(desc) -/* extern void rtl8723d_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */ -#define fill_default_txdesc rtl8723d_fill_default_txdesc -#endif /* CONFIG_RTL8723D */ - -#if defined(CONFIG_RTL8710B) -#define cal_txdesc_chksum(padapter, desc) rtl8710b_cal_txdesc_chksum(desc) -#define fill_default_txdesc rtl8710b_fill_default_txdesc -#endif /* CONFIG_RTL8710B */ - -#if defined(CONFIG_RTL8192E) -extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc); -#define cal_txdesc_chksum(padapter, desc) rtl8192e_cal_txdesc_chksum(desc) -#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI) -extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); -#define fill_default_txdesc rtl8192es_fill_default_txdesc -#endif /* CONFIG_SDIO_HCI */ -#endif /* CONFIG_RTL8192E */ - -#if defined(CONFIG_RTL8192F) -/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */ -#define cal_txdesc_chksum(padapter, desc) rtl8192f_cal_txdesc_chksum(desc) -/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */ -#define fill_default_txdesc rtl8192f_fill_default_txdesc -#endif /* CONFIG_RTL8192F */ - -#ifdef CONFIG_RTL8723F -#include <../../hal/rtl8723f/rtl8723f.h> - -#define REG_LOOPBACK_ENABLE 0x0103 -#define LOOKBACK_ENABLE_VALUE 0x0b -#define cal_txdesc_chksum(padapter, desc) rtl8723f_cal_txdesc_chksum(padapter, desc) -#define dump_txdesc_data(padapter, desc) rtl8723f_dbg_dump_tx_desc(padapter, DATA_FRAMETAG, desc); -#define get_rx_desc(rx_desc, rxbuf) rtl8723f_rxdesc2attribute(rx_desc, rxbuf) -#define hal_init rtl8723f_hal_init -#endif /* CONFIG_RTL8723F */ - -void dbg_dump_pkt(char *s, u8 *buf, u8 len) -{ - u8 i, j = 1; - - RTW_INFO("%s size = %u\n", s, len); - - for (i = 0; (i + 4) < len; i += 4) { - if (j % 4 == 1) - RTW_PRINT("idx:%u:", i); - _RTW_PRINT(" 0x%02x 0x%02x 0x%02x 0x%02x", buf[i], buf[i+1], buf[i+2], buf[i+3]); - if ((j++) % 4 == 0) - _RTW_PRINT("\n"); - } - - for (; i < len ; i++) { - _RTW_PRINT(" 0x%02x", buf[i]); - } - _RTW_PRINT("\n ================================\n"); -} - -static s32 initLoopback(PADAPTER padapter) +#if 0 /*#ifdef CONFIG_MAC_LOOPBACK_DRIVER*/ +static s32 initLoopback(_adapter *padapter) { PLOOPBACKDATA ploopback; + if (padapter->ploopback == NULL) { ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA)); if (ploopback == NULL) @@ -11518,10 +7509,11 @@ static s32 initLoopback(PADAPTER padapter) return 0; } -static void freeLoopback(PADAPTER padapter) +static void freeLoopback(_adapter *padapter) { PLOOPBACKDATA ploopback; + ploopback = padapter->ploopback; if (ploopback) { rtw_mfree((u8 *)ploopback, sizeof(LOOPBACKDATA)); @@ -11529,7 +7521,7 @@ static void freeLoopback(PADAPTER padapter) } } -static s32 initpseudoadhoc(PADAPTER padapter) +static s32 initpseudoadhoc(_adapter *padapter) { NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; s32 err; @@ -11546,7 +7538,7 @@ static s32 initpseudoadhoc(PADAPTER padapter) return _SUCCESS; } -static s32 createpseudoadhoc(PADAPTER padapter) +static s32 createpseudoadhoc(_adapter *padapter) { NDIS_802_11_AUTHENTICATION_MODE authmode; struct mlme_priv *pmlmepriv; @@ -11555,7 +7547,7 @@ static s32 createpseudoadhoc(PADAPTER padapter) u8 *pibss; u8 ssid[] = "pseduo_ad-hoc"; s32 err; - _irqL irqL; + pmlmepriv = &padapter->mlmepriv; @@ -11576,11 +7568,11 @@ static s32 createpseudoadhoc(PADAPTER padapter) rtw_update_registrypriv_dev_network(padapter); rtw_generate_random_ibss(pibss); - _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinlock_bh(&pmlmepriv->lock); /*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/ init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_spinunlock_bh(&pmlmepriv->lock); #if 0 err = rtw_create_ibss_cmd(padapter, 0); @@ -11605,20 +7597,16 @@ static s32 createpseudoadhoc(PADAPTER padapter) /* 3 join psudo AdHoc */ pcur_network->join_res = 1; - pcur_network->aid = psta->cmn.aid = 1; + pcur_network->aid = psta->phl_sta->aid = 1; _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network)); - /* set msr to WIFI_FW_ADHOC_STATE */ - padapter->hw_port = HW_PORT0; - Set_MSR(padapter, WIFI_FW_ADHOC_STATE); - } #endif return _SUCCESS; } - -static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) +/*GEORGIA_TODO_FIXIT_MOVE_TO_HAL*/ +static struct xmit_frame *createloopbackpkt(_adapter *padapter, u32 size) { struct xmit_priv *pxmitpriv; struct xmit_frame *pframe; @@ -11628,25 +7616,25 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) u8 *pkt_start, *pkt_end, *ptr; struct rtw_ieee80211_hdr *hdr; s32 bmcast; - _irqL irqL; - + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u16 xmitbuf_sz = GET_HAL_XMITBUF_SZ(dvobj); - if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ) + if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > xmitbuf_sz) return NULL; pxmitpriv = &padapter->xmitpriv; pframe = NULL; /* 2 1. allocate xmit frame */ - pframe = rtw_alloc_xmitframe(pxmitpriv, 0); + pframe = rtw_alloc_xmitframe(pxmitpriv); if (pframe == NULL) return NULL; pframe->padapter = padapter; /* 2 2. allocate xmit buffer */ - _enter_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinlock_bh(&pxmitpriv->lock); pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); - _exit_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinunlock_bh(&pxmitpriv->lock); if (pxmitbuf == NULL) { rtw_free_xmitframe(pxmitpriv, pframe); return NULL; @@ -11688,7 +7676,7 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) else pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - pattrib->mac_id = pattrib->psta->cmn.mac_id; + pattrib->mac_id = pattrib->psta->phl_sta->macid; pattrib->pktlen = size; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -11698,7 +7686,6 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) fill_default_txdesc(pframe, (u8 *)desc); -#if 0 /* Hw set sequence number */ ((PTXDESC)desc)->hwseq_en = 0; /* HWSEQ_EN, 0:disable, 1:enable * ((PTXDESC)desc)->hwseq_sel = 0; */ /* HWSEQ_SEL */ @@ -11723,11 +7710,9 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) desc->txdw13 = cpu_to_le32(desc->txdw13); desc->txdw14 = cpu_to_le32(desc->txdw14); desc->txdw15 = cpu_to_le32(desc->txdw15); -#endif #endif - cal_txdesc_chksum(padapter, (u8*)desc); - /* dump_txdesc_data(padapter, (u8*)desc); */ + cal_txdesc_chksum(desc); /* 2 5. coalesce */ pkt_start = pframe->buf_addr + TXDESC_SIZE; @@ -11745,20 +7730,17 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) get_random_bytes(ptr, pkt_end - ptr); pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) pxmitbuf->ptail += pxmitbuf->len; -#endif - - dbg_dump_pkt("TX packet", pxmitbuf->pbuf, pxmitbuf->len); return pframe; } -static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) +static void freeloopbackpkt(_adapter *padapter, struct xmit_frame *pframe) { struct xmit_priv *pxmitpriv; struct xmit_buf *pxmitbuf; + pxmitpriv = &padapter->xmitpriv; pxmitbuf = pframe->pxmitbuf; @@ -11770,6 +7752,7 @@ static void printdata(u8 *pbuf, u32 len) { u32 i, val; + for (i = 0; (i + 4) <= len; i += 4) { printk("%08X", *(u32 *)(pbuf + i)); if ((i + 4) & 0x1F) @@ -11802,25 +7785,16 @@ static void printdata(u8 *pbuf, u32 len) printk("\n"); } -static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) +static u8 pktcmp(_adapter *padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) { - struct rx_pkt_attrib rx_desc; -#if 0 struct recv_stat *prxstat; struct recv_stat report; PRXREPORT prxreport; -#endif + u32 drvinfosize; u32 rxpktsize; - u8 drvinfosize; - u8 shiftsize; + u8 fcssize; u8 ret = _FALSE; - u8 skip_len = 4; /* Don't compare the frame control and duration field */ - get_rx_desc(&rx_desc, rxbuf); - rxpktsize = rx_desc.pkt_len; - drvinfosize = rx_desc.drvinfo_sz; - shiftsize = rx_desc.shift_sz; -#if 0 prxstat = (struct recv_stat *)rxbuf; report.rxdw0 = le32_to_cpu(prxstat->rxdw0); report.rxdw1 = le32_to_cpu(prxstat->rxdw1); @@ -11832,19 +7806,20 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) prxreport = (PRXREPORT)&report; drvinfosize = prxreport->drvinfosize << 3; rxpktsize = prxreport->pktlen; -#endif if (rtw_hal_rcr_check(padapter, RCR_APPFCS)) - rxpktsize -= IEEE80211_FCS_LEN; + fcssize = IEEE80211_FCS_LEN; + else + fcssize = 0; - if ((txsz - TXDESC_SIZE) != rxpktsize) { + if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) { RTW_INFO("%s: ERROR! size not match tx/rx=%d/%d !\n", - __func__, txsz - TXDESC_SIZE, rxpktsize); + __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize); ret = _FALSE; } else { - ret = _rtw_memcmp(txbuf + TXDESC_SIZE + skip_len, \ - rxbuf + RXDESC_SIZE + skip_len + drvinfosize, \ - txsz - TXDESC_SIZE - skip_len); + ret = _rtw_memcmp(txbuf + TXDESC_SIZE, \ + rxbuf + RXDESC_SIZE + drvinfosize, \ + txsz - TXDESC_SIZE); if (ret == _FALSE) RTW_INFO("%s: ERROR! pkt content mismatch!\n", __func__); } @@ -11852,17 +7827,23 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) if (ret == _FALSE) { RTW_INFO("\n%s: TX PKT total=%d, desc=%d, content=%d\n", __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE); - dbg_dump_pkt("TX DESC", txbuf, TXDESC_SIZE); - dbg_dump_pkt("TX content", txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE); + RTW_INFO("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE); + printdata(txbuf, TXDESC_SIZE); + RTW_INFO("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE); + printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE); RTW_INFO("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n", __func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize); if (rxpktsize != 0) { - dbg_dump_pkt("RX DESC", rxbuf, RXDESC_SIZE); - dbg_dump_pkt("RX drvinfo", rxbuf + RXDESC_SIZE, drvinfosize); - dbg_dump_pkt("RX packet content", rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize); + RTW_INFO("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE); + printdata(rxbuf, RXDESC_SIZE); + RTW_INFO("%s: RX drvinfo size=%d\n", __func__, drvinfosize); + printdata(rxbuf + RXDESC_SIZE, drvinfosize); + RTW_INFO("%s: RX content size=%d\n", __func__, rxpktsize); + printdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize); } else { RTW_INFO("%s: RX data size=%d\n", __func__, rxsz); + printdata(rxbuf, rxsz); } } @@ -11871,15 +7852,17 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) thread_return lbk_thread(thread_context context) { +#if 0 s32 err; - PADAPTER padapter; + _adapter *padapter; PLOOPBACKDATA ploopback; struct xmit_frame *pxmitframe; u32 cnt, ok, fail, headerlen; u32 pktsize; u32 ff_hwaddr; - padapter = (PADAPTER)context; + + padapter = (_adapter *)context; ploopback = padapter->ploopback; if (ploopback == NULL) return -1; @@ -11887,8 +7870,7 @@ thread_return lbk_thread(thread_context context) ok = 0; fail = 0; - thread_enter("RTW_LBK_THREAD"); - /* daemonize("%s", "RTW_LBK_THREAD"); */ + daemonize("%s", "RTW_LBK_THREAD"); allow_signal(SIGTERM); do { @@ -11909,13 +7891,10 @@ thread_return lbk_thread(thread_context context) ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); cnt++; RTW_INFO("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize); -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) pxmitframe->pxmitbuf->pdata = ploopback->txbuf; -#endif rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf); /* wait for rx pkt */ - RTW_INFO("%s: wait for rx packet\n", __func__); _rtw_down_sema(&ploopback->sema); err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize); @@ -11950,15 +7929,17 @@ thread_return lbk_thread(thread_context context) ploopback->bstop = _TRUE; thread_exit(NULL); +#endif return 0; } -static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) +static void loopbackTest(_adapter *padapter, u32 cnt, u32 size, u8 *pmsg) { PLOOPBACKDATA ploopback; u32 len; s32 err; + ploopback = padapter->ploopback; if (ploopback) { @@ -11973,7 +7954,6 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) break; rtw_msleep_os(1); } while (1); - RTW_INFO("Free loopback, end the test.\n"); _rtw_memcpy(pmsg, ploopback->msg, len + 1); freeLoopback(padapter); @@ -11981,10 +7961,8 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) } /* disable dynamic algorithm */ -#ifndef CONFIG_NO_PHYDM rtw_phydm_ability_backup(padapter); rtw_phydm_func_disable_all(padapter); -#endif /* create pseudo ad-hoc connection */ err = initpseudoadhoc(padapter); @@ -12010,10 +7988,9 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) ploopback->bstop = _FALSE; ploopback->cnt = cnt; ploopback->size = size; - ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD"); - if (IS_ERR(ploopback->lbkthread)) { + ploopback->lbkthread = rtw_thread_start(lbk_thread, padapter, "RTW_LBK_THREAD"); + if (ploopback->lbkthread == NULL)) { freeLoopback(padapter); - ploopback->lbkthread = NULL; sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt); return; } @@ -12031,7 +8008,7 @@ static int rtw_test( u8 *pbuf, *pch; char *ptmp; u8 *delim = ","; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); RTW_INFO("+%s\n", __func__); @@ -12061,20 +8038,8 @@ static int rtw_test( return -EFAULT; } -#ifdef CONFIG_MAC_LOOPBACK_DRIVER - if (strcmp(pch, "init") == 0) { - u8 status; - - rtw_clr_drv_stopped(padapter); /* should clear drv_stopped, otherwise driver can't trx */ - - status = hal_init(padapter); - RTW_INFO("HAL_INIT %s\n", status ? "SUCCESS" : "FAIL"); - - rtw_write8(padapter, REG_LOOPBACK_ENABLE, LOOKBACK_ENABLE_VALUE); - RTW_INFO("Write 0x%03x to 0x%02x, enable loopback\n", - REG_LOOPBACK_ENABLE, LOOKBACK_ENABLE_VALUE); - - } else if (strcmp(pch, "loopback") == 0) { +#if 0 /*#ifdef CONFIG_MAC_LOOPBACK_DRIVER*/ + if (strcmp(pch, "loopback") == 0) { s32 cnt = 0; u32 size = 64; @@ -12105,26 +8070,6 @@ static int rtw_test( } #endif - -#ifdef CONFIG_BT_COEXIST - if (strcmp(pch, "bton") == 0) { - rtw_btcoex_SetManualControl(padapter, _FALSE); - goto free_buf; - } else if (strcmp(pch, "btoff") == 0) { - rtw_btcoex_SetManualControl(padapter, _TRUE); - goto free_buf; - } else if (strcmp(pch, "coex_auto") == 0) { - rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_AUTO); - goto free_buf; - } else if (strcmp(pch, "coex_force_freerun") == 0) { - rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_FORCE_FREERUN); - goto free_buf; - } else if (strcmp(pch, "coex_force_tdma") == 0) { - rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_FORCE_TDMA); - goto free_buf; - } -#endif - if (strcmp(pch, "h2c") == 0) { u8 param[8]; u8 count = 0; @@ -12162,18 +8107,12 @@ static int rtw_test( goto free_buf; } - if (strcmp(pch, "dump_mac_reg") == 0) { - mac_reg_dump(RTW_DBGDUMP, padapter); - goto free_buf; - } - free_buf: rtw_mfree(pbuf, len); return 0; } static iw_handler rtw_handlers[] = { -#ifdef CONFIG_IOCTL_WEXT NULL, /* SIOCSIWCOMMIT */ rtw_wx_get_name, /* SIOCGIWNAME */ dummy, /* SIOCSIWNWID */ @@ -12230,7 +8169,6 @@ static iw_handler rtw_handlers[] = { NULL, /* SIOCGIWENCODEEXT */ rtw_wx_set_pmkid, /* SIOCSIWPMKSA */ NULL, /*---hole---*/ -#endif }; @@ -12334,13 +8272,7 @@ static const struct iw_priv_args rtw_private_args[] = { #else {SIOCIWFIRSTPRIV + 0x17, IW_PRIV_TYPE_CHAR | 1024 , 0 , "NULL"}, #endif - -#ifdef CONFIG_PLATFORM_CMAP_INTFS - {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | 1024 , 0 , "cmap_intfs"}, -#else - {SIOCIWFIRSTPRIV + 0x18, 0, 0, "NULL"}, -#endif - + {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, #ifdef CONFIG_MP_INCLUDED {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"}, @@ -12354,25 +8286,21 @@ static const struct iw_priv_args rtw_private_args[] = { }, { SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, /* set */ - { SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get + { SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get * --- sub-ioctls definitions --- */ #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE { VENDOR_IE_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , "vendor_ie_set" }, { VENDOR_IE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "vendor_ie_get" }, #endif -#if defined(CONFIG_RTL8723B) - { MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" }, - { MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"}, +#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE) + { PHL_TEST_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , "phl_test" }, + { PHL_TEST_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "" }, #endif #ifdef CONFIG_WOWLAN { MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_mode" }, { MP_WOW_SET_PATTERN , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_set_pattern" }, -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - { MP_WOW_SET_KEEP_ALIVE_PATTERN ,IW_PRIV_TYPE_CHAR | 1024 , 0 , "wow_keep_alive"}, -#endif /* defined (CONFIG_KEEP_ALIVE_PATTERN)*/ #endif - #ifdef CONFIG_AP_WOWLAN { MP_AP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "ap_wow_mode" }, /* set */ #endif @@ -12380,65 +8308,135 @@ static const struct iw_priv_args rtw_private_args[] = { { MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iread" }, { MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iwrite" }, #endif +#ifdef CONFIG_MP_INCLUDED + { MP_GET_PHL_TEST, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "phl_get_io" }, + { MP_SET_PHL_TEST, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "phl_set_io" }, +#endif }; - +/* --- sub-ioctls definitions --- */ static const struct iw_priv_args rtw_mp_private_args[] = { - /* --- sub-ioctls definitions --- */ #ifdef CONFIG_MP_INCLUDED - { MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" }, - { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, - { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, - { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, - { MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" }, - { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, - { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, - { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, - { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, - { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, - { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, - { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, - { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, - { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, - { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, - { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, - { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, - { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, - { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, - { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, - { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, - { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, - { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, - { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, - { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"}, - { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, - { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, - { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" }, - { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, - { MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" }, - { MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" }, - { MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" }, - { EFUSE_BT_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_bt_mask" }, - { EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" }, - { EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" }, - { EFUSE_FILE_STORE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_store" }, - { MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, - { MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, - { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, - { MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" }, - { MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" }, + { MP_START , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" }, + { MP_PHYPARA, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, + { MP_STOP , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, + { MP_CHANNEL , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, + { MP_TRXSC_OFFSET , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_trxsc" }, + { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, + { MP_RATE , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, + { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, + { MP_QUERY , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, + { READ_REG , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, + { MP_RATE , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, + { READ_RF , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, + { MP_PSD , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, + { MP_DUMP, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, + { MP_TXPOWER , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, + { MP_ANT_TX , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, + { MP_ANT_RX , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, + { WRITE_REG , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, + { WRITE_RF , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, + { MP_CTX , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, + { MP_ARX , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, + { MP_THER , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, + { EFUSE_SET, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, + { EFUSE_GET, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, + { MP_PWRTRK , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"}, + { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, + { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" }, + { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, + { MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" }, + { MP_GETVER, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" }, + { MP_MON, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" }, + { EFUSE_BT_MASK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_bt_mask" }, + { EFUSE_MASK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" }, + { EFUSE_FILE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" }, + { EFUSE_FILE_STORE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_store" }, + { MP_TX, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, + { MP_RX, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, + { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, + { MP_PWRLMT, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" }, + { MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" }, { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, { MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"}, { MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"}, - { BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" }, - { MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" }, - { MP_LINK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_link" }, - { MP_DPK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk"}, - { MP_DPK_TRK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk_trk" }, - { MP_GET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_tsside" }, - { MP_SET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_set_tsside" }, + { BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" }, + { MP_SWRFPath, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" }, + { MP_LINK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_link" }, + { MP_DPK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk"}, + { MP_DPK_TRK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk_trk" }, + { MP_GET_TSSIDE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_tsside" }, + { MP_SET_TSSIDE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_set_tsside" }, + { MP_GET_PHL_TEST, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "phl_get_io" }, + { MP_SET_PHL_TEST, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "phl_set_io" }, + { MP_SET_PHL_TX_PATTERN, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx_patt" }, + { MP_SET_PHL_TX_METHOD, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "tx_method" }, + { MP_SET_PHL_CONIFG_PHY_NUM, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phy" }, + { MP_SET_PHL_PLCP_TX_DATA, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_plcp_data" }, + { MP_SET_PHL_PLCP_TX_USER, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_plcp_user" }, + { MP_PHL_RFK, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rfk" }, + { MP_PHL_BTC_PATH, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_btc_path" }, + { MP_GET_HE, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_he" }, #ifdef CONFIG_RTW_CUSTOMER_STR - { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, + { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, #endif #endif /* CONFIG_MP_INCLUDED */ @@ -12475,10 +8473,10 @@ static iw_handler rtw_private_handler[] = { rtw_priv_set, /*0x0E*/ rtw_priv_get, /*0x0F*/ - rtw_p2p_set, /* 0x10 */ - rtw_p2p_get, /* 0x11 */ - NULL, /* 0x12 */ - rtw_p2p_get2, /* 0x13 */ + NULL, /* 0x10 */ + NULL, /* 0x11 */ + NULL, /* 0x12 */ + NULL, /* 0x13 */ rtw_tdls, /* 0x14 */ rtw_tdls_get, /* 0x15 */ @@ -12489,24 +8487,19 @@ static iw_handler rtw_private_handler[] = { #else rtw_wx_priv_null, /* 0x17 */ #endif -#ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_ioctl, /* 0x18 */ -#else - NULL, /* 0x18 */ -#endif + rtw_rereg_nd_name, /* 0x18 */ rtw_wx_priv_null, /* 0x19 */ #ifdef CONFIG_MP_INCLUDED rtw_wx_priv_null, /* 0x1A */ rtw_wx_priv_null, /* 0x1B */ #else rtw_wx_priv_null, /* 0x1A */ - rtw_mp_efuse_get, /* 0x1B */ + /*rtw_mp_efuse_get,*/ /* 0x1B */ #endif NULL, /* 0x1C is reserved for hostapd */ rtw_test, /* 0x1D */ }; -#ifdef CONFIG_WIRELESS_EXT #if WIRELESS_EXT >= 17 static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) { @@ -12523,21 +8516,13 @@ static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) /* RTW_INFO("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); */ } else { #ifdef CONFIG_SIGNAL_DISPLAY_DBM - tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); + tmp_level = rtw_phl_rssi_to_dbm(padapter->recvinfo.signal_strength); #else - tmp_level = padapter->recvpriv.signal_strength; + tmp_level = padapter->recvinfo.signal_strength; #endif - tmp_qual = padapter->recvpriv.signal_qual; - #ifdef CONFIG_BACKGROUND_NOISE_MONITOR - if (IS_NM_ENABLE(padapter)) { - tmp_noise = rtw_noise_measure_curchan(padapter); - #ifndef CONFIG_SIGNAL_DISPLAY_DBM - tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/ - #endif - } - #endif - /* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */ + tmp_qual = padapter->recvinfo.signal_qual; + /* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvinfo.rssi); */ piwstats->qual.level = tmp_level; piwstats->qual.qual = tmp_qual; @@ -12563,6 +8548,7 @@ static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) } #endif +#ifdef CONFIG_WIRELESS_EXT struct iw_handler_def rtw_handlers_def = { .standard = rtw_handlers, .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler), @@ -12925,6 +8911,7 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq case IW_PRIV_TYPE_CHAR: /* Display args */ _rtw_memcpy(output, extra, n); + output_len = n; break; default: @@ -12933,7 +8920,7 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq goto exit; } - output_len = strlen(output) + 1; + output_len ++; wrq_data->data.length = output_len; if (copy_to_user(wrq_data->data.pointer, output, output_len)) { err = -EFAULT; @@ -13018,7 +9005,6 @@ int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) int ret = 0; switch (cmd) { -#ifdef CONFIG_IOCTL_WEXT case RTL_IOCTL_WPA_SUPPLICANT: ret = wpa_supplicant_ioctl(dev, &wrq->u.data); break; @@ -13032,7 +9018,6 @@ int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) break; #endif #endif /* CONFIG_AP_MODE */ -#endif /* CONFIG_IOCTL_WEXT */ case SIOCDEVPRIVATE: ret = rtw_ioctl_wext_private(dev, rq); break; diff --git a/os_dep/linux/ioctl_mp.c b/os_dep/linux/ioctl_mp.c index 17cca9c..f69c3b5 100644 --- a/os_dep/linux/ioctl_mp.c +++ b/os_dep/linux/ioctl_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,25 +16,8 @@ #include #include -#include "../../hal/phydm/phydm_precomp.h" -#include - - -#if defined(CONFIG_RTL8723B) - #include -#endif #define RTW_IWD_MAX_LEN 128 -inline u8 rtw_do_mp_iwdata_len_chk(const char *caller, u32 len) -{ - u8 is_illegal = _FALSE; - if (len >= RTW_IWD_MAX_LEN) { - RTW_ERR("%s : iw data len(%u) > RTW_IWD_MAX_LEN(%u)", - caller, len, RTW_IWD_MAX_LEN); - is_illegal = _TRUE; - } - return is_illegal; -} /* * Input Format: %s,%d,%d @@ -45,6 +28,7 @@ inline u8 rtw_do_mp_iwdata_len_chk(const char *caller, u32 len) * 1st %d is address(offset) * 2st %d is data to write */ + int rtw_mp_write_reg(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) @@ -54,12 +38,10 @@ int rtw_mp_write_reg(struct net_device *dev, char width; u32 addr, data; int ret; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); char input[RTW_IWD_MAX_LEN]; - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; - _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -82,17 +64,14 @@ int rtw_mp_write_reg(struct net_device *dev, if (pnext == NULL) return -EINVAL; *pnext = 0; - /*addr = simple_strtoul(pch, &ptmp, 16); - _rtw_memset(buf, '\0', sizeof(buf)); - _rtw_memcpy(buf, pch, pnext-pch); - ret = kstrtoul(buf, 16, &addr);*/ + ret = sscanf(pch, "%x", &addr); pch = pnext + 1; pnext = strpbrk(pch, " ,.-"); if ((pch - input) >= wrqu->length) return -EINVAL; - /*data = simple_strtoul(pch, &ptmp, 16);*/ + ret = sscanf(pch, "%x", &data); RTW_INFO("data=%x,addr=%x\n", (u32)data, (u32)addr); ret = 0; @@ -104,7 +83,7 @@ int rtw_mp_write_reg(struct net_device *dev, ret = -EINVAL; break; } - rtw_write8(padapter, addr, data); + rtw_phl_write8(dvobj->phl, addr, (u8)data); break; case 'w': /* 2 bytes*/ @@ -112,11 +91,11 @@ int rtw_mp_write_reg(struct net_device *dev, ret = -EINVAL; break; } - rtw_write16(padapter, addr, data); + rtw_phl_write16(dvobj->phl, addr, (u16)data); break; case 'd': /* 4 bytes*/ - rtw_write32(padapter, addr, data); + rtw_phl_write32(dvobj->phl, addr, (u32)data); break; default: ret = -EINVAL; @@ -149,11 +128,10 @@ int rtw_mp_read_reg(struct net_device *dev, char data[20], tmp[20]; u32 addr = 0, strtout = 0; u32 i = 0, j = 0, ret = 0, data32 = 0; - PADAPTER padapter = rtw_netdev_priv(dev); - char *pextra = extra; + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + char *pextra = extra; if (wrqu->length > 128) return -EFAULT; @@ -176,22 +154,20 @@ int rtw_mp_read_reg(struct net_device *dev, pch = pnext + 1; ret = sscanf(pch, "%x", &addr); - if (addr > MP_READ_REG_MAX_OFFSET) - return -EINVAL; ret = 0; width = width_str[0]; switch (width) { case 'b': - data32 = rtw_read8(padapter, addr); + data32 = rtw_phl_read8(dvobj->phl, addr); RTW_INFO("%x\n", data32); sprintf(extra, "%d", data32); wrqu->length = strlen(extra); break; case 'w': /* 2 bytes*/ - sprintf(data, "%04x\n", rtw_read16(padapter, addr)); + sprintf(data, "%04x\n", rtw_phl_read16(dvobj->phl, addr)); for (i = 0 ; i <= strlen(data) ; i++) { if (i % 2 == 0) { @@ -224,7 +200,7 @@ int rtw_mp_read_reg(struct net_device *dev, break; case 'd': /* 4 bytes */ - sprintf(data, "%08x", rtw_read32(padapter, addr)); + sprintf(data, "%08x", rtw_phl_read32(dvobj->phl, addr)); /*add read data format blank*/ for (i = 0 ; i <= strlen(data) ; i++) { if (i % 2 == 0) { @@ -275,14 +251,13 @@ int rtw_mp_write_rf(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { + u32 path, addr, data; int ret; - PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); char input[RTW_IWD_MAX_LEN]; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; _rtw_memset(input, 0, wrqu->length); if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -293,7 +268,7 @@ int rtw_mp_write_rf(struct net_device *dev, if (ret < 3) return -EINVAL; - if (path >= hal_spec->rf_reg_path_num) + if (path >= GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter))) return -EINVAL; if (addr > 0xFF) return -EINVAL; @@ -302,7 +277,7 @@ int rtw_mp_write_rf(struct net_device *dev, _rtw_memset(extra, 0, wrqu->length); - write_rfreg(padapter, path, addr, data); + rtw_phl_write_rfreg(GET_PHL_INFO(dvobj), path, addr, 0xFFFFF, data); sprintf(extra, "write_rf completed\n"); wrqu->length = strlen(extra); @@ -328,13 +303,10 @@ int rtw_mp_read_rf(struct net_device *dev, char data[20], tmp[20]; u32 path, addr, strtou; u32 ret, i = 0 , j = 0; - PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); char *pextra = extra; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; - if (wrqu->length > 128) return -EFAULT; _rtw_memset(input, 0, wrqu->length); @@ -345,15 +317,12 @@ int rtw_mp_read_rf(struct net_device *dev, if (ret < 2) return -EINVAL; - if (path >= hal_spec->rf_reg_path_num) - return -EINVAL; - - if (addr > MP_READ_REG_MAX_OFFSET) + if (path >= GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter))) return -EINVAL; _rtw_memset(extra, 0, wrqu->length); - sprintf(data, "%08x", read_rfreg(padapter, path, addr)); + sprintf(data, "%08x", rtw_phl_read_rfreg(GET_PHL_INFO(dvobj), path, addr , 0xFFFFF)); /*add read data format blank*/ for (i = 0 ; i <= strlen(data) ; i++) { if (i % 2 == 0) { @@ -390,52 +359,56 @@ int rtw_mp_start(struct net_device *dev, struct iw_point *wrqu, char *extra) { int ret = 0; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmppriv = &padapter->mppriv; - - rtw_pm_set_ips(padapter, IPS_NONE); - LeaveAllPowerSaveMode(padapter); + char *pextra = NULL; pmppriv->bprocess_mp_mode = _TRUE; - if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) { - rtw_mi_buddy_set_scan_deny(padapter, 5000); - rtw_mi_scan_abort(padapter, _TRUE); + if (pmppriv->mode == MP_ON) { + sprintf(extra, "Already mp_start\n"); + wrqu->length = strlen(extra); + return ret; } - rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + rtw_set_scan_deny(padapter, 5000); + rtw_mi_scan_abort(padapter, _TRUE); if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS) ret = -EPERM; _rtw_memset(extra, 0, wrqu->length); - sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail"); + pextra = extra; + pextra += sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail"); + pextra += sprintf(pextra, "EFUSE:%s\n", + RTW_EFUSE_FROM2STR(rtw_efuse_get_map_from(padapter))); wrqu->length = strlen(extra); return ret; } - - int rtw_mp_stop(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { int ret = 0; - PADAPTER padapter = rtw_netdev_priv(dev); + u8 status = 0; + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmppriv = &padapter->mppriv; - if (pmppriv->mode != MP_ON) - return -EPERM; if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS) ret = -EPERM; - pmppriv->bprocess_mp_mode = _FALSE; + if (pmppriv->mode != MP_OFF) + return -EPERM; + _rtw_memset(extra, 0, wrqu->length); - sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail"); + sprintf(extra, "mp_stop ok\n"); wrqu->length = strlen(extra); + pmppriv->bprocess_mp_mode = _FALSE; + return ret; } @@ -444,29 +417,29 @@ int rtw_mp_rate(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - u32 rate = MPT_RATE_1M; - u8 err = 0; - u8 input[RTW_IWD_MAX_LEN]; - PADAPTER padapter = rtw_netdev_priv(dev); + u16 rate = MPT_RATE_1M; + u8 input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); - struct mp_priv *pmppriv = &padapter->mppriv; - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + char *pextra = extra; + u8 path_i = 0, i = 0; + u16 pwr_dbm = 0; _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; input[wrqu->length] = '\0'; - rate = rtw_mpRateParseFunc(padapter, input); - pmppriv->rateidx = rate; + rate = rtw_mp_rate_parse(padapter, input); + padapter->mppriv.rateidx = rate; if (rate == 0 && strcmp(input, "1M") != 0) { rate = rtw_atoi(input); - if (rate <= MGN_VHT4SS_MCS9) - pmppriv->rateidx = MRateToHwRate(rate); +#ifndef CONFIG_80211AX_HE + padapter->mppriv.rateidx = mrate_to_hwrate(rate); +#endif /*if (rate <= 0x7f) rate = wifirate2_ratetbl_inx((u8)rate); else if (rate < 0xC8) @@ -479,51 +452,36 @@ int rtw_mp_rate(struct net_device *dev, rate =(rate - MPT_RATE_VHT1SS_MCS0); */ } - _rtw_memset(extra, 0, wrqu->length); - if (pmppriv->rateidx > DESC_RATEVHTSS4MCS9) { - sprintf(extra, "Set %s Error" , input); - return -EINVAL; - } + pextra += sprintf(pextra, "Set data rate to %s index %d\n" , input, padapter->mppriv.rateidx); + RTW_INFO("%s: %s rate index=%d\n", __func__, input, padapter->mppriv.rateidx); + pextra += sprintf(pextra, "PPDU Type %s\n", + PPDU_TYPE_STR(pmp_priv->rtw_mp_pmact_ppdu_type)); + pextra += sprintf(pextra, "CMD: [mp_plcp_datappdu=%%d]\nPLCP (PPDU Type):\n"); + for (i = pmp_priv->rtw_mp_pmact_ppdu_type; i <= RTW_MP_TYPE_HE_TB; i++) + pextra += sprintf(pextra, "%d:%s\n", i,PPDU_TYPE_STR(i)); - if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(HwRateToMPTRate(pmppriv->rateidx))) - err = 1; - if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(HwRateToMPTRate(pmppriv->rateidx))) - err = 1; - if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(HwRateToMPTRate(pmppriv->rateidx))) - err = 1; - if (!is_supported_vht(padapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(HwRateToMPTRate(pmppriv->rateidx))) - err = 1; - if (!is_supported_ht(padapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(HwRateToMPTRate(pmppriv->rateidx))) - err = 1; - - if (err == 1) { - sprintf(extra, "Set data rate to %s Error" , input); - pmppriv->rateidx = 0; - } else { - sprintf(extra, "Set data rate to %s index %d" , input, pmppriv->rateidx); - RTW_INFO("%s: %s rate index=%d\n", __func__, input, pmppriv->rateidx); - pMptCtx->mpt_rate_index = HwRateToMPTRate(pmppriv->rateidx); - SetDataRate(padapter); + SetDataRate(padapter); +#if 0 + for (path_i = 0 ; path_i < tx_nss; path_i++) { + pwr_dbm = rtw_mp_get_pwrtab_dbm(padapter, path_i); + pextra += sprintf(pextra, "Path%d Pwrdbm:%d" , path_i, pwr_dbm); } +#endif wrqu->length = strlen(extra); - return err; + return 0; } + int rtw_mp_channel(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 input[RTW_IWD_MAX_LEN]; - u8 channel = 1; - struct mp_priv *pmppriv = &padapter->mppriv; - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 input[RTW_IWD_MAX_LEN]; + u32 channel = 1; _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -531,45 +489,71 @@ int rtw_mp_channel(struct net_device *dev, input[wrqu->length] = '\0'; channel = rtw_atoi(input); - /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ + _rtw_memset(extra, 0, wrqu->length); - sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel); - padapter->mppriv.channel = channel; - rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); - rtw_adjust_chbw(padapter, channel, &pmppriv->bandwidth, &pmppriv->prime_channel_offset); + sprintf(extra, "Change channel %d to channel %d", pmp_priv->channel, channel); + pmp_priv->channel = channel; + //pHalData->current_channel = channel; //aka struct rtw_phl_com_t SetChannel(padapter); - pHalData->current_channel = channel; wrqu->length = strlen(extra); return 0; } +static void rtw_mp_update_trxsc(_adapter *padapter) { + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 trxsc_offset = pmp_priv->rtw_mp_trxsc; + + switch (trxsc_offset) { + case 0: + pmp_priv->rtw_mp_data_bandwidth = pmp_priv->bandwidth; + RTW_INFO("%s:TRXSC %d, MP bandwidth = %d\n", __func__, trxsc_offset, pmp_priv->bandwidth); + break; + case 1: + case 2: + case 3: + case 4: + pmp_priv->rtw_mp_data_bandwidth = CHANNEL_WIDTH_20; + RTW_INFO("%s:TRXSC %d, MP bandwidth = %d\n", __func__, trxsc_offset, pmp_priv->bandwidth); + break; + case 9: + case 10: + case 11: + case 12: + pmp_priv->rtw_mp_data_bandwidth = CHANNEL_WIDTH_40; + RTW_INFO("%s:TRXSC %d, MP bandwidth = %d\n", __func__, trxsc_offset, pmp_priv->bandwidth); + break; + case 13: + case 14: + pmp_priv->rtw_mp_data_bandwidth = CHANNEL_WIDTH_40; + RTW_INFO("%s:TRXSC %d, MP bandwidth = %d\n", __func__, trxsc_offset, pmp_priv->bandwidth); + break; + } +} -int rtw_mp_ch_offset(struct net_device *dev, +int rtw_mp_trxsc_offset(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - u8 input[RTW_IWD_MAX_LEN]; - u32 ch_offset = 0; - char *pch; - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 input[RTW_IWD_MAX_LEN]; + u32 trxsc_offset = 0; _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; input[wrqu->length] = '\0'; - ch_offset = rtw_atoi(input); - /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ + trxsc_offset = rtw_atoi(input); + RTW_INFO("%s: ch offset = %d\n", __func__, trxsc_offset); + + pmp_priv->rtw_mp_trxsc = trxsc_offset; + rtw_mp_update_trxsc(padapter); _rtw_memset(extra, 0, wrqu->length); - pch = extra; - pch += sprintf(pch, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset); - padapter->mppriv.prime_channel_offset = ch_offset; - SetChannel(padapter); + sprintf(extra, "change TRXSC to %d, current Bandwidth=%d\n", + pmp_priv->rtw_mp_trxsc, pmp_priv->bandwidth); wrqu->length = strlen(extra); return 0; @@ -581,30 +565,33 @@ int rtw_mp_bandwidth(struct net_device *dev, struct iw_point *wrqu, char *extra) { u8 bandwidth = 0, sg = 0; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mp_priv *pmppriv = &padapter->mppriv; - u8 input[RTW_IWD_MAX_LEN]; - - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 input[RTW_IWD_MAX_LEN]; if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; if (sscanf(input, "40M=%hhd,shortGI=%hhd", &bandwidth, &sg) > 0) - RTW_INFO("%s: bw=%hhd sg=%hhd\n", __func__, bandwidth , sg); - - rtw_adjust_chbw(padapter, pmppriv->channel, &bandwidth, &pmppriv->prime_channel_offset); + RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth , sg); +#if 0 + if (bandwidth == 1 && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_40M)) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2 && rtw_hw_chk_bw_cap(adapter_to_dvobj(padapter), BW_CAP_80M)) + bandwidth = CHANNEL_WIDTH_80; + else + bandwidth = CHANNEL_WIDTH_20; +#else + rtw_adjust_chbw(padapter, pmp_priv->channel, &bandwidth, &pmp_priv->prime_channel_offset); - padapter->mppriv.bandwidth = (u8)bandwidth; - padapter->mppriv.preamble = sg; + pmp_priv->bandwidth = (u8)bandwidth; + pmp_priv->preamble = sg; _rtw_memset(extra, 0, wrqu->length); - sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth); - rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); - SetBandwidth(padapter); - pHalData->current_channel_bw = bandwidth; + sprintf(extra, "Change BW %d to BW %d\n", pmp_priv->bandwidth , bandwidth); + SetBandwidth(padapter); + rtw_mp_update_trxsc(padapter); +#endif wrqu->length = strlen(extra); return 0; @@ -615,15 +602,12 @@ int rtw_mp_txpower_index(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); + _adapter *padapter = rtw_netdev_priv(dev); char input[RTW_IWD_MAX_LEN]; u32 rfpath = 0 ; u32 txpower_inx = 0, tarpowerdbm = 0; char *pextra = extra; - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + u8 rf_type = GET_HAL_RFPATH(adapter_to_dvobj(padapter)); if (wrqu->length > 128) return -EFAULT; @@ -637,50 +621,49 @@ int rtw_mp_txpower_index(struct net_device *dev, _rtw_memset(extra, 0, strlen(extra)); if (wrqu->length == 2) { +#ifndef CONFIG_80211AX_HE if (input[0] != '\0' ) { rfpath = rtw_atoi(input); txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); } +#endif pextra += sprintf(pextra, " %d\n", txpower_inx); tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath); if (tarpowerdbm > 0) pextra += sprintf(pextra, "\t\t dBm:%d", tarpowerdbm); } else { - if (phal_data->ant_path == 1) - rfpath = 1; - else - rfpath = 0; - - txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); +#ifndef CONFIG_80211AX_HE + txpower_inx = mpt_ProQueryCalTxPower(padapter, 0); pextra += sprintf(pextra, "patha=%d", txpower_inx); - if (phal_data->rf_type > RF_1T2R) { + if (rf_type > RF_1T2R) { txpower_inx = mpt_ProQueryCalTxPower(padapter, 1); pextra += sprintf(pextra, ",pathb=%d", txpower_inx); } - if (phal_data->rf_type > RF_2T4R) { + if (rf_type > RF_2T4R) { txpower_inx = mpt_ProQueryCalTxPower(padapter, 2); pextra += sprintf(pextra, ",pathc=%d", txpower_inx); } - if (phal_data->rf_type > RF_3T4R) { + if (rf_type > RF_3T4R) { txpower_inx = mpt_ProQueryCalTxPower(padapter, 3); pextra += sprintf(pextra, ",pathd=%d", txpower_inx); } - - tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath); +#endif + tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 0); pextra += sprintf(pextra, "\n\t\t\tpatha dBm=%d", tarpowerdbm); - if (phal_data->rf_type > RF_1T2R) { + if (rf_type > RF_1T2R) { tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 1); pextra += sprintf(pextra, ",pathb dBm=%d", tarpowerdbm); } - if (phal_data->rf_type > RF_2T4R) { + if (rf_type > RF_2T4R) { tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 2); pextra += sprintf(pextra, ",pathc dBm=%d", tarpowerdbm); } - if (phal_data->rf_type > RF_3T4R) { + if (rf_type > RF_3T4R) { tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 3); pextra += sprintf(pextra, ",pathd dBm=%d", tarpowerdbm); } } + wrqu->length = strlen(extra); return 0; @@ -693,47 +676,85 @@ int rtw_mp_txpower(struct net_device *dev, { u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0; int MsetPower = 1; - u8 input[RTW_IWD_MAX_LEN]; - u8 res = 0; - - PADAPTER padapter = rtw_netdev_priv(dev); - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; + char pout_str_buf[7]; + u8 input[RTW_IWD_MAX_LEN]; + u8 rfpath_i = 0; + u16 agc_cw_val = 0; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmppriv = &padapter ->mppriv; + u8 tx_nss = GET_HAL_TX_NSS(adapter_to_dvobj(padapter)); + char *pextra = extra; if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; MsetPower = strncmp(input, "off", 3); if (MsetPower == 0) { - padapter->mppriv.bSetTxPower = 0; - sprintf(extra, "MP Set power off"); + pmppriv->bSetTxPower = 0; + sprintf(pextra, "MP Set power off"); } else { - res = sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d); - if (res < 1) { - if(isdigit(input[0])){ - idx_a = rtw_atoi(input); - RTW_INFO("direct set RF Path A Power =%d\n", idx_a); - } else - RTW_INFO("Invalid format on %s !, Get patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d); + if (sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d) >= 1) { + pextra += sprintf(pextra, "Set power offset path_A:%d path_B:%d path_C:%d path_D:%d\n", idx_a , idx_b , idx_c , idx_d); + pmppriv->path_pwr_offset[RF_PATH_A] = (u8)idx_a; + pmppriv->path_pwr_offset[RF_PATH_B] = (u8)idx_b; + pmppriv->path_pwr_offset[RF_PATH_C] = (u8)idx_c; + pmppriv->path_pwr_offset[RF_PATH_D] = (u8)idx_d; + pmppriv->bSetTxPower = 1; + } else if (strncmp(input, "dbm", 3) == 0) { + u8 signed_flag = 0; + u8 ret = 0xff; + int int_num = 0; + u32 dec_num = 0; + s16 pout = 0; + int i; + u32 poutdbm = 0; + s32 db_temp = 0; + s16 pset = 0; + u8 rfpath; + + if (sscanf(input, "dbm=%7s", pout_str_buf) == 1) { + ret = 0; + } else { + sprintf(extra, "[dbm = -30 ~ 30.00]"); + goto invalid_param_format; } - if (res > 0 || idx_a !=0) - sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d); - else - sprintf(extra, "Invalid format on string :%s ", input); - padapter->mppriv.txpoweridx = (u8)idx_a; + if(pout_str_buf[0] == '-') + signed_flag = 1; + i = sscanf(pout_str_buf, "%d.%3u", &int_num, &dec_num); + RTW_INFO("%s: pars input =%d.%d\n", __func__, int_num, dec_num); + + if(i == 2) + dec_num = (dec_num < 10) ? dec_num * 10 : dec_num; + + if (int_num >= 30 || ret == 0xff || dec_num > 99 || (dec_num % 25 != 0)) { + sprintf(extra, "CMD Format:[dbm= -30.00 ~ 30.00]\n" + " each scale step value must 0.25 or -0.25\n"); + goto invalid_param_format; + } + + pset = int_num * TX_POWER_BASE + ((dec_num * TX_POWER_BASE) / 100); + RTW_INFO("%s: pset=%d\n", __func__, pset); + pset = ((pset < 0 || signed_flag == 1) ? -pset : pset); + - pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a; - pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b; - pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c; - pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)idx_d; - padapter->mppriv.bSetTxPower = 1; + pextra += sprintf(pextra, "Set power dbm :%d.%d\n", int_num, dec_num); + pmppriv->txpowerdbm = pset; + pmppriv->bSetTxPower = 1; + } else { + pextra += sprintf(pextra, "Invalid format on line %s\n", input); + RTW_INFO("Invalid format on line %s\n", input ); + wrqu->length = strlen(extra); + return 0; + } - SetTxPower(padapter); + for (rfpath_i = 0 ; rfpath_i < tx_nss; rfpath_i ++) { + agc_cw_val = rtw_mp_txpower_dbm(padapter, rfpath_i); + pextra += sprintf(pextra, "Path:%d PwrAGC:%d\n", rfpath_i,agc_cw_val); + } } +invalid_param_format: wrqu->length = strlen(extra); return 0; } @@ -744,51 +765,42 @@ int rtw_mp_ant_tx(struct net_device *dev, struct iw_point *wrqu, char *extra) { u8 i; - u8 input[RTW_IWD_MAX_LEN]; - u16 antenna = 0; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + u8 input[RTW_IWD_MAX_LEN]; + u8 antenna = 0; + u16 pwr_dbm = 0; + _adapter *padapter = rtw_netdev_priv(dev); + char *pextra = extra; _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; input[wrqu->length] = '\0'; - sprintf(extra, "switch Tx antenna to %s", input); + pextra += sprintf(pextra, "switch Tx antenna to %s\n", input); for (i = 0; i < strlen(input); i++) { switch (input[i]) { case 'a': - antenna |= ANTENNA_A; + antenna |= MP_ANTENNA_A; break; case 'b': - antenna |= ANTENNA_B; + antenna |= MP_ANTENNA_B; break; case 'c': - antenna |= ANTENNA_C; + antenna |= MP_ANTENNA_C; break; case 'd': - antenna |= ANTENNA_D; + antenna |= MP_ANTENNA_D; break; } } /*antenna |= BIT(extra[i]-'a');*/ RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); - padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_trx = antenna; - /*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/ - pHalData->antenna_tx_path = antenna; - if (IS_HARDWARE_TYPE_8822C(padapter) && padapter->mppriv.antenna_tx == ANTENNA_B) { - if (padapter->mppriv.antenna_rx == ANTENNA_A || padapter->mppriv.antenna_rx == ANTENNA_B) { - padapter->mppriv.antenna_rx = ANTENNA_AB; - pHalData->AntennaRxPath = ANTENNA_AB; - RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__); - } - } SetAntenna(padapter); + pwr_dbm = rtw_mp_get_pwrtab_dbm(padapter, antenna); + pextra += sprintf(pextra, "read pwr dbm:%d", pwr_dbm); wrqu->length = strlen(extra); return 0; @@ -801,12 +813,8 @@ int rtw_mp_ant_rx(struct net_device *dev, { u8 i; u16 antenna = 0; - u8 input[RTW_IWD_MAX_LEN]; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + u8 input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -817,29 +825,25 @@ int rtw_mp_ant_rx(struct net_device *dev, _rtw_memset(extra, 0, wrqu->length); sprintf(extra, "switch Rx antenna to %s", input); - for (i = 0; i < strlen(input); i++) { switch (input[i]) { case 'a': - antenna |= ANTENNA_A; + antenna |= MP_ANTENNA_A; break; case 'b': - antenna |= ANTENNA_B; + antenna |= MP_ANTENNA_B; break; case 'c': - antenna |= ANTENNA_C; + antenna |= MP_ANTENNA_C; break; case 'd': - antenna |= ANTENNA_D; + antenna |= MP_ANTENNA_D; break; } } - RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); - padapter->mppriv.antenna_rx = antenna; - pHalData->AntennaRxPath = antenna; - /*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/ + padapter->mppriv.antenna_trx = antenna; SetAntenna(padapter); wrqu->length = strlen(extra); @@ -855,7 +859,7 @@ int rtw_set_ctx_destAddr(struct net_device *dev, struct pkt_attrib *pattrib; struct mp_priv *pmp_priv; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; pattrib = &pmp_priv->tx.attrib; @@ -884,8 +888,7 @@ int rtw_mp_ctx(struct net_device *dev, u8 status; struct mp_priv *pmp_priv; struct pkt_attrib *pattrib; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _adapter *padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; pattrib = &pmp_priv->tx.attrib; @@ -903,7 +906,7 @@ int rtw_mp_ctx(struct net_device *dev, RTW_INFO("%s: in=%s\n", __func__, extra); #ifdef CONFIG_CONCURRENT_MODE if (!is_primary_adapter(padapter)) { - sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + sprintf(extra, "Error: MP mode can't support Virtual adapter, Please to use main adapter.\n"); wrqu->length = strlen(extra); return 0; } @@ -965,35 +968,12 @@ int rtw_mp_ctx(struct net_device *dev, return 0; } else if (stop == 0) { - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; - _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; - - u32 i = 0; bStartTest = 0; /* To set Stop*/ pmp_priv->tx.stop = 1; sprintf(extra, "Stop continuous Tx"); - odm_write_dig(&pHalData->odmpriv, 0x20); - do { - if (pxmitpriv->free_xmitframe_cnt == NR_XMITFRAME && pxmitpriv->free_xmitbuf_cnt == NR_XMITBUFF) - break; - else { - i++; - RTW_INFO("%s:wait queue_empty %d!!\n", __func__, i); - rtw_msleep_os(10); - } - } while (i < 1000); } else { bStartTest = 1; - odm_write_dig(&pHalData->odmpriv, 0x3f); - if (IS_HARDWARE_TYPE_8822C(padapter) && pmp_priv->antenna_tx == ANTENNA_B) { - if (pmp_priv->antenna_rx == ANTENNA_A || pmp_priv->antenna_rx == ANTENNA_B) { - pmp_priv->antenna_rx = ANTENNA_AB; - pHalData->AntennaRxPath = ANTENNA_AB; - RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__); - SetAntenna(padapter); - } - } + if (pmp_priv->mode != MP_ON) { if (pmp_priv->tx.stop != 1) { RTW_INFO("%s:Error MP_MODE %d != ON\n", __func__, pmp_priv->mode); @@ -1030,16 +1010,13 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { -#ifdef CONFIG_BT_COEXIST - PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); +#ifdef CONFIG_BTC + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); #endif u8 input[RTW_IWD_MAX_LEN]; u32 bt_coexist; - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->data.length + 1))) - return -EFAULT; - _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) @@ -1049,66 +1026,45 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, bt_coexist = rtw_atoi(input); +#if 0 if (bt_coexist == 0) { RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n"); -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC rtw_btcoex_HaltNotify(padapter); rtw_btcoex_SetManualControl(padapter, _TRUE); /* Force to switch Antenna to WiFi*/ rtw_write16(padapter, 0x870, 0x300); rtw_write16(padapter, 0x860, 0x110); #endif - /* CONFIG_BT_COEXIST */ + /* CONFIG_BTC */ } else { -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC rtw_btcoex_SetManualControl(padapter, _FALSE); #endif } +#endif return 0; } int rtw_mp_arx(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra) + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) { - int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0; - int bmac_filter = 0, bmon = 0, bSmpCfg = 0; - u8 input[RTW_IWD_MAX_LEN]; - char *pch, *token, *tmp[2] = {0x00, 0x00}; - u32 i = 0, jj = 0, kk = 0, cnts = 0, ret; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmppriv = &padapter->mppriv; - struct dbg_rx_counter rx_counter; - - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 input[RTW_IWD_MAX_LEN]; + u32 ret; + char *pch, *token, *tmp[2] = {0x00, 0x00}; + u32 i = 0, jj = 0, kk = 0, cnts = 0; if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; RTW_INFO("%s: %s\n", __func__, input); -#ifdef CONFIG_CONCURRENT_MODE - if (!is_primary_adapter(padapter)) { - sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); - wrqu->length = strlen(extra); - return 0; - } -#endif - bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - bSetRxframe = (strncmp(input, "frametype", 9) == 0) ? 1 : 0; - /*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/ - bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0; - bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0; - bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0; - pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ - - if (bSetBssid == 1) { + if (strncmp(input, "setbssid=", 8) == 0) { pch = input; while ((token = strsep(&pch, "=")) != NULL) { if (i > 1) @@ -1123,23 +1079,23 @@ int rtw_mp_arx(struct net_device *dev, RTW_INFO("%s: cnts=%d\n", __func__, cnts); RTW_INFO("%s: data=%s\n", __func__, tmp[1]); for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) { - pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); - RTW_INFO("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]); + pmppriv->network_macaddr[jj] = + key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + RTW_INFO("network_macaddr[%d]=%x\n", + jj, pmppriv->network_macaddr[jj]); } } else return -EFAULT; pmppriv->bSetRxBssid = _TRUE; - } - if (bSetRxframe) { + } else if (strncmp(input, "frametype", 9) == 0) { if (strncmp(input, "frametype beacon", 16) == 0) pmppriv->brx_filter_beacon = _TRUE; else pmppriv->brx_filter_beacon = _FALSE; - } - if (bmac_filter) { - pmppriv->bmac_filter = bmac_filter; + } else if (strncmp(input, "accept_mac", 10) == 0) { + pmppriv->bmac_filter = _TRUE; pch = input; while ((token = strsep(&pch, "=")) != NULL) { if (i > 1) @@ -1160,34 +1116,52 @@ int rtw_mp_arx(struct net_device *dev, } else return -EFAULT; - } - - if (bStartRx) { + } else if (strncmp(input, "start", 5) == 0) { sprintf(extra, "start"); - SetPacketRx(padapter, bStartRx, _FALSE); - } else if (bStopRx) { - SetPacketRx(padapter, bStartRx, _FALSE); - pmppriv->bmac_filter = _FALSE; - pmppriv->bSetRxBssid = _FALSE; - sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); - } else if (bQueryPhy) { - _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); - rtw_dump_phy_rx_counters(padapter, &rx_counter); - RTW_INFO("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa); - RTW_INFO("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa); - sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa); + } else if (strncmp(input, "stop", 5) == 0) { + struct rtw_mp_rx_arg rx_arg; + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + rtw_mp_phl_query_rx(padapter, &rx_arg, 2); + if (rx_arg.cmd_ok) { + pmppriv->rx_pktcount = rx_arg.rx_ok; + pmppriv->rx_crcerrpktcount = rx_arg.rx_err; + RTW_INFO("phl_query_rx rx_ok=%d rx_err=%d\n", + pmppriv->rx_pktcount, pmppriv->rx_crcerrpktcount); + } else + RTW_WARN("phl_query_rx Fail !!!"); + + pmppriv->bmac_filter = _FALSE; + pmppriv->bSetRxBssid = _FALSE; + sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", + pmppriv->rx_pktcount, pmppriv->rx_crcerrpktcount, + pmppriv->rx_pktcount_filter_out); + + } else if (strncmp(input, "phy", 3) == 0) { + struct rtw_mp_rx_arg rx_arg; + + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + rtw_mp_phl_query_rx(padapter, &rx_arg, 0); + if (rx_arg.cmd_ok) + sprintf(extra, "Phy Received packet OK:%d CRC error:%d", + rx_arg.rx_ok, rx_arg.rx_err); + else + sprintf(extra, "PHL Phy Query Fail !!!"); - } else if (bQueryMac) { - _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); - rtw_dump_mac_rx_counters(padapter, &rx_counter); - sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n", - rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop); + } else if (strncmp(input, "mac", 3) == 0) { + struct rtw_mp_rx_arg rx_arg; - } + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + rtw_mp_phl_query_rx(padapter, &rx_arg, 1); + if (rx_arg.cmd_ok) + sprintf(extra, "Mac Received packet OK:%d CRC error:%d", + rx_arg.rx_ok, rx_arg.rx_err); + else + sprintf(extra, "Mac Phy Query Fail !!!"); - if (bmon == 1) { + } else if (strncmp(input, "mon=", 4) == 0) { + int bmon = 0; ret = sscanf(input, "mon=%d", &bmon); if (bmon == 1) { @@ -1197,32 +1171,132 @@ int rtw_mp_arx(struct net_device *dev, pmppriv->rx_bindicatePkt = _FALSE; sprintf(extra, "Indicating Receive Packet to network Stop\n"); } - } - if (bSmpCfg == 1) { - ret = sscanf(input, "smpcfg=%d", &bSmpCfg); + } else if (strncmp(input, "loopbk", 6) == 0) { + u32 val32 = rtw_phl_read32(dvobj->phl, 0xCC20); + val32 |= BIT0; + rtw_phl_write32(dvobj->phl, 0xCC20 , val32); + pmppriv->bloopback = _TRUE; + sprintf(extra , "Enter MAC LoopBack mode\n"); - if (bSmpCfg == 1) { - pmppriv->bRTWSmbCfg = _TRUE; - sprintf(extra , "Indicate By Simple Config Format\n"); - SetPacketRx(padapter, _TRUE, _TRUE); - } else { - pmppriv->bRTWSmbCfg = _FALSE; - sprintf(extra , "Indicate By Normal Format\n"); - SetPacketRx(padapter, _TRUE, _FALSE); + } else if (strncmp(input, "gain", 4) == 0) { + struct rtw_mp_rx_arg rx_arg; + u32 gain_val = 0xff; + u8 path_num = 0; + u8 rf_path = 0xff; + u8 iscck = 0xff; + u8 *pch = extra; + + switch (input[4]) { + case 'a': + rf_path = RF_PATH_A; + break; + case 'b': + rf_path = RF_PATH_B; + break; + case 'c': + rf_path = RF_PATH_C; + break; + case 'd': + rf_path = RF_PATH_D; + break; } - } - if (pmppriv->bloopback == _TRUE) { - sprintf(extra , "Enter MAC LoopBack mode\n"); -#if defined(CONFIG_RTL8814B) - /* 1. No adhoc, 2. Enable short cut */ - rtw_write32(padapter, 0x100, 0x0B000EFF); -#else - rtw_write32(padapter, 0x100, 0x0B0106FF); -#endif - RTW_INFO("0x100 :0x%x", rtw_read32(padapter, 0x100)); - rtw_write16(padapter, 0x608, 0x30c); - RTW_INFO("0x608 :0x%x", rtw_read32(padapter, 0x608)); + if ((sscanf(input + 5, "=0x%x,iscck=%hhd", &gain_val, &iscck) == 2) || + (sscanf(input + 5, "=%d,iscck=%hhd", &gain_val, &iscck) == 2)) + RTW_INFO("%s: read gain = %d , is cck =%d\n", __func__, gain_val, iscck); + + else if ((sscanf(input + 4, "=0x%x", &gain_val) == 1) || + (sscanf(input + 4, "=%d", &gain_val) == 1)) + iscck = (u8)rtw_mp_is_cck_rate(pmppriv->rateidx); + else { + sprintf(pch, "error format: gain=[Dec/Hex]\n" + "\t\tgaina or gainb=[Dec/Hex],iscck=0/1\n"); + wrqu->length = strlen(pch) + 1; + return 0; + } + + if (rf_path == 0xff) { + rf_path = RF_PATH_A; + path_num = GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter)) - 1; + } else + path_num = rf_path; + + if (gain_val == 0xff || iscck == 0xff) { + sprintf(extra, "error format: gaina or gainb=%d,iscck=%d\n", gain_val, iscck); + wrqu->length = strlen(extra) + 1; + return 0; + } + + for (; rf_path <= path_num ; rf_path++) { + RTW_INFO("%s:set Path:%d gain_offset=%d iscck=%d\n", + __func__, rf_path, gain_val, iscck); + + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + rx_arg.offset = (s8)gain_val; + rx_arg.iscck = iscck; + rtw_mp_phl_rx_gain_offset(padapter, &rx_arg, rf_path); + + if (rx_arg.cmd_ok) + pch += sprintf(pch, "Path %s: 0x%hhx Rx Gain offset OK\n\t\t", + (rf_path == RF_PATH_A) ? "A":(rf_path == RF_PATH_B) ? "B": + (rf_path == RF_PATH_C) ? "C":"D", gain_val); + } + } else if (strncmp(input, "rssi", 4) == 0) { + struct rtw_mp_rx_arg rx_arg; + u8 rssi_path = 0, all_path_num = 0; + char *pcar = extra; + u8 i = 0; + + if (strncmp(input, "rssi a", 6) == 0) + rssi_path = 0; + else if (strncmp(input, "rssi b", 6) == 0) + rssi_path = 1; + else + all_path_num = GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter)); + + if (all_path_num > 1) { + rssi_path = 0; + all_path_num = all_path_num - 1; + } else + all_path_num = rssi_path; + + RTW_INFO("%s:Query RSSI Path:%d to %d\n", __func__, rssi_path, all_path_num); + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + + for (i = rssi_path ; i <= all_path_num; i++) { + rx_arg.rf_path = i; + + rtw_mp_phl_rx_rssi(padapter, &rx_arg); + if (rx_arg.cmd_ok) { + int result_int = 0; + int result_dec = 0; + + result_int = (rx_arg.rssi / 2) -110; + result_dec = (rx_arg.rssi % 2); + if (result_dec == 1) { + result_dec = (result_dec * 10) / 2; + result_int += 1; + } + pcar += sprintf(pcar, "Path%d RSSI=%d.%d ", i, result_int, result_dec); + } else + pcar += sprintf(pcar, "Path%d RSSI Fail\n", i); + + } + } else if (strncmp(input, "physts", 6) == 0) { + struct rtw_mp_rx_arg rx_arg; + bool bon; + + if (strncmp(input, "physts on", 9) == 0) + bon = true; + else + bon = false; + + _rtw_memset((void *)&rx_arg, 0, sizeof(struct rtw_mp_rx_arg)); + rtw_mp_phl_rx_physts(padapter, &rx_arg, bon); + if (rx_arg.cmd_ok) + sprintf(extra, "start OK" ); + else + sprintf(extra, "start Fail"); } wrqu->length = strlen(extra) + 1; @@ -1236,15 +1310,14 @@ int rtw_mp_trx_query(struct net_device *dev, struct iw_point *wrqu, char *extra) { u32 txok, txfail, rxok, rxfail, rxfilterout; - PADAPTER padapter = rtw_netdev_priv(dev); - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; - if (PMacTxInfo.bEnPMacTx == TRUE) - txok = hal_mpt_query_phytxok(padapter); - else - txok = padapter->mppriv.tx.sended; + if (pmp_priv->rtw_mp_tx_method == RTW_MP_PMACT_TX) + rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_CMD_PHY_OK, pmp_priv->rtw_mp_tx_method, _FALSE); + + txok = padapter->mppriv.tx.sended; txfail = 0; rxok = padapter->mppriv.rx_pktcount; rxfail = padapter->mppriv.rx_crcerrpktcount; @@ -1266,53 +1339,52 @@ int rtw_mp_pwrtrk(struct net_device *dev, { u8 enable; u32 thermal; - s32 ret; - PADAPTER padapter = rtw_netdev_priv(dev); + s32 ret = 0; + _adapter *padapter = rtw_netdev_priv(dev); u8 input[RTW_IWD_MAX_LEN]; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; - if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; _rtw_memset(extra, 0, wrqu->length); - enable = 1; + enable = RTW_MP_TSSI_OFF; if (wrqu->length > 1) { /* not empty string*/ - if (strncmp(input, "stop", 4) == 0) { - enable = 0; - sprintf(extra, "mp tx power tracking stop"); - } else if (sscanf(input, "ther=%d", &thermal) == 1) { - ret = SetThermalMeter(padapter, (u8)thermal); - if (ret == _FAIL) - return -EPERM; - sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal); - } else - return -EINVAL; + if (strncmp(input, "off", 3) == 0) { + enable = RTW_MP_TSSI_OFF; + sprintf(extra, "TSSI power tracking off"); + } else if (strncmp(input, "on", 2) == 0) { + enable = RTW_MP_TSSI_ON; + sprintf(extra, "TSSI power tracking on"); + } else if (strncmp(input, "cal", 3) == 0) { + enable = RTW_MP_TSSI_CAL; + sprintf(extra, "TSSI cal"); + } else { + input[wrqu->length] = '\0'; + enable = rtw_atoi(input); + sprintf(extra, "TSSI power tracking %d", enable); + } + if (enable <= RTW_MP_TSSI_CAL) + ret = rtw_mp_set_tssi_pwrtrk(padapter, enable); + if (ret == false) + sprintf(extra, "set TSSI power tracking fail"); + } else { + enable = rtw_mp_get_tssi_pwrtrk(padapter); + sprintf(extra, "Get TSSI state: %d\n\ + incput (int/str): [0]:off / [1]:on / [2]:cal for TSSI Tracking", enable); } - - ret = SetPowerTracking(padapter, enable); - if (ret == _FAIL) - return -EPERM; - wrqu->length = strlen(extra); return 0; } - - int rtw_mp_psd(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - u8 input[RTW_IWD_MAX_LEN]; - - if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1))) - return -EFAULT; + _adapter *padapter = rtw_netdev_priv(dev); + u8 input[RTW_IWD_MAX_LEN]; _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -1335,79 +1407,25 @@ int rtw_mp_thermal(struct net_device *dev, u8 ret = 0; u16 ther_path_addr[4] = {0}; u16 cnt = 1; - PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + _adapter *padapter = rtw_netdev_priv(dev); int rfpath = RF_PATH_A; -#ifdef CONFIG_RTL8188E - ther_path_addr[0] = EEPROM_THERMAL_METER_88E; -#endif -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) - ther_path_addr[0] = EEPROM_THERMAL_METER_8812; -#endif -#ifdef CONFIG_RTL8192E - ther_path_addr[0] = EEPROM_THERMAL_METER_8192E; -#endif -#ifdef CONFIG_RTL8192F - ther_path_addr[0] = EEPROM_THERMAL_METER_8192F; -#endif -#ifdef CONFIG_RTL8723B - ther_path_addr[0] = EEPROM_THERMAL_METER_8723B; -#endif -#ifdef CONFIG_RTL8703B - ther_path_addr[0] = EEPROM_THERMAL_METER_8703B; -#endif -#ifdef CONFIG_RTL8723D - ther_path_addr[0] = EEPROM_THERMAL_METER_8723D; -#endif -#ifdef CONFIG_RTL8188F - ther_path_addr[0] = EEPROM_THERMAL_METER_8188F; -#endif -#ifdef CONFIG_RTL8188GTV - ther_path_addr[0] = EEPROM_THERMAL_METER_8188GTV; -#endif -#ifdef CONFIG_RTL8822B - ther_path_addr[0] = EEPROM_THERMAL_METER_8822B; -#endif -#ifdef CONFIG_RTL8821C - ther_path_addr[0] = EEPROM_THERMAL_METER_8821C; -#endif -#ifdef CONFIG_RTL8710B - ther_path_addr[0] = EEPROM_THERMAL_METER_8710B; -#endif -#ifdef CONFIG_RTL8822C - ther_path_addr[0] = EEPROM_THERMAL_METER_A_8822C; - ther_path_addr[1] = EEPROM_THERMAL_METER_B_8822C; -#endif -#ifdef CONFIG_RTL8814B - ther_path_addr[0] = EEPROM_THERMAL_METER_A_8814B; - ther_path_addr[1] = EEPROM_THERMAL_METER_B_8814B; - ther_path_addr[2] = EEPROM_THERMAL_METER_C_8814B; - ther_path_addr[3] = EEPROM_THERMAL_METER_D_8814B; -#endif -#ifdef CONFIG_RTL8723F - ther_path_addr[0] = EEPROM_THERMAL_METER_8723F; -#endif - if (copy_from_user(extra, wrqu->pointer, wrqu->length)) return -EFAULT; if ((strncmp(extra, "write", 6) == 0)) { +#if 0 int i; u16 raw_cursize = 0, raw_maxsize = 0; -#ifdef RTW_HALMAC + raw_maxsize = efuse_GetavailableSize(padapter); -#else - efuse_GetCurrentSize(padapter, &raw_cursize); - raw_maxsize = efuse_GetMaxSize(padapter); -#endif RTW_INFO("[eFuse available raw size]= %d bytes\n", raw_maxsize - raw_cursize); if (2 > raw_maxsize - raw_cursize) { RTW_INFO("no available efuse!\n"); return -EFAULT; } - for (i = 0; i < hal_spec->rf_reg_path_num; i++) { + for (i = 0; i < GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter)); i++) { GetThermalMeter(padapter, i , &val[i]); if (ther_path_addr[i] != 0 && val[i] != 0) { if (rtw_efuse_map_write(padapter, ther_path_addr[i], cnt, &val[i]) == _FAIL) { @@ -1419,6 +1437,7 @@ int rtw_mp_thermal(struct net_device *dev, return -EFAULT; } } +#endif _rtw_memset(extra, 0, wrqu->length); sprintf(extra, " efuse write ok :%d", val[0]); } else { @@ -1427,15 +1446,16 @@ int rtw_mp_thermal(struct net_device *dev, rfpath = RF_PATH_A; RTW_INFO("default thermal of path(%d)\n", rfpath); } - if (rfpath >= hal_spec->rf_reg_path_num) + if (rfpath >= GET_HAL_RFPATH_NUM(adapter_to_dvobj(padapter))) return -EINVAL; RTW_INFO("read thermal of path(%d)\n", rfpath); GetThermalMeter(padapter, rfpath, &val[0]); _rtw_memset(extra, 0, wrqu->length); - sprintf(extra, "%d", val[0]); + sprintf(extra, "%d [0x%hhx]", val[0], val[0]); } + wrqu->length = strlen(extra); return 0; @@ -1448,7 +1468,7 @@ int rtw_mp_reset_stats(struct net_device *dev, struct iw_point *wrqu, char *extra) { struct mp_priv *pmp_priv; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; @@ -1458,8 +1478,7 @@ int rtw_mp_reset_stats(struct net_device *dev, pmp_priv->rx_pktcount_filter_out = 0; pmp_priv->rx_crcerrpktcount = 0; - rtw_reset_phy_rx_counters(padapter); - rtw_reset_mac_rx_counters(padapter); + rtw_mp_reset_phy_count(padapter); _rtw_memset(extra, 0, wrqu->length); sprintf(extra, "mp_reset_stats ok\n"); @@ -1474,21 +1493,18 @@ int rtw_mp_dump(struct net_device *dev, struct iw_point *wrqu, char *extra) { struct mp_priv *pmp_priv; - u8 input[RTW_IWD_MAX_LEN]; - PADAPTER padapter = rtw_netdev_priv(dev); + u8 input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; - if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; if (strncmp(input, "all", 4) == 0) { - mac_reg_dump(RTW_DBGDUMP, padapter); - bb_reg_dump(RTW_DBGDUMP, padapter); - rf_reg_dump(RTW_DBGDUMP, padapter); + //mac_reg_dump(RTW_DBGDUMP, padapter); + //bb_reg_dump(RTW_DBGDUMP, padapter); + //rf_reg_dump(RTW_DBGDUMP, padapter); } return 0; } @@ -1499,56 +1515,33 @@ int rtw_mp_phypara(struct net_device *dev, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - char input[RTW_IWD_MAX_LEN]; - u32 invalxcap = 0, ret = 0, bwrite_xcap = 0, hwxtaladdr = 0; - u16 pgval; + _adapter *padapter = rtw_netdev_priv(dev); + char input[RTW_IWD_MAX_LEN]; + u32 invalxcap = 0, ret = 0; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; RTW_INFO("%s:priv in=%s\n", __func__, input); - bwrite_xcap = (strncmp(input, "write_xcap=", 11) == 0) ? 1 : 0; - - if (bwrite_xcap == 1) { - ret = sscanf(input, "write_xcap=%d", &invalxcap); - invalxcap = invalxcap & 0x7f; /* xtal bit 0 ~6 */ - RTW_INFO("get crystal_cap %d\n", invalxcap); - - if (IS_HARDWARE_TYPE_8822C(padapter) && ret == 1) { - hwxtaladdr = 0x110; - pgval = invalxcap | 0x80; /* reserved default bit7 on */ - pgval = pgval | pgval << 8; /* xtal xi/xo efuse 0x110 0x111 */ - - RTW_INFO("Get crystal_cap 0x%x\n", pgval); - if (rtw_efuse_map_write(padapter, hwxtaladdr, 2, (u8*)&pgval) == _FAIL) { - RTW_INFO("%s: rtw_efuse_map_write xcap error!!\n", __func__); - sprintf(extra, "write xcap pgdata fail"); - ret = -EFAULT; - } else - sprintf(extra, "write xcap pgdata ok"); - } - } else { - ret = sscanf(input, "xcap=%d", &invalxcap); - - if (ret == 1) { - pHalData->crystal_cap = (u8)invalxcap; - RTW_INFO("%s:crystal_cap=%d\n", __func__, pHalData->crystal_cap); + if (strncmp(input, "xcap=", 5) == 0) { + if ((sscanf(input+4, "=0x%x", &invalxcap) == 1) || + (sscanf(input+4, "=%d", &invalxcap) == 1)) { + if (invalxcap < 255) { + rtw_mp_set_crystal_cap(padapter, invalxcap); + sprintf(extra, "Set xcap = %d [0x%hhx]", invalxcap, invalxcap); + } else + sprintf(extra, "Error formats , inpunt value over 255 !\n"); - if (rtw_phydm_set_crystal_cap(padapter, pHalData->crystal_cap) == _FALSE) { - RTW_ERR("set crystal_cap failed\n"); - rtw_warn_on(1); - } - sprintf(extra, "Set xcap=%d", invalxcap); + wrqu->length = strlen(extra); + return ret; } } - wrqu->length = strlen(extra) + 1; + sprintf(extra, "Error formats , inpunt [xcap=%%d/0x%%x]\n"); + + wrqu->length = strlen(extra); return ret; } @@ -1557,21 +1550,18 @@ int rtw_mp_SetRFPath(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - char input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); + char input[RTW_IWD_MAX_LEN]; int bMain = 1, bTurnoff = 1; #ifdef CONFIG_ANTENNA_DIVERSITY u8 ret = _TRUE; #endif - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; - RTW_INFO("%s:iwpriv in=%s\n", __func__, input); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; - +#if 0 bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/ bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ @@ -1599,7 +1589,7 @@ int rtw_mp_SetRFPath(struct net_device *dev, RTW_INFO("%s:Query RF Path = %s\n", __func__, (bMain ? "Main":"Aux")); sprintf(extra, "RF Path %s\n" , (bMain ? "1":"0")); } - +#endif wrqu->length = strlen(extra); return 0; @@ -1610,15 +1600,12 @@ int rtw_mp_switch_rf_path(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv; - char input[RTW_IWD_MAX_LEN]; - char *pch; + char input[RTW_IWD_MAX_LEN]; int bwlg = 1, bwla = 1, btg = 1, bbt=1; u8 ret = 0; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; @@ -1627,27 +1614,25 @@ int rtw_mp_switch_rf_path(struct net_device *dev, RTW_INFO("%s: in=%s\n", __func__, input); - _rtw_memset(extra, '\0', wrqu->length); - pch = extra; #ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */ if ((strncmp(input, "WLG", 3) == 0) || (strncmp(input, "1", 1) == 0)) { pmp_priv->rf_path_cfg = SWITCH_TO_WLG; - pch += sprintf(pch, "switch rf path WLG\n"); + sprintf(extra, "switch rf path WLG\n"); } else if ((strncmp(input, "WLA", 3) == 0) || (strncmp(input, "2", 1) == 0)) { pmp_priv->rf_path_cfg = SWITCH_TO_WLA; - pch += sprintf(pch, "switch rf path WLA\n"); + sprintf(extra, "switch rf path WLA\n"); } else if ((strncmp(input, "BTG", 3) == 0) || (strncmp(input, "0", 1) == 0)) { pmp_priv->rf_path_cfg = SWITCH_TO_BTG; - pch += sprintf(pch, "switch rf path BTG\n"); + sprintf(extra, "switch rf path BTG\n"); } else if ((strncmp(input, "BT", 3) == 0) || (strncmp(input, "3", 1) == 0)) { pmp_priv->rf_path_cfg = SWITCH_TO_BT; - pch += sprintf(pch, "switch rf path BT\n"); + sprintf(extra, "switch rf path BT\n"); } else { pmp_priv->rf_path_cfg = SWITCH_TO_WLG; - pch += sprintf(pch, "Error input, default set WLG\n"); + sprintf(extra, "Error input, default set WLG\n"); return -EFAULT; } @@ -1662,14 +1647,10 @@ int rtw_mp_QueryDrv(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - char input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); + char input[RTW_IWD_MAX_LEN]; int qAutoLoad = 1; - - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->data.length)) - return -EFAULT; + //struct efuse_info *efuse = adapter_to_efuse(padapter); if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; @@ -1680,10 +1661,10 @@ int rtw_mp_QueryDrv(struct net_device *dev, if (qAutoLoad == 0) { RTW_INFO("%s:qAutoLoad\n", __func__); - if (pHalData->bautoload_fail_flag) - sprintf(extra, "fail"); - else - sprintf(extra, "ok"); + //if (efuse->is_autoload_fail) + // sprintf(extra, "fail"); + //else + // sprintf(extra, "ok"); } wrqu->data.length = strlen(extra) + 1; return 0; @@ -1694,25 +1675,22 @@ int rtw_mp_PwrCtlDM(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - u8 input[RTW_IWD_MAX_LEN]; + _adapter *padapter = rtw_netdev_priv(dev); + u8 input[RTW_IWD_MAX_LEN]; u8 pwrtrk_state = 0; u8 pwtk_type[5][25] = {"Thermal tracking off","Thermal tracking on", "TSSI tracking off","TSSI tracking on","TSSI calibration"}; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) + if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; - if (copy_from_user(input, wrqu->pointer, wrqu->length)) - return -EFAULT; - - input[wrqu->length - 1] = '\0'; + input[wrqu->length] = '\0'; RTW_INFO("%s: in=%s\n", __func__, input); if (wrqu->length == 2) { if(input[0] >= '0' && input[0] <= '4') { pwrtrk_state = rtw_atoi(input); - MPT_PwrCtlDM(padapter, pwrtrk_state); + /*MPT_PwrCtlDM(padapter, pwrtrk_state);*/ sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]); } else { sprintf(extra, "Error unknown number ! Please check your input number\n" @@ -1739,16 +1717,15 @@ int rtw_mp_PwrCtlDM(struct net_device *dev, pwrtrk_state = 4; sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]); } else { - sprintf(extra, "Error input !!!\n" + pwrtrk_state = 0; + sprintf(extra, "Error input, default PwrCtlDM stop\n" " thertrk off : Thermal tracking off\n thertrk on : Thermal tracking on\n" " tssitrk off : TSSI tracking off\n tssitrk on : TSSI tracking on\n tssik : TSSI calibration\n\n" " 0 : Thermal tracking off\n 1 : Thermal tracking on\n 2 : TSSI tracking off\n" " 3 : TSSI tracking on\n 4 : TSSI calibration\n"); - wrqu->length = strlen(extra); - return 0; } - MPT_PwrCtlDM(padapter, pwrtrk_state); + /*MPT_PwrCtlDM(padapter, pwrtrk_state);*/ wrqu->length = strlen(extra); return 0; @@ -1758,7 +1735,7 @@ int rtw_mp_iqk(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); rtw_mp_trigger_iqk(padapter); @@ -1769,7 +1746,7 @@ int rtw_mp_lck(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); rtw_mp_trigger_lck(padapter); @@ -1780,34 +1757,31 @@ int rtw_mp_dpk(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; + _adapter *padapter = rtw_netdev_priv(dev); + //struct dm_struct *phydm = adapter_to_phydm(padapter); struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - char *pch; u8 ips_mode = IPS_NUM; /* init invalid value */ - u8 lps_mode = PS_MODE_NUM; /* init invalid value */ + u8 lps_mode = PM_PS_MODE_NUM; /* init invalid value */ if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; *(extra + wrqu->data.length) = '\0'; - pch = extra; if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { - pDM_Odm->dpk_info.is_dpk_enable = 0; - halrf_dpk_enable_disable(pDM_Odm); - pch += sprintf(pch, "set dpk off\n"); + //phydm->dpk_info.is_dpk_enable = 0; + //halrf_dpk_enable_disable(phydm); + sprintf(extra, "set dpk off\n"); } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { - pDM_Odm->dpk_info.is_dpk_enable = 1; - halrf_dpk_enable_disable(pDM_Odm); - pch += sprintf(pch, "set dpk on\n"); + //phydm->dpk_info.is_dpk_enable = 1; + //halrf_dpk_enable_disable(phydm); + sprintf(extra, "set dpk on\n"); } else { #ifdef CONFIG_LPS lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ - rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + rtw_pm_set_lps(padapter, PM_PS_MODE_ACTIVE); #endif #ifdef CONFIG_IPS ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ @@ -1823,7 +1797,7 @@ int rtw_mp_dpk(struct net_device *dev, rtw_pm_set_lps(padapter, lps_mode); #endif /* CONFIG_LPS */ } - pch += sprintf(pch, "set dpk trigger\n"); + sprintf(extra, "set dpk trigger\n"); } wrqu->data.length = strlen(extra); @@ -1835,32 +1809,19 @@ int rtw_mp_get_tsside(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; + _adapter *padapter = rtw_netdev_priv(dev); char input[RTW_IWD_MAX_LEN]; - u8 rfpath; - u32 tssi_de; - - u8 legal_param_num = 1; - int param_num; - char pout_str_buf[8]; - u8 signed_flag = 0; - int integer_num; - u32 decimal_num; - s32 pout; - char *pextra; + u8 rfpath = 0xff; + s8 tssi_de = 0; + char pout_str_buf[7]; + char tgr_str_buf[7]; + u8 pout_signed_flag = 0 , tgrpwr_signed_flag = 0; + int int_num = 0; + u32 dec_num = 0; + s32 pout = 0; + s32 tgrpwr = 0; int i; - #ifdef CONFIG_RTL8723F - /* - * rtwpriv wlan0 mp_get_tsside rf_path pout - * rf_path : 0 ~ 1 - * pout : -15.000 ~ 25.000 - * ex : rtwpriv wlan0 mp_get_tsside 0 -12.123 - */ - legal_param_num = 2; - #endif if (wrqu->length > 128) return -EFAULT; @@ -1868,61 +1829,104 @@ int rtw_mp_get_tsside(struct net_device *dev, if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; - param_num = sscanf(input, "%hhu %7s", &rfpath, pout_str_buf); - - /* Check parameter format*/ - if(param_num != legal_param_num) - goto invalid_param_format; - - if(rfpath <0 || 3 < rfpath) - goto invalid_param_format; - -#ifdef CONFIG_RTL8723F - /* Convert pout from floating-point to integer - * For Floating-Point Precision, pout*1000 - */ - if(pout_str_buf[0] == '-') - signed_flag = 1; - i = sscanf(pout_str_buf, "%d.%3u", &integer_num, &decimal_num); - pout = integer_num * 1000; - if(i == 2) { - /* Convert decimal number - * ex : 0.1 => 100, -0.1 => 100 - */ - decimal_num = (decimal_num < 10) ? decimal_num * 100 : decimal_num; - decimal_num = (decimal_num < 100) ? decimal_num * 10 : decimal_num; - pout += ((pout < 0 || signed_flag == 1) ? -decimal_num : decimal_num); - } - if(pout < -15000 || 25000 < pout) - goto invalid_param_format; -#endif + if (wrqu->length == 2) { + rfpath = rtw_atoi(input); + if (rfpath >= 0 && rfpath <= 3) { + tssi_de = rtw_mp_get_tssi_de(padapter, rfpath); + } else + sprintf(extra, "Invalid command format, please indicate RF path 0/1/2/3"); + + } else if (sscanf(input + 1, "dbm=%7s pwr=%7s", tgr_str_buf , pout_str_buf) == 2) { + /* + * rtwpriv wlan0 mp_get_tsside adbm=12 pwr=12 + * [adbm] target power [pwr] output power + * rf_path : 0 = adbm , 1 = bdbm + * dbm : -15.00 ~ 25.00 + * pwr : -15.00 ~ 25.00 + * ex : rtwpriv wlan0 mp_get_tsside adbm=16 pwr=14.25 + */ + RTW_INFO("%s: in=tgr_str %s pout_str %s\n", __func__, tgr_str_buf , pout_str_buf); + switch (input[0]) { + case 'a': + rfpath = RF_PATH_A; + break; + case 'b': + rfpath = RF_PATH_B; + break; + case 'c': + rfpath = RF_PATH_C; + break; + case 'd': + rfpath = RF_PATH_D; + break; + default: + goto error; + break; + } -#ifdef CONFIG_RTL8723F - /* For Floating-Point Precision, pout */ - tssi_de = halrf_get_online_tssi_de(pDM_Odm, rfpath, pout); -#else - tssi_de = halrf_tssi_get_de(pDM_Odm, rfpath); -#endif + if(pout_str_buf[0] == '-') + pout_signed_flag = 1; + + i = sscanf(pout_str_buf, "%d.%2u", &int_num, &dec_num); + pout = int_num * 100; + RTW_DBG("%s:pout %d int %d dec %d\n", __func__, pout, int_num , dec_num); + + if (i == 2) { + /* Convert decimal number + * ex : 0.1 => 100, -0.1 => 100*/ + dec_num = (dec_num < 1) ? dec_num * 10 : dec_num; + dec_num = (dec_num < 10) ? dec_num * 1 : dec_num; + pout += ((pout < 0 || pout_signed_flag == 1) ? -dec_num : dec_num); + } + if (pout < -1500 || 2500 < pout) + goto error; + RTW_INFO("%s:pout %d\n", __func__, pout); + + if (tgr_str_buf[0] == '-') + tgrpwr_signed_flag = 1; + + int_num = 0; + dec_num = 0; + + i = sscanf(tgr_str_buf, "%d.%2u", &int_num, &dec_num); + tgrpwr = int_num * 100; + RTW_DBG("%s:tgrpwr %d int %d dec %d\n", __func__, tgrpwr, int_num , dec_num); + + if (i == 2) { + /* Convert decimal number + * ex : 0.1 => 100, -0.1 => 100*/ + dec_num = (dec_num < 1) ? dec_num * 10 : dec_num; + dec_num = (dec_num < 10) ? dec_num * 1 : dec_num; + tgrpwr += ((tgrpwr < 0 || tgrpwr_signed_flag == 1) ? -dec_num : dec_num); + } + if (tgrpwr < -1500 || 2500 < tgrpwr) + goto error; + RTW_INFO("%s:tgrpwr %d\n", __func__, tgrpwr); + + tssi_de = (s8)rtw_mp_get_online_tssi_de(padapter, pout, tgrpwr, rfpath); + } if (rfpath == 0) - sprintf(extra, "patha=%d hex=%02x", tssi_de, (u8)tssi_de); + sprintf(extra, "patha=%d hex:%x", tssi_de, (u8)tssi_de); else if (rfpath == 1) - sprintf(extra, "pathb=%d hex=%02x", tssi_de, (u8)tssi_de); + sprintf(extra, "pathb=%d hex:%x", tssi_de, (u8)tssi_de); else if (rfpath == 2) - sprintf(extra, "pathc=%d hex=%02x", tssi_de, (u8)tssi_de); + sprintf(extra, "pathc=%d hex:%x", tssi_de, (u8)tssi_de); else if (rfpath == 3) - sprintf(extra, "pathd=%d hex=%02x", tssi_de, (u8)tssi_de); + sprintf(extra, "pathd=%d hex:%x", tssi_de, (u8)tssi_de); + else + goto error; wrqu->length = strlen(extra); return 0; +error: -invalid_param_format: - sprintf(extra, "Invalid command format, please indicate RF path 0/1/2/3"); -#ifdef CONFIG_RTL8723F - pextra = extra + strlen(extra); - sprintf(pextra, " and pout value : -15.000 ~ 25.000\n"); -#endif + sprintf(extra, "Invalid command format, please indicate RF path mp_get_tsside [0/1/2/3]\n\ + GET ONLINE TSSI DE:\n\ + mp_get_tsside adbm=-15.00 ~ 25.00 pwr=-15.00 ~ 25.00\n\ + mp_get_tsside bdbm=-15.00 ~ 25.00 pwr=-15.00 ~ 25.00\n"); wrqu->length = strlen(extra); return 0; @@ -1932,41 +1936,54 @@ int rtw_mp_set_tsside(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - u32 tsside_a = 0, tsside_b = 0, tsside_c = 0, tsside_d = 0; + u32 tsside_val = 0; + u8 rf_path = RF_PATH_A; char input[RTW_IWD_MAX_LEN]; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; - - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; + _adapter *padapter = rtw_netdev_priv(dev); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; - if (sscanf(input, "patha=%d", &tsside_a) == 1) { - sprintf(extra, "Set TSSI DE path_A: %d", tsside_a); - halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_a, RF_PATH_A); - mpt_trigger_tssi_tracking(padapter, RF_PATH_A); + RTW_INFO("%s:input =[%s]\n", __func__, input); - } else if (sscanf(input, "pathb=%d", &tsside_b) == 1) { - sprintf(extra, "Set TSSI DE path_B: %d", tsside_b); - halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_b, RF_PATH_B); - mpt_trigger_tssi_tracking(padapter, RF_PATH_B); + switch (input[4]) { + case 'a': + rf_path = RF_PATH_A; + break; + case 'b': + rf_path = RF_PATH_B; + break; + case 'c': + rf_path = RF_PATH_C; + break; + case 'd': + rf_path = RF_PATH_D; + break; + default: + goto exit_err; + } + + if ((sscanf(input+5, "=0x%x", &tsside_val) == 1) || + (sscanf(input+5, "=%d", &tsside_val) == 1)) { + if (tsside_val > 255) + sprintf(extra, "Error TSSI DE value: %d over 255" , tsside_val); + else { + sprintf(extra, "Set TSSI DE path_%s: %d", + rf_path == RF_PATH_A ? "A" : rf_path == RF_PATH_B ? "B" : + rf_path == RF_PATH_C ? "C":"D", tsside_val); + rtw_mp_set_tsside2verify(padapter, tsside_val, rf_path); + } + } else + goto exit_err; - } else if (sscanf(input, "pathc=%d", &tsside_c) == 1) { - sprintf(extra, "Set TSSI DE path_C: %d", tsside_c); - halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_c, RF_PATH_C); - mpt_trigger_tssi_tracking(padapter, RF_PATH_C); + wrqu->length = strlen(extra); - } else if (sscanf(input, "pathd=%d", &tsside_d) == 1) { - sprintf(extra, "Set TSSI DE path_D: %d", tsside_d); - halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_d, RF_PATH_D); - mpt_trigger_tssi_tracking(padapter, RF_PATH_D); + return 0; - } else - sprintf(extra, "Invalid command format, please input TSSI DE value within patha/b/c/d=xyz"); +exit_err: + sprintf(extra, "Invalid command format,\n\t\t" + "please input TSSI DE value within patha/b/c/d=[decimal] or [hex:0xXX]"); wrqu->length = strlen(extra); @@ -1977,7 +1994,7 @@ int rtw_mp_getver(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv; pmp_priv = &padapter->mppriv; @@ -1995,10 +2012,10 @@ int rtw_mp_mon(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv = &padapter->mppriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct hal_ops *pHalFunc = &padapter->hal_func; + //struct hal_ops *pHalFunc = &hal->hal_func; NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; int bstart = 1, bstop = 1; @@ -2010,7 +2027,7 @@ int rtw_mp_mon(struct net_device *dev, rtw_pm_set_ips(padapter, IPS_NONE); LeaveAllPowerSaveMode(padapter); -#ifdef CONFIG_MP_INCLUDED +#if 0 //def CONFIG_MP_INCLUDED if (init_mp_priv(padapter) == _FAIL) RTW_INFO("%s: initialize MP private data Fail!\n", __func__); padapter->mppriv.channel = 6; @@ -2046,7 +2063,7 @@ int rtw_mp_mon(struct net_device *dev, return 0; } -int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) +int rtw_mp_pretx_proc(_adapter *padapter, u8 bstart, char *extra) { struct mp_priv *pmp_priv = &padapter->mppriv; char *pextra = extra; @@ -2054,55 +2071,50 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) switch (pmp_priv->mode) { case MP_PACKET_TX: - if (bStartTest == 0) { + if (bstart == 0) { pmp_priv->tx.stop = 1; pmp_priv->mode = MP_ON; - #ifdef CONFIG_RTL8822B - rtw_write8(padapter, 0x838, 0x61); - #endif sprintf(extra, "Stop continuous Tx"); } else if (pmp_priv->tx.stop == 1) { pextra = extra + strlen(extra); pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count); pmp_priv->tx.stop = 0; - #ifdef CONFIG_RTL8822B - rtw_write8(padapter, 0x838, 0x6d); - #endif - SetPacketTx(padapter); + /*SetPacketTx(padapter);*/ } else return -EFAULT; + rtw_set_phl_packet_tx(padapter, bstart); return 0; case MP_SINGLE_TONE_TX: - if (bStartTest != 0) + if (bstart != 0) strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); - SetSingleToneTx(padapter, (u8)bStartTest); + + rtw_mp_singletone_tx(padapter, (u8)bstart); break; case MP_CONTINUOUS_TX: - if (bStartTest != 0) + if (bstart != 0) strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); - SetContinuousTx(padapter, (u8)bStartTest); + rtw_mp_continuous_tx(padapter, (u8)bstart); break; case MP_CARRIER_SUPPRISSION_TX: - if (bStartTest != 0) { - if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M) + if (bstart != 0) { + if (rtw_mp_hwrate2mptrate(pmp_priv->rateidx) <= MPT_RATE_11M) strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); else strcat(extra, "\nSpecify carrier suppression but not CCK rate"); } - SetCarrierSuppressionTx(padapter, (u8)bStartTest); + rtw_mp_carriersuppr_tx(padapter, (u8)bstart); break; case MP_SINGLE_CARRIER_TX: - if (bStartTest != 0) + if (bstart != 0) strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); - SetSingleCarrierTx(padapter, (u8)bStartTest); + rtw_mp_singlecarrier_tx(padapter, (u8)bstart); break; - default: sprintf(extra, "Error! Continuous-Tx is not on-going."); return -EFAULT; } - if (bStartTest == 1 && pmp_priv->mode != MP_ON) { + if (bstart == 1 && pmp_priv->mode != MP_ON) { struct mp_priv *pmp_priv = &padapter->mppriv; if (pmp_priv->tx.stop == 0) { @@ -2116,20 +2128,15 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) #endif pmp_priv->tx.stop = 0; pmp_priv->tx.count = 1; - SetPacketTx(padapter); + if (pmp_priv->rtw_mp_tx_method == RTW_MP_PMACT_TX) { + pmp_priv->rtw_mp_tx_method = RTW_MP_TMACT_TX; + rtw_set_phl_packet_tx(padapter, bstart); /* send 1 pkt for trigger HW non-pkt Tx*/ + pmp_priv->rtw_mp_tx_method = RTW_MP_PMACT_TX; + } + /*SetPacketTx(padapter);*/ } else pmp_priv->mode = MP_ON; -#if defined(CONFIG_RTL8812A) - if (IS_HARDWARE_TYPE_8812AU(padapter)) { - /* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/ - if (pmp_priv->mode == MP_PACKET_TX) - phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1); - else - phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0); - } -#endif - return 0; } @@ -2138,8 +2145,7 @@ int rtw_mp_tx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv = &padapter->mppriv; PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); char *pextra = extra; @@ -2153,9 +2159,10 @@ int rtw_mp_tx(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; RTW_INFO("extra = %s\n", extra); +#if 0 #ifdef CONFIG_CONCURRENT_MODE if (!is_primary_adapter(padapter)) { - sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + sprintf(extra, "Error: MP mode can't support Virtual adapter, Please to use main adapter.\n"); wrqu->data.length = strlen(extra); return 0; } @@ -2208,7 +2215,7 @@ int rtw_mp_tx(struct net_device *dev, pMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode; - pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/ + pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/ if (padapter->mppriv.pktInterval == 0) pMptCtx->PMacTxInfo.PacketPeriod = 100; @@ -2451,7 +2458,7 @@ int rtw_mp_tx(struct net_device *dev, } } - +#endif wrqu->data.length = strlen(extra); return status; } @@ -2461,8 +2468,7 @@ int rtw_mp_rx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv = &padapter->mppriv; char *pextra = extra; u32 bandwidth = 0, sg = 0, channel = 6, ant = 0; @@ -2471,10 +2477,10 @@ int rtw_mp_rx(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; - +#if 0 #ifdef CONFIG_CONCURRENT_MODE if (!is_primary_adapter(padapter)) { - sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + sprintf(extra, "Error: MP mode can't support Virtual adapter, Please to use main adapter.\n"); wrqu->data.length = strlen(extra); return 0; } @@ -2574,6 +2580,7 @@ int rtw_mp_rx(struct net_device *dev, strcat(extra, "\nstart Rx"); SetPacketRx(padapter, bStartRx, _FALSE); } +#endif wrqu->data.length = strlen(extra); return 0; } @@ -2583,31 +2590,26 @@ int rtw_mp_hwtx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - char *pch; + PMPT_CONTEXT mpt_ctx = &(padapter->mppriv.mpt_ctx); -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \ - || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8723F) +#if defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; *(extra + wrqu->data.length) = '\0'; - _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); - _rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)extra, sizeof(RT_PMAC_TX_INFO)); + _rtw_memset(&mpt_ctx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); + _rtw_memcpy((void *)&mpt_ctx->PMacTxInfo, (void *)extra, sizeof(RT_PMAC_TX_INFO)); _rtw_memset(extra, 0, wrqu->data.length); - pch = extra; - if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) { - pch += sprintf(pch, "MP Tx Running, Please Set PMac Tx Mode Stop\n"); + if (mpt_ctx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) { + sprintf(extra, "MP Tx Running, Please Set PMac Tx Mode Stop\n"); RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n"); } else { RTW_INFO("To set MAC Tx mode\n"); - if (mpt_ProSetPMacTx(padapter)) - pch += sprintf(pch, "Set PMac Tx Mode OK\n"); - else - pch += sprintf(pch, "Set PMac Tx Mode Error\n"); + mpt_ProSetPMacTx(padapter); + sprintf(extra, "Set PMac Tx Mode OK\n"); } wrqu->data.length = strlen(extra); #endif @@ -2619,373 +2621,740 @@ int rtw_mp_pwrlmt(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct registry_priv *registry_par = &padapter->registrypriv; - char *pch; + u8 pwrlimtstat = 0; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; *(extra + wrqu->data.length) = '\0'; - pch = extra; - #if CONFIG_TXPWR_LIMIT if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { - padapter->registrypriv.RegEnableTxPowerLimit = 0; - pch += sprintf(pch, "Turn off Power Limit\n"); - + if (rtw_mpt_set_power_limit_en(padapter, _FALSE)) + sprintf(extra, "Turn off Power Limit\n"); + else + sprintf(extra, "Turn off Power Limit Fail\n"); } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { - padapter->registrypriv.RegEnableTxPowerLimit = 1; - pch += sprintf(pch, "Turn on Power Limit\n"); - + if (rtw_mpt_set_power_limit_en(padapter, _TRUE)) + sprintf(extra, "Turn on Power Limit\n"); + else + sprintf(extra, "Turn on Power Limit Fail\n"); } else #endif - pch += sprintf(pch, "Get Power Limit Status:%s\n", (registry_par->RegEnableTxPowerLimit == 1) ? "ON" : "OFF"); - - + { + sprintf(extra, "PHL PWRLMT:%s\n", + (rtw_mpt_get_power_limit_en(padapter) == _TRUE) ?"ON" :"OFF"); + } wrqu->data.length = strlen(extra); return 0; } -int rtw_mp_pwrbyrate(struct net_device *dev, +int rtw_mp_dpk_track(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); + //struct dm_struct *phydm = adapter_to_phydm(padapter); if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; *(extra + wrqu->data.length) = '\0'; + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { - padapter->registrypriv.RegEnableTxPowerByRate = 0; - sprintf(extra, "Turn off Tx Power by Rate\n"); + //halrf_set_dpk_track(phydm, FALSE); + sprintf(extra, "set dpk track off\n"); } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { - padapter->registrypriv.RegEnableTxPowerByRate = 1; - sprintf(extra, "Turn On Tx Power by Rate\n"); - - } else { - sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF"); + //halrf_set_dpk_track(phydm, TRUE); + sprintf(extra, "set dpk track on\n"); } wrqu->data.length = strlen(extra); return 0; } - -int rtw_mp_dpk_track(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +int rtw_mp_set_phl_io(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_struct *pDM_Odm = &pHalData->odmpriv; - char *pch; + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct phl_info_t *phl_info = (struct phl_info_t *)(dvobj->phl); + struct rtw_mp_cmd_arg *cmd_arg = NULL; + struct rtw_mp_test_cmdbuf *pcmdbuf = NULL; + u16 i = 0; - if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + RTW_INFO("%s, wrqu->length %d !!!\n", __func__, wrqu->length); + + rtw_phl_test_submodule_cmd_process(rtw_phl_get_com(phl_info), (void*)extra, wrqu->length); + pcmdbuf = (struct rtw_mp_test_cmdbuf *)extra; + while (1) { + if (pcmdbuf) { + cmd_arg = (struct rtw_mp_cmd_arg *)pcmdbuf->buf; + rtw_phl_test_submodule_get_rpt(rtw_phl_get_com(phl_info), (void *)extra, wrqu->length); + } + if (cmd_arg != NULL && cmd_arg->cmd_ok) { + RTW_INFO("%s,GET CMD OK !!!\n", __func__); + break; + } else { + i++; + rtw_msleep_os(100); + if (i == 3) { + RTW_INFO("%s,GET CMD FAIL !!!\n", __func__); + break; + } + } + } + + if (copy_to_user(wrqu->pointer, extra, wrqu->length)) return -EFAULT; - *(extra + wrqu->data.length) = '\0'; - pch = extra; + return 0; +} - if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { - halrf_set_dpk_track(pDM_Odm, FALSE); - pch += sprintf(pch, "set dpk track off\n"); +int rtw_mp_get_phl_io(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct phl_info_t *phl_info = (struct phl_info_t *)(padapter->dvobj->phl); - } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { - halrf_set_dpk_track(pDM_Odm, TRUE); - pch += sprintf(pch, "set dpk track on\n"); - } + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + *(extra + wrqu->length) = '\0'; + + rtw_phl_test_submodule_get_rpt(rtw_phl_get_com(phl_info), (void *)&extra, wrqu->length); + + wrqu->length = strlen(extra); - wrqu->data.length = strlen(extra); return 0; } +int rtw_mp_tx_pattern_idx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; -int rtw_bt_efuse_mask_file(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + u32 tx_patt_idx = 0; + u32 ppdu_type = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + if (sscanf(extra, "index=%d,type=%d", &tx_patt_idx, &ppdu_type) > 0) { + RTW_INFO("%s: tx_patt_idx=%d ,ppdu_type=%d\n", __func__, tx_patt_idx , ppdu_type); + pmp_priv->rtw_mp_pmact_patt_idx = tx_patt_idx; + pmp_priv->rtw_mp_pmact_ppdu_type = ppdu_type; + rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_CONFIG_PLCP_PATTERN, pmp_priv->rtw_mp_tx_method, _TRUE); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config Tx Pattern idx %d to %d", pmp_priv->rtw_mp_pmact_patt_idx, tx_patt_idx); + } else if ((strncmp(extra, "stop", 4) == 0)) { + rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_CONFIG_PLCP_PATTERN, pmp_priv->rtw_mp_tx_method, _FALSE); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config Tx Pattern Stop"); + } else { + u8 *pstr = extra; + _rtw_memset(pstr, 0, wrqu->data.length); + } + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_tx_plcp_tx_data(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - char *rtw_efuse_mask_file_path; - u8 *pch; - char *ptmp, tmp; - u8 Status; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 user_idx = pmp_priv->mp_plcp_useridx; - _rtw_memset(btmaskfileBuffer, 0x00, sizeof(btmaskfileBuffer)); if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; - *(extra + wrqu->data.length) = '\0'; - ptmp = extra; + if ((strncmp(extra, "ppdu", 4) == 0)) { + u32 ppdu_type = 0; - if (strncmp(extra, "data,", 5) == 0) { - u8 count = 0; - u8 i = 0; + if (sscanf(extra, "ppdu=%d", &ppdu_type) > 0) { + u8 *pextra = extra; - pch = strsep(&ptmp, ","); + RTW_INFO("%s: ppdu_type=%d\n", __func__, ppdu_type); + _rtw_memset(extra, 0, wrqu->data.length); - if ((pch == NULL) || (strlen(pch) == 0)) { - RTW_INFO("%s: parameter error(no cmd)!\n", __func__); - return -EFAULT; + pextra += sprintf(pextra, "Config PPDU Type %s to %s\n", + PPDU_TYPE_STR(pmp_priv->rtw_mp_pmact_ppdu_type), PPDU_TYPE_STR(ppdu_type)); + pmp_priv->rtw_mp_pmact_ppdu_type = ppdu_type; + + rtw_update_giltf(padapter); + rtw_mp_update_coding(padapter); + + if (ppdu_type >= RTW_MP_TYPE_HE_MU_OFDMA) { + u8 ru_num = 0 , rualloc_num = 0 ,i = 0; + + ru_num = rtw_mp_update_ru_tone(padapter); + rualloc_num = rtw_mp_update_ru_alloc(padapter); + pextra += sprintf(pextra, "\nCurrent [%s] RU Alloc index:%d\n", + RU_TONE_STR(pmp_priv->rtw_mp_ru_tone), + pmp_priv->mp_plcp_user[user_idx].ru_alloc); + + pextra += sprintf(pextra, "RU Alloc list:["); + for (i = 0;i <= rualloc_num - 1; i++) + pextra += sprintf(pextra, "%d ", pmp_priv->ru_alloc_list[i]); + pextra += sprintf(pextra, "]\n"); + + pextra += sprintf(pextra, "\nRU Tone support list(Refer Coding:%s):\n", + (pmp_priv->mp_plcp_user[user_idx].coding ? "LDPC":"BCC")); + for (i = 0;i <= ru_num; i++) + pextra += sprintf(pextra, "%d : [%s]\n", + pmp_priv->ru_tone_sel_list[i], + RU_TONE_STR(pmp_priv->ru_tone_sel_list[i])); + pextra += sprintf(pextra, "\n\nCodingCMD:[mp_plcp_user coding=%%d] (0:BCC 1:LDPC )"); + pextra += sprintf(pextra, "\nRU Tone CMD:[ mp_plcp_user ru_tone=%%d ]"); + pextra += sprintf(pextra, "\nRU Alloc CMD:[ mp_plcp_user ru_alloc=%%d ]"); + } + } else { + u8 *pstr = extra; + _rtw_memset(pstr, 0, wrqu->data.length); + pstr += sprintf(pstr, "CMD: [mp_plcp_datappdu=%%d]\nPLCP (PPDU Type):\n\ +0:CCK\n1:LEGACY\n2:HT_MF\n3:HT_GF\n4:VHT\n5:HE_SU\n6:HE_ER_SU\n7:HE_MU_OFDMA\n8:HE_TB\n"); + } + }else if ((strncmp(extra, "preamble", 8) == 0)) { + u8 preamble = 0; + + if (sscanf(extra, "preamble=%hhd", &preamble) > 0) { + RTW_INFO("%s: preamble=%d\n", __func__, preamble); + _rtw_memset(extra, 0, wrqu->data.length); + + if (rtw_mp_is_cck_rate(pmp_priv->rateidx)) { + pmp_priv->preamble = preamble; + sprintf(extra, "Config Preamble %d to %d", pmp_priv->preamble, preamble); + } else + sprintf(extra, "Error !!! only B mode Rate for Preamble!\n"); + } else + sprintf(extra, "Error format ! input 'preamble=[num]'\n"); + + } else if ((strncmp(extra, "stbc", 4) == 0)) { + u8 stbc = 0; + + if (sscanf(extra, "stbc=%hhd", &stbc) > 0) { + RTW_INFO("%s: stbc=%d\n", __func__, stbc); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config STBC enable: %d to %d", pmp_priv->rtw_mp_stbc, stbc); + pmp_priv->rtw_mp_stbc = stbc; + if (pmp_priv->rtw_mp_stbc) + pmp_priv->mp_plcp_user[user_idx].dcm = 0; + } else { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "input [stbc=0/1]"); } - do { - pch = strsep(&ptmp, ":"); - if ((pch == NULL) || (strlen(pch) == 0)) - break; - if (strlen(pch) != 2 - || IsHexDigit(*pch) == _FALSE - || IsHexDigit(*(pch + 1)) == _FALSE - || sscanf(pch, "%hhx", &tmp) != 1 - ) { - RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__); - return -EFAULT; + } else if ((strncmp(extra, "giltf", 5) == 0)) { + u8 idx = 0; + u8 giltf_num = rtw_update_giltf(padapter); + + if (sscanf(extra, "giltf=%hhd", &idx) > 0) { + u8 gi = 0, ltf = 0; + + RTW_INFO("%s: gi+ltf=%d\n", __func__, idx); + _rtw_memset(extra, 0, wrqu->data.length); + + if (giltf_num != 0 && idx <= giltf_num) { + gi = pmp_priv->st_giltf[idx].gi; + ltf = pmp_priv->st_giltf[idx].ltf; + sprintf(extra, "Config GI+LTF to %s ", pmp_priv->st_giltf[idx].type_str); + pmp_priv->rtw_mp_plcp_gi = gi; + pmp_priv->rtw_mp_plcp_ltf = ltf; + RTW_INFO("%s: gi=%d ltf=%d\n", __func__, gi, ltf); + } else + sprintf(extra, "Not support GI+LTF index\n"); + + } else { + u8 *pextra = extra; + u8 i = 0; + + if (giltf_num > 0) { + pextra += sprintf(pextra, "GI + LTF list:\n"); + for (i = 0;i <= giltf_num; i++) + pextra += sprintf(pextra, "%d:[%s]\n", i, pmp_priv->st_giltf[i].type_str); } - btmaskfileBuffer[count++] = tmp; + sprintf(pextra, "PPDU Type Not support GI+LTF."); + } - } while (count < 64); + } else if ((strncmp(extra, "tx_time", 7) == 0)) { + u32 tx_time = 0; - _rtw_memset(extra, '\0' , strlen(extra)); + if (sscanf(extra, "tx_time=%d", &tx_time) > 0) { + u32 tmp_tx_time = (tx_time * 10) / 4; - for (i = 0; i < count; i++) - ptmp += sprintf(ptmp, "%02x:", btmaskfileBuffer[i]); + pmp_priv->rtw_mp_plcp_tx_time = tmp_tx_time; + pmp_priv->rtw_mp_plcp_tx_mode = 1; + sprintf(extra, "Config Tx Time:%d us", pmp_priv->rtw_mp_plcp_tx_time); + } - padapter->registrypriv.bBTFileMaskEfuse = _TRUE; + } else if ((strncmp(extra, "tx_len", 6) == 0)) { + u32 tx_len = 0; - ptmp += sprintf(ptmp, "\nLoad BT Efuse Mask data %d hex ok\n", count); - wrqu->data.length = strlen(extra); - return 0; - } - rtw_efuse_mask_file_path = extra; - - if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { - RTW_INFO("%s do rtw_is_file_readable = %s! ,sizeof BT maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(btmaskfileBuffer)); - Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, btmaskfileBuffer, sizeof(btmaskfileBuffer)); - _rtw_memset(extra, '\0' , strlen(extra)); - if (Status == _TRUE) { - padapter->registrypriv.bBTFileMaskEfuse = _TRUE; - ptmp += sprintf(ptmp, "BT efuse mask file read OK\n"); + if (sscanf(extra, "tx_len=%d", &tx_len) > 0) { + pmp_priv->mp_plcp_user[user_idx].plcp_txlen = tx_len; + pmp_priv->rtw_mp_plcp_tx_mode = 0; + sprintf(extra, "Config Tx Len:%d", pmp_priv->mp_plcp_user[user_idx].plcp_txlen); + } + + } else if ((strncmp(extra, "he_sigb", 7) == 0)) { + u32 he_sigb = 0; + + if (sscanf(extra, "he_sigb=%d", &he_sigb) > 0) { + if (he_sigb <= 5) { + pmp_priv->rtw_mp_he_sigb = he_sigb; + sprintf(extra, "Config HE SIGB:%d", he_sigb); + } else + sprintf(extra, "Error Config HE SIGB:[%d] (0~5)", he_sigb); + } else { + u8 *pstr = extra; + + _rtw_memset(pstr, 0, wrqu->data.length); + pstr += sprintf(pstr, "invalid CMD Format! input: he_sigb=[Num]\n\ + PLCP (HE SIGB):\n0\n\1\n2\n\3\n\4\n\5\n"); + } + + } else if ((strncmp(extra, "he_sigb_dcm", 7) == 0)) { + u32 he_sigb_dcm = 0; + + if (sscanf(extra, "he_sigb_dcm=%d", &he_sigb_dcm) > 0) { + if (he_sigb_dcm <= 1) { + pmp_priv->rtw_mp_he_sigb_dcm = he_sigb_dcm; + sprintf(extra, "Config HE SIGB DCM:%d", he_sigb_dcm); + } else + sprintf(extra, "Error Config HE SIGB:[%d] (0:Disable 1:Enable)", he_sigb_dcm); + + } else { + u8 *pstr = extra; + + _rtw_memset(pstr, 0, wrqu->data.length); + pstr += sprintf(pstr, "invalid CMD Format! input: he_sigb_dcm=[Num]\n\ + PLCP (HE SIGB DCM):\n0:Disable\n1:Enable"); + } + + } else if ((strncmp(extra, "er_su_ru106en", 7) == 0)) { + u32 ru106en = 0; + + if (sscanf(extra, "er_su_ru106en=%d", &ru106en) > 0) { + if (ru106en <= 1) { + pmp_priv->rtw_mp_he_er_su_ru_106_en = ru106en; + sprintf(extra, "Config he_er_su_ru106:%d", ru106en); + } else + sprintf(extra, "Error!!! Config HE ER SU RU106 Enable:[%d] (0:Disable 1:Enable)", + ru106en); + } else { + u8 *pstr = extra; + + _rtw_memset(pstr, 0, wrqu->data.length); + pstr += sprintf(pstr, "Error!!! Config HE ER SU RU106 Enable: Input number[ 0:Disable 1:Enable ]"); + } + + } else if ((strncmp(extra, "ru_tone", 7) == 0)) { + u32 ru_tone = 0; + + if (sscanf(extra, "ru_tone=%d", &ru_tone) > 0) { + RTW_INFO("%s: RU Tone=%d\n", __func__, ru_tone); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config RU tone %d to %d", pmp_priv->rtw_mp_ru_tone, ru_tone); + pmp_priv->rtw_mp_ru_tone = ru_tone; } else { - padapter->registrypriv.bBTFileMaskEfuse = _FALSE; - ptmp += sprintf(ptmp, "read BT efuse mask file FAIL\n"); - RTW_INFO("%s rtw_efuse_file_read BT mask fail!\n", __func__); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error!!!\tinput , [ru_tone= number]"); } + } else { - padapter->registrypriv.bBTFileMaskEfuse = _FALSE; - ptmp += sprintf(ptmp, "BT efuse mask file readable FAIL\n"); - RTW_INFO("%s rtw_is_file_readable BT Mask file fail!\n", __func__); - } + char *pstr = extra; + u8 ppdu_idx = pmp_priv->rtw_mp_pmact_ppdu_type; + + if (ppdu_idx < RTW_MP_TYPE_HT_MF) { + pstr += sprintf(pstr, "invalid PPDU Type ! input :ppdu=[Num] over the HT\n"); + } else { + u8 i = 0; + u8 num = rtw_update_giltf(padapter); + + _rtw_memset(extra, 0, wrqu->data.length); + pstr += sprintf(pstr, "invalid CMD Format !! please input: giltf=[Num]\n"); + pstr += sprintf(pstr, "PPDU %s GI+LTF:\n", PPDU_TYPE_STR(ppdu_idx)); + for (i = 0; i <= num; i++) + pstr += sprintf(pstr, "[%d]: %s\n" ,i , pmp_priv->st_giltf[i].type_str); + } + } wrqu->data.length = strlen(extra); return 0; } - -int rtw_efuse_mask_file(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +int rtw_mp_tx_plcp_tx_user(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - char *rtw_efuse_mask_file_path; - u8 Status; - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *mpprv = (struct mp_priv *)&padapter->mppriv; - _rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer)); + u32 tx_mcs = 0; + u8 user_idx = mpprv->mp_plcp_useridx; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; - *(extra + wrqu->data.length) = '\0'; - if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { - padapter->registrypriv.boffefusemask = 1; - sprintf(extra, "Turn off Efuse Mask\n"); - wrqu->data.length = strlen(extra); - return 0; - } - if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { - padapter->registrypriv.boffefusemask = 0; - sprintf(extra, "Turn on Efuse Mask\n"); - wrqu->data.length = strlen(extra); - return 0; - } - if (strncmp(extra, "data,", 5) == 0) { - u8 *pch; - char *ptmp, tmp; - u8 count = 0; - u8 i = 0; + if (sscanf(extra, "mcs=%d", &tx_mcs) > 0) { + RTW_INFO("%s: mcs=%d\n", __func__, tx_mcs); + mpprv->mp_plcp_user[user_idx].plcp_mcs = tx_mcs; + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config PLCP MCS idx %d to %d", + mpprv->mp_plcp_user[user_idx].plcp_mcs, tx_mcs); - ptmp = extra; - pch = strsep(&ptmp, ","); + } else if ((strncmp(extra, "dcm", 3) == 0)) { + u8 dcm = 0; - if ((pch == NULL) || (strlen(pch) == 0)) { - RTW_INFO("%s: parameter error(no cmd)!\n", __func__); - return -EFAULT; + if (sscanf(extra, "dcm=%hhd", &dcm) > 0) { + RTW_INFO("%s: dcm=%d\n", __func__, dcm); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config DCM enable: %d to %d", mpprv->mp_plcp_user[user_idx].dcm, dcm); + mpprv->mp_plcp_user[user_idx].dcm = dcm; + + if (mpprv->mp_plcp_user[user_idx].dcm) + mpprv->rtw_mp_stbc = 0; + } else { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error !!! input [dcm=0/1]"); } - do { - pch = strsep(&ptmp, ":"); - if ((pch == NULL) || (strlen(pch) == 0)) - break; - if (strlen(pch) != 2 - || IsHexDigit(*pch) == _FALSE - || IsHexDigit(*(pch + 1)) == _FALSE - || sscanf(pch, "%hhx", &tmp) != 1 - ) { - RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__); - return -EFAULT; - } - maskfileBuffer[count++] = tmp; + } else if ((strncmp(extra, "coding", 6) == 0)) { + u8 coding = 0; - } while (count < 64); + if (sscanf(extra, "coding=%hhd", &coding) > 0) { - _rtw_memset(extra, '\0' , strlen(extra)); + RTW_INFO("%s: coding=%d\n", __func__, coding); + _rtw_memset(extra, 0, wrqu->data.length); + mpprv->mp_plcp_user[user_idx].coding = coding; + rtw_mp_update_coding(padapter); + sprintf(extra, "Config coding to %s", + (mpprv->mp_plcp_user[user_idx].coding?"LDPC":"BCC")); + } else { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error !!!\n0:BCC 1:LDPC \t input Number [coding=0/1]"); + } - for (i = 0; i < count; i++) - ptmp += sprintf(ptmp, "%02x:", maskfileBuffer[i]); + } else if ((strncmp(extra, "ru_alloc", 8) == 0)) { + u32 ru_alloc = 0; - padapter->registrypriv.bFileMaskEfuse = _TRUE; + if (sscanf(extra, "ru_alloc=%d", &ru_alloc) > 0) { - sprintf(ptmp, "\nLoad Efuse Mask data %d hex ok\n", count); - wrqu->data.length = strlen(extra); - return 0; - } - rtw_efuse_mask_file_path = extra; - - if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { - RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer)); - Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer)); - if (Status == _TRUE) { - padapter->registrypriv.bFileMaskEfuse = _TRUE; - sprintf(extra, "efuse mask file read OK\n"); + RTW_INFO("%s: RU alloc=%d\n", __func__, ru_alloc); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Config RU alloc %d to %d", + mpprv->mp_plcp_user[user_idx].ru_alloc, ru_alloc); + mpprv->mp_plcp_user[user_idx].ru_alloc = ru_alloc; + } else { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error!!!\tinput , [ru_alloc= number]"); + } + + } else if ((strncmp(extra, "txuser", 6) == 0)) { + u32 txuser = 0; + + if (sscanf(extra, "txuser=%d", &txuser) > 0) { + RTW_INFO("%s: Sel User idx=%d\n", __func__, txuser); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "config Tx User %d to %d", mpprv->rtw_mp_plcp_tx_user, txuser); + mpprv->rtw_mp_plcp_tx_user = txuser; + } else { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error!!!\tinput , [txuser= number]"); + } + + } else if ((strncmp(extra, "user", 4) == 0)) { + u32 user_idx = 0; + + if (sscanf(extra, "user=%d", &user_idx) > 0) { + RTW_INFO("%s: Sel User idx=%d\n", __func__, user_idx); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "select User idx %d to %d", mpprv->mp_plcp_useridx, user_idx); + mpprv->mp_plcp_useridx = user_idx; } else { - padapter->registrypriv.bFileMaskEfuse = _FALSE; - sprintf(extra, "read efuse mask file FAIL\n"); - RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Error!!!\tinput , [user= number]"); } + + } else if ((strncmp(extra, "tx_len", 6) == 0)) { + u32 tx_len = 0; + + if (sscanf(extra, "tx_len=%d", &tx_len) > 0) { + mpprv->mp_plcp_user[user_idx].plcp_txlen = tx_len; + mpprv->rtw_mp_plcp_tx_mode = 0; + sprintf(extra, "Config Tx Len:%d", mpprv->mp_plcp_user[user_idx].plcp_txlen); + } + } else { - padapter->registrypriv.bFileMaskEfuse = _FALSE; - sprintf(extra, "efuse mask file readable FAIL\n"); - RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + u8 *pstr = extra; + _rtw_memset(pstr, 0, wrqu->data.length); + + pstr += sprintf(pstr, "invalid CMD Format!\n \ + \t input :\n\ + \t user=%%d\n\ + \t mcs=%%d\n\ + \t dcm=%%d,\n\ + \t coding=%%d\n\ + \t ru_alloc=%%d\n"); } wrqu->data.length = strlen(extra); return 0; } +int rtw_mp_tx_method(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; -int rtw_efuse_file_map(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + if ((strncmp(extra, "PMACT", 5) == 0)) { + pmp_priv->rtw_mp_tx_method = RTW_MP_PMACT_TX; + sprintf(extra, "set PMACT OK"); + } else if ((strncmp(extra, "TMACT", 5) == 0)) { + pmp_priv->rtw_mp_tx_method = RTW_MP_TMACT_TX; + rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_MODE_SWITCH, pmp_priv->rtw_mp_tx_method, _FALSE); + sprintf(extra, "set TMACT OK"); + } else if ((strncmp(extra, "FWPMACT", 7) == 0)) { + pmp_priv->rtw_mp_tx_method = RTW_MP_FW_PMACT_TX; + rtw_phl_mp_tx_cmd(padapter, RTW_MP_TX_MODE_SWITCH, pmp_priv->rtw_mp_tx_method, _FALSE); + sprintf(extra, "set FWPMACT OK"); + } + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_config_phy(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - char *rtw_efuse_file_map_path; - u8 Status; - PEFUSE_HAL pEfuseHal; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mp_priv *pmp_priv = &padapter->mppriv; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 set_phy = 0; - pEfuseHal = &pHalData->EfuseHal; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; - rtw_efuse_file_map_path = extra; + extra[wrqu->data.length] = '\0'; + set_phy = rtw_atoi(extra); - _rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN); + if (set_phy < 2) { + sprintf(extra, "set current phy %d to %d", pmp_priv->rtw_mp_cur_phy, set_phy); + pmp_priv->rtw_mp_cur_phy = set_phy; + rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SET_PHY_INDEX); + } else + sprintf(extra, "Not suuport phy %d", set_phy); - if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { - RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); - Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap)); - if (Status == _TRUE) { - pmp_priv->bloadefusemap = _TRUE; - sprintf(extra, "efuse file file_read OK\n"); - } else { - pmp_priv->bloadefusemap = _FALSE; - sprintf(extra, "efuse file file_read FAIL\n"); - } - } else { - sprintf(extra, "efuse file readable FAIL\n"); - RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); - } wrqu->data.length = strlen(extra); return 0; } - -int rtw_efuse_file_map_store(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +int rtw_mp_phl_rfk(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - char *rtw_efuse_file_map_path; - u8 Status; - u16 mapLen; - PEFUSE_HAL pEfuseHal; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mp_priv *pmp_priv = &padapter->mppriv; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 k_type = RTW_MP_CAL_MAX; + u8 k_cap_ctrl = false; + u8 k_cap_on = false; - pEfuseHal = &pHalData->EfuseHal; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; - rtw_efuse_file_map_path = extra; - RTW_INFO("%s rtw_is_file_readable! %s\n", __func__, rtw_efuse_file_map_path); + if (strncmp(extra, "iqk", 3) == 0) { + k_type = RTW_MP_CAL_IQK; - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE); + if (strncmp(extra, "iqk on", 6) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set iqk on"); - if (mapLen != 0) { - RTW_INFO("%s, efuse store path = %s! mapLen = %d\n", __func__, rtw_efuse_file_map_path, mapLen); - Status = rtw_efuse_file_store(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, mapLen); - if (Status) { - sprintf(extra, "efuse file restore OK\n"); - } else { - sprintf(extra, "efuse file restore FAIL\n"); + } else if ((strncmp(extra, "iqk off", 7) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set iqk off"); + } else + sprintf(extra, "set iqk trigger"); + + } else if (strncmp(extra, "dpk", 3) == 0) { + k_type = RTW_MP_CAL_DPK; + if (strncmp(extra, "dpk on", 6) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set dpk on"); + } else if ((strncmp(extra, "dpk off", 7) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set dpk off"); + } else + sprintf(extra, "set dpk trigger"); + + } else if (strncmp(extra, "chk", 3) == 0) { + k_type = RTW_MP_CAL_CHL_RFK; + if (strncmp(extra, "chk on", 6) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set chk on"); + } else if ((strncmp(extra, "chk off", 7) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set chk off"); + } else + sprintf(extra, "set chk trigger"); + + } else if (strncmp(extra, "dack", 3) == 0) { + k_type = RTW_MP_CAL_DACK; + if (strncmp(extra, "dack on", 6) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set dack on"); + } else if ((strncmp(extra, "dack off", 7) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set dack off"); + } else + sprintf(extra, "set dack trigger"); + + } else if (strncmp(extra, "lck", 3) == 0) { + k_type = RTW_MP_CAL_LCK; + if (strncmp(extra, "lck on", 6) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set lck on"); + } else if ((strncmp(extra, "lck off", 7) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set lck off"); + } else + sprintf(extra, "set lck trigger"); + + } else if (strncmp(extra, "dpk_trk", 7) == 0) { + k_type = RTW_MP_CAL_DPK_TRACK; + if (strncmp(extra, "dpk_trk on", 10) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set dpk_trk on"); + } else if ((strncmp(extra, "dpk_trk off", 11) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set dpk_trk off"); } - } else { - sprintf(extra, "efuse file readable FAIL\n"); - RTW_INFO("%s rtw_is_file_readable fail! map Len %d\n", __func__, mapLen); - } + + } else if (strncmp(extra, "tssi", 4) == 0) { + k_type = RTW_MP_CAL_TSSI; + if (strncmp(extra, "tssi on", 7) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set tssi on"); + } else if ((strncmp(extra, "tssi off", 8) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set tssi off"); + } else + sprintf(extra, "set tssi trigger"); + + } else if (strncmp(extra, "gapk", 4) == 0) { + k_type = RTW_MP_CAL_GAPK; + if (strncmp(extra, "gapk on", 7) == 0) { + k_cap_ctrl = true; + k_cap_on = true; + sprintf(extra, "set gapk on"); + } else if ((strncmp(extra, "gapk off", 8) == 0)) { + k_cap_ctrl = true; + k_cap_on = false; + sprintf(extra, "set gapk off"); + } else + sprintf(extra, "set gapk trigger"); + + } else + sprintf(extra, "Error! CMD Format:\n\ + [trigger K] or Set K on/off\n\ + chk\\chk on/off\n\ + dack\\dack on/off\n\ + iqk\\iqk on/off\n\ + lck\\lck on/off\n\ + dpk\\dpk on/off\n\ + dpk_trk on/off\n\ + tssi\\tssi on/off\n\ + gapk\\gapk on/off\n"); + + if (k_cap_ctrl) { + rtw_mp_cal_capab(padapter, k_type, k_cap_on); + } else if (k_type < RTW_MP_CAL_MAX) + rtw_mp_cal_trigger(padapter, k_type); wrqu->data.length = strlen(extra); return 0; } -int rtw_bt_efuse_file_map(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) +int rtw_mp_phl_btc_path(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { - char *rtw_efuse_file_map_path; - u8 Status; - PEFUSE_HAL pEfuseHal; - PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mp_priv *pmp_priv = &padapter->mppriv; + _adapter *padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = (struct mp_priv *)&padapter->mppriv; + u8 btc_mode = 0; - pEfuseHal = &pHalData->EfuseHal; - if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) - return -EFAULT; + if (strncmp(extra, "normal", 6) == 0) { - rtw_efuse_file_map_path = extra; + btc_mode = BTC_MODE_NORMAL; + RTW_INFO("set BTC Path Normal"); + } else if (strncmp(extra, "wl", 2) == 0 || strncmp(extra, "WL", 2) == 0) { - _rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + btc_mode = BTC_MODE_WL; + RTW_INFO("set BTC Path WL"); + } else if (strncmp(extra, "bt", 2) == 0 || strncmp(extra, "BT", 2) == 0) { - if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { - RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); - Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap)); - if (Status == _TRUE) { - pmp_priv->bloadBTefusemap = _TRUE; - sprintf(extra, "BT efuse file file_read OK\n"); - } else { - pmp_priv->bloadBTefusemap = _FALSE; - sprintf(extra, "BT efuse file file_read FAIL\n"); - } + btc_mode = BTC_MODE_BT; + RTW_INFO("set BTC Path BT"); } else { - sprintf(extra, "BT efuse file readable FAIL\n"); - RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + btc_mode = BTC_MODE_WL; + RTW_INFO("Default set BTC Path WL"); } + + pmp_priv->btc_path = btc_mode; + if (rtw_mp_phl_config_arg(padapter, RTW_MP_CONFIG_CMD_SWITCH_BT_PATH)) { + sprintf(extra, "set BTC Path %s", + (btc_mode == 0)? "Normal":((btc_mode == 1)? "WL": + ((btc_mode == 2)? "BT":"DEFAULT WL"))); + + } else + sprintf(extra, "set BTC Path Fail"); wrqu->data.length = strlen(extra); return 0; } +int rtw_mp_get_he(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct registry_priv *regsty = &padapter->registrypriv; +#ifdef CONFIG_80211AX_HE + if (!REGSTY_IS_11AX_ENABLE(regsty) || + !is_supported_he(regsty->wireless_mode)) + sprintf(extra, "false"); + else + sprintf(extra, "true"); +#endif + wrqu->data.length = strlen(extra); + return 0; +} static inline void dump_buf(u8 *buf, u32 len) { @@ -3001,11 +3370,11 @@ int rtw_mp_link(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - PADAPTER padapter = rtw_netdev_priv(dev); + _adapter *padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv; - char input[RTW_IWD_MAX_LEN]; + char input[RTW_IWD_MAX_LEN]; int bgetrxdata = 0, btxdata = 0, bsetbt = 0; - u8 err = 0; + int err = 0; u32 i = 0, datalen = 0,jj, kk, waittime = 0; u16 val = 0x00, ret = 0; char *pextra = NULL; @@ -3014,9 +3383,6 @@ int rtw_mp_link(struct net_device *dev, pmp_priv = &padapter->mppriv; - if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length)) - return -EFAULT; - if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; @@ -3031,7 +3397,7 @@ int rtw_mp_link(struct net_device *dev, if (bgetrxdata) { RTW_INFO("%s: in= 1 \n", __func__); if (pmp_priv->mplink_brx == _TRUE) { - pch = extra; + while (waittime < 100 && pmp_priv->mplink_brx == _FALSE) { if (pmp_priv->mplink_brx == _FALSE) rtw_msleep_os(10); @@ -3040,10 +3406,10 @@ int rtw_mp_link(struct net_device *dev, waittime++; } if (pmp_priv->mplink_brx == _TRUE) { - pch += sprintf(pch, "\n"); - + sprintf(extra, "\n"); + pextra = extra + strlen(extra); for (i = 0; i < pmp_priv->mplink_rx_len; i ++) { - pch += sprintf(pch, "%02x:", pmp_priv->mplink_buf[i]); + pextra += sprintf(pextra, "%02x:", pmp_priv->mplink_buf[i]); } _rtw_memset(pmp_priv->mplink_buf, '\0' , sizeof(pmp_priv->mplink_buf)); pmp_priv->mplink_brx = _FALSE; @@ -3102,12 +3468,13 @@ int rtw_mp_link(struct net_device *dev, pmp_priv->tx.count = 1; pmp_priv->tx.stop = 0; pmp_priv->mplink_btx = _TRUE; - SetPacketTx(padapter); + rtw_mp_set_packet_tx(padapter); pmp_priv->mode = MP_PACKET_TX; } else if (bsetbt) { -#ifdef CONFIG_BT_COEXIST +#if 0 +#ifdef CONFIG_BTC pch = input; i = 0; @@ -3162,17 +3529,17 @@ int rtw_mp_link(struct net_device *dev, if (tmp[2] != NULL) { _rtw_memset(extra, 0, wrqu->length); - pch = extra; ret = rtw_btcoex_btset_testmode(padapter, val); if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) { RTW_INFO("%s: BT_OP fail = 0x%x!\n", __FUNCTION__, val); - pch += sprintf(pch, "BT_OP fail 0x%x!\n", val); + sprintf(extra, "BT_OP fail 0x%x!\n", val); } else - pch += sprintf(pch, "Set BT_OP 0x%x done!\n", val); + sprintf(extra, "Set BT_OP 0x%x done!\n", val); } } -#endif /* CONFIG_BT_COEXIST */ +#endif /* CONFIG_BTC */ +#endif } exit: @@ -3184,347 +3551,317 @@ int rtw_mp_link(struct net_device *dev, } -#if defined(CONFIG_RTL8723B) -int rtw_mp_SetBT(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_ops *pHalFunc = &padapter->hal_func; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - BT_REQ_CMD BtReq; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - PBT_RSP_CMD pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0]; - char input[128]; - char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; - u8 setdata[100]; - u8 resetbt = 0x00; - u8 tempval, BTStatus; - u8 H2cSetbtmac[6]; - u8 u1H2CBtMpOperParm[4] = {0x01}; - int testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1; - u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0; - PRT_MP_FIRMWARE pBTFirmware = NULL; - if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) - return -EFAULT; - - *(extra + wrqu->data.length) = '\0'; - pch = extra; +int rtw_priv_mp_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ - if (strlen(extra) < 1) - return -EFAULT; + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int status = 0; + u8 i = 0; + char *pch = extra; - RTW_INFO("%s:iwpriv in=%s\n", __func__, extra); - ready = strncmp(extra, "ready", 5); - testmode = strncmp(extra, "testmode", 8); /* strncmp TRUE is 0*/ - trxparam = strncmp(extra, "trxparam", 8); - setgen = strncmp(extra, "setgen", 6); - getgen = strncmp(extra, "getgen", 6); - testctrl = strncmp(extra, "testctrl", 8); - testbt = strncmp(extra, "testbt", 6); - readtherm = strncmp(extra, "readtherm", 9); - setbtmac = strncmp(extra, "setbtmac", 8); - - if (strncmp(extra, "dlbt", 4) == 0) { - pHalData->LastHMEBoxNum = 0; - pHalData->bBTFWReady = _FALSE; - rtw_write8(padapter, 0xa3, 0x05); - BTStatus = rtw_read8(padapter, 0xa0); - RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); - if (BTStatus != 0x04) { - pch += sprintf(pch, "BT Status not Active DLFW FAIL\n"); - goto exit; - } - - tempval = rtw_read8(padapter, 0x6B); - tempval |= BIT7; - rtw_write8(padapter, 0x6B, tempval); - - /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/ - /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/ - rtw_usleep_os(100); - /* disable BT power cut*/ - /* 0x6A[14] = 0*/ - tempval = rtw_read8(padapter, 0x6B); - tempval &= ~BIT6; - rtw_write8(padapter, 0x6B, tempval); - rtw_usleep_os(100); - MPT_PwrCtlDM(padapter, 0); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); - rtw_msleep_os(600); - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); - rtw_msleep_os(1200); - pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE)); - if (pBTFirmware == NULL) - goto exit; - pHalData->bBTFWReady = _FALSE; - FirmwareDownloadBT(padapter, pBTFirmware); - if (pBTFirmware) - rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE)); - - RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n"); - rtw_msleep_os(2000); - _rtw_memset(extra, '\0', wrqu->data.length); - BtReq.opCodeVer = 1; - BtReq.OpCode = 0; - BtReq.paraLength = 0; - mptbt_BtControlProcess(padapter, &BtReq); - rtw_msleep_os(100); - - RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]); - if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) { - - if (padapter->mppriv.bTxBufCkFail == _TRUE) - pch += sprintf(pch, "check TxBuf Fail.\n"); - else - pch += sprintf(pch, "download FW Fail.\n"); - } else { - pch += sprintf(pch, "download FW OK.\n"); - goto exit; - } - goto exit; + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support, iface id = %d,\n", padapter->iface_id); + RTW_INFO("***Please use Primary Adapter:["ADPT_FMT"]***\n", ADPT_ARG(GET_PRIMARY_ADAPTER(padapter))); + pch +=sprintf(pch, "Only primary Adapter support MP CMD\n"); + pch +=sprintf(pch, "Please use Primary Adapter:"ADPT_FMT"", ADPT_ARG(GET_PRIMARY_ADAPTER(padapter))); + wrqu->length = strlen(extra); + return status; } - if (strncmp(extra, "dlfw", 4) == 0) { - pHalData->LastHMEBoxNum = 0; - pHalData->bBTFWReady = _FALSE; - rtw_write8(padapter, 0xa3, 0x05); - BTStatus = rtw_read8(padapter, 0xa0); - RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); - if (BTStatus != 0x04) { - pch += sprintf(pch, "BT Status not Active DLFW FAIL\n"); - goto exit; - } - - tempval = rtw_read8(padapter, 0x6B); - tempval |= BIT7; - rtw_write8(padapter, 0x6B, tempval); - - /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/ - /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/ - rtw_usleep_os(100); - /* disable BT power cut*/ - /* 0x6A[14] = 0*/ - tempval = rtw_read8(padapter, 0x6B); - tempval &= ~BIT6; - rtw_write8(padapter, 0x6B, tempval); - rtw_usleep_os(100); - - MPT_PwrCtlDM(padapter, 0); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); - rtw_msleep_os(600); - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); - rtw_msleep_os(1200); - -#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1) - /* Pull up BT reset pin.*/ - RTW_INFO("%s: pull up BT reset pin when bt start mp test\n", __func__); - rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON); -#endif - RTW_INFO(" FirmwareDownload!\n"); - -#if defined(CONFIG_RTL8723B) - status = rtl8723b_FirmwareDownload(padapter, _FALSE); -#endif - RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n"); - rtw_msleep_os(1000); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_HaltNotify(padapter); - RTW_INFO("SetBT btcoex HaltNotify !\n"); - /*hal_btcoex1ant_SetAntPath(padapter);*/ - rtw_btcoex_SetManualControl(padapter, _TRUE); -#endif - _rtw_memset(extra, '\0', wrqu->data.length); - BtReq.opCodeVer = 1; - BtReq.OpCode = 0; - BtReq.paraLength = 0; - mptbt_BtControlProcess(padapter, &BtReq); - rtw_msleep_os(200); - - RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]); - if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) { - if (padapter->mppriv.bTxBufCkFail == _TRUE) - pch += sprintf(pch, "check TxBuf Fail.\n"); - else - pch += sprintf(pch, "download FW Fail.\n"); - } else { -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SwitchBtTRxMask(padapter); -#endif - rtw_msleep_os(200); - pch += sprintf(pch, "download FW OK.\n"); - goto exit; + for (i = 0; i < dvobj->iface_nums; i++) { + _adapter *iface = dvobj->padapters[i]; + + if (iface == NULL) + continue; + if (rtw_is_adapter_up(iface) == _FALSE) + continue; + if (MLME_IS_AP(iface)) { + RTW_INFO("Adapter:["ADPT_FMT"], Please Leave AP mode or Down Interface\n", ADPT_ARG(iface)); + pch += sprintf(pch, "Check Adapter:"ADPT_FMT",\n\ + Please Leave AP mode or Down Interface\n", ADPT_ARG(iface)); + wrqu->length = strlen(extra); + return status; } - goto exit; - } - - if (strncmp(extra, "down", 4) == 0) { - RTW_INFO("SetBT down for to hal_init !\n"); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SetManualControl(padapter, _FALSE); - rtw_btcoex_Initialize(padapter); -#endif - pHalFunc->read_adapter_info(padapter); - pHalFunc->hal_deinit(padapter); - pHalFunc->hal_init(padapter); - rtw_pm_set_ips(padapter, IPS_NONE); - LeaveAllPowerSaveMode(padapter); - MPT_PwrCtlDM(padapter, 0); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); - rtw_msleep_os(600); - /*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/ - rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); - rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); - rtw_msleep_os(1200); - goto exit; - } - if (strncmp(extra, "disable", 7) == 0) { - RTW_INFO("SetBT disable !\n"); - rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB)); - rtw_msleep_os(500); - goto exit; - } - if (strncmp(extra, "enable", 6) == 0) { - RTW_INFO("SetBT enable !\n"); - rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004)); - rtw_msleep_os(500); - goto exit; - } - if (strncmp(extra, "h2c", 3) == 0) { - RTW_INFO("SetBT h2c !\n"); - pHalData->bBTFWReady = _TRUE; - rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm); - goto exit; - } - if (strncmp(extra, "2ant", 4) == 0) { - RTW_INFO("Set BT 2ant use!\n"); - phy_set_mac_reg(padapter, 0x67, BIT5, 0x1); - rtw_write32(padapter, 0x948, 0000); - - goto exit; } - if (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0) - return -EFAULT; - - if (testbt == 0) { - BtReq.opCodeVer = 1; - BtReq.OpCode = 6; - BtReq.paraLength = cnts / 2; - goto todo; - } - if (ready == 0) { - BtReq.opCodeVer = 1; - BtReq.OpCode = 0; - BtReq.paraLength = 0; - goto todo; - } + RTW_INFO("%s mutx in %d\n", __func__, subcmd); - i = 0; - while ((token = strsep(&pch, ",")) != NULL) { - if (i > 1) - break; - tmp[i] = token; - i++; - } - - if ((tmp[0] != NULL) && (tmp[1] != NULL)) { - cnts = strlen(tmp[1]); - if (cnts < 1) - return -EFAULT; - - RTW_INFO("%s: cnts=%d\n", __func__, cnts); - RTW_INFO("%s: data=%s\n", __func__, tmp[1]); - - for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) { - BtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); - /* RTW_INFO("BtReq.pParamStart[%d]=0x%02x\n", jj, BtReq.pParamStart[jj]);*/ - } - } else - return -EFAULT; - - if (testmode == 0) { - BtReq.opCodeVer = 1; - BtReq.OpCode = 1; - BtReq.paraLength = 1; - } - if (trxparam == 0) { - BtReq.opCodeVer = 1; - BtReq.OpCode = 2; - BtReq.paraLength = cnts / 2; - } - if (setgen == 0) { - RTW_INFO("%s: BT_SET_GENERAL\n", __func__); - BtReq.opCodeVer = 1; - BtReq.OpCode = 3;/*BT_SET_GENERAL 3*/ - BtReq.paraLength = cnts / 2; - } - if (getgen == 0) { - RTW_INFO("%s: BT_GET_GENERAL\n", __func__); - BtReq.opCodeVer = 1; - BtReq.OpCode = 4;/*BT_GET_GENERAL 4*/ - BtReq.paraLength = cnts / 2; - } - if (readtherm == 0) { - RTW_INFO("%s: BT_GET_GENERAL\n", __func__); - BtReq.opCodeVer = 1; - BtReq.OpCode = 4;/*BT_GET_GENERAL 4*/ - BtReq.paraLength = cnts / 2; - } - - if (testctrl == 0) { - RTW_INFO("%s: BT_TEST_CTRL\n", __func__); - BtReq.opCodeVer = 1; - BtReq.OpCode = 5;/*BT_TEST_CTRL 5*/ - BtReq.paraLength = cnts / 2; + switch (subcmd) { + case MP_START: + RTW_INFO("set case mp_start\n"); + status = rtw_mp_start(dev, info, wrqu, extra); + break; + case MP_STOP: + RTW_INFO("set case mp_stop\n"); + status = rtw_mp_stop(dev, info, wrqu, extra); + break; + case MP_BANDWIDTH: + RTW_INFO("set case mp_bandwidth\n"); + status = rtw_mp_bandwidth(dev, info, wrqu, extra); + break; + case MP_RESET_STATS: + RTW_INFO("set case MP_RESET_STATS\n"); + status = rtw_mp_reset_stats(dev, info, wrqu, extra); + break; + case MP_SetRFPathSwh: + RTW_INFO("set MP_SetRFPathSwitch\n"); + status = rtw_mp_SetRFPath(dev, info, wrqu, extra); + break; + case WRITE_REG: + status = rtw_mp_write_reg(dev, info, wrqu, extra); + break; + case WRITE_RF: + status = rtw_mp_write_rf(dev, info, wrqu, extra); + break; + case MP_PHYPARA: + RTW_INFO("mp_get MP_PHYPARA\n"); + status = rtw_mp_phypara(dev, info, wrqu, extra); + break; + case MP_CHANNEL: + RTW_INFO("set case mp_channel\n"); + status = rtw_mp_channel(dev , info, wrqu, extra); + break; + case MP_TRXSC_OFFSET: + RTW_INFO("set case rtw_mp_trxsc_offset\n"); + status = rtw_mp_trxsc_offset(dev , info, wrqu, extra); + break; + case READ_REG: + RTW_INFO("mp_get READ_REG\n"); + status = rtw_mp_read_reg(dev, info, wrqu, extra); + break; + case READ_RF: + RTW_INFO("mp_get READ_RF\n"); + status = rtw_mp_read_rf(dev, info, wrqu, extra); + break; + case MP_RATE: + RTW_INFO("set case mp_rate\n"); + status = rtw_mp_rate(dev, info, wrqu, extra); + break; + case MP_TXPOWER: + RTW_INFO("set case MP_TXPOWER\n"); + status = rtw_mp_txpower(dev, info, wrqu, extra); + break; + case MP_ANT_TX: + RTW_INFO("set case MP_ANT_TX\n"); + status = rtw_mp_ant_tx(dev, info, wrqu, extra); + break; + case MP_ANT_RX: + RTW_INFO("set case MP_ANT_RX\n"); + status = rtw_mp_ant_rx(dev, info, wrqu, extra); + break; + case MP_QUERY: + status = rtw_mp_trx_query(dev, info, wrqu, extra); + break; + case MP_CTX: + RTW_INFO("set case MP_CTX\n"); + status = rtw_mp_ctx(dev, info, wrqu, extra); + break; + case MP_ARX: + RTW_INFO("set case MP_ARX\n"); + status = rtw_mp_arx(dev, info, wrqu, extra); + break; + case MP_DUMP: + RTW_INFO("set case MP_DUMP\n"); + status = rtw_mp_dump(dev, info, wrqu, extra); + break; + case MP_PSD: + RTW_INFO("set case MP_PSD\n"); + status = rtw_mp_psd(dev, info, wrqu, extra); + break; + case MP_THER: + RTW_INFO("set case MP_THER\n"); + status = rtw_mp_thermal(dev, info, wrqu, extra); + break; + case MP_PwrCtlDM: + RTW_INFO("set MP_PwrCtlDM\n"); + status = rtw_mp_PwrCtlDM(dev, info, wrqu, extra); + break; + case MP_QueryDrvStats: + RTW_INFO("mp_get MP_QueryDrvStats\n"); + status = rtw_mp_QueryDrv(dev, info, wdata, extra); + break; + case MP_PWRTRK: + RTW_INFO("set case MP_PWRTRK\n"); + status = rtw_mp_pwrtrk(dev, info, wrqu, extra); + break; + case MP_SET_TSSIDE: + RTW_INFO("set case MP_TSSI_DE\n"); + status = rtw_mp_set_tsside(dev, info, wrqu, extra); + break; + case EFUSE_SET: + RTW_INFO("set case efuse set\n"); + status = rtw_ioctl_efuse_set(dev, info, wdata, extra); + break; + case EFUSE_GET: + RTW_INFO("efuse get EFUSE_GET\n"); + status = rtw_ioctl_efuse_get(dev, info, wdata, extra); + break; + case MP_GET_TXPOWER_INX: + RTW_INFO("mp_get MP_GET_TXPOWER_INX\n"); + status = rtw_mp_txpower_index(dev, info, wrqu, extra); + break; + case MP_GETVER: + RTW_INFO("mp_get MP_GETVER\n"); + status = rtw_mp_getver(dev, info, wdata, extra); + break; + case MP_MON: + RTW_INFO("mp_get MP_MON\n"); + status = rtw_mp_mon(dev, info, wdata, extra); + break; + case EFUSE_BT_MASK: + RTW_INFO("mp_get EFUSE_BT_MASK\n"); + status = rtw_ioctl_efuse_bt_file_mask_load(dev, info, wdata, extra); + break; + case EFUSE_MASK: + RTW_INFO("mp_get EFUSE_MASK\n"); + status = rtw_ioctl_efuse_file_mask_load(dev, info, wdata, extra); + break; + case EFUSE_FILE: + RTW_INFO("mp_get EFUSE_FILE\n"); + status = rtw_ioctl_efuse_file_map_load(dev, info, wdata, extra); + break; + case EFUSE_FILE_STORE: + RTW_INFO("mp_get EFUSE_FILE_STORE\n"); + /*status = rtw_efuse_file_map_store(dev, info, wdata, extra);*/ + break; + case MP_TX: + RTW_INFO("mp_get MP_TX\n"); + status = rtw_mp_tx(dev, info, wdata, extra); + break; + case MP_RX: + RTW_INFO("mp_get MP_RX\n"); + status = rtw_mp_rx(dev, info, wdata, extra); + break; + case MP_HW_TX_MODE: + RTW_INFO("mp_get MP_HW_TX_MODE\n"); + status = rtw_mp_hwtx(dev, info, wdata, extra); + break; + case MP_GET_TSSIDE: + RTW_INFO("mp_get TSSI_DE\n"); + status = rtw_mp_get_tsside(dev, info, wrqu, extra); + break; +#ifdef CONFIG_RTW_CUSTOMER_STR + case MP_CUSTOMER_STR: + RTW_INFO("customer str\n"); + status = rtw_mp_customer_str(dev, info, wdata, extra); + break; +#endif + case MP_PWRLMT: + RTW_INFO("mp_get MP_SETPWRLMT\n"); + status = rtw_mp_pwrlmt(dev, info, wdata, extra); + break; + case BT_EFUSE_FILE: + RTW_INFO("mp_get BT EFUSE_FILE\n"); + status = rtw_ioctl_efuse_bt_file_map_load(dev, info, wdata, extra); + break; + case MP_SWRFPath: + RTW_INFO("mp_get MP_SWRFPath\n"); + status = rtw_mp_switch_rf_path(dev, info, wrqu, extra); + break; + case MP_LINK: + RTW_INFO("mp_get MP_LINK\n"); + status = rtw_mp_link(dev, info, wrqu, extra); + break; + case MP_DPK_TRK: + RTW_INFO("mp_get MP_DPK_TRK\n"); + status = rtw_mp_dpk_track(dev, info, wdata, extra); + break; + case MP_DPK: + RTW_INFO("set MP_DPK\n"); + status = rtw_mp_dpk(dev, info, wdata, extra); + break; + case MP_GET_PHL_TEST: + RTW_INFO("mp_get MP_GET_PHL_TEST\n"); + status = rtw_mp_get_phl_io(dev, info, wrqu, extra); + break; + case MP_SET_PHL_TEST: + RTW_INFO("mp_get MP_SET_PHL_TEST\n"); + status = rtw_mp_set_phl_io(dev, info, wrqu, extra); + break; + case MP_SET_PHL_TX_PATTERN: + RTW_INFO("mp_get MP_SET_PHL_TEST\n"); + status = rtw_mp_tx_pattern_idx(dev, info, wdata, extra); + break; + case MP_SET_PHL_PLCP_TX_DATA: + RTW_INFO("mp_get MP_SET_PHL_PLCP_TX_DATA\n"); + status = rtw_mp_tx_plcp_tx_data(dev, info, wdata, extra); + break; + case MP_SET_PHL_PLCP_TX_USER: + RTW_INFO("mp_get MP_SET_PHL_PLCP_TX_USER\n"); + status = rtw_mp_tx_plcp_tx_user(dev, info, wdata, extra); + break; + case MP_SET_PHL_TX_METHOD: + RTW_INFO("mp_get MP_SET_PHL_TX_METHOD\n"); + status = rtw_mp_tx_method(dev, info, wdata, extra); + break; + case MP_SET_PHL_CONIFG_PHY_NUM: + RTW_INFO("mp_get MP_SET_PHL_CONIFG_PHY_NUM\n"); + status = rtw_mp_config_phy(dev, info, wdata, extra); + break; + case MP_PHL_RFK: + RTW_INFO("mp_get MP_PHL_RFK\n"); + status = rtw_mp_phl_rfk(dev, info, wdata, extra); + break; + case MP_PHL_BTC_PATH: + RTW_INFO("mp_get MP_PHL_BTC_PATH\n"); + status = rtw_mp_phl_btc_path(dev, info, wdata, extra); + break; + case MP_GET_HE: + RTW_INFO("mp_get MP_GET_HE\n"); + status = rtw_mp_get_he(dev, info, wdata, extra); + break; + default: + status = -EIO; } - RTW_INFO("%s: Req opCodeVer=%d OpCode=%d paraLength=%d\n", - __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength); + return status; +} - if (BtReq.paraLength < 1) - goto todo; - for (i = 0; i < BtReq.paraLength; i++) { - RTW_INFO("%s: BtReq.pParamStart[%d] = 0x%02x\n", - __func__, i, BtReq.pParamStart[i]); - } +int rtw_priv_mp_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ -todo: - _rtw_memset(extra, '\0', wrqu->data.length); + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + int status = 0; - if (pHalData->bBTFWReady == _FALSE) { - pch += sprintf(pch, "BTFWReady = FALSE.\n"); - goto exit; +#ifdef CONFIG_CONCURRENT_MODE + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support\n"); + return -EIO; } +#endif - mptbt_BtControlProcess(padapter, &BtReq); - - if (readtherm == 0) { - pch += sprintf(pch, "BT thermal="); - for (i = 4; i < pMptCtx->mptOutLen; i++) { - if ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00)) - goto exit; + RTW_INFO("%s mutx in %d\n", __func__, subcmd); + //_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); + switch (subcmd) { + case MP_DISABLE_BT_COEXIST: + RTW_INFO("set case MP_DISABLE_BT_COEXIST\n"); + status = rtw_mp_disable_bt_coexist(dev, info, wdata, extra); + break; + case MP_IQK: + RTW_INFO("set MP_IQK\n"); + status = rtw_mp_iqk(dev, info, wrqu, extra); + break; + case MP_LCK: + RTW_INFO("set MP_LCK\n"); + status = rtw_mp_lck(dev, info, wrqu, extra); + break; - pch += sprintf(pch, " %d ", (pMptCtx->mptOutBuf[i] & 0x1f)); - } - } else { - for (i = 4; i < pMptCtx->mptOutLen; i++) - pch += sprintf(pch, " 0x%x ", pMptCtx->mptOutBuf[i]); + default: + status = -EIO; } - -exit: - wrqu->data.length = strlen(extra) + 1; - RTW_INFO("-%s: output len=%d data=%s\n", __func__, wrqu->data.length, extra); + //_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL); + RTW_INFO("%s mutx done %d\n", __func__, subcmd); return status; } -#endif /*#ifdef CONFIG_RTL8723B*/ - #endif diff --git a/os_dep/linux/mlme_linux.c b/os_dep/linux/mlme_linux.c index 6fd24e8..2d5802e 100644 --- a/os_dep/linux/mlme_linux.c +++ b/os_dep/linux/mlme_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -101,9 +101,8 @@ void rtw_reset_securitypriv(_adapter *adapter) u8 backupTKIPCountermeasure = 0x00; u32 backupTKIPcountermeasure_time = 0; /* add for CONFIG_IEEE80211W, none 11w also can use */ - _irqL irqL; - _enter_critical_bh(&adapter->security_key_mutex, &irqL); + _rtw_spinlock_bh(&adapter->security_key_mutex); if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */ u8 backup_sw_encrypt, backup_sw_decrypt; @@ -159,7 +158,7 @@ void rtw_reset_securitypriv(_adapter *adapter) psec_priv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE; } /* add for CONFIG_IEEE80211W, none 11w also can use */ - _exit_critical_bh(&adapter->security_key_mutex, &irqL); + _rtw_spinunlock_bh(&adapter->security_key_mutex); RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter)); } @@ -241,16 +240,16 @@ void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->cmn.aid > pstapriv->max_aid) + if (psta->phl_sta->aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) + if (pstapriv->sta_aid[psta->phl_sta->aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->phl_sta->mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_assoc_event\n"); @@ -268,16 +267,16 @@ void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->cmn.aid > pstapriv->max_aid) + if (psta->phl_sta->aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) + if (pstapriv->sta_aid[psta->phl_sta->aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->phl_sta->mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_disassoc_event\n"); @@ -313,8 +312,6 @@ static int mgnt_netdev_open(struct net_device *pnetdev) rtw_netif_carrier_on(pnetdev); - /* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */ - return 0; } static int mgnt_netdev_close(struct net_device *pnetdev) @@ -329,8 +326,6 @@ static int mgnt_netdev_close(struct net_device *pnetdev) rtw_netif_stop_queue(pnetdev); - /* rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); */ - return 0; } diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index 2486c22..25fbeaa 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2019 Realtek Corporation. + * Copyright(c) 2007 - 2021 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,1569 +15,16 @@ #define _OS_INTFS_C_ #include -#include MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); MODULE_AUTHOR("Realtek Semiconductor Corp."); MODULE_VERSION(DRIVERVERSION); +MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver); -/* module param defaults */ -int rtw_chip_version = 0x00; -int rtw_rfintfs = HWPI; -int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */ -#ifdef DBG_LA_MODE -int rtw_la_mode_en=0; -module_param(rtw_la_mode_en, int, 0644); -#endif -int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */ -/* NDIS_802_11_SSID ssid; */ -int rtw_channel = 1;/* ad-hoc support requirement */ -int rtw_wireless_mode = WIRELESS_MODE_MAX; -module_param(rtw_wireless_mode, int, 0644); -int rtw_vrtl_carrier_sense = AUTO_VCS; -int rtw_vcs_type = RTS_CTS; -int rtw_rts_thresh = 2347; -int rtw_frag_thresh = 2346; -int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */ -int rtw_scan_mode = 1;/* active, passive */ -/* int smart_ps = 1; */ -#ifdef CONFIG_POWER_SAVING - /* IPS configuration */ - int rtw_ips_mode = RTW_IPS_MODE; - - /* LPS configuration */ -/* RTW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */ -#if (RTW_LPS_MODE > 0) - int rtw_power_mgnt = PS_MODE_MAX; - - #ifdef CONFIG_USB_HCI - int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/ - #else /*SDIO,PCIE*/ - int rtw_lps_level = (RTW_LPS_MODE - 1); - #endif/*CONFIG_USB_HCI*/ -#else - int rtw_power_mgnt = PS_MODE_ACTIVE; - int rtw_lps_level = LPS_NORMAL; -#endif - - int rtw_lps_chk_by_tp = 1; - - /* WOW LPS configuration */ -#ifdef CONFIG_WOWLAN -/* RTW_WOW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */ -#if (RTW_WOW_LPS_MODE > 0) - int rtw_wow_power_mgnt = PS_MODE_MAX; - int rtw_wow_lps_level = (RTW_WOW_LPS_MODE - 1); -#else - int rtw_wow_power_mgnt = PS_MODE_ACTIVE; - int rtw_wow_lps_level = LPS_NORMAL; -#endif -#endif /* CONFIG_WOWLAN */ - -#else /* !CONFIG_POWER_SAVING */ - int rtw_ips_mode = IPS_NONE; - int rtw_power_mgnt = PS_MODE_ACTIVE; - int rtw_lps_level = LPS_NORMAL; - int rtw_lps_chk_by_tp = 0; -#ifdef CONFIG_WOWLAN - int rtw_wow_power_mgnt = PS_MODE_ACTIVE; - int rtw_wow_lps_level = LPS_NORMAL; -#endif /* CONFIG_WOWLAN */ -#endif /* CONFIG_POWER_SAVING */ - -#ifdef CONFIG_NARROWBAND_SUPPORTING -int rtw_nb_config = CONFIG_NB_VALUE; -module_param(rtw_nb_config, int, 0644); -MODULE_PARM_DESC(rtw_nb_config, "5M/10M/Normal bandwidth configuration"); -#endif - -module_param(rtw_ips_mode, int, 0644); -MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); - -module_param(rtw_lps_level, int, 0644); -MODULE_PARM_DESC(rtw_lps_level, "The default LPS level"); - -#ifdef CONFIG_LPS_1T1R -int rtw_lps_1t1r = RTW_LPS_1T1R; -module_param(rtw_lps_1t1r, int, 0644); -MODULE_PARM_DESC(rtw_lps_1t1r, "The default LPS 1T1R setting"); -#endif - -module_param(rtw_lps_chk_by_tp, int, 0644); - -#ifdef CONFIG_WOWLAN -module_param(rtw_wow_power_mgnt, int, 0644); -MODULE_PARM_DESC(rtw_wow_power_mgnt, "The default WOW LPS mode"); -module_param(rtw_wow_lps_level, int, 0644); -MODULE_PARM_DESC(rtw_wow_lps_level, "The default WOW LPS level"); -#ifdef CONFIG_LPS_1T1R -int rtw_wow_lps_1t1r = RTW_WOW_LPS_1T1R; -module_param(rtw_wow_lps_1t1r, int, 0644); -MODULE_PARM_DESC(rtw_wow_lps_1t1r, "The default WOW LPS 1T1R setting"); -#endif -#endif /* CONFIG_WOWLAN */ - -/* LPS: - * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll - * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll - * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0 -*/ -int rtw_smart_ps = 2; - -int rtw_max_bss_cnt = 0; -module_param(rtw_max_bss_cnt, int, 0644); -#ifdef CONFIG_WMMPS_STA -/* WMMPS: - * rtw_smart_ps = 0 => Only for fw test - * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap - * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap -*/ -int rtw_wmm_smart_ps = 2; -#endif /* CONFIG_WMMPS_STA */ - -int rtw_check_fw_ps = 1; - -#ifdef CONFIG_TX_EARLY_MODE -int rtw_early_mode = 1; -#endif - -int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */ -module_param(rtw_usb_rxagg_mode, int, 0644); - -int rtw_dynamic_agg_enable = 1; -module_param(rtw_dynamic_agg_enable, int, 0644); - -/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4, -* please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -*/ -#ifdef CONFIG_RTW_DEBUG -#ifdef RTW_LOG_LEVEL - uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */ -#else - uint rtw_drv_log_level = _DRV_INFO_; -#endif -module_param(rtw_drv_log_level, uint, 0644); -MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4"); -#endif -int rtw_radio_enable = 1; -int rtw_long_retry_lmt = 7; -int rtw_short_retry_lmt = 7; -int rtw_busy_thresh = 40; -/* int qos_enable = 0; */ /* * */ -int rtw_ack_policy = NORMAL_ACK; - -int rtw_mp_mode = 0; - -#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) -uint rtw_mp_customer_str = 0; -module_param(rtw_mp_customer_str, uint, 0644); -MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode"); -#endif - -int rtw_software_encrypt = 0; -int rtw_software_decrypt = 0; - -int rtw_acm_method = 0;/* 0:By SW 1:By HW. */ - -int rtw_wmm_enable = 1;/* default is set to enable the wmm. */ - -#ifdef CONFIG_WMMPS_STA -/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ -/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */ -int rtw_uapsd_max_sp = NO_LIMIT; -/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ -int rtw_uapsd_ac_enable = 0x0; -#endif /* CONFIG_WMMPS_STA */ - -#if defined(CONFIG_RTL8814A) - int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ -#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) - /*PHYDM API, must enable by default*/ - int rtw_pwrtrim_enable = 1; -#else - int rtw_pwrtrim_enable = 0; /* Default Enalbe power trim by efuse config */ -#endif - -#if CONFIG_TX_AC_LIFETIME -uint rtw_tx_aclt_flags = CONFIG_TX_ACLT_FLAGS; -module_param(rtw_tx_aclt_flags, uint, 0644); -MODULE_PARM_DESC(rtw_tx_aclt_flags, "device TX AC queue packet lifetime control flags"); - -static uint rtw_tx_aclt_conf_default[3] = CONFIG_TX_ACLT_CONF_DEFAULT; -static uint rtw_tx_aclt_conf_default_num = 0; -module_param_array(rtw_tx_aclt_conf_default, uint, &rtw_tx_aclt_conf_default_num, 0644); -MODULE_PARM_DESC(rtw_tx_aclt_conf_default, "device TX AC queue lifetime config for default status"); - -#ifdef CONFIG_AP_MODE -#if CONFIG_RTW_AP_DATA_BMC_TO_UC -static uint rtw_tx_aclt_conf_ap_m2u[3] = CONFIG_TX_ACLT_CONF_AP_M2U; -static uint rtw_tx_aclt_conf_ap_m2u_num = 0; -module_param_array(rtw_tx_aclt_conf_ap_m2u, uint, &rtw_tx_aclt_conf_ap_m2u_num, 0644); -MODULE_PARM_DESC(rtw_tx_aclt_conf_ap_m2u, "device TX AC queue lifetime config for AP mode M2U status"); -#endif -#endif /* CONFIG_AP_MODE */ - -#ifdef CONFIG_RTW_MESH -static uint rtw_tx_aclt_conf_mesh[3] = CONFIG_TX_ACLT_CONF_MESH; -static uint rtw_tx_aclt_conf_mesh_num = 0; -module_param_array(rtw_tx_aclt_conf_mesh, uint, &rtw_tx_aclt_conf_mesh_num, 0644); -MODULE_PARM_DESC(rtw_tx_aclt_conf_mesh, "device TX AC queue lifetime config for MESH status"); -#endif -#endif /* CONFIG_TX_AC_LIFETIME */ - -uint rtw_tx_bw_mode = 0x21; -module_param(rtw_tx_bw_mode, uint, 0644); -MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode"); - -#ifdef CONFIG_FW_HANDLE_TXBCN -uint rtw_tbtt_rpt = 0; /*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/ -module_param(rtw_tbtt_rpt, uint, 0644); -#endif - -#ifdef CONFIG_80211N_HT -int rtw_ht_enable = 1; -/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz -* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 -* 0x21 means enable 2.4G 40MHz & 5G 80MHz */ -#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE -int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE; -#else -int rtw_bw_mode = 0x21; -#endif -int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ -int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ -#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) -int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ -#elif ((defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_SDIO_HCI)) -int rtw_rx_ampdu_amsdu = 1; -#else -int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ -#endif -/* -* 2: Follow the AMSDU filed in ADDBA Resp. (Deault) -* 0: Force the AMSDU filed in ADDBA Resp. to be disabled. -* 1: Force the AMSDU filed in ADDBA Resp. to be enabled. -*/ -int rtw_tx_ampdu_amsdu = 2; - -int rtw_quick_addba_req = 0; - -static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS; -static uint rtw_rx_ampdu_sz_limit_1ss_num = 0; -module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644); -MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation"); - -static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS; -static uint rtw_rx_ampdu_sz_limit_2ss_num = 0; -module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644); -MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation"); - -static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS; -static uint rtw_rx_ampdu_sz_limit_3ss_num = 0; -module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644); -MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation"); - -static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS; -static uint rtw_rx_ampdu_sz_limit_4ss_num = 0; -module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644); -MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation"); - -/* Short GI support Bit Map -* BIT0 - 20MHz, 0: non-support, 1: support -* BIT1 - 40MHz, 0: non-support, 1: support -* BIT2 - 80MHz, 0: non-support, 1: support -* BIT3 - 160MHz, 0: non-support, 1: support */ -int rtw_short_gi = 0xf; -/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ -int rtw_ldpc_cap = 0x33; -/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ -#ifdef CONFIG_RTL8192F -int rtw_stbc_cap = 0x30; -#else -int rtw_stbc_cap = 0x13; -#endif -module_param(rtw_stbc_cap, int, 0644); -/* -* BIT0: Enable VHT SU Beamformer -* BIT1: Enable VHT SU Beamformee -* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer -* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee -* BIT4: Enable HT Beamformer -* BIT5: Enable HT Beamformee -*/ -int rtw_beamform_cap = BIT(1) | BIT(3); -int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/ -int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, others for manual*/ - -#endif /* CONFIG_80211N_HT */ - -#ifdef CONFIG_80211AC_VHT -int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */ -module_param(rtw_vht_enable, int, 0644); - -int rtw_vht_24g_enable = 1; /* 0:disable, 1:enable */ -module_param(rtw_vht_24g_enable, int, 0644); - -int rtw_ampdu_factor = 7; - -uint rtw_vht_rx_mcs_map = 0xaaaa; -module_param(rtw_vht_rx_mcs_map, uint, 0644); -MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); -#endif /* CONFIG_80211AC_VHT */ - - -/* 0: not check in watch dog, 1: check in watch dog */ -int rtw_check_hw_status = 0; - -int rtw_low_power = 0; -int rtw_wifi_spec = 0; - - -int rtw_trx_path_bmp = 0x00; -module_param(rtw_trx_path_bmp, int, 0644); /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */ - -#ifdef CONFIG_SPECIAL_RF_PATH /* configure Nss/xTxR IC to 1ss/1T1R */ -int rtw_tx_path_lmt = 1; -int rtw_rx_path_lmt = 1; -int rtw_tx_nss = 1; -int rtw_rx_nss = 1; -#elif defined(CONFIG_CUSTOMER01_SMART_ANTENNA) -int rtw_tx_path_lmt = 2; -int rtw_rx_path_lmt = 2; -int rtw_tx_nss = 1; -int rtw_rx_nss = 1; -#else -int rtw_tx_path_lmt = 0; -int rtw_rx_path_lmt = 0; -int rtw_tx_nss = 0; -int rtw_rx_nss = 0; -#endif -module_param(rtw_tx_path_lmt, int, 0644); /* limit of TX path number, 0: not specified */ -module_param(rtw_rx_path_lmt, int, 0644); /* limit of RX path number, 0: not specified */ -module_param(rtw_tx_nss, int, 0644); -module_param(rtw_rx_nss, int, 0644); - -#ifdef CONFIG_REGD_SRC_FROM_OS -static uint rtw_regd_src = CONFIG_RTW_REGD_SRC; -module_param(rtw_regd_src, uint, 0644); -MODULE_PARM_DESC(rtw_regd_src, "The default regd source selection, 0:Realtek defined, 1: OS"); -#endif - -char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; -char *rtw_country_code = rtw_country_unspecified; -module_param(rtw_country_code, charp, 0644); -MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); - -int rtw_channel_plan = CONFIG_RTW_CHPLAN; -module_param(rtw_channel_plan, int, 0644); -MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); - -static uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS; -static int rtw_excl_chs_num = 0; -module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644); -MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array"); - -/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list. -But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/ -#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE - int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ -#else - int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ -#endif - -#ifdef CONFIG_BT_COEXIST -int rtw_btcoex_enable = 2; -module_param(rtw_btcoex_enable, int, 0644); -MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse"); - -int rtw_ant_num = 0; -module_param(rtw_ant_num, int, 0644); -MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse"); - -int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */ -int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */ -int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ -#endif /* CONFIG_BT_COEXIST */ - -int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */ - -int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */ -int rtw_antdiv_type = 0 - ; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ - -int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/ - -int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/ - -/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */ -int rtw_switch_usb_mode = 0; - -#ifdef CONFIG_USB_AUTOSUSPEND -int rtw_enusbss = 1;/* 0:disable,1:enable */ -#else -int rtw_enusbss = 0;/* 0:disable,1:enable */ -#endif - -int rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */ - -#ifdef CONFIG_HW_PWRP_DETECTION -int rtw_hwpwrp_detect = 1; -#else -int rtw_hwpwrp_detect = 0; /* HW power ping detect 0:disable , 1:enable */ -#endif - -#ifdef CONFIG_USB_HCI -int rtw_hw_wps_pbc = 1; -#else -int rtw_hw_wps_pbc = 0; -#endif - -#ifdef CONFIG_80211D -int rtw_80211d = 0; -#endif - -#ifdef CONFIG_PCI_ASPM -/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ -int rtw_pci_aspm_enable = 0x5; -#else -int rtw_pci_aspm_enable; -#endif - -/* - * BIT [15:12] mask of ps mode - * BIT [11:8] val of ps mode - * BIT [7:4] mask of perf mode - * BIT [3:0] val of perf mode - * - * L0s:BIT[+0] L1:BIT[+1] - * - * 0x0030: change value only if perf mode - * 0x3300: change value only if ps mode - * 0x3330: change value in both perf and ps mode - */ -#ifdef CONFIG_PCI_DYNAMIC_ASPM -#ifdef CONFIG_PCI_ASPM -int rtw_pci_dynamic_aspm_linkctrl = 0x3330; -#else -int rtw_pci_dynamic_aspm_linkctrl = 0x0030; -#endif -#else -int rtw_pci_dynamic_aspm_linkctrl = 0x0000; -#endif -module_param(rtw_pci_dynamic_aspm_linkctrl, int, 0644); - -#ifdef CONFIG_QOS_OPTIMIZATION -int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */ -#else -int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */ -#endif -module_param(rtw_qos_opt_enable, int, 0644); - -#ifdef CONFIG_RTW_ACS -int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/ -module_param(rtw_acs_auto_scan, int, 0644); - -int rtw_acs = 1; -module_param(rtw_acs, int, 0644); -#endif - -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR -int rtw_nm = 1;/*noise monitor*/ -module_param(rtw_nm, int, 0644); -#endif - -char *ifname = "wlan%d"; -module_param(ifname, charp, 0644); -MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); - -#ifdef CONFIG_PLATFORM_ANDROID - char *if2name = "p2p%d"; -#else /* CONFIG_PLATFORM_ANDROID */ - char *if2name = "wlan%d"; -#endif /* CONFIG_PLATFORM_ANDROID */ -module_param(if2name, charp, 0644); -MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); - -char *rtw_initmac = 0; /* temp mac address if users want to use instead of the mac address in Efuse */ - -#ifdef CONFIG_CONCURRENT_MODE - - #if (CONFIG_IFACE_NUMBER > 2) - int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1; - module_param(rtw_virtual_iface_num, int, 0644); - #else - int rtw_virtual_iface_num = 1; - #endif - -#ifdef CONFIG_P2P - - #ifdef CONFIG_SEL_P2P_IFACE - int rtw_sel_p2p_iface = CONFIG_SEL_P2P_IFACE; - #else - int rtw_sel_p2p_iface = IFACE_ID1; - #endif - - module_param(rtw_sel_p2p_iface, int, 0644); - -#endif - -#endif - -#ifdef CONFIG_AP_MODE -u8 rtw_bmc_tx_rate = MGN_UNKNOWN; - -#if CONFIG_RTW_AP_DATA_BMC_TO_UC -int rtw_ap_src_b2u_flags = CONFIG_RTW_AP_SRC_B2U_FLAGS; -module_param(rtw_ap_src_b2u_flags, int, 0644); - -int rtw_ap_fwd_b2u_flags = CONFIG_RTW_AP_FWD_B2U_FLAGS; -module_param(rtw_ap_fwd_b2u_flags, int, 0644); -#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */ -#endif /* CONFIG_AP_MODE */ - -#ifdef CONFIG_RTW_MESH -#if CONFIG_RTW_MESH_DATA_BMC_TO_UC -int rtw_msrc_b2u_flags = CONFIG_RTW_MSRC_B2U_FLAGS; -module_param(rtw_msrc_b2u_flags, int, 0644); - -int rtw_mfwd_b2u_flags = CONFIG_RTW_MFWD_B2U_FLAGS; -module_param(rtw_mfwd_b2u_flags, int, 0644); -#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ -#endif /* CONFIG_RTW_MESH */ - -#ifdef RTW_WOW_STA_MIX -int rtw_wowlan_sta_mix_mode = 1; -#else -int rtw_wowlan_sta_mix_mode = 0; -#endif -module_param(rtw_wowlan_sta_mix_mode, int, 0644); -module_param(rtw_pwrtrim_enable, int, 0644); -module_param(rtw_initmac, charp, 0644); -module_param(rtw_chip_version, int, 0644); -module_param(rtw_rfintfs, int, 0644); -module_param(rtw_lbkmode, int, 0644); -module_param(rtw_network_mode, int, 0644); -module_param(rtw_channel, int, 0644); -module_param(rtw_mp_mode, int, 0644); -module_param(rtw_wmm_enable, int, 0644); -#ifdef CONFIG_WMMPS_STA -module_param(rtw_uapsd_max_sp, int, 0644); -module_param(rtw_uapsd_ac_enable, int, 0644); -module_param(rtw_wmm_smart_ps, int, 0644); -#endif /* CONFIG_WMMPS_STA */ -module_param(rtw_vrtl_carrier_sense, int, 0644); -module_param(rtw_vcs_type, int, 0644); -module_param(rtw_busy_thresh, int, 0644); - -#ifdef CONFIG_80211N_HT -module_param(rtw_ht_enable, int, 0644); -module_param(rtw_bw_mode, int, 0644); -module_param(rtw_ampdu_enable, int, 0644); -module_param(rtw_rx_stbc, int, 0644); -module_param(rtw_rx_ampdu_amsdu, int, 0644); -module_param(rtw_tx_ampdu_amsdu, int, 0644); -module_param(rtw_quick_addba_req, int, 0644); -#endif /* CONFIG_80211N_HT */ - -#ifdef CONFIG_BEAMFORMING -module_param(rtw_beamform_cap, int, 0644); -#endif - -module_param(rtw_power_mgnt, int, 0644); -module_param(rtw_smart_ps, int, 0644); -module_param(rtw_low_power, int, 0644); -module_param(rtw_wifi_spec, int, 0644); - -module_param(rtw_full_ch_in_p2p_handshake, int, 0644); -module_param(rtw_antdiv_cfg, int, 0644); -module_param(rtw_antdiv_type, int, 0644); - -module_param(rtw_drv_ant_band_switch, int, 0644); -module_param(rtw_single_ant_path, int, 0644); - -module_param(rtw_switch_usb_mode, int, 0644); - -module_param(rtw_enusbss, int, 0644); -module_param(rtw_hwpdn_mode, int, 0644); -module_param(rtw_hwpwrp_detect, int, 0644); - -module_param(rtw_hw_wps_pbc, int, 0644); -module_param(rtw_check_hw_status, int, 0644); - -#ifdef CONFIG_PCI_HCI -module_param(rtw_pci_aspm_enable, int, 0644); -#endif - -#ifdef CONFIG_TX_EARLY_MODE -module_param(rtw_early_mode, int, 0644); -#endif -#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE -char *rtw_adaptor_info_caching_file_path = "/data/misc/wifi/rtw_cache"; -module_param(rtw_adaptor_info_caching_file_path, charp, 0644); -MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file"); -#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */ - -#ifdef CONFIG_LAYER2_ROAMING -uint rtw_max_roaming_times = 2; -module_param(rtw_max_roaming_times, uint, 0644); -MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try"); -#endif /* CONFIG_LAYER2_ROAMING */ - -#ifdef CONFIG_IOL -int rtw_fw_iol = 1; -module_param(rtw_fw_iol, int, 0644); -MODULE_PARM_DESC(rtw_fw_iol, "FW IOL. 0:Disable, 1:enable, 2:by usb speed"); -#endif /* CONFIG_IOL */ - -#ifdef CONFIG_FILE_FWIMG -char *rtw_fw_file_path = "/system/etc/firmware/rtlwifi/FW_NIC.BIN"; -module_param(rtw_fw_file_path, charp, 0644); -MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image"); - -char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN"; -module_param(rtw_fw_wow_file_path, charp, 0644); -MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image"); - -#ifdef CONFIG_MP_INCLUDED -char *rtw_fw_mp_bt_file_path = ""; -module_param(rtw_fw_mp_bt_file_path, charp, 0644); -MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image"); -#endif /* CONFIG_MP_INCLUDED */ -#endif /* CONFIG_FILE_FWIMG */ - -#ifdef CONFIG_80211D -module_param(rtw_80211d, int, 0644); -MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); -#endif - -#ifdef CONFIG_ADVANCE_OTA -/* BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B - BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */ -/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */ -int rtw_advnace_ota; -module_param(rtw_advnace_ota, int, 0644); -#endif - -uint rtw_notch_filter = RTW_NOTCH_FILTER; -module_param(rtw_notch_filter, uint, 0644); -MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); - -uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER; -module_param(rtw_hiq_filter, uint, 0644); -MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all"); - -uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN; -module_param(rtw_adaptivity_en, uint, 0644); -MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable"); - -uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE; -module_param(rtw_adaptivity_mode, uint, 0644); -MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense"); - -int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; -module_param(rtw_adaptivity_th_l2h_ini, int, 0644); -MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity"); - -int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF; -module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644); -MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity"); - -#ifdef CONFIG_DFS_MASTER -uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN; -module_param(rtw_dfs_region_domain, uint, 0644); -MODULE_PARM_DESC(rtw_dfs_region_domain, "0:NONE, 1:FCC, 2:MKK, 3:ETSI"); -#endif - -uint rtw_amsdu_mode = RTW_AMSDU_MODE_NON_SPP; -module_param(rtw_amsdu_mode, uint, 0644); -MODULE_PARM_DESC(rtw_amsdu_mode, "0:non-spp, 1:spp, 2:all drop"); - -uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G; -module_param(rtw_amplifier_type_2g, uint, 0644); -MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA"); - -uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G; -module_param(rtw_amplifier_type_5g, uint, 0644); -MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA"); - -uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE; -module_param(rtw_RFE_type, uint, 0644); -MODULE_PARM_DESC(rtw_RFE_type, "default init value:64"); - -uint rtw_powertracking_type = 64; -module_param(rtw_powertracking_type, uint, 0644); -MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64"); - -uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE; -module_param(rtw_GLNA_type, uint, 0644); -MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0"); - -uint rtw_TxBBSwing_2G = 0xFF; -module_param(rtw_TxBBSwing_2G, uint, 0644); -MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF"); - -uint rtw_TxBBSwing_5G = 0xFF; -module_param(rtw_TxBBSwing_5G, uint, 0644); -MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF"); - -uint rtw_OffEfuseMask = 0; -module_param(rtw_OffEfuseMask, uint, 0644); -MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0"); - -uint rtw_FileMaskEfuse = 0; -module_param(rtw_FileMaskEfuse, uint, 0644); -MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0"); - -uint rtw_rxgain_offset_2g = 0; -module_param(rtw_rxgain_offset_2g, uint, 0644); -MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0"); - -uint rtw_rxgain_offset_5gl = 0; -module_param(rtw_rxgain_offset_5gl, uint, 0644); -MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0"); - -uint rtw_rxgain_offset_5gm = 0; -module_param(rtw_rxgain_offset_5gm, uint, 0644); -MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0"); - -uint rtw_rxgain_offset_5gh = 0; -module_param(rtw_rxgain_offset_5gh, uint, 0644); -MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0"); - -uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; -module_param(rtw_pll_ref_clk_sel, uint, 0644); -MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); - -int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN; -module_param(rtw_tx_pwr_by_rate, int, 0644); -MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); - -#if CONFIG_TXPWR_LIMIT -int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN; -module_param(rtw_tx_pwr_lmt_enable, int, 0644); -MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse"); -#endif - -static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; -static int rtw_target_tx_pwr_2g_a_num = 0; -module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B; -static int rtw_target_tx_pwr_2g_b_num = 0; -module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C; -static int rtw_target_tx_pwr_2g_c_num = 0; -module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D; -static int rtw_target_tx_pwr_2g_d_num = 0; -module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); - -#if CONFIG_IEEE80211_BAND_5GHZ -static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A; -static int rtw_target_tx_pwr_5g_a_num = 0; -module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B; -static int rtw_target_tx_pwr_5g_b_num = 0; -module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C; -static int rtw_target_tx_pwr_5g_c_num = 0; -module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); - -static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D; -static int rtw_target_tx_pwr_5g_d_num = 0; -module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644); -MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); -#endif /* CONFIG_IEEE80211_BAND_5GHZ */ - -int rtw_antenna_gain = CONFIG_RTW_ANTENNA_GAIN; -module_param(rtw_antenna_gain, int, 0644); -MODULE_PARM_DESC(rtw_antenna_gain, "Antenna gain in mBi. 0x7FFF: unspecifed"); - -#ifdef CONFIG_RTW_TX_NPATH_EN -/*0:disable ,1: 2path*/ -int rtw_tx_npath_enable = 1; -module_param(rtw_tx_npath_enable, int, 0644); -MODULE_PARM_DESC(rtw_tx_npath_enable, "0:Disable, 1:TX-2PATH"); -#endif - -#ifdef CONFIG_RTW_PATH_DIV -/*0:disable ,1: path diversity*/ -int rtw_path_div_enable = 1; -module_param(rtw_path_div_enable, int, 0644); -MODULE_PARM_DESC(rtw_path_div_enable, "0:Disable, 1:Enable path diversity"); -#endif - - -int rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR; -module_param(rtw_tsf_update_pause_factor, int, 0644); -MODULE_PARM_DESC(rtw_tsf_update_pause_factor, "num of bcn intervals to stay TSF update pause status"); - -int rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR; -module_param(rtw_tsf_update_restore_factor, int, 0644); -MODULE_PARM_DESC(rtw_tsf_update_restore_factor, "num of bcn intervals to stay TSF update restore status"); - -#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE -char *rtw_phy_file_path = REALTEK_CONFIG_PATH; -module_param(rtw_phy_file_path, charp, 0644); -MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter"); -/* PHY FILE Bit Map -* BIT0 - MAC, 0: non-support, 1: support -* BIT1 - BB, 0: non-support, 1: support -* BIT2 - BB_PG, 0: non-support, 1: support -* BIT3 - BB_MP, 0: non-support, 1: support -* BIT4 - RF, 0: non-support, 1: support -* BIT5 - RF_TXPWR_TRACK, 0: non-support, 1: support -* BIT6 - RF_TXPWR_LMT, 0: non-support, 1: support */ -int rtw_load_phy_file = (BIT2 | BIT6); -module_param(rtw_load_phy_file, int, 0644); -MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map"); -int rtw_decrypt_phy_file = 0; -module_param(rtw_decrypt_phy_file, int, 0644); -MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File"); -#endif - -uint rtw_recvbuf_nr = NR_RECVBUFF; -module_param(rtw_recvbuf_nr, int, 0644); -MODULE_PARM_DESC(rtw_recvbuf_nr, "Preallocated number of struct recv_buf"); - -#ifdef CONFIG_SUPPORT_TRX_SHARED -#ifdef DFT_TRX_SHARE_MODE -int rtw_trx_share_mode = DFT_TRX_SHARE_MODE; -#else -int rtw_trx_share_mode = 0; -#endif -module_param(rtw_trx_share_mode, int, 0644); -MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared"); -#endif - -#ifdef CONFIG_DYNAMIC_SOML -uint rtw_dynamic_soml_en = 1; -module_param(rtw_dynamic_soml_en, int, 0644); -MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param."); - -uint rtw_dynamic_soml_train_num = 0; -module_param(rtw_dynamic_soml_train_num, int, 0644); -MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number"); - -uint rtw_dynamic_soml_interval = 0; -module_param(rtw_dynamic_soml_interval, int, 0644); -MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval"); - -uint rtw_dynamic_soml_period = 0; -module_param(rtw_dynamic_soml_period, int, 0644); -MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period"); - -uint rtw_dynamic_soml_delay = 0; -module_param(rtw_dynamic_soml_delay, int, 0644); -MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay"); -#endif - -uint rtw_phydm_ability = 0xffffffff; -module_param(rtw_phydm_ability, uint, 0644); - -uint rtw_halrf_ability = 0xffffffff; -module_param(rtw_halrf_ability, uint, 0644); - -#ifdef CONFIG_RTW_MESH -uint rtw_peer_alive_based_preq = 1; -module_param(rtw_peer_alive_based_preq, uint, 0644); -MODULE_PARM_DESC(rtw_peer_alive_based_preq, - "On demand PREQ will reference peer alive status. 0: Off, 1: On"); -#endif - -int _netdev_open(struct net_device *pnetdev); int netdev_open(struct net_device *pnetdev); static int netdev_close(struct net_device *pnetdev); -#ifdef CONFIG_PLATFORM_INTEL_BYT -extern int rtw_sdio_set_power(int on); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ - -#ifdef CONFIG_MCC_MODE -/* enable MCC mode or not */ -int rtw_en_mcc = 1; -/* can referece following value before insmod driver */ -int rtw_mcc_ap_bw20_target_tx_tp = MCC_AP_BW20_TARGET_TX_TP; -int rtw_mcc_ap_bw40_target_tx_tp = MCC_AP_BW40_TARGET_TX_TP; -int rtw_mcc_ap_bw80_target_tx_tp = MCC_AP_BW80_TARGET_TX_TP; -int rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP; -int rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP; -int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP; -int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA; -int rtw_mcc_policy_table_idx = 0; -int rtw_mcc_duration = 0; -int rtw_mcc_enable_runtime_duration = 1; -#ifdef CONFIG_MCC_PHYDM_OFFLOAD -int rtw_mcc_phydm_offload = 1; -#else -int rtw_mcc_phydm_offload = 0; -#endif -module_param(rtw_en_mcc, int, 0644); -module_param(rtw_mcc_single_tx_cri, int, 0644); -module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644); -module_param(rtw_mcc_ap_bw40_target_tx_tp, int, 0644); -module_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644); -module_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644); -module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644); -module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644); -module_param(rtw_mcc_policy_table_idx, int, 0644); -module_param(rtw_mcc_duration, int, 0644); -module_param(rtw_mcc_phydm_offload, int, 0644); -#endif /*CONFIG_MCC_MODE */ - -#ifdef CONFIG_RTW_NAPI -/*following setting should define NAPI in Makefile -enable napi only = 1, disable napi = 0*/ -int rtw_en_napi = 1; -module_param(rtw_en_napi, int, 0644); -#ifdef CONFIG_RTW_NAPI_DYNAMIC -int rtw_napi_threshold = 100; /* unit: Mbps */ -module_param(rtw_napi_threshold, int, 0644); -#endif /* CONFIG_RTW_NAPI_DYNAMIC */ -#ifdef CONFIG_RTW_GRO -/*following setting should define GRO in Makefile -enable gro = 1, disable gro = 0*/ -int rtw_en_gro = 1; -module_param(rtw_en_gro, int, 0644); -#endif /* CONFIG_RTW_GRO */ -#endif /* CONFIG_RTW_NAPI */ - -#ifdef RTW_IQK_FW_OFFLOAD -int rtw_iqk_fw_offload = 1; -#else -int rtw_iqk_fw_offload; -#endif /* RTW_IQK_FW_OFFLOAD */ -module_param(rtw_iqk_fw_offload, int, 0644); - -#ifdef RTW_CHANNEL_SWITCH_OFFLOAD -int rtw_ch_switch_offload = 0; -#else -int rtw_ch_switch_offload; -#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ -module_param(rtw_ch_switch_offload, int, 0644); - -#ifdef CONFIG_TDLS -int rtw_en_tdls = 1; -module_param(rtw_en_tdls, int, 0644); -#endif - -#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT -int rtw_fw_param_init = 1; -module_param(rtw_fw_param_init, int, 0644); -#endif - -#ifdef CONFIG_TDMADIG -int rtw_tdmadig_en = 1; -/* -1:MODE_PERFORMANCE -2:MODE_COVERAGE -*/ -int rtw_tdmadig_mode = 1; -int rtw_dynamic_tdmadig = 0; -module_param(rtw_tdmadig_en, int, 0644); -module_param(rtw_tdmadig_mode, int, 0644); -module_param(rtw_dynamic_tdmadig, int, 0644); -#endif/*CONFIG_TDMADIG*/ - -/*dynamic RRSR default enable*/ -int rtw_en_dyn_rrsr = 1; -int rtw_rrsr_value = 0xFFFFFFFF; -module_param(rtw_en_dyn_rrsr, int, 0644); -module_param(rtw_rrsr_value, int, 0644); - -#ifdef CONFIG_WOWLAN -/* - * 0: disable, 1: enable - */ -uint rtw_wow_enable = 1; -module_param(rtw_wow_enable, uint, 0644); -/* - * bit[0]: magic packet wake up - * bit[1]: unucast packet(HW/FW unuicast) - * bit[2]: deauth wake up - */ -uint rtw_wakeup_event = RTW_WAKEUP_EVENT; -module_param(rtw_wakeup_event, uint, 0644); -/* - * 0: common WOWLAN - * bit[0]: disable BB RF - * bit[1]: For wireless remote controller with or without connection - */ -uint rtw_suspend_type = RTW_SUSPEND_TYPE; -module_param(rtw_suspend_type, uint, 0644); -#endif - -#ifdef RTW_BUSY_DENY_SCAN -uint rtw_scan_interval_thr = BUSY_TRAFFIC_SCAN_DENY_PERIOD; -module_param(rtw_scan_interval_thr, uint, 0644); -MODULE_PARM_DESC(rtw_scan_interval_thr, "Threshold used to judge if scan " \ - "request comes from scan UI, unit is ms."); -#endif /* RTW_BUSY_DENY_SCAN */ - -#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY -uint rtw_8822c_xcap_overwrite = 1; -module_param(rtw_8822c_xcap_overwrite, uint, 0644); -#endif - -#ifdef CONFIG_RTW_MULTI_AP -static int rtw_unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM] = CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE; -static int rtw_unassoc_sta_mode_of_stype_num = 0; -module_param_array(rtw_unassoc_sta_mode_of_stype, int, &rtw_unassoc_sta_mode_of_stype_num, 0644); - -uint rtw_max_unassoc_sta_cnt = 0; -module_param(rtw_max_unassoc_sta_cnt, uint, 0644); -#endif - -#if CONFIG_TX_AC_LIFETIME -static void rtw_regsty_load_tx_ac_lifetime(struct registry_priv *regsty) -{ - int i, j; - struct tx_aclt_conf_t *conf; - uint *parm; - - regsty->tx_aclt_flags = (u8)rtw_tx_aclt_flags; - - for (i = 0; i < TX_ACLT_CONF_NUM; i++) { - conf = ®sty->tx_aclt_confs[i]; - if (i == TX_ACLT_CONF_DEFAULT) - parm = rtw_tx_aclt_conf_default; - #ifdef CONFIG_AP_MODE - #if CONFIG_RTW_AP_DATA_BMC_TO_UC - else if (i == TX_ACLT_CONF_AP_M2U) - parm = rtw_tx_aclt_conf_ap_m2u; - #endif - #endif /* CONFIG_AP_MODE */ - #ifdef CONFIG_RTW_MESH - else if (i == TX_ACLT_CONF_MESH) - parm = rtw_tx_aclt_conf_mesh; - #endif - else - parm = NULL; - - if (parm) { - conf->en = parm[0] & 0xF; - conf->vo_vi = parm[1]; - conf->be_bk = parm[2]; - } - } -} -#endif - -// OpenHD params -int openhd_override_channel = 0; -module_param(openhd_override_channel, int, 0644); -MODULE_PARM_DESC(openhd_override_channel, "OpenHD easy (CRDA workaround)"); -int openhd_override_tx_power_mbm = 0; -module_param(openhd_override_tx_power_mbm, int, 0644); -MODULE_PARM_DESC(openhd_override_tx_power_mbm, "OpenHD easy (CRDA workaround)"); - -void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) -{ - int path, rs; - int *target_tx_pwr; - - for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { - if (path == RF_PATH_A) - target_tx_pwr = rtw_target_tx_pwr_2g_a; - else if (path == RF_PATH_B) - target_tx_pwr = rtw_target_tx_pwr_2g_b; - else if (path == RF_PATH_C) - target_tx_pwr = rtw_target_tx_pwr_2g_c; - else if (path == RF_PATH_D) - target_tx_pwr = rtw_target_tx_pwr_2g_d; - - for (rs = CCK; rs < RATE_SECTION_NUM; rs++) - regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs]; - } - -#if CONFIG_IEEE80211_BAND_5GHZ - for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { - if (path == RF_PATH_A) - target_tx_pwr = rtw_target_tx_pwr_5g_a; - else if (path == RF_PATH_B) - target_tx_pwr = rtw_target_tx_pwr_5g_b; - else if (path == RF_PATH_C) - target_tx_pwr = rtw_target_tx_pwr_5g_c; - else if (path == RF_PATH_D) - target_tx_pwr = rtw_target_tx_pwr_5g_d; - - for (rs = OFDM; rs < RATE_SECTION_NUM; rs++) - regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1]; - } -#endif /* CONFIG_IEEE80211_BAND_5GHZ */ -} - -inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) -{ - int i; - int ch_num = 0; - - for (i = 0; i < MAX_CHANNEL_NUM; i++) - if (((u8)rtw_excl_chs[i]) != 0) - regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i]; - - if (ch_num < MAX_CHANNEL_NUM) - regsty->excl_chs[ch_num] = 0; -} - -#ifdef CONFIG_80211N_HT -inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty) -{ - int i, j; - uint *sz_limit; - - for (i = 0; i < 4; i++) { - if (i == 0) - sz_limit = rtw_rx_ampdu_sz_limit_1ss; - else if (i == 1) - sz_limit = rtw_rx_ampdu_sz_limit_2ss; - else if (i == 2) - sz_limit = rtw_rx_ampdu_sz_limit_3ss; - else if (i == 3) - sz_limit = rtw_rx_ampdu_sz_limit_4ss; - - for (j = 0; j < 4; j++) - regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j]; - } -} -#endif /* CONFIG_80211N_HT */ - -#ifdef CONFIG_RTW_MULTI_AP -inline void rtw_regsty_init_unassoc_sta_param(struct registry_priv *regsty) -{ - int i; - - for (i = 0; i < UNASOC_STA_SRC_NUM; i++) - regsty->unassoc_sta_mode_of_stype[i] = rtw_unassoc_sta_mode_of_stype[i]; - - regsty->max_unassoc_sta_cnt = (u16) rtw_max_unassoc_sta_cnt; -} -#endif - -uint loadparam(_adapter *padapter) -{ - uint status = _SUCCESS; - struct registry_priv *registry_par = &padapter->registrypriv; - - -#ifdef CONFIG_RTW_DEBUG - if (rtw_drv_log_level >= _DRV_MAX_) - rtw_drv_log_level = _DRV_DEBUG_; -#endif - - registry_par->chip_version = (u8)rtw_chip_version; - registry_par->rfintfs = (u8)rtw_rfintfs; - registry_par->lbkmode = (u8)rtw_lbkmode; - /* registry_par->hci = (u8)hci; */ - registry_par->network_mode = (u8)rtw_network_mode; - - _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); - registry_par->ssid.SsidLength = 3; - - registry_par->channel = (u8)rtw_channel; -#ifdef CONFIG_NARROWBAND_SUPPORTING - if (rtw_nb_config != RTW_NB_CONFIG_NONE) - rtw_wireless_mode &= ~WIRELESS_11B; -#endif - registry_par->wireless_mode = (u8)rtw_wireless_mode; - - if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode)) - && (registry_par->channel > 14)) - registry_par->channel = 1; - else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode)) - && (registry_par->channel <= 14)) - registry_par->channel = 36; - - registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; - registry_par->vcs_type = (u8)rtw_vcs_type; - registry_par->rts_thresh = (u16)rtw_rts_thresh; - registry_par->frag_thresh = (u16)rtw_frag_thresh; - registry_par->preamble = (u8)rtw_preamble; - registry_par->scan_mode = (u8)rtw_scan_mode; - registry_par->smart_ps = (u8)rtw_smart_ps; - registry_par->check_fw_ps = (u8)rtw_check_fw_ps; - #ifdef CONFIG_TDMADIG - registry_par->tdmadig_en = (u8)rtw_tdmadig_en; - registry_par->tdmadig_mode = (u8)rtw_tdmadig_mode; - registry_par->tdmadig_dynamic = (u8) rtw_dynamic_tdmadig; - registry_par->power_mgnt = PS_MODE_ACTIVE; - registry_par->ips_mode = IPS_NONE; - #else - registry_par->power_mgnt = (u8)rtw_power_mgnt; - registry_par->ips_mode = (u8)rtw_ips_mode; - #endif/*CONFIG_TDMADIG*/ - registry_par->lps_level = (u8)rtw_lps_level; - registry_par->en_dyn_rrsr = (u8)rtw_en_dyn_rrsr; - registry_par->set_rrsr_value = (u32)rtw_rrsr_value; -#ifdef CONFIG_LPS_1T1R - registry_par->lps_1t1r = (u8)(rtw_lps_1t1r ? 1 : 0); -#endif - registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp; -#ifdef CONFIG_WOWLAN - registry_par->wow_power_mgnt = (u8)rtw_wow_power_mgnt; - registry_par->wow_lps_level = (u8)rtw_wow_lps_level; - #ifdef CONFIG_LPS_1T1R - registry_par->wow_lps_1t1r = (u8)(rtw_wow_lps_1t1r ? 1 : 0); - #endif -#endif /* CONFIG_WOWLAN */ - registry_par->radio_enable = (u8)rtw_radio_enable; - registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; - registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; - registry_par->busy_thresh = (u16)rtw_busy_thresh; - registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt; - /* registry_par->qos_enable = (u8)rtw_qos_enable; */ - registry_par->ack_policy = (u8)rtw_ack_policy; - registry_par->mp_mode = (u8)rtw_mp_mode; -#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) - registry_par->mp_customer_str = (u8)rtw_mp_customer_str; -#endif - registry_par->software_encrypt = (u8)rtw_software_encrypt; - registry_par->software_decrypt = (u8)rtw_software_decrypt; - - registry_par->acm_method = (u8)rtw_acm_method; - registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; - registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; - - /* WMM */ - registry_par->wmm_enable = (u8)rtw_wmm_enable; - -#ifdef CONFIG_WMMPS_STA - /* UAPSD */ - registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp; - registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable; - registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps; -#endif /* CONFIG_WMMPS_STA */ - - registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; - -#if CONFIG_TX_AC_LIFETIME - rtw_regsty_load_tx_ac_lifetime(registry_par); -#endif - - registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode; - -#ifdef CONFIG_80211N_HT - registry_par->ht_enable = (u8)rtw_ht_enable; - if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) { -#ifdef CONFIG_NARROWBAND_SUPPORTING - if (rtw_nb_config != RTW_NB_CONFIG_NONE) - rtw_bw_mode = 0; -#endif - registry_par->bw_mode = (u8)rtw_bw_mode; - registry_par->ampdu_enable = (u8)rtw_ampdu_enable; - registry_par->rx_stbc = (u8)rtw_rx_stbc; - registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; - registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; - registry_par->tx_quick_addba_req = (u8)rtw_quick_addba_req; - registry_par->short_gi = (u8)rtw_short_gi; - registry_par->ldpc_cap = (u8)rtw_ldpc_cap; -#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA) - rtw_stbc_cap = 0x0; -#endif -#ifdef CONFIG_RTW_TX_NPATH_EN - registry_par->tx_npath = (u8)rtw_tx_npath_enable; -#endif -#ifdef CONFIG_RTW_PATH_DIV - registry_par->path_div = (u8)rtw_path_div_enable; -#endif - registry_par->stbc_cap = (u8)rtw_stbc_cap; - registry_par->beamform_cap = (u8)rtw_beamform_cap; - registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; - registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; - rtw_regsty_init_rx_ampdu_sz_limit(registry_par); - } -#endif -#ifdef DBG_LA_MODE - registry_par->la_mode_en = (u8)rtw_la_mode_en; -#endif -#ifdef CONFIG_NARROWBAND_SUPPORTING - registry_par->rtw_nb_config = (u8)rtw_nb_config; -#endif - -#ifdef CONFIG_80211AC_VHT - registry_par->vht_enable = (u8)rtw_vht_enable; - registry_par->vht_24g_enable = (u8)rtw_vht_24g_enable; - registry_par->ampdu_factor = (u8)rtw_ampdu_factor; - registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF); - registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8); -#endif - -#ifdef CONFIG_TX_EARLY_MODE - registry_par->early_mode = (u8)rtw_early_mode; -#endif - registry_par->trx_path_bmp = (u8)rtw_trx_path_bmp; - registry_par->tx_path_lmt = (u8)rtw_tx_path_lmt; - registry_par->rx_path_lmt = (u8)rtw_rx_path_lmt; - registry_par->tx_nss = (u8)rtw_tx_nss; - registry_par->rx_nss = (u8)rtw_rx_nss; - registry_par->low_power = (u8)rtw_low_power; - - registry_par->check_hw_status = (u8)rtw_check_hw_status; - - registry_par->wifi_spec = (u8)rtw_wifi_spec; - -#ifdef CONFIG_REGD_SRC_FROM_OS - if (regd_src_is_valid(rtw_regd_src)) - registry_par->regd_src = (u8)rtw_regd_src; - else { - RTW_WARN("%s invalid rtw_regd_src(%u), use REGD_SRC_RTK_PRIV instead\n", __func__, rtw_regd_src); - registry_par->regd_src = REGD_SRC_RTK_PRIV; - } -#endif - - if (strlen(rtw_country_code) != 2 - || is_alpha(rtw_country_code[0]) == _FALSE - || is_alpha(rtw_country_code[1]) == _FALSE - ) { - if (rtw_country_code != rtw_country_unspecified) - RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__); - _rtw_memset(registry_par->alpha2, 0xFF, 2); - } else - _rtw_memcpy(registry_par->alpha2, rtw_country_code, 2); - - registry_par->channel_plan = (u8)rtw_channel_plan; - rtw_regsty_load_excl_chs(registry_par); - - registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake; -#ifdef CONFIG_BT_COEXIST - registry_par->btcoex = (u8)rtw_btcoex_enable; - registry_par->bt_iso = (u8)rtw_bt_iso; - registry_par->bt_sco = (u8)rtw_bt_sco; - registry_par->bt_ampdu = (u8)rtw_bt_ampdu; - registry_par->ant_num = (u8)rtw_ant_num; - registry_par->single_ant_path = (u8) rtw_single_ant_path; -#endif - - registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; - - registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; - registry_par->antdiv_type = (u8)rtw_antdiv_type; - - registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch; - registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode; -#ifdef SUPPORT_HW_RFOFF_DETECTED - registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable,1:enable,2:by EFUSE config */ - registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable,1:enable */ -#endif - - registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; - -#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE - snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path); - registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0; -#endif - -#ifdef CONFIG_LAYER2_ROAMING - registry_par->max_roaming_times = (u8)rtw_max_roaming_times; -#endif - -#ifdef CONFIG_IOL - registry_par->fw_iol = rtw_fw_iol; -#endif - -#ifdef CONFIG_80211D - registry_par->enable80211d = (u8)rtw_80211d; -#endif - - snprintf(registry_par->ifname, 16, "%s", ifname); - snprintf(registry_par->if2name, 16, "%s", if2name); - - registry_par->notch_filter = (u8)rtw_notch_filter; - -#ifdef CONFIG_CONCURRENT_MODE - registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num; -#ifdef CONFIG_P2P - registry_par->sel_p2p_iface = (u8)rtw_sel_p2p_iface; - RTW_INFO("%s, Select P2P interface: iface_id:%d\n", __func__, registry_par->sel_p2p_iface); -#endif -#endif - registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; - -#if CONFIG_TXPWR_LIMIT - registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable; -#endif - registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate; - - rtw_regsty_load_target_tx_power(registry_par); - - registry_par->antenna_gain = (s16)rtw_antenna_gain; - - registry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor; - registry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor; - - registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; - registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; - registry_par->bEn_RFE = 1; - registry_par->RFE_Type = (u8)rtw_RFE_type; - registry_par->PowerTracking_Type = (u8)rtw_powertracking_type; - registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g; - registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g; - registry_par->GLNA_Type = (u8)rtw_GLNA_type; -#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - registry_par->load_phy_file = (u8)rtw_load_phy_file; - registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file; -#endif - registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable; - - registry_par->hiq_filter = (u8)rtw_hiq_filter; - - registry_par->adaptivity_en = (u8)rtw_adaptivity_en; - registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode; - registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; - registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; - -#ifdef CONFIG_DYNAMIC_SOML - registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en; - registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num; - registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval; - registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period; - registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay; -#endif - - registry_par->boffefusemask = (u8)rtw_OffEfuseMask; - registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; - registry_par->bBTFileMaskEfuse = (u8)rtw_FileMaskEfuse; - -#ifdef CONFIG_RTW_ACS - registry_par->acs_mode = (u8)rtw_acs; - registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan; -#endif -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - registry_par->nm_mode = (u8)rtw_nm; -#endif - registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g; - registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl; - registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm; - registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh; - -#ifdef CONFIG_DFS_MASTER - registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain; - #ifdef CONFIG_REGD_SRC_FROM_OS - if (rtw_regd_src == REGD_SRC_OS && registry_par->dfs_region_domain != RTW_DFS_REGD_NONE) { - RTW_WARN("%s force disable radar detection capability when regd_src is OS\n", __func__); - registry_par->dfs_region_domain = RTW_DFS_REGD_NONE; - } - #endif -#endif - - registry_par->amsdu_mode = (u8)rtw_amsdu_mode; - -#ifdef CONFIG_MCC_MODE - registry_par->en_mcc = (u8)rtw_en_mcc; - registry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp; - registry_par->rtw_mcc_ap_bw40_target_tx_tp = (u32)rtw_mcc_ap_bw40_target_tx_tp; - registry_par->rtw_mcc_ap_bw80_target_tx_tp = (u32)rtw_mcc_ap_bw80_target_tx_tp; - registry_par->rtw_mcc_sta_bw20_target_tx_tp = (u32)rtw_mcc_sta_bw20_target_tx_tp; - registry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp; - registry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp; - registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri; - registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx; - registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration; - registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration; - registry_par->rtw_mcc_phydm_offload = rtw_mcc_phydm_offload; -#endif /*CONFIG_MCC_MODE */ - -#ifdef CONFIG_WOWLAN - registry_par->wowlan_enable = rtw_wow_enable; - registry_par->wakeup_event = rtw_wakeup_event; - registry_par->suspend_type = rtw_suspend_type; -#endif - -#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_PREALLOC_RX_SKB_BUFFER) - if (rtw_recvbuf_nr != NR_RECVBUFF) { - RTW_WARN("CONFIG_PREALLOC_RX_SKB_BUFFER && CONFIG_SDIO_HCI, force recvbuf_nr to NR_RECVBUFF(%d)\n", NR_RECVBUFF); - rtw_recvbuf_nr = NR_RECVBUFF; - } -#endif - registry_par->recvbuf_nr = rtw_recvbuf_nr; - -#ifdef CONFIG_SUPPORT_TRX_SHARED - registry_par->trx_share_mode = rtw_trx_share_mode; -#endif - registry_par->wowlan_sta_mix_mode = rtw_wowlan_sta_mix_mode; - -#ifdef CONFIG_PCI_HCI - registry_par->pci_aspm_config = rtw_pci_aspm_enable; - registry_par->pci_dynamic_aspm_linkctrl = rtw_pci_dynamic_aspm_linkctrl; -#endif - -#ifdef CONFIG_RTW_NAPI - registry_par->en_napi = (u8)rtw_en_napi; -#ifdef CONFIG_RTW_NAPI_DYNAMIC - registry_par->napi_threshold = (u32)rtw_napi_threshold; -#endif /* CONFIG_RTW_NAPI_DYNAMIC */ -#ifdef CONFIG_RTW_GRO - registry_par->en_gro = (u8)rtw_en_gro; - if (!registry_par->en_napi && registry_par->en_gro) { - registry_par->en_gro = 0; - RTW_WARN("Disable GRO because NAPI is not enabled\n"); - } -#endif /* CONFIG_RTW_GRO */ -#endif /* CONFIG_RTW_NAPI */ - - registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload; - registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload; - -#ifdef CONFIG_TDLS - registry_par->en_tdls = rtw_en_tdls; -#endif - -#ifdef CONFIG_ADVANCE_OTA - registry_par->adv_ota = rtw_advnace_ota; -#endif -#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT - registry_par->fw_param_init = rtw_fw_param_init; -#endif -#ifdef CONFIG_AP_MODE - registry_par->bmc_tx_rate = rtw_bmc_tx_rate; - #if CONFIG_RTW_AP_DATA_BMC_TO_UC - registry_par->ap_src_b2u_flags = rtw_ap_src_b2u_flags; - registry_par->ap_fwd_b2u_flags = rtw_ap_fwd_b2u_flags; - #endif -#endif /* CONFIG_AP_MODE */ - -#ifdef CONFIG_RTW_MESH - #if CONFIG_RTW_MESH_DATA_BMC_TO_UC - registry_par->msrc_b2u_flags = rtw_msrc_b2u_flags; - registry_par->mfwd_b2u_flags = rtw_mfwd_b2u_flags; - #endif -#endif /* CONFIG_RTW_MESH */ - -#ifdef CONFIG_FW_HANDLE_TXBCN - registry_par->fw_tbtt_rpt = rtw_tbtt_rpt; -#endif - registry_par->phydm_ability = rtw_phydm_ability; - registry_par->halrf_ability = rtw_halrf_ability; -#ifdef CONFIG_RTW_MESH - registry_par->peer_alive_based_preq = rtw_peer_alive_based_preq; -#endif - -#ifdef RTW_BUSY_DENY_SCAN - registry_par->scan_interval_thr = rtw_scan_interval_thr; -#endif - -#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY - registry_par->rtw_8822c_xcap_overwrite = (u8)rtw_8822c_xcap_overwrite; -#endif - -#ifdef CONFIG_RTW_MULTI_AP - rtw_regsty_init_unassoc_sta_param(registry_par); -#endif - - return status; -} /** * rtw_net_set_mac_address @@ -1629,35 +76,11 @@ static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) } _rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) - dev_addr_set(pnetdev, sa->sa_data); -#else _rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */ -#endif - -#if 0 - if (rtw_is_hw_init_completed(padapter)) { - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ - -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_hal_change_macaddr_mbid(padapter, sa->sa_data); -#else - rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */ -#endif - - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); - } -#else - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_hal_change_macaddr_mbid(padapter, sa->sa_data); -#else - rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */ -#endif - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); -#endif + + /* Since the net_device is in down state, there is no wrole at this moment. + * The new mac address will be set to hw when changing the net_device to up state. + */ RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n" , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); @@ -1671,14 +94,14 @@ static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct recv_priv *precvpriv = &(padapter->recvpriv); + struct recv_info *precvinfo = &(padapter->recvinfo); padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */ - padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */ + padapter->stats.rx_packets = precvinfo->rx_pkts;/* precvinfo->rx_pkts++; */ padapter->stats.tx_dropped = pxmitpriv->tx_drop; - padapter->stats.rx_dropped = precvpriv->rx_drop; + padapter->stats.rx_dropped = precvinfo->rx_drop; padapter->stats.tx_bytes = pxmitpriv->tx_bytes; - padapter->stats.rx_bytes = precvpriv->rx_bytes; + padapter->stats.rx_bytes = precvinfo->rx_bytes; return &padapter->stats; } @@ -1726,7 +149,7 @@ static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb #else , void *accel_priv #endif - #if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0))) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) , select_queue_fallback_t fallback #endif #endif @@ -1778,6 +201,10 @@ static u8 is_rtw_ndev(struct net_device *ndev) #endif } + +#define _netdev_status_msg(_ndev, state, sts_str) \ + RTW_INFO(FUNC_NDEV_FMT" state:%lu - %s\n", FUNC_NDEV_ARG(_ndev), state, sts_str); + static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) { struct net_device *ndev; @@ -1797,21 +224,40 @@ static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state if (!is_rtw_ndev(ndev)) return NOTIFY_DONE; - RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state); - switch (state) { + case NETDEV_CHANGE: + _netdev_status_msg(ndev, state, "netdev change"); + break; + case NETDEV_GOING_DOWN: + _netdev_status_msg(ndev, state, "netdev going down"); + break; + case NETDEV_DOWN: + _netdev_status_msg(ndev, state, "netdev down"); + break; + case NETDEV_UP: + _netdev_status_msg(ndev, state, "netdev up"); + break; + case NETDEV_REBOOT: + _netdev_status_msg(ndev, state, "netdev reboot"); + break; case NETDEV_CHANGENAME: rtw_adapter_proc_replace(ndev); + _netdev_status_msg(ndev, state, "netdev chang ename"); break; - #ifdef CONFIG_NEW_NETDEV_HDL case NETDEV_PRE_UP : { _adapter *adapter = rtw_netdev_priv(ndev); rtw_pwr_wakeup(adapter); } + _netdev_status_msg(ndev, state, "netdev pre up"); + break; + case NETDEV_JOIN: + _netdev_status_msg(ndev, state, "netdev join"); + break; + default: + _netdev_status_msg(ndev, state, " "); break; - #endif } return NOTIFY_DONE; @@ -1839,8 +285,15 @@ int rtw_ndev_init(struct net_device *dev) , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr)); strncpy(adapter->old_ifname, dev->name, IFNAMSIZ); adapter->old_ifname[IFNAMSIZ - 1] = '\0'; +#ifdef CONFIG_ARCH_CORTINA + dev->priv_flags = IFF_DOMAIN_WLAN; +#endif rtw_adapter_proc_init(dev); +#ifdef CONFIG_RTW_NAPI + netif_napi_add(dev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT); +#endif /* CONFIG_RTW_NAPI */ + return 0; } @@ -1851,6 +304,14 @@ void rtw_ndev_uninit(struct net_device *dev) RTW_PRINT(FUNC_ADPT_FMT" if%d\n" , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1)); rtw_adapter_proc_deinit(dev); + +#ifdef CONFIG_RTW_NAPI + if(adapter->napi_state == NAPI_ENABLE) { + napi_disable(&adapter->napi); + adapter->napi_state = NAPI_DISABLE; + } + netif_napi_del(&adapter->napi); +#endif /* CONFIG_RTW_NAPI */ } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) @@ -1871,30 +332,6 @@ static const struct net_device_ops rtw_netdev_ops = { int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) { -#ifdef CONFIG_EASY_REPLACEMENT - _adapter *padapter = rtw_netdev_priv(pnetdev); - struct net_device *TargetNetdev = NULL; - _adapter *TargetAdapter = NULL; - - if (padapter->bDongle == 1) { - TargetNetdev = rtw_get_same_net_ndev_by_name(pnetdev, "wlan0"); - if (TargetNetdev) { - RTW_INFO("Force onboard module driver disappear !!!\n"); - TargetAdapter = rtw_netdev_priv(TargetNetdev); - TargetAdapter->DriverState = DRIVER_DISAPPEAR; - - padapter->pid[0] = TargetAdapter->pid[0]; - padapter->pid[1] = TargetAdapter->pid[1]; - padapter->pid[2] = TargetAdapter->pid[2]; - - dev_put(TargetNetdev); - unregister_netdev(TargetNetdev); - - padapter->DriverState = DRIVER_REPLACE_DONGLE; - } - } -#endif /* CONFIG_EASY_REPLACEMENT */ - if (dev_alloc_name(pnetdev, ifname) < 0) RTW_ERR("dev_alloc_name, fail!\n"); @@ -1983,9 +420,16 @@ struct net_device *rtw_init_netdev(_adapter *old_padapter) /* pnetdev->wireless_data = &priv->wireless_data; */ #endif +#ifdef CONFIG_TX_AMSDU_SW_MODE + pnetdev->needed_headroom += 8; /* +8 for rfc1042 header */ + pnetdev->needed_headroom += 4; /* +4 for padding */ +#endif + return pnetdev; } - +#ifdef CONFIG_PCI_HCI +#include +#endif int rtw_os_ndev_alloc(_adapter *adapter) { int ret = _FAIL; @@ -2001,9 +445,9 @@ int rtw_os_ndev_alloc(_adapter *adapter) #endif #ifdef CONFIG_PCI_HCI - if (adapter_to_dvobj(adapter)->bdma64) + if (is_pci_support_dma64(adapter_to_dvobj(adapter))) ndev->features |= NETIF_F_HIGHDMA; - ndev->irq = adapter_to_dvobj(adapter)->irq; + ndev->irq = dvobj_to_pci(adapter_to_dvobj(adapter))->irq; #endif #if defined(CONFIG_IOCTL_CFG80211) @@ -2025,6 +469,12 @@ void rtw_os_ndev_free(_adapter *adapter) rtw_cfg80211_ndev_res_free(adapter); #endif + /* free the old_pnetdev */ + if (adapter->rereg_nd_name_priv.old_pnetdev) { + rtw_free_netdev(adapter->rereg_nd_name_priv.old_pnetdev); + adapter->rereg_nd_name_priv.old_pnetdev = NULL; + } + if (adapter->pnetdev) { rtw_free_netdev(adapter->pnetdev); adapter->pnetdev = NULL; @@ -2038,7 +488,6 @@ static void rtw_ethtool_get_drvinfo(struct net_device *dev, struct ethtool_drvin { struct wireless_dev *wdev = NULL; _adapter *padapter = NULL; - HAL_DATA_TYPE *hal_data = NULL; wdev = dev->ieee80211_ptr; if (wdev) { @@ -2051,14 +500,20 @@ static void rtw_ethtool_get_drvinfo(struct net_device *dev, struct ethtool_drvin strlcpy(info->version, DRIVERVERSION, sizeof(info->version)); padapter = (_adapter *)rtw_netdev_priv(dev); + + + /*GEORGIA_TODO_FIXIT*/ + #if 0 + HAL_DATA_TYPE *hal_data = NULL; if (padapter) { - hal_data = GET_HAL_DATA(padapter); + hal_data = GET_PHL_COM(padapter); } - if (hal_data) { scnprintf(info->fw_version, sizeof(info->fw_version), "%d.%d", hal_data->firmware_version, hal_data->firmware_sub_version); - } else { + } else + #endif + { strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); } @@ -2092,7 +547,7 @@ static void rtw_ethtool_get_strings(struct net_device *dev, u32 sset, u8 *data) if (sset == ETH_SS_STATS) { sz_sta_stats = sizeof(rtw_ethtool_gstrings_sta_stats); - memcpy(data, rtw_ethtool_gstrings_sta_stats, sz_sta_stats); + _rtw_memcpy(data, rtw_ethtool_gstrings_sta_stats, sz_sta_stats); } } @@ -2103,18 +558,18 @@ static void rtw_ethtool_get_stats(struct net_device *dev, int i = 0; _adapter *padapter = NULL; struct xmit_priv *pxmitpriv = NULL; - struct recv_priv *precvpriv = NULL; + struct recv_info *precvinfo = NULL; memset(data, 0, sizeof(u64) * RTW_ETHTOOL_STATS_LEN); - + padapter = (_adapter *)rtw_netdev_priv(dev); if (padapter) { pxmitpriv = &(padapter->xmitpriv); - precvpriv = &(padapter->recvpriv); + precvinfo = &(padapter->recvinfo); - data[i++] = precvpriv->rx_pkts; - data[i++] = precvpriv->rx_bytes; - data[i++] = precvpriv->rx_drop; + data[i++] = precvinfo->rx_pkts; + data[i++] = precvinfo->rx_bytes; + data[i++] = precvinfo->rx_drop; data[i++] = pxmitpriv->tx_pkts; data[i++] = pxmitpriv->tx_bytes; @@ -2137,7 +592,7 @@ static const struct ethtool_ops rtw_ethtool_ops = { .get_ethtool_stats = rtw_ethtool_get_stats, .get_sset_count = rtw_ethtool_get_sset_count, }; -#endif // LINUX_VERSION_CODE >= 3.7.8 +#endif // LINUX_VERSION_CODE >= 3.7.8 #endif /* CONFIG_IOCTL_CFG80211 */ /* For ethtool --- */ @@ -2148,14 +603,6 @@ int rtw_os_ndev_register(_adapter *adapter, const char *name) struct net_device *ndev = adapter->pnetdev; u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); -#ifdef CONFIG_RTW_NAPI -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - netif_napi_add_weight(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT); -#else - netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT); -#endif -#endif /* CONFIG_RTW_NAPI */ - #if defined(CONFIG_IOCTL_CFG80211) if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) { rtw_warn_on(1); @@ -2173,15 +620,7 @@ int rtw_os_ndev_register(_adapter *adapter, const char *name) /* alloc netdev name */ rtw_init_netdev_name(ndev, name); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) - dev_addr_set(ndev, adapter_mac_addr(adapter)); -#else _rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN); -#endif - - #ifdef CONFIG_NET_NS - dev_net_set(ndev, wiphy_net(adapter_to_wiphy(adapter))); - #endif //CONFIG_NET_NS /* Tell the network stack we exist */ @@ -2198,19 +637,12 @@ int rtw_os_ndev_register(_adapter *adapter, const char *name) #if defined(CONFIG_IOCTL_CFG80211) if (ret != _SUCCESS) { rtw_cfg80211_ndev_res_unregister(adapter); - #if !defined(RTW_SINGLE_WIPHY) - rtw_wiphy_unregister(adapter_to_wiphy(adapter)); - #endif } #endif #if defined(CONFIG_IOCTL_CFG80211) exit: #endif -#ifdef CONFIG_RTW_NAPI - if (ret != _SUCCESS) - netif_napi_del(&adapter->napi); -#endif /* CONFIG_RTW_NAPI */ return ret; } @@ -2230,7 +662,7 @@ void rtw_os_ndev_unregister(_adapter *adapter) rtw_cfg80211_ndev_res_unregister(adapter); #endif - if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) { + if (netdev) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); @@ -2240,21 +672,6 @@ void rtw_os_ndev_unregister(_adapter *adapter) unregister_netdevice(netdev); } -#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY) -#ifdef CONFIG_RFKILL_POLL - rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter)); -#endif - rtw_wiphy_unregister(adapter_to_wiphy(adapter)); -#endif - -#ifdef CONFIG_RTW_NAPI - if (adapter->napi_state == NAPI_ENABLE) { - napi_disable(&adapter->napi); - adapter->napi_state = NAPI_DISABLE; - } - netif_napi_del(&adapter->napi); -#endif /* CONFIG_RTW_NAPI */ - adapter->registered = 0; adapter->ndev_unregistering = 0; } @@ -2320,8 +737,9 @@ int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) if (adapter && !adapter->pnetdev) { #ifdef CONFIG_RTW_DYNAMIC_NDEV - if (!is_primary_adapter(adapter)) - continue; + if (!is_primary_adapter(adapter) && + (i >= CONFIG_RTW_STATIC_NDEV_NUM)) + break; #endif status = rtw_os_ndev_alloc(adapter); @@ -2374,6 +792,7 @@ void rtw_os_ndevs_free(struct dvobj_priv *dvobj) #endif } +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ u32 rtw_start_drv_threads(_adapter *padapter) { u32 _status = _SUCCESS; @@ -2387,11 +806,9 @@ u32 rtw_start_drv_threads(_adapter *padapter) { if (padapter->xmitThread == NULL) { RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter)); - padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); - if (IS_ERR(padapter->xmitThread)) { - padapter->xmitThread = NULL; + padapter->xmitThread = rtw_thread_start(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); + if (padapter->xmitThread == NULL) _status = _FAIL; - } } } #endif /* #ifdef CONFIG_XMIT_THREAD_MODE */ @@ -2400,11 +817,9 @@ u32 rtw_start_drv_threads(_adapter *padapter) if (is_primary_adapter(padapter)) { if (padapter->recvThread == NULL) { RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter)); - padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); - if (IS_ERR(padapter->recvThread)) { - padapter->recvThread = NULL; + padapter->recvThread = rtw_thread_start(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); + if (padapter->recvThread == NULL) _status = _FAIL; - } } } #endif @@ -2412,29 +827,15 @@ u32 rtw_start_drv_threads(_adapter *padapter) if (is_primary_adapter(padapter)) { if (padapter->cmdThread == NULL) { RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter)); - padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); - if (IS_ERR(padapter->cmdThread)) { - padapter->cmdThread = NULL; + padapter->cmdThread = rtw_thread_start(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); + if (padapter->cmdThread == NULL) _status = _FAIL; - } else _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ } } - -#ifdef CONFIG_EVENT_THREAD_MODE - if (padapter->evtThread == NULL) { - RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter)); - padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); - if (IS_ERR(padapter->evtThread)) { - padapter->evtThread = NULL; - _status = _FAIL; - } - } -#endif - - rtw_hal_start_thread(padapter); + _status = rtw_intf_start_xmit_frame_thread(padapter); return _status; } @@ -2445,14 +846,6 @@ void rtw_stop_drv_threads(_adapter *padapter) if (is_primary_adapter(padapter)) rtw_stop_cmd_thread(padapter); -#ifdef CONFIG_EVENT_THREAD_MODE - if (padapter->evtThread) { - _rtw_up_sema(&padapter->evtpriv.evt_notify); - rtw_thread_stop(padapter->evtThread); - padapter->evtThread = NULL; - } -#endif - #ifdef CONFIG_XMIT_THREAD_MODE /* Below is to termindate tx_thread... */ #if defined(CONFIG_SDIO_HCI) @@ -2477,14 +870,17 @@ void rtw_stop_drv_threads(_adapter *padapter) } #endif - rtw_hal_stop_thread(padapter); + /*rtw_hal_stop_thread(padapter);*/ + rtw_intf_cancel_xmit_frame_thread(padapter); + } +#endif u8 rtw_init_default_value(_adapter *padapter) { u8 ret = _SUCCESS; struct registry_priv *pregistrypriv = &padapter->registrypriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct security_priv *psecuritypriv = &padapter->securitypriv; /* xmit_priv */ @@ -2513,28 +909,23 @@ u8 rtw_init_default_value(_adapter *padapter) psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled; +#ifdef CONFIG_CONCURRENT_MODE psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID; - +#endif /* pwrctrl_priv */ - /* registry_priv */ rtw_init_registrypriv_dev_network(padapter); rtw_update_registrypriv_dev_network(padapter); + pregistrypriv->wireless_mode &= rtw_hw_get_wireless_mode(adapter_to_dvobj(padapter)); + pregistrypriv->band_type &= rtw_hw_get_band_type(adapter_to_dvobj(padapter)); + /*init fw_psmode_iface_id*/ + adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; - /* hal_priv */ - rtw_hal_def_value_init(padapter); - -#ifdef CONFIG_MCC_MODE - /* MCC parameter */ - rtw_hal_mcc_parameter_init(padapter); -#endif /* CONFIG_MCC_MODE */ /* misc. */ - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); padapter->bLinkInfoDump = 0; padapter->bNotifyChannelChange = _FALSE; #ifdef CONFIG_P2P @@ -2542,9 +933,9 @@ u8 rtw_init_default_value(_adapter *padapter) #endif /* for debug purpose */ - padapter->fix_rate = 0xFF; + padapter->fix_rate = NO_FIX_RATE; padapter->data_fb = 0; - padapter->fix_bw = 0xFF; + padapter->fix_bw = NO_FIX_BW; padapter->power_offset = 0; padapter->rsvd_page_offset = 0; padapter->rsvd_page_num = 0; @@ -2564,7 +955,7 @@ u8 rtw_init_default_value(_adapter *padapter) padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; #ifdef CONFIG_TX_AMSDU padapter->tx_amsdu = 2; - padapter->tx_amsdu_rate = 400; + padapter->tx_amsdu_rate = 10; #endif padapter->driver_tx_max_agg_num = 0xFF; #ifdef DBG_RX_COUNTER_DUMP @@ -2577,116 +968,79 @@ u8 rtw_init_default_value(_adapter *padapter) padapter->napi_state = NAPI_DISABLE; #endif -#ifdef CONFIG_RTW_ACS - if (pregistrypriv->acs_mode) - rtw_acs_start(padapter); - else - rtw_acs_stop(padapter); -#endif -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - if (pregistrypriv->nm_mode) - rtw_nm_enable(padapter); - else - rtw_nm_disable(padapter); -#endif - #ifdef CONFIG_RTW_TOKEN_BASED_XMIT ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE); ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE); padapter->tbtx_capability = _TRUE; #endif +#ifdef CONFIG_CORE_TXSC + txsc_init(padapter); +#endif + return ret; } -#ifdef CONFIG_CLIENT_PORT_CFG -extern void rtw_clt_port_init(struct clt_port_t *cltp); -extern void rtw_clt_port_deinit(struct clt_port_t *cltp); -#endif + +#ifdef CONFIG_DRV_FAKE_AP +extern void rtw_fakeap_work(struct work_struct *work); +extern void rtw_fakeap_bcn_timer_hdl(void*); +#endif /* CONFIG_DRV_FAKE_AP */ struct dvobj_priv *devobj_init(void) { struct dvobj_priv *pdvobj = NULL; + struct rf_ctl_t *rfctl; pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj)); if (pdvobj == NULL) return NULL; + rfctl = dvobj_to_rfctl(pdvobj); + _rtw_mutex_init(&pdvobj->hw_init_mutex); - _rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex); _rtw_mutex_init(&pdvobj->setch_mutex); _rtw_mutex_init(&pdvobj->setbw_mutex); _rtw_mutex_init(&pdvobj->rf_read_reg_mutex); _rtw_mutex_init(&pdvobj->ioctrl_mutex); -#ifdef CONFIG_SDIO_INDIRECT_ACCESS - _rtw_mutex_init(&pdvobj->sd_indirect_access_mutex); -#endif -#ifdef CONFIG_SYSON_INDIRECT_ACCESS - _rtw_mutex_init(&pdvobj->syson_indirect_access_mutex); -#endif + #ifdef CONFIG_RTW_CUSTOMER_STR _rtw_mutex_init(&pdvobj->customer_str_mutex); _rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN); #endif -#ifdef CONFIG_PROTSEL_PORT - _rtw_mutex_init(&pdvobj->protsel_port.mutex); -#endif -#ifdef CONFIG_PROTSEL_ATIMDTIM - _rtw_mutex_init(&pdvobj->protsel_atimdtim.mutex); -#endif -#ifdef CONFIG_PROTSEL_MACSLEEP - _rtw_mutex_init(&pdvobj->protsel_macsleep.mutex); -#endif pdvobj->processing_dev_remove = _FALSE; ATOMIC_SET(&pdvobj->disable_func, 0); + /* move to phl */ + /* rtw_macid_ctl_init(&pdvobj->macid_ctl); */ - rtw_macid_ctl_init(&pdvobj->macid_ctl); -#ifdef CONFIG_CLIENT_PORT_CFG - rtw_clt_port_init(&pdvobj->clt_port); -#endif _rtw_spinlock_init(&pdvobj->cam_ctl.lock); _rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex); -#if defined(CONFIG_PLATFORM_RTK129X) && defined(CONFIG_PCI_HCI) +#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI) _rtw_spinlock_init(&pdvobj->io_reg_lock); #endif -#ifdef CONFIG_MBSSID_CAM - rtw_mbid_cam_init(pdvobj); -#endif -#ifdef CONFIG_AP_MODE - #ifdef CONFIG_SUPPORT_MULTI_BCN - pdvobj->nr_ap_if = 0; - pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */ - _rtw_init_queue(&pdvobj->ap_if_q); - pdvobj->vap_map = 0; - #endif /*CONFIG_SUPPORT_MULTI_BCN*/ - #ifdef CONFIG_SWTIMER_BASED_TXBCN - rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj); + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + rtw_init_timer(&(pdvobj->dynamic_chk_timer), rtw_dynamic_check_timer_handlder, pdvobj); #endif -#endif - - rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj); - rtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj); - -#ifdef CONFIG_MCC_MODE - _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex)); - _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex)); - _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex)); - _rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock); -#endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI_DYNAMIC pdvobj->en_napi_dynamic = 0; #endif /* CONFIG_RTW_NAPI_DYNAMIC */ + _rtw_mutex_init(&rfctl->offch_mutex); -#ifdef CONFIG_RTW_TPT_MODE - pdvobj->tpt_mode = 0; - pdvobj->edca_be_ul = 0x5ea42b; - pdvobj->edca_be_dl = 0x00a42b; -#endif pdvobj->scan_deny = _FALSE; + rtw_load_dvobj_registry(pdvobj); + +#ifdef CONFIG_DRV_FAKE_AP + skb_queue_head_init(&pdvobj->fakeap.rxq); + _init_workitem(&pdvobj->fakeap.work, rtw_fakeap_work, pdvobj); + _init_timer(&pdvobj->fakeap.bcn_timer, rtw_fakeap_bcn_timer_hdl, pdvobj); +#endif /* CONFIG_DRV_FAKE_AP */ + + /* wpas type default from w1.fi */ + pdvobj->wpas_type = RTW_WPAS_W1FI; return pdvobj; @@ -2702,57 +1056,26 @@ void devobj_deinit(struct dvobj_priv *pdvobj) rtw_cfg80211_dev_res_free(pdvobj); #endif -#ifdef CONFIG_MCC_MODE - _rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex)); - _rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex)); - _rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex)); - _rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock); -#endif /* CONFIG_MCC_MODE */ - _rtw_mutex_free(&pdvobj->hw_init_mutex); - _rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex); #ifdef CONFIG_RTW_CUSTOMER_STR _rtw_mutex_free(&pdvobj->customer_str_mutex); #endif -#ifdef CONFIG_PROTSEL_PORT - _rtw_mutex_free(&pdvobj->protsel_port.mutex); -#endif -#ifdef CONFIG_PROTSEL_ATIMDTIM - _rtw_mutex_free(&pdvobj->protsel_atimdtim.mutex); -#endif -#ifdef CONFIG_PROTSEL_MACSLEEP - _rtw_mutex_free(&pdvobj->protsel_macsleep.mutex); -#endif _rtw_mutex_free(&pdvobj->setch_mutex); _rtw_mutex_free(&pdvobj->setbw_mutex); _rtw_mutex_free(&pdvobj->rf_read_reg_mutex); _rtw_mutex_free(&pdvobj->ioctrl_mutex); -#ifdef CONFIG_SDIO_INDIRECT_ACCESS - _rtw_mutex_free(&pdvobj->sd_indirect_access_mutex); -#endif -#ifdef CONFIG_SYSON_INDIRECT_ACCESS - _rtw_mutex_free(&pdvobj->syson_indirect_access_mutex); -#endif - - rtw_macid_ctl_deinit(&pdvobj->macid_ctl); -#ifdef CONFIG_CLIENT_PORT_CFG - rtw_clt_port_deinit(&pdvobj->clt_port); -#endif + /* move to phl */ + /* rtw_macid_ctl_deinit(&pdvobj->macid_ctl); */ _rtw_spinlock_free(&pdvobj->cam_ctl.lock); _rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex); -#if defined(CONFIG_PLATFORM_RTK129X) && defined(CONFIG_PCI_HCI) +#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI) _rtw_spinlock_free(&pdvobj->io_reg_lock); #endif -#ifdef CONFIG_MBSSID_CAM - rtw_mbid_cam_deinit(pdvobj); -#endif -#ifdef CONFIG_SUPPORT_MULTI_BCN - _rtw_spinlock_free(&(pdvobj->ap_if_q.lock)); -#endif + rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj)); } @@ -2797,15 +1120,15 @@ u8 rtw_reset_drv_sw(_adapter *padapter) struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); /* hal_priv */ - rtw_hal_def_value_init(padapter); + rtw_hw_cap_init(adapter_to_dvobj(padapter)); - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_RX_BIT); + RTW_ENABLE_FUNC(adapter_to_dvobj(padapter), DF_TX_BIT); padapter->bLinkInfoDump = 0; padapter->xmitpriv.tx_pkts = 0; - padapter->recvpriv.rx_pkts = 0; + padapter->recvinfo.rx_pkts = 0; pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; @@ -2824,124 +1147,193 @@ u8 rtw_reset_drv_sw(_adapter *padapter) /* mlmeextpriv */ mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE); -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_set_signal_stat_timer(&padapter->recvpriv); -#endif - + #ifdef CONFIG_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvinfo); + #endif return ret8; } - -u8 rtw_init_drv_sw(_adapter *padapter) +static int devobj_set_phl_regulation_capability(struct dvobj_priv *dvobj) { - u8 ret8 = _SUCCESS; - -#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + bool band_2g = _FALSE; +#if CONFIG_IEEE80211_BAND_5GHZ + bool band_5g = _FALSE; +#endif +#if CONFIG_IEEE80211_BAND_6GHZ + bool band_6g = _FALSE; #endif + enum rtw_regulation_capability phl_regd_cap = 0; + int ret = _FAIL; - #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) - _rtw_init_listhead(&padapter->list); - #ifdef CONFIG_FW_HANDLE_TXBCN - padapter->vap_id = CONFIG_LIMITED_AP_NUM; - if (is_primary_adapter(padapter)) - adapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt; - #endif - #endif + if (is_supported_24g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_2G)) + band_2g = _TRUE; - #ifdef CONFIG_CLIENT_PORT_CFG - padapter->client_id = MAX_CLIENT_PORT_NUM; - padapter->client_port = CLT_PORT_INVALID; - #endif +#if CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_5G)) + band_5g = _TRUE; +#endif - if (is_primary_adapter(padapter)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); - - dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT); - dvobj->macid_ctl.macid_cap = hal_spec->macid_cap; - dvobj->macid_ctl.macid_txrpt = hal_spec->macid_txrpt; - dvobj->macid_ctl.macid_txrpt_pgsz = hal_spec->macid_txrpt_pgsz; - dvobj->cam_ctl.sec_cap = hal_spec->sec_cap; - dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT); - - dvobj->wow_ctl.wow_cap = hal_spec->wow_cap; - - #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT - dvobj->tx_aval_int_thr_mode = 2; /*setting by max tx length*/ - dvobj->tx_aval_int_thr_value = 0; - #endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/ - - #if CONFIG_TX_AC_LIFETIME - { - struct registry_priv *regsty = adapter_to_regsty(padapter); - int i; - - dvobj->tx_aclt_flags = regsty->tx_aclt_flags; - for (i = 0; i < TX_ACLT_CONF_NUM; i++) { - dvobj->tx_aclt_confs[i].en = regsty->tx_aclt_confs[i].en; - dvobj->tx_aclt_confs[i].vo_vi - = regsty->tx_aclt_confs[i].vo_vi / (hal_spec->tx_aclt_unit_factor * 32); - if (dvobj->tx_aclt_confs[i].vo_vi > 0xFFFF) - dvobj->tx_aclt_confs[i].vo_vi = 0xFFFF; - dvobj->tx_aclt_confs[i].be_bk - = regsty->tx_aclt_confs[i].be_bk / (hal_spec->tx_aclt_unit_factor * 32); - if (dvobj->tx_aclt_confs[i].be_bk > 0xFFFF) - dvobj->tx_aclt_confs[i].be_bk = 0xFFFF; - } +#if CONFIG_IEEE80211_BAND_6GHZ + if (is_supported_6g(regsty->band_type) && rtw_hw_chk_band_cap(dvobj, BAND_CAP_6G)) + band_6g = _TRUE; +#endif - dvobj->tx_aclt_force_val.en = 0xFF; - } + if (band_2g == _FALSE + #if CONFIG_IEEE80211_BAND_5GHZ + && band_5g == _FALSE #endif - #if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC) - dvobj->sync_tsfr_counter = 0x0; + #if CONFIG_IEEE80211_BAND_6GHZ + && band_6g == _FALSE #endif + ) { + RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); + goto exit; } - ret8 = rtw_init_default_value(padapter); + if (band_2g) + phl_regd_cap |= CAPABILITY_2GHZ; + #if CONFIG_IEEE80211_BAND_5GHZ + if (band_5g) + phl_regd_cap |= CAPABILITY_5GHZ; + #endif + #if CONFIG_IEEE80211_BAND_6GHZ + if (band_6g) + phl_regd_cap |= CAPABILITY_6GHZ; + #endif + #if CONFIG_DFS + phl_regd_cap |= CAPABILITY_DFS; + #endif - if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) { - ret8 = _FAIL; + if (rtw_phl_regulation_set_capability(GET_PHL_INFO(dvobj), phl_regd_cap) != true) { + RTW_WARN("rtw_phl_regulation_set_capability() != true\n"); goto exit; } - padapter->cmdpriv.padapter = padapter; + ret = _SUCCESS; - if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) { - ret8 = _FAIL; +exit: + return ret; +} + +static void devobj_decide_init_chplan(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + struct dev_cap_t *dev_cap = &GET_PHL_COM(dvobj)->dev_cap; + const char *alpha2 = NULL; /* TODO */ + u8 chplan = dev_cap->domain; + u8 chplan_6g = RTW_CHPLAN_6G_NULL; /* TODO */ + bool disable_sw_chplan = _FALSE; /* TODO */ + + if (alpha2) + RTW_INFO("%s alpha2:{%d,%d}\n", __func__, alpha2[0], alpha2[1]); + RTW_INFO("%s chplan:0x%02x\n", __func__, chplan); + RTW_INFO("%s chplan_6g:0x%02x\n", __func__, chplan_6g); + RTW_INFO("%s disable_sw_chplan:%d\n", __func__, disable_sw_chplan); + + /* + * treat {0xFF, 0xFF} as unspecified + */ + if (alpha2 && strncmp(alpha2, "\xFF\xFF", 2) == 0) + alpha2 = NULL; + +#ifdef CONFIG_FORCE_SW_CHANNEL_PLAN + disable_sw_chplan = _FALSE; +#endif + + rtw_rfctl_decide_init_chplan(rfctl, alpha2, chplan, chplan_6g, disable_sw_chplan); +} + +u8 devobj_data_init(struct dvobj_priv *dvobj) +{ + u8 ret = _FAIL; + + dev_set_drv_stopped(dvobj);/*init*/ + dev_clr_hw_start(dvobj); /* init */ + + /*init data of dvobj*/ + if (devobj_set_phl_regulation_capability(dvobj) != _SUCCESS) + goto exit; + + devobj_decide_init_chplan(dvobj); + + if (rtw_rfctl_init(dvobj) == _FAIL) + goto exit; + + rtw_edcca_mode_update(dvobj); + rtw_update_phl_edcca_mode(dvobj_get_primary_adapter(dvobj)); + rtw_rfctl_chplan_init(dvobj); + rtw_hw_cap_init(dvobj); + + RTW_ENABLE_FUNC(dvobj, DF_RX_BIT); + RTW_ENABLE_FUNC(dvobj, DF_TX_BIT); + + ret = _SUCCESS; + +exit: + return ret; +} + + +void devobj_data_deinit(struct dvobj_priv *dvobj) +{ +} + +u8 devobj_trx_resource_init(struct dvobj_priv *dvobj) +{ + u8 ret = _SUCCESS; + +#ifdef CONFIG_USB_HCI + ret = rtw_init_lite_xmit_resource(dvobj); + if (ret == _FAIL) + goto exit; + ret = rtw_init_lite_recv_resource(dvobj); + if (ret == _FAIL) + goto exit; +#endif + ret = rtw_init_recv_priv(dvobj); + if (ret == _FAIL) { + RTW_ERR("%s rtw_init_recv_priv failed\n", __func__); goto exit; } - if (is_primary_adapter(padapter)) { - if (rtw_hal_rfpath_init(padapter) == _FAIL) { - ret8 = _FAIL; - goto exit; - } - if (rtw_hal_trxnss_init(padapter) == _FAIL) { - ret8 = _FAIL; - goto exit; - } - if (rtw_hal_runtime_trx_path_decision(padapter) == _FAIL) { - ret8 = _FAIL; - goto exit; - } - if (rtw_rfctl_init(padapter) == _FAIL) { - ret8 = _FAIL; - goto exit; - } + ret = rtw_init_cmd_priv(dvobj); + if (ret == _FAIL) { + RTW_ERR("%s rtw_init_cmd_priv failed\n", __func__); + goto exit; } +exit: + return ret; +} + + +void devobj_trx_resource_deinit(struct dvobj_priv *dvobj) +{ +#ifdef CONFIG_USB_HCI + rtw_free_lite_xmit_resource(dvobj); + rtw_free_lite_recv_resource(dvobj); +#endif + rtw_free_recv_priv(dvobj); + rtw_free_cmd_priv(dvobj); +} + + +u8 rtw_init_drv_sw(_adapter *padapter) +{ + u8 ret8 = _SUCCESS; + +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif + + ret8 = rtw_init_default_value(padapter);/*load registrypriv value*/ if (rtw_init_mlme_priv(padapter) == _FAIL) { ret8 = _FAIL; goto exit; } -#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) - rtw_init_roch_info(padapter); -#endif - #ifdef CONFIG_P2P - rtw_init_wifidirect_timers(padapter); init_wifidirect_info(padapter, P2P_ROLE_DISABLE); reset_global_wifidirect_info(padapter); #ifdef CONFIG_WFD @@ -2972,12 +1364,12 @@ u8 rtw_init_drv_sw(_adapter *padapter) ret8 = _FAIL; goto exit; } - - if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) { - RTW_INFO("Can't _rtw_init_recv_priv\n"); + if (rtw_init_recv_info(padapter) == _FAIL) { + RTW_INFO("Can't rtw_init_recv_info\n"); ret8 = _FAIL; goto exit; } + /* add for CONFIG_IEEE80211W, none 11w also can use */ _rtw_spinlock_init(&padapter->security_key_mutex); @@ -2991,7 +1383,7 @@ u8 rtw_init_drv_sw(_adapter *padapter) } padapter->setband = WIFI_FREQUENCY_BAND_AUTO; - padapter->fix_rate = 0xFF; + padapter->fix_rate = NO_FIX_RATE; padapter->power_offset = 0; padapter->rsvd_page_offset = 0; padapter->rsvd_page_num = 0; @@ -3005,29 +1397,14 @@ u8 rtw_init_drv_sw(_adapter *padapter) padapter->drv_rx_cnt_crcerror = 0; padapter->drv_rx_cnt_drop = 0; #endif - rtw_init_bcmc_stainfo(padapter); rtw_init_pwrctrl_priv(padapter); +#ifdef CONFIG_WOWLAN + rtw_init_wow(padapter); +#endif /* CONFIG_WOWLAN */ /* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */ -#ifdef CONFIG_MP_INCLUDED - if (init_mp_priv(padapter) == _FAIL) - RTW_INFO("%s: initialize MP private data Fail!\n", __func__); -#endif - - rtw_hal_dm_init(padapter); - - if (is_primary_adapter(padapter)) - rtw_rfctl_chplan_init(padapter); - -#ifdef CONFIG_RTW_SW_LED - rtw_hal_sw_led_init(padapter); -#endif -#ifdef DBG_CONFIG_ERROR_DETECT - rtw_hal_sreset_init(padapter); -#endif - #ifdef CONFIG_WAPI_SUPPORT padapter->WapiSupport = true; /* set true temp, will revise according to Efuse or Registry value later. */ rtw_wapi_init(padapter); @@ -3037,27 +1414,20 @@ u8 rtw_init_drv_sw(_adapter *padapter) _rtw_spinlock_init(&padapter->br_ext_lock); #endif /* CONFIG_BR_EXT */ -#ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 - rtw_bf_init(padapter); -#endif /* RTW_BEAMFORMING_VERSION_2 */ -#endif /* CONFIG_BEAMFORMING */ - -#ifdef CONFIG_RTW_REPEATER_SON - init_rtw_rson_data(adapter_to_dvobj(padapter)); -#endif - #ifdef CONFIG_RTW_80211K rtw_init_rm(padapter); #endif #ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI - memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN); + _rtw_memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN); #endif -exit: - +#ifdef CONFIG_STA_CMD_DISPR + rtw_connect_req_init(padapter); + rtw_disconnect_req_init(padapter); +#endif /* CONFIG_STA_CMD_DISPR */ +exit: return ret8; @@ -3066,14 +1436,17 @@ u8 rtw_init_drv_sw(_adapter *padapter) #ifdef CONFIG_WOWLAN void rtw_cancel_dynamic_chk_timer(_adapter *padapter) { + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); + #endif } #endif void rtw_cancel_all_timer(_adapter *padapter) { - _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); + /*_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);*/ + cancel_assoc_timer(&padapter->mlmepriv); _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); @@ -3081,13 +1454,17 @@ void rtw_cancel_all_timer(_adapter *padapter) _cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer); #endif + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); - _cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer); + #endif + #ifdef CONFIG_RTW_SW_LED /* cancel sw led timer */ rtw_hal_sw_led_deinit(padapter); #endif +#ifdef CONFIG_POWER_SAVING _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); +#endif #ifdef CONFIG_TX_AMSDU _cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer); @@ -3096,31 +1473,22 @@ void rtw_cancel_all_timer(_adapter *padapter) _cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer); #endif -#ifdef CONFIG_IOCTL_CFG80211 - _cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer); -#endif /* CONFIG_IOCTL_CFG80211 */ - #ifdef CONFIG_SET_SCAN_DENY_TIMER _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer); rtw_clear_scan_deny(padapter); #endif - -#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); +#ifdef CONFIG_SIGNAL_STAT_PROCESS + _cancel_timer_ex(&padapter->recvinfo.signal_stat_timer); #endif - #ifdef CONFIG_LPS_RPWM_TIMER _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer)); #endif /* CONFIG_LPS_RPWM_TIMER */ -#ifdef CONFIG_RTW_TOKEN_BASED_XMIT +#ifdef CONFIG_RTW_TOKEN_BASED_XMIT _cancel_timer_ex(&padapter->mlmeextpriv.tbtx_xmit_timer); _cancel_timer_ex(&padapter->mlmeextpriv.tbtx_token_dispatch_timer); #endif - /* cancel dm timer */ - rtw_hal_dm_deinit(padapter); - #ifdef CONFIG_PLATFORM_FS_MX61 msleep(50); #endif @@ -3139,17 +1507,8 @@ u8 rtw_free_drv_sw(_adapter *padapter) #ifdef CONFIG_P2P { struct wifidirect_info *pwdinfo = &padapter->wdinfo; - #ifdef CONFIG_CONCURRENT_MODE - struct roch_info *prochinfo = &padapter->rochinfo; - #endif - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - _cancel_timer_ex(&pwdinfo->find_phase_timer); - _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); - _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); - #ifdef CONFIG_CONCURRENT_MODE - _cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer); - #endif /* CONFIG_CONCURRENT_MODE */ - rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DISABLE)) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); } } #endif @@ -3170,14 +1529,14 @@ u8 rtw_free_drv_sw(_adapter *padapter) rtw_free_rm_priv(padapter); #endif - rtw_free_cmd_priv(&padapter->cmdpriv); - - rtw_free_evt_priv(&padapter->evtpriv); - rtw_free_mlme_priv(&padapter->mlmepriv); +#ifdef CONFIG_STA_CMD_DISPR + rtw_connect_req_free(padapter); + rtw_disconnect_req_free(padapter); +#endif /* CONFIG_STA_CMD_DISPR */ if (is_primary_adapter(padapter)) - rtw_rfctl_deinit(padapter); + rtw_rfctl_deinit(adapter_to_dvobj(padapter)); /* free_io_queue(padapter); */ @@ -3185,185 +1544,74 @@ u8 rtw_free_drv_sw(_adapter *padapter) _rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */ - _rtw_free_recv_priv(&padapter->recvpriv); - rtw_free_pwrctrl_priv(padapter); - -#ifdef CONFIG_PLATFORM_CMAP_INTFS - if (padapter->cmap_bss_status_evt) { - cmap_intfs_mfree(padapter->cmap_bss_status_evt, padapter->cmap_bss_status_evt_len); - padapter->cmap_bss_status_evt = NULL; - } -#endif +#ifdef CONFIG_WOWLAN + rtw_free_wow(padapter); +#endif /* CONFIG_WOWLAN */ /* rtw_mfree((void *)padapter, sizeof (padapter)); */ - rtw_hal_free_data(padapter); - return _SUCCESS; } -void rtw_intf_start(_adapter *adapter) -{ - if (adapter->intf_start) - adapter->intf_start(adapter); - GET_HAL_DATA(adapter)->intf_start = 1; -} -void rtw_intf_stop(_adapter *adapter) -{ - if (adapter->intf_stop) - adapter->intf_stop(adapter); - GET_HAL_DATA(adapter)->intf_start = 0; -} - -#ifdef CONFIG_CONCURRENT_MODE -#ifndef CONFIG_NEW_NETDEV_HDL -int _netdev_vir_if_open(struct net_device *pnetdev) +void rtw_drv_stop_prim_iface(_adapter *adapter) { - _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); - _adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter); - - RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - - if (!primary_padapter) - goto _netdev_virtual_iface_open_error; - -#ifdef CONFIG_PLATFORM_INTEL_BYT - if (padapter->bup == _FALSE) { - u8 mac[ETH_ALEN]; - - /* get mac address from primary_padapter */ - if (primary_padapter->bup == _FALSE) - rtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter)); - - _rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN); - - /* - * If the BIT1 is 0, the address is universally administered. - * If it is 1, the address is locally administered - */ - mac[0] |= BIT(1); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - _rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + rtw_disassoc_cmd(adapter, 0, RTW_CMDF_DIRECTLY|RTW_CMDF_WAIT_ACK); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter)); -#endif - rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); - _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); +#ifdef CONFIG_AP_MODE + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { + free_mlme_ap_info(adapter); + #ifdef CONFIG_HOSTAPD_MLME + hostapd_mode_unload(adapter); + #endif } -#endif /*CONFIG_PLATFORM_INTEL_BYT*/ - - if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter)) - _netdev_open(primary_padapter->pnetdev); - - if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE && - rtw_is_hw_init_completed(primary_padapter)) { -#if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ - rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ #endif - } - - if (padapter->bup == _FALSE) { - if (rtw_start_drv_threads(padapter) == _FAIL) - goto _netdev_virtual_iface_open_error; - } + RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); -#ifdef CONFIG_RTW_NAPI - if (padapter->napi_state == NAPI_DISABLE) { - napi_enable(&padapter->napi); - padapter->napi_state = NAPI_ENABLE; + if (adapter->netif_up == _TRUE) { + #ifdef CONFIG_XMIT_ACK + if (adapter->xmitpriv.ack_tx) + rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); + #endif + rtw_hw_iface_deinit(adapter); + if (!pwrctl->bInSuspend) + adapter->netif_up = _FALSE; } -#endif + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ + rtw_stop_drv_threads(adapter); -#ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_init_wdev_data(padapter); -#endif - - padapter->bup = _TRUE; - - padapter->net_closed = _FALSE; - - rtw_netif_wake_queue(pnetdev); - - RTW_INFO(FUNC_NDEV_FMT" (bup=%d) exit\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - - return 0; - -_netdev_virtual_iface_open_error: - - padapter->bup = _FALSE; - -#ifdef CONFIG_RTW_NAPI - if(padapter->napi_state == NAPI_ENABLE) { - napi_disable(&padapter->napi); - padapter->napi_state = NAPI_DISABLE; + if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { + RTW_ERR("cmd_thread not stop !!\n"); + rtw_warn_on(1); } -#endif - - rtw_netif_carrier_off(pnetdev); - rtw_netif_stop_queue(pnetdev); - - return -1; - -} - -int netdev_vir_if_open(struct net_device *pnetdev) -{ - int ret; - _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); - - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); - ret = _netdev_vir_if_open(pnetdev); - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); - -#ifdef CONFIG_AUTO_AP_MODE - /* if(padapter->iface_id == 2) */ - /* rtw_start_auto_ap(padapter); */ -#endif - - return ret; -} - -static int netdev_vir_if_close(struct net_device *pnetdev) -{ - _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - padapter->net_closed = _TRUE; - pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; - - if (pnetdev) - rtw_netif_stop_queue(pnetdev); + #endif -#ifdef CONFIG_P2P - if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE)) - rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); -#endif + /* check the status of IPS */ + if (rtw_hal_check_ips_status(adapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */ + RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__); + pdbgpriv->dbg_dev_unload_inIPS_cnt++; + } else + RTW_PRINT("%s: driver not in IPS\n", __func__); -#ifdef CONFIG_IOCTL_CFG80211 - rtw_scan_abort(padapter); - rtw_cfg80211_wait_scan_req_empty(padapter, 200); - adapter_wdev_data(padapter)->bandroid_scan = _FALSE; -#endif + rtw_cancel_all_timer(adapter); + RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); - return 0; } -#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/ +#ifdef CONFIG_CONCURRENT_MODE #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) static const struct net_device_ops rtw_netdev_vir_if_ops = { .ndo_init = rtw_ndev_init, .ndo_uninit = rtw_ndev_uninit, - #ifdef CONFIG_NEW_NETDEV_HDL .ndo_open = netdev_open, .ndo_stop = netdev_close, - #else - .ndo_open = netdev_vir_if_open, - .ndo_stop = netdev_vir_if_close, - #endif .ndo_start_xmit = rtw_xmit_entry, .ndo_set_mac_address = rtw_net_set_mac_address, .ndo_get_stats = rtw_net_get_stats, @@ -3381,26 +1629,21 @@ static void rtw_hook_vir_if_ops(struct net_device *ndev) #else ndev->init = rtw_ndev_init; ndev->uninit = rtw_ndev_uninit; - #ifdef CONFIG_NEW_NETDEV_HDL ndev->open = netdev_open; ndev->stop = netdev_close; - #else - ndev->open = netdev_vir_if_open; - ndev->stop = netdev_vir_if_close; - #endif ndev->set_mac_address = rtw_net_set_mac_address; #endif } -_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, - void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)) +static _adapter *rtw_drv_add_vir_if(struct dvobj_priv *dvobj) { int res = _FAIL; _adapter *padapter = NULL; - struct dvobj_priv *pdvobjpriv; + _adapter *primary_padapter = dvobj_get_primary_adapter(dvobj); u8 mac[ETH_ALEN]; #ifdef CONFIG_MI_UNIQUE_MACADDR_BIT u32 mi_unique_macaddr_bit = 0; + bool is_uniq_macaddr = _FALSE; u8 i; #endif @@ -3409,14 +1652,17 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, if (padapter == NULL) goto exit; - if (loadparam(padapter) != _SUCCESS) - goto free_adapter; - _rtw_memcpy(padapter, primary_padapter, sizeof(_adapter)); +#ifdef CONFIG_STA_CMD_DISPR + /* Reset not proper variables value which copied from primary adapter */ + /* Check rtw_connect_req_init() & rtw_disconnect_req_init() */ + padapter->connect_state = CONNECT_ST_NOT_READY; +#endif + + if (rtw_load_registry(padapter) != _SUCCESS) + goto free_adapter; - /* */ - padapter->bup = _FALSE; - padapter->net_closed = _TRUE; + padapter->netif_up = _FALSE; padapter->dir_dev = NULL; padapter->dir_odm = NULL; @@ -3424,27 +1670,11 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, padapter->isprimary = _FALSE; padapter->adapter_type = VIRTUAL_ADAPTER; -#ifdef CONFIG_MI_WITH_MBSSID_CAM - padapter->hw_port = HW_PORT0; -#elif defined(CONFIG_PORT_BASED_TXBCN) - padapter->hw_port = adapter_to_dvobj(padapter)->iface_nums; -#else padapter->hw_port = HW_PORT1; -#endif - /****** hook vir if into dvobj ******/ - pdvobjpriv = adapter_to_dvobj(padapter); - padapter->iface_id = pdvobjpriv->iface_nums; - pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter; - - padapter->intf_start = primary_padapter->intf_start; - padapter->intf_stop = primary_padapter->intf_stop; - - /* step init_io_priv */ - if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) { - goto free_adapter; - } + padapter->iface_id = dvobj->iface_nums; + dvobj->padapters[dvobj->iface_nums++] = padapter; /*init drv data*/ if (rtw_init_drv_sw(padapter) != _SUCCESS) @@ -3457,15 +1687,19 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, #ifdef CONFIG_MI_UNIQUE_MACADDR_BIT mi_unique_macaddr_bit = BIT(CONFIG_MI_UNIQUE_MACADDR_BIT) >> 24; /* Find out CONFIG_MI_UNIQUE_MACADDR_BIT in which nic specific byte */ - for(i=3;i<6;i++) { - if((mi_unique_macaddr_bit >> 8) == 0) - break; + for(i = 3; i < 6; i++) { + if(((mi_unique_macaddr_bit >> 8) == 0) && + ((mac[i] & (u8)mi_unique_macaddr_bit) == 0)) { + is_uniq_macaddr = _TRUE; + RTW_INFO("%s() "MAC_FMT" : BIT%u is zero\n", + __func__, MAC_ARG(mac), CONFIG_MI_UNIQUE_MACADDR_BIT); + break; + } mi_unique_macaddr_bit >>= 8; } - if((mac[i] & (u8)mi_unique_macaddr_bit)== 0) { - RTW_INFO("%s() "MAC_FMT" : BIT%u is zero\n", __func__, MAC_ARG(mac), CONFIG_MI_UNIQUE_MACADDR_BIT); + if(is_uniq_macaddr) { /* IFACE_ID1/IFACE_ID3 : set locally administered bit */ if(padapter->iface_id & BIT(0)) mac[0] |= BIT(1); @@ -3475,24 +1709,18 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, } else #endif { - /* - * If the BIT1 is 0, the address is universally administered. - * If it is 1, the address is locally administered - */ - mac[0] |= BIT(1); - if (padapter->iface_id > IFACE_ID1) - mac[0] ^= ((padapter->iface_id)<<2); + /* + * If the BIT1 is 0, the address is universally administered. + * If it is 1, the address is locally administered + */ + mac[0] |= BIT(1); + if (padapter->iface_id > IFACE_ID1) + mac[0] ^= ((padapter->iface_id) << 2); } _rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN); - /* update mac-address to mbsid-cam cache*/ -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter)); -#endif + RTW_INFO("%s if%d mac_addr : "MAC_FMT"\n", __func__, padapter->iface_id + 1, MAC_ARG(adapter_mac_addr(padapter))); -#ifdef CONFIG_P2P - rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); -#endif rtw_led_set_ctl_en_mask_virtual(padapter); rtw_led_set_iface_en(padapter, 1); @@ -3510,11 +1738,30 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, exit: return padapter; } +u8 rtw_drv_add_vir_ifaces(struct dvobj_priv *dvobj) +{ + u8 i; + u8 rst = _FAIL; + + if (dvobj->virtual_iface_num > (CONFIG_IFACE_NUMBER - 1)) + dvobj->virtual_iface_num = (CONFIG_IFACE_NUMBER - 1); + + for (i = 0; i < dvobj->virtual_iface_num; i++) { + if (rtw_drv_add_vir_if(dvobj) == NULL) { + RTW_ERR("rtw_drv_add_vir_if failed! (%d)\n", i); + goto _exit; + } + } + rst = _SUCCESS; +_exit: + return rst; +} -void rtw_drv_stop_vir_if(_adapter *padapter) +static void rtw_drv_stop_vir_if(_adapter *padapter) { struct net_device *pnetdev = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); if (padapter == NULL) return; @@ -3522,8 +1769,8 @@ void rtw_drv_stop_vir_if(_adapter *padapter) pnetdev = padapter->pnetdev; - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) - rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY|RTW_CMDF_WAIT_ACK); #ifdef CONFIG_AP_MODE if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { @@ -3534,26 +1781,30 @@ void rtw_drv_stop_vir_if(_adapter *padapter) } #endif - if (padapter->bup == _TRUE) { + if (padapter->netif_up == _TRUE) { #ifdef CONFIG_XMIT_ACK if (padapter->xmitpriv.ack_tx) rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); #endif - - rtw_intf_stop(padapter); - #ifndef CONFIG_NEW_NETDEV_HDL - rtw_stop_drv_threads(padapter); - #endif - padapter->bup = _FALSE; + rtw_hw_iface_deinit(padapter); + if (!pwrctl->bInSuspend) + padapter->netif_up = _FALSE; } - #ifdef CONFIG_NEW_NETDEV_HDL + #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ rtw_stop_drv_threads(padapter); #endif /* cancel timer after thread stop */ rtw_cancel_all_timer(padapter); } +void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj) +{ + int i; + + for (i = VIF_START_ID; i < dvobj->iface_nums; i++) + rtw_drv_stop_vir_if(dvobj->padapters[i]); +} -void rtw_drv_free_vir_if(_adapter *padapter) +static void rtw_drv_free_vir_if(_adapter *padapter) { if (padapter == NULL) return; @@ -3566,16 +1817,6 @@ void rtw_drv_free_vir_if(_adapter *padapter) rtw_vmfree((u8 *)padapter, sizeof(_adapter)); } - - -void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj) -{ - int i; - - for (i = VIF_START_ID; i < dvobj->iface_nums; i++) - rtw_drv_stop_vir_if(dvobj->padapters[i]); -} - void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj) { int i; @@ -3672,7 +1913,7 @@ static int rtw_inet6addr_notifier_call(struct notifier_block *nb, RTW_IPv6_ADDR_LEN); RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__, pmlmeinfo->ip6_addr); - break; + break; case NETDEV_DOWN: #ifdef CONFIG_WOWLAN pwrctl->wowlan_ns_offload_en = _FALSE; @@ -3743,8 +1984,9 @@ int rtw_os_ndevs_register(struct dvobj_priv *dvobj) char *name; #ifdef CONFIG_RTW_DYNAMIC_NDEV - if (!is_primary_adapter(adapter)) - continue; + if (!is_primary_adapter(adapter) && + (i >= CONFIG_RTW_STATIC_NDEV_NUM)) + break; #endif if (adapter->iface_id == IFACE_ID0) @@ -3855,7 +2097,7 @@ void netdev_br_init(struct net_device *netdev) br_netdev = rtw_get_bridge_ndev_by_name(CONFIG_BR_EXT_BRNAME); if (br_netdev) { - memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN); + _rtw_memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN); dev_put(br_netdev); RTW_INFO(FUNC_NDEV_FMT" bind bridge dev "NDEV_FMT"("MAC_FMT")\n" , FUNC_NDEV_ARG(netdev), NDEV_ARG(br_netdev), MAC_ARG(br_netdev->dev_addr)); @@ -3869,254 +2111,117 @@ void netdev_br_init(struct net_device *netdev) } #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) - rcu_read_unlock(); -#endif -} -#endif /* CONFIG_BR_EXT */ - -#ifdef CONFIG_NEW_NETDEV_HDL -int _netdev_open(struct net_device *pnetdev) -{ - uint status; - _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - - RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev)); - - if (!rtw_is_hw_init_completed(padapter)) { // ips - rtw_clr_surprise_removed(padapter); - rtw_clr_drv_stopped(padapter); - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); - status = rtw_hal_init(padapter); - if (status == _FAIL) - goto netdev_open_error; - rtw_led_control(padapter, LED_CTL_NO_LINK); - #ifndef RTW_HALMAC - status = rtw_mi_start_drv_threads(padapter); - if (status == _FAIL) { - RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev)); - goto netdev_open_error; - } - - rtw_intf_start(GET_PRIMARY_ADAPTER(padapter)); - #endif /* !RTW_HALMAC */ - - { - #ifdef CONFIG_BT_COEXIST_SOCKET_TRX - _adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter); - - if (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) { - rtw_btcoex_init_socket(prim_adpt); - prim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04; - rtw_btcoex_SetHciVersion(prim_adpt, 0x04); - } - #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); - - #ifndef CONFIG_IPS_CHECK_IN_WD - rtw_set_pwr_state_check_timer(pwrctrlpriv); - #endif /*CONFIG_IPS_CHECK_IN_WD*/ - } - - } - - /*if (padapter->bup == _FALSE) */ - { - rtw_hal_iface_init(padapter); - - #ifdef CONFIG_RTW_NAPI - if(padapter->napi_state == NAPI_DISABLE) { - napi_enable(&padapter->napi); - padapter->napi_state = NAPI_ENABLE; - } - #endif - - #ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_init_wdev_data(padapter); - #endif - /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ - rtw_netif_wake_queue(pnetdev); - - #ifdef CONFIG_BR_EXT - if (is_primary_adapter(padapter)) - netdev_br_init(pnetdev); - #endif /* CONFIG_BR_EXT */ - - - padapter->bup = _TRUE; - padapter->net_closed = _FALSE; - padapter->netif_up = _TRUE; - pwrctrlpriv->bips_processing = _FALSE; - } - - RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - return 0; - -netdev_open_error: - padapter->bup = _FALSE; - - #ifdef CONFIG_RTW_NAPI - if(padapter->napi_state == NAPI_ENABLE) { - napi_disable(&padapter->napi); - padapter->napi_state = NAPI_DISABLE; - } - #endif - - rtw_netif_carrier_off(pnetdev); - rtw_netif_stop_queue(pnetdev); - - RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - - return -1; - -} - -#else -int _netdev_open(struct net_device *pnetdev) -{ - uint status; - _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); - struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - - - RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); - - padapter->netif_up = _TRUE; - -#ifdef CONFIG_PLATFORM_INTEL_BYT - rtw_sdio_set_power(1); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ - - if (padapter->bup == _FALSE) { -#ifdef CONFIG_PLATFORM_INTEL_BYT - rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter)); -#endif - rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); - _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ - - rtw_clr_surprise_removed(padapter); - rtw_clr_drv_stopped(padapter); - - status = rtw_hal_init(padapter); - if (status == _FAIL) { - goto netdev_open_error; - } -#if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ - rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ -#endif - - RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); - -#ifndef RTW_HALMAC - status = rtw_start_drv_threads(padapter); - if (status == _FAIL) { - RTW_INFO("Initialize driver software resource Failed!\n"); - goto netdev_open_error; - } -#endif /* !RTW_HALMAC */ - -#ifdef CONFIG_RTW_NAPI - if(padapter->napi_state == NAPI_DISABLE) { - napi_enable(&padapter->napi); - padapter->napi_state = NAPI_ENABLE; - } -#endif - -#ifndef RTW_HALMAC - rtw_intf_start(padapter); -#endif /* !RTW_HALMAC */ - -#ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_init_wdev_data(padapter); + rcu_read_unlock(); #endif +} +#endif /* CONFIG_BR_EXT */ - rtw_led_control(padapter, LED_CTL_NO_LINK); +#if 0 +/*FPGA_test*/ +static int _drv_enable_trx(struct dvobj_priv *d) +{ + struct _ADAPTER *adapter; + u32 status; - padapter->bup = _TRUE; - pwrctrlpriv->bips_processing = _FALSE; -#ifdef CONFIG_PLATFORM_INTEL_BYT -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_IpsNotify(padapter, IPS_NONE); -#endif /* CONFIG_BT_COEXIST */ -#endif /* CONFIG_PLATFORM_INTEL_BYT */ + adapter = dvobj_get_primary_adapter(d); + if (adapter->netif_up == _FALSE) { + status = rtw_mi_start_drv_threads(adapter); + + if (status == _FAIL) { + RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__); + return -1; + } } - padapter->net_closed = _FALSE; - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); -#ifndef CONFIG_IPS_CHECK_IN_WD - rtw_set_pwr_state_check_timer(pwrctrlpriv); + return 0; +} #endif - /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ - rtw_netif_wake_queue(pnetdev); +static int _netdev_open(struct net_device *pnetdev) +{ + uint status; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); -#ifdef CONFIG_BR_EXT - netdev_br_init(pnetdev); -#endif /* CONFIG_BR_EXT */ -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) { - rtw_btcoex_init_socket(padapter); - padapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04; - rtw_btcoex_SetHciVersion(padapter, 0x04); - } else - RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n"); -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ + RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev)); -#ifdef CONFIG_CONCURRENT_MODE +#ifdef DIRTY_FOR_WORK + if(pnetdev->priv_flags & IFF_DONT_BRIDGE) { - _adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1]; + RTW_INFO("Unable to be bridged !! Unlock for this iface !!\n"); + pnetdev->priv_flags &= ~(IFF_DONT_BRIDGE); + } +#endif + + if (!dev_is_hw_start(dvobj)) { + dev_clr_surprise_removed(dvobj); + dev_clr_drv_stopped(dvobj); + RTW_ENABLE_FUNC(dvobj, DF_RX_BIT); + RTW_ENABLE_FUNC(dvobj, DF_TX_BIT); + status = rtw_hw_start(dvobj); + if (status == _FAIL) + goto netdev_open_error; + rtw_led_control(padapter, LED_CTL_NO_LINK); - #ifndef CONFIG_RTW_DYNAMIC_NDEV - if (sec_adapter && (sec_adapter->bup == _FALSE)) - _netdev_vir_if_open(sec_adapter->pnetdev); + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + if (0){ + _set_timer(&dvobj->dynamic_chk_timer, 2000); + } + #endif + #if 0 /*CONFIG_CORE_THREAD*/ + _drv_enable_trx(dvobj);/*FPGA_test*/ #endif } -#endif -#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS - pwrctrlpriv->radio_on_start_time = rtw_get_current_time(); - pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time(); - pwrctrlpriv->pwr_saving_time = 0; - pwrctrlpriv->on_time = 0; - pwrctrlpriv->tx_time = 0; - pwrctrlpriv->rx_time = 0; -#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + #ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_DISABLE) { + napi_enable(&padapter->napi); + padapter->napi_state = NAPI_ENABLE; + } + #endif + + if (padapter->netif_up == _FALSE) { + if (rtw_hw_iface_init(padapter) == _FAIL) { + rtw_warn_on(1); + goto netdev_open_error; + } + + /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ + rtw_netif_wake_queue(pnetdev); + + #ifdef CONFIG_BR_EXT + if (is_primary_adapter(padapter)) + netdev_br_init(pnetdev); + #endif /* CONFIG_BR_EXT */ - RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup); + padapter->netif_up = _TRUE; + } + RTW_INFO(FUNC_NDEV_FMT" Success (netif_up=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); return 0; netdev_open_error: + padapter->netif_up = _FALSE; - padapter->bup = _FALSE; - -#ifdef CONFIG_RTW_NAPI + #ifdef CONFIG_RTW_NAPI if(padapter->napi_state == NAPI_ENABLE) { napi_disable(&padapter->napi); padapter->napi_state = NAPI_DISABLE; } -#endif + #endif rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); - RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); + RTW_ERR(FUNC_NDEV_FMT" Failed!! (netif_up=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); return -1; } -#endif + int netdev_open(struct net_device *pnetdev) { int ret = _FALSE; @@ -4128,18 +2233,11 @@ int netdev_open(struct net_device *pnetdev) return 0; } - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); -#ifdef CONFIG_NEW_NETDEV_HDL + RTW_INFO(FUNC_NDEV_FMT" , netif_up=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); + /*rtw_dump_stack();*/ + _rtw_mutex_lock_interruptible(&(adapter_to_dvobj(padapter)->hw_init_mutex)); ret = _netdev_open(pnetdev); -#else - if (is_primary_adapter(padapter)) - ret = _netdev_open(pnetdev); -#ifdef CONFIG_CONCURRENT_MODE - else - ret = _netdev_vir_if_open(pnetdev); -#endif -#endif - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + _rtw_mutex_unlock(&(adapter_to_dvobj(padapter)->hw_init_mutex)); #ifdef CONFIG_AUTO_AP_MODE @@ -4155,45 +2253,36 @@ int ips_netdrv_open(_adapter *padapter) { int status = _SUCCESS; /* struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); */ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - padapter->net_closed = _FALSE; RTW_INFO("===> %s.........\n", __FUNCTION__); - rtw_clr_drv_stopped(padapter); - /* padapter->bup = _TRUE; */ -#ifdef CONFIG_NEW_NETDEV_HDL - if (!rtw_is_hw_init_completed(padapter)) { - status = rtw_hal_init(padapter); + dev_clr_drv_stopped(dvobj); + /* padapter->netif_up = _TRUE; */ + if (!rtw_hw_is_init_completed(dvobj)) { + status = rtw_hw_start(dvobj); if (status == _FAIL) { goto netdev_open_error; } rtw_mi_hal_iface_init(padapter); } -#else - status = rtw_hal_init(padapter); - if (status == _FAIL) { - goto netdev_open_error; - } -#endif #if 0 rtw_mi_set_mac_addr(padapter); #endif -#ifndef RTW_HALMAC - rtw_intf_start(padapter); -#endif /* !RTW_HALMAC */ -#ifndef CONFIG_IPS_CHECK_IN_WD +#if 0 /*ndef CONFIG_IPS_CHECK_IN_WD*/ rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); #endif - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); - + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + _set_timer(&dvobj->dynamic_chk_timer, 2000); + #endif return _SUCCESS; netdev_open_error: /* padapter->bup = _FALSE; */ - RTW_INFO("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup); + RTW_INFO("-ips_netdrv_open - drv_open failure, netif_up=%d\n", padapter->netif_up); return _FAIL; } @@ -4203,7 +2292,7 @@ int rtw_ips_pwr_up(_adapter *padapter) int result; #if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) #ifdef DBG_CONFIG_ERROR_DETECT - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(adapter_to_dvobj(padapter)); struct sreset_priv *psrtpriv = &pHalData->srestpriv; #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ #endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ @@ -4231,7 +2320,6 @@ void rtw_ips_pwr_down(_adapter *padapter) systime start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_down...................\n"); - padapter->net_closed = _TRUE; rtw_ips_dev_unload(padapter); RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); @@ -4241,7 +2329,7 @@ void rtw_ips_dev_unload(_adapter *padapter) { #if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) #ifdef DBG_CONFIG_ERROR_DETECT - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + HAL_DATA_TYPE *pHalData = GET_PHL_COM(adapter_to_dvobj(padapter)); struct sreset_priv *psrtpriv = &pHalData->srestpriv; #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ #endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ @@ -4255,69 +2343,56 @@ void rtw_ips_dev_unload(_adapter *padapter) #endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ { rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0); - rtw_intf_stop(padapter); } - if (!rtw_is_surprise_removed(padapter)) - rtw_hal_deinit(padapter); + if (!dev_is_surprise_removed(adapter_to_dvobj(padapter)) && + rtw_hw_is_init_completed(adapter_to_dvobj(padapter))) + rtw_hw_stop(adapter_to_dvobj(padapter)); } -#ifdef CONFIG_NEW_NETDEV_HDL + int _pm_netdev_open(_adapter *padapter) { uint status; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); struct net_device *pnetdev = padapter->pnetdev; RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev)); - if (!rtw_is_hw_init_completed(padapter)) { // ips - rtw_clr_surprise_removed(padapter); - rtw_clr_drv_stopped(padapter); - status = rtw_hal_init(padapter); + if (!rtw_hw_is_init_completed(dvobj)) { // ips + dev_clr_surprise_removed(dvobj); + dev_clr_drv_stopped(dvobj); + status = rtw_hw_start(dvobj); if (status == _FAIL) goto netdev_open_error; rtw_led_control(padapter, LED_CTL_NO_LINK); - #ifndef RTW_HALMAC - status = rtw_mi_start_drv_threads(padapter); - if (status == _FAIL) { - RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev)); - goto netdev_open_error; - } - - rtw_intf_start(GET_PRIMARY_ADAPTER(padapter)); - #endif /* !RTW_HALMAC */ - - { - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + _set_timer(&dvobj->dynamic_chk_timer, 2000); + #endif - #ifndef CONFIG_IPS_CHECK_IN_WD - rtw_set_pwr_state_check_timer(pwrctrlpriv); + #if 0 /*ndef CONFIG_IPS_CHECK_IN_WD*/ + rtw_set_pwr_state_check_timer(pwrctrlpriv); #endif /*CONFIG_IPS_CHECK_IN_WD*/ - } - } - /*if (padapter->bup == _FALSE) */ + /*if (padapter->netif_up == _FALSE) */ { - rtw_hal_iface_init(padapter); + rtw_hw_iface_init(padapter); - padapter->bup = _TRUE; - padapter->net_closed = _FALSE; padapter->netif_up = _TRUE; - pwrctrlpriv->bips_processing = _FALSE; } - RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + RTW_INFO(FUNC_NDEV_FMT" Success (netif_up=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); return 0; netdev_open_error: - padapter->bup = _FALSE; + padapter->netif_up = _FALSE; rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); - RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + RTW_ERR(FUNC_NDEV_FMT" Failed!! (netif_up=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); return -1; @@ -4343,7 +2418,7 @@ int _mi_pm_netdev_open(struct net_device *pnetdev) return status; } -#endif /*CONFIG_NEW_NETDEV_HDL*/ + int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) { int status = 0; @@ -4351,13 +2426,10 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); if (_TRUE == bnormal) { - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); - #ifdef CONFIG_NEW_NETDEV_HDL + _rtw_mutex_lock_interruptible(&(adapter_to_dvobj(padapter)->hw_init_mutex)); status = _mi_pm_netdev_open(pnetdev); - #else - status = _netdev_open(pnetdev); - #endif - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + + _rtw_mutex_unlock(&(adapter_to_dvobj(padapter)->hw_init_mutex)); } #ifdef CONFIG_IPS else @@ -4366,38 +2438,23 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) return status; } -#ifdef CONFIG_CLIENT_PORT_CFG -extern void rtw_hw_client_port_release(_adapter *adapter); -#endif + static int netdev_close(struct net_device *pnetdev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); -#ifndef CONFIG_PLATFORM_INTEL_BYT - padapter->net_closed = _TRUE; - padapter->netif_up = _FALSE; - pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + RTW_INFO(FUNC_NDEV_FMT" , netif_up=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->netif_up); -#ifdef CONFIG_CLIENT_PORT_CFG - if (MLME_IS_STA(padapter)) - rtw_hw_client_port_release(padapter); -#endif - /* if (!rtw_is_hw_init_completed(padapter)) { - RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE"); - rtw_set_drv_stopped(padapter); + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; - rtw_dev_unload(padapter); - } - else*/ if (pwrctl->rf_pwrstate == rf_on) { - RTW_INFO("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE"); + RTW_INFO("netif_up=%d, hw_init_completed=%s\n", + padapter->netif_up, + rtw_hw_is_init_completed(dvobj) ? "_TRUE" : "_FALSE"); /* s1. */ if (pnetdev) @@ -4406,14 +2463,26 @@ static int netdev_close(struct net_device *pnetdev) #ifndef CONFIG_RTW_ANDROID /* s2. */ LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); - /* s2-2. indicate disconnect to os */ - rtw_indicate_disconnect(padapter, 0, _FALSE); - /* s2-3. */ - rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); - /* s2-4. */ - rtw_free_network_queue(padapter, _TRUE); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); + /* s2-2*/ + if (1 +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); + /* s2-3. indicate disconnect to os */ + rtw_indicate_disconnect(padapter, 0, _FALSE); + /* s2-4. */ + rtw_free_network_queue(padapter, _TRUE); + } + #endif +#ifdef CONFIG_STA_CMD_DISPR + rtw_connect_abort_wait(padapter); + rtw_disconnect_abort_wait(padapter); +#endif /* CONFIG_STA_CMD_DISPR */ } #ifdef CONFIG_BR_EXT @@ -4429,44 +2498,27 @@ static int netdev_close(struct net_device *pnetdev) rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); #endif /* CONFIG_P2P */ - rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */ + rtw_scan_abort(padapter, 0); /* stop scanning process before wifi is going to down */ #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_wait_scan_req_empty(padapter, 200); - adapter_wdev_data(padapter)->bandroid_scan = _FALSE; /* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */ #endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_WAPI_SUPPORT rtw_wapi_disable_tx(padapter); #endif -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) - rtw_btcoex_close_socket(padapter); - else - RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n"); -#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ -#else /* !CONFIG_PLATFORM_INTEL_BYT */ - if (pwrctl->bInSuspend == _TRUE) { - RTW_INFO("+871x_drv - drv_close, bInSuspend=%d\n", pwrctl->bInSuspend); - return 0; +#ifdef CONFIG_RTW_NAPI + if (padapter->napi_state == NAPI_ENABLE) { + napi_disable(&padapter->napi); + padapter->napi_state = NAPI_DISABLE; } +#endif /* CONFIG_RTW_NAPI */ - rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */ -#ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_wait_scan_req_empty(padapter, 200); -#endif - - RTW_INFO("netdev_close, bips_processing=%d\n", pwrctl->bips_processing); - while (pwrctl->bips_processing == _TRUE) /* waiting for ips_processing done before call rtw_dev_unload() */ - rtw_msleep_os(1); - - rtw_dev_unload(padapter); - rtw_sdio_set_power(0); - -#endif /* !CONFIG_PLATFORM_INTEL_BYT */ + rtw_hw_iface_deinit(padapter); + padapter->netif_up = _FALSE; - RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup); + RTW_INFO("-871x_drv - drv_close, netif_up=%d\n", padapter->netif_up); return 0; @@ -4787,72 +2839,6 @@ int rtw_gw_addr_query(_adapter *padapter) } #endif -void rtw_dev_unload(PADAPTER padapter) -{ - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); - struct dvobj_priv *pobjpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - - if (padapter->bup == _TRUE) { - RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); - -#ifdef CONFIG_WOWLAN -#ifdef CONFIG_GPIO_WAKEUP - /*default wake up pin change to BT*/ - RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); - rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctl->wowlan_gpio_index, _FALSE); -#endif /* CONFIG_GPIO_WAKEUP */ -#endif /* CONFIG_WOWLAN */ - - rtw_set_drv_stopped(padapter); -#ifdef CONFIG_XMIT_ACK - if (padapter->xmitpriv.ack_tx) - rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); -#endif - - rtw_intf_stop(padapter); - - rtw_stop_drv_threads(padapter); - - if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { - RTW_ERR("cmd_thread not stop !!\n"); - rtw_warn_on(1); - } - - /* check the status of IPS */ - if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */ - RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__); - pdbgpriv->dbg_dev_unload_inIPS_cnt++; - } else - RTW_PRINT("%s: driver not in IPS\n", __func__); - - if (!rtw_is_surprise_removed(padapter)) { -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req); -#endif -#ifdef CONFIG_WOWLAN - if (pwrctl->bSupportRemoteWakeup == _TRUE && - pwrctl->wowlan_mode == _TRUE) - RTW_PRINT("%s bSupportRemoteWakeup==_TRUE do not run rtw_hal_deinit()\n", __FUNCTION__); - else -#endif - { - /* amy modify 20120221 for power seq is different between driver open and ips */ - rtw_hal_deinit(padapter); - } - rtw_set_surprise_removed(padapter); - } - - padapter->bup = _FALSE; - - RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); - } else { - RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__); - } - rtw_cancel_all_timer(padapter); -} - int rtw_suspend_free_assoc_resource(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -4863,16 +2849,12 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) - #ifdef CONFIG_P2P - && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) - #if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE - || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) - #endif - ) - #endif /* CONFIG_P2P */ - ) { + if (MLME_IS_STA(padapter) && + #ifdef CONFIG_P2P + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && + #endif /* CONFIG_P2P */ + check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, pmlmepriv->cur_network.network.Ssid.Ssid, MAC_ARG(pmlmepriv->cur_network.network.MacAddress), @@ -4882,19 +2864,26 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) } } - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { - rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); - /* s2-2. indicate disconnect to os */ - rtw_indicate_disconnect(padapter, 0, _FALSE); - } + if (MLME_IS_STA(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY|RTW_CMDF_WAIT_ACK); #ifdef CONFIG_AP_MODE else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) rtw_sta_flush(padapter, _TRUE); #endif - /* s2-3. */ - rtw_free_assoc_resources(padapter, _TRUE); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { + /* s2-2. */ + if (1 +#ifdef CONFIG_STA_CMD_DISPR + && (MLME_IS_STA(padapter) == _FALSE) +#endif /* CONFIG_STA_CMD_DISPR */ + ) + rtw_free_assoc_resources(padapter, _TRUE); + /* s2-3. indicate disconnect to os */ + if (MLME_IS_STA(padapter)) + rtw_indicate_disconnect(padapter, 0, _FALSE); + } /* s2-4. */ rtw_free_network_queue(padapter, _TRUE); @@ -4918,14 +2907,9 @@ int rtw_suspend_wow(_adapter *padapter) { u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct wowlan_ioctl_param poidparam; int ret = _SUCCESS; - u8 en = _TRUE, i; - struct registry_priv *registry_par = &padapter->registrypriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -4942,70 +2926,10 @@ int rtw_suspend_wow(_adapter *padapter) rtw_mi_buddy_netif_carrier_off(padapter); #endif - /* 0. Power off LED */ - rtw_led_control(padapter, LED_CTL_POWER_OFF); - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - /* 2.only for SDIO disable interrupt */ - rtw_intf_stop(padapter); - - /* 2.1 clean interrupt */ - rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ - - /* enable ac lifetime during scan to avoid txfifo not empty. */ - dvobj->lifetime_en = rtw_read8(padapter, 0x426); - dvobj->pkt_lifetime = rtw_read32(padapter, 0x4c0); - rtw_write8(padapter, 0x426, rtw_read8(padapter, 0x426) | 0x0f); - if(hal_spec->tx_aclt_unit_factor == 1) { - rtw_write16(padapter, 0x4c0, 0x1000); // unit: 32us. 131ms - rtw_write16(padapter, 0x4c0 + 2 , 0x1000); // unit: 32us. 131ms - } else { - rtw_write16(padapter, 0x4c0, 0x0200); // unit: 256us. 131ms - rtw_write16(padapter, 0x4c0 + 2 , 0x0200); // unit: 256us. 131ms - } - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && rtw_is_adapter_up(iface)) { - rtw_write_port_cancel(iface); - RTW_INFO(ADPT_FMT " write port cancel\n", ADPT_ARG(iface)); - } - } - RTW_INFO("lifetime_en=%x, pkt_lifetime=%x\n", rtw_read8(padapter, 0x426), rtw_read32(padapter, 0x4c0)); - rtw_msleep_os(200); - - /* 1. stop thread */ - rtw_set_drv_stopped(padapter); /*for stop thread*/ - rtw_mi_stop_drv_threads(padapter); - - rtw_clr_drv_stopped(padapter); /*for 32k command*/ + rtw_hw_wow(padapter, _TRUE); - /* #ifdef CONFIG_LPS */ - /* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */ - /* #endif */ - - #ifdef CONFIG_SDIO_HCI - /* 2.2 free irq */ - #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - sdio_free_irq(adapter_to_dvobj(padapter)); - #endif - #endif/*CONFIG_SDIO_HCI*/ - -#ifdef CONFIG_RUNTIME_PORT_SWITCH - if (rtw_port_switch_chk(padapter)) { - RTW_INFO(" ### PORT SWITCH ###\n"); - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); - } -#endif - if(registry_par->suspend_type == FW_IPS_WRC) - rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en); -#ifdef CONFIG_LPS - rtw_wow_lps_level_decide(padapter, _TRUE); -#endif - poidparam.subcode = WOWLAN_ENABLE; - rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + if (MLME_IS_STA(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, pmlmepriv->cur_network.network.Ssid.Ssid, @@ -5025,38 +2949,31 @@ int rtw_suspend_wow(_adapter *padapter) clr_fwstate(pmlmepriv, WIFI_UNDER_SURVEY); } + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + rtw_sdio_free_irq(dvobj); + #endif + #endif/*CONFIG_SDIO_HCI*/ +#if 1 if (rtw_mi_check_status(padapter, MI_LINKED)) { ch = rtw_mi_get_union_chan(padapter); bw = rtw_mi_get_union_bw(padapter); offset = rtw_mi_get_union_offset(padapter); RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset); - set_channel_bwmode(padapter, ch, offset, bw); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); } - +#else + if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { + RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ch, bw, offset); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); + rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); + } +#endif #ifdef CONFIG_CONCURRENT_MODE rtw_mi_buddy_suspend_free_assoc_resource(padapter); #endif - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); -#endif - - if (pwrpriv->wowlan_pno_enable) { - RTW_PRINT("%s: pno: %d\n", __func__, - pwrpriv->wowlan_pno_enable); -#ifdef CONFIG_FWLPS_IN_IPS - rtw_set_fw_in_ips_mode(padapter, _TRUE); -#endif - } -#ifdef CONFIG_LPS - else { - if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) { - rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "WOWLAN"); - } - } -#endif /* #ifdef CONFIG_LPS */ - } else RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode); RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); @@ -5068,9 +2985,9 @@ int rtw_suspend_wow(_adapter *padapter) int rtw_suspend_ap_wow(_adapter *padapter) { u8 ch, bw, offset; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct wowlan_ioctl_param poidparam; int ret = _SUCCESS; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -5083,46 +3000,38 @@ int rtw_suspend_ap_wow(_adapter *padapter) /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); -#ifdef CONFIG_SDIO_HCI - /* 2.only for SDIO disable interrupt*/ - rtw_intf_stop(padapter); - - /* 2.1 clean interrupt */ - rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ /* 1. stop thread */ - rtw_set_drv_stopped(padapter); /*for stop thread*/ + dev_set_drv_stopped(dvobj); /*for stop thread*/ + #if 0 rtw_mi_stop_drv_threads(padapter); - rtw_clr_drv_stopped(padapter); /*for 32k command*/ + #endif + dev_clr_drv_stopped(dvobj); /*for 32k command*/ #ifdef CONFIG_SDIO_HCI /* 2.2 free irq */ #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - sdio_free_irq(adapter_to_dvobj(padapter)); + rtw_sdio_free_irq(dvobj); #endif #endif/*CONFIG_SDIO_HCI*/ -#ifdef CONFIG_RUNTIME_PORT_SWITCH - if (rtw_port_switch_chk(padapter)) { - RTW_INFO(" ### PORT SWITCH ###\n"); - rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); - } -#endif - rtw_wow_lps_level_decide(padapter, _TRUE); - poidparam.subcode = WOWLAN_AP_ENABLE; - rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); - RTW_PRINT("%s: wowmode suspending\n", __func__); - +#if 1 if (rtw_mi_check_status(padapter, MI_LINKED)) { ch = rtw_mi_get_union_chan(padapter); bw = rtw_mi_get_union_bw(padapter); offset = rtw_mi_get_union_offset(padapter); RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset); - set_channel_bwmode(padapter, ch, offset, bw); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); + } +#else + if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { + RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); + rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); } +#endif /*FOR ONE AP - TODO :Multi-AP*/ { @@ -5140,12 +3049,8 @@ int rtw_suspend_ap_wow(_adapter *padapter) } -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); -#endif - #ifdef CONFIG_LPS - if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) { + if(pwrpriv->wowlan_power_mgmt != PM_PS_MODE_ACTIVE) { rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "AP-WOWLAN"); } #endif @@ -5153,7 +3058,7 @@ int rtw_suspend_ap_wow(_adapter *padapter) RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); return ret; } -#endif /* CONFIG_AP_WOWLAN */ +#endif /* #ifdef CONFIG_AP_WOWLAN */ int rtw_suspend_normal(_adapter *padapter) @@ -5162,9 +3067,6 @@ int rtw_suspend_normal(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND); -#endif rtw_mi_netif_caroff_qstop(padapter); rtw_mi_suspend_free_assoc_resource(padapter); @@ -5175,19 +3077,24 @@ int rtw_suspend_normal(_adapter *padapter) || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__); - -#ifdef CONFIG_CONCURRENT_MODE - rtw_set_drv_stopped(padapter); /*for stop thread*/ + dev_set_drv_stopped(adapter_to_dvobj(padapter)); /*for stop thread*/ +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ rtw_stop_cmd_thread(padapter); +#endif +#ifdef CONFIG_CONCURRENT_MODE rtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter)); #endif - rtw_dev_unload(padapter); + rtw_drv_stop_prim_iface(padapter); + + if (rtw_hw_is_init_completed(adapter_to_dvobj(padapter))) + rtw_hw_stop(adapter_to_dvobj(padapter)); + dev_set_surprise_removed(adapter_to_dvobj(padapter)); #ifdef CONFIG_SDIO_HCI - sdio_deinit(adapter_to_dvobj(padapter)); + rtw_sdio_deinit(adapter_to_dvobj(padapter)); #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - sdio_free_irq(adapter_to_dvobj(padapter)); + rtw_sdio_free_irq(adapter_to_dvobj(padapter)); #endif #endif /*CONFIG_SDIO_HCI*/ @@ -5215,26 +3122,14 @@ int rtw_suspend_common(_adapter *padapter) pwrpriv->bInSuspend = _TRUE; - while (pwrpriv->bips_processing == _TRUE) - rtw_msleep_os(1); - -#ifdef CONFIG_IOL_READ_EFUSE_MAP - if (!padapter->bup) { - u8 bMacPwrCtrlOn = _FALSE; - rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); - if (bMacPwrCtrlOn) - rtw_hal_power_off(padapter); - } -#endif - - if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) { - RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__ - , padapter->bup - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + if ( RTW_CANNOT_RUN(dvobj)) { + RTW_INFO("%s bDriverStopped=%s bSurpriseRemoved = %s\n", __func__ + , dev_is_drv_stopped(adapter_to_dvobj(padapter)) ? "True" : "False" + , dev_is_surprise_removed(adapter_to_dvobj(padapter)) ? "True" : "False"); pdbgpriv->dbg_suspend_error_cnt++; goto exit; } + rtw_mi_scan_abort(padapter, _TRUE); rtw_ps_deny(padapter, PS_DENY_SUSPEND); @@ -5253,7 +3148,8 @@ int rtw_suspend_common(_adapter *padapter) pwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable; #ifdef CONFIG_P2P_WOWLAN - if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE) || P2P_ROLE_DISABLE != padapter->wdinfo.role) + if (rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_CLIENT) || + rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_GO)) pwrpriv->wowlan_p2p_mode = _TRUE; if (_TRUE == pwrpriv->wowlan_p2p_mode) pwrpriv->wowlan_mode |= pwrpriv->wowlan_p2p_mode; @@ -5286,17 +3182,13 @@ int rtw_suspend_common(_adapter *padapter) #ifdef CONFIG_WOWLAN int rtw_resume_process_wow(_adapter *padapter) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - struct wowlan_ioctl_param poidparam; - struct sta_info *psta = NULL; + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; struct registry_priv *registry_par = &padapter->registrypriv; int ret = _SUCCESS; - u8 en = _FALSE; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -5308,79 +3200,39 @@ int rtw_resume_process_wow(_adapter *padapter) goto exit; } - if (RTW_CANNOT_RUN(padapter)) { + if (RTW_CANNOT_RUN(dvobj)) { RTW_INFO("%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\n" , __func__, padapter - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False"); goto exit; } pwrpriv->wowlan_in_resume = _TRUE; -#ifdef CONFIG_PNO_SUPPORT -#ifdef CONFIG_FWLPS_IN_IPS - if (pwrpriv->wowlan_pno_enable) - rtw_set_fw_in_ips_mode(padapter, _FALSE); -#endif /* CONFIG_FWLPS_IN_IPS */ -#endif/* CONFIG_PNO_SUPPORT */ if (pwrpriv->wowlan_mode == _TRUE) { -#ifdef CONFIG_LPS - if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) { - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); - rtw_wow_lps_level_decide(padapter, _FALSE); - } -#endif /* CONFIG_LPS */ - - rtw_write8(padapter, 0x426, psdpriv->lifetime_en); - rtw_write32(padapter, 0x4c0, psdpriv->pkt_lifetime); - pwrpriv->bFwCurrentInPSMode = _FALSE; -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) - rtw_mi_intf_stop(padapter); - rtw_hal_clear_interrupt(padapter); -#endif - #ifdef CONFIG_SDIO_HCI #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { + if (rtw_sdio_alloc_irq(dvobj) != _SUCCESS) { ret = -1; goto exit; } #endif #endif/*CONFIG_SDIO_HCI*/ - /* Disable WOW, set H2C command */ - poidparam.subcode = WOWLAN_DISABLE; - rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); - #ifdef CONFIG_CONCURRENT_MODE rtw_mi_buddy_reset_drv_sw(padapter); #endif + rtw_hw_wow(padapter, _FALSE); - psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - if (psta) - set_sta_rate(padapter, psta); + dev_clr_drv_stopped(dvobj); + RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, dev_is_drv_stopped(dvobj) ? "True" : "False"); - - rtw_clr_drv_stopped(padapter); - RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False"); - - if(registry_par->suspend_type == FW_IPS_WRC) - rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en); - + #if 0 rtw_mi_start_drv_threads(padapter); - - rtw_mi_intf_start(padapter); - - if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { - if (!rtw_is_surprise_removed(padapter)) { - rtw_hal_deinit(padapter); - rtw_hal_init(padapter); - } - RTW_INFO("FW_IPS_DISABLE_BBRF hal deinit, hal init \n"); - } + #endif #ifdef CONFIG_CONCURRENT_MODE rtw_mi_buddy_netif_carrier_on(padapter); @@ -5397,7 +3249,7 @@ int rtw_resume_process_wow(_adapter *padapter) RTW_INFO("pid[1]:%d\n", padapter->pid[1]); rtw_signal_process(padapter->pid[1], SIGUSR2); } - +#if 0 /* WOW_ToDo */ if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT || pwrpriv->wowlan_wake_reason == RX_DISASSOC|| @@ -5405,13 +3257,13 @@ int rtw_resume_process_wow(_adapter *padapter) RTW_INFO("%s: disconnect reason: %02x\n", __func__, pwrpriv->wowlan_wake_reason); - rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_sta_media_status_rpt(padapter, rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)), 0); - - rtw_free_assoc_resources(padapter, _TRUE); + if (MLME_IS_ASOC(padapter) == _TRUE) + rtw_free_assoc_resources(padapter, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); pmlmeinfo->state = WIFI_FW_NULL_STATE; } else { @@ -5419,11 +3271,12 @@ int rtw_resume_process_wow(_adapter *padapter) rtw_roaming(padapter, NULL); } } - +#endif if (pwrpriv->wowlan_mode == _TRUE) { - pwrpriv->bips_processing = _FALSE; - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); -#ifndef CONFIG_IPS_CHECK_IN_WD + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + _set_timer(&dvobj->dynamic_chk_timer, 2000); + #endif +#if 0 /*ndef CONFIG_IPS_CHECK_IN_WD*/ rtw_set_pwr_state_check_timer(pwrpriv); #endif } else @@ -5445,10 +3298,6 @@ int rtw_resume_process_wow(_adapter *padapter) pwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason; pwrpriv->wowlan_wake_reason = 0; -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); -#endif /* CONFIG_BT_COEXIST */ - exit: RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); return ret; @@ -5460,9 +3309,8 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - struct wowlan_ioctl_param poidparam; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; struct sta_info *psta = NULL; int ret = _SUCCESS; u8 ch, bw, offset; @@ -5479,49 +3327,58 @@ int rtw_resume_process_ap_wow(_adapter *padapter) #ifdef CONFIG_LPS - if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) { - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); + if(pwrpriv->wowlan_power_mgmt != PM_PS_MODE_ACTIVE) { + rtw_set_ps_mode(padapter, PM_PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); rtw_wow_lps_level_decide(padapter, _FALSE); } #endif /* CONFIG_LPS */ pwrpriv->bFwCurrentInPSMode = _FALSE; +#if 0 /*GEORGIA_TODO_REMOVE_IT_FOR_PHL_ARCH*/ - rtw_hal_disable_interrupt(padapter); + rtw_hal_disable_interrupt(GET_PHL_COM(dvobj)); rtw_hal_clear_interrupt(padapter); +#endif #ifdef CONFIG_SDIO_HCI #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { + if (rtw_sdio_alloc_irq(dvobj) != _SUCCESS) { ret = -1; goto exit; } #endif #endif/*CONFIG_SDIO_HCI*/ - /* Disable WOW, set H2C command */ - poidparam.subcode = WOWLAN_AP_DISABLE; - rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); + pwrpriv->wowlan_ap_mode = _FALSE; - rtw_clr_drv_stopped(padapter); - RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False"); + dev_clr_drv_stopped(dvobj); + RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, dev_is_drv_stopped(dvobj) ? "True" : "False"); + #if 0 rtw_mi_start_drv_threads(padapter); + #endif +#if 1 if (rtw_mi_check_status(padapter, MI_LINKED)) { ch = rtw_mi_get_union_chan(padapter); bw = rtw_mi_get_union_bw(padapter); offset = rtw_mi_get_union_offset(padapter); RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset); - set_channel_bwmode(padapter, ch, offset, bw); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); + } +#else + if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { + RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset); + set_channel_bwmode(padapter, ch, offset, bw, _FALSE); + rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); } +#endif /*FOR ONE AP - TODO :Multi-AP*/ { int i; _adapter *iface; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -5532,7 +3389,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) } } - rtw_mi_intf_start(padapter); /* start netif queue */ rtw_mi_netif_wake_queue(padapter); @@ -5546,18 +3402,15 @@ int rtw_resume_process_ap_wow(_adapter *padapter) /* rtw_unlock_suspend(); */ #endif /* CONFIG_RESUME_IN_WORKQUEUE */ - pwrpriv->bips_processing = _FALSE; - _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); -#ifndef CONFIG_IPS_CHECK_IN_WD + #if 0 /*#ifdef CONFIG_CORE_DM_CHK_TIMER*/ + _set_timer(&dvobj->dynamic_chk_timer, 2000); + #endif +#if 0 /*ndef CONFIG_IPS_CHECK_IN_WD*/ rtw_set_pwr_state_check_timer(pwrpriv); #endif /* clean driver side wake up reason. */ pwrpriv->wowlan_wake_reason = 0; -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); -#endif /* CONFIG_BT_COEXIST */ - /* Power On LED */ #ifdef CONFIG_RTW_SW_LED @@ -5581,20 +3434,16 @@ void rtw_mi_resume_process_normal(_adapter *padapter) if ((iface) && rtw_is_adapter_up(iface)) { pmlmepriv = &iface->mlmepriv; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + if (MLME_IS_STA(padapter)) { RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME)) rtw_roaming(iface, NULL); - } -#ifdef CONFIG_AP_MODE - else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + } else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH"); rtw_ap_restore_network(iface); - } -#endif - else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); else RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); @@ -5606,7 +3455,7 @@ int rtw_resume_process_normal(_adapter *padapter) { struct net_device *pnetdev; struct pwrctrl_priv *pwrpriv; - struct dvobj_priv *psdpriv; + struct dvobj_priv *dvobj; struct debug_priv *pdbgpriv; int ret = _SUCCESS; @@ -5618,25 +3467,26 @@ int rtw_resume_process_normal(_adapter *padapter) pnetdev = padapter->pnetdev; pwrpriv = adapter_to_pwrctl(padapter); - psdpriv = padapter->dvobj; - pdbgpriv = &psdpriv->drv_dbg; + dvobj = padapter->dvobj; + pdbgpriv = &dvobj->drv_dbg; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); #ifdef CONFIG_SDIO_HCI /* interface init */ - if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) { + if (rtw_sdio_init(dvobj) != _SUCCESS) { ret = -1; goto exit; } #endif/*CONFIG_SDIO_HCI*/ - rtw_clr_surprise_removed(padapter); - rtw_hal_disable_interrupt(padapter); - + dev_clr_surprise_removed(dvobj); +#if 0 /*GEORGIA_TODO_REMOVE_IT_FOR_PHL_ARCH*/ + rtw_hal_disable_interrupt(GET_PHL_COM(dvobj)); +#endif #ifdef CONFIG_SDIO_HCI #if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { + if (rtw_sdio_alloc_irq(dvobj) != _SUCCESS) { ret = -1; goto exit; } @@ -5661,10 +3511,6 @@ int rtw_resume_process_normal(_adapter *padapter) rtw_signal_process(padapter->pid[1], SIGUSR2); } -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); -#endif /* CONFIG_BT_COEXIST */ - rtw_mi_resume_process_normal(padapter); #ifdef CONFIG_RESUME_IN_WORKQUEUE @@ -5707,6 +3553,7 @@ int rtw_resume_common(_adapter *padapter) #endif /* CONFIG_AP_WOWLAN */ } + pwrpriv->bInSuspend = _FALSE; pwrpriv->wowlan_in_resume = _FALSE; @@ -5775,10 +3622,3 @@ int rtw_vendor_ie_set_api(struct net_device *dev, char *extra) EXPORT_SYMBOL(rtw_vendor_ie_set_api); #endif - -int get_openhd_override_channel(void){ - return openhd_override_channel; -} -int get_openhd_override_tx_power_mbm(void){ - return openhd_override_tx_power_mbm; -} \ No newline at end of file diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c index 14fc295..209e903 100644 --- a/os_dep/linux/recv_linux.c +++ b/os_dep/linux/recv_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,10 +16,11 @@ #include -int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb) +int rtw_os_recvframe_duplicate_skb(_adapter *padapter, + union recv_frame *pcloneframe, struct sk_buff *pskb) { int res = _SUCCESS; - _pkt *pkt_copy = NULL; + struct sk_buff *pkt_copy = NULL; if (pskb == NULL) { RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__); @@ -52,12 +53,13 @@ int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pclonef return res; } -int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb) +int rtw_os_alloc_recvframe(_adapter *padapter, + union recv_frame *precvframe, u8 *pdata, struct sk_buff *pskb) { int res = _SUCCESS; u8 shift_sz = 0; u32 skb_len, alloc_sz; - _pkt *pkt_copy = NULL; + struct sk_buff *pkt_copy = NULL; struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; @@ -99,35 +101,20 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 _rtw_memcpy(pkt_copy->data, pdata, skb_len); precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; } else { -#if 0 - { - rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue); - rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); - - /* The case of can't allocate skb is serious and may never be recovered, - once bDriverStopped is enable, this task should be stopped.*/ - if (!rtw_is_drv_stopped(secondary_padapter)) -#ifdef PLATFORM_LINUX - tasklet_schedule(&precvpriv->recv_tasklet); -#endif - return ret; - } - -#endif #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX RTW_INFO("%s:can not allocate memory for skb copy\n", __func__); precvframe->u.hdr.pkt = NULL; - /* rtw_free_recvframe(precvframe, pfree_recv_queue); */ + /* rtw_free_recvframe(precvframe); */ /*exit_rtw_os_recv_resource_alloc;*/ res = _FAIL; #else if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { RTW_INFO("%s: alloc_skb fail , drop frag frame\n", __FUNCTION__); - /* rtw_free_recvframe(precvframe, pfree_recv_queue); */ + /* rtw_free_recvframe(precvframe); */ res = _FAIL; goto exit_rtw_os_recv_resource_alloc; } @@ -144,7 +131,7 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 precvframe->u.hdr.rx_end = pdata + alloc_sz; } else { RTW_INFO("%s: rtw_skb_clone fail\n", __FUNCTION__); - /* rtw_free_recvframe(precvframe, pfree_recv_queue); */ + /* rtw_free_recvframe(precvframe); */ /*exit_rtw_os_recv_resource_alloc;*/ res = _FAIL; } @@ -160,16 +147,15 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 void rtw_os_free_recvframe(union recv_frame *precvframe) { if (precvframe->u.hdr.pkt) { - rtw_os_pkt_free(precvframe->u.hdr.pkt); + rtw_skb_free(precvframe->u.hdr.pkt); precvframe->u.hdr.pkt = NULL; } } /* init os related resource in struct recv_priv */ -int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) +int rtw_os_recv_resource_init(struct recv_priv *precvpriv) { - int res = _SUCCESS; - + int res = _SUCCESS; #ifdef CONFIG_RTW_NAPI skb_queue_head_init(&precvpriv->rx_napi_skb_queue); @@ -179,7 +165,7 @@ int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) } /* alloc os related resource in union recv_frame */ -int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) +int rtw_os_recv_resource_alloc(union recv_frame *precvframe) { int res = _SUCCESS; @@ -208,59 +194,16 @@ void rtw_os_recv_resource_free(struct recv_priv *precvpriv) } } -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -#if !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C) -#ifdef CONFIG_SDIO_RX_COPY -static int sdio_init_recvbuf_with_skb(struct recv_priv *recvpriv, struct recv_buf *rbuf, u32 size) -{ -#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - if (RBUF_IS_PREALLOC(rbuf)) { - rbuf->pskb = rtw_alloc_skb_premem(size); - if (!rbuf->pskb) { - RTW_WARN("%s: Fail to get pre-alloc skb! size=%d\n", __func__, size); - return _FAIL; - } - skb_set_tail_pointer(rbuf->pskb, 0); /* TODO: do this in RTKM */ - } else -#else - { - SIZE_PTR tmpaddr = 0; - SIZE_PTR alignment = 0; - - rbuf->pskb = rtw_skb_alloc(size + RECVBUFF_ALIGN_SZ); - if (!rbuf->pskb) - return _FAIL; - - tmpaddr = (SIZE_PTR)rbuf->pskb->data; - alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1); - skb_reserve(rbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); - } -#endif - - rbuf->pskb->dev = recvpriv->adapter->pnetdev; - - /* init recvbuf */ - rbuf->phead = rbuf->pskb->head; - rbuf->pdata = rbuf->pskb->data; - rbuf->ptail = skb_tail_pointer(rbuf->pskb); - rbuf->pend = skb_end_pointer(rbuf->pskb); - rbuf->len = 0; - - return _SUCCESS; -} -#endif /* CONFIG_SDIO_RX_COPY */ -#endif /* !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C) */ -#endif /* defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) */ - +#if 0 /* alloc os related resource in struct recv_buf */ -int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, u32 size) +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) { int res = _SUCCESS; #ifdef CONFIG_USB_HCI #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct usb_device *pusbd = pdvobjpriv->pusbdev; + struct usb_device *pusbd = dvobj_to_usb(pdvobjpriv)->pusbdev; #endif precvbuf->irp_pending = _FALSE; @@ -279,26 +222,19 @@ int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, precvbuf->len = 0; #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX - precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)size, &precvbuf->dma_transfer_addr); + precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr); precvbuf->pbuf = precvbuf->pallocated_buf; if (precvbuf->pallocated_buf == NULL) return _FAIL; #endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ -#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #if !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C) - #ifdef CONFIG_SDIO_RX_COPY - res = sdio_init_recvbuf_with_skb(&padapter->recvpriv, precvbuf, size); - #endif - #endif - -#endif /* CONFIG_XXX_HCI */ +#endif /* CONFIG_USB_HCI */ return res; } /* free os related resource in struct recv_buf */ -int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) +int rtw_os_recvbuf_resource_free(_adapter *adapter, struct recv_buf *precvbuf) { int ret = _SUCCESS; @@ -306,8 +242,8 @@ int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct usb_device *pusbd = pdvobjpriv->pusbdev; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct usb_device *pusbd = dvobj_to_usb(dvobj)->pusbdev; rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr); precvbuf->pallocated_buf = NULL; @@ -332,12 +268,14 @@ int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) return ret; } +#endif -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa - , u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl) +struct sk_buff *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, + const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len, + enum rtw_rx_llc_hdl llc_hdl) { u8 *data_ptr; - _pkt *sub_skb; + struct sk_buff *sub_skb; struct rx_pkt_attrib *pattrib; pattrib = &prframe->u.hdr.attrib; @@ -383,8 +321,8 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *s #ifdef CONFIG_RTW_NAPI static int napi_recv(_adapter *padapter, int budget) { - _pkt *pskb; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct sk_buff *pskb; + struct recv_priv *precvpriv = &adapter_to_dvobj(padapter)->recvpriv; int work_done = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; u8 rx_ok; @@ -399,17 +337,8 @@ static int napi_recv(_adapter *padapter, int budget) rx_ok = _FALSE; #ifdef CONFIG_RTW_GRO - /* - cloned SKB use dataref to avoid kernel release it. - But dataref changed in napi_gro_receive. - So, we should prevent cloned SKB go into napi_gro_receive. - */ - if (pregistrypriv->en_gro && !skb_cloned(pskb)) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) - if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_MERGED_FREE) -#else + if (pregistrypriv->en_gro) { if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP) -#endif rx_ok = _TRUE; goto next; } @@ -434,7 +363,7 @@ int rtw_recv_napi_poll(struct napi_struct *napi, int budget) { _adapter *padapter = container_of(napi, _adapter, napi); int work_done = 0; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_priv *precvpriv = &adapter_to_dvobj(padapter)->recvpriv; work_done = napi_recv(padapter, budget); @@ -471,10 +400,11 @@ void dynamic_napi_th_chk (_adapter *adapter) #endif /* CONFIG_RTW_NAPI_DYNAMIC */ #endif /* CONFIG_RTW_NAPI */ -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe) +void rtw_os_recv_indicate_pkt(_adapter *padapter, struct sk_buff *pkt, + union recv_frame *rframe) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct recv_priv *precvpriv = &(padapter->recvpriv); + struct recv_priv *precvpriv = &adapter_to_dvobj(padapter)->recvpriv; struct registry_priv *pregistrypriv = &padapter->registrypriv; #ifdef CONFIG_BR_EXT void *br_port = NULL; @@ -486,9 +416,9 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *r struct ethhdr *ehdr = (struct ethhdr *)pkt->data; DBG_COUNTER(padapter->rx_logs.os_indicate); - #ifdef CONFIG_BR_EXT - if (!adapter_use_wds(padapter) && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + if (!adapter_use_wds(padapter) && + (MLME_IS_STA(padapter) || MLME_IS_ADHOC(padapter))) { /* Insert NAT2.5 RX here! */ #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) br_port = padapter->pnetdev->br_port; @@ -585,7 +515,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup else key_type |= NL80211_KEYTYPE_PAIRWISE; - cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC); + cfg80211_michael_mic_failure(padapter->pnetdev, sta->phl_sta->mac_addr, key_type, -1, NULL, GFP_ATOMIC); #endif _rtw_memset(&ev, 0x00, sizeof(ev)); @@ -595,7 +525,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup ev.flags |= IW_MICFAILURE_PAIRWISE; ev.src_addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(ev.src_addr.sa_data, sta->phl_sta->mac_addr, ETH_ALEN); _rtw_memset(&wrqu, 0x00, sizeof(wrqu)); wrqu.data.length = sizeof(ev); @@ -608,7 +538,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup #ifdef CONFIG_HOSTAPD_MLME void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) { - _pkt *skb; + struct sk_buff *skb; struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; @@ -653,7 +583,7 @@ void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) { int ret = _FAIL; - _pkt *skb; + struct sk_buff *skb; skb = precv_frame->u.hdr.pkt; if (skb == NULL) { @@ -683,7 +613,7 @@ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) inline void rtw_rframe_set_os_pkt(union recv_frame *rframe) { - _pkt *skb = rframe->u.hdr.pkt; + struct sk_buff *skb = rframe->u.hdr.pkt; skb->data = rframe->u.hdr.rx_data; skb_set_tail_pointer(skb, rframe->u.hdr.len); @@ -692,47 +622,18 @@ inline void rtw_rframe_set_os_pkt(union recv_frame *rframe) int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) { - struct recv_priv *precvpriv; - _queue *pfree_recv_queue; - - precvpriv = &(padapter->recvpriv); - pfree_recv_queue = &(precvpriv->free_recv_queue); - if (precv_frame->u.hdr.pkt == NULL) goto _recv_indicatepkt_drop; rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame); precv_frame->u.hdr.pkt = NULL; - rtw_free_recvframe(precv_frame, pfree_recv_queue); + rtw_free_recvframe(precv_frame); return _SUCCESS; _recv_indicatepkt_drop: - rtw_free_recvframe(precv_frame, pfree_recv_queue); + rtw_free_recvframe(precv_frame); DBG_COUNTER(padapter->rx_logs.os_indicate_err); return _FAIL; } -void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) -{ -#ifdef CONFIG_USB_HCI - struct recv_priv *precvpriv = &padapter->recvpriv; - - precvbuf->ref_cnt--; - - /* free skb in recv_buf */ - rtw_skb_free(precvbuf->pskb); - - precvbuf->pskb = NULL; - - if (precvbuf->irp_pending == _FALSE) - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - - -#endif -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - precvbuf->pskb = NULL; -#endif - -} - diff --git a/os_dep/linux/rhashtable.c b/os_dep/linux/rhashtable.c index af9c9ae..01bd66a 100644 --- a/os_dep/linux/rhashtable.c +++ b/os_dep/linux/rhashtable.c @@ -727,10 +727,10 @@ int rhashtable_init(struct rhashtable *ht, if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT)) return -EINVAL; - memset(ht, 0, sizeof(*ht)); + _rtw_memset(ht, 0, sizeof(*ht)); mutex_init(&ht->mutex); spin_lock_init(&ht->lock); - memcpy(&ht->p, params, sizeof(*params)); + _rtw_memcpy(&ht->p, params, sizeof(*params)); if (params->min_size) ht->p.min_size = roundup_pow_of_two(params->min_size); diff --git a/os_dep/linux/rhashtable.h b/os_dep/linux/rhashtable.h index a6db325..7416102 100644 --- a/os_dep/linux/rhashtable.h +++ b/os_dep/linux/rhashtable.h @@ -511,7 +511,7 @@ static inline int rhashtable_compare(struct rhashtable_compare_arg *arg, struct rhashtable *ht = arg->ht; const char *ptr = obj; - return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len); + return (_rtw_memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len) == _TRUE)? 0: 1; } /** diff --git a/os_dep/linux/rtw_android.c b/os_dep/linux/rtw_android.c index 10f8f23..45e51ae 100644 --- a/os_dep/linux/rtw_android.c +++ b/os_dep/linux/rtw_android.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -97,6 +97,9 @@ const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { "SET_AEK", "EXT_AUTH_STATUS", "DRIVER_VERSION" +#ifdef ROKU_PRIVATE + ,"ROKU_FIND_REMOTE" +#endif }; #ifdef CONFIG_PNO_SUPPORT @@ -282,7 +285,7 @@ static int rtw_android_pno_setup(struct net_device *net, char *command, int tota * net: net_device * request: cfg80211_request * */ - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) int rtw_android_cfg80211_pno_setup(struct net_device *net, struct cfg80211_ssid *ssids, int n_ssids, int interval) { @@ -305,7 +308,7 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, for (index = 0 ; index < nssid ; index++) { pno_ssids_local[index].SSID_len = ssids[index].ssid_len; - memcpy(pno_ssids_local[index].SSID, ssids[index].ssid, + _rtw_memcpy(pno_ssids_local[index].SSID, ssids[index].ssid, ssids[index].ssid_len); } #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) @@ -322,10 +325,10 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, #ifdef CONFIG_PNO_SET_DEBUG rtw_dev_pno_debug(net); #endif -exit_proc: + return res; } - +#endif int rtw_android_pno_enable(struct net_device *net, int pno_enable) { _adapter *padapter = (_adapter *)rtw_netdev_priv(net); @@ -373,7 +376,7 @@ int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d", - pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); + pcur_network->network.Ssid.Ssid, padapter->recvinfo.rssi); } return bytes_written; @@ -405,7 +408,7 @@ int rtw_android_set_country(struct net_device *net, char *command, int total_len char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1; int ret = _FAIL; - ret = rtw_set_country(adapter, country_code); + ret = rtw_set_country(adapter, country_code, RTW_REGD_SET_BY_USER); return (ret == _SUCCESS) ? 0 : -1; } @@ -598,7 +601,7 @@ static int rtw_android_set_aek(struct net_device *ndev, char *command, int total int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { - #define PRIVATE_COMMAND_MAX_LEN 8192 + #define PRIVATE_COMMAND_MAX_LEN 65536 int ret = 0; char *command = NULL; int cmd_num; @@ -697,7 +700,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) goto exit; } - if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (!rtw_hw_chk_wl_func(adapter_to_dvobj(padapter), WL_FUNC_MIRACAST)) { switch (cmd_num) { case ANDROID_WIFI_CMD_WFD_ENABLE: case ANDROID_WIFI_CMD_WFD_DISABLE: @@ -716,11 +719,6 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) case ANDROID_WIFI_CMD_SCAN_ACTIVE: /* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */ -#ifdef CONFIG_PLATFORM_MSTAR -#ifdef CONFIG_IOCTL_CFG80211 - adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->bandroid_scan = _TRUE; -#endif /* CONFIG_IOCTL_CFG80211 */ -#endif /* CONFIG_PLATFORM_MSTAR */ break; case ANDROID_WIFI_CMD_SCAN_PASSIVE: /* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */ @@ -828,13 +826,13 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) break; #ifdef CONFIG_IOCTL_CFG80211 - #ifdef CONFIG_AP_MODE case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: { int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3; bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0'); + + adapter_to_dvobj(padapter)->wpas_type = RTW_WPAS_ANDROID; break; } - #endif #endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_WFD @@ -848,8 +846,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) /* We can enable the WFD function by using the following command: */ /* wpa_cli driver wfd-enable */ - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - rtw_wfd_enable(padapter, 1); + rtw_wfd_enable(padapter, 1); break; } @@ -858,8 +855,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) /* We can disable the WFD function by using the following command: */ /* wpa_cli driver wfd-disable */ - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - rtw_wfd_enable(padapter, 0); + rtw_wfd_enable(padapter, 0); break; } case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: { @@ -867,8 +863,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) /* We can set the tcp port number by using the following command: */ /* wpa_cli driver wfd-set-tcpport = 554 */ - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command)); + rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command)); break; } case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: { @@ -879,10 +874,9 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) /* Specify the WFD device type ( WFD source/primary sink ) */ pwfd_info = &padapter->wfd_info; - if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { - pwfd_info->wfd_device_type = (u8) get_int_from_command(command); - pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL; - } + + pwfd_info->wfd_device_type = (u8) get_int_from_command(command); + pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL; break; } #endif @@ -927,7 +921,8 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) #endif /* CONFIG_GTK_OL */ case ANDROID_WIFI_CMD_P2P_DISABLE: { #ifdef CONFIG_P2P - rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); + /* This Android private command is no longer in use */ + /* rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); */ #endif /* CONFIG_P2P */ break; } @@ -949,6 +944,35 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) snprintf(command, bytes_written + 1, DRIVERVERSION); break; } +#ifdef ROKU_PRIVATE + case ANDROID_WIFI_CMD_ROKU_FIND_REMOTE: { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 num, cmdlen; + u8 *ptr,*remote_mac_addr; + int i; + + cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_ROKU_FIND_REMOTE]); + num = *(command + cmdlen + 1) - '0'; + + if (num != 0) { + pwdinfo->num_of_remote = num; + remote_mac_addr = pwdinfo->remote_mac_address; + ptr = command + cmdlen + 3; + + for (i = 0; i < num; i++) { + macstr2num(remote_mac_addr, ptr); + ptr += 18; /* skip space and go to next mac addr */ + remote_mac_addr += 6; + } + + set_find_remote_timer(pmlmeext, 1); + } + else + _cancel_timer_ex(&pmlmeext->find_remote_timer); + break; + } +#endif default: RTW_INFO("Unknown PRIVATE command %s - ignored\n", command); snprintf(command, 3, "OK"); @@ -1123,13 +1147,9 @@ static int wifi_probe(struct platform_device *pdev) (int)wifi_irqres->start, wifi_wake_gpio); if (wifi_wake_gpio > 0) { -#ifdef CONFIG_PLATFORM_INTEL_BYT - wifi_configure_gpio(); -#else /* CONFIG_PLATFORM_INTEL_BYT */ gpio_request(wifi_wake_gpio, "oob_irq"); gpio_direction_input(wifi_wake_gpio); oob_irq = gpio_to_irq(wifi_wake_gpio); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq); } else if (wifi_irqres) { oob_irq = wifi_irqres->start; @@ -1146,11 +1166,10 @@ static int wifi_probe(struct platform_device *pdev) } #ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN -extern PADAPTER g_test_adapter; +extern _adapter * g_test_adapter; static void shutdown_card(void) { - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(g_test_adapter); u32 addr; u8 tmp8, cnt = 0; @@ -1167,14 +1186,17 @@ static void shutdown_card(void) #ifdef CONFIG_GPIO_WAKEUP /*default wake up pin change to BT*/ RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); - rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, pwrpriv->wowlan_gpio_index, _FALSE); + /* ToDo: clear pin mux code is not ready + rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, WAKEUP_GPIO_IDX, _FALSE); */ #endif /* CONFIG_GPIO_WAKEUP */ #endif /* CONFIG_WOWLAN */ /* Leave SDIO HCI Suspend */ + #if 0 /*GEORGIA_TODO_REDEFINE_IO*/ addr = 0x10250086; rtw_write8(g_test_adapter, addr, 0); do { + tmp8 = rtw_read8(g_test_adapter, addr); cnt++; RTW_INFO(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n", @@ -1214,10 +1236,13 @@ static void shutdown_card(void) /* lock register page0 0x0~0xB read/write */ rtw_write8(g_test_adapter, 0x1C, 0x0E); - - rtw_set_surprise_removed(g_test_adapter); +#else + rtw_hal_sdio_leave_suspend(g_test_adapter); +#endif + dev_set_surprise_removed(adapter_to_dvobj(g_test_adapter)); RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s\n", - FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False"); + FUNC_ADPT_ARG(g_test_adapter), + dev_is_surprise_removed(adapter_to_dvobj(g_test_adapter)) ? "True" : "False"); } #endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */ @@ -1312,35 +1337,4 @@ static void wifi_del_dev(void) } #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ -#ifdef CONFIG_GPIO_WAKEUP -#ifdef CONFIG_PLATFORM_INTEL_BYT -int wifi_configure_gpio(void) -{ - if (gpio_request(oob_gpio, "oob_irq")) { - RTW_INFO("## %s Cannot request GPIO\n", __FUNCTION__); - return -1; - } - gpio_export(oob_gpio, 0); - if (gpio_direction_input(oob_gpio)) { - RTW_INFO("## %s Cannot set GPIO direction input\n", __FUNCTION__); - return -1; - } - oob_irq = gpio_to_irq(oob_gpio); - if (oob_irq < 0) { - RTW_INFO("## %s Cannot convert GPIO to IRQ\n", __FUNCTION__); - return -1; - } - - RTW_INFO("## %s OOB_IRQ=%d\n", __FUNCTION__, oob_irq); - return 0; -} -#endif /* CONFIG_PLATFORM_INTEL_BYT */ -void wifi_free_gpio(unsigned int gpio) -{ -#ifdef CONFIG_PLATFORM_INTEL_BYT - if (gpio) - gpio_free(gpio); -#endif /* CONFIG_PLATFORM_INTEL_BYT */ -} -#endif /* CONFIG_GPIO_WAKEUP */ diff --git a/os_dep/linux/rtw_cfg.c b/os_dep/linux/rtw_cfg.c new file mode 100644 index 0000000..0a14f42 --- /dev/null +++ b/os_dep/linux/rtw_cfg.c @@ -0,0 +1,1809 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _OS_INTFS_C_ + +#include + +/* module param defaults */ +int rtw_chip_version = 0x00; +int rtw_rfintfs = HWPI; +int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */ +#ifdef DBG_LA_MODE +int rtw_la_mode_en=0; +module_param(rtw_la_mode_en, int, 0644); +#endif +int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */ +/* NDIS_802_11_SSID ssid; */ +int rtw_channel = 36;/* ad-hoc support requirement */ +int rtw_wireless_mode = WLAN_MD_MAX; +int rtw_band_type = BAND_CAP_2G | BAND_CAP_5G | BAND_CAP_6G; +module_param(rtw_wireless_mode, int, 0644); +module_param(rtw_band_type, int, 0644); +#ifdef CONFIG_HW_RTS +int rtw_vrtl_carrier_sense = ENABLE_VCS; +int rtw_vcs_type = RTS_CTS; +int rtw_hw_rts_en = 1; +#else +int rtw_vrtl_carrier_sense = AUTO_VCS; +int rtw_vcs_type = RTS_CTS; +int rtw_hw_rts_en = 0; +#endif +int rtw_rts_thresh = 2347; +int rtw_frag_thresh = 2346; +int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */ +int rtw_scan_mode = 1;/* active, passive */ +/* int smart_ps = 1; */ +#ifdef CONFIG_POWER_SAVING + + /* LPS configuration */ +/* RTW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */ +#if (RTW_LPS_MODE > 0) + int rtw_power_mgnt = PM_PS_MODE_MAX; + + #ifdef CONFIG_USB_HCI + int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/ + #else /*SDIO,PCIE*/ + int rtw_lps_level = (RTW_LPS_MODE - 1); + #endif/*CONFIG_USB_HCI*/ +#else + int rtw_power_mgnt = PM_PS_MODE_ACTIVE; + int rtw_lps_level = LPS_NORMAL; +#endif + + int rtw_lps_chk_by_tp = 1; + + /* WOW LPS configuration */ +#ifdef CONFIG_WOWLAN +/* RTW_WOW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */ +#if (RTW_WOW_LPS_MODE > 0) + int rtw_wow_power_mgnt = PM_PS_MODE_MAX; + int rtw_wow_lps_level = (RTW_WOW_LPS_MODE - 1); +#else + int rtw_wow_power_mgnt = PM_PS_MODE_ACTIVE; + int rtw_wow_lps_level = LPS_NORMAL; +#endif +#endif /* CONFIG_WOWLAN */ + +#else /* !CONFIG_POWER_SAVING */ + int rtw_power_mgnt = PM_PS_MODE_ACTIVE; + int rtw_lps_level = LPS_NORMAL; + int rtw_lps_chk_by_tp = 0; +#ifdef CONFIG_WOWLAN + int rtw_wow_power_mgnt = PM_PS_MODE_ACTIVE; + int rtw_wow_lps_level = LPS_NORMAL; +#endif /* CONFIG_WOWLAN */ +#endif /* CONFIG_POWER_SAVING */ +#ifdef CONFIG_RTW_IPS + int rtw_ips_mode = PS_OP_MODE_AUTO; +#else + int rtw_ips_mode = PS_OP_MODE_DISABLED; +#endif +#ifdef CONFIG_RTW_LPS + int rtw_lps_mode = PS_OP_MODE_AUTO; + int rtw_lps_cap = PS_CAP_PWRON | + PS_CAP_RF_OFF | + PS_CAP_CLK_GATED | + PS_CAP_PWR_GATED; +#else + int rtw_lps_mode = PS_OP_MODE_DISABLED; + int rtw_lps_cap = PS_CAP_PWRON; +#endif + +#ifdef CONFIG_NARROWBAND_SUPPORTING +int rtw_nb_config = CONFIG_NB_VALUE; +module_param(rtw_nb_config, int, 0644); +MODULE_PARM_DESC(rtw_nb_config, "5M/10M/Normal bandwidth configuration"); +#endif + +module_param(rtw_ips_mode, int, 0644); +MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); + +module_param(rtw_lps_mode, int, 0644); +MODULE_PARM_DESC(rtw_lps_mode, "The default LPS mode"); + + +module_param(rtw_lps_cap, int, 0644); +MODULE_PARM_DESC(rtw_lps_cap, "The default LPS cap"); + +#ifdef CONFIG_LPS_1T1R +int rtw_lps_1t1r = RTW_LPS_1T1R; +module_param(rtw_lps_1t1r, int, 0644); +MODULE_PARM_DESC(rtw_lps_1t1r, "The default LPS 1T1R setting"); +#endif + +module_param(rtw_lps_chk_by_tp, int, 0644); + +#ifdef CONFIG_WOWLAN +module_param(rtw_wow_power_mgnt, int, 0644); +MODULE_PARM_DESC(rtw_wow_power_mgnt, "The default WOW LPS mode"); +module_param(rtw_wow_lps_level, int, 0644); +MODULE_PARM_DESC(rtw_wow_lps_level, "The default WOW LPS level"); +#ifdef CONFIG_LPS_1T1R +int rtw_wow_lps_1t1r = RTW_WOW_LPS_1T1R; +module_param(rtw_wow_lps_1t1r, int, 0644); +MODULE_PARM_DESC(rtw_wow_lps_1t1r, "The default WOW LPS 1T1R setting"); +#endif +#endif /* CONFIG_WOWLAN */ + +/* LPS: + * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll + * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll + * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0 +*/ +int rtw_smart_ps = 2; + +int rtw_max_bss_cnt = 0; +module_param(rtw_max_bss_cnt, int, 0644); +#ifdef CONFIG_WMMPS_STA +/* WMMPS: + * rtw_smart_ps = 0 => Only for fw test + * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap + * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap +*/ +int rtw_wmm_smart_ps = 2; +#endif /* CONFIG_WMMPS_STA */ + +int rtw_check_fw_ps = 1; + +#ifdef CONFIG_TX_EARLY_MODE +int rtw_early_mode = 1; +#endif + +int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */ +module_param(rtw_usb_rxagg_mode, int, 0644); + +int rtw_dynamic_agg_enable = 1; +module_param(rtw_dynamic_agg_enable, int, 0644); + +/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4, +* please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. +*/ +#ifdef CONFIG_RTW_DEBUG +#ifdef RTW_LOG_LEVEL + uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */ +#else + uint rtw_drv_log_level = _DRV_INFO_; +#endif +module_param(rtw_drv_log_level, uint, 0644); +MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4"); +#endif +int rtw_radio_enable = 1; +int rtw_long_retry_lmt = 7; +int rtw_short_retry_lmt = 7; +int rtw_busy_thresh = 40; +/* int qos_enable = 0; */ /* * */ +int rtw_ack_policy = NORMAL_ACK; + +int rtw_mp_mode = 0; + +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) +uint rtw_mp_customer_str = 0; +module_param(rtw_mp_customer_str, uint, 0644); +MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode"); +#endif + +int rtw_software_encrypt = 0; +int rtw_software_decrypt = 0; + +int rtw_acm_method = 0;/* 0:By SW 1:By HW. */ + +int rtw_wmm_enable = 1;/* default is set to enable the wmm. */ + +#ifdef CONFIG_WMMPS_STA +/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ +/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */ +int rtw_uapsd_max_sp = NO_LIMIT; +/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ +int rtw_uapsd_ac_enable = 0x0; +#endif /* CONFIG_WMMPS_STA */ + +#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) + /*PHYDM API, must enable by default*/ + int rtw_pwrtrim_enable = 1; +#else + int rtw_pwrtrim_enable = 0; /* Default Enalbe power trim by efuse config */ +#endif + +uint rtw_tx_bw_mode = 0x21; +module_param(rtw_tx_bw_mode, uint, 0644); +MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode"); + + +#ifdef CONFIG_80211N_HT +int rtw_ht_enable = 1; +/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz +* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 +* 0x21 means enable 2.4G 40MHz & 5G 80MHz */ +#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE +int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE; +#else +int rtw_bw_mode = ((BW_CAP_80M | BW_CAP_40M | BW_CAP_20M) << 4 ) | (BW_CAP_40M | BW_CAP_20M); +#endif + +int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ + +int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ + +/* 10.12 A-MSDU operation + * HT - 0: 3839, 1: 7935 octets - Maximum A-MSDU Length + * VHT - 0: 3895, 1: 7991, 2:11454 octets - Maximum MPDU Length + */ +int rtw_max_amsdu_len = 1; + +module_param(rtw_max_amsdu_len, uint, 0644); + +/* +* 2: Follow the AMSDU filed in ADDBA Resp. (Deault) +* 0: Force the AMSDU filed in ADDBA Resp. to be disabled. +* 1: Force the AMSDU filed in ADDBA Resp. to be enabled. +*/ +int rtw_tx_ampdu_amsdu = 2; + +int rtw_quick_addba_req = 0; + +static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS; +static uint rtw_rx_ampdu_sz_limit_1ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS; +static uint rtw_rx_ampdu_sz_limit_2ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS; +static uint rtw_rx_ampdu_sz_limit_3ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS; +static uint rtw_rx_ampdu_sz_limit_4ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation"); + +/* Short GI support Bit Map +* BIT0 - 20MHz, 0: non-support, 1: support +* BIT1 - 40MHz, 0: non-support, 1: support +* BIT2 - 80MHz, 0: non-support, 1: support +* BIT3 - 160MHz, 0: non-support, 1: support */ +int rtw_short_gi = 0xf; +/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ +int rtw_ldpc_cap = 0x33; +/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx +* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx +* BIT8: Enable HE STBC Rx, BIT9: Enable HE STBC Rx(greater than 80M) +* BIT10: Enable HE STBC Tx, BIT11: Enable HE STBC Tx(greater than 80M) +*/ +int rtw_stbc_cap = 0x133; +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_BEAMFORMING +/* +* BIT0: Enable VHT SU Beamformer +* BIT1: Enable VHT SU Beamformee +* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer +* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee +* BIT4: Enable HT Beamformer +* BIT5: Enable HT Beamformee +* BIT6: Enable HE SU Beamformer +* BIT7: Enable HE SU Beamformee +* BIT8: Enable HE MU Beamformer +* BIT9: Enable HE MU Beamformee +*/ +int rtw_beamform_cap = BIT(1) | BIT(7); /* For sw role BF cap. */ +int rtw_sw_proto_bf_cap_phy0 = BIT(1) | BIT(7); +int rtw_sw_proto_bf_cap_phy1 = BIT(1) | BIT(7); +int rtw_dyn_txbf = 1; +int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/ +int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, others for manual*/ +#endif + +#ifdef CONFIG_80211AC_VHT +int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */ +module_param(rtw_vht_enable, int, 0644); + +int rtw_vht_24g_enable = 0; /* 0:disable, 1:enable */ +module_param(rtw_vht_24g_enable, int, 0644); + +int rtw_ampdu_factor = 7; + +uint rtw_vht_rx_mcs_map = 0xaaaa; +module_param(rtw_vht_rx_mcs_map, uint, 0644); +MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); +#endif /* CONFIG_80211AC_VHT */ + +#ifdef CONFIG_80211AX_HE +int rtw_he_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */ +module_param(rtw_he_enable, int, 0644); +#endif + +int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */ + + +/* 0: not check in watch dog, 1: check in watch dog */ +int rtw_check_hw_status = 0; + +int rtw_low_power = 0; +int rtw_wifi_spec = 0; + +#ifdef CONFIG_SPECIAL_RF_PATH /* configure Nss/xTxR IC to 1ss/1T1R */ +int rtw_rf_path = RF_1T1R; +int rtw_tx_nss = 1; +int rtw_rx_nss = 1; +#else +int rtw_rf_path = RF_TYPE_MAX; +int rtw_tx_nss = 0; +int rtw_rx_nss = 0; +#endif +module_param(rtw_rf_path, int, 0644); +module_param(rtw_tx_nss, int, 0644); +module_param(rtw_rx_nss, int, 0644); + +#ifdef CONFIG_REGD_SRC_FROM_OS +static uint rtw_regd_src = CONFIG_RTW_REGD_SRC; +module_param(rtw_regd_src, uint, 0644); +MODULE_PARM_DESC(rtw_regd_src, "The default regd source selection, 0:Realtek defined, 1: OS"); +#endif + +char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; +char *rtw_country_code = rtw_country_unspecified; +module_param(rtw_country_code, charp, 0644); +MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); + +uint rtw_channel_plan = CONFIG_RTW_CHPLAN; +module_param(rtw_channel_plan, uint, 0644); +MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); + +static uint rtw_excl_chs[MAX_CHANNEL_NUM_2G_5G] = CONFIG_RTW_EXCL_CHS; +static int rtw_excl_chs_num = 0; +module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644); +MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array"); + +#if CONFIG_IEEE80211_BAND_6GHZ +uint rtw_channel_plan_6g = CONFIG_RTW_CHPLAN_6G; +module_param(rtw_channel_plan_6g, uint, 0644); +MODULE_PARM_DESC(rtw_channel_plan_6g, "The default chplan_6g ID when rtw_alpha2 is not specified or valid"); + +static uint rtw_excl_chs_6g[MAX_CHANNEL_NUM_6G] = CONFIG_RTW_EXCL_CHS_6G; +static int rtw_excl_chs_6g_num = 0; +module_param_array(rtw_excl_chs_6g, uint, &rtw_excl_chs_6g_num, 0644); +MODULE_PARM_DESC(rtw_excl_chs_6g, "exclusive channel array"); +#endif /* CONFIG_IEEE80211_BAND_6GHZ */ + +#ifdef CONFIG_80211D +static uint rtw_country_ie_slave_en_role = CONFIG_RTW_COUNTRY_IE_SLAVE_EN_ROLE; +module_param(rtw_country_ie_slave_en_role, uint, 0644); +MODULE_PARM_DESC(rtw_country_ie_slave_en_role, "802.11d country IE slave enable role: BIT0:pure STA mode, BIT1:P2P group client"); + +static uint rtw_country_ie_slave_en_ifbmp = CONFIG_RTW_COUNTRY_IE_SLAVE_EN_IFBMP; +module_param(rtw_country_ie_slave_en_ifbmp, uint, 0644); +MODULE_PARM_DESC(rtw_country_ie_slave_en_ifbmp, "802.11d country IE slave enable iface bitmap"); +#endif + +/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list. +But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/ +#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE + int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ +#else + int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ +#endif + +#ifdef CONFIG_BTC +int rtw_btcoex_enable = 2; +module_param(rtw_btcoex_enable, int, 0644); +MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse"); + +int rtw_ant_num = 0; +module_param(rtw_ant_num, int, 0644); +MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse"); + +int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */ +int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */ +int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ +#endif /* CONFIG_BTC */ + +int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */ + +int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */ +int rtw_antdiv_type = 0; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ + +int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/ + +int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/ + +/* 0: doesn't switch, 1: switch to usb 3.0 , 2: switch to usb 2.0 */ +int rtw_switch_usb_mode = 0; + + + +#ifdef CONFIG_HW_PWRP_DETECTION +int rtw_hwpwrp_detect = 1; +#else +int rtw_hwpwrp_detect = 0; /* HW power ping detect 0:disable , 1:enable */ +#endif + +#ifdef CONFIG_USB_HCI +int rtw_hw_wps_pbc = 1; +#else +int rtw_hw_wps_pbc = 0; +#endif + +#ifdef CONFIG_PCI_ASPM +/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ +int rtw_pci_aspm_enable = 0x5; +#else +int rtw_pci_aspm_enable; +#endif + +/* + * BIT [15:12] mask of ps mode + * BIT [11:8] val of ps mode + * BIT [7:4] mask of perf mode + * BIT [3:0] val of perf mode + * + * L0s:BIT[+0] L1:BIT[+1] + * + * 0x0030: change value only if perf mode + * 0x3300: change value only if ps mode + * 0x3330: change value in both perf and ps mode + */ +#ifdef CONFIG_PCI_DYNAMIC_ASPM +#ifdef CONFIG_PCI_ASPM +int rtw_pci_dynamic_aspm_linkctrl = 0x3330; +#else +int rtw_pci_dynamic_aspm_linkctrl = 0x0030; +#endif +#else +int rtw_pci_dynamic_aspm_linkctrl = 0x0000; +#endif +module_param(rtw_pci_dynamic_aspm_linkctrl, int, 0644); + +#ifdef CONFIG_QOS_OPTIMIZATION +int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */ +#else +int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */ +#endif +module_param(rtw_qos_opt_enable, int, 0644); + +#ifdef CONFIG_RTW_ACS +int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/ +module_param(rtw_acs_auto_scan, int, 0644); + +int rtw_acs = 1; +module_param(rtw_acs, int, 0644); +#endif + +char *ifname = "wlan%d"; +module_param(ifname, charp, 0644); +MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); + +#ifdef CONFIG_PLATFORM_ANDROID + char *if2name = "p2p%d"; +#else /* CONFIG_PLATFORM_ANDROID */ + char *if2name = "wlan%d"; +#endif /* CONFIG_PLATFORM_ANDROID */ +module_param(if2name, charp, 0644); +MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); + +char *rtw_initmac = 0; /* temp mac address if users want to use instead of the mac address in Efuse */ + +#ifdef CONFIG_CONCURRENT_MODE + + #if (CONFIG_IFACE_NUMBER > 2) + int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1; + module_param(rtw_virtual_iface_num, int, 0644); + #else + int rtw_virtual_iface_num = 1; + #endif + +#if defined(CONFIG_CONCURRENT_MODE) && !RTW_P2P_GROUP_INTERFACE +#ifdef CONFIG_P2P + #ifdef CONFIG_SEL_P2P_IFACE + int rtw_sel_p2p_iface = CONFIG_SEL_P2P_IFACE; + #else + int rtw_sel_p2p_iface = (CONFIG_RTW_STATIC_NDEV_NUM - 1); + #endif + + module_param(rtw_sel_p2p_iface, int, 0644); + +#endif +#endif + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST + int rtw_ignore_go_in_scan = 1; + uint rtw_ignore_low_rssi_in_scan = 30; + + module_param(rtw_ignore_go_in_scan, int, 0644); + module_param(rtw_ignore_low_rssi_in_scan, uint, 0644); +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + +#endif + +/* affect ap/go cw only so far , 0 is no change*/ +uint rtw_vo_edca = 0; +module_param(rtw_vo_edca, uint, 0644); + +#ifdef CONFIG_AP_MODE +u8 rtw_bmc_tx_rate = MGN_UNKNOWN; + +#if CONFIG_RTW_AP_DATA_BMC_TO_UC +int rtw_ap_src_b2u_flags = CONFIG_RTW_AP_SRC_B2U_FLAGS; +module_param(rtw_ap_src_b2u_flags, int, 0644); + +int rtw_ap_fwd_b2u_flags = CONFIG_RTW_AP_FWD_B2U_FLAGS; +module_param(rtw_ap_fwd_b2u_flags, int, 0644); +#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */ +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +int rtw_msrc_b2u_flags = CONFIG_RTW_MSRC_B2U_FLAGS; +module_param(rtw_msrc_b2u_flags, int, 0644); + +int rtw_mfwd_b2u_flags = CONFIG_RTW_MFWD_B2U_FLAGS; +module_param(rtw_mfwd_b2u_flags, int, 0644); +#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ +#endif /* CONFIG_RTW_MESH */ + +#ifdef RTW_WOW_STA_MIX +int rtw_wowlan_sta_mix_mode = 1; +#else +int rtw_wowlan_sta_mix_mode = 0; +#endif +module_param(rtw_wowlan_sta_mix_mode, int, 0644); +module_param(rtw_pwrtrim_enable, int, 0644); +module_param(rtw_initmac, charp, 0644); +module_param(rtw_chip_version, int, 0644); +module_param(rtw_rfintfs, int, 0644); +module_param(rtw_lbkmode, int, 0644); +module_param(rtw_network_mode, int, 0644); +module_param(rtw_channel, int, 0644); +module_param(rtw_mp_mode, int, 0644); +module_param(rtw_wmm_enable, int, 0644); +#ifdef CONFIG_WMMPS_STA +module_param(rtw_uapsd_max_sp, int, 0644); +module_param(rtw_uapsd_ac_enable, int, 0644); +module_param(rtw_wmm_smart_ps, int, 0644); +#endif /* CONFIG_WMMPS_STA */ +module_param(rtw_vrtl_carrier_sense, int, 0644); +module_param(rtw_vcs_type, int, 0644); +module_param(rtw_hw_rts_en, int, 0644); +module_param(rtw_busy_thresh, int, 0644); + +#ifdef CONFIG_80211N_HT +module_param(rtw_ht_enable, int, 0644); +module_param(rtw_bw_mode, int, 0644); +module_param(rtw_ampdu_enable, int, 0644); +module_param(rtw_stbc_cap, int, 0644); +module_param(rtw_rx_ampdu_amsdu, int, 0644); +module_param(rtw_tx_ampdu_amsdu, int, 0644); +module_param(rtw_quick_addba_req, int, 0644); +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_BEAMFORMING +module_param(rtw_beamform_cap, int, 0644); +module_param(rtw_sw_proto_bf_cap_phy0, int, 0644); +module_param(rtw_sw_proto_bf_cap_phy1, int, 0644); +module_param(rtw_dyn_txbf, int, 0644); +#endif +module_param(rtw_lowrate_two_xmit, int, 0644); + +module_param(rtw_power_mgnt, int, 0644); +module_param(rtw_smart_ps, int, 0644); +module_param(rtw_low_power, int, 0644); +module_param(rtw_wifi_spec, int, 0644); + +module_param(rtw_full_ch_in_p2p_handshake, int, 0644); +module_param(rtw_antdiv_cfg, int, 0644); +module_param(rtw_antdiv_type, int, 0644); + +module_param(rtw_drv_ant_band_switch, int, 0644); +module_param(rtw_single_ant_path, int, 0644); + +module_param(rtw_switch_usb_mode, int, 0644); + +module_param(rtw_hwpwrp_detect, int, 0644); + +module_param(rtw_hw_wps_pbc, int, 0644); +module_param(rtw_check_hw_status, int, 0644); + +#ifdef CONFIG_PCI_HCI +module_param(rtw_pci_aspm_enable, int, 0644); +#endif + +#ifdef CONFIG_TX_EARLY_MODE +module_param(rtw_early_mode, int, 0644); +#endif +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE +char *rtw_adaptor_info_caching_file_path = "/data/misc/wifi/rtw_cache"; +module_param(rtw_adaptor_info_caching_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file"); +#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */ + +#ifdef CONFIG_LAYER2_ROAMING +uint rtw_max_roaming_times = 2; +module_param(rtw_max_roaming_times, uint, 0644); +MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try"); +#endif /* CONFIG_LAYER2_ROAMING */ + +#ifdef CONFIG_FILE_FWIMG +char *rtw_fw_file_path = CONFIG_FIRMWARE_PATH; /* "/system/etc/firmware/rtlwifi/FW_NIC.BIN"; */ + +module_param(rtw_fw_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image"); + +char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN"; +module_param(rtw_fw_wow_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image"); + +#ifdef CONFIG_MP_INCLUDED +char *rtw_fw_mp_bt_file_path = ""; +module_param(rtw_fw_mp_bt_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image"); +#endif /* CONFIG_MP_INCLUDED */ +#endif /* CONFIG_FILE_FWIMG */ + +uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER; +module_param(rtw_hiq_filter, uint, 0644); +MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all"); + +uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN; +module_param(rtw_adaptivity_en, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable, 2:auto"); + +uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE; +module_param(rtw_adaptivity_mode, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense"); + +int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; +module_param(rtw_adaptivity_th_l2h_ini, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity"); + +int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF; +module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity"); + +#ifdef CONFIG_DFS_MASTER +uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN; +module_param(rtw_dfs_region_domain, uint, 0644); +MODULE_PARM_DESC(rtw_dfs_region_domain, "0:NONE, 1:FCC, 2:MKK, 3:ETSI"); +#endif + +uint rtw_amsdu_mode = RTW_AMSDU_MODE_NON_SPP; +module_param(rtw_amsdu_mode, uint, 0644); +MODULE_PARM_DESC(rtw_amsdu_mode, "0:non-spp, 1:spp, 2:all drop"); + +uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G; +module_param(rtw_amplifier_type_2g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA"); + +uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G; +module_param(rtw_amplifier_type_5g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA"); + +uint rtw_rfe_type = CONFIG_RTW_RFE_TYPE; +module_param(rtw_rfe_type, uint, 0644); +MODULE_PARM_DESC(rtw_rfe_type, "default init value:64"); + +#ifdef CONFIG_DBCC_SUPPORT +/*0:disable ,1: enable*/ +int rtw_dbcc_en = 0; +module_param(rtw_dbcc_en, int, 0644); +MODULE_PARM_DESC(rtw_dbcc_en, "0:Disable, 1:Enable DBCC"); +#endif + +uint rtw_powertracking_type = 64; +module_param(rtw_powertracking_type, uint, 0644); +MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64"); + +uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE; +module_param(rtw_GLNA_type, uint, 0644); +MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0"); + +uint rtw_TxBBSwing_2G = 0xFF; +module_param(rtw_TxBBSwing_2G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF"); + +uint rtw_TxBBSwing_5G = 0xFF; +module_param(rtw_TxBBSwing_5G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF"); + +uint rtw_OffEfuseMask = 0; +module_param(rtw_OffEfuseMask, uint, 0644); +MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0"); + +uint rtw_FileMaskEfuse = 0; +module_param(rtw_FileMaskEfuse, uint, 0644); +MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0"); + +uint rtw_rxgain_offset_2g = 0; +module_param(rtw_rxgain_offset_2g, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0"); + +uint rtw_rxgain_offset_5gl = 0; +module_param(rtw_rxgain_offset_5gl, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0"); + +uint rtw_rxgain_offset_5gm = 0; +module_param(rtw_rxgain_offset_5gm, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0"); + +uint rtw_rxgain_offset_5gh = 0; +module_param(rtw_rxgain_offset_5gh, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0"); + +uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; +module_param(rtw_pll_ref_clk_sel, uint, 0644); +MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); + +int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN; +module_param(rtw_tx_pwr_by_rate, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); + +#if CONFIG_TXPWR_LIMIT +int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN; +module_param(rtw_tx_pwr_lmt_enable, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse"); +#endif + +static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; +static int rtw_target_tx_pwr_2g_a_num = 0; +module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B; +static int rtw_target_tx_pwr_2g_b_num = 0; +module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C; +static int rtw_target_tx_pwr_2g_c_num = 0; +module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D; +static int rtw_target_tx_pwr_2g_d_num = 0; +module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); + +#if CONFIG_IEEE80211_BAND_5GHZ +static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A; +static int rtw_target_tx_pwr_5g_a_num = 0; +module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B; +static int rtw_target_tx_pwr_5g_b_num = 0; +module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C; +static int rtw_target_tx_pwr_5g_c_num = 0; +module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D; +static int rtw_target_tx_pwr_5g_d_num = 0; +module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + +#ifdef CONFIG_RTW_TX_NPATH_EN +/*0:disable ,1: 2path*/ +int rtw_tx_npath_enable = 1; +module_param(rtw_tx_npath_enable, int, 0644); +MODULE_PARM_DESC(rtw_tx_npath_enable, "0:Disable, 1:TX-2PATH"); +#endif + +#ifdef CONFIG_RTW_PATH_DIV +/*0:disable ,1: path diversity*/ +int rtw_path_div_enable = 1; +module_param(rtw_path_div_enable, int, 0644); +MODULE_PARM_DESC(rtw_path_div_enable, "0:Disable, 1:Enable path diversity"); +#endif + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +char *rtw_phy_file_path = REALTEK_CONFIG_PATH; +module_param(rtw_phy_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter"); +/* PHY FILE Bit Map +* BIT0 - MAC_REG, 0: non-support, 1: support +* BIT1 - BB_PHY_REG, 0: non-support, 1: support +* BIT2 - BB_PHY_REG_MP, 0: non-support, 1: support +* BIT3 - RF_RADIO, 0: non-support, 1: support +* BIT4 - RF_TXPWR_BY_RATE, 0: non-support, 1: support +* BIT5 - RF_TXPWR_TRACK, 0: non-support, 1: support +* BIT6 - RF_TXPWR_LMT, 0: non-support, 1: support +* BIT7 - RF_TXPWR_LMT_RU, 0: non-support, 1: support*/ +int rtw_load_phy_file = (BIT1 | BIT3); +module_param(rtw_load_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map"); +int rtw_decrypt_phy_file = 0; +module_param(rtw_decrypt_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File"); +#endif + + +uint rtw_phydm_ability = 0xffffffff; +module_param(rtw_phydm_ability, uint, 0644); + +uint rtw_halrf_ability = 0xffffffff; +module_param(rtw_halrf_ability, uint, 0644); + +#ifdef CONFIG_RTW_MESH +uint rtw_peer_alive_based_preq = 1; +module_param(rtw_peer_alive_based_preq, uint, 0644); +MODULE_PARM_DESC(rtw_peer_alive_based_preq, + "On demand PREQ will reference peer alive status. 0: Off, 1: On"); +#endif + +#ifdef CONFIG_RTW_NAPI +/*following setting should define NAPI in Makefile +enable napi only = 1, disable napi = 0*/ +int rtw_en_napi = 1; +module_param(rtw_en_napi, int, 0644); +#ifdef CONFIG_RTW_NAPI_DYNAMIC +int rtw_napi_threshold = 100; /* unit: Mbps */ +module_param(rtw_napi_threshold, int, 0644); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#ifdef CONFIG_RTW_GRO +/*following setting should define GRO in Makefile +enable gro = 1, disable gro = 0*/ +int rtw_en_gro = 1; +module_param(rtw_en_gro, int, 0644); +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + +#ifdef RTW_IQK_FW_OFFLOAD +int rtw_iqk_fw_offload = 1; +#else +int rtw_iqk_fw_offload; +#endif /* RTW_IQK_FW_OFFLOAD */ +module_param(rtw_iqk_fw_offload, int, 0644); + +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +int rtw_ch_switch_offload = 0; +#else +int rtw_ch_switch_offload; +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ +module_param(rtw_ch_switch_offload, int, 0644); + +#ifdef CONFIG_TDLS +int rtw_en_tdls = 1; +module_param(rtw_en_tdls, int, 0644); +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT +int rtw_fw_param_init = 1; +module_param(rtw_fw_param_init, int, 0644); +#endif + +#ifdef CONFIG_TDMADIG +int rtw_tdmadig_en = 1; +/* +1:MODE_PERFORMANCE +2:MODE_COVERAGE +*/ +int rtw_tdmadig_mode = 1; +int rtw_dynamic_tdmadig = 0; +module_param(rtw_tdmadig_en, int, 0644); +module_param(rtw_tdmadig_mode, int, 0644); +module_param(rtw_dynamic_tdmadig, int, 0644); +#endif/*CONFIG_TDMADIG*/ + +/*dynamic RRSR default enable*/ +int rtw_en_dyn_rrsr = 1; +int rtw_rrsr_value = 0xFFFFFFFF; +module_param(rtw_en_dyn_rrsr, int, 0644); +module_param(rtw_rrsr_value, int, 0644); + +#ifdef CONFIG_WOWLAN +/* + * 0: disable, 1: enable + */ +uint rtw_wow_enable = 1; +module_param(rtw_wow_enable, uint, 0644); +/* + * bit[0]: magic packet wake up + * bit[1]: unucast packet(HW/FW unuicast) + * bit[2]: deauth wake up + */ +uint rtw_wakeup_event = RTW_WAKEUP_EVENT; +module_param(rtw_wakeup_event, uint, 0644); +/* + * 0: common WOWLAN + * bit[0]: disable BB RF + * bit[1]: For wireless remote controller with or without connection + */ +uint rtw_suspend_type = RTW_SUSPEND_TYPE; +module_param(rtw_suspend_type, uint, 0644); +#endif + +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) +int rtw_go_hidden_ssid_mode = ALL_HIDE_SSID; +module_param(rtw_go_hidden_ssid_mode, int, 0644); +#endif + +#ifdef RTW_BUSY_DENY_SCAN +uint rtw_scan_interval_thr = BUSY_TRAFFIC_SCAN_DENY_PERIOD; +module_param(rtw_scan_interval_thr, uint, 0644); +MODULE_PARM_DESC(rtw_scan_interval_thr, "Threshold used to judge if scan " \ + "request comes from scan UI, unit is ms."); +#endif /* RTW_BUSY_DENY_SCAN */ + +#ifdef CONFIG_HW_HDR_CONVERSION +int rtw_hw_hdr_conv = true; +#else +int rtw_hw_hdr_conv = false; +#endif + +#ifdef CONFIG_MCC_MODE +int rtw_mcc_en = _TRUE; +module_param(rtw_mcc_en, int, 0644); +#endif + +#ifdef CONFIG_RTW_MULTI_AP +static int rtw_unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM] = CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE; +static int rtw_unassoc_sta_mode_of_stype_num = 0; +module_param_array(rtw_unassoc_sta_mode_of_stype, int, &rtw_unassoc_sta_mode_of_stype_num, 0644); + +uint rtw_max_unassoc_sta_cnt = 0; +module_param(rtw_max_unassoc_sta_cnt, uint, 0644); +#endif + +#ifdef CONFIG_IOCTL_CFG80211 +uint rtw_roch_min_home_dur = 1500; +uint rtw_roch_max_away_dur = 500; +uint rtw_roch_extend_dur = 500; +module_param(rtw_roch_min_home_dur, uint, 0644); +module_param(rtw_roch_max_away_dur, uint, 0644); +module_param(rtw_roch_extend_dur, uint, 0644); +#endif + +static void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) +{ + int path, rs; + int *target_tx_pwr; + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_2g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_2g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_2g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_2g_d; + + for (rs = CCK; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs]; + } + +#if CONFIG_IEEE80211_BAND_5GHZ + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_5g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_5g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_5g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_5g_d; + + for (rs = OFDM; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1]; + } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ +} + +static inline void rtw_regsty_load_chplan(struct registry_priv *regsty) +{ + u16 chplan = RTW_CHPLAN_UNSPECIFIED; + u16 chplan_6g = RTW_CHPLAN_6G_UNSPECIFIED; + + chplan = rtw_channel_plan; +#if CONFIG_IEEE80211_BAND_6GHZ + chplan_6g = rtw_channel_plan_6g; +#endif + + rtw_chplan_ioctl_input_mapping(&chplan, &chplan_6g); + + regsty->channel_plan = chplan; +#if CONFIG_IEEE80211_BAND_6GHZ + regsty->channel_plan_6g = chplan_6g; +#endif +} + +static inline void rtw_regsty_load_alpha2(struct registry_priv *regsty) +{ + if (strlen(rtw_country_code) != 2 + || (!IS_ALPHA2_WORLDWIDE(rtw_country_code) + && (is_alpha(rtw_country_code[0]) == _FALSE + || is_alpha(rtw_country_code[1]) == _FALSE) + ) + ) { + if (rtw_country_code != rtw_country_unspecified) + RTW_ERR("%s discard rtw_country_code not in alpha2 or \"%s\"\n", __func__, WORLDWIDE_ALPHA2); + SET_UNSPEC_ALPHA2(regsty->alpha2); + } else + _rtw_memcpy(regsty->alpha2, rtw_country_code, 2); +} + +static inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) +{ + int i; + int ch_num = 0; + + for (i = 0; i < MAX_CHANNEL_NUM_2G_5G; i++) + if (((u8)rtw_excl_chs[i]) != 0) + regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i]; + + if (ch_num < MAX_CHANNEL_NUM_2G_5G) + regsty->excl_chs[ch_num] = 0; + +#if CONFIG_IEEE80211_BAND_6GHZ + ch_num = 0; + for (i = 0; i < MAX_CHANNEL_NUM_6G; i++) + if (((u8)rtw_excl_chs_6g[i]) != 0) + regsty->excl_chs_6g[ch_num++] = (u8)rtw_excl_chs_6g[i]; + + if (ch_num < MAX_CHANNEL_NUM_6G) + regsty->excl_chs_6g[ch_num] = 0; +#endif +} + +#ifdef CONFIG_80211D +inline void rtw_regsty_load_country_ie_slave_settings(struct registry_priv *regsty) +{ + regsty->country_ie_slave_en_role = rtw_country_ie_slave_en_role; + regsty->country_ie_slave_en_ifbmp = rtw_country_ie_slave_en_ifbmp; +} +#endif + +#ifdef CONFIG_80211N_HT +static inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty) +{ + int i, j; + uint *sz_limit; + + for (i = 0; i < 4; i++) { + if (i == 0) + sz_limit = rtw_rx_ampdu_sz_limit_1ss; + else if (i == 1) + sz_limit = rtw_rx_ampdu_sz_limit_2ss; + else if (i == 2) + sz_limit = rtw_rx_ampdu_sz_limit_3ss; + else if (i == 3) + sz_limit = rtw_rx_ampdu_sz_limit_4ss; + + for (j = 0; j < 4; j++) + regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j]; + } +} +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_RTW_MULTI_AP +inline void rtw_regsty_init_unassoc_sta_param(struct registry_priv *regsty) +{ + int i; + + for (i = 0; i < UNASOC_STA_SRC_NUM; i++) + regsty->unassoc_sta_mode_of_stype[i] = rtw_unassoc_sta_mode_of_stype[i]; + + regsty->max_unassoc_sta_cnt = (u16)rtw_max_unassoc_sta_cnt; +} +#endif + +static void rtw_load_phy_file_path (struct dvobj_priv *dvobj) +{ + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (rtw_load_phy_file & LOAD_BB_PHY_REG_FILE) { + phl_com->phy_sw_cap[0].bb_phy_reg_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].bb_phy_reg_info.para_src = RTW_PARA_SRC_EXTNAL; + } + + if (rtw_load_phy_file & LOAD_RF_RADIO_FILE) { + phl_com->phy_sw_cap[0].rf_radio_a_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_radio_a_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[0].rf_radio_b_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_radio_b_info.para_src = RTW_PARA_SRC_EXTNAL; + } + + if (rtw_load_phy_file & LOAD_RF_TXPWR_BY_RATE) { + phl_com->phy_sw_cap[0].rf_txpwr_byrate_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_txpwr_byrate_info.para_src = RTW_PARA_SRC_EXTNAL; + } + + if (rtw_load_phy_file & LOAD_RF_TXPWR_TRACK_FILE) { + phl_com->phy_sw_cap[0].rf_txpwrtrack_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_txpwrtrack_info.para_src = RTW_PARA_SRC_EXTNAL; + } + + if (rtw_load_phy_file & LOAD_RF_TXPWR_LMT_FILE) { + phl_com->phy_sw_cap[0].rf_txpwrlmt_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_txpwrlmt_info.para_src = RTW_PARA_SRC_EXTNAL; + } + + if (rtw_load_phy_file & LOAD_RF_TXPWR_LMT_RU_FILE) { + phl_com->phy_sw_cap[0].rf_txpwrlmt_ru_info.para_src = RTW_PARA_SRC_EXTNAL; + phl_com->phy_sw_cap[1].rf_txpwrlmt_ru_info.para_src = RTW_PARA_SRC_EXTNAL; + } +#endif/* CONFIG_LOAD_PHY_PARA_FROM_FILE */ +} + +void rtw_core_update_default_setting (struct dvobj_priv *dvobj) +{ + struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj); + + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + rtw_load_phy_file_path(dvobj); + #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ + + phl_com->dev_sw_cap.fw_cap.dlram_en = true; + phl_com->dev_sw_cap.fw_cap.dlrom_en = false; + #ifdef CONFIG_FILE_FWIMG + phl_com->dev_sw_cap.fw_cap.fw_src = RTW_FW_SRC_EXTNAL; + #else /* !CONFIG_FILE_FWIMG */ + phl_com->dev_sw_cap.fw_cap.fw_src = RTW_FW_SRC_INTNAL; + #endif /* !CONFIG_FILE_FWIMG */ + + phl_com->phy_sw_cap[0].proto_sup = rtw_wireless_mode; + phl_com->phy_sw_cap[0].band_sup = rtw_band_type; + phl_com->phy_sw_cap[0].bw_sup = BW_CAP_80M | BW_CAP_40M | BW_CAP_20M; //rtw_bw_mode; + phl_com->phy_sw_cap[0].txss = rtw_tx_nss; + phl_com->phy_sw_cap[0].rxss = rtw_rx_nss; + + phl_com->phy_sw_cap[1].proto_sup = rtw_wireless_mode; + phl_com->phy_sw_cap[1].band_sup = rtw_band_type; + phl_com->phy_sw_cap[1].bw_sup = rtw_bw_mode; + phl_com->phy_sw_cap[1].txss = rtw_tx_nss; + phl_com->phy_sw_cap[1].rxss = rtw_rx_nss; + + phl_com->phy_sw_cap[0].hw_rts_time_th = 88; + phl_com->phy_sw_cap[0].hw_rts_len_th = 4080; + phl_com->phy_sw_cap[1].hw_rts_time_th = 88; + phl_com->phy_sw_cap[1].hw_rts_len_th = 4080; + + /*phl_com->dev_sw_cap.pkg_type = rtw_pkg_type;*/ + phl_com->dev_sw_cap.rfe_type = rtw_rfe_type; +#ifdef DBG_LA_MODE + phl_com->dev_sw_cap.la_mode = rtw_la_mode_en; +#endif +#ifdef CONFIG_DBCC_SUPPORT + phl_com->dev_sw_cap.dbcc_sup = rtw_dbcc_en; +#endif + + phl_com->dev_sw_cap.hw_hdr_conv = rtw_hw_hdr_conv; + + phl_com->proto_sw_cap[0].max_amsdu_len = rtw_max_amsdu_len; + phl_com->proto_sw_cap[1].max_amsdu_len = rtw_max_amsdu_len; + +#if defined(CONFIG_PCI_HCI) + #if !defined(CONFIG_PCI_ASPM) + /* Disable all PCIE Backdoor to avoid PCIE IOT */ + phl_com->bus_sw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; + phl_com->bus_sw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; + phl_com->bus_sw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; + phl_com->bus_sw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT; + phl_com->bus_sw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; + #endif + phl_com->bus_sw_cap.txbd_num = 256; + phl_com->bus_sw_cap.rxbd_num = 256; + phl_com->bus_sw_cap.rpbd_num = 0; /* by default */ +#ifdef CONFIG_RXBUF_NUM_1024 + phl_com->bus_sw_cap.rxbuf_num = 1024; +#else + phl_com->bus_sw_cap.rxbuf_num = 512; +#endif + phl_com->bus_sw_cap.rpbuf_num = 0; /* by default */ +#endif /*CONFIG_PCI_HCI*/ + +#ifdef CONFIG_BTC + phl_com->dev_sw_cap.btc_mode = BTC_MODE_NORMAL; +#else + phl_com->dev_sw_cap.btc_mode = BTC_MODE_WL; +#endif +#ifdef CONFIG_MCC_MODE + phl_com->dev_sw_cap.mcc_sup = rtw_mcc_en; +#endif +#ifdef CONFIG_USB_HCI + phl_com->bus_sw_cap.tx_buf_size = MAX_XMITBUF_SZ; + phl_com->bus_sw_cap.tx_buf_num = NR_XMITBUFF; + phl_com->bus_sw_cap.tx_mgnt_buf_size = MAX_MGNT_XMITBUF_SZ; + phl_com->bus_sw_cap.tx_mgnt_buf_num = NR_MGNT_XMITBUFF; + phl_com->bus_sw_cap.rx_buf_size = MAX_RECVBUF_SZ; + phl_com->bus_sw_cap.rx_buf_num = NR_RECVBUFF; + phl_com->bus_sw_cap.in_token_num = NR_RECV_URB; +#endif +#ifdef CONFIG_SDIO_HCI +#ifdef MAX_XMITBUF_SZ + phl_com->bus_sw_cap.tx_buf_size = MAX_XMITBUF_SZ; +#endif +#ifdef NR_XMITBUFF + phl_com->bus_sw_cap.tx_buf_num = NR_XMITBUFF; +#endif +#ifdef MAX_MGNT_XMITBUF_SZ + phl_com->bus_sw_cap.tx_mgnt_buf_size = MAX_MGNT_XMITBUF_SZ; +#endif +#ifdef NR_MGNT_XMITBUFF + phl_com->bus_sw_cap.tx_mgnt_buf_num = NR_MGNT_XMITBUFF; +#endif +#ifdef MAX_RECVBUF_SZ + phl_com->bus_sw_cap.rx_buf_size = MAX_RECVBUF_SZ; +#endif +#ifdef NR_RECVBUFF + phl_com->bus_sw_cap.rx_buf_num = NR_RECVBUFF; +#endif +#endif /* CONFIG_SDIO_HCI */ + + /* Set STBC Tx/Rx sw role cap */ + phl_com->role_sw_cap.stbc_cap = 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT5) ? HW_CAP_STBC_HT_TX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT1) ? HW_CAP_STBC_VHT_TX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT10) ? HW_CAP_STBC_HE_TX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT11) ? HW_CAP_STBC_HE_TX_GT_80M : 0; + + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT4) ? HW_CAP_STBC_HT_RX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT0) ? HW_CAP_STBC_VHT_RX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT8) ? HW_CAP_STBC_HE_RX : 0; + phl_com->role_sw_cap.stbc_cap |= + (rtw_stbc_cap & BIT9) ? HW_CAP_STBC_HE_RX_GT_80M : 0; + + /*Band0*/ + phl_com->proto_sw_cap[0].stbc_ht_tx = (rtw_stbc_cap & BIT5) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_vht_tx = (rtw_stbc_cap & BIT1) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_he_tx = (rtw_stbc_cap & BIT10) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_tx_greater_80mhz = (rtw_stbc_cap & BIT11) ? 1 : 0; + + phl_com->proto_sw_cap[0].stbc_ht_rx = (rtw_stbc_cap & BIT4) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_vht_rx = (rtw_stbc_cap & BIT0) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_he_rx = (rtw_stbc_cap & BIT8) ? 1 : 0; + phl_com->proto_sw_cap[0].stbc_rx_greater_80mhz = (rtw_stbc_cap & BIT9) ? 1 : 0; + + /*Band1*/ + phl_com->proto_sw_cap[1].stbc_ht_tx = (rtw_stbc_cap & BIT5) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_vht_tx = (rtw_stbc_cap & BIT1) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_he_tx = (rtw_stbc_cap & BIT10) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_tx_greater_80mhz = (rtw_stbc_cap & BIT11) ? 1 : 0; + + phl_com->proto_sw_cap[1].stbc_ht_rx = (rtw_stbc_cap & BIT4) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_vht_rx = (rtw_stbc_cap & BIT0) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_he_rx = (rtw_stbc_cap & BIT8) ? 1 : 0; + phl_com->proto_sw_cap[1].stbc_rx_greater_80mhz = (rtw_stbc_cap & BIT9) ? 1 : 0; + +#ifdef CONFIG_BEAMFORMING + phl_com->role_sw_cap.bf_cap = 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT0) ? HW_CAP_BFER_VHT_SU : 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT1) ? HW_CAP_BFEE_VHT_SU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT2) ? HW_CAP_BFER_VHT_MU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT3) ? HW_CAP_BFEE_VHT_MU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT4) ? HW_CAP_BFER_HT_SU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT5) ? HW_CAP_BFEE_HT_SU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT6) ? HW_CAP_BFER_HE_SU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT7) ? HW_CAP_BFEE_HE_SU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT8) ? HW_CAP_BFER_HE_MU: 0; + phl_com->role_sw_cap.bf_cap |= (rtw_beamform_cap & BIT9) ? HW_CAP_BFEE_HE_MU: 0; + + /*Band0*/ + phl_com->proto_sw_cap[0].vht_su_bfmr = (rtw_sw_proto_bf_cap_phy0 & BIT0) ? 1 : 0; + phl_com->proto_sw_cap[0].vht_su_bfme = (rtw_sw_proto_bf_cap_phy0 & BIT1) ? 1 : 0; + phl_com->proto_sw_cap[0].vht_mu_bfmr = (rtw_sw_proto_bf_cap_phy0 & BIT2) ? 1 : 0; + phl_com->proto_sw_cap[0].vht_mu_bfme = (rtw_sw_proto_bf_cap_phy0 & BIT3) ? 1 : 0; + phl_com->proto_sw_cap[0].ht_su_bfmr = (rtw_sw_proto_bf_cap_phy0 & BIT4) ? 1 : 0; + phl_com->proto_sw_cap[0].ht_su_bfme = (rtw_sw_proto_bf_cap_phy0 & BIT5) ? 1 : 0; + phl_com->proto_sw_cap[0].he_su_bfmr = (rtw_sw_proto_bf_cap_phy0 & BIT6) ? 1 : 0; + phl_com->proto_sw_cap[0].he_su_bfme = (rtw_sw_proto_bf_cap_phy0 & BIT7) ? 1 : 0; + phl_com->proto_sw_cap[0].he_mu_bfmr = (rtw_sw_proto_bf_cap_phy0 & BIT8) ? 1 : 0; + phl_com->proto_sw_cap[0].he_mu_bfme = (rtw_sw_proto_bf_cap_phy0 & BIT9) ? 1 : 0; + + /*Band1*/ + phl_com->proto_sw_cap[1].vht_su_bfmr = (rtw_sw_proto_bf_cap_phy1 & BIT0) ? 1 : 0; + phl_com->proto_sw_cap[1].vht_su_bfme = (rtw_sw_proto_bf_cap_phy1 & BIT1) ? 1 : 0; + phl_com->proto_sw_cap[1].vht_mu_bfmr = (rtw_sw_proto_bf_cap_phy1 & BIT2) ? 1 : 0; + phl_com->proto_sw_cap[1].vht_mu_bfme = (rtw_sw_proto_bf_cap_phy1 & BIT3) ? 1 : 0; + phl_com->proto_sw_cap[1].ht_su_bfmr = (rtw_sw_proto_bf_cap_phy1 & BIT4) ? 1 : 0; + phl_com->proto_sw_cap[1].ht_su_bfme = (rtw_sw_proto_bf_cap_phy1 & BIT5) ? 1 : 0; + phl_com->proto_sw_cap[1].he_su_bfmr = (rtw_sw_proto_bf_cap_phy1 & BIT6) ? 1 : 0; + phl_com->proto_sw_cap[1].he_su_bfme = (rtw_sw_proto_bf_cap_phy1 & BIT7) ? 1 : 0; + phl_com->proto_sw_cap[1].he_mu_bfmr = (rtw_sw_proto_bf_cap_phy1 & BIT8) ? 1 : 0; + phl_com->proto_sw_cap[1].he_mu_bfme = (rtw_sw_proto_bf_cap_phy1 & BIT9) ? 1 : 0; +#endif + +#if CONFIG_TXPWR_LIMIT + if (rtw_tx_pwr_lmt_enable == 2) + phl_com->dev_sw_cap.pwrlmt_type = RTW_PWLMT_BY_EFUSE; + else if (rtw_tx_pwr_lmt_enable == 1) + phl_com->dev_sw_cap.pwrlmt_type = RTW_PWBYRATE_AND_PWLMT; + else if (rtw_tx_pwr_lmt_enable == 0) + phl_com->dev_sw_cap.pwrlmt_type = RTW_PWLMT_DISABLE; +#else + phl_com->dev_sw_cap.pwrlmt_type = RTW_PWLMT_DISABLE; +#endif + + if (rtw_tx_pwr_by_rate == 1) + phl_com->dev_sw_cap.pwrbyrate_off = RTW_PW_BY_RATE_ON; + else if (rtw_tx_pwr_by_rate == 0) + phl_com->dev_sw_cap.pwrbyrate_off = RTW_PW_BY_RATE_ALL_SAME; + else + phl_com->dev_sw_cap.pwrbyrate_off = RTW_PW_BY_RATE_ON; + + /* If rf_board_opt is not assigned to specific value, it must be set to 0xFF as default. */ + phl_com->dev_sw_cap.rf_board_opt = 0xFF; + +#ifdef CONFIG_RTW_IPS + phl_com->dev_sw_cap.ps_cap.ips_en = rtw_ips_mode; +#endif +#ifdef CONFIG_RTW_LPS + phl_com->dev_sw_cap.ps_cap.lps_en = rtw_lps_mode; + phl_com->dev_sw_cap.ps_cap.lps_cap = rtw_lps_cap; +#endif + +#ifdef CONFIG_RTW_LED + rtw_phl_led_set_ctrl_mode(GET_PHL_INFO(dvobj), 0, RTW_LED_CTRL_HW_TX_MODE); +#endif + +#if defined (CONFIG_RPQ_AGG_NUM) && (CONFIG_RPQ_AGG_NUM > 0) + phl_com->dev_sw_cap.rpq_agg_num = CONFIG_RPQ_AGG_NUM; +#else + phl_com->dev_sw_cap.rpq_agg_num = 0; /* MAC default num: 121 for all IC */ +#endif +} + +u8 rtw_load_dvobj_registry(struct dvobj_priv *dvobj) +{ + /*struct rtw_phl_com_t *phl_com = GET_PHL_COM(dvobj);*/ + #ifdef CONFIG_CONCURRENT_MODE + dvobj->virtual_iface_num = (u8)rtw_virtual_iface_num; + #endif + return _SUCCESS; +} +uint rtw_load_registry(_adapter *padapter) +{ + uint status = _SUCCESS; + struct registry_priv *registry_par = &padapter->registrypriv; + + +#ifdef CONFIG_RTW_DEBUG + if (rtw_drv_log_level >= _DRV_MAX_) + rtw_drv_log_level = _DRV_DEBUG_; +#endif + + registry_par->chip_version = (u8)rtw_chip_version; + registry_par->rfintfs = (u8)rtw_rfintfs; + registry_par->lbkmode = (u8)rtw_lbkmode; + /* registry_par->hci = (u8)hci; */ + registry_par->network_mode = (u8)rtw_network_mode; + + _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); + registry_par->ssid.SsidLength = 3; + + registry_par->channel = (u8)rtw_channel; +#ifdef CONFIG_NARROWBAND_SUPPORTING + if (rtw_nb_config != RTW_NB_CONFIG_NONE) + rtw_wireless_mode &= ~WIRELESS_11B; +#endif + registry_par->wireless_mode = (u8)rtw_wireless_mode; + registry_par->band_type = (u8)rtw_band_type; + + if (is_supported_24g(registry_par->band_type) && (!is_supported_5g(registry_par->band_type)) + && (registry_par->channel > 14)) + registry_par->channel = 1; + else if (is_supported_5g(registry_par->band_type) && (!is_supported_24g(registry_par->band_type)) + && (registry_par->channel <= 14)) + registry_par->channel = 36; + + registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; + registry_par->vcs_type = (u8)rtw_vcs_type; + registry_par->rts_thresh = (u16)rtw_rts_thresh; + registry_par->hw_rts_en = (u8)rtw_hw_rts_en; + registry_par->frag_thresh = (u16)rtw_frag_thresh; + registry_par->preamble = (u8)rtw_preamble; + registry_par->scan_mode = (u8)rtw_scan_mode; + registry_par->smart_ps = (u8)rtw_smart_ps; + registry_par->check_fw_ps = (u8)rtw_check_fw_ps; + #ifdef CONFIG_TDMADIG + registry_par->tdmadig_en = (u8)rtw_tdmadig_en; + registry_par->tdmadig_mode = (u8)rtw_tdmadig_mode; + registry_par->tdmadig_dynamic = (u8) rtw_dynamic_tdmadig; + registry_par->power_mgnt = PM_PS_MODE_ACTIVE; + registry_par->ips_mode = IPS_NONE; + #else + registry_par->power_mgnt = (u8)rtw_power_mgnt; + registry_par->ips_mode = (u8)rtw_ips_mode; + #endif/*CONFIG_TDMADIG*/ + registry_par->lps_level = (u8)rtw_lps_level; + registry_par->en_dyn_rrsr = (u8)rtw_en_dyn_rrsr; + registry_par->set_rrsr_value = (u32)rtw_rrsr_value; +#ifdef CONFIG_LPS_1T1R + registry_par->lps_1t1r = (u8)(rtw_lps_1t1r ? 1 : 0); +#endif + registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp; +#ifdef CONFIG_WOWLAN + registry_par->wow_power_mgnt = (u8)rtw_wow_power_mgnt; + registry_par->wow_lps_level = (u8)rtw_wow_lps_level; + #ifdef CONFIG_LPS_1T1R + registry_par->wow_lps_1t1r = (u8)(rtw_wow_lps_1t1r ? 1 : 0); + #endif +#endif /* CONFIG_WOWLAN */ + registry_par->radio_enable = (u8)rtw_radio_enable; + registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; + registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; + registry_par->busy_thresh = (u16)rtw_busy_thresh; + registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt; + /* registry_par->qos_enable = (u8)rtw_qos_enable; */ + registry_par->ack_policy = (u8)rtw_ack_policy; + registry_par->mp_mode = (u8)rtw_mp_mode; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + registry_par->mp_customer_str = (u8)rtw_mp_customer_str; +#endif + registry_par->software_encrypt = (u8)rtw_software_encrypt; + registry_par->software_decrypt = (u8)rtw_software_decrypt; + + registry_par->acm_method = (u8)rtw_acm_method; + registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; + registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; + + /* WMM */ + registry_par->wmm_enable = (u8)rtw_wmm_enable; + +#ifdef CONFIG_WMMPS_STA + /* UAPSD */ + registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp; + registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable; + registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ + + registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; + + registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode; + +#ifdef CONFIG_80211N_HT + registry_par->ht_enable = (u8)rtw_ht_enable; + if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) { +#ifdef CONFIG_NARROWBAND_SUPPORTING + if (rtw_nb_config != RTW_NB_CONFIG_NONE) + rtw_bw_mode = 0; +#endif + registry_par->bw_mode = (u8)rtw_bw_mode; + registry_par->ampdu_enable = (u8)rtw_ampdu_enable; + registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; +#ifdef CONFIG_DISBALE_RX_AMSDU_FOR_BUS_LOW_SPEED +#ifdef CONFIG_USB_HCI + if (dvobj_to_usb(adapter_to_dvobj(padapter))->usb_speed < RTW_USB_SPEED_SUPER) + registry_par->rx_ampdu_amsdu = 0; +#endif +#endif + registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; + registry_par->tx_quick_addba_req = (u8)rtw_quick_addba_req; + registry_par->short_gi = (u8)rtw_short_gi; + registry_par->ldpc_cap = (u8)rtw_ldpc_cap; + +#ifdef CONFIG_RTW_TX_NPATH_EN + registry_par->tx_npath = (u8)rtw_tx_npath_enable; +#endif +#ifdef CONFIG_RTW_PATH_DIV + registry_par->path_div = (u8)rtw_path_div_enable; +#endif + registry_par->stbc_cap = (u16)rtw_stbc_cap; +#ifdef CONFIG_BEAMFORMING + registry_par->beamform_cap = (u8)rtw_beamform_cap; + registry_par->dyn_txbf = (u8)rtw_dyn_txbf; + registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; + registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; +#endif + rtw_regsty_init_rx_ampdu_sz_limit(registry_par); + } +#endif + +#if 0 +int rtw_short_gi = 0xf; +/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ +int rtw_ldpc_cap = 0x33; +/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ +int rtw_stbc_cap = 0x13; +#endif + +#ifdef DBG_LA_MODE + registry_par->la_mode_en = (u8)rtw_la_mode_en; +#endif +#ifdef CONFIG_NARROWBAND_SUPPORTING + registry_par->rtw_nb_config = (u8)rtw_nb_config; +#endif + +#ifdef CONFIG_80211AC_VHT + registry_par->vht_enable = (u8)rtw_vht_enable; + registry_par->vht_24g_enable = (u8)rtw_vht_24g_enable; + registry_par->ampdu_factor = (u8)rtw_ampdu_factor; + registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF); + registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8); +#endif + +#ifdef CONFIG_80211AX_HE + registry_par->he_enable = (u8)rtw_he_enable; +#endif + +#ifdef CONFIG_TX_EARLY_MODE + registry_par->early_mode = (u8)rtw_early_mode; +#endif + registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit; + registry_par->rf_path = (u8)rtw_rf_path; /*rf_config/rtw_rf_config*/ + registry_par->tx_nss = (u8)rtw_tx_nss; + registry_par->rx_nss = (u8)rtw_rx_nss; + registry_par->low_power = (u8)rtw_low_power; + + registry_par->check_hw_status = (u8)rtw_check_hw_status; + + registry_par->wifi_spec = (u8)rtw_wifi_spec; + +#ifdef CONFIG_REGD_SRC_FROM_OS + if (regd_src_is_valid(rtw_regd_src)) + registry_par->regd_src = (u8)rtw_regd_src; + else { + RTW_WARN("%s invalid rtw_regd_src(%u), use REGD_SRC_RTK_PRIV instead\n", __func__, rtw_regd_src); + registry_par->regd_src = REGD_SRC_RTK_PRIV; + } +#endif + + rtw_regsty_load_alpha2(registry_par); + rtw_regsty_load_chplan(registry_par); + rtw_regsty_load_excl_chs(registry_par); +#ifdef CONFIG_80211D + rtw_regsty_load_country_ie_slave_settings(registry_par); +#endif + + registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake; +#ifdef CONFIG_BTC + registry_par->btcoex = (u8)rtw_btcoex_enable; + registry_par->bt_iso = (u8)rtw_bt_iso; + registry_par->bt_sco = (u8)rtw_bt_sco; + registry_par->bt_ampdu = (u8)rtw_bt_ampdu; + registry_par->ant_num = (u8)rtw_ant_num; + registry_par->single_ant_path = (u8) rtw_single_ant_path; +#endif + + registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; + + registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; + registry_par->antdiv_type = (u8)rtw_antdiv_type; + + registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch; + + registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode; + + registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; + +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path); + registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0; +#endif + +#ifdef CONFIG_LAYER2_ROAMING + registry_par->max_roaming_times = (u8)rtw_max_roaming_times; +#endif + + snprintf(registry_par->ifname, 16, "%s", ifname); + snprintf(registry_par->if2name, 16, "%s", if2name); + +#if defined(CONFIG_CONCURRENT_MODE) && !RTW_P2P_GROUP_INTERFACE +#ifdef CONFIG_P2P + if (CONFIG_RTW_STATIC_NDEV_NUM <= rtw_sel_p2p_iface) { + RTW_ERR("rtw_sel_p2p_iface out of range\n"); + rtw_sel_p2p_iface = CONFIG_RTW_STATIC_NDEV_NUM - 1; + } + + registry_par->sel_p2p_iface = (u8)rtw_sel_p2p_iface; + RTW_INFO("%s, Select P2P interface: iface_id:%d\n", __func__, registry_par->sel_p2p_iface); +#endif +#endif + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST + registry_par->ignore_go_in_scan = (u8)rtw_ignore_go_in_scan; + registry_par->ignore_low_rssi_in_scan = rtw_ignore_low_rssi_in_scan; +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ + registry_par->vo_edca = rtw_vo_edca; + + registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; + + rtw_regsty_load_target_tx_power(registry_par); + + registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; + registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; + registry_par->bEn_RFE = 1; + registry_par->RFE_Type = (u8)rtw_rfe_type; + registry_par->PowerTracking_Type = (u8)rtw_powertracking_type; + registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g; + registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g; + registry_par->GLNA_Type = (u8)rtw_GLNA_type; +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + registry_par->load_phy_file = (u8)rtw_load_phy_file; + registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file; +#endif + registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable; + + registry_par->hiq_filter = (u8)rtw_hiq_filter; + + registry_par->adaptivity_en = (u8)rtw_adaptivity_en; + registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode; + registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; + registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; + + registry_par->boffefusemask = (u8)rtw_OffEfuseMask; + registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; + registry_par->bBTFileMaskEfuse = (u8)rtw_FileMaskEfuse; + +#ifdef CONFIG_RTW_ACS + registry_par->acs_mode = (u8)rtw_acs; + registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan; +#endif + + registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g; + registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl; + registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm; + registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh; + +#ifdef CONFIG_DFS_MASTER + registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain; + if (registry_par->dfs_region_domain != RTW_DFS_REGD_NONE) { + RTW_WARN("%s force disable radar detection capability for now\n", __func__); + registry_par->dfs_region_domain = RTW_DFS_REGD_NONE; + } + #ifdef CONFIG_REGD_SRC_FROM_OS + if (rtw_regd_src == REGD_SRC_OS && registry_par->dfs_region_domain != RTW_DFS_REGD_NONE) { + RTW_WARN("%s force disable radar detection capability when regd_src is OS\n", __func__); + registry_par->dfs_region_domain = RTW_DFS_REGD_NONE; + } + #endif +#endif + +#ifdef CONFIG_WOWLAN + registry_par->wowlan_enable = rtw_wow_enable; + registry_par->wakeup_event = rtw_wakeup_event; + registry_par->suspend_type = rtw_suspend_type; +#endif + + registry_par->wowlan_sta_mix_mode = rtw_wowlan_sta_mix_mode; + +#ifdef CONFIG_PCI_HCI + registry_par->pci_aspm_config = rtw_pci_aspm_enable; + registry_par->pci_dynamic_aspm_linkctrl = rtw_pci_dynamic_aspm_linkctrl; +#endif + +#ifdef CONFIG_RTW_NAPI + registry_par->en_napi = (u8)rtw_en_napi; +#ifdef CONFIG_RTW_NAPI_DYNAMIC + registry_par->napi_threshold = (u32)rtw_napi_threshold; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#ifdef CONFIG_RTW_GRO + registry_par->en_gro = (u8)rtw_en_gro; + if (!registry_par->en_napi && registry_par->en_gro) { + registry_par->en_gro = 0; + RTW_WARN("Disable GRO because NAPI is not enabled\n"); + } +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + + registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload; + registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload; + +#ifdef CONFIG_TDLS + registry_par->en_tdls = rtw_en_tdls; +#endif + + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + registry_par->fw_param_init = rtw_fw_param_init; +#endif +#ifdef CONFIG_AP_MODE + registry_par->bmc_tx_rate = rtw_bmc_tx_rate; + #if CONFIG_RTW_AP_DATA_BMC_TO_UC + registry_par->ap_src_b2u_flags = rtw_ap_src_b2u_flags; + registry_par->ap_fwd_b2u_flags = rtw_ap_fwd_b2u_flags; + #endif +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + registry_par->msrc_b2u_flags = rtw_msrc_b2u_flags; + registry_par->mfwd_b2u_flags = rtw_mfwd_b2u_flags; + #endif +#endif /* CONFIG_RTW_MESH */ + + registry_par->phydm_ability = rtw_phydm_ability; + registry_par->halrf_ability = rtw_halrf_ability; +#ifdef CONFIG_RTW_MESH + registry_par->peer_alive_based_preq = rtw_peer_alive_based_preq; +#endif + +#ifdef RTW_BUSY_DENY_SCAN + registry_par->scan_interval_thr = rtw_scan_interval_thr; +#endif + +#ifdef CONFIG_RTW_MULTI_AP + rtw_regsty_init_unassoc_sta_param(registry_par); +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + registry_par->roch_min_home_dur = (u16)rtw_roch_min_home_dur; + registry_par->roch_max_away_dur = (u16)rtw_roch_max_away_dur; + registry_par->roch_extend_dur = (u16)rtw_roch_extend_dur; +#endif + +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) + registry_par->go_hidden_ssid_mode = rtw_go_hidden_ssid_mode; + ATOMIC_SET(®istry_par->set_hide_ssid_timer, 0); +#endif + registry_par->amsdu_mode = (u8)rtw_amsdu_mode; + return status; +} + +static void rtw_cfg_adaptivity_en_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_"); + + if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) + _RTW_PRINT_SEL(sel, "DISABLE\n"); + else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) + _RTW_PRINT_SEL(sel, "ENABLE\n"); + else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO) + _RTW_PRINT_SEL(sel, "AUTO\n"); + else + _RTW_PRINT_SEL(sel, "INVALID\n"); +} + +static void rtw_cfg_adaptivity_mode_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + if (regsty->adaptivity_en != RTW_ADAPTIVITY_EN_ENABLE) + return; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_"); + + if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) + _RTW_PRINT_SEL(sel, "NORMAL\n"); + else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) + _RTW_PRINT_SEL(sel, "CARRIER_SENSE\n"); + else + _RTW_PRINT_SEL(sel, "INVALID\n"); +} + +void rtw_cfg_adaptivity_config_msg(void *sel, _adapter *adapter) +{ + rtw_cfg_adaptivity_en_msg(sel, adapter); + rtw_cfg_adaptivity_mode_msg(sel, adapter); +} + +bool rtw_cfg_adaptivity_needed(_adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + bool ret = _FALSE; + + if (regsty->adaptivity_en) + ret = _TRUE; + + return ret; +} + diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index 53153ba..1a4cb05 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -175,7 +175,7 @@ struct sk_buff *rtw_cfg80211_vendor_event_alloc( int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, struct net_device *dev, int event_id, const void *data, int len) { - gfp_t kflags; + int kflags; struct sk_buff *skb; kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; @@ -240,25 +240,19 @@ static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy, #define WIFI_FEATURE_CONTROL_ROAMING 0x800000 // Enable/Disable firmware roaming #define WIFI_FEATURE_IE_WHITELIST 0x1000000 // Support Probe IE white listing #define WIFI_FEATURE_SCAN_RAND 0x2000000 // Support MAC & Probe Sequence Number randomization -#define WIFI_FEATURE_SET_TX_POWER_LIMIT 0x4000000 // Support Tx Power Limit setting -#define WIFI_FEATURE_USE_BODY_HEAD_SAR 0x8000000 // Support Using Body/Head Proximity for SAR -#define WIFI_FEATURE_SET_LATENCY_MODE 0x40000000 // Support Latency mode setting -#define WIFI_FEATURE_P2P_RAND_MAC 0x80000000 // Support Support P2P MAC randomization // Add more features here #define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3 -#include int rtw_dev_get_feature_set(struct net_device *dev) { _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); int feature_set = 0; feature_set |= WIFI_FEATURE_INFRA; #if CONFIG_IEEE80211_BAND_5GHZ - if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode)) + if (is_supported_5g(adapter_to_regsty(adapter)->band_type)) feature_set |= WIFI_FEATURE_INFRA_5G; #endif @@ -280,9 +274,7 @@ int rtw_dev_get_feature_set(struct net_device *dev) #ifdef CONFIG_RTW_WIFI_HAL feature_set |= WIFI_FEATURE_CONFIG_NDO; -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) feature_set |= WIFI_FEATURE_SCAN_RAND; -#endif #endif return feature_set; @@ -784,7 +776,7 @@ static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy, switch (type) { case GSCAN_ATTRIBUTE_BSSID: - memcpy(&(pbssid[j].macaddr), + _rtw_memcpy(&(pbssid[j].macaddr), nla_data(inner), ETHER_ADDR_LEN); break; case GSCAN_ATTRIBUTE_RSSI_LOW: @@ -897,7 +889,7 @@ static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy, nla_for_each_nested(inner, outer, tmp1) { switch (nla_type(inner)) { case GSCAN_ATTRIBUTE_BSSID: - memcpy(&(pbssid[j].macaddr), + _rtw_memcpy(&(pbssid[j].macaddr), nla_data(inner), ETHER_ADDR_LEN); break; @@ -1031,7 +1023,7 @@ static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev type = nla_type(iter2); switch (type) { case RTT_ATTRIBUTE_TARGET_MAC: - memcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN); + _rtw_memcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN); break; case RTT_ATTRIBUTE_TARGET_TYPE: rtt_target->type = nla_get_u8(iter2); @@ -1040,7 +1032,7 @@ static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev rtt_target->peer = nla_get_u8(iter2); break; case RTT_ATTRIBUTE_TARGET_CHAN: - memcpy(&rtt_target->channel, nla_data(iter2), + _rtw_memcpy(&rtt_target->channel, nla_data(iter2), sizeof(rtt_target->channel)); break; case RTT_ATTRIBUTE_TARGET_MODE: @@ -1104,7 +1096,7 @@ static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_ break; case RTT_ATTRIBUTE_TARGET_MAC: if (mac_addr) - memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN); + _rtw_memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN); else { WL_ERR(("mac_list is NULL\n")); goto exit; @@ -1154,7 +1146,6 @@ enum { static void LinkLayerStats(_adapter *padapter) { struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct recv_priv *precvpriv = &(padapter->recvpriv); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); u32 ps_time, trx_total_time; @@ -1309,8 +1300,6 @@ static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy, { _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); - - struct recv_priv *precvpriv = &padapter->recvpriv; int err = 0, rem, type; const struct nlattr *iter; @@ -1338,7 +1327,7 @@ static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy, void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) { struct wireless_dev *wdev = padapter->rtw_wdev; struct wiphy *wiphy= wdev->wiphy; - struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_info *precvinfo = &padapter->recvinfo; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct wlan_network *pcur_network = &pmlmepriv->cur_network; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); @@ -1346,7 +1335,7 @@ void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) { u32 tot_len = NLMSG_DEFAULT_SIZE; gfp_t kflags; rssi_monitor_evt data ; - s8 rssi = precvpriv->rssi; + s8 rssi = precvinfo->rssi; if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE) return; @@ -1432,7 +1421,6 @@ static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); - HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter); int ret = 0, rem, type; int buf_len = 1024; char *buf_ptr; @@ -1450,10 +1438,10 @@ static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy, type = nla_type(iter); switch (type) { case LOGGER_ATTRIBUTE_GET_DRIVER: - memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1); + _rtw_memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1); break; case LOGGER_ATTRIBUTE_GET_FW: - sprintf(buf_ptr, "v%d.%d", hal->firmware_version, hal->firmware_sub_version); + rtw_phl_get_fw_ver(GET_PHL_INFO(adapter_to_dvobj(padapter)), buf_ptr, buf_len); break; default: RTW_ERR("Unknown type: %d\n", type); @@ -1578,20 +1566,20 @@ static void rtw_hal_random_gen_mac_addr(u8 *mac_addr) { do { get_random_bytes(&mac_addr[3], ETH_ALEN-3); - if (memcmp(mac_addr, null_addr, ETH_ALEN) != 0) + if (_rtw_memcmp(mac_addr, null_addr, ETH_ALEN) != _TRUE) break; } while(1); } -void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter) +void rtw_hal_pno_random_gen_mac_addr(_adapter *adapter) { u8 mac_addr[ETH_ALEN]; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); - memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN); + _rtw_memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN); if (mac_addr[0] == 0xFF) return; rtw_hal_random_gen_mac_addr(mac_addr); - memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); + _rtw_memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); #ifdef CONFIG_RTW_DEBUG print_hex_dump(KERN_DEBUG, "pno_mac_addr: ", DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr, @@ -1599,12 +1587,24 @@ void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter) #endif } +void rtw_hal_set_hw_mac_addr(_adapter *adapter, u8 *mac_addr) +{ + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr); + +#ifdef CONFIG_RTW_DEBUG + rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter); +#endif + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; - PADAPTER adapter; + _adapter *adapter; void *devaddr; struct net_device *netdev; int type, mac_len; @@ -1621,7 +1621,7 @@ static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy, } if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) { - memcpy(pno_random_mac_oui, nla_data(data), 3); + _rtw_memcpy(pno_random_mac_oui, nla_data(data), 3); print_hex_dump(KERN_DEBUG, "pno_random_mac_oui: ", DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui, 3, 1); @@ -1639,9 +1639,9 @@ static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy, pwdev_priv = adapter_wdev_data(adapter); - memcpy(mac_addr, pno_random_mac_oui, 3); + _rtw_memcpy(mac_addr, pno_random_mac_oui, 3); rtw_hal_random_gen_mac_addr(mac_addr); - memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); + _rtw_memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); #ifdef CONFIG_RTW_DEBUG print_hex_dump(KERN_DEBUG, "pno_mac_addr: ", DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr, @@ -1655,24 +1655,7 @@ static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy, return err; } -#endif -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) -void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr) -{ - rtw_ps_deny(adapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(adapter); - -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_hal_change_macaddr_mbid(adapter, mac_addr); -#else - rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr); -#endif -#ifdef CONFIG_RTW_DEBUG - rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter); -#endif - rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); -} #endif #ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD @@ -1746,7 +1729,7 @@ static int rtw_cfgvendor_set_country(struct wiphy *wiphy, RTW_INFO("%s country_code:\"%c%c\" \n", __func__, country_code[0], country_code[1]); - rtw_set_country(padapter, country_code); + rtw_set_country(padapter, country_code, RTW_REGD_SET_BY_USER); return err; } @@ -1783,7 +1766,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_gscan_get_capabilities + .doit = rtw_cfgvendor_gscan_get_capabilities, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1791,7 +1777,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_set_scan_cfg + .doit = rtw_cfgvendor_set_scan_cfg, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1799,7 +1788,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_set_batch_scan_cfg + .doit = rtw_cfgvendor_set_batch_scan_cfg, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1807,7 +1799,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_initiate_gscan + .doit = rtw_cfgvendor_initiate_gscan, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1815,7 +1810,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_enable_full_scan_result + .doit = rtw_cfgvendor_enable_full_scan_result, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1823,7 +1821,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_HOTLIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_hotlist_cfg + .doit = rtw_cfgvendor_hotlist_cfg, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1831,7 +1832,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_significant_change_cfg + .doit = rtw_cfgvendor_significant_change_cfg, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1839,7 +1843,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_gscan_get_batch_results + .doit = rtw_cfgvendor_gscan_get_batch_results, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1847,7 +1854,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_gscan_get_channel_list + .doit = rtw_cfgvendor_gscan_get_channel_list, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 @@ -1857,7 +1867,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_rtt_set_config + .doit = rtw_cfgvendor_rtt_set_config, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1865,7 +1878,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_CANCEL_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_rtt_cancel_config + .doit = rtw_cfgvendor_rtt_cancel_config, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1873,7 +1889,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_GETCAPABILITY }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_rtt_get_capability + .doit = rtw_cfgvendor_rtt_get_capability, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, #endif /* RTT_SUPPORT */ #ifdef CONFIG_RTW_CFGVENDOR_LLSTATS @@ -1883,10 +1902,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_GET_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_lstats_get_info + .doit = rtw_cfgvendor_lstats_get_info, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1894,10 +1913,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_SET_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_lstats_set_info + .doit = rtw_cfgvendor_lstats_set_info, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1905,10 +1924,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_CLEAR_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_lstats_clear_info + .doit = rtw_cfgvendor_lstats_clear_info, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */ #ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR @@ -1918,11 +1937,11 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_set_rssi_monitor - }, + .doit = rtw_cfgvendor_set_rssi_monitor, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif + }, #endif /* CONFIG_RTW_CFGVENDOR_RSSIMONITOR */ #ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER { @@ -1931,10 +1950,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_START_LOGGING }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_start_logging + .doit = rtw_cfgvendor_logger_start_logging, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1942,10 +1961,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_FEATURE }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_feature + .doit = rtw_cfgvendor_logger_get_feature, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1953,10 +1972,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_VER }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_version + .doit = rtw_cfgvendor_logger_get_version, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1964,10 +1983,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_RING_STATUS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_ring_status + .doit = rtw_cfgvendor_logger_get_ring_status, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1975,10 +1994,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_RING_DATA }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) - .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_ring_data + .doit = rtw_cfgvendor_logger_get_ring_data, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .policy= VENDOR_CMD_RAW_DATA, + #endif }, { { @@ -1986,10 +2005,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_TRIGGER_MEM_DUMP }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_logger_get_firmware_memory_dump, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_firmware_memory_dump + #endif }, { { @@ -1997,10 +2016,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_START_PKT_FATE_MONITORING }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring + #endif }, { { @@ -2008,10 +2027,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_TX_PKT_FATES }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_logger_get_tx_pkt_fates, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_tx_pkt_fates + #endif }, { { @@ -2019,10 +2038,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LOGGER_GET_RX_PKT_FATES }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_logger_get_rx_pkt_fates, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_logger_get_rx_pkt_fates + #endif }, #endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */ #ifdef CONFIG_RTW_WIFI_HAL @@ -2033,10 +2052,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_set_rand_mac_oui, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_set_rand_mac_oui + #endif }, #endif #ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD @@ -2046,10 +2065,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_start_mkeep_alive, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_start_mkeep_alive + #endif }, { { @@ -2057,10 +2076,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_stop_mkeep_alive, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_stop_mkeep_alive + #endif }, #endif { @@ -2069,11 +2088,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_NODFS_SET }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_set_nodfs_flag, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_set_nodfs_flag - + #endif }, { { @@ -2081,10 +2099,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_set_country, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_set_country + #endif }, { { @@ -2092,10 +2110,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_set_nd_offload, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_set_nd_offload + #endif }, #endif /* CONFIG_RTW_WIFI_HAL */ { @@ -2104,10 +2122,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_GET_FEATURE_SET }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_get_feature_set, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_get_feature_set + #endif }, { { @@ -2115,10 +2133,10 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + .doit = rtw_cfgvendor_get_feature_set_matrix, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) .policy = VENDOR_CMD_RAW_DATA, -#endif - .doit = rtw_cfgvendor_get_feature_set_matrix + #endif } }; diff --git a/os_dep/linux/rtw_cfgvendor.h b/os_dep/linux/rtw_cfgvendor.h index 3fefa27..6ad99b2 100644 --- a/os_dep/linux/rtw_cfgvendor.h +++ b/os_dep/linux/rtw_cfgvendor.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -591,14 +591,6 @@ typedef struct { u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact. } wifi_link_layer_params; -#define RSSI_MONITOR_EVT_VERSION 1 -typedef struct { - u8 version; - s8 cur_rssi; - mac_addr BSSID; -} rssi_monitor_evt; - - /* wifi statistics bitmap */ #define WIFI_STATS_RADIO 0x00000001 // all radio statistics #define WIFI_STATS_RADIO_CCA 0x00000002 // cca_busy_time (within radio statistics) @@ -611,6 +603,12 @@ typedef struct { #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */ +#define RSSI_MONITOR_EVT_VERSION 1 +typedef struct { + u8 version; + s8 cur_rssi; + mac_addr BSSID; +} rssi_monitor_evt; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) extern int rtw_cfgvendor_attach(struct wiphy *wiphy); @@ -628,10 +626,8 @@ void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter); #endif #ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI -void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter); -#endif -#if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND) -void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr); +void rtw_hal_pno_random_gen_mac_addr(_adapter *adapter); +void rtw_hal_set_hw_mac_addr(_adapter *adapter, u8 *mac_addr); #endif diff --git a/os_dep/linux/rtw_proc.c b/os_dep/linux/rtw_proc.c index c78af83..3a4130a 100644 --- a/os_dep/linux/rtw_proc.c +++ b/os_dep/linux/rtw_proc.c @@ -15,9 +15,9 @@ #include /* tolower() */ #include -#include #include "rtw_proc.h" -#include +#include +#include "_hal_rate.h" #ifdef CONFIG_PROC_DEBUG @@ -35,10 +35,8 @@ inline struct proc_dir_entry *get_rtw_drv_proc(void) #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) -#define pde_data(inode) PDE((inode))->data +#define PDE_DATA(inode) PDE((inode))->data #define proc_get_parent_data(inode) PDE((inode))->parent->data -#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)) -#define pde_data(inode) PDE_DATA(inode) #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) @@ -163,9 +161,40 @@ static int proc_get_mstat(struct seq_file *m, void *v) } #endif /* DBG_MEM_ALLOC */ +static bool regd_info; static int proc_get_country_chplan_map(struct seq_file *m, void *v) { - dump_country_chplan_map(m); + dump_country_chplan_map(m, regd_info); + return 0; +} + +static ssize_t proc_set_country_chplan_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + int regd_info_val; + + if (count < 1) + return -EINVAL; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d", ®d_info_val); + + if (num >= 1) + regd_info = regd_info_val ? 1 : 0; + } else + return -EFAULT; + + return count; +} + +static int proc_get_country_list(struct seq_file *m, void *v) +{ + dump_country_list(m); return 0; } @@ -175,6 +204,26 @@ static int proc_get_chplan_id_list(struct seq_file *m, void *v) return 0; } +static int proc_get_chplan_country_list(struct seq_file *m, void *v) +{ + dump_chplan_country_list(m); + return 0; +} + +#if CONFIG_IEEE80211_BAND_6GHZ +static int proc_get_chplan_6g_id_list(struct seq_file *m, void *v) +{ + dump_chplan_6g_id_list(m); + return 0; +} + +static int proc_get_chplan_6g_country_list(struct seq_file *m, void *v) +{ + dump_chplan_6g_country_list(m); + return 0; +} +#endif + #ifdef CONFIG_RTW_DEBUG static int proc_get_chplan_test(struct seq_file *m, void *v) { @@ -195,28 +244,19 @@ static int proc_get_global_op_class(struct seq_file *m, void *v) return 0; } -#ifdef CONFIG_RTW_DEBUG -static int proc_get_hw_rate_map_test(struct seq_file *m, void *v) -{ - dump_hw_rate_map_test(m); - return 0; -} -#endif - -#ifdef RTW_HALMAC -extern void rtw_halmac_get_version(char *str, u32 len); +extern void rtw_hal_get_version(char *str, u32 len); -static int proc_get_halmac_info(struct seq_file *m, void *v) +static int proc_get_hal_info(struct seq_file *m, void *v) { char ver[30] = {0}; + rtw_hal_get_version(ver, 30); - rtw_halmac_get_version(ver, 30); RTW_PRINT_SEL(m, "version: %s\n", ver); return 0; } -#endif + /* * rtw_drv_proc: @@ -229,19 +269,20 @@ const struct rtw_proc_hdl drv_proc_hdls[] = { #ifdef DBG_MEM_ALLOC RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL), #endif /* DBG_MEM_ALLOC */ - RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL), + RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, proc_set_country_chplan_map), + RTW_PROC_HDL_SSEQ("country_list", proc_get_country_list, NULL), RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL), + RTW_PROC_HDL_SSEQ("chplan_country_list", proc_get_chplan_country_list, NULL), +#if CONFIG_IEEE80211_BAND_6GHZ + RTW_PROC_HDL_SSEQ("chplan_6g_id_list", proc_get_chplan_6g_id_list, NULL), + RTW_PROC_HDL_SSEQ("chplan_6g_country_list", proc_get_chplan_6g_country_list, NULL), +#endif #ifdef CONFIG_RTW_DEBUG RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL), #endif RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL), RTW_PROC_HDL_SSEQ("global_op_class", proc_get_global_op_class, NULL), -#ifdef CONFIG_RTW_DEBUG - RTW_PROC_HDL_SSEQ("hw_rate_map_test", proc_get_hw_rate_map_test, NULL), -#endif -#ifdef RTW_HALMAC - RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), -#endif /* RTW_HALMAC */ + RTW_PROC_HDL_SSEQ("hal_info", proc_get_hal_info, NULL), }; const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -249,7 +290,7 @@ const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl static int rtw_drv_proc_open(struct inode *inode, struct file *file) { /* struct net_device *dev = proc_get_parent_data(inode); */ - ssize_t index = (ssize_t)pde_data(inode); + ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = drv_proc_hdls + index; void *private = NULL; @@ -266,8 +307,11 @@ static int rtw_drv_proc_open(struct inode *inode, struct file *file) return single_open(file, show, private); } else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) { int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy; - + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) return single_open_size(file, show, private, hdl->u.sz.size); + #else + return single_open(file, show, private); + #endif } else { return -EROFS; } @@ -275,7 +319,7 @@ static int rtw_drv_proc_open(struct inode *inode, struct file *file) static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { - ssize_t index = (ssize_t)pde_data(file_inode(file)); + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = drv_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -341,7 +385,7 @@ int rtw_drv_proc_init(void) if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i); else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ || - drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ) + drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ) entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i); else entry = NULL; @@ -435,142 +479,104 @@ struct seq_operations seq_file_test = { #endif /* RTW_SEQ_FILE_TEST */ #ifdef CONFIG_SDIO_HCI -static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v) +#include "rtw_sdio.h" +#define CCCR_LEN 0x100 +static void sd_f0_reg_dump(void *sel, struct _ADAPTER *a) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *d = adapter_to_dvobj(a); + u8 *cccr = NULL, *ptr, val; + u8 ret; + int i; - sd_f0_reg_dump(m, adapter); - return 0; -} + cccr = rtw_vmalloc(CCCR_LEN); + if (cccr) { + ret = rtw_sdio_f0_read(d, 0, cccr, CCCR_LEN); + if (ret == _FAIL) { + RTW_PRINT_SEL(sel, "Fail to read F0 register!"); + goto exit; + } + } else { + RTW_WARN(FUNC_ADPT_FMT ": alloc memory FAIL!\n", + FUNC_ADPT_ARG(a)); + ptr = &val; + } -static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + for (i = 0x0; i < CCCR_LEN; i++) { + if (cccr) { + ptr = &cccr[i]; + } else { + ret = rtw_sdio_f0_read(d, i, &val, 1); + if (ret == _FAIL) { + RTW_ERR(FUNC_ADPT_FMT ": Fail to read F0 " + "register 0x%02x!\n", + FUNC_ADPT_ARG(a), i); + RTW_PRINT_SEL(sel, "... error!\n"); + goto exit; + } + } - sdio_local_reg_dump(m, adapter); + if (i % 16 == 0) + RTW_PRINT_SEL(sel, "0x%02x ", i); - return 0; -} -static int proc_get_sdio_card_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _RTW_PRINT_SEL(sel, "%02x ", *ptr); - dump_sdio_card_info(m, adapter_to_dvobj(adapter)); + if (i % 16 == 15) + _RTW_PRINT_SEL(sel, "\n"); + else if (i % 8 == 7) + _RTW_PRINT_SEL(sel, "\t"); + } - return 0; +exit: + if (cccr) + rtw_vmfree(cccr, CCCR_LEN); } -#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION -int proc_get_sdio_recvbuf_aggregation(struct seq_file *m, void *v) +static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev)); - struct recv_priv *recvpriv = &adapter->recvpriv; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); +// struct dvobj_priv *d = adapter_to_dvobj(adapter); - RTW_PRINT_SEL(m, "%d\n", recvpriv->recvbuf_agg); +// rtw_hal_sd_f0_reg_dump(m, GET_PHL_INFO(d)); + sd_f0_reg_dump(m, adapter); return 0; } -ssize_t proc_set_sdio_recvbuf_aggregation(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev)); - struct recv_priv *recvpriv = &adapter->recvpriv; - - char tmp[32]; - u8 enable; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu", &enable); - - if (num >= 1) - recvpriv->recvbuf_agg = enable ? 1 : 0; - } - - return count; -} -#endif /* CONFIG_SDIO_RECVBUF_AGGREGATION */ - -#ifdef CONFIG_SDIO_RECVBUF_PWAIT -int proc_get_sdio_recvbuf_pwait(struct seq_file *m, void *v) +static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev)); - struct recv_priv *recvpriv = &adapter->recvpriv; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *d = adapter_to_dvobj(adapter); - dump_recvbuf_pwait_conf(m, recvpriv); + rtw_hal_sdio_local_reg_dump(m, GET_PHL_INFO(d)); return 0; } - -ssize_t proc_set_sdio_recvbuf_pwait(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_get_sdio_card_info(struct seq_file *m, void *v) { -#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST - struct net_device *dev = data; - _adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev)); - struct recv_priv *recvpriv = &adapter->recvpriv; - - char tmp[64]; - char type[64]; - s32 time; - s32 cnt_lmt; - - if (count < 3) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%s %d %d", type, &time, &cnt_lmt); - int i; - - if (num < 3) - return -EINVAL; + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - for (i = 0; i < RTW_PWAIT_TYPE_NUM; i++) - if (strncmp(_rtw_pwait_type_str[i], type, strlen(_rtw_pwait_type_str[i])) == 0) - break; + dump_sdio_card_info(m, adapter_to_dvobj(adapter)); - if (i < RTW_PWAIT_TYPE_NUM && recvbuf_pwait_config_req(recvpriv, i, time, cnt_lmt) != _SUCCESS) - return -EINVAL; - } - return count; -#else - return -EFAULT; -#endif /* CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST */ + return 0; } -#endif /* CONFIG_SDIO_RECVBUF_PWAIT */ #ifdef DBG_SDIO static int proc_get_sdio_dbg(struct seq_file *m, void *v) { struct net_device *dev; - struct _ADAPTER *a; + _adapter *a; struct dvobj_priv *d; struct sdio_data *sdio; dev = m->private; - a = (struct _ADAPTER *)rtw_netdev_priv(dev); + a = (_adapter *)rtw_netdev_priv(dev); d = adapter_to_dvobj(a); - sdio = &d->intf_data; + sdio = dvobj_to_sdio(d); dump_sdio_card_info(m, d); @@ -621,7 +627,7 @@ ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer, #if (DBG_SDIO >= 2) struct net_device *dev = data; struct dvobj_priv *d; - struct _ADAPTER *a; + _adapter *a; struct sdio_data *sdio; char tmp[32], cmd[32] = {0}; int num; @@ -635,9 +641,9 @@ ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer, return -EFAULT; } - a = (struct _ADAPTER *)rtw_netdev_priv(dev); + a = (_adapter *)rtw_netdev_priv(dev); d = adapter_to_dvobj(a); - sdio = &d->intf_data; + sdio = dvobj_to_sdio(d); if (buffer && !copy_from_user(tmp, buffer, count)) { num = sscanf(tmp, "%s", cmd); @@ -687,20 +693,13 @@ ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer, #endif /* DBG_SDIO */ #endif /* CONFIG_SDIO_HCI */ -static int proc_get_fw_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_dump_fw_info(m, adapter); - return 0; -} static int proc_get_mac_reg_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - mac_reg_dump(m, adapter); + rtw_phl_mac_reg_dump(m, GET_PHL_INFO(dvobj)); return 0; } @@ -709,8 +708,9 @@ static int proc_get_bb_reg_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - bb_reg_dump(m, adapter); + rtw_phl_bb_reg_dump(m, GET_PHL_INFO(dvobj)); return 0; } @@ -719,8 +719,9 @@ static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - bb_reg_dump_ex(m, adapter); + rtw_phl_bb_reg_dump_ex(m, GET_PHL_INFO(dvobj)); return 0; } @@ -729,13 +730,14 @@ static int proc_get_rf_reg_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - rf_reg_dump(m, adapter); + rtw_phl_rf_reg_dump(m, GET_PHL_INFO(dvobj)); return 0; } -#ifdef CONFIG_RTW_LED +#if 0 int proc_get_led_config(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -821,41 +823,6 @@ ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t return count; } -int proc_get_ap_isolate(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "%d\n", adapter->mlmepriv.ap_isolate); - - return 0; -} - -ssize_t proc_set_ap_isolate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int ap_isolate; - int num = sscanf(tmp, "%d", &ap_isolate); - - if (num >= 1) - adapter->mlmepriv.ap_isolate = ap_isolate ? 1 : 0; - } - - return count; -} - #if CONFIG_RTW_AP_DATA_BMC_TO_UC static int proc_get_ap_b2u_flags(struct seq_file *m, void *v) { @@ -1173,7 +1140,6 @@ static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct recv_priv *precvpriv = &(padapter->recvpriv); char tmp[32] = {0}; int phy_info_flag = 0; @@ -1193,10 +1159,6 @@ static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer if (buffer && !copy_from_user(tmp, buffer, count)) { int num = sscanf(tmp, "%d", &phy_info_flag); - if (num == 1) - precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag; - - /*RTW_INFO("precvpriv->store_law_data_flag = %d\n",( BOOLEAN )(precvpriv->store_law_data_flag));*/ } return count; } @@ -1205,12 +1167,11 @@ static int proc_get_rx_info_msg(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - rtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE); + /*rtw_hal_set_phydm_var(padapter, HAL_PHYDM_RX_DATA_INFO, m, _FALSE);*/ return 0; } static int proc_get_tx_info_msg(struct seq_file *m, void *v) { - _irqL irqL; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct sta_info *psta; @@ -1224,7 +1185,7 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) char *BW, *status; - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); if (MLME_IS_STA(padapter)) status = "station mode"; @@ -1245,11 +1206,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) plist = get_next(plist); - if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) - && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) { + if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) { - switch (psta->cmn.bw_mode) { + switch (psta->phl_sta->chandef.bw) { case CHANNEL_WIDTH_20: BW = "20M"; @@ -1271,11 +1232,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) BW = ""; break; } - current_rate_id = rtw_get_current_tx_rate(adapter, psta); + current_rate_id = rtw_hal_get_current_tx_rate(adapter, psta); current_sgi = rtw_get_current_tx_sgi(adapter, psta); RTW_PRINT_SEL(m, "==============================\n"); - _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr)); + _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->phl_sta->mac_addr)); _RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id)); _RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi); @@ -1283,93 +1244,298 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) } } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); return 0; } - -static int proc_get_linked_info_dump(struct seq_file *m, void *v) +#ifdef ROKU_PRIVATE +static u32 rtw_tx_sts_total(u32 *tx_sts, u8 num) { - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - if (padapter) - RTW_PRINT_SEL(m, "linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable"); + u32 ret = 0; + int i = 0; - return 0; + for (i = 0; i < num; i++) + ret += tx_sts[i]; + return ret; } - -static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_get_roku_trx_info_msg(struct seq_file *m, void *v) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - char tmp[32] = {0}; - int mode = 0, pre_mode = 0; - int num = 0; + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _list *plist, *phead; + struct sta_info *psta = NULL; + u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}}; + uint mac_id[NUM_STA]; + struct stainfo_stats *pstats = NULL; + struct sta_priv *pstapriv = &(adapter->stapriv); + u32 i, j, macid_rec_idx = 0; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + u32 tx_retry_cnt[PHL_AC_QUEUE_TOTAL] = {0}; + u32 tx_fail_cnt[PHL_AC_QUEUE_TOTAL] = {0}; + u32 tx_ok_cnt[PHL_AC_QUEUE_TOTAL] = {0}; - if (count < 1) - return -EFAULT; +#if 0 + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + struct sta_recv_dframe_info *psta_dframe_info; + char cnt_str[168] = {0}; + char tmp_str[21] = {0}; + u8 rx_nss_num = hal_spec->rx_nss_num; + char *BW; + u8 isCCKrate = 0, rf_path = 0; + u8 tx_stats_category = 1; /* 0: pass, 1:drop */ +#endif - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } +#if 0 + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta) { + RTW_PRINT_SEL(m, "Interface Name: %s\n", ADPT_ARG(adapter)); - pre_mode = padapter->bLinkInfoDump; - RTW_INFO("pre_mode=%d\n", pre_mode); + RTW_PRINT_SEL(m, "===== TX and RX Count Statistics =====\n"); + RTW_PRINT_SEL(m , "TX packets:%llu\n", pxmitpriv->tx_pkts); + RTW_PRINT_SEL(m , "RX packets:%llu\n", precvpriv->rx_pkts); - if (buffer && !copy_from_user(tmp, buffer, count)) { + RTW_PRINT_SEL(m, "===== TX Drop Statistics =====\n"); + RTW_PRINT_SEL(m, "[Driver] BK packets drop count: %llu\n", pxmitpriv->tx_bk_drop_cnt); + RTW_PRINT_SEL(m, "[Driver] BE packets drop count: %llu\n", pxmitpriv->tx_be_drop_cnt); + RTW_PRINT_SEL(m, "[Driver] VI packets drop count: %llu\n", pxmitpriv->tx_vi_drop_cnt); + RTW_PRINT_SEL(m, "[Driver] VO packets drop count: %llu\n", pxmitpriv->tx_vo_drop_cnt); - num = sscanf(tmp, "%d ", &mode); - RTW_INFO("num=%d mode=%d\n", num, mode); + RTW_PRINT_SEL(m, "===== RX VO packets Statistics =====\n"); - if (num != 1) { - RTW_INFO("argument number is wrong\n"); - return -EFAULT; + for(i = DESC_RATE1M ; i <= DESC_RATE11M ; i++) { + snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[i]); + strncat(cnt_str, tmp_str, strlen(tmp_str)); } + RTW_PRINT_SEL(m, "CCK (1M, 2M, 5.5M, 11M): [ %s]\n", cnt_str); + _rtw_memset(&cnt_str, '\0', sizeof(cnt_str)); - if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */ - padapter->bLinkInfoDump = mode; + for(i = DESC_RATE6M ; i <= DESC_RATE54M ; i++) { + snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[i]); + strncat(cnt_str, tmp_str, strlen(tmp_str)); + } + RTW_PRINT_SEL(m, "OFDM (6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M): [ %s]\n", cnt_str); + _rtw_memset(&cnt_str, '\0', sizeof(cnt_str)); - else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */ - /* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */ - linked_info_dump(padapter, mode); + for(i = 0 ; i < rx_nss_num ; i++) { + for(j = DESC_RATEMCS0 ; j <= DESC_RATEMCS7 ; j++) { + snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[j + (i<<3)]); + strncat(cnt_str, tmp_str, strlen(tmp_str)); + } + RTW_PRINT_SEL(m, "HT_MCS (%d-%d): [ %s]\n", (i<<3), (i<<3) + 7, cnt_str); + _rtw_memset(&cnt_str, '\0', sizeof(cnt_str)); } - } - return count; -} + if (rx_nss_num == 1) + RTW_PRINT_SEL(m, "HT_MCS (8-15): [ 0 0 0 0 0 0 0 0 ]\n"); -static int proc_get_sta_tp_dump(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + for(i = 0 ; i < rx_nss_num ; i++) { + for(j = DESC_RATEVHTSS1MCS0 ; j <= DESC_RATEVHTSS1MCS9 ; j++) { + snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[j + (i * 10)]); + strncat(cnt_str, tmp_str, strlen(tmp_str)); + } + RTW_PRINT_SEL(m, "VHT_%dSS_MCS (0-9): [ %s]\n", (i + 1), cnt_str); + _rtw_memset(&cnt_str, '\0', sizeof(cnt_str)); + } - if (padapter) - RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable"); + if (rx_nss_num == 1) + RTW_PRINT_SEL(m, "VHT_2SS_MCS (0-9): [ 0 0 0 0 0 0 0 0 0 0 ]\n"); - return 0; -} + RTW_PRINT_SEL(m, "RX counter for VO packets with retry bit set: %llu\n\n", precvpriv->rx_vo_pkt_retry_count); + } +#endif + _rtw_spinlock_bh(&pstapriv->sta_hash_lock); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) { + _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->phl_sta->mac_addr, ETH_ALEN); + mac_id[macid_rec_idx] = psta->phl_sta->macid; + macid_rec_idx++; + } + } + } + _rtw_spinunlock_bh(&pstapriv->sta_hash_lock); -static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + for (i = 0; i < macid_rec_idx; i++) { + psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]); - char tmp[32] = {0}; - int mode = 0; - int num = 0; +#if 0 + if (psta) { + psta_dframe_info = &psta->sta_dframe_info; - if (count < 1) - return -EFAULT; + isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE; - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } + switch (psta_dframe_info->sta_bw_mode) { + case CHANNEL_WIDTH_20: + BW = "20M"; + break; + case CHANNEL_WIDTH_40: + BW = "40M"; + break; + case CHANNEL_WIDTH_80: + BW = "80M"; + break; + case CHANNEL_WIDTH_160: + BW = "160M"; + break; + default: + BW = ""; + break; + } + + RTW_PRINT_SEL(m, "========= STA("MAC_FMT") =========\n", MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n", + rtw_get_oper_ch(adapter), rtw_get_oper_bw(adapter), rtw_get_oper_choffset(adapter)); + RTW_PRINT_SEL(m, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi); + RTW_PRINT_SEL(m, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate)); + RTW_PRINT_SEL(m, "Rx_Data_Rate_Int = %d\n", (psta_dframe_info->sta_data_rate)); + + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + if (!isCCKrate) { + RTW_PRINT_SEL(m , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]); + RTW_PRINT_SEL(m , "\nrx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]); + } else + RTW_PRINT_SEL(m , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100); + } + + if (pHalData->NumTotalRFPath == 1) { + if (!isCCKrate) { + RTW_PRINT_SEL(m , "RF_PATH_1 RSSI:%d(dBm)", 0); + RTW_PRINT_SEL(m , "\nrx_ofdm_snr:%d(dB)\n", 0); + } else + RTW_PRINT_SEL(m , "RF_PATH_1 RSSI:%d(dBm)\n", 0); + } + + RTW_PRINT_SEL(m , "Total False Alarm:%d / Cnt_CCA_all:%d\n", rtw_phydm_get_phy_cnt(adapter, FA_TOTAL) , rtw_phydm_get_phy_cnt(adapter, CCA_ALL)); + } else + RTW_PRINT_SEL(m, "STA is gone\n"); +#endif + + if(psta) { + rtw_phl_get_tx_retry_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)),psta->phl_sta, + tx_retry_cnt, PHL_AC_QUEUE_TOTAL); + rtw_phl_get_tx_fail_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)), psta->phl_sta, + tx_fail_cnt, PHL_AC_QUEUE_TOTAL); + rtw_phl_get_tx_ok_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)), psta->phl_sta, + tx_ok_cnt, PHL_AC_QUEUE_TOTAL); + pstats = &psta->sta_stats; + pstats->tx_retry_cnt = rtw_tx_sts_total(tx_retry_cnt, PHL_AC_QUEUE_TOTAL); + pstats->tx_fail_cnt = rtw_tx_sts_total(tx_fail_cnt, PHL_AC_QUEUE_TOTAL); + pstats->tx_ok_cnt = rtw_tx_sts_total(tx_ok_cnt, PHL_AC_QUEUE_TOTAL); + pstats->total_tx_retry_cnt += pstats->tx_retry_cnt; + + RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n", + MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt); + RTW_PRINT_SEL(m, "total_tx_retry: %llu, rx_retry: %u\n", pstats->total_tx_retry_cnt, + ATOMIC_READ((ATOMIC_T *)&pstats->rx_retry_cnt)); + ATOMIC_SET((ATOMIC_T *)&pstats->rx_retry_cnt, 0); + + RTW_PRINT_SEL(m, "[HW] BK packets drop count: %u\n", tx_fail_cnt[PHL_BE_QUEUE_SEL]); + RTW_PRINT_SEL(m, "[HW] BE packets drop count: %u\n", tx_fail_cnt[PHL_BK_QUEUE_SEL]); + RTW_PRINT_SEL(m, "[HW] VI packets drop count: %u\n", tx_fail_cnt[PHL_VI_QUEUE_SEL]); + RTW_PRINT_SEL(m, "[HW] VO packets drop count: %u\n", tx_fail_cnt[PHL_VO_QUEUE_SEL]); + } else { + RTW_PRINT_SEL(m, "STA is gone\n"); + } + + } + + return 0; +} +#endif /* ROKU_PRIVATE */ + + +static int proc_get_linked_info_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + if (padapter) + RTW_PRINT_SEL(m, "rtw_hal_linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable"); + + return 0; +} + + +static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32] = {0}; + int mode = 0, pre_mode = 0; + int num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + pre_mode = padapter->bLinkInfoDump; + RTW_INFO("pre_mode=%d\n", pre_mode); + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d ", &mode); + RTW_INFO("num=%d mode=%d\n", num, mode); + + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + + if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */ + padapter->bLinkInfoDump = mode; + + else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */ + /* RTW_INFO("rtw_hal_linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */ + rtw_hal_linked_info_dump(padapter, mode); + } + } + return count; +} + + +static int proc_get_sta_tp_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (padapter) + RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable"); + + return 0; +} + +static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32] = {0}; + int mode = 0; + int num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } if (buffer && !copy_from_user(tmp, buffer, count)) { @@ -1400,23 +1566,16 @@ static int proc_get_turboedca_ctrl(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - - if (hal_data) { - u32 edca_param; - - if (hal_data->dis_turboedca == 0) - RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Enable"); - else - RTW_PRINT_SEL(m, "Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\n", "Disable", hal_data->dis_turboedca, hal_data->edca_param_mode); - - - rtw_hal_get_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); - - _RTW_PRINT_SEL(m, "PARAM_BE:0x%x\n", edca_param); + if (padapter->dis_turboedca == EN_TURBO) + RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Enable"); + else if (padapter->dis_turboedca == DIS_TURBO) + RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Disable"); + else + RTW_PRINT_SEL(m, "Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\n", + "Disable", padapter->dis_turboedca, padapter->edca_param_mode); - } + _RTW_PRINT_SEL(m, "PARAM_BE:0x%x\n", padapter->edca_param_mode); return 0; } @@ -1425,7 +1584,6 @@ static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buf { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); char tmp[32] = {0}; int mode = 0, num = 0; u32 param_mode = 0; @@ -1453,23 +1611,21 @@ static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buf if (mode > 2) mode = 0; - hal_data->dis_turboedca = mode; + padapter->dis_turboedca = mode; - hal_data->edca_param_mode = 0; /* init. value */ + padapter->edca_param_mode = 0; /* init. value */ - RTW_INFO("dis_turboedca mode = 0x%x\n", hal_data->dis_turboedca); + RTW_INFO("dis_turboedca mode = 0x%x\n", padapter->dis_turboedca); if (num == 2) { - hal_data->edca_param_mode = param_mode; + padapter->edca_param_mode = param_mode; RTW_INFO("param_mode = 0x%x\n", param_mode); } } - return count; - } static int proc_get_mac_qinfo(struct seq_file *m, void *v) @@ -1498,6 +1654,7 @@ static int proc_get_chan_plan(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); dump_cur_chset(m, adapter_to_rfctl(adapter)); + return 0; } @@ -1506,7 +1663,8 @@ static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 chan_plan = RTW_CHPLAN_UNSPECIFIED; + u16 chplan = RTW_CHPLAN_UNSPECIFIED; + u16 chplan_6g = RTW_CHPLAN_6G_UNSPECIFIED; if (!padapter) return -EFAULT; @@ -1522,12 +1680,14 @@ static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhx", &chan_plan); - if (num != 1) + int num = sscanf(tmp, "%hx %hx", &chplan, &chplan_6g); + if (num < 1) return count; + + rtw_chplan_ioctl_input_mapping(&chplan, &chplan_6g); } - rtw_set_channel_plan(padapter, chan_plan); + rtw_set_channel_plan(padapter, chplan, chplan_6g, RTW_REGD_SET_BY_USER); return count; } @@ -1538,10 +1698,7 @@ static int proc_get_country_code(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - if (rfctl->country_ent) - dump_country_chplan(m, rfctl->country_ent); - else - RTW_PRINT_SEL(m, "unspecified\n"); + dump_cur_country(m, rfctl); return 0; } @@ -1569,7 +1726,7 @@ static ssize_t proc_set_country_code(struct file *file, const char __user *buffe if (num != 2) return count; - rtw_set_country(padapter, alpha2); + rtw_set_country(padapter, alpha2, RTW_REGD_SET_BY_USER); exit: return count; @@ -1946,6 +2103,62 @@ static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buff return count; } +#ifdef CONFIG_80211D +static int proc_get_country_ie_slave_en_conds(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%-4s %-5s\n", "role", "ifbmp"); + RTW_PRINT_SEL(m, "0x%02x 0x%02x\n" + , rfctl->country_ie_slave_en_role + , rfctl->country_ie_slave_en_ifbmp + ); + + return 0; +} + +static ssize_t proc_set_country_ie_slave_en_conds(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + u8 role, ifbmp; + int num = sscanf(tmp, "%hhx %hhx", &role, &ifbmp); + + if (num >= 1) + rfctl->country_ie_slave_en_role = role; + if (num >= 2) + rfctl->country_ie_slave_en_ifbmp = ifbmp; + } + + return count; +} + +static int proc_get_country_ie_slave_records(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + dump_country_ie_slave_records(m, rfctl, 0); + + return 0; +} +#endif /* CONFIG_80211D */ + #ifdef CONFIG_DFS_MASTER static int proc_get_dfs_test_case(struct seq_file *m, void *v) { @@ -1997,7 +2210,7 @@ ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, si _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); char tmp[32]; - u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 ch, bw = CHANNEL_WIDTH_20, offset = CHAN_OFFSET_NO_EXT; int ms = -1; bool updated = 0; @@ -2018,7 +2231,7 @@ ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, si if (bw == CHANNEL_WIDTH_20) updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set - , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); + , ch, bw, CHAN_OFFSET_NO_EXT, ms); else updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set , ch, bw, offset, ms); @@ -2284,16 +2497,16 @@ static int proc_get_udpport(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct recv_priv *precvpriv = &(padapter->recvpriv); + struct recv_info *precvinfo = &(padapter->recvinfo); - RTW_PRINT_SEL(m, "%d\n", precvpriv->sink_udpport); + RTW_PRINT_SEL(m, "%d\n", precvinfo->sink_udpport); return 0; } static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct recv_priv *precvpriv = &(padapter->recvpriv); + struct recv_info *precvinfo = &(padapter->recvinfo); int sink_udpport = 0; char tmp[32]; @@ -2321,12 +2534,13 @@ static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, si } } - precvpriv->sink_udpport = sink_udpport; + precvinfo->sink_udpport = sink_udpport; return count; } +#if 0 static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2340,6 +2554,8 @@ static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v) return 0; } +#endif +#if 0 static int proc_get_macid_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2360,7 +2576,7 @@ static int proc_get_macid_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s" , "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht"); - if (GET_HAL_TX_NSS(adapter) > 2) + if (GET_HAL_TX_NSS(dvobj) > 2) _RTW_PRINT_SEL(m, " %-10s", "rate_bmp1"); _RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status"); @@ -2370,7 +2586,7 @@ static int proc_get_macid_info(struct seq_file *m, void *v) || macid_ctl->h2c_msr[i] ) { if (macid_ctl->sta[i]) - macaddr = macid_ctl->sta[i]->cmn.mac_addr; + macaddr = macid_ctl->sta[i]->phl_sta->mac_addr; else macaddr = null_addr; @@ -2384,28 +2600,21 @@ static int proc_get_macid_info(struct seq_file *m, void *v) , macid_ctl->vht_en[i] ); - if (GET_HAL_TX_NSS(adapter) > 2) + if (GET_HAL_TX_NSS(dvobj) > 2) _RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]); - +#ifdef DBG_MACID_MSR_INFO _RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n" , macid_ctl->rate_bmp0[i] , H2C_MSR_ARG(&macid_ctl->h2c_msr[i]) , rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]" ); - } - } - RTW_PRINT_SEL(m, "\n"); - - for (i = 0; i < H2C_MSR_ROLE_MAX; i++) { - if (macid_ctl->op_num[i]) { - RTW_PRINT_SEL(m, "%-5s op_num:%u\n" - , h2c_msr_role_str(i), macid_ctl->op_num[i]); +#endif } } return 0; } - +#endif static int proc_get_sec_cam(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2422,7 +2631,9 @@ static int proc_get_sec_cam(struct seq_file *m, void *v) dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num); RTW_PRINT_SEL(m, "\n"); +#if 0 /*GEORGIA_TODO_REDEFINE_IO*/ RTW_PRINT_SEL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680)); +#endif RTW_PRINT_SEL(m, "\n"); dump_sec_cam(m, adapter); @@ -2490,7 +2701,34 @@ static int proc_get_sec_cam_cache(struct seq_file *m, void *v) return 0; } -#ifdef CONFIG_AP_MODE +#ifdef CONFIG_DBG_AX_CAM + +static int proc_get_ax_address_cam(struct seq_file *m, void *v) { + struct net_device *dev = m->private; + struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + + get_ax_address_cam(m, adapter); + return 0; +} + +static int proc_get_ax_sec_cam(struct seq_file *m, void *v) { + struct net_device *dev = m->private; + struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + + get_ax_sec_cam(m, adapter); + return 0; +} + +static int proc_get_ax_valid_key(struct seq_file *m, void *v) { + struct net_device *dev = m->private; + struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + + get_ax_valid_key(m, adapter); + return 0; +} + +#endif + static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; @@ -2538,25 +2776,67 @@ static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *bu exit: return count; } -#endif -#if CONFIG_TX_AC_LIFETIME -static int proc_get_tx_aclt_force_val(struct seq_file *m, void *v) +static int proc_get_tx_bw_mode(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_tx_aclt_force_val(m, dvobj); + RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode); + RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter))); + RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter))); return 0; } -static ssize_t proc_set_tx_aclt_force_val(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static void rtw_set_tx_bw_mode(_adapter *adapter, u8 bw_mode) +{ + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + /* macid_ctl move to phl */ + /* struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; */ + u8 update = _FALSE; + + if ((MLME_STATE(adapter) & WIFI_ASOC_STATE) + && ((mlmeext->chandef.chan <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter)) + || (mlmeext->chandef.chan >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter))) + ) { + /* RA mask update needed */ + update = _TRUE; + } + adapter->driver_tx_bw_mode = bw_mode; + +#if 0 + if (update == _TRUE) { + struct sta_info *sta; + int i; + + /*for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {*/ + //sta = macid_ctl->sta[i]; + + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (sta && !is_broadcast_mac_addr(sta->phl_sta->mac_addr)) { + rtw_phl_cmd_change_stainfo(adapter_to_dvobj(adapter)->phl, + sta->phl_sta, + STA_CHG_RAMASK, + NULL, + 0, + PHL_CMD_NO_WAIT, /*PHL_CMD_DIRECTLY,PHL_CMD_WAIT*/ + 0); + } + } + /*}*/ +#endif +} + +static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *adapter = rtw_netdev_priv(dev); - char tmp[32] = {0}; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 bw_mode; + + if (count < 1) + return -EFAULT; if (count > sizeof(tmp)) { rtw_warn_on(1); @@ -2564,183 +2844,34 @@ static ssize_t proc_set_tx_aclt_force_val(struct file *file, const char __user * } if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct tx_aclt_conf_t input; - int num = sscanf(tmp, "%hhx %u %u", &input.en, &input.vo_vi, &input.be_bk); - if (num < 1) - return count; + int num = sscanf(tmp, "%hhx", &bw_mode); + + if (num < 1 || bw_mode == adapter->driver_tx_bw_mode) + goto exit; - rtw_hal_set_tx_aclt_force_val(adapter, &input, num); - rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter); + rtw_set_tx_bw_mode(adapter, bw_mode); } +exit: return count; } -static int proc_get_tx_aclt_flags(struct seq_file *m, void *v) +static int proc_get_hal_txpwr_info(struct seq_file *m, void *v) { +#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX struct net_device *dev = m->private; - _adapter *adapter = rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - RTW_PRINT_SEL(m, "0x%02x\n", dvobj->tx_aclt_flags); + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *devob = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *hal_data = GET_PHL_COM(devob); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(devob); - return 0; -} - -static ssize_t proc_set_tx_aclt_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = rtw_netdev_priv(dev); - char tmp[32] = {0}; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - u8 flags; - int num = sscanf(tmp, "%hhx", &flags); - - if (num < 1) - return count; - - if (dvobj->tx_aclt_flags == flags) - return count; - - dvobj->tx_aclt_flags = flags; - - rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter); - } - - return count; -} - -static int proc_get_tx_aclt_confs(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - RTW_PRINT_SEL(m, "flags:0x%02x\n", dvobj->tx_aclt_flags); - dump_tx_aclt_confs(m, dvobj); - - return 0; -} - -static ssize_t proc_set_tx_aclt_confs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = rtw_netdev_priv(dev); - char tmp[32] = {0}; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - u8 id; - struct tx_aclt_conf_t input; - int num = sscanf(tmp, "%hhu %hhx %u %u", &id, &input.en, &input.vo_vi, &input.be_bk); - - if (num < 2) - return count; - - rtw_hal_set_tx_aclt_conf(adapter, id, &input, num - 1); - rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter); - } - - return count; -} -#endif /* CONFIG_TX_AC_LIFETIME */ - -static int proc_get_tx_bw_mode(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode); - RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter))); - RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter))); - - return 0; -} - -static void rtw_set_tx_bw_mode(struct _ADAPTER *adapter, u8 bw_mode) -{ - struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); - struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - u8 update = _FALSE; - - if ((MLME_STATE(adapter) & WIFI_ASOC_STATE) - && ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter)) - || (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter))) - ) { - /* RA mask update needed */ - update = _TRUE; - } - adapter->driver_tx_bw_mode = bw_mode; - - if (update == _TRUE) { - struct sta_info *sta; - int i; - - for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { - sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) - rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); - } - } -} - -static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 bw_mode; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &bw_mode); - - if (num < 1 || bw_mode == adapter->driver_tx_bw_mode) - goto exit; - - rtw_set_tx_bw_mode(adapter, bw_mode); - } - -exit: - return count; -} - -static int proc_get_hal_txpwr_info(struct seq_file *m, void *v) -{ -#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - - if (hal_data->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX) { - if (hal_is_band_support(adapter, BAND_ON_2_4G)) - dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_data->max_tx_cnt); + if (hal_data->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX) { + if (rtw_hw_is_band_support(devob, BAND_ON_24G)) + dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_data->max_tx_cnt); #if CONFIG_IEEE80211_BAND_5GHZ - if (hal_is_band_support(adapter, BAND_ON_5G)) + if (rtw_hw_is_band_support(devob, BAND_ON_5G)) dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_data->max_tx_cnt); #endif } @@ -2754,7 +2885,7 @@ static int proc_get_target_tx_power(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_target_tx_power(m, adapter); + rtw_hal_dump_target_tx_power(m, adapter); return 0; } @@ -2764,7 +2895,7 @@ static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_tx_power_by_rate(m, adapter); + rtw_hal_dump_tx_power_by_rate(m, adapter); return 0; } @@ -2781,98 +2912,12 @@ static int proc_get_tx_power_limit(struct seq_file *m, void *v) } #endif /* CONFIG_TXPWR_LIMIT */ -static int proc_get_tpc_settings(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - dump_txpwr_tpc_settings(m, adapter); - - return 0; -} - -static ssize_t proc_set_tpc_settings(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - char tmp[32] = {0}; - u8 mode; - u16 m_constraint; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu %hu", &mode, &m_constraint); - - if (num < 1) - return count; - - if (mode >= TPC_MODE_INVALID) - return count; - - if (mode == TPC_MODE_MANUAL && num >= 2) - rfctl->tpc_manual_constraint = rtw_min(m_constraint, TPC_MANUAL_CONSTRAINT_MAX); - rfctl->tpc_mode = mode; - - if (rtw_get_hw_init_completed(adapter)) - rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000); - } - - return count; -} - -static int proc_get_antenna_gain(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - dump_txpwr_antenna_gain(m, adapter); - - return 0; -} - -static ssize_t proc_set_antenna_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - char tmp[32] = {0}; - s16 gain; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hd", &gain); - - if (num < 1) - return count; - - rfctl->antenna_gain = gain; - - if (rtw_get_hw_init_completed(adapter)) - rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000); - } - - return count; -} - static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_tx_power_ext_info(m, adapter); + rtw_dump_phl_tx_power_ext_info(m, adapter); return 0; } @@ -2897,6 +2942,7 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * if (num < 1) return count; +#if 0 /* TODO */ #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE); #endif @@ -2914,11 +2960,13 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * clear_ps_deny: rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +#endif } return count; } +#ifdef GEORGIA_TODO_TX_PWR static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos) { u8 path = ((*pos) & 0xFF00) >> 8; @@ -2943,393 +2991,89 @@ static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos) path++; } - if (path >= RF_PATH_MAX) - return NULL; - - *pos = (path << 8) | rs; - - return pos; -} - -static int proc_get_tx_power_idx(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - u32 pos = *((loff_t *)(v)); - u8 path = (pos & 0xFF00) >> 8; - u8 rs = pos & 0xFF; - enum channel_width bw = hal_data->current_channel_bw; - u8 cch = hal_data->current_channel; - - if (0) - RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs); - - if (path == RF_PATH_A && rs == CCK) - dump_tx_power_idx_title(m, adapter, bw, cch, 0); - dump_tx_power_idx_by_path_rs(m, adapter, path, rs, bw, cch, 0); - - return 0; -} - -static struct seq_operations seq_ops_tx_power_idx = { - .start = proc_start_tx_power_idx, - .stop = proc_stop_tx_power_idx, - .next = proc_next_tx_power_idx, - .show = proc_get_tx_power_idx, -}; - -static ssize_t proc_set_tx_power_idx_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - char tmp[32] = {0}; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - u8 ch, bw, offset; - u8 cch; - - int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset); - - if (num < 3) - return count; - - cch = rtw_get_center_ch(ch, bw, offset); - dump_tx_power_idx(RTW_DBGDUMP, adapter, bw, cch, ch); - } - - return count; -} - -static void *proc_start_txpwr_total_dbm(struct seq_file *m, loff_t *pos) -{ - u8 rs = *pos; - - if (rs >= RATE_SECTION_NUM) - return NULL; - - return pos; -} - -static void proc_stop_txpwr_total_dbm(struct seq_file *m, void *v) -{ -} - -static void *proc_next_txpwr_total_dbm(struct seq_file *m, void *v, loff_t *pos) -{ - u8 rs = *pos; - - rs++; - if (rs >= RATE_SECTION_NUM) - return NULL; - - *pos = rs; - - return pos; -} - -static int proc_get_txpwr_total_dbm(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - u32 pos = *((loff_t *)(v)); - u8 rs = pos; - enum channel_width bw = hal_data->current_channel_bw; - u8 cch = hal_data->current_channel; - - if (rs == CCK) - dump_txpwr_total_dbm_title(m, adapter, bw, cch, 0); - dump_txpwr_total_dbm_by_rs(m, adapter, rs, bw, cch, 0); - - return 0; -} - -static struct seq_operations seq_ops_txpwr_total_dbm = { - .start = proc_start_txpwr_total_dbm, - .stop = proc_stop_txpwr_total_dbm, - .next = proc_next_txpwr_total_dbm, - .show = proc_get_txpwr_total_dbm, -}; - -static ssize_t proc_set_txpwr_total_dbm_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - char tmp[32] = {0}; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - u8 ch, bw, offset; - u8 cch; - - int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset); - - if (num < 3) - return count; - - cch = rtw_get_center_ch(ch, bw, offset); - dump_txpwr_total_dbm(RTW_DBGDUMP, adapter, bw, cch, ch); - } - - return count; -} - -#ifdef CONFIG_RF_POWER_TRIM -static int proc_get_kfree_flag(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - - RTW_PRINT_SEL(m, "0x%02x\n", kfree_data->flag); - - return 0; -} - -static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - char tmp[32] = {0}; - u8 flag; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &flag); - - if (num < 1) - return count; - - kfree_data->flag = flag; - } - - return count; -} - -static int proc_get_kfree_bb_gain(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - u8 i, j; - - for (i = 0; i < BB_GAIN_NUM; i++) { - - if (i == 0) - _RTW_PRINT_SEL(m, "2G: "); -#if CONFIG_IEEE80211_BAND_5GHZ - switch (i) { - case 1: - _RTW_PRINT_SEL(m, "5GLB1: "); - break; - case 2: - _RTW_PRINT_SEL(m, "5GLB2: "); - break; - case 3: - _RTW_PRINT_SEL(m, "5GMB1: "); - break; - case 4: - _RTW_PRINT_SEL(m, "5GMB2: "); - break; - case 5: - _RTW_PRINT_SEL(m, "5GHB: "); - break; - } -#endif - for (j = 0; j < hal_spec->rf_reg_path_num; j++) - _RTW_PRINT_SEL(m, "%d ", kfree_data->bb_gain[i][j]); - _RTW_PRINT_SEL(m, "\n"); - } - - return 0; -} - -static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0}; - u8 chidx; - s8 bb_gain[BB_GAIN_NUM]; - char ch_band_Group[6]; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - char *c, *next; - int i = 0; - - next = tmp; - c = strsep(&next, " \t"); - - if (sscanf(c, "%s", ch_band_Group) != 1) { - RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n"); - return count; - } - if (strcmp("2G", ch_band_Group) == 0) - chidx = BB_GAIN_2G; -#if CONFIG_IEEE80211_BAND_5GHZ - else if (strcmp("5GLB1", ch_band_Group) == 0) - chidx = BB_GAIN_5GLB1; - else if (strcmp("5GLB2", ch_band_Group) == 0) - chidx = BB_GAIN_5GLB2; - else if (strcmp("5GMB1", ch_band_Group) == 0) - chidx = BB_GAIN_5GMB1; - else if (strcmp("5GMB2", ch_band_Group) == 0) - chidx = BB_GAIN_5GMB2; - else if (strcmp("5GHB", ch_band_Group) == 0) - chidx = BB_GAIN_5GHB; -#endif /*CONFIG_IEEE80211_BAND_5GHZ*/ - else { - RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n"); - return count; - } - c = strsep(&next, " \t"); - - while (c != NULL) { - if (sscanf(c, "%hhx", &bb_gain[i]) != 1) - break; - - kfree_data->bb_gain[chidx][i] = bb_gain[i]; - RTW_INFO("%s,kfree_data->bb_gain[%d][%d]=%x\n", __func__, chidx, i, kfree_data->bb_gain[chidx][i]); - - c = strsep(&next, " \t"); - i++; - } - - } - - return count; - -} - -static int proc_get_kfree_thermal(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - - _RTW_PRINT_SEL(m, "%d\n", kfree_data->thermal); - - return 0; -} - -static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); - char tmp[32] = {0}; - s8 thermal; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhd", &thermal); - - if (num < 1) - return count; + if (path >= RF_PATH_MAX) + return NULL; - kfree_data->thermal = thermal; - } + *pos = (path << 8) | rs; - return count; + return pos; } -static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_get_tx_power_idx(struct seq_file *m, void *v) { - struct net_device *dev = data; - _adapter *adapter; - char tmp[32] = {0}; - u8 rf_path; - s8 offset; + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u32 pos = *((loff_t *)(v)); + u8 path = (pos & 0xFF00) >> 8; + u8 rs = pos & 0xFF; - adapter = (_adapter *)rtw_netdev_priv(dev); - if (!adapter) - return -EFAULT; + if (0) + RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs); - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } + if (path == RF_PATH_A && rs == CCK) + dump_tx_power_idx_title(m, adapter); + dump_tx_power_idx_by_path_rs(m, adapter, path, rs); - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset); + return 0; +} - if (num < 2) - return count; +static struct seq_operations seq_ops_tx_power_idx = { + .start = proc_start_tx_power_idx, + .stop = proc_stop_tx_power_idx, + .next = proc_next_tx_power_idx, + .show = proc_get_tx_power_idx, +}; - RTW_INFO("write rf_path:%u tx gain offset:%d\n", rf_path, offset); - rtw_rf_set_tx_gain_offset(adapter, rf_path, offset); - } +static void *proc_start_txpwr_total_dbm(struct seq_file *m, loff_t *pos) +{ + u8 rs = *pos; - return count; + if (rs >= RATE_SECTION_NUM) + return NULL; + + return pos; } -#endif /* CONFIG_RF_POWER_TRIM */ -#ifdef CONFIG_BT_COEXIST -ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static void proc_stop_txpwr_total_dbm(struct seq_file *m, void *v) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 btinfo[8]; - - if (count < 6) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } +} - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = 0; +static void *proc_next_txpwr_total_dbm(struct seq_file *m, void *v, loff_t *pos) +{ + u8 rs = *pos; - _rtw_memset(btinfo, 0, 8); + rs++; + if (rs >= RATE_SECTION_NUM) + return NULL; - num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx" - , &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3] - , &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]); + *pos = rs; - if (num < 6) - return -EINVAL; + return pos; +} - btinfo[1] = num - 2; +static int proc_get_txpwr_total_dbm(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u32 pos = *((loff_t *)(v)); + u8 rs = pos; - rtw_btinfo_cmd(padapter, btinfo, btinfo[1] + 2); - } + if (rs == CCK) + dump_txpwr_total_dbm_title(m, adapter); + dump_txpwr_total_dbm_by_rs(m, adapter, rs); - return count; + return 0; } +static struct seq_operations seq_ops_txpwr_total_dbm = { + .start = proc_start_txpwr_total_dbm, + .stop = proc_stop_txpwr_total_dbm, + .next = proc_next_txpwr_total_dbm, + .show = proc_get_txpwr_total_dbm, +}; +#endif + +#ifdef CONFIG_BTC static u8 btreg_read_type = 0; static u16 btreg_read_addr = 0; static int btreg_read_error = 0; @@ -3419,8 +3163,9 @@ static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) int proc_get_btreg_read(struct seq_file *m, void *v) { +#if 0 struct net_device *dev; - PADAPTER padapter; + _adapter *padapter; u16 ret; u32 data; @@ -3429,27 +3174,29 @@ int proc_get_btreg_read(struct seq_file *m, void *v) return btreg_read_error; dev = m->private; - padapter = (PADAPTER)rtw_netdev_priv(dev); + padapter = (_adapter *)rtw_netdev_priv(dev); - ret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data); + ret = rtw_btc_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data); if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data); else RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret); +#endif return 0; } ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#if 0 struct net_device *dev = data; - PADAPTER padapter; + _adapter *padapter; u8 tmp[80] = {0}; u32 num; int err; - padapter = (PADAPTER)rtw_netdev_priv(dev); + padapter = (_adapter *)rtw_netdev_priv(dev); if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", @@ -3487,14 +3234,16 @@ ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t exit: btreg_read_error = err; +#endif return count; } int proc_get_btreg_write(struct seq_file *m, void *v) { +#if 0 struct net_device *dev; - PADAPTER padapter; + _adapter *padapter; u16 ret; u32 data; @@ -3507,21 +3256,23 @@ int proc_get_btreg_write(struct seq_file *m, void *v) } dev = m->private; - padapter = (PADAPTER)rtw_netdev_priv(dev); + padapter = (_adapter *)rtw_netdev_priv(dev); - ret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data); + ret = rtw_btc_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data); if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data); else RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret); +#endif return 0; } ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#if 0 struct net_device *dev = data; - PADAPTER padapter; + _adapter *padapter; u8 tmp[80] = {0}; u32 num; u16 val; @@ -3529,7 +3280,7 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ int err; - padapter = (PADAPTER)rtw_netdev_priv(dev); + padapter = (_adapter *)rtw_netdev_priv(dev); if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", @@ -3563,91 +3314,19 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n", FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val); - ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val); + ret = rtw_btc_btreg_write(padapter, btreg_write_type, btreg_write_addr, val); if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) err = ret; exit: btreg_write_error = err; +#endif return count; } -int proc_get_btc_reduce_wl_txpwr(struct seq_file *m, void *v) -{ - struct net_device *dev; - PADAPTER padapter; - u8 data; - - dev = m->private; - padapter = (PADAPTER)rtw_netdev_priv(dev); - - data = rtw_btcoex_get_reduce_wl_txpwr(padapter); - RTW_PRINT_SEL(m, "BTC reduce WL TxPwr = %d dB\n", data); - - return 0; -} - -ssize_t proc_set_btc_reduce_wl_txpwr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - PADAPTER padapter; - HAL_DATA_TYPE *hal_data; - u8 tmp[80] = {0}; - u32 val = 0; - u32 num; - - padapter = (PADAPTER)rtw_netdev_priv(dev); - hal_data = GET_HAL_DATA(padapter); - - /* RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */ - - if (NULL == buffer) { - RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", - FUNC_ADPT_ARG(padapter)); - - return -EFAULT; - } - - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", - FUNC_ADPT_ARG(padapter)); - - return -EFAULT; - } - - num = count; - if (num > (sizeof(tmp) - 1)) - num = (sizeof(tmp) - 1); - - if (copy_from_user(tmp, buffer, num)) { - RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", - FUNC_ADPT_ARG(padapter)); - - return -EFAULT; - } - - num = sscanf(tmp, "%d", &val); - - if ((IS_HARDWARE_TYPE_8822C(padapter)) && (hal_data->EEPROMBluetoothCoexist == _TRUE)) - rtw_btc_reduce_wl_txpwr_cmd(padapter, val); - - return count; -} - -#endif /* CONFIG_BT_COEXIST */ - -#ifdef CONFIG_MBSSID_CAM -int proc_get_mbid_cam_cache(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); +#endif /* CONFIG_BTC */ - rtw_mbid_cam_cache_dump(m, __func__, adapter); - rtw_mbid_cam_dump(m, __func__, adapter); - return 0; -} -#endif /* CONFIG_MBSSID_CAM */ int proc_get_mac_addr(struct seq_file *m, void *v) { @@ -3704,6 +3383,15 @@ static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, } #ifdef CONFIG_RTW_ACS +#ifdef WKARD_ACS +static void rtw_acs_chan_info_dump(struct seq_file *m, _adapter *a) +{ +} + +static void rtw_acs_info_dump(struct seq_file *m, _adapter *a) +{ +} + static int proc_get_chan_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -3772,55 +3460,25 @@ static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t #endif /*CONFIG_RTW_ACS_DBG*/ return count; } +#endif /* WKARD_ACS */ #endif /*CONFIG_RTW_ACS*/ -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR -static int proc_get_nm(struct seq_file *m, void *v) +static int proc_get_env_rpt(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - rtw_noise_info_dump(m, adapter); - return 0; -} - -static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 nm_state = 0; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu", &nm_state); - - if (num < 1) - return -EINVAL; - - if (nm_state) - rtw_nm_enable(padapter); - else - rtw_nm_disable(padapter); + rtw_dump_env_rpt(adapter, m); - } - return count; + return 0; } -#endif /*CONFIG_RTW_ACS*/ static int proc_get_hal_spec(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_hal_spec(m, adapter); + rtw_hw_dump_hal_spec(m, adapter_to_dvobj(adapter)); return 0; } @@ -3829,7 +3487,7 @@ static int proc_get_hal_trx_mode(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = rtw_netdev_priv(dev); - dump_hal_trx_mode(m, adapter); + rtw_hal_dump_trx_mode(m, adapter); return 0; } @@ -3838,7 +3496,6 @@ static int proc_get_phy_cap(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - rtw_dump_phy_cap(m, adapter); #ifdef CONFIG_80211N_HT rtw_dump_drv_phy_cap(m, adapter); rtw_get_dft_phy_cap(m, adapter); @@ -3846,24 +3503,12 @@ static int proc_get_phy_cap(struct seq_file *m, void *v) return 0; } -#ifdef CONFIG_SUPPORT_TRX_SHARED -#include "../../hal/hal_halmac.h" -static int proc_get_trx_share_mode(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - dump_trx_share_mode(m, adapter); - return 0; -} -#endif - static int proc_dump_rsvd_page(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - rtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num); + rtw_hal_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num); return 0; } static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) @@ -3932,24 +3577,27 @@ static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, } #endif -#ifdef CONFIG_WOW_PATTERN_HW_CAM + +#ifdef CONFIG_WOWLAN int proc_dump_pattern_cam(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); int i; + #if 0 /* WOW_ToDo */ struct rtl_wow_pattern context; for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) { rtw_wow_pattern_read_cam_ent(padapter, i, &context); rtw_dump_wow_pattern(m, &context, i); } - + #endif return 0; } #endif + static int proc_get_napi_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -3997,10 +3645,10 @@ static int proc_get_napi_info(struct seq_file *m, void *v) static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *registry = &adapter->registrypriv; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - PADAPTER iface = NULL; + _adapter *iface = NULL; char tmp[32] = {0}; int thrshld = 0; int num = 0, i = 0; @@ -4054,7 +3702,7 @@ ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer if (buffer && !copy_from_user(tmp, buffer, count)) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - PADAPTER iface = NULL; + _adapter *iface = NULL; int num = sscanf(tmp, "%d", &enable); if (num != 1) { @@ -4243,7 +3891,6 @@ static int proc_get_unassoc_sta(struct seq_file *m, void *v) _adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev)); dump_unassoc_sta(m, adapter); - return 0; } @@ -4309,14 +3956,17 @@ ssize_t proc_set_unassoc_sta(struct file *file, const char __user *buffer, size_ RTW_WARN(FUNC_ADPT_FMT" invalid arguments of mode cmd\n", FUNC_ADPT_ARG(adapter)); goto exit; } + if (stype >= UNASOC_STA_SRC_NUM) { RTW_WARN(FUNC_ADPT_FMT" invalid stype:%u\n", FUNC_ADPT_ARG(adapter), stype); goto exit; } + if (mode >= UNASOC_STA_MODE_NUM) { RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u\n", FUNC_ADPT_ARG(adapter), mode); goto exit; } + rtw_unassoc_sta_set_mode(adapter, stype, mode); break; @@ -4346,7 +3996,7 @@ ssize_t proc_set_unassoc_sta(struct file *file, const char __user *buffer, size_ } else rtw_undo_interested_unassoc_sta(adapter, addr); } else if (!is_bcast) - rtw_add_interested_unassoc_sta(adapter, addr); + rtw_add_interested_unassoc_sta(adapter, addr); } c = strsep(&next, " \t"); @@ -4377,7 +4027,6 @@ int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v) if (MLME_IS_AP(adapter)) { struct sta_info *psta; - _irqL irqL; u8 *passoc_req = NULL; u32 assoc_req_len = 0; @@ -4387,9 +4036,10 @@ int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v) FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr)); return 0; } + RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") found\n", FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr)); - _enter_critical_bh(&psta->lock, &irqL); + _rtw_spinlock_bh(&psta->lock); if (psta->passoc_req && psta->assoc_req_len > 0) { passoc_req = rtw_zmalloc(psta->assoc_req_len); if (passoc_req) { @@ -4397,7 +4047,8 @@ int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v) _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); } } - _exit_critical_bh(&psta->lock, &irqL); + + _rtw_spinunlock_bh(&psta->lock); if (passoc_req && assoc_req_len > IEEE80211_3ADDR_LEN) { u8 *body = passoc_req + IEEE80211_3ADDR_LEN; u32 body_len = assoc_req_len - IEEE80211_3ADDR_LEN; @@ -4407,6 +4058,7 @@ int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v) _RTW_PRINT_SEL(m, "%02X", body[i]); _RTW_PRINT_SEL(m, "\n"); } + if (passoc_req && assoc_req_len > 0) rtw_mfree(passoc_req, assoc_req_len); } @@ -4890,7 +4542,7 @@ static int proc_get_mesh_gate_state(struct seq_file *m, void *v) static int proc_get_peer_alive_based_preq(struct seq_file *m, void *v) { struct net_device *dev = m->private; - struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev); + _adapter *adapter= (_adapter *)rtw_netdev_priv(dev); struct registry_priv *rp = &adapter->registrypriv; RTW_PRINT_SEL(m, "peer_alive_based_preq = %u\n", @@ -4904,7 +4556,7 @@ proc_set_peer_alive_based_preq(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *rp = &adapter->registrypriv; char tmp[8]; int num = 0; @@ -4933,13 +4585,14 @@ proc_set_peer_alive_based_preq(struct file *file, const char __user *buffer, exit: return count; } + #endif /* CONFIG_RTW_MESH */ #ifdef RTW_BUSY_DENY_SCAN static int proc_get_scan_interval_thr(struct seq_file *m, void *v) { struct net_device *dev = m->private; - struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev); + _adapter *adapter= (_adapter *)rtw_netdev_priv(dev); struct registry_priv *rp = &adapter->registrypriv; @@ -4954,7 +4607,7 @@ static ssize_t proc_set_scan_interval_thr(struct file *file, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev); + _adapter *adapter= (_adapter *)rtw_netdev_priv(dev); struct registry_priv *rp = &adapter->registrypriv; char tmp[12]; int num = 0; @@ -4989,7 +4642,7 @@ static ssize_t proc_set_scan_interval_thr(struct file *file, static int proc_get_scan_deny(struct seq_file *m, void *v) { struct net_device *dev = m->private; - struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev); + _adapter *adapter= (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); RTW_PRINT_SEL(m, "scan_deny is %s\n", (dvobj->scan_deny == _TRUE) ? "enable":"disable"); @@ -5001,7 +4654,7 @@ static ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); char tmp[8]; int num = 0; @@ -5030,144 +4683,82 @@ static ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer, return count; } -#ifdef CONFIG_RTW_TPT_MODE -static int proc_get_tpt_mode(struct seq_file *m, void *v) +int proc_get_cur_beacon_keys(struct seq_file *m, void *v) { struct net_device *dev = m->private; - struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *adapter = rtw_netdev_priv(dev); + struct mlme_priv *mlme = &adapter->mlmepriv; - RTW_PRINT_SEL(m, "current tpt_mode = %d\n", dvobj->tpt_mode); + rtw_dump_bcn_keys(m, &mlme->cur_beacon_keys); return 0; } -static void tpt_mode_default(struct _ADAPTER *adapter) +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) +static int proc_get_go_hidden_ssid_mode(struct seq_file *m, void *v) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - /* 1. disable scan deny */ - dvobj->scan_deny = _FALSE; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; - /* 2. back to original LPS mode */ -#ifdef CONFIG_LPS - rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt); -#endif + if (pregpriv) + RTW_PRINT_SEL(m, "0x%lx\n", pregpriv->go_hidden_ssid_mode); - /* 3. back to original 2.4 tx bw mode */ - rtw_set_tx_bw_mode(adapter, adapter->registrypriv.tx_bw_mode); + return 0; } -static void rtw_tpt_mode(struct _ADAPTER *adapter) +static ssize_t proc_set_go_hidden_ssid_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - if (dvobj->tpt_mode > 0) { - - /* when enable each tpt mode - 1. scan deny - 2. disable LPS */ - - dvobj->scan_deny = _TRUE; - -#ifdef CONFIG_LPS - rtw_pm_set_lps(adapter, PS_MODE_ACTIVE); -#endif - - } - - switch (dvobj->tpt_mode) { - case 0: /* default mode */ - tpt_mode_default(adapter); - break; - case 1: /* High TP*/ - /*tpt_mode1(adapter);*/ - dvobj->edca_be_ul = 0x5e431c; - dvobj->edca_be_dl = 0x00431c; - break; - case 2: /* noise */ - /* tpt_mode2(adapter); */ - dvobj->edca_be_ul = 0x00431c; - dvobj->edca_be_dl = 0x00431c; - - rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */ - break; - case 3: /* long distance */ - /* tpt_mode3(adapter); */ - dvobj->edca_be_ul = 0x00431c; - dvobj->edca_be_dl = 0x00431c; - - rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */ - break; - case 4: /* noise + long distance */ - /* tpt_mode4(adapter); */ - dvobj->edca_be_ul = 0x00431c; - dvobj->edca_be_dl = 0x00431c; - - rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */ - break; - default: /* default mode */ - tpt_mode_default(adapter); - break; - } - -} -static ssize_t proc_set_tpt_mode(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) -{ struct net_device *dev = data; - struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; char tmp[32]; - int num = 0; - int mode = 0; + int go_hidden_ssid_mode, feature_bit; -#define MAX_TPT_MODE_NUM 4 + if (!padapter) + return -EFAULT; + + if (count < 1) { + RTW_INFO("argument size is less than 1\n"); + return -EFAULT; + } if (count > sizeof(tmp)) { rtw_warn_on(1); return -EFAULT; } - if (!buffer || copy_from_user(tmp, buffer, count)) - goto exit; - - num = sscanf(tmp, "%d", &mode); - if (num != 1) { - RTW_ERR("%s: invalid parameter!\n", __FUNCTION__); - goto exit; - } + if (buffer && !copy_from_user(tmp, buffer, count)) { - if (mode > MAX_TPT_MODE_NUM ) - mode = 0; + int num = sscanf(tmp, "%d %d",&feature_bit, &go_hidden_ssid_mode); - RTW_PRINT("%s: previous mode = %d\n", - __FUNCTION__, dvobj->tpt_mode); + if (num < 1) + return -EINVAL; - RTW_PRINT("%s: enabled mode = %d\n", - __FUNCTION__, mode); + /* Cancel hide_ssid_timer and reset flag when unhide SSID by proc */ + if (!feature_bit && !go_hidden_ssid_mode) { + ATOMIC_SET(&pregpriv->set_hide_ssid_timer, 0); + _cancel_timer_ex(&pmlmeext->hide_ssid_timer); + } + if (go_hidden_ssid_mode == 1) + rtw_set_bit(feature_bit, &pregpriv->go_hidden_ssid_mode); + else if (!go_hidden_ssid_mode) + rtw_clear_bit(feature_bit, &pregpriv->go_hidden_ssid_mode); + else + return -EFAULT; - dvobj->tpt_mode = mode; + RTW_INFO("go_hidden_ssid_mode:0x%lx\n", pregpriv->go_hidden_ssid_mode); + } else + return -EFAULT; - rtw_tpt_mode(adapter); + issue_beacon(padapter, 0); -exit: return count; - } -#endif /* CONFIG_RTW_TPT_MODE */ - -int proc_get_cur_beacon_keys(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = rtw_netdev_priv(dev); - struct mlme_priv *mlme = &adapter->mlmepriv; - - rtw_dump_bcn_keys(m, &mlme->cur_beacon_keys); - return 0; -} +#endif static int proc_get_amsdu_mode(struct seq_file *m, void *v) { @@ -5225,6 +4816,93 @@ static ssize_t proc_set_amsdu_mode(struct file *file, const char __user *buffer, } +#ifdef ROKU_PRIVATE +static int proc_get_vendor_ie_filter(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + int i, j; + + if (!mlmepriv) + return -EFAULT; + + RTW_PRINT_SEL(m, "enable: %u\n", mlmepriv->vendor_ie_filter_enable); + RTW_PRINT_SEL(m, "index\tcontent\n"); + + for (i = 0; i < MAX_VENDOR_IE_NUM; i++) { + RTW_PRINT_SEL(m, "%d\t", i); + if (mlmepriv->vendor_ie_len[i]) + for (j = 0; j < mlmepriv->vendor_ie_len[i] + 2; j++) + RTW_PRINT_SEL(m, "%02x", mlmepriv->vendor_ie_filter[i][j]); + RTW_PRINT_SEL(m, "\n"); + } + + return 0; +} + +static ssize_t proc_set_vendor_ie_filter(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + char tmp[MAX_VENDOR_IE_PARAM_LEN]; + u8 vendor_ie_num = 0; + u8 *vendor_ie; + u8 enable; + int num, i, len = 0; + + vendor_ie = rtw_malloc(MAX_VENDOR_IE_LEN); + + if (!vendor_ie || !adapter) + return -EFAULT; + + if (count < 1) { + RTW_INFO("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + if (count > 2) { + num = sscanf(tmp, "%hhu %s", &vendor_ie_num, vendor_ie); + + if (num < 1) + return -EINVAL; + + if (vendor_ie_num > MAX_VENDOR_IE_NUM - 1) + return -EINVAL; + + if (_rtw_memcmp(vendor_ie, "0", 1)) { + _rtw_memset(mlmepriv->vendor_ie_filter[vendor_ie_num] , 0 , MAX_VENDOR_IE_LEN); + mlmepriv->vendor_ie_len[vendor_ie_num] = 0; + } + + for (i = 0; i < strlen(vendor_ie); i += 2) { + mlmepriv->vendor_ie_filter[vendor_ie_num][len] = key_2char2num(vendor_ie[i], vendor_ie[i+1]); + if (len == 1) + mlmepriv->vendor_ie_len[vendor_ie_num] = mlmepriv->vendor_ie_filter[vendor_ie_num][len]; + len++; + } + rtw_mfree(vendor_ie, MAX_VENDOR_IE_LEN); + } else if (count == 2) { + num = sscanf(tmp, "%hhu", &mlmepriv->vendor_ie_filter_enable); + } else { + RTW_INFO("argument size is wrong\n"); + return -EINVAL; + } + } else { + return -EFAULT; + } + + return count; +} +#endif + /* * rtw_adapter_proc: * init/deinit when register/unregister net_device @@ -5235,6 +4913,9 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #endif RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg), RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg), + + RTW_PROC_HDL_SSEQ("mac_dbg_status_dump", NULL, proc_set_mac_dbg_status_dump), + RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL), RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL), #ifdef CONFIG_RTW_CUSTOMER_STR @@ -5247,7 +4928,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL), RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL), RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param), - RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL), + RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, proc_set_scan_abort), #ifdef CONFIG_SCAN_BACKOP RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta), #ifdef CONFIG_AP_MODE @@ -5256,9 +4937,6 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_RTW_MESH RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh), #endif -#endif -#ifdef CONFIG_RTW_REPEATER_SON - RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data), #endif RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info), RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL), @@ -5270,10 +4948,16 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl), RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl), RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL), - RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), - RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), + /*RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), */ + /* RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), */ RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam), RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL), +#ifdef CONFIG_DBG_AX_CAM + RTW_PROC_HDL_SSEQ("dump_ax_valid_key", proc_get_ax_valid_key, NULL), + RTW_PROC_HDL_SSEQ("dump_ax_address_cam", proc_get_ax_address_cam, NULL), + RTW_PROC_HDL_SSEQ("dump_ax_security_cam", proc_get_ax_sec_cam, NULL), +#endif + RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info), RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL), #ifdef CONFIG_LAYER2_ROAMING @@ -5284,6 +4968,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_RTW_MBO RTW_PROC_HDL_SSEQ("non_pref_ch", rtw_mbo_proc_non_pref_chans_get, rtw_mbo_proc_non_pref_chans_set), RTW_PROC_HDL_SSEQ("cell_data", rtw_mbo_proc_cell_data_get, rtw_mbo_proc_cell_data_set), + RTW_PROC_HDL_SSEQ("mbo_attr", rtw_mbo_proc_attr_get, rtw_mbo_proc_attr_set), #endif #ifdef CONFIG_RTW_80211R RTW_PROC_HDL_SSEQ("ft_flags", rtw_ft_proc_flags_get, rtw_ft_proc_flags_set), @@ -5293,18 +4978,11 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL), RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL), RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL), - #ifdef CONFIG_SDIO_RECVBUF_AGGREGATION - RTW_PROC_HDL_SSEQ("sdio_recvbuf_aggregation", proc_get_sdio_recvbuf_aggregation, proc_set_sdio_recvbuf_aggregation), - #endif - #ifdef CONFIG_SDIO_RECVBUF_PWAIT - RTW_PROC_HDL_SSEQ("sdio_recvbuf_pwait", proc_get_sdio_recvbuf_pwait, proc_set_sdio_recvbuf_pwait), - #endif #ifdef DBG_SDIO RTW_PROC_HDL_SSEQ("sdio_dbg", proc_get_sdio_dbg, proc_set_sdio_dbg), #endif /* DBG_SDIO */ #endif /* CONFIG_SDIO_HCI */ - RTW_PROC_HDL_SSEQ("fwdl_test_case", NULL, proc_set_fwdl_test_case), RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case), RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty), RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test), @@ -5317,13 +4995,12 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL), RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL), -#ifdef CONFIG_RTW_LED +#if 0 RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config), #endif #ifdef CONFIG_AP_MODE RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status), - RTW_PROC_HDL_SSEQ("ap_isolate", proc_get_ap_isolate, proc_set_ap_isolate), RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL), RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate), #if CONFIG_RTW_AP_DATA_BMC_TO_UC @@ -5362,11 +5039,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_80211AC_VHT RTW_PROC_HDL_SSEQ("vht_24g_enable", proc_get_vht_24g_enable, proc_set_vht_24g_enable), -#endif - - #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT - RTW_PROC_HDL_SSEQ("tx_aval_int_threshold", proc_get_tx_aval_th, proc_set_tx_aval_th), - #endif +#endif /* CONFIG_80211AC_VHT */ RTW_PROC_HDL_SSEQ("dynamic_rrsr", proc_get_dyn_rrsr, proc_set_dyn_rrsr), RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps), @@ -5374,17 +5047,12 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { /* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL), * RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */ -#ifdef CONFIG_BT_COEXIST - RTW_PROC_HDL_SSEQ("btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg), - RTW_PROC_HDL_SSEQ("btcoex", proc_get_btcoex_info, NULL), - RTW_PROC_HDL_SSEQ("btinfo_evt", NULL, proc_set_btinfo_evt), +#ifdef CONFIG_BTC + RTW_PROC_HDL_SSEQ("btc_dbg", proc_get_btc_dbg, proc_set_btc_dbg), + RTW_PROC_HDL_SSEQ("btc", proc_get_btc_info, NULL), RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read), RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write), - RTW_PROC_HDL_SSEQ("btc_reduce_wl_txpwr", proc_get_btc_reduce_wl_txpwr, proc_set_btc_reduce_wl_txpwr), -#ifdef CONFIG_RF4CE_COEXIST - RTW_PROC_HDL_SSEQ("rf4ce_state", proc_get_rf4ce_state, proc_set_rf4ce_state), -#endif -#endif /* CONFIG_BT_COEXIST */ +#endif /* CONFIG_BTC */ #if defined(DBG_CONFIG_ERROR_DETECT) RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset), @@ -5394,13 +5062,15 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_HUAWEI_PROC RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL), #endif - RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump), + RTW_PROC_HDL_SSEQ("rtw_hal_linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump), RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump), RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL), RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl), RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL), RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg), - +#ifdef ROKU_PRIVATE + RTW_PROC_HDL_SSEQ("roku_trx_info_msg", proc_get_roku_trx_info_msg, NULL), +#endif #if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C) RTW_PROC_HDL_SSEQ("lps_pg_debug", proc_get_lps_pg_debug, NULL), #endif @@ -5442,14 +5112,8 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event, proc_set_wakeup_event), RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL), -#ifdef CONFIG_WOW_PATTERN_HW_CAM RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL), #endif -#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN - RTW_PROC_HDL_SSEQ("wow_keep_alive_info", proc_dump_wow_keep_alive_info, NULL), -#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ - -#endif #ifdef CONFIG_GPIO_WAKEUP RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info), @@ -5469,6 +5133,10 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta), #endif RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy), +#ifdef CONFIG_80211D + RTW_PROC_HDL_SSEQ("country_ie_slave_en_conds", proc_get_country_ie_slave_en_conds, proc_set_country_ie_slave_en_conds), + RTW_PROC_HDL_SSEQ("country_ie_slave_records", proc_get_country_ie_slave_records, NULL), +#endif #ifdef CONFIG_DFS_MASTER RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case), RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp), @@ -5478,39 +5146,23 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd), #endif -#endif -#ifdef CONFIG_BCN_CNT_CONFIRM_HDL - RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max), #endif RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport), #ifdef DBG_RX_COUNTER_DUMP RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump), #endif -#ifdef CONFIG_AP_MODE RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw), -#endif -#if CONFIG_TX_AC_LIFETIME - RTW_PROC_HDL_SSEQ("tx_aclt_force_val", proc_get_tx_aclt_force_val, proc_set_tx_aclt_force_val), - RTW_PROC_HDL_SSEQ("tx_aclt_flags", proc_get_tx_aclt_flags, proc_set_tx_aclt_flags), - RTW_PROC_HDL_SSEQ("tx_aclt_confs", proc_get_tx_aclt_confs, proc_set_tx_aclt_confs), -#endif RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode), - RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL), + RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL), RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL), #if CONFIG_TXPWR_LIMIT RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL), #endif - RTW_PROC_HDL_SSEQ("tpc_settings", proc_get_tpc_settings, proc_set_tpc_settings), - RTW_PROC_HDL_SSEQ("antenna_gain", proc_get_antenna_gain, proc_set_antenna_gain), RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info), - RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, proc_set_tx_power_idx_dump), - RTW_PROC_HDL_SEQ("txpwr_total_dbm", &seq_ops_txpwr_total_dbm, proc_set_txpwr_total_dbm_dump), -#ifdef CONFIG_RF_POWER_TRIM - RTW_PROC_HDL_SSEQ("tx_gain_offset", NULL, proc_set_tx_gain_offset), - RTW_PROC_HDL_SSEQ("kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag), - RTW_PROC_HDL_SSEQ("kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain), - RTW_PROC_HDL_SSEQ("kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal), +#ifdef GEORGIA_TODO_TX_PWR + RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, NULL), + RTW_PROC_HDL_SEQ("txpwr_total_dbm", &seq_ops_txpwr_total_dbm, NULL), #endif #ifdef CONFIG_POWER_SAVING RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, proc_set_ps_info), @@ -5523,18 +5175,17 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable), #endif RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor), -#ifdef RTW_SIMPLE_CONFIG - RTW_PROC_HDL_SSEQ("rtw_simple_config", proc_get_simple_config, proc_set_simple_config), -#endif #ifdef CONFIG_RTW_ACS +#ifdef WKARD_ACS RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs), RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL), #endif - -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR - RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm), #endif + RTW_PROC_HDL_SSEQ("env_info", proc_get_env_rpt, NULL), + RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL), + RTW_PROC_HDL_SSEQ("hal_trx_mode", proc_get_hal_trx_mode, NULL), + RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL), #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL), @@ -5546,17 +5197,8 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth), #endif /* CONFIG_IEEE80211W */ -#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA - RTW_PROC_HDL_SSEQ("pathb_phase", proc_get_pathb_phase, proc_set_pathb_phase), -#endif - -#ifdef CONFIG_MBSSID_CAM - RTW_PROC_HDL_SSEQ("mbid_cam", proc_get_mbid_cam_cache, NULL), -#endif RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL), RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band), - RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL), - RTW_PROC_HDL_SSEQ("hal_trx_mode", proc_get_hal_trx_mode, NULL), RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL), @@ -5564,7 +5206,6 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { /**** PHY Capability ****/ RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL), #ifdef CONFIG_80211N_HT - RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc), RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap), RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap), #endif /* CONFIG_80211N_HT */ @@ -5572,9 +5213,6 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap), #endif -#ifdef CONFIG_SUPPORT_TRX_SHARED - RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL), -#endif RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL), #ifdef CONFIG_RTW_NAPI_DYNAMIC RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th), @@ -5585,7 +5223,12 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_SUPPORT_FIFO_DUMP RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info), #endif - RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL), + +#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST + RTW_PROC_HDL_SSEQ("ignore_go_and_low_rssi_in_scan", + proc_get_ignore_go_and_low_rssi_in_scan, + proc_set_ignore_go_and_low_rssi_in_scan), +#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/ #ifdef DBG_XMIT_BLOCK RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block), @@ -5643,9 +5286,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL), RTW_PROC_HDL_SSEQ("mesh_peer_alive_based_preq", proc_get_peer_alive_based_preq, proc_set_peer_alive_based_preq), #endif -#ifdef CONFIG_FW_HANDLE_TXBCN - RTW_PROC_HDL_SSEQ("fw_tbtt_rpt", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt), -#endif + #ifdef CONFIG_LPS_CHK_BY_TP RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp), #endif @@ -5658,9 +5299,6 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { proc_set_scan_interval_thr), #endif RTW_PROC_HDL_SSEQ("scan_deny", proc_get_scan_deny, proc_set_scan_deny), -#ifdef CONFIG_RTW_TPT_MODE - RTW_PROC_HDL_SSEQ("tpt_mode", proc_get_tpt_mode, proc_set_tpt_mode), -#endif #ifdef CONFIG_CTRL_TXSS_BY_TP RTW_PROC_HDL_SSEQ("txss_tp", proc_get_txss_tp, proc_set_txss_tp), @@ -5671,26 +5309,31 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("cur_beacon_keys", proc_get_cur_beacon_keys, NULL), -#ifdef CONFIG_WAR_OFFLOAD - RTW_PROC_HDL_SSEQ("war_offload_enable", proc_get_war_offload_enable, proc_set_war_offload_enable), - RTW_PROC_HDL_SSEQ("war_offload_ipv4_addr", NULL, proc_set_war_offload_ipv4_addr), - RTW_PROC_HDL_SSEQ("war_offload_ipv6_addr", NULL, proc_set_war_offload_ipv6_addr), -#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) - RTW_PROC_HDL_SSEQ("war_offload_mdns_domain_name", proc_get_war_offload_mdns_domain_name, proc_set_war_offload_mdns_domain_name), - RTW_PROC_HDL_SSEQ("war_offload_mdns_machine_name", proc_get_war_offload_mdns_machine_name, proc_set_war_offload_mdns_machine_name), - RTW_PROC_HDL_SSEQ("war_offload_mdns_service_info", proc_get_war_offload_mdns_service_info, proc_set_war_offload_mdns_service_info), - RTW_PROC_HDL_SSEQ("war_offload_mdns_service_info_txt_rsp", proc_get_war_offload_mdns_txt_rsp, proc_set_war_offload_mdns_txt_rsp), -#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */ -#endif /* CONFIG_WAR_OFFLOAD */ - RTW_PROC_HDL_SSEQ("rtw_amsdu_mode", proc_get_amsdu_mode, proc_set_amsdu_mode), + RTW_PROC_HDL_SSEQ("chan", proc_get_chan, proc_set_chan), + + RTW_PROC_HDL_SSEQ("mr_test", proc_get_mr_test, proc_set_mr_test), + RTW_PROC_HDL_SSEQ("deny_legacy", proc_get_deny_legacy, proc_set_deny_legacy), +#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P) + RTW_PROC_HDL_SSEQ("go_hidden_ssid_mode", proc_get_go_hidden_ssid_mode, proc_set_go_hidden_ssid_mode), +#endif + RTW_PROC_HDL_SSEQ("rtw_amsdu_mode", proc_get_amsdu_mode, proc_set_amsdu_mode), +#ifdef CONFIG_80211AX_HE + RTW_PROC_HDL_SSEQ("tx_ul_mu_disable", proc_get_tx_ul_mu_disable, proc_set_tx_ul_mu_disable), +#endif +#ifdef ROKU_PRIVATE + RTW_PROC_HDL_SSEQ("vendor_ie_filter", proc_get_vendor_ie_filter, proc_set_vendor_ie_filter), +#endif +#ifdef RTW_DETECT_HANG + RTW_PROC_HDL_SSEQ("hang_info", proc_get_hang_info, NULL), +#endif }; const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl); static int rtw_adapter_proc_open(struct inode *inode, struct file *file) { - ssize_t index = (ssize_t)pde_data(inode); + ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index; void *private = proc_get_parent_data(inode); @@ -5708,7 +5351,11 @@ static int rtw_adapter_proc_open(struct inode *inode, struct file *file) } else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) { int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) return single_open_size(file, show, private, hdl->u.sz.size); + #else + return single_open(file, show, private); + #endif } else { return -EROFS; } @@ -5716,7 +5363,7 @@ static int rtw_adapter_proc_open(struct inode *inode, struct file *file) static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { - ssize_t index = (ssize_t)pde_data(file_inode(file)); + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -5748,7 +5395,7 @@ static const struct rtw_proc_ops rtw_adapter_proc_sseq_fops = { .proc_open = rtw_adapter_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, - .proc_release = single_release, + .proc_release = seq_release, .proc_write = rtw_adapter_proc_write, #else .owner = THIS_MODULE, @@ -5760,17 +5407,18 @@ static const struct rtw_proc_ops rtw_adapter_proc_sseq_fops = { #endif }; -int proc_get_odm_adaptivity(struct seq_file *m, void *v) +int proc_get_phy_adaptivity(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - rtw_odm_adaptivity_parm_msg(m, padapter); + rtw_cfg_adaptivity_config_msg(m, padapter); + rtw_hal_phy_adaptivity_parm_msg(m, padapter); return 0; } -ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_phy_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5793,7 +5441,7 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si if (num != 2) return count; - rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff); + rtw_hal_phy_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff); } return count; @@ -5802,23 +5450,21 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si static char *phydm_msg = NULL; #define PHYDM_MSG_LEN 80*24*4 -int proc_get_phydm_cmd(struct seq_file *m, void *v) +static int proc_get_phydm_cmd(struct seq_file *m, void *v) { - struct net_device *netdev; - PADAPTER padapter; - struct dm_struct *phydm; - - - netdev = m->private; - padapter = (PADAPTER)rtw_netdev_priv(netdev); - phydm = adapter_to_phydm(padapter); + struct net_device *netdev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(netdev); if (NULL == phydm_msg) { + _RTW_PRINT_SEL(m, "(Nothing to output)\n"); + return 0; +#if 0 phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); if (NULL == phydm_msg) return -ENOMEM; phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN); +#endif } _RTW_PRINT_SEL(m, "%s\n", phydm_msg); @@ -5829,25 +5475,24 @@ int proc_get_phydm_cmd(struct seq_file *m, void *v) return 0; } -ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_get_phl_cmd(struct seq_file *m, void *v) { - struct net_device *netdev; - PADAPTER padapter; - struct dm_struct *phydm; - char tmp[64] = {0}; - + return proc_get_phydm_cmd(m, v); +} - netdev = (struct net_device *)data; - padapter = (PADAPTER)rtw_netdev_priv(netdev); - phydm = adapter_to_phydm(padapter); +static ssize_t proc_set_phydm_cmd(struct file *file, char *buffer, size_t count, + loff_t *pos, void *data, + enum rtw_proc_cmd_type type) +{ + struct net_device *netdev = (struct net_device *)data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(netdev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_proc_cmd cmd; if (count < 1) return -EFAULT; - if (count > sizeof(tmp)) - return -EFAULT; - - if (buffer && !copy_from_user(tmp, buffer, count)) { + if (buffer) { if (NULL == phydm_msg) { phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); if (NULL == phydm_msg) @@ -5855,7 +5500,11 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t } else _rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN); - phydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN); + cmd.in_type = RTW_ARG_TYPE_BUF; + cmd.in_cnt_len = count; + cmd.in.buf = buffer; + + rtw_phl_proc_cmd(GET_PHL_INFO(dvobj), type, &cmd, phydm_msg, PHYDM_MSG_LEN); if (strlen(phydm_msg) == 0) { rtw_mfree(phydm_msg, PHYDM_MSG_LEN); @@ -5866,20 +5515,87 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t return count; } +static ssize_t proc_set_phl_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char *buf, *p; + enum rtw_proc_cmd_type type; + ssize_t ret, len; + int type_len; + + buf = _rtw_malloc(count + 1); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, buffer, count)) { + ret = -EFAULT; + goto err; + } + + if (strncmp(buf, "bb ", 3) == 0) { + type = RTW_PROC_CMD_BB; + type_len = 3; + } else if (strncmp(buf, "rf ", 3) == 0) { + type = RTW_PROC_CMD_RF; + type_len = 3; + } else if (strncmp(buf, "mac ", 4) == 0) { + type = RTW_PROC_CMD_MAC; + type_len = 4; + } else if (strncmp(buf, "phl ", 4) == 0) { + type = RTW_PROC_CMD_PHL; + type_len = 4; + } else if (strncmp(buf, "core ", 5) == 0) { + printk("%s(%d)\n",__func__,__LINE__); + type = RTW_PROC_CMD_CORE; + type_len = 5; + } else if (strncmp(buf, "btc ", 4) == 0) { + printk("%s(%d)\n",__func__,__LINE__); + type = RTW_PROC_CMD_BTC; + type_len = 4; + } else if (strncmp(buf, "efuse ", 6) == 0) { + type = RTW_PROC_CMD_EFUSE; + type_len = 6; + } else { + ret = -EINVAL; + goto err; + } + + /* skip first type token, like 'bb ', 'rf ' */ + p = buf + type_len; + len = count - type_len; + + /* remove trailing newline character, because BB/RF parser uses + * " ," as delimiter that leads the last token contains '\n' if + * we use 'echo' command without '-n' argument. + */ + if (p[len - 1] == '\n') + len--; + p[len++] = '\0'; + + ret = proc_set_phydm_cmd(file, p, len, pos, data, type); + +err: + _rtw_mfree(buf, count + 1); + + if (ret >= 0) + return count; + + return ret; +} + /* * rtw_odm_proc: * init/deinit when register/unregister net_device, along with rtw_adapter_proc */ const struct rtw_proc_hdl odm_proc_hdls[] = { - RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity), - RTW_PROC_HDL_SZSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd, PHYDM_MSG_LEN), + RTW_PROC_HDL_SSEQ("adaptivity", proc_get_phy_adaptivity, proc_set_phy_adaptivity), + RTW_PROC_HDL_SZSEQ("phl_cmd", proc_get_phl_cmd, proc_set_phl_cmd, PHYDM_MSG_LEN), }; const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl); static int rtw_odm_proc_open(struct inode *inode, struct file *file) { - ssize_t index = (ssize_t)pde_data(inode); + ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = odm_proc_hdls + index; void *private = proc_get_parent_data(inode); @@ -5897,7 +5613,11 @@ static int rtw_odm_proc_open(struct inode *inode, struct file *file) } else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) { int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) return single_open_size(file, show, private, hdl->u.sz.size); + #else + return single_open(file, show, private); + #endif } else { return -EROFS; } @@ -5905,7 +5625,7 @@ static int rtw_odm_proc_open(struct inode *inode, struct file *file) static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { - ssize_t index = (ssize_t)pde_data(file_inode(file)); + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = odm_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -5993,7 +5713,7 @@ struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) return dir_odm; } -void rtw_odm_proc_deinit(_adapter *adapter) +void rtw_odm_proc_deinit(_adapter *adapter) { struct proc_dir_entry *dir_odm = NULL; int i; @@ -6018,167 +5738,6 @@ void rtw_odm_proc_deinit(_adapter *adapter) } } -#ifdef CONFIG_MCC_MODE -/* -* rtw_mcc_proc: -* init/deinit when register/unregister net_device, along with rtw_adapter_proc -*/ -const struct rtw_proc_hdl mcc_proc_hdls[] = { - RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL), - RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable), - RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration), - #ifdef CONFIG_MCC_PHYDM_OFFLOAD - RTW_PROC_HDL_SSEQ("mcc_phydm_offload", proc_get_mcc_info, proc_set_mcc_phydm_offload_enable), - #endif - RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria), - RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp), - RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp), - RTW_PROC_HDL_SSEQ("mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp), - RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp), - RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp), - RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp), - RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL), -}; - -const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl); - -static int rtw_mcc_proc_open(struct inode *inode, struct file *file) -{ - ssize_t index = (ssize_t)pde_data(inode); - const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index; - void *private = proc_get_parent_data(inode); - - if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) { - int res = seq_open(file, hdl->u.seq_op); - - if (res == 0) - ((struct seq_file *)file->private_data)->private = private; - - return res; - } else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) { - int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy; - - return single_open(file, show, private); - } else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) { - int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy; - - return single_open_size(file, show, private, hdl->u.sz.size); - } else { - return -EROFS; - } -} - -static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) -{ - ssize_t index = (ssize_t)pde_data(file_inode(file)); - const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index; - ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; - - if (write) - return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private); - - return -EROFS; -} - -static const struct rtw_proc_ops rtw_mcc_proc_seq_fops = { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) - .proc_open = rtw_mcc_proc_open, - .proc_read = seq_read, - .proc_lseek = seq_lseek, - .proc_release = seq_release, - .proc_write = rtw_mcc_proc_write, -#else - .owner = THIS_MODULE, - .open = rtw_mcc_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release, - .write = rtw_mcc_proc_write, -#endif -}; - -static const struct rtw_proc_ops rtw_mcc_proc_sseq_fops = { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) - .proc_open = rtw_mcc_proc_open, - .proc_read = seq_read, - .proc_lseek = seq_lseek, - .proc_release = single_release, - .proc_write = rtw_mcc_proc_write, -#else - .owner = THIS_MODULE, - .open = rtw_mcc_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .write = rtw_mcc_proc_write, -#endif -}; - -struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) -{ - struct proc_dir_entry *dir_mcc = NULL; - struct proc_dir_entry *entry = NULL; - _adapter *adapter = rtw_netdev_priv(dev); - ssize_t i; - - if (adapter->dir_dev == NULL) { - rtw_warn_on(1); - goto exit; - } - - if (adapter->dir_mcc != NULL) { - rtw_warn_on(1); - goto exit; - } - - dir_mcc = rtw_proc_create_dir("mcc", adapter->dir_dev, dev); - if (dir_mcc == NULL) { - rtw_warn_on(1); - goto exit; - } - - adapter->dir_mcc = dir_mcc; - - for (i = 0; i < mcc_proc_hdls_num; i++) { - if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) - entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i); - else if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ || - mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ) - entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i); - else - entry = NULL; - - if (!entry) { - rtw_warn_on(1); - goto exit; - } - } - -exit: - return dir_mcc; -} - -void rtw_mcc_proc_deinit(_adapter *adapter) -{ - struct proc_dir_entry *dir_mcc = NULL; - int i; - - dir_mcc = adapter->dir_mcc; - - if (dir_mcc == NULL) { - rtw_warn_on(1); - return; - } - - for (i = 0; i < mcc_proc_hdls_num; i++) - remove_proc_entry(mcc_proc_hdls[i].name, dir_mcc); - - remove_proc_entry("mcc", adapter->dir_dev); - - adapter->dir_mcc = NULL; -} -#endif /* CONFIG_MCC_MODE */ - struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) { struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); @@ -6221,11 +5780,6 @@ struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) } rtw_odm_proc_init(dev); - -#ifdef CONFIG_MCC_MODE - rtw_mcc_proc_init(dev); -#endif /* CONFIG_MCC_MODE */ - exit: return dir_dev; } @@ -6248,11 +5802,6 @@ void rtw_adapter_proc_deinit(struct net_device *dev) remove_proc_entry(adapter_proc_hdls[i].name, dir_dev); rtw_odm_proc_deinit(adapter); - -#ifdef CONFIG_MCC_MODE - rtw_mcc_proc_deinit(adapter); -#endif /* CONFIG_MCC_MODE */ - remove_proc_entry(dev->name, drv_proc); adapter->dir_dev = NULL; @@ -6277,10 +5826,6 @@ void rtw_adapter_proc_replace(struct net_device *dev) rtw_odm_proc_deinit(adapter); -#ifdef CONFIG_MCC_MODE - rtw_mcc_proc_deinit(adapter); -#endif /* CONIG_MCC_MODE */ - remove_proc_entry(adapter->old_ifname, drv_proc); adapter->dir_dev = NULL; diff --git a/os_dep/linux/rtw_proc.h b/os_dep/linux/rtw_proc.h index 9247e36..2e9e30f 100644 --- a/os_dep/linux/rtw_proc.h +++ b/os_dep/linux/rtw_proc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/os_dep/linux/rtw_rhashtable.c b/os_dep/linux/rtw_rhashtable.c index df303b2..24ba4de 100644 --- a/os_dep/linux/rtw_rhashtable.c +++ b/os_dep/linux/rtw_rhashtable.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -74,4 +74,3 @@ void kvfree(const void *addr) #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */ #endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */ - diff --git a/os_dep/linux/rtw_rhashtable.h b/os_dep/linux/rtw_rhashtable.h index af5ba7e..f13bd06 100644 --- a/os_dep/linux/rtw_rhashtable.h +++ b/os_dep/linux/rtw_rhashtable.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index 1e51e34..122aef0 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,9 +15,9 @@ #define _HCI_INTF_C_ #include -#include #include +#include #ifndef CONFIG_USB_HCI #error "CONFIG_USB_HCI shall be on!\n" @@ -34,12 +34,11 @@ int ui_pid[3] = {0, 0, 0}; #endif -extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal); -static int rtw_suspend(struct usb_interface *intf, pm_message_t message); -static int rtw_resume(struct usb_interface *intf); +static int rtw_dev_suspend(struct usb_interface *intf, pm_message_t message); +static int rtw_dev_resume(struct usb_interface *intf); -static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid); +static int rtw_dev_probe(struct usb_interface *pusb_intf, const struct usb_device_id *pdid); static void rtw_dev_remove(struct usb_interface *pusb_intf); static void rtw_dev_shutdown(struct device *dev) @@ -55,27 +54,25 @@ static void rtw_dev_shutdown(struct device *dev) if (dvobj) { adapter = dvobj_get_primary_adapter(dvobj); if (adapter) { - if (!rtw_is_surprise_removed(adapter)) { + if (!dev_is_surprise_removed(dvobj)) { #ifdef CONFIG_WOWLAN struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); #ifdef CONFIG_GPIO_WAKEUP /*default wake up pin change to BT*/ RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); - rtw_hal_switch_gpio_wl_ctrl(adapter, pwrctl->wowlan_gpio_index, _FALSE); + /* ToDo: clear pin mux code is not ready + rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE); */ #endif /* CONFIG_GPIO_WAKEUP */ if (pwrctl->wowlan_mode == _TRUE) - RTW_PRINT("%s wowlan_mode ==_TRUE do not run rtw_hal_deinit()\n", __FUNCTION__); + RTW_PRINT("%s wowlan_mode ==_TRUE do not run rtw_hw_stop()\n", __FUNCTION__); else #endif { - #ifdef CONFIG_BT_COEXIST - RTW_INFO("%s call halt notify\n", __FUNCTION__); - rtw_btcoex_HaltNotify(adapter); - #endif - rtw_hal_deinit(adapter); - rtw_set_surprise_removed(adapter); + if (rtw_hw_is_init_completed(dvobj)) + rtw_hw_stop(dvobj); + dev_set_surprise_removed(dvobj); } } } @@ -144,171 +141,21 @@ static void rtw_dev_shutdown(struct device *dev) /* DID_USB_v916_20130116 */ static struct usb_device_id rtw_usb_id_tbl[] = { -#ifdef CONFIG_RTL8188E +#ifdef CONFIG_RTL8852A /*=== Realtek demoboard ===*/ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8179), .driver_info = RTL8188E}, /* 8188EUS */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0179), .driver_info = RTL8188E}, /* 8188ETV */ - /*=== Customer ID ===*/ - /****** 8188EUS ********/ - {USB_DEVICE(0x07B8, 0x8179), .driver_info = RTL8188E}, /* Abocom - Abocom */ -#endif - -#ifdef CONFIG_RTL8812A - /*=== Realtek demoboard ===*/ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8812), .driver_info = RTL8812}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x881A), .driver_info = RTL8812}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x881B), .driver_info = RTL8812}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x881C), .driver_info = RTL8812}, /* Default ID */ - /*=== Customer ID ===*/ - {USB_DEVICE(0x050D, 0x1106), .driver_info = RTL8812}, /* Belkin - sercomm */ - {USB_DEVICE(0x2001, 0x330E), .driver_info = RTL8812}, /* D-Link - ALPHA */ - {USB_DEVICE(0x7392, 0xA822), .driver_info = RTL8812}, /* Edimax - Edimax */ - {USB_DEVICE(0x0DF6, 0x0074), .driver_info = RTL8812}, /* Sitecom - Edimax */ - {USB_DEVICE(0x04BB, 0x0952), .driver_info = RTL8812}, /* I-O DATA - Edimax */ - {USB_DEVICE(0x0789, 0x016E), .driver_info = RTL8812}, /* Logitec - Edimax */ - {USB_DEVICE(0x0409, 0x0408), .driver_info = RTL8812}, /* NEC - */ - {USB_DEVICE(0x0B05, 0x17D2), .driver_info = RTL8812}, /* ASUS - Edimax */ - {USB_DEVICE(0x0E66, 0x0022), .driver_info = RTL8812}, /* HAWKING - Edimax */ - {USB_DEVICE(0x0586, 0x3426), .driver_info = RTL8812}, /* ZyXEL - */ - {USB_DEVICE(0x2001, 0x3313), .driver_info = RTL8812}, /* D-Link - ALPHA */ - {USB_DEVICE(0x1058, 0x0632), .driver_info = RTL8812}, /* WD - Cybertan*/ - {USB_DEVICE(0x1740, 0x0100), .driver_info = RTL8812}, /* EnGenius - EnGenius */ - {USB_DEVICE(0x2019, 0xAB30), .driver_info = RTL8812}, /* Planex - Abocom */ - {USB_DEVICE(0x07B8, 0x8812), .driver_info = RTL8812}, /* Abocom - Abocom */ - {USB_DEVICE(0x2001, 0x3315), .driver_info = RTL8812}, /* D-Link - Cameo */ - {USB_DEVICE(0x2001, 0x3316), .driver_info = RTL8812}, /* D-Link - Cameo */ -#endif - -#ifdef CONFIG_RTL8821A - /*=== Realtek demoboard ===*/ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0811), .driver_info = RTL8821}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0821), .driver_info = RTL8821}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8822), .driver_info = RTL8821}, /* Default ID */ - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0xA811) , .driver_info = RTL8821},/* Default ID */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x0820, 0xff, 0xff, 0xff), .driver_info = RTL8821}, /* 8821AU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x0823, 0xff, 0xff, 0xff), .driver_info = RTL8821}, /* 8821AU */ - /*=== Customer ID ===*/ - {USB_DEVICE(0x7392, 0xA811), .driver_info = RTL8821}, /* Edimax - Edimax */ - {USB_DEVICE(0x04BB, 0x0953), .driver_info = RTL8821}, /* I-O DATA - Edimax */ - {USB_DEVICE(0x2001, 0x3314), .driver_info = RTL8821}, /* D-Link - Cameo */ - {USB_DEVICE(0x2001, 0x3318), .driver_info = RTL8821}, /* D-Link - Cameo */ - {USB_DEVICE(0x0E66, 0x0023), .driver_info = RTL8821}, /* HAWKING - Edimax */ - {USB_DEVICE(0x056E, 0x400E) , .driver_info = RTL8821}, /* ELECOM - ELECOM */ - {USB_DEVICE(0x056E, 0x400F) , .driver_info = RTL8821}, /* ELECOM - ELECOM */ - {USB_DEVICE(0x20f4, 0x804b), .driver_info = RTL8821}, /* TRENDnet */ -#endif - -#ifdef CONFIG_RTL8192E - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x818B, 0xff, 0xff, 0xff), .driver_info = RTL8192E}, /* Default ID */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x818C, 0xff, 0xff, 0xff), .driver_info = RTL8192E}, /* Default ID */ -#endif - -#ifdef CONFIG_RTL8723B - /* === Realtek demoboard === */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB720, 0xff, 0xff, 0xff), .driver_info = RTL8723B}, /* 8723BU 1*1 */ - /* {USB_DEVICE(USB_VENDER_ID_REALTEK, 0xB720),.driver_info = RTL8723B}, 8723BU */ -#endif - -#ifdef CONFIG_RTL8703B - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB703, 0xff, 0xff, 0xff), .driver_info = RTL8703B}, /* 8723CU 1*1 */ - /* {USB_DEVICE(USB_VENDER_ID_REALTEK, 0xB703), .driver_info = RTL723C}, */ /* 8723CU 1*1 */ -#endif /* CONFIG_RTL8703B */ - -#ifdef CONFIG_RTL8814A - - {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8813), .driver_info = RTL8814A}, - {USB_DEVICE(0x2001, 0x331a), .driver_info = RTL8814A}, /* D-Link - D-Link */ - {USB_DEVICE(0x0b05, 0x1817), .driver_info = RTL8814A}, /* ASUS - ASUSTeK */ - {USB_DEVICE(0x056E, 0x400B), .driver_info = RTL8814A}, /* ELECOM - ELECOM */ - {USB_DEVICE(0x056E, 0x400D), .driver_info = RTL8814A}, /* ELECOM - ELECOM */ - {USB_DEVICE(0x7392, 0xA834), .driver_info = RTL8814A}, /* Edimax - Edimax */ -#endif /* CONFIG_RTL8814A */ - -#ifdef CONFIG_RTL8188F - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xF179, 0xff, 0xff, 0xff), .driver_info = RTL8188F}, /* 8188FU 1*1 */ -#endif - -#ifdef CONFIG_RTL8188GTV - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x018C, 0xff, 0xff, 0xff), .driver_info = RTL8188GTV}, /* 8188GTV 1*1 */ -#endif - -#ifdef CONFIG_RTL8822B - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB82C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID for USB multi-function */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB812, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID for USB Single-function, WiFi only */ - /*=== Customer ID ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ - {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1841, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* ASUS AC1300 USB-AC55 B1 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x184C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* ASUS U2*/ - {USB_DEVICE_AND_INTERFACE_INFO(0x0B05, 0x19AA, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* ASUS USB-AC58 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xB822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Edimax EW-7822ULC */ - {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xC822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Edimax EW-7822UTC */ - {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xF822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Edimax EW-7822UAD */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331e, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Dlink - DWA-181 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331c, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Dlink - DWA-182 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331f, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Dlink - DWA-183 D Ver */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3322, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Dlink - DWA-T185 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9055, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* NetGear A6150 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x012D, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* TP-Link Archer T3U */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0138, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* TP-Link Archer T3U Plus */ - {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0115, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* TP-Link Archer T4U V3 */ - {USB_DEVICE_AND_INTERFACE_INFO(0x20F4, 0x808A, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* TRENDnet TEW-808UBM */ -#endif /* CONFIG_RTL8822B */ - -#ifdef CONFIG_RTL8723D - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xD723, 0xff, 0xff, 0xff), .driver_info = RTL8723D}, /* 8723DU 1*1 */ -#endif - -#ifdef CONFIG_RTL8192F - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xF192, 0xff, 0xff, 0xff), .driver_info = RTL8192F}, /* 8192FU 2*2 */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xA725, 0xff, 0xff, 0xff), .driver_info = RTL8192F}, /* 8725AU 2*2 */ -#endif - -#ifdef CONFIG_RTL8821C - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xb82b, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xb820, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC821, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC820, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82A, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82B, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC811, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8811CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x8811, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8811CU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x8731, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8731AU */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC80C, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CUH */ - /*=== Customer ID ===*/ -#endif - -#ifdef CONFIG_RTL8710B - /*=== Realtek dongle ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB711, 0xff, 0xff, 0xff), .driver_info = RTL8710B}, /* 8710B = 8188GU 1*1 */ -#endif + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x8832, 0xff, 0xff, 0xff), .driver_info = RTL8852A}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x885A, 0xff, 0xff, 0xff), .driver_info = RTL8852A}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x885C, 0xff, 0xff, 0xff), .driver_info = RTL8852A}, +#endif /* CONFIG_RTL8852A */ -#ifdef CONFIG_RTL8822C +#ifdef CONFIG_RTL8852B /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82C, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* Default ID for USB multi-function */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82E, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* Default ID for USB multi-function */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC812, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* Default ID for USB Single-function, WiFi only */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xD820, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* 21D USB multi-fuction*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xD82B, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* 21D USB Single-fuction, WiFi only*/ - /*=== Customer ID ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822C}, /* Alpha - Alpha*/ -#endif /* CONFIG_RTL8822C */ - -#ifdef CONFIG_RTL8814B - /*=== Realtek demoboard ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB814, 0xff, 0xff, 0xff), .driver_info = RTL8814B}, /* Default ID for USB multi-function */ -#endif /* CONFIG_RTL8814B */ -#ifdef CONFIG_RTL8723F - /*=== Realtek IC ===*/ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB733, 0xff, 0xff, 0xff), .driver_info = RTL8723F}, -#endif + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB832, 0xff, 0xff, 0xff), .driver_info = RTL8852B}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB83A, 0xff, 0xff, 0xff), .driver_info = RTL8852B}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB852, 0xff, 0xff, 0xff), .driver_info = RTL8852B}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB85A, 0xff, 0xff, 0xff), .driver_info = RTL8852B}, + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xA85B, 0xff, 0xff, 0xff), .driver_info = RTL8852B}, +#endif /* CONFIG_RTL8852B */ {} /* Terminating entry */ }; @@ -333,18 +180,17 @@ static struct specific_device_id specific_device_id_tbl[] = { struct rtw_usb_drv { struct usb_driver usbdrv; int drv_registered; - u8 hw_type; }; struct rtw_usb_drv usb_drv = { .usbdrv.name = (char *)DRV_NAME, - .usbdrv.probe = rtw_drv_init, + .usbdrv.probe = rtw_dev_probe, .usbdrv.disconnect = rtw_dev_remove, .usbdrv.id_table = rtw_usb_id_tbl, - .usbdrv.suspend = rtw_suspend, - .usbdrv.resume = rtw_resume, + .usbdrv.suspend = rtw_dev_suspend, + .usbdrv.resume = rtw_dev_resume, #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) - .usbdrv.reset_resume = rtw_resume, + .usbdrv.reset_resume = rtw_dev_resume, #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) @@ -397,21 +243,22 @@ static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) { u8 rst = _SUCCESS; + PUSB_DATA pusb_data = dvobj_to_usb(dvobj); #ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _rtw_mutex_init(&dvobj->usb_vendor_req_mutex); + _rtw_mutex_init(&pusb_data->usb_vendor_req_mutex); #endif #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC - dvobj->usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE); - if (dvobj->usb_alloc_vendor_req_buf == NULL) { + pusb_data->usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE); + if (pusb_data->usb_alloc_vendor_req_buf == NULL) { RTW_INFO("alloc usb_vendor_req_buf failed... /n"); rst = _FAIL; goto exit; } - dvobj->usb_vendor_req_buf = - (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf), ALIGNMENT_UNIT); + pusb_data->usb_vendor_req_buf = + (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pusb_data->usb_alloc_vendor_req_buf), ALIGNMENT_UNIT); exit: #endif @@ -422,133 +269,84 @@ static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) { u8 rst = _SUCCESS; + PUSB_DATA pusb_data = dvobj_to_usb(dvobj); #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC - if (dvobj->usb_vendor_req_buf) - rtw_mfree(dvobj->usb_alloc_vendor_req_buf, MAX_USB_IO_CTL_SIZE); + if (pusb_data->usb_vendor_req_buf) + rtw_mfree(pusb_data->usb_alloc_vendor_req_buf, MAX_USB_IO_CTL_SIZE); #endif #ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _rtw_mutex_free(&dvobj->usb_vendor_req_mutex); + _rtw_mutex_free(&pusb_data->usb_vendor_req_mutex); #endif return rst; } -static void rtw_decide_chip_type_by_usb_info(struct dvobj_priv *pdvobjpriv, const struct usb_device_id *pdid) -{ - pdvobjpriv->chip_type = pdid->driver_info; - -#ifdef CONFIG_RTL8188E - if (pdvobjpriv->chip_type == RTL8188E) - rtl8188eu_set_hw_type(pdvobjpriv); -#endif - -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - if (pdvobjpriv->chip_type == RTL8812 || pdvobjpriv->chip_type == RTL8821) - rtl8812au_set_hw_type(pdvobjpriv); -#endif - -#ifdef CONFIG_RTL8192E - if (pdvobjpriv->chip_type == RTL8192E) - rtl8192eu_set_hw_type(pdvobjpriv); -#endif - -#ifdef CONFIG_RTL8723B - if (pdvobjpriv->chip_type == RTL8723B) - rtl8723bu_set_hw_type(pdvobjpriv); -#endif -#ifdef CONFIG_RTL8814A - if (pdvobjpriv->chip_type == RTL8814A) - rtl8814au_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8814A */ - -#ifdef CONFIG_RTL8188F - if (pdvobjpriv->chip_type == RTL8188F) - rtl8188fu_set_hw_type(pdvobjpriv); -#endif +static unsigned int rtw_endpoint_max_bpi(struct usb_device *dev, + struct usb_host_endpoint *ep) +{ + u16 psize; + u16 mult = 1; + int max_size_1 = 0, max_size_2 = 0; -#ifdef CONFIG_RTL8188GTV - if (pdvobjpriv->chip_type == RTL8188GTV) - rtl8188gtvu_set_hw_type(pdvobjpriv); + switch (dev->speed) { + case USB_SPEED_SUPER: +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 20) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) ||\ + LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0)) + case USB_SPEED_SUPER_PLUS: + max_size_1 = le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); + max_size_2 = usb_endpoint_maxp(&ep->desc); #endif + break; + case USB_SPEED_HIGH: + psize = usb_endpoint_maxp(&ep->desc); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 71)) + mult = usb_endpoint_maxp_mult(&ep->desc); + max_size_1 = psize * mult; + #endif + max_size_2 = usb_endpoint_maxp(&ep->desc); + break; + case USB_SPEED_WIRELESS: + max_size_1 = max_size_2 = usb_endpoint_maxp(&ep->desc); + break; + default: + max_size_1 = max_size_2 = usb_endpoint_maxp(&ep->desc); + break; -#ifdef CONFIG_RTL8703B - if (pdvobjpriv->chip_type == RTL8703B) - rtl8703bu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8703B */ - -#ifdef CONFIG_RTL8822B - if (pdvobjpriv->chip_type == RTL8822B) - rtl8822bu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8822B */ - -#ifdef CONFIG_RTL8723D - if (pdvobjpriv->chip_type == RTL8723D) - rtl8723du_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8723D */ - -#ifdef CONFIG_RTL8821C - if (pdvobjpriv->chip_type == RTL8821C) - rtl8821cu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8821C */ - -#ifdef CONFIG_RTL8710B - if (pdvobjpriv->chip_type == RTL8710B) - rtl8710bu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8710B */ - -#ifdef CONFIG_RTL8192F - if (pdvobjpriv->chip_type == RTL8192F) - rtl8192fu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8192F */ - -#ifdef CONFIG_RTL8822C - if (pdvobjpriv->chip_type == RTL8822C) - rtl8822cu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8822C */ - -#ifdef CONFIG_RTL8814B - if (pdvobjpriv->chip_type == RTL8814B) - rtl8814bu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8814B */ - -#ifdef CONFIG_RTL8723F - if (pdvobjpriv->chip_type == RTL8723F) - rtl8723fu_set_hw_type(pdvobjpriv); -#endif /* CONFIG_RTL8723F */ + } + RTW_INFO("USB EP MAX_PKT_SZ:%d-%d\n",max_size_1, max_size_2); + return max_size_1; } -static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const struct usb_device_id *pdid) +static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, + const struct usb_device_id *pdid) { int i; int status = _FAIL; - struct dvobj_priv *pdvobjpriv; + struct dvobj_priv *dvobj; struct usb_device_descriptor *pdev_desc; - struct usb_host_config *phost_conf; - struct usb_config_descriptor *pconf_desc; - struct usb_host_interface *phost_iface; + struct usb_host_config *phost_conf; + struct usb_config_descriptor *pconf_desc; + struct usb_host_interface *phost_iface; struct usb_interface_descriptor *piface_desc; - struct usb_host_endpoint *phost_endp; + struct usb_host_endpoint *phost_endp; struct usb_endpoint_descriptor *pendp_desc; - struct usb_device *pusbd; - - + struct usb_device *pusbd; + PUSB_DATA pusb_data; - pdvobjpriv = devobj_init(); - if (pdvobjpriv == NULL) + dvobj = devobj_init(); + if (dvobj == NULL) goto exit; + pusb_data = dvobj_to_usb(dvobj); - pdvobjpriv->pusbintf = usb_intf ; - pusbd = pdvobjpriv->pusbdev = interface_to_usbdev(usb_intf); - usb_set_intfdata(usb_intf, pdvobjpriv); + pusb_data->pusbintf = usb_intf; + pusbd = pusb_data->pusbdev = interface_to_usbdev(usb_intf); + usb_set_intfdata(usb_intf, dvobj); - pdvobjpriv->RtNumInPipes = 0; - pdvobjpriv->RtNumOutPipes = 0; - - /* padapter->EepromAddressSize = 6; */ - /* pdvobjpriv->nr_endpoint = 6; */ + pusb_data->RtNumInPipes = 0; + pusb_data->RtNumOutPipes = 0; pdev_desc = &pusbd->descriptor; @@ -573,17 +371,43 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const s phost_conf = pusbd->actconfig; pconf_desc = &phost_conf->desc; - - /* RTW_INFO("\n***** num of altsetting = (%d) *****\n", pusb_interface->num_altsetting); */ +#if 0 + RTW_INFO("\n[USB] configuration_descriptor:\n"); + RTW_INFO("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces); + RTW_INFO("bLength=%x\n", pconf_desc->bLength); + RTW_INFO("bDescriptorType=%x\n", pconf_desc->bDescriptorType); + RTW_INFO("wTotalLength=%x\n", pconf_desc->wTotalLength); + RTW_INFO("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue); + RTW_INFO("iConfiguration=%x\n", pconf_desc->iConfiguration); + RTW_INFO("bmAttributes=%x\n", pconf_desc->bmAttributes); + RTW_INFO("bMaxPower=%x\n", pconf_desc->bMaxPower); +#endif phost_iface = &usb_intf->altsetting[0]; piface_desc = &phost_iface->desc; - - pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints; +#if 0 + RTW_INFO("\n[USB] usb_interface_descriptor:\n"); + RTW_INFO("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber); + RTW_INFO("bAlternateSetting=%x\n", piface_desc->bAlternateSetting); + RTW_INFO("bLength=%x\n", piface_desc->bLength); + RTW_INFO("bDescriptorType=%x\n", piface_desc->bDescriptorType); + RTW_INFO("bNumEndpoints=%x\n", piface_desc->bNumEndpoints); + RTW_INFO("bInterfaceClass=%x\n", piface_desc->bInterfaceClass); + RTW_INFO("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass); + RTW_INFO("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol); + RTW_INFO("iInterface=%x\n", piface_desc->iInterface); +#endif + + pusb_data->nr_endpoint = piface_desc->bNumEndpoints; + if (pusb_data->nr_endpoint > MAX_ENDPOINT_NUM) { + RTW_ERR("USB EP_Number : %d > RT DEF-MAX_EP_NUM :%d\n", + pusb_data->nr_endpoint, MAX_ENDPOINT_NUM); + rtw_warn_on(1); + } /* RTW_INFO("\ndump usb_endpoint_descriptor:\n"); */ - for (i = 0; i < pdvobjpriv->nr_endpoint; i++) { + for (i = 0; i < pusb_data->nr_endpoint; i++) { phost_endp = phost_iface->endpoint + i; if (phost_endp) { pendp_desc = &phost_endp->desc; @@ -600,86 +424,98 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const s if (RT_usb_endpoint_is_bulk_in(pendp_desc)) { RTW_INFO("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc)); - pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); - pdvobjpriv->RtNumInPipes++; + pusb_data->RtInPipe[pusb_data->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); + pusb_data->inpipe_type[pusb_data->RtNumInPipes] = REALTEK_USB_BULK_IN_EP_IDX; + pusb_data->RtNumInPipes++; + RTW_INFO("USB#%d bulkin size:%d", pusb_data->RtNumOutPipes, + rtw_endpoint_max_bpi(pusbd, phost_endp)); } else if (RT_usb_endpoint_is_int_in(pendp_desc)) { RTW_INFO("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(pendp_desc), pendp_desc->bInterval); - pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); - pdvobjpriv->RtNumInPipes++; + pusb_data->RtInPipe[pusb_data->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); + pusb_data->inpipe_type[pusb_data->RtNumInPipes] = REALTEK_USB_IN_INT_EP_IDX; + pusb_data->RtNumInPipes++; } else if (RT_usb_endpoint_is_bulk_out(pendp_desc)) { RTW_INFO("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(pendp_desc)); - pdvobjpriv->RtOutPipe[pdvobjpriv->RtNumOutPipes] = RT_usb_endpoint_num(pendp_desc); - pdvobjpriv->RtNumOutPipes++; + pusb_data->RtOutPipe[pusb_data->RtNumOutPipes] = RT_usb_endpoint_num(pendp_desc); + RTW_INFO("USB#%d bulkout size:%d", pusb_data->RtNumOutPipes, + rtw_endpoint_max_bpi(pusbd, phost_endp)); + pusb_data->RtNumOutPipes++; } - pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc); + /*pusb_data->ep_num[i] = RT_usb_endpoint_num(pendp_desc);*/ } } - RTW_INFO("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); + RTW_INFO("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", + pusb_data->nr_endpoint, pusb_data->RtNumInPipes, pusb_data->RtNumOutPipes); switch (pusbd->speed) { case USB_SPEED_LOW: - RTW_INFO("USB_SPEED_LOW\n"); - pdvobjpriv->usb_speed = RTW_USB_SPEED_1_1; - break; case USB_SPEED_FULL: RTW_INFO("USB_SPEED_FULL\n"); - pdvobjpriv->usb_speed = RTW_USB_SPEED_1_1; + pusb_data->usb_speed = RTW_USB_SPEED_FULL;/*U2- 1.1 - 1.5MBs*/ + pusb_data->usb_bulkout_size = USB_FULL_SPEED_BULK_SIZE; break; case USB_SPEED_HIGH: RTW_INFO("USB_SPEED_HIGH\n"); - pdvobjpriv->usb_speed = RTW_USB_SPEED_2; + pusb_data->usb_speed = RTW_USB_SPEED_HIGH;/*U2- 2.1 - 60MBs*/ + pusb_data->usb_bulkout_size = USB_HIGH_SPEED_BULK_SIZE; break; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) case USB_SPEED_SUPER: RTW_INFO("USB_SPEED_SUPER\n"); - pdvobjpriv->usb_speed = RTW_USB_SPEED_3; + pusb_data->usb_speed = RTW_USB_SPEED_SUPER;/*U3- 3.0 - 640MBs*/ + pusb_data->usb_bulkout_size = USB_SUPER_SPEED_BULK_SIZE; break; +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 20) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) ||\ + LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0)) + case USB_SPEED_SUPER_PLUS: + RTW_INFO("USB_SPEED_SUPER_PLUS\n"); + pusb_data->usb_speed = RTW_USB_SPEED_SUPER_10G;/*U3- 3.1 - 1280MBs*/ + pusb_data->usb_bulkout_size = USB_SUPER_SPEED_BULK_SIZE; + break; +#endif #endif default: - RTW_INFO("USB_SPEED_UNKNOWN(%x)\n", pusbd->speed); - pdvobjpriv->usb_speed = RTW_USB_SPEED_UNKNOWN; + RTW_INFO("USB_SPEED_UNKNOWN(%d)\n", pusbd->speed); + pusb_data->usb_speed = RTW_USB_SPEED_UNKNOWN; break; } - if (pdvobjpriv->usb_speed == RTW_USB_SPEED_UNKNOWN) { + if (pusb_data->usb_speed == RTW_USB_SPEED_UNKNOWN) { RTW_INFO("UNKNOWN USB SPEED MODE, ERROR !!!\n"); goto free_dvobj; } - if (rtw_init_intf_priv(pdvobjpriv) == _FAIL) { + if (rtw_init_intf_priv(dvobj) == _FAIL) { goto free_dvobj; } - /*step 1-1., decide the chip_type via driver_info*/ - pdvobjpriv->interface_type = RTW_USB; - rtw_decide_chip_type_by_usb_info(pdvobjpriv, pdid); + /*step 1-1., get chip_id via driver_info*/ + dvobj->interface_type = RTW_HCI_USB; + dvobj->ic_id = pdid->driver_info; + dvobj->intf_ops = &usb_ops; /* .3 misc */ - _rtw_init_sema(&(pdvobjpriv->usb_suspend_sema), 0); - rtw_reset_continual_io_error(pdvobjpriv); + rtw_reset_continual_io_error(dvobj); usb_get_dev(pusbd); status = _SUCCESS; free_dvobj: - if (status != _SUCCESS && pdvobjpriv) { + if (status != _SUCCESS && dvobj) { usb_set_intfdata(usb_intf, NULL); - - devobj_deinit(pdvobjpriv); - - pdvobjpriv = NULL; + devobj_deinit(dvobj); + dvobj = NULL; } exit: - return pdvobjpriv; + return dvobj; } static void usb_dvobj_deinit(struct usb_interface *usb_intf) { struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf); - usb_set_intfdata(usb_intf, NULL); if (dvobj) { rtw_deinit_intf_priv(dvobj); @@ -691,154 +527,24 @@ static void usb_dvobj_deinit(struct usb_interface *usb_intf) } -static int usb_reprobe_switch_usb_mode(PADAPTER Adapter) +static int usb_reprobe_switch_usb_mode(_adapter *adapter) { - struct registry_priv *registry_par = &Adapter->registrypriv; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct registry_priv *registry_par = &adapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PUSB_DATA pusb_data = dvobj_to_usb(dvobj); u8 ret = _FALSE; - /* efuse not allow driver to switch usb mode */ - if (pHalData->EEPROMUsbSwitch == _FALSE) - goto exit; - /* registry not allow driver to switch usb mode */ if (registry_par->switch_usb_mode == 0) goto exit; - - rtw_hal_set_hwreg(Adapter, HW_VAR_USB_MODE, &ret); - + else if (registry_par->switch_usb_mode == 1 && pusb_data->usb_speed < RTW_USB_SPEED_SUPER) + ret = rtw_phl_cmd_force_usb_switch(dvobj->phl, RTW_USB_SPEED_SUPER, HW_BAND_0, PHL_CMD_DIRECTLY, 0); + else if (registry_par->switch_usb_mode == 2 && pusb_data->usb_speed >= RTW_USB_SPEED_SUPER) + ret = rtw_phl_cmd_force_usb_switch(dvobj->phl, RTW_USB_SPEED_HIGH, HW_BAND_0, PHL_CMD_DIRECTLY, 0); exit: return ret; } -u8 rtw_set_hal_ops(_adapter *padapter) -{ - /* alloc memory for HAL DATA */ - if (rtw_hal_data_init(padapter) == _FAIL) - return _FAIL; - -#ifdef CONFIG_RTL8188E - if (rtw_get_chip_type(padapter) == RTL8188E) - rtl8188eu_set_hal_ops(padapter); -#endif - -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - if (rtw_get_chip_type(padapter) == RTL8812 || rtw_get_chip_type(padapter) == RTL8821) - rtl8812au_set_hal_ops(padapter); -#endif - -#ifdef CONFIG_RTL8192E - if (rtw_get_chip_type(padapter) == RTL8192E) - rtl8192eu_set_hal_ops(padapter); -#endif -#ifdef CONFIG_RTL8723B - if (rtw_get_chip_type(padapter) == RTL8723B) - rtl8723bu_set_hal_ops(padapter); -#endif -#ifdef CONFIG_RTL8814A - if (rtw_get_chip_type(padapter) == RTL8814A) - rtl8814au_set_hal_ops(padapter); -#endif /* CONFIG_RTL8814A */ - -#ifdef CONFIG_RTL8188F - if (rtw_get_chip_type(padapter) == RTL8188F) - rtl8188fu_set_hal_ops(padapter); -#endif - -#ifdef CONFIG_RTL8188GTV - if (rtw_get_chip_type(padapter) == RTL8188GTV) - rtl8188gtvu_set_hal_ops(padapter); -#endif - -#ifdef CONFIG_RTL8703B - if (rtw_get_chip_type(padapter) == RTL8703B) - rtl8703bu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8703B */ - -#ifdef CONFIG_RTL8822B - if (rtw_get_chip_type(padapter) == RTL8822B) - rtl8822bu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8822B */ - -#ifdef CONFIG_RTL8723D - if (rtw_get_chip_type(padapter) == RTL8723D) - rtl8723du_set_hal_ops(padapter); -#endif /* CONFIG_RTL8723D */ - - -#ifdef CONFIG_RTL8821C - if (rtw_get_chip_type(padapter) == RTL8821C) { - if (rtl8821cu_set_hal_ops(padapter) == _FAIL) - return _FAIL; - } -#endif - -#ifdef CONFIG_RTL8710B - if (rtw_get_chip_type(padapter) == RTL8710B) - rtl8710bu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8710B */ - - -#ifdef CONFIG_RTL8192F - if (rtw_get_chip_type(padapter) == RTL8192F) - rtl8192fu_set_hal_ops(padapter); -#endif - -#ifdef CONFIG_RTL8822C - if (rtw_get_chip_type(padapter) == RTL8822C) - rtl8822cu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8822C */ - -#ifdef CONFIG_RTL8814B - if (rtw_get_chip_type(padapter) == RTL8814B) - rtl8814bu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8814B */ - -#ifdef CONFIG_RTL8723F - if (rtw_get_chip_type(padapter) == RTL8723F) - rtl8723fu_set_hal_ops(padapter); -#endif /* CONFIG_RTL8723F */ - - if (_FAIL == rtw_hal_ops_check(padapter)) - return _FAIL; - - if (hal_spec_init(padapter) == _FAIL) - return _FAIL; - - return _SUCCESS; -} - -static void usb_intf_start(_adapter *padapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); - - rtw_hal_inirp_init(padapter); - hal->usb_intf_start = _TRUE; - - -} - -static void usb_intf_stop(_adapter *padapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); - - /* disabel_hw_interrupt */ - if (!rtw_is_surprise_removed(padapter)) { - /* device still exists, so driver can do i/o operation */ - /* TODO: */ - } - - /* cancel in irp */ - rtw_hal_inirp_deinit(padapter); - - /* cancel out irp */ - rtw_write_port_cancel(padapter); - - /* todo:cancel other irps */ - - hal->usb_intf_start = _FALSE; - -} static void process_spec_devid(const struct usb_device_id *pdid) { @@ -854,6 +560,7 @@ static void process_spec_devid(const struct usb_device_id *pdid) #ifdef CONFIG_80211N_HT if ((pdid->idVendor == vid) && (pdid->idProduct == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) { + /*GEORGIA_TODO_FIXIT_MULTI_IC*/ rtw_ht_enable = 0; rtw_bw_mode = 0; rtw_ampdu_enable = 0; @@ -873,120 +580,12 @@ static void process_spec_devid(const struct usb_device_id *pdid) } } -#ifdef SUPPORT_HW_RFOFF_DETECTED -int rtw_hw_suspend(_adapter *padapter) -{ - struct pwrctrl_priv *pwrpriv; - struct usb_interface *pusb_intf; - struct net_device *pnetdev; - - if (NULL == padapter) - goto error_exit; - - if ((_FALSE == padapter->bup) || RTW_CANNOT_RUN(padapter)) { - RTW_INFO("padapter->bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n" - , padapter->bup - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); - goto error_exit; - } - - pwrpriv = adapter_to_pwrctl(padapter); - pusb_intf = adapter_to_dvobj(padapter)->pusbintf; - pnetdev = padapter->pnetdev; - - LeaveAllPowerSaveMode(padapter); - - RTW_INFO("==> rtw_hw_suspend\n"); - _enter_pwrlock(&pwrpriv->lock); - pwrpriv->bips_processing = _TRUE; - /* padapter->net_closed = _TRUE; */ - /* s1. */ - if (pnetdev) { - rtw_netif_carrier_off(pnetdev); - rtw_netif_stop_queue(pnetdev); - } - - /* s2. */ - rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); - - /* s2-2. indicate disconnect to os */ - /* rtw_indicate_disconnect(padapter); */ - { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { - _clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE); - rtw_led_control(padapter, LED_CTL_NO_LINK); - - rtw_os_indicate_disconnect(padapter, 0, _FALSE); - -#ifdef CONFIG_LPS - /* donnot enqueue cmd */ - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, RTW_CMDF_DIRECTLY); -#endif - } - } - /* s2-3. */ - rtw_free_assoc_resources(padapter, _TRUE); - - /* s2-4. */ - rtw_free_network_queue(padapter, _TRUE); -#ifdef CONFIG_IPS - rtw_ips_dev_unload(padapter); -#endif - pwrpriv->rf_pwrstate = rf_off; - pwrpriv->bips_processing = _FALSE; - _exit_pwrlock(&pwrpriv->lock); - - return 0; - -error_exit: - RTW_INFO("%s, failed\n", __FUNCTION__); - return -1; - -} - -int rtw_hw_resume(_adapter *padapter) -{ - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf; - struct net_device *pnetdev = padapter->pnetdev; - - RTW_INFO("==> rtw_hw_resume\n"); - _enter_pwrlock(&pwrpriv->lock); - pwrpriv->bips_processing = _TRUE; - rtw_reset_drv_sw(padapter); - - if (pm_netdev_open(pnetdev, _FALSE) != 0) { - _exit_pwrlock(&pwrpriv->lock); - goto error_exit; - } - rtw_netif_device_attach(pnetdev); - rtw_netif_carrier_on(pnetdev); - - rtw_netif_wake_queue(pnetdev); - - pwrpriv->bkeepfwalive = _FALSE; - pwrpriv->brfoffbyhw = _FALSE; - - pwrpriv->rf_pwrstate = rf_on; - pwrpriv->bips_processing = _FALSE; - _exit_pwrlock(&pwrpriv->lock); - - - return 0; -error_exit: - RTW_INFO("%s, Open net dev failed\n", __FUNCTION__); - return -1; -} -#endif - -static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) +static int rtw_dev_suspend(struct usb_interface *pusb_intf, pm_message_t message) { struct dvobj_priv *dvobj; struct pwrctrl_priv *pwrpriv; struct debug_priv *pdbgpriv; - PADAPTER padapter; + _adapter *padapter; int ret = 0; @@ -1007,7 +606,7 @@ static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) return ret; } -int rtw_resume_process(_adapter *padapter) +static int rtw_resume_process(_adapter *padapter) { int ret; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); @@ -1027,20 +626,20 @@ int rtw_resume_process(_adapter *padapter) * But they will not be clear in intf_start during wow resume flow. * It should move to os_intf in the feature. */ - RTW_ENABLE_FUNC(padapter, DF_RX_BIT); - RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + RTW_ENABLE_FUNC(pdvobj, DF_RX_BIT); + RTW_ENABLE_FUNC(pdvobj, DF_TX_BIT); ret = rtw_resume_common(padapter); return ret; } -static int rtw_resume(struct usb_interface *pusb_intf) +static int rtw_dev_resume(struct usb_interface *pusb_intf) { struct dvobj_priv *dvobj; struct pwrctrl_priv *pwrpriv; struct debug_priv *pdbgpriv; - PADAPTER padapter; + _adapter *padapter; struct mlme_ext_priv *pmlmeext; int ret = 0; @@ -1081,10 +680,6 @@ static int rtw_resume(struct usb_interface *pusb_intf) } -#ifdef CONFIG_PLATFORM_RTD2880B -extern void rtd2885_wlan_netlink_sendMsg(char *action_string, char *name); -#endif - /* * drv_init() - a device potentially for us * @@ -1096,18 +691,17 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, { _adapter *padapter = NULL; int status = _FAIL; + u8 hw_mac_addr[ETH_ALEN] = {0}; padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter)); if (padapter == NULL) goto exit; - if (loadparam(padapter) != _SUCCESS) - goto free_adapter; - padapter->dvobj = dvobj; - - rtw_set_drv_stopped(padapter);/*init*/ + /*registry_priv*/ + if (rtw_load_registry(padapter) != _SUCCESS) + goto free_adapter; dvobj->padapters[dvobj->iface_nums++] = padapter; padapter->iface_id = IFACE_ID0; @@ -1115,52 +709,21 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, /* set adapter_type/iface type for primary padapter */ padapter->isprimary = _TRUE; padapter->adapter_type = PRIMARY_ADAPTER; -#ifdef CONFIG_MI_WITH_MBSSID_CAM/*Configure all IFACE to PORT0-MBSSID*/ - padapter->hw_port = HW_PORT0; -#else - padapter->hw_port = HW_PORT0; -#endif - - /* step init_io_priv */ - if (rtw_init_io_priv(padapter, usb_set_intf_ops) == _FAIL) - goto free_adapter; - - /* step 2. hook HalFunc, allocate HalData */ - if (rtw_set_hal_ops(padapter) == _FAIL) - goto free_hal_data; - - - padapter->intf_start = &usb_intf_start; - padapter->intf_stop = &usb_intf_stop; - - /* step read_chip_version */ - rtw_hal_read_chip_version(padapter); - - /* step usb endpoint mapping */ - rtw_hal_chip_configure(padapter); - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_Initialize(padapter); -#endif - rtw_btcoex_wifionly_initialize(padapter); - - /* step read efuse/eeprom data and get mac_addr */ - if (rtw_hal_read_chip_info(padapter) == _FAIL) - goto free_hal_data; /* step 5. */ if (rtw_init_drv_sw(padapter) == _FAIL) { - goto free_hal_data; + goto free_adapter; } #ifdef CONFIG_PM #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) if (dvobj_to_pwrctl(dvobj)->bSupportRemoteWakeup) { - dvobj->pusbdev->do_remote_wakeup = 1; + dvobj_to_usb(dvobj)->pusbdev->do_remote_wakeup = 1; pusb_intf->needs_remote_wakeup = 1; device_init_wakeup(&pusb_intf->dev, 1); RTW_INFO("pwrctrlpriv.bSupportRemoteWakeup~~~~~~\n"); - RTW_INFO("pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n", device_may_wakeup(&pusb_intf->dev)); + RTW_INFO("pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n", + device_may_wakeup(&pusb_intf->dev)); } #endif #endif @@ -1169,36 +732,26 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, if (usb_autopm_get_interface(pusb_intf) < 0) RTW_INFO("can't get autopm:\n"); #endif -#ifdef CONFIG_BT_COEXIST +#ifdef CONFIG_BTC dvobj_to_pwrctl(dvobj)->autopm_cnt = 1; #endif + /* get mac addr */ + rtw_hw_get_mac_addr(dvobj, hw_mac_addr); /* set mac addr */ - rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter)); -#endif + rtw_macaddr_cfg(adapter_mac_addr(padapter), hw_mac_addr); -#ifdef CONFIG_P2P - rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); -#endif /* CONFIG_P2P */ - RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%d\n" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , padapter->bup - , rtw_get_hw_init_completed(padapter) + RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, netif_up:%d, hw_init_completed:%d\n" + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False" + , padapter->netif_up + , rtw_hw_get_init_completed(dvobj) ); status = _SUCCESS; -free_hal_data: - if (status != _SUCCESS && padapter->HalData) - rtw_hal_free_data(padapter); free_adapter: if (status != _SUCCESS && padapter) { - #ifdef RTW_HALMAC - rtw_halmac_deinit_adapter(dvobj); - #endif rtw_vmfree((u8 *)padapter, sizeof(*padapter)); padapter = NULL; } @@ -1208,45 +761,22 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, static void rtw_usb_primary_adapter_deinit(_adapter *padapter) { -#if defined(CONFIG_WOWLAN) || defined(CONFIG_BT_COEXIST) - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); -#endif - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); - if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) - rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); - -#ifdef CONFIG_AP_MODE - if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { - free_mlme_ap_info(padapter); - #ifdef CONFIG_HOSTAPD_MLME - hostapd_mode_unload(padapter); - #endif - } -#endif - - /*rtw_cancel_all_timer(if1);*/ - -#ifdef CONFIG_WOWLAN - pwrctl->wowlan_mode = _FALSE; -#endif /* CONFIG_WOWLAN */ - - rtw_dev_unload(padapter); +#ifdef CONFIG_BTC + if (1 == adapter_to_pwrctl(padapter)->autopm_cnt) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PUSB_DATA usb_data = dvobj_to_usb(dvobj); - RTW_INFO("+r871xu_dev_remove, hw_init_completed=%d\n", rtw_get_hw_init_completed(padapter)); - -#ifdef CONFIG_BT_COEXIST - if (1 == pwrctl->autopm_cnt) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) - usb_autopm_put_interface(adapter_to_dvobj(padapter)->pusbintf); + usb_autopm_put_interface(usb_data->pusbintf); #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)) - usb_autopm_enable(adapter_to_dvobj(padapter)->pusbintf); + usb_autopm_enable(usb_data->pusbintf); #else - usb_autosuspend_device(adapter_to_dvobj(padapter)->pusbdev, 1); + usb_autosuspend_device(usb_data->pusbdev, 1); #endif - pwrctl->autopm_cnt--; + adapter_to_pwrctl(padapter)->autopm_cnt--; } #endif @@ -1255,29 +785,38 @@ static void rtw_usb_primary_adapter_deinit(_adapter *padapter) /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ rtw_os_ndev_free(padapter); -#ifdef RTW_HALMAC - rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter)); -#endif /* RTW_HALMAC */ - rtw_vmfree((u8 *)padapter, sizeof(_adapter)); -#ifdef CONFIG_PLATFORM_RTD2880B - RTW_INFO("wlan link down\n"); - rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); -#endif +} + +static void rtw_usb_drop_all_phl_rx_pkt(struct dvobj_priv *dvobj) +{ + u16 rx_pkt_num = 0; + struct rtw_recv_pkt *rx_req = NULL; + + rx_pkt_num = rtw_phl_query_new_rx_num(GET_PHL_INFO(dvobj)); + if (rx_pkt_num) { + RTW_INFO("%s, rx_pkt not empty !!(%d)\n", __func__, rx_pkt_num); + + while (rx_pkt_num--) { + rx_req = rtw_phl_query_rx_pkt(GET_PHL_INFO(dvobj)); + if (rx_req) { + struct sk_buff *skb = rx_req->os_priv; + + rtw_phl_return_rxbuf(GET_PHL_INFO(dvobj), (u8 *)rx_req); + rtw_skb_free(skb); + } + } + } } -static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) +static int rtw_dev_probe(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) { _adapter *padapter = NULL; - int status = _FAIL; struct dvobj_priv *dvobj; -#ifdef CONFIG_CONCURRENT_MODE - int i; -#endif - /* RTW_INFO("+rtw_drv_init\n"); */ + RTW_INFO("+%s\n", __func__); /* step 0. */ process_spec_devid(pdid); @@ -1285,29 +824,40 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device /* Initialize dvobj_priv */ dvobj = usb_dvobj_init(pusb_intf, pdid); if (dvobj == NULL) { + RTW_ERR("usb_dvobj_init Failed!\n"); goto exit; } + if (devobj_trx_resource_init(dvobj) == _FAIL) + goto free_dvobj; + + /*init hw - register and get chip-info */ + if (rtw_hw_init(dvobj) == _FAIL) { + RTW_ERR("rtw_hw_init Failed!\n"); + goto free_trx_reso; + } + padapter = rtw_usb_primary_adapter_init(dvobj, pusb_intf); if (padapter == NULL) { - RTW_INFO("rtw_usb_primary_adapter_init Failed!\n"); - goto free_dvobj; + RTW_ERR("rtw_usb_primary_adapter_init Failed!\n"); + goto free_hw; } - if (usb_reprobe_switch_usb_mode(padapter) == _TRUE) + if (usb_reprobe_switch_usb_mode(padapter) == _TRUE) { + RTW_ERR("usb_reprobe_switch_usb_mode Failed!\n"); goto free_if_prim; + } #ifdef CONFIG_CONCURRENT_MODE - if (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1)) - padapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1); + if (rtw_drv_add_vir_ifaces(dvobj) == _FAIL) + goto free_if_vir; +#endif - for (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) { - if (rtw_drv_add_vir_if(padapter, usb_set_intf_ops) == NULL) { - RTW_INFO("rtw_drv_add_iface failed! (%d)\n", i); - goto free_if_vir; - } + /*init data of dvobj from registary and ic spec*/ + if (devobj_data_init(dvobj) == _FAIL) { + RTW_ERR("devobj_data_init Failed!\n"); + goto free_devobj_data; } -#endif #ifdef CONFIG_GLOBAL_UI_PID if (ui_pid[1] != 0) { @@ -1317,43 +867,39 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device #endif /* dev_alloc_name && register_netdev */ - if (rtw_os_ndevs_init(dvobj) != _SUCCESS) - goto free_if_vir; + if (rtw_os_ndevs_init(dvobj) != _SUCCESS) { + RTW_ERR("rtw_os_ndevs_init Failed!\n"); + goto free_devobj_data; + } #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_init(padapter); #endif + RTW_INFO("-%s success\n", __func__); + return 0; /*_SUCCESS*/ -#ifdef CONFIG_PLATFORM_RTD2880B - RTW_INFO("wlan link up\n"); - rtd2885_wlan_netlink_sendMsg("linkup", "8712"); -#endif - +free_devobj_data: + devobj_data_deinit(dvobj); - status = _SUCCESS; - -#if 0 /* not used now */ -os_ndevs_deinit: - if (status != _SUCCESS) - rtw_os_ndevs_deinit(dvobj); +#ifdef CONFIG_CONCURRENT_MODE +free_if_vir: + rtw_drv_stop_vir_ifaces(dvobj); + rtw_drv_free_vir_ifaces(dvobj); #endif -free_if_vir: - if (status != _SUCCESS) { - #ifdef CONFIG_CONCURRENT_MODE - rtw_drv_stop_vir_ifaces(dvobj); - rtw_drv_free_vir_ifaces(dvobj); - #endif - } free_if_prim: - if (status != _SUCCESS && padapter) + if (padapter) rtw_usb_primary_adapter_deinit(padapter); +free_hw: + rtw_hw_deinit(dvobj); + +free_trx_reso: + devobj_trx_resource_deinit(dvobj); free_dvobj: - if (status != _SUCCESS) - usb_dvobj_deinit(pusb_intf); + usb_dvobj_deinit(pusb_intf); exit: - return status == _SUCCESS ? 0 : -ENODEV; + return -ENODEV; } /* @@ -1368,7 +914,7 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) #endif _adapter *padapter = dvobj_get_primary_adapter(dvobj); - RTW_INFO("+rtw_dev_remove\n"); + RTW_INFO("+%s\n", __func__); dvobj->processing_dev_remove = _TRUE; @@ -1377,38 +923,36 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) if (usb_drv.drv_registered == _TRUE) { /* RTW_INFO("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); */ - rtw_set_surprise_removed(padapter); + dev_set_surprise_removed(dvobj); } - /*else - { - - rtw_set_hw_init_completed(padapter, _FALSE); - }*/ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) rtw_unregister_early_suspend(pwrctl); #endif - - if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) { +#if 0 /*GEORGIA_TODO_FIXIT*/ + if (GET_PHL_COM(dvobj)->fw_ready == _TRUE) { rtw_pm_set_ips(padapter, IPS_NONE); - rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + rtw_pm_set_lps(padapter, PM_PS_MODE_ACTIVE); LeaveAllPowerSaveMode(padapter); } - rtw_set_drv_stopped(padapter); /*for stop thread*/ +#endif + dev_set_drv_stopped(adapter_to_dvobj(padapter)); /*for stop thread*/ +#if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/ rtw_stop_cmd_thread(padapter); +#endif #ifdef CONFIG_CONCURRENT_MODE rtw_drv_stop_vir_ifaces(dvobj); #endif /* CONFIG_CONCURRENT_MODE */ -#ifdef CONFIG_BT_COEXIST -#ifdef CONFIG_BT_COEXIST_SOCKET_TRX - if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist) - rtw_btcoex_close_socket(padapter); -#endif - rtw_btcoex_HaltNotify(padapter); -#endif + rtw_drv_stop_prim_iface(padapter); + + if (rtw_hw_is_init_completed(dvobj)) + rtw_hw_stop(dvobj); + dev_set_surprise_removed(dvobj); + + rtw_usb_drop_all_phl_rx_pkt(dvobj); rtw_usb_primary_adapter_deinit(padapter); @@ -1416,10 +960,12 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) rtw_drv_free_vir_ifaces(dvobj); #endif /* CONFIG_CONCURRENT_MODE */ + rtw_hw_deinit(dvobj); + devobj_data_deinit(dvobj); + devobj_trx_resource_deinit(dvobj); usb_dvobj_deinit(pusb_intf); - RTW_INFO("-r871xu_dev_remove, done\n"); - + RTW_INFO("-%s done\n", __func__); return; } @@ -1451,9 +997,6 @@ static int __init rtw_drv_entry(void) rtw_suspend_lock_init(); rtw_drv_proc_init(); rtw_nlrtw_init(); -#ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_init(); -#endif rtw_ndev_notifier_register(); rtw_inetaddr_notifier_register(); @@ -1464,9 +1007,6 @@ static int __init rtw_drv_entry(void) rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_nlrtw_deinit(); -#ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_deinit(); -#endif rtw_ndev_notifier_unregister(); rtw_inetaddr_notifier_unregister(); goto exit; @@ -1490,9 +1030,6 @@ static void __exit rtw_drv_halt(void) rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_nlrtw_deinit(); -#ifdef CONFIG_PLATFORM_CMAP_INTFS - cmap_intfs_deinit(); -#endif rtw_ndev_notifier_unregister(); rtw_inetaddr_notifier_unregister(); diff --git a/os_dep/linux/usb_ops_linux.c b/os_dep/linux/usb_ops_linux.c index db178b8..90708e0 100644 --- a/os_dep/linux/usb_ops_linux.c +++ b/os_dep/linux/usb_ops_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,19 +15,11 @@ #define _USB_OPS_LINUX_C_ #include -#include #include -struct rtw_async_write_data { - u8 data[VENDOR_CMD_MAX_DATA_LEN]; - struct usb_ctrlrequest dr; -}; - -int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) +int usbctrl_vendorreq(struct dvobj_priv *pdvobjpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) { - _adapter *padapter = pintfhdl->padapter; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct usb_device *udev = pdvobjpriv->pusbdev; + struct usb_device *udev = dvobj_to_usb(pdvobjpriv)->pusbdev; unsigned int pipe; int status = 0; @@ -38,13 +30,6 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde u8 *pIo_buf; int vendorreq_times = 0; -#if (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) || defined(CONFIG_RTL8822C) -#define REG_ON_SEC 0x00 -#define REG_OFF_SEC 0x01 -#define REG_LOCAL_SEC 0x02 - u8 current_reg_sec = REG_LOCAL_SEC; -#endif - #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE u8 *tmp_buf; #else /* use stack memory */ @@ -55,7 +40,7 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde /* RTW_INFO("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); */ - if (RTW_CANNOT_IO(padapter)) { + if (RTW_CANNOT_IO(pdvobjpriv)) { status = -EPERM; goto exit; } @@ -67,13 +52,13 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde } #ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _enter_critical_mutex_lock(&pdvobjpriv->usb_vendor_req_mutex, NULL); + _rtw_mutex_lock(&dvobj_to_usb(pdvobjpriv)->usb_vendor_req_mutex); #endif /* Acquire IO memory for vendorreq */ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC - pIo_buf = pdvobjpriv->usb_vendor_req_buf; + pIo_buf = dvobj_to_usb(pdvobjpriv)->usb_vendor_req_buf; #else #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE tmp_buf = rtw_malloc((u32) len + ALIGNMENT_UNIT); @@ -118,33 +103,27 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde switch (len) { case 1: RTW_INFO("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" - , value, (requesttype == 0x01) ? "read" : "write" , len, status, *(u8 *)pdata, vendorreq_times); + , (index << 16 | value), (requesttype == 0x01) ? "read" : "write" , len, status, *(u8 *)pdata, vendorreq_times); break; case 2: RTW_INFO("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" - , value, (requesttype == 0x01) ? "read" : "write" , len, status, *(u16 *)pdata, vendorreq_times); + , (index << 16 | value), (requesttype == 0x01) ? "read" : "write" , len, status, *(u16 *)pdata, vendorreq_times); break; case 4: RTW_INFO("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" - , value, (requesttype == 0x01) ? "read" : "write" , len, status, *(u32 *)pdata, vendorreq_times); + , (index << 16 | value), (requesttype == 0x01) ? "read" : "write" , len, status, *(u32 *)pdata, vendorreq_times); break; default: RTW_INFO("reg 0x%x, usb %s %u fail, status:%d, vendorreq_times:%d\n" - , value, (requesttype == 0x01) ? "read" : "write" , len, status, vendorreq_times); + , (index << 16 | value), (requesttype == 0x01) ? "read" : "write" , len, status, vendorreq_times); break; - } if (status < 0) { if (status == (-ESHUTDOWN) || status == -ENODEV) - rtw_set_surprise_removed(padapter); + dev_set_surprise_removed(pdvobjpriv); else { - #ifdef DBG_CONFIG_ERROR_DETECT - { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL; - } - #endif + } } else { /* status != len && status >= 0 */ if (status > 0) { @@ -156,50 +135,17 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde } if (rtw_inc_and_chk_continual_io_error(pdvobjpriv) == _TRUE) { - rtw_set_surprise_removed(padapter); + dev_set_surprise_removed(pdvobjpriv); break; } } - /* firmware download is checksumed, don't retry */ - if ((value >= FW_START_ADDRESS) || status == len) + if (status == len) break; } -#if (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) || defined(CONFIG_RTL8822C) - if (value < 0xFE00) { - if (value <= 0xff) - current_reg_sec = REG_ON_SEC; - else if (0x1000 <= value && value <= 0x10ff) - current_reg_sec = REG_ON_SEC; - else - current_reg_sec = REG_OFF_SEC; - } else { - current_reg_sec = REG_LOCAL_SEC; - } - - if (current_reg_sec == REG_ON_SEC) { - unsigned int t_pipe = usb_sndctrlpipe(udev, 0);/* write_out */ - u8 t_reqtype = REALTEK_USB_VENQT_WRITE; - u8 t_len = 1; - u8 t_req = 0x05; - u16 t_reg = 0; - u16 t_index = 0; - - t_reg = 0x4e0; - - status = rtw_usb_control_msg(udev, t_pipe, t_req, t_reqtype, t_reg, t_index, pIo_buf, t_len, RTW_USB_CONTROL_MSG_TIMEOUT); - - if (status == t_len) - rtw_reset_continual_io_error(pdvobjpriv); - else - RTW_INFO("reg 0x%x, usb %s %u fail, status:%d\n", t_reg, "write" , t_len, status); - - } -#endif - /* release IO memory used by vendorreq */ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE rtw_mfree(tmp_buf, tmp_buflen); @@ -207,304 +153,149 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde release_mutex: #ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); + _rtw_mutex_unlock(&dvobj_to_usb(pdvobjpriv)->usb_vendor_req_mutex); #endif exit: return status; } -#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ -static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *regs) -{ - if (urb) { - if (urb->context) - rtw_mfree(urb->context, sizeof(struct rtw_async_write_data)); - usb_free_urb(urb); - } -} - -int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, - u16 value, u16 index, void *pdata, u16 len, u8 requesttype) -{ - int rc; - unsigned int pipe; - u8 reqtype; - struct usb_ctrlrequest *dr; - struct urb *urb; - struct rtw_async_write_data *buf; - if (requesttype == VENDOR_READ) { - pipe = usb_rcvctrlpipe(udev, 0);/* read_in */ - reqtype = REALTEK_USB_VENQT_READ; - } else { - pipe = usb_sndctrlpipe(udev, 0);/* write_out */ - reqtype = REALTEK_USB_VENQT_WRITE; - } +#if (KERNEL_VERSION(2, 5, 0) > LINUX_VERSION_CODE) ||\ + (KERNEL_VERSION(2, 6, 18) < LINUX_VERSION_CODE) +/*#define _usbctrl_vendorreq_async_callback(urb, regs)\*/ + /*_usbctrl_vendorreq_async_callback(urb)*/ +/*#define usb_bulkout_zero_complete(purb, regs)\*/ + /*usb_bulkout_zero_complete(purb)*/ +#define rtw_usb_write_port_complete(purb, regs)\ + rtw_usb_write_port_complete(purb) +#define rtw_usb_read_port_complete(purb, regs)\ + rtw_usb_read_port_complete(purb) +#define rtw_usb_read_interrupt_complete(purb, regs)\ + rtw_usb_read_interrupt_complete(purb) +#endif - buf = (struct rtl819x_async_write_data *)rtw_zmalloc(sizeof(*buf)); - if (!buf) { - rc = -ENOMEM; - goto exit; +static unsigned int bulkid2pipe(struct dvobj_priv *pdvobj, u32 addr, u8 bulk_out) +{ + unsigned int pipe = 0, ep_num = 0; + PUSB_DATA usb_data = dvobj_to_usb(pdvobj); + struct usb_device *usbd = usb_data->pusbdev; + + if (!bulk_out) { + if (usb_data->inpipe_type[addr] == REALTEK_USB_BULK_IN_EP_IDX) + pipe = usb_rcvbulkpipe(usbd, usb_data->RtInPipe[addr]); + else if (usb_data->inpipe_type[addr] == REALTEK_USB_IN_INT_EP_IDX) + pipe = usb_rcvintpipe(usbd, usb_data->RtInPipe[addr]); + } else if (addr < MAX_BULKOUT_NUM) { + ep_num = usb_data->RtOutPipe[addr]; + pipe = usb_sndbulkpipe(usbd, ep_num); } + return pipe; +} - urb = usb_alloc_urb(0, GFP_ATOMIC); - if (!urb) { - rtw_mfree((u8 *)buf, sizeof(*buf)); - rc = -ENOMEM; - goto exit; +int rtw_os_urb_resource_alloc(struct data_urb *dataurb) +{ + dataurb->urb= usb_alloc_urb(0, GFP_KERNEL); + + if (dataurb->urb == NULL) { + rtw_msleep_os(10); + dataurb->urb = usb_alloc_urb(0, GFP_KERNEL); + if (dataurb->urb == NULL) { + RTW_ERR("(dataurb->urb == NULL"); + rtw_warn_on(1); + return _FAIL; + } } + return _SUCCESS; +} - dr = &buf->dr; - - dr->bRequestType = reqtype; - dr->bRequest = request; - dr->wValue = cpu_to_le16(value); - dr->wIndex = cpu_to_le16(index); - dr->wLength = cpu_to_le16(len); - - _rtw_memcpy(buf, pdata, len); - - usb_fill_control_urb(urb, udev, pipe, (unsigned char *)dr, buf, len, - _usbctrl_vendorreq_async_callback, buf); - - rc = usb_submit_urb(urb, GFP_ATOMIC); - if (rc < 0) { - rtw_mfree((u8 *)buf, sizeof(*buf)); - usb_free_urb(urb); +void rtw_os_urb_resource_free(struct data_urb *dataurb) +{ + if (dataurb->urb) { + usb_free_urb(dataurb->urb); + dataurb->urb = NULL; } - -exit: - return rc; } - -#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ - -unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr) +struct data_urb *rtw_alloc_dataurb(struct trx_urb_buf_q *urb_q) { - unsigned int pipe = 0, ep_num = 0; - struct usb_device *pusbd = pdvobj->pusbdev; + struct data_urb *urb = NULL; + _list *urb_list, *urb_head; + _queue *free_urb_q = &urb_q->free_urb_buf_queue; + unsigned long sp_flags; - if (addr == RECV_BULK_IN_ADDR) - pipe = usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe[0]); + /* RTW_INFO("+rtw_alloc_litexmitbuf\n"); */ - else if (addr == RECV_INT_IN_ADDR) - pipe = usb_rcvintpipe(pusbd, pdvobj->RtInPipe[1]); - -#ifdef RTW_HALMAC - /* halmac already translate queue id to bulk out id (addr 0~3) */ - /* 8814BU bulk out id range is 0~6 */ - else if (addr < MAX_BULKOUT_NUM) { - ep_num = pdvobj->RtOutPipe[addr]; - pipe = usb_sndbulkpipe(pusbd, ep_num); - } -#else - else if (addr < HW_QUEUE_ENTRY) { - ep_num = pdvobj->Queue2Pipe[addr]; - pipe = usb_sndbulkpipe(pusbd, ep_num); - } -#endif + _rtw_spinlock_irq(&free_urb_q->lock, &sp_flags); + if (_rtw_queue_empty(free_urb_q) == _TRUE) + urb = NULL; + else { - return pipe; -} + urb_head = get_list_head(free_urb_q); -struct zero_bulkout_context { - void *pbuf; - void *purb; - void *pirp; - void *padapter; -}; -#if 0 -static void usb_bulkout_zero_complete(struct urb *purb, struct pt_regs *regs) -{ - struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)purb->context; + urb_list = get_next(urb_head); - /* RTW_INFO("+usb_bulkout_zero_complete\n"); */ + urb = LIST_CONTAINOR(urb_list, + struct data_urb, list); - if (pcontext) { - if (pcontext->pbuf) - rtw_mfree(pcontext->pbuf, sizeof(int)); + rtw_list_delete(&(urb->list)); + } - if (pcontext->purb && (pcontext->purb == purb)) - usb_free_urb(pcontext->purb); + if (urb != NULL) + urb_q->free_urb_buf_cnt--; - rtw_mfree((u8 *)pcontext, sizeof(struct zero_bulkout_context)); - } + _rtw_spinunlock_irq(&free_urb_q->lock, &sp_flags); + return urb; } -static u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) +s32 rtw_free_dataurb(struct trx_urb_buf_q *urb_q, + struct data_urb *urb) { - int pipe, status, len; - u32 ret; - unsigned char *pbuf; - struct zero_bulkout_context *pcontext; - PURB purb = NULL; - _adapter *padapter = (_adapter *)pintfhdl->padapter; - struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); - struct usb_device *pusbd = pdvobj->pusbdev; - - /* RTW_INFO("%s\n", __func__); */ + _queue *free_urb_q = &urb_q->free_urb_buf_queue; + unsigned long sp_flags; + /* RTW_INFO("+rtw_free_xmiturb\n"); */ - if (RTW_CANNOT_TX(padapter)) + if (urb_q == NULL) return _FAIL; - - pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context)); - if (pcontext == NULL) + if (urb == NULL) return _FAIL; - pbuf = (unsigned char *)rtw_zmalloc(sizeof(int)); - purb = usb_alloc_urb(0, GFP_ATOMIC); + _rtw_spinlock_irq(&free_urb_q->lock, &sp_flags); - /* translate DMA FIFO addr to pipehandle */ - pipe = ffaddr2pipehdl(pdvobj, addr); + rtw_list_delete(&urb->list); - len = 0; - pcontext->pbuf = pbuf; - pcontext->purb = purb; - pcontext->pirp = NULL; - pcontext->padapter = padapter; + rtw_list_insert_tail(&(urb->list), + get_list_head(free_urb_q)); + urb_q->free_urb_buf_cnt++; - /* translate DMA FIFO addr to pipehandle */ - /* pipe = ffaddr2pipehdl(pdvobj, addr); */ - - usb_fill_bulk_urb(purb, pusbd, pipe, - pbuf, - len, - usb_bulkout_zero_complete, - pcontext);/* context is pcontext */ - - status = usb_submit_urb(purb, GFP_ATOMIC); - - if (!status) - ret = _SUCCESS; - else - ret = _FAIL; - + _rtw_spinunlock_irq(&free_urb_q->lock, &sp_flags); return _SUCCESS; - -} -#endif -void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) -{ - -} - -void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) -{ - -} - - -void usb_read_port_cancel(struct intf_hdl *pintfhdl) -{ - int i; - struct recv_buf *precvbuf; - _adapter *padapter = pintfhdl->padapter; - struct registry_priv *regsty = adapter_to_regsty(padapter); - precvbuf = (struct recv_buf *)padapter->recvpriv.precv_buf; - - RTW_INFO("%s\n", __func__); - - for (i = 0; i < regsty->recvbuf_nr ; i++) { - - if (precvbuf->purb) { - /* RTW_INFO("usb_read_port_cancel : usb_kill_urb\n"); */ - usb_kill_urb(precvbuf->purb); - } - precvbuf++; - } - -#ifdef CONFIG_USB_INTERRUPT_IN_PIPE - usb_kill_urb(padapter->recvpriv.int_in_urb); -#endif } -static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) +static void rtw_usb_write_port_complete(struct urb *purb, struct pt_regs *regs) { - _irqL irqL; - struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context; - /* struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; */ - /* _adapter *padapter = pxmitframe->padapter; */ - _adapter *padapter = pxmitbuf->padapter; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - /* struct pkt_attrib *pattrib = &pxmitframe->attrib; */ - - - switch (pxmitbuf->flags) { - case VO_QUEUE_INX: - pxmitpriv->voq_cnt--; - break; - case VI_QUEUE_INX: - pxmitpriv->viq_cnt--; - break; - case BE_QUEUE_INX: - pxmitpriv->beq_cnt--; - break; - case BK_QUEUE_INX: - pxmitpriv->bkq_cnt--; - break; - default: - break; - } - - - /* - _enter_critical(&pxmitpriv->lock, &irqL); - - pxmitpriv->txirp_cnt--; - - switch(pattrib->priority) - { - case 1: - case 2: - pxmitpriv->bkq_cnt--; - - break; - case 4: - case 5: - pxmitpriv->viq_cnt--; - - break; - case 6: - case 7: - pxmitpriv->voq_cnt--; - - break; - case 0: - case 3: - default: - pxmitpriv->beq_cnt--; - - break; - - } - _exit_critical(&pxmitpriv->lock, &irqL); + struct lite_data_buf *litexmitbuf = + (struct lite_data_buf *)purb->context; + struct data_urb *xmiturb = litexmitbuf->dataurb; + struct dvobj_priv *pdvobj = litexmitbuf->dvobj; + unsigned long sp_flags; - - if(pxmitpriv->txirp_cnt==0) - { - _rtw_up_sema(&(pxmitpriv->tx_retevt)); - } - */ - /* rtw_free_xmitframe(pxmitpriv, pxmitframe); */ - - if (RTW_CANNOT_TX(padapter)) { - RTW_INFO("%s(): TX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s) pxmitbuf->buf_tag(%x)\n" + if (RTW_CANNOT_TX(pdvobj)) { + RTW_INFO( + "%s(): TX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , pxmitbuf->buf_tag); + , dev_is_drv_stopped(pdvobj) ? "True" : "False" + , dev_is_surprise_removed(pdvobj) ? "True" : "False"); goto check_completion; } @@ -513,11 +304,13 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) if (purb->status == 0) { } else { - RTW_INFO("###=> urb_write_port_complete status(%d)\n", purb->status); + RTW_INFO("###=> urb_write_port_complete status(%d)\n", + purb->status); if ((purb->status == -EPIPE) || (purb->status == -EPROTO)) { /* usb_clear_halt(pusbdev, purb->pipe); */ /* msleep(10); */ - sreset_set_wifi_error_status(padapter, USB_WRITE_PORT_FAIL); + /*sreset_set_wifi_error_status(padapter,*/ + /*USB_WRITE_PORT_FAIL);*/ } else if (purb->status == -EINPROGRESS) { goto check_completion; @@ -530,151 +323,93 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) goto check_completion; } else if (purb->status == -ESHUTDOWN) { - rtw_set_drv_stopped(padapter); + dev_set_drv_stopped(pdvobj); goto check_completion; } else { - rtw_set_surprise_removed(padapter); + dev_set_surprise_removed(pdvobj); RTW_INFO("bSurpriseRemoved=TRUE\n"); goto check_completion; } } - #ifdef DBG_CONFIG_ERROR_DETECT - { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time(); - } - #endif check_completion: - _enter_critical(&pxmitpriv->lock_sctx, &irqL); - rtw_sctx_done_err(&pxmitbuf->sctx, - purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); - _exit_critical(&pxmitpriv->lock_sctx, &irqL); - rtw_free_xmitbuf(pxmitpriv, pxmitbuf); - /* if(rtw_txframes_pending(padapter)) */ - { - tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); - } + rtw_sctx_done_err(&litexmitbuf->sctx, + purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); + rtw_phl_recycle_tx_buf(pdvobj->phl, litexmitbuf->phl_buf_ptr); + rtw_free_litedatabuf(&pdvobj->litexmitbuf_q, litexmitbuf); + rtw_free_dataurb(&pdvobj->xmit_urb_q, xmiturb); + rtw_phl_tx_req_notify(pdvobj->phl); } -u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) + +u32 rtw_usb_write_port(void *d, u8 *phl_tx_buf_ptr, + u8 bulk_id, u32 len, u8 *pkt_data_buf) { - _irqL irqL; - unsigned int pipe; + int status; + unsigned int pipe; u32 ret = _FAIL; - PURB purb = NULL; - _adapter *padapter = (_adapter *)pintfhdl->padapter; - struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct xmit_buf *pxmitbuf = (struct xmit_buf *)wmem; - struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; - struct usb_device *pusbd = pdvobj->pusbdev; - - if (RTW_CANNOT_TX(padapter)) { -#ifdef DBG_TX - RTW_INFO(" DBG_TX %s:%d bDriverStopped%s, bSurpriseRemoved:%s\n", __func__, __LINE__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); -#endif - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_TX_DENY); + struct dvobj_priv *pdvobj = (struct dvobj_priv *)d; + struct usb_device *pusbd = dvobj_to_usb(pdvobj)->pusbdev; + struct lite_data_buf *litexmitbuf = NULL; + struct data_urb *xmiturb = NULL; + + + litexmitbuf = rtw_alloc_litedatabuf(&pdvobj->litexmitbuf_q); + if (litexmitbuf == NULL) { + RTW_INFO("%s,%d Can't alloc lite xmit buf\n", + __func__, __LINE__); goto exit; } - - _enter_critical(&pxmitpriv->lock, &irqL); - - switch (addr) { - case VO_QUEUE_INX: - pxmitpriv->voq_cnt++; - pxmitbuf->flags = VO_QUEUE_INX; - break; - case VI_QUEUE_INX: - pxmitpriv->viq_cnt++; - pxmitbuf->flags = VI_QUEUE_INX; - break; - case BE_QUEUE_INX: - pxmitpriv->beq_cnt++; - pxmitbuf->flags = BE_QUEUE_INX; - break; - case BK_QUEUE_INX: - pxmitpriv->bkq_cnt++; - pxmitbuf->flags = BK_QUEUE_INX; - break; - case HIGH_QUEUE_INX: - pxmitbuf->flags = HIGH_QUEUE_INX; - break; - default: - pxmitbuf->flags = MGT_QUEUE_INX; - break; + xmiturb = rtw_alloc_dataurb(&pdvobj->xmit_urb_q); + if (xmiturb == NULL) { + RTW_INFO("%s,%d Can't alloc lite xmit urb\n", + __func__, __LINE__); + goto exit; } - _exit_critical(&pxmitpriv->lock, &irqL); - - purb = pxmitbuf->pxmit_urb[0]; - - /* translate DMA FIFO addr to pipehandle */ -#ifdef RTW_HALMAC - pipe = ffaddr2pipehdl(pdvobj, pxmitbuf->bulkout_id); -#else - pipe = ffaddr2pipehdl(pdvobj, addr); + if (RTW_CANNOT_TX(pdvobj)) { +#ifdef DBG_TX + RTW_INFO(" DBG_TX %s:%d bDriverStopped:%s, bSurpriseRemoved:%s\n" + ,__func__, __LINE__, + dev_is_drv_stopped(pdvobj) ? "True" : "False", + dev_is_surprise_removed(pdvobj) ? "True" : "False"); #endif - -#ifdef CONFIG_REDUCE_USB_TX_INT - if ((pxmitpriv->free_xmitbuf_cnt % NR_XMITBUFF == 0) - || (pxmitbuf->buf_tag > XMITBUF_DATA)) - purb->transfer_flags &= (~URB_NO_INTERRUPT); - else { - purb->transfer_flags |= URB_NO_INTERRUPT; - /* RTW_INFO("URB_NO_INTERRUPT "); */ + rtw_sctx_done_err(&litexmitbuf->sctx, RTW_SCTX_DONE_TX_DENY); + goto exit; } -#endif - - usb_fill_bulk_urb(purb, pusbd, pipe, - pxmitframe->buf_addr, /* = pxmitbuf->pbuf */ - cnt, - usb_write_port_complete, - pxmitbuf);/* context is pxmitbuf */ + litexmitbuf->dvobj = pdvobj; + litexmitbuf->pbuf = pkt_data_buf; + litexmitbuf->dataurb = xmiturb; + litexmitbuf->phl_buf_ptr = phl_tx_buf_ptr; -#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX - purb->transfer_dma = pxmitbuf->dma_transfer_addr; - purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; - purb->transfer_flags |= URB_ZERO_PACKET; -#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ + pipe = bulkid2pipe(pdvobj, bulk_id, _TRUE); -#ifdef USB_PACKET_OFFSET_SZ -#if (USB_PACKET_OFFSET_SZ == 0) - purb->transfer_flags |= URB_ZERO_PACKET; -#endif -#endif - -#if 0 - if (bwritezero) - purb->transfer_flags |= URB_ZERO_PACKET; -#endif - - status = usb_submit_urb(purb, GFP_ATOMIC); + usb_fill_bulk_urb(xmiturb->urb, pusbd, pipe, + litexmitbuf->pbuf, + len, + rtw_usb_write_port_complete, + litexmitbuf); + xmiturb->urb->transfer_flags |= URB_ZERO_PACKET; + status = usb_submit_urb(xmiturb->urb, GFP_ATOMIC); if (!status) { - #ifdef DBG_CONFIG_ERROR_DETECT - { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - pHalData->srestpriv.last_tx_time = rtw_get_current_time(); - } - #endif + } else { - rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR); - RTW_INFO("usb_write_port, status=%d\n", status); + rtw_sctx_done_err(&litexmitbuf->sctx, + RTW_SCTX_DONE_WRITE_PORT_ERR); + RTW_INFO("%s, status=%d\n", __func__, status); switch (status) { case -ENODEV: - rtw_set_drv_stopped(padapter); + dev_set_drv_stopped(pdvobj); break; default: break; @@ -684,305 +419,119 @@ u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ret = _SUCCESS; - /* Commented by Albert 2009/10/13 - * We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. */ - /* - if(bwritezero == _TRUE) - { - usb_bulkout_zero(pintfhdl, addr); - } - */ - - exit: - if (ret != _SUCCESS) - rtw_free_xmitbuf(pxmitpriv, pxmitbuf); - return ret; - -} - -void usb_write_port_cancel(struct intf_hdl *pintfhdl) -{ - int i, j; - _adapter *padapter = pintfhdl->padapter; - struct xmit_buf *pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmitbuf; - - RTW_INFO("%s\n", __func__); - - for (i = 0; i < NR_XMITBUFF; i++) { - for (j = 0; j < 8; j++) { - if (pxmitbuf->pxmit_urb[j]) - usb_kill_urb(pxmitbuf->pxmit_urb[j]); - } - pxmitbuf++; - } - - pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmit_extbuf; - for (i = 0; i < NR_XMIT_EXTBUFF ; i++) { - for (j = 0; j < 8; j++) { - if (pxmitbuf->pxmit_urb[j]) - usb_kill_urb(pxmitbuf->pxmit_urb[j]); - } - pxmitbuf++; + if (ret != _SUCCESS) { + rtw_free_litedatabuf(&pdvobj->litexmitbuf_q, litexmitbuf); + rtw_free_dataurb(&pdvobj->xmit_urb_q, xmiturb); } -} - -void usb_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf) -{ - - precvbuf->transfer_len = 0; - precvbuf->len = 0; - - precvbuf->ref_cnt = 0; + if (ret == _SUCCESS) + ret = RTW_PHL_STATUS_SUCCESS; + else + ret = RTW_PHL_STATUS_FAILURE; - if (precvbuf->pbuf) { - precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf; - precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ; - } + return ret; } -int recvbuf2recvframe(PADAPTER padapter, void *ptr); - -#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX -void usb_recv_tasklet(unsigned long data) -{ - struct recv_buf *precvbuf = NULL; - _adapter *padapter = (_adapter *)data; - struct recv_priv *precvpriv = &padapter->recvpriv; - - while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) { - if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO("recv_tasklet => bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , rtw_is_drv_stopped(padapter)? "True" : "False" - , rtw_is_surprise_removed(padapter)? "True" : "False"); - break; - } - - recvbuf2recvframe(padapter, precvbuf); - - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - } -} -void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) +void rtw_usb_write_port_cancel(void *d) { - struct recv_buf *precvbuf = (struct recv_buf *)purb->context; - _adapter *padapter = (_adapter *)precvbuf->adapter; - struct recv_priv *precvpriv = &padapter->recvpriv; + int i, j; + struct dvobj_priv *dvobj = (struct dvobj_priv *)d; + struct data_urb *xmiturb = (struct data_urb *)dvobj->xmit_urb_q.urb_buf; + u32 xmiturb_nr = RTW_XMITURB_NR; - ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); - if (RTW_CANNOT_RX(padapter)) { - RTW_INFO("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + if (dvobj == NULL) { + RTW_ERR("%s dvobj is NULL\n", __func__); + rtw_warn_on(1); return; } - if (purb->status == 0) { - - if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { - RTW_INFO("%s()-%d: urb->actual_length:%u, MAX_RECVBUF_SZ:%u, RXDESC_SIZE:%u\n" - , __FUNCTION__, __LINE__, purb->actual_length, MAX_RECVBUF_SZ, RXDESC_SIZE); - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - } else { - rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); - - precvbuf->transfer_len = purb->actual_length; - - rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); - - tasklet_schedule(&precvpriv->recv_tasklet); - } - } else { - - RTW_INFO("###=> usb_read_port_complete => urb.status(%d)\n", purb->status); - - if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) - rtw_set_surprise_removed(padapter); - - switch (purb->status) { - case -EINVAL: - case -EPIPE: - case -ENODEV: - case -ESHUTDOWN: - case -ENOENT: - rtw_set_drv_stopped(padapter); - break; - case -EPROTO: - case -EILSEQ: - case -ETIME: - case -ECOMM: - case -EOVERFLOW: - #ifdef DBG_CONFIG_ERROR_DETECT - { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; - } - #endif - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - break; - case -EINPROGRESS: - RTW_INFO("ERROR: URB IS IN PROGRESS!/n"); - break; - default: - break; - } - } - -} - -u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) -{ - int err; - unsigned int pipe; - u32 ret = _SUCCESS; - PURB purb = NULL; - struct recv_buf *precvbuf = (struct recv_buf *)rmem; - _adapter *adapter = pintfhdl->padapter; - struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); - struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobj); - struct recv_priv *precvpriv = &adapter->recvpriv; - struct usb_device *pusbd = pdvobj->pusbdev; - - - if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) { - return _FAIL; - } - - usb_init_recvbuf(adapter, precvbuf); - - if (precvbuf->pbuf) { - ATOMIC_INC(&(precvpriv->rx_pending_cnt)); - purb = precvbuf->purb; - - /* translate DMA FIFO addr to pipehandle */ - pipe = ffaddr2pipehdl(pdvobj, addr); - - usb_fill_bulk_urb(purb, pusbd, pipe, - precvbuf->pbuf, - MAX_RECVBUF_SZ, - usb_read_port_complete, - precvbuf);/* context is precvbuf */ - - purb->transfer_dma = precvbuf->dma_transfer_addr; - purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; - - err = usb_submit_urb(purb, GFP_ATOMIC); - if ((err) && (err != (-EPERM))) { - RTW_INFO("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n", err, purb->status); - ret = _FAIL; - } + RTW_INFO("%s\n", __func__); + for (i = 0; i < xmiturb_nr; i++) { + usb_kill_urb(xmiturb->urb); + xmiturb++; } - return ret; } -#else /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ -void usb_recv_tasklet(unsigned long data) +static void rtw_usb_read_port_complete(struct urb *urb, struct pt_regs *regs) { - _pkt *pskb; - _adapter *padapter = (_adapter *)data; - struct recv_priv *precvpriv = &padapter->recvpriv; - struct recv_buf *precvbuf = NULL; - - while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) { - - if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO("recv_tasklet => bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); - #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - if (rtw_free_skb_premem(pskb) != 0) - #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ - rtw_skb_free(pskb); - break; - } - - recvbuf2recvframe(padapter, pskb); - - skb_reset_tail_pointer(pskb); - pskb->len = 0; - - skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); - - precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue); - if (NULL != precvbuf) { - precvbuf->pskb = NULL; - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - } + struct lite_data_buf *literecvbuf = + (struct lite_data_buf *)urb->context; + struct data_urb *recvurb = literecvbuf->dataurb; + struct dvobj_priv *dvobj = literecvbuf->dvobj; + struct trx_data_buf_q *rx_data_buf_q = NULL; + struct trx_urb_buf_q *rx_urb_q = NULL; + u32 actual_length = urb->actual_length; + u32 transfer_buffer_length = urb->transfer_buffer_length; + u8 bulk_id = recvurb->bulk_id; + u8 minlen = recvurb->minlen; + unsigned long sp_flags; + u8 status = _SUCCESS; + + + if (bulk_id == REALTEK_USB_BULK_IN_EP_IDX) { + rx_data_buf_q = &dvobj->literecvbuf_q; + rx_urb_q = &dvobj->recv_urb_q; + ATOMIC_DEC(&(dvobj->rx_pending_cnt)); + } else { + #ifdef CONFIG_USB_INTERRUPT_IN_PIPE + rx_data_buf_q = &dvobj->intin_buf_q; + rx_urb_q = &dvobj->intin_urb_q; + #endif } -} -void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) -{ - struct recv_buf *precvbuf = (struct recv_buf *)purb->context; - _adapter *padapter = (_adapter *)precvbuf->adapter; - struct recv_priv *precvpriv = &padapter->recvpriv; - - ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); - - if (RTW_CANNOT_RX(padapter)) { + if (RTW_CANNOT_RX(dvobj)) { RTW_INFO("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , dev_is_drv_stopped(dvobj) ? "True" : "False" + , dev_is_surprise_removed(dvobj) ? "True" : "False"); + + status = _FAIL; goto exit; } - if (purb->status == 0) { + if (urb->status == 0) { + if ((actual_length > transfer_buffer_length) || (actual_length < minlen)) { + RTW_INFO("%s()-%d: actual_length:%u, transfer_buffer_length:%u, minlen:%u\n" + , __FUNCTION__, __LINE__, actual_length, transfer_buffer_length, minlen); - if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { - RTW_INFO("%s()-%d: urb->actual_length:%u, MAX_RECVBUF_SZ:%u, RXDESC_SIZE:%u\n" - , __FUNCTION__, __LINE__, purb->actual_length, MAX_RECVBUF_SZ, RXDESC_SIZE); - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + status = _FAIL; + goto exit; } else { - rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); - - precvbuf->transfer_len = purb->actual_length; - skb_put(precvbuf->pskb, purb->actual_length); - skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); - - #ifndef CONFIG_FIX_NR_BULKIN_BUFFER - if (skb_queue_len(&precvpriv->rx_skb_queue) <= 1) - #endif - tasklet_schedule(&precvpriv->recv_tasklet); - - precvbuf->pskb = NULL; - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + rtw_reset_continual_io_error(dvobj); + status = _SUCCESS; + goto exit; } + } if (urb->status == -ENOENT) { + /*use usb_kill_urb urb status code = -ENOENT*/ + status = _FAIL; + goto exit; } else { - RTW_INFO("###=> usb_read_port_complete => urb.status(%d)\n", purb->status); + RTW_INFO("###=> %s => urb.status(%d)\n", __func__, urb->status); + status = _FAIL; - if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) - rtw_set_surprise_removed(padapter); + if (rtw_inc_and_chk_continual_io_error(dvobj) == _TRUE) + dev_set_surprise_removed(dvobj); - switch (purb->status) { + switch (urb->status) { case -EINVAL: case -EPIPE: case -ENODEV: case -ESHUTDOWN: - case -ENOENT: - rtw_set_drv_stopped(padapter); + dev_set_drv_stopped(dvobj); break; case -EPROTO: case -EILSEQ: case -ETIME: case -ECOMM: case -EOVERFLOW: - #ifdef DBG_CONFIG_ERROR_DETECT - { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; - } - #endif - rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); break; case -EINPROGRESS: RTW_INFO("ERROR: URB IS IN PROGRESS!/n"); @@ -990,168 +539,158 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) default: break; } + goto exit; } exit: - return; + + if (status == _SUCCESS) + status = RTW_PHL_STATUS_SUCCESS; + else + status = RTW_PHL_STATUS_FAILURE; + + rtw_phl_post_in_complete(dvobj->phl, literecvbuf->phl_buf_ptr, actual_length, status); + rtw_free_litedatabuf(rx_data_buf_q, literecvbuf); + rtw_free_dataurb(rx_urb_q, recvurb); } -u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) +u32 rtw_usb_read_port(void *d, void *rxobj, + u8 *inbuf, u32 inbuf_len, u8 bulk_id, u8 minlen) { int err; unsigned int pipe; u32 ret = _FAIL; - PURB purb = NULL; - struct recv_buf *precvbuf = (struct recv_buf *)rmem; - _adapter *adapter = pintfhdl->padapter; - struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); - struct recv_priv *precvpriv = &adapter->recvpriv; - struct usb_device *pusbd = pdvobj->pusbdev; - - - if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) { + struct dvobj_priv *dvobj = (struct dvobj_priv *)d; + struct usb_device *usbd = dvobj_to_usb(dvobj)->pusbdev; + struct lite_data_buf *literecvbuf = NULL; + struct data_urb *recvurb = NULL; + struct trx_data_buf_q *rx_data_buf_q = NULL; + struct trx_urb_buf_q *rx_urb_q = NULL; + struct usb_data *usb_data = dvobj_to_usb(dvobj); + + if (RTW_CANNOT_RX(dvobj) || (inbuf == NULL)) { goto exit; } - usb_init_recvbuf(adapter, precvbuf); - - if (precvbuf->pskb == NULL) { - SIZE_PTR tmpaddr = 0; - SIZE_PTR alignment = 0; - - precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue); - if (NULL != precvbuf->pskb) - goto recv_buf_hook; - - #ifndef CONFIG_FIX_NR_BULKIN_BUFFER - precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); + if (bulk_id == REALTEK_USB_BULK_IN_EP_IDX) { + rx_data_buf_q = &dvobj->literecvbuf_q; + rx_urb_q = &dvobj->recv_urb_q; + } else if (bulk_id == REALTEK_USB_IN_INT_EP_IDX) { + #ifdef CONFIG_USB_INTERRUPT_IN_PIPE + rx_data_buf_q = &dvobj->intin_buf_q; + rx_urb_q = &dvobj->intin_urb_q; + #else + goto exit; #endif - - if (precvbuf->pskb == NULL) { - if (0) - RTW_INFO("usb_read_port() enqueue precvbuf=%p\n", precvbuf); - /* enqueue precvbuf and wait for free skb */ - rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); - goto exit; - } - - tmpaddr = (SIZE_PTR)precvbuf->pskb->data; - alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1); - skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); + } else { + RTW_INFO("%s,%d Unkown bulk id:%d\n", + __func__, __LINE__, bulk_id); + ret = _FAIL; + goto exit; } -recv_buf_hook: - precvbuf->phead = precvbuf->pskb->head; - precvbuf->pdata = precvbuf->pskb->data; - precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); - precvbuf->pend = skb_end_pointer(precvbuf->pskb); - precvbuf->pbuf = precvbuf->pskb->data; + literecvbuf = rtw_alloc_litedatabuf(rx_data_buf_q); + if (literecvbuf == NULL) { + RTW_INFO("%s,%d Can't alloc lite recv buf\n", + __func__, __LINE__); + goto exit; + } + recvurb = rtw_alloc_dataurb(rx_urb_q); + if (recvurb == NULL) { + RTW_INFO("%s,%d Can't alloc lite recv urb\n", + __func__, __LINE__); + goto exit; + } - purb = precvbuf->purb; + recvurb->bulk_id = bulk_id; + recvurb->minlen = minlen; + literecvbuf->dvobj = dvobj; + literecvbuf->pbuf = inbuf; + literecvbuf->dataurb = recvurb; + literecvbuf->phl_buf_ptr = rxobj; - /* translate DMA FIFO addr to pipehandle */ - pipe = ffaddr2pipehdl(pdvobj, addr); + pipe = bulkid2pipe(dvobj, bulk_id, _FALSE); - usb_fill_bulk_urb(purb, pusbd, pipe, - precvbuf->pbuf, - MAX_RECVBUF_SZ, - usb_read_port_complete, - precvbuf); + if (bulk_id == REALTEK_USB_BULK_IN_EP_IDX) { + usb_fill_bulk_urb(recvurb->urb, usbd, pipe, + literecvbuf->pbuf, + inbuf_len, + rtw_usb_read_port_complete, + literecvbuf); + } else { + #ifdef CONFIG_USB_INTERRUPT_IN_PIPE + if (usb_data->inpipe_type[bulk_id] == REALTEK_USB_BULK_IN_EP_IDX) + usb_fill_bulk_urb(recvurb->urb, usbd, pipe, + literecvbuf->pbuf, + inbuf_len, + rtw_usb_read_port_complete, + literecvbuf); + else + usb_fill_int_urb(recvurb->urb, usbd, pipe, + literecvbuf->pbuf, + inbuf_len, + rtw_usb_read_port_complete, + literecvbuf, + 1); + #endif + } - err = usb_submit_urb(purb, GFP_ATOMIC); - if (err && err != (-EPERM)) { - RTW_INFO("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n" - , err, purb->status); + err = usb_submit_urb(recvurb->urb, GFP_ATOMIC); + if ((err) && (err != (-EPERM))) { + RTW_INFO("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n", err, recvurb->urb->status); + ret = _FAIL; goto exit; } - ATOMIC_INC(&(precvpriv->rx_pending_cnt)); - ret = _SUCCESS; + /* record usb bulk in */ + if (bulk_id == REALTEK_USB_BULK_IN_EP_IDX) + ATOMIC_INC(&(dvobj->rx_pending_cnt)); + ret = _SUCCESS; exit: + if (ret != _SUCCESS) { + rtw_free_litedatabuf(rx_data_buf_q, literecvbuf); + rtw_free_dataurb(rx_urb_q, recvurb); + } + if (ret == _SUCCESS) + ret = RTW_PHL_STATUS_SUCCESS; + else + ret = RTW_PHL_STATUS_FAILURE; return ret; } -#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ -#ifdef CONFIG_USB_INTERRUPT_IN_PIPE -void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) +void rtw_usb_read_port_cancel(void *d) { - int err; - _adapter *padapter = (_adapter *)purb->context; - - if (RTW_CANNOT_RX(padapter)) { - RTW_INFO("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + int i; + struct dvobj_priv *dvobj = (struct dvobj_priv *)d; + struct data_urb *recvurb = (struct data_urb *)dvobj->recv_urb_q.urb_buf; + /*Elwin_todo need use correct literecvbuf_nr recvurb_nr */ + u32 recvurb_nr = RTW_RECVURB_NR; +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + u32 initinurb_nr = RTW_INTINURB_NR; +#endif + if (dvobj == NULL) { + RTW_ERR("%s dvobj is NULL\n", __func__); + rtw_warn_on(1); return; } + RTW_INFO("%s\n", __func__); - if (purb->status == 0) {/*SUCCESS*/ - if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN) - RTW_INFO("usb_read_interrupt_complete: purb->actual_length > INTERRUPT_MSG_FORMAT_LEN(%d)\n", INTERRUPT_MSG_FORMAT_LEN); - - rtw_hal_interrupt_handler(padapter, purb->actual_length, purb->transfer_buffer); - - err = usb_submit_urb(purb, GFP_ATOMIC); - if ((err) && (err != (-EPERM))) - RTW_INFO("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n", err, purb->status); - } else { - RTW_INFO("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status); - - switch (purb->status) { - case -EINVAL: - case -EPIPE: - case -ENODEV: - case -ESHUTDOWN: - case -ENOENT: - rtw_set_drv_stopped(padapter); - break; - case -EPROTO: - break; - case -EINPROGRESS: - RTW_INFO("ERROR: URB IS IN PROGRESS!/n"); - break; - default: - break; - } - } -} - -u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) -{ - int err; - unsigned int pipe; - u32 ret = _SUCCESS; - _adapter *adapter = pintfhdl->padapter; - struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); - struct recv_priv *precvpriv = &adapter->recvpriv; - struct usb_device *pusbd = pdvobj->pusbdev; - - - if (RTW_CANNOT_RX(adapter)) { - return _FAIL; + + for (i = 0; i < recvurb_nr; i++) { + usb_kill_urb(recvurb->urb); + recvurb++; } - /*translate DMA FIFO addr to pipehandle*/ - pipe = ffaddr2pipehdl(pdvobj, addr); - - usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, - precvpriv->int_in_buf, - INTERRUPT_MSG_FORMAT_LEN, - usb_read_interrupt_complete, - adapter, - 1); - err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC); - if ((err) && (err != (-EPERM))) { - RTW_INFO("cannot submit interrupt in-token(err = 0x%08x), urb_status = %d\n", err, precvpriv->int_in_urb->status); - ret = _FAIL; +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + recvurb = (struct data_urb *)dvobj->intin_urb_q.urb_buf; + for (i = 0; i < initinurb_nr; i++) { + usb_kill_urb(recvurb->urb); + recvurb++; } - - return ret; +#endif } -#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ diff --git a/os_dep/linux/wifi_regd.c b/os_dep/linux/wifi_regd.c index 1430614..d2a1ef9 100644 --- a/os_dep/linux/wifi_regd.c +++ b/os_dep/linux/wifi_regd.c @@ -16,16 +16,245 @@ #include #ifdef CONFIG_IOCTL_CFG80211 -static void rtw_regd_overide_flags(struct wiphy *wiphy, struct rf_ctl_t *rfctl) +void rtw_chset_hook_os_channels(struct rf_ctl_t *rfctl) { + struct wiphy *wiphy = dvobj_to_wiphy(rfctl_to_dvobj(rfctl)); RT_CHANNEL_INFO *channel_set = rfctl->channel_set; u8 max_chan_nums = rfctl->max_chan_nums; - struct ieee80211_supported_band *sband; struct ieee80211_channel *ch; - unsigned int i, j; + unsigned int i; u16 channel; u32 freq; + for (i = 0; i < max_chan_nums; i++) { + channel = channel_set[i].ChannelNum; + #if CONFIG_IEEE80211_BAND_6GHZ + if (channel_set[i].band == BAND_ON_6G) + continue; /* TODO: wiphy with 6G band */ + else + #endif + freq = rtw_ch2freq(channel); + ch = ieee80211_get_channel(wiphy, freq); + if (!ch) { + rtw_warn_on(1); + continue; + } + + channel_set[i].os_chan = ch; + } +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) +bool rtw_regd_is_wiphy_self_managed(struct wiphy *wiphy) +{ + return rtw_rfctl_is_disable_sw_channel_plan(wiphy_to_dvobj(wiphy)) + || !REGSTY_REGD_SRC_FROM_OS(dvobj_to_regsty(wiphy_to_dvobj(wiphy))); +} + +static struct ieee80211_reg_rule rtw_get_ieee80211_reg_rule(struct get_chplan_resp *chplan, enum band_type band, int last_end_freq, int start_freq, int end_freq, int next_start_freq, u32 flags) +{ + struct ieee80211_reg_rule rule = REG_RULE( + start_freq - 10, end_freq + 10, 20, 6, 20, + ((flags & RTW_CHF_NO_IR) ? NL80211_RRF_NO_IR : 0) + //| ((flags & RTW_CHF_DFS) ? NL80211_RRF_DFS : 0) /* TODO: DFS */ + ); + + int regd_max_bw = 160; + int frange_max_bw = 160; + + if (!(chplan->proto_en & CHPLAN_PROTO_EN_AC) || band == BAND_ON_24G) + regd_max_bw = 40; + /* TODO: !RFCTL_REG_EN_11HT(rfctl) limit to 20MHz */ + + while ((end_freq - start_freq + 20) < frange_max_bw) { + frange_max_bw /= 2; + if (frange_max_bw == 20) + break; + } + rule.freq_range.max_bandwidth_khz = MHZ_TO_KHZ(rtw_min(regd_max_bw, frange_max_bw)); + + if (regd_max_bw > frange_max_bw + && (rtw_freq_consecutive(last_end_freq, start_freq) + || rtw_freq_consecutive(end_freq, next_start_freq) + ) + ) + rule.flags |= NL80211_RRF_AUTO_BW; + + if (regd_max_bw < 40) + rule.flags |= NL80211_RRF_NO_HT40; + if (regd_max_bw < 80) + rule.flags |= NL80211_RRF_NO_80MHZ; + if (regd_max_bw < 160) + rule.flags |= NL80211_RRF_NO_160MHZ; + + return rule; +} + +static int rtw_build_wiphy_regd(struct wiphy *wiphy, struct get_chplan_resp *chplan, struct ieee80211_regdomain **regd) +{ + int i; + RT_CHANNEL_INFO *chinfo; + enum band_type start_band, band; + int last_end_freq, start_freq, end_freq, freq; + u32 start_flags, flags; + struct ieee80211_regdomain *r; + int rule_num = 0; + bool build = 0; + + if (regd) + *regd = NULL; + +loop: + start_band = BAND_MAX; + last_end_freq = 0; + for (i = 0; i < chplan->chset_num; i++) { + chinfo = &chplan->chset[i]; + freq = rtw_ch2freq_by_band(chinfo->band, chinfo->ChannelNum); + if (!freq) { + RTW_WARN(FUNC_WIPHY_FMT" rtw_ch2freq_by_band(%s, %u) fail\n" + , FUNC_WIPHY_ARG(wiphy), band_str(chinfo->band), chinfo->ChannelNum); + continue; + } + band = chinfo->band; + flags = chinfo->flags & (RTW_CHF_NO_IR | RTW_CHF_DFS); + + if (start_band == BAND_MAX) { + start_band = band; + start_freq = end_freq = freq; + start_flags = flags; + continue; + } + + if (start_band == band + && start_flags == flags + && rtw_freq_consecutive(end_freq, freq) + ) { + end_freq = freq; + continue; + } + + /* create rule */ + if (build) { + RTW_DBG("add rule_%02d(%s, %d, %d, 0x%x)\n" + , r->n_reg_rules, band_str(start_band), start_freq, end_freq, start_flags); + r->reg_rules[r->n_reg_rules++] = rtw_get_ieee80211_reg_rule(chplan, start_band + , last_end_freq, start_freq, end_freq, freq, start_flags); + } else + rule_num++; + + /* start a new rule */ + start_band = band; + last_end_freq = end_freq; + start_freq = end_freq = freq; + start_flags = flags; + } + + if (start_band != BAND_MAX) { + /* create rule */ + if (build) { + RTW_DBG("add rule_%02d(%s, %d, %d, 0x%x)\n" + , r->n_reg_rules, band_str(start_band), start_freq, end_freq, start_flags); + r->reg_rules[r->n_reg_rules++] = rtw_get_ieee80211_reg_rule(chplan, start_band + , last_end_freq, start_freq, end_freq, 0, start_flags); + } else + rule_num++; + } + + if (!build) { + /* switch to build phase */ + build = 1; + if (!regd) + goto exit; + + r = rtw_zmalloc(sizeof(**regd) + sizeof(struct ieee80211_reg_rule) * rule_num); + if (!r) { + rule_num = -1; + goto exit; + } + + _rtw_memcpy(r->alpha2, chplan->alpha2, 2); + r->alpha2[2] = 0; + r->dfs_region = NL80211_DFS_UNSET; + goto loop; + } + + *regd = r; + +exit: + return rule_num; +} + +static void rtw_regd_disable_no_20mhz_chs(struct wiphy *wiphy) +{ + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + unsigned int i, j; + + for (i = 0; i < NUM_NL80211_BANDS; i++) { + sband = wiphy->bands[i]; + if (!sband) + continue; + for (j = 0; j < sband->n_channels; j++) { + ch = &sband->channels[j]; + if (!ch) + continue; + if (ch->flags & IEEE80211_CHAN_NO_20MHZ) { + RTW_INFO(FUNC_WIPHY_FMT" disable band:%d ch:%u w/o 20MHz\n", FUNC_WIPHY_ARG(wiphy), ch->band, ch->hw_value); + ch->flags = IEEE80211_CHAN_DISABLED; + } + } + } +} + +void rtw_update_wiphy_regd(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed) +{ + struct ieee80211_regdomain *regd; + int ret; + + ret = rtw_build_wiphy_regd(wiphy, chplan, ®d); + if (ret == -1) { + RTW_WARN(FUNC_WIPHY_FMT" rtw_build_wiphy_regd() fail\n", FUNC_WIPHY_ARG(wiphy)); + return; + } + + if (ret == 0) { + RTW_WARN(FUNC_WIPHY_FMT" rtw_build_wiphy_regd() builds empty regd, bypass regd setting\n", FUNC_WIPHY_ARG(wiphy)); + goto free_regd; + } + + if (rtnl_lock_needed) + rtnl_lock(); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) + ret = regulatory_set_wiphy_regd_sync(wiphy, regd); + #else + ret = regulatory_set_wiphy_regd_sync_rtnl(wiphy, regd); + #endif + + rtw_regd_disable_no_20mhz_chs(wiphy); + + if (rtnl_lock_needed) + rtnl_unlock(); + + if (ret != 0) + RTW_INFO(FUNC_WIPHY_FMT" regulatory_set_wiphy_regd_sync_rtnl return %d\n", FUNC_WIPHY_ARG(wiphy), ret); + +free_regd: + rtw_mfree(regd, sizeof(*regd) + sizeof(struct ieee80211_reg_rule) * regd->n_reg_rules); +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */ + +static void rtw_regd_overide_flags(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed) +{ + RT_CHANNEL_INFO *channel_set = chplan->chset; + u8 max_chan_nums = chplan->chset_num; + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + unsigned int i, j; + + if (rtnl_lock_needed) + rtnl_lock(); + /* all channels disable */ for (i = 0; i < NUM_NL80211_BANDS; i++) { sband = wiphy->bands[i]; @@ -41,13 +270,9 @@ static void rtw_regd_overide_flags(struct wiphy *wiphy, struct rf_ctl_t *rfctl) /* channels apply by channel plans. */ for (i = 0; i < max_chan_nums; i++) { - channel = channel_set[i].ChannelNum; - freq = rtw_ch2freq(channel); - ch = ieee80211_get_channel(wiphy, freq); - if (!ch) { - rtw_warn_on(1); + ch = channel_set[i].os_chan; + if (!ch) continue; - } /* enable */ ch->flags = 0; @@ -58,7 +283,9 @@ static void rtw_regd_overide_flags(struct wiphy *wiphy, struct rf_ctl_t *rfctl) * bypass IEEE80211_CHAN_RADAR when configured with radar detection * to prevent from hostapd blocking DFS channels */ - if (rtw_rfctl_dfs_domain_unknown(rfctl)) + #ifdef CONFIG_DFS_MASTER + if (chplan->dfs_domain == RTW_DFS_REGD_NONE) + #endif ch->flags |= IEEE80211_CHAN_RADAR; } @@ -70,48 +297,46 @@ static void rtw_regd_overide_flags(struct wiphy *wiphy, struct rf_ctl_t *rfctl) #endif } } + + if (rtnl_lock_needed) + rtnl_unlock(); } #ifdef CONFIG_REGD_SRC_FROM_OS -static void rtw_regd_apply_dfs_flags(struct rf_ctl_t *rfctl) +static void rtw_regd_apply_dfs_flags(struct get_chplan_resp *chplan, bool rtnl_lock_needed) { - RT_CHANNEL_INFO *channel_set = rfctl->channel_set; - u8 max_chan_nums = rfctl->max_chan_nums; + RT_CHANNEL_INFO *channel_set = chplan->chset; + u8 max_chan_nums = chplan->chset_num; unsigned int i; struct ieee80211_channel *chan; + if (rtnl_lock_needed) + rtnl_lock(); + /* channels apply by channel plans. */ for (i = 0; i < max_chan_nums; i++) { chan = channel_set[i].os_chan; + if (!chan) { + rtw_warn_on(1); + continue; + } if (channel_set[i].flags & RTW_CHF_DFS) { /* * before integrating with nl80211 flow * clear IEEE80211_CHAN_RADAR when configured with radar detection * to prevent from hostapd blocking DFS channels */ - if (!rtw_rfctl_dfs_domain_unknown(rfctl)) + #ifdef CONFIG_DFS_MASTER + if (chplan->dfs_domain != RTW_DFS_REGD_NONE) chan->flags &= ~IEEE80211_CHAN_RADAR; + #endif } } -} -#endif - -void rtw_regd_apply_flags(struct wiphy *wiphy) -{ - struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); - if (rfctl->regd_src == REGD_SRC_RTK_PRIV) - rtw_regd_overide_flags(wiphy, rfctl); -#ifdef CONFIG_REGD_SRC_FROM_OS - else if (rfctl->regd_src == REGD_SRC_OS) - rtw_regd_apply_dfs_flags(rfctl); -#endif - else - rtw_warn_on(1); + if (rtnl_lock_needed) + rtnl_unlock(); } -#ifdef CONFIG_REGD_SRC_FROM_OS /* init_channel_set_from_wiphy */ u8 rtw_os_init_channel_set(_adapter *padapter, RT_CHANNEL_INFO *channel_set) { @@ -141,6 +366,7 @@ u8 rtw_os_init_channel_set(_adapter *padapter, RT_CHANNEL_INFO *channel_set) } channel_set[chanset_size].ChannelNum = chan->hw_value; + channel_set[chanset_size].band = nl80211_band_to_rtw_band(i); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) if (chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN)) #else @@ -233,6 +459,22 @@ static enum rtw_dfs_regd nl80211_dfs_regions_to_rtw_dfs_region(enum nl80211_dfs_ #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */ #endif /* CONFIG_REGD_SRC_FROM_OS */ +static enum rtw_regd_inr nl80211_reg_initiator_to_rtw_regd_inr(enum nl80211_reg_initiator initiator) +{ + switch (initiator) { + case NL80211_REGDOM_SET_BY_DRIVER: + return RTW_REGD_SET_BY_DRIVER; + case NL80211_REGDOM_SET_BY_CORE: + return RTW_REGD_SET_BY_CORE; + case NL80211_REGDOM_SET_BY_USER: + return RTW_REGD_SET_BY_USER; + case NL80211_REGDOM_SET_BY_COUNTRY_IE: + return RTW_REGD_SET_BY_COUNTRY_IE; + } + rtw_warn_on(1); + return RTW_REGD_SET_BY_NUM; +}; + #ifdef CONFIG_RTW_DEBUG static const char *nl80211_reg_initiator_str(enum nl80211_reg_initiator initiator) { @@ -341,8 +583,12 @@ static void dump_requlatory_request(void *sel, struct regulatory_request *reques static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) { struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); struct registry_priv *regsty = dvobj_to_regsty(dvobj); + enum rtw_regd_inr inr; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + rtw_set_rtnl_lock_holder(dvobj, current); +#endif #ifdef CONFIG_RTW_DEBUG if (rtw_drv_log_level >= _DRV_INFO_) { @@ -351,6 +597,8 @@ static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *req } #endif + inr = nl80211_reg_initiator_to_rtw_regd_inr(request->initiator); + #ifdef CONFIG_REGD_SRC_FROM_OS if (REGSTY_REGD_SRC_FROM_OS(regsty)) { enum rtw_dfs_regd dfs_region = RTW_DFS_REGD_NONE; @@ -360,25 +608,35 @@ static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *req #endif /* trigger command to sync regulatory form OS */ - rtw_sync_os_regd_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, request->alpha2, dfs_region); + rtw_sync_os_regd_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, request->alpha2, dfs_region, inr); } else #endif { /* use alpha2 as input to select the corresponding channel plan settings defined by Realtek */ + struct get_chplan_resp *chplan; + switch (request->initiator) { - case NL80211_REGDOM_SET_BY_DRIVER: - break; - case NL80211_REGDOM_SET_BY_CORE: - break; case NL80211_REGDOM_SET_BY_USER: - rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2); + rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2, inr); break; + case NL80211_REGDOM_SET_BY_DRIVER: + case NL80211_REGDOM_SET_BY_CORE: case NL80211_REGDOM_SET_BY_COUNTRY_IE: + default: + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) + rtw_warn_on(rtw_regd_is_wiphy_self_managed(wiphy)); + #endif + if (rtw_get_chplan_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, &chplan) == _SUCCESS) + rtw_regd_change_complete_sync(wiphy, chplan, 0); + else + rtw_warn_on(1); break; } - - rtw_regd_apply_flags(wiphy); } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + rtw_set_rtnl_lock_holder(dvobj, NULL); +#endif } #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) @@ -389,8 +647,38 @@ static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_reques } #endif +struct async_regd_change_evt { + _list list; /* async_regd_change_list */ + struct wiphy *wiphy; + struct get_chplan_resp *chplan; +}; + +static void async_regd_change_work_hdl(_workitem *work) +{ + struct rtw_wiphy_data *wiphy_data = container_of(work, struct rtw_wiphy_data, async_regd_change_work); + struct async_regd_change_evt *evt; + _list *list, *head = &wiphy_data->async_regd_change_list; + + while (1) { + _rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex); + list = rtw_is_list_empty(head) ? NULL : get_next(head); + if (list) + rtw_list_delete(list); + _rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex); + + if (!list) + break; + + evt = LIST_CONTAINOR(list, struct async_regd_change_evt, list); + rtw_regd_change_complete_sync(evt->wiphy, evt->chplan, 1); + rtw_mfree(evt, sizeof(*evt)); + } +} + int rtw_regd_init(struct wiphy *wiphy) { + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) wiphy->reg_notifier = rtw_reg_notifier_return; #else @@ -405,12 +693,98 @@ int rtw_regd_init(struct wiphy *wiphy) wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 39)) - return 0; -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF; #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) + if (rtw_regd_is_wiphy_self_managed(wiphy)) + wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED; +#endif + + _rtw_init_listhead(&wiphy_data->async_regd_change_list); + _rtw_mutex_init(&wiphy_data->async_regd_change_mutex); + _init_workitem(&wiphy_data->async_regd_change_work, async_regd_change_work_hdl, NULL); + return 0; } + +static void rtw_regd_async_regd_change_list_free(struct wiphy *wiphy) +{ + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + struct async_regd_change_evt *evt; + struct get_chplan_resp *chplan; + _list *cur, *head; + + _rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex); + + head = &wiphy_data->async_regd_change_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + evt = LIST_CONTAINOR(cur, struct async_regd_change_evt, list); + chplan = evt->chplan; + cur = get_next(cur); + rtw_list_delete(&evt->list); + rtw_vmfree(chplan, sizeof(*chplan) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num); + rtw_mfree(evt, sizeof(*evt)); + } + + _rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex); +} + +void rtw_regd_deinit(struct wiphy *wiphy) +{ + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + + _cancel_workitem_sync(&wiphy_data->async_regd_change_work); + rtw_regd_async_regd_change_list_free(wiphy); + _rtw_mutex_free(&wiphy_data->async_regd_change_mutex); +} + +void rtw_regd_change_complete_sync(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed) +{ + if (chplan->regd_src == REGD_SRC_RTK_PRIV) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) + if (rtw_regd_is_wiphy_self_managed(wiphy)) + rtw_update_wiphy_regd(wiphy, chplan, rtnl_lock_needed); + else + #endif + rtw_regd_overide_flags(wiphy, chplan, rtnl_lock_needed); + } +#ifdef CONFIG_REGD_SRC_FROM_OS + else if (chplan->regd_src == REGD_SRC_OS) + rtw_regd_apply_dfs_flags(chplan, rtnl_lock_needed); +#endif + else + rtw_warn_on(1); + + rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num); +} + +int rtw_regd_change_complete_async(struct wiphy *wiphy, struct get_chplan_resp *chplan) +{ + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + struct async_regd_change_evt *evt; + + evt = rtw_malloc(sizeof(*evt)); + if (!evt) { + rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num); + return _FAIL; + } + + _rtw_init_listhead(&evt->list); + evt->wiphy = wiphy; + evt->chplan = chplan; + + _rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex); + + rtw_list_insert_tail(&evt->list, &wiphy_data->async_regd_change_list); + + _rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex); + + _set_workitem(&wiphy_data->async_regd_change_work); + + return _SUCCESS; +} #endif /* CONFIG_IOCTL_CFG80211 */ diff --git a/os_dep/linux/wifi_regd.h b/os_dep/linux/wifi_regd.h index 4e147fc..c7e2f2c 100644 --- a/os_dep/linux/wifi_regd.h +++ b/os_dep/linux/wifi_regd.h @@ -16,12 +16,15 @@ #ifndef __WIFI_REGD_H__ #define __WIFI_REGD_H__ -void rtw_regd_apply_flags(struct wiphy *wiphy); +void rtw_chset_hook_os_channels(struct rf_ctl_t *rfctl); +void rtw_regd_change_complete_sync(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed); +int rtw_regd_change_complete_async(struct wiphy *wiphy, struct get_chplan_resp *chplan); #ifdef CONFIG_REGD_SRC_FROM_OS struct _RT_CHANNEL_INFO; u8 rtw_os_init_channel_set(_adapter *padapter, struct _RT_CHANNEL_INFO *channel_set); s16 rtw_os_get_total_txpwr_regd_lmt_mbm(_adapter *adapter, u8 cch, enum channel_width bw); #endif int rtw_regd_init(struct wiphy *wiphy); +void rtw_regd_deinit(struct wiphy *wiphy); #endif /* __WIFI_REGD_H__ */ diff --git a/os_dep/linux/xmit_linux.c b/os_dep/linux/xmit_linux.c index f4f508e..5ee707c 100644 --- a/os_dep/linux/xmit_linux.c +++ b/os_dep/linux/xmit_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -23,7 +23,7 @@ uint rtw_remainder_len(struct pkt_file *pfile) return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start)); } -void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile) +void _rtw_open_pktfile(struct sk_buff *pktptr, struct pkt_file *pfile) { pfile->pkt = pktptr; @@ -63,7 +63,7 @@ sint rtw_endofpktfile(struct pkt_file *pfile) return _FALSE; } -void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) +void rtw_set_tx_chksum_offload(struct sk_buff *pkt, struct pkt_attrib *pattrib) { #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX struct sk_buff *skb = (struct sk_buff *)pkt; @@ -111,13 +111,13 @@ void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) #endif } - +#if 0 /*CONFIG_CORE_XMITBUF*/ int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag) { if (alloc_sz > 0) { #ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct usb_device *pusbd = pdvobjpriv->pusbdev; + struct usb_device *pusbd = dvobj_to_usb(pdvobjpriv)->pusbdev; pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr); pxmitbuf->pbuf = pxmitbuf->pallocated_buf; @@ -129,7 +129,7 @@ int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u3 if (pxmitbuf->pallocated_buf == NULL) return _FAIL; - pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); + pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), SZ_ALIGN_XMITFRAME_EXT); #endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ } @@ -168,7 +168,7 @@ void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u3 if (free_sz > 0) { #ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct usb_device *pusbd = pdvobjpriv->pusbdev; + struct usb_device *pusbd = dvobj_to_usb(pdvobjpriv)->pusbdev; rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr); pxmitbuf->pallocated_buf = NULL; @@ -179,6 +179,57 @@ void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u3 #endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ } } +#else +u8 rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_frame *pxframe) +{ + u32 alloc_sz = SZ_XMITFRAME_EXT + SZ_ALIGN_XMITFRAME_EXT; + +#if 0 /*def CONFIG_USE_USB_BUFFER_ALLOC_TX*/ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct usb_device *pusbd = dvobj_to_usb(dvobj)->pusbdev; + + pxframe->prealloc_buf_addr = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxframe->dma_transfer_addr); + if (pxframe->prealloc_buf_addr == NULL) { + RTW_ERR("%s prealloc_buf_addr failed\n", __func__); + rtw_warn_on(1); + return _FAIL; + } + pxframe->buf_addr = pxframe->prealloc_buf_addr; +#else + pxframe->prealloc_buf_addr = rtw_zmalloc(alloc_sz); + if (pxframe->prealloc_buf_addr == NULL) { + RTW_ERR("%s prealloc_buf_addr failed\n", __func__); + rtw_warn_on(1); + return _FAIL; + } + pxframe->buf_addr = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxframe->prealloc_buf_addr), SZ_ALIGN_XMITFRAME_EXT); +#endif + return _SUCCESS; +} + +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_frame *pxframe) +{ + u32 free_sz = SZ_XMITFRAME_EXT + SZ_ALIGN_XMITFRAME_EXT; + +#if 0 /*def CONFIG_USE_USB_BUFFER_ALLOC_TX*/ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct usb_device *pusbd = dvobj_to_usb(dvobj)->pusbdev; + + if (pxframe->prealloc_buf_addr) { + rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxframe->prealloc_buf_addr, pxframe->dma_transfer_addr); + pxframe->prealloc_buf_addr = NULL; + pxframe->buf_addr = NULL; + pxframe->dma_transfer_addr = 0; + } +#else + if (pxframe->prealloc_buf_addr) { + rtw_mfree(pxframe->prealloc_buf_addr, free_sz); + pxframe->prealloc_buf_addr = NULL; + pxframe->buf_addr = NULL; + } +#endif +} +#endif void dump_os_queue(void *sel, _adapter *padapter) { @@ -214,24 +265,10 @@ static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 os_qid) #endif/* #ifdef DBG_CONFIG_ERROR_RESET */ #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ } else { -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) - && MCC_STOP(padapter)) - return _FALSE; - } -#endif /* CONFIG_MCC_MODE */ return _TRUE; } return _FALSE; #else -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) - && MCC_STOP(padapter)) - return _FALSE; - } -#endif /* CONFIG_MCC_MODE */ return _TRUE; #endif } @@ -255,7 +292,7 @@ static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 os_qid) return _FALSE; } -void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt) +void rtw_os_pkt_complete(_adapter *padapter, struct sk_buff *pkt) { rtw_skb_free(pkt); } @@ -270,7 +307,7 @@ void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe) void rtw_os_xmit_schedule(_adapter *padapter) { -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#if 0 /*defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/ _adapter *pri_adapter; if (!padapter) @@ -281,8 +318,7 @@ void rtw_os_xmit_schedule(_adapter *padapter) _rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema); -#else - _irqL irqL; +#elif defined(CONFIG_PCI_HCI) || defined(CONFIG_USB_HCI) struct xmit_priv *pxmitpriv; if (!padapter) @@ -290,55 +326,55 @@ void rtw_os_xmit_schedule(_adapter *padapter) pxmitpriv = &padapter->xmitpriv; - _enter_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinlock_bh(&pxmitpriv->lock); if (rtw_txframes_pending(padapter)) - tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); - _exit_critical_bh(&pxmitpriv->lock, &irqL); + _rtw_spinunlock_bh(&pxmitpriv->lock); -#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE) + #if 0 /*defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)*/ if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) _rtw_up_sema(&padapter->xmitpriv.xmit_sema); -#endif + #endif #endif } -void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid) +void rtw_os_check_wakup_queue(_adapter *padapter, u16 os_qid) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - if (rtw_os_need_wake_queue(adapter, os_qid)) { + if (rtw_os_need_wake_queue(padapter, os_qid)) { if (DBG_DUMP_OS_QUEUE_CTL) - RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid); - netif_wake_subqueue(adapter->pnetdev, os_qid); + RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), os_qid); + netif_wake_subqueue(padapter->pnetdev, os_qid); } #else - if (rtw_os_need_wake_queue(adapter, 0)) { + if (rtw_os_need_wake_queue(padapter, 0)) { if (DBG_DUMP_OS_QUEUE_CTL) - RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(adapter)); - netif_wake_queue(adapter->pnetdev); + RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter)); + netif_wake_queue(padapter->pnetdev); } #endif } -bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid) +bool rtw_os_check_stop_queue(_adapter *padapter, u16 os_qid) { bool busy = _FALSE; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - if (rtw_os_need_stop_queue(adapter, os_qid)) { + if (rtw_os_need_stop_queue(padapter, os_qid)) { if (DBG_DUMP_OS_QUEUE_CTL) - RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid); - netif_stop_subqueue(adapter->pnetdev, os_qid); + RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), os_qid); + netif_stop_subqueue(padapter->pnetdev, os_qid); busy = _TRUE; } #else - if (rtw_os_need_stop_queue(adapter, 0)) { + if (rtw_os_need_stop_queue(padapter, 0)) { if (DBG_DUMP_OS_QUEUE_CTL) - RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(adapter)); - rtw_netif_stop_queue(adapter->pnetdev); + RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(padapter)); + rtw_netif_stop_queue(padapter->pnetdev); busy = _TRUE; } #endif @@ -371,7 +407,7 @@ void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed) #endif } -int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) +int _rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -389,11 +425,7 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) } DBG_COUNTER(padapter->tx_logs.os_tx); - if ((rtw_if_up(padapter) == _FALSE) -#ifdef CONFIG_LAYER2_ROAMING - &&(!padapter->mlmepriv.roam_network) -#endif - ){ + if (rtw_if_up(padapter) == _FALSE) { DBG_COUNTER(padapter->tx_logs.os_tx_err_up); #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); @@ -452,91 +484,232 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) return 0; } -#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL -int check_alibaba_meshpkt(struct sk_buff *skb) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) +/* copy from skbuff.c to be compatible with old kernel */ +static void kfree_skb_list(struct sk_buff *segs) { - u16 protocol; - - if (skb) - return (htons(skb->protocol) == ETH_P_ALL); - - return _FALSE; -} + while (segs) { + struct sk_buff *next = segs->next; -s32 rtw_alibaba_mesh_xmit_entry(_pkt *pkt, struct net_device *ndev) -{ - u16 frame_ctl; - - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct pkt_file pktfile; - struct rtw_ieee80211_hdr *pwlanhdr; - struct pkt_attrib *pattrib; - struct xmit_frame *pmgntframe; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - unsigned char *pframe; - struct sk_buff *skb = (struct sk_buff *)pkt; - int len = skb->len; - - rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - goto fail; - return -1; + kfree_skb(segs); + segs = next; } - - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - _rtw_open_pktfile(pkt, &pktfile); - _rtw_pktfile_read(&pktfile, pframe, len); - - pattrib->type = pframe[0] & 0x0C; - pattrib->subtype = pframe[0] & 0xF0; - pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); - pattrib->rate = MGN_24M; - pattrib->pktlen = len; - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; - - RTW_DBG_DUMP("rtw_alibaba_mesh_xmit_entry payload:", skb->data, len); - - pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(padapter, pmgntframe); - -fail: - rtw_skb_free(skb); - return 0; } #endif -int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) +netdev_tx_t rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev) +#else +int rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev) +#endif { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); int ret = 0; if (pkt) { -#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL - if (check_alibaba_meshpkt(pkt)) { - return rtw_alibaba_mesh_xmit_entry(pkt, pnetdev); - } -#endif if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev); #endif } else { +#ifdef CONFIG_RTW_NETIF_SG + /* After turning on SG, net stack may (0.0025%) TX + * strange skb that is skb_has_frag_list() but linear + * (i.e. skb_is_nonlinear() is false). This is out of + * our expectation, so I free fragment list to be + * compatible with our design. + */ + if (skb_has_frag_list(pkt)) { + if (!skb_is_nonlinear(pkt)) { + kfree_skb_list(skb_shinfo(pkt)->frag_list); + skb_shinfo(pkt)->frag_list = NULL; + RTW_DBG("%s:%d free frag list\n", __func__, __LINE__); + } else { + RTW_DBG("%s:%d nonlinear frag list\n", __func__, __LINE__); + } + } +#endif rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize); - ret = _rtw_xmit_entry(pkt, pnetdev); +#ifdef CONFIG_TX_SKB_ORPHAN + skb_orphan(pkt); +#endif + ret = rtw_os_tx(pkt, pnetdev); } } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) + return (ret == 0) ? NETDEV_TX_OK : NETDEV_TX_BUSY; +#else return ret; +#endif +} + + + +#ifdef RTW_PHL_TX +int rtw_os_is_adapter_ready(_adapter *padapter, struct sk_buff *pkt) +{ + + if (padapter->registrypriv.mp_mode) { + RTW_INFO("MP_TX_DROP_OS_FRAME\n"); + return _FALSE; + } + + DBG_COUNTER(padapter->tx_logs.os_tx); + + if (rtw_if_up(padapter) == _FALSE) { + PHLTX_LOG; + DBG_COUNTER(padapter->tx_logs.os_tx_err_up); + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); + #endif + return _FALSE; + } + + if (IS_CH_WAITING(adapter_to_rfctl(padapter))){ + PHLTX_LOG; + return _FALSE; + } + + if (rtw_linked_check(padapter) == _FALSE){ + PHLTX_LOG; + return _FALSE; + } + + return _TRUE; +} + +int rtw_os_tx(struct sk_buff *pkt, _nic_hdl pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u16 os_qid = 0; + s32 res = 0; + +#ifdef RTW_PHL_DBG_CMD + core_add_record(padapter, REC_TX_DATA, pkt); +#endif + + PHLTX_LOG; + + if (pkt->len == 0) + return 0; + + if ((rtw_os_is_adapter_ready(padapter, pkt) == _FALSE) +#ifdef CONFIG_LAYER2_ROAMING + && (!padapter->mlmepriv.roam_network) +#endif + ) + goto drop_packet; + + PHLTX_LOG; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + os_qid = skb_get_queue_mapping(pkt); +#endif + + PHLTX_LOG; + if (rtw_core_tx(padapter, &pkt, NULL, os_qid) == FAIL) + goto inc_drop_cnt; + + PHLTX_LOG; + + goto exit; + +drop_packet: + rtw_os_pkt_complete(padapter, pkt); + +inc_drop_cnt: + pxmitpriv->tx_drop++; + +exit: + return 0; +} +#endif + +#ifdef CONFIG_TX_AMSDU_SW_MODE +static void ieee8023_header_to_rfc1042(struct sk_buff *skb, int pads) +{ + void *data; + int pad; + __be16 len; + const int headroom = SNAP_SIZE + 2 + pads; + + if (!skb) + return; + + if (skb_headroom(skb) < headroom) { + RTW_WARN("%s: headroom=%d isn't enough\n", __func__, skb_headroom(skb)); + if (pskb_expand_head(skb, headroom, 0, GFP_ATOMIC)) { + RTW_ERR("%s: no headroom=%d for skb\n", + __func__, headroom); + return; + } + } + + data = skb_push(skb, headroom); + memset(data, 0, pads); + data += pads; + memmove(data, data + SNAP_SIZE + 2, 2 * ETH_ALEN); + data += 2 * ETH_ALEN; + len = cpu_to_be16(skb->len - pads - 2 * ETH_ALEN - 2); + memcpy(data, &len, 2); + memcpy(data + 2, rtw_rfc1042_header, SNAP_SIZE); +} + +void rtw_coalesce_tx_amsdu(_adapter *padapter, struct xmit_frame *pxframes[], + int xf_nr, bool amsdu, u32 *pktlen) +{ + struct xmit_frame *head_xframe; + struct xmit_frame *pxframe; + struct sk_buff *skb; + struct sk_buff *head_skb; + struct sk_buff **frag_tail; + int pads; + int i; + + /* prepare head xmitframe */ + head_xframe = pxframes[0]; + head_skb = head_xframe->pkt; + + ieee8023_header_to_rfc1042(head_skb, 0); + + frag_tail = &skb_shinfo(head_skb)->frag_list; + while (*frag_tail) + frag_tail = &(*frag_tail)->next; + + for (i = 1; i < xf_nr; i++) { + pxframe = pxframes[i]; + skb = pxframe->pkt; + + if (head_skb->len & 0x03) + pads = 4 - (head_skb->len & 0x03); + else + pads = 0; + + ieee8023_header_to_rfc1042(skb, pads); + + /* free sk accounting to have TP like doing skb_linearize() */ + if (skb->destructor) + skb_orphan(skb); + + /* add this skb to head_skb */ + head_skb->len += skb->len; + head_skb->data_len += skb->len; + *frag_tail = skb; + while (*frag_tail) + frag_tail = &(*frag_tail)->next; + + /* free this xframe */ + pxframe->pkt = NULL; /* head xframe own */ + core_tx_free_xmitframe(padapter, pxframe); + } + + /* total skb length (includes all fragments) */ + *pktlen = head_skb->len; } +#endif /* CONFIG_TX_AMSDU_SW_MODE */ diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index a490028..b65fc90 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2019 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,53 +12,19 @@ * more details. * *****************************************************************************/ - - #define _OSDEP_SERVICE_C_ #include -#include - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)) -#define kthread_complete_and_exit(comp, code) complete_and_exit(comp, code) -#endif - -#define RT_TAG '1178' - -#ifdef DBG_MEMORY_LEAK -#ifdef PLATFORM_LINUX -atomic_t _malloc_cnt = ATOMIC_INIT(0); -atomic_t _malloc_size = ATOMIC_INIT(0); -#endif -#endif /* DBG_MEMORY_LEAK */ - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0) -MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver); -#endif - -#if defined(PLATFORM_LINUX) -/* -* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE -* @return: one of RTW_STATUS_CODE -*/ -inline int RTW_STATUS_CODE(int error_code) -{ - if (error_code >= 0) - return _SUCCESS; - switch (error_code) { - /* case -ETIMEDOUT: */ - /* return RTW_STATUS_TIMEDOUT; */ - default: - return _FAIL; - } -} -#else -inline int RTW_STATUS_CODE(int error_code) +#ifdef CONFIG_HWSIM +#include "rtw_hwsim_intf.h" +inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) { - return error_code; + skb->dev = ndev; + rtw_hwsim_medium_pre_netif_rx(skb); + return netif_rx(skb); } -#endif +#endif /* CONFIG_HWSIM */ u32 rtw_atoi(u8 *s) { @@ -81,337 +47,6 @@ u32 rtw_atoi(u8 *s) } -inline void *_rtw_vmalloc(u32 sz) -{ - void *pbuf; -#ifdef PLATFORM_LINUX - pbuf = vmalloc(sz); -#endif -#ifdef PLATFORM_FREEBSD - pbuf = malloc(sz, M_DEVBUF, M_NOWAIT); -#endif - -#ifdef PLATFORM_WINDOWS - NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG); -#endif - -#ifdef DBG_MEMORY_LEAK -#ifdef PLATFORM_LINUX - if (pbuf != NULL) { - atomic_inc(&_malloc_cnt); - atomic_add(sz, &_malloc_size); - } -#endif -#endif /* DBG_MEMORY_LEAK */ - - return pbuf; -} - -inline void *_rtw_zvmalloc(u32 sz) -{ - void *pbuf; -#ifdef PLATFORM_LINUX - pbuf = _rtw_vmalloc(sz); - if (pbuf != NULL) - memset(pbuf, 0, sz); -#endif -#ifdef PLATFORM_FREEBSD - pbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); -#endif -#ifdef PLATFORM_WINDOWS - NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG); - if (pbuf != NULL) - NdisFillMemory(pbuf, sz, 0); -#endif - - return pbuf; -} - -inline void _rtw_vmfree(void *pbuf, u32 sz) -{ -#ifdef PLATFORM_LINUX - vfree(pbuf); -#endif -#ifdef PLATFORM_FREEBSD - free(pbuf, M_DEVBUF); -#endif -#ifdef PLATFORM_WINDOWS - NdisFreeMemory(pbuf, sz, 0); -#endif - -#ifdef DBG_MEMORY_LEAK -#ifdef PLATFORM_LINUX - atomic_dec(&_malloc_cnt); - atomic_sub(sz, &_malloc_size); -#endif -#endif /* DBG_MEMORY_LEAK */ -} - -void *_rtw_malloc(u32 sz) -{ - void *pbuf = NULL; - -#ifdef PLATFORM_LINUX -#ifdef RTK_DMP_PLATFORM - if (sz > 0x4000) - pbuf = dvr_malloc(sz); - else -#endif - pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); - -#endif -#ifdef PLATFORM_FREEBSD - pbuf = malloc(sz, M_DEVBUF, M_NOWAIT); -#endif -#ifdef PLATFORM_WINDOWS - - NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG); - -#endif - -#ifdef DBG_MEMORY_LEAK -#ifdef PLATFORM_LINUX - if (pbuf != NULL) { - atomic_inc(&_malloc_cnt); - atomic_add(sz, &_malloc_size); - } -#endif -#endif /* DBG_MEMORY_LEAK */ - - return pbuf; - -} - - -void *_rtw_zmalloc(u32 sz) -{ -#ifdef PLATFORM_FREEBSD - return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); -#else /* PLATFORM_FREEBSD */ - void *pbuf = _rtw_malloc(sz); - - if (pbuf != NULL) { - -#ifdef PLATFORM_LINUX - memset(pbuf, 0, sz); -#endif - -#ifdef PLATFORM_WINDOWS - NdisFillMemory(pbuf, sz, 0); -#endif - - } - - return pbuf; -#endif /* PLATFORM_FREEBSD */ -} - -void _rtw_mfree(void *pbuf, u32 sz) -{ - -#ifdef PLATFORM_LINUX -#ifdef RTK_DMP_PLATFORM - if (sz > 0x4000) - dvr_free(pbuf); - else -#endif - kfree(pbuf); - -#endif -#ifdef PLATFORM_FREEBSD - free(pbuf, M_DEVBUF); -#endif -#ifdef PLATFORM_WINDOWS - - NdisFreeMemory(pbuf, sz, 0); - -#endif - -#ifdef DBG_MEMORY_LEAK -#ifdef PLATFORM_LINUX - atomic_dec(&_malloc_cnt); - atomic_sub(sz, &_malloc_size); -#endif -#endif /* DBG_MEMORY_LEAK */ - -} - -#ifdef PLATFORM_FREEBSD -/* review again */ -struct sk_buff *dev_alloc_skb(unsigned int size) -{ - struct sk_buff *skb = NULL; - u8 *data = NULL; - - /* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */ - skb = _rtw_malloc(sizeof(struct sk_buff)); - if (!skb) - goto out; - data = _rtw_malloc(size); - if (!data) - goto nodata; - - skb->head = (unsigned char *)data; - skb->data = (unsigned char *)data; - skb->tail = (unsigned char *)data; - skb->end = (unsigned char *)data + size; - skb->len = 0; - /* printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); */ - -out: - return skb; -nodata: - _rtw_mfree(skb, sizeof(struct sk_buff)); - skb = NULL; - goto out; - -} - -void dev_kfree_skb_any(struct sk_buff *skb) -{ - /* printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); */ - if (skb->head) - _rtw_mfree(skb->head, 0); - /* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */ - if (skb) - _rtw_mfree(skb, 0); -} -struct sk_buff *skb_clone(const struct sk_buff *skb) -{ - return NULL; -} - -#endif /* PLATFORM_FREEBSD */ - -inline struct sk_buff *_rtw_skb_alloc(u32 sz) -{ -#ifdef PLATFORM_LINUX - return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - return dev_alloc_skb(sz); -#endif /* PLATFORM_FREEBSD */ -} - -inline void _rtw_skb_free(struct sk_buff *skb) -{ - dev_kfree_skb_any(skb); -} - -inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) -{ -#ifdef PLATFORM_LINUX - return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - return NULL; -#endif /* PLATFORM_FREEBSD */ -} - -inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) -{ -#ifdef PLATFORM_LINUX - return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - return skb_clone(skb); -#endif /* PLATFORM_FREEBSD */ -} -inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb) -{ -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) - return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); -#else - return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); -#endif -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - return NULL; -#endif /* PLATFORM_FREEBSD */ -} - -inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) -{ -#if defined(PLATFORM_LINUX) - skb->dev = ndev; - return netif_rx(skb); -#elif defined(PLATFORM_FREEBSD) - return (*ndev->if_input)(ndev, skb); -#else - rtw_warn_on(1); - return -1; -#endif -} - -#ifdef CONFIG_RTW_NAPI -inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb) -{ -#if defined(PLATFORM_LINUX) - skb->dev = ndev; - return netif_receive_skb(skb); -#else - rtw_warn_on(1); - return -1; -#endif -} - -#ifdef CONFIG_RTW_GRO -inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb) -{ -#if defined(PLATFORM_LINUX) - return napi_gro_receive(napi, skb); -#else - rtw_warn_on(1); - return -1; -#endif -} -#endif /* CONFIG_RTW_GRO */ -#endif /* CONFIG_RTW_NAPI */ - -void _rtw_skb_queue_purge(struct sk_buff_head *list) -{ - struct sk_buff *skb; - - while ((skb = skb_dequeue(list)) != NULL) - _rtw_skb_free(skb); -} - -#ifdef CONFIG_USB_HCI -inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma) -{ -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); -#else - return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); -#endif -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - return malloc(size, M_USBDEV, M_NOWAIT | M_ZERO); -#endif /* PLATFORM_FREEBSD */ -} -inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma) -{ -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - usb_free_coherent(dev, size, addr, dma); -#else - usb_buffer_free(dev, size, addr, dma); -#endif -#endif /* PLATFORM_LINUX */ - -#ifdef PLATFORM_FREEBSD - free(addr, M_USBDEV); -#endif /* PLATFORM_FREEBSD */ -} -#endif /* CONFIG_USB_HCI */ - #if defined(DBG_MEM_ALLOC) struct rtw_mem_stat { @@ -545,7 +180,7 @@ void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 s } #ifndef SIZE_MAX - #define SIZE_MAX (~(size_t)0) +#define SIZE_MAX (~(size_t)0) #endif struct mstat_sniff_rule { @@ -555,7 +190,7 @@ struct mstat_sniff_rule { }; struct mstat_sniff_rule mstat_sniff_rules[] = { - {MSTAT_TYPE_PHY, 4097, SIZE_MAX}, + {MSTAT_TYPE_VIR, 32, 32}, }; int mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule); @@ -674,6 +309,20 @@ inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const ch ); } +inline void dbg_rtw_skb_mstat_aid(struct sk_buff *skb_head, const enum mstat_f flags, enum mstat_status status) +{ + unsigned int truesize = 0; + struct sk_buff *skb; + + if (!skb_head) + return; + + rtw_mstat_update(flags, status, skb_head->truesize); + + skb_walk_frags(skb_head, skb) + rtw_mstat_update(flags, status, skb->truesize); +} + inline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line) { struct sk_buff *skb; @@ -703,13 +352,9 @@ inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, cons if (match_mstat_sniff_rules(flags, truesize)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); - _rtw_skb_free(skb); + dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_FREE); - rtw_mstat_update( - flags - , MSTAT_FREE - , truesize - ); + _rtw_skb_free(skb); } inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line) @@ -756,27 +401,21 @@ inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f return skb_cl; } -inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +inline int dbg_rtw_skb_linearize(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) { + unsigned int truesize = 0; int ret; - unsigned int truesize = skb->truesize; - if (match_mstat_sniff_rules(flags, truesize)) - RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); + dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_FREE); - ret = _rtw_netif_rx(ndev, skb); + ret = _rtw_skb_linearize(skb); - rtw_mstat_update( - flags - , MSTAT_FREE - , truesize - ); + dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_ALLOC_SUCCESS); return ret; } -#ifdef CONFIG_RTW_NAPI -inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) { int ret; unsigned int truesize = skb->truesize; @@ -784,7 +423,7 @@ inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const e if (match_mstat_sniff_rules(flags, truesize)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); - ret = _rtw_netif_receive_skb(ndev, skb); + ret = _rtw_netif_rx(ndev, skb); rtw_mstat_update( flags @@ -795,8 +434,8 @@ inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const e return ret; } -#ifdef CONFIG_RTW_GRO -inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +#ifdef CONFIG_RTW_NAPI +inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) { int ret; unsigned int truesize = skb->truesize; @@ -804,2136 +443,196 @@ inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk if (match_mstat_sniff_rules(flags, truesize)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); - ret = _rtw_napi_gro_receive(napi, skb); - - rtw_mstat_update( - flags - , MSTAT_FREE - , truesize - ); - - return ret; -} -#endif /* CONFIG_RTW_GRO */ -#endif /* CONFIG_RTW_NAPI */ - -inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line) -{ - struct sk_buff *skb; - - while ((skb = skb_dequeue(list)) != NULL) - dbg_rtw_skb_free(skb, flags, func, line); -} - -#ifdef CONFIG_USB_HCI -inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line) -{ - void *p; - - if (match_mstat_sniff_rules(flags, size)) - RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); - - p = _rtw_usb_buffer_alloc(dev, size, dma); - - rtw_mstat_update( - flags - , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL - , size - ); - - return p; -} - -inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line) -{ - - if (match_mstat_sniff_rules(flags, size)) - RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); - - _rtw_usb_buffer_free(dev, size, addr, dma); + ret = _rtw_netif_receive_skb(ndev, skb); rtw_mstat_update( flags , MSTAT_FREE - , size - ); -} -#endif /* CONFIG_USB_HCI */ - -#endif /* defined(DBG_MEM_ALLOC) */ - -void *rtw_malloc2d(int h, int w, size_t size) -{ - int j; - - void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size); - if (a == NULL) { - RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__); - return NULL; - } - - for (j = 0; j < h; j++) - a[j] = ((char *)(a + h)) + j * w * size; - - return a; -} - -void rtw_mfree2d(void *pbuf, int h, int w, int size) -{ - rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size); -} - -inline void rtw_os_pkt_free(_pkt *pkt) -{ -#if defined(PLATFORM_LINUX) - rtw_skb_free(pkt); -#elif defined(PLATFORM_FREEBSD) - m_freem(pkt); -#else - #error "TBD\n" -#endif -} - -inline _pkt *rtw_os_pkt_copy(_pkt *pkt) -{ -#if defined(PLATFORM_LINUX) - return rtw_skb_copy(pkt); -#elif defined(PLATFORM_FREEBSD) - return m_dup(pkt, M_NOWAIT); -#else - #error "TBD\n" -#endif -} - -inline void *rtw_os_pkt_data(_pkt *pkt) -{ -#if defined(PLATFORM_LINUX) - return pkt->data; -#elif defined(PLATFORM_FREEBSD) - return pkt->m_data; -#else - #error "TBD\n" -#endif -} - -inline u32 rtw_os_pkt_len(_pkt *pkt) -{ -#if defined(PLATFORM_LINUX) - return pkt->len; -#elif defined(PLATFORM_FREEBSD) - return pkt->m_pkthdr.len; -#else - #error "TBD\n" -#endif -} - -void _rtw_memcpy(void *dst, const void *src, u32 sz) -{ - -#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) - - memcpy(dst, src, sz); - -#endif - -#ifdef PLATFORM_WINDOWS - - NdisMoveMemory(dst, src, sz); - -#endif - -} - -inline void _rtw_memmove(void *dst, const void *src, u32 sz) -{ -#if defined(PLATFORM_LINUX) - memmove(dst, src, sz); -#else - #error "TBD\n" -#endif -} - -int _rtw_memcmp(const void *dst, const void *src, u32 sz) -{ - -#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) - /* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */ - - if (!(memcmp(dst, src, sz))) - return _TRUE; - else - return _FALSE; -#endif - - -#ifdef PLATFORM_WINDOWS - /* under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 */ - - if (NdisEqualMemory(dst, src, sz)) - return _TRUE; - else - return _FALSE; - -#endif - - - -} - -int _rtw_memcmp2(const void *dst, const void *src, u32 sz) -{ - const unsigned char *p1 = dst, *p2 = src; - - if (sz == 0) - return 0; - - while (*p1 == *p2) { - p1++; - p2++; - sz--; - if (sz == 0) - return 0; - } - - return *p1 - *p2; -} - -void _rtw_memset(void *pbuf, int c, u32 sz) -{ - -#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) - - memset(pbuf, c, sz); - -#endif - -#ifdef PLATFORM_WINDOWS -#if 0 - NdisZeroMemory(pbuf, sz); - if (c != 0) - memset(pbuf, c, sz); -#else - NdisFillMemory(pbuf, sz, c); -#endif -#endif - -} - -#ifdef PLATFORM_FREEBSD -static inline void __list_add(_list *pnew, _list *pprev, _list *pnext) -{ - pnext->prev = pnew; - pnew->next = pnext; - pnew->prev = pprev; - pprev->next = pnew; -} -#endif /* PLATFORM_FREEBSD */ - - -void _rtw_init_listhead(_list *list) -{ - -#ifdef PLATFORM_LINUX - - INIT_LIST_HEAD(list); - -#endif - -#ifdef PLATFORM_FREEBSD - list->next = list; - list->prev = list; -#endif -#ifdef PLATFORM_WINDOWS - - NdisInitializeListHead(list); - -#endif - -} - - -/* -For the following list_xxx operations, -caller must guarantee the atomic context. -Otherwise, there will be racing condition. -*/ -u32 rtw_is_list_empty(_list *phead) -{ - -#ifdef PLATFORM_LINUX - - if (list_empty(phead)) - return _TRUE; - else - return _FALSE; - -#endif -#ifdef PLATFORM_FREEBSD - - if (phead->next == phead) - return _TRUE; - else - return _FALSE; - -#endif - - -#ifdef PLATFORM_WINDOWS - - if (IsListEmpty(phead)) - return _TRUE; - else - return _FALSE; - -#endif - - -} - -void rtw_list_insert_head(_list *plist, _list *phead) -{ - -#ifdef PLATFORM_LINUX - list_add(plist, phead); -#endif - -#ifdef PLATFORM_FREEBSD - __list_add(plist, phead, phead->next); -#endif - -#ifdef PLATFORM_WINDOWS - InsertHeadList(phead, plist); -#endif -} - -void rtw_list_insert_tail(_list *plist, _list *phead) -{ - -#ifdef PLATFORM_LINUX - - list_add_tail(plist, phead); - -#endif -#ifdef PLATFORM_FREEBSD - - __list_add(plist, phead->prev, phead); - -#endif -#ifdef PLATFORM_WINDOWS - - InsertTailList(phead, plist); - -#endif - -} - -inline void rtw_list_splice(_list *list, _list *head) -{ -#ifdef PLATFORM_LINUX - list_splice(list, head); -#else - #error "TBD\n" -#endif -} - -inline void rtw_list_splice_init(_list *list, _list *head) -{ -#ifdef PLATFORM_LINUX - list_splice_init(list, head); -#else - #error "TBD\n" -#endif -} - -inline void rtw_list_splice_tail(_list *list, _list *head) -{ -#ifdef PLATFORM_LINUX - #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) - if (!list_empty(list)) - __list_splice(list, head); - #else - list_splice_tail(list, head); - #endif -#else - #error "TBD\n" -#endif -} - -inline void rtw_hlist_head_init(rtw_hlist_head *h) -{ -#ifdef PLATFORM_LINUX - INIT_HLIST_HEAD(h); -#else - #error "TBD\n" -#endif -} - -inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h) -{ -#ifdef PLATFORM_LINUX - hlist_add_head(n, h); -#else - #error "TBD\n" -#endif -} - -inline void rtw_hlist_del(rtw_hlist_node *n) -{ -#ifdef PLATFORM_LINUX - hlist_del(n); -#else - #error "TBD\n" -#endif -} - -inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h) -{ -#ifdef PLATFORM_LINUX - hlist_add_head_rcu(n, h); -#else - #error "TBD\n" -#endif -} - -inline void rtw_hlist_del_rcu(rtw_hlist_node *n) -{ -#ifdef PLATFORM_LINUX - hlist_del_rcu(n); -#else - #error "TBD\n" -#endif -} - -void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx) -{ - _adapter *adapter = (_adapter *)padapter; - -#ifdef PLATFORM_LINUX - _init_timer(ptimer, adapter->pnetdev, pfunc, ctx); -#endif -#ifdef PLATFORM_FREEBSD - _init_timer(ptimer, adapter->pifp, pfunc, ctx); -#endif -#ifdef PLATFORM_WINDOWS - _init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx); -#endif -} - -/* - -Caller must check if the list is empty before calling rtw_list_delete - -*/ - - -void _rtw_init_sema(_sema *sema, int init_val) -{ - -#ifdef PLATFORM_LINUX - - sema_init(sema, init_val); - -#endif -#ifdef PLATFORM_FREEBSD - sema_init(sema, init_val, "rtw_drv"); -#endif -#ifdef PLATFORM_OS_XP - - KeInitializeSemaphore(sema, init_val, SEMA_UPBND); /* count=0; */ - -#endif - -#ifdef PLATFORM_OS_CE - if (*sema == NULL) - *sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL); -#endif - -} - -void _rtw_free_sema(_sema *sema) -{ -#ifdef PLATFORM_FREEBSD - sema_destroy(sema); -#endif -#ifdef PLATFORM_OS_CE - CloseHandle(*sema); -#endif - -} - -void _rtw_up_sema(_sema *sema) -{ - -#ifdef PLATFORM_LINUX - - up(sema); - -#endif -#ifdef PLATFORM_FREEBSD - sema_post(sema); -#endif -#ifdef PLATFORM_OS_XP - - KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1, FALSE); - -#endif - -#ifdef PLATFORM_OS_CE - ReleaseSemaphore(*sema, 1, NULL); -#endif -} - -u32 _rtw_down_sema(_sema *sema) -{ - -#ifdef PLATFORM_LINUX - - if (down_interruptible(sema)) - return _FAIL; - else - return _SUCCESS; - -#endif -#ifdef PLATFORM_FREEBSD - sema_wait(sema); - return _SUCCESS; -#endif -#ifdef PLATFORM_OS_XP - - if (STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL)) - return _SUCCESS; - else - return _FAIL; -#endif - -#ifdef PLATFORM_OS_CE - if (WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE)) - return _SUCCESS; - else - return _FAIL; -#endif -} - -inline void thread_exit(_completion *comp) -{ -#ifdef PLATFORM_LINUX - kthread_complete_and_exit(comp, 0); -#endif - -#ifdef PLATFORM_FREEBSD - printf("%s", "RTKTHREAD_exit"); -#endif - -#ifdef PLATFORM_OS_CE - ExitThread(STATUS_SUCCESS); -#endif - -#ifdef PLATFORM_OS_XP - PsTerminateSystemThread(STATUS_SUCCESS); -#endif -} - -inline void _rtw_init_completion(_completion *comp) -{ -#ifdef PLATFORM_LINUX - init_completion(comp); -#endif -} -inline void _rtw_wait_for_comp_timeout(_completion *comp) -{ -#ifdef PLATFORM_LINUX - wait_for_completion_timeout(comp, msecs_to_jiffies(3000)); -#endif -} -inline void _rtw_wait_for_comp(_completion *comp) -{ -#ifdef PLATFORM_LINUX - wait_for_completion(comp); -#endif -} - -void _rtw_mutex_init(_mutex *pmutex) -{ -#ifdef PLATFORM_LINUX - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) - mutex_init(pmutex); -#else - init_MUTEX(pmutex); -#endif - -#endif -#ifdef PLATFORM_FREEBSD - mtx_init(pmutex, "", NULL, MTX_DEF | MTX_RECURSE); -#endif -#ifdef PLATFORM_OS_XP - - KeInitializeMutex(pmutex, 0); - -#endif - -#ifdef PLATFORM_OS_CE - *pmutex = CreateMutex(NULL, _FALSE, NULL); -#endif -} - -void _rtw_mutex_free(_mutex *pmutex); -void _rtw_mutex_free(_mutex *pmutex) -{ -#ifdef PLATFORM_LINUX - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) - mutex_destroy(pmutex); -#else -#endif - -#ifdef PLATFORM_FREEBSD - sema_destroy(pmutex); -#endif - -#endif - -#ifdef PLATFORM_OS_XP - -#endif - -#ifdef PLATFORM_OS_CE - -#endif -} - -void _rtw_spinlock_init(_lock *plock) -{ - -#ifdef PLATFORM_LINUX - - spin_lock_init(plock); - -#endif -#ifdef PLATFORM_FREEBSD - mtx_init(plock, "", NULL, MTX_DEF | MTX_RECURSE); -#endif -#ifdef PLATFORM_WINDOWS - - NdisAllocateSpinLock(plock); - -#endif - -} - -void _rtw_spinlock_free(_lock *plock) -{ -#ifdef PLATFORM_FREEBSD - mtx_destroy(plock); -#endif - -#ifdef PLATFORM_WINDOWS - - NdisFreeSpinLock(plock); - -#endif - -} -#ifdef PLATFORM_FREEBSD -extern PADAPTER prtw_lock; - -void rtw_mtx_lock(_lock *plock) -{ - if (prtw_lock) - mtx_lock(&prtw_lock->glock); - else - printf("%s prtw_lock==NULL", __FUNCTION__); -} -void rtw_mtx_unlock(_lock *plock) -{ - if (prtw_lock) - mtx_unlock(&prtw_lock->glock); - else - printf("%s prtw_lock==NULL", __FUNCTION__); - -} -#endif /* PLATFORM_FREEBSD */ - - -void _rtw_spinlock(_lock *plock) -{ - -#ifdef PLATFORM_LINUX - - spin_lock(plock); - -#endif -#ifdef PLATFORM_FREEBSD - mtx_lock(plock); -#endif -#ifdef PLATFORM_WINDOWS - - NdisAcquireSpinLock(plock); - -#endif - -} - -void _rtw_spinunlock(_lock *plock) -{ - -#ifdef PLATFORM_LINUX - - spin_unlock(plock); - -#endif -#ifdef PLATFORM_FREEBSD - mtx_unlock(plock); -#endif -#ifdef PLATFORM_WINDOWS - - NdisReleaseSpinLock(plock); - -#endif -} - - -void _rtw_spinlock_ex(_lock *plock) -{ - -#ifdef PLATFORM_LINUX - - spin_lock(plock); - -#endif -#ifdef PLATFORM_FREEBSD - mtx_lock(plock); -#endif -#ifdef PLATFORM_WINDOWS - - NdisDprAcquireSpinLock(plock); - -#endif - -} - -void _rtw_spinunlock_ex(_lock *plock) -{ - -#ifdef PLATFORM_LINUX - - spin_unlock(plock); - -#endif -#ifdef PLATFORM_FREEBSD - mtx_unlock(plock); -#endif -#ifdef PLATFORM_WINDOWS - - NdisDprReleaseSpinLock(plock); - -#endif -} - - - -void _rtw_init_queue(_queue *pqueue) -{ - _rtw_init_listhead(&(pqueue->queue)); - _rtw_spinlock_init(&(pqueue->lock)); -} - -void _rtw_deinit_queue(_queue *pqueue) -{ - _rtw_spinlock_free(&(pqueue->lock)); -} - -u32 _rtw_queue_empty(_queue *pqueue) -{ - return rtw_is_list_empty(&(pqueue->queue)); -} - - -u32 rtw_end_of_queue_search(_list *head, _list *plist) -{ - if (head == plist) - return _TRUE; - else - return _FALSE; -} - - -systime _rtw_get_current_time(void) -{ - -#ifdef PLATFORM_LINUX - return jiffies; -#endif -#ifdef PLATFORM_FREEBSD - struct timeval tvp; - getmicrotime(&tvp); - return tvp.tv_sec; -#endif -#ifdef PLATFORM_WINDOWS - LARGE_INTEGER SystemTime; - NdisGetCurrentSystemTime(&SystemTime); - return SystemTime.LowPart;/* count of 100-nanosecond intervals */ -#endif -} - -inline u32 _rtw_systime_to_ms(systime stime) -{ -#ifdef PLATFORM_LINUX - return jiffies_to_msecs(stime); -#endif -#ifdef PLATFORM_FREEBSD - return stime * 1000; -#endif -#ifdef PLATFORM_WINDOWS - return stime / 10000 ; -#endif -} - -inline systime _rtw_ms_to_systime(u32 ms) -{ -#ifdef PLATFORM_LINUX - return msecs_to_jiffies(ms); -#endif -#ifdef PLATFORM_FREEBSD - return ms / 1000; -#endif -#ifdef PLATFORM_WINDOWS - return ms * 10000 ; -#endif -} - -inline systime _rtw_us_to_systime(u32 us) -{ -#ifdef PLATFORM_LINUX - return usecs_to_jiffies(us); -#else - #error "TBD\n" -#endif -} - -/* the input parameter start use the same unit as returned by rtw_get_current_time */ -inline s32 _rtw_get_passing_time_ms(systime start) -{ - return _rtw_systime_to_ms(_rtw_get_current_time() - start); -} - -inline s32 _rtw_get_remaining_time_ms(systime end) -{ - return _rtw_systime_to_ms(end - _rtw_get_current_time()); -} - -inline s32 _rtw_get_time_interval_ms(systime start, systime end) -{ - return _rtw_systime_to_ms(end - start); -} - -inline bool _rtw_time_after(systime a, systime b) -{ -#ifdef PLATFORM_LINUX - return time_after(a, b); -#else - #error "TBD\n" -#endif -} - -sysptime rtw_sptime_get(void) -{ - /* CLOCK_MONOTONIC */ -#ifdef PLATFORM_LINUX - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0)) - struct timespec64 cur; - - ktime_get_ts64(&cur); - return timespec64_to_ktime(cur); - #else - struct timespec cur; - - ktime_get_ts(&cur); - return timespec_to_ktime(cur); - #endif -#else - #error "TBD\n" -#endif -} - -sysptime rtw_sptime_set(s64 secs, const u32 nsecs) -{ -#ifdef PLATFORM_LINUX - return ktime_set(secs, nsecs); -#else - #error "TBD\n" -#endif -} - -sysptime rtw_sptime_zero(void) -{ -#ifdef PLATFORM_LINUX - return ktime_set(0, 0); -#else - #error "TBD\n" -#endif -} - -/* - * cmp1 < cmp2: return <0 - * cmp1 == cmp2: return 0 - * cmp1 > cmp2: return >0 - */ -int rtw_sptime_cmp(const sysptime cmp1, const sysptime cmp2) -{ -#ifdef PLATFORM_LINUX - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - return ktime_compare(cmp1, cmp2); - #else - if (cmp1.tv64 < cmp2.tv64) - return -1; - if (cmp1.tv64 > cmp2.tv64) - return 1; - return 0; - #endif -#else - #error "TBD\n" -#endif -} - -bool rtw_sptime_eql(const sysptime cmp1, const sysptime cmp2) -{ -#ifdef PLATFORM_LINUX - return rtw_sptime_cmp(cmp1, cmp2) == 0; -#else - #error "TBD\n" -#endif -} - -bool rtw_sptime_is_zero(const sysptime sptime) -{ -#ifdef PLATFORM_LINUX - return rtw_sptime_cmp(sptime, rtw_sptime_zero()) == 0; -#else - #error "TBD\n" -#endif -} - -/* - * sub = lhs - rhs, in normalized form - */ -sysptime rtw_sptime_sub(const sysptime lhs, const sysptime rhs) -{ -#ifdef PLATFORM_LINUX - return ktime_sub(lhs, rhs); -#else - #error "TBD\n" -#endif -} - -/* - * add = lhs + rhs, in normalized form - */ -sysptime rtw_sptime_add(const sysptime lhs, const sysptime rhs) -{ -#ifdef PLATFORM_LINUX - return ktime_add(lhs, rhs); -#else - #error "TBD\n" -#endif -} - -s64 rtw_sptime_to_ms(const sysptime sptime) -{ -#ifdef PLATFORM_LINUX - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - return ktime_to_ms(sptime); - #else - struct timeval tv = ktime_to_timeval(sptime); - - return (s64) tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; - #endif -#else - #error "TBD\n" -#endif -} - -sysptime rtw_ms_to_sptime(u64 ms) -{ -#ifdef PLATFORM_LINUX - return ns_to_ktime(ms * NSEC_PER_MSEC); -#else - #error "TBD\n" -#endif -} - -s64 rtw_sptime_to_us(const sysptime sptime) -{ -#ifdef PLATFORM_LINUX - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) - return ktime_to_us(sptime); - #else - struct timeval tv = ktime_to_timeval(sptime); - - return (s64) tv.tv_sec * USEC_PER_SEC + tv.tv_usec; - #endif -#else - #error "TBD\n" -#endif -} - -sysptime rtw_us_to_sptime(u64 us) -{ -#ifdef PLATFORM_LINUX - return ns_to_ktime(us * NSEC_PER_USEC); -#else - #error "TBD\n" -#endif -} - -s64 rtw_sptime_to_ns(const sysptime sptime) -{ -#ifdef PLATFORM_LINUX - return ktime_to_ns(sptime); -#else - #error "TBD\n" -#endif -} - -sysptime rtw_ns_to_sptime(u64 ns) -{ -#ifdef PLATFORM_LINUX - return ns_to_ktime(ns); -#else - #error "TBD\n" -#endif -} - -s64 rtw_sptime_diff_ms(const sysptime start, const sysptime end) -{ - sysptime diff; - - diff = rtw_sptime_sub(end, start); - - return rtw_sptime_to_ms(diff); -} - -s64 rtw_sptime_pass_ms(const sysptime start) -{ - sysptime cur, diff; - - cur = rtw_sptime_get(); - diff = rtw_sptime_sub(cur, start); - - return rtw_sptime_to_ms(diff); -} - -s64 rtw_sptime_diff_us(const sysptime start, const sysptime end) -{ - sysptime diff; - - diff = rtw_sptime_sub(end, start); - - return rtw_sptime_to_us(diff); -} - -s64 rtw_sptime_pass_us(const sysptime start) -{ - sysptime cur, diff; - - cur = rtw_sptime_get(); - diff = rtw_sptime_sub(cur, start); - - return rtw_sptime_to_us(diff); -} - -s64 rtw_sptime_diff_ns(const sysptime start, const sysptime end) -{ - sysptime diff; - - diff = rtw_sptime_sub(end, start); - - return rtw_sptime_to_ns(diff); -} - -s64 rtw_sptime_pass_ns(const sysptime start) -{ - sysptime cur, diff; - - cur = rtw_sptime_get(); - diff = rtw_sptime_sub(cur, start); - - return rtw_sptime_to_ns(diff); -} - -void rtw_sleep_schedulable(int ms) -{ - -#ifdef PLATFORM_LINUX - - u32 delta; - - delta = (ms * HZ) / 1000; /* (ms) */ - if (delta == 0) { - delta = 1;/* 1 ms */ - } - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(delta); - return; - -#endif -#ifdef PLATFORM_FREEBSD - DELAY(ms * 1000); - return ; -#endif - -#ifdef PLATFORM_WINDOWS - - NdisMSleep(ms * 1000); /* (us)*1000=(ms) */ - -#endif - -} - - -void rtw_msleep_os(int ms) -{ - -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) - if (ms < 20) { - unsigned long us = ms * 1000UL; - usleep_range(us, us + 1000UL); - } else -#endif - msleep((unsigned int)ms); - -#endif -#ifdef PLATFORM_FREEBSD - /* Delay for delay microseconds */ - DELAY(ms * 1000); - return ; -#endif -#ifdef PLATFORM_WINDOWS - - NdisMSleep(ms * 1000); /* (us)*1000=(ms) */ - -#endif - - -} -void rtw_usleep_os(int us) -{ -#ifdef PLATFORM_LINUX - - /* msleep((unsigned int)us); */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) - usleep_range(us, us + 1); -#else - if (1 < (us / 1000)) - msleep(1); - else - msleep((us / 1000) + 1); -#endif -#endif - -#ifdef PLATFORM_FREEBSD - /* Delay for delay microseconds */ - DELAY(us); - - return ; -#endif -#ifdef PLATFORM_WINDOWS - - NdisMSleep(us); /* (us) */ - -#endif - - -} - - -#ifdef DBG_DELAY_OS -void _rtw_mdelay_os(int ms, const char *func, const int line) -{ -#if 0 - if (ms > 10) - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); - rtw_msleep_os(ms); - return; -#endif - - - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); - -#if defined(PLATFORM_LINUX) - - mdelay((unsigned long)ms); - -#elif defined(PLATFORM_WINDOWS) - - NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */ - -#endif - - -} -void _rtw_udelay_os(int us, const char *func, const int line) -{ - -#if 0 - if (us > 1000) { - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); - rtw_usleep_os(us); - return; - } -#endif - - - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); - - -#if defined(PLATFORM_LINUX) - - udelay((unsigned long)us); - -#elif defined(PLATFORM_WINDOWS) - - NdisStallExecution(us); /* (us) */ - -#endif - -} -#else -void rtw_mdelay_os(int ms) -{ - -#ifdef PLATFORM_LINUX - - mdelay((unsigned long)ms); - -#endif -#ifdef PLATFORM_FREEBSD - DELAY(ms * 1000); - return ; -#endif -#ifdef PLATFORM_WINDOWS - - NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */ - -#endif - - -} -void rtw_udelay_os(int us) -{ - -#ifdef PLATFORM_LINUX - - udelay((unsigned long)us); - -#endif -#ifdef PLATFORM_FREEBSD - /* Delay for delay microseconds */ - DELAY(us); - return ; -#endif -#ifdef PLATFORM_WINDOWS - - NdisStallExecution(us); /* (us) */ - -#endif - -} -#endif - -void rtw_yield_os(void) -{ -#ifdef PLATFORM_LINUX - yield(); -#endif -#ifdef PLATFORM_FREEBSD - yield(); -#endif -#ifdef PLATFORM_WINDOWS - SwitchToThread(); -#endif -} - -const char *_rtw_pwait_type_str[] = { - [RTW_PWAIT_TYPE_MSLEEP] = "MS", - [RTW_PWAIT_TYPE_USLEEP] = "US", - [RTW_PWAIT_TYPE_YIELD] = "Y", - [RTW_PWAIT_TYPE_MDELAY] = "MD", - [RTW_PWAIT_TYPE_UDELAY] = "UD", - [RTW_PWAIT_TYPE_NUM] = "unknown", -}; - -static void rtw_pwctx_yield(int us) -{ - rtw_yield_os(); -} - -static void (*const rtw_pwait_hdl[])(int)= { - [RTW_PWAIT_TYPE_MSLEEP] = rtw_msleep_os, - [RTW_PWAIT_TYPE_USLEEP] = rtw_usleep_os, - [RTW_PWAIT_TYPE_YIELD] = rtw_pwctx_yield, - [RTW_PWAIT_TYPE_MDELAY] = rtw_mdelay_os, - [RTW_PWAIT_TYPE_UDELAY] = rtw_udelay_os, -}; - -int rtw_pwctx_config(struct rtw_pwait_ctx *pwctx, enum rtw_pwait_type type, s32 time, s32 cnt_lmt) -{ - int ret = _FAIL; - - if (!RTW_PWAIT_TYPE_VALID(type)) - goto exit; - - pwctx->conf.type = type; - pwctx->conf.wait_time = time; - pwctx->conf.wait_cnt_lmt = cnt_lmt; - pwctx->wait_hdl = rtw_pwait_hdl[type]; - - ret = _SUCCESS; - -exit: - return ret; -} - -bool rtw_macaddr_is_larger(const u8 *a, const u8 *b) -{ - u32 va, vb; - - va = be32_to_cpu(*((u32 *)a)); - vb = be32_to_cpu(*((u32 *)b)); - if (va > vb) - return 1; - else if (va < vb) - return 0; - - return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4))); -} - -#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" -#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" -#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" -#ifdef CONFIG_WAKELOCK -static struct wake_lock rtw_suspend_lock; -static struct wake_lock rtw_suspend_traffic_lock; -static struct wake_lock rtw_suspend_resume_lock; -#elif defined(CONFIG_ANDROID_POWER) -static android_suspend_lock_t rtw_suspend_lock = { - .name = RTW_SUSPEND_LOCK_NAME -}; -static android_suspend_lock_t rtw_suspend_traffic_lock = { - .name = RTW_SUSPEND_TRAFFIC_LOCK_NAME -}; -static android_suspend_lock_t rtw_suspend_resume_lock = { - .name = RTW_SUSPEND_RESUME_LOCK_NAME -}; -#endif - -inline void rtw_suspend_lock_init(void) -{ -#ifdef CONFIG_WAKELOCK - wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); - wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME); - wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME); -#elif defined(CONFIG_ANDROID_POWER) - android_init_suspend_lock(&rtw_suspend_lock); - android_init_suspend_lock(&rtw_suspend_traffic_lock); - android_init_suspend_lock(&rtw_suspend_resume_lock); -#endif -} - -inline void rtw_suspend_lock_uninit(void) -{ -#ifdef CONFIG_WAKELOCK - wake_lock_destroy(&rtw_suspend_lock); - wake_lock_destroy(&rtw_suspend_traffic_lock); - wake_lock_destroy(&rtw_suspend_resume_lock); -#elif defined(CONFIG_ANDROID_POWER) - android_uninit_suspend_lock(&rtw_suspend_lock); - android_uninit_suspend_lock(&rtw_suspend_traffic_lock); - android_uninit_suspend_lock(&rtw_suspend_resume_lock); -#endif -} - -inline void rtw_lock_suspend(void) -{ -#ifdef CONFIG_WAKELOCK - wake_lock(&rtw_suspend_lock); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend(&rtw_suspend_lock); -#endif - -#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) - /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ -#endif -} - -inline void rtw_unlock_suspend(void) -{ -#ifdef CONFIG_WAKELOCK - wake_unlock(&rtw_suspend_lock); -#elif defined(CONFIG_ANDROID_POWER) - android_unlock_suspend(&rtw_suspend_lock); -#endif - -#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) - /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ -#endif -} - -inline void rtw_resume_lock_suspend(void) -{ -#ifdef CONFIG_WAKELOCK - wake_lock(&rtw_suspend_resume_lock); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend(&rtw_suspend_resume_lock); -#endif - -#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) - /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ -#endif -} - -inline void rtw_resume_unlock_suspend(void) -{ -#ifdef CONFIG_WAKELOCK - wake_unlock(&rtw_suspend_resume_lock); -#elif defined(CONFIG_ANDROID_POWER) - android_unlock_suspend(&rtw_suspend_resume_lock); -#endif - -#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) - /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ -#endif -} - -inline void rtw_lock_suspend_timeout(u32 timeout_ms) -{ -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); -#endif -} - - -inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) -{ -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); -#endif - /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ -} - -inline void rtw_set_bit(int nr, unsigned long *addr) -{ -#ifdef PLATFORM_LINUX - set_bit(nr, addr); -#else - #error "TBD\n"; -#endif -} - -inline void rtw_clear_bit(int nr, unsigned long *addr) -{ -#ifdef PLATFORM_LINUX - clear_bit(nr, addr); -#else - #error "TBD\n"; -#endif -} - -inline int rtw_test_and_clear_bit(int nr, unsigned long *addr) -{ -#ifdef PLATFORM_LINUX - return test_and_clear_bit(nr, addr); -#else - #error "TBD\n"; -#endif -} - -inline void ATOMIC_SET(ATOMIC_T *v, int i) -{ -#ifdef PLATFORM_LINUX - atomic_set(v, i); -#elif defined(PLATFORM_WINDOWS) - *v = i; /* other choice???? */ -#elif defined(PLATFORM_FREEBSD) - atomic_set_int(v, i); -#endif -} - -inline int ATOMIC_READ(ATOMIC_T *v) -{ -#ifdef PLATFORM_LINUX - return atomic_read(v); -#elif defined(PLATFORM_WINDOWS) - return *v; /* other choice???? */ -#elif defined(PLATFORM_FREEBSD) - return atomic_load_acq_32(v); -#endif -} - -inline void ATOMIC_ADD(ATOMIC_T *v, int i) -{ -#ifdef PLATFORM_LINUX - atomic_add(i, v); -#elif defined(PLATFORM_WINDOWS) - InterlockedAdd(v, i); -#elif defined(PLATFORM_FREEBSD) - atomic_add_int(v, i); -#endif -} -inline void ATOMIC_SUB(ATOMIC_T *v, int i) -{ -#ifdef PLATFORM_LINUX - atomic_sub(i, v); -#elif defined(PLATFORM_WINDOWS) - InterlockedAdd(v, -i); -#elif defined(PLATFORM_FREEBSD) - atomic_subtract_int(v, i); -#endif -} - -inline void ATOMIC_INC(ATOMIC_T *v) -{ -#ifdef PLATFORM_LINUX - atomic_inc(v); -#elif defined(PLATFORM_WINDOWS) - InterlockedIncrement(v); -#elif defined(PLATFORM_FREEBSD) - atomic_add_int(v, 1); -#endif -} - -inline void ATOMIC_DEC(ATOMIC_T *v) -{ -#ifdef PLATFORM_LINUX - atomic_dec(v); -#elif defined(PLATFORM_WINDOWS) - InterlockedDecrement(v); -#elif defined(PLATFORM_FREEBSD) - atomic_subtract_int(v, 1); -#endif -} - -inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) -{ -#ifdef PLATFORM_LINUX - return atomic_add_return(i, v); -#elif defined(PLATFORM_WINDOWS) - return InterlockedAdd(v, i); -#elif defined(PLATFORM_FREEBSD) - atomic_add_int(v, i); - return atomic_load_acq_32(v); -#endif -} - -inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) -{ -#ifdef PLATFORM_LINUX - return atomic_sub_return(i, v); -#elif defined(PLATFORM_WINDOWS) - return InterlockedAdd(v, -i); -#elif defined(PLATFORM_FREEBSD) - atomic_subtract_int(v, i); - return atomic_load_acq_32(v); -#endif -} - -inline int ATOMIC_INC_RETURN(ATOMIC_T *v) -{ -#ifdef PLATFORM_LINUX - return atomic_inc_return(v); -#elif defined(PLATFORM_WINDOWS) - return InterlockedIncrement(v); -#elif defined(PLATFORM_FREEBSD) - atomic_add_int(v, 1); - return atomic_load_acq_32(v); -#endif -} - -inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) -{ -#ifdef PLATFORM_LINUX - return atomic_dec_return(v); -#elif defined(PLATFORM_WINDOWS) - return InterlockedDecrement(v); -#elif defined(PLATFORM_FREEBSD) - atomic_subtract_int(v, 1); - return atomic_load_acq_32(v); -#endif -} - -inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u) -{ -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) - return atomic_add_unless(v, 1, u); -#else - /* only make sure not exceed after this function */ - if (ATOMIC_INC_RETURN(v) > u) { - ATOMIC_DEC(v); - return 0; - } - return 1; -#endif -#else - #error "TBD\n" -#endif -} - -#ifdef PLATFORM_LINUX -/* -* Open a file with the specific @param path, @param flag, @param mode -* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success -* @param path the path of the file to open -* @param flag file operation flags, please refer to linux document -* @param mode please refer to linux document -* @return Linux specific error code -*/ -static int openFile(struct file **fpp, const char *path, int flag, int mode) -{ - struct file *fp; - - fp = filp_open(path, flag, mode); - if (IS_ERR(fp)) { - *fpp = NULL; - return PTR_ERR(fp); - } else { - *fpp = fp; - return 0; - } -} - -/* -* Close the file with the specific @param fp -* @param fp the pointer of struct file to close -* @return always 0 -*/ -static int closeFile(struct file *fp) -{ - filp_close(fp, NULL); - return 0; -} - -static int readFile(struct file *fp, char *buf, int len) -{ - int rlen = 0, sum = 0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - if (!(fp->f_mode & FMODE_CAN_READ)) -#else - if (!fp->f_op || !fp->f_op->read) -#endif - return -EPERM; - - while (sum < len) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); -#else - rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); -#endif - if (rlen > 0) - sum += rlen; - else if (0 != rlen) - return rlen; - else - break; - } - - return sum; - -} - -static int writeFile(struct file *fp, char *buf, int len) -{ - int wlen = 0, sum = 0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - if (!(fp->f_mode & FMODE_CAN_WRITE)) -#else - if (!fp->f_op || !fp->f_op->write) -#endif - return -EPERM; - - while (sum < len) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos); -#else - wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos); -#endif - if (wlen > 0) - sum += wlen; - else if (0 != wlen) - return wlen; - else - break; - } - - return sum; + , truesize + ); + return ret; } -/* -* Test if the specifi @param pathname is a direct and readable -* If readable, @param sz is not used -* @param pathname the name of the path to test -* @return Linux specific error code -*/ -static int isDirReadable(const char *pathname, u32 *sz) +#ifdef CONFIG_RTW_GRO +inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) { - struct path path; - int error = 0; - - return kern_path(pathname, LOOKUP_FOLLOW, &path); -} + int ret; + unsigned int truesize = skb->truesize; -/* -* Test if the specifi @param path is a file and readable -* If readable, @param sz is got -* @param path the path of the file to test -* @return Linux specific error code -*/ -static int isFileReadable(const char *path, u32 *sz) -{ - struct file *fp; - int ret = 0; - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - mm_segment_t oldfs; - #endif - char buf; - - fp = filp_open(path, O_RDONLY, 0); - if (IS_ERR(fp)) - ret = PTR_ERR(fp); - else { - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - oldfs = get_fs(); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) - set_fs(KERNEL_DS); - #else - set_fs(get_ds()); - #endif - #endif + if (match_mstat_sniff_rules(flags, truesize)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); - if (1 != readFile(fp, &buf, 1)) - ret = PTR_ERR(fp); + ret = _rtw_napi_gro_receive(napi, skb); - if (ret == 0 && sz) { - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) - *sz = i_size_read(fp->f_path.dentry->d_inode); - #else - *sz = i_size_read(fp->f_dentry->d_inode); - #endif - } + rtw_mstat_update( + flags + , MSTAT_FREE + , truesize + ); - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - set_fs(oldfs); - #endif - filp_close(fp, NULL); - } return ret; } +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ -/* -* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most -* @param path the path of the file to open and read -* @param buf the starting address of the buffer to store file content -* @param sz how many bytes to read at most -* @return the byte we've read, or Linux specific error code -*/ -static int retriveFromFile(const char *path, u8 *buf, u32 sz) +inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line) { - int ret = -1; - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - mm_segment_t oldfs; - #endif - struct file *fp; - - if (path && buf) { - ret = openFile(&fp, path, O_RDONLY, 0); - if (0 == ret) { - RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - oldfs = get_fs(); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) - set_fs(KERNEL_DS); - #else - set_fs(get_ds()); - #endif - #endif - - ret = readFile(fp, buf, sz); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - set_fs(oldfs); - #endif - closeFile(fp); - - RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret); - - } else - RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); - } else { - RTW_INFO("%s NULL pointer\n", __FUNCTION__); - ret = -EINVAL; - } - return ret; -} + struct sk_buff *skb; -/* -* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file -* @param path the path of the file to open and write -* @param buf the starting address of the data to write into file -* @param sz how many bytes to write at most -* @return the byte we've written, or Linux specific error code -*/ -static int storeToFile(const char *path, u8 *buf, u32 sz) -{ - int ret = 0; - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - mm_segment_t oldfs; - #endif - struct file *fp; - - if (path && buf) { - ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666); - if (0 == ret) { - RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - oldfs = get_fs(); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) - set_fs(KERNEL_DS); - #else - set_fs(get_ds()); - #endif - #endif - - ret = writeFile(fp, buf, sz); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) - set_fs(oldfs); - #endif - closeFile(fp); - - RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret); - - } else - RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); - } else { - RTW_INFO("%s NULL pointer\n", __FUNCTION__); - ret = -EINVAL; - } - return ret; + while ((skb = skb_dequeue(list)) != NULL) + dbg_rtw_skb_free(skb, flags, func, line); } -#endif /* PLATFORM_LINUX */ -/* -* Test if the specifi @param path is a direct and readable -* @param path the path of the direct to test -* @return _TRUE or _FALSE -*/ -int rtw_is_dir_readable(const char *path) +#ifdef CONFIG_USB_HCI +inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line) { -#ifdef PLATFORM_LINUX - if (isDirReadable(path, NULL) == 0) - return _TRUE; - else - return _FALSE; -#else - /* Todo... */ - return _FALSE; -#endif -} + void *p; -/* -* Test if the specifi @param path is a file and readable -* @param path the path of the file to test -* @return _TRUE or _FALSE -*/ -int rtw_is_file_readable(const char *path) -{ -#ifdef PLATFORM_LINUX - if (isFileReadable(path, NULL) == 0) - return _TRUE; - else - return _FALSE; -#else - /* Todo... */ - return _FALSE; -#endif -} + if (match_mstat_sniff_rules(flags, size)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); -/* -* Test if the specifi @param path is a file and readable. -* If readable, @param sz is got -* @param path the path of the file to test -* @return _TRUE or _FALSE -*/ -int rtw_is_file_readable_with_size(const char *path, u32 *sz) -{ -#ifdef PLATFORM_LINUX - if (isFileReadable(path, sz) == 0) - return _TRUE; - else - return _FALSE; -#else - /* Todo... */ - return _FALSE; -#endif + p = _rtw_usb_buffer_alloc(dev, size, dma); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , size + ); + + return p; } -/* -* Test if the specifi @param path is a readable file with valid size. -* If readable, @param sz is got -* @param path the path of the file to test -* @return _TRUE or _FALSE -*/ -int rtw_readable_file_sz_chk(const char *path, u32 sz) +inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line) { - u32 fsz; - if (rtw_is_file_readable_with_size(path, &fsz) == _FALSE) - return _FALSE; + if (match_mstat_sniff_rules(flags, size)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); - if (fsz > sz) - return _FALSE; - - return _TRUE; -} + _rtw_usb_buffer_free(dev, size, addr, dma); -/* -* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most -* @param path the path of the file to open and read -* @param buf the starting address of the buffer to store file content -* @param sz how many bytes to read at most -* @return the byte we've read -*/ -int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz) -{ -#ifdef PLATFORM_LINUX - int ret = retriveFromFile(path, buf, sz); - return ret >= 0 ? ret : 0; -#else - /* Todo... */ - return 0; -#endif + rtw_mstat_update( + flags + , MSTAT_FREE + , size + ); } +#endif /* CONFIG_USB_HCI */ -/* -* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file -* @param path the path of the file to open and write -* @param buf the starting address of the data to write into file -* @param sz how many bytes to write at most -* @return the byte we've written -*/ -int rtw_store_to_file(const char *path, u8 *buf, u32 sz) -{ -#ifdef PLATFORM_LINUX - int ret = storeToFile(path, buf, sz); - return ret >= 0 ? ret : 0; -#else - /* Todo... */ - return 0; -#endif -} +#endif /* defined(DBG_MEM_ALLOC) */ -#ifdef PLATFORM_LINUX -struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) +void *rtw_malloc2d(int h, int w, size_t size) { - struct net_device *pnetdev; - struct rtw_netdev_priv_indicator *pnpi; + int j; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); -#else - pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); -#endif - if (!pnetdev) - goto RETURN; + void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size); + if (a == NULL) { + RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__); + return NULL; + } - pnpi = netdev_priv(pnetdev); - pnpi->priv = old_priv; - pnpi->sizeof_priv = sizeof_priv; + for (j = 0; j < h; j++) + a[j] = ((char *)(a + h)) + j * w * size; -RETURN: - return pnetdev; + return a; } -struct net_device *rtw_alloc_etherdev(int sizeof_priv) +void rtw_mfree2d(void *pbuf, int h, int w, int size) { - struct net_device *pnetdev; - struct rtw_netdev_priv_indicator *pnpi; + rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size); +} -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); -#else - pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); -#endif - if (!pnetdev) - goto RETURN; +int _rtw_memcmp2(const void *dst, const void *src, u32 sz) +{ + const unsigned char *p1 = dst, *p2 = src; - pnpi = netdev_priv(pnetdev); + if (sz == 0) + return 0; - pnpi->priv = rtw_zvmalloc(sizeof_priv); - if (!pnpi->priv) { - free_netdev(pnetdev); - pnetdev = NULL; - goto RETURN; + while (*p1 == *p2) { + p1++; + p2++; + sz--; + if (sz == 0) + return 0; } - pnpi->sizeof_priv = sizeof_priv; -RETURN: - return pnetdev; + return *p1 - *p2; } -void rtw_free_netdev(struct net_device *netdev) +void _rtw_init_queue(_queue *pqueue) { - struct rtw_netdev_priv_indicator *pnpi; - - if (!netdev) - goto RETURN; - - pnpi = netdev_priv(netdev); - - if (!pnpi->priv) - goto RETURN; - - free_netdev(netdev); - -RETURN: - return; + _rtw_init_listhead(&(pqueue->queue)); + _rtw_spinlock_init(&(pqueue->lock)); } -#endif - -#ifdef PLATFORM_FREEBSD -/* - * Copy a buffer from userspace and write into kernel address - * space. - * - * This emulation just calls the FreeBSD copyin function (to - * copy data from user space buffer into a kernel space buffer) - * and is designed to be used with the above io_write_wrapper. - * - * This function should return the number of bytes not copied. - * I.e. success results in a zero value. - * Negative error values are not returned. - */ -unsigned long -copy_from_user(void *to, const void *from, unsigned long n) +void _rtw_deinit_queue(_queue *pqueue) { - if (copyin(from, to, n) != 0) { - /* Any errors will be treated as a failure - to copy any of the requested bytes */ - return n; - } - - return 0; + _rtw_spinlock_free(&(pqueue->lock)); } -unsigned long -copy_to_user(void *to, const void *from, unsigned long n) +u32 _rtw_queue_empty(_queue *pqueue) { - if (copyout(from, to, n) != 0) { - /* Any errors will be treated as a failure - to copy any of the requested bytes */ - return n; - } - - return 0; + return rtw_is_list_empty(&(pqueue->queue)); } -/* - * The usb_register and usb_deregister functions are used to register - * usb drivers with the usb subsystem. In this compatibility layer - * emulation a list of drivers (struct usb_driver) is maintained - * and is used for probing/attaching etc. - * - * usb_register and usb_deregister simply call these functions. - */ -int -usb_register(struct usb_driver *driver) +u32 rtw_end_of_queue_search(_list *head, _list *plist) { - rtw_usb_linux_register(driver); - return 0; + if (head == plist) + return _TRUE; + else + return _FALSE; } - -int -usb_deregister(struct usb_driver *driver) +/* the input parameter start use the same unit as returned by rtw_get_current_time */ +inline s32 _rtw_get_passing_time_ms(systime start) { - rtw_usb_linux_deregister(driver); - return 0; + return _rtw_systime_to_ms(_rtw_get_current_time() - start); } -void module_init_exit_wrapper(void *arg) +inline s32 _rtw_get_remaining_time_ms(systime end) { - int (*func)(void) = arg; - func(); - return; + return _rtw_systime_to_ms(end - _rtw_get_current_time()); } -#endif /* PLATFORM_FREEBSD */ - -#ifdef CONFIG_PLATFORM_SPRD - #ifdef do_div - #undef do_div - #endif - #include -#endif - -u64 rtw_modular64(u64 x, u64 y) +inline s32 _rtw_get_time_interval_ms(systime start, systime end) { -#ifdef PLATFORM_LINUX - return do_div(x, y); -#elif defined(PLATFORM_WINDOWS) - return x % y; -#elif defined(PLATFORM_FREEBSD) - return x % y; -#endif + return _rtw_systime_to_ms(end - start); } -u64 rtw_division64(u64 x, u64 y) +bool rtw_macaddr_is_larger(const u8 *a, const u8 *b) { -#ifdef PLATFORM_LINUX - do_div(x, y); - return x; -#elif defined(PLATFORM_WINDOWS) - return x / y; -#elif defined(PLATFORM_FREEBSD) - return x / y; -#endif + u32 va, vb; + + va = be32_to_cpu(*((u32 *)a)); + vb = be32_to_cpu(*((u32 *)b)); + if (va > vb) + return 1; + else if (va < vb) + return 0; + + return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4))); } -inline u32 rtw_random32(void) + +/* +* Test if the specifi @param path is a readable file with valid size. +* If readable, @param sz is got +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_readable_file_sz_chk(const char *path, u32 sz) { -#ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)) - return get_random_u32(); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - return prandom_u32(); -#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18)) - u32 random_int; - get_random_bytes(&random_int , 4); - return random_int; -#else - return random32(); -#endif -#elif defined(PLATFORM_WINDOWS) -#error "to be implemented\n" -#elif defined(PLATFORM_FREEBSD) -#error "to be implemented\n" -#endif + u32 fsz; + + if (rtw_is_file_readable_with_size(path, &fsz) == _FALSE) + return _FALSE; + + if (fsz > sz) + return _FALSE; + + return _TRUE; } void rtw_buf_free(u8 **buf, u32 *buf_len) @@ -2953,7 +652,7 @@ void rtw_buf_free(u8 **buf, u32 *buf_len) } } -void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len) +void rtw_buf_update(u8 **buf, u32 *buf_len, const u8 *src, u32 src_len) { u32 ori_len = 0, dup_len = 0; u8 *ori = NULL; @@ -3169,14 +868,13 @@ u8 map_read8(const struct map_t *map, u16 offset) return val; } -#ifdef CONFIG_RTW_MESH int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms) { struct blacklist_ent *ent; _list *list, *head; u8 exist = _FALSE, timeout = _FALSE; - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); head = &blist->queue; list = get_next(head); @@ -3209,7 +907,7 @@ int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms) } } - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL); } @@ -3220,7 +918,7 @@ int rtw_blacklist_del(_queue *blist, const u8 *addr) _list *list, *head; u8 exist = _FALSE; - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); head = &blist->queue; list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { @@ -3240,7 +938,7 @@ int rtw_blacklist_del(_queue *blist, const u8 *addr) } } - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); return exist == _TRUE ? _SUCCESS : RTW_ALREADY; } @@ -3251,7 +949,7 @@ int rtw_blacklist_search(_queue *blist, const u8 *addr) _list *list, *head; u8 exist = _FALSE; - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); head = &blist->queue; list = get_next(head); while (rtw_end_of_queue_search(head, list) == _FALSE) { @@ -3273,7 +971,7 @@ int rtw_blacklist_search(_queue *blist, const u8 *addr) } } - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); return exist; } @@ -3286,9 +984,9 @@ void rtw_blacklist_flush(_queue *blist) _rtw_init_listhead(&tmp); - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); rtw_list_splice_init(&blist->queue, &tmp); - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); head = &tmp; list = get_next(head); @@ -3305,7 +1003,7 @@ void dump_blacklist(void *sel, _queue *blist, const char *title) struct blacklist_ent *ent = NULL; _list *list, *head; - enter_critical_bh(&blist->lock); + _rtw_spinlock_bh(&blist->lock); head = &blist->queue; list = get_next(head); @@ -3325,9 +1023,8 @@ void dump_blacklist(void *sel, _queue *blist, const char *title) } } - exit_critical_bh(&blist->lock); + _rtw_spinunlock_bh(&blist->lock); } -#endif /** * is_null - @@ -3380,6 +1077,20 @@ inline BOOLEAN is_space(char c) return _FALSE; } +/** +* is_decimal - +* +* Return TRUE if chTmp is represent for decimal digit +* FALSE otherwise. +*/ +inline BOOLEAN is_decimal(char chTmp) +{ + if ((chTmp >= '0' && chTmp <= '9')) + return _TRUE; + else + return _FALSE; +} + /** * IsHexDigit - * @@ -3458,30 +1169,3 @@ int hexstr2bin(const char *hex, u8 *buf, size_t len) return 0; } -/** - * hwaddr_aton - Convert ASCII string to MAC address - * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") - * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) - * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) - */ -int hwaddr_aton_i(const char *txt, u8 *addr) -{ - int i; - - for (i = 0; i < 6; i++) { - int a, b; - - a = hex2num_i(*txt++); - if (a < 0) - return -1; - b = hex2num_i(*txt++); - if (b < 0) - return -1; - *addr++ = (a << 4) | b; - if (i < 5 && *txt++ != ':') - return -1; - } - - return 0; -} - diff --git a/os_dep/osdep_service_linux.c b/os_dep/osdep_service_linux.c new file mode 100644 index 0000000..8dab5a3 --- /dev/null +++ b/os_dep/osdep_service_linux.c @@ -0,0 +1,858 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _OSDEP_SERVICE_LINUX_C_ +#include + +#ifdef DBG_MEMORY_LEAK +ATOMIC_T _malloc_cnt = ATOMIC_INIT(0); +ATOMIC_T _malloc_size = ATOMIC_INIT(0); +#endif /* DBG_MEMORY_LEAK */ + +/* +* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE +* @return: one of RTW_STATUS_CODE +*/ +inline int RTW_STATUS_CODE(int error_code) +{ + if (error_code >= 0) + return _SUCCESS; + + switch (error_code) { + /* case -ETIMEDOUT: */ + /* return RTW_STATUS_TIMEDOUT; */ + default: + return _FAIL; + } +} + +void _rtw_skb_queue_purge(struct sk_buff_head *list) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(list)) != NULL) + _rtw_skb_free(skb); +} + +void _rtw_memcpy(void *dst, const void *src, u32 sz) +{ + memcpy(dst, src, sz); +} + +inline void _rtw_memmove(void *dst, const void *src, u32 sz) +{ + memmove(dst, src, sz); +} + +int _rtw_memcmp(const void *dst, const void *src, u32 sz) +{ + /* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */ + if (!(memcmp(dst, src, sz))) + return _TRUE; + else + return _FALSE; +} + +void _rtw_memset(void *pbuf, int c, u32 sz) +{ + memset(pbuf, c, sz); +} + +void _rtw_init_listhead(_list *list) +{ + INIT_LIST_HEAD(list); +} +/* +For the following list_xxx operations, +caller must guarantee the atomic context. +Otherwise, there will be racing condition. +*/ +u32 rtw_is_list_empty(_list *phead) +{ + if (list_empty(phead)) + return _TRUE; + else + return _FALSE; +} + +void rtw_list_insert_head(_list *plist, _list *phead) +{ + list_add(plist, phead); +} + +void rtw_list_insert_tail(_list *plist, _list *phead) +{ + list_add_tail(plist, phead); +} + +inline void rtw_list_splice(_list *list, _list *head) +{ + list_splice(list, head); +} + +inline void rtw_list_splice_init(_list *list, _list *head) +{ + list_splice_init(list, head); +} + +inline void rtw_list_splice_tail(_list *list, _list *head) +{ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) + if (!list_empty(list)) + __list_splice(list, head); + #else + list_splice_tail(list, head); + #endif +} + +inline void rtw_hlist_head_init(rtw_hlist_head *h) +{ + INIT_HLIST_HEAD(h); +} + +inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h) +{ + hlist_add_head(n, h); +} + +inline void rtw_hlist_del(rtw_hlist_node *n) +{ + hlist_del(n); +} + +inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h) +{ + hlist_add_head_rcu(n, h); +} + +inline void rtw_hlist_del_rcu(rtw_hlist_node *n) +{ + hlist_del_rcu(n); +} + +void rtw_init_timer(_timer *ptimer, void *pfunc, void *ctx) +{ + _init_timer(ptimer, pfunc, ctx); +} + +systime _rtw_get_current_time(void) +{ + return jiffies; +} + +inline u32 _rtw_systime_to_ms(systime stime) +{ + return jiffies_to_msecs(stime); +} + +inline u32 _rtw_systime_to_us(systime stime) +{ + return jiffies_to_usecs(stime); +} + +inline systime _rtw_ms_to_systime(u32 ms) +{ + return msecs_to_jiffies(ms); +} + +inline systime _rtw_us_to_systime(u32 us) +{ + return usecs_to_jiffies(us); +} + +inline bool _rtw_time_after(systime a, systime b) +{ + return time_after(a, b); +} + +void rtw_sleep_schedulable(int ms) +{ + u32 delta; + + delta = (ms * HZ) / 1000; /* (ms) */ + if (delta == 0) { + delta = 1;/* 1 ms */ + } + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(delta); + return; +} + +void rtw_msleep_os(int ms) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) + if (ms < 20) { + unsigned long us = ms * 1000UL; + usleep_range(us, us + 1000UL); + } else +#endif + msleep((unsigned int)ms); + +} +void rtw_usleep_os(int us) +{ + /* msleep((unsigned int)us); */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) + usleep_range(us, us + 1); +#else + if (1 < (us / 1000)) + msleep(1); + else + msleep((us / 1000) + 1); +#endif +} + + +#ifdef DBG_DELAY_OS +void _rtw_mdelay_os(int ms, const char *func, const int line) +{ + RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); + mdelay((unsigned long)ms); +} +void _rtw_udelay_os(int us, const char *func, const int line) +{ + RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); + udelay((unsigned long)us); +} +#else +void rtw_mdelay_os(int ms) +{ + mdelay((unsigned long)ms); +} +void rtw_udelay_os(int us) +{ + udelay((unsigned long)us); +} +#endif + +void rtw_yield_os(void) +{ + yield(); +} + + +#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" +#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" +#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" + +#ifdef CONFIG_WAKELOCK +static struct wake_lock rtw_suspend_lock; +static struct wake_lock rtw_suspend_traffic_lock; +static struct wake_lock rtw_suspend_resume_lock; +#elif defined(CONFIG_ANDROID_POWER) +static android_suspend_lock_t rtw_suspend_lock = { + .name = RTW_SUSPEND_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_traffic_lock = { + .name = RTW_SUSPEND_TRAFFIC_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_resume_lock = { + .name = RTW_SUSPEND_RESUME_LOCK_NAME +}; +#endif + +inline void rtw_suspend_lock_init(void) +{ +#ifdef CONFIG_WAKELOCK + wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); + wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME); + wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME); +#elif defined(CONFIG_ANDROID_POWER) + android_init_suspend_lock(&rtw_suspend_lock); + android_init_suspend_lock(&rtw_suspend_traffic_lock); + android_init_suspend_lock(&rtw_suspend_resume_lock); +#endif +} + +inline void rtw_suspend_lock_uninit(void) +{ +#ifdef CONFIG_WAKELOCK + wake_lock_destroy(&rtw_suspend_lock); + wake_lock_destroy(&rtw_suspend_traffic_lock); + wake_lock_destroy(&rtw_suspend_resume_lock); +#elif defined(CONFIG_ANDROID_POWER) + android_uninit_suspend_lock(&rtw_suspend_lock); + android_uninit_suspend_lock(&rtw_suspend_traffic_lock); + android_uninit_suspend_lock(&rtw_suspend_resume_lock); +#endif +} + +inline void rtw_lock_suspend(void) +{ +#ifdef CONFIG_WAKELOCK + wake_lock(&rtw_suspend_lock); +#elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend(&rtw_suspend_lock); +#endif + +#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ +#endif +} + +inline void rtw_unlock_suspend(void) +{ +#ifdef CONFIG_WAKELOCK + wake_unlock(&rtw_suspend_lock); +#elif defined(CONFIG_ANDROID_POWER) + android_unlock_suspend(&rtw_suspend_lock); +#endif + +#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ +#endif +} + +inline void rtw_resume_lock_suspend(void) +{ +#ifdef CONFIG_WAKELOCK + wake_lock(&rtw_suspend_resume_lock); +#elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend(&rtw_suspend_resume_lock); +#endif + +#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ +#endif +} + +inline void rtw_resume_unlock_suspend(void) +{ +#ifdef CONFIG_WAKELOCK + wake_unlock(&rtw_suspend_resume_lock); +#elif defined(CONFIG_ANDROID_POWER) + android_unlock_suspend(&rtw_suspend_resume_lock); +#endif + +#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + /* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */ +#endif +} + +inline void rtw_lock_suspend_timeout(u32 timeout_ms) +{ +#ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); +#elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); +#endif +} + +inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) +{ +#ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); +#elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); +#endif + /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ +} + +inline void rtw_set_bit(int nr, unsigned long *addr) +{ + set_bit(nr, addr); +} + +inline void rtw_clear_bit(int nr, unsigned long *addr) +{ + clear_bit(nr, addr); +} + +inline int rtw_test_and_clear_bit(int nr, unsigned long *addr) +{ + return test_and_clear_bit(nr, addr); +} +inline int rtw_test_and_set_bit(int nr, unsigned long *addr) +{ + return test_and_set_bit(nr, addr); +} +/* +* Open a file with the specific @param path, @param flag, @param mode +* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success +* @param path the path of the file to open +* @param flag file operation flags, please refer to linux document +* @param mode please refer to linux document +* @return Linux specific error code +*/ +static int openFile(struct file **fpp, const char *path, int flag, int mode) +{ + struct file *fp; + + fp = filp_open(path, flag, mode); + if (IS_ERR(fp)) { + *fpp = NULL; + return PTR_ERR(fp); + } else { + *fpp = fp; + return 0; + } +} + +/* +* Close the file with the specific @param fp +* @param fp the pointer of struct file to close +* @return always 0 +*/ +static int closeFile(struct file *fp) +{ + filp_close(fp, NULL); + return 0; +} + +static int readFile(struct file *fp, char *buf, int len) +{ + int rlen = 0, sum = 0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + if (!(fp->f_mode & FMODE_CAN_READ)) +#else + if (!fp->f_op || !fp->f_op->read) +#endif + return -EPERM; + + while (sum < len) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); +#else + rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); +#endif + if (rlen > 0) + sum += rlen; + else if (0 != rlen) + return rlen; + else + break; + } + + return sum; + +} + +#ifndef CONFIG_RTW_ANDROID +static int writeFile(struct file *fp, char *buf, int len) +{ + int wlen = 0, sum = 0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + if (!(fp->f_mode & FMODE_CAN_WRITE)) +#else + if (!fp->f_op || !fp->f_op->write) +#endif + return -EPERM; + + while (sum < len) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos); +#else + wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos); +#endif + if (wlen > 0) + sum += wlen; + else if (0 != wlen) + return wlen; + else + break; + } + + return sum; + +} + +/* +* Test if the specifi @param pathname is a direct and readable +* If readable, @param sz is not used +* @param pathname the name of the path to test +* @return Linux specific error code +*/ +static int isDirReadable(const char *pathname, u32 *sz) +{ + struct path path; + int error = 0; + + return kern_path(pathname, LOOKUP_FOLLOW, &path); +} +#endif /* CONFIG_RTW_ANDROID */ + +/* +* Test if the specifi @param path is a file and readable +* If readable, @param sz is got +* @param path the path of the file to test +* @return Linux specific error code +*/ +static int isFileReadable(const char *path, u32 *sz) +{ + struct file *fp; + int ret = 0; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + mm_segment_t oldfs; + #endif + char buf; + + fp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(fp)) + ret = PTR_ERR(fp); + else { + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + oldfs = get_fs(); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + set_fs(KERNEL_DS); + #else + set_fs(get_ds()); + #endif + #endif + + if (1 != readFile(fp, &buf, 1)) + ret = PTR_ERR(fp); + + if (ret == 0 && sz) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + *sz = i_size_read(fp->f_path.dentry->d_inode); + #else + *sz = i_size_read(fp->f_dentry->d_inode); + #endif + } + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + set_fs(oldfs); + #endif + filp_close(fp, NULL); + } + return ret; +} + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read, or Linux specific error code +*/ +static int retriveFromFile(const char *path, u8 *buf, u32 sz) +{ + int ret = -1; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + mm_segment_t oldfs; + #endif + struct file *fp; + + if (path && buf) { + ret = openFile(&fp, path, O_RDONLY, 0); + if (0 == ret) { + RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + oldfs = get_fs(); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + set_fs(KERNEL_DS); + #else + set_fs(get_ds()); + #endif + #endif + + ret = readFile(fp, buf, sz); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + set_fs(oldfs); + #endif + closeFile(fp); + + RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret); + + } else + RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); + } else { + RTW_INFO("%s NULL pointer\n", __FUNCTION__); + ret = -EINVAL; + } + return ret; +} + +#ifndef CONFIG_RTW_ANDROID +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written, or Linux specific error code +*/ +static int storeToFile(const char *path, u8 *buf, u32 sz) +{ + int ret = 0; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + mm_segment_t oldfs; + #endif + struct file *fp; + + if (path && buf) { + ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666); + if (0 == ret) { + RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + oldfs = get_fs(); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + set_fs(KERNEL_DS); + #else + set_fs(get_ds()); + #endif + #endif + + ret = writeFile(fp, buf, sz); + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + set_fs(oldfs); + #endif + closeFile(fp); + + RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret); + + } else + RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); + } else { + RTW_INFO("%s NULL pointer\n", __FUNCTION__); + ret = -EINVAL; + } + return ret; +} + +/* +* Test if the specifi @param path is a direct and readable +* @param path the path of the direct to test +* @return _TRUE or _FALSE +*/ +int rtw_is_dir_readable(const char *path) +{ + if (isDirReadable(path, NULL) == 0) + return _TRUE; + else + return _FALSE; +} +#endif /* CONFIG_RTW_ANDROID */ + +/* +* Test if the specifi @param path is a file and readable +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable(const char *path) +{ + if (isFileReadable(path, NULL) == 0) + return _TRUE; + else + return _FALSE; +} + +/* +* Test if the specifi @param path is a file and readable. +* If readable, @param sz is got +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable_with_size(const char *path, u32 *sz) +{ + if (isFileReadable(path, sz) == 0) + return _TRUE; + else + return _FALSE; +} + + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read +*/ +int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz) +{ + int ret = retriveFromFile(path, buf, sz); + return ret >= 0 ? ret : 0; +} + +#ifndef CONFIG_RTW_ANDROID +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written +*/ +int rtw_store_to_file(const char *path, u8 *buf, u32 sz) +{ + int ret = storeToFile(path, buf, sz); + return ret >= 0 ? ret : 0; +} +#endif /* CONFIG_RTW_ANDROID */ + +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); +#else + pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); +#endif + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + pnpi->priv = old_priv; + pnpi->sizeof_priv = sizeof_priv; + +RETURN: + return pnetdev; +} + +struct net_device *rtw_alloc_etherdev(int sizeof_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); +#else + pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); +#endif + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + + pnpi->priv = rtw_zvmalloc(sizeof_priv); + if (!pnpi->priv) { + free_netdev(pnetdev); + pnetdev = NULL; + goto RETURN; + } + + pnpi->sizeof_priv = sizeof_priv; +RETURN: + return pnetdev; +} + +void rtw_free_netdev(struct net_device *netdev) +{ + struct rtw_netdev_priv_indicator *pnpi; + + if (!netdev) + goto RETURN; + + pnpi = netdev_priv(netdev); + + if (!pnpi->priv) + goto RETURN; + + free_netdev(netdev); + +RETURN: + return; +} + +int rtw_change_ifname(_adapter *padapter, const char *ifname) +{ + struct dvobj_priv *dvobj; + struct net_device *pnetdev; + struct net_device *cur_pnetdev; + struct rereg_nd_name_data *rereg_priv; + int ret; + u8 rtnl_lock_needed; + + if (!padapter) + goto error; + + dvobj = adapter_to_dvobj(padapter); + cur_pnetdev = padapter->pnetdev; + rereg_priv = &padapter->rereg_nd_name_priv; + + /* free the old_pnetdev */ + if (rereg_priv->old_pnetdev) { + free_netdev(rereg_priv->old_pnetdev); + rereg_priv->old_pnetdev = NULL; + } + + rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + if (rtnl_lock_needed) + unregister_netdev(cur_pnetdev); + else + unregister_netdevice(cur_pnetdev); + + rereg_priv->old_pnetdev = cur_pnetdev; + + pnetdev = rtw_init_netdev(padapter); + if (!pnetdev) { + ret = -1; + goto error; + } + + SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter))); + + rtw_init_netdev_name(pnetdev, ifname); + + _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); + + if (rtnl_lock_needed) + ret = register_netdev(pnetdev); + else + ret = register_netdevice(pnetdev); + + if (ret != 0) { + goto error; + } + + return 0; + +error: + + return -1; + +} + +#ifdef CONFIG_PLATFORM_SPRD +#ifdef do_div + #undef do_div +#endif + #include +#endif + +u64 rtw_modular64(u64 x, u64 y) +{ + return do_div(x, y); +} + +u64 rtw_division64(u64 x, u64 y) +{ + do_div(x, y); + return x; +} + +inline u32 rtw_random32(void) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + return prandom_u32(); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18)) + u32 random_int; + get_random_bytes(&random_int , 4); + return random_int; +#else + return random32(); +#endif +} diff --git a/phl/custom/phl_custom.c b/phl/custom/phl_custom.c new file mode 100644 index 0000000..3523662 --- /dev/null +++ b/phl/custom/phl_custom.c @@ -0,0 +1,463 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CUSTOM_C_ +#include "../phl_headers.h" +#include "phl_custom_fb.h" + +#ifdef CONFIG_PHL_CUSTOM_FEATURE + +#define MAX_DATA_SIZE (512) +enum custom_status { + CUS_STAT_CMD_USED = BIT0, + CUS_STAT_RPT_USED = BIT1, + CUS_STAT_RPT_SENDING = BIT2, +}; + +struct phl_custom_ctx { + struct phl_info_t *phl_info; + u8 status; /* refer to enum custom_status*/ + u8 cmd_buf[MAX_DATA_SIZE]; + u8 rpt_buf[MAX_DATA_SIZE]; +#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB + struct _custom_facebook_ctx fb_ctx; +#endif +}; + +bool +_custom_rpt_notify_check(void* priv, struct phl_msg* msg) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + bool ret = true; + if (!TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED) || + TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING)) { + ret = false; + } + return ret; +} + +void +_custom_rpt_notify_complete(void* priv, struct phl_msg* msg) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + + CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED); + CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING); +} + +void +_custom_rpt_notify_start(void* priv, + struct phl_msg* msg, + struct phl_msg_attribute* attr) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + struct rtw_custom_decrpt *evt_rpt = (struct rtw_custom_decrpt *)ctx->rpt_buf; + + SET_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING); + + SET_MSG_MDL_ID_FIELD(msg->msg_id, PHL_MDL_CUSTOM); + SET_MSG_EVT_ID_FIELD(msg->msg_id, MSG_EVT_CUSTOM_CMD_DONE); + + msg->inbuf = (u8*) evt_rpt; + msg->inlen = evt_rpt->len + sizeof(struct rtw_custom_decrpt); + + attr->completion.completion = _custom_rpt_notify_complete; + attr->completion.priv = ctx; +} + +static void +_indicate_custome_evt_rpt(struct phl_custom_ctx *ctx) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + if (!_custom_rpt_notify_check((void*)ctx, &msg)) + return; + + _custom_rpt_notify_start((void*)ctx, &msg, &attr); + + if (phl_msg_hub_send(ctx->phl_info, + &attr, &msg) != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s send msg fail\n", __func__); + _custom_rpt_notify_complete((void*)ctx, &msg); + } +} +enum rtw_phl_status +_phl_custom_prepare_default_fail_rpt(struct phl_custom_ctx *ctx, + struct phl_msg* msg) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + u8 ret = MDL_RET_FAIL; + + if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED)) + return RTW_PHL_STATUS_RESOURCE; + + phl_custom_prepare_evt_rpt(ctx, + cmd->evt_id, + cmd->customer_id, + &ret, + 1); + return RTW_PHL_STATUS_SUCCESS; +} +static enum phl_mdl_ret_code +_phl_custom_hdl_fail_evt(void* dispr, + struct phl_custom_ctx* ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct rtw_custom_decrpt *cmd = NULL; + + cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_EDCA_ADJUST: +#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB + if(cmd->customer_id == CUS_ID_FB) { + ret = phl_custom_hdl_fb_fail_evt(dispr, + ctx, + &(ctx->fb_ctx), + msg); + } +#else + ret = MDL_RET_IGNORE; +#endif + break; + default: + ret = MDL_RET_IGNORE; + break; + } + return ret; +} +static enum phl_mdl_ret_code +_phl_custom_hdl_internal_evt(void* dispr, + struct phl_custom_ctx* ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + struct rtw_custom_decrpt *cmd = NULL; + + cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_CUSTOME_FEATURE_ENABLE: + case MSG_EVT_CUSTOME_FEATURE_QUERY: + case MSG_EVT_CUSTOME_TESTMODE_PARAM: + case MSG_EVT_CUSTOME_SET_WIFI_ROLE: + case MSG_EVT_AMPDU_CFG: + case MSG_EVT_AMPDU_QUERY: + case MSG_EVT_PDTHR_CFG: + case MSG_EVT_PDTHR_QUERY: + case MSG_EVT_POP_CFG: + case MSG_EVT_POP_QUERY: +#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB + if(cmd->customer_id == CUS_ID_FB) { + ret = phl_custom_hdl_fb_evt(dispr, + ctx, + &(ctx->fb_ctx), + msg); + } +#else + ret = MDL_RET_IGNORE; +#endif + break; + default: + ret = MDL_RET_IGNORE; + break; + } + return ret; +} +static enum phl_mdl_ret_code +_phl_custom_hdl_external_evt(void* dispr, + struct phl_custom_ctx* ctx, + struct phl_msg* msg) +{ + return MDL_RET_IGNORE; +} + +void +_phl_custom_cmd_completion(void* priv, struct phl_msg* msg) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED); +} + +enum phl_mdl_ret_code +_phl_custom_mdl_init(void* phl_info, + void* dispr, + void** priv) +{ + struct phl_info_t *phl = (struct phl_info_t *)phl_info; + struct phl_custom_ctx* ctx = NULL; + void *d = phl_to_drvpriv(phl); + + FUNCIN(); + if (priv == NULL) + return MDL_RET_FAIL; + + (*priv) = NULL; + ctx = (struct phl_custom_ctx *)_os_mem_alloc(d, sizeof(struct phl_custom_ctx)); + if (ctx == NULL) { + PHL_ERR(" %s, alloc fail\n",__FUNCTION__); + return MDL_RET_FAIL; + } + ctx->phl_info = phl_info; + (*priv) = (void*)ctx; + PHL_INFO(" %s, size phl_custom_ctx(%d)\n", + __FUNCTION__, (int)sizeof(struct phl_custom_ctx)); + return MDL_RET_SUCCESS; +} +void +_phl_custom_mdl_deinit(void* dispr, void* priv) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx*)priv; + void *d = phl_to_drvpriv(ctx->phl_info); + + _os_mem_free(d, ctx, sizeof(struct phl_custom_ctx)); + PHL_INFO(" %s\n", __FUNCTION__); +} +enum phl_mdl_ret_code +_phl_custom_mdl_start(void* dispr, void* priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + + FUNCIN(); + FUNCOUT(); + + ret = MDL_RET_SUCCESS; + return ret; +} +enum phl_mdl_ret_code +_phl_custom_mdl_stop(void* dispr, void* priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + + FUNCIN(); + FUNCOUT(); + + ret = MDL_RET_SUCCESS; + return ret; +} +enum phl_mdl_ret_code +_phl_custom_mdl_msg_hdlr(void* dispr, + void* priv, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct phl_custom_ctx *ctx = (struct phl_custom_ctx*)priv; + + FUNCIN(); + if (IS_MSG_FAIL(msg->msg_id)) { + ret = _phl_custom_hdl_fail_evt(dispr, priv, msg); + _indicate_custome_evt_rpt(ctx); + return MDL_RET_IGNORE; + } + + switch (MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_MDL_CUSTOM: + ret = _phl_custom_hdl_internal_evt(dispr, priv, msg); + break; + default: + ret = _phl_custom_hdl_external_evt(dispr, priv, msg); + break; + } + _indicate_custome_evt_rpt(ctx); + FUNCOUT(); + return ret; +} +enum phl_mdl_ret_code +_phl_custom_mdl_set_info(void* dispr, + void* priv, + struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + void *d = phl_to_drvpriv(ctx->phl_info); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_custom_decrpt *cmd = NULL; + u8 idx = 0xff; + + phl_dispr_get_idx(dispr, &idx); + FUNCIN(); + switch (info->op_code) { + case BK_MODL_OP_INPUT_CMD: + if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED) || + info->inlen > MAX_DATA_SIZE) { + PHL_ERR("%s buf len err or used\n", __func__); + break; + } + SET_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED); + _os_mem_cpy(d, ctx->cmd_buf, info->inbuf, info->inlen); + cmd = (struct rtw_custom_decrpt *)ctx->cmd_buf; + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_CUSTOM); + SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)cmd->evt_id); + msg.inbuf = ctx->cmd_buf; + msg.inlen = info->inlen; + attr.completion.priv = priv; + attr.completion.completion = _phl_custom_cmd_completion; + msg.band_idx = idx; + if (phl_disp_eng_send_msg(ctx->phl_info, + &msg, + &attr, + NULL) == RTW_PHL_STATUS_SUCCESS) { + ret = MDL_RET_SUCCESS; + } else { + CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED); + PHL_ERR("%s send msg fail\n", __func__); + ret = MDL_RET_FAIL; + } + break; + case BK_MODL_OP_CUS_SET_ROLE_CAP: + ret = phl_custom_fb_set_role_cap(dispr, + (void *)ctx, + &ctx->fb_ctx, + info); + break; + default: + break; + } + FUNCOUT(); + return ret; +} +enum phl_mdl_ret_code +_phl_custom_mdl_query_info(void* dispr, + void* priv, + struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv; + void *d = phl_to_drvpriv(ctx->phl_info); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_custom_decrpt *cmd = NULL; + u8 idx = 0xff; + + FUNCIN(); + switch(info->op_code) { + case BK_MODL_OP_INPUT_CMD: + if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED) || + info->inlen > MAX_DATA_SIZE) { + PHL_ERR("%s buf len err or used\n", __func__); + break; + } + SET_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED); + _os_mem_cpy(d, ctx->cmd_buf, info->inbuf, info->inlen); + _os_mem_cpy(d, ctx->rpt_buf, info->outbuf, info->outlen); + cmd = (struct rtw_custom_decrpt *)ctx->cmd_buf; + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_CUSTOM); + SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)cmd->evt_id); + msg.inbuf = ctx->cmd_buf; + msg.inlen = info->inlen; + msg.outbuf = ctx->rpt_buf; + msg.outlen = info->outlen; + attr.completion.priv = priv; + attr.completion.completion = _phl_custom_cmd_completion; + msg.band_idx = idx; + if (phl_disp_eng_send_msg(ctx->phl_info, + &msg, + &attr, + NULL) == RTW_PHL_STATUS_SUCCESS) { + ret = MDL_RET_SUCCESS; + } else { + CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED); + PHL_ERR("%s send msg fail\n", __func__); + ret = MDL_RET_FAIL; + } + break; + case BK_MODL_OP_CUS_UPDATE_ROLE_CAP: + ret = phl_custom_fb_update_opt_ie(dispr, (void*)ctx, &ctx->fb_ctx, info); + break; + default: + break; + } + + FUNCOUT(); + return ret; +} + +enum rtw_phl_status +phl_register_custom_module(struct phl_info_t *phl_info, u8 band_idx) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_bk_module_ops bk_ops = {0}; + + bk_ops.init = _phl_custom_mdl_init; + bk_ops.deinit = _phl_custom_mdl_deinit; + bk_ops.start = _phl_custom_mdl_start; + bk_ops.stop = _phl_custom_mdl_stop; + bk_ops.msg_hdlr = _phl_custom_mdl_msg_hdlr; + bk_ops.query_info = _phl_custom_mdl_query_info; + bk_ops.set_info = _phl_custom_mdl_set_info; + + phl_status = phl_disp_eng_register_module(phl_info, + band_idx, + PHL_MDL_CUSTOM, + &bk_ops); + if (RTW_PHL_STATUS_SUCCESS != phl_status) + PHL_ERR("%s register Custom module in cmd disp failed\n", __func__); + + return phl_status; + +} + +enum rtw_phl_status +phl_custom_prepare_evt_rpt(void *custom_ctx, + u32 evt_id, + u32 customer_id, + u8 *rpt, + u32 rpt_len) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)custom_ctx; + struct rtw_custom_decrpt *evt_rpt = (struct rtw_custom_decrpt *)ctx->rpt_buf; + void *d = phl_to_drvpriv(ctx->phl_info); + u8* val = (u8*)(evt_rpt +1); + + if ((rpt_len > (MAX_DATA_SIZE - sizeof(struct rtw_custom_decrpt))) || + TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED)) + return RTW_PHL_STATUS_RESOURCE; + + SET_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED); + evt_rpt->evt_id = evt_id; + evt_rpt->customer_id = customer_id; + evt_rpt->len = rpt_len; + _os_mem_cpy(d, val, rpt, rpt_len); + return RTW_PHL_STATUS_SUCCESS; +} +struct phl_info_t* +phl_custom_get_phl_info(void *custom_ctx) +{ + struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)custom_ctx; + + return ctx->phl_info; +} + +/** + * phl_custom_init_role_cap + * 1. role cap customization + * input: + * @phl_info: (struct phl_info_t *) + * @hw_band:hw_band + * @role_cap: (struct role_cap_t) + * return: rtw_phl_status + */ +enum rtw_phl_status +phl_custom_init_role_cap(struct phl_info_t *phl_info, + u8 hw_band, + struct role_cap_t *role_cap) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + status = phl_custom_fb_init_role_cap(phl_info, hw_band, role_cap); + + return status; +} +#endif diff --git a/phl/custom/phl_custom.h b/phl/custom/phl_custom.h new file mode 100644 index 0000000..d120907 --- /dev/null +++ b/phl/custom/phl_custom.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CUSTOM_H_ +#define _PHL_CUSTOM_H_ + +#ifdef CONFIG_PHL_CUSTOM_FEATURE + +enum rtw_phl_status +phl_register_custom_module(struct phl_info_t *phl_info, u8 band_idx); + +enum rtw_phl_status +phl_custom_prepare_evt_rpt(void *custom_ctx, + u32 evt_id, + u32 customer_id, + u8 *rpt, + u32 rpt_len); +struct phl_info_t * +phl_custom_get_phl_info(void *custom_ctx); + +enum rtw_phl_status +phl_custom_init_role_cap(struct phl_info_t *phl_info, + u8 hw_band, + struct role_cap_t *role_cap); +#else +#define phl_register_custom_module(_phl_info, _band_idx) (RTW_PHL_STATUS_SUCCESS) +#define phl_custom_init_role_cap(_phl_info, _hw_band, _role_cap) (RTW_PHL_STATUS_SUCCESS) +#endif + +#endif /*_PHL_CUSTOMIZE_FEATURE_H_*/ + diff --git a/phl/custom/phl_custom_api.h b/phl/custom/phl_custom_api.h new file mode 100644 index 0000000..2094d99 --- /dev/null +++ b/phl/custom/phl_custom_api.h @@ -0,0 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CUSTOM_API_H_ +#define _PHL_CUSTOM_API_H_ + + +#endif /*_PHL_CUSTOM_API_H_*/ diff --git a/phl/custom/phl_custom_def.h b/phl/custom/phl_custom_def.h new file mode 100644 index 0000000..3dee4cb --- /dev/null +++ b/phl/custom/phl_custom_def.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CUSTOM_DEF_H_ +#define _PHL_CUSTOM_DEF_H_ + +#define PRIVATE_EVT_START (BIT15) + +enum rtw_customer_feature_id { + CUS_ID_NONE = 0, + CUS_ID_FB = 1, + CUS_ID_MAX +}; + +enum rtw_msg_custom_evt_id { + /* Reserved for Custom Feature + * be aware that the order of the following id are also used in + * upper layer application, thus, it shall not be changed to + * avoid mismatch error!! + */ + MSG_EVT_CUSTOME_NONE = PRIVATE_EVT_START, + MSG_EVT_CUSTOME_FEATURE_ENABLE = PRIVATE_EVT_START + 1, + MSG_EVT_CUSTOME_FEATURE_QUERY = PRIVATE_EVT_START + 2, + MSG_EVT_CUSTOME_TESTMODE_PARAM = PRIVATE_EVT_START + 3, + MSG_EVT_CUSTOME_SET_WIFI_ROLE = PRIVATE_EVT_START + 4, + MSG_EVT_EDCA_ADJUST = PRIVATE_EVT_START + 5, + MSG_EVT_EDCA_QUERY = PRIVATE_EVT_START + 6, + MSG_EVT_NAV_PADDING = PRIVATE_EVT_START + 7, + MSG_EVT_NAV_PADDING_QUERY = PRIVATE_EVT_START + 8, + MSG_EVT_CUSTOM_CMD_DONE = PRIVATE_EVT_START + 9, + MSG_EVT_AMPDU_CFG = PRIVATE_EVT_START + 10, + MSG_EVT_AMPDU_QUERY = PRIVATE_EVT_START + 11, + MSG_EVT_COLDBOOT_CALI = PRIVATE_EVT_START + 12, + MSG_EVT_PDTHR_CFG = PRIVATE_EVT_START + 13, + MSG_EVT_PDTHR_QUERY = PRIVATE_EVT_START + 14, + MSG_EVT_POP_CFG = PRIVATE_EVT_START + 15, + MSG_EVT_POP_QUERY = PRIVATE_EVT_START + 16, + MSG_EVT_STATS_RPT_CFG = PRIVATE_EVT_START + 17, + MSG_EVT_STATS_RPT_NOTIFY = PRIVATE_EVT_START + 18, + MSG_EVT_CHNL_SW = PRIVATE_EVT_START + 19, + MSG_EVT_STA_ASOC_NOTIFY = PRIVATE_EVT_START + 20, + MSG_EVT_BCN_OPT_IES_CFG = PRIVATE_EVT_START + 21, + MSG_EVT_BCN_VDR_IE_CFG = PRIVATE_EVT_START + 22, + MSG_EVT_SET_AP_START_CHNL = PRIVATE_EVT_START + 23, + MSG_EVT_SET_CUS_CHNL_LIST = PRIVATE_EVT_START + 24, + MSG_EVT_GET_CUS_CHNL_LIST = PRIVATE_EVT_START + 25, +}; + +enum custom_type { + CUSTOM_CORE = 0, + CUSTOM_PHL = 1, + CUSTOM_MAX +}; + +/* + * #pragma pack(1) would set the structure as 1-byte alignment . + */ +#pragma pack(1) +struct rtw_custom_decrpt { + u32 evt_id; + u32 customer_id; + enum custom_type type; + u32 len; +}; +#pragma pack() + +struct rtw_phl_custom_ampdu_cfg { + u32 max_agg_time_32us; + u32 max_agg_num; +}; + +#endif /*_PHL_CUSTOM_DEF_H_*/ diff --git a/phl/custom/phl_custom_fb.c b/phl/custom/phl_custom_fb.c new file mode 100644 index 0000000..cc79c80 --- /dev/null +++ b/phl/custom/phl_custom_fb.c @@ -0,0 +1,479 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CUSTOMIZE_FEATURE_C_ +#include "../phl_headers.h" + +#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB +#include "phl_custom_fb.h" + +#define LLC_HDR_LENGTH 6 +#define SNAP_HDR_LENGTH 2 + +enum phl_mdl_ret_code +_is_fb_mode_valid(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg, u32 size) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + if (!fb_ctx->init.enable || cmd->len < size || fb_ctx->init.wifi_role == NULL) { + PHL_INFO(" %s, evt_id(%d) not accepted\n", + __FUNCTION__, + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + return ret; + } + //check chanctx if wifi_role exists + if (fb_ctx->init.wifi_role->chanctx == NULL) { + PHL_INFO(" %s, wifi_role->chanctx is NULL\n", __FUNCTION__); + fb_ctx->init.wifi_role = NULL; + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_feature_enable(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + + if (cmd->len < sizeof(u32)) + return MDL_RET_FAIL; + + fb_ctx->init.enable = *(u32*)(cmd + 1); + fb_ctx->init.test_mode = 0; + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&(fb_ctx->init.enable), + sizeof(u32)); + + return MDL_RET_SUCCESS; +} + +enum phl_mdl_ret_code +_custom_fb_feature_query(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + if (cmd->len < sizeof(u32)) + return ret; + PHL_INFO("%s, fb query feature enable(%d)\n", + __FUNCTION__, + fb_ctx->init.enable); + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&(fb_ctx->init.enable), + sizeof(u32)); + ret = MDL_RET_SUCCESS; + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_testmode_param(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + + if (cmd->len < sizeof(u32)) + return ret; + fb_ctx->init.test_mode = *(u32*)(cmd + 1); + PHL_INFO("%s, test mode(0x%x)\n", __FUNCTION__, + fb_ctx->init.test_mode); + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&ret, + sizeof(u8)); + + ret = MDL_RET_SUCCESS; + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_set_wifi_role(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u32 size = MAC_ADDRESS_LENGTH; + u8* val = (u8*)(cmd + 1); + + if (cmd->len < MAC_ADDRESS_LENGTH) + return ret; + if (!(fb_ctx->init.test_mode & FB_TEST_MODE_USE_STA_MAC)) + *val |= (BIT1 | BIT7); + PHL_INFO("val - MAC-Addr:%02x-%02x-%02x-%02x-%02x-%02x\n", + *val,*(val + 1),*(val + 2), + *(val + 3), *(val + 4),*(val + 5)); + fb_ctx->init.wifi_role = phl_get_wrole_by_addr(phl, val); + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&ret, + sizeof(u8)); + + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_ampdu_cfg(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + void *d = phl_to_drvpriv(phl); + struct rtw_phl_stainfo_t *phl_sta = NULL; + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + struct rtw_phl_custom_ampdu_cfg custom_fb_ampdu_cfg = {0}; + u32 size = sizeof(struct rtw_phl_custom_ampdu_cfg); + u8* val = (u8*)(cmd + 1); + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS) { + goto exit; + } + phl_sta = rtw_phl_get_stainfo_self(phl, fb_ctx->init.wifi_role); + _os_mem_cpy(d, &custom_fb_ampdu_cfg, val, size); + hal_status = rtw_hal_custom_cfg_tx_ampdu(phl->hal, + fb_ctx->init.wifi_role, + &custom_fb_ampdu_cfg); + phl_sta->asoc_cap.num_ampdu = (u8)custom_fb_ampdu_cfg.max_agg_num; + + PHL_INFO("%s, halsta(%d) ampdu dur(%d) num(%d)\n", + __FUNCTION__, + hal_status, + custom_fb_ampdu_cfg.max_agg_time_32us, + custom_fb_ampdu_cfg.max_agg_num); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + ret = MDL_RET_FAIL; +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&ret, + sizeof(u8)); + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_ampdu_query(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + struct rtw_phl_custom_ampdu_cfg custom_fb_ampdu_cfg = {0}; + u32 size = sizeof(struct rtw_phl_custom_ampdu_cfg); + + /* 0xffffffff is querying failed for SDK*/ + custom_fb_ampdu_cfg.max_agg_num = 0xffffffff; + custom_fb_ampdu_cfg.max_agg_time_32us = 0xffffffff; + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS) { + goto exit; + } + hal_status = rtw_hal_get_ampdu_cfg(phl->hal, + fb_ctx->init.wifi_role, + &custom_fb_ampdu_cfg); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + ret = MDL_RET_FAIL; + PHL_INFO(" %s, ampdu dur(%d) time(%d)\n", + __FUNCTION__, + custom_fb_ampdu_cfg.max_agg_time_32us, + custom_fb_ampdu_cfg.max_agg_num); +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&custom_fb_ampdu_cfg, + sizeof(struct rtw_phl_custom_ampdu_cfg)); + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_pdthr_cfg(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + int pd_thr = 0xff; + u32 size = sizeof(int); + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS) { + goto exit; + } + pd_thr = *(int*)(cmd + 1); + PHL_INFO("%s, pd_thr(%d)\n", __FUNCTION__, pd_thr); + PHL_INFO("%s, bw(%d) band(%d)\n", __FUNCTION__, + fb_ctx->init.wifi_role->chanctx->chan_def.bw, + fb_ctx->init.wifi_role->hw_band); + hal_status = rtw_hal_set_pkt_detect_thold(phl->hal, (u32)pd_thr); + PHL_INFO("%s, hal_status(%d)\n", __FUNCTION__, hal_status); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + ret = MDL_RET_FAIL; +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&ret, + sizeof(u8)); + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_pdthr_query(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + int pd_thr = 0xff; + u32 size = sizeof(int); + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS) { + goto exit; + } + /*confirm whether pd thr is enabling or not*/ + pd_thr = rtw_hal_query_pkt_detect_thold(phl->hal, + true, + fb_ctx->init.wifi_role->hw_band); + if (pd_thr == 0) { + PHL_INFO("%s, disable! pd_thr(%d)\n", __FUNCTION__, pd_thr); + } else { + pd_thr = rtw_hal_query_pkt_detect_thold(phl->hal, + false, + fb_ctx->init.wifi_role->hw_band); + PHL_INFO("%s, pd_thr(%d)\n", __FUNCTION__, pd_thr); + } +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&pd_thr, + sizeof(int)); + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_pop_cfg(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + u32 size = sizeof(u32); + u32 pop_enable = 0xff; + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS) { + goto exit; + } + pop_enable = *(u32*)(cmd + 1); + PHL_INFO("%s, pop_enable(%d)\n", __FUNCTION__, pop_enable); + if (pop_enable != 0xff) { + hal_status = rtw_hal_set_pop_en(phl->hal, + (bool)pop_enable, + fb_ctx->init.wifi_role->hw_band); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + ret = MDL_RET_FAIL; + } +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&ret, + sizeof(u8)); + return ret; +} + +enum phl_mdl_ret_code +_custom_fb_pop_query(void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf); + u32 size = sizeof(u32); + u32 pop_enable = 0xff; + + ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size); + if (ret != MDL_RET_SUCCESS){ + goto exit; + } + + pop_enable = rtw_hal_query_pop_en(phl->hal, fb_ctx->init.wifi_role->hw_band); + PHL_INFO("%s, pop_en(%d)\n", __FUNCTION__, pop_enable); +exit: + phl_custom_prepare_evt_rpt(custom_ctx, + cmd->evt_id, + cmd->customer_id, + (u8*)&pop_enable, + sizeof(u32)); + return ret; +} + +enum phl_mdl_ret_code +phl_custom_hdl_fb_evt(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u8 prephase = (IS_MSG_IN_PRE_PHASE(msg->msg_id)) ? (true) : (false); + + if (prephase == true) + return MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_CUSTOME_FEATURE_ENABLE: + ret = _custom_fb_feature_enable(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_CUSTOME_FEATURE_QUERY: + ret = _custom_fb_feature_query(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_CUSTOME_TESTMODE_PARAM: + ret = _custom_fb_testmode_param(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_CUSTOME_SET_WIFI_ROLE: + ret = _custom_fb_set_wifi_role(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_AMPDU_CFG: + ret = _custom_fb_ampdu_cfg(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_AMPDU_QUERY: + ret = _custom_fb_ampdu_query(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_PDTHR_CFG: + ret = _custom_fb_pdthr_cfg(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_PDTHR_QUERY: + ret = _custom_fb_pdthr_query(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_POP_CFG: + ret = _custom_fb_pop_cfg(custom_ctx, fb_ctx, msg); + break; + case MSG_EVT_POP_QUERY: + ret = _custom_fb_pop_query(custom_ctx, fb_ctx, msg); + break; + default: + ret = MDL_RET_SUCCESS; + break; + } + PHL_INFO("%s, evt(%d), ret(%d)\n", __FUNCTION__, + MSG_EVT_ID_FIELD(msg->msg_id), + ret); + return ret; +} +enum phl_mdl_ret_code +phl_custom_hdl_fb_fail_evt(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg) +{ + return MDL_RET_IGNORE; +} + +enum phl_mdl_ret_code +phl_custom_fb_update_opt_ie(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code status = MDL_RET_SUCCESS; + struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx); + void *d = phl_to_drvpriv(phl); + + if (info->outlen == 0) + return MDL_RET_FAIL; + _os_mem_cpy(d, info->outbuf, &fb_ctx->bcn_param, info->outlen); + + return status; +} + +enum phl_mdl_ret_code +phl_custom_fb_set_role_cap(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code status = MDL_RET_SUCCESS; + + FUNCIN(); + + fb_ctx->bcn_param.enable = true; + fb_ctx->bcn_param.cus_wmode = *(u8*)info->inbuf; + + FUNCOUT(); + + return status; +} + +enum rtw_phl_status +phl_custom_fb_init_role_cap(struct phl_info_t *phl_info, + u8 hw_band, + struct role_cap_t *role_cap) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct phl_module_op_info op_info = {0}; + struct _facebook_bcn_param bcn_param = {0}; + + op_info.op_code = BK_MODL_OP_CUS_UPDATE_ROLE_CAP; + op_info.outbuf = (u8*)&bcn_param; + op_info.outlen = sizeof(struct _facebook_bcn_param); + if (phl_disp_eng_query_bk_module_info(phl_info, + hw_band, + PHL_MDL_CUSTOM, + &op_info) == MDL_RET_SUCCESS) { + if (bcn_param.enable == true) { + role_cap->wmode &= bcn_param.cus_wmode; + } + PHL_INFO("%s, wmode(%d) cus_wmode(%d) enable(%d)\n", __FUNCTION__, + role_cap->wmode, + bcn_param.cus_wmode, + bcn_param.enable); + } else { + status = RTW_PHL_STATUS_FAILURE; + } + return status; +} +#endif diff --git a/phl/custom/phl_custom_fb.h b/phl/custom/phl_custom_fb.h new file mode 100644 index 0000000..4922bf7 --- /dev/null +++ b/phl/custom/phl_custom_fb.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CUSTOM_FB_H_ +#define _PHL_CUSTOM_FB_H_ + +#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB +#define TX_PKT_CYCLE (10) + +#define FC_QOS_BIT BIT7 +#define GET_80211_HDR_TO_DS(_hdr) LE_BITS_TO_2BYTE(_hdr, 8, 1) +#define GET_80211_HDR_FROM_DS(_hdr) LE_BITS_TO_2BYTE(_hdr, 9, 1) +#define GET_80211_HDR_WEP(_hdr) LE_BITS_TO_2BYTE(_hdr, 14, 1) +#define GET_80211_HDR_ORDER(_hdr) LE_BITS_TO_2BYTE(_hdr, 15, 1) +#define IS_DATA_FRAME(pdu) ( ((EF1Byte(pdu[0]) & 0x0C)==0x08) ? TRUE : FALSE ) +#define IS_QOS_DATA_FRAME(pdu) (IS_DATA_FRAME(pdu) && (EF1Byte(pdu[0]) & FC_QOS_BIT) ) + +enum _fackbook_test_mode { + FB_TEST_MODE_FAKE_TX_CYCLE = BIT0, + FB_TEST_MODE_USE_STA_MAC = BIT1, +}; + +struct _facebook_init_param { + u32 enable; + u32 test_mode; + struct rtw_wifi_role_t *wifi_role; +}; + +struct _facebook_bcn_param { + u32 enable; + u8 cus_wmode; +}; +struct _custom_facebook_ctx { + struct _facebook_init_param init; + struct _facebook_bcn_param bcn_param; +}; + +enum phl_mdl_ret_code +phl_custom_hdl_fb_evt(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg); +enum phl_mdl_ret_code +phl_custom_hdl_fb_fail_evt(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_msg* msg); + +enum phl_mdl_ret_code +phl_custom_fb_update_opt_ie(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_module_op_info* info); + +enum phl_mdl_ret_code +phl_custom_fb_set_role_cap(void* dispr, + void* custom_ctx, + struct _custom_facebook_ctx* fb_ctx, + struct phl_module_op_info* info); + +enum rtw_phl_status +phl_custom_fb_init_role_cap(struct phl_info_t *phl_info, + u8 hw_band, + struct role_cap_t *role_cap); +#else +#define phl_custom_fb_update_opt_ie(_dispr, _ctx, _fb_ctx, _info) (MDL_RET_SUCCESS) +#define phl_custom_fb_set_role_cap(_dispr, _ctx, _fb_ctx, _info) (RTW_PHL_STATUS_SUCCESS) +#define phl_custom_fb_init_role_cap(_phl_info, _hw_band, _role_cap) (RTW_PHL_STATUS_SUCCESS) +#endif + +#endif /*_PHL_CUSTOMIZE_FEATURE_H_*/ + diff --git a/phl/hal_g6/btc/btc.mk b/phl/hal_g6/btc/btc.mk new file mode 100644 index 0000000..6be0ded --- /dev/null +++ b/phl/hal_g6/btc/btc.mk @@ -0,0 +1,50 @@ +# All needed files would be added to _HAL_INTFS_FILES, and it would include +# hal_g6/btc and all related files in directory hal_g6/btc/. +# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC +# (CONFIG_RTL*) setting are all ready! + +HAL = hal_g6 + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/hal_g6 +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := hal_g6 +phl_path_d1 := $(src)/$(HAL) +endif + +# Base directory +path_halbtc_d1 := $(phl_path)/btc + +halbtc-y += $(path_halbtc_d1)/hal_btc.o \ + $(path_halbtc_d1)/halbtc_def.o \ + $(path_halbtc_d1)/halbtc_action.o \ + $(path_halbtc_d1)/halbtc_fw.o \ + $(path_halbtc_d1)/halbtc_dbg_cmd.o + +ifeq ($(CONFIG_RTL8852A), y) +ic := 8852a +# Level 2 directory +path_halbtc_8852a := $(path_halbtc_d1)/btc_$(ic) + +halbtc-y += $(path_halbtc_8852a)/btc_8852a.o + +endif + +ifeq ($(CONFIG_RTL8852B), y) +ic := 8852b +# Level 2 directory +path_halbtc_8852b := $(path_halbtc_d1)/btc_$(ic) + +halbtc-y += $(path_halbtc_8852b)/btc_8852b.o +endif + +ifeq ($(CONFIG_RTL8852C), y) +ic := 8852c +# Level 2 directory +path_halbtc_8852c := $(path_halbtc_d1)/btc_$(ic) + +halbtc-y += $(path_halbtc_8852c)/btc_8852c.o +endif + +_BTC_FILES += $(halbtc-y) diff --git a/phl/hal_g6/btc/btc_8852b/btc_8852b.c b/phl/hal_g6/btc/btc_8852b/btc_8852b.c new file mode 100644 index 0000000..5980d3c --- /dev/null +++ b/phl/hal_g6/btc/btc_8852b/btc_8852b.c @@ -0,0 +1,400 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_BTC_C_ + +#include "../../hal_headers_le.h" +#include "../hal_btc.h" + +#ifdef CONFIG_BTCOEX +#ifdef CONFIG_RTL8852B + +#include "btc_8852b.h" + +/* WL rssi threshold in % (dbm = % - 110) + * array size limit by BTC_WL_RSSI_THMAX + * BT rssi threshold in % (dbm = % - 100) + * array size limit by BTC_BT_RSSI_THMAX + */ +static const u8 btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; +static const u8 btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; + +static struct btc_chip_ops btc_8852b_ops = { + _8852b_rfe_type, + _8852b_init_cfg, + _8852b_wl_pri, + _8852b_wl_tx_power, + _8852b_wl_rx_gain, + _8852b_wl_s1_standby, + _8852b_wl_req_mac, + _8852b_update_bt_cnt, + _8852b_bt_rssi +}; + +/* Set WL/BT periodical moniter reg, Max size: CXMREG_MAX*/ +static struct fbtc_mreg btc_8852b_mon_reg[] = { + {REG_MAC, 4, 0xda24}, + {REG_MAC, 4, 0xda28}, + {REG_MAC, 4, 0xda2c}, + {REG_MAC, 4, 0xda30}, + {REG_MAC, 4, 0xda4c}, + {REG_MAC, 4, 0xda10}, + {REG_MAC, 4, 0xda20}, + {REG_MAC, 4, 0xda34}, + {REG_MAC, 4, 0xcef4}, + {REG_MAC, 4, 0x8424}, + {REG_MAC, 4, 0xd200}, + {REG_MAC, 4, 0xd220}, + {REG_BB, 4, 0x980}, + /*{REG_RF, 2, 0x2},*/ /* for RF, bytes->path, 1:A, 2:B... */ + /*{REG_RF, 2, 0x18},*/ + /*{REG_BT_RF, 2, 0x9},*/ + /*{REG_BT_MODEM, 2, 0xa} */ +}; + +/* wl_tx_power: 255->original, else-> bit7:signed bit, ex: 13:13dBm, 0x85:-5dBm + * wl_rx_gain: 0->original, 1-> for Free-run, 2-> for BTG co-rx + * bt_tx_power: decrease power, 0->original, 5 -> decreas 5dB. + * bt_rx_gain: BT LNA constrain Level, 7->original + */ + +struct btc_rf_trx_para btc_8852b_rf_ul[] = { + {255, 0, 0, 7}, /* 0 -> original */ + {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ + {6, 1, 0, 7}, + {13, 1, 0, 7}, + {13, 1, 0, 7} +}; + +struct btc_rf_trx_para btc_8852b_rf_dl[] = { + {255, 0, 0, 7}, /* 0 -> original */ + {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ + {255, 1, 0, 7}, + {255, 1, 0, 7}, + {255, 1, 0, 7} +}; + +const struct btc_chip chip_8852b = { + CHIP_WIFI6_8852B, /* chip id */ + 0x0, /* chip para ver */ + 0x6, /* desired bt_ver */ + 0x06010000, /* desired halbtc ver */ + 0x1, /* scoreboard version */ + 0x1, /* mailbox version*/ + BTC_COEX_RTK_MODE, /* pta_mode */ + BTC_COEX_INNER, /* pta_direction */ + 6, /* afh_guard_ch */ + btc_8852b_wl_rssi_thres, /* wl rssi threshold level */ + btc_8852b_bt_rssi_thres, /* bt rssi threshold level */ + (u8)2, /* rssi tolerance */ + &btc_8852b_ops, /* chip-dependent function */ + ARRAY_SIZE(btc_8852b_mon_reg), + btc_8852b_mon_reg, /* wl moniter register */ + ARRAY_SIZE(btc_8852b_rf_ul), + btc_8852b_rf_ul, + ARRAY_SIZE(btc_8852b_rf_dl), + btc_8852b_rf_dl +}; + +void _8852b_rfe_type(struct btc_t *btc) +{ + struct rtw_phl_com_t *p = btc->phl; + struct rtw_hal_com_t *h = btc->hal; + struct btc_module *module = &btc->mdinfo; + + PHL_INFO("[BTC], %s !! \n", __FUNCTION__); + + module->rfe_type = p->dev_cap.rfe_type;/* get from final capability of device */ + module->kt_ver = h->cv; + module->bt_solo = 0; + module->switch_type = BTC_SWITCH_INTERNAL; + +#if BTC_NON_SHARED_ANT_FREERUN + module->ant.num = 3; +#else + if (module->rfe_type > 0) + module->ant.num = (module->rfe_type % 2? 2 : 3); + else + module->ant.num = 2; +#endif + module->ant.diversity = 0; + module->ant.isolation = 10; + + if (module->ant.num == 3) { + module->ant.type = BTC_ANT_DEDICATED; + module->bt_pos = BTC_BT_ALONE; + } else { + module->ant.type = BTC_ANT_SHARED; + module->bt_pos = BTC_BT_BTG; + } +} + +void _8852b_wl_tx_power(struct btc_t *btc, u32 level) +{ + /* + * =========== All-Time WL Tx power control =========== + * (ex: all-time fix WL Tx 10dBm , don¡¦t care GNT _BT and GNT _LTE) + * Turn off per-packet power control + * 0xD220[1] = 0, 0xD220[2] = 0; + * + * disable using related power table + * 0xd208[20] = 0, 0xd208[21] = 0, 0xd21c[17] = 0, 0xd20c[29] = 0; + * + * enable force tx power mode and value + * 0xD200[9] = 1; + * 0xD200[8:0] = 0x28; S(9,2): 1step= 0.25dB, i.e. 40*0.25 = 10 dBm + * ======================================================= + * + * =========== per-packet Tx power control =========== + * (ex: GNT_BT = 1 -> 5dBm, GNT _BT = 0 -> 10dBm) + * Turn on per-packet power control + * 0xD220[1] = 1, 0xD220[2] = 0; + * 0xD220[11:3] = 0x14; S(9,2): 1step = 0.25dB, i.e. 20*0.25 = 5 dBm + * + * disable using related power table + * 0xd208[20] = 0, 0xd208[21] = 0, 0xd21c[17] = 0, 0xd20c[29] = 0; + * + * enable force tx power mode and value + * 0xD200[9] = 1; + * 0xD200[8:0] = 0x28; S(9,2), sign, 1 step = 0.25dB, i.e. 40*0.25 = 10 dBm + * ========================================================================= + * + * level define: + * if level = 255 -> back to original (btc don't control) + * else in dBm --> bit7->signed bit, ex: 0xa-> +10dBm, 0x85-> -5dBm + * pwr_val define: + bit15~0 --> All-time (GNT_BT = 0) Tx power control + bit31~16 --> Per-Packet (GNT_BT = 1) Tx power control + */ + u32 pwr_val; + + if (level == BTC_WL_DEF_TX_PWR) { /* back to original */ + pwr_val = bMASKDW; + } else { /* only apply "force tx power" */ + pwr_val = (level & 0x7f) << 2; /* to fit s(9,2) format */ + if (pwr_val > BTC_WL_DEF_TX_PWR) + pwr_val = BTC_WL_DEF_TX_PWR; + + if (level & BIT(7)) /* negative value */ + pwr_val |= BIT(8); /* to fit s(9,2) format */ + pwr_val |= bMASKHW; + } + + rtw_hal_rf_wl_tx_power_control(btc->hal, pwr_val); +} + +void _8852b_set_wl_lna2(struct btc_t *btc, u8 level) +{ + /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB + * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB + * To improve BT ACI in co-rx + */ +#if 0 /* RDC: disable this function for A-cut RxA TIA gain bug, + * it should be enabled for B-cut if nug fixed */ + switch (level) { + case 0: /* default */ + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x1000); + _write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x3); + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x17); + _write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x2); + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x15); + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0); + break; + case 1: /* Fix LNA2=5 */ + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x1000); + _write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x3); + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x5); + _write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x2); + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x15); + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0); + break; + } +#endif +} + +void _8852b_wl_rx_gain(struct btc_t *btc, u32 level) +{ + /* wl bb setting for FDD -> rtw_hal_bb_ctrl_btc_preagc() + * OP1db Back-off(no LNA6) + Fixed TIA corner + RX_BB Back-off + + * DFIR Type 3 + */ + + switch (level) { + case 0: /* original */ + rtw_hal_bb_ctrl_btc_preagc(btc->hal, false); + /* _8852b_set_wl_lna2(btc, 0); */ + break; + case 1: /* for FDD free-run */ + rtw_hal_bb_ctrl_btc_preagc(btc->hal, true); + /* _8852b_set_wl_lna2(btc, 0); */ + break; + case 2: /* for BTG Co-Rx*/ + rtw_hal_bb_ctrl_btc_preagc(btc->hal, false); + /* _8852b_set_wl_lna2(btc, 1); */ + break; + } +} + +u8 _8852b_bt_rssi(struct btc_t *btc, u8 val) +{ + val = (val <= 127? 100 : (val >= 156? val - 156 : 0)); + val = val + 6; /* compensate offset */ + + if (val > 100) + val = 100; + + return (val); +} + +void _8852b_set_wl_trx_mask(struct btc_t *btc, u8 path, u8 group, u32 val) +{ + _write_wl_rf_reg(btc, path, 0xef, bMASKRF, 0x20000); + _write_wl_rf_reg(btc, path, 0x33, bMASKRF, group); + _write_wl_rf_reg(btc, path, 0x3f, bMASKRF, val); + _write_wl_rf_reg(btc, path, 0xef, bMASKRF, 0x0); +} + +void _8852b_wl_s1_standby(struct btc_t *btc, u32 state) +{ + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x80000); + _write_wl_rf_reg(btc, RF_PATH_B, 0x33, bMASKRF, 0x1); + _write_wl_rf_reg(btc, RF_PATH_B, 0x3e, bMASKRF, 0x31); + + /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ + if (state == 1) + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x00579); + else + _write_wl_rf_reg(btc, RF_PATH_B, 0x3f, bMASKRF, 0x00020); + + _write_wl_rf_reg(btc, RF_PATH_B, 0xef, bMASKRF, 0x0); +} + +void _8852b_wl_req_mac(struct btc_t *btc, u8 mac_id) +{ + u32 val1; + + val1 = _read_cx_reg(btc, R_BTC_CFG); + + if (mac_id == HW_PHY_0) + val1 = val1 & (~B_BTC_WL_SRC); + else + val1 = val1 | B_BTC_WL_SRC; + + _write_cx_reg(btc, R_BTC_CFG, val1); +} + +void _8852b_update_bt_cnt(struct btc_t *btc) +{ + struct btc_cx *cx = &btc->cx; + u32 val, val1; + + val = _read_cx_reg(btc, R_BTC_BT_STAST_HIGH); + cx->cnt_bt[BTC_BCNT_HIPRI_TX] = val & bMASKLW; + cx->cnt_bt[BTC_BCNT_HIPRI_RX] = (val & bMASKHW) >> 16; + + val = _read_cx_reg(btc, R_BTC_BT_STAST_LOW); + cx->cnt_bt[BTC_BCNT_LOPRI_TX] = val & bMASKLW; + cx->cnt_bt[BTC_BCNT_LOPRI_RX] = (val & bMASKHW) >> 16; + + /* clock-gate off before reset counter*/ + val1 = _read_cx_reg(btc, R_BTC_CFG); + _write_cx_reg(btc, R_BTC_CFG, val1 | B_BTC_DIS_BTC_CLK_G); + + val = _read_cx_reg(btc, R_BTC_CSR_MODE); + _write_cx_reg(btc, R_BTC_CSR_MODE, val & (~B_BTC_BT_CNT_REST)); + _write_cx_reg(btc, R_BTC_CSR_MODE, val | B_BTC_BT_CNT_REST); + + _write_cx_reg(btc, R_BTC_CFG, val1 & (~B_BTC_DIS_BTC_CLK_G)); +} + +void _8852b_init_cfg(struct btc_t *btc) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_module *module = &btc->mdinfo; + u32 val = 0; + + PHL_INFO("[BTC], %s !! \n", __FUNCTION__); + + /* PTA init */ + rtw_hal_mac_coex_init(h, chip_8852b.pta_mode, chip_8852b.pta_direction); + + /* set WL Tx response = Hi-Pri */ + btc->chip->ops->wl_pri(btc, BTC_PRI_MASK_TX_RESP, true); + + /* set WL Tx beacon = Hi-Pri */ + btc->chip->ops->wl_pri(btc, BTC_PRI_MASK_BEACON, true); + + /* set rf gnt debug off*/ + _write_wl_rf_reg(btc, RF_PATH_A, 0x2, bMASKRF, 0x0); + _write_wl_rf_reg(btc, RF_PATH_B, 0x2, bMASKRF, 0x0); + + /* set WL Tx thru in TRX mask table if GNT_WL=0 && BT_S1=ss group */ + if (module->ant.type == BTC_ANT_SHARED) { + _8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); + _8852b_set_wl_trx_mask(btc, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); + /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ + _8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); + } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ + _8852b_set_wl_trx_mask(btc, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); + _8852b_set_wl_trx_mask(btc, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); + } + + /* set PTA break table */ + _write_cx_reg(btc, R_BTC_BREAK_TABLE, 0xf0ffffff); + + /* enable BT counter 0xda40[16,2] = 2b'11 */ + val = _read_cx_reg(btc, R_BTC_CSR_MODE); + _write_cx_reg(btc, R_BTC_CSR_MODE, val | BIT16 | BIT2); +} + +void _8852b_wl_pri (struct btc_t *btc, u8 map, bool state) +{ + u32 reg = 0, bitmap = 0, val = 0; + + switch (map) { + case BTC_PRI_MASK_TX_RESP: + reg = R_BTC_BT_COEX_MSK_TABLE; + bitmap = B_BTC_PRI_MASK_TX_RESP_V1; + break; + case BTC_PRI_MASK_BEACON: + reg = R_BTC_WL_PRI_MSK; + bitmap = B_BTC_PTA_WL_PRI_MASK_BCNQ; + break; + case BTC_PRI_MASK_RX_CCK: + reg = R_BTC_BT_COEX_MSK_TABLE; + bitmap = B_BTC_PRI_MASK_RXCCK_V1; + break; + } + + val = _read_cx_reg(btc, reg); + if (state) + val = val | bitmap; + else + val = val & (~bitmap); + + _write_cx_reg(btc, reg, val); +} + +#endif /* CONFIG_RTL8852B */ +#endif + + diff --git a/phl/hal_g6/btc/btc_8852b/btc_8852b.h b/phl/hal_g6/btc/btc_8852b/btc_8852b.h new file mode 100644 index 0000000..dfd292d --- /dev/null +++ b/phl/hal_g6/btc/btc_8852b/btc_8852b.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8852B_BTC_H__ +#define __RTL8852B_BTC_H__ +/* rtl8852b_btc.c */ + +extern const struct btc_chip chip_8852b; +void _8852b_rfe_type(struct btc_t *btc); +void _8852b_init_cfg(struct btc_t *btc); +void _8852b_wl_pri (struct btc_t *btc, u8 map, bool state); +void _8852b_wl_tx_power(struct btc_t *btc, u32 level); +void _8852b_wl_rx_gain(struct btc_t *btc, u32 level); +void _8852b_wl_s1_standby(struct btc_t *btc, u32 state); +void _8852b_wl_req_mac(struct btc_t *btc, u8 mac_id); +void _8852b_update_bt_cnt(struct btc_t *btc); +u8 _8852b_bt_rssi(struct btc_t *btc, u8 val); +#endif /*__RTL8852B_PHY_H__*/ diff --git a/phl/hal_g6/btc/hal_btc.c b/phl/hal_g6/btc/hal_btc.c new file mode 100644 index 0000000..37609d9 --- /dev/null +++ b/phl/hal_g6/btc/hal_btc.c @@ -0,0 +1,1803 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_BTC_C_ +#include "../hal_headers_le.h" +#include "hal_btc.h" +#include "halbtc_fw.h" +#include "halbtc_def.h" +#include "halbtc_action.h" + +#ifdef CONFIG_BTCOEX + +/* [31:24] -> main-version + * [23:16] -> sub-version + * [15:8] -> Hot-Fix-version + * [7:0] -> branch ID, ex: 0x00-> Main-Branch + * Modify bt_8852x.c chip_8852x member: btcx_desired, wlcx_desired if required + * btcx_desired: BT FW coex version -> main-version + 1 if update. + * wlcx_desired: WL FW coex version -> sub-version + 1 if update + */ +const u32 coex_ver = 0x0601010f; + +static struct btc_ops _btc_ops = { + _send_fw_cmd, + _ntfy_power_on, + _ntfy_power_off, + _ntfy_init_coex, + _ntfy_scan_start, + _ntfy_scan_finish, + _ntfy_switch_band, + _ntfy_specific_packet, + _ntfy_role_info, + _ntfy_radio_state, + _ntfy_customerize, + _ntfy_wl_rfk, + _ntfy_wl_sta, + _ntfy_fwinfo, + _ntfy_timer +}; + +#define _update_dbcc_band(phy_idx) \ + btc->cx.wl.dbcc_info.real_band[phy_idx] =\ + (btc->cx.wl.scan_info.phy_map & BIT(phy_idx) ?\ + btc->cx.wl.dbcc_info.scan_band[phy_idx] :\ + btc->cx.wl.dbcc_info.op_band[phy_idx]) + +/****************************************************************************** + * + * coex internal functions + * + *****************************************************************************/ +static void _set_btc_timer(struct btc_t *btc, u16 tmr_id, u32 ms) +{ + struct btc_tmr *btmr = NULL; + + if (tmr_id < BTC_TIMER_MAX) { + btmr = &btc->timer[tmr_id]; + _os_set_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr, ms); + } +} + +static void _btmr_stop(struct btc_t *btc) +{ + struct btc_tmr *btmr = NULL; + u8 i = 0; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): stop btc timers!!\n", + __func__); + + btc->tmr_stop = true; + + for (i = 0; i < BTC_TIMER_MAX; i++) { + btmr = &btc->timer[i]; + _os_cancel_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr); + } + _os_cancel_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr); +} + +static void _btmr_release(struct btc_t *btc) +{ + struct btc_tmr *btmr = NULL; + u8 i = 0; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): release btc timers!!\n", + __func__); + + for (i = 0; i < BTC_TIMER_MAX; i++) { + btmr = &btc->timer[i]; + _os_release_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr); + } + _os_release_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr); +} + +static void _btmr_start(struct btc_t *btc) +{ + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): start btc periodic timer!!\n", + __func__); + + btc->tmr_stop = false; + + /* Wait 2 sec for phl starting then periodic timer will be started */ + _os_set_timer(halcom_to_drvpriv(btc->hal), + &btc->delay_tmr, BTC_DELAYED_PERIODIC_TIME); +} + +static void _delay_tmr_cb(void *ctx) +{ + struct btc_t *btc = NULL; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s() !!\n", __func__); + + if (!ctx) + return; + + btc = (struct btc_t *)ctx; + + _set_btc_timer(btc, BTC_TIMER_PERIODIC, BTC_PERIODIC_TIME); +} + +static void _btmr_cb(void *ctx) +{ + struct btc_tmr *btmr = NULL; + struct btc_t *btc = NULL; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(), ctx = 0x%p !!\n", + __func__, ctx); + + if (!ctx) + return; + + btmr = (struct btc_tmr *)ctx; + btc = (struct btc_t *)btmr->btc; + + if (!btc->tmr_init || btc->tmr_stop) + return; + + hal_btc_send_event(btc, (u8 *)btmr, sizeof(struct btc_tmr *), + BTC_HMSG_TMR_EN); +} + +static void _btmr_init(struct btc_t *btc) +{ + struct btc_tmr *btmr = NULL; + u8 i = 0; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): !!\n", __func__); + + for (i = 0; i < BTC_TIMER_MAX; i++) { + btmr = &btc->timer[i]; + btmr->btc = btc; + btmr->id = i; + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], init btc timer(%d) = 0x%p !!\n", i, btmr); + _os_init_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr, + _btmr_cb, btmr, "btc_tmr"); + } + + _os_init_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr, + _delay_tmr_cb, btc, NULL); + + btc->tmr_init = true; + btc->tmr_stop = true; +} + +static void _btmr_deinit(struct btc_t *btc) +{ + if (btc->tmr_init) { + _btmr_stop(btc); + _btmr_release(btc); + btc->tmr_init = false; + } +} + +static void +_send_fw_cmd(struct btc_t *btc, u8 h2c_class, u8 h2c_func, u8 *param, u16 len) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_wl_info *wl = &btc->cx.wl; + struct rtw_g6_h2c_hdr hdr = {0}; + + hdr.h2c_class = h2c_class; + hdr.h2c_func = h2c_func; + hdr.type = H2CB_TYPE_DATA; + hdr.content_len = len; + hdr.done_ack = 1; + + if (!wl->status.map.init_ok) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return by btc not init!!\n", + __func__); + btc->fwinfo.cnt_h2c_fail++; + return; + } else if ((wl->status.map.rf_off_pre == 1 && + wl->status.map.rf_off == 1) || + (wl->status.map.lps_pre == 1 && + wl->status.map.lps == 1)) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return by wl off!!\n", + __func__); + btc->fwinfo.cnt_h2c_fail++; + return; + } + + btc->fwinfo.cnt_h2c++; + + if (rtw_hal_mac_send_h2c(h, &hdr, (u32 *)param) != 0) + btc->fwinfo.cnt_h2c_fail++; +} + +u32 _read_cx_reg(struct btc_t *btc, u32 offset) +{ + u32 val = 0; + rtw_hal_mac_coex_reg_read(btc->hal, offset, &val); + return val; +} + +u8 _read_cx_ctrl(struct btc_t *btc) +{ + u32 val = 0; + rtw_hal_mac_get_coex_ctrl(btc->hal, &val); + + return ((u8)val); +} + +u32 _read_scbd(struct btc_t *btc) +{ + const struct btc_chip *chip = btc->chip; + u32 scbd_val = 0; + + if (!chip->scbd) + return 0; + + rtw_hal_mac_get_scoreboard(btc->hal, &scbd_val); + + PHL_INFO("[BTC], read scbd : 0x%08x \n", scbd_val); + btc->cx.cnt_bt[BTC_BCNT_SCBDREAD]++; + return (scbd_val); +} + +void _write_scbd(struct btc_t *btc, u32 val, bool state) +{ + const struct btc_chip *chip = btc->chip; + struct btc_wl_info *wl = &btc->cx.wl; + u32 scbd_val = 0; + + if (!chip->scbd) + return; + + /* only use bit23~0 */ + scbd_val = (state ? (wl->scbd | val) : (wl->scbd & (~val))); + + if (scbd_val != wl->scbd) { + rtw_hal_mac_set_scoreboard(btc->hal, &scbd_val); + PHL_INFO("[BTC], write scbd : 0x%08x \n", scbd_val); + wl->scbd = scbd_val; + + btc->cx.cnt_wl[BTC_WCNT_SCBDUPDATE]++; + _os_delay_us(btc->hal, 1000); /* avoid BT FW loss information */ + } +} + +static u8 +_update_rssi_state(struct btc_t *btc, u8 pre_state, u8 rssi, u8 thresh) +{ + u8 next_state, tol = btc->chip->rssi_tol; + + if (pre_state == BTC_RSSI_ST_LOW || + pre_state == BTC_RSSI_ST_STAY_LOW) { + if (rssi >= (thresh + tol)) + next_state = BTC_RSSI_ST_HIGH; + else + next_state = BTC_RSSI_ST_STAY_LOW; + } else { + if (rssi < thresh) + next_state = BTC_RSSI_ST_LOW; + else + next_state = BTC_RSSI_ST_STAY_HIGH; + } + + return next_state; +} + +void _write_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr, u32 val) +{ + u8 buf[4] = {0}; + + /* set write address */ + buf[0] = reg_type; + buf[1] = addr & bMASKB0; + buf[2] = (addr & bMASKB1) >> 8; + hal_btc_fw_set_bt(btc, SET_BT_WREG_ADDR, 3, buf); + + /* set write value */ + buf[0] = val & bMASKB0; + buf[1] = (val & bMASKB1) >> 8; + buf[2] = (val & bMASKB2) >> 16; + buf[3] = (val & bMASKB3) >> 23; + hal_btc_fw_set_bt(btc, SET_BT_WREG_VAL, 4, buf); +} + +void _read_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr) +{ + /* this function is only for API call. + * If BTC should use hal_btc_fw_set_monreg to read bt reg. + */ + u8 buf[3] = {0}; + + /* set write address */ + buf[0] = reg_type; + buf[1] = addr & bMASKB0; + buf[2] = (addr & bMASKB1) >> 8; + hal_btc_fw_set_bt(btc, SET_BT_RREG_ADDR, sizeof(buf), buf); + + /* To do wait FW event -> BTF_EVNT_BT_REG*/ +} + +void _set_bt_psd_report(struct btc_t *btc, u8 start_idx, u8 rpt_type) +{ + u8 buf[2] = {0}; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): set bt psd\n", + __func__); + + buf[0] = start_idx; + buf[1] = rpt_type; + hal_btc_fw_set_bt(btc, SET_BT_PSD_REPORT, 2, buf); +} + +static void _set_bt_info_report(struct btc_t *btc, u8 trigger) +{ + u8 buf = 0; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): query bt info\n", + __func__); + + buf = trigger; + hal_btc_fw_set_bt(btc, SET_BT_INFO_REPORT, 1, &buf); +} + +static void _reset_btc_var(struct btc_t *btc, u8 type) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_info *bt = &cx->bt; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + struct btc_wl_link_info *wl_linfo = wl->link_info; + u8 i; + + PHL_INFO("[BTC], %s()\n", __func__); + + /* Reset Coex variable */ + if (type & BTC_RESET_CX) + hal_mem_set(h, cx, 0, sizeof(struct btc_cx)); + else if (type & BTC_RESET_BTINFO) /* only for BT enable */ + hal_mem_set(h, bt, 0, sizeof(struct btc_bt_info)); + + if (type & BTC_RESET_CTRL) + hal_mem_set(h, &btc->ctrl, 0, sizeof(struct btc_ctrl)); + + /* Init Coex variables that are not zero */ + if (type & BTC_RESET_DM) { + hal_mem_set(h, &btc->dm, 0, sizeof(struct btc_dm)); + hal_mem_set(h, bt_linfo->rssi_state, 0, BTC_BT_RSSI_THMAX); + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) + hal_mem_set(h, wl_linfo[i].rssi_state, 0, + BTC_WL_RSSI_THMAX); + + /* set the slot_now table to original */ + _tdma_cpy(&btc->dm.tdma_now, &t_def[CXTD_OFF]); + _tdma_cpy(&btc->dm.tdma, &t_def[CXTD_OFF]); + _slots_cpy(btc->dm.slot_now, s_def); + _slots_cpy(btc->dm.slot, s_def); + btc->policy_len = 0; + btc->bt_req_len = 0; + btc->hubmsg_cnt = 0; + + btc->dm.coex_info_map = BTC_COEX_INFO_ALL; + btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF; + btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF; + } + + if (type & BTC_RESET_MDINFO) + hal_mem_set(h, &btc->mdinfo, 0, sizeof(struct btc_module)); +} + +static bool _chk_wl_rfk_request(struct btc_t *btc) +{ + struct btc_cx *cx = &btc->cx; + struct btc_bt_info *bt = &cx->bt; + + _update_bt_scbd(btc, true); + + cx->cnt_wl[BTC_WCNT_RFK_REQ]++; + + if ((bt->rfk_info.map.run || bt->rfk_info.map.req) && + (!bt->rfk_info.map.timeout)) { + cx->cnt_wl[BTC_WCNT_RFK_REJECT]++; + return BTC_WRFK_REJECT; + } else { + cx->cnt_wl[BTC_WCNT_RFK_GO]++; + return BTC_WRFK_ALLOW; + } +} + +void _set_init_info(struct btc_t *btc) +{ + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &btc->cx.wl; + + dm->init_info.wl_only = (u8)dm->wl_only; + dm->init_info.bt_only = (u8)dm->bt_only; + dm->init_info.wl_init_ok = (u8)wl->status.map.init_ok; + dm->init_info.dbcc_en = btc->hal->dbcc_en; + dm->init_info.cx_other = btc->cx.other.type; + dm->init_info.wl_guard_ch = btc->chip->afh_guard_ch; + dm->init_info.module = btc->mdinfo; +} + +u8 _get_role_link_mode(struct btc_t *btc, u8 role) +{ + switch(role) { + case PHL_RTYPE_STATION: + return BTC_WLINK_2G_STA; + case PHL_RTYPE_P2P_GO: + return BTC_WLINK_2G_GO; + case PHL_RTYPE_P2P_GC: + return BTC_WLINK_2G_GC; + case PHL_RTYPE_AP: + return BTC_WLINK_2G_AP; + default: + return BTC_WLINK_OTHER; + } +} + +u8 _get_wl_role_idx(struct btc_t *btc, u8 role) +{ + struct btc_wl_role_info *wl_rinfo = &btc->cx.wl.role_info; + u8 i, pid = 0; + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + if (wl_rinfo->active_role[i].role == role) + break; + } + + pid = i; + return pid; /*cation: return MAX_WIFI_ROLE_NUMBER if role not found */ +} + +void _set_wl_req_mac(struct btc_t *btc, u8 mac_id) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_chip_ops *ops = btc->chip->ops; + + if (mac_id == wl->pta_req_mac) + return; + + if (ops && ops->wl_req_mac) + ops->wl_req_mac(btc, mac_id); + + wl->pta_req_mac = mac_id; +} + +static bool _chk_role_ch_group(struct btc_t *btc, struct rtw_chan_def r1, struct rtw_chan_def r2) +{ + bool is_grouped = false; + + if (r1.chan != r2.chan) { + /* primary ch is different */ + goto exit; + } else if (r1.bw == CHANNEL_WIDTH_40 && r2.bw == CHANNEL_WIDTH_40) { + if (r1.offset != r2.offset) + goto exit; + } + + is_grouped = true; + +exit: + return is_grouped; +} + +static void _update_wl_info(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_link_info *wl_linfo = wl->link_info; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; + struct btc_wl_active_role *active_role = NULL; + struct rtw_hal_com_t *h = btc->hal; + struct rtw_chan_def cid_ch[MAX_WIFI_ROLE_NUMBER]; + u8 i, j, k, cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; + u8 cnt_2g = 0, cnt_5g = 0, max_role_cnt = BTC_TDMA_WLROLE_MAX; + u8 cid_phy[MAX_WIFI_ROLE_NUMBER] = {0}; + u8 cid_role[MAX_WIFI_ROLE_NUMBER] = {0}; + u8 dbcc_2g_phy = 0, dbcc_2g_cid = 0, dbcc_2g_role = 0; + u32 noa_duration = 0; + bool b2g = false, b5g = false, client_joined = false, noa_exist = false; + + hal_mem_set(h, wl_rinfo, 0, sizeof(struct btc_wl_role_info)); + hal_mem_set(h, wl_dinfo, 0, sizeof(struct btc_wl_dbcc_info)); + hal_mem_set(h, cid_ch, 0, MAX_WIFI_ROLE_NUMBER * sizeof(struct rtw_chan_def)); + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + /* check if role active? */ + if (!wl_linfo[i].active || wl_linfo[i].phy >= HW_PHY_MAX) + continue; + + cnt_active++; + active_role = &wl_rinfo->active_role[cnt_active-1]; + active_role->role = wl_linfo[i].role; + active_role->pid = wl_linfo[i].pid; + active_role->phy = wl_linfo[i].phy; + active_role->band = wl_linfo[i].chdef.band; + active_role->noa = (u8)wl_linfo[i].noa; + active_role->noa_duration = wl_linfo[i].noa_duration/1000; + + /* check if role connect? */ + if (wl_linfo[i].connected == MLME_NO_LINK) { + wl_rinfo->active_role[cnt_active-1].connected = 0; + continue; + } else if (wl_linfo[i].connected == MLME_LINKING) { + cnt_connecting++; + } else { + cnt_connect++; + /* only if client connect for p2p-Go/AP */ + if ((wl_linfo[i].role == PHL_RTYPE_P2P_GO || + wl_linfo[i].role == PHL_RTYPE_AP) && + wl_linfo[i].client_cnt > 1) + client_joined = true; + + cid_phy[cnt_connect-1] = wl_linfo[i].phy; + hal_mem_cpy(h, &cid_ch[cnt_connect-1], + &wl_linfo[i].chdef, sizeof(struct rtw_chan_def)); + + cid_role[cnt_connect-1] = wl_linfo[i].role; + } + + wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); + active_role->ch = wl_linfo[i].chdef.center_ch; + active_role->bw = wl_linfo[i].chdef.bw; + active_role->connected = 1; + + /* only one noa-role exist */ + if (active_role->noa && active_role->noa_duration > 0) { + noa_exist = true; + noa_duration = active_role->noa_duration; + } + + /* Check dbcc role,the last role may overwrite the former role, + * This will be modified in the below code. + */ + if (h->dbcc_en) { + wl_dinfo->role[wl_linfo[i].phy] = wl_linfo[i].role; + wl_dinfo->op_band[wl_linfo[i].phy] = wl_linfo[i].chdef.band; + max_role_cnt = BTC_TDMA_WLROLE_MAX + 1; + } + + if (wl_linfo[i].chdef.band != BAND_ON_24G) { + cnt_5g++; + b5g = true; + } else { + cnt_2g++; + b2g = true; + } + } + + wl_rinfo->connect_cnt = cnt_connect; + + /* Be careful to change the following sequence!! */ + if (cnt_connect == 0) { + wl_rinfo->link_mode = BTC_WLINK_NOLINK; + wl_rinfo->role_map.role.none = 1; + } else if (!b2g && b5g) { + wl_rinfo->link_mode = BTC_WLINK_5G; + } else if (wl_rinfo->role_map.role.nan) { + wl_rinfo->link_mode = BTC_WLINK_2G_NAN; + } else if (cnt_connect > max_role_cnt) { + wl_rinfo->link_mode = BTC_WLINK_OTHER; + } else if (h->dbcc_en) { + /* find out the 2G-PHY by connect-id ->ch */ + for (j = 0; j < cnt_connect; j++) { + if (cid_ch[j].center_ch <= 14 || j == cnt_connect-1) + break; + } + + dbcc_2g_cid = j; + dbcc_2g_phy = cid_phy[j]; + dbcc_2g_role = cid_role[j]; + + /* find out the other role in the 2.4G_band-PHY*/ + if (cnt_connect == 3) { + for (k = 0; k < cnt_connect; k++) { + if (k == j) + continue; + else if (cid_phy[k] == dbcc_2g_phy) + break; + } + + if (k < cnt_connect) { /* if find -> DBCC + MCC/SCC */ + if (cid_ch[k].center_ch > 14) + wl_rinfo->link_mode = BTC_WLINK_25G_MCC; + else if (_chk_role_ch_group(btc, cid_ch[j], cid_ch[k])) + wl_rinfo->link_mode = BTC_WLINK_2G_SCC; + else + wl_rinfo->link_mode = BTC_WLINK_2G_MCC; + + /* correct 2G-located PHY role/band + * for gnt ctrl. + */ + wl_dinfo->role[dbcc_2g_phy] = dbcc_2g_role; + wl_dinfo->op_band[dbcc_2g_phy] = BAND_ON_24G; + goto exit; + } + } + + wl_rinfo->link_mode = _get_role_link_mode(btc, cid_role[j]); + } else if (b2g && b5g && cnt_connect == 2) { + wl_rinfo->link_mode = BTC_WLINK_25G_MCC; + } else if (!b5g && cnt_connect == 2) { /* cnt_connect = 2 */ + if (_chk_role_ch_group(btc, cid_ch[0], cid_ch[cnt_connect - 1])) + wl_rinfo->link_mode = BTC_WLINK_2G_SCC; + else + wl_rinfo->link_mode= BTC_WLINK_2G_MCC; + } else if (!b5g && cnt_connect == 1) { /* cnt_connect = 1 */ + wl_rinfo->link_mode = _get_role_link_mode(btc, cid_role[0]); + } + + /* if no client_joined, don't care P2P-GO/AP role */ + if ((wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) && + !client_joined) { +#if 0 /* work-around for Go/AP(no-client) can not move channel to same as STA*/ + if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || + wl_rinfo->link_mode == BTC_WLINK_2G_MCC) +#else + if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC) +#endif + + { + wl_rinfo->link_mode = BTC_WLINK_2G_STA; + wl_rinfo->connect_cnt--; + } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || + wl_rinfo->link_mode == BTC_WLINK_2G_AP) { + wl_rinfo->link_mode = BTC_WLINK_NOLINK; + wl_rinfo->connect_cnt--; + } + } + +exit: + /* Identify 2-Role type */ + if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || + wl_rinfo->link_mode == BTC_WLINK_2G_MCC || + wl_rinfo->link_mode == BTC_WLINK_25G_MCC || + (wl_rinfo->link_mode == BTC_WLINK_5G && cnt_connect > 1)) { + if (wl_rinfo->role_map.role.p2p_go || + wl_rinfo->role_map.role.ap) { + if (noa_exist) + wl_rinfo->mrole_type = BTC_WLMROLE_STA_GO_NOA; + else + wl_rinfo->mrole_type = BTC_WLMROLE_STA_GO; + } else if (wl_rinfo->role_map.role.p2p_gc) { + if (noa_exist) + wl_rinfo->mrole_type = BTC_WLMROLE_STA_GC_NOA; + else + wl_rinfo->mrole_type = BTC_WLMROLE_STA_GC; + } else { + wl_rinfo->mrole_type = BTC_WLMROLE_STA_STA; + } + + wl_rinfo->mrole_noa_duration = noa_duration; + } else { + wl_rinfo->mrole_type = BTC_WLMROLE_NONE; + wl_rinfo->mrole_noa_duration = 0; + } + + hal_btc_fw_set_drv_info(btc, CXDRVINFO_ROLE); + + if (h->dbcc_en) { + _set_wl_req_mac(btc, dbcc_2g_phy); + _update_dbcc_band(HW_PHY_0); + _update_dbcc_band(HW_PHY_1); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC); + } else { + _set_wl_req_mac(btc, HW_PHY_0); + } +} + +void _run_coex(struct btc_t *btc, const char *reason) +{ + struct btc_dm *dm = &btc->dm; + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_info *bt = &cx->bt; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + u8 mode = wl_rinfo->link_mode; + + PHL_INFO("[BTC], %s(): reason = %s, mode=%d\n", __func__, reason, mode); + _rsn_cpy(dm->run_reason, (char*)reason); + _update_dm_step(btc, reason); + +#if BTC_CX_FW_OFFLOAD + if (wl->rfk_info.state != BTC_WRFK_STOP && mode != BTC_WLINK_5G) { + _action_wl_rfk(btc); + } else if (wl->rfk_info.state == BTC_WRFK_STOP) { + PHL_INFO("[BTC], %s(): offload to WL_FW\n", __func__); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_SMAP); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_RUN); + } + + goto exit; +#else + + _update_btc_state_map(btc); + _get_wl_nhm_dbm(btc); + + /* Be careful to change the following function sequence!! */ + if (btc->ctrl.manual) { + PHL_INFO("[BTC], %s(): return for Manual CTRL!!\n", __func__); + return; + } + + if (btc->ctrl.igno_bt && + (run_rsn("_update_bt_info") || run_rsn("_update_bt_scbd"))) { + PHL_INFO("[BTC], %s(): return for Stop Coex DM!!\n", __func__); + return; + } + + if (!wl->status.map.init_ok) { + PHL_INFO("[BTC], %s(): return for WL init fail!!\n", __func__); + return; + } + + if (wl->status.map.rf_off_pre == wl->status.map.rf_off && + wl->status.map.lps_pre == wl->status.map.lps) { + if (run_rsn("_ntfy_power_off") || + run_rsn("_ntfy_radio_state")) { + PHL_INFO("[BTC], %s(): return for WL rf off state no change!!\n", + __func__); + return; + } + + if (wl->status.map.rf_off == 1 || wl->status.map.lps == 1) { + PHL_INFO("[BTC], %s(): return for WL rf off state!!\n", + __func__); + return; + } + } + + dm->cnt_dm[BTC_DCNT_RUN]++; + dm->freerun = false; + btc->ctrl.igno_bt = false; + bt->scan_rx_low_pri = false; + + if (btc->ctrl.always_freerun) { + _action_freerun(btc); + btc->ctrl.igno_bt = true; + goto exit; + } + + if (dm->wl_only) { + _action_wl_only(btc); + btc->ctrl.igno_bt = true; + goto exit; + } + + if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { + _action_wl_off(btc); + btc->ctrl.igno_bt = true; + goto exit; + } + + if (run_rsn("_ntfy_init_coex")) { + _action_wl_init(btc); + goto exit; + } + + if (!cx->bt.enable.now && !cx->other.type) { + _action_bt_off(btc); + goto exit; + } + + if (cx->bt.whql_test) { + _action_bt_whql(btc); + goto exit; + } + + if (wl->rfk_info.state != BTC_WRFK_STOP) { + _action_wl_rfk(btc); + goto exit; + } + + if (cx->state_map == BTC_WLINKING && + (mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_2G_STA || + mode == BTC_WLINK_5G)) { + _action_wl_scan(btc); + goto exit; + } + + if (wl->status.map.scan) { + _action_wl_scan(btc); + goto exit; + } + + switch (mode) { + case BTC_WLINK_NOLINK: + _action_wl_nc(btc); + break; + case BTC_WLINK_2G_STA: + _action_wl_2g_sta(btc); + break; + case BTC_WLINK_2G_AP: + bt->scan_rx_low_pri = true; + _action_wl_2g_ap(btc); + break; + case BTC_WLINK_2G_GO: + bt->scan_rx_low_pri = true; + _action_wl_2g_go(btc); + break; + case BTC_WLINK_2G_GC: + bt->scan_rx_low_pri = true; + _action_wl_2g_gc(btc); + break; + case BTC_WLINK_2G_SCC: + bt->scan_rx_low_pri = true; + _action_wl_2g_scc(btc); + break; + case BTC_WLINK_2G_MCC: + bt->scan_rx_low_pri = true; + _action_wl_2g_mcc(btc); + break; + case BTC_WLINK_25G_MCC: + bt->scan_rx_low_pri = true; + _action_wl_25g_mcc(btc); + break; + case BTC_WLINK_5G: + _action_wl_5g(btc); + break; + case BTC_WLINK_2G_NAN: + _action_wl_2g_nan(btc); + break; + default: + _action_wl_other(btc); + break; + } +#endif +exit: + _action_common(btc); +} + +static void _update_offload_runinfo(struct btc_t *btc, u8 *buf, u32 len) +{ +#if BTC_CX_FW_OFFLOAD + u32 val; + struct btc_cxr_result *r = NULL; + + if (!buf || buf[0] >= BTC_CXR_MAX) + return; + + switch(buf[0]) { + case BTC_CXR_WSCBD: + val = (buf[4] << 24) + (buf[3] << 16) + (buf[2] << 8) + buf[1]; + if (val & BIT(31)) /* if val & BIT(31) --> write scbd bit false */ + _write_scbd(btc, val & 0x7fffffff, false); + else + _write_scbd(btc, val, true); + break; + case BTC_CXR_RESULT: + r = (struct btc_cxr_result*) &buf[1]; + + btc->dm.freerun = r->dm.freerun; + btc->dm.wl_ps_ctrl = r->dm.wl_ps_ctrl; + btc->dm.leak_ap = r->dm.leak_ap; + btc->ctrl.igno_bt = (u16)r->dm.igno_bt; + btc->dm.noisy_level = r->dm.noisy_level; + btc->dm.set_ant_path = r->dm.set_ant_path; + + btc->dm.rf_trx_para = r->rf_trx_para; + btc->cx.state_map = r->cx_state_map; + btc->policy_type = (u16)r->policy_type; + btc->dm.cnt_dm[BTC_DCNT_RUN] = r->run_cnt; + + hal_mem_cpy(btc->hal, btc->dm.run_reason, r->run_reason, + BTC_RSN_MAXLEN); + hal_mem_cpy(btc->hal, btc->dm.run_action, r->run_action, + BTC_ACT_MAXLEN); + break; + } +#endif +} + +void _update_bt_scbd(struct btc_t *btc, bool only_update) +{ + struct btc_cx *cx = &btc->cx; + struct btc_bt_info *bt = &cx->bt; + u32 val; + bool status_change = false, bt_link_change = false; + + if (!btc->chip->scbd) + return; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__); + + val = _read_scbd(btc); + + if (val == 0xffffffff) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s return by invalid scbd value\n", + __func__); + return; + } + + if (!(val & BTC_BSCB_ON) || + btc->dm.cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX) + bt->enable.now = 0; + else + bt->enable.now = 1; + + if (bt->enable.now != bt->enable.last) { + status_change = true; + bt_link_change = true; + } + + /* reset bt info if bt re-enable */ + if (bt->enable.now && !bt->enable.last) { + _reset_btc_var(btc, BTC_RESET_BTINFO); + cx->cnt_bt[BTC_BCNT_REENABLE]++; + bt->enable.now = 1; + } + + bt->enable.last = bt->enable.now; + + bt->scbd = val; + bt->mbx_avl = !!(val & BTC_BSCB_ACT); + + if (bt->whql_test != (u32)(!!(val & BTC_BSCB_WHQL))) + status_change = true; + + bt->whql_test = !!(val & BTC_BSCB_WHQL); + + bt->btg_type = (val & BTC_BSCB_BT_S1 ? BTC_BT_BTG: BTC_BT_ALONE); + + bt->link_info.a2dp_desc.active = !!(val & BTC_BSCB_A2DP_ACT); + + /* if rfk run 1->0 */ + if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN)) + status_change = true; + + bt->rfk_info.map.run = !!(val & BTC_BSCB_RFK_RUN); + + bt->rfk_info.map.req = !!(val & BTC_BSCB_RFK_REQ); + + bt->hi_lna_rx = !!(val & BTC_BSCB_BT_HILNA); + + /* if connect change */ + if ((bt->link_info.status.map.connect && (!(val & BTC_BSCB_BT_CONNECT))) || + (!bt->link_info.status.map.connect && (val & BTC_BSCB_BT_CONNECT))) { + status_change = true; + bt_link_change = true; + } + + bt->link_info.status.map.connect = !!(val & BTC_BSCB_BT_CONNECT); + + bt->run_patch_code = !!(val & BTC_BSCB_PATCH_CODE); + +#if !BTC_CX_FW_OFFLOAD + if (bt_link_change) { + PHL_INFO("[BTC], %s: bt status change!!\n", __func__); + hal_btc_send_event(btc, NULL, 0, BTC_HMSG_BT_LINK_CHG); + } + + if (!only_update && status_change) + _run_coex(btc, __func__); +#endif +} + +/****************************************************************************** + * + * coexistence operations for external notifications + * + *****************************************************************************/ +static void _ntfy_power_on(struct btc_t *btc) +{ + /* no action for power on, beacuse power-on move halmac API + * the _ntfy_power_on = _ntfy_init_coex + */ +} + +static void _ntfy_power_off(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s()\n", __func__); + btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++; + + btc->cx.wl.status.map.rf_off = 1; + btc->cx.wl.status.map.busy = 0; + _write_scbd(btc, BTC_WSCB_ALL, false); + _run_coex(btc, __func__); + + hal_btc_fw_en_rpt(btc, RPT_EN_ALL, 0); + + btc->cx.wl.status.map.rf_off_pre = btc->cx.wl.status.map.rf_off; +} + +static void _ntfy_init_coex(struct btc_t *btc, u8 mode) +{ + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_chip_ops *ops = btc->chip->ops; + + PHL_INFO("[BTC], %s(): mode=%d\n", __func__, mode); + dm->cnt_notify[BTC_NCNT_INIT_COEX]++; + dm->wl_only = (mode == BTC_MODE_WL? 1 : 0); + dm->bt_only = (mode == BTC_MODE_BT? 1 : 0); + wl->status.map.rf_off = (mode == BTC_MODE_WLOFF? 1 : 0); + + if (!wl->status.map.init_ok) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return for WL init fail!!\n", + __func__); + dm->error.map.init = true; + return; + } + + /* Setup RF front end type from EFuse RFE type*/ + if (ops && ops->set_rfe) + ops->set_rfe(btc); + + if (ops && ops->init_cfg) + ops->init_cfg(btc); + + _write_scbd(btc, BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true); + _update_bt_scbd(btc, true); + + /* check PTA control owner to avoid BT coex issue */ + if (_read_cx_ctrl(btc) == BTC_CTRL_BY_WL) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): PTA owner warning!!\n", + __func__); + dm->error.map.pta_owner = true; + } + + _set_init_info(btc); + _set_wl_tx_power(btc, BTC_WL_DEF_TX_PWR); /* original tx power, no Tx power adjust */ + hal_btc_fw_set_slots(btc, CXST_MAX, dm->slot); + hal_btc_fw_set_monreg(btc); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL); + + _run_coex(btc, __func__); + _btmr_start(btc); + +#if 0 + hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_EN_MAP, + BIT(BTC_DBG_GNT_WL) | BIT(BTC_DBG_GNT_BT)); +#endif +} + +static void _ntfy_scan_start(struct btc_t *btc, u8 phy_idx, u8 band) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + PHL_INFO("[BTC], %s(): phy_idx=%d, band=%d\n", __func__, phy_idx, band); + btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++; + + wl->status.map.scan = true; + wl->scan_info.band[phy_idx] = band; + wl->scan_info.phy_map |= BIT(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN); + + if (btc->hal->dbcc_en) { + wl->dbcc_info.scan_band[phy_idx] = band; + _update_dbcc_band(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC); + } + + _run_coex(btc, __func__); +} + +static void _ntfy_scan_finish(struct btc_t *btc, u8 phy_idx) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + PHL_INFO("[BTC], %s(): phy_idx=%d\n", __func__, phy_idx); + btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++; + + wl->status.map.scan = false; + wl->scan_info.phy_map &= ~BIT(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN); + + if (btc->hal->dbcc_en) { + _update_dbcc_band(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC); + } + + _run_coex(btc, __func__); +} + +static void _ntfy_switch_band(struct btc_t *btc, u8 phy_idx, u8 band) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + PHL_INFO("[BTC], %s(): phy_idx=%d, band=%d\n", __func__, phy_idx, band); + btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++; + + wl->scan_info.band[phy_idx] = band; + wl->scan_info.phy_map |= BIT(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN); + + if (btc->hal->dbcc_en) { + wl->dbcc_info.scan_band[phy_idx] = band; + _update_dbcc_band(phy_idx); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC); + } + + _run_coex(btc, __func__); +} + +static void _ntfy_specific_packet(struct btc_t *btc, u8 pkt_type) +{ + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_link_info *b = &cx->bt.link_info; + struct btc_bt_hfp_desc *hfp = &b->hfp_desc; + struct btc_bt_hid_desc *hid = &b->hid_desc; + u32 cnt, delay = BTC_SPECPKT_MAXT; + + switch (pkt_type) { + case BTC_PKT_EVT_DHCP: + cnt = ++cx->cnt_wl[BTC_WCNT_DHCP]; + PHL_INFO("[BTC], %s(): pkt_type=%d, DHCP cnt=%d \n", __func__, + pkt_type, cnt); + wl->status.map.connecting = true; + _set_btc_timer(btc, BTC_TIMER_WL_SPECPKT, delay); + break; + case BTC_PKT_EVT_EAPOL: + cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; + PHL_INFO("[BTC], %s(): pkt_type=%d, EAPOL cnt=%d \n", __func__, + pkt_type, cnt); + wl->status.map._4way = true; + + if (hfp->exist || hid->exist) + delay = delay / 2; + + _set_btc_timer(btc, BTC_TIMER_WL_SPECPKT, delay); + break; + case BTC_PKT_EVT_ADD_KEY: + cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; + PHL_INFO("[BTC], %s(): pkt_type=%d, EAPOL_End cnt=%d \n", __func__, + pkt_type, cnt); + wl->status.map._4way = false; + break; + default: + case BTC_PKT_EVT_ARP: + cnt = ++cx->cnt_wl[BTC_WCNT_ARP]; + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): pkt_type=%d, ARP cnt=%d\n", + __func__, pkt_type, cnt); + return; + } + + btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++; + + _run_coex(btc, __func__); +} + +static void _update_bt_psd(struct btc_t *btc, u8 *buf, u32 len) +{ + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s():\n", __func__); +} + +void _update_dm_step(struct btc_t *btc, const char *strin) +{ + struct btc_dm *dm = &btc->dm; + u32 store_index = 0; + + dm->dm_step.cnt++; + if (dm->dm_step.cnt == 0) + dm->dm_step.cnt = 1; + + store_index = ((dm->dm_step.cnt-1) % BTC_DM_MAXSTEP); + _rsn_cpy(dm->dm_step.step[store_index], (char*)strin); +} + +static void _update_bt_info(struct btc_t *btc, u8 *buf, u32 len) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_cx *cx = &btc->cx; + struct btc_bt_info *bt = &cx->bt; + struct btc_bt_link_info *b = &bt->link_info; + struct btc_bt_hfp_desc *hfp = &b->hfp_desc; + struct btc_bt_hid_desc *hid = &b->hid_desc; + struct btc_bt_a2dp_desc *a2dp = &b->a2dp_desc; + struct btc_bt_pan_desc *pan = &b->pan_desc; + union btc_btinfo btinfo; + bool bt_link_change = false; + + if (buf[BTC_BTINFO_L1] != BTC_BT_INFO_LEN) + return; + + /* return if bt info match last bt-info */ + if (!hal_mem_cmp(h, bt->raw_info, buf, BTC_BTINFO_MAX)) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s return by bt-info duplicate!!\n", + __func__); + cx->cnt_bt[BTC_BCNT_INFOSAME]++; + return; + } + + hal_mem_cpy(h, bt->raw_info, buf, BTC_BTINFO_MAX); + + PHL_INFO("[BTC], %s: bt_info[2]=0x%02x\n", __func__, bt->raw_info[2]); + + /* reset to mo-connect before update */ + b->profile_cnt.last = b->profile_cnt.now; + b->relink.last = b->relink.now; + a2dp->exist_last = a2dp->exist; + b->multi_link.last = b->multi_link.now; + bt->inq_pag.last = bt->inq_pag.now; + b->profile_cnt.now = 0; + hid->type = 0; + + /* ======= parse raw info low-Byte2 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_L2]; + b->status.map.connect = btinfo.lb2.connect; + b->status.map.sco_busy = btinfo.lb2.sco_busy; + b->status.map.acl_busy = btinfo.lb2.acl_busy; + b->status.map.inq_pag = btinfo.lb2.inq_pag; + bt->inq_pag.now = btinfo.lb2.inq_pag; + cx->cnt_bt[BTC_BCNT_INQPAG] += !!(bt->inq_pag.now && !bt->inq_pag.last); + + hfp->exist = btinfo.lb2.hfp; + b->profile_cnt.now += (u8)hfp->exist; + hid->exist = btinfo.lb2.hid; + b->profile_cnt.now += (u8)hid->exist; + a2dp->exist = btinfo.lb2.a2dp; + b->profile_cnt.now += (u8)a2dp->exist; + pan->exist = btinfo.lb2.pan; + b->profile_cnt.now += (u8)pan->exist; + + /* ======= parse raw info low-Byte3 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_L3]; + if (btinfo.lb3.retry != 0) + cx->cnt_bt[BTC_BCNT_RETRY]++; + b->cqddr = btinfo.lb3.cqddr; + cx->cnt_bt[BTC_BCNT_INQ] += !!(btinfo.lb3.inq && !bt->inq); + bt->inq = btinfo.lb3.inq; + cx->cnt_bt[BTC_BCNT_PAGE] += !!(btinfo.lb3.pag && !bt->pag); + bt->pag = btinfo.lb3.pag; + + b->status.map.mesh_busy = btinfo.lb3.mesh_busy; + /* ======= parse raw info high-Byte0 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_H0]; + /* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/ + b->rssi = btc->chip->ops->bt_rssi(btc, btinfo.hb0.rssi); + + /* ======= parse raw info high-Byte1 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_H1]; + b->status.map.ble_connect = btinfo.hb1.ble_connect; + if (btinfo.hb1.ble_connect) + hid->type |= (hid->exist? BTC_HID_BLE : BTC_HID_RCU); + + cx->cnt_bt[BTC_BCNT_REINIT] += !!(btinfo.hb1.reinit && !bt->reinit); + bt->reinit = btinfo.hb1.reinit; + cx->cnt_bt[BTC_BCNT_RELINK] += !!(btinfo.hb1.relink && !b->relink.now); + b->relink.now = btinfo.hb1.relink; + cx->cnt_bt[BTC_BCNT_IGNOWL] += !!(btinfo.hb1.igno_wl && !bt->igno_wl); + bt->igno_wl = btinfo.hb1.igno_wl; + + hid->type |= (btinfo.hb1.voice? BTC_HID_RCU_VOICE : 0); + bt->ble_scan_en = btinfo.hb1.ble_scan; + + cx->cnt_bt[BTC_BCNT_ROLESW] += !!(btinfo.hb1.role_sw && !b->role_sw); + b->role_sw = btinfo.hb1.role_sw; + + b->multi_link.now = btinfo.hb1.multi_link; + + if (b->multi_link.now != b->multi_link.last) + bt_link_change = true; + + /* ======= parse raw info high-Byte2 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_H2]; + pan->active = !!btinfo.hb2.pan_active; + + cx->cnt_bt[BTC_BCNT_AFH] += !!(btinfo.hb2.afh_update && !b->afh_update); + b->afh_update = btinfo.hb2.afh_update; + a2dp->active = btinfo.hb2.a2dp_active; + b->slave_role = btinfo.hb2.slave; + hid->slot_info = btinfo.hb2.hid_slot; + + if (hid->pair_cnt != btinfo.hb2.hid_cnt) + bt_link_change = true; + + hid->pair_cnt = btinfo.hb2.hid_cnt; + hid->type |= (hid->slot_info == BTC_HID_218? BTC_HID_218 : BTC_HID_418); + + /* ======= parse raw info high-Byte3 ======= */ + btinfo.val = bt->raw_info[BTC_BTINFO_H3]; + a2dp->bitpool = btinfo.hb3.a2dp_bitpool; + + if (b->tx_3M != (u32)btinfo.hb3.tx_3M) + cx->cnt_bt[BTC_BCNT_RATECHG]++; + b->tx_3M = (u32)btinfo.hb3.tx_3M; + + a2dp->sink = btinfo.hb3.a2dp_sink; + +#if !BTC_CX_FW_OFFLOAD + if (bt->igno_wl && !cx->wl.status.map.rf_off) + _set_bt_ignore_wlan_act(btc, false); + + if (b->profile_cnt.now || b->status.map.ble_connect) + hal_btc_fw_en_rpt(btc, RPT_EN_BT_AFH_MAP, 1); + else + hal_btc_fw_en_rpt(btc, RPT_EN_BT_AFH_MAP, 0); + + if (bt_link_change) { + PHL_INFO("[BTC], %s: bt link change!!\n", __func__); + hal_btc_send_event(btc, NULL, 0, BTC_HMSG_BT_LINK_CHG); + } + + /* reset after A2DP stop->play */ + if (!a2dp->exist_last && a2dp->exist) { + a2dp->vendor_id = 0; + a2dp->flush_time = 0; + a2dp->play_latency = 1; + _set_btc_timer(btc, BTC_TIMER_BT_A2DPPLAY, BTC_A2DP_RESUME_MAXT); + } + + if (a2dp->exist && (a2dp->flush_time == 0 || a2dp->vendor_id == 0 || + a2dp->play_latency == 1)) + hal_btc_fw_en_rpt(btc, RPT_EN_BT_DEVICE_INFO, 1); + else + hal_btc_fw_en_rpt(btc, RPT_EN_BT_DEVICE_INFO, 0); + + _run_coex(btc, __func__); +#endif +} + +static void _ntfy_role_info(struct btc_t *btc, u8 rid, + struct btc_wl_link_info *info, + enum role_state reason) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_link_info *wlinfo = NULL; + + PHL_INFO("[BTC], %s(), role_id=%d, reason=%d\n", __func__, rid, reason); + + if (rid >= MAX_WIFI_ROLE_NUMBER) + return; + + btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++; + + wlinfo = &wl->link_info[rid]; + + hal_mem_cpy(h, wlinfo, info, sizeof(struct btc_wl_link_info)); + + /* update wifi_link_info_ext variable */ + _update_wl_info(btc); + + if (wlinfo->role == PHL_RTYPE_STATION && + wlinfo->connected == MLME_NO_LINK) + btc->dm.leak_ap = 0; + + if (reason == PHL_ROLE_MSTS_STA_CONN_START) + wl->status.map.connecting = 1; + else + wl->status.map.connecting = 0; + + if (reason == PHL_ROLE_MSTS_STA_DIS_CONN) + wl->status.map._4way = false; + + _run_coex(btc, __func__); +} + +static void _ntfy_radio_state(struct btc_t *btc, u8 rf_state) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_chip_ops *ops = btc->chip->ops; + + PHL_INFO("[BTC], %s(): rf_state =%d\n", __func__, rf_state); + btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++; + + switch(rf_state) { + case BTC_RFCTRL_WL_OFF: + wl->status.map.rf_off = 1; + wl->status.map.lps = 0; + wl->status.map.busy = 0; + break; + case BTC_RFCTRL_FW_CTRL: /* LPS-PG, LPS-CG */ + wl->status.map.rf_off = 0; + wl->status.map.lps = 1; + wl->status.map.busy = 0; + break; + case BTC_RFCTRL_LPS_WL_ON: /* LPS-Protocol (RFon) */ + wl->status.map.rf_off = 0; + wl->status.map.lps = 2; + wl->status.map.busy = 0; + break; + case BTC_RFCTRL_WL_ON: + default: + wl->status.map.rf_off = 0; + wl->status.map.lps = 0; + break; + } + + if (rf_state == BTC_RFCTRL_WL_ON) { + hal_btc_fw_en_rpt(btc, RPT_EN_MREG, 1); + _write_scbd(btc, BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true); + _update_bt_scbd(btc, true); + if (ops && ops->init_cfg) + ops->init_cfg(btc); + } else { + hal_btc_fw_en_rpt(btc, RPT_EN_ALL, 0); + /* for BT only isolated issue, + * clear all scbd if LPS-PG or "LPS-off to LPS-Protocol" + */ + if (rf_state == BTC_RFCTRL_LPS_WL_ON && + wl->status.map.lps_pre != 0) { + _write_scbd(btc, BTC_WSCB_ON, true); + } else { + _write_scbd(btc, BTC_WSCB_ALL, false); + } + } + + _run_coex(btc, __func__); + + wl->status.map.rf_off_pre = wl->status.map.rf_off; + wl->status.map.lps_pre = wl->status.map.lps; +} + +static void _ntfy_customerize(struct btc_t *btc, u8 type, u16 len, u8 *buf) +{ + struct btc_bt_info *bt = &btc->cx.bt; + + if (!buf) + return; + + PHL_INFO("[BTC], %s !! \n", __func__); + btc->dm.cnt_notify[BTC_NCNT_CUSTOMERIZE]++; + + switch (type) { + case PHL_BTC_CNTFY_BTINFO: + if (len != 1) + return; + buf[0] = bt->raw_info[BTC_BTINFO_L2]; + break; + } +} + +static u8 _ntfy_wl_rfk(struct btc_t *btc, u8 phy_path, u8 type, u8 state) +{ + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + bool result = BTC_WRFK_REJECT; + + wl->rfk_info.type = type; + wl->rfk_info.path_map = phy_path & BTC_RFK_PATH_MAP; + wl->rfk_info.phy_map = (phy_path & BTC_RFK_PHY_MAP) >> 4; + wl->rfk_info.band = (phy_path & BTC_RFK_BAND_MAP) >> 6; + state &= (BIT(0) | BIT(1)); + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()_start: phy=0x%x, path=0x%x, type=%d, state=%d\n", + __func__, wl->rfk_info.phy_map, wl->rfk_info.path_map, + type, state); + + switch (state) { + case BTC_WRFK_START: + result = _chk_wl_rfk_request(btc); + wl->rfk_info.state = (result? BTC_WRFK_START : BTC_WRFK_STOP); +#if 0 + hal_btc_fw_set_drv_info(btc, CXDRVINFO_RFK); + _write_scbd(btc, BTC_WSCB_WLRFK, result); +#endif + + btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++; + break; + case BTC_WRFK_ONESHOT_START: + case BTC_WRFK_ONESHOT_STOP: + if (wl->rfk_info.state == BTC_WRFK_STOP) { + result = BTC_WRFK_REJECT; + } else { + result = BTC_WRFK_ALLOW; + wl->rfk_info.state = state; + } + break; + case BTC_WRFK_STOP: + result = BTC_WRFK_ALLOW; + wl->rfk_info.state = BTC_WRFK_STOP; +#if 0 + hal_btc_fw_set_drv_info(btc, CXDRVINFO_RFK); + _write_scbd(btc, BTC_WSCB_WLRFK, false); +#endif + break; + } + + if (result == BTC_WRFK_ALLOW) { + /* Only update coex for RFK START and STOP + * because Start -> OneSHOT_START time is short + */ + if (wl->rfk_info.state == BTC_WRFK_START || + wl->rfk_info.state == BTC_WRFK_STOP) + _run_coex(btc, __func__); + + if (wl->rfk_info.state == BTC_WRFK_START) /* wait 300ms */ + _set_btc_timer(btc, BTC_TIMER_WL_RFKTO, BTC_WRFK_MAXT); + + } + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,"[BTC], %s()_finish: rfk_cnt=%d, result=%d\n", + __func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result); + + return result; +} + +static void _ntfy_wl_sta(struct btc_t *btc, u8 ntfy_num, + struct btc_wl_stat_info stat_info[], u8 reason) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_module *module = &btc->mdinfo; + struct btc_wl_stat_info *w = NULL; + struct btc_traffic *t = NULL, *link_info_t = NULL; + struct btc_wl_link_info *link_info = NULL; + u8 i, j, busy = 0, dir = 0, rssi_map = 0; + u8 busy_all = 0, dir_all = 0, rssi_map_all = 0; + bool is_sta_change = false, is_traffic_change = false; + u16 last_tx_rate, last_rx_rate, last_tx_lvl, last_rx_lvl; + u32 chk_intvl = 20; + + /* rssi_map = 4 bits for rssi locate in which {60, 50, 40, 30} + * if rssi >= 60% (-50dBm) --> map = 4b'0000 --> rssi_level = 0 + * if 50% <= rssi < 60% --> map = 4b'0001 --> rssi_level = 1 + * if 40% <= rssi < 50% --> map = 4b'0011 --> rssi_level = 2 + * if 30% <= rssi < 40% --> map = 4b'0111 --> rssi_level = 3 + * if rssi < 20% --> map = 4b'1111 --> rssi_level = 4 + */ + + btc->dm.cnt_notify[BTC_NCNT_WL_STA]++; + + for (i = 0; i < ntfy_num; i++) { + w = &stat_info[i]; + t = &w->stat.traffic; + + link_info = &wl->link_info[w->pid]; + link_info_t = &link_info->stat.traffic; + rssi_map = 0; + + if (link_info->connected == MLME_NO_LINK) { + link_info->rx_rate_drop_cnt = 0; + rssi_map_all |= rssi_map; + continue; + } + + last_tx_rate = link_info_t->tx_rate; + last_rx_rate = link_info_t->rx_rate; + last_tx_lvl = (u16)link_info_t->tx_lvl; + last_rx_lvl = (u16)link_info_t->rx_lvl; + + /* refresh link_info traffic/rssi related info from t */ + hal_mem_cpy(h, (void *)link_info_t, (void *)t, + sizeof(struct btc_traffic)); + + link_info->stat.rssi = w->stat.rssi; + + /* check if rssi across wl_rssi_thres boundary */ + for (j = 0; j < BTC_WL_RSSI_THMAX; j++) { + link_info->rssi_state[j] = + _update_rssi_state(btc, + link_info->rssi_state[j], + link_info->stat.rssi, + btc->chip->wl_rssi_thres[j]); + /* fill rssi bit map 0~3 if rssi < threshold */ + if (BTC_RSSI_LOW(link_info->rssi_state[j])) + rssi_map |= BIT(j); + + if (module->ant.type == BTC_ANT_DEDICATED && + BTC_RSSI_CHANGE(link_info->rssi_state[j])) + is_sta_change = true; + } + + /* OR all role rssi map */ + rssi_map_all |= rssi_map; + + /* set busy once idle->busy immediately */ + if (t->tx_lvl != RTW_TFC_IDLE || t->rx_lvl != RTW_TFC_IDLE) { + busy = 1; + link_info->busy_t = _os_get_cur_time_ms(); + + if (t->tx_lvl > t->rx_lvl) + dir = TRAFFIC_UL; + else + dir = TRAFFIC_DL; + } else {/*set idle if busy -> idle after BTC_BUSY2IDLE_THRES*/ + if (phl_get_passing_time_ms(link_info->busy_t) > + BTC_BUSY2IDLE_THRES || !wl->role_info.role_map.role.station || + wl->role_info.link_mode == BTC_WLINK_NOLINK) { + busy = 0; + dir = TRAFFIC_DL; + } else { + busy = link_info->busy; + dir = link_info->dir; + } + } + + if (link_info->busy != busy || link_info->dir != dir) { + is_sta_change = true; + link_info->busy = busy; + link_info->dir = dir; + } + + busy_all |= link_info->busy; + dir_all |= BIT(link_info->dir); + + if (link_info_t->rx_rate <= RTW_DATA_RATE_CCK2 && + last_rx_rate > RTW_DATA_RATE_CCK2 && + link_info_t->rx_lvl > 0) + link_info->rx_rate_drop_cnt++; + + if (last_tx_rate != link_info_t->tx_rate || + last_rx_rate != link_info_t->rx_rate || + last_tx_lvl != link_info_t->tx_lvl || + last_rx_lvl != link_info_t->rx_lvl ) + is_traffic_change = true; + + wl->role_info.active_role[w->pid].tx_lvl = (u16)t->tx_lvl; + wl->role_info.active_role[w->pid].rx_lvl = (u16)t->rx_lvl; + wl->role_info.active_role[w->pid].tx_rate = t->tx_rate; + wl->role_info.active_role[w->pid].rx_rate = t->rx_rate; + } + + wl->rssi_level = 0; + for (j = BTC_WL_RSSI_THMAX; j > 0; j--) { + /* set RSSI level 4 ~ 0 if rssi bit map match */ + if (rssi_map_all & BIT(j-1)) { + wl->rssi_level = j; + break; + } + } + + /* for TDD/FDD packet estimation in WL FW */ + if (is_traffic_change) + hal_btc_fw_set_drv_info(btc, CXDRVINFO_ROLE); + + chk_intvl = 2000/BTC_PERIODIC_TIME; + + if (is_sta_change) { + wl->status.map.busy = (u32)busy_all; + wl->status.map.traffic_dir = (u32)dir_all; + _write_scbd(btc, BTC_WSCB_WLBUSY, (bool)(!!wl->status.map.busy)); + _run_coex(btc, __func__); + } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >= + btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + chk_intvl) { + _get_wl_nhm_dbm(btc); + btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = + btc->dm.cnt_notify[BTC_NCNT_WL_STA]; + } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] < + btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) { + btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = + btc->dm.cnt_notify[BTC_NCNT_WL_STA]; + } +} + +static void _ntfy_fwinfo(struct btc_t *btc, u8 *buf, u32 len, u8 cls, u8 func) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + + if (!buf || !len) + return; + + btc->dm.cnt_notify[BTC_NCNT_FWINFO]++; + pfwinfo->cnt_c2h++; + + if (cls == BTFC_FW_EVENT) { + switch (func) { + case BTF_EVNT_RPT: + case BTF_EVNT_BUF_OVERFLOW: + pfwinfo->event[func]++; + hal_btc_fw_event(btc, func, buf, len); + break; + case BTF_EVNT_BT_INFO: + btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++; + _update_bt_info(btc, buf, len); + break; + case BTF_EVNT_BT_SCBD: + btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++; + _update_bt_scbd(btc, false); + break; + case BTF_EVNT_BT_PSD: + _update_bt_psd(btc, buf, len); + break; + case BTF_EVNT_BT_REG: + btc->dbg.rb_done = true; + btc->dbg.rb_val = ((buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | (buf[0])); + break; + case BTF_EVNT_C2H_LOOPBACK: + btc->dbg.rb_done = true; + btc->dbg.rb_val = buf[0]; + break; + case BTF_EVNT_CX_RUNINFO: + btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++; + _update_offload_runinfo(btc, buf, len); + break; + } + } +} + +static void _ntfy_timer(struct btc_t *btc, u16 tmr_id) +{ + struct btc_dm *dm = &btc->dm; + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_a2dp_desc *a2dp = &cx->bt.link_info.a2dp_desc; + bool is_sta_change = false; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], %s(): tmr_id =%d\n", __func__, tmr_id); + + dm->cnt_notify[BTC_NCNT_TIMER]++; + + if (tmr_id == BTC_TIMER_PERIODIC) { + /* start next periodic timer */ + _set_btc_timer(btc, BTC_TIMER_PERIODIC, BTC_PERIODIC_TIME); + } else if (tmr_id == BTC_TIMER_WL_RFKTO) { + if (wl->rfk_info.state != BTC_WRFK_STOP) { + cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]++; + dm->error.map.wl_rfk_timeout = true; + wl->rfk_info.state = BTC_WRFK_STOP; + /* _write_scbd(btc, BTC_WSCB_WLRFK, false); */ + is_sta_change = true; + } + } else if (tmr_id == BTC_TIMER_WL_SPECPKT) { + wl->status.map._4way = false; + wl->status.map.connecting = 0; + is_sta_change = true; + } else if (tmr_id == BTC_TIMER_BT_A2DPPLAY) { + a2dp->play_latency = 0; + is_sta_change = true; + } + + if (is_sta_change) + _run_coex(btc, __func__); +} + +/****************************************************************************** + * + * coexistence extern functions + * + *****************************************************************************/ +/* + * btc related sw initialization + */ +bool hal_btc_init(struct btc_t *btc) +{ + switch (btc->hal->chip_id) { +#ifdef BTC_8852A_SUPPORT + case CHIP_WIFI6_8852A: + PHL_INFO("[BTC], %s(): Init 8852A!!\n", __func__); + btc->chip = &chip_8852a; + break; +#endif +#ifdef BTC_8852B_SUPPORT + case CHIP_WIFI6_8852B: + PHL_INFO("[BTC], %s(): Init 8852B!!\n", __func__); + btc->chip = &chip_8852b; + break; +#endif +#ifdef BTC_8852C_SUPPORT + case CHIP_WIFI6_8852C: + PHL_INFO("[BTC], %s(): Init 8852C!!\n", __func__); + btc->chip = &chip_8852c; + break; +#endif + default: + PHL_ERR("[BTC], %s(): no matched IC!!\n", __func__); + btc->cx.wl.status.map.init_ok = false; + return false; + } + + _reset_btc_var(btc, BTC_RESET_ALL); + _btmr_init(btc); + + _rsn_cpy(btc->dm.run_reason, "None"); + _act_cpy(btc->dm.run_action, "None"); + + btc->hal->btc_vc.btc_ver = coex_ver; + btc->ops = &_btc_ops; + btc->mlen = BTC_MSG_MAXLEN; + btc->ctrl.igno_bt = true; + btc->cx.wl.status.map.init_ok = true; + + return true; +} + +void hal_btc_deinit(struct btc_t *btc) +{ + _btmr_deinit(btc); +} + +#endif + diff --git a/phl/hal_g6/btc/hal_btc.h b/phl/hal_g6/btc/hal_btc.h new file mode 100644 index 0000000..2d5bc90 --- /dev/null +++ b/phl/hal_g6/btc/hal_btc.h @@ -0,0 +1,1341 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_BTC_H_ +#define _HAL_BTC_H_ + +#include "halbtc_fw.h" +#include "halbtc_dbg_cmd.h" + +#ifdef CONFIG_RTL8852A +#define BTC_8852A_SUPPORT +#endif + +#ifdef CONFIG_RTL8852B +#define BTC_8852B_SUPPORT +#endif + +#ifdef CONFIG_RTL8852C +#define BTC_8852C_SUPPORT +#endif + +#define BTC_GPIO_DBG_EN 1 +#define BTC_CX_FW_OFFLOAD 0 +#define BTC_PHY_MAX 2 +#define BTC_NON_SHARED_ANT_FREERUN 0 + +#define BTC_MSG_MAXLEN 200 +#define BTC_POLICY_MAXLEN 512 +#define BTC_HUBMSG_MAXLEN 512 +#define BTC_RPT_PERIOD 2000 +#define BTC_RSN_MAXLEN 32 +#define BTC_ACT_MAXLEN 32 +#define BTC_DELAYED_PERIODIC_TIME 2000 /* 2000ms, delayed to start periodic timer */ +#define BTC_PERIODIC_TIME 100 /* 100ms, must be non zero and < 2000 */ +#define BTC_WRFK_MAXT 300 /* WL RFK 300ms */ +#define BTC_BRFK_MAXT 800 /* BT RFK 800ms */ +#define BTC_SPECPKT_MAXT 4000 /* special pkt unit: 4000ms */ +#define BTC_A2DP_RESUME_MAXT 16000 /* for A2DP resume, 16sec = 16000ms */ +#define BTC_RPT_HDR_SIZE 3 +#define BTC_BUSY2IDLE_THRES 10000 /* wait time for WL busy-to-idle, 10sec = 10000ms */ +#define BTC_WL_DEF_TX_PWR 255 +/* reserved 5 rf_trx_para level for non-freerun case */ +#define BTC_LEVEL_ID_OFFSET 5 +/* Define MAC-Related Reg Addr and Bitmap + * These definitions should be removed if MACAPI support. + */ +#define BTC_DM_MAXSTEP 30 + +#define BTC_LEAK_AP_TH 10 +#define BTC_CYSTA_CHK_PERIOD 100 + +#define BTC_SCC_CYCLE 100 +#define BTC_NULL1_EBT_EARLY_T 10 + +#define R_BTC_CFG 0xDA00 +#define R_BTC_WL_PRI_MSK 0xDA10 +#define R_BTC_BREAK_TABLE 0xDA2C +#define R_BTC_BT_COEX_MSK_TABLE 0xDA30 +#define R_BTC_CSR_MODE 0xDA40 +#define R_BTC_BT_STAST_HIGH 0xDA44 +#define R_BTC_BT_STAST_LOW 0xDA48 + +#define B_BTC_WL_SRC BIT(0) +#define B_BTC_DIS_BTC_CLK_G BIT(2) +#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) +#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28) +#define B_BTC_DBG_GNT_WL_BT BIT(27) +#define B_BTC_BT_CNT_REST BIT(16) +#define B_BTC_PTA_WL_PRI_MASK_BCNQ BIT(8) +#define B_BTC_PTA_WL_PRI_MASK_MGQ BIT(4) + +struct btc_t; + +#define NM_EXEC false +#define FC_EXEC true + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +#define bMASKDW 0xffffffff +#define bMASKHW 0xffff0000 +#define bMASKLW 0x0000ffff +#define bMASKB0 0x000000ff +#define bMASKB1 0x0000ff00 +#define bMASKB2 0x00ff0000 +#define bMASKB3 0xff000000 +#define bMASKRF 0x000fffff + +#define BTC_WL_RSSI_THMAX 4 +#define BTC_BT_RSSI_THMAX 4 + +#define BTC_TDMA_WLROLE_MAX 2 +#define BTC_TDMA_BTHID_MAX 2 +#define BTC_FREERUN_ANTISO_MIN 30 +#define BTC_BT_RX_NORMAL_LVL 7 + +#define BTC_BT_INFO_LEN 6 +#define BTC_B1_MAX 250 /* unit:ms, used for Max A2DP retry adjust */ + +#define BTC_COEX_RTK_MODE 0 +#define BTC_COEX_CSR_MODE 1 +#define BTC_COEX_INNER 0 +#define BTC_COEX_OUTPUT 1 +#define BTC_COEX_INPUT 2 + +#define BTC_BLINK_NOCONNECT 0 +#define BTC_WL_NONE 0 +#define BTC_CHK_HANG_MAX 3 +#define BTC_CHK_WLSLOT_DRIFT_MAX 15 +#define BTC_CHK_BTSLOT_DRIFT_MAX 15 + +#define BTC_RFK_PATH_MAP 0xf +#define BTC_RFK_PHY_MAP 0x30 +#define BTC_RFK_BAND_MAP 0xc0 + +#define _write_cx_reg(btc, offset, val) \ + rtw_hal_mac_coex_reg_write(btc->hal, offset, val) + +#define _read_wl_rf_reg(btc, path, addr, mask) \ + rtw_hal_read_rf_reg(btc->hal, path, addr, mask); +#define _write_wl_rf_reg(btc, path, addr, mask, data) \ + rtw_hal_write_rf_reg(btc->hal, path, addr, mask, data) + +#define _update_poicy hal_btc_fw_set_policy + +#define run_rsn(r) \ + (hal_mem_cmp(btc->hal, btc->dm.run_reason, r, _os_strlen((u8*)r))? 0:1) +#define _rsn_cpy(dst, src) \ + hal_mem_cpy(btc->hal, dst, src, BTC_RSN_MAXLEN) +#define _act_cpy(dst, src) \ + hal_mem_cpy(btc->hal, dst, src, BTC_ACT_MAXLEN) + +#define _tdma_cmp(dst, src) \ + hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_tdma)) +#define _tdma_cpy(dst, src) \ + hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_tdma)) +#define _tdma_set(tp,rxflc,txflc,wtg,lek,ext,flc_role) \ + do { \ + btc->dm.tdma.type = tp;\ + btc->dm.tdma.rxflctrl = rxflc; \ + btc->dm.tdma.txflctrl = txflc; \ + btc->dm.tdma.wtgle_n = wtg; \ + btc->dm.tdma.leak_n = lek; \ + btc->dm.tdma.ext_ctrl = ext; \ + btc->dm.tdma.rxflctrl_role = flc_role; \ + } while (0) +#define _tdma_set_rxflctrl(rxflc) btc->dm.tdma.rxflctrl = rxflc +#define _tdma_set_txflctrl(txflc) btc->dm.tdma.txflctrl = txflc +#define _tdma_set_flctrl_role(role) btc->dm.tdma.rxflctrl_role = role +#define _tdma_set_tog(wtg) btc->dm.tdma.wtgle_n = wtg +#define _tdma_set_lek(lek) btc->dm.tdma.leak_n = lek + +#define _slot_cmp(dst, src) \ + hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_slot)) +#define _slot_cpy(dst, src) \ + hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_slot)) +#define _slots_cpy(dst, src) \ + hal_mem_cpy(btc->hal, dst, src, CXST_MAX*sizeof(struct fbtc_slot)) +#define _slot_set(sid,dura,tbl,type) \ + do { \ + btc->dm.slot[sid].dur = dura;\ + btc->dm.slot[sid].cxtbl = tbl; \ + btc->dm.slot[sid].cxtype = type; \ + } while (0) +#define _slot_set_dur(sid,dura) btc->dm.slot[sid].dur = dura +#define _slot_set_tbl(sid,tbl) btc->dm.slot[sid].cxtbl = tbl +#define _slot_set_type(sid,type) btc->dm.slot[sid].cxtype = type + +enum btc_wl_gpio_debug { + BTC_DBG_GNT_BT = 0, + BTC_DBG_GNT_WL = 1, + /* The following signals should 0-1 tiggle by each function-call */ + BTC_DBG_BCN_EARLY = 2, + BTC_DBG_WL_NULL0 = 3, + BTC_DBG_WL_NULL1 = 4, + BTC_DBG_WL_RXISR = 5, + BTC_DBG_TDMA_ENTRY = 6, + BTC_DBG_A2DP_EMPTY = 7, + BTC_DBG_BT_RETRY = 8, + /* The following signals should 0-1 tiggle by state L/H */ + BTC_DBG_BT_RELINK = 9, + BTC_DBG_SLOT_WL = 10, + BTC_DBG_SLOT_BT = 11, + BTC_DBG_WL_RFK = 12, + BTC_DBG_BT_RFK = 13, + /* The following signals should appear only 1 "Hi" at same time */ + BTC_DBG_SLOT_B2W = 14, + BTC_DBG_SLOT_W1 = 15, + BTC_DBG_SLOT_W2 = 16, + BTC_DBG_SLOT_W2B = 17, + BTC_DBG_SLOT_B1 = 18, + BTC_DBG_SLOT_B2 = 19, + BTC_DBG_SLOT_B3 = 20, + BTC_DBG_SLOT_B4 = 21, + BTC_DBG_SLOT_LK = 22, + BTC_DBG_SLOT_E2G = 23, + BTC_DBG_SLOT_E5G = 24, + BTC_DBG_SLOT_EBT = 25, + BTC_DBG_SLOT_ENULL = 26, + BTC_DBG_SLOT_WLK = 27, + BTC_DBG_SLOT_W1FDD = 28, + BTC_DBG_SLOT_B1FDD = 29, + BTC_DBG_BT_CHANGE = 30 +}; + +enum btc_cx_run_info { + BTC_CXR_WSCBD = 0, + BTC_CXR_RESULT, + BTC_CXR_MAX +}; + +enum btc_bt_rfk_state { + BTC_BRFK_STOP = 0, + BTC_BRFK_START = 1 +}; + +enum btc_wl_rfk_state { + BTC_WRFK_STOP = 0, + BTC_WRFK_START = 1, + BTC_WRFK_ONESHOT_START = 2, + BTC_WRFK_ONESHOT_STOP = 3 +}; + +enum btc_wl_rfk_result { + BTC_WRFK_REJECT = 0, + BTC_WRFK_ALLOW = 1 +}; + +enum { + BTC_CTRL_BY_BT = 0, + BTC_CTRL_BY_WL +}; + +enum { + BTC_3CX_NONE = 0, + BTC_3CX_LTE = 1, + BTC_3CX_ZB = 2, + BTC_3CX_MAX +}; + +enum { + BTC_PRI_MASK_RX_RESP = 0, + BTC_PRI_MASK_TX_RESP, + BTC_PRI_MASK_BEACON, + BTC_PRI_MASK_RX_CCK, + BTC_PRI_MASK_TX_MNGQ, + BTC_PRI_MASK_MAX +}; + +enum { + BTC_INIT_NORMAL, + BTC_INIT_WLONLY, + BTC_INIT_WLOFF +}; + +enum { + BTC_BRANCH_MAIN = 0, + BTC_BRANCH_HP, + BTC_BRANCH_LENOVO, + BTC_BRANCH_HUAWEI, + BTC_BRANCH_MAX +}; + +enum { + BTC_STR_ROLE = 0, + BTC_STR_MROLE, + BTC_STR_REG, + BTC_STR_SLOT, + BTC_STR_TDMA, + BTC_STR_TRACE, + BTC_STR_BRANCH, + BTC_STR_RXFLCTRL, + BTC_STR_WLLINK, + BTC_STR_ANTPATH, + BTC_STR_GDBG, + BTC_STR_CHIPID, + BTC_STR_EVENT, + BTC_STR_WLMODE, + BTC_STR_WLBW, + BTC_STR_RFTYPE, + BTC_STR_POLICY, + BTC_STR_MSTATE, + BTC_STR_RATE, + BTC_STR_POLUT, + BTC_STR_MAX +}; + +enum { + BTC_WL = 0, + BTC_BT, + BTC_ZB, + BTC_LTE, + BTC_MAX +}; + +enum { + BTC_BT_SS_GROUP = 0x0, + BTC_BT_TX_GROUP = 0x2, + BTC_BT_RX_GROUP = 0x3, + BTC_BT_MAX_GROUP, +}; + +enum btc_rssi_st { + BTC_RSSI_ST_LOW = 0x0, + BTC_RSSI_ST_HIGH, + BTC_RSSI_ST_STAY_LOW, + BTC_RSSI_ST_STAY_HIGH, + BTC_RSSI_ST_MAX +}; + +#define BTC_RSSI_HIGH(_rssi_) \ + ((_rssi_ == BTC_RSSI_ST_HIGH || _rssi_ == BTC_RSSI_ST_STAY_HIGH)? 1:0) +#define BTC_RSSI_LOW(_rssi_) \ + ((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_STAY_LOW)? 1:0) +#define BTC_RSSI_CHANGE(_rssi_) \ + ((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_HIGH)? 1:0) + +enum btc_coex_info_map_en { + BTC_COEX_INFO_CX = BIT(0), + BTC_COEX_INFO_WL = BIT(1), + BTC_COEX_INFO_BT = BIT(2), + BTC_COEX_INFO_DM = BIT(3), + BTC_COEX_INFO_MREG = BIT(4), + BTC_COEX_INFO_SUMMARY = BIT(5), + BTC_COEX_INFO_ALL = 0xff +}; + +/* list all-chip scoreboard definition, remap at chip file */ +enum btc_w2b_scoreboard { + BTC_WSCB_ACTIVE = BIT(0), + BTC_WSCB_ON = BIT(1), + BTC_WSCB_SCAN = BIT(2), + BTC_WSCB_UNDERTEST = BIT(3), + BTC_WSCB_RXGAIN = BIT(4), /* set BT LNA constrain for free-run */ + BTC_WSCB_WLBUSY = BIT(7), + BTC_WSCB_EXTFEM = BIT(8), + BTC_WSCB_TDMA = BIT(9), + BTC_WSCB_FIX2M = BIT(10), + BTC_WSCB_WLRFK = BIT(11), + BTC_WSCB_RXSCAN_PRI = BIT(12), /* set BT Rx-Scan PTA pri */ + BTC_WSCB_BT_HILNA = BIT(13), /* 1: request BT use Hi-LNA table for BTG */ + BTC_WSCB_BTLOG = BIT(14), /* open BT log */ + BTC_WSCB_ALL = 0xffffff /* driver only use bit0~23 */ +}; + +enum btc_b2w_scoreboard { + BTC_BSCB_ACT = BIT(0), + BTC_BSCB_ON = BIT(1), + BTC_BSCB_WHQL = BIT(2), + BTC_BSCB_BT_S1 = BIT(3), /* 1-> BT at S1, 0-> BT at S0 */ + BTC_BSCB_A2DP_ACT = BIT(4), + BTC_BSCB_RFK_RUN = BIT(5), + BTC_BSCB_RFK_REQ = BIT(6), + BTC_BSCB_LPS = BIT(7), + BTC_BSCB_WLRFK = BIT(11), + BTC_BSCB_BT_HILNA = BIT(13), /* reply if BT use Hi-LNA table for BTG */ + BTC_BSCB_BT_CONNECT = BIT(16), /* If any BT connected */ + BTC_BSCB_PATCH_CODE = BIT(30), /* BT use 1: patch code 2:ROM code */ + BTC_BSCB_ALL = 0x7fffffff +}; + +enum btc_bt_link_status { + BTC_BLINK_CONNECT = BIT(0), + BTC_BLINK_BLE_CONNECT = BIT(1), + BTC_BLINK_ACL_BUSY = BIT(2), + BTC_BLINK_SCO_BUSY = BIT(3), + BTC_BLINK_MESH_BUSY = BIT(4), + BTC_BLINK_INQ_PAGE = BIT(5) +}; + +enum { + BTC_DCNT_RUN = 0x0, + BTC_DCNT_CX_RUNINFO, + BTC_DCNT_RPT, + BTC_DCNT_RPT_FREEZE, + BTC_DCNT_CYCLE, + BTC_DCNT_CYCLE_FREEZE, + BTC_DCNT_W1, + BTC_DCNT_W1_FREEZE, + BTC_DCNT_B1, + BTC_DCNT_B1_FREEZE, + BTC_DCNT_TDMA_NONSYNC, + BTC_DCNT_SLOT_NONSYNC, + BTC_DCNT_BTCNT_FREEZE, + BTC_DCNT_WL_SLOT_DRIFT, + BTC_DCNT_WL_STA_LAST, + BTC_DCNT_BT_SLOT_DRIFT, + BTC_DCNT_MAX +}; + +enum { + BTC_NCNT_POWER_ON = 0x0, + BTC_NCNT_POWER_OFF, + BTC_NCNT_INIT_COEX, + BTC_NCNT_SCAN_START, + BTC_NCNT_SCAN_FINISH, + BTC_NCNT_SPECIAL_PACKET, + BTC_NCNT_SWITCH_BAND, + BTC_NCNT_RFK_TIMEOUT, + BTC_NCNT_SHOW_COEX_INFO, + BTC_NCNT_ROLE_INFO, + BTC_NCNT_CONTROL, + BTC_NCNT_RADIO_STATE, + BTC_NCNT_CUSTOMERIZE, + BTC_NCNT_WL_RFK, + BTC_NCNT_WL_STA, + BTC_NCNT_FWINFO, + BTC_NCNT_TIMER, + BTC_NCNT_MAX +}; + +enum btc_wl_state_cnt { + BTC_WCNT_SCANAP = 0x0, + BTC_WCNT_DHCP, + BTC_WCNT_EAPOL, + BTC_WCNT_ARP, + BTC_WCNT_SCBDUPDATE, + BTC_WCNT_RFK_REQ, + BTC_WCNT_RFK_GO, + BTC_WCNT_RFK_REJECT, + BTC_WCNT_RFK_TIMEOUT, + BTC_WCNT_CH_UPDATE, + BTC_WCNT_MAX +}; + +enum btc_bt_state_cnt { + BTC_BCNT_RETRY = 0x0, + BTC_BCNT_REINIT, + BTC_BCNT_REENABLE, + BTC_BCNT_SCBDREAD, + BTC_BCNT_RELINK, + BTC_BCNT_IGNOWL, + BTC_BCNT_INQPAG, + BTC_BCNT_INQ, + BTC_BCNT_PAGE, + BTC_BCNT_ROLESW, + BTC_BCNT_AFH, + BTC_BCNT_INFOUPDATE, + BTC_BCNT_INFOSAME, + BTC_BCNT_SCBDUPDATE, + BTC_BCNT_HIPRI_TX, + BTC_BCNT_HIPRI_RX, + BTC_BCNT_LOPRI_TX, + BTC_BCNT_LOPRI_RX, + BTC_BCNT_RATECHG, + BTC_BCNT_MAX +}; + +enum btc_wl_link_mode { + BTC_WLINK_NOLINK = 0x0, + BTC_WLINK_2G_STA, + BTC_WLINK_2G_AP, + BTC_WLINK_2G_GO, + BTC_WLINK_2G_GC, + BTC_WLINK_2G_SCC, + BTC_WLINK_2G_MCC, + BTC_WLINK_25G_MCC, + BTC_WLINK_25G_DBCC, + BTC_WLINK_5G, + BTC_WLINK_2G_NAN, + BTC_WLINK_OTHER, + BTC_WLINK_MAX +}; + +enum btc_wl_mrole_type { + BTC_WLMROLE_NONE = 0x0, + BTC_WLMROLE_STA_GC, + BTC_WLMROLE_STA_GC_NOA, + BTC_WLMROLE_STA_GO, + BTC_WLMROLE_STA_GO_NOA, + BTC_WLMROLE_STA_STA, + BTC_WLMROLE_MAX +}; + +enum { + BTC_BTINFO_L0 = 0, + BTC_BTINFO_L1, + BTC_BTINFO_L2, + BTC_BTINFO_L3, + BTC_BTINFO_H0, + BTC_BTINFO_H1, + BTC_BTINFO_H2, + BTC_BTINFO_H3, + BTC_BTINFO_MAX +}; + +struct btc_btinfo_lb2 { + u8 connect: 1; + u8 sco_busy: 1; + u8 inq_pag: 1; + u8 acl_busy: 1; + u8 hfp: 1; + u8 hid: 1; + u8 a2dp: 1; + u8 pan: 1; +}; + +struct btc_btinfo_lb3 { + u8 retry: 4; + u8 cqddr: 1; + u8 inq: 1; + u8 mesh_busy: 1; + u8 pag: 1; +}; + +struct btc_btinfo_hb0 { + u8 rssi; +}; + +struct btc_btinfo_hb1 { + u8 ble_connect: 1; + u8 reinit: 1; + u8 relink: 1; + u8 igno_wl: 1; + u8 voice: 1; + u8 ble_scan: 1; + u8 role_sw: 1; + u8 multi_link: 1; +}; + +struct btc_btinfo_hb2 { + u8 pan_active: 1; + u8 afh_update: 1; + u8 a2dp_active: 1; + u8 slave: 1; + u8 hid_slot: 2; + u8 hid_cnt: 2; +}; + +struct btc_btinfo_hb3 { + u8 a2dp_bitpool: 6; + u8 tx_3M: 1; + u8 a2dp_sink: 1; +}; + +union btc_btinfo { + u8 val; + struct btc_btinfo_lb2 lb2; + struct btc_btinfo_lb3 lb3; + struct btc_btinfo_hb0 hb0; + struct btc_btinfo_hb1 hb1; + struct btc_btinfo_hb2 hb2; + struct btc_btinfo_hb3 hb3; +}; + +enum btc_rinfo_lo_b2 { + BTC_RINFO_INQPAG = BIT(2), +}; + +enum btc_bt_hfp_type { + BTC_HFP_SCO = 0, + BTC_HFP_ESCO = 1, + BTC_HFP_ESCO_2SLOT = 2, +}; + +enum btc_bt_hid_type { + BTC_HID_218 = BIT(0), + BTC_HID_418 = BIT(1), + BTC_HID_BLE = BIT(2), + BTC_HID_RCU = BIT(3), + BTC_HID_RCU_VOICE = BIT(4), + BTC_HID_OTHER_LEGACY = BIT(5) +}; + +enum btc_bt_a2dp_type { + BTC_A2DP_LEGACY = 0, + BTC_A2DP_TWS_SNIFF = 1, /* Airpod */ + BTC_A2DP_TWS_RELAY = 2, /* RTL8763B */ +}; + +enum btc_bt_PAN_type { + BTC_BT_PAN_ONLY = 0, + BTC_BT_OPP_ONLY = 1 +}; + +enum btc_bt_scan_type { + BTC_SCAN_INQ = 0, + BTC_SCAN_PAGE, + BTC_SCAN_BLE, + BTC_SCAN_INIT, + BTC_SCAN_TV, + BTC_SCAN_ADV, + BTC_SCAN_MAX1 +}; + +enum btc_bt_mailbox_id { + BTC_BTINFO_REPLY = 0x23, + BTC_BTINFO_AUTO = 0x27 +}; + +enum { + BTC_BT_HFP = BIT(0), + BTC_BT_HID = BIT(1), + BTC_BT_A2DP = BIT(2), + BTC_BT_PAN = BIT(3), + BTC_PROFILE_MAX = 4 +}; + +enum { + BTC_BT_IQK_OK = 0, + BTC_BT_IQK_START = 1, + BTC_BT_IQK_STOP = 2, + BTC_BT_IQK_MAX +}; + +enum { + BTC_ANT_SHARED = 0, + BTC_ANT_DEDICATED, + BTC_ANTTYPE_MAX +}; + +enum { + BTC_BT_ALONE = 0, + BTC_BT_BTG +}; + +enum { + BTC_SWITCH_INTERNAL = 0, + BTC_SWITCH_EXTERNAL +}; + +enum { + BTC_RESET_CX = BIT(0), + BTC_RESET_DM = BIT(1), + BTC_RESET_CTRL = BIT(2), + BTC_RESET_CXDM = BIT(0) | BIT(1), + BTC_RESET_BTINFO = BIT(3), + BTC_RESET_MDINFO = BIT(4), + BTC_RESET_ALL = 0xff +}; + +enum btc_gnt_state { + BTC_GNT_HW = 0, + BTC_GNT_SW_LO, + BTC_GNT_SW_HI, + BTC_GNT_MAX +}; + +enum btc_wl_max_tx_time { + BTC_MAX_TX_TIME_L1 = 500, + BTC_MAX_TX_TIME_L2 = 1000, + BTC_MAX_TX_TIME_L3 = 2000, + BTC_MAX_TX_TIME_DEF = 5280 +}; + +enum btc_wl_max_tx_retry { + BTC_MAX_TX_RETRY_L1 = 7, + BTC_MAX_TX_RETRY_L2 = 15, + BTC_MAX_TX_RETRY_DEF = 31 +}; + +struct btc_wl_tx_limit_para { + u16 enable; + u32 tx_time; /* unit: us */ + u16 tx_retry; +}; + +struct btc_rf_trx_para { + u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ + u32 wl_rx_gain; /* rx gain table index (TBD.) */ + u32 bt_tx_power; /* decrease Tx power (dB) */ + u32 bt_rx_gain; /* LNA constrain level */ +}; + +struct btc_gnt_ctrl { + u8 gnt_bt_sw_en; + u8 gnt_bt; + u8 gnt_wl_sw_en; + u8 gnt_wl; +}; + +struct btc_fw_dm { + u32 freerun: 1; + u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */ + u32 wl_mimo_ps: 1; + u32 leak_ap: 1; + u32 igno_bt: 1; + u32 noisy_level: 3; + u32 set_ant_path: 16; + u32 rsvd: 7; +}; + +struct btc_cxr_result { + struct btc_fw_dm dm; + struct btc_rf_trx_para rf_trx_para; + u32 cx_state_map; + u32 policy_type; + u32 run_cnt; + + char run_reason[BTC_RSN_MAXLEN]; + char run_action[BTC_ACT_MAXLEN]; +}; + +struct btc_bt_hfp_desc { + u32 exist: 1; + u32 type: 2; /* refer to btc_bt_hfp_type */ + u32 rsvd: 29; +}; + +struct btc_bt_hid_desc { + u32 exist: 1; + u32 slot_info: 2; + u32 pair_cnt: 2; + u32 type: 8; /* refer to btc_bt_hid_type */ + u32 rsvd: 19; +}; + +struct btc_bt_a2dp_desc { + u8 exist: 1; + u8 exist_last: 1; + u8 play_latency: 1; + u8 type: 3; /* refer to btc_bt_a2dp_type */ + u8 active: 1; + u8 sink: 1; + + u8 bitpool; + u16 vendor_id; + u32 device_name; + u32 flush_time; +}; + +struct btc_bt_pan_desc { + u32 exist: 1; + u32 type: 1; /* refer to btc_bt_pan_type */ + u32 active: 1; + u32 rsvd: 29; +}; + +struct btc_wl_nhm { + s8 instant_wl_nhm_dbm; + s8 instant_wl_nhm_per_mhz; + u16 valid_record_times; + s8 record_pwr[16]; + u8 record_ratio[16]; + s8 pwr; /* dbm_per_MHz */ + u8 ratio; + u8 current_status; + u8 refresh; + bool start_flag; + u8 last_ccx_rpt_stamp; +}; + +struct btc_chip_ops { + void (*set_rfe)(struct btc_t *btc); + void (*init_cfg)(struct btc_t *btc); + void (*wl_pri)(struct btc_t *btc, u8 mask, bool state); + void (*wl_tx_power)(struct btc_t *btc, u32 level); + void (*wl_rx_gain)(struct btc_t *btc, u32 level); + void (*wl_s1_standby)(struct btc_t *btc, u32 state); + void (*wl_req_mac)(struct btc_t *btc, u8 mac_id); + void (*update_bt_cnt)(struct btc_t *btc); + u8 (*bt_rssi)(struct btc_t *btc, u8 val); +}; + +struct btc_chip { + u8 chip_id; + u32 para_ver; /* chip parameter version */ + u8 btcx_desired; /* bt fw desired coex version */ + u32 wlcx_desired; /* wl fw desired coex version */ + u8 scbd; /* scoreboard version, 0: not support*/ + u8 mailbox; /* mailbox version, 0: not support */ + u8 pta_mode; + u8 pta_direction; + u8 afh_guard_ch; + const u8 *wl_rssi_thres; /* wl rssi thre level */ + const u8 *bt_rssi_thres; /* bt rssi thre level */ + u8 rssi_tol; /* rssi tolerance */ + struct btc_chip_ops *ops; + u8 mon_reg_num; + struct fbtc_mreg *mon_reg; + u8 rf_para_ulink_num; + struct btc_rf_trx_para *rf_para_ulink; + u8 rf_para_dlink_num; + struct btc_rf_trx_para *rf_para_dlink; + +}; + +struct btc_bt_scan_info { + u16 win; + u16 intvl; + u32 enable: 1; + u32 interlace: 1; + u32 rsvd: 30; +}; + +struct btc_bt_rfk_info { + u32 run: 1; + u32 req: 1; + u32 timeout: 1; + u32 rsvd: 29; +}; + +union btc_bt_rfk_info_map { + u32 val; + struct btc_bt_rfk_info map; +}; + +struct btc_bt_ver_info { + u32 fw_coex; /* match with which coex_ver */ + u32 fw; +}; +struct btc_bool_sta_chg { /* status change varible */ + u32 now: 1; + u32 last: 1; + u32 remain: 1; + u32 srvd: 29; +}; + +struct btc_u8_sta_chg { /* status change varible */ + u8 now; + u8 last; + u8 remain; + u8 rsvd; +}; + +struct btc_bit_remap { + u32 index; + u32 bpos; +}; + +struct btc_ant_info { + u8 type; /* shared, dedicated */ + u8 num; + u8 isolation; + + u8 single_pos: 1;/* Single antenna at S0 or S1 */ + u8 diversity: 1; +}; + +struct btc_traffic { + enum rtw_tfc_lvl tx_lvl; + enum rtw_tfc_sts tx_sts; + enum rtw_tfc_lvl rx_lvl; + enum rtw_tfc_sts rx_sts; + u16 tx_rate; + u16 rx_rate; + u8 tx_1ss_limit; +}; + +struct btc_wl_scan_info { + u8 band[HW_PHY_MAX]; + u8 phy_map; + u8 rsvd; +}; + +struct btc_wl_dbcc_info { + u8 op_band[HW_PHY_MAX]; /* op band in each phy */ + u8 scan_band[HW_PHY_MAX]; /* scan band in each phy */ + u8 real_band[HW_PHY_MAX]; + u8 role[HW_PHY_MAX]; /* role in each phy */ +}; + +struct btc_wl_active_role { /* struct size must be n*4 bytes */ + u8 connected: 1; + u8 pid: 3; + u8 phy: 1; + u8 noa: 1; + u8 band: 2; /* enum band_type RF band: 2.4G/5G/6G */ + + u8 client_ps: 1; + u8 bw: 7; /* enum channel_width */ + + u8 role; /*enum role_type */ + u8 ch; + + u16 tx_lvl; + u16 rx_lvl; + u16 tx_rate; + u16 rx_rate; + + u32 noa_duration; /* ms */ +}; + +struct btc_wl_role_info_bpos { + u16 none: 1; + u16 station: 1; + u16 ap: 1; + u16 vap: 1; + u16 adhoc: 1; + u16 adhoc_master: 1; + u16 mesh: 1; + u16 moniter: 1; + u16 p2p_device: 1; + u16 p2p_gc: 1; + u16 p2p_go: 1; + u16 nan: 1; +}; + +union btc_wl_role_info_map { + u16 val; + struct btc_wl_role_info_bpos role; +}; + +struct btc_wl_scc_ctrl { + u8 null_role1; + u8 null_role2; + u8 ebt_null; /* if tx null at EBT slot */ + u8 rsvd; +}; + +struct btc_wl_role_info { /* struct size must be n*4 bytes */ + u8 connect_cnt; + u8 link_mode; + union btc_wl_role_info_map role_map; + struct btc_wl_active_role active_role[MAX_WIFI_ROLE_NUMBER]; + u32 mrole_type; /* btc_wl_mrole_type */ + u32 mrole_noa_duration; /* ms */ +}; + +struct btc_statistic { + u8 rssi; /* 0%~110% (dBm = rssi -110) */ + struct btc_traffic traffic; +}; + +struct btc_wl_stat_info { + u8 pid; + struct btc_statistic stat; +}; + +struct btc_wl_link_info { + struct btc_statistic stat; + enum rtw_traffic_dir dir; + struct rtw_chan_def chdef; + + u8 mode; /* wl mode: 11b, 11g, 11n... */ + u8 ch; + u8 bw; + u8 band; /* enum RF band: 2.4G/5G/6G */ + u8 role; /*enum role_type */ + u8 pid; /* MAC HW Port id: 0~4 */ + u8 phy; /* PHY-0 or PHY-1*/ + u8 dtim_period; + + u8 busy; + u8 rssi_state[BTC_WL_RSSI_THMAX]; + u8 mac_addr[6]; + u8 tx_retry; + + u16 mac_id; /* 0~63 */ + + u32 bcn_period; + u32 noa_duration; /* us */ + u32 busy_t; /* busy start time */ + u32 tx_time; /* the original max_tx_time */ + u32 client_cnt; /* connected-client cnt for p2p-GO/soft-AP mode */ + u32 rx_rate_drop_cnt; + + u32 active: 1; + u32 noa: 1; /* Todo: for P2P */ + u32 client_ps: 1; /* Todo: for soft-AP */ + u32 connected: 2; +}; + +struct btc_wl_rfk_info { + u32 state: 2; + u32 path_map: 4; + u32 phy_map: 2; + u32 band: 2; /*0:2g, 1:5g, 2:6g */ + u32 type: 8; + u32 rsvd: 14; +}; + +struct btc_wl_ver_info { + u32 fw_coex; /* match with which coex_ver */ + u32 fw; + u32 mac; + u32 bb; + u32 rf; +}; + +struct btc_wl_afh_info { + u8 en; + u8 ch; + u8 bw; + u8 rsvd; +}; + +struct btc_ops { + void (*fw_cmd)(struct btc_t *btc, u8 h2c_class, u8 h2c_func, + u8 *param, u16 len); + void (*ntfy_power_on)(struct btc_t *btc); + void (*ntfy_power_off)(struct btc_t *btc); + void (*ntfy_init_coex)(struct btc_t *btc, u8 mode); + void (*ntfy_scan_start)(struct btc_t *btc, u8 band_idx, u8 band); + void (*ntfy_scan_finish)(struct btc_t *btc, u8 band_idx); + void (*ntfy_switch_band)(struct btc_t *btc, u8 band_idx, u8 band); + void (*ntfy_specific_packet)(struct btc_t *btc, u8 pkt_type); + void (*ntfy_role_info)(struct btc_t *btc, u8 rid, + struct btc_wl_link_info *info, + enum role_state reason); + void (*ntfy_radio_state)(struct btc_t *btc, u8 rf_state); + void (*ntfy_customerize)(struct btc_t *btc, u8 type, u16 len, u8 *buf); + u8 (*ntfy_wl_rfk)(struct btc_t *btc, u8 phy, u8 type, u8 state); + void (*ntfy_wl_sta)(struct btc_t *btc, u8 ntfy_num, + struct btc_wl_stat_info stat_info[], u8 reason); + void (*ntfy_fwinfo)(struct btc_t *btc, u8 *buf, u32 len, u8 cls, + u8 func); + void (*ntfy_timer)(struct btc_t *btc, u16 tmr_id); +}; + +struct btc_bt_smap { + u32 connect: 1; + u32 ble_connect: 1; + u32 acl_busy: 1; + u32 sco_busy: 1; + u32 mesh_busy: 1; + u32 inq_pag: 1; +}; + +union btc_bt_state_map { + u32 val; + struct btc_bt_smap map; +}; + +struct btc_bt_link_info { + struct btc_u8_sta_chg profile_cnt; + struct btc_bool_sta_chg multi_link; + struct btc_bool_sta_chg relink; + struct btc_bt_hfp_desc hfp_desc; + struct btc_bt_hid_desc hid_desc; + struct btc_bt_a2dp_desc a2dp_desc; + struct btc_bt_pan_desc pan_desc; + union btc_bt_state_map status; + + u8 sut_pwr_level[BTC_PROFILE_MAX]; + u8 golden_rx_shift[BTC_PROFILE_MAX]; + u8 rssi_state[BTC_BT_RSSI_THMAX]; + u8 afh_map[12]; + + u32 role_sw: 1; + u32 slave_role: 1; + u32 afh_update: 1; + u32 cqddr: 1; + u32 rssi: 8; + u32 tx_3M: 1; + u32 rsvd: 19; +}; + +struct btc_3rdcx_info { + u8 type; /* 0: none, 1:zigbee, 2:LTE */ + u8 hw_coex; + u16 rsvd; +}; + +struct btc_rf_para { + u32 tx_pwr_freerun; + u32 rx_gain_freerun; + u32 tx_pwr_perpkt; + u32 rx_gain_perpkt; +}; + +struct btc_bt_info { + struct btc_bt_link_info link_info; + struct btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; + struct btc_bt_ver_info ver_info; + struct btc_bool_sta_chg enable; + struct btc_bool_sta_chg inq_pag; + struct btc_rf_para rf_para; /* for record */ + union btc_bt_rfk_info_map rfk_info; + + u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ + + u32 scbd; /* scoreboard value */ + u32 feature; + + u32 mbx_avl: 1; /* mailbox available */ + u32 whql_test: 1; + u32 igno_wl: 1; + u32 reinit: 1; + u32 ble_scan_en: 1; + u32 btg_type: 1; /* BT located at BT only or BTG */ + u32 inq: 1; + u32 pag: 1; + + u32 run_patch_code: 1; + u32 hi_lna_rx: 1; + u32 scan_rx_low_pri: 1; + + u32 rsvd: 21; +}; + +struct btc_wl_smap { + u32 busy: 1; + u32 scan: 1; + u32 connecting: 1; + u32 roaming: 1; + u32 _4way: 1; + u32 rf_off: 1; + u32 lps: 2; /* 1: LPS-Protocol + WL_power, 2:LPS_Protocol */ + u32 ips: 1; + u32 init_ok: 1; + u32 traffic_dir : 2; + u32 rf_off_pre: 1; + u32 lps_pre: 2; +}; + +union btc_wl_state_map { + u32 val; + struct btc_wl_smap map; +}; + +struct btc_dm_emap { + u32 init: 1; + u32 pta_owner: 1; + u32 wl_rfk_timeout: 1; + u32 bt_rfk_timeout: 1; + + u32 wl_fw_hang: 1; + u32 offload_mismatch: 1; + u32 cycle_hang: 1; + u32 w1_hang: 1; + + u32 b1_hang: 1; + u32 tdma_no_sync: 1; + u32 wl_slot_drift: 1; + u32 bt_slot_drift: 1; /* for external slot control */ +}; + +union btc_dm_error_map { + u32 val; + struct btc_dm_emap map; +}; + +struct btc_wl_info { + struct btc_wl_link_info link_info[MAX_WIFI_ROLE_NUMBER]; + struct btc_wl_rfk_info rfk_info; + struct btc_wl_ver_info ver_info; + struct btc_wl_afh_info afh_info; + struct btc_wl_role_info role_info; + struct btc_wl_scan_info scan_info; + struct btc_wl_dbcc_info dbcc_info; + struct btc_bool_sta_chg cck_lock; + struct btc_rf_para rf_para; /* for record */ + union btc_wl_state_map status; + struct btc_wl_nhm nhm; + + u8 iot_peer; + u8 rssi_level;/* the overall-role rssi-level 0~4, "low_rssi->hi_level"*/ + u8 bssid[6]; + u8 pta_req_mac; + u8 bt_polut_type[2]; /* BT polluted WL-Tx type for phy0/1 */ + + u32 scbd; +}; + +struct btc_module { + struct btc_ant_info ant; + u8 rfe_type; + u8 kt_ver; + + u8 bt_solo: 1; + u8 bt_pos: 1; /* wl-end view: get from efuse, must compare bt.btg_type */ + u8 switch_type: 1; /* WL/BT switch type: 0: internal, 1: external */ + + u8 rsvd; +}; + +struct btc_init_info { + struct btc_module module; + u8 wl_guard_ch; + + u8 wl_only: 1; + u8 wl_init_ok: 1; + u8 dbcc_en: 1; + u8 cx_other: 1; + u8 bt_only: 1; + + u16 rsvd; +}; + +/* recird the last 20 reason/action */ +struct btc_dm_step { + char step[BTC_DM_MAXSTEP][BTC_RSN_MAXLEN]; + u32 cnt; +}; + +/* dynamic coex mechanism */ +struct btc_dm { + struct fbtc_slot slot[CXST_MAX]; + struct fbtc_slot slot_now[CXST_MAX]; + struct fbtc_tdma tdma; + struct fbtc_tdma tdma_now; + struct btc_gnt_ctrl gnt[2]; + struct btc_init_info init_info; /* pass to wl_fw if offload */ + struct btc_rf_trx_para rf_trx_para; + struct btc_wl_tx_limit_para wl_tx_limit; + struct btc_wl_scc_ctrl wl_scc; + struct btc_dm_step dm_step; + union btc_dm_error_map error; + + char run_reason[BTC_RSN_MAXLEN]; + char run_action[BTC_ACT_MAXLEN]; + + u16 slot_dur[CXST_MAX]; /* for user-define slot duration */ + + u32 set_ant_path; + u32 cnt_dm[BTC_DCNT_MAX]; + u32 cnt_notify[BTC_NCNT_MAX]; + + u32 wl_only: 1; /* drv->Fw if offload */ + u32 wl_fw_cx_offload: 1; /* BTC_CX_FW_OFFLOAD from FW code */ + u32 freerun: 1; + u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */ + u32 wl_mimo_ps: 1; + u32 leak_ap: 1; + u32 noisy_level: 3; + u32 coex_info_map: 8; + u32 bt_only: 1; /* drv->Fw if offload */ + u32 wl_btg_rx: 1; /* if wl rx shared with bt */ + u32 trx_para_level: 8; /* trx parameter level */ + u32 wl_stb_chg: 1; /* if change s1 WL standby mode table = Rx */ + u32 rsvd: 3; +}; + +/* the wl/bt/zb cx instance */ +struct btc_cx { + struct btc_wl_info wl; + struct btc_bt_info bt; + struct btc_3rdcx_info other; + struct btc_rf_trx_para rf_para; + u32 state_map; /* wl/bt combined state map */ + u32 cnt_bt[BTC_BCNT_MAX]; + u32 cnt_wl[BTC_WCNT_MAX]; +}; + +struct btc_ctrl { + u32 manual: 1; + u32 igno_bt: 1; + u32 always_freerun: 1; + u32 rsvd: 29; +}; + +struct btc_dbg { + /* cmd "rb" */ + bool rb_done; + u32 rb_val; +}; + +struct btc_tmr { + void *btc; + u16 id; + _os_timer tmr; +}; + +struct btc_t { + struct rtw_phl_com_t *phl; + struct rtw_hal_com_t *hal; + + struct btc_ops *ops; + const struct btc_chip *chip; + + struct btc_cx cx; + struct btc_dm dm; + struct btc_ctrl ctrl; + struct btc_module mdinfo; + struct btf_fwinfo fwinfo; + struct btc_dbg dbg; + + /* btc timers */ + bool tmr_init; + bool tmr_stop; + struct btc_tmr timer[BTC_TIMER_MAX]; + _os_timer delay_tmr; /* a delayed timer to start periodic timer (wait phl started) */ + + char mbuf[BTC_MSG_MAXLEN]; /* msg buffer */ + size_t mlen; /* max msg len */ + + u8 policy[BTC_POLICY_MAXLEN]; /* coex policy buffer */ + u16 policy_len; + u16 policy_type; + + u8 hubmsg[BTC_HUBMSG_MAXLEN]; /* phl hub msg */ + u16 hubmsg_len; + u32 hubmsg_cnt; + u32 bt_req_len; /* request bt-slot in WL SCC/MCC +BT coex */ + bool bt_req_en; +}; + +static void _send_fw_cmd(struct btc_t *btc, u8 h2c_class, u8 h2c_func, + u8 *param, u16 len); +static void _ntfy_power_on(struct btc_t *btc); +static void _ntfy_power_off(struct btc_t *btc); +static void _ntfy_init_coex(struct btc_t *btc, u8 mode); +static void _ntfy_scan_start(struct btc_t *btc, u8 phy_idx, u8 band); +static void _ntfy_scan_finish(struct btc_t *btc, u8 pyh_idx); +static void _ntfy_switch_band(struct btc_t *btc, u8 phy_idx, u8 band); +static void _ntfy_specific_packet(struct btc_t *btc, u8 pkt_type); +static void _ntfy_role_info(struct btc_t *btc, u8 rid, + struct btc_wl_link_info *info, + enum role_state reason); +static void _ntfy_radio_state(struct btc_t *btc, u8 rf_state); +static void _ntfy_customerize(struct btc_t *btc, u8 type, u16 len, u8 *buf); +static u8 _ntfy_wl_rfk(struct btc_t *btc, u8 phy_path, u8 type, u8 state); +static void _ntfy_wl_sta(struct btc_t *btc, u8 ntfy_num, + struct btc_wl_stat_info stat_info[], u8 reason); +static void _ntfy_fwinfo(struct btc_t *btc, u8 *buf, u32 len, u8 cls, u8 func); +static void _ntfy_timer(struct btc_t *btc, u16 tmr_id); + +#ifdef BTC_8852A_SUPPORT +extern const struct btc_chip chip_8852a; +#endif +#ifdef BTC_8852B_SUPPORT +extern const struct btc_chip chip_8852b; +#endif +#ifdef BTC_8852C_SUPPORT +extern const struct btc_chip chip_8852c; +#endif +extern const u32 coex_ver; + +void _update_bt_scbd(struct btc_t *btc, bool only_update); +bool hal_btc_init(struct btc_t *btc); +void hal_btc_deinit(struct btc_t *btc); +u32 _read_cx_reg(struct btc_t *btc, u32 offset); +u8 _read_cx_ctrl(struct btc_t *btc); +void _write_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr, u32 val); +void _read_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr); +u32 _read_scbd(struct btc_t *btc); +void _write_scbd(struct btc_t *btc, u32 val, bool state); +void _run_coex(struct btc_t *btc, const char *reason); +void _set_init_info(struct btc_t *btc); +void _set_bt_psd_report(struct btc_t *btc, u8 start_idx, u8 rpt_type); +void _update_dm_step(struct btc_t *btc, const char *strin); +void hal_btc_send_event(struct btc_t *btc, u8 *buf, u32 len, u16 ev_id); +u8 _get_wl_role_idx(struct btc_t *btc, u8 role); +#endif /*_HAL_BTC_H_*/ diff --git a/phl/hal_g6/btc/halbtc_action.c b/phl/hal_g6/btc/halbtc_action.c new file mode 100644 index 0000000..f459c3e --- /dev/null +++ b/phl/hal_g6/btc/halbtc_action.c @@ -0,0 +1,2009 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_BTC_ACTION_C_ +#include "../hal_headers_le.h" +#include "hal_btc.h" +#include "halbtc_fw.h" +#include "halbtc_fwdef.h" +#include "halbtc_action.h" +#include "halbtc_def.h" + +#ifdef CONFIG_BTCOEX + +#define _set_cx_ctrl(btc, val) rtw_hal_mac_set_coex_ctrl(btc->hal, val) + +/* tdma policy template */ +struct fbtc_tdma t_def[] = { + { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /*CXTD_OFF*/ + { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0}, /*CXTD_B2*/ + { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 2, 0, 0}, /*CXTD_OFF_EXT*/ + { CXTDMA_FIX, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_FIX */ + { CXTDMA_FIX, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, /* CXTD_PFIX */ + { CXTDMA_AUTO, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_AUTO */ + { CXTDMA_AUTO, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, /* CXTD_PAUTO */ + {CXTDMA_AUTO2, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_AUTO2 */ + {CXTDMA_AUTO2, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0} /* CXTD_PAUTO2 */ +}; + +/* slot policy template */ +struct fbtc_slot s_def[] = { + {100, 0x55555555, SLOT_MIX}, /* CXST_OFF */ + { 5, 0xea5a5a5a, SLOT_ISO}, /* CXST_B2W */ + { 70, 0xea5a5a5a, SLOT_ISO}, /* CXST_W1 */ + { 15, 0xea5a5a5a, SLOT_ISO}, /* CXST_W2 */ + { 15, 0xea5a5a5a, SLOT_ISO}, /* CXST_W2B */ + {250, 0xe5555555, SLOT_MIX}, /* CXST_B1 */ + { 7, 0xea5a5a5a, SLOT_MIX}, /* CXST_B2 */ + { 5, 0xe5555555, SLOT_MIX}, /* CXST_B3 */ + { 50, 0xe5555555, SLOT_MIX}, /* CXST_B4 */ + { 20, 0xea5a5a5a, SLOT_ISO}, /* CXST_LK */ + {400, 0x55555555, SLOT_MIX}, /* CXST_BLK */ + { 0, 0xea5a5a5a, SLOT_MIX}, /* CXST_E2G */ + { 0, 0xffffffff, SLOT_MIX}, /* CXST_E5G */ + { 0, 0xe5555555, SLOT_MIX}, /* CXST_EBT */ + { 0, 0xaaaaaaaa, SLOT_ISO}, /* CXST_ENULL */ + {250, 0xea5a5a5a, SLOT_MIX}, /* CXST_WLK */ + { 35, 0xfafafafa, SLOT_ISO}, /* CXST_W1FDD */ + {250, 0xffffffff, SLOT_MIX} /* CXST_B1FDD */ +}; + +const u32 cxtbl[] = { + 0xffffffff, /* 0 */ + 0xaaaaaaaa, /* 1 */ + 0xe5555555, /* 2 */ + 0xee555555, /* 3 */ + 0xd5555555, /* 4 */ + 0x5a5a5a5a, /* 5 */ + 0x5a5a5aaa, /* 6 */ + 0xda5a5a5a, /* 7 */ + 0xea5a5a5a, /* 8 */ + 0x6a5a5aaa, /* 9 */ + 0x6a5a6a5a, /* 10 */ + 0x6a5a6aaa, /* 11 */ + 0x6afa5afa, /* 12 */ + 0xaaaa5aaa, /* 13 */ + 0xaaffffaa, /* 14 */ + 0xaa5555aa, /* 15 */ + 0xfafafafa, /* 16 */ + 0xffffddff, /* 17 */ + 0xdaffdaff, /* 18 */ + 0xfafadafa /* 19 */ +}; + +void _set_bt_ignore_wlan_act(struct btc_t *btc, u8 enable) +{ + u8 buf = 0; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): set bt %s wlan_act\n", + __func__, (enable? "ignore" : "do not ignore")); + + buf = enable; + hal_btc_fw_set_bt(btc, SET_BT_IGNORE_WLAN_ACT, 1, &buf); +} + +void _set_wl_tx_power(struct btc_t *btc, u32 level) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + if (wl->rf_para.tx_pwr_freerun == level) + return; + + wl->rf_para.tx_pwr_freerun = level; + btc->dm.rf_trx_para.wl_tx_power = level; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n", + __func__, level); + + btc->chip->ops->wl_tx_power(btc, level); +} + +void _set_wl_rx_gain(struct btc_t *btc, u32 level) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + if (wl->rf_para.rx_gain_freerun == level) + return; + + wl->rf_para.rx_gain_freerun = level; + btc->dm.rf_trx_para.wl_rx_gain = level; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n", + __func__, level); + + btc->chip->ops->wl_rx_gain(btc, level); +} + +void _set_bt_tx_power(struct btc_t *btc, u32 level) +{ + struct btc_bt_info *bt = &btc->cx.bt; + u8 buf = 0; + + if (bt->rf_para.tx_pwr_freerun == level) + return; + + bt->rf_para.tx_pwr_freerun = level; + btc->dm.rf_trx_para.bt_tx_power = level; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n", + __func__, level); + + buf = (0x100 - level) & bMASKB0; + hal_btc_fw_set_bt(btc, SET_BT_TX_PWR, 1, &buf); +} + +void _set_bt_rx_gain(struct btc_t *btc, u32 level) +{ + struct btc_bt_info *bt = &btc->cx.bt; + u8 buf = 0; + + if (bt->rf_para.rx_gain_freerun == level || + level > BTC_BT_RX_NORMAL_LVL) + return; + + bt->rf_para.rx_gain_freerun = level; + btc->dm.rf_trx_para.bt_rx_gain = level; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n", + __func__, level); + + buf = level & bMASKB0; + + if (buf == BTC_BT_RX_NORMAL_LVL) + _write_scbd(btc, BTC_WSCB_RXGAIN, false); + else + _write_scbd(btc, BTC_WSCB_RXGAIN, true); + + hal_btc_fw_set_bt(btc, SET_BT_LNA_CONSTRAIN, 1, &buf); +} + +static void _set_rf_trx_para(struct btc_t *btc) +{ + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_bt_link_info *b = &bt->link_info; + struct btc_rf_trx_para para; + u8 level_id = 0; + u32 wl_stb_chg = 0; + + if (!dm->freerun) { + dm->trx_para_level = 0; + +#if 1 + /* fix LNA2 = level-5 for BT ACI issue at BTG */ + if (btc->hal->chip_id == CHIP_WIFI6_8852A && + btc->dm.wl_btg_rx && b->profile_cnt.now != 0) + dm->trx_para_level = 1; +#endif + } + + level_id = (u8)dm->trx_para_level; + + if (level_id >= btc->chip->rf_para_dlink_num || + level_id >= btc->chip->rf_para_ulink_num) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): invalid level_id: %d\n", + __func__, level_id); + return; + } + + if (wl->status.map.traffic_dir & BIT(TRAFFIC_UL)) + para = btc->chip->rf_para_ulink[level_id]; + else + para = btc->chip->rf_para_dlink[level_id]; + + _set_wl_tx_power(btc, para.wl_tx_power); + _set_wl_rx_gain(btc, para.wl_rx_gain); + _set_bt_tx_power(btc, para.bt_tx_power); + _set_bt_rx_gain(btc, para.bt_rx_gain); + + if (bt->enable.now == 0 || wl->status.map.rf_off == 1 || + wl->status.map.lps) + wl_stb_chg = 0; + else + wl_stb_chg = 1; + + if (wl_stb_chg != dm->wl_stb_chg) { + dm->wl_stb_chg = wl_stb_chg; + btc->chip->ops->wl_s1_standby(btc, dm->wl_stb_chg); + } + +} + +void _update_btc_state_map(struct btc_t *btc) +{ + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_info *bt = &cx->bt; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + + if (wl->status.map.connecting || wl->status.map._4way || + wl->status.map.roaming) { + cx->state_map = BTC_WLINKING; + } else if (wl->status.map.scan) { /* wl scan */ + if (bt_linfo->status.map.inq_pag) + cx->state_map = BTC_WSCAN_BSCAN; + else + cx->state_map = BTC_WSCAN_BNOSCAN; + } else if (wl->status.map.busy) { /* only busy */ + if (bt_linfo->status.map.inq_pag) + cx->state_map = BTC_WBUSY_BSCAN; + else + cx->state_map = BTC_WBUSY_BNOSCAN; + } else { /* wl idle */ + cx->state_map = BTC_WIDLE; + } +} + +static void _set_bt_golden_rx_range(struct btc_t *btc, u8 p_id, u8 level) +{ + struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; + u8 buf[2] = {0}, pos = 0, i; + + if (p_id > BTC_BT_PAN) + return; + + for (i = 0; i< BTC_PROFILE_MAX; i++) { + if ((p_id >> i) & 0x1) { + pos = i; + break; + } + } + + if (bt_linfo->golden_rx_shift[pos] == level) + return; + + bt_linfo->golden_rx_shift[pos] = level; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): p_id=%d, level=%d\n", + __func__, p_id, level); + + buf[0] = level; + buf[1] = pos; + hal_btc_fw_set_bt(btc, SET_BT_GOLDEN_RX_RANGE, sizeof(buf), buf); +} + +static void _set_bt_afh_info(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_bt_link_info *b = &bt->link_info; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + /*struct btc_module *module = &btc->mdinfo;*/ + u8 en = 0, i, ch = 0, bw = CHANNEL_WIDTH_MAX; + u8 max_role_cnt = BTC_TDMA_WLROLE_MAX; + + if (btc->ctrl.manual || wl->status.map.scan) + return; + + if (btc->hal->dbcc_en) + max_role_cnt++; + + /* TBD if include module->ant.type == BTC_ANT_SHARED */ + if (wl->status.map.rf_off || bt->whql_test || + wl_rinfo->link_mode == BTC_WLINK_NOLINK || + wl_rinfo->link_mode == BTC_WLINK_5G || + wl_rinfo->connect_cnt > max_role_cnt) { + en = false; + ch = 0; + bw = 0; + goto exit; + } else { + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + /* get p2p channel for MCC */ + if (wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { + if (wl_rinfo->active_role[i].role == PHL_RTYPE_AP || + wl_rinfo->active_role[i].role == PHL_RTYPE_P2P_GO || + wl_rinfo->active_role[i].role == PHL_RTYPE_P2P_GC) { + en = true; + ch = wl_rinfo->active_role[i].ch; + bw = wl_rinfo->active_role[i].bw; + break; + } + } else if (wl_rinfo->active_role[i].connected && + wl_rinfo->active_role[i].band == BAND_ON_24G) { + en = true; + ch = wl_rinfo->active_role[i].ch; + bw = wl_rinfo->active_role[i].bw; + + /* get the max bw if scc */ + if (wl_rinfo->link_mode != BTC_WLINK_2G_SCC || + wl_rinfo->active_role[i].bw == CHANNEL_WIDTH_40) { + break; + } + } + } + } + + + if (!en || ch > 14 || ch == 0) + bw = CHANNEL_WIDTH_MAX; + + /* default AFH channel sapn = center-ch +- 6MHz */ + switch (bw) { + case CHANNEL_WIDTH_20: + if (btc->dm.freerun) + bw = 48; + else + bw = 20 + btc->chip->afh_guard_ch * 2; + break; + case CHANNEL_WIDTH_40: + bw = 40 + btc->chip->afh_guard_ch * 2; + break; + case CHANNEL_WIDTH_5: + bw = 5 + btc->chip->afh_guard_ch * 2; + break; + case CHANNEL_WIDTH_10: + bw = 10 + btc->chip->afh_guard_ch * 2; + break; + default: + case CHANNEL_WIDTH_MAX: + en = false; /* turn off AFH info if invalid BW */ + bw = 0; + ch = 0; + break; + } + +exit: + if (wl->afh_info.en == en && + wl->afh_info.ch == ch && + wl->afh_info.bw == bw && + b->profile_cnt.last == b->profile_cnt.now) + return; + + wl->afh_info.en = en; + wl->afh_info.ch = ch; + wl->afh_info.bw = bw; + hal_btc_fw_set_bt(btc, SET_BT_WL_CH_INFO, 3, (u8*)&wl->afh_info); + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): en=%d, ch=%d, bw=%d\n", + __func__, en, ch, bw); + btc->cx.cnt_wl[BTC_WCNT_CH_UPDATE]++; +} + +static void _set_halbb_btg_ctrl(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; + bool is_btg = false; + + if (btc->ctrl.manual) + return; + + /* notify halbb ignore GNT_BT or not for WL BB Rx-AGC control */ + if (wl_rinfo->link_mode == BTC_WLINK_5G) /* always 0 if 5G */ + is_btg = false; + else if (btc->dm.freerun) + is_btg = false; + else if (wl_rinfo->link_mode == BTC_WLINK_25G_DBCC && + wl_dinfo->real_band[1] != BAND_ON_24G) + is_btg = false; + else + is_btg = true; + + if (!run_rsn("_ntfy_init_coex") && is_btg == btc->dm.wl_btg_rx) + return; + + btc->dm.wl_btg_rx = is_btg; + /* rtw_hal_bb_ctrl_btg control the following: + * if btc->dm.wl_btg_rx = false (gnt_wl always = 1) + * Lte_rx: 0x10980[17]=1, 0x10980[29]=0 + * Gnt_wl: 0x10980[18]=1, 0x10980[28]=1 + * Gnt_bt_tx: 0x10980[19]=1, 0x10980[27]=0 + * Gnt_bt: 0x10980[20]=1, 0x10980[26]=0 + * if if btc->dm.wl_btg_rx = true (gnt from MAC) + * Lte_rx: 0x10980[17]=0, 0x10980[29]=0 + * Gnt_wl: 0x10980[18]=0, 0x10980[28]=1 + * Gnt_bt_tx: 0x10980[19]=0, 0x10980[27]=0 + * Gnt_bt: 0x10980[20]=0, 0x10980[26]=0 + */ + + /* skip if MCC dual_band, call ctrl_btg8852a() in WL FW by slot */ + if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC) + return; + + rtw_hal_bb_ctrl_btg(btc->hal, is_btg); +} + +static void _set_bt_slot_req(struct btc_t *btc) +{ + struct btc_bt_link_info *b = &btc->cx.bt.link_info; + u8 len = 0; + + /* don't change bt slot req state during RFK for p2p/mcc case*/ + if (!run_rsn("_ntfy_wl_rfk") && + btc->cx.wl.rfk_info.state == BTC_WRFK_STOP) + btc->bt_req_en = false; + + /* enable bt-slot req if ext-slot-control */ + if (btc->dm.tdma_now.type == CXTDMA_OFF && + btc->dm.tdma_now.ext_ctrl == CXECTL_EXT) + btc->bt_req_en = true; + + if (!btc->bt_req_en) { + len = 0; + } else { + if (b->a2dp_desc.exist || b->a2dp_desc.active || + (b->profile_cnt.now == 1 && + b->hid_desc.pair_cnt == 1 && + b->multi_link.now)) /*a2dp, hid + acl-idle */ { + if (b->profile_cnt.now >= 2) + len = BTC_BSLOT_A2DP_HID; + else + len = BTC_BSLOT_A2DP; + } else if (b->pan_desc.exist || b->status.map.inq_pag) { + len = BTC_BSLOT_INQ; + } else { + len = BTC_BSLOT_IDLE; + } + } + + if (len == btc->bt_req_len) + return; + + btc->bt_req_len = len; + + hal_btc_send_event(btc, (u8*)&btc->bt_req_len, 4, BTC_HMSG_SET_BT_REQ_SLOT); + + PHL_INFO("[BTC], %s(): bt_req_len=%d\n", __func__, btc->bt_req_len); +} + +static void _set_bt_rx_agc(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + struct btc_bt_info *bt = &btc->cx.bt; + bool bt_hi_lna_rx = false; + + if (wl_rinfo->link_mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx) + bt_hi_lna_rx = true; + + if (bt_hi_lna_rx == bt->hi_lna_rx) + return; + + /* true: bt use Hi-LNA rx gain table (f/e/3/2) in -3x~-9xdBm for co-rx + * false: bt use original rx gain table (f/b/7/3/2) + */ + + _write_scbd(btc, BTC_WSCB_BT_HILNA, bt_hi_lna_rx); +} + +static void _set_bt_rx_scan_pri(struct btc_t *btc) +{ + struct btc_bt_info *bt = &btc->cx.bt; + + _write_scbd(btc, BTC_WSCB_RXSCAN_PRI, (bool)(!!bt->scan_rx_low_pri)); +} + +static void _set_halmac_tx_limit(struct btc_t *btc) +{ + struct btc_cx *cx = &btc->cx; + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_info *bt = &cx->bt; + struct btc_bt_link_info *b = &bt->link_info; + struct btc_bt_hfp_desc *hfp = &b->hfp_desc; + struct btc_bt_hid_desc *hid = &b->hid_desc; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + struct btc_wl_link_info *plink = NULL; + u8 mode = wl_rinfo->link_mode, i; + u8 tx_retry = 0; + u32 tx_time = 0; + u16 enable = 0; + bool reenable = false; + + if (btc->ctrl.manual) + return; + + if (btc->dm.freerun || btc->ctrl.igno_bt || b->profile_cnt.now == 0 || + mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) { + enable = 0; + tx_time = BTC_MAX_TX_TIME_DEF; + tx_retry = BTC_MAX_TX_RETRY_DEF; + } else if ((hfp->exist && hid->exist) || hid->pair_cnt > 1) { + enable = 1; + tx_time = BTC_MAX_TX_TIME_L2; + tx_retry = BTC_MAX_TX_RETRY_L1; + } else if (hfp->exist || hid->exist) { + enable = 1; + tx_time = BTC_MAX_TX_TIME_L3; + tx_retry = BTC_MAX_TX_RETRY_L1; + } else { + enable = 0; + tx_time = BTC_MAX_TX_TIME_DEF; + tx_retry = BTC_MAX_TX_RETRY_DEF; + } + + if (dm->wl_tx_limit.enable == enable && + dm->wl_tx_limit.tx_time == tx_time && + dm->wl_tx_limit.tx_retry == tx_retry) + return; + + if (!dm->wl_tx_limit.enable && enable) + reenable = true; + + dm->wl_tx_limit.enable = enable; + dm->wl_tx_limit.tx_time = tx_time; + dm->wl_tx_limit.tx_retry = tx_retry; + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + plink = &wl->link_info[i]; + + if (!plink->connected) + continue; + + /* backup the original tx time before tx-limit on */ + if (reenable) { + rtw_hal_mac_get_tx_time(btc->hal, + (u8)plink->mac_id, + &plink->tx_time); + rtw_hal_mac_get_tx_retry_limit(btc->hal, + (u8)plink->mac_id, + &plink->tx_retry); + } + + /* restore the original tx time if no tx-limit */ + if (!enable) { + rtw_hal_mac_set_tx_time(btc->hal, 1, 1, + (u8)plink->mac_id, + plink->tx_time); + rtw_hal_mac_set_tx_retry_limit(btc->hal, 1, 1, + (u8)plink->mac_id, + plink->tx_retry); + } else { + rtw_hal_mac_set_tx_time(btc->hal, 1, 0, + (u8)plink->mac_id, tx_time); + rtw_hal_mac_set_tx_retry_limit(btc->hal, 1, 0, + (u8)plink->mac_id, + tx_retry); + } + } +} + +static bool _check_freerun(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + struct btc_bt_hid_desc *hid = &bt_linfo->hid_desc; + u8 max_role_cnt = BTC_TDMA_WLROLE_MAX; + + if (btc->hal->dbcc_en) + max_role_cnt++; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + btc->dm.trx_para_level = 0; + return false; + } + + /* The below is dedicated antenna case */ + + if (wl_rinfo->connect_cnt > max_role_cnt) { + btc->dm.trx_para_level = 5; + return true; + } + + if (bt_linfo->profile_cnt.now == 0) { + btc->dm.trx_para_level = 5; + return true; + } + + if (hid->pair_cnt > BTC_TDMA_BTHID_MAX) { + btc->dm.trx_para_level = 5; + return true; + } + + /* Todo: get isolation by BT psd */ + if (btc->mdinfo.ant.isolation >= BTC_FREERUN_ANTISO_MIN) { + btc->dm.trx_para_level = 5; + return true; + } + + if (!wl->status.map.busy) {/* wl idle -> freerun */ + btc->dm.trx_para_level = 5; + return true; + } else if (wl->rssi_level > 1) {/* WL rssi < 50% (-60dBm) */ + btc->dm.trx_para_level = 0; + return false; + } else if (wl->status.map.traffic_dir & BIT(TRAFFIC_UL)) { /* uplink */ + if (wl->rssi_level == 0 && bt_linfo->rssi > 31) { + btc->dm.trx_para_level = 6; + return true; + } else if (wl->rssi_level == 1 && bt_linfo->rssi > 36) { + btc->dm.trx_para_level = 7; + return true; + } else { + btc->dm.trx_para_level = 0; + return false; + } + } else if (wl->status.map.traffic_dir & BIT(TRAFFIC_DL)) { /*downlink*/ + if (bt_linfo->rssi > 28) { + btc->dm.trx_para_level = 6; + return true; + } + } + + btc->dm.trx_para_level = 0; + return false; +} + +static void _set_policy(struct btc_t *btc, u16 policy_type, const char* action) +{ + struct btc_dm *dm = &btc->dm; + struct fbtc_tdma *t = &dm->tdma; + struct fbtc_slot *s = dm->slot; + struct btc_wl_role_info *wl_rinfo = &btc->cx.wl.role_info; + struct btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc; + u8 type, null_role = 0; + u16 dur = 0; + u32 tbl_w1, tbl_b1, tbl_b4; + bool mode = NM_EXEC; + + type = (u8)((policy_type & bMASKB1) >> 8); + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->cx.wl.status.map._4way) + tbl_w1 = cxtbl[1]; + else if (hid->exist && hid->type == BTC_HID_218) + tbl_w1 = cxtbl[7]; /* Ack/BA no break bt Hi-Pri-rx */ + else + tbl_w1 = cxtbl[8]; + + if (dm->leak_ap && + (type == BTC_CXP_PFIX || type == BTC_CXP_PAUTO2)) { + tbl_b1 = cxtbl[3]; + tbl_b4 = cxtbl[3]; + } else if (hid->exist && hid->type == BTC_HID_218) { + tbl_b1 = cxtbl[4]; /* Ack/BA no break bt Hi-Pri-rx */ + tbl_b4 = cxtbl[4]; + } else { + tbl_b1 = cxtbl[2]; + tbl_b4 = cxtbl[2]; + } + } else { + tbl_w1 = cxtbl[16]; /* 19 for HID exist */ + tbl_b1 = cxtbl[17]; + tbl_b4 = cxtbl[17]; + } + + switch(type) { + case BTC_CXP_USERDEF0: + mode = FC_EXEC; + _tdma_cpy(t, &t_def[CXTD_OFF]); + _slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]); + _slot_set_tbl(CXST_OFF, cxtbl[2]); + break; + case BTC_CXP_OFF: /* TDMA off */ + _write_scbd(btc, BTC_WSCB_TDMA, false); + _tdma_cpy(t, &t_def[CXTD_OFF]); + _slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]); + + switch (policy_type) { + case BTC_CXP_OFF_BT: + _slot_set_tbl(CXST_OFF, cxtbl[2]); + break; + case BTC_CXP_OFF_WL: + _slot_set_tbl(CXST_OFF, cxtbl[1]); + break; + case BTC_CXP_OFF_EQ0: + _slot_set_tbl(CXST_OFF, cxtbl[0]); + break; + case BTC_CXP_OFF_EQ1: + _slot_set_tbl(CXST_OFF, cxtbl[16]); + break; + case BTC_CXP_OFF_EQ2: + _slot_set_tbl(CXST_OFF, cxtbl[17]); + break; + case BTC_CXP_OFF_EQ3: + _slot_set_tbl(CXST_OFF, cxtbl[18]); + break; + case BTC_CXP_OFF_BWB0: + _slot_set_tbl(CXST_OFF, cxtbl[5]); + break; + case BTC_CXP_OFF_BWB1: + _slot_set_tbl(CXST_OFF, cxtbl[8]); + break; + case BTC_CXP_OFF_BWB2: + _slot_set_tbl(CXST_OFF, cxtbl[7]); + break; + } + break; + case BTC_CXP_OFFB: /* TDMA off + beacon protect */ + _write_scbd(btc, BTC_WSCB_TDMA, false); + _tdma_cpy(t, &t_def[CXTD_OFF_B2]); + _slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]); + switch (policy_type) { + case BTC_CXP_OFFB_BWB0: + _slot_set_tbl(CXST_OFF, cxtbl[8]); + break; + } + break; + case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_OFF_EXT]); + + if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC && + dm->wl_scc.ebt_null) { + _tdma_set_rxflctrl(1); + _tdma_set_txflctrl(1); + if ((wl_rinfo->mrole_noa_duration > 0) && + (wl_rinfo->mrole_noa_duration + + 2 * BTC_NULL1_EBT_EARLY_T < BTC_SCC_CYCLE)) + dur = BTC_SCC_CYCLE - BTC_NULL1_EBT_EARLY_T - + wl_rinfo->mrole_noa_duration; + } + + switch (policy_type) { + case BTC_CXP_OFFE_2GBWISOB: /* for normal-case */ + _slot_set(CXST_E2G, dur, tbl_w1, SLOT_ISO); + _slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]); + break; + case BTC_CXP_OFFE_2GISOB: /* for bt no-link */ + _slot_set(CXST_E2G, dur, cxtbl[1], SLOT_ISO); + _slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]); + break; + case BTC_CXP_OFFE_2GBWMIXB: /* for GC-only NOA < bt_slot_req */ + _slot_set(CXST_E2G, dur, tbl_w1, SLOT_MIX); + _slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]); + break; + case BTC_CXP_OFFE_2GBWMIXB2: /* for GC+STA NOA < bt_slot_req */ + _slot_set(CXST_E2G, dur, tbl_w1, SLOT_MIX); + _slot_set(CXST_EBT, BTC_BSLOT_A2DP_HID, + cxtbl[2], SLOT_MIX); + break; + case BTC_CXP_OFFE_WL: /*for 4-way */ + _slot_set(CXST_E2G, dur, cxtbl[1], SLOT_MIX); + _slot_set(CXST_EBT, 0, cxtbl[1], SLOT_MIX); + break; + } + + _slot_cpy(&s[CXST_E5G], &s_def[CXST_E5G]); + _slot_cpy(&s[CXST_ENULL], &s_def[CXST_ENULL]); + break; + case BTC_CXP_FIX: /* TDMA Fix-Slot */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_FIX]); + switch (policy_type) { + case BTC_CXP_FIX_TD3030: /* W1:B1 = 30:30 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD5050: /* W1:B1 = 50:50 */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 50, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD2030: /* W1:B1 = 20:30 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD4010: /* W1:B1 = 40:10 */ + _slot_set(CXST_W1, 40, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD4010ISO: /* W1:B1 = 40:10 for WL busy/scan */ + _slot_set(CXST_W1, 40, cxtbl[1], SLOT_ISO); + _slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD7010: /* W1:B1 = 70:10 */ + _slot_set(CXST_W1, 70, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD2060: /* W1:B1 = 20:60 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD3060: /* W1:B1 = 30:60 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD2080: /* W1:B1 = 20:80 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 80, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + break; + } + break; + case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_PFIX]); + + switch (policy_type) { + case BTC_CXP_PFIX_TD3030: /* W1:B1 = 30:30 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TD5050: /* W1:B1 = 50:50 */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 50, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TD2030: /* W1:B1 = 20:30 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TD2060: /* W1:B1 = 20:60 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TD3070: /* W1:B1 = 30:60 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TD2080: /* W1:B1 = 20:80 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, 80, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PFIX_TDW1B1: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + break; + } + break; + case BTC_CXP_AUTO: /* TDMA Auto-Slot */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_AUTO]); + switch (policy_type) { + case BTC_CXP_AUTO_TD50B1: /* W1:B1 = 50:BTC_B1_MAX */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_AUTO_TD60B1: /* W1:B1 = 60:BTC_B1_MAX */ + _slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_AUTO_TD20B1: /* W1:B1 = 20:BTC_B1_MAX */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + break; + } + break; + case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_PAUTO]); + switch (policy_type) { + case BTC_CXP_PAUTO_TD50B1: /* W1:B1 = 50:BTC_B1_MAX */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PAUTO_TD60B1: /* W1:B1 = 60:BTC_B1_MAX */ + _slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PAUTO_TD20B1: /* W1:B1 = 20:BTC_B1_MAX */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_PAUTO_TDW1B1: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + break; + } + break; + case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_AUTO2]); + switch (policy_type) { + case BTC_CXP_AUTO2_TD3050: /* W1:B4 = 30:50 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_AUTO2_TD3070: /* W1:B4 = 30:70 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 70, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_AUTO2_TD5050: /* W1:B4 = 50:50 */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_AUTO2_TD6060: /* W1:B4 = 60:60 */ + _slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 60, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_AUTO2_TD2080: /* W1:B4 = 20:80 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 80, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, dm->slot_dur[CXST_B4], + tbl_b4, SLOT_MIX); + break; + } + break; + case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */ + _write_scbd(btc, BTC_WSCB_TDMA, true); + _tdma_cpy(t, &t_def[CXTD_PAUTO2]); + switch (policy_type) { + case BTC_CXP_PAUTO2_TD3050: /* W1:B4 = 30:50 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_PAUTO2_TD3070: /* W1:B4 = 30:70 */ + _slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, cxtbl[3], SLOT_MIX); + _slot_set(CXST_B4, 70, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_PAUTO2_TD5050: /* W1:B4 = 50:50 */ + _slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_PAUTO2_TD6060: /* W1:B4 = 60:60 */ + _slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 60, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_PAUTO2_TD2080: /* W1:B4 = 20:80 */ + _slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, 80, tbl_b4, SLOT_MIX); + break; + case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */ + _slot_set(CXST_W1, dm->slot_dur[CXST_W1], + tbl_w1, SLOT_ISO); + _slot_set(CXST_B1, dm->slot_dur[CXST_B1], + tbl_b1, SLOT_MIX); + _slot_set(CXST_B4, dm->slot_dur[CXST_B4], + tbl_b4, SLOT_MIX); + break; + } + break; + } + + if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC && dm->tdma.rxflctrl) { + null_role = (dm->wl_scc.null_role1 & 0xf) + + ((dm->wl_scc.null_role2 & 0xf) << 4); + _tdma_set_flctrl_role(null_role); + } + + /* enter leak_slot after each null-1 */ + if (dm->leak_ap && dm->tdma.leak_n > 1) + _tdma_set_lek(1); + + if (run_rsn("_cmd_set_coex")) + mode = FC_EXEC; + + _update_poicy(btc, mode, policy_type, action); +} + +void _set_gnt_wl(struct btc_t *btc, u8 phy_map, u8 state) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_dm *dm = &btc->dm; + struct btc_gnt_ctrl *g = dm->gnt; + u8 i; + + if (phy_map > BTC_PHY_ALL) + return; + + for (i = 0; i < BTC_PHY_MAX; i++) { + if (!(phy_map & BIT(i))) + continue; + + switch (state) { + case BTC_GNT_HW: + g[i].gnt_wl_sw_en = 0; + g[i].gnt_wl = 0; + break; + case BTC_GNT_SW_LO: + g[i].gnt_wl_sw_en = 1; + g[i].gnt_wl = 0; + break; + case BTC_GNT_SW_HI: + g[i].gnt_wl_sw_en = 1; + g[i].gnt_wl = 1; + break; + } + } + + rtw_hal_mac_set_grant(h, (u8*)g); +} + +void _set_gnt_bt(struct btc_t *btc, u8 phy_map, u8 state) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_dm *dm = &btc->dm; + struct btc_gnt_ctrl *g = dm->gnt; + u8 i; + + if (phy_map > BTC_PHY_ALL) + return; + + for (i = 0; i < BTC_PHY_MAX; i++) { + if (!(phy_map & BIT(i))) + continue; + + switch (state) { + case BTC_GNT_HW: + g[i].gnt_bt_sw_en = 0; + g[i].gnt_bt = 0; + break; + case BTC_GNT_SW_LO: + g[i].gnt_bt_sw_en = 1; + g[i].gnt_bt = 0; + break; + case BTC_GNT_SW_HI: + g[i].gnt_bt_sw_en = 1; + g[i].gnt_bt = 1; + break; + } + } + + rtw_hal_mac_set_grant(h, (u8*)g); +} + +static void _set_bt_plut(struct btc_t *btc, u8 phy_map, u8 tx_val, u8 rx_val) +{ + if (phy_map & BTC_PHY_0) { + rtw_hal_mac_set_polluted(btc->hal, HW_PHY_0, tx_val, rx_val); + btc->cx.wl.bt_polut_type[HW_PHY_0] = tx_val; + } + + if (!btc->hal->dbcc_en) + return; + + if (phy_map & BTC_PHY_1) { + rtw_hal_mac_set_polluted(btc->hal, HW_PHY_1, tx_val, rx_val); + btc->cx.wl.bt_polut_type[HW_PHY_1] = tx_val; + } +} + +static void _set_ant(struct btc_t *btc, bool force_exec, u8 phy_map, u8 type) +{ + struct btc_dm *dm = &btc->dm; + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_bt_info *bt = &cx->bt; + struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; + u8 gnt_wl_ctrl, gnt_bt_ctrl, plt_ctrl, i, b2g = 0; + u32 ant_path_type; + + ant_path_type = ((phy_map << 8) + type); + + if (run_rsn("_cmd_set_coex") || run_rsn("_ntfy_power_off") || + run_rsn("_ntfy_radio_state")) + force_exec = FC_EXEC; + + if (!force_exec && (ant_path_type == dm->set_ant_path)) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): return by no change!!\n", + __func__); + return; + } else if (bt->rfk_info.map.run) { + PHL_INFO("[BTC], %s(): return by bt rfk!!\n", __func__); + return; + } else if (!run_rsn("_ntfy_wl_rfk") && + wl->rfk_info.state != BTC_WRFK_STOP) { + PHL_INFO("[BTC], %s(): return by wl rfk!!\n", __func__); + return; + } + + dm->set_ant_path = ant_path_type; + + PHL_INFO("[BTC], %s(): path=0x%x, set_type=%s\n", __func__, + phy_map, id_to_str(BTC_STR_ANTPATH, dm->set_ant_path & 0xff)); + + switch (type){ + case BTC_ANT_WPOWERON: + _set_cx_ctrl(btc, BTC_CTRL_BY_BT); + break; + case BTC_ANT_WINIT: + /* To avoid BT MP driver case (bt_enable but no mailbox) */ + if (bt->enable.now && bt->run_patch_code) { + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_LO); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI); + } else { + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO); + } + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + _set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_BT, BTC_PLT_BT); + break; + case BTC_ANT_WONLY: + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO); + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + _set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); + break; + case BTC_ANT_WOFF: + _set_cx_ctrl(btc, BTC_CTRL_BY_BT); + _set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); + break; + case BTC_ANT_W2G: + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + if (btc->hal->dbcc_en) { + for (i = 0; i < HW_PHY_MAX; i++) { + b2g = (wl_dinfo->real_band[i] == BAND_ON_24G); + + gnt_wl_ctrl = (b2g? BTC_GNT_HW : BTC_GNT_SW_HI); + _set_gnt_wl(btc, BIT(i), gnt_wl_ctrl); + + gnt_bt_ctrl = BTC_GNT_HW; + _set_gnt_bt(btc, BIT(i), gnt_bt_ctrl); + + plt_ctrl = (b2g? BTC_PLT_BT : BTC_PLT_NONE); + _set_bt_plut(btc, BIT(i), plt_ctrl, plt_ctrl); + } + } else { + _set_gnt_wl(btc, phy_map, BTC_GNT_HW); + _set_gnt_bt(btc, phy_map, BTC_GNT_HW); + plt_ctrl = BTC_PLT_BT; + _set_bt_plut(btc, BTC_PHY_ALL, plt_ctrl, plt_ctrl); + } + break; + case BTC_ANT_W5G: + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI); + _set_gnt_bt(btc, phy_map, BTC_GNT_HW); + _set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); + break; + case BTC_ANT_W25G: + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + if (btc->hal->dbcc_en) { + /* if BAND_ON_24G, the other role in the sane PHY = 5G*/ + for (i = 0; i < HW_PHY_MAX; i++) { + b2g = (wl_dinfo->real_band[i] == BAND_ON_24G); + + gnt_wl_ctrl = (b2g? BTC_GNT_HW : BTC_GNT_SW_HI); + _set_gnt_wl(btc, BIT(i), gnt_wl_ctrl); + + gnt_bt_ctrl = BTC_GNT_HW; + _set_gnt_bt(btc, BIT(i), gnt_bt_ctrl); + + plt_ctrl = (b2g? BTC_PLT_GNT_WL : BTC_PLT_NONE); + _set_bt_plut(btc, BIT(i), plt_ctrl, plt_ctrl); + } + } else { + _set_gnt_wl(btc, phy_map, BTC_GNT_HW); + _set_gnt_bt(btc, phy_map, BTC_GNT_HW); + plt_ctrl = BTC_PLT_GNT_WL; + _set_bt_plut(btc, BTC_PHY_ALL, plt_ctrl, plt_ctrl); + } + break; + case BTC_ANT_FREERUN: + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI); + _set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); + break; + case BTC_ANT_WRFK: + _set_cx_ctrl(btc, BTC_CTRL_BY_WL); + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO); + _set_bt_plut(btc, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); + break; + case BTC_ANT_BRFK: + _set_cx_ctrl(btc, BTC_CTRL_BY_BT); + _set_gnt_wl(btc, phy_map, BTC_GNT_SW_LO); + _set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI); + _set_bt_plut(btc, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); + break; + } +} + +void _action_wl_only(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_wl_init(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WINIT); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_wl_off(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + + PHL_INFO("[BTC], %s !!\n", __func__); + + /* don't set PTA control if LPS */ + if (wl->status.map.rf_off || btc->dm.bt_only) { + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF); + } else if (wl->status.map.lps == 2) { + if (wl->role_info.link_mode == BTC_WLINK_5G) + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); + else + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + } + + if (wl->role_info.link_mode == BTC_WLINK_5G) { + _set_policy(btc, BTC_CXP_OFF_EQ0, __func__); + } else if (wl->status.map.lps == 2) { + if (btc->cx.bt.link_info.a2dp_desc.active) + _set_policy(btc, BTC_CXP_OFF_BT, __func__); + else + _set_policy(btc, BTC_CXP_OFF_BWB1, __func__); + } else { + _set_policy(btc, BTC_CXP_OFF_BT, __func__); + } +} + +void _action_freerun(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + btc->dm.freerun = true; + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_bt_whql(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_bt_rfk(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_BRFK); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_bt_off(struct btc_t *btc) +{ + PHL_INFO("[BTC], %s !!\n", __func__); + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +static void _action_bt_idle(struct btc_t *btc) +{ + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_bt_link_info *b = &btc->cx.bt.link_info; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt idle*/ + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ + if (b->status.map.connect) + policy_type = BTC_CXP_FIX_TD4010; + else + policy_type = BTC_CXP_FIX_TD4010ISO; + break; + case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */ + if (bt->pag) + policy_type = BTC_CXP_PFIX_TD2080; + else + policy_type = BTC_CXP_PFIX_TD5050; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */ + if (bt->pag) + policy_type = BTC_CXP_FIX_TD2080; + else + policy_type = BTC_CXP_FIX_TD5050; + break; + case BTC_WLINKING: /* wl-connecting + bt-inq or bt-idle */ + if (bt->pag) + policy_type = BTC_CXP_FIX_TD2080; + else + policy_type = BTC_CXP_FIX_TD7010; + break; + case BTC_WIDLE: /* wl-idle + bt-idle */ + policy_type = BTC_CXP_OFF_BWB1; + break; + } + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_hfp(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->cx.wl.status.map._4way) + policy_type = BTC_CXP_OFF_WL; + else + policy_type = BTC_CXP_OFF_BWB1; + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ2; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_hid(struct btc_t *btc) +{ + struct btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->cx.wl.status.map._4way) { + policy_type = BTC_CXP_OFF_WL; + } else if (hid->type == BTC_HID_218) { + btc->cx.bt.scan_rx_low_pri = true; + policy_type = BTC_CXP_OFF_BWB2; + } else { + policy_type = BTC_CXP_OFF_BWB1; + } + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ3; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_a2dp(struct btc_t *btc) +{ + struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; + struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; + struct btc_dm *dm = &btc->dm; + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */ + if (a2dp.vendor_id == 0x4c || dm->leak_ap || + bt_linfo->slave_role) { + if (bt_linfo->slave_role) + dm->slot_dur[CXST_W1] = 20; + else + dm->slot_dur[CXST_W1] = 40; + dm->slot_dur[CXST_B1] = BTC_B1_MAX; + policy_type = BTC_CXP_PAUTO_TDW1B1; + } else { + policy_type = BTC_CXP_PAUTO_TD50B1; + } + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */ + policy_type = BTC_CXP_PAUTO2_TD3050; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */ + policy_type = BTC_CXP_AUTO2_TD3050; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */ + case BTC_WLINKING: /* wl-connecting + bt-A2DP */ + if (a2dp.vendor_id == 0x4c || dm->leak_ap || + bt_linfo->slave_role) { + if (bt_linfo->slave_role) + dm->slot_dur[CXST_W1] = 20; + else + dm->slot_dur[CXST_W1] = 40; + dm->slot_dur[CXST_B1] = BTC_B1_MAX; + policy_type = BTC_CXP_AUTO_TDW1B1; + } else { + policy_type = BTC_CXP_AUTO_TD50B1; + } + break; + case BTC_WIDLE: /* wl-idle + bt-A2DP */ + policy_type = BTC_CXP_AUTO_TD20B1; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_a2dpsink(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2dp_Sink */ + policy_type = BTC_CXP_PFIX_TD2030; + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2dp_Sink */ + policy_type = BTC_CXP_PFIX_TD2060; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2dp_Sink */ + policy_type = BTC_CXP_FIX_TD2030; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2dp_Sink */ + policy_type = BTC_CXP_FIX_TD2060; + break; + case BTC_WLINKING: /* wl-connecting + bt-A2dp_Sink */ + policy_type = BTC_CXP_FIX_TD3030; + break; + case BTC_WIDLE: /* wl-idle + bt-A2dp_Sink */ + policy_type = BTC_CXP_FIX_TD2080; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_pan(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN */ + policy_type = BTC_CXP_PFIX_TD5050; + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN */ + policy_type = BTC_CXP_PFIX_TD3070; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN */ + policy_type = BTC_CXP_FIX_TD3030; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN */ + policy_type = BTC_CXP_FIX_TD3060; + break; + case BTC_WLINKING: /* wl-connecting + bt-PAN */ + policy_type = BTC_CXP_FIX_TD4010ISO; + break; + case BTC_WIDLE: /* wl-idle + bt-pan */ + policy_type = BTC_CXP_PFIX_TD2080; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_a2dp_hid(struct btc_t *btc) +{ + struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; + struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; + struct btc_dm *dm = &btc->dm; + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */ + case BTC_WIDLE: /* wl-idle + bt-A2DP */ + if (a2dp.vendor_id == 0x4c || dm->leak_ap || + bt_linfo->slave_role) { + if (bt_linfo->slave_role) + dm->slot_dur[CXST_W1] = 20; + else + dm->slot_dur[CXST_W1] = 40; + dm->slot_dur[CXST_W1] = 40; + dm->slot_dur[CXST_B1] = BTC_B1_MAX; + policy_type = BTC_CXP_PAUTO_TDW1B1; + } else { + policy_type = BTC_CXP_PAUTO_TD50B1; + } + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */ + policy_type = BTC_CXP_PAUTO2_TD3050; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */ + policy_type = BTC_CXP_AUTO2_TD3050; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */ + case BTC_WLINKING: /* wl-connecting + bt-A2DP */ + if (a2dp.vendor_id == 0x4c || dm->leak_ap || + bt_linfo->slave_role) { + if (bt_linfo->slave_role) + dm->slot_dur[CXST_W1] = 20; + else + dm->slot_dur[CXST_W1] = 40; + dm->slot_dur[CXST_B1] = BTC_B1_MAX; + policy_type = BTC_CXP_AUTO_TDW1B1; + } else { + policy_type = BTC_CXP_AUTO_TD50B1; + } + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_a2dp_pan(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN */ + policy_type = BTC_CXP_PAUTO2_TD3070; + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN */ + policy_type = BTC_CXP_PAUTO2_TD3070; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN */ + policy_type = BTC_CXP_AUTO2_TD5050; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN */ + policy_type = BTC_CXP_AUTO2_TD3070; + break; + case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN */ + policy_type = BTC_CXP_AUTO2_TD3050; + break; + case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN */ + policy_type = BTC_CXP_PAUTO2_TD2080; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_pan_hid(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN+HID */ + policy_type = BTC_CXP_PFIX_TD3030; + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN+HID */ + policy_type = BTC_CXP_PFIX_TD3070; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN+HID */ + policy_type = BTC_CXP_FIX_TD3030; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN+HID */ + policy_type = BTC_CXP_FIX_TD3060; + break; + case BTC_WLINKING: /* wl-connecting + bt-PAN+HID */ + policy_type = BTC_CXP_FIX_TD4010; + break; + case BTC_WIDLE: /* wl-idle + bt-PAN+HID */ + policy_type = BTC_CXP_PFIX_TD2080; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +static void _action_bt_a2dp_pan_hid(struct btc_t *btc) +{ + u16 policy_type = BTC_CXP_OFF_BT; + + switch(btc->cx.state_map) { + case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN+HID */ + policy_type = BTC_CXP_PAUTO2_TD3070; + break; + case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN+HID */ + policy_type = BTC_CXP_PAUTO2_TD3070; + break; + case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN+HID */ + policy_type = BTC_CXP_AUTO2_TD3070; + break; + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN+HID */ + case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN+HID */ + policy_type = BTC_CXP_AUTO2_TD3050; + break; + case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN+HID */ + policy_type = BTC_CXP_PAUTO2_TD2080; + break; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_5g(struct btc_t *btc) +{ + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); + _set_policy(btc, BTC_CXP_OFF_EQ0, __func__); +} + +void _action_wl_other(struct btc_t *btc) +{ + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + _set_policy(btc, BTC_CXP_OFFB_BWB0, __func__); + else + _set_policy(btc, BTC_CXP_OFF_EQ0, __func__); +} + +void _action_wl_idle(struct btc_t *btc) +{ + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + _set_policy(btc, BTC_CXP_OFFB_BWB0, __func__); + else + _set_policy(btc, BTC_CXP_OFF_EQ0, __func__); +} + +void _action_wl_nc(struct btc_t *btc) +{ + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, BTC_CXP_OFF_BT, __func__); +} + +void _action_wl_rfk(struct btc_t *btc) +{ + struct btc_wl_rfk_info rfk = btc->cx.wl.rfk_info; + + if (rfk.state != BTC_WRFK_START) + return; + + PHL_INFO("[BTC], %s(): band = %d\n", __func__, rfk.band); + + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK); + _set_policy(btc, BTC_CXP_OFF_WL, __func__); + +#if 0 + if (rfk.band == BAND_ON_24G) { + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK); + _set_policy(btc, BTC_CXP_OFF_WL, __func__); + } else { + _set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN); + _set_policy(btc, BTC_CXP_OFF_EQ0, __func__); + } +#endif +} + +void _action_common(struct btc_t *btc) +{ + _set_halbb_btg_ctrl(btc); + _set_halmac_tx_limit(btc); + _set_bt_afh_info(btc); + _set_bt_rx_agc(btc); /* must call after _set_halbb_btg_ctrl */ + _set_bt_slot_req(btc); + _set_bt_rx_scan_pri(btc); + _set_rf_trx_para(btc); +} + +static void _action_by_bt(struct btc_t *btc) +{ + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + struct btc_bt_hid_desc hid = bt_linfo->hid_desc; + struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; + struct btc_bt_pan_desc pan = bt_linfo->pan_desc; + u8 profile_map = 0; + + if (bt_linfo->hfp_desc.exist) + profile_map |= BTC_BT_HFP; + + if (bt_linfo->hid_desc.exist) + profile_map |= BTC_BT_HID; + + if (bt_linfo->a2dp_desc.exist) + profile_map |= BTC_BT_A2DP; + + if (bt_linfo->pan_desc.exist) + profile_map |= BTC_BT_PAN; + + switch (profile_map) { + case 0: + if (_check_freerun(btc)) + _action_freerun(btc); + else if (a2dp.active || pan.active) + _action_bt_pan(btc); + else + _action_bt_idle(btc); + break; + case BTC_BT_HFP: + if (_check_freerun(btc)) + _action_freerun(btc); + else + _action_bt_hfp(btc); + break; + case BTC_BT_HFP | BTC_BT_HID: + case BTC_BT_HID: + if (_check_freerun(btc)) + _action_freerun(btc); + else + _action_bt_hid(btc); + break; + case BTC_BT_A2DP: + if (_check_freerun(btc)) + _action_freerun(btc); + else if (a2dp.sink) + _action_bt_a2dpsink(btc); + else if (bt_linfo->multi_link.now && !hid.pair_cnt) + _action_bt_a2dp_pan(btc); + else + _action_bt_a2dp(btc); + break; + case BTC_BT_PAN: + _action_bt_pan(btc); + break; + case BTC_BT_A2DP | BTC_BT_HFP: + case BTC_BT_A2DP | BTC_BT_HID: + case BTC_BT_A2DP | BTC_BT_HFP | BTC_BT_HID: + if (_check_freerun(btc)) + _action_freerun(btc); + else + _action_bt_a2dp_hid(btc); + break; + case BTC_BT_A2DP | BTC_BT_PAN: + _action_bt_a2dp_pan(btc); + break; + case BTC_BT_PAN | BTC_BT_HFP: + case BTC_BT_PAN | BTC_BT_HID: + case BTC_BT_PAN | BTC_BT_HFP | BTC_BT_HID: + _action_bt_pan_hid(btc); + break; + case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HID: + case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HFP: + default: + _action_bt_a2dp_pan_hid(btc); + break; + } +} + +void _action_wl_2g_sta(struct btc_t *btc) +{ + _action_by_bt(btc); +} + +void _action_wl_scan(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; + + if (btc->hal->dbcc_en) { + if (wl_dinfo->real_band[HW_PHY_0] != BAND_ON_24G && + wl_dinfo->real_band[HW_PHY_1] != BAND_ON_24G) + _action_wl_5g(btc); + else + _action_by_bt(btc); + } else { + if (wl->scan_info.band[HW_PHY_0] != BAND_ON_24G) + _action_wl_5g(btc); + else + _action_by_bt(btc); + } +} + +void _action_wl_25g_mcc(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED)/* shared-antenna */ { + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_mcc(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_scc(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_dm *dm = &btc->dm; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + u16 policy_type = BTC_CXP_OFF_BT; + u32 dur; + + if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED) { + policy_type = BTC_CXP_OFF_EQ0; + goto exit; + } + + /* shared-antenna */ + switch(wl_rinfo->mrole_type) { + default: +#if 0 + case BTC_WLMROLE_STA_GO: + case BTC_WLMROLE_STA_GO_NOA: + dm->wl_scc.null_role1 = PHL_RTYPE_STATION; + dm->wl_scc.null_role2 = PHL_RTYPE_NONE; + dm->wl_scc.ebt_null = 0; + policy_type = BTC_CXP_OFF_BWB1; +#endif + break; + case BTC_WLMROLE_STA_GC: + dm->wl_scc.null_role1 = PHL_RTYPE_STATION; + dm->wl_scc.null_role2 = PHL_RTYPE_P2P_GC; + dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ + _action_by_bt(btc); + return; + case BTC_WLMROLE_STA_STA: + dm->wl_scc.null_role1 = PHL_RTYPE_STATION; + dm->wl_scc.null_role2 = PHL_RTYPE_STATION; + dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ + _action_by_bt(btc); + return; + case BTC_WLMROLE_STA_GC_NOA: + case BTC_WLMROLE_STA_GO: + case BTC_WLMROLE_STA_GO_NOA: + dm->wl_scc.null_role1 = PHL_RTYPE_STATION; + dm->wl_scc.null_role2 = PHL_RTYPE_NONE; + dur = wl_rinfo->mrole_noa_duration; + + if (wl->status.map._4way) { + dm->wl_scc.ebt_null = 0; + policy_type = BTC_CXP_OFFE_WL; + } else if (bt->link_info.status.map.connect == 0) { + dm->wl_scc.ebt_null = 0; + policy_type = BTC_CXP_OFFE_2GISOB; + } else if (bt->link_info.a2dp_desc.exist && + dur < btc->bt_req_len) { + dm->wl_scc.ebt_null = 1; /* tx null at EBT */ + policy_type = BTC_CXP_OFFE_2GBWMIXB2; + } else if (bt->link_info.a2dp_desc.exist || + bt->link_info.pan_desc.exist) { + dm->wl_scc.ebt_null = 1; /* tx null at EBT */ + policy_type = BTC_CXP_OFFE_2GBWISOB; + }else { + dm->wl_scc.ebt_null = 0; + policy_type = BTC_CXP_OFFE_2GBWISOB; + } + + break; + } + +exit: + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_ap(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + u16 policy_type = BTC_CXP_OFF_BT; + + /* Todo:if client issue Null-P, ap should follow Null/Null-P slot */ + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } else {/* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_go(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_gc(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + u8 noa = 0, pid = 0; + u16 policy_type = BTC_CXP_OFF_BT; + u32 noa_duration = 0; + + pid = _get_wl_role_idx(btc, PHL_RTYPE_P2P_GC); + + if (pid < MAX_WIFI_ROLE_NUMBER) { + noa = wl_rinfo->active_role[pid].noa; + noa_duration = wl_rinfo->active_role[pid].noa_duration; + } + /* Check GC, GC+NOA */ + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (!noa) { /* Gc without NOA */ + _action_by_bt(btc); + return; + } else { /* Gc with NOA */ + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else if (bt->link_info.a2dp_desc.exist && + noa_duration < btc->bt_req_len) + policy_type = BTC_CXP_OFFE_2GBWMIXB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } + } else {/* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +void _action_wl_2g_nan(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + u16 policy_type = BTC_CXP_OFF_BT; + + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (wl->status.map._4way) + policy_type = BTC_CXP_OFFE_WL; + else if (bt->link_info.status.map.connect == 0) + policy_type = BTC_CXP_OFFE_2GISOB; + else + policy_type = BTC_CXP_OFFE_2GBWISOB; + } else { /* dedicated-antenna */ + policy_type = BTC_CXP_OFF_EQ0; + } + + _set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + _set_policy(btc, policy_type, __func__); +} + +#endif diff --git a/phl/hal_g6/btc/halbtc_action.h b/phl/hal_g6/btc/halbtc_action.h new file mode 100644 index 0000000..88ece2d --- /dev/null +++ b/phl/hal_g6/btc/halbtc_action.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_BTC_ACTION_H__ +#define __INC_BTC_ACTION_H__ + +enum { + BTC_PHY_0 = BIT(0), + BTC_PHY_1 = BIT(1), + BTC_PHY_ALL = BIT(0) | BIT(1), +}; + +enum btc_cx_state_map { + BTC_WIDLE = 0, + BTC_WBUSY_BNOSCAN, + BTC_WBUSY_BSCAN, + BTC_WSCAN_BNOSCAN, + BTC_WSCAN_BSCAN, + BTC_WLINKING +}; + +enum btc_ant_phase { + BTC_ANT_WPOWERON = 0, + BTC_ANT_WINIT, + BTC_ANT_WONLY, + BTC_ANT_WOFF, + BTC_ANT_W2G, + BTC_ANT_W5G, + BTC_ANT_W25G, + BTC_ANT_FREERUN, + BTC_ANT_WRFK, + BTC_ANT_BRFK, + BTC_ANT_MAX +}; + +enum { + BTC_PLT_NONE = 0, + BTC_PLT_LTE_RX = BIT(0), + BTC_PLT_GNT_BT_TX = BIT(1), + BTC_PLT_GNT_BT_RX = BIT(2), + BTC_PLT_GNT_WL = BIT(3), + BTC_PLT_BT = BIT(1) | BIT(2), + BTC_PLT_ALL = 0xf +}; + +enum btc_cx_poicy_main_type { + BTC_CXP_OFF = 0, + BTC_CXP_OFFB, + BTC_CXP_OFFE, + BTC_CXP_FIX, + BTC_CXP_PFIX, + BTC_CXP_AUTO, + BTC_CXP_PAUTO, + BTC_CXP_AUTO2, + BTC_CXP_PAUTO2, + BTC_CXP_MANUAL, + BTC_CXP_USERDEF0, + BTC_CXP_MAIN_MAX +}; + +enum { + BTC_BSLOT_A2DP_HID = 60, + BTC_BSLOT_A2DP = 50, + BTC_BSLOT_INQ = 30, + BTC_BSLOT_IDLE = 20, +}; + +enum btc_cx_poicy_type { + /* TDMA off + pri: BT > WL */ + BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0, + + /* TDMA off + pri: WL > BT */ + BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1, + + /* TDMA off + pri: BT = WL */ + BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2, + + /* TDMA off + pri: BT = WL > BT_Lo */ + BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3, + + /* TDMA off + pri: WL = BT, BT_Rx > WL_Lo_Tx */ + BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4, + + /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ + BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5, + + /* TDMA off + pri: BT_Hi > WL > BT_Lo */ + BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6, + + /* TDMA off + pri: BT_Hi_Tx = WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */ + BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7, + + /* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-WL > BT_Lo */ + BTC_CXP_OFF_BWB2 = (BTC_CXP_OFF << 8) | 8, + + /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/ + BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0, + + /* TDMA off + Ext-Ctrl + pri: default */ + BTC_CXP_OFFE_2GBWISOB = (BTC_CXP_OFFE << 8) | 0, + + /* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */ + BTC_CXP_OFFE_2GISOB = (BTC_CXP_OFFE << 8) | 1, + + /* TDMA off + Ext-Ctrl + pri: E2G-slot WL > BT */ + BTC_CXP_OFFE_2GBWMIXB = (BTC_CXP_OFFE << 8) | 2, + + /* TDMA off + Ext-Ctrl + pri: E2G/EBT-slot WL > BT */ + BTC_CXP_OFFE_WL = (BTC_CXP_OFFE << 8) | 3, + + /* TDMA off + Ext-Ctrl + pri: default */ + BTC_CXP_OFFE_2GBWMIXB2 = (BTC_CXP_OFFE << 8) | 4, + + /* TDMA Fix slot-0: W1:B1 = 30:30 */ + BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0, + + /* TDMA Fix slot-1: W1:B1 = 50:50 */ + BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1, + + /* TDMA Fix slot-2: W1:B1 = 20:30 */ + BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2, + + /* TDMA Fix slot-3: W1:B1 = 40:10 */ + BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3, + + /* TDMA Fix slot-4: W1:B1 = 70:10 */ + BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4, + + /* TDMA Fix slot-5: W1:B1 = 20:60 */ + BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5, + + /* TDMA Fix slot-6: W1:B1 = 30:60 */ + BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6, + + /* TDMA Fix slot-7: W1:B1 = 20:80 */ + BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7, + + /* TDMA Fix slot-8: W1:B1 = user-define */ + BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8, + + /* TDMA Fix slot-9: W1:B1 = 40:10 */ + BTC_CXP_FIX_TD4010ISO = (BTC_CXP_FIX << 8) | 9, + + /* PS-TDMA Fix slot-0: W1:B1 = 30:30 */ + BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0, + + /* PS-TDMA Fix slot-1: W1:B1 = 50:50 */ + BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1, + + /* PS-TDMA Fix slot-2: W1:B1 = 20:30 */ + BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2, + + /* PS-TDMA Fix slot-3: W1:B1 = 20:60 */ + BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3, + + /* PS-TDMA Fix slot-4: W1:B1 = 30:70 */ + BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4, + + /* PS-TDMA Fix slot-5: W1:B1 = 20:80 */ + BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5, + + /* PS-TDMA Fix slot-6: W1:B1 = user-define */ + BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6, + + /* TDMA Auto slot-0: W1:B1 = 50:BTC_B1_MAX */ + BTC_CXP_AUTO_TD50B1 = (BTC_CXP_AUTO << 8) | 0, + + /* TDMA Auto slot-1: W1:B1 = 60:BTC_B1_MAX */ + BTC_CXP_AUTO_TD60B1 = (BTC_CXP_AUTO << 8) | 1, + + /* TDMA Auto slot-2: W1:B1 = 20:BTC_B1_MAX */ + BTC_CXP_AUTO_TD20B1 = (BTC_CXP_AUTO << 8) | 2, + + /* TDMA Auto slot-3: W1:B1 = user-define */ + BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3, + + /* PS-TDMA Auto slot-0: W1:B1 = 50:BTC_B1_MAX */ + BTC_CXP_PAUTO_TD50B1 = (BTC_CXP_PAUTO << 8) | 0, + + /* PS-TDMA Auto slot-1: W1:B1 = 60:BTC_B1_MAX */ + BTC_CXP_PAUTO_TD60B1 = (BTC_CXP_PAUTO << 8) | 1, + + /* PS-TDMA Auto slot-2: W1:B1 = 20:BTC_B1_MAX */ + BTC_CXP_PAUTO_TD20B1 = (BTC_CXP_PAUTO << 8) | 2, + + /* PS-TDMA Auto slot-3: W1:B1 = user-define */ + BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3, + + /* TDMA Auto slot2-0: W1:B4 = 30:50 */ + BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0, + + /* TDMA Auto slot2-1: W1:B4 = 30:70 */ + BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1, + + /* TDMA Auto slot2-2: W1:B4 = 50:50 */ + BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2, + + /* TDMA Auto slot2-3: W1:B4 = 60:60 */ + BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3, + + /* TDMA Auto slot2-4: W1:B4 = 20:80 */ + BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4, + + /* TDMA Auto slot2-5: W1:B4 = user-define */ + BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5, + + /* PS-TDMA Auto slot2-0: W1:B4 = 30:50 */ + BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0, + + /* PS-TDMA Auto slot2-1: W1:B4 = 30:70 */ + BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1, + + /* PS-TDMA Auto slot2-2: W1:B4 = 50:50 */ + BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2, + + /* PS-TDMA Auto slot2-3: W1:B4 = 60:60 */ + BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3, + + /* PS-TDMA Auto slot2-4: W1:B4 = 20:80 */ + BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4, + + /* PS-TDMA Auto slot2-5: W1:B4 = user-define */ + BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5, + + BTC_CXP_MAX = 0xffff +}; + +void _action_wl_25g_mcc(struct btc_t *btc); +void _action_wl_2g_ap(struct btc_t *btc); +void _action_wl_2g_go(struct btc_t *btc); +void _action_wl_2g_gc(struct btc_t *btc); +void _action_wl_2g_nan(struct btc_t *btc); +void _action_wl_2g_scc(struct btc_t *btc); +void _action_wl_2g_sta(struct btc_t *btc); +void _action_wl_scan(struct btc_t *btc); +void _action_wl_2g_mcc(struct btc_t *btc); +void _action_wl_5g(struct btc_t *btc); +void _action_wl_other(struct btc_t *btc); +void _action_wl_idle(struct btc_t *btc); +void _action_wl_nc(struct btc_t *btc); +void _action_wl_rfk(struct btc_t *btc); +void _action_wl_init(struct btc_t *btc); +void _action_wl_off(struct btc_t *btc); +void _action_freerun(struct btc_t *btc); +void _action_wl_only(struct btc_t *btc); +void _action_bt_off(struct btc_t *btc); +void _action_bt_rfk(struct btc_t *btc); +void _action_bt_whql(struct btc_t *btc); +void _action_common(struct btc_t *btc); +//extern const u32 cxtbl[]; + +void _update_btc_state_map(struct btc_t *btc); +void _set_bt_ignore_wlan_act(struct btc_t *btc, u8 enable); +void _set_wl_tx_power(struct btc_t *btc, u32 level); +void _set_wl_rx_gain(struct btc_t *btc, u32 level); +void _set_bt_tx_power(struct btc_t *btc, u32 level); +void _set_bt_rx_gain(struct btc_t *btc, u32 level); +void _set_gnt_wl(struct btc_t *btc, u8 phy_map, u8 state); +void _set_gnt_bt(struct btc_t *btc, u8 phy_map, u8 state); + +extern struct fbtc_tdma t_def[]; +extern struct fbtc_slot s_def[]; + +#endif diff --git a/phl/hal_g6/btc/halbtc_dbg_cmd.c b/phl/hal_g6/btc/halbtc_dbg_cmd.c new file mode 100644 index 0000000..91377d4 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_dbg_cmd.c @@ -0,0 +1,2043 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_BTC_DBG_CMD_C_ +#include "../hal_headers_le.h" +#include "hal_btc.h" +#include "halbtc_fw.h" +#include "halbtc_fwdef.h" +#include "halbtc_action.h" +#include "halbtc_def.h" + +#ifdef CONFIG_BTCOEX + +#define BTC_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) + + +struct halbtc_cmd_info { + char name[16]; + u8 id; +}; + +enum HALBTC_CMD_ID { + HALBTC_HELP, + HALBTC_SHOW, + HALBTC_READ_BT, + HALBTC_WRITE_BT, + HALBTC_SET_COEX, + HALBTC_UPDATE_POLICY, + HALBTC_TDMA, + HALBTC_SLOT, + HALBTC_SIG_GDBG_EN, + HALBTC_SGPIO_MAP, + HALBTC_TRACE_STEP, + HALBTC_WL_TX_POWER, + HALBTC_WL_RX_LNA, + HALBTC_BT_AFH_MAP, + HALBTC_BT_TX_POWER, + HALBTC_BT_RX_LNA, + HALBTC_BT_IGNO_WLAN, + HALBTC_SET_GNT_WL, + HALBTC_SET_GNT_BT, + HALBTC_SET_BT_PSD, + HALBTC_GET_WL_NHM_DBM, + HALBTC_DBG +}; + +struct halbtc_cmd_info halbtc_cmd_i[] = { + {"-h", HALBTC_HELP}, + {"show", HALBTC_SHOW}, + {"rb", HALBTC_READ_BT}, + {"wb", HALBTC_WRITE_BT}, + {"mode", HALBTC_SET_COEX}, + {"update", HALBTC_UPDATE_POLICY}, + {"tdma", HALBTC_TDMA}, + {"slot", HALBTC_SLOT}, + {"sig", HALBTC_SIG_GDBG_EN}, + {"gpio", HALBTC_SGPIO_MAP}, + {"wpwr", HALBTC_WL_TX_POWER}, + {"wlna", HALBTC_WL_RX_LNA}, + {"afh", HALBTC_BT_AFH_MAP}, + {"bpwr", HALBTC_BT_TX_POWER}, + {"blna", HALBTC_BT_RX_LNA}, + {"igwl", HALBTC_BT_IGNO_WLAN}, + {"gwl", HALBTC_SET_GNT_WL}, + {"gbt", HALBTC_SET_GNT_BT}, + {"bpsd", HALBTC_SET_BT_PSD}, + {"wnhm", HALBTC_GET_WL_NHM_DBM}, + {"dbg", HALBTC_DBG} +}; + +static void _cmd_rb(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 i = 0, type = 0, addr = 0; + + if (input_num < 3) + goto help; + + _os_sscanf(input[1], "%d", &type); + _os_sscanf(input[2], "%x", &addr); + + if (type > 4) + goto help; + + btc->dbg.rb_done = false; + btc->dbg.rb_val = 0xffffffff; + _read_bt_reg(btc, (u8)(type), (u16)addr); + for (i = 0; i < 50; i++) { + if (!btc->dbg.rb_done) + hal_mdelay(btc->hal, 10); + else + goto exit; + } + +exit: + if (!btc->dbg.rb_done) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " timeout !! \n"); + } else { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " rb %d(0x%x), val = 0x%x !! \n", type, addr, btc->dbg.rb_val); + } + return; + +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " rb \n"); + return; +} + +static void _show_cx_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_dm *dm = &btc->dm; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_wl_info *wl = &btc->cx.wl; + struct rtw_hal_com_t *h = btc->hal; + u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0; + + if (!(dm->coex_info_map & BTC_COEX_INFO_CX)) + return; + + dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r========== [BTC COEX INFO (%s)] ==========", + id_to_str(BTC_STR_CHIPID, (u32)btc->chip->chip_id)); + + ver_main = (coex_ver & bMASKB3) >> 24; + ver_sub = (coex_ver & bMASKB2) >> 16; + ver_hotfix = (coex_ver & bMASKB1) >> 8; + id_branch = coex_ver & bMASKB0; + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : Coex:%d.%d.%d(branch:%d), ", + "[coex_version]", ver_main, ver_sub, ver_hotfix, id_branch); + + ver_main = (wl->ver_info.fw_coex & bMASKB3) >> 24; + ver_sub = (wl->ver_info.fw_coex & bMASKB2) >> 16; + ver_hotfix = (wl->ver_info.fw_coex & bMASKB1) >> 8; + id_branch = wl->ver_info.fw_coex & bMASKB0; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "WL_FW_coex:%d.%d.%d(branch:%d)", + ver_main, ver_sub, ver_hotfix, id_branch); + + ver_main = (btc->chip->wlcx_desired & bMASKB3) >> 24; + ver_sub = (btc->chip->wlcx_desired & bMASKB2) >> 16; + ver_hotfix = (btc->chip->wlcx_desired & bMASKB1) >> 8; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "(%s, desired:%d.%d.%d), ", + (wl->ver_info.fw_coex >= btc->chip->wlcx_desired ? + "Match" : "Mis-Match"), + ver_main, ver_sub, ver_hotfix); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "BT_FW_coex:%d(%s, desired:%d)", + bt->ver_info.fw_coex, + (bt->ver_info.fw_coex >= btc->chip->btcx_desired ? + "Match" : "Mis-Match"), + btc->chip->btcx_desired); + + if (bt->enable.now && bt->ver_info.fw == 0) + hal_btc_fw_en_rpt(btc, RPT_EN_BT_VER_INFO, 1); + else + hal_btc_fw_en_rpt(btc, RPT_EN_BT_VER_INFO, 0); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : WL_FW:%d.%d.%d.%d, BT_FW:0x%x(%s)", + "[sub_module]", (wl->ver_info.fw & bMASKB3) >> 24, + (wl->ver_info.fw & bMASKB2) >> 16, + (wl->ver_info.fw & bMASKB1) >> 8, + (wl->ver_info.fw & bMASKB0), bt->ver_info.fw, + (bt->run_patch_code ? "patch" : "ROM")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : kt_ver:%x, rfe_type:0x%x, hw_id:0x%x, ant_iso:%d, ant_pg:%d, %s", + "[hw_info]", btc->mdinfo.kt_ver, btc->mdinfo.rfe_type, + ((btc->phl->id.id & 0xff00) >> 8), + btc->mdinfo.ant.isolation, btc->mdinfo.ant.num, + (btc->mdinfo.ant.num > 1? "" : (btc->mdinfo.ant.single_pos? + "1Ant_Pos:S1, " : "1Ant_Pos:S0, "))); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d", + btc->cx.other.type, h->dbcc_en, h->rfpath_tx_num, + h->rfpath_rx_num); +} + +static void _show_wl_role_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_wl_link_info *plink = NULL; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; + struct btc_traffic t; + u8 i; + + if (btc->hal->dbcc_en) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : PHY0_band(op:%d/scan:%d/real:%d), ", + "[dbcc_info]", wl_dinfo->op_band[HW_PHY_0], + wl_dinfo->scan_band[HW_PHY_0], + wl_dinfo->real_band[HW_PHY_0]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "PHY1_band(op:%d/scan:%d/real:%d)", + wl_dinfo->op_band[HW_PHY_1], + wl_dinfo->scan_band[HW_PHY_1], + wl_dinfo->real_band[HW_PHY_1]); + } + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + plink = &btc->cx.wl.link_info[i]; + + if (!plink->active) + continue; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r [port_%d] : role=%s(phy-%d), connect=%s(client_cnt=%d), mode=%s, ch=(ct:%d/pr:%d), bw=%s", + plink->pid, + id_to_str(BTC_STR_ROLE, (u32)plink->role), + plink->phy, + id_to_str(BTC_STR_MSTATE, (u32)plink->connected), + plink->client_cnt-1, + id_to_str(BTC_STR_WLMODE, (u32)plink->mode), + plink->chdef.center_ch, plink->chdef.chan, + id_to_str(BTC_STR_WLBW, (u32)plink->chdef.bw)); + + if (plink->connected == MLME_NO_LINK) + continue; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", mac_id=%d, noa(%d)=%d.%03dms", + plink->mac_id, plink->noa, + plink->noa_duration/1000, plink->noa_duration%1000); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r [port_%d] : rssi=-%ddBm(%d), busy=%d, dir=%s, ", + plink->pid, 110-plink->stat.rssi, + plink->stat.rssi, plink->busy, + (plink->dir == TRAFFIC_UL ? "UL" : "DL")); + + t = plink->stat.traffic; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "tx[rate:%s/busy_level:%d/sts:0x%x], ", + id_to_str(BTC_STR_RATE, (u32)t.tx_rate), + t.tx_lvl, t.tx_sts); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "rx[rate:%s/busy_level:%d/sts:0x%x/drop:%d]", + id_to_str(BTC_STR_RATE, (u32)t.rx_rate), + t.rx_lvl, t.rx_sts, plink->rx_rate_drop_cnt); + } +} + +static void _show_wl_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &cx->wl; + struct btc_wl_role_info *wl_rinfo = &wl->role_info; + + if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL)) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r========== [WL Status] =========="); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : link_mode:%s, mrole:%s, ", + "[status]", + id_to_str(BTC_STR_WLLINK, (u32)wl_rinfo->link_mode), + id_to_str(BTC_STR_MROLE, wl_rinfo->mrole_type)); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "rf_off:%s, power_save:%d, init_ok:%s, nhm:%d(status=%d, ratio:%d)", + (wl->status.map.rf_off? "Y" : "N"), + wl->status.map.lps, + (wl->status.map.init_ok? "Y" : "N"), + wl->nhm.pwr, + wl->nhm.current_status, wl->nhm.ratio); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : scan:%s(band:%d/phy_map:0x%x), connecting:%s, roam:%s, 4way:%s", + "[scan]", (wl->status.map.scan? "Y" : "N"), + wl->scan_info.band[HW_PHY_0], wl->scan_info.phy_map, + (wl->status.map.connecting? "Y" : "N"), + (wl->status.map.roaming? "Y" : "N"), + (wl->status.map._4way? "Y" : "N")); + + _show_wl_role_info(btc, used, input, input_num, output, out_len); +} + +static void _show_dm_step(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_dm *dm = &btc->dm; + u32 n_begin = 0, n_end = 0, i = 0, cnt = 0; + u32 step_cnt = dm->dm_step.cnt; + + if (step_cnt == 0) + return; + + if (step_cnt <= BTC_DM_MAXSTEP) + n_begin = 1; + else + n_begin = step_cnt - BTC_DM_MAXSTEP + 1; + + n_end = step_cnt; + + if (n_begin > n_end) + return; + + for (i = n_begin; i <= n_end; i++) { + if (cnt % 6 == 0) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : ", "[dm_steps]"); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "-> %s", dm->dm_step.step[(i-1) % BTC_DM_MAXSTEP]); + cnt++; + } +} + +static void _show_bt_profile_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; + struct btc_bt_hfp_desc hfp = bt_linfo->hfp_desc; + struct btc_bt_hid_desc hid = bt_linfo->hid_desc; + struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; + struct btc_bt_pan_desc pan = bt_linfo->pan_desc; + + if (hfp.exist) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : type:%s, sut_pwr:%d, golden-rx:%d", + "[HFP]", + (hfp.type == 0? "SCO" : "eSCO"), + bt_linfo->sut_pwr_level[0], + bt_linfo->golden_rx_shift[0]); + } + + if (hid.exist) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : type:%s%s%s%s%s pair-cnt:%d, sut_pwr:%d, golden-rx:%d", + "[HID]", + (hid.type & BTC_HID_218? "2/18," : ""), + (hid.type & BTC_HID_418? "4/18," : ""), + (hid.type & BTC_HID_BLE? "BLE," : ""), + (hid.type & BTC_HID_RCU? "RCU," : ""), + (hid.type & BTC_HID_RCU_VOICE? "RCU-Voice," : ""), + hid.pair_cnt, bt_linfo->sut_pwr_level[1], + bt_linfo->golden_rx_shift[1]); + } + + if (a2dp.exist) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : type:%s, bit-pool:%d, flush-time:%d, ", + "[A2DP]", + (a2dp.type == BTC_A2DP_LEGACY ? "Legacy" : "TWS"), + a2dp.bitpool, a2dp.flush_time); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "vid:0x%x, Dev-name:0x%x, sut_pwr:%d, golden-rx:%d", + a2dp.vendor_id, a2dp.device_name, + bt_linfo->sut_pwr_level[2], + bt_linfo->golden_rx_shift[2]); + } + + if (pan.exist) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : sut_pwr:%d, golden-rx:%d", + "[PAN]", + bt_linfo->sut_pwr_level[3], + bt_linfo->golden_rx_shift[3]); + } +} + +static void _show_bt_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_cx *cx = &btc->cx; + struct btc_bt_info *bt = &cx->bt; + struct btc_wl_info *wl = &cx->wl; + struct btc_module *module = &btc->mdinfo; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + u8 *afh = bt_linfo->afh_map; + u16 polt_cnt = 0; + + if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "%s", "\n\r========== [BT Status] =========="); + + /*bt->btg_type = (bt->ver_info.fw & BIT(28) ? BTC_BT_BTG: BTC_BT_ALONE);*/ + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : enable:%s, btg:%s%s, connect:%s, ", + "[status]", (bt->enable.now? "Y" : "N"), + (bt->btg_type? "Y" : "N"), + (bt->enable.now && (bt->btg_type != module->bt_pos)? + "(efuse-mismatch!!)" : ""), + (bt_linfo->status.map.connect? "Y" : "N")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "igno_wl:%s, mailbox_avl:%s, rfk_state:0x%x", + (bt->igno_wl? "Y" : "N"), + (bt->mbx_avl? "Y" : "N"), bt->rfk_info.val); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : profile:%s%s%s%s%s ", + "[profile]", + ((bt_linfo->profile_cnt.now == 0) ? "None," : ""), + (bt_linfo->hfp_desc.exist? "HFP," : ""), + (bt_linfo->hid_desc.exist? "HID," : ""), + (bt_linfo->a2dp_desc.exist? + (bt_linfo->a2dp_desc.sink ? "A2DP_sink," :"A2DP,") : ""), + (bt_linfo->pan_desc.exist? "PAN," : "")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "multi-link:%s, role:%s, ble-connect:%s, CQDDR:%s, A2DP_active:%s, PAN_active:%s", + (bt_linfo->multi_link.now? "Y" : "N"), + (bt_linfo->slave_role ? "Slave" : "Master"), + (bt_linfo->status.map.ble_connect? "Y" : "N"), + (bt_linfo->cqddr? "Y" : "N"), + (bt_linfo->a2dp_desc.active? "Y" : "N"), + (bt_linfo->pan_desc.active? "Y" : "N")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : rssi:%ddBm, tx_rate:%dM, %s%s%s%s", + "[link]", bt_linfo->rssi-100, + (bt_linfo->tx_3M? 3 : 2), + (bt->pag? " paging!!" : ""), + (bt->inq? " inquirying!!" : ""), + (bt_linfo->status.map.acl_busy? " acl_busy!!" : ""), + (bt_linfo->status.map.mesh_busy? " mesh_busy!!" : "")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "%s afh_map[%02x%02x_%02x%02x_%02x%02x_%02x%02x_%02x%02x], ", + (bt_linfo->relink.now? " ReLink!!" : ""), + afh[0], afh[1], afh[2], afh[3], afh[4], + afh[5], afh[6], afh[7], afh[8], afh[9]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "wl_ch_map[en:%d/ch:%d/bw:%d]", + wl->afh_info.en, wl->afh_info.ch, wl->afh_info.bw); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : retry:%d, relink:%d, rate_chg:%d, reinit:%d, reenable:%d, ", + "[stat_cnt]", cx->cnt_bt[BTC_BCNT_RETRY], + cx->cnt_bt[BTC_BCNT_RELINK], + cx->cnt_bt[BTC_BCNT_RATECHG], + cx->cnt_bt[BTC_BCNT_REINIT], + cx->cnt_bt[BTC_BCNT_REENABLE]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "role-switch:%d, afh:%d, inq_page:%d(inq:%d/page:%d), igno_wl:%d", + cx->cnt_bt[BTC_BCNT_ROLESW], + cx->cnt_bt[BTC_BCNT_AFH], + cx->cnt_bt[BTC_BCNT_INQPAG], + cx->cnt_bt[BTC_BCNT_INQ], + cx->cnt_bt[BTC_BCNT_PAGE], + cx->cnt_bt[BTC_BCNT_IGNOWL]); + + _show_bt_profile_info(btc, used, input, input_num, output, out_len); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)", + "[bt_info]", + bt->raw_info[2], bt->raw_info[3], + bt->raw_info[4], bt->raw_info[5], + bt->raw_info[6], bt->raw_info[7], + (bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply"), + cx->cnt_bt[BTC_BCNT_INFOUPDATE], + cx->cnt_bt[BTC_BCNT_INFOSAME]); + + /* To avoid I/O if WL LPS or power-off */ + if (wl->status.map.lps == 1 || wl->status.map.rf_off) + return; + + btc->chip->ops->update_bt_cnt(btc); + _chk_btc_err(btc, BTC_DCNT_BTCNT_FREEZE, 0); + rtw_hal_mac_get_bt_polt_cnt(btc->hal, HW_PHY_0, &polt_cnt); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)", + "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], + cx->cnt_bt[BTC_BCNT_HIPRI_TX], + cx->cnt_bt[BTC_BCNT_LOPRI_RX], + cx->cnt_bt[BTC_BCNT_LOPRI_TX], + polt_cnt); +} + +static void _show_fbtc_tdma(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_tdma *t = NULL; + + pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; + if (!pcinfo->valid) + return; + + t = &pfwinfo->rpt_fbtc_tdma.finfo.tdma; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : ", "[tdma_policy]"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "type:%s, rx_flow_ctrl:%d, tx_flow_ctrl:%d, ", + id_to_str(BTC_STR_TDMA, (u32)t->type), + t->rxflctrl, t->txflctrl); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "wl_toggle_n:%d, leak_n:%d, ext_ctrl:%d, null_role:0x%x, ", + t->wtgle_n, t->leak_n, t->ext_ctrl, t->rxflctrl_role); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "policy_type:%s", + id_to_str(BTC_STR_POLICY, (u32)btc->policy_type)); +} + +static void _show_dm_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_module *module = &btc->mdinfo; + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + + if (!(dm->coex_info_map & BTC_COEX_INFO_DM)) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r========== [Mechanism Status %s] ==========", + (btc->ctrl.manual? "(Manual)":"(Auto)")); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : type:%s, reason:%s(), action:%s(), ant_path:%s, run_cnt:%d", + "[status]", + (module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated"), + dm->run_reason, dm->run_action, + id_to_str(BTC_STR_ANTPATH, dm->set_ant_path & 0xff), + dm->cnt_dm[BTC_DCNT_RUN]); + + _show_fbtc_tdma(btc, used, input, input_num, output, out_len); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, ", + "[dm_flag]", dm->wl_only, dm->bt_only, btc->ctrl.igno_bt, + dm->freerun, btc->hal->btc_ctrl.lps); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "leak_ap:%d, fw_offload:%s%s, error_map:0x%x", dm->leak_ap, + (BTC_CX_FW_OFFLOAD? "Y" : "N"), + (dm->error.map.offload_mismatch? + "(Mis-Match!!)" : ""), dm->error.val); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : wl_tx_limit[en:%d/max_t:%dus/max_retry:%d], bt_slot_req:%d-TU, bt_scan_rx_low_pri:%d", + "[dm_drv_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time, + dm->wl_tx_limit.tx_retry, btc->bt_req_len, bt->scan_rx_low_pri); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : wl[rssi_lvl:%d/para_lvl:%d/tx_pwr:%d/rx_lvl:%d/_btg_rx:%d/stb_chg:%d] ", + "[dm_rf_ctrl]", wl->rssi_level, dm->trx_para_level, + dm->rf_trx_para.wl_tx_power, dm->rf_trx_para.wl_rx_gain, + dm->wl_btg_rx, dm->wl_stb_chg); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "bt[tx_pwr_dec:%d/rx_lna:%d(%s-tbl)]", + dm->rf_trx_para.bt_tx_power, dm->rf_trx_para.bt_rx_gain, + (bt->hi_lna_rx? "Hi" : "Ori")); + + _show_dm_step(btc, used, input, input_num, output, out_len); +} + +static void _show_mreg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_mreg_val *pmreg = NULL; + struct fbtc_gpio_dbg *gdbg = NULL; + struct rtw_hal_com_t *h = btc->hal; + struct btc_cx *cx = &btc->cx; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_gnt_ctrl gnt[2] = {0}; + u8 i = 0, type = 0, cnt = 0; + u32 val, offset; + + if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG)) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r========== [HW Status] =========="); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)", + "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], + bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], + cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); + + /* To avoid I/O if WL LPS or power-off */ + if (wl->status.map.lps != 1 && !wl->status.map.rf_off) { + rtw_hal_mac_get_grant(h, (u8*)gnt); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : pta_owner:%s, pta_req_mac:MAC%d, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d/polut_type:%s]", + "[gnt_status]", + (_read_cx_ctrl(btc) == BTC_CTRL_BY_WL? "WL" : "BT"), + wl->pta_req_mac, + (gnt[0].gnt_wl_sw_en? "SW" : "HW"), gnt[0].gnt_wl, + (gnt[0].gnt_bt_sw_en? "SW" : "HW"), gnt[0].gnt_bt, + id_to_str(BTC_STR_POLUT, wl->bt_polut_type[HW_PHY_0])); + + if (h->dbcc_en) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " ,phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d/polut_type:%s]", + (gnt[1].gnt_wl_sw_en? "SW" : "HW"), + gnt[1].gnt_wl, + (gnt[1].gnt_bt_sw_en? "SW" : "HW"), + gnt[1].gnt_bt, + id_to_str(BTC_STR_POLUT, + wl->bt_polut_type[HW_PHY_1])); + } + + pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; + if (!pcinfo->valid) + return; + + pmreg = &pfwinfo->rpt_fbtc_mregval.finfo; + + for (i = 0; i < pmreg->reg_num; i++) { + type = (u8)btc->chip->mon_reg[i].type; + offset = btc->chip->mon_reg[i].offset; + val = pmreg->mreg_val[i]; + + if (cnt % 6 == 0) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : %s_0x%x=0x%x", + "[reg]", + id_to_str(BTC_STR_REG, (u32)type), + offset, val); + else + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", %s_0x%x=0x%x", + id_to_str(BTC_STR_REG, (u32)type), + offset, val); + cnt++; + } + + pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; + if (!pcinfo->valid) + return; + + gdbg = &pfwinfo->rpt_fbtc_gpio_dbg.finfo; + if (!gdbg->en_map) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : enable_map:0x%08x", + "[gpio_dbg]", gdbg->en_map); + + for (i = 0; i < BTC_DBG_MAX1; i++) { + if (!(gdbg->en_map & BIT(i))) + continue; + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", %s->GPIO%d", + id_to_str(BTC_STR_GDBG, (u32)i), + gdbg->gpio_map[i]); + } +} + +static void _show_summary(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_rpt_ctrl *prptctrl = NULL; + struct btc_cx *cx = &btc->cx; + struct btc_dm *dm = &btc->dm; + struct btc_wl_info *wl = &cx->wl; + u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; + u8 i; + + if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "%s", "\n\r========== [Statistics] =========="); + + pcinfo = &pfwinfo->rpt_ctrl.cinfo; + if (pcinfo->valid && wl->status.map.lps != 1 && !wl->status.map.rf_off) { + prptctrl = &pfwinfo->rpt_ctrl.finfo; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d, len:%d, max:%d), ", + "[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, + prptctrl->rpt_info.cnt_h2c, pfwinfo->cnt_c2h, + prptctrl->rpt_info.cnt_c2h, prptctrl->rpt_info.len_c2h, + RTW_PHL_BTC_FWINFO_BUF); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x", + pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_info.cnt, + prptctrl->rpt_info.en); + + _chk_btc_err(btc, BTC_DCNT_RPT_FREEZE, + pfwinfo->event[BTF_EVNT_RPT]); + + if (dm->error.map.wl_fw_hang) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, " (WL FW Hang!!)"); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : send_ok:%d, send_fail:%d, recv:%d, ", + "[mailbox]", prptctrl->bt_mbx_info.cnt_send_ok, + prptctrl->bt_mbx_info.cnt_send_fail, + prptctrl->bt_mbx_info.cnt_recv); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "A2DP_empty:%d(stop:%d/tx:%d/ack:%d/nack:%d)", + prptctrl->bt_mbx_info.a2dp.cnt_empty, + prptctrl->bt_mbx_info.a2dp.cnt_flowctrl, + prptctrl->bt_mbx_info.a2dp.cnt_tx, + prptctrl->bt_mbx_info.a2dp.cnt_ack, + prptctrl->bt_mbx_info.a2dp.cnt_nack); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]", + "[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ], + cx->cnt_wl[BTC_WCNT_RFK_GO], + cx->cnt_wl[BTC_WCNT_RFK_REJECT], + cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]", + prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REQ], + prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_GO], + prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REJECT], + prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT], + prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_FAIL]); + } else { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d", + "[summary]", pfwinfo->cnt_h2c, + pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " WL FW rpt error!!(valid=%d, lps=%d, rf_off=%d)", + pcinfo->valid, wl->status.map.lps, + wl->status.map.rf_off); + } + + for (i = 0; i < BTC_NCNT_MAX; i++) + cnt_sum += dm->cnt_notify[i]; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", + "[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], + cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d", + cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], + cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], + cnt[BTC_NCNT_WL_STA]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", + "[notify_cnt]", cnt[BTC_NCNT_SCAN_START], + cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND], + cnt[BTC_NCNT_SPECIAL_PACKET]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "timer=%d, control=%d, customerize=%d, hub_msg=%d", + cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], + cnt[BTC_NCNT_CUSTOMERIZE], btc->hubmsg_cnt); +} + +static void _show_error(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct fbtc_cysta *pcysta = NULL; + + pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; + + if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW] == 0 && + pcysta->except_cnt == 0 && + !pfwinfo->len_mismch && !pfwinfo->fver_mismch) + return; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : ", "[error]"); + + if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "overflow-cnt: %d, ", + pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]); + } + + if (pfwinfo->len_mismch) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "len-mismatch: 0x%x, ", + pfwinfo->len_mismch); + } + + if (pfwinfo->fver_mismch) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "fver-mismatch: 0x%x, ", + pfwinfo->fver_mismch); + } + + /* cycle statistics exceptions */ + if (pcysta->except_map || pcysta->except_cnt) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "exception-type: 0x%x, exception-cnt = %d", + pcysta->except_map, pcysta->except_cnt); + } +} + +static void _show_fbtc_slots(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_dm *dm = &btc->dm; + struct fbtc_slot s; + u8 i = 0; + + for (i = 0; i < CXST_MAX; i++) { + s = dm->slot_now[i]; + if (i % 5 == 0) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : %s[%d/0x%x/%d]", + "[slot_list]", + id_to_str(BTC_STR_SLOT, (u32)i), + s.dur, s.cxtbl, s.cxtype); + else + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", %s[%d/0x%x/%d]", + id_to_str(BTC_STR_SLOT, (u32)i), + s.dur, s.cxtbl, s.cxtype); + } +} + +static void _show_fbtc_cysta(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_dm *dm = &btc->dm; + struct btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_cysta *pcysta = NULL; + u8 i, cnt = 0, slot_pair, divide_cnt = 12; + u16 cycle, c_begin, c_end, s_id; + + pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; + if (!pcinfo->valid) + return; + + pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", + "[slot_cnt]", pcysta->bcn_cnt[CXBCN_ALL], + pcysta->bcn_cnt[CXBCN_ALL_OK], pcysta->bcn_cnt[CXBCN_BT_SLOT], + pcysta->bcn_cnt[CXBCN_BT_OK]); + + for (i = 0; i < CXST_MAX; i++) { + if (!pcysta->slot_cnt[i]) + continue; + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", %s:%d", + id_to_str(BTC_STR_SLOT, (u32)i), + pcysta->slot_cnt[i]); + } + + if (dm->tdma_now.rxflctrl) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", leak_rx:%d", pcysta->leak_slot.cnt_rximr); + } + + if (pcysta->collision_cnt) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", collision:%d", pcysta->collision_cnt); + } + + if (pcysta->skip_cnt) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", skip:%d", pcysta->skip_cnt); + } + + _chk_btc_err(btc, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); + _chk_btc_err(btc, BTC_DCNT_B1_FREEZE, pcysta->slot_cnt[CXST_B1]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : cycle:%d, avg_t[wl:%d/bt:%d/lk:%d.%03d]", + "[cycle_time]", + pcysta->cycles, + pcysta->cycle_time.tavg[CXT_WL], + pcysta->cycle_time.tavg[CXT_BT], + pcysta->leak_slot.tavg/1000, pcysta->leak_slot.tavg%1000); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", max_t[wl:%d/bt:%d/lk:%d.%03d]", + pcysta->cycle_time.tmax[CXT_WL], + pcysta->cycle_time.tmax[CXT_BT], + pcysta->leak_slot.tamx/1000, pcysta->leak_slot.tamx%1000); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", maxdiff_t[wl:%d/bt:%d]", + pcysta->cycle_time.tmaxdiff[CXT_WL], + pcysta->cycle_time.tmaxdiff[CXT_BT]); + + _chk_btc_err(btc, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles); + + if (a2dp->exist) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : a2dp_ept:%d, a2dp_late:%d", + "[a2dp_t_sta]", + pcysta->a2dp_ept.cnt, pcysta->a2dp_ept.cnt_timeout); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + ", avg_t:%d, max_t:%d", + pcysta->a2dp_ept.tavg, pcysta->a2dp_ept.tmax); + } + + if (pcysta->cycles <= 1) + return; + + /* 1 cycle = 1 wl-slot + 1 bt-slot */ + slot_pair = BTC_CYCLE_SLOT_MAX/2; + + if (pcysta->cycles <= slot_pair) + c_begin = 1; + else + c_begin = pcysta->cycles - slot_pair + 1; + + c_end = pcysta->cycles; + + if (a2dp->exist) + divide_cnt = 3; + else + divide_cnt = 12; + + if (c_begin > c_end) + return; + + for (cycle = c_begin; cycle <= c_end; cycle++) { + cnt++; + s_id = ((cycle-1) % slot_pair)*2; + + if (cnt % divide_cnt == 1) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "\n\r %-15s : ", "[cycleT_ermtan]"); + + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "->b%d", pcysta->slot_step_time[s_id]); +#if 1 + if (a2dp->exist) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "(%d/%d/%dM/%d/%d/%d)", + pcysta->a2dp_trx[s_id].empty_cnt, + pcysta->a2dp_trx[s_id].retry_cnt, + (pcysta->a2dp_trx[s_id].tx_rate ? 3:2), + pcysta->a2dp_trx[s_id].tx_cnt, + pcysta->a2dp_trx[s_id].ack_cnt, + pcysta->a2dp_trx[s_id].nack_cnt); +#endif + + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "->w%d", pcysta->slot_step_time[s_id+1]); +#if 1 + if (a2dp->exist) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "(%d/%d/%dM/%d/%d/%d)", + pcysta->a2dp_trx[s_id+1].empty_cnt, + pcysta->a2dp_trx[s_id+1].retry_cnt, + (pcysta->a2dp_trx[s_id+1].tx_rate ? 3:2), + pcysta->a2dp_trx[s_id+1].tx_cnt, + pcysta->a2dp_trx[s_id+1].ack_cnt, + pcysta->a2dp_trx[s_id+1].nack_cnt); +#endif + } +} + +static void _show_fbtc_nullsta(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_cynullsta *ns = NULL; + u8 i = 0; + + if (!btc->dm.tdma_now.rxflctrl) + return; + + pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; + if (!pcinfo->valid) + return; + + ns = &pfwinfo->rpt_fbtc_nullsta.finfo; + + for (i = CXNULL_STATE_0; i <= CXNULL_STATE_1; i++) { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : ", "[null_status]"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "null-%d", i); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "[Tx:%d/", ns->result[i][CXNULL_TX]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "ok:%d/", ns->result[i][CXNULL_OK]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "late:%d/", ns->result[i][CXNULL_LATE]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "fail:%d/", ns->result[i][CXNULL_FAIL]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "retry:%d/", ns->result[i][CXNULL_RETRY]); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "avg_t:%d.%03d/", + ns->tavg[i]/1000, ns->tavg[i]%1000); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "max_t:%d.%03d]", + ns->tmax[i]/1000, ns->tmax[i]%1000); + } +} + +static void _show_fbtc_step(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct fbtc_steps *pstep = NULL; + u8 type, val; + u16 diff_t; + u32 i, cnt = 0, n_begin = 0, n_end = 0, array_idx = 0; + + PHL_INFO("[BTC], %s(), rpt_en_map=0x%x\n", __func__, pfwinfo->rpt_en_map); + + if ((pfwinfo->rpt_en_map & RPT_EN_FW_STEP_INFO) == 0) + return; + + pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; + if (!pcinfo->valid) + return; + + pstep = &pfwinfo->rpt_fbtc_step.finfo; + + if (pcinfo->req_fver != pstep->fver || !pstep->cnt) + return; + + if (pstep->cnt <= FCXDEF_STEP) + n_begin = 1; + else + n_begin = pstep->cnt - FCXDEF_STEP + 1; + + n_end = pstep->cnt; + + if (n_begin > n_end) + return; + + /* restore step info by using ring instead of FIFO */ + for (i = n_begin; i <= n_end; i++) { + array_idx = (i - 1) % FCXDEF_STEP; + type = pstep->step[array_idx].type; + val = pstep->step[array_idx].val; + diff_t = pstep->step[array_idx].difft; + + if (type == CXSTEP_NONE || type >= CXSTEP_MAX) + continue; + + if (cnt % 10 == 0) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "\n\r %-15s : ", "[fw_steps]"); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "-> %s(%d)", (type == CXSTEP_SLOT? + id_to_str(BTC_STR_SLOT, (u32)val) : + id_to_str(BTC_STR_EVENT, (u32)val)), + diff_t); + cnt++; + } +} + +static void _show_fw_dm_msg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM)) + return; + + _show_error(btc, used, input, input_num, output, out_len); + _show_fbtc_slots(btc, used, input, input_num, output, out_len); + _show_fbtc_cysta(btc, used, input, input_num, output, out_len); + _show_fbtc_nullsta(btc, used, input, input_num, output, out_len); + _show_fbtc_step(btc, used, input, input_num, output, out_len); +} + +static void _cmd_show(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 show_map = 0xff; + + if (input_num > 1) + _os_sscanf(input[1], "%x", &show_map); + + btc->dm.coex_info_map = show_map & 0xff; + + _show_cx_info(btc, used, input, input_num, output, out_len); + _show_wl_info(btc, used, input, input_num, output, out_len); + _show_bt_info(btc, used, input, input_num, output, out_len); + _show_dm_info(btc, used, input, input_num, output, out_len); + _show_fw_dm_msg(btc, used, input, input_num, output, out_len); + _show_mreg(btc, used, input, input_num, output, out_len); + _show_summary(btc, used, input, input_num, output, out_len); +} + +static void _cmd_dbg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct btc_ops *ops = btc->ops; + u8 buf[8] = {0}; + u32 len, n; + u32 val = 0, type = 0, i; + + if ((input_num < 3) || (input_num > 10)) + goto help; + + len = input_num - 1; + _os_sscanf(input[1], "%d", &type); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " test type=%d", type); + + buf[0] = (u8)(type & 0xff); + + for (n = 2; n <= len; n++) { + _os_sscanf(input[n], "%x", &val); + buf[n-1] = (u8)(val & 0xff); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " para%d=0x%x", n-1, buf[n-1]); + } + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, " \n"); + + switch (type) { + case 0: /* H2C-C2H loopback */ + ops->fw_cmd(btc, BTFC_SET, SET_H2C_TEST, buf, (u16)len); + btc->dbg.rb_done = false; + btc->dbg.rb_val = 0xff; + for (i = 0; i < 50; i++) { + if (!btc->dbg.rb_done) { + hal_mdelay(btc->hal, 10); + } else { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + " H2C-C2H loopback data = 0x%x !!\n", + btc->dbg.rb_val); + return; + } + } + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " timeout !!\n"); + break; + case 1: /* H2C-mailbox */ + ops->fw_cmd(btc, BTFC_SET, SET_H2C_TEST, buf, (u16)len); + break; + case 2: /* bt slot request */ + btc->bt_req_len = (u32)buf[1]; + hal_btc_send_event(btc, (u8*)&btc->bt_req_len, 4, + BTC_HMSG_SET_BT_REQ_SLOT); + break; + case 3: /* fw_step debug */ + if (buf[1] > 0) + hal_btc_fw_en_rpt(btc, RPT_EN_FW_STEP_INFO, 1); + else + hal_btc_fw_en_rpt(btc, RPT_EN_FW_STEP_INFO, 0); + break; + } + + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " dbg ... \n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " dbg = 0: H2C-C2H loopback \n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " dbg = 1: H2C-mailbox \n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " dbg = 2: slot request for P2P+BT coex \n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " dbg = 3: enable fw_step debug \n"); + return; +} + +static void _cmd_wb(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 type = 0, addr = 0, val = 0; + + if (input_num < 4) + goto help; + + _os_sscanf(input[1], "%d", &type); + _os_sscanf(input[2], "%x", &addr); + _os_sscanf(input[3], "%x", &val); + + if (type > 4) + goto help; + + _write_bt_reg(btc, (u8)type, (u16)addr, val); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " wb type=%d, addr=0x%x, val=0x%x !! \n", type, addr, val); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " wb \n"); + return; +} + +static void _cmd_set_coex(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 mode = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &mode); + + switch(mode) { + case 0: /* original */ + btc->ctrl.manual = 0; + btc->ctrl.always_freerun = 0; + btc->dm.wl_only = 0; + btc->dm.bt_only = 0; + _set_init_info(btc); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL); + _run_coex(btc, __func__); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " recovery original coex mechanism !! \n"); + break; + case 1: /* freeze */ + btc->ctrl.manual = 1; + hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL); + _run_coex(btc, __func__); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " freeze coex mechanism !! \n"); + break; + case 2: /* fix freerun */ + btc->ctrl.always_freerun = 1; + hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL); + _run_coex(btc, __func__); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " freerun coex mechanism !! \n"); + break; + case 3: /* fix wl only */ + btc->dm.wl_only = 1; + _set_init_info(btc); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT); + _run_coex(btc, __func__); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " always WL-only coex mechanism!! \n"); + break; + case 4: /* fix bt only */ + btc->dm.bt_only = 1; + _set_init_info(btc); + hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT); + _run_coex(btc, __func__); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " always BT-only coex mechanism!! \n"); + break; + } + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " mode \n"); + return; +} + +static void _cmd_update_policy(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + hal_btc_fw_set_policy(btc, FC_EXEC, (u16)BTC_CXP_MANUAL<<8, __func__); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " Update tdma/slot policy !! \n"); +} + +static void _cmd_tdma(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 para1 = 0, para2 = 0; + u8 buf[8] = {0}; + + if (input_num < 3) + goto help; + + _os_sscanf(input[1], "%x", ¶1); + _os_sscanf(input[2], "%x", ¶2); + + buf[0] = (u8)((para1 & bMASKB3) >> 24); + buf[1] = (u8)((para1 & bMASKB2) >> 16); + buf[2] = (u8)((para1 & bMASKB1) >> 8); + buf[3] = (u8)(para1 & bMASKB0); + + buf[4] = (u8)((para2 & bMASKB3) >> 24); + buf[5] = (u8)((para2 & bMASKB2) >> 16); + buf[6] = (u8)((para2 & bMASKB1) >> 8); + buf[7] = (u8)(para2 & bMASKB0); + + if (!hal_btc_fw_set_1tdma(btc, (u16)sizeof(struct fbtc_tdma), buf)) + goto help; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set tdma parameters1 type=%s, rxflctrl=0x%x, txflctrl=%d, wtgle_n=%d\n", + id_to_str(BTC_STR_TDMA, (u32)buf[0]), buf[1], buf[2], buf[3]); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set tdma parameters2 leak_n=%d, ext_ctrl=%x, rxflctrl_role=0x%x\n", + buf[4], buf[5], buf[6]); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " tdma \n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[31:24]-> type --- 0:off, 1:fix, 2:auto, 3:auto2\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[23:19]-> rx_flow_ctrl --- send rx flow ctrl every n*w2b-slot\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[18:16]-> rx_flow_ctrl_type --- type 0:off, 1:null, 2:Qos-null, 3:cts\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[15:8] -> tx_flow_ctrl --- 0:off, 1:on\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[7:0] -> wtgle_n --- toggle coex table every n*w1-slot\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[31:24]-> leak_n --- enter leak slot every n*w2b-slot\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[23:16]-> ext_ctrl --- 0:off, 1:bcn-early_protect only 2:ext\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[15:8] -> resevrd\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bit[7:0] -> resevrd\n"); + return; +} + +static void _cmd_slot(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 sid = 0, dur = 0, cx_tbl = 0, cx_type = 0, i; + u32 *tmp32 = NULL; + u8 buf[9] = {0}; + + if (input_num < 5) + goto help; + + _os_sscanf(input[1], "%d", &sid); + _os_sscanf(input[2], "%d", &dur); + _os_sscanf(input[3], "%x", &cx_tbl); + _os_sscanf(input[4], "%d", &cx_type); + + buf[0] = (u8) sid; + buf[1] = (u8)(dur & bMASKB0); + buf[2] = (u8)((dur & bMASKB1) >> 8); + + tmp32 = (u32 *)&buf[3]; + *tmp32 = cx_tbl; + + buf[7] = (u8)(cx_type & bMASKB0); + buf[8] = (u8)((cx_type & bMASKB1) >> 8); + + if (!hal_btc_fw_set_1slot(btc, (u16)sizeof(struct fbtc_slot)+1, buf)) + goto help; + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set slot parameters: slot:%s, duration:%d, table:%08x, type=%s!!\n", + id_to_str(BTC_STR_SLOT, sid), dur, cx_tbl, + (cx_type? "iso" : "mix")); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " slot \n"); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " \n"); + + for (i = 0; i < CXST_MAX; i++) { + if ((i+1) % 5 == 1) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + " %d: %s", + i, id_to_str(BTC_STR_SLOT, i)); + else + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + ", %d: %s", i, id_to_str(BTC_STR_SLOT, i)); + + if (((i+1) % 5 == 0) || (i == CXST_MAX - 1)) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "\n"); + } + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " unit: ms\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " 32bits coex table\n"); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " BT packet at WL slot 0: allowed, 1: isolated\n"); + return; +} + +static void _cmd_sig_gdbg_en(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 map = 0, i; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%x", &map); + + hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_EN_MAP, map); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " signal to gpio debug map = 0x%08x!!\n", map); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " sig \n"); + + for (i = 0; i < BTC_DBG_MAX1; i++) { + if ((i+1) % 8 == 1) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + " %d: %s", + i, id_to_str(BTC_STR_GDBG, i)); + else + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + ", %d: %s", i, id_to_str(BTC_STR_GDBG, i)); + + if (((i+1) % 8 == 0) || (i == BTC_DBG_MAX1 - 1)) + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "\n"); + } + return; +} + +static void _cmd_sgpio_map(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 sig = 0, gpio = 0; + + if (input_num < 3) + goto help; + + _os_sscanf(input[1], "%d", &sig); + _os_sscanf(input[2], "%d", &gpio); + + if ((sig > 31) || (gpio > 7)) + goto help; + + hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_MUX_MAP, ((gpio << 8) + sig)); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " signal-%s -> gpio-%d\n", id_to_str(BTC_STR_GDBG, sig), gpio); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " gpio \n"); + return; +} + +static void _cmd_wl_tx_power(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 pwr = 0; + u8 is_negative = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &pwr); + if (pwr & BIT(31)) { + pwr = ~pwr + 1; + is_negative = 1; + } + + pwr = pwr & bMASKB0; + + if ((pwr != 255) && (pwr > 20)) + goto help; + + if (is_negative) + pwr |= BIT(7); + + _set_wl_tx_power(btc, pwr); + + if (pwr == 0xff) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set wl tx power level to original!!\n"); + else if (is_negative) + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set wl tx power level = -%d dBm!!\n", pwr & 0x7f); + else + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set wl tx power level = +%d dBm!!\n", pwr & 0x7f); + + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " wpwr original tx power\n"); + return; +} + +static void _cmd_wl_rx_lna(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 lna = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &lna); + + _set_wl_rx_gain(btc, lna); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set wl rx level = %d!!\n", lna); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " wlna \n"); + return; +} + +static void _cmd_bt_afh_map(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 en = 0, ch = 0, bw = 0; + + if (input_num < 4) + goto help; + + _os_sscanf(input[1], "%d", &en); + _os_sscanf(input[2], "%d", &ch); + _os_sscanf(input[3], "%d", &bw); + + btc->cx.wl.afh_info.en = (u8)en; + btc->cx.wl.afh_info.ch = (u8)ch; + btc->cx.wl.afh_info.bw = (u8)bw; + hal_btc_fw_set_bt(btc, SET_BT_WL_CH_INFO, 3, (u8*)&btc->cx.wl.afh_info); + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set bt afh map: en=%d, ch=%d, map=%d!!\n", en, ch, bw); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " afh \n"); + return; +} + +static void _cmd_bt_tx_power(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 pwr = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &pwr); + + _set_bt_tx_power(btc, pwr); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " decrease bt tx power level = %d!!\n", pwr); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bpwr \n"); + return; +} + +static void _cmd_bt_rx_lna(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 lna = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &lna); + + if (lna > 7) + goto help; + + _set_bt_rx_gain(btc, lna); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set bt rx lna constrain level = %d!!\n", lna); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " blna \n"); + return; +} + +static void _cmd_bt_igno_wlan(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 igno = 0; + + if (input_num < 2) + goto help; + + _os_sscanf(input[1], "%d", &igno); + + igno = igno & BIT(0); + + _set_bt_ignore_wlan_act(btc, (u8)igno); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set bt ignore wlan = %d!!\n", igno); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " igwl <0: don't ignore wlan, 1: ignore wlan > \n"); + return; +} + +static void _cmd_set_gnt_wl(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 gwl = 0, phy_map = BTC_PHY_ALL; + + if ((input_num != 2) && (input_num != 3)) + goto help; + + _os_sscanf(input[1], "%d", &gwl); + + if (input_num == 3) { + _os_sscanf(input[2], "%d", &phy_map); + phy_map = (phy_map == 0? BTC_PHY_0 : BTC_PHY_1); + } + + switch(gwl) { + case 0: + _set_gnt_wl(btc, (u8)phy_map, BTC_GNT_SW_LO); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_wl = SW-0 (phy_map=0x%x)\n", phy_map); + break; + case 1: + _set_gnt_wl(btc, (u8)phy_map, BTC_GNT_SW_HI); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_wl = SW-1 (phy_map=0x%x)\n", phy_map); + break; + case 2: + _set_gnt_wl(btc, (u8)phy_map, BTC_GNT_HW); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_wl = HW-PTA ctrl (phy_map=0x%x)\n", phy_map); + break; + } + + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " gwl <0:SW_0, 1:SW_1, 2:HW_PTA> <0:PHY-0, 1:PHY-1, none:All> \n"); + return; +} + +static void _cmd_set_gnt_bt(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 gbt = 0, phy_map = BTC_PHY_ALL; + + if ((input_num != 2) && (input_num != 3)) + goto help; + + _os_sscanf(input[1], "%d", &gbt); + + if (input_num == 3) { + _os_sscanf(input[2], "%d", &phy_map); + phy_map = (phy_map == 0? BTC_PHY_0 : BTC_PHY_1); + } + + switch(gbt) { + case 0: + _set_gnt_bt(btc, (u8)phy_map, BTC_GNT_SW_LO); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_bt = SW-0 (phy_map=0x%x)\n", phy_map); + break; + case 1: + _set_gnt_bt(btc, (u8)phy_map, BTC_GNT_SW_HI); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_bt = SW-1 (phy_map=0x%x)\n", phy_map); + break; + case 2: + _set_gnt_bt(btc, (u8)phy_map, BTC_GNT_HW); + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " set gnt_bt = HW-PTA ctrl (phy_map=0x%x)\n", phy_map); + break; + } + + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " gbt <0:SW_0, 1:SW_1, 2:HW_PTA> <0:PHY-0, 1:PHY-1, none:All> \n"); + return; +} + +static void _cmd_set_bt_psd(struct btc_t *btc, u32 *used, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 idx = 0, type = 0; + + if (input_num < 3) + goto help; + + _os_sscanf(input[1], "%d", &idx); + _os_sscanf(input[2], "%d", &type); + + _set_bt_psd_report(btc, (u8)idx, (u8)type); + return; +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " bpsd \n"); + return; +} + +void _get_wl_nhm_dbm(struct btc_t *btc) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_nhm *wl_nhm = &wl->nhm; + u8 set_result = false; + s8 bw_att_db = 13; + s8 nhm_pwr_dbm = 0; + s8 pwr = 0; + s8 cur_pwr = 0; + u16 save_index = 0; + bool new_data_flag = false; + struct watchdog_nhm_report nhm_rpt = {0}; + + if (wl->afh_info.bw < CHANNEL_WIDTH_5) { + + if (wl->afh_info.bw != CHANNEL_WIDTH_80_80) { + bw_att_db = + 13 + 3 * (s8)(wl->afh_info.bw - CHANNEL_WIDTH_20); + } else { + bw_att_db = 13 + 3 * 3; + } + } + + rtw_hal_bb_nhm_mntr_result(btc->hal, &nhm_rpt, HW_PHY_0); + + set_result = nhm_rpt.ccx_rpt_result; + + if (set_result) { + nhm_pwr_dbm = nhm_rpt.nhm_pwr_dbm; + + wl_nhm->instant_wl_nhm_dbm = nhm_pwr_dbm; + + if (wl_nhm->start_flag == false) { + wl_nhm->start_flag = true; + pwr = nhm_pwr_dbm - bw_att_db; + new_data_flag = true; + } else { + pwr = wl_nhm->pwr; + if (wl_nhm->last_ccx_rpt_stamp != + nhm_rpt.ccx_rpt_stamp) { + new_data_flag = true; + wl_nhm->current_status = 1; // new data + } else { + wl_nhm->current_status = 2; //duplicated data + } + } + + if (new_data_flag) { + wl_nhm->last_ccx_rpt_stamp = nhm_rpt.ccx_rpt_stamp; + cur_pwr = nhm_pwr_dbm - bw_att_db; + wl_nhm->instant_wl_nhm_per_mhz = cur_pwr; + + wl_nhm->valid_record_times += 1; + + if (wl_nhm->valid_record_times == 0) { + wl_nhm->valid_record_times = 16; + } + + save_index = (wl_nhm->valid_record_times + 16 - 1) % 16; + + wl_nhm->ratio = nhm_rpt.nhm_ratio; + + if (cur_pwr < pwr) { + pwr = cur_pwr; + wl_nhm->refresh = true; + } else { + pwr = (pwr >> 1) + (cur_pwr >> 1); + wl_nhm->refresh = false; + } + + wl_nhm->pwr = pwr; + + wl_nhm->record_pwr[(save_index & 0xF)] = pwr; + wl_nhm->record_ratio[(save_index & 0xF)] = nhm_rpt.nhm_ratio; + } + } +} + +static void _cmd_get_wl_nhm_dbm(struct btc_t *btc, u32 *used, + char input[][MAX_ARGV], u32 input_num, + char *output, u32 out_len) +{ + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_wl_nhm *wl_nhm = &wl->nhm; + u16 start_index = 0; + u16 stop_index = 0; + u16 i; + u32 show_record_num = 16; + + if (input_num >= 3) + goto help; + + _get_wl_nhm_dbm(btc); + + _os_sscanf(input[1], "%d", &show_record_num); + + if (show_record_num >= 16) + show_record_num = 16; + else if (show_record_num == 0) + show_record_num = 1; + + if (wl_nhm->valid_record_times > 0) { + + if (wl_nhm->current_status == 0) { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, "wl nhm failed this time\n"); + } + + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "nhm_psd = %d dBm/MHz, nhm_ratio = %d, status = %d, " + "valid_record_times = %d\n", + wl_nhm->pwr, wl_nhm->ratio, + wl_nhm->current_status, wl_nhm->valid_record_times); + + stop_index = wl_nhm->valid_record_times; + if (wl_nhm->valid_record_times > (u16)show_record_num) { + start_index = + wl_nhm->valid_record_times - (u16)show_record_num; + } + + for (i = start_index; i < stop_index; i++) { + if (i == start_index) { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "record_pwr(old->new) = %4d", + wl_nhm->record_pwr[(i + 16) & 0xF]); + + } else if (i == (stop_index - 1)) { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, ", %4d dBm/MHz\n", + wl_nhm->record_pwr[(i + 16) & 0xF]); + } else { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, ", %4d", + wl_nhm->record_pwr[(i + 16) & 0xF]); + } + } + + for (i = start_index; i < stop_index; i++) { + if (i == start_index) { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, + "record_ratio(old->new) = %4d", + wl_nhm->record_ratio[(i + 16) & 0xF]); + + } else if (i == (stop_index - 1)) { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, ", %4d percent\n", + wl_nhm->record_ratio[(i + 16) & 0xF]); + } else { + BTC_CNSL(out_len, *used, output + *used, + out_len - *used, ", %4d", + wl_nhm->record_ratio[(i + 16) & 0xF]); + } + } + + } else { + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + "wl nhm not ready\n"); + } + return; + +help: + BTC_CNSL(out_len, *used, output + *used, out_len - *used, + " wnhm \n"); + return; +} + +void halbtc_cmd_parser(struct btc_t *btc, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + u32 used = 0; + u8 id = 0; + u32 i; + u32 array_size = sizeof(halbtc_cmd_i) / sizeof(struct halbtc_cmd_info); + + BTC_CNSL(out_len, used, output + used, out_len - used, "\n"); + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < array_size; i++) { + if (_os_strcmp(halbtc_cmd_i[i].name, input[0]) == 0) { + id = halbtc_cmd_i[i].id; + break; + } + } + } + + switch (id) { + case HALBTC_DBG: + _cmd_dbg(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SHOW: + _cmd_show(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_WRITE_BT: + _cmd_wb(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_READ_BT: + _cmd_rb(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SET_COEX: + _cmd_set_coex(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_UPDATE_POLICY: + _cmd_update_policy(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_TDMA: + _cmd_tdma(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SLOT: + _cmd_slot(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SIG_GDBG_EN: + _cmd_sig_gdbg_en(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SGPIO_MAP: + _cmd_sgpio_map(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_WL_TX_POWER: + _cmd_wl_tx_power(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_WL_RX_LNA: + _cmd_wl_rx_lna(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_BT_AFH_MAP: + _cmd_bt_afh_map(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_BT_TX_POWER: + _cmd_bt_tx_power(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_BT_RX_LNA: + _cmd_bt_rx_lna(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_BT_IGNO_WLAN: + _cmd_bt_igno_wlan(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SET_GNT_WL: + _cmd_set_gnt_wl(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SET_GNT_BT: + _cmd_set_gnt_bt(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_SET_BT_PSD: + _cmd_set_bt_psd(btc, &used, input, input_num, output, out_len); + break; + case HALBTC_GET_WL_NHM_DBM: + _cmd_get_wl_nhm_dbm(btc, &used, input, input_num, output, out_len); + break; + default: + BTC_CNSL(out_len, used, output + used, out_len - used, + "command not supported !!\n"); + + /* fall through */ + + case HALBTC_HELP: + BTC_CNSL(out_len, used, output + used, out_len - used, + "BTC cmd ==>\n"); + + for (i = 0; i < array_size - 1; i++) + BTC_CNSL(out_len, used, output + used, out_len - used, + " %s\n", halbtc_cmd_i[i + 1].name); + break; + } +} + +s32 halbtc_cmd(struct btc_t *btc, char *input, char *output, u32 out_len) +{ + char *token; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; + + do { + token = _os_strsep(&input, ", "); + if (token) { + if (_os_strlen((u8 *)token) <= MAX_ARGV) + _os_strcpy(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < MAX_ARGC); +#if 0 + if (argc == 1) + argv[0][_os_strlen((u8 *)argv[0]) - 1] = '\0'; +#endif + + halbtc_cmd_parser(btc, argv, argc, output, out_len); + return 0; +} + +#endif + diff --git a/phl/hal_g6/btc/halbtc_dbg_cmd.h b/phl/hal_g6/btc/halbtc_dbg_cmd.h new file mode 100644 index 0000000..05590e0 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_dbg_cmd.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBTC_DBG_CMD_H_ +#define _HALBTC_DBG_CMD_H_ + +void halbtc_cmd_parser(struct btc_t *btc, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len); +s32 halbtc_cmd(struct btc_t *btc, char *input, char *output, u32 out_len); +void _get_wl_nhm_dbm(struct btc_t *btc); + + +#endif diff --git a/phl/hal_g6/btc/halbtc_def.c b/phl/hal_g6/btc/halbtc_def.c new file mode 100644 index 0000000..b4852a5 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_def.c @@ -0,0 +1,523 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_BTC_DEF_C_ +#include "../hal_headers_le.h" +#include "hal_btc.h" +#include "halbtc_fw.h" +#include "halbtc_action.h" + +#ifdef CONFIG_BTCOEX + +#define case_role(src) \ + case PHL_RTYPE_##src: return #src +#define case_mrole(src) \ + case BTC_WLMROLE_##src: return #src +#define case_slot(src) \ + case CXST_##src: return #src +#define case_reg(src) \ + case REG_##src: return #src +#define case_tdma(src) \ + case CXTDMA_##src: return #src +#define case_trace(src) \ + case CXSTEP_##src: return #src +#define case_branch(src) \ + case BTC_BRANCH_##src: return #src +#define case_rxflctrl_(src) \ + case CXFLC_##src: return #src +#define case_wllink(src) \ + case BTC_WLINK_##src: return #src +#define case_antpath(src) \ + case BTC_ANT_##src: return #src +#define case_gdbg(src) \ + case BTC_DBG_##src: return #src +#define case_chip(src) \ + case CHIP_##src: return #src +#define case_event(src) \ + case CXEVNT_##src: return #src +#define case_wlmode(src) \ + case WLAN_MD_##src: return #src +#define case_wlbw(src) \ + case CHANNEL_WIDTH_##src: return #src +#define case_cxp(src) \ + case BTC_CXP_##src: return #src +#define case_rftype(src) \ + case RF_##src: return #src +#define case_mstate(src) \ + case MLME_##src: return #src +#define case_rate(src) \ + case RTW_DATA_RATE_##src: return #src +#define case_polut(src) \ + case BTC_PLT_##src: return #src + +const char *id_to_str(u8 type, u32 id) +{ + switch(type) { + case BTC_STR_ROLE: + switch (id) { + case_role(NONE); + case_role(STATION); + case_role(AP); + case_role(VAP); + case_role(ADHOC); + case_role(ADHOC_MASTER); + case_role(MESH); + case_role(MONITOR); + case_role(P2P_DEVICE); + case_role(P2P_GC); + case_role(P2P_GO); + case_role(NAN); + } + break; + case BTC_STR_MROLE: + switch (id) { + case_mrole(NONE); + case_mrole(STA_GC); + case_mrole(STA_GC_NOA); + case_mrole(STA_GO); + case_mrole(STA_GO_NOA); + case_mrole(STA_STA); + } + break; + case BTC_STR_SLOT: + switch (id) { + case_slot(OFF); + case_slot(B2W); + case_slot(W1); + case_slot(W2); + case_slot(W2B); + case_slot(B1); + case_slot(B2); + case_slot(B3); + case_slot(B4); + case_slot(LK); + case_slot(BLK); + case_slot(E2G); + case_slot(E5G); + case_slot(EBT); + case_slot(ENULL); + case_slot(WLK); + case_slot(W1FDD); + case_slot(B1FDD); + } + break; + case BTC_STR_REG: + switch (id) { + case_reg(MAC); + case_reg(BB); + case_reg(RF); + case_reg(BT_RF); + case_reg(BT_MODEM); + case_reg(BT_BLUEWIZE); + case_reg(BT_VENDOR); + case_reg(BT_LE); + } + break; + case BTC_STR_TDMA: + switch (id) { + case_tdma(OFF); + case_tdma(FIX); + case_tdma(AUTO); + case_tdma(AUTO2); + } + break; + case BTC_STR_TRACE: + switch (id) { + case_trace(NONE); + case_trace(EVNT); + case_trace(SLOT); + } + break; + case BTC_STR_BRANCH: + switch (id) { + case_branch(MAIN); + case_branch(HP); + case_branch(LENOVO); + case_branch(HUAWEI); + } + break; + case BTC_STR_RXFLCTRL: + switch (id) { + case_rxflctrl_(OFF); + case_rxflctrl_(NULLP); + case_rxflctrl_(QOSNULL); + case_rxflctrl_(CTS); + } + break; + case BTC_STR_WLLINK: + switch (id) { + case_wllink(NOLINK); + case_wllink(2G_STA); + case_wllink(2G_GO); + case_wllink(2G_GC); + case_wllink(2G_AP); + case_wllink(2G_SCC); + case_wllink(2G_MCC); + case_wllink(25G_MCC); + case_wllink(25G_DBCC); + case_wllink(5G); + case_wllink(2G_NAN); + case_wllink(OTHER); + } + break; + case BTC_STR_ANTPATH: + switch (id) { + case_antpath(WPOWERON); + case_antpath(WINIT); + case_antpath(WONLY); + case_antpath(WOFF); + case_antpath(W2G); + case_antpath(W5G); + case_antpath(W25G); + case_antpath(FREERUN); + case_antpath(WRFK); + case_antpath(BRFK); + } + break; + case BTC_STR_GDBG: + switch (id) { + case_gdbg(GNT_BT); + case_gdbg(GNT_WL); + case_gdbg(BCN_EARLY); + case_gdbg(WL_NULL0); + case_gdbg(WL_NULL1); + case_gdbg(WL_RXISR); + case_gdbg(TDMA_ENTRY); + case_gdbg(A2DP_EMPTY); + case_gdbg(BT_RETRY); + case_gdbg(BT_RELINK); + case_gdbg(SLOT_WL); + case_gdbg(SLOT_BT); + case_gdbg(WL_RFK); + case_gdbg(BT_RFK); + case_gdbg(SLOT_B2W); + case_gdbg(SLOT_W1); + case_gdbg(SLOT_W2); + case_gdbg(SLOT_W2B); + case_gdbg(SLOT_B1); + case_gdbg(SLOT_B2); + case_gdbg(SLOT_B3); + case_gdbg(SLOT_B4); + case_gdbg(SLOT_LK); + case_gdbg(SLOT_E2G); + case_gdbg(SLOT_E5G); + case_gdbg(SLOT_EBT); + case_gdbg(SLOT_ENULL); + case_gdbg(SLOT_WLK); + case_gdbg(SLOT_W1FDD); + case_gdbg(SLOT_B1FDD); + case_gdbg(BT_CHANGE); + } + break; + case BTC_STR_CHIPID: + switch (id) { + case_chip(WIFI6_8852A); + case_chip(WIFI6_8852B); + case_chip(WIFI6_8852C); + } + break; + case BTC_STR_POLUT: + switch (id) { + case_polut(NONE); + case_polut(GNT_BT_TX); + case_polut(GNT_BT_RX); + case_polut(GNT_WL); + case_polut(BT); + case_polut(ALL); + } + break; + case BTC_STR_EVENT: + switch(id) { + case_event(TDMA_ENTRY); + case_event(WL_TMR); + case_event(B1_TMR); + case_event(B2_TMR); + case_event(B3_TMR); + case_event(B4_TMR); + case_event(W2B_TMR); + case_event(B2W_TMR); + case_event(BCN_EARLY); + case_event(A2DP_EMPTY); + case_event(LK_END); + case_event(RX_ISR); + case_event(RX_FC0); + case_event(RX_FC1); + case_event(BT_RELINK); + case_event(BT_RETRY); + case_event(E2G); + case_event(E5G); + case_event(EBT); + case_event(ENULL); + case_event(DRV_WLK); + case_event(BCN_OK); + case_event(BT_CHANGE); + case_event(EBT_EXTEND); + case_event(E2G_NULL1); + } + break; + case BTC_STR_WLMODE: + switch(id) { + case_wlmode(INVALID); + case_wlmode(11B); + case_wlmode(11A); + case_wlmode(11G); + case_wlmode(11N); + case_wlmode(11AC); + case_wlmode(11AX); + case_wlmode(11BG); + case_wlmode(11GN); + case_wlmode(11AN); + case_wlmode(11BN); + case_wlmode(11BGN); + case_wlmode(11BGAC); + case_wlmode(11BGAX); + case_wlmode(11A_AC); + case_wlmode(11A_AX); + case_wlmode(11AGN); + case_wlmode(11ABGN); + case_wlmode(24G_MIX); + case_wlmode(5G_MIX); + case_wlmode(MAX); + } + break; + case BTC_STR_WLBW: + switch(id) { + case_wlbw(20); + case_wlbw(40); + case_wlbw(80); + case_wlbw(160); + case_wlbw(80_80); + case_wlbw(5); + case_wlbw(10); + case_wlbw(MAX); + } + break; + case BTC_STR_RFTYPE: + switch(id) { + case_rftype(1T1R); + case_rftype(1T2R); + case_rftype(2T3R); + case_rftype(2T4R); + case_rftype(3T3R); + case_rftype(3T4R); + case_rftype(4T4R); + } + break; + case BTC_STR_POLICY: + switch(id) { + case_cxp(OFF_BT); + case_cxp(OFF_WL); + case_cxp(OFF_EQ0); + case_cxp(OFF_EQ1); + case_cxp(OFF_EQ2); + case_cxp(OFF_EQ3); + case_cxp(OFF_BWB0); + case_cxp(OFF_BWB1); + case_cxp(OFF_BWB2); + case_cxp(OFFB_BWB0); + case_cxp(OFFE_2GBWISOB); + case_cxp(OFFE_2GISOB); + case_cxp(OFFE_2GBWMIXB); + case_cxp(OFFE_2GBWMIXB2); + case_cxp(OFFE_WL); + case_cxp(FIX_TD3030); + case_cxp(FIX_TD5050); + case_cxp(FIX_TD2030); + case_cxp(FIX_TD4010); + case_cxp(FIX_TD7010); + case_cxp(FIX_TD2060); + case_cxp(FIX_TD3060); + case_cxp(FIX_TD2080); + case_cxp(FIX_TDW1B1); + case_cxp(FIX_TD4010ISO); + case_cxp(PFIX_TD3030); + case_cxp(PFIX_TD5050); + case_cxp(PFIX_TD2030); + case_cxp(PFIX_TD2060); + case_cxp(PFIX_TD3070); + case_cxp(PFIX_TD2080); + case_cxp(PFIX_TDW1B1); + case_cxp(AUTO_TD50B1); + case_cxp(AUTO_TD60B1); + case_cxp(AUTO_TD20B1); + case_cxp(AUTO_TDW1B1); + case_cxp(PAUTO_TD50B1); + case_cxp(PAUTO_TD60B1); + case_cxp(PAUTO_TD20B1); + case_cxp(PAUTO_TDW1B1); + case_cxp(AUTO2_TD3050); + case_cxp(AUTO2_TD3070); + case_cxp(AUTO2_TD5050); + case_cxp(AUTO2_TD6060); + case_cxp(AUTO2_TD2080); + case_cxp(AUTO2_TDW1B4); + case_cxp(PAUTO2_TD3050); + case_cxp(PAUTO2_TD3070); + case_cxp(PAUTO2_TD5050); + case_cxp(PAUTO2_TD6060); + case_cxp(PAUTO2_TD2080); + case_cxp(PAUTO2_TDW1B4); + } + break; + case BTC_STR_MSTATE: + switch(id) { + case_mstate(NO_LINK); + case_mstate(LINKING); + case_mstate(LINKED); + } + break; + case BTC_STR_RATE: + switch(id) { + case_rate(CCK1); + case_rate(CCK2); + case_rate(CCK5_5); + case_rate(CCK11); + case_rate(OFDM6); + case_rate(OFDM9); + case_rate(OFDM12); + case_rate(OFDM18); + case_rate(OFDM24); + case_rate(OFDM36); + case_rate(OFDM48); + case_rate(OFDM54); + case_rate(MCS0); + case_rate(MCS1); + case_rate(MCS2); + case_rate(MCS3); + case_rate(MCS4); + case_rate(MCS5); + case_rate(MCS6); + case_rate(MCS7); + case_rate(MCS8); + case_rate(MCS9); + case_rate(MCS10); + case_rate(MCS11); + case_rate(MCS12); + case_rate(MCS13); + case_rate(MCS14); + case_rate(MCS15); + case_rate(MCS16); + case_rate(MCS17); + case_rate(MCS18); + case_rate(MCS19); + case_rate(MCS20); + case_rate(MCS21); + case_rate(MCS22); + case_rate(MCS23); + case_rate(MCS24); + case_rate(MCS25); + case_rate(MCS26); + case_rate(MCS27); + case_rate(MCS28); + case_rate(MCS29); + case_rate(MCS30); + case_rate(MCS31); + case_rate(VHT_NSS1_MCS0); + case_rate(VHT_NSS1_MCS1); + case_rate(VHT_NSS1_MCS2); + case_rate(VHT_NSS1_MCS3); + case_rate(VHT_NSS1_MCS4); + case_rate(VHT_NSS1_MCS5); + case_rate(VHT_NSS1_MCS6); + case_rate(VHT_NSS1_MCS7); + case_rate(VHT_NSS1_MCS8); + case_rate(VHT_NSS1_MCS9); + case_rate(VHT_NSS2_MCS0); + case_rate(VHT_NSS2_MCS1); + case_rate(VHT_NSS2_MCS2); + case_rate(VHT_NSS2_MCS3); + case_rate(VHT_NSS2_MCS4); + case_rate(VHT_NSS2_MCS5); + case_rate(VHT_NSS2_MCS6); + case_rate(VHT_NSS2_MCS7); + case_rate(VHT_NSS2_MCS8); + case_rate(VHT_NSS2_MCS9); + case_rate(VHT_NSS3_MCS0); + case_rate(VHT_NSS3_MCS1); + case_rate(VHT_NSS3_MCS2); + case_rate(VHT_NSS3_MCS3); + case_rate(VHT_NSS3_MCS4); + case_rate(VHT_NSS3_MCS5); + case_rate(VHT_NSS3_MCS6); + case_rate(VHT_NSS3_MCS7); + case_rate(VHT_NSS3_MCS8); + case_rate(VHT_NSS3_MCS9); + case_rate(VHT_NSS4_MCS0); + case_rate(VHT_NSS4_MCS1); + case_rate(VHT_NSS4_MCS2); + case_rate(VHT_NSS4_MCS3); + case_rate(VHT_NSS4_MCS4); + case_rate(VHT_NSS4_MCS5); + case_rate(VHT_NSS4_MCS6); + case_rate(VHT_NSS4_MCS7); + case_rate(VHT_NSS4_MCS8); + case_rate(VHT_NSS4_MCS9); + case_rate(HE_NSS1_MCS0); + case_rate(HE_NSS1_MCS1); + case_rate(HE_NSS1_MCS2); + case_rate(HE_NSS1_MCS3); + case_rate(HE_NSS1_MCS4); + case_rate(HE_NSS1_MCS5); + case_rate(HE_NSS1_MCS6); + case_rate(HE_NSS1_MCS7); + case_rate(HE_NSS1_MCS8); + case_rate(HE_NSS1_MCS9); + case_rate(HE_NSS1_MCS10); + case_rate(HE_NSS1_MCS11); + case_rate(HE_NSS2_MCS0); + case_rate(HE_NSS2_MCS1); + case_rate(HE_NSS2_MCS2); + case_rate(HE_NSS2_MCS3); + case_rate(HE_NSS2_MCS4); + case_rate(HE_NSS2_MCS5); + case_rate(HE_NSS2_MCS6); + case_rate(HE_NSS2_MCS7); + case_rate(HE_NSS2_MCS8); + case_rate(HE_NSS2_MCS9); + case_rate(HE_NSS2_MCS10); + case_rate(HE_NSS2_MCS11); + case_rate(HE_NSS3_MCS0); + case_rate(HE_NSS3_MCS1); + case_rate(HE_NSS3_MCS2); + case_rate(HE_NSS3_MCS3); + case_rate(HE_NSS3_MCS4); + case_rate(HE_NSS3_MCS5); + case_rate(HE_NSS3_MCS6); + case_rate(HE_NSS3_MCS7); + case_rate(HE_NSS3_MCS8); + case_rate(HE_NSS3_MCS9); + case_rate(HE_NSS3_MCS10); + case_rate(HE_NSS3_MCS11); + case_rate(HE_NSS4_MCS0); + case_rate(HE_NSS4_MCS1); + case_rate(HE_NSS4_MCS2); + case_rate(HE_NSS4_MCS3); + case_rate(HE_NSS4_MCS4); + case_rate(HE_NSS4_MCS5); + case_rate(HE_NSS4_MCS6); + case_rate(HE_NSS4_MCS7); + case_rate(HE_NSS4_MCS8); + case_rate(HE_NSS4_MCS9); + case_rate(HE_NSS4_MCS10); + case_rate(HE_NSS4_MCS11); + case_rate(MAX); + } + break; + } + + return "Undefine"; +} + + +#endif diff --git a/phl/hal_g6/btc/halbtc_def.h b/phl/hal_g6/btc/halbtc_def.h new file mode 100644 index 0000000..7212843 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_def.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_BTC_DEF_H__ +#define __INC_BTC_DEF_H__ + + +const char *id_to_str(u8 type, u32 id); + +#endif \ No newline at end of file diff --git a/phl/hal_g6/btc/halbtc_fw.c b/phl/hal_g6/btc/halbtc_fw.c new file mode 100644 index 0000000..e89ff99 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_fw.c @@ -0,0 +1,842 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_BTC_FW_C_ +#include "../hal_headers_le.h" +#include "hal_btc.h" +#include "halbtc_fw.h" +#include "halbtc_def.h" + +#ifdef CONFIG_BTCOEX + +void _chk_btc_err(struct btc_t *btc, u8 type, u32 cnt) +{ + struct btc_cx *cx = &btc->cx; + struct btc_dm *dm = &btc->dm; + struct btc_bt_info *bt = &cx->bt; + + switch (type) { + case BTC_DCNT_RPT_FREEZE: + if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map) + dm->cnt_dm[BTC_DCNT_RPT_FREEZE]++; + else + dm->cnt_dm[BTC_DCNT_RPT_FREEZE] = 0; + + if (dm->cnt_dm[BTC_DCNT_RPT_FREEZE] >= BTC_CHK_HANG_MAX) + dm->error.map.wl_fw_hang = true; + else + dm->error.map.wl_fw_hang = false; + + dm->cnt_dm[BTC_DCNT_RPT] = cnt; + break; + case BTC_DCNT_CYCLE_FREEZE: + if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt && + (dm->tdma_now.type != CXTDMA_OFF || + dm->tdma_now.ext_ctrl == CXECTL_EXT)) + dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE]++; + else + dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] = 0; + + if (dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] >= BTC_CHK_HANG_MAX) + dm->error.map.cycle_hang = true; + else + dm->error.map.cycle_hang = false; + + dm->cnt_dm[BTC_DCNT_CYCLE] = cnt; + break; + case BTC_DCNT_W1_FREEZE: + if (dm->cnt_dm[BTC_DCNT_W1] == cnt && + dm->tdma_now.type != CXTDMA_OFF) + dm->cnt_dm[BTC_DCNT_W1_FREEZE]++; + else + dm->cnt_dm[BTC_DCNT_W1_FREEZE] = 0; + + if (dm->cnt_dm[BTC_DCNT_W1_FREEZE] >= BTC_CHK_HANG_MAX) + dm->error.map.w1_hang = true; + else + dm->error.map.w1_hang = false; + + dm->cnt_dm[BTC_DCNT_W1] = cnt; + break; + case BTC_DCNT_B1_FREEZE: + if (dm->cnt_dm[BTC_DCNT_B1] == cnt && + dm->tdma_now.type != CXTDMA_OFF) + dm->cnt_dm[BTC_DCNT_B1_FREEZE]++; + else + dm->cnt_dm[BTC_DCNT_B1_FREEZE] = 0; + + if (dm->cnt_dm[BTC_DCNT_B1_FREEZE] >= BTC_CHK_HANG_MAX) + dm->error.map.b1_hang = true; + else + dm->error.map.b1_hang = false; + + dm->cnt_dm[BTC_DCNT_B1] = cnt; + break; + case BTC_DCNT_TDMA_NONSYNC: + if (cnt != 0) /* if tdma not sync between drv/fw */ + dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++; + else + dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0; + + if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX) + dm->error.map.tdma_no_sync = true; + else + dm->error.map.tdma_no_sync = false; + break; + case BTC_DCNT_SLOT_NONSYNC: + if (cnt != 0) /* if slot not sync between drv/fw */ + dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++; + else + dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0; + + if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX) + dm->error.map.tdma_no_sync = true; + else + dm->error.map.tdma_no_sync = false; + break; + case BTC_DCNT_BTCNT_FREEZE: + cnt = cx->cnt_bt[BTC_BCNT_HIPRI_RX] + + cx->cnt_bt[BTC_BCNT_HIPRI_TX] + + cx->cnt_bt[BTC_BCNT_LOPRI_RX] + + cx->cnt_bt[BTC_BCNT_LOPRI_TX]; + + if (cnt == 0) + dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE]++; + else + dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] = 0; + + if ((dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX && + bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] && + !bt->enable.now)) + _update_bt_scbd(btc, false); + break; + case BTC_DCNT_WL_SLOT_DRIFT: + if (cnt >= BTC_CHK_WLSLOT_DRIFT_MAX) + dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++; + else + dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0; + + if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) + dm->error.map.wl_slot_drift = true; + else + dm->error.map.wl_slot_drift = false; + break; + case BTC_DCNT_BT_SLOT_DRIFT: + if (cnt >= BTC_CHK_BTSLOT_DRIFT_MAX) + dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT]++; + else + dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] = 0; + + if (dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) + dm->error.map.bt_slot_drift = true; + else + dm->error.map.bt_slot_drift = false; + break; + } +} + +static void _update_bt_report(struct btc_t *btc, u8 rpt_type, u8* pfinfo) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_bt_info *bt = &btc->cx.bt; + struct btc_bt_link_info *bt_linfo = &bt->link_info; + struct btc_bt_a2dp_desc *a2dp = &bt_linfo->a2dp_desc; + + struct fbtc_btver* pver = (struct fbtc_btver*) pfinfo; + struct fbtc_btscan* pscan = (struct fbtc_btscan*) pfinfo; + struct fbtc_btafh* pafh = (struct fbtc_btafh*) pfinfo; + struct fbtc_btdevinfo* pdev = (struct fbtc_btdevinfo*) pfinfo; + + switch (rpt_type) { + case BTC_RPT_TYPE_BT_VER: + bt->ver_info.fw = pver->fw_ver; + bt->ver_info.fw_coex = (pver->coex_ver & bMASKB0); + bt->feature = pver->feature; + break; + case BTC_RPT_TYPE_BT_SCAN: + hal_mem_cpy(h, bt->scan_info, pscan->scan, BTC_SCAN_MAX1); + break; + case BTC_RPT_TYPE_BT_AFH: + hal_mem_cpy(h, &bt_linfo->afh_map[0], pafh->afh_l, 4); + hal_mem_cpy(h, &bt_linfo->afh_map[4], pafh->afh_m, 4); + hal_mem_cpy(h, &bt_linfo->afh_map[8], pafh->afh_h, 2); + break; + case BTC_RPT_TYPE_BT_DEVICE: + a2dp->device_name = pdev->dev_name; + a2dp->vendor_id = pdev->vendor_id; + a2dp->flush_time = pdev->flush_time; + break; + default: + break; + } +} + +static u32 _chk_btc_report(struct btc_t *btc, struct btf_fwinfo *pfwinfo, + u8 *prptbuf, u32 index) +{ + struct btc_dm *dm = &btc->dm; + struct rtw_hal_com_t *hal = btc->hal; + struct btc_rpt_cmn_info *pcinfo = NULL; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_bt_info *bt = &btc->cx.bt; + struct fbtc_rpt_ctrl *prpt = NULL; + struct fbtc_cysta *pcysta = NULL; + u8 rpt_type = 0, *rpt_content = NULL, *pfinfo = NULL; + u16 wl_slot_set = 0; + u32 rpt_len = 0, diff_t, bt_slot_real = 0; + + if (!prptbuf) { + pfwinfo->err[BTFRE_INVALID_INPUT]++; + return 0; + } + + rpt_type = prptbuf[index]; + rpt_len = (prptbuf[index+2] << 8) + prptbuf[index+1]; + rpt_content = &prptbuf[index+3]; + + switch (rpt_type) { + case BTC_RPT_TYPE_CTRL: + pcinfo = &pfwinfo->rpt_ctrl.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_ctrl.finfo); + pcinfo->req_len = sizeof(struct fbtc_rpt_ctrl); + pcinfo->req_fver = FCX_BTCRPT_VER; + pcinfo->rsp_fver = *rpt_content; + break; + case BTC_RPT_TYPE_TDMA: + pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_tdma.finfo); + pcinfo->req_len = sizeof(struct fbtc_1tdma); + pcinfo->req_fver = FCX_TDMA_VER; + break; + case BTC_RPT_TYPE_SLOT: + pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_slots.finfo); + pcinfo->req_len = sizeof(struct fbtc_slots); + pcinfo->req_fver = FCX_SLOT_VER; + break; + case BTC_RPT_TYPE_CYSTA: + pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo); + pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; + pcinfo->req_len = sizeof(struct fbtc_cysta); + pcinfo->req_fver = FCX_CYSTA_VER; + break; + case BTC_RPT_TYPE_STEP: + pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_step.finfo); + pcinfo->req_len = 8 + sizeof(struct fbtc_step) * FCXDEF_STEP; + pcinfo->req_fver = FCX_STEP_VER; + break; + case BTC_RPT_TYPE_NULLSTA: + pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_nullsta.finfo); + pcinfo->req_len = sizeof(struct fbtc_cynullsta); + pcinfo->req_fver = FCX_NULLSTA_VER; + break; + case BTC_RPT_TYPE_MREG: + pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_mregval.finfo); + pcinfo->req_len = sizeof(struct fbtc_mreg_val); + pcinfo->req_fver = FCX_MREG_VER; + break; + case BTC_RPT_TYPE_GPIO_DBG: + pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_gpio_dbg.finfo); + pcinfo->req_len = sizeof(struct fbtc_gpio_dbg); + pcinfo->req_fver = FCX_GPIODBG_VER; + break; + case BTC_RPT_TYPE_BT_VER: + pcinfo = &pfwinfo->rpt_fbtc_btver.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btver.finfo); + pcinfo->req_len = sizeof(struct fbtc_btver); + pcinfo->req_fver = FCX_BTVER_VER; + break; + case BTC_RPT_TYPE_BT_SCAN: + pcinfo = &pfwinfo->rpt_fbtc_btscan.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btscan.finfo); + pcinfo->req_len = sizeof(struct fbtc_btscan); + pcinfo->req_fver = FCX_BTSCAN_VER; + break; + case BTC_RPT_TYPE_BT_AFH: + pcinfo = &pfwinfo->rpt_fbtc_btafh.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btafh.finfo); + pcinfo->req_len = sizeof(struct fbtc_btafh); + pcinfo->req_fver = FCX_BTAFH_VER; + break; + case BTC_RPT_TYPE_BT_DEVICE: + pcinfo = &pfwinfo->rpt_fbtc_btdev.cinfo; + pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btdev.finfo); + pcinfo->req_len = sizeof(struct fbtc_btdevinfo); + pcinfo->req_fver = FCX_BTDEVINFO_VER; + break; + default: + pfwinfo->err[BTFRE_UNDEF_TYPE]++; + return 0; + } + + pcinfo->rsp_fver = *rpt_content; + pcinfo->rx_len = rpt_len; + pcinfo->rx_cnt++; + + if (rpt_len != pcinfo->req_len) { + if (rpt_type < BTC_RPT_TYPE_MAX) + pfwinfo->len_mismch |= (0x1 << rpt_type); + else + pfwinfo->len_mismch |= BIT31; + + pcinfo->valid = 0; + return 0; + } else if (pcinfo->req_fver != pcinfo->rsp_fver) { + if (rpt_type < BTC_RPT_TYPE_MAX) + pfwinfo->fver_mismch |= (0x1 << rpt_type); + else + pfwinfo->fver_mismch |= BIT31; + pcinfo->valid = 0; + return 0; + } else if (!pfinfo || !rpt_content || !pcinfo->req_len) { + pfwinfo->err[BTFRE_EXCEPTION]++; + pcinfo->valid = 0; + return 0; + } + + + hal_mem_cpy(hal, (void *)pfinfo, (void *)rpt_content, pcinfo->req_len); + pcinfo->valid = 1; + + if (rpt_type == BTC_RPT_TYPE_TDMA) { +#if BTC_CX_FW_OFFLOAD /* update tdma_now if fw offload for debug */ + _tdma_cpy(&dm->tdma_now, &pfwinfo->rpt_fbtc_tdma.finfo.tdma); +#else + _chk_btc_err(btc, BTC_DCNT_TDMA_NONSYNC, + _tdma_cmp(&dm->tdma_now, + &pfwinfo->rpt_fbtc_tdma.finfo.tdma)); +#endif + } + + if (rpt_type == BTC_RPT_TYPE_SLOT) { +#if BTC_CX_FW_OFFLOAD /* update slot_now if fw offload for debug */ + _slots_cpy(dm->slot_now, pfwinfo->rpt_fbtc_slots.finfo.slot); +#else + _chk_btc_err(btc, BTC_DCNT_SLOT_NONSYNC, + _tdma_cmp(dm->slot_now, + pfwinfo->rpt_fbtc_slots.finfo.slot)); +#endif + } + + if (rpt_type == BTC_RPT_TYPE_CYSTA && + pcysta->cycles >= BTC_CYSTA_CHK_PERIOD) { + /* Check Leak-AP */ + if (pcysta->slot_cnt[CXST_LK] != 0 && + pcysta->leak_slot.cnt_rximr != 0 && dm->tdma_now.rxflctrl) { + if (pcysta->slot_cnt[CXST_LK] < + BTC_LEAK_AP_TH * pcysta->leak_slot.cnt_rximr) + dm->leak_ap = 1; + } + + /* Check diff time between real WL slot and W1 slot */ + if (dm->tdma_now.type != CXTDMA_OFF) { + wl_slot_set = dm->slot_now[CXST_W1].dur; + + if (pcysta->cycle_time.tavg[CXT_WL] > wl_slot_set) { + diff_t = pcysta->cycle_time.tavg[CXT_WL] - + wl_slot_set; + _chk_btc_err(btc, BTC_DCNT_WL_SLOT_DRIFT, diff_t); + } + } + + /* Check diff time between real BT slot and EBT/E5G slot */ + if (dm->tdma_now.type == CXTDMA_OFF && + dm->tdma_now.ext_ctrl == CXECTL_EXT && + btc->bt_req_len != 0) { + bt_slot_real = pcysta->cycle_time.tavg[CXT_BT]; + + if (btc->bt_req_len > bt_slot_real) { + diff_t = btc->bt_req_len - bt_slot_real; + _chk_btc_err(btc, BTC_DCNT_BT_SLOT_DRIFT, diff_t); + } + + } + } + + if (rpt_type == BTC_RPT_TYPE_CTRL) { + prpt = &pfwinfo->rpt_ctrl.finfo; + btc->fwinfo.rpt_en_map = prpt->rpt_info.en; + wl->ver_info.fw_coex = prpt->wl_fw_info.cx_ver; + wl->ver_info.fw = prpt->wl_fw_info.fw_ver; + dm->wl_fw_cx_offload = !!(prpt->wl_fw_info.cx_offload); + + if (dm->wl_fw_cx_offload != BTC_CX_FW_OFFLOAD) + dm->error.map.offload_mismatch = true; + else + dm->error.map.offload_mismatch = false; + + if (prpt->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT] > 0) + bt->rfk_info.map.timeout = 1; + else + bt->rfk_info.map.timeout = 0; + + dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout; + } + + if (rpt_type >= BTC_RPT_TYPE_BT_VER && + rpt_type <= BTC_RPT_TYPE_BT_DEVICE) + _update_bt_report(btc, rpt_type, pfinfo); + + return (rpt_len + BTC_RPT_HDR_SIZE); +} + +static void _parse_btc_report(struct btc_t *btc, struct btf_fwinfo *pfwinfo, + u8 *pbuf, u32 buf_len) +{ + u32 index = 0, rpt_len = 0; + + while (pbuf) { + if (index+2 >= RTW_PHL_BTC_FWINFO_BUF) + break; + /* At least 3 bytes: type(1) & len(2) */ + rpt_len = (pbuf[index+2] << 8) + pbuf[index+1]; + if ((index + rpt_len + BTC_RPT_HDR_SIZE) > buf_len) + break; + + rpt_len = _chk_btc_report(btc, pfwinfo, pbuf, index); + if (!rpt_len) + break; + index += rpt_len; + } +} + +static void _append_tdma(struct btc_t *btc, bool force_exec) +{ + struct btc_dm *dm = &btc->dm; + struct btf_tlv *tlv = NULL; + struct fbtc_1tdma *v = NULL; + u16 len = btc->policy_len; + + if (!force_exec && !_tdma_cmp(&dm->tdma, &dm->tdma_now)) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): tdma no change!\n", + __func__); + return; + } + + tlv = (struct btf_tlv *)&btc->policy[len]; + tlv->type = CXPOLICY_TDMA; + tlv->len = sizeof(struct fbtc_1tdma); + v = (struct fbtc_1tdma *)&tlv->val[0]; + v->fver = FCX_TDMA_VER; + + _tdma_cpy(&v->tdma, &dm->tdma); + + btc->policy_len = len + 2 + sizeof(struct fbtc_1tdma); + + PHL_INFO("[BTC], %s: type:%d, rxflctrl=%d, txflctrl=%d, wtgle_n=%d, leak_n=%d, ext_ctrl=%d, rxflctrl_role=0x%x\n", + __func__, dm->tdma.type, dm->tdma.rxflctrl, dm->tdma.txflctrl, + dm->tdma.wtgle_n, dm->tdma.leak_n, dm->tdma.ext_ctrl, + dm->tdma.rxflctrl_role); +} + +static void _append_slot(struct btc_t *btc, bool force_exec) +{ + struct btc_dm *dm = &btc->dm; + struct btf_tlv *tlv = NULL; + struct fbtc_1slot *v = NULL; + u16 len = 0; + u8 i, cnt = 0; + + for (i = 0; i < CXST_MAX; i++) { + if (!force_exec && !_slot_cmp(&dm->slot[i], &dm->slot_now[i])) + continue; + + len = btc->policy_len; + + tlv = (struct btf_tlv *)&btc->policy[len]; + tlv->type = CXPOLICY_SLOT; + tlv->len = sizeof(struct fbtc_1slot); + v = (struct fbtc_1slot *)&tlv->val[0]; + + v->fver = FCX_SLOT_VER; + v->sid = i; + _slot_cpy(&v->slot, &dm->slot[i]); + + PHL_INFO("[BTC], %s: slot-%d: dur=%d, table=0x%08x, type=%d\n", + __func__, i,dm->slot[i].dur, dm->slot[i].cxtbl, + dm->slot[i].cxtype); + cnt++; + btc->policy_len = len + 2 + sizeof(struct fbtc_1slot); + } + + if (cnt > 0) + PHL_INFO("[BTC], %s: slot update (cnt=%d)!!\n", __func__, cnt); +} + +/* + * extern functions + */ + +void hal_btc_fw_en_rpt(struct btc_t *btc, u32 rpt_map, u32 rpt_state) +{ + struct btc_ops *ops = btc->ops; + struct btf_set_report r = {0}; + struct btf_fwinfo* fwinfo = &btc->fwinfo; + u32 val = 0; + u8 en; + + if (!ops || !ops->fw_cmd) + return; + + en = rpt_state & 0x1; + if (en) + val = fwinfo->rpt_en_map | rpt_map; + else + val = fwinfo->rpt_en_map & (~rpt_map); + + if (val == fwinfo->rpt_en_map) + return; + + fwinfo->rpt_en_map = val; + + r.fver = FCX_BTCRPT_VER; + r.enable = val; + r.para = en; + + ops->fw_cmd(btc, BTFC_SET, SET_REPORT_EN, (u8 *)&r, sizeof(r)); +} + +void hal_btc_fw_set_slots(struct btc_t *btc, u8 num, struct fbtc_slot *s) +{ +#if !BTC_CX_FW_OFFLOAD + struct rtw_hal_com_t *h = btc->hal; + struct btc_ops *ops = btc->ops; + struct btf_set_slot_table *tbl = NULL; + u8 *ptr = NULL; + u16 n = 0; + + if (!ops || !ops->fw_cmd) + return; + + n = (sizeof(struct fbtc_slot) * num) + sizeof(*tbl) - 1; + tbl = hal_mem_alloc(h, n); + if (!tbl) + return; + + tbl->fver = FCX_SLOT_VER; + tbl->tbl_num = num; + ptr = &tbl->buf[0]; + hal_mem_cpy(h, (void*)ptr, s, num * sizeof(struct fbtc_slot)); + + ops->fw_cmd(btc, BTFC_SET, SET_SLOT_TABLE, (u8*)tbl, n); + hal_mem_free(h, (void*)tbl, n); +#endif +} + +/* set RPT_EN_MREG = 0 to stop 2s monitor timer in WL FW, + * before SET_MREG_TABLE, and set RPT_EN_MREG = 1 after + * SET_MREG_TABLE + */ +void hal_btc_fw_set_monreg(struct btc_t *btc) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_ops *ops = btc->ops; + struct btf_set_mon_reg *monreg = NULL; + u8 n, *ptr = NULL, ulen; + u16 sz = 0; + + if (!ops || !ops->fw_cmd) + return; + + n = btc->chip->mon_reg_num; + + if (n > CXMREG_MAX) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], mon reg count %d > %d\n", + n, CXMREG_MAX); + return; + } + + ulen = sizeof(struct fbtc_mreg); + sz = (ulen * n) + sizeof(*monreg) - 1; + monreg = hal_mem_alloc(h, sz); + if (!monreg) + return; + + monreg->fver = FCX_MREG_VER; + monreg->reg_num = n; + ptr = &monreg->buf[0]; + hal_mem_cpy(h, (void *)ptr, btc->chip->mon_reg, n * ulen); + + ops->fw_cmd(btc, BTFC_SET, SET_MREG_TABLE, (u8 *)monreg, sz); + hal_mem_free(h, (void *)monreg, sz); + hal_btc_fw_en_rpt(btc, RPT_EN_MREG, 1); +} + +bool hal_btc_fw_set_1tdma(struct btc_t *btc, u16 len, u8 *buf) +{ /* for wlcli manual control */ + struct btc_dm *dm = &btc->dm; + + if (len != sizeof(struct fbtc_tdma)) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because len != %d\n", + __func__, (int)sizeof(struct fbtc_tdma)); + return false; + } else if (buf[0] >= CXTDMA_MAX) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because tdma_type >= %d\n", + __func__, CXTDMA_MAX); + return false; + } + + _tdma_cpy(&dm->tdma, buf); + return true; +} + +bool hal_btc_fw_set_1slot(struct btc_t *btc, u16 len, u8 *buf) +{ /* for wlcli manual control */ + struct btc_dm *dm = &btc->dm; + + if (len != sizeof(struct fbtc_slot) + 1) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because len != %d\n", + __func__, (int)sizeof(struct fbtc_slot) + 1); + return false; + } else if (buf[0] >= CXST_MAX) { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because slot_id >= %d\n", + __func__, CXST_MAX); + return false; + } + + _slot_cpy(&dm->slot[buf[0]], &buf[1]); + return true; +} + +bool hal_btc_fw_set_policy(struct btc_t *btc, bool force_exec, u16 policy_type, + const char* action) +{ + struct btc_dm *dm = &btc->dm; + struct btc_ops *ops = btc->ops; + + if (!ops || !ops->fw_cmd) + return false; + + _act_cpy(dm->run_action, (char*)action); + _update_dm_step(btc, action); + _update_dm_step(btc, id_to_str(BTC_STR_POLICY, (u32)policy_type)); + + btc->policy_len = 0; /* clear length before append */ + btc->policy_type = policy_type; + + _append_tdma(btc, force_exec); + _append_slot(btc, force_exec); + + if (btc->policy_len == 0 || btc->policy_len > BTC_POLICY_MAXLEN) + return false; + + PHL_INFO("[BTC], %s(): action=%s -> policy type/len: 0x%04x/%d\n", + __func__, action, policy_type, btc->policy_len); + + if (dm->tdma.rxflctrl == CXFLC_NULLP) + btc->hal->btc_ctrl.lps = 1; + else + btc->hal->btc_ctrl.lps = 0; + + if (btc->hal->btc_ctrl.lps == 1) + hal_btc_notify_ps_tdma(btc, btc->hal->btc_ctrl.lps); + + ops->fw_cmd(btc, BTFC_SET, SET_CX_POLICY, btc->policy, btc->policy_len); + + _tdma_cpy(&dm->tdma_now, &dm->tdma); + _slots_cpy(dm->slot_now, dm->slot); + + if (btc->hal->btc_ctrl.lps == 0) + hal_btc_notify_ps_tdma(btc, btc->hal->btc_ctrl.lps); + + return true; +} + +void hal_btc_fw_set_gpio_dbg(struct btc_t *btc, u8 type, u32 val) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_ops *ops = btc->ops; + u8 data[7] = {0}, len = 0; + + if (!ops || !ops->fw_cmd || type >= CXDGPIO_MAX) + return; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__); + + data[0] = FCX_GPIODBG_VER; + data[1] = 0; + data[2] = type; + + switch(type) { + case CXDGPIO_EN_MAP: + len = sizeof(u32) + 3; + hal_mem_cpy(h, &data[3], &val, sizeof(u32)); + break; + case CXDGPIO_MUX_MAP: + len = sizeof(8) * 2 + 3; + data[3] = (u8)(val & bMASKB0); + data[4] = (u8)((val & bMASKB1) >> 8); + break; + default: + return; + } + + ops->fw_cmd(btc, BTFC_SET, SET_GPIO_DBG, data, len); +} + +void hal_btc_fw_set_drv_info(struct btc_t *btc, u8 type) +{ + struct rtw_hal_com_t *h = btc->hal; + struct btc_wl_info *wl = &btc->cx.wl; + struct btc_dm *dm = &btc->dm; + struct btc_ops *ops = btc->ops; + u8 buf[256] = {0}; + u8 sz = 0, n = 0; + + if (!ops || !ops->fw_cmd || type >= CXDRVINFO_MAX) + return; + + switch (type) { + case CXDRVINFO_INIT: + n = sizeof(dm->init_info); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_INIT; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &dm->init_info, n); + break; + case CXDRVINFO_ROLE: + n = sizeof(wl->role_info); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_ROLE; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &wl->role_info, n); + break; + case CXDRVINFO_CTRL: + n = sizeof(btc->ctrl); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_CTRL; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &btc->ctrl, n); + break; + case CXDRVINFO_RFK: + n = sizeof(wl->rfk_info); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_RFK; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &wl->rfk_info, n); + break; +#if BTC_CX_FW_OFFLOAD + case CXDRVINFO_DBCC: + n = sizeof(wl->dbcc_info); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_DBCC; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &wl->dbcc_info, n); + break; + case CXDRVINFO_SMAP: + n = sizeof(wl->status); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_SMAP; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &wl->status, n); + break; + case CXDRVINFO_RUN: + n = BTC_RSN_MAXLEN; + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_RUN; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], dm->run_reason, n); + break; + case CXDRVINFO_SCAN: + n = sizeof(wl->scan_info); + sz = n + 2; + + if (sz > sizeof(buf)) + return; + + buf[0] = CXDRVINFO_SCAN; + buf[1] = n; + hal_mem_cpy(h, (void *)&buf[2], &wl->scan_info, n); + break; +#endif + default: + return; + } + + ops->fw_cmd(btc, BTFC_SET, SET_DRV_INFO, (u8*)buf, sz); +} + +void hal_btc_fw_set_drv_event(struct btc_t *btc, u8 type) +{ + struct btc_ops *ops = btc->ops; + + if (!ops || !ops->fw_cmd) + return; + + ops->fw_cmd(btc, BTFC_SET, SET_DRV_EVENT, &type, 1); +} + +void hal_btc_fw_set_bt(struct btc_t *btc, u8 type, u16 len, u8* buf) +{ + struct btc_ops *ops = btc->ops; + + if (!ops || !ops->fw_cmd || + (type < SET_BT_WREG_ADDR || type > SET_BT_GOLDEN_RX_RANGE)) + return; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__); + + ops->fw_cmd(btc, BTFC_SET, type, buf, len); +} + +void hal_btc_fw_event(struct btc_t *btc, u8 evt_id, void *data, u32 len) +{ + struct btf_fwinfo *pfwinfo = &btc->fwinfo; + + if (!len || !data) + return; + + switch (evt_id) { + case BTF_EVNT_RPT: + _parse_btc_report(btc, pfwinfo, data, len); + break; + default: + break; + } +} + +#endif diff --git a/phl/hal_g6/btc/halbtc_fw.h b/phl/hal_g6/btc/halbtc_fw.h new file mode 100644 index 0000000..dad3926 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_fw.h @@ -0,0 +1,305 @@ +#ifndef __INC_BTC_FW_H__ +#define __INC_BTC_FW_H__ + +#include "halbtc_fwdef.h" + +#pragma pack(push) +#pragma pack(1) + +struct btc_t; + +struct btf_tlv { + u8 type; + u8 len; + u8 val[1]; +}; + +enum btf_reg_type { + REG_MAC = 0x0, + REG_BB = 0x1, + REG_RF = 0x2, + REG_BT_RF = 0x3, + REG_BT_MODEM = 0x4, + REG_BT_BLUEWIZE = 0x5, + REG_BT_VENDOR = 0x6, + REG_BT_LE = 0x7, + REG_MAX_TYPE +}; + +/* + * h2c_class : 0x10~0x17: BTC + * Please see : struct rtw_g6_h2c_hdr + */ +enum bt_h2c_class { + BTFC_SET = 0x10, /* 0x10~0x17 for BTC */ + BTFC_GET = 0x11, + BTFC_FW_EVENT = 0x12, + BTFC_MAX +}; + +/* ======================================= + * BTFC_SET class 0x10 ->function + */ +enum btf_set { + SET_REPORT_EN = 0x0, + SET_SLOT_TABLE, /* Slot table */ + SET_MREG_TABLE, /* moniter register */ + SET_CX_POLICY, + SET_GPIO_DBG, + SET_DRV_INFO, + SET_DRV_EVENT, + SET_BT_WREG_ADDR, + SET_BT_WREG_VAL, + SET_BT_RREG_ADDR, + SET_BT_WL_CH_INFO, + SET_BT_INFO_REPORT, + SET_BT_IGNORE_WLAN_ACT, + SET_BT_TX_PWR, + SET_BT_LNA_CONSTRAIN, + SET_BT_GOLDEN_RX_RANGE, + SET_BT_PSD_REPORT, + SET_H2C_TEST, + SET_MAX1 +}; + +/* SET_REPORT_EN function 0x0 -> TLV sub-function */ +enum btf_set_report_en { + RPT_EN_TDMA = BIT0, + RPT_EN_CYCLE = BIT1, + RPT_EN_MREG = BIT2, + RPT_EN_BT_VER_INFO = BIT3, /* FW, Coex, Feature*/ + RPT_EN_BT_SCAN_INFO = BIT4, /* BT scan parameter */ + RPT_EN_BT_AFH_MAP = BIT5, /* AFH map H/M/L */ + RPT_EN_BT_DEVICE_INFO = BIT6, /* vendor id, device name, flush-val*/ + RPT_EN_FW_STEP_INFO = BIT7, + RPT_EN_WL_ALL = 0x7, + RPT_EN_BT_ALL = 0x78, + RPT_EN_ALL = 0x7f +}; + +/* SET_SLOT_TABLE function 0x1 -> sub-function */ +struct btf_set_report { + u8 fver; + u32 enable; + u32 para; +}; + +struct btf_set_slot_table { + u8 fver; + u8 tbl_num; + u8 buf[1]; +}; + +/* SET_MREG_TABLE function 0x2 -> sub-function */ +struct btf_set_mon_reg { + u8 fver; + u8 reg_num; + u8 buf[1]; +}; + +/* SET_CX_POLICY function 0x3 -> TLV sub-function */ +enum btf_set_cx_policy { + CXPOLICY_TDMA = 0x0, + CXPOLICY_SLOT = 0x1, + CXPOLICY_TYPE = 0x2, + CXPOLICY_MAX +}; + +/* SET_GPIO_DBG function 0x4 -> TLV sub-function */ +enum { + CXDGPIO_EN_MAP = 0x0, + CXDGPIO_MUX_MAP = 0x1, + CXDGPIO_MAX +}; + +/* SET_DRV_INFO function 0x5 -> TLV sub-function */ +enum { + CXDRVINFO_INIT = 0, /* wl_only, dbcc_en...*/ + CXDRVINFO_ROLE, /* Role */ + CXDRVINFO_DBCC, /* DBCC */ + CXDRVINFO_SMAP, /* status map */ + CXDRVINFO_RFK, /* wl rfk info */ + CXDRVINFO_RUN, /* wl run reason */ + CXDRVINFO_CTRL, /* ctrl info */ + CXDRVINFO_SCAN, /* scan info */ + CXDRVINFO_MAX +}; + +/* SET_DRV_EVENT function 0x6 -> TLV sub-function */ +enum { + CXDRVEVNT_1 = 0x0, + CXDRVEVNT_2 = 0x1, + CXDRVEVNT_MAX +}; + +/* ======================================= + * BTFC_GET class 0x11 ->function + */ +enum btf_get { + GET_BT_REG, + GET_MAX +}; + +/* ======================================= + * BTFC_FW_EVENT class 0x12 ->function + */ +enum btf_fw_event { + BTF_EVNT_RPT = 0, + BTF_EVNT_BT_INFO = 1, + BTF_EVNT_BT_SCBD = 2, + BTF_EVNT_BT_REG = 3, + BTF_EVNT_CX_RUNINFO = 4, + BTF_EVNT_BT_PSD = 5, + BTF_EVNT_BUF_OVERFLOW, + BTF_EVNT_C2H_LOOPBACK, + BTF_EVNT_MAX +}; + +struct btf_event { + u8 event; + u8 reserved; + u16 length; + u8 buf[1]; +}; + +/* BTF_EVNT_RPT function 0x0 -> TLV type */ +enum btf_fw_event_report { + BTC_RPT_TYPE_CTRL = 0x0, + BTC_RPT_TYPE_TDMA, + BTC_RPT_TYPE_SLOT, + BTC_RPT_TYPE_CYSTA, + BTC_RPT_TYPE_STEP, + BTC_RPT_TYPE_NULLSTA, + BTC_RPT_TYPE_MREG, + BTC_RPT_TYPE_GPIO_DBG, + BTC_RPT_TYPE_BT_VER, + BTC_RPT_TYPE_BT_SCAN, + BTC_RPT_TYPE_BT_AFH, + BTC_RPT_TYPE_BT_DEVICE, + BTC_RPT_TYPE_TEST, + BTC_RPT_TYPE_MAX = 31 +}; + +struct btc_rpt_cmn_info { + u32 rx_cnt; + u32 rx_len; + u32 req_len; /* expected rsp len */ + u8 req_fver; /* expected rsp fver */ + u8 rsp_fver; /* fver from fw */ + u8 valid; +}; + +#pragma pack(pop) + +struct btc_report_ctrl_state { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_rpt_ctrl finfo; /* info from fw */ +}; + +struct btc_fbtc_tdma { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_1tdma finfo; /* info from fw */ +}; + +struct btc_fbtc_slots { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_slots finfo; /* info from fw */ +}; + +struct btc_fbtc_cysta { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_cysta finfo; /* info from fw */ +}; + +struct btc_fbtc_step { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_steps finfo; /* info from fw */ +}; + +struct btc_fbtc_nullsta { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_cynullsta finfo; /* info from fw */ +}; + +struct btc_fbtc_mreg { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_mreg_val finfo; /* info from fw */ +}; + +struct btc_fbtc_gpio_dbg { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_gpio_dbg finfo; /* info from fw */ +}; + +struct btc_fbtc_btver { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_btver finfo; /* info from fw */ +}; + +struct btc_fbtc_btscan { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_btscan finfo; /* info from fw */ +}; + +struct btc_fbtc_btafh { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_btafh finfo; /* info from fw */ +}; + +struct btc_fbtc_btdev { + struct btc_rpt_cmn_info cinfo; /* common info, by driver */ + struct fbtc_btdevinfo finfo; /* info from fw */ +}; + +enum { + BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ + BTFRE_UNDEF_TYPE, + BTFRE_EXCEPTION, + BTFRE_MAX +}; + +struct btf_fwinfo { + u32 cnt_c2h; /* total c2h cnt */ + u32 cnt_h2c; /* total h2c cnt */ + u32 cnt_h2c_fail; /* total h2c fail cnt */ + u32 event[BTF_EVNT_MAX]; /* event statistics */ + + u32 err[BTFRE_MAX]; /* counters for statistics */ + u32 len_mismch; /* req/rsp length mis match */ + u32 fver_mismch; /* req/rsp fver mis match */ + u32 rpt_en_map; + + struct btc_report_ctrl_state rpt_ctrl; + struct btc_fbtc_tdma rpt_fbtc_tdma; + struct btc_fbtc_slots rpt_fbtc_slots; + struct btc_fbtc_cysta rpt_fbtc_cysta; + struct btc_fbtc_step rpt_fbtc_step; + struct btc_fbtc_nullsta rpt_fbtc_nullsta; + struct btc_fbtc_mreg rpt_fbtc_mregval; + struct btc_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; + struct btc_fbtc_btver rpt_fbtc_btver; + struct btc_fbtc_btscan rpt_fbtc_btscan; + struct btc_fbtc_btafh rpt_fbtc_btafh; + struct btc_fbtc_btdev rpt_fbtc_btdev; +}; + +/* + * extern functions + */ + +void _chk_btc_err(struct btc_t *btc, u8 type, u32 cnt); +void hal_btc_fw_event(struct btc_t *btc, u8 evt_id, void *data, u32 len); +void hal_btc_fw_en_rpt(struct btc_t *btc, u32 rpt_map, u32 rpt_state); +void hal_btc_fw_set_slots(struct btc_t *btc, u8 num, struct fbtc_slot *s); +void hal_btc_fw_set_monreg(struct btc_t *btc); +bool hal_btc_fw_set_1tdma(struct btc_t *btc, u16 len, u8 *buf); +bool hal_btc_fw_set_1slot(struct btc_t *btc, u16 len, u8 *buf); +bool hal_btc_fw_set_policy(struct btc_t *btc, bool force_exec, u16 policy_type, + const char* action); +void hal_btc_fw_set_gpio_dbg(struct btc_t *btc, u8 type, u32 val); +void hal_btc_fw_set_drv_info(struct btc_t *btc, u8 type); +void hal_btc_fw_set_bt(struct btc_t *btc, u8 type, u16 len, u8* buf); +void hal_btc_fw_set_drv_event(struct btc_t *btc, u8 type); +void hal_btc_notify_ps_tdma(struct btc_t *btc, bool tdma_start); + +#endif /* __INC_BTC_FW_H__ */ diff --git a/phl/hal_g6/btc/halbtc_fwdef.h b/phl/hal_g6/btc/halbtc_fwdef.h new file mode 100644 index 0000000..51bbc54 --- /dev/null +++ b/phl/hal_g6/btc/halbtc_fwdef.h @@ -0,0 +1,420 @@ +#ifndef __INC_BTC_FW_DEF_H__ +#define __INC_BTC_FW_DEF_H__ + +#pragma pack(push) +#pragma pack(1) +/* + * shared FW Definition + */ + +#define CXMREG_MAX 30 +#define FCXDEF_STEP 50 /* MUST fw_step size*/ +#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ + +enum btc_bt_rfk_counter { + BTC_BCNT_RFK_REQ = 0, + BTC_BCNT_RFK_GO = 1, + BTC_BCNT_RFK_REJECT = 2, + BTC_BCNT_RFK_FAIL = 3, + BTC_BCNT_RFK_TIMEOUT = 4, + BTC_BCNT_RFK_MAX +}; + +struct btc_rpt_ctrl_wl_fw_info { + u32 cx_ver; /* match which driver's coex version */ + u32 cx_offload; + u32 fw_ver; +}; + +struct btc_rpt_ctrl_info { + u32 cnt; /* fw report counter */ + u32 en; /* report map */ + u32 para; /* not used */ + + u32 cnt_c2h; /* fw send c2h counter */ + u32 cnt_h2c; /* fw recv h2c counter */ + u32 len_c2h; /* The total length of the last C2H */ +}; + +struct btc_rpt_ctrl_a2dp_empty { + u32 cnt_empty; /* a2dp empty count */ + u32 cnt_flowctrl; /* a2dp empty flow control counter */ + u32 cnt_tx; + u32 cnt_ack; + u32 cnt_nack; +}; + +struct btc_rpt_ctrl_bt_mailbox { + u32 cnt_send_ok; /* fw send mailbox ok counter */ + u32 cnt_send_fail; /* fw send mailbox fail counter */ + u32 cnt_recv; /* fw recv mailbox counter */ + struct btc_rpt_ctrl_a2dp_empty a2dp; +}; + +#define FCX_BTCRPT_VER 2 +struct fbtc_rpt_ctrl { + u8 fver; + u8 rsvd; + u16 rsvd1; + struct btc_rpt_ctrl_info rpt_info; + struct btc_rpt_ctrl_wl_fw_info wl_fw_info; + struct btc_rpt_ctrl_bt_mailbox bt_mbx_info; + u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; +}; + +/* + * ============== TDMA related ============== + */ +enum fbtc_tdma_template { + CXTD_OFF = 0x0, + CXTD_OFF_B2, + CXTD_OFF_EXT, + CXTD_FIX, + CXTD_PFIX, + CXTD_AUTO, + CXTD_PAUTO, + CXTD_AUTO2, + CXTD_PAUTO2, + CXTD_MAX +}; + +enum fbtc_tdma_type { + CXTDMA_OFF = 0x0, /* tdma off */ + CXTDMA_FIX = 0x1, /* fixed slot */ + CXTDMA_AUTO = 0x2, /* auto slot */ + CXTDMA_AUTO2 = 0x3, /* extended auto slot */ + CXTDMA_MAX +}; + +enum fbtc_tdma_rx_flow_ctrl { + CXFLC_OFF = 0x0, /* rx flow off */ + CXFLC_NULLP = 0x1, /* Null/Null-P */ + CXFLC_QOSNULL = 0x2, /* QOS Null/Null-P */ + CXFLC_CTS = 0x3, /* CTS to Self control */ + CXFLC_MAX +}; + +enum fbtc_tdma_wlan_tx_pause { + CXTPS_OFF = 0x0, /* no wl tx pause*/ + CXTPS_ON = 0x1, + CXTPS_MAX +}; + +/* define if ext-ctrl-slot allowed while TDMA off */ +enum fbtc_ext_ctrl_type { + CXECTL_OFF = 0x0, /* tdma off */ + CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ + CXECTL_EXT = 0x2, + CXECTL_MAX +}; + +union fbtc_rxflct { + u8 val; + u8 type: 3; + u8 tgln_n: 5; +}; + +#define FCX_TDMA_VER 2 +struct fbtc_tdma { + u8 type; /* refer to fbtc_tdma_type*/ + u8 rxflctrl; /* refer to fbtc_tdma_rx_flow_ctrl */ + u8 txflctrl; /* If WL stop Tx while enter BT-slot */ + u8 wtgle_n; /* wl slot toggle every toggle_n cycles */ + u8 leak_n; /* every leak_n cycle do leak detection */ + u8 ext_ctrl; /* refer to fbtc_ext_ctrl_type*/ + /* send rxflctrl to which role + * enum role_type, default: 0 for single-role + * if multi-role: [7:4] second-role, [3:0] fisrt-role + */ + u8 rxflctrl_role; + u8 rsvd; +}; + +struct fbtc_1tdma { + u8 fver; + u8 rsvd; + u16 rsvd1; + struct fbtc_tdma tdma; +}; + + +/* + * ============== SLOT related ============== + */ + enum { /* slot */ + CXST_OFF = 0x0, + CXST_B2W = 0x1, + CXST_W1 = 0x2, + CXST_W2 = 0x3, + CXST_W2B = 0x4, + CXST_B1 = 0x5, + CXST_B2 = 0x6, + CXST_B3 = 0x7, + CXST_B4 = 0x8, + CXST_LK = 0x9, + CXST_BLK = 0xa, + CXST_E2G = 0xb, /* for ext-control-slot 2G*/ + CXST_E5G = 0xc, /* for ext-control-slot 5G*/ + CXST_EBT = 0xd, /* for ext-control-slot BT*/ + CXST_ENULL = 0xe, /* for ext-control-slot Null*/ + CXST_WLK = 0xf, /* for WL link slot */ + CXST_W1FDD = 0x10, + CXST_B1FDD = 0x11, + CXST_MAX = 0x12 /* The max slot must be even*/ +}; + +enum { + CXEVNT_TDMA_ENTRY = 0x0, + CXEVNT_WL_TMR, + CXEVNT_B1_TMR, + CXEVNT_B2_TMR, + CXEVNT_B3_TMR, + CXEVNT_B4_TMR, + CXEVNT_W2B_TMR, + CXEVNT_B2W_TMR, + CXEVNT_BCN_EARLY, + CXEVNT_A2DP_EMPTY, + CXEVNT_LK_END, + CXEVNT_RX_ISR, + CXEVNT_RX_FC0, + CXEVNT_RX_FC1, + CXEVNT_BT_RELINK, + CXEVNT_BT_RETRY, + CXEVNT_E2G, + CXEVNT_E5G, + CXEVNT_EBT, + CXEVNT_ENULL, + CXEVNT_DRV_WLK, + CXEVNT_BCN_OK, + CXEVNT_BT_CHANGE, + CXEVNT_EBT_EXTEND, + CXEVNT_E2G_NULL1, + CXEVNT_MAX +}; + +enum { + CXBCN_ALL = 0x0, + CXBCN_ALL_OK, + CXBCN_BT_SLOT, + CXBCN_BT_OK, + CXBCN_MAX +}; + +/* Slot isolation Definition + * Same definition as WL RX Definition + */ +enum { + SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ + SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ + CXSTYPE_MAX +}; + +enum { /* TIME */ + CXT_BT = 0x0, + CXT_WL = 0x1, + CXT_MAX +}; + +enum { /* TIME-A2DP */ + CXT_FLCTRL_OFF = 0x0, + CXT_FLCTRL_ON = 0x1, + CXT_FLCTRL_MAX +}; + +enum { /* STEP TYPE */ + CXSTEP_NONE = 0x0, + CXSTEP_EVNT = 0x1, + CXSTEP_SLOT = 0x2, + CXSTEP_MAX +}; + +enum { + CXNULL_STATE_0 = 0, + CXNULL_STATE_1 = 1, + CXNULL_STATE_MAX = 2 +}; + +enum { + CXNULL_FAIL = 0, + CXNULL_OK = 1, + CXNULL_LATE = 2, + CXNULL_RETRY = 3, + CXNULL_TX = 4, + CXNULL_MAX = 5 +}; + +struct fbtc_set_drvinfo { + u8 type; + u8 len; + u8 buf[1]; +}; + +#define FCX_GPIODBG_VER 1 +#define BTC_DBG_MAX1 32 +struct fbtc_gpio_dbg { + u8 fver; + u8 rsvd; + u16 rsvd2; + u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ + u32 pre_state; /* the debug signal is 1 or 0 */ + u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position mapping */ +}; + +#define FCX_MREG_VER 1 +struct fbtc_mreg_val { + u8 fver; + u8 reg_num; + u16 rsvd; + u32 mreg_val[CXMREG_MAX]; +}; + +struct fbtc_mreg { + u16 type; + u16 bytes; + u32 offset; +}; + +#define FCX_SLOT_VER 1 +struct fbtc_slot { + u16 dur; /* slot duration */ + u32 cxtbl; + u16 cxtype; +}; + +struct fbtc_1slot { + u8 fver; + u8 sid; /* slot id */ + struct fbtc_slot slot; +}; + +struct fbtc_slots { + u8 fver; + u8 tbl_num; + u16 rsvd; + u32 update_map; + struct fbtc_slot slot[CXST_MAX]; +}; + +#define FCX_STEP_VER 3 +struct fbtc_step { + u8 type; + u8 val; + u16 difft; +}; + +struct fbtc_steps { + u8 fver; + u8 en; + u16 rsvd; + u32 cnt; + struct fbtc_step step[FCXDEF_STEP]; +}; + +#define FCX_CYSTA_VER 3 +struct fbtc_fdd_try_info { + u16 cycles[CXT_FLCTRL_MAX]; + u16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ + u16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ +}; + +struct fbtc_cycle_time_info { + u16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ + u16 tmax[CXT_MAX]; /* max wl/bt cycle time */ + u16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ +}; + +struct fbtc_a2dp_trx_stat { + u8 empty_cnt; + u8 retry_cnt; + u8 tx_rate; + u8 tx_cnt; + u8 ack_cnt; + u8 nack_cnt; + u8 rsvd1; + u8 rsvd2; +}; + +struct fbtc_cycle_a2dp_empty_info { + u16 cnt; /* a2dp empty cnt */ + u16 cnt_timeout; /* a2dp empty timeout cnt*/ + u16 tavg; /* avg a2dp empty time */ + u16 tmax; /* max a2dp empty time */ +}; + +struct fbtc_cycle_leak_info { + u32 cnt_rximr; /* the rximr occur at leak slot */ + u16 tavg; /* avg leak-slot time */ + u16 tamx; /* max leak-slot time */ +}; + +struct fbtc_cysta { /* statistics for cycles */ + u8 fver; + u8 rsvd; + u16 cycles; /* total cycle number */ + u16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /*record the wl/bt slot time, max_step = BTC_CYCLE_SLOT_MAX */ + struct fbtc_cycle_time_info cycle_time; + struct fbtc_fdd_try_info fdd_try; + struct fbtc_cycle_a2dp_empty_info a2dp_ept; + struct fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; + struct fbtc_cycle_leak_info leak_slot; + u32 slot_cnt[CXST_MAX]; /* slot count */ + u32 bcn_cnt[CXBCN_MAX]; + u32 collision_cnt; /* counter for event/timer occur at the same time */ + u32 skip_cnt; + u32 except_cnt; + u32 except_map; +}; + +#define FCX_NULLSTA_VER 2 +struct fbtc_cynullsta { /* cycle null statistics */ + u8 fver; + u8 rsvd; + u16 rsvd2; + u32 tmax[CXNULL_STATE_MAX]; /* max_t for 0:null0/1:null1 */ + u32 tavg[CXNULL_STATE_MAX]; /* avg_t for 0:null0/1:null1 */ + u32 result[CXNULL_STATE_MAX][CXNULL_MAX]; /* result for null , 0:fail, 1:ok, 2:late, 3:retry */ +}; + +#define FCX_BTVER_VER 1 +struct fbtc_btver { + u8 fver; + u8 rsvd; + u16 rsvd2; + u32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ + u32 fw_ver; + u32 feature; +}; + +#define FCX_BTSCAN_VER 1 +struct fbtc_btscan { + u8 fver; + u8 rsvd; + u16 rsvd2; + u8 scan[6]; +}; + +#define FCX_BTAFH_VER 1 +struct fbtc_btafh { + u8 fver; + u8 rsvd; + u16 rsvd2; + u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ + u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ + u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ +}; + +#define FCX_BTDEVINFO_VER 1 +struct fbtc_btdevinfo { + u8 fver; + u8 rsvd; + u16 vendor_id; + u32 dev_name; /* only 24 bits valid */ + u32 flush_time; +}; + +/* + * End of FW Definition + */ +#pragma pack(pop) + +#endif /* __INC_BTC_FW_DEF_H__ */ diff --git a/phl/hal_g6/efuse/hal_efuse.c b/phl/hal_g6/efuse/hal_efuse.c new file mode 100644 index 0000000..737cc4b --- /dev/null +++ b/phl/hal_g6/efuse/hal_efuse.c @@ -0,0 +1,1393 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* +The purpose of hal_efuse.c + +Provide efuse operations. +a. efuse init function +b. efuse shadow map read/write/update +c. efuse information query, map size/used bytes... + +*/ + +#define _HAL_EFUSE_C_ +#include "../hal_headers.h" +#include "hal_efuse.h" +#include "hal_efuse_export.h" + +/* WIFI EFUSE API */ +void efuse_shadow_read_one_byte(struct efuse_t *efuse, u16 offset, u8 *value) +{ + *value = efuse->shadow_map[offset]; +} + +void efuse_shadow_read_two_byte(struct efuse_t *efuse, u16 offset, u16 *value) +{ + *value = efuse->shadow_map[offset]; + *value |= efuse->shadow_map[offset+1] << 8; +} + +void efuse_shadow_read_four_byte(struct efuse_t *efuse, u16 offset, u32 *value) +{ + *value = efuse->shadow_map[offset]; + *value |= efuse->shadow_map[offset+1] << 8; + *value |= efuse->shadow_map[offset+2] << 16; + *value |= efuse->shadow_map[offset+3] << 24; +} + +void efuse_shadow_write_one_byte(struct efuse_t *efuse, u16 offset, u16 value) +{ + efuse->shadow_map[offset] = (u8)(value&0x00FF); +} + +void efuse_shadow_write_two_byte(struct efuse_t *efuse, u16 offset, u16 value) +{ + efuse->shadow_map[offset] = (u8)(value&0x00FF); + efuse->shadow_map[offset+1] = (u8)((value&0xFF00) >> 8); +} + +void efuse_shadow_write_four_byte(struct efuse_t *efuse, u16 offset, u32 value) +{ + efuse->shadow_map[offset] = (u8)(value&0x000000FF); + efuse->shadow_map[offset+1] = (u8)((value&0x0000FF00) >> 8); + efuse->shadow_map[offset+2] = (u8)((value&0x00FF0000) >> 16); + efuse->shadow_map[offset+3] = (u8)((value&0xFF000000) >> 24); +} + +u32 efuse_check_autoload(struct efuse_t *efuse) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_check_efuse_autoload(efuse->hal_com, + &efuse->is_map_valid); + if (efuse->is_map_valid != true) + efuse->map_from_status = DEFAULT_MAP; + + return hal_status; +} + +u32 efuse_hidden_handle(struct efuse_t *efuse) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_read_hidden_rpt(efuse->hal_com); + + return hal_status; +} + +enum rtw_hal_status efuse_set_hw_cap(struct efuse_t *efuse) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = efuse->hal_com; + u8 pkg_type = 0xFF; + u8 rfe_type = 0xFF; + u8 xcap = 0xFF; + u8 domain = 0xFF; + u8 rf_board_opt = 0xFF; + + status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_PKG_TYPE, &pkg_type, + sizeof(pkg_type)); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("%s: Get pkg type fail! Status(%x)\n", __FUNCTION__, status); + } + + status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_RFE, &rfe_type, + sizeof(rfe_type)); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("%s: Get rfe type fail! Status(%x)\n", __FUNCTION__, status); + } + + status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_XTAL, &xcap, + sizeof(xcap)); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("%s: Get xcap fail! Status(%x)\n", __FUNCTION__, status); + } + + status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_CHAN_PLAN, &domain, + sizeof(domain)); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("%s: Get domain fail! Status(%x)\n", __FUNCTION__, status); + } + + status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_BOARD_OPTION, &rf_board_opt, + sizeof(rf_board_opt)); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("%s: Get domain fail! Status(%x)\n", __FUNCTION__, status); + } + + hal_com->dev_hw_cap.pkg_type = pkg_type; + hal_com->dev_hw_cap.rfe_type = rfe_type; + hal_com->dev_hw_cap.xcap = xcap; + hal_com->dev_hw_cap.domain = domain; + hal_com->dev_hw_cap.rf_board_opt = rf_board_opt; + + return status; +} + +enum rtw_hal_status rtw_efuse_logicmap_buf_load(void *efuse, u8* buf, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com, + buf, + is_limit); + return status; +} + +enum rtw_hal_status rtw_efuse_shadow_load(void *efuse, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com, + efuse_info->shadow_map, + is_limit); + + if (efuse_info->is_map_valid == true && status == RTW_HAL_STATUS_SUCCESS) + efuse_info->map_from_status = HW_LOG_MAP; + + return status; +} + +enum rtw_hal_status rtw_efuse_shadow_file_load(void *efuse, char *ic_name, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + +#ifdef CONFIG_EFUSE_CONFIG_FILE + struct efuse_t *efuse_info = efuse; + + if (efuse_info->is_map_valid != true || + rtw_hal_rf_check_efuse_data(efuse_info->hal_com, HW_PHY_0) != true) { + + if (rtw_hal_efuse_shadow_file_load(efuse_info->hal_com , + ic_name, is_limit) == RTW_HAL_STATUS_SUCCESS) { + + if (rtw_hal_rf_check_efuse_data(efuse_info->hal_com, HW_PHY_0) == true) { + efuse_info->is_map_valid = true; + PHL_INFO(" %s() hal_rf check file efuse is_map_valid.\n", __FUNCTION__); + } else { + status = RTW_HAL_STATUS_FAILURE; + PHL_WARN(" %s() efuse Power invalid !\n", __FUNCTION__); + } + } else { + PHL_WARN("%s: efuse shadow_file_load fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_FAILURE; + } + } +#endif + return status; +} + +enum rtw_hal_status rtw_efuse_shadow_update(void *efuse, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + enum rtw_hal_status reload_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 map_size = 0, mask_size = 0; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + /* Load efuse mask file before PG */ + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MASK_FILE_LOADED) == false) { + PHL_WARN("%s: efuse mask not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + goto exit; + } + + /* + * If driver does not load external map file, + * assign the map version with the mask version for the version check. + */ + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MAP_FILE_LOADED) == false) { + _os_mem_cpy(efuse_info->hal_com->drv_priv, efuse_info->map_version, + efuse_info->mask_version, efuse_info->version_len); + } + + if(is_limit) { + map_size = efuse_info->limit_efuse_size; + mask_size = efuse_info->limit_mask_size; + } + else { + map_size = efuse_info->log_efuse_size; + mask_size = efuse_info->mask_size; + } + + status = rtw_hal_mac_write_log_efuse_map(efuse_info->hal_com, + efuse_info->shadow_map, + map_size, + efuse_info->mask, + mask_size, + efuse_info->map_version, + efuse_info->mask_version, + efuse_info->version_len, + 0, + is_limit); + + if(status != RTW_HAL_STATUS_SUCCESS) + PHL_WARN("%s: PG Fail!\n", __FUNCTION__); + + /* Reload shadow map after PG */ + reload_status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com, + efuse_info->shadow_map, + is_limit); + if(reload_status != RTW_HAL_STATUS_SUCCESS) + PHL_WARN("%s: Reload shadow map Fail!\n", __FUNCTION__); + + /* + * Clear the load external map file flag and map version + * after reloading the map. + */ + if(TEST_STATUS_FLAG(efuse_info->status, + EFUSE_STATUS_MAP_FILE_LOADED) == true) { + CLEAR_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MAP_FILE_LOADED); + } + + _os_mem_set(efuse_info->hal_com->drv_priv, + efuse_info->map_version, + 0, + efuse_info->version_len); +exit: + return status; +} + +enum rtw_hal_status +rtw_efuse_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value, + bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 efuse_size = 0; + + if(is_limit) + efuse_size = efuse_info->limit_efuse_size; + else + efuse_size = efuse_info->log_efuse_size; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + if((u32)(offset+byte_count) > efuse_size) { + PHL_WARN("%s: Invalid offset!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + goto exit; + } + + if (byte_count == 1) + efuse_shadow_read_one_byte(efuse_info, offset, (u8 *)value); + else if (byte_count == 2) + efuse_shadow_read_two_byte(efuse_info, offset, (u16 *)value); + else if (byte_count == 4) + efuse_shadow_read_four_byte(efuse_info, offset, (u32 *)value); + + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + +enum rtw_hal_status +rtw_efuse_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value, + bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 efuse_size = 0; + + if(is_limit) + efuse_size = efuse_info->limit_efuse_size; + else + efuse_size = efuse_info->log_efuse_size; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + if((u32)(offset+byte_count) > efuse_size) { + PHL_WARN("%s: Invalid offset!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + goto exit; + } + + if (byte_count == 1) + efuse_shadow_write_one_byte(efuse_info, offset, (u8)value); + else if (byte_count == 2) + efuse_shadow_write_two_byte(efuse_info, offset, (u16)value); + else if (byte_count == 4) + efuse_shadow_write_four_byte(efuse_info, offset, (u32)value); + + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + + +/* + * This API is used for original mp dll command. + * usage = used percentage(1 Byte) + used bytes(2 Bytes) + */ +enum rtw_hal_status rtw_efuse_get_usage(void *efuse, u32 *usage) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 avl_size = 0; + u16 used_byte = 0; + u32 total_size = 0; + u8 used_percentage = 0; + + status = rtw_hal_mac_get_efuse_avl(efuse_info->hal_com, &avl_size); + status = rtw_hal_mac_get_efuse_size(efuse_info->hal_com, &total_size); + + if(total_size != 0){ + used_byte = (u16)(total_size - avl_size); + used_percentage = (u8)(used_byte*100/total_size); + *usage = (used_percentage<<16)|(used_byte); + } + + return status; +} + +enum rtw_hal_status rtw_efuse_shadow2buf(void *efuse, u8 *destbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct efuse_t *efuse_info = efuse; + + _os_mem_cpy(efuse_info->hal_com->drv_priv, (void *)destbuf, + (void *)efuse_info->shadow_map , buflen); + + return status; +} + +enum rtw_hal_status +efuse_map_buf2shadow(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->shadow_map, + (void *)srcbuf, buflen); + SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_MAP_FILE_LOADED); + + return status; +} + +enum rtw_hal_status +efuse_file_map2version(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->map_version, + (void *)srcbuf, buflen); + debug_dump_data(efuse->map_version, efuse->version_len, + "[HAL EFUSE] map version ="); + + return status; +} + +enum rtw_hal_status +efuse_file_mask2buf(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->mask, (void *)srcbuf, + buflen); + SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_MASK_FILE_LOADED); + status = RTW_HAL_STATUS_SUCCESS; + + debug_dump_data(efuse->mask, efuse->mask_size, "[HAL EFUSE] mask data ="); + + return status; +} + +enum rtw_hal_status +efuse_file_mask2version(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + if (buflen <= efuse->version_len) { + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->mask_version, + (void *)srcbuf, buflen); + debug_dump_data(efuse->mask_version, efuse->version_len, + "[HAL EFUSE] mask ver ="); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + +static u16 efuse_file_open(void *d, char *filepath, u8 *buf, u32 buflen) +{ + char *ptmpbuf = NULL, *ptr; + u32 bufsize = 5120; + u8 val8 = 0; + u32 file_size = 0, i = 0, j= 0, tmp = 0; + int err = 0; + + ptmpbuf = _os_mem_alloc(d, bufsize); + if (ptmpbuf == NULL) { + PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__); + return 0; + } + + file_size = _os_read_file(filepath, (u8*)ptmpbuf, bufsize); + if (file_size > 0) { + if (file_size <= 90) { + _os_mem_free(d, (void*)ptmpbuf, bufsize); + PHL_INFO("%s, filepatch %s, size=%d not over 90, FAIL!!\n", + __FUNCTION__, filepath, file_size); + return 0; + } + i = 0; + j = 0; + ptr = ptmpbuf; + while ((j < buflen) && (i < file_size)) { + if (ptmpbuf[i] == '\0') + break; + ptr = _os_strpbrk((char *)&ptmpbuf[i], " \t\n\r"); + if (ptr) { + if (ptr == &ptmpbuf[i]) { + i++; + continue; + } + /* Add string terminating null */ + *ptr = 0; + } else { + ptr = &ptmpbuf[file_size-1]; + } + + err = _os_sscanf((char *)&ptmpbuf[i], "%x", &tmp); + + if (err != 1) { + PHL_INFO("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]); + } else { + val8 = (u8)tmp; + buf[j] = val8; + PHL_INFO("i=%d, j=%d, 0x%02x\n", i, j, buf[j]); + j++; + } + i = (u32)(ptr - ptmpbuf + 1); + } + } + if (ptmpbuf) + _os_mem_free(d, (void*)ptmpbuf, bufsize); + PHL_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepath, file_size); + return (u16)j; +} + +enum rtw_hal_status +rtw_efuse_file_map_load(void *efuse, char *file_path, u8 is_limit) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + void *d = efuse_info->hal_com->drv_priv; + u8 *mapbuf = NULL; + u16 data_len = 0; + u32 map_sz = 0, full_map_sz = 0; + + if (is_limit) + map_sz = efuse_info->limit_efuse_size; + else + map_sz = efuse_info->log_efuse_size; + + if (map_sz == 0) { + map_sz = MAX_EFUSE_MAP_LEN; + full_map_sz = MAX_EFUSE_MAP_LEN + MAX_EFUSE_FILE_VERSION_LENGTH; + } else + full_map_sz = map_sz + efuse_info->version_len; + + if (file_path && full_map_sz != 0) { + mapbuf= _os_mem_alloc(d, full_map_sz); + if (mapbuf == NULL) { + PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__); + goto exit; + } + _os_mem_set(d, mapbuf, 0xFF, full_map_sz); + + data_len = efuse_file_open(d, file_path, mapbuf, full_map_sz); + + if ((data_len > map_sz) && (data_len <= full_map_sz)) { + efuse_file_map2version(efuse_info, mapbuf + map_sz, + efuse_info->version_len); + + if (data_len > map_sz) + data_len -= efuse_info->version_len; + + PHL_INFO("%s , File eFuse map to shadow len %d\n", __FUNCTION__, data_len); + hal_status = efuse_map_buf2shadow(efuse_info, mapbuf, data_len); + efuse_info->map_from_status = FILE_MAP; + } else { + PHL_INFO("Error No Map Version !, File Map Data Len %d not over 1536.\n", data_len); + goto exit; + } + } +exit: + if (mapbuf) + _os_mem_free(d, (void*)mapbuf, full_map_sz); + + return hal_status; +} + +enum rtw_hal_status +rtw_efuse_file_mask_load(void *efuse, char *file_path, u8 is_limit) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + void *d = efuse_info->hal_com->drv_priv; + u8 *maskbuf = NULL; + u16 data_len = 0; + u32 mask_sz = 0, full_mask_sz = 0; + + if (is_limit) + mask_sz = efuse_info->limit_mask_size; + else + mask_sz = efuse_info->mask_size; + + if (mask_sz == 0) { + mask_sz = EFUSE_MASK_FILE_LEN; + full_mask_sz = EFUSE_MASK_FILE_LEN + MAX_EFUSE_FILE_VERSION_LENGTH; + } else + full_mask_sz = mask_sz + efuse_info->version_len; + + if (file_path) { + maskbuf= _os_mem_alloc(d, full_mask_sz); + if (maskbuf == NULL) { + PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__); + goto exit; + } + _os_mem_set(d, maskbuf, 0xFF, full_mask_sz); + + data_len = efuse_file_open(d, file_path, maskbuf, full_mask_sz); + + if ((data_len > mask_sz) && (data_len <= full_mask_sz)) { + efuse_file_mask2version(efuse_info, maskbuf + mask_sz, + efuse_info->version_len); + + if (data_len > mask_sz) + data_len -= efuse_info->version_len; + + PHL_INFO("Mask File data 2 buf len %d\n", data_len); + hal_status = efuse_file_mask2buf(efuse_info, maskbuf, data_len); + + } else { + PHL_INFO("Error No Map Version !, File Map Data Len %d not over 102.\n", data_len); + goto exit; + } + } +exit: + if (maskbuf) + _os_mem_free(d, (void*)maskbuf, full_mask_sz); + + return hal_status; +} + +enum rtw_hal_status rtw_efuse_get_logical_size(void *efuse, u32 *size, + bool is_limited) +{ + struct efuse_t *efuse_info = efuse; + + if(is_limited == true) + *size = efuse_info->limit_efuse_size; + else + *size = efuse_info->log_efuse_size; + + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_efuse_get_size(void *efuse, u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_get_efuse_size(efuse_info->hal_com, size); + + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return status; +} + +enum rtw_hal_status rtw_efuse_get_avl(void *efuse, u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_get_efuse_avl(efuse_info->hal_com, size); + + /* [TEMP] Set avl size for testing */ + /* size = 512; */ + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return status; +} + +enum rtw_hal_status rtw_efuse_get_offset_mask(void *efuse, u16 offset, u8 *mask) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) + return RTW_HAL_STATUS_EFUSE_UNINIT; + + if(offset >= efuse_info->limit_mask_size) + return RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + + *mask = efuse_info->mask[offset]; + PHL_INFO("%s: offset = %x mask = %x\n", __FUNCTION__, offset, *mask); + return status; +} + +enum rtw_hal_status rtw_efuse_get_shadowmap_from(void *efuse, u8 *val) +{ + struct efuse_t *efuse_info = efuse; + + *val = efuse_info->map_from_status; + + PHL_INFO("%s:get efuse %s\n", __FUNCTION__, SHADOWMAP_FROM2STR(*val)); + return RTW_HAL_STATUS_SUCCESS; +} + +char* rtw_efuse_get_shadowmap_from_to_str(void *efuse) +{ + struct efuse_t *efuse_info = efuse; + + return SHADOWMAP_FROM2STR(efuse_info->map_from_status); +} + + +enum rtw_hal_status rtw_efuse_get_info(void *efuse, + enum rtw_efuse_info info_type, + void *value, + u8 size) +{ + struct efuse_t *efuse_info = efuse; + struct rtw_hal_com_t *hal_com = efuse_info->hal_com; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) + return RTW_HAL_STATUS_EFUSE_UNINIT; + + if(info_type <= EFUSE_INFO_MAC_MAX) + hal_status = rtw_hal_mac_get_efuse_info(hal_com, + efuse_info->shadow_map, + info_type, + value, + size, + efuse_info->is_map_valid); + else if (info_type <= EFUSE_INFO_BB_MAX) + hal_status = rtw_hal_bb_get_efuse_info(hal_com, + efuse_info->shadow_map, + info_type, + value, + size, + efuse_info->is_map_valid); + else if (info_type <= EFUSE_INFO_RF_MAX) + hal_status = rtw_hal_rf_get_efuse_info(hal_com, + efuse_info->shadow_map, + info_type, + value, + size, + efuse_info->is_map_valid); + else + hal_status = rtw_hal_btc_get_efuse_info(hal_com, + efuse_info->shadow_map, + info_type, + value, + size, + efuse_info->is_map_valid); + + return hal_status; +} + +void rtw_efuse_process(void *efuse, char *ic_name) +{ + struct efuse_t *efuse_info = (struct efuse_t *)efuse; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == true) { + PHL_INFO("%s EFUSE module is already initialized.\n", __FUNCTION__); + return; + } + + efuse_check_autoload(efuse_info); + /* Load wifi full map to shadow map */ + rtw_efuse_shadow_load(efuse_info, false); + + rtw_efuse_shadow_file_load(efuse_info, ic_name, true); + + debug_dump_data(efuse_info->shadow_map, efuse_info->log_efuse_size, + "Logical EFUSE MAP:"); + efuse_hidden_handle(efuse_info); + + SET_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS); + /* + * We can set the hw cap after we got the shadow map. + * The efuse get info API will check the efuse is processed or not. + */ + efuse_set_hw_cap(efuse_info); + + if (RTW_DRV_MODE_EQC == efuse_info->phl_com->drv_mode) { + rtw_hal_rf_get_default_rfe_type(efuse_info->hal_com); + rtw_hal_rf_get_default_xtal(efuse_info->hal_com); + PHL_WARN("%s: Use default RFE type(0x%x) / XTAL(0x%x) configuration for EQC mode\n", + __FUNCTION__, + efuse_info->hal_com->dev_hw_cap.rfe_type, + efuse_info->hal_com->dev_hw_cap.xcap); + } +} + +u32 rtw_efuse_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **efuse) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = NULL; + + efuse_info = _os_mem_alloc(hal_com->drv_priv, sizeof(struct efuse_t)); + + if(efuse_info == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + goto error_efuse_init; + } + + /* Allocate shadow map memory */ + hal_status = rtw_hal_mac_get_log_efuse_size(hal_com, + &(efuse_info->log_efuse_size), + false); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get full logical efuse map size fail!\n",__FUNCTION__); + goto error_efuse_shadow_init; + } + + efuse_info->shadow_map = _os_mem_alloc(hal_com->drv_priv, + efuse_info->log_efuse_size); + + if(efuse_info->shadow_map == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("%s Allocate shadow efuse map fail!\n", __FUNCTION__); + goto error_efuse_shadow_init; + } + + hal_status = rtw_hal_mac_get_log_efuse_size(hal_com, + &(efuse_info->limit_efuse_size), + true); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get limited logical efuse map size fail!\n", __FUNCTION__); + goto error_efuse_shadow_init; + } + + /* Allocate mask memory */ + hal_status = rtw_hal_mac_get_efuse_mask_size(hal_com, + &(efuse_info->mask_size), + false); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get full efuse mask size fail!\n", __FUNCTION__); + goto error_efuse_mask_init; + } + + efuse_info->mask = _os_mem_alloc(hal_com->drv_priv, + efuse_info->mask_size); + + if(efuse_info->mask == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("%s Allocate efuse mask fail!\n", __FUNCTION__); + goto error_efuse_mask_init; + } + + hal_status = rtw_hal_mac_get_efuse_mask_size(hal_com, + &(efuse_info->limit_mask_size), + true); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get limited efuse mask size fail!\n", __FUNCTION__); + goto error_efuse_mask_init; + } + + efuse_info->version_len = rtw_hal_mac_get_efuse_ver_len(hal_com); + + efuse_info->map_version = _os_mem_alloc(hal_com->drv_priv, + efuse_info->version_len); + + if(efuse_info->map_version == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + goto error_map_version_init; + } + + efuse_info->mask_version = _os_mem_alloc(hal_com->drv_priv, + efuse_info->version_len); + if(efuse_info->mask_version == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + goto error_mask_version_init; + } + + /* Allocate bt shadow map memory */ + hal_status = rtw_hal_mac_get_log_efuse_bt_size(hal_com, + &(efuse_info->bt_log_efuse_size)); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get full logical efuse map size fail!\n",__FUNCTION__); + goto error_efuse_bt_shadow_init; + } + + efuse_info->bt_shadow_map = _os_mem_alloc(hal_com->drv_priv, + efuse_info->bt_log_efuse_size); + + if(efuse_info->bt_shadow_map == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("%s Allocate shadow efuse map fail!\n", __FUNCTION__); + goto error_efuse_bt_shadow_init; + } + + /* Allocate mask memory */ + hal_status = rtw_hal_mac_get_efuse_bt_mask_size(hal_com, + &(efuse_info->bt_mask_size)); + + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Get full efuse mask size fail!\n", __FUNCTION__); + goto error_efuse_bt_mask_init; + } + + efuse_info->bt_mask = _os_mem_alloc(hal_com->drv_priv, + efuse_info->bt_mask_size); + + if(efuse_info->bt_mask == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("%s Allocate efuse mask fail!\n", __FUNCTION__); + goto error_efuse_bt_mask_init; + } + + + efuse_info->phl_com = phl_com; + efuse_info->hal_com = hal_com; + + *efuse = efuse_info; + + hal_status = RTW_HAL_STATUS_SUCCESS; + return hal_status; + +error_efuse_bt_mask_init: + _os_mem_free(hal_com->drv_priv, efuse_info->bt_shadow_map, + efuse_info->bt_log_efuse_size); + +error_efuse_bt_shadow_init: + _os_mem_free(hal_com->drv_priv, efuse_info->mask_version, + efuse_info->version_len); + +error_mask_version_init: + _os_mem_free(hal_com->drv_priv, efuse_info->map_version, + efuse_info->version_len); + +error_map_version_init: + _os_mem_free(hal_com->drv_priv, efuse_info->mask, + efuse_info->mask_size); + +error_efuse_mask_init: + _os_mem_free(hal_com->drv_priv, efuse_info->shadow_map, + efuse_info->log_efuse_size); + +error_efuse_shadow_init: + _os_mem_free(hal_com->drv_priv, efuse_info, sizeof(struct efuse_t)); + +error_efuse_init: + return hal_status; +} + +void rtw_efuse_deinit(struct rtw_hal_com_t *hal_com, void *efuse) +{ + struct efuse_t *efuse_info = efuse; + + if(efuse_info->bt_mask) { + _os_mem_free(hal_com->drv_priv, efuse_info->bt_mask, + efuse_info->bt_mask_size); + efuse_info->bt_mask = NULL; + } + + if(efuse_info->bt_shadow_map) { + _os_mem_free(hal_com->drv_priv, efuse_info->bt_shadow_map, + efuse_info->bt_log_efuse_size); + efuse_info->bt_shadow_map = NULL; + } + + if(efuse_info->mask) { + _os_mem_free(hal_com->drv_priv, efuse_info->mask, + efuse_info->mask_size); + efuse_info->mask = NULL; + } + if(efuse_info->map_version) { + _os_mem_free(hal_com->drv_priv, efuse_info->map_version, + efuse_info->version_len); + efuse_info->map_version = NULL; + } + if(efuse_info->mask_version) { + _os_mem_free(hal_com->drv_priv, efuse_info->mask_version, + efuse_info->version_len); + efuse_info->mask_version = NULL; + } + if(efuse_info->shadow_map) { + _os_mem_free(hal_com->drv_priv, efuse_info->shadow_map, + efuse_info->log_efuse_size); + efuse_info->shadow_map = NULL; + } + + if (efuse_info) { + _os_mem_free(hal_com->drv_priv, efuse_info, sizeof(struct efuse_t)); + efuse_info = NULL; + } +} + +/* BT EFUSE API */ +void efuse_bt_shadow_read_one_byte(struct efuse_t *efuse, u16 offset, u8 *value) +{ + *value = efuse->bt_shadow_map[offset]; +} + +void efuse_bt_shadow_read_two_byte(struct efuse_t *efuse, u16 offset, u16 *value) +{ + *value = efuse->bt_shadow_map[offset]; + *value |= efuse->bt_shadow_map[offset+1] << 8; +} + +void efuse_bt_shadow_read_four_byte(struct efuse_t *efuse, u16 offset, u32 *value) +{ + *value = efuse->bt_shadow_map[offset]; + *value |= efuse->bt_shadow_map[offset+1] << 8; + *value |= efuse->bt_shadow_map[offset+2] << 16; + *value |= efuse->bt_shadow_map[offset+3] << 24; +} + +void efuse_bt_shadow_write_one_byte(struct efuse_t *efuse, u16 offset, u16 value) +{ + efuse->bt_shadow_map[offset] = (u8)(value&0x00FF); +} + +void efuse_bt_shadow_write_two_byte(struct efuse_t *efuse, u16 offset, u16 value) +{ + efuse->bt_shadow_map[offset] = (u8)(value&0x00FF); + efuse->bt_shadow_map[offset+1] = (u8)((value&0xFF00) >> 8); +} + +void efuse_bt_shadow_write_four_byte(struct efuse_t *efuse, u16 offset, u32 value) +{ + efuse->bt_shadow_map[offset] = (u8)(value&0x000000FF); + efuse->bt_shadow_map[offset+1] = (u8)((value&0x0000FF00) >> 8); + efuse->bt_shadow_map[offset+2] = (u8)((value&0x00FF0000) >> 16); + efuse->bt_shadow_map[offset+3] = (u8)((value&0xFF000000) >> 24); +} + +enum rtw_hal_status rtw_efuse_bt_shadow_load(void *efuse) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_read_log_efuse_bt_map(efuse_info->hal_com, + efuse_info->bt_shadow_map); + + return status; +} + +enum rtw_hal_status rtw_efuse_bt_shadow_update(void *efuse) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + enum rtw_hal_status reload_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 map_size = 0, mask_size = 0; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + /* Load efuse mask file before PG */ + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_BT_MASK_FILE_LOADED) == false) { + PHL_WARN("%s: efuse mask not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + goto exit; + } + + map_size = efuse_info->bt_log_efuse_size; + mask_size = efuse_info->bt_mask_size; + + status = rtw_hal_mac_write_log_efuse_bt_map(efuse_info->hal_com, + efuse_info->bt_shadow_map, + map_size, + efuse_info->bt_mask, + mask_size); + + if(status != RTW_HAL_STATUS_SUCCESS) + PHL_WARN("%s: BT PG Fail!\n", __FUNCTION__); + + /* Reload shadow map after PG */ + reload_status = rtw_hal_mac_read_log_efuse_bt_map(efuse_info->hal_com, + efuse_info->bt_shadow_map); + if(reload_status != RTW_HAL_STATUS_SUCCESS) + PHL_WARN("%s: Reload bt shadow map Fail!\n", __FUNCTION__); + + /* + * Clear the load external map file flag and map version + * after reloading the map. + */ + if(TEST_STATUS_FLAG(efuse_info->status, + EFUSE_STATUS_BT_MAP_FILE_LOADED) == true) { + CLEAR_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_BT_MAP_FILE_LOADED); + } + +exit: + return status; +} + +enum rtw_hal_status +rtw_efuse_bt_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 efuse_bt_size = 0; + + efuse_bt_size = efuse_info->bt_log_efuse_size; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + if((u32)(offset+byte_count) > efuse_bt_size) { + PHL_WARN("%s: Invalid offset!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + goto exit; + } + + if (byte_count == 1) + efuse_bt_shadow_read_one_byte(efuse_info, offset, (u8 *)value); + else if (byte_count == 2) + efuse_bt_shadow_read_two_byte(efuse_info, offset, (u16 *)value); + else if (byte_count == 4) + efuse_bt_shadow_read_four_byte(efuse_info, offset, (u32 *)value); + + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + +enum rtw_hal_status +rtw_efuse_bt_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 efuse_bt_size = 0; + + efuse_bt_size = efuse_info->bt_log_efuse_size; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) { + PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_UNINIT; + goto exit; + } + + if((u32)(offset+byte_count) > efuse_bt_size) { + PHL_WARN("%s: Invalid offset!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + goto exit; + } + + if (byte_count == 1) + efuse_bt_shadow_write_one_byte(efuse_info, offset, (u8)value); + else if (byte_count == 2) + efuse_bt_shadow_write_two_byte(efuse_info, offset, (u16)value); + else if (byte_count == 4) + efuse_bt_shadow_write_four_byte(efuse_info, offset, (u32)value); + + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + +/* + * This API is used for original mp dll command. + * usage = used percentage(1 Byte) + used bytes(2 Bytes) + */ +enum rtw_hal_status rtw_efuse_bt_get_usage(void *efuse, u32 *usage) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + u32 avl_size = 0; + u16 used_byte = 0; + u32 total_size = 0; + u8 used_percentage = 0; + + status = rtw_hal_mac_get_efuse_bt_avl(efuse_info->hal_com, &avl_size); + status = rtw_hal_mac_get_efuse_bt_size(efuse_info->hal_com, &total_size); + + if(total_size != 0){ + used_byte = (u16)(total_size - avl_size); + used_percentage = (u8)(used_byte*100/total_size); + *usage = (used_percentage<<16)|(used_byte); + } + + return status; +} + +enum rtw_hal_status rtw_efuse_bt_shadow2buf(void *efuse, u8 *destbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct efuse_t *efuse_info = efuse; + + _os_mem_cpy(efuse_info->hal_com->drv_priv, (void *)destbuf, + (void *)efuse_info->bt_shadow_map , buflen); + + return status; +} + +enum rtw_hal_status +efuse_bt_map_buf2shadow(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->bt_shadow_map, + (void *)srcbuf, buflen); + SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_BT_MAP_FILE_LOADED); + status = RTW_HAL_STATUS_SUCCESS; + + return status; +} + +enum rtw_hal_status +efuse_bt_file_mask2buf(struct efuse_t *efuse, u8 *srcbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + _os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->bt_mask, (void *)srcbuf, + buflen); + SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_BT_MASK_FILE_LOADED); + status = RTW_HAL_STATUS_SUCCESS; + + debug_dump_data(efuse->bt_mask, efuse->bt_mask_size, "[HAL EFUSE] bt mask data ="); + + return status; +} + +enum rtw_hal_status +rtw_efuse_bt_file_map_load(void *efuse, char *file_path) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + void *d = efuse_info->hal_com->drv_priv; + u8 *mapbuf = NULL; + u16 data_len = 0; + u32 bt_map_sz = 0; + + bt_map_sz = efuse_info->bt_log_efuse_size; + + if (bt_map_sz == 0) + bt_map_sz = MAX_EFUSE_MAP_LEN; + + if (file_path) { + mapbuf= _os_mem_alloc(d, bt_map_sz); + if (mapbuf == NULL) { + PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__); + goto exit; + } + _os_mem_set(d, mapbuf, 0xFF, bt_map_sz); + + data_len = efuse_file_open(d, file_path, mapbuf, bt_map_sz); + + if (data_len <= bt_map_sz) { + PHL_INFO("%s , File eFuse bt map to shadow len %d\n", __FUNCTION__, data_len); + hal_status = efuse_bt_map_buf2shadow(efuse_info, mapbuf, data_len); + + } else { + PHL_INFO("Error No bt Map Version !, File Map Data Len %d not over 1024.\n", data_len); + goto exit; + } + } +exit: + if (mapbuf) + _os_mem_free(d, (void*)mapbuf, bt_map_sz); + + return hal_status; +} + + +enum rtw_hal_status +rtw_efuse_bt_file_mask_load(void *efuse, char *file_path) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + void *d = efuse_info->hal_com->drv_priv; + u8 *maskbuf = NULL; + u16 data_len = 0; + u32 bt_mask_sz = 0; + + bt_mask_sz = efuse_info->bt_mask_size; + + if (bt_mask_sz == 0) + goto exit; + + if (file_path) { + maskbuf= _os_mem_alloc(d, bt_mask_sz); + if (maskbuf == NULL) { + PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__); + goto exit; + } + _os_mem_set(d, maskbuf, 0xFF, bt_mask_sz); + + data_len = efuse_file_open(d, file_path, maskbuf, bt_mask_sz); + + if (data_len <= bt_mask_sz) { + PHL_INFO("Mask File data 2 buf len %d\n", data_len); + hal_status = efuse_bt_file_mask2buf(efuse_info, maskbuf, data_len); + + } else { + PHL_INFO("Error No Map Version !, File Map Data Len %d not over 96.\n", data_len); + goto exit; + } + } +exit: + if (maskbuf) + _os_mem_free(d, (void*)maskbuf, bt_mask_sz); + + return hal_status; +} + +enum rtw_hal_status rtw_efuse_bt_get_logical_size(void *efuse, u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_get_log_efuse_bt_size(efuse_info->hal_com, size); + + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return status; +} + +enum rtw_hal_status rtw_efuse_bt_get_size(void *efuse, u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_get_efuse_bt_size(efuse_info->hal_com, size); + + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return status; +} + +enum rtw_hal_status rtw_efuse_bt_get_avl(void *efuse, u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_get_efuse_bt_avl(efuse_info->hal_com, size); + + PHL_INFO("%s: size = %d\n", __FUNCTION__, *size); + return status; +} + +enum rtw_hal_status rtw_efuse_bt_get_offset_mask(void *efuse, u16 offset, u8 *mask) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) + return RTW_HAL_STATUS_EFUSE_UNINIT; + + if(offset >= efuse_info->bt_mask_size) + return RTW_HAL_STATUS_EFUSE_IVALID_OFFSET; + + *mask = efuse_info->bt_mask[offset]; + PHL_INFO("%s: bt offset = %x mask = %x\n", __FUNCTION__, offset, *mask); + return status; +} + + +enum rtw_hal_status rtw_efuse_bt_read_hidden(void *efuse, u32 addr, u32 size, u8 *val) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_read_efuse_bt_hidden(efuse_info->hal_com, addr, size, val); + + if(status == RTW_HAL_STATUS_SUCCESS) + { + PHL_INFO("%s: bt hidden read ok!\n", __FUNCTION__); + }else{ + PHL_INFO("%s: bt hidden read fail!\n", __FUNCTION__); + } + + return status; +} + +enum rtw_hal_status rtw_efuse_bt_write_hidden(void *efuse, u32 addr, u8 val) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + status = rtw_hal_mac_write_efuse_bt_hidden(efuse_info->hal_com, addr, val); + + if(status == RTW_HAL_STATUS_SUCCESS) + { + PHL_INFO("%s: bt hidden PG ok!\n", __FUNCTION__); + }else{ + PHL_INFO("%s: bt hidden PG fail!\n", __FUNCTION__); + } + + return status; +} + +enum rtw_hal_status rtw_efuse_read_phy_wifi(void *efuse, u32 addr, u32 size, u8 *data, u8 type) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct efuse_t *efuse_info = efuse; + + if(type == HAL_MP_EFUSE_WIFI) + status = rtw_hal_mac_read_phy_efuse(efuse_info->hal_com, addr, size, data); + else if(type == HAL_MP_EFUSE_BT) + status = rtw_hal_mac_read_bt_phy_efuse(efuse_info->hal_com, addr, size, data); + + if(status == RTW_HAL_STATUS_SUCCESS) + { + PHL_INFO("%s: real raw read ok!\n", __FUNCTION__); + }else{ + PHL_INFO("%s: real raw read fail!\n", __FUNCTION__); + } + + return status; +} + +enum rtw_hal_status rtw_efuse_renew(void *efuse, u8 type) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct efuse_t *efuse_info = efuse; + + if (type == HAL_MP_EFUSE_WIFI) { + rtw_hal_bb_get_efuse_init(efuse_info->hal_com); + rtw_hal_rf_get_efuse_ex(efuse_info->hal_com, HW_PHY_MAX); + PHL_INFO("%s: hal efuse renew done\n", __FUNCTION__); + + } else if (type == HAL_MP_EFUSE_BT) { + PHL_INFO("%s: Not ready\n", __FUNCTION__); + } + + return status; +} diff --git a/phl/hal_g6/efuse/hal_efuse.h b/phl/hal_g6/efuse/hal_efuse.h new file mode 100644 index 0000000..6b8874d --- /dev/null +++ b/phl/hal_g6/efuse/hal_efuse.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_EFUSE_H_ +#define _HAL_EFUSE_H_ + +#define MAX_EFUSE_FILE_VERSION_LENGTH 6 +#define EFUSE_MASK_FILE_LEN 96 +#define MAX_EFUSE_MAP_LEN 1536 + +enum EFUSE_STATUS_FLAGS { + EFUSE_STATUS_PROCESS = BIT0, + EFUSE_STATUS_MAP_FILE_LOADED = BIT1, + EFUSE_STATUS_MASK_FILE_LOADED = BIT2, + EFUSE_STATUS_BT_MAP_FILE_LOADED = BIT3, + EFUSE_STATUS_BT_MASK_FILE_LOADED = BIT4 +}; + +enum EFUSE_SHADOW_MAP_STATUS { + DEFAULT_MAP = 0, + HW_LOG_MAP = 1, + FILE_MAP = 2, + EFUSE_UNKNOWN, +}; + +#define SHADOWMAP_FROM2STR(status)\ +(status == DEFAULT_MAP) ? "DEFAULT" :\ +(status == HW_LOG_MAP) ? "HW_LOG_EFUSE" :\ +(status == FILE_MAP) ? "FILE_EFUSE" :\ +"UNknow" + +/* + * @phl_com + * @hal_com + * @shadow_map: Buffer pointer for limited size logical map + * @mask: Buffer pointer for limited size mask read from mask file + * @map_version: Buffer pointer for map version read from map file + * @mask_version: Buffer pointer for mask version read from mask file + * @log_efuse_size: Limited logical map size + * @mask_size: Limited mask size + * @version_len: Length of verion field in map/mask + * @status: Efuse status + * @is_map_valid: Flag to check autoload status + * @reserved + */ +struct efuse_t { + struct rtw_phl_com_t *phl_com; + struct rtw_hal_com_t *hal_com; + u8 *shadow_map; + u8 *mask; + u8 *map_version; + u8 *mask_version; + u32 log_efuse_size; + u32 mask_size; + u32 limit_efuse_size; + u32 limit_mask_size; + u8 version_len; + u8 status; + u8 is_map_valid; + u8 reserved; + u8 map_from_status; + /* BT*/ + u8 *bt_shadow_map; + u8 *bt_mask; + u32 bt_log_efuse_size; + u32 bt_efuse_size; + u32 bt_mask_size; +}; + +#endif /* _HAL_EFUSE_H_ */ diff --git a/phl/hal_g6/efuse/hal_efuse_export.h b/phl/hal_g6/efuse/hal_efuse_export.h new file mode 100644 index 0000000..98e2919 --- /dev/null +++ b/phl/hal_g6/efuse/hal_efuse_export.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_EFUSE_EXPORT_H_ +#define _HAL_EFUSE_EXPORT_H_ + +enum HAL_EFUSE_CMD_ID { + HAL_EFUSE_HELP, + HAL_EFUSE_WIFI_DUMP_MAP, + HAL_EFUSE_WIFI_LOGIC_DUMP_MAP +}; + +static const struct hal_cmd_info hal_efuse_cmd_i[] = { + {"-h", HAL_EFUSE_HELP}, + {"dump_map", HAL_EFUSE_WIFI_DUMP_MAP}, + {"dump_hw_map", HAL_EFUSE_WIFI_LOGIC_DUMP_MAP}, +}; + +/* efuse exported API */ +u32 +rtw_efuse_init(struct rtw_phl_com_t *phl_com, struct rtw_hal_com_t *hal_com, + void **efuse); + +void rtw_efuse_deinit(struct rtw_hal_com_t *hal_com, void *efuse); + +enum rtw_hal_status +rtw_efuse_get_info(void *efuse, enum rtw_efuse_info info_type, void *value, + u8 size); + +void rtw_efuse_process(void *efuse, char *ic_name); + +enum rtw_hal_status +rtw_efuse_logicmap_buf_load(void *efuse, u8* buf, bool is_limit); + +enum rtw_hal_status +rtw_efuse_shadow_load(void *efuse, bool is_limit); + +enum rtw_hal_status +rtw_efuse_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value, + bool is_limit); + +enum rtw_hal_status +rtw_efuse_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value, + bool is_limit); + +enum rtw_hal_status +rtw_efuse_shadow_update(void *efuse, bool is_limit); + +enum rtw_hal_status +rtw_efuse_shadow2buf(void *efuse, u8 *destbuf, u16 buflen); + +enum rtw_hal_status +rtw_efuse_file_map_load(void *efuse, char *file_path, u8 is_limit); + +enum rtw_hal_status +rtw_efuse_file_mask_load(void *efuse, char *file_path, u8 is_limit); + +enum rtw_hal_status +rtw_efuse_get_usage(void *efuse, u32 *usage); + +enum rtw_hal_status +rtw_efuse_get_logical_size(void *efuse, u32 *size, bool is_limited); + +enum rtw_hal_status +rtw_efuse_get_size(void *efuse, u32 *size); + +enum rtw_hal_status +rtw_efuse_get_avl(void *efuse, u32 *size); + +enum rtw_hal_status +rtw_efuse_get_shadowmap_from(void *efuse, u8 *val); + +char* +rtw_efuse_get_shadowmap_from_to_str(void *efuse); + +enum rtw_hal_status +rtw_efuse_get_offset_mask(void *efuse, u16 offset, u8 *mask); + +/* BT EFUSE */ +enum rtw_hal_status +rtw_efuse_bt_shadow_load(void *efuse); + +enum rtw_hal_status +rtw_efuse_bt_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value); + +enum rtw_hal_status +rtw_efuse_bt_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value); + +enum rtw_hal_status +rtw_efuse_bt_shadow_update(void *efuse); + +enum rtw_hal_status +rtw_efuse_bt_shadow2buf(void *efuse, u8 *destbuf, u16 buflen); + +enum rtw_hal_status +rtw_efuse_bt_file_map_load(void *efuse, char *file_path); + +enum rtw_hal_status +rtw_efuse_bt_file_mask_load(void *efuse, char *file_path); + +enum rtw_hal_status +rtw_efuse_bt_get_usage(void *efuse, u32 *usage); + +enum rtw_hal_status +rtw_efuse_bt_get_logical_size(void *efuse, u32 *size); + +enum rtw_hal_status +rtw_efuse_bt_get_size(void *efuse, u32 *size); + +enum rtw_hal_status +rtw_efuse_bt_get_avl(void *efuse, u32 *size); + +enum rtw_hal_status +rtw_efuse_bt_get_offset_mask(void *efuse, u16 offset, u8 *mask); + +enum rtw_hal_status rtw_efuse_bt_read_hidden(void *efuse, u32 addr, u32 size, u8 *val); + +enum rtw_hal_status rtw_efuse_bt_write_hidden(void *efuse, u32 addr, u8 val); + +enum rtw_hal_status rtw_efuse_read_phy_wifi(void *efuse, u32 addr, u32 size, u8 *data, u8 type); + +enum rtw_hal_status rtw_efuse_renew(void *efuse, u8 type); + +#endif /* _HAL_EFUSE_EXPORT_H_ */ diff --git a/phl/hal_g6/hal.mk b/phl/hal_g6/hal.mk new file mode 100644 index 0000000..b4f35af --- /dev/null +++ b/phl/hal_g6/hal.mk @@ -0,0 +1,96 @@ +########### HAL PATH ################################# +HAL = hal_g6 + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/ +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := +phl_path_d1 := $(src)/$(HAL) +endif + +_HAL_FILES := $(phl_path)$(HAL)/hal_api_mac.o \ + $(phl_path)$(HAL)/hal_api_bb.o \ + $(phl_path)$(HAL)/hal_api_rf.o \ + $(phl_path)$(HAL)/hal_api_btc.o \ + $(phl_path)$(HAL)/hal_api_efuse.o \ + $(phl_path)$(HAL)/hal_com_i.o \ + $(phl_path)$(HAL)/hal_init.o \ + $(phl_path)$(HAL)/hal_io.o \ + $(phl_path)$(HAL)/hal_rx.o \ + $(phl_path)$(HAL)/hal_tx.o \ + $(phl_path)$(HAL)/hal_sta.o \ + $(phl_path)$(HAL)/hal_cam.o \ + $(phl_path)$(HAL)/hal_csi_buffer.o \ + $(phl_path)$(HAL)/hal_beamform.o \ + $(phl_path)$(HAL)/hal_sound.o \ + $(phl_path)$(HAL)/hal_chan.o \ + $(phl_path)$(HAL)/hal_str_proc.o \ + $(phl_path)$(HAL)/hal_fw.o \ + $(phl_path)$(HAL)/hal_cap.o \ + $(phl_path)$(HAL)/hal_ser.o \ + $(phl_path)$(HAL)/hal_ps.o \ + $(phl_path)$(HAL)/hal_c2h.o \ + $(phl_path)$(HAL)/hal_dbcc.o \ + $(phl_path)$(HAL)/hal_chan_info.o \ + $(phl_path)$(HAL)/hal_wow.o \ + $(phl_path)$(HAL)/hal_ld_file.o \ + $(phl_path)$(HAL)/hal_regulation.o \ + $(phl_path)$(HAL)/hal_led.o \ + $(phl_path)$(HAL)/hal_trx_mit.o \ + $(phl_path)$(HAL)/hal_acs.o \ + $(phl_path)$(HAL)/hal_mcc.o \ + $(phl_path)$(HAL)/hal_api.o \ + $(phl_path)$(HAL)/hal_twt.o \ + $(phl_path)$(HAL)/hal_notify.o \ + $(phl_path)$(HAL)/hal_p2pps.o \ + $(phl_path)$(HAL)/hal_thermal.o \ + $(phl_path)$(HAL)/hal_txpwr.o + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_FILES += $(phl_path)$(HAL)/hal_pci.o +endif +ifeq ($(CONFIG_USB_HCI), y) +_HAL_FILES += $(phl_path)$(HAL)/hal_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_FILES += $(phl_path)$(HAL)/hal_sdio.o +endif +########### hal test ################################# +ifeq ($(CONFIG_PHL_TEST_SUITE), y) +_HAL_FILES += $(phl_path)$(HAL)/test/hal_test_module.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_cal.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_config.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_efuse.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_reg.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_rx.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_tx.o +_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_txpwr.o +endif + +_HAL_FILES += $(phl_path)$(HAL)/efuse/hal_efuse.o +include $(phl_path_d1)/mac/mac.mk + +ifeq ($(USE_TRUE_PHY), y) +include $(phl_path_d1)/phy/bb/bb.mk +include $(phl_path_d1)/phy/rf/rf.mk +endif + +########### HALBTC ####################################### +include $(phl_path_d1)/btc/btc.mk +########### HAL_RTL8852A ################################# +ifeq ($(CONFIG_RTL8852A), y) +include $(phl_path_d1)/$(IC_NAME)/rtl8852a.mk +endif +########### HAL_RTL8852B ################################# +ifeq ($(CONFIG_RTL8852B), y) +include $(phl_path_d1)/$(IC_NAME)/rtl8852b.mk +endif +########### HAL_RTL8852C ################################# +ifeq ($(CONFIG_RTL8852C), y) +include $(phl_path_d1)/$(IC_NAME)/rtl8852c.mk +endif + +OBJS += $(_HAL_FILES) $(_HAL_MAC_FILES) $(_BTC_FILES) $(_HAL_IC_FILES) +OBJS += $(_HAL_BB_FILES) $(_HAL_RF_FILES) $(_HAL_EFUSE_FILES) diff --git a/phl/hal_g6/hal_acs.c b/phl/hal_g6/hal_acs.c new file mode 100644 index 0000000..62388b6 --- /dev/null +++ b/phl/hal_g6/hal_acs.c @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_ACS_C_ +#include "hal_headers.h" + +#ifdef CONFIG_RTW_ACS +void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + rtw_hal_bb_acs_mntr_trigger(hal_info, monitor_time); +} + +enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_bb_acs_mntr_result(hal_info, rpt); +} +#endif /* CONFIG_RTW_ACS */ \ No newline at end of file diff --git a/phl/hal_g6/hal_acs.h b/phl/hal_g6/hal_acs.h new file mode 100644 index 0000000..3286400 --- /dev/null +++ b/phl/hal_g6/hal_acs.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_ACS_H_ +#define _HAL_ACS_H_ + +void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time); +enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt); + +#endif \ No newline at end of file diff --git a/phl/hal_g6/hal_api.c b/phl/hal_g6/hal_api.c new file mode 100644 index 0000000..729e8f5 --- /dev/null +++ b/phl/hal_g6/hal_api.c @@ -0,0 +1,94 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_C_ +#include "hal_headers.h" + +enum rtw_hal_status rtw_hal_get_tsf(void *hal, u8 port, u32 *tsf_h, u32 *tsf_l) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + status = rtw_hal_mac_get_tsf(hal, &port, tsf_h, tsf_l); + + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_get_tsf(): get failed\n"); + } + return status; +} + +enum rtw_hal_status +rtw_hal_tsf_sync(void *hal, u8 port_sync_from, + u8 port_sync_to, enum phl_band_idx band, + s32 sync_offset_tu, enum hal_tsf_sync_act act) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_tsf_sync(hal_info, port_sync_from, + port_sync_to, band, sync_offset_tu, act); +} + +enum rtw_hal_status +rtw_hal_config_rts_th(void *hal, u8 band_idx, u16 rts_time_th, u16 rts_len_th) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_set_hw_rts_th(hal_info, band_idx, rts_time_th, rts_len_th); +} + +u32 rtw_hal_get_btc_req_slot(void *hal) +{ + return rtw_hal_btc_req_bt_slot_t(hal); +} + +/** + * This function is used to pause/unpause multiple macid + * @hal: see hal_info_t + * @macid_arr: macid array to be pause/unpause + * 1 means to be set (pause/unpause) + * 0 means don't care + * @macid_arr_sz: size of macid array + * @pause: all macid of this array to be paused/unpaused + * 1=paused,0=unpaused + */ +enum rtw_hal_status +rtw_hal_set_macid_grp_pause(void *hal, u32 *macid_arr, u8 arr_size, bool pause) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + return rtw_hal_mac_set_macid_grp_pause(hal_com, macid_arr, arr_size, pause); +} + +/** + * This function is used to pause/unpause single macid + * @hal: see hal_info_t + * @macid: macid be pause/unpause + * @pause: all macid of this array to be paused/unpaused + * 1=paused,0=unpaused + */ +enum rtw_hal_status +rtw_hal_set_macid_pause(void *hal, u16 macid, bool pause) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + return rtw_hal_mac_set_macid_pause(hal_com, macid, pause); +} + +enum rtw_hal_status rtw_hal_set_dfs_tb_ctrl(void *hal, u8 set) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_set_dfs_tb_ctrl(hal_info, set); +} + diff --git a/phl/hal_g6/hal_api.h b/phl/hal_g6/hal_api.h new file mode 100644 index 0000000..748623e --- /dev/null +++ b/phl/hal_g6/hal_api.h @@ -0,0 +1,969 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_H_ +#define _HAL_API_H_ + +/******************* IO APIs *******************/ +u8 rtw_hal_read8(void *h, u32 addr); +u16 rtw_hal_read16(void *h, u32 addr); +u32 rtw_hal_read32(void *h, u32 addr); +void rtw_hal_write8(void *h, u32 addr, u8 val); +void rtw_hal_write16(void *h, u32 addr, u16 val); +void rtw_hal_write32(void *h, u32 addr, u32 val); + +u32 rtw_hal_read_macreg(void *h, u32 offset, u32 bit_mask); +void rtw_hal_write_macreg(void *h, + u32 offset, u32 bit_mask, u32 data); +u32 rtw_hal_read_bbreg(void *h, u32 offset, u32 bit_mask); +void rtw_hal_write_bbreg(void *h, + u32 offset, u32 bit_mask, u32 data); +u32 rtw_hal_read_rfreg(void *h, + enum rf_path path, u32 offset, u32 bit_mask); +void rtw_hal_write_rfreg(void *h, + enum rf_path path, u32 offset, u32 bit_mask, u32 data); + +#ifdef PHL_PLATFORM_LINUX +void rtw_hal_mac_reg_dump(void *sel, void *h); +void rtw_hal_bb_reg_dump(void *sel, void *h); +void rtw_hal_bb_reg_dump_ex(void *sel, void *h); +void rtw_hal_rf_reg_dump(void *sel, void *h); +#endif + +enum rtw_hal_status +rtw_hal_get_addr_cam(void *h, u16 num, u8 *buf, u16 size); +enum rtw_hal_status +rtw_hal_get_sec_cam(void *h, u16 num, u8 *buf, u16 size); + +void rtw_hal_enable_interrupt(struct rtw_phl_com_t *phl_com, void *h); +void rtw_hal_disable_interrupt(struct rtw_phl_com_t *phl_com, void *h); +void rtw_hal_config_interrupt(void *h, enum rtw_phl_config_int int_mode); +bool rtw_hal_recognize_interrupt(void *h); +bool rtw_hal_recognize_halt_c2h_interrupt(void *h); +void rtw_hal_clear_interrupt(void *h); +void rtw_hal_restore_interrupt(struct rtw_phl_com_t *phl_com, void *h); + +u32 rtw_hal_interrupt_handler(void *h); +void rtw_hal_restore_rx_interrupt(void *h); + +enum rtw_hal_status rtw_hal_get_pwr_state(void *h, enum rtw_mac_pwr_st *pwr_state); + +enum rtw_hal_status rtw_hal_init(void *drv_priv, + struct rtw_phl_com_t *phl_com, void **hal, enum rtl_ic_id chip_id); +struct rtw_hal_com_t *rtw_hal_get_halcom(void *hal); +void rtw_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal); + +bool rtw_hal_is_inited(struct rtw_phl_com_t *phl_com, void *hal); + +u32 rtw_hal_hci_cfg(struct rtw_phl_com_t *phl_com, void *hal, + struct rtw_ic_info *ic_info); +u32 rtw_hal_read_chip_info(struct rtw_phl_com_t *phl_com, void *hal); + +void rtw_hal_set_default_var(void *hal, enum rtw_hal_set_def_var_rsn rsn); + +u32 rtw_hal_var_init(struct rtw_phl_com_t *phl_com, void *hal); + +enum rtw_hal_status rtw_hal_ser_ctrl(void *hal, bool en); + +u32 +rtw_hal_ser_get_error_status(void *hal, u32 *err); + +enum rtw_hal_status rtw_hal_ser_set_error_status(void *hal, u32 err); + +enum rtw_hal_status rtw_hal_trigger_cmac_err(void *hal); + +enum rtw_hal_status rtw_hal_trigger_dmac_err(void *hal); + +enum rtw_hal_status rtw_hal_lv1_rcvy(void *hal, u32 step); + +void +rtw_hal_dump_fw_rsvd_ple(void *phl); +void +rtw_hal_ser_reset_wdt_intr(void *hal); + +enum rtw_hal_status rtw_hal_cfg_fw_ps_log(void *hal, u8 en); + +enum rtw_hal_status rtw_hal_cfg_fw_mcc_log(void *hal, u8 en); + +enum rtw_hal_status +rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal); + +enum rtw_hal_status +rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal); +void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power); + +enum rtw_fw_status rtw_hal_get_fw_status(void *h); + +enum rtw_hal_status rtw_hal_preload(struct rtw_phl_com_t *phl_com, void *hal); +enum rtw_hal_status rtw_hal_start(struct rtw_phl_com_t *phl_com, void *hal); +void rtw_hal_stop(struct rtw_phl_com_t *phl_com, void *hal); +enum rtw_hal_status rtw_hal_restart(struct rtw_phl_com_t *phl_com, void *hal); +enum rtw_hal_status rtw_hal_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal); + +#ifdef CONFIG_WOWLAN +enum rtw_hal_status rtw_hal_get_wake_rsn(void *hal, enum rtw_wow_wake_reason *wake_rsn, u8 *reset); +enum rtw_hal_status rtw_hal_cfg_wow_sleep(void *hal, u8 sleep); +enum rtw_hal_status rtw_hal_get_wow_aoac_rpt(void *hal, struct rtw_aoac_report *aoac_info, u8 rx_ready); +enum rtw_hal_status rtw_hal_get_wow_fw_status(void *hal, u8 *status); +enum rtw_hal_status rtw_hal_wow_cfg_txdma(void *hal, u8 en); + +enum rtw_hal_status rtw_hal_wow_init(struct rtw_phl_com_t *phl_com, void *hal, struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status rtw_hal_wow_deinit(struct rtw_phl_com_t *phl_com, void *hal, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status rtw_hal_wow_func_en(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg); +enum rtw_hal_status rtw_hal_wow_func_dis(struct rtw_phl_com_t *phl_com, void *hal, u16 macid); + +enum rtw_hal_status rtw_hal_wow_func_start(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg); +enum rtw_hal_status rtw_hal_wow_func_stop(struct rtw_phl_com_t *phl_com, void *hal, u16 macid); + +enum rtw_hal_status rtw_hal_set_wowlan(struct rtw_phl_com_t *phl_com, void *hal, u8 enter); +enum rtw_hal_status rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t *phl_com, void *hal, u8 high, u8 gpio); +enum rtw_hal_status rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t *phl_com, void *hal, enum rtw_gpio_mode mode, u8 gpio); +enum rtw_hal_status rtw_hal_wow_drop_tx(void *hal, u8 band); + +#endif /* CONFIG_WOWLAN */ + +void + rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal); + +enum rtw_hal_status rtw_hal_trx_init(void *hal, u8 *txbd_buf, u8 *rxbd_buf); +void rtw_hal_trx_deinit(void *hal); + +enum rtw_hal_status +rtw_hal_role_cfg(void *hal, struct rtw_wifi_role_t *wrole); +enum rtw_hal_status +rtw_hal_role_cfg_ex(void *hal, struct rtw_wifi_role_t *wrole, + enum pcfg_type type, void *param); +enum rtw_hal_status +rtw_hal_beacon_stop(void *hal, struct rtw_wifi_role_t *wrole, bool stop); + +enum rtw_hal_status +rtw_hal_stainfo_init(void *hal, struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_stainfo_deinit(void *hal, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_add_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_del_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta, + bool is_connect); +enum rtw_hal_status +rtw_hal_change_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta, + enum phl_upd_mode mode); +u8 rtw_hal_get_sta_rssi(struct rtw_phl_stainfo_t *sta); +u8 rtw_hal_get_sta_rssi_bcn(struct rtw_phl_stainfo_t *sta); + +bool rtw_hal_is_sta_linked(void *hal, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_set_sta_rx_sts(struct rtw_phl_stainfo_t *sta, u8 rst, + struct rtw_r_meta_data *meta); + +enum rtw_hal_status +rtw_hal_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo); + +enum rtw_hal_status +rtw_hal_start_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, + u8 dialog_token, u16 timeout, u16 start_seq_num, + u16 ba_policy, u16 tid, u16 buf_size); +enum rtw_hal_status +rtw_hal_stop_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, u16 tid); + +/** + * rtw_hal_set_edca() - setup WMM EDCA parameter + * @hal: struct hal_info_t * + * @wrole: struct rtw_wifi_role_t * + * @ac: Access Category, 0:BE, 1:BK, 2:VI, 3:VO + * @param: AIFS:BIT[7:0], CWMIN:BIT[11:8], CWMAX:BIT[15:12], + * TXOP:BIT[31:16] + * + * Setup WMM EDCA parameter set for sending packets. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status +rtw_hal_set_edca(void *hal, struct rtw_wifi_role_t *wrole, u8 ac, u32 edca); + +enum rtw_hal_status +rtw_hal_cfg_tx_ampdu(void *hal, struct rtw_phl_stainfo_t *sta); + +#ifdef CONFIG_PHL_CUSTOM_FEATURE +enum rtw_hal_status +rtw_hal_custom_cfg_tx_ampdu(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *ampdu); +enum rtw_hal_status +rtw_hal_get_ampdu_cfg(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *cfg); +enum rtw_hal_status +rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx); + +bool +rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_set_pkt_detect_thold(void *hal, u32 bound); + +u8 +rtw_hal_query_pkt_detect_thold(void *hal, + bool get_en_info, + enum phl_phy_idx phy_idx); +#endif +enum rtw_hal_status +rtw_hal_thermal_protect_cfg_tx_duty( + void *hal, + u16 tx_duty_interval, + u8 ratio); + +enum rtw_hal_status +rtw_hal_thermal_protect_stop_tx_duty( + void *hal); + +enum rtw_hal_status +rtw_hal_set_key(void *hal, struct rtw_phl_stainfo_t *sta, u8 type, u8 ext_key, u8 spp, + u8 keyid, u8 keytype, u8 *keybuf); + +u32 +rtw_hal_search_key_idx(void *hal, struct rtw_phl_stainfo_t *sta, + u8 keyid, u8 keytype); +/** + * rtw_hal_tx_chnl_mapping - query hw tx dma channel mapping to the sw xmit ring + * identified by macid, tid and band + * @hal: see struct hal_info_t + * @macid: input target macid is 0 ~ 127 + * @cat: input target packet category, see enum rtw_phl_ring_cat + * @band: input target band, 0 for band 0 / 1 for band 1 + * + * returns the mapping hw tx dma channel + */ +u8 rtw_hal_tx_chnl_mapping(void *hal, u16 macid, + enum rtw_phl_ring_cat cat, u8 band); + + +/** + * rtw_hal_convert_qsel_to_tid - convert qsel to tid value + * @hal: see struct hal_info_t + * @qsel: HW queue selection + * @tid_indic: tid indicator + * + * returns enum RTW_HAL_STATUS + */ +u8 rtw_hal_convert_qsel_to_tid(void *hal, u8 qsel_id, u8 tid_indic); + + +/** + * rtw_hal_tx_res_query - query current HW tx resource with specifc dma channel + * @hal: see struct hal_info_t + * @dma_ch: the target dma channel + * @host_idx: current host index of this channel + * @hw_idx: current hw index of this channel + * + * this function returns the number of available tx resource + * NOTE, input host_idx and hw_idx ptr shall NOT be NULL + */ +u16 rtw_hal_tx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx); + +/** + * rtw_hal_rx_res_query - query current HW rx resource with specifc dma channel + * @hal: see struct hal_info_t + * @dma_ch: the target dma channel + * @host_idx: current host index of this channel + * @hw_idx: current hw index of this channel + * + * this function returns the number of available tx resource + * NOTE, input host_idx and hw_idx ptr shall NOT be NULL + */ +u16 rtw_hal_rx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx); + + +/** + * rtw_hal_query_txch_num - query total hw tx dma channels number + * + * returns the number of hw tx dma channel + */ +u8 rtw_hal_query_txch_num(void *hal); + +/** + * rtw_hal_query_rxch_num - query total hw rx dma channels number + * + * returns the number of hw rx dma channel + */ +u8 rtw_hal_query_rxch_num(void *hal); + + +/** + * rtw_hal_update_wd_page - update wd page for xmit packet + * @hal: see struct hal_info_t + * @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_update_wd_page(void *hal, void *phl_pkt_req); + +enum rtw_hal_status +rtw_hal_handle_rx_buffer(struct rtw_phl_com_t *phl_com, void* hal, + u8 *buf, u32 buf_size, + struct rtw_phl_rx_pkt *rxpkt); + +enum rtw_hal_status +rtw_hal_query_info(void* hal, u8 info_id, void *value); + +#ifdef CONFIG_PHL_DFS +bool rtw_hal_in_radar_domain(void *hal, u8 ch, enum channel_width bw); +enum rtw_hal_status rtw_hal_radar_detect_cfg(void *hal, bool dfs_enable); +#endif /*CONFIG_PHL_DFS*/ + +enum rtw_hal_status +rtw_hal_set_ch_bw(void *hal, u8 band_idx, + struct rtw_chan_def *chdef, bool do_rfk); +u8 rtw_hal_get_cur_ch(void *hal, u8 band_idx); +void rtw_hal_get_cur_chdef(void *hal, u8 band_idx, + struct rtw_chan_def *cur_chandef); + +void rtw_hal_sync_cur_ch(void *hal, u8 band_idx, struct rtw_chan_def chandef); + +u8 rtw_hal_get_fwcmd_queue_idx(void* hal); +void rtw_hal_cfg_txhci(void *hal, u8 en); +void rtw_hal_cfg_rxhci(void *hal, u8 en); +enum rtw_hal_status rtw_hal_chk_allq_empty(void *hal, u8 *empty); +s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy, + u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel); +enum rtw_hal_status rtw_hal_set_power_lmt(void *hal, u8 band_idx); +void rtw_hal_enable_ext_pwr_lmt(void *hal, u8 hw_band, + struct rtw_tpu_ext_pwr_lmt_info *ext_pwr_lmt_info); + +#ifdef CONFIG_RTW_ACS +void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time); +enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt); +#endif /* CONFIG_RTW_ACS */ + +/*watchdog update env result*/ +void rtw_hal_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, + struct rtw_wifi_role_t *wrole); + +#ifdef CONFIG_PCI_HCI +/** + * rtw_hal_update_txbd - update tx bd for xmit packet + * @hal: see struct hal_info_t + * @txbd: the target txbd to update + * @wd: buffer pointer of wd page to fill in txbd + * + * returns enum RTW_HAL_STATUS + * NOTE, this function is PCIe specific function + */ +enum rtw_hal_status +rtw_hal_update_txbd(void *hal, void *txbd, void *wd, u8 dma_ch, u16 wd_num); + +/** + * rtw_hal_update_rxbd - update rx bd for recv packet + * @hal: see struct hal_info_t + * @rxbd: the target rxbd to update + * @wd: buffer pointer of wd page to fill in rxbd + * + * returns enum RTW_HAL_STATUS + * NOTE, this function is PCIe specific function + */ +enum rtw_hal_status +rtw_hal_update_rxbd(void *hal, struct rx_base_desc *rxbd, + struct rtw_rx_buf *rxbuf); + +/** + * rtw_hal_update_trigger_txstart - trigger hw to start tx + * @hal: see struct hal_info_t + * @txbd: the target txbd to update + * @dma_ch: the dma channel index of this txbd_ring + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_trigger_txstart(void *hal, void *txbd, u8 dma_ch); + +/** + * rtw_hal_notify_rxdone - notify hw rx done + * @hal: see struct hal_info_t + * @rxbd: the target rxbd to update + * @ch: the target rx channel + * @rxcnt: handling done rx count this function will notify hw + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_notify_rxdone(void* hal, void *rxbd, u8 ch, + u16 rxcnt); + +/** + * rtw_hal_handle_wp_rpt -parsing the wp recycle report packet + * @hal: see struct hal_info_t + * @rp: input, the pointer of target recycle report buffer to parse + * @len: input, the length of this report buffer + * @sw_retry: output, the packet mentioned in this report needs sw retry if sw_retry == 1 + * @dma_ch: output, the tx dma channel of this packet mentioned in this report + * @wp_seq: output, the wp_seq of this packet mentioned in this report + * @txsts: output, the tx status of this packet mentioned in this report + * + * returns the length of report buffer which has been parsed in this function + */ +u16 rtw_hal_handle_wp_rpt(void *hal, u8 *rp, u16 len, u8 *sw_retry, u8 *dma_ch, + u16 *wp_seq, u8 *txsts); + +u8 rtw_hal_check_rxrdy(struct rtw_phl_com_t *phl_com, void* hal, u8 *rxbuf, u8 dma_ch); +u8 rtw_hal_handle_rxbd_info(void* hal, u8 *rxbuf, u16 *buf_size); +enum rtw_hal_status rtw_hal_set_l2_leave(void *hal); +void rtw_hal_clear_bdidx(void *hal); +void rtw_hal_rst_bdram(void *hal); +bool rtw_hal_poll_txdma_idle(void *hal); +void rtw_hal_cfg_dma_io(void *hal, u8 en); + + +enum rtw_hal_status rtw_hal_ltr_sw_trigger(void *hal, + enum rtw_pcie_ltr_state state); +enum rtw_hal_status rtw_hal_ltr_en_hw_mode(void *hal, bool hw_mode); +#ifdef RTW_WKARD_DYNAMIC_LTR +void rtw_hal_ltr_update_stats(void *hal, bool clear); +bool rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal); +bool rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t *phl_com, void *hal); +#endif + +#endif /*CONFIG_PCI_HCI*/ + +#ifdef CONFIG_USB_HCI + +u8 rtw_hal_get_bulkout_id(void *hal, u8 dma_ch, u8 mode); + +enum rtw_hal_status rtw_hal_fill_wd(void *hal, + struct rtw_xmit_req *tx_req, + u8 *wd_buf, u32 *wd_len); + +enum rtw_hal_status + rtw_hal_usb_tx_agg_cfg(void *hal, u8* wd_buf, u8 agg_num); + +enum rtw_hal_status + rtw_hal_usb_rx_agg_cfg(void *hal, u8 mode, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num); + +u8 rtw_hal_get_max_bulkout_wd_num(void *hal); +u32 rtwl_hal_get_cur_usb_mode(void *h); +u32 rtwl_hal_get_usb_support_ability(void *h); +enum rtw_hal_status rtw_hal_force_usb_switch(void *h, enum usb_type type); +/** + * rtw_hal_handle_wp_rpt_usb -parsing the wp recycle report packet + * @hal: see struct hal_info_t + * @rp: input, the pointer of target recycle report buffer to parse + * @len: input, the length of this report buffer + * @macid: output, the mac_id of this packet mentioned in this report + * @ac_queue: output, the tid of this packet mentioned in this report + * @txsts: output, the tx status of this packet mentioned in this report + * + * returns the length of report buffer which has been parsed in this function + */ +u16 rtw_hal_handle_wp_rpt_usb(void *hal, u8 *rp, u16 len, u8 *macid, u8 *ac_queue, + u8 *txsts); + +enum rtw_rx_status rtw_hal_get_usb_status(void *h); +#endif + +#ifdef CONFIG_SDIO_HCI +/** + * rtw_hal_sdio_tx_cfg - SDIO TX related setting + * @hal: pointer of struct hal_info_t + * + * Configure setting for SDIO TX. + * + * No return value for this function. + */ +void rtw_hal_sdio_tx_cfg(void *hal); + +enum rtw_hal_status rtw_hal_sdio_tx(void *hal, u8 dma_ch, u8 *buf, u32 buf_len, + u8 agg_count, u16 *pkt_len, u8 *wp_offset); +void rtw_hal_sdio_rx_agg_cfg(void *hal, bool enable, u8 drv_define, + u8 timeout, u8 size, u8 pkt_num); +int rtw_hal_sdio_rx(void *hal, struct rtw_rx_buf *rxbuf); +int rtw_hal_sdio_parse_rx(void *hal, struct rtw_rx_buf *rxbuf); +#endif /* CONFIG_SDIO_HCI */ + +/* HAL SOUND API */ +enum rtw_hal_status rtw_hal_snd_query_proc_sta_res( + void *hal, struct rtw_phl_stainfo_t *sta, + bool mu, enum channel_width bw, bool en_swap); + +enum rtw_hal_status +rtw_hal_snd_release_proc_sta_res(void *hal, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_snd_proc_pre_cfg_sta(void *hal, struct rtw_phl_stainfo_t *sta); + +void +rtw_hal_snd_ndpa_sta_info_vht(struct rtw_phl_stainfo_t *psta_info, + u32 *ndpa, u8 mu); + +void +rtw_hal_snd_ndpa_sta_info_he(struct rtw_phl_stainfo_t *psta_info, + u32 *ndpa, enum channel_width bw, u8 fb_type); + +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg_sta(void *hal, + struct rtw_phl_stainfo_t *sta, bool mu); + +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg_gid(void *hal, u8 gid, void *ba_info); + +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg(void *hal, bool he, bool mu, bool en_fixed_mode); + +enum rtw_hal_status +rtw_hal_snd_mac_ctrl(void *hal, u8 band, u8 ctrl); + +enum rtw_hal_status +rtw_hal_snd_chk_bf_res(void *hal, struct rtw_phl_stainfo_t *sta, + bool mu, enum channel_width bw); + +void +rtw_hal_snd_polling_snd_sts(void *hal, struct rtw_phl_stainfo_t *sta); + +/* fw sounding commmand ralated */ +void rtw_hal_snd_set_fw_cmd_dialogtkn(void *hal, u8 *buf, u8 he, u8 token); + +void rtw_hal_snd_vht_fwcmd_su(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u32 *npda_sta); + +void rtw_hal_snd_vht_fwcmd_mu_pri(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u8 sta_nr, u32 *ndpa_sta); + +void rtw_hal_snd_vht_fwcmd_mu_add_sta(void *hal, u8 *buf, u32 *ndpa_sta, + struct rtw_phl_stainfo_t *sta, + u8 ndpa_idx, u8 last); + +void rtw_hal_snd_ax_fwcmd_nontb(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u32 *npda_sta); + +void rtw_hal_snd_ax_fwcmd_tb_pri(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u8 sta_nr1, u8 sta_nr2); + +void rtw_hal_snd_ax_fwcmd_tb_add_sta(void *hal, u8 *buf, u32 *ndpa_sta, + struct rtw_phl_stainfo_t *sta, u8 ru_idx, + u8 ndpa_idx, u8 bfrp_idx, u8 bfrp_u_idx); + +u8 *rtw_hal_snd_prepare_snd_cmd(void *hal); +enum rtw_hal_status rtw_hal_snd_release_snd_cmd(void *hal, u8 *buf); +enum rtw_hal_status rtw_hal_snd_send_fw_cmd(void *hal, u8 *cmd); + +/*HAL CSI Buffer Mgnt APIs*/ +enum channel_width +rtw_hal_get_csi_buf_bw(void *buf); + +bool +rtw_hal_get_csi_buf_type(void *buf); + +/*HAL Beamform Mgnt APIs*/ +void rtw_hal_bf_dbg_dump_entry(void *entry); +void rtw_hal_bf_dbg_dump_entry_all(void *hal); +u8 rtw_hal_bf_get_sumu_idx(void *hal, void *entry); +bool rtw_hal_bf_chk_bf_type(void *hal_info, + struct rtw_phl_stainfo_t *sta, bool mu); +void rtw_hal_bf_preset_mu_ba_info(void *hal, + struct rtw_phl_stainfo_t *psta, void *hal_ba_info); +void rtw_hal_bf_set_txmu_para(void *hal, u8 gid , u8 en, + enum rtw_hal_protection_type rts_type, + enum rtw_hal_ack_resp_type ack_type); +enum rtw_hal_status +rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he); +enum rtw_hal_status +rtw_hal_bf_get_entry_snd_sts(void *entry); + +void rtw_hal_beamform_set_vht_gid(void *hal, u8 band, + struct rtw_phl_gid_pos_tbl *tbl); + +/****************************************************************************** + * + * BTC APIs + * + *****************************************************************************/ +#ifdef CONFIG_BTCOEX +void rtw_hal_btc_scan_start_ntfy(void *hinfo, enum phl_phy_idx phy_idx, + enum band_type band); +void rtw_hal_btc_scan_finish_ntfy(void *hinfo, enum phl_phy_idx phy_idx); +void rtw_hal_btc_update_role_info_ntfy(void *hinfo, u8 role_id, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + enum role_state rstate); +void rtw_hal_btc_packet_event_ntfy(void *hinfo, u8 pkt_evt_type); +void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state); +void rtw_hal_btc_customerize_ntfy(void *hinfo, u8 type, u16 len, u8 *buf); +void rtw_hal_btc_wl_status_ntfy(void *hinfo, struct rtw_phl_com_t *phl_com, u8 ntfy_num, + struct rtw_phl_stainfo_t *sta[], + u8 reason); +void rtw_hal_btc_timer(void *hinfo, void *timer); +void rtw_hal_btc_fwinfo_ntfy(void *hinfo); +#endif + +enum rtw_hal_status rtw_hal_scan_set_rxfltr_by_mode(void *hinfo, + enum phl_phy_idx phy_idx, bool off_channel, u8 *mode); +enum rtw_hal_status +rtw_hal_enter_mon_mode(void *hinfo, enum phl_phy_idx phy_idx); +enum rtw_hal_status +rtw_hal_leave_mon_mode(void *hinfo, enum phl_phy_idx phy_idx); +#ifdef CONFIG_FSM +enum rtw_hal_status rtw_hal_scan_flush_queue(void *hinfo, + struct rtw_wifi_role_t *wrole); +#endif +enum rtw_hal_status rtw_hal_scan_pause_tx_fifo(void *hinfo, + u8 band_idx, bool off_ch); + +enum rtw_hal_status rtw_hal_dfs_pause_tx(void *hinfo, + u8 band_idx, bool off_ch); +/*****************************************************************************/ + +void rtw_hal_com_scan_set_tx_lifetime(void *hal, u8 band); +void rtw_hal_com_scan_restore_tx_lifetime(void *hal, u8 band); + +#ifdef RTW_PHL_BCN +enum rtw_hal_status +rtw_hal_add_beacon(struct rtw_phl_com_t *phl_com, void *hal, void *bcn_cmn); + +enum rtw_hal_status +rtw_hal_update_beacon(struct rtw_phl_com_t *phl_com, void *hal, u8 bcn_id); + +enum rtw_hal_status +rtw_hal_free_beacon(struct rtw_phl_com_t *phl_com, void *hal, u8 bcn_id); +#endif + +enum rtw_hal_status +rtw_hal_proc_cmd(void *hal, char proc_cmd, struct rtw_proc_cmd *incmd, + char *output, u32 out_len); + +void rtw_hal_get_fw_ver(void *hal, char *ver_str, u16 len); + +enum rtw_hal_status +rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com, + u8 band_idx, bool tx_pause, enum tx_pause_rson rson); + +enum rtw_hal_status rtw_hal_set_macid_pause(void *hinfo, + u16 macid, + bool pause); + +/** + * rtw_hal_set_rxfltr_by_mode - Set rx filter option by scenario + * @hal: pointer of struct hal_info_t + * @band: 0x0: band0, 0x1: band1 + * @mode: scenario mode + * + * Set RX filter setting by scenario. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status rtw_hal_set_rxfltr_by_mode(void *hal, u8 band, + enum rtw_rx_fltr_mode mode); + +/** + * rtw_hal_get_rxfltr_mode - Get rx filter option + * @hal: pointer of struct hal_info_t + * @band: 0x0: band0, 0x1: band1 + * + * Get RX filter mode + * + * Return rtw_rx_fltr_mode + */ +enum rtw_rx_fltr_mode rtw_hal_get_rxfltr_mode(void *hal, u8 band); + +/** + * rtw_hal_mac_acpt_crc_err_pkt - Accept CRC error packets or not + * @hal: pointer of struct rtw_hal_info_t + * @band: 0x0: band0, 0x1: band1 + * @enable: 0: deny, 1: accept + * + * Control accepting CRC error packets or not. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status rtw_hal_acpt_crc_err_pkt(void *hal, u8 band, u8 enable); + +/** + * rtw_hal_set_rxfltr_mpdu_size - Set max MPDU size + * @hal: pointer of struct hal_info_t + * @band: 0x0: band0, 0x1: band1 + * @size: MPDU max size, unit: byte. 0 for no limit. + * + * MPDU size exceed max size would be dropped. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status rtw_hal_set_rxfltr_mpdu_size(void *hal, u8 band, u16 size); +enum rtw_hal_status rtw_hal_set_rxfltr_by_type(void *hal, u8 band, u8 type,u8 target); + + +enum rtw_hal_status +rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value); + +void rtw_hal_dbg_status_dump(void *hal, struct hal_mac_dbg_dump_cfg *cfg); +/****************************************************************************** + * + * Packet Offload APIs + * + *****************************************************************************/ +enum rtw_hal_status rtw_hal_reset_pkt_ofld_state(void *hal); + +enum rtw_hal_status rtw_hal_pkt_ofld(void *hal, u8 *id, u8 op, + u8 *pkt, u16 *len); +enum rtw_hal_status rtw_hal_pkt_update_ids(void *hal, + struct pkt_ofld_entry *entry); +void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal); +void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal); +void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal); +void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal); + +/****************************************************************************** + * + * Power Save APIs + * + *****************************************************************************/ + +enum rtw_hal_status +rtw_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, void *hal, + u32 req_pwr_lvl); +enum rtw_hal_status +rtw_hal_ps_lps_cfg(void *hal, struct rtw_hal_lps_info *lps_info); + +enum rtw_hal_status +rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal, + u8 band, struct protocol_cap_t *proto_cap); + +enum rtw_hal_status +rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal, + u8 band, struct protocol_cap_t *proto_cap); + +enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force); + +enum rtw_hal_status rtw_hal_watchdog(void *hal); +enum rtw_hal_status rtw_hal_simple_watchdog(void *hal, u8 io_en); +void rtw_hal_ps_chk_hw_rf_state(struct rtw_phl_com_t *phl_com, void *hal); + +/****************************************************************************** + * + * TWT APIs + * + *****************************************************************************/ +#ifdef CONFIG_PHL_TWT +enum rtw_hal_status +rtw_hal_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, + struct rtw_wifi_role_t *role, u8 action); + +enum rtw_hal_status +rtw_hal_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action); + +enum rtw_hal_status +rtw_hal_twt_sta_announce(void *hal, u8 macid); +#endif /* CONFIG_PHL_TWT */ + +/****************************************************************************** + * + * BB APIs + * + *****************************************************************************/ +/*@--------------------------[Prptotype]-------------------------------------*/ +/** + * rtw_hal_bb_get_txsc input arguments: + * @hal_com: hal com info + * @pri_ch: Spec-defined primary channel index + * @central_ch: Spec-defined central channel index + * @cbw: Channel BW + * @dbw: Data BW + */ +u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch, + u8 central_ch, enum channel_width cbw, enum channel_width dbw); + + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_hal_status +rtw_hal_dbcc_pre_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en); + +enum rtw_hal_status +rtw_hal_dbcc_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en); + +enum rtw_hal_status +rtw_hal_clean_tx_queue(void *hal); + +enum rtw_hal_status +rtw_hal_dbcc_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band); + +enum rtw_hal_status +rtw_hal_dbcc_reset_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band); +#endif + +/* + * API for config channel info CR + */ +#ifdef CONFIG_PHL_CHANNEL_INFO + +enum rtw_hal_status +rtw_hal_cfg_chinfo(void *hal, struct rtw_phl_stainfo_t *sta, u8 enable); + +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +enum rtw_hal_status +rtw_hal_get_efuse_info(void *hal, enum rtw_efuse_info info_type, + void *value, u8 size); + +enum rtw_hal_status +rtw_hal_cfg_trx_path(void *hal, enum rf_path tx, u8 tx_nss, + enum rf_path rx, u8 rx_nss); + +enum rtw_hal_status +rtw_hal_tsf_sync(void *hal, u8 wrole_sync_from, u8 wrole_sync_to, + enum phl_band_idx band, s32 sync_offset_tu, + enum hal_tsf_sync_act act); + +/** + * rtw_hal_fill_txdesc() - Fill hardware tx header + * @hal: pointer of struct hal_info_t + * @treq: the xmit request for this tx descriptor + * @wd_buf: the wd buffer to fill + * @wd_len: output, return the total length of filled wd + * + * Fill hardware tx header/tx descriptor/wifi descriptor + * + * Return RTW_HAL_STATUS_SUCCESS when everything is ok. + */ +enum rtw_hal_status rtw_hal_fill_txdesc(void *hal, struct rtw_xmit_req *treq, + u8 *wd_buf, u32 *wd_len); + +enum rtw_hal_status rtw_hal_poll_hw_tx_done(void *hal); +enum rtw_hal_status rtw_hal_hw_tx_resume(void *hal); +enum rtw_hal_status rtw_hal_poll_hw_rx_done(void *hal); +enum rtw_hal_status rtw_hal_hw_rx_resume(void *hal); + +void rtw_hal_tx_dbg_status_dump(void *hal); + +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +enum rtw_hal_status rtw_hal_bf_bfee_ctrl(void *hal, u8 band, bool ctrl); +#endif + + +enum rtw_hal_status +rtw_hal_set_mu_edca(void *hal, u8 band, u8 ac, + u16 timer, u8 cw_min, u8 cw_max, u8 aifsn); +enum rtw_hal_status +rtw_hal_set_mu_edca_ctrl(void *hal, u8 band, u8 wmm, u8 set); + +enum rtw_hal_status rtw_hal_led_set_ctrl_mode(void *hal, enum rtw_led_id led_id, + enum rtw_led_ctrl_mode ctrl_mode); +enum rtw_hal_status rtw_hal_led_control(void *hal, enum rtw_led_id led_id, + u8 high); + +enum rtw_hal_status rtw_hal_pcie_trx_mit(void *hal, u32 tx_timer, u8 tx_counter, + u32 rx_timer, u8 rx_counter); + +enum rtw_hal_status rtw_hal_get_tsf(void *hal, u8 port, u32 *tsf_h, u32 *tsf_l); + +u32 rtw_hal_get_btc_req_slot(void *hal); + +enum rtw_hal_status +rtw_hal_set_macid_pause(void *hal, u16 macid, bool pause); + +enum rtw_hal_status +rtw_hal_set_macid_grp_pause(void *hal, u32 *macid_arr, u8 arr_size, bool pause); + +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status rtw_hal_mcc_get_2ports_tsf(void *hal, u8 group, + u16 macid_x, u16 macid_y, u32 *tsf_x_h, u32 *tsf_x_l, + u32 *tsf_y_h, u32 *tsf_y_l); + +enum rtw_hal_status rtw_hal_notify_mcc_macid(void *hal, + struct rtw_phl_mcc_role *mrole, + enum rtw_phl_tdmra_wmode wmode); + +enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group, + u16 macid, struct rtw_phl_mcc_macid_bitmap *info); + +enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal, + struct rtw_phl_mcc_en_info *info); + +enum rtw_hal_status rtw_hal_mcc_change_pattern(void *hal, + struct rtw_phl_mcc_en_info *ori_info, + struct rtw_phl_mcc_en_info *new_info, + struct rtw_phl_mcc_bt_info *new_bt_info); + +enum rtw_hal_status rtw_hal_mcc_disable(void *hal, u8 group, u16 macid, + enum rtw_phl_tdmra_wmode wmode); + +enum rtw_hal_status rtw_hal_mcc_enable(void *hal, struct rtw_phl_mcc_en_info *info, + struct rtw_phl_mcc_bt_info *bt_info, + enum rtw_phl_tdmra_wmode wmode); +#endif /* CONFIG_MCC_SUPPORT */ + +#ifdef CONFIG_PHL_P2PPS +enum rtw_hal_status rtw_hal_noa_enable(void *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_noa_disable(void *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_tsf32_tog_enable(void *hal, + struct rtw_wifi_role_t *w_role); + +enum rtw_hal_status rtw_hal_tsf32_tog_disable(void *hal, + struct rtw_wifi_role_t *w_role); + +enum rtw_hal_status rtw_hal_get_tsf32_tog_rpt(void *hal, + struct rtw_phl_tsf32_tog_rpt *rpt); +#endif +void rtw_hal_disconnect_notify(void *hal, struct rtw_chan_def *chandef); + +bool rtw_hal_check_ch_rfk(void *hal, struct rtw_chan_def *chandef); +enum rtw_hal_status rtw_hal_ppdu_sts_cfg(void *hal, u8 band_idx, bool en); +void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx); + +void rtw_hal_cmd_notification(void *hal, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx); + +enum rtw_hal_status +rtw_hal_config_rts_th(void *hal, u8 band_idx, u16 rts_time_th, u16 rts_len_th); + +enum rtw_hal_status +rtw_hal_query_txsts_rpt(void *hal, u16 macid); + +enum rtw_hal_status rtw_hal_set_dfs_tb_ctrl(void *hal, u8 set); +enum rtw_hal_status +rtw_hal_thermal_protect_cfg_tx_ampdu( + void *hal, + struct rtw_phl_stainfo_t *sta, + u8 ratio); + +bool rtw_hal_check_thermal_protect( + struct rtw_phl_com_t *phl_com, + void *hal); + +enum rtw_hal_status +rtw_hal_beamform_set_aid(void *hal, struct rtw_phl_stainfo_t *sta, u16 aid); + +/****************************************************************************** + * + * TX power APIs + * + *****************************************************************************/ +const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band); + +bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx); + +enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx, + enum phl_pwr_table pwr_table); + +#endif /*_HAL_API_H_*/ diff --git a/phl/hal_g6/hal_api_bb.c b/phl/hal_g6/hal_api_bb.c new file mode 100644 index 0000000..e48380c --- /dev/null +++ b/phl/hal_g6/hal_api_bb.c @@ -0,0 +1,2242 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_BB_C_ +#include "hal_headers.h" +#include "phy/bb/halbb_export_fun.h" + +//kevin-cmd +#include "phy/bb/halbb_hw_cfg_ex.h" + +#ifdef USE_TRUE_PHY +enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx) +{ + enum phl_phy_idx p_idx = HW_PHY_0; + + if (band_idx == 1) + p_idx = HW_PHY_1; + + return p_idx; +} + +void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en) +{ + halbb_dfs_en(hal_info->bb, en); +} + +void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path) +{ + halbb_tssi_cont_en(hal_info->bb, en, path); +} + +void rtw_hal_bb_adc_en(struct hal_info_t *hal_info, bool en) +{ + halbb_adc_en(hal_info->bb, en); +} + +void rtw_hal_bb_reset_en(struct hal_info_t *hal_info, bool en, enum phl_phy_idx phy_idx) +{ + halbb_bb_reset_en(hal_info->bb, en, phy_idx); +} + +bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + if(incmd->in_type == RTW_ARG_TYPE_BUF) + halbb_cmd(hal_info->bb, incmd->in.buf, output, out_len); + else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){ + halbb_cmd_parser(hal_info->bb, incmd->in.vector, + incmd->in_cnt_len, output, out_len); + } + + return true; +} + +enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps) +{ + enum bb_watchdog_mode_t mode = BB_WATCHDOG_NORMAL; + + if (is_lps) + mode = BB_WATCHDOG_LOW_IO; + + halbb_watchdog(hal_info->bb, mode, HW_PHY_0); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en) +{ + enum bb_watchdog_mode_t mode = BB_WATCHDOG_NON_IO; + + if (io_en) + mode = BB_WATCHDOG_LOW_IO; + + halbb_watchdog(hal_info->bb, mode, HW_PHY_0); + + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_reset(struct hal_info_t *hal_info) +{ + halbb_watchdog_reset(hal_info->bb); +} + +void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info) +{ + PHL_INFO("[Cert], %s() ==> !! \n", __func__); + + halbb_fw_edcca(hal_info->bb); +} + +void rtw_hal_bb_dm_init(struct hal_info_t *hal_info) +{ + halbb_dm_init(hal_info->bb, HW_PHY_0); +} + +void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + halbb_dm_deinit(phl_com, hal_info->bb); +} + +enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com, + bool cca_en, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + halbb_ctrl_rx_cca(hal->bb, cca_en, phy_idx); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en) +{ + halbb_ctrl_dbcc(hal_info->bb, dbcc_en); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en) +{ + halbb_cfg_dbcc(hal_info->bb, dbcc_en); + + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hal_status; + + hal_status = halbb_buffer_init(phl_com, hal_com, &(hal_info->bb)); + + if ((hal_status != RTW_HAL_STATUS_SUCCESS) || (hal_info->bb == NULL)) + PHL_ERR("[PHL] rtw_hal_bb_init failed status(%d), hal_info->bb(%p)\n", + hal_status, hal_info->bb); + + return hal_status; +} + +void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + halbb_buffer_deinit(phl_com, hal_com, hal_info->bb); +} + +void rtw_hal_init_bb_reg(struct hal_info_t *hal_info) +{ + halbb_init_reg(hal_info->bb); + halbb_reset_bb(hal_info->bb); +} + +u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + return halbb_read_rf_reg(hal->bb, path, addr, mask); +} + +bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + return halbb_write_rf_reg(hal->bb, path, addr, mask, data); +} + +u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + return halbb_get_reg(hal->bb, addr, mask); +} + +bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + halbb_set_reg(hal->bb, addr, mask, data); + return true; +} + +u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + return halbb_rf_get_bb_reg(hal->bb, addr, mask); +} + +bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv; + + return halbb_rf_set_bb_reg(hal->bb, addr, mask, data); +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if (halbb_sta_info_init(hal_info->bb, sta)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("[HAL] halbb_stainfo_init failed status(%d)\n", + hal_status); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if (halbb_sta_info_deinit(hal_info->bb, sta)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("[HAL] rtw_hal_bb_stainfo_deinit failed status(%d)\n", + hal_status); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if (halbb_sta_info_add_entry(hal_info->bb, sta)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("[HAL] halbb_stainfo_init failed status(%d)\n", + hal_status); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if (halbb_sta_info_delete_entry(hal_info->bb, sta)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("[HAL] rtw_hal_bb_stainfo_deinit failed status(%d)\n", + hal_status); + + return hal_status; +} + +void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, bool is_connected) +{ + halbb_media_status_update(hal_info->bb, sta, is_connected); +} + +enum rtw_hal_status +rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + if (!rtw_halbb_dft_mask(hal_info->bb, sta)) { + PHL_ERR("rtw_halbb_set_dft_mask failed\n"); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("sta's cur_ra_mask : 0x%016llx\n", sta->hal_sta->ra_info.cur_ra_mask); + + if (sta->hal_sta->ra_info.ra_mask) { + sta->hal_sta->ra_info.cur_ra_mask &= sta->hal_sta->ra_info.ra_mask; + PHL_INFO("ra_mask : 0x%016llx, cur_ra_mask : 0x%016llx\n", + sta->hal_sta->ra_info.ra_mask, sta->hal_sta->ra_info.cur_ra_mask); + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_register(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + if (!rtw_halbb_raregistered(hal_info->bb, sta)) + return RTW_HAL_STATUS_FAILURE; + + sta->hal_sta->ra_info.ra_registered = true; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + if (!rtw_halbb_ra_deregistered(hal_info->bb, sta)) + PHL_ERR("rtw_halbb_ra_deregistered failed\n"); + + sta->hal_sta->ra_info.ra_registered = false; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + if (!sta->hal_sta->ra_info.ra_registered) { + PHL_WARN("%s mac-id:%d not register RA\n", __func__, sta->macid); + return RTW_HAL_STATUS_SUCCESS; + } + + if (sta->hal_sta->ra_info.ra_mask) { + sta->hal_sta->ra_info.cur_ra_mask &= sta->hal_sta->ra_info.ra_mask; + PHL_INFO("ra_mask : 0x%016llx, cur_ra_mask : 0x%016llx\n", + sta->hal_sta->ra_info.ra_mask, sta->hal_sta->ra_info.cur_ra_mask); + } + + if (rtw_halbb_raupdate(hal_info->bb, sta) == true) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +#ifdef CONFIG_BTCOEX +enum rtw_hal_status rtw_hal_btc_cfg_tx_1ss(struct rtw_hal_com_t *hal_com, + struct rtw_phl_com_t *phl_com, u8 rid, bool enable) +{ + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_i = (struct hal_info_t *)hal_com->hal_priv; + void *drv = halcom_to_drvpriv(hal_com); + struct rtw_wifi_role_t *wrole = rtw_phl_get_wrole_by_ridx(phl_com, rid); + struct phl_queue *sta_queue = NULL; + struct rtw_phl_stainfo_t *sta = NULL; + u8 ra_nss_limit = enable ? 1 : 0; + + PHL_PRINT("%s: rid(%d), enable(%d)\n", __FUNCTION__, rid, enable); + if (wrole == NULL) { + PHL_ERR("%s: Get role failed\n", __FUNCTION__); + goto exit; + } + sta_queue = &wrole->assoc_sta_queue; + _os_spinlock(drv, &sta_queue->lock, _bh, NULL); + phl_list_for_loop(sta, struct rtw_phl_stainfo_t, + &sta_queue->queue, list) { + if (!sta) + continue; + sta->hal_sta->ra_info.ra_nss_limit = ra_nss_limit; + hstats = rtw_hal_bb_ra_update(hal_i, sta); + if (RTW_HAL_STATUS_SUCCESS != hstats) { + PHL_ERR("%s: macid(%d), Fail to cfg ra_nss_limit(%d)\n", + __FUNCTION__, sta->macid, ra_nss_limit); + break; + } else { + PHL_PRINT("%s: macid(%d), succee to cfg ra_nss_limit(%d)\n", + __FUNCTION__, sta->macid, ra_nss_limit); + } + } + _os_spinunlock(drv, &sta_queue->lock, _bh, NULL); +exit: + return hstats; +} +#endif /* CONFIG_BTCOEX */ + +enum rtw_hal_status +rtw_hal_bb_query_txsts_rpt(struct hal_info_t *hal_info, + u16 macid0, u16 macid1) +{ + if (!rtw_halbb_query_txsts(hal_info->bb, macid0, macid1)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#define INVALID_ARFR_IDX 0xFF +#define rtw_halbb_get_arfr_idx(_bb, _sta) INVALID_ARFR_IDX +u8 rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return rtw_halbb_get_arfr_idx(hal_info->bb, sta); +} + +enum rtw_hal_status +rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +u8 hal_get_primary_channel_idx(u8 pri_ch, + u8 central_ch, enum channel_width bw, + enum chan_offset bw_offset) +{ + u8 idx = 255; + + if(bw == CHANNEL_WIDTH_80) { + if(bw_offset == CHAN_OFFSET_NO_EXT || + bw_offset == CHAN_OFFSET_NO_DEF) { + PHL_ERR("%s invalid bw offset\n",__FUNCTION__); + return idx; + } + if (central_ch > pri_ch) + idx = (bw_offset == CHAN_OFFSET_UPPER) ? (4) : (2); + else + idx = (bw_offset == CHAN_OFFSET_UPPER) ? (1) : (3); + } + else if(bw == CHANNEL_WIDTH_40) { + if(bw_offset == CHAN_OFFSET_NO_EXT || + bw_offset == CHAN_OFFSET_NO_DEF) { + PHL_ERR("%s invalid bw offset\n",__FUNCTION__); + return idx; + } + idx = (bw_offset == CHAN_OFFSET_UPPER) ? (2) : (1); + } + else { + idx = 0; + } + PHL_INFO("Using SC index %u for P%u C%u B%u O%u\n", + idx, pri_ch, central_ch, bw, bw_offset); + return idx; +} + +enum rtw_hal_status rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info, + enum phl_phy_idx phy_idx, + u8 pri_ch, + u8 central_ch_seg0, + u8 central_ch_seg1, + enum band_type band, + enum channel_width bw) +{ + if(halbb_ctrl_bw_ch(hal_info->bb, pri_ch, central_ch_seg0, + central_ch_seg1, band, bw, phy_idx) == false) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_PHL_CUSTOM_FEATURE +/** + * Early Weak Interference Rejection (EWIR) + * rtw_hal_bb_set_pop_en: configure bb feature about packet on packet. + * @hal_info: see struct hal_info_t + * @en: enable: true, disable: false + * @phy_idx: corresponding to the hw_band in wifi_role. + * returns enum rtw_hal_status + */ +enum rtw_hal_status rtw_hal_bb_set_pop_en(struct hal_info_t *hal_info, + bool en, + enum phl_phy_idx phy_idx) +{ + PHL_INFO(" %s, pop_enable(%d)\n", __FUNCTION__, en); + halbb_pop_en(hal_info->bb, en, phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * Early Weak Interference Rejection (EWIR) + * rtw_hal_bb_query_pop_en: query the status of packet on packet operation. + * @hal_info: see struct hal_info_t + * @phy_idx: corresponding to the hw_band in wifi_role. + * returns true: running; false: not running. + */ +bool rtw_hal_bb_query_pop_en(struct hal_info_t *hal_info, + enum phl_phy_idx phy_idx) +{ + return halbb_querry_pop_en(hal_info->bb, phy_idx); +} + +/** + * rtw_hal_bb_set_pkt_detect_thold: configure packet threshold(dbm) detection + * It would pause DIG while pd threshold enabling(value > 0) + * @hal_info: see struct hal_info_t + * @bound: pd threshold value + * returns enum rtw_hal_status + */ +enum rtw_hal_status rtw_hal_bb_set_pkt_detect_thold(struct hal_info_t *hal_info, + u32 bound) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + enum halbb_pause_type pause_type = HALBB_PAUSE; + u8 pause_result = 0; + u32 val[5] = {0}; + val[0] = bound; + val[1] = 0; + if (bound == 0) { + pause_type = HALBB_RESUME; + } else if ((bound > 102) || (bound < 40)) { + PHL_INFO(" %s, invalid boundary!\n", __FUNCTION__); + return hal_status; + } + pause_result = halbb_pause_func(hal_info->bb, + F_DIG, pause_type, + HALBB_PAUSE_LV_2, + 2, + val); + if (pause_result == PAUSE_SUCCESS) + hal_status = RTW_HAL_STATUS_SUCCESS; + return hal_status; +} + +/** + * rtw_hal_bb_query_pkt_detect_thold: query packet threshold(dbm) value. + * @hal_info: see struct hal_info_t + * @get_en_info: Caller can confirm the feature running or not with true value. + * 1. true: for query pd threshold detection enabling or not. + * 2. false:for query pd threshold value. + * @phy_idx: corresponding to the hw_band in wifi_role. + * returns pd threshold value + */ +u8 rtw_hal_bb_query_pkt_detect_thold(struct hal_info_t *hal_info, + bool get_en_info, + enum phl_phy_idx phy_idx) +{ + return halbb_querry_pd_lower_bound(hal_info->bb, get_en_info, phy_idx); +} +#endif + +#ifdef CONFIG_PHL_DFS +bool rtw_hal_in_radar_domain(void *hal, + u8 ch, enum channel_width bw) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return halbb_is_dfs_band(hal_info->bb, ch, bw); +} + +enum rtw_hal_status +rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en) +{ + if (dfs_en) + halbb_radar_detect_enable(hal_info->bb); + else + halbb_radar_detect_disable(hal_info->bb); + return RTW_HAL_STATUS_SUCCESS; +} + +bool +rtw_hal_bb_radar_detect(struct hal_info_t *hal_info, + struct hal_dfs_rpt *hal_dfs) +{ + + return halbb_radar_detect(hal_info->bb, hal_dfs); +} +#endif /*CONFIG_PHL_DFS*/ + +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_hal_status +rtw_hal_bb_ch_info_parsing(struct hal_info_t *hal_info, + u8 *addr, u32 len, u8 *rpt_buf, struct ch_rpt_hdr_info *ch_hdr_rpt, + struct phy_info_rpt *phy_rpt, struct ch_info_drv_rpt *drv) +{ + enum bb_ch_info_t chinfo_status = BB_CH_INFO_SUCCESS; + + chinfo_status = halbb_ch_info_parsing(hal_info->bb, addr, len, rpt_buf + , (void*)ch_hdr_rpt, (void *)phy_rpt, (void *)drv); + + if (chinfo_status == BB_CH_INFO_SUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else if (chinfo_status == BB_CH_INFO_LAST_SEG) + return RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG; + else + return RTW_HAL_STATUS_FAILURE; +} + +void +rtw_hal_bb_chan_info_cfg(struct hal_info_t *hal_info, struct chinfo_bbcr_cfg *bbcr) +{ + halbb_cfg_ch_info_cr(hal_info->bb, (void*)bbcr); +} +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +enum rtw_hal_status +rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("[HAL] call rtw_hal_bb_ctrl_btg !!!\n"); + + halbb_ctrl_btg(hal_info->bb, btg); + + return status; +} + +enum rtw_hal_status +rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("[HAL] call rtw_hal_bb_ctrl_btc_preagc !!!\n"); + + halbb_ctrl_btc_preagc(hal_info->bb, bt_en); + + return status; +} + +enum rtw_hal_status +rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("[HAL] call halbb_ctrl_rx_path !!!\n"); + + if(halbb_ctrl_rx_path(hal_info->bb, rx_path)) + status = RTW_HAL_STATUS_SUCCESS; + else + status = RTW_HAL_STATUS_FAILURE; + + return status; + +} + +enum rtw_hal_status +rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("[HAL] call halbb_ctrl_tx_path !!!\n"); + + if(halbb_ctrl_tx_path(hal_info->bb, tx_path)) + status = RTW_HAL_STATUS_SUCCESS; + else + status = RTW_HAL_STATUS_FAILURE; + return status; +} + +enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_ok) +{ + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL BB API]%s\n", __FUNCTION__); + + *rx_ok = halbb_mp_get_rx_crc_ok(hal_info->bb, cur_phy_idx); + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_crc_err) +{ + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL BB API]%s\n", __FUNCTION__); + + *rx_crc_err = halbb_mp_get_rx_crc_err(hal_info->bb, cur_phy_idx); + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_INFO("[HAL] call halbb_mp_seset_cnt !!!\n"); + halbb_mp_reset_cnt(hal_info->bb); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm, + enum phl_phy_idx phy_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + PHL_INFO("[MP HAL API] %s: call halbb_set_txpwr_dbm \n", __FUNCTION__); + PHL_INFO("[MP HAL API] %s: power_dbm = %d\n", __FUNCTION__, power_dbm); + + if(halbb_set_txpwr_dbm(hal_info->bb, power_dbm, phy_idx)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + hal_status = RTW_HAL_STATUS_FAILURE; + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm, + enum phl_phy_idx phy_idx) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + PHL_INFO("[MP HAL API] %s: call halbb_get_txpwr_dbm \n", __FUNCTION__); + *power_dbm = halbb_get_txpwr_dbm(hal_info->bb, phy_idx); + PHL_INFO("[MP HAL API] %s: power_dbm = %d\n", __FUNCTION__, *power_dbm); + return ret; +} + +enum rtw_hal_status +rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_INFO("[MP HAL API] %s: call halbb_set_txpwr_idx\n", __FUNCTION__); + + if (is_cck) { + if(halbb_set_cck_txpwr_idx(hal_info->bb, pwr_idx, tx_path)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + hal_status = RTW_HAL_STATUS_FAILURE; + + } else { + if(halbb_set_ofdm_txpwr_idx(hal_info->bb, pwr_idx, tx_path)) + hal_status = RTW_HAL_STATUS_SUCCESS; + else + hal_status = RTW_HAL_STATUS_FAILURE; + } + return hal_status; +} + +enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx, enum rf_path tx_path, bool is_cck){ + int ret = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_INFO("[MP HAL API] %s: call halbb_get_txpwr_idx\n", __FUNCTION__); + + if (is_cck) { + PHL_INFO("[MP HAL API] call halbb_get_cck_txpwr_idx\n"); + *pwr_idx = halbb_get_cck_txpwr_idx(hal_info->bb, tx_path); + + } else { + PHL_INFO("[MP HAL API] call halbb_get_ofdm_txpwr_idx\n"); + *pwr_idx = halbb_get_ofdm_txpwr_idx(hal_info->bb, tx_path); + } + + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com, + struct mp_plcp_param_t *plcp_tx_struct, + struct mp_usr_plcp_gen_in *plcp_usr_info, + enum phl_phy_idx plcp_phy_idx, + u8 *plcp_sts) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + PHL_INFO("%s\n", __FUNCTION__); + + *plcp_sts = halbb_plcp_gen(hal_info->bb, (void*)plcp_tx_struct,(void*)plcp_usr_info,plcp_phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, u8 is_cck, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct halbb_pmac_info tx_info = {0}; + + PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n", + __FUNCTION__, enable, is_cck, phy_idx); + + tx_info.en_pmac_tx = enable; + tx_info.is_cck = is_cck; + tx_info.mode = CONT_TX; + + halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct halbb_pmac_info tx_info = {0}; + + PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n", + __FUNCTION__, enable, is_cck, phy_idx); + PHL_INFO("%s: tx_cnt = %d period = %d tx_time = %d\n", + __FUNCTION__, tx_cnt, period, tx_time); + + tx_info.en_pmac_tx = enable; + tx_info.is_cck = is_cck; + tx_info.mode = PKTS_TX; + tx_info.tx_cnt = tx_cnt; + tx_info.period = period; + tx_info.tx_time = tx_time; + + halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt, u8 tx_duty, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct halbb_pmac_info tx_info = {0}; + + PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n", + __FUNCTION__, enable, is_cck, phy_idx); + PHL_INFO("%s: tx_cnt = %d\n", __FUNCTION__, tx_cnt); + PHL_INFO("%s: tx_duty = %d\n", __FUNCTION__, tx_duty); + + tx_info.en_pmac_tx = enable; + tx_info.is_cck = is_cck; + tx_info.mode = FW_TRIG_TX; + tx_info.tx_cnt = tx_cnt; + tx_info.duty_cycle = tx_duty; + + halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts, + struct rtw_phl_rx_pkt *phl_rx, u8 is_su) +{ + enum rtw_hal_status hstutus = RTW_HAL_STATUS_SUCCESS; + + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ppdu_sts *hal_ppdu = (struct hal_ppdu_sts *)ppdu_sts; + struct rtw_r_meta_data *mdata = &(phl_rx->r.mdata); + struct rtw_phl_ppdu_phy_info *phy_info = &(phl_rx->r.phy_info); + struct physts_rxd rxdesc = {0}; + struct physts_result bb_rpt = {0}; + u8 i = 0; + + + rxdesc.data_rate = mdata->rx_rate; + rxdesc.gi_ltf = mdata->rx_gi_ltf; + rxdesc.is_su = is_su; + rxdesc.macid_su = (u8)mdata->macid; + rxdesc.user_num = hal_ppdu->usr_num; + rxdesc.is_to_self = mdata->a1_match; + rxdesc.phy_idx = (mdata->bb_sel == 0) ? HW_PHY_0 : HW_PHY_1; + + for (i = 0; i < rxdesc.user_num; i++) { + rxdesc.user_i[i].macid = (u8)hal_ppdu->usr[i].macid; + rxdesc.user_i[i].is_data = hal_ppdu->usr[i].has_data; + rxdesc.user_i[i].is_ctrl = hal_ppdu->usr[i].has_ctrl; + rxdesc.user_i[i].is_mgnt = hal_ppdu->usr[i].has_ctrl; + rxdesc.user_i[i].is_bcn = hal_ppdu->usr[i].has_bcn; + } + + halbb_physts_parsing(hal_info->bb, hal_ppdu->phy_st_ptr, + (u16)hal_ppdu->phy_st_size, + &rxdesc, &bb_rpt); + + if ((bb_rpt.rssi_avg != 0) || (bb_rpt.physts_rpt_valid == 1)) { + phy_info->is_valid = true; + /* rssi from bb rpt, bit 0 is 0.0 ~ 0.9, removed it */ + phy_info->rssi = (bb_rpt.rssi_avg >> 1); + phy_info->ch_idx = bb_rpt.ch_idx; + phy_info->tx_bf = bb_rpt.is_bf; + for (i = 0; i < RTW_PHL_MAX_RF_PATH; i++) { + /* rssi from bb rpt, bit 0 is 0.0 ~ 0.9, removed it */ + phy_info->rssi_path[i] = (bb_rpt.rssi[i] >> 1); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "phy_info->rssi_path[%d] = %d\n", + i, phy_info->rssi_path[i]); + } +#ifdef RTW_WKARD_SINGLE_PATH_RSSI + if (RF_PATH_A == hal_info->hal_com->cur_rx_rfpath) { + phy_info->rssi = phy_info->rssi_path[0]; + } else if (RF_PATH_B == hal_info->hal_com->cur_rx_rfpath) { + phy_info->rssi = phy_info->rssi_path[1]; + } else if (RF_PATH_C == hal_info->hal_com->cur_rx_rfpath) { + phy_info->rssi = phy_info->rssi_path[2]; + } else if (RF_PATH_D == hal_info->hal_com->cur_rx_rfpath) { + phy_info->rssi = phy_info->rssi_path[3]; + } +#endif + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "avg_rssi %d ; ch_idx %d\n", + phy_info->rssi, phy_info->ch_idx); + } + + return hstutus; +} + +enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok) +{ + /* struct hal_info_t *hal_info = (struct hal_info_t *)hal; */ + + PHL_INFO("[HAL] call get halbb_mp_get_tx_ok !!!\n"); + /*tx_ok = halbb_mp_get_tx_ok(hal_info->bb, cur_phy_idx);*/ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path, s16 *txpwr_ref) +{ + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + if (is_cck) + *txpwr_ref = halbb_get_cck_ref_dbm(hal_info->bb, tx_path); + else + *txpwr_ref = halbb_get_ofdm_ref_dbm(hal_info->bb, tx_path); + + PHL_INFO("[MP HAL API] %s: txpwr_ref = %x\n", __FUNCTION__, *txpwr_ref); + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info, enum rf_path rx_path, u8 *rssi) +{ + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + *rssi = halbb_mp_get_rssi(hal_info->bb, rx_path); + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info, enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx) +{ + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + /* + ToDo: Should follow halbb master + [HALBB][8852A][B-Cut] Refine rssi structure from s32 to s8 + sha-1:f301ebb0e7cd0c1521d3c67e94c2dd4434d87f44 + + struct rssi_physts rssi_t; + *rssi_t = halbb_get_mp_rssi_physts(hal_info->bb, RF_PATH_AB, cur_phy_idx); + *rssi = rssi_t.rssi_seg[cur_phy_idx].rssi[0]; + *rssi = (*rssi<<8)|rssi_t.rssi_seg[cur_phy_idx].rssi[1]; + */ + return ret; +} + +enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user, u8 strm, u8 rxevm_table, u8 *rx_evm) +{ + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + *rx_evm = halbb_mp_get_rxevm(hal_info->bb, user, strm, rxevm_table); + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm, + u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm) +{ + + struct rxevm_physts evm; + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + evm = halbb_mp_get_rxevm_physts(hal_info->bb, cur_phy_idx); + *phy0_user0_rxevm = evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_3; + *phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_2; + *phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1; + *phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0; + + *phy0_user1_rxevm = evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_3; + *phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_2; + *phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_1; + *phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_0; + + *phy0_user2_rxevm = evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_3; + *phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_2; + *phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_1; + *phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_0; + + *phy0_user3_rxevm = evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_3; + *phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_2; + *phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_1; + *phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_0; + + *phy1_user0_rxevm = evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_3; + *phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_2; + *phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_1; + *phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_0; + + *phy1_user1_rxevm = evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_3; + *phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_2; + *phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_1; + *phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_0; + + *phy1_user2_rxevm = evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_3; + *phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_2; + *phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_1; + *phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_0; + + *phy1_user3_rxevm = evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_3; + *phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_2; + *phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_1; + *phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_0; + + return ret; +} + +/* mode: 0 = tmac, 1 = pmac */ +enum rtw_hal_status +rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, + u8 mode) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + if(mode == 0) { + PHL_INFO("%s: tmac mode\n", __FUNCTION__); + halbb_set_tmac_tx(hal_info->bb, phy_idx); + } + else { + PHL_INFO("%s: pmac mode\n", __FUNCTION__); + } + + return ret; +} + +enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc, + enum phl_phy_idx phy_idx) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + PHL_INFO("[HAL] call halbb_set_txsc !!!\n"); + + if(halbb_set_txsc(hal_info->bb, txsc, phy_idx)) + status = RTW_HAL_STATUS_SUCCESS; + else + status = RTW_HAL_STATUS_FAILURE; + + return status; +} + + +u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch, + u8 central_ch, enum channel_width cbw, enum channel_width dbw) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + + return halbb_get_txsc(hal_info->bb, pri_ch, central_ch, cbw, dbw); +} + +u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h) +{ +#ifdef RTW_WKARD_BB_C2H + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 cls = c2h->c2h_class; + u8 func = c2h->c2h_func; + u16 len = c2h->content_len; + u8 *buf = c2h->content; + + return rtw_halbb_c2h_parsing(hal_info->bb, cls, func, (u8)len, buf); +#else + return 0; +#endif +} + +u16 rtw_hal_bb_get_su_rx_rate(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + struct bb_pkt_cnt_su_info rpt; + u16 max_num_tmp = 0; + u16 rx_rate = 0; + u16 i = 0; + u16 *pkt_cnt_tmp; + u8 rate_num_tmp; + u16 ofst_mode = 0; + u16 ofst_ss = 0; + u16 idx = 0; + bool is_ht_mode = false; + bool is_legacy_rate = true; + + halbb_get_rx_pkt_cnt_rpt_su(hal_info->bb, &rpt); + + /*Legacy rate*/ + if (rpt.pkt_cnt_cck || rpt.pkt_cnt_ofdm) { + for (i = 0; i < 12; i++) { + if (rpt.pkt_cnt_legacy[i] >= max_num_tmp) { + max_num_tmp = rpt.pkt_cnt_legacy[i]; + rx_rate = i; + } + } + } + if (rpt.pkt_cnt_t == 0) { + return rx_rate; + } + /*HT, VHT, HE*/ + if (rpt.he_pkt_not_zero) { + pkt_cnt_tmp = rpt.pkt_cnt_he; + rate_num_tmp = 24; + ofst_mode = 0x180; + } else if (rpt.vht_pkt_not_zero) { + pkt_cnt_tmp = rpt.pkt_cnt_vht; + rate_num_tmp = 24; + ofst_mode = 0x100; + } else if (rpt.ht_pkt_not_zero) { + pkt_cnt_tmp = rpt.pkt_cnt_ht; + rate_num_tmp = 16; + ofst_mode = 0x80; + is_ht_mode = true; + } else { + return rx_rate; + } + for (i = 0; i < rate_num_tmp; i++) { + if (pkt_cnt_tmp[i] >= max_num_tmp) { + max_num_tmp = pkt_cnt_tmp[i]; + idx = i; + is_legacy_rate = false; + } + } + if (is_legacy_rate) + return rx_rate; + if (!is_ht_mode) { + ofst_ss = idx / HE_VHT_NUM_MCS; + + if (ofst_ss >= 0) /*>=2SS*/ + idx -= (ofst_ss * HE_VHT_NUM_MCS); + } + rx_rate = ofst_mode + (ofst_ss << 4) + idx; + return rx_rate; +} + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_hal_status +rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + + rtw_hal_init_bb_reg(hal_info); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + /* BB DBCC Settings */ + rtw_hal_bb_cfg_dbcc(hal_info, dbcc_en); + /* enable/disable rf */ + hal_status = rtw_hal_rf_ctrl_dbcc(hal_info->hal_com, dbcc_en); + if (RTW_HAL_STATUS_SUCCESS != hal_status) { + hal_status = RTW_HAL_STATUS_FAILURE; + } + + return hal_status; +} +#endif + +enum rtw_hal_status +rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info, + s16 *txinfo_power_dbm) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s: call halbb_get_txinfo_txpwr_dbm \n", + __FUNCTION__); + + *txinfo_power_dbm = halbb_get_txinfo_txpwr_dbm(hal_info->bb); + + PHL_INFO("[MP HAL API] %s: txinfo_power_dbm = %d\n", + __FUNCTION__, *txinfo_power_dbm); + return ret; +} + +enum rtw_hal_status +rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info, + enum phl_rf_mode rf_mode){ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s: call rtw_hal_bb_ctrl_rf_mode \n", + __FUNCTION__); + + halbb_ctrl_rf_mode(hal_info->bb, rf_mode); + + return ret; +} + +enum rtw_hal_status +rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info, + u16 staid, enum phl_phy_idx phy_idx) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + halbb_set_sta_id(hal_info->bb, staid, phy_idx); + + return ret; +} + +enum rtw_hal_status +rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info, + u8 bsscolor, enum phl_phy_idx phy_idx) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + halbb_set_bss_color(hal_info->bb, bsscolor, phy_idx); + + return ret; +} + +#ifdef RTW_WKARD_DEF_CMACTBL_CFG +enum rtw_hal_status +rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info, + enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + halbb_ctrl_trx_path(hal_info->bb, tx, tx_nss, rx, rx_nss); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "tx_ant(%d) tx_nss(%d) rx_ant(%d) rx_nss(%d)\n", + tx, tx_nss, rx, rx_nss); + return ret; +} + +u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info, + enum rf_path tx_path) +{ + u16 ret; + + ret = (BIT(RF_PATH_A) | BIT(RF_PATH_B))|(RF_PATH_A<<4)|(RF_PATH_B<<6); + ret = halbb_cfg_cmac_tx_ant(hal_info->bb, tx_path); + + return ret; +} +#endif + +enum rtw_hal_status +rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s ==>start\n", __FUNCTION__); + + halbb_backup_info(hal_info->bb, cur_phy_idx); + + PHL_INFO("[MP HAL API] %s ==>end\n", __FUNCTION__); + + return ret; +} + +enum rtw_hal_status +rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s ==>start\n", __FUNCTION__); + + halbb_restore_info(hal_info->bb, cur_phy_idx); + + PHL_INFO("[MP HAL API] %s ==>end\n", __FUNCTION__); + + return ret; +} + +void rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + halbb_set_tx_pow_ref(hal_info->bb, phy_idx); +} + +#ifdef CONFIG_RTW_ACS +void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time) +{ + struct ccx_para_info para = {0}; + struct env_trig_rpt trig_rpt = {0}; + + para.rac_lv = RAC_LV_3; + para.mntr_time = monitor_time; + /*clm para*/ + para.clm_app = CLM_ACS; + para.clm_input_opt = CLM_CCA_P20; + + /*nhm para*/ + para.nhm_app = NHM_ACS; + para.nhm_incld_cca = NHM_INCLUDE_CCA; + + halbb_env_mntr_trigger(hal_info->bb, ¶, &trig_rpt); +} + +enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt) +{ + u8 result = 0; + struct env_mntr_rpt mntr_rpt = {0}; + struct auto_chan_sel_report *acs_rpt = (struct auto_chan_sel_report *)rpt; + + result = halbb_env_mntr_result(hal_info->bb, &mntr_rpt); + + if ((result & (CLM_SUCCESS | NHM_SUCCESS)) != (CLM_SUCCESS | NHM_SUCCESS)) { + return RTW_HAL_STATUS_FAILURE; + } else { + acs_rpt->clm_ratio = mntr_rpt.clm_ratio; + acs_rpt->nhm_pwr = mntr_rpt.nhm_pwr; + return RTW_HAL_STATUS_SUCCESS; + } +} +#endif /* CONFIG_RTW_ACS */ + +enum rtw_hal_status +rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + halbb_tssi_bb_reset(hal_info->bb); + + return RTW_HAL_STATUS_SUCCESS; +} +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en) +{ + halbb_dcr_en(hal_info->bb, en); + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, + "rtw_hal_bb_dcr_en : %d \n", (en ? 1 : 0)); + return; +} + +bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info) +{ + bool ret = true; + if (0 == halbb_dyn_csi_rsp_rlt_get(hal_info->bb)) { + ret = false; + } + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, + "rtw_hal_bb_csi_rsp : %d \n", (ret ? 1 : 0)); + return ret; +} +#endif + +void rtw_hal_bb_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx) +{ + halbb_wifi_event_notify(hal_info->bb, event, phy_idx); +} + +void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx) +{ + halbb_bb_cmd_notify(hal_info->bb, hal_cmd, phy_idx); +} + +enum rtw_hal_status +rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset, + enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck) +{ + if(iscck) + halbb_normal_efuse_verify_cck(hal_info->bb, rx_gain_offset, rx_path, phy_idx); + else + halbb_normal_efuse_verify(hal_info->bb, rx_gain_offset, rx_path, phy_idx); + + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + halbb_get_efuse_init(hal_info->bb); + PHL_INFO("[HAL API] %s ==>end\n", __FUNCTION__); +} +enum rtw_hal_status +rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + PHL_INFO("%s: pdp_bypass = %d phy_idx = %d\n", + __FUNCTION__, pdp_bypass, phy_idx); + + halbb_dpd_bypass(hal_info->bb, pdp_bypass, phy_idx); + return RTW_HAL_STATUS_SUCCESS; +} + + +void rtw_hal_bb_gpio_setting(struct rtw_hal_com_t *hal_com, u8 gpio_idx, u8 path, + bool inv, u8 src) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + + halbb_gpio_setting(hal_info->bb, gpio_idx, path, inv, src); +} + +void rtw_hal_bb_gpio_setting_all(struct rtw_hal_com_t *hal_com, u8 rfe_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + + halbb_gpio_setting_all(hal_info->bb, rfe_idx); +} + +bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx) +{ + return halbb_chk_tx_idle(hal_info->bb, phy_idx); +} + +static enum rtw_hal_status +_cnvrt_rainfo_to_rate(enum hal_rate_mode rate_mode, u8 mcs_ss_idx, + enum rtw_data_rate *data_rate) +{ + enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE; + u16 rate_idx = 0, ss = 0; + + switch(rate_mode) { + case HAL_LEGACY_MODE: + rate_idx = (u16)(mcs_ss_idx & 0xf); + ss = 0; + hal_sts = RTW_HAL_STATUS_SUCCESS; + break; + case HAL_HT_MODE: + rate_idx = (u16)(mcs_ss_idx & 0x1f); + ss = 0; + hal_sts = RTW_HAL_STATUS_SUCCESS; + break; + case HAL_VHT_MODE: + case HAL_HE_MODE: + rate_idx = (u16)(mcs_ss_idx & 0xf); + ss = (mcs_ss_idx & 0x30) >> 4; + hal_sts = RTW_HAL_STATUS_SUCCESS; + break; + default: + PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_, + "%s : incorrect rate mode(0x%x), fail to covert rate\n", + __func__, rate_mode); + hal_sts = RTW_HAL_STATUS_FAILURE; + break; + } + + if (RTW_HAL_STATUS_SUCCESS == hal_sts) + *data_rate = rate_idx | (ss << 4) | (rate_mode << 7); + + return hal_sts; +} + +enum rtw_hal_status +rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info) +{ + halbb_dm_init(hal_info->bb, HW_PHY_0); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo) +{ + enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE; + struct rtw_rate_info *rainfo = NULL; + + do { + if (NULL == hal_sta) { + PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_, + "%s : hal_sta is NULL\n", + __func__); + break; + } + + if (NULL == phl_rainfo) { + PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_, + "%s : Input parameter is NULL\n", + __func__); + break; + } + + rainfo = &hal_sta->ra_info.rpt_rt_i; + + phl_rainfo->gi_ltf = rainfo->gi_ltf; + if (HAL_RATE_BW_20 == rainfo->bw) { + phl_rainfo->bw = CHANNEL_WIDTH_20; + } else if (HAL_RATE_BW_40 == rainfo->bw) { + phl_rainfo->bw = CHANNEL_WIDTH_40; + } else if (HAL_RATE_BW_80 == rainfo->bw) { + phl_rainfo->bw = CHANNEL_WIDTH_80; + } else if (HAL_RATE_BW_160 == rainfo->bw) { + phl_rainfo->bw = CHANNEL_WIDTH_160; + } else { + PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_, + "%s : incorrect bw(0x%x), fail to covert rate\n", + __func__, rainfo->bw); + break; + } + + if (RTW_HAL_STATUS_SUCCESS == + _cnvrt_rainfo_to_rate(rainfo->mode, + rainfo->mcs_ss_idx, + &phl_rainfo->rate)) { + hal_sts = RTW_HAL_STATUS_SUCCESS; + break; + } else { + break; + } + } while (false); + + return hal_sts; +} + +void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + struct env_mntr_rpt mntr_rpt = {0}; + struct watchdog_nhm_report *nhm_rpt = (struct watchdog_nhm_report *)rpt; + + halbb_env_mntr_get_bg_result(hal_info->bb, &mntr_rpt, phy_idx); + + nhm_rpt->ccx_rpt_stamp = mntr_rpt.ccx_rpt_stamp; + nhm_rpt->ccx_rpt_result = mntr_rpt.ccx_rpt_result; + nhm_rpt->nhm_pwr_dbm = (s8) ((s16) mntr_rpt.nhm_pwr - 110); + nhm_rpt->nhm_ratio = mntr_rpt.nhm_ratio; +} + +void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx) +{ + u8 is_ofdm = (is_cck == 0)?1:0; + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + struct rtw_tpu_info *tpu = &hal_info->hal_com->band[phy_idx].rtw_tpu_i; + tpu->tx_ptrn_shap_idx = sharp_id; + + halbb_set_tx_pow_pattern_shap(hal_info->bb, channel, is_ofdm, phy_idx); +} + +void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, + enum phl_phy_idx phy_indx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv); + struct env_mntr_rpt bg_rpt = {0}; + u8 env_rpt_status = 0; + + halbb_env_mntr_get_bg_result(hal_info->bb, &bg_rpt, phy_indx); + env_rpt_status = bg_rpt.ccx_rpt_result; + env_rpt_status = env_rpt_status & CCX_SUCCESS; + + /*if ok update env rpt */ + if (env_rpt_status == CCX_SUCCESS) { + env_rpt->clm_ratio = bg_rpt.clm_ratio; + env_rpt->nhm_pwr = bg_rpt.nhm_pwr; + env_rpt->nhm_ratio = bg_rpt.nhm_ratio; + env_rpt->nhm_cca_ratio = bg_rpt.nhm_cca_ratio; + env_rpt->rpt_status = 1; + } else { + env_rpt->rpt_status = 0; + } +} + +enum rtw_hal_status +rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info, + s16 ofst, enum phl_phy_idx phy_idx) +{ + bool ret = false; + + ret = halbb_set_pwr_ul_tb_ofst(hal_info->bb, ofst, phy_idx); + if (ret == true) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status +rtw_hal_bb_upd_mcc_macid(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *mrole) +{ + bool ret = false; + struct bb_mcc_i mi = {0}; + + mi.type = mrole->wrole->type; + mi.self_macid = (u8)mrole->macid; + mi.chandef = mrole->chandef; + mi.macid_bitmap = mrole->used_macid.bitmap; + mi.macid_map_len = mrole->used_macid.len; + + ret = halbb_upd_mcc_macid(hal_info->bb, &mi); + + if (ret == true) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +void +rtw_hal_bb_mcc_stop(struct hal_info_t *hal_info) +{ + halbb_mcc_stop(hal_info->bb); +} + +enum rtw_hal_status +rtw_hal_bb_mcc_start(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *m_role1, + struct rtw_phl_mcc_role *m_role2) +{ + bool ret = false; + struct bb_mcc_i mi_1 = {0}, mi_2 = {0}; + + mi_1.type = m_role1->wrole->type; + mi_1.self_macid = (u8)m_role1->macid; + mi_1.chandef = m_role1->chandef; + mi_1.macid_bitmap = m_role1->used_macid.bitmap; + mi_1.macid_map_len = m_role1->used_macid.len; + + mi_2.type = m_role2->wrole->type; + mi_2.self_macid = (u8)m_role2->macid; + mi_2.chandef = m_role2->chandef; + mi_2.macid_bitmap = m_role2->used_macid.bitmap; + mi_2.macid_map_len = m_role2->used_macid.len; + + ret = halbb_mcc_start(hal_info->bb, &mi_1, &mi_2); + + if (ret == true) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} +#endif + + +#else /*ifndef USE_TRUE_PHY*/ +enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx) +{ + return HW_PHY_0; +} + +void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en) +{ +} + +void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path) +{ +} + +void rtw_hal_bb_adc_en(struct hal_info_t *hal_info, bool en) +{ +} + +void rtw_hal_bb_reset_en(struct hal_info_t *hal_info, bool en, enum phl_phy_idx phy_idx) +{ +} +bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + return true; +} + +enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_reset(struct hal_info_t *hal_info) +{ +} + +void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info) +{ +} + +void rtw_hal_bb_dm_init(struct hal_info_t *hal_info) +{ +} + +void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ +} + +enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com, + bool cca_en, enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ +} + +void rtw_hal_init_bb_reg(struct hal_info_t *hal_info) +{ +} + +void rtw_hal_bb_init_reg_by_hdr(struct hal_info_t *hal_info, u32 *folder_array, + u32 folder_len, u8 is_form_folder, enum phl_phy_idx phy_idx) + +{ +} + +u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask, u32 data) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask, u32 data) +{ + return true; +} + +u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask, + u32 data) +{ + return true; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, bool is_connected) +{ +} + +enum rtw_hal_status +rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_register(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ra_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +u8 rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com, u8 *efuse_map, + enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +u8 hal_get_primary_channel_idx(u8 pri_ch, u8 central_ch, enum channel_width bw, + enum chan_offset bw_offset) +{ + return 0; +} + +enum rtw_hal_status rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info, + enum phl_phy_idx phy_idx, + u8 pri_ch, + u8 central_ch_seg0, + u8 central_ch_seg1, + enum band_type band, + enum channel_width bw) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_in_radar_domain(void *hal, u8 ch, enum channel_width bw) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_bb_radar_detect(struct hal_info_t *hal_info, + struct hal_dfs_rpt *hal_dfs) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info, + u8 cur_phy_idx, u32 *rx_ok) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info, + u8 cur_phy_idx, u32 *rx_crc_err) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx, + enum rf_path tx_path, bool is_cck) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com, + struct mp_plcp_param_t *plcp_tx_struct, + struct mp_usr_plcp_gen_in *plcp_usr_info, + enum phl_phy_idx plcp_phy_idx, + u8 *plcp_sts) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt, u8 tx_duty, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts, + struct rtw_phl_rx_pkt *phl_rx, u8 is_su) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path, + s16 *txpwr_ref) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info, + enum rf_path rx_path, u8 *rssi) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info, + enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user, + u8 strm, u8 rxevm_table, u8 *rx_evm) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm, + u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +/* mode: 0 = tmac, 1 = pmac */ +enum rtw_hal_status +rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, u8 mode) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_FAILURE; +} + +u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch, + u8 central_ch, enum channel_width cbw, enum channel_width dbw) +{ + return 0; +} + +u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h) +{ + return 0; +} + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_hal_status +rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} +enum rtw_hal_status +rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} +#endif + +enum rtw_hal_status +rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info, + s16 *txinfo_power_dbm) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info, + enum phl_rf_mode rf_mode){ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info, + u16 staid, enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info, + u8 bsscolor, enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef RTW_WKARD_DEF_CMACTBL_CFG +enum rtw_hal_status +rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info, + enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info, + enum rf_path tx_path) +{ + return 0; +} +#endif + +enum rtw_hal_status +rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx) +{ +} + +enum rtw_hal_status +rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_RTW_ACS +void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time) +{ + +} + +enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt) +{ + return RTW_HAL_STATUS_FAILURE; +} +#endif /* CONFIG_RTW_ACS */ +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en) +{ + return; +} + +bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info) +{ + return true; +} + + +#endif + +void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com) +{ + +} + +void rtw_hal_bb_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx) +{ + +} + +void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx) +{ + +} + +enum rtw_hal_status +rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass, + enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset, + enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx) +{ + return false; +} + +enum rtw_hal_status +rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info) +{ + + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo) +{ + return RTW_HAL_STATUS_FAILURE; +} + + +void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx) +{ + +} + + +void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx) +{ + +} + +void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, + enum phl_phy_idx phy_indx) +{ + +} + + +enum rtw_hal_status +rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info, + s16 ofst, enum phl_phy_idx phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status +rtw_hal_bb_upd_mcc_macid(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *mrole) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void +rtw_hal_bb_mcc_stop(struct hal_info_t *hal_info) +{ + +} + +enum rtw_hal_status +rtw_hal_bb_mcc_start(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *m_role1, + struct rtw_phl_mcc_role *m_role2) +{ + return RTW_HAL_STATUS_SUCCESS; +} +#endif +#endif /*ifdef USE_TRUE_PHY*/ diff --git a/phl/hal_g6/hal_api_bb.h b/phl/hal_g6/hal_api_bb.h new file mode 100644 index 0000000..060a8cf --- /dev/null +++ b/phl/hal_g6/hal_api_bb.h @@ -0,0 +1,258 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_BB_H_ +#define _HAL_API_BB_H_ +enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx); +void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en); +void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path); +void rtw_hal_bb_adc_en(struct hal_info_t *hal_info,bool en); +void rtw_hal_bb_reset_en(struct hal_info_t *hal_info,bool en, enum phl_phy_idx phy_idx); + +bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, u32 out_len); + +enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps); +enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en); + +void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info); + +void rtw_hal_bb_reset(struct hal_info_t *hal_info); + +void rtw_hal_bb_dm_init(struct hal_info_t *hal_info); + +void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com, + bool cca_en, enum phl_phy_idx phy_idx); +enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en); +enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en); + +u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); + +void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); + +void rtw_hal_init_bb_reg(struct hal_info_t *hal_info); + +u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask); + +bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask, u32 data); + +u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask); + +bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com, + u32 addr, u32 mask, u32 data); + +enum rtw_hal_status +rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, bool is_connected); +enum rtw_hal_status +rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_bb_ra_update(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_bb_ra_register(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +u8 +rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info, + enum phl_phy_idx phy_idx, + u8 pri_ch, + u8 central_ch_seg0, + u8 central_ch_seg1, + enum band_type band, + enum channel_width bw); +#ifdef CONFIG_PHL_CUSTOM_FEATURE +enum rtw_hal_status +rtw_hal_bb_set_pop_en(struct hal_info_t *hal_info, + bool en, + enum phl_phy_idx phy_idx); + +bool +rtw_hal_bb_query_pop_en(struct hal_info_t *hal_info, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_pkt_detect_thold(struct hal_info_t *hal_info, u32 bound); + +u8 +rtw_hal_bb_query_pkt_detect_thold(struct hal_info_t *hal_info, + bool get_en_info, + enum phl_phy_idx phy_idx); +#endif +#ifdef CONFIG_RTW_ACS +void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time); +enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt); +#endif /* CONFIG_RTW_ACS */ +#ifdef CONFIG_PHL_DFS +enum rtw_hal_status +rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en); +bool +rtw_hal_bb_radar_detect(struct hal_info_t *hal_info, + struct hal_dfs_rpt *hal_dfs); + +#endif + +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_hal_status +rtw_hal_bb_ch_info_parsing(struct hal_info_t *hal_info, + u8 *addr, u32 len, u8 *rpt_buf, struct ch_rpt_hdr_info *ch_hdr_rpt, + struct phy_info_rpt *phy_rpt, struct ch_info_drv_rpt *drv); + +void +rtw_hal_bb_chan_info_cfg(struct hal_info_t *hal_info, struct chinfo_bbcr_cfg *bbcr); +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_ok); + +enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_crc_err); + +enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal); + +enum rtw_hal_status rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck); + +enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx, enum rf_path tx_path, bool is_cck); + +enum rtw_hal_status +rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts, + struct rtw_phl_rx_pkt *phl_rx, u8 is_su); + +enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok); + +enum rtw_hal_status rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path, s16 *txpwr_ref); + +enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info, enum rf_path rx_path, u8 *rssi); + +enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info, enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx); + +enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user, u8 strm, u8 rxevm_table, u8 *rx_evm); + +enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm, + u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm); + +enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc, + enum phl_phy_idx phy_idx); +u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h); + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_hal_status +rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en); + +enum rtw_hal_status +rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info, + struct rtw_phl_com_t *phl_com, bool dbcc_en); +#endif + +enum rtw_hal_status +rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info, + s16 *txinfo_power_dbm); + +enum rtw_hal_status +rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info, + enum phl_rf_mode rf_mode); + +enum rtw_hal_status +rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info, + u16 staid, enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info, + u8 bsscolor, enum phl_phy_idx phy_idx); + +#ifdef RTW_WKARD_DEF_CMACTBL_CFG +enum rtw_hal_status +rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info, + enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss); + +u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info, + enum rf_path tx_path); +#endif + +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en); +bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info); +#endif + +void rtw_hal_bb_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx); + +void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset, + enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck); + +void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com); + +enum rtw_hal_status +rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info); + +bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo); + +enum rtw_hal_status +rtw_hal_bb_query_txsts_rpt(struct hal_info_t *hal_info, + u16 macid0, u16 macid1); + +enum rtw_hal_status +rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info, + s16 ofst, enum phl_phy_idx phy_idx); +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status +rtw_hal_bb_upd_mcc_macid(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *mrole); + +void +rtw_hal_bb_mcc_stop(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_bb_mcc_start(struct hal_info_t *hal_info, + struct rtw_phl_mcc_role *m_role1, + struct rtw_phl_mcc_role *m_role2); +#endif +#endif /*_HAL_API_BB_H_*/ diff --git a/phl/hal_g6/hal_api_btc.c b/phl/hal_g6/hal_api_btc.c new file mode 100644 index 0000000..3caee07 --- /dev/null +++ b/phl/hal_g6/hal_api_btc.c @@ -0,0 +1,657 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_BTC_C_ +#include "hal_headers.h" +#include "btc/hal_btc.h" + +#ifdef CONFIG_BTCOEX +/******************************************* + * C2H FW message + *******************************************/ +#define BTC_FWBUF_NUM 4 +struct fw_msg_entry { + _os_list list; + u8 c2h_class; + u8 c2h_func; + u16 len; + u8 buf[RTW_PHL_BTC_FWINFO_BUF]; +}; + +static void _bt_msg_init(struct rtw_hal_com_t *hal_com, + struct hal_bt_msg *msg) +{ + void *d = halcom_to_drvpriv(hal_com); + + _os_spinlock_init(d, &msg->lock); + _os_mem_set(d, &msg->latest[0], 0, RTW_BTC_OVERWRITE_BUF_LEN); + _os_mem_set(d, &msg->working[0], 0, RTW_BTC_OVERWRITE_BUF_LEN); + msg->len = 0; + msg->cnt = 0; +} + +static void _bt_msg_deinit(struct rtw_hal_com_t *hal_com, + struct hal_bt_msg *msg) +{ + void *d = halcom_to_drvpriv(hal_com); + + _os_spinlock_free(d, &msg->lock); +} + +static void _msg_enq(struct rtw_hal_com_t *hal_com, + struct phl_queue *q, struct fw_msg_entry *entry) +{ + pq_push(halcom_to_drvpriv(hal_com), q, &entry->list, _tail, _bh); +} + +static struct fw_msg_entry *_msg_deq(struct rtw_hal_com_t *hal_com, + struct phl_queue *q) +{ + struct fw_msg_entry *entry = NULL; + _os_list *list = NULL; + + if (pq_pop(halcom_to_drvpriv(hal_com), q, &list, _first, _bh)) + entry = (struct fw_msg_entry *)list; + + return entry; +} + +static bool _fw_msg_init(struct rtw_hal_com_t *hal_com) +{ + void *d = halcom_to_drvpriv(hal_com); + struct btc_fw_msg *fw_msg = &hal_com->btc_msg; + struct fw_msg_entry *entry = NULL; + u16 i = 0; + + _os_spinlock_init(d, &fw_msg->lock); + fw_msg->fev_cnt = 0; + + _bt_msg_init(hal_com, &fw_msg->btinfo); + _bt_msg_init(hal_com, &fw_msg->scbd); + + pq_init(d, &fw_msg->idleq); + pq_init(d, &fw_msg->waitq); + for (i = 0; i < BTC_FWBUF_NUM; i++) { + entry = (struct fw_msg_entry *)_os_kmem_alloc(d, + sizeof(struct fw_msg_entry)); + if (entry) + _msg_enq(hal_com, &fw_msg->idleq, entry); + else + return false; + } + + return true; +} + +static void _fw_msg_free(struct rtw_hal_com_t *hal_com) +{ + void *d = halcom_to_drvpriv(hal_com); + struct btc_fw_msg *fw_msg = &hal_com->btc_msg; + struct fw_msg_entry *entry = NULL; + + _bt_msg_deinit(hal_com, &fw_msg->btinfo); + _bt_msg_deinit(hal_com, &fw_msg->scbd); + + while (1) { + entry = _msg_deq(hal_com, &fw_msg->waitq); + if (entry) + _os_kmem_free(d, entry, sizeof(struct fw_msg_entry)); + else + break; + } + pq_deinit(d, &fw_msg->waitq); + + while (1) { + entry = _msg_deq(hal_com, &fw_msg->idleq); + if (entry) + _os_kmem_free(d, entry, sizeof(struct fw_msg_entry)); + else + break; + } + pq_deinit(d, &fw_msg->idleq); + + _os_spinlock_free(d, &fw_msg->lock); +} + +static void _copy_btmsg(struct rtw_hal_com_t *hal_com, + struct hal_bt_msg *msg, u16 len, u8 *buf) +{ + void *d = halcom_to_drvpriv(hal_com); + + if (len > RTW_BTC_OVERWRITE_BUF_LEN) + return; + + _os_spinlock(d, &msg->lock, _bh, NULL); + msg->cnt++; + msg->len = len; + _os_mem_cpy(d, &msg->latest[0], buf, len); + _os_spinunlock(d, &msg->lock, _bh, NULL); +} + +static bool _fw_evnt_enq(struct rtw_hal_com_t *hal_com, + u8 cls, u8 func, u16 len, u8 *buf) +{ + struct btc_fw_msg *fmsg = &hal_com->btc_msg; + void *d = halcom_to_drvpriv(hal_com); + struct fw_msg_entry *entry = NULL; + + entry = _msg_deq(hal_com, &fmsg->idleq); + if (!entry) + return false; + + entry->c2h_class = cls; + entry->c2h_func = func; + entry->len = len; + _os_mem_cpy(d, &entry->buf[0], buf, len); + _msg_enq(hal_com, &fmsg->waitq, entry); + + return true; +} + +enum rtw_hal_status rtw_hal_btc_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct btc_t *btc = NULL; + void *drv_priv = NULL; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "%s\n", __FUNCTION__); + + drv_priv = halcom_to_drvpriv(hal_info->hal_com); + btc = _os_mem_alloc(drv_priv, sizeof(struct btc_t)); + if (!btc) { + hal_status = RTW_HAL_STATUS_RESOURCE; + goto error_btc_init; + } + + /* assign phl_com & hal_com */ + btc->phl = phl_com; + btc->hal = hal_info->hal_com; + + if (!hal_btc_init(btc)) { + hal_status = RTW_HAL_STATUS_BTC_INIT_FAILURE; + goto error_btc_init; + } + + if (!_fw_msg_init(hal_info->hal_com)) { + hal_status = RTW_HAL_STATUS_BTC_INIT_FAILURE; + goto error_msg_init; + } + + + hal_status = RTW_HAL_STATUS_SUCCESS; + hal_info->btc = btc; + + return hal_status; + +error_msg_init: + _fw_msg_free(hal_info->hal_com); + +error_btc_init: + if (btc) { + _os_mem_free(drv_priv, (void *)btc, sizeof(struct btc_t)); + hal_info->btc = NULL; + } + + return hal_status; +} + +void rtw_hal_btc_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct btc_t *btc = hal_info->btc; + void *drv_priv = NULL; + + _fw_msg_free(hal_info->hal_com); + + drv_priv = halcom_to_drvpriv(hal_info->hal_com); + if (drv_priv && btc) { + hal_btc_deinit(btc); + _os_mem_free(drv_priv, (void *)btc, sizeof(struct btc_t)); + } +} + +/**********************/ +/* called by non-hal layers */ +/**********************/ +void rtw_hal_btc_update_role_info_ntfy(void *hinfo, u8 role_id, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + enum role_state rstate) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + struct btc_wl_link_info r = {0}; +#ifdef CONFIG_PHL_P2PPS + u8 i =0; +#endif /* CONFIG_PHL_P2PPS */ + + if (role_id >= MAX_WIFI_ROLE_NUMBER) + return; + + + if (wrole) { + r.role = wrole->type; +#ifdef RTW_WKARD_ROLE_TYPE + if (wrole->mstate != MLME_NO_LINK && + wrole->real_type != PHL_RTYPE_NONE) { + r.role = wrole->real_type; + PHL_INFO("[BTC], rtw_hal_btc_update_role_info_ntfy(): set r.role from type(%d) to real_type(%d)\n", + wrole->type, wrole->real_type); + } +#endif /* RTW_WKARD_ROLE_TYPE */ +#ifdef CONFIG_PHL_P2PPS + r.noa = 0; + r.noa_duration = 0; + for (i = 0; i < MAX_NOA_DESC; i++) { + if (wrole->noa_desc[i].enable) { + r.noa = 1; + r.noa_duration = wrole->noa_desc[i].duration; + break; + } + } +#endif /* CONFIG_PHL_P2PPS */ + r.phy = wrole->hw_band; + r.pid = wrole->hw_port; + r.active = wrole->active; + r.connected = wrole->mstate; + r.mode = wrole->cap.wmode; + r.client_cnt = wrole->assoc_sta_queue.cnt; + #ifdef RTW_PHL_BCN + r.bcn_period = wrole->bcn_cmn.bcn_interval; + r.dtim_period = wrole->dtim_period; + #endif + /* Remove it after btc ready */ + r.band = wrole->chandef.band; + r.ch = wrole->chandef.center_ch; + r.bw = wrole->chandef.bw; + hal_mem_cpy(h->hal_com, &r.chdef, &wrole->chandef, + sizeof(struct rtw_chan_def)); + hal_mem_cpy(h->hal_com, r.mac_addr, wrole->mac_addr, MAC_ALEN); + } + + if (sta && wrole->type == PHL_RTYPE_STATION) {/*associated node info??*/ + r.mac_id = sta->macid; + r.mode = (u8)sta->wmode; + } + + if (ops && ops->ntfy_role_info) + ops->ntfy_role_info(btc, role_id, &r, rstate); +} + +void rtw_hal_btc_power_on_ntfy(void *hinfo) +{ +} + +void rtw_hal_btc_power_off_ntfy(void *hinfo) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_power_off) + ops->ntfy_power_off(btc); +} + +void rtw_hal_btc_init_coex_cfg_ntfy(void *hinfo) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + u8 mode = btc->phl->dev_cap.btc_mode; + + if (ops && ops->ntfy_init_coex) + ops->ntfy_init_coex(btc, mode); +} + +void rtw_hal_btc_scan_start_ntfy(void *hinfo, enum phl_phy_idx phy_idx, + enum band_type band) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_scan_start) + ops->ntfy_scan_start(btc, phy_idx, band); +} + +void rtw_hal_btc_scan_finish_ntfy(void *hinfo, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_scan_finish) + ops->ntfy_scan_finish(btc, phy_idx); +} + +void rtw_hal_btc_switch_band_ntfy(void *hinfo, enum phl_phy_idx phy_idx, + enum band_type band) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_switch_band) + ops->ntfy_switch_band(btc, phy_idx, band); +} + +void rtw_hal_btc_packet_event_ntfy(void *hinfo, u8 pkt_evt_type) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_specific_packet) + ops->ntfy_specific_packet(btc, pkt_evt_type); +} + +void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_radio_state) + ops->ntfy_radio_state(btc, rf_state); +} + +void rtw_hal_btc_customerize_ntfy(void *hinfo, u8 type, u16 len, u8 *buf) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + + if (ops && ops->ntfy_customerize) + ops->ntfy_customerize(btc, type, len, buf); +} + +u8 rtw_hal_btc_wl_rfk_ntfy(struct rtw_hal_com_t *hal_com, u8 phy_idx, u8 rfk_type, u8 rfk_process) +{ + struct hal_info_t *h = hal_com->hal_priv; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + u8 val = 0; + + if (ops && ops->ntfy_wl_rfk) + val = ops->ntfy_wl_rfk(btc, phy_idx, rfk_type, rfk_process); + + return val; +} + +void rtw_hal_btc_wl_status_ntfy(void *hinfo, struct rtw_phl_com_t *phl_com, u8 ntfy_num, + struct rtw_phl_stainfo_t *sta[], u8 reason) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + struct btc_wl_stat_info stat_info[MAX_WIFI_ROLE_NUMBER] = {0}; + struct btc_traffic *t; + struct rtw_stats *phl_stats = &phl_com->phl_stats; + struct rtw_phl_rainfo ra_info = {0}; + u8 i; + + if(ntfy_num == 0) + return; + + for (i = 0; i < ntfy_num; i++) { + _os_mem_set(halcom_to_drvpriv(h->hal_com), &ra_info, 0, + sizeof(ra_info)); + + stat_info[i].pid = sta[i]->wrole->id; + stat_info[i].stat.rssi = sta[i]->hal_sta->rssi_stat.rssi >> 1; + + t = &stat_info[i].stat.traffic; + t->tx_lvl = phl_stats->tx_traffic.lvl; + t->tx_sts = phl_stats->tx_traffic.sts; + t->tx_1ss_limit = sta[i]->hal_sta->ra_info.ra_nss_limit; + + t->rx_lvl = phl_stats->rx_traffic.lvl; + t->rx_sts = phl_stats->rx_traffic.sts; + + if (RTW_HAL_STATUS_SUCCESS == + rtw_hal_bb_query_rainfo(h, sta[i]->hal_sta, &ra_info)) + t->tx_rate = ra_info.rate; + else + t->tx_rate = RTW_DATA_RATE_MAX; + + t->rx_rate = h->hal_com->trx_stat.rx_rate_plurality; + } + + if (ops && ops->ntfy_wl_sta) + ops->ntfy_wl_sta(btc, ntfy_num, stat_info, reason); + +} + +void rtw_hal_btc_fwinfo_ntfy(void *hinfo) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + struct rtw_hal_com_t *hal_com = h->hal_com; + void *d = halcom_to_drvpriv(hal_com); + struct btc_fw_msg *fmsg = &hal_com->btc_msg; + struct hal_bt_msg *bmsg = NULL; + struct fw_msg_entry *entry = NULL; + + _os_spinlock(d, &fmsg->lock, _bh, NULL); + fmsg->fev_cnt = 0; + _os_spinunlock(d, &fmsg->lock, _bh, NULL); + + if (!ops || !ops->ntfy_fwinfo) + return; + + /* bt score board notification */ + while (1) { + bmsg = &fmsg->scbd; + if (bmsg->cnt) { + _os_spinlock(d, &bmsg->lock, _bh, NULL); + bmsg->cnt = 0; + _os_mem_cpy(d, &bmsg->working[0], + &bmsg->latest[0], bmsg->len); + _os_spinunlock(d, &bmsg->lock, _bh, NULL); + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], scoreboard notify !! \n"); + ops->ntfy_fwinfo(btc, &bmsg->working[0], bmsg->len, + BTC_CLASS_FEV, BTC_FEV_BT_SCBD); + } else + break; + } + + /* bt info notification */ + while (1) { + bmsg = &fmsg->btinfo; + if (bmsg->cnt) { + _os_spinlock(d, &bmsg->lock, _bh, NULL); + bmsg->cnt = 0; + _os_mem_cpy(d, &bmsg->working[0], + &bmsg->latest[0], bmsg->len); + _os_spinunlock(d, &bmsg->lock, _bh, NULL); + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], bt info notify !! \n"); + ops->ntfy_fwinfo(btc, &bmsg->working[0], bmsg->len, + BTC_CLASS_FEV, BTC_FEV_BT_INFO); + } else + break; + } + + /* common btc fw events */ + while (1) { + entry = _msg_deq(hal_com, &fmsg->waitq); + if (entry) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], fw event notify !! \n"); + ops->ntfy_fwinfo(btc, entry->buf, entry->len, + entry->c2h_class, entry->c2h_func); + _msg_enq(hal_com, &fmsg->idleq, entry); + } + else + break; + } +} + +void rtw_hal_btc_timer(void *hinfo, void *timer) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + struct btc_ops *ops = btc->ops; + struct btc_tmr *btmr = NULL; + u8 i = 0; + bool found = false; + + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], %s(), timer = 0x%p !!\n", __func__, timer); + + if (!hinfo || !timer) + return; + + btmr = (struct btc_tmr *)timer; + + for (i = 0; i < BTC_TIMER_MAX; i++) { + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], %s(): btmr = 0x%p, &btc->timer[%d] = 0x%p \n", + __func__, btmr, i, &btc->timer[i]); + if (btmr == &btc->timer[i]) { + found = true; + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], %s(): found timer %p, id = %d \n", + __func__, btmr, btmr->id); + break; + } + } + + if (ops && found) { + if (btmr->id == BTC_TIMER_PERIODIC) { + struct rtw_wifi_role_t *wrole = NULL; + struct rtw_phl_stainfo_t *sta = NULL; + struct rtw_phl_stainfo_t *wrole_sta[MAX_WIFI_ROLE_NUMBER] = {0}; + u8 ntfy_num = 0; + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) { + wrole = &(btc->phl->wifi_roles[i]); + if(wrole->mstate == MLME_LINKED) { + sta = rtw_phl_get_stainfo_self( + btc->phl->phl_priv, wrole); + if(sta != NULL) { + wrole_sta[ntfy_num] = sta; + ntfy_num++; + } + } + } + rtw_hal_btc_wl_status_ntfy(hinfo, btc->phl, ntfy_num, + wrole_sta, PHL_BTC_NTFY_RSN_PERIOTIC); + } + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, + "[BTC], %s(): btmr->id = %d \n", + __func__, btmr->id); + if(ops->ntfy_timer) + ops->ntfy_timer(btc, btmr->id); + } else { + PHL_INFO("[BTC], %s(): not found, ops = 0x%p, found = %d \n", + __func__, ops, found); + } +} + +u32 rtw_hal_btc_req_bt_slot_t(void *hinfo) +{ + struct hal_info_t *h = (struct hal_info_t *)hinfo; + struct btc_t *btc = (struct btc_t *)h->btc; + + return btc->bt_req_len; +} + +/***********************/ +/* Called by BTC submodule */ +/***********************/ +void hal_btc_send_event(struct btc_t *btc, u8 *buf, u32 len, u16 ev_id) +{ +#ifdef CONFIG_PHL_CMD_BTC + rtw_phl_btc_send_cmd(btc->phl, buf, len, ev_id); +#endif +} + +void hal_btc_notify_ps_tdma(struct btc_t *btc, bool tdma_start) +{ +#ifdef CONFIG_POWER_SAVE + enum rtw_hal_status hstatus; + + hstatus = rtw_hal_ps_pwr_req(btc->phl, HAL_BTC_PWR_REQ, (tdma_start ? true : false)); + if (hstatus != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("[BTC], %s, TDMA (%d) request pwr fail, status: %d \n", + __func__, tdma_start, hstatus); + } +#endif +} + +bool rtw_hal_btc_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + if(incmd->in_type == RTW_ARG_TYPE_BUF) + halbtc_cmd(hal_info->btc, incmd->in.buf, output, out_len); + else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){ + halbtc_cmd_parser(hal_info->btc, incmd->in.vector, + incmd->in_cnt_len, output, out_len); + } + + return true; +} + + +#endif + +enum rtw_hal_status +rtw_hal_btc_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_btc_process_c2h(void *hal, struct rtw_c2h_info *c2h) +{ + struct hal_info_t *h = (struct hal_info_t *)hal; + struct btc_t *btc = (struct btc_t *)h->btc; + struct rtw_hal_com_t *hal_com = h->hal_com; + struct btc_fw_msg *fmsg = &hal_com->btc_msg; + void *d = halcom_to_drvpriv(hal_com); + u8 cls = c2h->c2h_class; + u8 func = c2h->c2h_func; + u16 len = c2h->content_len; + u8 *buf = c2h->content; + + if (len && len < RTW_PHL_BTC_FWINFO_BUF) { + if (cls == BTC_CLASS_FEV && func == BTC_FEV_BT_INFO) + _copy_btmsg(hal_com, &fmsg->btinfo, len, buf); + else if (cls == BTC_CLASS_FEV && func == BTC_FEV_BT_SCBD) + _copy_btmsg(hal_com, &fmsg->scbd, len, buf); + else + _fw_evnt_enq(hal_com, cls, func, len, buf); + + _os_spinlock(d, &fmsg->lock, _bh, NULL); + if (fmsg->fev_cnt == 0) { + if (rtw_phl_btc_send_cmd(btc->phl, NULL, 0, + BTC_HMSG_FW_EV)) + fmsg->fev_cnt++; + } + _os_spinunlock(d, &fmsg->lock, _bh, NULL); + } else { + PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): Invalid c2h packet len : %d\n", + __func__, len); + } + + return 0; +} + diff --git a/phl/hal_g6/hal_api_btc.h b/phl/hal_g6/hal_api_btc.h new file mode 100644 index 0000000..b371951 --- /dev/null +++ b/phl/hal_g6/hal_api_btc.h @@ -0,0 +1,40 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_BTC_H_ +#define _HAL_API_BTC_H_ + +#ifdef CONFIG_BTCOEX +enum rtw_hal_status +rtw_hal_btc_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); + +void rtw_hal_btc_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +#else +#define rtw_hal_btc_init(_phl_com_, _hal_info_) RTW_HAL_STATUS_SUCCESS +#define rtw_hal_btc_deinit(_phl_com_, _hal_info_) +#endif + +void rtw_hal_btc_switch_band_ntfy(void *hinfo, enum phl_phy_idx phy_idx, + enum band_type band); +void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state); + +u32 rtw_hal_btc_process_c2h(void *hal, struct rtw_c2h_info *c2h); +void rtw_hal_btc_init_coex_cfg_ntfy(void *hinfo); +bool rtw_hal_btc_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len); +u32 rtw_hal_btc_req_bt_slot_t(void *hinfo); + +#endif /*_HAL_API_BTC_H_*/ diff --git a/phl/hal_g6/hal_api_drv.h b/phl/hal_g6/hal_api_drv.h new file mode 100644 index 0000000..864209c --- /dev/null +++ b/phl/hal_g6/hal_api_drv.h @@ -0,0 +1,384 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_DRV_H_ +#define _HAL_API_DRV_H_ + +u32 rtw_hal_mac_coex_init(struct rtw_hal_com_t *hal_com, u8 pta_mode, u8 direction); +u32 rtw_hal_mac_coex_reg_read(struct rtw_hal_com_t *hal_com, u32 offset, u32 *value); +u32 rtw_hal_mac_coex_reg_write(struct rtw_hal_com_t *hal_com, u32 offset, u32 value); +u32 rtw_hal_mac_set_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value); +u32 rtw_hal_mac_get_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value); +u32 rtw_hal_mac_set_grant(struct rtw_hal_com_t *hal_com, u8 *value); +u32 rtw_hal_mac_get_grant(struct rtw_hal_com_t *hal_com, u8 *value); +u32 rtw_hal_mac_set_polluted(struct rtw_hal_com_t *hal_com, u8 band, u8 tx_val, u8 rx_val); +u32 rtw_hal_mac_set_tx_time(struct rtw_hal_com_t *hal_com, u8 is_btc, + u8 is_resume, u8 macid, u32 tx_time); +u32 rtw_hal_mac_get_tx_time(struct rtw_hal_com_t *hal_com, u8 macid, u32 *tx_time); +u32 rtw_hal_mac_set_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 is_btc, + u8 is_resume, u8 macid, u8 tx_retry); +u32 rtw_hal_mac_get_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 macid, + u8 *tx_retry); +u32 rtw_hal_mac_get_bt_polt_cnt(struct rtw_hal_com_t *hal_com, u8 band, + u16 *cnt); +u32 rtw_hal_mac_set_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 val); +u32 rtw_hal_mac_get_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 *val); + +u32 rtw_hal_mac_send_h2c(struct rtw_hal_com_t *hal_com, + struct rtw_g6_h2c_hdr *hdr, u32 *pvalue); + +u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask); + +bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com, + enum rf_path path, u32 addr, u32 mask, u32 data); + +u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask); + +bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask, + u32 data); + +u32 rtw_hal_mac_write_msk_pwr_reg( + struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 mask, u32 val); + +u32 rtw_hal_mac_set_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 val); + +u32 rtw_hal_mac_get_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_log_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val, + bool is_limited); + +enum rtw_hal_status +rtw_hal_mac_read_log_efuse_map(struct rtw_hal_com_t *hal_com, u8 *map, + bool is_limited); + +enum rtw_hal_status +rtw_hal_mac_write_log_efuse_map(struct rtw_hal_com_t *hal_com, + u8 *map, + u32 map_size, + u8 *mask, + u32 mask_size, + u8 *map_version, + u8 *mask_version, + u8 version_length, + u8 part, + bool is_limited); + +enum rtw_hal_status +rtw_hal_mac_read_hidden_rpt(struct rtw_hal_com_t *hal_com); + +enum rtw_hal_status +rtw_hal_mac_check_efuse_autoload(struct rtw_hal_com_t *hal_com, u8 *autoload); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_avl(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_mask_size(struct rtw_hal_com_t *hal_com, u32 *val, + bool is_limited); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid); + +enum rtw_hal_status +rtw_hal_mac_read_phy_efuse(struct rtw_hal_com_t *hal_com, + u32 addr, u32 size, u8 *value); + +enum rtw_hal_status +rtw_hal_mac_read_bt_phy_efuse(struct rtw_hal_com_t *hal_com, + u32 addr, u32 size, u8 *value); + +enum rtw_hal_status +rtw_hal_mac_get_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 *value); + +enum rtw_hal_status +rtw_hal_mac_set_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 value); + +enum rtw_hal_status +rtw_hal_mac_get_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 *val); + +enum rtw_hal_status +rtw_hal_mac_set_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 val); + +enum rtw_hal_status +rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid); + +enum rtw_hal_status +rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid); + +void +rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, + u8 pwrbyrate_type, u8 pwrlmt_type); + +void +rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status rtw_hal_rf_read_pwr_table( + struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate, + u8 bandwidth, u8 channel, u8 offset, u8 dcm, + u8 beamforming, s16 *get_item); + +enum rtw_hal_status rtw_hal_rf_wl_tx_power_control( + struct rtw_hal_com_t *hal_com, + u32 tx_power_val); + +enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com, + bool dbcc_en); + +void rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, enum rf_path path); + +enum rtw_hal_status +rtw_hal_btc_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid); + +enum rtw_hal_status rtw_hal_efuse_get_info(struct rtw_hal_com_t *hal_com, + enum rtw_efuse_info info_type, void *value, u8 size); +enum rtw_hal_status rtw_hal_notify_switch_band(void *hinfo, + enum band_type band, enum phl_phy_idx phy_idx); + +enum rtw_hal_status rtw_hal_reset(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, u8 band_idx, bool reset); + +#ifndef CONFIG_BTCOEX +#define rtw_hal_btc_wl_rfk_ntfy(hal_com, phy_idx, rfk_type, rfk_process) 0 +#else +u8 rtw_hal_btc_wl_rfk_ntfy(struct rtw_hal_com_t *hal_com, u8 phy_idx, u8 rfk_type, u8 rfk_process); + +enum rtw_hal_status rtw_hal_btc_cfg_tx_1ss(struct rtw_hal_com_t *hal_com, + struct rtw_phl_com_t *phl_com, u8 rid, bool enable); +#endif +void rtw_hal_btc_power_on_ntfy(void *hinfo); +void rtw_hal_btc_power_off_ntfy(void *hinfo); + +enum rtw_hal_status +rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com, + u8 band_idx, bool tx_pause, enum tx_pause_rson rson); + +enum rtw_hal_status +rtw_hal_mac_set_macid_pause(struct rtw_hal_com_t *hal_com, + u16 macid, bool pause); + +enum rtw_hal_status +rtw_hal_mac_set_macid_grp_pause(struct rtw_hal_com_t *hal_com, + u32 *macid_arr, u8 macid_arr_sz, bool pause); + +u32 +rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig); + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel, + u32 *addr_start, u32 *addr_end); + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en, + u8 restart_en, u8 timeout_en, u8 timeout_val, + u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val); + +enum rtw_hal_status +rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state, + u16 *la_finish_addr, bool *la_round_up, + bool *la_loss_data); + +void +rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr, + u8 *buf, u32 len, u32 dbg_path); + +enum rtw_hal_status +rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value); + + +/* HALBB APIs for HW TX */ + +enum rtw_hal_status +rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com, + struct mp_plcp_param_t *plcp_tx_struct, + struct mp_usr_plcp_gen_in *plcp_usr_info, + enum phl_phy_idx plcp_phy_idx, + u8 *plcp_sts); + +enum rtw_hal_status +rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, u8 is_cck, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable, + u8 is_cck, u16 tx_cnt, u8 tx_duty, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm, + enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg); + +enum rtw_hal_status +rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en); + +enum rtw_hal_status +rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path); + +enum rtw_hal_status +rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path); + +/* mode: 0 = tmac, 1 = pmac */ +enum rtw_hal_status +rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, + u8 mode); +/* HALBB APIs for HW TX END*/ +/*@--------------------------[Prptotype]-------------------------------------*/ +/** + * rtw_hal_bb_get_txsc input arguments: + * @hal_com: hal com info + * @pri_ch: Spec-defined primary channel index + * @central_ch: Spec-defined central channel index + * @cbw: Channel BW + * @dbw: Data BW + */ +u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch, + u8 central_ch, enum channel_width cbw, enum channel_width dbw); + +void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx); + +bool rtw_hal_query_regulation(void *phl, struct rtw_regulation_info *info); + +enum rtw_hal_status +rtw_hal_mac_set_tpu_mode(struct rtw_hal_com_t *hal_com, + enum rtw_tpu_op_mode op_mode_new, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_avl(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_mask_size(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_get_log_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val); + +enum rtw_hal_status +rtw_hal_mac_read_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, u8 *map); + +enum rtw_hal_status +rtw_hal_mac_write_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, + u8 *map, + u32 map_size, + u8 *mask, + u32 mask_size); + + +enum rtw_hal_status +rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx); + +enum rtw_hal_status +rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx); + +enum rtw_hal_status +rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com); + +enum rtw_hal_status +rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo); +enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com, + bool cca_en, enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_mac_write_pwr_ofst_mode(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_ofst_bw(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_ref_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_en(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_set_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band, bool en_val); +bool +rtw_hal_mac_get_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band); +enum rtw_hal_status +rtw_hal_mac_read_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u32 size, u8 *val); + +enum rtw_hal_status +rtw_hal_mac_write_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u8 val); + +enum rtw_hal_status +rtw_hal_mac_ax_init_bf_role(struct rtw_hal_com_t *hal_com, u8 bf_role, u8 band); + +enum rtw_hal_status +rtw_hal_mac_ax_deinit_bfee(struct rtw_hal_com_t *hal_com, u8 band); + +void rtw_hal_bb_gpio_setting_all(struct rtw_hal_com_t *hal_com, u8 rfe_idx); + +void rtw_hal_bb_gpio_setting(struct rtw_hal_com_t *hal_com, u8 gpio_idx, u8 path, + bool inv, u8 src); + +enum rtw_hal_status +rtw_hal_mac_set_gpio_func(struct rtw_hal_com_t *hal_com, u8 func, s8 gpio_cfg); + +enum rtw_phl_status +rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx); +#ifdef CONFIG_FW_IO_OFLD_SUPPORT +enum rtw_hal_status rtw_hal_mac_add_cmd_ofld(struct rtw_hal_com_t *hal_com, struct rtw_mac_cmd *cmd); +#endif + +void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, + enum phl_phy_idx phy_indx); + +void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx); + +#endif /*_HAL_API_DRV_H_*/ diff --git a/phl/hal_g6/hal_api_efuse.c b/phl/hal_g6/hal_api_efuse.c new file mode 100644 index 0000000..a743ffe --- /dev/null +++ b/phl/hal_g6/hal_api_efuse.c @@ -0,0 +1,593 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_EFUSE_C_ +#include "hal_headers.h" +#include "efuse/hal_efuse_export.h" + +/*WIFI Efuse*/ +enum rtw_hal_status +rtw_hal_efuse_shadow_load(struct hal_info_t *hal_info, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_shadow_load(hal_info->efuse, is_limit); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_shadow_update(struct hal_info_t *hal_info, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + + status = rtw_efuse_shadow_update(hal_info->efuse, is_limit); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_shadow_read(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 *value, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_shadow_read(hal_info->efuse, byte_count, offset, value, + is_limit); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_shadow_write(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 value, bool is_limit) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_shadow_write(hal_info->efuse, byte_count, offset, value, + is_limit); + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_shadow2buf(struct hal_info_t *hal_info, u8 *pbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + status = rtw_efuse_shadow2buf(hal_info->efuse, pbuf, buflen); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_file_map_load( + struct hal_info_t *hal_info, char *file_path, u8 is_limit) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_file_map_load(hal_info->efuse, file_path ,is_limit); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_efuse_file_mask_load( + struct hal_info_t *hal_info, char *file_path, u8 is_limit) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_file_mask_load(hal_info->efuse, file_path, is_limit); + + return hal_status; +} + +/* usage = used percentage(1 Byte) + used bytes(2 Bytes) */ +enum rtw_hal_status rtw_hal_efuse_get_usage(struct hal_info_t *hal_info, + u32 *usage) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_usage(hal_info->efuse, usage); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_get_logical_size(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_logical_size(hal_info->efuse, size, true); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_get_size(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_size(hal_info->efuse, size); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_get_avl(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_avl(hal_info->efuse, size); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_get_shadowmap_from(struct hal_info_t *hal_info, + u8 *val) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_shadowmap_from(hal_info->efuse, val); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_get_offset_mask(struct hal_info_t *hal_info, + u16 offset, u8 *mask) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_offset_mask(hal_info->efuse, offset, mask); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_get_info(struct rtw_hal_com_t *hal_com, + enum rtw_efuse_info info_type, + void *value, + u8 size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = hal_com->hal_priv; + + status = rtw_efuse_get_info(hal_info->efuse, info_type, value, size); + + return status; +} + +/* API export to PHL : rtw_hal_get_efuse_info */ +enum rtw_hal_status +rtw_hal_get_efuse_info(void *hal, + enum rtw_efuse_info info_type, + void *value, + u8 size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + status = rtw_efuse_get_info(hal_info->efuse, info_type, value, size); + + return status; +} + +void rtw_hal_efuse_process(struct hal_info_t *hal_info, char *ic_name) +{ + rtw_efuse_process(hal_info->efuse, ic_name); +} + +enum rtw_hal_status rtw_hal_efuse_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + status = rtw_efuse_init(phl_com, hal_com, &(hal_info->efuse)); + + return status; +} + +void rtw_hal_efuse_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + rtw_efuse_deinit(hal_com, hal_info->efuse); +} + + +enum rtw_hal_status +rtw_hal_efuse_bt_shadow_load(struct hal_info_t *hal_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_shadow_load(hal_info->efuse); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_bt_shadow_update(struct hal_info_t *hal_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + + status = rtw_efuse_bt_shadow_update(hal_info->efuse); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_bt_shadow_read(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 *value) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_shadow_read(hal_info->efuse, byte_count, offset, value); + + return status; +} + +enum rtw_hal_status +rtw_hal_efuse_bt_shadow_write(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 value) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_shadow_write(hal_info->efuse, byte_count, offset, value); + return status; +} + + +enum rtw_hal_status +rtw_hal_efuse_bt_shadow2buf(struct hal_info_t *hal_info, u8 *pbuf, u16 buflen) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + status = rtw_efuse_bt_shadow2buf(hal_info->efuse, pbuf, buflen); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_file_map_load( + struct hal_info_t *hal_info, char *file_path) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_bt_file_map_load(hal_info->efuse, file_path); + + return hal_status; +} + + +enum rtw_hal_status rtw_hal_efuse_bt_file_mask_load( + struct hal_info_t *hal_info, char *file_path) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_bt_file_mask_load(hal_info->efuse, file_path); + + return hal_status; +} + +/* usage = used percentage(1 Byte) + used bytes(2 Bytes) */ +enum rtw_hal_status rtw_hal_efuse_bt_get_usage(struct hal_info_t *hal_info, + u32 *usage) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_get_usage(hal_info->efuse, usage); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_get_logical_size(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_get_logical_size(hal_info->efuse, size); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_get_size(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_get_size(hal_info->efuse, size); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_get_avl(struct hal_info_t *hal_info, + u32 *size) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_get_avl(hal_info->efuse, size); + + return status; +} + + +enum rtw_hal_status rtw_hal_efuse_bt_get_offset_mask(struct hal_info_t *hal_info, + u16 offset, u8 *mask) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_bt_get_offset_mask(hal_info->efuse, offset, mask); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_read_hidden( + struct hal_info_t *hal_info, u32 addr, u32 size, u8 *val) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_bt_read_hidden(hal_info->efuse, addr, size, val); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_efuse_bt_write_hidden( + struct hal_info_t *hal_info, u32 addr, u8 val) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_efuse_bt_write_hidden(hal_info->efuse, addr, val); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_efuse_read_phy_efuse( + struct hal_info_t *hal_info, u32 addr, u32 size, u8 *data, u8 type) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_read_phy_wifi(hal_info->efuse, addr, size, data, type); + + return status; +} + +enum rtw_hal_status rtw_hal_efuse_renew( + struct hal_info_t *hal_info, u8 type) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_efuse_renew(hal_info->efuse, type); + + return status; +} + +void hal_efuse_dump_wifi_map( + struct hal_info_t *hal_info, + u32 *used_len, + char *output, + u32 *out_len + ) +{ + void *d = hal_info->hal_com->drv_priv; + u32 _used_len = *used_len; + u32 _out_len = *out_len; + u32 map_len = 0; + u32 i = 0, j = 0; + u8 *buf = NULL; + + rtw_efuse_get_logical_size(hal_info->efuse, &map_len, true); + + if(map_len == 0){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "map length is 0!\n"); + goto exit; + } + + buf = _os_mem_alloc(d, map_len); + + if(buf == NULL){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "Allocate buffer fail!\n"); + goto exit; + } + rtw_efuse_shadow2buf(hal_info->efuse, buf, (u16)map_len); + + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "EFUSE Wifi shadow map from %s\n\n", + rtw_efuse_get_shadowmap_from_to_str(hal_info->efuse)); + + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "%14s%-6s%-6s%-6s%-6s%-6s%-6s%-6s%-6s\n", + " ", "00", "02", "04", "06", "08", "0A", "0C", "0E"); + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "%14s%s\n", + " ", "================================================\n"); + for(i = 0; i < map_len; i+=16){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "0x%08X%4s", i, ""); + for(j = 0; j<16;j++){ + if((i+j) >= map_len) + break; + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "%02X ", buf[i+j]); + } + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "\n"); + } + if(buf) + _os_mem_free(d, buf, map_len); +exit: + *used_len = _used_len; + *out_len = _out_len; +} + +void hal_efuse_dump_wifi_logic_map( + struct hal_info_t *hal_info, + u32 *used_len, + char *output, + u32 *out_len + ) +{ + void *d = hal_info->hal_com->drv_priv; + u32 _used_len = *used_len; + u32 _out_len = *out_len; + u32 map_len = 0; + u32 i = 0, j = 0; + u8 *data = NULL; + + rtw_efuse_get_logical_size(hal_info->efuse, &map_len, true); + + if(map_len == 0){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "map length is 0!\n"); + goto exit; + } + + data = _os_mem_alloc(d, map_len); + + if(data == NULL){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "Allocate buffer fail!\n"); + goto exit; + } + + rtw_efuse_logicmap_buf_load(hal_info->efuse, data, false); + + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "EFUSE Wifi map from HW\n"); + + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "%14s%-6s%-6s%-6s%-6s%-6s%-6s%-6s%-6s\n", + " ", "00", "02", "04", "06", "08", "0A", "0C", "0E"); + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len, + "%14s%s\n", + " ", "================================================\n"); + for(i = 0; i < map_len; i+=16){ + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "0x%08X%4s", i, ""); + for(j = 0; j<16;j++){ + if((i+j) >= map_len) + break; + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "%02X ", data[i+j]); + } + PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, + _out_len - _used_len, "\n"); + } + if(data) + _os_mem_free(d, data, map_len); +exit: + *used_len = _used_len; + *out_len = _out_len; +} + +void hal_efuse_cmd_parser( + struct hal_info_t *hal_info, + char input[][MAX_ARGV], + u32 input_num, + char *output, + u32 out_len + ) +{ + u32 hal_cmd_ary_size = sizeof(hal_efuse_cmd_i) / sizeof(struct hal_cmd_info); + u32 i = 0; + u8 id = 0; + u32 used = 0; + + PHL_DBG_OUTBUF(out_len, used, output + used, out_len - used, "\n"); + + if (hal_cmd_ary_size == 0) + return; + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < hal_cmd_ary_size; i++) { + if (_os_strcmp(hal_efuse_cmd_i[i].name, input[0]) == 0) { + id = hal_efuse_cmd_i[i].id; + PHL_INFO("enter EFUSE cmd %s\n", hal_efuse_cmd_i[i].name); + break; + } + } + if (i == hal_cmd_ary_size) { + PHL_DBG_OUTBUF(out_len, used, output + used, + out_len - used, + "EFUSE command not found!\n"); + return; + } + } + + switch (id) { + case HAL_EFUSE_HELP: + PHL_DBG_OUTBUF(out_len, used, output + used, + out_len - used, + "EFUSE cmd =>\n"); + for (i = 0; i < hal_cmd_ary_size - 1; i++) + PHL_DBG_OUTBUF(out_len, used, output + used, + out_len - used," %s\n", hal_efuse_cmd_i[i].name); + break; + case HAL_EFUSE_WIFI_DUMP_MAP: + hal_efuse_dump_wifi_map(hal_info, &used, output, &out_len); + break; + case HAL_EFUSE_WIFI_LOGIC_DUMP_MAP: + hal_efuse_dump_wifi_logic_map(hal_info, &used, output, &out_len); + break; + default: + PHL_DBG_OUTBUF(out_len, used, output + used, + out_len - used,"Do not support this command\n"); + break; + } +} + +s32 hal_efuse_cmd( + struct hal_info_t *hal_info, + char *input, + char *output, + u32 out_len + ) +{ + char *token; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; + + do { + token = _os_strsep(&input, ", "); + if (token) { + if (_os_strlen((u8*)token) <= MAX_ARGV) + _os_strcpy(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < MAX_ARGC); + + hal_efuse_cmd_parser(hal_info, argv, argc, output, out_len); + + return 0; +} + +bool rtw_hal_efuse_proc_cmd( + struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, + u32 out_len + ) +{ + if(incmd->in_type == RTW_ARG_TYPE_BUF) + hal_efuse_cmd(hal_info, incmd->in.buf, output, out_len); + else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){ + hal_efuse_cmd_parser(hal_info, incmd->in.vector, + incmd->in_cnt_len, output, out_len); + } + + return true; +} \ No newline at end of file diff --git a/phl/hal_g6/hal_api_efuse.h b/phl/hal_g6/hal_api_efuse.h new file mode 100644 index 0000000..b921b47 --- /dev/null +++ b/phl/hal_g6/hal_api_efuse.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_EFUSE_H_ +#define _HAL_API_EFUSE_H_ + +/* efuse exported API */ +/* WIFI EFUSE */ +enum rtw_hal_status rtw_hal_efuse_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +void rtw_hal_efuse_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +void rtw_hal_efuse_process(struct hal_info_t *hal_info, char *ic_name); +enum rtw_hal_status +rtw_hal_efuse_shadow_load(struct hal_info_t *hal_info, bool is_limit); +enum rtw_hal_status +rtw_hal_efuse_shadow_read(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 *value, bool is_limit); +enum rtw_hal_status +rtw_hal_efuse_shadow_write(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 value, bool is_limit); +enum rtw_hal_status +rtw_hal_efuse_shadow_update(struct hal_info_t *hal_info, bool is_limit); +enum rtw_hal_status rtw_hal_efuse_shadow2buf(struct hal_info_t *hal_info, + u8 *pbuf, u16 buflen); +enum rtw_hal_status rtw_hal_efuse_file_map_load(struct hal_info_t *hal_info, + char *file_path, u8 is_limit); +enum rtw_hal_status rtw_hal_efuse_file_mask_load(struct hal_info_t *hal_info, + char *file_path, u8 is_limit); +enum rtw_hal_status rtw_hal_efuse_get_usage(struct hal_info_t *hal_info, + u32 *usage); +enum rtw_hal_status rtw_hal_efuse_get_logical_size(struct hal_info_t *hal_info, + u32 *size); +enum rtw_hal_status rtw_hal_efuse_get_size(struct hal_info_t *hal_info, + u32 *size); +enum rtw_hal_status rtw_hal_efuse_get_avl(struct hal_info_t *hal_info, + u32 *size); +enum rtw_hal_status rtw_hal_efuse_get_shadowmap_from(struct hal_info_t *hal_info, + u8 *val); +enum rtw_hal_status rtw_hal_efuse_get_offset_mask(struct hal_info_t *hal_info, + u16 offset, u8 *mask); + + +/* BT EFUSE */ +enum rtw_hal_status rtw_hal_efuse_bt_shadow_load(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_efuse_bt_shadow_read(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 *value); + +enum rtw_hal_status rtw_hal_efuse_bt_shadow_write(struct hal_info_t *hal_info, u8 byte_count, + u16 offset, u32 value); + +enum rtw_hal_status rtw_hal_efuse_bt_shadow_update(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_efuse_bt_shadow2buf(struct hal_info_t *hal_info, + u8 *pbuf, u16 buflen); + +enum rtw_hal_status rtw_hal_efuse_bt_file_map_load( + struct hal_info_t *hal_info, char *file_path); + +enum rtw_hal_status rtw_hal_efuse_bt_file_mask_load( + struct hal_info_t *hal_info, char *file_path); + +enum rtw_hal_status rtw_hal_efuse_bt_get_usage(struct hal_info_t *hal_info, + u32 *usage); + +enum rtw_hal_status rtw_hal_efuse_bt_get_logical_size(struct hal_info_t *hal_info, + u32 *size); + +enum rtw_hal_status rtw_hal_efuse_bt_get_size(struct hal_info_t *hal_info, + u32 *size); + +enum rtw_hal_status rtw_hal_efuse_bt_get_avl(struct hal_info_t *hal_info, + u32 *size); + +enum rtw_hal_status rtw_hal_efuse_bt_get_offset_mask(struct hal_info_t *hal_info, + u16 offset, u8 *mask); + +enum rtw_hal_status rtw_hal_efuse_bt_read_hidden( + struct hal_info_t *hal_info, u32 addr, u32 size, u8 *val); + +enum rtw_hal_status rtw_hal_efuse_bt_write_hidden( + struct hal_info_t *hal_info, u32 addr, u8 val); + +enum rtw_hal_status rtw_hal_efuse_read_phy_efuse( + struct hal_info_t *hal_info, u32 addr, u32 size, u8 *data, u8 type); + +enum rtw_hal_status rtw_hal_efuse_renew( + struct hal_info_t *hal_info, u8 type); + +bool rtw_hal_efuse_proc_cmd( + struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, + u32 out_len + ); + +#endif /* _HAL_API_EFUSE_H_ */ diff --git a/phl/hal_g6/hal_api_mac.c b/phl/hal_g6/hal_api_mac.c new file mode 100644 index 0000000..bc01ca0 --- /dev/null +++ b/phl/hal_g6/hal_api_mac.c @@ -0,0 +1,8933 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_MAC_C_ +#include "mac/mac_ax.h" +#include "hal_headers.h" +#ifdef RTW_PHL_BCN +#include "mac/mac_ax/fwcmd.h" +#endif + +#define RTL8852A_FPGA_VERIFICATION 1 + +u16 hal_mac_get_macid_num(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + + return mac->hw_info->macid_num; +} +void hal_mac_get_hwinfo(struct hal_info_t *hal, struct hal_spec_t *hal_spec) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_hw_info *mac_info = mac->hw_info; + struct mac_ax_ops *ops = mac->ops; + /*struct mac_ax_hw_info* (*get_hw_info)(struct mac_ax_adapter *adapter);*/ + + mac_info = ops->get_hw_info(mac); + + hal_spec->macid_num = mac_info->macid_num; + + hal->hal_com->cv = mac_info->cv; + PHL_INFO("[MAC-INFO]- CV : %d\n", mac_info->cv); + PHL_INFO("[MAC-INFO]- tx_ch_num: %d\n", mac_info->tx_ch_num); + + PHL_INFO("[MAC-INFO]- tx_data_ch_num: %d\n", mac_info->tx_data_ch_num); + PHL_INFO("[MAC-INFO]- wd_body_len: %d\n", mac_info->wd_body_len); + PHL_INFO("[MAC-INFO]- wd_info_len: %d\n", mac_info->wd_info_len); + + PHL_INFO("[MAC-INFO]- pwr_seq_ver: %d\n", mac_info->pwr_seq_ver); + PHL_INFO("[MAC-INFO]- fifo_size: %d\n", mac_info->fifo_size); + PHL_INFO("[MAC-INFO]- macid_num: %d\n", mac_info->macid_num); + PHL_INFO("[MAC-INFO]- wl_efuse_size: %d\n", mac_info->wl_efuse_size); + + PHL_INFO("[MAC-INFO]- efuse_size: %d\n", mac_info->efuse_size); + PHL_INFO("[MAC-INFO]- log_efuse_size: %d\n", mac_info->log_efuse_size); + + PHL_INFO("[MAC-INFO]- bt_efuse_size: %d\n", mac_info->bt_efuse_size); + PHL_INFO("[MAC-INFO]- sec_ctrl_efuse_size: %d\n", mac_info->sec_ctrl_efuse_size); + PHL_INFO("[MAC-INFO]- sec_data_efuse_size: %d\n", mac_info->sec_data_efuse_size); + +} + +enum rtw_hal_status rtw_hal_mac_watchdog(struct hal_info_t *hal_info) +{ +#ifdef CONFIG_HAL_MAC_WATCHDOG + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + + ret = mac->ops->watchdog(mac); + + return (ret == MACSUCCESS) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +#else + return RTW_HAL_STATUS_SUCCESS; +#endif +} + +#ifdef CONFIG_PCI_HCI +enum rtw_hal_status rtw_hal_mac_set_pcicfg(struct hal_info_t *hal_info, + struct mac_ax_pcie_cfgspc_param *pci_cfgspc) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + + ret = mac->ops->set_hw_value(mac, MAC_AX_HW_PCIE_CFGSPC_SET, pci_cfgspc); + return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status rtw_hal_mac_ltr_sw_trigger(struct hal_info_t *hal_info, enum rtw_pcie_ltr_state state) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + enum mac_ax_pcie_ltr_sw_ctrl ctrl; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + u32 ret = 0; + + switch (state) { + + case RTW_PCIE_LTR_SW_ACT: + ctrl = MAC_AX_PCIE_LTR_SW_ACT; + break; + case RTW_PCIE_LTR_SW_IDLE: + ctrl = MAC_AX_PCIE_LTR_SW_IDLE; + break; + default: + PHL_INFO("%s: state = %u, fail to trigger \n", __func__, state); + return RTW_HAL_STATUS_FAILURE; + + } + + ret = mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_LTR_SW_TRIGGER, &ctrl); + + if (ret == 0) + hstats = RTW_HAL_STATUS_SUCCESS; + else + hstats = RTW_HAL_STATUS_FAILURE; + + return hstats; +} + +enum rtw_hal_status rtw_hal_mac_ltr_set_pcie(struct hal_info_t *hal_info, + enum rtw_pcie_bus_func_cap_t hw_ctrl, + u8 idle_ctrl, u32 idle_val, u8 act_ctrl, u32 act_val) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_pcie_ltr_param param; + u32 ret = 0; + enum mac_ax_pcie_func_ctrl ctrl; + + switch (hw_ctrl) { + + case RTW_PCIE_BUS_FUNC_ENABLE: + ctrl = MAC_AX_PCIE_ENABLE; + break; + case RTW_PCIE_BUS_FUNC_DISABLE: + ctrl = MAC_AX_PCIE_DISABLE; + break; + case RTW_PCIE_BUS_FUNC_DEFAULT: + ctrl = MAC_AX_PCIE_DEFAULT; + break; + default: + ctrl = MAC_AX_PCIE_IGNORE; + } + + param.write = 1; + param.read = 0; + param.ltr_ctrl = MAC_AX_PCIE_IGNORE; + param.ltr_hw_ctrl = ctrl; + param.ltr_spc_ctrl = MAC_AX_PCIE_LTR_SPC_IGNORE; + param.ltr_idle_timer_ctrl = MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE; + param.ltr_rx0_th_ctrl.ctrl = MAC_AX_PCIE_IGNORE; + param.ltr_rx0_th_ctrl.val = 0; + param.ltr_rx1_th_ctrl.ctrl = MAC_AX_PCIE_IGNORE; + param.ltr_rx1_th_ctrl.val = 0; + + /* when ctrl is not equal to 0, setting ignore to make hw control the value */ + if (idle_ctrl) { + param.ltr_idle_lat_ctrl.ctrl = MAC_AX_PCIE_ENABLE; + param.ltr_idle_lat_ctrl.val = idle_val; + } else { + param.ltr_idle_lat_ctrl.ctrl = MAC_AX_PCIE_IGNORE; + param.ltr_idle_lat_ctrl.val = 0; + } + + if (act_ctrl) { + param.ltr_act_lat_ctrl.ctrl = MAC_AX_PCIE_ENABLE; + param.ltr_act_lat_ctrl.val = act_val; + } else { + param.ltr_act_lat_ctrl.ctrl = MAC_AX_PCIE_IGNORE; + param.ltr_act_lat_ctrl.val = 0; + } + + PHL_INFO("%s: ltr_hw_ctrl %u \n", __func__, param.ltr_hw_ctrl); + PHL_INFO("%s: ltr_idle_lat_ctrl, ctrl %u, val %u\n", __func__, + param.ltr_idle_lat_ctrl.ctrl, param.ltr_idle_lat_ctrl.val); + PHL_INFO("%s: ltr_act_lat_ctrl, ctrl %u, val %u\n", __func__, + param.ltr_act_lat_ctrl.ctrl, param.ltr_act_lat_ctrl.val); + + + ret = mac->ops->intf_ops->ltr_set_pcie(mac, ¶m); + return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status hal_mac_set_l2_leave(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + u8 set = true; + + ret = mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_L2_LEAVE, &set); + return (ret == MACSUCCESS) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status rtw_hal_mac_poll_txdma_idle(struct hal_info_t *hal, + struct mac_ax_txdma_ch_map *ch_map) +{ + + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 ret = 0; + + ret = hal_mac_ops->intf_ops->poll_txdma_ch_idle(mac, ch_map); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); + +} + +enum rtw_hal_status rtw_hal_mac_poll_rxdma_idle(struct hal_info_t *hal, + struct mac_ax_rxdma_ch_map *ch_map) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 ret = 0; + + ret = hal_mac_ops->intf_ops->poll_rxdma_ch_idle(mac, ch_map); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} +enum rtw_hal_status rtw_hal_mac_cfg_txdma(struct hal_info_t *hal, + struct mac_ax_txdma_ch_map *ch_map) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 ret = 0; + + ret = hal_mac_ops->intf_ops->ctrl_txdma_ch(mac, ch_map); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); + +} + + +enum rtw_hal_status rtw_hal_mac_clr_bdidx(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 ret = 0; + + ret = hal_mac_ops->intf_ops->clr_idx_all(mac); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status rtw_hal_mac_rst_bdram(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 ret = 0; + u8 val; + + ret = hal_mac_ops->set_hw_value(mac, MAC_AX_HW_PCIE_RST_BDRAM, &val); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status rtw_hal_mac_cfg_dma_io(struct hal_info_t *hal, u8 en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + enum mac_ax_func_sw ctrl; + u32 ret = 0; + + if (en) + ctrl = MAC_AX_FUNC_EN; + else + ctrl = MAC_AX_FUNC_DIS; + + ret = hal_mac_ops->intf_ops->ctrl_dma_io(mac, ctrl); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + + +#endif + +#ifdef CONFIG_USB_HCI +u8 hal_mac_get_bulkout_id(struct hal_info_t *hal, u8 dma_ch, u8 mode) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + + return mac->ops->intf_ops->get_bulkout_id(mac, dma_ch, mode); +} + +u32 hal_mac_usb_tx_agg_cfg(struct hal_info_t *hal, u8* wd_buf, u8 agg_num) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_usb_tx_agg_cfg agg; + + agg.pkt = wd_buf; + agg.agg_num = agg_num; + + return mac->ops->intf_ops->usb_tx_agg_cfg(mac, &agg); +} + +u32 hal_mac_usb_rx_agg_cfg(struct hal_info_t *hal, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_rx_agg_cfg cfg; + + cfg.mode = agg_mode; + cfg.thold.drv_define = drv_define; + cfg.thold.timeout = timeout; + cfg.thold.size = size; + cfg.thold.pkt_num = pkt_num; + + return mac->ops->intf_ops->usb_rx_agg_cfg(mac, &cfg); +} + +enum rtw_hal_status hal_mac_force_usb_switch(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + + if(mac->ops->intf_ops->u2u3_switch(mac) == MACSUCCESS) { + PHL_INFO("%s,success!\n", __func__); + return RTW_HAL_STATUS_SUCCESS; + } + else { + PHL_INFO("%s,fail!\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } +} + +u32 hal_mac_get_cur_usb_mode(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + return mac->ops->intf_ops->get_usb_mode(mac); +} +u32 hal_mac_get_usb_support_ability(struct hal_info_t *hal) + +{ + + struct mac_ax_adapter *mac = hal_to_mac(hal); + + return mac->ops->intf_ops->get_usb_support_ability(mac); + +} +u8 hal_mac_usb_get_max_bulkout_wd_num(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + + return mac->usb_info.max_bulkout_wd_num; +} +#endif + +#ifdef CONFIG_SDIO_HCI +u8 hal_mac_sdio_read8(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return mac_intf_ops->reg_read8(mac, addr); +} + +u16 hal_mac_sdio_read16(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return mac_intf_ops->reg_read16(mac, addr); +} + +u32 hal_mac_sdio_read32(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return mac_intf_ops->reg_read32(mac, addr); +} + +int hal_mac_sdio_write8(struct rtw_hal_com_t *hal, u32 addr, u8 value) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + mac_intf_ops->reg_write8(mac, addr, value); + return 0; +} + +int hal_mac_sdio_write16(struct rtw_hal_com_t *hal, u32 addr, u16 value) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + mac_intf_ops->reg_write16(mac, addr, value); + return 0; +} + +int hal_mac_sdio_write32(struct rtw_hal_com_t *hal, u32 addr, u32 value) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + mac_intf_ops->reg_write32(mac, addr, value); + return 0; +} + +static void _read_register(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *buf) +{ + u32 i, n; + u16 val16; + u32 val32; + + i = addr & 0x3; + /* Handle address not start from 4 bytes alignment case */ + if (i) { + val32 = cpu_to_le32(hal_read32(hal, addr & ~0x3)); + n = 4 - i; + _os_mem_cpy(hal->drv_priv, buf, ((u8 *)&val32) + i, n); + i = n; + cnt -= n; + } + + while (cnt) { + if (cnt >= 4) + n = 4; + else if (cnt >= 2) + n = 2; + else + n = 1; + cnt -= n; + + switch (n) { + case 1: + buf[i] = hal_read8(hal, addr+i); + i++; + break; + case 2: + val16 = cpu_to_le16(hal_read16(hal, addr+i)); + _os_mem_cpy(hal->drv_priv, &buf[i], &val16, 2); + i += 2; + break; + case 4: + val32 = cpu_to_le32(hal_read32(hal, addr+i)); + _os_mem_cpy(hal->drv_priv, &buf[i], &val32, 4); + i += 4; + break; + } + } +} + +static int _sdio_read_local(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *buf) +{ + /*struct hal_info_t *hal_info = hal->hal_priv;*/ + /*struct mac_ax_adapter *mac = hal_to_mac(hal_info);*/ + /*struct mac_ax_ops *mac_api = mac->ops;*/ + /*struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;*/ + + if (buf == NULL) + return -1; + /*GEORGIA_TODO_FIXIT_ASKFORMAC*/ + /*mac_intf_ops->reg_readrn(mac, addr, cnt, buf);*/ + return 0; +} + +void hal_mac_sdio_read_mem(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem) +{ + + if (pmem == NULL) { + PHL_ERR("pmem is NULL\n"); + return; + } + + if (addr & 0xFFFF0000) { + int err = 0; + + err = _sdio_read_local(hal, addr, cnt, pmem); + if (!err) + return; + } + _read_register(hal, addr, cnt, pmem); +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 hal_mac_sdio_iread8(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return mac_intf_ops->reg_read8(mac, addr); +} + +u16 hal_mac_sdio_iread16(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return mac_intf_ops->reg_read16(mac, addr); +} + +u32 hal_mac_sdio_iread32(struct rtw_hal_com_t *hal, u32 addr) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *mac_api = mac->ops; + struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops; + + return 0; +} +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + + +#ifndef CONFIG_NEW_HALMAC_INTERFACE +#ifdef CONFIG_SDIO_HCI +static u8 hal_mac_sdio_cmd52_r8(void *h, u32 addr) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_cmd52_r8(hal->drv_priv, addr); +} +static u8 hal_mac_sdio_cmd53_r8(void *h, u32 addr) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_cmd53_r8(hal->drv_priv, addr); +} +static u16 hal_mac_sdio_cmd53_r16(void *h, u32 addr) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_cmd53_r16(hal->drv_priv, addr); +} +static u32 hal_mac_sdio_cmd53_r32(void *h, u32 addr) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_cmd53_r32(hal->drv_priv, addr); +} +static u8 hal_mac_sdio_cmd53_rn(void *h, u32 addr, u32 size, u8 *val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_cmd53_rn(hal->drv_priv, addr, size,val); +} +static void hal_mac_sdio_cmd52_w8(void *h, u32 addr, u8 val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_sdio_cmd52_w8(hal->drv_priv, addr, val); +} +static void hal_mac_sdio_cmd53_w8(void *h, u32 addr, u8 val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_sdio_cmd53_w8(hal->drv_priv, addr, val); +} +static void hal_mac_sdio_cmd53_w16(void *h, u32 addr, u16 val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_sdio_cmd53_w16(hal->drv_priv, addr, val); +} +static void hal_mac_sdio_cmd53_w32(void *h, u32 addr, u32 val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_sdio_cmd53_w32(hal->drv_priv, addr, val); +} +static u8 hal_mac_sdio_cmd53_wn(void *h, u32 addr, u32 size, u8 *val) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_sdio_cmd53_wn(hal->drv_priv, addr, size, val); + return true; +} +static u8 hal_mac_sdio_cmd52_cia_r8(void *h, u32 addr) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_sdio_read_cia_r8(hal->drv_priv, addr); +} +#endif /*CONFIG_SDIO_HCI*/ + +static u8 hal_mac_reg_r8(void *h, u32 addr) +{ + return hal_read8((struct rtw_hal_com_t *)h, addr); +} +static u16 hal_mac_reg_r16(void *h, u32 addr) +{ + return hal_read16((struct rtw_hal_com_t *)h, addr); +} +static u32 hal_mac_reg_r32(void *h, u32 addr) +{ + return hal_read32((struct rtw_hal_com_t *)h, addr); +} +static void hal_mac_reg_w8(void *h, u32 addr, u8 val) +{ + hal_write8((struct rtw_hal_com_t *)h, addr, val); +} +static void hal_mac_reg_w16(void *h, u32 addr, u16 val) +{ + hal_write16((struct rtw_hal_com_t *)h, addr, val); +} +static void hal_mac_reg_w32(void *h, u32 addr, u32 val) +{ + hal_write32((struct rtw_hal_com_t *)h, addr, val); +} + + +#ifdef DBG_HAL_MAC_MEM_MOINTOR +static void hal_mac_mem_free(void *h, void *buf, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + /*PHL_INFO("MAC free mem - :%d\n", size);*/ + _os_atomic_sub(hal->drv_priv, &(hal->hal_mac_mem), size); + _os_mem_free(hal->drv_priv, buf, size); +} +static void* hal_mac_mem_alloc(void *h, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + /*PHL_INFO("MAC Alloc mem - :%d\n", size);*/ + _os_atomic_add_return(hal->drv_priv, &(hal->hal_mac_mem), size); + + return _os_mem_alloc(hal->drv_priv, size); +} +#else +static void hal_mac_mem_free(void *h, void *buf, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mem_free(hal->drv_priv, buf, size); +} +static void* hal_mac_mem_alloc(void *h, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_mem_alloc(hal->drv_priv, size); +} +#endif /*DBG_HAL_MAC_MEM_MOINTOR*/ +static void hal_mac_mem_cpy(void *h, void *dest, void *src, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mem_cpy(hal->drv_priv, dest, src, size); +} +static void hal_mac_mem_set(void *h, void *addr, u8 val, u32 size) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mem_set(hal->drv_priv, addr, val, size); + +} +static s32 hal_mac_mem_cmp(void *h, void *ptr1, void *ptr2, u32 num) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + return _os_mem_cmp(hal->drv_priv, ptr1, ptr2, num); +} +static void hal_mac_udelay(void *h, u32 us) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_delay_us(hal->drv_priv, us); +} +static void hal_mac_mdelay(void *h, u32 ms) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_delay_ms(hal->drv_priv, ms); +} + +static void hal_mac_mutex_init(void *h, mac_ax_mutex *mutex) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mutex_init(hal->drv_priv, mutex); +} +static void hal_mac_mutex_deinit(void *h, mac_ax_mutex *mutex) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mutex_deinit(hal->drv_priv, mutex); +} +static void hal_mac_mutex_lock(void *h, mac_ax_mutex *mutex) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mutex_lock(hal->drv_priv, mutex); +} +static void hal_mac_mutex_unlock(void *h, mac_ax_mutex *mutex) +{ + struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + + _os_mutex_unlock(hal->drv_priv, mutex); +} + +static void hal_mac_event_notify(void *h, + enum mac_ax_feature mac_ft, + enum mac_ax_status stat, u8 *buf, u32 size) +{ + //struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h; + +} + +struct rtw_h2c_pkt *hal_query_h2c_pkt(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, + enum h2c_buf_class type) +{ + struct rtw_h2c_pkt *h2c_pkt = NULL; + enum rtw_h2c_pkt_type pkt_type = H2CB_TYPE_MAX; + + switch (type) { + case H2CB_CLASS_CMD: + pkt_type = H2CB_TYPE_CMD; + break; + case H2CB_CLASS_DATA: + pkt_type = H2CB_TYPE_DATA; + break; + case H2CB_CLASS_LONG_DATA: + pkt_type = H2CB_TYPE_LONG_DATA; + break; + case H2CB_CLASS_LAST: + pkt_type = H2CB_TYPE_MAX; + break; + default: + PHL_ERR("%s: Unknown type(%d)\n", __func__, type); + break; + } + + h2c_pkt = rtw_phl_query_h2c_pkt(phl_com, pkt_type); + + if (!h2c_pkt) + PHL_ERR("hal_query_h2c_pkt fail (type %d).\n", type); + + return h2c_pkt; +} + +enum rtw_hal_status hal_pltfm_tx(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, + struct rtw_h2c_pkt *pkt) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + if (rtw_phl_pltfm_tx(phl_com, pkt) == RTW_PHL_STATUS_SUCCESS) + hstatus = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("hal_pltfm_tx fail.\n"); + + return hstatus; +} + +void hal_ser_l2_notify(void *phl, void *hal) +{ + struct rtw_phl_com_t *phl_com = (struct rtw_phl_com_t *)phl; + + rtw_phl_ser_l2_notify(phl_com); +} + +static s32 hal_mac_sprintf(void *drv_adapter, char *buf, size_t size, const char *fmt, ...) +{ +#if defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS) + s32 ret; + va_list args; + + va_start(args, fmt); + ret = _os_vsnprintf(buf, size, fmt, args); + if (ret >= 0) + ret = _os_strlen((u8 *)buf); + + /* PHL_PRINT("[HAL_MMAC]%s", buf); */ + va_end(args); + return ret; +#else + return 0; +#endif +} + +static s32 hal_mac_strcmp(void *drv_adapter, const char *s1, const char *s2) +{ + return _os_strcmp(s1, s2); +} + +static char* hal_mac_strsep(void *drv_adapter, char **s, const char *ct) +{ + return _os_strsep(s, ct); +} + +static u32 hal_mac_strlen(void *drv_adapter, char *buf) +{ + return _os_strlen((u8 *)buf); +} + +static char* hal_mac_strcpy(void *drv_adapter, char *dest, const char *src) +{ + return _os_strcpy(dest, src); +} + +static char* hal_mac_strpbrk(void *drv_adapter, const char *cs, const char *ct) +{ + return _os_strpbrk(cs, ct); +} + +static u32 hal_mac_strtoul(void *drv_adapter, const char *buf, u32 base) +{ +#if 1 + u32 ret = 0, val = 0; + + if (base == 10) + ret = _os_sscanf(buf, "%d", &val); + else if (base == 16) + ret = _os_sscanf(buf, "%x", &val); + else + ret = _os_sscanf(buf, "%d", &val); + + return val; +#else + //stdlib strtoul +#endif + +} + +static u8 +hal_mac_ld_fw_symbol(void *phl_com, void *hal_com, const char *name, + u8 **buf, u32 *buf_size) +{ + return rtw_hal_ld_fw_symbol((struct rtw_phl_com_t *)phl_com, + (struct rtw_hal_com_t *)hal_com, name, buf, buf_size); +} + +#define RTW_HALMAC_FAIL 0 +#define RTW_HALMAC_SUCCESS 1 +#define MSG_PREFIX "[MAC]" + +void hal_mac_msg_print(void *p, u8 dbg_level, s8 *fmt, ...) +{ +#if defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS) +#define MSG_LEN 100 + va_list args; + char str[MSG_LEN] = {0}; + int err; + u8 ret = RTW_HALMAC_SUCCESS; + + str[0] = '\n'; + va_start(args, fmt); + err = _os_vsnprintf(str, MSG_LEN, fmt, args); + va_end(args); + + /* An output error is encountered */ + if (err < 0) + return; + /* Output may be truncated due to size limit */ + if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n')) + ret = RTW_HALMAC_FAIL; + + PHL_TRACE(COMP_PHL_MAC, dbg_level, MSG_PREFIX " %s", str); +#endif +} + +struct mac_ax_pltfm_cb rtw_plt_cb = {0}; +void rtw_plt_cb_init(void) +{ + /* R/W register */ +#ifdef CONFIG_SDIO_HCI + rtw_plt_cb.sdio_cmd52_r8 = hal_mac_sdio_cmd52_r8; + rtw_plt_cb.sdio_cmd53_r8 = hal_mac_sdio_cmd53_r8; + rtw_plt_cb.sdio_cmd53_r16 = hal_mac_sdio_cmd53_r16; + rtw_plt_cb.sdio_cmd53_r32 = hal_mac_sdio_cmd53_r32; + rtw_plt_cb.sdio_cmd53_rn = hal_mac_sdio_cmd53_rn; + rtw_plt_cb.sdio_cmd52_w8 = hal_mac_sdio_cmd52_w8; + rtw_plt_cb.sdio_cmd53_w8 = hal_mac_sdio_cmd53_w8; + rtw_plt_cb.sdio_cmd53_w16 = hal_mac_sdio_cmd53_w16; + rtw_plt_cb.sdio_cmd53_w32 = hal_mac_sdio_cmd53_w32; + rtw_plt_cb.sdio_cmd53_wn = hal_mac_sdio_cmd53_wn; + rtw_plt_cb.sdio_cmd52_cia_r8 = hal_mac_sdio_cmd52_cia_r8; +#endif /* CONFIG_SDIO_HCI */ + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + rtw_plt_cb.reg_r8 = hal_mac_reg_r8; + rtw_plt_cb.reg_r16 = hal_mac_reg_r16; + rtw_plt_cb.reg_r32 = hal_mac_reg_r32; + rtw_plt_cb.reg_w8 = hal_mac_reg_w8; + rtw_plt_cb.reg_w16 = hal_mac_reg_w16; + rtw_plt_cb.reg_w32 = hal_mac_reg_w32; +#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */ + + /* Memory allocate */ + rtw_plt_cb.rtl_free = hal_mac_mem_free; + rtw_plt_cb.rtl_malloc = hal_mac_mem_alloc; + rtw_plt_cb.rtl_memcpy = hal_mac_mem_cpy; + rtw_plt_cb.rtl_memset = hal_mac_mem_set; + rtw_plt_cb.rtl_memcmp = hal_mac_mem_cmp; + /* Sleep */ + rtw_plt_cb.rtl_delay_us = hal_mac_udelay; + rtw_plt_cb.rtl_delay_ms = hal_mac_mdelay; + + /* Process Synchronization */ + rtw_plt_cb.rtl_mutex_init = hal_mac_mutex_init; + rtw_plt_cb.rtl_mutex_deinit = hal_mac_mutex_deinit; + rtw_plt_cb.rtl_mutex_lock = hal_mac_mutex_lock; + rtw_plt_cb.rtl_mutex_unlock = hal_mac_mutex_unlock; + + rtw_plt_cb.msg_print = hal_mac_msg_print; + rtw_plt_cb.event_notify = hal_mac_event_notify; + rtw_plt_cb.ser_l2_notify = hal_ser_l2_notify; + rtw_plt_cb.ld_fw_symbol = hal_mac_ld_fw_symbol; + /*.tx = ; */ +#if MAC_AX_PHL_H2C + rtw_plt_cb.tx = hal_pltfm_tx; + rtw_plt_cb.rtl_query_h2c = hal_query_h2c_pkt; +#endif +#if MAC_AX_FEATURE_DBGCMD + rtw_plt_cb.rtl_sprintf = hal_mac_sprintf; + rtw_plt_cb.rtl_strcmp = hal_mac_strcmp; + rtw_plt_cb.rtl_strsep = hal_mac_strsep; + rtw_plt_cb.rtl_strlen = hal_mac_strlen; + rtw_plt_cb.rtl_strcpy = hal_mac_strcpy; + rtw_plt_cb.rtl_strpbrk = hal_mac_strpbrk; + rtw_plt_cb.rtl_strtoul = hal_mac_strtoul; +#endif +} + + +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +/* halmac wrapper API for hal and proto type is at hal_api_mac.h */ +#define MAC_STATUS_MAX MACSDIOSEQERR+1 /* Wrong interface */ +const char *const ma_status[] = { + "MAC Success", + "Callback of platform is null", + "Endian of platform error", + "Invalid base address", + "Leave suspend error", + "Pointer is null", + "Chip ID is undefined", + "Can not get MAC adapter", + "Unexpected structure alignment", + "Buffer space is not enough", + "Buffer size error", + "Invalid item", + "Polling timeout", + "Power switch fail", + "Work queue is busy", + "Failed compare result", + "Wrong interface", + "Incorrect FW bin file", + "Wrong FIFO configuration", + "Same MACID", + "MACID full", + "There is no FW", + "Process is busy", + "state machine error", + "switch efuse bank fail", + "read efuse fail", + "write efuse fail", + "efuse size error", + "eeprom parsing fail", + "compare efuse fail", + "secure on, no host indirect access", + "invalid tx dma channel", + "address cam update error", + "Power state error", + "SDIO Tx mix mode", + "SDIO Tx sequence error", +}; + +#define mac_sstr(status) (((status) >= MAC_STATUS_MAX) ? "unknown" : ma_status[(status)]) + +/** + * rtw_hal_mac_get_version() - Get HALMAC version + * @ver_str: string buffer for storing version string + * @len: string buffer length + * + * HALMAC version format is "V[major].[prototype].[sub ver].[sub index]", + * ex: V0.16.1.0 + * + */ +void rtw_hal_mac_get_version(char *ver_str, u16 len) +{ + _os_snprintf(ver_str, len, "V%u.%u.%u.%u", + MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER, + MAC_AX_SUB_VER, MAC_AX_SUB_INDEX); +} + +/** + * rtw_hal_mac_get_fw_ver() - Get Firmware version + * @hal_info: struct hal_info_t * + * @ver_str: string buffer for storing version string + * @len: string buffer length + * + * Firmware version format is "V[major].[ver].[sub ver].[sub index]", + * ex: V0.5.0 + * + */ +void rtw_hal_mac_get_fw_ver(struct hal_info_t *hal_info, char *ver_str, u16 len) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + _os_snprintf(ver_str, len, "V%u.%u.%u.%u", + mac->fw_info.major_ver,mac->fw_info.minor_ver, + mac->fw_info.sub_ver, mac->fw_info.sub_idx); +} + +#define _IS_FW_READY(hal_info) \ + (hal_to_mac(hal_info)->sm.fwdl == MAC_AX_FWDL_INIT_RDY) + +void hal_mac_print_fw_version(struct hal_info_t *hal_info) +{ + char ver[20] = {0}; + rtw_hal_mac_get_fw_ver(hal_info, ver, 20); + PHL_PRINT("%s: FW version %s, %sReady\n", __func__, ver, + _IS_FW_READY(hal_info) ? "" : "Not "); +} + +u32 rtw_hal_mac_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct mac_ax_adapter *mac = NULL; + struct mac_ax_ops *mac_ops; + u32 status; + +#ifdef DBG_HAL_MAC_MEM_MOINTOR + _os_atomic_set(hal_com->drv_priv, &(hal_com->hal_mac_mem), 0); +#endif + hal_info->mac = NULL; +#ifdef CONFIG_NEW_HALMAC_INTERFACE + status = new_mac_ax_ops_init(phl_com, hal_com, &mac, &mac_ops); +#else + { + enum mac_ax_intf intf = MAC_AX_INTF_INVALID; + if (phl_com->hci_type == RTW_HCI_PCIE) + intf = MAC_AX_INTF_PCIE; + else if (phl_com->hci_type == RTW_HCI_USB) + intf = MAC_AX_INTF_USB; + else if ((phl_com->hci_type == RTW_HCI_SDIO) || + (phl_com->hci_type == RTW_HCI_GSPI)) + intf = MAC_AX_INTF_SDIO; + + rtw_plt_cb_init(); + status = mac_ax_ops_init(hal_com, + &rtw_plt_cb, intf, &mac, &mac_ops); + #if MAC_AX_PHL_H2C + if (status == MACSUCCESS && mac != NULL) + mac_ax_phl_init(phl_com, mac); + #endif + } +#endif + + if (status != MACSUCCESS) { + PHL_ERR("%s: halmac_init_adapter fail!(status=%d-%s)\n", + __func__, status, mac_sstr(status)); + hal_status = RTW_HAL_STATUS_MAC_INIT_FAILURE; + goto error_mac_init; + } + + if (!mac) { + PHL_ERR("halmac alloc failed\n"); + hal_status = RTW_HAL_STATUS_MAC_INIT_FAILURE; + /*_os_warn_on(1);*/ + goto error_mac_init; + } + hal_com->cv = mac->hw_info->cv; + hal_info->mac = mac; + + return hal_status; + +error_mac_init: + if (mac) { + mac_ax_ops_exit(mac); + hal_info->mac = NULL; + } + return hal_status; +} + +u32 rtw_hal_mac_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + #ifdef DBG_HAL_MAC_MEM_MOINTOR + struct rtw_hal_com_t *hal = hal_info->hal_com; + #endif + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + if (mac) { + if(mac_ax_ops_exit(mac) == MACSUCCESS) { + hal_status = RTW_HAL_STATUS_FAILURE; + + hal_info->mac = NULL; + } else { + PHL_ERR("%s failed\n", __func__); + } + } + #ifdef DBG_HAL_MAC_MEM_MOINTOR + PHL_INFO("[PHL-MEM] %s HALMAC memory :%d\n", __func__, + _os_atomic_read(hal_to_drvpriv(hal_info), &(hal->hal_mac_mem))); + #endif + + return hal_status; +} + +u8 _hal_mac_ax_dmach2datach(u8 dmach) +{ + u8 data_ch = MAC_AX_DATA_CH0; + + + if ((MAC_AX_DMA_B0HI == dmach) || + (MAC_AX_DMA_B1HI == dmach)) + data_ch = MAC_AX_DATA_HIQ; + else if ((MAC_AX_DMA_B0MG == dmach) || + (MAC_AX_DMA_B1MG == dmach)) + data_ch = 0; + else { + data_ch = dmach; + } + return data_ch; +} + +#ifdef CONFIG_SDIO_HCI +void rtw_hal_mac_sdio_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct rtw_ic_info *ic_info) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_sdio_info info; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + info.sdio_4byte = (ic_info->sdio_info.io_align_sz == 4) + ? MAC_AX_SDIO_4BYTE_MODE_RW : MAC_AX_SDIO_4BYTE_MODE_DISABLE; + + if (ic_info->sdio_info.sd3_bus_mode) + info.spec_ver = MAC_AX_SDIO_SPEC_VER_3_00; + else + info.spec_ver = MAC_AX_SDIO_SPEC_VER_2_00; + + info.block_size = ic_info->sdio_info.block_sz; + + if (ic_info->sdio_info.tx_512_by_byte_mode) + info.opn_mode = MAC_AX_SDIO_OPN_MODE_BYTE; + else + info.opn_mode = MAC_AX_SDIO_OPN_MODE_BLOCK; + + /* + * MAC_AX_HW_SDIO_INFO always return MACSUCCESS, + * so don't check return value here. + */ + mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_INFO, &info); +} + +/** + * rtw_hal_mac_sdio_tx_cfg - SDIO TX related setting + * @hal: pointer of struct rtw_hal_com_t + * + * Configure setting for SDIO TX. + * All tx related setting which need to be config after mac init(power on) + * should be included here. + * + * Config tx mode to DUMMY_AUTO to release (32K-4) bytes TX size limitation, + * but this mode only work on SDIO host supporting block mode. + * + * No return value for this function. + */ +void rtw_hal_mac_sdio_tx_cfg(struct rtw_hal_com_t *hal) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_sdio_tx_mode mode = MAC_AX_SDIO_TX_MODE_DUMMY_AUTO; + u32 err; + + + err = mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_TX_MODE, &mode); + if (err != MACSUCCESS) + PHL_ERR("%s: set TX mode(%u) FAIL!(%u)\n", __func__, mode, err); +} + +/** + * rtw_hal_mac_sdio_rx_agg_cfg - SDIO RX aggregation setting + * @hal: pointer of struct rtw_hal_com_t + * @enable: enable function or not + * @drv_define: use driver's parameters or not + * @timeout: timeout threshold, unit 1us + * @size: size threshold, unit 1KB + * @pkt_num: packet number threshold + * + * Configure setting for SDIO RX aggregation. + * + * No return value for this function. + */ +void rtw_hal_mac_sdio_rx_agg_cfg(struct rtw_hal_com_t *hal, bool enable, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_rx_agg_cfg cfg = {MAC_AX_RX_AGG_MODE_NONE}; + + + if (enable) { + cfg.mode = MAC_AX_RX_AGG_MODE_DMA; + cfg.thold.drv_define = drv_define; + cfg.thold.timeout = timeout; + cfg.thold.size = size; + cfg.thold.pkt_num = pkt_num; + } + + mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_RX_AGG, &cfg); +} + +/* AX TX DESC */ +/* DWORD 0 ; Offset 00h */ +#define GET_TX_AX_DESC_CHANNEL_DMA(_wd) LE_BITS_TO_4BYTE(_wd, 16, 4) +#define GET_TX_AX_DESC_WP_OFFSET(_wd) LE_BITS_TO_4BYTE(_wd, 24, 8) + +/* DWORD 2 ; Offset 08h */ +#define GET_TX_AX_DESC_PKT_LEN(_wd) LE_BITS_TO_2BYTE(_wd+8, 0, 14) + +/** + * rtw_hal_mac_sdio_check_tx_allow - Check hardware resource enough to xmit + * @hal: pointer of struct rtw_hal_com_t + * @dma_ch: dma channel to xmit, should be the same as field "CHANNEL_DMA "in WD + * @buf: data buffer to xmit + * @len: data buffer length + * @agg_count: how many packets aggregated in this buffer + * @pkt_len: array to store each packet's lenght in this buffer, + * pkt_len should be the same as field "PKT_LEN" in WD + * @wp_offset: array to store each packet's wp_offset in this buffer + * wp_offset should be the same as field "WP_OFFSET" in WD + * @txaddr: return SDIO TX address for this tx buffer, and only valid when + * function's return value is true. + * @txlen: return SDIO TX length for this tx buffer, and only valid when + * function's return value is true. txlen would >= len and align + * to particular size by IC. + * + * Check if hardware resource is enough to send this tx buffer and return + * SDIO TX address. + * + * Return true if hardware resource is enough, otherwise false. + */ +bool rtw_hal_mac_sdio_check_tx_allow(struct rtw_hal_com_t *hal, u8 dma_ch, + u8 *buf, u32 len, u8 agg_count, + u16 *pkt_len, u8 *wp_offset, u32 *txaddr, + u32 *txlen) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_sdio_tx_info info = {0}; + int i; + u32 err; + u16 pkt_len_tmp; + u8 wp_offset_tmp; + u8 wd_ch; + + + /* For H2C, pkt_len & wp_offset may be invalid */ + if (!pkt_len && (agg_count == 1)) { + pkt_len_tmp = GET_TX_AX_DESC_PKT_LEN(buf); + pkt_len = &pkt_len_tmp; + } + if (!wp_offset && (agg_count == 1)) { + wp_offset_tmp = (u8)GET_TX_AX_DESC_WP_OFFSET(buf); + wp_offset = &wp_offset_tmp; + } + + /* check tx wd */ + wd_ch = (u8)GET_TX_AX_DESC_CHANNEL_DMA(buf); + if (wd_ch != dma_ch) { + PHL_ERR("%s: tx channel abnormal, %u(wd) != %u(input)\n", + __func__, wd_ch, dma_ch); + debug_dump_data(buf, len&0xFFFF0000?0xFFFF:(u16)len, "wd:"); + } + + info.total_size = len; + info.dma_txagg_num = agg_count; + info.ch_dma = dma_ch; + /* halmac request pkt_size should be little endian */ + for (i = 0; i < agg_count; i++) + pkt_len[i] = cpu_to_le16(pkt_len[i]); + info.pkt_size = (u8*)pkt_len; + info.wp_offset = wp_offset; + info.chk_cnt = 5; + + err = mac->ops->intf_ops->tx_allow_sdio(mac, &info); + if (err != MACSUCCESS) { + PHL_DBG("%s: tx allow fail! (%d)\n", __func__, err); + goto err_exit; + } + + err = mac->ops->intf_ops->tx_cmd_addr_sdio(mac, &info, txaddr); + if (err != MACSUCCESS) { + PHL_ERR("%s: get tx addr fail! (%d)\n", __func__, err); + goto err_exit; + } + + /* + * TX I/O size should align to 8 bytes on SDIO byte count mode, + * or hardware would go wrong. + * + * TODO: alignment size would be get from HALMAC return. + */ + *txlen = _ALIGN(len, 8); + + return true; + +err_exit: + /* Revert pkt_len to CPU endian */ + for (i = 0; i < agg_count; i++) + pkt_len[i] = le16_to_cpu(pkt_len[i]); + + return false; +} + +static enum rtw_rx_type _pkt_type_mac2phl(enum mac_ax_pkt_t mac_type) +{ + enum rtw_rx_type t = RTW_RX_TYPE_MAX; + + + switch (mac_type) { + case MAC_AX_PKT_DATA: + t = RTW_RX_TYPE_WIFI; + break; + case MAC_AX_PKT_MGNT: + case MAC_AX_PKT_CTRL: + case MAC_AX_PKT_8023: + case MAC_AX_PKT_H2C: + case MAC_AX_PKT_FWDL: + /* TODO: unknown */ + PHL_WARN("%s: unhandled RX type(%d)\n", __func__, mac_type); + break; + case MAC_AX_PKT_C2H: + t = RTW_RX_TYPE_C2H; + break; + case MAC_AX_PKT_PPDU: + t = RTW_RX_TYPE_PPDU_STATUS; + break; + case MAC_AX_PKT_CH_INFO: + t = RTW_RX_TYPE_CHANNEL_INFO; + break; + case MAC_AX_PKT_DFS: + t = RTW_RX_TYPE_DFS_RPT; + break; + default: + PHL_WARN("%s: unknon RX type(%d)\n", __func__, mac_type); + break; + } + + return t; +} + +static void hal_mac_parse_rxpkt_info(struct mac_ax_rxpkt_info *info, + struct rtw_r_meta_data *meta) +{ + meta->pktlen = (u16)info->pktsize; /* DW0 [0:13] */ + meta->shift = info->shift; /* DW0 [14:15] */ + meta->rpkt_type = _pkt_type_mac2phl(info->type); /* DW0 [24:27] */ + meta->drv_info_size = info->drvsize; /* DW0 [28:30] */ + meta->long_rxd = (info->rxdlen == RXD_LONG_LEN) ? 1 : 0; /* DW0 [31:31] */ + + if (info->type == MAC_AX_PKT_DATA) { +#if 0 + meta->dma_ch; + meta->hal_port; + meta->ta[6]; /* Transmitter Address */ +#endif +#if 0 + meta->wl_hd_iv_len; /* DW0 [16:21] */ + meta->bb_sel; /* DW0 [22:22] */ + meta->mac_info_vld; /* DW0 [23:23] */ +#endif +#if 0 + meta->long_rxd; /* DW0 [31:31] */ + + meta->ppdu_type; /* DW1 [0:3] */ + meta->ppdu_cnt; /* DW1 [4:6] */ + meta->sr_en; /* DW1 [7:7] */ + meta->user_id; /* DW1 [8:15] */ + meta->rx_rate; /* DW1 [16:24] */ + meta->rx_gi_ltf; /* DW1 [25:27] */ + meta->non_srg_ppdu; /* DW1 [28:28] */ + meta->inter_ppdu; /* DW1 [29:29] */ + meta->bw; /* DW1 [30:31] */ + + meta->freerun_cnt; /* DW2 [0:31] */ + + meta->a1_match; /* DW3 [0:0] */ + meta->sw_dec; /* DW3 [1:1] */ + meta->hw_dec; /* DW3 [2:2] */ + meta->ampdu; /* DW3 [3:3] */ + meta->ampdu_end_pkt; /* DW3 [4:4] */ + meta->amsdu; /* DW3 [5:5] */ + meta->amsdu_cut; /* DW3 [6:6] */ + meta->last_msdu; /* DW3 [7:7] */ + meta->bypass; /* DW3 [8:8] */ +#endif + meta->crc32 = info->u.data.crc_err; /* DW3 [9:9] */ + meta->icverr = info->u.data.icv_err; /* DW3 [10:10] */ +#if 0 + meta->magic_wake; /* DW3 [11:11] */ + meta->unicast_wake; /* DW3 [12:12] */ + meta->pattern_wake; /* DW3 [13:13] */ + meta->get_ch_info; /* DW3 [14:15] */ + meta->pattern_idx; /* DW3 [16:20] */ + meta->target_idc; /* DW3 [21:23] */ + meta->chksum_ofld_en; /* DW3 [24:24] */ + meta->with_llc; /* DW3 [25:25] */ + meta->rx_statistics; /* DW3 [26:26] */ + + meta->frame_type; /* DW4 [0:1] */ + meta->mc; /* DW4 [2:2] */ + meta->bc; /* DW4 [3:3] */ + meta->more_data; /* DW4 [4:4] */ + meta->more_frag; /* DW4 [5:5] */ + meta->pwr_bit; /* DW4 [6:6] */ + meta->qos; /* DW4 [7:7] */ + meta->tid; /* DW4 [8:11] */ + meta->eosp; /* DW4 [12:12] */ + meta->htc; /* DW4 [13:13] */ + meta->q_null; /* DW4 [14:14] */ + meta->seq; /* DW4 [16:27] */ + meta->frag_num; /* DW4 [28:31] */ + + meta->sec_cam_idx; /* DW5 [0:7] */ + meta->addr_cam; /* DW5 [8:15] */ + meta->macid; /* DW5 [16:23] */ + meta->rx_pl_id; /* DW5 [24:27] */ + meta->addr_cam_vld; /* DW5 [28:28] */ + meta->addr_fwd_en; /* DW5 [29:29] */ + meta->rx_pl_match; /* DW5 [30:30] */ + + meta->mac_addr[6]; /* DW6 [0:31] DW7 [0:15] */ + meta->smart_ant; /* DW7 [16:16] */ + meta->sec_type; /* DW7 [17:20] */ +#endif + } else if (info->type == MAC_AX_PKT_PPDU) { + meta->mac_info_vld = info->u.ppdu.mac_info; /* DW0 [23:23] */ + } +} + +/* AX RX DESC */ +/* DWORD 0 ; Offset 00h */ +#define GET_RX_AX_DESC_PKT_LEN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) +#define GET_RX_AX_DESC_SHIFT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 2) +#define GET_RX_AX_DESC_HDR_IV_L(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 6) +#define GET_RX_AX_DESC_BB_SEL(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 22, 1) +#define GET_RX_AX_DESC_MAC_INFO_VLD(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_AX_DESC_RPKT_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 4) +#define GET_RX_AX_DESC_DRV_INFO_SIZE(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 3) +#define GET_RX_AX_DESC_LONG_RXD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) + +/* DWORD 1 ; Offset 04h */ +#define GET_RX_AX_DESC_PPDU_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 4) +#define GET_RX_AX_DESC_PPDU_CNT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 4, 3) +#define GET_RX_AX_DESC_SR_EN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1) +#define GET_RX_AX_DESC_USER_ID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 8) +#define GET_RX_AX_DESC_RX_DATARATE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 9) +#define GET_RX_AX_DESC_RX_GI_LTF(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 3) +#define GET_RX_AX_DESC_NON_SRG_PPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 1) +#define GET_RX_AX_DESC_INTER_PPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 29, 1) +#define GET_RX_AX_DESC_BW(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 2) + +/* DWORD 2 ; Offset 08h */ +#define GET_RX_AX_DESC_FREERUN_CNT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 32) + +/* DWORD 3 ; Offset 0ch */ +#define GET_RX_AX_DESC_A1_MATCH(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 1) +#define GET_RX_AX_DESC_SW_DEC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 1, 1) +#define GET_RX_AX_DESC_HW_DEC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 2, 1) +#define GET_RX_AX_DESC_AMPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 3, 1) +#define GET_RX_AX_DESC_AMPDU_EDN_PKT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 4, 1) +#define GET_RX_AX_DESC_AMSDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 5, 1) +#define GET_RX_AX_DESC_AMSDU_CUT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 6, 1) +#define GET_RX_AX_DESC_LAST_MSDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 1) +#define GET_RX_AX_DESC_BYPASS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 8, 1) +#define GET_RX_AX_DESC_CRC32(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 9, 1) +#define GET_RX_AX_DESC_ICVERR(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) +#define GET_RX_AX_DESC_MAGIC_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) +#define GET_RX_AX_DESC_UNICAST_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 1) +#define GET_RX_AX_DESC_PATTERN_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 13, 1) + +#define GET_RX_AX_DESC_CH_INFO(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 14, 1) +#define GET_RX_AX_DESC_STATISTICS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 15, 1) +#define GET_RX_AX_DESC_PATTERN_IDX(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 5) +#define GET_RX_AX_DESC_TARGET_IDC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 21, 3) +#define GET_RX_AX_DESC_CHKSUM_OFFLOAD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 24, 1) +#define GET_RX_AX_DESC_WITH_LLC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 25, 1) + +/* DWORD 4 ; Offset 10h */ +#define GET_RX_AX_DESC_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 2) +#define GET_RX_AX_DESC_MC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 2, 1) +#define GET_RX_AX_DESC_BC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 3, 1) +#define GET_RX_AX_DESC_MD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 4, 1) +#define GET_RX_AX_DESC_MF(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 5, 1) +#define GET_RX_AX_DESC_PWR(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 6, 1) +#define GET_RX_AX_DESC_QOS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 7, 1) +#define GET_RX_AX_DESC_TID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 4) +#define GET_RX_AX_DESC_EOSP(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 12, 1) +#define GET_RX_AX_DESC_HTC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 13, 1) +#define GET_RX_AX_DESC_QNULL(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 14, 1) + +#define GET_RX_AX_DESC_SEQ(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 12) +#define GET_RX_AX_DESC_FRAG(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 28, 4) + +/* DWORD 5 ; Offset 14h */ +#define GET_RX_AX_DESC_CAM_IDX(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 8) +#define GET_RX_AX_DESC_ADDR_CAM(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 8, 8) +#define GET_RX_AX_DESC_MACID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 16, 8) +#define GET_RX_AX_DESC_PL_ID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 24, 4) +#define GET_RX_AX_DESC_CAM_VLD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 28, 1) +#define GET_RX_AX_DESC_FWD_EN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 29, 1) +#define GET_RX_AX_DESC_PL_MATCH(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 30, 1) + +#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX +static void hal_mac_parse_rxd_checksume(struct rtw_hal_com_t *hal, + struct rtw_r_meta_data *meta, u8 status) +{ + if ((status == MAC_AX_CHKSUM_OFD_IPV4_TCP_OK) || + (status == MAC_AX_CHKSUM_OFD_IPV6_TCP_OK) || + (status == MAC_AX_CHKSUM_OFD_IPV4_UDP_OK) || + (status == MAC_AX_CHKSUM_OFD_IPV6_UDP_OK)) + meta->chksum_status = 0; + else + meta->chksum_status = 1; +} +#endif + +static void hal_mac_parse_rxd(struct rtw_hal_com_t *hal, + u8 *rxd, struct rtw_r_meta_data *meta) +{ +#if 0 + meta->pktlen = GET_RX_AX_DESC_PKT_LEN(rxd); + meta->shift = GET_RX_AX_DESC_SHIFT(rxd); + meta->wl_hd_iv_len = GET_RX_AX_DESC_HDR_IV_L(rxd); + meta->bb_sel = GET_RX_AX_DESC_BB_SEL(rxd); + meta->mac_info_vld = GET_RX_AX_DESC_MAC_INFO_VLD(rxd); + meta->rpkt_type = GET_RX_AX_DESC_RPKT_TYPE(rxd); + meta->drv_info_size = GET_RX_AX_DESC_DRV_INFO_SIZE(rxd); + meta->long_rxd = GET_RX_AX_DESC_LONG_RXD(rxd); + + meta->ppdu_type = GET_RX_AX_DESC_PPDU_TYPE(rxd); + meta->ppdu_cnt = GET_RX_AX_DESC_PPDU_CNT(rxd); + meta->sr_en = GET_RX_AX_DESC_SR_EN(rxd); + meta->user_id = GET_RX_AX_DESC_USER_ID(rxd); + meta->rx_rate = GET_RX_AX_DESC_RX_DATARATE(rxd); + meta->rx_gi_ltf = GET_RX_AX_DESC_RX_GI_LTF(rxd); + meta->non_srg_ppdu = GET_RX_AX_DESC_NON_SRG_PPDU(rxd); + meta->inter_ppdu = GET_RX_AX_DESC_INTER_PPDU(rxd); + meta->bw = GET_RX_AX_DESC_BW(rxd); + + meta->freerun_cnt = GET_RX_AX_DESC_FREERUN_CNT(rxd); + + meta->a1_match = GET_RX_AX_DESC_A1_MATCH(rxd); +#endif + meta->sw_dec = GET_RX_AX_DESC_SW_DEC(rxd); + meta->hw_dec = GET_RX_AX_DESC_HW_DEC(rxd); +#if 0 + meta->ampdu = GET_RX_AX_DESC_AMPDU(rxd); + meta->ampdu_end_pkt = GET_RX_AX_DESC_AMPDU_EDN_PKT(rxd); + meta->amsdu = GET_RX_AX_DESC_AMSDU(rxd); +#endif + meta->amsdu_cut = GET_RX_AX_DESC_AMSDU_CUT(rxd); + meta->last_msdu = GET_RX_AX_DESC_LAST_MSDU(rxd); +#if 0 + meta->bypass = GET_RX_AX_DESC_BYPASS(rxd); + meta->crc32 = GET_RX_AX_DESC_CRC32(rxd); + meta->icverr = GET_RX_AX_DESC_ICVERR(rxd); + meta->magic_wake = GET_RX_AX_DESC_MAGIC_WAKE(rxd); + meta->unicast_wake = GET_RX_AX_DESC_UNICAST_WAKE(rxd); + meta->pattern_wake = GET_RX_AX_DESC_PATTERN_WAKE(rxd); + meta->get_ch_info = GET_RX_AX_DESC_CH_INFO(rxd); + meta->rx_statistics = GET_RX_AX_DESC_STATISTICS(rxd); + + meta->pattern_idx = GET_RX_AX_DESC_PATTERN_IDX(rxd); + meta->target_idc = GET_RX_AX_DESC_TARGET_IDC(rxd); + meta->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD(rxd); + meta->with_llc = GET_RX_AX_DESC_WITH_LLC(rxd); +#endif + meta->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD(rxd); + + if (meta->long_rxd == 1) { +#if 0 + meta->frame_type = GET_RX_AX_DESC_TYPE(rxd); +#endif + meta->mc = GET_RX_AX_DESC_MC(rxd); + meta->bc = GET_RX_AX_DESC_BC(rxd); +#if 0 + meta->more_data = GET_RX_AX_DESC_MD(rxd); +#endif + meta->more_frag = GET_RX_AX_DESC_MF(rxd); +#if 0 + meta->pwr_bit = GET_RX_AX_DESC_PWR(rxd); +#endif + meta->qos = GET_RX_AX_DESC_QOS(rxd); + + meta->tid = GET_RX_AX_DESC_TID(rxd); +#if 0 + meta->eosp = GET_RX_AX_DESC_EOSP(rxd); + meta->htc = GET_RX_AX_DESC_HTC(rxd); +#endif + meta->q_null = GET_RX_AX_DESC_QNULL(rxd); + meta->seq = GET_RX_AX_DESC_SEQ(rxd); + meta->frag_num = GET_RX_AX_DESC_FRAG(rxd); + +#if 0 + meta->sec_cam_idx = GET_RX_AX_DESC_CAM_IDX(rxd); + meta->addr_cam = GET_RX_AX_DESC_ADDR_CAM(rxd); + + meta->macid = GET_RX_AX_DESC_MACID(rxd); + meta->rx_pl_id = GET_RX_AX_DESC_PL_ID(rxd); + meta->addr_cam_vld = GET_RX_AX_DESC_CAM_VLD(rxd); + meta->addr_fwd_en = GET_RX_AX_DESC_FWD_EN(rxd); + meta->rx_pl_match = GET_RX_AX_DESC_PL_MATCH(rxd); +#endif + + _os_mem_cpy(hal->drv_priv, + (void*)&meta->mac_addr, (void*)(rxd + 24), MAC_ALEN); + } +} + +int rtw_hal_mac_sdio_parse_rx(struct rtw_hal_com_t *hal, + struct rtw_rx_buf *rxbuf) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_rxpkt_info info; + struct sdio_rx_pkt *pkt; + u8 *ptr; + u32 len; + int i; + u32 offset; + u32 err = MACSUCCESS; + + + rxbuf->agg_cnt = 0; + rxbuf->agg_start = 0; + ptr = rxbuf->ptr; + len = rxbuf->len; + + for (i = 0; i < MAX_BUS_RX_AGG; i++) { + _os_mem_set(hal->drv_priv, &info, 0, sizeof(info)); + err = mac->ops->parse_rxdesc(mac, &info, ptr, len); + if (err != MACSUCCESS) { + PHL_ERR("%s: agg_idx=%d, len=%u(%u), parse_rxdesc FAIL!(%u)\n", + __func__, i, len, rxbuf->len, err); + rxbuf->len -= len; + len = 0; + break; + } + + pkt = &rxbuf->pkt[i]; + _os_mem_set(hal->drv_priv, pkt, 0, sizeof(*pkt)); + + pkt->wd = ptr; + pkt->wd_len = (u8)info.rxdlen; + offset = info.rxdlen + (info.drvsize * 8) + (info.shift * 2); + pkt->pkt = ptr + offset; + pkt->pkt_len = (u16)info.pktsize; + hal_mac_parse_rxpkt_info(&info, &pkt->meta); + hal_mac_parse_rxd(hal, ptr, &pkt->meta); + _os_mem_cpy(hal->drv_priv, pkt->meta.ta, pkt->pkt + 10, 6); + + offset += info.pktsize; + + offset = _ALIGN(offset, 8); +#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX + if (pkt->meta.chksum_ofld_en) { + u8 status; + u32 result; + + status = *(ptr + offset); + result = mac->ops->chk_rx_tcpip_chksum_ofd(mac, status); + hal_mac_parse_rxd_checksume(hal, &pkt->meta, result); + offset += 8; + } +#endif /* CONFIG_PHL_CSUM_OFFLOAD_RX */ + ptr += offset; + if (offset >= len) { + len = 0; + i++; + break; + } + len -= offset; + } + + rxbuf->agg_cnt = (u8)i; + if (len) { + /* not finish yet */ + rxbuf->next_ptr = ptr; + offset = (u32)(ptr - rxbuf->ptr); + } else { + rxbuf->next_ptr = NULL; + offset = rxbuf->len; + } + + return offset; +} + +int rtw_hal_mac_sdio_rx(struct rtw_hal_com_t *hal, struct rtw_rx_buf *rxbuf) +{ + u32 len; + + + len = hal_read32(hal, R_AX_SDIO_RX_REQ_LEN) & B_AX_RX_REQ_LEN_MSK; + if (!len) + return 0; + if (len > rxbuf->buf_len) { + /* TODO: read and drop */ + return 0; + } + + if (_FAIL == hal_sdio_cmd53_r(hal, SDIO_CMD_ADDR_RXFF, len, rxbuf->buffer)) + return 0; + + rxbuf->used_len = len; + rxbuf->ptr = rxbuf->buffer; + rxbuf->len = len; + +#ifndef CONFIG_PHL_SDIO_READ_RXFF_IN_INT + len = rtw_hal_mac_sdio_parse_rx(hal, rxbuf); +#endif + + return len; +} +#endif /*CONFIG_SDIO_HCI*/ + +enum rtw_hal_status rtw_hal_mac_get_pwr_state(struct hal_info_t *hal_info, + enum rtw_mac_pwr_st *pwr_state) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + enum mac_ax_mac_pwr_st st; + + if (hal_mac_ops->get_hw_value(mac, MAC_AX_HW_GET_PWR_STATE, &st) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s : retrieve WL MAC state %u\n", __func__, st); + + switch (st) { + case MAC_AX_MAC_OFF: + *pwr_state = RTW_MAC_PWR_OFF; + break; + case MAC_AX_MAC_ON: + *pwr_state = RTW_MAC_PWR_ON; + break; + case MAC_AX_MAC_LPS: + *pwr_state = RTW_MAC_PWR_LPS; + break; + default: + *pwr_state = RTW_MAC_PWR_NONE; + break; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +/* halmac wrapper API for hal and proto type is at hal_api_mac.h */ +enum rtw_hal_status +rtw_hal_mac_power_switch(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 on_off) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + //u8 pwr_state = 0; + + /*pwr_state = hal_mac_get_pwr_state(mac); + if(pwr_state != on_off)*/ + + if (mac->ops->pwr_switch(mac, on_off) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef DBG_PHL_MAC_REG_RW +#define HALPHY_BASE_OFFSET 0x10000 + +bool rtw_hal_mac_reg_chk(struct rtw_hal_com_t *hal_com, u32 addr) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + bool rst = true; + u32 mac_rst; + + if (addr & HALPHY_BASE_OFFSET) + goto _exit; + + if (mac != NULL && mac->ops->io_chk_access) { + mac_rst = mac->ops->io_chk_access(mac, addr); + if (mac_rst != MACSUCCESS) { + rst = false; + PHL_ERR("%s failed - addr(0x%08x) is err code(%d)\n", + __func__, addr, mac_rst); + _os_warn_on(1); + } + } +_exit: + return rst; +} +#endif + +/* halmac wrapper API for hal and proto type is at hal_api_mac.h */ +enum rtw_hal_status rtw_hal_mac_dbcc_pre_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 dbcc_en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_trx_info trx_info = { 0 }; + struct mac_ax_pkt_drop_info drop_info = { 0 }; + + if (dbcc_en) { + if (true == phl_com->dev_cap.tx_mu_ru) + trx_info.trx_mode = MAC_AX_TRX_SW_MODE; + else + trx_info.trx_mode = MAC_AX_TRX_HW_MODE; + trx_info.qta_mode = MAC_AX_QTA_DBCC; + + if (mac->ops->dbcc_enable(mac, &trx_info, dbcc_en) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + } else { + /* disable FW band 1 feature (H2C) */ + + drop_info.sel = MAC_AX_PKT_DROP_SEL_BAND; + drop_info.band = MAC_AX_BAND_1; + + if (mac->ops->pkt_drop(mac, &drop_info) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_dbcc_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 dbcc_en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_trx_info trx_info = { 0 }; + + if (dbcc_en) { + /* Pass Throught, mac already enable at pre_cfg */ + } else { + if (true == phl_com->dev_cap.tx_mu_ru) + trx_info.trx_mode = MAC_AX_TRX_SW_MODE; + else + trx_info.trx_mode = MAC_AX_TRX_HW_MODE; + trx_info.qta_mode = MAC_AX_QTA_SCC; + + if (mac->ops->dbcc_enable(mac, &trx_info, dbcc_en) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_mac_coex_init(struct rtw_hal_com_t *hal_com, u8 pta_mode, u8 direction) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_coex pta_para; + + pta_para.pta_mode = pta_mode; + pta_para.direction = direction; + + return (ops->coex_init(mac, &pta_para)); +} + +u32 rtw_hal_mac_coex_reg_read(struct rtw_hal_com_t *hal_com, u32 offset, u32 *value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + /* valid offset -> 0xda00~0xdaff */ + offset = offset & 0xff; + + return (ops->coex_read(mac, offset, value)); +} + +u32 rtw_hal_mac_set_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + return (ops->set_hw_value(mac, MAC_AX_HW_SET_SCOREBOARD, value)); +} + +u32 rtw_hal_mac_get_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + return (ops->get_hw_value(mac, MAC_AX_HW_GET_SCOREBOARD, value)); +} + +u32 rtw_hal_mac_set_grant(struct rtw_hal_com_t *hal_com, u8 *value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_coex_gnt gnt_val; + + gnt_val.band0.gnt_bt_sw_en = value[0]; + gnt_val.band0.gnt_bt = value[1]; + gnt_val.band0.gnt_wl_sw_en = value[2]; + gnt_val.band0.gnt_wl = value[3]; + + gnt_val.band1.gnt_bt_sw_en = value[4]; + gnt_val.band1.gnt_bt = value[5]; + gnt_val.band1.gnt_wl_sw_en = value[6]; + gnt_val.band1.gnt_wl = value[7]; + + return (ops->set_hw_value(mac, MAC_AX_HW_SET_COEX_GNT, &gnt_val)); +} + +u32 rtw_hal_mac_get_grant(struct rtw_hal_com_t *hal_com, u8 *value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + return (ops->get_hw_value(mac, MAC_AX_HW_GET_COEX_GNT, value)); +} + +u32 rtw_hal_mac_set_polluted(struct rtw_hal_com_t *hal_com, u8 band, u8 tx_val, u8 rx_val) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_plt plt_val; + + plt_val.band = band; + plt_val.tx = tx_val; + plt_val.rx = rx_val; + + return (ops->set_hw_value(mac, MAC_AX_HW_SET_POLLUTED, &plt_val)); +} + +u32 rtw_hal_mac_set_tx_time(struct rtw_hal_com_t *hal_com, u8 is_btc, u8 is_resume, u8 macid, u32 tx_time) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_max_tx_time max_tx_time; + u32 result = 0xffffffff; + + max_tx_time.macid = macid; + max_tx_time.is_cctrl = 1; + max_tx_time.max_tx_time = tx_time; + + if (is_btc && !is_resume) { /* for btc control tx time case */ + hal_com->btc_ctrl.tx_time = true; + result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time); + } else if (is_btc && is_resume) { /* for btc release tx time case */ + result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time); + hal_com->btc_ctrl.tx_time = false; + } else { /* not btc control case */ + if (hal_com->btc_ctrl.tx_time) + return result; + else + result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time); + } + + return result; +} + +u32 rtw_hal_mac_get_tx_time(struct rtw_hal_com_t *hal_com, u8 macid, u32 *tx_time) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_max_tx_time max_tx_time; + u32 result; + + max_tx_time.macid = macid; + max_tx_time.is_cctrl = 1; + max_tx_time.max_tx_time = *tx_time; + + result = ops->get_hw_value(mac, MAC_AX_HW_GET_MAX_TX_TIME, &max_tx_time); + *tx_time = max_tx_time.max_tx_time; + + return (result); +} + +u32 rtw_hal_mac_set_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 is_btc, u8 is_resume, u8 macid, u8 tx_retry) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_cctl_rty_lmt_cfg tx_retry_limit; + u32 result = 0xffffffff; + + tx_retry_limit.macid = macid; + tx_retry_limit.data_lmt_sel = 1; + tx_retry_limit.data_lmt_val = tx_retry; + tx_retry_limit.rts_lmt_sel = 0; + tx_retry_limit.rts_lmt_val = 0; + + if (is_btc && !is_resume) { /* for btc control tx time case */ + hal_com->btc_ctrl.tx_retry = true; + result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit); + } else if (is_btc && is_resume) { /* for btc release tx time case */ + result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit); + hal_com->btc_ctrl.tx_retry = false; + } else { /* not btc control case */ + if (hal_com->btc_ctrl.tx_retry) + return result; + else + result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit); + } + + return result; +} + +u32 rtw_hal_mac_get_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 macid, u8 *tx_retry) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_rty_lmt tx_retry_limit; + u32 result; + + tx_retry_limit.macid = macid; + tx_retry_limit.tx_cnt = *tx_retry; + result = ops->get_hw_value(mac, MAC_AX_HW_GET_DATA_RTY_LMT, &tx_retry_limit); + *tx_retry = (u8)tx_retry_limit.tx_cnt; + + return (result); +} + +u32 rtw_hal_mac_get_bt_polt_cnt(struct rtw_hal_com_t *hal_com, u8 band, u16 *cnt) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_bt_polt_cnt polt; + u32 result; + + polt.band = band; + polt.cnt = *cnt; + result = ops->get_hw_value(mac, MAC_AX_HW_GET_POLLUTED_CNT, &polt); + *cnt = polt.cnt; + + return (result); +} + +u32 rtw_hal_mac_set_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 val) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + return (ops->set_hw_value(mac, MAC_AX_HW_SET_COEX_CTRL, &val)); +} + +u32 rtw_hal_mac_get_coex_ctrl(struct rtw_hal_com_t *hal_com, u32* val) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + return (ops->get_hw_value(mac, MAC_AX_HW_GET_COEX_CTRL, val)); +} + +u32 rtw_hal_mac_coex_reg_write(struct rtw_hal_com_t *hal_com, u32 offset, u32 value) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + + /* valid offset -> 0xda00~0xdaff */ + offset = offset & 0xff; + + return (ops->coex_write(mac, offset, value)); +} + +/* halmac wrapper API for hal and proto type is at hal_api_drv.h */ +u32 rtw_hal_mac_send_h2c(struct rtw_hal_com_t *hal_com, + struct rtw_g6_h2c_hdr *hdr, u32 *pvalue) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + u32 mac_err = 0; + + mac_err = ops->outsrc_h2c_common(mac, hdr, pvalue); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +static enum mac_ax_net_type +_rtype_to_mac_nettype(struct rtw_wifi_role_t *wifi_role) +{ + enum mac_ax_net_type net_type = MAC_AX_NET_TYPE_NO_LINK; + + switch (wifi_role->type) { + case PHL_RTYPE_STATION: + case PHL_RTYPE_TDLS: + net_type = (wifi_role->mstate == MLME_NO_LINK) + ? MAC_AX_NET_TYPE_NO_LINK + : MAC_AX_NET_TYPE_INFRA; + break; + case PHL_RTYPE_MONITOR: + case PHL_RTYPE_P2P_DEVICE: + net_type = MAC_AX_NET_TYPE_NO_LINK; + break; + case PHL_RTYPE_P2P_GC: + net_type = MAC_AX_NET_TYPE_INFRA; + break; + case PHL_RTYPE_AP: + case PHL_RTYPE_P2P_GO: + case PHL_RTYPE_MESH: + net_type = MAC_AX_NET_TYPE_AP; + break; + case PHL_RTYPE_ADHOC: + case PHL_RTYPE_ADHOC_MASTER: + net_type = MAC_AX_NET_TYPE_ADHOC; + break; + case PHL_RTYPE_NAN: /*TODO*/ + default: + net_type = MAC_AX_NET_TYPE_NO_LINK; + break; + } + + return net_type; +} + + +enum rtw_hal_status +rtw_hal_mac_port_init(struct hal_info_t *hal_info, + struct rtw_wifi_role_t *wifi_role) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_port_init_para ppara = {0}; + struct rtw_phl_stainfo_t *phl_sta; + + ppara.net_type = _rtype_to_mac_nettype(wifi_role); + ppara.band_idx = wifi_role->hw_band; + ppara.port_idx = wifi_role->hw_port; + /*#ifdef CONFIG_AP*/ + ppara.hiq_win = wifi_role->hiq_win; + ppara.dtim_period = wifi_role->dtim_period; + ppara.mbid_num = wifi_role->mbid_num;/*max mbid number*/ + /*#endif - CONFIG_AP*/ + + if (ppara.net_type == MAC_AX_NET_TYPE_INFRA) { + phl_sta = rtw_phl_get_stainfo_self(wifi_role->phl_com->phl_priv, + wifi_role); + if (phl_sta->asoc_cap.bcn_interval) + ppara.bcn_interval = phl_sta->asoc_cap.bcn_interval; + else + ppara.bcn_interval = 100; + ppara.bss_color = phl_sta->asoc_cap.bsscolor; + } else if (ppara.net_type == MAC_AX_NET_TYPE_AP) { + #ifdef RTW_PHL_BCN + ppara.bcn_interval = (u16)wifi_role->bcn_cmn.bcn_interval; + #else + ppara.bcn_interval = 100; + #endif + ppara.bss_color = wifi_role->proto_role_cap.bsscolor; + } else if (ppara.net_type == MAC_AX_NET_TYPE_ADHOC) { + /* TODO */ + ppara.bcn_interval = 100; + } else { + /* other net_type, i.e. MAC_AX_NO_LINK */ + ppara.bcn_interval = 100; + } + + if (mac->ops->port_init(mac, &ppara) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_port_cfg(struct hal_info_t *hal_info, + struct rtw_wifi_role_t *wifi_role, + enum pcfg_type type, void *param) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_port_cfg_type ptype = MAC_AX_PCFG_FUNC_SW; + struct mac_ax_port_cfg_para ppara = {0}; + + switch (type){ + case PCFG_FUNC_SW : + ptype = MAC_AX_PCFG_FUNC_SW; + break; + case PCFG_TBTT_AGG : + ptype = MAC_AX_PCFG_TBTT_AGG; + break; + case PCFG_TBTT_SHIFT : + ptype = MAC_AX_PCFG_TBTT_SHIFT; + break; + case PCFG_HIQ_WIN : + ptype = MAC_AX_PCFG_HIQ_WIN; + break; + case PCFG_HIQ_DTIM : + ptype = MAC_AX_PCFG_HIQ_DTIM; + break; + case PCFG_BCN_INTERVAL : + ptype = MAC_AX_PCFG_BCN_INTV; + break; + case PCFG_BSS_CLR : + ptype = MAC_AX_PCFG_BSS_CLR; + break; + case PCFG_BCN_EN : + ptype = MAC_AX_PCFG_TX_SW; + break; + default : + PHL_ERR("Unknown port cfg type %d\n", type); + goto _error; + } + + ppara.band = wifi_role->hw_band; + ppara.port = wifi_role->hw_port; + #ifdef RTW_PHL_BCN/*#ifdef CONFIG_AP*/ + ppara.mbssid_idx = wifi_role->hw_mbssid; + #endif + ppara.val = *(u32 *)param; + + if (mac->ops->port_cfg(mac, ptype, &ppara) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; +_error: + return RTW_HAL_STATUS_FAILURE; +} + +static enum mac_ax_wifi_role +_rtype_to_mac_wifirole(struct rtw_wifi_role_t *wifi_role) +{ + enum mac_ax_wifi_role mac_wifi_role = MAC_AX_WIFI_ROLE_NONE; + + switch (wifi_role->type) { + case PHL_RTYPE_NONE: + mac_wifi_role = MAC_AX_WIFI_ROLE_NONE; + break; + case PHL_RTYPE_STATION: + case PHL_RTYPE_TDLS: + mac_wifi_role = MAC_AX_WIFI_ROLE_STATION; + break; + case PHL_RTYPE_AP: + mac_wifi_role = MAC_AX_WIFI_ROLE_AP; + break; + case PHL_RTYPE_VAP: + mac_wifi_role = MAC_AX_WIFI_ROLE_VAP; + break; + case PHL_RTYPE_ADHOC: + mac_wifi_role = MAC_AX_WIFI_ROLE_ADHOC; + break; + case PHL_RTYPE_ADHOC_MASTER: + mac_wifi_role = MAC_AX_WIFI_ROLE_ADHOC_MASTER; + break; + case PHL_RTYPE_MESH: + mac_wifi_role = MAC_AX_WIFI_ROLE_MESH; + break; + case PHL_RTYPE_MONITOR: + mac_wifi_role = MAC_AX_WIFI_ROLE_MONITOR; + break; + case PHL_RTYPE_P2P_DEVICE: + mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_DEVICE; + break; + case PHL_RTYPE_P2P_GC: + mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_GC; + break; + case PHL_RTYPE_P2P_GO: + mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_GO; + break; + case PHL_RTYPE_NAN: + mac_wifi_role = MAC_AX_WIFI_ROLE_NAN; + break; + default: + mac_wifi_role = MAC_AX_WIFI_ROLE_STATION; + break; + } + + return mac_wifi_role; +} + +static enum mac_ax_upd_mode + _hal_updmode_to_mac_upt_mode(enum phl_upd_mode mode) +{ + enum mac_ax_upd_mode upd_mode = MAC_AX_ROLE_INFO_CHANGE; + + switch (mode) { + case PHL_UPD_ROLE_CREATE: + upd_mode = MAC_AX_ROLE_CREATE; + break; + case PHL_UPD_ROLE_REMOVE: + upd_mode = MAC_AX_ROLE_REMOVE; + break; + case PHL_UPD_ROLE_TYPE_CHANGE: + upd_mode = MAC_AX_ROLE_TYPE_CHANGE; + break; + case PHL_UPD_ROLE_INFO_CHANGE: + case PHL_UPD_STA_INFO_CHANGE: + upd_mode = MAC_AX_ROLE_INFO_CHANGE; + break; + case PHL_UPD_STA_CON_DISCONN: + upd_mode = MAC_AX_ROLE_CON_DISCONN; + break; + case PHL_UPD_ROLE_MAX: + /* fallthrough */ + default: + PHL_ERR("error upt mode %d\n", mode); + break; + } + + return upd_mode; +} + +static void _hal_stainfo_to_macrinfo(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, + struct mac_ax_role_info *rinfo, + enum phl_upd_mode mode, + bool is_connect) +{ + struct rtw_wifi_role_t *wifi_role = sta->wrole; + void *drv = hal_to_drvpriv(hal_info); + bool is_self = false; + + rinfo->macid = (u8)sta->macid; + rinfo->band = wifi_role->hw_band; + rinfo->port = wifi_role->hw_port; + rinfo->wmm = wifi_role->hw_wmm; + + rinfo->net_type = _rtype_to_mac_nettype(wifi_role); + rinfo->wifi_role = _rtype_to_mac_wifirole(wifi_role); + rinfo->bcn_hit_cond = sta->bcn_hit_cond; + rinfo->hit_rule = sta->hit_rule; + rinfo->tsf_sync = wifi_role->hw_port; + rinfo->aid = sta->aid; + rinfo->wapi = sta->wapi; + rinfo->sec_ent_mode = sta->sec_mode; + rinfo->upd_mode = _hal_updmode_to_mac_upt_mode(mode); + rinfo->opmode = (is_connect == true) ? MAC_AX_ROLE_CONNECT : MAC_AX_ROLE_DISCONN; + + if (rinfo->net_type == MAC_AX_NET_TYPE_AP) { + if (_os_mem_cmp(drv, wifi_role->mac_addr, sta->mac_addr, MAC_ALEN) == 0) + is_self = true; + + if(is_self == true) { + rinfo->self_role = MAC_AX_SELF_ROLE_AP; + } else { + rinfo->self_role = MAC_AX_SELF_ROLE_AP_CLIENT; + /* for ap client disconnect case, + need to set no-link only for MAC_AX_ROLE_CON_DISCONN mode */ + if (is_connect == false && rinfo->upd_mode == MAC_AX_ROLE_CON_DISCONN) + rinfo->net_type = MAC_AX_NET_TYPE_NO_LINK; + /* only for client under AX SoftAP mode */ + if (sta->wmode & WLAN_MD_11AX) + rinfo->tf_mac_padding = sta->asoc_cap.trig_padding; + } + } else if (rinfo->net_type == MAC_AX_NET_TYPE_INFRA || rinfo->net_type == MAC_AX_NET_TYPE_NO_LINK) { + rinfo->self_role = MAC_AX_SELF_ROLE_CLIENT; + } + + if ((sta->wmode & WLAN_MD_11AX) && (wifi_role->mstate == MLME_LINKED)) { + rinfo->trigger = sta->tf_trs; + rinfo->bss_color = sta->asoc_cap.bsscolor; + rinfo->addr_mask = (sta->addr_msk > 0)?MAC_AX_BYTE5:MAC_AX_MSK_NONE; + rinfo->mask_sel = (sta->addr_sel > 0)?MAC_AX_BSSID_MSK:MAC_AX_NO_MSK; + } + + //TODO + switch (rinfo->net_type) { + case MAC_AX_NET_TYPE_NO_LINK : + _os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN); + break; + case MAC_AX_NET_TYPE_ADHOC : + _os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN); + break; + case MAC_AX_NET_TYPE_INFRA : + rinfo->aid = sta->aid; + _os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN); + _os_mem_cpy(drv, rinfo->target_mac, sta->mac_addr, MAC_ALEN); + _os_mem_cpy(drv, rinfo->bssid, sta->mac_addr, MAC_ALEN); + break; + case MAC_AX_NET_TYPE_AP : + _os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN); + _os_mem_cpy(drv, rinfo->target_mac, sta->mac_addr, MAC_ALEN); + _os_mem_cpy(drv, rinfo->bssid, wifi_role->mac_addr, MAC_ALEN); + break; + default : + break; + } + +} + + +enum rtw_hal_status +rtw_hal_mac_role_sync(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_role_info mac_rinfo = {0}; + u32 rst = 0; + + _hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, PHL_UPD_ROLE_CREATE, + false); + + rst = mac->ops->role_sync(mac, &mac_rinfo); + + if ((rst == MACSUCCESS) || (rst == MACSAMACID)) + return RTW_HAL_STATUS_SUCCESS; + + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_addr_cam_add_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_role_info mac_rinfo = {0}; + u32 rst = 0; + + _hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, PHL_UPD_ROLE_CREATE, false); + + rst = mac->ops->add_role(mac, &mac_rinfo); + + if ((rst == MACSUCCESS) || (rst == MACSAMACID)) + return RTW_HAL_STATUS_SUCCESS; + + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_addr_cam_change_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, + enum phl_upd_mode mode, + bool is_connect) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_role_info mac_rinfo = {0}; + + _hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, mode, is_connect); + + if (mac->ops->change_role(mac, &mac_rinfo) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_addr_cam_set_aid(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, + u16 aid) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_role_info mac_rinfo = {0}; + + _hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, PHL_UPD_STA_INFO_CHANGE, true); + + mac_rinfo.aid = aid; + + if (mac->ops->change_role(mac, &mac_rinfo) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + + return RTW_HAL_STATUS_FAILURE; +} + + +enum rtw_hal_status +rtw_hal_mac_addr_cam_del_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->remove_role(mac, (u8)sta->macid) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_add_key(struct hal_info_t *hal_info, u8 macid, u8 type, u8 ext_key, + u8 spp, u8 keyid, u8 keytype, u8 *keybuf) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + void *drv = hal_to_drvpriv(hal_info); + struct mac_ax_sec_cam_info sec_cam; + u32 mac_err; + + sec_cam.type = type; + sec_cam.ext_key = ext_key; + sec_cam.spp_mode = spp; + sec_cam.len = 20; + sec_cam.offset = 0; + _os_mem_set(drv, &sec_cam.key, 0, sizeof(sec_cam.key)); + + switch (type) + { + case RTW_ENC_WEP40: + _os_mem_cpy(drv, &sec_cam.key, keybuf, 5); + break; + case RTW_ENC_WEP104: + _os_mem_cpy(drv, &sec_cam.key, keybuf, 13); + break; + case RTW_ENC_TKIP: + case RTW_ENC_CCMP: + case RTW_ENC_CCMP256: + case RTW_ENC_GCMP: + case RTW_ENC_GCMP256: + case RTW_ENC_BIP_CCMP128: + case RTW_ENC_WAPI: + case RTW_ENC_GCMSMS4: + _os_mem_cpy(drv, &sec_cam.key, keybuf, 16); + break; + default: + break; + } + + mac_err = mac->ops->sta_add_key(mac, &sec_cam, macid, keyid, keytype); + + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_delete_key(struct hal_info_t *hal_info, u8 macid, u8 type, + u8 ext_key, u8 spp, u8 keyid, u8 keytype) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_err; + + mac_err = mac->ops->sta_del_key(mac, macid, keyid, keytype); + + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +u32 +rtw_hal_mac_search_key_idx(struct hal_info_t *hal_info, u8 macid, + u8 keyid, u8 keytype) +{ + u32 sec_cam_idx; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + sec_cam_idx = mac->ops->sta_search_key_idx(mac, macid, keyid, keytype); + + return sec_cam_idx; +} + +u32 +rtw_hal_mac_ser_reset_wdt_intr(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + u8 dummyval = 0; + u32 result = 0xffffffff; + + result = ops->set_hw_value(mac, MAC_AX_HW_SET_WDT_ISR_RST, &dummyval); + + return result; +} + +enum rtw_hal_status +rtw_hal_mac_ser_get_error_status(struct hal_info_t *hal_info, u32 *err) +{ + u32 mac_err = 0; + enum mac_ax_err_info err_info = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac_err = mac->ops->get_err_status(mac, &err_info); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + *err = err_info; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_ser_set_error_status(struct hal_info_t *hal_info, enum RTW_PHL_SER_RCVY_STEP err) +{ + u32 mac_err = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 err_info = 0; + + if (err == RTW_PHL_SER_L1_DISABLE_EN) { + err_info = MAC_AX_ERR_L1_DISABLE_EN; + } else if (err == RTW_PHL_SER_L1_RCVY_EN) { + err_info = MAC_AX_ERR_L1_RCVY_EN; + } else if (err == RTW_PHL_SER_L0_CFG_NOTIFY) { + err_info = MAC_AX_ERR_L0_CFG_NOTIFY; + } else if (err == RTW_PHL_SER_L0_CFG_DIS_NOTIFY) { + err_info = MAC_AX_ERR_L0_CFG_DIS_NOTIFY; + } else if (err == RTW_PHL_SER_L0_CFG_HANDSHAKE) { + err_info = MAC_AX_ERR_L0_CFG_HANDSHAKE; + } else if (err == RTW_PHL_SER_L0_RCVY_EN) { + err_info = MAC_AX_ERR_L0_RCVY_EN; + } + PHL_INFO("%s : error info to mac 0x%x.\n", __func__, err_info); + + mac_err = mac->ops->set_err_status(mac, err_info); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_trigger_cmac_err(struct hal_info_t *hal_info) +{ + u32 mac_err = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac_err = mac->ops->trigger_cmac_err(mac); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_trigger_dmac_err(struct hal_info_t *hal_info) +{ + u32 mac_err = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac_err = mac->ops->trigger_dmac_err(mac); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_lv1_rcvy(struct hal_info_t *hal_info, enum rtw_phl_ser_lv1_recv_step step) +{ + u32 mac_err = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac_err = mac->ops->lv1_rcvy(mac, step); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_ser_ctrl(struct hal_info_t *hal_info, bool en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_err = 0; + enum mac_ax_func_sw cfg = (en == true) ? MAC_AX_FUNC_EN : MAC_AX_FUNC_DIS; + u32 start_t = 0; + + start_t = _os_get_cur_time_us(); + + PHL_INFO("%s\n", __func__); + + mac_err = mac->ops->ser_ctrl(mac, cfg); + + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s : %s ser success with %d us.\n", __func__, + (en ? "start" : "stop"), phl_get_passing_time_us(start_t)); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_poll_hw_tx_done(struct hal_info_t *hal_info) +{ + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "poll hw tx done is not supported now!\n"); + return RTW_HAL_STATUS_MAC_API_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_hw_tx_resume(struct hal_info_t *hal_info) +{ + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "resume hw tx is not supported now!\n"); + return RTW_HAL_STATUS_MAC_API_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_poll_hw_rx_done(struct hal_info_t *hal_info) +{ + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "poll hw rx done is not supported now!\n"); + return RTW_HAL_STATUS_MAC_API_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_hw_rx_resume(struct hal_info_t *hal_info) +{ + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "resume hw rx is not supported now!\n"); + return RTW_HAL_STATUS_MAC_API_FAILURE; +} + + +#define FW_PLE_SIZE 0x800 +#define FW_PLE_SEGMENT_SIZE 512 /*Because PHL_PRINT have prefix 5 bytes "PHL: "*/ + +void +_hal_fw_dbg_dump(struct hal_info_t *hal_info, u8 *buffer, u16 bufsize) +{ + char str[FW_PLE_SEGMENT_SIZE + 1] = {0}; + u16 i = 0, ofst = 0; + + for (ofst = 0; ofst < bufsize; ofst += FW_PLE_SEGMENT_SIZE) { + for (i = 0; i < FW_PLE_SEGMENT_SIZE; i++) + _os_snprintf(str + i, 2, "%c", buffer[i + ofst]); + PHL_PRINT("%s\n", str); + _os_mem_set(hal_to_drvpriv(hal_info), str, 0, sizeof(str)); + } +} + +enum rtw_hal_status +rtw_hal_mac_dump_fw_rsvd_ple(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u8 *buffer = NULL; + u16 bufSize = FW_PLE_SIZE; + + if(mac->ops->dump_fw_rsvd_ple(mac, &buffer) != 0) { + PHL_ERR("%s fail!\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + if (buffer != NULL) { + PHL_PRINT("=======================\n"); + PHL_PRINT("Start to dump fw rsvd ple :\n\n"); + _hal_fw_dbg_dump(hal_info, buffer, bufSize); + PHL_PRINT("\n=======================\n"); + _os_mem_free(hal_info->hal_com->drv_priv, buffer, bufSize); + } else { + PHL_ERR("dump_fw_rsvd_ple return invalid buffer!\n"); + } + + return RTW_HAL_STATUS_SUCCESS; +} + + +/* + * halmac wrapper API for hal and proto type is at hal_api_mac.h + * init HW scope or start HW scope? + */ +enum rtw_hal_status +rtw_hal_mac_init_mac(void *mac,struct hal_init_info_t *init_info) +{ + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct mac_ax_ops *hal_mac_ops = mac_info->ops; + struct mac_ax_trx_info trx_info; + + trx_info.trx_mode = init_info->trx_info.trx_mode; + trx_info.qta_mode = init_info->trx_info.qta_mode; + + if (hal_mac_ops->sys_init(mac_info)) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + if (hal_mac_ops->trx_init(mac_info, &trx_info)) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_trx_init(void *mac, struct hal_init_info_t *init_info) +{ + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct mac_ax_ops *hal_mac_ops = mac_info->ops; + struct mac_ax_trx_info trx_info; + + trx_info.trx_mode = init_info->trx_info.trx_mode; + trx_info.qta_mode = init_info->trx_info.qta_mode; + + if (hal_mac_ops->trx_init(mac_info, &trx_info)) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +void _hal_mac_get_ofld_cap(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ +#ifdef CONFIG_FW_IO_OFLD_SUPPORT + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_status = 0; + + mac_status = mac->ops->get_hw_value(mac, MAC_AX_HW_GET_FW_CAP, + &(hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap)); + if (mac_status == MACSUCCESS) { + phl_com->dev_cap.fw_cap.offload_cap = phl_com->dev_sw_cap.fw_cap.offload_cap & + hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap; + PHL_INFO("%s: sw ofld cap: 0x%x, fw ofld cap 0x%x, final ofld cap: 0x%x!\n", __func__, + phl_com->dev_sw_cap.fw_cap.offload_cap, + hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap, + phl_com->dev_cap.fw_cap.offload_cap); + } else { + hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap = 0; + phl_com->dev_cap.fw_cap.offload_cap = 0; + PHL_WARN("%s: fw ofld cap not enabled.\n", __func__); + } +#else + hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap = 0; + phl_com->dev_cap.fw_cap.offload_cap = 0; + PHL_INFO("%s: fw ofld cap not enabled.\n", __func__); +#endif +} + +enum rtw_hal_status +rtw_hal_mac_hal_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct mac_ax_fwdl_info fwdl_info; + u32 mac_status = 0; + enum rtw_fw_type fw_type = RTW_FW_MAX; +#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX + u8 tx_chksum_offload = 0; + u8 rx_chksum_offload = 0; +#endif + FUNCIN_WSTS(hstatus); + +#ifdef PHL_FEATURE_NIC + fw_type = RTW_FW_NIC; +#elif defined(PHL_FEATURE_AP) + fw_type = RTW_FW_AP; +#else + fw_type = RTW_FW_MAX; +#endif + + hstatus = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, fw_type); + if(RTW_HAL_STATUS_SUCCESS != hstatus) { + PHL_ERR("%s : Cfg FW Failed: %d!\n", __func__, hstatus); + return hstatus; + } + /* fwdl_info */ + fwdl_info.fw_en = fw_info->fw_en; + fwdl_info.dlram_en = fw_info->dlram_en; + fwdl_info.dlrom_en = fw_info->dlrom_en; + fwdl_info.ram_buff = fw_info->ram_buff; + fwdl_info.ram_size = fw_info->ram_size; + fwdl_info.rom_buff = fw_info->rom_buff; + fwdl_info.rom_size = fw_info->rom_size; + fwdl_info.fw_cat = fw_info->fw_type; + + if(fw_info->fw_src == RTW_FW_SRC_EXTNAL) + fwdl_info.fw_from_hdr = 0; + else + fwdl_info.fw_from_hdr = 1; + + mac_status = mac->ops->hal_init(mac, &init_info->trx_info, &fwdl_info, &init_info->intf_info); + + if (mac_status == MACSUCCESS) { + hstatus = RTW_HAL_STATUS_SUCCESS; + hal_mac_print_fw_version(hal_info); + } else { + hstatus = RTW_HAL_STATUS_MAC_INIT_FAILURE; + PHL_ERR("%s : mac_status %d!\n", __func__, mac_status); + } + _hal_mac_get_ofld_cap(phl_com, hal_info); +#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX + rx_chksum_offload = 1; + mac_status = mac->ops->tcpip_chksum_ofd(mac, tx_chksum_offload, rx_chksum_offload); + if (mac_status != MACSUCCESS) + PHL_ERR("%s : tcpip_chksum_ofd mac_status %d!!!!!!!\n", __func__, mac_status); +#endif + + FUNCOUT_WSTS(hstatus); + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_hal_fast_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct mac_ax_fwdl_info fwdl_info; + u32 mac_status = 0; + enum rtw_fw_type fw_type = RTW_FW_MAX; + + FUNCIN_WSTS(hstatus); + +#ifdef PHL_FEATURE_NIC + fw_type = RTW_FW_NIC; +#elif defined(PHL_FEATURE_AP) + fw_type = RTW_FW_AP; +#else + fw_type = RTW_FW_MAX; +#endif + hstatus = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, fw_type); + if(RTW_HAL_STATUS_SUCCESS != hstatus) { + PHL_ERR("%s : Cfg FW Failed: %d!\n", __func__, hstatus); + return hstatus; + } + + /* fwdl_info */ + fwdl_info.fw_en = fw_info->fw_en; + fwdl_info.dlram_en = fw_info->dlram_en; + fwdl_info.dlrom_en = fw_info->dlrom_en; + fwdl_info.ram_buff = fw_info->ram_buff; + fwdl_info.ram_size = fw_info->ram_size; + fwdl_info.rom_buff = fw_info->rom_buff; + fwdl_info.rom_size = fw_info->rom_size; + fwdl_info.fw_cat = fw_info->fw_type; + + if(fw_info->fw_src == RTW_FW_SRC_EXTNAL) + fwdl_info.fw_from_hdr = 0; + else + fwdl_info.fw_from_hdr = 1; + + mac_status = mac->ops->hal_fast_init(mac, &init_info->trx_info, &fwdl_info, &init_info->intf_info); + if (mac_status == MACSUCCESS) + hstatus = RTW_HAL_STATUS_SUCCESS; + else { + + hstatus = RTW_HAL_STATUS_HAL_INIT_FAILURE; + PHL_ERR("%s : mac_status %d!\n", __func__, mac_status); + } + + FUNCOUT_WSTS(hstatus); + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_hal_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_status = 0; + + mac_status = mac->ops->hal_deinit(mac); + + if (mac_status == MACSUCCESS) + hstatus = RTW_HAL_STATUS_SUCCESS; + else + PHL_ERR("%s : mac_status %d!\n", __func__, mac_status); + + FUNCOUT_WSTS(hstatus); + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_chk_allq_empty(struct hal_info_t *hal_info, u8 *empty) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + + if (hal_mac_ops->chk_allq_empty(mac, empty)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_WOWLAN +enum rtw_hal_status +rtw_hal_mac_cfg_wow_sleep(struct hal_info_t *hal_info, u8 sleep) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + + if (hal_mac_ops->cfg_wow_sleep(mac,sleep)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_wow_fw_status(struct hal_info_t *hal_info, u8 *status, u8 func_en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + + if (hal_mac_ops->get_wow_fw_status(mac,status, func_en)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_keep_alive(struct hal_info_t *hal_info, u16 macid, u8 en, + struct rtw_keep_alive_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_keep_alive_info info = {0}; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + if (en) { + info.keepalive_en = cfg->keep_alive_en; + info.period = cfg->keep_alive_period; + info.packet_id = cfg->null_pkt_id; + } + + if (hal_mac_ops->cfg_keepalive(mac, (u8)macid, &info)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_disc_dec(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_disc_det_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_disconnect_det_info info = {0}; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + if (en) { + info.disconnect_detect_en = cfg->disc_det_en; + info.disconnect_en = (cfg->disc_wake_en == 1) ? 0 : 1; + info.check_period = cfg->check_period; + info.try_pkt_count = cfg->try_pkt_count; + info.tryok_bcnfail_count_en = cfg->cnt_bcn_lost_en; + info.tryok_bcnfail_count_limit = cfg->cnt_bcn_lost_limit; + } + + if (hal_mac_ops->cfg_disconnect_det(mac, (u8)macid, &info)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_dev2hst_gpio(struct hal_info_t *hal_info, u8 en, struct rtw_wow_gpio_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_dev2hst_gpio_info info = {0}; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + if (en) { + info.dev2hst_gpio_en = cfg->dev2hst_gpio_en; + info.disable_inband = cfg->disable_inband; + info.gpio_output_input = cfg->gpio_output_input; + info.gpio_active = cfg->gpio_active; + info.toggle_pulse = cfg->toggle_pulse; + info.data_pin_wakeup = cfg->data_pin_wakeup; + info.gpio_pulse_nonstop = cfg->gpio_pulse_nonstop; + info.gpio_time_unit = cfg->gpio_time_unit; + info.gpio_num = cfg->dev2hst_gpio; + info.gpio_pulse_dura = cfg->gpio_pulse_dura; + info.gpio_pulse_period = cfg->gpio_pulse_period; + info.gpio_pulse_count = cfg->gpio_pulse_count; + info.customer_id = cfg->customer_id; + info.gpio_pulse_en_a = cfg->gpio_pulse_en_a; + info.gpio_duration_unit_a = cfg->gpio_duration_unit_a; + info.gpio_pulse_nonstop_a = cfg->gpio_pulse_nonstop_a; + info.special_reason_a = cfg->special_reason_a; + info.gpio_duration_a = cfg->gpio_duration_a; + info.gpio_pulse_count_a = cfg->gpio_pulse_count_a; + } + + if (hal_mac_ops->cfg_dev2hst_gpio(mac, &info)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_wow_wake(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_wow_wake_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_wow_wake_info info = {0}; + struct mac_ax_remotectrl_info_parm_ *content = NULL; + struct mac_ax_remotectrl_info_parm_ param; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + if (en) { + info.wow_en = cfg->wow_en; + info.drop_all_pkt = cfg->drop_all_pkt; + info.rx_parse_after_wake = cfg->rx_parse_after_wake; + info.pairwise_sec_algo = cfg->pairwise_sec_algo; + info.group_sec_algo = cfg->group_sec_algo; + /* + info.bip_sec_algo = cfg->bip_sec_algo; + */ + info.pattern_match_en = cfg->pattern_match_en; + info.magic_en = cfg->magic_pkt_en; + info.hw_unicast_en = cfg->hw_unicast_en; + info.fw_unicast_en = cfg->fw_unicast_en; + info.deauth_wakeup = cfg->deauth_wakeup; + info.rekey_wakeup = cfg->rekey_wakeup; + info.eap_wakeup = cfg->eap_wakeup; + info.all_data_wakeup = cfg->all_data_wakeup; + + if (cfg->pairwise_sec_algo) { + param.validcheck = cfg->remote_wake_ctrl_info.valid_check; + param.symbolchecken = cfg->remote_wake_ctrl_info.symbol_check_en; + param.lastkeyid = cfg->remote_wake_ctrl_info.gtk_key_idx; + _os_mem_cpy(hal_to_drvpriv(hal_info), param.ptktxiv, cfg->remote_wake_ctrl_info.ptk_tx_iv, IV_LENGTH); + _os_mem_cpy(hal_to_drvpriv(hal_info), param.rxptkiv, cfg->remote_wake_ctrl_info.ptk_rx_iv, IV_LENGTH); + _os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_0, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx0, IV_LENGTH); + _os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_1, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx1, IV_LENGTH); + _os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_2, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx2, IV_LENGTH); + _os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_3, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx3, IV_LENGTH); + content = ¶m; + } + } + + /* should pass cfg->remote_wake_ctrl_info to halmac */ + if (hal_mac_ops->cfg_wow_wake(mac, (u8)macid, &info, content)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_wake_rsn(struct hal_info_t *hal_info, u8 *wake_rsn, u8 *reset) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + + if (hal_mac_ops->get_wow_wake_rsn(mac, wake_rsn, reset) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_ndp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_ndp_ofld_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_ndp_ofld_info info = {0}; + struct mac_ax_ndp_info_parm_ content[2]; + void* drv_priv = hal_to_drvpriv(hal_info); + u8 idx = 0; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_ndp_ofld_info)); + _os_mem_set(drv_priv, content, 0, sizeof(struct mac_ax_ndp_info_parm_)*2); + + if (en) { + info.ndp_en = cfg->ndp_en; + info.na_id = cfg->ndp_id; + for (idx = 0; idx < 2; idx++) { + content[idx].enable = cfg->ndp_ofld_content[idx].ndp_en; + _os_mem_cpy(drv_priv,content[idx].targetlinkaddress, + cfg->ndp_ofld_content[idx].mac_addr, MAC_ADDRESS_LENGTH); + content[idx].checkremoveip = cfg->ndp_ofld_content[idx].chk_remote_ip; + _os_mem_cpy(drv_priv,content[idx].remoteipv6address, + cfg->ndp_ofld_content[idx].remote_ipv6_addr, IPV6_ADDRESS_LENGTH); + content[idx].numberoftargetip = cfg->ndp_ofld_content[0].num_target_ip; + _os_mem_cpy(drv_priv,&(content[idx].targetip[0][0]), + &(cfg->ndp_ofld_content[idx].target_ipv6_addr[0][0]), IPV6_ADDRESS_LENGTH*2); + } + } + + if (hal_mac_ops->cfg_ndp_ofld(mac, (u8)macid, &info, content)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_arp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, + struct rtw_arp_ofld_info *cfg) +{ + + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_arp_ofld_info info = {0}; + + if (en && cfg == NULL) + return RTW_HAL_STATUS_FAILURE; + + if (en) { + info.arp_en = cfg->arp_en; + info.arp_rsp_id = cfg->arp_rsp_id; + info.arp_action = cfg->arp_action; + } + + if (hal_mac_ops->cfg_arp_ofld(mac, (u8)macid, &info, NULL)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_wow_cam(struct hal_info_t *hal_info, u16 macid, u8 en, + struct rtw_pattern_match_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct rtw_wowcam_upd_info *wowcam_info = NULL; + struct mac_ax_wowcam_upd_info info; + void* drv_priv = hal_to_drvpriv(hal_info); + u8 i = 0; + u8 j = 0; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s (en: %u) ==>\n", __func__, en); + + if (en && cfg == NULL) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input cfg == NULL\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + /* config each wow cam, no matter valid or not */ + for (i = 0; i < MAX_WOW_CAM_NUM; ++i) { + _os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_wowcam_upd_info)); + + if (en) { + wowcam_info = &(cfg->wowcam_info[i]); + + info.idx = wowcam_info->wow_cam_idx; + info.r_w = wowcam_info->rw; + info.valid = wowcam_info->valid; + + if (wowcam_info->valid != 0) { + info.wkfm1 = wowcam_info->wake_mask[0]; + info.wkfm2 = wowcam_info->wake_mask[1]; + info.wkfm3 = wowcam_info->wake_mask[2]; + info.wkfm4 = wowcam_info->wake_mask[3]; + info.crc = wowcam_info->match_crc; + info.negative_pattern_match = wowcam_info->is_negative_pattern_match; + info.skip_mac_hdr = wowcam_info->skip_mac_hdr; + info.uc = wowcam_info->uc; + info.mc = wowcam_info->mc; + info.bc = wowcam_info->bc; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "wow_cam [%u]:\n", info.idx); + + for (j = 0; j < 4; ++j) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- wake_mask[%u] = 0x%08x\n", j, wowcam_info->wake_mask[j]); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rw, crc = (%u, 0x%08x)\n", info.r_w, info.crc); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- Neg_ptn_mtch = %u\n", info.negative_pattern_match); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- SkipMacHdr = %u\n", info.skip_mac_hdr); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- (UC, MC, BC) = (%u, %u, %u)\n", info.uc, info.mc, info.bc); + } else { + continue; + } + } else { + info.idx = i; + info.r_w = 1; + info.valid = 0; + } + + if (hal_mac_ops->cfg_wowcam_upd(mac, &info)) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for cfg wowcam(%u)\n", __func__, info.idx); + return RTW_HAL_STATUS_FAILURE; + } + } + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s() <==\n", __func__); + + return RTW_HAL_STATUS_SUCCESS; +} + +static u32 _hal_mac_recv_aoac_report(struct mac_ax_adapter *mac, struct mac_ax_aoac_report *buf, u8 rx_rdy) +{ + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 mac_status = 0; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s(): request aoac report.\n", __func__); + + mac_status = hal_mac_ops->request_aoac_report(mac, rx_rdy); + + if (mac_status) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== mac_status(%u) from request_aoac_report()\n", __func__, mac_status); + return mac_status; + } + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s(): read aoac report\n", __func__); + + mac_status = hal_mac_ops->read_aoac_report(mac, buf, rx_rdy); + + if (mac_status) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== get mac_status(%u) from read_aoac_report()\n", __func__, mac_status); + return mac_status; + } + + return mac_status; +} + +#define KEY_ID_MASK 0x3 +#define KEY_ID_OFFSET 6 + +enum rtw_hal_status _hal_mac_aoac_rpt_chk(struct rtw_aoac_report *aoac_info) +{ + u8 key_id_from_iv = 0; + u32 rx_iv = *((u32 *)aoac_info->ptk_rx_iv); + + /* Case I. Aoac report is all zero in phase 0 */ + if (rx_iv == 0) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): ptk_rx_iv is Zero, treating this case as error.\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + /* Case II. KEY_IDX does not match with GTK_RX_IV */ + key_id_from_iv = (aoac_info->gtk_rx_iv[aoac_info->key_idx][3] >> KEY_ID_OFFSET) & KEY_ID_MASK; + + if (key_id_from_iv != aoac_info->key_idx) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Key_idx(%u) not match with the one(%u) parsed from GTK_RX_IV[%u]\n", + __func__, aoac_info->key_idx, key_id_from_iv, aoac_info->key_idx); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +/* +AOAC_RPT - PHASE 0: + Halmac will get aoac report through c2h reg. + + (Cuz at this moment, the rx is still blocked by host. + The rx cannot be resume only if those IV be updated by aoac_rpt) + + In PHASE 0, Fw will transfer some necessary info, + such as RX_IV, GTK_KEY_ID, GTK_RX_IV, Rekey_OK and iGTK_ipn. +*/ + +enum rtw_hal_status +_hal_mac_read_aoac_rpt_phase_0(void* drv_priv, struct mac_ax_aoac_report *aoac_rpt_buf, struct rtw_aoac_report *aoac_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + aoac_info->rekey_ok = aoac_rpt_buf->rekey_ok; + aoac_info->key_idx = aoac_rpt_buf->key_idx; + _os_mem_cpy(drv_priv, aoac_info->ptk_rx_iv, aoac_rpt_buf->ptk_rx_iv, IV_LENGTH); + + switch (aoac_info->key_idx) { + case 0: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[0], aoac_rpt_buf->gtk_rx_iv_0, IV_LENGTH); + break; + case 1: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[1], aoac_rpt_buf->gtk_rx_iv_1, IV_LENGTH); + break; + case 2: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[2], aoac_rpt_buf->gtk_rx_iv_2, IV_LENGTH); + break; + case 3: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[3], aoac_rpt_buf->gtk_rx_iv_3, IV_LENGTH); + break; + default: + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Unknown gtk_key_idx(%u)\n", __func__, aoac_info->key_idx); + break; + } + + if (aoac_info->rekey_ok) + _os_mem_cpy(drv_priv, aoac_info->igtk_ipn, aoac_rpt_buf->igtk_ipn, sizeof(aoac_rpt_buf->igtk_ipn)); + + hal_status = _hal_mac_aoac_rpt_chk(aoac_info); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "PHASE 0:\n"); + + debug_dump_data((u8 *)aoac_rpt_buf, sizeof(struct mac_ax_aoac_report), "aoac_report"); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rekey_ok = %u\n", aoac_info->rekey_ok); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- key_idx = %u\n", aoac_info->key_idx); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_rx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_rx_iv)+1), *((u32*)(aoac_info->ptk_rx_iv))); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- gtk_rx_iv[%u] = 0x%08x%08x\n", + aoac_info->key_idx, + *((u32*)(aoac_info->gtk_rx_iv[aoac_info->key_idx])+1), + *((u32*)(aoac_info->gtk_rx_iv[aoac_info->key_idx]))); + + if (aoac_info->rekey_ok) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- igtk_ipn = 0x%08x%08x\n", *((u32*)(aoac_info->igtk_ipn)+1), *((u32*)(aoac_info->igtk_ipn))); + + return hal_status; +} + +/* +AOAC_RPT - PHASE 1: + Halmac will get aoac report through c2h pkt. + + (Cuz at this moment, + the host has resumed the rx, c2h pkt can be used here.) + + In PHASE 1, Fw will transfer all info in aoac report. + Those entries got in phase 0 should remain the same value in phase 1. +*/ + +enum rtw_hal_status +_hal_mac_read_aoac_rpt_phase_1(void* drv_priv, struct mac_ax_aoac_report *aoac_rpt_buf, struct rtw_aoac_report *aoac_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + u8 i = 0; + + aoac_info->rpt_ver = aoac_rpt_buf->rpt_ver; + aoac_info->sec_type = aoac_rpt_buf->sec_type; + aoac_info->pattern_idx = aoac_rpt_buf->pattern_idx; + + _os_mem_cpy(drv_priv, aoac_info->ptk_tx_iv, aoac_rpt_buf->ptk_tx_iv, IV_LENGTH); + + for (i = 0; i < 4; ++i) { + switch (i) { + case 0: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[0], aoac_rpt_buf->gtk_rx_iv_0, IV_LENGTH); + break; + case 1: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[1], aoac_rpt_buf->gtk_rx_iv_1, IV_LENGTH); + break; + case 2: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[2], aoac_rpt_buf->gtk_rx_iv_2, IV_LENGTH); + break; + case 3: + _os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[3], aoac_rpt_buf->gtk_rx_iv_3, IV_LENGTH); + break; + default: + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Unknown gtk_key_idx(%u)\n", __func__, aoac_info->key_idx); + break; + } + } + + _os_mem_cpy(drv_priv, aoac_info->gtk, aoac_rpt_buf->gtk, sizeof(aoac_rpt_buf->gtk)); + _os_mem_cpy(drv_priv, aoac_info->eapol_key_replay_count, aoac_rpt_buf->eapol_key_replay_count, sizeof(aoac_rpt_buf->eapol_key_replay_count)); + _os_mem_cpy(drv_priv, aoac_info->igtk_key_id, aoac_rpt_buf->igtk_key_id, sizeof(aoac_rpt_buf->igtk_key_id)); + _os_mem_cpy(drv_priv, aoac_info->igtk, aoac_rpt_buf->igtk, sizeof(aoac_rpt_buf->igtk)); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "PHASE 1:\n"); + + debug_dump_data((u8 *)aoac_rpt_buf, sizeof(struct mac_ax_aoac_report), "aoac_report"); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rekey_ok = %u\n", aoac_info->rekey_ok); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- key_idx = %u\n", aoac_info->key_idx); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_rx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_rx_iv)+1), *((u32*)(aoac_info->ptk_rx_iv))); + for(i = 0; i < 4; ++i) { + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- gtk_rx_iv[%u] = 0x%08x%08x\n", + i, + *((u32*)(aoac_info->gtk_rx_iv[i])+1), + *((u32*)(aoac_info->gtk_rx_iv[i]))); + } + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_tx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_tx_iv)+1), *((u32*)(aoac_info->ptk_tx_iv))); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rpt_ver = %u\n", aoac_info->rpt_ver); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- sec_type = %u\n", aoac_info->sec_type); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- pattern_idx = %u\n", aoac_info->pattern_idx); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- eapol_key_replay_cnt = 0x%08x%08x\n", *((u32*)(aoac_info->eapol_key_replay_count)+1), *((u32*)(aoac_info->eapol_key_replay_count))); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- igtk_key_id = 0x%08x%08x\n", *((u32*)(aoac_info->igtk_key_id)+1), *((u32*)(aoac_info->igtk_key_id))); + debug_dump_data(aoac_info->gtk, sizeof(aoac_rpt_buf->gtk), "GTK:"); + debug_dump_data(aoac_info->igtk, sizeof(aoac_rpt_buf->igtk), "iGTK:"); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_mac_get_aoac_rpt(struct hal_info_t *hal_info, struct rtw_aoac_report *aoac_info, u8 rx_ready) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; +#ifndef RTW_WKARD_WOW_SKIP_AOAC_RPT + struct mac_ax_adapter *mac = hal_to_mac(hal_info); +#endif + struct mac_ax_aoac_report aoac_rpt_buf; + void* drv_priv = hal_to_drvpriv(hal_info); + u32 mac_status = 0; + + if (aoac_info == NULL) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input info == NULL\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + +#ifdef RTW_WKARD_WOW_SKIP_AOAC_RPT + mac_status = MACPROCERR; +#else + mac_status = _hal_mac_recv_aoac_report(mac, &aoac_rpt_buf, rx_ready); +#endif + + if (mac_status) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for _hal_mac_recv_aoac_report fail with mac_status(%u).\n", + __func__, mac_status); + hal_status = RTW_HAL_STATUS_FAILURE; + } else { + if (rx_ready == 0) + hal_status = _hal_mac_read_aoac_rpt_phase_0(drv_priv, &aoac_rpt_buf, aoac_info); + else + hal_status = _hal_mac_read_aoac_rpt_phase_1(drv_priv, &aoac_rpt_buf, aoac_info); + } + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_mac_cfg_gtk_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, + struct rtw_gtk_ofld_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_gtk_ofld_info info; + struct mac_ax_gtk_info_parm_ param; + void* drv_priv = hal_to_drvpriv(hal_info); + + _os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_gtk_ofld_info)); + _os_mem_set(drv_priv, ¶m, 0, sizeof(struct mac_ax_gtk_info_parm_)); + + if (en && cfg == NULL) { + PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input cfg == NULL\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + if (en) { + info.gtk_en = cfg->gtk_en; + info.tkip_en = cfg->tkip_en; + info.ieee80211w_en = cfg->ieee80211w_en; + info.pairwise_wakeup = cfg->pairwise_wakeup; + info.gtk_rsp_id = cfg->gtk_rsp_id; + + info.algo_akm_suit = cfg->akmtype_byte3; + + if (info.gtk_en) { + _os_mem_cpy(drv_priv, param.kck, cfg->gtk_ofld_content.kck, cfg->gtk_ofld_content.kck_len); + _os_mem_cpy(drv_priv, param.kek, cfg->gtk_ofld_content.kek, cfg->gtk_ofld_content.kek_len); + + if (info.tkip_en) + _os_mem_cpy(drv_priv, param.rxmickey, cfg->gtk_ofld_content.rxmickey, TKIP_MIC_KEY_LENGTH); + } + + if (info.ieee80211w_en) { + info.bip_sec_algo = cfg->bip_sec_algo; + info.pmf_sa_query_id = cfg->sa_query_id; + + _os_mem_cpy(drv_priv, param.igtk_keyid, cfg->gtk_ofld_content.igtk_keyid, cfg->gtk_ofld_content.igtk_len); + _os_mem_cpy(drv_priv, param.ipn, cfg->gtk_ofld_content.ipn, IGTK_PKT_NUM_LENGTH); + _os_mem_cpy(drv_priv, param.igtk, &(cfg->gtk_ofld_content.igtk[0]), cfg->gtk_ofld_content.igtk_len); + + if (cfg->hw_11w_en == 0) + _os_mem_cpy(drv_priv, param.sk, cfg->gtk_ofld_content.psk, cfg->gtk_ofld_content.psk_len); + } + } else { + info.gtk_en = false; + info.ieee80211w_en = false; + } + + if (hal_mac_ops->cfg_gtk_ofld(mac, (u8)macid, &info, ¶m)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; + +} + +enum rtw_hal_status +rtw_hal_mac_cfg_realwow(struct hal_info_t *hal_info, u16 macid, u8 en, + struct rtw_realwow_info *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_realwow_info info = {0}; + struct mac_ax_realwowv2_info_parm_ param = {0}; + void *drv_priv = hal_to_drvpriv(hal_info); + + _os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_realwow_info)); + _os_mem_set(drv_priv, ¶m, 0, sizeof(struct mac_ax_realwowv2_info_parm_)); + + if (en) { + info.realwow_en = cfg->realwow_en; + info.auto_wakeup = cfg->auto_wakeup; + info.keepalive_id = cfg->keepalive_id; + info.wakeup_pattern_id = cfg->wakeup_pattern_id; + info.ack_pattern_id = cfg->ack_pattern_id; + if (info.realwow_en) { + param.interval = cfg->realwow_ofld_content.interval; + param.kapktsize = cfg->realwow_ofld_content.keep_alive_pkt_size; + param.acklostlimit = cfg->realwow_ofld_content.ack_lost_limit; + param.ackpatternsize = cfg->realwow_ofld_content.ack_ptrn_size; + param.wakeuppatternsize = cfg->realwow_ofld_content.wakeup_ptrn_size; + param.wakeupsecnum = cfg->realwow_ofld_content.wakeup_sec_num; + } + } else { + info.realwow_en = false; + } + + if (hal_mac_ops->cfg_realwow(mac, (u8)macid, &info, ¶m)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_set_wowlan(struct hal_info_t *hal, u8 enter) +{ + u32 mac_err = 0; + struct mac_ax_adapter *mac = hal_to_mac(hal); + enum mac_ax_wow_ctrl ctrl = (enter == 1) ? MAC_AX_WOW_ENTER : MAC_AX_WOW_LEAVE; + + mac_err = mac->ops->intf_ops->set_wowlan(mac, ctrl); + if (mac_err != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +static bool _wow_is_txq_empty(struct mac_ax_tx_queue_empty *val) +{ + u8 i = 0; + u8 size = ARRAY_SIZE(val->macid_txq_empty); + + if (!val->others_empty) + return false; + + if (!val->band0_mgnt_empty) + return false; + + if (!val->band1_mgnt_empty) + return false; + + for (i = 0; i < size; i++) { + if (val->macid_txq_empty[i] != 0xFF) + return false; + } + + PHL_INFO("%s : others_empty %d.\n", __func__, val->others_empty); + PHL_INFO("%s : band0_mgnt_empty %d.\n", __func__, val->band0_mgnt_empty); + PHL_INFO("%s : band1_mgnt_empty %d.\n", __func__, val->band1_mgnt_empty); + for (i = 0; i < size; i++) + PHL_INFO("%s : macid_txq_empty[%d] %d.\n", __func__, i, val->macid_txq_empty[i]); + + return true; +} + +#define MAX_WOW_POLLNG_TXQ_EMPTY_TIME 50000 /* us */ +#define MAX_WOW_CHK_TXQ_EMPTY_CNT 2 /* continously check ok should satisfied this value */ +enum rtw_hal_status rtw_hal_mac_wow_chk_txq_empty(struct hal_info_t *hal, u8 *empty) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_tx_queue_empty val = {0}; + u32 start_t = _os_get_cur_time_us(); + u8 chk_cnt = 0; + + while (1) { + + if (phl_get_passing_time_us(start_t) >= MAX_WOW_POLLNG_TXQ_EMPTY_TIME) { + PHL_ERR("%s : reach maximum polling time.\n", __func__); + break; + } + + for (chk_cnt = 0; chk_cnt < MAX_WOW_CHK_TXQ_EMPTY_CNT; chk_cnt++) { + if (mac->ops->is_txq_empty(mac, &val) != MACSUCCESS) + break; + + if (!_wow_is_txq_empty(&val)) { + break; + } else { + *empty = 1; + } + } + + if (*empty) + break; + + _os_delay_us(hal_to_drvpriv(hal), 50); + } + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : polling empty %d with duration %d.\n", + __func__, *empty, phl_get_passing_time_us(start_t)); + + return hstatus; +} + +enum rtw_hal_status rtw_hal_mac_wow_wde_drop(struct hal_info_t *hal, u8 band) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_pkt_drop_info info = {0}; + u32 mac_err = 0; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s with band %d.\n", __func__, band); + + info.sel = MAC_AX_PKT_DROP_SEL_BAND_ONCE; + info.band = band; + + mac_err = mac->ops->pkt_drop(mac, &info); + if (mac_err != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#endif /* CONFIG_WOWLAN */ + +static enum rtw_hal_status +hal_mac_read_efuse(struct mac_ax_adapter *mac, u32 addr, u32 size, + u8 *val, enum mac_ax_efuse_bank bank) +{ + if (mac->ops->read_efuse(mac, addr, size, val, bank) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +static enum rtw_hal_status +hal_mac_write_efuse(struct mac_ax_adapter *mac, u32 addr, u8 val, + enum mac_ax_efuse_bank bank) +{ + if (mac->ops->write_efuse(mac, addr, val, bank) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_enable_cpu(struct hal_info_t *hal_info, u8 reason, u8 dlfw) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->enable_cpu(mac, reason, dlfw) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_disable_cpu(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->disable_cpu(mac) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_romdl(struct hal_info_t *hal_info, u8 *rom_buf, u32 rom_size) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 rom_addr = 0x18900000; + + if (mac->ops->romdl(mac, rom_buf, rom_addr, rom_size) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_fwdl(struct hal_info_t *hal_info, u8 *fw_buf, u32 fw_size) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_err; + + mac_err = mac->ops->fwdl(mac, fw_buf, fw_size); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + hal_mac_print_fw_version(hal_info); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_enable_fw(struct hal_info_t *hal_info, u8 fw_type) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_err; + + mac_err = mac->ops->enable_fw(mac, fw_type); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + hal_mac_print_fw_version(hal_info); + return RTW_HAL_STATUS_SUCCESS; +} + + +/* */ +/** + * rtw_hal_mac_ax_fill_txdesc + * @mac: see struct mac_ax_adapter + * @treq: the xmit request for this tx descriptor + * @wd_buf: the wd buffer to fill + * @wd_len: output, return the total length of filled wd + * + * Note,halmac API for hal and proto type is at hal_api_mac.h + */ +enum rtw_hal_status +rtw_hal_mac_ax_fill_txdesc(void *mac, struct rtw_xmit_req *treq, + u8 *wd_buf, u32 *wd_len) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + + *wd_len = mac_info->ops->txdesc_len( + mac_info, + &treq->mdata); + + hal_status = mac_info->ops->build_txdesc( + mac_info, + &treq->mdata, wd_buf, *wd_len); + + + return hal_status; +} + +/** + * rtw_hal_mac_set_hw_ampdu_cfg + * @hal_info: see struct hal_info_t + * @band: target band this AMPDU going to send + * @max_agg_num: AMPDU maximum aggregation number + * @max_agg_time: AMPDU maximum aggregation time, in unit of 32 us + * + * Note, + * (1) halmac API for hal and proto type is at hal_api_mac.h + */ +enum rtw_hal_status +rtw_hal_mac_set_hw_ampdu_cfg(struct hal_info_t *hal_info, + u8 band, + u16 max_agg_num, u8 max_agg_time) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_ampdu_cfg info; + u32 mac_err; + + _os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info)); + + info.band = band; + info.wdbk_mode = MAC_AX_WDBK_MODE_SINGLE_BK; + info.rty_bk_mode = MAC_AX_RTY_BK_MODE_AGG; + info.max_agg_num = max_agg_num; + info.max_agg_time_32us = max_agg_time; + + mac_err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_AMPDU_CFG, &info); + + if (mac_err != MACSUCCESS) + goto fail; + + return RTW_HAL_STATUS_SUCCESS; +fail: + return RTW_HAL_STATUS_MAC_API_FAILURE; +} + + +/** + * the function to update DMAC control info by halmac api + * @hal_info: see struct hal_info_t + * @dctl_info: structure of dmac control information, define by halmac + * @macid: the macid corresponding to this cmac control info + * + * return RTW_HAL_STATUS_MAC_API_FAILURE if update fail + */ +enum rtw_hal_status rtw_hal_dmc_tbl_cfg(struct hal_info_t *hal_info, + struct mac_ax_dctl_info *dctl_info, + struct mac_ax_dctl_info *dctl_info_mask, + u16 macid) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + + ret = mac->ops->upd_dctl_info(mac, dctl_info, dctl_info_mask, (u8)macid, 1); + + if (0 == ret) { + sts = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_upd_dctl_info fail (0x%08X)\n", + ret); + sts = RTW_HAL_STATUS_MAC_API_FAILURE; + } + + return sts; +} + + + +/** + * the function to update CMAC control info by halmac api + * @hal_info: see struct hal_info_t + * @cctl_info: structure of cmac control information, define by halmac + * @macid: the macid corresponding to this cmac control info + * + * return RTW_HAL_STATUS_MAC_API_FAILURE if update fail + */ +enum rtw_hal_status rtw_hal_cmc_tbl_cfg(struct hal_info_t *hal_info, + struct mac_ax_cctl_info *cctl_info, + struct mac_ax_cctl_info *cctl_info_mask, + u16 macid) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + cctl_info_mask->addr_cam_index = 0; + + ret = mac->ops->upd_cctl_info(mac, cctl_info, cctl_info_mask, (u8)macid, 1); + + if (0 == ret) { + sts = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_upd_cctl_info fail (0x%08X)\n", + ret); + sts = RTW_HAL_STATUS_MAC_API_FAILURE; + } + + return sts; +} + + +/** + * the function to update BA CAM entry by halmac api + * @hal_info: see struct hal_info_t + * @ba_cam: structure of ba cam entry, define by halmac + * + * return RTW_HAL_STATUS_MAC_API_FAILURE if update fail + */ +enum rtw_hal_status rtw_hal_bacam_cfg(struct hal_info_t *hal_info, + struct mac_ax_bacam_info *ba_cam) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + + ret = mac->ops->bacam_info(mac, ba_cam); + + if (0 == ret) { + sts = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_bacam_info fail (0x%08X)\n", + ret); + sts = RTW_HAL_STATUS_MAC_API_FAILURE; + } + + return sts; +} + +/** + * rtw_hal_mac_set_bw() - Update channel and bandwdith related setting + * @hal_info: struct hal_info_t* + * @band_idx: 0x0: band0, 0x1: band1 + * @ch: center channel + * @band: band + * @bw: bandwidth + * + * All channel and bandwidth related MAC setting would be done in + * this function. + * Following setting may be done in this functions: + * a. Enable changing CCK data rate to OFDM 6M function + * to avoid BB/RF abnormal when channel is not 2.4G. + * + * Return RTW_HAL_STATUS_SUCCESS when operation success. + */ +enum rtw_hal_status rtw_hal_mac_set_bw(struct hal_info_t *hal_info, + u8 band_idx, u8 pri_ch, u8 central_ch_seg0, + u8 central_ch_seg1, enum band_type band, + enum channel_width bw) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_cfg_bw mac_bw = {0}; + u32 ret = 0; + + mac_bw.cbw = bw; + mac_bw.band = band_idx; + mac_bw.pri_ch = pri_ch; + mac_bw.central_ch = central_ch_seg0; + + ret = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_BW_CFG, &mac_bw); + return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE); +} + +/** + * rtw_hal_mac_ax_init_bf_role + * @bf_role: 0 = BFEE, 1 = BFER + * @band: 0 = BAND0, 1 = BAND1 + */ +enum rtw_hal_status +rtw_hal_mac_ax_init_bf_role(struct rtw_hal_com_t *hal_com, u8 bf_role, u8 band) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac_info = hal_to_mac(hal_info); + + if (bf_role == HAL_BF_ROLE_BFEE) { + hal_status = mac_info->ops->init_snd_mee( + mac_info, band); + } else { + hal_status = mac_info->ops->init_snd_mer( + mac_info, band); + }; + return hal_status; +} + + +/** + * rtw_hal_mac_ax_disable_bfee + * @band: 0 = BAND0, 1 = BAND1 + */ +enum rtw_hal_status +rtw_hal_mac_ax_deinit_bfee(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s : Warning BFee is going to deinit\n", __func__); + + hal_status = mac_info->ops->deinit_mee(mac_info, band); + + return hal_status; +} + + +/** + * rtw_hal_mac_ax_bfee_para_reg + * Set BFee capability with STA info by method : Control Register + * input: + * @sta: (struct rtw_phl_stainfo_t *) + */ +enum rtw_hal_status +rtw_hal_mac_ax_bfee_para_reg(void *mac, struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_reg_csi_para csi_para; + + _os_mem_set(hal_com->drv_priv, &csi_para, 0, sizeof(csi_para)); + + csi_para.band = sta->wrole->hw_band; + csi_para.portsel = (sta->wrole->hw_port == 0) ? 0 : 1; + csi_para.nc = (sta->wrole->proto_role_cap.max_nc > sta->asoc_cap.num_snd_dim) ? + sta->asoc_cap.num_snd_dim : + sta->wrole->proto_role_cap.max_nc; + csi_para.nr = (sta->wrole->proto_role_cap.bfme_sts > + sta->asoc_cap.num_snd_dim) ? + sta->asoc_cap.num_snd_dim : + sta->wrole->proto_role_cap.bfme_sts; + /** + * For HE/VHT, Ng = 0 can provide the most detail information. + * Ng do not care bfer cap. + **/ + csi_para.ng = 0; + /** + * for HE/VHT, Cb = 1 {6,4}/{9,7} can provide the most detail information + * Cb do not care bfer cap, only care bfee self capabiltiy. + **/ + if (sta->wmode & WLAN_MD_11AX) + csi_para.cb = sta->wrole->proto_role_cap.cb_sz_su_fb; + else if (sta->wmode & WLAN_MD_11AC) + csi_para.cb = sta->wrole->proto_role_cap.ht_vht_cb; + else + csi_para.cb = 0; + + csi_para.cs = 1; /* Carrier Sense */ + if (sta->asoc_cap.ht_ldpc && + sta->asoc_cap.vht_ldpc && + sta->asoc_cap.he_ldpc) + csi_para.ldpc_en = 1; + + if (sta->asoc_cap.stbc_ht_rx && + sta->asoc_cap.stbc_vht_rx && + sta->asoc_cap.stbc_he_rx) + csi_para.stbc_en = 1; + + csi_para.bf_en = 0; + + hal_status = mac_info->ops->set_csi_para_reg(mac_info, &csi_para); + + return hal_status; +} + +/** + * rtw_hal_mac_ax_bfee_para_cctl + * Set BFee capability with STA info by method : CMAC Control Table + * input: + * @sta: (struct rtw_phl_stainfo_t *) + */ +enum rtw_hal_status +rtw_hal_mac_ax_bfee_para_cctl(void *mac, struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_cctl_csi_para csi_para; + + _os_mem_set(hal_com->drv_priv, &csi_para, 0, sizeof(csi_para)); + + csi_para.macid = (u8)sta->macid; + csi_para.band = sta->wrole->hw_band; + csi_para.nc = (sta->wrole->proto_role_cap.max_nc > sta->asoc_cap.num_snd_dim) ? + sta->asoc_cap.num_snd_dim : + sta->wrole->proto_role_cap.max_nc; + csi_para.nr = (sta->wrole->proto_role_cap.bfme_sts > + sta->asoc_cap.num_snd_dim) ? + sta->asoc_cap.num_snd_dim : + sta->wrole->proto_role_cap.bfme_sts; + /** + * For HE/VHT, Ng = 0 can provide the most detail information. + * Ng do not care bfer cap. + **/ + csi_para.ng = 0; + /** + * for HE/VHT, Cb = 1 {6,4}/{9,7} can provide the most detail information + * Cb do not care bfer cap. + **/ + if (sta->wmode & WLAN_MD_11AX) + csi_para.cb = sta->wrole->proto_role_cap.cb_sz_su_fb; + else if (sta->wmode & WLAN_MD_11AC) + csi_para.cb = sta->wrole->proto_role_cap.ht_vht_cb; + else + csi_para.cb = 0; + csi_para.cs = 1; + csi_para.bf_en = 0; + + if (sta->asoc_cap.stbc_ht_rx && + sta->asoc_cap.stbc_vht_rx && + sta->asoc_cap.stbc_he_rx) + csi_para.stbc_en = 1; + + if (sta->asoc_cap.ht_ldpc && + sta->asoc_cap.vht_ldpc && + sta->asoc_cap.he_ldpc) + csi_para.ldpc_en = 1; + csi_para.rate = MAC_AX_OFDM54; + csi_para.gi_ltf = MAC_AX_SGI_4XHE08; + csi_para.gid_sel = 1; + csi_para.bw = MAC_AX_BW_20M; + + hal_status = mac_info->ops->set_csi_para_cctl(mac_info, &csi_para); + return hal_status; +} + +enum rtw_hal_status +rtw_hal_mac_ax_bfee_set_csi_rrsc(void *mac, u8 band, u32 rrsc) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + + hal_status = mac_info->ops->csi_rrsc(mac_info, band, rrsc); + + return hal_status; +} + +/** + * rtw_hal_mac_ax_bfee_forced_csi_rate + * set bf report frame rate + * @mac:(struct mac_ax_adapter *) + * @ht_rate: + * @vht_rate: + * @he_rate: + */ + +enum rtw_hal_status +rtw_hal_mac_ax_bfee_forced_csi_rate(void *mac, struct rtw_phl_stainfo_t *sta, + u8 ht_rate, u8 vht_rate, u8 he_rate) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + + hal_status = mac_info->ops->csi_force_rate(mac_info, + sta->wrole->hw_band, ht_rate, vht_rate, he_rate); + + return hal_status; +} + +/** + * rtw_hal_mac_ax_set_bf_entry + * set HW BF entry for sounding and TxBF + * input : + * @band: BF Entry is band0 or band1; + * @macid: BF Entry's macid + * @bfee_idx: SU/MU HW Entry Index + * @txbf_idx: Tx BF CSI Entry Index + * @buffer_idx: CSI Buffer idx used by TxBF entry + */ +enum rtw_hal_status +rtw_hal_mac_ax_set_bf_entry(void *mac, u8 band, + u8 macid, u8 bfee_idx, u16 txbf_idx, u16 buffer_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + /* 1. CSI Buffer Idx */ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "set_csi_buffer_index : band 0x%x macid 0x%x txbf_idx 0x%x buffer_idx 0x%x\n", + band, macid, txbf_idx, buffer_idx); + hal_status = mac_info->ops->set_csi_buffer_index(mac_info, band, macid, + txbf_idx, buffer_idx); + + + /*TODO: this api might revised in the future */ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "set_snd_sts_index: band 0x%x macid 0x%x bf_idx 0x%x\n", + band, macid, bfee_idx); + hal_status = mac_info->ops->set_snd_sts_index( + mac_info, band, macid, bfee_idx); + + + return hal_status; +} + + +/** + * rtw_hal_mac_ax_get_snd_sts + * Get HW BF entry sounding status + * input : + * @band: BF Entry is band0 or band1; + * @bfee_idx: SU/MU HW Entry Index + * return + * @hal_status: enum rtw_hal_status + * RTW_HAL_STATUS_SUCCESS = Sounding Success + * RTW_HAL_STATUS_FAILURE = Sounding Fail + */ +enum rtw_hal_status +rtw_hal_mac_ax_get_snd_sts(void *mac, u8 band, u8 bfee_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + u32 sts = 0; + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "get_snd_sts_index: band 0x%x bf_idx 0x%x\n", band, bfee_idx); + /*TODO: This API shall modify to return sounding status instead of CR value*/ + /*MAC Define : #define B_AX_MER_SU_BFMEE0_SND_STS BIT(9)*/ + sts = mac_info->ops->get_snd_sts_index(mac_info, band, bfee_idx); + if (sts & B_AX_MER_SU_BFMEE0_SND_STS) + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +/** + * rtw_hal_mac_ax_hw_snd_control + * @band: 0 = BAND0, 1 = BAND1 + * @hw_snd_ctrl: 0 = HW_SND_PAUSE 1 = HW_SND_RELEASE + */ +enum rtw_hal_status +rtw_hal_mac_ax_hw_snd_control( + void *mac, + u8 band, + u8 hw_snd_ctrl) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "mac_hw_snd_pause_release: band 0x%x hw_snd_ctrl 0x%x\n", + band, hw_snd_ctrl); + + hal_status = mac_info->ops->hw_snd_pause_release( + mac_info, + band, + hw_snd_ctrl); + + return hal_status; +} + +/* Tx Frame Exchange Related : MU */ +/** + * rtw_hal_mac_ax_mu_sta_upd + * @mac: (struct mac_ax_adapter *) + * @macid: sta macid for configuration + * @bfmu_idx: 0~5, MU STA Index + * @prot_type: RTS/CTS type for the group : enum rtw_hal_protection_type + * @resp_type: Ack Policy for the group : enum rtw_hal_ack_resp_type + * @grp_bitmap: group bitmap for STA, + **/ +enum rtw_hal_status +rtw_hal_mac_ax_mu_sta_upd(void *mac, u8 macid, u8 bfmu_idx, + enum rtw_hal_protection_type prot_type, + enum rtw_hal_ack_resp_type resp_type, u8 mugrp_bm) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_ax_mu_sta_upd sta_info; + u8 i = 0; + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_mac_ax_mu_sta_upd \n"); + _os_mem_set(hal_com->drv_priv, &sta_info, 0, sizeof(sta_info)); + + sta_info.macid = macid; + sta_info.mu_idx = bfmu_idx; + for (i = 0; i < 5; i++) { + if (mugrp_bm & BIT(i)) { + sta_info.prot_rsp_type[i].u.feld_type.protect = + prot_type & 0xF; + sta_info.prot_rsp_type[i].u.feld_type.rsp = + resp_type & 0xF; + } else { + sta_info.prot_rsp_type[i].u.feld_type.protect = 0; + sta_info.prot_rsp_type[i].u.feld_type.rsp = 0; + } + } + sta_info.mugrp_bitmap = mugrp_bm & 0x1F; + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.macid = 0x%x \n", sta_info.macid); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.mu_idx = 0x%x \n", sta_info.mu_idx); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.mugrp_bitmap = 0x%x \n", sta_info.mugrp_bitmap); + + hal_status = mac_info->ops->mu_sta_upd(mac_info, &sta_info); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== rtw_hal_mac_ax_mu_sta_upd \n"); + return hal_status; +} + +/** + * rtw_hal_mac_ax_mu_decision_para + * @mac: (struct mac_ax_adapter *) + * @mu_thold: MU MIMO pkt Threshold + * @bypass_thold: by pass mu_thold + * @bypass_tp: by pass MU TP > SU TP check. + **/ +enum rtw_hal_status +rtw_hal_mac_ax_mu_decision_para(void *mac, u32 mu_thold, + bool bypass_thold, bool bypass_tp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_ax_mudecision_para mu_d_para; + + _os_mem_set(hal_com->drv_priv, &mu_d_para, 0, sizeof(mu_d_para)); + + mu_d_para.mu_thold = mu_thold; + mu_d_para.bypass_thold = bypass_thold ? 1 : 0; + mu_d_para.bypass_tp = bypass_tp ? 1 : 0; + + hal_status = mac_info->ops->upd_mudecision_para(mac_info, &mu_d_para); + + return hal_status; +} + +/** + * rtw_hal_mac_ax_set_mu_fix_mode + * @mac: (struct mac_ax_adapter *) + * @gid: GID for STA X + STAY + * @prot_type: RTS/CTS type for the group : enum rtw_hal_protection_type + * @resp_type: Ack Policy for the group : enum rtw_hal_ack_resp_type + * @fix_mu: true = Fix FW decision = MU + * @he: true = Fix TX HE MU, false = Fix TX VHT MU; + * @fix_resp: fix frame exchange ack policy + * @fix_prot: fix frame exchange protection type + **/ +enum rtw_hal_status +rtw_hal_mac_ax_set_mu_fix_mode( + void *mac, u8 gid, enum rtw_hal_protection_type prot_type, + enum rtw_hal_ack_resp_type resp_type, + bool fix_mu, bool he, bool fix_resp, bool fix_prot) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_ax_fixmode_para fix_info; + PHL_INFO("===>rtw_hal_mac_ax_set_mu_fix_mode\n"); + + _os_mem_set(hal_com->drv_priv, &fix_info, 0, sizeof(fix_info)); + + fix_info.force_sumuru_en = fix_mu ? 1:0 ; + fix_info.forcemu = fix_mu ? 1:0 ; + + if (fix_mu) { + if (!he){ + fix_info.fix_fe_vhtmu_en = fix_prot ? 1 : 0; + fix_info.fix_frame_seq_vhtmu = fix_resp ? 1 : 0; + fix_info.prot_type_vhtmu = fix_prot ? prot_type : 5;/*default hw setting*/ + fix_info.resp_type_vhtmu = fix_resp ? resp_type : 4;/*default hw setting*/ + PHL_INFO("fix_info.prot_type_vhtmu = 0x%x\n", fix_info.prot_type_vhtmu); + PHL_INFO("fix_info.resp_type_vhtmu = 0x%x\n", fix_info.resp_type_vhtmu); + + } else { + fix_info.fix_fe_hemu_en = fix_prot ? 1 : 0;; + fix_info.fix_frame_seq_hemu = fix_resp ? 1 : 0; + fix_info.prot_type_hemu = fix_prot ? prot_type : 5;/*default hw setting*/ + fix_info.resp_type_hemu = fix_resp ? resp_type : 4;/*default hw setting*/ + PHL_INFO("fix_info.prot_type_hemu = 0x%x\n", fix_info.prot_type_hemu); + PHL_INFO("fix_info.resp_type_hemu = 0x%x\n", fix_info.resp_type_hemu); + } + + fix_info.mugrpid = gid; + PHL_INFO("fix_info.mugrpid = 0x%x\n", fix_info.mugrpid); + } + + hal_status = mac_info->ops->set_fw_fixmode(mac_info, &fix_info); + PHL_INFO("<===rtw_hal_mac_ax_set_mu_fix_mode\n"); + return hal_status; +} + + +void +_hal_mac_fill_mu_sc_tbl_row(u32 *mac_score, void *hal_score) +{ + struct hal_mu_score_tbl_score *h_score = + (struct hal_mu_score_tbl_score *)hal_score; + + *mac_score = (u32)h_score->score[0] | + ((u32)h_score->score[1] << 8) | ((u32)h_score->valid << 10) | + ((u32)h_score->macid << 11); + +} +/** + * rtw_hal_mac_ax_set_mu_table_whole +* @mac: (struct mac_ax_adapter *) + *@hal_score_tbl: struct hal_mu_score_tbl * + */ +enum rtw_hal_status +rtw_hal_mac_ax_set_mu_table_whole(void *mac, void *hal_score_tbl) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac; + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)mac_info->drv_adapter; + struct mac_mu_table mu_table; + struct hal_mu_score_tbl *score_tbl = (struct hal_mu_score_tbl *)hal_score_tbl; + _os_mem_set(hal_com->drv_priv, &mu_table, 0, sizeof(mu_table)); + + /*TODO: halmac api shall refine!!!*/ + mu_table.mu_score_tbl_ctrl = (score_tbl->mu_ctrl.mu_sc_thr) | + (score_tbl->mu_ctrl.mu_opt << 2); + + /*TODO: if next IC has more than 6 MU STAs!!! */ + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_0, &score_tbl->mu_score[0]); + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_1, &score_tbl->mu_score[1]); + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_2, &score_tbl->mu_score[2]); + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_3, &score_tbl->mu_score[3]); + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_4, &score_tbl->mu_score[4]); + _hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_5, &score_tbl->mu_score[5]); + + hal_status = mac_info->ops->set_mu_table(mac_info, &mu_table); + + return hal_status; +} + + +enum rtw_hal_status +rtw_hal_mac_parse_c2h(void *hal, u8 *buf, u32 buf_len, void *c2h) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + + hal_status = mac->ops->process_c2h(mac, buf, buf_len, (u8 *)c2h); + + return hal_status; +} + +/** + * Required information in (hal_handle_rx_buffer_XXXXX case RX_DESC_PKT_TYPE_PPDU_STATUS), + * it cannot be used by core/phl/other hal module + **/ +void +_hal_mac_ax_ppdu_sts_to_hal_ppdu_sts( + struct mac_ax_ppdu_rpt *mac_ppdu, void *hal_ppdu_sts) +{ + struct hal_ppdu_sts *hal_ppdu = + (struct hal_ppdu_sts *)hal_ppdu_sts; + u8 i = 0; + u32 j = 0; + + hal_ppdu->rx_cnt_ptr = mac_ppdu->rx_cnt_ptr; + hal_ppdu->phy_st_ptr = mac_ppdu->phy_st_ptr; + hal_ppdu->plcp_ptr = mac_ppdu->plcp_ptr; + hal_ppdu->plcp_size = mac_ppdu->plcp_size; + hal_ppdu->phy_st_size = mac_ppdu->phy_st_size; + hal_ppdu->rx_cnt_size = mac_ppdu->rx_cnt_size; + hal_ppdu->usr_num = mac_ppdu->usr_num; + for(i = 0; i < mac_ppdu->usr_num; i++) { + if(1 == mac_ppdu->usr[i].vld) { + hal_ppdu->usr[i].vld = 1; + hal_ppdu->usr[i].macid = mac_ppdu->usr[i].macid; + hal_ppdu->usr[i].has_data = mac_ppdu->usr[i].has_data; + hal_ppdu->usr[i].has_ctrl = mac_ppdu->usr[i].has_ctrl; + hal_ppdu->usr[i].has_mgnt = mac_ppdu->usr[i].has_mgnt; + hal_ppdu->usr[i].has_bcn = mac_ppdu->usr[i].has_bcn; + } + } + /* process / decode rx cnt report */ + /* TODO: Halmac api shall provid decoder */ + if ((0 != hal_ppdu->rx_cnt_size) && (NULL != hal_ppdu->rx_cnt_ptr)) { + for(j = 0; (j < (hal_ppdu->rx_cnt_size/2)) && + (j < HAL_RXCNT_MAX); j++) { + hal_ppdu->rx_cnt.ppdu_cnt[j] = + ((u16)*(hal_ppdu->rx_cnt_ptr + 2 * j)); + } + } +} + +/** + * if any information is required for other core/phl module, + * copy to rx meta data or hal_info from halmac ax ppdu status. + **/ +void +_hal_mac_ax_ppdu_sts_to_hal_info(struct hal_info_t *hal_info, + struct mac_ax_ppdu_rpt *mac_ppdu, void *rx_mdata) +{ + /* struct rtw_r_meta_data *mdata = + (struct rtw_r_meta_data *)rx_mdata; */ + return; +} +/** + * rtw_hal_mac_ax_parse_ppdu_sts + * @hal:(struct hal_info_t *) + * @mac_valid:if mac information invalid (from rx desc) + * @buf: pointer of ppdu status, point to header of mac_info + * @buf_l:ppdu status payload size + * @ppdu_sts: (struct hal_ppdu_sts *) for return value to hal + * @rx_mdata: (struct rtw_r_meta_data *) for saving ppdu status + */ +enum rtw_hal_status +rtw_hal_mac_ax_parse_ppdu_sts(void *hal, u8 mac_valid, u8 *buf, u16 buf_l, + void *ppdu_sts, void *rx_mdata) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_ppdu_rpt ppdu_rpt = {0}; + + PHL_DBG("%s\n", __FUNCTION__); + + hal_status = mac->ops->parse_ppdu(hal_info->mac, buf, buf_l, + mac_valid, &ppdu_rpt); + + if (hal_status == RTW_HAL_STATUS_SUCCESS) { + _hal_mac_ax_ppdu_sts_to_hal_ppdu_sts(&ppdu_rpt, ppdu_sts); + _hal_mac_ax_ppdu_sts_to_hal_info(hal_info ,&ppdu_rpt, + rx_mdata); + } + + return hal_status; +} + + +/** + * the function to enable HW header conversion function + * @hal_info: see struct hal_info_t + * @en_hdr_conv: true to enable, false to disable + * + * return RTW_HAL_STATUS_MAC_API_FAILURE if update fail + */ +enum rtw_hal_status rtw_hal_hdr_conv_cfg(struct hal_info_t *hal_info, + u8 en_hdr_conv) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 ret = 0; + + ret = mac->ops->hdr_conv(mac, en_hdr_conv); + + if (MACSUCCESS == ret) { + sts = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "hdr_conv fail (0x%08X)\n", + ret); + sts = RTW_HAL_STATUS_MAC_API_FAILURE; + } + + return sts; +} + + +#ifdef RTW_PHL_BCN //fill hal mac ops +enum rtw_hal_status +hal_mac_ax_config_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct rtw_bcn_info_cmn *bcn_cmn = bcn_entry->bcn_cmn; + struct rtw_bcn_info_hw *bcn_hw = &bcn_entry->bcn_hw; + enum mac_ax_port_cfg_type ptype; + struct mac_ax_port_cfg_para ppara = {0}; + + ppara.band = bcn_hw->band; + ppara.port = bcn_hw->port; + ppara.mbssid_idx = bcn_hw->mbssid; + + ptype = MAC_AX_PCFG_BCN_INTV; + ppara.val = bcn_cmn->bcn_interval; + if (mac->ops->port_cfg(mac, ptype, &ppara) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + ptype = MAC_AX_PCFG_HIQ_DTIM; + ppara.val = bcn_cmn->bcn_dtim; + if (mac->ops->port_cfg(mac, ptype, &ppara) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +hal_mac_ax_send_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry) +{ + + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct rtw_bcn_info_cmn *bcn_cmn = bcn_entry->bcn_cmn; + struct rtw_bcn_info_hw *bcn_hw = &bcn_entry->bcn_hw; + struct mac_ax_bcn_info info = {0}; + + if(!mac->ops->send_bcn_h2c) + return RTW_HAL_STATUS_FAILURE; + + info.pld_buf = bcn_cmn->bcn_buf; + info.pld_len = (u16)bcn_cmn->bcn_length; + + info.band = bcn_hw->band; + info.port = bcn_hw->port; + info.mbssid = bcn_hw->mbssid; + info.grp_ie_ofst = (u8)bcn_cmn->ie_offset_tim; + info.macid = bcn_hw->mac_id; + + if(bcn_cmn->bcn_offload & BIT(BCN_HW_TIM)) + info.grp_ie_ofst |= BIT(7); + + if(bcn_cmn->bcn_offload & BIT(BCN_HW_SEQ)){ + info.ssn_sel = 1; + info.ssn_mode = 1; + } + else { + info.ssn_sel = 0; + info.ssn_mode = 0; + } + + info.rate_sel = (u16)bcn_cmn->bcn_rate; + + mac->ops->send_bcn_h2c(mac, &info); + + return RTW_HAL_STATUS_SUCCESS; + +} +#endif //RTW_PHL_BCN + +enum rtw_hal_status +rtw_hal_mac_ppdu_stat_cfg(struct hal_info_t *hal_info, + u8 band_idx, + bool ppdu_stat_en, + u8 appen_info, + u8 filter) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_phy_rpt_cfg cfg = {0}; + + cfg.en = ppdu_stat_en; + cfg.type = MAC_AX_PPDU_STATUS; + /*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/ + + cfg.u.ppdu.band = band_idx; + if (ppdu_stat_en) { + if (appen_info&HAL_PPDU_MAC_INFO) + cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_MAC_INFO; + if (appen_info&HAL_PPDU_PLCP) + cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_PLCP; + if (appen_info&HAL_PPDU_RX_CNT) + cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_RX_CNT; + + if (filter&HAL_PPDU_HAS_A1M) + cfg.u.ppdu.bmp_filter |= MAC_AX_PPDU_HAS_A1M; + if (filter&HAL_PPDU_HAS_CRC_OK) + cfg.u.ppdu.bmp_filter |= MAC_AX_PPDU_HAS_CRC_OK; + + cfg.u.ppdu.dup2fw_en = false; + cfg.u.ppdu.dup2fw_len = 0; + } + + if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) { + PHL_ERR("%s fault\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_config_hw_mgnt_sec(struct hal_info_t *hal_info, u8 en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *hal_mac_ops = mac->ops; + + hal_mac_ops->sta_hw_security_support(mac, SEC_UC_MGNT_ENC, en); + hal_mac_ops->sta_hw_security_support(mac, SEC_BMC_MGNT_ENC, en); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_get_append_fcs(struct hal_info_t *hal_info, u8 *val) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + + if (ops->get_hw_value(mac, MAC_AX_HW_GET_APP_FCS, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + else + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_get_acpt_icv_err(struct hal_info_t *hal_info, u8 *val) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + + if (ops->get_hw_value(mac, MAC_AX_HW_GET_RX_ICVERR, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + else + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_hal_status +rtw_hal_mac_chan_info_cfg(struct hal_info_t *hal_info, + bool chinfo_en, u8 macid, + u8 mode, u8 filter, u8 sg_size) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_phy_rpt_cfg cfg = {0}; + + cfg.en = chinfo_en; + cfg.type = MAC_AX_CH_INFO; + /*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/ + cfg.u.chif.macid = macid; + + if (chinfo_en) { + /*ToDo - mode*/ + cfg.u.chif.trigger = MAC_AX_CH_INFO_MACID; + /*ToDo - filter*/ + cfg.u.chif.bmp_filter = MAC_AX_CH_INFO_DATA_FRM; + cfg.u.chif.dis_to = 0; + /*ToDo - sg_size*/ + cfg.u.chif.seg_size = MAC_AX_CH_IFNO_SEG_512; + } + if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) { + PHL_ERR("%s fault\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +void rtw_hal_mac_dbg_status_dump(struct hal_info_t *hal, struct hal_mac_dbg_dump_cfg *cfg) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_dbgpkg pkg = {0}; + struct mac_ax_dbgpkg_en pkg_en = {0}; + + pkg.ss_dbg_0 = cfg->ss_dbg_0; + pkg.ss_dbg_1 = cfg->ss_dbg_1; + + pkg_en.ss_dbg = cfg->ss_dbg; + pkg_en.dle_dbg = cfg->dle_dbg; + pkg_en.dmac_dbg = cfg->dmac_dbg; + pkg_en.cmac_dbg = cfg->cmac_dbg; + pkg_en.mac_dbg_port = cfg->mac_dbg_port; + pkg_en.plersvd_dbg = cfg->plersvd_dbg; + pkg_en.tx_flow_dbg = cfg->tx_flow_dbg; + + PHL_INFO("%s: ss_dbg_0 %d, ss_dbg_1 %d, ss_dbg %d\n", __func__, pkg.ss_dbg_0, pkg.ss_dbg_1, pkg_en.ss_dbg); + PHL_INFO("%s: dle_dbg %d, dmac_dbg %d, cmac_dbg %d\n", __func__, pkg_en.dle_dbg, pkg_en.dmac_dbg, pkg_en.cmac_dbg); + PHL_INFO("%s: mac_dbg_port %d, plersvd_dbg %d, tx_flow_dbg %d\n", __func__, pkg_en.mac_dbg_port, pkg_en.plersvd_dbg, pkg_en.tx_flow_dbg); + + mac->ops->dbg_status_dump(mac, &pkg, &pkg_en); +} + +#ifdef CONFIG_PHL_DFS +enum rtw_hal_status +rtw_hal_mac_dfs_rpt_cfg(struct hal_info_t *hal_info, + bool rpt_en, u8 rpt_num, u8 rpt_to) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_phy_rpt_cfg cfg = {0}; + + cfg.en = rpt_en; + cfg.type = MAC_AX_DFS; + /*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/ + + if (rpt_en) { + cfg.u.dfs.num_th = rpt_num; + cfg.u.dfs.en_timeout = rpt_to; + } + + if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) { + PHL_ERR("%s fault\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_parse_dfs(struct hal_info_t *hal_info, + u8 *buf, u32 buf_len, struct mac_ax_dfs_rpt *dfs_rpt) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + + if (mac->ops->parse_dfs(mac, buf, buf_len, dfs_rpt) != MACSUCCESS) { + PHL_ERR("%s fault\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} +#endif /*CONFIG_PHL_DFS*/ + +enum rtw_hal_status +_hal_mac_get_pkt_ofld(struct hal_info_t *hal_info, u8 *id) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u8 *pkt_buf = NULL; + u16 pkt_len; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + if (mac->ops->pkt_ofld_packet(mac, &pkt_buf, &pkt_len, id) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + debug_dump_data((u8 *)pkt_buf, pkt_len, "pkt ofld"); + + _os_mem_free(hal_com->drv_priv, pkt_buf, pkt_len); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +_hal_mac_chk_pkt_ofld(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + void *d = hal_to_drvpriv(hal_info); + u16 loop_cnt = 0; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + do + { + if (mac->ops->check_fwofld_done(mac, 1) == MACSUCCESS) + break; + + _os_sleep_ms(d, POLLING_HALMAC_TIME); + + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if ( loop_cnt < POLLING_HALMAC_CNT) { + PHL_PRINT("%s, check count = %d.\n", __func__, loop_cnt); + return RTW_HAL_STATUS_SUCCESS; + } else { + PHL_ERR("%s, polling timeout!!!\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } +} + +enum rtw_hal_status +_hal_mac_add_pkt_ofld(struct hal_info_t *hal_info, u8 *pkt, u16 len, u8 *id) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 status; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + PHL_PRINT("%s: len %d.\n", __func__, len); + + status = mac->ops->add_pkt_ofld(mac, pkt, len, id); + if (status != MACSUCCESS) { + PHL_ERR("%s fault, status = %d.\n", __func__, status); + return RTW_HAL_STATUS_FAILURE; + } + PHL_PRINT("%s: id %d.\n", __func__, *id); + + status = _hal_mac_chk_pkt_ofld(hal_info); + return status; +} + +enum rtw_hal_status +_hal_mac_del_pkt_ofld(struct hal_info_t *hal_info, u8 *id) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 status; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + PHL_PRINT("%s: id %d.\n", __func__, *id); + + status = mac->ops->del_pkt_ofld(mac, *id); + if (status != MACSUCCESS) { + PHL_ERR("%s fault, status = %d.\n", __func__, status); + return RTW_HAL_STATUS_FAILURE; + } + + status = _hal_mac_chk_pkt_ofld(hal_info); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +_hal_mac_read_pkt_ofld(struct hal_info_t *hal_info, u8 *id) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 status; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + PHL_PRINT("%s: id %d.\n", __func__, *id); + + status = mac->ops->read_pkt_ofld(mac, *id); + if (status != MACSUCCESS) { + PHL_ERR("%s fault, status = %d.\n", __func__, status); + return RTW_HAL_STATUS_FAILURE; + } + + status = _hal_mac_chk_pkt_ofld(hal_info); + if (status != MACSUCCESS) { + return RTW_HAL_STATUS_FAILURE; + } + + status = _hal_mac_get_pkt_ofld(hal_info, id); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_pkt_ofld(struct hal_info_t *hal, u8 *id, u8 op, + u8 *pkt, u16 *len) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + switch(op) { + case PKT_OFLD_ADD: + status = _hal_mac_add_pkt_ofld(hal, pkt, *len, id); + break; + + case PKT_OFLD_DEL: + status = _hal_mac_del_pkt_ofld(hal, id); + break; + + case PKT_OFLD_READ: + status = _hal_mac_read_pkt_ofld(hal, id); + break; + + default: + PHL_ERR("%s op(%d) not define.\n", __func__, op); + break; + } + + return status; +} + +enum rtw_hal_status rtw_hal_mac_pkt_update_ids(struct hal_info_t *hal, + struct pkt_ofld_entry *entry) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal->mac; + struct mac_ax_general_pkt_ids mac_ids = {0}; + u32 status; + + mac_ids.macid = (u8)entry->macid; + mac_ids.probersp = entry->pkt_info[PKT_TYPE_PROBE_RSP].id; + mac_ids.pspoll = entry->pkt_info[PKT_TYPE_PS_POLL].id; + mac_ids.nulldata = entry->pkt_info[PKT_TYPE_NULL_DATA].id; + mac_ids.qosnull = entry->pkt_info[PKT_TYPE_QOS_NULL].id; + mac_ids.cts2self = entry->pkt_info[PKT_TYPE_CTS2SELF].id; + + PHL_PRINT("macid %d, probersp %d, pspoll %d, nulldata %d, qosnull %d, cts2self %d.\n", + mac_ids.macid, + mac_ids.probersp, + mac_ids.pspoll, + mac_ids.nulldata, + mac_ids.qosnull, + mac_ids.cts2self); + + status = mac->ops->general_pkt_ids(mac, &mac_ids); + if (status != MACSUCCESS) { + PHL_ERR("%s fault, status = %d.\n", __func__, status); + return RTW_HAL_STATUS_FAILURE; + } + return status; +} +enum rtw_hal_status +rtw_hal_mac_reset_pkt_ofld_state(struct hal_info_t *hal_info) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + + if (mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + if (mac->ops->reset_fwofld_state(mac, 1) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + else + return RTW_HAL_STATUS_SUCCESS; + +} + +/* comment temporary and review it later */ +#if 0 +u4Byte hal_mac_ax_dbg_h2cpkt_lb(RT_HAL_MAC_INFO *hm_info, u32 size) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret = 0; + + u8 *h2cbuf = NULL; + FunctionIn(COMP_HAL_MAC_API); + + //ret = hm_info->halmac_ax_ops->fwcmd_lb(hm_info->halmac_ax_apter, + // 100, 0); + + PlatformAllocateMemory(adapter, (PVOID *)&h2cbuf, size); + PlatformZeroMemory(h2cbuf,size); + + for (u4Byte tmpc = 0; tmpc < size - 32; tmpc++) { + h2cbuf[32 + tmpc] = (u8)tmpc & 0xFF; + } + + hal_mac_ax_send_h2c_pkt(adapter, h2cbuf, size); + + PlatformFreeMemory(h2cbuf, size); + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + + +u4Byte hal_mac_ax_update_table_dl_swru(RT_HAL_MAC_INFO *hm_info, + struct ofdma_dl_group *dl_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_dlru_grptbl( + hm_info->halmac_ax_apter, + &dl_group->dl_grp_table); + + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + +u4Byte hal_mac_ax_update_table_dl_swfix(RT_HAL_MAC_INFO *hm_info, + struct ofdma_dl_group *dl_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_dlru_fixtbl( + hm_info->halmac_ax_apter, + &dl_group->fixed_mode_group); + + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + + +u4Byte hal_mac_ax_update_table_ul_rufix(RT_HAL_MAC_INFO *hm_info, + struct ofdma_ul_group *ul_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_ulru_fixtbl( + hm_info->halmac_ax_apter, + &ul_group->fixed_mode_group); + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + +u4Byte hal_mac_ax_update_table_ul_ru_table(RT_HAL_MAC_INFO *hm_info, + struct ofdma_ul_group *ul_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_ulru_grptbl( + hm_info->halmac_ax_apter, + &ul_group->ul_grp_table); + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + + +u4Byte hal_mac_ax_update_table_ul_drvfix(RT_HAL_MAC_INFO *hm_info, + struct ofdma_ul_group *ul_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_ul_fixinfo( + hm_info->halmac_ax_apter, + &ul_group->drv_fixed_info); + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + + +u4Byte hal_mac_ax_issue_bsrp(RT_HAL_MAC_INFO *hm_info, + struct ofdma_ul_group *ul_group) +{ + PADAPTER adapter = hm_info->adapter; + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + + ret = hm_info->halmac_ax_ops->upd_ul_fixinfo( + hm_info->halmac_ax_apter, + &ul_group->drv_fixed_info + ); + + FunctionOut(COMP_HAL_MAC_API); + return ret; +} + + +u4Byte hal_mac_ax_update_ru_sta(RT_HAL_MAC_INFO *hm_info, + u8 *ru_sta_info) +{ + /* upd_rusta_info */ + struct mac_ax_bb_stainfo *bb_stainfo = (struct mac_ax_bb_stainfo *)ru_sta_info; + + hm_info->halmac_ax_ops->upd_rusta_info( + hm_info->halmac_ax_apter, + bb_stainfo + ); + return 0; +} + +u4Byte hal_mac_ax_update_ba_info_table(RT_HAL_MAC_INFO *hm_info, + u8 ba_info) +{ + /* upd_ba_infotbl */ + struct mac_ax_ba_infotbl *ba_info_tbl = (struct mac_ax_ba_infotbl *)ba_info; + + hm_info->halmac_ax_ops->upd_ba_infotbl( + hm_info->halmac_ax_apter, + ba_info_tbl + ); + + return 0; +} + +u4Byte hal_mac_ax_Test_H2C(RT_HAL_MAC_INFO *hm_info, + u32 length, u8 Burst) +{ + + u32 ret =0; + FunctionIn(COMP_HAL_MAC_API); + ret = hm_info->halmac_ax_ops->fwcmd_lb( + hm_info->halmac_ax_apter, + length, + Burst + ); + + + FunctionOut(COMP_HAL_MAC_API); + + return ret; +} + +u4Byte hal_mac_ax_compare_h2c_c2h(RT_HAL_MAC_INFO *hm_info, + u8 *buf, u32 len) +{ + u32 ret=0; + FunctionIn(COMP_HAL_MAC_API); + ret = hm_info->halmac_ax_ops->process_c2h( + hm_info->halmac_ax_apter, + buf, + len + ); + FunctionOut(COMP_HAL_MAC_API); + return ret; +} +#endif +//==================================================================== + +/* + * halmac wrapper API for hal and proto type is at hal_api_mac.h + * Efuse part. + */ +enum rtw_hal_status +rtw_hal_mac_get_log_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val, + bool is_limited) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + if(is_limited == true) { + if(mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE, val) != MACSUCCESS){ + PHL_ERR("%s: Get limited logical efuse size fail!\n", + __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + } + else { + if(mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE, val) != MACSUCCESS){ + PHL_ERR("%s: Get logical efuse size fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + } + PHL_INFO("%s: Logical efuse size = %d!\n", __FUNCTION__, *val); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_read_log_efuse_map(struct rtw_hal_com_t *hal_com, u8 *map, + bool is_limited) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->dump_log_efuse(mac, + MAC_AX_EFUSE_PARSER_MAP, + #ifdef RTW_WKARD_EFUSE_OPERATION + MAC_AX_EFUSE_R_DRV, + #else + MAC_AX_EFUSE_R_AUTO, + #endif + map, + is_limited + ) != MACSUCCESS) { + PHL_INFO("%s: Dump logical efuse fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s: Dump logical efuse ok!\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +/* + * HALMAC PG EFUSE API put version length at the tail of map/mask buffer + */ + +enum rtw_hal_status +rtw_hal_mac_write_log_efuse_map(struct rtw_hal_com_t *hal_com, + u8 *map, + u32 map_size, + u8 *mask, + u32 mask_size, + u8 *map_version, + u8 *mask_version, + u8 version_length, + u8 part, + bool is_limited) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_pg_efuse_info info; + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + u8 *tmp_map = NULL; + u8 *tmp_mask = NULL; + + tmp_map = _os_mem_alloc(hal_com->drv_priv, (map_size + version_length)); + if(tmp_map == NULL) { + PHL_WARN("%s: Allocate pg map buffer fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_RESOURCE; + goto err_mem_tmp_map; + } + + tmp_mask = _os_mem_alloc(hal_com->drv_priv, (mask_size + version_length)); + if(tmp_mask == NULL) { + PHL_WARN("%s: Allocate pg mask buffer fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_RESOURCE; + goto err_mem_tmp_mask; + } + + /* Copy efuse map and map version to tmp_map buffer */ + _os_mem_cpy(hal_com->drv_priv, tmp_map, map, map_size); + _os_mem_cpy(hal_com->drv_priv, tmp_map+map_size, map_version, + version_length); + /* Copy efuse mask and mask version to tmp_mask buffer */ + _os_mem_cpy(hal_com->drv_priv, tmp_mask, mask, mask_size); + _os_mem_cpy(hal_com->drv_priv, tmp_mask+mask_size, mask_version, + version_length); +#if 0 /* For debug usage */ + debug_dump_data(map, (u16)map_size, "logical map:"); + debug_dump_data(map_version, version_length, "logical map version:"); + debug_dump_data(mask, (u16)mask_size, "mask:"); + debug_dump_data(mask_version, version_length, "mask version:"); + debug_dump_data(tmp_map, (u16)(map_size + version_length), "tmp_map:"); + debug_dump_data(tmp_mask, (u16)(mask_size + version_length), "tmp_mask:"); +#endif + info.efuse_map = tmp_map; + info.efuse_map_size = map_size; + info.efuse_mask = tmp_mask; + info.efuse_mask_size= mask_size; + + if (mac->ops->pg_efuse_by_map(mac, + &info, + MAC_AX_EFUSE_R_DRV, + part, + is_limited) != MACSUCCESS) { + PHL_INFO("%s: PG Fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + } + else { + PHL_INFO("%s: PG ok!\n", __FUNCTION__); + status = RTW_HAL_STATUS_SUCCESS; + } + _os_mem_free(hal_com->drv_priv, tmp_map, (map_size + version_length)); + _os_mem_free(hal_com->drv_priv, tmp_mask, (mask_size + version_length)); + + return status; + +err_mem_tmp_mask: + _os_mem_free(hal_com->drv_priv, tmp_map, (map_size + version_length)); + +err_mem_tmp_map: + + return status; +} + + +enum rtw_hal_status +rtw_hal_mac_read_hidden_rpt(struct rtw_hal_com_t *hal_com) +{ + + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_defeature_value rpt; + u32 err; + + err = mac->ops->read_hidden_rpt(mac, &rpt); + if (err != MACSUCCESS) { + PHL_TRACE(COMP_PHL_TRIG, _PHL_INFO_, "err=0x%x\n", err); + return RTW_HAL_STATUS_FAILURE; + } + + if (rpt.tx_spatial_stream != 7 && rpt.tx_spatial_stream > 0) { + hal_com->phy_hw_cap[0].tx_num = rpt.tx_spatial_stream; + hal_com->phy_hw_cap[1].tx_num = rpt.tx_spatial_stream; + hal_com->rfpath_tx_num = rpt.tx_spatial_stream; + } + if (rpt.rx_spatial_stream != 7 && rpt.rx_spatial_stream > 0) { + hal_com->phy_hw_cap[0].rx_num = rpt.rx_spatial_stream; + hal_com->phy_hw_cap[1].rx_num = rpt.rx_spatial_stream; + hal_com->rfpath_rx_num = rpt.rx_spatial_stream; + } + if (rpt.hw_special_type > EFUSE_HW_STYPE_NONE && + rpt.hw_special_type < EFUSE_HW_STYPE_GENERAL) + hal_com->dev_hw_cap.hw_stype_cap = rpt.hw_special_type; + + if (rpt.wl_func_support > EFUSE_WL_FUNC_NONE && + rpt.wl_func_support < EFUSE_WL_FUNC_GENERAL) + hal_com->dev_hw_cap.wl_func_cap = rpt.wl_func_support; + + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden tx=%d hidden rx=%d\n", + rpt.tx_spatial_stream, rpt.rx_spatial_stream); + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden bw=%d\n", rpt.bandwidth); + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden protocol = %d\n", + rpt.protocol_80211); + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden nic=%d\n", rpt.NIC_router); + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden hw special type=%d\n", + rpt.hw_special_type); + PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden wl func=%d\n", + rpt.wl_func_support); + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_mac_check_efuse_autoload(struct rtw_hal_com_t *hal_com, u8 *autoload) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->check_efuse_autoload(mac, autoload) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + if(*autoload == true) + PHL_INFO("%s: efuse auto load SUCCESS!\n", __FUNCTION__); + else + PHL_INFO("%s: efuse auto load FAIL!\n", __FUNCTION__); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_avl(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_efuse_avl_size(mac, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_EFUSE_SIZE, val) != MACSUCCESS){ + PHL_ERR("%s: Get efuse size fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + PHL_INFO("%s: Efuse size = %d!\n", __FUNCTION__, *val); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_mask_size(struct rtw_hal_com_t *hal_com, u32 *val, + bool is_limited) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if(is_limited == true) { + if(mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + } + else { + if(mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_EFUSE_MASK_SIZE, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s: efuse mask size = %d\n", __FUNCTION__, *val); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + PHL_INFO("%s\n", __FUNCTION__); + + if (mac->ops->get_efuse_info(mac, efuse_map, info_type, value, size, + &map_valid) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_read_phy_efuse(struct rtw_hal_com_t *hal_com, + u32 addr, u32 size, u8 *value) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + PHL_INFO("%s\n", __FUNCTION__); + + if (mac->ops->read_efuse(mac, addr, size, value, + MAC_AX_EFUSE_BANK_WIFI) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_read_bt_phy_efuse(struct rtw_hal_com_t *hal_com, + u32 addr, u32 size, u8 *value) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + PHL_INFO("%s\n", __FUNCTION__); + + if (mac->ops->read_efuse(mac, addr, size, value, + MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_mac_write_msk_pwr_reg( + struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 mask, u32 val) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + u32 result = 0; + + result = ops->write_msk_pwr_reg(mac, band, offset, mask, val); + + if (result != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, + "Write power register failure, status = %d\n", result); + + return result; +} + +u32 rtw_hal_mac_set_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 val){ + + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + u32 result = 0; + + result = ops->write_pwr_reg(mac, band, offset, val); + + if (result != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set power register failure, status = %d\n", result); + + return result; +} + +u32 rtw_hal_mac_get_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 *val){ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + u32 result = 0; + + result = ops->read_pwr_reg(mac, band, offset, val); + + if (result != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Get power register failure, status = %d\n", result); + + return result; +} + +enum rtw_hal_status +rtw_hal_mac_get_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 *value){ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = ops->read_xcap_reg(mac, sc_xo, value); + + if (ret != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Get xacp failure, status = %d\n", ret); + + return ret; +} + +enum rtw_hal_status +rtw_hal_mac_set_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 value){ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = ops->write_xcap_reg(mac, sc_xo, value); + + if (ret != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set xacp failure, status = %d\n", ret); + + return ret; +} + +enum rtw_hal_status +rtw_hal_mac_get_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8* val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + /* Because mac si function is not support mac ops*/ + /* we call mac si function temporarily until mac team feedback.*/ + if (mac_read_xtal_si(mac, offset, val) != MACSUCCESS) { + PHL_INFO("Get xsi failure, status = %s\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_set_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + /* Because mac si function is not support mac ops*/ + /* we call mac si function temporarily until mac team feedback.*/ + if (mac_write_xtal_si(mac, offset, val, 0xff) != MACSUCCESS) { + PHL_INFO("Set xsi failure, status = %s\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_mac_fw_dbg_dump(struct hal_info_t *hal_info, u8 is_low_power) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u8 *buffer = NULL; + u16 bufSize = FW_PLE_SIZE; + struct mac_ax_fwdbg_en en; + u32 mac_err = 0; + + en.status_dbg = 1; + en.ps_dbg = 1; + en.rsv_ple_dbg = 0; + + mac_err = mac->ops->fw_dbg_dump(mac, &buffer, &en); + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + if (en.rsv_ple_dbg && buffer) { + /*fw buffer is 2048, but Windows DbgPrint only 512 Bytes, so we split buffer to 4 segments*/ + if (buffer != NULL) { + PHL_PRINT("=======================\n"); + PHL_PRINT("Start to dump fw rsvd ple:\n\n"); + _hal_fw_dbg_dump(hal_info, buffer, bufSize); + PHL_PRINT("\n=======================\n"); + } + } + if (buffer != NULL) + _os_mem_free(hal_info->hal_com->drv_priv, buffer, bufSize); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_req_pwr_state(struct hal_info_t *hal_info, u8 pwr_state) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if(mac->ops->ps_pwr_state(mac, MAC_AX_PWR_STATE_ACT_REQ, pwr_state) + == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_chk_pwr_state(struct hal_info_t *hal_info, u8 pwr_state, u32 *mac_sts) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + *mac_sts = mac->ops->ps_pwr_state(mac, MAC_AX_PWR_STATE_ACT_CHK, pwr_state); + if(*mac_sts == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_lps_cfg(struct hal_info_t *hal_info, + struct rtw_hal_lps_info *lps_info) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_ps_mode ax_ps_mode; + struct mac_ax_lps_info ax_lps_info; + + if (lps_info->lps_en) { + ax_ps_mode = MAC_AX_PS_MODE_LEGACY; + } else { + ax_ps_mode = MAC_AX_PS_MODE_ACTIVE; + } + + ax_lps_info.listen_bcn_mode = lps_info->listen_bcn_mode; + ax_lps_info.awake_interval = lps_info->awake_interval; + ax_lps_info.smart_ps_mode = lps_info->smart_ps_mode; + + if (mac->ops->cfg_lps(mac, (u8)lps_info->macid, ax_ps_mode, + &ax_lps_info) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_lps_chk_leave(struct hal_info_t *hal_info, u16 macid, u32 *mac_sts) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + *mac_sts = mac->ops->chk_leave_lps(mac, (u8)macid); + if(*mac_sts == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_lps_chk_access(struct hal_info_t *hal_info, u32 offset) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if(mac->ops->io_chk_access(mac, offset) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_mac_get_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx, u8 type_idx, u32 *ret_value){ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + struct mac_ax_rx_cnt rx_cnt; + u16 rx_cnt_buff[MAC_AX_RX_PPDU_MAX]; + u32 rx_cnt_total=0; + u16 ppdu_idx; + + rx_cnt.type = type_idx; + rx_cnt.op = MAC_AX_RXCNT_R; + rx_cnt.buf = rx_cnt_buff; + rx_cnt.band = cur_phy_idx; + + ret = ops->rx_cnt(mac, &rx_cnt); + + for(ppdu_idx=0;ppdu_idxops; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + struct mac_ax_rx_cnt rx_cnt; + u16 rx_cnt_buff[MAC_AX_RX_PPDU_MAX]; + + rx_cnt.type = MAC_AX_RX_IDX; + rx_cnt.op = MAC_AX_RXCNT_RST_ALL; + rx_cnt.buf = rx_cnt_buff; + rx_cnt.band = cur_phy_idx; + + ret = ops->rx_cnt(mac, &rx_cnt); + + if (ret != MACSUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "mac reset rx cnt fail, status=%d\n",ret); + } + + return ret; +} + +enum rtw_hal_status +rtw_hal_mac_tx_idle_poll(struct rtw_hal_com_t *hal_com, u8 band_idx) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_tx_idle_poll_cfg cfg = {0}; + u32 err = 0; + + + cfg.sel = MAC_AX_TX_IDLE_POLL_SEL_BAND; + cfg.band = band_idx; + err = mac->ops->tx_idle_poll(mac, &cfg); + if (err != MACSUCCESS) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, + "Polling tx idle failure(%d)!\n", err); + return RTW_HAL_STATUS_TIMEOUT; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_sch_txen_cfg { + RTW_TXEN_BE0 = 1 << 0, + RTW_TXEN_BK0 = 1 << 1, + RTW_TXEN_VI0 = 1 << 2, + RTW_TXEN_VO0 = 1 << 3, + RTW_TXEN_BE1 = 1 << 4, + RTW_TXEN_BK1 = 1 << 5, + RTW_TXEN_VI1 = 1 << 6, + RTW_TXEN_VO1 = 1 << 7, + RTW_TXEN_MG0 = 1 << 8, + RTW_TXEN_MG1 = 1 << 9, + RTW_TXEN_MG2 = 1 << 10, + RTW_TXEN_HI = 1 << 11, + RTW_TXEN_BCN = 1 << 12, + RTW_TXEN_UL = 1 << 13, + RTW_TXEN_TWT0 = 1 << 14, + RTW_TXEN_TWT1 = 1 << 15, + RTW_TXEN_DRV_MASK = 0x19FF, + RTW_TXEN_ALL = 0xFFFF, +}; + +enum rtw_hal_status +rtw_hal_mac_set_sch_tx_en(struct rtw_hal_com_t *hal_com, u8 band_idx, + u16 tx_en, u16 tx_en_mask) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_sch_tx_en_cfg cfg; + enum rtw_hal_status ret; + u32 result = 0; + + ret = RTW_HAL_STATUS_SUCCESS; + cfg.band = band_idx; + + cfg.tx_en.be0 = ((tx_en & RTW_TXEN_BE0) ? 1 : 0); + cfg.tx_en.bk0 = ((tx_en & RTW_TXEN_BK0) ? 1 : 0); + cfg.tx_en.vi0 = ((tx_en & RTW_TXEN_VI0) ? 1 : 0); + cfg.tx_en.vo0 = ((tx_en & RTW_TXEN_VO0) ? 1 : 0); + cfg.tx_en.be1 = ((tx_en & RTW_TXEN_BE1) ? 1 : 0); + cfg.tx_en.bk1 = ((tx_en & RTW_TXEN_BK1) ? 1 : 0); + cfg.tx_en.vi1 = ((tx_en & RTW_TXEN_VI1) ? 1 : 0); + cfg.tx_en.vo1 = ((tx_en & RTW_TXEN_VO1) ? 1 : 0); + cfg.tx_en.mg0 = ((tx_en & RTW_TXEN_MG0) ? 1 : 0); + cfg.tx_en.mg1 = ((tx_en & RTW_TXEN_MG1) ? 1 : 0); + cfg.tx_en.mg2 = ((tx_en & RTW_TXEN_MG2) ? 1 : 0); + cfg.tx_en.hi = ((tx_en & RTW_TXEN_HI) ? 1 : 0); + cfg.tx_en.bcn = ((tx_en & RTW_TXEN_BCN) ? 1 : 0); + cfg.tx_en.ul = ((tx_en & RTW_TXEN_UL) ? 1 : 0); + cfg.tx_en.twt0 = ((tx_en & RTW_TXEN_TWT0) ? 1 : 0); + cfg.tx_en.twt1 = ((tx_en & RTW_TXEN_TWT1) ? 1 : 0); + + cfg.tx_en_mask.be0 = ((tx_en_mask & RTW_TXEN_BE0) ? 1 : 0); + cfg.tx_en_mask.bk0 = ((tx_en_mask & RTW_TXEN_BK0) ? 1 : 0); + cfg.tx_en_mask.vi0 = ((tx_en_mask & RTW_TXEN_VI0) ? 1 : 0); + cfg.tx_en_mask.vo0 = ((tx_en_mask & RTW_TXEN_VO0) ? 1 : 0); + cfg.tx_en_mask.be1 = ((tx_en_mask & RTW_TXEN_BE1) ? 1 : 0); + cfg.tx_en_mask.bk1 = ((tx_en_mask & RTW_TXEN_BK1) ? 1 : 0); + cfg.tx_en_mask.vi1 = ((tx_en_mask & RTW_TXEN_VI1) ? 1 : 0); + cfg.tx_en_mask.vo1 = ((tx_en_mask & RTW_TXEN_VO1) ? 1 : 0); + cfg.tx_en_mask.mg0 = ((tx_en_mask & RTW_TXEN_MG0) ? 1 : 0); + cfg.tx_en_mask.mg1 = ((tx_en_mask & RTW_TXEN_MG1) ? 1 : 0); + cfg.tx_en_mask.mg2 = ((tx_en_mask & RTW_TXEN_MG2) ? 1 : 0); + cfg.tx_en_mask.hi = ((tx_en_mask & RTW_TXEN_HI) ? 1 : 0); + cfg.tx_en_mask.bcn = ((tx_en_mask & RTW_TXEN_BCN) ? 1 : 0); + cfg.tx_en_mask.ul = ((tx_en_mask & RTW_TXEN_UL) ? 1 : 0); + cfg.tx_en_mask.twt0 = ((tx_en_mask & RTW_TXEN_TWT0) ? 1 : 0); + cfg.tx_en_mask.twt1 = ((tx_en_mask & RTW_TXEN_TWT1) ? 1 : 0); + + result = ops->set_hw_value(mac, MAC_AX_HW_SET_SCH_TXEN_CFG, &cfg); + + if (result != MACSUCCESS) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set Tx pause failure, status = %d\n", result); + ret = RTW_HAL_STATUS_FAILURE; + } + + return ret; +} + +enum rtw_hal_status +rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com, + u8 band_idx, bool tx_pause, enum tx_pause_rson rson) +{ + u16 *tx_off; + enum tx_pause_rson i; + u16 tx_cfg = 0; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + + tx_off = &hal_com->band[band_idx].tx_pause[rson]; + if (tx_pause == true) { + switch (rson) { + case PAUSE_RSON_NOR_SCAN: + *tx_off = (u16)~RTW_TXEN_MG0; + break; + case PAUSE_RSON_RFK: + case PAUSE_RSON_PSD: + case PAUSE_RSON_DFS: + case PAUSE_RSON_DBCC: + case PAUSE_RSON_RESET: + *tx_off = (u16)RTW_TXEN_ALL; + break; + default: + PHL_ERR("Unknow pause reason:%d\n", rson); + goto _error; + } + } else { + *tx_off = 0; + } + + tx_off = hal_com->band[band_idx].tx_pause; + for (i = 0; (i < PAUSE_RSON_MAX) && (tx_cfg != RTW_TXEN_ALL); i++) + if (tx_off[i]) + tx_cfg |= tx_off[i]; + /* tx_cfg is white list, but tx_pause of struct rtw_hw_band is black list */ + tx_cfg = ~tx_cfg; + PHL_INFO("TX %sPause - Reason(%d) for band-%u, final tx_cfg(0x%04x)\n", + tx_pause?"":"Un-", rson, band_idx, tx_cfg); + + hstatus = rtw_hal_mac_set_sch_tx_en(hal_com, band_idx, + tx_cfg, RTW_TXEN_ALL); + if (hstatus != RTW_HAL_STATUS_SUCCESS) + goto _error; + + if ((rson == PAUSE_RSON_RFK) && tx_pause) { + hstatus = rtw_hal_mac_tx_idle_poll(hal_com, band_idx); + if (hstatus != RTW_HAL_STATUS_SUCCESS) + goto _error; + } + +_error: + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_set_macid_pause(struct rtw_hal_com_t *hal_com, + u16 macid, bool pause) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_macid_pause_cfg cfg = {0}; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + + cfg.macid = (u8)macid; + cfg.pause = pause; + + PHL_INFO("%s macid:%d(%s) \n", __func__, macid, pause ? "pause":"unpause"); + /*TODO - MAC_AX_HW_SET_MULTI_ID_PAUSE*/ + if (ops->set_hw_value(mac, MAC_AX_HW_SET_ID_PAUSE, &cfg) != MACSUCCESS) { + PHL_ERR("%s failed\n", __func__); + hstatus = RTW_HAL_STATUS_FAILURE; + } + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_set_macid_grp_pause(struct rtw_hal_com_t *hal_com, + u32 *macid_arr, u8 macid_arr_sz, bool pause) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *ops = mac->ops; + struct mac_ax_macid_pause_grp cfg = {0}; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + u8 pause_grp_sz = 0, mac_grp_sz = 0, arr_idx = 0, bit_idx = 0; + u32 mac_ret = MACSUCCESS; + + /* size check */ + mac_grp_sz = sizeof(cfg.pause_grp) / sizeof(cfg.pause_grp[0]); + pause_grp_sz = MIN(mac_grp_sz, macid_arr_sz); + + for (arr_idx = 0; arr_idx < pause_grp_sz; arr_idx++) { + for (bit_idx = 0; bit_idx < 32; bit_idx++) { + if (macid_arr[arr_idx] & BIT(bit_idx)) { + cfg.mask_grp[arr_idx] |= BIT(bit_idx); + if (pause) + cfg.pause_grp[arr_idx] |= BIT(bit_idx); + else + cfg.pause_grp[arr_idx] &= ~BIT(bit_idx); + } + } + } + + PHL_INFO("%s cfg pause_grp:0x%x,0x%x,0x%x,0x%x, mask_grp:0x%x,0x%x,0x%x,0x%x(%s)\n", __func__, + cfg.pause_grp[0], cfg.pause_grp[1], cfg.pause_grp[2], cfg.pause_grp[3], + cfg.mask_grp[0], cfg.mask_grp[1], cfg.mask_grp[2], cfg.mask_grp[3], + pause ? "pause":"unpause"); + + mac_ret = ops->set_hw_value(mac, MAC_AX_HW_SET_MULTI_ID_PAUSE, &cfg); + if (mac_ret != MACSUCCESS) { + PHL_ERR("%s failed(mac ret:%d)\n", __func__, mac_ret); + hstatus = RTW_HAL_STATUS_FAILURE; + } + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_mac_fw_log_cfg(struct rtw_hal_com_t *hal_com, + struct rtw_hal_fw_log_cfg *fl_cfg) +{ + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_fw_log log_cfg = {0}; + u32 status; + + if(mac == NULL) + return RTW_HAL_STATUS_MAC_INIT_FAILURE; + + log_cfg.level = fl_cfg->level; + log_cfg.output = fl_cfg->output; + log_cfg.comp = fl_cfg->comp; + log_cfg.comp_ext = fl_cfg->comp_ext; + + PHL_PRINT("%s: level %d, output 0x%08x, comp 0x%08x, comp ext 0x%08x.\n", + __func__, + log_cfg.level, + log_cfg.output, + log_cfg.comp, + log_cfg.comp_ext); + + if(log_cfg.output == MAC_AX_FL_LV_UART) + { + mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_TX_GPIO5); + mac->ops->sel_uart_tx_pin(mac, MAC_AX_UART_TX_GPIO5); + mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_RX_GPIO6); + mac->ops->sel_uart_rx_pin(mac, MAC_AX_UART_RX_GPIO6); + } + + status = mac->ops->fw_log_cfg(mac, &log_cfg); + if (status != MACSUCCESS) { + PHL_ERR("%s fault, status = %d.\n", __func__, status); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +u32 +rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 rpt = 0; + + rpt = mac->ops->lamode_trigger(mac, trig); + + return rpt; +} + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel, + u32 *addr_start, u32 *addr_end) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_la_buf_param param; + + param.la_buf_sel = buf_sel; + + mac->ops->lamode_buf_cfg(mac, ¶m); + + *addr_start = param.start_addr; + *addr_end = param.end_addr; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en, + u8 restart_en, u8 timeout_en, u8 timeout_val, + u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_la_cfg cfg; + + cfg.la_func_en = func_en; + cfg.la_restart_en = restart_en; + cfg.la_timeout_en = timeout_en; + cfg.la_timeout_val = timeout_val; + cfg.la_data_loss_imr = data_loss_imr; + cfg.la_tgr_tu_sel = la_tgr_tu_sel; + cfg.la_tgr_time_val = tgr_time_val; + + mac->ops->lamode_cfg(mac, &cfg); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state, + u16 *la_finish_addr, bool *la_round_up, + bool *la_loss_data) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_la_status info; + + info = mac->ops->get_lamode_st(mac); + + *la_state = info.la_sw_fsmst; + *la_finish_addr = info.la_buf_wptr; + *la_round_up = info.la_buf_rndup_ind; + *la_loss_data = info.la_data_loss; + + return RTW_HAL_STATUS_SUCCESS; +} + +static inline void _hal_set_dft_rxfltr(struct mac_ax_rx_fltr_ctrl_t *ctrl, + struct mac_ax_rx_fltr_ctrl_t *mask) +{ + /* filter packets by address */ + ctrl->sniffer_mode = 0; + mask->sniffer_mode = 1; + + /* check unicast */ + ctrl->acpt_a1_match_pkt = 1; + mask->acpt_a1_match_pkt = 1; + ctrl->uc_pkt_chk_cam_match = 1; + mask->uc_pkt_chk_cam_match = 1; + + /* check broadcast */ + ctrl->acpt_bc_pkt = 1; + mask->acpt_bc_pkt = 1; + ctrl->bc_pkt_chk_cam_match = 1; + mask->bc_pkt_chk_cam_match = 1; + + /* check multicast */ + ctrl->acpt_mc_pkt = 1; + mask->acpt_mc_pkt = 1; + /* black list filter */ + ctrl->mc_pkt_white_lst_mode = 0; + mask->mc_pkt_white_lst_mode = 1; + + /* check beacon */ + ctrl->bcn_chk_en = 1; + mask->bcn_chk_en = 1; + ctrl->bcn_chk_rule = 0; /* 2: A2&A3 match */ + mask->bcn_chk_rule = 0x3; + + /* misc */ + ctrl->acpt_pwr_mngt_pkt = 1; + mask->acpt_pwr_mngt_pkt = 1; + + ctrl->acpt_ftm_req_pkt = 1; + mask->acpt_ftm_req_pkt = 1; +} +/** + * rtw_hal_mac_set_rxfltr_by_mode - Set rx filter option by scenario + * @hal_com: pointer of struct rtw_hal_com_t + * @band: 0x0: band0, 0x1: band1 + * @mode: scenario mode + * + * Set RX filter setting by scenario. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_by_mode(struct rtw_hal_com_t *hal_com, + u8 band, enum rtw_rx_fltr_mode mode) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_rx_fltr_ctrl_t ctrl = {0}; + struct mac_ax_rx_fltr_ctrl_t mask = {0}; + u32 err; + + + switch (mode) { + case RX_FLTR_MODE_RESTORE: + break; + case RX_FLTR_MODE_SNIFFER: + ctrl.sniffer_mode = 1; + mask.sniffer_mode = 1; + break; + case RX_FLTR_MODE_SCAN: + ctrl.acpt_a1_match_pkt = 1; + mask.acpt_a1_match_pkt = 1; + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.acpt_mc_pkt = 1; + mask.acpt_mc_pkt = 1; + ctrl.uc_pkt_chk_cam_match = 0; + mask.uc_pkt_chk_cam_match = 1; + ctrl.bc_pkt_chk_cam_match = 0; + mask.bc_pkt_chk_cam_match = 1; + + /* Do NOT check B_AX_A_BCN_CHK_RULE + * when receiving beacon and probe_response + */ + ctrl.bcn_chk_en = 0; + mask.bcn_chk_en = 1; + break; + case RX_FLTR_MODE_STA_NORMAL: + #if 1 + _hal_set_dft_rxfltr(&ctrl, &mask); + + #else + /* filter packets by address */ + ctrl.sniffer_mode = 0; + mask.sniffer_mode = 1; + /* check unicast */ + ctrl.acpt_a1_match_pkt = 1; + mask.acpt_a1_match_pkt = 1; + ctrl.uc_pkt_chk_cam_match = 1; + mask.uc_pkt_chk_cam_match = 1; + /* check broadcast */ + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.bc_pkt_chk_cam_match = 1; + mask.bc_pkt_chk_cam_match = 1; + + if ((hal_com->chip_id == CHIP_WIFI6_8852A) + && (hal_com->cv == CAV)) { + /* don't check address cam for multicast, accept all */ + ctrl.acpt_mc_pkt = 0; + mask.acpt_mc_pkt = 1; + } else { + /* check multicast */ + ctrl.acpt_mc_pkt = 1; + mask.acpt_mc_pkt = 1; + /* black list filter */ + ctrl.mc_pkt_white_lst_mode = 0; + mask.mc_pkt_white_lst_mode = 1; + } + /* check beacon */ + ctrl.bcn_chk_en = 1; + mask.bcn_chk_en = 1; + ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */ + mask.bcn_chk_rule = 0x3; + /* misc */ + ctrl.acpt_pwr_mngt_pkt = 1; + mask.acpt_pwr_mngt_pkt = 1; + ctrl.acpt_ftm_req_pkt = 1; + mask.acpt_ftm_req_pkt = 1; + #endif + break; + case RX_FLTR_MODE_STA_LINKING: + #if 1 + _hal_set_dft_rxfltr(&ctrl, &mask); + /* check broadcast */ + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.bc_pkt_chk_cam_match = 0; + mask.bc_pkt_chk_cam_match = 1; + + /* check beacon */ + ctrl.bcn_chk_en = 0; + mask.bcn_chk_en = 1; + + #else + /* filter packets by address */ + ctrl.sniffer_mode = 0; + mask.sniffer_mode = 1; + /* check unicast */ + ctrl.acpt_a1_match_pkt = 1; + mask.acpt_a1_match_pkt = 1; + ctrl.uc_pkt_chk_cam_match = 1; + mask.uc_pkt_chk_cam_match = 1; + /* check broadcast */ + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.bc_pkt_chk_cam_match = 0; + mask.bc_pkt_chk_cam_match = 1; + + if ((hal_com->chip_id == CHIP_WIFI6_8852A) + && (hal_com->cv == CAV)) { + /* don't check address cam for multicast, accept all */ + ctrl.acpt_mc_pkt = 0; + mask.acpt_mc_pkt = 1; + } else { + /* check multicast */ + ctrl.acpt_mc_pkt = 1; + mask.acpt_mc_pkt = 1; + /* black list filter */ + ctrl.mc_pkt_white_lst_mode = 0; + mask.mc_pkt_white_lst_mode = 1; + } + /* check beacon */ + ctrl.bcn_chk_en = 0; + mask.bcn_chk_en = 1; + ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */ + mask.bcn_chk_rule = 0x3; + /* misc */ + ctrl.acpt_pwr_mngt_pkt = 1; + mask.acpt_pwr_mngt_pkt = 1; + ctrl.acpt_ftm_req_pkt = 1; + mask.acpt_ftm_req_pkt = 1; + #endif + break; + + case RX_FLTR_MODE_AP_NORMAL: + #if 1 + _hal_set_dft_rxfltr(&ctrl, &mask); + + /* check unicast */ + ctrl.acpt_a1_match_pkt = 1; + mask.acpt_a1_match_pkt = 1; + ctrl.uc_pkt_chk_cam_match = 0; + mask.uc_pkt_chk_cam_match = 1; + + /* check broadcast (for probe req) */ + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.bc_pkt_chk_cam_match = 0; + mask.bc_pkt_chk_cam_match = 1; + + #else + /* + * SNIFFER: OFF + * UC address CAM A1: ON + * UC addr CAM match: OFF + * BC accept: ON + * BC address CAM: OFF + * Beacon check: OFF + */ + /* filter packets by address */ + ctrl.sniffer_mode = 0; + mask.sniffer_mode = 1; + /* Unicast + * Do not enable address CAM matching filtering but all A1 + * matched ones. AP should accept all UC requests from + * unknown STAs. + */ + ctrl.acpt_a1_match_pkt = 1; + mask.acpt_a1_match_pkt = 1; + ctrl.uc_pkt_chk_cam_match = 0; + mask.uc_pkt_chk_cam_match = 1; + + /* check broadcast (Probe req) */ + ctrl.acpt_bc_pkt = 1; + mask.acpt_bc_pkt = 1; + ctrl.bc_pkt_chk_cam_match = 0; + mask.bc_pkt_chk_cam_match = 1; + + if ((hal_com->chip_id == CHIP_WIFI6_8852A) + && (hal_com->cv == CAV)) { + /* don't check address cam for multicast, accept all */ + ctrl.acpt_mc_pkt = 1; + mask.acpt_mc_pkt = 1; + } else { + /* check multicast */ + ctrl.acpt_mc_pkt = 1; + mask.acpt_mc_pkt = 1; + /* black list filter */ + ctrl.mc_pkt_white_lst_mode = 0; + mask.mc_pkt_white_lst_mode = 1; + } + + /* check beacon */ + ctrl.bcn_chk_en = 1; + mask.bcn_chk_en = 1; + ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */ + mask.bcn_chk_rule = 0x3; + + /* bcn_chk_rule + 0: A3 hit + 1: A2 hit + 2: A2 & A3 hit + 3: A2 | A3 hit + */ + /* accept power management frame */ + ctrl.acpt_pwr_mngt_pkt = 1; + mask.acpt_pwr_mngt_pkt = 1; + ctrl.acpt_ftm_req_pkt = 1; + mask.acpt_ftm_req_pkt = 1; + #endif + break; + + } + + err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_set_rxfltr_acpt_crc_err - Accept CRC error packets or not + * @hal_com: pointer of struct rtw_hal_com_t + * @band: 0x0: band0, 0x1: band1 + * @enable: 0: deny, 1: accept + * + * Control accepting CRC error packets or not. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status rtw_hal_mac_set_rxfltr_acpt_crc_err( + struct rtw_hal_com_t *hal_com, u8 band, u8 enable) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_rx_fltr_ctrl_t ctrl = {0}; + struct mac_ax_rx_fltr_ctrl_t mask = {0}; + u32 err; + + + if (enable) + ctrl.acpt_crc32_err_pkt = 1; + else + ctrl.acpt_crc32_err_pkt = 0; + mask.acpt_crc32_err_pkt = 1; + + err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_set_rxfltr_mpdu_size - Set max MPDU size + * @hal_com: pointer of struct rtw_hal_com_t + * @band: 0x0: band0, 0x1: band1 + * @size: MPDU max size, unit: byte. 0 for no limit. + * + * MPDU size exceed Max size would be dropped. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status rtw_hal_mac_set_rxfltr_mpdu_size( + struct rtw_hal_com_t *hal_com, u8 band, u16 size) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_rx_fltr_ctrl_t ctrl = {0}; + struct mac_ax_rx_fltr_ctrl_t mask = {0}; + u32 err; + + + /* unit of pkt_len_fltr is 512 bytes */ + ctrl.pkt_len_fltr = size >> 9; + ctrl.pkt_len_fltr += (size & 0x7F) ? 1 : 0; + mask.pkt_len_fltr = 0x3F; + + err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_set_rxfltr_by_type - Filter RX frame by frame type + * @hal_com: pointer of struct rtw_hal_com_t + * @band: 0x0: band0, 0x1: band1 + * @type: 802.11 frame type, b'00: mgmt, b'01: ctrl, b'10: data + * @target: 0: drop, 1: accept(driver), 2: firmware + * + * Set RX filter setting by 802.11 frame type and frame would be dropped or + * forward to specific target. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok, otherwise fail. + */ +enum rtw_hal_status rtw_hal_mac_set_rxfltr_by_type( + struct rtw_hal_com_t *hal_com, u8 band, u8 type, u8 target) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_pkt_t ftype; + enum mac_ax_fwd_target fwd; + u32 err; + + + switch (type) { + case RTW_PHL_PKT_TYPE_MGNT: + ftype = MAC_AX_PKT_MGNT; + break; + case RTW_PHL_PKT_TYPE_CTRL: + ftype = MAC_AX_PKT_CTRL; + break; + case RTW_PHL_PKT_TYPE_DATA: + ftype = MAC_AX_PKT_DATA; + break; + default: + return RTW_HAL_STATUS_FAILURE; + } + + if (target > MAC_AX_FWD_TO_WLAN_CPU) + return RTW_HAL_STATUS_FAILURE; + fwd = (enum mac_ax_fwd_target)target; + + err = mac->ops->set_rx_fltr_typ_opt(mac, ftype, fwd, band); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_set_rxfltr_by_subtype - Filter RX frame by frame type & subtype + * @hal_com: pointer of struct rtw_hal_com_t + * @band: 0x0: band0, 0x1: band1 + * @type: 802.11 frame type, b'00: mgmt, b'01: ctrl, b'10: data + * @subtype: 802.11 frame subtype, value range is 0x00~0xFF. + * @target: 0: drop, 1: accept(driver), 2: firmware + * + * Set RX filter setting by 802.11 frame type and subtype, then frame would be + * dropped or forward to specific target. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok, otherwise fail. + */ +enum rtw_hal_status rtw_hal_mac_set_rxfltr_by_subtype( + struct rtw_hal_com_t *hal_com, u8 band, + u8 type, u8 subtype, u8 target) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_pkt_t ftype; + enum mac_ax_fwd_target fwd; + u32 err; + + + switch (type) { + case 0: + ftype = MAC_AX_PKT_MGNT; + break; + case 1: + ftype = MAC_AX_PKT_CTRL; + break; + case 2: + ftype = MAC_AX_PKT_DATA; + break; + default: + return RTW_HAL_STATUS_FAILURE; + } + + if (subtype > 0xFF) + return RTW_HAL_STATUS_FAILURE; + + if (target > MAC_AX_FWD_TO_WLAN_CPU) + return RTW_HAL_STATUS_FAILURE; + fwd = (enum mac_ax_fwd_target)target; + + err = mac->ops->set_rx_fltr_typstyp_opt(mac, ftype, subtype, fwd, band); + if (err) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_enable_bb_rf(struct hal_info_t *hal_info, u8 enable) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + + mac->ops->set_hw_value(mac, MAC_AX_HW_EN_BB_RF, &enable); + return RTW_HAL_STATUS_SUCCESS; +} + +void +rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr, + u8 *buf, u32 len, u32 dbg_path) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac_mem_dump(mac, MAC_AX_MEM_SHARED_BUF, strt_addr, buf, len, dbg_path); +} + +void +rtl_hal_dump_sec_cam_tbl(struct rtw_hal_com_t *hal_com) +{ + u32 i = 0; + u32 sec_cam_tbl_sz = 128; + struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct sec_cam_table_t *sec_cam_table = mac->hw_info->sec_cam_table; + struct sec_cam_entry_t *entry = NULL; + + PHL_PRINT("===== HW Info Security CAM Table =====\n"); + PHL_PRINT("entry valid mac_id key_id key_type\n"); + for (i = 0; i < sec_cam_tbl_sz; i++) { + entry = sec_cam_table->sec_cam_entry[i]; + if (entry == NULL) + continue; + + PHL_PRINT(" %3d %3d %3d %3d %3d\n", + i, entry->valid, entry->mac_id, entry->key_id, entry->key_type); + } +} + +void halmac_cmd_parser(struct hal_info_t *hal_info, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac->ops->halmac_cmd_parser(mac, input, input_num, output, out_len); +} + + +s32 halmac_cmd(struct hal_info_t *hal_info, char *input, char *output, u32 out_len) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + return mac->ops->halmac_cmd(mac, input, output, out_len); +} + +bool rtw_hal_mac_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + if(incmd->in_type == RTW_ARG_TYPE_BUF) + halmac_cmd(hal_info, incmd->in.buf, output, out_len); + else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){ + halmac_cmd_parser(hal_info, incmd->in.vector, + incmd->in_cnt_len, output, out_len); + } + + return true; +} + +static enum mac_ax_cmac_path_sel _ac_drv2mac(u8 ac, u8 wmm) +{ + enum mac_ax_cmac_path_sel sel = MAC_AX_CMAC_PATH_SEL_INVALID; + + + switch (ac) { + case 0: + /* BE */ + sel = MAC_AX_CMAC_PATH_SEL_BE0; + break; + case 1: + /* BK */ + sel = MAC_AX_CMAC_PATH_SEL_BK0; + break; + case 2: + /* VI */ + sel = MAC_AX_CMAC_PATH_SEL_VI0; + break; + case 3: + /* VO */ + sel = MAC_AX_CMAC_PATH_SEL_VO0; + break; + } + + if (sel != MAC_AX_CMAC_PATH_SEL_INVALID && wmm) + /* wmm == 1 */ + sel += 4; + + return sel; +} + +/** + * rtw_hal_mac_set_edca() - setup WMM EDCA parameter + * @hal_com: struct rtw_hal_com_t * + * @band: 0x0: band0, 0x1: band1 + * @wmm: hardware wmm index + * @ac: Access Category, 0:BE, 1:BK, 2:VI, 3:VO + * @param: AIFS:BIT[7:0], CWMIN:BIT[11:8], CWMAX:BIT[15:12], + * TXOP:BIT[31:16] + * + * Setup WMM EDCA parameter set for specific AC. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status +rtw_hal_mac_set_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 wmm, u8 ac, + u32 param) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_edca_param edca = {0}; + u32 err = 0; + + + edca.band = band; + edca.path = _ac_drv2mac(ac, wmm); + edca.txop_32us = param >> 16; + edca.ecw_max = (param >> 12) & 0xF; + edca.ecw_min = (param >> 8) & 0xF; + edca.aifs_us = param & 0xFF; + + err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_EDCA_PARAM, &edca); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#ifdef CONFIG_PHL_TWT +enum rtw_hal_status +rtw_hal_mac_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_twt_para mac_twt_para = {0}; + u32 mac_status = MACSUCCESS; + + switch (twt_info.nego_type) + { + case RTW_PHL_INDIV_TWT: + mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_IND; + mac_twt_para.flow_id = 0; + break; + case RTW_PHL_WAKE_TBTT_INR: + mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_WAKE; + mac_twt_para.flow_id = 0; + break; + case RTW_PHL_BCAST_TWT: + mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_BRC; + mac_twt_para.flow_id = twt_info.bcast_twt_id; + break; + default: + PHL_ERR("%s : Error TWT nego type %d\n", __func__, twt_info.nego_type); + return RTW_HAL_STATUS_FAILURE; + } + switch (action) { + case TWT_CFG_ADD: + mac_twt_para.act = MAC_AX_TWT_ACT_TP_ADD; + break; + case TWT_CFG_DELETE: + mac_twt_para.act = MAC_AX_TWT_ACT_TP_DEL; + break; + case TWT_CFG_MODIFY: + mac_twt_para.act = MAC_AX_TWT_ACT_TP_MOD; + break; + default: + PHL_ERR("%s : Error TWT action %d\n", __func__, action); + return RTW_HAL_STATUS_FAILURE; + } + mac_twt_para.trig = twt_info.trigger; + mac_twt_para.flow_tp = twt_info.flow_type; + mac_twt_para.proct = twt_info.twt_protection; + mac_twt_para.id = twt_info.twt_id; + mac_twt_para.wake_exp = twt_info.twt_wake_int_exp; + mac_twt_para.band = role->hw_band; + mac_twt_para.port = role->hw_port; + mac_twt_para.rsp_pm = twt_info.responder_pm_mode; + mac_twt_para.wake_unit = twt_info.wake_dur_unit; + mac_twt_para.impt = twt_info.implicit_lastbcast; + mac_twt_para.wake_man = twt_info.twt_wake_int_mantissa; + mac_twt_para.dur = twt_info.nom_min_twt_wake_dur; + mac_twt_para.trgt_l = twt_info.target_wake_time_l; + mac_twt_para.trgt_h = twt_info.target_wake_time_h; + /* HalMac API to setup/delete TWT config*/ + mac_status = mac->ops->twt_info_upd_h2c(mac, &mac_twt_para); + if (MACSUCCESS != mac_status){ + PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_info_update(): mac_twt_info_upd_h2c fail(%d)\n", + mac_status); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_twtact_para mac_twtact_para = {0}; + u32 mac_status = MACSUCCESS; + + switch (action) { + case TWT_STA_ADD_MACID: + mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_ADD; + break; + case TWT_STA_DEL_MACID: + mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_DEL; + break; + case TWT_STA_TETMINATW_SP: + mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_TRMNT; + break; + case TWT_STA_SUSPEND_TWT: + mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_SUS; + break; + case TWT_STA_RESUME_TWT: + mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_RSUM; + break; + default: + PHL_ERR("%s : Error TWT action %d\n", __func__, action); + return RTW_HAL_STATUS_FAILURE; + } + mac_twtact_para.macid = macid; + mac_twtact_para.id = twt_id; + /* Call HalMac API to setup/delete TWT STA config*/ + mac_status = mac->ops->twt_act_h2c(mac, &mac_twtact_para); + if (MACSUCCESS != mac_status) { + PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_sta_update(): mac_twt_act_h2c fail(%d)\n", + mac_status); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_twt_sta_announce(void *hal, u8 macid) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_twtanno_para mac_twtanno_para = {0}; + u32 mac_status = MACSUCCESS; + + mac_twtanno_para.macid = macid; + mac_status = mac->ops->twt_anno_h2c(mac, &mac_twtanno_para); + if (MACSUCCESS != mac_status) { + PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_sta_announce(): mac_twt_anno_h2c fail(%d)\n", + mac_status); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; +} +#endif /* CONFIG_PHL_TWT */ + +/** + * rtw_hal_mac_get_ampdu_cfg() - get ampdu config + * @hal_com: struct rtw_hal_com_t * + * @band: 0x0: band0, 0x1: band1 + * @cfg: struct hal_ax_ampdu_cfg * + * Get ampdu config. + * Return RTW_HAL_STATUS_SUCCESS when query is done. + */ +enum rtw_hal_status +rtw_hal_mac_get_ampdu_cfg(struct rtw_hal_com_t *hal_com, + u8 band, + struct mac_ax_ampdu_cfg *cfg) +{ + /* To Do: need to refine after Mac api updating*/ +#if 0 + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + u32 err = 0; + cfg->band = band; + err = mac->ops->get_hw_value(mac, MAC_AX_HW_GET_AMPDU_CFG, cfg); + if (err) + return RTW_HAL_STATUS_FAILURE; +#endif + return RTW_HAL_STATUS_SUCCESS; +} + +/* + * rtw_hal_mac_set_rty_lmt() - setup retry limit parameter + * @hal_com: struct rtw_hal_com_t * + * @macid: + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status +rtw_hal_mac_set_rty_lmt(struct rtw_hal_com_t *hal_com, u8 macid, + u8 rts_lmt_sel, u8 rts_lmt_val, u8 data_lmt_sel, u8 data_lmt_val) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_cctl_rty_lmt_cfg cfg = {0}; + u32 err = 0; + + + cfg.macid = macid; + cfg.data_lmt_sel = data_lmt_sel; + cfg.data_lmt_val = data_lmt_val; + cfg.rts_lmt_sel = rts_lmt_sel; + cfg.rts_lmt_val = rts_lmt_val; + + err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &cfg); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_is_tx_mgnt_empty() - Get tx mgnt queue status + * @hal_info: struct rtw_hal_info_t * + * @band: 0x0: band0, 0x1: band1 + * @st: queue status, 1 for empty and 0 for not empty. + * + * Return RTW_HAL_STATUS_SUCCESS when setting is ok. + */ +enum rtw_hal_status +rtw_hal_mac_is_tx_mgnt_empty(struct hal_info_t *hal_info, u8 band, u8 *st) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_tx_queue_empty q_st = {{0}}; + u32 err; + + + err = mac->ops->is_txq_empty(mac, &q_st); + if (err != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + if ((band == 0) && (q_st.band0_mgnt_empty == DLE_QUEUE_EMPTY)) + *st = 1; + else if ((band == 1) && (q_st.band1_mgnt_empty == DLE_QUEUE_EMPTY)) + *st = 1; + else + *st = 0; + + return RTW_HAL_STATUS_SUCCESS; +} + + +/* FW Sounding Command */ +/* 1. NDPA Content */ +void _hal_max_ax_snd_cmd_ndpa(struct mac_ax_ndpa_para *mac_ndpa, + struct hal_ndpa_para *hal_ndpa, + bool he, u8 sta_nr) +{ + u8 i = 0; + struct hal_he_ndpa_sta_info *hal_he_sta = NULL; + struct hal_vht_ndpa_sta_info *hal_vht_sta = NULL; + + mac_ndpa->common.frame_ctl = hal_ndpa->common.frame_ctl; + mac_ndpa->common.duration = hal_ndpa->common.duration; + for (i = 0; i < MAC_ALEN; i++) { + mac_ndpa->common.addr1[i] = hal_ndpa->common.addr1[i]; + mac_ndpa->common.addr2[i] = hal_ndpa->common.addr2[i]; + } + mac_ndpa->snd_dialog.dialog = hal_ndpa->snd_dialog.token; + mac_ndpa->snd_dialog.he = hal_ndpa->snd_dialog.he; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac he 0x%x sta_nr %d \n", he, sta_nr); + if (he) { + for (i = 0; (i < sta_nr)&&(i < HAL_MAX_HE_SND_STA_NUM); i++) { + hal_he_sta = (struct hal_he_ndpa_sta_info *) + &hal_ndpa->ndpa_sta_info[i]; + mac_ndpa->he_para.sta_info[i].aid = hal_he_sta->aid; + mac_ndpa->he_para.sta_info[i].bw = hal_he_sta->bw; + mac_ndpa->he_para.sta_info[i].fb_ng = hal_he_sta->fb_ng; + mac_ndpa->he_para.sta_info[i].disambiguation = 1; + mac_ndpa->he_para.sta_info[i].cb = hal_he_sta->cb;//cb nc + mac_ndpa->he_para.sta_info[i].nc = hal_he_sta->nc;//cb nc + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac cmd buf HE (%d) : aid 0x%x bw 0x%x fbng 0x%x cb 0x%x nc 0x%x\n", + i, mac_ndpa->he_para.sta_info[i].aid, + mac_ndpa->he_para.sta_info[i].bw, + mac_ndpa->he_para.sta_info[i].fb_ng, + mac_ndpa->he_para.sta_info[i].cb, + mac_ndpa->he_para.sta_info[i].nc); + } + } else { + for (i = 0; (i < sta_nr)&&(i < HAL_MAX_VHT_SND_STA_NUM); i++) { + hal_vht_sta = (struct hal_vht_ndpa_sta_info *) + &hal_ndpa->ndpa_sta_info[i]; + mac_ndpa->vht_para.sta_info[i].aid = + (u16)hal_vht_sta->aid12; + mac_ndpa->vht_para.sta_info[i].fb_type = + (u16)hal_vht_sta->feedback_type; + mac_ndpa->vht_para.sta_info[i].nc = + (u16)hal_vht_sta->nc; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac cmd buf VHT(%d) : aid 0x%x fb 0x%x nc 0x%x\n", + i, + mac_ndpa->vht_para.sta_info[i].aid, + mac_ndpa->vht_para.sta_info[i].fb_type, + mac_ndpa->vht_para.sta_info[i].nc); + } + } +} +/* 2-1. BFRP Content - VHT */ +void _hal_max_ax_snd_cmd_bfrp_vht(struct mac_ax_bfrp_para *mac_bfrp, + struct hal_bfrp_para *hal_bfrp, u8 bfrp_num) +{ + struct mac_ax_vht_bfrp_para *mac_vht_bfrp = NULL; + struct hal_bfrp_vht *hal_vht_bfrp = NULL; + u8 i = 0, j = 0; + for (i = 0; (i <= bfrp_num)&&(i < HAL_MAX_VHT_BFRP_NUM); i++){ + mac_bfrp->hdr[i].frame_ctl = hal_bfrp->hdr[i].frame_ctl; + mac_bfrp->hdr[i].duration = hal_bfrp->hdr[i].duration; + for (j = 0; j < MAC_ALEN; j++) { + mac_bfrp->hdr[i].addr1[j] = hal_bfrp->hdr[i].addr1[j]; + mac_bfrp->hdr[i].addr2[j] = hal_bfrp->hdr[i].addr2[j]; + } + mac_vht_bfrp = &mac_bfrp->vht_para[i]; + hal_vht_bfrp = &hal_bfrp->vht_para[i]; + mac_vht_bfrp->retransmission_bitmap = hal_vht_bfrp->rexmit_bmp; + } +} +/* 2-2. BFRP Content - HE */ +void _hal_max_ax_snd_cmd_bfrp_he(struct mac_ax_bfrp_para *mac_bfrp, + struct hal_bfrp_para *hal_bfrp, + u8 num_1, u8 num_2) +{ + u8 i = 0; + struct mac_ax_he_bfrp_para *mac_he_bfrp = NULL; + struct hal_bfrp_he *hal_he_bfrp = NULL; + + /* BFRP-0 */ + if (num_1) { + mac_bfrp->hdr[0].frame_ctl = hal_bfrp->hdr[0].frame_ctl; + mac_bfrp->hdr[0].duration = hal_bfrp->hdr[0].duration; + for (i = 0; i < MAC_ALEN; i++) { + mac_bfrp->hdr[0].addr1[i] = hal_bfrp->hdr[0].addr1[i]; + mac_bfrp->hdr[0].addr2[i] = hal_bfrp->hdr[0].addr2[i]; + } + mac_he_bfrp = &mac_bfrp->he_para[0]; + hal_he_bfrp = &hal_bfrp->he_para[0]; + mac_he_bfrp->common.tgr_info = hal_he_bfrp->common.tgr_info; + mac_he_bfrp->common.ul_len = hal_he_bfrp->common.ul_len; + mac_he_bfrp->common.more_tf = hal_he_bfrp->common.more_tf; + mac_he_bfrp->common.cs_rqd = hal_he_bfrp->common.cs_rqd; + mac_he_bfrp->common.ul_bw = hal_he_bfrp->common.ul_bw; + mac_he_bfrp->common.gi_ltf = hal_he_bfrp->common.gi_ltf; + mac_he_bfrp->common.mimo_ltfmode = + hal_he_bfrp->common.mimo_ltfmode; + mac_he_bfrp->common.num_heltf = hal_he_bfrp->common.num_heltf; + mac_he_bfrp->common.ul_pktext = hal_he_bfrp->common.ul_pktext; + mac_he_bfrp->common.ul_stbc = hal_he_bfrp->common.ul_stbc; + mac_he_bfrp->common.ldpc_extra_sym = + hal_he_bfrp->common.ldpc_extra_sym; + mac_he_bfrp->common.dplr = hal_he_bfrp->common.dplr; + mac_he_bfrp->common.ap_tx_pwr = hal_he_bfrp->common.ap_tx_pwr; + mac_he_bfrp->common.ul_sr = hal_he_bfrp->common.ul_sr; + mac_he_bfrp->common.ul_siga2_rsvd = + hal_he_bfrp->common.ul_siga2_rsvd; + for( i = 0; (i < num_1)&&(i < HAL_MAX_HE_BFRP_STA_NUM); i++) { + mac_he_bfrp->user[i].aid12 = + hal_he_bfrp->user[i].aid12; + mac_he_bfrp->user[i].fbseg_rexmit_bmp = + hal_he_bfrp->fbseg_rexmit_bmp[i]; + mac_he_bfrp->user[i].ru_pos = + hal_he_bfrp->user[i].ru_pos; + mac_he_bfrp->user[i].ss_alloc = + hal_he_bfrp->user[i].ss_alloc; + mac_he_bfrp->user[i].ul_dcm = + hal_he_bfrp->user[i].ul_dcm; + mac_he_bfrp->user[i].ul_fec_code = + hal_he_bfrp->user[i].ul_fec_code; + mac_he_bfrp->user[i].ul_mcs = + hal_he_bfrp->user[i].ul_mcs; + mac_he_bfrp->user[i].ul_tgt_rssi = + hal_he_bfrp->user[i].ul_tgt_rssi; + } + } + /* BFRP - 1 */ + if (num_2) { + mac_bfrp->hdr[1].frame_ctl = hal_bfrp->hdr[1].frame_ctl; + mac_bfrp->hdr[1].duration = hal_bfrp->hdr[1].duration; + for (i = 0; i < MAC_ALEN; i++) { + mac_bfrp->hdr[1].addr1[i] = hal_bfrp->hdr[1].addr1[i]; + mac_bfrp->hdr[1].addr2[i] = hal_bfrp->hdr[1].addr2[i]; + } + mac_he_bfrp = &mac_bfrp->he_para[1]; + hal_he_bfrp = &hal_bfrp->he_para[1]; + mac_he_bfrp->common.tgr_info = hal_he_bfrp->common.tgr_info; + mac_he_bfrp->common.ul_len = hal_he_bfrp->common.ul_len; + mac_he_bfrp->common.more_tf = hal_he_bfrp->common.more_tf; + mac_he_bfrp->common.cs_rqd = hal_he_bfrp->common.cs_rqd; + mac_he_bfrp->common.ul_bw = hal_he_bfrp->common.ul_bw; + mac_he_bfrp->common.gi_ltf = hal_he_bfrp->common.gi_ltf; + mac_he_bfrp->common.mimo_ltfmode = + hal_he_bfrp->common.mimo_ltfmode; + mac_he_bfrp->common.num_heltf = hal_he_bfrp->common.num_heltf; + mac_he_bfrp->common.ul_pktext = hal_he_bfrp->common.ul_pktext; + mac_he_bfrp->common.ul_stbc = hal_he_bfrp->common.ul_stbc; + mac_he_bfrp->common.ldpc_extra_sym = + hal_he_bfrp->common.ldpc_extra_sym; + mac_he_bfrp->common.dplr = hal_he_bfrp->common.dplr; + mac_he_bfrp->common.ap_tx_pwr = hal_he_bfrp->common.ap_tx_pwr; + mac_he_bfrp->common.ul_sr = hal_he_bfrp->common.ul_sr; + mac_he_bfrp->common.ul_siga2_rsvd = + hal_he_bfrp->common.ul_siga2_rsvd; + for( i = 0; (i < num_1)&&(i < HAL_MAX_HE_BFRP_STA_NUM); i++) { + mac_he_bfrp->user[i].aid12 = + hal_he_bfrp->user[i].aid12; + mac_he_bfrp->user[i].fbseg_rexmit_bmp = + hal_he_bfrp->fbseg_rexmit_bmp[i]; + mac_he_bfrp->user[i].ru_pos = + hal_he_bfrp->user[i].ru_pos; + mac_he_bfrp->user[i].ss_alloc = + hal_he_bfrp->user[i].ss_alloc; + mac_he_bfrp->user[i].ul_dcm = + hal_he_bfrp->user[i].ul_dcm; + mac_he_bfrp->user[i].ul_fec_code = + hal_he_bfrp->user[i].ul_fec_code; + mac_he_bfrp->user[i].ul_mcs = + hal_he_bfrp->user[i].ul_mcs; + mac_he_bfrp->user[i].ul_tgt_rssi = + hal_he_bfrp->user[i].ul_tgt_rssi; + } + } +} + +/* 2-3 he bfrp f2p cmd */ +void _hal_max_ax_snd_cmd_bfrp_he_f2p(struct mac_ax_snd_f2P *mac_bfrp_f2p, + struct hal_bfrp_para *hal_bfrp, + u8 num_1, u8 num_2) +{ + struct hal_bfrp_he *hal_he_bfrp = NULL; + if (num_1) { + hal_he_bfrp = &hal_bfrp->he_para[0]; + mac_bfrp_f2p[0].csi_len_bfrp = + hal_he_bfrp->f2p_info.csi_len_bfrp; + mac_bfrp_f2p[0].tb_t_pe_bfrp = + hal_he_bfrp->f2p_info.tb_t_pe_bfrp; + mac_bfrp_f2p[0].tri_pad_bfrp = + hal_he_bfrp->f2p_info.tri_pad_bfrp; + mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp = + hal_he_bfrp->f2p_info.ul_cqi_rpt_tri_bfrp; + mac_bfrp_f2p[0].rf_gain_idx_bfrp = + hal_he_bfrp->f2p_info.rf_gain_idx_bfrp; + mac_bfrp_f2p[0].fix_gain_en_bfrp = + hal_he_bfrp->f2p_info.fix_gain_en_bfrp; + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "==> _hal_max_ax_snd_cmd_bfrp_he_f2p[0] \n"); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].csi_len_bfrp = 0x%x \n", + mac_bfrp_f2p[0].csi_len_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].tb_t_pe_bfrp = 0x%x \n", + mac_bfrp_f2p[0].tb_t_pe_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].tri_pad_bfrp = 0x%x \n", + mac_bfrp_f2p[0].tri_pad_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp = 0x%x \n", + mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].rf_gain_idx_bfrp = 0x%x \n", + mac_bfrp_f2p[0].rf_gain_idx_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[0].fix_gain_en_bfrp = 0x%x \n", + mac_bfrp_f2p[0].fix_gain_en_bfrp); + } + if (num_2) { + hal_he_bfrp = &hal_bfrp->he_para[1]; + mac_bfrp_f2p[1].csi_len_bfrp = + hal_he_bfrp->f2p_info.csi_len_bfrp; + mac_bfrp_f2p[1].tb_t_pe_bfrp = + hal_he_bfrp->f2p_info.tb_t_pe_bfrp; + mac_bfrp_f2p[1].tri_pad_bfrp = + hal_he_bfrp->f2p_info.tri_pad_bfrp; + mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp = + hal_he_bfrp->f2p_info.ul_cqi_rpt_tri_bfrp; + mac_bfrp_f2p[1].rf_gain_idx_bfrp = + hal_he_bfrp->f2p_info.rf_gain_idx_bfrp; + mac_bfrp_f2p[1].fix_gain_en_bfrp = + hal_he_bfrp->f2p_info.fix_gain_en_bfrp; + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "==> _hal_max_ax_snd_cmd_bfrp_he_f2p[1] \n"); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].csi_len_bfrp = 0x%x \n", + mac_bfrp_f2p[1].csi_len_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].tb_t_pe_bfrp = 0x%x \n", + mac_bfrp_f2p[1].tb_t_pe_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].tri_pad_bfrp = 0x%x \n", + mac_bfrp_f2p[1].tri_pad_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp = 0x%x \n", + mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].rf_gain_idx_bfrp = 0x%x \n", + mac_bfrp_f2p[1].rf_gain_idx_bfrp); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, + "mac_bfrp_f2p[1].fix_gain_en_bfrp = 0x%x \n", + mac_bfrp_f2p[1].fix_gain_en_bfrp); + } +} + + +/* 3. WD Content */ +void _hal_max_ax_snd_cmd_wd(struct mac_ax_snd_wd_para *mac_wd, + struct hal_snd_wd_para *hal_wd) +{ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> _hal_max_ax_snd_cmd_wd \n"); + mac_wd->txpktsize = hal_wd->txpktsize; + mac_wd->ndpa_duration = hal_wd->ndpa_duration; + mac_wd->datarate = hal_wd->datarate; + mac_wd->macid = hal_wd->macid; + mac_wd->force_txop = hal_wd->force_txop; + mac_wd->data_bw = hal_wd->data_bw; + mac_wd->gi_ltf = hal_wd->gi_ltf; + mac_wd->data_er = hal_wd->data_er; + mac_wd->data_dcm = hal_wd->data_dcm; + mac_wd->data_stbc = hal_wd->data_stbc; + mac_wd->data_ldpc = hal_wd->data_ldpc; + mac_wd->data_bw_er = hal_wd->data_bw_er; + mac_wd->multiport_id = hal_wd->multiport_id; + mac_wd->mbssid = hal_wd->mbssid; + + mac_wd->signaling_ta_pkt_sc = hal_wd->signaling_ta_pkt_sc; + mac_wd->sw_define = hal_wd->sw_define; + mac_wd->txpwr_ofset_type = hal_wd->txpwr_ofset_type; + mac_wd->lifetime_sel = hal_wd->lifetime_sel; + mac_wd->stf_mode = hal_wd->stf_mode; + mac_wd->disdatafb = hal_wd->disdatafb; + mac_wd->data_txcnt_lmt_sel = hal_wd->data_txcnt_lmt_sel; + mac_wd->data_txcnt_lmt = hal_wd->data_txcnt_lmt; + mac_wd->sifs_tx = hal_wd->sifs_tx; + mac_wd->snd_pkt_sel = hal_wd->snd_pkt_sel; + mac_wd->ndpa = hal_wd->ndpa; + + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->txpktsize = 0x%x \n", mac_wd->txpktsize); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->ndpa_duration = 0x%x \n", mac_wd->ndpa_duration); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->datarate = 0x%x \n", mac_wd->datarate); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->macid = 0x%x \n", mac_wd->macid); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->force_txop = 0x%x \n", mac_wd->force_txop); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_bw = 0x%x \n", mac_wd->data_bw); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->gi_ltf = 0x%x \n", mac_wd->gi_ltf); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_er = 0x%x \n", mac_wd->data_er); + + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_dcm = 0x%x \n", mac_wd->data_dcm); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_stbc = 0x%x \n", mac_wd->data_stbc); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_ldpc = 0x%x \n", mac_wd->data_ldpc); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_bw_er = 0x%x \n", mac_wd->data_bw_er); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->multiport_id = 0x%x \n", mac_wd->multiport_id); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->mbssid = 0x%x \n", mac_wd->mbssid); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->signaling_ta_pkt_sc = 0x%x \n", mac_wd->signaling_ta_pkt_sc); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->sw_define = 0x%x \n", mac_wd->sw_define); + + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->txpwr_ofset_type = 0x%x \n", mac_wd->txpwr_ofset_type); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->lifetime_sel = 0x%x \n", mac_wd->lifetime_sel); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->stf_mode = 0x%x \n", mac_wd->stf_mode); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->disdatafb = 0x%x \n", mac_wd->disdatafb); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_txcnt_lmt_sel = 0x%x \n", mac_wd->data_txcnt_lmt_sel); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_txcnt_lmt = 0x%x \n", mac_wd->data_txcnt_lmt); + PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->sifs_tx = 0x%x \n", mac_wd->sifs_tx); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->snd_pkt_sel = 0x%x \n", mac_wd->snd_pkt_sel); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->ndpa = 0x%x \n", mac_wd->ndpa); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== _hal_max_ax_snd_cmd_wd \n"); +} + + +enum rtw_hal_status +hal_mac_ax_send_fw_snd(struct hal_info_t *hal_info, + struct hal_ax_fwcmd_snd *hal_cmd) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_fwcmd_snd snd_cmd = {0}; + u8 i = 0, he = 0, sta_nr = 0; + + /* 1. COMMAND Common */ + snd_cmd.frexgtype = hal_cmd->frame_ex_type; + snd_cmd.bfrp0_user_num = hal_cmd->bfrp0_sta_nr; + snd_cmd.bfrp1_user_num = hal_cmd->bfrp1_sta_nr; + for (i = 0; i < HAL_MAX_HE_SND_STA_NUM; i++) { + snd_cmd.macid[i] = (u8)hal_cmd->macid[i]; + } + + he = (hal_cmd->frame_ex_type >= HAL_FEXG_TYPE_AX_SU) ? 1 : 0; + + if (hal_cmd->frame_ex_type == HAL_FEXG_TYPE_AX_SU) { + sta_nr = 1; + } else { + sta_nr = he ? (hal_cmd->bfrp0_sta_nr + hal_cmd->bfrp1_sta_nr) : + (hal_cmd->frame_ex_type - HAL_FEXG_TYPE_AC_SU + 1); + } + + /* 2. NDPA Content */ + _hal_max_ax_snd_cmd_ndpa(&snd_cmd.pndpa, &hal_cmd->ndpa, + he, sta_nr); + /* 3. BFRP Content */ + if (he) { + _hal_max_ax_snd_cmd_bfrp_he(&snd_cmd.pbfrp, &hal_cmd->bfrp, + hal_cmd->bfrp0_sta_nr, hal_cmd->bfrp1_sta_nr); + _hal_max_ax_snd_cmd_bfrp_he_f2p(snd_cmd.f2p, &hal_cmd->bfrp, + hal_cmd->bfrp0_sta_nr, hal_cmd->bfrp1_sta_nr); + } else { + _hal_max_ax_snd_cmd_bfrp_vht(&snd_cmd.pbfrp, &hal_cmd->bfrp, + (sta_nr - 1)); + } + /* 4. WD Content */ + /* 4-1 NDPA */ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "NDPA WD: \n"); + _hal_max_ax_snd_cmd_wd(&snd_cmd.wd[0], &hal_cmd->wd[0]); + /* 4-2 NDP */ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "NDP WD: \n"); + _hal_max_ax_snd_cmd_wd(&snd_cmd.wd[1], &hal_cmd->wd[1]); + /* 4-3 BFRP*/ + if (he) { + if (hal_cmd->bfrp0_sta_nr) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE BFRP-1 WD: \n"); + _hal_max_ax_snd_cmd_wd(&snd_cmd.wd[2], + &hal_cmd->wd[2]); + } + if (hal_cmd->bfrp1_sta_nr) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE BFRP-2 WD: \n"); + _hal_max_ax_snd_cmd_wd(&snd_cmd.wd[3], + &hal_cmd->wd[3]); + } + } else { + for (i = 0; i < (sta_nr - 1)&&(i < HAL_MAX_VHT_BFRP_NUM); + i++) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "VHT BFRP %d WD: \n", i); + _hal_max_ax_snd_cmd_wd(&snd_cmd.wd[2 + i], + &hal_cmd->wd[2 + i]); + } + } + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.macid[0] = 0x%x \n", snd_cmd.macid[0]); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.bfrp0_user_num = 0x%x \n", snd_cmd.bfrp0_user_num); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.bfrp1_user_num = 0x%x \n", snd_cmd.bfrp1_user_num); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.mode = 0x%x \n", snd_cmd.mode); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.frexgtype = 0x%x \n", snd_cmd.frexgtype); + hstatus = mac->ops->set_snd_para(mac, &snd_cmd); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] hal_mac_ax_send_fw_snd hstatus = 0x%x\n", hstatus); + + return hstatus; +} + + + +enum rtw_hal_status +rtw_hal_mac_tx_mode_sel(struct hal_info_t *hal_info, u8 fw_tx, u8 txop_wmm_en_bm) +{ + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + + struct mac_ax_mac_tx_mode_sel mode_sel = {0}; + + if (fw_tx) + mode_sel.sw_mode_band0_en = 1; + if (txop_wmm_en_bm & BIT(0)) + mode_sel.txop_rot_wmm0_en = 1; + if (txop_wmm_en_bm & BIT(1)) + mode_sel.txop_rot_wmm1_en = 1; + if (txop_wmm_en_bm & BIT(2)) + mode_sel.txop_rot_wmm2_en = 1; + if (txop_wmm_en_bm & BIT(3)) + mode_sel.txop_rot_wmm3_en = 1; + + mac->ops->tx_mode_sel(mac, &mode_sel); + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtw_hal_mac_process_c2h(void *hal, struct rtw_c2h_info *c2h) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + struct mac_ax_ccxrpt mac_ccx = {0}; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; +#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL + u32 retry_limit = 32; +#endif + u32 retid = 0; + + hal_status = mac->ops->get_c2h_event(mac, c2h, (enum phl_msg_evt_id *)&retid, (u8 *)&mac_ccx); + /*PHL_INFO("%s, hal_status=%d, retid=%d\n", __func__, hal_status, retid);*/ + + if (hal_status == RTW_HAL_STATUS_SUCCESS && (retid == MSG_EVT_CCX_REPORT_TX_OK || retid == MSG_EVT_CCX_REPORT_TX_FAIL)) { + #if 0 + PHL_INFO("%s, mac_ccx.tx_state=%d\n", __func__, mac_ccx.tx_state); + PHL_INFO("%s, mac_ccx.sw_define=%d\n", __func__, mac_ccx.sw_define); + PHL_INFO("%s, mac_ccx.macid=%d\n", __func__, mac_ccx.macid); + PHL_INFO("%s, mac_ccx.pkt_ok_num=%d\n", __func__, mac_ccx.pkt_ok_num); + PHL_INFO("%s, mac_ccx.data_txcnt=%d\n", __func__, mac_ccx.data_txcnt); + #endif + +#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL + if (hal_info->hal_com->spe_pkt_cnt_lmt) + retry_limit = hal_info->hal_com->spe_pkt_cnt_lmt; + + if (retid == MSG_EVT_CCX_REPORT_TX_FAIL && mac_ccx.data_txcnt != retry_limit) + retid = 0; +#endif + } + return retid; +} + +enum rtw_hal_status +rtw_hal_mac_f2p_test_cmd(struct hal_info_t *hal_info, + struct mp_mac_ax_f2p_test_para *info, + struct mp_mac_ax_f2p_wd *f2pwd, + struct mp_mac_ax_f2p_tx_cmd *ptxcmd, + u8 *psigb_addr) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 ret = RTW_HAL_STATUS_FAILURE; + + if (mac->ops->f2p_test_cmd(mac, (void*)info, (void*)f2pwd, (void*)ptxcmd, psigb_addr) == MACSUCCESS) + ret = RTW_HAL_STATUS_SUCCESS; + + return ret; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_ofst_mode(struct rtw_hal_com_t *hal_com, u8 band) +{ + + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_ofst_mode(mac, band, tpu); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_ofst_bw(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_ofst_bw(mac, band, tpu); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_ref_reg(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_ref_reg(mac, band, tpu); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_en(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_limit_en(mac, band, tpu); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_set_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band, bool en_val) +{ + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + tpu->pwr_lmt_en = en_val; + + return RTW_HAL_STATUS_SUCCESS; +} + +bool +rtw_hal_mac_get_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band) +{ + + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + return tpu->pwr_lmt_en; +} + +enum rtw_hal_status +rtw_hal_mac_set_tpu_mode(struct rtw_hal_com_t *hal_com, + enum rtw_tpu_op_mode op_mode_new, u8 band) +{ + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (op_mode_new == TPU_DBG_MODE) { + tpu->op_mode = TPU_DBG_MODE; + tpu->normal_mode_lock_en = true; + } else { + tpu->op_mode = TPU_NORMAL_MODE; + tpu->normal_mode_lock_en = false; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_limit_rua_reg(mac, band, tpu); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + struct rtw_tpu_pwr_imt_info *lmt = &tpu->rtw_tpu_pwr_imt_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_limit_reg(mac, band, lmt); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i; + struct rtw_tpu_pwr_by_rate_info *by_rate = &tpu->rtw_tpu_pwr_by_rate_i; + + if (tpu->normal_mode_lock_en) + return RTW_HAL_STATUS_FAILURE; + + mac->ops->write_pwr_by_rate_reg(mac, band, by_rate); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_log_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE, val) != MACSUCCESS){ + PHL_ERR("%s: Get bt efuse size fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + PHL_INFO("%s: BT Efuse log size = %d!\n", __FUNCTION__, *val); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_mask_size(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if(mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: bt efuse mask size = %d\n", __FUNCTION__, *val); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, + u8 *map, + u32 map_size, + u8 *mask, + u32 mask_size) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_pg_efuse_info info; + enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + u8 *tmp_map = NULL; + u8 *tmp_mask = NULL; + + tmp_map = _os_mem_alloc(hal_com->drv_priv, map_size); + if(tmp_map == NULL) { + PHL_WARN("%s: Allocate pg map buffer fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_RESOURCE; + goto err_mem_tmp_map; + } + + tmp_mask = _os_mem_alloc(hal_com->drv_priv, mask_size); + if(tmp_mask == NULL) { + PHL_WARN("%s: Allocate pg mask buffer fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_RESOURCE; + goto err_mem_tmp_mask; + } + + /* Copy efuse map to tmp_map buffer */ + _os_mem_cpy(hal_com->drv_priv, tmp_map, map, map_size); + + /* Copy efuse mask to tmp_mask buffer */ + _os_mem_cpy(hal_com->drv_priv, tmp_mask, mask, mask_size); + + + info.efuse_map = tmp_map; + info.efuse_map_size = map_size; + info.efuse_mask = tmp_mask; + info.efuse_mask_size= mask_size; + + if (mac->ops->pg_efuse_by_map_bt(mac, + &info, + MAC_AX_EFUSE_R_DRV) != MACSUCCESS) { + PHL_INFO("%s: BT PG Fail!\n", __FUNCTION__); + status = RTW_HAL_STATUS_EFUSE_PG_FAIL; + } + else { + PHL_INFO("%s: BT PG ok!\n", __FUNCTION__); + status = RTW_HAL_STATUS_SUCCESS; + } + _os_mem_free(hal_com->drv_priv, tmp_map, map_size); + _os_mem_free(hal_com->drv_priv, tmp_mask, mask_size); + + return status; + +err_mem_tmp_mask: + _os_mem_free(hal_com->drv_priv, tmp_mask, mask_size); + +err_mem_tmp_map: + _os_mem_free(hal_com->drv_priv, tmp_map, map_size); + + return status; +} + +enum rtw_hal_status +rtw_hal_mac_read_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, u8 *map) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->dump_log_efuse_bt(mac, + MAC_AX_EFUSE_PARSER_MAP, + #ifdef RTW_WKARD_EFUSE_OPERATION + MAC_AX_EFUSE_R_DRV, + #else + MAC_AX_EFUSE_R_AUTO, + #endif + map + ) != MACSUCCESS) { + PHL_INFO("%s: Dump bt logical efuse fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s: Dump bt logical efuse ok!\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_avl(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_efuse_avl_size_bt(mac, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_get_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_hw_value(mac, + MAC_AX_HW_GET_BT_EFUSE_SIZE, val) != MACSUCCESS){ + PHL_ERR("%s: Get efuse bt size fail!\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + PHL_INFO("%s: Efuse size = %d!\n", __FUNCTION__, *val); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_set_mu_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 ac, + u16 timer, u8 cw_min, u8 cw_max, u8 aifs) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_muedca_param edca = {0}; + u32 err = 0; + + edca.band = band; + edca.ac = ac; + edca.aifs_us = aifs; + edca.ecw_min = cw_min; + edca.ecw_max = cw_max; + edca.muedca_timer_32us = timer; + err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_MUEDCA_PARAM, &edca); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_set_mu_edca_ctrl(struct rtw_hal_com_t *hal_com, + u8 band, u8 wmm, u8 set) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_muedca_cfg cfg = {0}; + u32 err = 0; + + cfg.band = band; + cfg.wmm_sel = wmm; + cfg.countdown_en = set; + cfg.tb_update_en = set; + err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_MUEDCA_CTRL, &cfg); + if (err) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_led_set_ctrl_mode(struct hal_info_t *hal_info, + enum mac_ax_led_mode mode, + u8 led_id) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->set_led_mode(mac, mode, led_id) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_led_ctrl(struct hal_info_t *hal_info, u8 high, + u8 led_id) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->led_ctrl(mac, high, led_id) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_sw_gpio_ctrl(struct hal_info_t *hal_info, u8 high, + u8 gpio) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->sw_gpio_ctrl(mac, high, gpio) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_set_sw_gpio_mode(struct hal_info_t *hal_info, enum rtw_gpio_mode mode, + u8 gpio) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->set_sw_gpio_mode(mac, mode, gpio) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_get_wl_dis_val(struct hal_info_t *hal_info, u8 *val) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->get_wl_dis_val(mac, val) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_pcie_trx_mit(struct hal_info_t *hal_info, + struct mac_ax_pcie_trx_mitigation *mit_info) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (MACSUCCESS != + mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_MIT, mit_info)) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_read_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u32 size, u8 *val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + if (mac->ops->read_efuse(mac, addr, size, val, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) + return RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_write_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u8 val) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + u8 tmp_value; + + if (mac->ops->read_efuse(mac, addr, 1, &tmp_value, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) { + PHL_INFO("%s read bt efuse hideen block fail.\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + if(tmp_value != 0xFF) { + PHL_INFO("%s bt efuse hidden offset = 0x%x has value = 0x%x.\n", __FUNCTION__, addr, tmp_value); + return RTW_HAL_STATUS_FAILURE; + } + + if (mac->ops->write_efuse(mac, addr, val, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) { + PHL_INFO("%s write bt efuse hideen block fail.\n", __FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_tsf_sync(struct hal_info_t *hal_info, + u8 from_port, u8 to_port, enum phl_band_idx band, + s32 sync_offset_tu, enum hal_tsf_sync_act action) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum mac_ax_tsf_sync_act mac_action = MAC_AX_TSF_SYNC_NOW_ONCE; + s32 sync_offset_unit = 0;/* for halmac API use, unit is 32us */ + + switch (action){ + case HAL_TSF_SYNC_NOW_ONCE : + mac_action = MAC_AX_TSF_SYNC_NOW_ONCE; + break; + case HAL_TSF_EN_SYNC_AUTO : + mac_action = MAC_AX_TSF_EN_SYNC_AUTO; + break; + case HAL_TSF_DIS_SYNC_AUTO : + mac_action = MAC_AX_TSF_DIS_SYNC_AUTO; + break; + default : + PHL_ERR("Unknown tsf sync action %d\n", action); + goto _error; + } + + /* covert TU to unit(unit is 32us, 1TU=1024us=32*32us) */ + sync_offset_unit = sync_offset_tu * 32; + + if (mac->ops->tsf_sync(mac, from_port, to_port, + sync_offset_unit, mac_action) == MACSUCCESS) + return RTW_HAL_STATUS_SUCCESS; +_error: + return RTW_HAL_STATUS_FAILURE; +} + +/** + * rtw_hal_mac_get_sec_cam() - get the security cam raw data from HW + * @hal_info: struct hal_info_t * + * @num: How many cam you wnat to dump from the first one. + * @buf: ptr to buffer which store the content from HW. + * If buf is NULL, use console as debug path. + * @size Size of allocated memroy for @buf. + * The size should be @num * size of security cam offset(0x20). + * + * Return RTW_HAL_STATUS_SUCCESS when function successfully works, + * otherwise, return RTW_HAL_STATUS_FAILURE. + */ +enum rtw_hal_status +rtw_hal_mac_get_sec_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + int i = 0; + /* ToDO: fix the magic number later */ + u8 sec_cam_offset_sz = 0x20; + + if (buf == NULL) { + /* to console */ + for (i = 0; i < num; i++) { + PHL_INFO("======= SEC CAM (%d)DUMP =======\n", i); + mac_mem_dump(mac, MAC_AX_MEM_SECURITY_CAM, i*sec_cam_offset_sz\ + , NULL, sec_cam_offset_sz, 0); + PHL_INFO("\n"); + } + } else { + /* to buffer */ + if (size < sec_cam_offset_sz*num) { + PHL_ERR("%s buf size is not enough to dump security cam\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + for (i = 0; i < num; i++) + mac_mem_dump(mac, MAC_AX_MEM_SECURITY_CAM, i*sec_cam_offset_sz\ + , buf + (i*sec_cam_offset_sz), sec_cam_offset_sz, 1); + } + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_get_addr_cam() - get the address cam raw data from HW + * @hal_info: struct hal_info_t * + * @num: How many cam you wnat to dump from the first one. + * @buf: ptr to buffer which store the content from HW. + * If buf is NULL, use console as debug path. + * @size Size of allocated memroy for @buf. + * The size should be @num * size of Addr cam offset(0x40). + * + * Return RTW_HAL_STATUS_SUCCESS when function successfully works, + * otherwise, return RTW_HAL_STATUS_FAILURE. + */ +enum rtw_hal_status +rtw_hal_mac_get_addr_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + int i = 0; + /* ToDO: fix the magic number later */ + u8 addr_cam_offset_sz = 0x40; + + if (buf == NULL) { + /* to console */ + for (i = 0; i < num; i++) { + PHL_INFO("======= ADDR CAM (%d)DUMP =======\n", i); + mac_mem_dump(mac, MAC_AX_MEM_ADDR_CAM, i*addr_cam_offset_sz\ + , NULL, addr_cam_offset_sz, 0); + PHL_INFO("\n"); + } + } else { + /* to buffer */ + if (size < addr_cam_offset_sz*num) { + PHL_ERR("%s buf size is not enough to dump addr cam\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + for (i = 0; i < num; i++) + mac_mem_dump(mac, MAC_AX_MEM_ADDR_CAM, i*addr_cam_offset_sz\ + , buf + (i*addr_cam_offset_sz), addr_cam_offset_sz, 1); + + } + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_get_tsf(struct hal_info_t *hal, u8 *port, + u32 *tsf_h, u32 *tsf_l) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + struct mac_ax_port_tsf val = {0}; + + val.port = *port; + if (hal_mac_ops->get_hw_value(mac, MAC_AX_HW_GET_TSF, &val)) + return RTW_HAL_STATUS_FAILURE; + *tsf_h = val.tsf_h; + *tsf_l = val.tsf_l; + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mac_cfg_txhci(struct hal_info_t *hal, u8 en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + enum mac_ax_func_sw mac_en; + u32 ret = 0; + + if (en) + mac_en = MAC_AX_FUNC_EN; + else + mac_en = MAC_AX_FUNC_DIS; + + ret = hal_mac_ops->intf_ops->ctrl_txhci(mac, mac_en); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS):(RTW_HAL_STATUS_FAILURE); +} + +enum rtw_hal_status rtw_hal_mac_cfg_rxhci(struct hal_info_t *hal, u8 en) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + enum mac_ax_func_sw mac_en; + u32 ret = 0; + + if (en) + mac_en = MAC_AX_FUNC_EN; + else + mac_en = MAC_AX_FUNC_DIS; + + ret = hal_mac_ops->intf_ops->ctrl_rxhci(mac, mac_en); + + return (ret == MACSUCCESS) ? + (RTW_HAL_STATUS_SUCCESS):(RTW_HAL_STATUS_FAILURE); +} + +#ifdef CONFIG_MCC_SUPPORT +void _hal_mac_mcc_fill_role_info(struct rtw_phl_mcc_role *mcc_role, + struct mac_ax_mcc_role *info) +{ + struct rtw_phl_mcc_policy_info *policy = &mcc_role->policy; + + if (mcc_role->bt_role) { + info->group = mcc_role->group; + info->btc_in_2g = true; + info->duration = policy->dur_info.dur; + } else { + info->macid = mcc_role->macid; + info->central_ch_seg0 = mcc_role->chandef->center_ch; + info->central_ch_seg1 = (u8)mcc_role->chandef->center_freq2; + info->primary_ch = mcc_role->chandef->chan; + info->bandwidth = mcc_role->chandef->bw; + info->group = mcc_role->group; + info->c2h_rpt = policy->c2h_rpt; + info->dis_tx_null = policy->dis_tx_null; + info->dis_sw_retry = policy->dis_sw_retry; + info->in_curr_ch = policy->in_curr_ch; + info->sw_retry_count = policy->sw_retry_count; + info->tx_null_early= policy->tx_null_early; + info->duration = policy->dur_info.dur; + info->courtesy_en = policy->courtesy_en; + info->courtesy_num = policy->courtesy_num; + info->courtesy_target = policy->courtesy_target; + } + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): macid(%d), central_ch_seg0(%d), central_ch_seg1(%d)\n", + info->macid, info->central_ch_seg0, info->central_ch_seg1); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): primary_ch(%d), bandwidth(%d), group(%d), c2h_rpt(%d)\n", + info->primary_ch, info->bandwidth, info->group, info->c2h_rpt); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): dis_tx_null(%d), dis_sw_retry(%d), in_curr_ch(%d)\n", + info->dis_tx_null, info->dis_sw_retry, info->in_curr_ch); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): sw_retry_count(%d), tx_null_early(%d), btc_in_2g(%d)\n", + info->sw_retry_count, info->tx_null_early, info->btc_in_2g); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): duration(%d)\n", + info->duration); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): courtesy_en(%d), courtesy_num(%d), courtesy_target(0x%x)\n", + info->courtesy_en, info->courtesy_num, info->courtesy_target); +} + +void _hal_mac_mcc_fill_duration_info(struct rtw_phl_mcc_en_info *en_info, + struct rtw_phl_mcc_bt_info *bt_info, + struct mac_ax_mcc_duration_info *info) +{ + info->group = en_info->mcc_role[0].group; + info->btc_in_group = (bt_info->bt_dur > 0) ? 1 : 0; + info->start_macid = en_info->mcc_role[en_info->ref_role_idx].macid; + info->macid_x = en_info->mcc_role[0].macid; + info->macid_y = en_info->mcc_role[1].macid; + info->duration_x = en_info->mcc_role[0].policy.dur_info.dur; + info->duration_y = en_info->mcc_role[1].policy.dur_info.dur; + info->start_tsf_low = en_info->tsf_low; + info->start_tsf_high = en_info->tsf_high; + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_duration_info(): info->group(%d), btc_in_group(%d), start_macid(%d), macid_x(%d), macid_y(%d)\n", + info->group, info->btc_in_group, info->start_macid, + info->macid_x, info->macid_y); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_duration_info(): duration_x(%d), duration_y(%d), start_tsf(0x%08x %08x)\n", + info->duration_x, info->duration_y, info->start_tsf_high, + info->start_tsf_low); +} + +void _hal_mac_mcc_fill_start_info(u8 group, u8 macid, u32 tsf_high, u32 tsf_low, + u8 btc_in_group, u8 old_group_action, u8 old_group, + struct mac_ax_mcc_start *info) +{ + info->group = group; + info->btc_in_group = btc_in_group; + info->old_group_action = old_group_action; + info->old_group = old_group; + info->macid = macid; + info->tsf_low = tsf_low; + info->tsf_high = tsf_high; + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_start_info(): info->group(%d), btc_in_group(%d), old_group_action(%d), old_group(%d), macid(%d), Tsf(0x%08x %08x)\n", + info->group, info->btc_in_group, info->old_group_action, + info->old_group, info->macid, info->tsf_high, info->tsf_low); +} + +enum rtw_hal_status rtw_hal_mac_add_mcc(struct hal_info_t *hal, + struct rtw_phl_mcc_role *mcc_role) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + struct mac_ax_mcc_role info = {0}; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_add_mcc()\n"); + if (mac == NULL) + goto exit; + _hal_mac_mcc_fill_role_info(mcc_role, &info); + mac_status = mac->ops->add_mcc(mac, &info); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_add_mcc(): fault, status = %d.\n", + mac_status); + goto exit; + } + do { + if (mac->ops->check_add_mcc_done(mac, (u8)info.group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_add_mcc(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_add_mcc(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_start_mcc(struct hal_info_t *hal, + u8 group, u8 macid, u32 tsf_high, u32 tsf_low, + u8 btc_in_group, u8 old_group_action, u8 old_group) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_mcc_start info = {0}; + u32 mac_status = MACSUCCESS; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_start_mcc(): group(%d), macid(%d) Start tsf(0x%08X %08X), btc_in_group(%d)\n", + group, macid, tsf_high, tsf_low, btc_in_group); + if (mac == NULL) + goto exit; + _hal_mac_mcc_fill_start_info(group, macid, tsf_high, tsf_low, + btc_in_group, old_group_action, + old_group, &info); + mac_status = mac->ops->start_mcc(mac, &info); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_start_mcc(): fault, status = %d.\n", + mac_status); + goto exit; + } + do { + if (mac->ops->check_start_mcc_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_start_mcc(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_start_mcc(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_stop_mcc(struct hal_info_t *hal, u8 group, + u8 macid) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_stop_mcc(): group(%d), macid(%d)\n", + group, macid); + if (mac == NULL) + goto exit; + /*prev_groups always set to 1, driver stop all group pattern in the same hw band.*/ + mac_status = mac->ops->stop_mcc(mac, group, macid, 1); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_stop_mcc(): fault, status = %d.\n", + mac_status); + goto exit; + } + do { + if (mac->ops->check_stop_mcc_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_stop_mcc(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_stop_mcc(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_del_mcc_group(struct hal_info_t *hal, u8 group) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_del_mcc_group(): group(%d)\n", + group); + if (mac == NULL) + goto exit; + /*prev_groups always set to 1, driver stop all group pattern in the same hw band.*/ + mac_status = mac->ops->del_mcc_group(mac, group, 1); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_del_mcc_group(): fault, status = %d.\n", + mac_status); + goto exit; + } + + do { + if (mac->ops->check_del_mcc_group_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_del_mcc_group(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_del_mcc_group(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_mcc_request_tsf(struct hal_info_t *hal, + u8 group, u8 macid_x, u8 macid_y) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_request_tsf(): group(%d), macid_x(%d), macid_y(%d)\n", + group, macid_x, macid_y); + if (mac == NULL) + goto exit; + mac_status = mac->ops->mcc_request_tsf(mac, group, macid_x, macid_y); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_request_tsf(): fault, status = %d.\n", + mac_status); + goto exit; + } + + do { + if (mac->ops->check_mcc_request_tsf_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_mcc_request_tsf(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_request_tsf(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_mcc_macid_bitmap(struct hal_info_t *hal, + u8 group, u8 macid, u8 *bitmap, u8 len) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_macid_bitmap(): group(%d), macid(%d)\n", + group, macid); + if (mac == NULL) + goto exit; + mac_status = mac->ops->mcc_macid_bitmap(mac, group, macid, bitmap, len); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_macid_bitmap(): fault, status = %d.\n", + mac_status); + goto exit; + } + + do { + if (mac->ops->check_mcc_macid_bitmap_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_mcc_macid_bitmap(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_macid_bitmap(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_mcc_sync_enable(struct hal_info_t *hal, + u8 group, u8 source, u8 target, u8 offset) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_sync_enable(): group(%d), source macid(%d), target macid(%d), offset(%d)\n", + group, source, target, offset); + if (mac == NULL) + goto exit; + mac_status = mac->ops->mcc_sync_enable(mac, group, source, target, offset); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): fault, status = %d.\n", + mac_status); + goto exit; + } + do { + if (mac->ops->check_mcc_sync_enable_done(mac, group) == + MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "mac_mcc_sync_enable(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): polling timeout\n"); + } +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_set_duration(struct hal_info_t *hal, + struct rtw_phl_mcc_en_info *en_info, + struct rtw_phl_mcc_bt_info *bt_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_mcc_duration_info info = {0}; + u32 mac_status; + u16 loop_cnt = 0; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_set_duration()\n"); + _hal_mac_mcc_fill_duration_info(en_info, bt_info, &info); + mac_status = mac->ops->mcc_set_duration(mac, &info); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_set_duration(): fault, status = %d.\n", + mac_status); + goto exit; + } + do { + if (mac->ops->check_mcc_set_duration_done(mac, (u8)info.group) + == MACSUCCESS) + break; + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + loop_cnt++; + } while (loop_cnt < POLLING_HALMAC_CNT); + + if (loop_cnt < POLLING_HALMAC_CNT) { + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_set_duration(): polling ok, count(%d)\n", + loop_cnt); + hal_status = RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_set_duration(): polling timeout\n"); + } +exit: + return hal_status; + +} + +enum rtw_hal_status rtw_hal_mac_get_mcc_tsf_rpt(struct hal_info_t *hal, + u8 group, u32 *tsf_x_h, u32 *tsf_x_l, + u32 *tsf_y_h, u32 *tsf_y_l) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + + if (mac == NULL) + goto exit; + mac_status = mac->ops->get_mcc_tsf_rpt(mac, group, tsf_x_h, tsf_x_l, + tsf_y_h, tsf_y_l); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_get_mcc_tsf_rpt(): fault, status = %d.\n", + mac_status); + goto exit; + } + hal_status = RTW_HAL_STATUS_SUCCESS; +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_get_mcc_status_rpt(struct hal_info_t *hal, + u8 group, u8 *status, u32 *tsf_h, u32 *tsf_l) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + + if (mac == NULL) + goto exit; + mac_status = mac->ops->get_mcc_status_rpt(mac, group, status, tsf_h, + tsf_l); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): fault, status = %d.\n", + mac_status); + goto exit; + } + hal_status = RTW_HAL_STATUS_SUCCESS; +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mac_get_mcc_group(struct hal_info_t *hal, u8 *group) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status; + + if (mac == NULL) + goto exit; + mac_status = mac->ops->get_mcc_group(mac, group); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_get_mcc_group(): fault, status = %d.\n", + mac_status); + goto exit; + } + hal_status = RTW_HAL_STATUS_SUCCESS; +exit: + return hal_status; +} +#endif /* CONFIG_MCC_SUPPORT */ + +#ifdef CONFIG_PHL_P2PPS +#define P2P_ACT_INIT 0 +#define P2P_ACT_UPDATE 1 +#define P2P_ACT_REMOVE 2 +#define P2P_ACT_TERMINATE 3 + +#define P2P_TYPE_GO 0 +#define P2P_TYPE_GC 1 + +void _hal_mac_dump_p2p_act_struct(struct mac_ax_p2p_act_info *mac_p2p_info) +{ + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): macid = %d\n", + mac_p2p_info->macid); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): noaid = %d\n", + mac_p2p_info->noaid); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): act = %d\n", + mac_p2p_info->act); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): type = %d\n", + mac_p2p_info->type); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): all_slep = %d\n", + mac_p2p_info->all_slep); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): srt = %x\n", + mac_p2p_info->srt); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): itvl = %d\n", + mac_p2p_info->itvl); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): dur = %d\n", + mac_p2p_info->dur); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): cnt = %d\n", + mac_p2p_info->cnt); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): ctw = %d\n", + mac_p2p_info->ctw); +} + +void _hal_mac_noa_fill_info(u8 action, + struct rtw_phl_noa_desc *desc, + u16 macid, + struct mac_ax_p2p_act_info *mac_p2p_info) +{ + struct rtw_wifi_role_t *wrole = desc->w_role; + + mac_p2p_info->macid = (u8)macid; + mac_p2p_info->noaid = desc->noa_id; + mac_p2p_info->act = action; + if (wrole->type == PHL_RTYPE_AP) + mac_p2p_info->type = P2P_TYPE_GO; + else if (wrole->type == PHL_RTYPE_STATION) + mac_p2p_info->type = P2P_TYPE_GC; + mac_p2p_info->srt = desc->start_t_l; + mac_p2p_info->itvl = desc->interval; + mac_p2p_info->dur = desc->duration; + mac_p2p_info->cnt = desc->count; +} + +enum rtw_hal_status _hal_mac_get_p2p_stat(struct hal_info_t *hal) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + u16 loop_cnt; + u32 m_stat; + + for (loop_cnt = 0; loop_cnt < POLLING_HALMAC_CNT; loop_cnt++) { + m_stat = mac->ops->get_p2p_stat(mac) ; + if (m_stat == MACSUCCESS) { + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_get_p2p_stat(): polling ok, count(%d)\n", + loop_cnt); + return RTW_HAL_STATUS_SUCCESS; + } else if (m_stat == MACP2PSTFAIL) { + PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_get_p2p_stat(): polling error, count(%d)\n", + loop_cnt); + return RTW_HAL_STATUS_FAILURE; + } + _os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME); + } + PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_get_p2p_stat(): polling timeout!\n"); + return RTW_HAL_STATUS_FAILURE; +} + + +enum rtw_hal_status _hal_mac_set_p2p_act(struct hal_info_t *hal, + struct mac_ax_p2p_act_info *mac_p2p_info) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 m_stat; + + m_stat = mac->ops->p2p_act_h2c(mac, mac_p2p_info); + if (m_stat != MACSUCCESS) { + PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_set_noa_act(): Fault, status = %d, Action = %d\n", + m_stat, mac_p2p_info->act); + return RTW_HAL_STATUS_MAC_API_FAILURE; + } + h_stat = _hal_mac_get_p2p_stat(hal); + return h_stat; +} + +enum rtw_hal_status rtw_hal_mac_noa_init(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_p2p_act_info mac_p2p_info = {0}; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_init()\n"); + _hal_mac_noa_fill_info(P2P_ACT_INIT, in_desc, macid, &mac_p2p_info); + _hal_mac_dump_p2p_act_struct(&mac_p2p_info); + h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info); + return h_stat; +} + +enum rtw_hal_status rtw_hal_mac_noa_update(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_p2p_act_info mac_p2p_info = {0}; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_update()\n"); + _hal_mac_noa_fill_info(P2P_ACT_UPDATE, in_desc, macid, &mac_p2p_info); + _hal_mac_dump_p2p_act_struct(&mac_p2p_info); + h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info); + return h_stat; +} + +enum rtw_hal_status rtw_hal_mac_noa_remove(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_p2p_act_info mac_p2p_info = {0}; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_remove()\n"); + _hal_mac_noa_fill_info(P2P_ACT_REMOVE, in_desc, macid, &mac_p2p_info); + _hal_mac_dump_p2p_act_struct(&mac_p2p_info); + h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info); + return h_stat; + +} + +enum rtw_hal_status rtw_hal_mac_noa_terminate(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_p2p_act_info mac_p2p_info = {0}; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_terminate()\n"); + _hal_mac_noa_fill_info(P2P_ACT_TERMINATE, in_desc, macid, &mac_p2p_info); + _hal_mac_dump_p2p_act_struct(&mac_p2p_info); + h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info); + return h_stat; + +} + +enum rtw_hal_status rtw_hal_mac_tsf32_tog_enable(struct hal_info_t *hal, + u8 hw_band, + u8 port, + u16 early) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_t32_togl_info mac_t32_tog_info = {0}; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 m_stat; + + mac_t32_tog_info.band = hw_band; + mac_t32_tog_info.port = port; + mac_t32_tog_info.en = true; + mac_t32_tog_info.early = early; + m_stat = mac->ops->tsf32_togl_h2c(mac, &mac_t32_tog_info); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_tsf32_tog_enable() m_stat = %d\n", + m_stat); + if(m_stat == MACSUCCESS) + h_stat = RTW_HAL_STATUS_SUCCESS; + return h_stat; +} + +enum rtw_hal_status rtw_hal_mac_tsf32_tog_disable(struct hal_info_t *hal, + u8 hw_band, + u8 port) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct mac_ax_t32_togl_info mac_t32_tog_info = {0}; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 m_stat; + + mac_t32_tog_info.band = hw_band; + mac_t32_tog_info.port = port; + mac_t32_tog_info.en = false; + m_stat = mac->ops->tsf32_togl_h2c(mac, &mac_t32_tog_info); + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_tsf32_tog_disable() m_stat = %d\n", + m_stat); + if(m_stat == MACSUCCESS) + h_stat = RTW_HAL_STATUS_SUCCESS; + return h_stat; +} + +enum rtw_hal_status rtw_hal_mac_get_tsf32_tog_rpt(struct hal_info_t *hal, + struct rtw_phl_tsf32_tog_rpt *rpt) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_t32_togl_rpt m_rpt = {0}; + u32 m_stat = 0; + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_get_tsf32_tog_rpt()\n"); + m_stat = mac->ops->get_t32_togl_rpt(mac, &m_rpt); + if (m_stat != MACSUCCESS) { + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_get_tsf32_tog_rpt() MAC FAIL(%d)!\n", + m_stat); + return RTW_HAL_STATUS_FAILURE; + } + rpt->band = m_rpt.band; + rpt->port = m_rpt.port; + rpt->valid = m_rpt.valid; + rpt->early = m_rpt.early; + rpt->status = m_rpt.status; + rpt->tsf_l = m_rpt.tsf_l; + rpt->tsf_h = m_rpt.tsf_h; + return RTW_HAL_STATUS_SUCCESS; +} +#endif +void rtw_hal_mac_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + u8 band) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + mac->ops->event_notify(mac, event, band); +} + +void rtw_hal_mac_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + u8 band) +{ + /*todo*/ +} + +enum rtw_hal_status +rtw_hal_mac_trigger_fw_conflict(struct hal_info_t *hal_info, u32 addr, u8 vol) +{ + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 i = 0; + u32 convert_mask = 0xffffffff; + u32 val; + + /* Switch voltage */ + mac->ops->set_hw_value(mac, MAC_AX_HW_SET_CORE_SWR_VOLT, &vol); + + /* Trigger method: H2C Halt */ + hal_ops->write_macreg(hal_info, 0x168, convert_mask, 0x5dc0007); + hal_ops->write_macreg(hal_info, 0x160, convert_mask, 0x1); + + /* loop read reg */ + for(i = 0; i<1000; i++){ + val = hal_ops->read_macreg(hal_info, + addr, + convert_mask); + PHL_INFO("%s: voltag %d count %d io_value = %x\n", __FUNCTION__,vol, i, val); + } + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_mac_set_gpio_func(struct rtw_hal_com_t *hal_com, u8 func, s8 gpio_cfg){ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + struct mac_ax_ops *ops = mac->ops; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = ops->set_gpio_func(mac, func, gpio_cfg); + + if (ret != MACSUCCESS) + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set GPIO failure, status = %d\n", ret); + + return ret; +} + +enum rtw_hal_status +rtw_hal_mac_bfee_set_vht_gid(struct hal_info_t *hal, + u8 band, struct rtw_phl_gid_pos_tbl *tbl) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct mac_gid_pos gid_pos = {0}; + struct mac_ax_adapter *mac = hal_to_mac(hal); + u32 mac_status = 0; + u8 i = 0; + + gid_pos.band = band; + /* For GID 0~31 */ + for (i = 0; i < 4; i++) { + gid_pos.gid_tab[0] |= (tbl->gid_vld[i] << (i << 3)); + } + + for (i = 0; i < 8; i++) { + if (i < 4) + gid_pos.user_pos[0] |= (tbl->pos[i] << (i << 3)); + else + gid_pos.user_pos[1] |= (tbl->pos[i] << ((i - 4) << 3)); + } + /* For GID 32~64 */ + for (i = 4; i < 8; i++) { + gid_pos.gid_tab[1] |= (tbl->gid_vld[i] << ((i - 4) << 3)); + } + for (i = 8; i < 16; i++) { + if (i < 12) + gid_pos.user_pos[2] |= (tbl->pos[i] << ((i - 8) << 3)); + else + gid_pos.user_pos[3] |= (tbl->pos[i] << ((i - 12) << 3)); + } + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : Set VHT GID for band %d;\n", + __func__, band); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : band %d ; gid tbl 0x%x 0x%x;\n", + __func__, band, + gid_pos.gid_tab[0], gid_pos.gid_tab[1]); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : user position 0x%x 0x%x 0x%x 0x%x;\n", + __func__, + gid_pos.user_pos[0], gid_pos.user_pos[1], + gid_pos.user_pos[2], gid_pos.user_pos[3]); + + mac_status = mac->ops->gidpos(mac, &gid_pos); + if (mac_status != MACSUCCESS) { + hal_status = RTW_HAL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n", + __func__, mac_status); + } + + return hal_status; +} + +/* acq_val/mgq_val , input unit : us */ +enum rtw_hal_status +rtw_hal_mac_set_tx_lifetime(struct hal_info_t *hal, enum phl_band_idx band, + bool acq_en, bool mgq_en, u16 acq_val, u16 mgq_val) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_lifetime_cfg cfg = {0}; + u32 mac_status = 0; + u16 tmp = 0; +#define HAL_MAC_TX_LIFETIME_UNIT_US_SHT 8 /* 256 us */ + + if (HW_BAND_1 == band) + cfg.band = 1; + else + cfg.band = 0; + + if(true == acq_en) { + cfg.en.acq_en = 1; + tmp = acq_val >> HAL_MAC_TX_LIFETIME_UNIT_US_SHT; + cfg.val.acq_val_1 = tmp; + cfg.val.acq_val_2 = tmp; + cfg.val.acq_val_3 = tmp; + cfg.val.acq_val_4 = tmp; + } + + if (true == mgq_en) { + cfg.en.mgq_en = 1; + tmp = mgq_val >> HAL_MAC_TX_LIFETIME_UNIT_US_SHT; + cfg.val.mgq_val = tmp; + } + + mac_status = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_LIFETIME_CFG, (void *)&cfg); + + if (mac_status != MACSUCCESS) { + hal_status = RTW_HAL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n", + __func__, mac_status); + } + + return hal_status; +} + +#ifdef CONFIG_FW_IO_OFLD_SUPPORT +enum rtw_hal_status rtw_hal_mac_add_cmd_ofld(struct rtw_hal_com_t *hal_com, struct rtw_mac_cmd *cmd) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u32 mac_status; + + if (mac == NULL) + goto exit; + mac_status = mac->ops->add_cmd_ofld(mac, cmd); + if (mac_status != MACSUCCESS) { + PHL_TRACE(COMP_PHL_MAC, _PHL_ERR_, "%s(): fault, status = %d.\n", + __func__, mac_status); + goto exit; + } + hal_status = RTW_HAL_STATUS_SUCCESS; +exit: + return hal_status; +} +#endif + + +enum rtw_hal_status rtw_hal_mac_set_hw_rts_th(struct hal_info_t *hal, u8 band, + u16 time_th, u16 len_th) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_hw_rts_th hw_rts_th = {0}; + u32 mac_err; + + PHL_INFO("%s\n", __func__); + _os_mem_set(hal_to_drvpriv(hal), &hw_rts_th, 0, sizeof(hw_rts_th)); + + hw_rts_th.band = band; + hw_rts_th.time_th = time_th; + hw_rts_th.len_th = len_th; + + mac_err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_HW_RTS_TH, + &hw_rts_th); + + if (mac_err != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, mac_err); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +u8 rtw_hal_mac_get_efuse_ver_len(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + + return mac->hw_info->efuse_version_size; +} + + +enum rtw_hal_status +rtw_hal_mac_set_dfs_tb_ctrl(struct hal_info_t *hal_info, u8 set) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + u8 dis_ru_26 = 0; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + if (set) + dis_ru_26 = 1; + ret = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_TX_RU26_TB, &dis_ru_26); + if (ret != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, ret); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_mac_patch_rx_rate(struct hal_info_t *hal_info, struct rtw_r_meta_data *mdata) +{ + struct mac_ax_adapter *mac = hal_to_mac(hal_info); + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = mac->ops->patch_rx_rate(mac, mdata); + if (ret != MACSUCCESS) { + PHL_ERR("%s : mac status %d.\n", __func__, ret); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +/** + * rtw_hal_mac_set_tx_duty() - Set tx pause/un-pause interval + * @hal_info: struct hal_info_t* + * @pause_interval: tx pause interval (ms) + * @tx_interval: tx interval (ms) + * + * Return RTW_HAL_STATUS_SUCCESS when operation success. + */ +enum rtw_hal_status +rtw_hal_mac_set_tx_duty(struct hal_info_t *hal_info, + u16 pause_interval, + u16 tx_interval) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 mac_status = 0; + + mac_status = mac->ops->tx_duty(mac, pause_interval, tx_interval); + if (mac_status != MACSUCCESS) { + hal_status = RTW_HAL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n", + __func__, mac_status); + } + + return hal_status; +} + +/** + * rtw_hal_mac_stop_tx_duty() - Stop previous tx duty config + * @hal_info: struct hal_info_t* + * + * Return RTW_HAL_STATUS_SUCCESS when operation success. + */ +enum rtw_hal_status +rtw_hal_mac_stop_tx_duty(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac; + u32 mac_status = 0; + + mac_status = mac->ops->tx_duty_stop(mac); + if (mac_status != MACSUCCESS) { + hal_status = RTW_HAL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n", + __func__, mac_status); + } + + return hal_status; +} \ No newline at end of file diff --git a/phl/hal_g6/hal_api_mac.h b/phl/hal_g6/hal_api_mac.h new file mode 100644 index 0000000..dcaeb8f --- /dev/null +++ b/phl/hal_g6/hal_api_mac.h @@ -0,0 +1,658 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_MAC_H_ +#define _HAL_API_MAC_H_ +#include "mac/mac_ax.h" + + +#define POLLING_HALMAC_TIME 5 +#define POLLING_HALMAC_CNT 100 + +#define hal_to_mac(_halinfo) ((struct mac_ax_adapter *)((_halinfo)->mac)) + +#ifdef CONFIG_SDIO_HCI +u8 hal_mac_sdio_read8(struct rtw_hal_com_t *hal, u32 addr); +u16 hal_mac_sdio_read16(struct rtw_hal_com_t *hal, u32 addr); +u32 hal_mac_sdio_read32(struct rtw_hal_com_t *hal, u32 addr); +int hal_mac_sdio_write8(struct rtw_hal_com_t *hal, u32 addr, u8 value); +int hal_mac_sdio_write16(struct rtw_hal_com_t *hal, u32 addr, u16 value); +int hal_mac_sdio_write32(struct rtw_hal_com_t *hal, u32 addr, u32 value); +void hal_mac_sdio_read_mem(struct rtw_hal_com_t *hal, + u32 addr, u32 cnt, u8 *pmem); + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 hal_mac_sdio_iread8(struct rtw_hal_com_t *hal, u32 addr); +u16 hal_mac_sdio_iread16(struct rtw_hal_com_t *hal, u32 addr); +u32 hal_mac_sdio_iread32(struct rtw_hal_com_t *hal, u32 addr); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ + +#endif /* CONFIG_SDIO_HCI */ + +void rtw_hal_mac_get_version(char *ver_str, u16 len); +void rtw_hal_mac_get_fw_ver(struct hal_info_t *hal_info, char *ver_str, u16 len); + +u16 hal_mac_get_macid_num(struct hal_info_t *hal); +void hal_mac_get_hwinfo(struct hal_info_t *hal, struct hal_spec_t *hal_spec); + +#ifdef DBG_PHL_MAC_REG_RW +bool rtw_hal_mac_reg_chk(struct rtw_hal_com_t *hal_com, u32 addr); +#endif + +u32 rtw_hal_mac_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +u32 rtw_hal_mac_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +bool rtw_hal_mac_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd, + char *output, u32 out_len); + +enum rtw_hal_status rtw_hal_mac_get_pwr_state(struct hal_info_t *hal_info, + enum rtw_mac_pwr_st *pwr_state); + +enum rtw_hal_status rtw_hal_mac_power_switch(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 on_off); + +enum rtw_hal_status rtw_hal_mac_dbcc_pre_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 dbcc_en); +enum rtw_hal_status rtw_hal_mac_dbcc_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + u8 dbcc_en); +enum rtw_hal_status +rtw_hal_mac_poll_hw_tx_done(struct hal_info_t *hal_info); +enum rtw_hal_status +rtw_hal_mac_hw_tx_resume(struct hal_info_t *hal_info); +enum rtw_hal_status +rtw_hal_mac_poll_hw_rx_done(struct hal_info_t *hal_info); +enum rtw_hal_status +rtw_hal_mac_hw_rx_resume(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_mac_watchdog(struct hal_info_t *hal_info); +#ifdef CONFIG_PCI_HCI +enum rtw_hal_status rtw_hal_mac_set_pcicfg(struct hal_info_t *hal_info, + struct mac_ax_pcie_cfgspc_param *pci_cfgspc); +enum rtw_hal_status rtw_hal_mac_ltr_set_pcie(struct hal_info_t *hal_info, + enum rtw_pcie_bus_func_cap_t hw_ctrl, + u8 idle_ctrl, u32 idle_val, u8 act_ctrl, u32 act_val); + +enum rtw_hal_status rtw_hal_mac_ltr_sw_trigger(struct hal_info_t *hal_info, enum rtw_pcie_ltr_state state); +enum rtw_hal_status hal_mac_set_l2_leave(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_mac_poll_txdma_idle(struct hal_info_t *hal, + struct mac_ax_txdma_ch_map *ch_map); + +enum rtw_hal_status rtw_hal_mac_poll_rxdma_idle(struct hal_info_t *hal, + struct mac_ax_rxdma_ch_map *ch_map); + +enum rtw_hal_status rtw_hal_mac_clr_bdidx(struct hal_info_t *hal); + +enum rtw_hal_status rtw_hal_mac_rst_bdram(struct hal_info_t *hal); + +enum rtw_hal_status rtw_hal_mac_cfg_txdma(struct hal_info_t *hal, + struct mac_ax_txdma_ch_map *ch_map); + +enum rtw_hal_status rtw_hal_mac_cfg_dma_io(struct hal_info_t *hal, u8 en); + +#endif + + +#ifdef CONFIG_USB_HCI +u8 hal_mac_get_bulkout_id(struct hal_info_t *hal, u8 ch_dma, u8 mode); +u32 hal_mac_usb_tx_agg_cfg(struct hal_info_t *hal, u8* wd_buf, u8 agg_num); +u32 hal_mac_usb_rx_agg_cfg(struct hal_info_t *hal, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num); +u8 hal_mac_usb_get_max_bulkout_wd_num(struct hal_info_t *hal); +enum rtw_hal_status hal_mac_force_usb_switch(struct hal_info_t *hal); +u32 hal_mac_get_cur_usb_mode(struct hal_info_t *hal); +u32 hal_mac_get_usb_support_ability(struct hal_info_t *hal); +#endif + +#ifdef CONFIG_SDIO_HCI +void rtw_hal_mac_sdio_cfg(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, struct rtw_ic_info *ic_info); +void rtw_hal_mac_sdio_tx_cfg(struct rtw_hal_com_t *hal); +void rtw_hal_mac_sdio_rx_agg_cfg(struct rtw_hal_com_t *hal, bool enable, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num); +bool rtw_hal_mac_sdio_check_tx_allow(struct rtw_hal_com_t *hal, u8 dma_ch, + u8 *buf, u32 len, u8 agg_count, + u16 *pkt_len, u8 *wp_offset, u32 *txaddr, + u32 *txlen); +int rtw_hal_mac_sdio_parse_rx(struct rtw_hal_com_t *hal, + struct rtw_rx_buf *rxbuf); +int rtw_hal_mac_sdio_rx(struct rtw_hal_com_t *hal, + struct rtw_rx_buf *rxbuf); +#endif + +struct hal_init_info_t { + struct mac_ax_trx_info trx_info; + struct mac_ax_intf_info intf_info; + char *ic_name; +}; +enum rtw_hal_status +rtw_hal_mac_init_mac(void *mac, struct hal_init_info_t *init_info); + +enum rtw_hal_status +rtw_hal_mac_trx_init(void *mac, struct hal_init_info_t *init_info); + +enum rtw_hal_status +rtw_hal_mac_hal_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info); + +enum rtw_hal_status +rtw_hal_mac_hal_fast_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info); + +enum rtw_hal_status +rtw_hal_mac_hal_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_mac_chk_allq_empty(struct hal_info_t *hal_info, u8 *empty); + +#ifdef CONFIG_WOWLAN +enum rtw_hal_status +rtw_hal_mac_cfg_wow_sleep(struct hal_info_t *hal_info, u8 sleep); +enum rtw_hal_status +rtw_hal_mac_get_wow_fw_status(struct hal_info_t *hal_info, u8 *status, u8 func_en); + +enum rtw_hal_status +rtw_hal_mac_cfg_wow_wake(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_wow_wake_info *info); + +enum rtw_hal_status +rtw_hal_mac_cfg_disc_dec(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_disc_det_info *info); + +enum rtw_hal_status +rtw_hal_mac_cfg_dev2hst_gpio(struct hal_info_t *hal_info, u8 en, struct rtw_wow_gpio_info *cfg); + +enum rtw_hal_status +rtw_hal_mac_cfg_keep_alive(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_keep_alive_info *info); + +enum rtw_hal_status +rtw_hal_mac_cfg_ndp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_ndp_ofld_info *cfg); + +enum rtw_hal_status +rtw_hal_mac_cfg_arp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_arp_ofld_info *cfg); + +enum rtw_hal_status +rtw_hal_mac_cfg_gtk_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_gtk_ofld_info *cfg); + +enum rtw_hal_status +rtw_hal_mac_cfg_realwow(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_realwow_info *cfg); + +enum rtw_hal_status rtw_hal_mac_get_wake_rsn(struct hal_info_t *hal_info, u8 *wake_rsn, u8 *reset); + +enum rtw_hal_status +rtw_hal_mac_cfg_wow_cam(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_pattern_match_info *cfg); + +enum rtw_hal_status +rtw_hal_mac_get_aoac_rpt(struct hal_info_t *hal_info, struct rtw_aoac_report *aoac_info, u8 rx_ready); + +enum rtw_hal_status rtw_hal_mac_set_wowlan(struct hal_info_t *hal, u8 enter); +enum rtw_hal_status rtw_hal_mac_wow_chk_txq_empty(struct hal_info_t *hal, u8 *empty); +enum rtw_hal_status rtw_hal_mac_wow_wde_drop(struct hal_info_t *hal, u8 band); + +#endif /* CONFIG_WOWLAN */ + +enum rtw_hal_status +rtw_hal_mac_ax_fill_txdesc(void *mac, struct rtw_xmit_req *treq, + u8 *wd_buf, u32 *wd_len); + +enum rtw_hal_status +rtw_hal_mac_enable_cpu(struct hal_info_t *hal_info, u8 reason, u8 dlfw); + +enum rtw_hal_status +rtw_hal_mac_disable_cpu(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_mac_romdl(struct hal_info_t *hal_info, u8 *rom_buf, u32 rom_size); + +enum rtw_hal_status +rtw_hal_mac_fwdl(struct hal_info_t *hal_info, u8 *fw_buf, u32 fw_size); + +enum rtw_hal_status +rtw_hal_mac_enable_fw(struct hal_info_t *hal_info, u8 fw_type); + +enum rtw_hal_status +rtw_hal_mac_set_hw_ampdu_cfg(struct hal_info_t *hal_info, u8 band, + u16 max_agg_num, u8 max_agg_time); + +enum rtw_hal_status rtw_hal_dmc_tbl_cfg(struct hal_info_t *hal_info, + struct mac_ax_dctl_info *dctl_info, + struct mac_ax_dctl_info *dctl_info_mask, + u16 macid); + +enum rtw_hal_status rtw_hal_cmc_tbl_cfg(struct hal_info_t *hal_info, + struct mac_ax_cctl_info *cctl_info, + struct mac_ax_cctl_info *cctl_info_mask, + u16 macid); + +enum rtw_hal_status rtw_hal_bacam_cfg(struct hal_info_t *hal_info, + struct mac_ax_bacam_info *ba_cam); + +enum rtw_hal_status +rtw_hal_mac_port_init(struct hal_info_t *hal_info, + struct rtw_wifi_role_t *wifi_role); + +enum rtw_hal_status +rtw_hal_mac_port_cfg(struct hal_info_t *hal_info, + struct rtw_wifi_role_t *wifi_role, + enum pcfg_type type, void *param); + +enum rtw_hal_status +rtw_hal_mac_role_sync(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_mac_addr_cam_add_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status +rtw_hal_mac_addr_cam_change_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, + enum phl_upd_mode mode, + bool is_connect); +enum rtw_hal_status +rtw_hal_mac_addr_cam_del_entry(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_mac_add_key(struct hal_info_t *hal_info, u8 macid, u8 type, u8 ext_key, + u8 spp, u8 keyid, u8 keytype, u8 *keybuf); +enum rtw_hal_status +rtw_hal_mac_delete_key(struct hal_info_t *hal_info, u8 macid, u8 type, + u8 ext_key, u8 spp, u8 keyid, u8 keytype); + +u32 +rtw_hal_mac_search_key_idx(struct hal_info_t *hal_info, u8 macid, u8 keyid, u8 keytype); + +u32 +rtw_hal_mac_ser_reset_wdt_intr(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_mac_ser_get_error_status(struct hal_info_t *hal_info, u32 *err); + +enum rtw_hal_status +rtw_hal_mac_ser_set_error_status(struct hal_info_t *hal_info, enum RTW_PHL_SER_RCVY_STEP err); + +enum rtw_hal_status +rtw_hal_mac_trigger_cmac_err(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_mac_trigger_dmac_err(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_mac_lv1_rcvy(struct hal_info_t *hal_info, enum rtw_phl_ser_lv1_recv_step step); + +enum rtw_hal_status rtw_hal_mac_ser_ctrl(struct hal_info_t *hal_info, bool en); + +enum rtw_hal_status +rtw_hal_mac_dump_fw_rsvd_ple(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_mac_set_bw(struct hal_info_t *hal_info, u8 band_idx, u8 pri_ch, + u8 central_ch_seg0, u8 central_ch_seg1, enum band_type band, enum channel_width bw); + +enum rtw_hal_status +rtw_hal_mac_ax_set_bf_entry(void *mac, u8 band, u8 macid, + u8 bfee_idx, u16 txbf_idx, u16 buffer_idx); + +enum rtw_hal_status +rtw_hal_mac_ax_get_snd_sts(void *mac, u8 band, u8 bfee_idx); + +enum rtw_hal_status +rtw_hal_mac_ax_bfee_para_reg(void *mac, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_mac_ax_bfee_para_cctl(void *mac, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_mac_bfee_set_vht_gid(struct hal_info_t *hal, + u8 band, struct rtw_phl_gid_pos_tbl *tbl); + +enum rtw_hal_status +rtw_hal_mac_ax_hw_snd_control(void *mac, u8 band, u8 hw_snd_ctrl); + +enum rtw_hal_status +rtw_hal_mac_ax_mu_sta_upd(void *mac, u8 macid, u8 bfmu_idx, + enum rtw_hal_protection_type prot_type, + enum rtw_hal_ack_resp_type resp_type, u8 mugrp_bm); + +enum rtw_hal_status +rtw_hal_mac_ax_mu_decision_para(void *mac, u32 mu_thold, + bool bypass_thold, bool bypass_tp); + +enum rtw_hal_status +rtw_hal_mac_ax_set_mu_fix_mode( + void *mac, u8 gid, enum rtw_hal_protection_type prot_type, + enum rtw_hal_ack_resp_type resp_type, + bool fix_mu, bool he, bool fix_resp, bool fix_prot); + +enum rtw_hal_status +rtw_hal_mac_ax_set_mu_table_whole(void *mac, void *hal_score_tbl); + +enum rtw_hal_status +rtw_hal_mac_ax_snd_fx_cmd(void *mac, u8 *cmd_buf); + +enum rtw_hal_status +rtw_hal_mac_parse_c2h(void *hal, u8 *buf, u32 buf_len, void *c2h); + +enum rtw_hal_status +rtw_hal_mac_ax_parse_ppdu_sts(void *hal, u8 mac_valid, u8 *buf, u16 buf_l, + void *ppdu_sts, void *rx_mdata); +enum rtw_hal_status +rtw_hal_hdr_conv_cfg(struct hal_info_t *hal_info, u8 en_hdr_conv); +enum rtw_hal_status +rtw_hal_mac_enable_bb_rf(struct hal_info_t *hal_info, u8 enable); + +#ifdef RTW_PHL_BCN +enum rtw_hal_status +hal_mac_ax_config_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); + +enum rtw_hal_status +hal_mac_ax_send_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); +#endif + +enum rtw_hal_status +rtw_hal_mac_ppdu_stat_cfg(struct hal_info_t *hal_info, + u8 band_idx, bool ppdu_stat_en, + u8 appen_info, u8 filter); +enum rtw_hal_status rtw_hal_mac_config_hw_mgnt_sec( struct hal_info_t *hal_info, u8 en); +enum rtw_hal_status rtw_hal_mac_get_append_fcs(struct hal_info_t *hal_info, u8 *val); +enum rtw_hal_status rtw_hal_mac_get_acpt_icv_err(struct hal_info_t *hal_info, u8 *val); + + +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_hal_status +rtw_hal_mac_chan_info_cfg(struct hal_info_t *hal_info, + bool chinfo_en, u8 macid, + u8 mode, u8 filter, u8 sg_size); +#endif + +void rtw_hal_mac_dbg_status_dump(struct hal_info_t *hal, struct hal_mac_dbg_dump_cfg *cfg); + +#ifdef CONFIG_PHL_DFS +enum rtw_hal_status +rtw_hal_mac_dfs_rpt_cfg(struct hal_info_t *hal_info, + bool rpt_en, u8 rpt_num, u8 rpt_to); +enum rtw_hal_status +rtw_hal_mac_parse_dfs(struct hal_info_t *hal_info, + u8 *buf, u32 buf_len, struct mac_ax_dfs_rpt *dfs_rpt); +#endif /*CONFIG_PHL_DFS*/ +u32 +rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig); + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel, + u32 *addr_start, u32 *addr_end); + +enum rtw_hal_status +rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en, + u8 restart_en, u8 timeout_en, u8 timeout_val, + u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val); +enum rtw_hal_status +rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state, + u16 *la_finish_addr, bool *la_round_up, + bool *la_loss_data); + +void +rtl_hal_dump_sec_cam_tbl(struct rtw_hal_com_t *hal_com); + +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_by_mode(struct rtw_hal_com_t *hal_com, u8 band, + enum rtw_rx_fltr_mode mode); +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_acpt_crc_err(struct rtw_hal_com_t *hal_com, + u8 band, u8 enable); +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_mpdu_size(struct rtw_hal_com_t *hal_com, + u8 band, u16 size); +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_by_type(struct rtw_hal_com_t *hal_com, u8 band, + u8 type, u8 target); +enum rtw_hal_status +rtw_hal_mac_set_rxfltr_by_subtype(struct rtw_hal_com_t *hal_com, u8 band, + u8 type, u8 subtype, u8 target); + +enum rtw_hal_status +rtw_hal_mac_fw_log_cfg(struct rtw_hal_com_t *hal_com, + struct rtw_hal_fw_log_cfg *fl_cfg); + +enum rtw_hal_status rtw_hal_set_macid_pause(void *hinfo, + u16 macid, + bool pause); + +void +rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr, + u8 *buf, u32 len, u32 dbg_path); + +enum rtw_hal_status rtw_hal_mac_pkt_ofld(struct hal_info_t *hal, u8 *id, u8 op, + u8 *pkt, u16 *len); +enum rtw_hal_status rtw_hal_mac_pkt_update_ids(struct hal_info_t *hal, + struct pkt_ofld_entry *entry); + +enum rtw_hal_status rtw_hal_mac_reset_pkt_ofld_state(struct hal_info_t *hal_info); + + +enum rtw_hal_status +rtw_hal_mac_set_edca(struct rtw_hal_com_t *hal_com, + u8 band, + u8 wmm, + u8 ac, + u32 param); +enum rtw_hal_status +rtw_hal_mac_get_ampdu_cfg(struct rtw_hal_com_t *hal_com, + u8 band, + struct mac_ax_ampdu_cfg *cfg); +enum rtw_hal_status +rtw_hal_mac_set_rty_lmt(struct rtw_hal_com_t *hal_com, u8 macid, + u8 rts_lmt_sel, u8 rts_lmt_val, u8 data_lmt_sel, u8 data_lmt_val); +enum rtw_hal_status +rtw_hal_mac_is_tx_mgnt_empty(struct hal_info_t *hal_info, u8 band, u8 *st); + +enum rtw_hal_status +rtw_hal_mac_fw_dbg_dump(struct hal_info_t *hal_info, u8 is_low_pwr); +enum rtw_hal_status +rtw_hal_mac_req_pwr_state(struct hal_info_t *hal_info, u8 pwr_state); +enum rtw_hal_status +rtw_hal_mac_chk_pwr_state(struct hal_info_t *hal_info, u8 pwr_state, u32 *mac_sts); +enum rtw_hal_status +rtw_hal_mac_lps_cfg(struct hal_info_t *hal_info, + struct rtw_hal_lps_info *lps_info); +enum rtw_hal_status +rtw_hal_mac_lps_chk_leave(struct hal_info_t *hal_info, u16 macid, u32 *mac_sts); + +enum rtw_hal_status +rtw_hal_mac_lps_chk_access(struct hal_info_t *hal_info, u32 offset); + +enum rtw_hal_status +hal_mac_ax_send_fw_snd(struct hal_info_t *hal_info, + struct hal_ax_fwcmd_snd *hal_cmd); + +enum rtw_hal_status +rtw_hal_mac_tx_mode_sel(struct hal_info_t *hal_info, u8 fw_tx, u8 txop_wmm_en_bm); + +enum rtw_hal_status +rtw_hal_mac_get_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx, u8 type_idx, u32 *ret_value); +enum rtw_hal_status +rtw_hal_mac_set_reset_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx); + +#ifdef CONFIG_PHL_TWT +enum rtw_hal_status +rtw_hal_mac_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action); + +enum rtw_hal_status +rtw_hal_mac_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action); + +enum rtw_hal_status +rtw_hal_mac_twt_sta_announce(void *hal, u8 macid); +#endif /* CONFIG_PHL_TWT */ + +enum rtw_hal_status +rtw_hal_mac_ax_bfee_set_csi_rrsc(void *mac, u8 band, u32 rrsc); + +u32 rtw_hal_mac_process_c2h(void *hal, struct rtw_c2h_info *c2h); + +enum rtw_hal_status +rtw_hal_mac_f2p_test_cmd(struct hal_info_t *hal_info, + struct mp_mac_ax_f2p_test_para *info, + struct mp_mac_ax_f2p_wd *f2pwd, + struct mp_mac_ax_f2p_tx_cmd *ptxcmd, + u8 *psigb_addr); +enum rtw_hal_status +rtw_hal_mac_set_mu_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 ac, + u16 timer, u8 cw_min, u8 cw_max, u8 aifs); +enum rtw_hal_status +rtw_hal_mac_set_mu_edca_ctrl(struct rtw_hal_com_t *hal_com, + u8 band, u8 wmm, u8 set); + +enum rtw_hal_status rtw_hal_mac_led_set_ctrl_mode(struct hal_info_t *hal_info, + enum mac_ax_led_mode mode, + u8 led_id); +enum rtw_hal_status rtw_hal_mac_led_ctrl(struct hal_info_t *hal_info, u8 high, + u8 led_id); + +enum rtw_hal_status rtw_hal_mac_sw_gpio_ctrl(struct hal_info_t *hal_info, u8 high, + u8 gpio); +enum rtw_hal_status rtw_hal_mac_set_sw_gpio_mode(struct hal_info_t *hal_info, enum rtw_gpio_mode mode, + u8 gpio); + +enum rtw_hal_status rtw_hal_mac_get_wl_dis_val(struct hal_info_t *hal_info, u8 *val); + +enum rtw_hal_status +rtw_hal_mac_pcie_trx_mit(struct hal_info_t *hal_info, + struct mac_ax_pcie_trx_mitigation *mit_info); + +enum rtw_hal_status +rtw_hal_mac_tsf_sync(struct hal_info_t *hal_info, + u8 from_port, u8 to_port, enum phl_band_idx band, + s32 sync_offset_tu, enum hal_tsf_sync_act action); + +enum rtw_hal_status +rtw_hal_mac_get_sec_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size); +enum rtw_hal_status +rtw_hal_mac_get_addr_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size); + +enum rtw_hal_status rtw_hal_mac_get_tsf(struct hal_info_t *hal, u8 *port, + u32 *tsf_h, u32 *tsf_l); + +enum rtw_hal_status rtw_hal_mac_cfg_txhci(struct hal_info_t *hal,u8 en); + +enum rtw_hal_status rtw_hal_mac_cfg_rxhci(struct hal_info_t *hal,u8 en); + +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status rtw_hal_mac_add_mcc(struct hal_info_t *hal, + struct rtw_phl_mcc_role *mcc_role); + +enum rtw_hal_status rtw_hal_mac_start_mcc(struct hal_info_t *hal, + u8 group, u8 macid, u32 tsf_high, u32 tsf_low, u8 btc_in_group, + u8 old_group_action, u8 old_group); + +enum rtw_hal_status rtw_hal_mac_stop_mcc(struct hal_info_t *hal, u8 group, + u8 macid); + +enum rtw_hal_status rtw_hal_mac_del_mcc_group(struct hal_info_t *hal, u8 group); + +enum rtw_hal_status rtw_hal_mac_mcc_request_tsf(struct hal_info_t *hal, + u8 group, u8 macid_x, u8 macid_y); + +enum rtw_hal_status rtw_hal_mac_mcc_macid_bitmap(struct hal_info_t *hal, + u8 group, u8 macid, u8 *bitmap, u8 len); + +enum rtw_hal_status rtw_hal_mac_mcc_sync_enable(struct hal_info_t *hal, + u8 group, u8 source, u8 target, u8 offset); + +enum rtw_hal_status rtw_hal_mac_set_duration(struct hal_info_t *hal, + struct rtw_phl_mcc_en_info *en_info, + struct rtw_phl_mcc_bt_info *bt_info); + +enum rtw_hal_status rtw_hal_mac_get_mcc_tsf_rpt(struct hal_info_t *hal, + u8 group, u32 *tsf_x_h, u32 *tsf_x_l, + u32 *tsf_y_h, u32 *tsf_y_l); + +enum rtw_hal_status rtw_hal_mac_get_mcc_status_rpt(struct hal_info_t *hal, + u8 group, u8 *status, u32 *tsf_h, u32 *tsf_l); + +enum rtw_hal_status rtw_hal_mac_get_mcc_group(struct hal_info_t *hal, u8 *group); +#endif /* CONFIG_MCC_SUPPORT */ +void rtw_hal_mac_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + u8 band); + +void rtw_hal_mac_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + u8 band); + +enum rtw_hal_status rtw_hal_mac_set_hw_rts_th(struct hal_info_t *hal, u8 band, + u16 time_th, u16 len_th); + +enum rtw_hal_status rtw_hal_mac_set_dfs_tb_ctrl(struct hal_info_t *hal, u8 set); + +enum rtw_hal_status +rtw_hal_mac_trigger_fw_conflict(struct hal_info_t *hal_com, u32 addr, u8 vol); + +u8 rtw_hal_mac_get_efuse_ver_len(struct rtw_hal_com_t *hal_com); + +#ifdef CONFIG_PHL_P2PPS +enum rtw_hal_status rtw_hal_mac_noa_init(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_mac_noa_update(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_mac_noa_remove(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_mac_noa_terminate(struct hal_info_t *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid); + +enum rtw_hal_status rtw_hal_mac_tsf32_tog_enable(struct hal_info_t *hal, + u8 hw_band, + u8 port, + u16 early); + +enum rtw_hal_status rtw_hal_mac_tsf32_tog_disable(struct hal_info_t *hal, + u8 hw_band, + u8 port); + +enum rtw_hal_status rtw_hal_mac_get_tsf32_tog_rpt(struct hal_info_t *hal, + struct rtw_phl_tsf32_tog_rpt *rpt); + +#endif +enum rtw_hal_status +rtw_hal_mac_addr_cam_set_aid(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta, + u16 aid); + +enum rtw_hal_status +rtw_hal_mac_set_tx_lifetime(struct hal_info_t *hal, enum phl_band_idx band, + bool acq_en, bool mgq_en, u16 acq_val, u16 mgq_val); + +enum rtw_hal_status +rtw_hal_mac_patch_rx_rate(struct hal_info_t *hal_info, struct rtw_r_meta_data *mdata); +enum rtw_hal_status +rtw_hal_mac_set_tx_duty(struct hal_info_t *hal_info, + u16 pause_interval, + u16 tx_interval); + +enum rtw_hal_status +rtw_hal_mac_stop_tx_duty(struct hal_info_t *hal_info); +#endif /*_HAL_API_MAC_H_*/ diff --git a/phl/hal_g6/hal_api_rf.c b/phl/hal_g6/hal_api_rf.c new file mode 100644 index 0000000..1dbda16 --- /dev/null +++ b/phl/hal_g6/hal_api_rf.c @@ -0,0 +1,1292 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_API_RF_C_ +#include "hal_headers.h" +#include "phy/rf/halrf_api.h" +#include "phy/rf/halrf_export_fun.h" + +#ifdef USE_TRUE_PHY +enum rtw_hal_status +rtw_hal_rf_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = halrf_init(phl_com, hal_com, &(hal_info->rf)); + + if ((hal_status != RTW_HAL_STATUS_SUCCESS) || + (hal_info->rf == NULL)) { + PHL_ERR("[PHL] rtw_halrf_init failed status(%d), hal_info->rf(%p)\n", + hal_status, hal_info->rf); + } + + return hal_status; +} + +void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + halrf_deinit(phl_com, hal_com, hal_info->rf); +} + +void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_para_info_t *phy_reg_info = NULL; + struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL; + u8 phy_idx = 0; + + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_a_info; + halrf_config_radio_a_reg(hal_info->rf, phy_reg_info->para_src, + phy_reg_info->para_data_len, phy_reg_info->para_data); + } + + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_b_info; + halrf_config_radio_b_reg(hal_info->rf , phy_reg_info->para_src, + phy_reg_info->para_data_len, phy_reg_info->para_data); + } + + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwr_byrate_info; + halrf_config_store_power_by_rate(hal_info->rf , phy_reg_info->para_src, + phy_reg_info->para_data_len, phy_reg_info->para_data); + } + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrtrack_info; + halrf_config_store_power_track(hal_info->rf , phy_reg_info->para_src, + phy_reg_info->para_data_len, phy_reg_info->para_data); + } + + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + pwrlmt_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrlmt_info; + halrf_config_store_power_limit(hal_info->rf , pwrlmt_info->para_src, + pwrlmt_info->para_data_len, pwrlmt_info->para_data); + } + + for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { + pwrlmt_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrlmt_ru_info; + halrf_config_store_power_limit_ru(hal_info->rf , pwrlmt_info->para_src, + pwrlmt_info->para_data_len, pwrlmt_info->para_data); + } +} + +void rtw_hal_rf_dm_init(struct hal_info_t *hal_info) +{ + halrf_dm_init(hal_info->rf); +} + +enum rtw_hal_status +rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com, + u8 *efuse_map, enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + PHL_INFO("%s\n", __FUNCTION__); + + if(halrf_get_efuse_info(hal_info->rf, efuse_map, info_type, value, size, + map_valid)) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; +} + +void +rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, + u8 pwrbyrate_type, u8 pwrlmt_type) +{ +/* struct hal_info_t *hal_info = hal_com->hal_priv; + + halrf_set_power_table_switch(hal_info->rf, phy_idx, + pwrbyrate_type, pwrlmt_type);*/ +} + +int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str) +{ + return halrf_get_predefined_pw_lmt_regu_type_from_str(str); +} + +const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num) +{ + return halrf_get_predefined_pw_lmt_regu_type_str_array(num); +} + +const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band) +{ + return halrf_get_pw_lmt_regu_type_str(hal_info->rf, band); +} + +enum rtw_hal_status rtw_hal_rf_read_pwr_table( + struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate, + u8 bandwidth, u8 channel, u8 offset, u8 dcm, + u8 beamforming, s16 *get_item) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + *get_item = halrf_get_power(hal_info->rf, rf_path, rate, dcm,offset, bandwidth, beamforming, channel); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_wl_tx_power_control(struct rtw_hal_com_t *hal_com, + u32 tx_power_val) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + PHL_INFO("%s\n", __FUNCTION__); + + halrf_wl_tx_power_control(hal_info->rf, tx_power_val); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info, u8 *txpwr_track_status) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + *txpwr_track_status = halrf_get_power_track(hal_info->rf); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info, u8 phy_idx, u8 txpwr_track_status) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + halrf_set_power_track(hal_info->rf, phy_idx, txpwr_track_status); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info, u8 rf_path, u8 *thermal) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + *thermal = halrf_get_thermal(hal_info->rf, rf_path); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 tssi_de) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + halrf_set_tssi_de_for_tx_verify(hal_info->rf, phy_idx, tssi_de, rf_path); + + return ret; + +} + +enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + halrf_set_tssi_de_offset(hal_info->rf, phy_idx, tssi_de_offset, rf_path); + + return ret; + +} + +enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 *tssi_de) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + *tssi_de = halrf_get_tssi_de(hal_info->rf, phy_idx, rf_path); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_get_online_tssi_de(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path,s32 dbm, s32 pout, s32 *tssi_de) +{ + int ret = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("[MP HAL API] %s \n", __FUNCTION__); + + *tssi_de = halrf_get_online_tssi_de(hal_info->rf, phy_idx, rf_path, dbm, pout); + + return ret; +} + +enum rtw_hal_status +rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info) +{ + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info, + u8 is_on,enum rf_path path) +{ + PHL_INFO("%s: enable = %d path = %x\n", __FUNCTION__, is_on, path); + halrf_lo_test(hal_info->rf, is_on, path); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info) +{ + PHL_INFO("%s\n", __FUNCTION__); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com, + bool dbcc_en) +{ + /*need replace with rf api*/ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + + if (halrf_set_dbcc(hal_info->rf, dbcc_en)) + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +#define DBG_RFK_TIME +enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal, + u8 phy_idx, u8 force) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + #ifdef DBG_RFK_TIME + u32 iqk_start = _os_get_cur_time_ms(); + #endif + + PHL_INFO("[DBG_RFK]%s: phy_idx(%d), force(%d)\n", __func__, + phy_idx, force); + rtw_hal_mac_ser_ctrl(hal_info, false); + + hal_status = halrf_chl_rfk_trigger(hal_info->rf, phy_idx, force); + + #ifdef DBG_RFK_TIME + PHL_INFO("[DBG_RFK]%s: RFK take %d (ms)\n", __func__, + phl_get_passing_time_ms(iqk_start)); + #endif + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + rtw_hal_mac_ser_ctrl(hal_info, true); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info, + u8 force) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_dack_trigger(hal_info->rf, force); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = halrf_iqk_trigger(hal_info->rf, phy_idx, force); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_lck_trigger(hal_info->rf); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = halrf_dpk_trigger(hal_info->rf, phy_idx, force); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info, + u8 phy_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_tssi_trigger(hal_info->rf, phy_idx); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_gapk_trigger(hal_info->rf, phy_idx, force); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + + +enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_dack_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_iqk_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_dpk_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_dpk_track_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_tssi_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info, + u8 enable) +{ +#if 0 + halrf_gapk_onoff(hal_info->rf, enable); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_dack_onoff(hal_info->rf); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_iqk_onoff(hal_info->rf); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_dpk_onoff(hal_info->rf); +#endif + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_dpk_track_onoff(hal_info->rf); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_tssi_onoff(hal_info->rf); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info, + u8 *enable) +{ +#if 0 + *enable = halrf_get_gapk_onoff(hal_info->rf); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_get_tssi_de_value(hal_info->rf); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_set_tssi_de_tx_verify(hal_info->rf); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#if 0 + hal_status = halrf_get_txpwr_final_abs(hal_info->rf); +#else + hal_status = RTW_HAL_STATUS_SUCCESS; +#endif + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +bool +rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + + if(incmd->in_type == RTW_ARG_TYPE_BUF) + halrf_cmd(hal_info->rf, incmd->in.buf, output, out_len); + + else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){ + + halrf_cmd_parser(hal_info->rf, incmd->in.vector, + incmd->in_cnt_len, output, out_len); + } + + return true; +} + +enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info) +{ + + halrf_watchdog(hal_info->rf); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if(halrf_set_power(hal_info->rf, phy, pwr_table)) + { + hal_status = RTW_HAL_STATUS_SUCCESS; + } + else + { + hal_status = RTW_HAL_STATUS_FAILURE; + } + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx, + s8 offset, u8 rf_path) +{ + + enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS; + PHL_INFO("[MP HAL API]%s\n", __FUNCTION__); + + halrf_set_rx_gain_offset_for_rx_verify(hal_info->rf, cur_phy_idx, offset, rf_path); + + return ret; +} + +enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = halrf_dpk_tracking(hal_info->rf); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + hal_com->dev_hw_cap.rfe_type = halrf_get_default_rfe_type(hal_info->rf); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + hal_com->dev_hw_cap.xcap = halrf_get_default_xtal(hal_info->rf); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 xdbm) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_set_tssi_avg_mp(hal_info->rf, cur_phy_idx, xdbm); + + return hal_status; +} + +void rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_info, u8 cur_phy_idx) +{ + halrf_do_tssi_scan(hal_info->rf, cur_phy_idx); +} + +enum rtw_hal_status +rtw_hal_rf_update_ext_pwr_lmt_table(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_power_limit_set_ext_pwr_limit_table(hal_info->rf, HW_PHY_0); + halrf_power_limit_set_ext_pwr_limit_ru_table(hal_info->rf, HW_PHY_0); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info) +{ + halrf_config_radio_to_fw(hal_info->rf); + + return RTW_HAL_STATUS_SUCCESS; +} + +bool +rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + return halrf_tssi_check_efuse_data(hal_info->rf, phy_idx); +} + +void +rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + halrf_disconnect_notify(hal_info->rf, chandef); +} + +bool +rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + return halrf_check_mcc_ch(hal_info->rf, chandef); +} + +void +rtw_hal_rf_dpk_switch(void *hal, bool enable) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_rf_dpk_switch(): enable(%d)\n", + enable); + halrf_dpk_switch(hal_info->rf, enable); +} + +void +rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_rf_tssi_config(): enable(%d), phy_idx(%d)\n", + enable, phy_idx); + if (enable) + halrf_tssi_enable(hal_info->rf, phy_idx); + else + halrf_tssi_disable(hal_info->rf, phy_idx); +} + +enum rtw_hal_status +rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch, + enum band_type band, enum channel_width bw) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_ctrl_bw_ch(hal_info->rf, phy, center_ch, band, bw); + + return hal_status; +} + +void +rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + halrf_tssi_get_efuse_ex(hal_info->rf, phy_idx); + +} + + +/* PSD */ +enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx, + u8 path, u8 iq_path, u32 avg, u32 fft) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_psd_init(hal_info->rf, cur_phy_idx, path, iq_path, avg, fft); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_psd_restore(hal_info->rf, cur_phy_idx); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 point, u32 *value) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + *value = halrf_psd_get_point_data(hal_info->rf, cur_phy_idx, point); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + halrf_psd_query(hal_info->rf, cur_phy_idx, point, start_point, stop_point, outbuf); + + return hal_status; +} + +void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/u8 ant) +{ + halrf_2g_rxant(hal_info->rf, ant); +} + +enum halrf_thermal_status +rtw_hal_rf_get_ther_protected_threshold( + struct hal_info_t *hal_info +) +{ + s8 val = 0; + enum halrf_thermal_status status = HALRF_THERMAL_STATUS_UNKNOWN; + + val = halrf_get_ther_protected_threshold(hal_info->rf); + + if(val == -1){ + status = HALRF_THERMAL_STATUS_ABOVE_THRESHOLD; + PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal above threshold!\n"); + } + else if(val == 0){ + status = HALRF_THERMAL_STATUS_STAY_THRESHOLD; + PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal stay at threshold!\n"); + } + else if(val == 1){ + status = HALRF_THERMAL_STATUS_BELOW_THRESHOLD; + PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal below threshold!\n"); + } + else{ + status = HALRF_THERMAL_STATUS_UNKNOWN; + PHL_TRACE(COMP_PHL_RF, _PHL_WARNING_, "[HALRF] Thermal unknown status!\n"); + } + return status; +} + +void rtw_hal_rf_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx) +{ + halrf_wifi_event_notify(hal_info->rf, event, phy_idx); +} + +void +rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, enum rf_path path) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + + halrf_tssi_scan_ch(hal_info->rf, path); + + halrf_tssi_set_efuse_to_de(hal_info->rf, phy_idx); +} + +s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy, + u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return halrf_get_power_limit(hal_info->rf, phy, RF_PATH_A, rate, + bandwidth, beamforming, tx_num, channel); +} + +void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx) +{ + /*to do*/ +} + +#else /*ifdef USE_TRUE_PHY*/ +enum rtw_hal_status +rtw_hal_rf_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} +void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ +} + +void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal) +{ +} + +void rtw_hal_rf_dm_init(struct hal_info_t *hal_info) +{ +} + +enum rtw_hal_status +rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com, u8 *efuse_map, + enum rtw_efuse_info info_type, void *value, + u8 size, u8 map_valid) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_read_pwr_table(struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate, + u8 bandwidth, u8 channel, u8 offset, u8 dcm, + u8 beamforming, s16 *get_item) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_wl_tx_power_control(struct rtw_hal_com_t *hal_com, + u32 tx_power_val) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info, + u8 *txpwr_track_status) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info, + u8 phy_idx, u8 txpwr_track_status) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info, + u8 rf_path, u8 *thermal) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info, + u8 phy_idx, u8 rf_path, u32 tssi_de) +{ + return RTW_HAL_STATUS_SUCCESS; +} +enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path) +{ + return RTW_HAL_STATUS_SUCCESS; +} +enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info, + u8 phy_idx, u8 rf_path, u32 *tssi_de) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_online_tssi_de( + struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, + s32 dbm, s32 pout, s32 *tssi_de) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info, + u8 is_on,enum rf_path path) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com, + bool dbcc_en) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info, + u8 force) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info, + u8 phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info, + u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info, + u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info, + u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info, u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info, u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info, + u8 enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info, + u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info, + u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info, + u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info, u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info, + u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info, + u8 *enable) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + return true; +} + +enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} +enum rtw_hal_status +rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx, + s8 offset, u8 rf_path) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_info, u8 cur_phy_idx) +{ + +} + +enum rtw_hal_status +rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info) +{ + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 xdbm) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +bool +rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx) +{ + return true; +} + +enum rtw_hal_status +rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch, + enum band_type band, enum channel_width bw) + +{ + return RTW_HAL_STATUS_SUCCESS; +} + +/* PSD */ +enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx, + u8 path, u8 iq_path, u32 avg, u32 fft) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 point, u32 *value) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf) +{ + return RTW_HAL_STATUS_SUCCESS; +} + +void +rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef) +{ +} + +bool +rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef) +{ + return false; +} + +void +rtw_hal_rf_dpk_switch(void *hal, bool enable) +{ + +} + +void +rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable) +{ + +} + +void +rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx) +{ +} + +void +rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, + u8 pwrbyrate_type, u8 pwrlmt_type) +{ + return; +} + +int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str) +{ + return -1; +} + +const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num) +{ + return NULL; +} + +const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band) +{ + return NULL; +} + +void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/u8 ant) +{ + +} + +enum halrf_thermal_status +rtw_hal_rf_get_ther_protected_threshold( + struct hal_info_t *hal_info +) +{ + return HALRF_THERMAL_STATUS_BELOW_THRESHOLD; +} + +void rtw_hal_rf_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx) +{ + return; +} + +void +rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com, + enum phl_phy_idx phy_idx, enum rf_path path) + +{ + return; +} + +s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy, + u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel) +{ + return 0; +} + +void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx) +{ + +} +#endif /*ifdef USE_TRUE_PHY*/ diff --git a/phl/hal_g6/hal_api_rf.h b/phl/hal_g6/hal_api_rf.h new file mode 100644 index 0000000..cf650a3 --- /dev/null +++ b/phl/hal_g6/hal_api_rf.h @@ -0,0 +1,232 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_API_RF_H_ +#define _HAL_API_RF_H_ + +enum halrf_thermal_status{ + HALRF_THERMAL_STATUS_BELOW_THRESHOLD, + HALRF_THERMAL_STATUS_STAY_THRESHOLD, + HALRF_THERMAL_STATUS_ABOVE_THRESHOLD, + HALRF_THERMAL_STATUS_UNKNOWN +}; + +enum rtw_hal_status +rtw_hal_rf_init(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); + +void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); + +void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal); + +enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info, u8 *txpwr_track_status); + +void rtw_hal_rf_dm_init(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info, u8 phy_idx, u8 txpwr_track_status); + +void rtw_hal_rf_dm_init(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info, u8 rf_path, u8 *thermal); + +enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 tssi_de); + +enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 *tssi); + +enum rtw_hal_status rtw_hal_rf_get_online_tssi_de(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path,s32 dbm, s32 pout, s32 *tssi_de); + +enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path); + +enum rtw_hal_status rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info, + u8 is_on,enum rf_path path); + +enum rtw_hal_status rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force); + + +enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info, + u8 force); + + +enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force); + + +enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info); + + +enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force); + + +enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info, + u8 phy_idx); + + +enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info, + u8 phy_idx, u8 force); + + +enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info, + u8 enable); + + +enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info, + u8 enable); + + +enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info, + u8 enable); + + +enum rtw_hal_status rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info, + u8 enable); + + + +enum rtw_hal_status rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info, + u8 enable); + + +enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info, + u8 enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info, + u8 *enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info, + u8 *enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info, + u8 *enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info, + u8 *enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info, + u8 *enable); + + +enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info, + u8 *enable); + +enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info); + +enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info); + +int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str); +const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num); +const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band); + +bool +rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info, + struct rtw_proc_cmd *incmd, + char *output, u32 out_len); + +enum rtw_hal_status +rtw_hal_rf_recover(struct hal_info_t *hal_info, u32 offset, u32 val, enum rf_path path); + +enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table); + +enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx, + s8 offset, u8 rf_path); + +enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com); + +enum rtw_hal_status +rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com); + + +enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 xdbm); +void +rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_ionfo, u8 cur_phy_idx); + +enum rtw_hal_status +rtw_hal_rf_update_ext_pwr_lmt_table(struct hal_info_t *hal_info); + +enum rtw_hal_status +rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info); + +bool +rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx); + +void +rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef); + +bool +rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef); + +void +rtw_hal_rf_dpk_switch(void *hal, bool enable); + +void +rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable); + + +enum rtw_hal_status +rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch, + enum band_type band, enum channel_width bw); + +void +rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx); + + +/* PSD */ +enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx, + u8 path, u8 iq_path, u32 avg, u32 fft); + +enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx); + +enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx, + s32 point, u32 *value); + +enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf); + +void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/ u8 ant); + +enum halrf_thermal_status +rtw_hal_rf_get_ther_protected_threshold( + struct hal_info_t *hal_info +); + +void rtw_hal_rf_notification(struct hal_info_t *hal_info, + enum phl_msg_evt_id event, + enum phl_phy_idx phy_idx); + +void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info, + void *hal_cmd, + enum phl_phy_idx phy_idx); + +#endif /*_HAL_API_RF_H_*/ diff --git a/phl/hal_g6/hal_beamform.c b/phl/hal_g6/hal_beamform.c new file mode 100644 index 0000000..ece69df --- /dev/null +++ b/phl/hal_g6/hal_beamform.c @@ -0,0 +1,1188 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "hal_headers.h" + +/** + * rtw_hal_bf_dbg_dump_entry + * @entry: hal_bf_entry for dump content + **/ +void rtw_hal_bf_dbg_dump_entry(void *entry) +{ + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + if (bf_entry == NULL) { + return; + } + + PHL_INFO("-----DUMP BF ENTRY-----\n"); + PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx); + PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid); + PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12); + PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band); + PHL_INFO("bf_entry->en_swap 0x%x \n", bf_entry->en_swap ? 1 : 0); + PHL_INFO("bf_entry->counter 0x%x \n", bf_entry->couter); + PHL_INFO("bf_entry->csi_buf 0x%x \n", bf_entry->csi_buf); + PHL_INFO("bf_entry->csi_buf_swap 0x%x \n", bf_entry->csi_buf_swap); + if (bf_entry->bfee != NULL) { + PHL_INFO("bf_entry->bfee->type 0x%x \n", bf_entry->bfee->type); + } +} +/** + * rtw_hal_bf_dbg_dump_entry_all + * @hal: hal_info_t + **/ +void rtw_hal_bf_dbg_dump_entry_all(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry; + _os_list *busy_list = &bf_obj->bf_busy_list; + _os_list *idle_list = &bf_obj->bf_idle_list; + + PHL_INFO("-----DUMP BF BUSY LIST-----\n"); + if(list_empty(busy_list)) { + PHL_INFO("BF Entry BUSY LIST is Empty\n"); + } else { + phl_list_for_loop(bf_entry, struct hal_bf_entry, busy_list, + list) { + PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx); + PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid); + PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12); + PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band); + PHL_INFO("bf_entry->en_swap 0x%x \n", bf_entry->en_swap ? 1 : 0); + PHL_INFO("bf_entry->counter 0x%x \n", bf_entry->couter); + PHL_INFO("bf_entry->csi_buf 0x%x \n", + bf_entry->csi_buf); + PHL_INFO("bf_entry->csi_buf_swap 0x%x \n", + bf_entry->csi_buf_swap); + if (NULL!=bf_entry->bfee) { + PHL_INFO("bfee->idx 0x%x \n", + bf_entry->bfee->idx); + PHL_INFO("bfee->type 0x%x \n", + bf_entry->bfee->type); + } + } + } + PHL_INFO("-----DUMP BF IDLE LIST-----\n"); + if(list_empty(idle_list)) { + PHL_INFO("BF Entry IDLE LIST is Empty\n"); + } else { + phl_list_for_loop(bf_entry, struct hal_bf_entry, idle_list, + list) { + PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx); + PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid); + PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12); + PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band); + PHL_INFO("bf_entry->csi_buf 0x%x \n", + bf_entry->csi_buf); + } + } +} + +void _reset_bf_entry(struct hal_bf_entry *bf_entry) +{ + bf_entry->macid = 0; + bf_entry->aid12 = 0; + bf_entry->csi_buf = 0; + bf_entry->bfee = NULL; + bf_entry->csi_buf_swap = 0; + bf_entry->couter = 0; +} + +void _reset_sumu_entry(struct hal_sumu_entry *entry) +{ + entry->snd_sts = 0; + return; +} + +/* START of tx bf entry */ +static struct hal_bf_entry *_query_idle_bf_entry(struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *idle_list = &bf_obj->bf_idle_list; + struct hal_bf_entry *bf_entry = NULL; + + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + if (true == list_empty(idle_list)) { + bf_entry = NULL; + } else { + bf_entry = list_first_entry(idle_list, struct hal_bf_entry, + list); + bf_obj->num_idle_bf_entry--; + list_del(&bf_entry->list); + } + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + + return bf_entry; +} + +static enum rtw_hal_status _enqueue_idle_bf_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_bf_entry *bf_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->bf_idle_list; + + if (bf_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add(&bf_entry->list, list); + bf_obj->num_idle_bf_entry++; + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + +static enum rtw_hal_status _enqueue_busy_bf_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_bf_entry *bf_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->bf_busy_list; + + if (bf_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add_tail(&bf_entry->list, list); + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} +/*su entry*/ +static struct hal_sumu_entry *_query_idle_su_entry(struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *idle_list = &bf_obj->su_idle_list; + struct hal_sumu_entry *su_entry = NULL; + + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + if (true == list_empty(idle_list)) { + su_entry = NULL; + } else { + su_entry = list_first_entry(idle_list, struct hal_sumu_entry, + list); + bf_obj->num_idle_su_entry--; + list_del(&su_entry->list); + } + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + + return su_entry; +} + +static enum rtw_hal_status _enqueue_idle_su_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_sumu_entry *su_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->su_idle_list; + + if (su_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add(&su_entry->list, list); + bf_obj->num_idle_su_entry++; + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + +static enum rtw_hal_status _enqueue_busy_su_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_sumu_entry *su_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->su_busy_list; + + if (su_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add_tail(&su_entry->list, list); + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + + +/*mu entry*/ +static struct hal_sumu_entry *_query_idle_mu_entry(struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *idle_list = &bf_obj->mu_idle_list; + struct hal_sumu_entry *mu_entry = NULL; + + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + if (true == list_empty(idle_list)) { + mu_entry = NULL; + } else { + mu_entry = list_first_entry(idle_list, struct hal_sumu_entry, + list); + bf_obj->num_idle_mu_entry--; + list_del(&mu_entry->list); + } + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + + return mu_entry; +} + +static enum rtw_hal_status _enqueue_idle_mu_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_sumu_entry *mu_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->mu_idle_list; + + if (mu_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add(&mu_entry->list, list); + bf_obj->num_idle_mu_entry++; + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + +static enum rtw_hal_status _enqueue_busy_mu_entry( + struct hal_info_t *hal_info, + struct hal_bf_obj *bf_obj, + struct hal_sumu_entry *mu_entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + void *drv_priv = hal_to_drvpriv(hal_info); + _os_list *list = &bf_obj->mu_busy_list; + + if (mu_entry != NULL) { + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_add_tail(&mu_entry->list, list); + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + + return status; +} + +/* hal bf init */ +enum rtw_hal_status _hal_bf_init_su_entry( + struct hal_info_t *hal_info, + u8 num) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + void *drv_priv = hal_to_drvpriv(hal_info); + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_sumu_entry *su_entry = NULL; + u8 i; + + do { + bf_obj->su_entry = _os_mem_alloc(drv_priv, + sizeof(*su_entry) * num); + + if (NULL == bf_obj->su_entry) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + _os_mem_set(drv_priv, bf_obj->su_entry, 0, + sizeof(*su_entry) * num); + + su_entry = bf_obj->su_entry; + + for ( i = 0 ; i < num; i++) { + su_entry[i].idx = i; + su_entry[i].type = HAL_BFEE_SU; + _reset_sumu_entry(&su_entry[i]); + INIT_LIST_HEAD(&su_entry[i].list); + list_add_tail(&su_entry[i].list, &bf_obj->su_idle_list); + bf_obj->num_idle_su_entry++; + } + + } while (0); + return status; +} + + +enum rtw_hal_status _hal_bf_init_mu_entry( + struct hal_info_t *hal_info, + u8 num) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + void *drv_priv = hal_to_drvpriv(hal_info); + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_sumu_entry *mu_entry = NULL; + u8 i; + + do { + bf_obj->mu_entry = _os_mem_alloc(drv_priv, + sizeof(*mu_entry) * num); + + if (NULL == bf_obj->mu_entry) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + _os_mem_set(drv_priv, bf_obj->mu_entry, 0, + sizeof(*mu_entry) * num); + + mu_entry = bf_obj->mu_entry; + + for ( i = 0 ; i < num; i++) { + mu_entry[i].idx = i; + mu_entry[i].type = HAL_BFEE_MU; + _reset_sumu_entry(&mu_entry[i]); + INIT_LIST_HEAD(&mu_entry[i].list); + list_add_tail(&mu_entry[i].list, &bf_obj->mu_idle_list); + bf_obj->num_idle_mu_entry++; + } + + } while (0); + return status; +} + + +enum rtw_hal_status _hal_bf_init_bf_entry( + struct hal_info_t *hal_info, + u8 num) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + void *drv_priv = hal_to_drvpriv(hal_info); + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry = NULL; + u8 i; + + do { + bf_obj->bf_entry = _os_mem_alloc(drv_priv, + sizeof(*bf_entry) * num); + if (NULL == bf_obj->bf_entry) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + _os_mem_set(drv_priv, bf_obj->bf_entry, 0, + sizeof(*bf_entry) * num); + + bf_entry = bf_obj->bf_entry; + + for ( i = 0 ; i < num; i++) { + bf_entry[i].bf_idx = i; + _reset_bf_entry(&bf_entry[i]); + INIT_LIST_HEAD(&bf_entry[i].list); + list_add_tail(&bf_entry[i].list, + &bf_obj->bf_idle_list); + bf_obj->num_idle_bf_entry++; + } + + } while (0); + return status; +} + + +/* Start of HAL API for other HAL modules */ +/** + * hal_bf_init: + * initialize of beamform resource mgnt module + * input : + * @hal_info: (struct hal_info_t *) + * @bf_entry_nr: Number of HW support TxBF Entry + * @su_entry_nr: Number of HW support BFee-SU Entry + * @mu_entry_nr: Number of HW support BFee-MU Entry + **/ +enum rtw_hal_status hal_bf_init( + struct hal_info_t *hal_info, + u8 bf_entry_nr, + u8 su_entry_nr, + u8 mu_entry_nr) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = NULL; + void *drv_priv = hal_to_drvpriv(hal_info); + + FUNCIN(); + do { + bf_obj = _os_mem_alloc(drv_priv, sizeof(*bf_obj)); + + if (bf_obj == NULL) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + hal_com->bf_obj = bf_obj; + + _os_spinlock_init(drv_priv, &bf_obj->bf_lock); + + INIT_LIST_HEAD(&bf_obj->bf_idle_list); + INIT_LIST_HEAD(&bf_obj->bf_busy_list); + + INIT_LIST_HEAD(&bf_obj->su_idle_list); + INIT_LIST_HEAD(&bf_obj->su_busy_list); + + INIT_LIST_HEAD(&bf_obj->mu_idle_list); + INIT_LIST_HEAD(&bf_obj->mu_busy_list); + + if (RTW_HAL_STATUS_SUCCESS != + _hal_bf_init_bf_entry(hal_info, bf_entry_nr)) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + bf_obj->max_bf_entry_nr = bf_entry_nr; + + if (RTW_HAL_STATUS_SUCCESS != + _hal_bf_init_su_entry(hal_info, su_entry_nr)) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + bf_obj->max_su_bfee_nr = su_entry_nr; + + if (RTW_HAL_STATUS_SUCCESS != + _hal_bf_init_mu_entry(hal_info, mu_entry_nr)) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + bf_obj->max_mu_bfee_nr = mu_entry_nr; + + bf_obj->self_bf_cap[0] = 0; + bf_obj->self_bf_cap[1] = 0; + + } while (0); + + if (RTW_HAL_STATUS_SUCCESS != status) { + hal_bf_deinit(hal_info); + } + FUNCOUT(); + + return status; +} + +/** + * hal_bf_deinit + * deinitialize of beamform resource mgnt module + * input : + * @hal_info: (struct hal_info_t *) + **/ +void hal_bf_deinit(struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + void *drv_priv = hal_to_drvpriv(hal_info); + struct hal_bf_entry *bf_entry = bf_obj->bf_entry; + struct hal_sumu_entry *mu_entry = bf_obj->mu_entry; + struct hal_sumu_entry *su_entry = bf_obj->su_entry; + + if (bf_obj != NULL) { + if (bf_entry != NULL) { + _os_mem_free(hal_to_drvpriv(hal_info), bf_entry, + sizeof(*bf_entry) * bf_obj->max_bf_entry_nr); + bf_obj->bf_entry = NULL; + } + if (su_entry != NULL) { + _os_mem_free(hal_to_drvpriv(hal_info), su_entry, + sizeof(*su_entry) * bf_obj->max_su_bfee_nr); + bf_obj->su_entry = NULL; + } + + if (mu_entry != NULL) { + _os_mem_free(hal_to_drvpriv(hal_info), mu_entry, + sizeof(*mu_entry) * bf_obj->max_mu_bfee_nr); + bf_obj->mu_entry = NULL; + } + + _os_spinlock_free(drv_priv, &bf_obj->bf_lock); + + /* bf obj need free as last */ + _os_mem_free(hal_to_drvpriv(hal_info), bf_obj, + sizeof(struct hal_bf_obj)); + hal_com->bf_obj = NULL; + } +} +/** + * hal_bf_release_target_bf_entry + * Release the bf entry resource + * input + * @hal_info: (struct hal_info_t *) + * @entry: hal_bf_entry to be released + **/ +enum rtw_hal_status hal_bf_release_target_bf_entry( + struct hal_info_t *hal_info, + void *entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + void *drv_priv = hal_to_drvpriv(hal_info); + u8 bfee_idx = 0; + u16 macid_rsvd = 0; + FUNCIN(); + if (bf_obj != NULL && bf_entry != NULL) { + if (bf_entry->bfee != NULL) { + + bfee_idx = bf_entry->bfee->idx + + ((bf_entry->bfee->type == HAL_BFEE_MU) ? + bf_obj->max_su_bfee_nr : 0); + /* Clear HW CR to avoid TxBF when sounding is abort */ + rtw_hal_mac_ax_set_bf_entry(hal_info->mac, + bf_entry->band, (u8)macid_rsvd, + bfee_idx, bf_entry->bf_idx, 0); + + _reset_sumu_entry(bf_entry->bfee); + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_del(&bf_entry->bfee->list); + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + if (bf_entry->bfee->type == HAL_BFEE_MU) { + _enqueue_idle_mu_entry( + hal_info, bf_obj, bf_entry->bfee); + } else { + _enqueue_idle_su_entry( + hal_info, bf_obj, bf_entry->bfee); + } + } + _reset_bf_entry(bf_entry); + _os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + list_del(&bf_entry->list); + _os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL); + _enqueue_idle_bf_entry(hal_info, bf_obj, bf_entry); + status = RTW_HAL_STATUS_SUCCESS; + } + FUNCOUT(); + return status; +} + +/** + * hal_bf_query_idle_bf_entry + * Get available beamformee entry + * @hal_info: (struct hal_info_t *) + * @mu: Is MU BFee ? 1 = MU / 0 = SU + * return : + * @hal_bf_entry: hal_bf_entry pointer + **/ +struct hal_bf_entry * +hal_bf_query_idle_bf_entry( + struct hal_info_t *hal_info, + bool mu) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry = NULL; + struct hal_sumu_entry *sumu_entry; + + FUNCIN(); + + do { + if (bf_obj == NULL) + break; + + bf_entry = _query_idle_bf_entry(hal_info, bf_obj); + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "_query_idle_bf_entry bf_entry %p \n", bf_entry); + + if (NULL == bf_entry) + break; + + if (true == mu) + bf_entry->bfee = _query_idle_mu_entry(hal_info, bf_obj); + else + bf_entry->bfee = _query_idle_su_entry(hal_info, bf_obj); + + if (NULL == bf_entry->bfee) + break; + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "_query_idle_bf_entry sumu_entry %p \n", bf_entry->bfee); + sumu_entry = bf_entry->bfee; + + status = _enqueue_busy_bf_entry(hal_info, bf_obj, bf_entry); + if (RTW_HAL_STATUS_SUCCESS != status) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :hal_bf_entry add busy queue fail !!!\n"); + break; + } + + if (true == mu) + status = _enqueue_busy_mu_entry( + hal_info, bf_obj, sumu_entry); + else + status = _enqueue_busy_su_entry( + hal_info, bf_obj, sumu_entry); + if (RTW_HAL_STATUS_SUCCESS != status) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :sumu_entry add busy queue fail !!!\n"); + break; + } + } while (0); + + if((status != RTW_HAL_STATUS_SUCCESS) && (bf_entry != NULL)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Get BF Entry Fail !!!\n"); + hal_bf_release_target_bf_entry(hal_info, (void *)bf_entry); + } + FUNCOUT(); + return bf_entry; +} +/** + * hal_bf_cfg_swbf_entry + * Fill BF Entry SW Content + * input: + * @sta: rtw_phl_stainfo_t + **/ +enum rtw_hal_status +hal_bf_cfg_swbf_entry(struct rtw_phl_stainfo_t *sta, bool swap) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_bf_entry *bf_entry = + (struct hal_bf_entry *)sta->hal_sta->bf_entry; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_cfg_swbf_entry bf_entry->idx = 0x%x\n", + bf_entry->bf_idx); + + bf_entry->macid = sta->macid; + bf_entry->aid12 = sta->aid; + bf_entry->band = sta->wrole->hw_band; //TODO: :BSOD in snd_test whole = NULL + bf_entry->csi_buf = sta->hal_sta->bf_csi_buf; + if (swap) { + bf_entry->en_swap = true; + bf_entry->csi_buf_swap = sta->hal_sta->bf_csi_buf_swap; + } + + return status; +} + +/** + * hal_bf_set_entry_hwcfg + * Configure BF Entry HW Setting + * input + * @hal_info: (struct hal_info_t *) + * @entry: struct hal_bf_entry + **/ +enum rtw_hal_status hal_bf_set_entry_hwcfg( + struct hal_info_t *hal_info, + void *entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + u8 bfee_idx = 0; + u16 csi_buf = 0; + + /*TODO: 8852A : SU : 0 ~ N-1; MU : N ~ M*/ + bfee_idx = bf_entry->bfee->idx + + ((bf_entry->bfee->type == HAL_BFEE_MU) ? + bf_obj->max_su_bfee_nr : 0); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "hal_bf_set_entry_hwcfg set bf sts idx = 0x%x \n", bfee_idx); + + /*1. HALMAC Settings*/ + if ((bf_entry->bfee->type == HAL_BFEE_MU) && bf_entry->en_swap) { + /*swap mode*/ + if(0 == (bf_entry->couter % 2)) + csi_buf = bf_entry->csi_buf&CSI_BUF_IDX_HW_MSK; + else + csi_buf = bf_entry->csi_buf_swap&CSI_BUF_IDX_HW_MSK; + + rtw_hal_mac_ax_set_bf_entry( + hal_info->mac, bf_entry->band, + (u8)(bf_entry->macid&0xFF), bfee_idx, + bf_entry->bf_idx, csi_buf); + + bf_entry->couter++; + } else { + rtw_hal_mac_ax_set_bf_entry( + hal_info->mac, bf_entry->band, + (u8)(bf_entry->macid&0xFF), bfee_idx, + bf_entry->bf_idx, + bf_entry->csi_buf&CSI_BUF_IDX_HW_MSK); + } + /*2.TODO: HALBB Settings if needed*/ + + return status; +} + +/** + * hal_bf_update_entry_snd_sts + * Update BF Entry Sounding Status + * input + * @hal_info: (struct hal_info_t *) + * @entry: struct hal_bf_entry + **/ +void hal_bf_update_entry_snd_sts(struct hal_info_t *hal_info, void *entry) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + u8 bfee_idx = 0; + /*TODO: 8852A : SU : 0 ~ N-1; MU : N ~ M*/ + if (NULL == bf_entry) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[ERROR] hal_bf_update_entry_snd_sts BF_Entry = NULL\n"); + return; + } + if (NULL == bf_entry->bfee) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->macid = 0x%x\n", bf_entry->macid); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->bfee = NULL\n"); + return; + } + bfee_idx = bf_entry->bfee->idx + + ((bf_entry->bfee->type == HAL_BFEE_MU) ? + bf_obj->max_su_bfee_nr : 0); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_update_entry_snd_sts idx = 0x%x \n", bfee_idx); + + status = rtw_hal_mac_ax_get_snd_sts(hal_info->mac, + bf_entry->band, bfee_idx); + + bf_entry->bfee->snd_sts = (status == RTW_HAL_STATUS_SUCCESS) ? 1 : 0; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_update_entry_snd_sts bf_entry->bfee->snd_sts = 0x%x \n", + bf_entry->bfee->snd_sts); + +} + +enum rtw_hal_status +hal_bf_hw_mac_deinit_bfee(struct hal_info_t *hal_info, u8 band) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + + do { + if (band >= 2) { + status = RTW_HAL_STATUS_FAILURE; + break; + } + if ((0 == (bf_obj->self_bf_cap[band]&BF_CAP_HE_BFEE)) && + (0 == (bf_obj->self_bf_cap[band]&BF_CAP_VHT_BFEE))) { + /* already disable */ + break; + } + status = rtw_hal_mac_ax_deinit_bfee(hal_info->hal_com, band); + + if (status != RTW_HAL_STATUS_SUCCESS) + break; + + bf_obj->self_bf_cap[band] &= ~(BF_CAP_HE_BFEE|BF_CAP_VHT_BFEE); + } while (0); + + return status; +} + +/** + * rtw_hal_bf_get_entry_snd_sts + * Get BF Entry Sounding Status + * input + * @hal_info: (struct hal_info_t *) + * @entry: struct hal_bf_entry + * return + * rtw_hal_status : RTW_HAL_STATUS_FAILURE or RTW_HAL_STATUS_SUCCESS + **/ +enum rtw_hal_status +rtw_hal_bf_get_entry_snd_sts(void *entry) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + if (NULL == bf_entry) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[ERROR] rtw_hal_bf_get_entry_snd_sts BF_Entry = NULL\n"); + return hstatus; + } + if (NULL == bf_entry->bfee) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->macid = 0x%x\n", bf_entry->macid); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->bfee = NULL\n"); + return hstatus; + } + + if (1 == bf_entry->bfee->snd_sts) + hstatus = RTW_HAL_STATUS_SUCCESS; + + return hstatus; +} + +/** + * hal_bf_hw_mac_init_bfee + * Initialize BFee HW Settings + * input + * @hal_info: struct hal_info_t + * @band: Band 0 / Band 1 + **/ +enum rtw_hal_status hal_bf_hw_mac_init_bfee( + struct hal_info_t *hal_info, + u8 band) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + + do { + if (band >= 2) { + status = RTW_HAL_STATUS_FAILURE; + break; + } + status = rtw_hal_mac_ax_init_bf_role( + hal_info->hal_com, HAL_BF_ROLE_BFEE, band); + + if(status != RTW_HAL_STATUS_SUCCESS) + break; + + /*TODO: Check Wireless Mode*/ + bf_obj->self_bf_cap[band] |= BF_CAP_HE_BFEE|BF_CAP_VHT_BFEE; + + } while (0); + + return status; +} +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +enum rtw_hal_status +rtw_hal_bf_bfee_ctrl(void *hal, u8 band, bool ctrl) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + bool cur_bfee_cap = false; + + if ((bf_obj->self_bf_cap[band] & BF_CAP_HE_BFEE) || + (bf_obj->self_bf_cap[band] & BF_CAP_VHT_BFEE)) { + cur_bfee_cap = true; + } + + /* BB Workaround */ + if ((ctrl != cur_bfee_cap) && (true == ctrl)) { + /* From Tx to Rx (need Enable BFee) */ + rtw_hal_bb_dcr_en(hal_info, true); + } else if ((ctrl != cur_bfee_cap) && (false == ctrl)) { + rtw_hal_bb_dcr_en(hal_info, false); + } + + if ((ctrl == true) && + (false == rtw_hal_bb_csi_rsp(hal_info))) { + ctrl = false; + } + + if (ctrl != cur_bfee_cap) { + status = ((true == ctrl) ? + hal_bf_hw_mac_init_bfee(hal_info, band) : + hal_bf_hw_mac_deinit_bfee(hal_info, band)); + } + + return status; +} +#endif + +/** + * hal_bf_set_bfee_csi_para + * Set self bfee hw capability. + * input: + * @hal_info: struct hal_info_t * + * @cr_cctl: set bfee capabiliy method + * true = by register (only support 2 sets, Port 0 / Port 1-4 ) + * false = by cmac control table + * @sta: struct rtw_phl_stainfo_t * (self) + */ +enum rtw_hal_status hal_bf_set_bfee_csi_para(struct hal_info_t *hal_info, + bool cr_cctl, struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + u32 rrsc = BIT(HAL_BF_RRSC_6M) | BIT(HAL_BF_RRSC_24M); + + if (false == cr_cctl) { + status = rtw_hal_mac_ax_bfee_para_reg(hal_info->mac, sta); + } else { + status = rtw_hal_mac_ax_bfee_para_cctl(hal_info->mac, sta); + } + /* mac/bb csi rate settings initialize */ + if (RTW_HAL_STATUS_SUCCESS == status) { + /* Initialize CSI rate RA parameters */ + sta->hal_sta->ra_info.fixed_csi_rate_en = false; + sta->hal_sta->ra_info.ra_csi_rate_en = true; + sta->hal_sta->ra_info.band_num = sta->wrole->hw_band; + if (sta->chandef.bw >= CHANNEL_WIDTH_80) + sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_80; + else if (sta->chandef.bw == CHANNEL_WIDTH_40) + sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_40; + else + sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_20; + sta->hal_sta->ra_info.csi_rate.gi_ltf = RTW_GILTF_LGI_4XHE32; + sta->hal_sta->ra_info.csi_rate.mcs_ss_idx = 5; + if (sta->wmode & WLAN_MD_11N) { + rrsc |= (BIT(HAL_BF_RRSC_HT_MSC0) | + BIT(HAL_BF_RRSC_HT_MSC3) | + BIT(HAL_BF_RRSC_HT_MSC5)); + sta->hal_sta->ra_info.csi_rate.mode = HAL_HT_MODE; + } + if (sta->wmode & WLAN_MD_11AC) { + rrsc |= (BIT(HAL_BF_RRSC_VHT_MSC0) | + BIT(HAL_BF_RRSC_VHT_MSC3) | + BIT(HAL_BF_RRSC_VHT_MSC5)); + sta->hal_sta->ra_info.csi_rate.mode = HAL_VHT_MODE; + } + if (sta->wmode & WLAN_MD_11AX) { + rrsc |= (BIT(HAL_BF_RRSC_HE_MSC0) | + BIT(HAL_BF_RRSC_HE_MSC3) | + BIT(HAL_BF_RRSC_HE_MSC5)); + sta->hal_sta->ra_info.csi_rate.mode = HAL_HE_MODE; + } + /* Initialize mac rrsc function */ + rtw_hal_mac_ax_bfee_set_csi_rrsc(hal_info->mac, + sta->wrole->hw_band, rrsc); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, " set bfee csi rrsc = 0x%x\n", rrsc); + } + + return status; +} + + + +/** + * hal_bf_hw_mac_init_bfer + * Initialize BFer HW Settings + * @hal_info: struct hal_info_t + * @band: Band 0 / Band 1 + **/ +enum rtw_hal_status hal_bf_hw_mac_init_bfer( + struct hal_info_t *hal_info, + u8 band) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + + do { + if (band >= 2) { + status = RTW_HAL_STATUS_FAILURE; + break; + } + status = rtw_hal_mac_ax_init_bf_role(hal_info->hal_com, + HAL_BF_ROLE_BFER, band); + if(status != RTW_HAL_STATUS_SUCCESS) + break; + /*TODO: Check Wireless Mode*/ + bf_obj->self_bf_cap[band] |= BF_CAP_HE_BFER|BF_CAP_VHT_BFER; + + } while (0); + + return status; +} + +/** + * rtw_hal_bf_chk_bf_type + * Check the STA's BF Entry Type + * @hal_info: struct hal_info_t + * @sta: rtw_phl_stainfo_t * + * @mu: check condition MU or SU? + * return : + * @ret: true : bf entry type is same to flag(mu) + * false : bf entry is not same to flag(mu) or bf entry is NULL + **/ +bool rtw_hal_bf_chk_bf_type( + void *hal_info, + struct rtw_phl_stainfo_t *sta, + bool mu) +{ + struct hal_bf_entry *bf_entry = + (struct hal_bf_entry *)sta->hal_sta->bf_entry; + bool ret = false; + do { + if (NULL == bf_entry) + break; + + if (bf_entry->bfee == NULL) + break; + + if (true == mu) { + if (HAL_BFEE_MU != bf_entry->bfee->type) + break; + } else { + if (HAL_BFEE_SU != bf_entry->bfee->type) + break; + } + + ret = true; + } while(0); + + return ret; +} + +u8 rtw_hal_bf_get_sumu_idx(void *hal, void *entry) +{ + struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry; + u8 ret = 0xFF; + if (bf_entry->bfee != NULL) + ret = bf_entry->bfee->idx; + + return ret; +} + + +void +rtw_hal_bf_preset_mu_ba_info( + void *hal, + struct rtw_phl_stainfo_t *psta, + void *hal_ba_info) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + void *drv_priv = hal_to_drvpriv(hal_info); + struct rtw_hal_muba_info *ba_info = + (struct rtw_hal_muba_info *)hal_ba_info; + + if (1 == bf_obj->fixed_para.fix_ba_info.fix_ba) { + /*Fixed BA info*/ + _os_mem_cpy(drv_priv, ba_info, &bf_obj->fixed_para.fix_ba_info, sizeof(*ba_info)); + } else { + /* TODO: Config BA by STA Capabiliy or default value*/ + ba_info->fix_ba = 0; + ba_info->ru_psd = 0; + ba_info->tf_rate = RTW_DATA_RATE_OFDM24; + ba_info->rf_gain_fix = 0; + ba_info->rf_gain_idx = 0; + ba_info->tb_ppdu_bw = (psta->chandef.bw == CHANNEL_WIDTH_80) ? 2 : 0; + ba_info->dcm = 0; + ba_info->ss = 0; + ba_info->mcs = 3; + ba_info->gi_ltf = 2; + ba_info->doppler = 0; + ba_info->stbc = 0; + ba_info->sta_coding = 0; + ba_info->tb_t_pe_nom = 0; + ba_info->pr20_bw_en = 0; + ba_info->ma_type = 0; + } +} + +void +rtw_hal_bf_set_txmu_para(void *hal, u8 gid , u8 en, + enum rtw_hal_protection_type rts_type, + enum rtw_hal_ack_resp_type ack_type) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_fixed_m_para *para = &bf_obj->fixed_para; + + para->fix_m = (1 == en) ? HAL_BF_FIX_M_MU : HAL_BF_FIX_M_DISABLE; + para->gid = gid; + para->fix_resp = en; + para->fix_prot = en; + if (en) { + para->prot_type = rts_type; + para->resp_type = ack_type; + } +} + +enum rtw_hal_status +rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj; + struct hal_bf_fixed_m_para *para = &bf_obj->fixed_para; + + + if (mu) { + status = rtw_hal_mac_ax_set_mu_fix_mode( + hal_info->mac, + para->gid, + para->prot_type, + para->resp_type, + (para->fix_m == HAL_BF_FIX_M_MU) ? true : false, + he, + para->fix_resp, + para->fix_prot); + } else { + /*TODO: Force SU*/ + } + return status; +} + +enum rtw_hal_status +hal_bf_set_mu_sta_fw(void *hal, struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_bf_entry *bf_entry = + (struct hal_bf_entry *)sta->hal_sta->bf_entry; + struct hal_sumu_entry *mu_entry = NULL; + + do { + if (NULL == bf_entry) + break; + + if (NULL == bf_entry->bfee) + break; + + mu_entry = bf_entry->bfee; + + if (HAL_BFEE_MU != mu_entry->type) + break; + + status = rtw_hal_mac_ax_mu_sta_upd( + hal_info->mac, + (u8)(sta->macid&0xFF), + mu_entry->idx, + sta->hal_sta->prot_type, + sta->hal_sta->resp_type, + sta->hal_sta->mugrp_bmp); + + } while (0); + + return status; +} + +void rtw_hal_beamform_set_vht_gid(void *hal, u8 band, + struct rtw_phl_gid_pos_tbl *tbl) +{ + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s()\n", __func__); + if (RTW_HAL_STATUS_SUCCESS != + rtw_hal_mac_bfee_set_vht_gid(hal, band, tbl)) { + PHL_INFO("%s : Error to set VHT GID Position to MAC !!! \n", + __func__); + } + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<-- %s()\n", __func__); +} + +enum rtw_hal_status rtw_hal_beamform_set_aid(void *hal, struct rtw_phl_stainfo_t *sta, u16 aid) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s() : set aid = %d\n", __func__, aid); + + /*TODO: halmac need provide api that only change AID */ + status = rtw_hal_mac_addr_cam_set_aid(hal_info, sta, aid); + + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n"); + } + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<-- %s()\n", __func__); + + return status; +} \ No newline at end of file diff --git a/phl/hal_g6/hal_beamform.h b/phl/hal_g6/hal_beamform.h new file mode 100644 index 0000000..5e65c32 --- /dev/null +++ b/phl/hal_g6/hal_beamform.h @@ -0,0 +1,200 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HAL_BEAMFORM_H__ +#define __HAL_BEAMFORM_H__ + +#define BF_MU_IDX_INVALID 0xFF + +#define BF_CAP_HT_BFEE BIT(0) +#define BF_CAP_HT_BFER BIT(1) +#define BF_CAP_VHT_BFEE BIT(2) +#define BF_CAP_VHT_BFER BIT(3) +#define BF_CAP_HE_BFEE BIT(4) +#define BF_CAP_HE_BFER BIT(5) + +#define IS_SUPPORT_ACT_AS_BFER(_cap) \ + (_cap & BF_CAP_HE_BFER) || (_cap & BF_CAP_VHT_BFER) \ + || (_cap & BF_CAP_HT_BFER) + +#define IS_SUPPORT_ACT_AS_BFEE(_cap) \ + (_cap & BF_CAP_HE_BFEE) || (_cap & BF_CAP_VHT_BFEE) \ + || (_cap & BF_CAP_HT_BFEE) + +//B[0:7] = {6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M} +//B[8:15] = HT MCS0~MCS7 +//B[16:23] = VHT 1SSMCS0~MCS7 +//B[24:31] = HE 1SSMCS0~MCS7 +enum hal_bf_rrsc_rata { + HAL_BF_RRSC_6M = 0, + HAL_BF_RRSC_9M = 1, + HAL_BF_RRSC_12M, + HAL_BF_RRSC_18M, + HAL_BF_RRSC_24M, + HAL_BF_RRSC_36M, + HAL_BF_RRSC_48M, + HAL_BF_RRSC_54M, + HAL_BF_RRSC_HT_MSC0, + HAL_BF_RRSC_HT_MSC1, + HAL_BF_RRSC_HT_MSC2, + HAL_BF_RRSC_HT_MSC3, + HAL_BF_RRSC_HT_MSC4, + HAL_BF_RRSC_HT_MSC5, + HAL_BF_RRSC_HT_MSC6, + HAL_BF_RRSC_HT_MSC7, + HAL_BF_RRSC_VHT_MSC0, + HAL_BF_RRSC_VHT_MSC1, + HAL_BF_RRSC_VHT_MSC2, + HAL_BF_RRSC_VHT_MSC3, + HAL_BF_RRSC_VHT_MSC4, + HAL_BF_RRSC_VHT_MSC5, + HAL_BF_RRSC_VHT_MSC6, + HAL_BF_RRSC_VHT_MSC7, + HAL_BF_RRSC_HE_MSC0, + HAL_BF_RRSC_HE_MSC1, + HAL_BF_RRSC_HE_MSC2, + HAL_BF_RRSC_HE_MSC3, + HAL_BF_RRSC_HE_MSC4, + HAL_BF_RRSC_HE_MSC5, + HAL_BF_RRSC_HE_MSC6, + HAL_BF_RRSC_HE_MSC7 = 31, + HAL_BF_RRSC_MAX = 32 +}; + +enum hal_bf_role { + HAL_BF_ROLE_BFEE, + HAL_BF_ROLE_BFER +}; + +enum hal_bfee_type { + HAL_BFEE_SU, + HAL_BFEE_MU +}; + +struct hal_sumu_entry { + _os_list list; + enum hal_bfee_type type; + u8 idx; + u8 snd_sts; /*0: Fail or Not Sound, 1: Sound Success*/ +}; +struct hal_bf_entry { + _os_list list; + u8 bf_idx; + u16 macid; + u16 aid12; + u8 band; + u16 csi_buf; + /* csi_buf for swap mode */ + bool en_swap; + u16 csi_buf_swap; + u8 couter; /*for swap*/ + struct hal_sumu_entry *bfee; +}; + +enum hal_bf_forced_mode{ + HAL_BF_FIX_M_DISABLE = 0, + HAL_BF_FIX_M_SU = 1, + HAL_BF_FIX_M_MU = 2 +}; +struct hal_bf_fixed_m_para { + enum hal_bf_forced_mode fix_m; + u8 gid; + u8 fix_resp; + u8 fix_prot; + enum rtw_hal_protection_type prot_type; + enum rtw_hal_ack_resp_type resp_type; + struct rtw_hal_muba_info fix_ba_info; +}; + +struct hal_bf_obj { + /*tx bf entry*/ + u8 max_bf_entry_nr; + struct hal_bf_entry *bf_entry; + _os_list bf_idle_list; + _os_list bf_busy_list; + u8 num_idle_bf_entry; + + /*su entry*/ + u8 max_su_bfee_nr; + struct hal_sumu_entry *su_entry; + _os_list su_idle_list; + _os_list su_busy_list; + u8 num_idle_su_entry; + + /*mu entry*/ + u8 max_mu_bfee_nr; + struct hal_sumu_entry *mu_entry; + _os_list mu_idle_list; + _os_list mu_busy_list; + u8 num_idle_mu_entry; + + _os_lock bf_lock; + + u8 self_bf_cap[2]; + /*for fixed mode*/ + struct hal_bf_fixed_m_para fixed_para; +}; + + +enum rtw_hal_status hal_bf_init( + struct hal_info_t *hal_info, + u8 bf_entry_nr, + u8 su_entry_nr, + u8 mu_entry_nr); + +void hal_bf_deinit(struct hal_info_t *hal_info); + + +struct hal_bf_entry * +hal_bf_query_idle_bf_entry( + struct hal_info_t *hal_info, + bool mu); + + +enum rtw_hal_status +hal_bf_release_target_bf_entry( + struct hal_info_t *hal_info, + void *entry); + + +enum rtw_hal_status hal_bf_hw_mac_init_bfee( + struct hal_info_t *hal_info, + u8 band); + +enum rtw_hal_status hal_bf_hw_mac_init_bfer( + struct hal_info_t *hal_info, + u8 band); + +enum rtw_hal_status hal_bf_set_entry_hwcfg( + struct hal_info_t *hal_info, void *entry); + +void hal_bf_update_entry_snd_sts(struct hal_info_t *hal_info, void *entry); + +enum rtw_hal_status hal_bf_cfg_swbf_entry(struct rtw_phl_stainfo_t *sta, + bool swap); + +enum rtw_hal_status +hal_bf_set_mu_sta_fw(void *hal, struct rtw_phl_stainfo_t *sta); + +enum rtw_hal_status +rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he); + +bool rtw_hal_bf_chk_bf_type(void *hal_info, + struct rtw_phl_stainfo_t *sta, bool mu); + +enum rtw_hal_status +hal_bf_set_bfee_csi_para(struct hal_info_t *hal_info, bool cr_cctl, + struct rtw_phl_stainfo_t *sta); + +#endif diff --git a/phl/hal_g6/hal_c2h.c b/phl/hal_g6/hal_c2h.c new file mode 100644 index 0000000..e746496 --- /dev/null +++ b/phl/hal_g6/hal_c2h.c @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_C2H_C_ +#include "hal_headers.h" + + +struct hal_c2h_hdl c2h_list[] = +{ + {C2H_CAT_OUTSRC, C2H_CLS_PHYDM_MIN, C2H_CLS_PHYDM_MAX, + rtw_hal_bb_process_c2h}, + {C2H_CAT_OUTSRC, C2H_CLS_BTC_MIN, C2H_CLS_BTC_MAX, + rtw_hal_btc_process_c2h}, + {C2H_CAT_MAC, C2H_CLS_MAC_MIN, C2H_CLS_MAC_MAX, + rtw_hal_mac_process_c2h}, + {C2H_CAT_MAX, C2H_CLS_MAX, C2H_CLS_MAX, NULL} +}; + +void hal_c2h_post_process(void *phl, void *hal, void *c2h) +{ + struct rtw_phl_com_t *phl_com = (struct rtw_phl_com_t *)phl; + struct rtw_c2h_info *c = (struct rtw_c2h_info *)c2h; + u8 i = 0; + u32 ret = 0; + + for (i = 0; C2H_CAT_MAX != c2h_list[i].cat; i++) { + if (c->c2h_cat == c2h_list[i].cat) { + if (c->c2h_class >= c2h_list[i].cls_min && + c->c2h_class <= c2h_list[i].cls_max) { + ret = c2h_list[i].c2h_hdl(hal, c2h); + break; + } + } + } + + if (ret > 0) { + /* submit phl msg hub */ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_RX); + SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)ret); + if (rtw_phl_msg_hub_hal_send(phl_com, &attr, &msg) != + RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_phl_msg_hub_hal_send failed\n", __func__); + } + } +} + diff --git a/phl/hal_g6/hal_c2h.h b/phl/hal_g6/hal_c2h.h new file mode 100644 index 0000000..6794b3d --- /dev/null +++ b/phl/hal_g6/hal_c2h.h @@ -0,0 +1,21 @@ + +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_C2H_H_ +#define _HAL_C2H_H_ + +void hal_c2h_post_process(void *phl, void *hal, void *c2h); + +#endif /*_HAL_C2H_H_*/ diff --git a/phl/hal_g6/hal_cam.c b/phl/hal_g6/hal_cam.c new file mode 100644 index 0000000..6d3e986 --- /dev/null +++ b/phl/hal_g6/hal_cam.c @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_CAM_C_ +#include "hal_headers.h" + +/** + * This function calls halmac api to configure security cam + * @hal: see struct hal_info_t + * @sta: sta info of specified address cam entry + * @type: encryption type of this key + * @ext_key: whether 256bit key or not + * @spp: spp mode + * @keyid: key index + * @keytype: specify unicast or multicast or bip key type + * @keybuf: key buffer length according to ext_key + * return enum RTW_HAL_STATUS + */ +enum rtw_hal_status +rtw_hal_set_key(void *hal, struct rtw_phl_stainfo_t *sta, u8 type, u8 ext_key, u8 spp, + u8 keyid, u8 keytype, u8 *keybuf) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 macid = (u8)sta->macid; + + if (keybuf == NULL) { + /* delete key */ + hal_status = rtw_hal_mac_delete_key(hal_info, macid, type, ext_key, + spp, keyid, keytype); + } else { + /* add key */ + if (ext_key) { + hal_status = rtw_hal_mac_add_key(hal_info, macid, type, ext_key, + spp, keyid, keytype, keybuf); + hal_status = rtw_hal_mac_add_key(hal_info, macid, type, ext_key, spp, + keyid, keytype, (keybuf+16)); + } else { + hal_status = rtw_hal_mac_add_key(hal_info, macid, type, 0, + spp, keyid, keytype, keybuf); + } + } + + return hal_status; +} + +u32 +rtw_hal_search_key_idx(void *hal, struct rtw_phl_stainfo_t *sta, + u8 keyid, u8 keytype) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u32 sec_cam_idx = 0; + u8 macid = (u8)sta->macid; + + sec_cam_idx = rtw_hal_mac_search_key_idx(hal_info, + macid, + keyid, + keytype); + + return sec_cam_idx; +} \ No newline at end of file diff --git a/phl/hal_g6/hal_cap.c b/phl/hal_g6/hal_cap.c new file mode 100644 index 0000000..a047831 --- /dev/null +++ b/phl/hal_g6/hal_cap.c @@ -0,0 +1,605 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "hal_headers.h" + +static void _hal_bus_cap_pre_decision(struct rtw_phl_com_t *phl_com, + void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; + struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap; + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + +#ifdef CONFIG_PCI_HCI + bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l0s_ctrl : bus_sw->l0s_ctrl; + bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l1_ctrl : bus_sw->l1_ctrl; + bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl; + bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->wake_ctrl : bus_sw->wake_ctrl; + bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->crq_ctrl : bus_sw->crq_ctrl; + + + bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl; + bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl; + bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl; + + + bus_cap->txbd_num = (bus_sw->txbd_num) ? + ((bus_sw->txbd_num > bus_hw->max_txbd_num) ? + bus_hw->max_txbd_num : bus_sw->txbd_num) : + bus_hw->max_txbd_num; + bus_cap->rxbd_num = (bus_sw->rxbd_num) ? + ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ? + bus_hw->max_rxbd_num : bus_sw->rxbd_num) : + bus_hw->max_rxbd_num; + bus_cap->rpbd_num = (bus_sw->rpbd_num) ? + ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ? + bus_hw->max_rpbd_num : bus_sw->rpbd_num) : + bus_hw->max_rpbd_num; + + /* rx buffer number must be larger or equal to rx bd number */ + bus_cap->rxbuf_num = (bus_sw->rxbuf_num < bus_cap->rxbd_num) ? + bus_cap->rxbd_num : bus_sw->rxbuf_num; + bus_cap->rpbuf_num = (bus_sw->rpbuf_num < bus_cap->rpbd_num) ? + bus_cap->rpbd_num : bus_sw->rpbuf_num; + + bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl; + bus_cap->ltr_act.val = bus_sw->ltr_act.val; + bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl; + bus_cap->ltr_idle.val = bus_sw->ltr_idle.val; + bus_cap->ltr_init_state = bus_sw->ltr_init_state; + bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ? + (bus_sw->ltr_sw_ctrl ? true : false) : false; + bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ? + (bus_sw->ltr_hw_ctrl ? true : false) : false; +#elif defined (CONFIG_USB_HCI) + bus_cap->tx_buf_size = (bus_sw->tx_buf_size) ? + ((bus_sw->tx_buf_size < bus_hw->tx_buf_size) ? + bus_sw->tx_buf_size : bus_hw->tx_buf_size) : + bus_hw->tx_buf_size; + bus_cap->tx_buf_num = (bus_sw->tx_buf_num) ? + ((bus_sw->tx_buf_num < bus_hw->tx_buf_num) ? + bus_sw->tx_buf_num : bus_hw->tx_buf_num) : + bus_hw->tx_buf_num; + bus_cap->tx_mgnt_buf_size = (bus_sw->tx_mgnt_buf_size) ? + ((bus_sw->tx_mgnt_buf_size < bus_hw->tx_mgnt_buf_size) ? + bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size) : + bus_hw->tx_mgnt_buf_size; + bus_cap->tx_mgnt_buf_num = (bus_sw->tx_mgnt_buf_num) ? + ((bus_sw->tx_mgnt_buf_num < bus_hw->tx_mgnt_buf_num) ? + bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num) : + bus_hw->tx_mgnt_buf_num; + bus_cap->tx_h2c_buf_num = (bus_sw->tx_h2c_buf_num) ? + ((bus_sw->tx_h2c_buf_num < bus_hw->tx_h2c_buf_num) ? + bus_sw->tx_h2c_buf_num : bus_hw->tx_h2c_buf_num) : + bus_hw->tx_h2c_buf_num; + bus_cap->rx_buf_size = (bus_sw->rx_buf_size) ? + ((bus_sw->rx_buf_size < bus_hw->rx_buf_size) ? + bus_sw->rx_buf_size : bus_hw->rx_buf_size) : + bus_hw->rx_buf_size; + bus_cap->rx_buf_num = (bus_sw->rx_buf_num) ? + ((bus_sw->rx_buf_num < bus_hw->rx_buf_num) ? + bus_sw->rx_buf_num : bus_hw->rx_buf_num) : + bus_hw->rx_buf_num; + bus_cap->in_token_num = (bus_sw->in_token_num) ? + ((bus_sw->in_token_num < bus_hw->in_token_num) ? + bus_sw->in_token_num : bus_hw->in_token_num) : + bus_hw->in_token_num; +#elif defined(CONFIG_SDIO_HCI) + bus_cap->tx_buf_size = bus_sw->tx_buf_size ? + bus_sw->tx_buf_size : bus_hw->tx_buf_size; + bus_cap->tx_buf_num = bus_sw->tx_buf_num ? + bus_sw->tx_buf_num : bus_hw->tx_buf_num; + bus_cap->tx_mgnt_buf_size = bus_sw->tx_mgnt_buf_size ? + bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size; + bus_cap->tx_mgnt_buf_num = bus_sw->tx_mgnt_buf_num ? + bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num; + bus_cap->rx_buf_size = bus_sw->rx_buf_size ? + bus_sw->rx_buf_size : bus_hw->rx_buf_size; + bus_cap->rx_buf_num = bus_sw->rx_buf_num ? + bus_sw->rx_buf_num : bus_hw->rx_buf_num; +#endif +} + +#ifdef CONFIG_PCI_HCI +static void _hal_bus_final_cap_decision(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com) +{ + struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; + struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap; + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + + bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l0s_ctrl : bus_sw->l0s_ctrl; + bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l1_ctrl : bus_sw->l1_ctrl; + bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl; + bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->wake_ctrl : bus_sw->wake_ctrl; + bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ? + bus_hw->crq_ctrl : bus_sw->crq_ctrl; + + bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl; + bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl; + bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ? + bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl; + + + bus_cap->txbd_num = (bus_sw->txbd_num) ? + ((bus_sw->txbd_num > bus_hw->max_txbd_num) ? + bus_hw->max_txbd_num : bus_sw->txbd_num) : + bus_hw->max_txbd_num; + bus_cap->rxbd_num = (bus_sw->rxbd_num) ? + ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ? + bus_hw->max_rxbd_num : bus_sw->rxbd_num) : + bus_hw->max_rxbd_num; + bus_cap->rpbd_num = (bus_sw->rpbd_num) ? + ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ? + bus_hw->max_rpbd_num : bus_sw->rpbd_num) : + bus_hw->max_rpbd_num; + + bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl; + bus_cap->ltr_act.val = bus_sw->ltr_act.val; + bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl; + bus_cap->ltr_idle.val = bus_sw->ltr_idle.val; + bus_cap->ltr_init_state = bus_sw->ltr_init_state; + bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ? + (bus_sw->ltr_sw_ctrl ? true : false) : false; + bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ? + (bus_sw->ltr_hw_ctrl ? true : false) : false; +} +#endif + +static void _hal_ps_final_cap_decision(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com) +{ + struct rtw_ps_cap_t *ps_cap = &phl_com->dev_cap.ps_cap; + struct rtw_ps_cap_t *ps_sw_cap = &phl_com->dev_sw_cap.ps_cap; + struct rtw_ps_cap_t *ps_hw_cap = &hal_com->dev_hw_cap.ps_cap; + + /* sw */ + ps_cap->init_rf_state = ps_sw_cap->init_rf_state; + ps_cap->init_rt_stop_rson = ps_sw_cap->init_rt_stop_rson; + ps_cap->leave_fail_act = ps_sw_cap->leave_fail_act; + ps_cap->ips_en = ps_sw_cap->ips_en; + ps_cap->ips_wow_en = ps_sw_cap->ips_wow_en; + ps_cap->lps_en = ps_sw_cap->lps_en; + ps_cap->lps_awake_interval = ps_sw_cap->lps_awake_interval; + ps_cap->lps_listen_bcn_mode = ps_sw_cap->lps_listen_bcn_mode; + ps_cap->lps_smart_ps_mode = ps_sw_cap->lps_smart_ps_mode; + ps_cap->lps_rssi_enter_threshold = ps_sw_cap->lps_rssi_enter_threshold; + ps_cap->lps_rssi_leave_threshold = ps_sw_cap->lps_rssi_leave_threshold; + ps_cap->lps_rssi_diff_threshold = ps_sw_cap->lps_rssi_diff_threshold; + ps_cap->lps_wow_en = ps_sw_cap->lps_wow_en; + ps_cap->lps_wow_awake_interval = ps_sw_cap->lps_wow_awake_interval; + ps_cap->lps_wow_listen_bcn_mode = ps_sw_cap->lps_wow_listen_bcn_mode; + ps_cap->lps_wow_smart_ps_mode = ps_sw_cap->lps_wow_smart_ps_mode; + /* hw */ + ps_cap->lps_pause_tx = ps_hw_cap->lps_pause_tx; + /* sw & hw */ + ps_cap->ips_cap = (ps_sw_cap->ips_cap & ps_hw_cap->ips_cap); + ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap); + ps_cap->lps_cap = (ps_sw_cap->lps_cap & ps_hw_cap->lps_cap); + ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap); +} + +static void _hal_edcca_final_cap_decision(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com) +{ + struct rtw_edcca_cap_t *edcca_cap = &phl_com->dev_cap.edcca_cap; + struct rtw_edcca_cap_t *edcca_sw_cap = &phl_com->dev_sw_cap.edcca_cap; + struct rtw_edcca_cap_t *edcca_hw_cap = &hal_com->dev_hw_cap.edcca_cap; + + edcca_cap->edcca_adap_th_2g = (edcca_sw_cap->edcca_adap_th_2g)? + (edcca_sw_cap->edcca_adap_th_2g): + (edcca_hw_cap->edcca_adap_th_2g); + edcca_cap->edcca_adap_th_5g = (edcca_sw_cap->edcca_adap_th_5g)? + (edcca_sw_cap->edcca_adap_th_5g): + (edcca_hw_cap->edcca_adap_th_5g); + + edcca_cap->edcca_carrier_sense_th = (edcca_sw_cap->edcca_carrier_sense_th)? + (edcca_sw_cap->edcca_carrier_sense_th): + (edcca_hw_cap->edcca_carrier_sense_th); +} + +void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal) +{ + + struct dev_cap_t *dev_cap = &phl_com->dev_cap; + struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap; + + /* leaving for fw hw cap + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap; + */ + + dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src; + dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en; + dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en; +} + +void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal) +{ + _hal_bus_cap_pre_decision(phl_com, hal); +} + + + +void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal) +{ + + struct dev_cap_t *dev_cap = &phl_com->dev_cap; + struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap; + + /* leaving for fw hw cap + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap; + */ + + dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src; + dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en; + dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en; +} + +void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct phy_hw_cap_t *phy_hw = hal_com->phy_hw_cap; + struct phy_sw_cap_t *phy_sw = phl_com->phy_sw_cap; + struct phy_cap_t *phy_cap = phl_com->phy_cap; + + struct dev_cap_t *dev_cap = &phl_com->dev_cap; + struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap; + struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap; + +#ifdef RTW_WKARD_PHY_CAP + phy_cap[0].proto_sup = phy_sw[0].proto_sup; + phy_cap[1].proto_sup = phy_sw[1].proto_sup; + phy_cap[0].band_sup = phy_sw[0].band_sup; + phy_cap[1].band_sup = phy_sw[1].band_sup; + phy_cap[0].bw_sup = phy_sw[0].bw_sup; + phy_cap[1].bw_sup = phy_sw[1].bw_sup; + + phy_cap[0].txss = (phy_sw[0].txss)?((phy_sw[0].txss > phy_hw[0].tx_num)? + phy_hw[0].tx_num:phy_sw[0].txss):phy_hw[0].tx_num; + phy_cap[0].rxss = (phy_sw[0].rxss)?((phy_sw[0].rxss > phy_hw[0].rx_num)? + phy_hw[0].rx_num:phy_sw[0].rxss):phy_hw[0].rx_num; + phy_cap[1].txss = (phy_sw[1].txss)?((phy_sw[1].txss > phy_hw[1].tx_num)? + phy_hw[1].tx_num:phy_sw[1].txss):phy_hw[1].tx_num; + phy_cap[1].rxss = (phy_sw[1].rxss)?((phy_sw[1].rxss > phy_hw[1].rx_num)? + phy_hw[1].rx_num:phy_sw[1].rxss):phy_hw[1].rx_num; + phy_cap[0].hw_rts_time_th = (phy_sw[0].hw_rts_time_th)? + phy_sw[0].hw_rts_time_th:phy_hw[0].hw_rts_time_th; + phy_cap[1].hw_rts_time_th = (phy_sw[1].hw_rts_time_th)? + phy_sw[1].hw_rts_time_th:phy_hw[1].hw_rts_time_th; + phy_cap[0].hw_rts_len_th = (phy_sw[0].hw_rts_len_th)? + phy_sw[0].hw_rts_len_th:phy_hw[0].hw_rts_len_th; + phy_cap[1].hw_rts_len_th = (phy_sw[1].hw_rts_len_th)? + phy_sw[1].hw_rts_len_th:phy_hw[1].hw_rts_len_th; + /* fw */ + rtw_hal_fw_final_cap_config(phl_com,hal); +#endif + +#ifdef RTW_WKARD_LAMODE + if (dev_sw_cap->la_mode && dev_hw_cap->la_mode) + dev_cap->la_mode = true; +#endif + + /* wow, to be refined along with hw cap */ + dev_cap->wow_cap.magic_sup = dev_sw_cap->wow_cap.magic_sup; + dev_cap->wow_cap.pattern_sup = dev_sw_cap->wow_cap.pattern_sup; + dev_cap->wow_cap.arp_ofld_sup = dev_sw_cap->wow_cap.arp_ofld_sup; + dev_cap->wow_cap.ns_oflod_sup = dev_sw_cap->wow_cap.ns_oflod_sup; + dev_cap->wow_cap.gtk_ofld_sup = dev_sw_cap->wow_cap.gtk_ofld_sup; + dev_cap->wow_cap.ping_pattern_wake_sup = dev_sw_cap->wow_cap.ping_pattern_wake_sup; + + if (dev_sw_cap->pkg_type != 0xFF) + dev_cap->pkg_type = dev_sw_cap->pkg_type; + else + dev_cap->pkg_type = dev_hw_cap->pkg_type; + + if (dev_sw_cap->rfe_type != 0xFF) + dev_cap->rfe_type = dev_sw_cap->rfe_type; + else + dev_cap->rfe_type = dev_hw_cap->rfe_type; + + dev_cap->bypass_rfe_chk = dev_sw_cap->bypass_rfe_chk; + + hal_com->dbcc_en = false;/*init default value*/ +#ifdef CONFIG_DBCC_SUPPORT + if (dev_sw_cap->dbcc_sup && dev_hw_cap->dbcc_sup) + dev_cap->dbcc_sup = true; + /*TODO - update dbcc_en from sw & hw cap + if (dev_cap->dbcc_sup && dft->dbcc_en) + hal_com->dbcc_en = true; + */ +#endif + +#ifdef CONFIG_MCC_SUPPORT + if (dev_sw_cap->mcc_sup && dev_hw_cap->mcc_sup) + dev_cap->mcc_sup = true; +#endif /*CONFIG_MCC_SUPPORT*/ + +#ifdef CONFIG_PHL_TWT + dev_cap->twt_sup = (dev_sw_cap->twt_sup & dev_hw_cap->twt_sup); +#endif /*CONFIG_PHL_TWT*/ + + if (dev_sw_cap->hw_hdr_conv && dev_hw_cap->hw_hdr_conv) + dev_cap->hw_hdr_conv = true; + if (dev_sw_cap->tx_mu_ru && dev_hw_cap->tx_mu_ru) + dev_cap->tx_mu_ru = true; + + dev_cap->xcap = dev_hw_cap->xcap; + dev_cap->domain = dev_hw_cap->domain; + dev_cap->btc_mode = dev_sw_cap->btc_mode; + +#ifdef CONFIG_PCI_HCI + _hal_bus_final_cap_decision(phl_com, hal_com); +#endif + + if (dev_sw_cap->pwrbyrate_off != 0xFF) + dev_cap->pwrbyrate_off = dev_sw_cap->pwrbyrate_off; + else + dev_cap->pwrbyrate_off = PW_BY_RATE_ON; + + if (dev_sw_cap->pwrlmt_type != 0xFF) + dev_cap->pwrlmt_type = dev_sw_cap->pwrlmt_type; + else + dev_cap->pwrlmt_type = PWLMT_BY_EFUSE; + + if (dev_sw_cap->rf_board_opt != 0xFF) + dev_cap->rf_board_opt = dev_sw_cap->rf_board_opt; + else + dev_cap->rf_board_opt = dev_hw_cap->rf_board_opt; + + if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru) { + /* auto : use hw default setting */ + dev_cap->sta_ulru = dev_hw_cap->sta_ulru; + } else { + /* forced use sw settings */ + dev_cap->sta_ulru = dev_sw_cap->sta_ulru; + } + PHL_INFO("sta_ulru final : 0x%x ; sw 0x%x ; hw 0x%x\n", + dev_cap->sta_ulru, dev_sw_cap->sta_ulru, dev_hw_cap->sta_ulru); + +#ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA + /* 2.4G 40MHz UL OFDAM : bb ask to disable */ + if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru_2g40mhz) { + /* auto : use hw default setting */ + dev_cap->sta_ulru_2g40mhz = dev_hw_cap->sta_ulru_2g40mhz; + } else { + /* forced use sw settings */ + dev_cap->sta_ulru_2g40mhz = dev_sw_cap->sta_ulru_2g40mhz; + } + PHL_INFO("sta_ulru_2g40mhz final : 0x%x ; sw 0x%x ; hw 0x%x\n", + dev_cap->sta_ulru_2g40mhz, dev_sw_cap->sta_ulru_2g40mhz, dev_hw_cap->sta_ulru_2g40mhz); +#endif + + _hal_ps_final_cap_decision(phl_com, hal_com); + + _hal_edcca_final_cap_decision(phl_com, hal_com); + + if (dev_hw_cap->hw_stype_cap != EFUSE_HW_STYPE_GENERAL) + dev_cap->hw_stype_cap = dev_hw_cap->hw_stype_cap; + else + dev_cap->hw_stype_cap = EFUSE_HW_STYPE_NONE; + + if (dev_hw_cap->wl_func_cap != EFUSE_WL_FUNC_GENERAL) + dev_cap->wl_func_cap = dev_hw_cap->wl_func_cap; + else + dev_cap->wl_func_cap = EFUSE_WL_FUNC_NONE; + + dev_cap->rpq_agg_num = dev_sw_cap->rpq_agg_num ? + dev_sw_cap->rpq_agg_num : dev_hw_cap->rpq_agg_num; +} + +/** + * rtw_hal_get_bf_proto_cap + * input: + * @phl: (struct phl_info_t *phl_info) + * @band: + * input_output: + * @proto_cap: (struct protocol_cap_t *proto_cap) the variable to save the bf_cap result. + * return: + * @rtw_hal_status: + */ +enum rtw_hal_status +rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal, + u8 band, struct protocol_cap_t *proto_cap) +{ +#ifdef RTW_WKARD_PHY_CAP + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct protocol_cap_t *hw_cap = NULL; + struct protocol_cap_t *sw_cap = NULL; + + if (band >= HW_BAND_MAX) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : invalid band index \n"); + return RTW_HAL_STATUS_FAILURE; + } + if (proto_cap == NULL) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : input proto_cap is NULL \n"); + return RTW_HAL_STATUS_FAILURE; + } + + + hw_cap = &hal_com->proto_hw_cap[band]; + sw_cap = &phl_com->proto_sw_cap[band]; + + proto_cap->he_su_bfmr = + (sw_cap->he_su_bfmr && hw_cap->he_su_bfmr) ? 1 : 0; + proto_cap->he_su_bfme = + (sw_cap->he_su_bfme && hw_cap->he_su_bfme) ? 1 : 0; + proto_cap->he_mu_bfmr = + (sw_cap->he_mu_bfmr && hw_cap->he_mu_bfmr) ? 1 : 0; + proto_cap->he_mu_bfme = + (sw_cap->he_mu_bfme && hw_cap->he_mu_bfme) ? 1 : 0; + proto_cap->non_trig_cqi_fb = + (sw_cap->non_trig_cqi_fb && hw_cap->non_trig_cqi_fb) ? 1 : 0; + proto_cap->trig_cqi_fb = + (sw_cap->trig_cqi_fb && hw_cap->trig_cqi_fb) ? 1 : 0; + + proto_cap->vht_su_bfme = + (sw_cap->vht_su_bfme && hw_cap->vht_su_bfme) ? 1 : 0; + proto_cap->vht_su_bfmr = + (sw_cap->vht_su_bfmr && hw_cap->vht_su_bfmr) ? 1 : 0; + proto_cap->vht_mu_bfme = + (sw_cap->vht_mu_bfme && hw_cap->vht_mu_bfme) ? 1 : 0; + proto_cap->vht_mu_bfmr = + (sw_cap->vht_mu_bfmr && hw_cap->vht_mu_bfmr) ? 1 : 0; + + proto_cap->ht_su_bfme = + (sw_cap->ht_su_bfme && hw_cap->ht_su_bfme) ? 1 : 0; + proto_cap->ht_su_bfmr = + (sw_cap->ht_su_bfmr && hw_cap->ht_su_bfmr) ? 1 : 0; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfmr = 0x%x \n", + proto_cap->he_su_bfmr); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfme = 0x%x \n", + proto_cap->he_su_bfme); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfmr = 0x%x \n", + proto_cap->he_mu_bfmr); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfme = 0x%x \n", + proto_cap->he_mu_bfme); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->non_trig_cqi_fb = 0x%x \n", + proto_cap->non_trig_cqi_fb); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->trig_cqi_fb = 0x%x \n", + proto_cap->trig_cqi_fb); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfme = 0x%x \n", + proto_cap->vht_su_bfme); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfmr = 0x%x \n", + proto_cap->vht_su_bfmr); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfme = 0x%x \n", + proto_cap->vht_mu_bfme); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfmr = 0x%x \n", + proto_cap->vht_mu_bfmr); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfme = 0x%x \n", + proto_cap->ht_su_bfme); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfmr = 0x%x \n", + proto_cap->ht_su_bfmr); +#endif + return RTW_HAL_STATUS_SUCCESS; +} + + +/** + * rtw_hal_get_stbc_proto_cap() - Get the intersection proto_cap of the proto_hw_cap and proto_sw_cap + * @phl_com: input, the pointer of phl_com (struct rtw_phl_com_t) + * @hal: input, the pointer of hal (struct hal_info_t) + * @band: input, the band index + * @proto_cap: input_output (struct protocol_cap_t) + * The variable pointer to save the ouput proto_cap results. + * Here, we update STBC cap into STBC fileds of proto_cap. + * Return: return the result of getting proto_cap (enum @rtw_hal_status) + */ +enum rtw_hal_status +rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal, + u8 band, struct protocol_cap_t *proto_cap) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct protocol_cap_t *hw_cap = NULL; + struct protocol_cap_t *sw_cap = NULL; + + if (band >= HW_BAND_MAX) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : invalid band index \n"); + return RTW_HAL_STATUS_FAILURE; + } + if (proto_cap == NULL) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : input proto_cap is NULL \n"); + return RTW_HAL_STATUS_FAILURE; + } + + hw_cap = &hal_com->proto_hw_cap[band]; + sw_cap = &phl_com->proto_sw_cap[band]; + + proto_cap->stbc_tx = + (sw_cap->stbc_tx && hw_cap->stbc_tx) ? 1 : 0; /* Remove later */ + proto_cap->stbc_ht_tx = + (sw_cap->stbc_ht_tx && hw_cap->stbc_ht_tx) ? 1 : 0; + proto_cap->stbc_vht_tx = + (sw_cap->stbc_vht_tx && hw_cap->stbc_vht_tx) ? 1 : 0; + proto_cap->stbc_he_tx = + (sw_cap->stbc_he_tx && hw_cap->stbc_he_tx) ? 1 : 0; + proto_cap->stbc_tx_greater_80mhz = + (sw_cap->stbc_tx_greater_80mhz && hw_cap->stbc_tx_greater_80mhz) ? 1 : 0; + + proto_cap->stbc_ht_rx = + (sw_cap->stbc_ht_rx <= hw_cap->stbc_ht_rx) ? + sw_cap->stbc_ht_rx : hw_cap->stbc_ht_rx; + proto_cap->stbc_vht_rx = + (sw_cap->stbc_vht_rx <= hw_cap->stbc_vht_rx) ? + sw_cap->stbc_vht_rx : hw_cap->stbc_vht_rx; + proto_cap->stbc_he_rx = + (sw_cap->stbc_he_rx && hw_cap->stbc_he_rx) ? 1 : 0; + proto_cap->stbc_rx_greater_80mhz = + (sw_cap->stbc_rx_greater_80mhz && hw_cap->stbc_rx_greater_80mhz) ? 1 : 0; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_tx = 0x%x \n", + __func__, proto_cap->stbc_tx); /* Remove later */ + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_ht_tx = 0x%x \n", + __func__, proto_cap->stbc_ht_tx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_vht_tx = 0x%x \n", + __func__, proto_cap->stbc_vht_tx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_he_tx = 0x%x \n", + __func__, proto_cap->stbc_he_tx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_tx_greater_80mhz = 0x%x \n", + __func__, proto_cap->stbc_tx_greater_80mhz); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_ht_rx = 0x%x \n", + __func__, proto_cap->stbc_ht_rx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_vht_rx = 0x%x \n", + __func__, proto_cap->stbc_vht_rx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_he_rx = 0x%x \n", + __func__, proto_cap->stbc_he_rx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : proto_cap->stbc_rx_greater_80mhz = 0x%x \n", + __func__, proto_cap->stbc_rx_greater_80mhz); + + return RTW_HAL_STATUS_SUCCESS; +} diff --git a/phl/hal_g6/hal_chan.c b/phl/hal_g6/hal_chan.c new file mode 100644 index 0000000..fbcfa8d --- /dev/null +++ b/phl/hal_g6/hal_chan.c @@ -0,0 +1,172 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_CHAN_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_DFS +enum rtw_hal_status +rtw_hal_radar_detect_cfg(void *hal, bool dfs_enable) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 rpt_num = 0;/*52A - 29/61/93/125 pkt*/ + u8 rpt_to = 1;/*52A CAV - 0 , 80us ,2ms, CBV - 0 / 20ms / 40ms / 80ms*/ + + PHL_INFO("====>%s dfs_en:%d ============\n", __func__, dfs_enable); + if (dfs_enable) { + rtw_hal_mac_dfs_rpt_cfg(hal_info, true, rpt_num, rpt_to); + rtw_hal_bb_dfs_rpt_cfg(hal_info, true); + } + else { + rtw_hal_mac_dfs_rpt_cfg(hal_info, false, 0, 0); + rtw_hal_bb_dfs_rpt_cfg(hal_info, true); + } + return RTW_HAL_STATUS_SUCCESS; +} +#endif /*CONFIG_PHL_DFS*/ + +enum rtw_hal_status rtw_hal_set_ch_bw(void *hal, u8 band_idx, + struct rtw_chan_def *chdef, bool do_rfk) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_chan_def *cur_chdef = &(hal_com->band[band_idx].cur_chandef); + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + u8 center_ch = 0; + u8 central_ch_seg1 = 0; + enum band_type change_band; + enum phl_phy_idx phy_idx = HW_PHY_0; + + if ((chdef->chan != cur_chdef->chan) || + (chdef->bw != cur_chdef->bw) || + (chdef->offset != cur_chdef->offset)) { + if (band_idx == 1) + phy_idx = HW_PHY_1; + + status = rtw_hal_reset(hal_com, phy_idx, band_idx, true); + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_reset en - failed\n", __func__); + _os_warn_on(1); + } + /* if central channel changed, reset BB & MAC */ + center_ch = rtw_phl_get_center_ch(chdef->chan, chdef->bw, chdef->offset); + PHL_INFO("Using central channel %u for primary channel %u BW %u\n", + center_ch, chdef->chan, chdef->bw); + + change_band = chdef->band; + + status = rtw_hal_mac_set_bw(hal_info, band_idx, chdef->chan, + center_ch, central_ch_seg1, change_band, + chdef->bw); + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_mac_set_bw - failed\n", __func__); + return status; + } + + + if(chdef->bw == CHANNEL_WIDTH_80_80 && central_ch_seg1 == 0) { + PHL_ERR("%s mising info for 80+80M configuration\n", __func__); + return RTW_HAL_STATUS_FAILURE; + } + status = rtw_hal_bb_set_ch_bw(hal_info, phy_idx, chdef->chan, + center_ch, central_ch_seg1, change_band, + chdef->bw); + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_bb_set_ch_bw - failed\n", __func__); + return status; + } + + status = rtw_hal_rf_set_ch_bw(hal_info, phy_idx, center_ch, change_band, chdef->bw); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_rf_set_ch_bw - failed\n", __func__); + return status; + } + + cur_chdef->chan = chdef->chan; + cur_chdef->bw = chdef->bw; + cur_chdef->center_ch = center_ch; + + if (cur_chdef->band != change_band) { + cur_chdef->band = change_band; + rtw_hal_notify_switch_band(hal, change_band, phy_idx); + } + + status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_rf_set_power - failed\n", __func__); + return status; + } + + status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT_RU); + + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_rf_set_power - failed\n", __func__); + return status; + } + + PHL_INFO("%s band_idx:%d, ch:%d, bw:%d, offset:%d\n", + __func__, band_idx, chdef->chan, chdef->bw, chdef->offset); + + status = rtw_hal_reset(hal_com, phy_idx, band_idx, false); + if(status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_reset dis- failed\n", __func__); + _os_warn_on(1); + } + + /*PHL_DUMP_CHAN_DEF_EX(chandef);*/ + } + if (do_rfk) { + status = rtw_hal_rf_chl_rfk_trigger(hal_info, phy_idx, true); + if (status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_rf_chl_rfk_trigger fail!\n"); + } + PHL_INFO("%s: Switch chdef done, do_rfk:%s\n", __func__, + (do_rfk) ? "Y" : "N"); + return status; +} + +u8 rtw_hal_get_cur_ch(void *hal, u8 band_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_chan_def *chandef = &(hal_com->band[band_idx].cur_chandef); + + return chandef->chan; +} + +void rtw_hal_get_cur_chdef(void *hal, u8 band_idx, + struct rtw_chan_def *cur_chandef) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_chan_def *chandef = &(hal_com->band[band_idx].cur_chandef); + void *drv = hal_com->drv_priv; + + _os_mem_cpy(drv, cur_chandef, chandef, sizeof(struct rtw_chan_def)); +} + +void rtw_hal_sync_cur_ch(void *hal, u8 band_idx, struct rtw_chan_def chandef) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_chan_def *cur_chandef = &(hal_com->band[band_idx].cur_chandef); + + PHL_INFO("%s: Sync cur chan to ch:%d bw:%d offset:%d\n", + __FUNCTION__, chandef.chan, chandef.bw, chandef.offset); + cur_chandef->chan = chandef.chan; + cur_chandef->bw = chandef.bw; + cur_chandef->offset = chandef.offset; +} diff --git a/phl/hal_g6/hal_chan.h b/phl/hal_g6/hal_chan.h new file mode 100644 index 0000000..300615d --- /dev/null +++ b/phl/hal_g6/hal_chan.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_CHAN_H_ +#define _HAL_CHAN_H_ + +enum rtw_hal_status rtw_hal_set_ch_bw(void *hal, u8 band_idx, + struct rtw_chan_def *chdef, bool do_rfk); + + +#ifdef DBG_PHL_CHAN +void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller, + struct rtw_chan_def *chandef); +#define PHL_DUMP_CHAN_DEF(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, false, _chandef); +#define PHL_DUMP_CHAN_DEF_EX(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, true, _chandef); +#else +#define PHL_DUMP_CHAN_DEF(_chandef) +#define PHL_DUMP_CHAN_DEF_EX(_chandef) +#endif + +#endif /* _HAL_CHAN_H_ */ + diff --git a/phl/hal_g6/hal_chan_info.c b/phl/hal_g6/hal_chan_info.c new file mode 100644 index 0000000..e64d188 --- /dev/null +++ b/phl/hal_g6/hal_chan_info.c @@ -0,0 +1,103 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_CHAN_INFO_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_CHANNEL_INFO + +enum rtw_hal_status +rtw_hal_cfg_chinfo(void *hal, struct rtw_phl_stainfo_t *sta, u8 enable) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct chinfo_bbcr_cfg bbcr = {0}; + u8 mode = 0, filter = 0, sg_size = 0; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 macid = (u8)sta->macid; + /* + *TODO: Discuss how to config accroding to different mode. + * Currently, macid, mode, filter, sg_size use default value, + * which is hard code in rtw_hal_mac_chan_info_cfg. + */ + hal_status = rtw_hal_mac_chan_info_cfg(hal_info, enable, macid, mode, filter, sg_size); + if (hal_status == RTW_HAL_STATUS_SUCCESS) { + if (enable) { + /* + *Below is Example code for BBCR set to Legacy channel 80MHz + *TODO 1: need to calculate channel raw data size to see if + * it is acceptable. + *TODO 2: there should be 10 sets of pre-defined configuration for BBCR. + * need to decide which CR to use. + */ + bbcr.ch_i_phy0_en =1; + bbcr.ch_i_phy1_en = 0; + bbcr.ch_i_grp_num_he = 1; + bbcr.ch_i_grp_num_non_he = 1; + bbcr.ch_i_data_src = 0; /*LS, channel estimation*/ + bbcr.ch_i_cmprs = 0; /*8 bits*/ + bbcr.ch_i_ele_bitmap = 0x101; + bbcr.ch_i_blk_start_idx = 1; + bbcr.ch_i_blk_end_idx = 10; + bbcr.ch_i_type = 0; /* legacy channel*/ + bbcr.ch_i_seg_len = 0; /*12*/ + rtw_hal_bb_chan_info_cfg(hal_info, &bbcr); + } + } + + return hal_status; +} + +void +_hal_fill_csi_header_remain(void* hal, struct csi_header_t *csi_header + , struct rtw_r_meta_data *mdata) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *h = hal_info->hal_com; + + /* from mdata */ + csi_header->hw_assigned_timestamp = mdata->freerun_cnt; + csi_header->rx_data_rate = mdata->rx_rate; + csi_header->bandwidth = mdata->bw; + csi_header->ch_matrix_report = mdata->get_ch_info; + /* TODO: from drv define, get value from other side.*/ + csi_header->channel = 0; + csi_header->num_sub_carrier = 0; + csi_header->num_bit_per_tone = 0; + /* Others: mac addres not from TA ? */ + /* hal_mem_cpy(h, &(csi_header->mac_addr[0]), &(mdata->ta[0]), MAC_ALEN); */ +} + +void +_hal_fill_csi_header_phy_info(void* hal, struct csi_header_t *csi_header + , struct ch_rpt_hdr_info *ch_hdr_rpt, struct phy_info_rpt *phy_info) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *h = hal_info->hal_com; + + /* Initialize csi header */ + hal_mem_set(h, csi_header, 0, sizeof(struct csi_header_t)); + /* from phy_info_rpt */ + hal_mem_cpy(h, &(csi_header->rssi[0]), &(phy_info->rssi[0]), 2); + csi_header->rxsc = phy_info->rxsc; + /* from ch_rpt_hdr_info */ + csi_header->nc = ch_hdr_rpt->n_rx; + csi_header->nr = ch_hdr_rpt->n_sts; + csi_header->avg_idle_noise_pwr = ch_hdr_rpt->avg_noise_pow; + csi_header->csi_data_length = (ch_hdr_rpt->total_len_l <<16 | ch_hdr_rpt->total_len_m) + - 16; /* header(8byte) + Phy_info_in_seg_0(8byte) */ + csi_header->csi_valid = ch_hdr_rpt->set_valid; + hal_mem_cpy(h, &(csi_header->evm[0]), &(ch_hdr_rpt->evm[0]), 2); +} + +#endif /* CONFIG_PHL_CHANNEL_INFO */ \ No newline at end of file diff --git a/phl/hal_g6/hal_chan_info.h b/phl/hal_g6/hal_chan_info.h new file mode 100644 index 0000000..c36161d --- /dev/null +++ b/phl/hal_g6/hal_chan_info.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_CHAN_INFO_H_ +#define _HAL_CHAN_INFO_H_ + +#ifdef CONFIG_PHL_CHANNEL_INFO + +void +_hal_fill_csi_header_remain(void* hal, struct csi_header_t *csi_header + , struct rtw_r_meta_data *mdata); + +void +_hal_fill_csi_header_phy_info(void* hal, struct csi_header_t *csi_header + , struct ch_rpt_hdr_info *ch_hdr_rpt, struct phy_info_rpt *phy_info); + +#endif /* CONFIG_PHL_CHANNEL_INFO */ +#endif /* _HAL_CHAN_INFO_H_ */ + diff --git a/phl/hal_g6/hal_com_i.c b/phl/hal_g6/hal_com_i.c new file mode 100644 index 0000000..d0a86a8 --- /dev/null +++ b/phl/hal_g6/hal_com_i.c @@ -0,0 +1,334 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_COM_I_C_ +#define _HAL_COM_I_C_ +#include "hal_headers.h" + +void +rtw_hal_com_scan_set_tx_lifetime(void *hal, u8 band) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + /* set mgnt queue pkt lifetime */ +#define HAL_COM_MGQ_TX_LIFETIME_MS 19 + rtw_hal_mac_set_tx_lifetime(hal_info, band, false, true, 0, + (HAL_COM_MGQ_TX_LIFETIME_MS * 1000)); +} + +void rtw_hal_com_scan_restore_tx_lifetime(void *hal, u8 band) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + /* reset data/mgnt queue pkt lifetime to 0 */ + rtw_hal_mac_set_tx_lifetime(hal_info, band, false, false, 0, 0); + +} + +enum rtw_hal_status rtw_hal_scan_pause_tx_fifo(void *hinfo, + u8 band_idx, bool off_ch) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hinfo; + + + hal_status = rtw_hal_tx_pause(hal_info->hal_com, band_idx, + off_ch, PAUSE_RSON_NOR_SCAN); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_dfs_pause_tx(void *hinfo, + u8 band_idx, bool off_ch) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hinfo; + + hal_status = rtw_hal_tx_pause(hal_info->hal_com, band_idx, + off_ch, PAUSE_RSON_DFS); + + return hal_status; +} + +#ifdef CONFIG_FSM +enum rtw_hal_status rtw_hal_scan_flush_queue(void *hinfo, + struct rtw_wifi_role_t *wrole) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hinfo; + int wait = 5/* 10ms */, hal_status; + u8 val8; +#if 0 + struct phl_queue *sta_queue; + struct rtw_phl_stainfo_t *sta; + void *drv = hal_to_drvpriv(hal_info); + _os_list *sta_list; + u8 rts_txcnt_lmt_sel = 1; + u8 rts_txcnt_lmt = 1; + u8 data_txcnt_lmt_sel = 1; + u8 data_tx_cnt_lmt = 1; +#endif + hal_status = rtw_hal_mac_is_tx_mgnt_empty(hal_info, wrole->hw_band, &val8); + + if (val8) + return RTW_HAL_STATUS_SUCCESS; + +#if 0 + sta_queue = &wrole->assoc_sta_queue; + sta_list = &sta_queue->queue; + + /* TODO wait halmac api */ + /* shorten retry limit */ + _os_spinlock(drv, &sta_queue->lock, _bh, NULL); + phl_list_for_loop(sta, struct rtw_phl_stainfo_t, sta_list, list) { + rtw_hal_mac_set_rty_lmt(hal_info->hal_com, sta->macid, + rts_txcnt_lmt_sel, rts_txcnt_lmt, + data_txcnt_lmt_sel, data_tx_cnt_lmt); + } + _os_spinunlock(drv, &sta_queue->lock, _bh, NULL); +#endif + while (wait-- && (!val8)) { + _os_delay_ms(hal_info->hal_com->drv_priv, 2); + rtw_hal_mac_is_tx_mgnt_empty(hal_info, wrole->hw_band, &val8); + } +#if 0 + /* restore retry limit */ + if (wrole->cap.rty_lmt_rts == 0xFF) + rts_txcnt_lmt_sel = 0; + else + rts_txcnt_lmt = wrole->cap.rty_lmt_rts & 0xF; + + if (wrole->cap.rty_lmt == 0xFF) + data_txcnt_lmt_sel = 0; + else + data_tx_cnt_lmt = wrole->cap.rty_lmt & 0x3F; + + rtw_hal_mac_set_rty_lmt(hal_info->hal_com, sta->macid, + rts_txcnt_lmt_sel, rts_txcnt_lmt, + data_txcnt_lmt_sel, data_tx_cnt_lmt); +#endif + if (val8 == DLE_QUEUE_EMPTY) + return RTW_HAL_STATUS_SUCCESS; + + return RTW_HAL_STATUS_FAILURE; +} +#endif + +enum rtw_hal_status rtw_hal_notify_switch_band(void *hinfo, + enum band_type band, enum phl_phy_idx phy_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hinfo; + +#ifdef CONFIG_BTCOEX + rtw_hal_btc_switch_band_ntfy(hal_info, phy_idx, band); +#endif + + rtw_hal_bb_fw_edcca(hal_info); + + rtw_hal_rf_set_power(hal_info, phy_idx, PWR_BY_RATE); + + rtw_hal_rf_do_tssi_scan(hal_info, phy_idx); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_proc_cmd(void *hal, char proc_cmd, struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if(proc_cmd == RTW_PROC_CMD_BB){ + if(rtw_hal_bb_proc_cmd(hal_info, incmd, output, out_len)) + hal_status = RTW_HAL_STATUS_SUCCESS; + } + if(proc_cmd == RTW_PROC_CMD_RF){ + if(rtw_hal_rf_proc_cmd(hal_info, incmd, output, out_len)) + hal_status = RTW_HAL_STATUS_SUCCESS; + } + if(proc_cmd == RTW_PROC_CMD_MAC){ + if(rtw_hal_mac_proc_cmd(hal_info, incmd, output, out_len)) + hal_status = RTW_HAL_STATUS_SUCCESS; + } +#ifdef CONFIG_BTCOEX + if(proc_cmd == RTW_PROC_CMD_BTC){ + if(rtw_hal_btc_proc_cmd(hal_info, incmd, output, out_len)) + hal_status = RTW_HAL_STATUS_SUCCESS; + } +#endif + if(proc_cmd == RTW_PROC_CMD_EFUSE){ + if(rtw_hal_efuse_proc_cmd(hal_info, incmd, output, out_len)) + hal_status = RTW_HAL_STATUS_SUCCESS; + } + return hal_status; +} + +void rtw_hal_get_fw_ver(void *hal, char *ver_str, u16 len) +{ + rtw_hal_mac_get_fw_ver((struct hal_info_t *)hal, ver_str, len); +} + +enum rtw_hal_status +rtw_hal_set_mu_edca(void *hal, u8 band, u8 ac, + u16 timer, u8 cw_min, u8 cw_max, u8 aifsn) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u16 timer_32us; + u8 aifs_us; + u8 slot_time, sifs; + + /* TODO: Get aSlotTime and aSIFS according to current PHY */ + slot_time = 9; + sifs = 16; + timer_32us = (timer<<8); + aifs_us = (aifsn == 0)?0:(aifsn*slot_time + sifs); + hal_status = rtw_hal_mac_set_mu_edca(hal_info->hal_com, + band, ac, timer_32us, cw_min, cw_max, aifs_us); + return hal_status; +} + +enum rtw_hal_status +rtw_hal_set_mu_edca_ctrl(void *hal, u8 band, u8 wmm, u8 set) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_set_mu_edca_ctrl(hal_info->hal_com, + band, wmm, set); + return hal_status; +} +enum rtw_hal_status +rtw_hal_reset(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx, u8 band_idx, bool reset) +{ + struct hal_info_t *hal_info = hal_com->hal_priv; + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + if (reset){ + /* disable contention */ + status = rtw_hal_tx_pause(hal_com, band_idx, true, PAUSE_RSON_RESET); + if(status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("%s rtw_hal_tx_pause - failed\n", __func__); + return status; + } + + /* disable ppdu_sts */ + status = rtw_hal_mac_ppdu_stat_cfg(hal_info, band_idx, false, 0, 0); + if(status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("%s rtw_hal_mac_ppdu_stat_cfg - failed\n", __func__); + return status; + } + + /*disable DFS/TSSI*/ + rtw_hal_bb_dfs_en(hal_info, false); + if (!hal_com->dbcc_en) { + rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_A); + rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_B); + }else{ + if(phy_idx == HW_PHY_0) + rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_A); + else + rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_B); + } + /*disable ADC*/ + rtw_hal_bb_adc_en(hal_info, false); + /* wait 40us*/ + _os_delay_us(hal_com->drv_priv, 40); + /* reset BB*/ + rtw_hal_bb_reset_en(hal_info, false, phy_idx); + }else{ + /*enable ppdu_sts*/ + status = rtw_hal_mac_ppdu_stat_cfg( + hal_info, band_idx, true, + hal_com->band[band_idx].ppdu_sts_appen_info, + hal_com->band[band_idx].ppdu_sts_filter); + + if(status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("%s rtw_hal_mac_ppdu_stat_cfg - failed\n", __func__); + return status; + } + /*enable ADC*/ + rtw_hal_bb_adc_en(hal_info, true); + /*enable DFS/TSSI*/ + rtw_hal_bb_dfs_en(hal_info, true); + if (!hal_com->dbcc_en) { + rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_A); + rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_B); + }else{ + if(phy_idx == HW_PHY_0) + rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_A); + else + rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_B); + } + /*BB reset set to 1*/ + rtw_hal_bb_reset_en(hal_info, true, phy_idx); + + status = rtw_hal_tx_pause(hal_com, band_idx, false, PAUSE_RSON_RESET); + if(status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("%s rtw_hal_tx_pause - failed\n", __func__); + return status; + } + } + return status; +} + +enum rtw_hal_status rtw_hal_ppdu_sts_cfg(void *hal, u8 band_idx, bool en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + if (en) { + hal_status = rtw_hal_mac_ppdu_stat_cfg( + hal_info, band_idx, true, + hal_com->band[band_idx].ppdu_sts_appen_info, + hal_com->band[band_idx].ppdu_sts_filter); + } else { + hal_status = rtw_hal_mac_ppdu_stat_cfg(hal_info, band_idx, false, 0, 0); + } + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("%s (en %d) - failed\n", __func__, en); + + return hal_status; +} + +void +rtw_hal_disconnect_notify(void *hal, struct rtw_chan_def *chandef) +{ + rtw_hal_rf_disconnect_notify(hal, chandef); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_disconnect_notify(): chandef band(%d), chan(%d), bw(%d), offset(%d)\n", + chandef->band, chandef->chan, chandef->bw, chandef->offset); +} + +bool rtw_hal_check_ch_rfk(void *hal, struct rtw_chan_def *chandef) +{ + bool check = false; + check = rtw_hal_rf_check_mcc_ch(hal, chandef); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_check_ch_rfk(): check ok(%d), band(%d), chan(%d), bw(%d), offset(%d)\n", + check, chandef->band, chandef->chan, chandef->bw, chandef->offset); + return check; +} + +void rtw_hal_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, + struct rtw_wifi_role_t *wrole) +{ + enum phl_phy_idx p_idx = HW_PHY_0; + + p_idx = rtw_hal_bb_band_to_phy_idx(hal_com, wrole->hw_band); + rtw_hal_bb_env_rpt(hal_com, env_rpt, p_idx); +} + +#endif /* _HAL_COM_I_C_ */ diff --git a/phl/hal_g6/hal_config.h b/phl/hal_g6/hal_config.h new file mode 100644 index 0000000..732ad50 --- /dev/null +++ b/phl/hal_g6/hal_config.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_CONFIG_H_ +#define _HAL_CONFIG_H_ + +#ifdef CONFIG_PHL_TEST_MP + #define CONFIG_HAL_TEST_MP +#endif + +#define MAX_PATH_LEN 256 + +#define MAX_LINES_HWCONFIG_TXT 2000 +#define MAX_BYTES_LINE_HWCONFIG_TXT 256 +#define MAX_HWCONFIG_FILE_CONTENT MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT + +/* Disable HALBB Features */ +#ifndef CONFIG_PHL_DFS + #define DRV_BB_DFS_DISABLE +#endif + +#ifdef CONFIG_BB_TIMER_SUPPORT_DISABLE + #define DRV_BB_TIMER_SUPPORT_DISABLE +#endif + +/* Compile flag for fw for different cut versions. +* This should be wrapped with the compile flags from core, and need to be discussed +*/ +#ifdef CONFIG_RTL8852A +#define MAC_FW_8852A_U1 1 +#define MAC_FW_8852A_U2 1 +#define MAC_FW_8852A_U3 1 +#endif + +#ifdef CONFIG_RTL8852B +#define MAC_FW_8852B_U1 1 +#define MAC_FW_8852B_U2 1 +#endif + + +#ifdef CONFIG_WPP +#define DRV_BB_DBG_TRACE_DISABLE +#endif +/* HALRF Features */ + +#ifdef RTW_WKARD_PHL_LPS_IQK_TWICE +#define RTW_WKARD_HAL_LPS_IQK_TWICE +#endif + +#ifdef CONFIG_PHL_MAC_WATCHDOG +#define CONFIG_HAL_MAC_WATCHDOG +#endif + +#endif /*_HAL_CONFIG_H_*/ diff --git a/phl/hal_g6/hal_csi_buffer.c b/phl/hal_g6/hal_csi_buffer.c new file mode 100644 index 0000000..6f9d84a --- /dev/null +++ b/phl/hal_g6/hal_csi_buffer.c @@ -0,0 +1,589 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "hal_headers.h" + +/** + * _dump_csi_buf_status + * Dump all of the csi buffer status; + * @csi_obj: (struct hal_csi_obj *) + **/ +void _dump_csi_buf_status(struct hal_csi_obj *csi_obj) +{ + struct hal_csi_buf *csi_buf = NULL; + u8 i = 0; + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> DUMP HAL CSI Buffer Status\n"); + for (i = 0; i < csi_obj->max_csi_buf_nr; i++) { + csi_buf = &csi_obj->csi_buf[i]; + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF][%d] status 0x%x \n", + csi_buf->idx, csi_buf->sub_idx); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20UU (%d) \n", + IS_SUB20_BUSY(csi_buf, 3)); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20UL (%d) \n", + IS_SUB20_BUSY(csi_buf, 2)); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20LU (%d) \n", + IS_SUB20_BUSY(csi_buf, 1)); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20LL (%d) \n", + IS_SUB20_BUSY(csi_buf, 0)); + } + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== DUMP HAL CSI Buffer Status\n"); +} + +/** + * __query_avl_buf_idx_20 + * Get available sub 20MHz csi buffer + * input : + * @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible + * return + * @sub_idx: (u8) csi buffer sub index + **/ +u8 __query_avl_buf_idx_20(struct hal_csi_buf *csi_buf) +{ + u8 sub_idx = CSI_BUF_SUB_IDX_NON; + do { + if (IS_SUB20_BUSY(csi_buf, 0) == CSI_BUF_STS_IDLE) { + SET_SUB20_BUSY(csi_buf, 0); + sub_idx = CSI_BUF_SUB_IDX_20_LL; + break; + } + if (IS_SUB20_BUSY(csi_buf, 1) == CSI_BUF_STS_IDLE) { + SET_SUB20_BUSY(csi_buf, 1); + sub_idx = CSI_BUF_SUB_IDX_20_LU; + break; + } + if (IS_SUB20_BUSY(csi_buf, 2) == CSI_BUF_STS_IDLE) { + SET_SUB20_BUSY(csi_buf, 2); + sub_idx = CSI_BUF_SUB_IDX_20_UL; + break; + } + if (IS_SUB20_BUSY(csi_buf, 3) == CSI_BUF_STS_IDLE) { + SET_SUB20_BUSY(csi_buf, 3); + sub_idx = CSI_BUF_SUB_IDX_20_UU; + break; + } + } while (0); + + return sub_idx; +} +/** + * __query_avl_buf_idx_40 + * Get available sub 40MHz csi buffer + * input : + * @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible + * return + * @sub_idx: (u8) csi buffer sub index + **/ +u8 __query_avl_buf_idx_40(struct hal_csi_buf *csi_buf) +{ + u8 sub_idx = CSI_BUF_SUB_IDX_NON; + do { + if(IS_40L_BUSY(csi_buf) == CSI_BUF_STS_IDLE) { + SET_40L_BUSY(csi_buf); + sub_idx = CSI_BUF_SUB_IDX_40_L; + break; + } + if (IS_40U_BUSY(csi_buf) == CSI_BUF_STS_IDLE) { + SET_40U_BUSY(csi_buf); + sub_idx = CSI_BUF_SUB_IDX_40_U; + break; + } + } while (0); + + return sub_idx; +} +/** + * __query_avl_buf_idx_80 + * Get available sub 80MHz csi buffer + * input : + * @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible + * return + * @sub_idx: (u8) csi buffer sub index + **/ +u8 __query_avl_buf_idx_80(struct hal_csi_buf *csi_buf) +{ + u8 sub_idx = CSI_BUF_SUB_IDX_NON; + if (csi_buf->sub_idx == CSI_BUF_STS_IDLE) { + sub_idx = CSI_BUF_SUB_IDX_80; + csi_buf->sub_idx = 0xF; + } + return sub_idx; +} + +/** + * _query_csi_buf_su + * Get available sub 40MHz csi buffer + * input : + * @hal_info: (struct hal_info_t *) + * @size:enum hal_csi_buf_size 20/40/80 MHz + * return + * @sub_id: (u8) available csi buffer sub index + * @csi_buf: (struct hal_csi_buf *) original hal csi buffer + **/ +struct hal_csi_buf *_query_csi_buf_su( + struct hal_info_t *hal_info, + enum hal_csi_buf_size size, + u8 *sub_id) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + struct hal_csi_buf *csi_buf = NULL; + u8 i = 0; + u8 e_idx_su = csi_obj->max_csi_buf_nr_su; + + *sub_id = CSI_BUF_SUB_IDX_NON; + + switch (size) { + case HAL_CSI_BUF_SIZE_20: + for (i = 0; i < e_idx_su; i++) { + *sub_id = __query_avl_buf_idx_20(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + case HAL_CSI_BUF_SIZE_40: + for (i = 0; i < e_idx_su; i++) { + *sub_id = __query_avl_buf_idx_40(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + case HAL_CSI_BUF_SIZE_80: + for (i = 0; i < e_idx_su; i++) { + *sub_id = __query_avl_buf_idx_80(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + default: + break; + } + if (*sub_id == CSI_BUF_SUB_IDX_NON) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :_query_csi_buf_su fail !!!\n"); + } + return csi_buf; +} + +/** + * _query_csi_buf_mu + * Get available sub 40MHz csi buffer + * input : + * @hal_info: (struct hal_info_t *) + * @size:enum hal_csi_buf_size 20/40/80 MHz + * return + * @sub_id: (u8) available csi buffer sub index + * @csi_buf: (struct hal_csi_buf *) original hal csi buffer + **/ +struct hal_csi_buf *_query_csi_buf_mu( + struct hal_info_t *hal_info, + enum hal_csi_buf_size size, + u8 *sub_id) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + struct hal_csi_buf *csi_buf = NULL; + u8 i = 0; + u8 s_idx_mu = csi_obj->max_csi_buf_nr_su; + u8 e_idx_mu = csi_obj->max_csi_buf_nr; + + *sub_id = CSI_BUF_SUB_IDX_NON; + + switch (size) { + case HAL_CSI_BUF_SIZE_20: + for (i = s_idx_mu; i < e_idx_mu; i++) { + *sub_id = __query_avl_buf_idx_20(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + case HAL_CSI_BUF_SIZE_40: + for (i = s_idx_mu; i < e_idx_mu; i++) { + *sub_id = __query_avl_buf_idx_40(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + case HAL_CSI_BUF_SIZE_80: + for (i = s_idx_mu; i < e_idx_mu; i++) { + *sub_id = __query_avl_buf_idx_80(&csi_obj->csi_buf[i]); + if(*sub_id != CSI_BUF_SUB_IDX_NON) { + csi_buf = &csi_obj->csi_buf[i]; + break; + } + } + break; + default: + break; + } + + if (*sub_id == CSI_BUF_SUB_IDX_NON) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :_query_csi_buf_mu fail !!!\n"); + } + return csi_buf; +} + +/** + * _bw2csi + * phl channel width to hal csi buffer size + * input : + * @bw: (struct hal_info_t *) + * return + * @ret: enum hal_csi_buf_size + **/ +enum hal_csi_buf_size +_bw2csi(enum channel_width bw) +{ + enum hal_csi_buf_size ret = HAL_CSI_BUF_SIZE_NONE; + switch (bw){ + case CHANNEL_WIDTH_20: + ret = HAL_CSI_BUF_SIZE_20; + break; + case CHANNEL_WIDTH_40: + ret = HAL_CSI_BUF_SIZE_40; + break; + case CHANNEL_WIDTH_80: + ret = HAL_CSI_BUF_SIZE_80; + break; + default: + break; + } + return ret; +} + +enum rtw_hal_status _hal_csi_init_buf(struct hal_info_t *hal_info, u8 num) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + void *drv_priv = hal_to_drvpriv(hal_info); + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = hal_com->csi_obj; + struct hal_csi_buf *csi_buf = NULL; + u8 idx = 0; + + do { + csi_obj->csi_buf = _os_mem_alloc(drv_priv, + sizeof(*csi_buf) * num); + _os_mem_set(drv_priv, csi_obj->csi_buf, 0, + sizeof(*csi_buf) * num); + + if (NULL == csi_obj->csi_buf) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + csi_buf = csi_obj->csi_buf; + for (idx = 0; idx < num ; idx++) { + csi_buf[idx].idx = idx; + csi_buf[idx].sub_idx = 0; + } + } while (0); + + return status; +} + + +/** + * hal_csi_init + * hal csi module initialize + * input : + * @hal_info: struct hal_info_t + * @su_buf_nr: Number of HW SU CSI Buffer for HAL + * @mu_buf_nr: Number of HW MU CSI Buffer for HAL + **/ +enum rtw_hal_status +hal_csi_init(struct hal_info_t *hal_info, u8 su_buf_nr, u8 mu_buf_nr) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = NULL; + void *drv_priv = hal_to_drvpriv(hal_info); + u8 idx = 0; + FUNCIN(); + + do { + csi_obj = _os_mem_alloc(drv_priv, sizeof(*csi_obj)); + + if (csi_obj == NULL) { + status = RTW_HAL_STATUS_RESOURCE; + break; + } + hal_com->csi_obj = csi_obj; + _os_spinlock_init(drv_priv, &csi_obj->csi_lock); + + if ((su_buf_nr + mu_buf_nr) == 0) { + PHL_ERR("hal_csi_init fail : csi buffer number = 0\n"); + status = RTW_HAL_STATUS_RESOURCE; + break; + } + _hal_csi_init_buf(hal_info, mu_buf_nr + su_buf_nr); + + csi_obj->max_csi_buf_nr_mu = mu_buf_nr; + csi_obj->max_csi_buf_nr_su = su_buf_nr; + csi_obj->max_csi_buf_nr = su_buf_nr + mu_buf_nr; + for (idx = su_buf_nr; idx < csi_obj->max_csi_buf_nr; idx++){ + csi_obj->csi_buf[idx].type = HAL_CSI_BUF_TYPE_MU; + } + + } while (0); + + if (RTW_HAL_STATUS_SUCCESS != status) { + hal_csi_deinit(hal_info); + } + FUNCOUT(); + return status; +} +/** + * hal_csi_deinit + * hal csi module deinitialize + * input : + * @hal_info: struct hal_info_t + **/ +void hal_csi_deinit(struct hal_info_t *hal_info) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + void *drv_priv = hal_to_drvpriv(hal_info); + struct hal_csi_buf *csi_buf = csi_obj->csi_buf; + + if (csi_obj != NULL) { + if (csi_buf != NULL) { + _os_mem_free(hal_to_drvpriv(hal_info), csi_buf, + sizeof(struct hal_csi_buf) * csi_obj->max_csi_buf_nr); + csi_obj->csi_buf = NULL; + } + + _os_spinlock_free(drv_priv, &csi_obj->csi_lock); + /* bf obj need free as last */ + _os_mem_free(hal_to_drvpriv(hal_info), csi_obj, + sizeof(struct hal_csi_obj)); + hal_com->csi_obj = NULL; + } +} + +/** + * hal_csi_query_idle_csi_buf + * Get available CSI buffer + * input : + * @hal_info: struct hal_info_t + * @mu: Request CSI Type : 1 = MU / 0 = SU + * @bw: Request CSI BW : enum channel_width (20/40/80MHz) + * @buf: (struct hal_csi_buf *)input/return : memory for CSI buffer index+subindex + * (the call shall provied 1byte memory to save csi index) + **/ +enum rtw_hal_status hal_csi_query_idle_csi_buf( + struct hal_info_t *hal_info, + u8 mu, + enum channel_width bw, + void *buf) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + void *drv_priv = hal_to_drvpriv(hal_info); + struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf; + struct hal_csi_buf *tmp_csi_buf = NULL; + u8 sub_idx = CSI_BUF_SUB_IDX_NON; + enum hal_csi_buf_size size = HAL_CSI_BUF_SIZE_NONE; + enum hal_csi_buf_type type = HAL_CSI_BUF_TYPE_SU; + + FUNCIN(); + if (csi_buf == NULL) { + return status; + } + + size = _bw2csi(bw); + type = mu ? HAL_CSI_BUF_TYPE_MU : HAL_CSI_BUF_TYPE_SU; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "size = 0x%x , type = 0x%x \n", + size, type); + + switch (type) { + case HAL_CSI_BUF_TYPE_SU: + { + _os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + tmp_csi_buf = _query_csi_buf_su(hal_info, size, &sub_idx); + _os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + } + break; + case HAL_CSI_BUF_TYPE_MU: + { + _os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + tmp_csi_buf = _query_csi_buf_mu(hal_info, size, &sub_idx); + _os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + } + break; + default: + break; + } + if (tmp_csi_buf == NULL || sub_idx == CSI_BUF_SUB_IDX_NON) { + status = RTW_HAL_STATUS_RESOURCE; + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "hal_csi_query_idle_csi_buf Fail\n"); + } else { + csi_buf->idx = tmp_csi_buf->idx; + csi_buf->sub_idx = sub_idx; + csi_buf->type = type; + status = RTW_HAL_STATUS_SUCCESS; + } + + FUNCOUT(); + return status; +} + +/** + * hal_csi_release_csi_buf + * Release the CSI buffer + * input : + * @hal_info: struct hal_info_t + * @buf: (struct hal_csi_buf *)input/return : CSI buffer index to release + **/ +enum rtw_hal_status hal_csi_release_csi_buf( + struct hal_info_t *hal_info, + void *buf) +{ + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + void *drv_priv = hal_to_drvpriv(hal_info); + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct hal_csi_buf *tmp_csi_buf = NULL; + struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf; + + if (csi_buf == NULL) { + return status; + } + + if (csi_buf->idx < csi_obj->max_csi_buf_nr) { + tmp_csi_buf = &csi_obj->csi_buf[csi_buf->idx]; + + _os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + + switch (csi_buf->sub_idx) { + case CSI_BUF_SUB_IDX_80: + tmp_csi_buf->sub_idx = 0; + break; + case CSI_BUF_SUB_IDX_40_U: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 3); + CLEAR_CSI_STS_BIT(tmp_csi_buf, 2); + break; + case CSI_BUF_SUB_IDX_40_L: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 1); + CLEAR_CSI_STS_BIT(tmp_csi_buf, 0); + break; + case CSI_BUF_SUB_IDX_20_UU: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 3); + break; + case CSI_BUF_SUB_IDX_20_UL: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 2); + break; + case CSI_BUF_SUB_IDX_20_LU: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 1); + break; + case CSI_BUF_SUB_IDX_20_LL: + CLEAR_CSI_STS_BIT(tmp_csi_buf, 0); + break; + default: + break; + } + csi_buf->idx = 0; + csi_buf->sub_idx = CSI_BUF_SUB_IDX_NON; + _os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL); + status = RTW_HAL_STATUS_SUCCESS; + } + return status; +} + +/** + * hal_is_csi_buf_valid : check the csi buffer index is valid or not. + * @hal_info: struct hal_info_t + * @buf: (struct hal_csi_buf *)input/return : CSI buffer index to release + **/ +u8 hal_is_csi_buf_valid(struct hal_info_t *hal_info, void *buf) +{ + struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj; + + u8 ret = _SUCCESS; + do { + if(csi_buf->idx >= csi_obj->max_csi_buf_nr){ + ret = _FAIL; + break; + } + if(csi_buf->sub_idx == CSI_BUF_SUB_IDX_NON) { + ret = _FAIL; + break; + } + } while(0); + + return ret; +} + +/** + * rtw_hal_get_csi_buf_bw : Get the csi buf bandwidth; + * @buf: (struct hal_csi_buf *) + * return + * @ret: enum channel_width + **/ +enum channel_width +rtw_hal_get_csi_buf_bw(void *buf) +{ + struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf; + enum channel_width bw = CHANNEL_WIDTH_20; + switch (csi_buf->sub_idx) { + case CSI_BUF_SUB_IDX_80: + bw = CHANNEL_WIDTH_80; + break; + case CSI_BUF_SUB_IDX_40_U: + case CSI_BUF_SUB_IDX_40_L: + bw = CHANNEL_WIDTH_40; + break; + case CSI_BUF_SUB_IDX_20_UU: + case CSI_BUF_SUB_IDX_20_UL: + case CSI_BUF_SUB_IDX_20_LU: + case CSI_BUF_SUB_IDX_20_LL: + bw = CHANNEL_WIDTH_20; + break; + case CSI_BUF_SUB_IDX_NON: + default: + bw = CHANNEL_WIDTH_MAX; + break; + } + + return bw; +} + + +/** + * rtw_hal_get_csi_buf_type : check the csi buffer index is valid or not. + * @buf: (struct hal_csi_buf *) + * return: + * @ret: true = TYPE MU ; false = TYPE SU + **/ +bool +rtw_hal_get_csi_buf_type(void *buf) +{ + struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf; + bool ret = false; + + if (csi_buf != NULL) { + ret = (csi_buf->type == HAL_CSI_BUF_TYPE_MU) ? true : false; + } + + return ret; +} diff --git a/phl/hal_g6/hal_csi_buffer.h b/phl/hal_g6/hal_csi_buffer.h new file mode 100644 index 0000000..4fb727b --- /dev/null +++ b/phl/hal_g6/hal_csi_buffer.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HAL_CSI_BUFFER_H__ +#define __HAL_CSI_BUFFER_H__ + +#define CSI_BUF_IDX_HW_MSK 0x7FF + +#define CSI_BUF_SUB_IDX_80 0b0 +#define CSI_BUF_SUB_IDX_40_U 0b100100 +#define CSI_BUF_SUB_IDX_40_L 0b101000 +#define CSI_BUF_SUB_IDX_20_UU 0b000100 +#define CSI_BUF_SUB_IDX_20_UL 0b001000 +#define CSI_BUF_SUB_IDX_20_LU 0b001100 +#define CSI_BUF_SUB_IDX_20_LL 0b010000 +#define CSI_BUF_SUB_IDX_NON 0b111111 + +#define CSI_BUF_STS_BUSY 1 +#define CSI_BUF_STS_IDLE 0 + +#define IS_SUB20_BUSY(_csi, _idx) \ + (((_csi->sub_idx&BIT(_idx)) == BIT(_idx)) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE) + +#define SET_SUB20_BUSY(_csi, _idx) _csi->sub_idx |= BIT(_idx) + +#define IS_40L_BUSY(_csi) \ + (((_csi->sub_idx & (BIT(0)|BIT(1)))==(BIT(0)|BIT(1))) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE) +#define IS_40U_BUSY(_csi) \ + (((_csi->sub_idx & (BIT(2)|BIT(3)))==(BIT(2)|BIT(3))) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE) + +#define SET_40L_BUSY(_csi) _csi->sub_idx |= (BIT(0)|BIT(1)) +#define SET_40U_BUSY(_csi) _csi->sub_idx |= (BIT(2)|BIT(3)) + +#define CLEAR_CSI_STS_BIT(_csi, _x) _csi->sub_idx &= ~(1 << _x) + +enum hal_csi_buf_type { + HAL_CSI_BUF_TYPE_SU = 0, + HAL_CSI_BUF_TYPE_MU = 1 +}; + +enum hal_csi_buf_size { + HAL_CSI_BUF_SIZE_NONE = 0, + HAL_CSI_BUF_SIZE_20, + HAL_CSI_BUF_SIZE_40, + HAL_CSI_BUF_SIZE_80, + HAL_CSI_BUF_SIZE_160 +}; + +struct hal_csi_buf { + u16 sub_idx:6; + u16 idx:5; + u16 type:1; + u16 rsvd:4; +}; + +struct hal_csi_obj { + u8 max_csi_buf_nr; + u8 max_csi_buf_nr_su; + u8 max_csi_buf_nr_mu; + struct hal_csi_buf *csi_buf; + _os_lock csi_lock; +}; + +enum rtw_hal_status +hal_csi_init(struct hal_info_t *hal_info, u8 su_buf_nr, u8 mu_buf_nr); + +void hal_csi_deinit(struct hal_info_t *hal_info); + +enum rtw_hal_status hal_csi_query_idle_csi_buf( + struct hal_info_t *hal_info, u8 mu, enum channel_width bw, void *buf); + +enum rtw_hal_status hal_csi_release_csi_buf( + struct hal_info_t *hal_info, + void *buf); + +u8 hal_is_csi_buf_valid(struct hal_info_t *hal_info, void *buf); + +enum channel_width +rtw_hal_get_csi_buf_bw(void *buf); + +bool +rtw_hal_get_csi_buf_type(void *buf); + +#endif diff --git a/phl/hal_g6/hal_custom.c b/phl/hal_g6/hal_custom.c new file mode 100644 index 0000000..ffe965f --- /dev/null +++ b/phl/hal_g6/hal_custom.c @@ -0,0 +1,86 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_CUSTOM_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_CUSTOM_FEATURE +enum rtw_hal_status +rtw_hal_custom_cfg_tx_ampdu(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *ampdu) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + if (wrole == NULL || ampdu == NULL) + return hsts; + hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, + wrole->hw_band, + (u16)ampdu->max_agg_num, + (u8)ampdu->max_agg_time_32us); + return hsts; +} + +enum rtw_hal_status +rtw_hal_get_ampdu_cfg(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *cfg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_ampdu_cfg ampdu_cfg = {0}; + + if (wrole == NULL || cfg == NULL) + return hsts; + hsts = rtw_hal_mac_get_ampdu_cfg(hal_info->hal_com, + wrole->hw_band, + &du_cfg); + if (hsts == RTW_HAL_STATUS_SUCCESS) { + cfg->max_agg_num = ampdu_cfg.max_agg_num; + cfg->max_agg_time_32us = ampdu_cfg.max_agg_time_32us; + } + return hsts; +} + +enum rtw_hal_status +rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + return rtw_hal_bb_set_pop_en(hal_info, en, phy_idx); +} + +bool +rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + return rtw_hal_bb_query_pop_en(hal_info, phy_idx); +} + +enum rtw_hal_status +rtw_hal_set_pkt_detect_thold(void *hal, u32 bound) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + return rtw_hal_bb_set_pkt_detect_thold(hal_info, bound); +} + +u8 +rtw_hal_query_pkt_detect_thold(void *hal, + bool get_en_info, + enum phl_phy_idx phy_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + return rtw_hal_bb_query_pkt_detect_thold(hal_info, get_en_info, phy_idx); +} +#endif + diff --git a/phl/hal_g6/hal_custom.h b/phl/hal_g6/hal_custom.h new file mode 100644 index 0000000..8f904e8 --- /dev/null +++ b/phl/hal_g6/hal_custom.h @@ -0,0 +1,43 @@ + +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_CUSTOM_H_ +#define _HAL_CUSTOM_H_ + +#ifdef CONFIG_PHL_CUSTOM_FEATURE +enum rtw_hal_status +rtw_hal_custom_cfg_tx_ampdu(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *ampdu); +enum rtw_hal_status +rtw_hal_get_ampdu_cfg(void *hal, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_custom_ampdu_cfg *cfg); +enum rtw_hal_status +rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx); + +bool +rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx); + +enum rtw_hal_status +rtw_hal_set_pkt_detect_thold(void *hal, u32 bound); + +u8 +rtw_hal_query_pkt_detect_thold(void *hal, + bool get_en_info, + enum phl_phy_idx phy_idx); +#endif + +#endif /*_HAL_CUSTOM_H_*/ diff --git a/phl/hal_g6/hal_dbcc.c b/phl/hal_g6/hal_dbcc.c new file mode 100644 index 0000000..c0de31b --- /dev/null +++ b/phl/hal_g6/hal_dbcc.c @@ -0,0 +1,174 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_DBCC_C_ +#include "hal_headers.h" + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_hal_status +rtw_hal_dbcc_pre_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + + hal_com->dbcc_en = (dbcc_en) ? true : false; + + /*mac_dbcc_pre_cfg*/ + hsts = rtw_hal_mac_dbcc_pre_cfg(phl_com, hal_info, dbcc_en); + if (hsts != RTW_HAL_STATUS_SUCCESS) { + PHL_ASSERT("%s mac_dbcc_pre_cfg failed\n", __func__); + hal_com->dbcc_en = false; + goto exit_func; + } + /*phy_dbcc_pre_cfg*/ + hsts = rtw_hal_phy_dbcc_pre_cfg(hal_info, phl_com, dbcc_en); + if (hsts != RTW_HAL_STATUS_SUCCESS) { + PHL_ASSERT("%s phy_dbcc_pre_cfg failed\n", __func__); + hal_com->dbcc_en = false; + goto exit_func; + } + + PHL_INFO("%s-%s done and success\n", __func__, (dbcc_en) ? "EN" : "DIS"); + +exit_func: + + return hsts; +} + +enum rtw_hal_status +rtw_hal_dbcc_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + + /*if(phl_com->drv_mode == RTW_DRV_MODE_MP)*/ + + if(hal_info->hal_com->chip_id ==CHIP_WIFI6_8852B) + { + PHL_ASSERT("%s 8852B doesn't support dbcc\n", __func__); + hal_com->dbcc_en = false; + goto exit_func; + } + +#if 1 + /* band 0 tx pause */ + rtw_hal_tx_pause(hal_com, HW_BAND_0, true, PAUSE_RSON_DBCC); +#else + /* mac-id pause - rtw_hal_mac_set_macid_pause */ + rtw_hal_mac_set_macid_pause(hal_info->hal_com, 0, true); + rtw_hal_mac_set_macid_pause(hal_info->hal_com, 1, true); +#endif + /* FW tx pause , BT tx pause*/ + /* bb cca pause */ + rtw_hal_bb_ctrl_rx_cca(hal_info->hal_com, false, HW_PHY_0); + + /*mac_dbcc_cfg*/ + hsts = rtw_hal_mac_dbcc_cfg(phl_com, hal_info, dbcc_en); + if (hsts != RTW_HAL_STATUS_SUCCESS) { + PHL_ASSERT("%s mac_dbcc_cfg failed\n", __func__); + hal_com->dbcc_en = false; + goto exit_func; + } + + /*bb_dbcc_cfg*/ + hsts = rtw_hal_phy_dbcc_cfg(hal_info, phl_com, dbcc_en); + if (hsts != RTW_HAL_STATUS_SUCCESS) { + PHL_ASSERT("%s phy_dbcc_cfg failed\n", __func__); + hal_com->dbcc_en = false; + goto exit_func; + } + +#if 1 + /* band 0 tx unpause */ + rtw_hal_tx_pause(hal_com, HW_BAND_0, false, PAUSE_RSON_DBCC); +#else + /* mac-id unpause - rtw_hal_mac_set_macid_pause */ + rtw_hal_mac_set_macid_pause(hal_info->hal_com, 0, false); + rtw_hal_mac_set_macid_pause(hal_info->hal_com, 1, false); +#endif + + /* FW tx unpause , BT tx unpause*/ + /* bb cca unpause */ + rtw_hal_bb_ctrl_rx_cca(hal_info->hal_com, true, HW_PHY_0); + + PHL_INFO("%s-%s done and success\n", __func__, (dbcc_en) ? "EN" : "DIS"); + + /*mac role recovery*/ + /*if (has_ap)*/ + /*mac_port_cfg(BCN_EN-MAC_AX_PCFG_TX_SW)*/ + /*mac_port_cfg(BCN_DIS-MAC_AX_PCFG_MBSSID_EN)*/ +exit_func: + + return hsts; +} + +enum rtw_hal_status +rtw_hal_clean_tx_queue(void *hal) +{ +#if 0 + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + u32 start_time; + + start_time = _os_get_cur_time_ms(); + + // set retry limit =1 -rtw_hal_mac_set_rty_lmt + /* rtw_hal_mac_set_rty_lmt(hal_com, sta->macid, + rts_txcnt_lmt_sel, rts_txcnt_lmt, + data_txcnt_lmt_sel, data_tx_cnt_lmt);*/ + + //polling mac_is_txq_empty - rtw_hal_mac_is_txq_empty + //chk_allq_empty - rtw_hal_mac_is_allq_empty + + //polling TX idle + //FW tx pause/unpause + + // if (has ap) + //polling HIQ & WLCPU queue, + //disable beacon TX mode + //mac_port_cfg(BCN_DIS-MAC_AX_PCFG_TX_SW) + //mac_port_cfg(BCN_DIS-MAC_AX_PCFG_MBSSID_EN) + + PHL_INFO("[DBCC] %s: pass %u ms\n", __FUNCTION__, + _get_passing_time_ms(start_time)); +#endif + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_dbcc_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band) +{ +#if 1 /* no rtw_hal_mac_get_tx_cnt api */ + return RTW_HAL_STATUS_SUCCESS; +#else + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_get_tx_cnt(hal_info, band, MAC_AX_TX_ALLTYPE, NULL); +#endif +} + +enum rtw_hal_status +rtw_hal_dbcc_reset_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band) +{ +#if 1 /* no rtw_hal_mac_set_reset_tx_cnt */ + return RTW_HAL_STATUS_SUCCESS; +#else + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_set_reset_tx_cnt(hal_info, band); +#endif +} +#endif /*CONFIG_DBCC_SUPPORT*/ diff --git a/phl/hal_g6/hal_dbcc.h b/phl/hal_g6/hal_dbcc.h new file mode 100644 index 0000000..7c7b2df --- /dev/null +++ b/phl/hal_g6/hal_dbcc.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_DBCC_H_ +#define _HAL_DBCC_H_ + + +#endif /* _HAL_DBCC_H_ */ + diff --git a/phl/hal_g6/hal_def.h b/phl/hal_g6/hal_def.h new file mode 100644 index 0000000..a1adc32 --- /dev/null +++ b/phl/hal_g6/hal_def.h @@ -0,0 +1,1265 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_DEF_H_ +#define _HAL_DEF_H_ + +#define halcom_to_drvpriv(_hcom) (_hcom->drv_priv) + +#define MAX_WD_LEN (48) +#define MAX_WD_BODY_LEN (24) +#define MAX_BAENTRY 2 + +enum HAL_CMD_ID { + HAL_HELP, + MAC_DD_DBG, + MAC_DUMP_SEC_CAM_TBL +}; + +struct hal_cmd_info { + char name[16]; + u8 id; +}; + +static const struct hal_cmd_info hal_cmd_i[] = { + {"-h", HAL_HELP}, + {"dd_dbg", MAC_DD_DBG},/*@do not move this element to other position*/ + {"sec_cam_tbl", MAC_DUMP_SEC_CAM_TBL} +}; + + +enum rtw_hal_status { + RTW_HAL_STATUS_SUCCESS, /* 0 */ + RTW_HAL_STATUS_FAILURE, /* 1 */ + RTW_HAL_STATUS_RESOURCE, /* 2 */ + RTW_HAL_STATUS_IO_INIT_FAILURE, /* 3 */ + RTW_HAL_STATUS_MAC_INIT_FAILURE, /* 4 */ + RTW_HAL_STATUS_BB_INIT_FAILURE, /* 5 */ + RTW_HAL_STATUS_RF_INIT_FAILURE, /* 6 */ + RTW_HAL_STATUS_BTC_INIT_FAILURE, /* 7 */ + RTW_HAL_STATUS_HAL_INIT_FAILURE, /* 8 */ + RTW_HAL_STATUS_EFUSE_UNINIT, /* 9 */ + RTW_HAL_STATUS_EFUSE_IVALID_OFFSET, /* 10 */ + RTW_HAL_STATUS_EFUSE_PG_FAIL, /* 11 */ + RTW_HAL_STATUS_MAC_API_FAILURE, /* 12 */ + RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG, /*13*/ + RTW_HAL_STATUS_UNKNOWN_RFE_TYPE, /* 14 */ + RTW_HAL_STATUS_TIMEOUT, /* 15 */ +}; + +#define FW_FILE_NIC_POSTFIX "" +#define FW_FILE_WOWLAN_POSTFIX "_wowlan" +#define FW_FILE_SPIC_POSTFIX "_spic" +#define FW_FILE_AP_POSTFIX "_ap" + +enum rtw_fw_type { + RTW_FW_NIC, /* 1 */ + RTW_FW_WOWLAN, /* 2 */ + RTW_FW_AP, /* 3 */ + RTW_FW_ROM, /* 4 */ + RTW_FW_SPIC, /* 5 */ + RTW_FW_NIC_MP, /* 6 */ + RTW_FW_AP_MP, /* 7 */ + RTW_FW_VRAP, /* 8 */ + RTW_FW_MAX +}; + +enum _rtw_hal_query_info { + RTW_HAL_RXDESC_SIZE, +}; + +enum rtw_h2c_pkt_type { + H2CB_TYPE_CMD = 0, + H2CB_TYPE_DATA = 1, + H2CB_TYPE_LONG_DATA = 2, + H2CB_TYPE_MAX = 0x3 +}; + +enum tx_pause_rson { + PAUSE_RSON_NOR_SCAN, /*normal scan*/ + PAUSE_RSON_UNSPEC_BY_MACID, /*P2P_SCAN*/ + PAUSE_RSON_RFK, + PAUSE_RSON_PSD, + PAUSE_RSON_DFS, + PAUSE_RSON_DBCC, + PAUSE_RSON_RESET, + PAUSE_RSON_MAX +}; + +enum rtw_hal_config_int { + RTW_HAL_EN_DEFAULT_INT, + RTW_HAL_DIS_DEFAULT_INT, + RTW_HAL_STOP_RX_INT, + RTW_HAL_RESUME_RX_INT, + RTW_HAL_SER_HANDSHAKE_MODE, + RTW_HAL_EN_HCI_INT, + RTW_HAL_DIS_HCI_INT, + RTW_HAL_CONFIG_INT_MAX +}; + +enum hal_mp_efuse_type { + HAL_MP_EFUSE_WIFI = 0, + HAL_MP_EFUSE_BT, + HAL_MP_EFUSE_NONE, +}; + +struct rtw_g6_h2c_hdr { + u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC + u8 h2c_func; + u8 seq_valid:1; + u8 seq:3; + u8 seq_stop:1; + enum rtw_h2c_pkt_type type; //0:cmd ; 1:cmd+data ; 2:cmd+long data + u16 content_len:12; + u16 rec_ack:1; //Ack when receive H2C + u16 done_ack:1; //Ack when FW execute H2C cmd done + u16 rsvd2:2; +}; + +/** + * @c2h_cat: target category of this c2h / c2h ack + * @c2h_class: target class of this c2h / c2h ack + * @c2h_func: target function of this c2h / c2h ack + * @type_rec_ack: set 1 as a receive ack to this c2h + * @type_done_ack: set 1 as a done ack to this c2h + * @h2c_return: status code of done ack responding to h2c + * + */ +struct rtw_c2h_info { + u8 c2h_cat; + u8 c2h_class; + u8 c2h_func; + u8 type_rec_ack:1; + u8 type_done_ack:1; + u8 rsvd:6; + u8 h2c_return;/*H2C return value, 0 = success*/ + u8 h2c_seq; + u16 content_len; + u8 *content; +}; + + +#define RTW_BTC_OVERWRITE_BUF_LEN 10 +struct hal_bt_msg { + _os_lock lock; + u16 len; + u16 cnt; /* update cnt */ + u8 latest[RTW_BTC_OVERWRITE_BUF_LEN]; + u8 working[RTW_BTC_OVERWRITE_BUF_LEN]; +}; + +struct btc_fw_msg { + _os_lock lock; + u32 fev_cnt; /* fw event cnt, need to be protected by lock */ + + struct hal_bt_msg btinfo; + struct hal_bt_msg scbd; + + /* common fwinfo queue */ + struct phl_queue idleq; + struct phl_queue waitq; +}; + +struct btc_ctrl_t { + u8 lps; + u8 tx_time; + u8 tx_retry; +}; + +/*except version*/ +struct ver_ctrl_t { + u64 mac_ver; + u64 bb_ver; + u64 rf_ver; + u64 btc_ver; + u64 fw_ver; +}; + + +struct hal_mu_score_tbl_ctrl { + u32 mu_sc_thr:2; + u32 mu_opt:1; + u32 rsvd:29; +}; + +#define HAL_MAX_MU_SCORE_SIZE 8 /* Unit: Byte */ +struct hal_mu_score_tbl_score { + u8 valid; + u16 macid; + u8 score[HAL_MAX_MU_SCORE_SIZE]; /*by case: [1:0], [3:2], ..... */ +}; + +#define HAL_MAX_MU_STA_NUM 6 +struct hal_mu_score_tbl { + struct hal_mu_score_tbl_ctrl mu_ctrl; + _os_lock lock; + u8 num_mu_sta; /*By IC, shall alway <= than HAL_MAX_MU_STA_NUM , 0 = tbl invalid */ + u8 sz_mu_score; /*By IC, shall alway <= than HAL_MAX_MU_SCORE_SIZE , 0 = score invalid */ + struct hal_mu_score_tbl_score mu_score[HAL_MAX_MU_STA_NUM]; /* mu_score[num_mu_sta] */ +}; + + +#define HAL_MAX_VHT_BFRP_NUM 3 +#define HAL_MAX_HE_BFRP_NUM 2 +#define HLA_MAX_BFRP_NUM ((HAL_MAX_VHT_BFRP_NUM > HAL_MAX_HE_BFRP_NUM) ?\ + HAL_MAX_VHT_BFRP_NUM : HAL_MAX_HE_BFRP_NUM) +#define HAL_MAX_VHT_SND_STA_NUM HAL_MAX_VHT_BFRP_NUM + 1 +#define HAL_MAX_HE_BFRP_STA_NUM 4 +#define HAL_MAX_HE_SND_STA_NUM HAL_MAX_HE_BFRP_NUM * HAL_MAX_HE_BFRP_STA_NUM + +struct hal_frame_hdr { + u16 frame_ctl; + u16 duration; + u8 addr1[MAC_ALEN]; + u8 addr2[MAC_ALEN]; +}; +struct hal_npda_dialog_token { + u8 rsvd:1; + u8 he:1; + u8 token:6; +}; + +#define HAL_NPDA_AC_SU 0 +#define HAL_NPDA_AC_MU 1 +#define HAL_NDPA_AX_FB_SU_NG_4 0 +#define HAL_NDPA_AX_FB_SU_NG_16 2 +#define HAL_NDPA_AX_FB_MU_NG_4 1 +#define HAL_NDPA_AX_FB_MU_NG_16 3 +#define HAL_NDPA_AX_FB_CQI 3 +#define HAL_NPDA_AX_CB_SU42_MU75 0 +#define HAL_NPDA_AX_CB_SU64_MU97 1 + +struct hal_he_snd_f2p { + u16 csi_len_bfrp:12; + u16 tb_t_pe_bfrp:2; + u16 tri_pad_bfrp:2; + + u16 ul_cqi_rpt_tri_bfrp:1; + u16 rf_gain_idx_bfrp:10; + u16 fix_gain_en_bfrp:1; + u16 rsvd:4; +}; + +struct hal_vht_ndpa_sta_info { + u32 aid12:12; + u32 feedback_type:1; + u32 nc:3; + u32 rsvd:16; +}; + +struct hal_he_ndpa_sta_info { + u32 aid:11; + u32 bw:14; + u32 fb_ng:2; + u32 disambiguation:1; + u32 cb:1; + u32 nc:3; +}; + +struct hal_ndpa_para { + struct hal_frame_hdr common; + struct hal_npda_dialog_token snd_dialog; + u32 ndpa_sta_info[HAL_MAX_HE_SND_STA_NUM]; +}; + +struct hal_he_trg_frm_cmn { + u32 tgr_info: 4; + u32 ul_len: 12; + u32 more_tf: 1; + u32 cs_rqd: 1; + u32 ul_bw: 2; + u32 gi_ltf: 2; + u32 mimo_ltfmode: 1; + u32 num_heltf: 3; + u32 ul_pktext: 3; + u32 ul_stbc: 1; + u32 ldpc_extra_sym: 1; + u32 dplr: 1; + u32 ap_tx_pwr: 6; + u32 ul_sr: 16; + u32 ul_siga2_rsvd: 9; + u32 rsvd: 1; +}; + +struct hal_he_trg_fm_user { + u16 aid12; + u8 ru_pos; + u8 ul_fec_code; + u8 ul_mcs; + u8 ul_dcm; + u8 ss_alloc; + u8 ul_tgt_rssi; +}; + +struct hal_bfrp_he { + struct hal_he_trg_frm_cmn common; + struct hal_he_trg_fm_user user[HAL_MAX_HE_BFRP_STA_NUM]; + u8 fbseg_rexmit_bmp[HAL_MAX_HE_BFRP_STA_NUM];/*BFRP only*/ + struct hal_he_snd_f2p f2p_info; +}; + + +struct hal_bfrp_vht { + u8 rexmit_bmp; +}; + +struct hal_bfrp_para { + struct hal_frame_hdr hdr[HLA_MAX_BFRP_NUM]; + struct hal_bfrp_he he_para[HAL_MAX_HE_BFRP_NUM]; + struct hal_bfrp_vht vht_para[HAL_MAX_VHT_BFRP_NUM]; +}; + +struct hal_snd_wd_para { + u16 txpktsize; + u16 ndpa_duration; + u16 datarate:9; + u16 macid:7; + u8 force_txop:1; + u8 data_bw:2; + u8 gi_ltf:3; + u8 data_er:1; + u8 data_dcm:1; + u8 data_stbc:1; + u8 data_ldpc:1; + u8 data_bw_er:1; + u8 multiport_id:1; + u8 mbssid:4; + u8 signaling_ta_pkt_sc:4; + u8 sw_define:4; + u8 txpwr_ofset_type:3; + u8 lifetime_sel:3; + u8 stf_mode:1; + u8 disdatafb:1; + u8 data_txcnt_lmt_sel:1; + u8 data_txcnt_lmt:6; + u8 sifs_tx:1; + u8 snd_pkt_sel:3; + u8 ndpa:2; + u8 rsvd:3; +}; + +#define HAL_FEXG_TYPE_AC_SU 31 +#define HAL_FEXG_TYPE_AC_MU_1 32 +#define HAL_FEXG_TYPE_AC_MU_2 33 +#define HAL_FEXG_TYPE_AC_MU_3 34 +#define HAL_FEXG_TYPE_AX_SU 35 +#define HAL_FEXG_TYPE_AX_MU_1 36 +#define HAL_FEXG_TYPE_AX_MU_2 37 + +struct hal_ax_fwcmd_snd { + u8 frame_ex_type; + u8 bfrp0_sta_nr; + u8 bfrp1_sta_nr; + u16 macid[8]; + struct hal_ndpa_para ndpa; + struct hal_bfrp_para bfrp; + /** + * HE: NDPA NDP HE_Trigger_BFRP (CSI) BFRP (CSI) + * VHT: NDPA NDP (CSI) VHT_BFRP (CSI) BFRP (CSI) BFRP (CSI) + **/ + struct hal_snd_wd_para wd[HLA_MAX_BFRP_NUM + 2]; +}; + + +struct rtw_hal_com_t; +struct hal_io_ops { + u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr); + u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr); + u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr); + void (*_read_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem); + + int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); + int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); + int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); + int (*_write_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 length, u8 *pdata); + +#ifdef RTW_WKARD_BUS_WRITE + int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, u32 val); +#endif + +#ifdef CONFIG_SDIO_HCI + u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr); + u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr); + u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr); + int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); + int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); + int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif +}; + +struct hal_io_priv { + #ifdef CONFIG_SDIO_INDIRECT_ACCESS + _os_mutex sd_indirect_access_mutex; + #endif + struct hal_io_ops io_ops; +}; + +#define halcom_to_drvpriv(_hcom) (_hcom->drv_priv) +#define hal_get_chip_id(_halcom) (_halcom->chip_id) + +enum pcfg_type { + PCFG_FUNC_SW, + PCFG_TBTT_AGG, + PCFG_TBTT_SHIFT, + PCFG_HIQ_WIN, + PCFG_HIQ_DTIM, + PCFG_HIQ_MAX, + PCFG_BCN_INTERVAL, /* Beacon Interval */ + PCFG_BSS_CLR, + PCFG_BCN_EN +}; + +/* + * refers to _usb.h + * #define USB11 0x1 + * #define USB2 0x2 + * #define USB3 0x3 + * */ +enum usb_type { + USB_1_1 = 1, + USB_2_0, + USB_3_0, +}; +#ifdef RTW_PHL_BCN +struct bcn_entry_pool { + u8 bcn_num; + _os_list bcn_list; + _os_lock bcn_lock; +}; +#endif + +enum rtw_hal_set_def_var_rsn { + SET_DEF_RSN_HAL_INIT, + SET_DEF_RSN_WOW_RESUME_HNDL_RX, + SET_DEF_RSN_WOW_RESUME_DONE +}; + +struct hal_intr_mask_cfg { + u8 halt_c2h_en; + u8 wdt_en; +}; + +struct hal_halt_c2h_int { + /* halt c2h */ + u32 intr; + u32 val_mask; + u32 val_default; +}; + +struct hal_watchdog_timer_int { + /* watchdog timer */ + u32 intr; + u32 val_mask; + u32 val_default; +}; + +struct hal_int_array { + struct hal_halt_c2h_int halt_c2h_int; + struct hal_watchdog_timer_int watchdog_timer_int; +}; + +/* c2h event id for hal/phl layer */ +enum rtw_hal_c2h_ev { + HAL_C2H_EV_DO_NOTHING = 0, + HAL_C2H_EV_BB_MUGRP_DOWN = 1,/* BB Process C2H mu-score-tbl done */ + HAL_C2H_EV_BTC_INFO = 2, /* BTC event */ + HAL_C2H_EV_BTC_SCBD = 3, /* BTC event */ + HAL_C2H_EV_MAC_TSF32_TOG = 4, /* MAC event */ + HAL_C2H_EV_MAX +}; + +/* ppdu status : per user info */ +struct hal_ppdu_sts_usr { + /* MAC */ + u8 vld:1; + u8 has_data:1; + u8 has_ctrl:1; + u8 has_mgnt:1; + u8 has_bcn:1; + u16 macid; +}; + +enum hal_rxcnt_sel { + HAL_RXCNT_OFDM_OK = 0, + HAL_RXCNT_OFDM_FAIL = 1, + HAL_RXCNT_OFDM_FAM = 2, + HAL_RXCNT_CCK_OK = 3, + HAL_RXCNT_CCK_FAIL = 4, + HAL_RXCNT_CCK_FAM = 5, + HAL_RXCNT_HT_OK = 6, + HAL_RXCNT_HT_FAIL = 7, + HAL_RXCNT_HT_PPDU = 8, + HAL_RXCNT_HT_FAM = 9, + HAL_RXCNT_VHTSU_OK = 0xA, + HAL_RXCNT_VHTSU_FAIL = 0xB, + HAL_RXCNT_VHTSU_PPDU = 0xC, + HAL_RXCNT_VHTSU_FAM = 0xD, + HAL_RXCNT_VHTMU_OK = 0xE, + HAL_RXCNT_VHTMU_FAIL = 0xF, + HAL_RXCNT_VHTMU_PPDU = 0x10, + HAL_RXCNT_VHTMU_FAM = 0x11, + HAL_RXCNT_HESU_OK = 0x12, + HAL_RXCNT_HESU_FAIL = 0x13, + HAL_RXCNT_HESU_PPDU = 0x14, + HAL_RXCNT_HESU_FAM = 0x15, + HAL_RXCNT_HEMU_OK = 0x16, + HAL_RXCNT_HEMU_FAIL = 0x17, + HAL_RXCNT_HEMU_PPDU = 0x18, + HAL_RXCNT_HEMU_FAM = 0x19, + HAL_RXCNT_HETB_OK = 0x1A, + HAL_RXCNT_HETB_FAIL = 0x1B, + HAL_RXCNT_HETB_PPDU = 0x1C, + HAL_RXCNT_HETB_FAM = 0x1D, + HAL_RXCNT_INVD = 0x1E, + HAL_RXCNT_RECCA = 0x1F, + HAL_RXCNT_FULLDRP = 0x20, + HAL_RXCNT_FULLDRP_PKT = 0x21, + HAL_RXCNT_RXDMA = 0x22, + HAL_RXCNT_USER0 = 0x23, + HAL_RXCNT_USER1 = 0x24, + HAL_RXCNT_USER2 = 0x25, + HAL_RXCNT_USER3 = 0x26, + HAL_RXCNT_CONT_FCS = 0x27, + HAL_RXCNT_PKTFLTR_DRP = 0x28, + HAL_RXCNT_CSIPKT_DMA_OK = 0x29, + HAL_RXCNT_CSIPKT_DMA_DROP = 0x2A, + HAL_RXCNT_MAX +}; + +enum hal_rate_mode { + HAL_LEGACY_MODE = 0, + HAL_HT_MODE = 1, + HAL_VHT_MODE = 2, + HAL_HE_MODE = 3 +}; + +enum hal_rate_bw { + HAL_RATE_BW_20 = 0, + HAL_RATE_BW_40 = 1, + HAL_RATE_BW_80 = 2, + HAL_RATE_BW_160 = 3, +}; + +struct hal_ppdu_rx_cnt { + u16 ppdu_cnt[HAL_RXCNT_MAX]; +}; + +/* ppdu sts mac bmp_append_info */ +#define HAL_PPDU_MAC_INFO BIT(1) +#define HAL_PPDU_PLCP BIT(3) +#define HAL_PPDU_RX_CNT BIT(2) +/* ppdu sts mac bmp_filter */ +#define HAL_PPDU_HAS_A1M BIT(4) +#define HAL_PPDU_HAS_CRC_OK BIT(5) + +/* ppdu status (mac info + phy info) */ +struct hal_ppdu_sts { +#define RTW_HAL_PPDU_STS_MAX_USR 4 + /* MAC */ + /* NOTE: (rx_cnt, plcp, phy_st)_ptr are only available before phl_recycle_rx_buf() */ + u8 *rx_cnt_ptr; + u8 *plcp_ptr; + u8 *phy_st_ptr; /* for bb phy status */ + u8 plcp_size; + u32 phy_st_size;/* for bb phy status */ + u32 rx_cnt_size; + u8 usr_num; + struct hal_ppdu_sts_usr usr[RTW_HAL_PPDU_STS_MAX_USR]; + struct hal_ppdu_rx_cnt rx_cnt; +}; + +#define HAL_RSSI_MAVG_NUM 16 +#define STA_UPDATE_MA_RSSI_FAST(_RSSI, _VAL) _RSSI = ((_RSSI * \ + (HAL_RSSI_MAVG_NUM - 1)) + _VAL) \ + / HAL_RSSI_MAVG_NUM + +struct rtw_cfo_info { + s32 cfo_tail; + s32 pre_cfo_avg; + s32 cfo_avg; + u16 cfo_cnt; + u32 tp; +}; + +struct rtw_rssi_info { + u8 rssi; /* u(8,1), hal-bb provide, read only : 0~110 (dBm = rssi -110) */ + u16 rssi_ma; /* u(16,5), hal-bb provide, read only : u16 U(12,4)*/ + u16 rssi_ma_path[4]; + u16 pkt_cnt_data; + u8 rssi_bcn; /* u(8,1), beacon RSSI, hal-bb provide, read only : 0~110 (dBm = rssi -110) */ + u16 rssi_bcn_ma; /* u(16,5), beacon RSSI, hal-bb provide, read only*/ + u16 pkt_cnt_bcn; + u8 ma_factor:4; + u8 ma_factor_bcn:4; + u8 rssi_ofdm; /* u(8,1), hal-bb provide, read only : packet, for debug */ + u8 rssi_cck; /* u(8,1), hal-bb provide, read only : packet, for debug */ + u8 assoc_rssi; /* phl_rx provide, read only */ + /* phl_rx provide, read only : Moving Average RSSI information for the STA */ + u8 ma_rssi; /* moving average : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ + u8 ma_rssi_mgnt; /* moving average rssi for beacon/probe : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ + u16 snr_ma; /* u(16,4), hal-bb provide, read only, SNR= snr_ma dBm*/ +}; + +struct rtw_rate_info { + enum rtw_gi_ltf gi_ltf; /* 3bit GILTF */ + enum hal_rate_mode mode; /* 2bit 0:legacy, 1:HT, 2:VHT, 3:HE*/ + enum hal_rate_bw bw; /*2bit 0:5M/10M/20M, 1:40M, 2:80M, 3:160M or 80+80*/ + u8 mcs_ss_idx; /*HE: 3bit SS + 4bit MCS; non-HE: 5bit MCS/rate idx */ +}; + +/* from cmn_sta_info */ +struct rtw_ra_sta_info { + /*u8 rate_id; remove !!! use wmode in phl, [PHYDM] ratr_idx*/ + /*u8 rssi_level; [PHYDM]*/ + /*u8 is_first_connect:1; change connect flow, [PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/ + /*u8 is_support_sgi:1; mov to phl [driver]*/ + /*u8 is_vht_enable:2; mov to phl [driver]*/ + /*u8 disable_ra:1; mov to hal [driver]*/ + /*u8 disable_pt:1; remove for no PT, [driver] remove is_disable_power_training*/ + /*u8 txrx_state:2; ///////////////need to check if needed, [PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/ + /*u8 is_noisy:1; ///////////////need to check if needed, [PHYDM]*/ + u16 curr_tx_rate; /*use struct bb_rate_info, [PHYDM] FW->Driver*/ + enum channel_width ra_bw_mode; /*remove to phl, [Driver] max bandwidth, for RA only*/ + enum channel_width curr_tx_bw; /*bb_rate_info, [PHYDM] FW->Driver*/ + /* u8 drv_ractrl; */ + + /* Ctrl */ + u8 ra_nss_limit; /* 0: no limitation, otherwise, limit to tx nss pkt*/ + bool dis_ra; /*move from rtw_hal_stainfo_t*/ + bool ra_registered;/*move from rtw_hal_stainfo_t*/ + u64 ra_mask;/*move from rtw_hal_stainfo_t*/ /*drv decide by specific req*/ + u64 cur_ra_mask;/*move from rtw_hal_stainfo_t*/ + /*halbb create, mod by driver and decide by rssi or other*/ + u8 cal_giltf; /* 3bit gi_ltf ctrl by driver*/ + bool fix_giltf_en; /*giltf from cal_giltf or halbb*/ + bool fixed_rt_en; + struct rtw_rate_info fixed_rt_i; + u8 rainfo_cfg1; /* prepare for other control*/ + u8 rainfo_cfg2; /* prepare for other control*/ + + /* Report */ + struct rtw_rate_info rpt_rt_i; + u8 curr_retry_ratio; /*[HALBB] FW->Driver*/ + + bool ra_csi_rate_en; + bool fixed_csi_rate_en; + u8 band_num; + struct rtw_rate_info csi_rate; + + u8 avg_agg; + u32 tx_ok_cnt[4]; + u32 tx_retry_cnt[4]; + u32 tx_total_cnt; + /*u64 ramask;*/ +}; + +struct rtw_mura_info { + /* Ctrl */ + bool fixed_rt_en; + struct rtw_rate_info fixed_rt_i; + /* Report */ + struct rtw_rate_info rpt_rt_i; + u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/ +}; + +/* from cmn_sta_info */ +struct rtw_dtp_info { + u8 dyn_tx_power; /*Dynamic Tx power offset*/ + u8 last_tx_power; + u8 sta_tx_high_power_lvl:4; + u8 sta_last_dtp_lvl:4; +}; + +struct rtw_hal_muba_info { + u32 fix_ba:1; + u32 ru_psd:9; + u32 tf_rate:9; + u32 rf_gain_fix:1; + u32 rf_gain_idx:10; + u32 tb_ppdu_bw:2; + u8 dcm:1; + u8 ss:3; + u8 mcs:4; + u8 gi_ltf:3; + u8 doppler:1; + u8 stbc:1; + u8 sta_coding:1; + u8 tb_t_pe_nom:2; + u8 pr20_bw_en:1; + u8 ma_type: 1; + u8 rsvd1: 6; +}; + +enum rtw_hal_protection_type { + HAL_PROT_NO_PROETCT = 0, + HAL_PROT_PRIUSER_HW_RTS = 1, + HAL_PROT_RTS = 2, + HAL_PROT_CTS2SELF = 3, + HAL_PROT_MU_RTS = 4, + HAL_PROT_HW_DEFAULT_ = 5 +}; + +enum rtw_hal_ack_resp_type { + HAL_ACK_N_MINUS_1USER_BA = 0, + HAL_ACK_N_USER_BA = 1, + HAL_ACK_MU_BAR = 2, + HAL_ACK_HTP_ACK = 3, + HAL_ACK_HW_DEFAULT = 4 +}; + +struct rtw_wp_rpt_stats { + u32 busy_cnt; + u32 tx_ok_cnt; + u32 rty_fail_cnt; + u32 lifetime_drop_cnt; + u32 macid_drop_cnt; + u32 sw_drop_cnt; + u32 recycle_fail_cnt; + u32 delay_tx_ok_cnt; + u32 delay_rty_fail_cnt; + u32 delay_lifetime_drop_cnt; + u32 delay_macid_drop_cnt; +}; + +struct rtw_trx_stat { + u32 rx_ok_cnt; + u32 rx_err_cnt; + u16 rx_rate_plurality; + /* add lock for tx statistics */ + _os_lock tx_sts_lock; + /* Below info is for release report*/ + u32 tx_fail_cnt; + u32 tx_ok_cnt; +#ifdef CONFIG_USB_HCI + struct rtw_wp_rpt_stats wp_rpt_stats[PHL_AC_QUEUE_TOTAL]; +#endif +#ifdef CONFIG_PCI_HCI + u8 *wp_rpt_stats; + u32 ltr_tx_dly_count; + u32 ltr_last_tx_dly_time; +#endif +}; + +struct bacam_ctrl_t { + u8 used_map[MAX_BAENTRY]; + u8 tid[MAX_BAENTRY]; + u8 count; +}; + +struct rtw_hal_stainfo_t { + /* from cmn_sta_info */ + u16 dm_ctrl; + /* struct su_ra_info */ + struct rtw_rssi_info rssi_stat; + struct rtw_cfo_info cfo_stat; + + /* Beamform Related */ + u8 bf_cap;/* sta's beamform capability : ht/vht/he + bfee/bfer */ + void *bf_entry; + u16 bf_csi_buf; + u16 bf_csi_buf_swap;/*used in mu swap mode*/ + /* BFee capability */ + u8 max_nc; + u8 nr; + u8 ng16;/* 0:non-support ; BIT0:support SU ; BIT1:support MU */ + u8 cb_sz;/* 0:non-support ; BIT0:support (4,2) SU ; BIT1:support (7,5) MU */ + u8 support_cqi_fb; + /*mu group*/ + u8 mugrp_bmp; + u32 mu_score; + /*FW Frame Exchange : when STA is primary STA, prefer protect type and ack resp type in MU*/ + enum rtw_hal_protection_type prot_type; + enum rtw_hal_ack_resp_type resp_type; + struct bacam_ctrl_t ba_ctl; + + /* from cmn_sta_info */ + struct rtw_ra_sta_info ra_info; + /* from cmn_sta_info */ + struct rtw_dtp_info dtp_stat; + struct rtw_trx_stat trx_stat; + void *hw_cfg_tab; + void *bb_sta; +}; + + + +struct bus_hw_cap_t { +#ifdef CONFIG_PCI_HCI + enum rtw_pcie_bus_func_cap_t l0s_ctrl; + enum rtw_pcie_bus_func_cap_t l1_ctrl; + enum rtw_pcie_bus_func_cap_t l1ss_ctrl; + enum rtw_pcie_bus_func_cap_t wake_ctrl; + enum rtw_pcie_bus_func_cap_t crq_ctrl; + u8 clkdly_ctrl; + u8 l0sdly_ctrl; + u8 l1dly_ctrl; + u8 ltr_sw_ctrl; /* whether ltr can be controlled by sw */ + u8 ltr_hw_ctrl; + u32 max_txbd_num; + u32 max_rxbd_num; + u32 max_rpbd_num; + u8 max_phyaddr_num; + u8 max_wd_page_size; + u8 txbd_len; + u8 rxbd_len; + u8 wdb_size; + u8 wdi_size; + u8 addr_info_size; + u8 seq_info_size; +#elif defined (CONFIG_USB_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 tx_h2c_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; + u32 in_token_num; +#elif defined (CONFIG_SDIO_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; +#else + u8 temp_for_struct_empty; /* for undefined interface */ +#endif +}; + +/* phy capability of phy */ +struct phy_hw_cap_t { + #ifdef RTW_WKARD_BTC_RFETYPE + u8 rfe_type; + #endif + u8 tx_num; + u8 rx_num; + u16 hw_rts_time_th; + u16 hw_rts_len_th; +}; + + +/*PHYx + Sx*/ +enum phl_phy_idx { + HW_PHY_0, + HW_PHY_1, + HW_PHY_MAX +}; + +enum phl_pwr_table { + PWR_BY_RATE = BIT0, + PWR_LIMIT = BIT1, + PWR_LIMIT_RU = BIT2 +}; + +enum phl_rf_mode { + RF_MODE_NORMAL = 0, + RF_MODE_SHUTDOWN = 1, + RF_MODE_STANDBY = 2, + RF_MODE_RX = 3, + RF_MODE_TX = 4, + RF_MODE_MAX +}; + + +/*--------------------------------------------------------------------------*/ +/*[TX Power Unit(TPU) array size]*/ +#define TPU_SIZE_PWR_TAB 16 /*MCS0~MCS11(12) + {dcm_0,1,3,4}4 = 16*/ +#define TPU_SIZE_PWR_TAB_lGCY 12 /*cck(4) + ofdm(8) = 12*/ +#define TPU_SIZE_MODE 5 /*0~4: HE, VHT, HT, Legacy, CCK, */ +#define TPU_SIZE_BW 5 /*0~4: 80_80, 160, 80, 40, 20*/ +#define TPU_SIZE_RUA 3 /*{26, 52, 106}*/ +#define TPU_SIZE_BW20_SC 8 /*8 * 20M = 160M*/ +#define TPU_SIZE_BW40_SC 4 /*4 * 40M = 160M*/ +#define TPU_SIZE_BW80_SC 2 /*2 * 80M = 160M*/ +#define TPU_SIZE_BF 2 /*{NON_BF, BF}*/ + +#if defined(CONFIG_RTL8851A) + #define HAL_COMPILE_IC_1SS +#endif + +#if (defined(CONFIG_RTL8852A) || defined(CONFIG_RTL8852B) || defined(CONFIG_RTL8852C)) + #define HAL_COMPILE_IC_2SS +#endif + +#if defined(CONFIG_RTL8853A) + #define HAL_COMPILE_IC_3SS +#endif + +#if defined(CONFIG_RTL8834A) + #define HAL_COMPILE_IC_4SS +#endif + +/*@==========================================================================*/ +#if (defined(HAL_COMPILE_IC_4SS)) + #define HAL_COMPILE_ABOVE_4SS +#endif + +#if (defined(HAL_COMPILE_IC_3SS) || defined(HAL_COMPILE_ABOVE_4SS)) + #define HAL_COMPILE_ABOVE_3SS +#endif + +#if (defined(HAL_COMPILE_IC_2SS) || defined(HAL_COMPILE_ABOVE_3SS)) + #define HAL_COMPILE_ABOVE_2SS +#endif + +#if (defined(HAL_COMPILE_IC_1SS) || defined(HAL_COMPILE_ABOVE_2SS)) + #define HAL_COMPILE_ABOVE_1SS +#endif + +#if (defined(HAL_COMPILE_ABOVE_4SS)) + #define HAL_MAX_PATH 4 +#elif (defined(HAL_COMPILE_ABOVE_3SS)) + #define HAL_MAX_PATH 3 +#elif (defined(HAL_COMPILE_ABOVE_2SS)) + #define HAL_MAX_PATH 2 +#else + #define HAL_MAX_PATH 1 +#endif + +/*--------------------------[Structure]-------------------------------------*/ +enum rtw_tpu_op_mode { + TPU_NORMAL_MODE = 0, + TPU_DBG_MODE = 1 +}; + +struct rtw_tpu_pwr_by_rate_info { /*TX Power Unit (TPU)*/ + s8 pwr_by_rate_lgcy[TPU_SIZE_PWR_TAB_lGCY]; + s8 pwr_by_rate[HAL_MAX_PATH][TPU_SIZE_PWR_TAB]; +}; + +struct rtw_tpu_ext_pwr_lmt_info { /*TX Power Unit (TPU)*/ + s8 ext_pwr_lmt_2_4g[HAL_MAX_PATH]; + s8 ext_pwr_lmt_5g_band1[HAL_MAX_PATH]; /*CH36 ~ CH48*/ + s8 ext_pwr_lmt_5g_band2[HAL_MAX_PATH]; /*CH52 ~ CH64*/ + s8 ext_pwr_lmt_5g_band3[HAL_MAX_PATH]; /*CH100 ~ CH144*/ + s8 ext_pwr_lmt_5g_band4[HAL_MAX_PATH]; /*CH149 ~ CH165*/ +}; + +struct rtw_tpu_pwr_imt_info { /*TX Power Unit (TPU)*/ + s8 pwr_lmt_cck_20m[HAL_MAX_PATH][TPU_SIZE_BF]; + s8 pwr_lmt_cck_40m[HAL_MAX_PATH][TPU_SIZE_BF]; + s8 pwr_lmt_lgcy_20m[HAL_MAX_PATH][TPU_SIZE_BF]; /*ofdm*/ + s8 pwr_lmt_20m[HAL_MAX_PATH][TPU_SIZE_BW20_SC][TPU_SIZE_BF]; + s8 pwr_lmt_40m[HAL_MAX_PATH][TPU_SIZE_BW40_SC][TPU_SIZE_BF]; + s8 pwr_lmt_80m[HAL_MAX_PATH][TPU_SIZE_BW80_SC][TPU_SIZE_BF]; + s8 pwr_lmt_160m[HAL_MAX_PATH][TPU_SIZE_BF]; + s8 pwr_lmt_40m_0p5[HAL_MAX_PATH][TPU_SIZE_BF]; + s8 pwr_lmt_40m_2p5[HAL_MAX_PATH][TPU_SIZE_BF]; +}; + +struct rtw_tpu_info { /*TX Power Unit (TPU)*/ + enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/ + bool normal_mode_lock_en; + s8 ofst_int; /*SW: S(8,3) -16 ~ +15.875 (dB)*/ + u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/ + u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/ + u16 tssi_16dBm_cw; + /*[Ref Pwr]*/ + s16 ref_pow_ofdm; /*-> HW: s(9,2)*/ + s16 ref_pow_cck; /*-> HW: s(9,2)*/ + u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/ + u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/ + /*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/ + s8 pwr_ofst_mode[TPU_SIZE_MODE]; /*0~4: HE, VHT, HT, Legacy, CCK, */ + s8 pwr_ofst_bw[TPU_SIZE_BW]; /*0~4: 80_80, 160, 80, 40, 20*/ + /*[Pwr By rate]*/ /*-> HW: s(7,1)*/ + struct rtw_tpu_pwr_by_rate_info rtw_tpu_pwr_by_rate_i; + /*[Pwr Limit]*/ /*-> HW: s(7,1)*/ + struct rtw_tpu_pwr_imt_info rtw_tpu_pwr_imt_i; + /*[Pwr Limit RUA]*/ /*-> HW: s(7,1)*/ + s8 pwr_lmt_ru[HAL_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC]; + u16 pwr_lmt_ru_mem_size; + bool pwr_lmt_en; + u8 tx_ptrn_shap_idx; + u8 tx_ptrn_shap_idx_cck; +}; + +struct rtw_hal_stat_info { + u32 cnt_fail_all; + u32 cnt_cck_fail; + u32 cnt_ofdm_fail; + u32 cnt_cca_all; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_crc32_error_all; + u32 cnt_he_crc32_error; + u32 cnt_vht_crc32_error; + u32 cnt_ht_crc32_error ; + u32 cnt_ofdm_crc32_error; + u32 cnt_cck_crc32_error; + u32 cnt_crc32_ok_all; + u32 cnt_he_crc32_ok; + u32 cnt_vht_crc32_ok; + u32 cnt_ht_crc32_ok; + u32 cnt_ofdm_crc32_ok; + u32 cnt_cck_crc32_ok; + u32 igi_fa_rssi; +}; + +struct rtw_hw_band { + struct rtw_chan_def cur_chandef; + u8 ppdu_sts_appen_info; + u8 ppdu_sts_filter; + struct rtw_tpu_info rtw_tpu_i; /*TX Power Unit (TPU)*/ + u16 tx_pause[PAUSE_RSON_MAX]; /* ref: enum rtw_sch_txen_cfg */ + struct rtw_hal_stat_info stat_info; +}; + +struct rtw_hal_com_t { + enum rtw_chip_id chip_id; + enum rtw_cv cv; + + struct ver_ctrl_t mac_vc; + struct ver_ctrl_t bb_vc; + struct ver_ctrl_t rf_vc; + struct ver_ctrl_t btc_vc; + struct ver_ctrl_t fw_vc; + + struct protocol_cap_t proto_hw_cap[MAX_BAND_NUM]; /* wifi protocol capability from EFUSE/halmac/halbb/halrf/... */ + struct phy_hw_cap_t phy_hw_cap[MAX_BAND_NUM]; /* phy capability from EFUSE/halmac/halbb/halrf/... */ + struct dev_cap_t dev_hw_cap; + + struct bus_hw_cap_t bus_hw_cap; /* Bus HW capability */ + struct bus_cap_t bus_cap; /* Final bus capability */ + struct hal_io_priv iopriv; + #ifdef DBG_HAL_MAC_MEM_MOINTOR + _os_atomic hal_mac_mem; + #endif + #ifdef DBG_HAL_MEM_MOINTOR + _os_atomic hal_mem; + #endif + bool is_hal_init; + struct rtw_hw_band band[MAX_BAND_NUM];/*band0/band1 for DBCC*/ + + bool dbcc_en; + u8 assoc_sta_cnt; /*number of associated nodes (sta or ap)*/ + + u8 rfpath_tx_num; /* rf path - instead of rf_type -1T1R.... */ + u8 rfpath_rx_num; +#ifdef RTW_WKARD_SINGLE_PATH_RSSI + enum rf_path cur_rx_rfpath; +#endif + + bool ext_pwr_lmt_en; + struct rtw_tpu_ext_pwr_lmt_info rtw_tpu_ext_pwr_lmt_i[MAX_BAND_NUM];/*for phy0 & phy1 exetend power limit*/ + + +#ifdef CONFIG_PCI_HCI /*TODO move to hal_info_t*/ + /*interrupt*/ + u32 int_array[4]; + u32 int_mask[4]; + u32 int_mask_default[4]; +#endif /* CONFIG_PCI_HCI */ +#ifdef CONFIG_SDIO_HCI /*TODO move to hal_info_t*/ + u32 block_sz; + + /*interrupt*/ + /* + * Change type of int_mask from u32 to unsigned long for bit operation + * API, ex: _os_test_and_clear_bit() and _os_test_and_set_bit() . + */ + unsigned long int_mask; + u32 int_mask_default; +#endif /* CONFIG_SDIO_HCI */ + + struct hal_int_array intr; + +#ifdef RTW_PHL_BCN + struct bcn_entry_pool bcn_pool; +#endif + struct rtw_trx_stat trx_stat; + void *hal_priv;/*pointer to hal_info*/ + void *drv_priv; /*drv priv*/ + + void *csi_obj; + void *bf_obj; + void *snd_obj; + + struct hal_mu_score_tbl bb_mu_score_tbl; + bool csi_para_ctrl_sel; + + struct btc_ctrl_t btc_ctrl; + struct btc_fw_msg btc_msg; +#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL + u8 spe_pkt_cnt_lmt; +#endif +}; + +#define FL_CFG_OP_SET 0 +#define FL_CFG_OP_CLR 1 +#define FL_CFG_OP_INFO 2 + +#define FL_CFG_TYPE_LEVEL 0 +#define FL_CFG_TYPE_OUTPUT 1 +#define FL_CFG_TYPE_COMP 2 +#define FL_CFG_TYPE_COMP_EXT 3 + +#define FL_LV_OFF 0 +#define FL_LV_CRT 1 +#define FL_LV_SER 2 +#define FL_LV_WARN 3 +#define FL_LV_LOUD 4 +#define FL_LV_TR 5 + +#define FL_OP_UART BIT0 +#define FL_OP_C2H BIT1 +#define FL_OP_SNI BIT2 + +#define FL_COMP_VER BIT0 +#define FL_COMP_INIT BIT1 +#define FL_COMP_TASK BIT2 +#define FL_COMP_CNS BIT3 +#define FL_COMP_H2C BIT4 +#define FL_COMP_C2H BIT5 +#define FL_COMP_TX BIT6 +#define FL_COMP_RX BIT7 +#define FL_COMP_IPSEC BIT8 +#define FL_COMP_TIMER BIT9 +#define FL_COMP_DBGPKT BIT10 +#define FL_COMP_PS BIT11 +#define FL_COMP_BB BIT16 + +struct rtw_hal_fw_log_cfg { + u32 level; + u32 output; + u32 comp; + u32 comp_ext; +}; + +enum pkt_ofld_op_type { + PKT_OFLD_ADD = 0, + PKT_OFLD_DEL = 1, + PKT_OFLD_READ = 2, + PKT_OFLD_MAX +}; + +struct pkt_ofld_info { + struct list_head req_q; + u32 req_cnt; + u8 id; +}; + +struct pkt_ofld_entry { + struct list_head list; + u16 macid; + struct pkt_ofld_info pkt_info[PKT_OFLD_TYPE_MAX]; +}; + +enum rtw_c2h_cat { + C2H_CAT_TEST = 0, + C2H_CAT_MAC = 1, + C2H_CAT_OUTSRC = 2, + C2H_CAT_MAX = 3 +}; + +enum rtw_c2h_clas { + C2H_CLS_PHYDM_MIN = 0, + C2H_CLS_PHYDM_MAX = 7, + C2H_CLS_RF_MIN = 8, + C2H_CLS_RF_MAX = 0xf, + C2H_CLS_BTC_MIN = 0x10, + C2H_CLS_BTC_MAX = 0x17, + C2H_CLS_MAX = 0x18 +}; + +#define C2H_CLS_MAC_MIN 0x00 +#define C2H_CLS_MAC_MAX 0xFF + +enum rtw_hal_ps_pwr_req_src { + HAL_BB_PWR_REQ = 0, + HAL_RF_PWR_REQ = 1, + HAL_MAC_PWR_REQ = 2, + HAL_BTC_PWR_REQ = 3 +}; + +struct rtw_hal_lps_info { + u8 lps_en; + u16 macid; + enum rtw_lps_listen_bcn_mode listen_bcn_mode; + u8 awake_interval; + enum rtw_lps_smart_ps_mode smart_ps_mode; +}; + +enum ps_pwr_state { + PS_PWR_STATE_ACTIVE = 0, + PS_PWR_STATE_BAND0_RFON = 1, + PS_PWR_STATE_BAND1_RFON = 2, + PS_PWR_STATE_BAND0_RFOFF = 3, + PS_PWR_STATE_BAND1_RFOFF = 4, + PS_PWR_STATE_CLK_GATED = 5, + PS_PWR_STATE_PWR_GATED = 6, + PS_PWR_STATE_MAX, +}; + +#ifdef CONFIG_PHL_DFS +struct hal_dfs_rpt { + u8 *dfs_ptr; + u16 dfs_num; + u8 phy_idx; /*phy0,phy1*/ +}; +#endif + +#ifdef CONFIG_WOWLAN +struct rtw_hal_wow_cfg { + struct rtw_keep_alive_info *keep_alive_cfg; + struct rtw_disc_det_info *disc_det_cfg; + struct rtw_nlo_info *nlo_cfg; + struct rtw_arp_ofld_info *arp_ofld_cfg; + struct rtw_ndp_ofld_info *ndp_ofld_cfg; + struct rtw_gtk_ofld_info *gtk_ofld_cfg; + struct rtw_realwow_info *realwow_cfg; + struct rtw_wow_wake_info *wow_wake_cfg; + struct rtw_pattern_match_info *pattern_match_info; + struct rtw_wow_gpio_info *wow_gpio; +}; +#endif /* CONFIG_WOWLAN */ + + +enum hal_tsf_sync_act { + HAL_TSF_SYNC_NOW_ONCE = 0, + HAL_TSF_EN_SYNC_AUTO = 1, + HAL_TSF_DIS_SYNC_AUTO = 2, +}; + +#ifdef CONFIG_RTW_ACS +struct auto_chan_sel_report { + u8 clm_ratio; + u8 nhm_pwr; +}; +#endif + +struct watchdog_nhm_report { + u8 ccx_rpt_stamp; + u8 ccx_rpt_result; + s8 nhm_pwr_dbm; + u8 nhm_ratio; +}; + +struct hal_mac_dbg_dump_cfg { + u32 ss_dbg_0; + u32 ss_dbg_1; + u8 ss_dbg; + u8 dle_dbg; + u8 dmac_dbg; + u8 cmac_dbg; + u8 mac_dbg_port; + u8 plersvd_dbg; + u8 tx_flow_dbg; +}; + +#endif /*_HAL_DEF_H_*/ diff --git a/phl/hal_g6/hal_def_btc.h b/phl/hal_g6/hal_def_btc.h new file mode 100644 index 0000000..93c1cc3 --- /dev/null +++ b/phl/hal_g6/hal_def_btc.h @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_DEF_BTC_H_ +#define _HAL_DEF_BTC_H_ + +#endif /*_HAL_DEF_BTC_H_*/ diff --git a/phl/hal_g6/hal_def_mac.h b/phl/hal_g6/hal_def_mac.h new file mode 100644 index 0000000..7785263 --- /dev/null +++ b/phl/hal_g6/hal_def_mac.h @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_DEF_MAC_H_ +#define _HAL_DEF_MAC_H_ + +#endif /*_HAL_DEF_MAC_H_*/ diff --git a/phl/hal_g6/hal_def_phy.h b/phl/hal_g6/hal_def_phy.h new file mode 100644 index 0000000..ec67dda --- /dev/null +++ b/phl/hal_g6/hal_def_phy.h @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_DEF_PHY_H_ +#define _HAL_DEF_PHY_H_ + +#endif /*_HAL_DEF_PHY_H_*/ diff --git a/phl/hal_g6/hal_ext_tx_pwr_lmt.c b/phl/hal_g6/hal_ext_tx_pwr_lmt.c new file mode 100644 index 0000000..d34be66 --- /dev/null +++ b/phl/hal_g6/hal_ext_tx_pwr_lmt.c @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_EXT_TX_PWR_LMT_C_ +#include "hal_headers.h" + + +enum rtw_hal_status +rtw_hal_set_power_lmt(void *hal, u8 band_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + enum phl_phy_idx phy_idx = HW_PHY_0; + + if (band_idx == 1) + phy_idx = HW_PHY_1; + + status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT); + + return status; +} + + +void +rtw_hal_enable_ext_pwr_lmt(void *hal, u8 hw_band, + struct rtw_tpu_ext_pwr_lmt_info *ext_pwr_lmt_info) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_tpu_ext_pwr_lmt_info *tpu_ext_pwr_lmt_info; + u8 i; + + PHL_INFO("%s\n", __func__); + + tpu_ext_pwr_lmt_info = &(hal_com->rtw_tpu_ext_pwr_lmt_i[hw_band]); + + /* enable external tx power limit mechanism */ + hal_com->ext_pwr_lmt_en = true; + + /* Fill external tx power limit into hal_com->rtw_tpu_ext_pwr_lmt_info */ + for (i = 0; i < HAL_MAX_PATH; i++) { + tpu_ext_pwr_lmt_info->ext_pwr_lmt_2_4g[i] + = ext_pwr_lmt_info->ext_pwr_lmt_2_4g[i]; + + tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band1[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band1[i]; + tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band2[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band2[i]; + tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band3[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band3[i]; + tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band4[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band4[i]; + } + + rtw_hal_rf_update_ext_pwr_lmt_table(hal_info); + +} + diff --git a/phl/hal_g6/hal_fw.c b/phl/hal_g6/hal_fw.c new file mode 100644 index 0000000..36324e5 --- /dev/null +++ b/phl/hal_g6/hal_fw.c @@ -0,0 +1,268 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_FW_C_ +#include "hal_headers.h" + +static void _hal_send_fwdl_hub_msg(struct rtw_phl_com_t *phl_com, u8 dl_ok) +{ + struct phl_msg msg = {0}; + u16 evt_id = (dl_ok) ? MSG_EVT_FWDL_OK : MSG_EVT_FWDL_FAIL; + + msg.inbuf = NULL; + msg.inlen = 0; + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id); + msg.band_idx = HW_BAND_0; + rtw_phl_msg_hub_hal_send(phl_com, NULL, &msg); +} + +static void _hal_fw_log_set(struct rtw_hal_fw_log_cfg *fl_cfg, u8 type, u32 value) +{ + switch(type) { + case FL_CFG_TYPE_LEVEL: + fl_cfg->level = value; + break; + + case FL_CFG_TYPE_OUTPUT: + fl_cfg->output |= value; + break; + + case FL_CFG_TYPE_COMP: + fl_cfg->comp |= value; + break; + + case FL_CFG_TYPE_COMP_EXT: + fl_cfg->comp_ext |= value; + break; + + default: + break; + } +} + +static void _hal_fw_log_clr(struct rtw_hal_fw_log_cfg *fl_cfg, u8 type, u32 value) +{ + switch(type) { + case FL_CFG_TYPE_LEVEL: + break; + + case FL_CFG_TYPE_OUTPUT: + fl_cfg->output &= (~value); + break; + + case FL_CFG_TYPE_COMP: + fl_cfg->comp &= (~value); + break; + + case FL_CFG_TYPE_COMP_EXT: + fl_cfg->comp_ext &= (~value); + break; + + default: + break; + } +} + +static void _hal_fw_log_info(struct rtw_hal_fw_log_cfg *fl_cfg) +{ + PHL_PRINT("%s: level %d, output 0x%08x, comp 0x%08x, comp ext 0x%08x.\n", + __func__, + fl_cfg->level, + fl_cfg->output, + fl_cfg->comp, + fl_cfg->comp_ext); +} + +enum rtw_hal_status rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value) +{ + struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)hal; + static struct rtw_hal_fw_log_cfg fl_cfg = {0}; + + switch(op) { + case FL_CFG_OP_SET: + _hal_fw_log_set(&fl_cfg, type, value); + break; + case FL_CFG_OP_CLR: + _hal_fw_log_clr(&fl_cfg, type, value); + break; + case FL_CFG_OP_INFO: + _hal_fw_log_info(&fl_cfg); + break; + default: + break; + } + + return rtw_hal_mac_fw_log_cfg(hal_com, &fl_cfg); +} + +void hal_fw_en_basic_log(struct rtw_hal_com_t *hal_com) +{ + rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_LEVEL, + FL_LV_LOUD); + rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_OUTPUT, + FL_OP_C2H); + rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_COMP, + FL_COMP_TASK); +} + +enum rtw_hal_status rtw_hal_cfg_fw_ps_log(void *hal, u8 en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + if(en) + return rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_SET, + FL_CFG_TYPE_COMP, FL_COMP_PS); + else + return rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_CLR, + FL_CFG_TYPE_COMP, FL_COMP_PS); +} + +enum rtw_hal_status rtw_hal_cfg_fw_mcc_log(void *hal, u8 en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + if(en) + status = rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_SET, + FL_CFG_TYPE_COMP, MAC_AX_FL_COMP_MCC); + else + status = rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_CLR, + FL_CFG_TYPE_COMP, MAC_AX_FL_COMP_MCC); + + PHL_INFO("rtw_hal_cfg_fw_mcc_log(): status(%d), en(%d)\n", status, en); + return status; +} + +enum rtw_hal_status +rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + + FUNCIN_WSTS(hal_status); + + if (!fw_info->fw_en) + return hal_status; + + if (fw_info->dlrom_en) { + hal_status = rtw_hal_mac_romdl(hal_info, fw_info->rom_buff, + fw_info->rom_size); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + } + + hal_status = rtw_hal_mac_disable_cpu(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("disable cpu fail!\n"); + return hal_status; + } + + hal_status = rtw_hal_mac_enable_cpu(hal_info, 0, true); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("enable cpu fail!\n"); + return hal_status; + } + + if (fw_info->dlram_en) { + hal_status = rtw_hal_mac_fwdl(hal_info, fw_info->ram_buff, + fw_info->ram_size); + } + + _hal_send_fwdl_hub_msg(phl_com, (!hal_status) ? true : false); + + FUNCOUT_WSTS(hal_status); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + + FUNCIN_WSTS(hal_status); + + /* Disable/Enable CPU is necessary first when FWDL from files */ + if(fw_info->dlram_en && fw_info->fw_src == RTW_FW_SRC_EXTNAL) { + + hal_status = rtw_hal_mac_disable_cpu(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("disable cpu fail!\n"); + return hal_status; + } + + hal_status = rtw_hal_mac_enable_cpu(hal_info, 0, true); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("enable cpu fail!\n"); + return hal_status; + } + } + + if (fw_info->dlram_en) { + if(fw_info->fw_src == RTW_FW_SRC_EXTNAL) { + hal_status = rtw_hal_mac_fwdl(hal_info, fw_info->ram_buff, + fw_info->ram_size); + } else { + hal_status = rtw_hal_mac_enable_fw(hal_info, fw_info->fw_type); + } + } + + rtw_phl_pkt_ofld_reset_all_entry(phl_com); + rtw_hal_rf_config_radio_to_fw(hal_info); + + _hal_send_fwdl_hub_msg(phl_com, (!hal_status) ? true : false); + + FUNCOUT_WSTS(hal_status); + + return hal_status; +} + +void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + rtw_hal_mac_fw_dbg_dump(hal_info, is_low_power); +} + +enum rtw_fw_status rtw_hal_get_fw_status(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 mac_fw_sts; + + mac_fw_sts = hal_mac_ops->get_fw_status(mac); + + switch (mac_fw_sts) { + case MACSUCCESS: + return RTW_FW_STATUS_OK; + case MACNOFW: + return RTW_FW_STATUS_NOFW; + case MACFWASSERT: + return RTW_FW_STATUS_ASSERT; + case MACFWEXCEP: + return RTW_FW_STATUS_EXCEP; + case MACFWRXI300: + return RTW_FW_STATUS_RXI300; + case MACFWPCHANG: + return RTW_FW_STATUS_HANG; + default: + return RTW_FW_STATUS_OK; + } +} \ No newline at end of file diff --git a/phl/hal_g6/hal_fw.h b/phl/hal_g6/hal_fw.h new file mode 100644 index 0000000..f5f1952 --- /dev/null +++ b/phl/hal_g6/hal_fw.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_FW_H_ +#define _HAL_FW_H_ + +enum rtw_hal_status +rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal); + +enum rtw_hal_status +rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal); + +void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power); + +enum rtw_hal_status +rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value); + +void hal_fw_en_basic_log(struct rtw_hal_com_t *hal_com); + +#endif /* _HAL_FW_H_ */ + diff --git a/phl/hal_g6/hal_general_def.h b/phl/hal_g6/hal_general_def.h new file mode 100644 index 0000000..0620d6f --- /dev/null +++ b/phl/hal_g6/hal_general_def.h @@ -0,0 +1,287 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_GENERAL_DEF_H_ +#define _HAL_GENERAL_DEF_H_ + +#define RTW_MAC_TBTT_AGG_DEF 1 + +enum rtw_chip_id { + CHIP_WIFI6_8852A, + CHIP_WIFI6_8834A, + CHIP_WIFI6_8852B, + CHIP_WIFI6_8852C, + CHIP_WIFI6_MAX +}; + +enum rtw_efuse_info { + /* MAC Part */ + EFUSE_INFO_MAC_ADDR, + EFUSE_INFO_MAC_PID, + EFUSE_INFO_MAC_DID, + EFUSE_INFO_MAC_VID, + EFUSE_INFO_MAC_SVID, + EFUSE_INFO_MAC_SMID, + EFUSE_INFO_MAC_MAX, + /* BB Part */ + EFUSE_INFO_BB_ANTDIV, + EFUSE_INFO_BB_MAX, + /* RF Part */ + EFUSE_INFO_RF_PKG_TYPE, + EFUSE_INFO_RF_PA, + EFUSE_INFO_RF_VALID_PATH, + EFUSE_INFO_RF_RFE, + EFUSE_INFO_RF_TXPWR, + EFUSE_INFO_RF_BOARD_OPTION, + EFUSE_INFO_RF_CHAN_PLAN, + EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW, + EFUSE_INFO_RF_COUNTRY, + EFUSE_INFO_RF_THERMAL, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5, + EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6, + EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1, + EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2, + EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3, + EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4, + EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13, + EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5, + EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6, + EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1, + EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2, + EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3, + EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4, + EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13, + EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14, + EFUSE_INFO_RF_THERMAL_A, + EFUSE_INFO_RF_THERMAL_B, + EFUSE_INFO_RF_THERMAL_C, + EFUSE_INFO_RF_THERMAL_D, + EFUSE_INFO_RF_XTAL, + /*RX Gain K*/ + EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK, + EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD, + EFUSE_INFO_RF_RX_GAIN_K_A_5GL, + EFUSE_INFO_RF_RX_GAIN_K_A_5GM, + EFUSE_INFO_RF_RX_GAIN_K_A_5GH, + EFUSE_INFO_RF_MAX, + /* BTCOEX Part */ + EFUSE_INFO_BTCOEX_COEX, + EFUSE_INFO_BTCOEX_ANT_NUM, + EFUSE_INFO_BTCOEX_ANT_PATH, + EFUSE_INFO_BTCOEX_MAX, +}; + +enum rtw_cv { + CAV, + CBV, + CCV, + CDV, + CEV, + CFV, + CGV, + CTV, + CMAXV, +}; + +enum rtw_fv { + FTV, + FUV, + FSV, +}; + +enum rtw_dv_sel { + DAV, + DDV, +}; + +enum hal_pwr_by_rate_setting { + PW_BY_RATE_ON = 0, + PW_BY_RATE_ALL_SAME = 1 +}; + +enum hal_pwr_limit_type { + PWLMT_BY_EFUSE = 0, + PWLMT_DISABLE = 1, + PWBYRATE_AND_PWLMT = 2 +}; + +enum rtw_mac_gfunc { + RTW_MAC_GPIO_WL_PD, + RTW_MAC_GPIO_BT_PD, + RTW_MAC_GPIO_WL_EXTWOL, + RTW_MAC_GPIO_BT_GPIO, + RTW_MAC_GPIO_WL_SDIO_INT, + RTW_MAC_GPIO_BT_SDIO_INT, + RTW_MAC_GPIO_WL_FLASH, + RTW_MAC_GPIO_BT_FLASH, + RTW_MAC_GPIO_SIC, + RTW_MAC_GPIO_LTE_UART, + RTW_MAC_GPIO_LTE_3W, + RTW_MAC_GPIO_WL_PTA, + RTW_MAC_GPIO_BT_PTA, + RTW_MAC_GPIO_MAILBOX, + RTW_MAC_GPIO_WL_LED, + RTW_MAC_GPIO_OSC, + RTW_MAC_GPIO_XTAL_CLK, + RTW_MAC_GPIO_EXT_XTAL_CLK, + RTW_MAC_GPIO_DBG_GNT, + RTW_MAC_GPIO_WL_RFE_CTRL, + RTW_MAC_GPIO_BT_UART_RQB, + RTW_MAC_GPIO_BT_WAKE_HOST, + RTW_MAC_GPIO_HOST_WAKE_BT, + RTW_MAC_GPIO_DBG, + RTW_MAC_GPIO_WL_UART_TX, + RTW_MAC_GPIO_WL_UART_RX, + RTW_MAC_GPIO_WL_JTAG, + RTW_MAC_GPIO_SW_IO, + + /* keep last */ + RTW_MAC_GPIO_LAST, + RTW_MAC_GPIO_MAX = RTW_MAC_GPIO_LAST, + RTW_MAC_GPIO_INVALID = RTW_MAC_GPIO_LAST, + RTW_MAC_GPIO_DFLT = RTW_MAC_GPIO_LAST, +}; + + +#ifdef CONFIG_FW_IO_OFLD_SUPPORT +enum rtw_mac_src_cmd_ofld { + RTW_MAC_BB_CMD_OFLD = 0, + RTW_MAC_RF_CMD_OFLD, + RTW_MAC_MAC_CMD_OFLD, + RTW_MAC_OTHER_CMD_OFLD +}; +enum rtw_mac_cmd_type_ofld { + RTW_MAC_WRITE_OFLD = 0, + RTW_MAC_COMPARE_OFLD, + RTW_MAC_DELAY_OFLD +}; +enum rtw_mac_rf_path { + RTW_MAC_RF_PATH_A = 0, //Radio Path A + RTW_MAC_RF_PATH_B, //Radio Path B + RTW_MAC_RF_PATH_C, //Radio Path C + RTW_MAC_RF_PATH_D, //Radio Path D +}; +struct rtw_mac_cmd { + enum rtw_mac_src_cmd_ofld src; + enum rtw_mac_cmd_type_ofld type; + u8 lc; + enum rtw_mac_rf_path rf_path; + u16 offset; + u16 id; + u32 value; + u32 mask; +}; +enum rtw_fw_ofld_cap { + FW_CAP_IO_OFLD = BIT(0), +}; +#endif + +enum wl_func { + EFUSE_WL_FUNC_NONE = 0, + EFUSE_WL_FUNC_DRAGON = 0xe, + EFUSE_WL_FUNC_GENERAL = 0xf +}; + +enum hw_stype{ + EFUSE_HW_STYPE_NONE = 0x0, + EFUSE_HW_STYPE_GENERAL = 0xf +}; + +#endif /* _HAL_GENERAL_DEF_H_*/ + diff --git a/phl/hal_g6/hal_headers.h b/phl/hal_g6/hal_headers.h new file mode 100644 index 0000000..c1c88b9 --- /dev/null +++ b/phl/hal_g6/hal_headers.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_HEADERS_H_ +#define _HAL_HEADERS_H_ +#include "../rtw_general_def.h" +#include "../phl_list.h" +#include "../phl_status.h" +#include "../pltfm_ops.h" +#include "../phl_config.h" +#include "../phl_types.h" +#include "../phl_util.h" +#include "../phl_def.h" +#include "../phl_debug.h" +#include "../phl_trx_def.h" +#include "../phl_wow_def.h" +#include "../phl_p2pps_def.h" +#include "../phl_btc_def.h" +#include "../phl_test_def.h" +#include "../phl_ser_def.h" +#include "../phl_regulation_def.h" +#include "../phl_led_def.h" +#include "../custom/phl_custom_def.h" +#include "../custom/phl_custom_api.h" + +#ifdef CONFIG_PCI_HCI +#include "../hci/phl_trx_def_pcie.h" +#endif +#ifdef CONFIG_USB_HCI +#include "../hci/phl_trx_def_usb.h" +#endif +#ifdef CONFIG_SDIO_HCI +#include "../hci/phl_trx_def_sdio.h" +#endif + +#include "hal_general_def.h" +#include "hal_def.h" +#include "hal_config.h" +#include "../phl_api_drv.h" +#include "hal_struct.h" +#include "hal_io.h" + +#include "hal_api_mac.h" +#include "hal_api_bb.h" +#include "hal_api_rf.h" +#include "hal_api_btc.h" +#include "hal_api_efuse.h" +#include "hal_str_proc.h" + +#include "hal_tx.h" +#include "hal_rx.h" +#include "hal_sta.h" +#include "hal_chan.h" +#ifdef CONFIG_PHL_CHANNEL_INFO +#include "hal_chan_info.h" +#endif /* CONFIG_PHL_CHANNEL_INFO */ +#include "hal_fw.h" +#include "hal_wow.h" + +#include "hal_csi_buffer.h" +#include "hal_beamform.h" +#include "hal_sound.h" +#include "hal_ser.h" +#include "hal_c2h.h" +#include "hal_acs.h" +#include "hal_mcc_def.h" +#include "hal_ld_file.h" +#include "hal_notify.h" +#include "hal_ps.h" +#include "hal_custom.h" +#include "hal_txpwr.h" + +#define hal_to_drvpriv(_halinfo) (_halinfo->hal_com->drv_priv) + +#endif /*_HAL_HEADERS_H_*/ diff --git a/phl/hal_g6/hal_headers_le.h b/phl/hal_g6/hal_headers_le.h new file mode 100644 index 0000000..c665528 --- /dev/null +++ b/phl/hal_g6/hal_headers_le.h @@ -0,0 +1,344 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_HEADERS_LE_H_ +#define _HAL_HEADERS_LE_H_ + +/* Common definition from PHL */ +#include "../rtw_general_def.h" +#include "../phl_list.h" +#include "../phl_status.h" +#include "../pltfm_ops.h" +#include "../phl_config.h" +#include "../phl_types.h" +#include "../phl_regulation_def.h" +#include "../phl_chnlplan.h" +#include "../phl_country.h" +#include "../phl_txpwr.h" +/* Exported structure/definition from PHL */ +#include "../phl_util.h" +#include "../phl_def.h" +#include "../phl_trx_def.h" +#include "../phl_wow_def.h" +#include "../phl_btc_def.h" +#include "../phl_test_def.h" +#include "../phl_debug.h" + +#ifdef CONFIG_PCI_HCI +#include "../hci/phl_trx_def_pcie.h" +#endif +#ifdef CONFIG_USB_HCI +#include "../hci/phl_trx_def_usb.h" +#endif +#ifdef CONFIG_SDIO_HCI +#include "../hci/phl_trx_def_sdio.h" +#endif + +/* Common definition from HAL*/ +#include "hal_general_def.h" +/* Exported structure/definition from HAL */ +#include "hal_def.h" +#include "hal_config.h" + +/* +Exported hal API from HAL +Prevent HAL mac/bb/ rf/ btc cross referencing +*/ +#include "hal_api_drv.h" + +#include "hal_io.h" /*exported hal_read, hal_write API from HAL */ +#include "hal_fw.h" + + +#if 1 +static inline void hal_mdelay(struct rtw_hal_com_t *h, int ms) +{ + _os_delay_ms(halcom_to_drvpriv(h), ms); +} +static inline void hal_udelay(struct rtw_hal_com_t *h, int us) +{ + _os_delay_ms(halcom_to_drvpriv(h), us); +} + +static inline void hal_msleep(struct rtw_hal_com_t *h, int ms) +{ + _os_sleep_ms(halcom_to_drvpriv(h),ms); +} + +static inline void hal_usleep(struct rtw_hal_com_t *h, int us) +{ + _os_sleep_us(halcom_to_drvpriv(h), us); +} + +#ifdef DBG_HAL_MEM_MOINTOR +static inline void *hal_mem_alloc(struct rtw_hal_com_t *h, u32 buf_sz) +{ + _os_atomic_sub(halcom_to_drvpriv(h), &(h->hal_mem), buf_sz); + return _os_mem_alloc(halcom_to_drvpriv(h), buf_sz); +} + +static inline void hal_mem_free(struct rtw_hal_com_t *h, void *buf, u32 buf_sz) +{ + _os_atomic_add_return(halcom_to_drvpriv(h), &(h->hal_mem), buf_sz); + _os_mem_free(halcom_to_drvpriv(h), buf, buf_sz); +} +#else +static inline void *hal_mem_alloc(struct rtw_hal_com_t *h, u32 buf_sz) +{ + return _os_mem_alloc(halcom_to_drvpriv(h), buf_sz); +} + +static inline void hal_mem_free(struct rtw_hal_com_t *h, void *buf, u32 buf_sz) +{ + _os_mem_free(halcom_to_drvpriv(h), buf, buf_sz); +} +#endif /*DBG_HAL_MEM_MOINTOR*/ +static inline void hal_mem_set(struct rtw_hal_com_t *h, void *buf, s8 value, u32 size) +{ + _os_mem_set(halcom_to_drvpriv(h), buf, value, size); +} + +static inline void hal_mem_cpy(struct rtw_hal_com_t *h, void *dest, + void *src, u32 size) +{ + _os_mem_cpy(halcom_to_drvpriv(h), dest, src, size); +} + +static inline int hal_mem_cmp(struct rtw_hal_com_t *h, void *dest, + void *src, u32 size) +{ + return _os_mem_cmp(halcom_to_drvpriv(h), dest, src, size); +} +static inline void hal_mutex_init(struct rtw_hal_com_t *h, _os_mutex *mutex) +{ + _os_mutex_init(halcom_to_drvpriv(h), mutex); +} +static inline void hal_mutex_deinit(struct rtw_hal_com_t *h, _os_mutex *mutex) +{ + _os_mutex_deinit(halcom_to_drvpriv(h), mutex); +} +static inline void hal_mutex_lock(struct rtw_hal_com_t *h, _os_mutex *mutex) +{ + _os_mutex_lock(halcom_to_drvpriv(h), mutex); +} +static inline void hal_mutex_unlock(struct rtw_hal_com_t *h, _os_mutex *mutex) +{ + _os_mutex_unlock(halcom_to_drvpriv(h), mutex); +} +static inline void hal_init_timer(struct rtw_hal_com_t *h, _os_timer *timer, + void (*call_back_func)(void* context), + void *context, const char *sz_id) +{ + _os_init_timer(halcom_to_drvpriv(h), timer, call_back_func, context, sz_id); +} + +static inline void hal_set_timer(struct rtw_hal_com_t *h, _os_timer *timer, + u32 ms_delay) +{ + _os_set_timer(halcom_to_drvpriv(h), timer, ms_delay); +} +static inline void hal_cancel_timer(struct rtw_hal_com_t *h, _os_timer *timer) +{ + _os_cancel_timer(halcom_to_drvpriv(h), timer); +} +static inline void hal_release_timer(struct rtw_hal_com_t *h, _os_timer *timer) +{ + _os_release_timer(halcom_to_drvpriv(h), timer); +} + +/*IO OPS*/ +#ifdef CONFIG_PCI_HCI +static inline u8 hal_pci_read8(struct rtw_hal_com_t *h,u32 addr) +{ + return _os_read8_pcie(halcom_to_drvpriv(h), addr); +} +static inline u16 hal_pci_read16(struct rtw_hal_com_t *h,u32 addr) +{ + return _os_read16_pcie(halcom_to_drvpriv(h), addr); +} +static inline u32 hal_pci_read32(struct rtw_hal_com_t *h,u32 addr) +{ + return _os_read32_pcie(halcom_to_drvpriv(h), addr); +} + +static inline int hal_pci_write8(struct rtw_hal_com_t *h, u32 addr, u8 val) +{ + return _os_write8_pcie(halcom_to_drvpriv(h), addr, val); +} +static inline int hal_pci_write16(struct rtw_hal_com_t *h, u32 addr, u16 val) +{ + return _os_write16_pcie(halcom_to_drvpriv(h), addr, val); +} +static inline int hal_pci_write32(struct rtw_hal_com_t *h, u32 addr, u32 val) +{ + return _os_write32_pcie(halcom_to_drvpriv(h), addr, val); +} + +#endif +#ifdef CONFIG_USB_HCI +static inline int hal_usb_vendor_req(struct rtw_hal_com_t *h, + u8 request, u16 value, u16 index, + void *pdata, u16 len, u8 requesttype) +{ + return _os_usbctrl_vendorreq(halcom_to_drvpriv(h), request, value, + index, pdata, len, requesttype); +} +#endif /*CONFIG_USB_HCI*/ + + +#ifdef CONFIG_SDIO_HCI +static inline u8 hal_sdio_cmd52_r8(struct rtw_hal_com_t *h, u32 offset) +{ + return _os_sdio_cmd52_r8(halcom_to_drvpriv(h), offset); +} +static inline u8 hal_sdio_cmd53_r8(struct rtw_hal_com_t *h, u32 offset) +{ + return _os_sdio_cmd53_r8(halcom_to_drvpriv(h), offset); +} + +static inline u16 hal_sdio_cmd53_r16(struct rtw_hal_com_t *h, u32 offset) +{ + return _os_sdio_cmd53_r16(halcom_to_drvpriv(h), offset); +} + +static inline u32 hal_sdio_cmd53_r32(struct rtw_hal_com_t *h, u32 offset) +{ + return _os_sdio_cmd53_r32(halcom_to_drvpriv(h), offset); +} + +static inline u8 hal_sdio_cmd53_rn(struct rtw_hal_com_t *h, + u32 offset, u32 size, u8 *data) +{ + return _os_sdio_cmd53_rn(halcom_to_drvpriv(h), offset, size, data); +} + +static inline u8 hal_sdio_cmd53_r(struct rtw_hal_com_t *h, + u32 offset, u32 size, u8 *val) +{ + size = _ALIGN(size, 4); + if (size > h->block_sz) + size = _ALIGN(size, h->block_sz); + return _os_sdio_cmd53_r(halcom_to_drvpriv(h), offset, size, val); +} + +static inline void hal_sdio_cmd52_w8(struct rtw_hal_com_t *h, + u32 offset, u8 val) +{ + _os_sdio_cmd52_w8(halcom_to_drvpriv(h), offset, val); +} + +static inline void hal_sdio_cmd53_w8(struct rtw_hal_com_t *h, + u32 offset, u8 val) +{ + _os_sdio_cmd53_w8(halcom_to_drvpriv(h), offset, val); +} + +static inline void hal_sdio_cmd53_w16(struct rtw_hal_com_t *h, + u32 offset, u16 val) +{ + _os_sdio_cmd53_w16(halcom_to_drvpriv(h), offset, val); +} + +static inline void hal_sdio_cmd53_w32(struct rtw_hal_com_t *h, + u32 offset, u32 val) +{ + _os_sdio_cmd53_w32(halcom_to_drvpriv(h), offset, val); +} + +static inline void hal_sdio_cmd53_wn(struct rtw_hal_com_t *h, + u32 offset, u32 size, u8 *val) +{ + _os_sdio_cmd53_wn(halcom_to_drvpriv(h), offset, size, val); +} + +static inline void hal_sdio_cmd53_w(struct rtw_hal_com_t *h, + u32 offset, u32 size, u8 *val) +{ + size = _ALIGN(size, 4); + if (size > h->block_sz) + size = _ALIGN(size, h->block_sz); + + _os_sdio_cmd53_w(halcom_to_drvpriv(h), offset, size, val); +} + +static inline u8 hal_sdio_f0_read(struct rtw_hal_com_t *h, + u32 addr, void *buf, u32 len) +{ + + return _os_sdio_f0_read(halcom_to_drvpriv(h), addr, buf, len); +} + +static inline u8 hal_sdio_read_cia_r8(struct rtw_hal_com_t *h, u32 addr) +{ + return _os_sdio_read_cia_r8(halcom_to_drvpriv(h), addr); +} + +#endif /*CONFIG_SDIO_HCI*/ + +#else +/*please refer to hal_pltfm_ops.h*/ +#define hal_mdelay(h, ms) _os_delay_ms(halcom_to_drvpriv(h), ms) +#define hal_udelay(h, us) _os_delay_ms(halcom_to_drvpriv(h), us) +#define hal_msleep(h, ms) _os_sleep_ms(halcom_to_drvpriv(h),ms) +#define hal_usleep(h, us) _os_sleep_us(halcom_to_drvpriv(h), us) + +#define hal_mem_alloc(h, buf_sz) _os_mem_alloc(halcom_to_drvpriv(h), buf_sz) +#define hal_mem_free(h, buf, buf_sz) _os_mem_free(halcom_to_drvpriv(h), buf, buf_sz) +#define hal_mem_set(h, buf, value, size) _os_mem_set(halcom_to_drvpriv(h), buf, value, size) +#define hal_mem_cpy(h, dest, src, size) _os_mem_cpy(halcom_to_drvpriv(h), dest, src, size) +#define hal_mem_cmp(h, dest, src, size) _os_mem_cmp(halcom_to_drvpriv(h), dest, src, size) + +#define hal_mutex_init(h, mutex) _os_mutex_init(halcom_to_drvpriv(h), mutex) +#define hal_mutex_deinit(h, hmutex) _os_mutex_deinit(halcom_to_drvpriv(h), mutex) +#define hal_mutex_lock(h, mutex) _os_mutex_lock(halcom_to_drvpriv(h), mutex) +#define hal_mutex_unlock(h, mutex) _os_mutex_unlock(halcom_to_drvpriv(h), mutex) + +#define hal_init_timer(h, timer, call_back_func, context, sz_id) \ + _os_init_timer(halcom_to_drvpriv(h), timer, call_back_func, context, sz_id) +#define hal_set_timer(h, timer, ms_delay) _os_set_timer(halcom_to_drvpriv(h), timer, ms_delay) +#define hal_cancel_timer(h, timer) _os_cancel_timer(halcom_to_drvpriv(h), timer) +#define hal_release_timer(h, timer) _os_release_timer(halcom_to_drvpriv(h), timer) + +/*IO OPS*/ +#ifdef CONFIG_PCI_HCI +#define hal_pci_read8(h, addr) _os_read8_pcie(halcom_to_drvpriv(h), addr) +#define hal_pci_read16(h, addr) _os_read16_pcie(halcom_to_drvpriv(h), addr) +#define hal_pci_read32(h, addr) _os_read32_pcie(halcom_to_drvpriv(h), addr) +#define hal_pci_write8(h, addr, val) _os_write8_pcie(halcom_to_drvpriv(h), addr, val) +#define hal_pci_write16(h, addr, val) _os_write16_pcie(halcom_to_drvpriv(h), addr, val) +#define hal_pci_write32(h, addr, val) _os_write32_pcie(halcom_to_drvpriv(h), addr, val) +#endif + +#ifdef CONFIG_USB_HCI +#define hal_usb_vendor_req(h, request, value, index, pdata, len, requesttype) \ + _os_usbctrl_vendorreq(halcom_to_drvpriv(h), request, value, index, pdata, len, requesttype) +#endif /*CONFIG_USB_HCI*/ + +#ifdef CONFIG_SDIO_HCI +#define hal_sdio_cmd52_r8(h, offset) _os_sdio_cmd52_r8(halcom_to_drvpriv(h), offset) +#define hal_sdio_cmd53_r8(h, offset) _os_sdio_cmd53_r8(halcom_to_drvpriv(h), offset) +#define hal_sdio_cmd53_r16(h, offset) _os_sdio_cmd53_r16(halcom_to_drvpriv(h), offset) +#define hal_sdio_cmd53_r32(h, offset) _os_sdio_cmd53_r32(halcom_to_drvpriv(h), offset) +#define hal_sdio_cmd53_rn(h, offset, size, data) _os_sdio_cmd53_rn(halcom_to_drvpriv(h), offset, size, data) +#define hal_sdio_cmd52_w8(h, offset, val) _os_sdio_cmd52_w8(halcom_to_drvpriv(h), offset, val) +#define hal_sdio_cmd53_w8(h, offset, val) _os_sdio_cmd53_w8(halcom_to_drvpriv(h), offset, val) +#define hal_sdio_cmd53_w16(h, offset, val) _os_sdio_cmd53_w16(halcom_to_drvpriv(h), offset, val) +#define hal_sdio_cmd53_w32(h, offset, val) _os_sdio_cmd53_w32(halcom_to_drvpriv(h), offset, val) +#define hal_sdio_f0_read(h, addr, buf, len) _os_sdio_f0_read(halcom_to_drvpriv(h), addr, buf, len) +#define hal_sdio_read_cia_r8(h, addr) _os_sdio_read_cia_r8(halcom_to_drvpriv(h), addr) +#endif /*CONFIG_SDIO_HCI*/ +#endif + + +#endif /*_HAL_HEADERS_LE_H_*/ diff --git a/phl/hal_g6/hal_init.c b/phl/hal_g6/hal_init.c new file mode 100644 index 0000000..dce811d --- /dev/null +++ b/phl/hal_g6/hal_init.c @@ -0,0 +1,1561 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_INIT_C_ +#include "hal_headers.h" + +#if defined(CONFIG_PCI_HCI) +#include "hal_pci.h" +#elif defined(CONFIG_USB_HCI) +#include "hal_usb.h" +#elif defined(CONFIG_SDIO_HCI) +#include "hal_sdio.h" +#endif + + +/******************* IO APIs *******************/ +u8 rtw_hal_read8(void *h, u32 addr) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + return hal_read8(hal_com, addr); +} +u16 rtw_hal_read16(void *h, u32 addr) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + return hal_read16(hal_com, addr); +} +u32 rtw_hal_read32(void *h, u32 addr) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + return hal_read32(hal_com, addr); +} +void rtw_hal_write8(void *h, u32 addr, u8 val) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + hal_write8(hal_com, addr, val); +} +void rtw_hal_write16(void *h, u32 addr, u16 val) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + hal_write16(hal_com, addr, val); +} +void rtw_hal_write32(void *h, u32 addr, u32 val) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + hal_write32(hal_com, addr, val); +} + +u32 rtw_hal_read_macreg(void *h, u32 offset, u32 bit_mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + return hal_ops->read_macreg(hal, offset, bit_mask); +} +void rtw_hal_write_macreg(void *h, + u32 offset, u32 bit_mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + hal_ops->write_macreg(hal, offset, bit_mask, data); +} +u32 rtw_hal_read_bbreg(void *h, u32 offset, u32 bit_mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + return hal_ops->read_bbreg(hal, offset, bit_mask); +} +void rtw_hal_write_bbreg(void *h, + u32 offset, u32 bit_mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + hal_ops->write_bbreg(hal, offset, bit_mask, data); +} + +u32 rtw_hal_read_rfreg(void *h, + enum rf_path path, u32 offset, u32 bit_mask) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + return hal_ops->read_rfreg(hal, path, offset, bit_mask); +} + +void rtw_hal_write_rfreg(void *h, + enum rf_path path, u32 offset, u32 bit_mask, u32 data) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + hal_ops->write_rfreg(hal, path, offset, bit_mask, data); +} + + +#ifdef PHL_PLATFORM_LINUX +void rtw_hal_mac_reg_dump(void *sel, void *h) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal = hal_info->hal_com; + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= MAC REG =======\n"); + + for (i = 0x0; i < 0x800; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + +#if 1 + for (i = 0x1000; i < 0xF000; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +#endif +} + +void rtw_hal_bb_reg_dump(void *sel, void *h) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal = hal_info->hal_com; + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= BB REG =======\n"); + for (i = 0x800; i < 0x1000; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + +#if 0 + for (i = 0x1800; i < 0x2000; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +#endif + +#if 0 + for (i = 0x2c00; i < 0x2c60; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x2d00; i < 0x2df0; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x4000; i < 0x4060; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x4100; i < 0x4200; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + +#endif + +} + +void rtw_hal_bb_reg_dump_ex(void *sel, void *h) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal = hal_info->hal_com; + int i; + + RTW_PRINT_SEL(sel, "======= BB REG =======\n"); + for (i = 0x800; i < 0x1000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + _RTW_PRINT_SEL(sel, "\n"); + } + +#if 0 + for (i = 0x1800; i < 0x2000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i)); + _RTW_PRINT_SEL(sel, "\n"); + } +#endif +} + + +void rtw_hal_rf_reg_dump(void *sel, void *h) +{ +#ifdef RTW_WKARD_RF_CR_DUMP + int i, j = 1, path; + struct hal_info_t *hal_info = (struct hal_info_t *)h; + struct rtw_hal_com_t *hal = hal_info->hal_com; + u32 value; + u8 path_nums; + + if (hal->rfpath_tx_num > hal->rfpath_rx_num) + path_nums = hal->rfpath_tx_num; + else + path_nums = hal->rfpath_rx_num; + + RTW_PRINT_SEL(sel, "======= RF REG =======\n"); + for (path = 0; path < path_nums; path++) { + RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path); + for (i = 0; i < 0x100; i++) { + value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff); + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%02x ", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", value); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + j = 1; + #ifdef CONFIG_RTL8852B + for (i = 0x10000; i < 0x10100; i++) { + value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff); + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%02x ", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", value); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + _RTW_PRINT_SEL(sel, "\n"); + #endif + } +#endif/*RTW_WKARD_RF_CR_DUMP*/ + +} +#endif + +/** + * rtw_hal_get_sec_cam() - get the security cam raw data from HW + * @h: struct hal_info_t * + * @num: How many cam you wnat to dump from the first one. + * @buf: ptr to buffer which store the content from HW. + * If buf is NULL, use console as debug path. + * @size Size of allocated memroy for @buf. + * The size should be @num * size of security cam offset(0x20). + * + * Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type. + */ +enum rtw_hal_status +rtw_hal_get_sec_cam(void *h, u16 num, u8 *buf, u16 size) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = rtw_hal_mac_get_sec_cam(hal_info, num, buf, size); + + return ret; +} + +/** + * rtw_hal_get_addr_cam() - get the address cam raw data from HW + * @h: struct hal_info_t * + * @num: How many cam you wnat to dump from the first one. + * @buf: ptr to buffer which store the content from HW. + * If buf is NULL, use console as debug path. + * @size Size of allocated memroy for @buf. + * The size should be @num * size of Addr cam offset(0x40). + * + * Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type. + */ +enum rtw_hal_status +rtw_hal_get_addr_cam(void *h, u16 num, u8 *buf, u16 size) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)h; + enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS; + + ret = rtw_hal_mac_get_addr_cam(hal_info, num, buf, size); + + return ret; +} + +void rtw_hal_enable_interrupt(struct rtw_phl_com_t *phl_com, void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->enable_interrupt) + hal_ops->enable_interrupt(hal); +} + +void rtw_hal_disable_interrupt(struct rtw_phl_com_t *phl_com, void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->disable_interrupt) + hal_ops->disable_interrupt(hal); +} + +void rtw_hal_config_interrupt(void *h, enum rtw_phl_config_int int_mode) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->config_interrupt) + hal_ops->config_interrupt(hal, int_mode); +} + +bool rtw_hal_recognize_interrupt(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->recognize_interrupt) + return hal_ops->recognize_interrupt(hal); + else + return false; +} + +bool rtw_hal_recognize_halt_c2h_interrupt(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->recognize_halt_c2h_interrupt) + return hal_ops->recognize_halt_c2h_interrupt(hal); + else + return false; +} + +void rtw_hal_clear_interrupt(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->clear_interrupt) + hal_ops->clear_interrupt(hal); +} + +u32 rtw_hal_interrupt_handler(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + u32 ret = 0; + + + if (hal_ops->interrupt_handler) + ret = hal_ops->interrupt_handler(hal); + else + PHL_DBG("hal_ops->interrupt_handler is NULL\n"); + + PHL_DBG("hal_ops->interrupt_handler ret=0x%x\n", ret); + + + return ret; +} + +void rtw_hal_restore_interrupt(struct rtw_phl_com_t *phl_com, void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->restore_interrupt) + hal_ops->restore_interrupt(hal); +} + +void rtw_hal_restore_rx_interrupt(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct hal_ops_t *hal_ops = hal_get_ops(hal); + + if (hal_ops->restore_rx_interrupt) + hal_ops->restore_rx_interrupt(hal); + else + PHL_DBG("hal_ops->restore_rx_interrupt is NULL\n"); +} + +static enum rtw_hal_status hal_ops_check(struct hal_info_t *hal) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_ops_t *ops = hal_get_ops(hal); + struct hal_trx_ops *trx_ops = hal_get_trx_ops(hal); + + /***hal_ops initialize section ***/ + if (!ops->init_hal_spec) { + hal_error_msg("init_hal_spec"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!ops->read_chip_version) { + hal_error_msg("read_chip_version"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!ops->hal_init) { + hal_error_msg("hal_init"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->hal_deinit) { + hal_error_msg("hal_deinit"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!ops->hal_start) { + hal_error_msg("hal_start"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->hal_stop) { + hal_error_msg("hal_stop"); + status = RTW_HAL_STATUS_FAILURE; + } +#ifdef CONFIG_WOWLAN + if (!ops->hal_wow_init) { + hal_error_msg("hal_wow_init"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->hal_wow_deinit) { + hal_error_msg("hal_wow_deinit"); + status = RTW_HAL_STATUS_FAILURE; + } +#endif /* CONFIG_WOWLAN */ + if (!ops->hal_mp_init) { + hal_error_msg("hal_mp_init"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->hal_mp_deinit) { + hal_error_msg("hal_mp_deinit"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!ops->hal_cfg_fw) { + hal_error_msg("hal_cfg_fw"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->init_default_value) { + hal_error_msg("init_default_value"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->hal_hci_configure) { + hal_error_msg("hal_hci_configure"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->read_macreg) { + hal_error_msg("read_macreg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->write_macreg) { + hal_error_msg("write_macreg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->read_bbreg) { + hal_error_msg("read_bbreg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->write_bbreg) { + hal_error_msg("write_bbreg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->read_rfreg) { + hal_error_msg("read_rfreg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->write_rfreg) { + hal_error_msg("write_rfreg"); + status = RTW_HAL_STATUS_FAILURE; + } + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) + if (!ops->enable_interrupt) { + hal_error_msg("enable_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->disable_interrupt) { + hal_error_msg("disable_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } +#ifdef CONFIG_SDIO_HCI + if (!ops->config_interrupt) { + hal_error_msg("config_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->recognize_halt_c2h_interrupt) { + hal_error_msg("recognize_halt_c2h_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } +#endif + if (!ops->recognize_interrupt) { + hal_error_msg("recognize_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->clear_interrupt) { + hal_error_msg("clear_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->interrupt_handler) { + hal_error_msg("interrupt_handler"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!ops->restore_interrupt) { + hal_error_msg("restore_interrupt"); + status = RTW_HAL_STATUS_FAILURE; + } +#endif /*defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)*/ + + + /***hal_trx_ops section ***/ + if (!trx_ops->init) { + hal_error_msg("trx init"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->deinit) { + hal_error_msg("trx deinit"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->map_hw_tx_chnl) { + hal_error_msg("trx map_hw_tx_chnl"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->get_fwcmd_queue_idx) { + hal_error_msg("trx get_fwcmd_queue_idx"); + status = RTW_HAL_STATUS_FAILURE; + } +#ifdef CONFIG_PCI_HCI + if (!trx_ops->query_tx_res) { + hal_error_msg("trx query_tx_res"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->query_rx_res) { + hal_error_msg("trx query_rx_res"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->cfg_wow_txdma) { + hal_error_msg("trx cfg_wow_txdma"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->poll_txdma_idle) { + hal_error_msg("trx poll_txdma_idle"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->qsel_to_tid) { + hal_error_msg("trx qsel_to_tid"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!trx_ops->query_txch_num) { + hal_error_msg("trx query_txch_num"); + status = RTW_HAL_STATUS_FAILURE; + } + + if (!trx_ops->query_rxch_num) { + hal_error_msg("trx query_rxch_num"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->update_wd) { + hal_error_msg("trx update_wd"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->update_txbd) { + hal_error_msg("trx update_txbd"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->tx_start) { + hal_error_msg("trx tx_start"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->check_rxrdy) { + hal_error_msg("trx check_rxrdy"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->handle_rxbd_info) { + hal_error_msg("trx handle_rxbd_info"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->handle_rx_buffer) { + hal_error_msg("trx handle_rx_buffer"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->update_rxbd) { + hal_error_msg("trx update_rxbd"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->notify_rxdone) { + hal_error_msg("trx notify_rxdone"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->handle_wp_rpt) { + hal_error_msg("trx handle_wp_rpt"); + status = RTW_HAL_STATUS_FAILURE; + } +#endif /*CONFIG_PCIE_HCI*/ + +#ifdef CONFIG_USB_HCI + if (!trx_ops->hal_fill_wd) { + hal_error_msg("trx hal_fill_wd"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->get_bulkout_id) { + hal_error_msg("trx get_bulkout_id"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->handle_rx_buffer) { + hal_error_msg("trx handle_rx_buffer"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->usb_tx_agg_cfg) { + hal_error_msg("trx usb_tx_agg_cfg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->usb_rx_agg_cfg) { + hal_error_msg("trx usb_rx_agg_cfg"); + status = RTW_HAL_STATUS_FAILURE; + } + if (!trx_ops->handle_wp_rpt) { + hal_error_msg("trx handle_wp_rpt"); + status = RTW_HAL_STATUS_FAILURE; + } +#endif + +#ifdef CONFIG_SDIO_HCI + +#endif + return status; +} +static enum rtw_hal_status hal_set_ops(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + #ifdef CONFIG_PCI_HCI + if (phl_get_hci_type(phl_com) == RTW_HCI_PCIE) + hal_set_ops_pci(phl_com, hal_info); + #endif + + #ifdef CONFIG_USB_HCI + if (phl_get_hci_type(phl_com) == RTW_HCI_USB) + hal_set_ops_usb(phl_com, hal_info); + #endif + + #ifdef CONFIG_SDIO_HCI + if (phl_get_hci_type(phl_com) == RTW_HCI_SDIO) + hal_set_ops_sdio(phl_com, hal_info); + #endif + + return hal_ops_check(hal_info); +} + +#ifdef RTW_PHL_BCN +enum rtw_hal_status hal_bcn_init(struct hal_info_t *hal_info) +{ + struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool; + + hal_info->hal_com->bcn_pool.bcn_num = 0; + INIT_LIST_HEAD(&bcn_pool->bcn_list); + _os_spinlock_init(hal_to_drvpriv(hal_info), &hal_info->hal_com->bcn_pool.bcn_lock); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status hal_bcn_deinit(struct hal_info_t *hal_info) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool; + struct rtw_bcn_entry *tmp_entry, *type = NULL; + + _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + phl_list_for_loop_safe(tmp_entry, type, + struct rtw_bcn_entry, &bcn_pool->bcn_list, list) + { + list_del(&tmp_entry->list); + _os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry)); + } + + _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status hal_alloc_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + struct rtw_bcn_entry **bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool; + struct rtw_bcn_entry *new_entry = _os_mem_alloc(drv_priv, sizeof(struct rtw_bcn_entry)); + + if(new_entry == NULL) + return RTW_HAL_STATUS_FAILURE; + + _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + list_add_tail(&new_entry->list, &bcn_pool->bcn_list); + bcn_pool->bcn_num ++; + + _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + *bcn_entry = new_entry; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status hal_free_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + u8 bcn_id) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool; + struct rtw_bcn_entry *tmp_entry, *type = NULL; + u8 is_found = 0; + + _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + phl_list_for_loop_safe(tmp_entry, type, + struct rtw_bcn_entry, &bcn_pool->bcn_list, list) + { + if(tmp_entry->bcn_cmn->bcn_id == bcn_id){ + is_found = 1; + break; + } + } + + _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + if(is_found){ + list_del(&tmp_entry->list); + _os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry)); + bcn_pool->bcn_num --; + return RTW_HAL_STATUS_SUCCESS; + } + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status hal_get_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + struct rtw_bcn_entry **bcn_entry, u8 bcn_id) +{ + void *drv_priv = hal_to_drvpriv(hal_info); + struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool; + struct rtw_bcn_entry *tmp_entry, *type = NULL; + u8 is_found = 0; + + _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + phl_list_for_loop_safe(tmp_entry, type, + struct rtw_bcn_entry, &bcn_pool->bcn_list, list) + { + if(tmp_entry->bcn_cmn->bcn_id == bcn_id){ + is_found = 1; + break; + } + } + + _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL); + + if(is_found){ + *bcn_entry = tmp_entry; + return RTW_HAL_STATUS_SUCCESS; + } + else + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status hal_update_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + struct rtw_bcn_entry *bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn) +{ + struct rtw_wifi_role_t *wrole = &phl_com->wifi_roles[bcn_cmn->role_idx]; + struct rtw_phl_stainfo_t *phl_sta = rtw_phl_get_stainfo_self(phl_com->phl_priv, wrole); + + bcn_entry->bcn_cmn = bcn_cmn; + + bcn_entry->bcn_hw.band = wrole->hw_band; + bcn_entry->bcn_hw.port = wrole->hw_port; + bcn_entry->bcn_hw.mbssid = wrole->hw_mbssid; + bcn_entry->bcn_hw.mac_id = (u8)phl_sta->macid; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_add_beacon(struct rtw_phl_com_t *phl_com, void *hal, + void *bcn_cmn) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct rtw_bcn_entry *bcn_entry = NULL; + + if(hal_alloc_bcn_entry(phl_com, hal_info, &bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + if(hal_update_bcn_entry(phl_com, hal_info, bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + if(hal_ops->cfg_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_update_beacon(struct rtw_phl_com_t *phl_com, void *hal, + u8 bcn_id) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct rtw_bcn_entry *bcn_entry = NULL; + + if(hal_get_bcn_entry(phl_com, hal_info, &bcn_entry, bcn_id) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_free_beacon(struct rtw_phl_com_t *phl_com, void *hal, + u8 bcn_id) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + if(hal_free_bcn_entry(phl_com, hal_info, bcn_id) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} +#endif + +enum rtw_hal_status rtw_hal_pkt_ofld(void *hal, u8 *id, u8 op, + u8 *pkt_buf, u16 *pkt_len) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + return hal_ops->pkt_ofld(hal, id, op, pkt_buf, pkt_len); +} + +enum rtw_hal_status rtw_hal_pkt_update_ids(void *hal, + struct pkt_ofld_entry *entry) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + return hal_ops->pkt_update_ids(hal, entry); +} + +enum rtw_hal_status rtw_hal_get_pwr_state(void *hal, enum rtw_mac_pwr_st *pwr_state) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_get_pwr_state(hal_info, pwr_state); +} + +enum rtw_hal_status rtw_hal_init(void *drv_priv, + struct rtw_phl_com_t *phl_com, void **hal, enum rtl_ic_id ic_id) +{ + struct hal_info_t *hal_info = NULL; + struct rtw_hal_com_t *hal_com = NULL; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops) = NULL; + enum rtw_chip_id chip_id = CHIP_WIFI6_MAX; + + if (ic_id == RTL8852A) + chip_id = CHIP_WIFI6_8852A; + else if(ic_id == RTL8834A) + chip_id = CHIP_WIFI6_8834A; + else if(ic_id == RTL8852B) + chip_id = CHIP_WIFI6_8852B; + else if(ic_id == RTL8852C) + chip_id = CHIP_WIFI6_8852C; + else + return RTW_HAL_STATUS_FAILURE; + + hal_info = _os_mem_alloc(drv_priv, sizeof(struct hal_info_t)); + if (hal_info == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("alloc hal_info failed\n"); + goto error_hal_mem; + } + *hal = hal_info; + + hal_com = _os_mem_alloc(drv_priv, sizeof(struct rtw_hal_com_t)); + if (hal_com == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("alloc hal_com failed\n"); + goto error_hal_com_mem; + } + + hal_info->hal_com = hal_com; + hal_com->drv_priv = drv_priv; + hal_com->hal_priv = hal_info; + hal_com->chip_id = chip_id; + hal_com->dbcc_en = false; + #ifdef DBG_HAL_MEM_MOINTOR + _os_atomic_set(drv_priv, &(hal_com->hal_mem), 0); + #endif + + /*set io_ops*/ + #ifdef CONFIG_PCI_HCI + if (phl_com->hci_type == RTW_HCI_PCIE) + set_intf_ops = hal_pci_set_io_ops; + #endif + + #ifdef CONFIG_USB_HCI + if (phl_com->hci_type == RTW_HCI_USB) + set_intf_ops = hal_usb_set_io_ops; + #endif + + #ifdef CONFIG_SDIO_HCI + if (phl_com->hci_type == RTW_HCI_SDIO) + set_intf_ops = hal_sdio_set_io_ops; + #endif + + hal_status = hal_init_io_priv(hal_info->hal_com, set_intf_ops); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("hal_init_io_priv failed\n"); + goto error_io_priv; + } + + /*set hal_ops and hal_hook_trx_ops*/ + hal_status = hal_set_ops(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("hal_set_ops failed\n"); + goto error_hal_ops; + } + + hal_status = hal_info->hal_ops.hal_init(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("hal_ops.hal_init failed\n"); + goto error_hal_init; + } + + hal_status = rtw_hal_mac_init(phl_com, hal_info); + if ((hal_status != RTW_HAL_STATUS_SUCCESS) || (hal_info->mac == NULL)) { + PHL_ERR("rtw_hal_mac_init failed\n"); + goto error_mac_init; + } + + hal_status = rtw_hal_efuse_init(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_efuse_init failed\n"); + goto error_efuse_init; + } + + hal_status = rtw_hal_bb_init(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_bb_init failed\n"); + goto error_bb_init; + } + + hal_status = rtw_hal_rf_init(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_rf_init failed\n"); + goto error_rf_init; + } + + hal_status = rtw_hal_btc_init(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("rtw_hal_btc_init failed\n"); + goto error_btc_init; + } + +#ifdef RTW_PHL_BCN + hal_status = hal_bcn_init(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("hal_bcn_init failed\n"); + goto error_bcn_init; + } +#endif + + return RTW_HAL_STATUS_SUCCESS; + +#ifdef RTW_PHL_BCN +error_bcn_init: + rtw_hal_btc_deinit(phl_com, hal_info); +#endif + +error_btc_init: + rtw_hal_rf_deinit(phl_com, hal_info); + +error_rf_init: + rtw_hal_bb_deinit(phl_com, hal_info); + +error_bb_init: + rtw_hal_efuse_deinit(phl_com, hal_info); + +error_efuse_init: + rtw_hal_mac_deinit(phl_com, hal_info); + +error_mac_init: + hal_info->hal_ops.hal_deinit(phl_com, hal_info); + +error_hal_init: +error_hal_ops: + hal_deinit_io_priv(hal_com); + +error_io_priv: + if (hal_com) { + _os_mem_free(drv_priv, hal_com, sizeof(struct rtw_hal_com_t)); + hal_com = NULL; + } + +error_hal_com_mem: + if (hal_info) { + _os_mem_free(drv_priv, hal_info, sizeof(struct hal_info_t)); + *hal = hal_info = NULL; + } + +error_hal_mem: + return hal_status; +} +struct rtw_hal_com_t *rtw_hal_get_halcom(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return hal_info->hal_com; +} + +void rtw_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + void *drv_priv = hal_to_drvpriv(hal_info); + + if(hal_info == NULL) + return; + + /* stop mechanism / disassociate hal ops */ +#ifdef RTW_PHL_BCN + hal_bcn_deinit(hal_info); +#endif + rtw_hal_btc_deinit(phl_com, hal_info); + rtw_hal_rf_deinit(phl_com, hal_info); + rtw_hal_bb_deinit(phl_com, hal_info); + rtw_hal_efuse_deinit(phl_com, hal_info); + rtw_hal_mac_deinit(phl_com, hal_info); + hal_info->hal_ops.hal_deinit(phl_com, hal_info); + hal_deinit_io_priv(hal_info->hal_com); + + #ifdef DBG_HAL_MEM_MOINTOR + PHL_INFO("[PHL-MEM] %s HAL memory :%d\n", __func__, + _os_atomic_read(hal_to_drvpriv(hal_info), &(hal_info->hal_com->hal_mem))); + #endif + + if (hal_info->hal_com) { + if(hal_info->hal_com->bf_obj) + hal_bf_deinit(hal_info); + if(hal_info->hal_com->csi_obj) + hal_csi_deinit(hal_info); + if(hal_info->hal_com->snd_obj) + hal_snd_obj_deinit(hal_info); + _os_mem_free(drv_priv, + hal_info->hal_com, sizeof(struct rtw_hal_com_t)); + hal_info->hal_com = NULL; + } + if (hal_info) { + _os_mem_free(drv_priv, + hal_info, sizeof(struct hal_info_t)); + hal_info = NULL; + } +} + +bool rtw_hal_is_inited(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return hal_info->hal_com->is_hal_init; +} + +u32 rtw_hal_hci_cfg(struct rtw_phl_com_t *phl_com, void *hal, + struct rtw_ic_info *ic_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + +#ifdef CONFIG_SDIO_HCI + hal_info->hal_com->block_sz = ic_info->sdio_info.block_sz; +#endif + hal_ops->hal_hci_configure(phl_com, hal_info, ic_info); + + return hal_status; +} + +u32 rtw_hal_read_chip_info(struct rtw_phl_com_t *phl_com, void *hal) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + hal_ops->read_chip_version(phl_com, hal_info); + + /*get mac,bb,rf capability*/ + hal_ops->init_hal_spec(phl_com, hal_info); + + return hal_status; +} + +static void _hal_reset_chandef(struct rtw_hal_com_t *hal_com) +{ + struct rtw_chan_def *chandef = NULL; + u8 bid = 0; + + for (bid = 0; bid < HW_BAND_MAX; bid++) { + chandef = &(hal_com->band[bid].cur_chandef); + chandef->bw = CHANNEL_WIDTH_MAX; + chandef->chan = 0; + chandef->offset = CHAN_OFFSET_NO_EXT; + } +} + +void rtw_hal_set_default_var(void *hal, enum rtw_hal_set_def_var_rsn rsn) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + struct hal_intr_mask_cfg intr_cfg = {0}; + + switch (rsn) { + case SET_DEF_RSN_HAL_INIT: + intr_cfg.halt_c2h_en = 1; + intr_cfg.wdt_en = 1; + hal_info->hal_com->assoc_sta_cnt = 0; + _hal_reset_chandef(hal_info->hal_com); + break; + case SET_DEF_RSN_WOW_RESUME_HNDL_RX: + intr_cfg.halt_c2h_en = 0; + intr_cfg.wdt_en = 1; + break; + case SET_DEF_RSN_WOW_RESUME_DONE: + intr_cfg.halt_c2h_en = 1; + intr_cfg.wdt_en = 1; + break; + default: + intr_cfg.halt_c2h_en = 1; + intr_cfg.wdt_en = 1; + hal_info->hal_com->assoc_sta_cnt = 0; + _hal_reset_chandef(hal_info->hal_com); + break; + } + + PHL_INFO("%s : rsn %d.\n", __func__, rsn); + hal_ops->init_default_value(hal_info, &intr_cfg); +} + +u32 rtw_hal_var_init(struct rtw_phl_com_t *phl_com, void *hal) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + hal_com->is_hal_init = false; + rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT); + + /*csi init shall after read hw chip info*/ + hal_status = hal_csi_init( + hal_info, + phl_com->hal_spec.max_csi_buf_su_nr, + phl_com->hal_spec.max_csi_buf_mu_nr); + if (hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("rtw_hal_csi_init failed\n"); + } + + /*bf init shall after read hw chip info*/ + hal_status = hal_bf_init( + hal_info, + phl_com->hal_spec.max_bf_ent_nr, + phl_com->hal_spec.max_su_sta_nr, + phl_com->hal_spec.max_mu_sta_nr); + if (hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("rtw_hal_bf_init failed\n"); + } + + hal_status = hal_snd_obj_init(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("hal_snd_obj_init failed\n"); + } + return hal_status; +} + +static int +_hal_parse_macreg(void *drv_priv, u32 *pdest_buf, u8 *psrc_buf, u32 buflen) +{ + return 0; +} + +enum rf_path _get_path_from_ant_num(u8 antnum) +{ + enum rf_path ret = RF_PATH_B; + + switch (antnum) { + default: + break; + case 1: + ret = RF_PATH_B; + break; + case 2: + ret = RF_PATH_AB; + break; + case 3: + ret = RF_PATH_ABC; + break; + } + return ret; +} + +static void _hal_send_hal_init_hub_msg(struct rtw_phl_com_t *phl_com, u8 init_ok) +{ + struct phl_msg msg = {0}; + u16 evt_id = (init_ok) ? MSG_EVT_HAL_INIT_OK : MSG_EVT_HAL_INIT_FAIL; + + msg.inbuf = NULL; + msg.inlen = 0; + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id); + msg.band_idx = HW_BAND_0; + rtw_phl_msg_hub_hal_send(phl_com, NULL, &msg); +} + +enum rtw_hal_status rtw_hal_preload(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + FUNCIN(); + + hal_status = hal_ops->hal_get_efuse(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + return hal_status; +} + +enum rtw_hal_status hal_rfe_type_chk(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_UNKNOWN_RFE_TYPE; + + if(phl_com->dev_cap.rfe_type != 0xff){ + hal_status = RTW_HAL_STATUS_SUCCESS; + } + else { + if(phl_com->dev_cap.bypass_rfe_chk == true){ + rtw_hal_rf_get_default_rfe_type(hal_info->hal_com); + rtw_hal_rf_get_default_xtal(hal_info->hal_com); + PHL_WARN("%s: Use default RFE type(0x%x) / XTAL(0x%x) configuration for empty EFUSE\n", + __FUNCTION__, + hal_info->hal_com->dev_hw_cap.rfe_type, + hal_info->hal_com->dev_hw_cap.xcap); + hal_status = RTW_HAL_STATUS_SUCCESS; + } + } + + return hal_status; +} + +enum rtw_hal_status rtw_hal_start(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); +#ifdef RTW_WKARD_DEF_CMACTBL_CFG + enum rf_path tx, rx; +#endif + hal_status = hal_rfe_type_chk(phl_com, hal_info); + if(hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_ERR("%s: Unknown RFE type!!!\n", __FUNCTION__); + return hal_status; + } + + hal_status = hal_ops->hal_start(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + hal_status = RTW_HAL_STATUS_SUCCESS; + hal_info->hal_com->is_hal_init = true; + rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT); + + rtw_hal_rf_set_power(hal_info, HW_PHY_0, PWR_BY_RATE); +#ifdef RTW_WKARD_DEF_CMACTBL_CFG + if (phl_com->phy_cap[0].txss < hal_info->hal_com->rfpath_tx_num) + hal_info->hal_com->rfpath_tx_num = phl_com->phy_cap[0].txss; + if (phl_com->phy_cap[0].rxss < hal_info->hal_com->rfpath_rx_num) + hal_info->hal_com->rfpath_rx_num = phl_com->phy_cap[0].rxss; + tx = _get_path_from_ant_num(hal_info->hal_com->rfpath_tx_num); + rx = _get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num); + rtw_hal_bb_trx_path_cfg(hal_info, tx, phl_com->phy_cap[0].txss, + rx, phl_com->phy_cap[0].rxss); +#endif +#ifdef RTW_WKARD_SINGLE_PATH_RSSI + hal_info->hal_com->cur_rx_rfpath = + _get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num); +#endif + #ifdef CONFIG_BTCOEX + rtw_hal_btc_radio_state_ntfy(hal_info, true); + #endif + + return hal_status; +} + +void rtw_hal_stop(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + do { + if (true == TEST_STATUS_FLAG(phl_com->dev_state, + RTW_DEV_SURPRISE_REMOVAL)) { + PHL_WARN("%s(): Device has removed, skip HW stop functions!\n", __func__); + break; + } + +#ifdef CONFIG_BTCOEX + rtw_hal_btc_radio_state_ntfy(hal_info, false); +#endif + hal_status = hal_ops->hal_stop(phl_com, hal_info); + hal_info->hal_com->is_hal_init = false; + } while (false); +} + +enum rtw_hal_status rtw_hal_restart(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + #ifdef CONFIG_BTCOEX + rtw_hal_btc_radio_state_ntfy(hal_info, false); + #endif + + hal_status = hal_ops->hal_stop(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + hal_status = hal_ops->hal_start(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + #ifdef CONFIG_BTCOEX + rtw_hal_btc_radio_state_ntfy(hal_info, true); + #endif + + hal_info->hal_com->is_hal_init = true; + + return hal_status; +} + +enum rtw_hal_status rtw_hal_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + hstatus = rtw_hal_mac_hal_deinit(phl_com, hal_info); + + return hstatus; +} + +enum rtw_hal_status +rtw_hal_role_cfg(void *hal, struct rtw_wifi_role_t *wrole) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + /*enable & configure mac hw-port*/ + hal_status = rtw_hal_mac_port_init(hal_info, wrole); + + /* init hal mac bfer function if wrole cap if any of bfer cap is true*/ + if (wrole->proto_role_cap.he_su_bfmr || + wrole->proto_role_cap.he_mu_bfmr || + wrole->proto_role_cap.vht_su_bfmr || + wrole->proto_role_cap.vht_mu_bfmr || + wrole->proto_role_cap.ht_su_bfmr) { + if ((PHL_RTYPE_AP == wrole->type) || + ((PHL_RTYPE_STATION == wrole->type) && + (MLME_LINKED == wrole->mstate))) { + hal_status = hal_bf_hw_mac_init_bfer(hal_info, + wrole->hw_band); + } + } + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_role_cfg_ex(void *hal, struct rtw_wifi_role_t *wrole, + enum pcfg_type type, void *param) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_port_cfg(hal_info, wrole, type, param); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_beacon_stop(void *hal, struct rtw_wifi_role_t *wrole, bool stop) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + u32 bcn_en = (stop) ? 0 : 1; + + PHL_INFO("%s wr-%d, bcn_en:%s\n", __func__, wrole->id, (bcn_en) ? "E" : "D"); + hsts = rtw_hal_mac_port_cfg(hal_info, wrole, PCFG_BCN_EN, &bcn_en); + + return hsts; +} + +enum rtw_hal_status +hal_ver_check(struct rtw_hal_com_t *hal_com) +{ + if ((hal_com->mac_vc.mac_ver < hal_com->bb_vc.mac_ver) || + (hal_com->mac_vc.mac_ver < hal_com->rf_vc.mac_ver) || + (hal_com->mac_vc.mac_ver < hal_com->btc_vc.mac_ver) || + (hal_com->mac_vc.mac_ver < hal_com->fw_vc.mac_ver)) + return RTW_HAL_STATUS_FAILURE; + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status +rtw_hal_watchdog(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_bb_watchdog(hal_info, false); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_bb_watchdog fail (%x)\n", __FUNCTION__, hal_status); + goto exit; + } + + hal_status = rtw_hal_rf_watchdog(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_rf_watchdog fail (%x)\n", __FUNCTION__, hal_status); + goto exit; + } + + hal_status = rtw_hal_mac_watchdog(hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s rtw_hal_mac_watchdog fail (%x)\n", __FUNCTION__, hal_status); + goto exit; + } + +exit: + return hal_status; +} + +enum rtw_hal_status +rtw_hal_simple_watchdog(void *hal, u8 io_en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_bb_simple_watchdog(hal_info, io_en); + if(hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_INFO("%s fail (%x)\n", + __FUNCTION__, hal_status); + goto exit; + } + +exit: + return hal_status; +} + + +enum rtw_hal_status +rtw_hal_cfg_trx_path(void *hal, enum rf_path tx, u8 tx_nss, + enum rf_path rx, u8 rx_nss) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if (tx < RF_PATH_AB) { + /* forced tx nss = 1*/ + tx_nss = 1; + } + if (rx < RF_PATH_AB) { + /* forced rx nss = 1*/ + rx_nss = 1; + } + + hal_status = rtw_hal_bb_trx_path_cfg( + hal_info, + tx, + ((tx_nss > hal_info->hal_com->rfpath_tx_num) ? + hal_info->hal_com->rfpath_tx_num : tx_nss), + rx, + ((rx_nss > hal_info->hal_com->rfpath_rx_num) ? + hal_info->hal_com->rfpath_rx_num : rx_nss)); +#ifdef RTW_WKARD_SINGLE_PATH_RSSI + hal_info->hal_com->cur_rx_rfpath = rx; +#endif + + return hal_status; +} + +enum rtw_hal_status rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t *phl_com, void *hal, enum rtw_gpio_mode mode, u8 gpio) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_set_sw_gpio_mode(hal_info, mode, gpio); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t *phl_com, void *hal, u8 high, u8 gpio) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_sw_gpio_ctrl(hal_info, high, gpio); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status); + + return hal_status; +} + +void rtw_hal_dbg_status_dump(void *hal, struct hal_mac_dbg_dump_cfg *cfg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + rtw_hal_mac_dbg_status_dump(hal_info, cfg); +} + diff --git a/phl/hal_g6/hal_io.c b/phl/hal_g6/hal_io.c new file mode 100644 index 0000000..544e333 --- /dev/null +++ b/phl/hal_g6/hal_io.c @@ -0,0 +1,799 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* +The purpose of hal_io.c + +a. provides the API +b. provides the protocol engine +c. provides the software interface between caller and the hardware interface + +Compiler Flag Option: +1. CONFIG_SDIO_HCI: + a. USE_SYNC_IRP: Only sync operations are provided. + b. USE_ASYNC_IRP:Both sync/async operations are provided. + +2. CONFIG_USB_HCI: + a. USE_ASYNC_IRP: Both sync/async operations are provided. + +3. CONFIG_CFIO_HCI: + b. USE_SYNC_IRP: Only sync operations are provided. + +Only sync read/rtw_write_mem operations are provided. +*/ + +#define _HAL_IO_C_ +#include "hal_headers.h" + +u8 _hal_read8(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 r_val; + struct hal_io_priv *io_priv = &hal->iopriv; + u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr); + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) { + r_val = 0xEA; + return r_val; + } + #endif + + _read8 = io_priv->io_ops._read8; + r_val = _read8(hal, addr); + return r_val; +} + +u16 _hal_read16(struct rtw_hal_com_t *hal, u32 addr) +{ + u16 r_val; + struct hal_io_priv *io_priv = &hal->iopriv; + u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr); + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) { + r_val = 0xEAEA; + return r_val; + } + #endif + + _read16 = io_priv->io_ops._read16; + r_val = _read16(hal, addr); + return r_val; +} + +u32 _hal_read32(struct rtw_hal_com_t *hal, u32 addr) +{ + u32 r_val; + struct hal_io_priv *io_priv = &hal->iopriv; + u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr); + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) { + r_val = 0xEAEAEAEA; + return r_val; + } + #endif + + _read32 = io_priv->io_ops._read32; + r_val = _read32(hal, addr); + return r_val; +} + +int _hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); + #ifdef RTW_WKARD_BUS_WRITE + int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, + u32 value) = NULL; + #endif + int ret; + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) + return 0; + #endif + + _write8 = io_priv->io_ops._write8; + ret = _write8(hal, addr, val); + + #ifdef RTW_WKARD_BUS_WRITE + _write_post_cfg = io_priv->io_ops._write_post_cfg; + if(NULL != _write_post_cfg) { + ret = _write_post_cfg(hal, addr, val); + } + #endif + return ret; +} +int _hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); + #ifdef RTW_WKARD_BUS_WRITE + int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, + u32 value) = NULL; + #endif + int ret; + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) + return 0; + #endif + + _write16 = io_priv->io_ops._write16; + ret = _write16(hal, addr, val); + + #ifdef RTW_WKARD_BUS_WRITE + _write_post_cfg = io_priv->io_ops._write_post_cfg; + if(NULL != _write_post_cfg) { + ret = _write_post_cfg(hal, addr, val); + } + #endif + return ret; +} +int _hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); + #ifdef RTW_WKARD_BUS_WRITE + int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, + u32 value) = NULL; + #endif + int ret; + + #ifdef DBG_PHL_MAC_REG_RW + if (rtw_hal_mac_reg_chk(hal, addr) == false) + return 0; + #endif + + _write32 = io_priv->io_ops._write32; + ret = _write32(hal, addr, val); + + #ifdef RTW_WKARD_BUS_WRITE + _write_post_cfg = io_priv->io_ops._write_post_cfg; + if(NULL != _write_post_cfg) { + ret = _write_post_cfg(hal, addr, val); + } + #endif + return ret; +} + +#ifdef CONFIG_SDIO_HCI +u8 _hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 r_val = 0x00; + struct hal_io_priv *io_priv = &hal->iopriv; + u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr); + + _sd_f0_read8 = io_priv->io_ops._sd_f0_read8; + + if (_sd_f0_read8) + r_val = _sd_f0_read8(hal, addr); + + return r_val; +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 _hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 r_val = 0x00; + struct hal_io_priv *io_priv = &hal->iopriv; + u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr); + + _sd_iread8 = io_priv->io_ops._sd_iread8; + + if (_sd_iread8) + r_val = _sd_iread8(hal, addr); + return r_val; +} + +u16 _hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr) +{ + u16 r_val = 0x00; + struct hal_io_priv *io_priv = &hal->iopriv; + u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr); + + _sd_iread16 = io_priv->io_ops._sd_iread16; + + if (_sd_iread16) + r_val = _sd_iread16(hal, addr); + return r_val; +} + +u32 _hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr) +{ + u32 r_val = 0x00; + struct hal_io_priv *io_priv = &hal->iopriv; + u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr); + + _sd_iread32 = io_priv->io_ops._sd_iread32; + + if (_sd_iread32) + r_val = _sd_iread32(hal, addr); + return r_val; +} + +int _hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); + int ret = -1; + + _sd_iwrite8 = io_priv->io_ops._sd_iwrite8; + + if (_sd_iwrite8) + ret = _sd_iwrite8(hal, addr, val); + + return ret; +} + +int _hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); + int ret = -1; + + _sd_iwrite16 = io_priv->io_ops._sd_iwrite16; + + if (_sd_iwrite16) + ret = _sd_iwrite16(hal, addr, val); + return ret; +} +int _hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val) +{ + struct hal_io_priv *io_priv = &hal->iopriv; + int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); + int ret = -1; + + _sd_iwrite32 = io_priv->io_ops._sd_iwrite32; + + if (_sd_iwrite32) + ret = _sd_iwrite32(hal, addr, val); + + return ret; +} +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +u32 hal_init_io_priv(struct rtw_hal_com_t *hal, + void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops)) +{ + struct hal_io_priv *iopriv = &hal->iopriv; + + if (set_intf_ops == NULL) + return RTW_HAL_STATUS_IO_INIT_FAILURE; + + #ifdef CONFIG_SDIO_INDIRECT_ACCESS + _os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex); + #endif + set_intf_ops(hal, &iopriv->io_ops); + + return RTW_HAL_STATUS_SUCCESS; +} +u32 hal_deinit_io_priv(struct rtw_hal_com_t *hal) +{ + #ifdef CONFIG_SDIO_INDIRECT_ACCESS + struct hal_io_priv *iopriv = &hal->iopriv; + + _os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex); + #endif + + return RTW_HAL_STATUS_SUCCESS; +} + +/*******************common IO APIs *******************/ +static inline u32 _bit_shift(u32 mask) +{ + u32 i; + + for (i = 0; i <= 31; i++) + if (mask & BIT(i)) + break; + + return i; +} + +u32 hal_read_macreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask) +{ + u32 val = 0, val32, shift; + + val32 = hal_read32(hal->hal_com, offset); + if (bit_mask != 0xFFFFFFFF) { + shift = _bit_shift(bit_mask); + val = (val32 & bit_mask) >> shift; + return val; + } + else { + return val32; + } +} +void hal_write_macreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data) +{ + u32 val32, shift; + + if (bit_mask != 0xFFFFFFFF) { + val32 = hal_read32(hal->hal_com, offset); + shift = _bit_shift(bit_mask); + data = ((val32 & (~bit_mask)) | ((data << shift) & bit_mask)); + } + + hal_write32(hal->hal_com, offset, data); +} + +u32 hal_read_bbreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask) +{ + u32 val32 = 0; + val32 = rtw_hal_read_bb_reg(hal->hal_com, offset, bit_mask); + + return val32; +} + +void hal_write_bbreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data) +{ + rtw_hal_write_bb_reg(hal->hal_com, offset, bit_mask, data); +} + +u32 hal_read_rfreg(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask) +{ + u32 val32 = 0; + val32 = rtw_hal_read_rf_reg(hal->hal_com, path, offset, bit_mask); +#ifdef DBG_IO + if (match_rf_read_sniff_ranges(hal->hal_com, path, offset, bit_mask)) { + PHL_INFO("DBG_IO hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n" + , path, offset, bit_mask, (val32 << _bit_shift(bit_mask)), val32); + } +#endif + + return val32; +} +void hal_write_rfreg(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask, u32 data) +{ + rtw_hal_write_rf_reg(hal->hal_com, path, offset, bit_mask, data); +#ifdef DBG_IO + if (match_rf_write_sniff_ranges(hal->hal_com, path, offset, bit_mask)) { + PHL_INFO("DBG_IO hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n" + , path, offset, bit_mask, (data << _bit_shift(bit_mask)), data); + } +#endif +} + +static u32 _cal_bit_shift(u32 bit_mask) +{ + u32 i; + + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 1) + break; + } + + return (i); +} + +void hal_write32_mask(struct rtw_hal_com_t *hal, u16 addr, u32 mask, u32 val) +{ + u32 original_value, new_value; + u32 bit_shift; + + if (mask == 0xFFFFFFFF) { + hal_write32(hal, addr, val); + } else { + original_value = hal_read32(hal, addr); + bit_shift = _cal_bit_shift(mask); + new_value = (((original_value) & (~mask)) | ((val << bit_shift) & mask)); + hal_write32(hal, addr, new_value); + } +} + + +#ifdef DBG_IO +#define RTW_IO_SNIFF_TYPE_RANGE 0 /* specific address range is accessed */ +#define RTW_IO_SNIFF_TYPE_VALUE 1 /* value match for sniffed range */ + +struct rtw_io_sniff_ent { + u8 chip; + u8 hci; + u32 addr; + u8 type; + union { + u32 end_addr; + struct { + u32 mask; + u32 val; + bool equal; + } vm; /* value match */ + } u; + bool trace; + char *tag; +}; + +#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,} + +#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} + +/* part or all sniffed range is enabled (not all 0) */ +#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} + +/* part or all sniffed range is disabled (not all 1) */ +#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,} + +const struct rtw_io_sniff_ent read_sniff[] = { +#ifdef DBG_IO_HCI_EN_CHK + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"), + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"), + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"), +#endif +#ifdef DBG_IO_SNIFF_EXAMPLE + RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "read TXPAUSE"), + RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"), +#endif +}; + +const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent); + +const struct rtw_io_sniff_ent write_sniff[] = { +#ifdef DBG_IO_HCI_EN_CHK + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"), + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"), + RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"), +#endif +#ifdef DBG_IO_SNIFF_EXAMPLE + RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "write TXPAUSE"), + RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"), +#endif +}; + +const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent); + +static bool match_io_sniff_ranges(struct rtw_hal_com_t *hal + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len) +{ + + /* check if IO range after sniff end address */ + if (addr > sniff->u.end_addr) + return 0; + + return 1; +} + +static bool match_io_sniff_value(struct rtw_hal_com_t *hal + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) +{ + u8 sniff_len; + s8 mask_shift; + u32 mask; + s8 value_shift; + u32 value; + bool ret = 0; + + /* check if IO range after sniff end address */ + sniff_len = 4; + while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) { + sniff_len--; + if (sniff_len == 0) + goto exit; + } + if (sniff->addr + sniff_len <= addr) + goto exit; + + /* align to IO addr */ + mask_shift = (sniff->addr - addr) * 8; + value_shift = mask_shift + bitshift(sniff->u.vm.mask); + if (mask_shift > 0) + mask = sniff->u.vm.mask << mask_shift; + else if (mask_shift < 0) + mask = sniff->u.vm.mask >> -mask_shift; + else + mask = sniff->u.vm.mask; + + if (value_shift > 0) + value = sniff->u.vm.val << value_shift; + else if (mask_shift < 0) + value = sniff->u.vm.val >> -value_shift; + else + value = sniff->u.vm.val; + + if ((sniff->u.vm.equal && (mask & val) == (mask & value)) + || (!sniff->u.vm.equal && (mask & val) != (mask & value)) + ) { + ret = 1; + if (0) + PHL_INFO(" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n" + , addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal); + } + +exit: + return ret; +} + +static bool match_io_sniff(struct rtw_hal_com_t *hal + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) +{ + bool ret = 0; + + if (sniff->chip != CHIP_WIFI6_MAX + && sniff->chip != hal_get_chip_id(hal)) + goto exit; + /* + if (sniff->hci + && !(sniff->hci & hal_get_hci_type(hal))) + goto exit; + */ + if (sniff->addr >= addr + len) /* IO range below sniff start address */ + goto exit; + + switch (sniff->type) { + case RTW_IO_SNIFF_TYPE_RANGE: + ret = match_io_sniff_ranges(hal, sniff, i, addr, len); + break; + case RTW_IO_SNIFF_TYPE_VALUE: + if (len == 1 || len == 2 || len == 4) + ret = match_io_sniff_value(hal, sniff, i, addr, len, val); + break; + default: + /*_os_warn_on(1);*/ + break; + } + +exit: + return ret; +} + +u32 match_read_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val) +{ + int i; + bool trace = 0; + u32 match = 0; + + for (i = 0; i < read_sniff_num; i++) { + if (match_io_sniff(hal, &read_sniff[i], i, addr, len, val)) { + match++; + trace |= read_sniff[i].trace; + if (read_sniff[i].tag) + PHL_INFO("DBG_IO TAG %s\n", read_sniff[i].tag); + } + } + + /*_os_warn_on(trace);*/ + + return match; +} + +u32 match_write_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val) +{ + int i; + bool trace = 0; + u32 match = 0; + + for (i = 0; i < write_sniff_num; i++) { + if (match_io_sniff(hal, &write_sniff[i], i, addr, len, val)) { + match++; + trace |= write_sniff[i].trace; + if (write_sniff[i].tag) + PHL_INFO("DBG_IO TAG %s\n", write_sniff[i].tag); + } + } + + /*_os_warn_on(trace);*/ + + return match; +} + +struct rf_sniff_ent { + u8 path; + u16 reg; + u32 mask; +}; + +struct rf_sniff_ent rf_read_sniff_ranges[] = { + /* example for all path addr 0x55 with all RF Reg mask */ + /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ +}; + +struct rf_sniff_ent rf_write_sniff_ranges[] = { + /* example for all path addr 0x55 with all RF Reg mask */ + /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ +}; + +int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent); +int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent); + +bool match_rf_read_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask) +{ + int i; + + for (i = 0; i < rf_read_sniff_num; i++) { + if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || + rf_read_sniff_ranges[i].path == path) + if ((addr == rf_read_sniff_ranges[i].reg) && + (mask & rf_read_sniff_ranges[i].mask)) + return true; + } + + return false; +} + +bool match_rf_write_sniff_ranges(struct rtw_hal_com_t *hal, + u8 path, u32 addr, u32 mask) +{ + int i; + + for (i = 0; i < rf_write_sniff_num; i++) { + if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || + rf_write_sniff_ranges[i].path == path) + if ((addr == rf_write_sniff_ranges[i].reg) && + (mask & rf_write_sniff_ranges[i].mask)) + return true; + } + + return false; +} + +u8 dbg_hal_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u8 val = _hal_read8(hal, addr); + + if (match_read_sniff(hal, addr, 1, val)) { + PHL_INFO("DBG_IO %s:%d hal_read8(0x%04x) return 0x%02x\n" + , caller, line, addr, val); + } + + return val; +} + +u16 dbg_hal_read16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u16 val = _hal_read16(hal, addr); + + if (match_read_sniff(hal, addr, 2, val)) { + PHL_INFO("DBG_IO %s:%d hal_read16(0x%04x) return 0x%04x\n" + , caller, line, addr, val); + } + + return val; +} + +u32 dbg_hal_read32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u32 val = _hal_read32(hal, addr); + + if (match_read_sniff(hal, addr, 4, val)) { + PHL_INFO("DBG_IO %s:%d hal_read32(0x%04x) return 0x%08x\n" + , caller, line, addr, val); + } + + return val; +} + +int dbg_hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 1, val)) { + PHL_INFO("DBG_IO %s:%d hal_write8(0x%04x, 0x%02x)\n" + , caller, line, addr, val); + } + + return _hal_write8(hal, addr, val); +} +int dbg_hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 2, val)) { + PHL_INFO("DBG_IO %s:%d hal_write16(0x%04x, 0x%04x)\n" + , caller, line, addr, val); + } + + return _hal_write16(hal, addr, val); +} +int dbg_hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 4, val)) { + PHL_INFO("DBG_IO %s:%d hal_write32(0x%04x, 0x%08x)\n" + , caller, line, addr, val); + } + + return _hal_write32(hal, addr, val); +} + +#ifdef CONFIG_SDIO_HCI +u8 dbg_hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u8 val = _hal_sd_f0_read8(hal, addr); + +#if 0 + if (match_read_sniff(adapter, addr, 1, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_f0_read8(0x%04x) return 0x%02x\n" + , caller, line, addr, val); + } +#endif + + return val; +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 dbg_hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u8 val = hal_sd_iread8(hal, addr); + + if (match_read_sniff(hal, addr, 1, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iread8(0x%04x) return 0x%02x\n" + , caller, line, addr, val); + } + + return val; +} + +u16 dbg_hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u16 val = _hal_sd_iread16(hal, addr); + + if (match_read_sniff(hal, addr, 2, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iread16(0x%04x) return 0x%04x\n" + , caller, line, addr, val); + } + + return val; +} + +u32 dbg_hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line) +{ + u32 val = _hal_sd_iread32(hal, addr); + + if (match_read_sniff(hal, addr, 4, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iread32(0x%04x) return 0x%08x\n" + , caller, line, addr, val); + } + + return val; +} + +int dbg_hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 1, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iwrite8(0x%04x, 0x%02x)\n" + , caller, line, addr, val); + } + + return _hal_sd_iwrite8(hal, addr, val); +} +int dbg_hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 2, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iwrite16(0x%04x, 0x%04x)\n" + , caller, line, addr, val); + } + + return _hal_sd_iwrite16(hal, addr, val); +} +int dbg_hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line) +{ + if (match_write_sniff(hal, addr, 4, val)) { + PHL_INFO("DBG_IO %s:%d hal_sd_iwrite32(0x%04x, 0x%08x)\n" + , caller, line, addr, val); + } + + return _hal_sd_iwrite32(hal, addr, val); +} + +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ + +#endif /* CONFIG_SDIO_HCI */ +#endif diff --git a/phl/hal_g6/hal_io.h b/phl/hal_g6/hal_io.h new file mode 100644 index 0000000..e0f5533 --- /dev/null +++ b/phl/hal_g6/hal_io.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_IO_H_ +#define _HAL_IO_H_ + +/* +Below is the data structure used by _io_handler +*/ + +extern u8 _hal_read8(struct rtw_hal_com_t *hal, u32 addr); +extern u16 _hal_read16(struct rtw_hal_com_t *hal, u32 addr); +extern u32 _hal_read32(struct rtw_hal_com_t *hal, u32 addr); +extern void _hal_read_mem(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem); + +extern int _hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val); +extern int _hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val); +extern int _hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val); + + +#ifdef CONFIG_SDIO_HCI +u8 _hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 _hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr); +u16 _hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr); +u32 _hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr); +int _hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val); +int _hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val); +int _hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + + +#ifdef DBG_IO +u32 match_read_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val); +u32 match_write_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val); +bool match_rf_read_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask); +bool match_rf_write_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask); + +extern u8 dbg_hal_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +extern u16 dbg_hal_read16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +extern u32 dbg_hal_read32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); + +extern int dbg_hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line); +extern int dbg_hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line); +extern int dbg_hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line); +extern int dbg_hal_writeN(struct rtw_hal_com_t *hal, u32 addr , u32 length , u8 *data, const char *caller, const int line); + +#ifdef CONFIG_SDIO_HCI +u8 dbg_hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 dbg_hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +u16 dbg_hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +u32 dbg_hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line); +int dbg_hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line); +int dbg_hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line); +int dbg_hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#define hal_read8(hal, addr) dbg_hal_read8((hal), (addr), __FUNCTION__, __LINE__) +#define hal_read16(hal, addr) dbg_hal_read16((hal), (addr), __FUNCTION__, __LINE__) +#define hal_read32(hal, addr) dbg_hal_read32((hal), (addr), __FUNCTION__, __LINE__) + +#define hal_write8(hal, addr, val) dbg_hal_write8((hal), (addr), (val), __FUNCTION__, __LINE__) +#define hal_write16(hal, addr, val) dbg_hal_write16((hal), (addr), (val), __FUNCTION__, __LINE__) +#define hal_write32(hal, addr, val) dbg_hal_write32((hal), (addr), (val), __FUNCTION__, __LINE__) + + +#ifdef CONFIG_SDIO_HCI +#define hal_sd_f0_read8(hal, addr) dbg_hal_sd_f0_read8((hal), (addr), __func__, __LINE__) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define hal_sd_iread8(hal, addr) dbg_hal_sd_iread8((hal), (addr), __func__, __LINE__) +#define hal_sd_iread16(hal, addr) dbg_hal_sd_iread16((hal), (addr), __func__, __LINE__) +#define hal_sd_iread32(hal, addr) dbg_hal_sd_iread32((hal), (addr), __func__, __LINE__) +#define hal_sd_iwrite8(hal, addr, val) dbg_hal_sd_iwrite8((hal), (addr), (val), __func__, __LINE__) +#define hal_sd_iwrite16(hal, addr, val) dbg_hal_sd_iwrite16((hal), (addr), (val), __func__, __LINE__) +#define hal_sd_iwrite32(hal, addr, val) dbg_hal_sd_iwrite32((hal), (addr), (val), __func__, __LINE__) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#else /* DBG_IO */ +#define hal_read8(hal, addr) _hal_read8((hal), (addr)) +#define hal_read16(hal, addr) _hal_read16((hal), (addr)) +#define hal_read32(hal, addr) _hal_read32((hal), (addr)) + +#define hal_write8(hal, addr, val) _hal_write8((hal), (addr), (val)) +#define hal_write16(hal, addr, val) _hal_write16((hal), (addr), (val)) +#define hal_write32(hal, addr, val) _hal_write32((hal), (addr), (val)) + + +#ifdef CONFIG_SDIO_HCI +#define hal_sd_f0_read8(hal, addr) _hal_sd_f0_read8((hal), (addr)) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define hal_sd_iread8(hal, addr) _hal_sd_iread8((hal), (addr)) +#define hal_sd_iread16(hal, addr) _hal_sd_iread16((hal), (addr)) +#define hal_sd_iread32(hal, addr) _hal_sd_iread32((hal), (addr)) +#define hal_sd_iwrite8(hal, addr, val) _hal_sd_iwrite8((hal), (addr), (val)) +#define hal_sd_iwrite16(hal, addr, val) _hal_sd_iwrite16((hal), (addr), (val)) +#define hal_sd_iwrite32(hal, addr, val) _hal_sd_iwrite32((hal), (addr), (val)) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#endif /* DBG_IO */ + +void hal_write32_mask(struct rtw_hal_com_t *hal, u16 addr, u32 mask, u32 val); + +u32 hal_init_io_priv(struct rtw_hal_com_t *hal, +void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops)); +u32 hal_deinit_io_priv(struct rtw_hal_com_t *hal); + +#endif /* _RTW_IO_H_ */ diff --git a/phl/hal_g6/hal_ld_file.c b/phl/hal_g6/hal_ld_file.c new file mode 100644 index 0000000..315d0a7 --- /dev/null +++ b/phl/hal_g6/hal_ld_file.c @@ -0,0 +1,2055 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_LD_FILE_C_ +#include "hal_headers.h" +#include "hal_ld_file.h" + +static int +_hal_parse_phyreg(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ + struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char *sz_line, *ptmp; + u32 dest_buf_idx = 0; + u32 u4bregoffset, u4bregvalue, u4bmove; + + ptmp = (char *)psrc_buf; + + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) { + if (!hal_is_comment_string(sz_line)) { + /* Get 1st hex value as register offset. */ + if (hal_get_hexvalue_fromstring(sz_line, &u4bregoffset, &u4bmove)) { + + pdest_buf[dest_buf_idx] = u4bregoffset; + dest_buf_idx++; + + if (u4bregoffset == 0xffff) { + /* Ending. */ + pdest_buf[dest_buf_idx] = 0xffff; + PHL_INFO(" dest_buf_len: %d \n", dest_buf_idx); + break; + } + /* Get 2nd hex value as register value. */ + sz_line += u4bmove; + if (hal_get_hexvalue_fromstring(sz_line, &u4bregvalue, &u4bmove)) { + /* PHL_INFO("[BB-ADDR]%03lX=%08lX\n", u4bregoffset, u4bregvalue); */ + pdest_buf[dest_buf_idx] = u4bregvalue; + dest_buf_idx++; + } + } + } + } +#if 0 + { /*debug dump buf*/ + u32 i = 0; + for (i = 0; i <= dest_buf_idx; i+=2) + PHL_INFO("[BB-ADDR] 0x%x :[0x%x]\n", pdest_buf[i], pdest_buf[i+1]); + } +#endif + return dest_buf_idx; +} + +static u32 phypg_combvalue_fromstring( char *sz_line) +{ + u32 u4bmove; + u32 combvalue = 0; + u8 integer = 0, fraction = 0; + u8 txgi_pdbm = 4; + + if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove)) + sz_line += u4bmove; + else + goto exit; + + combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100)); + + if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove)) + sz_line += u4bmove; + else + goto exit; + + combvalue <<= 8; + combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100)); + + if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove)) + sz_line += u4bmove; + else + goto exit; + + combvalue <<= 8; + combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100)); + + if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove)) + sz_line += u4bmove; + else + goto exit; + + combvalue <<= 8; + combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100)); + + /*PHL_DBG("[combvalue 4] 0x%x , hex = %x\n", combvalue , integer);*/ +exit: + return combvalue; +} + +static int +_hal_parse_txpwr_by_rate(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ + struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char *sz_line, *ptmp; + u8 band = 0; + u8 phy_reg_pg_version = 0; + u8 phy_reg_pg_value_type = 0; + u32 pwrhexval = 0; + u32 line_idx = 0; + u32 buf_idx = 0; + bool firstline = true; + + ptmp = (char*)psrc_buf; + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) { + if (hal_is_allspace_tab(sz_line, sizeof(*sz_line))) + continue; + + if (!hal_is_comment_string(sz_line)) { + if (firstline) { + if (_os_strncmp(sz_line, "#[v2]", 5) == 0 + || _os_strncmp(sz_line, "#[v3]", 5) == 0) { + phy_reg_pg_version = sz_line[3] - '0'; /* store pg version*/ + PHL_INFO("phy_reg_pg_version %d\n", phy_reg_pg_version); + } else { + PHL_ERR("The format in PHY_REG_PG are invalid %s\n", sz_line); + goto exit; + } + if (_os_strncmp(sz_line + 5, "[Exact]#", 8) == 0) { + phy_reg_pg_value_type = 1; /* store PHY_REG_PG_EXACT_VALUE*/ + firstline = false; + PHL_INFO("REG_PG_EXACT_VALUE\n"); + continue; + } else { + PHL_ERR("The values in PHY_REG_PG are invalid %s\n", sz_line); + goto exit; + } + } + if (_os_strncmp(sz_line , "#[2.4G]#", 8) == 0) { + band = 0; + continue; + } + if (_os_strncmp(sz_line , "#[5G]#", 6) == 0) { + band = 1; + continue; + } + if ((_os_strncmp(sz_line , "#[START]#", 9) == 0) || (_os_strncmp(sz_line , "#[END]#", 9) == 0) ) { + continue; + } + if (_os_strncmp(sz_line , "[Nss1]", 6) == 0) { + line_idx = 0; + pwrhexval = 0; + + pdest_buf[buf_idx++] = band; + pdest_buf[buf_idx++] = PHYPG_RF1Tx; + line_idx += 6; + PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx); + + while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\0' || sz_line[line_idx] == '\t') + ++line_idx; + + sz_line += line_idx; + if (_os_strncmp(sz_line , "11M_1M", 6) == 0) { + pdest_buf[buf_idx++] = CCK_11M_1M; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "18M_6M", 6) == 0) { + pdest_buf[buf_idx++] = OFDM_18M_6M; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "54M_24M", 7) == 0) { + pdest_buf[buf_idx++] = OFDM_54M_24M; + sz_line += 7; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "MCS3_0", 6) == 0) { + pdest_buf[buf_idx++] = HE1SS_MCS3_0; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "MCS7_4", 6) == 0) { + pdest_buf[buf_idx++] = HE1SS_MCS7_4; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "MCS11_8", 6) == 0) { + pdest_buf[buf_idx++] = HE1SS_MCS11_8; + sz_line += 7; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "DCM4_0", 6) == 0) { + pdest_buf[buf_idx++] = HE1SS_DCM4_0; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } + } else if (_os_strncmp(sz_line , "[Nss2]", 6) == 0) { + line_idx = 0; + pwrhexval = 0; + + pdest_buf[buf_idx++] = band; + pdest_buf[buf_idx++] = PHYPG_RF2Tx; + PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx); + + line_idx += 6; + while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\0' || sz_line[line_idx] == '\t') + ++line_idx; + + sz_line += line_idx; + if (_os_strncmp(sz_line , "MCS3_0", 6) == 0) { + pdest_buf[buf_idx++] = HE2SS_MCS3_0; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "MCS7_4", 6) == 0) { + pdest_buf[buf_idx++] = HE2SS_MCS7_4; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "MCS11_8", 6) == 0) { + pdest_buf[buf_idx++] = HE2SS_MCS11_8; + sz_line += 7; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } else if (_os_strncmp(sz_line , "DCM4_0", 6) == 0) { + pdest_buf[buf_idx++] = HE2SS_DCM4_0; + sz_line += 6; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } + } else if (_os_strncmp(sz_line , "[Offset]", 8) == 0) { + line_idx = 0; + pwrhexval = 0; + + pdest_buf[buf_idx++] = band; + pdest_buf[buf_idx++] = PHYPG_OFFSET; + PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx); + + line_idx += 8; + while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\t' || sz_line[line_idx] == '\0') + ++line_idx; + + sz_line += line_idx; + if (band == 0) { + if (_os_strncmp(sz_line , "AllRate1", 8) == 0) { + pdest_buf[buf_idx++] = Legacy_AllRate; + sz_line += 8; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } + else if (_os_strncmp(sz_line , "AllRate2", 8) == 0) { + pdest_buf[buf_idx++] = HE_AllRate; + sz_line += 8; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } + } + if (band == 1) { + if (_os_strncmp(sz_line , "AllRate1", 8) == 0) { + pdest_buf[buf_idx++] = Legacy_AllRate; /* 5G band all rate only OFDM upper */ + sz_line += 8; + PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx); + pwrhexval = phypg_combvalue_fromstring(sz_line); + PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval); + pdest_buf[buf_idx++] = pwrhexval; + } + } + } + } + } + return buf_idx; +exit: +#if 0 /*dbg dump*/ + { + u32 i = 0 ; + char *strbuf , *pextra; + strbuf = _os_mem_alloc(drv_priv, buf_idx * sizeof(u32)); + pextra = strbuf; + + sprintf(strbuf, "\n"); + pextra = strbuf + _os_strlen(strbuf); + for (i = 0; i <= buf_idx; i ++) { + pextra += sprintf(pextra, " %x \t", pdest_buf[i]); + if ( ((i+1)%4 == 0) && (i != 0)) + pextra += sprintf(pextra, "\n"); + } + printk( "%s \n" , strbuf); + _os_mem_free(drv_priv, strbuf, buf_idx * sizeof(u32)); + } +#endif + return 0; +} + +static int +_hal_parse_radio(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ + struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char *sz_line, *ptmp; + u32 dest_buf_idx = 0; + u32 u4bregoffset, u4bregvalue, u4bmove; + + ptmp = (char *)psrc_buf; + + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) { + if (!hal_is_comment_string(sz_line)) { + /* Get 1st hex value as register offset. */ + if (hal_get_hexvalue_fromstring(sz_line, &u4bregoffset, &u4bmove)) { + + pdest_buf[dest_buf_idx] = u4bregoffset; + dest_buf_idx++; + + if (u4bregoffset == 0xffff) { + /* Ending. */ + pdest_buf[dest_buf_idx] = 0xffff; + PHL_INFO(" dest_buf_len: %d \n", dest_buf_idx); + break; + } + /* Get 2nd hex value as register value. */ + sz_line += u4bmove; + if (hal_get_hexvalue_fromstring(sz_line, &u4bregvalue, &u4bmove)) { + /*PHL_INFO("[RF-ADDR]%03lx=%08lx\n", u4bregoffset, u4bregvalue);*/ + pdest_buf[dest_buf_idx] = u4bregvalue; + dest_buf_idx++; + } + } + } + } +#if 0 + { /*debug dump buf*/ + u32 i = 0; + for (i = 0; i <= dest_buf_idx; i+=2) + PHL_INFO("[Radio-ADDR] 0x%x :[0x%x]\n", pdest_buf[i], pdest_buf[i+1]); + } +#endif + return dest_buf_idx; +} + +static int +hal_phy_find_ext_regd_num(struct rtw_para_pwrlmt_info_t *para_info, + char *regd_name) +{ + int i = 0; + + for (i = 0; i <= para_info->ext_regd_arridx ; i++) { + if (_os_strcmp(regd_name, para_info->ext_regd_name[i]) == 0) { + return i; + } + } + return -1; +} + +static void +_hal_add_ext_reg_codemap(void *d, + struct rtw_para_pwrlmt_info_t *para_info, + const char *country, + u16 domain, + const char *regd_name, + u32 nlen) +{ + struct _hal_file_regd_ext *pregd_codemap; + struct _hal_file_regd_ext *ent; + + if (!regd_name || !nlen) { + PHL_ERR("regd_name || nlen Null\n"); + goto exit; + } + + pregd_codemap = (struct _hal_file_regd_ext *)para_info->ext_reg_codemap; + ent = &pregd_codemap[para_info->ext_reg_map_num]; + + if (regd_name && _os_strlen((u8*)regd_name) < 10) { + + if (hal_phy_find_ext_regd_num(para_info, (char *)regd_name) == -1) { + u8 idx = (u8)(para_info->ext_regd_arridx + 1); + + if (idx < regd_name_max_size) { + _os_strcpy(para_info->ext_regd_name[idx], regd_name); + para_info->ext_regd_arridx++; + PHL_INFO("extrea reg [%d] = [%s]\n", + idx, para_info->ext_regd_name[idx]); + } else { + PHL_ERR("extrea reg [%d] over size\n", idx); + goto exit; + } + } + + _os_mem_cpy(d, ent->reg_name, (void*)regd_name, nlen); + PHL_INFO("store reg_name = [%s]\n", ent->reg_name); + } else { + PHL_ERR("reg_name = [%s]\n", ent->reg_name); + goto exit; + } + + if (domain != 0) + ent->domain = domain; + else + ent->domain = 0xffff; + PHL_INFO("Store DomainCode = [0x%x]\n", ent->domain); + + if (country) { + _os_mem_cpy(d, ent->country, (void*)country, 2); + PHL_INFO("Store country = [%c%c]\n", ent->country[0], ent->country[1]); + } else + _os_mem_set(d, ent->country, '\0', 2); + + para_info->ext_reg_map_num++; +exit: + return; +} + +/* +* @@Ver=2.0 +* or +* @@DomainCode=0x28, Regulation=C6 +* or +* @@CountryCode=GB, Regulation=C7 +*/ +static u8 +parse_reg_exc_config(void *drv_priv, + char *sz_line , + struct rtw_para_pwrlmt_info_t *para_info) +{ +#define VER_PREFIX "Ver=" +#define DOMAIN_PREFIX "DomainCode=0x" +#define COUNTRY_PREFIX "CountryCode=" +#define REG_PREFIX "Regulation=" + + const u8 ver_prefix_len = (u8)_os_strlen((u8*)VER_PREFIX); + const u8 domain_prefix_len = (u8)_os_strlen((u8*)DOMAIN_PREFIX); + const u8 country_prefix_len = (u8)_os_strlen((u8*)COUNTRY_PREFIX); + const u8 reg_prefix_len = (u8)_os_strlen((u8*)REG_PREFIX); + u32 i, i_val_s, i_val_e; + u32 j; + u16 domain = 0; + char *country = NULL; + u8 parse_reg = 0; + + if (sz_line[0] != '@' || sz_line[1] != '@') + return false; + + i = 2; + if (_os_strncmp(sz_line + i, VER_PREFIX, ver_prefix_len) == 0) + ; /* nothing to do */ + else if (_os_strncmp(sz_line + i, DOMAIN_PREFIX, domain_prefix_len) == 0) { + /* get string after domain prefix to ',' */ + i += domain_prefix_len; + i_val_s = i; + while (sz_line[i] != ',') { + if (sz_line[i] == '\0') + return false; + i++; + } + i_val_e = i; + + /* check if all hex */ + for (j = i_val_s; j < i_val_e; j++) + if (hal_ishexdigit(sz_line[j]) == false) + return false; + + /* get value from hex string */ + if (_os_sscanf(sz_line + i_val_s, "%hx", &domain) != 1) + return false; + + parse_reg = 1; + } else if (_os_strncmp(sz_line + i, COUNTRY_PREFIX, country_prefix_len) == 0) { + /* get string after country prefix to ',' */ + i += country_prefix_len; + i_val_s = i; + while (sz_line[i] != ',') { + if (sz_line[i] == '\0') + return false; + i++; + } + i_val_e = i; + + if (i_val_e - i_val_s != 2) + return false; + + /* check if all alpha */ + for (j = i_val_s; j < i_val_e; j++) + if (hal_is_alpha(sz_line[j]) == false) + return false; + + country = sz_line + i_val_s; + + parse_reg = 1; + + } else + return false; + + if (parse_reg) { + /* move to 'R' */ + while (sz_line[i] != 'R') { + if (sz_line[i] == '\0') + return false; + i++; + } + + /* check if matching regulation prefix */ + if (_os_strncmp(sz_line + i, REG_PREFIX, reg_prefix_len) != 0) + return false; + + /* get string after regulation prefix ending with space */ + i += reg_prefix_len; + i_val_s = i; + while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0') + i++; + + if (i == i_val_s) + return false; + + _hal_add_ext_reg_codemap(drv_priv, para_info, + country, domain, + sz_line + i_val_s, i - i_val_s); + } + + return true; +} + +static void hal_phy_store_tx_power_limit (void *drv_priv, + u8 *sregulation, + u8 *sband, + u8 *sbandwidth, + u8 *sratesection, + u8 *sbf, + u8 *sntx, + u8 *schannel, + u8 *spwrlimit, + u8 *spshape_idx, + void *pstc_txpwr_lmt, + struct rtw_para_pwrlmt_info_t *para_info) +{ + u8 band = 0, bandwidth = 0, ratesec = 0, channel = 0; + u8 ntx_idx = 0 , bf = 0 , pshape_idx = 0; + int regulation = -1; + s8 powerlimit = 0; + + struct hal_txpwr_lmt_t *array_tc_8852a_txpwr_lmt = (struct hal_txpwr_lmt_t *)pstc_txpwr_lmt; + + if (hal_get_u1bint_fromstr_indec((char *)schannel, &channel) == false + || hal_get_s1bint_fromstr_indec((char *)spwrlimit, &powerlimit) == false) { + PHL_INFO("Illegal index of power limit table [ch %s][val %s]\n", + (char *)schannel, (char *)spwrlimit); + return; + } + + if (spshape_idx != NULL) { + if (hal_get_u1bint_fromstr_indec((char *)spshape_idx, &pshape_idx) == false) { + PHL_INFO("Illegal index of pshape idx [val %s]\n", (char *)spshape_idx); + return; + } + } + + if (_os_strncmp((char *)sratesection, (const char *)"CCK", 3) == 0) + ratesec = _PW_LMT_RS_CCK; + else if (_os_strncmp((char *)sratesection, (const char *)"OFDM", 4) == 0) + ratesec = _PW_LMT_RS_OFDM; + else if (_os_strncmp((char *)sratesection, (const char *)"HT", 2) == 0) + ratesec = _PW_LMT_RS_HT; + else if (_os_strncmp((char *)sratesection, (const char *)"VHT", 3) == 0) + ratesec = _PW_LMT_RS_VHT; + else if (_os_strncmp((char *)sratesection, (const char *)"HE", 2) == 0) + ratesec = _PW_LMT_RS_HE; + else { + PHL_INFO("Wrong rate section:%s\n", (char *)sratesection); + return; + } + + if (_os_strncmp((char *)sntx, (const char *)"1T", 2) == 0) + ntx_idx = _PW_LMT_PH_1T; + else if (_os_strncmp((char *)sntx, (const char *)"2T", 2) == 0) + ntx_idx = _PW_LMT_PH_2T; + else if (_os_strncmp((char *)sntx, (const char *)"3T", 2) == 0) + ntx_idx = _PW_LMT_PH_3T; + else if (_os_strncmp((char *)sntx, (const char *)"4T", 2) == 0) + ntx_idx = _PW_LMT_PH_4T; + else { + PHL_INFO("Wrong tx num:%s\n", (char *)sntx); + return; + } + + if (_os_strncmp((char *)sbandwidth, (const char *)"20M", 3) == 0) + bandwidth = _PW_LMT_BW_20M; + else if (_os_strncmp((char *)sbandwidth, (const char *)"40M", 3) == 0) + bandwidth = _PW_LMT_BW_40M; + else if (_os_strncmp((char *)sbandwidth, (const char *)"80M", 3) == 0) + bandwidth = _PW_LMT_BW_80M; + else if (_os_strncmp((char *)sbandwidth, (const char *)"160M", 4) == 0) + bandwidth = _PW_LMT_BW_160M; + else { + PHL_INFO("unknown bandwidth: %s\n", (char *)sbandwidth); + return; + } + + if (_os_strncmp((char *)sband, (const char *)"2.4G", 4) == 0) + band = _PW_LMT_BAND_2_4G; + else if (_os_strncmp((char *)sband, (const char *)"5G", 2) == 0) + band = _PW_LMT_BAND_5G; + else { + PHL_INFO("unknown band: %s\n", (char *)sband); + return; + } + + if (_os_strncmp((char *)sbf, (const char *)"Non-BF", 6) == 0 || _os_strncmp((char *)sbf, (const char *)"NA", 2) == 0) + bf = _PW_LMT_NONBF; + else if (_os_strncmp((char *)sbf, (const char *)"BF", 2) == 0) + bf = _PW_LMT_BF; + else { + PHL_INFO("unknown BF: %s\n", (char *)sbf); + return; + } + + regulation = rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str((char *)sregulation); + if (regulation == -1) { + int regd_num = hal_phy_find_ext_regd_num(para_info, (char *)sregulation); + + if (regd_num != -1) { + regulation = (u8)regd_num; + PHL_INFO("new regulation num: %d\n", regulation); + } else { + PHL_INFO("unknown regulation: %s\n", (char *)sregulation); + return; + } + } + + array_tc_8852a_txpwr_lmt->band = band; + array_tc_8852a_txpwr_lmt->bw = bandwidth; + array_tc_8852a_txpwr_lmt->ch = channel; + array_tc_8852a_txpwr_lmt->rs = ratesec; + array_tc_8852a_txpwr_lmt->ntx = ntx_idx; + array_tc_8852a_txpwr_lmt->bf = bf; + array_tc_8852a_txpwr_lmt->val = powerlimit; + array_tc_8852a_txpwr_lmt->reg = (u8)regulation; + array_tc_8852a_txpwr_lmt->tx_shap_idx = pshape_idx; + + PHL_INFO("Store of power limit table [regulation %d][band %d][bw %d]"\ + "[rate section %d][ntx %d][BF %d][chnl %d][val %d] [sphape_idx %d]\n", + array_tc_8852a_txpwr_lmt->reg, array_tc_8852a_txpwr_lmt->band, + array_tc_8852a_txpwr_lmt->bw , array_tc_8852a_txpwr_lmt->rs, + array_tc_8852a_txpwr_lmt->ntx, array_tc_8852a_txpwr_lmt->bf, + array_tc_8852a_txpwr_lmt->ch, array_tc_8852a_txpwr_lmt->val, + array_tc_8852a_txpwr_lmt->tx_shap_idx); + +} + + +static int +_hal_parse_txpwrlmt(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ +#define LD_STAGE_EXC_MAPPING 0 +#define LD_STAGE_TAB_DEFINE 1 +#define LD_STAGE_TAB_START 2 +#define LD_STAGE_COLUMN_DEFINE 3 +#define LD_STAGE_COLUMN_REG 4 +#define LD_STAGE_CH_ROW 5 +#define LD_STAGE_PSHAPE_NUM 6 + + struct rtw_para_pwrlmt_info_t *para_info = (struct rtw_para_pwrlmt_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char **regulation = NULL; + char **pshape = NULL; + char *sz_line = NULL, *ptmp = NULL; + char band[10], bandwidth[10], ratesection[10], ntx[10], colnumbuf[10], bf_type[10]; + u8 colnum = 0; + u8 loadingstage = LD_STAGE_EXC_MAPPING; + u32 struct_idx = 0; + u32 i = 0, forcnt = 0; + PHAL_TXPWR_LMT_T array_tc_8852a_txpwr_lmt; + + if (pdest_buf == NULL || psrc_buf == NULL) { + PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__); + return 0; + } + + array_tc_8852a_txpwr_lmt = (PHAL_TXPWR_LMT_T)pdest_buf; + + ptmp = (char *)psrc_buf; + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) { +line_start: + if (hal_is_allspace_tab(sz_line, sizeof(*sz_line))) + continue; + + if (hal_is_comment_string(sz_line)) + continue; + + if (loadingstage == LD_STAGE_EXC_MAPPING) { + if (sz_line[0] == '#' || sz_line[1] == '#') { + loadingstage = LD_STAGE_TAB_DEFINE; + } else { + if (parse_reg_exc_config(drv_priv, sz_line, para_info) == false) { + PHL_ERR("Fail to parse regulation exception ruls!\n"); + goto exit; + } + continue; + } + } + + if (loadingstage == LD_STAGE_TAB_DEFINE) { + /* read "## 2.4G, 20M, 1T, CCK" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + sz_line[--i] = ' '; /* return the space in front of the regulation info */ + + /* Parse the label of the table */ + _os_mem_set(drv_priv, (void *) band, 0, 10); + _os_mem_set(drv_priv, (void *) bandwidth, 0, 10); + _os_mem_set(drv_priv, (void *) ntx, 0, 10); + _os_mem_set(drv_priv, (void *) ratesection, 0, 10); + _os_mem_set(drv_priv, (void *) bf_type, 0, 10); + + if (!hal_parse_fiedstring(sz_line, &i, band, ' ', ',')) { + PHL_ERR("Fail to parse band!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, bandwidth, ' ', ',')) { + PHL_ERR("Fail to parse bandwidth!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, ntx, ' ', ',')) { + PHL_ERR("Fail to parse ntx!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, ratesection, ' ', ',')) { + PHL_ERR("Fail to parse rate!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, bf_type, ' ', '/')) { + PHL_ERR("Fail to parse BF!\n"); + struct_idx = 0; + goto exit; + } + + loadingstage = LD_STAGE_TAB_START; + } else if (loadingstage == LD_STAGE_TAB_START) { + /* read "## START" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + if (_os_strncmp((char *)(sz_line + i), (const char *)"START", 5)) { + PHL_ERR("Missing \"## START\" label\n"); + struct_idx = 0; + goto exit; + } + loadingstage = LD_STAGE_COLUMN_DEFINE; + } else if (loadingstage == LD_STAGE_COLUMN_DEFINE) { + /* read "## #5# " */ + if (sz_line[0] != '#' || sz_line[1] != '#') + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + _os_mem_set(drv_priv, (void *) colnumbuf, 0, 10); + if (!hal_parse_fiedstring(sz_line, &i, colnumbuf, '#', '#')) { + PHL_ERR("Fail to parse column number!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_get_u1bint_fromstr_indec(colnumbuf, &colnum)) { + PHL_ERR("Column number \"%s\" is not unsigned decimal\n", colnumbuf); + struct_idx = 0; + goto exit; + } + if (colnum == 0) { + PHL_ERR("Column number is 0\n"); + struct_idx = 0; + goto exit; + } + PHL_INFO("[%s][%s][%s][%s][%s] column num:%d\n", + band, bandwidth, ratesection, ntx, bf_type, colnum); + + regulation = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * colnum); + if (!regulation) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + pshape = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * colnum); + if (!pshape) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + loadingstage = LD_STAGE_COLUMN_REG; + } else if (loadingstage == LD_STAGE_COLUMN_REG) { + /* read "## FCC ETSI MKK IC KCC" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + for (forcnt = 0; forcnt < colnum; ++forcnt) { + u32 i_ns; + + /* skip the space */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + i++; + i_ns = i; + + while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0') + i++; + + regulation[forcnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1); + if (!regulation[forcnt]) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + + _os_mem_cpy(drv_priv, regulation[forcnt], sz_line + i_ns, i - i_ns); + regulation[forcnt][i - i_ns] = '\0'; + } + + if (1) { + PHL_INFO("column name:"); + for (forcnt = 0; forcnt < colnum; ++forcnt) + PHL_INFO(" %s", regulation[forcnt]); + PHL_INFO("\n"); + } + + loadingstage = LD_STAGE_PSHAPE_NUM; + }else if (loadingstage == LD_STAGE_PSHAPE_NUM) { + + if (sz_line[0] == '#' || sz_line[1] == '#') + continue; + + if ((sz_line[0] != 'p' && sz_line[0] != 'P') || + (sz_line[1] != 's' && sz_line[1] != 'S')) { + PHL_INFO("No PShape prefix: '%c','%c'(%d,%d), continue to CH ROW\n", + sz_line[0], sz_line[1], sz_line[0], sz_line[1]); + loadingstage = LD_STAGE_CH_ROW; + goto line_start; + } + PHL_INFO("1.sz_line[0 1] %c %c", sz_line[0], sz_line[1]); + i = 6;/* move to the location behind 'e' */ + + for (forcnt = 0; forcnt < colnum; ++forcnt) { + u32 i_ns; + + /* skip the space */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + i++; + i_ns = i; + PHL_INFO("1.sz_line[%d] %c\n", i ,sz_line[i]); + while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0') + i++; + + pshape[forcnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1); + if (!pshape[forcnt]) { + PHL_ERR("Regulation alloc fail, pshape [%d]\n", forcnt); + goto exit; + } + PHL_INFO("2.pshape [%d] = %s\n", forcnt, pshape[forcnt]); + + _os_mem_cpy(drv_priv, pshape[forcnt], sz_line + i_ns, i - i_ns); + pshape[forcnt][i - i_ns] = '\0'; + PHL_INFO(" forcnt %d shape idx: %s:", forcnt, pshape[forcnt]); + } + + if (1) { + PHL_INFO("pshape idx:"); + for (forcnt = 0; forcnt < colnum; ++forcnt) + PHL_INFO(" %s", pshape[forcnt]); + PHL_INFO("\n"); + } + + loadingstage = LD_STAGE_CH_ROW; + } else if (loadingstage == LD_STAGE_CH_ROW) { + char channel[10] = {0}, powerlimit[10] = {0}; + u8 cnt = 0; + + /* the table ends */ + if (sz_line[0] == '#' && sz_line[1] == '#') { + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + if (_os_strncmp((char *)(sz_line + i), (const char *)"END", 3) == 0) { + loadingstage = LD_STAGE_TAB_DEFINE; + if (regulation) { + for (forcnt = 0; forcnt < colnum; ++forcnt) { + if (regulation[forcnt]) { + _os_mem_free(drv_priv, + (u8 *)regulation[forcnt], + _os_strlen((u8 *)regulation[forcnt]) + 1); + regulation[forcnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * colnum); + regulation = NULL; + } + if (pshape) { + for (forcnt = 0; forcnt < colnum; ++forcnt) { + if (pshape[forcnt]) { + _os_mem_free(drv_priv, + (u8 *)pshape[forcnt], + _os_strlen((u8 *)pshape[forcnt]) + 1); + pshape[forcnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * colnum); + pshape = NULL; + } + colnum = 0; + continue; + } else { + PHL_ERR("Missing \"## END\" label\n"); + struct_idx = 0; + goto exit; + } + } + + if ((sz_line[0] != 'c' && sz_line[0] != 'C') || + (sz_line[1] != 'h' && sz_line[1] != 'H')) { + PHL_ERR("Wrong channel prefix: '%c','%c'(%d,%d)\n", + sz_line[0], sz_line[1], sz_line[0], sz_line[1]); + continue; + } + i = 2;/* move to the location behind 'h' */ + + /* load the channel number */ + cnt = 0; + while (sz_line[i] >= '0' && sz_line[i] <= '9') { + channel[cnt] = sz_line[i]; + ++cnt; + ++i; + } + PHL_INFO("chnl %s!\n", channel); + + for (forcnt = 0; forcnt < colnum; ++forcnt) { + /* skip the space between channel number and the power limit value */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + /* load the power limit value */ + _os_mem_set(drv_priv, (void *) powerlimit, 0, 10); + + if (sz_line[i] == 'W' && sz_line[i + 1] == 'W') { + /* + * case "WW" assign special ww value + * means to get minimal limit in other regulations at same channel + */ + s8 ww_value = -63; + _os_snprintf(powerlimit, 10, "%d", ww_value); + i += 2; + + } else if (sz_line[i] == 'N' && sz_line[i + 1] == 'A') { + /* + * case "NA" assign max txgi value + * means no limitation + */ + _os_snprintf(powerlimit, 10, "%d", 63); + i += 2; + + } else if ((sz_line[i] >= '0' && sz_line[i] <= '9') || sz_line[i] == '.' + || sz_line[i] == '+' || sz_line[i] == '-') { + /* case of dBm value */ + u8 integer = 0, fraction = 0, negative = 0; + u32 u4bmove; + s8 lmt = 0; + + if (sz_line[i] == '+' || sz_line[i] == '-') { + if (sz_line[i] == '-') + negative = 1; + i++; + } + + if (hal_get_fractionvalue_fromstring(&sz_line[i], &integer, &fraction, &u4bmove)) + i += u4bmove; + else { + PHL_ERR("Limit \"%s\" is not valid decimal\n", &sz_line[i]); + struct_idx = 0; + goto exit; + } + + /* transform to string of value in unit of txgi */ + lmt = (integer * 4) + ((u16)fraction * 4 / 100); + if (negative) + lmt = -lmt; + _os_snprintf(powerlimit, 10, "%d", lmt); + + } else { + PHL_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n" + , sz_line[i], sz_line[i + 1], sz_line[i], sz_line[i + 1]); + struct_idx = 0; + goto exit; + } + + /* store the power limit value */ + hal_phy_store_tx_power_limit(drv_priv, (u8 *)regulation[forcnt], + (u8 *)band, (u8 *)bandwidth, (u8 *)ratesection, + (u8 *)bf_type, (u8 *)ntx, (u8 *)channel, + (u8 *)powerlimit, (u8 *)pshape[forcnt], + (void*)&array_tc_8852a_txpwr_lmt[struct_idx], para_info); + + struct_idx++; + } + } + } +exit: + if (regulation) { + for (forcnt = 0; forcnt < colnum; ++forcnt) { + if (regulation[forcnt]) { + _os_mem_free(drv_priv, + (u8 *)regulation[forcnt], + _os_strlen((u8 *)regulation[forcnt]) + 1); + regulation[forcnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * colnum); + regulation = NULL; + } + if (pshape) { + for (forcnt = 0; forcnt < colnum; ++forcnt) { + if (pshape[forcnt]) { + _os_mem_free(drv_priv, + (u8 *)pshape[forcnt], + _os_strlen((u8 *)pshape[forcnt]) + 1); + pshape[forcnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * colnum); + pshape = NULL; + } + + return struct_idx; +} + + +static void hal_phy_store_tx_power_limit_ru (void *drv_priv, + u8 *sregulation, + u8 *sband, + u8 *sbandwidth, + u8 *sratesection, + u8 *sntx, + u8 *schannel, + u8 *spwrlimit, + u8 *spshape_idx, + void *pstc_txpwr_lmt_ru, + struct rtw_para_pwrlmt_info_t *para_info) +{ + u8 band = 0, bandwidth = 0, ratesec = 0, channel = 0; + u8 ntx_idx = 0 , pshape_idx = 0; + int regulation = -1; + s8 powerlimit = 0; + + struct hal_txpwr_lmt_ru_t *array_tc_8852a_txpwr_lmt_ru = (struct hal_txpwr_lmt_ru_t *)pstc_txpwr_lmt_ru; + + if (hal_get_u1bint_fromstr_indec((char *)schannel, &channel) == false + || hal_get_s1bint_fromstr_indec((char *)spwrlimit, &powerlimit) == false) { + PHL_INFO("Illegal index of power limit table [ch %s][val %s]\n", + (char *)schannel, (char *)spwrlimit); + return; + } + + if (spshape_idx != NULL) { + if (hal_get_u1bint_fromstr_indec((char *)spshape_idx, &pshape_idx) == false) { + PHL_INFO("Illegal index of pshape idx [val %s]\n", (char *)spshape_idx); + return; + } + } + + if (_os_strncmp((char *)sband, (const char *)"2.4G", 4) == 0) + band = _PW_LMT_BAND_2_4G; + else if (_os_strncmp((char *)sband, (const char *)"5G", 2) == 0) + band = _PW_LMT_BAND_5G; + else { + PHL_INFO("unknown band: %s\n", (char *)sband); + return; + } + + if (_os_strncmp((char *)sbandwidth, (const char *)"RU26", 4) == 0) + bandwidth = _PW_LMT_RU_BW_RU26; + else if (_os_strncmp((char *)sbandwidth, (const char *)"RU52", 4) == 0) + bandwidth = _PW_LMT_RU_BW_RU52; + else if (_os_strncmp((char *)sbandwidth, (const char *)"RU106", 5) == 0) + bandwidth = _PW_LMT_RU_BW_RU106; + else { + PHL_INFO("unknown RU bandwidth: %s\n", (char *)sbandwidth); + return; + } + + if (_os_strncmp((char *)sntx, (const char *)"1T", 2) == 0) + ntx_idx = _PW_LMT_PH_1T; + else if (_os_strncmp((char *)sntx, (const char *)"2T", 2) == 0) + ntx_idx = _PW_LMT_PH_2T; + else if (_os_strncmp((char *)sntx, (const char *)"3T", 2) == 0) + ntx_idx = _PW_LMT_PH_3T; + else if (_os_strncmp((char *)sntx, (const char *)"4T", 2) == 0) + ntx_idx = _PW_LMT_PH_4T; + else { + PHL_INFO("Wrong tx num:%s\n", (char *)sntx); + return; + } + + if (_os_strncmp((char *)sratesection, (const char *)"HE", 2) == 0) + ratesec = _PW_LMT_RS_HE; + else { + PHL_INFO("Wrong RU rate section:%s\n", (char *)sratesection); + return; + } + + regulation = rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str((char *)sregulation); + if (regulation == -1) { + int regd_num = hal_phy_find_ext_regd_num(para_info, (char *)sregulation); + + if (regd_num != -1) { + regulation = (u8)regd_num; + PHL_INFO("new regulation num: %d\n", regulation); + } else { + PHL_INFO("unknown regulation: %s\n", (char *)sregulation); + return; + } + + } + + array_tc_8852a_txpwr_lmt_ru->band = band; + array_tc_8852a_txpwr_lmt_ru->rubw = bandwidth; + array_tc_8852a_txpwr_lmt_ru->ntx = ntx_idx; + array_tc_8852a_txpwr_lmt_ru->rs = ratesec; + array_tc_8852a_txpwr_lmt_ru->reg = (u8)regulation; + array_tc_8852a_txpwr_lmt_ru->ch = channel; + array_tc_8852a_txpwr_lmt_ru->val = powerlimit; + array_tc_8852a_txpwr_lmt_ru->tx_shap_idx = pshape_idx; + + PHL_INFO("Store of power limit RU table [band %d][bw %d][ntx %d]"\ + "[rate section %d][regulation %d][chnl %d][val %d] [sphape_idx %d]\n", + array_tc_8852a_txpwr_lmt_ru->band , array_tc_8852a_txpwr_lmt_ru->rubw, + array_tc_8852a_txpwr_lmt_ru->ntx, array_tc_8852a_txpwr_lmt_ru->rs, + array_tc_8852a_txpwr_lmt_ru->reg, array_tc_8852a_txpwr_lmt_ru->ch, + array_tc_8852a_txpwr_lmt_ru->val, array_tc_8852a_txpwr_lmt_ru->tx_shap_idx); +} + + +static int +_hal_parse_txpwrlmt_ru(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ +#define LD_STAGE_EXC_MAPPING 0 +#define LD_STAGE_TAB_DEFINE 1 +#define LD_STAGE_TAB_START 2 +#define LD_STAGE_COLUMN_DEFINE 3 +#define LD_STAGE_COLUMN_REG 4 +#define LD_STAGE_CH_ROW 5 +#define LD_STAGE_PSHAPE_NUM 6 + + struct rtw_para_pwrlmt_info_t *para_info = (struct rtw_para_pwrlmt_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char **regulation = NULL; + char **pshape = NULL; + char *sz_line = NULL, *ptmp = NULL; + char band[10], bandwidth[10], ratesection[10], ntx[10], col_num_buf[10]; + u8 col_num = 0; + u8 loadingstage = LD_STAGE_EXC_MAPPING; + u32 struct_idx = 0; + u32 i = 0, for_cnt = 0; + pHal_Txpwr_lmt_Ru_t array_tc_8852a_txpwr_lmt_ru; + + if (pdest_buf == NULL || psrc_buf == NULL) { + PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__); + return 0; + } + + array_tc_8852a_txpwr_lmt_ru = (pHal_Txpwr_lmt_Ru_t)pdest_buf; + + ptmp = (char *)psrc_buf; + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) { +line_start: + if (hal_is_allspace_tab(sz_line, sizeof(*sz_line))) + continue; + + if (hal_is_comment_string(sz_line)) + continue; + + if (loadingstage == LD_STAGE_EXC_MAPPING) { + if (sz_line[0] == '#' || sz_line[1] == '#') { + loadingstage = LD_STAGE_TAB_DEFINE; + } else { + if (parse_reg_exc_config(drv_priv, sz_line, para_info) == false) { + PHL_ERR("Fail to parse regulation exception ruls!\n"); + goto exit; + } + continue; + } + } + + if (loadingstage == LD_STAGE_TAB_DEFINE) { + /* read "## 2.4G, RU26, 1T, HE //" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + sz_line[--i] = ' '; /* return the space in front of the regulation info */ + + /* Parse the label of the table */ + _os_mem_set(drv_priv, (void *) band, 0, 10); + _os_mem_set(drv_priv, (void *) bandwidth, 0, 10); + _os_mem_set(drv_priv, (void *) ntx, 0, 10); + _os_mem_set(drv_priv, (void *) ratesection, 0, 10); + + if (!hal_parse_fiedstring(sz_line, &i, band, ' ', ',')) { + PHL_ERR("Fail to parse band!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, bandwidth, ' ', ',')) { + PHL_ERR("Fail to parse bandwidth!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, ntx, ' ', ',')) { + PHL_ERR("Fail to parse ntx!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_parse_fiedstring(sz_line, &i, ratesection, ' ', ' ')) { + PHL_ERR("Fail to parse rate!\n"); + struct_idx = 0; + goto exit; + } + + loadingstage = LD_STAGE_TAB_START; + } else if (loadingstage == LD_STAGE_TAB_START) { + /* read "## START" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + if (_os_strncmp((char *)(sz_line + i), (const char *)"START", 5)) { + PHL_ERR("Missing \"## START\" label\n"); + struct_idx = 0; + goto exit; + } + loadingstage = LD_STAGE_COLUMN_DEFINE; + } else if (loadingstage == LD_STAGE_COLUMN_DEFINE) { + /* read "## #5# " */ + if (sz_line[0] != '#' || sz_line[1] != '#') + + /* skip the space */ + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + _os_mem_set(drv_priv, (void *) col_num_buf, 0, 10); + if (!hal_parse_fiedstring(sz_line, &i, col_num_buf, '#', '#')) { + PHL_ERR("Fail to parse column number!\n"); + struct_idx = 0; + goto exit; + } + if (!hal_get_u1bint_fromstr_indec(col_num_buf, &col_num)) { + PHL_ERR("Column number \"%s\" is not unsigned decimal\n", col_num_buf); + struct_idx = 0; + goto exit; + } + if (col_num == 0) { + PHL_ERR("Column number is 0\n"); + struct_idx = 0; + goto exit; + } + PHL_INFO("[%s][%s][%s][%s] column num:%d\n", + band, bandwidth, ratesection, ntx, col_num); + + regulation = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * col_num); + if (!regulation) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + pshape = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * col_num); + if (!pshape) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + loadingstage = LD_STAGE_COLUMN_REG; + }else if (loadingstage == LD_STAGE_COLUMN_REG) { + /* read "## FCC ETSI MKK IC KCC" */ + if (sz_line[0] != '#' || sz_line[1] != '#') + continue; + + /* skip the space */ + i = 2; + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + u32 i_ns; + + /* skip the space */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + i++; + i_ns = i; + + while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0') + i++; + + regulation[for_cnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1); + if (!regulation[for_cnt]) { + PHL_ERR("Regulation alloc fail\n"); + struct_idx = 0; + goto exit; + } + + _os_mem_cpy(drv_priv, regulation[for_cnt], sz_line + i_ns, i - i_ns); + regulation[for_cnt][i - i_ns] = '\0'; + } + + if (1) { + PHL_INFO("column name:"); + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) + PHL_INFO(" %s", regulation[for_cnt]); + PHL_INFO("\n"); + } + loadingstage = LD_STAGE_PSHAPE_NUM; + }else if (loadingstage == LD_STAGE_PSHAPE_NUM) { + + if (sz_line[0] == '#' || sz_line[1] == '#') + continue; + + if ((sz_line[0] != 'p' && sz_line[0] != 'P') || + (sz_line[1] != 's' && sz_line[1] != 'S')) { + PHL_INFO("No PShape prefix: '%c','%c'(%d,%d), continue to CH ROW\n", + sz_line[0], sz_line[1], sz_line[0], sz_line[1]); + loadingstage = LD_STAGE_CH_ROW; + goto line_start; + } + PHL_INFO("1.sz_line[0 1] %c %c", sz_line[0], sz_line[1]); + i = 6;/* move to the location behind 'e' */ + + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + u32 i_ns; + + /* skip the space */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + i++; + i_ns = i; + PHL_INFO("1.sz_line[%d] %c\n", i ,sz_line[i]); + while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0') + i++; + + pshape[for_cnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1); + if (!pshape[for_cnt]) { + PHL_ERR("Regulation alloc fail, pshape [%d]\n", for_cnt); + goto exit; + } + PHL_INFO("2.pshape [%d] = %s\n", for_cnt, pshape[for_cnt]); + + _os_mem_cpy(drv_priv, pshape[for_cnt], sz_line + i_ns, i - i_ns); + pshape[for_cnt][i - i_ns] = '\0'; + PHL_INFO(" forcnt %d shape idx: %s:", for_cnt, pshape[for_cnt]); + } + + if (1) { + PHL_INFO("pshape idx:"); + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) + PHL_INFO(" %s", pshape[for_cnt]); + PHL_INFO("\n"); + } + + loadingstage = LD_STAGE_CH_ROW; + } else if (loadingstage == LD_STAGE_CH_ROW) { + char channel[10] = {0}, powerlimit[10] = {0}; + u8 cnt = 0; + + /* the table ends */ + if (sz_line[0] == '#' && sz_line[1] == '#') { + i = 2; + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + if (_os_strncmp((char *)(sz_line + i), (const char *)"END", 3) == 0) { + loadingstage = LD_STAGE_TAB_DEFINE; + if (regulation) { + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + if (regulation[for_cnt]) { + _os_mem_free(drv_priv, + (u8 *)regulation[for_cnt], + _os_strlen((u8 *)regulation[for_cnt]) + 1); + regulation[for_cnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * col_num); + regulation = NULL; + } + if (pshape) { + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + if (pshape[for_cnt]) { + _os_mem_free(drv_priv, + (u8 *)pshape[for_cnt], + _os_strlen((u8 *)pshape[for_cnt]) + 1); + pshape[for_cnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * col_num); + pshape = NULL; + } + col_num = 0; + continue; + } else { + PHL_ERR("Missing \"## END\" label\n"); + struct_idx = 0; + goto exit; + } + } + + if ((sz_line[0] != 'c' && sz_line[0] != 'C') || + (sz_line[1] != 'h' && sz_line[1] != 'H')) { + PHL_ERR("Wrong channel prefix: '%c','%c'(%d,%d)\n", + sz_line[0], sz_line[1], sz_line[0], sz_line[1]); + continue; + } + i = 2;/* move to the location behind 'h' */ + + /* load the channel number */ + cnt = 0; + while (sz_line[i] >= '0' && sz_line[i] <= '9') { + channel[cnt] = sz_line[i]; + ++cnt; + ++i; + } + PHL_INFO("chnl %s!\n", channel); + + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + /* skip the space between channel number and the power limit value */ + while (sz_line[i] == ' ' || sz_line[i] == '\t') + ++i; + + /* load the power limit value */ + _os_mem_set(drv_priv, (void *) powerlimit, 0, 10); + + if (sz_line[i] == 'W' && sz_line[i + 1] == 'W') { + /* + * case "WW" assign special ww value + * means to get minimal limit in other regulations at same channel + */ + s8 ww_value = -63;//phy_txpwr_ww_lmt_value(Adapter); + + _os_snprintf(powerlimit, 10, "%d", ww_value); + i += 2; + + } else if (sz_line[i] == 'N' && sz_line[i + 1] == 'A') { + /* + * case "NA" assign max txgi value + * means no limitation + */ + _os_snprintf(powerlimit, 10, "%d", 127); + i += 2; + + } else if ((sz_line[i] >= '0' && sz_line[i] <= '9') || sz_line[i] == '.' + || sz_line[i] == '+' || sz_line[i] == '-') { + /* case of dBm value */ + u8 integer = 0, fraction = 0, negative = 0; + u32 u4bmove; + s8 lmt = 0; + + if (sz_line[i] == '+' || sz_line[i] == '-') { + if (sz_line[i] == '-') + negative = 1; + i++; + } + + if (hal_get_fractionvalue_fromstring(&sz_line[i], &integer, &fraction, &u4bmove)) + i += u4bmove; + else { + PHL_ERR("Limit \"%s\" is not valid decimal\n", &sz_line[i]); + struct_idx = 0; + goto exit; + } + /* transform to string of value in unit of txgi */ + lmt = (integer * 4) + ((u16)fraction * 4 / 100); + if (negative) + lmt = -lmt; + _os_snprintf(powerlimit, 10, "%d", lmt); + + } else { + PHL_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n" + , sz_line[i], sz_line[i + 1], sz_line[i], sz_line[i + 1]); + struct_idx = 0; + goto exit; + } + + /* store the power limit value */ + hal_phy_store_tx_power_limit_ru(drv_priv, + (u8 *)regulation[for_cnt], (u8 *)band, + (u8 *)bandwidth, (u8 *)ratesection, + (u8 *)ntx, (u8 *)channel, (u8 *)powerlimit, + (u8 *)pshape[for_cnt], + (void*)&array_tc_8852a_txpwr_lmt_ru[struct_idx], + para_info); + PHL_INFO("array_tc_8852a_txpwr_lmt_ru[%d] \n", struct_idx); + struct_idx++; + } + } + } +exit: + if (regulation) { + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + if (regulation[for_cnt]) { + _os_mem_free(drv_priv, + (u8 *)regulation[for_cnt], + _os_strlen((u8 *)regulation[for_cnt]) + 1); + regulation[for_cnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * col_num); + regulation = NULL; + } + if (pshape) { + for (for_cnt = 0; for_cnt < col_num; ++for_cnt) { + if (pshape[for_cnt]) { + _os_mem_free(drv_priv, + (u8 *)pshape[for_cnt], + _os_strlen((u8 *)pshape[for_cnt]) + 1); + pshape[for_cnt] = NULL; + } + } + _os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * col_num); + pshape = NULL; + } + + return struct_idx; +} + +static void hal_phy_store_tx_power_track( + void *drv_priv, + char *band, + char *path, + char *sign, + char *channel, + char *rate, + char *data, + void *txpwr_track_table) +{ +#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \ + ((_os_strcmp(band, _band) == 0) && (_os_strcmp(path, _path) == 0) && (_os_strcmp(sign, _sign) == 0) &&\ + (_os_strcmp(rate, _rate) == 0) && (_os_strcmp(channel, _chnl) == 0)\ + ) +#define STR_EQUAL_2G(_band, _path, _sign, _rate) \ + ((_os_strcmp(band, _band) == 0) && (_os_strcmp(path, _path) == 0) && (_os_strcmp(sign, _sign) == 0) &&\ + (_os_strcmp(rate, _rate) == 0)\ + ) + +#define STORE_SWING_TABLE(_array, _iteratedIdx) \ + do { \ + for (token = (char *)_os_strsep(&data, delim); token != (char *)NULL; token = (char *)_os_strsep(&data, delim)) {\ + _os_sscanf(token, "%d", &idx);\ + _array[_iteratedIdx++] = (s8)idx;\ + } } while (0)\ + + struct hal_txpwr_track_t *prfcalibrateInfo = (struct hal_txpwr_track_t *)txpwr_track_table; + + u32 j = 0; + char *token; + char delim[] = ","; + u32 idx = 0; + + PHL_INFO("===>initDeltaSwingIndexTables():"\ + "Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n", + band, path, sign, channel, rate, data); + + if (STR_EQUAL_2G("2G", "A", "+", "CCK")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j); + else if (STR_EQUAL_2G("2G", "A", "-", "CCK")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j); + else if (STR_EQUAL_2G("2G", "B", "+", "CCK")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j); + else if (STR_EQUAL_2G("2G", "B", "-", "CCK")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j); + else if (STR_EQUAL_2G("2G", "A", "+", "ALL")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2ga_p, j); + else if (STR_EQUAL_2G("2G", "A", "-", "ALL")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2ga_n, j); + else if (STR_EQUAL_2G("2G", "B", "+", "ALL")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2gb_p, j); + else if (STR_EQUAL_2G("2G", "B", "-", "ALL")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2gb_n, j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[0], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[0], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[0], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[0], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[1], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[1], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[1], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[1], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[2], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[2], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[2], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[2], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[3], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[3], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[3], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3")) + STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[3], j); + else + PHL_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n"); +} + +static int +_hal_parse_txpwrtrack(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen) +{ + struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t; + u32 *pdest_buf = para_info->para_data; + char *sz_line = NULL, *ptmp = NULL; + u32 i = 0; + struct hal_txpwr_track_t *txpwr_track; + + if (pdest_buf == NULL || psrc_buf == NULL) { + PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__); + return 0; + } + /* Assing destination buffer to be Txpwr_track table format*/ + txpwr_track = (struct hal_txpwr_track_t *)pdest_buf; + + ptmp = (char *)psrc_buf; + for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; + sz_line = hal_getLinefrombuffer(ptmp)) + { + if (!hal_is_comment_string(sz_line)) { + char band[5] = "", path[5] = "", sign[5] = ""; + char chnl[5] = "", rate[10] = ""; + char data[300] = ""; /* 100 is too small */ + + if (_os_strlen((u8 *)sz_line) < 10 || sz_line[0] != '[') + continue; + + _os_strncpy(band, sz_line + 1, 2); + _os_strncpy(path, sz_line + 5, 1); + _os_strncpy(sign, sz_line + 8, 1); + + i = 10; /* sz_line+10 */ + if (!hal_parse_fiedstring(sz_line, &i, rate, '[', ']')) { + PHL_ERR("Fail to parse rate!\n"); + } + if (!hal_parse_fiedstring(sz_line, &i, chnl, '[', ']')) { + if (!_os_strcmp("5G",band)) + PHL_ERR("Fail to parse channel group!\n"); + } + while (i < _os_strlen((u8 *)sz_line) && '{' != sz_line[i]) + i++; + if (!hal_parse_fiedstring(sz_line, &i, data, '{', '}')) { + PHL_ERR("Fail to parse data!\n"); + } + hal_phy_store_tx_power_track(drv_priv, + band, path, sign, + chnl, rate, data, + (void*)txpwr_track); + } + } + return 1; +} + +void +_hal_dl_para_file(struct rtw_phl_com_t *phl_com, + void *para_info_t, char *ic_name, + int (*parser_fun)(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen), + const char *file_name) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + + void *drv = phl_com->drv_priv; + char *hal_phy_folder = HAL_FILE_CONFIG_PATH; + u32 para_size = 0; + u8 *para_buf = NULL; + struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t; + + if (para_info->para_src == RTW_PARA_SRC_INTNAL) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s.parser_fun=NULL \n", file_name); + return; + } + + if (!parser_fun || (!para_info->para_data)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s.parser_fun=NULL \n", file_name); + para_info->para_src = RTW_PARA_SRC_INTNAL; + return; + } + + if ((para_info->para_data_len != 0) && (para_info->para_src == RTW_PARA_SRC_EXTNAL)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s. para_data_len != 0 !!!\n", file_name); + return; + } + + para_buf = _os_mem_alloc(drv, MAX_HWCONFIG_FILE_CONTENT); + if (!para_buf) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "para_buf=NULL \n"); + para_info->para_src = RTW_PARA_SRC_INTNAL; + return; + } + + + if (para_info->para_src == RTW_PARA_SRC_EXTNAL) { + _os_snprintf(para_info->para_path, MAX_PATH_LEN, "%s%s%s%s", + hal_phy_folder ,ic_name, _os_path_sep, file_name); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s:: %s\n",__FUNCTION__, + para_info->para_path); + + para_size = _os_read_file(para_info->para_path, para_buf, + MAX_HWCONFIG_FILE_CONTENT); + } else if (para_info->para_src == RTW_PARA_SRC_CUSTOM) { + _os_mem_cpy(drv, para_buf, para_info->para_data, para_info->para_data_len); + _os_mem_set(drv, para_info->para_data, 0, para_info->para_data_len); + para_size = para_info->para_data_len; + para_info->para_data_len = 0; + } + + if (para_size != 0) { + /* Parsing file content */ + para_info->para_data_len = parser_fun(drv, para_info, para_buf, + para_size); + + if (para_info->para_data_len) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, + "%s:: Download file ok.\n", __FUNCTION__); + } else { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, + "%s:: Failed to parser %s\n", + __FUNCTION__, file_name); + para_info->para_src = RTW_PARA_SRC_INTNAL; + } + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s:: Download file ok.\n", + file_name); + } else { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s:: Error reading file.\n", + file_name); + + para_info->para_src = RTW_PARA_SRC_INTNAL; + para_info->para_data_len = 0; + } + _os_mem_free(drv, para_buf, MAX_HWCONFIG_FILE_CONTENT); +#endif +} + +enum rtw_hal_status +_phl_pwrlmt_para_alloc(struct rtw_phl_com_t* phl_com, + struct rtw_para_pwrlmt_info_t *para_info) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (para_info->para_src == RTW_PARA_SRC_EXTNAL) { + u32 file_buf_sz = MAX_HWCONFIG_FILE_CONTENT; + u32 buf_sz = MAX_LINES_HWCONFIG_TXT; + void *drv = phl_com->drv_priv; + u8 para_regd_str_arridx; + const char * const *_para_regd_str = rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(¶_regd_str_arridx); + u8 i = 0; + + for (i = 0; i < para_regd_str_arridx ; i++) { + _os_strcpy(para_info->ext_regd_name[i] , _para_regd_str[i]); + PHL_INFO(" prepare ext_regd_name[%d] = %s", + i , para_info->ext_regd_name[i]); + } + para_info->ext_regd_arridx = para_regd_str_arridx; + + para_info->para_data = _os_mem_alloc(drv, file_buf_sz * sizeof(u32)); + if (!para_info->para_data) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, + "%s::para_data allocmem fail\n",__FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + + para_info->ext_reg_codemap = _os_mem_alloc(drv, buf_sz * sizeof(u8)); + if (!para_info->ext_reg_codemap) { + if (para_info->para_data) + _os_mem_free(drv, para_info->para_data, file_buf_sz * sizeof(u32)); + para_info->para_data = NULL; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, + "%s::ext_reg_codemap allocmem fail\n",__FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; + } else + return RTW_HAL_STATUS_FAILURE; +#else + return RTW_HAL_STATUS_FAILURE; +#endif +} + +enum rtw_hal_status +phl_load_file_data_alloc(struct rtw_phl_com_t* phl_com, struct rtw_para_info_t *para_info) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + u32 buf_sz = MAX_HWCONFIG_FILE_CONTENT; + void *drv = phl_com->drv_priv; + + if (para_info->para_src == RTW_PARA_SRC_EXTNAL) { + if (para_info->para_data_len == 0) { + para_info->para_data = _os_mem_alloc(drv, buf_sz * sizeof(u32)); + } + if (!para_info->para_data) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, + "%s:: allocmem fail\n",__FUNCTION__); + return RTW_HAL_STATUS_FAILURE; + } + return RTW_HAL_STATUS_SUCCESS; + } else + return RTW_HAL_STATUS_FAILURE; +#else + return RTW_HAL_STATUS_FAILURE; +#endif +} + +void +rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, + char *ic_name, void *hal) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + struct hal_info_t *hal_info = hal; + struct phy_sw_cap_t *phy_sw_cap = NULL; + u8 idx=0; + u8 max_phy_num = 1; + + if (hal_info->hal_com->dbcc_en == true) + max_phy_num = 2; + + for (idx=0; idx < max_phy_num; idx++) {/*Temp modiy for 1 BB phy Reg file */ + + phy_sw_cap = &phl_com->phy_sw_cap[idx]; + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->bb_phy_reg_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->bb_phy_reg_info, + ic_name, + _hal_parse_phyreg, + "PHY_REG.txt"); + + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->bb_phy_reg_gain_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->bb_phy_reg_gain_info, + ic_name, + _hal_parse_phyreg, + "PHY_REG_GAIN.txt"); + + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->rf_radio_a_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_radio_a_info, + ic_name, + _hal_parse_radio, + "RadioA.txt"); + + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->rf_radio_b_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_radio_b_info, + ic_name, + _hal_parse_radio, + "RadioB.txt"); + + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->rf_txpwr_byrate_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_txpwr_byrate_info, + ic_name, + _hal_parse_txpwr_by_rate, + "TXPWR_ByRate.txt"); + + if (phl_load_file_data_alloc(phl_com, + &phy_sw_cap->rf_txpwrtrack_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_txpwrtrack_info, + ic_name, + _hal_parse_txpwrtrack, + "TXPWR_TrackTSSI.txt"); + + if (_phl_pwrlmt_para_alloc(phl_com, + &phy_sw_cap->rf_txpwrlmt_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_txpwrlmt_info, + ic_name, + _hal_parse_txpwrlmt, + "TXPWR_LMT.txt"); + + if (_phl_pwrlmt_para_alloc(phl_com, + &phy_sw_cap->rf_txpwrlmt_ru_info) == RTW_HAL_STATUS_SUCCESS) + _hal_dl_para_file(phl_com, + &phy_sw_cap->rf_txpwrlmt_ru_info, + ic_name, + _hal_parse_txpwrlmt_ru, + "TXPWR_LMT_RU.txt"); + } +#endif +} + +u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size) +{ + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + char path[256] = {0}; + char *ic_name = NULL; + char *intf = NULL; + void *d = phlcom_to_drvpriv(phl_com); + + switch (phl_com->hci_type) { + case RTW_HCI_PCIE: + intf = "e"; + break; + case RTW_HCI_USB: + intf = "u"; + break; + case RTW_HCI_SDIO: + intf = "s"; + break; + default: + PHL_WARN("%s unknown hci type %u \n", __func__, phl_com->hci_type); + return (u8)RTW_HAL_STATUS_FAILURE; + } + + switch (hal_com->chip_id) { + case CHIP_WIFI6_8852A: + ic_name = "rtl8852a"; + break; + case CHIP_WIFI6_8852B: + ic_name = "rtl8852b"; + break; + default: + PHL_WARN("%s unknown chip id %u \n", __func__, hal_com->chip_id); + return (u8)RTW_HAL_STATUS_FAILURE; + } + + if (name == NULL || buf_size == NULL) + return (u8)RTW_HAL_STATUS_FAILURE; + + if (!fw_info->sym_buf) { + + fw_info->sym_buf = _os_mem_alloc(d, RTW_MAX_FW_SIZE); + if (!fw_info->sym_buf) { + PHL_WARN("%s : buf for fw symbol allocate fail!!\n", __func__); + return (u8)RTW_HAL_STATUS_FAILURE; + } + } + _os_snprintf(path, MAX_PATH_LEN, "%s%s%s%s%s", FW_FILE_CONFIG_PATH, + ic_name, intf, _os_path_sep, name); + + PHL_INFO("%s : %s\n", __func__, path); + + fw_info->sym_buf_size = _os_read_file(path, fw_info->sym_buf, + RTW_MAX_FW_SIZE); + /* reading fw file failed */ + if (0 == fw_info->sym_buf_size) + return (u8)RTW_HAL_STATUS_FAILURE; + + *buf = fw_info->sym_buf; + *buf_size = fw_info->sym_buf_size; + + return (u8)RTW_HAL_STATUS_SUCCESS; +} + +u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit) +{ + u8 status = true; +#ifdef CONFIG_EFUSE_CONFIG_FILE + struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)hal; + struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv; + char *hal_phy_folder = HAL_FILE_CONFIG_PATH; + char file_path[256]; + + _os_snprintf(file_path, MAX_PATH_LEN, "%s%s%s%s", + hal_phy_folder , ic_name, _os_path_sep, "efuse.map"); + PHL_INFO("%s::open map path: %s\n", __FUNCTION__, file_path); + + status = rtw_hal_efuse_file_map_load(hal_info, file_path, is_limit); + if (status == RTW_HAL_STATUS_FAILURE) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "%s:: %s FAIL\n", __FUNCTION__, file_path); + status = false; + goto exit; + } + + _os_snprintf(file_path, MAX_PATH_LEN, "%s%s%s%s", + hal_phy_folder , ic_name, _os_path_sep, "efuse.mask"); + PHL_INFO("%s::open mask path: %s\n", __FUNCTION__, file_path); + + status = rtw_hal_efuse_file_mask_load(hal_info, file_path, is_limit); + if (status == RTW_HAL_STATUS_FAILURE) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "%s:: %s FAIL\n", __FUNCTION__, file_path); + status = false; + goto exit; + } +exit: +#endif + return status; +} + diff --git a/phl/hal_g6/hal_ld_file.h b/phl/hal_g6/hal_ld_file.h new file mode 100644 index 0000000..73a8c26 --- /dev/null +++ b/phl/hal_g6/hal_ld_file.h @@ -0,0 +1,240 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef _HAL_LD_FILE_H_ +#define _HAL_LD_FILE_H_ + +#define PHYPG_BAND2G 0 +#define PHYPG_BAND5G 1 +#define PHYPG_RF1Tx 0 +#define PHYPG_RF2Tx 1 +#define PHYPG_OFFSET 15 + +enum PHY_PG_RATE_def { + CCK_11M_1M = 0, + OFDM_18M_6M = 1, + OFDM_54M_24M = 2, + HE1SS_MCS3_0 = 3, + HE1SS_MCS7_4 = 4, + HE1SS_MCS11_8 = 5, + HE1SS_DCM4_0 = 6, + HE2SS_MCS3_0 = 3, + HE2SS_MCS7_4 = 4, + HE2SS_MCS11_8 = 5, + HE2SS_DCM4_0 = 6, + Legacy_AllRate = 7, + HE_AllRate = 8, +}; + +struct _hal_file_regd_ext { + u16 domain; + char country[2]; + char reg_name[10]; +}; + +typedef struct hal_txpwr_lmt_t { + u8 band; + u8 bw; + u8 ntx; + u8 rs; + u8 bf; + u8 reg; + u8 ch; + s8 val; + u8 tx_shap_idx; +} HAL_TXPWR_LMT_T , *PHAL_TXPWR_LMT_T; + +typedef struct hal_txpwr_lmt_ru_t { + u8 band; + u8 rubw; + u8 ntx; + u8 rs; + u8 reg; + u8 ch; + s8 val; + u8 tx_shap_idx; +} Hal_Txpwr_lmt_Ru_t , *pHal_Txpwr_lmt_Ru_t; + +enum _halrf_tx_pw_lmt_ru_bandwidth_type { + _PW_LMT_RU_BW_RU26, + _PW_LMT_RU_BW_RU52, + _PW_LMT_RU_BW_RU106, + _PW_LMT_RU_BW_NULL +}; + +enum _halrf_pw_lmt_band_type { + _PW_LMT_BAND_2_4G = 0, + _PW_LMT_BAND_5G = 1 +}; + +enum _halrf_pw_lmt_bandwidth_type { + _PW_LMT_BW_20M = 0, + _PW_LMT_BW_40M = 1, + _PW_LMT_BW_80M = 2, + _PW_LMT_BW_160M = 3, + _PW_LMT_MAX_BANDWIDTH_NUM = 4 +}; + +enum _halrf_pw_lmt_ratesection_type { + _PW_LMT_RS_CCK = 0, + _PW_LMT_RS_OFDM = 1, + _PW_LMT_RS_HT = 2, + _PW_LMT_RS_VHT = 3, + _PW_LMT_RS_HE = 4, + _PW_LMT_MAX_RS_NUM = 5 +}; + +enum _halrf_pw_lmt_rfpath_type { + _PW_LMT_PH_1T = 0, + _PW_LMT_PH_2T = 1, + _PW_LMT_PH_3T = 2, + _PW_LMT_PH_4T = 3, + _PW_LMT_MAX_PH_NUM = 4 +}; + +enum _halrf_pw_lmt_beamforming_type { + _PW_LMT_NONBF = 0, + _PW_LMT_BF = 1, + _PW_LMT_MAX_BF_NUM = 2 +}; + +/*@--------------------------Define Parameters-------------------------------*/ +#define AVG_THERMAL_NUM 8 +#define MAX_RF_PATH 4 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 4 +#define DELTA_SWINTSSI_SIZE 61 + +/*@---------------------------End Define Parameters---------------------------*/ + +struct hal_txpwr_track_t { + /* u8 is_txpowertracking; */ + u8 tx_powercount; + bool is_txpowertracking_init; + bool is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_path[MAX_RF_PATH]; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_avg_index_path[MAX_RF_PATH]; + s8 power_index_offset_path[MAX_RF_PATH]; + + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + bool txpowertracking_in_progress; + + bool is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset; + s8 delta_power_index; + s8 delta_power_index_path[MAX_RF_PATH]; + s8 delta_power_index_last; + s8 delta_power_index_last_path[MAX_RF_PATH]; + bool is_tx_power_changed; + + /*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/ + u8 delta_lck; + s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; + u8 bb_swing_idx_ofdm_base; + u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH]; + bool bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + bool bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + bool modify_tx_agc_flag_path_a; + bool modify_tx_agc_flag_path_b; + bool modify_tx_agc_flag_path_c; + bool modify_tx_agc_flag_path_d; + bool modify_tx_agc_flag_path_a_cck; + bool modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + }; + +void rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal); +u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit); +u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size); +#endif /*_HAL_LD_FILE_H_*/ \ No newline at end of file diff --git a/phl/hal_g6/hal_led.c b/phl/hal_g6/hal_led.c new file mode 100644 index 0000000..ff0987e --- /dev/null +++ b/phl/hal_g6/hal_led.c @@ -0,0 +1,73 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_LED_C_ +#include "hal_headers.h" + +#define HAL_LED_GET_CTRL_MODE(m) \ + ((m) == RTW_LED_CTRL_SW_PP_MODE \ + ? MAC_AX_LED_MODE_SW_CTRL_PP \ + : ((m) == RTW_LED_CTRL_SW_OD_MODE \ + ? MAC_AX_LED_MODE_SW_CTRL_OD \ + : ((m) == RTW_LED_CTRL_HW_TX_MODE \ + ? MAC_AX_LED_MODE_TX_ON \ + : ((m) == RTW_LED_CTRL_HW_RX_MODE \ + ? MAC_AX_LED_MODE_RX_ON \ + : MAC_AX_LED_MODE_TRX_ON)))) + +#define HAL_LED_GET_ID(i) \ + ((i) == RTW_LED_ID_0 ? 0 : ((i) == RTW_LED_ID_1 ? 1 : 0)) + +enum rtw_hal_status rtw_hal_led_set_ctrl_mode(void *hal, enum rtw_led_id led_id, + enum rtw_led_ctrl_mode ctrl_mode) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, + "%s: led_id == %d, ctrl_mode == %d\n", __func__, led_id, + ctrl_mode); + + if (ctrl_mode == RTW_LED_CTRL_NOT_SUPPORT) + return RTW_HAL_STATUS_SUCCESS; + + return rtw_hal_mac_led_set_ctrl_mode( + hal_info, HAL_LED_GET_CTRL_MODE(ctrl_mode), HAL_LED_GET_ID(led_id)); +} + +enum rtw_hal_status rtw_hal_led_control(void *hal, enum rtw_led_id led_id, + u8 high) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, "===> hal_led_ctrl()\n"); + + if (high) { + PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, + "hal_led_ctrl() : LED HIGH\n"); + status = + rtw_hal_mac_led_ctrl(hal_info, 1, HAL_LED_GET_ID(led_id)); + } else { + PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, + "hal_led_ctrl() : LED LOW\n"); + status = + rtw_hal_mac_led_ctrl(hal_info, 0, HAL_LED_GET_ID(led_id)); + } + + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, + "hal_led_ctrl() : rtw_hal_mac_led_ctrl() failed\n"); + } + + return status; +} diff --git a/phl/hal_g6/hal_mcc.c b/phl/hal_g6/hal_mcc.c new file mode 100644 index 0000000..9c78bf7 --- /dev/null +++ b/phl/hal_g6/hal_mcc.c @@ -0,0 +1,418 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_MCC_C_ +#include "hal_headers.h" +#include "hal_mcc.h" + +#ifdef CONFIG_MCC_SUPPORT +#define _mcc_fill_slot_bt_coex(_dbg_hal_i, _en) ((struct rtw_phl_mcc_dbg_hal_info *)_dbg_hal_i)->btc_in_group = _en; + +void _mcc_update_slot_dbg_info(struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i, + bool bt_role, u16 macid, u16 dur) +{ + struct rtw_phl_mcc_dbg_slot_info *dbg_slot_i = NULL; + u8 idx = 0; + + for (idx = 0; idx < dbg_hal_i->slot_num; idx++) { + dbg_slot_i = &dbg_hal_i->dbg_slot_i[idx]; + if (dbg_slot_i->bt_role) { + if (bt_role) { + dbg_slot_i->dur = dur; + break; + } + } else if (false == bt_role && dbg_slot_i->macid == macid) { + dbg_slot_i->dur = dur; + break; + } + } +} + +void _mcc_update_dbg_info(struct rtw_phl_mcc_en_info *info, + struct rtw_phl_mcc_bt_info *bt_info) +{ + u8 idx = 0; + + if (bt_info->bt_dur > 0) { + _mcc_fill_slot_bt_coex(&info->dbg_hal_i, true); + } else { + _mcc_fill_slot_bt_coex(&info->dbg_hal_i, false); + } + for (idx = 0; idx < info->mrole_num; idx++) { + _mcc_update_slot_dbg_info(&info->dbg_hal_i, false, + info->mcc_role[idx].macid, + info->mcc_role[idx].policy.dur_info.dur); + } +} + +void _mcc_fill_slot_dbg_info(struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i, + struct rtw_phl_mcc_role *mrole) +{ + struct rtw_phl_mcc_dbg_slot_info *dbg_slot_i = NULL; + if (dbg_hal_i->slot_num >= SLOT_NUM) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_hal_dbg_info(): Fill fail, dbg_hal_i->slot_num(%d) >= SLOT_NUM(%d), please check code\n", + dbg_hal_i->slot_num, SLOT_NUM); + goto exit; + } + dbg_slot_i = &dbg_hal_i->dbg_slot_i[dbg_hal_i->slot_num]; + dbg_slot_i->bt_role = mrole->bt_role ? true : false; + dbg_slot_i->dur = mrole->policy.dur_info.dur; + if (false == dbg_slot_i->bt_role) { + dbg_slot_i->ch = mrole->chandef->chan; + dbg_slot_i->macid = mrole->macid; + } + dbg_hal_i->slot_num++; +exit: + return; +} + +enum rtw_hal_status _mcc_add_bt_role(struct hal_info_t *hal, u8 group, + struct rtw_phl_mcc_slot_info *slot_i, + struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_role mrole = {0}; + + mrole.policy.dur_info.dur = (u8)slot_i->slot; + mrole.bt_role = true; + mrole.group = group; + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_bt_role(): add bt role\n"); + _mcc_fill_slot_dbg_info(dbg_hal_i, &mrole); + status = rtw_hal_mac_add_mcc(hal, &mrole); + return status; +} + +enum rtw_hal_status _mcc_add_wifi_role(struct hal_info_t *hal, + u8 group, struct rtw_phl_mcc_slot_info *slot_i, + struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_role *mrole = slot_i->mrole; + + if (NULL == mrole) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Fail, NULL == mrole, Please check code\n"); + goto exit; + } + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): add wifi role\n"); + mrole->group = group; + _mcc_fill_slot_dbg_info(dbg_hal_i, mrole); + status = rtw_hal_mac_add_mcc(hal, mrole); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Add mcc failed\n"); + goto exit; + } + status = rtw_hal_mcc_update_macid_bitmap(hal, group, + (u8)mrole->macid, + &mrole->used_macid); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Add MACID bitmap failed\n"); + goto exit; + } +exit: + return status; +} + +enum rtw_hal_status _mcc_fill_role_setting(struct hal_info_t *hal, + struct rtw_phl_mcc_en_info *info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_slot_info *slot_i = info->m_pattern.slot_order; + u8 i = 0; + + if (info->m_pattern.slot_num > SLOT_NUM) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Fial, slot_num(%d) > SLOT_NUM(%d), please check code\n", + info->m_pattern.slot_num, SLOT_NUM); + goto exit; + } else if (info->m_pattern.slot_num < MIN_TDMRA_SLOT_NUM) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Fial, slot_num(%d) < MIN_TDMRA_SLOT_NUM(%d), please check code\n", + info->m_pattern.slot_num, MIN_TDMRA_SLOT_NUM); + goto exit; + } + for (i = 0; i < info->m_pattern.slot_num; i++) { + if (!slot_i[i].bt_role) { + if (RTW_HAL_STATUS_SUCCESS!= _mcc_add_wifi_role(hal, + info->group, &slot_i[i], &info->dbg_hal_i)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Add wifi role failed\n"); + goto exit; + } + } else { + if (RTW_HAL_STATUS_SUCCESS != _mcc_add_bt_role(hal, + info->group, &slot_i[i], &info->dbg_hal_i)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Add bt role failed\n"); + goto exit; + } + } + } + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + +enum rtw_hal_status _mcc_replace_pattern(struct hal_info_t *hal, + struct rtw_phl_mcc_en_info *ori_info, + struct rtw_phl_mcc_en_info *new_info, + struct rtw_phl_mcc_bt_info *new_bt_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_role *ref_role = + &new_info->mcc_role[new_info->ref_role_idx]; + bool btc_in_group = false; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> _mcc_replace_pattern\n"); + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_get_mcc_group(hal, &new_info->group)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Allocate group fail\n"); + goto exit; + } + _os_mem_set(hal_to_drvpriv(hal), &new_info->dbg_hal_i, 0, + sizeof(struct rtw_phl_mcc_dbg_hal_info)); + status = _mcc_fill_role_setting(hal, new_info); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Fail fill role setting\n"); + goto exit; + } + if (new_info->sync_tsf_info.sync_en) { + status = rtw_hal_mcc_sync_enable(hal, new_info); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Sync enable failed\n"); + goto exit; + } + } + if (new_bt_info->bt_dur > 0) { + btc_in_group = true; + _mcc_fill_slot_bt_coex(&new_info->dbg_hal_i, true); + } else { + _mcc_fill_slot_bt_coex(&new_info->dbg_hal_i, false); + } + status = rtw_hal_mac_start_mcc(hal, new_info->group, + (u8)ref_role->macid, new_info->tsf_high, + new_info->tsf_low, btc_in_group, 1, ori_info->group); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Start MCC failed\n"); + goto exit; + } + status = RTW_HAL_STATUS_SUCCESS; +exit: + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "<<< _mcc_replace_pattern(): Ststus(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_mcc_get_2ports_tsf(void *hal, u8 group, + u16 macid_x, u16 macid_y, u32 *tsf_x_h, u32 *tsf_x_l, + u32 *tsf_y_h, u32 *tsf_y_l) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_hal_mac_mcc_request_tsf(hal, group, (u8)macid_x, (u8)macid_y); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_get_2ports_tsf(): Req tsf failed\n"); + goto exit; + } + status = rtw_hal_mac_get_mcc_tsf_rpt(hal, group, tsf_x_h, tsf_x_l, + tsf_y_h, tsf_y_l); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_get_2ports_tsf(): Get tsf rpt failed\n"); + goto exit; + } +exit: + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_get_2ports_tsf(): Ststus(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_notify_mcc_macid(void *hal, + struct rtw_phl_mcc_role *mrole, + enum rtw_phl_tdmra_wmode wmode) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + + if (wmode == RTW_PHL_TDMRA_AP_CLIENT_WMODE || + wmode == RTW_PHL_TDMRA_2CLIENTS_WMODE) { + if (sts != rtw_hal_bb_upd_mcc_macid(hal, mrole)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "%s: Notify BB MCC MACID bitmap failed\n", + __FUNCTION__); + goto exit; + + } + } + sts = RTW_HAL_STATUS_SUCCESS; +exit: + return sts; +} + +enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group, + u16 macid, struct rtw_phl_mcc_macid_bitmap *info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_hal_mac_mcc_macid_bitmap(hal, group, (u8)macid, + (u8 *)info->bitmap, info->len); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_update_macid_bitmap(): Add MACID bitmap failed\n"); + } + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_update_macid_bitmap(): Ststus(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal, + struct rtw_phl_mcc_en_info *info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_role *ref_role = &info->mcc_role[info->ref_role_idx]; + + if (info->sync_tsf_info.sync_en) { + status = rtw_hal_mac_mcc_sync_enable(hal, ref_role->group, + (u8)info->sync_tsf_info.source, + (u8)info->sync_tsf_info.target, + (u8)info->sync_tsf_info.offset); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_sync_enable(): Sync enable failed\n"); + goto exit; + } + } else { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_sync_enable(): sync_en == false, please check code\n"); + goto exit; + } + status = RTW_HAL_STATUS_SUCCESS; +exit: + return status; +} + +enum rtw_hal_status _mcc_set_duration(void *hal, + struct rtw_phl_mcc_en_info *info, + struct rtw_phl_mcc_bt_info *bt_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_hal_mac_set_duration(hal, info, bt_info); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_set_duration(): set duration failed\n"); + } else { + _mcc_update_dbg_info(info, bt_info); + } + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_mcc_set_duration(): Ststus(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_mcc_change_pattern(void *hal, + struct rtw_phl_mcc_en_info *ori_info, + struct rtw_phl_mcc_en_info *new_info, + struct rtw_phl_mcc_bt_info *new_bt_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + /* mcc_set_duration only can change 2 wifi slot, + otherwise we shall create new pattern and replace previous pattern*/ + if (new_info->m_pattern.slot_num == 2 && + new_info->m_pattern.bt_slot_num == 0 && + ori_info->m_pattern.slot_num == 2 && + ori_info->m_pattern.bt_slot_num == 0) { + status = _mcc_set_duration(hal, new_info, new_bt_info); + } else { + status = _mcc_replace_pattern(hal, ori_info, new_info, + new_bt_info); + } + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_change_pattern(): status(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_mcc_disable(void *hal, u8 group, u16 macid, + enum rtw_phl_tdmra_wmode wmode) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = rtw_hal_mac_stop_mcc(hal, group, (u8)macid); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_disable(): Stop mcc failed\n"); + goto exit; + } + status = rtw_hal_mac_del_mcc_group(hal, group); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_disable(): Delete group failed\n"); + goto exit; + } + if (wmode == RTW_PHL_TDMRA_AP_CLIENT_WMODE || + wmode == RTW_PHL_TDMRA_2CLIENTS_WMODE) { + rtw_hal_bb_mcc_stop(hal); + } + +#ifdef RTW_WKARD_HALRF_MCC + rtw_hal_rf_dpk_switch(hal, true); +#endif /* RTW_WKARD_HALRF_MCC */ + status = RTW_HAL_STATUS_SUCCESS; +exit: + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_disable(): Ststus(%d)\n", + status); + return status; +} + +enum rtw_hal_status rtw_hal_mcc_enable(void *hal, struct rtw_phl_mcc_en_info *info, + struct rtw_phl_mcc_bt_info *bt_info, + enum rtw_phl_tdmra_wmode wmode) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct rtw_phl_mcc_role *ref_role = &info->mcc_role[info->ref_role_idx]; + bool btc_in_group = false; + + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_get_mcc_group(hal, &info->group)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Allocate group fail\n"); + goto exit; + } +#ifdef RTW_WKARD_HALRF_MCC + rtw_hal_rf_dpk_switch(hal, false); +#endif /* RTW_WKARD_HALRF_MCC */ + if (RTW_HAL_STATUS_SUCCESS != _mcc_fill_role_setting(hal, info)) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Fail fill role setting\n"); + goto exit; + } +/*fill start setting*/ + if (info->sync_tsf_info.sync_en) { + status = rtw_hal_mcc_sync_enable(hal, info); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Sync enable failed\n"); + goto exit; + } + } + if (bt_info->bt_dur > 0) { + btc_in_group = true; + _mcc_fill_slot_bt_coex(&info->dbg_hal_i, true); + } else { + _mcc_fill_slot_bt_coex(&info->dbg_hal_i, false); + } + status = rtw_hal_mac_start_mcc(hal, info->group, + (u8)ref_role->macid, info->tsf_high, + info->tsf_low, btc_in_group, 0, 0); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Start MCC failed\n"); + goto exit; + } + + if (wmode == RTW_PHL_TDMRA_AP_CLIENT_WMODE || + wmode == RTW_PHL_TDMRA_2CLIENTS_WMODE) { + status = rtw_hal_bb_mcc_start(hal, &info->mcc_role[0], + &info->mcc_role[1]); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Notify MCC start failed\n"); + } + } + + status = RTW_HAL_STATUS_SUCCESS; +exit: + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_enable(): Ststus(%d)\n", + status); + return status; +} +#endif /* CONFIG_MCC_SUPPORT */ diff --git a/phl/hal_g6/hal_mcc.h b/phl/hal_g6/hal_mcc.h new file mode 100644 index 0000000..aef8ab1 --- /dev/null +++ b/phl/hal_g6/hal_mcc.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_MCC_H_ +#define _HAL_MCC_H_ +/* MCC definition for private usage */ +#ifdef CONFIG_MCC_SUPPORT +enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group, + u16 macid, struct rtw_phl_mcc_macid_bitmap *info); + +enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal, + struct rtw_phl_mcc_en_info *info); +#endif /*CONFIG_MCC_SUPPORT*/ +#endif /*_HAL_MCC_H_*/ diff --git a/phl/hal_g6/hal_mcc_def.h b/phl/hal_g6/hal_mcc_def.h new file mode 100644 index 0000000..a758c5c --- /dev/null +++ b/phl/hal_g6/hal_mcc_def.h @@ -0,0 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_MCC_DEF_H_ +#define _HAL_MCC_DEF_H_ +/* MCC definition for public usage in hal layer */ + +#endif /*_HAL_MCC_DEF_H_*/ diff --git a/phl/hal_g6/hal_notify.c b/phl/hal_g6/hal_notify.c new file mode 100644 index 0000000..0fbb4ae --- /dev/null +++ b/phl/hal_g6/hal_notify.c @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_NOTIFY_C_ +#include "hal_headers.h" + +void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 idx = 0; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: event(%d), hw_idx(%d)\n", + __func__, event, hw_idx); + + if (hw_idx == HW_BAND_MAX) { + for (idx = 0; idx < hw_idx; idx++) { + rtw_hal_bb_notification(hal_info, event, idx); + rtw_hal_mac_notification(hal_info, event, idx); + rtw_hal_rf_notification(hal_info, event, idx); + } + } else { + rtw_hal_bb_notification(hal_info, event, hw_idx); + rtw_hal_mac_notification(hal_info, event, hw_idx); + rtw_hal_rf_notification(hal_info, event, idx); + } +} + + +void rtw_hal_cmd_notification(void *hal, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + if (event == MSG_EVT_NOTIFY_BB) + rtw_hal_bb_cmd_notification(hal_info, hal_cmd, hw_idx); + else if (event == MSG_EVT_NOTIFY_RF) + rtw_hal_rf_cmd_notification(hal_info, hal_cmd, hw_idx); + else if (event == MSG_EVT_NOTIFY_MAC) + rtw_hal_mac_cmd_notification(hal_info, hal_cmd, hw_idx); + else + PHL_ERR("%s unexpect eve id = 0x%x\n", __func__, event); + +} + +enum rtw_phl_status +rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx) +{ +#ifdef CONFIG_CMD_DISP + return rtw_phl_cmd_notify(phl_com, event, hal_cmd, hw_idx); +#else + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: not support cmd notify\n", + __func__); + + return RTW_PHL_STATUS_FAILURE; +#endif /* CONFIG_CMD_DISP */ +} diff --git a/phl/hal_g6/hal_notify.h b/phl/hal_g6/hal_notify.h new file mode 100644 index 0000000..fde6178 --- /dev/null +++ b/phl/hal_g6/hal_notify.h @@ -0,0 +1,34 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_NOTIFY_H_ +#define _HAL_NOTIFY_H_ + +void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx); + + +void rtw_hal_cmd_notification(void *hal, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx); + + +enum rtw_phl_status +rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx); + +#endif /*_HAL_NOTIFY_H_*/ + diff --git a/phl/hal_g6/hal_p2pps.c b/phl/hal_g6/hal_p2pps.c new file mode 100644 index 0000000..c6d675c --- /dev/null +++ b/phl/hal_g6/hal_p2pps.c @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_P2PPS_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_P2PPS +#define TSF32_TOG_EARLY_T 2000 /*2ms*/ + +enum rtw_hal_status rtw_hal_noa_enable(void *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 cur_en_desc_num = noa_info->en_desc_num; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]%s: macid(0x%x), cur_en_desc_num(%d)\n", + __func__, macid, cur_en_desc_num); + if (cur_en_desc_num == 0) { + ret = rtw_hal_mac_noa_init(hal_info, noa_info, in_desc, macid); + } else { + ret = rtw_hal_mac_noa_update(hal_info, noa_info, in_desc, macid); + } + return ret; +} + +enum rtw_hal_status rtw_hal_noa_disable(void *hal, + struct rtw_phl_noa_info *noa_info, + struct rtw_phl_noa_desc *in_desc, + u16 macid) +{ + enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 cur_en_desc_num = noa_info->en_desc_num; + + PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]%s(): cur_en_desc_num(%d)\n", + __func__, cur_en_desc_num); + if (cur_en_desc_num == 1) { + ret = rtw_hal_mac_noa_terminate(hal_info, noa_info, in_desc, + macid); + } else { + ret = rtw_hal_mac_noa_remove(hal_info, noa_info, in_desc, macid); + } + return ret; +} + +enum rtw_hal_status rtw_hal_tsf32_tog_enable(void *hal, + struct rtw_wifi_role_t *w_role) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = hal; + h_stat = rtw_hal_mac_tsf32_tog_enable(hal_info, w_role->hw_band, + w_role->hw_port, + TSF32_TOG_EARLY_T); + return h_stat; +} + +enum rtw_hal_status rtw_hal_tsf32_tog_disable(void *hal, + struct rtw_wifi_role_t *w_role) +{ + enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = hal; + h_stat = rtw_hal_mac_tsf32_tog_disable(hal_info, w_role->hw_band, + w_role->hw_port); + return h_stat; +} + +enum rtw_hal_status rtw_hal_get_tsf32_tog_rpt(void *hal, + struct rtw_phl_tsf32_tog_rpt *rpt) +{ + struct hal_info_t *hal_info = hal; + + return rtw_hal_mac_get_tsf32_tog_rpt(hal_info, rpt); +} +#endif + diff --git a/phl/hal_g6/hal_ps.c b/phl/hal_g6/hal_ps.c new file mode 100644 index 0000000..cf10eed --- /dev/null +++ b/phl/hal_g6/hal_ps.c @@ -0,0 +1,370 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_PS_C_ +#include "hal_headers.h" +#ifdef CONFIG_POWER_SAVE +#define case_pwr_state(src) \ + case PS_PWR_STATE_##src: return #src +const char *hal_ps_pwr_state_to_str(u8 pwr_state) +{ + switch (pwr_state) { + case_pwr_state(ACTIVE); + case_pwr_state(BAND0_RFON); + case_pwr_state(BAND1_RFON); + case_pwr_state(BAND0_RFOFF); + case_pwr_state(BAND1_RFOFF); + case_pwr_state(CLK_GATED); + case_pwr_state(PWR_GATED); + case_pwr_state(MAX); + default: + return "Undefined"; + } +} + +#define LPS_PROTOCAL_LEAVE_TOLERANCE 50 /* ms */ +#define PWR_LVL_CHANGE_TOLERANCE 50 /* ms */ +#define MAX_CHK_PWR_STATE_CHANGE_CNT 5 + +static enum rtw_hal_status +_hal_ps_lps_chk_leave(struct hal_info_t *hal_info, u16 macid) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + u32 mac_sts = 0; + u32 priv_mac_sts = 0; + u32 start_time = _os_get_cur_time_ms(); + u32 pass_time = 0; + + do { + status = rtw_hal_mac_lps_chk_leave(hal_info, macid, &mac_sts); + if (status == RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): pass time = %d ms.\n", + __func__, pass_time); + break; + } + + if (mac_sts != priv_mac_sts) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): mac status %u.\n", + __func__, mac_sts); + priv_mac_sts = mac_sts; + } + + pass_time = phl_get_passing_time_ms(start_time); + if (pass_time > LPS_PROTOCAL_LEAVE_TOLERANCE) + break; + + _os_sleep_us(hal_to_drvpriv(hal_info), 50); + + } while (1); + + rtw_hal_fw_dbg_dump(hal_info, false); + + if (status != RTW_HAL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): polling timeout!\n", __func__); + + return status; +} + +static enum rtw_hal_status +_hal_ps_lps_cfg(struct hal_info_t *hal_info, + struct rtw_hal_lps_info *lps_info) +{ + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): mode(%d), listen bcn mode(%d), awake interval(%d), smart_ps_mode(%d).\n", + __func__, lps_info->lps_en, lps_info->listen_bcn_mode, + lps_info->awake_interval, lps_info->smart_ps_mode); + + return rtw_hal_mac_lps_cfg(hal_info, lps_info); +} + +static enum rtw_hal_status +_hal_ps_pwr_state_chk(struct hal_info_t *hal_info, u8 req_pwr_state) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + u32 mac_sts = 0; + u32 priv_mac_sts = 0; + u32 start_time = _os_get_cur_time_ms(); + u32 pass_time = 0; + + do { + status = rtw_hal_mac_chk_pwr_state(hal_info, req_pwr_state, &mac_sts); + if (status == RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): pass time = %d ms.\n", + __func__, pass_time); + break; + } + + if (mac_sts != priv_mac_sts) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): mac status %u.\n", + __func__, mac_sts); + priv_mac_sts = mac_sts; + } + + pass_time = phl_get_passing_time_ms(start_time); + if (pass_time > PWR_LVL_CHANGE_TOLERANCE) + break; + + _os_sleep_us(hal_to_drvpriv(hal_info), 50); + + } while (1); + + rtw_hal_fw_dbg_dump(hal_info, true); + + if (status != RTW_HAL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): polling timeout!\n", __func__); + + return status; +} + +static enum rtw_hal_status +_hal_ps_cfg_pwr_state(struct hal_info_t *hal_info, u8 req_pwr_state) +{ +#if (HAL_LPS_SKIP_HW_CFG == 0) + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + u8 cnt = 0; + + for (cnt = 0; cnt < MAX_CHK_PWR_STATE_CHANGE_CNT; cnt++) { + + /* rpwm */ + status = rtw_hal_mac_req_pwr_state(hal_info, req_pwr_state); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, + "[HALPS], %s(): set pwr state %s fail!\n", + __func__, hal_ps_pwr_state_to_str(req_pwr_state)); + return RTW_HAL_STATUS_FAILURE; + } + + /* cpwm */ + status = _hal_ps_pwr_state_chk(hal_info, req_pwr_state); + if (status == RTW_HAL_STATUS_SUCCESS) + break; + } + + if (cnt < MAX_CHK_PWR_STATE_CHANGE_CNT) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, + "[HALPS], %s(): chk pwr state %s success, cnt %d.\n", + __func__, hal_ps_pwr_state_to_str(req_pwr_state), cnt); + return RTW_HAL_STATUS_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, + "[HALPS], %s(): chk pwr state %s fail!\n", + __func__, hal_ps_pwr_state_to_str(req_pwr_state)); + return RTW_HAL_STATUS_FAILURE; + } +#else + return RTW_HAL_STATUS_SUCCESS; +#endif +} + +static enum rtw_hal_status +_hal_ps_cfg_pwr_on(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_phl_evt_ops *ops = &phl_com->evt_ops; + enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS; + + if (hal_info->hal_com->is_hal_init) { + #if (HAL_LPS_SKIP_HW_CFG == 0) + status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_ACTIVE); + #else + status = RTW_HAL_STATUS_SUCCESS; + #endif + } else { + #if (HAL_IPS_SKIP_HW_CFG == 0) + if (ops->set_rf_state(phlcom_to_drvpriv(phl_com), RTW_RF_ON) == true) + status = RTW_HAL_STATUS_SUCCESS; + else + status = RTW_HAL_STATUS_FAILURE; + #else + status = RTW_HAL_STATUS_SUCCESS; + #endif + } + + return status; +} + +static enum rtw_hal_status +_hal_ps_cfg_pwr_off(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct rtw_phl_evt_ops *ops = &phl_com->evt_ops; + + #if (HAL_IPS_SKIP_HW_CFG == 0) + if (ops->set_rf_state(phlcom_to_drvpriv(phl_com), RTW_RF_OFF) == true) + return RTW_HAL_STATUS_SUCCESS; + else + return RTW_HAL_STATUS_FAILURE; + #else + return RTW_HAL_STATUS_SUCCESS; + #endif +} + +static enum rtw_hal_status +_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + u8 req_pwr_lvl) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + switch (req_pwr_lvl) { + case PS_PWR_LVL_PWROFF: + status = _hal_ps_cfg_pwr_off(phl_com, hal_info); + break; + case PS_PWR_LVL_PWR_GATED: + status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_PWR_GATED); + break; + case PS_PWR_LVL_CLK_GATED: + status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_CLK_GATED); + break; + case PS_PWR_LVL_RF_OFF: + status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_BAND0_RFOFF); + break; + case PS_PWR_LVL_PWRON: + status = _hal_ps_cfg_pwr_on(phl_com, hal_info); + break; + default: + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[HALPS], %s(): undefined pwr lvl!\n", __func__); + break; + } + + return status; +} + +void _hal_ps_proc_hw_rf_state_done(void* priv, struct phl_msg* msg) +{ + struct rtw_phl_com_t *phl_com = (struct rtw_phl_com_t *)priv; + + if (msg->inbuf && msg->inlen) { + _os_kmem_free(phlcom_to_drvpriv(phl_com), msg->inbuf, msg->inlen); + } +} + +static void +_hal_ps_ntfy_hw_rf_state(struct rtw_phl_com_t *phl_com, + enum rtw_rf_state rf_state) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + void *d = phlcom_to_drvpriv(phl_com); + enum rtw_rf_state *rf_ntfy = NULL; + + rf_ntfy = (enum rtw_rf_state *)_os_kmem_alloc(d, sizeof(*rf_ntfy)); + if (rf_ntfy == NULL) { + PHL_ERR("[HALPS], %s(): alloc for ntfy fail.\n", __func__); + return; + } + + *rf_ntfy = rf_state; + msg.inbuf = (u8 *)rf_ntfy; + msg.inlen = sizeof(*rf_ntfy); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_HW_RF_CHG); + attr.completion.completion = _hal_ps_proc_hw_rf_state_done; + attr.completion.priv = phl_com; + if (rtw_phl_msg_hub_hal_send(phl_com, &attr, &msg) != + RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("[HALPS], %s(): send msg failed\n", __func__); + _os_kmem_free(d, rf_ntfy, sizeof(*rf_ntfy)); + } +} + +/** + * configured requested power level + * return success if configure power level ok + * @phl_com: see rtw_phl_com_t + * @hal: see hal_info_t + * @req_pwr_lvl: target power level to configured + */ +enum rtw_hal_status +rtw_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, void *hal, + u8 req_pwr_lvl) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + status = _hal_ps_pwr_lvl_cfg(phl_com, hal_info, req_pwr_lvl); + if (status != RTW_HAL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): pwr lvl cfg fail!\n", __func__); + } + + return status; +} + +/** + * configure the legacy power save (protocol) + * return configure lps fail or not + * @hal: see hal_info_t + * @lps: see rtw_hal_lps_info + */ +enum rtw_hal_status +rtw_hal_ps_lps_cfg(void *hal, struct rtw_hal_lps_info *lps_info) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + status = _hal_ps_lps_cfg(hal_info, lps_info); + + if (status == RTW_HAL_STATUS_SUCCESS) { + if (lps_info->lps_en == false) + status = _hal_ps_lps_chk_leave(hal_info, lps_info->macid); + } + + return status; +} + +enum rtw_hal_status rtw_hal_ps_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + + status = phl_ps_hal_pwr_req(phl_com, src, pwr_req); + if (status != RTW_PHL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): fail (pwr_req %d).\n", __func__, pwr_req); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +void +rtw_hal_ps_chk_hw_rf_state(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + enum rtw_rf_state rf_state = RTW_RF_ON; + u8 val = 0; + + hstatus = rtw_hal_mac_get_wl_dis_val(hal_info, &val); + if (hstatus != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("[HALPS], %s(): get wl dis val fail, status: %d\n", __func__, hstatus); + return; + } + + /* get new rf state */ + if (val == 1) { + rf_state = RTW_RF_ON; + } else if (val == 0) { + rf_state = RTW_RF_OFF; + } else { + PHL_INFO("[HALPS], %s(): wl_dis is invalid value: %d\n", __func__, val); + return; + } + + PHL_INFO("[HALPS], %s(): rf state = %d\n", __func__, rf_state); + _hal_ps_ntfy_hw_rf_state(phl_com, rf_state); +} +#endif /* CONFIG_POWER_SAVE */ diff --git a/phl/hal_g6/hal_ps.h b/phl/hal_g6/hal_ps.h new file mode 100644 index 0000000..905a1de --- /dev/null +++ b/phl/hal_g6/hal_ps.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_PS_H_ +#define _HAL_PS_H_ +#ifdef CONFIG_POWER_SAVE +/* Can be used to verify sw flow without configure hw */ +#define HAL_LPS_SKIP_HW_CFG 0 +#define HAL_IPS_SKIP_HW_CFG 0 + +enum rtw_hal_status rtw_hal_ps_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req); +#endif +#endif /*_HAL_PS_H_*/ diff --git a/phl/hal_g6/hal_regulation.c b/phl/hal_g6/hal_regulation.c new file mode 100644 index 0000000..67e7668 --- /dev/null +++ b/phl/hal_g6/hal_regulation.c @@ -0,0 +1,23 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_REGULATION_C_ +#include "hal_headers.h" + +bool rtw_hal_query_regulation(void *phl, struct rtw_regulation_info *info) +{ + return rtw_phl_query_regulation_info(phl, info); +} + + diff --git a/phl/hal_g6/hal_rx.c b/phl/hal_g6/hal_rx.c new file mode 100644 index 0000000..45d4405 --- /dev/null +++ b/phl/hal_g6/hal_rx.c @@ -0,0 +1,551 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_RX_C_ +#include "hal_headers.h" + +void rtw_hal_cfg_rxhci(void *hal, u8 en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en); + + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_rxhci(hal_info, en)) + PHL_ERR("%s failure \n", __func__); +} + +enum rtw_hal_status +rtw_hal_set_rxfltr_by_mode(void *hal, u8 band, enum rtw_rx_fltr_mode mode) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + enum rtw_rx_fltr_mode set_mode = -1; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : band(%d), mode(%d)\n", + __func__, band, mode); + /* Note: @hal_info_t.rx_fltr_mode is used to recored any mode other than + * sniffer mode, it effectively records the mode before entering monitor + * mode and the subsequent modes set after entering monitor mode. + */ + + if ((mode == RX_FLTR_MODE_SNIFFER && hal_info->monitor_mode) || + (mode == RX_FLTR_MODE_RESTORE && !hal_info->monitor_mode)) + return RTW_HAL_STATUS_FAILURE; + + if (hal_info->monitor_mode && mode != RX_FLTR_MODE_RESTORE) { + hal_info->rx_fltr_mode = mode; + return RTW_HAL_STATUS_SUCCESS; + } + + set_mode = (mode == RX_FLTR_MODE_RESTORE) ? + hal_info->rx_fltr_mode : mode; + + hstatus = rtw_hal_mac_set_rxfltr_by_mode(hal_com, band, set_mode); + if (hstatus != RTW_HAL_STATUS_SUCCESS) + return hstatus; + + hal_info->monitor_mode = (mode == RX_FLTR_MODE_SNIFFER); + + /* Record @hal_info_t.rx_fltr_mode only when the mode is not monitor and + * restore, otherwise, it is kept intact. + * TODO: The rx fltr mode should be recorded separately for each band. + */ + if (mode != RX_FLTR_MODE_SNIFFER && + mode != RX_FLTR_MODE_RESTORE) + hal_info->rx_fltr_mode = mode; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_rx_fltr_mode rtw_hal_get_rxfltr_mode(void *hal, u8 band) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return (hal_info->monitor_mode) ? RX_FLTR_MODE_SNIFFER : + hal_info->rx_fltr_mode; +} + +enum rtw_hal_status rtw_hal_scan_set_rxfltr_by_mode(void *hinfo, + enum phl_phy_idx phy_idx, bool off_channel, u8 *mode) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + if (off_channel) { + /* backup rx filter mode */ + *mode = rtw_hal_get_rxfltr_mode(hinfo, phy_idx); + hal_status = rtw_hal_set_rxfltr_by_mode(hinfo, + phy_idx, RX_FLTR_MODE_SCAN); + } else { + /* restore rx filter mode */ + hal_status = rtw_hal_set_rxfltr_by_mode(hinfo, + phy_idx, *mode); + } + return hal_status; +} + +enum rtw_hal_status +rtw_hal_enter_mon_mode(void *hinfo, enum phl_phy_idx phy_idx) +{ + return rtw_hal_set_rxfltr_by_mode(hinfo, phy_idx, RX_FLTR_MODE_SNIFFER); +} + +enum rtw_hal_status +rtw_hal_leave_mon_mode(void *hinfo, enum phl_phy_idx phy_idx) +{ + return rtw_hal_set_rxfltr_by_mode(hinfo, phy_idx, RX_FLTR_MODE_RESTORE); +} + +enum rtw_hal_status rtw_hal_acpt_crc_err_pkt(void *hal, u8 band, u8 enable) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + + return rtw_hal_mac_set_rxfltr_acpt_crc_err(hal_com, band, enable); +} + +enum rtw_hal_status rtw_hal_set_rxfltr_mpdu_size(void *hal, u8 band, u16 size) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + + return rtw_hal_mac_set_rxfltr_mpdu_size(hal_com, band, size); +} +enum rtw_hal_status rtw_hal_set_rxfltr_by_type(void *hal, u8 band, u8 type, u8 target) +{ + + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + + hstats = rtw_hal_mac_set_rxfltr_by_type(hal_info->hal_com, band, type, target); + + if (RTW_HAL_STATUS_SUCCESS != hstats) + PHL_ERR("%s : type %u status %u target %u.band %u \n", __func__, type, hstats, target, band); + + + return hstats; +} + +enum rtw_hal_status +rtw_hal_poll_hw_rx_done(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS; + + sts = rtw_hal_mac_poll_hw_rx_done(hal_info); + + return sts; +} + +enum rtw_hal_status +rtw_hal_hw_rx_resume(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS; + + sts = rtw_hal_mac_hw_rx_resume(hal_info); + + return sts; +} + +#ifdef CONFIG_PCI_HCI +/** + * rtw_hal_rx_res_query - query current HW rx resource with specifc dma channel + * @hal: see struct hal_info_t + * @dma_ch: the target dma channel + * @host_idx: current host index of this channel + * @hw_idx: current hw index of this channel + * + * this function returns the number of available tx resource + * NOTE, input host_idx and hw_idx ptr shall NOT be NULL + */ +u16 rtw_hal_rx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u16 res_num = 0; + + res_num = trx_ops->query_rx_res(hal_info->hal_com, dma_ch, host_idx, + hw_idx); + + return res_num; +} + + +/** + * rtw_hal_query_rxch_num - query total hw rx dma channels number + * + * returns the number of hw rx dma channel + */ +u8 rtw_hal_query_rxch_num(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u8 ch_num = 0; + + ch_num = trx_ops->query_rxch_num(); + + return ch_num; +} +u8 rtw_hal_check_rxrdy(struct rtw_phl_com_t *phl_com, void* hal, u8 *rxbuf, u8 dma_ch) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u8 res = 0; + + res = trx_ops->check_rxrdy(phl_com, rxbuf, dma_ch); + + return res; +} + +u8 rtw_hal_handle_rxbd_info(void* hal, u8 *rxbuf, u16 *buf_size) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u8 res = 0; + + res = trx_ops->handle_rxbd_info(hal_info, rxbuf, buf_size); + + return res; +} + +enum rtw_hal_status +rtw_hal_update_rxbd(void *hal, struct rx_base_desc *rxbd, + struct rtw_rx_buf *rxbuf) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->update_rxbd(hal_info, rxbd, rxbuf); + + return hstatus; +} + + +enum rtw_hal_status rtw_hal_notify_rxdone(void* hal, + struct rx_base_desc *rxbd, u8 ch, u16 rxcnt) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->notify_rxdone(hal_info, rxbd, ch, rxcnt); + + return hstatus; +} + +u16 rtw_hal_handle_wp_rpt(void *hal, u8 *rp, u16 len, u8 *sw_retry, u8 *dma_ch, + u16 *wp_seq, u8 *txsts) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u16 rsize = 0; + + rsize = trx_ops->handle_wp_rpt(hal_info, rp, len, sw_retry, dma_ch, + wp_seq, txsts); + return rsize; +} + +#endif /*CONFIG_PCI_HCI*/ + + +#ifdef CONFIG_USB_HCI +enum rtw_hal_status +rtw_hal_query_info(void* hal, u8 info_id, void *value) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->query_hal_info(hal_info, info_id, value); + + return hstatus; +} + +enum rtw_hal_status + rtw_hal_usb_rx_agg_cfg(void *hal, u8 mode, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->usb_rx_agg_cfg(hal, mode, agg_mode, + drv_define, timeout, size, pkt_num); + + return hstatus; +} + +u16 rtw_hal_handle_wp_rpt_usb(void *hal, u8 *rp, u16 len, u8 *macid, u8 *ac_queue, + u8 *txsts) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u16 rsize = 0; + + rsize = trx_ops->handle_wp_rpt(hal_info, rp, len, macid, ac_queue, txsts); + return rsize; +} + +#endif + +enum rtw_hal_status +rtw_hal_handle_rx_buffer(struct rtw_phl_com_t *phl_com, void* hal, + u8 *buf, u32 buf_size, + struct rtw_phl_rx_pkt *rxpkt) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->handle_rx_buffer(phl_com, hal_info, + buf, buf_size, rxpkt); + + return hstatus; +} + +#ifdef CONFIG_SDIO_HCI +void rtw_hal_sdio_rx_agg_cfg(void *hal, bool enable, u8 drv_define, + u8 timeout, u8 size, u8 pkt_num) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + + rtw_hal_mac_sdio_rx_agg_cfg(hal_info->hal_com, enable, drv_define, + timeout, size, pkt_num); +} + +int rtw_hal_sdio_rx(void *hal, struct rtw_rx_buf *rxbuf) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + + return rtw_hal_mac_sdio_rx(hal_info->hal_com, rxbuf); +} + +int rtw_hal_sdio_parse_rx(void *hal, struct rtw_rx_buf *rxbuf) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + + return rtw_hal_mac_sdio_parse_rx(hal_info->hal_com, rxbuf); +} +#endif /* CONFIG_SDIO_HCI */ + +void +hal_rx_ppdu_sts_normal_data(struct rtw_phl_com_t *phl_com, + void *hdr, + struct rtw_r_meta_data *meta) +{ + struct rtw_phl_ppdu_sts_info *ppdu_info = NULL; + enum phl_band_idx band = HW_BAND_0; + + do { + if ((NULL == phl_com) || (NULL == meta)) + break; + ppdu_info = &phl_com->ppdu_sts_info; + band = (meta->bb_sel > 0) ? HW_BAND_1 : HW_BAND_0; + if ((ppdu_info->cur_rx_ppdu_cnt[band] == meta->ppdu_cnt) && + (false == ppdu_info->latest_rx_is_psts[band])) { + /** + * add condition to avoid check fail for ppdu cnt run around 0 -> 1 -> ... -> 0 + * example : + * [frame_A(ppdu_cnt = 0)] -> [ppdu_sts(ppdu_cnt = 0)] + * ->[ppdu_sts(ppdu_cnt = 1)] -> [ppdu_sts(ppdu_cnt = 2)] ... + * ... ->[ppdu_sts(ppdu_cnt = 7)] -> [frame_B(ppdu_cnt = 0)] ... + * Therefore, frame_B has same ppdu_cnt with frame_A. + * But they are different PPDU. + **/ + break; + } + meta->ppdu_cnt_chg = true; + /* start of the PPDU */ + ppdu_info->latest_rx_is_psts[band] = false; + ppdu_info->sts_ent[band][meta->ppdu_cnt].addr_cam_vld = meta->addr_cam_vld; + ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type = PHL_GET_80211_HDR_TYPE(hdr); + ppdu_info->sts_ent[band][meta->ppdu_cnt].crc32 = meta->crc32; + ppdu_info->sts_ent[band][meta->ppdu_cnt].rx_rate = meta->rx_rate; + ppdu_info->sts_ent[band][meta->ppdu_cnt].ppdu_type = meta->ppdu_type; + + if(RTW_IS_BEACON_OR_PROBE_RESP_PKT(ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type)) { + PHL_GET_80211_HDR_ADDRESS3(phl_com->drv_priv, hdr, + ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr); + } + else if (meta->a1_match && + RTW_IS_ASOC_REQ_PKT(ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type)) { + + PHL_GET_80211_HDR_ADDRESS2(phl_com->drv_priv, hdr, + ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr); + + #ifdef DBG_AP_CLIENT_ASSOC_RSSI + { + u8 *src = NULL; + + src = ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr; + + PHL_INFO("%s [Rx-ASOC_REQ] - MAC-Addr:%02x-%02x-%02x-%02x-%02x-%02x, a1_match:%d ppdu_cnt:%d\n", + __func__, + src[0], src[1], src[2], src[3], src[4], src[5], + meta->a1_match, + meta->ppdu_cnt); + } + #endif + } + else { + _os_mem_cpy(phl_com->drv_priv, + ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr, + meta->ta, MAC_ADDRESS_LENGTH); + } + ppdu_info->sts_ent[band][meta->ppdu_cnt].valid = false; + ppdu_info->cur_rx_ppdu_cnt[band] = meta->ppdu_cnt; + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "Start of the PPDU : band %d ; ppdu_cnt %d ; frame_type %d ; addr_cam_vld %d ; size %d ; rate 0x%x ; crc32 %d\n", + band, + ppdu_info->cur_rx_ppdu_cnt[band], + ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type, + ppdu_info->sts_ent[band][meta->ppdu_cnt].addr_cam_vld, + meta->pktlen, + meta->rx_rate, + meta->crc32); + } while (false); + +} + +void +hal_rx_ppdu_sts(struct rtw_phl_com_t *phl_com, + struct rtw_phl_rx_pkt *phl_rx, + struct hal_ppdu_sts *ppdu_sts) +{ + struct rtw_phl_ppdu_sts_info *ppdu_info = NULL; + struct rtw_phl_rssi_stat *rssi_stat = NULL; + struct rtw_r_meta_data *meta = &(phl_rx->r.mdata); + struct rtw_phl_ppdu_phy_info *phy_info = &(phl_rx->r.phy_info); + u8 i = 0; + enum phl_band_idx band = HW_BAND_0; + struct rtw_phl_ppdu_sts_ent *sts_ent = NULL; + + if ((NULL == phl_com) || (NULL == meta) || (NULL == ppdu_sts)) + return; + + ppdu_info = &phl_com->ppdu_sts_info; + rssi_stat = &phl_com->rssi_stat; + band = (meta->bb_sel > 0) ? HW_BAND_1 : HW_BAND_0; + ppdu_info->latest_rx_is_psts[band] = true; + + if (0 == phy_info->is_valid) + return; + + if (ppdu_info->cur_rx_ppdu_cnt[band] != meta->ppdu_cnt) { + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "[WARNING] ppdu cnt mis-match (band %d ; cur : %d , rxmeta : %d)\n", + band, + ppdu_info->cur_rx_ppdu_cnt[band], + meta->ppdu_cnt); + } + sts_ent = &(ppdu_info->sts_ent[band][meta->ppdu_cnt]); + + if (meta->crc32 || sts_ent->crc32) { + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN, + phy_info->rssi); + return; + } + if (sts_ent->rx_rate != meta->rx_rate) { + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "[WARNING] PPDU STS rx rate mis-match\n"); + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN, + phy_info->rssi); + return; + } + if (sts_ent->ppdu_type != meta->ppdu_type) { + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "[WARNING] PPDU STS ppdu_type mis-match\n"); + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN, + phy_info->rssi); + return; + } + if (sts_ent->valid == true) { + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "[WARNING] PPDU STS is already updated, skip this ppdu status\n"); + return; + } + + /* update ppdu_info entry */ + sts_ent->freerun_cnt = meta->freerun_cnt; + _os_mem_cpy(phl_com->drv_priv, + &(sts_ent->phy_info), + phy_info, sizeof(struct rtw_phl_ppdu_phy_info)); + + sts_ent->usr_num = ppdu_sts->usr_num; + for (i = 0; i < ppdu_sts->usr_num; i++) { + if (ppdu_sts->usr[i].vld) { + sts_ent->sta[i].macid = + ppdu_sts->usr[i].macid; + sts_ent->sta[i].vld = 1; + } else { + sts_ent->sta[i].vld = 0; + } + } + sts_ent->phl_done = false; + sts_ent->valid = true; + + /* update rssi stat */ + _os_spinlock(phl_com->drv_priv, &rssi_stat->lock, _bh, NULL); + switch (sts_ent->frame_type & + (BIT(1) | BIT(0))) { + case RTW_FRAME_TYPE_MGNT : + if (sts_ent->addr_cam_vld) { + UPDATE_MA_RSSI(rssi_stat, + (1 == meta->a1_match) ? + RTW_RSSI_MGNT_ACAM_A1M : + RTW_RSSI_MGNT_ACAM, + phy_info->rssi); + } else { + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_MGNT_OTHER, + phy_info->rssi); + } + break; + case RTW_FRAME_TYPE_CTRL : + if (sts_ent->addr_cam_vld) { + UPDATE_MA_RSSI(rssi_stat, + (1 == meta->a1_match) ? + RTW_RSSI_CTRL_ACAM_A1M : + RTW_RSSI_CTRL_ACAM, + phy_info->rssi); + } else { + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_CTRL_OTHER, + phy_info->rssi); + } + break; + case RTW_FRAME_TYPE_DATA : + if (sts_ent->addr_cam_vld) { + UPDATE_MA_RSSI(rssi_stat, + (1 == meta->a1_match) ? + RTW_RSSI_DATA_ACAM_A1M : + RTW_RSSI_DATA_ACAM, + phy_info->rssi); + } else { + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_DATA_OTHER, + phy_info->rssi); + } + break; + default: + UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN, + phy_info->rssi); + break; + } + _os_spinunlock(phl_com->drv_priv, &rssi_stat->lock, _bh, NULL); +} diff --git a/phl/hal_g6/hal_rx.h b/phl/hal_g6/hal_rx.h new file mode 100644 index 0000000..3135423 --- /dev/null +++ b/phl/hal_g6/hal_rx.h @@ -0,0 +1,38 @@ + +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_RX_H_ +#define _HAL_RX_H_ + +void +hal_rx_ppdu_sts_normal_data(struct rtw_phl_com_t *phl_com, + void *hdr, + struct rtw_r_meta_data *meta); + +void +hal_rx_ppdu_sts(struct rtw_phl_com_t *phl_com, + struct rtw_phl_rx_pkt *phl_rx, + struct hal_ppdu_sts *ppdu_sts); + +#ifdef CONFIG_PCI_HCI +/** + * rtw_hal_query_rxch_num - query total hw rx dma channels number + * + * returns the number of hw rx dma channel + */ +u8 rtw_hal_query_rxch_num(void *hal); +#endif + +#endif /*_HAL_RX_H_*/ diff --git a/phl/hal_g6/hal_ser.c b/phl/hal_g6/hal_ser.c new file mode 100644 index 0000000..bda1227 --- /dev/null +++ b/phl/hal_g6/hal_ser.c @@ -0,0 +1,103 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_SER_C_ +#include "hal_headers.h" + +enum rtw_hal_status rtw_hal_ser_ctrl(void *hal, bool en) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + hstatus = rtw_hal_mac_ser_ctrl(hal_info, en); + + return hstatus; +} + +u32 +rtw_hal_ser_get_error_status(void *hal, u32 *err) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET; + + rtw_hal_mac_ser_get_error_status(hal_info, err); + + if ((*err == MAC_AX_ERR_L1_ERR_DMAC) || (*err == MAC_AX_ERR_L0_PROMOTE_TO_L1)) { + notify = RTW_PHL_SER_PAUSE_TRX; + } else if (*err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { + notify = RTW_PHL_SER_DO_RECOVERY; + } else if (*err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { + notify = RTW_PHL_SER_READY; + } else if (*err < MAC_AX_ERR_L0_PROMOTE_TO_L1) { + notify = RTW_PHL_SER_L0_RESET; + } else if (*err == MAC_AX_DUMP_SHAREBUFF_INDICATOR) { + notify = RTW_PHL_SER_DUMP_FW_LOG; + } else if (*err == MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC) { + notify = RTW_PHL_SER_LOG_ONLY; + } else if ((*err == MAC_AX_ERR_L1_PROMOTE_TO_L2) || + ((*err >= MAC_AX_ERR_L2_ERR_AH_DMA) && (*err <= MAC_AX_GET_ERR_MAX))) { + notify = RTW_PHL_SER_L2_RESET; + } + + return notify; +} + +enum rtw_hal_status rtw_hal_ser_set_error_status(void *hal, u32 err) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_ser_set_error_status(hal_info, err); +} + +enum rtw_hal_status rtw_hal_trigger_cmac_err(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_trigger_cmac_err(hal_info); +} + +enum rtw_hal_status rtw_hal_trigger_dmac_err(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_trigger_dmac_err(hal_info); +} + +enum rtw_hal_status rtw_hal_lv1_rcvy(void *hal, u32 step) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> rtw_hal_lv1_rcvy step %d\n", step); + status = rtw_hal_mac_lv1_rcvy(hal_info, step); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== rtw_hal_lv1_rcvy step %d, status 0x%x\n", step, status); + + return status; +} + +void rtw_hal_dump_fw_rsvd_ple(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u32 mac_err; + mac_err = rtw_hal_mac_dump_fw_rsvd_ple(hal_info); +} + +void +rtw_hal_ser_reset_wdt_intr(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u32 mac_err; + mac_err = rtw_hal_mac_ser_reset_wdt_intr(hal_info); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "rtw_hal_ser_reset_wdt_intr status 0x%x\n",mac_err); +} diff --git a/phl/hal_g6/hal_ser.h b/phl/hal_g6/hal_ser.h new file mode 100644 index 0000000..3e16703 --- /dev/null +++ b/phl/hal_g6/hal_ser.h @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_SER_H_ +#define _HAL_SER_H_ + +#endif /* _HAL_SER_H_ */ diff --git a/phl/hal_g6/hal_sound.c b/phl/hal_g6/hal_sound.c new file mode 100644 index 0000000..3261c71 --- /dev/null +++ b/phl/hal_g6/hal_sound.c @@ -0,0 +1,1025 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_SOUND_C_ + +#include "hal_headers.h" + +struct csi_rpt_na { + u8 nr; + u8 nc; + u8 na; +}; + +#define CSI_NA_MATRIX_SIZE 35 +static const struct csi_rpt_na csi_na[CSI_NA_MATRIX_SIZE] = +{ + {2, 1, 2}, {2, 2, 2}, + {3, 1, 4}, {3, 2, 6}, {3, 3, 6}, + {4, 1, 6}, {4, 2, 10}, {4, 3, 12}, {4, 4, 12}, + {5, 1, 8}, {5, 2, 14}, {5, 3, 18}, {5, 4, 20}, {5, 5, 20}, + {6, 1, 10}, {6, 2, 18}, {6, 3, 24}, {6, 4, 28}, {6, 5, 30}, + {6, 6, 30}, + {7, 1, 12}, {7, 2, 22}, {7, 3, 30}, {7, 4, 36}, + {7, 5, 40}, {7, 6, 42}, {7, 7, 42}, + {8, 1, 14}, {8, 2, 26}, {8, 3, 36}, {8, 4, 55}, + {8, 5, 50}, {8, 6, 54}, {8, 7, 56}, {8, 8, 56} +}; + + +u32 _cal_he_csi_size(u8 mu, enum channel_width bw, u8 nr, u8 nc, u8 ng, u8 cb) +{ + u8 na = 0; + u8 ns = 0; + u8 i = 0; + u32 csi_size = 0; + u8 cb_s = 0; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "%s : mu(%d) ; bw(%d) ; nr(%d) ; nc(%d), ng(%d), cb(%d)\n", + __func__, mu, bw, nr, nc, ng ,cb); + do { + if (CHANNEL_WIDTH_80 == bw) + ns = (ng == 4) ? 250 : 64; + else if(CHANNEL_WIDTH_40 == bw) + ns = (ng == 4) ? 122 : 32; + else if(CHANNEL_WIDTH_20 == bw) + ns = (ng == 4) ? 64 : 20; + else + break; + + for (i = 0; i < CSI_NA_MATRIX_SIZE; i++) { + if ((nr == csi_na[i].nr) && (nc ==csi_na[i].nc)) { + na = csi_na[i].na; + break; + } + } + if (na == 0) + break; + + if (cb) { + if(mu) + cb_s = 8; + else + cb_s = 5; + } else { + if(mu) + cb_s = 6; + else + cb_s = 3; + } + } while(0); + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "%s : na %d ; ns %d ; cb_s %d",__func__, na, ns, cb_s); + + if ((0 != na) && (0 != ns) && (0 != cb_s)) { + csi_size = ((8 * (u32)nc) + + ((u32)na * (u32)cb_s * (u32)ns)) / 8; + if(mu) + csi_size += (4 * (u32)nc * (u32)ns) / 8; + } + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, + "%s : expected he csi report size = %d byte", + __func__, csi_size); + return csi_size; +} + +u32 _cal_he_cqi_only_rpt_size(enum channel_width bw, u8 nc) +{ + u32 ret = 0; + if (CHANNEL_WIDTH_80 == bw) + ret = (u32)nc * 37; + else if(CHANNEL_WIDTH_40 == bw) + ret = (u32)nc * 18; + else if(CHANNEL_WIDTH_20 == bw) + ret = (u32)nc * 9; + + return ret; +} + +/*1. BF Resource Related*/ +u8 _get_bw_ru_end_idx(enum channel_width bw) { + u8 ru_end_idx = 0; + + switch (bw) { + case CHANNEL_WIDTH_20: + ru_end_idx = HAL_NPDA_RU_IDX_END_20MHZ; + break; + case CHANNEL_WIDTH_40: + ru_end_idx = HAL_NPDA_RU_IDX_END_40MHZ; + break; + case CHANNEL_WIDTH_80: + ru_end_idx = HAL_NPDA_RU_IDX_END_80MHZ; + break; + case CHANNEL_WIDTH_160: + case CHANNEL_WIDTH_80_80: + ru_end_idx = HAL_NPDA_RU_IDX_END_160MHZ; + default: + break; + } + return ru_end_idx; +} + +void _hal_snd_set_default_var(struct hal_snd_obj *snd_obj) +{ + snd_obj->ndpa_xpara.bw = CHANNEL_WIDTH_20; + snd_obj->ndpa_xpara.rate = RTW_DATA_RATE_OFDM6; + snd_obj->ndpa_xpara.gi_ltf = RTW_GILTF_LGI_4XHE32; + snd_obj->ndpa_xpara.stbc = 0; + snd_obj->ndpa_xpara.ldpc = 0; + + snd_obj->bfrp_xpara.bw = CHANNEL_WIDTH_20; + snd_obj->bfrp_xpara.rate = RTW_DATA_RATE_OFDM6; + snd_obj->bfrp_xpara.gi_ltf = RTW_GILTF_LGI_4XHE32; + snd_obj->bfrp_xpara.stbc = 0; + snd_obj->bfrp_xpara.ldpc = 0; +} + +enum rtw_hal_status +hal_snd_obj_init(void *hal) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct hal_snd_obj *snd_obj = NULL; + + do { + hal_com->snd_obj = _os_mem_alloc(hal_to_drvpriv(hal_info), + sizeof(struct hal_snd_obj)); + if (NULL == hal_com->snd_obj) { + break; + } + snd_obj = hal_com->snd_obj; + /* preset hal sounding default values */ + _hal_snd_set_default_var(snd_obj); + + hstatus = RTW_HAL_STATUS_SUCCESS; + } while (0); + return hstatus; +} + + +enum rtw_hal_status +hal_snd_obj_deinit(void *hal) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + do { + if (hal_com->snd_obj == NULL) + break; + _os_mem_free(hal_to_drvpriv(hal_info), hal_com->snd_obj, + sizeof(struct hal_snd_obj)); + hal_com->snd_obj = NULL; + } while (0); + + return hstatus; +} + +/** + * rtw_hal_snd_release_proc_sta_res + * free the resource for a STA used in sounding process + * input: + * @hal: (struct hal_info_t *) + * @sta: (struct rtw_phl_stainfo_t *) + **/ +enum rtw_hal_status +rtw_hal_snd_release_proc_sta_res(void *hal, struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta; + do { + if (hal_sta->bf_entry != NULL) { + hal_status = hal_bf_release_target_bf_entry( + hal_info, hal_sta->bf_entry); + } + + if (hal_is_csi_buf_valid(hal_info, &hal_sta->bf_csi_buf)) { + hal_status = hal_csi_release_csi_buf( + hal_info, &hal_sta->bf_csi_buf); + } + if (hal_is_csi_buf_valid(hal_info, &hal_sta->bf_csi_buf_swap)) { + hal_status = hal_csi_release_csi_buf( + hal_info, &hal_sta->bf_csi_buf_swap); + } + } while(0); + + return hal_status; +} + + +/** + * rtw_hal_snd_query_proc_sta_res + * input: + * @hal: hal_info + * @sta: rtw_phl_stainfo_t + * @mu: is this MU-MIMO STA resource request + * @bw: enum channel_width sounding bandwidth + **/ +enum rtw_hal_status +rtw_hal_snd_query_proc_sta_res( + void *hal, + struct rtw_phl_stainfo_t *sta, + bool mu, + enum channel_width bw, + bool en_swap) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta; + + do { + if (hal_sta->bf_entry != NULL) { + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[WARNING] sta->bf_entry != NULL\n"); + /* TODO:Shall Release First ?*/ + /* rtw_hal_snd_release_proc_sta_res(hal, sta); */ + } + + hal_sta->bf_entry = + (void *)hal_bf_query_idle_bf_entry(hal_info, mu); + + if (hal_sta->bf_entry == NULL) + break; + + hal_status = hal_csi_query_idle_csi_buf( + hal_info, mu, bw, &hal_sta->bf_csi_buf); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) + break; + + if (mu && en_swap) { + hal_status = hal_csi_query_idle_csi_buf( + hal_info, mu, bw, &hal_sta->bf_csi_buf_swap); + } + if (hal_status == RTW_HAL_STATUS_FAILURE) { + PHL_INFO("Cannot Enable Swap Mode! Because of the CSI resource is not enougth.\n"); + break; + } + + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta->bf_csi_buf 0x%x \n", + hal_sta->bf_csi_buf); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta->bf_csi_buf_swap 0x%x \n", + hal_sta->bf_csi_buf_swap); + + /* Set STA-INFO info to BF Entry */ + hal_status = hal_bf_cfg_swbf_entry(sta, en_swap); + } while (0); + + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_INFO("rtw_hal_snd_query_proc_sta_res FAIL \n"); + rtw_hal_snd_release_proc_sta_res(hal, sta); + } + + return hal_status; +} + +/** + * rtw_hal_snd_proc_pre_cfg_sta + * hw preconfiguration for a sounding sta + * input: + * @hal: hal_info + * @sta: (struct rtw_phl_stainfo_t *) + **/ +enum rtw_hal_status +rtw_hal_snd_proc_pre_cfg_sta( + void *hal, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta; + + /* 1. MAC HW BF Entry Settings */ + hal_status = hal_bf_set_entry_hwcfg( + hal_info, hal_sta->bf_entry); + + /* 2. Add other HAL setting here */ + /*TODO:*/ + + return hal_status; +} + + +/** + * rtw_hal_snd_proc_post_cfg + * hw/fw post configuration for a sounding event + * input: + * @hal: hal_info + **/ +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg(void *hal, bool he, bool mu, bool en_fixed_mode) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_mu_score_tbl *hal_score_table = &hal_info->hal_com->bb_mu_score_tbl; + if (mu) { + /*1. MU Score Board */ + hal_status = rtw_hal_mac_ax_set_mu_table_whole( + hal_info->mac, hal_score_table); + + /*2. (optional) MU Fixed Mode */ + if (en_fixed_mode) + hal_status = rtw_hal_bf_set_fix_mode(hal, mu, he); + } + + return hal_status; +} + + +/** + * rtw_hal_snd_proc_post_cfg_gid + * hw/fw post configuration for a vht/he gid + * input: + * @hal: hal_info + * @gid: wifi protolcol gid (PLCP) for configuration + * @ba_info: pointer of struct rtw_hal_muba_info + **/ +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg_gid(void *hal, u8 gid, void *ba_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + /* + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct rtw_hal_muba_info *hal_ba_info = (struct rtw_hal_muba_info *)ba_info; + */ + + /*TODO:*/ + /*1. MU BAR Table : Table ID = GID, GID = STA-x + sSTA-y*/ + return hal_status; +} + +/** + * rtw_hal_snd_proc_post_cfg_sta + * hw/fw post configuration for a single sounding sta + * input: + * @hal: hal_info + * @sta: (struct rtw_phl_stainfo_t *) + **/ +enum rtw_hal_status +rtw_hal_snd_proc_post_cfg_sta( + void *hal, + struct rtw_phl_stainfo_t *sta, + bool mu) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + /* MAC/FW Settings */ + if (mu) { + /*1. FW MU STA Update */ + hal_status = hal_bf_set_mu_sta_fw(hal, sta); + /*2. MU Score Board */ + /* mac->mac_set_mu_table_single_sta */ + } + + /* BB/FW Settings */ + /*TODO:*/ + + /* 2. Add other setting here */ + /*TODO:*/ + + return hal_status; +} + +/** + * rtw_hal_snd_mac_ctrl + * control sounding process : pause or start. + * @hal: hal_info + * @band: band0 / band1 + * @ctrl: 0 = pause souning / 1 = start sounding + **/ +enum rtw_hal_status +rtw_hal_snd_mac_ctrl(void *hal, u8 band, u8 ctrl) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + hstatus = rtw_hal_mac_ax_hw_snd_control(hal_info->mac, band, ctrl); + + return hstatus; +} + +/** + * rtw_hal_snd_chk_bf_res + * check the sta's sounding resource is enough for sounding + * input : + * @hal: hal_info + * @sta: (struct rtw_hal_stainfo_t *) + * @mu: true = mu / false = su + * @bw: enum channel_width + * return : + * @hstatus: RTW_HAL_STATUS_FAILURE = need release and query bf entry and CSI buffer + * RTW_HAL_STATUS_SUCCESS = STA's BF Entry and CSI Buffer is same to condition. + **/ +enum rtw_hal_status +rtw_hal_snd_chk_bf_res(void *hal, struct rtw_phl_stainfo_t *sta, + bool mu, enum channel_width bw) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta; + do { + if (sta == NULL) + break; + + if (false == rtw_hal_bf_chk_bf_type(hal, sta, mu)) + break; + if (mu != rtw_hal_get_csi_buf_type(&hal_sta->bf_csi_buf)) + break; + if (bw != rtw_hal_get_csi_buf_bw(&hal_sta->bf_csi_buf)) + break; + + hstatus = RTW_HAL_STATUS_SUCCESS; + } while (0); + + return hstatus; +} + +/** + * rtw_hal_snd_polling_snd_sts + * update the sta's sounding status into sta->hal_sta->bf_entry->bfee + * input : + * @hal: hal_info + * @sta: (struct rtw_hal_stainfo_t *) + **/ +void +rtw_hal_snd_polling_snd_sts(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + do { + if (sta == NULL) + break; + + hal_bf_update_entry_snd_sts(hal_info, sta->hal_sta->bf_entry); + + } while (0); +} + +/* SND H2C CMD related functions */ +void +rtw_hal_snd_ndpa_sta_info_vht(struct rtw_phl_stainfo_t *psta_info, + u32 *ndpa, u8 mu) +{ + struct hal_vht_ndpa_sta_info *ndpa_sta = + (struct hal_vht_ndpa_sta_info *)ndpa; + if (PHL_RTYPE_STATION == psta_info->wrole->type) + ndpa_sta->aid12 = 0; /* Target is an AP, AID = 0 */ + else + ndpa_sta->aid12 = psta_info->aid; + ndpa_sta->feedback_type = (mu == 0) ? HAL_NPDA_AC_SU : HAL_NPDA_AC_MU; + /* Nc shall alwary <= Nr */ + if (psta_info->asoc_cap.max_nc > + psta_info->wrole->proto_role_cap.num_snd_dim) { + ndpa_sta->nc = psta_info->wrole->proto_role_cap.num_snd_dim; + } else { + ndpa_sta->nc = psta_info->asoc_cap.max_nc; + } + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "vht ndpa_sta aid12 0x%x ; fb 0x%x ; nc 0x%x\n", + ndpa_sta->aid12, ndpa_sta->feedback_type, ndpa_sta->nc); +} + +void +rtw_hal_snd_ndpa_sta_info_he(struct rtw_phl_stainfo_t *psta_info, + u32 *ndpa, enum channel_width bw, u8 fb_type) +{ + + struct hal_he_ndpa_sta_info *ndpa_sta = + (struct hal_he_ndpa_sta_info *)ndpa; + u16 ru_start = HAL_NPDA_RU_IDX_START; + u16 ru_end = _get_bw_ru_end_idx(bw); + + if (PHL_RTYPE_STATION == psta_info->wrole->type) + ndpa_sta->aid = 0; /* Target is and AP, AID = 0 */ + else + ndpa_sta->aid = (psta_info->aid&0x7FF); + ndpa_sta->bw = ((ru_start&0x7F) << 0) | ((ru_end&0x7F) << 7); + if (0 == fb_type) { + ndpa_sta->fb_ng = psta_info->asoc_cap.ng_16_su_fb ? + HAL_NDPA_AX_FB_SU_NG_16 : HAL_NDPA_AX_FB_SU_NG_4; + ndpa_sta->cb = psta_info->asoc_cap.cb_sz_su_fb ? + HAL_NPDA_AX_CB_SU42_MU75 : HAL_NPDA_AX_CB_SU64_MU97; + } else if (1 == fb_type) { + ndpa_sta->fb_ng = psta_info->asoc_cap.ng_16_mu_fb ? + HAL_NDPA_AX_FB_MU_NG_16 : HAL_NDPA_AX_FB_MU_NG_4; + ndpa_sta->cb = psta_info->asoc_cap.cb_sz_mu_fb ? + HAL_NPDA_AX_CB_SU42_MU75 : HAL_NPDA_AX_CB_SU64_MU97; + } else { + ndpa_sta->fb_ng = HAL_NDPA_AX_FB_CQI; + ndpa_sta->cb = 1; + } + ndpa_sta->disambiguation = 1; + /* Nc shall alwary <= Nr */ + if (psta_info->asoc_cap.max_nc > + psta_info->wrole->proto_role_cap.num_snd_dim) { + ndpa_sta->nc = psta_info->wrole->proto_role_cap.num_snd_dim; + } else { + ndpa_sta->nc = psta_info->asoc_cap.max_nc; + } + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE NDPA : aid 0x%x fb_ng 0x%x cb 0x%x nc 0x%x \n", + ndpa_sta->aid, ndpa_sta->fb_ng, ndpa_sta->cb, ndpa_sta->nc); +} + + +/** + * rtw_hal_snd_set_fw_cmd_dialogtkn() + * Set cmd dialog token value in NDPA + * input + * @he: is NDPA HE or not(VHT). + * @token: dialog token value. + **/ +void rtw_hal_snd_set_fw_cmd_dialogtkn(void *hal, u8 *buf, u8 he, u8 token) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + + cmd->ndpa.snd_dialog.he = he; + cmd->ndpa.snd_dialog.token = token; +} + +/** + * rtw_hal_snd_vht_fwcmd_su() + * Prepared VHT SU Sounding Fw Cmd. + * @hal: + * @buf: (struct hal_ax_fwcmd_snd *) cmd buffer pointer. + * @psta: (struct rtw_phl_stainfo_t *) STA to be sounding. + * @npda_sta: NPDA sta_info value + **/ +void rtw_hal_snd_vht_fwcmd_su(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u32 *npda_sta) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_snd_obj *snd_obj = + (struct hal_snd_obj *)hal_info->hal_com->snd_obj; + u8 i = 0; + + cmd->frame_ex_type = HAL_FEXG_TYPE_AC_SU; + cmd->macid[0] = psta->macid; + cmd->ndpa.common.frame_ctl = HAL_SND_VHT_NDPA_FRM_CTRL; /*TODO*/ + for (i = 0; i < 6;i++) { + cmd->ndpa.common.addr1[i] = psta->mac_addr[i]; /* NDPA-RA*/ + cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/ + } + cmd->ndpa.common.duration = 100; + cmd->ndpa.ndpa_sta_info[0] = *npda_sta; + /* NDPA WD */ + cmd->wd[0].txpktsize = 21;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */ + cmd->wd[0].ndpa_duration = 100; + cmd->wd[0].disdatafb = 1; + cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate; + cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw; + cmd->wd[0].macid = psta->macid; + cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf; + cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc; + cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc; + cmd->wd[0].sifs_tx = 1; + cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_UST_NDPA;/* unicast ndpa */ + cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_VHT; + /* NDP WD */ + cmd->wd[1].disdatafb = 1; + if (1 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0; + else if (2 ==psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS3_MCS0; + else if (3 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS4_MCS0; + else + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "psta->asoc_cap.nss_rx = 0x%x\n", psta->asoc_cap.nss_rx); + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "cmd->wd[1].datarate = 0x%x\n", cmd->wd[1].datarate); + cmd->wd[1].data_bw = bw; + cmd->wd[1].macid = psta->macid; + cmd->wd[1].gi_ltf = RTW_GILTF_LGI_4XHE32; + cmd->wd[1].sifs_tx = 0; + cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_NDP; + cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_VHT; +} + +void rtw_hal_snd_vht_fwcmd_mu_add_sta(void *hal, u8 *buf, u32 *ndpa_sta, + struct rtw_phl_stainfo_t *sta, + u8 ndpa_idx, u8 last) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_snd_obj *snd_obj = + (struct hal_snd_obj *)hal_info->hal_com->snd_obj; + u8 i = 0; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_snd_vht_fwcmd_mu_add_sta\n"); + + if (ndpa_idx >= HAL_MAX_VHT_SND_STA_NUM) + return; + + cmd->macid[ndpa_idx] = sta->macid; + /* NDPA sta_info*/ + cmd->ndpa.ndpa_sta_info[ndpa_idx] = *ndpa_sta; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac id 0x%x ; ndpa sta_info 0x%x\n", + cmd->macid[ndpa_idx], cmd->ndpa.ndpa_sta_info[ndpa_idx]); + + /* VHT BFRP */ + cmd->bfrp.hdr[ndpa_idx - 1].frame_ctl = HAL_SND_VHT_BFRP_FRM_CTRL; + cmd->bfrp.hdr[ndpa_idx - 1].duration = 100; + for (i = 0; i < 6; i++) { + cmd->bfrp.hdr[ndpa_idx - 1].addr1[i] = sta->mac_addr[i]; /* NDPA-RA = Broadcast*/ + cmd->bfrp.hdr[ndpa_idx - 1].addr2[i] = sta->wrole->mac_addr[i]; /* NDPA-TA*/ + } + cmd->bfrp.vht_para[ndpa_idx - 1].rexmit_bmp = 0; + /*BFRP WD*/ + cmd->wd[1 + ndpa_idx].txpktsize = 17; /* 2 + 2 + 6 + 6 + 1 */ + cmd->wd[1 + ndpa_idx].ndpa_duration = 100; + cmd->wd[1 + ndpa_idx].datarate = snd_obj->bfrp_xpara.rate; + cmd->wd[1 + ndpa_idx].data_ldpc = snd_obj->bfrp_xpara.ldpc; + cmd->wd[1 + ndpa_idx].data_stbc = snd_obj->bfrp_xpara.stbc; + cmd->wd[1 + ndpa_idx].macid = sta->macid; + cmd->wd[1 + ndpa_idx].data_bw = snd_obj->bfrp_xpara.bw; + cmd->wd[1 + ndpa_idx].gi_ltf = snd_obj->bfrp_xpara.gi_ltf; + cmd->wd[1 + ndpa_idx].disdatafb = 1; + if(last) { + cmd->wd[1 + ndpa_idx].sifs_tx = 0; + cmd->wd[1 + ndpa_idx].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP;/* Final BFRP */ + } else { + cmd->wd[1 + ndpa_idx].sifs_tx = 1; + cmd->wd[1 + ndpa_idx].snd_pkt_sel = HAL_SND_PKT_SEL_MID_BFRP; + } + cmd->wd[1 + ndpa_idx].ndpa = HAL_SND_PKT_NDPA_VHT; + +} + +void rtw_hal_snd_vht_fwcmd_mu_pri(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u8 sta_nr, u32 *ndpa_sta) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_snd_obj *snd_obj = + (struct hal_snd_obj *)hal_info->hal_com->snd_obj; + u8 i = 0; + + if (sta_nr == 4) + cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_3; + else if(sta_nr == 3) + cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_2; + else if(sta_nr == 2) + cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_1; + else + PHL_INFO("rtw_hal_snd_vht_fwcmd_mu_pri : ERROR!!!!!!!!!!!!!!!"); + cmd->macid[0] = psta->macid; + + /* NDPA */ + cmd->ndpa.common.frame_ctl = HAL_SND_VHT_NDPA_FRM_CTRL; + for (i = 0; i < 6;i++) { + /** + * Addr1: In VHT Case, Fill User_0's MAC Address to match BF Entry, + * HW will auto re-fill to Broadcast Address + **/ + cmd->ndpa.common.addr1[i] = psta->mac_addr[i]; + cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/ + } + cmd->ndpa.common.duration = 150;/*TODO:*/ + /* primary sta ndpa sta_info*/ + cmd->ndpa.ndpa_sta_info[0] = *ndpa_sta; + + /* VHT BFRP ==> by STA */ + + /* NDPA WD */ + cmd->wd[0].txpktsize = 17 + HAL_SND_VHT_NDPA_STA_SZ * sta_nr;/* 2 + 2 + 6 + 6 + 1 + 2, NO FCS */ + cmd->wd[0].ndpa_duration = 150; + cmd->wd[0].disdatafb = 1; + cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate; + cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw; + cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc; + cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc; + cmd->wd[0].macid = psta->macid; + cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf; + cmd->wd[0].sifs_tx = 1; + cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_BST_NDPA; + cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_VHT; + /* NDP WD */ + cmd->wd[1].disdatafb = 1; + if (1 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0; + else if (2 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS3_MCS0; + else if (3 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS4_MCS0; + else + cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0; + cmd->wd[1].data_bw = bw; + cmd->wd[1].macid = psta->macid; + cmd->wd[1].gi_ltf = RTW_GILTF_LGI_4XHE32; + cmd->wd[1].sifs_tx = 1; + cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_MID_NDP;/*Last NDP*/ + cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_VHT; +} + +/* HE FW Command */ +/** + * rtw_hal_snd_ax_fwcmd_su() + * fill the fw cmd for HE sounding type HE Non-TB : NDPA - NDP - CSI Report + * + **/ +void rtw_hal_snd_ax_fwcmd_nontb(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u32 *npda_sta) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_snd_obj *snd_obj = + (struct hal_snd_obj *)hal_info->hal_com->snd_obj; + u8 i = 0; + + cmd->frame_ex_type = HAL_FEXG_TYPE_AX_SU; + cmd->macid[0] = psta->macid; + cmd->ndpa.common.frame_ctl = HAL_SND_HE_NDPA_FRM_CTRL; + for (i = 0; i < 6;i++) { + cmd->ndpa.common.addr1[i] = psta->mac_addr[i]; /* NDPA-RA*/ + cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/ + } + cmd->ndpa.common.duration = 100; + cmd->ndpa.ndpa_sta_info[0] = *npda_sta; + /* NDPA WD */ + cmd->wd[0].txpktsize = 21;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */ + cmd->wd[0].ndpa_duration = 100; + cmd->wd[0].disdatafb = 1; + cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate; + cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw; + cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc; + cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc; + cmd->wd[0].macid = psta->macid; + cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf; + cmd->wd[0].sifs_tx = 1; + cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_UST_NDPA;/*unicast ndpa*/ + cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_HE; + /* NDP WD */ + cmd->wd[1].disdatafb = 1; + if (1 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0; + else if (2 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS3_MCS0; + else if (3 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS4_MCS0; + else + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0; + cmd->wd[1].data_bw = bw; + cmd->wd[1].macid = psta->macid; + cmd->wd[1].gi_ltf = RTW_GILTF_2XHE16; /* TODO: if psta->asoc_cap.ltf_gi support NDP 4XHE32;*/ + cmd->wd[1].sifs_tx = 0; + cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_NDP; + cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_HE; +} + +/** + * rtw_hal_snd_ax_fwcmd_tb_add_sta() + * fill fw cmd for HE sounding with TB case. + * shall call rtw_hal_snd_ax_fwcmd_tb_pri() first, and add STA by this api. + * Note that RU-Allocation shall dicide from phl caller, + * and shall avoid same with others + * function input: + * @hal: + * @buf: (struct hal_ax_fwcmd_snd *) command buf pointer. + * @ndpa_sta: + * @sta: (struct rtw_phl_stainfo_t *) + * @ru_idx: RU Allocation index; + * @ndpa_idx: 0-7 for 8852a + * @bfrp_idx: 0-1 for 8852a + * @bfrp_u_idx: 0-3 for 8852a + **/ +void rtw_hal_snd_ax_fwcmd_tb_add_sta(void *hal, u8 *buf, u32 *ndpa_sta, + struct rtw_phl_stainfo_t *sta, u8 ru_idx, + u8 ndpa_idx, u8 bfrp_idx, u8 bfrp_u_idx) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_he_ndpa_sta_info *ndpa = + (struct hal_he_ndpa_sta_info *)ndpa_sta; + u8 mu = 0, ng = 4; + u32 rpt_size = 0; + + if (ndpa_idx >= HAL_MAX_HE_SND_STA_NUM) + return; + if (bfrp_idx >= HAL_MAX_HE_BFRP_NUM) + return; + cmd->macid[ndpa_idx] = sta->macid; + /* NDPA sta_info*/ + cmd->ndpa.ndpa_sta_info[ndpa_idx] = *ndpa_sta; + /* BFRP user_info */ + cmd->bfrp.he_para[bfrp_idx].fbseg_rexmit_bmp[bfrp_u_idx] = 0; + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].aid12 = sta->aid; + if (cmd->bfrp.he_para[bfrp_idx].common.ul_bw > CHANNEL_WIDTH_80) { + ru_idx = (ru_idx << 1) | BIT(0); + } else { + ru_idx = (ru_idx << 1) &(~BIT(0)); + } + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ru_pos = ru_idx; + + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_fec_code = 0; + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_mcs = 3;/* HE-MCS3, TODO: Default value of golden */ + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_dcm = 0 ; + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ss_alloc = 0;/* 1SS, TODO: Default value of golden */ + cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_tgt_rssi = + (u8)(sta->hal_sta->rssi_stat.rssi >> 1);/*TODO: From Rx ST SU RSSI */ + if (ndpa->fb_ng == HAL_NDPA_AX_FB_MU_NG_4) { + mu = 1; + ng = 4; + } else if (ndpa->fb_ng == HAL_NDPA_AX_FB_MU_NG_16) { + mu = 1; + ng = 16; + } else if (ndpa->fb_ng == HAL_NDPA_AX_FB_SU_NG_4) { + mu = 0; + ng = 4; + } else if (ndpa->fb_ng == HAL_NDPA_AX_FB_SU_NG_16) { + mu = 0; + ng = 4; + } + rpt_size = _cal_he_csi_size(mu, sta->chandef.bw, + (sta->wrole->proto_role_cap.num_snd_dim + 1), + ((u8)ndpa->nc + 1), ng, (u8)ndpa->cb); + if (cmd->bfrp.he_para[bfrp_idx].f2p_info.csi_len_bfrp < (rpt_size/64)) + cmd->bfrp.he_para[bfrp_idx].f2p_info.csi_len_bfrp = + (u16)(rpt_size / 64); /*unit 64 byte*/ +} + +void rtw_hal_snd_ax_fwcmd_tb_pri(void *hal, u8 *buf, enum channel_width bw, + struct rtw_phl_stainfo_t *psta, u8 sta_nr1, u8 sta_nr2) +{ + struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_snd_obj *snd_obj = + (struct hal_snd_obj *)hal_info->hal_com->snd_obj; + u8 i = 0; + u8 sta_nr = sta_nr1 + sta_nr2; + + if (sta_nr2 != 0) + cmd->frame_ex_type = HAL_FEXG_TYPE_AX_MU_2; + else + cmd->frame_ex_type = HAL_FEXG_TYPE_AX_MU_1; + cmd->bfrp0_sta_nr = sta_nr1; + cmd->bfrp1_sta_nr = sta_nr2; + cmd->macid[0] = psta->macid; + + /* NDPA */ + cmd->ndpa.common.frame_ctl = HAL_SND_HE_NDPA_FRM_CTRL; /*TODO:*/ + for (i = 0; i < 6;i++) { + cmd->ndpa.common.addr1[i] = 0xFF; /* NDPA-RA = Broadcast*/ + cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/ + /* BFRP - 1*/ + cmd->bfrp.hdr[0].addr1[i] = 0xFF; + cmd->bfrp.hdr[0].addr2[i] = psta->wrole->mac_addr[i]; + if (sta_nr2 != 0) { + /* BFRP - 2*/ + cmd->bfrp.hdr[1].addr1[i] = 0xFF; + cmd->bfrp.hdr[1].addr2[i] = psta->wrole->mac_addr[i]; + } + } + cmd->ndpa.common.duration = 150;/*TODO:*/ + /*TODO: ndpa user info in other api */ + + /* BFRP #1 */ + cmd->bfrp.hdr[0].frame_ctl = HAL_SND_HE_BFRP_FRM_CTRL; /* Trigger Frame */ + cmd->bfrp.hdr[0].duration = 100; + cmd->bfrp.he_para[0].common.tgr_info = HAL_SND_TRIG_INFO_BFRP;/*BFRP*/ + cmd->bfrp.he_para[0].common.ul_len = 0xFFF;/*TODO: LSIG Length : sw provide or fw calculate */ + cmd->bfrp.he_para[0].common.more_tf = 0; + cmd->bfrp.he_para[0].common.cs_rqd = 1; + cmd->bfrp.he_para[0].common.ul_bw = bw; + cmd->bfrp.he_para[0].common.gi_ltf = RTW_TB_GILTF_4XHE32;/* 8852A Limitation of UL OFDMA */ + cmd->bfrp.he_para[0].common.num_heltf = 0;/* TODO: Default value of golden */ + cmd->bfrp.he_para[0].common.ul_pktext = 0;/* TODO: fw? hw? */ + cmd->bfrp.he_para[0].common.ap_tx_pwr = 0x3C;/* TODO: Default value of golden */ + + /* F2P cmd parameters */ + cmd->bfrp.he_para[0].f2p_info.tb_t_pe_bfrp = 2; + cmd->bfrp.he_para[0].f2p_info.tri_pad_bfrp = 2; + cmd->bfrp.he_para[0].f2p_info.ul_cqi_rpt_tri_bfrp = 0; + cmd->bfrp.he_para[0].f2p_info.rf_gain_idx_bfrp = 0;/* ?? */ + cmd->bfrp.he_para[0].f2p_info.fix_gain_en_bfrp = 0;/* ?? */ + + if (sta_nr2) { + cmd->bfrp.hdr[1].frame_ctl = HAL_SND_HE_BFRP_FRM_CTRL; /* Trigger Frame */ + cmd->bfrp.hdr[1].duration = 100; + cmd->bfrp.he_para[1].common.tgr_info = HAL_SND_TRIG_INFO_BFRP;/*BFRP*/ + cmd->bfrp.he_para[1].common.ul_len = 0xFFF;/*TODO: LSIG Length : sw provide or fw calculate */ + cmd->bfrp.he_para[1].common.more_tf = 0; + cmd->bfrp.he_para[1].common.cs_rqd = 1; + cmd->bfrp.he_para[1].common.ul_bw = bw; + cmd->bfrp.he_para[1].common.gi_ltf = RTW_TB_GILTF_4XHE32;/* 8852A Limitation of UL OFDMA */ + cmd->bfrp.he_para[1].common.num_heltf = 0;/* TODO: Default value of golden */ + cmd->bfrp.he_para[1].common.ul_pktext = 0;/* TODO: fw? hw? */ + cmd->bfrp.he_para[1].common.ap_tx_pwr = 0x32;/* TODO: Default value of golden */ + + cmd->bfrp.he_para[1].f2p_info.tb_t_pe_bfrp = 2; + cmd->bfrp.he_para[1].f2p_info.tri_pad_bfrp = 2; + cmd->bfrp.he_para[1].f2p_info.ul_cqi_rpt_tri_bfrp = 0; + cmd->bfrp.he_para[1].f2p_info.rf_gain_idx_bfrp = 0; + cmd->bfrp.he_para[1].f2p_info.fix_gain_en_bfrp = 0; + } + /* NDPA WD */ + cmd->wd[0].txpktsize = 17 + HAL_SND_HE_NDPA_STA_SZ * sta_nr;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */ + cmd->wd[0].ndpa_duration = 100; + cmd->wd[0].disdatafb = 1; + cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate; + cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw; + cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc; + cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc; + cmd->wd[0].macid = psta->macid; + cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf; + cmd->wd[0].sifs_tx = 1; + cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_BST_NDPA; + cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_HE; + /* NDP WD */ + cmd->wd[1].disdatafb = 1; + if (1 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0; + else if (2 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS3_MCS0; + else if(3 == psta->wrole->proto_role_cap.num_snd_dim) + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS4_MCS0; + else + cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0; + cmd->wd[1].data_bw = bw; + cmd->wd[1].macid = psta->macid; + cmd->wd[1].gi_ltf = RTW_GILTF_2XHE16; /* TODO: if support 4x32 NDP */ + cmd->wd[1].sifs_tx = 0; + cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_MID_NDP; + cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_HE; + /* BFRP #1 WD */ + cmd->wd[2].txpktsize = 24 + HAL_SND_HE_BFRP_STA_SZ * sta_nr1; /* 2 + 2 + 6 + 6 + 8 + 5*N */ + cmd->wd[2].ndpa_duration = 100; + cmd->wd[2].datarate = snd_obj->bfrp_xpara.rate; + //cmd->wd[2].macid + cmd->wd[2].data_bw = snd_obj->bfrp_xpara.bw; + cmd->wd[2].data_stbc = snd_obj->bfrp_xpara.stbc; + cmd->wd[2].data_ldpc = snd_obj->bfrp_xpara.ldpc; + cmd->wd[2].gi_ltf = snd_obj->bfrp_xpara.gi_ltf; + cmd->wd[2].disdatafb = 1; + if(sta_nr2) { + cmd->wd[2].sifs_tx = 1; + cmd->wd[2].snd_pkt_sel = HAL_SND_PKT_SEL_MID_BFRP; + } else { + cmd->wd[2].sifs_tx = 0;/* Final BFRP */ + cmd->wd[2].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP; + } + cmd->wd[2].ndpa = HAL_SND_PKT_NDPA_HE; + if (sta_nr2) { + cmd->wd[3].txpktsize = 24 + HAL_SND_HE_BFRP_STA_SZ * sta_nr2; /* 2 + 2 + 6 + 6 + 8 + 5*N */ + cmd->wd[3].ndpa_duration = 100; + cmd->wd[3].datarate = snd_obj->bfrp_xpara.rate; + cmd->wd[3].data_bw = snd_obj->bfrp_xpara.bw; + cmd->wd[3].data_stbc = snd_obj->bfrp_xpara.stbc; + cmd->wd[3].data_ldpc = snd_obj->bfrp_xpara.ldpc; + cmd->wd[3].gi_ltf = snd_obj->bfrp_xpara.gi_ltf; + cmd->wd[3].disdatafb = 1; + cmd->wd[3].sifs_tx = 0;/* Final BFRP */ + cmd->wd[3].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP; + cmd->wd[3].ndpa = HAL_SND_PKT_NDPA_HE; + } +} + +u8 * +rtw_hal_snd_prepare_snd_cmd(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 *buf = NULL; + + buf = _os_mem_alloc(hal_to_drvpriv(hal_info), + sizeof(struct hal_ax_fwcmd_snd)); + + return buf; +} + + +enum rtw_hal_status +rtw_hal_snd_release_snd_cmd(void *hal, u8 *buf) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + do { + if (buf == NULL) + break; + _os_mem_free(hal_to_drvpriv(hal_info), buf, + sizeof(struct hal_ax_fwcmd_snd)); + } while (0); + + return hstatus; +} + + +enum rtw_hal_status +rtw_hal_snd_send_fw_cmd(void *hal, u8 *cmd) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_snd_send_fw_cmd \n"); + hstatus = hal_mac_ax_send_fw_snd(hal_info, + (struct hal_ax_fwcmd_snd *)cmd); + /*TODO: Dump CMD content */ + PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== rtw_hal_snd_send_fw_cmd \n"); + return hstatus; +} diff --git a/phl/hal_g6/hal_sound.h b/phl/hal_g6/hal_sound.h new file mode 100644 index 0000000..71afed9 --- /dev/null +++ b/phl/hal_g6/hal_sound.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_SOUND_H_ +#define _HAL_SOUND_H_ + +#define HAL_NPDA_RU_IDX_START 0 +#define HAL_NPDA_RU_IDX_END_20MHZ 8 +#define HAL_NPDA_RU_IDX_END_40MHZ 17 +#define HAL_NPDA_RU_IDX_END_80MHZ 36 +#define HAL_NPDA_RU_IDX_END_160MHZ 73 + +#define HAL_SND_HE_BFRP_STA_SZ 5 +#define HAL_SND_HE_NDPA_STA_SZ 4 +#define HAL_SND_VHT_NDPA_STA_SZ 2 + +#define HAL_SND_VHT_NDPA_FRM_CTRL 0x54 +#define HAL_SND_HE_NDPA_FRM_CTRL 0x54 +#define HAL_SND_VHT_BFRP_FRM_CTRL 0x44 +#define HAL_SND_HE_BFRP_FRM_CTRL 0x24 /* Trigger Frame */ + +#define HAL_SND_TRIG_INFO_BFRP 0x1 + +enum hal_snd_pkt_sel { + HAL_SND_PKT_SEL_UST_NDPA = 0, + HAL_SND_PKT_SEL_BST_NDPA =1, + HAL_SND_PKT_SEL_LAST_NDP = 2, + HAL_SND_PKT_SEL_MID_NDP = 3, + HAL_SND_PKT_SEL_MID_BFRP = 4, + HAL_SND_PKT_SEL_LAST_BFRP = 5, + HAL_SND_PKT_SEL_MAX +}; + +enum hal_snd_pkt_ndpa_type { + HAL_SND_PKT_NDPA_HT = 1, + HAL_SND_PKT_NDPA_VHT = 2, + HAL_SND_PKT_NDPA_HE = 3, + HAL_SND_PKT_NDPA_MAX +}; + + +struct hal_snd_pkt_xmit_para { + enum channel_width bw; + enum rtw_data_rate rate; + enum rtw_gi_ltf gi_ltf; + u8 stbc; + u8 ldpc; +}; + +struct hal_snd_obj { + struct hal_snd_pkt_xmit_para ndpa_xpara; + struct hal_snd_pkt_xmit_para bfrp_xpara; +}; + +enum rtw_hal_status hal_snd_obj_init(void *hal); +enum rtw_hal_status hal_snd_obj_deinit(void *hal); + +#endif diff --git a/phl/hal_g6/hal_sta.c b/phl/hal_g6/hal_sta.c new file mode 100644 index 0000000..f788820 --- /dev/null +++ b/phl/hal_g6/hal_sta.c @@ -0,0 +1,802 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_STA_C_ +#include "hal_headers.h" + +void +_hal_sta_rssi_init(struct rtw_phl_stainfo_t *sta) +{ + sta->hal_sta->rssi_stat.assoc_rssi = 0; + sta->hal_sta->rssi_stat.ma_rssi = 0; +} + +static enum rtw_hal_status +_hal_bfee_init(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct rtw_wifi_role_t *wrole = NULL; + bool enable_bfee = false; + + do { + if(NULL == sta) + break; + wrole = sta->wrole; + if(NULL == wrole) + break; + + /*only init BFee when wrole cap's bfee and sta cap 's bfer matched */ + + if ((wrole->proto_role_cap.he_su_bfme || + wrole->proto_role_cap.he_mu_bfme) && + (sta->asoc_cap.he_su_bfmr || sta->asoc_cap.he_mu_bfmr)) { + enable_bfee = true; + } + + if ((wrole->proto_role_cap.vht_su_bfme || + wrole->proto_role_cap.vht_mu_bfme) && + (sta->asoc_cap.vht_su_bfmr || sta->asoc_cap.vht_mu_bfmr)) { + enable_bfee = true; + } + + if (wrole->proto_role_cap.ht_su_bfme && + sta->asoc_cap.ht_su_bfmr) + enable_bfee = true; + + if (true == enable_bfee) { + /* BFee Functions */ + if (RTW_HAL_STATUS_SUCCESS != + hal_bf_hw_mac_init_bfee(hal_info, + sta->wrole->hw_band)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : Init HW MAC BFee Fail\n", + __func__); + break; + } + /* BFee CSI parameters*/ + hal_info->hal_com->csi_para_ctrl_sel = false; + if (RTW_HAL_STATUS_SUCCESS != + hal_bf_set_bfee_csi_para(hal_info, + hal_info->hal_com->csi_para_ctrl_sel, + sta)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : Set BFee CSI Para Fail\n", + __func__); + break; + } +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP + /* BB Workaround */ + rtw_hal_bb_dcr_en(hal_info, true); +#endif + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%s : Enable HW BFee Function Success\n", + __func__); + } + hstatus = RTW_HAL_STATUS_SUCCESS; + } while (0); + + return hstatus; +} + +static enum rtw_hal_status +_hal_set_default_cctrl_tbl(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_cctl_info cctrl, cctl_info_mask; +#ifdef RTW_WKARD_DEF_CMACTBL_CFG + u16 cfg; + enum rf_path path = (hal_info->hal_com->rfpath_tx_num == 1)?RF_PATH_B:RF_PATH_AB; +#endif + _os_mem_set(hal_to_drvpriv(hal_info), &cctrl, 0, sizeof(struct mac_ax_cctl_info)); + _os_mem_set(hal_to_drvpriv(hal_info), &cctl_info_mask, 0, sizeof(struct mac_ax_cctl_info)); + + if (NULL == sta) + goto out; + + cctrl.txpwr_mode = 0; + cctl_info_mask.txpwr_mode = 0x7; +#ifdef RTW_WKARD_DEF_CMACTBL_CFG + cfg = rtw_hal_bb_cfg_cmac_tx_ant(hal_info, path); + cctrl.ntx_path_en = cfg & 0x0f; + cctl_info_mask.ntx_path_en = 0xF; + cctrl.path_map_a = ((cfg>>4) & 0x03); + cctl_info_mask.path_map_a = 0x3; + cctrl.path_map_b = ((cfg>>6) & 0x03); + cctl_info_mask.path_map_b = 0x3; + cctrl.path_map_c = ((cfg>>8) & 0x03); + cctl_info_mask.path_map_c = 0x3; + cctrl.path_map_d = ((cfg>>10) & 0x03); + cctl_info_mask.path_map_d = 0x3; +#else + cctrl.ntx_path_en = 0x3; + cctl_info_mask.ntx_path_en = 0xF; + cctrl.path_map_a = 0x0; + cctl_info_mask.path_map_a = 0x3; + cctrl.path_map_b = 0x1; + cctl_info_mask.path_map_b = 0x3; + cctrl.path_map_c = 0x2; + cctl_info_mask.path_map_c = 0x3; + cctrl.path_map_d = 0x3; + cctl_info_mask.path_map_d = 0x3; +#endif + cctrl.antsel_a = 0x0; + cctl_info_mask.antsel_a = 0x1; + cctrl.antsel_b = 0x0; + cctl_info_mask.antsel_b = 0x1; + cctrl.antsel_c = 0x0; + cctl_info_mask.antsel_c = 0x1; + cctrl.antsel_d = 0x0; + cctl_info_mask.antsel_d = 0x1; + cctrl.doppler_ctrl = 0; + cctl_info_mask.doppler_ctrl = 0x3; + cctrl.txpwr_tolerence = 0; + cctl_info_mask.txpwr_tolerence = 0xF; + +#ifdef CONFIG_PHL_DEFAULT_MGNT_Q_RPT_EN + cctrl.mgq_rpt_en = 1; + cctl_info_mask.mgq_rpt_en = 1; +#endif + sts = rtw_hal_cmc_tbl_cfg(hal_info, &cctrl ,&cctl_info_mask, sta->macid); + +out: + return sts; +} + +static enum rtw_hal_status +_hal_update_cctrl_tbl(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct rtw_wifi_role_t *wrole = sta->wrole; + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_cctl_info cctrl, cctl_info_mask; + + _os_mem_set(hal_to_drvpriv(hal_info), &cctrl, 0, sizeof(struct mac_ax_cctl_info)); + _os_mem_set(hal_to_drvpriv(hal_info), &cctl_info_mask, 0, sizeof(struct mac_ax_cctl_info)); + + if (NULL == sta) + goto out; + + /*TODO - update cctrl tab from stainfo*/ + cctrl.disrtsfb = 1; + cctl_info_mask.disrtsfb = 1; + + cctrl.disdatafb = 1; + cctl_info_mask.disdatafb = 1; + + /* + if (!cctrl.disdatafb) + cctrl.arfr_ctrl = rtw_hal_bb_get_arfr_idx(hal_info, sta); + */ + + if (wrole->cap.rty_lmt_rts == 0xFF) { + cctrl.rts_txcnt_lmt_sel = 0; + } else { + cctrl.rts_txcnt_lmt_sel = 1; + cctrl.rts_txcnt_lmt = wrole->cap.rty_lmt_rts & 0xF; + cctl_info_mask.rts_txcnt_lmt = 0xF; + } + cctl_info_mask.rts_txcnt_lmt_sel = 1; + cctrl.rts_rty_lowest_rate = (sta->chandef.band == BAND_ON_24G) ? (RTW_DATA_RATE_CCK1) : (RTW_DATA_RATE_OFDM6); + cctl_info_mask.rts_rty_lowest_rate = 0xF; + + if (wrole->cap.rty_lmt == 0xFF) { + cctrl.data_txcnt_lmt_sel = 0; + } else { + cctrl.data_txcnt_lmt_sel = 1; + cctrl.data_tx_cnt_lmt = wrole->cap.rty_lmt & 0x3F; + cctl_info_mask.data_tx_cnt_lmt = 0x3F; + } + cctl_info_mask.data_txcnt_lmt_sel = 1; + + /* hana_todo: follow wd agg_num settings before updating cmac tbl while addba handshake is ready */ +/* cctrl.max_agg_num_sel = 1; + cctl_info_mask.max_agg_num_sel = 1; + + cctrl.max_agg_num = sta->asoc_cap.num_ampdu - 1; + cctl_info_mask.max_agg_num = 0xFF; +*/ + if (cctrl.max_agg_num > 0x3F) { + cctrl.ba_bmap = 1; + cctl_info_mask.ba_bmap = 0x3; + } + + if (sta->wrole->type == PHL_RTYPE_STATION || sta->wrole->type == PHL_RTYPE_TDLS) { + cctrl.uldl = 1; + cctl_info_mask.uldl = 1; + } else { + cctrl.uldl = 0; + cctl_info_mask.uldl = 1; + } + + cctrl.multi_port_id = sta->wrole->hw_port; + cctl_info_mask.multi_port_id = 0x7; + + if (sta->wrole->type == PHL_RTYPE_AP) { + cctrl.data_dcm = 0; /*(sta->asoc_cap.dcm_max_const_rx > 0)*/ + cctl_info_mask.data_dcm = 1; + } + + if (sta->asoc_cap.pkt_padding == 3) { + /* follow PPE threshold */ + u8 ppe16 = 0, ppe8 = 0; + u8 nss = sta->asoc_cap.nss_rx; + + /* bw = 20MHz */ + ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_20] & 0x7); + ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_20]>>3) & 0x7; + + if ((ppe16 != 7) && (ppe8 == 7)) { + cctrl.nominal_pkt_padding = 2; + cctl_info_mask.nominal_pkt_padding = 0x3; + } else if (ppe8 != 7) { + cctrl.nominal_pkt_padding = 1; + cctl_info_mask.nominal_pkt_padding = 0x3; + } else { + cctrl.nominal_pkt_padding = 0; + cctl_info_mask.nominal_pkt_padding = 0x3; + } + /* bw = 40MHz */ + ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_40] & 0x7); + ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_40]>>3) & 0x7; + + if ((ppe16 != 7) && (ppe8 == 7)) { + cctrl.nominal_pkt_padding40 = 2; + cctl_info_mask.nominal_pkt_padding40 = 0x3; + } else if (ppe8 != 7) { + cctrl.nominal_pkt_padding40 = 1; + cctl_info_mask.nominal_pkt_padding40 = 0x3; + } else { + cctrl.nominal_pkt_padding40 = 0; + cctl_info_mask.nominal_pkt_padding40 = 0x3; + } + /* bw = 80MHz */ + ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_80] & 0x7); + ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_80]>>3) & 0x7; + + if ((ppe16 != 7) && (ppe8 == 7)) { + cctrl.nominal_pkt_padding80 = 2; + cctl_info_mask.nominal_pkt_padding80 = 0x3; + } else if (ppe8 != 7) { + cctrl.nominal_pkt_padding80 = 1; + cctl_info_mask.nominal_pkt_padding80 = 0x3; + } else { + cctrl.nominal_pkt_padding80 = 0; + cctl_info_mask.nominal_pkt_padding80 = 0x3; + } + } else { + cctrl.nominal_pkt_padding = sta->asoc_cap.pkt_padding; + cctrl.nominal_pkt_padding40 = sta->asoc_cap.pkt_padding; + cctrl.nominal_pkt_padding80 = sta->asoc_cap.pkt_padding; + cctl_info_mask.nominal_pkt_padding = 0x3; + cctl_info_mask.nominal_pkt_padding40 = 0x3; + cctl_info_mask.nominal_pkt_padding80 = 0x3; + } + + if (sta->wmode&WLAN_MD_11AX) { + /** + * bsr_queue_size_format: + * 1: buffer status unit is 802.11, HE mode + * 0: buffer status unit is 802.11, legacy mode + **/ + cctrl.bsr_queue_size_format = 1; + cctl_info_mask.bsr_queue_size_format = 1; + } + + sts = rtw_hal_cmc_tbl_cfg(hal_info, &cctrl, &cctl_info_mask, sta->macid); + +out: + return sts; +} + +static enum rtw_hal_status +_hal_update_dctrl_tbl(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE; + struct mac_ax_dctl_info dctrl, dctl_info_mask; + + if (NULL == sta) + goto out; + + _os_mem_set(hal_to_drvpriv(hal_info), &dctrl, 0, sizeof(struct mac_ax_dctl_info)); + _os_mem_set(hal_to_drvpriv(hal_info), &dctl_info_mask, 0, sizeof(struct mac_ax_dctl_info)); + +#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX + dctrl.chksum_offload_en = 1; + dctl_info_mask.chksum_offload_en = 1; + dctrl.with_llc = 1; + dctl_info_mask.with_llc = 1; +#endif /*CONFIG_PHL_CSUM_OFFLOAD_RX*/ + sts = rtw_hal_dmc_tbl_cfg(hal_info, &dctrl, &dctl_info_mask, sta->macid); + +out: + return sts; +} + +enum rtw_hal_status +_hal_update_ba_cam(struct hal_info_t *hal_info, u8 valid, u16 macid, + u8 dialog_token, u16 timeout, u16 start_seq_num, + u16 ba_policy, u16 tid, u16 buf_size, u8 camid) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + void *drv = hal_to_drvpriv(hal_info); + struct mac_ax_bacam_info ba_cam = {0}; + FUNCIN(); + _os_mem_set(drv, &ba_cam, 0, sizeof(ba_cam)); + ba_cam.valid = valid; + ba_cam.init_req = 1; + ba_cam.entry_idx = camid; + ba_cam.tid = tid; + ba_cam.macid = (u8)macid; + if (buf_size > 64) + ba_cam.bmap_size = 4; + else + ba_cam.bmap_size = 0; + ba_cam.ssn = start_seq_num; + + PHL_INFO("[BACAM] ba_cam.valid = %d, ba_cam.init_req = %d, ba_cam.entry_idx = %d\n", + ba_cam.valid, + ba_cam.init_req, + ba_cam.entry_idx); + PHL_INFO("[BACAM] ba_cam.tid = %d, ba_cam.macid = %d, ba_cam.bmap_size = %d\n", + ba_cam.tid, + ba_cam.macid, + ba_cam.bmap_size); + PHL_INFO("[BACAM] ba_cam.ssn = 0x%X\n", + ba_cam.ssn); + + hal_status = rtw_hal_bacam_cfg(hal_info, &ba_cam); + + if (RTW_HAL_STATUS_FAILURE == hal_status) { + PHL_WARN("rtw_hal_bacam_cfg fail 0x%08X\n", hal_status); + + } + + FUNCOUT(); + return hal_status; +} + +enum rtw_hal_status +rtw_hal_start_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, + u8 dialog_token, u16 timeout, u16 start_seq_num, + u16 ba_policy, u16 tid, u16 buf_size) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 idx = 0; + + if (sta->hal_sta->ba_ctl.count == MAX_BAENTRY) { + PHL_INFO("No avail standard entry found\n"); + if (tid != 0) + goto out; + else { + for (idx = 0; idx < MAX_BAENTRY; idx++) { + if (sta->hal_sta->ba_ctl.tid[idx] != 0) { + PHL_INFO("Remove old entry(%d) tid(%d)\n", + idx, sta->hal_sta->ba_ctl.tid[idx]); + hal_status = _hal_update_ba_cam(hal_info, 0, sta->macid, 0, + 0, 0, 0, 0, 0, idx); + if (hal_status == RTW_HAL_STATUS_SUCCESS) { + sta->hal_sta->ba_ctl.used_map[idx] = false; + sta->hal_sta->ba_ctl.count--; + break; + } + } else { + PHL_INFO("Use existing entry(%d)\n", idx); + sta->hal_sta->ba_ctl.used_map[idx] = false; + sta->hal_sta->ba_ctl.count--; + break; + } + } + } + } + for (idx = 0; idx < MAX_BAENTRY; idx++) { + if (!sta->hal_sta->ba_ctl.used_map[idx]) + break; + } + if (idx == MAX_BAENTRY) { + PHL_WARN("No avail standard entry found but count is(%d)\n", + sta->hal_sta->ba_ctl.count); + goto out; + } + hal_status = _hal_update_ba_cam(hal_info, 1, sta->macid, dialog_token, + timeout, start_seq_num, ba_policy, tid, + buf_size, idx); + if (RTW_HAL_STATUS_SUCCESS != hal_status) + goto out; + + sta->hal_sta->ba_ctl.used_map[idx] = 1; + sta->hal_sta->ba_ctl.tid[idx] = (u8)tid; + sta->hal_sta->ba_ctl.count++; +out: + return hal_status; +} + +enum rtw_hal_status +rtw_hal_stop_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, u16 tid) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 i; + + for (i = 0; i < MAX_BAENTRY; i++) { + if (sta->hal_sta->ba_ctl.used_map[i] && + ((u8)tid == sta->hal_sta->ba_ctl.tid[i])) { + hal_status = _hal_update_ba_cam(hal_info, 0, sta->macid, 0, + 0, 0, 0, 0, 0, i); + break; + } + } + if (RTW_HAL_STATUS_SUCCESS != hal_status) + goto out; + sta->hal_sta->ba_ctl.used_map[i] = 0; + sta->hal_sta->ba_ctl.tid[i] = 0xff; + sta->hal_sta->ba_ctl.count--; +out: + return hal_status; +} + + + +enum rtw_hal_status +rtw_hal_stainfo_init(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + void *drv = hal_to_drvpriv(hal_info); + + sta->hal_sta = _os_mem_alloc(drv, sizeof(struct rtw_hal_stainfo_t)); + if (sta->hal_sta == NULL) { + PHL_ERR("alloc hal_sta failed\n"); + goto error_exit; + } + + sta->hal_sta->hw_cfg_tab = + _os_mem_alloc(drv, sizeof(struct rtw_hw_cfg_tab)); + if (sta->hal_sta->hw_cfg_tab == NULL) { + PHL_ERR("alloc hw_cfg_tab failed\n"); + goto error_hsta_mem; + } + + hal_status = rtw_hal_bb_stainfo_init(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("alloc bb_stainfo failed\n"); + goto error_hw_cfg_tab; + } + /* Init lock for tx statistics */ + _os_spinlock_init(drv, &sta->hal_sta->trx_stat.tx_sts_lock); + /* Init STA RSSI Statistics */ + _hal_sta_rssi_init(sta); + + return hal_status; + +error_hw_cfg_tab : + if (sta->hal_sta->hw_cfg_tab) { + _os_mem_free(drv, sta->hal_sta->hw_cfg_tab, + sizeof(struct rtw_hw_cfg_tab)); + sta->hal_sta->hw_cfg_tab = NULL; + } +error_hsta_mem : + if (sta->hal_sta) { + _os_mem_free(drv, sta->hal_sta, + sizeof(struct rtw_hal_stainfo_t)); + sta->hal_sta = NULL; + } +error_exit : + return hal_status; +} + +enum rtw_hal_status +rtw_hal_stainfo_deinit(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + void *drv = hal_to_drvpriv(hal_info); + + if (sta->hal_sta) { + /* Free lock for tx statistics */ + _os_spinlock_free(drv, &sta->hal_sta->trx_stat.tx_sts_lock); + hal_status = rtw_hal_bb_stainfo_deinit(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("bb_stainfo deinit failed\n"); + + if (sta->hal_sta->hw_cfg_tab) { + _os_mem_free(drv, sta->hal_sta->hw_cfg_tab, + sizeof(struct rtw_hw_cfg_tab)); + sta->hal_sta->hw_cfg_tab = NULL; + } + + _os_mem_free(drv, sta->hal_sta, + sizeof(struct rtw_hal_stainfo_t)); + sta->hal_sta = NULL; + } + + return hal_status; +} +static void _hal_sta_set_default_value(struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + u8 i; + sta->hal_sta->ra_info.ra_registered = false; + sta->hal_sta->ba_ctl.count = 0; + for (i = 0; ihal_sta->ba_ctl.tid[i] = 0xff; + sta->hal_sta->ba_ctl.used_map[i] = 0; + } +} + +enum rtw_hal_status +rtw_hal_add_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + _hal_sta_set_default_value(hal_info, sta); + + /*add mac address-cam*/ + if (rtw_hal_mac_addr_cam_add_entry(hal_info, sta) != + RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_mac_addr_cam_add_entry failed\n"); + goto _exit; + } + + /*update default cmac table*/ + if (_hal_set_default_cctrl_tbl(hal_info, sta) != + RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("_hal_set_default_cctrl_tbl failed\n"); + /* goto _exit; */ /* shall be unmark after header FW is ready */ + } + + if (_hal_update_dctrl_tbl(hal_info, sta) != + RTW_HAL_STATUS_SUCCESS) { + PHL_WARN("_hal_set_default_dctrl_tbl failed\n"); + /* goto _exit; */ + } + + /*add bb stainfo*/ + if (rtw_hal_bb_stainfo_add(hal_info, sta) != + RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_bb_stainfo_add failed\n"); + goto _err_bbsta_add; + } + return RTW_HAL_STATUS_SUCCESS; + +_err_bbsta_add: + rtw_hal_mac_addr_cam_del_entry(hal_info, sta); +_exit: + return RTW_HAL_STATUS_FAILURE; +} + +enum rtw_hal_status +rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta, + bool is_connect) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + enum phl_upd_mode mode = PHL_UPD_STA_CON_DISCONN; + + /*update cmac table*/ + if (RTW_HAL_STATUS_SUCCESS != _hal_update_cctrl_tbl(hal_info, sta)) + PHL_WARN("_hal_update_cctrl_tbl failed\n"); + + /*update dmac table*/ + if (RTW_HAL_STATUS_SUCCESS != _hal_update_dctrl_tbl(hal_info, sta)) + PHL_WARN("_hal_update_dctrl_tbl failed\n"); + + /*change mac address-cam & mac_h2c_join_info*/ + hal_status = rtw_hal_mac_addr_cam_change_entry(hal_info, sta, mode, is_connect); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n"); + } + + if (is_connect) { + + if (RTW_HAL_STATUS_SUCCESS != _hal_bfee_init(hal_info, sta)) { + PHL_ERR("_hal_bfee_init Fail!\n"); + } + + if (sta->hal_sta->rssi_stat.assoc_rssi == 0 + #ifdef CONFIG_PHL_TDLS + /* There is no association frame for TDLS connection */ + && sta->wrole->type != PHL_RTYPE_TDLS + #endif + ) { + PHL_ERR("%s macid:%d assoc_rssi == 0\n", __func__, sta->macid); + _os_warn_on(1); + } + + hal_status = rtw_hal_bb_upt_ramask(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_bb_upt_ramask failed\n"); + + hal_status = rtw_hal_bb_ra_register(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_bb_ra_register failed\n"); + hal_info->hal_com->assoc_sta_cnt++; + + if (sta->wmode & WLAN_MD_11AX) { + rtw_hal_bb_set_sta_id(hal_info, sta->aid, sta->wrole->hw_band); + rtw_hal_bb_set_bss_color(hal_info, sta->asoc_cap.bsscolor, + sta->wrole->hw_band); + rtw_hal_bb_set_tb_pwr_ofst(hal_info, 0, sta->wrole->hw_band); + } + /* reset rssi stat value */ + sta->hal_sta->rssi_stat.ma_rssi_mgnt = 0; + } + else { + hal_status = rtw_hal_bb_ra_deregister(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_bb_ra_deregister failed\n"); + hal_info->hal_com->assoc_sta_cnt--; + /* reset drv rssi_stat */ + _hal_sta_rssi_init(sta); + _hal_sta_set_default_value(hal_info, sta); + } + /* reset bb rssi_stat */ + rtw_hal_bb_media_status_update(hal_info, sta, is_connect); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_change_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta, + enum phl_upd_mode mode) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + bool is_connect = false; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: sta->macid(0x%X), mode(%d)\n", + __FUNCTION__, sta->macid , mode); + /*update cmac table*/ + if (RTW_HAL_STATUS_SUCCESS != _hal_update_cctrl_tbl(hal_info, sta)) + PHL_WARN("_hal_update_cctrl_tbl failed\n"); + + /*update dmac table*/ + if (RTW_HAL_STATUS_SUCCESS != _hal_update_dctrl_tbl(hal_info, sta)) + PHL_WARN("_hal_update_dctrl_tbl failed\n"); + + /*change mac address-cam & mac_h2c_join_info */ + is_connect = (sta->wrole->mstate == MLME_LINKED) ? true : false; + hal_status = rtw_hal_mac_addr_cam_change_entry(hal_info, sta, mode, is_connect); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n"); + + hal_status = rtw_hal_bb_ra_update(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("rtw_hal_bb_ra_update failed\n"); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_del_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + _hal_sta_set_default_value(hal_info, sta); + + hal_status = rtw_hal_mac_addr_cam_del_entry(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("mac_addr_cam_del_entry failed\n"); + + hal_status = rtw_hal_bb_stainfo_delete(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + PHL_ERR("bb_stainfo deinit failed\n"); + + return hal_status; +} + +u8 rtw_hal_get_sta_rssi(struct rtw_phl_stainfo_t *sta) +{ + u8 rssi = (sta->hal_sta->rssi_stat.rssi >> 1); + + return rssi; +} + +u8 rtw_hal_get_sta_rssi_bcn(struct rtw_phl_stainfo_t *sta) +{ + u8 rssi = (sta->hal_sta->rssi_stat.rssi_bcn >> 1); + + return rssi; +} + +bool rtw_hal_is_sta_linked(void *hal, struct rtw_phl_stainfo_t *sta) +{ + return (sta->hal_sta->ra_info.ra_registered == true) ? true : false; +} + +enum rtw_hal_status +rtw_hal_set_edca(void *hal, struct rtw_wifi_role_t *wrole, u8 ac, u32 edca) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status; + + + hal_status = rtw_hal_mac_set_edca(hal_info->hal_com, wrole->hw_band, + wrole->hw_wmm, ac, edca); + + return hal_status; +} + +enum rtw_hal_status +rtw_hal_cfg_tx_ampdu(void *hal, struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + + /* update ampdu configuration */ + if (64 == sta->asoc_cap.num_ampdu) + hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, 0x3F, 0xA5); + else if (128 == sta->asoc_cap.num_ampdu) + hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, 0x7F, 0xAB); + + if (RTW_HAL_STATUS_SUCCESS != hsts) + goto out; + + /* todo: update cmac table */ + +out: + return hsts; +} + +enum rtw_hal_status +rtw_hal_set_sta_rx_sts(struct rtw_phl_stainfo_t *sta, u8 rst, + struct rtw_r_meta_data *meta) +{ + if (rst) { + sta->hal_sta->trx_stat.rx_ok_cnt = 0; + sta->hal_sta->trx_stat.rx_err_cnt = 0; + } else { + if (meta->crc32 || meta->icverr) + sta->hal_sta->trx_stat.rx_err_cnt++; + else + sta->hal_sta->trx_stat.rx_ok_cnt++; + } + /* TODO: rx_rate_plurality */ + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status +rtw_hal_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, + struct rtw_phl_rainfo *phl_rainfo) +{ + enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE; + + hal_sts = rtw_hal_bb_query_rainfo(hal, hal_sta, phl_rainfo); + + + return hal_sts; +} + +/** + * rtw_hal_query_txsts_rpt() - get txok and tx retry info + * @hal: struct hal_info_t * + * @macid: indicate the first macid that you want to query. + * Return rtw_hal_bb_query_txsts_rpt's return value in enum rtw_hal_status type. + */ +enum rtw_hal_status +rtw_hal_query_txsts_rpt(void *hal, u16 macid) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + /*get tx ok and tx retry statistics*/ + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_bb_query_txsts_rpt(hal_info, macid, 0xFFFF)) + return RTW_HAL_STATUS_FAILURE; + else + return RTW_HAL_STATUS_SUCCESS; +} + diff --git a/phl/hal_g6/hal_sta.h b/phl/hal_g6/hal_sta.h new file mode 100644 index 0000000..efed3d0 --- /dev/null +++ b/phl/hal_g6/hal_sta.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_STA_H_ +#define _HAL_STA_H_ + +struct rtw_hw_cfg_tab { + u8 dummy; +}; + +enum rtw_hal_status +rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta, + bool is_connect); + +#endif /*_HAL_STA_H_*/ diff --git a/phl/hal_g6/hal_str_proc.c b/phl/hal_g6/hal_str_proc.c new file mode 100644 index 0000000..65510ae --- /dev/null +++ b/phl/hal_g6/hal_str_proc.c @@ -0,0 +1,248 @@ +/****************************************************************************** +* +* Copyright(c) 2019 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +*****************************************************************************/ + +#include "hal_str_proc.h" + + +bool hal_is_comment_string( + char *szStr +) +{ + if (*szStr == '/' && *(szStr + 1) == '/') + return true; + else + return false; +} + +bool hal_get_fractionvalue_fromstring( + char *szStr, + u8 *pInteger, + u8 *pFraction, + u32 *pu4bMove +) +{ + char *szScan = szStr; + + /* Initialize output. */ + *pu4bMove = 0; + *pInteger = 0; + *pFraction = 0; + + /* Skip leading space. */ + while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) { + ++szScan; + ++(*pu4bMove); + } + + if (*szScan < '0' || *szScan > '9') + return false; + + /* Parse each digit. */ + do { + (*pInteger) *= 10; + *pInteger += (*szScan - '0'); + + ++szScan; + ++(*pu4bMove); + + if (*szScan == '.') { + ++szScan; + ++(*pu4bMove); + + if (*szScan < '0' || *szScan > '9') + return false; + + *pFraction += (*szScan - '0') * 10; + ++szScan; + ++(*pu4bMove); + + if (*szScan >= '0' && *szScan <= '9') { + *pFraction += *szScan - '0'; + ++szScan; + ++(*pu4bMove); + } + return true; + } + } while (*szScan >= '0' && *szScan <= '9'); + + return true; +} + +bool hal_is_alpha(char ch_tmp) +{ + if ((ch_tmp >= 'a' && ch_tmp <= 'z') || + (ch_tmp >= 'A' && ch_tmp <= 'Z')) + return true; + else + return false; +} + +bool hal_ishexdigit(char ch_tmp) +{ + if ((ch_tmp >= '0' && ch_tmp <= '9') || + (ch_tmp >= 'a' && ch_tmp <= 'f') || + (ch_tmp >= 'A' && ch_tmp <= 'F')) + return true; + else + return false; +} + +bool hal_get_hexvalue_fromstring( + char *szStr, + u32 *pu4bVal, + u32 *pu4bMove +) +{ + char *szScan = szStr; + + /* Check input parameter. */ + if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) { + PHL_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove); + return false; + } + + /* Initialize output. */ + *pu4bMove = 0; + *pu4bVal = 0; + + /* Skip leading space. */ + while (*szScan != '\0' && + (*szScan == ' ' || *szScan == '\t')) { + szScan++; + (*pu4bMove)++; + } + + /* Skip leading '0x' or '0X'. */ + if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) { + szScan += 2; + (*pu4bMove) += 2; + } + + /* Check if szScan is now pointer to a character for hex digit, */ + /* if not, it means this is not a valid hex number. */ + if (!hal_ishexdigit(*szScan)) + return false; + + /* Parse each digit. */ + do { + (*pu4bVal) <<= 4; + *pu4bVal += hal_mapchar_tohexdigit(*szScan); + + szScan++; + (*pu4bMove)++; + } while (hal_ishexdigit(*szScan)); + + return true; +} + +bool hal_is_allspace_tab( + char *data, + u8 size +) +{ + u8 cnt = 0, NumOfSpaceAndTab = 0; + + while (size > cnt) { + if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0') + ++NumOfSpaceAndTab; + + ++cnt; + } + + return size == NumOfSpaceAndTab; +} + +u32 hal_mapchar_tohexdigit( + char chTmp +) +{ + if (chTmp >= '0' && chTmp <= '9') + return chTmp - '0'; + else if (chTmp >= 'a' && chTmp <= 'f') + return 10 + (chTmp - 'a'); + else if (chTmp >= 'A' && chTmp <= 'F') + return 10 + (chTmp - 'A'); + else + return 0; +} + + +bool hal_parse_fiedstring(char *in_str, u32 *start, char *out_str, char lqualifier, char rqualifier) +{ + u32 i = 0, j = 0; + char c = in_str[(*start)++]; + + if (c != lqualifier) + return false; + + i = (*start); + c = in_str[(*start)++]; + + while (c != rqualifier && c != '\0') + c = in_str[(*start)++]; + + if (c == '\0') + return false; + + j = (*start) - 2; + _os_strncpy((char *)out_str, (const char *)(in_str + i), j - i + 1); + + return true; +} + + +bool hal_get_u1bint_fromstr_indec(char *str, u8 *pint) +{ + u16 i = 0; + *pint = 0; + + while (str[i] != '\0') { + if (str[i] >= '0' && str[i] <= '9') { + *pint *= 10; + *pint += (str[i] - '0'); + } else + return false; + ++i; + } + + return true; +} + + +bool hal_get_s1bint_fromstr_indec(char *str, s8 *val) +{ + u8 negative = 0; + u16 i = 0; + + *val = 0; + + while (str[i] != '\0') { + if (i == 0 && (str[i] == '+' || str[i] == '-')) { + if (str[i] == '-') + negative = 1; + } else if (str[i] >= '0' && str[i] <= '9') { + *val *= 10; + *val += (str[i] - '0'); + } else + return false; + ++i; + } + + if (negative) + *val = -*val; + + return true; +} + diff --git a/phl/hal_g6/hal_str_proc.h b/phl/hal_g6/hal_str_proc.h new file mode 100644 index 0000000..3c67a72 --- /dev/null +++ b/phl/hal_g6/hal_str_proc.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "hal_headers.h" + + +#define hal_getLinefrombuffer(buffer) _os_strsep(&buffer, "\r\n") + +bool hal_is_comment_string(char *szStr); + +bool hal_is_alpha(char ch_tmp); + +bool hal_ishexdigit(char chTmp); + +bool hal_get_hexvalue_fromstring(char *szStr, u32 *pu4bVal, u32 *pu4bMove); + +bool hal_get_fractionvalue_fromstring( + char *szStr, + u8 *pInteger, + u8 *pFraction, + u32 *pu4bMove); + +bool hal_is_allspace_tab(char *data, u8 size); + +u32 hal_mapchar_tohexdigit(char chTmp); + +bool hal_parse_fiedstring(char *in_str, u32 *start, char *out_str, char lqualifier, char rqualifier); + +bool hal_get_u1bint_fromstr_indec(char *str, u8 *pint); + +bool hal_get_s1bint_fromstr_indec(char *str, s8 *val); + diff --git a/phl/hal_g6/hal_struct.h b/phl/hal_g6/hal_struct.h new file mode 100644 index 0000000..69d832d --- /dev/null +++ b/phl/hal_g6/hal_struct.h @@ -0,0 +1,334 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_STRUCT_H_ +#define _HAL_STRUCT_H_ + + +struct hal_info_t; + +#define hal_get_trx_ops(_halinfo) (_halinfo->trx_ops) +/** + * struct hal_trx_ops - hw ic specific operations + * + * @init: the function for initializing IC specific data and hw configuration + * @deinit: the function for deinitializing IC specific data and hw configuration + * @query_tx_res: the function for querying hw tx resource + * @query_rx_res: the function for querying hw rx resource + * @map_hw_tx_chnl: the function for getting mapping hw tx channel + * @qsel_to_tid: the function for converting hw qsel to tid value + * @query_txch_num: the function for querying total hw tx dma channels number + * @query_rxch_num: the function for querying total hw rx dma channels number + * @update_wd: the function for updating wd page for xmit packet + * @update_txbd: the function for updating tx bd for xmit packet + * @tx_start: the function to trigger hw to start tx + * @get_fwcmd_queue_idx: the function to get fwcmd queue idx + * @check_rxrdy: the function check if hw rx buffer is ready to access + * @handle_rxbd_info: the function handling hw rxbd information + * @handle_rx_buffer: the function handling hw rx buffer + * @update_rxbd: the function for updating rx bd for recv packet + * @notify_rxdone: the function to notify hw rx done + * @handle_wp_rpt: the function parsing wp report content + */ +struct hal_trx_ops { + u8 (*map_hw_tx_chnl)(u16 macid, enum rtw_phl_ring_cat cat, u8 band); + u8 (*query_txch_num)(void); + u8 (*query_rxch_num)(void); + +#ifdef CONFIG_PCI_HCI + enum rtw_hal_status (*init)(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf); + void (*deinit)(struct hal_info_t *hal); + + u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, + u16 *host_idx, u16 *hw_idx); + u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, + u16 *host_idx, u16 *hw_idx); + void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); + void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); + void (*cfg_wow_txdma)(struct hal_info_t *hal, u8 en); + void (*cfg_txhci)(struct hal_info_t *hal, u8 en); + void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); + void (*clr_rwptr)(struct hal_info_t *hal); + void (*rst_bdram)(struct hal_info_t *hal); + u8 (*poll_txdma_idle)(struct hal_info_t *hal); + void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); + u8 (*qsel_to_tid)(struct hal_info_t *hal, u8 qsel_id, u8 tid_indic); + + enum rtw_hal_status + (*update_wd)(struct hal_info_t *hal, struct rtw_phl_pkt_req *req); + enum rtw_hal_status + (*update_txbd)(struct hal_info_t *hal, + struct tx_base_desc *txbd_ring, + struct rtw_wd_page *wd_page, + u8 ch_idx, u16 wd_num); + enum rtw_hal_status + (*tx_start)(struct hal_info_t *hal, + struct tx_base_desc *txbd, u8 dma_ch); + + u8 (*get_fwcmd_queue_idx)(void); + + u8 (*check_rxrdy)(struct rtw_phl_com_t *phl_com, u8 *rxbuf, u8 dma_ch); + enum rtw_hal_status + (*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u32 buf_size, + struct rtw_phl_rx_pkt *rxpkt); + u8 (*handle_rxbd_info)(struct hal_info_t *hal, u8 *rxbuf, u16 *buf_size); + + enum rtw_hal_status + (*update_rxbd)(struct hal_info_t *hal, + struct rx_base_desc *rxbd, + struct rtw_rx_buf *rx_buf); + + enum rtw_hal_status + (*notify_rxdone)(struct hal_info_t *hal, + struct rx_base_desc *rxbd, u8 ch, u16 rxcnt); + + u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len, + u8 *sw_retry, u8 *dma_ch, u16 *wp_seq, u8 *txsts); +#endif /*CONFIG_PCI_HCI*/ + +#ifdef CONFIG_USB_HCI + enum rtw_hal_status (*init)(struct hal_info_t *hal); + void (*deinit)(struct hal_info_t *hal); + + enum rtw_hal_status + (*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req, + u8 *wd_buf, u32 *wd_len); + u8 (*get_bulkout_id)(struct hal_info_t *hal, u8 ch_dma, u8 mode); + enum rtw_hal_status + (*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u32 buf_size, + struct rtw_phl_rx_pkt *rxpkt); + enum rtw_hal_status + (*query_hal_info)(struct hal_info_t *hal, u8 info_id, void *value); + enum rtw_hal_status + (*usb_tx_agg_cfg)(struct hal_info_t *hal, u8* wd_buf, u8 agg_num); + enum rtw_hal_status + (*usb_rx_agg_cfg)(struct hal_info_t *hal, u8 mode, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num); + u8 (*get_fwcmd_queue_idx)(void); + u8 (*get_max_bulkout_wd_num)(struct hal_info_t *hal); + void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); + void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); + void (*cfg_txhci)(struct hal_info_t *hal, u8 en); + void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); + void (*clr_rwptr)(struct hal_info_t *hal); + void (*rst_bdram)(struct hal_info_t *hal); + void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); + u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len, + u8 *mac_id, u8 *ac_queue, u8 *txsts); +#endif /*CONFIG_USB_HCI*/ + +#ifdef CONFIG_SDIO_HCI + enum rtw_hal_status (*init)(struct hal_info_t *hal); + void (*deinit)(struct hal_info_t *hal); + u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, + u16 *host_idx, u16 *hw_idx); + u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, + u16 *host_idx, u16 *hw_idx); + + enum rtw_hal_status + (*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req, + u8 *wd_buf, u32 *wd_len); + u8 (*get_fwcmd_queue_idx)(void); + void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); + void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); + void (*cfg_txhci)(struct hal_info_t *hal, u8 en); + void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); + void (*clr_rwptr)(struct hal_info_t *hal); + void (*rst_bdram)(struct hal_info_t *hal); + void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); + + enum rtw_hal_status(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u32 buf_size, + struct rtw_phl_rx_pkt *rxpkt); +#endif + +}; + +#define hal_get_ops(_halinfo) (&_halinfo->hal_ops) + +struct hal_ops_t { + /*** initialize section ***/ + void (*read_chip_version)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + void (*init_hal_spec)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + void (*init_default_value)(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg); + u32 (*hal_hci_configure)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + struct rtw_ic_info *ic_info); + + enum rtw_hal_status (*hal_get_efuse)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + enum rtw_hal_status (*hal_init)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + void (*hal_deinit)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + enum rtw_hal_status (*hal_start)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + enum rtw_hal_status (*hal_stop)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + enum rtw_hal_status (*hal_cfg_fw)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + char *ic_name, + enum rtw_fw_type fw_type); +#ifdef CONFIG_WOWLAN + enum rtw_hal_status (*hal_wow_init)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); + enum rtw_hal_status (*hal_wow_deinit)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); +#endif /* CONFIG_WOWLAN */ + + /* MP */ + enum rtw_hal_status (*hal_mp_init)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + enum rtw_hal_status (*hal_mp_deinit)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + /*IO ops*/ + u32 (*read_macreg)(struct hal_info_t *hal, + u32 offset, u32 bit_mask); + void (*write_macreg)(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data); + u32 (*read_bbreg)(struct hal_info_t *hal, + u32 offset, u32 bit_mask); + void (*write_bbreg)(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data); + u32 (*read_rfreg)(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask); + void (*write_rfreg)(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask, u32 data); +#ifdef RTW_WKARD_BUS_WRITE + enum rtw_hal_status (*write_reg_post_cfg)(struct hal_info_t *hal_info, + u32 offset, u32 value); +#endif + + /*** interrupt hdl section ***/ + void (*enable_interrupt)(struct hal_info_t *hal); + void (*disable_interrupt)(struct hal_info_t *hal); + void (*config_interrupt)(struct hal_info_t *hal, enum rtw_phl_config_int int_mode); + bool (*recognize_interrupt)(struct hal_info_t *hal); + bool (*recognize_halt_c2h_interrupt)(struct hal_info_t *hal); + void (*clear_interrupt)(struct hal_info_t *hal); + u32 (*interrupt_handler)(struct hal_info_t *hal); + void (*restore_interrupt)(struct hal_info_t *hal); + void (*restore_rx_interrupt)(struct hal_info_t *hal); + +#ifdef RTW_PHL_BCN //hal_ops_t + enum rtw_hal_status (*cfg_bcn)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); + enum rtw_hal_status (*upt_bcn)(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); +#endif + + enum rtw_hal_status (*pkt_ofld)(struct hal_info_t *hal, u8 *id, u8 op, + u8 *pkt, u16 *len); + enum rtw_hal_status (*pkt_update_ids)(struct hal_info_t *hal, + struct pkt_ofld_entry *entry); +}; + +struct hal_info_t { + struct rtw_hal_com_t *hal_com; + _os_atomic hal_mac_mem; + + struct hal_trx_ops *trx_ops; + struct hal_ops_t hal_ops; +#ifdef CONFIG_PCI_HCI + void *txch_map; +#endif + void *rpr_cfg; + + void *mac; /*halmac*/ + void *bb; + void *rf; + void *btc; + void *efuse; + enum rtw_rx_fltr_mode rx_fltr_mode; + u8 monitor_mode; /* default: 0 */ +}; + +struct hal_c2h_hdl { + u8 cat; + u8 cls_min; + u8 cls_max; + u32 (*c2h_hdl)(void *hal, struct rtw_c2h_info *c2h); +}; + + +#ifdef CONFIG_PHL_CHANNEL_INFO + +struct chinfo_bbcr_cfg { + bool ch_i_phy0_en; + bool ch_i_phy1_en; + bool ch_i_data_src; + bool ch_i_cmprs; + u8 ch_i_grp_num_non_he; + u8 ch_i_grp_num_he; + u8 ch_i_blk_start_idx; + u8 ch_i_blk_end_idx; + u32 ch_i_ele_bitmap; + bool ch_i_type; + u8 ch_i_seg_len; +}; + +struct ch_rpt_hdr_info { + u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/ + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 total_len_m:1; + u8 total_seg_num:7; + #else + u8 total_seg_num:7; + u8 total_len_m:1; + #endif + u8 avg_noise_pow; + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 is_pkt_end:1; + u8 set_valid:1; + u8 n_rx:3; + u8 n_sts:3; + #else + u8 n_sts:3; + u8 n_rx:3; + u8 set_valid:1; + u8 is_pkt_end:1; + #endif + u8 segment_size; /*unit (8Byte)*/ + u8 evm[2]; +}; + +struct phy_info_rpt { + u8 rssi[2]; + u16 rsvd_0; + u8 rssi_avg; + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 rxsc:4; + u8 rsvd_1:4; + #else + u8 rsvd_1:4; + u8 rxsc:4; + #endif + u16 rsvd_2; +}; + + +struct ch_info_drv_rpt { + u32 raw_data_len; + u8 seg_idx_curr; +}; + +#endif /* CONFIG_PHL_CHANNEL_INFO */ +#endif /*_HAL_STRUCT_H_*/ diff --git a/phl/hal_g6/hal_thermal.c b/phl/hal_g6/hal_thermal.c new file mode 100644 index 0000000..cb877b0 --- /dev/null +++ b/phl/hal_g6/hal_thermal.c @@ -0,0 +1,166 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_THERMAL_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_THERMAL_PROTECT + +enum rtw_hal_status +rtw_hal_thermal_protect_cfg_tx_ampdu( + void *hal, + struct rtw_phl_stainfo_t *sta, + u8 ratio) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + u8 num_ampdu = 0, tx_time = 0; + + if (64 == sta->asoc_cap.num_ampdu) + tx_time = 0xA5; + else if (128 == sta->asoc_cap.num_ampdu) + tx_time = 0xAB; + + if(sta->asoc_cap.num_ampdu_bk == 0) + sta->asoc_cap.num_ampdu_bk = sta->asoc_cap.num_ampdu; + + sta->asoc_cap.num_ampdu = sta->asoc_cap.num_ampdu_bk * ratio / 100; + num_ampdu = sta->asoc_cap.num_ampdu; + + if(num_ampdu == 0) + num_ampdu = 1; + + hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, num_ampdu, tx_time); + + PHL_INFO("%s: bk_num_ampdu = %d num_ampdu = %d, tx_time = %x\n", + __FUNCTION__, sta->asoc_cap.num_ampdu_bk, num_ampdu, tx_time); + + if (RTW_HAL_STATUS_SUCCESS != hsts) + goto out; + +out: + return hsts; +} + +bool rtw_hal_check_thermal_protect( + struct rtw_phl_com_t *phl_com, + void *hal +) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum halrf_thermal_status status = HALRF_THERMAL_STATUS_BELOW_THRESHOLD; + bool action_changed = false; + + status = rtw_hal_rf_get_ther_protected_threshold(hal_info); + + PHL_INFO("%s: Cur action = %x\n", __FUNCTION__, phl_com->thermal_protect_action); + PHL_INFO("%s: status = %x\n", __FUNCTION__, status); + + switch (phl_com->thermal_protect_action){ + case PHL_THERMAL_PROTECT_ACTION_NONE: + if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){ + phl_com->thermal_protect_action = + PHL_THERMAL_PROTECT_ACTION_LEVEL1; + phl_com->drv_mode = RTW_DRV_MODE_HIGH_THERMAL; + action_changed = true; + } + else if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD || + status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){ + /* Do nothing */ + } + else{ + PHL_ERR("Unknown thermal status(%x)!\n", status); + } + break; + case PHL_THERMAL_PROTECT_ACTION_LEVEL1: + if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD){ + phl_com->thermal_protect_action = + PHL_THERMAL_PROTECT_ACTION_NONE; + phl_com->drv_mode = RTW_DRV_MODE_NORMAL; + action_changed = true; + } + else if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){ + phl_com->thermal_protect_action = + PHL_THERMAL_PROTECT_ACTION_LEVEL2; + action_changed = true; + } + else if(status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){ + /* Do nothing */ + } + else{ + PHL_ERR("Unknown thermal status(%x)!\n", status); + } + break; + case PHL_THERMAL_PROTECT_ACTION_LEVEL2: + if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD){ + phl_com->thermal_protect_action = + PHL_THERMAL_PROTECT_ACTION_LEVEL1; + action_changed = true; + } + else if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){ + /* No next action */ + } + else if(status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){ + /* Do nothing */ + } + else{ + PHL_ERR("Unknown thermal status(%x)!\n", status); + } + break; + default: + PHL_ERR("Unknown thermal protect action(%x)!\n", + phl_com->thermal_protect_action); + break; + } + if(action_changed) + PHL_INFO("%s: Next action = %x\n", __FUNCTION__, phl_com->thermal_protect_action); + return action_changed; +} + +#endif /* CONFIG_PHL_THERMAL_PROTECT */ + + +enum rtw_hal_status +rtw_hal_thermal_protect_cfg_tx_duty( + void *hal, + u16 tx_duty_interval, + u8 ratio) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + u16 pause_duration = 0, tx_duration = 0; + + tx_duration = tx_duty_interval * ratio / 100; + pause_duration = tx_duty_interval - tx_duration; + PHL_INFO("%s: tx duty interval = %d tx duration = %d, pause duration = %d\n", + __FUNCTION__, tx_duty_interval, tx_duration, pause_duration); + + hsts = rtw_hal_mac_set_tx_duty(hal_info, pause_duration, tx_duration); + + return hsts; +} + +enum rtw_hal_status +rtw_hal_thermal_protect_stop_tx_duty( + void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: Stop tx duty!\n", __FUNCTION__); + + hsts = rtw_hal_mac_stop_tx_duty(hal_info); + + return hsts; +} \ No newline at end of file diff --git a/phl/hal_g6/hal_trx_mit.c b/phl/hal_g6/hal_trx_mit.c new file mode 100644 index 0000000..1a83183 --- /dev/null +++ b/phl/hal_g6/hal_trx_mit.c @@ -0,0 +1,118 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TRX_MIT_C_ +#include "hal_headers.h" + +static void +_hal_trx_mit_timer_convert(u32 timer, u8 *mul_ptr, + enum mac_ax_trx_mitigation_timer_unit *unit_ptr) +{ + /* timer = mul * unit */ + + const enum mac_ax_trx_mitigation_timer_unit UNIT_ARR[] = { + MAC_AX_MIT_64US, MAC_AX_MIT_128US, MAC_AX_MIT_256US, + MAC_AX_MIT_512US}; + const u8 UNIT_EXP_ARR[] = {6, 7, 8, 9}; /* 2^exp = unit */ + const u8 UNIT_ARR_LEN = 4; + + const u8 MUL_MAX = 0xff; /* 8 bits for mul */ + + u32 timer_ = 0; + u8 idx; + + for (idx = 0; idx < UNIT_ARR_LEN; idx++) { + + timer_ = timer >> UNIT_EXP_ARR[idx]; + + if (timer_ <= MUL_MAX) + break; + } + + if (timer_ > MUL_MAX) + *mul_ptr = MUL_MAX; + else + *mul_ptr = (u8)timer_; + + if (idx < UNIT_ARR_LEN) + *unit_ptr = UNIT_ARR[idx]; + else + *unit_ptr = UNIT_ARR[UNIT_ARR_LEN - 1]; +} + +enum rtw_hal_status rtw_hal_pcie_trx_mit(void *hal, u32 tx_timer, u8 tx_counter, + u32 rx_timer, u8 rx_counter) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + struct mac_ax_pcie_trx_mitigation mit_info; + struct mac_ax_txdma_ch_map txch_map; + struct mac_ax_rxdma_ch_map rxch_map; + + /* tx */ + + txch_map.ch0 = MAC_AX_PCIE_DISABLE; + txch_map.ch1 = MAC_AX_PCIE_DISABLE; + txch_map.ch2 = MAC_AX_PCIE_DISABLE; + txch_map.ch3 = MAC_AX_PCIE_DISABLE; + txch_map.ch4 = MAC_AX_PCIE_DISABLE; + txch_map.ch5 = MAC_AX_PCIE_DISABLE; + txch_map.ch6 = MAC_AX_PCIE_DISABLE; + txch_map.ch7 = MAC_AX_PCIE_DISABLE; + txch_map.ch8 = MAC_AX_PCIE_DISABLE; + txch_map.ch9 = MAC_AX_PCIE_DISABLE; + txch_map.ch10 = MAC_AX_PCIE_DISABLE; + txch_map.ch11 = MAC_AX_PCIE_DISABLE; + txch_map.ch12 = MAC_AX_PCIE_DISABLE; + + mit_info.txch_map = &txch_map; + mit_info.tx_counter = tx_counter; + + _hal_trx_mit_timer_convert(tx_timer, &(mit_info.tx_timer), + &(mit_info.tx_timer_unit)); + + PHL_INFO( + "%s :: mit_info.tx_timer == %d, mit_info.tx_timer_unit == %d\n", + __func__, mit_info.tx_timer, mit_info.tx_timer_unit); + + /* tx - END */ + + /* rx */ + + rxch_map.rxq = MAC_AX_PCIE_ENABLE; + rxch_map.rpq = MAC_AX_PCIE_ENABLE; + + mit_info.rxch_map = &rxch_map; + mit_info.rx_counter = rx_counter; + + _hal_trx_mit_timer_convert(rx_timer, &(mit_info.rx_timer), + &(mit_info.rx_timer_unit)); + + PHL_INFO( + "%s :: mit_info.rx_timer == %d, mit_info.rx_timer_unit == %d\n", + __func__, mit_info.rx_timer, mit_info.rx_timer_unit); + + /* rx - END */ + + if (rtw_hal_mac_pcie_trx_mit(hal_info, &mit_info) != + RTW_HAL_STATUS_SUCCESS) { + + PHL_INFO( + "%s :: failed to config pcie trx interrupt mitigation\n", + __func__); + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} diff --git a/phl/hal_g6/hal_twt.c b/phl/hal_g6/hal_twt.c new file mode 100644 index 0000000..5799aac --- /dev/null +++ b/phl/hal_g6/hal_twt.c @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TWT_C_ +#include "hal_headers.h" + +#ifdef CONFIG_PHL_TWT +enum rtw_hal_status +rtw_hal_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action) +{ + return rtw_hal_mac_twt_info_update(hal, twt_info, role, action); +} + +enum rtw_hal_status +rtw_hal_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action) +{ + return rtw_hal_mac_twt_sta_update(hal, macid, twt_id, action); +} + +enum rtw_hal_status +rtw_hal_twt_sta_announce(void *hal, u8 macid) +{ + return rtw_hal_mac_twt_sta_announce(hal, macid); +} +#endif /* CONFIG_PHL_TWT */ + diff --git a/phl/hal_g6/hal_tx.c b/phl/hal_g6/hal_tx.c new file mode 100644 index 0000000..c0ceb5a --- /dev/null +++ b/phl/hal_g6/hal_tx.c @@ -0,0 +1,414 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TX_C_ +#include "hal_headers.h" +/** + * this function will be used in read / write pointer mechanism and + * return the number of available read pointer + * @rptr: input, the read pointer + * @wptr: input, the write pointer + * @bndy: input, the boundary of read / write pointer mechanism + */ +u16 hal_calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy) +{ + u16 avail_rptr = 0; + + if (wptr >= rptr) + avail_rptr = wptr - rptr; + else if (rptr > wptr) + avail_rptr = wptr + (bndy - rptr); + + return avail_rptr; +} + + +/** + * this function will be used in read / write pointer mechanism and + * return the number of available write pointer + * @rptr: input, the read pointer + * @wptr: input, the write pointer + * @bndy: input, the boundary of read / write pointer mechanism + */ +u16 hal_calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy) +{ + u16 avail_wptr = 0; + + if (rptr > wptr) + avail_wptr = rptr - wptr - 1; + else if (wptr >= rptr) + avail_wptr = rptr + (bndy - wptr) - 1; + + return avail_wptr; +} + +/** + * rtw_hal_tx_chnl_mapping - query hw tx dma channel mapping to the sw xmit ring + * identified by macid, tid and band + * @hal: see struct hal_info_t + * @macid: input target macid is 0 ~ 127 + * @cat: input target packet category, see enum rtw_phl_ring_cat + * @band: input target band, 0 for band 0 / 1 for band 1 + * + * returns the mapping hw tx dma channel + */ +u8 rtw_hal_tx_chnl_mapping(void *hal, u16 macid, + enum rtw_phl_ring_cat cat, u8 band) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u8 tx_chnl = 0; + + tx_chnl = trx_ops->map_hw_tx_chnl(macid, cat, band); + + return tx_chnl; +} + +/** + * rtw_hal_get_fwcmd_queue_idx - get idx of fwcmd queue + * @hal: see struct hal_info_t + * + * returns u8 idx of fwcmd queue + */ +u8 rtw_hal_get_fwcmd_queue_idx(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + return trx_ops->get_fwcmd_queue_idx(); +} +void rtw_hal_cfg_txhci(void *hal, u8 en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en); + + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_txhci(hal_info, en)) + PHL_ERR("%s failure \n", __func__); +} + + + +enum rtw_hal_status rtw_hal_chk_allq_empty(void *hal, u8 *empty) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + FUNCIN(); + + return rtw_hal_mac_chk_allq_empty(hal_info, empty); +} + + +enum rtw_hal_status rtw_hal_fill_txdesc(void *hal, struct rtw_xmit_req *treq, + u8 *wd_buf, u32 *wd_len) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + + return rtw_hal_mac_ax_fill_txdesc(hal_info->mac, treq, wd_buf, wd_len); +} + +enum rtw_hal_status +rtw_hal_poll_hw_tx_done(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS; + + sts = rtw_hal_mac_poll_hw_tx_done(hal_info); + + return sts; +} + +enum rtw_hal_status +rtw_hal_hw_tx_resume(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS; + + sts = rtw_hal_mac_hw_tx_resume(hal_info); + + return sts; +} + +#ifdef CONFIG_PCI_HCI +/** + * rtw_hal_convert_qsel_to_tid - convert qsel to tid value + * @hal: see struct hal_info_t + * @qsel: HW queue selection + * + * returns enum RTW_HAL_STATUS + */ +u8 rtw_hal_convert_qsel_to_tid(void *hal, u8 qsel_id, u8 tid_indic) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->qsel_to_tid(hal_info, qsel_id, tid_indic); + + return hstatus; +} +/** + * rtw_hal_tx_res_query - query current HW tx resource with specifc dma channel + * @hal: see struct hal_info_t + * @dma_ch: the target dma channel + * @host_idx: current host index of this channel + * @hw_idx: current hw index of this channel + * + * this function returns the number of available tx resource + * NOTE, input host_idx and hw_idx ptr shall NOT be NULL + */ +u16 rtw_hal_tx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u16 res_num = 0; + + res_num = trx_ops->query_tx_res(hal_info->hal_com, dma_ch, host_idx, + hw_idx); + + return res_num; +} + + +/** + * rtw_hal_query_txch_num - query total hw tx dma channels number + * + * returns the number of hw tx dma channel + */ +u8 rtw_hal_query_txch_num(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + u8 ch_num = 0; + + ch_num = trx_ops->query_txch_num(); + + return ch_num; +} + +enum rtw_hal_status rtw_hal_trx_init(void *hal, u8 *txbd_buf, u8 *rxbd_buf) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->init(hal_info, txbd_buf, rxbd_buf); + + return hstatus; +} + +void rtw_hal_trx_deinit(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + trx_ops->deinit(hal_info); +} + +/** + * rtw_hal_update_wd_page - update wd page for xmit packet + * @hal: see struct hal_info_t + * @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_update_wd_page(void *hal, void *phl_pkt_req) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->update_wd(hal_info, phl_pkt_req); + + return hstatus; +} + +/** + * rtw_hal_update_txbd - update tx bd for xmit packet + * @hal: see struct hal_info_t + * @wd: buffer pointer of wd page to fill in txbd + * + * returns enum RTW_HAL_STATUS + * NOTE, this function is PCIe specific function + */ +enum rtw_hal_status rtw_hal_update_txbd(void *hal, void *txbd, void *wd, u8 dma_ch, u16 wd_num) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->update_txbd(hal, txbd, wd, dma_ch, wd_num); + + return hstatus; +} + + +/** + * rtw_hal_update_trigger_txstart - trigger hw to start tx + * @hal: see struct hal_info_t + * @txbd: the target txbd to update + * @dma_ch: the dma channel index of this txbd_ring + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_trigger_txstart(void *hal, void *txbd, u8 dma_ch) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->tx_start(hal, txbd, dma_ch); + + return hstatus; +} + +u8 rtw_hal_poll_txdma_idle(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + FUNCIN(); + + return trx_ops->poll_txdma_idle(hal_info); +} + +#endif /*CONFIG_PCI_HCI*/ + +#ifdef CONFIG_USB_HCI +enum rtw_hal_status rtw_hal_trx_init(void *hal) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->init(hal_info); + + return hstatus; +} + +void rtw_hal_trx_deinit(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + trx_ops->deinit(hal_info); +} + +u8 rtw_hal_get_bulkout_id(void *hal, u8 dma_ch, u8 mode) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->get_bulkout_id(hal, dma_ch, mode); + + return hstatus; +} + +enum rtw_hal_status + rtw_hal_usb_tx_agg_cfg(void *hal, u8* wd_buf, u8 agg_num) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + hstatus = trx_ops->usb_tx_agg_cfg(hal, wd_buf, agg_num); + + return hstatus; +} + + +u8 rtw_hal_get_max_bulkout_wd_num(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + return trx_ops->get_max_bulkout_wd_num(hal); +} + +/** + * rtw_hal_fill_wd - fill wd-info and wd-boddy for xmit packet + * @hal: see struct hal_info_t + * @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req + * + * returns enum RTW_HAL_STATUS + */ +enum rtw_hal_status rtw_hal_fill_wd(void *hal, + struct rtw_xmit_req *tx_req, + u8 *wd_buf, u32 *wd_len) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + +#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL + if (tx_req->mdata.spe_rpt) { + if (tx_req->mdata.data_tx_cnt_lmt_en) + hal_info->hal_com->spe_pkt_cnt_lmt = tx_req->mdata.data_tx_cnt_lmt; + } +#endif + hstatus = trx_ops->hal_fill_wd(hal_info, tx_req, wd_buf, wd_len); + + return hstatus; +} + +#endif + +#ifdef CONFIG_SDIO_HCI +void rtw_hal_sdio_tx_cfg(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + + rtw_hal_mac_sdio_tx_cfg(hal_info->hal_com); +} + +enum rtw_hal_status rtw_hal_sdio_tx(void *hal, u8 dma_ch, u8 *buf, u32 buf_len, + u8 agg_count, u16 *pkt_len, u8 *wp_offset) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u32 txaddr; + u32 txlen; + bool ready; + + + ready = rtw_hal_mac_sdio_check_tx_allow(hal_info->hal_com, dma_ch, + buf, buf_len, agg_count, + pkt_len, wp_offset, &txaddr, + &txlen); + if (!ready) + return RTW_HAL_STATUS_RESOURCE; + + hal_sdio_cmd53_w(hal_info->hal_com, txaddr, txlen, buf); + + return RTW_HAL_STATUS_SUCCESS; +} +#endif /* CONFIG_SDIO_HCI */ + +#define TX_DBG_STATUS_DUMP_INTERVAL 30000 /* ms */ +void rtw_hal_tx_dbg_status_dump(void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_mac_dbg_dump_cfg cfg = {0}; + static u32 last_dump_t = 0; + + cfg.tx_flow_dbg = 1; + + if (phl_get_passing_time_ms(last_dump_t) >= TX_DBG_STATUS_DUMP_INTERVAL) { + rtw_hal_mac_dbg_status_dump(hal_info, &cfg); + last_dump_t = _os_get_cur_time_ms(); + } +} + diff --git a/phl/hal_g6/hal_tx.h b/phl/hal_g6/hal_tx.h new file mode 100644 index 0000000..bc03919 --- /dev/null +++ b/phl/hal_g6/hal_tx.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_TX_H_ +#define _HAL_TX_H_ + +/** + * this function will be used in read / write pointer mechanism and + * return the number of available read pointer + * @rptr: input, the read pointer + * @wptr: input, the write pointer + * @bndy: input, the boundary of read / write pointer mechanism + */ +u16 hal_calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy); + +/** + * this function will be used in read / write pointer mechanism and + * return the number of available write pointer + * @rptr: input, the read pointer + * @wptr: input, the write pointer + * @bndy: input, the boundary of read / write pointer mechanism + */ +u16 hal_calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy); + +#ifdef CONFIG_PCI_HCI +/** + * rtw_hal_query_txch_num - query total hw tx dma channels number + * + * returns the number of hw tx dma channel + */ +u8 rtw_hal_query_txch_num(void *hal); +#endif + +#endif /*_HAL_TX_H_*/ diff --git a/phl/hal_g6/hal_txpwr.c b/phl/hal_g6/hal_txpwr.c new file mode 100644 index 0000000..513ca82 --- /dev/null +++ b/phl/hal_g6/hal_txpwr.c @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TXPWR_C_ +#include "hal_headers.h" + +const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_rf_get_pw_lmt_regu_type_str(hal_info, band); +} + +bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + + return rtw_hal_mac_get_pwr_lmt_en_val(hal_info->hal_com, band_idx); +} + +enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx, + enum phl_pwr_table pwr_table) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum phl_phy_idx phy_idx = HW_PHY_0; + + if (band_idx == 1) + phy_idx = HW_PHY_1; + + return rtw_hal_rf_set_power(hal_info, phy_idx, pwr_table); +} + diff --git a/phl/hal_g6/hal_txpwr.h b/phl/hal_g6/hal_txpwr.h new file mode 100644 index 0000000..9986fcd --- /dev/null +++ b/phl/hal_g6/hal_txpwr.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c)2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_TXPWR_H_ +#define _HAL_TXPWR_H_ + +const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band); + +bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx); + +enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx, + enum phl_pwr_table pwr_table); + +#endif \ No newline at end of file diff --git a/phl/hal_g6/hal_usb.c b/phl/hal_g6/hal_usb.c new file mode 100644 index 0000000..599d46f --- /dev/null +++ b/phl/hal_g6/hal_usb.c @@ -0,0 +1,291 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_USB_C_ +#include "hal_headers.h" +#include "hal_usb.h" + +#ifdef CONFIG_USB_HCI +u8 usb_read8(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u8 data = 0; + + request = 0x05; + requesttype = 0x01;/* read_in */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 1; + + _os_usbctrl_vendorreq(hal->drv_priv, request, wvalue, index, + &data, len, requesttype); + + return data; +} + +u16 usb_read16(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u16 data = 0; + + request = 0x05; + requesttype = 0x01;/* read_in */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 2; + + _os_usbctrl_vendorreq(hal->drv_priv, request, wvalue, index, + &data, len, requesttype); + return le16_to_cpu(data); + +} + +u32 usb_read32(struct rtw_hal_com_t *hal, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u32 data = 0; + + request = 0x05; + requesttype = 0x01;/* read_in */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 4; + + _os_usbctrl_vendorreq(hal->drv_priv, request, wvalue, index, + &data, len, requesttype); + return le32_to_cpu(data); +} + +int usb_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u8 data; + int ret; + + + request = 0x05; + requesttype = 0x00;/* write_out */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 1; + data = val; + + ret = _os_usbctrl_vendorreq(hal->drv_priv, + request, wvalue, index, &data, len, requesttype); + return ret; +} + +int usb_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u16 data; + int ret; + + request = 0x05; + requesttype = 0x00;/* write_out */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 2; + data = cpu_to_le16(val); + + ret = _os_usbctrl_vendorreq(hal->drv_priv, + request, wvalue, index, &data, len, requesttype); + + return ret; + +} + +int usb_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u32 data; + int ret; + + request = 0x05; + requesttype = 0x00;/* write_out */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = 4; + data = cpu_to_le32(val); + + ret = _os_usbctrl_vendorreq(hal->drv_priv, + request, wvalue, index, &data, len, requesttype); + + return ret; + +} + +int usb_write_mem(struct rtw_hal_com_t *hal, u32 addr, u32 length, u8 *pdata) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + int ret; + u8 buf[MAX_VENDOR_REQ_CMD_SIZE] = {0}; + + request = 0x05; + requesttype = 0x00;/* write_out */ + index = (u16)((addr & 0x00ff0000) >> 16); + wvalue = (u16)(addr & 0x0000ffff); + len = (u16)length; + + _os_mem_cpy(hal->drv_priv, buf, pdata, len); + + ret = _os_usbctrl_vendorreq(hal->drv_priv, + request, wvalue, index, pdata, len, requesttype); + + return ret; + +} +#ifdef RTW_WKARD_BUS_WRITE +static int usb_write_post_cfg(struct rtw_hal_com_t *hal, u32 addr, u32 val) +{ + struct hal_info_t *hal_info = hal->hal_priv; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + if(NULL != hal_ops->write_reg_post_cfg) { + hal_status = hal_ops->write_reg_post_cfg(hal_info, addr, val); + } + + return hal_status; +} +#endif +static void hal_usb_set_io_ops_gen(struct rtw_hal_com_t *hal, struct hal_io_ops *pops) +{ + /*_rtw_memset((u8 *)pops, 0, sizeof(struct hal_io_ops));*/ + _os_mem_set(hal->drv_priv, (u8 *)pops, 0, sizeof(struct hal_io_ops)); + + pops->_read8 = &usb_read8; + pops->_read16 = &usb_read16; + pops->_read32 = &usb_read32; + pops->_read_mem = NULL; + + pops->_write8 = &usb_write8; + pops->_write16 = &usb_write16; + pops->_write32 = &usb_write32; + pops->_write_mem = &usb_write_mem; +#ifdef RTW_WKARD_BUS_WRITE + pops->_write_post_cfg = &usb_write_post_cfg; +#endif +} + +void hal_usb_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *pops) +{ + hal_usb_set_io_ops_gen(hal, pops); + /*hal_usb_set_io_ops_8852au(hal, pops);*/ +} + + +/* To avoid RX affect TX throughput */ +#ifdef CONFIG_PHL_USB_RX_AGGREGATION +void rtw_hal_usb_adjust_txagg(void *h) +{ + #if 0 + struct hal_info_t *hal = (struct hal_info_t *)h; + struct registry_priv *registry_par = &padapter->registrypriv; + + if (!registry_par->dynamic_agg_enable) + return; + + if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter) + || IS_HARDWARE_TYPE_8822CU(padapter) || IS_HARDWARE_TYPE_8814BU(padapter)) + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL); + #endif +} +#endif /* CONFIG_PHL_USB_RX_AGGREGATION */ + +enum rtw_hal_status rtw_hal_force_usb_switch(void *h, enum usb_type type) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + u32 mode = hal_mac_get_cur_usb_mode(hal); + bool bswitch = false; + + bswitch = ((enum usb_type)mode != type) ? (true) : (false); + PHL_INFO("%s, switch from %d to %d\n", __func__, + mode , type); + if(bswitch) + return hal_mac_force_usb_switch(hal); + else + return RTW_HAL_STATUS_SUCCESS; +} + +u32 rtwl_hal_get_cur_usb_mode(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + /*refer to enum usb_type*/ + return hal_mac_get_cur_usb_mode(hal); +} +u32 rtwl_hal_get_usb_support_ability(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + /* + * refers to _usb.h + * #define SWITCHMODE 0x2 + * #define FORCEUSB3MODE 0x1 + * #define FORCEUSB2MODE 0x0 + */ + return hal_mac_get_usb_support_ability(hal); +} + +enum rtw_rx_status rtw_hal_get_usb_status(void *h) +{ + struct hal_info_t *hal = (struct hal_info_t *)h; + struct mac_ax_adapter *mac = hal_to_mac(hal); + struct mac_ax_ops *hal_mac_ops = mac->ops; + u32 mac_usb_sts; + u32 val; + + mac_usb_sts = hal_mac_ops->get_hw_value(mac, MAC_AX_HW_GET_USB_STS, &val); + + switch (mac_usb_sts) { + case MACSUCCESS: + case MACNOITEM: + return RTW_STATUS_RX_OK; + case MACRXDMAHANG: + return RTW_STATUS_RXDMA_HANG; + case MACUSBRXHANG: + return RTW_STATUS_RXFIFO_HANG; + default: + return RTW_STATUS_RX_OK; + } +} +#endif /*CONFIG_USB_HCI*/ diff --git a/phl/hal_g6/hal_usb.h b/phl/hal_g6/hal_usb.h new file mode 100644 index 0000000..8306b88 --- /dev/null +++ b/phl/hal_g6/hal_usb.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_USB_H_ +#define _HAL_USB_H_ + +#ifdef CONFIG_USB_HCI +#define MAX_VENDOR_REQ_CMD_SIZE 254 + +void hal_usb_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *ops); + +#ifdef CONFIG_RTL8852A +#include "rtl8852a/rtl8852a.h" +#endif + +#ifdef CONFIG_RTL8852B +#include "rtl8852b/rtl8852b.h" +#endif + +#ifdef CONFIG_RTL8852C +#include "rtl8852c/rtl8852c.h" +#endif + +static inline void hal_set_ops_usb(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + #ifdef CONFIG_RTL8852A + if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852A) { + hal_set_ops_8852au(phl_com, hal); + hal_hook_trx_ops_8852au(hal); + } + #endif + + #ifdef CONFIG_RTL8852B + if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852B) { + hal_set_ops_8852bu(phl_com, hal); + hal_hook_trx_ops_8852bu(hal); + } + #endif + #ifdef CONFIG_RTL8852C + if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852C) { + hal_set_ops_8852cu(phl_com, hal); + hal_hook_trx_ops_8852cu(hal); + } + #endif + +} +#endif /*CONFIG_USB_HCI*/ +#endif /* _HAL_USB_H_ */ diff --git a/phl/hal_g6/hal_wow.c b/phl/hal_g6/hal_wow.c new file mode 100644 index 0000000..2693aae --- /dev/null +++ b/phl/hal_g6/hal_wow.c @@ -0,0 +1,447 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_WOW_C_ +#include "hal_headers.h" + +#ifdef CONFIG_WOWLAN + +#define case_rsn(rsn) \ + case MAC_AX_WOW_##rsn: return RTW_WOW_RSN_##rsn + +u8 _trans_wake_rsn(u8 mac_rsn) +{ + switch (mac_rsn) { + case_rsn(RX_PAIRWISEKEY); + case_rsn(RX_GTK); + case_rsn(RX_FOURWAY_HANDSHAKE); + case_rsn(RX_DISASSOC); + case_rsn(RX_DEAUTH); + case_rsn(RX_ARP_REQUEST); + case_rsn(RX_NS); + case_rsn(RX_EAPREQ_IDENTIFY); + case_rsn(FW_DECISION_DISCONNECT); + case_rsn(RX_MAGIC_PKT); + case_rsn(RX_UNICAST_PKT); + case_rsn(RX_PATTERN_PKT); + case_rsn(RTD3_SSID_MATCH); + case_rsn(RX_DATA_PKT); + case_rsn(RX_SSDP_MATCH); + case_rsn(RX_WSD_MATCH); + case_rsn(RX_SLP_MATCH); + case_rsn(RX_LLTD_MATCH); + case_rsn(RX_MDNS_MATCH); + case_rsn(RX_REALWOW_V2_WAKEUP_PKT); + case_rsn(RX_REALWOW_V2_ACK_LOST); + case_rsn(RX_REALWOW_V2_TX_KAPKT); + case_rsn(ENABLE_FAIL_DMA_IDLE); + case_rsn(ENABLE_FAIL_DMA_PAUSE); + case_rsn(RTIME_FAIL_DMA_IDLE); + case_rsn(RTIME_FAIL_DMA_PAUSE); + case_rsn(RX_SNMP_MISMATCHED_PKT); + case_rsn(RX_DESIGNATED_MAC_PKT); + case_rsn(NLO_SSID_MACH); + case_rsn(AP_OFFLOAD_WAKEUP); + case_rsn(DMAC_ERROR_OCCURRED); + case_rsn(EXCEPTION_OCCURRED); + case_rsn(L0_TO_L1_ERROR_OCCURRED); + case_rsn(ASSERT_OCCURRED); + case_rsn(L2_ERROR_OCCURRED); + case_rsn(WDT_TIMEOUT_WAKE); + case_rsn(RX_ACTION); + case_rsn(CLK_32K_UNLOCK); + case_rsn(CLK_32K_LOCK); + default: + return RTW_WOW_RSN_MAX; + } +} + +#define MAX_POLLING_WOW_FW_STS_CNT 1000 /* 50ms */ + +static enum rtw_hal_status _hal_check_wow_fw_ready(void *hal, u8 func_en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + void* drv_priv = hal_to_drvpriv(hal_info); + u8 fw_status = 0; + u32 poll_cnt = 0; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : start polling... (func_en %d)\n", __func__, func_en); + + /* polling fw status */ + while (1) { + + if (poll_cnt >= MAX_POLLING_WOW_FW_STS_CNT) { + PHL_ERR("%s polling fw status timeout !!!\n", __func__); + hstats = RTW_HAL_STATUS_FAILURE; + break; + } + + hstats = rtw_hal_mac_get_wow_fw_status(hal_info, &fw_status, + func_en); + + if (RTW_HAL_STATUS_SUCCESS != hstats) { + + PHL_ERR("%s : status %u\n", __func__, fw_status); + break; + } + + if (fw_status) { + hstats = RTW_HAL_STATUS_SUCCESS; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, + "%s : polling count %u\n", __func__, poll_cnt); + break; + } else { + + _os_delay_us(drv_priv, 50); + + } + poll_cnt++; + + } + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : finish polling... (func_en %d)\n", __func__, func_en); + + return hstats; +} + +enum rtw_hal_status rtw_hal_get_wake_rsn(void *hal, enum rtw_wow_wake_reason *wake_rsn, u8 *reset) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + u8 mac_rsn = 0; + + hstats = rtw_hal_mac_get_wake_rsn(hal_info, &mac_rsn, reset); + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : wake rsn from mac in hex 0x%x (reset %d).\n", + __func__, mac_rsn, *reset); + + if (RTW_HAL_STATUS_SUCCESS != hstats) { + PHL_ERR("%s : rtw_hal_mac_get_wake_rsn failed.\n", __func__); + } else { + *wake_rsn = (mac_rsn == 0) ? RTW_WOW_RSN_UNKNOWN : _trans_wake_rsn(mac_rsn) ; + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : wake reason %u.\n", __func__, *wake_rsn); + } + + return hstats; +} + +enum rtw_hal_status rtw_hal_cfg_wow_sleep(void *hal, u8 sleep) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + + hstats = rtw_hal_mac_cfg_wow_sleep(hal_info, sleep); + + if (RTW_HAL_STATUS_SUCCESS != hstats) + PHL_ERR("%s : sleep %u\n", __func__, sleep); + + return hstats; +} + +enum rtw_hal_status rtw_hal_get_wow_aoac_rpt(void *hal, struct rtw_aoac_report *aoac_info, u8 rx_ready) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + FUNCIN(); + + /* get aoac report */ + hstatus = rtw_hal_mac_get_aoac_rpt(hal_info, aoac_info, rx_ready); + + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s(): failed with status(%u)\n", __func__, hstatus); + + FUNCOUT(); + + return hstatus; +} + + +enum rtw_hal_status rtw_hal_reset_pkt_ofld_state(void *hal) +{ + + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE; + + hstats = rtw_hal_mac_reset_pkt_ofld_state(hal_info); + + if (RTW_HAL_STATUS_SUCCESS != hstats) + PHL_ERR("%s : failed \n", __func__); + + return hstats; +} + +#ifdef CONFIG_PCI_HCI +enum rtw_hal_status rtw_hal_wow_cfg_txdma(void *hal, u8 en) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_trx_ops *trx_ops = hal_info->trx_ops; + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en); + + trx_ops->cfg_wow_txdma(hal_info, en); + + return RTW_HAL_STATUS_SUCCESS; +} +#endif +enum rtw_hal_status rtw_hal_wow_init(struct rtw_phl_com_t *phl_com, void *hal, + struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + FUNCIN_WSTS(hal_status); + + /* download wowlan fw and do related tasks needed after redownload fw */ + hal_status = hal_ops->hal_wow_init(phl_com, hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s successfully done.\n", __func__); + + FUNCOUT_WSTS(hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_wow_deinit(struct rtw_phl_com_t *phl_com, void *hal, + struct rtw_phl_stainfo_t *sta) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + FUNCIN_WSTS(hal_status); + + /* download wowlan fw and do related tasks needed after redownload fw */ + hal_status = hal_ops->hal_wow_deinit(phl_com, hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + return hal_status; + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s successfully done.\n", __func__); + + FUNCOUT_WSTS(hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_wow_func_en(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg) +{ + + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + FUNCIN(); + + do { + /* config wow cam : pattern match */ +#ifndef RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG + hstatus = rtw_hal_mac_cfg_wow_cam(hal_info, macid, true, cfg->pattern_match_info); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; +#endif + /* gtk offload */ + hstatus = rtw_hal_mac_cfg_gtk_ofld(hal_info, macid, true, cfg->gtk_ofld_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* arp offload */ + hstatus = rtw_hal_mac_cfg_arp_ofld(hal_info, macid, true, cfg->arp_ofld_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* ndp offload */ + hstatus = rtw_hal_mac_cfg_ndp_ofld(hal_info, macid, true, cfg->ndp_ofld_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* config keep alive */ + hstatus = rtw_hal_mac_cfg_keep_alive(hal_info, macid, true, cfg->keep_alive_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* config disconnect detection */ + hstatus = rtw_hal_mac_cfg_disc_dec(hal_info, macid, true, cfg->disc_det_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* realwow offload */ + hstatus = rtw_hal_mac_cfg_realwow(hal_info, macid, true, cfg->realwow_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* config gpio */ + hstatus = rtw_hal_mac_cfg_dev2hst_gpio(hal_info, true, cfg->wow_gpio); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + } while(0); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus); + + FUNCOUT(); + + return hstatus; +} + +enum rtw_hal_status rtw_hal_wow_func_dis(struct rtw_phl_com_t *phl_com, void *hal, u16 macid) +{ + + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + FUNCIN(); + + /* cancel pattern match */ +#ifndef RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG + hstatus = rtw_hal_mac_cfg_wow_cam(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_wow_cam failed \n"); +#endif + /* cancel gtk offload */ + hstatus = rtw_hal_mac_cfg_gtk_ofld(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_gtk_ofld failed \n"); + /* cancel arp offload */ + hstatus = rtw_hal_mac_cfg_arp_ofld(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_arp_ofld failed \n"); + /* cancel ndp offload */ + hstatus = rtw_hal_mac_cfg_ndp_ofld(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_ndp_ofld failed \n"); + /* disable keep alive */ + hstatus = rtw_hal_mac_cfg_keep_alive(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_keep_alive failed \n"); + /* disable disconect detection */ + hstatus = rtw_hal_mac_cfg_disc_dec(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_disc_dec failed \n"); + /* realwow offload */ + hstatus = rtw_hal_mac_cfg_realwow(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_realwow_ofld failed \n"); + /* config gpio */ + hstatus = rtw_hal_mac_cfg_dev2hst_gpio(hal_info, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_dev2hst_gpio failed \n"); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus); + + FUNCOUT(); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_wow_func_start(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + do { + hstatus = rtw_hal_mac_cfg_wow_wake(hal_info, macid, true, cfg->wow_wake_cfg); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* poll fw status */ + hstatus = _hal_check_wow_fw_ready(hal_info, 1); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + } while(0); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus); + + return hstatus; +} + +enum rtw_hal_status rtw_hal_wow_func_stop(struct rtw_phl_com_t *phl_com, void *hal, u16 macid) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + /* config wow ctrl */ + hstatus = rtw_hal_mac_cfg_wow_wake(hal_info, macid, false, NULL); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_wow_wake failed \n"); + + hstatus = _hal_check_wow_fw_ready(hal_info, 0); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] _hal_poll_wow_fw_status failed \n"); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus); + + return hstatus; +} + +enum rtw_hal_status rtw_hal_set_wowlan(struct rtw_phl_com_t *phl_com, void *hal, u8 enter) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + hal_status = rtw_hal_mac_set_wowlan(hal_info, enter); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status); + + return hal_status; +} + +static enum rtw_hal_status _wow_chk_txq_empty(struct hal_info_t *hal_info, u8 *empty) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_wow_chk_txq_empty(hal_info, empty); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status); + + return hal_status; +} + +static enum rtw_hal_status _wow_wde_drop(struct hal_info_t *hal_info, u8 band) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_mac_wow_wde_drop(hal_info, band); + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status); + + return hal_status; +} + +#define MAX_WOW_DROP_HWTX_TRYCNT 3 +enum rtw_hal_status rtw_hal_wow_drop_tx(void *hal, u8 band) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + u8 empty = 0; + u8 i = 0; + + for (i = 0; i < MAX_WOW_DROP_HWTX_TRYCNT; i++) { + + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : chk/drop for the %d time\n", __func__, i + 1); + + if (RTW_HAL_STATUS_SUCCESS != _wow_chk_txq_empty(hal_info, &empty)) + PHL_WARN("[wow] _wow_chk_txq_empty failed.\n"); + + /* force drop wde if txq is not empty */ + if (!empty) + _wow_wde_drop(hal_info, band); + else + break; + } + + if (!empty) { + PHL_WARN("[wow] %s : chk/drop fail!\n", __func__); + } else { + PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : chk/drop ok.\n", __func__); + hal_status = RTW_HAL_STATUS_SUCCESS; + } + + return hal_status; +} + +#endif /* CONFIG_WOWLAN */ diff --git a/phl/hal_g6/hal_wow.h b/phl/hal_g6/hal_wow.h new file mode 100644 index 0000000..05e4934 --- /dev/null +++ b/phl/hal_g6/hal_wow.h @@ -0,0 +1,23 @@ +/****************************************************************************** + * + * Copyright(c)2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_WOW_H_ +#define _HAL_WOW_H_ + +#ifdef CONFIG_WOWLAN +/* ... */ +#endif /* CONFIG_WOWLAN */ + +#endif /* _HAL_WOW_H_ */ + diff --git a/phl/hal_g6/mac/chip_cfg.h b/phl/hal_g6/mac/chip_cfg.h new file mode 100644 index 0000000..8d7e277 --- /dev/null +++ b/phl/hal_g6/mac/chip_cfg.h @@ -0,0 +1,81 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_CHIP_CFG_H_ +#define _MAC_AX_CHIP_CFG_H_ + +#ifndef __cplusplus /* for win/linux driver */ + +/* Modify MakeFile to reduce code size (chip & interface) */ +#ifdef CONFIG_RTL8852A +#define MAC_AX_8852A_SUPPORT 1 +#else +#define MAC_AX_8852A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8852B +#define MAC_AX_8852B_SUPPORT 1 +#else +#define MAC_AX_8852B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8852C +#define MAC_AX_8852C_SUPPORT 1 +#else +#define MAC_AX_8852C_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8192XB +#define MAC_AX_8192XB_SUPPORT 1 +#else +#define MAC_AX_8192XB_SUPPORT 0 +#endif + +/* Interface support */ +#ifdef CONFIG_SDIO_HCI +#define MAC_AX_SDIO_SUPPORT 1 +#else +#define MAC_AX_SDIO_SUPPORT 0 +#endif +#ifdef CONFIG_USB_HCI +#define MAC_AX_USB_SUPPORT 1 +#else +#define MAC_AX_USB_SUPPORT 0 +#endif +#ifdef CONFIG_PCI_HCI +#define MAC_AX_PCIE_SUPPORT 1 +#else +#define MAC_AX_PCIE_SUPPORT 0 +#endif + +#else /* for WD1 test program */ + +/* Modify MakeFile to reduce code size (chip & interface) */ + +#define MAC_AX_8852A_SUPPORT 1 +#define MAC_AX_8852B_SUPPORT 1 +#define MAC_AX_8852C_SUPPORT 1 +#define MAC_AX_8192XB_SUPPORT 1 + +/* Interface support */ +#define MAC_AX_SDIO_SUPPORT 1 +#define MAC_AX_USB_SUPPORT 1 +#define MAC_AX_PCIE_SUPPORT 1 + +#endif // #else /* for WD1 test program */ + +#endif + diff --git a/phl/hal_g6/mac/chip_cfg_drv.h b/phl/hal_g6/mac/chip_cfg_drv.h new file mode 100644 index 0000000..5bf09ce --- /dev/null +++ b/phl/hal_g6/mac/chip_cfg_drv.h @@ -0,0 +1,62 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_CHIP_CFG_H_ +#define _MAC_AX_CHIP_CFG_H_ + +/* Modify MakeFile to reduce code size (chip & interface) */ +#ifdef CONFIG_RTL8852A +#define MAC_AX_8852A_SUPPORT 1 +#else +#define MAC_AX_8852A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8852B +#define MAC_AX_8852B_SUPPORT 1 +#else +#define MAC_AX_8852B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8852C +#define MAC_AX_8852C_SUPPORT 1 +#else +#define MAC_AX_8852C_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8192XB +#define MAC_AX_8192XB_SUPPORT 1 +#else +#define MAC_AX_8192XB_SUPPORT 0 +#endif + +/* Interface support */ +#ifdef CONFIG_SDIO_HCI +#define MAC_AX_SDIO_SUPPORT 1 +#else +#define MAC_AX_SDIO_SUPPORT 0 +#endif +#ifdef CONFIG_USB_HCI +#define MAC_AX_USB_SUPPORT 1 +#else +#define MAC_AX_USB_SUPPORT 0 +#endif +#ifdef CONFIG_PCI_HCI +#define MAC_AX_PCIE_SUPPORT 1 +#else +#define MAC_AX_PCIE_SUPPORT 0 +#endif +#endif + diff --git a/phl/hal_g6/mac/errors.h b/phl/hal_g6/mac/errors.h new file mode 100644 index 0000000..218f5b2 --- /dev/null +++ b/phl/hal_g6/mac/errors.h @@ -0,0 +1,274 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_ERR_H_ +#define _MAC_AX_ERR_H_ + +#define MACSUCCESS 0 /* Success return value */ +#define MACPFCB 1 /* Callback of platform is null */ +#define MACPFED 2 /* Endian of platform error */ +#define MACBADDR 3 /* Invalid base address */ +#define MACLSUS 4 /* Leave suspend error */ +#define MACNPTR 5 /* Pointer is null */ +#define MACCHIPID 6 /* Chip ID is undefined */ +#define MACADAPTER 7 /* Can not get MAC adapter */ +#define MACSTCAL 8 /* Unexpected structure alignment */ +#define MACNOBUF 9 /* Buffer space is not enough */ +#define MACBUFSZ 10 /* Buffer size error */ +#define MACNOITEM 11 /* Invalid item */ +#define MACPOLLTO 12 /* Polling timeout */ +#define MACPWRSW 13 /* Power switch fail */ +#define MACBUFALLOC 14 /* Buffer allocation fail */ +#define MACWQBUSY 15 /* Work queue is busy */ +#define MACCMP 16 /* Failed compare result */ +#define MACINTF 17 /* Wrong interface */ +#define MACFWBIN 18 /* Incorrect FW bin file */ +#define MACFFCFG 19 /* Wrong FIFO configuration */ +#define MACSAMACID 20 /* Same MACID */ +#define MACMACIDFL 21 /* MACID full */ +#define MACNOFW 22 /* There is no FW */ +#define MACPROCBUSY 23 /* Process is busy */ +#define MACPROCERR 24 /* state machine error */ +#define MACEFUSEBANK 25 /* switch efuse bank fail */ +#define MACEFUSEREAD 26 /* read efuse fail */ +#define MACEFUSEWRITE 27 /* write efuse fail */ +#define MACEFUSESIZE 28 /* efuse size error */ +#define MACEFUSEPARSE 29 /* eeprom parsing fail */ +#define MACEFUSECMP 30 /* compare efuse fail */ +#define MACSECUREON 31 /* secure on, no host indirect access */ +#define MACTXCHDMA 32 /* invalid tx dma channel */ +#define MACADDRCAMUPDERR 33 /* address cam update error */ +#define MACPWRSTAT 34 /* Power state error */ +#define MACSDIOMIXMODE 35 /* SDIO Tx mix mode */ +#define MACSDIOSEQERR 36 /* SDIO Tx sequence error */ +#define MACHFCH2CQTA 37 /* HCI FC invalid H2C quota */ +#define MACHFCCH011QTA 38 /* HCI FC invalid CH0-11 quota */ +#define MACHFCCH011GRP 39 /* HCI FC invalid CH0-11 group */ +#define MACHFCPUBQTA 40 /* HCI FC invalid public quota */ +#define MACHFCPUBINFO 41 /* HCI FC public info error */ +#define MACRFPMCAM 42 /* RX forwarding PM CAM access fail */ +#define MACHFSWDENOTNUF 43 /* HCI FC WDE page not enough */ +#define MACHFSPLENOTNUF 44 /* HCI FC PLE page not enough */ +#define MACMEMRO 45 /* Address is not writable */ +#define MACFUNCINPUT 46 /* invalid function input */ +#define MACALRDYON 47 /* MAC has already powered on */ +#define MACADDRCAMFL 48 /* ADDRESS CAM full */ +#define MACBSSIDCAMFL 49 /* BSSID CAM full */ +#define MACGPIOUSED 50 /* GPIO is used */ +#define MACDLELINK 51 /* DLE link error */ +#define MACPOLLTXIDLE 52 /* polling Tx idle fail */ +#define MACPARSEERR 53 /* parse report err */ +#define MACROLEINITFL 54 /* Role API init fail or C2H notify role init fail */ +#define MACPORTCFGTYPE 55 /* Port cfg type error */ +#define MACPORTCFGPORT 56 /* Port cfg port error */ +#define MACWNGKEYTYPE 57 /* Sec cam wrong key type*/ +#define MACKEYNOTEXT 58 /* Delete key , key not exist*/ +#define MACSECCAMFL 59 /* SEC CAM full*/ +#define MACADDRCAMKEYFL 60 /* Addr CAM key full*/ +#define MACNOROLE 61 /* SEC no this role*/ +#define MACHWNOTEN 62 /* hw module not enable*/ +#define MACPTMTXFAIL 63 /* platform TX fail*/ +#define MACSSLINK 64 /* STA scheduler link error */ +#define MACDBGPORTSEL 65 /* Debug port sel error */ +#define MACDBGPORTDMP 66 /* Debug port dump error */ +#define MACCPWMSEQERR 67 /* CPWM sequence mismatch */ +#define MACCPWMSTATERR 68 /* CPWM state mismatch */ +#define MACCPUSTATE 69 /* Incorrect CPU state */ +#define MACPSSTATFAIL 70 /* protocol power state check fail */ +#define MACLV1STEPERR 71 /* lv1 rcvy step sel error */ +#define MACFWCHKSUM 72 /* FW checksum is incorrect */ +#define MACFWSECBOOT 73 /* FW security boot is failed */ +#define MACFWCUT 74 /* Mismatch chip and FW cut */ +#define MACSUBSPCERR 75 /* Beacon sub-space setting fail */ +#define MACLENCMP 76 /* Length is not match */ +#define MACCHKSUMEMPTY 77 /* Checksum report empty */ +#define MACCHKSUMFAIL 78 /* Checksum report fail */ +#define MACVERERR 79 /* Map and mask version mismatch */ +#define MACFWNONRDY 80 /* FW not ready h2c error*/ +#define MACGPIONUM 81 /* The gpio number is wrong */ +#define MACNOTSUP 82 /* The function is NOT supported */ +#define MACCSIBUFIDERR 83 /* CSI buffer index is NOT supported */ +#define MACSNDSTSIDERR 84 /* Sounding status ID is NOT supported */ +#define MACCCTLWRFAIL 85 /* control info wrrite fail */ +#define MACHWNOSUP 86 /* HW not support */ +#define MACUNDEFCH 87 /* Channel is undefined */ +#define MACHWERR 88 /* HW error */ +#define MACFWTESTFAIL 89 /* FW auto test fail */ +#define MACP2PSTFAIL 90 /* P2P state fail */ +#define MACFLASHFAIL 91 /* FW auto test fail */ +#define MACSETVALERR 92 /* Setting value error */ +#define MACIOERRPWR 93 /* IO not allow when power not on */ +#define MACIOERRSERL1 94 /* IO not allow when SER Lv1 */ +#define MACIOERRLPS 95 /* IO not allow when LPS */ +#define MACIOERRDMAC 96 /* IO not allow when dmac not en */ +#define MACIOERRCMAC0 97 /* IO not allow when cmac0 not en */ +#define MACIOERRCMAC1 98 /* IO not allow when cmac1 not en */ +#define MACIOERRBB0 99 /* IO not allow when bb0 not en */ +#define MACIOERRBB1 100 /* IO not allow when bb1 not en */ +#define MACIOERRRF 101 /* IO not allow when rf not en */ +#define MACIOERRIND 102 /* IO not allow when indirect access */ +#define MACIOERRRSVD 103 /* IO not allow if address is rsvd */ +#define MACC2HREGEMP 104 /* C2H reg empty */ +#define MACBADC2HREG 105 /* received unexpected c2hreg */ +#define MACFIOOFLD 106 /* IO offload fail */ +#define MACROLEALOCFL 107 /* C2H notify alloc role failed */ +#define MACROLEHWUPDFL 108 /* C2H notify addrcam upd failed*/ +#define MACSDIOTXMODE 109 /* SDIO Tx mode undefined*/ +#define MACSDIOOPNMODE 110 /* SDIO opn mode unknown*/ +#define MACFWSTATUSFAIL 111 /* fw status command fail */ +#define MACIOERRPLAT 112 /* IO not allow when platform not on */ +#define MACCPWMPWRSTATERR 113 /* CPWM power state mismatch */ +#define MACIOERRISH 114 /* IO not allow when io state hang */ +#define MACHWDMACERR 115 /* DMAC_ERR_ISR */ +#define MACHWCMAC0ERR 116 /* CMAC0_ERR_ISR */ +#define MACHWCMAC1ERR 116 /* CMAC1_ERR_ISR */ +#define MACDRVRM 117 /* driver is removed unexpectedly */ +#define MACMCCGPFL 118 /* Get MCC Group index fail*/ +#define MACFWSTATEERR 119 /* fw state error */ +#define MACFWLOGINTERR 120 /*fw log parsing error*/ +#define MACFWASSERT 123 /* FW Assertion error */ +#define MACFWEXCEP 124 /* FW Exception error */ +#define MACFWRXI300 125 /* FW RXI300 error */ +#define MACFWPCHANG 126 /* FW PC hang error */ +#define MACRXDMAHANG 127 /*USB RXDMA HANG */ +#define MACUSBRXHANG 128 /*USB RX HANG */ +#define MACCPWMINTFERR 129 /* CPWM interface error */ + +/*MAC DBG Status Indication*/ +#define MACSCH_NONEMPTY 1 /* MAC Scheduler non empty */ + +/* Debug Package Indication */ +/* STA Scheduler 0, indirect */ +#define SS_TX_LEN_BE BIT(0) +#define SS_TX_LEN_BK BIT(1) +#define SS_TX_LEN_VI BIT(2) +#define SS_TX_LEN_VO BIT(3) +#define SS_LINK_WMM0_BE BIT(4) +#define SS_LINK_WMM0_BK (SS_LINK_WMM0_BE << 1) +#define SS_LINK_WMM0_VI (SS_LINK_WMM0_BE << 2) +#define SS_LINK_WMM0_VO (SS_LINK_WMM0_BE << 3) +#define SS_LINK_WMM1_BE (SS_LINK_WMM0_BE << 4) +#define SS_LINK_WMM1_BK (SS_LINK_WMM0_BE << 5) +#define SS_LINK_WMM1_VI (SS_LINK_WMM0_BE << 6) +#define SS_LINK_WMM1_VO (SS_LINK_WMM0_BE << 7) +#define SS_LINK_WMM2_BE (SS_LINK_WMM0_BE << 8) +#define SS_LINK_WMM2_BK (SS_LINK_WMM0_BE << 9) +#define SS_LINK_WMM2_VI (SS_LINK_WMM0_BE << 10) +#define SS_LINK_WMM2_VO (SS_LINK_WMM0_BE << 11) +#define SS_LINK_WMM3_BE (SS_LINK_WMM0_BE << 12) +#define SS_LINK_WMM3_BK (SS_LINK_WMM0_BE << 13) +#define SS_LINK_WMM3_VI (SS_LINK_WMM0_BE << 14) +#define SS_LINK_WMM3_VO (SS_LINK_WMM0_BE << 15) +#define SS_LINK_UL (SS_LINK_WMM0_BE << 16) +#define SS_POLL_OWN_TX_LEN BIT(24) +#define SS_POLL_OWN_LINK BIT(25) +#define SS_POLL_STAT_TX_LEN BIT(26) +#define SS_POLL_STAT_LINK BIT(27) +/* STA Scheduler 1, direct */ +#define SS_TX_HW_LEN_UDN BIT(0) +#define SS_TX_SW_LEN_UDN BIT(1) +#define SS_TX_HW_LEN_OVF BIT(2) +#define SS_STAT_FWTX BIT(8) +#define SS_STAT_RPTA BIT(9) +#define SS_STAT_WDEA BIT(10) +#define SS_STAT_PLEA BIT(11) +#define SS_STAT_ULRU BIT(12) +#define SS_STAT_DLTX BIT(13) + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +#define PLTFM_MSG_ALWAYS(...) \ + _os_dbgdump("[MAC][ERR] " fmt, ##__VA_ARGS__) +#else +#define PLTFM_MSG_ALWAYS(...) \ + adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ALWAYS_, __VA_ARGS__) +#endif + +#if MAC_AX_DBG_MSG_EN + +#ifdef CONFIG_NEW_HALMAC_INTERFACE + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ALWAYS) + #define PLTFM_MSG_ALWAYS(...) \ + _os_dbgdump("[MAC][LOG] " fmt, ##__VA_ARGS__) + #else + #define PLTFM_MSG_ALWAYS(...) do {} while (0) + #endif + + /* Enable debug msg depends on HALMAC_MSG_LEVEL */ + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ERR) + #define PLTFM_MSG_ERR(...) \ + _os_dbgdump("[MAC][ERR] " fmt, ##__VA_ARGS__) + #else + #define PLTFM_MSG_ERR(...) do {} while (0) + #endif + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_WARNING) + #define PLTFM_MSG_WARN(...) \ + _os_dbgdump("[MAC][WARN] " fmt, ##__VA_ARGS__) + #else + #define PLTFM_MSG_WARN(...) do {} while (0) + #endif + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_TRACE) + #define PLTFM_MSG_TRACE(...) \ + _os_dbgdump("[MAC][TRACE] " fmt, ##__VA_ARGS__) + #else + #define PLTFM_MSG_TRACE(...) do {} while (0) + #endif + +#else + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ALWAYS) + #define PLTFM_MSG_ALWAYS(...) \ + adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ALWAYS_, __VA_ARGS__) + #else + #define PLTFM_MSG_ALWAYS(...) do {} while (0) + #endif + + /* Enable debug msg depends on HALMAC_MSG_LEVEL */ + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ERR) + #define PLTFM_MSG_ERR(...) \ + adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ERR_, __VA_ARGS__) + #else + #define PLTFM_MSG_ERR(...) do {} while (0) + #endif + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_WARNING) + #define PLTFM_MSG_WARN(...) \ + adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_WARNING_, __VA_ARGS__) + #else + #define PLTFM_MSG_WARN(...) do {} while (0) + #endif + + #if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_TRACE) + #define PLTFM_MSG_TRACE(...) \ + adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_DEBUG_, __VA_ARGS__) + #else + #define PLTFM_MSG_TRACE(...) do {} while (0) + #endif +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +#else + +/* Disable debug msg */ +#define PLTFM_MSG_ALWAYS(...) do {} while (0) +#define PLTFM_MSG_ERR(...) do {} while (0) +#define PLTFM_MSG_WARN(...) do {} while (0) +#define PLTFM_MSG_TRACE(...) do {} while (0) + +#endif + +#endif diff --git a/phl/hal_g6/mac/feature_cfg.h b/phl/hal_g6/mac/feature_cfg.h new file mode 100644 index 0000000..89c2c4c --- /dev/null +++ b/phl/hal_g6/mac/feature_cfg.h @@ -0,0 +1,87 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FEATURE_CFG_H_ +#define _MAC_AX_FEATURE_CFG_H_ + +#ifndef __cplusplus /* for win/linux driver */ + +/* [Note] Modify MakeFile to reduce code size */ + +/* Debug package for debugging */ +#define MAC_AX_FEATURE_DBGPKG 1 + +/* Hadrware verification module */ +#define MAC_AX_FEATURE_HV 0 + +/* FW offload reg read/write */ +#define MAC_AX_FW_REG_OFLD 0 + +/* Temp code for FPGA verification*/ +#define MAC_AX_FPGA_TEST 0 + +/* Temp code for lack of BTC driver*/ +#define MAC_AX_ASIC_TEMP 1 + +/* temp for h2c alloc move to phl layer*/ +#define MAC_AX_PHL_H2C 1 + +/* Debug command */ +#define MAC_AX_FEATURE_DBGCMD 1 + +/* Debug Log Decode */ +#define MAC_AX_FEATURE_DBGDEC 1 + +#ifdef CONFIG_BTCOEX +#define MAC_AX_COEX_INIT_EN 0 +#else +#define MAC_AX_COEX_INIT_EN 1 +#endif + +#else /* for WD1 test program */ + +/* [Note] Modify MakeFile to reduce code size */ + +/* Debug package for debugging */ +#define MAC_AX_FEATURE_DBGPKG 1 + +/* Debug package for debugging */ +#define MAC_AX_FW_REG_OFLD 0 + +/* Hadrware verification module */ +#define MAC_AX_FEATURE_HV 1 + +#define MAC_AX_FPGA_TEST 1 + +#define MAC_AX_ASIC_TEMP 1 + +/* temp for h2c alloc move to phl layer */ +#define MAC_AX_PHL_H2C 0 + +/* [HV] for SIC command generagor */ +#define MAC_AX_HV_SIC_GEN 0 + +#define MAC_AX_COEX_INIT_EN 1 + +/* Debug command */ +#define MAC_AX_FEATURE_DBGCMD 1 + +/* Debug Log Decode */ +#define MAC_AX_FEATURE_DBGDEC 1 +#endif // #else /* for WD1 test program */ + +#endif + diff --git a/phl/hal_g6/mac/feature_cfg_drv.h b/phl/hal_g6/mac/feature_cfg_drv.h new file mode 100644 index 0000000..63e97d3 --- /dev/null +++ b/phl/hal_g6/mac/feature_cfg_drv.h @@ -0,0 +1,53 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FEATURE_CFG_H_ +#define _MAC_AX_FEATURE_CFG_H_ + +/* [Note] Modify MakeFile to reduce code size */ + +/* Debug package for debugging */ +#define MAC_AX_FEATURE_DBGPKG 1 + +/* Hadrware verification module */ +#define MAC_AX_FEATURE_HV 0 + +/* Debug package for debugging */ +#define MAC_AX_FW_REG_OFLD 0 + +/* Temp code for FPGA verification*/ +#define MAC_AX_FPGA_TEST 0 + +/* Temp code for lack of BTC driver*/ +#define MAC_AX_ASIC_TEMP 1 + +/* temp for h2c alloc move to phl layer*/ +#define MAC_AX_PHL_H2C 1 + +/* Debug command */ +#define MAC_AX_FEATURE_DBGCMD 1 + +/* Debug Log Decode */ +#define MAC_AX_FEATURE_DBGDEC 1 + +#ifdef CONFIG_BTCOEX +#define MAC_AX_COEX_INIT_EN 0 +#else +#define MAC_AX_COEX_INIT_EN 1 +#endif + +#endif + diff --git a/phl/hal_g6/mac/fw_ax/inc_hdr/fwcmd_intf.h b/phl/hal_g6/mac/fw_ax/inc_hdr/fwcmd_intf.h new file mode 100644 index 0000000..9f1c486 --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/inc_hdr/fwcmd_intf.h @@ -0,0 +1,6128 @@ +#ifndef _MAC_FWCMD_INTF_H_ +#define _MAC_FWCMD_INTF_H_ + +#define FWCMD_VER 0x0 + +// ID definition// + +// +//H2CREG +// +#define FWCMD_H2CREG_FUNC_H2CREG_LB 0x0 +#define FWCMD_H2CREG_FUNC_CNSL_CMD 0x1 +#define FWCMD_H2CREG_FUNC_FWERR 0x2 +#define FWCMD_H2CREG_FUNC_HIDDEN_GET 0x3 +#define FWCMD_H2CREG_FUNC_GETPKT_INFORM 0x4 +#define FWCMD_H2CREG_FUNC_SCH_TX_EN 0x5 +#define FWCMD_H2CREG_FUNC_WOW_TRX_STOP 0x6 +#define FWCMD_H2CREG_FUNC_AOAC_RPT_1 0x7 +#define FWCMD_H2CREG_FUNC_AOAC_RPT_2 0x8 + +// +//C2HREG +// +#define FWCMD_C2HREG_FUNC_C2HREG_LB 0x0 +#define FWCMD_C2HREG_FUNC_ERR_RPT 0x1 +#define FWCMD_C2HREG_FUNC_ERR_MSG 0x2 +#define FWCMD_C2HREG_FUNC_EFUSE_HIDDEN 0x3 +#define FWCMD_C2HREG_FUNC_TX_PAUSE_RPT 0x4 +#define FWCMD_C2HREG_FUNC_AOAC_RPT_1 0x5 +#define FWCMD_C2HREG_FUNC_AOAC_RPT_2 0x6 +#define FWCMD_C2HREG_FUNC_AOAC_RPT_3 0x7 +#define FWCMD_C2HREG_FUNC_WOW_TRX_STOP 0x8 +#define FWCMD_C2HREG_FUNC_IO_OFLD_RESULT 0x9 + +// +//H2CPKT - CAT(TEST) +// +#define FWCMD_H2C_CAT_TEST 0x0 +#define FWCMD_H2C_CAT_MAC 0x1 +#define FWCMD_H2C_CAT_OUTSRC 0x2 +#define FWCMD_H2C_CL_CMD_PATH 0x0 +#define FWCMD_H2C_CL_SND_TEST 0x1 +#define FWCMD_H2C_CL_PLAT_AUTO_TEST 0x2 +#define FWCMD_H2C_CL_MAC_TEST 0x3 +#define FWCMD_H2C_CL_FW_AUTO_TEST 0x4 +#define FWCMD_H2C_CL_FW_STATUS_TEST 0x5 + +// CLASS 0 - CMD_PATH +#define FWCMD_H2C_FUNC_H2C_LB 0x0 + +// CLASS 1 - SND_Test + +// CLASS 2 - PLATFORM_AUTO_TEST +#define FWCMD_H2C_FUNC_PLAT_SPIC_TEST 0x0 +#define FWCMD_H2C_FUNC_PLAT_CPU_PLATFORM 0x1 +#define FWCMD_H2C_FUNC_PLAT_EFUSE_CTRL 0x2 +#define FWCMD_H2C_FUNC_PLAT_IDDMA 0x3 +#define FWCMD_H2C_FUNC_PLAT_AXIDMA 0x4 +#define FWCMD_H2C_FUNC_PLAT_IPSEC 0x5 +#define FWCMD_H2C_FUNC_PLAT_UART 0x6 +#define FWCMD_H2C_FUNC_PLAT_HIOE 0x7 +#define FWCMD_H2C_FUNC_PLAT_WATCHDOG 0x8 +#define FWCMD_H2C_FUNC_PLAT_SECURITY 0x9 +#define FWCMD_H2C_FUNC_PLAT_FL_WRITE 0xa +#define FWCMD_H2C_FUNC_PLAT_FL_ERASE 0xb +#define FWCMD_H2C_FUNC_PL_FLASH_READ 0xc +#define FWCMD_H2C_FUNC_PLAT_MODULE_MAX 0x10 +#define FWCMD_H2C_FUNC_PLAT_INVALID 0x11 + +// CLASS 3 - MAC_TEST +#define FWCMD_H2C_FUNC_LONG_RUN 0x0 + +// CLASS 4 - FW_AUTO_TEST +#define FWCMD_H2C_FUNC_LPS_TEST 0x0 +#define FWCMD_H2C_FUNC_LPS_ONOFF_TEST 0x1 + +// CLASS 5 - FW_STATUS_TEST +#define FWCMD_H2C_FUNC_FW_STATUS 0x0 + +// +//H2CPKT - CAT(MAC) +// +#define FWCMD_H2C_CAT_TEST 0x0 +#define FWCMD_H2C_CAT_MAC 0x1 +#define FWCMD_H2C_CAT_OUTSRC 0x2 +#define FWCMD_H2C_CL_FW_INFO 0x0 +#define FWCMD_H2C_CL_WOW 0x1 +#define FWCMD_H2C_CL_PS 0x2 +#define FWCMD_H2C_CL_FWDL 0x3 +#define FWCMD_H2C_CL_TWT 0x4 +#define FWCMD_H2C_CL_FR_EXCHG 0x5 +#define FWCMD_H2C_CL_ADDR_CAM_UPDATE 0x6 +#define FWCMD_H2C_CL_BSSID_CAM_UPDATE 0x7 +#define FWCMD_H2C_CL_MEDIA_RPT 0x8 +#define FWCMD_H2C_CL_FW_OFLD 0x9 +#define FWCMD_H2C_CL_SEC_CAM 0xA +#define FWCMD_H2C_CL_SOUND 0xB +#define FWCMD_H2C_CL_BA_CAM 0xC +#define FWCMD_H2C_CL_IE_CAM 0xD +#define FWCMD_H2C_CL_MCC 0xE +#define FWCMD_H2C_CL_SCSI 0xF +#define FWCMD_H2C_CL_FLASH 0x10 +#define FWCMD_H2C_CL_FCS 0x11 +#define FWCMD_H2C_CL_MISC 0x12 +#define FWCMD_H2C_CL_MPORT 0x13 + +// CLASS 0 - FW_INFO +#define FWCMD_H2C_FUNC_LOG_CFG 0x0 +#define FWCMD_H2C_FUNC_GENERAL_PKT 0x1 +#define FWCMD_H2C_FUNC_C2H_RPT_CFG 0x2 +#define FWCMD_H2C_FUNC_WLAN_DUMP_CMD 0x2 +#define FWCMD_H2C_FUNC_FW_DBGREG_CFG 0x3 + +// CLASS 1 - WOW +#define FWCMD_H2C_FUNC_KEEP_ALIVE 0x0 +#define FWCMD_H2C_FUNC_DISCONNECT_DETECT 0x1 +#define FWCMD_H2C_FUNC_WOW_GLOBAL 0x2 +#define FWCMD_H2C_FUNC_GTK_OFLD 0x3 +#define FWCMD_H2C_FUNC_ARP_OFLD 0x4 +#define FWCMD_H2C_FUNC_NDP_OFLD 0x5 +#define FWCMD_H2C_FUNC_REALWOW 0x6 +#define FWCMD_H2C_FUNC_NLO 0x7 +#define FWCMD_H2C_FUNC_WAKEUP_CTRL 0x8 +#define FWCMD_H2C_FUNC_NEGATIVE_PATTERN 0x9 +#define FWCMD_H2C_FUNC_DEV2HST_GPIO 0xA +#define FWCMD_H2C_FUNC_UPHY_CTRL 0xB +#define FWCMD_H2C_FUNC_WOW_CAM_UPD 0xC +#define FWCMD_H2C_FUNC_AOAC_REPORT_REQ 0xD +#define FWCMD_H2C_FUNC_WOW_STOP_FW_TRX 0xE + +// CLASS 2 - PS +#define FWCMD_H2C_FUNC_LPS_PARM 0x0 +#define FWCMD_H2C_FUNC_P2P_ACT 0x1 +#define FWCMD_H2C_FUNC_P2P_MACID_CTRL 0x2 +#define FWCMD_H2C_FUNC_IPS_CFG 0x3 +#define FWCMD_H2C_FUNC_PS_ADVANCE_PARM 0x4 + +// CLASS 3 - FWDL +#define FWCMD_H2C_FUNC_FWHDR_DL 0x0 +#define FWCMD_H2C_FUNC_FWHDR_REDL 0x1 + +// CLASS 4 - TWT +#define FWCMD_H2C_FUNC_TWT_ANNOUNCE_UPD 0x00 +#define FWCMD_H2C_FUNC_TWTINFO_UPD 0x1 +#define FWCMD_H2C_FUNC_TWT_STANSP_UPD 0x2 + +// CLASS 5 - Frame Exchange +#define FWCMD_H2C_FUNC_TBLUD 0x0 +#define FWCMD_H2C_FUNC_DCTLINFO_UD 0x1 +#define FWCMD_H2C_FUNC_CCTLINFO_UD 0x2 +#define FWCMD_H2C_FUNC_F2P_TEST 0x3 +#define FWCMD_H2C_FUNC_SHCUT_UPDATE 0x4 +#define FWCMD_H2C_FUNC_BCN_UPD 0x5 +#define FWCMD_H2C_FUNC_SS_ULSTA_UPD 0x6 +#define FWCMD_H2C_FUNC_F2PDBG_SET 0x7 +#define FWCMD_H2C_FUNC_WLANINFO_GET 0x8 +#define FWCMD_H2C_FUNC_FW_STS_PARA 0x9 + +// CLASS 6 - Address CAM +#define FWCMD_H2C_FUNC_ADDRCAM_INFO 0x0 + +// CLASS 8 - Media Status Report +#define FWCMD_H2C_FUNC_JOININFO 0x0 +#define FWCMD_H2C_FUNC_DL_GRP_UPD 0x1 +#define FWCMD_H2C_FUNC_UL_GRP_UPD 0x2 +#define FWCMD_H2C_FUNC_MU_STA_UPD 0x3 +#define FWCMD_H2C_FUNC_FWROLE_MAINTAIN 0x4 +#define FWCMD_H2C_FUNC_NOTIFY_DBCC 0x5 + +// CLASS 9 - FW_OFLD +#define FWCMD_H2C_FUNC_DUMP_EFUSE 0x0 +#define FWCMD_H2C_FUNC_PACKET_OFLD 0x1 +#define FWCMD_H2C_FUNC_READ_OFLD 0x2 +#define FWCMD_H2C_FUNC_WRITE_OFLD 0x3 +#define FWCMD_H2C_FUNC_CONF_OFLD 0x4 +#define FWCMD_H2C_FUNC_SYS_INIT 0x5 +#define FWCMD_H2C_FUNC_TRX_INIT 0x6 +#define FWCMD_H2C_FUNC_INTF_INIT 0x7 +#define FWCMD_H2C_FUNC_MACID_PAUSE 0x8 +#define FWCMD_H2C_FUNC_RX_FWD 0x9 +#define FWCMD_H2C_FUNC_EN_MAC_HDR_CONV 0xB +#define FWCMD_H2C_FUNC_SET_HWSEQ_REG 0xA +#define FWCMD_H2C_FUNC_HWAMSDU_REG 0xC +#define FWCMD_H2C_FUNC_AMSDU_CUT_REG 0xD +#define FWCMD_H2C_FUNC_TCPIP_CHKSUM_OFFLOAD_REG 0xE +#define FWCMD_H2C_FUNC_USR_EDCA 0xF +#define FWCMD_H2C_FUNC_TSF32_TOGL 0x10 +#define FWCMD_H2C_FUNC_CMD_OFLD_REG 0x11 +#define FWCMD_H2C_FUNC_USR_TX_RPT 0x12 +#define FWCMD_H2C_FUNC_CMD_OFLD_PKT 0x13 +#define FWCMD_H2C_FUNC_OFLD_CFG 0x14 +#define FWCMD_H2C_FUNC_H2C_AGG 0x15 +#define FWCMD_H2C_FUNC_ADD_SCANOFLD_CH 0x16 +#define FWCMD_H2C_FUNC_SCANOFLD 0x17 +#define FWCMD_H2C_FUNC_TX_DUTY 0x18 +#define FWCMD_H2C_FUNC_DISABLE_RF 0x19 +#define FWCMD_H2C_FUNC_CH_SWITCH 0x1A +#define FWCMD_H2C_FUNC_PKT_DROP 0x1B + +// CLASS 10 - SECCAM +#define FWCMD_H2C_FUNC_SEC_CAM_INIT 0x0 +#define FWCMD_H2C_FUNC_SECCAM_INFO 0x1 + +// CLASS 11 - Sound +#define FWCMD_H2C_FUNC_SET_SND_PARA 0x0 +#define FWCMD_H2C_FUNC_GET_CSI_BUF 0x1 +#define FWCMD_H2C_FUNC_SET_CSI_BUF 0x2 +#define FWCMD_H2C_FUNC_GET_SND_STS 0x3 +#define FWCMD_H2C_FUNC_SET_SND_STS 0x4 +#define FWCMD_H2C_FUNC_INIT_SND_MER 0x5 +#define FWCMD_H2C_FUNC_INIT_SND_MEE 0x6 +#define FWCMD_H2C_FUNC_CSI_FIX_RATE 0x7 +#define FWCMD_H2C_FUNC_CSI_RRSC 0x8 +#define FWCMD_H2C_FUNC_SET_MU_TABLE 0x9 +#define FWCMD_H2C_FUNC_SET_CSI_PARA_REG 0xA +#define FWCMD_H2C_FUNC_HW_SND_PR 0xB +#define FWCMD_H2C_FUNC_BYPASS_SND_STS 0xC +#define FWCMD_H2C_FUNC_SET_SND_PARA_V1 0xD + +// CLASS 12 - BACAM +#define FWCMD_H2C_FUNC_BA_CAM 0x0 + +// CLASS 13 - IECAM +#define FWCMD_H2C_FUNC_IE_CAM 0x0 + +// CLASS 14 - MCC +#define FWCMD_H2C_FUNC_ADD_MCC 0x0 +#define FWCMD_H2C_FUNC_START_MCC 0x1 +#define FWCMD_H2C_FUNC_STOP_MCC 0x2 +#define FWCMD_H2C_FUNC_DEL_MCC_GROUP 0x3 +#define FWCMD_H2C_FUNC_RESET_MCC_GROUP 0x4 +#define FWCMD_H2C_FUNC_MCC_REQ_TSF 0x5 +#define FWCMD_H2C_FUNC_MCC_MACID_BITMAP 0x6 +#define FWCMD_H2C_FUNC_MCC_SYNC 0x7 +#define FWCMD_H2C_FUNC_MCC_SET_DURATION 0x8 + +// CLASS 15 - SCSI +#define FWCMD_H2C_FUNC_SCSI_TX 0x0 +#define FWCMD_H2C_FUNC_USB_SWITCH 0x1 + +// CLASS 16 - FLASH +#define FWCMD_H2C_FUNC_PLAT_FLASH_WRITE 0x0 +#define FWCMD_H2C_FUNC_PLAT_FLASH_ERASE 0x1 +#define FWCMD_H2C_FUNC_PLAT_FLASH_READ 0x2 + +// CLASS 17 - FCS +#define FWCMD_H2C_FUNC_FCS 0x0 + +// CLASS 18 - MISC +#define FWCMD_H2C_FUNC_CFG_WPS 0x0 + +// CLASS 19 - MPORT +#define FWCMD_H2C_FUNC_PORT_INIT 0x0 +#define FWCMD_H2C_FUNC_PORT_CFG 0x1 + +// +//H2CPKT - CAT(Table) +// + +// +//H2CPKT - CAT(OutSrc,Phydm) +// +#define FWCMD_H2C_CAT_TEST 0x0 +#define FWCMD_H2C_CAT_MAC 0x1 +#define FWCMD_H2C_CAT_OUTSRC 0x2 +#define FWCMD_H2C_CL_RUA 0x0 +#define FWCMD_H2C_CL_RA 0x1 + +// CLASS 0 (RUA) +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 1 (RA) +#define FWCMD_H2C_FUNC_MACID_CFG 0x0 +#define FWCMD_H2C_FUNC_RSSI_RA_CONFIG 0x1 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 2 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 3 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 4 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 5 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 6 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 7 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// +//H2CPKT - CAT(OutSrc, RF) +// +#define FWCMD_H2C_CAT_TEST 0x0 +#define FWCMD_H2C_CAT_MAC 0x1 +#define FWCMD_H2C_CAT_OUTSRC 0x2 + +// CLASS 8 +#define FWCMD_H2C_FUNC_RADIO_INIT_0 0x0 +#define FWCMD_H2C_FUNC_RADIO_INIT_1 0x1 +#define FWCMD_H2C_FUNC_RADIO_INIT_2 0x2 +#define FWCMD_H2C_FUNC_RADIO_INIT_3 0x3 +#define FWCMD_H2C_FUNC_RADIO_INIT_4 0x4 +#define FWCMD_H2C_FUNC_RADIO_INIT_5 0x5 +#define FWCMD_H2C_FUNC_RADIO_INIT_6 0x6 +#define FWCMD_H2C_FUNC_RADIO_INIT_7 0x7 +#define FWCMD_H2C_FUNC_RADIO_INIT_8 0x8 +#define FWCMD_H2C_FUNC_RADIO_INIT_9 0x9 + +// CLASS 9 +#define FWCMD_H2C_FUNC_DACK_BACKUP 0x0 +#define FWCMD_H2C_FUNC_DACK_RELOAD 0x1 + +// CLASS 10 +#define FWCMD_H2C_FUNC_FCS_BACKUP_RFK 0x0 +#define FWCMD_H2C_FUNC_FCS_RELOAD_RFK 0x1 +#define FWCMD_H2C_FUNC_GET_MCCCH 0x2 +#define FWCMD_H2C_FUNC_FWIQK_TRIGGER 0x4 + +// CLASS 11 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 12 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 13 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 14 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// CLASS 15 +#define FWCMD_H2C_FUNC_EXAMPLE 0x0 + +// +//H2CPKT - CAT(OutSrc, BTC) +// +#define FWCMD_H2C_CAT_TEST 0x0 +#define FWCMD_H2C_CAT_MAC 0x1 +#define FWCMD_H2C_CAT_OUTSRC 0x2 + +// CLASS 16 +#define FWCMD_H2C_FUNC_TDMA 0x0 + +// +//C2HPKT - CAT(TEST) +// +#define FWCMD_C2H_CAT_TEST 0x0 +#define FWCMD_C2H_CAT_MAC 0x1 +#define FWCMD_C2H_CAT_OUTSRC 0x2 +#define FWCMD_C2H_CL_CMD_PATH 0x0 +#define FWCMD_C2H_CL_PLAT_AUTO 0x2 +#define FWCMD_C2H_CL_FW_AUTO 0x3 +#define FWCMD_C2H_CL_FW_STATUS 0x4 + +// CLASS 0 - CMD_PATH +#define FWCMD_C2H_FUNC_C2H_LB 0x00 +#define FWCMD_C2H_FUNC_TEST_PHY_RPT 0x01 + +// CLASS 2 - PLATFORM_AUTO_TEST +#define FWCMD_C2H_FUNC_SPIC 0x00 +#define FWCMD_C2H_FUNC_SPIC2 0x01 + +// CLASS 3 - FW_AUTO_TEST +#define FWCMD_C2H_FUNC_LPS_TEST 0x00 +#define FWCMD_C2H_FUNC_LPS_ONOFF_TEST 0x1 + +// CLASS 4 - FW_STATUS +#define FWCMD_C2H_FUNC_FW_STATUS 0x00 + +// +//C2HPKT - CAT(MAC) +// +#define FWCMD_C2H_CAT_TEST 0x0 +#define FWCMD_C2H_CAT_MAC 0x1 +#define FWCMD_C2H_CAT_OUTSRC 0x2 +#define FWCMD_C2H_CL_FW_INFO 0x0 +#define FWCMD_C2H_CL_FW_OFLD 0x1 +#define FWCMD_C2H_CL_TWT 0x2 +#define FWCMD_C2H_CL_WOW 0x3 +#define FWCMD_C2H_CL_MCC 0x4 +#define FWCMD_C2H_CL_FW_DBG 0x5 +#define FWCMD_C2H_CL_FLASH 0x6 +#define FWCMD_C2H_CL_SCSI 0x7 +#define FWCMD_C2H_CL_FCS 0x8 +#define FWCMD_C2H_CL_MISC 0x9 +#define FWCMD_C2H_CL_MPORT 0xA +#define FWCMD_C2H_CL_OFDMA_INFO 0xB + +// CLASS 0 - FW_INFO +#define FWCMD_C2H_FUNC_REC_ACK 0x00 +#define FWCMD_C2H_FUNC_DONE_ACK 0x01 +#define FWCMD_C2H_FUNC_C2H_LOG 0x02 +#define FWCMD_C2H_FUNC_BCN_CNT 0x03 +#define FWCMD_C2H_FUNC_BCN_CSAZERO 0x04 + +// CLASS 1 - FW_OFLD +#define FWCMD_C2H_FUNC_EFUSE_DUMP 0x00 +#define FWCMD_C2H_FUNC_READ_RSP 0x01 +#define FWCMD_C2H_FUNC_PKT_OFLD_RSP 0x02 +#define FWCMD_C2H_FUNC_BEACON_RESEND 0x3 +#define FWCMD_C2H_FUNC_MACID_PAUSE 0x4 +#define FWCMD_C2H_FUNC_FW_GETPKT_RPT 0x5 +#define FWCMD_C2H_FUNC_TSF32_TOGL_RPT 0x6 +#define FWCMD_C2H_FUNC_USR_TX_RPT_INFO 0x7 +#define FWCMD_C2H_FUNC_CMD_OFLD_RSP 0x8 +#define FWCMD_C2H_FUNC_SCANOFLD_RSP 0x9 +#define FWCMD_C2H_FUNC_TX_DUTY_RPT 0xA +#define FWCMD_C2H_FUNC_CH_SWITCH_RPT 0xB + +// CLASS 2 - TWT +#define FWCMD_C2H_FUNC_WAIT_ANNOUNCE 0x00 + +// CLASS 3 - WOW +#define FWCMD_C2H_FUNC_AOAC_REPORT 0x00 +#define FWCMD_C2H_FUNC_READ_WOW_CAM 0x01 + +// CLASS 4 - MCC +#define FWCMD_C2H_FUNC_MCC_RCV_ACK 0x00 +#define FWCMD_C2H_FUNC_MCC_REQ_ACK 0x01 +#define FWCMD_C2H_FUNC_MCC_TSF_RPT 0x02 +#define FWCMD_C2H_FUNC_MCC_STATUS_RPT 0x03 + +// CLASS 5 - FW_DBG +#define FWCMD_C2H_FUNC_RX_DBG 0x00 + +// CLASS 6 - FLASH +#define FWCMD_C2H_FUNC_PLAT_FLASH_WRITE 0x0 +#define FWCMD_C2H_FUNC_PLAT_FLASH_ERASE 0x1 +#define FWCMD_C2H_FUNC_PLAT_FLASH_READ 0x2 + +// CLASS 7 - SCSI +#define FWCMD_C2H_FUNC_SCSI_RX 0x00 + +// CLASS 8 - FCS +#define FWCMD_C2H_FUNC_FCS_RPT 0x00 + +// CLASS 9 - MISC +#define FWCMD_C2H_FUNC_WPS_RPT 0x0 +#define FWCMD_C2H_FUNC_CCXRPT 0x1 + +// CLASS 10 - MPORT +#define FWCMD_C2H_FUNC_PORT_INIT_STAT 0x0 +#define FWCMD_C2H_FUNC_PORT_CFG_STAT 0x1 + +// CLASS 11 - OFDMA_STS +#define FWCMD_C2H_FUNC_OFDMA_STS 0x00 + +// +//C2HPKT - CAT(OutSrc, Phydm) +// +#define FWCMD_C2H_CAT_TEST 0x0 +#define FWCMD_C2H_CAT_MAC 0x1 +#define FWCMD_C2H_CAT_OUTSRC 0x2 +#define FWCMD_C2H_CL_RUA 0x0 +#define FWCMD_C2H_CL_RA 0x1 +#define FWCMD_C2H_CL_HALBB 0x2 +#define FWCMD_C2H_CL_DBG 0x7 + +// CLASS 0 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 1 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 2 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 3 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 4 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 5 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 6 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 7 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// +//C2HPKT - CAT(OutSrc, RF) +// +#define FWCMD_C2H_CAT_TEST 0x0 +#define FWCMD_C2H_CAT_MAC 0x1 +#define FWCMD_C2H_CAT_OUTSRC 0x2 + +// CLASS 9 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 10 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 11 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 12 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 13 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 14 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// CLASS 15 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// +//C2HPKT - CAT(OutSrc, BTC) +// +#define FWCMD_C2H_CAT_TEST 0x0 +#define FWCMD_C2H_CAT_MAC 0x1 +#define FWCMD_C2H_CAT_OUTSRC 0x2 + +// CLASS 16 +#define FWCMD_C2H_FUNC_EXAMPLE 0x0 + +// Bit definition// + +// +//H2CREG +// +#define FWCMD_H2CREG_H2CREG_HDR_FUNC_SH 0 +#define FWCMD_H2CREG_H2CREG_HDR_FUNC_MSK 0x7f +#define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7) +#define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_H2CREG_HDR_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_H2CREG_HDR_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_H2CREG_DWORD0_SH 0 +#define FWCMD_H2CREG_H2CREG_DWORD0_MSK 0xffffffff +#define FWCMD_H2CREG_H2CREG_DWORD1_SH 0 +#define FWCMD_H2CREG_H2CREG_DWORD1_MSK 0xffffffff +#define FWCMD_H2CREG_H2CREG_DWORD2_SH 0 +#define FWCMD_H2CREG_H2CREG_DWORD2_MSK 0xffffffff +#define FWCMD_H2CREG_H2CREG_DWORD3_SH 0 +#define FWCMD_H2CREG_H2CREG_DWORD3_MSK 0xffffffff +#define FWCMD_H2CREG_H2CREG_LB_FUNC_SH 0 +#define FWCMD_H2CREG_H2CREG_LB_FUNC_MSK 0x7f +#define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7) +#define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_H2CREG_LB_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_H2CREG_LB_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_SH 16 +#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_MSK 0xffff +#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD1_SH 0 +#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD1_MSK 0xffffffff +#define FWCMD_H2CREG_CNSL_CMD_FUNC_SH 0 +#define FWCMD_H2CREG_CNSL_CMD_FUNC_MSK 0x7f +#define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7) +#define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_CNSL_CMD_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_CNSL_CMD_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_CNSL_CMD_CMD_ID_SH 16 +#define FWCMD_H2CREG_CNSL_CMD_CMD_ID_MSK 0xff +#define FWCMD_H2CREG_CNSL_CMD_ARG_NUM_SH 24 +#define FWCMD_H2CREG_CNSL_CMD_ARG_NUM_MSK 0xf +#define FWCMD_H2CREG_CNSL_CMD_ARG_UNIT_SH 28 +#define FWCMD_H2CREG_CNSL_CMD_ARG_UNIT_MSK 0x3 +#define FWCMD_H2CREG_FWERR_FUNC_SH 0 +#define FWCMD_H2CREG_FWERR_FUNC_MSK 0x7f +#define FWCMD_H2CREG_FWERR_ACK BIT(7) +#define FWCMD_H2CREG_FWERR_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_FWERR_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_FWERR_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_FWERR_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_FWERR_OP_SH 16 +#define FWCMD_H2CREG_FWERR_OP_MSK 0xf +#define FWCMD_H2CREG_FWERR_IDX_SH 0 +#define FWCMD_H2CREG_FWERR_IDX_MSK 0xffffffff +#define FWCMD_H2CREG_HIDDEN_GET_FUNC_SH 0 +#define FWCMD_H2CREG_HIDDEN_GET_FUNC_MSK 0x7f +#define FWCMD_H2CREG_HIDDEN_GET_ACK BIT(7) +#define FWCMD_H2CREG_HIDDEN_GET_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_HIDDEN_GET_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_HIDDEN_GET_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_HIDDEN_GET_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_GETPKT_INFORM_FUNC_SH 0 +#define FWCMD_H2CREG_GETPKT_INFORM_FUNC_MSK 0x7f +#define FWCMD_H2CREG_GETPKT_INFORM_ACK BIT(7) +#define FWCMD_H2CREG_GETPKT_INFORM_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_GETPKT_INFORM_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_GETPKT_INFORM_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_GETPKT_INFORM_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_GETPKT_INFORM_MACID_SH 16 +#define FWCMD_H2CREG_GETPKT_INFORM_MACID_MSK 0xff +#define FWCMD_H2CREG_GETPKT_INFORM_PKTTYPE_SH 24 +#define FWCMD_H2CREG_GETPKT_INFORM_PKTTYPE_MSK 0xff +#define FWCMD_H2CREG_SCH_TX_EN_FUNC_SH 0 +#define FWCMD_H2CREG_SCH_TX_EN_FUNC_MSK 0x7f +#define FWCMD_H2CREG_SCH_TX_EN_ACK BIT(7) +#define FWCMD_H2CREG_SCH_TX_EN_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_SCH_TX_EN_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_SCH_TX_EN_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_SCH_TX_EN_SEQ_NUM_MSK 0xf +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BE0 BIT(16) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BK0 BIT(17) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VI0 BIT(18) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VO0 BIT(19) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BE1 BIT(20) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BK1 BIT(21) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VI1 BIT(22) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VO1 BIT(23) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG0 BIT(24) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG1 BIT(25) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG2 BIT(26) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_HI BIT(27) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BCN BIT(28) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_UL BIT(29) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_TWT0 BIT(30) +#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_TWT1 BIT(31) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_BE0 BIT(0) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_BK0 BIT(1) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_VI0 BIT(2) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_VO0 BIT(3) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_BE1 BIT(4) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_BK1 BIT(5) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_VI1 BIT(6) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_VO1 BIT(7) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG0 BIT(8) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG1 BIT(9) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG2 BIT(10) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_HI BIT(11) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_BCN BIT(12) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_UL BIT(13) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_TWT0 BIT(14) +#define FWCMD_H2CREG_SCH_TX_EN_MASK_TWT1 BIT(15) +#define FWCMD_H2CREG_SCH_TX_EN_BAND BIT(16) +#define FWCMD_H2CREG_WOW_TRX_STOP_FUNC_SH 0 +#define FWCMD_H2CREG_WOW_TRX_STOP_FUNC_MSK 0x7f +#define FWCMD_H2CREG_WOW_TRX_STOP_ACK BIT(7) +#define FWCMD_H2CREG_WOW_TRX_STOP_TOTAL_LEN_SH 8 +#define FWCMD_H2CREG_WOW_TRX_STOP_TOTAL_LEN_MSK 0xf +#define FWCMD_H2CREG_WOW_TRX_STOP_SEQ_NUM_SH 12 +#define FWCMD_H2CREG_WOW_TRX_STOP_SEQ_NUM_MSK 0xf + +// +//C2HREG +// +#define FWCMD_C2HREG_C2HREG_HDR_FUNC_SH 0 +#define FWCMD_C2HREG_C2HREG_HDR_FUNC_MSK 0x7f +#define FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_C2HREG_HDR_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_C2HREG_HDR_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_C2HREG_DWORD0_SH 0 +#define FWCMD_C2HREG_C2HREG_DWORD0_MSK 0xffffffff +#define FWCMD_C2HREG_C2HREG_DWORD1_SH 0 +#define FWCMD_C2HREG_C2HREG_DWORD1_MSK 0xffffffff +#define FWCMD_C2HREG_C2HREG_DWORD2_SH 0 +#define FWCMD_C2HREG_C2HREG_DWORD2_MSK 0xffffffff +#define FWCMD_C2HREG_C2HREG_DWORD3_SH 0 +#define FWCMD_C2HREG_C2HREG_DWORD3_MSK 0xffffffff +#define FWCMD_C2HREG_C2HREG_LB_FUNC_SH 0 +#define FWCMD_C2HREG_C2HREG_LB_FUNC_MSK 0x7f +#define FWCMD_C2HREG_C2HREG_LB_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_C2HREG_LB_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_C2HREG_LB_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_C2HREG_LB_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD0_SH 16 +#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD0_MSK 0xffff +#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD1_SH 0 +#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD1_MSK 0xffffffff +#define FWCMD_C2HREG_ERR_RPT_FUNC_SH 0 +#define FWCMD_C2HREG_ERR_RPT_FUNC_MSK 0x7f +#define FWCMD_C2HREG_ERR_RPT_ACK BIT(7) +#define FWCMD_C2HREG_ERR_RPT_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_ERR_RPT_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_ERR_RPT_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_ERR_RPT_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_ERR_RPT_IDX_SH 16 +#define FWCMD_C2HREG_ERR_RPT_IDX_MSK 0xf +#define FWCMD_C2HREG_ERR_RPT_CODE_SH 0 +#define FWCMD_C2HREG_ERR_RPT_CODE_MSK 0xffffffff +#define FWCMD_C2HREG_ERR_MSG_FUNC_SH 0 +#define FWCMD_C2HREG_ERR_MSG_FUNC_MSK 0x7f +#define FWCMD_C2HREG_ERR_MSG_ACK BIT(7) +#define FWCMD_C2HREG_ERR_MSG_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_ERR_MSG_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_ERR_MSG_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_ERR_MSG_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_ERR_MSG_MSG_SH 16 +#define FWCMD_C2HREG_ERR_MSG_MSG_MSK 0xffff +#define FWCMD_C2HREG_EFUSE_HIDDEN_FUNC_SH 0 +#define FWCMD_C2HREG_EFUSE_HIDDEN_FUNC_MSK 0x7f +#define FWCMD_C2HREG_EFUSE_HIDDEN_ACK BIT(7) +#define FWCMD_C2HREG_EFUSE_HIDDEN_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_EFUSE_HIDDEN_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_EFUSE_HIDDEN_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_EFUSE_HIDDEN_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS_SH 16 +#define FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_BW_SH 24 +#define FWCMD_C2HREG_EFUSE_HIDDEN_BW_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS_SH 0 +#define FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211_SH 8 +#define FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER_SH 16 +#define FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT_SH 24 +#define FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE_SH 0 +#define FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0_SH 8 +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1_SH 16 +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2_SH 24 +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2_MSK 0xff +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3_SH 0 +#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3_MSK 0xff +#define FWCMD_C2HREG_TX_PAUSE_RPT_FUNC_SH 0 +#define FWCMD_C2HREG_TX_PAUSE_RPT_FUNC_MSK 0x7f +#define FWCMD_C2HREG_TX_PAUSE_RPT_ACK BIT(7) +#define FWCMD_C2HREG_TX_PAUSE_RPT_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_TX_PAUSE_RPT_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_TX_PAUSE_RPT_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_TX_PAUSE_RPT_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_TX_PAUSE_RPT_RPT_SH 16 +#define FWCMD_C2HREG_TX_PAUSE_RPT_RPT_MSK 0xffff +#define FWCMD_C2HREG_AOAC_RPT_1_FUNC_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_1_FUNC_MSK 0x7f +#define FWCMD_C2HREG_AOAC_RPT_1_ACK BIT(7) +#define FWCMD_C2HREG_AOAC_RPT_1_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_1_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_1_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_AOAC_RPT_1_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_0_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_0_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_1_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_1_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_2_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_2_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_3_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_3_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_4_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_4_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_5_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_5_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_6_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_6_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_IV_7_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_1_IV_7_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_FUNC_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_2_FUNC_MSK 0x7f +#define FWCMD_C2HREG_AOAC_RPT_2_ACK BIT(7) +#define FWCMD_C2HREG_AOAC_RPT_2_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_2_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_2_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_AOAC_RPT_2_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5_SH 24 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7_MSK 0xff +#define FWCMD_C2HREG_AOAC_RPT_2_RPT_MSK 0xffff +#define FWCMD_C2HREG_AOAC_RPT_3_FUNC_SH 0 +#define FWCMD_C2HREG_AOAC_RPT_3_FUNC_MSK 0x7f +#define FWCMD_C2HREG_AOAC_RPT_3_ACK BIT(7) +#define FWCMD_C2HREG_AOAC_RPT_3_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_AOAC_RPT_3_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_3_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_AOAC_RPT_3_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_AOAC_RPT_3_RPT_SH 16 +#define FWCMD_C2HREG_AOAC_RPT_3_RPT_MSK 0xffff +#define FWCMD_C2HREG_WOW_TRX_STOP_FUNC_SH 0 +#define FWCMD_C2HREG_WOW_TRX_STOP_FUNC_MSK 0x7f +#define FWCMD_C2HREG_WOW_TRX_STOP_ACK BIT(7) +#define FWCMD_C2HREG_WOW_TRX_STOP_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_WOW_TRX_STOP_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_WOW_TRX_STOP_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_WOW_TRX_STOP_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_WOW_TRX_STOP_RPT_SH 16 +#define FWCMD_C2HREG_WOW_TRX_STOP_RPT_MSK 0xffff +#define FWCMD_C2HREG_IO_OFLD_RESULT_FUNC_SH 0 +#define FWCMD_C2HREG_IO_OFLD_RESULT_FUNC_MSK 0x7f +#define FWCMD_C2HREG_IO_OFLD_RESULT_TOTAL_LEN_SH 8 +#define FWCMD_C2HREG_IO_OFLD_RESULT_TOTAL_LEN_MSK 0xf +#define FWCMD_C2HREG_IO_OFLD_RESULT_SEQ_NUM_SH 12 +#define FWCMD_C2HREG_IO_OFLD_RESULT_SEQ_NUM_MSK 0xf +#define FWCMD_C2HREG_IO_OFLD_RESULT_RET_SH 16 +#define FWCMD_C2HREG_IO_OFLD_RESULT_RET_MSK 0xff +#define FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM_SH 24 +#define FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM_MSK 0xff +#define FWCMD_C2HREG_IO_OFLD_RESULT_OFFSET_SH 0 +#define FWCMD_C2HREG_IO_OFLD_RESULT_OFFSET_MSK 0xffffffff +#define FWCMD_C2HREG_IO_OFLD_RESULT_EXP_VAL_SH 0 +#define FWCMD_C2HREG_IO_OFLD_RESULT_EXP_VAL_MSK 0xffffffff +#define FWCMD_C2HREG_IO_OFLD_RESULT_R_VAL_SH 0 +#define FWCMD_C2HREG_IO_OFLD_RESULT_R_VAL_MSK 0xffffffff + +// +//H2CPKT - CAT(TEST) +// +#define H2C_HDR_CAT_SH 0 +#define H2C_HDR_CAT_MSK 0x3 +#define H2C_HDR_CLASS_SH 2 +#define H2C_HDR_CLASS_MSK 0x3f +#define H2C_HDR_FUNC_SH 8 +#define H2C_HDR_FUNC_MSK 0xff +#define H2C_HDR_DEL_TYPE_SH 16 +#define H2C_HDR_DEL_TYPE_MSK 0xf +#define H2C_HDR_H2C_SEQ_SH 24 +#define H2C_HDR_H2C_SEQ_MSK 0xff +#define H2C_HDR_TOTAL_LEN_SH 0 +#define H2C_HDR_TOTAL_LEN_MSK 0x3fff +#define H2C_HDR_REC_ACK BIT(14) +#define H2C_HDR_DONE_ACK BIT(15) +#define H2C_HDR_SEQ_VALID BIT(16) +#define H2C_HDR_SEQ_SH 17 +#define H2C_HDR_SEQ_MSK 0x7 +#define H2C_HDR_SEQ_STOP BIT(20) +#define FWCMD_H2C_H2C_LB_PAYLOAD0_SH 0 +#define FWCMD_H2C_H2C_LB_PAYLOAD0_MSK 0xffffffff +#define FWCMD_H2C_H2C_LB_PAYLOAD1_SH 0 +#define FWCMD_H2C_H2C_LB_PAYLOAD1_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD0_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD0_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD1_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD1_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD2_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD2_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD3_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD3_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD4_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD4_MSK 0xffffffff +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD5_SH 0 +#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD5_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FL_WRITE_ADDR_SH 0 +#define FWCMD_H2C_PLAT_FL_WRITE_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FL_WRITE_LENGTH_SH 0 +#define FWCMD_H2C_PLAT_FL_WRITE_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FL_ERASE_ADDR_SH 0 +#define FWCMD_H2C_PLAT_FL_ERASE_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FL_ERASE_LENGTH_SH 0 +#define FWCMD_H2C_PLAT_FL_ERASE_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_PL_FLASH_READ_ADDR_SH 0 +#define FWCMD_H2C_PL_FLASH_READ_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PL_FLASH_READ_LENGTH_SH 0 +#define FWCMD_H2C_PL_FLASH_READ_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_LONG_RUN_PAYLOAD0_SH 0 +#define FWCMD_H2C_LONG_RUN_PAYLOAD0_MSK 0xffffffff +#define FWCMD_H2C_LONG_RUN_PAYLOAD1_SH 0 +#define FWCMD_H2C_LONG_RUN_PAYLOAD1_MSK 0xffffffff +#define FWCMD_H2C_LPS_TEST_COUNT_SH 0 +#define FWCMD_H2C_LPS_TEST_COUNT_MSK 0xffffffff +#define FWCMD_H2C_LPS_ONOFF_TEST_TYPE_SH 0 +#define FWCMD_H2C_LPS_ONOFF_TEST_TYPE_MSK 0xffffffff +#define FWCMD_H2C_LPS_ONOFF_TEST_PARA_SH 0 +#define FWCMD_H2C_LPS_ONOFF_TEST_PARA_MSK 0xffffffff +#define FWCMD_H2C_FW_STATUS_COUNT_SH 0 +#define FWCMD_H2C_FW_STATUS_COUNT_MSK 0xffffffff + +// +//H2CPKT - CAT(MAC) +// +#define H2C_HDR_CAT_SH 0 +#define H2C_HDR_CAT_MSK 0x3 +#define H2C_HDR_CLASS_SH 2 +#define H2C_HDR_CLASS_MSK 0x3f +#define H2C_HDR_FUNC_SH 8 +#define H2C_HDR_FUNC_MSK 0xff +#define H2C_HDR_DEL_TYPE_SH 16 +#define H2C_HDR_DEL_TYPE_MSK 0xf +#define H2C_HDR_H2C_SEQ_SH 24 +#define H2C_HDR_H2C_SEQ_MSK 0xff +#define H2C_HDR_TOTAL_LEN_SH 0 +#define H2C_HDR_TOTAL_LEN_MSK 0x3fff +#define H2C_HDR_REC_ACK BIT(14) +#define H2C_HDR_DONE_ACK BIT(15) +#define H2C_HDR_SEQ_VALID BIT(16) +#define H2C_HDR_SEQ_SH 17 +#define H2C_HDR_SEQ_MSK 0x7 +#define H2C_HDR_SEQ_STOP BIT(20) +#define FWCMD_H2C_LOG_CFG_DBG_LV_SH 0 +#define FWCMD_H2C_LOG_CFG_DBG_LV_MSK 0xff +#define FWCMD_H2C_LOG_CFG_PATH_SH 8 +#define FWCMD_H2C_LOG_CFG_PATH_MSK 0xff +#define FWCMD_H2C_LOG_CFG_COMP_SH 0 +#define FWCMD_H2C_LOG_CFG_COMP_MSK 0xffffffff +#define FWCMD_H2C_LOG_CFG_COMP_EXT_SH 0 +#define FWCMD_H2C_LOG_CFG_COMP_EXT_MSK 0xffffffff +#define FWCMD_H2C_GENERAL_PKT_MACID_SH 0 +#define FWCMD_H2C_GENERAL_PKT_MACID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_PROBRSP_ID_SH 8 +#define FWCMD_H2C_GENERAL_PKT_PROBRSP_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_PSPOLL_ID_SH 16 +#define FWCMD_H2C_GENERAL_PKT_PSPOLL_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_NULL_ID_SH 24 +#define FWCMD_H2C_GENERAL_PKT_NULL_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID_SH 0 +#define FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID_SH 8 +#define FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_PROBREQ_ID_SH 16 +#define FWCMD_H2C_GENERAL_PKT_PROBREQ_ID_MSK 0xff +#define FWCMD_H2C_GENERAL_PKT_APCSA_ID_SH 24 +#define FWCMD_H2C_GENERAL_PKT_APCSA_ID_MSK 0xff +#define FWCMD_H2C_C2H_RPT_CFG_TX_STATISTIC_EN BIT(0) +#define FWCMD_H2C_C2H_RPT_CFG_RX_STATISTIC_EN BIT(1) +#define FWCMD_H2C_C2H_RPT_CFG_BEACON_STATISTIC_EN BIT(2) +#define FWCMD_H2C_C2H_RPT_CFG_DL_STATISTIC_EN BIT(3) +#define FWCMD_H2C_C2H_RPT_CFG_RPT_INTERVAL_SH 0 +#define FWCMD_H2C_C2H_RPT_CFG_RPT_INTERVAL_MSK 0xffff +#define FWCMD_H2C_WLAN_DUMP_CMD_CMD_ID_SH 0 +#define FWCMD_H2C_WLAN_DUMP_CMD_CMD_ID_MSK 0xf +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV0_SH 8 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV0_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV1_SH 16 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV1_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV2_SH 24 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV2_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV3_SH 0 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV3_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV4_SH 8 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV4_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV5_SH 16 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV5_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV6_SH 24 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV6_MSK 0xff +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV7_SH 0 +#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV7_MSK 0xff +#define FWCMD_H2C_FW_DBGREG_CFG_FW_DBG_LOCK BIT(0) +#define FWCMD_H2C_KEEP_ALIVE_KEEPALIVE_EN BIT(0) +#define FWCMD_H2C_KEEP_ALIVE_PACKET_ID_SH 8 +#define FWCMD_H2C_KEEP_ALIVE_PACKET_ID_MSK 0xff +#define FWCMD_H2C_KEEP_ALIVE_PERIOD_SH 16 +#define FWCMD_H2C_KEEP_ALIVE_PERIOD_MSK 0xff +#define FWCMD_H2C_KEEP_ALIVE_MAC_ID_SH 24 +#define FWCMD_H2C_KEEP_ALIVE_MAC_ID_MSK 0xff +#define FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_DETECT_EN BIT(0) +#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN BIT(1) +#define FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_EN BIT(2) +#define FWCMD_H2C_DISCONNECT_DETECT_MAC_ID_SH 8 +#define FWCMD_H2C_DISCONNECT_DETECT_MAC_ID_MSK 0xff +#define FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD_SH 16 +#define FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD_MSK 0xff +#define FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT_SH 24 +#define FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT_MSK 0xff +#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT_SH 0 +#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT_MSK 0xff +#define FWCMD_H2C_WOW_GLOBAL_WOW_EN BIT(0) +#define FWCMD_H2C_WOW_GLOBAL_DROP_ALL_PKT BIT(1) +#define FWCMD_H2C_WOW_GLOBAL_RX_PARSE_AFTER_WAKE BIT(2) +#define FWCMD_H2C_WOW_GLOBAL_WAKE_BAR_PULLED BIT(3) +#define FWCMD_H2C_WOW_GLOBAL_MAC_ID_SH 8 +#define FWCMD_H2C_WOW_GLOBAL_MAC_ID_MSK 0xff +#define FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO_SH 16 +#define FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO_MSK 0xff +#define FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO_SH 24 +#define FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO_MSK 0xff +#define FWCMD_H2C_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT_SH 0 +#define FWCMD_H2C_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_GTK_OFLD_GTK_EN BIT(0) +#define FWCMD_H2C_GTK_OFLD_TKIP_EN BIT(1) +#define FWCMD_H2C_GTK_OFLD_IEEE80211W_EN BIT(2) +#define FWCMD_H2C_GTK_OFLD_PAIRWISE_WAKEUP BIT(3) +#define FWCMD_H2C_GTK_OFLD_AOAC_REPORT_ID_SH 8 +#define FWCMD_H2C_GTK_OFLD_AOAC_REPORT_ID_MSK 0xff +#define FWCMD_H2C_GTK_OFLD_MAC_ID_SH 16 +#define FWCMD_H2C_GTK_OFLD_MAC_ID_MSK 0xff +#define FWCMD_H2C_GTK_OFLD_GTK_RSP_ID_SH 24 +#define FWCMD_H2C_GTK_OFLD_GTK_RSP_ID_MSK 0xff +#define FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID_SH 0 +#define FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID_MSK 0xff +#define FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO_SH 8 +#define FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO_MSK 0x3 +#define FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT_SH 10 +#define FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT_MSK 0xff +#define FWCMD_H2C_GTK_OFLD_GTK_INFO_CONTENT_SH 0 +#define FWCMD_H2C_GTK_OFLD_GTK_INFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_ARP_OFLD_ARP_EN BIT(0) +#define FWCMD_H2C_ARP_OFLD_ARP_ACTION BIT(1) +#define FWCMD_H2C_ARP_OFLD_MAC_ID_SH 16 +#define FWCMD_H2C_ARP_OFLD_MAC_ID_MSK 0xff +#define FWCMD_H2C_ARP_OFLD_ARP_RSP_ID_SH 24 +#define FWCMD_H2C_ARP_OFLD_ARP_RSP_ID_MSK 0xff +#define FWCMD_H2C_ARP_OFLD_ARP_INFO_CONTENT_SH 0 +#define FWCMD_H2C_ARP_OFLD_ARP_INFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_NDP_OFLD_NDP_EN BIT(0) +#define FWCMD_H2C_NDP_OFLD_MAC_ID_SH 16 +#define FWCMD_H2C_NDP_OFLD_MAC_ID_MSK 0xff +#define FWCMD_H2C_NDP_OFLD_NA_ID_SH 24 +#define FWCMD_H2C_NDP_OFLD_NA_ID_MSK 0xff +#define FWCMD_H2C_NDP_OFLD_NDP_INFO_CONTENT_SH 0 +#define FWCMD_H2C_NDP_OFLD_NDP_INFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_REALWOW_REALWOW_EN BIT(0) +#define FWCMD_H2C_REALWOW_AUTO_WAKEUP BIT(1) +#define FWCMD_H2C_REALWOW_MAC_ID_SH 24 +#define FWCMD_H2C_REALWOW_MAC_ID_MSK 0xff +#define FWCMD_H2C_REALWOW_KEEPALIVE_ID_SH 0 +#define FWCMD_H2C_REALWOW_KEEPALIVE_ID_MSK 0xff +#define FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID_SH 8 +#define FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID_MSK 0xff +#define FWCMD_H2C_REALWOW_ACK_PATTERN_ID_SH 16 +#define FWCMD_H2C_REALWOW_ACK_PATTERN_ID_MSK 0xff +#define FWCMD_H2C_REALWOW_REALWOW_INFO_CONTENT_SH 0 +#define FWCMD_H2C_REALWOW_REALWOW_INFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_NLO_NLO_EN BIT(0) +#define FWCMD_H2C_NLO_NLO_32K_EN BIT(1) +#define FWCMD_H2C_NLO_IGNORE_CIPHER_TYPE BIT(2) +#define FWCMD_H2C_NLO_MAC_ID_SH 24 +#define FWCMD_H2C_NLO_MAC_ID_MSK 0xff +#define FWCMD_H2C_NLO_NLO_NETWORKLISTINFO_CONTENT_SH 0 +#define FWCMD_H2C_NLO_NLO_NETWORKLISTINFO_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_WAKEUP_CTRL_PATTERN_MATCH_EN BIT(0) +#define FWCMD_H2C_WAKEUP_CTRL_MAGIC_EN BIT(1) +#define FWCMD_H2C_WAKEUP_CTRL_HW_UNICAST_EN BIT(2) +#define FWCMD_H2C_WAKEUP_CTRL_FW_UNICAST_EN BIT(3) +#define FWCMD_H2C_WAKEUP_CTRL_DEAUTH_WAKEUP BIT(4) +#define FWCMD_H2C_WAKEUP_CTRL_REKEY_WAKEUP BIT(5) +#define FWCMD_H2C_WAKEUP_CTRL_EAP_WAKEUP BIT(6) +#define FWCMD_H2C_WAKEUP_CTRL_ALL_DATA_WAKEUP BIT(7) +#define FWCMD_H2C_WAKEUP_CTRL_MAC_ID_SH 24 +#define FWCMD_H2C_WAKEUP_CTRL_MAC_ID_MSK 0xff +#define FWCMD_H2C_NEGATIVE_PATTERN_NEGATIVE_PATTERN_EN BIT(0) +#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT_SH 20 +#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT_MSK 0xf +#define FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID_SH 24 +#define FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID_MSK 0xff +#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_CONTENT_SH 0 +#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_DEV2HST_GPIO_DEV2HST_GPIO_EN BIT(0) +#define FWCMD_H2C_DEV2HST_GPIO_DISABLE_INBAND BIT(1) +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_OUTPUT_INPUT BIT(2) +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_ACTIVE BIT(3) +#define FWCMD_H2C_DEV2HST_GPIO_TOGGLE_PULSE BIT(4) +#define FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP BIT(5) +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_NONSTOP BIT(6) +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_TIME_UNIT BIT(7) +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM_SH 8 +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION_SH 16 +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD_SH 24 +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT_SH 0 +#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID_SH 0 +#define FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_EN BIT(0) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_TOGGLE_PULSE BIT(1) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_NONSTOP BIT(2) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_TIME_UNIT BIT(3) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_SH 0 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION_SH 8 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD_SH 16 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT_SH 24 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_EN BIT(0) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_TOGGLE_PULSE BIT(1) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_NONSTOP BIT(2) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_TIME_UNIT BIT(3) +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_SH 0 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION_SH 8 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD_SH 16 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD_MSK 0xff +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT_SH 24 +#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT_MSK 0xff +#define FWCMD_H2C_UPHY_CTRL_DISABLE_UPHY BIT(0) +#define FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE_SH 1 +#define FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE_MSK 0x7 +#define FWCMD_H2C_UPHY_CTRL_RISE_HST2DEV_DIS_UPHY BIT(8) +#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_UNIT BIT(9) +#define FWCMD_H2C_UPHY_CTRL_PDN_AS_UPHY_DIS BIT(10) +#define FWCMD_H2C_UPHY_CTRL_PDN_TO_ENABLE_UPHY BIT(11) +#define FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM_SH 16 +#define FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM_MSK 0xff +#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT_SH 24 +#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT_MSK 0xff +#define FWCMD_H2C_WOW_CAM_UPD_R_W BIT(0) +#define FWCMD_H2C_WOW_CAM_UPD_IDX_SH 1 +#define FWCMD_H2C_WOW_CAM_UPD_IDX_MSK 0x7f +#define FWCMD_H2C_WOW_CAM_UPD_WKFM1_SH 0 +#define FWCMD_H2C_WOW_CAM_UPD_WKFM1_MSK 0xffffffff +#define FWCMD_H2C_WOW_CAM_UPD_WKFM2_SH 0 +#define FWCMD_H2C_WOW_CAM_UPD_WKFM2_MSK 0xffffffff +#define FWCMD_H2C_WOW_CAM_UPD_WKFM3_SH 0 +#define FWCMD_H2C_WOW_CAM_UPD_WKFM3_MSK 0xffffffff +#define FWCMD_H2C_WOW_CAM_UPD_WKFM4_SH 0 +#define FWCMD_H2C_WOW_CAM_UPD_WKFM4_MSK 0xffffffff +#define FWCMD_H2C_WOW_CAM_UPD_CRC_SH 0 +#define FWCMD_H2C_WOW_CAM_UPD_CRC_MSK 0xffff +#define FWCMD_H2C_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH BIT(22) +#define FWCMD_H2C_WOW_CAM_UPD_SKIP_MAC_HDR BIT(23) +#define FWCMD_H2C_WOW_CAM_UPD_UC BIT(24) +#define FWCMD_H2C_WOW_CAM_UPD_MC BIT(25) +#define FWCMD_H2C_WOW_CAM_UPD_BC BIT(26) +#define FWCMD_H2C_WOW_CAM_UPD_VALID BIT(31) +#define FWCMD_H2C_AOAC_REPORT_REQ_RX_READY BIT(0) +#define FWCMD_H2C_LPS_PARM_MACID_SH 0 +#define FWCMD_H2C_LPS_PARM_MACID_MSK 0xff +#define FWCMD_H2C_LPS_PARM_PSMODE_SH 8 +#define FWCMD_H2C_LPS_PARM_PSMODE_MSK 0xff +#define FWCMD_H2C_LPS_PARM_RLBM_SH 16 +#define FWCMD_H2C_LPS_PARM_RLBM_MSK 0xf +#define FWCMD_H2C_LPS_PARM_SMARTPS_SH 20 +#define FWCMD_H2C_LPS_PARM_SMARTPS_MSK 0xf +#define FWCMD_H2C_LPS_PARM_AWAKEINTERVAL_SH 24 +#define FWCMD_H2C_LPS_PARM_AWAKEINTERVAL_MSK 0xff +#define FWCMD_H2C_LPS_PARM_VOUAPSD BIT(0) +#define FWCMD_H2C_LPS_PARM_VIUAPSD BIT(1) +#define FWCMD_H2C_LPS_PARM_BEUAPSD BIT(2) +#define FWCMD_H2C_LPS_PARM_BKUAPSD BIT(3) +#define FWCMD_H2C_LPS_PARM_LASTRPWM_SH 8 +#define FWCMD_H2C_LPS_PARM_LASTRPWM_MSK 0xff +#define FWCMD_H2C_P2P_ACT_MACID_SH 0 +#define FWCMD_H2C_P2P_ACT_MACID_MSK 0xff +#define FWCMD_H2C_P2P_ACT_P2PID_SH 8 +#define FWCMD_H2C_P2P_ACT_P2PID_MSK 0xf +#define FWCMD_H2C_P2P_ACT_NOAID_SH 12 +#define FWCMD_H2C_P2P_ACT_NOAID_MSK 0xf +#define FWCMD_H2C_P2P_ACT_ACT_SH 16 +#define FWCMD_H2C_P2P_ACT_ACT_MSK 0xf +#define FWCMD_H2C_P2P_ACT_TYPE BIT(20) +#define FWCMD_H2C_P2P_ACT_ALL_SLEP BIT(21) +#define FWCMD_H2C_P2P_ACT_SRT_SH 0 +#define FWCMD_H2C_P2P_ACT_SRT_MSK 0xffffffff +#define FWCMD_H2C_P2P_ACT_ITVL_SH 0 +#define FWCMD_H2C_P2P_ACT_ITVL_MSK 0xffffffff +#define FWCMD_H2C_P2P_ACT_DUR_SH 0 +#define FWCMD_H2C_P2P_ACT_DUR_MSK 0xffffffff +#define FWCMD_H2C_P2P_ACT_CNT_SH 0 +#define FWCMD_H2C_P2P_ACT_CNT_MSK 0xff +#define FWCMD_H2C_P2P_ACT_CTW_SH 8 +#define FWCMD_H2C_P2P_ACT_CTW_MSK 0xffff +#define FWCMD_H2C_P2P_MACID_CTRL_P2PID_SH 0 +#define FWCMD_H2C_P2P_MACID_CTRL_P2PID_MSK 0xf +#define FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE_SH 4 +#define FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE_MSK 0xf +#define FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT_SH 8 +#define FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT_MSK 0xff +#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN_SH 16 +#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN_MSK 0xff +#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_SRT_SH 0 +#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_SRT_MSK 0xffffffff +#define FWCMD_H2C_IPS_CFG_MACID_SH 0 +#define FWCMD_H2C_IPS_CFG_MACID_MSK 0xff +#define FWCMD_H2C_IPS_CFG_ENABLE BIT(8) +#define FWCMD_H2C_PS_ADVANCE_PARM_MACID_SH 0 +#define FWCMD_H2C_PS_ADVANCE_PARM_MACID_MSK 0xff +#define FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMESET_SH 8 +#define FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMESET_MSK 0x3 +#define FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMEVAL_SH 0 +#define FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMEVAL_MSK 0xff +#define FWCMD_H2C_FWHDR_DL_FWHDR_SH 0 +#define FWCMD_H2C_FWHDR_DL_FWHDR_MSK 0xffffffff +#define FWCMD_H2C_FWHDR_REDL_FWHDR_SH 0 +#define FWCMD_H2C_FWHDR_REDL_FWHDR_MSK 0xffffffff +#define FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID_SH 0 +#define FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID_MSK 0xff +#define FWCMD_H2C_TWTINFO_UPD_NEGOTYPE_SH 0 +#define FWCMD_H2C_TWTINFO_UPD_NEGOTYPE_MSK 0x3 +#define FWCMD_H2C_TWTINFO_UPD_TRIGGER BIT(2) +#define FWCMD_H2C_TWTINFO_UPD_FLOWTYPE BIT(3) +#define FWCMD_H2C_TWTINFO_UPD_IMPT BIT(4) +#define FWCMD_H2C_TWTINFO_UPD_WAKEDURUNIT BIT(5) +#define FWCMD_H2C_TWTINFO_UPD_RSPPM BIT(6) +#define FWCMD_H2C_TWTINFO_UPD_FLOWID_SH 7 +#define FWCMD_H2C_TWTINFO_UPD_FLOWID_MSK 0x7 +#define FWCMD_H2C_TWTINFO_UPD_PROT BIT(10) +#define FWCMD_H2C_TWTINFO_UPD_ACT_SH 11 +#define FWCMD_H2C_TWTINFO_UPD_ACT_MSK 0x7 +#define FWCMD_H2C_TWTINFO_UPD_ID_SH 14 +#define FWCMD_H2C_TWTINFO_UPD_ID_MSK 0x7 +#define FWCMD_H2C_TWTINFO_UPD_BAND BIT(17) +#define FWCMD_H2C_TWTINFO_UPD_PORT_SH 18 +#define FWCMD_H2C_TWTINFO_UPD_PORT_MSK 0x7 +#define FWCMD_H2C_TWTINFO_UPD_WAKE_MAN_SH 0 +#define FWCMD_H2C_TWTINFO_UPD_WAKE_MAN_MSK 0xffff +#define FWCMD_H2C_TWTINFO_UPD_WAKE_EXP_SH 16 +#define FWCMD_H2C_TWTINFO_UPD_WAKE_EXP_MSK 0x1f +#define FWCMD_H2C_TWTINFO_UPD_ULFIXMODE_SH 21 +#define FWCMD_H2C_TWTINFO_UPD_ULFIXMODE_MSK 0x7 +#define FWCMD_H2C_TWTINFO_UPD_DUR_SH 24 +#define FWCMD_H2C_TWTINFO_UPD_DUR_MSK 0xff +#define FWCMD_H2C_TWTINFO_UPD_TGT_L_SH 0 +#define FWCMD_H2C_TWTINFO_UPD_TGT_L_MSK 0xffffffff +#define FWCMD_H2C_TWTINFO_UPD_TGT_H_SH 0 +#define FWCMD_H2C_TWTINFO_UPD_TGT_H_MSK 0xffffffff +#define FWCMD_H2C_TWT_STANSP_UPD_MACID_SH 0 +#define FWCMD_H2C_TWT_STANSP_UPD_MACID_MSK 0xff +#define FWCMD_H2C_TWT_STANSP_UPD_ID_SH 8 +#define FWCMD_H2C_TWT_STANSP_UPD_ID_MSK 0x7 +#define FWCMD_H2C_TWT_STANSP_UPD_ACT_SH 11 +#define FWCMD_H2C_TWT_STANSP_UPD_ACT_MSK 0xf +#define FWCMD_H2C_TBLUD_R_W BIT(0) +#define FWCMD_H2C_TBLUD_MACID_GROUP_SH 1 +#define FWCMD_H2C_TBLUD_MACID_GROUP_MSK 0x7f +#define FWCMD_H2C_TBLUD_OFFSET_SH 8 +#define FWCMD_H2C_TBLUD_OFFSET_MSK 0x1f +#define FWCMD_H2C_TBLUD_LENGTH_SH 13 +#define FWCMD_H2C_TBLUD_LENGTH_MSK 0x3ff +#define FWCMD_H2C_TBLUD_TYPE BIT(23) +#define FWCMD_H2C_TBLUD_TABLE_CLASS_SH 24 +#define FWCMD_H2C_TBLUD_TABLE_CLASS_MSK 0xff +#define FWCMD_H2C_DCTLINFO_UD_MACID_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_MACID_MSK 0x7f +#define FWCMD_H2C_DCTLINFO_UD_OP BIT(7) +#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_VAL_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_VAL_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_VAL_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_VAL_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_VAL_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_VAL_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_VAL_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_VAL_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_MSK_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_MSK_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_MSK_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_MSK_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_MSK_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_MSK_MSK 0xffffffff +#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_MSK_SH 0 +#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_MACID_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_MACID_MSK 0x7f +#define FWCMD_H2C_CCTLINFO_UD_OP BIT(7) +#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_VAL_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_VAL_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_MSK_MSK 0xffffffff +#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_MSK_SH 0 +#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_MSK_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D0_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D0_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D1_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D1_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D2_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D2_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D3_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D3_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D4_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D4_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D5_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D5_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D6_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D6_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D7_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D7_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D8_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D8_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D9_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D9_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D10_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D10_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D11_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D11_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D12_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D12_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D13_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D13_MSK 0xffffffff +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D14_SH 0 +#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D14_MSK 0xffffffff +#define FWCMD_H2C_BCN_UPD_PORT_SH 0 +#define FWCMD_H2C_BCN_UPD_PORT_MSK 0xff +#define FWCMD_H2C_BCN_UPD_MBSSID_SH 8 +#define FWCMD_H2C_BCN_UPD_MBSSID_MSK 0xff +#define FWCMD_H2C_BCN_UPD_BAND_SH 16 +#define FWCMD_H2C_BCN_UPD_BAND_MSK 0xff +#define FWCMD_H2C_BCN_UPD_GRP_IE_OFST_SH 24 +#define FWCMD_H2C_BCN_UPD_GRP_IE_OFST_MSK 0xff +#define FWCMD_H2C_BCN_UPD_MACID_SH 0 +#define FWCMD_H2C_BCN_UPD_MACID_MSK 0xff +#define FWCMD_H2C_BCN_UPD_SSN_SEL_SH 8 +#define FWCMD_H2C_BCN_UPD_SSN_SEL_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_SSN_MODE_SH 10 +#define FWCMD_H2C_BCN_UPD_SSN_MODE_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_RATE_SH 12 +#define FWCMD_H2C_BCN_UPD_RATE_MSK 0x1ff +#define FWCMD_H2C_BCN_UPD_TXPWR_SH 21 +#define FWCMD_H2C_BCN_UPD_TXPWR_MSK 0x7 +#define FWCMD_H2C_BCN_UPD_TXINFO_CTRL_EN BIT(0) +#define FWCMD_H2C_BCN_UPD_NTX_PATH_EN_SH 1 +#define FWCMD_H2C_BCN_UPD_NTX_PATH_EN_MSK 0xf +#define FWCMD_H2C_BCN_UPD_PATH_MAP_A_SH 5 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_A_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_B_SH 7 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_B_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_C_SH 9 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_C_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_D_SH 11 +#define FWCMD_H2C_BCN_UPD_PATH_MAP_D_MSK 0x3 +#define FWCMD_H2C_BCN_UPD_ANTSEL_A BIT(13) +#define FWCMD_H2C_BCN_UPD_ANTSEL_B BIT(14) +#define FWCMD_H2C_BCN_UPD_ANTSEL_C BIT(15) +#define FWCMD_H2C_BCN_UPD_ANTSEL_D BIT(16) +#define FWCMD_H2C_BCN_UPD_CSA_OFST_SH 17 +#define FWCMD_H2C_BCN_UPD_CSA_OFST_MSK 0x7fff +#define FWCMD_H2C_SS_ULSTA_UPD_MODE_SH 0 +#define FWCMD_H2C_SS_ULSTA_UPD_MODE_MSK 0xff +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U0_SH 0 +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U0_MSK 0xff +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U1_SH 8 +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U1_MSK 0xff +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U2_SH 16 +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U2_MSK 0xff +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U3_SH 24 +#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U3_MSK 0xff +#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0_SH 0 +#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0_MSK 0xffff +#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1_SH 16 +#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1_MSK 0xffff +#define FWCMD_H2C_F2PDBG_SET_SET_TXDBG BIT(0) +#define FWCMD_H2C_F2PDBG_SET_TXDBG_EN BIT(1) +#define FWCMD_H2C_F2PDBG_SET_SET_TPPKTSIZE BIT(2) +#define FWCMD_H2C_F2PDBG_SET_PKT_SIZE_SH 3 +#define FWCMD_H2C_F2PDBG_SET_PKT_SIZE_MSK 0xffff +#define FWCMD_H2C_WLANINFO_GET_INFO_SEL_SH 0 +#define FWCMD_H2C_WLANINFO_GET_INFO_SEL_MSK 0xf +#define FWCMD_H2C_WLANINFO_GET_ARGV0_SH 8 +#define FWCMD_H2C_WLANINFO_GET_ARGV0_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV1_SH 16 +#define FWCMD_H2C_WLANINFO_GET_ARGV1_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV2_SH 24 +#define FWCMD_H2C_WLANINFO_GET_ARGV2_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV3_SH 0 +#define FWCMD_H2C_WLANINFO_GET_ARGV3_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV4_SH 8 +#define FWCMD_H2C_WLANINFO_GET_ARGV4_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV5_SH 16 +#define FWCMD_H2C_WLANINFO_GET_ARGV5_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV6_SH 24 +#define FWCMD_H2C_WLANINFO_GET_ARGV6_MSK 0xff +#define FWCMD_H2C_WLANINFO_GET_ARGV7_SH 0 +#define FWCMD_H2C_WLANINFO_GET_ARGV7_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_R_W BIT(0) +#define FWCMD_H2C_ADDRCAM_INFO_IDX_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_IDX_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_OFFSET_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_OFFSET_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_LEN_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_LEN_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_VALID BIT(0) +#define FWCMD_H2C_ADDRCAM_INFO_NET_TYPE_SH 1 +#define FWCMD_H2C_ADDRCAM_INFO_NET_TYPE_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND_SH 3 +#define FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_HIT_RULE_SH 5 +#define FWCMD_H2C_ADDRCAM_INFO_HIT_RULE_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_BB_SEL BIT(7) +#define FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK_MSK 0x3f +#define FWCMD_H2C_ADDRCAM_INFO_MASK_SEL_SH 14 +#define FWCMD_H2C_ADDRCAM_INFO_MASK_SEL_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SMA_HASH_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_SMA_HASH_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA_HASH_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_TMA_HASH_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX_MSK 0x3f +#define FWCMD_H2C_ADDRCAM_INFO_IS_MUL_ENT BIT(8) +#define FWCMD_H2C_ADDRCAM_INFO_SMA0_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_SMA0_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SMA1_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_SMA1_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SMA2_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_SMA2_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SMA3_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_SMA3_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SMA4_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_SMA4_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SMA5_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_SMA5_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA0_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_TMA0_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA1_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_TMA1_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA2_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_TMA2_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA3_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_TMA3_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA4_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_TMA4_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_TMA5_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_TMA5_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_MACID_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_MACID_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_PORT_INT_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_PORT_INT_MSK 0x7 +#define FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC_SH 11 +#define FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC_MSK 0x7 +#define FWCMD_H2C_ADDRCAM_INFO_TF_TRS BIT(14) +#define FWCMD_H2C_ADDRCAM_INFO_LSIG_TXOP BIT(15) +#define FWCMD_H2C_ADDRCAM_INFO_TGT_IND_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_TGT_IND_MSK 0x7 +#define FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND_SH 27 +#define FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND_MSK 0x7 +#define FWCMD_H2C_ADDRCAM_INFO_AID12_0_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_AID12_0_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_AID12_1_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_AID12_1_MSK 0xf +#define FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN BIT(12) +#define FWCMD_H2C_ADDRCAM_INFO_WOL_UC BIT(13) +#define FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC BIT(14) +#define FWCMD_H2C_ADDRCAM_INFO_WAPI BIT(15) +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID_SH 18 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID_SH 20 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID_SH 22 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID_SH 26 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID_SH 28 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID_SH 30 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_B_IDX_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_B_IDX_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_B_OFFSET_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_B_OFFSET_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_B_LEN_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_B_LEN_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_B_VALID BIT(0) +#define FWCMD_H2C_ADDRCAM_INFO_B_BB_SEL BIT(1) +#define FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR_MSK 0x7f +#define FWCMD_H2C_ADDRCAM_INFO_BSSID0_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID0_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID1_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID1_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID2_SH 0 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID2_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID3_SH 8 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID3_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID4_SH 16 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID4_MSK 0xff +#define FWCMD_H2C_ADDRCAM_INFO_BSSID5_SH 24 +#define FWCMD_H2C_ADDRCAM_INFO_BSSID5_MSK 0xff +#define FWCMD_H2C_JOININFO_MACID_SH 0 +#define FWCMD_H2C_JOININFO_MACID_MSK 0xff +#define FWCMD_H2C_JOININFO_OPMODE BIT(8) +#define FWCMD_H2C_JOININFO_BAND BIT(9) +#define FWCMD_H2C_JOININFO_WMM_SH 10 +#define FWCMD_H2C_JOININFO_WMM_MSK 0x3 +#define FWCMD_H2C_JOININFO_TRIGGER BIT(12) +#define FWCMD_H2C_JOININFO_ISHESTA BIT(13) +#define FWCMD_H2C_JOININFO_DL_BW_SH 14 +#define FWCMD_H2C_JOININFO_DL_BW_MSK 0x3 +#define FWCMD_H2C_JOININFO_TF_MAC_PADDING_SH 16 +#define FWCMD_H2C_JOININFO_TF_MAC_PADDING_MSK 0x3 +#define FWCMD_H2C_JOININFO_DL_T_PE_SH 18 +#define FWCMD_H2C_JOININFO_DL_T_PE_MSK 0x7 +#define FWCMD_H2C_JOININFO_PORT_ID_SH 21 +#define FWCMD_H2C_JOININFO_PORT_ID_MSK 0x7 +#define FWCMD_H2C_JOININFO_NET_TYPE_SH 24 +#define FWCMD_H2C_JOININFO_NET_TYPE_MSK 0x3 +#define FWCMD_H2C_JOININFO_WIFI_ROLE_SH 26 +#define FWCMD_H2C_JOININFO_WIFI_ROLE_MSK 0xf +#define FWCMD_H2C_JOININFO_SELF_ROLE_SH 30 +#define FWCMD_H2C_JOININFO_SELF_ROLE_MSK 0x3 +#define FWCMD_H2C_DL_GRP_UPD_GRP_VALID BIT(0) +#define FWCMD_H2C_DL_GRP_UPD_GRP_ID_SH 1 +#define FWCMD_H2C_DL_GRP_UPD_GRP_ID_MSK 0x1f +#define FWCMD_H2C_DL_GRP_UPD_IS_HWGRP BIT(6) +#define FWCMD_H2C_DL_GRP_UPD_MACID_U0_SH 8 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U0_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U1_SH 16 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U1_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U2_SH 24 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U2_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U3_SH 0 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U3_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U4_SH 8 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U4_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U5_SH 16 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U5_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U6_SH 24 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U6_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_MACID_U7_SH 0 +#define FWCMD_H2C_DL_GRP_UPD_MACID_U7_MSK 0xff +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0_SH 8 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1_SH 12 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2_SH 16 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3_SH 20 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4_SH 24 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5_SH 28 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6_SH 0 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7_SH 4 +#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE_SH 8 +#define FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE_MSK 0xf +#define FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE_SH 12 +#define FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE_MSK 0xf +#define FWCMD_H2C_UL_GRP_UPD_MACID_U0_SH 0 +#define FWCMD_H2C_UL_GRP_UPD_MACID_U0_MSK 0xff +#define FWCMD_H2C_UL_GRP_UPD_MACID_U1_SH 8 +#define FWCMD_H2C_UL_GRP_UPD_MACID_U1_MSK 0xff +#define FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP_SH 16 +#define FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP_MSK 0xffff +#define FWCMD_H2C_MU_STA_UPD_MACID_SH 0 +#define FWCMD_H2C_MU_STA_UPD_MACID_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_MU_IDX_SH 8 +#define FWCMD_H2C_MU_STA_UPD_MU_IDX_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0_SH 16 +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1_SH 24 +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2_SH 0 +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3_SH 8 +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4_SH 16 +#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4_MSK 0xff +#define FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP_SH 24 +#define FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP_MSK 0x1f +#define FWCMD_H2C_MU_STA_UPD_DIS_256Q BIT(29) +#define FWCMD_H2C_MU_STA_UPD_DIS_1024Q BIT(30) +#define FWCMD_H2C_FWROLE_MAINTAIN_MACID_SH 0 +#define FWCMD_H2C_FWROLE_MAINTAIN_MACID_MSK 0xff +#define FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE_SH 8 +#define FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE_MSK 0x3 +#define FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE_SH 10 +#define FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE_MSK 0x7 +#define FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE_SH 13 +#define FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE_MSK 0xf +#define FWCMD_H2C_NOTIFY_DBCC_EN BIT(0) +#define FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE_SH 0 +#define FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE_MSK 0x7ff +#define FWCMD_H2C_DUMP_EFUSE_IS_HIDDEN BIT(11) +#define FWCMD_H2C_PACKET_OFLD_PKT_IDX_SH 0 +#define FWCMD_H2C_PACKET_OFLD_PKT_IDX_MSK 0xff +#define FWCMD_H2C_PACKET_OFLD_PKT_OP_SH 8 +#define FWCMD_H2C_PACKET_OFLD_PKT_OP_MSK 0x7 +#define FWCMD_H2C_PACKET_OFLD_PKT_LENGTH_SH 16 +#define FWCMD_H2C_PACKET_OFLD_PKT_LENGTH_MSK 0xffff +#define FWCMD_H2C_PACKET_OFLD_PKT_START_SH 0 +#define FWCMD_H2C_PACKET_OFLD_PKT_START_MSK 0xffffffff +#define FWCMD_H2C_READ_OFLD_VALUE_LEN_SH 0 +#define FWCMD_H2C_READ_OFLD_VALUE_LEN_MSK 0x7ff +#define FWCMD_H2C_READ_OFLD_LS BIT(15) +#define FWCMD_H2C_READ_OFLD_OFLD_ID_SH 16 +#define FWCMD_H2C_READ_OFLD_OFLD_ID_MSK 0xff +#define FWCMD_H2C_READ_OFLD_ENTRY_NUM_SH 24 +#define FWCMD_H2C_READ_OFLD_ENTRY_NUM_MSK 0xff +#define FWCMD_H2C_READ_OFLD_OFFSET_SH 0 +#define FWCMD_H2C_READ_OFLD_OFFSET_MSK 0xffff +#define FWCMD_H2C_WRITE_OFLD_VALUE_LEN_SH 0 +#define FWCMD_H2C_WRITE_OFLD_VALUE_LEN_MSK 0x7ff +#define FWCMD_H2C_WRITE_OFLD_POLLING BIT(13) +#define FWCMD_H2C_WRITE_OFLD_MASK_EN BIT(14) +#define FWCMD_H2C_WRITE_OFLD_LS BIT(15) +#define FWCMD_H2C_WRITE_OFLD_OFLD_ID_SH 16 +#define FWCMD_H2C_WRITE_OFLD_OFLD_ID_MSK 0xff +#define FWCMD_H2C_WRITE_OFLD_ENTRY_NUM_SH 24 +#define FWCMD_H2C_WRITE_OFLD_ENTRY_NUM_MSK 0xff +#define FWCMD_H2C_WRITE_OFLD_OFFSET_SH 0 +#define FWCMD_H2C_WRITE_OFLD_OFFSET_MSK 0xffff +#define FWCMD_H2C_WRITE_OFLD_START_SH 0 +#define FWCMD_H2C_WRITE_OFLD_START_MSK 0xffffffff +#define FWCMD_H2C_CONF_OFLD_PATTERN_COUNT_SH 0 +#define FWCMD_H2C_CONF_OFLD_PATTERN_COUNT_MSK 0xffff +#define FWCMD_H2C_CONF_OFLD_START_SH 0 +#define FWCMD_H2C_CONF_OFLD_START_MSK 0xffffffff +#define FWCMD_H2C_TRX_INIT_TRX_MODE_SH 0 +#define FWCMD_H2C_TRX_INIT_TRX_MODE_MSK 0xff +#define FWCMD_H2C_TRX_INIT_QTA_MODE_SH 8 +#define FWCMD_H2C_TRX_INIT_QTA_MODE_MSK 0x1ff +#define FWCMD_H2C_INTF_INIT_TXBD_TRUNC_MODE BIT(0) +#define FWCMD_H2C_INTF_INIT_RXBD_TRUNC_MODE BIT(1) +#define FWCMD_H2C_INTF_INIT_RXBD_MODE BIT(2) +#define FWCMD_H2C_INTF_INIT_TAG_MODE BIT(3) +#define FWCMD_H2C_INTF_INIT_TX_BURST_MODE_SH 4 +#define FWCMD_H2C_INTF_INIT_TX_BURST_MODE_MSK 0xf +#define FWCMD_H2C_INTF_INIT_RX_BURST_MODE_SH 8 +#define FWCMD_H2C_INTF_INIT_RX_BURST_MODE_MSK 0xf +#define FWCMD_H2C_INTF_INIT_WD_DMA_IDLE_INTVL_SH 12 +#define FWCMD_H2C_INTF_INIT_WD_DMA_IDLE_INTVL_MSK 0xf +#define FWCMD_H2C_INTF_INIT_WD_DMA_ACT_INTVL_SH 16 +#define FWCMD_H2C_INTF_INIT_WD_DMA_ACT_INTVL_MSK 0xf +#define FWCMD_H2C_INTF_INIT_SKIP_ALL_SH 24 +#define FWCMD_H2C_INTF_INIT_SKIP_ALL_MSK 0xff +#define FWCMD_H2C_INTF_INIT_RX_SEP_APPEND_LEN_SH 0 +#define FWCMD_H2C_INTF_INIT_RX_SEP_APPEND_LEN_MSK 0xffff +#define FWCMD_H2C_INTF_INIT_TXBD_BUF_SH 16 +#define FWCMD_H2C_INTF_INIT_TXBD_BUF_MSK 0xff +#define FWCMD_H2C_INTF_INIT_RXBD_BUF_SH 24 +#define FWCMD_H2C_INTF_INIT_RXBD_BUF_MSK 0xff +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_1_SH 0 +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_1_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_2_SH 0 +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_2_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_3_SH 0 +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_3_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_4_SH 0 +#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_4_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_1_SH 0 +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_1_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_2_SH 0 +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_2_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_3_SH 0 +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_3_MSK 0xffffffff +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_4_SH 0 +#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_4_MSK 0xffffffff +#define FWCMD_H2C_RX_FWD_TYPE_SH 0 +#define FWCMD_H2C_RX_FWD_TYPE_MSK 0xff +#define FWCMD_H2C_RX_FWD_FRAME_SH 8 +#define FWCMD_H2C_RX_FWD_FRAME_MSK 0xff +#define FWCMD_H2C_RX_FWD_FWD_TG_SH 16 +#define FWCMD_H2C_RX_FWD_FWD_TG_MSK 0xff +#define FWCMD_H2C_RX_FWD_AF_UD_INDEX_SH 0 +#define FWCMD_H2C_RX_FWD_AF_UD_INDEX_MSK 0xff +#define FWCMD_H2C_RX_FWD_AF_UD_FWD_TG_SH 8 +#define FWCMD_H2C_RX_FWD_AF_UD_FWD_TG_MSK 0xff +#define FWCMD_H2C_RX_FWD_AF_UD_CATEGORY_SH 16 +#define FWCMD_H2C_RX_FWD_AF_UD_CATEGORY_MSK 0xff +#define FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD_SH 24 +#define FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD_MSK 0xff +#define FWCMD_H2C_RX_FWD_PM_CAM_VALID BIT(0) +#define FWCMD_H2C_RX_FWD_PM_CAM_TYPE_SH 1 +#define FWCMD_H2C_RX_FWD_PM_CAM_TYPE_MSK 0x3 +#define FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE_SH 3 +#define FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE_MSK 0xf +#define FWCMD_H2C_RX_FWD_PM_CAM_SKIP_MAC_IV_HDR BIT(7) +#define FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND_SH 8 +#define FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND_MSK 0x7 +#define FWCMD_H2C_RX_FWD_PM_CAM_INDEX_SH 12 +#define FWCMD_H2C_RX_FWD_PM_CAM_INDEX_MSK 0xf +#define FWCMD_H2C_RX_FWD_PM_CAM_CRC16_SH 16 +#define FWCMD_H2C_RX_FWD_PM_CAM_CRC16_MSK 0xffff +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0_SH 0 +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0_MSK 0xffffffff +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1_SH 0 +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1_MSK 0xffffffff +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2_SH 0 +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2_MSK 0xffffffff +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3_SH 0 +#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3_MSK 0xffffffff +#define FWCMD_H2C_EN_MAC_HDR_CONV_ENABLE BIT(0) +#define FWCMD_H2C_SET_HWSEQ_REG_REG_IDX_SH 0 +#define FWCMD_H2C_SET_HWSEQ_REG_REG_IDX_MSK 0x3 +#define FWCMD_H2C_SET_HWSEQ_REG_SEQ_VAL_SH 2 +#define FWCMD_H2C_SET_HWSEQ_REG_SEQ_VAL_MSK 0xfff +#define FWCMD_H2C_HWAMSDU_REG_ENABLE BIT(0) +#define FWCMD_H2C_HWAMSDU_REG_MAX_AMSDU_SUBFRAME_NUMBER_SH 1 +#define FWCMD_H2C_HWAMSDU_REG_MAX_AMSDU_SUBFRAME_NUMBER_MSK 0x3 +#define FWCMD_H2C_HWAMSDU_REG_ENABLE_SINGLE_AMSDU BIT(3) +#define FWCMD_H2C_HWAMSDU_REG_ENABLE_LAST_AMSDU_PADDING BIT(4) +#define FWCMD_H2C_AMSDU_CUT_REG_ENABLE BIT(0) +#define FWCMD_H2C_AMSDU_CUT_REG_LOW_THRESHOLD_SH 1 +#define FWCMD_H2C_AMSDU_CUT_REG_LOW_THRESHOLD_MSK 0x1ff +#define FWCMD_H2C_AMSDU_CUT_REG_HIGH_THRESHOLD_SH 10 +#define FWCMD_H2C_AMSDU_CUT_REG_HIGH_THRESHOLD_MSK 0xffff +#define FWCMD_H2C_AMSDU_CUT_REG_EXTRA_SHIFT_SH 26 +#define FWCMD_H2C_AMSDU_CUT_REG_EXTRA_SHIFT_MSK 0x3 +#define FWCMD_H2C_TCPIP_CHKSUM_OFFLOAD_REG_ENABLE_TX_TCPIP_CHECKSUM_OFFLOAD BIT(0) +#define FWCMD_H2C_TCPIP_CHKSUM_OFFLOAD_REG_ENABLE_RX_TCPIP_CHECKSUM_OFFLOAD BIT(1) +#define FWCMD_H2C_USR_EDCA_PARAM_SEL_SH 0 +#define FWCMD_H2C_USR_EDCA_PARAM_SEL_MSK 0x3 +#define FWCMD_H2C_USR_EDCA_ENABLE BIT(2) +#define FWCMD_H2C_USR_EDCA_BAND BIT(3) +#define FWCMD_H2C_USR_EDCA_WMM BIT(4) +#define FWCMD_H2C_USR_EDCA_AC_SH 5 +#define FWCMD_H2C_USR_EDCA_AC_MSK 0x3 +#define FWCMD_H2C_USR_EDCA_AGGRESSIVE_SH 0 +#define FWCMD_H2C_USR_EDCA_AGGRESSIVE_MSK 0xffffffff +#define FWCMD_H2C_USR_EDCA_MODERATE_SH 0 +#define FWCMD_H2C_USR_EDCA_MODERATE_MSK 0xffffffff +#define FWCMD_H2C_TSF32_TOGL_BAND BIT(0) +#define FWCMD_H2C_TSF32_TOGL_EN BIT(1) +#define FWCMD_H2C_TSF32_TOGL_PORT_SH 2 +#define FWCMD_H2C_TSF32_TOGL_PORT_MSK 0x7 +#define FWCMD_H2C_TSF32_TOGL_EARLY_SH 16 +#define FWCMD_H2C_TSF32_TOGL_EARLY_MSK 0xffff +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D0_SH 0 +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D0_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D1_SH 0 +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D1_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D2_SH 0 +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D2_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D3_SH 0 +#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D3_MSK 0xffffffff +#define FWCMD_H2C_USR_TX_RPT_MODE_SH 0 +#define FWCMD_H2C_USR_TX_RPT_MODE_MSK 0x7 +#define FWCMD_H2C_USR_TX_RPT_RTP_START BIT(3) +#define FWCMD_H2C_USR_TX_RPT_MACID_SH 0 +#define FWCMD_H2C_USR_TX_RPT_MACID_MSK 0xff +#define FWCMD_H2C_USR_TX_RPT_AC_SH 8 +#define FWCMD_H2C_USR_TX_RPT_AC_MSK 0x3 +#define FWCMD_H2C_USR_TX_RPT_BAND BIT(10) +#define FWCMD_H2C_USR_TX_RPT_PORT_SH 11 +#define FWCMD_H2C_USR_TX_RPT_PORT_MSK 0x7 +#define FWCMD_H2C_USR_TX_RPT_RPT_PERIOD_SH 0 +#define FWCMD_H2C_USR_TX_RPT_RPT_PERIOD_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D0_SH 0 +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D0_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D1_SH 0 +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D1_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D2_SH 0 +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D2_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D3_SH 0 +#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D3_MSK 0xffffffff +#define FWCMD_H2C_OFLD_CFG_MODE_SH 0 +#define FWCMD_H2C_OFLD_CFG_MODE_MSK 0x7 +#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE BIT(3) +#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE_VAL_SH 0 +#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE_VAL_MSK 0xffff +#define FWCMD_H2C_H2C_AGG_PLD_SH 0 +#define FWCMD_H2C_H2C_AGG_PLD_MSK 0xffffffff +#define FWCMD_H2C_ADD_SCANOFLD_CH_NUM_OF_CH_SH 0 +#define FWCMD_H2C_ADD_SCANOFLD_CH_NUM_OF_CH_MSK 0xff +#define FWCMD_H2C_ADD_SCANOFLD_CH_SIZE_OF_CHINFO_SH 8 +#define FWCMD_H2C_ADD_SCANOFLD_CH_SIZE_OF_CHINFO_MSK 0xff +#define FWCMD_H2C_SCANOFLD_MACID_SH 0 +#define FWCMD_H2C_SCANOFLD_MACID_MSK 0xff +#define FWCMD_H2C_SCANOFLD_NORM_CY_SH 8 +#define FWCMD_H2C_SCANOFLD_NORM_CY_MSK 0xff +#define FWCMD_H2C_SCANOFLD_PORT_ID_SH 16 +#define FWCMD_H2C_SCANOFLD_PORT_ID_MSK 0x7 +#define FWCMD_H2C_SCANOFLD_BAND BIT(19) +#define FWCMD_H2C_SCANOFLD_OPERATION_SH 20 +#define FWCMD_H2C_SCANOFLD_OPERATION_MSK 0x3 +#define FWCMD_H2C_SCANOFLD_C2H_NOTIFY_END BIT(0) +#define FWCMD_H2C_SCANOFLD_TARGET_CH_MODE BIT(1) +#define FWCMD_H2C_SCANOFLD_START_MODE BIT(2) +#define FWCMD_H2C_SCANOFLD_SCAN_TYPE_SH 3 +#define FWCMD_H2C_SCANOFLD_SCAN_TYPE_MSK 0x3 +#define FWCMD_H2C_SCANOFLD_TARGET_CH_BW_SH 5 +#define FWCMD_H2C_SCANOFLD_TARGET_CH_BW_MSK 0x7 +#define FWCMD_H2C_SCANOFLD_TARGET_PRI_CH_SH 8 +#define FWCMD_H2C_SCANOFLD_TARGET_PRI_CH_MSK 0xff +#define FWCMD_H2C_SCANOFLD_TARGET_CENTRAL_CH_SH 16 +#define FWCMD_H2C_SCANOFLD_TARGET_CENTRAL_CH_MSK 0xff +#define FWCMD_H2C_SCANOFLD_PROBE_REQ_PKT_ID_SH 24 +#define FWCMD_H2C_SCANOFLD_PROBE_REQ_PKT_ID_MSK 0xff +#define FWCMD_H2C_SCANOFLD_NORM_PD_SH 0 +#define FWCMD_H2C_SCANOFLD_NORM_PD_MSK 0xffff +#define FWCMD_H2C_SCANOFLD_SLOW_PD_SH 16 +#define FWCMD_H2C_SCANOFLD_SLOW_PD_MSK 0xffff +#define FWCMD_H2C_SCANOFLD_TSF_HIGH_SH 0 +#define FWCMD_H2C_SCANOFLD_TSF_HIGH_MSK 0xffffffff +#define FWCMD_H2C_SCANOFLD_TSF_LOW_SH 0 +#define FWCMD_H2C_SCANOFLD_TSF_LOW_MSK 0xffffffff +#define FWCMD_H2C_DISABLE_RF_FUNC_SH 0 +#define FWCMD_H2C_DISABLE_RF_FUNC_MSK 0xf +#define FWCMD_H2C_DISABLE_RF_NET_TYPE_SH 4 +#define FWCMD_H2C_DISABLE_RF_NET_TYPE_MSK 0x3 +#define FWCMD_H2C_TX_DUTY_PAUSE_INTVL_SH 0 +#define FWCMD_H2C_TX_DUTY_PAUSE_INTVL_MSK 0xffff +#define FWCMD_H2C_TX_DUTY_TX_INTVL_SH 16 +#define FWCMD_H2C_TX_DUTY_TX_INTVL_MSK 0xffff +#define FWCMD_H2C_TX_DUTY_STOP BIT(0) +#define FWCMD_H2C_CH_SWITCH_PRI_CH_SH 0 +#define FWCMD_H2C_CH_SWITCH_PRI_CH_MSK 0xff +#define FWCMD_H2C_CH_SWITCH_CENTRAL_CH_SH 8 +#define FWCMD_H2C_CH_SWITCH_CENTRAL_CH_MSK 0xff +#define FWCMD_H2C_CH_SWITCH_BW_SH 16 +#define FWCMD_H2C_CH_SWITCH_BW_MSK 0x7 +#define FWCMD_H2C_CH_SWITCH_CH_BAND_SH 19 +#define FWCMD_H2C_CH_SWITCH_CH_BAND_MSK 0x3 +#define FWCMD_H2C_CH_SWITCH_BAND BIT(21) +#define FWCMD_H2C_CH_SWITCH_RELOAD_RF BIT(22) +#define FWCMD_H2C_PKT_DROP_DROP_SEL_SH 0 +#define FWCMD_H2C_PKT_DROP_DROP_SEL_MSK 0xff +#define FWCMD_H2C_PKT_DROP_MACID_SH 8 +#define FWCMD_H2C_PKT_DROP_MACID_MSK 0xff +#define FWCMD_H2C_PKT_DROP_BAND_SH 16 +#define FWCMD_H2C_PKT_DROP_BAND_MSK 0xff +#define FWCMD_H2C_PKT_DROP_PORT_SH 24 +#define FWCMD_H2C_PKT_DROP_PORT_MSK 0xff +#define FWCMD_H2C_PKT_DROP_MBSSID_SH 0 +#define FWCMD_H2C_PKT_DROP_MBSSID_MSK 0xff +#define FWCMD_H2C_PKT_DROP_ROLE_A_INFO_TF_TRS_SH 8 +#define FWCMD_H2C_PKT_DROP_ROLE_A_INFO_TF_TRS_MSK 0xff +#define FWCMD_H2C_PKT_DROP_RSVVD_SH 16 +#define FWCMD_H2C_PKT_DROP_RSVVD_MSK 0xffff +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_0_SH 0 +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_0_MSK 0xffffffff +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_1_SH 0 +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_1_MSK 0xffffffff +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_2_SH 0 +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_2_MSK 0xffffffff +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_3_SH 0 +#define FWCMD_H2C_PKT_DROP_MACID_BAND_SEL_3_MSK 0xffffffff +#define FWCMD_H2C_SECCAM_INFO_IDX_SH 0 +#define FWCMD_H2C_SECCAM_INFO_IDX_MSK 0xff +#define FWCMD_H2C_SECCAM_INFO_OFFSET_SH 8 +#define FWCMD_H2C_SECCAM_INFO_OFFSET_MSK 0xff +#define FWCMD_H2C_SECCAM_INFO_LEN_SH 16 +#define FWCMD_H2C_SECCAM_INFO_LEN_MSK 0xff +#define FWCMD_H2C_SECCAM_INFO_TYPE_SH 0 +#define FWCMD_H2C_SECCAM_INFO_TYPE_MSK 0xf +#define FWCMD_H2C_SECCAM_INFO_EXT_KEY BIT(4) +#define FWCMD_H2C_SECCAM_INFO_SPP_MODE BIT(5) +#define FWCMD_H2C_SECCAM_INFO_KEY_0_SH 0 +#define FWCMD_H2C_SECCAM_INFO_KEY_0_MSK 0xffffffff +#define FWCMD_H2C_SECCAM_INFO_KEY_1_SH 0 +#define FWCMD_H2C_SECCAM_INFO_KEY_1_MSK 0xffffffff +#define FWCMD_H2C_SECCAM_INFO_KEY_2_SH 0 +#define FWCMD_H2C_SECCAM_INFO_KEY_2_MSK 0xffffffff +#define FWCMD_H2C_SECCAM_INFO_KEY_3_SH 0 +#define FWCMD_H2C_SECCAM_INFO_KEY_3_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE_SH 0 +#define FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_MODE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_MODE_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_MACID0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_MACID0_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID1_SH 8 +#define FWCMD_H2C_SET_SND_PARA_MACID1_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID2_SH 16 +#define FWCMD_H2C_SET_SND_PARA_MACID2_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID3_SH 24 +#define FWCMD_H2C_SET_SND_PARA_MACID3_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_MACID4_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID5_SH 8 +#define FWCMD_H2C_SET_SND_PARA_MACID5_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID6_SH 16 +#define FWCMD_H2C_SET_SND_PARA_MACID6_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_MACID7_SH 24 +#define FWCMD_H2C_SET_SND_PARA_MACID7_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_NDPA_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_HE BIT(0) +#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG_SH 1 +#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL_SH 16 +#define FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_FEEDBACK_TYPE BIT(12) +#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC_SH 13 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12_SH 16 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_FEEDBACK_TYPE BIT(28) +#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_FEEDBACK_TYPE BIT(12) +#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC_SH 13 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12_SH 16 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_FEEDBACK_TYPE BIT(28) +#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA0_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA1_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA2_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA3_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA4_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA5_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA6_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_HE_STA7_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH_SH 4 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF BIT(16) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED BIT(17) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW_SH 18 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF_SH 20 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE BIT(22) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF_SH 23 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC BIT(29) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL BIT(30) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER BIT(31) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_TRIGGER_INFO_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_TRIGGER_INFO_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_LENGTH_SH 4 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_LENGTH_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_MORE_TF BIT(16) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_CS_REQUIRED BIT(17) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_BW_SH 18 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_BW_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_GI_LTF_SH 20 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_GI_LTF_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_MU_MIMO_LTF_MODE BIT(22) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_NUM_OF_HE_LTF_SH 23 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_NUM_OF_HE_LTF_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_PKTEXT_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_PKTEXT_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_STBC BIT(29) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_LDPC_EXTRA_SYMBOL BIT(30) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_DOPPLER BIT(31) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_AP_TX_POWER_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_AP_TX_POWER_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_SPATIAL_REUSE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_SPATIAL_REUSE_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT_SH 8 +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT_SH 16 +#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0_SH 16 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0_SH 9 +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0_SH 19 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0_SH 28 +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0_SH 4 +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0_SH 8 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0_SH 11 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0_SH 24 +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0_SH 27 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD1_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD1_SH 16 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD1_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD1_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD1_SH 9 +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD1_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD1_SH 19 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD1 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD1 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD1 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD1 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD1 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD1 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD1_SH 28 +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD1_SH 4 +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD1_SH 8 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD1_SH 11 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD1 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD1 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD1_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD1 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD1_SH 24 +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD1_SH 27 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD2_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD2_SH 16 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD2_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD2_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD2_SH 9 +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD2_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD2 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD2_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD2_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD2_SH 19 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD2 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD2 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD2 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD2 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD2 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD2 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD2_SH 28 +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD2_SH 4 +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD2_SH 8 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD2_SH 11 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD2 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD2 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD2 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD2_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD2_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD2 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD2_SH 24 +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD2_SH 27 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD2_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD3_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD3_SH 16 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD3_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD3_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD3_SH 9 +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD3_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD3 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD3_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD3_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD3_SH 19 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD3 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD3 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD3 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD3 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD3 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD3 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD3_SH 28 +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD3_SH 4 +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD3_SH 8 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD3_SH 11 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD3 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD3 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD3 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD3_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD3_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD3 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD3_SH 24 +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD3_SH 27 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD3_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD4_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD4_SH 16 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD4_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD4_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD4_SH 9 +#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD4_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD4 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD4_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD4_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD4_SH 19 +#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD4 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD4 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD4 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD4 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD4 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD4 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD4_SH 28 +#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD4_SH 4 +#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD4_SH 8 +#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD4_SH 11 +#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD4 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD4 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD4 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD4_SH 17 +#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD4_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD4 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD4_SH 24 +#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD4_SH 27 +#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD4_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0_SH 12 +#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0_SH 14 +#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0_MSK 0x3ff +#define FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP1_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP1_SH 12 +#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP1_SH 14 +#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP1_MSK 0x3ff +#define FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP1 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_F2P_TYPE_SH 0 +#define FWCMD_H2C_SET_SND_PARA_F2P_TYPE_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_F2P_INDEX_SH 8 +#define FWCMD_H2C_SET_SND_PARA_F2P_INDEX_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_F2P_PERIOD_SH 16 +#define FWCMD_H2C_SET_SND_PARA_F2P_PERIOD_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT_SH 0 +#define FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_CR_IDX_SH 8 +#define FWCMD_H2C_SET_SND_PARA_CR_IDX_MSK 0x3fffff +#define FWCMD_H2C_GET_CSI_BUF_BAND_SH 0 +#define FWCMD_H2C_GET_CSI_BUF_BAND_MSK 0xff +#define FWCMD_H2C_GET_CSI_BUF_CSI_BUF_ID_SH 8 +#define FWCMD_H2C_GET_CSI_BUF_CSI_BUF_ID_MSK 0xff +#define FWCMD_H2C_SET_CSI_BUF_BAND_SH 0 +#define FWCMD_H2C_SET_CSI_BUF_BAND_MSK 0xff +#define FWCMD_H2C_SET_CSI_BUF_MACID_SH 8 +#define FWCMD_H2C_SET_CSI_BUF_MACID_MSK 0xff +#define FWCMD_H2C_SET_CSI_BUF_CSI_BUF_ID_SH 16 +#define FWCMD_H2C_SET_CSI_BUF_CSI_BUF_ID_MSK 0xffff +#define FWCMD_H2C_SET_CSI_BUF_BUF_IDX_SH 0 +#define FWCMD_H2C_SET_CSI_BUF_BUF_IDX_MSK 0xffff +#define FWCMD_H2C_GET_SND_STS_BAND_SH 0 +#define FWCMD_H2C_GET_SND_STS_BAND_MSK 0xff +#define FWCMD_H2C_GET_SND_STS_INDEX_SH 8 +#define FWCMD_H2C_GET_SND_STS_INDEX_MSK 0xff +#define FWCMD_H2C_SET_SND_STS_BAND_SH 0 +#define FWCMD_H2C_SET_SND_STS_BAND_MSK 0xff +#define FWCMD_H2C_SET_SND_STS_MACID_SH 8 +#define FWCMD_H2C_SET_SND_STS_MACID_MSK 0xff +#define FWCMD_H2C_SET_SND_STS_INDEX_SH 16 +#define FWCMD_H2C_SET_SND_STS_INDEX_MSK 0xff +#define FWCMD_H2C_INIT_SND_MER_BAND_SH 0 +#define FWCMD_H2C_INIT_SND_MER_BAND_MSK 0xff +#define FWCMD_H2C_INIT_SND_MEE_BAND_SH 0 +#define FWCMD_H2C_INIT_SND_MEE_BAND_MSK 0xff +#define FWCMD_H2C_CSI_FIX_RATE_BAND_SH 0 +#define FWCMD_H2C_CSI_FIX_RATE_BAND_MSK 0xff +#define FWCMD_H2C_CSI_FIX_RATE_HT_RATE_SH 8 +#define FWCMD_H2C_CSI_FIX_RATE_HT_RATE_MSK 0xff +#define FWCMD_H2C_CSI_FIX_RATE_VHT_RATE_SH 16 +#define FWCMD_H2C_CSI_FIX_RATE_VHT_RATE_MSK 0xff +#define FWCMD_H2C_CSI_FIX_RATE_HE_RATE_SH 24 +#define FWCMD_H2C_CSI_FIX_RATE_HE_RATE_MSK 0xff +#define FWCMD_H2C_CSI_RRSC_BAND_SH 0 +#define FWCMD_H2C_CSI_RRSC_BAND_MSK 0xff +#define FWCMD_H2C_CSI_RRSC_RRSC_SH 0 +#define FWCMD_H2C_CSI_RRSC_RRSC_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_CTRL_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_CTRL_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_0_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_0_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_1_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_1_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_2_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_2_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_3_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_3_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_4_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_4_MSK 0xffffffff +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_5_SH 0 +#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_5_MSK 0xffffffff +#define FWCMD_H2C_SET_CSI_PARA_REG_BAND BIT(0) +#define FWCMD_H2C_SET_CSI_PARA_REG_PORT_SEL BIT(1) +#define FWCMD_H2C_SET_CSI_PARA_REG_NC_SH 2 +#define FWCMD_H2C_SET_CSI_PARA_REG_NC_MSK 0x7 +#define FWCMD_H2C_SET_CSI_PARA_REG_NR_SH 5 +#define FWCMD_H2C_SET_CSI_PARA_REG_NR_MSK 0x7 +#define FWCMD_H2C_SET_CSI_PARA_REG_NG_SH 8 +#define FWCMD_H2C_SET_CSI_PARA_REG_NG_MSK 0x3 +#define FWCMD_H2C_SET_CSI_PARA_REG_CB_SH 10 +#define FWCMD_H2C_SET_CSI_PARA_REG_CB_MSK 0x3 +#define FWCMD_H2C_SET_CSI_PARA_REG_CS_SH 12 +#define FWCMD_H2C_SET_CSI_PARA_REG_CS_MSK 0x3 +#define FWCMD_H2C_SET_CSI_PARA_REG_LDPC_EN BIT(14) +#define FWCMD_H2C_SET_CSI_PARA_REG_STBC_EN BIT(15) +#define FWCMD_H2C_SET_CSI_PARA_REG_BF_EN BIT(16) +#define FWCMD_H2C_HW_SND_PR_BAND_SH 0 +#define FWCMD_H2C_HW_SND_PR_BAND_MSK 0xff +#define FWCMD_H2C_HW_SND_PR_PR_SH 8 +#define FWCMD_H2C_HW_SND_PR_PR_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_FREXCH_TYPE_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_FREXCH_TYPE_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_MODE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_V1_MODE_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_USER_NUM_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_USER_NUM_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_USER_NUM_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_USER_NUM_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID0_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID1_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID1_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID2_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID2_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID3_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID3_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID4_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID5_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID5_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID6_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID6_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID7_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID7_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID8_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID8_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID9_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID9_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID10_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID10_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID11_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID11_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID12_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID13_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID13_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID14_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID14_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_MACID15_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_MACID15_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_FRAME_CTRL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_FRAME_CTRL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_HE BIT(0) +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_DIALOG_SH 1 +#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_DIALOG_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_HT_SEQ_CONTROL_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_HT_SEQ_CONTROL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_FEEDBACK_TYPE BIT(12) +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_NC_SH 13 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_AID12_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_FEEDBACK_TYPE BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_FEEDBACK_TYPE BIT(12) +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_NC_SH 13 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_AID12_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_FEEDBACK_TYPE BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_AID11_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_AID11_MSK 0x7ff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_BW_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_BW_MSK 0x3fff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_FB_NG_SH 25 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_FB_NG_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_DISAMBIGUATION BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_CB BIT(28) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_NC_SH 29 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_NC_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_FRAME_CTL_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_FRAME_CTL_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_DURATION_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_DURATION_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_L_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_L_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_H_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_L_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_L_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_H_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_H_MSK 0xffffffff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_TRIGGER_INFO_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_TRIGGER_INFO_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_LENGTH_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_LENGTH_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_MORE_TF BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_CS_REQUIRED BIT(17) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_BW_SH 18 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_BW_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_GI_LTF_SH 20 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_GI_LTF_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_MU_MIMO_LTF_MODE BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_NUM_OF_HE_LTF_SH 23 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_NUM_OF_HE_LTF_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_PKTEXT_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_PKTEXT_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_STBC BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_LDPC_EXTRA_SYMBOL BIT(30) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_DOPPLER BIT(31) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_AP_TX_POWER_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_AP_TX_POWER_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_SPATIAL_REUSE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_SPATIAL_REUSE_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_TRIGGER_INFO_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_TRIGGER_INFO_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_LENGTH_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_LENGTH_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_MORE_TF BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_CS_REQUIRED BIT(17) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_BW_SH 18 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_BW_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_GI_LTF_SH 20 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_GI_LTF_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_MU_MIMO_LTF_MODE BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_NUM_OF_HE_LTF_SH 23 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_NUM_OF_HE_LTF_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_PKTEXT_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_PKTEXT_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_STBC BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_LDPC_EXTRA_SYMBOL BIT(30) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_DOPPLER BIT(31) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_AP_TX_POWER_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_AP_TX_POWER_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_SPATIAL_REUSE_SH 6 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_SPATIAL_REUSE_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_AID12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_AID12_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_RU_POS_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_RU_POS_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_FEC_CODE BIT(20) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_MCS_SH 21 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_MCS_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_DCM BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_SS_ALLOC_SH 26 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_SS_ALLOC_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_TGT_RSSI_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP0_FEEDBACKSEG_REXMIT_BITMAP_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP1_FEEDBACKSEG_REXMIT_BITMAP_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP2_FEEDBACKSEG_REXMIT_BITMAP_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD0_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD0_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD0_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD0_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD0_SH 9 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD0_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD0_SH 19 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD0 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD0 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD0 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD0 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD0 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD0 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD0_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD0_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD0_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD0_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD0 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD0 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD0_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD0 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD0_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD0_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD0_SH 27 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD0 BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD1_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD1_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD1_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD1_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD1_SH 9 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD1_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD1_SH 19 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD1 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD1 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD1 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD1 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD1 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD1 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD1_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD1_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD1_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD1_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD1 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD1 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD1_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD1 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD1_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD1_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD1_SH 27 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD1 BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD2_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD2_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD2_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD2_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD2_SH 9 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD2_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD2 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD2_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD2_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD2_SH 19 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD2 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD2 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD2 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD2 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD2 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD2 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD2_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD2_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD2_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD2_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD2_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD2_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD2 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD2 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD2 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD2_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD2_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD2 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD2_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD2_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD2_SH 27 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD2_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD2 BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD3_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD3_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD3_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD3_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD3_SH 9 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD3_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD3 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD3_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD3_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD3_SH 19 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD3 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD3 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD3 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD3 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD3 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD3 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD3_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD3_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD3_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD3_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD3_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD3_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD3 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD3 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD3 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD3_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD3_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD3 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD3_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD3_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD3_SH 27 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD3_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD3 BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD4_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD4_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD4_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD4_MSK 0x1ff +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD4_SH 9 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD4_MSK 0x7f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD4 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD4_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD4_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD4_SH 19 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD4 BIT(22) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD4 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD4 BIT(24) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD4 BIT(25) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD4 BIT(26) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD4 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD4_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD4_SH 4 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD4_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD4_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD4_SH 11 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD4 BIT(14) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD4 BIT(15) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD4 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD4_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD4_MSK 0x3f +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD4 BIT(23) +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD4_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD4_MSK 0x7 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD4_SH 27 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD4_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD4 BIT(29) +#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP0_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP0_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP0_SH 14 +#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP0_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_UL_CQI_RPT_TRI_BFRP0 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP0_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP0_MSK 0x3ff +#define FWCMD_H2C_SET_SND_PARA_V1_FIX_GAIN_EN_BFRP0 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP0_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP0_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP1_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP1_MSK 0xfff +#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP1_SH 12 +#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP1_SH 14 +#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP1_MSK 0x3 +#define FWCMD_H2C_SET_SND_PARA_V1_UL_CQI_RPT_TRI_BFRP1 BIT(16) +#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP1_SH 17 +#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP1_MSK 0x3ff +#define FWCMD_H2C_SET_SND_PARA_V1_FIX_GAIN_EN_BFRP1 BIT(27) +#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP1_SH 28 +#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP1_MSK 0xf +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_TYPE_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_TYPE_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_INDEX_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_INDEX_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_PERIOD_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_PERIOD_MSK 0xffff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX0_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX0_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX1_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX1_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX2_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX2_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX3_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX3_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX4_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX4_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX5_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX5_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX6_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX6_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX7_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX7_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX8_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX8_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX9_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX9_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX10_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX10_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX11_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX11_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX12_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX12_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX13_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX13_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX14_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX14_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX15_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX15_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX16_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX16_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX17_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX17_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX18_SH 16 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX18_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX19_SH 24 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX19_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX20_SH 0 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX20_MSK 0xff +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX21_SH 8 +#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX21_MSK 0xff +#define FWCMD_H2C_BA_CAM_VALID BIT(0) +#define FWCMD_H2C_BA_CAM_INIT_REQ BIT(1) +#define FWCMD_H2C_BA_CAM_ENTRY_IDX_SH 2 +#define FWCMD_H2C_BA_CAM_ENTRY_IDX_MSK 0x3 +#define FWCMD_H2C_BA_CAM_TID_SH 4 +#define FWCMD_H2C_BA_CAM_TID_MSK 0xf +#define FWCMD_H2C_BA_CAM_MACID_SH 8 +#define FWCMD_H2C_BA_CAM_MACID_MSK 0xff +#define FWCMD_H2C_BA_CAM_BMAP_SIZE_SH 16 +#define FWCMD_H2C_BA_CAM_BMAP_SIZE_MSK 0xf +#define FWCMD_H2C_BA_CAM_SSN_SH 20 +#define FWCMD_H2C_BA_CAM_SSN_MSK 0xfff +#define FWCMD_H2C_BA_CAM_UID_VALUE_SH 0 +#define FWCMD_H2C_BA_CAM_UID_VALUE_MSK 0xff +#define FWCMD_H2C_BA_CAM_STD_ENTRY_EN BIT(8) +#define FWCMD_H2C_BA_CAM_BAND_SEL BIT(9) +#define FWCMD_H2C_BA_CAM_ENTRY_IDX_V1_SH 28 +#define FWCMD_H2C_BA_CAM_ENTRY_IDX_V1_MSK 0xf +#define FWCMD_H2C_IE_CAM_BAND BIT(0) +#define FWCMD_H2C_IE_CAM_PORT_SH 1 +#define FWCMD_H2C_IE_CAM_PORT_MSK 0x7 +#define FWCMD_H2C_IE_CAM_CAM_EN BIT(4) +#define FWCMD_H2C_IE_CAM_HIT_FRWD_EN BIT(5) +#define FWCMD_H2C_IE_CAM_HIT_FRWD_SH 6 +#define FWCMD_H2C_IE_CAM_HIT_FRWD_MSK 0x3 +#define FWCMD_H2C_IE_CAM_MISS_FRWD_EN BIT(8) +#define FWCMD_H2C_IE_CAM_MISS_FRWD_SH 9 +#define FWCMD_H2C_IE_CAM_MISS_FRWD_MSK 0x3 +#define FWCMD_H2C_IE_CAM_UPD_NUM_SH 11 +#define FWCMD_H2C_IE_CAM_UPD_NUM_MSK 0x1f +#define FWCMD_H2C_IE_CAM_RST BIT(16) +#define FWCMD_H2C_IE_CAM_IDX_SH 0 +#define FWCMD_H2C_IE_CAM_IDX_MSK 0xff +#define FWCMD_H2C_IE_CAM_CAM_INFO0_SH 8 +#define FWCMD_H2C_IE_CAM_CAM_INFO0_MSK 0xffffff +#define FWCMD_H2C_IE_CAM_CAM_INFO1_SH 0 +#define FWCMD_H2C_IE_CAM_CAM_INFO1_MSK 0xffffffff +#define FWCMD_H2C_ADD_MCC_MACID_SH 0 +#define FWCMD_H2C_ADD_MCC_MACID_MSK 0xff +#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0_SH 8 +#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0_MSK 0xff +#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1_SH 16 +#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1_MSK 0xff +#define FWCMD_H2C_ADD_MCC_PRIMARY_CH_SH 24 +#define FWCMD_H2C_ADD_MCC_PRIMARY_CH_MSK 0xff +#define FWCMD_H2C_ADD_MCC_BANDWIDTH_SH 0 +#define FWCMD_H2C_ADD_MCC_BANDWIDTH_MSK 0xf +#define FWCMD_H2C_ADD_MCC_GROUP_SH 4 +#define FWCMD_H2C_ADD_MCC_GROUP_MSK 0x3 +#define FWCMD_H2C_ADD_MCC_C2H_RPT_SH 6 +#define FWCMD_H2C_ADD_MCC_C2H_RPT_MSK 0x3 +#define FWCMD_H2C_ADD_MCC_DIS_TX_NULL BIT(8) +#define FWCMD_H2C_ADD_MCC_DIS_SW_RETRY BIT(9) +#define FWCMD_H2C_ADD_MCC_IN_CURR_CH BIT(10) +#define FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT_SH 11 +#define FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT_MSK 0x7 +#define FWCMD_H2C_ADD_MCC_TX_NULL_EARLY_SH 14 +#define FWCMD_H2C_ADD_MCC_TX_NULL_EARLY_MSK 0xf +#define FWCMD_H2C_ADD_MCC_BTC_IN_2G BIT(18) +#define FWCMD_H2C_ADD_MCC_PTA_EN BIT(19) +#define FWCMD_H2C_ADD_MCC_RFK_BY_PASS BIT(20) +#define FWCMD_H2C_ADD_MCC_DURATION_SH 0 +#define FWCMD_H2C_ADD_MCC_DURATION_MSK 0xffffffff +#define FWCMD_H2C_ADD_MCC_COURTESY_EN BIT(0) +#define FWCMD_H2C_ADD_MCC_COURTESY_NUM_SH 8 +#define FWCMD_H2C_ADD_MCC_COURTESY_NUM_MSK 0xff +#define FWCMD_H2C_ADD_MCC_COURTESY_TARGET_SH 16 +#define FWCMD_H2C_ADD_MCC_COURTESY_TARGET_MSK 0xff +#define FWCMD_H2C_START_MCC_GROUP_SH 0 +#define FWCMD_H2C_START_MCC_GROUP_MSK 0x3 +#define FWCMD_H2C_START_MCC_BTC_IN_GROUP BIT(2) +#define FWCMD_H2C_START_MCC_OLD_GROUP_ACTION_SH 3 +#define FWCMD_H2C_START_MCC_OLD_GROUP_ACTION_MSK 0x3 +#define FWCMD_H2C_START_MCC_OLD_GROUP_SH 5 +#define FWCMD_H2C_START_MCC_OLD_GROUP_MSK 0x3 +#define FWCMD_H2C_START_MCC_MACID_SH 24 +#define FWCMD_H2C_START_MCC_MACID_MSK 0xff +#define FWCMD_H2C_START_MCC_TSF_LOW_SH 0 +#define FWCMD_H2C_START_MCC_TSF_LOW_MSK 0xffffffff +#define FWCMD_H2C_START_MCC_TSF_HIGH_SH 0 +#define FWCMD_H2C_START_MCC_TSF_HIGH_MSK 0xffffffff +#define FWCMD_H2C_STOP_MCC_MACID_SH 0 +#define FWCMD_H2C_STOP_MCC_MACID_MSK 0xff +#define FWCMD_H2C_STOP_MCC_GROUP_SH 8 +#define FWCMD_H2C_STOP_MCC_GROUP_MSK 0x3 +#define FWCMD_H2C_STOP_MCC_PREV_GROUPS BIT(10) +#define FWCMD_H2C_DEL_MCC_GROUP_GROUP_SH 0 +#define FWCMD_H2C_DEL_MCC_GROUP_GROUP_MSK 0x3 +#define FWCMD_H2C_DEL_MCC_GROUP_PREV_GROUPS BIT(2) +#define FWCMD_H2C_RESET_MCC_GROUP_GROUP_SH 0 +#define FWCMD_H2C_RESET_MCC_GROUP_GROUP_MSK 0x3 +#define FWCMD_H2C_MCC_REQ_TSF_GROUP_SH 0 +#define FWCMD_H2C_MCC_REQ_TSF_GROUP_MSK 0x3 +#define FWCMD_H2C_MCC_REQ_TSF_MACID_X_SH 8 +#define FWCMD_H2C_MCC_REQ_TSF_MACID_X_MSK 0xff +#define FWCMD_H2C_MCC_REQ_TSF_MACID_Y_SH 16 +#define FWCMD_H2C_MCC_REQ_TSF_MACID_Y_MSK 0xff +#define FWCMD_H2C_MCC_MACID_BITMAP_GROUP_SH 0 +#define FWCMD_H2C_MCC_MACID_BITMAP_GROUP_MSK 0x3 +#define FWCMD_H2C_MCC_MACID_BITMAP_MACID_SH 8 +#define FWCMD_H2C_MCC_MACID_BITMAP_MACID_MSK 0xff +#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH_SH 16 +#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH_MSK 0xff +#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_SH 0 +#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_MSK 0xffffffff +#define FWCMD_H2C_MCC_SYNC_GROUP_SH 0 +#define FWCMD_H2C_MCC_SYNC_GROUP_MSK 0x3 +#define FWCMD_H2C_MCC_SYNC_MACID_SOURCE_SH 8 +#define FWCMD_H2C_MCC_SYNC_MACID_SOURCE_MSK 0xff +#define FWCMD_H2C_MCC_SYNC_MACID_TARGET_SH 16 +#define FWCMD_H2C_MCC_SYNC_MACID_TARGET_MSK 0xff +#define FWCMD_H2C_MCC_SYNC_SYNC_OFFSET_SH 24 +#define FWCMD_H2C_MCC_SYNC_SYNC_OFFSET_MSK 0xff +#define FWCMD_H2C_MCC_SET_DURATION_GROUP_SH 0 +#define FWCMD_H2C_MCC_SET_DURATION_GROUP_MSK 0x3 +#define FWCMD_H2C_MCC_SET_DURATION_BTC_IN_GROUP BIT(2) +#define FWCMD_H2C_MCC_SET_DURATION_START_MACID_SH 8 +#define FWCMD_H2C_MCC_SET_DURATION_START_MACID_MSK 0xff +#define FWCMD_H2C_MCC_SET_DURATION_MACID_X_SH 16 +#define FWCMD_H2C_MCC_SET_DURATION_MACID_X_MSK 0xff +#define FWCMD_H2C_MCC_SET_DURATION_MACID_Y_SH 24 +#define FWCMD_H2C_MCC_SET_DURATION_MACID_Y_MSK 0xff +#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW_SH 0 +#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW_MSK 0xffffffff +#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH_SH 0 +#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH_MSK 0xffffffff +#define FWCMD_H2C_MCC_SET_DURATION_DURATION_X_SH 0 +#define FWCMD_H2C_MCC_SET_DURATION_DURATION_X_MSK 0xffffffff +#define FWCMD_H2C_MCC_SET_DURATION_DURATION_Y_SH 0 +#define FWCMD_H2C_MCC_SET_DURATION_DURATION_Y_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_WRITE_ADDR_SH 0 +#define FWCMD_H2C_PLAT_FLASH_WRITE_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_WRITE_LENGTH_SH 0 +#define FWCMD_H2C_PLAT_FLASH_WRITE_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_WRITE_PAYLOAD0_SH 0 +#define FWCMD_H2C_PLAT_FLASH_WRITE_PAYLOAD0_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_ERASE_ADDR_SH 0 +#define FWCMD_H2C_PLAT_FLASH_ERASE_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_ERASE_LENGTH_SH 0 +#define FWCMD_H2C_PLAT_FLASH_ERASE_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_READ_ADDR_SH 0 +#define FWCMD_H2C_PLAT_FLASH_READ_ADDR_MSK 0xffffffff +#define FWCMD_H2C_PLAT_FLASH_READ_LENGTH_SH 0 +#define FWCMD_H2C_PLAT_FLASH_READ_LENGTH_MSK 0xffffffff +#define FWCMD_H2C_FCS_AP_PORT_ID_SH 0 +#define FWCMD_H2C_FCS_AP_PORT_ID_MSK 0xf +#define FWCMD_H2C_FCS_CH_IDX_SH 4 +#define FWCMD_H2C_FCS_CH_IDX_MSK 0xf +#define FWCMD_H2C_FCS_THERMAL_IDX_SH 8 +#define FWCMD_H2C_FCS_THERMAL_IDX_MSK 0xf +#define FWCMD_H2C_FCS_PAUSE_REL_MODE_SH 12 +#define FWCMD_H2C_FCS_PAUSE_REL_MODE_MSK 0xf +#define FWCMD_H2C_FCS_CON_STA_NUM_SH 16 +#define FWCMD_H2C_FCS_CON_STA_NUM_MSK 0xff +#define FWCMD_H2C_FCS_BAND BIT(24) +#define FWCMD_H2C_FCS_BANDWIDTH_SH 25 +#define FWCMD_H2C_FCS_BANDWIDTH_MSK 0x3 +#define FWCMD_H2C_FCS_PRI_CH_SH 0 +#define FWCMD_H2C_FCS_PRI_CH_MSK 0xff +#define FWCMD_H2C_FCS_CENTRAL_CH_SH 8 +#define FWCMD_H2C_FCS_CENTRAL_CH_MSK 0xff +#define FWCMD_H2C_FCS_REL_PAUSE_TSFL_SH 0 +#define FWCMD_H2C_FCS_REL_PAUSE_TSFL_MSK 0xffffffff +#define FWCMD_H2C_FCS_REL_PAUSE_TSFH_SH 0 +#define FWCMD_H2C_FCS_REL_PAUSE_TSFH_MSK 0xffffffff +#define FWCMD_H2C_FCS_REL_PAUSE_DELAY_TIME_SH 0 +#define FWCMD_H2C_FCS_REL_PAUSE_DELAY_TIME_MSK 0xffffffff +#define FWCMD_H2C_FCS_CSA_PKT_ID0_SH 0 +#define FWCMD_H2C_FCS_CSA_PKT_ID0_MSK 0xff +#define FWCMD_H2C_FCS_CSA_PKT_ID1_SH 8 +#define FWCMD_H2C_FCS_CSA_PKT_ID1_MSK 0xff +#define FWCMD_H2C_FCS_CSA_PKT_ID2_SH 16 +#define FWCMD_H2C_FCS_CSA_PKT_ID2_MSK 0xff +#define FWCMD_H2C_FCS_CSA_PKT_ID3_SH 24 +#define FWCMD_H2C_FCS_CSA_PKT_ID3_MSK 0xff +#define FWCMD_H2C_CFG_WPS_EN BIT(0) +#define FWCMD_H2C_CFG_WPS_GPIO_SH 8 +#define FWCMD_H2C_CFG_WPS_GPIO_MSK 0xff +#define FWCMD_H2C_CFG_WPS_INTL_SH 16 +#define FWCMD_H2C_CFG_WPS_INTL_MSK 0xff +#define FWCMD_H2C_PORT_INIT_BAND BIT(0) +#define FWCMD_H2C_PORT_INIT_PORT_SH 1 +#define FWCMD_H2C_PORT_INIT_PORT_MSK 0x7 +#define FWCMD_H2C_PORT_INIT_NET_TYPE_SH 4 +#define FWCMD_H2C_PORT_INIT_NET_TYPE_MSK 0x7 +#define FWCMD_H2C_PORT_INIT_DTIM_PRD_SH 8 +#define FWCMD_H2C_PORT_INIT_DTIM_PRD_MSK 0xff +#define FWCMD_H2C_PORT_INIT_MBSSID_NUM_SH 16 +#define FWCMD_H2C_PORT_INIT_MBSSID_NUM_MSK 0xff +#define FWCMD_H2C_PORT_INIT_BSS_COLOR_SH 24 +#define FWCMD_H2C_PORT_INIT_BSS_COLOR_MSK 0xff +#define FWCMD_H2C_PORT_INIT_BCN_ITVL_SH 0 +#define FWCMD_H2C_PORT_INIT_BCN_ITVL_MSK 0xffff +#define FWCMD_H2C_PORT_INIT_HIQ_WND_SH 16 +#define FWCMD_H2C_PORT_INIT_HIQ_WND_MSK 0xff +#define FWCMD_H2C_PORT_CFG_BAND BIT(0) +#define FWCMD_H2C_PORT_CFG_PORT_SH 1 +#define FWCMD_H2C_PORT_CFG_PORT_MSK 0x7 +#define FWCMD_H2C_PORT_CFG_MBSSID_IDX_SH 8 +#define FWCMD_H2C_PORT_CFG_MBSSID_IDX_MSK 0xff +#define FWCMD_H2C_PORT_CFG_TYPE_SH 16 +#define FWCMD_H2C_PORT_CFG_TYPE_MSK 0xff +#define FWCMD_H2C_PORT_CFG_VAL_SH 0 +#define FWCMD_H2C_PORT_CFG_VAL_MSK 0xffffffff + +// +//H2CPKT - CAT(Table) +// +#define FWCMD_H2C_MUDE_PARA_TBLUD_TBLUD_SH 0 +#define FWCMD_H2C_MUDE_PARA_TBLUD_TBLUD_MSK 0xffffffff +#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA0_SH 0 +#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA0_MSK 0xffffffff +#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA1_SH 0 +#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA1_MSK 0xffffffff +#define FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD_SH 0 +#define FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD_MSK 0x3fffffff +#define FWCMD_H2C_MUDECISION_PARA_BYPASS_THOLD BIT(30) +#define FWCMD_H2C_MUDECISION_PARA_BYPASS_TP BIT(31) +#define FWCMD_H2C_MUDECISION_PARA_INIT_RATE_SH 0 +#define FWCMD_H2C_MUDECISION_PARA_INIT_RATE_MSK 0xf +#define FWCMD_H2C_MUDECISION_PARA_RETRY_TH_SH 4 +#define FWCMD_H2C_MUDECISION_PARA_RETRY_TH_MSK 0x7 +#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLDEN BIT(0) +#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLD_SH 1 +#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLD_MSK 0x3fffffff +#define FWCMD_H2C_MU_FIXINFO_BYPASS_THOLD BIT(31) +#define FWCMD_H2C_MU_FIXINFO_FIXMU_EN BIT(0) +#define FWCMD_H2C_MU_FIXINFO_FIXMU_ID_SH 1 +#define FWCMD_H2C_MU_FIXINFO_FIXMU_ID_MSK 0x7f +#define FWCMD_H2C_UL_FIXINFO_TBLUD_TBLUD_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_TBLUD_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D0_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D2_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D2_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D3_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D3_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D4_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D4_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D5_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D5_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D6_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D6_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D7_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D7_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D8_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D8_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D9_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D9_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D10_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D10_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D11_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D11_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D12_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D12_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D13_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D13_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D14_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D14_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D15_SH 0 +#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D15_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_CFG_MODE_SH 0 +#define FWCMD_H2C_UL_FIXINFO_CFG_MODE_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL_SH 2 +#define FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL_MSK 0x3f +#define FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD_SH 8 +#define FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD_MSK 0xff +#define FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE_SH 16 +#define FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR_SH 0 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR_MSK 0xffff +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE_SH 16 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGEN BIT(19) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC_SH 20 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC_MSK 0xf +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MURTS BIT(24) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_SH 25 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT_SH 27 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF_SH 29 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATART_SH 0 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATART_MSK 0x1ff +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATAER BIT(9) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW_SH 10 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_STBC_SH 12 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_STBC_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_LDPC BIT(14) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATADCM BIT(15) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN_SH 16 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN_MSK 0xfff +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MORETF BIT(28) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATA_VWER BIT(29) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_ISTWT BIT(30) +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT_SH 0 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID_SH 3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID_MSK 0xf +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE_SH 7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE_SH 10 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL_SH 13 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX_SH 15 +#define FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX_MSK 0xf +#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_0_1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_0_1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_2_3_SH 0 +#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_2_3_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_ULRUA_RU2SU BIT(0) +#define FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW_SH 1 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF_SH 3 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_STBC BIT(6) +#define FWCMD_H2C_UL_FIXINFO_ULRUA_DOPPLER BIT(7) +#define FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA_SH 8 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM_SH 11 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM_MSK 0xf +#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGFIX BIT(16) +#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX_SH 17 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX_MSK 0x3ff +#define FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM_SH 27 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_MODE BIT(0) +#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID_SH 1 +#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID_MSK 0x3f +#define FWCMD_H2C_UL_FIXINFO_ULRUA_FIX_MODE BIT(7) +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D0_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D0_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D0_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D0_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D1_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D1_MSK 0xffffffff +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0_SH 0 +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0_MSK 0xff +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0_SH 8 +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1_SH 16 +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1_MSK 0xff +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1_SH 24 +#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1_MSK 0x3 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP BIT(0) +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI_SH 1 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI_MSK 0x7f +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID_SH 8 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID_MSK 0xff +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS_SH 16 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS_MSK 0xff +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE BIT(24) +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP BIT(25) +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN_SH 0 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN_MSK 0x7fff +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM BIT(16) +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS_SH 17 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS_MSK 0x7 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS_SH 20 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS_MSK 0xf +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL_SH 24 +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL_MSK 0x3f +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC BIT(30) +#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG BIT(31) +#define FWCMD_H2C_ADDR_CAM_VALID BIT(0) +#define FWCMD_H2C_ADDR_CAM_NET_TYPE_SH 1 +#define FWCMD_H2C_ADDR_CAM_NET_TYPE_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_BCN_HIT_COND_SH 3 +#define FWCMD_H2C_ADDR_CAM_BCN_HIT_COND_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_HIT_RULE_SH 5 +#define FWCMD_H2C_ADDR_CAM_HIT_RULE_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_BB_SEL BIT(7) +#define FWCMD_H2C_ADDR_CAM_ADDR_MASK_SH 8 +#define FWCMD_H2C_ADDR_CAM_ADDR_MASK_MSK 0x3f +#define FWCMD_H2C_ADDR_CAM_MASK_SEL_SH 14 +#define FWCMD_H2C_ADDR_CAM_MASK_SEL_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SMA_HASH_SH 16 +#define FWCMD_H2C_ADDR_CAM_SMA_HASH_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA_HASH_SH 24 +#define FWCMD_H2C_ADDR_CAM_TMA_HASH_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_BSSID_CAM_IDX_SH 0 +#define FWCMD_H2C_ADDR_CAM_BSSID_CAM_IDX_MSK 0x3f +#define FWCMD_H2C_ADDR_CAM_SMA0_SH 0 +#define FWCMD_H2C_ADDR_CAM_SMA0_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SMA1_SH 8 +#define FWCMD_H2C_ADDR_CAM_SMA1_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SMA2_SH 16 +#define FWCMD_H2C_ADDR_CAM_SMA2_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SMA3_SH 24 +#define FWCMD_H2C_ADDR_CAM_SMA3_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SMA4_SH 0 +#define FWCMD_H2C_ADDR_CAM_SMA4_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SMA5_SH 8 +#define FWCMD_H2C_ADDR_CAM_SMA5_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA0_SH 16 +#define FWCMD_H2C_ADDR_CAM_TMA0_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA1_SH 24 +#define FWCMD_H2C_ADDR_CAM_TMA1_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA2_SH 0 +#define FWCMD_H2C_ADDR_CAM_TMA2_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA3_SH 8 +#define FWCMD_H2C_ADDR_CAM_TMA3_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA4_SH 16 +#define FWCMD_H2C_ADDR_CAM_TMA4_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_TMA5_SH 24 +#define FWCMD_H2C_ADDR_CAM_TMA5_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_MACID_SH 0 +#define FWCMD_H2C_ADDR_CAM_MACID_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_PORT_INT_SH 8 +#define FWCMD_H2C_ADDR_CAM_PORT_INT_MSK 0x7 +#define FWCMD_H2C_ADDR_CAM_TSF_SYNC_SH 11 +#define FWCMD_H2C_ADDR_CAM_TSF_SYNC_MSK 0x7 +#define FWCMD_H2C_ADDR_CAM_TF_TRS BIT(14) +#define FWCMD_H2C_ADDR_CAM_LSIG_TXOP BIT(15) +#define FWCMD_H2C_ADDR_CAM_TGT_IND_SH 24 +#define FWCMD_H2C_ADDR_CAM_TGT_IND_MSK 0x7 +#define FWCMD_H2C_ADDR_CAM_FRM_TGT_IND_SH 27 +#define FWCMD_H2C_ADDR_CAM_FRM_TGT_IND_MSK 0x7 +#define FWCMD_H2C_ADDR_CAM_AID12_0_SH 0 +#define FWCMD_H2C_ADDR_CAM_AID12_0_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_AID12_1_SH 8 +#define FWCMD_H2C_ADDR_CAM_AID12_1_MSK 0xf +#define FWCMD_H2C_ADDR_CAM_WOL_PATTERN BIT(12) +#define FWCMD_H2C_ADDR_CAM_WOL_UC BIT(13) +#define FWCMD_H2C_ADDR_CAM_WOL_MAGIC BIT(14) +#define FWCMD_H2C_ADDR_CAM_WAPI BIT(15) +#define FWCMD_H2C_ADDR_CAM_SEC_ENT_MODE_SH 16 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT_MODE_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_KEYID_SH 18 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_KEYID_SH 20 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_KEYID_SH 22 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_KEYID_SH 24 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_KEYID_SH 26 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_KEYID_SH 28 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_KEYID_SH 30 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_KEYID_MSK 0x3 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT_VALID_SH 0 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT_VALID_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_SH 8 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_SH 16 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_SH 24 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_SH 0 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_SH 8 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_SH 16 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_MSK 0xff +#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_SH 24 +#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID_VALID BIT(0) +#define FWCMD_H2C_BSSID_CAM_BB_SEL BIT(1) +#define FWCMD_H2C_BSSID_CAM_BSS_COLOR_SH 8 +#define FWCMD_H2C_BSSID_CAM_BSS_COLOR_MSK 0x7f +#define FWCMD_H2C_BSSID_CAM_BSSID0_SH 16 +#define FWCMD_H2C_BSSID_CAM_BSSID0_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID1_SH 24 +#define FWCMD_H2C_BSSID_CAM_BSSID1_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID2_SH 0 +#define FWCMD_H2C_BSSID_CAM_BSSID2_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID3_SH 8 +#define FWCMD_H2C_BSSID_CAM_BSSID3_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID4_SH 16 +#define FWCMD_H2C_BSSID_CAM_BSSID4_MSK 0xff +#define FWCMD_H2C_BSSID_CAM_BSSID5_SH 24 +#define FWCMD_H2C_BSSID_CAM_BSSID5_MSK 0xff +#define FWCMD_H2C_SEC_CAM_SEC_TYPE_SH 0 +#define FWCMD_H2C_SEC_CAM_SEC_TYPE_MSK 0xf +#define FWCMD_H2C_SEC_CAM_EXT_KEY BIT(4) +#define FWCMD_H2C_SEC_CAM_SPP_MODE BIT(5) +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_TBLUD_SH 0 +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_TBLUD_MSK 0xffffffff +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D0_SH 0 +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D0_MSK 0xffffffff +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D1_SH 0 +#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D1_MSK 0xffffffff +#define FWCMD_H2C_FIXMODE_PARA_FORCE_SUMURU_EN BIT(0) +#define FWCMD_H2C_FIXMODE_PARA_FORCESU BIT(1) +#define FWCMD_H2C_FIXMODE_PARA_FORCEMU BIT(2) +#define FWCMD_H2C_FIXMODE_PARA_FORCERU BIT(3) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_SU_EN BIT(4) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_VHTMU_EN BIT(5) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_HEMU_EN BIT(6) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_HERU_EN BIT(7) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_UL_EN BIT(8) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_SU BIT(9) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_VHTMU BIT(10) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HEMU BIT(11) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HERU BIT(12) +#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_UL BIT(13) +#define FWCMD_H2C_FIXMODE_PARA_IS_DLRUHWGRP BIT(14) +#define FWCMD_H2C_FIXMODE_PARA_IS_ULRUHWGRP BIT(15) +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU_SH 16 +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU_SH 20 +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU_SH 24 +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU_SH 28 +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU_SH 0 +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU_SH 4 +#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU_SH 8 +#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE_SH 12 +#define FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE_MSK 0xf +#define FWCMD_H2C_FIXMODE_PARA_RUGRPID_SH 16 +#define FWCMD_H2C_FIXMODE_PARA_RUGRPID_MSK 0x1f +#define FWCMD_H2C_FIXMODE_PARA_MUGRPID_SH 21 +#define FWCMD_H2C_FIXMODE_PARA_MUGRPID_MSK 0x1f +#define FWCMD_H2C_FIXMODE_PARA_ULGRPID_SH 26 +#define FWCMD_H2C_FIXMODE_PARA_ULGRPID_MSK 0x1f +#define FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN_SH 0 +#define FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN_MSK 0x7ff +#define FWCMD_H2C_WRITE_OFLD_REQ_POLLING BIT(13) +#define FWCMD_H2C_WRITE_OFLD_REQ_MASK_EN BIT(14) +#define FWCMD_H2C_WRITE_OFLD_REQ_LS BIT(15) +#define FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID_SH 16 +#define FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID_MSK 0xff +#define FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM_SH 24 +#define FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM_MSK 0xff +#define FWCMD_H2C_WRITE_OFLD_REQ_OFFSET_SH 0 +#define FWCMD_H2C_WRITE_OFLD_REQ_OFFSET_MSK 0xffff +#define FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN_SH 0 +#define FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN_MSK 0x7ff +#define FWCMD_H2C_READ_OFLD_REQ_LS BIT(15) +#define FWCMD_H2C_READ_OFLD_REQ_OFLD_ID_SH 16 +#define FWCMD_H2C_READ_OFLD_REQ_OFLD_ID_MSK 0xff +#define FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM_SH 24 +#define FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM_MSK 0xff +#define FWCMD_H2C_READ_OFLD_REQ_OFFSET_SH 0 +#define FWCMD_H2C_READ_OFLD_REQ_OFFSET_MSK 0xffff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE_SH 0 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE_MSK 0xff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP_SH 0 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP_MSK 0xff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE_SH 8 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE_MSK 0xff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE_SH 24 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE_MSK 0xff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_REGISTER_ADDR_SH 0 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_REGISTER_ADDR_MSK 0xffffffff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H_SH 0 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H_MSK 0xffff +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L_SH 16 +#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L_MSK 0xffff +#define FWCMD_H2C_DCTRL_QOS_FIELD_H_SH 0 +#define FWCMD_H2C_DCTRL_QOS_FIELD_H_MSK 0xff +#define FWCMD_H2C_DCTRL_HW_EXSEQ_MACID_SH 8 +#define FWCMD_H2C_DCTRL_HW_EXSEQ_MACID_MSK 0x7f +#define FWCMD_H2C_DCTRL_QOS_FIELD_H_EN BIT(15) +#define FWCMD_H2C_DCTRL_AES_IV_L_SH 16 +#define FWCMD_H2C_DCTRL_AES_IV_L_MSK 0xffff +#define FWCMD_H2C_DCTRL_AES_IV_H_SH 0 +#define FWCMD_H2C_DCTRL_AES_IV_H_MSK 0xffffffff +#define FWCMD_H2C_DCTRL_SEQ0_SH 0 +#define FWCMD_H2C_DCTRL_SEQ0_MSK 0xfff +#define FWCMD_H2C_DCTRL_SEQ1_SH 12 +#define FWCMD_H2C_DCTRL_SEQ1_MSK 0xfff +#define FWCMD_H2C_DCTRL_AMSDU_MAX_LEN_SH 24 +#define FWCMD_H2C_DCTRL_AMSDU_MAX_LEN_MSK 0x7 +#define FWCMD_H2C_DCTRL_STA_AMSDU_EN BIT(27) +#define FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN BIT(28) +#define FWCMD_H2C_DCTRL_WITH_LLC BIT(29) +#define FWCMD_H2C_DCTRL_SEC_HW_ENC BIT(31) +#define FWCMD_H2C_DCTRL_SEQ2_SH 0 +#define FWCMD_H2C_DCTRL_SEQ2_MSK 0xfff +#define FWCMD_H2C_DCTRL_SEQ3_SH 12 +#define FWCMD_H2C_DCTRL_SEQ3_MSK 0xfff +#define FWCMD_H2C_DCTRL_SEC_CAM_IDX_SH 24 +#define FWCMD_H2C_DCTRL_SEC_CAM_IDX_MSK 0xff +#define FWCMD_H2C_CCTRL_DATARATE_SH 0 +#define FWCMD_H2C_CCTRL_DATARATE_MSK 0x1ff +#define FWCMD_H2C_CCTRL_FORCE_TXOP BIT(9) +#define FWCMD_H2C_CCTRL_DATA_BW_SH 10 +#define FWCMD_H2C_CCTRL_DATA_BW_MSK 0x3 +#define FWCMD_H2C_CCTRL_DATA_GI_LTF_SH 12 +#define FWCMD_H2C_CCTRL_DATA_GI_LTF_MSK 0x7 +#define FWCMD_H2C_CCTRL_DARF_TC_INDEX BIT(15) +#define FWCMD_H2C_CCTRL_ARFR_CTRL_SH 16 +#define FWCMD_H2C_CCTRL_ARFR_CTRL_MSK 0xf +#define FWCMD_H2C_CCTRL_ACQ_RPT_EN BIT(20) +#define FWCMD_H2C_CCTRL_MGQ_RPT_EN BIT(21) +#define FWCMD_H2C_CCTRL_ULQ_RPT_EN BIT(22) +#define FWCMD_H2C_CCTRL_TWTQ_RPT_EN BIT(23) +#define FWCMD_H2C_CCTRL_DISRTSFB BIT(25) +#define FWCMD_H2C_CCTRL_DISDATAFB BIT(26) +#define FWCMD_H2C_CCTRL_TRYRATE BIT(27) +#define FWCMD_H2C_CCTRL_AMPDU_DENSITY_SH 28 +#define FWCMD_H2C_CCTRL_AMPDU_DENSITY_MSK 0xf +#define FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE_SH 0 +#define FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE_MSK 0x1ff +#define FWCMD_H2C_CCTRL_AMPDU_TIME_SEL BIT(9) +#define FWCMD_H2C_CCTRL_AMPDU_LEN_SEL BIT(10) +#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL BIT(11) +#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SH 12 +#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_MSK 0xf +#define FWCMD_H2C_CCTRL_RTSRATE_SH 16 +#define FWCMD_H2C_CCTRL_RTSRATE_MSK 0x1ff +#define FWCMD_H2C_CCTRL_VCS_STBC BIT(27) +#define FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE_SH 28 +#define FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE_MSK 0xf +#define FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_SH 0 +#define FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_MSK 0x3f +#define FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL BIT(6) +#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL BIT(7) +#define FWCMD_H2C_CCTRL_RTS_EN BIT(8) +#define FWCMD_H2C_CCTRL_CTS2SELF_EN BIT(9) +#define FWCMD_H2C_CCTRL_CCA_RTS_SH 10 +#define FWCMD_H2C_CCTRL_CCA_RTS_MSK 0x3 +#define FWCMD_H2C_CCTRL_HW_RTS_EN BIT(12) +#define FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE_SH 13 +#define FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE_MSK 0x3 +#define FWCMD_H2C_CCTRL_PRELD_EN BIT(15) +#define FWCMD_H2C_CCTRL_AMPDU_MAX_LEN_SH 16 +#define FWCMD_H2C_CCTRL_AMPDU_MAX_LEN_MSK 0x7ff +#define FWCMD_H2C_CCTRL_UL_MU_DIS BIT(27) +#define FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_SH 28 +#define FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_MSK 0xf +#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_SH 0 +#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_MSK 0xff +#define FWCMD_H2C_CCTRL_BA_BMAP_SH 8 +#define FWCMD_H2C_CCTRL_BA_BMAP_MSK 0x3 +#define FWCMD_H2C_CCTRL_VO_LFTIME_SEL_SH 16 +#define FWCMD_H2C_CCTRL_VO_LFTIME_SEL_MSK 0x7 +#define FWCMD_H2C_CCTRL_VI_LFTIME_SEL_SH 19 +#define FWCMD_H2C_CCTRL_VI_LFTIME_SEL_MSK 0x7 +#define FWCMD_H2C_CCTRL_BE_LFTIME_SEL_SH 22 +#define FWCMD_H2C_CCTRL_BE_LFTIME_SEL_MSK 0x7 +#define FWCMD_H2C_CCTRL_BK_LFTIME_SEL_SH 25 +#define FWCMD_H2C_CCTRL_BK_LFTIME_SEL_MSK 0x7 +#define FWCMD_H2C_CCTRL_SECTYPE_SH 28 +#define FWCMD_H2C_CCTRL_SECTYPE_MSK 0xf +#define FWCMD_H2C_CCTRL_MULTI_PORT_ID_SH 0 +#define FWCMD_H2C_CCTRL_MULTI_PORT_ID_MSK 0x7 +#define FWCMD_H2C_CCTRL_BMC BIT(3) +#define FWCMD_H2C_CCTRL_MBSSID_SH 4 +#define FWCMD_H2C_CCTRL_MBSSID_MSK 0xf +#define FWCMD_H2C_CCTRL_NAVUSEHDR BIT(8) +#define FWCMD_H2C_CCTRL_TXPWR_MODE_SH 9 +#define FWCMD_H2C_CCTRL_TXPWR_MODE_MSK 0x7 +#define FWCMD_H2C_CCTRL_DATA_DCM BIT(12) +#define FWCMD_H2C_CCTRL_DATA_ER BIT(13) +#define FWCMD_H2C_CCTRL_DATA_LDPC BIT(14) +#define FWCMD_H2C_CCTRL_DATA_STBC BIT(15) +#define FWCMD_H2C_CCTRL_A_CTRL_BQR BIT(16) +#define FWCMD_H2C_CCTRL_A_CTRL_UPH BIT(17) +#define FWCMD_H2C_CCTRL_A_CTRL_BSR BIT(18) +#define FWCMD_H2C_CCTRL_A_CTRL_CAS BIT(19) +#define FWCMD_H2C_CCTRL_DATA_BW_ER BIT(20) +#define FWCMD_H2C_CCTRL_LSIG_TXOP_EN BIT(21) +#define FWCMD_H2C_CCTRL_CTRL_CNT_VLD BIT(27) +#define FWCMD_H2C_CCTRL_CTRL_CNT_SH 28 +#define FWCMD_H2C_CCTRL_CTRL_CNT_MSK 0xf +#define FWCMD_H2C_CCTRL_RESP_REF_RATE_SH 0 +#define FWCMD_H2C_CCTRL_RESP_REF_RATE_MSK 0x1ff +#define FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT BIT(12) +#define FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT BIT(13) +#define FWCMD_H2C_CCTRL_NTX_PATH_EN_SH 16 +#define FWCMD_H2C_CCTRL_NTX_PATH_EN_MSK 0xf +#define FWCMD_H2C_CCTRL_PATH_MAP_A_SH 20 +#define FWCMD_H2C_CCTRL_PATH_MAP_A_MSK 0x3 +#define FWCMD_H2C_CCTRL_PATH_MAP_B_SH 22 +#define FWCMD_H2C_CCTRL_PATH_MAP_B_MSK 0x3 +#define FWCMD_H2C_CCTRL_PATH_MAP_C_SH 24 +#define FWCMD_H2C_CCTRL_PATH_MAP_C_MSK 0x3 +#define FWCMD_H2C_CCTRL_PATH_MAP_D_SH 26 +#define FWCMD_H2C_CCTRL_PATH_MAP_D_MSK 0x3 +#define FWCMD_H2C_CCTRL_ANTSEL_A BIT(28) +#define FWCMD_H2C_CCTRL_ANTSEL_B BIT(29) +#define FWCMD_H2C_CCTRL_ANTSEL_C BIT(30) +#define FWCMD_H2C_CCTRL_ANTSEL_D BIT(31) +#define FWCMD_H2C_CCTRL_ADDR_CAM_INDEX_SH 0 +#define FWCMD_H2C_CCTRL_ADDR_CAM_INDEX_MSK 0xff +#define FWCMD_H2C_CCTRL_PAID_SH 8 +#define FWCMD_H2C_CCTRL_PAID_MSK 0x1ff +#define FWCMD_H2C_CCTRL_ULDL BIT(17) +#define FWCMD_H2C_CCTRL_DOPPLER_CTRL_SH 18 +#define FWCMD_H2C_CCTRL_DOPPLER_CTRL_MSK 0x3 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING_SH 20 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING_MSK 0x3 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40_SH 22 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40_MSK 0x3 +#define FWCMD_H2C_CCTRL_TXPWR_TOLERENCE_SH 24 +#define FWCMD_H2C_CCTRL_TXPWR_TOLERENCE_MSK 0x3f +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80_SH 30 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80_MSK 0x3 +#define FWCMD_H2C_CCTRL_NC_SH 0 +#define FWCMD_H2C_CCTRL_NC_MSK 0x7 +#define FWCMD_H2C_CCTRL_NR_SH 3 +#define FWCMD_H2C_CCTRL_NR_MSK 0x7 +#define FWCMD_H2C_CCTRL_NG_SH 6 +#define FWCMD_H2C_CCTRL_NG_MSK 0x3 +#define FWCMD_H2C_CCTRL_CB_SH 8 +#define FWCMD_H2C_CCTRL_CB_MSK 0x3 +#define FWCMD_H2C_CCTRL_CS_SH 10 +#define FWCMD_H2C_CCTRL_CS_MSK 0x3 +#define FWCMD_H2C_CCTRL_CSI_TXBF_EN BIT(12) +#define FWCMD_H2C_CCTRL_CSI_STBC_EN BIT(13) +#define FWCMD_H2C_CCTRL_CSI_LDPC_EN BIT(14) +#define FWCMD_H2C_CCTRL_CSI_PARA_EN BIT(15) +#define FWCMD_H2C_CCTRL_CSI_FIX_RATE_SH 16 +#define FWCMD_H2C_CCTRL_CSI_FIX_RATE_MSK 0x1ff +#define FWCMD_H2C_CCTRL_CSI_GI_LTF_SH 25 +#define FWCMD_H2C_CCTRL_CSI_GI_LTF_MSK 0x7 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160_SH 28 +#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160_MSK 0x3 +#define FWCMD_H2C_CCTRL_CSI_BW_SH 30 +#define FWCMD_H2C_CCTRL_CSI_BW_MSK 0x3 +#define FWCMD_H2C_IE_CAM_INFO_TYPE_SH 0 +#define FWCMD_H2C_IE_CAM_INFO_TYPE_MSK 0xff +#define FWCMD_H2C_IE_CAM_INFO_DATA0_SH 8 +#define FWCMD_H2C_IE_CAM_INFO_DATA0_MSK 0xff +#define FWCMD_H2C_IE_CAM_INFO_DATA1_SH 16 +#define FWCMD_H2C_IE_CAM_INFO_DATA1_MSK 0xff +#define FWCMD_H2C_IE_CAM_INFO_DATA2_SH 24 +#define FWCMD_H2C_IE_CAM_INFO_DATA2_MSK 0xff +#define FWCMD_H2C_IE_CAM_INFO_DATA3_SH 0 +#define FWCMD_H2C_IE_CAM_INFO_DATA3_MSK 0xff +#define FWCMD_H2C_PLAT_AUTO_TEST_D0_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D0_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D1_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D1_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D2_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D2_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D3_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D3_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D4_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D4_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D5_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D5_MSK 0xffffffff +#define FWCMD_H2C_PLAT_AUTO_TEST_D6_SH 0 +#define FWCMD_H2C_PLAT_AUTO_TEST_D6_MSK 0xffffffff +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_FUNC_SH 0 +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_FUNC_MSK 0x7f +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_ACK BIT(7) +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TOTAL_LEN_SH 8 +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TOTAL_LEN_MSK 0xf +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_SEQ_NUM_SH 12 +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_SEQ_NUM_MSK 0xf +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN_SH 16 +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN_MSK 0xffff +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK_SH 0 +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK_MSK 0xffff +#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_BAND BIT(16) +#define FWCMD_H2C_CMD_OFLD_SRC_SH 0 +#define FWCMD_H2C_CMD_OFLD_SRC_MSK 0x3 +#define FWCMD_H2C_CMD_OFLD_TYPE_SH 2 +#define FWCMD_H2C_CMD_OFLD_TYPE_MSK 0x3 +#define FWCMD_H2C_CMD_OFLD_LC BIT(4) +#define FWCMD_H2C_CMD_OFLD_PATH_SH 5 +#define FWCMD_H2C_CMD_OFLD_PATH_MSK 0x3 +#define FWCMD_H2C_CMD_OFLD_CMD_NUM_SH 8 +#define FWCMD_H2C_CMD_OFLD_CMD_NUM_MSK 0x7f +#define FWCMD_H2C_CMD_OFLD_OFFSET_SH 16 +#define FWCMD_H2C_CMD_OFLD_OFFSET_MSK 0xffff +#define FWCMD_H2C_CMD_OFLD_ID_SH 0 +#define FWCMD_H2C_CMD_OFLD_ID_MSK 0xffff +#define FWCMD_H2C_CMD_OFLD_VALUE_SH 0 +#define FWCMD_H2C_CMD_OFLD_VALUE_MSK 0xffffffff +#define FWCMD_H2C_CMD_OFLD_MASK_SH 0 +#define FWCMD_H2C_CMD_OFLD_MASK_MSK 0xffffffff + +#define FWCMD_H2C_FW_STS_PARA_EN BIT(0) +#define FWCMD_H2C_FW_STS_PARA_INTVL_MS_SH 16 +#define FWCMD_H2C_FW_STS_PARA_INTVL_MS_MSK 0xffff + +// +//H2CPKT - CAT(OutSrc,Phydm) +// +#define H2C_HDR_CAT_SH 0 +#define H2C_HDR_CAT_MSK 0x3 +#define H2C_HDR_CLASS_SH 2 +#define H2C_HDR_CLASS_MSK 0x3f +#define H2C_HDR_FUNC_SH 8 +#define H2C_HDR_FUNC_MSK 0xff +#define H2C_HDR_DEL_TYPE_SH 16 +#define H2C_HDR_DEL_TYPE_MSK 0xf +#define H2C_HDR_H2C_SEQ_SH 24 +#define H2C_HDR_H2C_SEQ_MSK 0xff +#define H2C_HDR_TOTAL_LEN_SH 0 +#define H2C_HDR_TOTAL_LEN_MSK 0x3fff +#define H2C_HDR_REC_ACK BIT(14) +#define H2C_HDR_DONE_ACK BIT(15) +#define H2C_HDR_SEQ_VALID BIT(16) +#define H2C_HDR_SEQ_SH 17 +#define H2C_HDR_SEQ_MSK 0x7 +#define H2C_HDR_SEQ_STOP BIT(20) +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_MACID_CFG_IS_DISRA BIT(0) +#define FWCMD_H2C_MACID_CFG_MODE_CTRL_SH 1 +#define FWCMD_H2C_MACID_CFG_MODE_CTRL_MSK 0x1f +#define FWCMD_H2C_MACID_CFG_BW_CAP_SH 6 +#define FWCMD_H2C_MACID_CFG_BW_CAP_MSK 0x3 +#define FWCMD_H2C_MACID_CFG_MACID_SH 8 +#define FWCMD_H2C_MACID_CFG_MACID_MSK 0xff +#define FWCMD_H2C_MACID_CFG_DCM_CAP BIT(16) +#define FWCMD_H2C_MACID_CFG_ER_CAP BIT(17) +#define FWCMD_H2C_MACID_CFG_INIT_RATE_LV_SH 18 +#define FWCMD_H2C_MACID_CFG_INIT_RATE_LV_MSK 0x3 +#define FWCMD_H2C_MACID_CFG_BW_NOUPDATE BIT(20) +#define FWCMD_H2C_MACID_CFG_EN_SGI BIT(21) +#define FWCMD_H2C_MACID_CFG_LDPC_CAP BIT(22) +#define FWCMD_H2C_MACID_CFG_STBC_CAP BIT(23) +#define FWCMD_H2C_MACID_CFG_SS_NUM_SH 24 +#define FWCMD_H2C_MACID_CFG_SS_NUM_MSK 0x7 +#define FWCMD_H2C_MACID_CFG_GI_LTF_SH 27 +#define FWCMD_H2C_MACID_CFG_GI_LTF_MSK 0x7 +#define FWCMD_H2C_MACID_CFG_RA_MASK_LOW_SH 0 +#define FWCMD_H2C_MACID_CFG_RA_MASK_LOW_MSK 0xffffffff +#define FWCMD_H2C_MACID_CFG_RA_MASK_HI_SH 0 +#define FWCMD_H2C_MACID_CFG_RA_MASK_HI_MSK 0xfffffff +#define FWCMD_H2C_RSSI_RA_CONFIG_IS_DISRA BIT(0) +#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_LOW_SH 0 +#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_LOW_MSK 0xffffffff +#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_HI_SH 0 +#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_HI_MSK 0xffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff + +// +//H2CPKT - CAT(OutSrc, RF) +// +#define H2C_HDR_CAT_SH 0 +#define H2C_HDR_CAT_MSK 0x3 +#define H2C_HDR_CLASS_SH 2 +#define H2C_HDR_CLASS_MSK 0x3f +#define H2C_HDR_FUNC_SH 8 +#define H2C_HDR_FUNC_MSK 0xff +#define H2C_HDR_DEL_TYPE_SH 16 +#define H2C_HDR_DEL_TYPE_MSK 0xf +#define H2C_HDR_H2C_SEQ_SH 24 +#define H2C_HDR_H2C_SEQ_MSK 0xff +#define H2C_HDR_TOTAL_LEN_SH 0 +#define H2C_HDR_TOTAL_LEN_MSK 0x3fff +#define H2C_HDR_REC_ACK BIT(14) +#define H2C_HDR_DONE_ACK BIT(15) +#define H2C_HDR_SEQ_VALID BIT(16) +#define H2C_HDR_SEQ_SH 17 +#define H2C_HDR_SEQ_MSK 0x7 +#define H2C_HDR_SEQ_STOP BIT(20) +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff + +// +//H2CPKT - CAT(OutSrc, BTC) +// +#define H2C_HDR_CAT_SH 0 +#define H2C_HDR_CAT_MSK 0x3 +#define H2C_HDR_CLASS_SH 2 +#define H2C_HDR_CLASS_MSK 0x3f +#define H2C_HDR_FUNC_SH 8 +#define H2C_HDR_FUNC_MSK 0xff +#define H2C_HDR_DEL_TYPE_SH 16 +#define H2C_HDR_DEL_TYPE_MSK 0xf +#define H2C_HDR_H2C_SEQ_SH 24 +#define H2C_HDR_H2C_SEQ_MSK 0xff +#define H2C_HDR_TOTAL_LEN_SH 0 +#define H2C_HDR_TOTAL_LEN_MSK 0x3fff +#define H2C_HDR_REC_ACK BIT(14) +#define H2C_HDR_DONE_ACK BIT(15) +#define H2C_HDR_SEQ_VALID BIT(16) +#define H2C_HDR_SEQ_SH 17 +#define H2C_HDR_SEQ_MSK 0x7 +#define H2C_HDR_SEQ_STOP BIT(20) +#define FWCMD_H2C_TDMA_EN BIT(0) +#define FWCMD_H2C_TDMA_PRO_PS BIT(1) +#define FWCMD_H2C_TDMA_NULL BIT(2) +#define FWCMD_H2C_TDMA_QOS_NULL BIT(3) +#define FWCMD_H2C_TDMA_WL_SLOT_SH 8 +#define FWCMD_H2C_TDMA_WL_SLOT_MSK 0xff + +// +//C2HPKT - CAT(TEST) +// +#define C2H_HDR_CAT_SH 0 +#define C2H_HDR_CAT_MSK 0x3 +#define C2H_HDR_CLASS_SH 2 +#define C2H_HDR_CLASS_MSK 0x3f +#define C2H_HDR_FUNC_SH 8 +#define C2H_HDR_FUNC_MSK 0xff +#define C2H_HDR_DEL_TYPE_SH 16 +#define C2H_HDR_DEL_TYPE_MSK 0xf +#define C2H_HDR_C2H_SEQ_SH 24 +#define C2H_HDR_C2H_SEQ_MSK 0xff +#define C2H_HDR_TOTAL_LEN_SH 0 +#define C2H_HDR_TOTAL_LEN_MSK 0x3fff +#define FWCMD_C2H_C2H_LB_PAYLOAD_SH 0 +#define FWCMD_C2H_C2H_LB_PAYLOAD_MSK 0xffffffff +#define FWCMD_C2H_TEST_PHY_RPT_PAYLOAD_SH 0 +#define FWCMD_C2H_TEST_PHY_RPT_PAYLOAD_MSK 0xffffffff +#define FWCMD_C2H_SPIC_PAYLOAD0_SH 0 +#define FWCMD_C2H_SPIC_PAYLOAD0_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD1_SH 8 +#define FWCMD_C2H_SPIC_PAYLOAD1_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD2_SH 16 +#define FWCMD_C2H_SPIC_PAYLOAD2_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD3_SH 24 +#define FWCMD_C2H_SPIC_PAYLOAD3_MSK 0x1ff +#define FWCMD_C2H_SPIC_PAYLOAD4_SH 0 +#define FWCMD_C2H_SPIC_PAYLOAD4_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD5_SH 8 +#define FWCMD_C2H_SPIC_PAYLOAD5_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD6_SH 16 +#define FWCMD_C2H_SPIC_PAYLOAD6_MSK 0xff +#define FWCMD_C2H_SPIC_PAYLOAD7_SH 24 +#define FWCMD_C2H_SPIC_PAYLOAD7_MSK 0x1ff +#define FWCMD_C2H_SPIC2_PAYLOAD0_SH 0 +#define FWCMD_C2H_SPIC2_PAYLOAD0_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD1_SH 8 +#define FWCMD_C2H_SPIC2_PAYLOAD1_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD2_SH 16 +#define FWCMD_C2H_SPIC2_PAYLOAD2_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD3_SH 24 +#define FWCMD_C2H_SPIC2_PAYLOAD3_MSK 0x1ff +#define FWCMD_C2H_SPIC2_PAYLOAD4_SH 0 +#define FWCMD_C2H_SPIC2_PAYLOAD4_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD5_SH 8 +#define FWCMD_C2H_SPIC2_PAYLOAD5_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD6_SH 16 +#define FWCMD_C2H_SPIC2_PAYLOAD6_MSK 0xff +#define FWCMD_C2H_SPIC2_PAYLOAD7_SH 24 +#define FWCMD_C2H_SPIC2_PAYLOAD7_MSK 0x1ff +#define FWCMD_C2H_LPS_ONOFF_TEST_TYPE_SH 0 +#define FWCMD_C2H_LPS_ONOFF_TEST_TYPE_MSK 0xffffffff +#define FWCMD_C2H_LPS_ONOFF_TEST_RESULT_SH 0 +#define FWCMD_C2H_LPS_ONOFF_TEST_RESULT_MSK 0xffffffff + +// +//C2HPKT - CAT(MAC) +// +#define C2H_HDR_CAT_SH 0 +#define C2H_HDR_CAT_MSK 0x3 +#define C2H_HDR_CLASS_SH 2 +#define C2H_HDR_CLASS_MSK 0x3f +#define C2H_HDR_FUNC_SH 8 +#define C2H_HDR_FUNC_MSK 0xff +#define C2H_HDR_DEL_TYPE_SH 16 +#define C2H_HDR_DEL_TYPE_MSK 0xf +#define C2H_HDR_C2H_SEQ_SH 24 +#define C2H_HDR_C2H_SEQ_MSK 0xff +#define C2H_HDR_TOTAL_LEN_SH 0 +#define C2H_HDR_TOTAL_LEN_MSK 0x3fff +#define FWCMD_C2H_REC_ACK_CAT_SH 0 +#define FWCMD_C2H_REC_ACK_CAT_MSK 0x3 +#define FWCMD_C2H_REC_ACK_CLASS_SH 2 +#define FWCMD_C2H_REC_ACK_CLASS_MSK 0x3f +#define FWCMD_C2H_REC_ACK_FUNC_SH 8 +#define FWCMD_C2H_REC_ACK_FUNC_MSK 0xff +#define FWCMD_C2H_REC_ACK_H2C_SEQ_SH 16 +#define FWCMD_C2H_REC_ACK_H2C_SEQ_MSK 0xff +#define FWCMD_C2H_DONE_ACK_CAT_SH 0 +#define FWCMD_C2H_DONE_ACK_CAT_MSK 0x3 +#define FWCMD_C2H_DONE_ACK_CLASS_SH 2 +#define FWCMD_C2H_DONE_ACK_CLASS_MSK 0x3f +#define FWCMD_C2H_DONE_ACK_FUNC_SH 8 +#define FWCMD_C2H_DONE_ACK_FUNC_MSK 0xff +#define FWCMD_C2H_DONE_ACK_H2C_RETURN_SH 16 +#define FWCMD_C2H_DONE_ACK_H2C_RETURN_MSK 0xff +#define FWCMD_C2H_DONE_ACK_H2C_SEQ_SH 24 +#define FWCMD_C2H_DONE_ACK_H2C_SEQ_MSK 0xff +#define FWCMD_C2H_C2H_LOG_LOG_MSG_SH 0 +#define FWCMD_C2H_C2H_LOG_LOG_MSG_MSK 0xffffffff +#define FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX_SH 0 +#define FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX_MSK 0x7f +#define FWCMD_C2H_BCN_CNT_BAND_IDX BIT(7) +#define FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT_SH 8 +#define FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT_SH 12 +#define FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT_SH 16 +#define FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT_SH 20 +#define FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT_SH 24 +#define FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT_SH 28 +#define FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT_SH 0 +#define FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT_SH 4 +#define FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT_SH 8 +#define FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT_SH 12 +#define FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CNT_OK_CNT_SH 16 +#define FWCMD_C2H_BCN_CNT_OK_CNT_MSK 0xf +#define FWCMD_C2H_BCN_CSAZERO_PORT_MBSSID_IDX_SH 0 +#define FWCMD_C2H_BCN_CSAZERO_PORT_MBSSID_IDX_MSK 0x7f +#define FWCMD_C2H_BCN_CSAZERO_BAND_IDX BIT(7) +#define FWCMD_C2H_EFUSE_DUMP_UUID0_SH 16 +#define FWCMD_C2H_EFUSE_DUMP_UUID0_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_UUID2_SH 24 +#define FWCMD_C2H_EFUSE_DUMP_UUID2_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_REMARK_SH 24 +#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_REMARK_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_SH 28 +#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_HCI_TYPE_SH 0 +#define FWCMD_C2H_EFUSE_DUMP_HCI_TYPE_MSK 0xf +#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_SH 8 +#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_SH 12 +#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_SH 16 +#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_SH 20 +#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN0_SH 24 +#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN0_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN1_SH 0 +#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN1_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_REMARK_80211_SH 8 +#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_REMARK_80211_MSK 0x3 +#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_80211_SH 10 +#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_80211_MSK 0x3 +#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_REMARK_SH 12 +#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_REMARK_MSK 0x3 +#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_SH 14 +#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_MSK 0x3 +#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_REMARK_SH 16 +#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_REMARK_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_REMARK_SH 20 +#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_REMARK_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_REMARK_SH 24 +#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_REMARK_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_REMARK_SH 28 +#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_REMARK_MSK 0x7 +#define FWCMD_C2H_EFUSE_DUMP_WL_FUNCTION_SUPPORT_SH 0 +#define FWCMD_C2H_EFUSE_DUMP_WL_FUNCTION_SUPPORT_MSK 0xf +#define FWCMD_C2H_EFUSE_DUMP_HW_SPECIAL_TYPE_SH 4 +#define FWCMD_C2H_EFUSE_DUMP_HW_SPECIAL_TYPE_MSK 0xf +#define FWCMD_C2H_EFUSE_DUMP_UUID3_SH 0 +#define FWCMD_C2H_EFUSE_DUMP_UUID3_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_UUID1_SH 8 +#define FWCMD_C2H_EFUSE_DUMP_UUID1_MSK 0xff +#define FWCMD_C2H_EFUSE_DUMP_PFID_SH 16 +#define FWCMD_C2H_EFUSE_DUMP_PFID_MSK 0xff +#define FWCMD_C2H_READ_RSP_VALUE_LEN_SH 0 +#define FWCMD_C2H_READ_RSP_VALUE_LEN_MSK 0x7ff +#define FWCMD_C2H_READ_RSP_LS BIT(15) +#define FWCMD_C2H_READ_RSP_OFLD_ID_SH 16 +#define FWCMD_C2H_READ_RSP_OFLD_ID_MSK 0xff +#define FWCMD_C2H_READ_RSP_ENTRY_NUM_SH 24 +#define FWCMD_C2H_READ_RSP_ENTRY_NUM_MSK 0xff +#define FWCMD_C2H_READ_RSP_OFFSET_SH 0 +#define FWCMD_C2H_READ_RSP_OFFSET_MSK 0xffff +#define FWCMD_C2H_READ_RSP_START_SH 0 +#define FWCMD_C2H_READ_RSP_START_MSK 0xffffffff +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_ID_SH 0 +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_ID_MSK 0xff +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_OP_SH 8 +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_OP_MSK 0x7 +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH_SH 16 +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH_MSK 0xffff +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_CONTENT_SH 0 +#define FWCMD_C2H_PKT_OFLD_RSP_PKT_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_1_SH 0 +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_1_MSK 0xffffffff +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_2_SH 0 +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_2_MSK 0xffffffff +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_3_SH 0 +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_3_MSK 0xffffffff +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_4_SH 0 +#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_4_MSK 0xffffffff +#define FWCMD_C2H_FW_GETPKT_RPT_MACID_SH 0 +#define FWCMD_C2H_FW_GETPKT_RPT_MACID_MSK 0xff +#define FWCMD_C2H_FW_GETPKT_RPT_PKT_TYPE_SH 8 +#define FWCMD_C2H_FW_GETPKT_RPT_PKT_TYPE_MSK 0xf +#define FWCMD_C2H_TSF32_TOGL_RPT_BAND BIT(0) +#define FWCMD_C2H_TSF32_TOGL_RPT_PORT_SH 1 +#define FWCMD_C2H_TSF32_TOGL_RPT_PORT_MSK 0x7 +#define FWCMD_C2H_TSF32_TOGL_RPT_STATUS_SH 4 +#define FWCMD_C2H_TSF32_TOGL_RPT_STATUS_MSK 0xfff +#define FWCMD_C2H_TSF32_TOGL_RPT_EARLY_SH 16 +#define FWCMD_C2H_TSF32_TOGL_RPT_EARLY_MSK 0xffff +#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_L_SH 0 +#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_L_MSK 0xffffffff +#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_H_SH 0 +#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_H_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_RPT_MODE_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_RPT_MODE_MSK 0x7 +#define FWCMD_C2H_USR_TX_RPT_INFO_MACID_SH 8 +#define FWCMD_C2H_USR_TX_RPT_INFO_MACID_MSK 0xff +#define FWCMD_C2H_USR_TX_RPT_INFO_AC_SH 16 +#define FWCMD_C2H_USR_TX_RPT_INFO_AC_MSK 0x3 +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BE_1K_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BE_1K_MSK 0xffff +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BK_1K_SH 16 +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BK_1K_MSK 0xffff +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VI_1K_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VI_1K_MSK 0xffff +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VO_1K_SH 16 +#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VO_1K_MSK 0xffff +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_IN_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_IN_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_OUT_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_OUT_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_LAST_OUT_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_LAST_OUT_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BE_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BE_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BK_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BK_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VI_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VI_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VO_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VO_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BE_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BE_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BK_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BK_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VI_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VI_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VO_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VO_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_RX_CLEAR_US_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_RX_CLEAR_US_MSK 0xffffffff +#define FWCMD_C2H_USR_TX_RPT_INFO_BUSY_US_SH 0 +#define FWCMD_C2H_USR_TX_RPT_INFO_BUSY_US_MSK 0xffffffff +#define FWCMD_C2H_CMD_OFLD_RSP_RESULT BIT(0) +#define FWCMD_C2H_CMD_OFLD_RSP_CMD_NUM_SH 8 +#define FWCMD_C2H_CMD_OFLD_RSP_CMD_NUM_MSK 0xff +#define FWCMD_C2H_CMD_OFLD_RSP_OFFSET_SH 0 +#define FWCMD_C2H_CMD_OFLD_RSP_OFFSET_MSK 0xffffffff +#define FWCMD_C2H_CMD_OFLD_RSP_EXP_VAL_SH 0 +#define FWCMD_C2H_CMD_OFLD_RSP_EXP_VAL_MSK 0xffffffff +#define FWCMD_C2H_CMD_OFLD_RSP_R_VAL_SH 0 +#define FWCMD_C2H_CMD_OFLD_RSP_R_VAL_MSK 0xffffffff +#define FWCMD_C2H_SCANOFLD_RSP_CENTRAL_CH_SH 0 +#define FWCMD_C2H_SCANOFLD_RSP_CENTRAL_CH_MSK 0xff +#define FWCMD_C2H_SCANOFLD_RSP_SCANNED_CH_SH 8 +#define FWCMD_C2H_SCANOFLD_RSP_SCANNED_CH_MSK 0xff +#define FWCMD_C2H_SCANOFLD_RSP_NOTIFY_REASON_SH 16 +#define FWCMD_C2H_SCANOFLD_RSP_NOTIFY_REASON_MSK 0xf +#define FWCMD_C2H_SCANOFLD_RSP_STATUS_SH 20 +#define FWCMD_C2H_SCANOFLD_RSP_STATUS_MSK 0xf +#define FWCMD_C2H_SCANOFLD_RSP_TSF_LOW_SH 0 +#define FWCMD_C2H_SCANOFLD_RSP_TSF_LOW_MSK 0xffffffff +#define FWCMD_C2H_SCANOFLD_RSP_TSF_HIGH_SH 0 +#define FWCMD_C2H_SCANOFLD_RSP_TSF_HIGH_MSK 0xffffffff +#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_LOW_SH 0 +#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_LOW_MSK 0xffffffff +#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_HIGH_SH 0 +#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_HIGH_MSK 0xffffffff +#define FWCMD_C2H_CH_SWITCH_RPT_RESULT_SH 0 +#define FWCMD_C2H_CH_SWITCH_RPT_RESULT_MSK 0x7 +#define FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR_SH 0 +#define FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR_MSK 0x7 +#define FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE_SH 0 +#define FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE_MSK 0xf +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID0_SH 8 +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID0_MSK 0xff +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID1_SH 16 +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID1_MSK 0xff +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID2_SH 24 +#define FWCMD_C2H_WAIT_ANNOUNCE_MACID2_MSK 0xff +#define FWCMD_C2H_AOAC_REPORT_AOAC_REPORT_SH 0 +#define FWCMD_C2H_AOAC_REPORT_AOAC_REPORT_MSK 0xffffffff +#define FWCMD_C2H_READ_WOW_CAM_VALUE_LEN_SH 0 +#define FWCMD_C2H_READ_WOW_CAM_VALUE_LEN_MSK 0x7ff +#define FWCMD_C2H_READ_WOW_CAM_IDX_SH 24 +#define FWCMD_C2H_READ_WOW_CAM_IDX_MSK 0xff +#define FWCMD_C2H_READ_WOW_CAM_WOW_CAM_SH 0 +#define FWCMD_C2H_READ_WOW_CAM_WOW_CAM_MSK 0xffffffff +#define FWCMD_C2H_MCC_RCV_ACK_GROUP_SH 0 +#define FWCMD_C2H_MCC_RCV_ACK_GROUP_MSK 0x3 +#define FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC_SH 8 +#define FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC_MSK 0xff +#define FWCMD_C2H_MCC_REQ_ACK_GROUP_SH 0 +#define FWCMD_C2H_MCC_REQ_ACK_GROUP_MSK 0x3 +#define FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN_SH 2 +#define FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN_MSK 0x3f +#define FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC_SH 8 +#define FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC_MSK 0xff +#define FWCMD_C2H_MCC_TSF_RPT_MACID_X_SH 0 +#define FWCMD_C2H_MCC_TSF_RPT_MACID_X_MSK 0xff +#define FWCMD_C2H_MCC_TSF_RPT_MACID_Y_SH 8 +#define FWCMD_C2H_MCC_TSF_RPT_MACID_Y_MSK 0xff +#define FWCMD_C2H_MCC_TSF_RPT_GROUP_SH 16 +#define FWCMD_C2H_MCC_TSF_RPT_GROUP_MSK 0x3 +#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_X_SH 0 +#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_X_MSK 0xffffffff +#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_X_SH 0 +#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_X_MSK 0xffffffff +#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_Y_SH 0 +#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_Y_MSK 0xffffffff +#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_Y_SH 0 +#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_Y_MSK 0xffffffff +#define FWCMD_C2H_MCC_STATUS_RPT_STATUS_SH 0 +#define FWCMD_C2H_MCC_STATUS_RPT_STATUS_MSK 0x3f +#define FWCMD_C2H_MCC_STATUS_RPT_GROUP_SH 6 +#define FWCMD_C2H_MCC_STATUS_RPT_GROUP_MSK 0x3 +#define FWCMD_C2H_MCC_STATUS_RPT_MACID_SH 8 +#define FWCMD_C2H_MCC_STATUS_RPT_MACID_MSK 0xff +#define FWCMD_C2H_MCC_STATUS_RPT_TSF_LOW_SH 0 +#define FWCMD_C2H_MCC_STATUS_RPT_TSF_LOW_MSK 0xffffffff +#define FWCMD_C2H_MCC_STATUS_RPT_TSF_HIGH_SH 0 +#define FWCMD_C2H_MCC_STATUS_RPT_TSF_HIGH_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_WRITE_ADDR_SH 0 +#define FWCMD_C2H_PLAT_FLASH_WRITE_ADDR_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_WRITE_LENGTH_SH 0 +#define FWCMD_C2H_PLAT_FLASH_WRITE_LENGTH_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_ERASE_ADDR_SH 0 +#define FWCMD_C2H_PLAT_FLASH_ERASE_ADDR_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_ERASE_LENGTH_SH 0 +#define FWCMD_C2H_PLAT_FLASH_ERASE_LENGTH_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_READ_ADDR_SH 0 +#define FWCMD_C2H_PLAT_FLASH_READ_ADDR_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_READ_LENGTH_SH 0 +#define FWCMD_C2H_PLAT_FLASH_READ_LENGTH_MSK 0xffffffff +#define FWCMD_C2H_PLAT_FLASH_READ_PAYLOAD_SH 0 +#define FWCMD_C2H_PLAT_FLASH_READ_PAYLOAD_MSK 0xffffffff +#define FWCMD_C2H_FCS_RPT_STATUS_SH 0 +#define FWCMD_C2H_FCS_RPT_STATUS_MSK 0xffffffff +#define FWCMD_C2H_WPS_RPT_STATE_SH 0 +#define FWCMD_C2H_WPS_RPT_STATE_MSK 0xff +#define FWCMD_C2H_CCXRPT_DWORD0_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD0_MSK 0xffffffff +#define FWCMD_C2H_CCXRPT_DWORD1_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD1_MSK 0xffffffff +#define FWCMD_C2H_CCXRPT_DWORD2_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD2_MSK 0xffffffff +#define FWCMD_C2H_CCXRPT_DWORD3_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD3_MSK 0xffffffff +#define FWCMD_C2H_CCXRPT_DWORD4_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD4_MSK 0xffffffff +#define FWCMD_C2H_CCXRPT_DWORD5_SH 0 +#define FWCMD_C2H_CCXRPT_DWORD5_MSK 0xffffffff +#define FWCMD_C2H_PORT_INIT_STAT_BAND BIT(0) +#define FWCMD_C2H_PORT_INIT_STAT_PORT_SH 1 +#define FWCMD_C2H_PORT_INIT_STAT_PORT_MSK 0x7 +#define FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX_SH 8 +#define FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX_MSK 0xff +#define FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE_SH 16 +#define FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE_MSK 0xff +#define FWCMD_C2H_PORT_INIT_STAT_STEP_SH 24 +#define FWCMD_C2H_PORT_INIT_STAT_STEP_MSK 0xff +#define FWCMD_C2H_PORT_INIT_STAT_CFG_VAL_SH 0 +#define FWCMD_C2H_PORT_INIT_STAT_CFG_VAL_MSK 0xffffffff +#define FWCMD_C2H_PORT_INIT_STAT_RET_SH 0 +#define FWCMD_C2H_PORT_INIT_STAT_RET_MSK 0xffffffff +#define FWCMD_C2H_PORT_CFG_STAT_BAND BIT(0) +#define FWCMD_C2H_PORT_CFG_STAT_PORT_SH 1 +#define FWCMD_C2H_PORT_CFG_STAT_PORT_MSK 0x7 +#define FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX_SH 8 +#define FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX_MSK 0xff +#define FWCMD_C2H_PORT_CFG_STAT_TYPE_SH 16 +#define FWCMD_C2H_PORT_CFG_STAT_TYPE_MSK 0xff +#define FWCMD_C2H_PORT_CFG_STAT_VAL_SH 0 +#define FWCMD_C2H_PORT_CFG_STAT_VAL_MSK 0xffffffff +#define FWCMD_C2H_PORT_CFG_STAT_RET_SH 0 +#define FWCMD_C2H_PORT_CFG_STAT_RET_MSK 0xffffffff +#define FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM_SH 0 +#define FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER_SH 8 +#define FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_MACID_SH 0 +#define FWCMD_C2H_OFDMA_STS_TFSTS_MACID_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE_SH 8 +#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER_SH 16 +#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI_SH 24 +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER_SH 0 +#define FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH_SH 8 +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER_SH 16 +#define FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM_SH 24 +#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_TFSTS_TF_NUM_SH 0 +#define FWCMD_C2H_OFDMA_STS_TFSTS_TF_NUM_MSK 0xffffffff + +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_USER_NUM_SH 0 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_USER_NUM_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_RU_RATIO_SH 8 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_RU_RATIO_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_RU_FAIL_RATIO_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_RU_FAIL_RATIO_SH 16 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_FAIL_RATIO_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_FAIL_RATIO_SH 24 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_MACID_SH 0 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_MACID_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_RU_RATIO_SH 8 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_RU_RATIO_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_FAIL_SH 16 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_FAIL_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_FAIL_SH 24 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_FAIL_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_AVG_AGG_SH 0 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_AVG_AGG_MSK 0xff +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_RATE_SH 8 +#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_RATE_MSK 0xff + +// +//C2HPKT - CAT(OutSrc, Phydm) +// +#define C2H_HDR_CAT_SH 0 +#define C2H_HDR_CAT_MSK 0x3 +#define C2H_HDR_CLASS_SH 2 +#define C2H_HDR_CLASS_MSK 0x3f +#define C2H_HDR_FUNC_SH 8 +#define C2H_HDR_FUNC_MSK 0xff +#define C2H_HDR_DEL_TYPE_SH 16 +#define C2H_HDR_DEL_TYPE_MSK 0xf +#define C2H_HDR_C2H_SEQ_SH 24 +#define C2H_HDR_C2H_SEQ_MSK 0xff +#define C2H_HDR_TOTAL_LEN_SH 0 +#define C2H_HDR_TOTAL_LEN_MSK 0x3fff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff + +// +//C2HPKT - CAT(OutSrc, RF) +// +#define C2H_HDR_CAT_SH 0 +#define C2H_HDR_CAT_MSK 0x3 +#define C2H_HDR_CLASS_SH 2 +#define C2H_HDR_CLASS_MSK 0x3f +#define C2H_HDR_FUNC_SH 8 +#define C2H_HDR_FUNC_MSK 0xff +#define C2H_HDR_DEL_TYPE_SH 16 +#define C2H_HDR_DEL_TYPE_MSK 0xf +#define C2H_HDR_C2H_SEQ_SH 24 +#define C2H_HDR_C2H_SEQ_MSK 0xff +#define C2H_HDR_TOTAL_LEN_SH 0 +#define C2H_HDR_TOTAL_LEN_MSK 0x3fff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff + +// +//C2HPKT - CAT(OutSrc, BTC) +// +#define C2H_HDR_CAT_SH 0 +#define C2H_HDR_CAT_MSK 0x3 +#define C2H_HDR_CLASS_SH 2 +#define C2H_HDR_CLASS_MSK 0x3f +#define C2H_HDR_FUNC_SH 8 +#define C2H_HDR_FUNC_MSK 0xff +#define C2H_HDR_DEL_TYPE_SH 16 +#define C2H_HDR_DEL_TYPE_MSK 0xf +#define C2H_HDR_C2H_SEQ_SH 24 +#define C2H_HDR_C2H_SEQ_MSK 0xff +#define C2H_HDR_TOTAL_LEN_SH 0 +#define C2H_HDR_TOTAL_LEN_MSK 0x3fff +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0 +#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff + +// struct for halmac// +struct fwcmd_hdr { + u32 hdr0; + u32 hdr1; +}; + +// +//H2CREG +// +struct fwcmd_h2creg_hdr { + u32 dword0; +}; + +struct fwcmd_h2creg { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_h2creg_lb { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_cnsl_cmd { + u32 dword0; +}; + +struct fwcmd_fwerr { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_hidden_get { + u32 dword0; +}; + +struct fwcmd_getpkt_inform { + u32 dword0; +}; + +struct fwcmd_sch_tx_en { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_wow_trx_stop { + u32 dword0; +}; + + +// +//C2HREG +// +struct fwcmd_c2hreg_hdr { + u32 dword0; +}; + +struct fwcmd_c2hreg { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_c2hreg_lb { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_err_rpt { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_err_msg { + u32 dword0; +}; + +struct fwcmd_efuse_hidden { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_tx_pause_rpt { + u32 dword0; +}; + +struct fwcmd_aoac_rpt_1 { + u32 dword0; +}; + +struct fwcmd_aoac_rpt_2 { + u32 dword0; +}; + +struct fwcmd_aoac_rpt_3 { + u32 dword0; +}; + +struct fwcmd_io_ofld_result { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + + +// +//H2CPKT - CAT(TEST) +// +struct fwcmd_h2c_lb { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_plat_spic_test { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_plat_fl_write { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_plat_fl_erase { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_pl_flash_read { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_long_run { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_lps_test { + u32 dword0; +}; + +struct fwcmd_lps_onoff_test { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_fw_status { + u32 dword0; +}; + + +// +//H2CPKT - CAT(MAC) +// +struct fwcmd_log_cfg { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_general_pkt { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_c2h_rpt_cfg { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_wlan_dump_cmd { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_fw_dbgreg_cfg { + u32 dword0; +}; + +struct fwcmd_keep_alive { + u32 dword0; +}; + +struct fwcmd_disconnect_detect { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_wow_global { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_gtk_ofld { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_arp_ofld { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_ndp_ofld { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_realwow { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_nlo { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_wakeup_ctrl { + u32 dword0; +}; + +struct fwcmd_negative_pattern { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_dev2hst_gpio { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; +}; + +struct fwcmd_uphy_ctrl { + u32 dword0; +}; + +struct fwcmd_wow_cam_upd { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_aoac_report_req { + u32 dword0; +}; + +struct fwcmd_wow_stop_fw_trx { + u32 dword0; +}; + +struct fwcmd_lps_parm { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_p2p_act { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; +}; + +struct fwcmd_p2p_macid_ctrl { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_ips_cfg { + u32 dword0; +}; + +struct fwcmd_ps_advance_parm { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_fwhdr_dl { + u32 dword0; +}; + +struct fwcmd_fwhdr_redl { + u32 dword0; +}; + +struct fwcmd_twt_announce_upd { + u32 dword0; +}; + +struct fwcmd_twtinfo_upd { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_twt_stansp_upd { + u32 dword0; +}; + +struct fwcmd_tblud { + u32 dword0; +}; + +struct fwcmd_dctlinfo_ud { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; +}; + +struct fwcmd_cctlinfo_ud { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; + u32 dword16; +}; + +struct fwcmd_shcut_update { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; +}; + +struct fwcmd_bcn_upd { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_ss_ulsta_upd { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_f2pdbg_set { + u32 dword0; +}; + +struct fwcmd_wlaninfo_get { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_addrcam_info { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; +}; + +struct fwcmd_joininfo { + u32 dword0; +}; + +struct fwcmd_dl_grp_upd { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_ul_grp_upd { + u32 dword0; +}; + +struct fwcmd_mu_sta_upd { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_fwrole_maintain { + u32 dword0; +}; + +struct fwcmd_dump_efuse { + u32 dword0; +}; + +struct fwcmd_packet_ofld { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_read_ofld { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_write_ofld { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_conf_ofld { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_sys_init { + u32 dword0; +}; + +struct fwcmd_trx_init { + u32 dword0; +}; + +struct fwcmd_intf_init { + u32 dword0; +}; + +struct fwcmd_macid_pause { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +struct fwcmd_rx_fwd { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; +}; + +struct fwcmd_en_mac_hdr_conv { + u32 dword0; +}; + +struct fwcmd_set_hwseq_reg { + u32 dword0; +}; + +struct fwcmd_hwamsdu_reg { + u32 dword0; +}; + +struct fwcmd_amsdu_cut_reg { + u32 dword0; +}; + +struct fwcmd_tcpip_chksum_offload_reg { + u32 dword0; +}; + +struct fwcmd_usr_edca { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_tsf32_togl { + u32 dword0; +}; + +struct fwcmd_cmd_ofld_reg { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_usr_tx_rpt { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_cmd_ofld_pkt { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_ofld_cfg { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_h2c_agg { + u32 dword0; +}; + +struct fwcmd_add_scanofld_ch { + u32 dword0; +}; + +struct fwcmd_scanofld { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; +}; + +struct fwcmd_tx_duty { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_disable_rf { + u32 dword0; +}; + +struct fwcmd_ch_switch { + u32 dword0; +}; + +struct fwcmd_pkt_drop { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_seccam_info { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_set_snd_para { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; + u32 dword16; + u32 dword17; + u32 dword18; + u32 dword19; + u32 dword20; + u32 dword21; + u32 dword22; + u32 dword23; + u32 dword24; + u32 dword25; + u32 dword26; + u32 dword27; + u32 dword28; + u32 dword29; + u32 dword30; + u32 dword31; + u32 dword32; + u32 dword33; + u32 dword34; + u32 dword35; + u32 dword36; + u32 dword37; + u32 dword38; + u32 dword39; + u32 dword40; + u32 dword41; + u32 dword42; + u32 dword43; + u32 dword44; + u32 dword45; + u32 dword46; + u32 dword47; + u32 dword48; + u32 dword49; + u32 dword50; + u32 dword51; + u32 dword52; + u32 dword53; + u32 dword54; + u32 dword55; + u32 dword56; + u32 dword57; + u32 dword58; + u32 dword59; + u32 dword60; + u32 dword61; + u32 dword62; + u32 dword63; + u32 dword64; + u32 dword65; + u32 dword66; + u32 dword67; + u32 dword68; + u32 dword69; + u32 dword70; + u32 dword71; + u32 dword72; + u32 dword73; + u32 dword74; + u32 dword75; + u32 dword76; + u32 dword77; +}; + +struct fwcmd_get_csi_buf { + u32 dword0; +}; + +struct fwcmd_set_csi_buf { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_get_snd_sts { + u32 dword0; +}; + +struct fwcmd_set_snd_sts { + u32 dword0; +}; + +struct fwcmd_init_snd_mer { + u32 dword0; +}; + +struct fwcmd_init_snd_mee { + u32 dword0; +}; + +struct fwcmd_csi_fix_rate { + u32 dword0; +}; + +struct fwcmd_csi_rrsc { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_set_mu_table { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; +}; + +struct fwcmd_set_csi_para_reg { + u32 dword0; +}; + +struct fwcmd_hw_snd_pr { + u32 dword0; +}; + +struct fwcmd_set_snd_para_v1 { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; + u32 dword16; + u32 dword17; + u32 dword18; + u32 dword19; + u32 dword20; + u32 dword21; + u32 dword22; + u32 dword23; + u32 dword24; + u32 dword25; + u32 dword26; + u32 dword27; + u32 dword28; + u32 dword29; + u32 dword30; + u32 dword31; + u32 dword32; + u32 dword33; + u32 dword34; + u32 dword35; + u32 dword36; + u32 dword37; + u32 dword38; + u32 dword39; + u32 dword40; + u32 dword41; + u32 dword42; + u32 dword43; + u32 dword44; + u32 dword45; + u32 dword46; + u32 dword47; + u32 dword48; + u32 dword49; + u32 dword50; + u32 dword51; + u32 dword52; + u32 dword53; + u32 dword54; + u32 dword55; + u32 dword56; + u32 dword57; + u32 dword58; + u32 dword59; + u32 dword60; + u32 dword61; + u32 dword62; + u32 dword63; + u32 dword64; + u32 dword65; + u32 dword66; + u32 dword67; + u32 dword68; + u32 dword69; + u32 dword70; + u32 dword71; + u32 dword72; + u32 dword73; + u32 dword74; + u32 dword75; + u32 dword76; + u32 dword77; + u32 dword78; + u32 dword79; + u32 dword80; + u32 dword81; + u32 dword82; + u32 dword83; + u32 dword84; + u32 dword85; + u32 dword86; + u32 dword87; + u32 dword88; + u32 dword89; + u32 dword90; + u32 dword91; + u32 dword92; + u32 dword93; + u32 dword94; + u32 dword95; + u32 dword96; + u32 dword97; + u32 dword98; + u32 dword99; + u32 dword100; + u32 dword101; + u32 dword102; + u32 dword103; +}; + +struct fwcmd_ba_cam { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_ie_cam { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_add_mcc { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_start_mcc { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_stop_mcc { + u32 dword0; +}; + +struct fwcmd_del_mcc_group { + u32 dword0; +}; + +struct fwcmd_reset_mcc_group { + u32 dword0; +}; + +struct fwcmd_mcc_req_tsf { + u32 dword0; +}; + +struct fwcmd_mcc_macid_bitmap { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_mcc_sync { + u32 dword0; +}; + +struct fwcmd_mcc_set_duration { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; +}; + +struct fwcmd_scsi_tx { + u32 dword0; +}; + +struct fwcmd_usb_switch { + u32 dword0; +}; + +struct fwcmd_plat_flash_write { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_plat_flash_erase { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_plat_flash_read { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_fcs { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_cfg_wps { + u32 dword0; +}; + +struct fwcmd_port_init { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_port_cfg { + u32 dword0; + u32 dword1; +}; + + +// +//H2CPKT - CAT(Table) +// +struct fwcmd_mude_para_tblud { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_mudecision_para { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_mu_fixinfo { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_ul_fixinfo_tblud { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; + u32 dword16; +}; + +struct fwcmd_ul_fixinfo { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; +}; + +struct fwcmd_ul_fixinfo_sta_info { + u32 dword0; +}; + +struct fwcmd_ul_fixinfo_ul_rua_sta_ent { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_addr_cam { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; +}; + +struct fwcmd_bssid_cam { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_sec_cam { + u32 dword0; +}; + +struct fwcmd_fixmode_para_tblud { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_fixmode_para { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_write_ofld_req { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_read_ofld_req { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_conf_ofld_req_cmd { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_dctrl { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_cctrl { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +struct fwcmd_ie_cam_info { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_plat_auto_test { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; +}; + +struct fwcmd_h2creg_sch_tx_pause { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_cmd_ofld { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + + +// +//H2CPKT - CAT(OutSrc,Phydm) +// +struct fwcmd_example { + u32 dword0; +}; + +struct fwcmd_macid_cfg { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_rssi_ra_config { + u32 dword0; + u32 dword1; + u32 dword2; +}; + + +// +//H2CPKT - CAT(OutSrc, RF) +// + +// +//H2CPKT - CAT(OutSrc, BTC) +// +struct fwcmd_tdma { + u32 dword0; +}; + + +// +//C2HPKT - CAT(TEST) +// +struct fwcmd_c2h_lb { + u32 dword0; +}; + +struct fwcmd_test_phy_rpt { + u32 dword0; +}; + +struct fwcmd_spic { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_spic2 { + u32 dword0; + u32 dword1; +}; + + +// +//C2HPKT - CAT(MAC) +// +struct fwcmd_rec_ack { + u32 dword0; +}; + +struct fwcmd_done_ack { + u32 dword0; +}; + +struct fwcmd_c2h_log { + u32 dword0; +}; + +struct fwcmd_bcn_cnt { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_bcn_csazero { + u32 dword0; +}; + +struct fwcmd_efuse_dump { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +struct fwcmd_read_rsp { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_pkt_ofld_rsp { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_fw_getpkt_rpt { + u32 dword0; +}; + +struct fwcmd_tsf32_togl_rpt { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_usr_tx_rpt_info { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; + u32 dword14; + u32 dword15; +}; + +struct fwcmd_cmd_ofld_rsp { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +struct fwcmd_scanofld_rsp { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; +}; + +struct fwcmd_tx_duty_rpt { + u32 dword0; +}; + +struct fwcmd_ch_switch_rpt { + u32 dword0; +}; + +struct fwcmd_wait_announce { + u32 dword0; +}; + +struct fwcmd_aoac_report { + u32 dword0; +}; + +struct fwcmd_read_wow_cam { + u32 dword0; + u32 dword1; +}; + +struct fwcmd_mcc_rcv_ack { + u32 dword0; +}; + +struct fwcmd_mcc_req_ack { + u32 dword0; +}; + +struct fwcmd_mcc_tsf_rpt { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; +}; + +struct fwcmd_mcc_status_rpt { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_rx_dbg { + u32 dword0; +}; + +struct fwcmd_scsi_rx { + u32 dword0; +}; + +struct fwcmd_fcs_rpt { + u32 dword0; +}; + +struct fwcmd_wps_rpt { + u32 dword0; +}; + +struct fwcmd_ccxrpt { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct fwcmd_port_init_stat { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_port_cfg_stat { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +struct fwcmd_notify_dbcc { + u32 dword0; +}; + +// +//C2HPKT - CAT(OutSrc, Phydm) +// + +// +//C2HPKT - CAT(OutSrc, RF) +// + +// +//C2HPKT - CAT(OutSrc, BTC) +// + +#endif diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.c b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.c new file mode 100644 index 0000000..4dbe263 --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.c @@ -0,0 +1,125838 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../../type.h" + +#ifdef CONFIG_RTL8852B + +#ifdef PHL_FEATURE_NIC + +#ifdef MAC_FW_8852B_U2 + +u8 array_8852b_u2_nic[] = { +0x02, 0x01, 0x52, 0x88, 0x00, 0x05, 0x1D, 0x00, +0xCF, 0x2B, 0x87, 0xDB, 0x20, 0x10, 0x50, 0x00, +0x0A, 0x08, 0x0E, 0x0F, 0xE5, 0x07, 0x00, 0x00, +0x00, 0x03, 0x10, 0x00, 0xF8, 0x07, 0x00, 0x00, +0x00, 0x00, 0x97, 0xB8, 0x88, 0xFD, 0x03, 0x02, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x20, 0xE1, 0xB8, 0xB0, 0x2C, 0x00, 0x01, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x7C, 0xE1, 0xB8, 0x00, 0x08, 0x00, 0x29, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xD8, 0xFF, 0xBD, 0x27, 0x24, 0x00, 0xBF, 0xAF, +0xE0, 0xBE, 0x26, 0x76, 0x01, 0x00, 0x04, 0x24, +0xE1, 0xB8, 0x02, 0x3C, 0x80, 0x9E, 0x42, 0x8C, +0xE1, 0xB8, 0x04, 0x3C, 0xE1, 0xB8, 0x06, 0x3C, +0xB0, 0x4C, 0x84, 0x24, 0x40, 0x58, 0xC6, 0x24, +0x23, 0x30, 0xC4, 0x00, 0x09, 0xF8, 0x40, 0x00, +0x25, 0x28, 0x00, 0x00, 0xE1, 0xB8, 0x02, 0x3C, +0x00, 0x90, 0x42, 0x24, 0x10, 0x00, 0xA2, 0xAF, +0xE1, 0xB8, 0x02, 0x3C, 0xF4, 0x9E, 0x42, 0x24, +0x14, 0x00, 0xA2, 0xAF, 0xE1, 0xB8, 0x02, 0x3C, +0x00, 0x20, 0x42, 0x24, 0x18, 0x00, 0xA2, 0xAF, +0xE1, 0xB8, 0x02, 0x3C, 0xF4, 0x2E, 0x42, 0x24, +0x10, 0x00, 0xA4, 0x27, 0x26, 0x7B, 0x26, 0x76, +0x1C, 0x00, 0xA2, 0xAF, 0x1D, 0x1F, 0x26, 0x76, +0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x24, +0xE1, 0xB8, 0x02, 0x3C, 0x7E, 0xC3, 0x43, 0xA0, +0xE1, 0xB8, 0x02, 0x3C, 0xC4, 0x94, 0x42, 0x8C, +0x09, 0x00, 0x05, 0x24, 0x09, 0xF8, 0x40, 0x00, +0xF2, 0x83, 0x04, 0x34, 0x24, 0x00, 0xBF, 0x8F, +0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xE0, 0x03, +0x28, 0x00, 0xBD, 0x27, 0xFC, 0x63, 0x07, 0x62, +0x06, 0xD1, 0x05, 0xD0, 0xF7, 0xF0, 0x01, 0x6A, +0x40, 0x32, 0x40, 0x32, 0x73, 0xF4, 0x50, 0x9A, +0xF7, 0xF0, 0x01, 0x68, 0x40, 0xEA, 0x00, 0x30, +0xF7, 0xF0, 0x01, 0x6A, 0x40, 0x32, 0x40, 0x32, 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0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +u32 array_length_8852b_u2_wowlan_bplus = 228000; + +#endif /*MAC_FW_8852B_U2*/ + +#endif /*CONFIG_WOWLAN*/ + +#endif /*PHL_FEATURE_NIC*/ + +#endif /*CONFIG_RTL8852B*/ diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.h b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.h new file mode 100644 index 0000000..b673615 --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifdef CONFIG_RTL8852B + +#ifdef PHL_FEATURE_NIC +#ifdef MAC_FW_8852B_U2 +extern u8 array_8852b_u2_nic[275080]; +extern u32 array_length_8852b_u2_nic; +#endif /*MAC_FW_8852B_U2*/ +#ifdef MAC_FW_8852B_U2 +extern u8 array_8852b_u2_nic_bplus[275080]; +extern u32 array_length_8852b_u2_nic_bplus; +#endif /*MAC_FW_8852B_U2*/ +#ifdef CONFIG_WOWLAN +#ifdef MAC_FW_8852B_U2 +extern u8 array_8852b_u2_wowlan[228000]; +extern u32 array_length_8852b_u2_wowlan; +#endif /*MAC_FW_8852B_U2*/ +#endif /*CONFIG_WOWLAN*/ +#ifdef CONFIG_WOWLAN +#ifdef MAC_FW_8852B_U2 +extern u8 array_8852b_u2_wowlan_bplus[228000]; +extern u32 array_length_8852b_u2_wowlan_bplus; +#endif /*MAC_FW_8852B_U2*/ +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + +#endif /*CONFIG_RTL8852B*/ + diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.c b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.c new file mode 100644 index 0000000..016acba --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.c @@ -0,0 +1,719 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "./hal8852b_fw_log.h" + +struct mac_fw_msg fw_log_8852b[] = { + {MSG_8852B_FIRST, "RESERVED"}, + {MSG_8852B_SAMPLE_NO_PARAMETER, "Sample without parameter.\n"}, + {MSG_8852B_SAMPLE_PARAMETER, "Sample string:%s.\n"}, + {MSG_8852B_SAMPLE_INTEGER, "Sample integer:%d.\n"}, + {MSG_8852B_SAMPLE_INTEGER_X, "Sample integer:0x%x.\n"}, + {MSG_8852B_SAMPLE_INTEGER_2, "Sample integer1:%d, integer2:%d.\n"}, + {MSG_8852B_FCUN_NAME, "%s()\n"}, + {MSG_8852B_MAIN_1, "FW from host\n"}, + {MSG_8852B_MAIN_2, "Skip DL FW handler\n"}, + {MSG_8852B_MAIN_3, "FW from flash\n"}, + {MSG_8852B_MAIN_4, "Invalid boot mode\n"}, + {MSG_8852B_FWDLHDL_1, "Invalid boot reason\n"}, + {MSG_8852B_FWDLHDL_2, "Enter DL FW handler\n"}, + {MSG_8852B_FWDLHDL_3, "FWHDR H2C done\n"}, + {MSG_8852B_FLASHBOOT, "Enter flash FW loader\n"}, + {MSG_8852B_IRAMENTRN, "Load FW RAM code OK\n"}, + {MSG_8852B_FIRSTH2C_1, "First H2C Enqueue\n"}, + {MSG_8852B_FIRSTH2C_2, "H2C node malloc fail\n"}, + {MSG_8852B_FIRSTH2C_3, "H2C node content malloc fail\n"}, + {MSG_8852B_H2CDEQ_1, "H2C Dequeue\n"}, + {MSG_8852B_H2CDEQ_2, "H2CPKT enqueue fail\n"}, + {MSG_8852B_H2CPKT_1, "content = 0x%x 0x%x 0x%x 0x%x\n"}, + {MSG_8852B_RESERVED_ROM, "RESERVED"}, + {MSG_8852B_CMDTABLE_NAME, "%s "}, + {MSG_8852B_CMDTABLE_1, " ?\n"}, + {MSG_8852B_CMDTABLE_2, " dump bytes, ex: DB 0xb8e00000\n"}, + {MSG_8852B_CMDTABLE_3, " write bytes, ex: EB 0xb8e00000 0x1\n"}, + {MSG_8852B_CMDTABLE_4, " dump words, ex: DW 0xb8e00000\n"}, + {MSG_8852B_CMDTABLE_5, " write words, ex: EW 0xb8e00000, 0x12345678\n"}, + {MSG_8852B_CMDTABLE_6, " jump to address, ex: j 0xb8900000\n"}, + {MSG_8852B_CMDTABLE_7, " set debug level\n"}, + {MSG_8852B_CMDTABLE_8, " set debug compoment bitmap\n"}, + {MSG_8852B_CMDTABLE_9, " show task info\n"}, + {MSG_8852B_CMDTABLE_10, " show heap info\n"}, + {MSG_8852B_CMDTABLE_11, " show dynamic allocate memory info, , \n"}, + {MSG_8852B_CMDTABLE_12, " show task time state\n"}, + {MSG_8852B_CMDTABLE_13, " AXIDMA test\n"}, + {MSG_8852B_CMDTABLE_14, " SPIC test\n"}, + {MSG_8852B_CMDTABLE_15, " IDDMA test\n"}, + {MSG_8852B_CMDTABLE_16, " RXI300 test\n"}, + {MSG_8852B_CMDTABLE_17, " DLE test\n"}, + {MSG_8852B_CMDTABLE_18, " HIOE test\n"}, + {MSG_8852B_CMDTABLE_19, " RPT test\n"}, + {MSG_8852B_CMDTABLE_20, " MISC test\n"}, + {MSG_8852B_CMDTABLE_21, " Update STA para for F2PTXCMD\n"}, + {MSG_8852B_CMDTABLE_22, " Update Common para for F2PTXCMD\n"}, + {MSG_8852B_CMDTABLE_23, " Wlan Flow Test\n"}, + {MSG_8852B_CMDTABLE_24, " Wlan Test Mode Setting\n"}, + {MSG_8852B_CMDTABLE_25, " Wlan Flow with RUA Test\n"}, + {MSG_8852B_CMDTABLE_26, " Wlan UL Flow Test\n"}, + {MSG_8852B_CMDTABLE_27, " IPSec test\n"}, + {MSG_8852B_CMDTABLE_28, " CryptoSig test\n"}, + {MSG_8852B_CMDTABLE_29, " SecureBoot test\n"}, + {MSG_8852B_CMDTABLE_30, " Secure eFuse R/W test\n"}, + {MSG_8852B_CMDTABLE_31, " Plat test\n"}, + {MSG_8852B_CMDTABLE_32, " H2C/C2H test\n"}, + {MSG_8852B_CMDTABLE_33, " UL F2PCMD test, , , 0\n"}, + {MSG_8852B_CMDTABLE_34, " Sounding test\n"}, + {MSG_8852B_CMDTABLE_35, " security CAM test\n"}, + {MSG_8852B_CMDTABLE_36, " Gtimer test, , , , \n"}, + {MSG_8852B_CMDTABLE_37, " PStimer test, , , , (valid if mode = 0)\n"}, + {MSG_8852B_CMDTABLE_38, " RPWM test\n"}, + {MSG_8852B_CMDTABLE_39, " DLTXD test\n"}, + {MSG_8852B_CMDTABLE_40, " PS test\n"}, + {MSG_8852B_CMDTABLE_41, " 32K CAL test\n"}, + {MSG_8852B_CMDTABLE_42, " WoW CAM test\n"}, + {MSG_8852B_CMDTABLE_43, " PS ONOFF test\n"}, + {MSG_8852B_CMDTABLE_44, " BTCoex test\n"}, + {MSG_8852B_CMDTABLE_45, " DL Parameters Setting\n"}, + {MSG_8852B_CMDTABLE_46, " Dump Wlan common info, f2pcmd result, decision result\n"}, + {MSG_8852B_CMDTABLE_47, " Dump Wlan sta or muru grp info\n"}, + {MSG_8852B_CMDTABLE_48, " Dump Wlan decision info\n"}, + {MSG_8852B_CMDTABLE_49, " Dump FW info\n"}, + {MSG_8852B_CMDTABLE_50, " TFDBG\n"}, + {MSG_8852B_CMDTABLE_51, " CRT\n"}, + {MSG_8852B_MALLOC_F, "malloc is failed\n"}, + {MSG_8852B_STRING_0, "%s\n"}, + {MSG_8852B_STRING_1, "%s"}, + {MSG_8852B_PARA_INVALID, "Invalid parameters\n"}, + {MSG_8852B_CMD_UNKNOWN, "Unknown cmd\n"}, + {MSG_8852B_CONSOLE_1, "- CMD -\n"}, + {MSG_8852B_CONSOLE_2, "0x%x: 0x%x\n"}, + {MSG_8852B_CONSOLE_3, "Jump to 0x%x\n"}, + {MSG_8852B_CONSOLE_4, "Set dbg level to: 0x%x\n"}, + {MSG_8852B_CONSOLE_5, "Set dbg component bitmap to: 0x%x\n"}, + {MSG_8852B_CONSOLE_6, "Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n"}, + {MSG_8852B_CONSOLE_7, "--------------------------------------------------------------------------------\n"}, + {MSG_8852B_CONSOLE_8, "Index\t\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n"}, + {MSG_8852B_CONSOLE_9, "------------------------------------------------------------------------\n"}, + {MSG_8852B_CONSOLE_10, "Address\t\tOwner ID\tFunction\tType\t\tSize(B)\n"}, + {MSG_8852B_CONSOLE_11, "Owner ID\tFunction\tType\t\tCounter\t\tTotalSize(B)\tHistorical High\n"}, + {MSG_8852B_CONSOLE_12, "------------------------------------------------------------------------------------------------\n"}, + {MSG_8852B_CONSOLE_13, "Owner ID\tType\t\tTotalSize(B)\n"}, + {MSG_8852B_CONSOLE_14, "------------------------------------------------\n"}, + {MSG_8852B_MCC_SEARCHMACID_1, "[MCC] pmcc_info is NULL!\n"}, + {MSG_8852B_MCC_SEARCHMACID_2, "[MCC] pgroup_list is empty!\n"}, + {MSG_8852B_MCC_STATUSRPTHDL_1, "[MCC] MCCStatusRptHDL macid: %d, group: %d, status: %d\n"}, + {MSG_8852B_MCC_STATUSRPTHDL_2, "[MCC] tsf: 0x%x 0x%x\n"}, + {MSG_8852B_MCC_TBTTSTATUSRPTHDL, "[MCC] B%dP%d TBTT TSF = 0x%x\n"}, + {MSG_8852B_MCC_MACIDDROP, "[MCC] MACIDTxIdleCheck fail\n"}, + {MSG_8852B_MCC_ISSUENULLWOLPS_1, "[MCC][%d][CXEVNT_ENULL]\n"}, + {MSG_8852B_MCC_ISSUENULLWOLPS_2, "[MCC] Issue null %d fail!!!\n"}, + {MSG_8852B_MCC_ISSUENULL_1, "[MCC] macid %d role not found\n"}, + {MSG_8852B_MCC_ISSUENULL_2, "[MCC][%d]Macid %d Null %d, TSF = 0x%x, freerun = 0x%x\n"}, + {MSG_8852B_MCC_TXNULLCHK_1, "[MCC] mcc group not found\n"}, + {MSG_8852B_MCC_TXNULLCHK_2, "[MCC] take semaphore fail!\n"}, + {MSG_8852B_MCC_TXNULLCHK_3, "[MCC][%d]Macid %d TxNull %d SUCCESS, freerun = 0x%x\n"}, + {MSG_8852B_MCC_TXNULLCHK_4, "[MCC][%d]Macid %d TxNull %d FAIL, freerun = 0x%x\n"}, + {MSG_8852B_MCC_SENDNULLCB_1, "[MCC][RPT] MACID DROP => macid (%d)\n"}, + {MSG_8852B_MCC_SENDNULLCB_2, "[MCC][RPT] LIFE DROP => macid (%d)\n"}, + {MSG_8852B_MCC_SENDNULLCB_3, "[MCC][RPT] invalid RPT (%d)\n"}, + {MSG_8852B_MCC_SWITCHCH_1, "[MCC] cfg ch FAIL!!!\n"}, + {MSG_8852B_MCC_SWITCHCH_2, "[MCC] CH SW, CH= %d\n"}, + {MSG_8852B_MCC_SWITCHCH_3, "[MCC] CH SW WARNING (%d)\n"}, + {MSG_8852B_MCC_SWITCHCH_4, "[MCC] RFK bypass\n"}, + {MSG_8852B_MCC_CHANGEROLE_1, "[MCC] MCCMacidDrop fail\n"}, + {MSG_8852B_MCC_CHANGEROLE_2, "[MCC](courtesy)macid %d => macid %d\n"}, + {MSG_8852B_MCC_CHANGEROLE_3, "[MCC][%d][CXEVNT_EBT]\n"}, + {MSG_8852B_MCC_CHANGEROLE_4, "[MCC][%d][CXEVNT_E5G]\n"}, + {MSG_8852B_MCC_CHANGEROLE_5, "[MCC][%d][CXEVNT_E2G]\n"}, + {MSG_8852B_MCC_CHANGEROLE_6, "[MCC][%d]Start BT TSF = 0x%x, freerun = 0x%x\n"}, + {MSG_8852B_MCC_CHANGEROLE_7, "[MCC][%d]Start macid %d TSF = 0x%x, freerun = 0x%x\n"}, + {MSG_8852B_MCC_CHANGEROLE_8, "[MCC] MCCMacidDropRel fail\n"}, + {MSG_8852B_MCC_FIRSTDURATIONENDHDL_1, "[MCC] First duration running\n"}, + {MSG_8852B_MCC_FIRSTDURATIONENDHDL_2, "[MCC][REP/STP] act: %d, deal with old schedule now...\n"}, + {MSG_8852B_MCC_FIRSTDURATIONENDHDL_3, "[MCC] MCCGroupStop fail\n"}, + {MSG_8852B_MCC_FIRSTDURATIONENDHDL_4, "[MCC] MCCGroupDel fail\n"}, + {MSG_8852B_MCC_GROUPSTOP_1, "[MCC] FirstDuration timer del!\n"}, + {MSG_8852B_MCC_GROUPSTOP_2, "[MCC] replace/pause mode, FirstDuration del bypass!\n"}, + {MSG_8852B_MCC_NEWDURATIONHDL, "[MCC] Set duration\n"}, + {MSG_8852B_MCC_BITMAPCMP_1, "[MCC] Release macid %d\n"}, + {MSG_8852B_MCC_BITMAPCMP_2, "[MCC] Pause macid %d\n"}, + {MSG_8852B_MCC_H2CADDMCCHDL_1, "[MCC] Add MCC macid %d to group %d\n"}, + {MSG_8852B_MCC_H2CADDMCCHDL_2, "[MCC] macid: %d, duration: %d, bt_in_2g: %d\n"}, + {MSG_8852B_MCC_H2CADDMCCHDL_3, "[MCC] Add MCC band %d port %d\n"}, + {MSG_8852B_MCC_H2CSTARTMCCHDL_1, "[MCC] Start MCC group %d from macid %d\n"}, + {MSG_8852B_MCC_H2CSTARTMCCHDL_2, "[MCC][REP/STP] Group new idx: %d, old idx: %d, act: %d\n"}, + {MSG_8852B_MCC_H2CSTOPMCCHDL_1, "[MCC][stop]prev_groups: %d\n"}, + {MSG_8852B_MCC_H2CSTOPMCCHDL_2, "[MCC][stop]stop group %d fail\n"}, + {MSG_8852B_MCC_H2CSTOPMCCHDL_3, "[MCC][stop]group %d stop!\n"}, + {MSG_8852B_MCC_H2CDELMCCGROUPHDL_1, "[MCC][Del] prev_groups: %d\n"}, + {MSG_8852B_MCC_H2CDELMCCGROUPHDL_2, "[MCC][del]del group %d fail\n"}, + {MSG_8852B_MCC_H2CDELMCCGROUPHDL_3, "[MCC][del]group %d del!\n"}, + {MSG_8852B_MCC_H2CMCCREQTSFHDL_1, "[MCC] macid %d is not in role table\n"}, + {MSG_8852B_DEBUGINFO_1, "ISR Name\tCount\t\tExec Time(historical high)\n"}, + {MSG_8852B_DEBUGINFO_2, "------------------------------------------------\n"}, + {MSG_8852B_DEBUGINFO_3, "\t%d\t\t%d_%d\n"}, + {MSG_8852B_DEBUGINFO_4, "\t\t%d\t\t%d_%d\n"}, + {MSG_8852B_DEBUGINFO_5, "[Error] ISRInfo len = %d!\n"}, + {MSG_8852B_PROFILING_1, "func_name %s , "}, + {MSG_8852B_PROFILING_2, "line %d , cycle %d , offset = %d\n"}, + {MSG_8852B_WLANDUMP_0, "Tx ok packet cnt: %d\n Tx fail packet cnt: %d\n Txcmd success cnt: %d\n Txcmd abort (MU-RTS/RTS fail) cnt: %d\n Txcmd abort (over SP) cnt: %d\n"}, + {MSG_8852B_WLANDUMP_1, "Txcmd sounding abort cnt: %d\n Txcmd abort (pri user fail) cnt: %d\n Txcmd abort ( cca or medium busy) cnt: %d\n Txcmd RU/MU2SU cnt: %d\n"}, + {MSG_8852B_WLANDUMP_2, "chkcmd_sts cnt: %d %d %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_3, "TBD"}, + {MSG_8852B_WLANDUMP_4, "DL Txcmd in last TXOP cnt: %d\n UL Txcmd in last TXOP cnt: %d\n Empty DL SS2F report cnt: %d\n Empty UL SS2F report cnt: %d\n DL TxcmdQ empty cnt: %d\n"}, + {MSG_8852B_WLANDUMP_5, "Issue DL SU Txcmd cnt: %d\n Issue DL MU Txcmd cnt: %d\n Issue DL RU Txcmd cnt: %d\n Issue UL Txcmd cnt: %d\n f2p_Triggerpkt_cnt=%d\n"}, + {MSG_8852B_WLANDUMP_6, "Decision MU2SU cnt: %d\n Decision RU2SU cnt: %d\n DLDecision Result record: %x\n Decision SU_FORCESU cnt: %d\n Decision MU_FORCEMU cnt: %d\n"}, + {MSG_8852B_WLANDUMP_7, "Decision SU_FORCEMU_FAIL cnt: %d\n Decision SU_FORCERU_FAIL cnt: %d\n Decision SU_FORCERU_RUARST_RU2SU cnt: %d\n Decision SU_NOT4_USER cnt: %d\n Decision RU_FORCERU_RUSRST_FIXTBL cnt: %d\n"}, + {MSG_8852B_WLANDUMP_8, "Decision RU_FORCERU cnt: %d\n Decision SU_WDINFO_USERATE cnt: %d\n Decision SU_PRINULLWD cnt: %d\n ecision MU_BYPASS_MUTPCOMPARE cnt: %d\n Decision SU_MUTXTIME_PASS_MU_NOTSUPPORT cnt: %d\n"}, + {MSG_8852B_WLANDUMP_9, "Decision SU_MUTXTIME_FAIL_RU_NOTSUPPORT cnt: %d\n Decision SU_RUARST_RU2SU cnt: %d\n Decision RU_RUARST_FIXTBL cnt: %d\n Decision MU_TPCOMPARE_RST cnt: %d\n Decision RU_TPCOMPARE_RST cnt: %d\n Decision SU_TPCOMPARE_RST cnt: %d\n"}, + {MSG_8852B_WLANDUMP_10, "fw txcmdQ[0] cmd num: %d, fw txcmdQ[1] cmd num: %d,fw txcmdQ[2] cmd num: %d,fw txcmdQ[3] cmd num: %d,fw txcmdQ[4] cmd num: %d\n"}, + {MSG_8852B_WLANDUMP_11, "fw txcmdQ[5] cmd num: %d, fw txcmdQ[6] cmd num: %d,fw txcmdQ[7] cmd num: %d,fw txcmdQ[8] cmd num: %d,fw txcmdQ[9] cmd num: %d, fw txcmdQ[10] cmd num: %d\n"}, + {MSG_8852B_WLANDUMP_12, "TBD"}, + {MSG_8852B_WLANDUMP_13, "mbid0~7: %d %d %d %d %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_14, "macid %d info:\n isHESTA =%d\n AID12 =%d\n DL_BW =%d\n DL_T_PE =%d\n"}, + {MSG_8852B_WLANDUMP_15, "TF_MAC_Padding =%d\n force tx su =%d\n force tx mu =%d\n fw force mu2su TH = %d\n force tx ru =%d\n"}, + {MSG_8852B_WLANDUMP_16, "txok_pkt =%d\n txfail pkt cnt: %d\n retry_cnt =%d\n mbssid_idx =%d\n ulgroup_bitmap =%d\n null_wd_cnt =%d\n"}, + {MSG_8852B_WLANDUMP_17, "ul_sw_grp_bitmap =%d\n AMPDU_max_txtime =%d\n mu_doppler_ctrl =%d\n mu_gi_ltf =%d\n mu decision txtime_bypass =%d\n mu decision mutp_bypass =%d\n"}, + {MSG_8852B_WLANDUMP_18, "mu_maxinitrate = %x\n mu_maxfinalrate = %x\n mu_mininitrate = %x\n mu_minfinalrate = %x\n mu primary cnt = %d\n"}, + {MSG_8852B_WLANDUMP_19, " PwrBit =%d\n TP =%d Mbps\n Max Txlen = %x (unit23 byte)\n Min Txlen = %x (unit23 byte)\n Last Txlen = %x (unit23 byte)\n Last BSRlen = %x (unit256 byte) AC=%d\n"}, + {MSG_8852B_WLANDUMP_20, "mu sta %d info\n mu sta macid= %d\n"}, + {MSG_8852B_WLANDUMP_21, "mu sta rate array(8bit) 0-4: %x %x %x %x %x"}, + {MSG_8852B_WLANDUMP_22, "mu sta rate array(8bit) 5-9: %x %x %x %x %x"}, + {MSG_8852B_WLANDUMP_23, "su ok pkt cnt = %d\n su fail pkt cnt = %d\n su_norsp_pktcnt = %d\n SU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n SU TXCNT 1/<6/<16/>=16 : %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_24, "mu ok pkt cnt = %d\n mu fail pkt cnt = %d\n mu_norsp_pktcnt = %d\n mu2su ok pkt cnt = %d\n mu2su fail pkt cnt = %d\n"}, + {MSG_8852B_WLANDUMP_25, "ru ok pkt cnt = %d\n ru fail pkt cnt = %d\n"}, + {MSG_8852B_WLANDUMP_26, "MU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n MU DIFF <4/<8/<12/>=12 : %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_27, "MU TXCNT 1/<6/<16/>=16: %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_28, "pktmaxtxcnt(su base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu2nd base) [0]= %d [1]= %d [2]= %d \n"}, + {MSG_8852B_WLANDUMP_30, "F2PTXCMDRPT cnt= %d, SS2FWRPT cnt =%d, TXRPT cnt =%d, PLDRLSRPT cnt = %d\n"}, + {MSG_8852B_WLANDUMP_31, "pkt_max_queue_time = %x, pkt_min_queue_time=%x\n"}, + {MSG_8852B_WLANDUMP_32, "TWT %d info:\n Txcmd overSP= %d\n Txcmd pri user fail= %d\n DL cmdCnt inSP= %d\n UL cmdCnt inSP= %d\n"}, + {MSG_8852B_WLANDUMP_33, "DL cmdCnt all= %d\n UL cmdCnt all= %d\n UL fixmode = %x\n cur cmd num = %x\n SP 1st TF fail cnt = %x\n"}, + {MSG_8852B_WLANDUMP_34, "start_d= %d\n start_t= %d\n endearly_d= %d\n endearly_t= %d\n end_d= %d\n"}, + {MSG_8852B_WLANDUMP_35, "end_t= %d\n timer_qrydl= %d\n timer_qryul= %d\n start_qrydl= %d\n total_qryul=%d\n"}, + {MSG_8852B_WLANDUMP_36, "firstTF_fail = %d,%d\n"}, + {MSG_8852B_WLANDUMP_37, "twt_decision_brk = %d, %d, %d, %d, %d, %d, %d, %d\n"}, + {MSG_8852B_WLANDUMP_38, "twt_decision_rst= %d, %d, %d\n"}, + {MSG_8852B_WLANDUMP_39, "twt_ACdecision_rst= %d, %d, %d, %d\n"}, + {MSG_8852B_WLANDUMP_40, "twt_validdlss2f_cnt= %d, twt_emptydlss2f_cnt= %d, twt_validulss2f_cnt= %d, twt_emptyulss2f_cnt= %d, twt_dlss2f_fromquery= %d, twt_dlss2f_fromtxcmd=%d, twt_ulss2f_fromquery= %d, twt_ulss2f_fromtxcmd=%d\n"}, + {MSG_8852B_WLANDUMP_41, "TWT member: %d %d %d %d %d\n"}, + {MSG_8852B_WLANDUMP_42, "twt_dlss2f_qrycnt[0]=%d,twt_dlss2f_qrycnt[1]=%d,twt_dlss2f_qrycnt[2]=%d,twt_dlss2f_qrycnt[3]=%d\n"}, + {MSG_8852B_WLANDUMP_43, "reform_fail_rst[0]=%d, reform_fail_rst[1]=%d, reform_fail_rst[2]=%d, reform_fail_rst[3]=%d, reform_fail_rst[4]=%d\n"}, + {MSG_8852B_WLANDUMP_44, "MACID WD count BE:%d BK:%d VI:%d VO:%d\n"}, + {MSG_8852B_WLANDUMP_45, "PPS F2PCMD_PPS:%d/s TXRPT_PPS:%d/s TXPKT_PPS:%d/s SS2F_0_PPS:%d/s SS2F_1_PPS:%d/s SS2F_2_PPS:%d/s"}, + {MSG_8852B_ROLE_1, "B%dP%d RXBCNOK\n"}, + {MSG_8852B_ROLE_2, "B%dP%d BCNNOHIT\n"}, + {MSG_8852B_ROLE_3, "Role idx search fail\n"}, + {MSG_8852B_ROLE_4, "=>CreateRole\n"}, + {MSG_8852B_ROLE_5, "[FAIL] Role info alloc fail!\n"}, + {MSG_8852B_ROLE_6, "[FAIL] Role info - PPSDbgParm alloc fail!\n"}, + {MSG_8852B_ROLE_7, "[FAIL] Role info - PTWTParam alloc fail!\n"}, + {MSG_8852B_ROLE_8, "[CreateRole] ActRole=%d, LinkRole=%d.\n"}, + {MSG_8852B_ROLE_9, "[CreateRole] band=%d, port=%d, macid=%d.\n"}, + {MSG_8852B_ROLE_10, "=>DelRole\n"}, + {MSG_8852B_ROLE_11, "[Warn] ROLE_NOT_EXIST for DelRole!\n"}, + {MSG_8852B_ROLE_12, "[DelRole] ActRole=%d!role_idx=%d\n"}, + {MSG_8852B_ROLE_13, "Role idx search by macid fail\n"}, + {MSG_8852B_ROLE_14, "[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"}, + {MSG_8852B_ROLE_15, "[FAIL] Create Role idx > max_number!\n"}, + {MSG_8852B_ROLE_16, "[FAIL] Create Role fail!\n"}, + {MSG_8852B_ROLE_17, "[Warn] search role fail for JoinInfo!\n"}, + {MSG_8852B_ROLE_18, "[FAIL] JoinInfo Role idx > max_number!\n"}, + {MSG_8852B_ROLE_19, "[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"}, + {MSG_8852B_ROLE_20, "[Warn] search role fail for DelRole!\n"}, + {MSG_8852B_ROLE_21, "[FAIL] Del Role idx > max_number!\n"}, + {MSG_8852B_PMF_00, "start saquery timer fail\n"}, + {MSG_8852B_PMF_01, "start saquery timer\n"}, + {MSG_8852B_PMF_02, "creat saquery timer fail\n"}, + {MSG_8852B_PMF_03, "saquery timer is lanched alread\n"}, + {MSG_8852B_PMF_04, "SA Query timer deleted!\n"}, + {MSG_8852B_PMF_05, "Deauth content\n"}, + {MSG_8852B_PMF_06, "packet_len_no_fcs error\n"}, + {MSG_8852B_PMF_07, "ICV Error ok\n"}, + {MSG_8852B_PMF_08, "encrypted deauth frame, SEC_TYPE: 0x%x) \n"}, + {MSG_8852B_PMF_09, "not Encrypted Deauth/Disassoc\n"}, + {MSG_8852B_PMF_10, "deauth_reason = %x %x\n"}, + {MSG_8852B_PMF_11, "tx_sa_query_result = 0x%x\n"}, + {MSG_8852B_PMF_12, "issue saquery req fail\n"}, + {MSG_8852B_PMF_13, "ignore the deauth frame\n"}, + {MSG_8852B_PMF_14, "ICV Error\n"}, + {MSG_8852B_PMF_15, "bip_result=0x%x\n"}, + {MSG_8852B_PMF_16, "\npacket_len_no_fcs error\n"}, + {MSG_8852B_PMF_17, "\nOn SA Query Req! (len=0x%x)\n"}, + {MSG_8852B_PMF_18, "issue saquery rsp fail\n"}, + {MSG_8852B_PMF_19, "\nOn SA Query Resp!(len=0x%x)\n"}, + {MSG_8852B_PMF_20, "issue_sa_query_timeout_hdl!\n"}, + {MSG_8852B_PMF_21, "Deauth wake up!\n"}, + {MSG_8852B_PMF_22, "can't get offload PKT for saquery\n"}, + {MSG_8852B_PMF_23, "can't allocate sendpkt_buff \n"}, + {MSG_8852B_PMF_24, "FW IPN > pkt IPN\n"}, + {MSG_8852B_PMF_25, "FW IPN < pkt IPN\n"}, + {MSG_8852B_PMF_26, "FW IPN == pkt IPN\n"}, + {MSG_8852B_PMF_27, "IPSecAESECBInit false\n"}, + {MSG_8852B_PMF_28, "IPSecAESECBEncrypt false\n"}, + {MSG_8852B_PMF_30, "key_len = %d, false\n"}, + {MSG_8852B_PMF_31, "iv_len = %d, false\n"}, + {MSG_8852B_PMF_32, "IPSecInitWithISRDisable false\n"}, + {MSG_8852B_PMF_40, "MIC check fail\n"}, + {MSG_8852B_PMF_41, "\n: aes_gmac fail!\n"}, + {MSG_8852B_PMF_42, "\n: _bip_gcmp_protect(128) fail!\n"}, + {MSG_8852B_PMF_43, "\n: _bip_gcmp_protect(256) fail!\n"}, + {MSG_8852B_PMF_44, "\n: unsupport dot11wCipher !\n"}, + {MSG_8852B_PMF_45, "not a management frame\n"}, + {MSG_8852B_PMF_46, "is a beacon\n"}, + {MSG_8852B_PMF_47, "not a broadcast frame\n"}, + {MSG_8852B_PMF_48, "packet too small\n"}, + {MSG_8852B_PMF_49, "elemnt_id != 0x4c\n"}, + {MSG_8852B_PMF_50, "is_bip_enc_frameComm return TRUE\n"}, + {MSG_8852B_PMF_51, "\nbip_verifyComm: PKT (len=0x%x)\n"}, + {MSG_8852B_PMF_52, "BSSID not match\n"}, + {MSG_8852B_PMF_53, "ori_len = 0x%x\n"}, + {MSG_8852B_PMF_54, "SW BIP DEC FAIL\n"}, + {MSG_8852B_PMF_55, "NOT encrypted\n"}, + {MSG_8852B_PMF_56, "IPN verify Fail\n"}, + {MSG_8852B_PMF_57, "bip_verifyComm return TRUE\n"}, + {MSG_8852B_PMF_58, "protection bit is not 1\n"}, + {MSG_8852B_PMF_59, "not a unicast frame\n"}, + {MSG_8852B_PMF_60, "PairwiseEncAlg not GCMP\n"}, + {MSG_8852B_PMF_61, "aes_gcm_ad fail\n"}, + {MSG_8852B_PMF_62, "aes_gcm_ae fail\n"}, + {MSG_8852B_RXFLOW_1, "can't allocate wlan pktbuf\n"}, + {MSG_8852B_RXFLOW_2, "DD=%x\n"}, + {MSG_8852B_RXFLOW_3, "A=%x\n"}, + {MSG_8852B_RXFLOW_4, "B=%x\n"}, + {MSG_8852B_RXFWD_1, "Unsupported index!\n"}, + {MSG_8852B_WLAN_1, "SS Query Report HW stuck!!\n"}, + {MSG_8852B_SECCAM_1, "Search key, mac_id : %d, key_id : %d, key_type : %d , fail\n"}, + {MSG_8852B_SECCAM_2, "Search key success\nMac_id : %d, key_id : %d, key_type : %d, key cam index : %d\n"}, + {MSG_8852B_SECCAM_3, "Wowlan rekey %d, %d, %d\n"}, + {MSG_8852B_SECCAM_4, "check addr key index full\n"}, + {MSG_8852B_SECCAM_5, "Free cam index: %d\n"}, + {MSG_8852B_SECCAM_6, "insertKeyAddrCam ret : %d\n"}, + {MSG_8852B_RPTHDL_1, "pldrlsrpt len %d not align\n"}, + {MSG_8852B_RPTHDL_2, "RlsRptHDLRAM8852B,rpt_num=%x,len=%x\n"}, + {MSG_8852B_RPTHDL_3, "ERR: TxCmdRptHDL get NULL txinfo node,rpt->QSEL=%x, (rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"}, + {MSG_8852B_RPTHDL_4, "ERR: TxRptHDL get NULL txinfo node,rpt->QSEL=%x,(rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"}, + {MSG_8852B_RPTHDL_5, "ERR: TfRptHDL get NULL txinfo node\n"}, + {MSG_8852B_RPTHDL_6, "SS2FInfoDeQ8852B\n"}, + {MSG_8852B_RPTHDL_7, "F2PTXCMDRPT HDL\n"}, + {MSG_8852B_RPTHDL_8, "SS2FWRPT HDL\n"}, + {MSG_8852B_RPTHDL_9, "TFRPT HDL\n"}, + {MSG_8852B_RPTHDL_10, "TXBCNRPT HDL\n"}, + {MSG_8852B_RPTHDL_11, "CCXRPT HDL\n"}, + {MSG_8852B_RPTHDL_12, "TXRPT HDL\n"}, + {MSG_8852B_RPTHDL_13, "PLDRLSRPT HDL\n"}, + {MSG_8852B_ERRHDL_1, "[ERR]DLE Timeout(idx = %d)\n"}, + {MSG_8852B_ERRHDL_2, "[ERR]AXIDMA is not idle!\n"}, + {MSG_8852B_ERRHDL_3, "[ERR]STA scheduler init\n"}, + {MSG_8852B_ERRHDL_4, "[ERR]WDE cfg ready\n"}, + {MSG_8852B_ERRHDL_5, "[ERR]PLE cfg ready\n"}, + {MSG_8852B_ERRHDL_6, "=>DmaTopStuck:FA sts: %d, data: %d!\n"}, + {MSG_8852B_ERRHDL_7, "=>DmaTopStuck:FA!\n"}, + {MSG_8852B_ERRHDL_8, "=>DmaTopStuck:know!\n"}, + {MSG_8852B_ERRHDL_9, "=>RecoveryCMAC!\n"}, + {MSG_8852B_ERRHDL_10, "[ERR]BBRPT CHIF\n"}, + {MSG_8852B_ERRHDL_11, "[ERR]Check CMAC_idle\n"}, + {MSG_8852B_ERRHDL_12, "[ERR]PTCL tx\n"}, + {MSG_8852B_ERRHDL_13, "[ERR]L0 promote event %x\n"}, + {MSG_8852B_ERRHDL_14, "[ERR][C2H]Previous: %x; Current: %x\n"}, + {MSG_8852B_ERRHDL_15, "ErrHDL in!\n"}, + {MSG_8852B_ERRHDL_16, "ErrHDL out!\n"}, + {MSG_8852B_ERRHDL_17, "DMAC error: %x\n"}, + {MSG_8852B_ERRHDL_18, "CMAC0 error: %x\n"}, + {MSG_8852B_ERRHDL_19, "CMAC1 error: %x\n"}, + {MSG_8852B_ERRHDL_20, "notify: %x\n"}, + {MSG_8852B_ERRHDL_21, "--->\n err=%x\n"}, + {MSG_8852B_ERRHDL_22, "R_AX_SER_DBG_INFO =%x\n"}, + {MSG_8852B_ERRHDL_23, "R_AX_DMAC_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_24, "R_AX_WDE_ERR_FLAG_CFG_NUM1 =%x\n"}, + {MSG_8852B_ERRHDL_25, "R_AX_PLE_ERR_FLAG_CFG_NUM1 =%x\n"}, + {MSG_8852B_ERRHDL_26, "R_AX_WDRLS_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_27, "R_AX_WDRLS_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_28, "R_AX_RPQ_RXBD_IDX =%x\n"}, + {MSG_8852B_ERRHDL_29, "R_AX_SEC_DEBUG =%x\n"}, + {MSG_8852B_ERRHDL_30, "R_AX_MPDU_TX_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_31, "R_AX_MPDU_TX_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_32, "R_AX_MPDU_RX_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_33, "R_AX_MPDU_RX_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_34, "R_AX_STA_SCHEDULER_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_35, "R_AX_STA_SCHEDULER_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_36, "R_AX_WDE_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_37, "R_AX_WDE_ERR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_38, "R_AX_PLE_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_39, "R_AX_PLE_ERR_FLAG_ISR=%x\n"}, + {MSG_8852B_ERRHDL_40, "R_AX_TXPKTCTL_ERR_IMR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_41, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=%x\n"}, + {MSG_8852B_ERRHDL_42, "R_AX_PKTIN_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_43, "R_AX_PKTIN_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_44, "R_AX_PKTIN_ERR_IMR =%x "}, + {MSG_8852B_ERRHDL_45, "R_AX_PKTIN_ERR_ISR =%x\n"}, + {MSG_8852B_ERRHDL_46, "R_AX_HOST_DISPATCHER_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_47, "R_AX_HOST_DISPATCHER_ERR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_48, "R_AX_CPU_DISPATCHER_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_49, "R_AX_CPU_DISPATCHER_ERR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_50, "R_AX_CPUIO_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_51, "R_AX_CPUIO_ERR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_52, "R_AX_BBRPT_COM_ERR_IMR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_53, "0xC164=%x\n"}, + {MSG_8852B_ERRHDL_54, "R_AX_SCHEDULE_ERR_IMR=%x "}, + {MSG_8852B_ERRHDL_55, "R_AX_SCHEDULE_ERR_ISR=%x\n"}, + {MSG_8852B_ERRHDL_56, "R_AX_PTCL_IMR0=%x "}, + {MSG_8852B_ERRHDL_57, "R_AX_PTCL_ISR0=%x\n"}, + {MSG_8852B_ERRHDL_58, "R_AX_DLE_CTRL=%x\n"}, + {MSG_8852B_ERRHDL_59, "R_AX_PHYINFO_ERR_IMR=%x\n"}, + {MSG_8852B_ERRHDL_60, "R_AX_TXPWR_IMR= N/A "}, + {MSG_8852B_ERRHDL_61, "R_AX_TXPWR_ISR= N/A\n"}, + {MSG_8852B_ERRHDL_62, "R_AX_DBGSEL_TRXPTCL=%x "}, + {MSG_8852B_ERRHDL_63, "R_AX_PHYINFO_ERR_IMR=%x\n"}, + {MSG_8852B_ERRHDL_64, "R_AX_TMAC_ERR_IMR_ISR=%x "}, + {MSG_8852B_ERRHDL_65, "R_AX_DBGSEL_TRXPTCL=%x\n"}, + {MSG_8852B_ERRHDL_66, "<---\n"}, + {MSG_8852B_MAIN_00, "SW Queue reCreate\n"}, + {MSG_8852B_MAIN_01, "Enter AXIDMA_init... \n"}, + {MSG_8852B_MAIN_02, "WDT_timer start... \n"}, + {MSG_8852B_MAIN_03, "InitHWPostDLRAM done\n"}, + {MSG_8852B_MAIN_04, "InitFWFuncPostDL RAM done\n"}, + {MSG_8852B_MAIN_05, "MAC per STAInfo %d bytes\n"}, + {MSG_8852B_MAIN_06, "BB per STAInfo %d bytes\n"}, + {MSG_8852B_MAIN_07, "InitWLANFuncRAM done\n"}, + {MSG_8852B_MAIN_08, "Enter test id (0~7): "}, + {MSG_8852B_MAIN_09, "%c\n"}, + {MSG_8852B_MAIN_10, "Thread Metric: %d\n"}, + {MSG_8852B_MAIN_11, "Test duration: %d seconds\n"}, + {MSG_8852B_MAIN_14, "WDT_timer start fail \n"}, + {MSG_8852B_MAIN_15, " SysMib.PInternal->PDebugInfo->DbgLvl =%x\n"}, + {MSG_8852B_MAIN_16, "Enter flash FW loader\n"}, + {MSG_8852B_IRAMENTRY_00, "Function ptr length :RAM %x,ROM %x\n"}, + {MSG_8852B_IRAMENTRY_01, "Function ptr length not equal!!\n"}, + {MSG_8852B_IRAMENTRY_02, "Start Init PLE memory\n"}, + {MSG_8852B_IRAMENTRY_03, "PLE data check error!!!"}, + {MSG_8852B_IRAMENTRY_04, "PLE usage :%x\n"}, + {MSG_8852B_IRAMENTRY_05, "Initializing RAM bss ...\n"}, + {MSG_8852B_IRAMENTRY_06, "_BSS_RAM_START_ : %x\t _BSS_RAM_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_07, "B cut\n"}, + {MSG_8852B_IRAMENTRY_08, "_RAM_FUNCPTR_START_ : %x\t _RAM_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_09, "_ROM_FUNCPTR_START_ : %x\t _ROM_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_10, "C cut\n"}, + {MSG_8852B_IRAMENTRY_11, "_RAM_CCUT_FUNCPTR_START_ : %x\t _RAM_CCUT_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_12, "_ROM_CCUT_FUNCPTR_START_ : %x\t _ROM_CCUT_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_13, "D cut\n"}, + {MSG_8852B_IRAMENTRY_14, "_RAM_DCUT_FUNCPTR_START_ : %x\t _RAM_DCUT_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_15, "_ROM_DCUT_FUNCPTR_START_ : %x\t _ROM_DCUT_FUNCPTR_END_ : %x\n"}, + {MSG_8852B_IRAMENTRY_16, "Load FW RAM code OK\n"}, + {MSG_8852B_BACKTRACE_00, "Heap space is not enough for backtrace.......\n"}, + {MSG_8852B_BACKTRACE_01, "Backtrace......\n"}, + {MSG_8852B_BACKTRACE_02, "Next SP:%x, Next RA:%x\n"}, + {MSG_8852B_BACKTRACE_03, "Backtrace is failed\n"}, + {MSG_8852B_BACKTRACE_04, "Done\n"}, + {MSG_8852B_BACKTRACE_05, "EPC: %x, Cause: %x, BADVADDR: %x, Status: %x\n"}, + {MSG_8852B_BACKTRACE_06, "hi: %x, lo: %x, ra: %x, fp: %x\n"}, + {MSG_8852B_BACKTRACE_07, "sp: %x, gp: %x, t9: %x, t8: %x\n"}, + {MSG_8852B_BACKTRACE_08, "s7: %x, s6: %x, s5: %x, s4: %x\n"}, + {MSG_8852B_BACKTRACE_09, "s3: %x, s2: %x, s1: %x, s0: %x\n"}, + {MSG_8852B_BACKTRACE_10, "t7: %x, t6: %x, t5: %x, t4: %x\n"}, + {MSG_8852B_BACKTRACE_11, "t3: %x, t2: %x, t1: %x, t0: %x\n"}, + {MSG_8852B_BACKTRACE_12, "a3: %x, a2: %x, a1: %x, a0: %x\n"}, + {MSG_8852B_BACKTRACE_13, "v1: %x, v0: %x, at: %x\n"}, + {MSG_8852B_BACKTRACE_14, "not send c2hHalt\n"}, + {MSG_8852B_BACKTRACE_15, "no loop\n"}, + {MSG_8852B_BACKTRACE_16, "Something wrong when allocating backtrace memory\n"}, + {MSG_8852B_BACKTRACE_17, "Backtrace memory is full!!\n"}, + {MSG_8852B_BACKTRACE_18, "Init Backtrace Memory failed\n"}, + {MSG_8852B_PSTIMER_00, "handle task:%x\n"}, + {MSG_8852B_PSTIMER_01, "handle tsf: %x\n"}, + {MSG_8852B_PSTIMER_02, "tsf in list: %x\n"}, + {MSG_8852B_AXIDMA_00, "[ERR] AXIDMA is not idle!\n"}, + {MSG_8852B_AXIDMA_01, "[ERR] AXIDMA is not enable\n"}, + {MSG_8852B_AXIDMA_02, "[AXIDMA RX Init]Allocate H2C buffer fail 123\n"}, + {MSG_8852B_AXIDMA_03, "[AXIDMA RX Init]Allocate PKT buffer fail\n"}, + {MSG_8852B_AXIDMA_04, "[AXIDMA RX Init]Allocate RPT buffer fail\n"}, + {MSG_8852B_PORT_00, "Assert at file: %s, line: %u\n"}, + {MSG_8852B_PORT_01, "not send c2hHalt\n"}, + {MSG_8852B_PORT_02, "no loop\n"}, + {MSG_8852B_PORT_03, "Watch dog timeout in critical section\n"}, + {MSG_8852B_PORT_04, "Watch dog remain: %d(us)\n"}, + {MSG_8852B_PORT_05, "Exec Time %x ~ %x: %d(us)\n"}, + {MSG_8852B_RXI300_00, "EPC Value: %x\n"}, + {MSG_8852B_RXI300_01, "Error id is inexistent(%x)!\n"}, + {MSG_8852B_RXI300_02, "Error code is inexistent(%x)!\n"}, + {MSG_8852B_RXI300_03, "RXI300_ERR_SRC_APB_DEF_SLV"}, + {MSG_8852B_RXI300_04, "RXI300_ERR_SRC_AXI_APB_SA"}, + {MSG_8852B_RXI300_05, "Error source is inexistent(%x)!\n"}, + {MSG_8852B_RXI300_06, "HaltC2H = %x, Error address = %x!\n"}, + {MSG_8852B_RXI300_07, "Clear interrupt fail!\n"}, + {MSG_8852B_RXI300_08, "RA/SP Value: %x, %x\n"}, + {MSG_8852B_PS_CHK_PLATFORM_ERR_1, "DMAC error: %x\n"}, + {MSG_8852B_PS_CHK_PLATFORM_ERR_2, "CMAC%d error: %x\n"}, + {MSG_8852B_PS_DDMA_BUFFER_SIZE_OVERFLOW, "MAC%d DDMA buffer size (%x) is overflow!\n"}, + {MSG_8852B_PS_HIOE_START_ADDR, "LPS HIOE start address = %x, size = %x\n"}, + {MSG_8852B_PS_HIOE_END_ADDR, "LPS HIOE end address = %x\n"}, + {MSG_8852B_PS_HIOE_INST_OVERFLOW, "LPS HIOE instruction is overflow! inst_size(%x).\n"}, + {MSG_8852B_PS_HIOE_READ_PCIEMIO_FAIL, "[Err] ReadPCIEMIO Fail! reg = %x\n"}, + {MSG_8852B_PS_HIOE_WRITE_PCIEMIO_FAIL, "[Err] WritePCIEMIO Fail! reg = %x\n"}, + {MSG_8852B_PS_HIOE_BACKUP_FAIL, "BKP fail st.(%x)\n"}, + {MSG_8852B_PS_HIOE_RESTORE_FAIL, "RES fail st.(%x)\n"}, + {MSG_8852B_PS_HIOE_INVALID_STATE, "Invalid st.(%x)\n"}, + {MSG_8852B_PS_HIOE_BACKUP_TIMEOUT, "Bkp (%d) polling timeout!\n"}, + {MSG_8852B_PS_HIOE_RESTORE_TIMEOUT, "Res polling timeout!\n"}, + {MSG_8852B_PS_ENTER_32K, ">C\n"}, + {MSG_8852B_PS_LEAVE_32K, "\n"}, + {MSG_8852B_PS_OPEN_RF, "<\n"}, + {MSG_8852B_PS_GRANT_WLAN_FAIL, "[PDCK] GNT WL FAIL!!\n"}, + {MSG_8852B_PS_PDCK_CAL_FAIL, "PDCK CAL FAIL!!\n"}, + {MSG_8852B_PS_ANACLK_CAL_FAIL, "ANACLK CAL FAIL!!\n"}, + {MSG_8852B_PS_EN_RX_NORMAL_MODE_FAIL, "RF is OFF. EnRxNormMode FAIL!\n"}, + {MSG_8852B_PS_EN_RX_NORMAL_MODE, "1->2"}, + {MSG_8852B_PS_SET_RF_OFF_PERMISSION, "SetRfOffPermission: PhyRfOffPermission[%d]=%d\n"}, + {MSG_8852B_PS_SET_32K_PERMISSION, "Set32KandPGPermission. 32K(%d), PG(%d)\n"}, + {MSG_8852B_PS_ENABLE_LPS_FW_TEST, "Enable LPS FW test. Target LPS number (%x)\n"}, + {MSG_8852B_PS_WAKE_BAR_PULL, "[RF OFF] Wake bar is pulled\n"}, + {MSG_8852B_PS_RX_FAIL_KEEP_RF_ON, "[RF OFF] Rx FAIL! keep RF on.\n"}, + {MSG_8852B_PS_CHECK_RF_CONDITION_FAIL, "Check RF OFF condition FAIL (%d)\n"}, + {MSG_8852B_PS_TX_NULL_FAIL, "[Error] Cannot tx null%d\n"}, + {MSG_8852B_PS_CREATE_ROLE_FAIL, "[FAIL] Create Role fail!\n"}, + {MSG_8852B_PS_ALREADY_IN_PS_MODE, "[Error] Already in LPS/WMM PS (%x)!!\n"}, + {MSG_8852B_PS_SET_POWER_MODE_1, "MAC ID = %d, PS Mode = %d, RLBM = %d\n"}, + {MSG_8852B_PS_SET_POWER_MODE_2, "Smart PS = %d, Awake Interval = %d, Last RPWM = %d\n"}, + {MSG_8852B_PS_BEACON_EARLY, "E\n"}, + {MSG_8852B_PS_RX_BEACON, "R\n"}, + {MSG_8852B_PS_RX_BEACON_NO_HIT, "N\n"}, + {MSG_8852B_PS_INVALID_BEACON_REPORT, "[Error] Does not receive BCN Parser Rpt\n"}, + {MSG_8852B_PS_KEEP_RF_ON, "Keep ON\n"}, + {MSG_8852B_PS_ENABLE_BEACON_TIMEOUT_TIMER_FAIL, "EnBcnTimeOutCount fail!!\n"}, + {MSG_8852B_PS_TIMER_VALUE_NOT_INIT, "Timer (%d) val is not init!! role_idx(%d)\n"}, + {MSG_8852B_PS_CREATE_TIMER_FAIL, "Create timer (%d) fail!! role_idx(%d)\n"}, + {MSG_8852B_PS_SEND_NULL_FAIL_RESULT, "TxNull %d FAIL! ret_type(%d), result(%d)\n"}, + {MSG_8852B_PS_INVALID_POWER_BIT, "[PsSendNullCb] invalid pwr_bit(%d)\n"}, + {MSG_8852B_PS_INIT_PS_PARAMETER, "InitPSParm, role_idx=%d\n"}, + {MSG_8852B_PS_S2_CONDITION_MISMATCH, "[ChkS2 no match] Condition(%d), LpsDbgInfo = 0x%x\n"}, + {MSG_8852B_PS_S4_CONDITION_MISMATCH, "[ChkS4 no match] Condition(%d), LpsDbgInfo = 0x%x\n"}, + {MSG_8852B_PS_CHANGE_PS_STATE, "[ChangePSStateByRPWM] REQ State: %d, Cur State: %d\n"}, + {MSG_8852B_PS_SET_POWER_MODE_ROLE_NOT_EXIST, "Role not exist! Condition (%d)\n"}, + {MSG_8852B_PS_SET_TBTT_AGG_NUM, "Step(%d), SetTbttAggNum(%d).\n"}, + {MSG_8852B_PS_RX_BEACON_TIMEOUT, "PsBcnTimeOut\n"}, + {MSG_8852B_PS_SET_POWER_STATE, "CURRENT_PS_STATE: %d, LASTRPWM: %d\n"}, + {MSG_8852B_PS_RESET_PS_PARAMETER, "ResetPSParm\n"}, + {MSG_8852B_PS_ACTIVATE_SETTING, "ActiveSetting\n"}, + {MSG_8852B_PS_SEND_NULL_RESULT, "[PsSendNullCb] type(%d), result(%d)\n"}, + {MSG_8852B_PACKET_TX_NOT_ENABLE, "[ERR]MGQ1 Txen = 0, TXEN(0xC348)=%x\n"}, + {MSG_8852B_PACKET_MACID_SLEEP, "MACID_SLEEP_0(0xC2C0)=%x\n"}, + {MSG_8852B_PACKET_TX_NULL, "Null %d\n"}, + {MSG_8852B_PACKET_SEND_NULL_FAIL, "Send NULL FAIL! ret_type(%d), ret_result(%d).\n"}, + {MSG_8852B_PACKET_INVALID_POWER_BIT, "Send NULL with invalid type(%d)!.\n"}, + {MSG_8852B_PACKET_NULL_PKTID_NOT_EXIST, "Null PKTID No Exist!!\n"}, + {MSG_8852B_PACKET_NULL_READ_PKT_OFFLOAD_FAIL, "[IssueNull]ReadFWOfldPKT FAIL!!\n"}, + {MSG_8852B_PACKET_NULL_PKT_OFFLOAD, "Null ID=%d, pkt_len=%d, ppkt_content=%x\n"}, + {MSG_8852B_PACKET_PROBE_REQ_PKTID_NOT_EXIST, "Probe req PKTID No Exist!!\n"}, + {MSG_8852B_PACKET_PROBE_REQ_READ_PKT_OFFLOAD_FAIL, "[IssueProbeReq]ReadFWOfldPKT FAIL!!\n"}, + {MSG_8852B_WOWLAN_1, "H2C wowlan, fun: %x"}, + {MSG_8852B_WOWLAN_2, "H2C Keep Alive, Enable: %x\n"}, + {MSG_8852B_WOWLAN_3, "H2C disconn, Enable: %x\n"}, + {MSG_8852B_WOWLAN_4, "Wow stop AXIDMA failed\n"}, + {MSG_8852B_WOWLAN_5, "H2C wow global, Enable: %x\n"}, + {MSG_8852B_WOWLAN_6, "H2C wakeup ctrl, pattern match Enable: %x\n"}, + {MSG_8852B_WOWLAN_7, "H2C , nlo Enable: %x\n"}, + {MSG_8852B_WOWLAN_8, "H2C , wow cam: %x\n"}, + {MSG_8852B_WOWLAN_9, "\nAppendTkipMICComm\n"}, + {MSG_8852B_WOWLAN_10, "key[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_11, "DA[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_12, "SA[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_13, "Priority[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_14, "data[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_15, "miccode[%d]=%bx\n"}, + {MSG_8852B_WOWLAN_16, "get 1st rx pktid fail\n"}, + {MSG_8852B_WOWLAN_17, "(%d, %d) Parsed Failed!\n"}, + {MSG_8852B_WOWLAN_18, "Magic Packet Parsed Done, reason_bits<%x>\n"}, + {MSG_8852B_WOWLAN_19, "H2C , arp ofld Enable: %x\n"}, + {MSG_8852B_WOWLAN_20, "Unexpected HCI type in togglewake\n"}, + {MSG_8852B_BEACON_1, "req bcn mem err\n"}, + {MSG_8852B_BEACON_2, "CPUIO rls bcn pld fail\n"}, + {MSG_8852B_BEACON_3, "req bcn wp err %d\n"}, + {MSG_8852B_BEACON_4, "bcnq lock fail\n"}, + {MSG_8852B_BEACON_5, "CPUIO deq bcn fail\n"}, + {MSG_8852B_BEACON_6, "bcn req wd fail %d\n"}, + {MSG_8852B_BEACON_7, "enq bcn fail %d\n"}, + {MSG_8852B_PPS_00, "B%d pps%d already enable\n"}, + {MSG_8852B_PPS_01, "B%d pps%d already disable\n"}, + {MSG_8852B_PPS_02, "B%d pps%d reg already enable\n"}, + {MSG_8852B_PPS_03, "B%d pps%d reg already disable\n"}, + {MSG_8852B_PPS_04, "invalid pps band %d\n"}, + {MSG_8852B_PPS_05, "B%d pps%d is not enable yet\n"}, + {MSG_8852B_PPS_06, "B%d pps%d pof%d already enable\n"}, + {MSG_8852B_PPS_07, "B%d pps%d pof%d already disable\n"}, + {MSG_8852B_PPS_08, "B%d pps%d pof%d reg already enable\n"}, + {MSG_8852B_PPS_09, "B%d pps%d pof%d reg already disable\n"}, + {MSG_8852B_PPS_10, "B%d pps%d pof%d running\n"}, + {MSG_8852B_PPS_11, "pps no param ptr %d\n"}, + {MSG_8852B_PPS_12, "invalid pps port %d\n"}, + {MSG_8852B_PPS_13, "no valid pps id\n"}, + {MSG_8852B_PPS_14, "pps is already running\n"}, + {MSG_8852B_PS_TX_REQ, "PsTxReq. role(%d), feature(%d), en(%d)\n"}, + {MSG_8852B_PS_TX_REQ_DUPLICATED_DISABLE, "[ERROR] role(%d), feature(%d) Tx has been disabled!\n"}, + {MSG_8852B_CHSW_00, "[ChSw] Channel Switch Fail. (ctrl_bw_ch return false)\n"}, + {MSG_8852B_P2P_00, "[P2P]no act info ptr\n"}, + {MSG_8852B_P2P_01, "[P2P]act h2c init Role idx srch fail macid %d\n"}, + {MSG_8852B_P2P_02, "[P2P]set pps param fail %d\n"}, + {MSG_8852B_P2P_03, "[P2P]B%d pps%d en%d fail %d\n"}, + {MSG_8852B_P2P_04, "[P2P]B%d pps%d pof%d en%d fail %d\n"}, + {MSG_8852B_P2P_05, "[P2P]set pof param fail %d\n"}, + {MSG_8852B_P2P_06, "[P2P]B%d P2P%d noa%d already disable\n"}, + {MSG_8852B_P2P_07, "[P2P]B%d P2P%d has no running NoA sch\n"}, + {MSG_8852B_P2P_08, "[P2P]no content ptr\n"}, + {MSG_8852B_P2P_09, "[P2P]act h2c p2p%d over max\n"}, + {MSG_8852B_P2P_10, "[P2P]act h2c noa%d over max\n"}, + {MSG_8852B_P2P_11, "[P2P]p2p%d already running\n"}, + {MSG_8852B_P2P_12, "[P2P]p2p%d not init yet\n"}, + {MSG_8852B_P2P_13, "[P2P]act h2c init fail %d\n"}, + {MSG_8852B_P2P_14, "[P2P]act h2c upd sch fail %d\n"}, + {MSG_8852B_P2P_15, "[P2P]act h2c rm sch fail %d\n"}, + {MSG_8852B_P2P_16, "[P2P]act h2c term fail %d\n"}, + {MSG_8852B_P2P_17, "[P2P]illegal act h2c %d\n"}, + {MSG_8852B_P2P_18, "[P2P] macid ctrl h2c p2p id %d over max\n"}, + {MSG_8852B_P2P_19, "[P2P]macid ctrl type %d invalid\n"}, + {MSG_8852B_P2P_20, "[P2P]no p2p info ptr\n"}, + {MSG_8852B_P2P_21, "[P2P]P2P%d clear MACID ctrl all fail %d\n"}, + {MSG_8852B_P2P_22, "[P2P]H2C Act fail %d\n"}, + {MSG_8852B_P2P_23, "[P2P]H2C MACID ctrl fail %d\n"}, + {MSG_8852B_NULL_RESULT, "TxNull %d result(%d)!!!\n"}, + {MSG_8852B_PS_CREATE_TIMER_DUPLICATED, "[ERR][LPS] Create timer (%d) is existed!! role_idx(%d)\n"}, + {MSG_8852B_PS_DELETE_TIMER_FAIL, "[ERR][LPS] Delete timer (%d) FAIL!! role_idx(%d)\n"}, + {MSG_8852B_PS_DELETE_TIMER_NOT_EXIST, "[ERR][LPS] Delete timer (%d) is not existed!! role_idx(%d)\n"}, + {MSG_8852B_PS_DTIM_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) DTIM timer is not existed!! role_idx(%d)\n"}, + {MSG_8852B_PS_BCN_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) BCN timer is not existed!! role_idx(%d)\n"}, + {MSG_8852B_PS_TRX_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) TRX timer is not existed!! role_idx(%d)\n"}, + {MSG_8852B_PS_ENABLE_DTIM_TIMEOUT_TIMER_FAIL, "[ERR][LPS] EnDTIMTimeOutCountComm FAIL!!\n"}, + {MSG_8852B_PS_ENABLE_TRX_TIMEOUT_TIMER_FAIL, "[ERR][LPS] EnTRXTimeOutCount FAIL!!\n"}, + {MSG_8852B_PS_DRFC_RESTORE_FAIL, "[ERR][LPS] Restore DRFC FAIL!! RF mode (%d)\n"}, + {MSG_8852B_PS_S2TOS4_TX_BUSY, "[WARN][LPS][S2ToS4State] Macid TX busy, role_idx(%d)\n"}, + {MSG_8852B_RPWM_SEQ_MISMATCH, "[ERR] RPWM Seq Num mismatch!\n"}, + {MSG_8852B_RPWM_REQ_STATE_INVALID, "[ERR] Req Pwr state (%d) is invalid!\n"}, + {MSG_8852B_READ_RPWM, "Read RPWM = %x\n"}, + {MSG_8852B_WRITE_CPWM, "LDM = %x, cpwm_val = %x, CPWM = %x\n"}, + {MSG_8852B_TASK_ERROR, "Task Error: %wx\n"}, + {MSG_8852B_GETMEDIASTS_1, "GetMediaStatusbyMacid fail, macid = %bx!\n"}, + {MSG_8852B_SETMEDIASTS_1, "SetMediaStatusbyMacid: macid number >= 32, macid = %bx!\n"}, + {MSG_8852B_SETMEDIASTS_2, "SetMediaStatusbyMacid: Role_idx error, macid = %bx, role_idx = %bx!\n"}, + {MSG_8852B_IPS_SET_CFG_ROLE_NOT_EXIST, "[SetIpsCfg] role is not existed\n"}, + {MSG_8852B_IPS_SET_CFG_DUPLICATE_ENABLE, "[SetIpsCfg] IPS is already enabled! role_idx(%d)\n"}, + {MSG_8852B_IPS_SET_CFG, "[SetIpsCfg] macid(%d), Enable(%d)\n"}, + {MSG_8852B_IPS_CHK_I1_COND_MATCH_1, "=>ChkI1ConditionMatch\n"}, + {MSG_8852B_IPS_CHK_I1_COND_MATCH_2, "[ChkI1 no match] IpsDbgInfo = 0x%x\n"}, + {MSG_8852B_IPS_CHANGE_IPS_STATE_INVALID_REQ_STATE, "[ChangeIpsState] Invalid req_state = %d\n"}, + {MSG_8852B_IPS_CHANGE_STATE_BY_CONDITION, "[ChangeIPSStateByCondition] REQ State: %d, Cur State: %d\n"}, + {MSG_8852B_PS_TRX_REQ_ROLE_NOT_EXIST, "[ERR] [PsTRxReq] role(%d) is not existed!\n"}, + {MSG_8852B_PS_TRX_REQ, "[PsTRxReq] %d. role(%d), feature(%d), en(%d)\n"}, + {MSG_8852B_PS_TRX_REQ_DISABLE_ERR, "[ERR] [PsTRxReq] %d. role(%d), feature(%d) Tx has been disabled!\n"}, + {MSG_8852B_ROLE_22, "[FAIL] Role info - IpsParm alloc fail!\n"}, + {MSG_8852B_OUTSRC_START, " out source delimiter start"}, + {MSG_8852B_OUTSRC_BB_SURA_0, "[RA]RateChange=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_1, "[RA]RDth=0x%x,RUth=0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_2, "[RA]r4=100\n"}, + {MSG_8852B_OUTSRC_BB_SURA_3, "[RA]ForceRD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_4, "[RA]RDCnt=0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_5, "[RA]RUCnt=0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_6, "[RA]RS\n"}, + {MSG_8852B_OUTSRC_BB_SURA_7, "[RA]SGIRD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_8, "[RA]BWRD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_9, "[RA]RDToLowest1\n"}, + {MSG_8852B_OUTSRC_BB_SURA_10, "[RA]RDToLowest2\n"}, + {MSG_8852B_OUTSRC_BB_SURA_11, "[RA]RD:crate=0x%x,mrate0=0x%x,mrate1=0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_12, "[RA]rate=0x%x,bw:0x%x,rate2=0x%x,bw2:0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_13, "[RA]Hit:bw=0x%x->0x%x,rate=0x%x->0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_14, "[RA]SR:rate0=0x%x,rate1=0x%x,rate2=0x%x,cnt=0x%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_15, "RSVD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_16, "[RA]SGIRU\n"}, + {MSG_8852B_OUTSRC_BB_SURA_17, "[RA]BWRU\n"}, + {MSG_8852B_OUTSRC_BB_SURA_18, "[RA]RUbw++\n"}, + {MSG_8852B_OUTSRC_BB_SURA_19, "[RA]RUToHighest\n"}, + {MSG_8852B_OUTSRC_BB_SURA_20, "[RA]NoUpRate\n"}, + {MSG_8852B_OUTSRC_BB_SURA_21, "[RA]RU:crate=%x,mrate0=%x,mrate1=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_22, "[RA,W]macid:%x,mode:%x,rate_idx:%x,mcs:%x,ss:%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_23, "[RA][TRY]PER=%x,RDR=%x,R4=%x, pre_tp=%d, next_tp=%d\n"}, + {MSG_8852B_OUTSRC_BB_SURA_24, "[RA][TRY]R4=100,cnt=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_25, "[RA][TRY]rate=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_26, "[RA]TryFail\n"}, + {MSG_8852B_OUTSRC_BB_SURA_27, "[RA]TrySuccess\n"}, + {MSG_8852B_OUTSRC_BB_SURA_28, "[RA]MtTryIdx=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_29, "[RA]TryFailCnt=%x,rate=%x,bw=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_30, "[RA]DrvFixRate\n"}, + {MSG_8852B_OUTSRC_BB_SURA_31, "[RA]POLLUTED\n"}, + {MSG_8852B_OUTSRC_BB_SURA_32, "[RA]Tot=0\n"}, + {MSG_8852B_OUTSRC_BB_SURA_33, "[RA]Tx=0,Tot:%x,Ok:%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_34, "[RA]StaNull\n"}, + {MSG_8852B_OUTSRC_BB_SURA_35, "[RA]NoHESU\n"}, + {MSG_8852B_OUTSRC_BB_SURA_36, "[RA]WDNoRelease\n"}, + {MSG_8852B_OUTSRC_BB_SURA_37, "[RA]TxRptTot=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_38, "[RA]Ovfl\n"}, + {MSG_8852B_OUTSRC_BB_SURA_39, "RSVD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_40, "RSVD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_41, "RSVD\n"}, + {MSG_8852B_OUTSRC_BB_SURA_42, "[RA]1 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_43, "[RA]PER=%x,RDR=%x,r4=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_44, "[RA]2 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_45, "[RA]3 chk_rate_up_lmt OK: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_46, "[RA]rate_changed=%x @ rate_check_for_update\n"}, + {MSG_8852B_OUTSRC_BB_SURA_47, "[RA]chk rate exist: rate_idx=%x->%x (%x,%x,%x)\n"}, + {MSG_8852B_OUTSRC_BB_SURA_48, "[RA]chk_rate_up_lmt=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_49, "[RA]r_idx = %x => per_ma = %x, per_var == %x, decision_offset_n=%x, decision_offset_p=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_50, "[RA]UpFailLimitCnt:%x,m_rtae_up_fail_cnt_lmt:%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_51, "[RA][txrpt]Txcnt=%x, Try=%x, total=%x, OK=%x, Initrate,Giltf=%x,%x, Finalrate,Giltf=%x,%x, BW=%x,wd_not_released=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_52, "[RA][TBTT]ID=%x,Media:%x,Tot=%x,Ok=%x,OK=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_53, "[RA][TBTT][FWfixrate]ID=%x,Media:%x,Tot=%x,Ok=%x,a-OK%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_54, "[RA]Sgi_pending_cnt = %x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_55, "[RA][SGI]New rate = %x, Old gi = %x, New gi = %x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_56, "[RA][H2C]Mode_sel=%x, gi_ltf=%x, dcm_cap=%x, er_cap=%x, init_rate_lv=%x, ldpc_cap=%x, stbc_cap=%x, arfr_ctrl=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_57, "[RA][H2C]Initial_BW=%x, max_ss_support=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_58, "[RA][H2C]Ra_mask0=%x, ra_mask1=%x, highest_rate=%x, max_start_rate=%x, lowest_rate=%x\n"}, + {MSG_8852B_OUTSRC_BB_SURA_59, "[RA][H2C]Initrate: rateidx=%x, mode=%x, gi_ltf=%x, bw_idx=%x\n"}, + {MSG_8852B_OUTSRC_END, " out source delimiter end"}, + {MSG_8852B_LAST, "Please add your log above."}, +}; diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.h b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.h new file mode 100644 index 0000000..e808ac6 --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.h @@ -0,0 +1,724 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __HAL8852B_FW_LOG__ +#define __HAL8852B_FW_LOG__ +#include "../../type.h" + +enum LOG_MSG_8852B_TABLE { + MSG_8852B_FIRST = 0, //"RESERVED" + MSG_8852B_SAMPLE_NO_PARAMETER, //"Sample without parameter.\n" + MSG_8852B_SAMPLE_PARAMETER, //"Sample string:%s.\n" + MSG_8852B_SAMPLE_INTEGER, //"Sample integer:%d.\n" + MSG_8852B_SAMPLE_INTEGER_X, //"Sample integer:0x%x.\n" + MSG_8852B_SAMPLE_INTEGER_2, //"Sample integer1:%d, integer2:%d.\n" + MSG_8852B_FCUN_NAME, //"%s()\n" + MSG_8852B_MAIN_1, //"FW from host\n" + MSG_8852B_MAIN_2, //"Skip DL FW handler\n" + MSG_8852B_MAIN_3, //"FW from flash\n" + MSG_8852B_MAIN_4, //"Invalid boot mode\n" + MSG_8852B_FWDLHDL_1, //"Invalid boot reason\n" + MSG_8852B_FWDLHDL_2, //"Enter DL FW handler\n" + MSG_8852B_FWDLHDL_3, //"FWHDR H2C done\n" + MSG_8852B_FLASHBOOT, //"Enter flash FW loader\n" + MSG_8852B_IRAMENTRN, //"Load FW RAM code OK\n" + MSG_8852B_FIRSTH2C_1, //"First H2C Enqueue\n" + MSG_8852B_FIRSTH2C_2, //"H2C node malloc fail\n" + MSG_8852B_FIRSTH2C_3, //"H2C node content malloc fail\n" + MSG_8852B_H2CDEQ_1, //"H2C Dequeue\n" + MSG_8852B_H2CDEQ_2, //"H2CPKT enqueue fail\n" + MSG_8852B_H2CPKT_1, //"content = 0x%x 0x%x 0x%x 0x%x\n" + MSG_8852B_RESERVED_ROM, //"RESERVED" + MSG_8852B_CMDTABLE_NAME, //"%s " + MSG_8852B_CMDTABLE_1, //" ?\n" + MSG_8852B_CMDTABLE_2, //" dump bytes, ex: DB 0xb8e00000\n" + MSG_8852B_CMDTABLE_3, //" write bytes, ex: EB 0xb8e00000 0x1\n" + MSG_8852B_CMDTABLE_4, //" dump words, ex: DW 0xb8e00000\n" + MSG_8852B_CMDTABLE_5, //" write words, ex: EW 0xb8e00000, 0x12345678\n" + MSG_8852B_CMDTABLE_6, //" jump to address, ex: j 0xb8900000\n" + MSG_8852B_CMDTABLE_7, //" set debug level\n" + MSG_8852B_CMDTABLE_8, //" set debug compoment bitmap\n" + MSG_8852B_CMDTABLE_9, //" show task info\n" + MSG_8852B_CMDTABLE_10, //" show heap info\n" + MSG_8852B_CMDTABLE_11, //" show dynamic allocate memory info, , \n" + MSG_8852B_CMDTABLE_12, //" show task time state\n" + MSG_8852B_CMDTABLE_13, //" AXIDMA test\n" + MSG_8852B_CMDTABLE_14, //" SPIC test\n" + MSG_8852B_CMDTABLE_15, //" IDDMA test\n" + MSG_8852B_CMDTABLE_16, //" RXI300 test\n" + MSG_8852B_CMDTABLE_17, //" DLE test\n" + MSG_8852B_CMDTABLE_18, //" HIOE test\n" + MSG_8852B_CMDTABLE_19, //" RPT test\n" + MSG_8852B_CMDTABLE_20, //" MISC test\n" + MSG_8852B_CMDTABLE_21, //" Update STA para for F2PTXCMD\n" + MSG_8852B_CMDTABLE_22, //" Update Common para for F2PTXCMD\n" + MSG_8852B_CMDTABLE_23, //" Wlan Flow Test\n" + MSG_8852B_CMDTABLE_24, //" Wlan Test Mode Setting\n" + MSG_8852B_CMDTABLE_25, //" Wlan Flow with RUA Test\n" + MSG_8852B_CMDTABLE_26, //" Wlan UL Flow Test\n" + MSG_8852B_CMDTABLE_27, //" IPSec test\n" + MSG_8852B_CMDTABLE_28, //" CryptoSig test\n" + MSG_8852B_CMDTABLE_29, //" SecureBoot test\n" + MSG_8852B_CMDTABLE_30, //" Secure eFuse R/W test\n" + MSG_8852B_CMDTABLE_31, //" Plat test\n" + MSG_8852B_CMDTABLE_32, //" H2C/C2H test\n" + MSG_8852B_CMDTABLE_33, //" UL F2PCMD test, , , 0\n" + MSG_8852B_CMDTABLE_34, //" Sounding test\n" + MSG_8852B_CMDTABLE_35, //" security CAM test\n" + MSG_8852B_CMDTABLE_36, //" Gtimer test, , , , \n" + MSG_8852B_CMDTABLE_37, //" PStimer test, , , , (valid if mode = 0)\n" + MSG_8852B_CMDTABLE_38, //" RPWM test\n" + MSG_8852B_CMDTABLE_39, //" DLTXD test\n" + MSG_8852B_CMDTABLE_40, //" PS test\n" + MSG_8852B_CMDTABLE_41, //" 32K CAL test\n" + MSG_8852B_CMDTABLE_42, //" WoW CAM test\n" + MSG_8852B_CMDTABLE_43, //" PS ONOFF test\n" + MSG_8852B_CMDTABLE_44, //" BTCoex test\n" + MSG_8852B_CMDTABLE_45, //" DL Parameters Setting\n" + MSG_8852B_CMDTABLE_46, //" Dump Wlan common info, f2pcmd result, decision result\n" + MSG_8852B_CMDTABLE_47, //" Dump Wlan sta or muru grp info\n" + MSG_8852B_CMDTABLE_48, //" Dump Wlan decision info\n" + MSG_8852B_CMDTABLE_49, //" Dump FW info\n" + MSG_8852B_CMDTABLE_50, //" TFDBG\n" + MSG_8852B_CMDTABLE_51, //" CRT\n" + MSG_8852B_MALLOC_F, //"malloc is failed\n" + MSG_8852B_STRING_0, //"%s\n" + MSG_8852B_STRING_1, //"%s" + MSG_8852B_PARA_INVALID, //"Invalid parameters\n" + MSG_8852B_CMD_UNKNOWN, //"Unknown cmd\n" + MSG_8852B_CONSOLE_1, //"- CMD -\n" + MSG_8852B_CONSOLE_2, //"0x%x: 0x%x\n" + MSG_8852B_CONSOLE_3, //"Jump to 0x%x\n" + MSG_8852B_CONSOLE_4, //"Set dbg level to: 0x%x\n" + MSG_8852B_CONSOLE_5, //"Set dbg component bitmap to: 0x%x\n" + MSG_8852B_CONSOLE_6, //"Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n" + MSG_8852B_CONSOLE_7, //"--------------------------------------------------------------------------------\n" + MSG_8852B_CONSOLE_8, //"Index\t\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n" + MSG_8852B_CONSOLE_9, //"------------------------------------------------------------------------\n" + MSG_8852B_CONSOLE_10, //"Address\t\tOwner ID\tFunction\tType\t\tSize(B)\n" + MSG_8852B_CONSOLE_11, //"Owner ID\tFunction\tType\t\tCounter\t\tTotalSize(B)\tHistorical High\n" + MSG_8852B_CONSOLE_12, //"------------------------------------------------------------------------------------------------\n" + MSG_8852B_CONSOLE_13, //"Owner ID\tType\t\tTotalSize(B)\n" + MSG_8852B_CONSOLE_14, //"------------------------------------------------\n" + MSG_8852B_MCC_SEARCHMACID_1, //"[MCC] pmcc_info is NULL!\n" + MSG_8852B_MCC_SEARCHMACID_2, //"[MCC] pgroup_list is empty!\n" + MSG_8852B_MCC_STATUSRPTHDL_1, //"[MCC] MCCStatusRptHDL macid: %d, group: %d, status: %d\n" + MSG_8852B_MCC_STATUSRPTHDL_2, //"[MCC] tsf: 0x%x 0x%x\n" + MSG_8852B_MCC_TBTTSTATUSRPTHDL, //"[MCC] B%dP%d TBTT TSF = 0x%x\n" + MSG_8852B_MCC_MACIDDROP, //"[MCC] MACIDTxIdleCheck fail\n" + MSG_8852B_MCC_ISSUENULLWOLPS_1, //"[MCC][%d][CXEVNT_ENULL]\n" + MSG_8852B_MCC_ISSUENULLWOLPS_2, //"[MCC] Issue null %d fail!!!\n" + MSG_8852B_MCC_ISSUENULL_1, //"[MCC] macid %d role not found\n" + MSG_8852B_MCC_ISSUENULL_2, //"[MCC][%d]Macid %d Null %d, TSF = 0x%x, freerun = 0x%x\n" + MSG_8852B_MCC_TXNULLCHK_1, //"[MCC] mcc group not found\n" + MSG_8852B_MCC_TXNULLCHK_2, //"[MCC] take semaphore fail!\n" + MSG_8852B_MCC_TXNULLCHK_3, //"[MCC][%d]Macid %d TxNull %d SUCCESS, freerun = 0x%x\n" + MSG_8852B_MCC_TXNULLCHK_4, //"[MCC][%d]Macid %d TxNull %d FAIL, freerun = 0x%x\n" + MSG_8852B_MCC_SENDNULLCB_1, //"[MCC][RPT] MACID DROP => macid (%d)\n" + MSG_8852B_MCC_SENDNULLCB_2, //"[MCC][RPT] LIFE DROP => macid (%d)\n" + MSG_8852B_MCC_SENDNULLCB_3, //"[MCC][RPT] invalid RPT (%d)\n" + MSG_8852B_MCC_SWITCHCH_1, //"[MCC] cfg ch FAIL!!!\n" + MSG_8852B_MCC_SWITCHCH_2, //"[MCC] CH SW, CH= %d\n" + MSG_8852B_MCC_SWITCHCH_3, //"[MCC] CH SW WARNING (%d)\n" + MSG_8852B_MCC_SWITCHCH_4, //"[MCC] RFK bypass\n" + MSG_8852B_MCC_CHANGEROLE_1, //"[MCC] MCCMacidDrop fail\n" + MSG_8852B_MCC_CHANGEROLE_2, //"[MCC](courtesy)macid %d => macid %d\n" + MSG_8852B_MCC_CHANGEROLE_3, //"[MCC][%d][CXEVNT_EBT]\n" + MSG_8852B_MCC_CHANGEROLE_4, //"[MCC][%d][CXEVNT_E5G]\n" + MSG_8852B_MCC_CHANGEROLE_5, //"[MCC][%d][CXEVNT_E2G]\n" + MSG_8852B_MCC_CHANGEROLE_6, //"[MCC][%d]Start BT TSF = 0x%x, freerun = 0x%x\n" + MSG_8852B_MCC_CHANGEROLE_7, //"[MCC][%d]Start macid %d TSF = 0x%x, freerun = 0x%x\n" + MSG_8852B_MCC_CHANGEROLE_8, //"[MCC] MCCMacidDropRel fail\n" + MSG_8852B_MCC_FIRSTDURATIONENDHDL_1, //"[MCC] First duration running\n" + MSG_8852B_MCC_FIRSTDURATIONENDHDL_2, //"[MCC][REP/STP] act: %d, deal with old schedule now...\n" + MSG_8852B_MCC_FIRSTDURATIONENDHDL_3, //"[MCC] MCCGroupStop fail\n" + MSG_8852B_MCC_FIRSTDURATIONENDHDL_4, //"[MCC] MCCGroupDel fail\n" + MSG_8852B_MCC_GROUPSTOP_1, //"[MCC] FirstDuration timer del!\n" + MSG_8852B_MCC_GROUPSTOP_2, //"[MCC] replace/pause mode, FirstDuration del bypass!\n" + MSG_8852B_MCC_NEWDURATIONHDL, //"[MCC] Set duration\n" + MSG_8852B_MCC_BITMAPCMP_1, //"[MCC] Release macid %d\n" + MSG_8852B_MCC_BITMAPCMP_2, //"[MCC] Pause macid %d\n" + MSG_8852B_MCC_H2CADDMCCHDL_1, //"[MCC] Add MCC macid %d to group %d\n" + MSG_8852B_MCC_H2CADDMCCHDL_2, //"[MCC] macid: %d, duration: %d, bt_in_2g: %d\n" + MSG_8852B_MCC_H2CADDMCCHDL_3, //"[MCC] Add MCC band %d port %d\n" + MSG_8852B_MCC_H2CSTARTMCCHDL_1, //"[MCC] Start MCC group %d from macid %d\n" + MSG_8852B_MCC_H2CSTARTMCCHDL_2, //"[MCC][REP/STP] Group new idx: %d, old idx: %d, act: %d\n" + MSG_8852B_MCC_H2CSTOPMCCHDL_1, //"[MCC][stop]prev_groups: %d\n" + MSG_8852B_MCC_H2CSTOPMCCHDL_2, //"[MCC][stop]stop group %d fail\n" + MSG_8852B_MCC_H2CSTOPMCCHDL_3, //"[MCC][stop]group %d stop!\n" + MSG_8852B_MCC_H2CDELMCCGROUPHDL_1, //"[MCC][Del] prev_groups: %d\n" + MSG_8852B_MCC_H2CDELMCCGROUPHDL_2, //"[MCC][del]del group %d fail\n" + MSG_8852B_MCC_H2CDELMCCGROUPHDL_3, //"[MCC][del]group %d del!\n" + MSG_8852B_MCC_H2CMCCREQTSFHDL_1, //"[MCC] macid %d is not in role table\n" + MSG_8852B_DEBUGINFO_1, //"ISR Name\tCount\t\tExec Time(historical high)\n" + MSG_8852B_DEBUGINFO_2, //"------------------------------------------------\n" + MSG_8852B_DEBUGINFO_3, //"\t%d\t\t%d_%d\n" + MSG_8852B_DEBUGINFO_4, //"\t\t%d\t\t%d_%d\n" + MSG_8852B_DEBUGINFO_5, //"[Error] ISRInfo len = %d!\n" + MSG_8852B_PROFILING_1, //"func_name %s , " + MSG_8852B_PROFILING_2, //"line %d , cycle %d , offset = %d\n" + MSG_8852B_WLANDUMP_0, //"Tx ok packet cnt: %d\n Tx fail packet cnt: %d\n Txcmd success cnt: %d\n Txcmd abort (MU-RTS/RTS fail) cnt: %d\n Txcmd abort (over SP) cnt: %d\n" + MSG_8852B_WLANDUMP_1, //"Txcmd sounding abort cnt: %d\n Txcmd abort (pri user fail) cnt: %d\n Txcmd abort ( cca or medium busy) cnt: %d\n Txcmd RU/MU2SU cnt: %d\n" + MSG_8852B_WLANDUMP_2, //"chkcmd_sts cnt: %d %d %d %d %d %d\n" + MSG_8852B_WLANDUMP_3, //"TBD" + MSG_8852B_WLANDUMP_4, //"DL Txcmd in last TXOP cnt: %d\n UL Txcmd in last TXOP cnt: %d\n Empty DL SS2F report cnt: %d\n Empty UL SS2F report cnt: %d\n DL TxcmdQ empty cnt: %d\n" + MSG_8852B_WLANDUMP_5, //"Issue DL SU Txcmd cnt: %d\n Issue DL MU Txcmd cnt: %d\n Issue DL RU Txcmd cnt: %d\n Issue UL Txcmd cnt: %d\n f2p_Triggerpkt_cnt=%d\n" + MSG_8852B_WLANDUMP_6, //"Decision MU2SU cnt: %d\n Decision RU2SU cnt: %d\n DLDecision Result record: %x\n Decision SU_FORCESU cnt: %d\n Decision MU_FORCEMU cnt: %d\n" + MSG_8852B_WLANDUMP_7, //"Decision SU_FORCEMU_FAIL cnt: %d\n Decision SU_FORCERU_FAIL cnt: %d\n Decision SU_FORCERU_RUARST_RU2SU cnt: %d\n Decision SU_NOT4_USER cnt: %d\n Decision RU_FORCERU_RUSRST_FIXTBL cnt: %d\n" + MSG_8852B_WLANDUMP_8, //"Decision RU_FORCERU cnt: %d\n Decision SU_WDINFO_USERATE cnt: %d\n Decision SU_PRINULLWD cnt: %d\n ecision MU_BYPASS_MUTPCOMPARE cnt: %d\n Decision SU_MUTXTIME_PASS_MU_NOTSUPPORT cnt: %d\n" + MSG_8852B_WLANDUMP_9, //"Decision SU_MUTXTIME_FAIL_RU_NOTSUPPORT cnt: %d\n Decision SU_RUARST_RU2SU cnt: %d\n Decision RU_RUARST_FIXTBL cnt: %d\n Decision MU_TPCOMPARE_RST cnt: %d\n Decision RU_TPCOMPARE_RST cnt: %d\n Decision SU_TPCOMPARE_RST cnt: %d\n" + MSG_8852B_WLANDUMP_10, //"fw txcmdQ[0] cmd num: %d, fw txcmdQ[1] cmd num: %d,fw txcmdQ[2] cmd num: %d,fw txcmdQ[3] cmd num: %d,fw txcmdQ[4] cmd num: %d\n" + MSG_8852B_WLANDUMP_11, //"fw txcmdQ[5] cmd num: %d, fw txcmdQ[6] cmd num: %d,fw txcmdQ[7] cmd num: %d,fw txcmdQ[8] cmd num: %d,fw txcmdQ[9] cmd num: %d, fw txcmdQ[10] cmd num: %d\n" + MSG_8852B_WLANDUMP_12, //TBD + MSG_8852B_WLANDUMP_13, //"mbid0~7: %d %d %d %d %d %d %d %d\n" + MSG_8852B_WLANDUMP_14, //"macid %d info:\n isHESTA =%d\n AID12 =%d\n DL_BW =%d\n DL_T_PE =%d\n" + MSG_8852B_WLANDUMP_15, //"TF_MAC_Padding =%d\n force tx su =%d\n force tx mu =%d\n fw force mu2su TH = %d\n force tx ru =%d\n" + MSG_8852B_WLANDUMP_16, //"txok_pkt =%d\n txfail pkt cnt: %d\n retry_cnt =%d\n mbssid_idx =%d\n ulgroup_bitmap =%d\n null_wd_cnt =%d\n" + MSG_8852B_WLANDUMP_17, //"ul_sw_grp_bitmap =%d\n AMPDU_max_txtime =%d\n mu_doppler_ctrl =%d\n mu_gi_ltf =%d\n mu decision txtime_bypass =%d\n mu decision mutp_bypass =%d\n" + MSG_8852B_WLANDUMP_18, //"mu_maxinitrate = %x\n mu_maxfinalrate = %x\n mu_mininitrate = %x\n mu_minfinalrate = %x\n mu primary cnt = %d\n" + MSG_8852B_WLANDUMP_19, //" PwrBit =%d\n TP =%d Mbps\n Max Txlen = %x (unit23 byte)\n Min Txlen = %x (unit23 byte)\n Last Txlen = %x (unit23 byte)\n Last BSRlen = %x (unit256 byte) AC=%d\n" + MSG_8852B_WLANDUMP_20, //"mu sta %d info\n mu sta macid= %d\n" + MSG_8852B_WLANDUMP_21, //"mu sta rate array(8bit) 0-4: %x %x %x %x %x" + MSG_8852B_WLANDUMP_22, //"mu sta rate array(8bit) 5-9: %x %x %x %x %x" + MSG_8852B_WLANDUMP_23, //"su ok pkt cnt = %d\n su fail pkt cnt = %d\n su_norsp_pktcnt = %d\n SU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n SU TXCNT 1/<6/<16/>=16 : %d %d %d %d\n" + MSG_8852B_WLANDUMP_24, //"mu ok pkt cnt = %d\n mu fail pkt cnt = %d\n mu_norsp_pktcnt = %d\n mu2su ok pkt cnt = %d\n mu2su fail pkt cnt = %d\n" + MSG_8852B_WLANDUMP_25, //"ru ok pkt cnt = %d\n ru fail pkt cnt = %d\n" + MSG_8852B_WLANDUMP_26, //"MU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n MU DIFF <4/<8/<12/>=12 : %d %d %d %d\n" + MSG_8852B_WLANDUMP_27, //"MU TXCNT 1/<6/<16/>=16: %d %d %d %d\n + MSG_8852B_WLANDUMP_28, //"pktmaxtxcnt(su base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu2nd base) [0]= %d [1]= %d [2]= %d \n" + MSG_8852B_WLANDUMP_30, //"F2PTXCMDRPT cnt= %d, SS2FWRPT cnt =%d, TXRPT cnt =%d, PLDRLSRPT cnt = %d\n" + MSG_8852B_WLANDUMP_31, //"pkt_max_queue_time = %x, pkt_min_queue_time=%x\n" + MSG_8852B_WLANDUMP_32, //"TWT %d info:\n Txcmd overSP= %d\n Txcmd pri user fail= %d\n DL cmdCnt inSP= %d\n UL cmdCnt inSP= %d\n" + MSG_8852B_WLANDUMP_33, //"DL cmdCnt all= %d\n UL cmdCnt all= %d\n UL fixmode = %x\n cur cmd num = %x\n SP 1st TF fail cnt = %x\n" + MSG_8852B_WLANDUMP_34, //"start_d= %d\n start_t= %d\n endearly_d= %d\n endearly_t= %d\n end_d= %d\n" + MSG_8852B_WLANDUMP_35, //"end_t= %d\n timer_qrydl= %d\n timer_qryul= %d\n start_qrydl= %d\n total_qryul=%d\n" + MSG_8852B_WLANDUMP_36, //"firstTF_fail = %d,%d\n" + MSG_8852B_WLANDUMP_37, //"twt_decision_brk = %d, %d, %d, %d, %d, %d, %d, %d\n" + MSG_8852B_WLANDUMP_38, //"twt_decision_rst= %d, %d, %d\n" + MSG_8852B_WLANDUMP_39, //"twt_ACdecision_rst= %d, %d, %d, %d\n" + MSG_8852B_WLANDUMP_40, //"twt_validdlss2f_cnt= %d, twt_emptydlss2f_cnt= %d, twt_validulss2f_cnt= %d, twt_emptyulss2f_cnt= %d, twt_dlss2f_fromquery= %d, twt_dlss2f_fromtxcmd=%d, twt_ulss2f_fromquery= %d, twt_ulss2f_fromtxcmd=%d\n" + MSG_8852B_WLANDUMP_41, //"TWT member: %d %d %d %d %d\n" + MSG_8852B_WLANDUMP_42, //"twt_dlss2f_qrycnt[0]=%d,twt_dlss2f_qrycnt[1]=%d,twt_dlss2f_qrycnt[2]=%d,twt_dlss2f_qrycnt[3]=%d\n" + MSG_8852B_WLANDUMP_43, //"reform_fail_rst[0]=%d, reform_fail_rst[1]=%d, reform_fail_rst[2]=%d, reform_fail_rst[3]=%d, reform_fail_rst[4]=%d\n" + MSG_8852B_WLANDUMP_44, //"MACID WD count BE:%d BK:%d VI:%d VO:%d\n" + MSG_8852B_WLANDUMP_45, //"PPS F2PCMD_PPS:%d/s TXRPT_PPS:%d/s TXPKT_PPS:%d/s SS2F_0_PPS:%d/s SS2F_1_PPS:%d/s SS2F_2_PPS:%d/s" + MSG_8852B_ROLE_1, //"B%dP%d RXBCNOK\n" + MSG_8852B_ROLE_2, //"B%dP%d BCNNOHIT\n" + MSG_8852B_ROLE_3, //"Role idx search fail\n + MSG_8852B_ROLE_4, //"=>CreateRole\n" + MSG_8852B_ROLE_5, //"[FAIL] Role info alloc fail!\n" + MSG_8852B_ROLE_6, //"[FAIL] Role info - PPSDbgParm alloc fail!\n" + MSG_8852B_ROLE_7, //"[FAIL] Role info - PTWTParam alloc fail!\n" + MSG_8852B_ROLE_8, //"[CreateRole] ActRole=%d, LinkRole=%d.\n + MSG_8852B_ROLE_9, //"[CreateRole] band=%d, port=%d, macid=%d.\n" + MSG_8852B_ROLE_10, //"=>DelRole\n" + MSG_8852B_ROLE_11, //"[Warn] ROLE_NOT_EXIST for DelRole!\n" + MSG_8852B_ROLE_12, //"[DelRole] ActRole=%d!role_idx=%d\n" + MSG_8852B_ROLE_13, //"Role idx search by macid fail\n" + MSG_8852B_ROLE_14, //"[WARN] Role exist for macid=0x%x! role_idx=0x%x\n" + MSG_8852B_ROLE_15, //"[FAIL] Create Role idx > max_number!\n" + MSG_8852B_ROLE_16, //"[FAIL] Create Role fail!\n" + MSG_8852B_ROLE_17, //"[Warn] search role fail for JoinInfo!\n" + MSG_8852B_ROLE_18, //"[FAIL] JoinInfo Role idx > max_number!\n" + MSG_8852B_ROLE_19, //"[WARN] Role exist for macid=0x%x! role_idx=0x%x\n" + MSG_8852B_ROLE_20, //"[Warn] search role fail for DelRole!\n" + MSG_8852B_ROLE_21, //"[FAIL] Del Role idx > max_number!\n" + MSG_8852B_PMF_00, //"start saquery timer fail\n" + MSG_8852B_PMF_01, //"start saquery timer\n" + MSG_8852B_PMF_02, //"creat saquery timer fail\n" + MSG_8852B_PMF_03, //"saquery timer is lanched alread\n" + MSG_8852B_PMF_04, //"SA Query timer deleted!\n" + MSG_8852B_PMF_05, //"Deauth content\n" + MSG_8852B_PMF_06, //"packet_len_no_fcs error\n" + MSG_8852B_PMF_07, //"ICV Error ok\n" + MSG_8852B_PMF_08, //"encrypted deauth frame, SEC_TYPE: 0x%x) \n" + MSG_8852B_PMF_09, //"not Encrypted Deauth/Disassoc\n" + MSG_8852B_PMF_10, //"deauth_reason = %x %x\n" + MSG_8852B_PMF_11, //"tx_sa_query_result = 0x%x\n" + MSG_8852B_PMF_12, //"issue saquery req fail\n" + MSG_8852B_PMF_13, //"ignore the deauth frame\n" + MSG_8852B_PMF_14, //"ICV Error\n" + MSG_8852B_PMF_15, //"bip_result=0x%x\n" + MSG_8852B_PMF_16, //"\npacket_len_no_fcs error\n" + MSG_8852B_PMF_17, //"\nOn SA Query Req! (len=0x%x)\n" + MSG_8852B_PMF_18, //"issue saquery rsp fail\n" + MSG_8852B_PMF_19, //"\nOn SA Query Resp!(len=0x%x)\n" + MSG_8852B_PMF_20, //"issue_sa_query_timeout_hdl!\n" + MSG_8852B_PMF_21, //"Deauth wake up!\n" + MSG_8852B_PMF_22, //"can't get offload PKT for saquery\n" + MSG_8852B_PMF_23, //"can't allocate sendpkt_buff \n" + MSG_8852B_PMF_24, //"FW IPN > pkt IPN\n" + MSG_8852B_PMF_25, //"FW IPN < pkt IPN\n" + MSG_8852B_PMF_26, //"FW IPN == pkt IPN\n" + MSG_8852B_PMF_27, //"IPSecAESECBInit false\n" + MSG_8852B_PMF_28, //"IPSecAESECBEncrypt false\n" + MSG_8852B_PMF_30, //"key_len = %d, false\n" + MSG_8852B_PMF_31, //"iv_len = %d, false\n" + MSG_8852B_PMF_32, //"IPSecInitWithISRDisable false\n" + MSG_8852B_PMF_40, //"MIC check fail\n" + MSG_8852B_PMF_41, //"\n: aes_gmac fail!\n" + MSG_8852B_PMF_42, //"\n: _bip_gcmp_protect(128) fail!\n" + MSG_8852B_PMF_43, //"\n: _bip_gcmp_protect(256) fail!\n" + MSG_8852B_PMF_44, //"\n: unsupport dot11wCipher !\n" + MSG_8852B_PMF_45, //"not a management frame\n" + MSG_8852B_PMF_46, //"is a beacon\n" + MSG_8852B_PMF_47, //"not a broadcast frame\n" + MSG_8852B_PMF_48, //"packet too small\n" + MSG_8852B_PMF_49, //"elemnt_id != 0x4c\n" + MSG_8852B_PMF_50, //"is_bip_enc_frameComm return TRUE\n" + MSG_8852B_PMF_51, //"\nbip_verifyComm: PKT (len=0x%x)\n" + MSG_8852B_PMF_52, //"BSSID not match\n" + MSG_8852B_PMF_53, //"ori_len = 0x%x\n" + MSG_8852B_PMF_54, //"SW BIP DEC FAIL\n" + MSG_8852B_PMF_55, //"NOT encrypted\n" + MSG_8852B_PMF_56, //"IPN verify Fail\n" + MSG_8852B_PMF_57, //"bip_verifyComm return TRUE\n" + MSG_8852B_PMF_58, //"protection bit is not 1\n" + MSG_8852B_PMF_59, //"not a unicast frame\n" + MSG_8852B_PMF_60, //"PairwiseEncAlg not GCMP\n" + MSG_8852B_PMF_61, //"aes_gcm_ad fail\n" + MSG_8852B_PMF_62, //"aes_gcm_ae fail\n" + MSG_8852B_RXFLOW_1, //"can't allocate wlan pktbuf\n" + MSG_8852B_RXFLOW_2, //"DD=%x\n" + MSG_8852B_RXFLOW_3, //"A=%x\n" + MSG_8852B_RXFLOW_4, //"B=%x\n" + MSG_8852B_RXFWD_1, //"Unsupported index!\n" + MSG_8852B_WLAN_1, //"SS Query Report HW stuck!!\n" + MSG_8852B_SECCAM_1, //"Search key, mac_id : %d, key_id : %d, key_type : %d , fail\n" + MSG_8852B_SECCAM_2, //"Search key success\nMac_id : %d, key_id : %d, key_type : %d, key cam index : %d\n" + MSG_8852B_SECCAM_3, //"Wowlan rekey %d, %d, %d\n" + MSG_8852B_SECCAM_4, //"check addr key index full\n" + MSG_8852B_SECCAM_5, //"Free cam index: %d\n" + MSG_8852B_SECCAM_6, //"insertKeyAddrCam ret : %d\n" + MSG_8852B_RPTHDL_1, //"pldrlsrpt len %d not align\n" + MSG_8852B_RPTHDL_2, //"RlsRptHDLRAM8852B,rpt_num=%x,len=%x\n" + MSG_8852B_RPTHDL_3, //"ERR: TxCmdRptHDL get NULL txinfo node,rpt->QSEL=%x, (rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n" + MSG_8852B_RPTHDL_4, //"ERR: TxRptHDL get NULL txinfo node,rpt->QSEL=%x,(rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n" + MSG_8852B_RPTHDL_5, //"ERR: TfRptHDL get NULL txinfo node\n" + MSG_8852B_RPTHDL_6, //"SS2FInfoDeQ8852B\n" + MSG_8852B_RPTHDL_7, //"F2PTXCMDRPT HDL\n" + MSG_8852B_RPTHDL_8, //"SS2FWRPT HDL\n" + MSG_8852B_RPTHDL_9, //"TFRPT HDL\n" + MSG_8852B_RPTHDL_10, //"TXBCNRPT HDL\n" + MSG_8852B_RPTHDL_11, //"CCXRPT HDL\n" + MSG_8852B_RPTHDL_12, //"TXRPT HDL\n" + MSG_8852B_RPTHDL_13, //"PLDRLSRPT HDL\n" + MSG_8852B_ERRHDL_1, //"[ERR]DLE Timeout(idx = %d)\n" + MSG_8852B_ERRHDL_2, //"[ERR]AXIDMA is not idle!\n" + MSG_8852B_ERRHDL_3, //"[ERR]STA scheduler init\n" + MSG_8852B_ERRHDL_4, //"[ERR]WDE cfg ready\n" + MSG_8852B_ERRHDL_5, //"[ERR]PLE cfg ready\n" + MSG_8852B_ERRHDL_6, //"=>DmaTopStuck:FA sts: %d, data: %d!\n" + MSG_8852B_ERRHDL_7, //"=>DmaTopStuck:FA!\n" + MSG_8852B_ERRHDL_8, //"=>DmaTopStuck:know!\n" + MSG_8852B_ERRHDL_9, //"=>RecoveryCMAC!\n" + MSG_8852B_ERRHDL_10, //"[ERR]BBRPT CHIF\n" + MSG_8852B_ERRHDL_11, //"[ERR]Check CMAC_idle\n" + MSG_8852B_ERRHDL_12, //"[ERR]PTCL tx\n" + MSG_8852B_ERRHDL_13, //"[ERR]L0 promote event %x\n" + MSG_8852B_ERRHDL_14, //"[ERR][C2H]Previous: %x; Current: %x\n" + MSG_8852B_ERRHDL_15, //"ErrHDL in!\n" + MSG_8852B_ERRHDL_16, //"ErrHDL out!\n" + MSG_8852B_ERRHDL_17, //"DMAC error: %x\n" + MSG_8852B_ERRHDL_18, //"CMAC0 error: %x\n" + MSG_8852B_ERRHDL_19, //"CMAC1 error: %x\n" + MSG_8852B_ERRHDL_20, //"notify: %x\n" + MSG_8852B_ERRHDL_21, //"--->\n err=%x\n" + MSG_8852B_ERRHDL_22, //"R_AX_SER_DBG_INFO =%x\n" + MSG_8852B_ERRHDL_23, //"R_AX_DMAC_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_24, //"R_AX_WDE_ERR_FLAG_CFG_NUM1 =%x\n" + MSG_8852B_ERRHDL_25, //"R_AX_PLE_ERR_FLAG_CFG_NUM1 =%x\n" + MSG_8852B_ERRHDL_26, //"R_AX_WDRLS_ERR_IMR =%x " + MSG_8852B_ERRHDL_27, //"R_AX_WDRLS_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_28, //"R_AX_RPQ_RXBD_IDX =%x\n" + MSG_8852B_ERRHDL_29, //"R_AX_SEC_DEBUG =%x\n" + MSG_8852B_ERRHDL_30, //"R_AX_MPDU_TX_ERR_IMR =%x " + MSG_8852B_ERRHDL_31, //"R_AX_MPDU_TX_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_32, //"R_AX_MPDU_RX_ERR_IMR =%x " + MSG_8852B_ERRHDL_33, //"R_AX_MPDU_RX_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_34, //"R_AX_STA_SCHEDULER_ERR_IMR =%x " + MSG_8852B_ERRHDL_35, //"R_AX_STA_SCHEDULER_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_36, //"R_AX_WDE_ERR_IMR=%x " + MSG_8852B_ERRHDL_37, //"R_AX_WDE_ERR_ISR=%x\n" + MSG_8852B_ERRHDL_38, //"R_AX_PLE_ERR_IMR=%x " + MSG_8852B_ERRHDL_39, //"R_AX_PLE_ERR_FLAG_ISR=%x\n" + MSG_8852B_ERRHDL_40, //"R_AX_TXPKTCTL_ERR_IMR_ISR=%x\n" + MSG_8852B_ERRHDL_41, //"R_AX_TXPKTCTL_ERR_IMR_ISR_B1=%x\n" + MSG_8852B_ERRHDL_42, //"R_AX_PKTIN_ERR_IMR =%x " + MSG_8852B_ERRHDL_43, //"R_AX_PKTIN_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_44, //"R_AX_PKTIN_ERR_IMR =%x " + MSG_8852B_ERRHDL_45, //"R_AX_PKTIN_ERR_ISR =%x\n" + MSG_8852B_ERRHDL_46, //"R_AX_HOST_DISPATCHER_ERR_IMR=%x " + MSG_8852B_ERRHDL_47, //"R_AX_HOST_DISPATCHER_ERR_ISR=%x\n" + MSG_8852B_ERRHDL_48, //"R_AX_CPU_DISPATCHER_ERR_IMR=%x " + MSG_8852B_ERRHDL_49, //"R_AX_CPU_DISPATCHER_ERR_ISR=%x\n" + MSG_8852B_ERRHDL_50, //"R_AX_CPUIO_ERR_IMR=%x " + MSG_8852B_ERRHDL_51, //"R_AX_CPUIO_ERR_ISR=%x\n" + MSG_8852B_ERRHDL_52, //"R_AX_BBRPT_COM_ERR_IMR_ISR=%x\n" + MSG_8852B_ERRHDL_53, //"0xC164=%x\n" + MSG_8852B_ERRHDL_54, //"R_AX_SCHEDULE_ERR_IMR=%x " + MSG_8852B_ERRHDL_55, //"R_AX_SCHEDULE_ERR_ISR=%x\n" + MSG_8852B_ERRHDL_56, //"R_AX_PTCL_IMR0=%x " + MSG_8852B_ERRHDL_57, //"R_AX_PTCL_ISR0=%x\n" + MSG_8852B_ERRHDL_58, //"R_AX_DLE_CTRL=%x\n" + MSG_8852B_ERRHDL_59, //"R_AX_PHYINFO_ERR_IMR=%x\n" + MSG_8852B_ERRHDL_60, //"R_AX_TXPWR_IMR= N/A " + MSG_8852B_ERRHDL_61, //"R_AX_TXPWR_ISR= N/A\n" + MSG_8852B_ERRHDL_62, //"R_AX_DBGSEL_TRXPTCL=%x " + MSG_8852B_ERRHDL_63, //"R_AX_PHYINFO_ERR_IMR=%x\n" + MSG_8852B_ERRHDL_64, //"R_AX_TMAC_ERR_IMR_ISR=%x " + MSG_8852B_ERRHDL_65, //"R_AX_DBGSEL_TRXPTCL=%x\n" + MSG_8852B_ERRHDL_66, //"<---\n" + MSG_8852B_MAIN_00, //"SW Queue reCreate\n" + MSG_8852B_MAIN_01, //"Enter AXIDMA_init... \n" + MSG_8852B_MAIN_02, //"WDT_timer start... \n" + MSG_8852B_MAIN_03, //"InitHWPostDLRAM done\n" + MSG_8852B_MAIN_04, //"InitFWFuncPostDL RAM done\n" + MSG_8852B_MAIN_05, //"MAC per STAInfo %d bytes\n" + MSG_8852B_MAIN_06, //"BB per STAInfo %d bytes\n" + MSG_8852B_MAIN_07, //"InitWLANFuncRAM done\n" + MSG_8852B_MAIN_08, //"Enter test id (0~7): " + MSG_8852B_MAIN_09, //"%c\n" + MSG_8852B_MAIN_10, //"Thread Metric: %d\n" + MSG_8852B_MAIN_11, //"Test duration: %d seconds\n" + MSG_8852B_MAIN_14, //"WDT_timer start fail \n" + MSG_8852B_MAIN_15, //" SysMib.PInternal->PDebugInfo->DbgLvl =%x\n" + MSG_8852B_MAIN_16, //"Enter flash FW loader\n + MSG_8852B_IRAMENTRY_00, //"Function ptr length :RAM %x,ROM %x\n" + MSG_8852B_IRAMENTRY_01, //"Function ptr length not equal!!\n" + MSG_8852B_IRAMENTRY_02, //"Start Init PLE memory\n" + MSG_8852B_IRAMENTRY_03, //"PLE data check error!!!" + MSG_8852B_IRAMENTRY_04, //"PLE usage :%x\n" + MSG_8852B_IRAMENTRY_05, //"Initializing RAM bss ...\n" + MSG_8852B_IRAMENTRY_06, //"_BSS_RAM_START_ : %x\t _BSS_RAM_END_ : %x\n" + MSG_8852B_IRAMENTRY_07, //"B cut\n" + MSG_8852B_IRAMENTRY_08, //"_RAM_FUNCPTR_START_ : %x\t _RAM_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_09, //"_ROM_FUNCPTR_START_ : %x\t _ROM_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_10, //"C cut\n" + MSG_8852B_IRAMENTRY_11, //"_RAM_CCUT_FUNCPTR_START_ : %x\t _RAM_CCUT_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_12, //"_ROM_CCUT_FUNCPTR_START_ : %x\t _ROM_CCUT_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_13, //"D cut\n" + MSG_8852B_IRAMENTRY_14, //"_RAM_DCUT_FUNCPTR_START_ : %x\t _RAM_DCUT_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_15, //"_ROM_DCUT_FUNCPTR_START_ : %x\t _ROM_DCUT_FUNCPTR_END_ : %x\n" + MSG_8852B_IRAMENTRY_16, //"Load FW RAM code OK\n" + MSG_8852B_BACKTRACE_00, //"Heap space is not enough for backtrace.......\n" + MSG_8852B_BACKTRACE_01, //"Backtrace......\n" + MSG_8852B_BACKTRACE_02, //"Next SP:%x, Next RA:%x\n" + MSG_8852B_BACKTRACE_03, //"Backtrace is failed\n" + MSG_8852B_BACKTRACE_04, //"Done\n" + MSG_8852B_BACKTRACE_05, //"EPC: %x, Cause: %x, BADVADDR: %x, Status: %x\n" + MSG_8852B_BACKTRACE_06, //"hi: %x, lo: %x, ra: %x, fp: %x\n" + MSG_8852B_BACKTRACE_07, //"sp: %x, gp: %x, t9: %x, t8: %x\n" + MSG_8852B_BACKTRACE_08, //"s7: %x, s6: %x, s5: %x, s4: %x\n" + MSG_8852B_BACKTRACE_09, //"s3: %x, s2: %x, s1: %x, s0: %x\n" + MSG_8852B_BACKTRACE_10, //"t7: %x, t6: %x, t5: %x, t4: %x\n" + MSG_8852B_BACKTRACE_11, //"t3: %x, t2: %x, t1: %x, t0: %x\n" + MSG_8852B_BACKTRACE_12, //"a3: %x, a2: %x, a1: %x, a0: %x\n" + MSG_8852B_BACKTRACE_13, //"v1: %x, v0: %x, at: %x\n" + MSG_8852B_BACKTRACE_14, //"not send c2hHalt\n" + MSG_8852B_BACKTRACE_15, //"no loop\n" + MSG_8852B_BACKTRACE_16, //"Something wrong when allocating backtrace memory\n" + MSG_8852B_BACKTRACE_17, //"Backtrace memory is full!!\n" + MSG_8852B_BACKTRACE_18, //"Init Backtrace Memory failed\n" + MSG_8852B_PSTIMER_00, //"handle task:%x\n" + MSG_8852B_PSTIMER_01, //"handle tsf: %x\n" + MSG_8852B_PSTIMER_02, //"tsf in list: %x\n" + MSG_8852B_AXIDMA_00, //"[ERR] AXIDMA is not idle!\n" + MSG_8852B_AXIDMA_01, //"[ERR] AXIDMA is not enable\n" + MSG_8852B_AXIDMA_02, //"[AXIDMA RX Init]Allocate H2C buffer fail 123\n" + MSG_8852B_AXIDMA_03, //"[AXIDMA RX Init]Allocate PKT buffer fail\n" + MSG_8852B_AXIDMA_04, //"[AXIDMA RX Init]Allocate RPT buffer fail\n" + MSG_8852B_PORT_00, //"Assert at file: %s, line: %u\n" + MSG_8852B_PORT_01, //"not send c2hHalt\n" + MSG_8852B_PORT_02, //"no loop\n" + MSG_8852B_PORT_03, //"Watch dog timeout in critical section\n" + MSG_8852B_PORT_04, //"Watch dog remain: %d(us)\n" + MSG_8852B_PORT_05, //"Exec Time %x ~ %x: %d(us)\n" + MSG_8852B_RXI300_00, //"EPC Value: %x\n" + MSG_8852B_RXI300_01, //"Error id is inexistent(%x)!\n" + MSG_8852B_RXI300_02, //"Error code is inexistent(%x)!\n" + MSG_8852B_RXI300_03, //"RXI300_ERR_SRC_APB_DEF_SLV" + MSG_8852B_RXI300_04, //"RXI300_ERR_SRC_AXI_APB_SA" + MSG_8852B_RXI300_05, //"Error source is inexistent(%x)!\n" + MSG_8852B_RXI300_06, //"HaltC2H = %x, Error address = %x!\n" + MSG_8852B_RXI300_07, //"Clear interrupt fail!\n" + MSG_8852B_RXI300_08, //"RA/SP Value: %x, %x\n" + MSG_8852B_PS_CHK_PLATFORM_ERR_1, //"DMAC error: %x\n" + MSG_8852B_PS_CHK_PLATFORM_ERR_2, //"CMAC%d error: %x\n" + MSG_8852B_PS_DDMA_BUFFER_SIZE_OVERFLOW, //"MAC%d DDMA buffer size (%x) is overflow!\n" + MSG_8852B_PS_HIOE_START_ADDR, //"LPS HIOE start address = %x, size = %x\n" + MSG_8852B_PS_HIOE_END_ADDR, //"LPS HIOE end address = %x\n" + MSG_8852B_PS_HIOE_INST_OVERFLOW, //"LPS HIOE instruction is overflow! inst_size(%x).\n" + MSG_8852B_PS_HIOE_READ_PCIEMIO_FAIL, //"[Err] ReadPCIEMIO Fail! reg = %x\n" + MSG_8852B_PS_HIOE_WRITE_PCIEMIO_FAIL, //"[Err] WritePCIEMIO Fail! reg = %x\n" + MSG_8852B_PS_HIOE_BACKUP_FAIL, //"BKP fail st.(%x)\n" + MSG_8852B_PS_HIOE_RESTORE_FAIL, //"RES fail st.(%x)\n" + MSG_8852B_PS_HIOE_INVALID_STATE, //"Invalid st.(%x)\n" + MSG_8852B_PS_HIOE_BACKUP_TIMEOUT, //"Bkp (%d) polling timeout!\n" + MSG_8852B_PS_HIOE_RESTORE_TIMEOUT, //"Res polling timeout!\n" + MSG_8852B_PS_ENTER_32K, //">C\n" + MSG_8852B_PS_LEAVE_32K, //"\n" + MSG_8852B_PS_OPEN_RF, //"<\n" + MSG_8852B_PS_GRANT_WLAN_FAIL, //"[PDCK] GNT WL FAIL!!\n" + MSG_8852B_PS_PDCK_CAL_FAIL, //"PDCK CAL FAIL!!\n" + MSG_8852B_PS_ANACLK_CAL_FAIL, //"ANACLK CAL FAIL!!\n" + MSG_8852B_PS_EN_RX_NORMAL_MODE_FAIL, //"RF is OFF. EnRxNormMode FAIL!\n" + MSG_8852B_PS_EN_RX_NORMAL_MODE, //"1->2" + MSG_8852B_PS_SET_RF_OFF_PERMISSION, //"SetRfOffPermission: PhyRfOffPermission[%d]=%d\n" + MSG_8852B_PS_SET_32K_PERMISSION, //"Set32KandPGPermission. 32K(%d), PG(%d)\n" + MSG_8852B_PS_ENABLE_LPS_FW_TEST, //"Enable LPS FW test. Target LPS number (%x)\n" + MSG_8852B_PS_WAKE_BAR_PULL, //"[RF OFF] Wake bar is pulled\n" + MSG_8852B_PS_RX_FAIL_KEEP_RF_ON, //"[RF OFF] Rx FAIL! keep RF on.\n" + MSG_8852B_PS_CHECK_RF_CONDITION_FAIL, //"Check RF OFF condition FAIL (%d)\n" + MSG_8852B_PS_TX_NULL_FAIL, //"[Error] Cannot tx null%d\n" + MSG_8852B_PS_CREATE_ROLE_FAIL, //"[FAIL] Create Role fail!\n" + MSG_8852B_PS_ALREADY_IN_PS_MODE, //"[Error] Already in LPS/WMM PS (%x)!!\n" + MSG_8852B_PS_SET_POWER_MODE_1, //"MAC ID = %d, PS Mode = %d, RLBM = %d\n" + MSG_8852B_PS_SET_POWER_MODE_2, //"Smart PS = %d, Awake Interval = %d, Last RPWM = %d\n" + MSG_8852B_PS_BEACON_EARLY, //"E\n" + MSG_8852B_PS_RX_BEACON, //"R\n" + MSG_8852B_PS_RX_BEACON_NO_HIT, //"N\n" + MSG_8852B_PS_INVALID_BEACON_REPORT, //"[Error] Does not receive BCN Parser Rpt\n" + MSG_8852B_PS_KEEP_RF_ON, //"Keep ON\n" + MSG_8852B_PS_ENABLE_BEACON_TIMEOUT_TIMER_FAIL, //"EnBcnTimeOutCount fail!!\n" + MSG_8852B_PS_TIMER_VALUE_NOT_INIT, //"Timer (%d) val is not init!! role_idx(%d)\n" + MSG_8852B_PS_CREATE_TIMER_FAIL, //"Create timer (%d) fail!! role_idx(%d)\n" + MSG_8852B_PS_SEND_NULL_FAIL_RESULT, //"TxNull %d FAIL! ret_type(%d), result(%d)\n" + MSG_8852B_PS_INVALID_POWER_BIT, //"[PsSendNullCb] invalid pwr_bit(%d)\n" + MSG_8852B_PS_INIT_PS_PARAMETER, //"InitPSParm, role_idx=%d\n" + MSG_8852B_PS_S2_CONDITION_MISMATCH, //"[ChkS2 no match] Condition(%d), LpsDbgInfo = 0x%x\n" + MSG_8852B_PS_S4_CONDITION_MISMATCH, //"[ChkS4 no match] Condition(%d), LpsDbgInfo = 0x%x\n" + MSG_8852B_PS_CHANGE_PS_STATE, //"[ChangePSStateByRPWM] REQ State: %d, Cur State: %d\n" + MSG_8852B_PS_SET_POWER_MODE_ROLE_NOT_EXIST, //"Role not exist! Condition (%d)\n" + MSG_8852B_PS_SET_TBTT_AGG_NUM, //"Step(%d), SetTbttAggNum(%d).\n" + MSG_8852B_PS_RX_BEACON_TIMEOUT, //"PsBcnTimeOut\n" + MSG_8852B_PS_SET_POWER_STATE, //"CURRENT_PS_STATE: %d, LASTRPWM: %d\n" + MSG_8852B_PS_RESET_PS_PARAMETER, //"ResetPSParm\n" + MSG_8852B_PS_ACTIVATE_SETTING, //"ActiveSetting\n" + MSG_8852B_PS_SEND_NULL_RESULT, //"[PsSendNullCb] type(%d), result(%d)\n" + MSG_8852B_PACKET_TX_NOT_ENABLE, //"[ERR]MGQ1 Txen = 0, TXEN(0xC348)=%x\n" + MSG_8852B_PACKET_MACID_SLEEP, //"MACID_SLEEP_0(0xC2C0)=%x\n" + MSG_8852B_PACKET_TX_NULL, //"Null %d\n" + MSG_8852B_PACKET_SEND_NULL_FAIL, //"Send NULL FAIL! ret_type(%d), ret_result(%d).\n" + MSG_8852B_PACKET_INVALID_POWER_BIT, //"Send NULL with invalid type(%d)!.\n" + MSG_8852B_PACKET_NULL_PKTID_NOT_EXIST, //"Null PKTID No Exist!!\n" + MSG_8852B_PACKET_NULL_READ_PKT_OFFLOAD_FAIL, //"[IssueNull]ReadFWOfldPKT FAIL!!\n" + MSG_8852B_PACKET_NULL_PKT_OFFLOAD, //"Null ID=%d, pkt_len=%d, ppkt_content=%x\n" + MSG_8852B_PACKET_PROBE_REQ_PKTID_NOT_EXIST, //"Probe req PKTID No Exist!!\n" + MSG_8852B_PACKET_PROBE_REQ_READ_PKT_OFFLOAD_FAIL, //"[IssueProbeReq]ReadFWOfldPKT FAIL!!\n" + MSG_8852B_WOWLAN_1, //"H2C wowlan, fun: %x" + MSG_8852B_WOWLAN_2, //"H2C Keep Alive, Enable: %x\n" + MSG_8852B_WOWLAN_3, //"H2C disconn, Enable: %x\n" + MSG_8852B_WOWLAN_4, //"Wow stop AXIDMA failed\n" + MSG_8852B_WOWLAN_5, //"H2C wow global, Enable: %x\n" + MSG_8852B_WOWLAN_6, //"H2C wakeup ctrl, pattern match Enable: %x\n" + MSG_8852B_WOWLAN_7, //"H2C , nlo Enable: %x\n" + MSG_8852B_WOWLAN_8, //"H2C , wow cam: %x\n" + MSG_8852B_WOWLAN_9, //"\nAppendTkipMICComm\n" + MSG_8852B_WOWLAN_10, //"key[%d]=%bx\n" + MSG_8852B_WOWLAN_11, //"DA[%d]=%bx\n" + MSG_8852B_WOWLAN_12, //"SA[%d]=%bx\n" + MSG_8852B_WOWLAN_13, //"Priority[%d]=%bx\n" + MSG_8852B_WOWLAN_14, //"data[%d]=%bx\n" + MSG_8852B_WOWLAN_15, //"miccode[%d]=%bx\n" + MSG_8852B_WOWLAN_16, //"get 1st rx pktid fail\n" + MSG_8852B_WOWLAN_17, //"(%d, %d) Parsed Failed!\n" + MSG_8852B_WOWLAN_18, //"Magic Packet Parsed Done, reason_bits<%x>\n" + MSG_8852B_WOWLAN_19, //"H2C , arp ofld Enable: %x\n" + MSG_8852B_WOWLAN_20, //"Unexpected HCI type in togglewake\n" + MSG_8852B_BEACON_1, //"req bcn mem err\n" + MSG_8852B_BEACON_2, //"CPUIO rls bcn pld fail\n" + MSG_8852B_BEACON_3, //"req bcn wp err %d\n" + MSG_8852B_BEACON_4, //"bcnq lock fail\n" + MSG_8852B_BEACON_5, //"CPUIO deq bcn fail\n" + MSG_8852B_BEACON_6, //"bcn req wd fail %d\n" + MSG_8852B_BEACON_7, //"enq bcn fail %d\n" + MSG_8852B_PPS_00, //"B%d pps%d already enable\n" + MSG_8852B_PPS_01, //"B%d pps%d already disable\n" + MSG_8852B_PPS_02, //"B%d pps%d reg already enable\n" + MSG_8852B_PPS_03, //"B%d pps%d reg already disable\n" + MSG_8852B_PPS_04, //"invalid pps band %d\n" + MSG_8852B_PPS_05, //"B%d pps%d is not enable yet\n" + MSG_8852B_PPS_06, //"B%d pps%d pof%d already enable\n" + MSG_8852B_PPS_07, //"B%d pps%d pof%d already disable\n" + MSG_8852B_PPS_08, //"B%d pps%d pof%d reg already enable\n" + MSG_8852B_PPS_09, //"B%d pps%d pof%d reg already disable\n" + MSG_8852B_PPS_10, //"B%d pps%d pof%d running\n" + MSG_8852B_PPS_11, //"pps no param ptr %d\n" + MSG_8852B_PPS_12, //"invalid pps port %d\n" + MSG_8852B_PPS_13, //"no valid pps id\n" + MSG_8852B_PPS_14, //"pps is already running\n" + MSG_8852B_PS_TX_REQ, //"PsTxReq. role(%d), feature(%d), en(%d)\n" + MSG_8852B_PS_TX_REQ_DUPLICATED_DISABLE, //"[ERROR] role(%d), feature(%d) Tx has been disabled!\n" + MSG_8852B_CHSW_00, //"[ChSw] Channel Switch Fail. (ctrl_bw_ch return false)\n" + MSG_8852B_P2P_00, //"[P2P]no act info ptr\n" + MSG_8852B_P2P_01, //"[P2P]act h2c init Role idx srch fail macid %d\n" + MSG_8852B_P2P_02, //"[P2P]set pps param fail %d\n" + MSG_8852B_P2P_03, //"[P2P]B%d pps%d en%d fail %d\n" + MSG_8852B_P2P_04, //"[P2P]B%d pps%d pof%d en%d fail %d\n" + MSG_8852B_P2P_05, //"[P2P]set pof param fail %d\n" + MSG_8852B_P2P_06, //"[P2P]B%d P2P%d noa%d already disable\n" + MSG_8852B_P2P_07, //"[P2P]B%d P2P%d has no running NoA sch\n" + MSG_8852B_P2P_08, //"[P2P]no content ptr\n" + MSG_8852B_P2P_09, //"[P2P]act h2c p2p%d over max\n" + MSG_8852B_P2P_10, //"[P2P]act h2c noa%d over max\n" + MSG_8852B_P2P_11, //"[P2P]p2p%d already running\n" + MSG_8852B_P2P_12, //"[P2P]p2p%d not init yet\n" + MSG_8852B_P2P_13, //"[P2P]act h2c init fail %d\n" + MSG_8852B_P2P_14, //"[P2P]act h2c upd sch fail %d\n" + MSG_8852B_P2P_15, //"[P2P]act h2c rm sch fail %d\n" + MSG_8852B_P2P_16, //"[P2P]act h2c term fail %d\n" + MSG_8852B_P2P_17, //"[P2P]illegal act h2c %d\n" + MSG_8852B_P2P_18, //"[P2P] macid ctrl h2c p2p id %d over max\n" + MSG_8852B_P2P_19, //"[P2P]macid ctrl type %d invalid\n" + MSG_8852B_P2P_20, //"[P2P]no p2p info ptr\n" + MSG_8852B_P2P_21, //"[P2P]P2P%d clear MACID ctrl all fail %d\n" + MSG_8852B_P2P_22, //"[P2P]H2C Act fail %d\n" + MSG_8852B_P2P_23, //"[P2P]H2C MACID ctrl fail %d\n" + MSG_8852B_NULL_RESULT, //"TxNull %d result(%d)!!!\n" + MSG_8852B_PS_CREATE_TIMER_DUPLICATED, //"[ERR][LPS] Create timer (%d) is existed!! role_idx(%d)\n" + MSG_8852B_PS_DELETE_TIMER_FAIL, //"[ERR][LPS] Delete timer (%d) FAIL!! role_idx(%d)\n" + MSG_8852B_PS_DELETE_TIMER_NOT_EXIST, //"[ERR][LPS] Delete timer (%d) is not existed!! role_idx(%d)\n" + MSG_8852B_PS_DTIM_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) DTIM timer is not existed!! role_idx(%d)\n" + MSG_8852B_PS_BCN_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) BCN timer is not existed!! role_idx(%d)\n" + MSG_8852B_PS_TRX_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) TRX timer is not existed!! role_idx(%d)\n" + MSG_8852B_PS_ENABLE_DTIM_TIMEOUT_TIMER_FAIL, //"[ERR][LPS] EnDTIMTimeOutCountComm FAIL!!\n" + MSG_8852B_PS_ENABLE_TRX_TIMEOUT_TIMER_FAIL, //"[ERR][LPS] EnTRXTimeOutCount FAIL!!\n" + MSG_8852B_PS_DRFC_RESTORE_FAIL, //"[ERR][LPS] Restore DRFC FAIL!! RF mode (%d)\n" + MSG_8852B_PS_S2TOS4_TX_BUSY, //"[WARN][LPS][S2ToS4State] Macid TX busy, role_idx(%d)\n" + MSG_8852B_RPWM_SEQ_MISMATCH, //"[ERR] RPWM Seq Num mismatch!\n" + MSG_8852B_RPWM_REQ_STATE_INVALID, //"[ERR] Req Pwr state (%d) is invalid!\n" + MSG_8852B_READ_RPWM, //"Read RPWM = %x\n" + MSG_8852B_WRITE_CPWM, //"LDM = %x, cpwm_val = %x, CPWM = %x\n" + MSG_8852B_TASK_ERROR, //"Task Error: %wx\n" + MSG_8852B_GETMEDIASTS_1, //"GetMediaStatusbyMacid fail, macid = %bx!\n" + MSG_8852B_SETMEDIASTS_1, //"SetMediaStatusbyMacid: macid number >= 32, macid = %bx!\n" + MSG_8852B_SETMEDIASTS_2, //"SetMediaStatusbyMacid: Role_idx error, macid = %bx, role_idx = %bx!\n" + MSG_8852B_IPS_SET_CFG_ROLE_NOT_EXIST, //"[SetIpsCfg] role is not existed\n" + MSG_8852B_IPS_SET_CFG_DUPLICATE_ENABLE, //"[SetIpsCfg] IPS is already enabled! role_idx(%d)\n" + MSG_8852B_IPS_SET_CFG, //"[SetIpsCfg] macid(%d), Enable(%d)\n" + MSG_8852B_IPS_CHK_I1_COND_MATCH_1, //"=>ChkI1ConditionMatch\n" + MSG_8852B_IPS_CHK_I1_COND_MATCH_2, //"[ChkI1 no match] IpsDbgInfo = 0x%x\n" + MSG_8852B_IPS_CHANGE_IPS_STATE_INVALID_REQ_STATE, //"[ChangeIpsState] Invalid req_state = %d\n" + MSG_8852B_IPS_CHANGE_STATE_BY_CONDITION, //"[ChangeIPSStateByCondition] REQ State: %d, Cur State: %d\n" + MSG_8852B_PS_TRX_REQ_ROLE_NOT_EXIST, //"[ERR] [PsTRxReq] role(%d) is not existed!\n" + MSG_8852B_PS_TRX_REQ, //"[PsTRxReq] %d. role(%d), feature(%d), en(%d)\n" + MSG_8852B_PS_TRX_REQ_DISABLE_ERR, //"[ERR] [PsTRxReq] %d. role(%d), feature(%d) Tx has been disabled!\n" + MSG_8852B_ROLE_22, //"[FAIL] Role info - IpsParm alloc fail!\n" + MSG_8852B_OUTSRC_START = 20000, // "out source delimiter start" + MSG_8852B_OUTSRC_BB_SURA_0, //"[RA]RateChange=%x\n" + MSG_8852B_OUTSRC_BB_SURA_1, //"[RA]RDth=0x%x,RUth=0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_2, //"[RA]r4=100\n" + MSG_8852B_OUTSRC_BB_SURA_3, //"[RA]ForceRD\n" + MSG_8852B_OUTSRC_BB_SURA_4, //"[RA]RDCnt=0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_5, //"[RA]RUCnt=0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_6, //"[RA]RS\n" + MSG_8852B_OUTSRC_BB_SURA_7, //"[RA]SGIRD\n" + MSG_8852B_OUTSRC_BB_SURA_8, //"[RA]BWRD\n" + MSG_8852B_OUTSRC_BB_SURA_9, //"[RA]RDToLowest1\n" + MSG_8852B_OUTSRC_BB_SURA_10, //"[RA]RDToLowest2\n" + MSG_8852B_OUTSRC_BB_SURA_11, //"[RA]RD:crate=0x%x,mrate0=0x%x,mrate1=0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_12, //"[RA]rate=0x%x,bw:0x%x,rate2=0x%x,bw2:0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_13, //"[RA]Hit:bw=0x%x->0x%x,rate=0x%x->0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_14, //"[RA]SR:rate0=0x%x,rate1=0x%x,rate2=0x%x,cnt=0x%x\n" + MSG_8852B_OUTSRC_BB_SURA_15, //"RSVD\n" + MSG_8852B_OUTSRC_BB_SURA_16, //"[RA]SGIRU\n" + MSG_8852B_OUTSRC_BB_SURA_17, //"[RA]BWRU\n" + MSG_8852B_OUTSRC_BB_SURA_18, //"[RA]RUbw++\n" + MSG_8852B_OUTSRC_BB_SURA_19, //"[RA]RUToHighest\n" + MSG_8852B_OUTSRC_BB_SURA_20, //"[RA]NoUpRate\n" + MSG_8852B_OUTSRC_BB_SURA_21, //"[RA]RU:crate=%x,mrate0=%x,mrate1=%x\n" + MSG_8852B_OUTSRC_BB_SURA_22, //"[RA,W]macid:%x,mode:%x,rate_idx:%x,mcs:%x,ss:%x\n" + MSG_8852B_OUTSRC_BB_SURA_23, //"[RA][TRY]PER=%x,RDR=%x,R4=%x, pre_tp=%d, next_tp=%d\n" + MSG_8852B_OUTSRC_BB_SURA_24, //"[RA][TRY]R4=100,cnt=%x\n" + MSG_8852B_OUTSRC_BB_SURA_25, //"[RA][TRY]rate=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n" + MSG_8852B_OUTSRC_BB_SURA_26, //"[RA]TryFail\n" + MSG_8852B_OUTSRC_BB_SURA_27, //"[RA]TrySuccess\n" + MSG_8852B_OUTSRC_BB_SURA_28, //"[RA]MtTryIdx=%x\n" + MSG_8852B_OUTSRC_BB_SURA_29, //"[RA]TryFailCnt=%x,rate=%x,bw=%x\n" + MSG_8852B_OUTSRC_BB_SURA_30, //"[RA]DrvFixRate\n" + MSG_8852B_OUTSRC_BB_SURA_31, //"[RA]POLLUTED\n" + MSG_8852B_OUTSRC_BB_SURA_32, //"[RA]Tot=0\n" + MSG_8852B_OUTSRC_BB_SURA_33, //"[RA]Tx=0,Tot:%x,Ok:%x\n" + MSG_8852B_OUTSRC_BB_SURA_34, //"[RA]StaNull\n" + MSG_8852B_OUTSRC_BB_SURA_35, //"[RA]NoHESU\n" + MSG_8852B_OUTSRC_BB_SURA_36, //"[RA]WDNoRelease\n" + MSG_8852B_OUTSRC_BB_SURA_37, //"[RA]TxRptTot=%x\n" + MSG_8852B_OUTSRC_BB_SURA_38, //"[RA]Ovfl\n" + MSG_8852B_OUTSRC_BB_SURA_39, //"RSVD\n" + MSG_8852B_OUTSRC_BB_SURA_40, //"RSVD\n" + MSG_8852B_OUTSRC_BB_SURA_41, //"RSVD\n" + MSG_8852B_OUTSRC_BB_SURA_42, //"[RA]1 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n" + MSG_8852B_OUTSRC_BB_SURA_43, //"[RA]PER=%x,RDR=%x,r4=%x\n" + MSG_8852B_OUTSRC_BB_SURA_44, //"[RA]2 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n" + MSG_8852B_OUTSRC_BB_SURA_45, //"[RA]3 chk_rate_up_lmt OK: r_idx = %x, c_mcs = %x >= l_mcs = %x\n" + MSG_8852B_OUTSRC_BB_SURA_46, //"[RA]rate_changed=%x @ rate_check_for_update\n" + MSG_8852B_OUTSRC_BB_SURA_47, //"[RA]chk rate exist: rate_idx=%x->%x (%x,%x,%x)\n" + MSG_8852B_OUTSRC_BB_SURA_48, //"[RA]chk_rate_up_lmt=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n" + MSG_8852B_OUTSRC_BB_SURA_49, //"[RA]r_idx = %x => per_ma = %x, per_var == %x, decision_offset_n=%x, decision_offset_p=%x\n" + MSG_8852B_OUTSRC_BB_SURA_50, //"[RA]UpFailLimitCnt:%x,m_rtae_up_fail_cnt_lmt:%x\n" + MSG_8852B_OUTSRC_BB_SURA_51, //"[RA][txrpt]Txcnt=%x, Try=%x, total=%x, OK=%x, Initrate,Giltf=%x,%x, Finalrate,Giltf=%x,%x, BW=%x,wd_not_released=%x\n" + MSG_8852B_OUTSRC_BB_SURA_52, //"[RA][TBTT]ID=%x,Media:%x,Tot=%x,Ok=%x,OK=%x\n" + MSG_8852B_OUTSRC_BB_SURA_53, //"[RA][TBTT][FWfixrate]ID=%x,Media:%x,Tot=%x,Ok=%x,a-OK%x\n" + MSG_8852B_OUTSRC_BB_SURA_54, //"[RA]Sgi_pending_cnt = %x\n" + MSG_8852B_OUTSRC_BB_SURA_55, //"[RA][SGI]New rate = %x, Old gi = %x, New gi = %x\n" + MSG_8852B_OUTSRC_BB_SURA_56, //"[RA][H2C]Mode_sel=%x, gi_ltf=%x, dcm_cap=%x, er_cap=%x, init_rate_lv=%x, ldpc_cap=%x, stbc_cap=%x, arfr_ctrl=%x\n" + MSG_8852B_OUTSRC_BB_SURA_57, //"[RA][H2C]Initial_BW=%x, max_ss_support=%x\n" + MSG_8852B_OUTSRC_BB_SURA_58, //"[RA][H2C]Ra_mask0=%x, ra_mask1=%x, highest_rate=%x, max_start_rate=%x, lowest_rate=%x\n" + MSG_8852B_OUTSRC_BB_SURA_59, //"[RA][H2C]Initrate: rateidx=%x, mode=%x, gi_ltf=%x, bw_idx=%x\n" + MSG_8852B_OUTSRC_END, // "out source delimiter end" + MSG_8852B_LAST, //"Please add your log above." +}; +extern struct mac_fw_msg fw_log_8852b[]; +#endif //__HAL8852B_FW_LOG__ diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.c b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.c new file mode 100644 index 0000000..e86d5ed --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.c @@ -0,0 +1,98850 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../../type.h" + +#ifdef CONFIG_RTL8852B + +#ifdef PHL_FEATURE_AP + +#ifdef MAC_FW_8852B_U1 + +u8 array_8852b_u1_ap_mp[] = { +0x01, 0x01, 0x52, 0x88, 0x00, 0x04, 0x0D, 0x00, +0xC2, 0xD3, 0x89, 0x04, 0x20, 0x10, 0x40, 0x00, +0x05, 0x0B, 0x0E, 0x1B, 0xE5, 0x07, 0x00, 0x00, +0x00, 0x02, 0x20, 0x00, 0xF8, 0x07, 0x00, 0x00, +0x00, 0x00, 0x97, 0xB8, 0xC8, 0x07, 0x02, 0x12, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0xE1, 0xB8, 0x00, 0x37, 0x00, 0x11, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xFC, 0x63, 0x07, 0x62, 0xF7, 0xF0, 0x01, 0x6A, +0x40, 0x32, 0xF7, 0xF0, 0x01, 0x6C, 0xF7, 0xF0, +0x01, 0x6E, 0x40, 0x32, 0x80, 0x34, 0xC0, 0x36, +0x98, 0xF6, 0x5C, 0x9A, 0x80, 0x34, 0xC0, 0x36, +0x06, 0xF7, 0x00, 0x4C, 0x07, 0xF2, 0x04, 0x4E, +0x9B, 0xE6, 0x40, 0xEA, 0x00, 0x6D, 0xF7, 0xF0, +0x01, 0x6A, 0xF7, 0xF0, 0x01, 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0x8B, 0x85, 0x8C, 0x1A, +0x7A, 0x21, 0x23, 0xC4, 0xB4, 0x50, 0xC3, 0xFB, +0xBC, 0x37, 0x0C, 0x20, 0xC9, 0xBB, 0x28, 0xBD, +0xC6, 0x7D, 0x02, 0xF7, 0x39, 0x39, 0xE5, 0xA4, +0x72, 0x28, 0xC5, 0x23, 0x80, 0x1D, 0xA4, 0x89, +0x92, 0x12, 0x21, 0x4B, 0x36, 0xB5, 0x98, 0x48 +}; + +u32 array_length_8852b_u1_nic = 253560; + +#endif /*MAC_FW_8852B_U1*/ + +#ifdef MAC_FW_8852B_U1 + +u8 array_8852b_u1_nic_mp[] = { +0x01, 0x01, 0x52, 0x88, 0x00, 0x04, 0x0D, 0x00, +0xC2, 0xD3, 0x89, 0x04, 0x20, 0x10, 0x50, 0x00, +0x05, 0x0B, 0x0E, 0x1A, 0xE5, 0x07, 0x00, 0x00, +0x00, 0x03, 0x10, 0x00, 0xF8, 0x07, 0x00, 0x00, +0x00, 0x00, 0x97, 0xB8, 0xF0, 0x7F, 0x03, 0x02, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0xE1, 0xB8, 0x78, 0x5A, 0x00, 0x01, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x7C, 0xE1, 0xB8, 0xC0, 0x03, 0x00, 0x29, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xFC, 0x63, 0x07, 0x62, 0xF7, 0xF0, 0x01, 0x6A, +0x40, 0x32, 0xF7, 0xF0, 0x01, 0x6C, 0xF7, 0xF0, +0x01, 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array_length_8852b_u1_nic_mp = 253560; + +#endif /*MAC_FW_8852B_U1*/ + +#ifdef CONFIG_WOWLAN + +#ifdef MAC_FW_8852B_U1 + +u8 array_8852b_u1_wowlan[] = { +0x01, 0x01, 0x52, 0x88, 0x00, 0x04, 0x0D, 0x00, +0xC2, 0xD3, 0x89, 0x04, 0x20, 0x10, 0x50, 0x00, +0x05, 0x0B, 0x0E, 0x1A, 0xE5, 0x07, 0x00, 0x00, +0x00, 0x03, 0x30, 0x00, 0xF8, 0x07, 0x00, 0x00, +0x00, 0x00, 0x97, 0xB8, 0xE8, 0xDC, 0x01, 0x02, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0xE1, 0xB8, 0xF0, 0x31, 0x00, 0x01, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x7C, 0xE1, 0xB8, 0xC0, 0x03, 0x00, 0x29, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xFC, 0x63, 0x07, 0x62, 0xF7, 0xF0, 0x01, 0x6A, +0x40, 0x32, 0xF7, 0xF0, 0x01, 0x6C, 0xF7, 0xF0, +0x01, 0x6E, 0x40, 0x32, 0x80, 0x34, 0xC0, 0x36, +0x98, 0xF6, 0x5C, 0x9A, 0x80, 0x34, 0xC0, 0x36, +0xE6, 0xF1, 0x10, 0x4C, 0xE6, 0xF4, 0x14, 0x4E, +0x9B, 0xE6, 0x40, 0xEA, 0x00, 0x6D, 0xF7, 0xF0, +0x01, 0x6A, 0xF7, 0xF0, 0x01, 0x6D, 0x40, 0x32, +0xF7, 0xF0, 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0x34, 0xAB, 0xE6, 0xBE, 0xD0, 0x40, +0x4A, 0xF5, 0x68, 0xB1, 0x18, 0x3B, 0xEB, 0xB9, +0x3D, 0xF5, 0x4E, 0x1B, 0x12, 0x11, 0x65, 0xDC, +0x28, 0x68, 0x0B, 0x6A, 0xD3, 0x34, 0x24, 0x61, +0x33, 0x2E, 0xE0, 0x7A, 0x41, 0x7C, 0x11, 0xF2, +0xF0, 0x67, 0xFA, 0x4D, 0x8F, 0x1A, 0x9A, 0x42, +0xC8, 0xE7, 0xB4, 0xA6, 0x91, 0x97, 0x4F, 0xDB, +0xBC, 0x27, 0xBA, 0x76, 0xB7, 0x6F, 0x3D, 0xCB, +0x33, 0x55, 0xDC, 0xC3, 0x09, 0xBE, 0x0D, 0x60, +0xBD, 0x65, 0xB4, 0x9F, 0x46, 0x84, 0x81, 0xC7, +0x73, 0xA3, 0xFE, 0x1A, 0xC5, 0xB7, 0xA0, 0x6F, +0x35, 0x28, 0x21, 0x43, 0xFA, 0xB6, 0x4B, 0x74, +0x10, 0x9C, 0x4E, 0x55, 0x85, 0x31, 0x00, 0x57, +0x18, 0x34, 0xE0, 0xA5, 0x42, 0x18, 0x26, 0x3F, +0xD8, 0x52, 0x29, 0xE9, 0x48, 0x84, 0x45, 0xE8, +0x58, 0x2A, 0x0F, 0x3C, 0x3B, 0x31, 0xF0, 0x3C, +0x75, 0x50, 0x3B, 0x82, 0x50, 0x6D, 0xD1, 0x2E, +0xDB, 0xFA, 0x6B, 0x5B, 0xE5, 0x6E, 0x5A, 0xB4, +0x9B, 0xAA, 0x71, 0x8F, 0x98, 0x37, 0x63, 0x44, +0x23, 0x83, 0x03, 0xE1, 0xF6, 0x03, 0xF2, 0x54 +}; + +u32 array_length_8852b_u1_wowlan = 135912; + +#endif /*MAC_FW_8852B_U1*/ + +#endif /*CONFIG_WOWLAN*/ + +#endif /*PHL_FEATURE_NIC*/ + +#endif /*CONFIG_RTL8852B*/ diff --git a/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.h b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.h new file mode 100644 index 0000000..c4545ed --- /dev/null +++ b/phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifdef CONFIG_RTL8852B + +#ifdef PHL_FEATURE_AP +#ifdef MAC_FW_8852B_U1 +extern u8 array_8852b_u1_ap_mp[147224]; +extern u32 array_length_8852b_u1_ap_mp; +#endif /*MAC_FW_8852B_U1*/ +#endif /*PHL_FEATURE_AP*/ +#ifdef PHL_FEATURE_NIC +#ifdef MAC_FW_8852B_U1 +extern u8 array_8852b_u1_nic[253560]; +extern u32 array_length_8852b_u1_nic; +#endif /*MAC_FW_8852B_U1*/ +#ifdef MAC_FW_8852B_U1 +extern u8 array_8852b_u1_nic_mp[253560]; +extern u32 array_length_8852b_u1_nic_mp; +#endif /*MAC_FW_8852B_U1*/ +#ifdef CONFIG_WOWLAN +#ifdef MAC_FW_8852B_U1 +extern u8 array_8852b_u1_wowlan[135912]; +extern u32 array_length_8852b_u1_wowlan; +#endif /*MAC_FW_8852B_U1*/ +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + +#endif /*CONFIG_RTL8852B*/ + diff --git a/phl/hal_g6/mac/halmac_wpp.h b/phl/hal_g6/mac/halmac_wpp.h new file mode 100644 index 0000000..b59240e --- /dev/null +++ b/phl/hal_g6/mac/halmac_wpp.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALMAC_WPP_H__ +#define __HALMAC_WPP_H__ + +#define HALMAC_WPP_CONTROL_GUIDS \ + WPP_DEFINE_CONTROL_GUID( \ + halMacGuid, (9f9d9e5b, 3854, 4b87, 8bc6, 4ce1f284d34b), \ + WPP_DEFINE_BIT(COMP_HALMAC_MSG_INIT) \ + WPP_DEFINE_BIT(COMP_HALMAC_MSG_EFUSE) \ + WPP_DEFINE_BIT(COMP_HALMAC_MSG_FW) \ + WPP_DEFINE_BIT(COMP_HALMAC_MSG_H2C) \ + WPP_DEFINE_BIT(COMP_HALMAC_MSG_PWR) \ + ) +#endif /* __HALBB_TYPES_H__ */ diff --git a/phl/hal_g6/mac/hv_type.h b/phl/hal_g6/mac/hv_type.h new file mode 100644 index 0000000..6cc2050 --- /dev/null +++ b/phl/hal_g6/mac/hv_type.h @@ -0,0 +1,1093 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HV_AX_TYPE_H_ +#define _HV_AX_TYPE_H_ + +#include "pltfm_cfg.h" + +typedef unsigned long long u64; + +#define SS_LINK_SIZE 256 +#define DL_RUGRP_SIZE 8 +#define DL_MUTBL_SIZE 5 + +#define HV_AX_FPGA 0 +#define HV_AX_ASIC 1 + +/** + * @enum hv_ax_ss_wmm + * + * @brief hv_ax_ss_wmm + * + * @var hv_ax_ss_wmm::HV_AX_SS_WMM0 + * Please Place Description here. + * @var hv_ax_ss_wmm::HV_AX_SS_WMM1 + * Please Place Description here. + * @var hv_ax_ss_wmm::HV_AX_SS_WMM2 + * Please Place Description here. + * @var hv_ax_ss_wmm::HV_AX_SS_WMM3 + * Please Place Description here. + * @var hv_ax_ss_wmm::HV_AX_SS_UL + * Please Place Description here. + */ +enum hv_ax_ss_wmm { + HV_AX_SS_WMM0, + HV_AX_SS_WMM1, + HV_AX_SS_WMM2, + HV_AX_SS_WMM3, + HV_AX_SS_UL, +}; + +/** + * @enum hv_ax_freerun_cfg + * + * @brief hv_ax_freerun_cfg + * + * @var hv_ax_freerun_cfg::HV_AX_FREERUN_EN + * Please Place Description here. + * @var hv_ax_freerun_cfg::HV_AX_FREERUN_DIS + * Please Place Description here. + * @var hv_ax_freerun_cfg::HV_AX_FREERUN_RST + * Please Place Description here. + */ +enum hv_ax_freerun_cfg { + HV_AX_FREERUN_EN, + HV_AX_FREERUN_DIS, + HV_AX_FREERUN_RST, +}; + +/** + * @enum hv_ax_ss_quota_mode_cfg + * + * @brief hv_ax_ss_quota_mode_cfg + * + * @var hv_ax_ss_quota_mode_cfg::HV_AX_SS_QUOTA_MODE_GET + * Please Place Description here. + * @var hv_ax_ss_quota_mode_cfg::HV_AX_SS_QUOTA_MODE_SET + * Please Place Description here. + */ +enum hv_ax_ss_quota_mode_cfg { + HV_AX_SS_QUOTA_MODE_GET, + HV_AX_SS_QUOTA_MODE_SET, +}; + +/** + * @enum hv_ax_ss_wmm_tbl_cfg + * + * @brief hv_ax_ss_wmm_tbl_cfg + * + * @var hv_ax_ss_wmm_tbl_cfg::HV_AX_SS_WMM_TBL_SET + * Please Place Description here. + */ +enum hv_ax_ss_wmm_tbl_cfg { + HV_AX_SS_WMM_TBL_SET, +}; + +/** + * @enum hv_ax_sta_len_cmd + * + * @brief hv_ax_sta_len_cmd + * + * @var hv_ax_sta_len_cmd::HV_AX_STA_LEN_INCR + * Please Place Description here. + * @var hv_ax_sta_len_cmd::HV_AX_STA_LEN_DECR + * Please Place Description here. + */ +enum hv_ax_sta_len_cmd { + HV_AX_STA_LEN_INCR, + HV_AX_STA_LEN_DECR, +}; + +/** + * @enum hv_ax_sta_len_cfg + * + * @brief hv_ax_sta_len_cfg + * + * @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_GET + * Please Place Description here. + * @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_SET + * Please Place Description here. + * @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_GET_INDIR + * Please Place Description here. + * @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_SET_INDIR + * Please Place Description here. + */ +enum hv_ax_sta_len_cfg { + HV_AX_STA_LEN_CFG_GET, + HV_AX_STA_LEN_CFG_SET, + HV_AX_STA_LEN_CFG_GET_INDIR, + HV_AX_STA_LEN_CFG_SET_INDIR, +}; + +/** + * @enum hv_ax_sta_quota_cfg + * + * @brief hv_ax_sta_quota_cfg + * + * @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_VAL_GET + * Please Place Description here. + * @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_VAL_SET + * Please Place Description here. + * @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_SETTING_GET + * Please Place Description here. + * @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_SETTING_SET + * Please Place Description here. + */ +enum hv_ax_sta_quota_cfg { + HV_AX_STA_QUOTA_CFG_VAL_GET, + HV_AX_STA_QUOTA_CFG_VAL_SET, + HV_AX_STA_QUOTA_CFG_SETTING_GET, + HV_AX_STA_QUOTA_CFG_SETTING_SET, +}; + +/** + * @enum hv_ax_sta_muru_cfg + * + * @brief hv_ax_sta_muru_cfg + * + * @var hv_ax_sta_muru_cfg::HV_AX_STA_MURU_CFG_GET + * Please Place Description here. + * @var hv_ax_sta_muru_cfg::HV_AX_STA_MURU_CFG_SET + * Please Place Description here. + */ +enum hv_ax_sta_muru_cfg { + HV_AX_STA_MURU_CFG_GET, + HV_AX_STA_MURU_CFG_SET, +}; + +/** + * @enum hv_ax_ss_quota_mode + * + * @brief hv_ax_ss_quota_mode + * + * @var hv_ax_ss_quota_mode::HV_AX_SS_QUOTA_MODE_TIME + * Please Place Description here. + * @var hv_ax_ss_quota_mode::HV_AX_SS_QUOTA_MODE_CNT + * Please Place Description here. + */ +enum hv_ax_ss_quota_mode { + HV_AX_SS_QUOTA_MODE_TIME = 0, + HV_AX_SS_QUOTA_MODE_CNT = 1, +}; + +/** + * @enum hv_ax_ss_link_cfg + * + * @brief hv_ax_ss_link_cfg + * + * @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_GET + * Please Place Description here. + * @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_ADD + * Please Place Description here. + * @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_DEL + * Please Place Description here. + * @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_CLEAN + * Please Place Description here. + */ +enum hv_ax_ss_link_cfg { + HV_AX_SS_LINK_CFG_GET, + HV_AX_SS_LINK_CFG_ADD, + HV_AX_SS_LINK_CFG_DEL, + HV_AX_SS_LINK_CFG_CLEAN, +}; + +/** + * @enum hv_ax_sta_bmp_cfg + * + * @brief hv_ax_sta_bmp_cfg + * + * @var hv_ax_sta_bmp_cfg::HV_AX_STA_BMP_CFG_GET + * Please Place Description here. + * @var hv_ax_sta_bmp_cfg::HV_AX_STA_BMP_CFG_SET + * Please Place Description here. + */ +enum hv_ax_sta_bmp_cfg { + HV_AX_STA_BMP_CFG_GET, + HV_AX_STA_BMP_CFG_SET, +}; + +/** + * @enum hv_ax_ss_rpt_cfg + * + * @brief hv_ax_ss_rpt_cfg + * + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_UL_RPT_CFG_GET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_UL_RPT_CFG_SET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_SU_RPT_CFG_GET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_SU_RPT_CFG_SET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_MU_RPT_CFG_GET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_MU_RPT_CFG_SET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_RU_RPT_CFG_GET + * Please Place Description here. + * @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_RU_RPT_CFG_SET + * Please Place Description here. + */ +enum hv_ax_ss_rpt_cfg { + HV_AX_SS_UL_RPT_CFG_GET, + HV_AX_SS_UL_RPT_CFG_SET, + HV_AX_SS_DL_SU_RPT_CFG_GET, + HV_AX_SS_DL_SU_RPT_CFG_SET, + HV_AX_SS_DL_MU_RPT_CFG_GET, + HV_AX_SS_DL_MU_RPT_CFG_SET, + HV_AX_SS_DL_RU_RPT_CFG_GET, + HV_AX_SS_DL_RU_RPT_CFG_SET, +}; + +/** + * @enum hv_ax_ss_rpt_path_cfg + * + * @brief hv_ax_ss_rpt_path_cfg + * + * @var hv_ax_ss_rpt_path_cfg::HV_AX_SS_RPT_PATH_CPU + * Please Place Description here. + * @var hv_ax_ss_rpt_path_cfg::HV_AX_SS_RPT_PATH_HOST + * Please Place Description here. + */ +enum hv_ax_ss_rpt_path_cfg { + HV_AX_SS_RPT_PATH_CPU, + HV_AX_SS_RPT_PATH_HOST, +}; + +/** + * @enum hv_ax_ss_dlru_search_mode + * + * @brief hv_ax_ss_dlru_search_mode + * + * @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LINK_THEN_AC + * Please Place Description here. + * @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_AC + * Please Place Description here. + * @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LINK_THEN_LEN + * Please Place Description here. + * @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LEN + * Please Place Description here. + */ +enum hv_ax_ss_dlru_search_mode { + HV_AX_SS_DLRU_SEARCH_LINK_THEN_AC = 0, + HV_AX_SS_DLRU_SEARCH_AC = 1, + HV_AX_SS_DLRU_SEARCH_LINK_THEN_LEN = 2, + HV_AX_SS_DLRU_SEARCH_LEN = 3, +}; + +/** + * @enum hv_ax_ss_delay_tx_band + * + * @brief hv_ax_ss_delay_tx_band + * + * @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_DIS + * Please Place Description here. + * @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B0 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B1 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B0_B1 + * Please Place Description here. + */ +enum hv_ax_ss_delay_tx_band { + HV_AX_SS_DELAY_TX_DIS = 0, + HV_AX_SS_DELAY_TX_B0 = 1, + HV_AX_SS_DELAY_TX_B1 = 2, + HV_AX_SS_DELAY_TX_B0_B1 = 3, +}; + +/** + * @enum mac_ax_plat_module + * + * @brief mac_ax_plat_module + * + * @var mac_ax_plat_module::SPIC + * Please Place Description here. + * @var mac_ax_plat_module::CPU_PLATFORM + * Please Place Description here. + * @var mac_ax_plat_module::EFUSE_CTRL + * Please Place Description here. + * @var mac_ax_plat_module::IDDMA + * Please Place Description here. + * @var mac_ax_plat_module::AXIDMA + * Please Place Description here. + * @var mac_ax_plat_module::IPSEC + * Please Place Description here. + * @var mac_ax_plat_module::UART + * Please Place Description here. + * @var mac_ax_plat_module::HIOE + * Please Place Description here. + * @var mac_ax_plat_module::WATCHDOG + * Please Place Description here. + * @var mac_ax_plat_module::SECURITY + * Please Place Description here. + * @var mac_ax_plat_module::PLAT_MODULE_MAX + * Please Place Description here. + */ +enum mac_ax_plat_module { + SPIC, + CPU_PLATFORM, + EFUSE_CTRL, + IDDMA, + AXIDMA, + IPSEC, + UART, + HIOE, + WATCHDOG, + SECURITY, + PLAT_MODULE_MAX +}; + +/** + * @struct hv_ax_lifetime_mg2_cfg + * @brief hv_ax_lifetime_mg2_cfg + * + * @var hv_ax_lifetime_mg2_cfg::band + * Please Place Description here. + * @var hv_ax_lifetime_mg2_cfg::en + * Please Place Description here. + * @var hv_ax_lifetime_mg2_cfg::val + * Please Place Description here. + */ +struct hv_ax_lifetime_mg2_cfg { + u8 band; + u8 en; + u16 val; +}; + +/** + * @struct hv_ax_ss_delay_tx_info + * @brief hv_ax_ss_delay_tx_info + * + * @var hv_ax_ss_delay_tx_info::band_sel + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::vovi_to_0 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::bebk_to_0 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::vovi_to_1 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::bebk_to_1 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::vovi_len_0 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::bebk_len_0 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::vovi_len_1 + * Please Place Description here. + * @var hv_ax_ss_delay_tx_info::bebk_len_1 + * Please Place Description here. + */ +struct hv_ax_ss_delay_tx_info { + enum hv_ax_ss_delay_tx_band band_sel; + u8 vovi_to_0; + u8 bebk_to_0; + u8 vovi_to_1; + u8 bebk_to_1; + u8 vovi_len_0; + u8 bebk_len_0; + u8 vovi_len_1; + u8 bebk_len_1; +}; + +/** + * @struct hv_ax_ss_search_info + * @brief hv_ax_ss_search_info + * + * @var hv_ax_ss_search_info::wmm + * Please Place Description here. + * @var hv_ax_ss_search_info::ac + * Please Place Description here. + * @var hv_ax_ss_search_info::ul + * Please Place Description here. + * @var hv_ax_ss_search_info::twt_grp + * Please Place Description here. + * @var hv_ax_ss_search_info::mode_sel + * Please Place Description here. + * @var hv_ax_ss_search_info::macid + * Please Place Description here. + * @var hv_ax_ss_search_info::search_fail + * Please Place Description here. + */ +struct hv_ax_ss_search_info { + u8 wmm; + u8 ac; + u8 ul; + u8 twt_grp; + u8 mode_sel; + u8 macid; + u8 search_fail; +}; + +/** + * @struct hv_ax_ss_dl_rpt_info + * @brief hv_ax_ss_dl_rpt_info + * + * @var hv_ax_ss_dl_rpt_info::wmm0_max + * Please Place Description here. + * @var hv_ax_ss_dl_rpt_info::wmm1_max + * Please Place Description here. + * @var hv_ax_ss_dl_rpt_info::twt_wmm0_max + * Please Place Description here. + * @var hv_ax_ss_dl_rpt_info::twt_wmm1_max + * Please Place Description here. + */ +struct hv_ax_ss_dl_rpt_info { + u8 wmm0_max; + u8 wmm1_max; + u8 twt_wmm0_max; + u8 twt_wmm1_max; +}; + +/** + * @struct hv_ax_ss_ul_rpt_info + * @brief hv_ax_ss_ul_rpt_info + * + * @var hv_ax_ss_ul_rpt_info::ul_wmm_sel + * Please Place Description here. + * @var hv_ax_ss_ul_rpt_info::ul_su_max + * Please Place Description here. + * @var hv_ax_ss_ul_rpt_info::twt_ul_su_max + * Please Place Description here. + * @var hv_ax_ss_ul_rpt_info::ul_ru_max + * Please Place Description here. + */ +struct hv_ax_ss_ul_rpt_info { + u8 ul_wmm_sel; + u8 ul_su_max; + u8 twt_ul_su_max; + u8 ul_ru_max; +}; + +/** + * @struct hv_ax_ss_link_info + * @brief hv_ax_ss_link_info + * + * @var hv_ax_ss_link_info::wmm + * Please Place Description here. + * @var hv_ax_ss_link_info::ac + * Please Place Description here. + * @var hv_ax_ss_link_info::ul + * Please Place Description here. + * @var hv_ax_ss_link_info::link_list + * Please Place Description here. + * @var hv_ax_ss_link_info::link_head + * Please Place Description here. + * @var hv_ax_ss_link_info::link_tail + * Please Place Description here. + * @var hv_ax_ss_link_info::link_len + * Please Place Description here. + * @var hv_ax_ss_link_info::macid0 + * Please Place Description here. + * @var hv_ax_ss_link_info::macid1 + * Please Place Description here. + * @var hv_ax_ss_link_info::macid2 + * Please Place Description here. + * @var hv_ax_ss_link_info::link_bitmap + * Please Place Description here. + */ +struct hv_ax_ss_link_info { + u8 wmm; + u8 ac; + u8 ul; + u8 link_list[SS_LINK_SIZE]; + u8 link_head; + u8 link_tail; + u8 link_len; + u8 macid0; + u8 macid1; + u8 macid2; + u8 link_bitmap[SS_LINK_SIZE]; +}; + +/** + * @struct hv_ax_sta_dl_rugrp_ctrl + * @brief hv_ax_sta_dl_rugrp_ctrl + * + * @var hv_ax_sta_dl_rugrp_ctrl::grpid + * Please Place Description here. + * @var hv_ax_sta_dl_rugrp_ctrl::grp_vld + * Please Place Description here. + * @var hv_ax_sta_dl_rugrp_ctrl::macid + * Please Place Description here. + * @var hv_ax_sta_dl_rugrp_ctrl::dis_ac + * Please Place Description here. + */ +struct hv_ax_sta_dl_rugrp_ctrl { + u8 grpid; + u8 grp_vld; + u8 macid[DL_RUGRP_SIZE]; + u8 dis_ac[DL_RUGRP_SIZE]; +}; + +/** + * @struct hv_ax_sta_dl_mutbl_ctrl + * @brief hv_ax_sta_dl_mutbl_ctrl + * + * @var hv_ax_sta_dl_mutbl_ctrl::tbl_id + * Please Place Description here. + * @var hv_ax_sta_dl_mutbl_ctrl::tbl_vld + * Please Place Description here. + * @var hv_ax_sta_dl_mutbl_ctrl::macid + * Please Place Description here. + * @var hv_ax_sta_dl_mutbl_ctrl::score + * Please Place Description here. + */ +struct hv_ax_sta_dl_mutbl_ctrl { + u8 tbl_id; + u8 tbl_vld; + u8 macid; + u8 score[DL_MUTBL_SIZE]; +}; + +/** + * @struct hv_ax_ss_quota_mode_ctrl + * @brief hv_ax_ss_quota_mode_ctrl + * + * @var hv_ax_ss_quota_mode_ctrl::wmm + * Please Place Description here. + * @var hv_ax_ss_quota_mode_ctrl::mode + * Please Place Description here. + */ +struct hv_ax_ss_quota_mode_ctrl { + enum hv_ax_ss_wmm wmm; + enum hv_ax_ss_quota_mode mode; +}; + +/** + * @struct hv_ax_sta_muru_ctrl + * @brief hv_ax_sta_muru_ctrl + * + * @var hv_ax_sta_muru_ctrl::macid + * Please Place Description here. + * @var hv_ax_sta_muru_ctrl::ul_tbl + * Please Place Description here. + * @var hv_ax_sta_muru_ctrl::dl_muru_dis + * Please Place Description here. + */ +struct hv_ax_sta_muru_ctrl { + u8 macid; + u32 ul_tbl; + u32 dl_muru_dis; +}; + +/** + * @struct hv_ax_sta_bmp_ctrl + * @brief hv_ax_sta_bmp_ctrl + * + * @var hv_ax_sta_bmp_ctrl::macid + * Please Place Description here. + * @var hv_ax_sta_bmp_ctrl::bmp + * Please Place Description here. + * @var hv_ax_sta_bmp_ctrl::mask + * Please Place Description here. + */ +struct hv_ax_sta_bmp_ctrl { + u8 macid; + u32 bmp; + u32 mask; +}; + +/** + * @struct hv_ax_sta_quota + * @brief hv_ax_sta_quota + * + * @var hv_ax_sta_quota::macid + * Please Place Description here. + * @var hv_ax_sta_quota::vo_quota + * Please Place Description here. + * @var hv_ax_sta_quota::vi_quota + * Please Place Description here. + * @var hv_ax_sta_quota::be_quota + * Please Place Description here. + * @var hv_ax_sta_quota::bk_quota + * Please Place Description here. + * @var hv_ax_sta_quota::ul_quota + * Please Place Description here. + */ +struct hv_ax_sta_quota { + u8 macid; + u32 vo_quota; + u32 vi_quota; + u32 be_quota; + u32 bk_quota; + u32 ul_quota; +}; + +/** + * @struct hv_ax_sta_len_ctrl + * @brief hv_ax_sta_len_ctrl + * + * @var hv_ax_sta_len_ctrl::macid + * Please Place Description here. + * @var hv_ax_sta_len_ctrl::len + * Please Place Description here. + * @var hv_ax_sta_len_ctrl::ac + * Please Place Description here. + * @var hv_ax_sta_len_ctrl::cmd + * Please Place Description here. + */ +struct hv_ax_sta_len_ctrl { + u8 macid; + u32 len; + enum mac_ax_cmac_ac_sel ac; + enum hv_ax_sta_len_cmd cmd; +}; + +/** + * @struct hv_ax_sta_len + * @brief hv_ax_sta_len + * + * @var hv_ax_sta_len::macid + * Please Place Description here. + * @var hv_ax_sta_len::vo_len + * Please Place Description here. + * @var hv_ax_sta_len::vi_len + * Please Place Description here. + * @var hv_ax_sta_len::be_len + * Please Place Description here. + * @var hv_ax_sta_len::bk_len + * Please Place Description here. + * @var hv_ax_sta_len::bsr_len + * Please Place Description here. + * @var hv_ax_sta_len::bsr_ac_type + * Please Place Description here. + */ +struct hv_ax_sta_len { + u8 macid; + u32 vo_len; + u32 vi_len; + u32 be_len; + u32 bk_len; + u32 bsr_len; + u8 bsr_ac_type; +}; + +/** + * @struct hv_aggregator_t + * @brief hv_aggregator_t + * + * @var hv_aggregator_t::pkt + * Please Place Description here. + * @var hv_aggregator_t::len + * Please Place Description here. + * @var hv_aggregator_t::agg_num + * Please Place Description here. + */ +struct hv_aggregator_t { + u8 *pkt; + u32 len; + u32 agg_num; +}; + +/** + * @struct hv_dbg_port + * @brief hv_dbg_port + * + * @var hv_dbg_port::info + * Please Place Description here. + * @var hv_dbg_port::len + * Please Place Description here. + * @var hv_dbg_port::read_addr + * Please Place Description here. + * @var hv_dbg_port::sel_addr + * Please Place Description here. + * @var hv_dbg_port::dbg_sel + * Please Place Description here. + */ +struct hv_dbg_port { + struct hv_dbg_port_info *info; + u32 len; + u32 read_addr; + u32 sel_addr; + u32 dbg_sel; +}; + +/** + * @struct hv_dbg_port_info + * @brief hv_dbg_port_info + * + * @var hv_dbg_port_info::addr + * Please Place Description here. + * @var hv_dbg_port_info::val + * Please Place Description here. + */ +struct hv_dbg_port_info { + u32 addr; + u32 val; +}; + +/** + * @struct mac_ax_mac_test + * @brief mac_ax_mac_test + * + * @var mac_ax_mac_test::dword0 + * Please Place Description here. + * @var mac_ax_mac_test::dword1 + * Please Place Description here. + */ +struct mac_ax_mac_test { + u32 dword0; + u32 dword1; +}; + +/** + * @struct mac_ax_plat_auto_test + * @brief mac_ax_plat_auto_test + * + * @var mac_ax_plat_auto_test::dword0 + * Please Place Description here. + * @var mac_ax_plat_auto_test::dword1 + * Please Place Description here. + * @var mac_ax_plat_auto_test::dword2 + * Please Place Description here. + * @var mac_ax_plat_auto_test::dword3 + * Please Place Description here. + * @var mac_ax_plat_auto_test::dword4 + * Please Place Description here. + * @var mac_ax_plat_auto_test::dword5 + * Please Place Description here. + */ +struct mac_ax_plat_auto_test { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +/** + * @struct hv_ctrl_frame_cnt + * @brief hv_ctrl_frame_cnt + * + * @var hv_ctrl_frame_cnt::band + * Please Place Description here. + * @var hv_ctrl_frame_cnt::op + * Please Place Description here. + * @var hv_ctrl_frame_cnt::stype + * Please Place Description here. + * @var hv_ctrl_frame_cnt::idx + * Please Place Description here. + * @var hv_ctrl_frame_cnt::rval + * Please Place Description here. + * @var hv_ctrl_frame_cnt::tval + * Please Place Description here. + */ +struct hv_ctrl_frame_cnt { +#define MAC_HV_CTRL_CNT_R 0 +#define MAC_HV_CTRL_CNT_W 1 +#define MAC_HV_CTRL_CNT_RST 2 +#define MAC_HV_CTRL_CNT_RST_ALL 3 + u8 band; + u8 op; + u8 stype; +#define MAC_HV_CTRL_CNT_NUM 16 + u8 idx; + u16 rval; + u16 tval; +}; + +/** + * @struct hv_rx_cnt + * @brief hv_rx_cnt + * + * @var hv_rx_cnt::op + * Please Place Description here. + * @var hv_rx_cnt::idx + * Please Place Description here. + * @var hv_rx_cnt::band + * Please Place Description here. + * @var hv_rx_cnt::type + * Please Place Description here. + * @var hv_rx_cnt::val + * Please Place Description here. + * @var hv_rx_cnt::subtype + * Please Place Description here. + * @var hv_rx_cnt::bssid + * Please Place Description here. + * @var hv_rx_cnt::rate + * Please Place Description here. + * @var hv_rx_cnt::gi_ltf + * Please Place Description here. + * @var hv_rx_cnt::ru + * Please Place Description here. + * @var hv_rx_cnt::msk + * Please Place Description here. + */ +struct hv_rx_cnt { +#define MAC_HV_RX_CNT_R 0 +#define MAC_HV_RX_CNT_W 1 +#define MAC_HV_RX_CNT_RST 2 + u8 op; +#define MAC_HV_RX_CNT_NUM 48 + u8 idx; + u8 band; + u8 type; + u16 val; + u8 subtype; + u8 bssid; + u16 rate; + u8 gi_ltf; + u8 ru; +#define MAC_HV_RX_CNT_MSK_FC BIT(0) +#define MAC_HV_RX_CNT_MSK_BSSID BIT(1) +#define MAC_HV_RX_CNT_MSK_RATE BIT(2) +#define MAC_HV_RX_CNT_MSK_RU BIT(3) + u8 msk; +}; + +struct hv_txpkt_info { + u8 null_0; + u8 null_1; + u8 tri_frame; + u8 ht_data_snd; + u8 chk_en; + u16 ndpa_dur; +}; + +/** + * @struct hv_ax_ops + * @brief hv_ax_ops + * + * @var hv_ax_ops::tx_post_desc + * Please Place Description here. + * @var hv_ax_ops::get_ppdu + * Please Place Description here. + * @var hv_ax_ops::chk_ps_dfs + * Please Place Description here. + * @var hv_ax_ops::chk_ps_ppdu + * Please Place Description here. + * @var hv_ax_ops::chk_ps_ch_info + * Please Place Description here. + * @var hv_ax_ops::phy_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_bmp_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_len_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_dl_rugrp_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_muru_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_quota_cfg + * Please Place Description here. + * @var hv_ax_ops::sta_link_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_dl_rpt_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_ul_rpt_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_query_search + * Please Place Description here. + * @var hv_ax_ops::ss_rpt_path_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_set_bsr_thold + * Please Place Description here. + * @var hv_ax_ops::ss_dlru_search_mode + * Please Place Description here. + * @var hv_ax_ops::ss_set_delay_tx + * Please Place Description here. + * @var hv_ax_ops::sta_dl_mutbl_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_dlmu_search_mode + * Please Place Description here. + * @var hv_ax_ops::ss_quota_mode + * Please Place Description here. + * @var hv_ax_ops::get_dbg_port_info + * Please Place Description here. + * @var hv_ax_ops::get_dle_dfi_info + * Please Place Description here. + * @var hv_ax_ops::ss_wmm_tbl_cfg + * Please Place Description here. + * @var hv_ax_ops::ss_wmm_sta_move + * Please Place Description here. + * @var hv_ax_ops::ss_set_wmm_bmp + * Please Place Description here. + * @var hv_ax_ops::cfg_btc_dbg_port + * Please Place Description here. + * @var hv_ax_ops::en_btc_rtk_mode + * Please Place Description here. + * @var hv_ax_ops::set_ctrl_frame_cnt + * Please Place Description here. + * @var hv_ax_ops::set_rx_cnt + * Please Place Description here. + * @var hv_ax_ops::set_freerun_cfg + * Please Place Description here. + * @var hv_ax_ops::get_freerun_info + * Please Place Description here. + * @var hv_ax_ops::set_lifetime_mg2 + * Please Place Description here. + * @var hv_ax_ops::get_lifetime_mg2 + * Please Place Description here. + * @var hv_ax_ops::ptn_h2c_common + * Please Place Description here. + * @var hv_ax_ops::get_mac_err_isr + * Please Place Description here. + * @var hv_ax_ops::get_gpio_status + * Please Place Description here. + * @var hv_ax_ops::get_gpio_val + * Please Place Description here. + */ +struct hv_ax_ops { + u32 (*tx_post_desc)(struct mac_ax_adapter *adapter, + struct hv_aggregator_t *agg); + u32 (*get_ppdu)(struct mac_ax_adapter *adapter, enum mac_ax_band band); + u32 (*chk_ps_dfs)(struct mac_ax_adapter *adapter, u8 *data, u32 len); + u32 (*chk_ps_ppdu)(struct mac_ax_adapter *adapter, u8 *data, u32 len); + u32 (*chk_ps_ch_info)(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + u32 (*phy_cfg)(struct mac_ax_adapter *adapter); + u32 (*sta_bmp_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_bmp_ctrl *ctrl, + enum hv_ax_sta_bmp_cfg cfg); + u32 (*sta_len_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_len *len, + enum hv_ax_sta_len_cfg cfg); + u32 (*sta_dl_rugrp_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_dl_rugrp_ctrl *rugrp, + enum hv_ax_sta_muru_cfg cfg); + u32 (*sta_muru_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_muru_ctrl *muru, + enum hv_ax_sta_muru_cfg cfg); + u32 (*sta_quota_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_quota *quota, + enum hv_ax_sta_quota_cfg cfg); + u32 (*sta_link_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_link_info *link, + enum hv_ax_ss_link_cfg cfg); + void (*ss_dl_rpt_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_dl_rpt_info *info, + enum hv_ax_ss_rpt_cfg cfg); + void (*ss_ul_rpt_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_ul_rpt_info *info, + enum hv_ax_ss_rpt_cfg cfg); + u32 (*ss_query_search)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_search_info *info); + void (*ss_rpt_path_cfg)(struct mac_ax_adapter *adapter, + enum hv_ax_ss_rpt_path_cfg cfg); + void (*ss_set_bsr_thold)(struct mac_ax_adapter *adapter, u16 thold_0, + u16 thold_1); + void (*ss_dlru_search_mode)(struct mac_ax_adapter *adapter, + enum hv_ax_ss_dlru_search_mode mode); + void (*ss_set_delay_tx)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_delay_tx_info *info); + u32 (*sta_dl_mutbl_cfg)(struct mac_ax_adapter *adapter, + struct hv_ax_sta_dl_mutbl_ctrl *mutbl, + enum hv_ax_sta_muru_cfg cfg); + void (*ss_dlmu_search_mode)(struct mac_ax_adapter *adapter, u8 mode, + u8 score_thr); + u32 (*ss_quota_mode)(struct mac_ax_adapter *adapter, + struct hv_ax_ss_quota_mode_ctrl *ctrl, + enum hv_ax_ss_quota_mode_cfg cfg); + u32 (*get_dbg_port_info)(struct mac_ax_adapter *adapter, + struct hv_dbg_port *dbg); + u32 (*get_dle_dfi_info)(struct mac_ax_adapter *adapter, + struct hv_dbg_port *dbg); + void (*ss_wmm_tbl_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_ss_wmm_tbl_ctrl *ctrl, + enum hv_ax_ss_wmm_tbl_cfg cfg); + u32 (*ss_wmm_sta_move)(struct mac_ax_adapter *adapter, + enum hv_ax_ss_wmm src_wmm, + enum mac_ax_ss_wmm_tbl dst_link); + u32 (*ss_set_wmm_bmp)(struct mac_ax_adapter *adapter, u8 wmm, u8 macid); + u32 (*cfg_btc_dbg_port)(struct mac_ax_adapter *adapter); + u32 (*en_btc_rtk_mode)(struct mac_ax_adapter *adapter); + u32 (*set_ctrl_frame_cnt)(struct mac_ax_adapter *adapter, + struct hv_ctrl_frame_cnt *ctrl); + u32 (*set_rx_cnt)(struct mac_ax_adapter *adapter, + struct hv_rx_cnt *cnt); + u32 (*set_freerun_cfg)(struct mac_ax_adapter *adapter, + enum hv_ax_freerun_cfg cfg); + u32 (*get_freerun_info)(struct mac_ax_adapter *adapter, u32 *cnt_low, + u32 *cnt_high); + u32 (*set_lifetime_mg2)(struct mac_ax_adapter *adapter, + struct hv_ax_lifetime_mg2_cfg *cfg); + u32 (*get_lifetime_mg2)(struct mac_ax_adapter *adapter, + struct hv_ax_lifetime_mg2_cfg *cfg); + u32 (*ptn_h2c_common)(struct mac_ax_adapter *adapter, + struct rtw_g6_h2c_hdr *hdr, + u32 *pvalue); + u32 (*get_mac_err_isr)(struct mac_ax_adapter *adapter); + u32 (*get_gpio_status)(struct mac_ax_adapter *adapter, + enum rtw_mac_gfunc *func, u8 gpio); + u32 (*get_gpio_val)(struct mac_ax_adapter *adapter, u8 gpio, u8 *val); + u32 (*get_rxd_drv_info_unit)(struct mac_ax_adapter *adapter); + u32 (*get_ampdu_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_ampdu_cfg *cfg); + u32 (*get_edca_param)(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param); + u32 (*get_muedca_param)(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_param *param); + u32 (*get_muedca_timer)(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_timer *timer); + u32 (*get_muedca_ctrl)(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_cfg *cfg); + u32 (*get_ch_stat_cnt)(struct mac_ax_adapter *adapter, + struct mac_ax_ch_stat_cnt *cnt); + u32 (*get_lifetime_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_lifetime_cfg *cfg); + u32 (*get_hw_edcca_param)(struct mac_ax_adapter *adapter, + struct mac_ax_edcca_param *param); + u32 (*set_ofld_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_ofld_cfg *param); + u32 (*get_macid_pause)(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_cfg *cfg); + u32 (*get_hw_sch_tx_en)(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *cfg); + u32 (*set_hw_muedca_timer)(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_timer *timer); + u32 (*set_hw_ch_busy_cnt)(struct mac_ax_adapter *adapter, + struct mac_ax_ch_busy_cnt_cfg *cfg); +}; + +#endif + +/** + * @brief mac_plat_auto_test + * + * @param *adapter + * @param *info + * @param test_module + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_plat_auto_test(struct mac_ax_adapter *adapter, + struct mac_ax_plat_auto_test *info, + enum mac_ax_plat_module test_module); + +/** + * @brief mac_long_run_test + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_long_run_test(struct mac_ax_adapter *adapter, + struct mac_ax_mac_test *info); + +/** + * @brief mac_flash_burn_test + * + * @param *adapter + * @param *fw + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_flash_burn_test(struct mac_ax_adapter *adapter, + u8 *fw, u32 len); diff --git a/phl/hal_g6/mac/mac.mk b/phl/hal_g6/mac/mac.mk new file mode 100644 index 0000000..5e9cc4f --- /dev/null +++ b/phl/hal_g6/mac/mac.mk @@ -0,0 +1,128 @@ +# All needed files would be added to _HAL_INTFS_FILES, and it would include +# hal/hal_halmac.c and all related files in directory hal/halmac/. +# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC +# (CONFIG_RTL*) setting are all ready! + +HAL = hal_g6 + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/hal_g6 +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := hal_g6 +phl_path_d1 := $(src)/$(HAL) +endif + +# Base directory +path_hm := $(phl_path)/mac +# Level 1 directory +path_hm_d1 := $(path_hm)/mac_ax +path_fw_d1 := $(path_hm)/fw_ax + +ifeq ($(CONFIG_PCI_HCI), y) +pci := y +endif +ifeq ($(CONFIG_SDIO_HCI), y) +sdio := y +endif +ifeq ($(CONFIG_USB_HCI), y) +usb := y +endif + +halmac-y += $(path_hm)/mac_ax.o + +# Modify level 1 directory if needed +# $(path_hm_d1)/fwdl.o + +halmac-y += $(path_hm_d1)/addr_cam.o \ + $(path_hm_d1)/cmac_tx.o \ + $(path_hm_d1)/coex.o \ + $(path_hm_d1)/cpuio.o \ + $(path_hm_d1)/dbcc.o \ + $(path_hm_d1)/dbgpkg.o \ + $(path_hm_d1)/dbgport_hw.o \ + $(path_hm_d1)/dbg_cmd.o \ + $(path_hm_d1)/dle.o \ + $(path_hm_d1)/efuse.o \ + $(path_hm_d1)/fwcmd.o \ + $(path_hm_d1)/fwdl.o \ + $(path_hm_d1)/fwofld.o \ + $(path_hm_d1)/gpio.o \ + $(path_hm_d1)/hci_fc.o \ + $(path_hm_d1)/hdr_conv.o \ + $(path_hm_d1)/hw_seq.o \ + $(path_hm_d1)/h2c_agg.o \ + $(path_hm_d1)/hw.o \ + $(path_hm_d1)/hwamsdu.o \ + $(path_hm_d1)/init.o \ + $(path_hm_d1)/la_mode.o \ + $(path_hm_d1)/mcc.o \ + $(path_hm_d1)/mport.o \ + $(path_hm_d1)/phy_rpt.o \ + $(path_hm_d1)/power_saving.o \ + $(path_hm_d1)/pwr.o \ + $(path_hm_d1)/p2p.o \ + $(path_hm_d1)/role.o \ + $(path_hm_d1)/rx_filter.o \ + $(path_hm_d1)/rx_forwarding.o \ + $(path_hm_d1)/rrsr.o \ + $(path_hm_d1)/ser.o \ + $(path_hm_d1)/security_cam.o \ + $(path_hm_d1)/sounding.o \ + $(path_hm_d1)/status.o \ + $(path_hm_d1)/sta_sch.o \ + $(path_hm_d1)/tblupd.o \ + $(path_hm_d1)/tcpip_checksum_offload.o \ + $(path_hm_d1)/trx_desc.o \ + $(path_hm_d1)/trxcfg.o \ + $(path_hm_d1)/twt.o \ + $(path_hm_d1)/wowlan.o \ + $(path_hm_d1)/flash.o \ + $(path_hm_d1)/spatial_reuse.o \ + $(path_hm_d1)/pwr_seq_func.o \ + $(path_hm_d1)/phy_misc.o \ + +halmac-$(pci) += $(path_hm_d1)/_pcie.o +halmac-$(usb) += $(path_hm_d1)/_usb.o +halmac-$(sdio) += $(path_hm_d1)/_sdio.o + + +ifeq ($(CONFIG_RTL8852A), y) +ic := 8852a +endif +ifeq ($(CONFIG_RTL8852B), y) +ic := 8852b +endif +ifeq ($(CONFIG_RTL8852C), y) +ic := 8852c +endif + + +# Level 2 directory +path_hm2 := $(path_hm_d1)/mac_$(ic) + +halmac-y += $(path_hm2)/gpio_$(ic).o \ + $(path_hm2)/init_$(ic).o \ + $(path_hm2)/pwr_seq_$(ic).o +halmac-$(usb) += $(path_hm2)/_usb_$(ic).o + + +ifeq ($(CONFIG_RTL8852B), y) +halmac-y += $(path_hm2)/pwr_seq_func_$(ic).o +endif + +ifeq ($(CONFIG_RTL8852C), y) +halmac-y += $(path_hm2)/pwr_seq_func_$(ic).o \ + $(path_hm2)/trx_desc_$(ic).o +endif + +# fw files +path_fw := $(path_fw_d1)/rtl$(ic) + +halmac-y += $(path_fw)/hal$(ic)_fw.o \ + $(path_fw)/hal$(ic)_fw_log.o +ifeq ($(CONFIG_RTL8852B), y) +halmac-y += $(path_fw)/hal$(ic)_fw_u1.o +endif + +_HAL_MAC_FILES += $(halmac-y) diff --git a/phl/hal_g6/mac/mac_ax.c b/phl/hal_g6/mac/mac_ax.c new file mode 100644 index 0000000..039ce4e --- /dev/null +++ b/phl/hal_g6/mac/mac_ax.c @@ -0,0 +1,544 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "mac_ax.h" + +#define CHIP_ID_HW_DEF_8852A 0x50 +#define CHIP_ID_HW_DEF_8852B 0x51 +#define CHIP_ID_HW_DEF_8852C 0x52 +#define CHIP_ID_HW_DEF_8192XB 0x53 + +#define SDIO_WAIT_CNT 50 +#if MAC_AX_SDIO_SUPPORT +static u8 r8_indir_cmd52_sdio(void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb, u32 adr); +#endif + +#ifndef CONFIG_NEW_HALMAC_INTERFACE +static u8 chk_pltfm_cb(void *drv_adapter, enum mac_ax_intf intf, + struct mac_ax_pltfm_cb *pltfm_cb) +{ + if (!pltfm_cb) + return MACSUCCESS; + + if (!pltfm_cb->msg_print) + return MACSUCCESS; + +#if MAC_AX_SDIO_SUPPORT + if (!pltfm_cb->sdio_cmd52_r8 || !pltfm_cb->sdio_cmd53_r8 || + !pltfm_cb->sdio_cmd53_r16 || !pltfm_cb->sdio_cmd53_r32 || + !pltfm_cb->sdio_cmd53_rn || !pltfm_cb->sdio_cmd52_w8 || + !pltfm_cb->sdio_cmd53_w8 || !pltfm_cb->sdio_cmd53_w16 || + !pltfm_cb->sdio_cmd53_w32 || !pltfm_cb->sdio_cmd53_wn || + !pltfm_cb->sdio_cmd52_cia_r8) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-SDIO\n"); + return MACSUCCESS; + } +#endif + +#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT) + if (!pltfm_cb->reg_r8 || !pltfm_cb->reg_r16 || + !pltfm_cb->reg_r32 || !pltfm_cb->reg_w8 || + !pltfm_cb->reg_w16 || !pltfm_cb->reg_w32) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-USB or PCIE\n"); + return MACSUCCESS; + } +#endif + if (!pltfm_cb->rtl_free || !pltfm_cb->rtl_malloc || + !pltfm_cb->rtl_memcpy || !pltfm_cb->rtl_memset || + !pltfm_cb->rtl_delay_us || !pltfm_cb->rtl_delay_ms || + !pltfm_cb->rtl_mutex_init || !pltfm_cb->rtl_mutex_deinit || + !pltfm_cb->rtl_mutex_lock || !pltfm_cb->rtl_mutex_unlock || + !pltfm_cb->event_notify) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-OS\n"); + return MACSUCCESS; + } + + return MACPFCB; +} +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +static u8 chk_pltfm_endian(void) +{ + u32 num = 1; + u8 *num_ptr = (u8 *)# + + if (*num_ptr != PLATFOM_IS_LITTLE_ENDIAN) + return MACSUCCESS; + + return MACPFCB; +} + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +#if MAC_AX_SDIO_SUPPORT +static u8 r8_indir_cmd52_sdio(void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb, u32 adr) +{ + u8 tmp; + u32 cnt; + + PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR, (u8)adr); + PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 1, (u8)(adr >> 8)); + PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 2, (u8)(adr >> 16)); + PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 3, + (u8)((adr | B_AX_INDIRECT_RDY) >> 24)); + PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_CTRL, (u8)B_AX_INDIRECT_REG_R); + + cnt = SDIO_WAIT_CNT; + do { + tmp = PLTFM_SDIO_CMD52_R8(R_AX_SDIO_INDIRECT_ADDR + 3); + cnt--; + } while (((tmp & BIT(7)) == 0) && (cnt > 0)); + + if (((tmp & BIT(7)) == 0) && cnt == 0) + PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n"); + + return PLTFM_SDIO_CMD52_R8(R_AX_SDIO_INDIRECT_DATA); +} +#endif +static u32 get_chip_info(struct mac_ax_adapter *adapter, + struct mac_ax_pltfm_cb *pltfm_cb, + enum mac_ax_intf intf, u8 *id, u8 *cv) +{ + u32 cv_temp; + u8 cur_id; + + if (!cv || !id) + return MACNPTR; + + switch (intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + cur_id = r8_indir_cmd52_sdio(adapter, R_AX_SYS_CHIPINFO); + *cv = r8_indir_cmd52_sdio(adapter, R_AX_SYS_CFG1 + 1) >> 4; + break; +#endif +#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT) + case MAC_AX_INTF_USB: + case MAC_AX_INTF_PCIE: + cur_id = PLTFM_REG_R8(R_AX_SYS_CHIPINFO); + *cv = PLTFM_REG_R8(R_AX_SYS_CFG1 + 1) >> 4; + + if (cur_id == CHIP_ID_HW_DEF_8852A) { + if (*cv <= CBV) { + cv_temp = PLTFM_REG_R32(R_AX_GPIO0_7_FUNC_SEL); + if (cv_temp == 0xdeadbeef) + *cv = CAV; + else + *cv = CBV; + } + } + break; +#endif + default: + return MACINTF; + } + + switch (cur_id) { + case CHIP_ID_HW_DEF_8852A: + *id = MAC_AX_CHIP_ID_8852A; + break; + case CHIP_ID_HW_DEF_8852B: + *id = MAC_AX_CHIP_ID_8852B; + break; + case CHIP_ID_HW_DEF_8852C: + *id = MAC_AX_CHIP_ID_8852C; + break; + default: + return MACCHIPID; + } + + return MACSUCCESS; +} + +u32 mac_ax_ops_init_v1(void *phl_adapter, void *drv_adapter, + enum rtw_chip_id chip_id, + enum rtw_hci_type hci, + struct mac_ax_adapter **mac_adapter, + struct mac_ax_ops **mac_ops) +{ + u32 ret; + u8 cv; + struct mac_ax_adapter *adapter; + enum mac_ax_intf intf = MAC_AX_INTF_INVALID; + + if (!chk_pltfm_endian()) + return MACPFED; + + ret = 0; + + if (hci == RTW_HCI_PCIE) + intf = MAC_AX_INTF_PCIE; + else if (hci == RTW_HCI_USB) + intf = MAC_AX_INTF_USB; + else if (hci == RTW_HCI_SDIO) + intf = MAC_AX_INTF_SDIO; + + ret = get_chip_info(drv_adapter, NULL, intf, &chip_id, &cv); + if (ret) + return ret; + + adapter = get_mac_ax_adapter(intf, chip_id, cv, phl_adapter, + drv_adapter, NULL); + if (!adapter) { + PLTFM_MSG_PRINT("[ERR]Get MAC adapter\n"); + return MACADAPTER; + } + PLTFM_MSG_ALWAYS("MAC_AX_MAJOR_VER = %d\n" + "MAC_AX_PROTOTYPE_VER = %d\n" + "MAC_AX_SUB_VER = %d\n" + "MAC_AX_SUB_INDEX = %d\n", + MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER, + MAC_AX_SUB_VER, MAC_AX_SUB_INDEX); + + *mac_adapter = adapter; + *mac_ops = adapter->ops; + + return MACSUCCESS; +} + +#else + +#if MAC_AX_SDIO_SUPPORT +static u8 r8_indir_cmd52_sdio(void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb, u32 adr) +{ + u8 tmp; + u32 cnt; + + pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR, + (u8)adr); + pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 1, + (u8)(adr >> 8)); + pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 2, + (u8)(adr >> 16)); + pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 3, + (u8)((adr | B_AX_INDIRECT_RDY) >> 24)); + pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_CTRL, + (u8)B_AX_INDIRECT_REG_R); + + cnt = SDIO_WAIT_CNT; + do { + tmp = pltfm_cb->sdio_cmd52_r8(drv_adapter, + R_AX_SDIO_INDIRECT_ADDR + 3); + cnt--; + } while (((tmp & BIT(7)) == 0) && (cnt > 0)); + + if (((tmp & BIT(7)) == 0) && cnt == 0) + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, + "[ERR]sdio indirect CMD52 read\n"); + + return pltfm_cb->sdio_cmd52_r8(drv_adapter, R_AX_SDIO_INDIRECT_DATA); +} +#endif +static u32 get_chip_info(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb, + enum mac_ax_intf intf, u8 *id, u8 *cv) +{ + u8 cur_id; + + if (!cv || !id) + return MACNPTR; + + switch (intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + cur_id = r8_indir_cmd52_sdio(drv_adapter, pltfm_cb, + R_AX_SYS_CHIPINFO); + *cv = r8_indir_cmd52_sdio(drv_adapter, pltfm_cb, + R_AX_SYS_CFG1 + 1) >> 4; + if (cur_id == CHIP_ID_HW_DEF_8852A) + if (*cv <= CBV) + *cv = CBV; + + break; +#endif +#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT) + case MAC_AX_INTF_USB: + case MAC_AX_INTF_PCIE: + cur_id = pltfm_cb->reg_r8(drv_adapter, R_AX_SYS_CHIPINFO); + *cv = pltfm_cb->reg_r8(drv_adapter, R_AX_SYS_CFG1 + 1) >> 4; + if (cur_id == CHIP_ID_HW_DEF_8852A) + if (*cv <= CBV) + *cv = CBV; + + break; +#endif + default: + return MACINTF; + } + + switch (cur_id) { + case CHIP_ID_HW_DEF_8852A: + *id = MAC_AX_CHIP_ID_8852A; + break; + case CHIP_ID_HW_DEF_8852B: + *id = MAC_AX_CHIP_ID_8852B; + break; + case CHIP_ID_HW_DEF_8852C: + *id = MAC_AX_CHIP_ID_8852C; + break; + case CHIP_ID_HW_DEF_8192XB: + *id = MAC_AX_CHIP_ID_8192XB; + break; + default: + return MACCHIPID; + } + + return MACSUCCESS; +} + +u32 mac_ax_ops_init(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb, + enum mac_ax_intf intf, + struct mac_ax_adapter **mac_adapter, + struct mac_ax_ops **mac_ops) +{ + u32 ret; + u8 chip_id = 0; + u8 cv = 0; + struct mac_ax_adapter *adapter; + + if (!chk_pltfm_cb(drv_adapter, intf, pltfm_cb)) + return MACPFCB; + + if (!chk_pltfm_endian()) + return MACPFED; + + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, + "MAC_AX_MAJOR_VER = %d\n" + "MAC_AX_PROTOTYPE_VER = %d\n" + "MAC_AX_SUB_VER = %d\n" + "MAC_AX_SUB_INDEX = %d\n", + MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER, + MAC_AX_SUB_VER, MAC_AX_SUB_INDEX); + + ret = get_chip_info(drv_adapter, pltfm_cb, intf, &chip_id, &cv); + if (ret) + return ret; + + adapter = get_mac_ax_adapter(intf, chip_id, cv, drv_adapter, + pltfm_cb); + if (!adapter) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]Get MAC adapter\n"); + return MACADAPTER; + } + + *mac_adapter = adapter; + *mac_ops = adapter->ops; + +#if MAC_AX_FEATURE_HV + adapter->hv_ops = get_hv_ax_ops(adapter); +#endif + +#if MAC_AX_PHL_H2C + +#else + ret = h2cb_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]h2cb init %d\n", ret); + return ret; + } +#endif + + ret = role_tbl_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]role tbl init %d\n", ret); + return ret; + } + + ret = sec_info_tbl_init(adapter, SEC_CAM_NORMAL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec info tbl init %d\n", ret); + return ret; + } + + ret = efuse_tbl_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]efuse tbl init %d\n", ret); + return ret; + } + + ret = p2p_info_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p info init %d\n", ret); + return ret; + } + + ret = mport_info_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]mpinfo info init %d\n", ret); + return ret; + } + + ret = mix_info_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]mix info init %d\n", ret); + return ret; + } + +#if MAC_AX_SDIO_SUPPORT + ret = sdio_tbl_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sdio tbl init %d\n", ret); + return ret; + } +#endif + + ret = hfc_info_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]hfc info init %d\n", ret); + return ret; + } + + return MACSUCCESS; +} +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +#if MAC_AX_PHL_H2C +u32 mac_ax_phl_init(void *phl_adapter, struct mac_ax_adapter *mac_adapter) +{ + struct mac_ax_adapter *adapter = mac_adapter; + + adapter->phl_adapter = phl_adapter; + + return MACSUCCESS; +} +#endif +u32 mac_ax_ops_exit(struct mac_ax_adapter *adapter) +{ + u32 ret; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + struct scan_chinfo_list *scan_list; + + ret = h2cb_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]h2c buffer exit %d\n", ret); + return ret; + } + + ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec table exit %d\n", ret); + return ret; + } + + ret = role_tbl_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]role table exit %d\n", ret); + return ret; + } + + ret = efuse_tbl_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]efuse table exit %d\n", ret); + return ret; + } + + ret = p2p_info_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p info exit %d\n", ret); + return ret; + } + + ret = mport_info_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]mpinfo info exit %d\n", ret); + return ret; + } + + ret = mix_info_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]mix info exit %d\n", ret); + return ret; + } + +#if MAC_AX_SDIO_SUPPORT + ret = sdio_tbl_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]efuse table exit %d\n", ret); + return ret; + } +#endif + + ret = hfc_info_exit(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]hfc info exit %d\n", ret); + return ret; + } + + ret = free_aoac_report(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]free aoac report %d\n", ret); + return ret; + } + + if (efuse_param->efuse_map) { + PLTFM_FREE(efuse_param->efuse_map, + adapter->hw_info->efuse_size); + efuse_param->efuse_map = (u8 *)NULL; + } + + if (efuse_param->bt_efuse_map) { + PLTFM_FREE(efuse_param->bt_efuse_map, + adapter->hw_info->bt_efuse_size); + efuse_param->bt_efuse_map = (u8 *)NULL; + } + + if (efuse_param->log_efuse_map) { + PLTFM_FREE(efuse_param->log_efuse_map, + adapter->hw_info->log_efuse_size); + efuse_param->log_efuse_map = (u8 *)NULL; + } + + if (efuse_param->bt_log_efuse_map) { + PLTFM_FREE(efuse_param->bt_log_efuse_map, + adapter->hw_info->bt_log_efuse_size); + efuse_param->bt_log_efuse_map = (u8 *)NULL; + } + + if (efuse_param->dav_efuse_map) { + PLTFM_FREE(efuse_param->dav_efuse_map, + adapter->hw_info->dav_efuse_size); + efuse_param->dav_efuse_map = (u8 *)NULL; + } + + if (efuse_param->dav_log_efuse_map) { + PLTFM_FREE(efuse_param->dav_log_efuse_map, + adapter->hw_info->dav_log_efuse_size); + efuse_param->dav_log_efuse_map = (u8 *)NULL; + } + + scan_list = adapter->scanofld_info.list; + if (scan_list) { + mac_scanofld_ch_list_clear(adapter, scan_list); + PLTFM_FREE((u8 *)scan_list, sizeof(struct scan_chinfo_list)); + adapter->scanofld_info.list = NULL; + } + + PLTFM_FREE(adapter->hw_info, sizeof(struct mac_ax_hw_info)); + + PLTFM_FREE(adapter, sizeof(struct mac_ax_adapter)); + return MACSUCCESS; +} + +u32 is_chip_id(struct mac_ax_adapter *adapter, enum mac_ax_chip_id id) +{ + return (id == adapter->hw_info->chip_id ? 1 : 0); +} + +u32 is_cv(struct mac_ax_adapter *adapter, enum rtw_cv cv) +{ + return (cv == adapter->hw_info->cv ? 1 : 0); +} + diff --git a/phl/hal_g6/mac/mac_ax.h b/phl/hal_g6/mac/mac_ax.h new file mode 100644 index 0000000..5c9b55d --- /dev/null +++ b/phl/hal_g6/mac/mac_ax.h @@ -0,0 +1,128 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_H_ +#define _MAC_AX_H_ + +#include "mac_def.h" +#include "mac_ax/fwcmd.h" +#include "mac_ax/security_cam.h" +#include "mac_ax/efuse.h" +#include "mac_ax/p2p.h" +#if MAC_AX_SDIO_SUPPORT +#include "mac_ax/_sdio.h" +#endif +#if MAC_AX_FEATURE_HV +#include "hv_ax/init_hv.h" +#include "hv_ax/fwcmd_hv.h" +#endif + +#if MAC_AX_FEATURE_HV +#include "hv_type.h" +#endif + +#define MAC_AX_MAJOR_VER 0 /*Software Architcture Modify*/ +#define MAC_AX_PROTOTYPE_VER 25 /*New Feature;Regular Release*/ +#define MAC_AX_SUB_VER 40 /*for bug fix*/ +#define MAC_AX_SUB_INDEX 0 /*for special used*/ + +#define MAC_AX_SRC_VER(a, b, c, d) \ + (((a) << 24) + ((b) << 16) + ((c) << 8) + (d)) + +#ifdef CONFIG_NEW_HALMAC_INTERFACE + +/** + * @brief mac_ax_ops_init_v1 + * + * @param *phl_adapter + * @param *drv_adapter + * @param chip_id + * @param hci + * @param **mac_adapter + * @param **mac_ops + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ax_ops_init_v1(void *phl_adapter, void *drv_adapter, + enum rtw_chip_id chip_id, + enum rtw_hci_type hci, + struct mac_ax_adapter **mac_adapter, + struct mac_ax_ops **mac_ops); + +/** + * @brief mac_ax_ops_init + * + * @param *drv_adapter + * @param *pltfm_cb + * @param intf + * @param **mac_adapter + * @param **mac_ops + * @return Please Place Description here. + * @retval u32 + */ +#else +u32 mac_ax_ops_init(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb, + enum mac_ax_intf intf, + struct mac_ax_adapter **mac_adapter, + struct mac_ax_ops **mac_ops); + +/** + * @brief mac_ax_phl_init + * + * @param *phl_adapter + * @param *mac_adapter + * @return Please Place Description here. + * @retval u32 + */ + +#endif +#if MAC_AX_PHL_H2C +u32 mac_ax_phl_init(void *phl_adapter, struct mac_ax_adapter *mac_adapter); + +/** + * @brief mac_ax_ops_exit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +#endif + +u32 mac_ax_ops_exit(struct mac_ax_adapter *adapter); + +/** + * @brief is_chip_id + * + * @param *adapter + * @param id + * @return Please Place Description here. + * @retval u32 + */ + +u32 is_chip_id(struct mac_ax_adapter *adapter, enum mac_ax_chip_id id); + +/** + * @brief is_cv + * + * @param *adapter + * @param rtw_cv cv + * @return Please Place Description here. + * @retval u32 + */ + +u32 is_cv(struct mac_ax_adapter *adapter, enum rtw_cv cv); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/_usb.c b/phl/hal_g6/mac/mac_ax/_usb.c new file mode 100644 index 0000000..b405eb8 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/_usb.c @@ -0,0 +1,79 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "_usb.h" +#include "../mac_ax.h" + +#if MAC_AX_USB_SUPPORT + +u32 usb_flush_mode(struct mac_ax_adapter *adapter, u8 mode) +{ + u32 reg, val32; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + reg = R_AX_USB_WLAN0_1; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + reg = R_AX_USB_WLAN0_1; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + reg = R_AX_USB_WLAN0_1_V1; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + reg = R_AX_USB_WLAN0_1_V1; + else + return MACCHIPID; + + if (mode == MAC_AX_FUNC_DIS) { + val32 = PLTFM_REG_R32(reg) & ~(B_AX_USBRX_RST | B_AX_USBTX_RST); + PLTFM_REG_W32(reg, val32); + return MACSUCCESS; + } else if (mode == MAC_AX_FUNC_EN) { + val32 = PLTFM_REG_R32(reg) | B_AX_USBRX_RST | B_AX_USBTX_RST; + PLTFM_REG_W32(reg, val32); + return MACSUCCESS; + } else { + return MACLV1STEPERR; + } +} + +u32 get_usb_mode(struct mac_ax_adapter *adapter) +{ + u32 reg, val32, hs; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + reg = R_AX_USB_STATUS; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + reg = R_AX_USB_STATUS; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + reg = R_AX_USB_STATUS_V1; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + reg = R_AX_USB_STATUS_V1; + else + return MACCHIPID; + + val32 = PLTFM_REG_R32(reg) & B_AX_R_USB2_SEL; + hs = PLTFM_REG_R32(reg) & B_AX_MODE_HS; + if (val32 == B_AX_R_USB2_SEL) + val32 = MAC_AX_USB3; + else if ((val32 != B_AX_R_USB2_SEL) && (hs == B_AX_MODE_HS)) + val32 = MAC_AX_USB2; + else + val32 = MAC_AX_USB11; + return val32; +} + +u32 usb_autok_counter_avg(struct mac_ax_adapter *adapter) +{ + return MACSUCCESS; +} + +#endif /* #if MAC_AX_USB_SUPPORT */ diff --git a/phl/hal_g6/mac/mac_ax/_usb.h b/phl/hal_g6/mac/mac_ax/_usb.h new file mode 100644 index 0000000..3108baf --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/_usb.h @@ -0,0 +1,124 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_USB_H_ +#define _MAC_AX_USB_H_ + +#include "../type.h" + +#define phyoffset 0x20 +#define USB11 0x1 +#define USB2 0x2 +#define USB3 0x3 +#define U3SWITCHU2 0x17 +#define U2SWITCHU3 0xB +#define USB_SWITCH_DELAY 0xF +#define SWITCHMODE 0x2 +#define FORCEUSB3MODE 0x1 +#define FORCEUSB2MODE 0x0 +#define USBEPMAPERR 0xFF +#define USB11_BULKSIZE 0x2 +#define USB2_BULKSIZE 0x1 +#define USB3_BULKSIZE 0x0 +#define EP4 0x4 +#define EP5 0x5 +#define EP6 0x6 +#define EP7 0x7 +#define EP8 0x8 +#define EP9 0x9 +#define EP10 0xA +#define EP11 0xB +#define EP12 0xC +#define NUMP 0x1 +#define BULKOUTID0 0x0 +#define BULKOUTID1 0x1 +#define BULKOUTID2 0x2 +#define BULKOUTID3 0x3 +#define BULKOUTID4 0x4 +#define BULKOUTID5 0x5 +#define BULKOUTID6 0x6 +#define USBPHYOFFSET 0x100 +#define DISABLE 0x0 +#define ENABLE 0x1 +#define RXAGGSIZE 0x5 +#define RXAGGTO 0x20 +#define EFUSESIZE 0x1 +#define CMAC_CLK_ALLEN 0xFFFFFFFF +#define SINGLE_MSDU_SIZE 0x600 +#define SEC_FCS_SIZE 0x80 +#define PLE_PAGE_SIZE 0x80 +#define PINGPONG 0x2 +#define RX_POLLING_PERIOD 0x40 +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ +/** + * @brief usb_flush_mode + * + * @param *adapter + * @param mode + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_flush_mode(struct mac_ax_adapter *adapter, u8 mode); + +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief get_usb_mode_8852a + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 get_usb_mode(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @brief usb_autok_counter_avg + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_autok_counter_avg(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/addr_cam.c b/phl/hal_g6/mac/mac_ax/addr_cam.c new file mode 100644 index 0000000..d0ed7dc --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/addr_cam.c @@ -0,0 +1,763 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "addr_cam.h" + +#define MAC_AX_NO_HIT_IDX 0xFF + +static u8 get_set_bits_of_msk(u8 msk) +{ + u8 set_bits; + + if (msk == 0) + return 0; + set_bits = msk & (msk - 1); + if (set_bits == 0) + return 1; + return get_set_bits_of_msk(set_bits) + 1; +} + +u32 find_avail_addr_cam_entry(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u16 i; + + for (i = 0; i < adapter->hw_info->macid_num; i++) { + if (!mac_role_srch_by_addr_cam(adapter, i)) + break; + } + if (i == adapter->hw_info->macid_num) + return MACADDRCAMFL; + info->a_info.addr_cam_idx = (u8)i; + + return MACSUCCESS; +} + +u32 find_avail_bssid_cam_entry(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u8 i; + struct mac_role_tbl *role; + u8 maddr_cmp_len = ETH_ALEN; + + info->a_info.bssid_cam_idx = adapter->hw_info->bssid_num; + info->b_info.bssid_cam_idx = adapter->hw_info->bssid_num; + + if (info->a_info.mask_sel == MAC_AX_BSSID_MSK) + maddr_cmp_len = get_set_bits_of_msk(info->a_info.addr_mask); + + for (i = 0; i < adapter->hw_info->bssid_num; i++) { + role = mac_role_srch_by_bssid(adapter, i); + if (role && + !PLTFM_MEMCMP(info->bssid, + role->info.bssid, maddr_cmp_len) && + info->band == role->info.band) { + info->a_info.bssid_cam_idx = + role->info.a_info.bssid_cam_idx; + if (maddr_cmp_len < ETH_ALEN) { + PLTFM_MEMCPY(info->b_info.bssid, + role->info.b_info.bssid, + ETH_ALEN); + } + break; + } else if (!role) { + if (info->a_info.bssid_cam_idx == + adapter->hw_info->bssid_num) { + info->a_info.bssid_cam_idx = i; + } + } + } + + if (info->a_info.bssid_cam_idx == adapter->hw_info->bssid_num) + return MACBSSIDCAMFL; + info->b_info.bssid_cam_idx = info->a_info.bssid_cam_idx; + + return MACSUCCESS; +} + +u32 init_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam) +{ + u32 ret; + + ret = find_avail_addr_cam_entry(adapter, info); + if (ret) + return ret; + + ret = find_avail_bssid_cam_entry(adapter, info); + if (ret) + return ret; + + fill_addr_cam_info(adapter, info, fw_addrcam); + fill_bssid_cam_info(adapter, info, fw_addrcam); + + return MACSUCCESS; +} + +u32 change_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam) +{ + u32 ret; + + ret = find_avail_bssid_cam_entry(adapter, info); + if (ret) + return ret; + + fill_addr_cam_info(adapter, info, fw_addrcam); + fill_bssid_cam_info(adapter, info, fw_addrcam); + + return MACSUCCESS; +} + +u32 fill_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam) +{ + struct mac_ax_addr_cam_info a_info; + u8 i; + u8 sma_hash = 0x00; + u8 tma_hash = 0x00; + u8 maddr_cmp_len; + + maddr_cmp_len = get_set_bits_of_msk(info->a_info.addr_mask); + + switch (info->a_info.mask_sel) { + case MAC_AX_SMA_MSK: + for (i = 0; i < maddr_cmp_len; i++) + sma_hash ^= info->a_info.sma[i]; + for (i = 0; i < ETH_ALEN; i++) + tma_hash ^= info->a_info.tma[i]; + break; + case MAC_AX_TMA_MSK: + for (i = 0; i < ETH_ALEN; i++) + sma_hash ^= info->a_info.sma[i]; + for (i = 0; i < maddr_cmp_len; i++) + tma_hash ^= info->a_info.tma[i]; + break; + case MAC_AX_NO_MSK: + case MAC_AX_BSSID_MSK: + default: + for (i = 0; i < ETH_ALEN; i++) + sma_hash ^= info->a_info.sma[i]; + for (i = 0; i < ETH_ALEN; i++) + tma_hash ^= info->a_info.tma[i]; + break; + } + + a_info = info->a_info; + + fw_addrcam->dword1 = + cpu_to_le32(SET_WORD(a_info.addr_cam_idx, + FWCMD_H2C_ADDRCAM_INFO_IDX) | + SET_WORD(a_info.offset, FWCMD_H2C_ADDRCAM_INFO_OFFSET) | + SET_WORD(a_info.len, FWCMD_H2C_ADDRCAM_INFO_LEN)); + + fw_addrcam->dword2 = + cpu_to_le32(((a_info.valid) ? FWCMD_H2C_ADDRCAM_INFO_VALID : 0) | + SET_WORD(a_info.net_type, FWCMD_H2C_ADDRCAM_INFO_NET_TYPE) | + SET_WORD(a_info.bcn_hit_cond, FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND) | + SET_WORD(a_info.hit_rule, FWCMD_H2C_ADDRCAM_INFO_HIT_RULE) | + ((a_info.bb_sel) ? FWCMD_H2C_ADDRCAM_INFO_BB_SEL : 0) | + SET_WORD(a_info.addr_mask, FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK) | + SET_WORD(a_info.mask_sel, FWCMD_H2C_ADDRCAM_INFO_MASK_SEL) | + SET_WORD(sma_hash, FWCMD_H2C_ADDRCAM_INFO_SMA_HASH) | + SET_WORD(tma_hash, FWCMD_H2C_ADDRCAM_INFO_TMA_HASH)); + + fw_addrcam->dword3 = + cpu_to_le32(SET_WORD(a_info.bssid_cam_idx, + FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX) | + ((a_info.is_mul_ent) ? FWCMD_H2C_ADDRCAM_INFO_IS_MUL_ENT : 0)); + + fw_addrcam->dword4 = + cpu_to_le32(SET_WORD(a_info.sma[0], FWCMD_H2C_ADDRCAM_INFO_SMA0) | + SET_WORD(a_info.sma[1], FWCMD_H2C_ADDRCAM_INFO_SMA1) | + SET_WORD(a_info.sma[2], FWCMD_H2C_ADDRCAM_INFO_SMA2) | + SET_WORD(a_info.sma[3], FWCMD_H2C_ADDRCAM_INFO_SMA3)); + + fw_addrcam->dword5 = + cpu_to_le32(SET_WORD(a_info.sma[4], FWCMD_H2C_ADDRCAM_INFO_SMA4) | + SET_WORD(a_info.sma[5], FWCMD_H2C_ADDRCAM_INFO_SMA5) | + SET_WORD(a_info.tma[0], FWCMD_H2C_ADDRCAM_INFO_TMA0) | + SET_WORD(a_info.tma[1], FWCMD_H2C_ADDRCAM_INFO_TMA1)); + + fw_addrcam->dword6 = + cpu_to_le32(SET_WORD(a_info.tma[2], FWCMD_H2C_ADDRCAM_INFO_TMA2) | + SET_WORD(a_info.tma[3], FWCMD_H2C_ADDRCAM_INFO_TMA3) | + SET_WORD(a_info.tma[4], FWCMD_H2C_ADDRCAM_INFO_TMA4) | + SET_WORD(a_info.tma[5], FWCMD_H2C_ADDRCAM_INFO_TMA5)); + + // dword7 rsvd + + fw_addrcam->dword8 = + cpu_to_le32(SET_WORD(a_info.macid, FWCMD_H2C_ADDRCAM_INFO_MACID) | + SET_WORD(a_info.port_int, FWCMD_H2C_ADDRCAM_INFO_PORT_INT) | + SET_WORD(a_info.tsf_sync, FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC) | + ((a_info.tf_trs) ? FWCMD_H2C_ADDRCAM_INFO_TF_TRS : 0) | + ((a_info.lsig_txop) ? FWCMD_H2C_ADDRCAM_INFO_LSIG_TXOP : 0) | + SET_WORD(a_info.tgt_ind, FWCMD_H2C_ADDRCAM_INFO_TGT_IND) | + SET_WORD(a_info.frm_tgt_ind, FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND)); + + fw_addrcam->dword9 = + cpu_to_le32((a_info.aid12 & 0xfff) | + ((a_info.wol_pattern) ? FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN : 0) | + ((a_info.wol_uc) ? FWCMD_H2C_ADDRCAM_INFO_WOL_UC : 0) | + ((a_info.wol_magic) ? FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC : 0) | + ((a_info.wapi) ? FWCMD_H2C_ADDRCAM_INFO_WAPI : 0) | + SET_WORD(a_info.sec_ent_mode, FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE) | + SET_WORD(a_info.sec_ent_keyid[0], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID) | + SET_WORD(a_info.sec_ent_keyid[1], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID) | + SET_WORD(a_info.sec_ent_keyid[2], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID) | + SET_WORD(a_info.sec_ent_keyid[3], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID) | + SET_WORD(a_info.sec_ent_keyid[4], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID) | + SET_WORD(a_info.sec_ent_keyid[5], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID) | + SET_WORD(a_info.sec_ent_keyid[6], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID)); + + fw_addrcam->dword10 = + cpu_to_le32(SET_WORD(a_info.sec_ent_valid, + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID) | + SET_WORD(a_info.sec_ent[0], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0) | + SET_WORD(a_info.sec_ent[1], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1) | + SET_WORD(a_info.sec_ent[2], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2)); + + fw_addrcam->dword11 = + cpu_to_le32(SET_WORD(a_info.sec_ent[3], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3) | + SET_WORD(a_info.sec_ent[4], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4) | + SET_WORD(a_info.sec_ent[5], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5) | + SET_WORD(a_info.sec_ent[6], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6)); + + return MACSUCCESS; +} + +u32 fill_bssid_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *role_info, + struct fwcmd_addrcam_info *fw_addrcam) +{ + struct mac_ax_bssid_cam_info b_info = role_info->b_info; + + fw_addrcam->dword12 = + cpu_to_le32(SET_WORD(b_info.bssid_cam_idx, + FWCMD_H2C_ADDRCAM_INFO_B_IDX) | + SET_WORD(b_info.offset, FWCMD_H2C_ADDRCAM_INFO_B_OFFSET) | + SET_WORD(b_info.len, FWCMD_H2C_ADDRCAM_INFO_B_LEN)); + + fw_addrcam->dword13 = + cpu_to_le32(((b_info.valid) ? FWCMD_H2C_ADDRCAM_INFO_B_VALID : 0) | + ((b_info.bb_sel) ? FWCMD_H2C_ADDRCAM_INFO_B_BB_SEL : 0) | + SET_WORD(b_info.bss_color, FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR) | + SET_WORD(b_info.bssid[0], FWCMD_H2C_ADDRCAM_INFO_BSSID0) | + SET_WORD(b_info.bssid[1], FWCMD_H2C_ADDRCAM_INFO_BSSID1)); + + fw_addrcam->dword14 = + cpu_to_le32(SET_WORD(b_info.bssid[2], FWCMD_H2C_ADDRCAM_INFO_BSSID2) | + SET_WORD(b_info.bssid[3], FWCMD_H2C_ADDRCAM_INFO_BSSID3) | + SET_WORD(b_info.bssid[4], FWCMD_H2C_ADDRCAM_INFO_BSSID4) | + SET_WORD(b_info.bssid[5], FWCMD_H2C_ADDRCAM_INFO_BSSID5)); + + return MACSUCCESS; +} + +u32 mac_upd_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + enum mac_ax_role_opmode op) +{ + u32 tbl[21]; + u32 ret; + u32 i; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct fwcmd_addrcam_info *fwcmd_tbl; + u8 ctlinfo_aidx_off; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + buf = h2cb_put(h2cb, sizeof(struct fwcmd_addrcam_info)); + if (!buf) { + ret = MACNOBUF; + goto FWOFLD_END; + } + fwcmd_tbl = (struct fwcmd_addrcam_info *)buf; + + if (op == CHG) + ret = change_addr_cam_info(adapter, info, fwcmd_tbl); + else + ret = init_addr_cam_info(adapter, info, fwcmd_tbl); + if (ret) + goto FWOFLD_END; + + // dword 0 + ret = h2c_pkt_set_hdr(adapter, + h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_ADDR_CAM_UPDATE, + FWCMD_H2C_FUNC_ADDRCAM_INFO, + 0, + 1); + if (ret) + goto FWOFLD_END; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto FWOFLD_END; + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + +FWOFLD_END: + h2cb_free(adapter, h2cb); + if (!ret) + h2c_end_flow(adapter); + + return ret; + } + if (op == CHG) + ret = change_addr_cam_info(adapter, + info, + (struct fwcmd_addrcam_info *) + tbl); + else + ret = init_addr_cam_info(adapter, info, + (struct fwcmd_addrcam_info *) + tbl); + if (ret) + return ret; + // Indirect write addr cam + for (i = 0; i < (u32)((info->a_info.len)) / 4; i++) + mac_sram_dbg_write(adapter, (info->a_info.addr_cam_idx * + info->a_info.len) + (i * 4), + le32_to_cpu(tbl[i + 2]), ADDR_CAM_SEL); + + // Indirect write BSSID cam + for (i = 0; i < (u32)((info->b_info.len)) / 4; i++) + mac_sram_dbg_write(adapter, (info->b_info.bssid_cam_idx * + info->b_info.len) + (i * 4), + le32_to_cpu(tbl[i + 13]), BSSID_CAM_SEL); + + // Indirect write cmac table addr cam idx + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + ctlinfo_aidx_off = 0x18; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + ctlinfo_aidx_off = 0x18; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + ctlinfo_aidx_off = 0x17; + else + ctlinfo_aidx_off = 0xFF; + PLTFM_MSG_WARN("%s ind access cmac tbl start\n", __func__); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W8(R_AX_INDIR_ACCESS_ENTRY + + info->macid * CCTL_INFO_SIZE + ctlinfo_aidx_off, + info->a_info.addr_cam_idx); + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access cmac tbl end\n", __func__); + + return MACSUCCESS; +} + +static void addr_cam_opt_2_uint(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *opt, + u32 *val32) +{ + *val32 = ((opt->addrcam_en) ? B_AX_ADDR_CAM_EN : 0) | + ((opt->srch_per_mpdu) ? B_AX_ADDR_CAM_SRCH_PERPKT : 0) | + ((opt->a2_bit0_cmp_en) ? B_AX_ADDR_CAM_A2_B0_CHK : 0) | + //opt->clr_all_content) ? B_AX_ADDR_CAM_CLR: 0) | + SET_WORD(opt->srch_time_lmt, B_AX_ADDR_CAM_CMPLIMT) | + SET_WORD(opt->srch_range_lmt, B_AX_ADDR_CAM_RANGE); +} + +static void addr_cam_dis_opt_2_uint(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *opt, + u32 *val32) +{ + *val32 = SET_WORD(opt->def_hit_idx, B_AX_ADDR_CAM_DIS_IDX) | + ((opt->def_hit_result) ? B_AX_ADDR_CAM_DIS_CAM_HIT : 0) | + ((opt->def_a1_hit_result) ? B_AX_ADDR_CAM_DIS_A1_HIT : 0) | + ((opt->def_a2_hit_result) ? B_AX_ADDR_CAM_DIS_A2_HIT : 0) | + ((opt->def_a3_hit_result) ? B_AX_ADDR_CAM_DIS_A3_HIT : 0) | + SET_WORD(opt->def_port, B_AX_ADDR_CAM_DIS_PORT) | + SET_WORD(opt->def_sec_idx, B_AX_ADDR_CAM_DIS_SEC_IDX) | + SET_WORD(opt->def_macid, B_AX_ADDR_CAM_DIS_MACID); +} + +u32 mac_get_cfg_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *opt, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + if (!opt) { + PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__); + return MACNPTR; + } + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL); + opt->addrcam_en = ((val32 & B_AX_ADDR_CAM_EN) != 0); + opt->srch_per_mpdu = ((val32 & B_AX_ADDR_CAM_SRCH_PERPKT) != 0); + opt->a2_bit0_cmp_en = ((val32 & B_AX_ADDR_CAM_A2_B0_CHK) != 0); + opt->srch_time_lmt = GET_FIELD(val32, B_AX_ADDR_CAM_CMPLIMT); + opt->srch_range_lmt = GET_FIELD(val32, B_AX_ADDR_CAM_RANGE); + + return MACSUCCESS; +} + +u32 mac_get_cfg_addr_cam_dis(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *opt, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + if (!opt) { + PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__); + return MACNPTR; + } + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_ADDR_CAM_DIS_INFO_C1 : + R_AX_ADDR_CAM_DIS_INFO); + + opt->def_hit_idx = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_IDX); + opt->def_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_CAM_HIT) != 0); + opt->def_a1_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A1_HIT) != 0); + opt->def_a2_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A2_HIT) != 0); + opt->def_a3_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A3_HIT) != 0); + opt->def_port = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_PORT); + opt->def_sec_idx = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_SEC_IDX); + opt->def_macid = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_MACID); + + return MACSUCCESS; +} + +u32 mac_cfg_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *ctl_opt, + struct mac_ax_addrcam_ctrl_t *ctl_msk, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_addrcam_ctrl_t opt = {0}; + u32 ctl_opt_val; + u32 ctl_msk_val; + u32 opt_val; + u32 reg; + u32 cnt; + u32 ret = MACSUCCESS; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return ret; + } + + reg = (band == MAC_AX_BAND_1) ? + R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL; + + mac_get_cfg_addr_cam(adapter, &opt, band); + + addr_cam_opt_2_uint(adapter, ctl_opt, &ctl_opt_val); + addr_cam_opt_2_uint(adapter, ctl_msk, &ctl_msk_val); + addr_cam_opt_2_uint(adapter, &opt, &opt_val); + + opt_val = (ctl_opt_val & ctl_msk_val) | + (~(~ctl_opt_val & ctl_msk_val) & opt_val); + + MAC_REG_W32(reg, opt_val); + + if (ctl_opt->clr_all_content & ctl_msk->clr_all_content) { + opt_val |= B_AX_ADDR_CAM_CLR; + MAC_REG_W32(reg, opt_val); + cnt = TRXCFG_WAIT_CNT; + while (cnt--) { + if (!(MAC_REG_R16(reg) & B_AX_ADDR_CAM_CLR)) + break; + PLTFM_DELAY_US(TRXCFG_WAIT_US); + } + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]ADDR_CAM reset\n"); + return MACPOLLTO; + } + } + + return MACSUCCESS; +} + +u32 mac_cfg_addr_cam_dis(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *ctl_opt, + struct mac_ax_addrcam_dis_ctrl_t *ctl_msk, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_addrcam_dis_ctrl_t opt = {0}; + u32 ctl_opt_val; + u32 ctl_msk_val; + u32 opt_val; + u32 reg; + u32 ret = MACSUCCESS; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return ret; + } + + reg = (band == MAC_AX_BAND_1) ? + R_AX_ADDR_CAM_DIS_INFO_C1 : R_AX_ADDR_CAM_DIS_INFO; + + mac_get_cfg_addr_cam_dis(adapter, &opt, band); + + addr_cam_dis_opt_2_uint(adapter, ctl_opt, &ctl_opt_val); + addr_cam_dis_opt_2_uint(adapter, ctl_msk, &ctl_msk_val); + addr_cam_dis_opt_2_uint(adapter, &opt, &opt_val); + + opt_val = (ctl_opt_val & ctl_msk_val) | + (~(~ctl_opt_val & ctl_msk_val) & opt_val); + + MAC_REG_W32(reg, opt_val); + + return MACSUCCESS; +} + +u32 addr_cam_init(struct mac_ax_adapter *adapter, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + u32 cnt = TRXCFG_WAIT_CNT; + u32 ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? + R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL; + val32 = MAC_REG_R32(reg); + val32 |= (SET_WORD(ADDR_CAM_SERCH_RANGE, B_AX_ADDR_CAM_RANGE) | + B_AX_ADDR_CAM_EN); + if (band == MAC_AX_BAND_0) + val32 |= B_AX_ADDR_CAM_CLR; + MAC_REG_W32(reg, val32); + + cnt = TRXCFG_WAIT_CNT; + while (cnt--) { + if (!(MAC_REG_R16(band == MAC_AX_BAND_1 ? + R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL) + & B_AX_ADDR_CAM_CLR)) + break; + PLTFM_DELAY_US(TRXCFG_WAIT_US); + } + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]ADDR_CAM reset\n"); + return MACPOLLTO; + } + return MACSUCCESS; +} + +static u32 _set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 ack, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u32 val32; + u32 offset_ctrl = band ? R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL; + u32 offset_hit = band ? R_AX_ADDR_CAM_DIS_INFO_C1 : + R_AX_ADDR_CAM_DIS_INFO; + + if (ack) { + val8 = MAC_REG_R8(offset_ctrl); + MAC_REG_W8(offset_ctrl, val8 | B_AX_ADDR_CAM_EN); + } else { + val8 = MAC_REG_R8(offset_ctrl); + MAC_REG_W8(offset_ctrl, val8 & ~B_AX_ADDR_CAM_EN); + val32 = MAC_REG_R32(offset_hit); + val32 = SET_CLR_WORD(val32, MAC_AX_NO_HIT_IDX, + B_AX_ADDR_CAM_DIS_IDX); + val32 &= ~(B_AX_ADDR_CAM_DIS_CAM_HIT | + B_AX_ADDR_CAM_DIS_A1_HIT); + MAC_REG_W32(offset_hit, val32); + } + + return MACSUCCESS; +} + +#if MAC_AX_FW_REG_OFLD +u32 set_mac_do_resp_ack_ofld(struct mac_ax_adapter *adapter) +{ + u32 ret; + u8 cmac1_en; + + cmac1_en = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS ? + 1 : 0; + + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL, B_AX_ADDR_CAM_EN, + 1, cmac1_en ? 0 : 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + if (cmac1_en) { + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL_C1, + B_AX_ADDR_CAM_EN, + 1, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + } + + return MACSUCCESS; +} + +u32 set_mac_not_resp_ack_ofld(struct mac_ax_adapter *adapter) +{ + u32 ret, msk; + u8 cmac1_en; + + cmac1_en = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS ? + 1 : 0; + + /* set 0xCE34[0] = 0 */ + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL, B_AX_ADDR_CAM_EN, + 0, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + + /* set 0xCE38[9:0] = 0xFF */ + msk = (B_AX_ADDR_CAM_DIS_IDX_MSK << B_AX_ADDR_CAM_DIS_IDX_SH) | + B_AX_ADDR_CAM_DIS_A1_HIT | + B_AX_ADDR_CAM_DIS_CAM_HIT; + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_DIS_INFO, msk, + MAC_AX_NO_HIT_IDX, cmac1_en ? 0 : 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + + if (cmac1_en) { + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL_C1, B_AX_ADDR_CAM_EN, + 0, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + + ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_DIS_INFO_C1, msk, + MAC_AX_NO_HIT_IDX, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + } + + return MACSUCCESS; +} + +u32 set_mac_resp_ack_ofld(struct mac_ax_adapter *adapter, u32 ack) +{ + u32 ret; + + if (ack) + ret = set_mac_do_resp_ack_ofld(adapter); + else + ret = set_mac_not_resp_ack_ofld(adapter); + + return ret; +} +#endif + +u32 set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack) +{ + u32 ret; +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) + return ret = set_mac_resp_ack_ofld(adapter, *ack); +#endif + + ret = _set_mac_resp_ack(adapter, *ack, 0); + if (ret == MACSUCCESS && + check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS) + ret = _set_mac_resp_ack(adapter, *ack, 1); + + return ret; +} + +u32 get_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack) +{ +#define MAC_AX_ACK_CMAC1_SH 1 +#define MAC_AX_ACK_CMAC0_SH 0 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 cmac0 = 0, cmac1 = 0; + + cmac0 = !!(MAC_REG_R8(R_AX_ADDR_CAM_CTRL) & B_AX_ADDR_CAM_EN); + if (check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS) + cmac1 = !!(MAC_REG_R8(R_AX_ADDR_CAM_CTRL_C1) & + B_AX_ADDR_CAM_EN); + + *ack = cmac0 << MAC_AX_ACK_CMAC0_SH | cmac1 << MAC_AX_ACK_CMAC1_SH; + + return MACSUCCESS; +} + +u8 get_addr_cam_size(struct mac_ax_adapter *adapter) +{ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + return ADDR_CAM_ENT_LONG_SIZE; + else + return ADDR_CAM_ENT_SHORT_SIZE; +} + diff --git a/phl/hal_g6/mac/mac_ax/addr_cam.h b/phl/hal_g6/mac/mac_ax/addr_cam.h new file mode 100644 index 0000000..5593e12 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/addr_cam.h @@ -0,0 +1,330 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_ADDR_CAM_H_ +#define _MAC_AX_ADDR_CAM_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "../fw_ax/inc_hdr/fwcmd_intf.h" + +#define ADDR_CAM_ENT_LONG_SIZE 0x40 +#define ADDR_CAM_ENT_SHORT_SIZE 0x20 + +#define BSSID_CAM_ENT_SIZE 0x08 +#define ETH_ALEN 6 +#define DEFAULT_HIT_MACID 0x0 + +#define ADDR_CAM_SERCH_RANGE 0x7f +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief addr_cam_init + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 addr_cam_init(struct mac_ax_adapter *adapter, + enum mac_ax_band band); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief addr_cam_init + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_cfg_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *opt, + enum mac_ax_band band); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief addr_cam_init + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_cfg_addr_cam_dis(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *opt, + enum mac_ax_band band); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief mac_cfg_addrcam + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *ctl_opt, + struct mac_ax_addrcam_ctrl_t *ctl_msk, + enum mac_ax_band band); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief mac_cfg_addrcam_dis + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_addr_cam_dis(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *ctl_opt, + struct mac_ax_addrcam_dis_ctrl_t *ctl_msk, + enum mac_ax_band band); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ +/** + * @brief fill_addr_cam_info + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ +u32 fill_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief fill_bssid_cam_info + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ + +u32 fill_bssid_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief init_addr_cam_info + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ + +u32 init_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief change_addr_cam_info + * + * @param *adapter + * @param *info + * @param *fw_addrcam + * @return Please Place Description here. + * @retval u32 + */ + +u32 change_addr_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct fwcmd_addrcam_info *fw_addrcam); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief mac_upd_addr_cam + * + * @param *adapter + * @param *info + * @param change_role + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_upd_addr_cam(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + enum mac_ax_role_opmode op); +/** + * @} + * @} + */ + +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief set_mac_resp_ack + * + * The function could contrl MAC resp ACK or not. + * + * @param *adapter + * @param ack + * @return 0 for success. Others are fail. + * @retval u32 + */ + +u32 set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack); +/** + * @} + * @} + */ + +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief get_mac_resp_ack + * + * The function could get MAC resp ACK ability + * + * @param *adapter + * @param ack + * @return 0 for success. Others are fail. + * @retval u32 + */ + +u32 get_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack); +/** + * @} + * @} + */ + +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup ADDRCAM + * @{ + */ + +/** + * @brief get_addr_cam_size + * + * Get the entry size of address CAM + * + * @param *adapter + * @return ret the size of address CAM. + * @retval u32 + */ + +u8 get_addr_cam_size(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/cmac_tx.c b/phl/hal_g6/mac/mac_ax/cmac_tx.c new file mode 100644 index 0000000..4fed504 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/cmac_tx.c @@ -0,0 +1,1853 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "cmac_tx.h" + +#define PTCL_IDLE_POLL_CNT 2200 +#define SW_CVR_DUR_US 30 +#define SW_CVR_CNT 8 +#define TX_DLY_MAX 9 + +static u32 stop_macid_ctn(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, + struct mac_ax_sch_tx_en_cfg *bak); +static u32 tx_idle_ck(struct mac_ax_adapter *adapter, u8 band); +static u32 tx_idle_sel_ck(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel, + u8 band); +static u32 tx_idle_sel_ck_b(struct mac_ax_adapter *adapter, + enum ptcl_tx_sel sel, u8 band); +static u32 macid_idle_ck(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role); +static u32 band_idle_ck(struct mac_ax_adapter *adapter, u8 band); +static void tx_on_dly(struct mac_ax_adapter *adapter, u8 band); +static void sch_2_u16(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en *tx_en, u16 *val16); +static void u16_2_sch(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en *tx_en, u16 val16); +static u32 h2c_usr_edca(struct mac_ax_adapter *adapter, + struct mac_ax_usr_edca_param *param); +static u32 h2c_usr_tx_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_usr_tx_rpt_cfg *cfg); +static u32 tx_duty_h2c(struct mac_ax_adapter *adapter, + u16 pause_intvl, u16 tx_intvl); + +u32 set_hw_ampdu_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_ampdu_cfg *cfg) +{ + u16 max_agg_num; + u8 max_agg_time; + u8 band; + u32 ret; + u32 bk_addr, agg_addr; + u32 val32; + u8 val8; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + band = cfg->band; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + max_agg_num = cfg->max_agg_num; + max_agg_time = cfg->max_agg_time_32us; + + bk_addr = band ? R_AX_AGG_BK_0_C1 : R_AX_AGG_BK_0; + agg_addr = band ? R_AX_AMPDU_AGG_LIMIT_C1 : R_AX_AMPDU_AGG_LIMIT; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + switch (cfg->wdbk_mode) { + case MAC_AX_WDBK_MODE_SINGLE_BK: + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_WDBK_CFG, 0, 0); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_WDBK_MODE_GRP_BK: + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_WDBK_CFG, 1, 0); + if (ret != MACSUCCESS) + return ret; + break; + default: + return MACNOITEM; + } + + switch (cfg->rty_bk_mode) { + case MAC_AX_RTY_BK_MODE_AGG: + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 0, 0); + if (ret != MACSUCCESS) + return ret; + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD, + 0, 0); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_RTY_BK_MODE_RATE_FB: + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 0, 0); + if (ret != MACSUCCESS) + return ret; + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD, + 1, 0); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_RTY_BK_MODE_BK: + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 1, 0); + if (ret != MACSUCCESS) + return ret; + ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD, + 1, 0); + if (ret != MACSUCCESS) + return ret; + break; + default: + return MACNOITEM; + } + + val32 = 0; + if (max_agg_num > 0 && max_agg_num <= 0x100) { + ret = MAC_REG_W_OFLD((u16)agg_addr, + GET_MSK(B_AX_MAX_AGG_NUM), + max_agg_num - 1, 0); + if (ret != MACSUCCESS) + return ret; + } else { + return MACSETVALERR; + } + if (max_agg_time > 0 && max_agg_time <= 0xA5) { + ret = MAC_REG_W_OFLD((u16)agg_addr, + (u32)GET_MSK(B_AX_AMPDU_MAX_TIME), + max_agg_time, 1); + if (ret != MACSUCCESS) + return ret; + } else { + return MACSETVALERR; + } + + return MACSUCCESS; + } +#endif + + val8 = MAC_REG_R8(bk_addr); + switch (cfg->wdbk_mode) { + case MAC_AX_WDBK_MODE_SINGLE_BK: + val8 &= ~B_AX_WDBK_CFG; + break; + case MAC_AX_WDBK_MODE_GRP_BK: + val8 |= B_AX_WDBK_CFG; + break; + default: + return MACNOITEM; + } + + switch (cfg->rty_bk_mode) { + case MAC_AX_RTY_BK_MODE_AGG: + val8 &= ~(B_AX_EN_RTY_BK | B_AX_EN_RTY_BK_COD); + break; + case MAC_AX_RTY_BK_MODE_RATE_FB: + val8 &= ~(B_AX_EN_RTY_BK); + val8 |= B_AX_EN_RTY_BK_COD; + break; + case MAC_AX_RTY_BK_MODE_BK: + val8 |= B_AX_EN_RTY_BK | B_AX_EN_RTY_BK_COD; + break; + default: + return MACNOITEM; + } + MAC_REG_W8(bk_addr, val8); + + val32 = MAC_REG_R32(agg_addr); + if (max_agg_num > 0 && max_agg_num <= 0x100) + val32 = SET_CLR_WORD(val32, max_agg_num - 1, B_AX_MAX_AGG_NUM); + else + return MACSETVALERR; + if (max_agg_time > 0 && max_agg_time <= 0xA5) + val32 = SET_CLR_WORD(val32, max_agg_time, B_AX_AMPDU_MAX_TIME); + else + return MACSETVALERR; + MAC_REG_W32(agg_addr, val32); + + return MACSUCCESS; +} + +u32 set_hw_usr_tx_rpt_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_usr_tx_rpt_cfg *cfg) +{ + u32 ret; + + ret = h2c_usr_tx_rpt(adapter, cfg); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 set_hw_usr_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_usr_edca_param *param) +{ + u32 ret; + + ret = h2c_usr_edca(adapter, param); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 set_hw_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param) +{ + u32 val32; + u32 reg_edca; + u32 ret; + u16 val16; + enum mac_ax_cmac_path_sel path; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + ret = get_edca_addr(adapter, param, ®_edca); + if (ret != MACSUCCESS) + return ret; + + path = param->path; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 || + path == MAC_AX_CMAC_PATH_SEL_MG2 || + path == MAC_AX_CMAC_PATH_SEL_BCN) { + val16 = SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_BE_0_CW) | + SET_WORD(param->aifs_us, B_AX_BE_0_AIFS); + ret = MAC_REG_W16_OFLD((u16)reg_edca, val16, 1); + if (ret != MACSUCCESS) + return ret; + } else { + val32 = SET_WORD(param->txop_32us, B_AX_BE_0_TXOPLMT) | + SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_BE_0_CW) | + SET_WORD(param->aifs_us, B_AX_BE_0_AIFS); + ret = MAC_REG_W32_OFLD((u16)reg_edca, val32, 1); + if (ret != MACSUCCESS) + return ret; + } + return MACSUCCESS; + } +#endif + + if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 || + path == MAC_AX_CMAC_PATH_SEL_MG2 || + path == MAC_AX_CMAC_PATH_SEL_BCN) { + val16 = SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_BE_0_CW) | + SET_WORD(param->aifs_us, B_AX_BE_0_AIFS); + MAC_REG_W16(reg_edca, val16); + } else { + val32 = SET_WORD(param->txop_32us, B_AX_BE_0_TXOPLMT) | + SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_BE_0_CW) | + SET_WORD(param->aifs_us, B_AX_BE_0_AIFS); + MAC_REG_W32(reg_edca, val32); + } + + return MACSUCCESS; +} + +u32 get_hw_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param) +{ + u32 val32; + u32 reg_edca; + u32 ret; + u16 val16; + enum mac_ax_cmac_path_sel path; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + ret = get_edca_addr(adapter, param, ®_edca); + if (ret != MACSUCCESS) + return ret; + + path = param->path; + + if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 || + path == MAC_AX_CMAC_PATH_SEL_MG2 || + path == MAC_AX_CMAC_PATH_SEL_BCN) { + val16 = MAC_REG_R16(reg_edca); + param->txop_32us = 0; + param->aifs_us = GET_FIELD(val16, B_AX_BE_0_AIFS); + param->ecw_max = (GET_FIELD(val16, B_AX_BE_0_CW) & 0xF0) >> 4; + param->ecw_min = GET_FIELD(val16, B_AX_BE_0_CW) & 0x0F; + } else { + val32 = MAC_REG_R32(reg_edca); + param->txop_32us = GET_FIELD(val32, B_AX_BE_0_TXOPLMT); + param->aifs_us = GET_FIELD(val32, B_AX_BE_0_AIFS); + param->ecw_max = (GET_FIELD(val32, B_AX_BE_0_CW) & 0xF0) >> 4; + param->ecw_min = GET_FIELD(val32, B_AX_BE_0_CW) & 0x0F; + } + + return MACSUCCESS; +} + +u32 set_hw_edcca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edcca_param *param) +{ + u32 reg_cca_ctl = 0; + u32 ret; + enum mac_ax_edcca_sel sel; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL); + if (ret) + return ret; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + sel = param->sel; + if (sel == MAC_AX_EDCCA_IN_TB_CHK) { + if (param->tb_check_en) + reg_cca_ctl |= B_AX_TB_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_TB_CHK_EDCCA; + } + if (sel == MAC_AX_EDCCA_IN_SIFS_CHK) { + if (param->sifs_check_en) + reg_cca_ctl |= B_AX_SIFS_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_SIFS_CHK_EDCCA; + } + if (sel == MAC_AX_EDCCA_IN_CTN_CHK) { + if (param->ctn_check_en) + reg_cca_ctl |= B_AX_CTN_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_CTN_CHK_EDCCA; + } else { + return MACNOITEM; + } + if (param->band) + ret = MAC_REG_W32_OFLD((u16)R_AX_CCA_CONTROL_C1, + reg_cca_ctl, 1); + else + ret = MAC_REG_W32_OFLD((u16)R_AX_CCA_CONTROL, + reg_cca_ctl, 1); + return ret; + } +#endif + + if (param->band) + reg_cca_ctl = MAC_REG_R32(R_AX_CCA_CONTROL_C1); + else + reg_cca_ctl = MAC_REG_R32(R_AX_CCA_CONTROL); + + sel = param->sel; + if (sel == MAC_AX_EDCCA_IN_TB_CHK) { + if (param->tb_check_en) + reg_cca_ctl |= B_AX_TB_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_TB_CHK_EDCCA; + } + if (sel == MAC_AX_EDCCA_IN_SIFS_CHK) { + if (param->sifs_check_en) + reg_cca_ctl |= B_AX_SIFS_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_SIFS_CHK_EDCCA; + } + if (sel == MAC_AX_EDCCA_IN_CTN_CHK) { + if (param->ctn_check_en) + reg_cca_ctl |= B_AX_CTN_CHK_EDCCA; + else + reg_cca_ctl &= ~B_AX_CTN_CHK_EDCCA; + } else { + return MACNOITEM; + } + + if (param->band) + MAC_REG_W32(R_AX_CCA_CONTROL_C1, reg_cca_ctl); + else + MAC_REG_W32(R_AX_CCA_CONTROL, reg_cca_ctl); + + return MACSUCCESS; +} + +u32 set_hw_muedca_param(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_param *param) +{ + u32 val32; + u32 reg_edca; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + ret = get_muedca_param_addr(adapter, param, ®_edca); + if (ret != MACSUCCESS) + return ret; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + val32 = SET_WORD(param->muedca_timer_32us, + B_AX_MUEDCA_BE_PARAM_0_TIMER) | + SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_MUEDCA_BE_PARAM_0_CW) | + SET_WORD(param->aifs_us, B_AX_MUEDCA_BE_PARAM_0_AIFS); + ret = MAC_REG_W32_OFLD((u16)reg_edca, val32, 1); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; + } +#endif + + val32 = SET_WORD(param->muedca_timer_32us, + B_AX_MUEDCA_BE_PARAM_0_TIMER) | + SET_WORD((param->ecw_max << 4) | param->ecw_min, + B_AX_MUEDCA_BE_PARAM_0_CW) | + SET_WORD(param->aifs_us, B_AX_MUEDCA_BE_PARAM_0_AIFS); + MAC_REG_W32(reg_edca, val32); + + return MACSUCCESS; +} + +u32 set_hw_muedca_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_cfg *cfg) +{ + u32 ret; + u8 band; + u16 val16; + u32 reg_en; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + band = cfg->band; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg_en = band ? R_AX_MUEDCA_EN_C1 : R_AX_MUEDCA_EN; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + val16 = 0; + if (cfg->wmm_sel == MAC_AX_CMAC_WMM1_SEL) { + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_WMM_SEL, + 1, 0); + if (ret != MACSUCCESS) + return ret; + } else { + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_WMM_SEL, + 0, 0); + if (ret != MACSUCCESS) + return ret; + } + + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_EN_0, + cfg->countdown_en, 0); + if (ret != MACSUCCESS) + return ret; + + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_SET_MUEDCATIMER_TF_0, + cfg->tb_update_en, 1); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; + } +#endif + + val16 = MAC_REG_R16(reg_en); + + if (cfg->wmm_sel == MAC_AX_CMAC_WMM1_SEL) + val16 |= B_AX_MUEDCA_WMM_SEL; + else + val16 &= ~B_AX_MUEDCA_WMM_SEL; + + if (cfg->countdown_en) + val16 |= B_AX_MUEDCA_EN_0; + else + val16 &= ~B_AX_MUEDCA_EN_0; + + if (cfg->tb_update_en) + val16 |= B_AX_SET_MUEDCATIMER_TF_0; + else + val16 &= ~B_AX_SET_MUEDCATIMER_TF_0; + + MAC_REG_W16(reg_en, val16); + + return MACSUCCESS; +} + +u32 set_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_tb_ppdu_ctrl *ctrl) +{ + u16 val16; + u8 pri_ac; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, ctrl->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + switch (ctrl->pri_ac) { + case MAC_AX_CMAC_AC_SEL_BE: + pri_ac = 0; + break; + case MAC_AX_CMAC_AC_SEL_BK: + pri_ac = 1; + break; + case MAC_AX_CMAC_AC_SEL_VI: + pri_ac = 2; + break; + case MAC_AX_CMAC_AC_SEL_VO: + pri_ac = 3; + break; + default: + return MACNOITEM; + } + + val16 = MAC_REG_R16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 : + R_AX_TB_PPDU_CTRL); + val16 &= ~(B_AX_TB_PPDU_BE_DIS | B_AX_TB_PPDU_BK_DIS | + B_AX_TB_PPDU_VI_DIS | B_AX_TB_PPDU_VO_DIS); + val16 |= (ctrl->be_dis ? B_AX_TB_PPDU_BE_DIS : 0) | + (ctrl->bk_dis ? B_AX_TB_PPDU_BK_DIS : 0) | + (ctrl->vi_dis ? B_AX_TB_PPDU_VI_DIS : 0) | + (ctrl->vo_dis ? B_AX_TB_PPDU_VO_DIS : 0); + val16 = SET_CLR_WORD(val16, pri_ac, B_AX_SW_PREFER_AC); + MAC_REG_W16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 : R_AX_TB_PPDU_CTRL, + val16); + + return MACSUCCESS; +} + +u32 get_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_tb_ppdu_ctrl *ctrl) +{ + u16 val16; + u8 pri_ac; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, ctrl->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val16 = MAC_REG_R16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 : + R_AX_TB_PPDU_CTRL); + ctrl->be_dis = (val16 & B_AX_TB_PPDU_BE_DIS) ? 1 : 0; + ctrl->bk_dis = (val16 & B_AX_TB_PPDU_BK_DIS) ? 1 : 0; + ctrl->vi_dis = (val16 & B_AX_TB_PPDU_VI_DIS) ? 1 : 0; + ctrl->vo_dis = (val16 & B_AX_TB_PPDU_VO_DIS) ? 1 : 0; + pri_ac = GET_FIELD(val16, B_AX_SW_PREFER_AC); + + switch (pri_ac) { + case 0: + ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_BE; + break; + case 1: + ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_BK; + break; + case 2: + ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_VI; + break; + case 3: + ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_VO; + break; + } + + return MACSUCCESS; +} + +u32 set_hw_sch_tx_en(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *cfg) +{ + u16 val16; + u8 band; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u16 tx_en_u16; + u16 mask_u16; + struct mac_ax_sch_tx_en tx_en; + struct mac_ax_sch_tx_en tx_en_mask; + u8 chip_id = adapter->hw_info->chip_id; + + band = cfg->band; + tx_en = cfg->tx_en; + tx_en_mask = cfg->tx_en_mask; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + sch_2_u16(adapter, &tx_en, &tx_en_u16); + sch_2_u16(adapter, &tx_en_mask, &mask_u16); + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY || + chip_id == MAC_AX_CHIP_ID_8852C || + chip_id == MAC_AX_CHIP_ID_8192XB) { + val16 = MAC_REG_R16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN); + + val16 = (tx_en_u16 & mask_u16) | (~(~tx_en_u16 & mask_u16) & val16); + + MAC_REG_W16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN, val16); + } else { + hw_sch_tx_en(adapter, band, tx_en_u16, mask_u16); + } + + return MACSUCCESS; +} + +u32 hw_sch_tx_en(struct mac_ax_adapter *adapter, u8 band, + u16 tx_en_u16, u16 mask_u16) +{ +#define RETRY_WAIT_US 1 + u32 ret; + struct mac_ax_h2creg_info h2c = {0}; + struct mac_ax_c2hreg_poll c2h = {0}; + + h2c.id = FWCMD_H2CREG_FUNC_SCH_TX_EN; + h2c.content_len = sizeof(struct sch_tx_en_h2creg); + + h2c.h2c_content.dword0 = + SET_WORD(tx_en_u16, FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN); + h2c.h2c_content.dword1 = + SET_WORD(mask_u16, FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK) | + (band ? FWCMD_H2C_H2CREG_SCH_TX_PAUSE_BAND : 0); + + c2h.polling_id = FWCMD_C2HREG_FUNC_TX_PAUSE_RPT; + c2h.retry_cnt = TX_PAUSE_WAIT_CNT; + c2h.retry_wait_us = RETRY_WAIT_US; + + ret = proc_msg_reg(adapter, &h2c, &c2h); + if (ret) { + PLTFM_MSG_ERR("[ERR]hw sch tx_en proc msg reg %d\n", ret); + return ret; + } + return MACSUCCESS; +} + +u32 get_hw_sch_tx_en(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *cfg) +{ + u8 band; + u32 ret; + u16 val16; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_sch_tx_en tx_en; + + band = cfg->band; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val16 = MAC_REG_R16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN); + u16_2_sch(adapter, &tx_en, val16); + cfg->tx_en = tx_en; + + return MACSUCCESS; +} + +u32 set_hw_lifetime_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_lifetime_cfg *cfg) +{ + u32 ret; + u8 band; + u8 val8; + u32 val32; + u32 reg_time_0, reg_time_1, reg_time_2, reg_en; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + band = cfg->band; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg_time_0 = band ? R_AX_LIFETIME_0_C1 : R_AX_LIFETIME_0; + reg_time_1 = band ? R_AX_LIFETIME_1_C1 : R_AX_LIFETIME_1; + reg_time_2 = band ? R_AX_LIFETIME_2_C1 : R_AX_LIFETIME_2; + reg_en = band ? R_AX_PTCL_COMMON_SETTING_0_C1 : + R_AX_PTCL_COMMON_SETTING_0; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (cfg->en.acq_en || cfg->en.mgq_en) { + ret = MAC_REG_W_OFLD(R_AX_TX_PASTE_TIMESTAMP_SETTING, + B_AX_HDT_TIMESTAMP_EN, 1, 0); + if (ret != MACSUCCESS) + return ret; + } + val32 = SET_WORD(cfg->val.acq_val_1, B_AX_PKT_LIFETIME_1) | + SET_WORD(cfg->val.acq_val_2, B_AX_PKT_LIFETIME_2); + ret = MAC_REG_W32_OFLD((u16)reg_time_0, val32, 0); + if (ret != MACSUCCESS) + return ret; + + val32 = SET_WORD(cfg->val.acq_val_3, B_AX_PKT_LIFETIME_3) | + SET_WORD(cfg->val.acq_val_4, B_AX_PKT_LIFETIME_4); + ret = MAC_REG_W32_OFLD((u16)reg_time_1, val32, 0); + if (ret != MACSUCCESS) + return ret; + + ret = MAC_REG_W16_OFLD((u16)reg_time_2, cfg->val.mgq_val, 0); + if (ret != MACSUCCESS) + return ret; + + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_LIFETIME_EN, + cfg->en.acq_en, 0); + if (ret != MACSUCCESS) + return ret; + ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MGQ_LIFETIME_EN, + cfg->en.mgq_en, 1); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; + } +#endif + + if (cfg->en.acq_en || cfg->en.mgq_en) + MAC_REG_W8(R_AX_TX_PASTE_TIMESTAMP_SETTING, + MAC_REG_R8(R_AX_TX_PASTE_TIMESTAMP_SETTING) | + B_AX_HDT_TIMESTAMP_EN); + + val32 = SET_WORD(cfg->val.acq_val_1, B_AX_PKT_LIFETIME_1) | + SET_WORD(cfg->val.acq_val_2, B_AX_PKT_LIFETIME_2); + MAC_REG_W32(reg_time_0, val32); + + val32 = SET_WORD(cfg->val.acq_val_3, B_AX_PKT_LIFETIME_3) | + SET_WORD(cfg->val.acq_val_4, B_AX_PKT_LIFETIME_4); + MAC_REG_W32(reg_time_1, val32); + + MAC_REG_W16(reg_time_2, cfg->val.mgq_val); + + val8 = MAC_REG_R8(reg_en); + val8 &= ~(B_AX_LIFETIME_EN | B_AX_MGQ_LIFETIME_EN); + val8 |= (cfg->en.acq_en ? B_AX_LIFETIME_EN : 0) | + (cfg->en.mgq_en ? B_AX_MGQ_LIFETIME_EN : 0); + MAC_REG_W8(reg_en, val8); + + return MACSUCCESS; +} + +u32 get_hw_lifetime_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_lifetime_cfg *cfg) +{ + u32 ret; + u8 band; + u8 val8; + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + band = cfg->band; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val8 = MAC_REG_R8(band ? R_AX_PTCL_COMMON_SETTING_0_C1 : + R_AX_PTCL_COMMON_SETTING_0); + cfg->en.acq_en = (val8 & B_AX_LIFETIME_EN) ? 1 : 0; + cfg->en.mgq_en = (val8 & B_AX_MGQ_LIFETIME_EN) ? 1 : 0; + + val32 = MAC_REG_R32(band ? R_AX_LIFETIME_0_C1 : R_AX_LIFETIME_0); + cfg->val.acq_val_1 = GET_FIELD(val32, B_AX_PKT_LIFETIME_1); + cfg->val.acq_val_2 = GET_FIELD(val32, B_AX_PKT_LIFETIME_2); + + val32 = MAC_REG_R32(band ? R_AX_LIFETIME_1_C1 : R_AX_LIFETIME_1); + cfg->val.acq_val_3 = GET_FIELD(val32, B_AX_PKT_LIFETIME_3); + cfg->val.acq_val_4 = GET_FIELD(val32, B_AX_PKT_LIFETIME_4); + + cfg->val.mgq_val = MAC_REG_R16(band ? R_AX_LIFETIME_2_C1 : + R_AX_LIFETIME_2); + + return MACSUCCESS; +} + +u32 stop_sch_tx(struct mac_ax_adapter *adapter, enum sch_tx_sel sel, + struct mac_ax_sch_tx_en_cfg *bak) +{ + struct mac_ax_sch_tx_en_cfg cfg; + u32 ret; + + ret = get_hw_sch_tx_en(adapter, bak); + if (ret != MACSUCCESS) + return ret; + + cfg.band = bak->band; + u16_2_sch(adapter, &cfg.tx_en_mask, 0); + + switch (sel) { + case SCH_TX_SEL_ALL: + u16_2_sch(adapter, &cfg.tx_en, 0); + u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF); + ret = set_hw_sch_tx_en(adapter, &cfg); + if (ret != MACSUCCESS) + return ret; + break; + case SCH_TX_SEL_HIQ: + cfg.tx_en.hi = 0; + cfg.tx_en_mask.hi = 1; + ret = set_hw_sch_tx_en(adapter, &cfg); + if (ret != MACSUCCESS) + return ret; + break; + case SCH_TX_SEL_MG0: + cfg.tx_en.mg0 = 0; + cfg.tx_en_mask.mg0 = 1; + ret = set_hw_sch_tx_en(adapter, &cfg); + if (ret != MACSUCCESS) + return ret; + break; + case SCH_TX_SEL_MACID: + u16_2_sch(adapter, &cfg.tx_en, 0); + u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF); + cfg.tx_en_mask.mg1 = 0; + cfg.tx_en_mask.mg2 = 0; + cfg.tx_en_mask.hi = 0; + cfg.tx_en_mask.bcn = 0; + ret = set_hw_sch_tx_en(adapter, &cfg); + if (ret != MACSUCCESS) + return ret; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 resume_sch_tx(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *bak) +{ + u32 ret; + + u16_2_sch(adapter, &bak->tx_en_mask, 0xFFFF); + ret = set_hw_sch_tx_en(adapter, bak); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 stop_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role, + enum tb_stop_sel stop_sel, struct macid_tx_bak *bak) +{ + u8 band; + u32 ret; + struct mac_ax_macid_pause_cfg pause; + + band = role->info.band; + + if (role->info.a_info.tf_trs) { + bak->ac_dis_bak.band = band; + ret = stop_ac_tb_tx(adapter, stop_sel, &bak->ac_dis_bak); + if (ret != MACSUCCESS) + return ret; + } + + pause.macid = role->macid; + pause.pause = 1; + ret = set_macid_pause(adapter, &pause); + if (ret != MACSUCCESS) + return ret; + + bak->sch_bak.band = band; + ret = stop_macid_ctn(adapter, role, &bak->sch_bak); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 resume_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role, + struct macid_tx_bak *bak) +{ + u32 ret; + struct mac_ax_macid_pause_cfg pause_cfg; + + if (role->info.band == MAC_AX_BAND_0) { + u16_2_sch(adapter, &bak->sch_bak.tx_en_mask, 0xFFFF); + ret = set_hw_sch_tx_en(adapter, &bak->sch_bak); + if (ret != MACSUCCESS) + return ret; + } + + if (role->info.a_info.tf_trs) { + ret = set_hw_tb_ppdu_ctrl(adapter, &bak->ac_dis_bak); + if (ret != MACSUCCESS) + return ret; + } + + pause_cfg.macid = role->macid; + pause_cfg.pause = 0; + ret = set_macid_pause(adapter, &pause_cfg); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 tx_idle_poll_macid(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role) +{ + return macid_idle_ck(adapter, role); +} + +u32 tx_idle_poll_band(struct mac_ax_adapter *adapter, u8 band, u8 txop_aware) +{ + if (txop_aware) + return tx_idle_ck(adapter, band); + + return band_idle_ck(adapter, band); +} + +u32 tx_idle_poll_sel(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel, + u8 band) +{ + return tx_idle_sel_ck_b(adapter, sel, band); +} + +u32 stop_ac_tb_tx(struct mac_ax_adapter *adapter, enum tb_stop_sel stop_sel, + struct mac_ax_tb_ppdu_ctrl *ac_dis_bak) +{ + u32 ret; + struct mac_ax_tb_ppdu_ctrl ctrl; + + ret = get_hw_tb_ppdu_ctrl(adapter, ac_dis_bak); + if (ret != MACSUCCESS) + return ret; + + ctrl.band = ac_dis_bak->band; + ctrl.pri_ac = ac_dis_bak->pri_ac; + ctrl.be_dis = 0; + ctrl.bk_dis = 0; + ctrl.vi_dis = 0; + ctrl.vo_dis = 0; + + switch (stop_sel) { + case TB_STOP_SEL_ALL: + ctrl.be_dis = 1; + ctrl.bk_dis = 1; + ctrl.vi_dis = 1; + ctrl.vo_dis = 1; + ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + break; + case TB_STOP_SEL_BE: + ctrl.be_dis = 1; + ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + break; + case TB_STOP_SEL_BK: + ctrl.bk_dis = 1; + ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + break; + case TB_STOP_SEL_VI: + ctrl.vi_dis = 1; + ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + break; + case TB_STOP_SEL_VO: + ctrl.vo_dis = 1; + ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + break; + } + + return MACSUCCESS; +} + +u32 get_edca_addr(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param, u32 *reg_edca) +{ + u8 band; + u32 ret; + enum mac_ax_cmac_path_sel path; + + band = param->band; + path = param->path; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + switch (path) { + case MAC_AX_CMAC_PATH_SEL_BE0: + *reg_edca = + band ? R_AX_EDCA_BE_PARAM_0_C1 : R_AX_EDCA_BE_PARAM_0; + break; + case MAC_AX_CMAC_PATH_SEL_BK0: + *reg_edca = + band ? R_AX_EDCA_BK_PARAM_0_C1 : R_AX_EDCA_BK_PARAM_0; + break; + case MAC_AX_CMAC_PATH_SEL_VI0: + *reg_edca = + band ? R_AX_EDCA_VI_PARAM_0_C1 : R_AX_EDCA_VI_PARAM_0; + break; + case MAC_AX_CMAC_PATH_SEL_VO0: + *reg_edca = + band ? R_AX_EDCA_VO_PARAM_0_C1 : R_AX_EDCA_VO_PARAM_0; + break; + case MAC_AX_CMAC_PATH_SEL_BE1: + *reg_edca = + band ? R_AX_EDCA_BE_PARAM_1_C1 : R_AX_EDCA_BE_PARAM_1; + break; + case MAC_AX_CMAC_PATH_SEL_BK1: + *reg_edca = + band ? R_AX_EDCA_BK_PARAM_1_C1 : R_AX_EDCA_BK_PARAM_1; + break; + case MAC_AX_CMAC_PATH_SEL_VI1: + *reg_edca = + band ? R_AX_EDCA_VI_PARAM_1_C1 : R_AX_EDCA_VI_PARAM_1; + break; + case MAC_AX_CMAC_PATH_SEL_VO1: + *reg_edca = + band ? R_AX_EDCA_VO_PARAM_1_C1 : R_AX_EDCA_VO_PARAM_1; + break; + case MAC_AX_CMAC_PATH_SEL_MG0_1: + *reg_edca = + band ? R_AX_EDCA_MGQ_PARAM_C1 : R_AX_EDCA_MGQ_PARAM; + break; + case MAC_AX_CMAC_PATH_SEL_MG2: + *reg_edca = + band ? (R_AX_EDCA_MGQ_PARAM_C1 + 2) : + (R_AX_EDCA_MGQ_PARAM + 2); + break; + case MAC_AX_CMAC_PATH_SEL_BCN: + *reg_edca = + band ? (R_AX_EDCA_BCNQ_PARAM_C1 + 2) : + (R_AX_EDCA_BCNQ_PARAM + 2); + break; + case MAC_AX_CMAC_PATH_SEL_TF: + *reg_edca = R_AX_EDCA_ULQ_PARAM; + break; + case MAC_AX_CMAC_PATH_SEL_TWT0: + *reg_edca = R_AX_EDCA_TWT_PARAM_0; + break; + case MAC_AX_CMAC_PATH_SEL_TWT1: + *reg_edca = R_AX_EDCA_TWT_PARAM_1; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 get_muedca_param_addr(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_param *param, + u32 *reg_edca) +{ + u8 band; + u32 ret; + enum mac_ax_cmac_ac_sel ac; + + band = param->band; + ac = param->ac; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + switch (ac) { + case MAC_AX_CMAC_AC_SEL_BE: + *reg_edca = + band ? R_AX_MUEDCA_BE_PARAM_0_C1 : + R_AX_MUEDCA_BE_PARAM_0; + break; + case MAC_AX_CMAC_AC_SEL_BK: + *reg_edca = + band ? R_AX_MUEDCA_BK_PARAM_0_C1 : + R_AX_MUEDCA_BK_PARAM_0; + break; + case MAC_AX_CMAC_AC_SEL_VI: + *reg_edca = + band ? R_AX_MUEDCA_VI_PARAM_0_C1 : + R_AX_MUEDCA_VI_PARAM_0; + break; + case MAC_AX_CMAC_AC_SEL_VO: + *reg_edca = + band ? R_AX_MUEDCA_VO_PARAM_0_C1 : + R_AX_MUEDCA_VO_PARAM_0; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +/* for sw mode Tx, need to stop sch */ +/* (for "F2PCMD.disable_sleep_chk"), soar 20200225*/ +static u32 stop_macid_ctn(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, + struct mac_ax_sch_tx_en_cfg *bak) +{ + struct mac_ax_sch_tx_en_cfg cfg; + u32 ret; + + ret = check_mac_en(adapter, role->info.band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + ret = get_hw_sch_tx_en(adapter, bak); + if (ret != MACSUCCESS) + return ret; + + cfg.band = role->info.band; + u16_2_sch(adapter, &cfg.tx_en_mask, 0); + + u16_2_sch(adapter, &cfg.tx_en, 0); + u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF); + cfg.tx_en_mask.mg0 = 0; + cfg.tx_en_mask.mg1 = 0; + cfg.tx_en_mask.mg2 = 0; + cfg.tx_en_mask.hi = 0; + cfg.tx_en_mask.bcn = 0; + + ret = set_hw_sch_tx_en(adapter, &cfg); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +static u32 tx_idle_ck(struct mac_ax_adapter *adapter, u8 band) +{ + u32 cnt; + u8 val8; + u32 ret; + u32 poll_addr; + u32 i; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + cnt = PTCL_IDLE_POLL_CNT; + while (--cnt) { + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) { + PLTFM_DELAY_US(SW_CVR_DUR_US); + } else { + for (i = 0; i < SW_CVR_CNT; i++) { + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) + break; + PLTFM_DELAY_US(SW_CVR_DUR_US); + } + if (i >= SW_CVR_CNT) + break; + } + } + if (!cnt) + return MACPOLLTXIDLE; + + return MACSUCCESS; +} + +static u32 tx_idle_sel_ck(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel, + u8 band) +{ + u32 cnt; + u8 val8; + u32 ret; + u32 poll_addr; + u32 i; + u8 ptcl_tx_qid; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + switch (sel) { + case PTCL_TX_SEL_HIQ: + ptcl_tx_qid = PTCL_TXQ_HIQ; + break; + case PTCL_TX_SEL_MG0: + ptcl_tx_qid = PTCL_TXQ_MG0; + break; + default: + return MACNOITEM; + } + + cnt = PTCL_IDLE_POLL_CNT; + while (--cnt) { + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) { + if (GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) == + ptcl_tx_qid) + PLTFM_DELAY_US(SW_CVR_DUR_US); + else + break; + } else { + for (i = 0; i < SW_CVR_CNT; i++) { + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) + break; + PLTFM_DELAY_US(SW_CVR_DUR_US); + } + if ((val8 & B_AX_PTCL_TX_ON_STAT) && + GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) != + ptcl_tx_qid) + break; + if (i >= SW_CVR_CNT) + break; + } + } + if (!cnt) + return MACPOLLTXIDLE; + + return MACSUCCESS; +} + +static u32 tx_idle_sel_ck_b(struct mac_ax_adapter *adapter, + enum ptcl_tx_sel sel, u8 band) +{ + u32 cnt; + u8 val8; + u32 ret; + u8 ptcl_tx_qid; + u32 poll_addr; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) + tx_on_dly(adapter, band); + else + return MACSUCCESS; + + switch (sel) { + case PTCL_TX_SEL_HIQ: + ptcl_tx_qid = PTCL_TXQ_HIQ; + break; + case PTCL_TX_SEL_MG0: + ptcl_tx_qid = PTCL_TXQ_MG0; + break; + default: + return MACNOITEM; + } + + cnt = PTCL_IDLE_POLL_CNT; + while (--cnt) { + val8 = MAC_REG_R8(poll_addr); + if ((val8 & B_AX_PTCL_TX_ON_STAT) && (val8 & B_AX_PTCL_DROP)) + PLTFM_DELAY_US(SW_CVR_DUR_US); + else if ((val8 & B_AX_PTCL_TX_ON_STAT) && + (GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) == + ptcl_tx_qid)) + PLTFM_DELAY_US(SW_CVR_DUR_US); + else + break; + } + if (!cnt) + return MACPOLLTXIDLE; + + return MACSUCCESS; +} + +static u32 macid_idle_ck(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role) +{ + u32 cnt; + u8 val8; + u32 ret; + u8 band; + u32 val32; + u8 macid; + u8 txq; + u32 poll_addr; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + band = role->info.band; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) + tx_on_dly(adapter, band); + else + return MACSUCCESS; + + macid = role->macid; + + cnt = PTCL_IDLE_POLL_CNT; + while (--cnt) { + val8 = MAC_REG_R8(poll_addr); + txq = GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX); + if ((val8 & B_AX_PTCL_TX_ON_STAT) && (val8 & B_AX_PTCL_DROP)) { + PLTFM_DELAY_US(SW_CVR_DUR_US); + } else if ((val8 & B_AX_PTCL_TX_ON_STAT) && + txq != PTCL_TXQ_HIQ && txq != PTCL_TXQ_BCNQ && + txq != PTCL_TXQ_MG0 && txq != PTCL_TXQ_MG1 && + txq != PTCL_TXQ_MG2 && txq != PTCL_TXQ_TB) { + PLTFM_DELAY_US(SW_CVR_DUR_US); + /* need to modify for 8852C, soar */ + val32 = MAC_REG_R32(band ? R_AX_PTCL_TX_MACID_0_C1 : + R_AX_PTCL_TX_MACID_0); + if (macid == GET_FIELD(val32, B_AX_TX_MACID_0) || + macid == GET_FIELD(val32, B_AX_TX_MACID_1) || + macid == GET_FIELD(val32, B_AX_TX_MACID_2) || + macid == GET_FIELD(val32, B_AX_TX_MACID_3)) + PLTFM_DELAY_US(SW_CVR_DUR_US); + else + break; + } else { + break; + } + } + if (!cnt) + return MACPOLLTXIDLE; + + return MACSUCCESS; +} + +static u32 band_idle_ck(struct mac_ax_adapter *adapter, u8 band) +{ + u32 cnt; + u8 val8; + u32 ret; + u32 poll_addr; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + cnt = PTCL_IDLE_POLL_CNT; + while (--cnt) { + val8 = MAC_REG_R8(poll_addr); + if (val8 & B_AX_PTCL_TX_ON_STAT) + PLTFM_DELAY_US(SW_CVR_DUR_US); + else + break; + } + if (!cnt) + return MACPOLLTXIDLE; + + return MACSUCCESS; +} + +static void tx_on_dly(struct mac_ax_adapter *adapter, u8 band) +{ + u32 val32; + u32 drop_dly_max; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(band ? R_AX_TX_CTRL_C1 : R_AX_TX_CTRL); + drop_dly_max = GET_FIELD(val32, B_AX_DROP_CHK_MAX_NUM) >> 2; + PLTFM_DELAY_US((drop_dly_max > TX_DLY_MAX) ? drop_dly_max : TX_DLY_MAX); +} + +static void sch_2_u16(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en *tx_en, u16 *val16) +{ + *val16 = (tx_en->be0 ? B_AX_CTN_TXEN_BE_0 : 0) | + (tx_en->bk0 ? B_AX_CTN_TXEN_BK_0 : 0) | + (tx_en->vi0 ? B_AX_CTN_TXEN_VI_0 : 0) | + (tx_en->vo0 ? B_AX_CTN_TXEN_VO_0 : 0) | + (tx_en->be1 ? B_AX_CTN_TXEN_BE_1 : 0) | + (tx_en->bk1 ? B_AX_CTN_TXEN_BK_1 : 0) | + (tx_en->vi1 ? B_AX_CTN_TXEN_VI_1 : 0) | + (tx_en->vo1 ? B_AX_CTN_TXEN_VO_1 : 0) | + (tx_en->mg0 ? B_AX_CTN_TXEN_MGQ : 0) | + (tx_en->mg1 ? B_AX_CTN_TXEN_MGQ1 : 0) | + (tx_en->mg2 ? B_AX_CTN_TXEN_CPUMGQ : 0) | + (tx_en->hi ? B_AX_CTN_TXEN_HGQ : 0) | + (tx_en->bcn ? B_AX_CTN_TXEN_BCNQ : 0) | + (tx_en->ul ? B_AX_CTN_TXEN_ULQ : 0) | + (tx_en->twt0 ? B_AX_CTN_TXEN_TWT_0 : 0) | + (tx_en->twt1 ? B_AX_CTN_TXEN_TWT_1 : 0); +} + +static void u16_2_sch(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en *tx_en, u16 val16) +{ + tx_en->be0 = val16 & B_AX_CTN_TXEN_BE_0 ? 1 : 0; + tx_en->bk0 = val16 & B_AX_CTN_TXEN_BK_0 ? 1 : 0; + tx_en->vi0 = val16 & B_AX_CTN_TXEN_VI_0 ? 1 : 0; + tx_en->vo0 = val16 & B_AX_CTN_TXEN_VO_0 ? 1 : 0; + tx_en->be1 = val16 & B_AX_CTN_TXEN_BE_1 ? 1 : 0; + tx_en->bk1 = val16 & B_AX_CTN_TXEN_BK_1 ? 1 : 0; + tx_en->vi1 = val16 & B_AX_CTN_TXEN_VI_1 ? 1 : 0; + tx_en->vo1 = val16 & B_AX_CTN_TXEN_VO_1 ? 1 : 0; + tx_en->mg0 = val16 & B_AX_CTN_TXEN_MGQ ? 1 : 0; + tx_en->mg1 = val16 & B_AX_CTN_TXEN_MGQ1 ? 1 : 0; + tx_en->mg2 = val16 & B_AX_CTN_TXEN_CPUMGQ ? 1 : 0; + tx_en->hi = val16 & B_AX_CTN_TXEN_HGQ ? 1 : 0; + tx_en->bcn = val16 & B_AX_CTN_TXEN_BCNQ ? 1 : 0; + tx_en->ul = val16 & B_AX_CTN_TXEN_ULQ ? 1 : 0; + tx_en->twt0 = val16 & B_AX_CTN_TXEN_TWT_0 ? 1 : 0; + tx_en->twt1 = val16 & B_AX_CTN_TXEN_TWT_1 ? 1 : 0; +} + +static u32 h2c_usr_edca(struct mac_ax_adapter *adapter, + struct mac_ax_usr_edca_param *param) +{ + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_usr_edca *fwcmd_tbl; + u32 ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_WARN("%s fw not ready\n", __func__); + return MACFWNONRDY; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_usr_edca)); + if (!buf) { + ret = MACNOBUF; + goto usr_edca_fail; + } + + fwcmd_tbl = (struct fwcmd_usr_edca *)buf; + fwcmd_tbl->dword0 = + cpu_to_le32(SET_WORD(param->idx, FWCMD_H2C_USR_EDCA_PARAM_SEL) | + (param->enable ? FWCMD_H2C_USR_EDCA_ENABLE : 0) | + (param->band ? FWCMD_H2C_USR_EDCA_BAND : 0) | + (param->wmm ? FWCMD_H2C_USR_EDCA_WMM : 0) | + SET_WORD(param->ac, FWCMD_H2C_USR_EDCA_AC)); + fwcmd_tbl->dword1 = + cpu_to_le32(SET_WORD(param->aggressive.txop_32us, B_AX_BE_0_TXOPLMT) | + SET_WORD((param->aggressive.ecw_max << 4) | + param->aggressive.ecw_min, B_AX_BE_0_CW) | + SET_WORD(param->aggressive.aifs_us, B_AX_BE_0_AIFS)); + fwcmd_tbl->dword2 = + cpu_to_le32(SET_WORD(param->moderate.txop_32us, B_AX_BE_0_TXOPLMT) | + SET_WORD((param->moderate.ecw_max << 4) | + param->moderate.ecw_min, B_AX_BE_0_CW) | + SET_WORD(param->moderate.aifs_us, B_AX_BE_0_AIFS)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_USR_EDCA, + 0, + 0); + + if (ret != MACSUCCESS) + goto usr_edca_fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto usr_edca_fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto usr_edca_fail; + + h2cb_free(adapter, h2cb); + return MACSUCCESS; + +usr_edca_fail: + h2cb_free(adapter, h2cb); + return ret; +} + +static u32 h2c_usr_tx_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_usr_tx_rpt_cfg *param) +{ + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_usr_tx_rpt *fwcmd_tbl; + u32 ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_WARN("%s fw not ready\n", __func__); + return MACFWNONRDY; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_usr_tx_rpt)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_tbl = (struct fwcmd_usr_tx_rpt *)buf; + fwcmd_tbl->dword0 = + cpu_to_le32(SET_WORD(param->mode, FWCMD_H2C_USR_TX_RPT_MODE) | + (param->rpt_start ? FWCMD_H2C_USR_TX_RPT_RTP_START : 0)); + fwcmd_tbl->dword1 = + cpu_to_le32(SET_WORD(param->macid, FWCMD_H2C_USR_TX_RPT_MACID) | + (param->band ? FWCMD_H2C_USR_TX_RPT_BAND : 0) | + SET_WORD(param->port, FWCMD_H2C_USR_TX_RPT_PORT)); + fwcmd_tbl->dword2 = cpu_to_le32(param->rpt_period_us); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_USR_TX_RPT, + 0, + 0); + + if (ret != MACSUCCESS) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + return MACSUCCESS; + +fail: + h2cb_free(adapter, h2cb); + return ret; +} + +u32 mac_set_cctl_max_tx_time(struct mac_ax_adapter *adapter, + struct mac_ax_max_tx_time *tx_time) +{ +#define MAC_AX_DFLT_TX_TIME 5280 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_cctl_info info, msk = {0}; + u32 ret = MACSUCCESS; + struct mac_role_tbl *role; + u8 band; + u32 offset, max_tx_time; + + role = mac_role_srch(adapter, tx_time->macid); + if (!role) { + PLTFM_MSG_ERR("%s: The MACID%d does not exist\n", + __func__, tx_time->macid); + return MACNOITEM; + } + + max_tx_time = tx_time->max_tx_time == 0 ? + MAC_AX_DFLT_TX_TIME : tx_time->max_tx_time; + + if (tx_time->is_cctrl) { + msk.ampdu_time_sel = 1; + info.ampdu_time_sel = 1; + msk.ampdu_max_time = FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_MSK; + info.ampdu_max_time = (max_tx_time - 512) >> 9; + ret = mac_upd_cctl_info(adapter, &info, &msk, tx_time->macid, 1); + } else { + band = role->info.wmm < 2 ? 0 : 1; + offset = band == 0 ? R_AX_AMPDU_AGG_LIMIT + 3 : + R_AX_AMPDU_AGG_LIMIT_C1 + 3; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W8_OFLD((u16)offset, + max_tx_time >> 5, + 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: ofld fail %d\n", + __func__, ret); + return ret; + } +#endif + MAC_REG_W8(offset, max_tx_time >> 5); + } + + return ret; +} + +u32 mac_get_max_tx_time(struct mac_ax_adapter *adapter, + struct mac_ax_max_tx_time *tx_time) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + struct mac_role_tbl *role; + u32 offset; + u8 band; + + role = mac_role_srch(adapter, tx_time->macid); + if (!role) { + PLTFM_MSG_ERR("%s: The MACID%d does not exist\n", + __func__, tx_time->macid); + return MACNOITEM; + } + + if (role->info.c_info.ampdu_time_sel) { + tx_time->max_tx_time = (role->info.c_info.ampdu_max_time + 1) << 9; + tx_time->is_cctrl = 1; + } else { + band = role->info.wmm < 2 ? 0 : 1; + offset = band == 0 ? R_AX_AMPDU_AGG_LIMIT + 3 : + R_AX_AMPDU_AGG_LIMIT_C1 + 3; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret == MACSUCCESS) + tx_time->max_tx_time = MAC_REG_R8(offset) << 5; + tx_time->is_cctrl = 0; + } + + return ret; +} + +u32 mac_set_hw_rts_th(struct mac_ax_adapter *adapter, + struct mac_ax_hw_rts_th *th) +{ +#define MAC_AX_MULT32_SH 5 +#define MAC_AX_MULT16_SH 4 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, offset; + u16 val; + + ret = check_mac_en(adapter, th->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + offset = th->band ? R_AX_AGG_LEN_HT_0_C1 : R_AX_AGG_LEN_HT_0; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)offset, + B_AX_RTS_LEN_TH_MSK << B_AX_RTS_LEN_TH_SH, + th->len_th >> MAC_AX_MULT16_SH, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + ret = MAC_REG_W_OFLD((u16)offset, + B_AX_RTS_TXTIME_TH_MSK << + B_AX_RTS_TXTIME_TH_SH, + th->time_th >> MAC_AX_MULT32_SH, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + return MACSUCCESS; + } +#endif + val = SET_WORD(th->len_th >> MAC_AX_MULT16_SH, B_AX_RTS_LEN_TH) | + SET_WORD(th->time_th >> MAC_AX_MULT32_SH, B_AX_RTS_TXTIME_TH); + MAC_REG_W16(offset, val); + + return MACSUCCESS; +} + +u32 mac_get_hw_rts_th(struct mac_ax_adapter *adapter, + struct mac_ax_hw_rts_th *th) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, offset; + u16 val; + + ret = check_mac_en(adapter, th->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + offset = th->band ? R_AX_AGG_LEN_HT_0_C1 : R_AX_AGG_LEN_HT_0; + val = MAC_REG_R16(offset); + + th->len_th = GET_FIELD(val, B_AX_RTS_LEN_TH); + th->len_th = th->len_th << MAC_AX_MULT16_SH; + th->time_th = GET_FIELD(val, B_AX_RTS_TXTIME_TH); + th->time_th = th->time_th << MAC_AX_MULT32_SH; + + return MACSUCCESS; +#undef MAC_AX_MULT32_SH +#undef MAC_AX_MULT16_SH +} + +u32 mac_tx_idle_poll(struct mac_ax_adapter *adapter, + struct mac_ax_tx_idle_poll_cfg *poll_cfg) +{ + switch (poll_cfg->sel) { + case MAC_AX_TX_IDLE_POLL_SEL_BAND: + return tx_idle_poll_band(adapter, poll_cfg->band, 1); + default: + return MACNOITEM; + } +} + +u32 mac_set_tx_ru26_tb(struct mac_ax_adapter *adapter, + u8 disable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + +#if MAC_AX_FW_REG_OFLD + u32 ret; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (disable) + ret = MAC_REG_W_OFLD(R_AX_RXTRIG_TEST_USER_2, B_AX_RXTRIG_RU26_DIS, 1, 1); + else + ret = MAC_REG_W_OFLD(R_AX_RXTRIG_TEST_USER_2, B_AX_RXTRIG_RU26_DIS, 0, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, R_AX_RXTRIG_TEST_USER_2); + return ret; + } + return MACSUCCESS; + } +#endif + val32 = MAC_REG_R32(R_AX_RXTRIG_TEST_USER_2) & (~B_AX_RXTRIG_RU26_DIS); + + if (disable) + MAC_REG_W32(R_AX_RXTRIG_TEST_USER_2, val32 | B_AX_RXTRIG_RU26_DIS); + else + MAC_REG_W32(R_AX_RXTRIG_TEST_USER_2, val32); + + return MACSUCCESS; +} + +u32 mac_tx_duty(struct mac_ax_adapter *adapter, + u16 pause_intvl, u16 tx_intvl) +{ + u32 ret; + + if (!(pause_intvl) || !(tx_intvl)) + return MACFUNCINPUT; + + ret = tx_duty_h2c(adapter, pause_intvl, tx_intvl); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 mac_tx_duty_stop(struct mac_ax_adapter *adapter) +{ + u32 ret; + + ret = tx_duty_h2c(adapter, 0, 0); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 tx_duty_h2c(struct mac_ax_adapter *adapter, + u16 pause_intvl, u16 tx_intvl) +{ + u32 ret, size; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + u8 *buf; + struct fwcmd_tx_duty cfg; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + size = sizeof(struct fwcmd_tx_duty); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, size); + if (!buf) { + h2cb_free(adapter, h2cb); + return MACNOBUF; + } + + cfg.dword0 = + cpu_to_le32(SET_WORD(pause_intvl, FWCMD_H2C_TX_DUTY_PAUSE_INTVL) | + SET_WORD(tx_intvl, FWCMD_H2C_TX_DUTY_TX_INTVL) + ); + cfg.dword1 = cpu_to_le32(pause_intvl ? 0 : FWCMD_H2C_TX_DUTY_STOP); + + PLTFM_MEMCPY(buf, &cfg, size); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_TX_DUTY, + 0, 0); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + h2cb_free(adapter, h2cb); + return ret; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/cmac_tx.h b/phl/hal_g6/mac/mac_ax/cmac_tx.h new file mode 100644 index 0000000..9ad9724 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/cmac_tx.h @@ -0,0 +1,787 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_CMAC_TX_H_ +#define _MAC_AX_CMAC_TX_H_ + +#include "../type.h" +#include "trxcfg.h" +#include "role.h" +#include "hw.h" +#include "dbgpkg.h" + +/*--------------------Define ----------------------------------------*/ +#define PTCL_TXQ_WMM0_BE 0 +#define PTCL_TXQ_WMM0_BK 1 +#define PTCL_TXQ_WMM0_VI 2 +#define PTCL_TXQ_WMM0_VO 3 +#define PTCL_TXQ_WMM1_BE 4 +#define PTCL_TXQ_WMM1_BK 5 +#define PTCL_TXQ_WMM1_VI 6 +#define PTCL_TXQ_WMM1_VO 7 +#define PTCL_TXQ_MG0 8 +#define PTCL_TXQ_MG1 9 +#define PTCL_TXQ_MG2 10 +#define PTCL_TXQ_HIQ 11 +#define PTCL_TXQ_BCNQ 12 +#define PTCL_TXQ_UL 13 +#define PTCL_TXQ_TWT0 14 +#define PTCL_TXQ_TWT1 15 +#define PTCL_TXQ_TB 16 + +#define TX_PAUSE_WAIT_CNT 5000 + +/*--------------------Define Enum------------------------------------*/ + +/** + * @enum tb_stop_sel + * + * @brief tb_stop_sel + * + * @var tb_stop_sel::TB_STOP_SEL_BE + * Please Place Description here. + * @var tb_stop_sel::TB_STOP_SEL_BK + * Please Place Description here. + * @var tb_stop_sel::TB_STOP_SEL_VI + * Please Place Description here. + * @var tb_stop_sel::TB_STOP_SEL_VO + * Please Place Description here. + * @var tb_stop_sel::TB_STOP_SEL_ALL + * Please Place Description here. + */ +enum tb_stop_sel { + TB_STOP_SEL_BE, + TB_STOP_SEL_BK, + TB_STOP_SEL_VI, + TB_STOP_SEL_VO, + TB_STOP_SEL_ALL, +}; + +/** + * @enum sch_tx_sel + * + * @brief sch_tx_sel + * + * @var sch_tx_sel::SCH_TX_SEL_ALL + * Please Place Description here. + * @var sch_tx_sel::SCH_TX_SEL_HIQ + * Please Place Description here. + * @var sch_tx_sel::SCH_TX_SEL_MG0 + * Please Place Description here. + * @var sch_tx_sel::SCH_TX_SEL_MACID + * Please Place Description here. + */ +enum sch_tx_sel { + SCH_TX_SEL_ALL, + SCH_TX_SEL_HIQ, + SCH_TX_SEL_MG0, + SCH_TX_SEL_MACID, +}; + +/** + * @enum ptcl_tx_sel + * + * @brief ptcl_tx_sel + * + * @var ptcl_tx_sel::PTCL_TX_SEL_HIQ + * Please Place Description here. + * @var ptcl_tx_sel::PTCL_TX_SEL_MG0 + * Please Place Description here. + */ +enum ptcl_tx_sel { + PTCL_TX_SEL_HIQ, + PTCL_TX_SEL_MG0, +}; + +/*--------------------Define MACRO----------------------------------*/ +/*--------------------Define Struct----------------------------------*/ + +/** + * @struct sch_tx_en_h2creg + * @brief sch_tx_en_h2creg + * + * @var sch_tx_en_h2creg::tx_en + * Please Place Description here. + * @var sch_tx_en_h2creg::mask + * Please Place Description here. + * @var sch_tx_en_h2creg::band + * Please Place Description here. + * @var sch_tx_en_h2creg::rsvd + * Please Place Description here. + */ +struct sch_tx_en_h2creg { + /* dword0 */ + u32 tx_en:16; + /* dword1 */ + u32 mask:16; + u32 band:1; + u32 rsvd0:15; +}; + +/*--------------------Export global variable----------------------------*/ +/*--------------------Function declaration-----------------------------*/ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ +/** + * @brief set_hw_ampdu_cfg + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_ampdu_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_ampdu_cfg *cfg); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_usr_edca_param + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_usr_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_usr_edca_param *param); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_usr_tx_rpt_cfg + * + * @param *adapter + * @param *cfg + * @return MACSUCCESS + * @retval u32 + */ +u32 set_hw_usr_tx_rpt_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_usr_tx_rpt_cfg *cfg); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_edca_param + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief get_hw_edca_param + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 get_hw_edca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_edcca_param + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_edcca_param(struct mac_ax_adapter *adapter, + struct mac_ax_edcca_param *param); +/** + * @} + * @} + */ + +/** + * @brief set_hw_muedca_param + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_muedca_param(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_param *param); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_muedca_ctrl + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_muedca_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_cfg *cfg); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_tb_ppdu_ctrl + * + * @param *adapter + * @param *ctrl + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_tb_ppdu_ctrl *ctrl); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief get_hw_tb_ppdu_ctrl + * + * @param *adapter + * @param *ctrl + * @return Please Place Description here. + * @retval u32 + */ +u32 get_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_tb_ppdu_ctrl *ctrl); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_sch_tx_en + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_sch_tx_en(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief hw_sch_tx_en + * + * @param *adapter + * @param band + * @param tx_en_u16 + * @param mask_u16 + * @return Please Place Description here. + * @retval u32 + */ +u32 hw_sch_tx_en(struct mac_ax_adapter *adapter, u8 band, + u16 tx_en_u16, u16 mask_u16); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief get_hw_sch_tx_en + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 get_hw_sch_tx_en(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief set_hw_lifetime_cfg + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_lifetime_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_lifetime_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @brief get_hw_lifetime_cfg + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 get_hw_lifetime_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_lifetime_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief stop_sch_tx + * + * @param *adapter + * @param sel + * @param *bak + * @return Please Place Description here. + * @retval u32 + */ +u32 stop_sch_tx(struct mac_ax_adapter *adapter, enum sch_tx_sel sel, + struct mac_ax_sch_tx_en_cfg *bak); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief resume_sch_tx + * + * @param *adapter + * @param *bak + * @return Please Place Description here. + * @retval u32 + */ +u32 resume_sch_tx(struct mac_ax_adapter *adapter, + struct mac_ax_sch_tx_en_cfg *bak); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief stop_macid_tx + * + * @param *adapter + * @param *role + * @param stop_sel + * @param *bak + * @return Please Place Description here. + * @retval u32 + */ +u32 stop_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role, + enum tb_stop_sel stop_sel, struct macid_tx_bak *bak); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief resume_macid_tx + * + * @param *adapter + * @param *role + * @param *bak + * @return Please Place Description here. + * @retval u32 + */ +u32 resume_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role, + struct macid_tx_bak *bak); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief tx_idle_poll_macid + * + * @param *adapter + * @param *role + * @return Please Place Description here. + * @retval u32 + */ +u32 tx_idle_poll_macid(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief tx_idle_poll_band + * + * @param *adapter + * @param band: 0/1 for band 0/1 + * @param txop_aware: 1: polling until end of TXOP; 0: polling until end of Tx sequence + * @return MACSUCCESS + * @retval u32 + */ +u32 tx_idle_poll_band(struct mac_ax_adapter *adapter, u8 band, u8 txop_aware); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief tx_idle_poll_sel + * + * @param *adapter + * @param sel + * @param band + * @return Please Place Description here. + * @retval u32 + */ +u32 tx_idle_poll_sel(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel, + u8 band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief stop_ac_tb_tx + * + * @param *adapter + * @param stop_sel + * @param *ac_dis_bak + * @return Please Place Description here. + * @retval u32 + */ +u32 stop_ac_tb_tx(struct mac_ax_adapter *adapter, enum tb_stop_sel stop_sel, + struct mac_ax_tb_ppdu_ctrl *ac_dis_bak); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +u32 get_edca_addr(struct mac_ax_adapter *adapter, + struct mac_ax_edca_param *param, u32 *reg_edca); + +u32 get_muedca_param_addr(struct mac_ax_adapter *adapter, + struct mac_ax_muedca_param *param, + u32 *reg_edca); + +/** + * @brief mac_set_cctl_max_tx_time + * + * @param *adapter + * @param *tx_time + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_cctl_max_tx_time(struct mac_ax_adapter *adapter, + struct mac_ax_max_tx_time *tx_time); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_get_max_tx_time + * + * @param *adapter + * @param *tx_time + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_max_tx_time(struct mac_ax_adapter *adapter, + struct mac_ax_max_tx_time *tx_time); +/** + * @} + * @} + */ +u32 mac_tx_idle_poll(struct mac_ax_adapter *adapter, + struct mac_ax_tx_idle_poll_cfg *poll_cfg); +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_set_hw_rts_th + * + * @param *adapter + * @param * + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_hw_rts_th(struct mac_ax_adapter *adapter, + struct mac_ax_hw_rts_th *th); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_get_hw_rts_th + * + * @param *adapter + * @param * + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_hw_rts_th(struct mac_ax_adapter *adapter, + struct mac_ax_hw_rts_th *th); +/** + * @} + * @} + */ + +/** + * @brief mac_set_tx_ru26_tb + * + * @param *adapter + * @param disable + * @return To enable or disable responding TB in RU26 + * @retval u32 + */ +u32 mac_set_tx_ru26_tb(struct mac_ax_adapter *adapter, + u8 disable); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_tx_duty + * + * @param *adapter + * @param pause_intvl + * @param tx_intvl + * @return Do tx_duty for Thermal Prodection + * @retval u32 + */ +u32 mac_tx_duty(struct mac_ax_adapter *adapter, + u16 pause_intvl, u16 tx_intvl); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_tx_duty_stop + * + * @param *adapter + * @param pause_intvl + * @param tx_intvl + * @return Stop tx_duty for Thermal Prodection + * @retval u32 + */ +u32 mac_tx_duty_stop(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/coex.c b/phl/hal_g6/mac/mac_ax/coex.c new file mode 100644 index 0000000..3e3b788 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/coex.c @@ -0,0 +1,498 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "coex.h" +#include "../mac_reg.h" +#include "hw.h" +#include "power_saving.h" + +#define MAC_AX_RTK_RATE 5 + +#define MAC_AX_BT_MODE_0_3 0 +#define MAC_AX_BT_MODE_2 2 + +#define MAC_AX_CSR_DELAY 0 +#define MAC_AX_CSR_PRI_TO 5 +#define MAC_AX_CSR_TRX_TO 4 + +#define MAC_AX_CSR_RATE 80 + +#define MAC_AX_SB_DRV_MSK 0xFFFFFF +#define MAC_AX_SB_DRV_SH 0 +#define MAC_AX_SB_FW_MSK 0x7F +#define MAC_AX_SB_FW_SH 24 + +#define R_AX_LTECOEX_STATUS 0x54 +#define B_AX_GNT_BT_RFC_S0_STA BIT(3) +#define B_AX_GNT_WL_RFC_S0_STA BIT(2) +#define B_AX_GNT_BT_RFC_S1_STA BIT(5) +#define B_AX_GNT_WL_RFC_S1_STA BIT(4) + +#define MAC_AX_BTGS1_NOTIFY BIT(0) + +u32 mac_coex_init(struct mac_ax_adapter *adapter, + struct mac_ax_coex *coex) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val; + u16 val16; + u32 ret, val32; + + val = MAC_REG_R8(R_AX_GPIO_MUXCFG); + MAC_REG_W8(R_AX_GPIO_MUXCFG, val | B_AX_ENBT); + + switch (coex->direction) { + case MAC_AX_COEX_INNER: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1); + val = (val & ~BIT(2)) | BIT(1); + MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val); + break; + case MAC_AX_COEX_OUTPUT: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1); + val = val | BIT(1) | BIT(0); + MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val); + break; + case MAC_AX_COEX_INPUT: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1); + val = val & ~(BIT(2) | BIT(1)); + MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val); + break; + default: + return MACNOITEM; + } + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD(R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN, + 1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_2, + B_AX_GNT_BT_BYPASS_PRIORITY, + 1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_CSR_MODE, + B_AX_WL_ACT_MSK | B_AX_STATIS_BT_EN | + B_AX_BT_CNT_REST, + 0x4003, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_TRXPTCL_RESP_0, B_AX_RSP_CHK_BTCCA, + 0, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_CCA_CFG_0, + B_AX_BTCCA_BRK_TXOP_EN | B_AX_BTCCA_EN, + 1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + switch (coex->pta_mode) { + case MAC_AX_COEX_RTK_MODE: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG); + val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, + B_AX_BTMODE); + MAC_REG_W8(R_AX_GPIO_MUXCFG, val); + + ret = MAC_REG_W_OFLD(R_AX_TDMA_MODE, + B_AX_RTK_BT_ENABLE, + 1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_5, + B_AX_BT_RPT_SAMPLE_RATE_MSK << + B_AX_BT_RPT_SAMPLE_RATE_SH, + MAC_AX_RTK_RATE, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + break; + case MAC_AX_COEX_CSR_MODE: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG); + val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); + MAC_REG_W8(R_AX_GPIO_MUXCFG, val); + + ret = MAC_REG_W_OFLD(R_AX_CSR_MODE, + B_AX_BT_PRI_DETECT_TO_MSK << + B_AX_BT_PRI_DETECT_TO_SH, + MAC_AX_CSR_PRI_TO, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_CSR_MODE, + B_AX_BT_TRX_INIT_DETECT_MSK << + B_AX_BT_TRX_INIT_DETECT_SH, + MAC_AX_CSR_TRX_TO, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_CSR_MODE, + B_AX_BT_STAT_DELAY_MSK << + B_AX_BT_STAT_DELAY_SH, + MAC_AX_CSR_DELAY, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W8_OFLD(R_AX_BT_COEX_CFG_2, + MAC_AX_CSR_RATE, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + break; + default: + return MACNOITEM; + } + + return ret; + } +#endif + + val = MAC_REG_R8(R_AX_BTC_FUNC_EN); + MAC_REG_W8(R_AX_BTC_FUNC_EN, val | B_AX_PTA_WL_TX_EN); + + val = MAC_REG_R8(R_AX_BT_COEX_CFG_2 + 1); + MAC_REG_W8(R_AX_BT_COEX_CFG_2 + 1, val | BIT(0)); + + val = MAC_REG_R8(R_AX_CSR_MODE); + MAC_REG_W8(R_AX_CSR_MODE, val | B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); + + val = MAC_REG_R8(R_AX_CSR_MODE + 2); + MAC_REG_W8(R_AX_CSR_MODE + 2, val | BIT(0)); + + val = MAC_REG_R8(R_AX_TRXPTCL_RESP_0 + 3); + MAC_REG_W8(R_AX_TRXPTCL_RESP_0 + 3, val & ~BIT(1)); + + val16 = MAC_REG_R16(R_AX_CCA_CFG_0); + val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; + MAC_REG_W16(R_AX_CCA_CFG_0, val16); + + ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val32); + if (ret) { + PLTFM_MSG_ERR("%s: Read LTE fail!\n", __func__); + return ret; + } + val32 = val32 & B_AX_WL_RX_CTRL; + ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val32); + if (ret) { + PLTFM_MSG_ERR("%s: Write LTE fail!\n", __func__); + return ret; + } + + switch (coex->pta_mode) { + case MAC_AX_COEX_RTK_MODE: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG); + val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, + B_AX_BTMODE); + MAC_REG_W8(R_AX_GPIO_MUXCFG, val); + + val = MAC_REG_R8(R_AX_TDMA_MODE); + MAC_REG_W8(R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); + + val = MAC_REG_R8(R_AX_BT_COEX_CFG_5); + val = SET_CLR_WORD(val, MAC_AX_RTK_RATE, + B_AX_BT_RPT_SAMPLE_RATE); + MAC_REG_W8(R_AX_BT_COEX_CFG_5, val); + break; + case MAC_AX_COEX_CSR_MODE: + val = MAC_REG_R8(R_AX_GPIO_MUXCFG); + val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); + MAC_REG_W8(R_AX_GPIO_MUXCFG, val); + + val16 = MAC_REG_R16(R_AX_CSR_MODE); + val16 = SET_CLR_WORD(val16, MAC_AX_CSR_PRI_TO, + B_AX_BT_PRI_DETECT_TO); + val16 = SET_CLR_WORD(val16, MAC_AX_CSR_TRX_TO, + B_AX_BT_TRX_INIT_DETECT); + val16 = SET_CLR_WORD(val16, MAC_AX_CSR_DELAY, + B_AX_BT_STAT_DELAY); + val16 = val16 | B_AX_ENHANCED_BT; + MAC_REG_W16(R_AX_CSR_MODE, val16); + + MAC_REG_W8(R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_get_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg) +{ + u32 val, ret, status; + struct mac_ax_gnt *gnt; + + ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val); + if (ret) { + PLTFM_MSG_ERR("Read LTE fail!\n"); + return ret; + } + + ret = mac_read_lte(adapter, R_AX_LTECOEX_STATUS, &status); + if (ret) { + PLTFM_MSG_ERR("Read LTE fail!\n"); + return ret; + } + + gnt = &gnt_cfg->band0; + gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S0_SW_CTRL); + gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S0_STA); + gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S0_SW_CTRL); + gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S0_STA); + + gnt = &gnt_cfg->band1; + gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S1_SW_CTRL); + gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S1_STA); + gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S1_SW_CTRL); + gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S1_STA); + + return MACSUCCESS; +} + +u32 mac_cfg_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg) +{ + u32 val, ret; + + ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val); + if (ret) { + PLTFM_MSG_ERR("Read LTE fail!\n"); + return ret; + } + val = (gnt_cfg->band0.gnt_bt ? (B_AX_GNT_BT_RFC_S0_SW_VAL | + B_AX_GNT_BT_BB_S0_SW_VAL) : 0) | + (gnt_cfg->band0.gnt_bt_sw_en ? + (B_AX_GNT_BT_RFC_S0_SW_CTRL | + B_AX_GNT_BT_BB_S0_SW_CTRL) : 0) | + (gnt_cfg->band0.gnt_wl ? (B_AX_GNT_WL_RFC_S0_SW_VAL | + B_AX_GNT_WL_BB_S0_SW_VAL) : 0) | + (gnt_cfg->band0.gnt_wl_sw_en ? + (B_AX_GNT_WL_RFC_S0_SW_CTRL | + B_AX_GNT_WL_BB_S0_SW_CTRL) : 0) | + (gnt_cfg->band1.gnt_bt ? (B_AX_GNT_BT_RFC_S1_SW_VAL | + B_AX_GNT_BT_BB_S1_SW_VAL) : 0) | + (gnt_cfg->band1.gnt_bt_sw_en ? + (B_AX_GNT_BT_RFC_S1_SW_CTRL | + B_AX_GNT_BT_BB_S1_SW_CTRL) : 0) | + (gnt_cfg->band1.gnt_wl ? (B_AX_GNT_WL_RFC_S1_SW_VAL | + B_AX_GNT_WL_BB_S1_SW_VAL) : 0) | + (gnt_cfg->band1.gnt_wl_sw_en ? + (B_AX_GNT_WL_RFC_S1_SW_CTRL | + B_AX_GNT_WL_BB_S1_SW_CTRL) : 0); + ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_1, val); + if (ret) { + PLTFM_MSG_ERR("Write LTE fail!\n"); + return ret; + } + + ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val); + if (ret) { + PLTFM_MSG_ERR("Read LTE fail!\n"); + return ret; + } + val = val & B_AX_WL_RX_CTRL ? B_AX_WL_RX_CTRL : 0 | + ((gnt_cfg->band0.gnt_bt_sw_en || gnt_cfg->band1.gnt_bt_sw_en) ? + (B_AX_GNT_BT_TX_SW_CTRL | B_AX_GNT_BT_RX_SW_CTRL) : 0) | + ((gnt_cfg->band0.gnt_bt || gnt_cfg->band1.gnt_bt) ? + (B_AX_GNT_BT_TX_SW_VAL | B_AX_GNT_BT_RX_SW_VAL) : 0) | + ((gnt_cfg->band0.gnt_wl_sw_en || gnt_cfg->band1.gnt_wl_sw_en) ? + (B_AX_GNT_WL_TX_SW_CTRL | B_AX_GNT_WL_RX_SW_CTRL) : 0) | + ((gnt_cfg->band0.gnt_wl || gnt_cfg->band1.gnt_wl) ? + (B_AX_GNT_WL_TX_SW_VAL | B_AX_GNT_WL_RX_SW_VAL) : 0); + + ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val); + if (ret) { + PLTFM_MSG_ERR("Write LTE fail!\n"); + return ret; + } + + return MACSUCCESS; +} + +u32 mac_cfg_plt(struct mac_ax_adapter *adapter, struct mac_ax_plt *plt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg, ret; + u16 val; + + ret = check_mac_en(adapter, plt->band, MAC_AX_CMAC_SEL); + if (ret) + return ret; + + reg = plt->band == 0 ? R_AX_BT_PLT : R_AX_BT_PLT_C1; + val = (plt->tx & MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | + (plt->tx & MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | + (plt->tx & MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | + (plt->tx & MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | + (plt->rx & MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | + (plt->rx & MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | + (plt->rx & MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | + (plt->rx & MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | + (plt->rx || plt->tx ? B_AX_PLT_EN : 0); + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)reg, + B_AX_TX_PLT_GNT_LTE_RX | + B_AX_TX_PLT_GNT_BT_TX | + B_AX_TX_PLT_GNT_BT_RX | + B_AX_TX_PLT_GNT_WL | + B_AX_RX_PLT_GNT_LTE_RX | + B_AX_RX_PLT_GNT_BT_TX | + B_AX_RX_PLT_GNT_BT_RX | + B_AX_RX_PLT_GNT_WL, + val, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + + return ret; + } +#endif + MAC_REG_W16(reg, val); + + return MACSUCCESS; +} + +u32 mac_read_coex_reg(struct mac_ax_adapter *adapter, + const u32 offset, u32 *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (offset > 0xFF) { + PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n"); + return MACBADDR; + } + + *val = MAC_REG_R32(R_AX_BTC_CFG + offset); + + return MACSUCCESS; +} + +u32 mac_write_coex_reg(struct mac_ax_adapter *adapter, + const u32 offset, const u32 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (offset > 0xFF) { + PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n"); + return MACBADDR; + } + + MAC_REG_W32(R_AX_BTC_CFG + offset, val); + + return MACSUCCESS; +} + +void mac_cfg_sb(struct mac_ax_adapter *adapter, u32 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 fw_sb; + + fw_sb = MAC_REG_R32(R_AX_SCOREBOARD); + fw_sb = GET_FIELD(fw_sb, MAC_AX_SB_FW); + fw_sb = fw_sb & ~MAC_AX_BTGS1_NOTIFY; + if (adapter->sm.pwr == MAC_AX_PWR_OFF || _is_in_lps(adapter)) + fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; + else + fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; + val = GET_FIELD(val, MAC_AX_SB_DRV); + val = B_AX_TOGGLE | + SET_WORD(val, MAC_AX_SB_DRV) | + SET_WORD(fw_sb, MAC_AX_SB_FW); + MAC_REG_W32(R_AX_SCOREBOARD, val); +} + +u32 mac_cfg_ctrl_path(struct mac_ax_adapter *adapter, u32 wl) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3); + + val = wl ? val | BIT(2) : val & ~BIT(2); + MAC_REG_W8(R_AX_SYS_SDIO_CTRL + 3, val); + + return MACSUCCESS; +} + +u32 mac_get_ctrl_path(struct mac_ax_adapter *adapter, u32 *wl) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3); + + *wl = !!(val & BIT(2)); + + return MACSUCCESS; +} + +u32 mac_get_bt_polt_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_bt_polt_cnt *cnt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 offset = cnt->band ? R_AX_BT_PLT_C1 : R_AX_BT_PLT; + u8 val; + + cnt->cnt = MAC_REG_R16(offset + 2); + + val = MAC_REG_R8(offset + 1); + MAC_REG_W8(offset + 1, val | BIT(1)); + + return MACSUCCESS; +} + +u32 mac_write_coex_mask(struct mac_ax_adapter *adapter, + u32 offset, u32 mask, u32 val) +{ + u32 ret; + + if (offset < R_AX_BTC_CFG || offset > R_AX_LTE_RDATA) { + PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n"); + return MACBADDR; + } + + ret = MAC_REG_W_OFLD((u16)offset, mask, val, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s fail\n", __func__); + return ret; + } + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/coex.h b/phl/hal_g6/mac/mac_ax/coex.h new file mode 100644 index 0000000..02cad1b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/coex.h @@ -0,0 +1,282 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_COEX_H_ +#define _MAC_AX_COEX_H_ + +#include "../mac_def.h" + +#define MAC_AX_NOTIFY_TP_MAJOR 0x81 +#define MAC_AX_NOTIFY_PWR_MAJOR 0x80 + +#define MAC_AX_NOTIFY_SH 24 + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_coex_init + * + * @param *adapter + * @param *coex + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_coex_init(struct mac_ax_adapter *adapter, + struct mac_ax_coex *coex); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_cfg_gnt + * + * @param *adapter + * @param *gnt_cfg + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_cfg_gnt(struct mac_ax_adapter *adapter, + struct mac_ax_coex_gnt *gnt_cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_get_gnt + * + * @param *adapter + * @param *gnt_cfg + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_gnt(struct mac_ax_adapter *adapter, + struct mac_ax_coex_gnt *gnt_cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_cfg_plt + * + * @param *adapter + * @param *plt + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_cfg_plt(struct mac_ax_adapter *adapter, struct mac_ax_plt *plt); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_write_coex_reg + * + * @param *adapter + * @param offset + * @param val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_write_coex_reg(struct mac_ax_adapter *adapter, + const u32 offset, const u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_read_coex_reg + * + * @param *adapter + * @param offset + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_read_coex_reg(struct mac_ax_adapter *adapter, + const u32 offset, u32 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_cfg_sb + * + * @param *adapter + * @param val + * @return Please Place Description here. + * @retval void + */ + +void mac_cfg_sb(struct mac_ax_adapter *adapter, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_cfg_ctrl_path + * + * @param *adapter + * @param wl + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_cfg_ctrl_path(struct mac_ax_adapter *adapter, u32 wl); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_get_ctrl_path + * + * @param *adapter + * @param *wl + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_ctrl_path(struct mac_ax_adapter *adapter, u32 *wl); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_get_bt_polt_cnt + * + * @param *adapter + * @param *cnt + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_bt_polt_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_bt_polt_cnt *cnt); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BTCoex + * @{ + */ + +/** + * @brief mac_write_coex_mask + * + * Write coex reg with mask + * + * @param *adapter + * @param offset + * @param mask + * @param val + * @return 0 for success, others are fail + * @retval u32 + */ + +u32 mac_write_coex_mask(struct mac_ax_adapter *adapter, + u32 offset, u32 mask, u32 val); + +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/cpuio.c b/phl/hal_g6/mac/mac_ax/cpuio.c new file mode 100644 index 0000000..7982789 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/cpuio.c @@ -0,0 +1,1042 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "cpuio.h" + +#define MAX_MACID_NUM 256 + +static u32 band_pkt_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info, u8 once); +static u32 hw_link_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info); +static u32 macid_pkt_drop_all(struct mac_ax_adapter *adapter, u8 macid); +static u32 ac_pkt_drop(struct mac_ax_adapter *adapter, u8 macid, + enum pkt_drop_ac ac); +static u32 deq_enq_to_tail(struct mac_ax_adapter *adapter, + struct deq_enq_info *info); +static u32 get_1st_pktid(struct mac_ax_adapter *adapter, + struct first_pid_info *info); +static u32 get_next_pktid(struct mac_ax_adapter *adapter, + struct next_pid_info *info); +static void set_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid); +static void set_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid); +static void rel_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid); +static void rel_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid); +static u32 set_hiq_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info); +static u32 rel_hiq_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info); +static void ss_hw_len_udn_clr(struct mac_ax_adapter *adapter); +static u32 hiq_link_drop(struct mac_ax_adapter *adapter, u8 band); +static u32 mg0_link_drop(struct mac_ax_adapter *adapter, u8 band); + +u32 mac_dle_buf_req_wd(struct mac_ax_adapter *adapter, + struct cpuio_buf_req_t *buf_req_p) +{ + u32 val32, timeout; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = 0; + val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_WD_BUF_REQ_LEN); + val32 |= B_AX_WD_BUF_REQ_EXEC; + MAC_REG_W32(R_AX_WD_BUF_REQ, val32); + + timeout = DLE_BUF_REQ_DLY_CNT; + while (timeout--) { + val32 = MAC_REG_R32(R_AX_WD_BUF_STATUS); + if (val32 & B_AX_WD_BUF_STAT_DONE) + break; + PLTFM_DELAY_US(DLE_BUF_REQ_DLY_US); + } + + if (!++timeout) { + PLTFM_MSG_ERR("[ERR]dle buf req wd %d timeout\n", + buf_req_p->len); + return MACPOLLTO; + } + + buf_req_p->pktid = GET_FIELD(val32, B_AX_WD_BUF_STAT_PKTID); + + if (buf_req_p->pktid == 0xfff) { + PLTFM_MSG_ERR("[ERR]dle buf req wd %d no pktid\n", + buf_req_p->len); + return MACNOBUF; + } + + return MACSUCCESS; +} + +u32 mac_dle_buf_req_pl(struct mac_ax_adapter *adapter, + struct cpuio_buf_req_t *buf_req_p) +{ + u32 val32, timeout; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = 0; + val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_PL_BUF_REQ_LEN); + val32 |= B_AX_PL_BUF_REQ_EXEC; + MAC_REG_W32(R_AX_PL_BUF_REQ, val32); + + timeout = DLE_BUF_REQ_DLY_CNT; + while (timeout--) { + val32 = MAC_REG_R32(R_AX_PL_BUF_STATUS); + if (val32 & B_AX_PL_BUF_STAT_DONE) + break; + PLTFM_DELAY_US(DLE_BUF_REQ_DLY_US); + } + + if (!++timeout) { + PLTFM_MSG_ERR("[ERR]dle buf req pl %d timeout\n", + buf_req_p->len); + return MACPOLLTO; + } + + buf_req_p->pktid = GET_FIELD(val32, B_AX_PL_BUF_STAT_PKTID); + + if (buf_req_p->pktid == 0xfff) { + PLTFM_MSG_ERR("[ERR]dle buf req pl %d no pktid\n", + buf_req_p->len); + return MACNOBUF; + } + + return MACSUCCESS; +} + +u32 mac_set_cpuio_wd(struct mac_ax_adapter *adapter, + struct cpuio_ctrl_t *ctrl_para_p) +{ + u32 val_op0, val_op1, val_op2; + u32 val32, cmd_type, timeout; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cmd_type = ctrl_para_p->cmd_type; + + val_op2 = 0; + val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid, + B_AX_WD_CPUQ_OP_STRT_PKTID); + val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid, + B_AX_WD_CPUQ_OP_END_PKTID); + MAC_REG_W32(R_AX_WD_CPUQ_OP_2, val_op2); + + val_op1 = 0; + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid, + B_AX_WD_CPUQ_OP_SRC_PID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid, + B_AX_WD_CPUQ_OP_SRC_QID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid, + B_AX_WD_CPUQ_OP_DST_PID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid, + B_AX_WD_CPUQ_OP_DST_QID); + MAC_REG_W32(R_AX_WD_CPUQ_OP_1, val_op1); + + val_op0 = 0; + val_op0 = SET_CLR_WORD(val_op0, cmd_type, + B_AX_WD_CPUQ_OP_CMD_TYPE); + val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid, + B_AX_WD_CPUQ_OP_MACID); + val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->pkt_num, + B_AX_WD_CPUQ_OP_PKTNUM); + val_op0 |= B_AX_WD_CPUQ_OP_EXEC; + MAC_REG_W32(R_AX_WD_CPUQ_OP_0, val_op0); + + timeout = SET_CPUIO_DLY_CNT; + do { + val32 = MAC_REG_R32(R_AX_WD_CPUQ_OP_STATUS); + if (val32 & B_AX_WD_CPUQ_OP_STAT_DONE) + break; + PLTFM_DELAY_US(SET_CPUIO_DLY_US); + timeout--; + } while (timeout); + + if (!timeout) { + PLTFM_MSG_ERR("[ERR]set cpuio wd timeout\n"); + PLTFM_MSG_ERR("[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n", + val_op0, val_op1, val_op2); + return MACPOLLTO; + } + + if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || + cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) + ctrl_para_p->pktid = GET_FIELD(val32, B_AX_WD_CPUQ_OP_PKTID); + + return MACSUCCESS; +} + +u32 mac_set_cpuio_pl(struct mac_ax_adapter *adapter, + struct cpuio_ctrl_t *ctrl_para_p) +{ + u32 val_op0, val_op1, val_op2; + u32 val32, cmd_type, timeout; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cmd_type = ctrl_para_p->cmd_type; + + val_op2 = 0; + val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid, + B_AX_PL_CPUQ_OP_STRT_PKTID); + val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid, + B_AX_PL_CPUQ_OP_END_PKTID); + MAC_REG_W32(R_AX_PL_CPUQ_OP_2, val_op2); + + val_op1 = 0; + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid, + B_AX_PL_CPUQ_OP_SRC_PID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid, + B_AX_PL_CPUQ_OP_SRC_QID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid, + B_AX_PL_CPUQ_OP_DST_PID); + val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid, + B_AX_PL_CPUQ_OP_DST_QID); + MAC_REG_W32(R_AX_PL_CPUQ_OP_1, val_op1); + + val_op0 = 0; + val_op0 = SET_CLR_WORD(val_op0, cmd_type, + B_AX_PL_CPUQ_OP_CMD_TYPE); + val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid, + B_AX_PL_CPUQ_OP_MACID); + val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->pkt_num, + B_AX_PL_CPUQ_OP_PKTNUM); + val_op0 |= B_AX_PL_CPUQ_OP_EXEC; + MAC_REG_W32(R_AX_PL_CPUQ_OP_0, val_op0); + + timeout = SET_CPUIO_DLY_CNT; + do { + val32 = MAC_REG_R32(R_AX_PL_CPUQ_OP_STATUS); + if (val32 & B_AX_PL_CPUQ_OP_STAT_DONE) + break; + PLTFM_DELAY_US(SET_CPUIO_DLY_US); + timeout--; + } while (timeout); + + if (!timeout) { + PLTFM_MSG_ERR("[ERR]set cpuio pl timeout\n"); + PLTFM_MSG_ERR("[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n", + val_op0, val_op1, val_op2); + return MACPOLLTO; + } + + if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || + cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) + ctrl_para_p->pktid = GET_FIELD(val32, B_AX_PL_CPUQ_OP_PKTID); + + return MACSUCCESS; +} + +u32 mac_wde_pkt_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info) +{ + u32 ret; + + switch (info->sel) { + case MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE: + ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_BE); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE: + ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_BK); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE: + ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_VI); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE: + ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_VO); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_MACID_ALL: + ret = macid_pkt_drop_all(adapter, info->macid); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_BAND_ONCE: + ret = band_pkt_drop(adapter, info, 1); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_BAND: + ret = band_pkt_drop(adapter, info, 0); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_REL_MACID: + rel_dmac_macid_drop(adapter, info->macid); + rel_cmac_macid_drop(adapter, info->macid); + break; + case MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT: + case MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID: + ret = rel_hiq_drop(adapter, info); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_HIQ_ONCE: + case MAC_AX_PKT_DROP_SEL_MG0_ONCE: + ret = hw_link_drop(adapter, info); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_HIQ_PORT: + case MAC_AX_PKT_DROP_SEL_HIQ_MBSSID: + ret = set_hiq_drop(adapter, info); + if (ret != MACSUCCESS) + return ret; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +static u32 band_pkt_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info, u8 once) +{ + u32 ret; + u32 qid; + u8 band = info->band; + u8 macid_grp_num = MAX_MACID_NUM >> 5; + u32 macid_band_sel[MAX_MACID_NUM >> 5] = {0}; + u32 macid_ctrl_sel[MAX_MACID_NUM >> 5] = {0}; + u32 macid_pause_bak[MAX_MACID_NUM >> 5] = {0}; + u32 macid_sleep_bak[MAX_MACID_NUM >> 5] = {0}; + u8 i_u8; + u16 i_u16; + u8 macid_grp; + u8 macid_sh; + u16 macid_num = adapter->hw_info->macid_num; + u8 dmac_macid_drop = 0; + struct mac_role_tbl *role; + struct deq_enq_info q_info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_sch_tx_en_cfg sch_backup; + struct mac_ax_tb_ppdu_ctrl ac_dis_bak; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info)); + + for (i_u16 = 0; i_u16 < macid_num; i_u16++) { + role = mac_role_srch(adapter, (u8)i_u16); + if (role) { + macid_sh = i_u16 & (32 - 1); + macid_grp = i_u16 >> 5; + if (role->info.band) + macid_band_sel[macid_grp] |= BIT(macid_sh); + else + macid_band_sel[macid_grp] &= ~(BIT(macid_sh)); + } + } + + if (band == MAC_AX_BAND_1) { + for (i_u8 = 0; i_u8 < macid_grp_num; i_u8++) + macid_ctrl_sel[i_u8] = macid_band_sel[i_u8]; + } else { + for (i_u8 = 0; i_u8 < macid_grp_num; i_u8++) + macid_ctrl_sel[i_u8] = ~macid_band_sel[i_u8]; + } + + /* TBD, pause H2C in val, mask format, Soar, 20200109 */ + + macid_sleep_bak[0] = MAC_REG_R32(R_AX_MACID_SLEEP_0); + MAC_REG_W32(R_AX_MACID_SLEEP_0, macid_sleep_bak[0] | macid_ctrl_sel[0]); + macid_pause_bak[0] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, macid_pause_bak[0] | + macid_ctrl_sel[0]); + macid_sleep_bak[1] = MAC_REG_R32(R_AX_MACID_SLEEP_1); + MAC_REG_W32(R_AX_MACID_SLEEP_1, macid_sleep_bak[1] | macid_ctrl_sel[1]); + macid_pause_bak[1] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, macid_pause_bak[1] | + macid_ctrl_sel[1]); + macid_sleep_bak[2] = MAC_REG_R32(R_AX_MACID_SLEEP_2); + MAC_REG_W32(R_AX_MACID_SLEEP_2, macid_sleep_bak[2] | macid_ctrl_sel[2]); + macid_pause_bak[2] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, macid_pause_bak[2] | + macid_ctrl_sel[2]); + macid_sleep_bak[3] = MAC_REG_R32(R_AX_MACID_SLEEP_3); + MAC_REG_W32(R_AX_MACID_SLEEP_3, macid_sleep_bak[3] | macid_ctrl_sel[3]); + macid_pause_bak[3] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, macid_pause_bak[3] | + macid_ctrl_sel[3]); + + sch_backup.band = band; + ret = stop_sch_tx(adapter, SCH_TX_SEL_ALL, &sch_backup); + if (ret != MACSUCCESS) + return ret; + + ac_dis_bak.band = band; + ret = stop_ac_tb_tx(adapter, TB_STOP_SEL_ALL, &ac_dis_bak); + if (ret != MACSUCCESS) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + PLTFM_MSG_TRACE("[TRACE]:do not support DMAC drop\n"); + dmac_macid_drop = 0; + } else { + dmac_macid_drop = 1; + } + } else { + dmac_macid_drop = 1; + } + + if (once == 0 && dmac_macid_drop == 1) { + MAC_REG_W32(R_AX_DMAC_MACID_DROP_0, + MAC_REG_R32(R_AX_DMAC_MACID_DROP_0) | + macid_ctrl_sel[0]); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_1, + MAC_REG_R32(R_AX_DMAC_MACID_DROP_1) | + macid_ctrl_sel[1]); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_2, + MAC_REG_R32(R_AX_DMAC_MACID_DROP_2) | + macid_ctrl_sel[2]); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_3, + MAC_REG_R32(R_AX_DMAC_MACID_DROP_3) | + macid_ctrl_sel[3]); + } + + ret = tx_idle_poll_band(adapter, band, 0); + if (ret != MACSUCCESS) + return ret; + + q_info.dst_pid = WDE_DLE_PID_WDRLS; + q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + q_info.src_pid = + (band == MAC_AX_BAND_1) ? WDE_DLE_PID_C1 : WDE_DLE_PID_C0; + + /* need to modify for 8852C, soar */ + if (band == MAC_AX_BAND_1) { + for (qid = WDE_DLE_QID_BCN_C1; qid <= WDE_DLE_QID_MG2_C1; + qid++) { + if (qid == WDE_DLE_QID_HI_C1) { + ret = hiq_link_drop(adapter, band); + if (ret != MACSUCCESS) + return ret; + } else { + q_info.src_qid = (u8)qid; + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } + } + } else { + for (qid = WDE_DLE_QID_BCN_C0; qid <= WDE_DLE_QID_MG2_C0; + qid++) { + if (qid == WDE_DLE_QID_HI_C0) { + ret = hiq_link_drop(adapter, band); + if (ret != MACSUCCESS) + return ret; + } else { + q_info.src_qid = (u8)qid; + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } + } + } + + for (i_u16 = 0; i_u16 < macid_num; i_u16++) { + macid_grp = i_u16 >> 5; + if (macid_ctrl_sel[macid_grp] & BIT(i_u16 & 31)) { + q_info.macid = (u8)i_u16; + q_info.src_pid = WDE_DLE_PID_C0; + q_info.dst_pid = WDE_DLE_PID_WDRLS; + q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + + for (qid = WDE_DLE_QID_BE; + qid <= WDE_DLE_QID_VO; qid++) { + q_info.src_qid = (u8)qid; + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } + } + } + + PLTFM_DELAY_MS(1); + ss_hw_len_udn_clr(adapter); + + /* TBD, pause H2C in val, mask format, Soar, 20200109 */ + + MAC_REG_W32(R_AX_MACID_SLEEP_0, macid_sleep_bak[0]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, macid_pause_bak[0]); + MAC_REG_W32(R_AX_MACID_SLEEP_1, macid_sleep_bak[1]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, macid_pause_bak[1]); + MAC_REG_W32(R_AX_MACID_SLEEP_2, macid_sleep_bak[2]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, macid_pause_bak[2]); + MAC_REG_W32(R_AX_MACID_SLEEP_3, macid_sleep_bak[3]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, macid_pause_bak[3]); + + ret = resume_sch_tx(adapter, &sch_backup); + if (ret != MACSUCCESS) + return ret; + + ret = set_hw_tb_ppdu_ctrl(adapter, &ac_dis_bak); + if (ret != MACSUCCESS) + return ret; + + return ret; +} + +static u32 hw_link_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info) +{ + u32 ret; + u8 band = info->band; + struct mac_ax_sch_tx_en_cfg sch_backup; + enum ptcl_tx_sel ptcl_sel; + enum sch_tx_sel sch_sel; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + switch (info->sel) { + case MAC_AX_PKT_DROP_SEL_MG0_ONCE: + ptcl_sel = PTCL_TX_SEL_MG0; + sch_sel = SCH_TX_SEL_MG0; + break; + case MAC_AX_PKT_DROP_SEL_HIQ_ONCE: + ptcl_sel = PTCL_TX_SEL_HIQ; + sch_sel = SCH_TX_SEL_HIQ; + break; + default: + return MACNOITEM; + } + + sch_backup.band = band; + ret = stop_sch_tx(adapter, sch_sel, &sch_backup); + if (ret != MACSUCCESS) + return ret; + + ret = tx_idle_poll_sel(adapter, ptcl_sel, band); + if (ret != MACSUCCESS) + return ret; + + switch (info->sel) { + case MAC_AX_PKT_DROP_SEL_MG0_ONCE: + ret = mg0_link_drop(adapter, band); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_PKT_DROP_SEL_HIQ_ONCE: + ret = hiq_link_drop(adapter, band); + if (ret != MACSUCCESS) + return ret; + break; + default: + return MACNOITEM; + } + + ret = resume_sch_tx(adapter, &sch_backup); + if (ret != MACSUCCESS) + return ret; + + return ret; +} + +static u32 macid_pkt_drop_all(struct mac_ax_adapter *adapter, u8 macid) +{ + u32 ret; + u32 qid; + struct deq_enq_info info; + struct macid_tx_bak bak; + struct mac_role_tbl *role; + + PLTFM_MEMSET(&info, 0, sizeof(struct deq_enq_info)); + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("[ERR]:role info is null\n"); + return MACNOITEM; + } + + ret = stop_macid_tx(adapter, role, TB_STOP_SEL_ALL, &bak); + if (ret != MACSUCCESS) + return ret; + + set_dmac_macid_drop(adapter, macid); + set_cmac_macid_drop(adapter, macid); + + ret = tx_idle_poll_macid(adapter, role); + if (ret != MACSUCCESS) + return ret; + + info.macid = macid; + info.src_pid = WDE_DLE_PID_C0; + info.dst_pid = WDE_DLE_PID_WDRLS; + info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + + for (qid = WDE_DLE_QID_BE; qid <= WDE_DLE_QID_VO; qid++) { + info.src_qid = (u8)qid; + ret = deq_enq_all(adapter, &info); + if (ret != MACSUCCESS) + return ret; + } + + ret = resume_macid_tx(adapter, role, &bak); + if (ret != MACSUCCESS) + return ret; + + return ret; +} + +static u32 ac_pkt_drop(struct mac_ax_adapter *adapter, u8 macid, + enum pkt_drop_ac ac) +{ + u32 ret; + struct deq_enq_info info; + struct mac_role_tbl *role; + enum tb_stop_sel stop_sel; + struct macid_tx_bak bak; + + PLTFM_MEMSET(&info, 0, sizeof(struct deq_enq_info)); + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("[ERR]:role info is null\n"); + return MACNOITEM; + } + + switch (ac) { + case PKT_DROP_BE: + stop_sel = TB_STOP_SEL_BE; + break; + case PKT_DROP_BK: + stop_sel = TB_STOP_SEL_BK; + break; + case PKT_DROP_VI: + stop_sel = TB_STOP_SEL_VI; + break; + case PKT_DROP_VO: + stop_sel = TB_STOP_SEL_VO; + break; + default: + return MACNOITEM; + } + + ret = stop_macid_tx(adapter, role, stop_sel, &bak); + if (ret != MACSUCCESS) + return ret; + + ret = tx_idle_poll_macid(adapter, role); + if (ret != MACSUCCESS) + return ret; + + info.macid = macid; + info.src_pid = WDE_DLE_PID_C0; + info.src_qid = ac; + info.dst_pid = WDE_DLE_PID_WDRLS; + info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + + ret = deq_enq_all(adapter, &info); + if (ret != MACSUCCESS) + return ret; + + ret = resume_macid_tx(adapter, role, &bak); + if (ret != MACSUCCESS) + return ret; + + return ret; +} + +static u32 deq_enq_to_tail(struct mac_ax_adapter *adapter, + struct deq_enq_info *info) +{ + struct cpuio_ctrl_t cpuio; + u32 ret; + + PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t)); + + cpuio.cmd_type = CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL; + cpuio.macid = info->macid; + cpuio.pkt_num = 0; + cpuio.src_pid = info->src_pid; + cpuio.src_qid = info->src_qid; + cpuio.dst_pid = info->dst_pid; + cpuio.dst_qid = info->dst_qid; + cpuio.start_pktid = info->pktid; + cpuio.end_pktid = info->pktid; + + ret = mac_set_cpuio_wd(adapter, &cpuio); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +u32 deq_enq_all(struct mac_ax_adapter *adapter, struct deq_enq_info *info) +{ + struct cpuio_ctrl_t cpuio; + struct first_pid_info pktid_info; + u32 ret; + + PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t)); + + pktid_info.macid = info->macid; + pktid_info.src_pid = info->src_pid; + pktid_info.src_qid = info->src_qid; + + ret = get_1st_pktid(adapter, &pktid_info); + if (ret != MACSUCCESS) + return ret; + + if (pktid_info.pktid != 0xFFF) { + cpuio.cmd_type = CPUIO_OP_CMD_DEQ_ENQ_ALL; + cpuio.macid = info->macid; + cpuio.src_pid = info->src_pid; + cpuio.src_qid = info->src_qid; + cpuio.dst_pid = info->dst_pid; + cpuio.dst_qid = info->dst_qid; + + ret = mac_set_cpuio_wd(adapter, &cpuio); + if (ret != MACSUCCESS) + return ret; + } + + return MACSUCCESS; +} + +static u32 get_1st_pktid(struct mac_ax_adapter *adapter, + struct first_pid_info *info) +{ + u32 ret = MACSUCCESS; + struct cpuio_ctrl_t cpuio; + + PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t)); + + cpuio.cmd_type = CPUIO_OP_CMD_GET_1ST_PID; + cpuio.macid = info->macid; + cpuio.src_pid = info->src_pid; + cpuio.src_qid = info->src_qid; + ret = mac_set_cpuio_wd(adapter, &cpuio); + + info->pktid = cpuio.pktid; + + return ret; +} + +static u32 get_next_pktid(struct mac_ax_adapter *adapter, + struct next_pid_info *info) +{ + u32 ret = MACSUCCESS; + struct cpuio_ctrl_t cpuio; + + PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t)); + + cpuio.cmd_type = CPUIO_OP_CMD_GET_NEXT_PID; + cpuio.macid = info->macid; + cpuio.src_pid = info->src_pid; + cpuio.src_qid = info->src_qid; + cpuio.start_pktid = info->start_pktid; + ret = mac_set_cpuio_wd(adapter, &cpuio); + + info->pktid = cpuio.pktid; + + return ret; +} + +static void set_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid) +{ + u32 val32; + u8 macid_sh = macid & (32 - 1); + u8 macid_grp = macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + PLTFM_MSG_TRACE("hw do not support dmac drop!\n"); + return; + } else { + if (MAC_REG_R32(R_AX_SS_DBG_3) & + B_AX_SS_HW_DECR_LEN_UDN) + PLTFM_MSG_WARN("STA len underflow bef drop\n"); + } + } else { + if (MAC_REG_R32(R_AX_SS_DBG_3) & + B_AX_SS_HW_DECR_LEN_UDN) + PLTFM_MSG_WARN("STA len underflow bef drop\n"); + } + + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_0); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_0, val32 | BIT(macid_sh)); + break; + case 1: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_1); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_1, val32 | BIT(macid_sh)); + break; + case 2: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_2); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_2, val32 | BIT(macid_sh)); + break; + case 3: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_3); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_3, val32 | BIT(macid_sh)); + break; + default: + break; + } +} + +static void set_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid) +{ + u32 val32; + u8 macid_sh = macid & (32 - 1); + u8 macid_grp = macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_0); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_0, val32 | BIT(macid_sh)); + break; + case 1: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_1); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_1, val32 | BIT(macid_sh)); + break; + case 2: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_2); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_2, val32 | BIT(macid_sh)); + break; + case 3: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_3); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_3, val32 | BIT(macid_sh)); + break; + default: + break; + } +} + +static void rel_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid) +{ + u32 val32; + u8 macid_sh = macid & (32 - 1); + u8 macid_grp = macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_0); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_0, val32 & ~(BIT(macid_sh))); + break; + case 1: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_1); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_1, val32 & ~(BIT(macid_sh))); + break; + case 2: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_2); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_2, val32 & ~(BIT(macid_sh))); + break; + case 3: + val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_3); + MAC_REG_W32(R_AX_DMAC_MACID_DROP_3, val32 & ~(BIT(macid_sh))); + break; + default: + break; + } + + ss_hw_len_udn_clr(adapter); +} + +static void rel_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid) +{ + u32 val32; + u8 macid_sh = macid & (32 - 1); + u8 macid_grp = macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_0); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_0, val32 & ~(BIT(macid_sh))); + break; + case 1: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_1); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_1, val32 & ~(BIT(macid_sh))); + break; + case 2: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_2); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_2, val32 & ~(BIT(macid_sh))); + break; + case 3: + val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_3); + MAC_REG_W32(R_AX_CMAC_MACID_DROP_3, val32 & ~(BIT(macid_sh))); + break; + default: + break; + } +} + +static u32 set_hiq_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info) +{ + u32 val32; + u32 addr; + u16 mbssid_sh; + u8 port_sh; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + addr = info->band ? R_AX_MBSSID_DROP_0_C1 : R_AX_MBSSID_DROP_0; + mbssid_sh = BIT(0) << info->mbssid; + port_sh = BIT(0) << info->port; + + val32 = MAC_REG_R32(addr); + switch (info->sel) { + case MAC_AX_PKT_DROP_SEL_HIQ_PORT: + val32 |= port_sh << B_AX_PORT_DROP_4_0_SH; + if (info->port == 0) + val32 |= BIT(0); + break; + case MAC_AX_PKT_DROP_SEL_HIQ_MBSSID: + val32 |= mbssid_sh; + break; + default: + return MACNOITEM; + } + MAC_REG_W32(addr, val32); + + return MACSUCCESS; +} + +static u32 rel_hiq_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info) +{ + u32 val32; + u32 addr; + u16 mbssid_sh; + u8 port_sh; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + addr = info->band ? R_AX_MBSSID_DROP_0_C1 : R_AX_MBSSID_DROP_0; + mbssid_sh = BIT(0) << info->mbssid; + port_sh = BIT(0) << info->port; + + val32 = MAC_REG_R32(addr); + switch (info->sel) { + case MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT: + val32 &= ~(port_sh << B_AX_PORT_DROP_4_0_SH); + if (info->port == 0) + val32 &= ~(BIT(0)); + break; + case MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID: + val32 &= ~mbssid_sh; + break; + default: + return MACNOITEM; + } + MAC_REG_W32(addr, val32); + + return MACSUCCESS; +} + +static void ss_hw_len_udn_clr(struct mac_ax_adapter *adapter) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_SS_DBG_3); + if (val32 & B_AX_SS_HW_DECR_LEN_UDN) { + val32 &= ~(B_AX_SS_HW_ADD_LEN_OVF | B_AX_SS_SW_DECR_LEN_UDN | + B_AX_SS_HW_DECR_LEN_UDN | B_AX_SS_ATM_ERR | + B_AX_SS_DEL_STA_ERR | B_AX_SS_ADD_STA_ERR); + MAC_REG_W32(R_AX_SS_DBG_3, val32 | B_AX_SS_HW_DECR_LEN_UDN); + } +} + +static u32 hiq_link_drop(struct mac_ax_adapter *adapter, u8 band) +{ + u32 ret; + u8 mbid, port; + struct deq_enq_info q_info; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info)); + + q_info.dst_pid = WDE_DLE_PID_WDRLS; + q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + if (band == MAC_AX_BAND_1) { + q_info.src_pid = WDE_DLE_PID_C1; + q_info.src_qid = WDE_DLE_QID_HI_C1; + } else { + q_info.src_pid = WDE_DLE_PID_C0; + q_info.src_qid = WDE_DLE_QID_HI_C0; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + for (mbid = 0; mbid < adapter->hw_info->mbssid_num; mbid++) { + q_info.macid = mbid; + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } + for (port = 1; port < adapter->hw_info->port_num; port++) { + q_info.macid = port << WDE_DLE_SUBQID_PORT_SH; + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + } + } else { + return MACNOITEM; + } + + return ret; +} + +static u32 mg0_link_drop(struct mac_ax_adapter *adapter, u8 band) +{ + u32 ret; + struct deq_enq_info q_info; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info)); + + q_info.dst_pid = WDE_DLE_PID_WDRLS; + q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP; + if (band == MAC_AX_BAND_1) { + q_info.src_pid = WDE_DLE_PID_C1; + q_info.src_qid = WDE_DLE_QID_MG0_C1; + } else { + q_info.src_pid = WDE_DLE_PID_C0; + q_info.src_qid = WDE_DLE_QID_MG0_C0; + } + + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) + return ret; + + return ret; +} + diff --git a/phl/hal_g6/mac/mac_ax/cpuio.h b/phl/hal_g6/mac/mac_ax/cpuio.h new file mode 100644 index 0000000..5cab9a4 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/cpuio.h @@ -0,0 +1,719 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_CPUIO_H_ +#define _MAC_AX_CPUIO_H_ + +#include "../type.h" +#include "trxcfg.h" +#include "role.h" +#include "hw.h" + +/*--------------------Define ----------------------------------------*/ +#define WDE_DLE_PID_C0 3 +#define WDE_DLE_PID_C1 4 +#define WDE_DLE_PID_WDRLS 7 +#define WDE_DLE_QID_BE 0 +#define WDE_DLE_QID_BK 1 +#define WDE_DLE_QID_VI 2 +#define WDE_DLE_QID_VO 3 +#define WDE_DLE_QID_WDRLS_DROP 3 +#define WDE_DLE_QID_BCN_C0 0x10 +#define WDE_DLE_QID_HI_C0 0x11 +#define WDE_DLE_QID_MG0_C0 0x12 +#define WDE_DLE_QID_MG1_C0 0x13 +#define WDE_DLE_QID_MG2_C0 0x14 +#define WDE_DLE_QID_BCN_C1 0x18 +#define WDE_DLE_QID_HI_C1 0x19 +#define WDE_DLE_QID_MG0_C1 0x1A +#define WDE_DLE_QID_MG1_C1 0x1B +#define WDE_DLE_QID_MG2_C1 0x1C + +#define WDE_DLE_SUBQID_PORT_SH 4 + +#define WDE_DLE_MAX_PKT_NUM 0xFFFF +#define WDE_DLE_NULL_PKTID 0xFFF + +#define DLE_BUF_REQ_DLY_CNT 2000 +#define DLE_BUF_REQ_DLY_US 1 +#define SET_CPUIO_DLY_CNT 2000 +#define SET_CPUIO_DLY_US 1 + +/*--------------------Define Enum------------------------------------*/ + +/** + * @enum WDE_DLE_PORT_ID + * + * @brief WDE_DLE_PORT_ID + * + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_DISPATCH + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_PKTIN + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CMAC0 + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CMAC1 + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CPU_IO + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_WDRLS + * Please Place Description here. + * @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_END + * Please Place Description here. + */ +enum WDE_DLE_PORT_ID { + WDE_DLE_PORT_ID_DISPATCH = 0, + WDE_DLE_PORT_ID_PKTIN = 1, + WDE_DLE_PORT_ID_CMAC0 = 3, + WDE_DLE_PORT_ID_CMAC1 = 4, + WDE_DLE_PORT_ID_CPU_IO = 6, + WDE_DLE_PORT_ID_WDRLS = 7, + WDE_DLE_PORT_ID_END = 8 +}; + +/** + * @enum PLE_DLE_PORT_ID + * + * @brief PLE_DLE_PORT_ID + * + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_DISPATCH + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_MPDU + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_SEC + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CMAC0 + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CMAC1 + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_WDRLS + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CPU_IO + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_PLRLS + * Please Place Description here. + * @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_END + * Please Place Description here. + */ +enum PLE_DLE_PORT_ID { + PLE_DLE_PORT_ID_DISPATCH = 0, + PLE_DLE_PORT_ID_MPDU = 1, + PLE_DLE_PORT_ID_SEC = 2, + PLE_DLE_PORT_ID_CMAC0 = 3, + PLE_DLE_PORT_ID_CMAC1 = 4, + PLE_DLE_PORT_ID_WDRLS = 5, + PLE_DLE_PORT_ID_CPU_IO = 6, + PLE_DLE_PORT_ID_PLRLS = 7, + PLE_DLE_PORT_ID_END = 8 +}; + +/** + * @enum WDE_DLE_QUEID_PKTIN + * + * @brief WDE_DLE_QUEID_PKTIN + * + * @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC0 + * Please Place Description here. + * @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC1 + * Please Place Description here. + * @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC2 + * Please Place Description here. + * @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC3 + * Please Place Description here. + * @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_MSIC + * Please Place Description here. + */ +enum WDE_DLE_QUEID_PKTIN { + WDE_DLE_QUEID_AC0 = 0x0, + WDE_DLE_QUEID_AC1 = 0x1, + WDE_DLE_QUEID_AC2 = 0x2, + WDE_DLE_QUEID_AC3 = 0x3, + WDE_DLE_QUEID_MSIC = 0x4 +}; + +/** + * @enum WDE_DLE_QUEID_CMAC + * + * @brief WDE_DLE_QUEID_CMAC + * + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_BE + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_BK + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_VI + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_VO + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_BEACON + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_HIGH + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_NORMAL + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_NO_POWER_SAVE + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_FAST_EDCA + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_BEACON + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_HIGH + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_NORMAL + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_NO_POWER_SAVE + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_FAST_EDCA + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_VO + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_VI + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_BE + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_BK + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_VO + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_VI + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_BE + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_BK + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_ULQ + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_TWTQ0 + * Please Place Description here. + * @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_TWTQ1 + * Please Place Description here. + */ +enum WDE_DLE_QUEID_CMAC { + WDE_DLE_QUEID_ACQ_BE = 0, + WDE_DLE_QUEID_ACQ_BK = 1, + WDE_DLE_QUEID_ACQ_VI = 2, + WDE_DLE_QUEID_ACQ_VO = 3, + WDE_DLE_QUEID_B0_BEACON = 0x10, + WDE_DLE_QUEID_B0_HIGH = 0x11, + WDE_DLE_QUEID_B0_MGN_NORMAL = 0x12, + WDE_DLE_QUEID_B0_MGN_NO_POWER_SAVE = 0x13, + WDE_DLE_QUEID_B0_MGN_FAST_EDCA = 0x14, + WDE_DLE_QUEID_B1_BEACON = 0x18, + WDE_DLE_QUEID_B1_HIGH = 0x19, + WDE_DLE_QUEID_B1_MGN_NORMAL = 0x1A, + WDE_DLE_QUEID_B1_MGN_NO_POWER_SAVE = 0x1B, + WDE_DLE_QUEID_B1_MGN_FAST_EDCA = 0x1C, + WDE_DLE_QUEID_WMM0_F2P_VO = 0x20, + WDE_DLE_QUEID_WMM0_F2P_VI = 0x21, + WDE_DLE_QUEID_WMM0_F2P_BE = 0x22, + WDE_DLE_QUEID_WMM0_F2P_BK = 0x23, + WDE_DLE_QUEID_WMM1_F2P_VO = 0x24, + WDE_DLE_QUEID_WMM1_F2P_VI = 0x25, + WDE_DLE_QUEID_WMM1_F2P_BE = 0x26, + WDE_DLE_QUEID_WMM1_F2P_BK = 0x27, + WDE_DLE_QUEID_B0_ULQ = 0x30, + WDE_DLE_QUEID_B0_TWTQ0 = 0x31, + WDE_DLE_QUEID_B0_TWTQ1 = 0x32 +}; + +/** + * @enum WDE_DLE_QUEID_CPUIO + * + * @brief WDE_DLE_QUEID_CPUIO + * + * @var WDE_DLE_QUEID_CPUIO::WDE_DLE_QUEID_CPUIO_0 + * Please Place Description here. + * @var WDE_DLE_QUEID_CPUIO::WDE_DLE_QUEID_CPUIO_1 + * Please Place Description here. + */ +enum WDE_DLE_QUEID_CPUIO { + WDE_DLE_QUEID_CPUIO_0 = 0x0, + WDE_DLE_QUEID_CPUIO_1 = 0x1 +}; + +/** + * @enum PLE_DLE_QUEID_CPUIO + * + * @brief PLE_DLE_QUEID_CPUIO + * + * @var PLE_DLE_QUEID_CPUIO::PLE_DLE_QUEID_CPUIO_0 + * Please Place Description here. + * @var PLE_DLE_QUEID_CPUIO::PLE_DLE_QUEID_CPUIO_1 + * Please Place Description here. + */ +enum PLE_DLE_QUEID_CPUIO { + PLE_DLE_QUEID_CPUIO_0 = 0x0, + PLE_DLE_QUEID_CPUIO_1 = 0x1 +}; + +/** + * @enum WDE_DLE_QUEID_WDRLS + * + * @brief WDE_DLE_QUEID_WDRLS + * + * @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_TXOK + * Please Place Description here. + * @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_RETRY_LIMIT + * Please Place Description here. + * @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_LIFETIME_TO + * Please Place Description here. + * @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_MACID_DROP + * Please Place Description here. + * @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_NO_REPORT + * Please Place Description here. + */ +enum WDE_DLE_QUEID_WDRLS { + WDE_DLE_QUEID_TXOK = 0x0, + WDE_DLE_QUEID_DROP_RETRY_LIMIT = 0x1, + WDE_DLE_QUEID_DROP_LIFETIME_TO = 0x2, + WDE_DLE_QUEID_DROP_MACID_DROP = 0x3, + WDE_DLE_QUEID_NO_REPORT = 0x4 +}; + +/** + * @enum PLE_DLE_QUEID_PLRLS + * + * @brief PLE_DLE_QUEID_PLRLS + * + * @var PLE_DLE_QUEID_PLRLS::PLE_DLE_QUEID_NO_REPORT + * Please Place Description here. + */ +enum PLE_DLE_QUEID_PLRLS { + PLE_DLE_QUEID_NO_REPORT = 0x0 +}; + +/** + * @enum WDE_DLE_QUOTA_ID + * + * @brief WDE_DLE_QUOTA_ID + * + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_HOST_IF + * Please Place Description here. + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_WLAN_CPU + * Please Place Description here. + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_DATA_CPU + * Please Place Description here. + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_PKTIN + * Please Place Description here. + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_CPUIO + * Please Place Description here. + * @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_END + * Please Place Description here. + */ +enum WDE_DLE_QUOTA_ID { + WDE_DLE_QUOTA_ID_HOST_IF = 0, + WDE_DLE_QUOTA_ID_WLAN_CPU = 1, + WDE_DLE_QUOTA_ID_DATA_CPU = 2, + WDE_DLE_QUOTA_ID_PKTIN = 3, + WDE_DLE_QUOTA_ID_CPUIO = 4, + WDE_DLE_QUOTA_ID_END = 5 +}; + +/** + * @enum PLE_DLE_QUOTA_ID + * + * @brief PLE_DLE_QUOTA_ID + * + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_BAND0_TXPL + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_BAND1_TXPL + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_C2H + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_H2C + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_WLAN_CPU + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_MPDU + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC0_RX + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC1_RX + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC1_BBRPT + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_WDRLS_RPT + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CPUIO + * Please Place Description here. + * @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_END + * Please Place Description here. + */ +enum PLE_DLE_QUOTA_ID { + PLE_DLE_QUOTA_ID_BAND0_TXPL = 0, + PLE_DLE_QUOTA_ID_BAND1_TXPL = 1, + PLE_DLE_QUOTA_ID_C2H = 2, + PLE_DLE_QUOTA_ID_H2C = 3, + PLE_DLE_QUOTA_ID_WLAN_CPU = 4, + PLE_DLE_QUOTA_ID_MPDU = 5, + PLE_DLE_QUOTA_ID_CMAC0_RX = 6, + PLE_DLE_QUOTA_ID_CMAC1_RX = 7, + PLE_DLE_QUOTA_ID_CMAC1_BBRPT = 8, + PLE_DLE_QUOTA_ID_WDRLS_RPT = 9, + PLE_DLE_QUOTA_ID_CPUIO = 10, + PLE_DLE_QUOTA_ID_END = 11 +}; + +/** + * @enum CPUIO_CTRL_TYPE + * + * @brief CPUIO_CTRL_TYPE + * + * @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_WD + * Please Place Description here. + * @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_PLD + * Please Place Description here. + * @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_NUM + * Please Place Description here. + */ +enum CPUIO_CTRL_TYPE { + CPUIO_CTRL_TYPE_WD = 0, + CPUIO_CTRL_TYPE_PLD = 1, + CPUIO_CTRL_TYPE_NUM = 2 +}; + +/** + * @enum CPUIO_OP_COMMAND_TYPE + * + * @brief CPUIO_OP_COMMAND_TYPE + * + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_GET_1ST_PID + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_GET_NEXT_PID + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_ENQ_TO_TAIL + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_ENQ_TO_HEAD + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ_ENQ_ALL + * Please Place Description here. + * @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL + * Please Place Description here. + */ +enum CPUIO_OP_COMMAND_TYPE { + CPUIO_OP_CMD_GET_1ST_PID = 0, + CPUIO_OP_CMD_GET_NEXT_PID = 1, + CPUIO_OP_CMD_ENQ_TO_TAIL = 4, + CPUIO_OP_CMD_ENQ_TO_HEAD = 5, + CPUIO_OP_CMD_DEQ = 8, + CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, + CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 +}; + +/** + * @enum pkt_drop_ac + * + * @brief pkt_drop_ac + * + * @var pkt_drop_ac::PKT_DROP_BE + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_BK + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_VI + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_VO + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_AC_LAST + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_AC_MAX + * Please Place Description here. + * @var pkt_drop_ac::PKT_DROP_AC_INVALID + * Please Place Description here. + */ +enum pkt_drop_ac { + PKT_DROP_BE = WDE_DLE_QID_BE, + PKT_DROP_BK = WDE_DLE_QID_BK, + PKT_DROP_VI = WDE_DLE_QID_VI, + PKT_DROP_VO = WDE_DLE_QID_VO, + + /* keep last */ + PKT_DROP_AC_LAST, + PKT_DROP_AC_MAX = PKT_DROP_AC_LAST, + PKT_DROP_AC_INVALID = PKT_DROP_AC_LAST, +}; + +/*--------------------Define MACRO----------------------------------*/ +#define VIRTUAL_ADDRESS_MAPPING(eng_sel, pkt_id, offset) \ + (0x00000000 | (((eng_sel) & 0x1) << 27) | \ + (((pkt_id) & 0xFFF) << 15) | ((offset) & 0xEFFF)) + +#define GET_VIRTUAL_ADDRESS_WD(pkt_id, offset)\ + ((((pkt_id) & 0xFFF) << 15) | ((offset) & 0xEFFF)) + +/*--------------------Define Struct----------------------------------*/ + +/** + * @struct cpuio_buf_req_t + * @brief cpuio_buf_req_t + * + * @var cpuio_buf_req_t::len + * Please Place Description here. + * @var cpuio_buf_req_t::pktid + * Please Place Description here. + */ +struct cpuio_buf_req_t { + // input + u16 len; + // output + u16 pktid; +}; + +/** + * @struct cpuio_ctrl_t + * @brief cpuio_ctrl_t + * + * @var cpuio_ctrl_t::pkt_num + * Please Place Description here. + * @var cpuio_ctrl_t::start_pktid + * Please Place Description here. + * @var cpuio_ctrl_t::end_pktid + * Please Place Description here. + * @var cpuio_ctrl_t::cmd_type + * Please Place Description here. + * @var cpuio_ctrl_t::macid + * Please Place Description here. + * @var cpuio_ctrl_t::src_pid + * Please Place Description here. + * @var cpuio_ctrl_t::src_qid + * Please Place Description here. + * @var cpuio_ctrl_t::dst_pid + * Please Place Description here. + * @var cpuio_ctrl_t::dst_qid + * Please Place Description here. + * @var cpuio_ctrl_t::pktid + * Please Place Description here. + */ +struct cpuio_ctrl_t { + // input + u16 pkt_num; + u16 start_pktid; + u16 end_pktid; + u8 cmd_type; + u8 macid; + u8 src_pid; + u8 src_qid; + u8 dst_pid; + u8 dst_qid; + // output + u16 pktid; +}; + +/** + * @struct deq_enq_info + * @brief deq_enq_info + * + * @var deq_enq_info::macid + * Please Place Description here. + * @var deq_enq_info::src_pid + * Please Place Description here. + * @var deq_enq_info::src_qid + * Please Place Description here. + * @var deq_enq_info::dst_pid + * Please Place Description here. + * @var deq_enq_info::dst_qid + * Please Place Description here. + * @var deq_enq_info::pktid + * Please Place Description here. + */ +struct deq_enq_info { + u8 macid; + u8 src_pid; + u8 src_qid; + u8 dst_pid; + u8 dst_qid; + u16 pktid; +}; + +/** + * @struct first_pid_info + * @brief first_pid_info + * + * @var first_pid_info::macid + * Please Place Description here. + * @var first_pid_info::src_pid + * Please Place Description here. + * @var first_pid_info::src_qid + * Please Place Description here. + * @var first_pid_info::pktid + * Please Place Description here. + */ +struct first_pid_info { + u8 macid; + u8 src_pid; + u8 src_qid; + u16 pktid; +}; + +/** + * @struct next_pid_info + * @brief next_pid_info + * + * @var next_pid_info::macid + * Please Place Description here. + * @var next_pid_info::src_pid + * Please Place Description here. + * @var next_pid_info::src_qid + * Please Place Description here. + * @var next_pid_info::start_pktid + * Please Place Description here. + * @var next_pid_info::pktid + * Please Place Description here. + */ +struct next_pid_info { + u8 macid; + u8 src_pid; + u8 src_qid; + u16 start_pktid; + u16 pktid; +}; + +/*--------------------Export global variable----------------------------*/ + +/*--------------------Function declaration-----------------------------*/ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief deq_enq_all + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 deq_enq_all(struct mac_ax_adapter *adapter, struct deq_enq_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief mac_dle_buf_req_wd + * + * @param *adapter + * @param *buf_req_p + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dle_buf_req_wd(struct mac_ax_adapter *adapter, + struct cpuio_buf_req_t *buf_req_p); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief mac_dle_buf_req_pl + * + * @param *adapter + * @param *buf_req_p + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dle_buf_req_pl(struct mac_ax_adapter *adapter, + struct cpuio_buf_req_t *buf_req_p); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief mac_set_cpuio_wd + * + * @param *adapter + * @param *ctrl_para_p + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_cpuio_wd(struct mac_ax_adapter *adapter, + struct cpuio_ctrl_t *ctrl_para_p); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief mac_set_cpuio_pl + * + * @param *adapter + * @param *ctrl_para_p + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_cpuio_pl(struct mac_ax_adapter *adapter, + struct cpuio_ctrl_t *ctrl_para_p); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup CPU_IO + * @{ + */ + +/** + * @brief mac_wde_pkt_drop + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_wde_pkt_drop(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/dbcc.c b/phl/hal_g6/mac/mac_ax/dbcc.c new file mode 100644 index 0000000..861040d --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbcc.c @@ -0,0 +1,233 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "dbcc.h" +#include "cpuio.h" + +static u32 band1_enable(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info) +{ + u32 ret; + u32 sleep_bak[4] = {0}; + u32 pause_bak[4] = {0}; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_sch_tx_en_cfg txen_bak; + + txen_bak.band = 0; + ret = stop_sch_tx(adapter, SCH_TX_SEL_ALL, &txen_bak); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]stop sch tx %d\n", ret); + return ret; + } + + sleep_bak[0] = MAC_REG_R32(R_AX_MACID_SLEEP_0); + sleep_bak[1] = MAC_REG_R32(R_AX_MACID_SLEEP_1); + sleep_bak[2] = MAC_REG_R32(R_AX_MACID_SLEEP_2); + sleep_bak[3] = MAC_REG_R32(R_AX_MACID_SLEEP_3); + pause_bak[0] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0); + pause_bak[1] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1); + pause_bak[2] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2); + pause_bak[3] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3); + + MAC_REG_W32(R_AX_MACID_SLEEP_0, 0xFFFFFFFF); + MAC_REG_W32(R_AX_MACID_SLEEP_1, 0xFFFFFFFF); + MAC_REG_W32(R_AX_MACID_SLEEP_2, 0xFFFFFFFF); + MAC_REG_W32(R_AX_MACID_SLEEP_3, 0xFFFFFFFF); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, 0xFFFFFFFF); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, 0xFFFFFFFF); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, 0xFFFFFFFF); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, 0xFFFFFFFF); + + ret = tx_idle_poll_band(adapter, 0, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]tx idle poll %d\n", ret); + return ret; + } + + ret = dle_quota_change(adapter, info->qta_mode); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]DLE quota change %d\n", ret); + return ret; + } + + MAC_REG_W32(R_AX_MACID_SLEEP_0, sleep_bak[0]); + MAC_REG_W32(R_AX_MACID_SLEEP_1, sleep_bak[1]); + MAC_REG_W32(R_AX_MACID_SLEEP_2, sleep_bak[2]); + MAC_REG_W32(R_AX_MACID_SLEEP_3, sleep_bak[3]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, pause_bak[0]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, pause_bak[1]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, pause_bak[2]); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, pause_bak[3]); + + ret = resume_sch_tx(adapter, &txen_bak); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d resume sch tx %d\n", + txen_bak.band, ret); + return ret; + } + + ret = cmac_func_en(adapter, MAC_AX_BAND_1, MAC_AX_FUNC_EN); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d func en %d\n", MAC_AX_BAND_1, ret); + return ret; + } + + ret = cmac_init(adapter, info, MAC_AX_BAND_1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d init %d\n", MAC_AX_BAND_1, ret); + return ret; + } + + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) | + (B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1)); + + adapter->sm.bb1_func = MAC_AX_FUNC_ON; + + ret = mac_enable_imr(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] enable CMAC1 IMR %d\n", ret); + return ret; + } + + return MACSUCCESS; +} + +static u32 band1_disable(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info) +{ + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_pkt_drop_info drop_info; + + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) & + ~B_AX_R_SYM_FEN_WLBBFUN_1); + + drop_info.band = MAC_AX_BAND_1; + drop_info.sel = MAC_AX_PKT_DROP_SEL_BAND; + ret = adapter->ops->pkt_drop(adapter, &drop_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d pkt drop %d\n", drop_info.band, ret); + return ret; + } + + ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]Remove Address CAM %d\n", ret); + return ret; + } + + ret = cmac_func_en(adapter, MAC_AX_BAND_1, MAC_AX_FUNC_DIS); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d func dis %d\n", MAC_AX_BAND_1, ret); + return ret; + } + + ret = dle_quota_change(adapter, info->qta_mode); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]DLE quota change %d\n", ret); + return ret; + } + + return 0; +} + +u32 mac_dbcc_enable(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info, u8 dbcc_en) +{ + u32 ret; + + if (dbcc_en) { + ret = band1_enable(adapter, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] band1_enable %d\n", ret); + return ret; + } + ret = mac_notify_fw_dbcc(adapter, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: [ERR] notfify dbcc fail %d\n", + __func__, ret); + return ret; + } + } else { + ret = mac_notify_fw_dbcc(adapter, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: [ERR] notfify dbcc fail %d\n", + __func__, ret); + return ret; + } + ret = band1_disable(adapter, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] band1_disable %d\n", ret); + return ret; + } + } + + return MACSUCCESS; +} + +u32 mac_dbcc_move_macid(struct mac_ax_adapter *adapter, u8 macid, u8 dbcc_en) +{ + struct mac_role_tbl *role; + struct deq_enq_info q_info; + u32 ret; + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("dbcc%d move macid%d srch role fail\n", + dbcc_en, macid); + return MACNOITEM; + } + + if (dbcc_en) { + ret = mac_ss_wmm_sta_move(adapter, + (enum mac_ax_ss_wmm)role->wmm, + MAC_AX_SS_WMM_TBL_C1_WMM0); + } else { + ret = mac_ss_wmm_sta_move(adapter, + (enum mac_ax_ss_wmm)role->wmm, + MAC_AX_SS_WMM_TBL_C0_WMM0); + } + + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("dbcc%d move macid%d wmm%d move %d\n", + dbcc_en, macid, role->wmm, ret); + return ret; + } + + PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info)); + + if (dbcc_en) { + q_info.src_pid = WDE_DLE_PID_C0; + q_info.src_qid = WDE_DLE_QID_MG0_C0; + q_info.dst_pid = WDE_DLE_PID_C1; + q_info.dst_qid = WDE_DLE_QID_MG0_C1; + } else { + q_info.src_pid = WDE_DLE_PID_C1; + q_info.src_qid = WDE_DLE_QID_MG0_C1; + q_info.dst_pid = WDE_DLE_PID_C0; + q_info.dst_qid = WDE_DLE_QID_MG0_C0; + } + + ret = deq_enq_all(adapter, &q_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("dbcc%d move mgq %d\n", dbcc_en, ret); + return ret; + } + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/dbcc.h b/phl/hal_g6/mac/mac_ax/dbcc.h new file mode 100644 index 0000000..658a433 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbcc.h @@ -0,0 +1,53 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_DBCC_H_ +#define _MAC_AX_DBCC_H_ + +#include "../type.h" +#include "trxcfg.h" +#include "sta_sch.h" + +/*--------------------Define -------------------------------------------*/ +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +/*--------------------Define Struct-------------------------------------*/ +/*--------------------Function Prototype--------------------------------*/ + +/** + * @brief mac_dbcc_enable + * + * @param *adapter + * @param *info + * @param dbcc_en + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dbcc_enable(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info, u8 dbcc_en); + +/** + * @brief mac_dbcc_move_macid + * + * @param *adapter + * @param macid + * @param dbcc_en + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dbcc_move_macid(struct mac_ax_adapter *adapter, u8 macid, u8 dbcc_en); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/dbg_cmd.c b/phl/hal_g6/mac/mac_ax/dbg_cmd.c new file mode 100644 index 0000000..23bd604 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbg_cmd.c @@ -0,0 +1,1676 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "dbg_cmd.h" + +const char *MallocIDName[eMallocMAX] = { + "OS", + "Common", + "Task", + "AXIDMA", + "SPIC", + "Timer", + "UART", + "H2C", + "C2H", + "DBG", + "Role", + "PS", + "WoWLAN", + "Sec", + "Ofld", + "TX", + "RX", + "Report", + "PHYDM", + "RF", + "BTCoex", + "SCSI", + "Free" +}; + +const char *MallocTypeName[eMallocTypeMAX] = { + "N/A", + "Fixed", + "Dynamic" +}; + +const char *ISRName[ISRStatistic_MAX] = { + /* First layer */ + // WDTISRROM8852A + "WDT", + // CMACISRROM8852A + "CMAC0", + "CMAC1", + "CMAC2", + "CMAC3", + "CMAC4", + "CMAC5", + "CMAC6", + "CMAC7", + "CMAC8", + "CMAC9", + "CMAC10", + // DMACISRROM8852A + "DMAC0", + "DMAC1", + "DMAC2", + // SysISRROM8852A + "SYS0", + // DataHDLISRROM8852A + "IPSec", + "AXIDMA", + "IDDMA", + // PlatISRROM8852A + "MACErr", + "UART", + "RXI300", + /* Second layer */ + "DMAC0_GT0", + "DMAC0_GT1", + "DMAC0_GT2_3", + "DMAC0_H2C", + "SYS0_HALT_H2C", + "SYS0_GPIO", + "MACErr_DMAC", + "MACErr_CMAC0", + "MACErr_CMAC1" +}; + +// gerrit test 5 +static const struct mac_hal_cmd_info mac_hal_cmd_i[] = { + {"-h", MAC_HAL_HELP, cmd_mac_help}, + {"dd_dbg", MAC_MAC_DD_DBG, cmd_mac_dbg_dump},/*@do not move this element to other position*/ + {"reg_dump", MAC_MAC_REG_DUMP, cmd_mac_reg_dump}, + {"fw_dbg", MAC_MAC_FW_DBG, cmd_mac_fw_dump}, + {"help", MAC_HAL_HELP, cmd_mac_help}, + {"fw_log", MAC_MAC_FW_LOG, cmd_mac_fw_log_cfg}, + {"fw_curtcb", MAC_MAC_FW_CURTCB, cmd_mac_fw_curtcb}, + {"fw_info", MAC_MAC_FW_INFO, cmd_mac_fw_status_parser}, + {"dl_sym", MAC_MAC_DL_SYM, cmd_mac_dl_sym} + /*@do not move this element to other position*/ +}; + +static const struct mac_hal_cmd_info mac_fw_status_cmd_i[] = { + {"task", FW_STATUS_TASKINFO}, + {"flash", FW_STATUS_FLASHINFO}, + {"heap", FW_STATUS_HEAPINFO}, + {"mem_fast", FW_STATUS_MEMINFO_FAST}, + {"mem_slow", FW_STATUS_MEMINFO_SLOW}, + {"ps", FW_STATUS_PSINFO}, + {"h2c_c2h", FW_STATUS_H2C_C2HINFO}, + {"isr", FW_STATUS_ISRINFO} +}; + +static const char * const type_names[] = { + "level", + "output", + "comp", + "comp_ext", + NULL +}; + +static struct fw_status_proc_class fw_status_proc_sys[] = { + {FW_STATUS_TASKINFO, fw_status_taskinfo_handler}, + {FW_STATUS_FLASHINFO, fw_status_flashinfo_handler}, + {FW_STATUS_HEAPINFO, fw_status_heapinfo_handler}, + {FW_STATUS_MEMINFO_FAST, fw_status_meminfo_fast_handler}, + {FW_STATUS_MEMINFO_SLOW, fw_status_meminfo_slow_handler}, + {FW_STATUS_PSINFO, fw_status_psinfo_handler}, + {FW_STATUS_H2C_C2HINFO, fw_status_h2c_c2hinfo_handler}, + {FW_STATUS_ISRINFO, fw_status_isrinfo_handler}, + {FW_STATUS_CHSW_TIMING, fw_status_chsw_handler}, + {FW_STATUS_MAX, NULL}, +}; + +u32 cmd_mac_help(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + u32 hal_cmd_ary_size = sizeof(mac_hal_cmd_i) / sizeof(struct mac_hal_cmd_info); + u32 i; + + //PLTFM_MSG_TRACE("HAL cmd ==>\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "HAL cmd ==>\n"); + for (i = 0; i < hal_cmd_ary_size - 1; i++) { + //PLTFM_MSG_TRACE(" %-5d: %s\n", + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, " %-5d: %s\n", + i, mac_hal_cmd_i[i + 1].name); + } + return MACSUCCESS; +} + +u32 cmd_mac_dbg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + //struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = adapter; + //struct mac_ax_ops *ops = mac->ops; + struct mac_ax_dbgpkg ss_dbg = {0}; + struct mac_ax_dbgpkg_en dbg_msk = {0}; + + ss_dbg.ss_dbg_0 = 0; + ss_dbg.ss_dbg_1 = 0; + dbg_msk.ss_dbg = 1; + dbg_msk.dle_dbg = 1; + dbg_msk.dmac_dbg = 1; + dbg_msk.cmac_dbg = 1; + dbg_msk.mac_dbg_port = 1; + + mac_dbg_status_dump(mac, &ss_dbg, &dbg_msk); + + //PLTFM_MSG_TRACE("rtw_hal_mac_dbg_dump(): ss_dbg.ss_dbg_0 = 0x%08X, + // ss_dbg.ss_dbg_1 = 0x%08X\n", + // ss_dbg.ss_dbg_0, ss_dbg.ss_dbg_1); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "rtw_hal_mac_dbg_dump(): ss_dbg.ss_dbg_0 = 0x%08X,ss_dbg.ss_dbg_1 = 0x%08X\n", + ss_dbg.ss_dbg_0, ss_dbg.ss_dbg_1); + + return MACSUCCESS; +} + +u32 cmd_mac_reg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + u32 ret = MACSUCCESS, val = 0; + + // input argument start from input[1], input[0] is mac_hal_cmd_info.name + if (input_num < 2) { + //PLTFM_MSG_TRACE("invalid argument\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "invalid argument\n"); + return MACFWSTATUSFAIL; + } + //PLTFM_SSCANF(input[1], "%d", &val); + val = PLTFM_STRTOUL(input[1], 10); + + //PLTFM_MSG_TRACE("%s: sel:%d\n", __func__, val); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s: sel:%d\n", __func__, val); + ret = mac_reg_dump(adapter, (enum mac_ax_reg_sel)val); + return ret; +} + +void cmd_mac_get_version(struct mac_ax_adapter *adapter, char *ver_str, u16 len) +{ + PLTFM_SNPRINTF(ver_str, len, "V%u.%u.%u.%u", + MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER, + MAC_AX_SUB_VER, MAC_AX_SUB_INDEX); +} + +void cmd_mac_get_fw_ver(struct mac_ax_adapter *adapter, char *ver_str, u16 len) +{ + PLTFM_SNPRINTF(ver_str, len, "V%u.%u.%u.%u", + adapter->fw_info.major_ver, adapter->fw_info.minor_ver, + adapter->fw_info.sub_ver, adapter->fw_info.sub_idx); +} + +u32 cmd_mac_fw_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + //struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 i; + char mac_ver[20], fw_ver[20]; + + cmd_mac_get_version(adapter, mac_ver, sizeof(mac_ver)); + //PLTFM_MSG_TRACE("HALMAC version %s\n", mac_ver); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "HALMAC version %s\n", mac_ver); + + cmd_mac_get_fw_ver(adapter, fw_ver, sizeof(fw_ver)); + //PLTFM_MSG_TRACE("FW version %s\n", fw_ver); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "FW version %s\n", fw_ver); + + /* dump dbg reg */ + //PLTFM_MSG_TRACE("0x01f4[31:0] = 0x%08x\n", MAC_REG_R32(0x01f4)); + //PLTFM_MSG_TRACE("0x01fc[31:0] = 0x%08x\n", MAC_REG_R32(0x01fc)); + //PLTFM_MSG_TRACE("0x8424[31:0] = 0x%08x\n", MAC_REG_R32(0x8424)); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "0x01f4[31:0] = 0x%08x\n", MAC_REG_R32(0x01f4)); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "0x01fc[31:0] = 0x%08x\n", MAC_REG_R32(0x01fc)); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "0x8424[31:0] = 0x%08x\n", MAC_REG_R32(0x8424)); + + /* dump fw pc */ + MAC_REG_W32(0x58, 0xf200f2); + MAC_REG_W8(0xf6, 0x1); + for (i = 0; i < 15; i++) { + //PLTFM_MSG_TRACE("0x00c0[31:0] = 0x%08x\n", MAC_REG_R32(0xc0)); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "0x00c0[31:0] = 0x%08x\n", MAC_REG_R32(0xc0)); + PLTFM_DELAY_MS(1); + } + return MACSUCCESS; +} + +static void cmd_mac_fw_log_set(struct mac_ax_fw_log *fl_cfg, u8 type, u32 value) +{ + switch (type) { + case FWDGB_CFG_TYPE_LEVEL: + fl_cfg->level = value; + break; + + case FWDGB_CFG_TYPE_OUTPUT: + fl_cfg->output |= value; + break; + + case FWDGB_CFG_TYPE_COMP: + fl_cfg->comp |= value; + break; + + case FWDGB_CFG_TYPE_COMP_EXT: + fl_cfg->comp_ext |= value; + break; + + default: + break; + } +} + +static void cmd_mac_fw_log_clr(struct mac_ax_fw_log *fl_cfg, u8 type, u32 value) +{ + switch (type) { + case FWDGB_CFG_TYPE_LEVEL: + break; + case FWDGB_CFG_TYPE_OUTPUT: + fl_cfg->output &= (~value); + break; + case FWDGB_CFG_TYPE_COMP: + fl_cfg->comp &= (~value); + break; + case FWDGB_CFG_TYPE_COMP_EXT: + fl_cfg->comp_ext &= (~value); + break; + default: + break; + } +} + +u32 cmd_mac_fw_log_cfg_set(struct mac_ax_adapter *adapter, + struct mac_ax_fw_log *log_cfg, char *output, u32 out_len, u32 *used) +{ + //struct hal_info_t *hal = hal_com->hal_priv; + struct mac_ax_adapter *mac = adapter; + //struct mac_ax_fw_log log_cfg = {0}; + u32 status; + + if (!mac) + return MACFWSTATUSFAIL; + + //log_cfg.level = fl_cfg->level; + //log_cfg.output = fl_cfg->output; + //log_cfg.comp = fl_cfg->comp; + //log_cfg.comp_ext = fl_cfg->comp_ext; + /* + *PLTFM_MSG_TRACE("Configuring firmware log level %d, output 0x%08x, " + * "comp 0x%08x, comp ext 0x%08x.\n", + * log_cfg->level, + * log_cfg->output, + * log_cfg->comp, + * log_cfg->comp_ext); + */ + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Config firmware log level %d,output 0x%08x,comp 0x%08x,comp ext 0x%08x.\n", + log_cfg->level, + log_cfg->output, + log_cfg->comp, + log_cfg->comp_ext); + if (log_cfg->output & MAC_AX_FL_LV_UART) { + //PLTFM_MSG_TRACE("%s: Enabling UART...\n", __func__); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s: Enabling UART...\n", __func__); + mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_TX_GPIO5); + mac->ops->sel_uart_tx_pin(mac, MAC_AX_UART_TX_GPIO5); + mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_RX_GPIO6); + mac->ops->sel_uart_rx_pin(mac, MAC_AX_UART_RX_GPIO6); + } + + status = mac->ops->fw_log_cfg(mac, log_cfg); + if (status != MACSUCCESS) { + //PLTFM_MSG_TRACE("%s fault, status = %d.\n", __func__, status); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s fault, status = %d.\n", __func__, status); + //return status; + } + return status; +} + +u32 cmd_mac_fw_log_cfg(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + //struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)adapter->drv_adapter; + //struct rtw_hal_fw_log_cfg *fl_cfg = &hal_com->fw_log_cfg; + /* TYPE VALUE(HEX) 1(SET)|2(CLEAR) */ + struct mac_ax_fw_log *plog_cfg = &adapter->log_cfg; + u8 type = 0; + u32 op = FWDGB_CFG_OP_INFO, value = 0; + + if (input_num == 4) { + //PLTFM_MSG_TRACE("%s,%s,%s\n", input[1], input[2], input[3]); + while (type_names[type]) { + if (PLTFM_STRCMP(input[1], type_names[type]) == 0) + break; + type++; + } + if (!type_names[type]) { + //PLTFM_MSG_TRACE("Invalid type \"%s\"\n", input[1]); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Invalid type \"%s\"\n", input[1]); + return MACFWSTATUSFAIL; + } + //PLTFM_SSCANF(input[2], "%x", &value); + value = PLTFM_STRTOUL(input[2], 16); + //PLTFM_SSCANF(input[3], "%d", &op); + op = PLTFM_STRTOUL(input[3], 10); + //PLTFM_MSG_TRACE("value = 0x%x, op = %d\n", value, op); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "value = 0x%x, op = %d\n", value, op); + if (op == 1) + op = FWDGB_CFG_OP_SET; + else if (op == 2) + op = FWDGB_CFG_OP_CLR; + else + op = FWDGB_CFG_OP_INFO; + } else { + //PLTFM_MSG_TRACE("invalid argument\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "invalid argument\n"); + return MACFWSTATUSFAIL; + } + + switch (op) { + case FWDGB_CFG_OP_SET: + cmd_mac_fw_log_set(plog_cfg, type, value); + break; + case FWDGB_CFG_OP_CLR: + cmd_mac_fw_log_clr(plog_cfg, type, value); + break; + case FWDGB_CFG_OP_INFO: + //default: + //_hal_fw_log_info(&log_cfg); + //PLTFM_MSG_TRACE("fw_log invalid op\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "fw_log invalid op\n"); + return MACFWSTATUSFAIL; + } + + return cmd_mac_fw_log_cfg_set(adapter, plog_cfg, output, out_len, used); +} + +u32 cmd_mac_fw_curtcb(struct mac_ax_adapter *adapter, + char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 curtcb, index, val32; + char task_name[FW_MAX_TASK_NAME_LEN]; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, FW_CURTCB_8852A); + } else { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Doesn't support this chip now!\n"); + return MACSUCCESS; + } + curtcb = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY); + + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, (curtcb & 0x1fffffff)); + + val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + + FW_CURTCB_SP_START_OFFSET); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "[FW]Start of the stack = 0x%08x\n", val32); + + for (index = 0; index < 16 ; index = index + 4) { + val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + + FW_CURTCB_TASK_NAME_OFFSET + index); + PLTFM_MEMCPY((u8 *)&task_name[index], (u8 *)&val32, 4); + } + + task_name[FW_MAX_TASK_NAME_LEN - 1] = '\0'; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "[FW]Current task name = %s\n", task_name); + return MACSUCCESS; +} + +u32 cmd_mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num, char *output, u32 out_len, u32 *used) +{ + u32 i, cmd_strlen; + char *fw_status_cmd; + u16 id = FWSTATUS_OPCODE_MASK; + struct mac_ax_fwstatus_payload data; + u32 hal_cmd_ary_size = sizeof(mac_fw_status_cmd_i) / sizeof(struct mac_hal_cmd_info); + + if (input_num < 2) { + //PLTFM_MSG_TRACE("fw status invalid op code\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "fw status invalid op code\n"); + return MACFWSTATUSFAIL; + } + /* Parsing Cmd ID */ + fw_status_cmd = input[1]; + cmd_strlen = PLTFM_STRLEN(fw_status_cmd); + for (i = 0; i < cmd_strlen; i++) { + if (*fw_status_cmd == '\n') + *fw_status_cmd = '\0'; + fw_status_cmd++; + } + for (i = 0; i < hal_cmd_ary_size; i++) { + //PLTFM_MSG_TRACE("[FW STATUS]input string : [%s], input_num = %d\n", + // input[1], input_num); + //PLTFM_MSG_TRACE("mac_fw_status_cmd_i[i].name : [%s]",mac_fw_status_cmd_i[i].name); + //MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + // "[FW STATUS]input string : [%s], input_num = %d\n", + // input[1], input_num); + //MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + // "mac_fw_status_cmd_i[i].name : [%s]", mac_fw_status_cmd_i[i].name); + if (PLTFM_STRCMP(mac_fw_status_cmd_i[i].name, input[1]) == 0) { + id = mac_fw_status_cmd_i[i].id; + //PLTFM_MSG_TRACE("enter fw status dbg %s\n", mac_fw_status_cmd_i[i].name); + //MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + // "enter fw status dbg %s\n", mac_fw_status_cmd_i[i].name); + break; + } + } + if (i == hal_cmd_ary_size) { + //PLTFM_MSG_TRACE("FW STATUS command not found!\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "FW STATUS command not found!\n"); + return MACFWSTATUSFAIL; + } + // gen h2c + data.dword0 = (u32)id; + data.dword1 = FWSTATUS_OPCODE_MASK; + + if (mac_fw_status_cmd(adapter, &data)) { + //PLTFM_MSG_TRACE("FW STATUS H2C Fail!\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "FW STATUS H2C Fail!\n"); + return MACFWSTATUSFAIL; + } + return MACSUCCESS; +} + +u32 cmd_mac_dl_sym(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num, char *output, u32 out_len, u32 *used) +{ +#if MAC_AX_FEATURE_DBGDEC + u32 val, ret; + struct mac_ax_adapter *mac = adapter; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 *symbol_ptr = NULL; + u32 file_size = 0; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "down symbol.bin\n"); + // input argument start from input[1], input[0] is mac_hal_cmd_info.name + if (input_num < 2) { + //PLTFM_MSG_TRACE("invalid argument\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "invalid argument\n"); + return MACFWSTATUSFAIL; + } + //PLTFM_SSCANF(input[1], "%d", &val); + val = PLTFM_STRTOUL(input[1], 10); + + if (val == 1) { + // download file + // PLTFM_DL file, assign symbol_ptr and file_size + switch (hw_info->chip_id) { +#if MAC_AX_8852A_SUPPORT + case MAC_AX_CHIP_ID_8852A: + ret = PLTFM_LD_FW_SYMBOL("hal8852a_msg_symbol.bin", &symbol_ptr, + &file_size); + break; +#endif +#if MAC_AX_8852B_SUPPORT + case MAC_AX_CHIP_ID_8852B: + ret = PLTFM_LD_FW_SYMBOL("hal8852b_msg_symbol.bin", &symbol_ptr, + &file_size); + break; +#endif +#if MAC_AX_8852C_SUPPORT + case MAC_AX_CHIP_ID_8852C: + ret = PLTFM_LD_FW_SYMBOL("hal8852c_msg_symbol.bin", &symbol_ptr, + &file_size); + break; +#endif + default: + return MACFWSTATUSFAIL; + break; + } + + if (ret != MACSUCCESS) { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "reading fw failed !!!\n"); + return MACFWSTATUSFAIL; + } + + ret = mac->ops->fw_log_set_array(adapter, (void *)symbol_ptr, file_size); + if (ret != MACSUCCESS) { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "load symbol failed\n"); + return MACFWSTATUSFAIL; + } + } else if (val == 0) { + //release file + ret = mac->ops->fw_log_unset_array(adapter); + if (ret != MACSUCCESS) + return MACFWSTATUSFAIL; + } + return MACSUCCESS; +#endif +} + +s32 mac_halmac_cmd(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len) +{ + char *token; + u32 argc = 0; + char argv[MAC_MAX_ARGC][MAC_MAX_ARGV]; + + if (output) { + adapter->fw_dbgcmd.buf = output; + adapter->fw_dbgcmd.out_len = out_len; + adapter->fw_dbgcmd.used = 0; + } else { + PLTFM_MSG_TRACE("%s invalid argument\n", __func__); + return MACFWSTATUSFAIL; + } + do { + token = PLTFM_STRSEP(&input, ", "); + if (token) { + if (PLTFM_STRLEN(token) <= MAC_MAX_ARGV) + PLTFM_STRCPY(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < MAC_MAX_ARGC); + + mac_halmac_cmd_parser(adapter, argv, argc, output, out_len); + + return MACSUCCESS; +} + +void mac_halmac_cmd_parser(struct mac_ax_adapter *adapter, + char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len) +{ + u32 hal_cmd_ary_size = sizeof(mac_hal_cmd_i) / sizeof(struct mac_hal_cmd_info); + u32 i = 0; + u32 *used; + + if (output) { + adapter->fw_dbgcmd.buf = output; + adapter->fw_dbgcmd.out_len = out_len; + adapter->fw_dbgcmd.used = 0; + } else { + PLTFM_MSG_TRACE("%s invalid argument\n", __func__); + return; + } + + used = &adapter->fw_dbgcmd.used; + //struct mac_ax_fwstatus_payload data; + + if (hal_cmd_ary_size == 0) + return; + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < hal_cmd_ary_size; i++) { + //PLTFM_MSG_TRACE("input string : %s\n, input_num = %d", + // input[0], input_num); + if (PLTFM_STRCMP(mac_hal_cmd_i[i].name, input[0]) == 0) { + //PLTFM_MSG_TRACE("enter hal dbg %s\n", mac_hal_cmd_i[i].name); + //MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + //"enter hal dbg %s\n", mac_hal_cmd_i[i].name); + if (mac_hal_cmd_i[i].handler(adapter, input, input_num, + output, out_len, used)) { + //PLTFM_MSG_TRACE("%s command process error\n", + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + mac_hal_cmd_i[i].name); + } + PLTFM_DELAY_MS(200); + break; + } + } + if (i == hal_cmd_ary_size) { + //PLTFM_MSG_TRACE("HAL command not found!\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "HAL command not found!\n"); + return; + } + } + PLTFM_MSG_TRACE("-----------------------%s function return\n", __func__); +} + +u32 c2h_fw_status(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + //struct c2h_proc_func *proc = c2h_proc_sys_palt_autotest; + //u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + // struct rtw_c2h_info *info) = NULL; + u32 hdr0, ret = MACSUCCESS; + u32 func, pkt_cnt, i; + u8 *content; + struct fw_status_pkt pkt_info; + struct fw_status_proc_class *proc = fw_status_proc_sys; + + PLTFM_MSG_TRACE("[--------------------]%s\n", __func__); + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + //set info + info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT); + info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS); + info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC); + //info->done_ack = 0; + //info->rec_ack = 0; + info->content = buf + FWCMD_HDR_LEN; + //info->h2c_return = info->c2h_data[1]; + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + if (func == FWCMD_C2H_FUNC_FW_STATUS) { + pkt_cnt = le32_to_cpu(*((u32 *)info->content)); + //PLTFM_MSG_TRACE("[------------------pkt_cnt--] %d\n", pkt_cnt); + content = info->content + LEN_PKTCNT; + for (i = 0; i < pkt_cnt; i++) { + proc = fw_status_proc_sys; + pkt_info.op_code = le32_to_cpu(*((u32 *)(content))); + //PLTFM_MSG_TRACE("[------------------op_code--] %d\n", pkt_info.op_code); + content += LEN_OPCODE; + pkt_info.length = le32_to_cpu(*((u32 *)(content))); + //PLTFM_MSG_TRACE("[------------------length--] %d\n", pkt_info.length); + content += LEN_LENGTH; + pkt_info.data = content; + content += pkt_info.length; + for (; proc->id != FW_STATUS_MAX; proc++) { + if (GET_FIELD_OPCODE(pkt_info.op_code) == proc->id) { + ret = proc->handler(adapter, pkt_info.data, + pkt_info.length); + } + } + } + } + return ret; +} + +u32 fw_status_taskinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + u32 ret = MACSUCCESS; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "-------------------------------------------\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s\n", (const char *)buf); + + //PLTFM_MSG_TRACE("Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\n"); + //PLTFM_MSG_TRACE("-------------------------------------------\n"); + //PLTFM_MSG_TRACE("%s", (const char *)buf); + return ret; +} + +u32 fw_status_flashinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + struct flash_info flashinfo; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + //PLTFM_MSG_TRACE("[--------------------]%s\n", __func__); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "[--------------------]%s\n", __func__); + PLTFM_MEMCPY(&flashinfo, buf, sizeof(struct flash_info)); + //PLTFM_MSG_TRACE("b1InitDone : %d\n", flashinfo.b1initdone); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "b1InitDone : %d\n", flashinfo.b1initdone); + //PLTFM_MSG_TRACE("u1FlashType : %d\n", flashinfo.u1flashtype); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "u1FlashType : %d\n", flashinfo.u1flashtype); + //PLTFM_MSG_TRACE("u4FlashSize : %d\n", flashinfo.u4flashsize); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "u4FlashSize : %d\n", flashinfo.u4flashsize); + + return MACSUCCESS; +} + +u32 fw_status_heapinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + u32 ret = MACSUCCESS; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Index\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "-------------------------------------------\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s", (const char *)buf); + return ret; +} + +u32 fw_status_meminfo_fast_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + struct mem_info *mem_info; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + mem_info = (struct mem_info *)buf; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Fast Heap:\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Owner ID\tType\t\tTotalSize(B)\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "------------------------------------------------\n"); + + while (mem_info->total_size != 0) { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "%s\t\t%s\t\t%u\r\n", + MallocIDName[mem_info->owner_id], + MallocTypeName[mem_info->owner_type], + mem_info->total_size); + mem_info++; + } + return MACSUCCESS; +} + +u32 fw_status_meminfo_slow_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + struct mem_info *mem_info; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + mem_info = (struct mem_info *)buf; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Slow Heap:\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "Owner ID\tType\t\tTotalSize(B)\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "------------------------------------------------\n"); + + while (mem_info->total_size != 0) { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "%s\t\t%s\t\t%u\r\n", + MallocIDName[mem_info->owner_id], + MallocTypeName[mem_info->owner_type], + mem_info->total_size); + mem_info++; + } + return MACSUCCESS; +} + +u32 fw_status_psinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + + // Not support now + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "[Err]\n"); + return MACFWSTATUSFAIL; +} + +u32 fw_status_h2c_c2hinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + + // Not support now + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "[Err]\n"); + return MACFWSTATUSFAIL; +} + +u32 fw_status_isrinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + struct isr_info *isr_info; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + u32 i; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + isr_info = (struct isr_info *)buf; + + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "ISR Name\tCount\t\tExec Time(historical high)\n"); + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "------------------------------------------------\n"); + + for (i = ISRStatistic_WDT; i < ISRStatistic_MAX; i++) { + if (i >= ISRStatistic_DMAC0_GT0) { + if (i == ISRStatistic_DMAC0_GT0) { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "------------------------------------------------\n"); + } + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s\t%u\t\t%u_%u\n", ISRName[i], + isr_info->ISRCnt[i], isr_info->ISRExecTimeMax_hi[i], + isr_info->ISRExecTimeMax_lo[i]); + } else { + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "%s\t\t%u\t\t%u_%u\n", ISRName[i], + isr_info->ISRCnt[i], isr_info->ISRExecTimeMax_hi[i], + isr_info->ISRExecTimeMax_lo[i]); + } + } + return MACSUCCESS; +} + +u32 fw_status_chsw_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len) +{ + struct chswofld_timing_info *timing; + char *output = adapter->fw_dbgcmd.buf; + u32 *used = &adapter->fw_dbgcmd.used; + u32 out_len = adapter->fw_dbgcmd.out_len; + u32 remain_len = out_len - *used; + + if (len > remain_len) + return MACFWSTATUSFAIL; + + timing = (struct chswofld_timing_info *)buf; + MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, + "total: %d (mac: %d, bb: %d, rf: %d, rf reld: %d)\n", + timing->total, timing->mac, timing->bb, timing->rf, timing->rf_reld); + return MACSUCCESS; +} + +#if MAC_AX_FEATURE_DBGDEC +static void fw_log_private_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msgno, + u8 para_num, u8 isint, char *str_buf) +{ + // check data integrity + switch (para_num) { + case 1: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf)); + break; + case 2: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1))); + break; + case 3: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2))); + break; + case 4: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3))); + break; + case 5: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4))); + break; + case 6: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5))); + break; + case 7: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6))); + break; + case 8: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7))); + break; + case 9: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8))); + break; + case 10: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9))); + break; + case 11: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10))); + break; + case 12: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11))); + break; + case 13: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12))); + break; + case 14: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13))); + break; + case 15: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13)), + le32_to_cpu(*(u32 *)(buf + 14))); + break; + case 16: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)", + msgno, + isint, + para_num, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13)), + le32_to_cpu(*(u32 *)(buf + 14)), + le32_to_cpu(*(u32 *)(buf + 15))); + break; + default: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d)", + msgno, + isint, + para_num); + break; + } + PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf); + //PLTFM_FREE(str_buf, H2C_LONG_DATA_LEN); + //return; +} + +static void fw_log_int_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msg_array_idx, + u8 para_num, char *str_buf) +{ + // check data integrity + switch (para_num) { + case 1: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf)); + break; + case 2: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1))); + + break; + case 3: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2))); + break; + case 4: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3))); + break; + case 5: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4))); + break; + case 6: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5))); + break; + case 7: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6))); + break; + case 8: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7))); + break; + case 9: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8))); + break; + case 10: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9))); + break; + case 11: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10))); + break; + case 12: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11))); + break; + case 13: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12))); + break; + case 14: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13))); + break; + case 15: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13)), + le32_to_cpu(*(u32 *)(buf + 14))); + break; + case 16: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + le32_to_cpu(*(u32 *)buf), + le32_to_cpu(*(u32 *)(buf + 1)), + le32_to_cpu(*(u32 *)(buf + 2)), + le32_to_cpu(*(u32 *)(buf + 3)), + le32_to_cpu(*(u32 *)(buf + 4)), + le32_to_cpu(*(u32 *)(buf + 5)), + le32_to_cpu(*(u32 *)(buf + 6)), + le32_to_cpu(*(u32 *)(buf + 7)), + le32_to_cpu(*(u32 *)(buf + 8)), + le32_to_cpu(*(u32 *)(buf + 9)), + le32_to_cpu(*(u32 *)(buf + 10)), + le32_to_cpu(*(u32 *)(buf + 11)), + le32_to_cpu(*(u32 *)(buf + 12)), + le32_to_cpu(*(u32 *)(buf + 13)), + le32_to_cpu(*(u32 *)(buf + 14)), + le32_to_cpu(*(u32 *)(buf + 15))); + break; + default: + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg); + break; + } + PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf); + //return; +} + +u32 fw_log_scan_array(struct mac_ax_adapter *adapter, u32 msgno) +{ + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u32 i = 0, msg_last, array_size; + + if (adapter->fw_log_array_dl_size) { + array_size = adapter->fw_log_array_dl_size / sizeof(struct mac_fw_msg); + for (i = 0; i < array_size ; i++) { + if (adapter->fw_log_array[i].msgno == msgno) + return i; + } + return 0; + } else { + switch (hw_info->chip_id) { +#if MAC_AX_8852A_SUPPORT + case MAC_AX_CHIP_ID_8852A: + msg_last = MSG_8852A_LAST; + break; +#endif +#if MAC_AX_8852B_SUPPORT + case MAC_AX_CHIP_ID_8852B: + msg_last = MSG_8852B_LAST; + break; +#endif +#if MAC_AX_8852C_SUPPORT + case MAC_AX_CHIP_ID_8852C: + msg_last = MSG_8852C_LAST; + break; +#endif + default: + PLTFM_MSG_WARN("array not exist\n"); + return 0; + } + if (msgno >= msg_last) + return 0; + + while (adapter->fw_log_array[i].msgno != msg_last) { + if (adapter->fw_log_array[i].msgno == msgno) + return i; + i++; + } + return 0; + } +} + +void fw_log_set_array(struct mac_ax_adapter *adapter) +{ + struct mac_ax_hw_info *hw_info = adapter->hw_info; + + switch (hw_info->chip_id) { +#if MAC_AX_8852A_SUPPORT + case MAC_AX_CHIP_ID_8852A: + adapter->fw_log_array = fw_log_8852a; + break; +#endif +#if MAC_AX_8852B_SUPPORT + case MAC_AX_CHIP_ID_8852B: + adapter->fw_log_array = fw_log_8852b; + break; +#endif +#if MAC_AX_8852C_SUPPORT + case MAC_AX_CHIP_ID_8852C: + adapter->fw_log_array = fw_log_8852c; + break; +#endif + default: + return; + } +} + +void fw_log_dump(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u8 syntax_3, isint, fileno; + u32 msgno_0, msgno_1, msgno_2, msgno_3; + u16 lineno_0, lineno_1; + u8 para_num, paranum_idx, color; + u32 msgno, msg_array_idx; + u16 lineno; + u8 *para; + char str_buf[STR_BUF_SIZE]; + + if (!adapter->fw_log_array) + fw_log_set_array(adapter); + if (!adapter->fw_log_array) { + PLTFM_MSG_ERR("[ERR]unsupported fw_log_array\n"); + return; + } + color = (*(buf + FWCMD_HDR_LEN + 2)) >> 1; + isint = (color & BIT1) >> 1; + paranum_idx = color & BIT0; + syntax_3 = *(buf + FWCMD_HDR_LEN + 3); + msgno_0 = (u32)*(buf + FWCMD_HDR_LEN + 4); + msgno_1 = (u32)*(buf + FWCMD_HDR_LEN + 5); + msgno_2 = (u32)*(buf + FWCMD_HDR_LEN + 6); + msgno_3 = (u32)*(buf + FWCMD_HDR_LEN + 7); + msgno = (msgno_0 & 0x000000ff) | + ((msgno_1 & 0x000000ff) << 8) | + ((msgno_2 & 0x000000ff) << 16) | + ((msgno_3 & 0x000000ff) << 24); + + fileno = *(buf + FWCMD_HDR_LEN + 8); + lineno_0 = (u16)*(buf + FWCMD_HDR_LEN + 9); + lineno_1 = (u16)*(buf + FWCMD_HDR_LEN + 10); + lineno = (lineno_0 & 0x00ff) | ((lineno_1 & 0x00ff) << 8); + if (paranum_idx) { + para_num = *(buf + FWCMD_HDR_LEN + 11); + para = (buf + FWCMD_HDR_LEN + 12); + } else { + para_num = 0; + para = NULL; + } + PLTFM_MEMSET(str_buf, 0, STR_BUF_SIZE); + #if 0 + str_buf = (char *)PLTFM_MALLOC(H2C_LONG_DATA_LEN); + if (!str_buf) { + PLTFM_MSG_WARN("fw_log_int_dump str_buf 0\n"); + return; + } + #endif + msg_array_idx = fw_log_scan_array(adapter, msgno); + //PLTFM_MSG_WARN("%s, msgno = %d, idx = %d, isint = %d, para_num = %d\n", + //__FUNCTION__, msgno, msg_array_idx, isint, para_num); + if (isint == 0 && para_num != 0 && msg_array_idx != 0) { + if (buf[len - 1] != '\0') + buf[len - 1] = '\0'; + + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + adapter->fw_log_array[msg_array_idx].msg, + (char *)(buf + FWCMD_HDR_LEN + 12)); + PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf); + } else if (msg_array_idx != 0 && isint == 1) { + fw_log_int_dump(adapter, (u32 *)para, msg_array_idx, para_num, str_buf); + } else { + // print specific message and msgno, parameters + if (isint == 1) { + fw_log_private_dump(adapter, (u32 *)para, msgno, para_num, isint, str_buf); + } else if (para_num != 0) { + PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE, + "fw_enc(%d,%d,%d,%s)", + msgno, + isint, + para_num, + (char *)(buf + FWCMD_HDR_LEN + 12)); + PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf); + } + } + //return; +} + +u8 *fw_log_skip_trailing_zero(u8 *s_ptr, u8 *end_ptr) +{ + u8 charac; + + while (s_ptr < end_ptr) { + charac = *(s_ptr); + if (charac != 0x00) + break; + s_ptr++; + } + return s_ptr; +} + +u32 fw_log_check_integrity(u8 *symbol_tab, u8 *end_ptr) +{ + u8 charac, i = 0; + u8 reserved[] = {'R', 'E', 'S', 'E', 'R', 'V', 'E', 'D', '\0'}; + + charac = *symbol_tab; + while (charac != 0x00) { + if (charac != reserved[i]) + return MACFWLOGINTERR;// return fail + i++; + if ((symbol_tab + i) >= end_ptr) + return MACFWLOGINTERR;// return fail + charac = *(symbol_tab + i); + } + return MACSUCCESS; +} + +u32 fw_log_create_array(struct mac_ax_adapter *adapter, struct mac_fw_msg *array_ptr, + u8 *symbol_tab, u8 *end_ptr, u32 enum_count, u8 *enum_list) +{ + u32 i; + u8 charac; + + for (i = 0; i < enum_count; i++) { + array_ptr[i].msgno = le32_to_cpu(*(u32 *)enum_list); + enum_list += 4; + // walk through symbol table + array_ptr[i].msg = (char *)symbol_tab; + //PLTFM_MSG_WARN("[test str] %s\n", (char *)symbol_tab); + //point to next msg + while (symbol_tab < end_ptr) { + charac = *(symbol_tab); + if (charac == 0x00) + break; + symbol_tab++; + } + symbol_tab = fw_log_skip_trailing_zero(symbol_tab, end_ptr); + if (symbol_tab > end_ptr) + return MACFWLOGINTERR; + } + return MACSUCCESS; +} + +u32 mac_fw_log_set_array(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size) +{ + u8 *sym_hdr, *enum_list, *symbol_tab, *end_ptr; + u32 enum_count, alignment_size, ret; + struct mac_fw_msg *new_fw_log_array = NULL; + + sym_hdr = (u8 *)symbol_ptr; + enum_list = (u8 *)(sym_hdr + 8); + alignment_size = le32_to_cpu(*(u32 *)sym_hdr); + enum_count = le32_to_cpu(*(u32 *)(sym_hdr + 4)); + symbol_tab = (u8 *)(enum_list + 4 * enum_count); + end_ptr = sym_hdr + file_size; + //PLTFM_MSG_WARN("alignment_size = %d, enum_count = %d\n", alignment_size, enum_count); + // alignment + symbol_tab = fw_log_skip_trailing_zero(symbol_tab, end_ptr); + + // check integrity + ret = fw_log_check_integrity(symbol_tab, end_ptr); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]check symbol integrity\n"); + return MACFWLOGINTERR;// return fail + } + + //create array + new_fw_log_array = (struct mac_fw_msg *)PLTFM_MALLOC(enum_count * + sizeof(struct mac_fw_msg)); + if (!new_fw_log_array) { + PLTFM_MSG_ERR("[ERR]malloc new_fw_log_array\n"); + return MACBUFALLOC; + } + + //PLTFM_MSG_WARN("addr of array = 0x%llx\n", (u64)new_fw_log_array); + ret = fw_log_create_array(adapter, new_fw_log_array, symbol_tab, end_ptr, enum_count, + enum_list); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("unexpected symbol\n"); + PLTFM_FREE((void *)new_fw_log_array, enum_count * sizeof(struct mac_fw_msg)); + return MACFWLOGINTERR;// return fail + } + + //PLTFM_FREE((void *)new_fw_log_array, enum_count * sizeof(struct mac_fw_msg)); + adapter->fw_log_array = new_fw_log_array; + adapter->fw_log_array_dl = new_fw_log_array; + adapter->fw_log_array_dl_size = enum_count * sizeof(struct mac_fw_msg); + return MACSUCCESS; +} + +u32 mac_fw_log_unset_array(struct mac_ax_adapter *adapter) +{ + if (adapter->fw_log_array_dl) { + PLTFM_FREE(adapter->fw_log_array_dl, adapter->fw_log_array_dl_size); + adapter->fw_log_array = NULL; + adapter->fw_log_array_dl = NULL; + adapter->fw_log_array_dl_size = 0; + } + fw_log_set_array(adapter); + return MACSUCCESS; +} + +#endif + diff --git a/phl/hal_g6/mac/mac_ax/dbg_cmd.h b/phl/hal_g6/mac/mac_ax/dbg_cmd.h new file mode 100644 index 0000000..a4171a4 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbg_cmd.h @@ -0,0 +1,723 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + + #ifndef _MAC_AX_DBG_CMD_H_ +#define _MAC_AX_DBG_CMD_H_ + +#include "../type.h" +#include "../mac_def.h" +#include "../mac_ax.h" +#include "tblupd.h" +#if MAC_AX_8852A_SUPPORT +#include "../fw_ax/rtl8852a/hal8852a_fw_log.h" +#endif +#if MAC_AX_8852B_SUPPORT +#include "../fw_ax/rtl8852b/hal8852b_fw_log.h" +#endif +#if MAC_AX_8852C_SUPPORT +#include "../fw_ax/rtl8852c/hal8852c_fw_log.h" +#endif + +#define FWDGB_CFG_OP_SET 0 +#define FWDGB_CFG_OP_CLR 1 +#define FWDGB_CFG_OP_INFO 2 + +#define FWDGB_CFG_TYPE_LEVEL 0 +#define FWDGB_CFG_TYPE_OUTPUT 1 +#define FWDGB_CFG_TYPE_COMP 2 +#define FWDGB_CFG_TYPE_COMP_EXT 3 + +#define LEN_PKT_HDR 8 +#define LEN_PKTCNT 4 +#define LEN_OPCODE 4 +#define LEN_LENGTH 4 +#define FWSTATUS_OPCODE_MASK 0xFFFF + +#define FW_CURTCB_8852A 0x18e0f5fc +#define FW_CURTCB_SP_START_OFFSET 0x30 +#define FW_CURTCB_TASK_NAME_OFFSET 0x34 +#define FW_MAX_TASK_NAME_LEN 16 + +#define eMallocMAX 23 +#define eMallocTypeMAX 3 + +//STR_BUF_SIZE , -128 for driver stack size warning +#define STR_BUF_SIZE (1024 - 128) + +#define GET_FIELD_OPCODE(opcode) ((opcode) & (FWSTATUS_OPCODE_MASK)) +#define MAC_DBG_MSG(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += PLTFM_SNPRINTF(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) + +/** + * @enum mac_hal_cmd_id + * + * @brief mac_hal_cmd_id + * + * @var mac_hal_cmd_id::MAC_HAL_HELP + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_DD_DBG + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_REG_DUMP + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_FW_DBG + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_FW_LOG + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_FW_CURTCB + * Please Place Description here. + * @var mac_hal_cmd_id::MAC_MAC_FW_INFO + * Please Place Description here. + */ +enum mac_hal_cmd_id { + MAC_HAL_HELP = 0, + MAC_MAC_DD_DBG, + MAC_MAC_REG_DUMP, + MAC_MAC_FW_DBG, + MAC_MAC_FW_LOG, + MAC_MAC_FW_CURTCB, + MAC_MAC_FW_INFO, + MAC_MAC_DL_SYM, +}; + +/** + * @enum mac_ax_fw_status + * + * @brief mac_ax_fw_status + * + * @var mac_ax_fw_status::FW_STATUS_TASKINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_FLASHINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_HEAPINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_MEMINFO_FAST + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_MEMINFO_SLOW + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_PSINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_H2C_C2HINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_ISRINFO + * Please Place Description here. + * @var mac_ax_fw_status::FW_STATUS_MAX + * Please Place Description here. + */ +enum mac_ax_fw_status { + FW_STATUS_TASKINFO, + FW_STATUS_FLASHINFO, + FW_STATUS_HEAPINFO, + FW_STATUS_MEMINFO_FAST, + FW_STATUS_MEMINFO_SLOW, + FW_STATUS_PSINFO, + FW_STATUS_H2C_C2HINFO, + FW_STATUS_ISRINFO, + FW_STATUS_DBGINFO_REG, + FW_STATUS_SERINFO, + FW_STATUS_CHSW_TIMING, + FW_STATUS_MAX +}; + +/** + * @enum ISRStatistic + * + * @brief ISRStatistic + * + * @var ISRStatistic::ISRStatistic_WDT + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC0 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC1 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC2 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC3 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC4 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC5 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC6 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC7 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC8 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC9 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_CMAC10 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC0 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC1 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC2 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_SYS0 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_IPSec + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_AXIDMA + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_IDDMA + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_MACErr + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_UART + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_RXI300 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC0_GT0 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC0_GT1 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC0_GT2_3 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_DMAC0_H2C + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_SYS0_HALT_H2C + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_SYS0_GPIO + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_MACErr_DMAC + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_MACErr_CMAC0 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_MACErr_CMAC1 + * Please Place Description here. + * @var ISRStatistic::ISRStatistic_MAX + * Please Place Description here. + */ +enum ISRStatistic { + /* Fisrt layer */ + // WDTISRROM8852A + ISRStatistic_WDT = 0, // no use currently + // CMACISRROM8852A + ISRStatistic_CMAC0 = 1, + ISRStatistic_CMAC1 = 2, + ISRStatistic_CMAC2 = 3, + ISRStatistic_CMAC3 = 4, + ISRStatistic_CMAC4 = 5, + ISRStatistic_CMAC5 = 6, + ISRStatistic_CMAC6 = 7, + ISRStatistic_CMAC7 = 8, + ISRStatistic_CMAC8 = 9, + ISRStatistic_CMAC9 = 10, + ISRStatistic_CMAC10 = 11, + // DMACISRROM8852A + ISRStatistic_DMAC0 = 12, + ISRStatistic_DMAC1 = 13, + ISRStatistic_DMAC2 = 14, + // SysISRROM8852A + ISRStatistic_SYS0 = 15, + // DataHDLISRROM8852A + ISRStatistic_IPSec = 16, + ISRStatistic_AXIDMA = 17, + ISRStatistic_IDDMA = 18, + // PlatISRROM8852A + ISRStatistic_MACErr = 19, + ISRStatistic_UART = 20, + ISRStatistic_RXI300 = 21, + // Second layer + ISRStatistic_DMAC0_GT0 = 22, + ISRStatistic_DMAC0_GT1 = 23, + ISRStatistic_DMAC0_GT2_3 = 24, + ISRStatistic_DMAC0_H2C = 25, + ISRStatistic_SYS0_HALT_H2C = 26, + ISRStatistic_SYS0_GPIO = 27, + ISRStatistic_MACErr_DMAC = 28, + ISRStatistic_MACErr_CMAC0 = 29, + ISRStatistic_MACErr_CMAC1 = 30, + ISRStatistic_MAX = 31 +}; + +/** + * @struct mac_hal_cmd_info + * @brief mac_hal_cmd_info + * + * @var mac_hal_cmd_info::name + * Please Place Description here. + * @var mac_hal_cmd_info::id + * Please Place Description here. + */ +struct mac_hal_cmd_info { + char name[16]; + u16 id; + u32 (*handler)(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num, char *output, u32 out_len, u32 *used); +}; + +/** + * @struct fw_status_pkt + * @brief fw_status_pkt + * + * @var fw_status_pkt::op_code + * Please Place Description here. + * @var fw_status_pkt::length + * Please Place Description here. + * @var fw_status_pkt::data + * Please Place Description here. + */ +struct fw_status_pkt { + u32 op_code; + u32 length; + u8 *data; +}; + +/** + * @struct flash_info + * @brief flash_info + * + * @var flash_info::b1initdone + * Please Place Description here. + * @var flash_info::b7rsvd + * Please Place Description here. + * @var flash_info::pid + * Please Place Description here. + */ +struct flash_info { + u8 b1initdone: 1; + u8 b7rsvd: 7; + u8 pid[3]; + u8 u1flashtype; + u8 u1dienum; + u8 dieindex; + u8 pageindex; + u8 bsupportps; //PS is Page Switch. Page size is 16MB for 3-Bytes address mode. + u8 u1addressmode; + u8 u1dieunitsize; // unit is "Byte" + u8 rsvd1; + u32 u4dieunitnum; // unit number of die + u32 u4flashsize; // flash total size = u4DieUnitNum * DieNum * FlashUnit. +}; + +/** + * @struct mem_info + * @brief mem_info + * + * @var mem_info::owner_id + * Please Place Description here. + * @var mem_info::owner_type + * Please Place Description here. + * @var mem_info::total_size + * Please Place Description here. + */ +struct mem_info { + u8 owner_id; + u8 owner_type; + u16 total_size; +}; + +/** + * @struct isr_info + * @brief isr_info + * + * @var isr_info::ISRCnt + * Please Place Description here. + * @var isr_info::ISRExecTimeMax_hi + * Please Place Description here. + * @var isr_info::ISRExecTimeMax_lo + * Please Place Description here. + */ +struct isr_info { + u32 ISRCnt[ISRStatistic_MAX]; + u32 ISRExecTimeMax_hi[ISRStatistic_MAX]; + u32 ISRExecTimeMax_lo[ISRStatistic_MAX]; +}; + +/** + * @struct chswofld_timing_info + * @brief chswofld_timing_info + * + * @var chswofld_timing_info::mac + * Please Place Description here. + * @var chswofld_timing_info::bb + * Please Place Description here. + * @var chswofld_timing_info::rf + * Please Place Description here. + * @var chswofld_timing_info::rfReload + * Please Place Description here. + * @var chswofld_timing_info::total + * Please Place Description here. + + */ +struct chswofld_timing_info { + u32 mac; + u32 bb; + u32 rf; + u32 rf_reld; + u32 total; +}; + +/** + * @struct fw_status_proc_class + * @brief fw_status_proc_class + * + * @var flash_info::b1initdone + * Please Place Description here. + * @var flash_info::b7rsvd + * Please Place Description here. + * @var flash_info::pid + * Please Place Description here. + */ +struct halcmd_proc_class { + u16 id; + u32 (*handler)(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV]); +}; + +/** + * @brief mac_fw_status_parser + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +void mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num); + +/** + * @brief mac_halmac_cmd + * + * @param *adapter + * @param *input + * @param *output + * @param *out_len + * @return Please Place Description here. + * @retval s32 + */ +s32 mac_halmac_cmd(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len); + +/** + * @brief mac_halmac_cmd_parser + * + * @param *adapter + * @param *input + * @param *input_num + * @param *output + * @param *out_len + * @return Please Place Description here. + * @retval void + */ +void mac_halmac_cmd_parser(struct mac_ax_adapter *adapter, + char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len); + +/** + * @brief c2h_fw_status + * + * @param *adapter + * @param *buf + * @param *len + * @param *info + * @return Please Place Description here. + * @retval void + */ +u32 c2h_fw_status(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); + +/** + * @brief fw_status_taskinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_taskinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_flashinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_flashinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_heapinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_heapinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_meminfo_fast_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_meminfo_fast_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_meminfo_slow_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_meminfo_slow_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_psinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_psinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_h2c_c2hinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_h2c_c2hinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_isrinfo_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_isrinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief fw_status_chsw_handler + * + * @param *adapter + * @param *buf + * @param *len + * @return Please Place Description here. + * @retval void + */ +u32 fw_status_chsw_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len); + +/** + * @brief cmd_mac_help + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_help(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used); + +/** + * @brief cmd_mac_dbg_dump + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_dbg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used); + +/** + * @brief cmd_mac_reg_dump + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_reg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used); + +/** + * @brief cmd_mac_fw_dump + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_fw_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used); + +/** + * @brief cmd_mac_fw_log_cfg + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_fw_log_cfg(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num, + char *output, u32 out_len, u32 *used); +/** + * @brief cmd_mac_fw_curtcb + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_fw_curtcb(struct mac_ax_adapter *adapter, + char input[][MAC_MAX_ARGV], + u32 input_num, + char *output, u32 out_len, u32 *used); + +/** + * @brief cmd_mac_fw_status_parser + * + * @param *adapter + * @param *input + * @param *input_num + * @return Please Place Description here. + * @retval void + */ +u32 cmd_mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num, char *output, u32 out_len, u32 *used); + +u32 cmd_mac_dl_sym(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], + u32 input_num, char *output, u32 out_len, u32 *used); + +/** + * @brief fw_log_int_dump + * + * @param *adapter + * @param *buf + * @param *msgno + * @param *para_num + * @return Please Place Description here. + * @retval void + */ +static void fw_log_int_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msgno, u8 para_num, + char *str_buf); + +/** + * @brief fw_log_scan_array + * + * @param *adapter + * @param *msgno + * @return Please Place Description here. + * @retval u32 + */ +u32 fw_log_scan_array(struct mac_ax_adapter *adapter, u32 msgno); + +/** + * @brief fw_log_set_array + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +void fw_log_set_array(struct mac_ax_adapter *adapter); + +/** + * @brief fw_log_dump + * + * @param *adapter + * @param *buf + * @param *len + * @param *info + * @return Please Place Description here. + * @retval void + */ +void fw_log_dump(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); + +/** + * @brief fw_log_skip_trailing_zero + * + * @param *s_ptr + * @param *end_ptr + * @return Please Place Description here. + * @retval u8* + */ +u8 *fw_log_skip_trailing_zero(u8 *s_ptr, u8 *end_ptr); + +/** + * @brief fw_log_check_integrity + * + * @param *symbol_tab + * @param *end_ptr + * @return Please Place Description here. + * @retval u32 + */ +u32 fw_log_check_integrity(u8 *symbol_tab, u8 *end_ptr); + +/** + * @brief fw_log_create_array + * + * @param *array_ptr + * @param *symbol_tab + * @param *end_ptr + * @param *enum_count + * @param *enum_list + * @return Please Place Description here. + * @retval u32 + */ +u32 fw_log_create_array(struct mac_ax_adapter *adapter, struct mac_fw_msg *array_ptr, + u8 *symbol_tab, u8 *end_ptr, u32 enum_count, u8 *enum_list); + +/** + * @brief mac_fw_log_set_array + * + * @param *adapter + * @param *symbol_ptr + * @param *file_size + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fw_log_set_array(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size); + +/** + * @brief mac_fw_log_unset_array + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fw_log_unset_array(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/dbgpkg.c b/phl/hal_g6/mac/mac_ax/dbgpkg.c new file mode 100644 index 0000000..b95c66b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbgpkg.c @@ -0,0 +1,6024 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "dbgpkg.h" +#include "dbgport_hw.h" + +#if MAC_AX_FEATURE_HV +#include "../hv_ax/phy_rpt_hv.h" +#endif + +static u8 *fwcmd_lb_data; + +/* For DLE DFI */ +static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_freepg = { + 0, + 1, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_quota = { + 0, + 4, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_pagellt = { + 0, + 0xFFF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_pktinfo = { + 0, + 0xFFF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_prepkt = { + 0, + 0xFFF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_nxtpkt = { + 0, + 0xFFF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_qlnktbl = { + 0, + 0x453, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_qempty = { + 0, + 0x11, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_freepg = { + 0, + 1, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_quota = { + 0, + 0xA, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_pagellt = { + 0, + 0xDBF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_pktinfo = { + 0, + 0xDBF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_prepkt = { + 0, + 0xDBF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_nxtpkt = { + 0, + 0xDBF, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_qlnktbl = { + 0, + 0x41, + 1 +}; + +static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_qempty = { + 0, + 1, + 1 +}; + +/* base address mapping table of enum mac_ax_mem_sel */ +static u32 base_addr_map_tbl[MAC_AX_MEM_MAX] = { + CPU_LOCAL_BASE_ADDR, + AXIDMA_BASE_ADDR, + SHARED_BUF_BASE_ADDR, + DMAC_TBL_BASE_ADDR, + SHCUT_MACHDR_BASE_ADDR, + STA_SCHED_BASE_ADDR, + RXPLD_FLTR_CAM_BASE_ADDR, + SEC_CAM_BASE_ADDR, + WOW_CAM_BASE_ADDR, + CMAC_TBL_BASE_ADDR, + ADDR_CAM_BASE_ADDR, + BA_CAM_BASE_ADDR, + BCN_IE_CAM0_BASE_ADDR, + BCN_IE_CAM1_BASE_ADDR, + TXD_FIFO_0_BASE_ADDR, + TXD_FIFO_1_BASE_ADDR, +}; + +/* For dbg port */ +static struct mac_ax_dbg_port_info dbg_port_ptcl_c0 = { + R_AX_PTCL_DBG, + MAC_AX_BYTE_SEL_1, + B_AX_PTCL_DBG_SEL_SH, + B_AX_PTCL_DBG_SEL_MSK, + 0x00, + 0x3F, + 1, + R_AX_PTCL_DBG_INFO, + MAC_AX_BYTE_SEL_4, + B_AX_PTCL_DBG_INFO_SH, + B_AX_PTCL_DBG_INFO_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_ptcl_c1 = { + R_AX_PTCL_DBG_C1, + MAC_AX_BYTE_SEL_1, + B_AX_PTCL_DBG_SEL_SH, + B_AX_PTCL_DBG_SEL_MSK, + 0x00, + 0x3F, + 1, + R_AX_PTCL_DBG_INFO_C1, + MAC_AX_BYTE_SEL_4, + B_AX_PTCL_DBG_INFO_SH, + B_AX_PTCL_DBG_INFO_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_sch_c0 = { + R_AX_SCH_DBG_SEL, + MAC_AX_BYTE_SEL_1, + B_AX_SCH_DBG_SEL_SH, + B_AX_SCH_DBG_SEL_MSK, + 0x00, + 0x2F, + 1, + R_AX_SCH_DBG, + MAC_AX_BYTE_SEL_4, + B_AX_SCHEDULER_DBG_SH, + B_AX_SCHEDULER_DBG_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_sch_c1 = { + R_AX_SCH_DBG_SEL_C1, + MAC_AX_BYTE_SEL_1, + B_AX_SCH_DBG_SEL_SH, + B_AX_SCH_DBG_SEL_MSK, + 0x00, + 0x2F, + 1, + R_AX_SCH_DBG_C1, + MAC_AX_BYTE_SEL_4, + B_AX_SCHEDULER_DBG_SH, + B_AX_SCHEDULER_DBG_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tmac_c0 = { + R_AX_MACTX_DBG_SEL_CNT, + MAC_AX_BYTE_SEL_1, + B_AX_DBGSEL_MACTX_SH, + B_AX_DBGSEL_MACTX_MSK, + 0x00, + 0x19, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tmac_c1 = { + R_AX_MACTX_DBG_SEL_CNT_C1, + MAC_AX_BYTE_SEL_1, + B_AX_DBGSEL_MACTX_SH, + B_AX_DBGSEL_MACTX_MSK, + 0x00, + 0x19, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_rmac_c0 = { + R_AX_RX_DEBUG_SELECT, + MAC_AX_BYTE_SEL_1, + B_AX_DEBUG_SEL_SH, + B_AX_DEBUG_SEL_MSK, + 0x00, + 0x58, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_rmac_c1 = { + R_AX_RX_DEBUG_SELECT_C1, + MAC_AX_BYTE_SEL_1, + B_AX_DEBUG_SEL_SH, + B_AX_DEBUG_SEL_MSK, + 0x00, + 0x58, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_rmacst_c0 = { + R_AX_RX_STATE_MONITOR, + MAC_AX_BYTE_SEL_1, + B_AX_STATE_SEL_SH, + B_AX_STATE_SEL_MSK, + 0x00, + 0x17, + 1, + R_AX_RX_STATE_MONITOR, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffffL +}; + +static struct mac_ax_dbg_port_info dbg_port_rmacst_c1 = { + R_AX_RX_STATE_MONITOR_C1, + MAC_AX_BYTE_SEL_1, + B_AX_STATE_SEL_SH, + B_AX_STATE_SEL_MSK, + 0x00, + 0x17, + 1, + R_AX_RX_STATE_MONITOR_C1, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffffL +}; + +static struct mac_ax_dbg_port_info dbg_port_rmac_plcp_c0 = { + R_AX_RMAC_PLCP_MON, + MAC_AX_BYTE_SEL_4, + B_AX_PCLP_MON_SEL_SH, + B_AX_PCLP_MON_SEL_MSK, + 0x0, + 0xF, + 1, + R_AX_RMAC_PLCP_MON, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffffL +}; + +static struct mac_ax_dbg_port_info dbg_port_rmac_plcp_c1 = { + R_AX_RMAC_PLCP_MON_C1, + MAC_AX_BYTE_SEL_4, + B_AX_PCLP_MON_SEL_SH, + B_AX_PCLP_MON_SEL_MSK, + 0x0, + 0xF, + 1, + R_AX_RMAC_PLCP_MON_C1, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffffL +}; + +static struct mac_ax_dbg_port_info dbg_port_trxptcl_c0 = { + R_AX_DBGSEL_TRXPTCL, + MAC_AX_BYTE_SEL_1, + B_AX_DBGSEL_TRXPTCL_SH, + B_AX_DBGSEL_TRXPTCL_MSK, + 0x08, + 0x10, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_trxptcl_c1 = { + R_AX_DBGSEL_TRXPTCL_C1, + MAC_AX_BYTE_SEL_1, + B_AX_DBGSEL_TRXPTCL_SH, + B_AX_DBGSEL_TRXPTCL_MSK, + 0x08, + 0x10, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tx_infol_c0 = { + R_AX_WMAC_TX_CTRL_DEBUG, + MAC_AX_BYTE_SEL_1, + B_AX_TX_CTRL_DEBUG_SEL_SH, + B_AX_TX_CTRL_DEBUG_SEL_MSK, + 0x00, + 0x07, + 1, + R_AX_WMAC_TX_INFO0_DEBUG, + MAC_AX_BYTE_SEL_4, + B_AX_TX_CTRL_INFO_P0_SH, + B_AX_TX_CTRL_INFO_P0_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tx_infoh_c0 = { + R_AX_WMAC_TX_CTRL_DEBUG, + MAC_AX_BYTE_SEL_1, + B_AX_TX_CTRL_DEBUG_SEL_SH, + B_AX_TX_CTRL_DEBUG_SEL_MSK, + 0x00, + 0x07, + 1, + R_AX_WMAC_TX_INFO1_DEBUG, + MAC_AX_BYTE_SEL_4, + B_AX_TX_CTRL_INFO_P1_SH, + B_AX_TX_CTRL_INFO_P1_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tx_infol_c1 = { + R_AX_WMAC_TX_CTRL_DEBUG_C1, + MAC_AX_BYTE_SEL_1, + B_AX_TX_CTRL_DEBUG_SEL_SH, + B_AX_TX_CTRL_DEBUG_SEL_MSK, + 0x00, + 0x07, + 1, + R_AX_WMAC_TX_INFO0_DEBUG_C1, + MAC_AX_BYTE_SEL_4, + B_AX_TX_CTRL_INFO_P0_SH, + B_AX_TX_CTRL_INFO_P0_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_tx_infoh_c1 = { + R_AX_WMAC_TX_CTRL_DEBUG_C1, + MAC_AX_BYTE_SEL_1, + B_AX_TX_CTRL_DEBUG_SEL_SH, + B_AX_TX_CTRL_DEBUG_SEL_MSK, + 0x00, + 0x07, + 1, + R_AX_WMAC_TX_INFO1_DEBUG_C1, + MAC_AX_BYTE_SEL_4, + B_AX_TX_CTRL_INFO_P1_SH, + B_AX_TX_CTRL_INFO_P1_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_txtf_infol_c0 = { + R_AX_WMAC_TX_TF_INFO_0, + MAC_AX_BYTE_SEL_1, + B_AX_WMAC_TX_TF_INFO_SEL_SH, + B_AX_WMAC_TX_TF_INFO_SEL_MSK, + 0x00, + 0x04, + 1, + R_AX_WMAC_TX_TF_INFO_1, + MAC_AX_BYTE_SEL_4, + B_AX_WMAC_TX_TF_INFO_P0_SH, + B_AX_WMAC_TX_TF_INFO_P0_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_txtf_infoh_c0 = { + R_AX_WMAC_TX_TF_INFO_0, + MAC_AX_BYTE_SEL_1, + B_AX_WMAC_TX_TF_INFO_SEL_SH, + B_AX_WMAC_TX_TF_INFO_SEL_MSK, + 0x00, + 0x04, + 1, + R_AX_WMAC_TX_TF_INFO_2, + MAC_AX_BYTE_SEL_4, + B_AX_WMAC_TX_TF_INFO_P1_SH, + B_AX_WMAC_TX_TF_INFO_P1_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_txtf_infol_c1 = { + R_AX_WMAC_TX_TF_INFO_0_C1, + MAC_AX_BYTE_SEL_1, + B_AX_WMAC_TX_TF_INFO_SEL_SH, + B_AX_WMAC_TX_TF_INFO_SEL_MSK, + 0x00, + 0x04, + 1, + R_AX_WMAC_TX_TF_INFO_1_C1, + MAC_AX_BYTE_SEL_4, + B_AX_WMAC_TX_TF_INFO_P0_SH, + B_AX_WMAC_TX_TF_INFO_P0_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_txtf_infoh_c1 = { + R_AX_WMAC_TX_TF_INFO_0_C1, + MAC_AX_BYTE_SEL_1, + B_AX_WMAC_TX_TF_INFO_SEL_SH, + B_AX_WMAC_TX_TF_INFO_SEL_MSK, + 0x00, + 0x04, + 1, + R_AX_WMAC_TX_TF_INFO_2_C1, + MAC_AX_BYTE_SEL_4, + B_AX_WMAC_TX_TF_INFO_P1_SH, + B_AX_WMAC_TX_TF_INFO_P1_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_cmac_dma0_c0 = { + R_AX_RXDMA_CTRL_0, + MAC_AX_BYTE_SEL_4, + B_AX_RXDMA_FIFO_DBG_SEL_SH, + 0x3F, + 0x00, + 0x3F, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_cmac_dma1_c0 = { + R_AX_TXDMA_DBG, + MAC_AX_BYTE_SEL_4, + B_AX_TXDMA_DBG_SEL_SH, + B_AX_TXDMA_DBG_SEL_MSK, + 0x00, + 0x03, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_cmac_dma0_c1 = { + R_AX_RXDMA_CTRL_0_C1, + MAC_AX_BYTE_SEL_4, + B_AX_RXDMA_FIFO_DBG_SEL_SH, + 0x3F, + 0x00, + 0x3F, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_cmac_dma1_c1 = { + R_AX_TXDMA_DBG_C1, + MAC_AX_BYTE_SEL_4, + B_AX_TXDMA_DBG_SEL_SH, + B_AX_TXDMA_DBG_SEL_MSK, + 0x00, + 0x03, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pktinfo = { + R_AX_DBG_FUN_INTF_CTL, + MAC_AX_BYTE_SEL_4, + B_AX_DFI_DATA_SH, + B_AX_DFI_DATA_MSK, + 0x80000000, + 0x8000017f, + 1, + R_AX_DBG_FUN_INTF_DATA, + MAC_AX_BYTE_SEL_4, + B_AX_DFI_DATA_SH, + B_AX_DFI_DATA_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_wdrls = { + R_AX_DBG_CTL_WDRLS, + MAC_AX_BYTE_SEL_2, + 0, + 0xffff, + 0x0000, + 0x0D0D, + 0x0101, + R_AX_DBG_OUT_WDRLS, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl0 = { + R_AX_DBG_CTL_TXPKT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, + 0x00000000, + 0x00030003, + 0x00010001, + R_AX_TPC_DBG_OUT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl1 = { + R_AX_DBG_CTL_TXPKT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, + 0x00800080, + 0x008F008F, + 0x00010001, + R_AX_TPC_DBG_OUT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl2 = { + R_AX_DBG_CTL_TXPKT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, + 0x01000100, + 0x01FF01FF, + 0x00010001, + R_AX_TPC_DBG_OUT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl3 = { + R_AX_DBG_CTL_TXPKT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, + 0x02800280, + 0x028F028F, + 0x00010001, + R_AX_TPC_DBG_OUT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl4 = { + R_AX_DBG_CTL_TXPKT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, + 0x03000300, + 0x030F030F, + 0x00010001, + R_AX_TPC_DBG_OUT, + MAC_AX_BYTE_SEL_4, + 0, + 0xffffffff, +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_txdma = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x03, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_rxdma = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x04, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_cvt = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x01, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac04 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x05, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac5 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac6 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac7 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_pnp_io = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x05, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac814 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x06, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac15 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac16 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac17 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_pcie_emac18 = { + R_AX_PCIE_DBG_CTRL, + MAC_AX_BYTE_SEL_2, + B_AX_DBG_SEL_SH, + B_AX_DBG_SEL_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_phy = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_sie = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x04, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_utmi = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x01, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_sie_mmu = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x03, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_sie_pce = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x03, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_utmi_if = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x00, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_wltx = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x04, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_wlrx = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x0D, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb3 = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x0E, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_setup = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x01, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_wltx_dma = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x09, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_wlrx_dma = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x0F, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_ainst = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x02, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_misc = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x01, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb_bttx = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x07, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_usb2_bt = { + R_AX_STC_INT_CS, + MAC_AX_BYTE_SEL_1, + B_AX_STC_INT_REALTIME_CS_SH, + B_AX_STC_INT_REALTIME_CS_MSK, + 0x00, + 0x01, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0xD, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx6 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x5, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx7 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x9, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx8 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x3, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx9_C = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x1, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_txD = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x0, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx0 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0xB, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx1 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x4, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx3 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x8, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx4 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x7, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x1, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx9 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x3, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx0 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x8, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x0, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx3 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_2, + B_AX_DISPATCHER_DBG_SEL_SH, + B_AX_DISPATCHER_DBG_SEL_MSK, + 0x0, + 0x6, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_rx_p0 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0x3, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x8, + 0xE, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_stf_ctrl = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0x5, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_addr_ctrl = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0x6, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_wde_intf = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0xF, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_ple_intf = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0x9, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_dspt_flow_ctrl = { + R_AX_DISPATCHER_DBG_PORT, + MAC_AX_BYTE_SEL_1, + B_AX_DISPATCHER_CH_SEL_SH, + B_AX_DISPATCHER_CH_SEL_MSK, + 0x0, + 0x3, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_axi_txdma_ctrl = { + R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, + MAC_AX_BYTE_SEL_4, + B_PL_AXIDMA_DBG_SEL_SH, + 0x3F, + 0x0, + 0x1B, + 9, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_axi_rxdma_ctrl = { + R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, + MAC_AX_BYTE_SEL_4, + B_PL_AXIDMA_DBG_SEL_SH, + 0x3F, + 0x0, + 0x36, + 9, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_axi_mst_wlan = { + R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, + MAC_AX_BYTE_SEL_4, + B_PL_AXIDMA_DBG_SEL_SH, + 0x3F, + 0x0, + 0, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_axi_int_wlan = { + R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, + MAC_AX_BYTE_SEL_4, + B_PL_AXIDMA_DBG_SEL_SH, + 0x3F, + 0x0, + 0, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +static struct mac_ax_dbg_port_info dbg_port_axi_page_fc = { + R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, + MAC_AX_BYTE_SEL_4, + B_PL_AXIDMA_DBG_SEL_SH, + 0x3F, + 0x0, + 0, + 1, + R_AX_DBG_PORT_SEL, + MAC_AX_BYTE_SEL_4, + B_AX_DEBUG_ST_SH, + B_AX_DEBUG_ST_MSK +}; + +u32 mac_fwcmd_lb(struct mac_ax_adapter *adapter, u32 len, u8 burst) +{ + u32 i; + u32 ret; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + enum h2c_buf_class buf_class; + u8 *buf; + + if (!burst) { + if (fwcmd_lb_data) { + PLTFM_MSG_ERR("C2H loopbakc is not received\n"); + return MACWQBUSY; + } + } + + if (len <= H2C_CMD_LEN) + buf_class = H2CB_CLASS_CMD; + else if (len <= H2C_DATA_LEN) + buf_class = H2CB_CLASS_DATA; + else + buf_class = H2CB_CLASS_LONG_DATA; + + h2cb = h2cb_alloc(adapter, buf_class); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, len - FWCMD_HDR_LEN); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + for (i = 0; i < len - FWCMD_HDR_LEN; i++) + buf[i] = (u8)(i & 0xFF); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_TEST, + FWCMD_H2C_CL_CMD_PATH, + FWCMD_H2C_FUNC_H2C_LB, + 0, + 0); + if (ret != MACSUCCESS) + goto fail; + + if (!burst) { + fwcmd_lb_data = (u8 *)PLTFM_MALLOC(len); +#if MAC_AX_PHL_H2C + PLTFM_MEMCPY(fwcmd_lb_data, h2cb->vir_data, len); +#else + PLTFM_MEMCPY(fwcmd_lb_data, h2cb->data, len); +#endif + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + goto fail; + } + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + PLTFM_FREE(fwcmd_lb_data, len); + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 c2h_sys_cmd_lb(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 hdr1; + u32 c2h_len; + u32 h2c_len; + u32 ret = MACSUCCESS; + + PLTFM_MSG_TRACE("receive c2h cmd_lb\n"); + + if (!fwcmd_lb_data) + return MACSUCCESS; + + hdr1 = ((struct fwcmd_hdr *)buf)->hdr1; + hdr1 = le32_to_cpu(hdr1); + c2h_len = GET_FIELD(hdr1, C2H_HDR_TOTAL_LEN); + + hdr1 = ((struct fwcmd_hdr *)fwcmd_lb_data)->hdr1; + hdr1 = le32_to_cpu(hdr1); + h2c_len = GET_FIELD(hdr1, H2C_HDR_TOTAL_LEN); + + if (c2h_len != h2c_len) { + PLTFM_MSG_ERR("[ERR]fwcmd lb wrong len\n"); + ret = MACCMP; + goto END; + } + + if (PLTFM_MEMCMP(buf + FWCMD_HDR_LEN, fwcmd_lb_data + FWCMD_HDR_LEN, + c2h_len - FWCMD_HDR_LEN)) { + PLTFM_MSG_ERR("[ERR]fwcmd lb contents compare fail\n"); + ret = MACCMP; + goto END; + } + +END: + PLTFM_FREE(fwcmd_lb_data, len); + fwcmd_lb_data = NULL; + + return ret; +} + +static struct c2h_proc_func c2h_proc_sys_cmd_path[] = { + {FWCMD_C2H_FUNC_C2H_LB, c2h_sys_cmd_lb}, +#if MAC_AX_FEATURE_HV + {FWCMD_C2H_FUNC_TEST_PHY_RPT, c2h_test_phy_rpt}, +#endif + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_sys_cmd_path(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_sys_cmd_path; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: 0x%X\n", proc->id); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_sys_plat_autotest(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + //struct c2h_proc_func *proc = c2h_proc_sys_palt_autotest; + //u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + // struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + //PLTFM_MSG_TRACE("c2h_sys_plat_autotest\n"); + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + //set info + info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT); + info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS); + info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC); + //info->done_ack = 0; + //info->rec_ack = 0; + info->content = buf + FWCMD_HDR_LEN; + //info->h2c_return = info->c2h_data[1]; + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + return MACSUCCESS; +} + +u32 iecam_aces_cfg(struct mac_ax_adapter *adapter, u8 band, u8 en, + struct iecam_cfg_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 camctrl_reg, rbp_reg, ioctrl_reg; + u16 ioctrl_bit; + u32 cnt; + + camctrl_reg = band == MAC_AX_BAND_0 ? + R_AX_BCN_IECAM_CTRL : R_AX_BCN_IECAM_CTRL_C1; + + rbp_reg = band == MAC_AX_BAND_0 ? + R_AX_BCN_PSR_CTRL : R_AX_BCN_PSR_CTRL_C1; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + ioctrl_reg = band == MAC_AX_BAND_0 ? + R_AX_RXGCK_CTRL : R_AX_RXGCK_CTRL_C1; + ioctrl_bit = B_AX_DISGCLK; + } else { + ioctrl_reg = camctrl_reg; + ioctrl_bit = B_AX_BCN_IECAM_IORST; + } + + if (en == MAC_AX_FUNC_DIS) { + /* Restore original setting */ + MAC_REG_W16(camctrl_reg, info->camctrl_bkp); + MAC_REG_W32(rbp_reg, info->rbp_bkp); + MAC_REG_W16(ioctrl_reg, info->ioctrl_bkp); + return MACSUCCESS; + } + + info->camctrl_bkp = MAC_REG_R16(camctrl_reg); + if (info->camctrl_bkp & B_AX_BCN_IECAM_EN) + MAC_REG_W16(camctrl_reg, info->camctrl_bkp & ~B_AX_BCN_IECAM_EN); + + info->rbp_bkp = MAC_REG_R32(rbp_reg); + if (info->rbp_bkp & B_AX_TIM_PARSER_EN) + MAC_REG_W32(rbp_reg, info->rbp_bkp & ~B_AX_TIM_PARSER_EN); + + info->ioctrl_bkp = MAC_REG_R16(ioctrl_reg); + if (!(info->ioctrl_bkp & ioctrl_bit)) + MAC_REG_W16(ioctrl_reg, info->ioctrl_bkp | ioctrl_bit); + + cnt = BCN_PSR_WAIT_CNT; + while (cnt-- && MAC_REG_R16(camctrl_reg) & B_AX_BCN_PSR_BUSY) + PLTFM_DELAY_US(BCN_PSR_WAIT_US); + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]BCN PSR polling timeout\n"); + return MACPOLLTO; + } + + return MACSUCCESS; +} + +static u32 __dump_mac_mem(struct mac_ax_adapter *adapter, + enum mac_ax_mem_sel sel, u32 offset, u8 *buf, u32 len, + u32 dbg_path) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct iecam_cfg_info iec_info; + u32 base_addr, strt_pg, residue, i, cnt, val32; + u32 ret = MACSUCCESS, ret2; + u8 iecam_cfg_flag, band; + + if (sel >= MAC_AX_MEM_LAST) + return MACNOITEM; + + if (sel == MAC_AX_MEM_BCN_IE_CAM0 || sel == MAC_AX_MEM_BCN_IE_CAM1) { + iecam_cfg_flag = 1; + band = sel == MAC_AX_MEM_BCN_IE_CAM0 ? + MAC_AX_BAND_0 : MAC_AX_BAND_1; + } else { + iecam_cfg_flag = 0; + band = 0; + } + + if (iecam_cfg_flag) { + ret = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_EN, &iec_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]iecam access en fail %d\n", ret); + ret2 = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_DIS, + &iec_info); + if (ret2 != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]iecam access dis fail %d\n", + ret2); + return ret; + } + } + + strt_pg = offset / MAC_MEM_DUMP_PAGE_SIZE; + residue = offset % MAC_MEM_DUMP_PAGE_SIZE; + base_addr = base_addr_map_tbl[sel] + strt_pg * MAC_MEM_DUMP_PAGE_SIZE; + + cnt = 0; + while (cnt < len) { + //PLTFM_MSG_ERR("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, base_addr); + for (i = R_AX_INDIR_ACCESS_ENTRY + residue; + i < R_AX_INDIR_ACCESS_ENTRY + MAC_MEM_DUMP_PAGE_SIZE; + i += 4) { + val32 = le32_to_cpu(MAC_REG_R32(i)); + if (dbg_path) + *(u32 *)(buf + cnt) = val32; + else + PLTFM_MSG_ALWAYS("0x%X: 0x%X\n", + (base_addr + i - + R_AX_INDIR_ACCESS_ENTRY), + val32); + cnt += 4; + if (cnt >= len) + break; + } + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + //PLTFM_MSG_ERR("%s ind access sel %d end\n", __func__, sel); + + residue = 0; + base_addr += MAC_MEM_DUMP_PAGE_SIZE; + } + + if (iecam_cfg_flag) { + ret = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_DIS, &iec_info); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]iecam access dis fail %d\n", ret); + } + + return ret; +} + +u32 mac_mem_dump(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel, + u32 strt_addr, u8 *buf, u32 len, u32 dbg_path) +{ + u32 ret, size; + + if (len & (4 - 1)) { + PLTFM_MSG_ERR("[ERR]not 4byte alignment\n"); + return MACBUFSZ; + } + + size = mac_get_mem_size(adapter, sel); + if (len > size) { + PLTFM_MSG_ERR("[ERR]len %d over max mem size %d\n", len, size); + return MACBUFSZ; + } + + /* dbg_path: 1: memory ; 0: console */ + if (dbg_path) { + if (!buf) { + PLTFM_MSG_ERR("[ERR]null buf for mem dump\n"); + return MACNPTR; + } + } + + ret = __dump_mac_mem(adapter, sel, strt_addr, buf, len, dbg_path); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dump mac memory\n"); + return ret; + } + + return MACSUCCESS; +} + +u32 mac_get_mem_size(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel) +{ + u32 size; + u16 macid_num = adapter->hw_info->macid_num; + + switch (sel) { + case MAC_AX_MEM_AXIDMA: + size = AXIDMA_REG_SIZE; + break; + case MAC_AX_MEM_SHARED_BUF: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + size = SHARE_BUFFER_SIZE_8852A; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + size = SHARE_BUFFER_SIZE_8852B; + else + size = 0; + break; + case MAC_AX_MEM_DMAC_TBL: + size = DCTL_INFO_SIZE * macid_num; + break; + case MAC_AX_MEM_SHCUT_MACHDR: + size = MACHDR_SIZE * macid_num; + break; + case MAC_AX_MEM_STA_SCHED: + size = STA_SCHED_MEM_SIZE; + break; + case MAC_AX_MEM_RXPLD_FLTR_CAM: + size = RXPLD_FLTR_CAM_MEM_SIZE; + break; + case MAC_AX_MEM_SECURITY_CAM: + size = SECURITY_CAM_MEM_SIZE; + break; + case MAC_AX_MEM_WOW_CAM: + size = WOW_CAM_MEM_SIZE; + break; + case MAC_AX_MEM_CMAC_TBL: + size = CCTL_INFO_SIZE * macid_num; + break; + case MAC_AX_MEM_ADDR_CAM: + size = ADDR_CAM_MEM_SIZE; + break; + case MAC_AX_MEM_BA_CAM: + size = BA_CAM_SIZE << BA_CAM_NUM_SH; + break; + case MAC_AX_MEM_BCN_IE_CAM0: + size = BCN_IE_CAM_SIZE * BCN_IE_CAM_NUM; + break; + case MAC_AX_MEM_BCN_IE_CAM1: + size = BCN_IE_CAM_SIZE * BCN_IE_CAM_NUM; + break; + case MAC_AX_MEM_TXD_FIFO_0: + case MAC_AX_MEM_TXD_FIFO_1: + size = TXD_FIFO_SIZE; + break; + default: + size = 0; + break; + } + + return size; +} + +static u32 __dump_reg_range(struct mac_ax_adapter *adapter, + u32 srt, u32 end) +{ +#define REG_PAGE_SIZE 0x100 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 i, j, k, page, val32; + + for (i = srt; i <= end; i++) { + page = i << 8; + for (j = page; j < page + REG_PAGE_SIZE; j += 16) { + PLTFM_MSG_ALWAYS("%08xh : ", 0x18600000 + j); + + for (k = 0; k < 4; k++) { + val32 = MAC_REG_R32(j + 4 * k); + PLTFM_MSG_ALWAYS("%08x ", val32); + } + PLTFM_MSG_ALWAYS("\n"); + } + } + + return MACSUCCESS; +#undef REG_PAGE_SIZE +} + +static u32 __dump_mac_reg(struct mac_ax_adapter *adapter, + enum mac_ax_reg_sel sel) +{ + u32 srt, end; + + switch (sel) { + case MAC_AX_REG_MAC: + srt = MAC_PAGE_SRT; + if (adapter->sm.pwr != MAC_AX_PWR_ON) { + PLTFM_MSG_WARN("[WARN]MAC is not power on %d\n", + adapter->sm.pwr); + end = MAC_PAGE_AON_END; + } else { + end = MAC_PAGE_TOP_END; + } + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + + srt = MAC_PAGE_HCI_SRT; + end = MAC_PAGE_HCI_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + + if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_DMAC_SEL) + == MACSUCCESS) { + srt = MAC_PAGE_DMAC_SRT; + end = MAC_PAGE_DMAC_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + } + + if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL) + == MACSUCCESS) { + srt = MAC_PAGE_CMAC0_SRT; + end = MAC_PAGE_CMAC0_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + } + + if (check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL) + == MACSUCCESS) { + srt = MAC_PAGE_CMAC1_SRT; + end = MAC_PAGE_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + } + + PLTFM_MSG_ALWAYS("dump MAC REG all\n"); + break; + case MAC_AX_REG_BB: + srt = BB_PAGE_SRT; + end = BB_PAGE_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + PLTFM_MSG_ALWAYS("dump BB REG all\n"); + break; + case MAC_AX_REG_IQK: + srt = IQK_PAGE_SRT; + end = IQK_PAGE_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + PLTFM_MSG_ALWAYS("dump IQK REG all\n"); + break; + case MAC_AX_REG_RFC: + srt = RFC_PAGE_SRT; + end = RFC_PAGE_END; + PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end); + __dump_reg_range(adapter, srt, end); + PLTFM_MSG_ALWAYS("dump RFC REG all\n"); + break; + default: + PLTFM_MSG_ERR("Page sel error (%d)\n", sel); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_reg_dump(struct mac_ax_adapter *adapter, enum mac_ax_reg_sel sel) +{ + u32 ret; + + adapter->sm.l2_st = MAC_AX_L2_DIS; + + ret = __dump_mac_reg(adapter, sel); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dump mac memory\n"); + return ret; + } + + adapter->sm.l2_st = MAC_AX_L2_EN; + + return MACSUCCESS; +} + +u32 dbg_port_sel(struct mac_ax_adapter *adapter, + struct mac_ax_dbg_port_info **info, u32 sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u16 val16; + u8 val8, index; + u32 ret = MACSUCCESS; + + PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock); + adapter->hw_info->dbg_port_cnt++; + + if (adapter->hw_info->dbg_port_cnt != 1) { + PLTFM_MSG_ERR("[ERR]dbg port sel %d lock cnt %d\n", sel, + adapter->hw_info->dbg_port_cnt); + ret = MACCMP; + goto err; + } + + switch (sel) { + case MAC_AX_DBG_PORT_SEL_PTCL_C0: + *info = &dbg_port_ptcl_c0; + val16 = MAC_REG_R16(R_AX_PTCL_DBG); + val16 |= B_AX_PTCL_DBG_EN; + MAC_REG_W16(R_AX_PTCL_DBG, val16); + PLTFM_MSG_ALWAYS("Enable PTCL C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PTCL_C1: + *info = &dbg_port_ptcl_c1; + val16 = MAC_REG_R16(R_AX_PTCL_DBG_C1); + val16 |= B_AX_PTCL_DBG_EN; + MAC_REG_W16(R_AX_PTCL_DBG_C1, val16); + PLTFM_MSG_ALWAYS("Enable PTCL C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_SCH_C0: + *info = &dbg_port_sch_c0; + val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL); + val32 |= B_AX_SCH_DBG_EN; + MAC_REG_W32(R_AX_SCH_DBG_SEL, val32); + PLTFM_MSG_ALWAYS("Enable SCH C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_SCH_C1: + *info = &dbg_port_sch_c1; + val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL_C1); + val32 |= B_AX_SCH_DBG_EN; + MAC_REG_W32(R_AX_SCH_DBG_SEL_C1, val32); + PLTFM_MSG_ALWAYS("Enable SCH C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TMAC_C0: + *info = &dbg_port_tmac_c0; + val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL); + val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W32(R_AX_DBGSEL_TRXPTCL, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + PLTFM_MSG_ALWAYS("Enable TMAC C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TMAC_C1: + *info = &dbg_port_tmac_c1; + val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL_C1); + val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W32(R_AX_DBGSEL_TRXPTCL_C1, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + PLTFM_MSG_ALWAYS("Enable TMAC C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_C0: + *info = &dbg_port_rmac_c0; + val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL); + val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W32(R_AX_DBGSEL_TRXPTCL, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + + val8 = MAC_REG_R8(R_AX_DBGSEL_TRXPTCL); + val8 = SET_CLR_WORD(val8, RMAC_CMAC_DBG_SEL, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W8(R_AX_DBGSEL_TRXPTCL, val8); + PLTFM_MSG_ALWAYS("Enable RMAC C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_C1: + *info = &dbg_port_rmac_c1; + val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL_C1); + val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W32(R_AX_DBGSEL_TRXPTCL_C1, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + + val8 = MAC_REG_R8(R_AX_DBGSEL_TRXPTCL_C1); + val8 = SET_CLR_WORD(val8, RMAC_CMAC_DBG_SEL, + B_AX_DBGSEL_TRXPTCL); + MAC_REG_W8(R_AX_DBGSEL_TRXPTCL_C1, val8); + PLTFM_MSG_ALWAYS("Enable RMAC C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMACST_C0: + *info = &dbg_port_rmacst_c0; + PLTFM_MSG_ALWAYS("Enable RMAC state C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMACST_C1: + *info = &dbg_port_rmacst_c1; + PLTFM_MSG_ALWAYS("Enable RMAC state C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0: + *info = &dbg_port_rmac_plcp_c0; + PLTFM_MSG_ALWAYS("Enable RMAC PLCP C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1: + *info = &dbg_port_rmac_plcp_c1; + PLTFM_MSG_ALWAYS("Enable RMAC PLCP C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TRXPTCL_C0: + *info = &dbg_port_trxptcl_c0; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + PLTFM_MSG_ALWAYS("Enable TRXPTCL C0 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TRXPTCL_C1: + *info = &dbg_port_trxptcl_c1; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + PLTFM_MSG_ALWAYS("Enable TRXPTCL C1 dbgport.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOL_C0: + *info = &dbg_port_tx_infol_c0; + val32 = MAC_REG_R32(R_AX_TCR1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1, val32); + PLTFM_MSG_ALWAYS("Enable tx infol dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOH_C0: + *info = &dbg_port_tx_infoh_c0; + val32 = MAC_REG_R32(R_AX_TCR1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1, val32); + PLTFM_MSG_ALWAYS("Enable tx infoh dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOL_C1: + *info = &dbg_port_tx_infol_c1; + val32 = MAC_REG_R32(R_AX_TCR1_C1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1_C1, val32); + PLTFM_MSG_ALWAYS("Enable tx infol dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOH_C1: + *info = &dbg_port_tx_infoh_c1; + val32 = MAC_REG_R32(R_AX_TCR1_C1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1_C1, val32); + PLTFM_MSG_ALWAYS("Enable tx infoh dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0: + *info = &dbg_port_txtf_infol_c0; + val32 = MAC_REG_R32(R_AX_TCR1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1, val32); + PLTFM_MSG_ALWAYS("Enable tx tf infol dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0: + *info = &dbg_port_txtf_infoh_c0; + val32 = MAC_REG_R32(R_AX_TCR1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1, val32); + PLTFM_MSG_ALWAYS("Enable tx tf infoh dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1: + *info = &dbg_port_txtf_infol_c1; + val32 = MAC_REG_R32(R_AX_TCR1_C1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1_C1, val32); + PLTFM_MSG_ALWAYS("Enable tx tf infol dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1: + *info = &dbg_port_txtf_infoh_c1; + val32 = MAC_REG_R32(R_AX_TCR1_C1); + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; + MAC_REG_W32(R_AX_TCR1_C1, val32); + PLTFM_MSG_ALWAYS("Enable tx tf infoh dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0: + *info = &dbg_port_cmac_dma0_c0; + + val32 = MAC_REG_R32(R_AX_TXDMA_DBG) | B_AX_TXDMA_DBG_EN; + MAC_REG_W32(R_AX_TXDMA_DBG, val32); + + val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0) | B_AX_RXDMA_DBGOUT_EN; + MAC_REG_W32(R_AX_RXDMA_CTRL_0, val32); + + val32 = MAC_REG_R32(R_AX_DLE_CTRL) | B_AX_DMA_DBG_SEL; + MAC_REG_W32(R_AX_DLE_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + PLTFM_MSG_ALWAYS("Enable cmac0 dma0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0: + *info = &dbg_port_cmac_dma1_c0; + + val32 = MAC_REG_R32(R_AX_TXDMA_DBG) | B_AX_TXDMA_DBG_EN; + MAC_REG_W32(R_AX_TXDMA_DBG, val32); + + val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0) | B_AX_RXDMA_DBGOUT_EN; + MAC_REG_W32(R_AX_RXDMA_CTRL_0, val32); + + val32 = MAC_REG_R32(R_AX_DLE_CTRL) & ~B_AX_DMA_DBG_SEL; + MAC_REG_W32(R_AX_DLE_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + PLTFM_MSG_ALWAYS("Enable cmac0 dma1 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1: + *info = &dbg_port_cmac_dma0_c1; + + val32 = MAC_REG_R32(R_AX_TXDMA_DBG_C1) | B_AX_TXDMA_DBG_EN; + MAC_REG_W32(R_AX_TXDMA_DBG_C1, val32); + + val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0_C1) | + B_AX_RXDMA_DBGOUT_EN; + MAC_REG_W32(R_AX_RXDMA_CTRL_0_C1, val32); + + val32 = MAC_REG_R32(R_AX_DLE_CTRL_C1) | B_AX_DMA_DBG_SEL; + MAC_REG_W32(R_AX_DLE_CTRL_C1, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + PLTFM_MSG_ALWAYS("Enable cmac1 dma0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1: + *info = &dbg_port_cmac_dma1_c1; + + val32 = MAC_REG_R32(R_AX_TXDMA_DBG_C1) | B_AX_TXDMA_DBG_EN; + MAC_REG_W32(R_AX_TXDMA_DBG_C1, val32); + + val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0_C1) | + B_AX_RXDMA_DBGOUT_EN; + MAC_REG_W32(R_AX_RXDMA_CTRL_0_C1, val32); + + val32 = MAC_REG_R32(R_AX_DLE_CTRL_C1) & ~B_AX_DMA_DBG_SEL; + MAC_REG_W32(R_AX_DLE_CTRL_C1, val32); + + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + PLTFM_MSG_ALWAYS("Enable cmac1 dma1 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PKTINFO: + *info = &dbg_port_pktinfo; + PLTFM_MSG_ALWAYS("Enable pktinfo dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_WDRLS: + *info = &dbg_port_wdrls; + PLTFM_MSG_ALWAYS("Enable wdrls dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0: + *info = &dbg_port_txpkt_ctrl0; + PLTFM_MSG_ALWAYS("Enable tx pkt control0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1: + *info = &dbg_port_txpkt_ctrl1; + PLTFM_MSG_ALWAYS("Enable tx pkt control1 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2: + *info = &dbg_port_txpkt_ctrl2; + PLTFM_MSG_ALWAYS("Enable tx pkt control2 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3: + *info = &dbg_port_txpkt_ctrl3; + PLTFM_MSG_ALWAYS("Enable tx pkt control3 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4: + *info = &dbg_port_txpkt_ctrl4; + PLTFM_MSG_ALWAYS("Enable tx pkt control4 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_TXDMA: + *info = &dbg_port_pcie_txdma; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie txdma dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_RXDMA: + *info = &dbg_port_pcie_rxdma; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie rxdma dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_CVT: + *info = &dbg_port_pcie_cvt; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie cvt dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC04: + *info = &dbg_port_pcie_emac04; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC04_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC04_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 0-4 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC5: + *info = &dbg_port_pcie_emac5; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC5_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC5_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 5 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC6: + *info = &dbg_port_pcie_emac6; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC6_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC6_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 6 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC7: + *info = &dbg_port_pcie_emac7; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC7_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC7_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 7 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO: + *info = &dbg_port_pcie_pnp_io; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_PNP_IO_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_PNP_IO_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie p np io dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC814: + *info = &dbg_port_pcie_emac814; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC814_DBG_SEL, + B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC814_DBG_SEL, + B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 8-14 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC15: + *info = &dbg_port_pcie_emac15; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC15_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC15_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 15 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC16: + *info = &dbg_port_pcie_emac16; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC16_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC16_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 16 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC17: + *info = &dbg_port_pcie_emac17; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC17_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC17_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 17 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC18: + *info = &dbg_port_pcie_emac18; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, PCIE_EMAC18_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, PCIE_EMAC18_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable pcie emac 18 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_PHY: + *info = &dbg_port_usb2_phy; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_PHY_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_PHY_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_PHY dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE: + *info = &dbg_port_usb2_sie; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_SIE_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_SIE_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_SIE dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_UTMI: + *info = &dbg_port_usb2_utmi; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_UTMI_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_UTMI_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_UTMI dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU: + *info = &dbg_port_usb2_sie_mmu; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_SIE_MMU_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_SIE_MMU_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_SIE_MMU dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE: + *info = &dbg_port_usb2_sie_pce; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_SIE_PCE_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_SIE_PCE_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_SIE_PCE dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF: + *info = &dbg_port_usb2_utmi_if; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_UTMI_IF_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_UTMI_IF_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_UTMI_IF dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLTX: + *info = &dbg_port_usb_wltx; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_WLTX_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_WLTX_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_WLTX dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLRX: + *info = &dbg_port_usb_wlrx; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_WLRX_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_WLRX_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_WLRX dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB3: + *info = &dbg_port_usb3; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB3_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB3_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB3 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_SETUP: + *info = &dbg_port_usb_setup; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_SETUP_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_SETUP_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_SETUP dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA: + *info = &dbg_port_usb_wltx_dma; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_WLTXDMA_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_WLTXDMA_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_WLTX_DMA dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA: + *info = &dbg_port_usb_wlrx_dma; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_WLRXDMA_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_WLRXDMA_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_WLRX_DMA dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_AINST: + *info = &dbg_port_usb_ainst; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_AINST_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_AINST_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_AINST_DMA dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_MISC: + *info = &dbg_port_usb_misc; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_MISC_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_MISC_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_MISC dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_BTTX: + *info = &dbg_port_usb_bttx; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB_BTTX_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB_BTTX_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB_BTTX dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_BT: + *info = &dbg_port_usb2_bt; + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, USB2_BT_DBG_SEL, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, USB2_BT_DBG_SEL, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_ALWAYS("Enable USB2_BT dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5: + if (sel == MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0) { + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, DISPATCHER_DBG_SEL, + B_AX_DBG_SEL0); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + } + *info = &dbg_port_dspt_hdt_tx0_5; + index = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx%x dump.\n", index); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6: + *info = &dbg_port_dspt_hdt_tx6; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 6, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx6 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7: + *info = &dbg_port_dspt_hdt_tx7; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 7, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx7 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8: + *info = &dbg_port_dspt_hdt_tx8; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 8, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx8 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC: + *info = &dbg_port_dspt_hdt_tx9_C; + index = sel + 9 - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx%x dump.\n", index); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD: + *info = &dbg_port_dspt_hdt_txD; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 0xD, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt txD dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0: + *info = &dbg_port_dspt_cdt_tx0; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX1: + *info = &dbg_port_dspt_cdt_tx1; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx1 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3: + *info = &dbg_port_dspt_cdt_tx3; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 3, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx3 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4: + *info = &dbg_port_dspt_cdt_tx4; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 4, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx4 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8: + *info = &dbg_port_dspt_cdt_tx5_8; + index = sel + 5 - MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx%x dump.\n", index); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9: + *info = &dbg_port_dspt_cdt_tx9; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 9, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx9 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0: + *info = &dbg_port_dspt_hdt_rx0; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2: + *info = &dbg_port_dspt_hdt_rx1_2; + index = sel + 1 - MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx%x dump.\n", index); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3: + *info = &dbg_port_dspt_hdt_rx3; + val16 = MAC_REG_R16((*info)->sel_addr); + val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL); + val16 = SET_CLR_WORD(val16, 3, B_AX_DISPATCHER_CH_SEL); + MAC_REG_W16((*info)->sel_addr, val16); + PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx3 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0: + *info = &dbg_port_dspt_cdt_rx_p0; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 3, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt rx part0 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1: + *info = &dbg_port_dspt_cdt_rx_p1; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 3, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher cdt rx part1 dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL: + *info = &dbg_port_dspt_stf_ctrl; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 4, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher stf control dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL: + *info = &dbg_port_dspt_addr_ctrl; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 5, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher addr control dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF: + *info = &dbg_port_dspt_wde_intf; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 6, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher wde interface dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF: + *info = &dbg_port_dspt_ple_intf; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 7, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher ple interface dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL: + *info = &dbg_port_dspt_flow_ctrl; + val8 = MAC_REG_R8((*info)->sel_addr); + val8 = SET_CLR_WORD(val8, 8, B_AX_DISPATCHER_INTN_SEL); + MAC_REG_W8((*info)->sel_addr, val8); + PLTFM_MSG_ALWAYS("Enable Dispatcher flow control dump.\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL: + *info = &dbg_port_axi_txdma_ctrl; + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32((*info)->sel_addr); + val32 = SET_CLR_WORD(val32, 0, B_AX_AXIDMA_INT_SEL); + MAC_REG_W32((*info)->sel_addr, val32); + PLTFM_MSG_ALWAYS("Enable AXIDMA TXDMA CTRL dump\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL: + *info = &dbg_port_axi_rxdma_ctrl; + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32((*info)->sel_addr); + val32 = SET_CLR_WORD(val32, 1, B_AX_AXIDMA_INT_SEL); + MAC_REG_W32((*info)->sel_addr, val32); + PLTFM_MSG_ALWAYS("Enable AXIDMA RXDMA CTRL dump\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN: + *info = &dbg_port_axi_mst_wlan; + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32((*info)->sel_addr); + val32 = SET_CLR_WORD(val32, 2, B_AX_AXIDMA_INT_SEL); + MAC_REG_W32((*info)->sel_addr, val32); + PLTFM_MSG_ALWAYS("Enable AXIDMA MST WLAN dump\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN: + *info = &dbg_port_axi_int_wlan; + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32((*info)->sel_addr); + val32 = SET_CLR_WORD(val32, 3, B_AX_AXIDMA_INT_SEL); + MAC_REG_W32((*info)->sel_addr, val32); + PLTFM_MSG_ALWAYS("Enable AXIDMA INT WLAN dump\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL: + *info = &dbg_port_axi_page_fc; + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_DBG_CTRL); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0); + val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1); + MAC_REG_W32(R_AX_DBG_CTRL, val32); + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32((*info)->sel_addr); + val32 = SET_CLR_WORD(val32, 4, B_AX_AXIDMA_INT_SEL); + MAC_REG_W32((*info)->sel_addr, val32); + PLTFM_MSG_ALWAYS("Enable AXIDMA PAGE FLOW CTRL dump\n"); + break; + default: + PLTFM_MSG_ALWAYS("Dbg port select err\n"); + *info = NULL; + ret = MACDBGPORTSEL; + goto err; + } + + return MACSUCCESS; +err: + if (ret == MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dbg port sel has no err code\n"); + ret = MACPROCERR; + } + adapter->hw_info->dbg_port_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock); + return ret; +} + +static void print_dbg_port_sel(struct mac_ax_adapter *adapter, u32 sel) +{ + u32 i; + + switch (sel) { + case MAC_AX_DBG_PORT_SEL_PTCL_C0: + PLTFM_MSG_ALWAYS("Dump debug port PTCL C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PTCL_C1: + PLTFM_MSG_ALWAYS("Dump debug port PTCL C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_SCH_C0: + PLTFM_MSG_ALWAYS("Dump debug port SCH C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_SCH_C1: + PLTFM_MSG_ALWAYS("Dump debug port SCH C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TMAC_C0: + PLTFM_MSG_ALWAYS("Dump debug port TMAC C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TMAC_C1: + PLTFM_MSG_ALWAYS("Dump debug port TMAC C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_C0: + PLTFM_MSG_ALWAYS("Dump debug port RMAC C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMAC_C1: + PLTFM_MSG_ALWAYS("Dump debug port RMAC C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMACST_C0: + PLTFM_MSG_ALWAYS("Dump debug port RMACST C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_RMACST_C1: + PLTFM_MSG_ALWAYS("Dump debug port RMACST C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TRXPTCL_C0: + PLTFM_MSG_ALWAYS("Dump debug port TRXPTCL C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TRXPTCL_C1: + PLTFM_MSG_ALWAYS("Dump debug port TRXPTCL C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOL_C0: + PLTFM_MSG_ALWAYS("Dump debug port TXINFOL C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOH_C0: + PLTFM_MSG_ALWAYS("Dump debug port TXINFOH C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOL_C1: + PLTFM_MSG_ALWAYS("Dump debug port TXINFOL C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TX_INFOH_C1: + PLTFM_MSG_ALWAYS("Dump debug port TXINFOH C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0: + PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOL C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0: + PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOH C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1: + PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOL C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1: + PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOH C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0: + PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA0 C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0: + PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA1 C0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1: + PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA0 C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1: + PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA1 C1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PKTINFO: + PLTFM_MSG_ALWAYS("Dump debug port PKTINFO:\n"); + break; + case MAC_AX_DBG_PORT_SEL_WDRLS: + PLTFM_MSG_ALWAYS("Dump debug port WDRLS:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0: + PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL0:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1: + PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL1:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2: + PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL2:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3: + PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL3:\n"); + break; + case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4: + PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL4:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_TXDMA: + PLTFM_MSG_ALWAYS("Dump debug port PCIE TXDMA:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_RXDMA: + PLTFM_MSG_ALWAYS("Dump debug port PCIE RXDMA:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_CVT: + PLTFM_MSG_ALWAYS("Dump debug port PCIE CVT:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC04: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 0-4:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC5: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 5:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC6: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 6:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC7: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 7:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC P-NP-IO:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC814: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 8-14:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC15: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 15:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC16: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 16:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC17: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 17:\n"); + break; + case MAC_AX_DBG_PORT_SEL_PCIE_EMAC18: + PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 18:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_PHY: + PLTFM_MSG_ALWAYS("Dump debug port USB2 PHY:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE: + PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_UTMI: + PLTFM_MSG_ALWAYS("Dump debug port USB2 UTMI:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU: + PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE MMU:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE: + PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE PCE:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF: + PLTFM_MSG_ALWAYS("Dump debug port USB2 UTMI IF:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLTX: + PLTFM_MSG_ALWAYS("Dump debug port USB WLTX:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLRX: + PLTFM_MSG_ALWAYS("Dump debug port USB WLRX:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB3: + PLTFM_MSG_ALWAYS("Dump debug port USB3:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_SETUP: + PLTFM_MSG_ALWAYS("Dump debug port USB SETUP:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA: + PLTFM_MSG_ALWAYS("Dump debug port USB WLTXDMA:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA: + PLTFM_MSG_ALWAYS("Dump debug port USB WLRXDMA:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_AINST: + PLTFM_MSG_ALWAYS("Dump debug port USB AINST:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_MISC: + PLTFM_MSG_ALWAYS("Dump debug port USB2 MISC:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB_BTTX: + PLTFM_MSG_ALWAYS("Dump debug port USB2 BTTX:\n"); + break; + case MAC_AX_DBG_PORT_SEL_USB2_BT: + PLTFM_MSG_ALWAYS("Dump debug port USB2 BT:\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD: + i = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0; + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER HDT TX%x:\n", i); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9: + if (sel == MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0) + i = 0; + else + i = sel + 3 - MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3; + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER CDT TX%x:\n", i); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2: + case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3: + i = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0; + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER HDT RX%x:\n", i); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0: + case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1: + i = sel - MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0; + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER CDT RX part%x:\n", + i); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER STF Control:\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER ADDR Control:\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF: + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER WDE Interface:\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF: + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER PLE Interface:\n"); + break; + case MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER FLOW Control:\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port AXI_TXDMA_CTRL:\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port AXI_RXDMA_CTRL:\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN: + PLTFM_MSG_ALWAYS("Dump debug port AXI_MST_WLAN:\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN: + PLTFM_MSG_ALWAYS("Dump debug port AXI_INT_WLAN::\n"); + break; + case MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL: + PLTFM_MSG_ALWAYS("Dump debug port AXI_PAGE_FLOW_CTRL:\n"); + break; + default: + PLTFM_MSG_WARN("Dump unknown debug port sel %d:\n", sel); + break; + } +} + +static void print_dbg_port(struct mac_ax_adapter *adapter, struct mac_ax_dbg_port_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 i; + u8 val8; + u16 val16; + u32 val32; + + for (i = info->srt; i <= info->end; i += info->inc_num) { + switch (info->sel_byte) { + case MAC_AX_BYTE_SEL_1: + default: + val8 = SET_CLR_WOR2(MAC_REG_R8(info->sel_addr), i, + info->sel_sh, + info->sel_msk); + MAC_REG_W8(info->sel_addr, val8); + PLTFM_MSG_ALWAYS("0x%02X: ", val8); + break; + case MAC_AX_BYTE_SEL_2: + val16 = SET_CLR_WOR2(MAC_REG_R16(info->sel_addr), i, + info->sel_sh, + info->sel_msk); + MAC_REG_W16(info->sel_addr, val16); + PLTFM_MSG_ALWAYS("0x%04X: ", val16); + break; + case MAC_AX_BYTE_SEL_4: + val32 = SET_CLR_WOR2(MAC_REG_R32(info->sel_addr), i, + info->sel_sh, + info->sel_msk); + MAC_REG_W32(info->sel_addr, val32); + PLTFM_MSG_ALWAYS("0x%08X: ", val32); + break; + } + + PLTFM_DELAY_US(DBG_PORT_DUMP_DLY_US); + + switch (info->rd_byte) { + case MAC_AX_BYTE_SEL_1: + default: + val8 = GET_FIEL2(MAC_REG_R8(info->rd_addr), + info->rd_sh, info->rd_msk); + PLTFM_MSG_ALWAYS("0x%02X\n", val8); + break; + case MAC_AX_BYTE_SEL_2: + val16 = GET_FIEL2(MAC_REG_R16(info->rd_addr), + info->rd_sh, info->rd_msk); + PLTFM_MSG_ALWAYS("0x%04X\n", val16); + break; + case MAC_AX_BYTE_SEL_4: + val32 = GET_FIEL2(MAC_REG_R32(info->rd_addr), + info->rd_sh, info->rd_msk); + PLTFM_MSG_ALWAYS("0x%08X\n", val32); + break; + } + } +} + +static u32 dbg_port_dump(struct mac_ax_adapter *adapter, u32 sel) +{ + struct mac_ax_dbg_port_info *info; + u32 ret; + + ret = dbg_port_sel(adapter, &info, sel); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dbg port sel %d %d\n", sel, ret); + return ret; + } + + print_dbg_port_sel(adapter, sel); + + PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info->sel_addr); + PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info->rd_addr); + + print_dbg_port(adapter, info); + + if (sel >= MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL && + sel <= MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL) { + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel); + } + + adapter->hw_info->dbg_port_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock); + + return MACSUCCESS; +} + +static u32 ss_poll_own(struct mac_ax_adapter *adapter, u32 addr) +{ + u32 cnt = 100; + u32 val32 = SS_POLL_UNEXPECTED; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + while (--cnt) { + val32 = MAC_REG_R32(addr); + if ((val32 & B_AX_SS_OWN) == 0) + break; + PLTFM_DELAY_US(1); + } + + return val32; +} + +static u32 ss_tx_len_chk(struct mac_ax_adapter *adapter, u16 macid) +{ + u32 sel; + u32 val32 = 0; + u32 dw[4]; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + for (sel = 0; sel < 4; sel++) { + MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, + B_AX_SS_OWN | + SET_WORD(SS_CTRL1_R_TX_LEN, B_AX_SS_CMD_SEL) | + SET_WORD(sel, B_AX_SS_AC) | macid); + dw[sel] = ss_poll_own(adapter, R_AX_SS_SRAM_CTRL_1); + if (dw[sel] & (BIT(29) | BIT(30))) { + val32 |= SS_POLL_STAT_TX_LEN; + PLTFM_MSG_ALWAYS("[ERR]SS_POLL_STAT_TX_LEN, macid %d, ", + macid); + PLTFM_MSG_ALWAYS("ac %d\n", sel); + PLTFM_MSG_ALWAYS("R_AX_SS_SRAM_CTRL_1 = 0x%x\n", + dw[sel]); + break; + } + if (dw[sel] & B_AX_SS_OWN) { + val32 |= SS_POLL_OWN_TX_LEN; + PLTFM_MSG_ALWAYS("[ERR]SS_POLL_OWN_TX_LEN, macid %d, ", + macid); + PLTFM_MSG_ALWAYS("ac %d\n", sel); + PLTFM_MSG_ALWAYS("R_AX_SS_SRAM_CTRL_1 = 0x%x\n", + dw[sel]); + break; + } + } + + if (((dw[0] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) { + val32 |= SS_TX_LEN_BE; + PLTFM_MSG_ALWAYS("[ERR]SS_TX_LEN_BE, macid %d, ", macid); + PLTFM_MSG_ALWAYS("len 0x%X\n", + (dw[0] >> SS_MACID_SH) & SS_TX_LEN_MSK); + } + if (((dw[1] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) { + val32 |= SS_TX_LEN_BK; + PLTFM_MSG_ALWAYS("[ERR]SS_TX_LEN_BK, macid %d, ", macid); + PLTFM_MSG_ALWAYS("len 0x%X\n", + (dw[1] >> SS_MACID_SH) & SS_TX_LEN_MSK); + } + if (((dw[2] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) { + val32 |= SS_TX_LEN_VI; + PLTFM_MSG_ALWAYS("[ERR]SS_TX_LEN_VI, macid %d, ", macid); + PLTFM_MSG_ALWAYS("len 0x%X\n", + (dw[2] >> SS_MACID_SH) & SS_TX_LEN_MSK); + } + if (((dw[3] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) { + val32 |= SS_TX_LEN_VO; + PLTFM_MSG_ALWAYS("[ERR]SS_TX_LEN_VO, macid %d, ", macid); + PLTFM_MSG_ALWAYS("len 0x%X\n", + (dw[3] >> SS_MACID_SH) & SS_TX_LEN_MSK); + } + + return val32; +} + +static u32 ss_link_chk(struct mac_ax_adapter *adapter, + struct ss_link_info *link) +{ + u32 val32 = 0; + u32 poll; + u8 wmm, ac; + u8 link_head; + u8 link_tail; + u8 link_len; + u32 i; + u32 cmd; + u8 macid; + u16 macid_num = adapter->hw_info->macid_num; + u16 id_empty = (macid_num << 1) - 1; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (link->ul) { + wmm = 0; + ac = 0; + } else { + wmm = link->wmm; + ac = link->ac; + } + + MAC_REG_W32(R_AX_SS_LINK_INFO, B_AX_SS_OWN | + (link->ul ? B_AX_SS_UL : 0) | + SET_WORD(wmm, B_AX_SS_WMM) | + SET_WORD(ac, B_AX_SS_AC)); + poll = ss_poll_own(adapter, R_AX_SS_LINK_INFO); + link_head = GET_FIELD(poll, B_AX_SS_LINK_HEAD); + link_tail = GET_FIELD(poll, B_AX_SS_LINK_TAIL); + link_len = GET_FIELD(poll, B_AX_SS_LINK_LEN); + + if (poll & (BIT(29) | BIT(30))) { + val32 |= SS_POLL_STAT_LINK; + PLTFM_MSG_ALWAYS("[ERR]SS_POLL_STAT_LINK, ul/wmm/ac %d/%d/%d\n", + link->ul, wmm, ac); + PLTFM_MSG_ALWAYS("R_AX_SS_LINK_INFO = 0x%x\n", poll); + return val32; + } + if (poll & B_AX_SS_OWN) { + val32 |= SS_POLL_OWN_LINK; + PLTFM_MSG_ALWAYS("[ERR]SS_POLL_OWN_LINK, ul/wmm/ac %d/%d/%d\n", + link->ul, wmm, ac); + PLTFM_MSG_ALWAYS("R_AX_SS_LINK_INFO = 0x%x\n", poll); + return val32; + } + + if (link_head != id_empty || link_tail != id_empty || link_len != 0) { + if (link->ul) + val32 |= SS_LINK_UL << ((wmm << 2) + ac); + else + val32 |= SS_LINK_WMM0_BE << ((wmm << 2) + ac); + PLTFM_MSG_ALWAYS("[ERR]SS_LINK_DUMP, ul/wmm/ac %d/%d/%d, ", + link->ul, wmm, ac); + PLTFM_MSG_ALWAYS("head/tail/len 0x%X/0x%X/%d\n", + link_head, link_tail, link_len); + macid = link_head; + i = 0; + do { + PLTFM_MSG_ALWAYS("0x%X, ", macid); + cmd = B_AX_SS_OWN | + SET_WORD(SS_CTRL1_R_NEXT_LINK, B_AX_SS_CMD_SEL) | + SET_WORD(ac, B_AX_SS_AC) | + (link->ul ? BIT(23) : 0) | macid; + MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, cmd); + poll = ss_poll_own(adapter, R_AX_SS_SRAM_CTRL_1); + if (poll & (BIT(29) | BIT(30))) { + PLTFM_MSG_ALWAYS("SS_LINK_DUMP_POLL_STAT\n"); + PLTFM_MSG_ALWAYS("R_AX_SS_SRAM_CTRL_1 = 0x%x\n", + poll); + break; + } + if (poll & B_AX_SS_OWN) { + PLTFM_MSG_ALWAYS("SS_LINK_DUMP_POLL_OWN\n"); + PLTFM_MSG_ALWAYS("R_AX_SS_SRAM_CTRL_1 = 0x%x\n", + poll); + break; + } + + if (GET_FIELD(poll, B_AX_SS_VALUE) == id_empty) { + if (macid != link_tail) { + PLTFM_MSG_ALWAYS("[ERR]tail error!!\n"); + break; + } + if (i >= link_len) { + PLTFM_MSG_ALWAYS("[ERR]len error!!\n"); + break; + } + break; + } + macid = GET_FIELD(poll, B_AX_SS_VALUE); + + i++; + } while (i < SS_LINK_SIZE); + PLTFM_MSG_ALWAYS("\n[ERR]SS_LINK_DUMP, end\n"); + } + + return val32; +} + +static u32 ss_stat_chk(struct mac_ax_adapter *adapter) +{ + u32 val32 = 0; + u32 r_val32; + u8 fw_vld; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (adapter->hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + fw_vld = SS_FW_SUPPORT_8852A; + break; + case MAC_AX_CHIP_ID_8852B: + fw_vld = SS_FW_SUPPORT_8852B; + break; + default: + fw_vld = 0; + break; + } + + r_val32 = MAC_REG_R32(R_AX_SS_DBG_3); + if (r_val32 & B_AX_SS_HW_DECR_LEN_UDN) + val32 |= SS_TX_HW_LEN_UDN; + if (r_val32 & B_AX_SS_SW_DECR_LEN_UDN) + val32 |= SS_TX_SW_LEN_UDN; + if (r_val32 & B_AX_SS_HW_ADD_LEN_OVF) + val32 |= SS_TX_HW_LEN_OVF; + + r_val32 = MAC_REG_R32(R_AX_SS_DBG_2); + if (fw_vld) { + if (GET_FIELD(r_val32, B_AX_SS_FWTX_STAT) != 1) + val32 |= SS_STAT_FWTX; + } + if (GET_FIELD(r_val32, B_AX_SS_RPTA_STAT) != 1) + val32 |= SS_STAT_RPTA; + if (GET_FIELD(r_val32, B_AX_SS_WDEA_STAT) != 1) + val32 |= SS_STAT_WDEA; + if (GET_FIELD(r_val32, B_AX_SS_PLEA_STAT) != 1) + val32 |= SS_STAT_PLEA; + + r_val32 = MAC_REG_R32(R_AX_SS_DBG_1); + if (GET_FIELD(r_val32, B_AX_SS_ULRU_STAT) > 1) + val32 |= SS_STAT_ULRU; + if (GET_FIELD(r_val32, B_AX_SS_DLTX_STAT) > 1) + val32 |= SS_STAT_DLTX; + + return val32; +} + +static void ss_dbgpkg_val_parser(struct mac_ax_adapter *adapter, + struct mac_ax_dbgpkg *val) +{ + /* STA Scheduler 0, indirect */ + PLTFM_MSG_ALWAYS("[ERR][STA_SCH] ss_dbg_0 = 0x%X\n", val->ss_dbg_0); + if (val->ss_dbg_0 & SS_TX_LEN_BE) + PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's BE length != 0\n"); + if (val->ss_dbg_0 & SS_TX_LEN_BK) + PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's BK length != 0\n"); + if (val->ss_dbg_0 & SS_TX_LEN_VI) + PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's VI length != 0\n"); + if (val->ss_dbg_0 & SS_TX_LEN_VO) + PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's VO length != 0\n"); + if (val->ss_dbg_0 & SS_LINK_WMM0_BE) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 BE not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM0_BK) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 BK not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM0_VI) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 VI not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM0_VO) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 VO not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM1_BE) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 BE not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM1_BK) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 BK not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM1_VI) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 VI not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM1_VO) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 VO not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM2_BE) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 BE not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM2_BK) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 BK not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM2_VI) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 VI not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM2_VO) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 VO not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM3_BE) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 BE not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM3_BK) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 BK not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM3_VI) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 VI not empty\n"); + if (val->ss_dbg_0 & SS_LINK_WMM3_VO) + PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 VO not empty\n"); + if (val->ss_dbg_0 & SS_LINK_UL) + PLTFM_MSG_ERR("[ERR][STA_SCH] UL not empty\n"); + if (val->ss_dbg_0 & SS_POLL_OWN_TX_LEN) + PLTFM_MSG_ERR("[ERR][STA_SCH] (length) own bit polling fail\n"); + if (val->ss_dbg_0 & SS_POLL_OWN_LINK) + PLTFM_MSG_ERR("[ERR][STA_SCH] (link) own bit polling fail\n"); + if (val->ss_dbg_0 & SS_POLL_STAT_TX_LEN) + PLTFM_MSG_ERR("[ERR][STA_SCH] (length) state machine fail\n"); + if (val->ss_dbg_0 & SS_POLL_STAT_LINK) + PLTFM_MSG_ERR("[ERR][STA_SCH] (link) state machine fail\n"); + + /* STA Scheduler 1, direct */ + PLTFM_MSG_ALWAYS("[ERR][STA_SCH] ss_dbg_1 = 0x%X\n", val->ss_dbg_1); + if (val->ss_dbg_1 & SS_TX_HW_LEN_UDN) + PLTFM_MSG_ERR("[ERR][STA_SCH] HW cause length underflow\n"); + if (val->ss_dbg_1 & SS_TX_SW_LEN_UDN) + PLTFM_MSG_ERR("[ERR][STA_SCH] SW cause length underflow\n"); + if (val->ss_dbg_1 & SS_TX_HW_LEN_OVF) + PLTFM_MSG_ERR("[ERR][STA_SCH] HW cause length overflow\n"); + if (val->ss_dbg_1 & SS_STAT_FWTX) + PLTFM_MSG_ERR("[ERR][STA_SCH] SW Tx state machine not idle\n"); + if (val->ss_dbg_1 & SS_STAT_RPTA) + PLTFM_MSG_ERR("[ERR][STA_SCH] Report state machine not idle\n"); + if (val->ss_dbg_1 & SS_STAT_WDEA) + PLTFM_MSG_ERR("[ERR][STA_SCH] WDE state machine not idle\n"); + if (val->ss_dbg_1 & SS_STAT_PLEA) + PLTFM_MSG_ERR("[ERR][STA_SCH] PLE state machine not idle\n"); + if (val->ss_dbg_1 & SS_STAT_ULRU) + PLTFM_MSG_ERR("[ERR][STA_SCH] UL RU state machine not idle\n"); + if (val->ss_dbg_1 & SS_STAT_DLTX) + PLTFM_MSG_ERR("[ERR][STA_SCH] HW Tx state machine not idle\n"); +} + +static void ps_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + enum mac_ax_intf intf = adapter->hw_info->intf; + + PLTFM_MSG_ALWAYS("R_AX_PLATFORM_ENABLE=0x%x\n", + MAC_REG_R32(R_AX_PLATFORM_ENABLE)); + PLTFM_MSG_ALWAYS("R_AX_WLLPS_CTRL=0x%x\n", + MAC_REG_R32(R_AX_WLLPS_CTRL)); + PLTFM_MSG_ALWAYS("R_AX_WLRESUME_CTRL=0x%x\n", + MAC_REG_R32(R_AX_WLRESUME_CTRL)); + PLTFM_MSG_ALWAYS("R_AX_SYS_CFG5=0x%x\n", + MAC_REG_R32(R_AX_SYS_CFG5)); + PLTFM_MSG_ALWAYS("R_AX_IC_PWR_STATE=0x%x\n", + MAC_REG_R32(R_AX_IC_PWR_STATE)); + switch (intf) { + case MAC_AX_INTF_USB: + PLTFM_MSG_ALWAYS("USB HRPWM=0x%x\n", + MAC_REG_R16(R_AX_USB_D2F_F2D_INFO + 2)); + break; + case MAC_AX_INTF_SDIO: + PLTFM_MSG_ALWAYS("SDIO HRPWM=0x%x\n", + MAC_REG_R16(R_AX_SDIO_HRPWM1 + 2)); + break; + case MAC_AX_INTF_PCIE: + PLTFM_MSG_ALWAYS("PCIE HRPWM=0x%x\n", + MAC_REG_R16(R_AX_PCIE_HRPWM)); + break; + default: + PLTFM_MSG_ALWAYS("RPWM error interface=%d\n", + intf); + break; + } + PLTFM_MSG_ALWAYS("R_AX_RPWM=0x%x\n", + MAC_REG_R16(R_AX_RPWM)); + PLTFM_MSG_ALWAYS("R_AX_LDM=0x%x\n", + MAC_REG_R32(R_AX_LDM)); + + if (mac_io_chk_access(adapter, R_AX_CPWM) == MACSUCCESS) { + PLTFM_MSG_ALWAYS("R_AX_CPWM=0x%x\n", + MAC_REG_R16(R_AX_CPWM)); + } +} + +u32 fw_backtrace_dump(struct mac_ax_adapter *adapter) +{ + u32 addr = 0; + u32 str_addr = 0; + u32 size = 0; + u32 key = 0; + u32 i; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct fw_backtrace_info info; + + if (adapter->mac_pwr_info.pwr_seq_proc || + adapter->sm.pwr != MAC_AX_PWR_ON || + adapter->mac_pwr_info.pwr_in_lps || + adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE || + adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) { + PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d/pwr in lps %d\n", + adapter->mac_pwr_info.pwr_seq_proc, + adapter->sm.pwr, + adapter->mac_pwr_info.pwr_in_lps); + PLTFM_MSG_ERR("[ERR]sm fw rst %d\n", adapter->sm.fw_rst); + return MACPROCERR; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + addr = RSVD_PLE_OFST_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + addr = RSVD_PLE_OFST_8852B; + } else { + PLTFM_MSG_ERR("[ERR]unknown chip id\n"); + return MACCHIPID; + } + + // Get FW Backtrace start address and size + addr = base_addr_map_tbl[MAC_AX_MEM_SHARED_BUF] + addr; + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr); + str_addr = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY) & ~0xA0000000; + size = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + FW_BACKTRACE_SIZE_OFST); + key = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + FW_BACKTRACE_KEY_OFST); + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_ERR("FW Backtrace addr(0x%x), size(0x%x), key(0x%x)\n", str_addr, size, key); + if (str_addr == 0) + return MACBADDR; + if (size == 0 || size > FW_BACKTRACE_MAX_SIZE + || (size % sizeof(struct fw_backtrace_info) != 0)) + return MACBUFSZ; + if (key != FW_BACKTRACE_KEY) + return MACNOITEM; + + // Dump FW backtrace + PLTFM_MSG_WARN("%s ind access FW backtrace start\n", __func__); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, str_addr); + for (i = 0; i < size; i += sizeof(struct fw_backtrace_info)) { + info.ra = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + i); + info.sp = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + i + 4); + PLTFM_MSG_ERR("Next SP:0x%x, Next RA:0x%x\n", info.sp, info.ra); + } + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access FW backtrace end\n", __func__); + + return MACSUCCESS; +} + +void pltfm_dbg_dump(struct mac_ax_adapter *adapter) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ERR("R_AX_SER_DBG_INFO =0x%08x\n", + MAC_REG_R32(R_AX_SER_DBG_INFO)); + + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INIT_CFG1, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INIT_CFG1 = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_DMA_STOP, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_DMA_STOP = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INIT_CFG2, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INIT_CFG2 = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INFO, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INFO = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_BUSY, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_BUSY = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH0_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH0_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH1_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH1_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH2_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH2_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH3_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH3_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH4_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH4_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH5_RXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH5_RXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH0_TXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH0_TXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH1_TXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH1_TXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH2_TXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH2_TXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH3_TXBD_IDX, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH3_TXBD_IDX = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_DBG_ERR_FLAG, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_DBG_ERR_FLAG = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWIMR0, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWIMR0 = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWIMR1, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWIMR1 = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWISR0, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWISR0 = 0x%x\n", val32); + val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWISR1, AXIDMA_SEL); + PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWISR1 = 0x%x\n", val32); +} + +u32 fw_st_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, i; + + if (adapter->mac_pwr_info.pwr_seq_proc || + adapter->sm.pwr != MAC_AX_PWR_ON) { + PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d\n", + adapter->mac_pwr_info.pwr_seq_proc, + adapter->sm.pwr); + return MACPROCERR; + } + + PLTFM_MSG_ALWAYS("FW status = 0x%x\n", MAC_REG_R32(R_AX_UDM0)); + PLTFM_MSG_ALWAYS("FW BADADDR = 0x%x\n", MAC_REG_R32(R_AX_UDM1)); + PLTFM_MSG_ALWAYS("FW EPC/RA = 0x%x\n", MAC_REG_R32(R_AX_UDM2)); + PLTFM_MSG_ALWAYS("FW MISC = 0x%x\n", MAC_REG_R32(R_AX_UDM3)); + PLTFM_MSG_ALWAYS("R_AX_HALT_C2H = 0x%x\n", MAC_REG_R32(R_AX_HALT_C2H)); + + if (mac_io_chk_access(adapter, R_AX_SER_DBG_INFO) == MACSUCCESS) + PLTFM_MSG_ALWAYS("R_AX_SER_DBG_INFO = 0x%x\n", MAC_REG_R32(R_AX_SER_DBG_INFO)); + + /* Dump FW program counter */ + MAC_REG_W32(R_AX_DBG_CTRL, DBG_SEL_FW_PROG_CNTR); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + + for (i = 0; i < FW_PROG_CNTR_DMP_CNT; i++) { + PLTFM_MSG_ALWAYS("FW PC = 0x%x\n", + MAC_REG_R32(R_AX_DBG_PORT_SEL)); + PLTFM_DELAY_US(FW_PROG_CNTR_DMP_DLY_US); + } + + return MACSUCCESS; +} + +u32 rsvd_ple_dump(struct mac_ax_adapter *adapter) +{ + u32 ret; + u32 addr; + + if (adapter->mac_pwr_info.pwr_seq_proc || + adapter->sm.pwr != MAC_AX_PWR_ON || + adapter->mac_pwr_info.pwr_in_lps || + adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE || + adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) { + PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d/pwr in lps %d\n", + adapter->mac_pwr_info.pwr_seq_proc, + adapter->sm.pwr, + adapter->mac_pwr_info.pwr_in_lps); + PLTFM_MSG_ERR("[ERR]sm fw rst %d\n", adapter->sm.fw_rst); + return MACPROCERR; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + addr = RSVD_PLE_OFST_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + addr = RSVD_PLE_OFST_8852B; + } else { + PLTFM_MSG_ERR("[ERR]unknown chip id\n"); + return MACCHIPID; + } + + ret = mac_mem_dump(adapter, MAC_AX_MEM_SHARED_BUF, addr, 0, + FW_RSVD_PLE_SIZE, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Dump fw rsvd ple\n"); + return ret; + } + + ret = fw_backtrace_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("fw backtrace dump %d\n", ret); + + return MACSUCCESS; +} + +static u32 crit_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ALWAYS("R_AX_SYS_ISO_CTRL=0x%x\n", + MAC_REG_R16(R_AX_SYS_ISO_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_SYS_FUNC_EN=0x%x\n", + MAC_REG_R16(R_AX_SYS_FUNC_EN)); + + PLTFM_MSG_ALWAYS("R_AX_SYS_PW_CTRL=0x%x\n", + MAC_REG_R32(R_AX_SYS_PW_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_SYS_CLK_CTRL=0x%x\n", + MAC_REG_R16(R_AX_SYS_CLK_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_SYS_EEPROM_CTRL=0x%x\n", + MAC_REG_R16(R_AX_SYS_EEPROM_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_DBG_CTRL=0x%x\n", + MAC_REG_R32(R_AX_DBG_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_PLATFORM_ENABLE=0x%x\n", + MAC_REG_R32(R_AX_PLATFORM_ENABLE)); + + PLTFM_MSG_ALWAYS("R_AX_WLLPS_CTRL=0x%x\n", + MAC_REG_R32(R_AX_WLLPS_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_WLRESUME_CTRL=0x%x\n", + MAC_REG_R32(R_AX_WLRESUME_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_DBG_PORT_SEL=0x%x\n", + MAC_REG_R32(R_AX_DBG_PORT_SEL)); + + PLTFM_MSG_ALWAYS("R_AX_HALT_H2C_CTRL=0x%x\n", + MAC_REG_R32(R_AX_HALT_H2C_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_HALT_H2C=0x%x\n", + MAC_REG_R32(R_AX_HALT_H2C)); + + PLTFM_MSG_ALWAYS("R_AX_HALT_C2H_CTRL=0x%x\n", + MAC_REG_R32(R_AX_HALT_C2H_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_HALT_C2H=0x%x\n", + MAC_REG_R32(R_AX_HALT_C2H)); + + PLTFM_MSG_ALWAYS("R_AX_SYS_CFG5=0x%x\n", + MAC_REG_R32(R_AX_SYS_CFG5)); + + PLTFM_MSG_ALWAYS("R_AX_WCPU_FW_CTRL=0x%x\n", + MAC_REG_R32(R_AX_WCPU_FW_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_RPWM=0x%x\n", + MAC_REG_R16(R_AX_RPWM)); + + PLTFM_MSG_ALWAYS("R_AX_BOOT_REASON=0x%x\n", + MAC_REG_R16(R_AX_BOOT_REASON)); + + PLTFM_MSG_ALWAYS("R_AX_LDM=0x%x\n", + MAC_REG_R32(R_AX_LDM)); + + PLTFM_MSG_ALWAYS("R_AX_UDM0=0x%x\n", + MAC_REG_R32(R_AX_UDM0)); + + PLTFM_MSG_ALWAYS("R_AX_UDM1=0x%x\n", + MAC_REG_R32(R_AX_UDM1)); + + PLTFM_MSG_ALWAYS("R_AX_UDM2=0x%x\n", + MAC_REG_R32(R_AX_UDM2)); + + PLTFM_MSG_ALWAYS("R_AX_UDM3=0x%x\n", + MAC_REG_R32(R_AX_UDM3)); + + PLTFM_MSG_ALWAYS("R_AX_IC_PWR_STATE=0x%x\n", + MAC_REG_R32(R_AX_IC_PWR_STATE)); + + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTF=0x%x\n", + MAC_REG_R32(R_AX_PCIE_MIO_INTF)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTD=0x%x\n", + MAC_REG_R32(R_AX_PCIE_MIO_INTD)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_INIT_CFG1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_INIT_CFG1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_STOP1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DMA_STOP1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_BUSY1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DMA_BUSY1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DBG_CTRL=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DBG_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_DBG_ERR_FLAG=0x%x\n", + MAC_REG_R32(R_AX_DBG_ERR_FLAG)); + + PLTFM_MSG_ALWAYS("R_AX_LBC_WATCHDOG=0x%x\n", + MAC_REG_R32(R_AX_LBC_WATCHDOG)); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + PLTFM_MSG_ALWAYS("R_AX_ACH0_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH0_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH1_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH1_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH2_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH2_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH3_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH3_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH4_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH4_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH5_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH5_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH6_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH6_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH7_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH7_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH8_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH8_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH9_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH9_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH12_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH12_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_RXQ_RXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_RXQ_RXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_RPQ_RXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_RPQ_RXBD_IDX)); + } + } + + return MACSUCCESS; +} + +static u32 ss_dbgpkg(struct mac_ax_adapter *adapter, struct mac_ax_dbgpkg *val) +{ + u8 wmm, ac; + struct ss_link_info link; + u16 macid_num = adapter->hw_info->macid_num; + u8 wmm_num; + u8 ul_vld; + u32 ret; + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u16 i_u16; + struct mac_role_tbl *role; + + PLTFM_MSG_ALWAYS("%s...", __func__); + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ALWAYS("[ERR] check dmac en %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN); + if ((val32 & B_AX_MAC_FUNC_EN) == 0) { + PLTFM_MSG_ALWAYS("[ERR] B_AX_MAC_FUNC_EN=0"); + return MACSUCCESS; + } + if ((val32 & B_AX_DMAC_FUNC_EN) == 0) { + PLTFM_MSG_ALWAYS("[ERR] B_AX_DMAC_FUNC_EN=0"); + return MACSUCCESS; + } + if ((val32 & B_AX_STA_SCH_EN) == 0) { + PLTFM_MSG_ALWAYS("[ERR] B_AX_STA_SCH_EN=0"); + return MACSUCCESS; + } + val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN); + if ((val32 & B_AX_STA_SCH_CLK_EN) == 0) { + PLTFM_MSG_ALWAYS("[ERR] B_AX_STA_SCH_CLK_EN=0"); + return MACSUCCESS; + } + val32 = MAC_REG_R32(R_AX_SS_CTRL); + if ((val32 & B_AX_SS_EN) == 0) { + PLTFM_MSG_ALWAYS("[ERR] B_AX_SS_EN=0"); + return MACSUCCESS; + } + + switch (adapter->hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + wmm_num = SS_WMM_NUM_8852A; + ul_vld = SS_UL_SUPPORT_8852A; + break; + case MAC_AX_CHIP_ID_8852B: + wmm_num = SS_WMM_NUM_8852B; + ul_vld = SS_UL_SUPPORT_8852B; + break; + case MAC_AX_CHIP_ID_8852C: + wmm_num = SS_WMM_NUM_8852C; + ul_vld = SS_UL_SUPPORT_8852C; + break; + case MAC_AX_CHIP_ID_8192XB: + wmm_num = SS_WMM_NUM_8192XB; + ul_vld = SS_UL_SUPPORT_8192XB; + break; + default: + wmm_num = 0; + ul_vld = 0; + break; + } + + for (i_u16 = 0; i_u16 < macid_num; i_u16++) { + role = mac_role_srch(adapter, (u8)i_u16); + if (role) { + PLTFM_MSG_ALWAYS("[ss_tx_len] macid = %d", i_u16); + val->ss_dbg_0 |= ss_tx_len_chk(adapter, i_u16); + if (val->ss_dbg_0 & + (SS_POLL_STAT_TX_LEN | SS_POLL_OWN_TX_LEN)) + break; + } + } + + link.ul = 0; + for (wmm = 0; wmm < wmm_num; wmm++) { + link.wmm = wmm; + for (ac = 0; ac < 4; ac++) { + link.ac = ac; + val->ss_dbg_0 |= ss_link_chk(adapter, &link); + if (val->ss_dbg_0 & + (SS_POLL_STAT_LINK | SS_POLL_OWN_LINK)) + break; + } + if (val->ss_dbg_0 & (SS_POLL_STAT_LINK | SS_POLL_OWN_LINK)) + break; + } + + if (ul_vld) { + link.ul = 1; + link.wmm = 0; + link.ac = 0; + val->ss_dbg_0 |= ss_link_chk(adapter, &link); + } + + val->ss_dbg_1 |= ss_stat_chk(adapter); + ss_dbgpkg_val_parser(adapter, val); + + return MACSUCCESS; +} + +static u32 dle_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct dle_dfi_freepg_t freepg; + struct dle_dfi_quota_t quota; + struct dle_dfi_qempty_t qempty; + u32 qtaid, grpsel; + u32 qnum, qtanum, ret, val32; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] check dmac en %d\n", ret); + return ret; + } + + PLTFM_MSG_ALWAYS("R_AX_WDE_PKTBUF_CFG=0x%x\n", + MAC_REG_R32(R_AX_WDE_PKTBUF_CFG)); + PLTFM_MSG_ALWAYS("R_AX_PLE_PKTBUF_CFG=0x%x\n", + MAC_REG_R32(R_AX_PLE_PKTBUF_CFG)); + + val32 = MAC_REG_R32(R_AX_WDE_QTA0_CFG); + PLTFM_MSG_ALWAYS("[WDE][HIF]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q0_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[WDE][HIF]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q0_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_WDE_QTA1_CFG); + PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q1_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q1_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_WDE_QTA2_CFG); + PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q2_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q2_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_WDE_QTA3_CFG); + PLTFM_MSG_ALWAYS("[WDE][PKTIN]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q3_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[WDE][PKTIN]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q3_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_WDE_QTA4_CFG); + PLTFM_MSG_ALWAYS("[WDE][CPUIO]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q4_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[WDE][CPUIO]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_WDE_Q4_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA0_CFG); + PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q0_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q0_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA1_CFG); + PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q1_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q1_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA2_CFG); + PLTFM_MSG_ALWAYS("[PLE][C2H]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q2_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][C2H]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q2_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA3_CFG); + PLTFM_MSG_ALWAYS("[PLE][H2C]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q3_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][H2C]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q3_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA4_CFG); + PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q4_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q4_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA5_CFG); + PLTFM_MSG_ALWAYS("[PLE][MPDU]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q5_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][MPDU]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q5_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG); + PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q6_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q6_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG); + PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q7_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q7_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA8_CFG); + PLTFM_MSG_ALWAYS("[PLE][BBRPT]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q8_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][BBRPT]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q8_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA9_CFG); + PLTFM_MSG_ALWAYS("[PLE][WDRLS]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q9_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][WDRLS]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q9_MAX_SIZE)); + + val32 = MAC_REG_R32(R_AX_PLE_QTA10_CFG); + PLTFM_MSG_ALWAYS("[PLE][CPUIO]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q10_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][CPUIO]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q10_MAX_SIZE)); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = MAC_REG_R32(R_AX_PLE_QTA11_CFG); + PLTFM_MSG_ALWAYS("[PLE][TXRPT]min_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q11_MIN_SIZE)); + PLTFM_MSG_ALWAYS("[PLE][TXRPT]max_pgnum=0x%x\n", + GET_FIELD(val32, B_AX_PLE_Q11_MAX_SIZE)); + } + + freepg.dle_type = DLE_CTRL_TYPE_WDE; + ret = dle_dfi_freepg(adapter, &freepg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] wde dfi freepg %d\n", ret); + return ret; + } + PLTFM_MSG_ALWAYS("[WDE]free_headpg = 0x%x\n", freepg.free_headpg); + PLTFM_MSG_ALWAYS("[WDE]free_tailpg = 0x%x\n", freepg.free_tailpg); + PLTFM_MSG_ALWAYS("[WDE]pub_pgnum = 0x%x\n", freepg.pub_pgnum); + + freepg.dle_type = DLE_CTRL_TYPE_PLE; + ret = dle_dfi_freepg(adapter, &freepg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] ple dfi freepg %d\n", ret); + return ret; + } + PLTFM_MSG_ALWAYS("[PLE]free_headpg = 0x%x\n", freepg.free_headpg); + PLTFM_MSG_ALWAYS("[PLE]free_tailpg = 0x%x\n", freepg.free_tailpg); + PLTFM_MSG_ALWAYS("[PLE]pub_pgunm = 0x%x\n", freepg.pub_pgnum); + + quota.dle_type = DLE_CTRL_TYPE_WDE; + for (qtaid = 0; qtaid < WDE_QTA_NUM; qtaid++) { + quota.qtaid = qtaid; + ret = dle_dfi_quota(adapter, "a); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] wde dfi quota %d\n", ret); + return ret; + } + + switch (qtaid) { + case WDE_QTAID_HOST_IF: + PLTFM_MSG_ALWAYS("[WDE][HIF]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[WDE][HIF]use_pgnum = %d\n", + quota.use_pgnum); + break; + case WDE_QTAID_WLAN_CPU: + PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]use_pgnum = %d\n", + quota.use_pgnum); + break; + case WDE_QTAID_DATA_CPU: + PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]use_pgnum = %d\n", + quota.use_pgnum); + break; + case WDE_QTAID_PKTIN: + PLTFM_MSG_ALWAYS("[WDE][PKTIN]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[WDE][PKTIN]use_pgnum = %d\n", + quota.use_pgnum); + break; + case WDE_QTAID_CPUIO: + PLTFM_MSG_ALWAYS("[WDE][CPUIO]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[WDE][CPUIO]use_pgnum = %d\n", + quota.use_pgnum); + break; + } + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + qtanum = PLE_QTA_NUM_8852AB; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + qtanum = PLE_QTA_NUM_8852C; + } else { + PLTFM_MSG_ERR("[ERR] ple qta num not define\n"); + return MACCHIPID; + } + quota.dle_type = DLE_CTRL_TYPE_PLE; + for (qtaid = 0; qtaid < qtanum; qtaid++) { + quota.qtaid = qtaid; + ret = dle_dfi_quota(adapter, "a); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dle dfi quota %d\n", ret); + return ret; + } + + switch (qtaid) { + case PLE_QTAID_B0_TXPL: + PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_B1_TXPL: + PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_C2H: + PLTFM_MSG_ALWAYS("[PLE][C2H]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][C2H]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_H2C: + PLTFM_MSG_ALWAYS("[PLE][H2C]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][H2C]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_WLAN_CPU: + PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_MPDU: + PLTFM_MSG_ALWAYS("[PLE][MPDU]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][MPDU]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_CMAC0_RX: + PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_CMAC1_RX: + PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_BBRPT: + PLTFM_MSG_ALWAYS("[PLE][BBRPT]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][BBRPT]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_WDRLS: + PLTFM_MSG_ALWAYS("[PLE][WDRLS]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][WDRLS]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_CPUIO: + PLTFM_MSG_ALWAYS("[PLE][CPUIO]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][CPUIO]use_pgnum = %d\n", + quota.use_pgnum); + break; + case PLE_QTAID_TXRPT: + PLTFM_MSG_ALWAYS("[PLE][TXRPT]rsv_pgnum = %d\n", + quota.rsv_pgnum); + PLTFM_MSG_ALWAYS("[PLE][TXRPT]use_pgnum = %d\n", + quota.use_pgnum); + break; + default: + PLTFM_MSG_ERR("[ERR] ple invalid qtaid %d\n", qtaid); + break; + } + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + qnum = WDE_QEMPTY_NUM_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + qnum = WDE_QEMPTY_NUM_8852B; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + qnum = WDE_QEMPTY_NUM_8852C; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + qnum = WDE_QEMPTY_NUM_8192XB; + } else { + PLTFM_MSG_ERR("[ERR] wde qempty num not define\n"); + return MACCHIPID; + } + qempty.dle_type = DLE_CTRL_TYPE_WDE; + for (grpsel = 0; grpsel < qnum; grpsel++) { + qempty.grpsel = grpsel; + ret = dle_dfi_qempty(adapter, &qempty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] wde dfi qempty %d\n", ret); + return ret; + } + PLTFM_MSG_ALWAYS("[WDE][Group_%d]qempty = 0x%x\n", + grpsel, qempty.qempty); + } + + qempty.dle_type = DLE_CTRL_TYPE_PLE; + for (grpsel = 0; grpsel < PLE_QEMPTY_NUM; grpsel++) { + qempty.grpsel = grpsel; + ret = dle_dfi_qempty(adapter, &qempty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] ple dfi qempty %d\n", ret); + return ret; + } + PLTFM_MSG_ALWAYS("[PLE][Group_%d]qempty = 0x%x\n", + grpsel, qempty.qempty); + } + + return MACSUCCESS; +} + +static u8 chk_dle_dfi_valid(struct mac_ax_adapter *adapter, u32 dbg_sel) +{ + if ((check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) == MACSUCCESS) && + dbg_sel <= MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY) + return 1; + + return 0; +} + +u32 dle_dfi_sel(struct mac_ax_adapter *adapter, + struct mac_ax_dle_dfi_info **info, + u32 *target, u32 sel) +{ + switch (sel) { + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG: + *info = &dle_dfi_wde_bufmgn_freepg; + *target = DLE_DFI_TYPE_FREEPG; + PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN FREEPG:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA: + *info = &dle_dfi_wde_bufmgn_quota; + *target = DLE_DFI_TYPE_QUOTA; + PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN QUOTA:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT: + *info = &dle_dfi_wde_bufmgn_pagellt; + *target = DLE_DFI_TYPE_PAGELLT; + PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN PAGELLT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO: + *info = &dle_dfi_wde_bufmgn_pktinfo; + *target = DLE_DFI_TYPE_PKTINFO; + PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN PKTINFO:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT: + *info = &dle_dfi_wde_quemgn_prepkt; + *target = DLE_DFI_TYPE_PREPKTLLT; + PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN PREPKT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT: + *info = &dle_dfi_wde_quemgn_nxtpkt; + *target = DLE_DFI_TYPE_NXTPKTLLT; + PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN NXTPKT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL: + *info = &dle_dfi_wde_quemgn_qlnktbl; + *target = DLE_DFI_TYPE_QLNKTBL; + PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN QLNKTBL:\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY: + *info = &dle_dfi_wde_quemgn_qempty; + *target = DLE_DFI_TYPE_QEMPTY; + PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN QEMPTY:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG: + *info = &dle_dfi_ple_bufmgn_freepg; + *target = DLE_DFI_TYPE_FREEPG; + PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN FREEPG:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA: + *info = &dle_dfi_ple_bufmgn_quota; + *target = DLE_DFI_TYPE_QUOTA; + PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN QUOTA:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT: + *info = &dle_dfi_ple_bufmgn_pagellt; + *target = DLE_DFI_TYPE_PAGELLT; + PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN PAGELLT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO: + *info = &dle_dfi_ple_bufmgn_pktinfo; + *target = DLE_DFI_TYPE_PKTINFO; + PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN PKTINFO:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT: + *info = &dle_dfi_ple_quemgn_prepkt; + *target = DLE_DFI_TYPE_PREPKTLLT; + PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN PREPKT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT: + *info = &dle_dfi_ple_quemgn_nxtpkt; + *target = DLE_DFI_TYPE_NXTPKTLLT; + PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN NXTPKT:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL: + *info = &dle_dfi_ple_quemgn_qlnktbl; + *target = DLE_DFI_TYPE_QLNKTBL; + PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN QLNKTBL:\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY: + *info = &dle_dfi_ple_quemgn_qempty; + *target = DLE_DFI_TYPE_QEMPTY; + PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN QEMPTY:\n"); + break; + default: + PLTFM_MSG_ALWAYS("dle dfi select err\n"); + *info = NULL; + return MACDBGPORTSEL; + } + + return MACSUCCESS; +} + +static u32 dle_dfi_dump(struct mac_ax_adapter *adapter, u32 sel) +{ + struct mac_ax_dle_dfi_info *info; + struct dle_dfi_ctrl_t ctrl; + u32 ret, i; + + ret = dle_dfi_sel(adapter, &info, &ctrl.target, sel); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dle dfi sel %d %d\n", sel, ret); + return ret; + } + + if (sel <= MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY) { + ctrl.type = DLE_CTRL_TYPE_WDE; + } else if (sel >= MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG && + sel <= MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY) { + ctrl.type = DLE_CTRL_TYPE_PLE; + } else { + PLTFM_MSG_ERR("[ERR]unknown dle dfi sel-2 %d\n", sel); + return MACFUNCINPUT; + } + + switch (sel) { + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG: + PLTFM_MSG_ALWAYS("WDE_BUFMGN_FREEPG\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA: + PLTFM_MSG_ALWAYS("WDE_BUFMGN_QUOTA\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT: + PLTFM_MSG_ALWAYS("WDE_BUFMGN_PAGELLT\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO: + PLTFM_MSG_ALWAYS("WDE_BUFMGN_PKTINFO\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT: + PLTFM_MSG_ALWAYS("WDE_QUEMGN_PREPKT\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT: + PLTFM_MSG_ALWAYS("WDE_QUEMGN_NXTPKT\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL: + PLTFM_MSG_ALWAYS("WDE_QUEMGN_QLNKTBL\n"); + break; + case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY: + PLTFM_MSG_ALWAYS("WDE_QUEMGN_QEMPTY\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG: + PLTFM_MSG_ALWAYS("PLE_BUFMGN_FREEPG\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA: + PLTFM_MSG_ALWAYS("PLE_BUFMGN_QUOTA\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT: + PLTFM_MSG_ALWAYS("PLE_BUFMGN_PAGELLT\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO: + PLTFM_MSG_ALWAYS("PLE_BUFMGN_PKTINFO\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT: + PLTFM_MSG_ALWAYS("PLE_QUEMGN_PREPKT\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT: + PLTFM_MSG_ALWAYS("PLE_QUEMGN_NXTPKT\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL: + PLTFM_MSG_ALWAYS("PLE_QUEMGN_QLNKTBL\n"); + break; + case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY: + PLTFM_MSG_ALWAYS("PLE_QUEMGN_QEMPTY\n"); + break; + default: + break; + } + + for (i = info->srt; i <= info->end; i += info->inc_num) { + ctrl.addr = i; + ret = dle_dfi_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle dfi ctrl %d\n", ret); + return ret; + } + PLTFM_MSG_ALWAYS("trg %d addr 0x%X: 0x%X\n", + ctrl.target, ctrl.addr, ctrl.out_data); + } + + return MACSUCCESS; +} + +static u32 tx_cnt_dump(struct mac_ax_adapter *adapter, u8 band, u32 loop_num) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, reg, val32, i; + u8 idx; + u32 prev_cnt[TMAC_TX_CNT_NUM]; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret); + return ret; + } + + PLTFM_MEMSET(prev_cnt, 0, sizeof(prev_cnt)); + + reg = band == MAC_AX_BAND_1 ? R_AX_TX_PPDU_CNT_C1 : R_AX_TX_PPDU_CNT; + for (i = 0; i < loop_num; i++) { + for (idx = 0; idx < TMAC_TX_CNT_NUM; idx++) { + MAC_REG_W8(reg, idx); + PLTFM_DELAY_US(TRX_CNT_READ_DLY_US); + val32 = GET_FIELD(MAC_REG_R32(reg), B_AX_TX_PPDU_CNT); + if (i == 0 || val32 != prev_cnt[idx]) + PLTFM_MSG_ALWAYS("B%d TX_PPDU_CNT[%d]-%d=0x%x\n", + band, idx, i, val32); + prev_cnt[idx] = val32; + } + PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US); + } + + return MACSUCCESS; +} + +static u32 rx_cnt_dump(struct mac_ax_adapter *adapter, u8 band, u32 loop_num) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, reg, val32, i; + u8 idx; + u32 prev_cnt[RMAC_RX_CNT_NUM]; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret); + return ret; + } + + PLTFM_MEMSET(prev_cnt, 0, sizeof(prev_cnt)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_RX_DBG_CNT_SEL_C1 : R_AX_RX_DBG_CNT_SEL; + for (i = 0; i < loop_num; i++) { + for (idx = 0; idx < RMAC_RX_CNT_NUM; idx++) { + MAC_REG_W8(reg, idx); + PLTFM_DELAY_US(TRX_CNT_READ_DLY_US); + val32 = GET_FIELD(MAC_REG_R32(reg), B_AX_RX_DBG_CNT); + if (i == 0 || val32 != prev_cnt[idx]) + PLTFM_MSG_ALWAYS("B%d RX_CNT[%d]-%d=0x%x\n", + band, idx, i, val32); + prev_cnt[idx] = val32; + } + PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US); + } + + return MACSUCCESS; +} + +static u32 dmac_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + + /* Func/Clk */ + PLTFM_MSG_ALWAYS("R_AX_DMAC_FUNC_EN=0x%x\n", + MAC_REG_R32(R_AX_DMAC_FUNC_EN)); + PLTFM_MSG_ALWAYS("R_AX_DMAC_CLK_EN=0x%x\n", + MAC_REG_R32(R_AX_DMAC_CLK_EN)); + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ALWAYS("[ERR] check dmac en %d\n", ret); + return ret; + } + + /* Common */ + PLTFM_MSG_ALWAYS("R_AX_SER_DBG_INFO=0x%x\n", + MAC_REG_R32(R_AX_SER_DBG_INFO)); + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY0)); + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY1)); + /* Error IMR/ISR & Flag */ + PLTFM_MSG_ALWAYS("R_AX_DMAC_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_DMAC_ERR_IMR)); + PLTFM_MSG_ALWAYS("R_AX_DMAC_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_DMAC_ERR_ISR)); + PLTFM_MSG_ALWAYS("[0]R_AX_WDRLS_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_WDRLS_ERR_IMR)); + PLTFM_MSG_ALWAYS("[0]R_AX_WDRLS_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_WDRLS_ERR_ISR)); + PLTFM_MSG_ALWAYS("[1]R_AX_SEC_ERR_IMR_ISR=0x%x\n", + MAC_REG_R32(R_AX_SEC_DEBUG)); + PLTFM_MSG_ALWAYS("[2.1]R_AX_MPDU_TX_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR)); + PLTFM_MSG_ALWAYS("[2.1]R_AX_MPDU_TX_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR)); + PLTFM_MSG_ALWAYS("[2.2]R_AX_MPDU_RX_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR)); + PLTFM_MSG_ALWAYS("[2.2]R_AX_MPDU_RX_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_MPDU_RX_ERR_ISR)); + PLTFM_MSG_ALWAYS("[3]R_AX_STA_SCHEDULER_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR)); + PLTFM_MSG_ALWAYS("[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_ISR)); + PLTFM_MSG_ALWAYS("[4]R_AX_WDE_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_WDE_ERR_IMR)); + PLTFM_MSG_ALWAYS("[4]R_AX_WDE_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_WDE_ERR_ISR)); + PLTFM_MSG_ALWAYS("[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%x\n", + MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR)); + PLTFM_MSG_ALWAYS("[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%x\n", + MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); + PLTFM_MSG_ALWAYS("[6]R_AX_PLE_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_PLE_ERR_IMR)); + PLTFM_MSG_ALWAYS("[6]R_AX_PLE_ERR_FLAG_ISR=0x%x\n", + MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR)); + PLTFM_MSG_ALWAYS("[7]R_AX_PKTIN_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_PKTIN_ERR_IMR)); + PLTFM_MSG_ALWAYS("[7]R_AX_PKTIN_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_PKTIN_ERR_ISR)); + PLTFM_MSG_ALWAYS("[8.1]R_AX_OTHER_DISPATCHER_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ALWAYS("[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_ISR)); + PLTFM_MSG_ALWAYS("[8.2]R_AX_HOST_DISPATCHER_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ALWAYS("[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_ISR)); + PLTFM_MSG_ALWAYS("[8.3]R_AX_CPU_DISPATCHER_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ALWAYS("[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_ISR)); + PLTFM_MSG_ALWAYS("[10]R_AX_CPUIO_ERR_IMR=0x%x\n", + MAC_REG_R32(R_AX_CPUIO_ERR_IMR)); + PLTFM_MSG_ALWAYS("[10]R_AX_CPUIO_ERR_ISR=0x%x\n", + MAC_REG_R32(R_AX_CPUIO_ERR_ISR)); + PLTFM_MSG_ALWAYS("[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%x\n", + MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR)); + PLTFM_MSG_ALWAYS("[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%x\n", + MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); + PLTFM_MSG_ALWAYS("[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%x\n", + MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR_ISR)); + PLTFM_MSG_ALWAYS("[11.4]R_AX_LA_ERRFLAG=0x%x\n", + MAC_REG_R32(R_AX_LA_ERRFLAG)); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + PLTFM_MSG_ALWAYS("R_AX_HCI_FC_ERR_FLAG=0x%x\n", + MAC_REG_R32(R_AX_HCI_FC_ERR_FLAG_V1)); + } else { + PLTFM_MSG_ALWAYS("R_AX_HCI_FC_ERR_FLAG=0x%x\n", + MAC_REG_R32(R_AX_HCI_FC_ERR_FLAG)); + } + /* Dispatcher */ + PLTFM_MSG_ALWAYS("R_AX_DISPATCHER_GLOBAL_SETTING_0=0x%x\n", + MAC_REG_R32(R_AX_DISPATCHER_GLOBAL_SETTING_0)); + PLTFM_MSG_ALWAYS("R_AX_TX_ADDRESS_INFO_MODE_SETTING=0x%x\n", + MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING)); + PLTFM_MSG_ALWAYS("R_AX_CPU_PORT_DEBUG_SETTING=0x%x\n", + MAC_REG_R32(R_AX_CPU_PORT_DEBUG_SETTING)); + PLTFM_MSG_ALWAYS("R_AX_HDP_DBG_INFO_4=0x%x\n", + MAC_REG_R32(R_AX_HDP_DBG_INFO_4)); + /* PKTIN */ + PLTFM_MSG_ALWAYS("R_AX_PKTIN_SETTING=0x%x\n", + MAC_REG_R32(R_AX_PKTIN_SETTING)); + /* MPDU Proc */ + PLTFM_MSG_ALWAYS("R_AX_TX_PTK_CNT=0x%x\n", + MAC_REG_R32(R_AX_TX_PTK_CNT)); + PLTFM_MSG_ALWAYS("R_AX_MPDU_TX_ERRFLAG=0x%x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR)); + PLTFM_MSG_ALWAYS("R_AX_MPDU_TX_ERRFLAG_MSK=0x%x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR)); + PLTFM_MSG_ALWAYS("R_AX_MPDU_RX_PKTCNT=0x%x\n", + MAC_REG_R32(R_AX_MPDU_RX_PKTCNT)); + PLTFM_MSG_ALWAYS("R_AX_MPDU_DROP_PKTCNT=0x%x\n", + MAC_REG_R32(R_AX_MPDU_DROP_PKTCNT)); + /* STA SCH */ + PLTFM_MSG_ALWAYS("R_AX_SS_CTRL=0x%x\n", MAC_REG_R32(R_AX_SS_CTRL)); + PLTFM_MSG_ALWAYS("R_AX_SS_DBG_0=0x%x\n", MAC_REG_R32(R_AX_SS_DBG_0)); + PLTFM_MSG_ALWAYS("R_AX_SS_DBG_1=0x%x\n", MAC_REG_R32(R_AX_SS_DBG_1)); + PLTFM_MSG_ALWAYS("R_AX_SS_DBG_2=0x%x\n", MAC_REG_R32(R_AX_SS_DBG_2)); + PLTFM_MSG_ALWAYS("R_AX_SS_DBG_3=0x%x\n", MAC_REG_R32(R_AX_SS_DBG_3)); + + return MACSUCCESS; +} + +static u32 cmac_dbg_dump(struct mac_ax_adapter *adapter, enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, reg; + + if (band == MAC_AX_BAND_1 && is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + return MACSUCCESS; + + adapter->sm.l2_st = MAC_AX_L2_DIS; + /* Func/Clk band 0 */ + if (band == MAC_AX_BAND_0) { + reg = R_AX_CMAC_FUNC_EN; + PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_FUNC_EN=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = R_AX_CK_EN; + PLTFM_MSG_ALWAYS("B%d R_AX_CK_EN=0x%x\n", band, + MAC_REG_R32(reg)); + } + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret); + return ret; + } + + /* Func/Clk band 1 */ + if (band == MAC_AX_BAND_1) { + reg = R_AX_CMAC_FUNC_EN_C1; + PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_FUNC_EN=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = R_AX_CK_EN_C1; + PLTFM_MSG_ALWAYS("B%d R_AX_CK_EN=0x%x\n", band, + MAC_REG_R32(reg)); + } + + /* Error IMR/ISR & Flag */ + reg = band == MAC_AX_BAND_1 ? R_AX_CMAC_ERR_IMR_C1 : R_AX_CMAC_ERR_IMR; + PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_ERR_IMR=0x%x\n", band, MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? R_AX_CMAC_ERR_ISR_C1 : R_AX_CMAC_ERR_ISR; + PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_ERR_ISR=0x%x\n", band, MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_SCHEDULE_ERR_IMR_C1 : R_AX_SCHEDULE_ERR_IMR; + PLTFM_MSG_ALWAYS("[0]B%d R_AX_SCHEDULE_ERR_IMR=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_SCHEDULE_ERR_ISR_C1 : R_AX_SCHEDULE_ERR_ISR; + PLTFM_MSG_ALWAYS("[0]B%d R_AX_SCHEDULE_ERR_ISR=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? R_AX_PTCL_IMR0_C1 : R_AX_PTCL_IMR0; + PLTFM_MSG_ALWAYS("[1]B%d R_AX_PTCL_IMR0=0x%x\n", band, MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? R_AX_PTCL_ISR0_C1 : R_AX_PTCL_ISR0; + PLTFM_MSG_ALWAYS("[1]B%d R_AX_PTCL_ISR0=0x%x\n", band, MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? R_AX_DLE_CTRL_C1 : R_AX_DLE_CTRL; + PLTFM_MSG_ALWAYS("[3]B%d R_AX_DLE_CTRL=0x%x\n", band, MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_PHYINFO_ERR_ISR_C1 : R_AX_PHYINFO_ERR_ISR; + PLTFM_MSG_ALWAYS("[4]B%d R_AX_PHYINFO_ERR_ISR=0x%x\n", band, + MAC_REG_R8(reg)); + + reg = band == MAC_AX_BAND_1 ? R_AX_TXPWR_IMR_C1 : R_AX_TXPWR_IMR; + PLTFM_MSG_ALWAYS("[5]B%d R_AX_TXPWR_IMR=0x%x\n", band, MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? R_AX_TXPWR_ISR_C1 : R_AX_TXPWR_ISR; + PLTFM_MSG_ALWAYS("[5]B%d R_AX_TXPWR_ISR=0x%x\n", band, MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? R_AX_RMAC_ERR_ISR_C1 : R_AX_RMAC_ERR_ISR; + PLTFM_MSG_ALWAYS("[6]B%d R_AX_RMAC_ERR_ISR=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_TMAC_ERR_IMR_ISR_C1 : R_AX_TMAC_ERR_IMR_ISR; + PLTFM_MSG_ALWAYS("[7]B%d R_AX_TMAC_ERR_IMR_ISR=0x%x\n", band, + MAC_REG_R32(reg)); + + /* CMAC DMA */ + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_ERR_FLG_0_C1 : R_AX_RXDMA_ERR_FLG_0; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_ERR_FLG_0=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_ERR_FLG_1_C1 : R_AX_RXDMA_ERR_FLG_1; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_ERR_FLG_1=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_PKT_INFO_0_C1 : R_AX_RXDMA_PKT_INFO_0; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_0=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_PKT_INFO_1_C1 : R_AX_RXDMA_PKT_INFO_1; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_1=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_PKT_INFO_2_C1 : R_AX_RXDMA_PKT_INFO_2; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_2=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_PKT_INFO_3_C1 : R_AX_RXDMA_PKT_INFO_3; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_3=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_RXDMA_PKT_INFO_4_C1 : R_AX_RXDMA_PKT_INFO_4; + PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_4=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_FIFO_INFO_0_C1 : R_AX_TXDMA_FIFO_INFO_0; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_0=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_FIFO_INFO_1_C1 : R_AX_TXDMA_FIFO_INFO_1; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_1=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_FIFO_INFO_2_C1 : R_AX_TXDMA_FIFO_INFO_2; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_2=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? R_AX_TXDMA_DBG_C1 : R_AX_TXDMA_DBG; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_DBG=0x%x\n", band, MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_RU_INFO_0_C1 : R_AX_TXDMA_RU_INFO_0; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_0=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_RU_INFO_1_C1 : R_AX_TXDMA_RU_INFO_1; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_1=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_RU_INFO_2_C1 : R_AX_TXDMA_RU_INFO_2; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_2=0x%x\n", band, + MAC_REG_R32(reg)); + reg = band == MAC_AX_BAND_1 ? + R_AX_TXDMA_RU_INFO_3_C1 : R_AX_TXDMA_RU_INFO_3; + PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_3=0x%x\n", band, + MAC_REG_R32(reg)); + + /* TMAC */ + reg = band == MAC_AX_BAND_1 ? + R_AX_MACTX_DBG_SEL_CNT_C1 : R_AX_MACTX_DBG_SEL_CNT; + PLTFM_MSG_ALWAYS("B%d R_AX_MACTX_DBG_SEL_CNT=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_WMAC_TX_CTRL_DEBUG_C1 : R_AX_WMAC_TX_CTRL_DEBUG; + PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_CTRL_DEBUG=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_WMAC_TX_INFO0_DEBUG_C1 : R_AX_WMAC_TX_INFO0_DEBUG; + PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_INFO0_DEBUG=0x%x\n", band, + MAC_REG_R32(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_WMAC_TX_INFO1_DEBUG_C1 : R_AX_WMAC_TX_INFO1_DEBUG; + PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_INFO1_DEBUG=0x%x\n", band, + MAC_REG_R32(reg)); + + /* TMAC TX COUNTER */ + ret = tx_cnt_dump(adapter, band, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ALWAYS("[ERR]tx cnt dump err %d\n", ret); + + /* TRX PTCL */ + reg = band == MAC_AX_BAND_1 ? + R_AX_MAC_LOOPBACK_COUNT_C1 : R_AX_MAC_LOOPBACK_COUNT; + PLTFM_MSG_ALWAYS("B%d R_AX_MAC_LOOPBACK_COUNT=0x%x\n", band, + MAC_REG_R32(reg)); + + /* RMAC */ + reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR; + PLTFM_MSG_ALWAYS("B%d R_AX_RCR=0x%x\n", band, MAC_REG_R16(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL; + PLTFM_MSG_ALWAYS("B%d R_AX_DLK_PROTECT_CTL=0x%x\n", band, MAC_REG_R16(reg)); + + reg = band == MAC_AX_BAND_1 ? R_AX_PPDU_STAT_C1 : R_AX_PPDU_STAT; + PLTFM_MSG_ALWAYS("B%d R_AX_PPDU_STAT=0x%x\n", band, MAC_REG_R16(reg)); + + reg = band == MAC_AX_BAND_1 ? + R_AX_PPDU_STAT_ERR_C1 : R_AX_PPDU_STAT_ERR; + PLTFM_MSG_ALWAYS("B%d R_AX_PPDU_STAT_ERR=0x%x\n", band, MAC_REG_R16(reg)); + + /* RMAC RX COUNTER */ + ret = rx_cnt_dump(adapter, band, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ALWAYS("[ERR]rx cnt dump err %d\n", ret); + + adapter->sm.l2_st = MAC_AX_L2_EN; + + return MACSUCCESS; +} + +static u32 tx_dbg_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + u32 i; + + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_0=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_0)); + + PLTFM_MSG_ALWAYS("R_AX_MBSSID_DROP_0=0x%x\n", + MAC_REG_R32(R_AX_MBSSID_DROP_0)); + + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_0=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_0)); + + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_1=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_1)); + + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_2=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_2)); + + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_3=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_3)); + + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_0=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_0)); + + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_1=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_1)); + + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_2=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_2)); + + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_3=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_3)); + + PLTFM_MSG_ALWAYS("R_AX_CTN_TXEN=0x%x\n", + MAC_REG_R32(R_AX_CTN_TXEN)); + + PLTFM_MSG_ALWAYS("R_AX_PTCL_COMMON_SETTING_0=0x%x\n", + MAC_REG_R32(R_AX_PTCL_COMMON_SETTING_0)); + + PLTFM_MSG_ALWAYS("R_AX_MAC_LOOPBACK=0x%x\n", + MAC_REG_R32(R_AX_MAC_LOOPBACK)); + + ret = dbg_port_dump(adapter, MAC_AX_DBG_PORT_SEL_PTCL_C0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("PTCL_C0 dbg port dump %d\n", ret); + + ret = dbg_port_dump(adapter, MAC_AX_DBG_PORT_SEL_SCH_C0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("SCH_C0 dbg port dump %d\n", ret); + + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY0)); + + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY1)); + + for (i = 0; i < TRX_CNT_REPT_CNT; i++) { + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTF=0x%x\n", + MAC_REG_R32(R_AX_PCIE_MIO_INTF)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTD=0x%x\n", + MAC_REG_R32(R_AX_PCIE_MIO_INTD)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_INIT_CFG1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_INIT_CFG1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_STOP1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DMA_STOP1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_BUSY1=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DMA_BUSY1)); + + PLTFM_MSG_ALWAYS("R_AX_PCIE_DBG_CTRL=0x%x\n", + MAC_REG_R32(R_AX_PCIE_DBG_CTRL)); + + PLTFM_MSG_ALWAYS("R_AX_DBG_ERR_FLAG=0x%x\n", + MAC_REG_R32(R_AX_DBG_ERR_FLAG)); + + PLTFM_MSG_ALWAYS("R_AX_LBC_WATCHDOG=0x%x\n", + MAC_REG_R32(R_AX_LBC_WATCHDOG)); + + PLTFM_MSG_ALWAYS("R_AX_ACH0_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH0_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH1_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH1_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH2_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH2_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH3_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH3_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH4_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH4_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH5_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH5_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH6_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH6_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_ACH7_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_ACH7_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH8_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH8_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH9_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH9_TXBD_IDX)); + + PLTFM_MSG_ALWAYS("R_AX_CH12_TXBD_IDX=0x%x\n", + MAC_REG_R32(R_AX_CH12_TXBD_IDX)); + } + + /* TMAC TX COUNTER */ + ret = tx_cnt_dump(adapter, MAC_AX_BAND_0, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ALWAYS("[ERR]tx cnt dump err %d\n", ret); + + pltfm_dbg_dump(adapter); + + PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US); + } + + return MACSUCCESS; +} + +u8 is_dbg_port_not_valid(struct mac_ax_adapter *adapter, u32 dbg_sel) +{ + if (adapter->hw_info->intf != MAC_AX_INTF_PCIE && + dbg_sel >= MAC_AX_DBG_PORT_SEL_PCIE_TXDMA && + dbg_sel <= MAC_AX_DBG_PORT_SEL_PCIE_EMAC18) + return 1; + if (adapter->hw_info->intf != MAC_AX_INTF_USB && + dbg_sel >= MAC_AX_DBG_PORT_SEL_USB2_PHY && + dbg_sel <= MAC_AX_DBG_PORT_SEL_USB2_BT) + return 1; + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + dbg_sel >= MAC_AX_DBG_PORT_SEL_PTCL_C1 && + dbg_sel <= MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1) + return 1; + if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS && + dbg_sel >= MAC_AX_DBG_PORT_SEL_PKTINFO && + dbg_sel <= MAC_AX_DBG_PORT_SEL_PKTINFO) + return 1; + if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS && + dbg_sel >= MAC_AX_DBG_PORT_SEL_WDRLS && + dbg_sel <= MAC_AX_DBG_PORT_SEL_WDRLS) + return 1; + if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS && + dbg_sel >= MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0 && + dbg_sel <= MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4) + return 1; + if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS && + dbg_sel >= MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0 && + dbg_sel <= MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL) + return 1; + if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL) != MACSUCCESS && + dbg_sel <= MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0) + return 1; + if (check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL) != MACSUCCESS && + dbg_sel >= MAC_AX_DBG_PORT_SEL_PTCL_C1 && + dbg_sel <= MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1) + return 1; + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY && + dbg_sel >= MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL && + dbg_sel <= MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL) { + return 1; + } + + return 0; +} + +static u32 mac_dle_status_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY0)); + PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n", + MAC_REG_R32(R_AX_DLE_EMPTY1)); + + return MACSUCCESS; +} + +static u32 mac_hci_flow_ctrl_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ALWAYS("R_AX_HDP_DBG_INFO_4=0x%x\n", + MAC_REG_R32(R_AX_HDP_DBG_INFO_4)); + + return MACSUCCESS; +} + +static u32 mac_quota_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + /* quota */ +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + PLTFM_MSG_ALWAYS("R_AX_ACH0_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH0_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH1_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH1_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH2_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH2_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH3_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH3_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH4_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH4_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH5_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH5_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH6_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH6_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_ACH7_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_ACH7_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_CH8_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_CH8_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_CH9_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_CH9_PAGE_INFO)); +#if MAC_AX_8852A_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + PLTFM_MSG_ALWAYS("R_AX_CH10_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_CH10_PAGE_INFO)); + PLTFM_MSG_ALWAYS("R_AX_CH11_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_CH11_PAGE_INFO)); + } +#endif + PLTFM_MSG_ALWAYS("R_AX_CH12_PAGE_INFO=0x%x\n", + MAC_REG_R32(R_AX_CH12_PAGE_INFO)); + } +#endif + return MACSUCCESS; +} + +static u32 mac_tx_status_dump(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 idx = 0, ret = 0, cmac0_en = 0, cmac1_en = 0; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ALWAYS("[ERR] check dmac en %d\n", ret); + return ret; + } + + /* Dispatcher */ + PLTFM_MSG_ALWAYS("R_AX_DMAC_MACID_DROP_0=0x%x\n", + MAC_REG_R32(R_AX_DMAC_MACID_DROP_0)); + PLTFM_MSG_ALWAYS("R_AX_DMAC_MACID_DROP_1=0x%x\n", + MAC_REG_R32(R_AX_DMAC_MACID_DROP_1)); + PLTFM_MSG_ALWAYS("R_AX_DMAC_MACID_DROP_2=0x%x\n", + MAC_REG_R32(R_AX_DMAC_MACID_DROP_2)); + PLTFM_MSG_ALWAYS("R_AX_DMAC_MACID_DROP_3=0x%x\n", + MAC_REG_R32(R_AX_DMAC_MACID_DROP_3)); + +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT + if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) && + !is_cv(adapter, CAV)) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + cmac0_en = check_mac_en(adapter, 0, MAC_AX_CMAC_SEL); + if (cmac0_en == MACSUCCESS) { + /* MGQ */ + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_0=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_0)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_1=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_1)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_2=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_2)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_3=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_3)); + /* HIQ */ + PLTFM_MSG_ALWAYS("R_AX_MBSSID_DROP_0=0x%x\n", + MAC_REG_R32(R_AX_MBSSID_DROP_0)); + /* lifetime, PTCL TX mode */ + PLTFM_MSG_ALWAYS("R_AX_PTCL_COMMON_SETTING_0=0x%x\n", + MAC_REG_R32(R_AX_PTCL_COMMON_SETTING_0)); + } + cmac1_en = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL); + if (cmac1_en == MACSUCCESS) { + /* MGQ */ + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_0_C1=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_0_C1)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_1_C1=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_1_C1)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_2_C1=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_2_C1)); + PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_3_C1=0x%x\n", + MAC_REG_R32(R_AX_CMAC_MACID_DROP_3_C1)); + /* HIQ */ + PLTFM_MSG_ALWAYS("R_AX_MBSSID_DROP_0_C1=0x%x\n", + MAC_REG_R32(R_AX_MBSSID_DROP_0_C1)); + /* lifetime, PTCL TX mode */ + PLTFM_MSG_ALWAYS("R_AX_PTCL_COMMON_SETTING_0_C1=0x%x\n", + MAC_REG_R32(R_AX_PTCL_COMMON_SETTING_0_C1)); + } + } +#endif + + /* Sleep */ + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_0=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_0)); + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_1=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_1)); + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_2=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_2)); + PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_3=0x%x\n", + MAC_REG_R32(R_AX_MACID_SLEEP_3)); + + /* Pause */ + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_0=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_0)); + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_1=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_1)); + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_2=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_2)); + PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_3=0x%x\n", + MAC_REG_R32(R_AX_SS_MACID_PAUSE_3)); + + if (cmac0_en == MACSUCCESS) { + /* Scheduler Tx_en */ + PLTFM_MSG_ALWAYS("R_AX_CTN_TXEN=0x%x\n", + MAC_REG_R32(R_AX_CTN_TXEN)); + /* Loopback mode */ + PLTFM_MSG_ALWAYS("R_AX_MAC_LOOPBACK=0x%x\n", + MAC_REG_R32(R_AX_MAC_LOOPBACK)); + } + + if (cmac1_en == MACSUCCESS) { + /* Scheduler Tx_en */ + PLTFM_MSG_ALWAYS("R_AX_CTN_TXEN_C1=0x%x\n", + MAC_REG_R32(R_AX_CTN_TXEN_C1)); + /* Loopback mode */ + PLTFM_MSG_ALWAYS("R_AX_MAC_LOOPBACK_C1=0x%x\n", + MAC_REG_R32(R_AX_MAC_LOOPBACK_C1)); + } + + /* per MACID WD empty */ + for (idx = 0; idx < 4; idx++) { + MAC_REG_W32(R_AX_WDE_Q_STATUS_CFG, idx); + PLTFM_MSG_ALWAYS("R_AX_WDE_Q_STATUS_VAL=0x%x\n", + MAC_REG_R32(R_AX_WDE_Q_STATUS_VAL)); + } + + mac_quota_dump(adapter); + + for (idx = 0; idx < MAC_DBG_DMP_CNT; idx++) { + /* Polluted */ + PLTFM_MSG_ALWAYS("R_AX_CCA_CONTROL=0x%x\n", + MAC_REG_R32(R_AX_CCA_CONTROL)); + PLTFM_MSG_ALWAYS("R_AX_BT_PLT=0x%x\n", + MAC_REG_R32(R_AX_BT_PLT)); + + /* FW Tx report counter */ + PLTFM_MSG_ALWAYS("R_AX_UDM0=0x%x\n", + MAC_REG_R32(R_AX_UDM0)); + + pltfm_dbg_dump(adapter); + + /* FW CMAC error counter */ + if (mac_io_chk_access(adapter, R_AX_SER_DBG_INFO) == MACSUCCESS) + PLTFM_MSG_ALWAYS("R_AX_SER_DBG_INFO = 0x%x\n", + MAC_REG_R32(R_AX_SER_DBG_INFO)); + PLTFM_DELAY_US(MAC_DBG_DUMP_DLY_US); + } + + return MACSUCCESS; +} + +static u32 ptcl_status_dump(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, reg, val32; + u8 idx; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret); + return ret; + } + + reg = band == MAC_AX_BAND_1 ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL; + + for (idx = 0; idx < PTCL_ST_NUM; idx++) { + val32 = MAC_REG_R32(reg); + PLTFM_MSG_ALWAYS("B%d PTCL_TX_CTN_SEL[%d]=0x%x\n", + band, idx, val32); + PLTFM_DELAY_US(TRX_CNT_READ_DLY_US); + } + + return MACSUCCESS; +} + +static u32 tx_flow_ptcl_dbg_port(struct mac_ax_adapter *adapter, u8 band) +{ + u8 i; + u16 val16; + u32 ret = MACSUCCESS; + struct mac_ax_dbg_port_info info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ALWAYS("[ERR] check cmac en %d\n", ret); + return ret; + } + info = band == MAC_AX_BAND_1 ? dbg_port_ptcl_c1 : dbg_port_ptcl_c0; + PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock); + adapter->hw_info->dbg_port_cnt++; + if (adapter->hw_info->dbg_port_cnt != 1) { + PLTFM_MSG_ERR("[ERR]dbg port sel %x lock cnt %d\n", + info.sel_addr, adapter->hw_info->dbg_port_cnt); + ret = MACCMP; + goto err; + } + + val16 = MAC_REG_R16(info.sel_addr); + val16 |= B_AX_PTCL_DBG_EN; + MAC_REG_W16(info.sel_addr, val16); + + info.srt = PTCL_SEL_FSM_0; + info.end = PTCL_SEL_FSM_1; + + PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info.sel_addr); + PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info.rd_addr); + + info.srt = PTCL_SEL_PHY_DBG; + info.end = PTCL_SEL_PHY_DBG; + for (i = 0; i < PTCL_DBG_DMP_CNT; i++) + print_dbg_port(adapter, &info); + +err: + adapter->hw_info->dbg_port_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock); + return ret; +} + +static u32 tx_flow_sch_dbg_port(struct mac_ax_adapter *adapter, u8 band) +{ + u8 i; + u32 val32, ret = MACSUCCESS; + struct mac_ax_dbg_port_info info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ALWAYS("[ERR] check cmac en %d\n", ret); + return ret; + } + + info = band == MAC_AX_BAND_1 ? dbg_port_sch_c1 : dbg_port_sch_c0; + PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock); + adapter->hw_info->dbg_port_cnt++; + if (adapter->hw_info->dbg_port_cnt != 1) { + PLTFM_MSG_ERR("[ERR]dbg port sel %x lock cnt %d\n", + info.sel_addr, adapter->hw_info->dbg_port_cnt); + ret = MACCMP; + goto err; + } + + val32 = MAC_REG_R32(info.sel_addr); + val32 |= B_AX_SCH_DBG_EN; + MAC_REG_W32(info.sel_addr, val32); + + info.srt = SCH_SEL_PREBKF_DBG_1; + info.end = SCH_SEL_EDCA_DBG; + + PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info.sel_addr); + PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info.rd_addr); + + for (i = 0; i <= SCH_DBG_DMP_CNT; i++) + print_dbg_port(adapter, &info); + +err: + adapter->hw_info->dbg_port_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock); + return ret; +} + +static u32 mac_tx_flow_dbg(struct mac_ax_adapter *adapter) +{ + u32 ret; + + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + /* commom check */ + ret = mac_tx_status_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]common check %d\n", ret); + + /* dump TMAC tr counter */ + ret = tx_cnt_dump(adapter, MAC_AX_BAND_0, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 tx cnt dump err %d\n", ret); + + ret = tx_cnt_dump(adapter, MAC_AX_BAND_1, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 tx cnt dump err %d\n", ret); + + /* dump PTCL TX status */ + ret = ptcl_status_dump(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 ptcl tx status dump err %d\n", ret); + ret = ptcl_status_dump(adapter, MAC_AX_BAND_1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 ptcl tx status dump err %d\n", ret); + + /* PTCL Debug port */ + ret = tx_flow_ptcl_dbg_port(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 ptcl dbg dump err %d\n", ret); + + ret = tx_flow_ptcl_dbg_port(adapter, MAC_AX_BAND_1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 ptcl dbg dump err %d\n", ret); + + /* check dle status */ + ret = mac_dle_status_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR] dle status err %d\n", ret); + + /* Sch Debug port */ + ret = tx_flow_sch_dbg_port(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 sch dbg err %d\n", ret); + + ret = tx_flow_sch_dbg_port(adapter, MAC_AX_BAND_1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 sch dbg dump err %d\n", ret); + + /* HCI flow control */ + mac_hci_flow_ctrl_dump(adapter); + + /* zero delimiter */ +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + /* zero delimiter */ + PLTFM_MSG_ALWAYS("R_AX_DEBUG_ZLD_COUNTER_U0_U1=0x%x\n", + MAC_REG_R32(R_AX_DEBUG_ZLD_COUNTER_U0_U1)); + PLTFM_MSG_ALWAYS("R_AX_DEBUG_ZLD_COUNTER_U2_U3=0x%x\n", + MAC_REG_R32(R_AX_DEBUG_ZLD_COUNTER_U2_U3)); + } +#endif + + PLTFM_MSG_ALWAYS("R_AX_PREBKF_CFG_0=0x%x\n", + MAC_REG_R32(R_AX_PREBKF_CFG_0)); + + return MACSUCCESS; +} + +void mac_dbg_status_dump(struct mac_ax_adapter *adapter, + struct mac_ax_dbgpkg *val, struct mac_ax_dbgpkg_en *en) +{ + u32 ret, i; + u32 ret_dmac = MACSUCCESS; + u8 cmac_allow; + + adapter->sm.l2_st = MAC_AX_L2_DIS; + ret = crit_dbg_dump(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("crit dbg dump %d\n", ret); + return; + } + + ret = fw_st_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("fw st dump %d\n", ret); + + if (en->dmac_dbg) { + ret_dmac = dmac_dbg_dump(adapter); + if (ret_dmac != MACSUCCESS) + PLTFM_MSG_ERR("dmac dbg dump %d\n", ret_dmac); + } + + cmac_allow = en->cmac_dbg && ret_dmac == MACSUCCESS ? 1 : 0; + if (cmac_allow) { + ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("cmac%d dbg dump %d\n", + MAC_AX_BAND_0, ret); + + ret = cmac_dbg_dump(adapter, MAC_AX_BAND_1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("cmac%d dbg dump %d\n", + MAC_AX_BAND_1, ret); + } + + if (en->mac_dbg_port) { + for (i = MAC_AX_DBG_PORT_SEL_PTCL_C0; + i < MAC_AX_DBG_PORT_SEL_LAST; i++) { + if (is_dbg_port_not_valid(adapter, i)) + continue; + ret = dbg_port_dump(adapter, i); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("dbg port %d dump %d\n", i, ret); + break; + } + } + } + + if (cmac_allow) { + /* 2nd dump trx counter after dbg port dump */ + ret = tx_cnt_dump(adapter, MAC_AX_BAND_0, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 tx cnt dump err %d\n", ret); + ret = rx_cnt_dump(adapter, MAC_AX_BAND_0, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B0 rx cnt dump err %d\n", ret); + + ret = tx_cnt_dump(adapter, MAC_AX_BAND_1, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 tx cnt dump err %d\n", ret); + ret = rx_cnt_dump(adapter, MAC_AX_BAND_1, TRX_CNT_REPT_CNT); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]B1 rx cnt dump err %d\n", ret); + } + + if (en->dle_dbg && ret_dmac == MACSUCCESS) { + ret = dle_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("dle dbg dump %d\n", ret); + + for (i = MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG; + i < MAC_AX_DLE_DFI_SEL_LAST; i++) { + if (!chk_dle_dfi_valid(adapter, i)) + continue; + ret = dle_dfi_dump(adapter, i); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("dle dfi %d dump %d\n", i, ret); + break; + } + } + } + + if (en->plersvd_dbg) { + ret = rsvd_ple_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("rsvd dle dump %d\n", ret); + } + + if (en->ss_dbg && ret_dmac == MACSUCCESS) { + ret = ss_dbgpkg(adapter, val); + if (ret != MACSUCCESS) + PLTFM_MSG_ALWAYS("ss dbgpkg %d\n", ret); + } + + ret = dbgport_hw_dump(adapter, &en->dp_hw_en); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("dbgport hw dump %d\n", ret); + + PLTFM_MSG_ALWAYS("access H2CREG before MAC init: %d\n", + adapter->stats.h2c_reg_uninit); + PLTFM_MSG_ALWAYS("access C2HREG before MAC init: %d\n", + adapter->stats.c2h_reg_uninit); + PLTFM_MSG_ALWAYS("access H2CPKT before MAC init: %d\n", + adapter->stats.h2c_pkt_uninit); + + adapter->sm.l2_st = MAC_AX_L2_EN; + + if (en->tx_flow_dbg) { + ret = mac_tx_flow_dbg(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("tx flow dbg %d\n", ret); + } +} + +u32 mac_sram_dbg_write(struct mac_ax_adapter *adapter, u32 offset, + u32 val, enum mac_ax_sram_dbg_sel sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_base; + + switch (sel) { + case CPU_LOCAL_SEL: + reg_base = CPU_LOCAL_BASE_ADDR + offset; + break; + case AXIDMA_SEL: + reg_base = AXIDMA_BASE_ADDR + offset; + break; + case STA_SCHED_SEL: + reg_base = STA_SCHED_BASE_ADDR + offset; + break; + case RXPLD_FLTR_CAM_SEL: + reg_base = RXPLD_FLTR_CAM_BASE_ADDR + offset; + break; + case SEC_CAM_SEL: + reg_base = SEC_CAM_BASE_ADDR + offset; + break; + case WOW_CAM_SEL: + reg_base = WOW_CAM_BASE_ADDR + offset; + break; + case CMAC_TBL_SEL: + reg_base = CMAC_TBL_BASE_ADDR + offset; + break; + case ADDR_CAM_SEL: + reg_base = ADDR_CAM_BASE_ADDR + offset; + break; + case BSSID_CAM_SEL: + reg_base = BSSID_CAM_BASE_ADDR + offset; + break; + case BA_CAM_SEL: + reg_base = BA_CAM_BASE_ADDR + offset; + break; + case BCN_IE_CAM0_SEL: + reg_base = BCN_IE_CAM0_BASE_ADDR + offset; + break; + case SHARED_BUF_SEL: + reg_base = SHARED_BUF_BASE_ADDR + offset; + break; + case DMAC_TBL_SEL: + reg_base = DMAC_TBL_BASE_ADDR + offset; + break; + case SHCUT_MACHDR_SEL: + reg_base = SHCUT_MACHDR_BASE_ADDR + offset; + break; + case BCN_IE_CAM1_SEL: + reg_base = BCN_IE_CAM1_BASE_ADDR + offset; + break; + default: + PLTFM_MSG_ERR("[ERR] sel %d", sel); + return MACNOITEM; + } + + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, reg_base); + MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, val); + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel); + + return MACSUCCESS; +} + +u32 mac_sram_dbg_read(struct mac_ax_adapter *adapter, u32 offset, + enum mac_ax_sram_dbg_sel sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_base, ret; + + switch (sel) { + case CPU_LOCAL_SEL: + reg_base = CPU_LOCAL_BASE_ADDR + offset; + break; + case AXIDMA_SEL: + reg_base = AXIDMA_BASE_ADDR + offset; + break; + case STA_SCHED_SEL: + reg_base = STA_SCHED_BASE_ADDR + offset; + break; + case RXPLD_FLTR_CAM_SEL: + reg_base = RXPLD_FLTR_CAM_BASE_ADDR + offset; + break; + case SEC_CAM_SEL: + reg_base = SEC_CAM_BASE_ADDR + offset; + break; + case WOW_CAM_SEL: + reg_base = WOW_CAM_BASE_ADDR + offset; + break; + case CMAC_TBL_SEL: + reg_base = CMAC_TBL_BASE_ADDR + offset; + break; + case ADDR_CAM_SEL: + reg_base = ADDR_CAM_BASE_ADDR + offset; + break; + case BSSID_CAM_SEL: + reg_base = BSSID_CAM_BASE_ADDR + offset; + break; + case BA_CAM_SEL: + reg_base = BA_CAM_BASE_ADDR + offset; + break; + case BCN_IE_CAM0_SEL: + reg_base = BCN_IE_CAM0_BASE_ADDR + offset; + break; + case SHARED_BUF_SEL: + reg_base = SHARED_BUF_BASE_ADDR + offset; + break; + case DMAC_TBL_SEL: + reg_base = DMAC_TBL_BASE_ADDR + offset; + break; + case SHCUT_MACHDR_SEL: + reg_base = SHCUT_MACHDR_BASE_ADDR + offset; + break; + case BCN_IE_CAM1_SEL: + reg_base = BCN_IE_CAM1_BASE_ADDR + offset; + break; + default: + PLTFM_MSG_ERR("[ERR] sel %d", sel); + return MACNOITEM; + } + + PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, reg_base); + ret = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY); + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel); + + return ret; +} + +static u32 get_rx_idx(struct mac_ax_adapter *adapter, + struct mac_ax_rx_cnt *rxcnt, u8 *idx) +{ + u8 rx_type[MAC_AX_RX_CNT_TYPE_NUM][MAC_AX_RX_PPDU_MAX] = { + MAC_AX_RXCRC_OK_IDX, MAC_AX_RXCRC_FAIL_IDX, + MAC_AX_RXFA_IDX, MAC_AX_RXPPDU_IDX}; + u8 type = rxcnt->type; + + switch (type) { + case MAC_AX_RX_CRC_OK: + case MAC_AX_RX_CRC_FAIL: + case MAC_AX_RX_FA: + case MAC_AX_RX_PPDU: + PLTFM_MEMCPY(idx, rx_type[type], MAC_AX_RX_PPDU_MAX); + break; + case MAC_AX_RX_IDX: + PLTFM_MEMSET(idx, MAC_AX_RX_CNT_IDX_MAX, MAC_AX_RX_PPDU_MAX); + idx[0] = rxcnt->idx; + break; + default: + PLTFM_MSG_ERR("Wrong RX cnt type\n"); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_rx_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_cnt *rxcnt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + u32 reg = rxcnt->band ? R_AX_RX_DBG_CNT_SEL_C1 : R_AX_RX_DBG_CNT_SEL; + u32 clk = rxcnt->band ? R_AX_RXGCK_CTRL_C1 : R_AX_RXGCK_CTRL; + u8 i; + u8 idx[MAC_AX_RX_PPDU_MAX] = {MAC_AX_RX_CNT_IDX_MAX}; + u16 *buf = rxcnt->buf; + u8 val; + + switch (rxcnt->op) { + case MAC_AX_RXCNT_R: + if (!buf) { + PLTFM_MSG_ERR("The rx cnt buffer is NULL\n"); + return MACNPTR; + } + + ret = get_rx_idx(adapter, rxcnt, idx); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Get RX index fail\n"); + return ret; + } + + for (i = 0; i < MAC_AX_RX_PPDU_MAX; i++) { + if (idx[i] == MAC_AX_RX_CNT_IDX_MAX) { + buf[i] = 0; + continue; + } + MAC_REG_W8(reg, idx[i]); + buf[i] = MAC_REG_R16(reg + 2); + } + break; + case MAC_AX_RXCNT_RST_ALL: + val = MAC_REG_R8(clk); + MAC_REG_W8(clk, val | BIT(0)); + MAC_REG_W8(reg + 1, BIT(0)); + MAC_REG_W8(clk, val); + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_dump_fw_rsvd_ple(struct mac_ax_adapter *adapter, u8 **buf) +{ + u32 ret = MACSUCCESS; + u32 addr; + *buf = NULL; + + if (adapter->mac_pwr_info.pwr_seq_proc || + adapter->sm.pwr != MAC_AX_PWR_ON || + adapter->mac_pwr_info.pwr_in_lps || + adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV || + adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE || + adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) + return MACPWRSTAT; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + addr = RSVD_PLE_OFST_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + addr = RSVD_PLE_OFST_8852B; + } else { + PLTFM_MSG_ERR("[ERR]unknown chip id\n"); + return MACCHIPID; + } + + *buf = (u8 *)PLTFM_MALLOC(FW_RSVD_PLE_SIZE); + if (!*buf) + return MACBUFALLOC; + + ret = __dump_mac_mem(adapter, MAC_AX_MEM_SHARED_BUF, addr, + *buf, FW_RSVD_PLE_SIZE, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Dump fw rsvd ple %d\n", ret); + PLTFM_FREE(buf, FW_RSVD_PLE_SIZE); + } + + ret = fw_backtrace_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("fw backtrace dump %d\n", ret); + + return ret; +} + +void mac_dump_ple_dbg_page(struct mac_ax_adapter *adapter, u8 page_num) +{ + u32 ret = MACSUCCESS; + u32 addr = 0; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + addr = RSVD_PLE_OFST_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + addr = RSVD_PLE_OFST_8852B; + } else { + PLTFM_MSG_ERR("unknown chip id\n"); + return; + } + + addr = addr + RSVD_PLE_OFST_DBG_START + (page_num * FW_RSVD_PLE_DBG_SIZE); + PLTFM_MSG_ERR("Dump fw ple dbg page %d:\n", page_num); + ret = __dump_mac_mem(adapter, MAC_AX_MEM_SHARED_BUF, addr, + NULL, FW_RSVD_PLE_DBG_SIZE, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Dump fw ple dbg page fail: %d\n", ret); + return; + } +} + +u32 mac_fw_dbg_dump(struct mac_ax_adapter *adapter, u8 **buf, struct mac_ax_fwdbg_en *en) +{ + u32 ret = MACSUCCESS; + + if (en->status_dbg) + fw_st_dbg_dump(adapter); + + if (en->rsv_ple_dbg) + mac_dump_fw_rsvd_ple(adapter, buf); + + if (en->ps_dbg) + ps_dbg_dump(adapter); + + return ret; +} + +u32 mac_event_notify(struct mac_ax_adapter *adapter, enum phl_msg_evt_id id, + u8 band) +{ + u32 ret = MACSUCCESS, io_ret = MACSUCCESS; + struct mac_ax_dbgpkg dbg_val; + struct mac_ax_dbgpkg_en dbg_en; + struct mac_ax_io_stat pcie_io_stat; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); +#ifdef CONFIG_FW_IO_OFLD_SUPPORT + struct mac_ax_drv_stats *status = &adapter->drv_stats; +#endif + + switch (id) { + case MSG_EVT_DBG_SIP_REG_DUMP: + ret = crit_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("crit dbg dump %d\n", ret); + + ret = fw_st_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("fw st dump %d\n", ret); + + ret = dmac_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("dmac dbg dump %d\n", ret); + + ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("cmac%d dbg dump %d\n", + MAC_AX_BAND_0, ret); + + break; + case MSG_EVT_DBG_FULL_REG_DUMP: + ret = mac_reg_dump(adapter, MAC_AX_REG_MAC); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("fw st dump %d\n", ret); + break; + case MSG_EVT_DBG_L2_DIAGNOSE: + ret = mac_ps_pwr_state(adapter, MAC_AX_PWR_STATE_ACT_REQ, + MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("PWR_STATE_ACT_REQ fail\n"); + + PLTFM_MEMSET(&dbg_en, 0, sizeof(struct mac_ax_dbgpkg_en)); + + if (ret == MACSUCCESS) { + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + io_ret = ops->get_io_stat(adapter, + &pcie_io_stat); + if (io_ret == MACSUCCESS && + pcie_io_stat.to_flag == 0) { + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.plersvd_dbg = 1; + } + } else { + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.plersvd_dbg = 1; + } + } + mac_dbg_status_dump(adapter, &dbg_val, &dbg_en); + break; + case MSG_EVT_DBG_RX_DUMP: + ret = crit_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("crit dbg dump %d\n", ret); + + ret = dmac_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("dmac dbg dump %d\n", ret); + + ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("cmac%d dbg dump %d\n", + MAC_AX_BAND_0, ret); + + ret = dle_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("dle dbg dump %d\n", ret); + break; + case MSG_EVT_DBG_TX_DUMP: + ret = tx_dbg_dump(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("tx dbg dump %d\n", ret); + break; +#ifdef CONFIG_FW_IO_OFLD_SUPPORT + case MSG_EVT_DATA_PATH_START: + status->rx_ok = 1; + break; + case MSG_EVT_DATA_PATH_STOP: + status->rx_ok = 0; + break; + case MSG_EVT_SURPRISE_REMOVE: + status->drv_rm = 1; + break; +#endif + default: + return MACNOITEM; + } + + return ret; +} + +u32 mac_fw_dbg_dle_cfg(struct mac_ax_adapter *adapter, bool lock) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_general_pkt *write_ptr; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_general_pkt_ids)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + write_ptr = (struct fwcmd_general_pkt *)buf; + write_ptr->dword0 = + cpu_to_le32((lock ? FWCMD_H2C_FW_DBGREG_CFG_FW_DBG_LOCK : 0)); + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_INFO, + FWCMD_H2C_FUNC_FW_DBGREG_CFG, + 0, 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_get_fw_status(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val8 = FWDL_INITIAL_STATE; + u32 i = 0, fw_pc = 0; + u32 val32, dbg_ctrl_bk, sys_status_bk; + + val8 = GET_FIELD(MAC_REG_R8(R_AX_WCPU_FW_CTRL), B_AX_WCPU_FWDL_STS); + if (val8 == FWDL_WCPU_FW_INIT_RDY) { + /* Dump FW status */ + val32 = Read_DBG_FS_REG(); + if (val32 == FS_L2ERR_IN || + val32 == FS_L2ERR_CPU_IN || + val32 == FS_L2ERR_HCI_IN || + val32 == FS_L2ERR_ELSE_IN) { + return MACFWRXI300; + } else if (val32 == FS_ASSERT_IN) { + return MACFWASSERT; + } else if (val32 == FS_EXCEP_IN) { + return MACFWEXCEP; + } + + /* Dump FW program counter */ + dbg_ctrl_bk = MAC_REG_R32(R_AX_DBG_CTRL); + sys_status_bk = MAC_REG_R32(R_AX_SYS_STATUS1); + MAC_REG_W32(R_AX_DBG_CTRL, DBG_SEL_FW_PROG_CNTR); + + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + for (i = 0; i < FW_PROG_CNTR_DMP_CNT; i++) { + val32 = MAC_REG_R32(R_AX_DBG_PORT_SEL); +// PLTFM_MSG_ALWAYS("FW PC = 0x%x\n", val32); + if (fw_pc == val32) + return MACFWPCHANG; + fw_pc = val32; + PLTFM_DELAY_US(FW_PROG_CNTR_DMP_DLY_US); + } + + MAC_REG_W32(R_AX_DBG_CTRL, dbg_ctrl_bk); + MAC_REG_W32(R_AX_SYS_STATUS1, sys_status_bk); + } else { + return MACNOFW; + } + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/dbgpkg.h b/phl/hal_g6/mac/mac_ax/dbgpkg.h new file mode 100644 index 0000000..7fbf7d6 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbgpkg.h @@ -0,0 +1,1153 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_DBGPKG_H_ +#define _MAC_AX_DBGPKG_H_ + +#include "../mac_def.h" +#include "../mac_ax.h" +#include "fwcmd.h" +#include "trx_desc.h" +#include "trxcfg.h" +#include "dle.h" + +#define FW_RSVD_PLE_SIZE 0x800 +#define RSVD_PLE_OFST_8852A 0x6f800 +#define RSVD_PLE_OFST_8852B 0x2f800 +#define FW_RSVD_PLE_DBG_SIZE 0x100 +#define RSVD_PLE_OFST_DBG_START 0x400 +#define SHARE_BUFFER_SIZE_8852A 0x70000 +#define SHARE_BUFFER_SIZE_8852B 0x30000 +#define STA_SCHED_MEM_SIZE 0x1200 +#define RXPLD_FLTR_CAM_MEM_SIZE 0x200 +#define SECURITY_CAM_MEM_SIZE 0x800 +#define WOW_CAM_MEM_SIZE 0x240 +#define ADDR_CAM_MEM_SIZE 0x4000 +#define TXD_FIFO_SIZE 0x200 +#define DBG_PORT_DUMP_DLY_US 10 +#define FW_BACKTRACE_MAX_SIZE 512 // 8 * 64(entry) +#define FW_BACKTRACE_KEY 0xBACEBACE +#define FW_BACKTRACE_SIZE_OFST 4 +#define FW_BACKTRACE_KEY_OFST 8 + +#define B_AX_AXIDMA_INT_SEL_SH 22 +#define B_AX_AXIDMA_INT_SEL_MSK 0x7 + +#define TMAC_TX_CNT_NUM 11 +#define RMAC_RX_CNT_NUM 37 +#define TRX_CNT_REPT_CNT 5 +#define TRX_CNT_REPT_DLY_US 10 +#define TRX_CNT_READ_DLY_US 1 +#define PTCL_ST_NUM 11 +#define PTCL_ST_READ_DLY_US 1 +#define PTCL_SEL_FSM_0 0x0 +#define PTCL_SEL_FSM_1 0x1 +#define PTCL_SEL_PHY_DBG 0x10 +#define SCH_SEL_PREBKF_DBG_1 0x03 +#define SCH_SEL_EDCA_DBG 0x04 +#define PTCL_DBG_DMP_CNT 15 +#define SCH_DBG_DMP_CNT 15 + +#define PTCL_SEL_PHY_DBG 0x10 +#define SCH_SEL_EDCA_DBG 0x04 +#define PTCL_DBG_DMP_CNT 15 +#define SCH_DBG_DMP_CNT 15 +#define MAC_DBG_DMP_CNT 15 +#define MAC_DBG_DUMP_DLY_US 10 + +#define DBG_SEL_FW_PROG_CNTR 0xF200F2 +#define FW_PROG_CNTR_DMP_CNT 15 +#define FW_PROG_CNTR_DMP_DLY_US 10 + +/* Wait for BCN parser idle shall consider RX beacon max time */ +#define BCN_PSR_WAIT_CNT 900 +#define BCN_PSR_WAIT_US 10 + +/* REG dump*/ +#define MAC_PAGE_SRT 0 +#define MAC_PAGE_AON_END 0x4 +#define MAC_PAGE_TOP_END 0xF +#define MAC_PAGE_HCI_SRT 0x10 +#define MAC_PAGE_HCI_END 0x1F +#define MAC_PAGE_DMAC_SRT 0x80 +#define MAC_PAGE_DMAC_END 0x9F +#define MAC_PAGE_CMAC0_SRT 0xC0 +#define MAC_PAGE_CMAC0_END 0xDF +#define MAC_PAGE_CMAC1_SRT 0xE0 +#define MAC_PAGE_END 0xFF +#define BB_PAGE_SRT 0x100 +#define BB_PAGE_END 0x17F +#define IQK_PAGE_SRT 0x180 +#define IQK_PAGE_END 0x1BF +#define RFC_PAGE_SRT 0x1C0 +#define RFC_PAGE_END 0x1FF + +/* STA scheduler */ +#define SS_MACID_SH 8 +#define SS_TX_LEN_MSK 0x1FFFFF +#define SS_CTRL1_R_TX_LEN 5 +#define SS_CTRL1_R_NEXT_LINK 20 +#define SS_WMM_NUM_8852A 4 +#define SS_WMM_NUM_8852B 2 +#define SS_WMM_NUM_8852C 4 +#define SS_WMM_NUM_8192XB 4 +#define SS_UL_SUPPORT_8852A 1 +#define SS_UL_SUPPORT_8852B 0 +#define SS_UL_SUPPORT_8852C 1 +#define SS_UL_SUPPORT_8192XB 1 +#define SS_FW_SUPPORT_8852A 1 +#define SS_FW_SUPPORT_8852B 0 +#define SS_FW_SUPPORT_8852C 1 +#define SS_FW_SUPPORT_8192XB 1 +#define SS_POLL_UNEXPECTED 0xFFFFFFFF + +/* MAC debug port */ +#define CMAC_DMA_DBG_SEL_C0 0xA0 +#define TMAC_DBG_SEL_C0 0xA5 +#define RMAC_DBG_SEL_C0 0xA6 +#define TRXPTCL_DBG_SEL_C0 0xA7 +#define CMAC_DMA_DBG_SEL_C1 0xB0 +#define TMAC_DBG_SEL_C1 0xB5 +#define RMAC_DBG_SEL_C1 0xB6 +#define TRXPTCL_DBG_SEL_C1 0xB7 +#define PCIE_TXDMA_DBG_SEL 0x30 +#define PCIE_RXDMA_DBG_SEL 0x31 +#define PCIE_CVT_DBG_SEL 0x32 +#define PCIE_EMAC04_DBG_SEL 0x33 +#define PCIE_EMAC5_DBG_SEL 0x34 +#define PCIE_EMAC6_DBG_SEL 0x35 +#define PCIE_EMAC7_DBG_SEL 0x36 +#define PCIE_PNP_IO_DBG_SEL 0x37 +#define PCIE_EMAC814_DBG_SEL 0x38 +#define PCIE_EMAC15_DBG_SEL 0x39 +#define PCIE_EMAC16_DBG_SEL 0x3A +#define PCIE_EMAC17_DBG_SEL 0x3B +#define PCIE_EMAC18_DBG_SEL 0x3C +#define PCIE_IO_DBG_SEL 0x37 +#define PCIE_MISC_DBG_SEL 0x38 +#define PCIE_MISC2_DBG_SEL 0x00 +#define USB2_PHY_DBG_SEL 0x50 +#define USB2_SIE_DBG_SEL 0x51 +#define USB2_UTMI_DBG_SEL 0x52 +#define USB2_SIE_MMU_DBG_SEL 0x53 +#define USB2_SIE_PCE_DBG_SEL 0x54 +#define USB2_UTMI_IF_DBG_SEL 0x55 +#define USB_WLTX_DBG_SEL 0x56 +#define USB_WLRX_DBG_SEL 0x57 +#define USB3_DBG_SEL 0x58 +#define USB_SETUP_DBG_SEL 0x59 +#define USB_WLTXDMA_DBG_SEL 0x5A +#define USB_WLRXDMA_DBG_SEL 0x5B +#define USB_AINST_DBG_SEL 0x5C +#define USB_MISC_DBG_SEL 0x5D +#define USB_BTTX_DBG_SEL 0x5E +#define USB2_BT_DBG_SEL 0x5F +#define DISPATCHER_DBG_SEL 0x80 +#define MAC_DBG_SEL 1 +#define RMAC_CMAC_DBG_SEL 1 + +/* TRXPTCL dbg port sel */ +#define TRXPTRL_DBG_SEL_TMAC 0 +#define TRXPTRL_DBG_SEL_RMAC 1 + +#define MAC_AX_RX_CNT_NUM 48 +#define MAC_AX_RX_CNT_IDX_MAX MAC_AX_RX_CNT_NUM +#define MAC_AX_RX_CNT_TYPE_NUM 5 + +/* the order is CCK, OFDM, HT, VHTSU, VHTMU, HESU, HEMU, HETB */ +#define MAC_AX_RXCRC_OK_IDX \ + {3, 0, 6, 10, 14, 18, 22, 26} +#define MAC_AX_RXCRC_FAIL_IDX \ + {4, 1, 7, 11, 15, 19, 23, 27} +#define MAC_AX_RXPPDU_IDX \ + {MAC_AX_RX_CNT_IDX_MAX, MAC_AX_RX_CNT_IDX_MAX, 8, 16, 20, 24, 28} +#define MAC_AX_RXFA_IDX \ + {5, 2, 9, 17, 21, 25, 29} + +#define Read_DBG_FS_REG() GET_FIELD(MAC_REG_R32(R_AX_UDM0), B_AX_UDM0_FS_CODE) + +/** + * @enum mac_ax_sram_dbg_sel + * + * @brief mac_ax_sram_dbg_sel + * + * @var mac_ax_sram_dbg_sel::CPU_LOCAL_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::AXIDMA_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::STA_SCHED_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::RXPLD_FLTR_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::SEC_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::WOW_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::CMAC_TBL_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::ADDR_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::BSSID_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::BA_CAM_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::BCN_IE_CAM0_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::SHARED_BUF_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::DMAC_TBL_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::SHCUT_MACHDR_SEL + * Please Place Description here. + * @var mac_ax_sram_dbg_sel::BCN_IE_CAM1_SEL + * Please Place Description here. + */ +enum mac_ax_sram_dbg_sel { + CPU_LOCAL_SEL, + AXIDMA_SEL, + STA_SCHED_SEL, + RXPLD_FLTR_CAM_SEL, + SEC_CAM_SEL, + WOW_CAM_SEL, + CMAC_TBL_SEL, + ADDR_CAM_SEL, + BSSID_CAM_SEL, + BA_CAM_SEL, + BCN_IE_CAM0_SEL, + SHARED_BUF_SEL, + DMAC_TBL_SEL, + SHCUT_MACHDR_SEL, + BCN_IE_CAM1_SEL, +}; + +/** + * @enum mac_ax_dle_dfi_sel + * + * @brief mac_ax_dle_dfi_sel + * + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY + * Please Place Description here. + */ +enum mac_ax_dle_dfi_sel { + MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG = 0, + MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA, + MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT, + MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO, + MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT, + MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT, + MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL, + MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY, + MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG, + MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA, + MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT, + MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO, + MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT, + MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT, + MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL, + MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY, + + /* keep last */ + MAC_AX_DLE_DFI_SEL_LAST, + MAC_AX_DLE_DFI_SEL_MAX = MAC_AX_DLE_DFI_SEL_LAST, + MAC_AX_DLE_DFI_SEL_INVALID = MAC_AX_DLE_DFI_SEL_LAST, +}; + +/** + * @struct mac_ax_dle_dfi_info + * @brief mac_ax_dle_dfi_info + * + * @var mac_ax_dle_dfi_info::srt + * Please Place Description here. + * @var mac_ax_dle_dfi_info::end + * Please Place Description here. + * @var mac_ax_dle_dfi_info::inc_num + * Please Place Description here. + */ +struct mac_ax_dle_dfi_info { + u32 srt; + u32 end; + u32 inc_num; +}; + +/** + * @enum mac_ax_dbg_port_sel + * + * @brief mac_ax_dbg_port_sel + * + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PTCL_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_SCH_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TMAC_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMACST_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TRXPTCL_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOL_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOH_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PTCL_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_SCH_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TMAC_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMACST_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TRXPTCL_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOL_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOH_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PKTINFO + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_TXDMA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_RXDMA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_CVT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC04 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC5 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC6 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC7 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC814 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC15 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC16 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC17 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC18 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_PHY + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_UTMI + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLTX + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLRX + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB3 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_SETUP + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_AINST + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_MISC + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_BTTX + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_BT + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1 + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_LAST + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_MAX + * Please Place Description here. + * @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_dbg_port_sel { + /* CMAC 0 related */ + MAC_AX_DBG_PORT_SEL_PTCL_C0 = 0, + MAC_AX_DBG_PORT_SEL_SCH_C0, + MAC_AX_DBG_PORT_SEL_TMAC_C0, + MAC_AX_DBG_PORT_SEL_RMAC_C0, + MAC_AX_DBG_PORT_SEL_RMACST_C0, + MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0, + MAC_AX_DBG_PORT_SEL_TRXPTCL_C0, + MAC_AX_DBG_PORT_SEL_TX_INFOL_C0, + MAC_AX_DBG_PORT_SEL_TX_INFOH_C0, + MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0, + MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0, + MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0, + MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0, + /* CMAC 1 related */ + MAC_AX_DBG_PORT_SEL_PTCL_C1, + MAC_AX_DBG_PORT_SEL_SCH_C1, + MAC_AX_DBG_PORT_SEL_TMAC_C1, + MAC_AX_DBG_PORT_SEL_RMAC_C1, + MAC_AX_DBG_PORT_SEL_RMACST_C1, + MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1, + MAC_AX_DBG_PORT_SEL_TRXPTCL_C1, + MAC_AX_DBG_PORT_SEL_TX_INFOL_C1, + MAC_AX_DBG_PORT_SEL_TX_INFOH_C1, + MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1, + MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1, + MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1, + MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1, + /* DLE related */ + MAC_AX_DBG_PORT_SEL_PKTINFO, + MAC_AX_DBG_PORT_SEL_WDRLS, + /* TXPKT_CTRL related */ + MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0, + MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1, + MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2, + MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3, + MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4, + /* PCIE related */ + MAC_AX_DBG_PORT_SEL_PCIE_TXDMA, + MAC_AX_DBG_PORT_SEL_PCIE_RXDMA, + MAC_AX_DBG_PORT_SEL_PCIE_CVT, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC04, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC5, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC6, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC7, + MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC814, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC15, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC16, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC17, + MAC_AX_DBG_PORT_SEL_PCIE_EMAC18, + /* USB related */ + MAC_AX_DBG_PORT_SEL_USB2_PHY, + MAC_AX_DBG_PORT_SEL_USB2_SIE, + MAC_AX_DBG_PORT_SEL_USB2_UTMI, + MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU, + MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE, + MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF, + MAC_AX_DBG_PORT_SEL_USB_WLTX, + MAC_AX_DBG_PORT_SEL_USB_WLRX, + MAC_AX_DBG_PORT_SEL_USB3, + MAC_AX_DBG_PORT_SEL_USB_SETUP, + MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA, + MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA, + MAC_AX_DBG_PORT_SEL_USB_AINST, + MAC_AX_DBG_PORT_SEL_USB_MISC, + MAC_AX_DBG_PORT_SEL_USB_BTTX, + MAC_AX_DBG_PORT_SEL_USB2_BT, + /* DISPATCHER related */ + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX1, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2, + MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0, + MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1, + MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL, + MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL, + MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF, + MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF, + MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL, + /*AXIDMAC related*/ + MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL, + MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL, + MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN, + MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN, + MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL, + + /* keep last */ + MAC_AX_DBG_PORT_SEL_LAST, + MAC_AX_DBG_PORT_SEL_MAX = MAC_AX_DBG_PORT_SEL_LAST, + MAC_AX_DBG_PORT_SEL_INVALID = MAC_AX_DBG_PORT_SEL_LAST, +}; + +struct ss_link_info { + u8 wmm; + u8 ac; + u8 ul; +}; + +/** + * @struct mac_ax_dbg_port_info + * @brief mac_ax_dbg_port_info + * + * @var mac_ax_dbg_port_info::sel_addr + * Please Place Description here. + * @var mac_ax_dbg_port_info::sel_byte + * Please Place Description here. + * @var mac_ax_dbg_port_info::sel_sh + * Please Place Description here. + * @var mac_ax_dbg_port_info::sel_msk + * Please Place Description here. + * @var mac_ax_dbg_port_info::srt + * Please Place Description here. + * @var mac_ax_dbg_port_info::end + * Please Place Description here. + * @var mac_ax_dbg_port_info::inc_num + * Please Place Description here. + * @var mac_ax_dbg_port_info::rd_addr + * Please Place Description here. + * @var mac_ax_dbg_port_info::rd_byte + * Please Place Description here. + * @var mac_ax_dbg_port_info::rd_sh + * Please Place Description here. + * @var mac_ax_dbg_port_info::rd_msk + * Please Place Description here. + */ +struct mac_ax_dbg_port_info { + u32 sel_addr; + u8 sel_byte; + u32 sel_sh; + u32 sel_msk; + u32 srt; + u32 end; + u32 inc_num; + u32 rd_addr; + u8 rd_byte; + u32 rd_sh; + u32 rd_msk; +}; + +/** + * @struct iecam_cfg_info + * @brief iecam_cfg_info + * + * @var iecam_cfg_info::camctrl_bkp + * Please Place Description here. + * @var iecam_cfg_info::ioctrl_bkp + * Please Place Description here. + * @var iecam_cfg_info::rbp_bkp + * Please Place Description here. + */ +struct iecam_cfg_info { + u16 camctrl_bkp; + u16 ioctrl_bkp; + u32 rbp_bkp; +}; + +struct fw_backtrace_info { + u32 ra; + u32 sp; +}; + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_fwcmd_lb + * + * @param *adapter + * @param len + * @param burst + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_fwcmd_lb(struct mac_ax_adapter *adapter, u32 len, u8 burst); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief c2h_sys_cmd_path + * + * @param *adapter + * @param *buf + * @param len + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 c2h_sys_cmd_path(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief c2h_sys_plat_autotest + * + * @param *adapter + * @param *buf + * @param len + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 c2h_sys_plat_autotest(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief iecam_aces_cfg + * + * @param *adapter + * @param band + * @param en + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 iecam_aces_cfg(struct mac_ax_adapter *adapter, u8 band, u8 en, + struct iecam_cfg_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_mem_dump + * + * @param *adapter + * @param sel + * @param strt_addr + * @param *buf + * @param len + * @param dbg_path + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mem_dump(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel, + u32 strt_addr, u8 *buf, u32 len, u32 dbg_path); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_get_mem_size + * + * @param *adapter + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_mem_size(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_reg_dump + * + * @param *adapter + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_reg_dump(struct mac_ax_adapter *adapter, enum mac_ax_reg_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief dle_dfi_sel + * + * @param *adapter + * @param **info + * @param *ctrl + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 dle_dfi_sel(struct mac_ax_adapter *adapter, + struct mac_ax_dle_dfi_info **info, + u32 *target, u32 sel); +/** + * @} + * @} + */ + +/** + * @brief is_dbg_port_not_valid + * + * @param *adapter + * @param dbg_sel + * @return Please Place Description here. + * @retval u8 + */ +u8 is_dbg_port_not_valid(struct mac_ax_adapter *adapter, u32 dbg_sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_dbg_status_dump + * + * @param *adapter + * @param *val + * @param *en + * @return Please Place Description here. + * @retval void + */ +void mac_dbg_status_dump(struct mac_ax_adapter *adapter, + struct mac_ax_dbgpkg *val, + struct mac_ax_dbgpkg_en *en); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief dbg_port_sel + * + * @param *adapter + * @param **info + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 dbg_port_sel(struct mac_ax_adapter *adapter, + struct mac_ax_dbg_port_info **info, u32 sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_sram_dbg_write + * + * @param *adapter + * @param offset + * @param val + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sram_dbg_write(struct mac_ax_adapter *adapter, u32 offset, + u32 val, enum mac_ax_sram_dbg_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_sram_dbg_read + * + * @param *adapter + * @param offset + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sram_dbg_read(struct mac_ax_adapter *adapter, u32 offset, + enum mac_ax_sram_dbg_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_rx_cnt + * + * @param *adapter + * @param *rxcnt + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_rx_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_cnt *rxcnt); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_dump_fw_rsvd_ple + * + * @param *adapter + * @param **buf + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_fw_rsvd_ple(struct mac_ax_adapter *adapter, u8 **buf); +/** + * @} + * @} + */ + +/** + * @brief mac_dump_ple_dbg_page + * + * @param *adapter + * @return Please Place Description here. + * @retval void + */ +void mac_dump_ple_dbg_page(struct mac_ax_adapter *adapter, u8 page_num); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_fw_dbg_dump + * + * @param *adapter + * @param **buf + * @param *en + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fw_dbg_dump(struct mac_ax_adapter *adapter, + u8 **buf, + struct mac_ax_fwdbg_en *en); +/** + * @} + * @} + */ +u32 fw_st_dbg_dump(struct mac_ax_adapter *adapter); + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_event_notify + * for Sta mode debug usage + * @param *adapter + * @param **buf + * @param *en + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_event_notify(struct mac_ax_adapter *adapter, enum phl_msg_evt_id id, + u8 band); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DebugPackage + * @{ + */ + +/** + * @brief mac_fwdbg_lock + * lock or unlock fwdbgreg + * @param *adapter + * @param lock + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fw_dbg_dle_cfg(struct mac_ax_adapter *adapter, bool lock); +/** + * @} + * @} + */ + +/** + * @brief pltfm_dbg_dump + * dump cpu platform for dbg + * @param *adapter + */ +void pltfm_dbg_dump(struct mac_ax_adapter *adapter); + +/** + * @} + * @} + */ +/** + * @brief mac_get_fw_status + * get fw status + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_fw_status(struct mac_ax_adapter *adapter); +#endif diff --git a/phl/hal_g6/mac/mac_ax/dbgport_hw.c b/phl/hal_g6/mac/mac_ax/dbgport_hw.c new file mode 100644 index 0000000..f9f2d0f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbgport_hw.c @@ -0,0 +1,812 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "dbgpkg.h" +#include "dbgport_hw.h" + +static u32 dp_intn_idx_set(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw *dp_hw, u8 sel_idx) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, intn_val; + u16 val16; + u8 dbg_sel, intn_idx; + + dbg_sel = dp_hw->dbg_sel[sel_idx]; + intn_idx = dp_hw->intn_idx[sel_idx]; + + switch (dbg_sel) { + case MAC_AX_DP_SEL_SYS_0: + case MAC_AX_DP_SEL_SYS_1F: + /* To do... */ + break; + case MAC_AX_DP_SEL_PINMUX_0: + case MAC_AX_DP_SEL_PINMUX_7: + /* To do... */ + break; + case MAC_AX_DP_SEL_LOADER_0: + case MAC_AX_DP_SEL_LOADER_3: + /* To do... */ + break; + case MAC_AX_DP_SEL_HMUX_0: + case MAC_AX_DP_SEL_HMUX_3: + /* To do... */ + break; + case MAC_AX_DP_SEL_PCIE_0: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_0_0: + case MAC_AX_DP_INTN_IDX_PCIE_0_1: + case MAC_AX_DP_INTN_IDX_PCIE_0_2: + case MAC_AX_DP_INTN_IDX_PCIE_0_3: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_1: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_1_0: + case MAC_AX_DP_INTN_IDX_PCIE_1_1: + case MAC_AX_DP_INTN_IDX_PCIE_1_2: + case MAC_AX_DP_INTN_IDX_PCIE_1_3: + case MAC_AX_DP_INTN_IDX_PCIE_1_4: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_2: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_2_0: + case MAC_AX_DP_INTN_IDX_PCIE_2_1: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_3: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_3_0: + case MAC_AX_DP_INTN_IDX_PCIE_3_1: + case MAC_AX_DP_INTN_IDX_PCIE_3_2: + case MAC_AX_DP_INTN_IDX_PCIE_3_3: + case MAC_AX_DP_INTN_IDX_PCIE_3_4: + case MAC_AX_DP_INTN_IDX_PCIE_3_5: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_4: + case MAC_AX_DP_SEL_PCIE_5: + case MAC_AX_DP_SEL_PCIE_6: + // don't have internal setting + break; + case MAC_AX_DP_SEL_PCIE_7: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_7_0: + intn_val = 0x0; + break; + case MAC_AX_DP_INTN_IDX_PCIE_7_1: + intn_val = 0x4; + break; + case MAC_AX_DP_INTN_IDX_PCIE_7_2: + intn_val = 0x1; + break; + case MAC_AX_DP_INTN_IDX_PCIE_7_3: + intn_val = 0x5; + break; + case MAC_AX_DP_INTN_IDX_PCIE_7_4: + intn_val = 0x2; + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_val, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_8: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PCIE_8_0: + case MAC_AX_DP_INTN_IDX_PCIE_8_1: + case MAC_AX_DP_INTN_IDX_PCIE_8_2: + case MAC_AX_DP_INTN_IDX_PCIE_8_3: + case MAC_AX_DP_INTN_IDX_PCIE_8_4: + case MAC_AX_DP_INTN_IDX_PCIE_8_5: + case MAC_AX_DP_INTN_IDX_PCIE_8_6: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); + MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_PCIE_9: + case MAC_AX_DP_SEL_PCIE_A: + case MAC_AX_DP_SEL_PCIE_B: + case MAC_AX_DP_SEL_PCIE_C: + // don't have internal setting + break; + case MAC_AX_DP_SEL_PCIE_D: + case MAC_AX_DP_SEL_PCIE_E: + case MAC_AX_DP_SEL_PCIE_F: + // don't have this item + return MACNOITEM; + case MAC_AX_DP_SEL_USB_0: + case MAC_AX_DP_SEL_USB_F: + /* To do... */ + break; + case MAC_AX_DP_SEL_SDIO_0: + case MAC_AX_DP_SEL_SDIO_F: + /* To do... */ + break; + case MAC_AX_DP_SEL_BT: + /* To do... */ + break; + case MAC_AX_DP_SEL_AXIDMA: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_AXIDMA_0: + intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_1: + intn_val = (0x1 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_2: + intn_val = (0x2 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x2 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_3: + intn_val = (0x3 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x3 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_4: + intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_5: + intn_val = (0x1 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_6: + intn_val = (0x2 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x2 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_7: + intn_val = (0x3 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x3 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_8: + intn_val = (0x4 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x4 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_9: + intn_val = (0x5 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x5 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_A: + intn_val = (0x6 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x6 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x1 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_B: + intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x2 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_C: + intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x3 << AXIDMA_DBG_SEL_INTN2_SH); + break; + case MAC_AX_DP_INTN_IDX_AXIDMA_D: + intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) | + (0x0 << AXIDMA_DBG_SEL_INTN1_SH) | + (0x4 << AXIDMA_DBG_SEL_INTN2_SH); + break; + default: + return MACNOITEM; + } + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR); + val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL); + val32 = SET_CLR_WORD(val32, intn_val, B_PL_AXIDMA_DBG_SEL); + MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, val32); + break; + case MAC_AX_DP_SEL_WLPHYDBG_GPIO: + /* To do... */ + break; + case MAC_AX_DP_SEL_BTCOEXIST: + /* To do... */ + break; + case MAC_AX_DP_SEL_LTECOEX: + /* To do... */ + break; + case MAC_AX_DP_SEL_WLPHYDBG: + /* To do... */ + break; + case MAC_AX_DP_SEL_WLAN_MAC_REG: + /* To do... */ + break; + case MAC_AX_DP_SEL_WLAN_MAC_PMC: + /* To do... */ + break; + case MAC_AX_DP_SEL_CALIB_TOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_DISPATCHER_TOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_WDE_DLE: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_WDE_DLE_0: + intn_val = 0x0; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_1: + intn_val = 0x1; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_2: + intn_val = 0xE; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_3: + intn_val = 0x10; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_4: + intn_val = 0x11; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_5: + intn_val = 0x14; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_6: + intn_val = 0x1E; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_7: + intn_val = 0x80; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_8: + intn_val = 0x81; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_9: + intn_val = 0x82; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_A: + intn_val = 0x90; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_B: + intn_val = 0x91; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_C: + intn_val = 0x92; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_D: + intn_val = 0xB0; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_E: + intn_val = 0xB1; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_F: + intn_val = 0xB2; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_10: + intn_val = 0xC0; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_11: + intn_val = 0xC1; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_12: + intn_val = 0xC2; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_13: + intn_val = 0xE0; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_14: + intn_val = 0xE1; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_15: + intn_val = 0xE2; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_16: + intn_val = 0xF0; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_17: + intn_val = 0xF1; + break; + case MAC_AX_DP_INTN_IDX_WDE_DLE_18: + intn_val = 0xF2; + break; + default: + return MACNOITEM; + } + val16 = MAC_REG_R16(R_AX_WDE_DBG_CTL); + val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG0_SEL); + val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG1_SEL); + MAC_REG_W16(R_AX_WDE_DBG_CTL, val16); + break; + case MAC_AX_DP_SEL_PLE_DLE: + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_PLE_DLE_0: + intn_val = 0x0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_1: + intn_val = 0x1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_2: + intn_val = 0xE; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_3: + intn_val = 0x10; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_4: + intn_val = 0x11; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_5: + intn_val = 0x14; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_6: + intn_val = 0x1E; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_7: + intn_val = 0x80; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_8: + intn_val = 0x81; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_9: + intn_val = 0x82; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_A: + intn_val = 0x90; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_B: + intn_val = 0x91; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_C: + intn_val = 0x92; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_D: + intn_val = 0xA0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_E: + intn_val = 0xA1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_F: + intn_val = 0xA2; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_10: + intn_val = 0xB0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_11: + intn_val = 0xB1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_12: + intn_val = 0xB2; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_13: + intn_val = 0xC0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_14: + intn_val = 0xC1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_15: + intn_val = 0xC2; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_16: + intn_val = 0xD0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_17: + intn_val = 0xD1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_18: + intn_val = 0xD2; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_19: + intn_val = 0xE0; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_1A: + intn_val = 0xE1; + break; + case MAC_AX_DP_INTN_IDX_PLE_DLE_1B: + intn_val = 0xE2; + break; + default: + return MACNOITEM; + } + val16 = MAC_REG_R16(R_AX_PLE_DBG_CTL); + val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG0_SEL); + val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG1_SEL); + MAC_REG_W16(R_AX_PLE_DBG_CTL, val16); + break; + case MAC_AX_DP_SEL_WDRLS: + /* To do... */ + break; + case MAC_AX_DP_SEL_DLE_CPUIO: + /* To do... */ + break; + case MAC_AX_DP_SEL_BBRPT: + /* To do... */ + break; + case MAC_AX_DP_SEL_TXPKTCTL: + /* To do... */ + break; + case MAC_AX_DP_SEL_PKTBUFFER: + /* To do... */ + break; + case MAC_AX_DP_SEL_DMAC_TABLE: + /* To do... */ + break; + case MAC_AX_DP_SEL_STA_SCHEDULER: + val32 = MAC_REG_R32(R_AX_SS_DBG_0); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_LM_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_SA_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PC_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PARAM_STAT); + MAC_REG_W32(R_AX_SS_DBG_0, val32); + + val32 = MAC_REG_R32(R_AX_SS_DBG_1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_LEN_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLTX_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_ULRU_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_ADD_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DEL_STAT); + MAC_REG_W32(R_AX_SS_DBG_1, val32); + + val32 = MAC_REG_R32(R_AX_SS_DBG_2); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_FWTX_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_RPTA_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_WDEA_STAT); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PLEA_STAT); + MAC_REG_W32(R_AX_SS_DBG_2, val32); + + val32 = MAC_REG_R32(R_AX_SS_MU_CTRL); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLMU_STATE); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLRU_STATE); + MAC_REG_W32(R_AX_SS_MU_CTRL, val32); + + switch (intn_idx) { + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_0: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_1: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_2: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_3: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_4: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_5: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_6: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_7: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_8: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_9: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_A: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_B: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_C: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_D: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_E: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_F: + case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_10: + break; + default: + return MACNOITEM; + } + val32 = MAC_REG_R32(R_AX_SS_DBG_3); + val32 = SET_CLR_WORD(val32, intn_idx, B_AX_SS_TOP_DBG_SEL); + MAC_REG_W32(R_AX_SS_DBG_3, val32); + break; + case MAC_AX_DP_SEL_DMAC_PKTIN: + /* To do... */ + break; + case MAC_AX_DP_SEL_WSEC_TOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_MPDU_PROCESSOR: + /* To do... */ + break; + case MAC_AX_DP_SEL_DMAC_APB_BRIDGE: + /* To do... */ + break; + case MAC_AX_DP_SEL_LTR_CTRL: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_PTCLTOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_MACTX: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_MACRX: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_PTCLTOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_MACTX: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_MACRX: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL: + /* To do... */ + break; + case MAC_AX_DP_SEL_CMAC_SHARE: + /* To do... */ + break; + /* WLAN_MAC */ + case MAC_AX_DP_SEL_WL_CPU_0: + case MAC_AX_DP_SEL_WL_CPU_F: + /* To do... */ + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +static u32 dp_intn_dump(struct mac_ax_adapter *adapter, + u8 dbg_sel, u8 intn_idx_max) +{ + struct mac_ax_dbgport_hw dp_hw; + u32 ret = MACSUCCESS; + u8 intn_idx; + + PLTFM_MEMSET(&dp_hw, 0, sizeof(struct mac_ax_dbgport_hw)); + + for (intn_idx = 0; intn_idx < intn_idx_max; intn_idx++) { + dp_hw.dbg_sel[0] = dbg_sel; + dp_hw.intn_idx[0] = intn_idx; + dp_hw.dbg_sel_16b[0] = MAC_AX_DP_SEL0_16B_0_15; + dp_hw.dbg_sel_4b[0] = MAC_AX_DP_SEL_4B_0_7; + dp_hw.dbg_sel[1] = dbg_sel; + dp_hw.intn_idx[1] = intn_idx; + dp_hw.dbg_sel_16b[1] = MAC_AX_DP_SEL1_16B_16_31; + dp_hw.dbg_sel_4b[1] = MAC_AX_DP_SEL_4B_0_7; + dp_hw.mode = MAC_AX_DP_MODE_DUMP; + + PLTFM_MSG_ERR("Internal index(%d):", intn_idx); + ret = mac_dbgport_hw_set(adapter, &dp_hw); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + + return ret; +} + +u32 dbgport_hw_dump(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw_en *dp_hw_en) +{ + u32 ret; + u8 dbg_sel, intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX; + + /* PCIE */ + if (dp_hw_en->pcie) { + for (dbg_sel = MAC_AX_DP_SEL_PCIE_0; + dbg_sel <= MAC_AX_DP_SEL_PCIE_C; dbg_sel++) { + switch (dbg_sel) { + case MAC_AX_DP_SEL_PCIE_0: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_0_MAX; + break; + case MAC_AX_DP_SEL_PCIE_1: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_1_MAX; + break; + case MAC_AX_DP_SEL_PCIE_2: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_2_MAX; + break; + case MAC_AX_DP_SEL_PCIE_3: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_3_MAX; + break; + case MAC_AX_DP_SEL_PCIE_4: + case MAC_AX_DP_SEL_PCIE_5: + case MAC_AX_DP_SEL_PCIE_6: + intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX; + break; + case MAC_AX_DP_SEL_PCIE_7: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_7_MAX; + break; + case MAC_AX_DP_SEL_PCIE_8: + intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_8_MAX; + break; + case MAC_AX_DP_SEL_PCIE_9: + case MAC_AX_DP_SEL_PCIE_A: + case MAC_AX_DP_SEL_PCIE_B: + case MAC_AX_DP_SEL_PCIE_C: + intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX; + break; + } + PLTFM_MSG_ERR("Dbgport PCIE(0x%x):\n", dbg_sel); + + ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + } + + /* WLAN_MAC */ + if (dp_hw_en->axidma) { + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + ret = MACFWNONRDY; + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + dbg_sel = MAC_AX_DP_SEL_AXIDMA; + intn_idx_max = MAC_AX_DP_INTN_IDX_AXIDMA_MAX; + PLTFM_MSG_TRACE("Dbgport axidma(0x%x):\n", dbg_sel); + + ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + + /* DMAC */ + if (dp_hw_en->wde_dle) { + dbg_sel = MAC_AX_DP_SEL_WDE_DLE; + intn_idx_max = MAC_AX_DP_INTN_IDX_WDE_DLE_MAX; + PLTFM_MSG_TRACE("Dbgport wde dle(0x%x):\n", dbg_sel); + + ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + + if (dp_hw_en->ple_dle) { + dbg_sel = MAC_AX_DP_SEL_PLE_DLE; + intn_idx_max = MAC_AX_DP_INTN_IDX_PLE_DLE_MAX; + PLTFM_MSG_TRACE("Dbgport ple dle(0x%x):\n", dbg_sel); + + ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + + if (dp_hw_en->sta_scheduler) { + dbg_sel = MAC_AX_DP_SEL_STA_SCHEDULER; + intn_idx_max = MAC_AX_DP_INTN_IDX_STA_SCHEDULER_MAX; + PLTFM_MSG_TRACE("Dbgport sta scheduler(0x%x):\n", dbg_sel); + + ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + return ret; + } + } + + return MACSUCCESS; +} + +u32 mac_dbgport_hw_set(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw *dp_hw) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS, backup = 0, val32; + u8 dbg_sel, dbg_sel_16b, dbg_sel_4b, sel_idx; + + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + + if (dp_hw->mode == MAC_AX_DP_MODE_LA) { + /* For AL mode, set GPIO PINMUX */ + val32 = 0xEEEEEEEE; + MAC_REG_W32(R_AX_GPIO0_7_FUNC_SEL, val32); + MAC_REG_W32(R_AX_GPIO8_15_FUNC_SEL, val32); + } else { + /* For dump mode, need backup R_AX_DBG_CTRL */ + backup = MAC_REG_R32(R_AX_DBG_CTRL); + } + + val32 = 0; + for (sel_idx = 0; sel_idx < MAC_AX_DP_SEL_NUM; sel_idx++) { + dbg_sel = dp_hw->dbg_sel[sel_idx]; + dbg_sel_16b = dp_hw->dbg_sel_16b[sel_idx]; + dbg_sel_4b = dp_hw->dbg_sel_4b[sel_idx]; + + /* dbg port select */ + if (sel_idx == 0) { + val32 = SET_CLR_WORD(val32, dbg_sel, B_AX_DBG_SEL0); + val32 |= (dbg_sel_16b ? B_AX_DBG_SEL0_16BIT : 0); + val32 = SET_CLR_WORD(val32, dbg_sel_4b, + B_AX_DBG_SEL0_4BIT); + } else { + val32 = SET_CLR_WORD(val32, dbg_sel, B_AX_DBG_SEL1); + val32 |= (dbg_sel_16b ? B_AX_DBG_SEL1_16BIT : 0); + val32 = SET_CLR_WORD(val32, dbg_sel_4b, + B_AX_DBG_SEL1_4BIT); + } + + /* internal index for each module */ + ret = dp_intn_idx_set(adapter, dp_hw, sel_idx); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s, %d\n", __func__, ret); + goto DONE; + } + } + MAC_REG_W32(R_AX_DBG_CTRL, val32); + + /* Enable */ + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + + /* dump info */ + dp_hw->rsp_val = MAC_REG_R32(R_AX_DBG_PORT_SEL); + PLTFM_MSG_TRACE("0x%08X\n", dp_hw->rsp_val); + + /* For dump mode, need restore R_AX_DBG_CTRL */ + if (dp_hw->mode == MAC_AX_DP_MODE_DUMP) + MAC_REG_W32(R_AX_DBG_CTRL, backup); + +DONE: + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + + return ret; +} + diff --git a/phl/hal_g6/mac/mac_ax/dbgport_hw.h b/phl/hal_g6/mac/mac_ax/dbgport_hw.h new file mode 100644 index 0000000..a2e1be3 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dbgport_hw.h @@ -0,0 +1,471 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_DBGPORT_HW_H_ +#define _MAC_AX_DBGPORT_HW_H_ + +#include "../mac_def.h" +#include "../mac_ax.h" + +#define MAC_AX_DP_MODE_DUMP 0 +#define MAC_AX_DP_MODE_LA 1 + +#define AXIDMA_DBG_SEL_INTN0_SH 0 +#define AXIDMA_DBG_SEL_INTN1_SH 3 +#define AXIDMA_DBG_SEL_INTN2_SH 6 + +/** + * @enum mac_ax_dbgport_sel + * + * @brief mac_ax_dbgport_sel + * + * @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_SYS_0 + * Please Place Description here. + * @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_SYS_1F + * Please Place Description here. + * @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_LAST + * Please Place Description here. + */ +enum mac_ax_dbgport_sel { + /* SYSTEM */ + MAC_AX_DP_SEL_SYS_0 = 0x0, // 0x0 -0x1F + MAC_AX_DP_SEL_SYS_1F = 0x1F, + /* PINMUX */ + MAC_AX_DP_SEL_PINMUX_0 = 0x20, // 0x20 - 0x27 + MAC_AX_DP_SEL_PINMUX_7 = 0x27, + /* LOADER */ + MAC_AX_DP_SEL_LOADER_0 = 0x28, //0x28-0x2B + MAC_AX_DP_SEL_LOADER_3 = 0x2B, + /* HMUX */ + MAC_AX_DP_SEL_HMUX_0 = 0x2C, //0x2C-0x2F + MAC_AX_DP_SEL_HMUX_3 = 0x2F, + /* PCIE */ + MAC_AX_DP_SEL_PCIE_0 = 0x30, + MAC_AX_DP_SEL_PCIE_1 = 0x31, + MAC_AX_DP_SEL_PCIE_2 = 0x32, + MAC_AX_DP_SEL_PCIE_3 = 0x33, + MAC_AX_DP_SEL_PCIE_4 = 0x34, + MAC_AX_DP_SEL_PCIE_5 = 0x35, + MAC_AX_DP_SEL_PCIE_6 = 0x36, + MAC_AX_DP_SEL_PCIE_7 = 0x37, + MAC_AX_DP_SEL_PCIE_8 = 0x38, + MAC_AX_DP_SEL_PCIE_9 = 0x39, + MAC_AX_DP_SEL_PCIE_A = 0x3A, + MAC_AX_DP_SEL_PCIE_B = 0x3B, + MAC_AX_DP_SEL_PCIE_C = 0x3C, + MAC_AX_DP_SEL_PCIE_D = 0x3D, + MAC_AX_DP_SEL_PCIE_E = 0x3E, + MAC_AX_DP_SEL_PCIE_F = 0x3F, + /* USB */ + MAC_AX_DP_SEL_USB_0 = 0x40, //0x40-0x4F + MAC_AX_DP_SEL_USB_F = 0x4F, + /* SDIO */ + MAC_AX_DP_SEL_SDIO_0 = 0x50, //0x50-0x5F + MAC_AX_DP_SEL_SDIO_F = 0x5F, + /* BT */ + MAC_AX_DP_SEL_BT = 0x60, + /* WLAN_MAC */ + MAC_AX_DP_SEL_AXIDMA = 0x71, + MAC_AX_DP_SEL_WLPHYDBG_GPIO = 0x72, + MAC_AX_DP_SEL_BTCOEXIST = 0x74, + MAC_AX_DP_SEL_LTECOEX = 0x75, + MAC_AX_DP_SEL_WLPHYDBG = 0x76, + MAC_AX_DP_SEL_WLAN_MAC_REG = 0x77, + MAC_AX_DP_SEL_WLAN_MAC_PMC = 0x78, + MAC_AX_DP_SEL_CALIB_TOP = 0x79, + /* MAC */ + // DMAC + MAC_AX_DP_SEL_DISPATCHER_TOP = 0x80, + MAC_AX_DP_SEL_WDE_DLE = 0x81, + MAC_AX_DP_SEL_PLE_DLE = 0x82, + MAC_AX_DP_SEL_WDRLS = 0x83, + MAC_AX_DP_SEL_DLE_CPUIO = 0x84, + MAC_AX_DP_SEL_BBRPT = 0x85, + MAC_AX_DP_SEL_TXPKTCTL = 0x86, + MAC_AX_DP_SEL_PKTBUFFER = 0x87, + MAC_AX_DP_SEL_DMAC_TABLE = 0x88, + MAC_AX_DP_SEL_STA_SCHEDULER = 0x89, + MAC_AX_DP_SEL_DMAC_PKTIN = 0x8A, + MAC_AX_DP_SEL_WSEC_TOP = 0x8B, + MAC_AX_DP_SEL_MPDU_PROCESSOR = 0x8C, + MAC_AX_DP_SEL_DMAC_APB_BRIDGE = 0x8D, + MAC_AX_DP_SEL_LTR_CTRL = 0x8E, + // CMAC_0 + MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP = 0xA0, + MAC_AX_DP_SEL_CMAC0_PTCLTOP = 0xA1, + MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP = 0xA2, + MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL = 0xA3, + MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE = 0xA4, + MAC_AX_DP_SEL_CMAC0_MACTX = 0xA5, + MAC_AX_DP_SEL_CMAC0_MACRX = 0xA6, + MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL = 0xA7, + // CMAC_1 + MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP = 0xB0, + MAC_AX_DP_SEL_CMAC1_PTCLTOP = 0xB1, + MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP = 0xB2, + MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL = 0xB3, + MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE = 0xB4, + MAC_AX_DP_SEL_CMAC1_MACTX = 0xB5, + MAC_AX_DP_SEL_CMAC1_MACRX = 0xB6, + MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL = 0xB7, + MAC_AX_DP_SEL_CMAC_SHARE = 0xC0, + /* WLAN_MAC */ + MAC_AX_DP_SEL_WL_CPU_0 = 0xF0, //0xF0-0xFF + MAC_AX_DP_SEL_WL_CPU_F = 0xFF, + + /* keep last */ + MAC_AX_DP_SEL_LAST +}; + +/** + * @enum mac_ax_dbgport_sel0_16b + * + * @brief mac_ax_dbgport_sel0_16b + * + * @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_0_15 + * Please Place Description here. + * @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_16_31 + * Please Place Description here. + * @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_END + * Please Place Description here. + */ +enum mac_ax_dbgport_sel0_16b { + MAC_AX_DP_SEL0_16B_0_15 = 0, + MAC_AX_DP_SEL0_16B_16_31 = 1, + MAC_AX_DP_SEL0_16B_END +}; + +/** + * @enum mac_ax_dbgport_sel1_16b + * + * @brief mac_ax_dbgport_sel1_16b + * + * @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_16_31 + * Please Place Description here. + * @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_0_15 + * Please Place Description here. + * @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_END + * Please Place Description here. + */ +enum mac_ax_dbgport_sel1_16b { + MAC_AX_DP_SEL1_16B_16_31 = 0, + MAC_AX_DP_SEL1_16B_0_15 = 1, + MAC_AX_DP_SEL1_16B_END +}; + +/** + * @enum mac_ax_dbgport_sel_4b + * + * @brief mac_ax_dbgport_sel_4b + * + * @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_0_7 + * Please Place Description here. + * @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_4_11 + * Please Place Description here. + * @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_8_15 + * Please Place Description here. + * @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_0_3_12_15 + * Please Place Description here. + * @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_END + * Please Place Description here. + */ +enum mac_ax_dbgport_sel_4b { + MAC_AX_DP_SEL_4B_0_7 = 0, + MAC_AX_DP_SEL_4B_4_11 = 1, + MAC_AX_DP_SEL_4B_8_15 = 2, + MAC_AX_DP_SEL_4B_0_3_12_15 = 3, + MAC_AX_DP_SEL_4B_END +}; + +/* For internal index */ +/* COMMON */ +enum mac_ax_dbgport_intn_idx_na { + MAC_AX_DP_INTN_IDX_NA = 0x0, + MAC_AX_DP_INTN_IDX_NA_MAX = 0x1, +}; + +/* SYSTEM */ +// MAC_AX_DP_SEL_SYS_0 = 0x0, // 0x0 -0x1F +// MAC_AX_DP_SEL_SYS_1F = 0x1F, + +/* PINMUX */ +// MAC_AX_DP_SEL_PINMUX_0 = 0x20, // 0x20 - 0x27 +// MAC_AX_DP_SEL_PINMUX_7 = 0x27, + +/* LOADER */ +// MAC_AX_DP_SEL_LOADER_0 = 0x28, //0x28-0x2B +// MAC_AX_DP_SEL_LOADER_3 = 0x2B, + +/* HMUX */ +// MAC_AX_DP_SEL_HMUX_0 = 0x2C, //0x2C-0x2F +// MAC_AX_DP_SEL_HMUX_3 = 0x2F, + +/* PCIE */ +// MAC_AX_DP_SEL_PCIE_0 = 0x30, +enum mac_ax_dbgport_intn_idx_pcie_0 { + MAC_AX_DP_INTN_IDX_PCIE_0_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_0_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_0_2 = 0x2, + MAC_AX_DP_INTN_IDX_PCIE_0_3 = 0x3, + MAC_AX_DP_INTN_IDX_PCIE_0_MAX = 0x4 +}; + +// MAC_AX_DP_SEL_PCIE_1 = 0x31, +enum mac_ax_dbgport_intn_idx_pcie_1 { + MAC_AX_DP_INTN_IDX_PCIE_1_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_1_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_1_2 = 0x2, + MAC_AX_DP_INTN_IDX_PCIE_1_3 = 0x3, + MAC_AX_DP_INTN_IDX_PCIE_1_4 = 0x4, + MAC_AX_DP_INTN_IDX_PCIE_1_MAX = 0x5 +}; + +// MAC_AX_DP_SEL_PCIE_2 = 0x32, +enum mac_ax_dbgport_intn_idx_pcie_2 { + MAC_AX_DP_INTN_IDX_PCIE_2_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_2_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_2_MAX = 0x2 +}; + +// MAC_AX_DP_SEL_PCIE_3 = 0x33, +enum mac_ax_dbgport_intn_idx_pcie_3 { + MAC_AX_DP_INTN_IDX_PCIE_3_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_3_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_3_2 = 0x2, + MAC_AX_DP_INTN_IDX_PCIE_3_3 = 0x3, + MAC_AX_DP_INTN_IDX_PCIE_3_4 = 0x4, + MAC_AX_DP_INTN_IDX_PCIE_3_5 = 0x5, + MAC_AX_DP_INTN_IDX_PCIE_3_MAX = 0x6 +}; + +// MAC_AX_DP_SEL_PCIE_4 = 0x34, +// MAC_AX_DP_SEL_PCIE_5 = 0x35, +// MAC_AX_DP_SEL_PCIE_6 = 0x36, +// MAC_AX_DP_SEL_PCIE_7 = 0x37, +enum mac_ax_dbgport_intn_idx_pcie_7 { + MAC_AX_DP_INTN_IDX_PCIE_7_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_7_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_7_2 = 0x2, + MAC_AX_DP_INTN_IDX_PCIE_7_3 = 0x3, + MAC_AX_DP_INTN_IDX_PCIE_7_4 = 0x4, + MAC_AX_DP_INTN_IDX_PCIE_7_MAX = 0x5 +}; + +// MAC_AX_DP_SEL_PCIE_8 = 0x38, +enum mac_ax_dbgport_intn_idx_pcie_8 { + MAC_AX_DP_INTN_IDX_PCIE_8_0 = 0x0, + MAC_AX_DP_INTN_IDX_PCIE_8_1 = 0x1, + MAC_AX_DP_INTN_IDX_PCIE_8_2 = 0x2, + MAC_AX_DP_INTN_IDX_PCIE_8_3 = 0x3, + MAC_AX_DP_INTN_IDX_PCIE_8_4 = 0x4, + MAC_AX_DP_INTN_IDX_PCIE_8_5 = 0x5, + MAC_AX_DP_INTN_IDX_PCIE_8_6 = 0x6, + MAC_AX_DP_INTN_IDX_PCIE_8_MAX = 0x7 +}; + +// MAC_AX_DP_SEL_PCIE_9 = 0x39, +// MAC_AX_DP_SEL_PCIE_A = 0x3A, +// MAC_AX_DP_SEL_PCIE_B = 0x3B, +// MAC_AX_DP_SEL_PCIE_C = 0x3C, +// MAC_AX_DP_SEL_PCIE_D = 0x3D, +// MAC_AX_DP_SEL_PCIE_E = 0x3E, +// MAC_AX_DP_SEL_PCIE_F = 0x3F, + +/* USB */ +// MAC_AX_DP_SEL_USB_0 = 0x40, //0x40-0x4F +// MAC_AX_DP_SEL_USB_F = 0x4F, + +/* SDIO */ +// MAC_AX_DP_SEL_SDIO_0 = 0x50, //0x50-0x5F +// MAC_AX_DP_SEL_SDIO_F = 0x5F, + +/* BT */ +// MAC_AX_DP_SEL_BT = 0x60, + +/* WLAN_MAC */ +// MAC_AX_DP_SEL_AXIDMA = 0x71, +enum mac_ax_dbgport_intn_idx_axidma { + MAC_AX_DP_INTN_IDX_AXIDMA_0 = 0x0, + MAC_AX_DP_INTN_IDX_AXIDMA_1 = 0x1, + MAC_AX_DP_INTN_IDX_AXIDMA_2 = 0x2, + MAC_AX_DP_INTN_IDX_AXIDMA_3 = 0x3, + MAC_AX_DP_INTN_IDX_AXIDMA_4 = 0x4, + MAC_AX_DP_INTN_IDX_AXIDMA_5 = 0x5, + MAC_AX_DP_INTN_IDX_AXIDMA_6 = 0x6, + MAC_AX_DP_INTN_IDX_AXIDMA_7 = 0x7, + MAC_AX_DP_INTN_IDX_AXIDMA_8 = 0x8, + MAC_AX_DP_INTN_IDX_AXIDMA_9 = 0x9, + MAC_AX_DP_INTN_IDX_AXIDMA_A = 0xA, + MAC_AX_DP_INTN_IDX_AXIDMA_B = 0xB, + MAC_AX_DP_INTN_IDX_AXIDMA_C = 0xC, + MAC_AX_DP_INTN_IDX_AXIDMA_D = 0xD, + MAC_AX_DP_INTN_IDX_AXIDMA_MAX = 0xE +}; + +// MAC_AX_DP_SEL_WLPHYDBG_GPIO = 0x72, +// MAC_AX_DP_SEL_BTCOEXIST = 0x74, +// MAC_AX_DP_SEL_LTECOEX = 0x75, +// MAC_AX_DP_SEL_WLPHYDBG = 0x76, +// MAC_AX_DP_SEL_WLAN_MAC_REG = 0x77, +// MAC_AX_DP_SEL_WLAN_MAC_PMC = 0x78, +// MAC_AX_DP_SEL_CALIB_TOP = 0x79, + +/* MAC */ +// DMAC +// MAC_AX_DP_SEL_DISPATCHER_TOP = 0x80, +// MAC_AX_DP_SEL_WDE_DLE = 0x81, +enum mac_ax_dbgport_intn_idx_wde_dle { + MAC_AX_DP_INTN_IDX_WDE_DLE_0 = 0x0, + MAC_AX_DP_INTN_IDX_WDE_DLE_1 = 0x1, + MAC_AX_DP_INTN_IDX_WDE_DLE_2 = 0x2, + MAC_AX_DP_INTN_IDX_WDE_DLE_3 = 0x3, + MAC_AX_DP_INTN_IDX_WDE_DLE_4 = 0x4, + MAC_AX_DP_INTN_IDX_WDE_DLE_5 = 0x5, + MAC_AX_DP_INTN_IDX_WDE_DLE_6 = 0x6, + MAC_AX_DP_INTN_IDX_WDE_DLE_7 = 0x7, + MAC_AX_DP_INTN_IDX_WDE_DLE_8 = 0x8, + MAC_AX_DP_INTN_IDX_WDE_DLE_9 = 0x9, + MAC_AX_DP_INTN_IDX_WDE_DLE_A = 0xA, + MAC_AX_DP_INTN_IDX_WDE_DLE_B = 0xB, + MAC_AX_DP_INTN_IDX_WDE_DLE_C = 0xC, + MAC_AX_DP_INTN_IDX_WDE_DLE_D = 0xD, + MAC_AX_DP_INTN_IDX_WDE_DLE_E = 0xE, + MAC_AX_DP_INTN_IDX_WDE_DLE_F = 0xF, + MAC_AX_DP_INTN_IDX_WDE_DLE_10 = 0x10, + MAC_AX_DP_INTN_IDX_WDE_DLE_11 = 0x11, + MAC_AX_DP_INTN_IDX_WDE_DLE_12 = 0x12, + MAC_AX_DP_INTN_IDX_WDE_DLE_13 = 0x13, + MAC_AX_DP_INTN_IDX_WDE_DLE_14 = 0x14, + MAC_AX_DP_INTN_IDX_WDE_DLE_15 = 0x15, + MAC_AX_DP_INTN_IDX_WDE_DLE_16 = 0x16, + MAC_AX_DP_INTN_IDX_WDE_DLE_17 = 0x17, + MAC_AX_DP_INTN_IDX_WDE_DLE_18 = 0x18, + MAC_AX_DP_INTN_IDX_WDE_DLE_MAX = 0x19 +}; + +// MAC_AX_DP_SEL_PLE_DLE = 0x82, +enum mac_ax_dbgport_intn_idx_ple_dle { + MAC_AX_DP_INTN_IDX_PLE_DLE_0 = 0x0, + MAC_AX_DP_INTN_IDX_PLE_DLE_1 = 0x1, + MAC_AX_DP_INTN_IDX_PLE_DLE_2 = 0x2, + MAC_AX_DP_INTN_IDX_PLE_DLE_3 = 0x3, + MAC_AX_DP_INTN_IDX_PLE_DLE_4 = 0x4, + MAC_AX_DP_INTN_IDX_PLE_DLE_5 = 0x5, + MAC_AX_DP_INTN_IDX_PLE_DLE_6 = 0x6, + MAC_AX_DP_INTN_IDX_PLE_DLE_7 = 0x7, + MAC_AX_DP_INTN_IDX_PLE_DLE_8 = 0x8, + MAC_AX_DP_INTN_IDX_PLE_DLE_9 = 0x9, + MAC_AX_DP_INTN_IDX_PLE_DLE_A = 0xA, + MAC_AX_DP_INTN_IDX_PLE_DLE_B = 0xB, + MAC_AX_DP_INTN_IDX_PLE_DLE_C = 0xC, + MAC_AX_DP_INTN_IDX_PLE_DLE_D = 0xD, + MAC_AX_DP_INTN_IDX_PLE_DLE_E = 0xE, + MAC_AX_DP_INTN_IDX_PLE_DLE_F = 0xF, + MAC_AX_DP_INTN_IDX_PLE_DLE_10 = 0x10, + MAC_AX_DP_INTN_IDX_PLE_DLE_11 = 0x11, + MAC_AX_DP_INTN_IDX_PLE_DLE_12 = 0x12, + MAC_AX_DP_INTN_IDX_PLE_DLE_13 = 0x13, + MAC_AX_DP_INTN_IDX_PLE_DLE_14 = 0x14, + MAC_AX_DP_INTN_IDX_PLE_DLE_15 = 0x15, + MAC_AX_DP_INTN_IDX_PLE_DLE_16 = 0x16, + MAC_AX_DP_INTN_IDX_PLE_DLE_17 = 0x17, + MAC_AX_DP_INTN_IDX_PLE_DLE_18 = 0x18, + MAC_AX_DP_INTN_IDX_PLE_DLE_19 = 0x19, + MAC_AX_DP_INTN_IDX_PLE_DLE_1A = 0x1A, + MAC_AX_DP_INTN_IDX_PLE_DLE_1B = 0x1B, + MAC_AX_DP_INTN_IDX_PLE_DLE_MAX = 0x1C +}; + +// MAC_AX_DP_SEL_WDRLS = 0x83, +// MAC_AX_DP_SEL_DLE_CPUIO = 0x84, +// MAC_AX_DP_SEL_BBRPT = 0x85, +// MAC_AX_DP_SEL_TXPKTCTL = 0x86, +// MAC_AX_DP_SEL_PKTBUFFER = 0x87, +// MAC_AX_DP_SEL_DMAC_TABLE = 0x88, +// MAC_AX_DP_SEL_STA_SCHEDULER = 0x89, +enum mac_ax_dbgport_intn_idx_sta_scheduler { + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_0 = 0x0, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_1 = 0x1, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_2 = 0x2, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_3 = 0x3, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_4 = 0x4, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_5 = 0x5, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_6 = 0x6, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_7 = 0x7, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_8 = 0x8, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_9 = 0x9, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_A = 0xA, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_B = 0xB, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_C = 0xC, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_D = 0xD, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_E = 0xE, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_F = 0xF, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_10 = 0x10, + MAC_AX_DP_INTN_IDX_STA_SCHEDULER_MAX = 0x11 +}; + +// MAC_AX_DP_SEL_DMAC_PKTIN = 0x8A, +// MAC_AX_DP_SEL_WSEC_TOP = 0x8B, +// MAC_AX_DP_SEL_MPDU_PROCESSOR = 0x8C, +// MAC_AX_DP_SEL_DMAC_APB_BRIDGE = 0x8D, +// MAC_AX_DP_SEL_LTR_CTRL = 0x8E, +// CMAC_0 +// MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP = 0xA0, +// MAC_AX_DP_SEL_CMAC0_PTCLTOP = 0xA1, +// MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP = 0xA2, +// MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL = 0xA3, +// MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE = 0xA4, +// MAC_AX_DP_SEL_CMAC0_MACTX = 0xA5, +// MAC_AX_DP_SEL_CMAC0_MACRX = 0xA6, +// MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL = 0xA7, +// CMAC_1 +// MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP = 0xB0, +// MAC_AX_DP_SEL_CMAC1_PTCLTOP = 0xB1, +// MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP = 0xB2, +// MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL = 0xB3, +// MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE = 0xB4, +// MAC_AX_DP_SEL_CMAC1_MACTX = 0xB5, +// MAC_AX_DP_SEL_CMAC1_MACRX = 0xB6, +// MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL = 0xB7, +// MAC_AX_DP_SEL_CMAC_SHARE = 0xC0, + +/* WLAN_MAC */ +// MAC_AX_DP_SEL_WL_CPU_0 = 0xF0, //0xF0-0xFF +// MAC_AX_DP_SEL_WL_CPU_F = 0xFF, + +/** + * @brief mac_dbgport_hw_dump + * + * @param *adapter + * @param *dp_hw_en + * @return Please Place Description here. + * @retval u32 + */ +u32 dbgport_hw_dump(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw_en *dp_hw_en); + +/** + * @brief mac_dbgport_hw_set + * + * @param *adapter + * @param *dbgport_hw + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dbgport_hw_set(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw *dp_hw); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/dle.c b/phl/hal_g6/mac/mac_ax/dle.c new file mode 100644 index 0000000..4ee9d11 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dle.c @@ -0,0 +1,2834 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "dle.h" + +/* PCIE 64 */ +static struct dle_size_t wde_size0 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 4095, /* lnk_pge_num */ + 1, /* unlnk_pge_num */ +}; + +/* SDIO, PCIE STF, USB */ +static struct dle_size_t wde_size1 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 768, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* PCIE 128 */ +static struct dle_size_t wde_size2 = { + MAC_AX_WDE_PG_128, /* pge_size */ + 2016, /* lnk_pge_num */ + 32, /* unlnk_pge_num */ +}; + +/* PCIE SU TP */ +static struct dle_size_t wde_size3 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 496, /* lnk_pge_num */ + 3600, /* unlnk_pge_num */ +}; + +/* DLFW */ +static struct dle_size_t wde_size4 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 0, /* lnk_pge_num */ + 4096, /* unlnk_pge_num */ +}; + +/* PCIE BCN TEST */ +static struct dle_size_t wde_size5 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 3904, /* lnk_pge_num */ + 64, /* unlnk_pge_num */ +}; + +/* PCIE 64 */ +static struct dle_size_t wde_size6 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 1024, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* PCIE 128 */ +static struct dle_size_t wde_size7 = { + MAC_AX_WDE_PG_128, /* pge_size */ + 960, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* PCIE STF, USB */ +static struct dle_size_t wde_size8 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 256, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* DLFW */ +static struct dle_size_t wde_size9 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 0, /* lnk_pge_num */ + 1024, /* unlnk_pge_num */ +}; + +/* LA-PCIE */ +static struct dle_size_t wde_size10 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 1408, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* LA-PCIE */ +static struct dle_size_t wde_size11 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 256, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* LA-SDIO */ +static struct dle_size_t wde_size12 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 328, /* lnk_pge_num */ + 56, /* unlnk_pge_num */ +}; + +/* SDIO SCC */ +static struct dle_size_t wde_size13 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 128, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* SDIO LA */ +static struct dle_size_t wde_size14 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 124, /* lnk_pge_num */ + 4, /* unlnk_pge_num */ +}; + +/* LA-USB 8852A*/ +static struct dle_size_t wde_size15 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 384, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* LA-USB 8852B*/ +static struct dle_size_t wde_size16 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 124, /* lnk_pge_num */ + 4, /* unlnk_pge_num */ +}; + +/* 8852C USB */ +static struct dle_size_t wde_size17 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 332, /* lnk_pge_num */ + 52, /* unlnk_pge_num */ +}; + +/* 8852C DLFW */ +static struct dle_size_t wde_size18 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 0, /* lnk_pge_num */ + 2048, /* unlnk_pge_num */ +}; + +/* 8852C PCIE SCC */ +static struct dle_size_t wde_size19 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 3328, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* 8852C PCIE DBCC */ +static struct dle_size_t wde_size20 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 3328, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* 8852C PCIE SCC/DBCC STF */ +static struct dle_size_t wde_size21 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 256, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* 8852C PCIE LA */ +static struct dle_size_t wde_size22 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 3224, /* lnk_pge_num */ + 104, /* unlnk_pge_num */ +}; + +/* 8852B PCIE STF AB */ +static struct dle_size_t wde_size23 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 216, /* lnk_pge_num */ + 40, /* unlnk_pge_num */ +}; + +/* 8852B USB CABV*/ +static struct dle_size_t wde_size24 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 216, /* lnk_pge_num */ + 40, /* unlnk_pge_num */ +}; + +/* 8852B USB2.0 */ +static struct dle_size_t wde_size25 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 242, /* lnk_pge_num */ + 14, /* unlnk_pge_num */ +}; + +/* 8852AU ccv*/ +static struct dle_size_t wde_size26 = { + MAC_AX_WDE_PG_64, /* pge_size */ + 760, /* lnk_pge_num */ + 8, /* unlnk_pge_num */ +}; + +/* PCIE */ +static struct dle_size_t ple_size0 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1520, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* SDIO, USB */ +static struct dle_size_t ple_size1 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 3184, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* PCIE STF */ +static struct dle_size_t ple_size2 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 3184, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* PCIE SU TP */ +static struct dle_size_t ple_size3 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 330, /* lnk_pge_num */ + 1206, /* unlnk_pge_num */ +}; + +/* DLFW */ +static struct dle_size_t ple_size4 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 64, /* lnk_pge_num */ + 1472, /* unlnk_pge_num */ +}; + +/* PCIE BCN TEST */ +static struct dle_size_t ple_size5 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1520, /* lnk_pge_num */ + 80, /* unlnk_pge_num */ +}; + +/* PCIE 64 */ +static struct dle_size_t ple_size6 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1008, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* PCIE STF, USB */ +static struct dle_size_t ple_size7 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1392, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* DLFW */ +static struct dle_size_t ple_size8 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 64, /* lnk_pge_num */ + 960, /* unlnk_pge_num */ +}; + +/* PCIE 128 */ +static struct dle_size_t ple_size9 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 576, /* lnk_pge_num */ + 0, /* unlnk_pge_num */ +}; + +/* LA-PCIE 8852A*/ +static struct dle_size_t ple_size10 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 816, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* LA-PCIE */ +static struct dle_size_t ple_size11 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 368, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* LA-SDIO 8852A*/ +static struct dle_size_t ple_size12 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1328, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* SDIO SCC */ +static struct dle_size_t ple_size13 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1456, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* SDIO LA */ +static struct dle_size_t ple_size14 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 432, /* lnk_pge_num */ + 528, /* unlnk_pge_num */ +}; + +/* LA-USB 8852A */ +static struct dle_size_t ple_size15 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1328, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* LA-USB 8852B */ +static struct dle_size_t ple_size16 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 432, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852C USB */ +static struct dle_size_t ple_size17 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 3336, /* lnk_pge_num */ + 56, /* unlnk_pge_num */ +}; + +/* 8852C DLFW*/ +static struct dle_size_t ple_size18 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 2544, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852C PCIE SCC */ +static struct dle_size_t ple_size19 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1904, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852C PCIE DBCC */ +static struct dle_size_t ple_size20 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1904, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852C PCIE SCC/DBCC STF */ +static struct dle_size_t ple_size21 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 3440, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852C PCIE LA */ +static struct dle_size_t ple_size22 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1904, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852B PCIE AB */ +static struct dle_size_t ple_size23 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 496, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852B PCIE STF AB */ +static struct dle_size_t ple_size24 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 880, /* lnk_pge_num */ + 16, /* unlnk_pge_num */ +}; + +/* 8852B DLFW AB */ +static struct dle_size_t ple_size25 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 64, /* lnk_pge_num */ + 448, /* unlnk_pge_num */ +}; + +/* 8852B USB CABV*/ +static struct dle_size_t ple_size26 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 872, /* lnk_pge_num */ + 24, /* unlnk_pge_num */ +}; + +/* 8852B USB2.0 */ +static struct dle_size_t ple_size27 = { + MAC_AX_PLE_PG_128, /* pge_size */ + 1402, /* lnk_pge_num */ + 6, /* unlnk_pge_num */ +}; + +/* PCIE 64 */ +static struct wde_quota_t wde_qt0 = { + 3792, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 107, /* cpu_io */ +}; + +/* SDIO, PCIE STF, USB */ +static struct wde_quota_t wde_qt1 = { + 512, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 60, /* cpu_io */ +}; + +/* PCIE 128 */ +static struct wde_quota_t wde_qt2 = { + 1896, /* hif */ + 98, /* wcpu */ + 0, /* pkt_in */ + 22, /* cpu_io */ +}; + +/* PCIE SU TP */ +static struct wde_quota_t wde_qt3 = { + 256, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 44, /* cpu_io */ +}; + +/* DLFW */ +static struct wde_quota_t wde_qt4 = { + 0, /* hif */ + 0, /* wcpu */ + 0, /* pkt_in */ + 0, /* cpu_io */ +}; + +/* PCIE BCN TEST */ +static struct wde_quota_t wde_qt5 = { + 3666, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 44, /* cpu_io */ +}; + +/* PCIE 64 */ +static struct wde_quota_t wde_qt6 = { + 960, /* hif */ + 48, /* wcpu */ + 0, /* pkt_in */ + 16, /* cpu_io */ +}; + +/* PCIE 128 */ +static struct wde_quota_t wde_qt7 = { + 896, /* hif */ + 56, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* PCIE STF, USB */ +static struct wde_quota_t wde_qt8 = { + 204, /* hif */ + 44, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* LA-PCIE 8852A*/ +static struct wde_quota_t wde_qt9 = { + 1172, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 40, /* cpu_io */ +}; + +/* LA-PCIE */ +static struct wde_quota_t wde_qt10 = { + 200, /* hif */ + 48, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* LA-SDIO 8852A*/ +static struct wde_quota_t wde_qt11 = { + 128, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 4, /* cpu_io */ +}; + +/* SDIO SCC */ +static struct wde_quota_t wde_qt12 = { + 112, /* hif */ + 8, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* SDIO LA */ +static struct wde_quota_t wde_qt13 = { + 112, /* hif */ + 4, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* LA USB 8852A */ +static struct wde_quota_t wde_qt14 = { + 256, /* hif */ + 118, /* wcpu */ + 0, /* pkt_in */ + 10, /* cpu_io */ +}; + +/* LA USB 8852B */ +static struct wde_quota_t wde_qt15 = { + 112, /* hif */ + 4, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/*8852C USB */ +static struct wde_quota_t wde_qt16 = { + 292, /* hif */ + 20, /* wcpu */ + 0, /* pkt_in */ + 20, /* cpu_io */ +}; + +/*8852C DLFW */ +static struct wde_quota_t wde_qt17 = { + 0, /* hif */ + 0, /* wcpu */ + 0, /* pkt_in */ + 0, /* cpu_io */ +}; + +/* 8852C PCIE SCC */ +static struct wde_quota_t wde_qt18 = { + 3228, /* hif */ + 60, /* wcpu */ + 0, /* pkt_in */ + 40, /* cpu_io */ +}; + +/* 8852C PCIE DBCC */ +static struct wde_quota_t wde_qt19 = { + 3218, /* hif */ + 60, /* wcpu */ + 0, /* pkt_in */ + 50, /* cpu_io */ +}; + +/* 8852C PCIE SCC STF */ +static struct wde_quota_t wde_qt20 = { + 216, /* hif */ + 20, /* wcpu */ + 0, /* pkt_in */ + 20, /* cpu_io */ +}; + +/* 8852C PCIE DBCC STF */ +static struct wde_quota_t wde_qt21 = { + 152, /* hif */ + 64, /* wcpu */ + 0, /* pkt_in */ + 40, /* cpu_io */ +}; + +/* 8852C PCIE LA */ +static struct wde_quota_t wde_qt22 = { + 3120, /* hif */ + 64, /* wcpu */ + 0, /* pkt_in */ + 40, /* cpu_io */ +}; + +/* 8852B PCIE STF AB */ +static struct wde_quota_t wde_qt23 = { + 164, /* hif */ + 44, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* 8852B USB CABV */ +static struct wde_quota_t wde_qt24 = { + 164, /* hif */ + 44, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* 8852B USB2.0 */ +static struct wde_quota_t wde_qt25 = { + 190, /* hif */ + 44, /* wcpu */ + 0, /* pkt_in */ + 8, /* cpu_io */ +}; + +/* PCIE DBCC */ +static struct ple_quota_t ple_qt0 = { + 264, /* cmac0_tx */ + 66, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* 8852AU ccv */ +static struct wde_quota_t wde_qt26 = { + 504, /* hif */ + 196, /* wcpu */ + 0, /* pkt_in */ + 60, /* cpu_io */ +}; + +/* PCIE DBCC */ +static struct ple_quota_t ple_qt1 = { + 264, /* cmac0_tx */ + 66, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 941, /* cmac0_dma */ + 679, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 240, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO */ +static struct ple_quota_t ple_qt2 = { + 1536, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 26, /* mpdu_proc */ + 360, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO */ +static struct ple_quota_t ple_qt3 = { + 1536, /* cmac0_tx */ + 0, /* cmac1_tx */ + 1149, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 1159, /* mpdu_proc */ + 1493, /* cmac0_dma */ + 0, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 120, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE SCC */ +static struct ple_quota_t ple_qt4 = { + 264, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE SCC */ +static struct ple_quota_t ple_qt5 = { + 264, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 1101, /* cmac0_dma */ + 0, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 120, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO */ +static struct ple_quota_t ple_qt6 = { + 2048, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 26, /* mpdu_proc */ + 360, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO */ +static struct ple_quota_t ple_qt7 = { + 2048, /* cmac0_tx */ + 0, /* cmac1_tx */ + 530, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 540, /* mpdu_proc */ + 874, /* cmac0_dma */ + 608, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 240, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF SCC */ +static struct ple_quota_t ple_qt8 = { + 1536, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF SCC */ +static struct ple_quota_t ple_qt9 = { + 2686, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 1506, /* cmac0_dma */ + 0, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 120, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF DBCC */ +static struct ple_quota_t ple_qt10 = { + 2272, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF DBCC */ +static struct ple_quota_t ple_qt11 = { + 2579, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 663, /* cmac0_dma */ + 401, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 240, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE SU TP */ +static struct ple_quota_t ple_qt12 = { + 66, /* cmac0_tx */ + 66, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 25, /* cmac0_dma */ + 25, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* DLFW */ +static struct ple_quota_t ple_qt13 = { + 0, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 0, /* wcpu */ + 0, /* mpdu_proc */ + 0, /* cmac0_dma */ + 0, /* cma1_dma */ + 0, /* bb_rpt */ + 0, /* wd_rel */ + 0, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE BCN TEST */ +static struct ple_quota_t ple_qt14 = { + 588, /* cmac0_tx */ + 147, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 26, /* mpdu_proc */ + 356, /* cmac0_dma */ + 89, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 80, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE BCN TEST */ +static struct ple_quota_t ple_qt15 = { + 688, /* cmac0_tx */ + 247, /* cmac1_tx */ + 116, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 126, /* mpdu_proc */ + 456, /* cmac0_dma */ + 189, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 80, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB DBCC */ +static struct ple_quota_t ple_qt16 = { + 2048, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 360, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB DBCC */ +static struct ple_quota_t ple_qt17 = { + 2048, /* cmac0_tx */ + 0, /* cmac1_tx */ + 515, /* c2h */ + 48, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 859, /* cmac0_dma */ + 593, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 240, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE 64 */ +static struct ple_quota_t ple_qt18 = { + 147, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE 64 */ +static struct ple_quota_t ple_qt19 = { + 147, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 580, /* wcpu */ + 13, /* mpdu_proc */ + 745, /* cmac0_dma */ + 0, /* cma1_dma */ + 599, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF */ +static struct ple_quota_t ple_qt20 = { + 962, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 88, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE STF */ +static struct ple_quota_t ple_qt21 = { + 1023, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 149, /* wcpu */ + 13, /* mpdu_proc */ + 239, /* cmac0_dma */ + 0, /* cma1_dma */ + 93, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE 128 */ +static struct ple_quota_t ple_qt22 = { + 269, /* cmac0_tx */ + 0, /* cmac1_tx */ + 18, /* c2h */ + 20, /* h2c */ + 15, /* wcpu */ + 28, /* mpdu_proc */ + 180, /* cmac0_dma */ + 0, /* cma1_dma */ + 34, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA PCIE 8852A*/ +static struct ple_quota_t ple_qt23 = { + 104, /* cmac0_tx */ + 26, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA PCIE 8852A*/ +static struct ple_quota_t ple_qt24 = { + 104, /* cmac0_tx */ + 26, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 437, /* cmac0_dma */ + 175, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 89, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB SCC */ +static struct ple_quota_t ple_qt25 = { + 1536, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 360, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB SCC */ +static struct ple_quota_t ple_qt26 = { + 2654, /* cmac0_tx */ + 0, /* cmac1_tx */ + 1134, /* c2h */ + 48, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 1478, /* cmac0_dma */ + 0, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 120, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB3.0 52B */ +static struct ple_quota_t ple_qt27 = { + 962, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 88, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB3.0 52B */ +static struct ple_quota_t ple_qt28 = { + 962, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 48, /* h2c */ + 121, /* wcpu */ + 13, /* mpdu_proc */ + 211, /* cmac0_dma */ + 0, /* cma1_dma */ + 65, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE SU TP */ +static struct ple_quota_t ple_qt29 = { + 66, /* cmac0_tx */ + 66, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 1224, /* cmac0_dma */ + 1224, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 240, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE LA */ +static struct ple_quota_t ple_qt30 = { + 51, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* PCIE LA */ +static struct ple_quota_t ple_qt31 = { + 74, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 36, /* wcpu */ + 13, /* mpdu_proc */ + 201, /* cmac0_dma */ + 0, /* cma1_dma */ + 55, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA SDIO 8852A*/ +static struct ple_quota_t ple_qt32 = { + 500, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 26, /* wcpu */ + 26, /* mpdu_proc */ + 360, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA SDIO 8852A*/ +static struct ple_quota_t ple_qt33 = { + 500, /* cmac0_tx */ + 0, /* cmac1_tx */ + 222, /* c2h */ + 20, /* h2c */ + 64, /* wcpu */ + 232, /* mpdu_proc */ + 566, /* cmac0_dma */ + 300, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 214, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO SCC */ +static struct ple_quota_t ple_qt34 = { + 836, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 16, /* h2c */ + 26, /* wcpu */ + 0, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 16, /* bb_rpt */ + 1, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO SCC */ +static struct ple_quota_t ple_qt35 = { + 836, /* cmac0_tx */ + 0, /* cmac1_tx */ + 375, /* c2h */ + 16, /* h2c */ + 385, /* wcpu */ + 0, /* mpdu_proc */ + 537, /* cmac0_dma */ + 0, /* cma1_dma */ + 375, /* bb_rpt */ + 1, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO LA */ +static struct ple_quota_t ple_qt36 = { + 86, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 52, /* wcpu */ + 26, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* SDIO LA */ +static struct ple_quota_t ple_qt37 = { + 86, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 52, /* wcpu */ + 26, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA USB 8852A*/ +static struct ple_quota_t ple_qt38 = { + 512, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 60, /* h2c */ + 26, /* wcpu */ + 13, /* mpdu_proc */ + 360, /* cmac0_dma */ + 94, /* cma1_dma */ + 32, /* bb_rpt */ + 40, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA USB 8852A*/ +static struct ple_quota_t ple_qt39 = { + 512, /* cmac0_tx */ + 0, /* cmac1_tx */ + 184, /* c2h */ + 60, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 527, /* cmac0_dma */ + 261, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 175, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA USB 8852B*/ +static struct ple_quota_t ple_qt40 = { + 26, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 52, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* LA USB 8852B*/ +static struct ple_quota_t ple_qt41 = { + 26, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 48, /* h2c */ + 97, /* wcpu */ + 13, /* mpdu_proc */ + 223, /* cmac0_dma */ + 0, /* cma1_dma */ + 77, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB 52C */ +static struct ple_quota_t ple_qt42 = { + 1196, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 130, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 20, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* USB 52C */ +static struct ple_quota_t ple_qt43 = { + 2938, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 1755, /* wcpu */ + 13, /* mpdu_proc */ + 1872, /* cmac0_dma */ + 0, /* cma1_dma */ + 1774, /* bb_rpt */ + 20, /* wd_rel */ + 120, /* cpu_io */ + 1758, /* tx_rpt */ +}; + +/* DLFW 52C */ +static struct ple_quota_t ple_qt44 = { + 0, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 256, /* h2c */ + 0, /* wcpu */ + 0, /* mpdu_proc */ + 0, /* cmac0_dma */ + 0, /* cma1_dma */ + 0, /* bb_rpt */ + 0, /* wd_rel */ + 0, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* DLFW 52C */ +static struct ple_quota_t ple_qt45 = { + 0, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 256, /* h2c */ + 0, /* wcpu */ + 0, /* mpdu_proc */ + 0, /* cmac0_dma */ + 0, /* cma1_dma */ + 0, /* bb_rpt */ + 0, /* wd_rel */ + 0, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* 8852C PCIE SCC */ +static struct ple_quota_t ple_qt46 = { + 525, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 62, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* 8852C PCIE SCC */ +static struct ple_quota_t ple_qt47 = { + 525, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 1034, /* wcpu */ + 13, /* mpdu_proc */ + 1199, /* cmac0_dma */ + 0, /* cma1_dma */ + 1053, /* bb_rpt */ + 62, /* wd_rel */ + 160, /* cpu_io */ + 1037, /* tx_rpt */ +}; + +/* 8852C PCIE DBCC */ +static struct ple_quota_t ple_qt48 = { + 525, /* cmac0_tx */ + 200, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 178, /* cma1_dma */ + 32, /* bb_rpt */ + 62, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* 8852C PCIE DBCC */ +static struct ple_quota_t ple_qt49 = { + 525, /* cmac0_tx */ + 200, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 656, /* wcpu */ + 13, /* mpdu_proc */ + 821, /* cmac0_dma */ + 821, /* cma1_dma */ + 675, /* bb_rpt */ + 62, /* wd_rel */ + 160, /* cpu_io */ + 659, /* tx_rpt */ +}; + +/* 8852C PCIE SCC STF */ +static struct ple_quota_t ple_qt50 = { + 1248, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 130, /* cmac0_dma */ + 130, /* cma1_dma */ + 32, /* bb_rpt */ + 38, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* 8852C PCIE SCC STF */ +static struct ple_quota_t ple_qt51 = { + 3024, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 1789, /* wcpu */ + 13, /* mpdu_proc */ + 1906, /* cmac0_dma */ + 1906, /* cma1_dma */ + 1808, /* bb_rpt */ + 38, /* wd_rel */ + 40, /* cpu_io */ + 1792, /* tx_rpt */ +}; + +/* 8852C PCIE DBCC STF */ +static struct ple_quota_t ple_qt52 = { + 1664, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 130, /* cmac0_dma */ + 130, /* cma1_dma */ + 32, /* bb_rpt */ + 38, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* 8852C PCIE DBCC STF */ +static struct ple_quota_t ple_qt53 = { + 3024, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 1373, /* wcpu */ + 13, /* mpdu_proc */ + 1490, /* cmac0_dma */ + 1490, /* cma1_dma */ + 1392, /* bb_rpt */ + 38, /* wd_rel */ + 160, /* cpu_io */ + 1376, /* tx_rpt */ +}; + +/* 8852C PCIE LA */ +static struct ple_quota_t ple_qt54 = { + 300, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 13, /* wcpu */ + 13, /* mpdu_proc */ + 356, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 62, /* wd_rel */ + 8, /* cpu_io */ + 16, /* tx_rpt */ +}; + +/* 8852C PCIE LA */ +static struct ple_quota_t ple_qt55 = { + 300, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 1081, /* wcpu */ + 13, /* mpdu_proc */ + 1424, /* cmac0_dma */ + 0, /* cma1_dma */ + 1100, /* bb_rpt */ + 62, /* wd_rel */ + 160, /* cpu_io */ + 1084, /* tx_rpt */ +}; + +/* 8852B PCIE AB */ +static struct ple_quota_t ple_qt56 = { + 147, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 68, /* wcpu */ + 13, /* mpdu_proc */ + 233, /* cmac0_dma */ + 0, /* cma1_dma */ + 87, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* 8852B PCIE STF AB */ +static struct ple_quota_t ple_qt57 = { + 442, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 20, /* h2c */ + 88, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* 8852B PCIE STF AB*/ +static struct ple_quota_t ple_qt58 = { + 511, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 20, /* h2c */ + 157, /* wcpu */ + 13, /* mpdu_proc */ + 247, /* cmac0_dma */ + 0, /* cma1_dma */ + 101, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB 52B CABV*/ +static struct ple_quota_t ple_qt59 = { + 442, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 88, /* wcpu */ + 13, /* mpdu_proc */ + 178, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB 52B CABV*/ +static struct ple_quota_t ple_qt60 = { + 442, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 48, /* h2c */ + 121, /* wcpu */ + 13, /* mpdu_proc */ + 211, /* cmac0_dma */ + 0, /* cma1_dma */ + 65, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB2.0 52B */ +static struct ple_quota_t ple_qt61 = { + 780, /* cmac0_tx */ + 0, /* cmac1_tx */ + 16, /* c2h */ + 48, /* h2c */ + 88, /* wcpu */ + 13, /* mpdu_proc */ + 370, /* cmac0_dma */ + 0, /* cma1_dma */ + 32, /* bb_rpt */ + 14, /* wd_rel */ + 8, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* USB2.0 52B */ +static struct ple_quota_t ple_qt62 = { + 780, /* cmac0_tx */ + 0, /* cmac1_tx */ + 32, /* c2h */ + 48, /* h2c */ + 121, /* wcpu */ + 13, /* mpdu_proc */ + 403, /* cmac0_dma */ + 0, /* cma1_dma */ + 65, /* bb_rpt */ + 14, /* wd_rel */ + 24, /* cpu_io */ + 0, /* tx_rpt */ +}; + +/* 8852AU ccv */ +static struct ple_quota_t ple_qt63 = { + 2654, /* cmac0_tx */ + 0, /* cmac1_tx */ + 1134, /* c2h */ + 48, /* h2c */ + 64, /* wcpu */ + 13, /* mpdu_proc */ + 1478, /* cmac0_dma */ + 0, /* cma1_dma */ + 64, /* bb_rpt */ + 128, /* wd_rel */ + 120, /* cpu_io */ + 0, /* tx_rpt */ +}; + +#if MAC_AX_PCIE_SUPPORT +static struct dle_mem_t dle_mem_pcie_8852a[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size0, &ple_size0, /* wde_size, ple_size */ + &wde_qt0, &wde_qt0, /* wde_min_qt, wde_max_qt */ + &ple_qt4, &ple_qt5}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size0, &ple_size0, /* wde_size, ple_size */ + &wde_qt0, &wde_qt0, /* wde_min_qt, wde_max_qt */ + &ple_qt0, &ple_qt1}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC_STF, /* qta_mode */ + &wde_size1, &ple_size2, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt8, &ple_qt9}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC_STF, /* qta_mode */ + &wde_size1, &ple_size2, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt10, &ple_qt11}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SU_TP, /* qta_mode */ + &wde_size3, &ple_size3, /* wde_size, ple_size */ + &wde_qt3, &wde_qt3, /* wde_min_qt, wde_max_qt */ + &ple_qt12, &ple_qt29}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size4, &ple_size4, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size10, &ple_size10, /* wde_size, ple_size */ + &wde_qt9, &wde_qt9, /* wde_min_qt, wde_max_qt */ + &ple_qt23, &ple_qt24}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_pcie_8852b[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size6, &ple_size6, /* wde_size, ple_size */ + &wde_qt6, &wde_qt6, /* wde_min_qt, wde_max_qt */ + &ple_qt18, &ple_qt19}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC_STF, /* qta_mode */ + &wde_size8, &ple_size7, /* wde_size, ple_size */ + &wde_qt8, &wde_qt8, /* wde_min_qt, wde_max_qt */ + &ple_qt20, &ple_qt21}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size8, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size11, &ple_size11, /* wde_size, ple_size */ + &wde_qt10, &wde_qt10, /* wde_min_qt, wde_max_qt */ + &ple_qt30, &ple_qt31}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_pcie_8852b_cabv[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size6, &ple_size23, /* wde_size, ple_size */ + &wde_qt6, &wde_qt6, /* wde_min_qt, wde_max_qt */ + &ple_qt18, &ple_qt56}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC_STF, /* qta_mode */ + &wde_size23, &ple_size24, /* wde_size, ple_size */ + &wde_qt23, &wde_qt23, /* wde_min_qt, wde_max_qt */ + &ple_qt57, &ple_qt58}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size25, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size11, &ple_size11, /* wde_size, ple_size */ + &wde_qt10, &wde_qt10, /* wde_min_qt, wde_max_qt */ + &ple_qt30, &ple_qt31}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_pcie_8852c[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size19, &ple_size19, /* wde_size, ple_size */ + &wde_qt18, &wde_qt18, /* wde_min_qt, wde_max_qt */ + &ple_qt46, &ple_qt47}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size20, &ple_size20, /* wde_size, ple_size */ + &wde_qt19, &wde_qt19, /* wde_min_qt, wde_max_qt */ + &ple_qt48, &ple_qt49}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC_STF, /* qta_mode */ + &wde_size21, &ple_size21, /* wde_size, ple_size */ + &wde_qt20, &wde_qt20, /* wde_min_qt, wde_max_qt */ + &ple_qt50, &ple_qt51}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC_STF, /* qta_mode */ + &wde_size21, &ple_size21, /* wde_size, ple_size */ + &wde_qt21, &wde_qt21, /* wde_min_qt, wde_max_qt */ + &ple_qt52, &ple_qt53}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size18, &ple_size18, /* wde_size, ple_size */ + &wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */ + &ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size22, &ple_size22, /* wde_size, ple_size */ + &wde_qt22, &wde_qt22, /* wde_min_qt, wde_max_qt */ + &ple_qt54, &ple_qt55}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_pcie_8192xb[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size19, &ple_size19, /* wde_size, ple_size */ + &wde_qt18, &wde_qt18, /* wde_min_qt, wde_max_qt */ + &ple_qt46, &ple_qt47}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size20, &ple_size20, /* wde_size, ple_size */ + &wde_qt19, &wde_qt19, /* wde_min_qt, wde_max_qt */ + &ple_qt48, &ple_qt49}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC_STF, /* qta_mode */ + &wde_size21, &ple_size21, /* wde_size, ple_size */ + &wde_qt20, &wde_qt20, /* wde_min_qt, wde_max_qt */ + &ple_qt50, &ple_qt51}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC_STF, /* qta_mode */ + &wde_size21, &ple_size21, /* wde_size, ple_size */ + &wde_qt21, &wde_qt21, /* wde_min_qt, wde_max_qt */ + &ple_qt52, &ple_qt53}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size18, &ple_size18, /* wde_size, ple_size */ + &wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */ + &ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size22, &ple_size22, /* wde_size, ple_size */ + &wde_qt22, &wde_qt22, /* wde_min_qt, wde_max_qt */ + &ple_qt54, &ple_qt55}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; +#endif + +#if MAC_AX_USB_SUPPORT +static struct dle_mem_t dle_mem_usb_8852a[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size1, &ple_size1, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt25, &ple_qt26}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size1, &ple_size1, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt16, &ple_qt17}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size4, &ple_size4, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size15, &ple_size15, /* wde_size, ple_size */ + &wde_qt14, &wde_qt14, /* wde_min_qt, wde_max_qt */ + &ple_qt38, &ple_qt39}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb_8852a_ccv[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size26, &ple_size1, /* wde_size, ple_size */ + &wde_qt26, &wde_qt26, /* wde_min_qt, wde_max_qt */ + &ple_qt25, &ple_qt63}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size1, &ple_size1, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt16, &ple_qt17}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size4, &ple_size4, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size15, &ple_size15, /* wde_size, ple_size */ + &wde_qt14, &wde_qt14, /* wde_min_qt, wde_max_qt */ + &ple_qt38, &ple_qt39}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb2_8852b[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size25, &ple_size27, /* wde_size, ple_size */ + &wde_qt25, &wde_qt25, /* wde_min_qt, wde_max_qt */ + &ple_qt61, &ple_qt62}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size8, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size16, &ple_size16, /* wde_size, ple_size */ + &wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */ + &ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb3_8852b[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size8, &ple_size7, /* wde_size, ple_size */ + &wde_qt8, &wde_qt8, /* wde_min_qt, wde_max_qt */ + &ple_qt27, &ple_qt28}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size8, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size16, &ple_size16, /* wde_size, ple_size */ + &wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */ + &ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb_8852b_cabv[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size24, &ple_size26, /* wde_size, ple_size */ + &wde_qt24, &wde_qt24, /* wde_min_qt, wde_max_qt */ + &ple_qt59, &ple_qt60}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size25, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size16, &ple_size16, /* wde_size, ple_size */ + &wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */ + &ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb_8852c[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size17, &ple_size17, /* wde_size, ple_size */ + &wde_qt16, &wde_qt16, /* wde_min_qt, wde_max_qt */ + &ple_qt42, &ple_qt43}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size18, &ple_size18, /* wde_size, ple_size */ + &wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */ + &ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size16, &ple_size16, /* wde_size, ple_size */ + &wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */ + &ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_usb_8192xb[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size17, &ple_size17, /* wde_size, ple_size */ + &wde_qt16, &wde_qt16, /* wde_min_qt, wde_max_qt */ + &ple_qt42, &ple_qt43}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size18, &ple_size18, /* wde_size, ple_size */ + &wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */ + &ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size16, &ple_size16, /* wde_size, ple_size */ + &wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */ + &ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; +#endif + +#if MAC_AX_SDIO_SUPPORT +static struct dle_mem_t dle_mem_sdio_8852a[] = { + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size1, &ple_size1, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt2, &ple_qt3}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DBCC, /* qta_mode */ + &wde_size1, &ple_size1, /* wde_size, ple_size */ + &wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */ + &ple_qt6, &ple_qt7}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size4, &ple_size4, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size12, &ple_size12, /* wde_size, ple_size */ + &wde_qt11, &wde_qt11, /* wde_min_qt, wde_max_qt */ + &ple_qt32, &ple_qt33}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; + +static struct dle_mem_t dle_mem_sdio_8852b[] = { + {MAC_AX_QTA_DLFW, /* qta_mode */ + &wde_size9, &ple_size8, /* wde_size, ple_size */ + &wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */ + &ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_SCC, /* qta_mode */ + &wde_size13, &ple_size13, /* wde_size, ple_size */ + &wde_qt12, &wde_qt12, /* wde_min_qt, wde_max_qt */ + &ple_qt34, &ple_qt35}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_LAMODE, /* qta_mode */ + &wde_size14, &ple_size14, /* wde_size, ple_size */ + &wde_qt13, &wde_qt13, /* wde_min_qt, wde_max_qt */ + &ple_qt36, &ple_qt37}, /* ple_min_qt, ple_max_qt */ + {MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL}, +}; +#endif + +u32 dle_is_txq_empty(struct mac_ax_adapter *adapter, u8 *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, rval32; + + val32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | + B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | + B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | + B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | + B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | + B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | + B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | + B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | + B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | + B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | + B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | + B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | + B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; + + rval32 = MAC_REG_R32(R_AX_DLE_EMPTY0); + if (val32 != (rval32 & val32)) { + *val = DLE_QUEUE_NONEMPTY; + PLTFM_MSG_TRACE("[TRACE]TXQ non empty 0x%X\n", rval32); + } else { + *val = DLE_QUEUE_EMPTY; + PLTFM_MSG_TRACE("[TRACE]TXQ empty 0x%X\n", rval32); + } + + return MACSUCCESS; +} + +u32 dle_is_rxq_empty(struct mac_ax_adapter *adapter, u8 *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, rval32; + + val32 = B_AX_WDE_EMPTY_QUE_DMAC_WDRLS | B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX | + B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX | B_AX_PLE_EMPTY_QUE_DMAC_HDP | + B_AX_PLE_EMPTY_QUE_DMAC_PLRLS | B_AX_PLE_EMPTY_QUE_DMAC_CPUIO | + B_AX_PLE_EMPTY_QTA_DMAC_C2H | B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX | + B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX | + B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT | + B_AX_PLE_EMPTY_QTA_DMAC_WDRLS; + + rval32 = MAC_REG_R32(R_AX_DLE_EMPTY1); + if (val32 != (rval32 & val32)) { + *val = DLE_QUEUE_NONEMPTY; + PLTFM_MSG_TRACE("[TRACE] RXQ non empty 0x%X\n", rval32); + } else { + *val = DLE_QUEUE_EMPTY; + PLTFM_MSG_TRACE("[TRACE] RXQ empty 0x%X\n", rval32); + } + + return MACSUCCESS; +} + +u32 dle_dfi_ctrl(struct mac_ax_adapter *adapter, struct dle_dfi_ctrl_t *ctrl_p) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt, ctrl_reg, data_reg, ctrl_data; + + switch (ctrl_p->type) { + case DLE_CTRL_TYPE_WDE: + ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; + data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; + ctrl_data = SET_WORD(ctrl_p->target, + B_AX_WDE_DFI_TRGSEL) | + SET_WORD(ctrl_p->addr, B_AX_WDE_DFI_ADDR) | + B_AX_WDE_DFI_ACTIVE; + break; + case DLE_CTRL_TYPE_PLE: + ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; + data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; + ctrl_data = SET_WORD(ctrl_p->target, + B_AX_PLE_DFI_TRGSEL) | + SET_WORD(ctrl_p->addr, B_AX_PLE_DFI_ADDR) | + B_AX_PLE_DFI_ACTIVE; + break; + default: + PLTFM_MSG_ERR("[ERR] dfi ctrl type %d\n", ctrl_p->type); + return MACFUNCINPUT; + } + + MAC_REG_W32(ctrl_reg, ctrl_data); + + cnt = DLE_DFI_WAIT_CNT; + while (cnt && MAC_REG_R32(ctrl_reg) & B_AX_WDE_DFI_ACTIVE) { + PLTFM_DELAY_US(DLE_DFI_WAIT_US); + cnt--; + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", + ctrl_reg, ctrl_data); + return MACPOLLTO; + } + + ctrl_p->out_data = MAC_REG_R32(data_reg); + return MACSUCCESS; +} + +u32 dle_dfi_freepg(struct mac_ax_adapter *adapter, + struct dle_dfi_freepg_t *freepg) +{ + struct dle_dfi_ctrl_t ctrl; + u32 ret; + + ctrl.type = freepg->dle_type; + ctrl.target = DLE_DFI_TYPE_FREEPG; + ctrl.addr = DFI_TYPE_FREEPG_IDX; + ret = dle_dfi_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret); + return ret; + } + freepg->free_headpg = GET_FIELD(ctrl.out_data, B_AX_DLE_FREE_HEADPG); + freepg->free_tailpg = GET_FIELD(ctrl.out_data, B_AX_DLE_FREE_TAILPG); + + ctrl.addr = DFI_TYPE_FREEPG_PUBNUM; + ret = dle_dfi_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret); + return ret; + } + freepg->pub_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_PUB_PGNUM); + + return MACSUCCESS; +} + +u32 dle_dfi_quota(struct mac_ax_adapter *adapter, + struct dle_dfi_quota_t *quota) +{ + struct dle_dfi_ctrl_t ctrl; + u32 ret; + + ctrl.type = quota->dle_type; + ctrl.target = DLE_DFI_TYPE_QUOTA; + ctrl.addr = quota->qtaid; + ret = dle_dfi_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret); + return ret; + } + + quota->rsv_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_RSV_PGNUM); + quota->use_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_USE_PGNUM); + + return MACSUCCESS; +} + +u32 dle_dfi_qempty(struct mac_ax_adapter *adapter, + struct dle_dfi_qempty_t *qempty) +{ + struct dle_dfi_ctrl_t ctrl; + u32 ret; + + ctrl.type = qempty->dle_type; + ctrl.target = DLE_DFI_TYPE_QEMPTY; + ctrl.addr = qempty->grpsel; + ret = dle_dfi_ctrl(adapter, &ctrl); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret); + return ret; + } + + qempty->qempty = GET_FIELD(ctrl.out_data, B_AX_DLE_QEMPTY_GRP); + + return MACSUCCESS; +} + +u32 mac_is_txq_empty(struct mac_ax_adapter *adapter, + struct mac_ax_tx_queue_empty *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct dle_dfi_qempty_t qempty; + u32 val32, val32_emp0, ret; + u32 i, j, qnum; + + PLTFM_MEMSET(val, 0xFF, sizeof(struct mac_ax_tx_queue_empty)); + + qempty.dle_type = DLE_CTRL_TYPE_WDE; + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + qnum = WDE_QEMPTY_ACQ_NUM_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + qnum = WDE_QEMPTY_ACQ_NUM_8852B; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + qnum = WDE_QEMPTY_ACQ_NUM_8852C; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + qnum = WDE_QEMPTY_ACQ_NUM_8192XB; + } else { + PLTFM_MSG_ERR("[ERR]wde qempty acq num not define\n"); + return MACCHIPID; + } + for (i = 0; i < qnum; i++) { + qempty.grpsel = i; + ret = dle_dfi_qempty(adapter, &qempty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle dfi acq empty %d\n", ret); + return ret; + } + for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { + val32 = GET_FIEL2(qempty.qempty, + j * QEMP_ACQ_GRP_QSEL_SH, + QEMP_ACQ_GRP_QSEL_MASK); + if (val32 != QEMP_ACQ_GRP_QSEL_MASK) + val->macid_txq_empty[i] &= ~BIT(j); + } + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852A; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852B; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852C; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8192XB; + } else { + PLTFM_MSG_ERR("[ERR]wde qempty mgq sel not define\n"); + return MACCHIPID; + } + ret = dle_dfi_qempty(adapter, &qempty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dle dfi mgq empty %d\n", ret); + return ret; + } + if (!(qempty.qempty & B_CMAC0_MGQ_NORMAL)) + val->band0_mgnt_empty = 0; + + if (is_curr_dbcc(adapter) && !(qempty.qempty & B_CMAC1_MGQ_NORMAL)) + val->band1_mgnt_empty = 0; + + val32 = B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; + if (is_curr_dbcc(adapter)) + val32 |= B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; + if ((qempty.qempty & val32) != val32) + val->fw_txq_empty = 0; + + val32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | + B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | + B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; + val32_emp0 = MAC_REG_R32(R_AX_DLE_EMPTY0); + if (val32 != (val32_emp0 & val32)) + val->fw_txq_empty = 0; + + if (!(val32_emp0 & B_AX_PLE_EMPTY_QTA_DMAC_H2C)) + val->h2c_empty = 0; + + val32 = B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | + B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | + B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | + B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | + B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | + B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | + B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; + + if (val32 != (val32_emp0 & val32)) + val->others_empty = 0; + + return MACSUCCESS; +} + +u32 mac_is_rxq_empty(struct mac_ax_adapter *adapter, + struct mac_ax_rx_queue_empty *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, val32_emp1; + + PLTFM_MEMSET(val, 0xFF, sizeof(struct mac_ax_rx_queue_empty)); + + val32_emp1 = MAC_REG_R32(R_AX_DLE_EMPTY1); + if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX)) + val->band0_rxq_empty = 0; + + if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX)) + val->band1_rxq_empty = 0; + + if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_DMAC_C2H)) + val->c2h_empty = 0; + + val32 = B_AX_WDE_EMPTY_QUE_DMAC_WDRLS | B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX | + B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX | B_AX_PLE_EMPTY_QUE_DMAC_HDP | + B_AX_PLE_EMPTY_QUE_DMAC_PLRLS | B_AX_PLE_EMPTY_QUE_DMAC_CPUIO | + B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT | + B_AX_PLE_EMPTY_QTA_DMAC_WDRLS; + + if (val32 != (val32_emp1 & val32)) + val->others_empty = 0; + + return MACSUCCESS; +} + +u32 mac_chk_allq_empty(struct mac_ax_adapter *adapter, u8 *empty) +{ + u8 chk_cnt, txq_empty, rxq_empty; + u32 ret; + *empty = 1; + + for (chk_cnt = 0; chk_cnt < QUEUE_EMPTY_CHK_CNT; chk_cnt++) { + ret = dle_is_txq_empty(adapter, &txq_empty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] TXQ chk fail %d\n", ret); + return ret; + } + + ret = dle_is_rxq_empty(adapter, &rxq_empty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] TXQ chk fail %d\n", ret); + return ret; + } + + if (!(txq_empty & rxq_empty)) { + PLTFM_MSG_TRACE("[TRACE] CHK TXQ %d RXQ %d\n", + txq_empty, rxq_empty); + *empty = 0; + break; + } + } + + return MACSUCCESS; +} + +u32 dle_used_size(struct dle_size_t *wde, struct dle_size_t *ple) +{ + return (u32)(wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num)) + + (u32)(ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num)); +} + +u32 dle_rsvd_size(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode) +{ + if (mode != MAC_AX_QTA_LAMODE) + return 0; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + return DLE_LAMODE_SIZE_8852A; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + return DLE_LAMODE_SIZE_8852B; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + return DLE_LAMODE_SIZE_8852C; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + return DLE_LAMODE_SIZE_8192XB; + else + return 0; +} + +void dle_func_en(struct mac_ax_adapter *adapter, u8 en) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN); + if (en == MAC_AX_FUNC_EN) + val32 |= (B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); + else if (en == MAC_AX_FUNC_DIS) + val32 &= ~(B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); + else + return; + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); +} + +void dle_clk_en(struct mac_ax_adapter *adapter, u8 en) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN); + if (en == MAC_AX_FUNC_EN) + val32 |= (B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); + else if (en == MAC_AX_FUNC_DIS) + val32 &= ~(B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); + else + return; + MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); +} + +struct dle_mem_t *get_dle_mem_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_qta_mode mode) +{ + struct dle_mem_t *cfg; + enum mac_ax_intf intf = adapter->hw_info->intf; + + switch (intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + cfg = dle_mem_sdio_8852a; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + cfg = dle_mem_sdio_8852b; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + cfg = dle_mem_sdio_8852b; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + cfg = dle_mem_sdio_8852b; + else + cfg = NULL; + break; +#endif +#if MAC_AX_USB_SUPPORT + case MAC_AX_INTF_USB: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) && + (is_cv(adapter, CCV))) + cfg = dle_mem_usb_8852a_ccv; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + cfg = dle_mem_usb_8852a; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + (is_cv(adapter, CAV) || is_cv(adapter, CBV))) + cfg = dle_mem_usb_8852b_cabv; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + (get_usb_mode(adapter) == MAC_AX_USB2)) + cfg = dle_mem_usb2_8852b; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + cfg = dle_mem_usb3_8852b; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + cfg = dle_mem_usb_8852a; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + cfg = dle_mem_usb_8192xb; + else + cfg = NULL; + break; +#endif +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_INTF_PCIE: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + cfg = dle_mem_pcie_8852a; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + (is_cv(adapter, CAV) || is_cv(adapter, CBV))) + cfg = dle_mem_pcie_8852b_cabv; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + cfg = dle_mem_pcie_8852b; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + cfg = dle_mem_pcie_8852c; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + cfg = dle_mem_pcie_8192xb; + else + cfg = NULL; + break; +#endif + default: + cfg = NULL; + break; + } + + if (!cfg) + return NULL; + for (; cfg->mode != MAC_AX_QTA_INVALID; cfg++) { + if (cfg->mode == mode) { + adapter->dle_info.wde_pg_size = cfg->wde_size->pge_size; + adapter->dle_info.ple_pg_size = cfg->ple_size->pge_size; + adapter->dle_info.qta_mode = mode; + adapter->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; + adapter->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; + adapter->dle_info.c0_tx_min = cfg->ple_min_qt->cma0_tx; + adapter->dle_info.c1_tx_min = cfg->ple_min_qt->cma1_tx; + return cfg; + } + } + + return NULL; +} + +u32 dle_mix_cfg(struct mac_ax_adapter *adapter, struct dle_mem_t *cfg) +{ + u8 bound; + u32 val32; + struct dle_size_t *size_cfg; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_WDE_PKTBUF_CFG); + bound = 0; + size_cfg = cfg->wde_size; + + switch (size_cfg->pge_size) { + default: + case MAC_AX_WDE_PG_64: + val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_64, + B_AX_WDE_PAGE_SEL); + break; + case MAC_AX_WDE_PG_128: + val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_128, + B_AX_WDE_PAGE_SEL); + break; + case MAC_AX_WDE_PG_256: + PLTFM_MSG_ERR("[ERR]WDE DLE doesn't support 256 byte!\n"); + return MACHWNOSUP; + } + + val32 = SET_CLR_WORD(val32, bound, B_AX_WDE_START_BOUND); + val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, + B_AX_WDE_FREE_PAGE_NUM); + MAC_REG_W32(R_AX_WDE_PKTBUF_CFG, val32); + + val32 = MAC_REG_R32(R_AX_PLE_PKTBUF_CFG); + bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) + * size_cfg->pge_size / DLE_BOUND_UNIT; + size_cfg = cfg->ple_size; + + switch (size_cfg->pge_size) { + default: + case MAC_AX_PLE_PG_64: + PLTFM_MSG_ERR("[ERR]PLE DLE doesn't support 64 byte!\n"); + return MACHWNOSUP; + case MAC_AX_PLE_PG_128: + val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_128, + B_AX_PLE_PAGE_SEL); + break; + case MAC_AX_PLE_PG_256: + val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_256, + B_AX_PLE_PAGE_SEL); + break; + } + + val32 = SET_CLR_WORD(val32, bound, B_AX_PLE_START_BOUND); + val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, + B_AX_PLE_FREE_PAGE_NUM); + MAC_REG_W32(R_AX_PLE_PKTBUF_CFG, val32); + + return MACSUCCESS; +} + +void wde_quota_cfg(struct mac_ax_adapter *adapter, + struct wde_quota_t *min_cfg, + struct wde_quota_t *max_cfg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = SET_WORD(min_cfg->hif, B_AX_WDE_Q0_MIN_SIZE) | + SET_WORD(max_cfg->hif, B_AX_WDE_Q0_MAX_SIZE); + MAC_REG_W32(R_AX_WDE_QTA0_CFG, val32); + + val32 = SET_WORD(min_cfg->wcpu, B_AX_WDE_Q1_MIN_SIZE) | + SET_WORD(max_cfg->wcpu, B_AX_WDE_Q1_MAX_SIZE); + MAC_REG_W32(R_AX_WDE_QTA1_CFG, val32); + + val32 = SET_WORD(min_cfg->pkt_in, B_AX_WDE_Q3_MIN_SIZE) | + SET_WORD(max_cfg->pkt_in, B_AX_WDE_Q3_MAX_SIZE); + MAC_REG_W32(R_AX_WDE_QTA3_CFG, val32); + + val32 = SET_WORD(min_cfg->cpu_io, B_AX_WDE_Q4_MIN_SIZE) | + SET_WORD(max_cfg->cpu_io, B_AX_WDE_Q4_MAX_SIZE); + MAC_REG_W32(R_AX_WDE_QTA4_CFG, val32); +} + +void ple_quota_cfg(struct mac_ax_adapter *adapter, + struct ple_quota_t *min_cfg, + struct ple_quota_t *max_cfg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = SET_WORD(min_cfg->cma0_tx, B_AX_PLE_Q0_MIN_SIZE) | + SET_WORD(max_cfg->cma0_tx, B_AX_PLE_Q0_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA0_CFG, val32); + + val32 = SET_WORD(min_cfg->cma1_tx, B_AX_PLE_Q1_MIN_SIZE) | + SET_WORD(max_cfg->cma1_tx, B_AX_PLE_Q1_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA1_CFG, val32); + + val32 = SET_WORD(min_cfg->c2h, B_AX_PLE_Q2_MIN_SIZE) | + SET_WORD(max_cfg->c2h, B_AX_PLE_Q2_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA2_CFG, val32); + + val32 = SET_WORD(min_cfg->h2c, B_AX_PLE_Q3_MIN_SIZE) | + SET_WORD(max_cfg->h2c, B_AX_PLE_Q3_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA3_CFG, val32); + + val32 = SET_WORD(min_cfg->wcpu, B_AX_PLE_Q4_MIN_SIZE) | + SET_WORD(max_cfg->wcpu, B_AX_PLE_Q4_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA4_CFG, val32); + + val32 = SET_WORD(min_cfg->mpdu_proc, B_AX_PLE_Q5_MIN_SIZE) | + SET_WORD(max_cfg->mpdu_proc, B_AX_PLE_Q5_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA5_CFG, val32); + + val32 = SET_WORD(min_cfg->cma0_dma, B_AX_PLE_Q6_MIN_SIZE) | + SET_WORD(max_cfg->cma0_dma, B_AX_PLE_Q6_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA6_CFG, val32); + + val32 = SET_WORD(min_cfg->cma1_dma, B_AX_PLE_Q7_MIN_SIZE) | + SET_WORD(max_cfg->cma1_dma, B_AX_PLE_Q7_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA7_CFG, val32); + + val32 = SET_WORD(min_cfg->bb_rpt, B_AX_PLE_Q8_MIN_SIZE) | + SET_WORD(max_cfg->bb_rpt, B_AX_PLE_Q8_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA8_CFG, val32); + + val32 = SET_WORD(min_cfg->wd_rel, B_AX_PLE_Q9_MIN_SIZE) | + SET_WORD(max_cfg->wd_rel, B_AX_PLE_Q9_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA9_CFG, val32); + + val32 = SET_WORD(min_cfg->cpu_io, B_AX_PLE_Q10_MIN_SIZE) | + SET_WORD(max_cfg->cpu_io, B_AX_PLE_Q10_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA10_CFG, val32); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = SET_WORD(min_cfg->tx_rpt, B_AX_PLE_Q11_MIN_SIZE) | + SET_WORD(max_cfg->tx_rpt, B_AX_PLE_Q11_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA11_CFG, val32); + } +} + +void dle_quota_cfg(struct mac_ax_adapter *adapter, struct dle_mem_t *cfg) +{ + wde_quota_cfg(adapter, cfg->wde_min_qt, cfg->wde_max_qt); + ple_quota_cfg(adapter, cfg->ple_min_qt, cfg->ple_max_qt); +} + +u32 dle_quota_change(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode) +{ + u32 ret = MACSUCCESS; + struct dle_mem_t *cfg; + struct cpuio_buf_req_t buf_req; + struct cpuio_ctrl_t ctrl_para; + u32 val32_1, val32_2; + + cfg = get_dle_mem_cfg(adapter, mode); + if (!cfg) { + PLTFM_MSG_ERR("[ERR]wd/dle mem cfg\n"); + return MACNOITEM; + } + + val32_1 = dle_used_size(cfg->wde_size, cfg->ple_size); + val32_2 = adapter->hw_info->fifo_size - dle_rsvd_size(adapter, mode); + if (val32_1 != val32_2) { + PLTFM_MSG_ERR("[ERR]dle used size %d not match %d\n", + val32_1, val32_2); + return MACFFCFG; + } + + dle_quota_cfg(adapter, cfg); + + //Trigger change by enqueue packet + // Use CPUIO temporarily. + //WD + buf_req.len = 0x20; // chris comment + ret = mac_dle_buf_req_wd(adapter, &buf_req); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]WDE DLE buf req %d\n", ret); + return ret; + } + + PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para)); + ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; + ctrl_para.start_pktid = buf_req.pktid; + ctrl_para.end_pktid = buf_req.pktid; + ctrl_para.pkt_num = 0; + ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; + ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; + ret = mac_set_cpuio_wd(adapter, &ctrl_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]WDE DLE enqueue to head %d\n", ret); + return ret; + } + + //PL + buf_req.len = 0x20; + ret = mac_dle_buf_req_pl(adapter, &buf_req); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]PLE DLE buf req %d\n", ret); + return ret; + } + + PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para)); + ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; + ctrl_para.start_pktid = buf_req.pktid; + ctrl_para.end_pktid = buf_req.pktid; + ctrl_para.pkt_num = 0; + ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; + ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; + ret = mac_set_cpuio_pl(adapter, &ctrl_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]PLE DLE enqueue to head %d\n", ret); + return ret; + } + return ret; +} + +u32 dle_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + enum mac_ax_qta_mode ext_mode) +{ + u32 ret = MACSUCCESS; + u32 cnt, val32_1, val32_2; + struct dle_mem_t *cfg, *ext_cfg; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct dle_mem_t cfg_tmp; + struct dle_size_t wde_size_tmp, ple_size_tmp; + struct wde_quota_t wde_min_qt_tmp, wde_max_qt_tmp; + struct ple_quota_t ple_min_qt_tmp, ple_max_qt_tmp; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]chk dmac en %d\n", ret); + return ret; + } + + cfg = get_dle_mem_cfg(adapter, mode); + if (!cfg) { + ret = MACNOITEM; + PLTFM_MSG_ERR("[ERR]get_dle_mem_cfg %d\n", mode); + goto error; + } + + PLTFM_MEMCPY(&wde_size_tmp, cfg->wde_size, sizeof(struct dle_size_t)); + PLTFM_MEMCPY(&ple_size_tmp, cfg->ple_size, sizeof(struct dle_size_t)); + PLTFM_MEMCPY(&wde_min_qt_tmp, cfg->wde_min_qt, sizeof(struct wde_quota_t)); + PLTFM_MEMCPY(&wde_max_qt_tmp, cfg->wde_max_qt, sizeof(struct wde_quota_t)); + PLTFM_MEMCPY(&ple_min_qt_tmp, cfg->ple_min_qt, sizeof(struct ple_quota_t)); + PLTFM_MEMCPY(&ple_max_qt_tmp, cfg->ple_max_qt, sizeof(struct ple_quota_t)); + cfg_tmp.mode = cfg->mode; + cfg_tmp.wde_size = &wde_size_tmp; + cfg_tmp.ple_size = &ple_size_tmp; + cfg_tmp.wde_min_qt = &wde_min_qt_tmp; + cfg_tmp.wde_max_qt = &wde_max_qt_tmp; + cfg_tmp.ple_min_qt = &ple_min_qt_tmp; + cfg_tmp.ple_max_qt = &ple_max_qt_tmp; + cfg = &cfg_tmp; + + if (mode == MAC_AX_QTA_DLFW) { + ext_cfg = get_dle_mem_cfg(adapter, ext_mode); + if (!ext_cfg) { + ret = MACNOITEM; + PLTFM_MSG_ERR("[ERR]get_dle_ext_mem_cfg %d\n", + ext_mode); + goto error; + } + + cfg->wde_min_qt->wcpu = ext_cfg->wde_min_qt->wcpu; + } + + val32_1 = dle_used_size(cfg->wde_size, cfg->ple_size); + val32_2 = adapter->hw_info->fifo_size - dle_rsvd_size(adapter, mode); + if (val32_1 != val32_2) { + PLTFM_MSG_ERR("[ERR]dle init used size %d not match %d\n", + val32_1, val32_2); + ret = MACFFCFG; + goto error; + } + + dle_func_en(adapter, MAC_AX_FUNC_DIS); + dle_clk_en(adapter, MAC_AX_FUNC_EN); + + ret = dle_mix_cfg(adapter, cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dle mix cfg %d\n", ret); + goto error; + } + dle_quota_cfg(adapter, cfg); + + dle_func_en(adapter, MAC_AX_FUNC_EN); + + cnt = DLE_WAIT_CNT; + while (cnt--) { + if ((MAC_REG_R32(R_AX_WDE_INI_STATUS) & WDE_MGN_INI_RDY) + == WDE_MGN_INI_RDY) + break; + PLTFM_DELAY_US(DLE_WAIT_US); + } + + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]WDE cfg ready timeout\n"); + return MACPOLLTO; + } + + cnt = DLE_WAIT_CNT; + while (cnt--) { + if ((MAC_REG_R32(R_AX_PLE_INI_STATUS) & PLE_MGN_INI_RDY) + == PLE_MGN_INI_RDY) + break; + PLTFM_DELAY_US(DLE_WAIT_US); + } + + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]PLE cfg ready timeout\n"); + return MACPOLLTO; + } + + return ret; +error: + dle_func_en(adapter, MAC_AX_FUNC_DIS); + PLTFM_MSG_ERR("[ERR]trxcfg wde 0x8900 = %x\n", + MAC_REG_R32(R_AX_WDE_INI_STATUS)); + PLTFM_MSG_ERR("[ERR]trxcfg ple 0x8D00 = %x\n", + MAC_REG_R32(R_AX_PLE_INI_STATUS)); + + return ret; +} + +u32 is_qta_dbcc(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + u8 *is_dbcc) +{ + struct dle_mem_t *cfg; + + cfg = get_dle_mem_cfg(adapter, mode); + if (!cfg) { + PLTFM_MSG_ERR("[ERR]get_dle_mem_cfg\n"); + return MACNOITEM; + } + + *is_dbcc = (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma) ? + 1 : 0; + + return MACSUCCESS; +} + +u8 is_curr_dbcc(struct mac_ax_adapter *adapter) +{ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + return 0; + + return adapter->dle_info.c1_rx_qta ? 1 : 0; +} + +u32 is_qta_poh(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + u8 *is_poh) +{ + *is_poh = (mode == MAC_AX_QTA_SCC_STF || mode == MAC_AX_QTA_DBCC_STF) ? + 0 : 1; + + return MACSUCCESS; +} + +u32 _patch_redu_rx_qta(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u16 new_qta, qta_min, qta_max, rdu_pg_num; + + if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))) + return MACSUCCESS; + + val32 = GET_FIELD(MAC_REG_R32(R_AX_PLE_PKTBUF_CFG), B_AX_PLE_PAGE_SEL); + if (val32 == S_AX_PLE_PAGE_SEL_128) { + rdu_pg_num = PLE_QTA_PG128B_12KB; + } else if (val32 == S_AX_PLE_PAGE_SEL_256) { + rdu_pg_num = PLE_QTA_PG128B_12KB / 2; + } else { + PLTFM_MSG_ERR("[ERR]PLE page sel %d unsupport\n", val32); + return MACHWERR; + } + + val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG); + if (!val32) { + PLTFM_MSG_ERR("[ERR]no rx 0 qta\n"); + return MACHWERR; + } + qta_min = GET_FIELD(val32, B_AX_PLE_Q6_MIN_SIZE); + qta_max = GET_FIELD(val32, B_AX_PLE_Q6_MAX_SIZE); + + adapter->dle_info.c0_ori_max = qta_max; + + new_qta = (qta_max - qta_min) < rdu_pg_num ? + qta_min : (qta_max - rdu_pg_num); + val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q6_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA6_CFG, val32); + + val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG); + if (!val32) + return MACSUCCESS; + qta_min = GET_FIELD(val32, B_AX_PLE_Q7_MIN_SIZE); + qta_max = GET_FIELD(val32, B_AX_PLE_Q7_MAX_SIZE); + + adapter->dle_info.c1_ori_max = qta_max; + + new_qta = (qta_max - qta_min) < rdu_pg_num ? + qta_min : (qta_max - rdu_pg_num); + val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q7_MAX_SIZE); + MAC_REG_W32(R_AX_PLE_QTA7_CFG, val32); + + return MACSUCCESS; +} + +u32 _patch_restr_rx_qta(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, w_val32; + + if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))) + return MACSUCCESS; + + val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG); + if (!val32) { + PLTFM_MSG_ERR("[ERR]no rx 0 qta\n"); + return MACHWERR; + } + w_val32 = SET_CLR_WORD(val32, adapter->dle_info.c0_ori_max, + B_AX_PLE_Q6_MAX_SIZE); + if (w_val32 != val32) + MAC_REG_W32(R_AX_PLE_QTA6_CFG, w_val32); + + val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG); + if (!val32) + return MACSUCCESS; + w_val32 = SET_CLR_WORD(val32, adapter->dle_info.c1_ori_max, + B_AX_PLE_Q7_MAX_SIZE); + if (w_val32 != val32) + MAC_REG_W32(R_AX_PLE_QTA7_CFG, w_val32); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/dle.h b/phl/hal_g6/mac/mac_ax/dle.h new file mode 100644 index 0000000..92cba65 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/dle.h @@ -0,0 +1,704 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_DLE_H_ +#define _MAC_AX_DLE_H_ + +#include "../type.h" +#include "../mac_ax.h" +#include "cpuio.h" + +/*--------------------Define ----------------------------------------*/ +#define DLE_DFI_WAIT_CNT 1000 +#define DLE_DFI_WAIT_US 1 + +#define DLE_WAIT_CNT 2000 +#define DLE_WAIT_US 1 + +// DLE_DFI_TYPE_FREEPG +#define B_AX_DLE_FREE_TAILPG_SH 16 +#define B_AX_DLE_FREE_TAILPG_MSK 0xfff +#define B_AX_DLE_FREE_HEADPG_SH 0 +#define B_AX_DLE_FREE_HEADPG_MSK 0xfff + +#define B_AX_DLE_PUB_PGNUM_SH 0 +#define B_AX_DLE_PUB_PGNUM_MSK 0x1fff + +// DLE_DFI_TYPE_QUOTA +#define B_AX_DLE_USE_PGNUM_SH 16 +#define B_AX_DLE_USE_PGNUM_MSK 0xfff +#define B_AX_DLE_RSV_PGNUM_SH 0 +#define B_AX_DLE_RSV_PGNUM_MSK 0xfff + +// DLE_DFI_TYPE_QEMPTY +#define B_AX_DLE_QEMPTY_GRP_SH 0 +#define B_AX_DLE_QEMPTY_GRP_MSK 0xffffffff + +#define QUEUE_EMPTY_CHK_CNT 2 +#define WDE_QEMPTY_NUM_8852A 18 +#define WDE_QEMPTY_NUM_8852B 5 +#define WDE_QEMPTY_NUM_8852C 19 +#define WDE_QEMPTY_NUM_8192XB 18 +#define PLE_QEMPTY_NUM 2 +#define WDE_QEMPTY_ACQ_NUM_8852A 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */ +#define WDE_QEMPTY_ACQ_NUM_8852B 4 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */ +#define WDE_QEMPTY_ACQ_NUM_8852C 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */ +#define WDE_QEMPTY_ACQ_NUM_8192XB 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */ +#define WDE_QEMPTY_MGQ_SEL_8852A 16 +#define WDE_QEMPTY_MGQ_SEL_8852B 4 +#define WDE_QEMPTY_MGQ_SEL_8852C 16 +#define WDE_QEMPTY_MGQ_SEL_8192XB 16 +#define QEMP_ACQ_GRP_MACID_NUM 8 +#define QEMP_ACQ_GRP_QSEL_SH 4 +#define QEMP_ACQ_GRP_QSEL_MASK 0xF +#define S_AX_WDE_PAGE_SEL_64 0 +#define S_AX_WDE_PAGE_SEL_128 1 +/* #define S_AX_WDE_PAGE_SEL_256 2 // HDP not support */ + +/* #define S_AX_PLE_PAGE_SEL_64 0 // HDP not support */ +#define S_AX_PLE_PAGE_SEL_128 1 +#define S_AX_PLE_PAGE_SEL_256 2 + +#define DLE_BOUND_UNIT (8 * 1024) + +#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) +#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) +#define DLE_QUEUE_NONEMPTY 0 +#define DLE_QUEUE_EMPTY 1 + +#define B_CMAC0_MGQ_NORMAL BIT2 +#define B_CMAC0_MGQ_NO_PWRSAV BIT3 +#define B_CMAC0_CPUMGQ BIT4 +#define B_CMAC1_MGQ_NORMAL BIT10 +#define B_CMAC1_MGQ_NO_PWRSAV BIT11 +#define B_CMAC1_CPUMGQ BIT12 + +#define DLE_LAMODE_SIZE_8852A (256 * 1024) +#define DLE_LAMODE_SIZE_8852B (64 * 1024) +#define DLE_LAMODE_SIZE_8852C (192 * 1024) +#define DLE_LAMODE_SIZE_8192XB (192 * 1024) + +#define WDE_QTA_NUM 5 +#define PLE_QTA_NUM_8852AB 11 +#define PLE_QTA_NUM_8852C 12 +#define PLE_QTA_NUM_8192XB 12 + +#define PLE_QTA_PG128B_12KB 96 + +/*--------------------Define Enum------------------------------------*/ + +/** + * @enum WDE_QTAID + * + * @brief WDE_QTAID + * + * @var WDE_QTAID::WDE_QTAID_HOST_IF + * Please Place Description here. + * @var WDE_QTAID::WDE_QTAID_WLAN_CPU + * Please Place Description here. + * @var WDE_QTAID::WDE_QTAID_DATA_CPU + * Please Place Description here. + * @var WDE_QTAID::WDE_QTAID_PKTIN + * Please Place Description here. + * @var WDE_QTAID::WDE_QTAID_CPUIO + * Please Place Description here. + */ +enum WDE_QTAID { + WDE_QTAID_HOST_IF = 0, + WDE_QTAID_WLAN_CPU = 1, + WDE_QTAID_DATA_CPU = 2, + WDE_QTAID_PKTIN = 3, + WDE_QTAID_CPUIO = 4 +}; + +/** + * @enum PLE_QTAID + * + * @brief PLE_QTAID + * + * @var PLE_QTAID::PLE_QTAID_B0_TXPL + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_B1_TXPL + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_C2H + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_H2C + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_WLAN_CPU + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_MPDU + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_CMAC0_RX + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_CMAC1_RX + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_CMAC1_BBRPT + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_WDRLS + * Please Place Description here. + * @var PLE_QTAID::PLE_QTAID_CPUIO + * Please Place Description here. + */ +enum PLE_QTAID { + PLE_QTAID_B0_TXPL = 0, + PLE_QTAID_B1_TXPL = 1, + PLE_QTAID_C2H = 2, + PLE_QTAID_H2C = 3, + PLE_QTAID_WLAN_CPU = 4, + PLE_QTAID_MPDU = 5, + PLE_QTAID_CMAC0_RX = 6, + PLE_QTAID_CMAC1_RX = 7, + PLE_QTAID_BBRPT = 8, + PLE_QTAID_WDRLS = 9, + PLE_QTAID_CPUIO = 10, + PLE_QTAID_TXRPT = 11 +}; + +/** + * @enum DLE_CTRL_TYPE + * + * @brief DLE_CTRL_TYPE + * + * @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_WDE + * Please Place Description here. + * @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_PLE + * Please Place Description here. + * @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_NUM + * Please Place Description here. + */ +enum DLE_CTRL_TYPE { + DLE_CTRL_TYPE_WDE = 0, + DLE_CTRL_TYPE_PLE = 1, + DLE_CTRL_TYPE_NUM = 2 +}; + +/** + * @enum DLE_DFI_TYPE + * + * @brief DLE_DFI_TYPE + * + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_FREEPG + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_QUOTA + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_PAGELLT + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_PKTINFO + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_PREPKTLLT + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_NXTPKTLLT + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_QLNKTBL + * Please Place Description here. + * @var DLE_DFI_TYPE::DLE_DFI_TYPE_QEMPTY + * Please Place Description here. + */ +enum DLE_DFI_TYPE { + DLE_DFI_TYPE_FREEPG = 0, + DLE_DFI_TYPE_QUOTA = 1, + DLE_DFI_TYPE_PAGELLT = 2, + DLE_DFI_TYPE_PKTINFO = 3, + DLE_DFI_TYPE_PREPKTLLT = 4, + DLE_DFI_TYPE_NXTPKTLLT = 5, + DLE_DFI_TYPE_QLNKTBL = 6, + DLE_DFI_TYPE_QEMPTY = 7 +}; + +enum DFI_TYPE_FREEPG_SEL { + DFI_TYPE_FREEPG_IDX = 0, + DFI_TYPE_FREEPG_PUBNUM +}; + +/*--------------------Define MACRO----------------------------------*/ + +/*--------------------Define Struct-----------------------------------*/ + +/** + * @struct dle_dfi_ctrl_t + * @brief dle_dfi_ctrl_t + * + * @var dle_dfi_ctrl_t::ctrl_type + * Please Place Description here. + * @var dle_dfi_ctrl_t::dfi_ctrl + * Please Place Description here. + * @var dle_dfi_ctrl_t::dfi_data + * Please Place Description here. + */ +struct dle_dfi_ctrl_t { + enum DLE_CTRL_TYPE type; + u32 target; + u32 addr; + u32 out_data; +}; + +/** + * @struct dle_dfi_freepg_t + * @brief dle_dfi_freepg_t + * + * @var dle_dfi_freepg_t::dle_type + * Please Place Description here. + * @var dle_dfi_freepg_t::free_headpg + * Please Place Description here. + * @var dle_dfi_freepg_t::free_tailpg + * Please Place Description here. + * @var dle_dfi_freepg_t::pub_pgnum + * Please Place Description here. + */ +struct dle_dfi_freepg_t { + // input parameter + enum DLE_CTRL_TYPE dle_type; + // output parameter + u16 free_headpg; + u16 free_tailpg; + u16 pub_pgnum; +}; + +/** + * @struct dle_dfi_quota_t + * @brief dle_dfi_quota_t + * + * @var dle_dfi_quota_t::dle_type + * Please Place Description here. + * @var dle_dfi_quota_t::qtaid + * Please Place Description here. + * @var dle_dfi_quota_t::rsv_pgnum + * Please Place Description here. + * @var dle_dfi_quota_t::use_pgnum + * Please Place Description here. + */ +struct dle_dfi_quota_t { + // input parameter + enum DLE_CTRL_TYPE dle_type; + u32 qtaid; + // output parameter + u16 rsv_pgnum; + u16 use_pgnum; +}; + +/** + * @struct dle_dfi_qempty_t + * @brief dle_dfi_qempty_t + * + * @var dle_dfi_qempty_t::dle_type + * Please Place Description here. + * @var dle_dfi_qempty_t::grpsel + * Please Place Description here. + * @var dle_dfi_qempty_t::qempty + * Please Place Description here. + */ +struct dle_dfi_qempty_t { + // input parameter + enum DLE_CTRL_TYPE dle_type; + u32 grpsel; + // output parameter + u32 qempty; +}; + +/** + * @struct dle_size_t + * @brief dle_size_t + * + * @var dle_size_t::pge_size + * Please Place Description here. + * @var dle_size_t::lnk_pge_num + * Please Place Description here. + * @var dle_size_t::unlnk_pge_num + * Please Place Description here. + */ +struct dle_size_t { + u16 pge_size; + u16 lnk_pge_num; + u16 unlnk_pge_num; +}; + +/** + * @struct wde_quota_t + * @brief wde_quota_t + * + * @var wde_quota_t::hif + * Please Place Description here. + * @var wde_quota_t::wcpu + * Please Place Description here. + * @var wde_quota_t::pkt_in + * Please Place Description here. + * @var wde_quota_t::cpu_io + * Please Place Description here. + */ +struct wde_quota_t { + u16 hif; + u16 wcpu; + u16 pkt_in; + u16 cpu_io; +}; + +/** + * @struct ple_quota_t + * @brief ple_quota_t + * + * @var ple_quota_t::cma0_tx + * Please Place Description here. + * @var ple_quota_t::cma1_tx + * Please Place Description here. + * @var ple_quota_t::c2h + * Please Place Description here. + * @var ple_quota_t::h2c + * Please Place Description here. + * @var ple_quota_t::wcpu + * Please Place Description here. + * @var ple_quota_t::mpdu_proc + * Please Place Description here. + * @var ple_quota_t::cma0_dma + * Please Place Description here. + * @var ple_quota_t::cma1_dma + * Please Place Description here. + * @var ple_quota_t::bb_rpt + * Please Place Description here. + * @var ple_quota_t::wd_rel + * Please Place Description here. + * @var ple_quota_t::cpu_io + * Please Place Description here. + * @var ple_quota_t::tx_rpt + * Please Place Description here. + */ +struct ple_quota_t { + u16 cma0_tx; + u16 cma1_tx; + u16 c2h; + u16 h2c; + u16 wcpu; + u16 mpdu_proc; + u16 cma0_dma; + u16 cma1_dma; + u16 bb_rpt; + u16 wd_rel; + u16 cpu_io; + u16 tx_rpt; +}; + +/** + * @struct dle_mem_t + * @brief dle_mem_t + * + * @var dle_mem_t::mode + * Please Place Description here. + * @var dle_mem_t::wde_size + * Please Place Description here. + * @var dle_mem_t::ple_size + * Please Place Description here. + * @var dle_mem_t::wde_min_qt + * Please Place Description here. + * @var dle_mem_t::wde_max_qt + * Please Place Description here. + * @var dle_mem_t::ple_min_qt + * Please Place Description here. + * @var dle_mem_t::ple_max_qt + * Please Place Description here. + */ +struct dle_mem_t { + enum mac_ax_qta_mode mode; + struct dle_size_t *wde_size; + struct dle_size_t *ple_size; + struct wde_quota_t *wde_min_qt; + struct wde_quota_t *wde_max_qt; + struct ple_quota_t *ple_min_qt; + struct ple_quota_t *ple_max_qt; +}; + +/*--------------------Export global variable----------------------------*/ + +/*--------------------Function declaration-----------------------------*/ +u32 dle_dfi_ctrl(struct mac_ax_adapter *adapter, struct dle_dfi_ctrl_t *ctrl_p); + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ +/** + * @brief dle_dfi_freepg + * + * @param *adapter + * @param *freepg + * @return Please Place Description here. + * @retval u32 + */ +u32 dle_dfi_freepg(struct mac_ax_adapter *adapter, + struct dle_dfi_freepg_t *freepg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_dfi_quota + * + * @param *adapter + * @param *quota + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_dfi_quota(struct mac_ax_adapter *adapter, + struct dle_dfi_quota_t *quota); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_dfi_qempty + * + * @param *adapter + * @param *qempty + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_dfi_qempty(struct mac_ax_adapter *adapter, + struct dle_dfi_qempty_t *qempty); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief mac_chk_allq_empty + * + * @param *adapter + * @param *empty + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_chk_allq_empty(struct mac_ax_adapter *adapter, u8 *empty); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_quota_change + * + * @param *adapter + * @param mode + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_quota_change(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_init + * + * @param *adapter + * @param mode + * @param ext_mode + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + enum mac_ax_qta_mode ext_mode); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_is_txq_empty + * + * @param *adapter + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_is_txq_empty(struct mac_ax_adapter *adapter, u8 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief dle_is_rxq_empty + * + * @param *adapter + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 dle_is_rxq_empty(struct mac_ax_adapter *adapter, u8 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief mac_is_txq_empty + * + * @param *adapter + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_is_txq_empty(struct mac_ax_adapter *adapter, + struct mac_ax_tx_queue_empty *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief mac_is_rxq_empty + * + * @param *adapter + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_is_rxq_empty(struct mac_ax_adapter *adapter, + struct mac_ax_rx_queue_empty *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief is_qta_dbcc + * + * @param *adapter + * @param mode + * @param *is_dbcc + * @return Please Place Description here. + * @retval u32 + */ + +u32 is_qta_dbcc(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + u8 *is_dbcc); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup DLE + * @{ + */ + +/** + * @brief is_qta_poh + * + * @param *adapter + * @param mode + * @param *is_poh + * @return Please Place Description here. + * @retval u32 + */ + +u8 is_curr_dbcc(struct mac_ax_adapter *adapter); + +u32 is_qta_poh(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, + u8 *is_poh); +/** + * @} + * @} + */ + +u32 _patch_redu_rx_qta(struct mac_ax_adapter *adapter); +u32 _patch_restr_rx_qta(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/efuse.c b/phl/hal_g6/mac/mac_ax/efuse.c new file mode 100644 index 0000000..cd22fd2 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/efuse.c @@ -0,0 +1,3962 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "efuse.h" + +static struct mac_efuse_tbl efuse_tbl; +static struct mac_bank_efuse_info bank_efuse_info; +u16 efuse_ctrl = R_AX_EFUSE_CTRL; +u16 read_efuse_cnt = EFUSE_WAIT_CNT; +bool OTP_test; +enum rtw_dv_sel dv_sel = DDV; + +static struct efuse_info_item offset_pcie = { + 0x400, /* mac_addr */ + 0, /* pid */ + 0x408, /* did */ + 0x406, /* vid */ + 0x40A, /* svid */ + 0x40C, /* smid */ +}; + +static struct efuse_info_item offset_usb_8852a = { + 0x438, /* mac_addr */ + 0x432, /* pid */ + 0, /* did */ + 0x430, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item offset_usb_8852b = { + 0x488, /* mac_addr */ + 0x482, /* pid */ + 0, /* did */ + 0x480, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item offset_sdio = { + 0x41A, /* mac_addr */ + 0, /* pid */ + 0, /* did */ + 0, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item def_val_pcie = { + 0x0, /* mac_addr */ + 0, /* pid */ + 0x52, /* did */ + 0xEC, /* vid */ + 0xEC, /* svid */ + 0x52, /* smid */ +}; + +static struct efuse_info_item def_val_usb_8852a = { + 0x0, /* mac_addr */ + 0x5A, /* pid */ + 0, /* did */ + 0xDA, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item def_val_usb_8852b = { + 0x0, /* mac_addr */ + 0x5B, /* pid */ + 0, /* did */ + 0xDA, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item def_val_sdio = { + 0x0, /* mac_addr */ + 0, /* pid */ + 0, /* did */ + 0, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item len_pcie = { + 6, /* mac_addr */ + 0, /* pid */ + 2, /* did */ + 2, /* vid */ + 2, /* svid */ + 2, /* smid */ +}; + +static struct efuse_info_item len_usb = { + 6, /* mac_addr */ + 2, /* pid */ + 0, /* did */ + 2, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info_item len_sdio = { + 6, /* mac_addr */ + 0, /* pid */ + 0, /* did */ + 0, /* vid */ + 0, /* svid */ + 0, /* smid */ +}; + +static struct efuse_info efuse_info_pcie = { + &offset_pcie, /* offset */ + &def_val_pcie, /* def_val */ + &len_pcie, /* len */ +}; + +static struct efuse_info efuse_info_usb_8852a = { + &offset_usb_8852a, /* offset */ + &def_val_usb_8852a, /* def_val */ + &len_usb, /* len */ +}; + +static struct efuse_info efuse_info_usb_8852b = { + &offset_usb_8852b, /* offset */ + &def_val_usb_8852b, /* def_val */ + &len_usb, /* len */ +}; + +static struct efuse_info efuse_info_sdio = { + &offset_sdio, /* offset */ + &def_val_sdio, /* def_val */ + &len_sdio, /* len */ +}; + +static u32 efuse_map_init(struct mac_ax_adapter *adapter, + enum efuse_map_sel map_sel); +static u32 efuse_fwcmd_ck(struct mac_ax_adapter *adapter); +static u32 efuse_proc_ck(struct mac_ax_adapter *adapter); +static u32 cnv_efuse_state(struct mac_ax_adapter *adapter, u8 dest_state); +static u32 switch_efuse_bank(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_bank bank); +static u32 proc_dump_efuse(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg); +static u32 read_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map); +static u32 write_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u8 value); +static u32 cmp_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u16 val); +static u32 eeprom_parser(struct mac_ax_adapter *adapter, u8 *phy_map, + u8 *log_map, enum mac_ax_efuse_parser_cfg cfg); +static u32 read_log_efuse_map(struct mac_ax_adapter *adapter, u8 *map, + u32 log_efuse_size); +static u32 proc_pg_efuse_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg); +static u32 dump_efuse_drv(struct mac_ax_adapter *adapter); +static u32 dump_efuse_fw(struct mac_ax_adapter *adapter); +static u32 proc_write_log_efuse(struct mac_ax_adapter *adapter, u32 offset, + u8 value); +static u32 read_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map); +static u32 update_eeprom_mask(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + u8 *updated_mask, bool pg_sim); +static u32 check_efuse_enough(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + u8 *updated_mask); +static u32 proc_pg_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset, bool pg_sim); +static u32 program_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *updated_mask, + bool pg_sim); +static void mask_eeprom(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); +static u32 query_status_map(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_feature_id feature_id, + u8 *map, bool is_limit); +static u32 adjust_mask(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); +static u32 compare_info_length(struct efuse_info *info, + enum rtw_efuse_info id, u32 length); +static u32 set_check_sum_val(struct mac_ax_adapter *adapter, + u8 *map, u16 value); +static void cal_check_sum(struct mac_ax_adapter *adapter, + u16 *chksum); +static u32 compare_version(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u32 ver_len); +static void add_dummy_read(struct mac_ax_adapter *adapter); +static void enable_OTP_burst_mode(struct mac_ax_adapter *adapter, + bool enable); +static void enable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter, + bool is_write); +static void disable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter, + bool is_write); +static u32 enable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter, + bool is_write); +static u32 disable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter, + bool is_write); +static u32 read_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map); +static u32 write_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, + u8 value); +static void switch_dv(struct mac_ax_adapter *adapter, enum rtw_dv_sel); + +u32 mac_dump_efuse_map_wl_plus(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_dump_efuse_map_wl(adapter, cfg, efuse_map); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + ret = mac_dump_efuse_map_wl(adapter, cfg, efuse_map); + if (ret) + return ret; + switch_dv(adapter, DAV); + ret = mac_dump_efuse_map_wl(adapter, MAC_AX_EFUSE_R_DRV, + efuse_map + hw_info->efuse_size); + switch_dv(adapter, DDV); + break; + default: + break; + } + + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_dump_efuse_map_wl(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map) +{ + u32 ret, stat; + +#if 0 + if (cfg == MAC_AX_EFUSE_R_FW || + (cfg == MAC_AX_EFUSE_R_AUTO && + adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY)) + return MACNOITEM; +#else + if (cfg == MAC_AX_EFUSE_R_FW && + adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) // no fw file + return MACNOFW; +#endif + + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (dv_sel == DAV) + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + else + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret != 0) + return ret; + + ret = proc_dump_efuse(adapter, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]dump efuse!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + query_status_map(adapter, MAC_AX_DUMP_PHYSICAL_EFUSE, efuse_map, 0); + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_dump_efuse_map_bt(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map) +{ + u32 ret, stat; + +#if 0 + if (cfg == MAC_AX_EFUSE_R_FW || + (cfg == MAC_AX_EFUSE_R_AUTO && + adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY)) + return MACNOITEM; +#else + if (cfg == MAC_AX_EFUSE_R_FW && + adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) // no fw file + return MACNOFW; +#endif + + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT); + if (ret != 0) + return ret; + + ret = proc_dump_efuse(adapter, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]dump efuse!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + query_status_map(adapter, MAC_AX_DUMP_PHYSICAL_EFUSE, efuse_map, 0); + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_write_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val, + enum mac_ax_efuse_bank bank) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + u32 efuse_size = hw_info->wl_efuse_size; + + switch (bank) { + case MAC_AX_EFUSE_BANK_WIFI: + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_write_efuse(adapter, addr, val, bank); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + if (addr < efuse_size) { + ret = mac_write_efuse(adapter, addr, val, bank); + } else { + switch_dv(adapter, DAV); + ret = mac_write_efuse(adapter, addr - + efuse_size, val, bank); + switch_dv(adapter, DDV); + } + break; + default: + break; + } + break; + case MAC_AX_EFUSE_BANK_BT: + ret = mac_write_efuse(adapter, addr, val, bank); + break; + default: + break; + } + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_write_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val, + enum mac_ax_efuse_bank bank) +{ + u32 ret, stat, efuse_size = 0; + + if (bank == MAC_AX_EFUSE_BANK_WIFI) { + if (OTP_test) + efuse_size = OTP_PHY_SIZE; + else + efuse_size = adapter->hw_info->wl_efuse_size; + } else if (bank == MAC_AX_EFUSE_BANK_BT) { + efuse_size = adapter->hw_info->bt_efuse_size; + } else { + return MACEFUSEBANK; + } + + if (addr >= efuse_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return MACEFUSESIZE; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, bank); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + enable_efuse_sw_pwr_cut(adapter, 1); + ret = write_hw_efuse(adapter, addr, val); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write physical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + disable_efuse_sw_pwr_cut(adapter, 1); + + if (bank == MAC_AX_EFUSE_BANK_BT) { + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return ret; +} + +u32 mac_read_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val, enum mac_ax_efuse_bank bank) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + u32 efuse_size = hw_info->wl_efuse_size; + u32 size1, size2; + + switch (bank) { + case MAC_AX_EFUSE_BANK_WIFI: + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_read_efuse(adapter, addr, size, val, bank); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + if (addr < efuse_size && addr + size <= efuse_size) { + ret = mac_read_efuse(adapter, addr, size, + val, bank); + } else if (addr >= efuse_size) { + switch_dv(adapter, DAV); + ret = mac_read_efuse(adapter, addr - efuse_size, + size, val, bank); + switch_dv(adapter, DDV); + } else if (addr < efuse_size && + addr + size > efuse_size) { + size1 = efuse_size - addr; + size2 = addr + size - efuse_size; + + ret = mac_read_efuse(adapter, addr, size1, + val, bank); + if (ret) + return ret; + + switch_dv(adapter, DAV); + ret = mac_read_efuse(adapter, 0, size2, + val + size1, bank); + switch_dv(adapter, DDV); + } + if (ret) + return ret; + break; + default: + break; + } + break; + case MAC_AX_EFUSE_BANK_BT: + ret = mac_read_efuse(adapter, addr, size, val, bank); + break; + default: + break; + } + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_read_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, u8 *val, + enum mac_ax_efuse_bank bank) +{ + u32 ret, stat, efuse_size = 0; + + if (bank == MAC_AX_EFUSE_BANK_WIFI) { + if (OTP_test) + efuse_size = OTP_PHY_SIZE; + else + efuse_size = adapter->hw_info->wl_efuse_size; + } else if (bank == MAC_AX_EFUSE_BANK_BT) { + efuse_size = adapter->hw_info->bt_efuse_size; + } else { + return MACEFUSEBANK; + } + + if (addr >= efuse_size || addr + size > efuse_size) { + PLTFM_MSG_ERR("[ERR] Wrong efuse index\n"); + return MACEFUSESIZE; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, bank); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = read_hw_efuse(adapter, addr, size, val); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]read hw efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (bank == MAC_AX_EFUSE_BANK_BT) { + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_get_efuse_avl_size(struct mac_ax_adapter *adapter, u32 *size) +{ + u32 ret; + u8 *map; + u32 efuse_size = adapter->hw_info->log_efuse_size; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + ret = mac_dump_log_efuse(adapter, MAC_AX_EFUSE_PARSER_MAP, + MAC_AX_EFUSE_R_AUTO, map, 0); + + PLTFM_FREE(map, efuse_size); + + if (ret != 0) + return ret; + + *size = adapter->hw_info->efuse_size - efuse_param->efuse_end; + + return MACSUCCESS; +} + +u32 mac_get_efuse_avl_size_bt(struct mac_ax_adapter *adapter, u32 *size) +{ + u32 ret; + u8 *map; + u32 efuse_size = adapter->hw_info->bt_log_efuse_size; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + ret = mac_dump_log_efuse_bt(adapter, MAC_AX_EFUSE_PARSER_MAP, + MAC_AX_EFUSE_R_DRV, map); + + PLTFM_FREE(map, efuse_size); + + if (ret != 0) + return ret; + + *size = adapter->hw_info->bt_efuse_size - efuse_param->bt_efuse_end; + + return MACSUCCESS; +} + +u32 mac_dump_log_efuse_plus(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map, bool is_limit) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + enum mac_ax_intf intf = adapter->hw_info->intf; + u32 map_size = hw_info->log_efuse_size; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_dump_log_efuse(adapter, parser_cfg, cfg, + efuse_map, is_limit); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + ret = mac_dump_log_efuse(adapter, parser_cfg, cfg, + efuse_map, is_limit); + if (ret) + return ret; + switch_dv(adapter, DAV); + if (is_limit) { + switch (intf) { + case MAC_AX_INTF_PCIE: + map_size = hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + map_size = hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + map_size = hw_info->limit_efuse_size_sdio; + break; + default: + break; + } + } + ret = mac_dump_log_efuse(adapter, parser_cfg, + MAC_AX_EFUSE_R_DRV, efuse_map + + map_size, 0); + switch_dv(adapter, DDV); + break; + default: + break; + } + + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_dump_log_efuse(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map, bool is_limit) +{ + u8 *map = NULL; + u32 ret, stat; + u32 efuse_size; + +#if 0 + if (cfg == MAC_AX_EFUSE_R_FW || + (cfg == MAC_AX_EFUSE_R_AUTO && + adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY)) + return MACNOITEM; +#else + if (cfg == MAC_AX_EFUSE_R_FW && + adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; +#endif + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + efuse_size = *bank_efuse_info.log_map_size; + + if (dv_sel == DAV) { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + if (ret != 0) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV); + } else { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG); + if (ret != 0) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + } + if (ret) + return ret; + + if (*bank_efuse_info.log_map_valid == 0) { + ret = proc_dump_efuse(adapter, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]dump efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (*bank_efuse_info.phy_map_valid == 1) { + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + stat = cnv_efuse_state(adapter, + MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return MACBUFALLOC; + } + + ret = eeprom_parser(adapter, *bank_efuse_info.phy_map, + map, parser_cfg); + if (ret != 0) { + PLTFM_FREE(map, efuse_size); + stat = cnv_efuse_state(adapter, + MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(*bank_efuse_info.log_map, map, + efuse_size); + *bank_efuse_info.log_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + } + } + + query_status_map(adapter, MAC_AX_DUMP_LOGICAL_EFUSE, + efuse_map, is_limit); + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_read_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + u32 efuse_size = hw_info->log_efuse_size; + u32 size1, size2; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_read_log_efuse(adapter, addr, size, val); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + if (addr < efuse_size && addr + size <= efuse_size) { + ret = mac_read_log_efuse(adapter, addr, size, val); + } else if (addr >= efuse_size) { + switch_dv(adapter, DAV); + ret = mac_read_log_efuse(adapter, addr - efuse_size, + size, val); + switch_dv(adapter, DDV); + } else if (addr < efuse_size && addr + size > efuse_size) { + size1 = efuse_size - addr; + size2 = addr + size - efuse_size; + + ret = mac_read_log_efuse(adapter, addr, size1, val); + if (ret) + return ret; + + switch_dv(adapter, DAV); + ret = mac_read_log_efuse(adapter, 0, size2, + val + size1); + switch_dv(adapter, DDV); + } + if (ret) + return ret; + break; + default: + break; + } + + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_read_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val) +{ + u8 *map = NULL; + u32 ret = 0, stat; + u32 efuse_size; + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + efuse_size = *bank_efuse_info.log_map_size; + + if (addr >= efuse_size || addr + size > efuse_size) { + PLTFM_MSG_ERR("[ERR] Wrong efuse index\n"); + return MACEFUSESIZE; + } + + if (dv_sel == DAV) { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV); + } else { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG); + } + if (ret) + return ret; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return MACBUFALLOC; + } + + ret = read_log_efuse_map(adapter, map, efuse_size); + if (ret != 0) { + PLTFM_FREE(map, efuse_size); + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(val, map + addr, size); + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + + return MACSUCCESS; +} + +u32 mac_write_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val) +{ + u32 ret = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = hw_info->chip_id; + u32 efuse_size = hw_info->log_efuse_size; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_write_log_efuse(adapter, addr, val); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + if (addr < efuse_size) { + ret = mac_write_log_efuse(adapter, addr, val); + } else { + switch_dv(adapter, DAV); + ret = mac_write_log_efuse(adapter, + addr - efuse_size, val); + switch_dv(adapter, DDV); + } + break; + default: + break; + } + + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_write_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val) +{ + u32 ret, stat; + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (addr >= *bank_efuse_info.log_map_size) { + PLTFM_MSG_ERR("[ERR]addr is too large\n"); + return MACEFUSESIZE; + } + + if (dv_sel == DAV) { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV); + } else { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG); + } + if (ret) + return ret; + + ret = proc_write_log_efuse(adapter, addr, val); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write logical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_dump_log_efuse_bt(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map) +{ + u8 *map = NULL; + u32 ret, stat; + u32 efuse_size = adapter->hw_info->bt_log_efuse_size; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + +#if 0 + if (cfg == MAC_AX_EFUSE_R_FW || + (cfg == MAC_AX_EFUSE_R_AUTO && + adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY)) + return MACNOITEM; +#else + if (cfg == MAC_AX_EFUSE_R_FW && + adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; +#endif + + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT); + if (ret != 0) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT); + if (ret != 0) + return ret; + + if (efuse_param->bt_log_efuse_map_valid == 0) { + ret = proc_dump_efuse(adapter, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]dump efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (efuse_param->bt_efuse_map_valid == 1) { + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + stat = cnv_efuse_state(adapter, + MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return MACBUFALLOC; + } + + ret = eeprom_parser(adapter, efuse_param->bt_efuse_map, + map, parser_cfg); + if (ret != 0) { + PLTFM_FREE(map, efuse_size); + stat = cnv_efuse_state(adapter, + MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(efuse_param->bt_log_efuse_map, map, + efuse_size); + efuse_param->bt_log_efuse_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + } + } + + query_status_map(adapter, MAC_AX_DUMP_LOGICAL_EFUSE, efuse_map, 0); + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_read_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val) +{ + u8 *map = NULL; + u32 ret, stat; + u32 efuse_size = adapter->hw_info->bt_log_efuse_size; + + if (addr >= efuse_size || addr + size > efuse_size) { + PLTFM_MSG_ERR("[ERR] Wrong efuse index\n"); + return MACEFUSESIZE; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT); + if (ret) + return ret; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return MACBUFALLOC; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + + ret = read_log_efuse_map(adapter, map, efuse_size); + if (ret != 0) { + PLTFM_FREE(map, efuse_size); + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(val, map + addr, size); + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + + return MACSUCCESS; +} + +u32 mac_write_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u8 val) +{ + u32 ret, stat; + + if (addr >= adapter->hw_info->log_efuse_size) { + PLTFM_MSG_ERR("[ERR]addr is too large\n"); + return MACEFUSESIZE; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT); + if (ret) + return ret; + + ret = proc_write_log_efuse(adapter, addr, val); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write logical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_pg_efuse_by_map_plus(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg, + bool part, bool is_limit) +{ + u8 chip_id = adapter->hw_info->chip_id; + u32 ret; + struct mac_ax_pg_efuse_info info_DAV; + u32 ver_len = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + enum mac_ax_intf intf = adapter->hw_info->intf; + u32 map_size = adapter->hw_info->log_efuse_size; + //u8 *phy_map = NULL; + + ret = mac_get_hw_value(adapter, + MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len); + if (ret) + return ret; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_pg_efuse_by_map(adapter, info, cfg, part, is_limit); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + /* cut map */ + if (is_limit) { + switch (intf) { + case MAC_AX_INTF_PCIE: + map_size = hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + map_size = hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + map_size = hw_info->limit_efuse_size_sdio; + break; + default: + break; + } + } + + info_DAV.efuse_map_size = hw_info->dav_log_efuse_size; + info_DAV.efuse_mask_size = hw_info->dav_log_efuse_size >> 4; + + info_DAV.efuse_map = (u8 *)PLTFM_MALLOC(info_DAV.efuse_map_size + ver_len); + if (!info_DAV.efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + info_DAV.efuse_mask = (u8 *)PLTFM_MALLOC(info_DAV.efuse_mask_size + ver_len); + if (!info_DAV.efuse_mask) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + PLTFM_MEMCPY(info_DAV.efuse_map, info->efuse_map + map_size, + info_DAV.efuse_map_size + ver_len); + PLTFM_MEMCPY(info_DAV.efuse_mask, + info->efuse_mask + (map_size >> 4), + info_DAV.efuse_mask_size + ver_len); + + info->efuse_map_size -= info_DAV.efuse_map_size; + info->efuse_mask_size -= info_DAV.efuse_mask_size; + + PLTFM_MEMCPY(info->efuse_map + map_size, info->efuse_map + + map_size + info_DAV.efuse_map_size, ver_len); + PLTFM_MEMCPY(info->efuse_mask + (map_size >> 4), + info->efuse_mask + (map_size >> 4) + + info_DAV.efuse_mask_size, ver_len); + + ret = mac_pg_efuse_by_map(adapter, info, cfg, part, is_limit); + if (ret) + return ret; + switch_dv(adapter, DAV); + ret = mac_pg_efuse_by_map(adapter, + &info_DAV, cfg, part, 0); + //phy_map = (u8 *)PLTFM_MALLOC(hw_info->wl_efuse_size_DAV); + //if (!phy_map) { + // PLTFM_MSG_ERR("[ERR]malloc map\n"); + // return MACBUFALLOC; + //} + //PLTFM_MEMSET(phy_map, 0xFF, hw_info->wl_efuse_size_DAV); + //ret = mac_pg_simulator(adapter, &info_DAV, phy_map); + switch_dv(adapter, DDV); + break; + default: + break; + } + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_pg_efuse_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg, + bool part, bool is_limit) +{ + u32 ret, stat; + enum mac_ax_intf intf = adapter->hw_info->intf; + u32 map_size = adapter->hw_info->log_efuse_size; + u32 ver_len = 0; + + if (is_limit) { + switch (intf) { + case MAC_AX_INTF_PCIE: + map_size = adapter->hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + map_size = adapter->hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + map_size = adapter->hw_info->limit_efuse_size_sdio; + break; + default: + break; + } + } + + if (dv_sel == DAV) + map_size = adapter->hw_info->dav_log_efuse_size; + + if (info->efuse_map_size != map_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return MACEFUSESIZE; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return MACEFUSESIZE; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return MACNPTR; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return MACNPTR; + } + + ret = mac_get_hw_value(adapter, + MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len); + if (ret) + return ret; + ret = compare_version(adapter, info, ver_len); + if (ret != 0) + return ret; + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + if (dv_sel == DAV) { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV); + } else { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG); + } + if (ret) + return ret; + + if (part) + ret = adjust_mask(adapter, info); + if (ret != 0) { + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = proc_pg_efuse_by_map(adapter, info, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_pg_efuse_by_map_bt(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg) +{ + u32 ret, stat; + + if (info->efuse_map_size != adapter->hw_info->bt_log_efuse_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return MACEFUSESIZE; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return MACEFUSESIZE; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return MACNPTR; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return MACNPTR; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = proc_pg_efuse_by_map(adapter, info, cfg); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_mask_log_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info) +{ + if (info->efuse_map_size != adapter->hw_info->log_efuse_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return MACEFUSESIZE; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return MACEFUSESIZE; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return MACNPTR; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return MACNPTR; + } + + mask_eeprom(adapter, info); + + return MACSUCCESS; +} + +u32 mac_pg_sec_data_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info) +{ + u32 ret, stat; + u32 addr, efuse_size, sec_data_size; + u8 *map_pg; + u32 mac_addr_size = 6; + + /*Soar TBD add MAC address PG*/ + + map_pg = info->efuse_map; + efuse_size = adapter->hw_info->efuse_size; + sec_data_size = adapter->hw_info->sec_data_efuse_size; + + if (info->efuse_map_size != adapter->hw_info->sec_data_efuse_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return MACNPTR; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + enable_efuse_sw_pwr_cut(adapter, 1); + for (addr = mac_addr_size; addr < sec_data_size; addr++) { + ret = write_hw_efuse(adapter, addr + efuse_size, + *(map_pg + addr)); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write physical efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + } + disable_efuse_sw_pwr_cut(adapter, 1); + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_cmp_sec_data_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info) +{ + u32 ret, stat; + u32 addr, start_addr, sec_data_size; + u16 val16; + u8 *map_pg; + + map_pg = info->efuse_map; + start_addr = adapter->hw_info->efuse_size; + sec_data_size = adapter->hw_info->sec_data_efuse_size; + + if (info->efuse_map_size != adapter->hw_info->sec_data_efuse_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return MACNPTR; + } + + ret = efuse_proc_ck(adapter); + if (ret != 0) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + return ret; + } + + for (addr = 0; + addr < sec_data_size; addr += 2) { + val16 = *(map_pg + addr) | (*(map_pg + addr + 1) << 8); + ret = cmp_hw_efuse(adapter, addr + start_addr, val16); + if (ret == MACEFUSECMP) { + *(map_pg + addr) = 0xFF; + *(map_pg + addr + 1) = 0xFF; + } else if (ret == MACEFUSEREAD) { + PLTFM_MSG_ERR("[ERR]compare hw efuse\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != 0) + return stat; + } else if (ret == 0) { + *(map_pg + addr) = 0x00; + *(map_pg + addr + 1) = 0x00; + } + } + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != 0) + return ret; + + return MACSUCCESS; +} + +u32 mac_get_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 *autoload_status) +{ + u32 offset, def_val; + u32 ret; + enum mac_ax_intf intf = adapter->hw_info->intf; + struct efuse_info info; + + switch (intf) { + case MAC_AX_INTF_USB: + info = (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) ? + efuse_info_usb_8852a : efuse_info_usb_8852b; + break; + case MAC_AX_INTF_PCIE: + info = efuse_info_pcie; + break; + case MAC_AX_INTF_SDIO: + info = efuse_info_sdio; + break; + default: + return MACINTF; + } + + ret = compare_info_length(&info, id, length); + if (ret != MACSUCCESS) + return ret; + + switch (id) { + case EFUSE_INFO_MAC_ADDR: + offset = info.offset->mac_addr; + def_val = info.def_val->mac_addr; + break; + case EFUSE_INFO_MAC_PID: + offset = info.offset->pid; + def_val = info.def_val->pid; + break; + case EFUSE_INFO_MAC_DID: + offset = info.offset->did; + def_val = info.def_val->did; + break; + case EFUSE_INFO_MAC_VID: + offset = info.offset->vid; + def_val = info.def_val->vid; + break; + case EFUSE_INFO_MAC_SVID: + offset = info.offset->svid; + def_val = info.def_val->svid; + break; + case EFUSE_INFO_MAC_SMID: + offset = info.offset->smid; + def_val = info.def_val->smid; + break; + default: + return MACNOITEM; + } + + if (*autoload_status == 0) + PLTFM_MEMCPY(value, &def_val, 1); + else + PLTFM_MEMCPY(value, efuse_map + offset, length); + + return MACSUCCESS; +} + +u32 mac_set_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length) +{ + u32 offset; + u32 ret; + enum mac_ax_intf intf = adapter->hw_info->intf; + struct efuse_info info; + + switch (intf) { + case MAC_AX_INTF_USB: + info = (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) ? + efuse_info_usb_8852a : efuse_info_usb_8852b; + break; + case MAC_AX_INTF_PCIE: + info = efuse_info_pcie; + break; + case MAC_AX_INTF_SDIO: + info = efuse_info_sdio; + break; + default: + return MACINTF; + } + + ret = compare_info_length(&info, id, length); + if (ret != MACSUCCESS) + return ret; + + switch (id) { + case EFUSE_INFO_MAC_ADDR: + offset = info.offset->mac_addr; + break; + case EFUSE_INFO_MAC_PID: + offset = info.offset->pid; + break; + case EFUSE_INFO_MAC_DID: + offset = info.offset->did; + break; + case EFUSE_INFO_MAC_VID: + offset = info.offset->vid; + break; + case EFUSE_INFO_MAC_SVID: + offset = info.offset->svid; + break; + case EFUSE_INFO_MAC_SMID: + offset = info.offset->smid; + break; + default: + return MACNOITEM; + } + + PLTFM_MEMCPY(efuse_map + offset, value, length); + + return MACSUCCESS; +} + +u32 mac_read_hidden_rpt(struct mac_ax_adapter *adapter, + struct mac_defeature_value *rpt) +{ +#if 0 + return MACNOITEM; +#else + u32 ret, stat; + struct mac_ax_h2creg_info h2c; + struct mac_ax_c2hreg_poll c2h; + struct fwcmd_c2hreg *c2h_content; + + ret = efuse_proc_ck(adapter); + if (ret != MACSUCCESS) + return ret; + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY); + if (ret != MACSUCCESS) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat != MACSUCCESS) + return stat; + return ret; + } + + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret != MACSUCCESS) + return ret; + + h2c.id = FWCMD_H2CREG_FUNC_HIDDEN_GET; + h2c.content_len = sizeof(struct mac_efuse_hidden_h2creg); + + c2h.polling_id = FWCMD_C2HREG_FUNC_EFUSE_HIDDEN; + c2h.retry_cnt = EFUSE_C2HREG_WAIT_CNT; + c2h.retry_wait_us = EFUSE_C2HREG_RETRY_WAIT_US; + + ret = proc_msg_reg(adapter, &h2c, &c2h); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]read hidden rpt proc msg reg %d\n", ret); + stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (stat) + return stat; + return ret; + } + + c2h_content = &c2h.c2hreg_cont.c2h_content; + rpt->rx_spatial_stream = + GET_FIELD(c2h_content->dword0, FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS); + rpt->bandwidth = + GET_FIELD(c2h_content->dword0, FWCMD_C2HREG_EFUSE_HIDDEN_BW); + rpt->tx_spatial_stream = + GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS); + rpt->protocol_80211 = + GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211); + rpt->NIC_router = + GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER); + rpt->wl_func_support = + GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT); + rpt->hw_special_type = + GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE); + rpt->uuid = + GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3) << 24 | + GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2) << 16 | + GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1) << 8 | + GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0); + + ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +#endif +} + +u32 mac_check_efuse_autoload(struct mac_ax_adapter *adapter, + u8 *autoload_status) +{ +#define AUTOLOAD_SUS 1 +#define AUTOLOAD_FAIL 0 + + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (MAC_REG_R16(R_AX_SYS_EEPROM_CTRL) & B_AX_AUTOLOAD_SUS) + *autoload_status = AUTOLOAD_SUS; + else + *autoload_status = AUTOLOAD_FAIL; + + return MACSUCCESS; + +#undef AUTOLOAD_SUS +#undef AUTOLOAD_FAIL +} + +u32 mac_pg_simulator_plus(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *phy_map) +{ + u8 chip_id = adapter->hw_info->chip_id; + u32 ret; + struct mac_ax_pg_efuse_info info_dav; + u32 ver_len = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u32 map_size = hw_info->log_efuse_size; + + ret = mac_get_hw_value(adapter, + MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len); + if (ret) + return ret; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + ret = mac_pg_simulator(adapter, info, phy_map); + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + /* cut log map */ + info_dav.efuse_map_size = hw_info->dav_log_efuse_size; + info_dav.efuse_mask_size = hw_info->dav_log_efuse_size >> 4; + + info_dav.efuse_map = + (u8 *)PLTFM_MALLOC(info_dav.efuse_map_size + ver_len); + if (!info_dav.efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + info_dav.efuse_mask = + (u8 *)PLTFM_MALLOC(info_dav.efuse_mask_size + + ver_len); + if (!info_dav.efuse_mask) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + PLTFM_MEMCPY(info_dav.efuse_map, info->efuse_map + map_size, + info_dav.efuse_map_size + ver_len); + PLTFM_MEMCPY(info_dav.efuse_mask, + info->efuse_mask + (map_size >> 4), + info_dav.efuse_mask_size + ver_len); + + info->efuse_map_size -= info_dav.efuse_map_size; + info->efuse_mask_size -= info_dav.efuse_mask_size; + + PLTFM_MEMCPY(info->efuse_map + map_size, info->efuse_map + + map_size + info_dav.efuse_map_size, ver_len); + PLTFM_MEMCPY(info->efuse_mask + (map_size >> 4), + info->efuse_mask + (map_size >> 4) + + info_dav.efuse_mask_size, ver_len); + + ret = mac_pg_simulator(adapter, info, phy_map); + if (ret) + return ret; + switch_dv(adapter, DAV); + ret = mac_pg_simulator(adapter, &info_dav, + phy_map + hw_info->wl_efuse_size); + switch_dv(adapter, DDV); + PLTFM_MEMCPY(info->efuse_map + map_size, info_dav.efuse_map, + info_dav.efuse_map_size + ver_len); + break; + default: + break; + } + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_pg_simulator(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *phy_map) +{ + u8 *updated_mask; + u32 ret; + u32 mask_size; + u8 *log_efuse_map = NULL; + enum mac_ax_intf intf = adapter->hw_info->intf; + u32 map_size = adapter->hw_info->log_efuse_size; + u32 ver_len = 0; + + if (info->efuse_map_size != adapter->hw_info->log_efuse_size) { + switch (intf) { + case MAC_AX_INTF_PCIE: + map_size = adapter->hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + map_size = adapter->hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + map_size = adapter->hw_info->limit_efuse_size_sdio; + break; + default: + break; + } + } + + if (dv_sel == DAV) + map_size = adapter->hw_info->dav_log_efuse_size; + + if (info->efuse_map_size != map_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return MACEFUSESIZE; + } + + mask_size = map_size >> 4; + + ret = mac_get_hw_value(adapter, + MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len); + if (ret) + return ret; + + ret = compare_version(adapter, info, ver_len); + if (ret != 0) + return ret; + + ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return ret; + } + + if (dv_sel == DAV) { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV); + } else { + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL); + if (ret) + return ret; + ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG); + } + if (ret) + return ret; + + ret = eeprom_parser(adapter, phy_map, *bank_efuse_info.log_map, + MAC_AX_EFUSE_PARSER_MAP); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]logical map parser\n"); + return ret; + } + PLTFM_MEMCPY(*bank_efuse_info.phy_map, phy_map, + *bank_efuse_info.phy_map_size); + + updated_mask = (u8 *)PLTFM_MALLOC(mask_size); + if (!updated_mask) { + PLTFM_MSG_ERR("[ERR]malloc updated mask\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(updated_mask, 0x00, mask_size); + + ret = update_eeprom_mask(adapter, info, updated_mask, 1); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]update eeprom mask\n"); + goto error; + } + + ret = check_efuse_enough(adapter, info, updated_mask); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]chk efuse enough\n"); + goto error; + } + + ret = program_efuse(adapter, info, updated_mask, 1); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + goto error; + } + + PLTFM_FREE(updated_mask, mask_size); + + PLTFM_MEMCPY(phy_map, *bank_efuse_info.phy_map, + *bank_efuse_info.phy_map_size); + ret = eeprom_parser(adapter, phy_map, info->efuse_map, + MAC_AX_EFUSE_PARSER_MAP); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]parser error\n"); + PLTFM_FREE(log_efuse_map, map_size); + return ret; + } + + /* For subsequent dump */ + *bank_efuse_info.log_map_valid = 0; + *bank_efuse_info.phy_map_valid = 0; + + return MACSUCCESS; + +error: + PLTFM_FREE(updated_mask, mask_size); + return ret; +} + +u32 mac_checksum_update(struct mac_ax_adapter *adapter) +{ + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u32 log_efuse_size = hw_info->log_efuse_size; + u8 *map; + u16 chksum; + u32 ret; + + map = (u8 *)PLTFM_MALLOC(log_efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(map, 0xFF, log_efuse_size); + + ret = mac_dump_log_efuse(adapter, MAC_AX_EFUSE_PARSER_MAP, + MAC_AX_EFUSE_R_AUTO, map, 0); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]Dump log map\n"); + goto error; + } + + cal_check_sum(adapter, &chksum); + + ret = set_check_sum_val(adapter, map, chksum); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write check sum\n"); + goto error; + } + + PLTFM_FREE(map, log_efuse_size); + return MACSUCCESS; +error: + PLTFM_FREE(map, log_efuse_size); + return ret; +} + +u32 mac_checksum_rpt(struct mac_ax_adapter *adapter, u16 *chksum) +{ + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u32 log_efuse_size = hw_info->log_efuse_size; + u8 *tmp; + u32 ret; + u16 real_chksum = 0; + + /* Read chksum val */ + tmp = (u8 *)PLTFM_MALLOC(sizeof(real_chksum)); + if (!tmp) { + PLTFM_MSG_ERR("[ERR]malloc tmp\n"); + return MACBUFALLOC; + } + ret = mac_read_log_efuse(adapter, chksum_offset_1, sizeof(real_chksum), + tmp); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]read log efuse\n"); + PLTFM_FREE(tmp, sizeof(real_chksum)); + return ret; + } + + real_chksum = *(u16 *)tmp; + PLTFM_FREE(tmp, sizeof(real_chksum)); + + if (real_chksum == 0xFFFF) + return MACCHKSUMEMPTY; + + /* Read log map*/ + tmp = (u8 *)PLTFM_MALLOC(log_efuse_size); + if (!tmp) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(tmp, 0xFF, log_efuse_size); + + ret = mac_read_log_efuse(adapter, 0, log_efuse_size, tmp); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]read log efuse\n"); + PLTFM_FREE(tmp, log_efuse_size); + return ret; + } + PLTFM_FREE(tmp, log_efuse_size); + + cal_check_sum(adapter, chksum); + if (*chksum != real_chksum) + return MACCHKSUMFAIL; + + return MACSUCCESS; +} + +u32 mac_disable_rf(struct mac_ax_adapter *adapter, + enum mac_ax_disable_rf_func func, enum mac_ax_net_type type) +{ + u32 ret; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + u8 *buf; + struct fwcmd_disable_rf *write_ptr; + + /* H2C */ + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr)); + if (!buf) { + h2cb_free(adapter, h2cb); + return MACNOBUF; + } + + write_ptr = (struct fwcmd_disable_rf *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(func, FWCMD_H2C_DISABLE_RF_FUNC) | + SET_WORD(type, FWCMD_H2C_DISABLE_RF_NET_TYPE) + ); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_DISABLE_RF, + 0, 0); + if (ret) { + h2cb_free(adapter, h2cb); + return ret; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + h2cb_free(adapter, h2cb); + return ret; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + h2cb_free(adapter, h2cb); + return ret; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +} + +u32 mac_check_OTP(struct mac_ax_adapter *adapter, u8 is_start) +{ +#define is_read 0 +#define secure 1 + u32 ret; + u8 val8; + + if (is_start == 1) { + enable_efuse_sw_pwr_cut(adapter, is_read); + + mac_set_efuse_ctrl(adapter, secure); + read_efuse_cnt = CHK_OTP_WAIT_CNT; + + ret = mac_read_efuse_plus(adapter, CHK_OTP_ADDR, 1, &val8, + MAC_AX_EFUSE_BANK_WIFI); + + disable_efuse_sw_pwr_cut(adapter, is_read); + + mac_set_efuse_ctrl(adapter, !secure); + read_efuse_cnt = EFUSE_WAIT_CNT; + } + + return MACSUCCESS; +} + +void mac_set_efuse_ctrl(struct mac_ax_adapter *adapter, u8 is_secure) +{ + efuse_ctrl = is_secure ? R_AX_EFUSE_CTRL_S : R_AX_EFUSE_CTRL; +} + +u32 mac_otp_test(struct mac_ax_adapter *adapter, bool is_OTP_test) +{ + if (is_OTP_test) + OTP_test = 1; + else + OTP_test = 0; + + return MACSUCCESS; +} + +void cfg_efuse_auto_ck(struct mac_ax_adapter *adapter, u8 enable) +{ + /*Soar TBD* move to set hw value */ + +#ifdef NEVER + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + adapter->efuse_param.auto_ck_en = enable; + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); +#endif /* NEVER */ +} + +u32 efuse_tbl_init(struct mac_ax_adapter *adapter) +{ + PLTFM_MUTEX_INIT(&efuse_tbl.lock); + + return MACSUCCESS; +} + +u32 efuse_tbl_exit(struct mac_ax_adapter *adapter) +{ + PLTFM_MUTEX_DEINIT(&efuse_tbl.lock); + + return MACSUCCESS; +} + +static u32 efuse_map_init(struct mac_ax_adapter *adapter, + enum efuse_map_sel map_sel) +{ + u32 size; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + + switch (map_sel) { + case EFUSE_MAP_SEL_PHY_WL: + size = adapter->hw_info->efuse_size; + if (!efuse_param->efuse_map) { + efuse_param->efuse_map = (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + case EFUSE_MAP_SEL_PHY_BT: + size = adapter->hw_info->bt_efuse_size; + if (!efuse_param->bt_efuse_map) { + efuse_param->bt_efuse_map = (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->bt_efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + case EFUSE_MAP_SEL_LOG: + size = adapter->hw_info->log_efuse_size; + if (!efuse_param->log_efuse_map) { + efuse_param->log_efuse_map = (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->log_efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + case EFUSE_MAP_SEL_LOG_BT: + size = adapter->hw_info->bt_log_efuse_size; + if (!efuse_param->bt_log_efuse_map) { + efuse_param->bt_log_efuse_map = + (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->bt_log_efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + case EFUSE_MAP_SEL_PHY_DAV: + size = adapter->hw_info->dav_efuse_size; + if (!efuse_param->dav_efuse_map) { + efuse_param->dav_efuse_map = (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->dav_efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + case EFUSE_MAP_SEL_LOG_DAV: + size = adapter->hw_info->dav_log_efuse_size; + if (!efuse_param->dav_log_efuse_map) { + efuse_param->dav_log_efuse_map = + (u8 *)PLTFM_MALLOC(size); + if (!efuse_param->dav_log_efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + } + break; + default: + break; + } + + return MACSUCCESS; +} + +static u32 efuse_fwcmd_ck(struct mac_ax_adapter *adapter) +{ +/*Soar TBD*/ +#ifdef NEVER + u32 ret; + + ret = fwcmd_wq_idle(adapter, + SET_FWCMD_ID(FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + TBD, + TBD)); + if (ret != 0) { + PLTFM_MSG_WARN("[WARN]H2C not idle(efuse)\n"); + return ret; + } +#endif /* NEVER */ + return MACSUCCESS; +} + +static u32 efuse_proc_ck(struct mac_ax_adapter *adapter) +{ +/*Soar TBD*/ +#ifdef NEVER + u32 ret; + + ret = efuse_fwcmd_ck(adapter); + if (ret != 0) + return ret; +#endif /* NEVER */ + if (adapter->sm.efuse != MAC_AX_EFUSE_IDLE) { + PLTFM_MSG_WARN("[WARN]Proc not idle(efuse)\n"); + return MACPROCBUSY; + } + + if (adapter->sm.pwr != MAC_AX_PWR_ON) + PLTFM_MSG_ERR("[ERR]Access efuse in suspend\n"); + + return MACSUCCESS; +} + +static u32 cnv_efuse_state(struct mac_ax_adapter *adapter, u8 dest_state) +{ + if (adapter->sm.efuse >= MAC_AX_EFUSE_MAX) + return MACPROCERR; + + if (adapter->sm.efuse == dest_state) + return MACPROCERR; + + if (dest_state != MAC_AX_EFUSE_IDLE) { + if (adapter->sm.efuse != MAC_AX_EFUSE_IDLE) + return MACPROCERR; + } + + adapter->sm.efuse = dest_state; + + return MACSUCCESS; +} + +static u32 switch_efuse_bank(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_bank bank) +{ + u8 reg_value; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u8 chip_id = adapter->hw_info->chip_id; + + switch (chip_id) { + case MAC_AX_CHIP_ID_8852A: + if (bank == MAC_AX_EFUSE_BANK_BT) { + /* check bt state */ + MAC_REG_W8(R_AX_SYSON_FSM_MON + 3, 0x05); + reg_value = MAC_REG_R8(R_AX_SYSON_FSM_MON); + if (reg_value != 0x04) + return MACEFUSEBANK; + } + + reg_value = MAC_REG_R8(R_AX_EFUSE_CTRL_1 + 1); + if (bank == (reg_value & B_AX_EF_CELL_SEL_MSK)) + goto set_val; + + reg_value &= ~B_AX_EF_CELL_SEL_MSK; + reg_value |= bank; + MAC_REG_W8(R_AX_EFUSE_CTRL_1 + 1, reg_value); + + reg_value = MAC_REG_R8(R_AX_EFUSE_CTRL_1 + 1); + if ((reg_value & B_AX_EF_CELL_SEL_MSK) == bank) + goto set_val; + else + return MACEFUSEBANK; + break; + case MAC_AX_CHIP_ID_8852B: + case MAC_AX_CHIP_ID_8852C: + case MAC_AX_CHIP_ID_8192XB: + goto set_val; + default: + break; + } + +set_val: + switch (bank) { + case MAC_AX_EFUSE_BANK_WIFI: + if (dv_sel == DAV) { + bank_efuse_info.phy_map = &efuse_param->dav_efuse_map; + bank_efuse_info.log_map = + &efuse_param->dav_log_efuse_map; + bank_efuse_info.phy_map_valid = + &efuse_param->dav_efuse_map_valid; + bank_efuse_info.log_map_valid = + &efuse_param->dav_log_efuse_map_valid; + bank_efuse_info.efuse_end = + &efuse_param->dav_efuse_end; + bank_efuse_info.phy_map_size = + &hw_info->dav_efuse_size; + bank_efuse_info.log_map_size = + &hw_info->dav_log_efuse_size; + bank_efuse_info.efuse_start = + &hw_info->dav_efuse_start_addr; + break; + } + + bank_efuse_info.phy_map = &efuse_param->efuse_map; + bank_efuse_info.log_map = &efuse_param->log_efuse_map; + bank_efuse_info.phy_map_valid = &efuse_param->efuse_map_valid; + bank_efuse_info.log_map_valid = + &efuse_param->log_efuse_map_valid; + bank_efuse_info.efuse_end = &efuse_param->efuse_end; + bank_efuse_info.phy_map_size = &hw_info->efuse_size; + bank_efuse_info.log_map_size = &hw_info->log_efuse_size; + bank_efuse_info.efuse_start = &hw_info->wl_efuse_start_addr; + break; + case MAC_AX_EFUSE_BANK_BT: + bank_efuse_info.phy_map = &efuse_param->bt_efuse_map; + bank_efuse_info.log_map = &efuse_param->bt_log_efuse_map; + bank_efuse_info.phy_map_valid = + &efuse_param->bt_efuse_map_valid; + bank_efuse_info.log_map_valid = + &efuse_param->bt_log_efuse_map_valid; + bank_efuse_info.efuse_end = &efuse_param->bt_efuse_end; + bank_efuse_info.phy_map_size = &hw_info->bt_efuse_size; + bank_efuse_info.log_map_size = &hw_info->bt_log_efuse_size; + bank_efuse_info.efuse_start = &hw_info->bt_efuse_start_addr; + break; + default: + return MACEFUSEBANK; + } + + return MACSUCCESS; +} + +static u32 proc_dump_efuse(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg) +{ + u32 ret; + + if (cfg == MAC_AX_EFUSE_R_AUTO) { + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + ret = dump_efuse_drv(adapter); + else + ret = dump_efuse_fw(adapter); + } else if (cfg == MAC_AX_EFUSE_R_FW) { + ret = dump_efuse_fw(adapter); + } else { + ret = dump_efuse_drv(adapter); + } + + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n"); + return ret; + } + + return MACSUCCESS; +} + +static u32 read_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map) +{ + u32 addr; + u32 tmp32 = 0; + u32 cnt; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 efuse_start = *bank_efuse_info.efuse_start; + + offset += efuse_start; + + if (dv_sel == DDV) { + enable_efuse_sw_pwr_cut(adapter, 0); + + for (addr = offset; addr < offset + size; addr++) { + MAC_REG_W32(efuse_ctrl, + ((addr & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH) + & ~B_AX_EF_RDY); + + cnt = read_efuse_cnt; + while (--cnt) { + tmp32 = MAC_REG_R32(efuse_ctrl); + if (tmp32 & B_AX_EF_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + return MACEFUSEREAD; + } + + *(map + addr - offset) = (u8)(tmp32 & 0xFF); + } + + disable_efuse_sw_pwr_cut(adapter, 0); + } else { + read_hw_efuse_dav(adapter, offset, size, map); + } + + return MACSUCCESS; +} + +static u32 write_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u8 value) +{ + //const u8 unlock_code = 0x69; + u8 value_read = 0; + u32 value32; + u32 cnt; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + u32 efuse_start = *bank_efuse_info.efuse_start; + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + *bank_efuse_info.phy_map_valid = 0; + *bank_efuse_info.log_map_valid = 0; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + + offset += efuse_start; + + if (dv_sel == DDV) { + //MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, unlock_code); + + value32 = value | + ((offset & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH); + value32 &= ~B_AX_EF_RDY; + MAC_REG_W32(efuse_ctrl, + value32 | (MODE_WRITE << B_AX_EF_MODE_SEL_SH)); + + cnt = EFUSE_WAIT_CNT; + while (--cnt) { + if (MAC_REG_R32(efuse_ctrl) & B_AX_EF_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return MACEFUSEWRITE; + } + + //MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, 0x00); + } else { + write_hw_efuse_dav(adapter, offset, value); + } + + if (efuse_param->auto_ck_en == 1) { + ret = read_hw_efuse(adapter, offset, 1, &value_read); + if (ret != 0) + return ret; + + if (value_read != value) { + PLTFM_MSG_ERR("[ERR]efuse compare\n"); + return MACEFUSEWRITE; + } + } + + return MACSUCCESS; +} + +static u32 cmp_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u16 val) +{ + u32 val32; + u32 tmp32 = 0; + u32 cnt; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = val | ((offset & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH); + MAC_REG_W32(efuse_ctrl, val32 | (MODE_CMP << B_AX_EF_MODE_SEL_SH)); + + cnt = EFUSE_WAIT_CNT; + while (--cnt) { + tmp32 = MAC_REG_R32(efuse_ctrl); + if (tmp32 & B_AX_EF_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]compare efuse\n"); + return MACEFUSEREAD; + } + + if (0 == (tmp32 & B_AX_EF_COMP_RESULT)) + return MACEFUSECMP; + + return MACSUCCESS; +} + +static u32 eeprom_parser(struct mac_ax_adapter *adapter, u8 *phy_map, + u8 *log_map, enum mac_ax_efuse_parser_cfg cfg) +{ + u8 i; + u8 value8; + u8 blk_idx; + u8 word_en; + u8 valid; + u8 hdr = 0; + u8 hdr2 = 0; + u32 eeprom_idx; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + u32 sec_ctrl_size = hw_info->sec_ctrl_efuse_size; + u32 efuse_idx; + u32 efuse_size = *bank_efuse_info.phy_map_size; + bool is_bt = 0; + u32 log_efuse_size = *bank_efuse_info.log_map_size; + + PLTFM_MEMSET(log_map, 0xFF, log_efuse_size); + + if (log_efuse_size == hw_info->bt_log_efuse_size) { + sec_ctrl_size = 0; + is_bt = 1; + } + efuse_idx = sec_ctrl_size; + + do { + if (efuse_idx >= efuse_size) // secure zone + break; + + value8 = *(phy_map + efuse_idx); + hdr = value8; + if (hdr == 0xff) + break; + efuse_idx++; + + if (is_bt) { + if ((hdr & 0xF) != 0xF) {// 1byte entry + blk_idx = (hdr & 0xF0) >> 4; + word_en = hdr & 0x0F; + } else {// 2byte entry + value8 = *(phy_map + efuse_idx); + hdr2 = value8; + if (hdr2 == 0xff) + break; + + blk_idx = (((hdr2 & 0xF0) >> 4) << 3) + + (((hdr & 0xF0) >> 4) >> 1); // offset + word_en = hdr2 & 0x0F; + + efuse_idx++; + } + } else { // WLAN + value8 = *(phy_map + efuse_idx); + hdr2 = value8; + if (hdr2 == 0xff) + break; + + blk_idx = ((hdr2 & 0xF0) >> 4) | ((hdr & 0x0F) << 4); + word_en = hdr2 & 0x0F; + + efuse_idx++; + } + + if (efuse_idx >= efuse_size - 1) + return MACEFUSEPARSE; + + for (i = 0; i < 4; i++) { + valid = (u8)((~(word_en >> i)) & BIT(0)); + if (valid == 1) { + eeprom_idx = (blk_idx << 3) + (i << 1); + + if ((eeprom_idx + 1) > + *bank_efuse_info.log_map_size) { + PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n", + efuse_idx - 1); + PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n", + hdr); + PLTFM_MSG_ERR("[ERR]read hdr2:0x%X\n", + hdr2); + return MACEFUSEPARSE; + } + + if (cfg == MAC_AX_EFUSE_PARSER_MAP) { + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + } else if (cfg == MAC_AX_EFUSE_PARSER_MASK) { + *(log_map + eeprom_idx) = 0x00; + } + + eeprom_idx++;// 1 byte + efuse_idx++; + + if (efuse_idx > efuse_size - 1) + return MACEFUSEPARSE; + + if (cfg == MAC_AX_EFUSE_PARSER_MAP) { + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + } else if (cfg == MAC_AX_EFUSE_PARSER_MASK) { + *(log_map + eeprom_idx) = 0x00; + } + + efuse_idx++; + + if (efuse_idx > efuse_size) + return MACEFUSEPARSE; + } + } + } while (1); + + *bank_efuse_info.efuse_end = efuse_idx; + + return MACSUCCESS; +} + +static u32 read_log_efuse_map(struct mac_ax_adapter *adapter, u8 *map, + u32 log_efuse_size) +{ + u8 *local_map = NULL; + u32 efuse_size = *bank_efuse_info.phy_map_size; + u32 ret; + + if (*bank_efuse_info.log_map_valid == 0) { + if (*bank_efuse_info.phy_map_valid == 0) { + local_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!local_map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + ret = read_efuse(adapter, 0, efuse_size, local_map); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + goto error; + } + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(*bank_efuse_info.phy_map, local_map, + efuse_size); + *bank_efuse_info.phy_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + + PLTFM_FREE(local_map, efuse_size); + } + + ret = eeprom_parser(adapter, *bank_efuse_info.phy_map, map, + MAC_AX_EFUSE_PARSER_MAP); + if (ret != 0) + return ret; + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(*bank_efuse_info.log_map, map, log_efuse_size); + *bank_efuse_info.log_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + } else { + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size); + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + } + + return MACSUCCESS; +error: + PLTFM_FREE(local_map, efuse_size); + return ret; +} + +static u32 proc_pg_efuse_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg) +{ + u8 *updated_mask = NULL; + u32 ret; + u32 log_efuse_size = *bank_efuse_info.log_map_size; + u32 mask_size = log_efuse_size >> 4; + + updated_mask = (u8 *)PLTFM_MALLOC(mask_size); + if (!updated_mask) { + PLTFM_MSG_ERR("[ERR]malloc updated mask\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(updated_mask, 0x00, mask_size); + + ret = update_eeprom_mask(adapter, info, updated_mask, 0); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]update eeprom mask\n"); + goto error; + } + + ret = check_efuse_enough(adapter, info, updated_mask); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]chk efuse enough\n"); + goto error; + } + + ret = program_efuse(adapter, info, updated_mask, 0); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + goto error; + } + + PLTFM_FREE(updated_mask, mask_size); + return MACSUCCESS; +error: + PLTFM_FREE(updated_mask, mask_size); + return ret; +} + +static u32 dump_efuse_drv(struct mac_ax_adapter *adapter) +{ + u8 *map = NULL; + u32 efuse_size = *bank_efuse_info.phy_map_size; + u32 ret; + + if (*bank_efuse_info.phy_map_valid == 0) { + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + ret = read_hw_efuse(adapter, 0, efuse_size, map); + if (ret != 0) { + PLTFM_FREE(map, efuse_size); + return ret; + } + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(*bank_efuse_info.phy_map, map, efuse_size); + *bank_efuse_info.phy_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + } + + return MACSUCCESS; +} + +static u32 dump_efuse_fw(struct mac_ax_adapter *adapter) +{ + u32 ret, cnt; + struct mac_ax_ops *ops = adapter->ops; + u8 *map = NULL; + u32 efuse_size = *bank_efuse_info.phy_map_size; + + if (*bank_efuse_info.phy_map_valid == 0) { + /* H2C */ + ret = ops->dump_efuse_ofld(adapter, efuse_size, 0); + if (ret) + return ret; + + /* Wait for C2H */ + cnt = EFUSE_FW_DUMP_WAIT_CNT; + while (--cnt) { + if (adapter->sm.efuse_ofld == MAC_AX_OFLD_H2C_DONE) + break; + PLTFM_DELAY_US(1); + } + if (!cnt) { + PLTFM_MSG_ERR("[ERR]efuse C2H\n"); + adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE; + return MACPROCERR; + } + + /* cpy map */ + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + + ret = ops->efuse_ofld_map(adapter, map, efuse_size); + if (ret) { + PLTFM_FREE(map, efuse_size); + return ret; + } + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(*bank_efuse_info.phy_map, map, efuse_size); + *bank_efuse_info.phy_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + PLTFM_FREE(map, efuse_size); + } + + return MACSUCCESS; +} + +static u32 proc_write_log_efuse(struct mac_ax_adapter *adapter, u32 offset, + u8 value) +{ + u8 byte1; + u8 byte2; + u8 blk; + u8 blk_idx; + u8 hdr; + u8 hdr2 = 0; + u8 *map = NULL; + u32 log_efuse_size = *bank_efuse_info.log_map_size; + u32 end, ret; + bool is_bt = 0; + + map = (u8 *)PLTFM_MALLOC(log_efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + if (*bank_efuse_info.log_map_valid == 0) { + ret = read_log_efuse_map(adapter, map, log_efuse_size); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + PLTFM_FREE(map, log_efuse_size); + return ret; + } + } else { + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size); + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + } + + if (log_efuse_size == adapter->hw_info->bt_log_efuse_size) + is_bt = 1; + + if (*(map + offset) != value) { + end = *bank_efuse_info.efuse_end; + + if (is_bt) { + if (offset < BT_1B_ENTRY_SIZE) { // 1 byte entry + blk = (u8)(offset >> 3); + blk_idx = (u8)((offset & (8 - 1)) >> 1);//mod8 + + hdr = (u8)((blk << 4) + + ((0x1 << blk_idx) ^ 0x0F)); + } else { // 2 byte entry + blk = (u8)(offset >> 3 >> 3); // large section + blk_idx = (u8)(((offset >> 3) & (8 - 1)) << 1); + hdr = (u8)((blk_idx << 4) + 0xF); + + blk_idx = (u8)((offset & (8 - 1)) >> 1); + hdr2 = (u8)((blk << 4) + + ((0x1 << blk_idx) ^ 0x0F)); + } + } else { + blk = (u8)(offset >> 3);// offset + blk_idx = (u8)((offset & (8 - 1)) >> 1); // mod8 0 1 2 3 + + hdr = ((blk & 0xF0) >> 4) | 0x30; + hdr2 = (u8)(((blk & 0x0F) << 4) + + ((0x1 << blk_idx) ^ 0x0F)); + } + + if ((offset & 1) == 0) { + byte1 = value; + byte2 = *(map + offset + 1); + } else { + byte1 = *(map + offset - 1); + byte2 = value; + } + + if (*bank_efuse_info.phy_map_size <= 4 + end) { // write 4 bytes + PLTFM_FREE(map, log_efuse_size); + return MACEFUSESIZE; + } + + enable_efuse_sw_pwr_cut(adapter, 1); + + ret = write_hw_efuse(adapter, end, hdr); + if (ret != 0) + goto error; + + if (!is_bt || offset >= BT_1B_ENTRY_SIZE) { + ret = write_hw_efuse(adapter, end + 1, hdr2); + if (ret != 0) + goto error; + end++; + } + + ret = write_hw_efuse(adapter, end + 1, byte1); + if (ret != 0) + goto error; + + ret = write_hw_efuse(adapter, end + 2, byte2); + if (ret != 0) + goto error; + + disable_efuse_sw_pwr_cut(adapter, 1); + } + + PLTFM_FREE(map, log_efuse_size); + return MACSUCCESS; +error: + PLTFM_FREE(map, log_efuse_size); + return ret; +} + +static u32 read_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map) +{ + u32 ret; + + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + + if (*bank_efuse_info.phy_map_valid == 1) { + PLTFM_MEMCPY(map, *bank_efuse_info.phy_map + offset, size); + } else { + ret = read_hw_efuse(adapter, offset, size, map); + if (ret != 0) + return ret; + } + + return MACSUCCESS; +} + +static u32 update_eeprom_mask(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + u8 *updated_mask, bool pg_sim) +{ + u8 *map = NULL; + u8 *mask_map = NULL; + u8 clr_bit = 0; + u8 *map_pg; + u8 *efuse_mask; + u32 i; + u16 j; + u16 map_offset; + u16 mask_offset; + u32 ret; + u32 log_efuse_size = *bank_efuse_info.log_map_size; + + map = (u8 *)PLTFM_MALLOC(log_efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return MACBUFALLOC; + } + PLTFM_MEMSET(map, 0xFF, log_efuse_size); // default: 0xFF + + if (pg_sim) { //WL + PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size); + } else { + ret = read_log_efuse_map(adapter, map, log_efuse_size); + if (ret != 0) + goto error; + } + + /*log mask*/ + mask_map = (u8 *)PLTFM_MALLOC(log_efuse_size); + if (!mask_map) { + PLTFM_MSG_ERR("[ERR]malloc mask map\n"); + PLTFM_FREE(map, log_efuse_size); + return MACBUFALLOC; + } + PLTFM_MEMSET(mask_map, 0xFF, log_efuse_size);// default: 0xFF + + ret = eeprom_parser(adapter, *bank_efuse_info.phy_map, + mask_map, MAC_AX_EFUSE_PARSER_MASK); + if (ret != 0) { + PLTFM_FREE(mask_map, log_efuse_size); + goto error; + } + + map_pg = info->efuse_map; + efuse_mask = info->efuse_mask; + + PLTFM_MEMCPY(updated_mask, efuse_mask, info->efuse_mask_size); + + for (i = 0; i < info->efuse_map_size; i += 16) { + for (j = 0; j < 16; j += 2) { + map_offset = i + j; + mask_offset = i >> 4; + if (*(u16 *)(map_pg + map_offset) == + *(u16 *)(map + map_offset) && + *(mask_map + map_offset) == 0x00) { + switch (j) { + case 0: + clr_bit = BIT(4); + break; + case 2: + clr_bit = BIT(5); + break; + case 4: + clr_bit = BIT(6); + break; + case 6: + clr_bit = BIT(7); + break; + case 8: + clr_bit = BIT(0); + break; + case 10: + clr_bit = BIT(1); + break; + case 12: + clr_bit = BIT(2); + break; + case 14: + clr_bit = BIT(3); + break; + default: + break; + } + *(updated_mask + mask_offset) &= ~clr_bit; + } + } + } + + PLTFM_FREE(map, log_efuse_size); + PLTFM_FREE(mask_map, log_efuse_size); + return MACSUCCESS; +error: + PLTFM_FREE(map, log_efuse_size); + return ret; +} + +static u32 check_efuse_enough(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + u8 *updated_mask) +{ + u8 pre_word_en; + u32 i; + u16 j; + u32 eeprom_offset; + u32 pg_num = 0; + + for (i = 0; i < info->efuse_map_size; i += 8) { + eeprom_offset = i; + + if ((eeprom_offset & 0xF) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + if (pre_word_en > 0) { // msk ==1 -> write + pg_num += 2; + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) > 0) + pg_num += 2; + } + } + } + + if (*bank_efuse_info.phy_map_size + < (pg_num + *bank_efuse_info.efuse_end)) + return MACEFUSESIZE; + + return MACSUCCESS; +} + +static u32 proc_pg_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset, bool pg_sim) +{ + u8 blk, blk_idx; + u8 hdr; + u8 hdr2 = 0xFF; + u8 i; + u32 efuse_end, ret; + u8 *efuse_map = *bank_efuse_info.phy_map; + bool is_bt = 0; + + if (info->efuse_map_size == adapter->hw_info->bt_log_efuse_size) + is_bt = 1; + + efuse_end = *bank_efuse_info.efuse_end; + + if (is_bt) { + if (eeprom_offset < BT_1B_ENTRY_SIZE) { + blk = (u8)(eeprom_offset >> 3); + hdr = (u8)((blk << 4) + word_en); + } else { + blk = (u8)(eeprom_offset >> 3 >> 3); + blk_idx = (u8)(((eeprom_offset >> 3) & (8 - 1)) << 1); + hdr = (u8)((blk_idx << 4) | 0xF); + hdr2 = (u8)((blk << 4) + word_en); + } + } else { + blk = (u8)(eeprom_offset >> 3); + hdr = ((blk & 0xF0) >> 4) | 0x30; + hdr2 = (u8)(((blk & 0x0F) << 4) + word_en); + } + + if (pg_sim) { //WL + *(efuse_map + efuse_end) = hdr; + *(efuse_map + efuse_end + 1) = hdr2; + + efuse_end += 2; + + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + *(efuse_map + efuse_end) = *(info->efuse_map + + eeprom_offset + (i << 1)); + efuse_end++; + + *(efuse_map + efuse_end) = *(info->efuse_map + + eeprom_offset + (i << 1) + 1); + efuse_end++; + } + } + } else { + ret = write_hw_efuse(adapter, efuse_end, hdr); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return ret; + } + + if (is_bt == 0 || eeprom_offset >= BT_1B_ENTRY_SIZE) { + ret = write_hw_efuse(adapter, efuse_end + 1, hdr2); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write efuse(+1)\n"); + return ret; + } + efuse_end++; + } + + efuse_end++; + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + ret = write_hw_efuse(adapter, efuse_end, + *(info->efuse_map + + eeprom_offset + (i << 1))); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return ret; + } + + ret = write_hw_efuse(adapter, efuse_end + 1, + *(info->efuse_map + + eeprom_offset + + (i << 1) + 1)); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]write efuse+1\n"); + return ret; + } + efuse_end = efuse_end + 2; + } + } + } + *bank_efuse_info.efuse_end = efuse_end; + return MACSUCCESS; +} + +static u32 program_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *updated_mask, + bool pg_sim) +{ + u8 pre_word_en; + u8 word_en; + u32 i; + u32 eeprom_offset, ret; + + enable_efuse_sw_pwr_cut(adapter, 1); + + for (i = 0; i < info->efuse_map_size; i += 8) { + eeprom_offset = i; + + if (((eeprom_offset >> 3) & 1) > 0) { + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + word_en = pre_word_en ^ 0x0F; + } else { + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + word_en = pre_word_en ^ 0x0F; + } + + if (pre_word_en > 0) { + ret = proc_pg_efuse(adapter, info, word_en, pre_word_en, + eeprom_offset, pg_sim); + if (ret != 0) { + PLTFM_MSG_ERR("[ERR]pg efuse"); + return ret; + } + } + } + + disable_efuse_sw_pwr_cut(adapter, 1); + + return MACSUCCESS; +} + +static void mask_eeprom(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info) +{ + u8 pre_word_en; + u8 *updated_mask; + u8 *efuse_map; + u32 i; + u16 j; + u32 offset; + + updated_mask = info->efuse_mask; + efuse_map = info->efuse_map; + + for (i = 0; i < info->efuse_map_size; i += 8) { + offset = i; + + if (((offset >> 3) & 1) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) == 0) { + *(efuse_map + offset + (j << 1)) = 0xFF; + *(efuse_map + offset + (j << 1) + 1) = 0xFF; + } + } + } +} + +static u32 query_status_map(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_feature_id feature_id, + u8 *map, bool is_limit) +{ + struct mac_ax_hw_info *hw_info = adapter->hw_info; + enum mac_ax_intf intf = adapter->hw_info->intf; + u32 map_size = 0; + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + switch (feature_id) { + case MAC_AX_DUMP_PHYSICAL_EFUSE: + map_size = *bank_efuse_info.phy_map_size; + PLTFM_MEMCPY(map, *bank_efuse_info.phy_map, map_size); + break; + case MAC_AX_DUMP_LOGICAL_EFUSE: + if (!is_limit) { + map_size = *bank_efuse_info.log_map_size; + } else {// WL + switch (intf) { + case MAC_AX_INTF_PCIE: + map_size = hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + map_size = hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + map_size = hw_info->limit_efuse_size_sdio; + break; + default: + break; + } + } + PLTFM_MEMCPY(map, *bank_efuse_info.log_map, map_size); + break; + default: + return MACFUNCINPUT; + } + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + + return MACSUCCESS; +} + +static u32 adjust_mask(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info) +{ + u8 *efuse_mask = info->efuse_mask; + u8 *efuse_map = info->efuse_map; + u32 i = 0; + u16 j = 0; + u16 map_offset; + u16 mask_offset; + u8 adj_bit = 0; + + PLTFM_MEMSET(efuse_mask, 0xFF, info->efuse_mask_size); + + for (i = 0; i < info->efuse_map_size; i += 16) { + for (j = 0; j < 16; j += 2) { + map_offset = i + j; + mask_offset = i >> 4; + + if (*(u16 *)(efuse_map + map_offset) == 0xFFFF) { + switch (j) { + case 0: + adj_bit = BIT(4); + break; + case 2: + adj_bit = BIT(5); + break; + case 4: + adj_bit = BIT(6); + break; + case 6: + adj_bit = BIT(7); + break; + case 8: + adj_bit = BIT(0); + break; + case 10: + adj_bit = BIT(1); + break; + case 12: + adj_bit = BIT(2); + break; + case 14: + adj_bit = BIT(3); + break; + } + *(efuse_mask + mask_offset) &= ~adj_bit; + } + } + } + + return MACSUCCESS; +} + +static u32 compare_info_length(struct efuse_info *info, + enum rtw_efuse_info id, u32 length) +{ + u32 idle_len; + + switch (id) { + case EFUSE_INFO_MAC_ADDR: + idle_len = info->len->mac_addr; + break; + case EFUSE_INFO_MAC_PID: + idle_len = info->len->pid; + break; + case EFUSE_INFO_MAC_DID: + idle_len = info->len->did; + break; + case EFUSE_INFO_MAC_VID: + idle_len = info->len->vid; + break; + case EFUSE_INFO_MAC_SVID: + idle_len = info->len->svid; + break; + case EFUSE_INFO_MAC_SMID: + idle_len = info->len->smid; + break; + default: + return MACNOITEM; + } + + if (length != idle_len || idle_len == 0) + return MACLENCMP; + + return MACSUCCESS; +} + +static u32 set_check_sum_val(struct mac_ax_adapter *adapter, + u8 *map, u16 value) +{ + u8 byte1; + u8 byte2; + u8 blk; + u8 blk_idx; + u8 hdr; + u8 hdr2; + u32 end = *bank_efuse_info.efuse_end, ret; + u32 offset = chksum_offset_1; + u8 i = 0; + u8 value8 = (u8)(value & 0xFF); + + enable_efuse_sw_pwr_cut(adapter, 1); + + for (i = 0; i < 2; i++) { + blk = (u8)(offset >> 3); + blk_idx = (u8)((offset & (8 - 1)) >> 1); + + hdr = ((blk & 0xF0) >> 4) | 0x30; + hdr2 = (u8)(((blk & 0x0F) << 4) + ((0x1 << blk_idx) ^ 0x0F)); + + if ((offset & 1) == 0) { + byte1 = value8; + byte2 = *(map + offset + 1); + } else { + byte1 = (u8)(value & 0xFF); + byte2 = value8; + } + + if (*bank_efuse_info.phy_map_size <= 4 + end) + return MACEFUSESIZE; + + ret = write_hw_efuse(adapter, end, hdr); + if (ret != 0) + return ret; + + ret = write_hw_efuse(adapter, end + 1, hdr2); + if (ret != 0) + return ret; + + ret = write_hw_efuse(adapter, end + 2, byte1); + if (ret != 0) + return ret; + + ret = write_hw_efuse(adapter, end + 3, byte2); + if (ret != 0) + return ret; + + offset = chksum_offset_2; + value8 = (u8)((value & 0xFF00) >> 8); + end += 4; + } + + disable_efuse_sw_pwr_cut(adapter, 1); + + return MACSUCCESS; +} + +static void cal_check_sum(struct mac_ax_adapter *adapter, u16 *chksum) +{ + u32 i = 0; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param; + u8 *map = efuse_param->log_efuse_map; + u16 *data; + + data = (u16 *)map; + + *chksum = 0x0000; + for (i = 0; i < hw_info->log_efuse_size >> 2; i++) { + if (i == chksum_offset_1 >> 2) + *chksum ^= 0x0000 ^ *(data + (2 * i + 1)); + else + *chksum ^= *(data + 2 * i) ^ *(data + (2 * i + 1)); + } +} + +static u32 compare_version(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u32 ver_len) +{ + u8 *map = info->efuse_map; + u8 *mask = info->efuse_mask; + u32 map_size = info->efuse_map_size; + u32 i = 0; + + for (i = 0; i < ver_len; i++) { + if (*(map + map_size + i) != *(mask + (map_size >> 4) + i)) + return MACVERERR; + } + return MACSUCCESS; +} + +static void add_dummy_read(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_EFUSE_CTRL_S, + SET_WORD(CHK_OTP_ADDR, B_AX_EF_ADDR) & ~B_AX_EF_RDY); + PLTFM_DELAY_US(DUMMY_READ_DELAY); + MAC_REG_W32(R_AX_EFUSE_CTRL, + SET_WORD(CHK_OTP_ADDR, B_AX_EF_ADDR) & ~B_AX_EF_RDY); + PLTFM_DELAY_US(DUMMY_READ_DELAY); +} + +static void enable_OTP_burst_mode(struct mac_ax_adapter *adapter, + bool enable) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_EFUSE_CTRL_1_V1); + + if (enable) + MAC_REG_W32(R_AX_EFUSE_CTRL_1_V1, val32 | B_AX_EF_BURST); + else + MAC_REG_W32(R_AX_EFUSE_CTRL_1_V1, val32 & ~B_AX_EF_BURST); +} + +static void enable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter, + bool is_write) +{ + u16 val16; + u8 val8; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 chip_id = adapter->hw_info->chip_id; + + if (dv_sel == DDV) { + if (chip_id == MAC_AX_CHIP_ID_8852A && !(is_write)) + return; + + if (is_write) + MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, UNLOCK_CODE); + + val8 = MAC_REG_R8(R_AX_PMC_DBG_CTRL2); + MAC_REG_W8(R_AX_PMC_DBG_CTRL2, val8 | B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, val16 | BIT(B_AX_PWC_EV2EF_SH)); + + PLTFM_DELAY_US(1000); + + val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + val16 | BIT(B_AX_PWC_EV2EF_SH + 1)); + + if (chip_id == MAC_AX_CHIP_ID_8852A) { + return; + } else if (chip_id == MAC_AX_CHIP_ID_8852B) { + val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + val16 & ~(B_AX_ISO_EB2CORE)); + if (is_cv(adapter, CAV)) + enable_OTP_burst_mode(adapter, 1); + } else { + val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + val16 & ~(B_AX_ISO_EB2CORE)); + } + } else { + enable_efuse_pwr_cut_dav(adapter, is_write); + } +} + +static void disable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter, + bool is_write) +{ + u16 value16; + u8 value8; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 chip_id = adapter->hw_info->chip_id; + + if (dv_sel == DDV) { + if (chip_id == MAC_AX_CHIP_ID_8852A) { + if (!(is_write)) + return; + } else if (chip_id == MAC_AX_CHIP_ID_8852B) { + if (is_cv(adapter, CAV)) + enable_OTP_burst_mode(adapter, 0); + value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + value16 | B_AX_ISO_EB2CORE); + } else { + value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + value16 | B_AX_ISO_EB2CORE); + } + + value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + value16 & ~(BIT(B_AX_PWC_EV2EF_SH + 1)));// [15]=0 + + PLTFM_DELAY_US(1000); + + value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL); + MAC_REG_W16(R_AX_SYS_ISO_CTRL, + value16 & ~(BIT(B_AX_PWC_EV2EF_SH)));// [14]=0, + + if (is_write) + MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, 0x00); + + value8 = MAC_REG_R8(R_AX_PMC_DBG_CTRL2); + MAC_REG_W8(R_AX_PMC_DBG_CTRL2, value8 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK); + } else { + disable_efuse_pwr_cut_dav(adapter, is_write); + } +} + +static u32 enable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter, + bool is_write) +{ + u32 ret; + u8 chip_id = adapter->hw_info->chip_id; + + if (!(is_write)) + return MACSUCCESS; + + if (chip_id == MAC_AX_CHIP_ID_8852A) { + return MACSUCCESS; + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, + XTAL_SI_SMALL_PWR_CUT, + XTAL_SI_SMALL_PWR_CUT); + if (ret) + return ret; + + ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, + XTAL_SI_BIG_PWR_CUT, + XTAL_SI_BIG_PWR_CUT); + if (ret) + return ret; + } + + return MACSUCCESS; +} + +static u32 disable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter, + bool is_write) +{ + u32 ret; + u8 chip_id = adapter->hw_info->chip_id; + + if (!(is_write)) + return MACSUCCESS; + + if (chip_id == MAC_AX_CHIP_ID_8852A) { + return MACSUCCESS; + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, 0, + XTAL_SI_BIG_PWR_CUT); + if (ret) + return ret; + + ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, 0, + XTAL_SI_SMALL_PWR_CUT); + if (ret) + return ret; + } + + return MACSUCCESS; +} + +static u32 read_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, u32 size, + u8 *map) +{ + u32 addr; + u8 tmp8; + u32 cnt; + u32 ret; + + ret = enable_efuse_pwr_cut_dav(adapter, 0); + if (ret) + return ret; + + for (addr = offset; addr < offset + size; addr++) { + /* clear ready bit*/ + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK); + if (ret) + return ret; + /* set addr */ + ret = mac_write_xtal_si(adapter, XTAL_SI_LOW_ADDR, + (addr & 0xff) << XTAL_SI_LOW_ADDR_SH, + XTAL_SI_LOW_ADDR_MSK); + if (ret) + return ret; + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, (addr >> 8) + << XTAL_SI_HIGH_ADDR_SH, + XTAL_SI_HIGH_ADDR_MSK + << XTAL_SI_HIGH_ADDR_SH); + if (ret) + return ret; + /* set ctrl mode sel */ + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0, + XTAL_SI_MODE_SEL_MSK + << XTAL_SI_MODE_SEL_SH); + if (ret) + return ret; + + /* polling */ + cnt = EFUSE_WAIT_CNT; + while (--cnt) { + ret = mac_read_xtal_si(adapter, XTAL_SI_CTRL, &tmp8); + if (ret) + return ret; + if (tmp8 & XTAL_SI_RDY) + break; + PLTFM_DELAY_US(1); + } + if (!cnt) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + return MACEFUSEREAD; + } + + ret = mac_read_xtal_si(adapter, XTAL_SI_READ_VAL, &tmp8); + if (ret) + return ret; + *(map + addr - offset) = tmp8; + } + + ret = disable_efuse_pwr_cut_dav(adapter, 0); + if (ret) + return ret; + + return MACSUCCESS; +} + +static u32 write_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, + u8 value) +{ + u32 cnt; + u32 ret; + u8 tmp8; + + PLTFM_MUTEX_LOCK(&efuse_tbl.lock); + *bank_efuse_info.phy_map_valid = 0; + *bank_efuse_info.log_map_valid = 0; + PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock); + + /* clear ready bit*/ + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK); + if (ret) + return ret; + /* set val */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WRITE_VAL, value << + XTAL_SI_WRITE_DATA_SH, XTAL_SI_WRITE_DATA_MSK << + XTAL_SI_WRITE_DATA_SH); + if (ret) + return ret; + /* set addr */ + ret = mac_write_xtal_si(adapter, XTAL_SI_LOW_ADDR, (offset & 0xff) + << XTAL_SI_LOW_ADDR_SH, + XTAL_SI_LOW_ADDR_MSK << XTAL_SI_LOW_ADDR_SH); + if (ret) + return ret; + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, (offset >> 8) + << XTAL_SI_HIGH_ADDR_SH, + XTAL_SI_HIGH_ADDR_MSK << XTAL_SI_HIGH_ADDR_SH); + if (ret) + return ret; + /* set ctrl mode sel */ + ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x2 + << XTAL_SI_MODE_SEL_SH, + XTAL_SI_MODE_SEL_MSK << XTAL_SI_MODE_SEL_SH); + if (ret) + return ret; + + /* polling */ + cnt = EFUSE_WAIT_CNT; + while (--cnt) { + ret = mac_read_xtal_si(adapter, XTAL_SI_CTRL, &tmp8); + if (ret) + return ret; + if (tmp8 & XTAL_SI_RDY) + break; + PLTFM_DELAY_US(1); + } + if (!cnt) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return MACEFUSEREAD; + } + + return MACSUCCESS; +} + +static void switch_dv(struct mac_ax_adapter *adapter, enum rtw_dv_sel sel) +{ + dv_sel = sel; +} + diff --git a/phl/hal_g6/mac/mac_ax/efuse.h b/phl/hal_g6/mac/mac_ax/efuse.h new file mode 100644 index 0000000..1a94ac5 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/efuse.h @@ -0,0 +1,1059 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_EFUSE_H_ +#define _MAC_AX_EFUSE_H_ + +#include "../type.h" +#include "fwcmd.h" + +#define RSVD_EFUSE_SIZE 16 +#define RSVD_CS_EFUSE_SIZE 24 +#define EFUSE_WAIT_CNT 10000 +#define EFUSE_C2HREG_WAIT_CNT 10000 +#define EFUSE_C2HREG_RETRY_WAIT_US 1 +#define EFUSE_FW_DUMP_WAIT_CNT 100000 +#define OTP_PHY_SIZE 0x800 +#define CHK_OTP_ADDR 0x4 +#define CHK_OTP_WAIT_CNT 50000 +#define DUMMY_READ_DELAY 200 + +#define BT_1B_ENTRY_SIZE 0x80 +#define UNLOCK_CODE 0x69 + +#define XTAL_SI_PWR_CUT 0x10 +#define XTAL_SI_SMALL_PWR_CUT BIT(0) +#define XTAL_SI_BIG_PWR_CUT BIT(1) + +#define XTAL_SI_LOW_ADDR 0x62 +#define XTAL_SI_LOW_ADDR_SH 0 +#define XTAL_SI_LOW_ADDR_MSK 0xFF + +#define XTAL_SI_CTRL 0x63 +#define XTAL_SI_MODE_SEL_SH 6 +#define XTAL_SI_MODE_SEL_MSK 0x3 +#define XTAL_SI_RDY BIT(5) +#define XTAL_SI_HIGH_ADDR_SH 0 +#define XTAL_SI_HIGH_ADDR_MSK 0x7 + +#define XTAL_SI_READ_VAL 0x7A +#define XTAL_SI_WRITE_VAL 0x60 +#define XTAL_SI_WRITE_DATA_SH 0 +#define XTAL_SI_WRITE_DATA_MSK 0xFF + +/** + * @struct mac_efuse_tbl + * @brief mac_efuse_tbl + * + * @var mac_efuse_tbl::lock + * Please Place Description here. + */ +struct mac_efuse_tbl { + mac_ax_mutex lock; +}; + +/** + * @struct mac_efuse_hidden_h2creg + * @brief mac_efuse_hidden_h2creg + * + * @var mac_efuse_hidden_h2creg::rsvd0 + * Please Place Description here. + */ +struct mac_efuse_hidden_h2creg { + /* dword0 */ + u32 rsvd0:16; +}; + +/** + * @enum efuse_map_sel + * + * @brief efuse_map_sel + * + * @var efuse_map_sel::EFUSE_MAP_SEL_PHY_WL + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_PHY_BT + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_LOG + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_LOG_BT + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_PHY_OTP + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_LAST + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_MAX + * Please Place Description here. + * @var efuse_map_sel::EFUSE_MAP_SEL_INVALID + * Please Place Description here. + */ +enum efuse_map_sel { + EFUSE_MAP_SEL_PHY_WL, + EFUSE_MAP_SEL_PHY_BT, + EFUSE_MAP_SEL_LOG, + EFUSE_MAP_SEL_LOG_BT, + EFUSE_MAP_SEL_PHY_OTP, + EFUSE_MAP_SEL_PHY_DAV, + EFUSE_MAP_SEL_LOG_DAV, + + /* keep last */ + EFUSE_MAP_SEL_LAST, + EFUSE_MAP_SEL_MAX = EFUSE_MAP_SEL_LAST, + EFUSE_MAP_SEL_INVALID = EFUSE_MAP_SEL_LAST, +}; + +/** + * @struct efuse_info_item + * @brief efuse_info_item + * + * @var efuse_info_item::mac_addr + * MAC Address + * @var efuse_info_item::pid + * Product ID + * @var efuse_info_item::did + * Device ID + * @var efuse_info_item::vid + * Vendor ID + * @var efuse_info_item::svid + * Sybsystem Vendor ID + * @var efuse_info_offset::smid + * Sybsystem Device ID + */ +struct efuse_info_item { + u32 mac_addr; + u32 pid; + u32 did; + u32 vid; + u32 svid; + u32 smid; +}; + +/** + * @struct efuse_info + * @brief efuse_info + * + * @var efuse_info::offset + * Efuse information offset + * @var efuse_info::def_val + * Efuse information default value + * @var efuse_info::len + * Efuse information length + */ +struct efuse_info { + struct efuse_info_item *offset; + struct efuse_info_item *def_val; + struct efuse_info_item *len; +}; + +/** + * @enum mac_checksum_offset + * + * @brief mac_checksum_offset + * + * @var mac_checksum_offset::chksum_offset_1 + * Please Place Description here. + * @var mac_checksum_offset::chksum_offset_2 + * Please Place Description here. + */ +enum mac_checksum_offset { + chksum_offset_1 = 0x1AC, + chksum_offset_2 = 0x1AD, +}; + +/** + * @struct mac_bank_efuse_info + * @brief mac_bank_efuse_info + * + * @var mac_bank_efuse_info::phy_map + * Please Place Description here. + * @var mac_bank_efuse_info::log_map + * Please Place Description here. + * @var mac_bank_efuse_info::phy_map_valid + * Please Place Description here. + * @var mac_bank_efuse_info::log_map_valid + * Please Place Description here. + * @var mac_bank_efuse_info::efuse_end + * Please Place Description here. + * @var mac_bank_efuse_info::phy_map_size + * Please Place Description here. + * @var mac_bank_efuse_info::log_map_size + * Please Place Description here. + */ +struct mac_bank_efuse_info { + /* efuse_param */ + u8 **phy_map; + u8 **log_map; + u8 *phy_map_valid; + u8 *log_map_valid; + u32 *efuse_end; + /* hw_info */ + u32 *phy_map_size; + u32 *log_map_size; + u32 *efuse_start; +}; + +/** + * @enum mac_defeature_offset + * + * @brief mac_defeature_offset + * + * @var mac_defeature_offset::rx_spatial_stream + * Please Place Description here. + * @var mac_defeature_offset::rx_spatial_stream_sh + * Please Place Description here. + * @var mac_defeature_offset::rx_spatial_stream_msk + * Please Place Description here. + * @var mac_defeature_offset::bandwidth + * Please Place Description here. + * @var mac_defeature_offset::bandwidth_sh + * Please Place Description here. + * @var mac_defeature_offset::bandwidth_msk + * Please Place Description here. + * @var mac_defeature_offset::tx_spatial_stream + * Please Place Description here. + * @var mac_defeature_offset::tx_spatial_stream_sh + * Please Place Description here. + * @var mac_defeature_offset::tx_spatial_stream_msk + * Please Place Description here. + * @var mac_defeature_offset::protocol_80211 + * Please Place Description here. + * @var mac_defeature_offset::protocol_80211_sh + * Please Place Description here. + * @var mac_defeature_offset::protocol_80211_msk + * Please Place Description here. + * @var mac_defeature_offset::NIC_router + * Please Place Description here. + * @var mac_defeature_offset::NIC_router_sh + * Please Place Description here. + * @var mac_defeature_offset::NIC_router_msk + * Please Place Description here. + */ +enum mac_defeature_offset { + rx_spatial_stream = 0xB, + rx_spatial_stream_sh = 0x4, + rx_spatial_stream_msk = 0x7, + bandwidth = 0xD, + bandwidth_sh = 0x0, + bandwidth_msk = 0x7, + tx_spatial_stream = 0xD, + tx_spatial_stream_sh = 0x4, + tx_spatial_stream_msk = 0x7, + protocol_80211 = 0x11, + protocol_80211_sh = 0x2, + protocol_80211_msk = 0x3, + NIC_router = 0x11, + NIC_router_sh = 0x6, + NIC_router_msk = 0x3, +}; + +/** + * @enum mac_cntlr_mode_sel + * + * @brief mac_cntlr_mode_sel + * + * @var mac_cntlr_mode_sel::MODE_READ + * Please Place Description here. + * @var mac_cntlr_mode_sel::MODE_AUTOLOAD_EN + * Please Place Description here. + * @var mac_cntlr_mode_sel::MODE_WRITE + * Please Place Description here. + * @var mac_cntlr_mode_sel::MODE_CMP + * Please Place Description here. + */ +enum mac_cntlr_mode_sel { + MODE_READ, + MODE_AUTOLOAD_EN, + MODE_WRITE, + MODE_CMP, +}; + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_efuse_map_wl + * + * @param *adapter + * @param cfg + * @param *efuse_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_efuse_map_wl_plus(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_efuse_map_wl + * + * @param *adapter + * @param cfg + * @param *efuse_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_efuse_map_wl(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_efuse_map_bt + * + * @param *adapter + * @param cfg + * @param *efuse_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_efuse_map_bt(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_write_efuse + * + * @param *adapter + * @param addr + * @param val + * @param bank + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val, + enum mac_ax_efuse_bank bank); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_write_efuse + * + * @param *adapter + * @param addr + * @param val + * @param bank + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val, + enum mac_ax_efuse_bank bank); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_efuse_plus + * + * @param *adapter + * @param addr + * @param size + * @param *val + * @param bank + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val, enum mac_ax_efuse_bank bank); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_efuse + * + * @param *adapter + * @param addr + * @param size + * @param *val + * @param bank + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, u8 *val, + enum mac_ax_efuse_bank bank); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_get_efuse_avl_size + * + * @param *adapter + * @param *size + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_efuse_avl_size(struct mac_ax_adapter *adapter, u32 *size); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_get_efuse_avl_size_bt + * + * @param *adapter + * @param *size + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_efuse_avl_size_bt(struct mac_ax_adapter *adapter, u32 *size); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_log_efuse + * + * @param *adapter + * @param parser_cfg + * @param cfg + * @param *efuse_map + * @param is_limit + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_log_efuse_plus(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map, bool is_limit); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_log_efuse + * + * @param *adapter + * @param parser_cfg + * @param cfg + * @param *efuse_map + * @param is_limit + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_log_efuse(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map, bool is_limit); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_log_efuse_plus + * + * @param *adapter + * @param addr + * @param size + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_log_efuse + * + * @param *adapter + * @param addr + * @param size + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_write_log_efuse_plus + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_write_log_efuse + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_dump_log_efuse_bt + * + * @param *adapter + * @param parser_cfg + * @param cfg + * @param *efuse_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_log_efuse_bt(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_log_efuse_bt + * + * @param *adapter + * @param addr + * @param size + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_write_log_efuse_bt + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u8 val); + +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_efuse_by_map_plus + * + * @param *adapter + * @param *info + * @param cfg + * @param part + * @param is_limit + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_efuse_by_map_plus(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg, + bool part, bool is_limit); + +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_efuse_by_map + * + * @param *adapter + * @param *info + * @param cfg + * @param part + * @param is_limit + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_efuse_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg, bool part, + bool is_limit); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_efuse_by_map_bt + * + * @param *adapter + * @param *info + * @param cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_efuse_by_map_bt(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_mask_log_efuse + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mask_log_efuse(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_sec_data_by_map + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_sec_data_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_cmp_sec_data_by_map + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cmp_sec_data_by_map(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_get_efuse_info + * + * @param *adapter + * @param *efuse_map + * @param id + * @param *value + * @param length + * @param *autoload_status + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 *autoload_status); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_set_efuse_info + * + * @param *adapter + * @param *efuse_map + * @param id + * @param *value + * @param length + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_read_hidden_rpt + * + * @param *adapter + * @param *rpt + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_hidden_rpt(struct mac_ax_adapter *adapter, + struct mac_defeature_value *rpt); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_check_efuse_autoload + * + * @param *adapter + * @param *autoload_status + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_efuse_autoload(struct mac_ax_adapter *adapter, + u8 *autoload_status); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_simulator_plus + * + * @param *adapter + * @param *info + * @param *phy_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_simulator_plus(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *phy_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_pg_simulator + * + * @param *adapter + * @param *info + * @param *phy_map + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pg_simulator(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *phy_map); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_checksum_update + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_checksum_update(struct mac_ax_adapter *adapter); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_checksum_rpt + * + * @param *adapter + * @param *chksum + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_checksum_rpt(struct mac_ax_adapter *adapter, u16 *chksum); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_check_OTP + * + * @param *adapter + * @param *is_start + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_OTP(struct mac_ax_adapter *adapter, u8 is_start); + +/** + * @brief mac_disable_rf + * + * @param *adapter + * @param *func + * @param *type + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_disable_rf(struct mac_ax_adapter *adapter, + enum mac_ax_disable_rf_func func, enum mac_ax_net_type type); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_set_efuse_ctrl + * + * @param *adapter + * @param is_secure + * @return Please Place Description here. + * @retval void + */ +void mac_set_efuse_ctrl(struct mac_ax_adapter *adapter, u8 is_secure); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief mac_otp_test + * + * @param *adapter + * @param is_OTP_test + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_otp_test(struct mac_ax_adapter *adapter, bool is_OTP_test); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief cfg_efuse_auto_ck + * + * @param *adapter + * @param enable + * @return Please Place Description here. + * @retval void + */ +void cfg_efuse_auto_ck(struct mac_ax_adapter *adapter, u8 enable); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief efuse_tbl_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 efuse_tbl_init(struct mac_ax_adapter *adapter); +/** + * @} + */ + +/** + * @addtogroup Efuse + * @{ + */ + +/** + * @brief efuse_tbl_exit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 efuse_tbl_exit(struct mac_ax_adapter *adapter); +/** + * @} + */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/flash.c b/phl/hal_g6/mac/mac_ax/flash.c new file mode 100644 index 0000000..1eb0f49 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/flash.c @@ -0,0 +1,944 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "flash.h" +#include "../mac_ax/fwcmd.h" + +#if MAC_AX_FW_REG_OFLD +u32 mac_flash_erase(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0; + u32 data[2]; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erase_done = 0; + adapter->flash_info.erasing = 1; + adapter->flash_info.erase_addr = addr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACNPTR; // Maybe set a timeout counter + } + pkt_len = LEN_FLASH_H2C_HDR; + buf = h2cb_put(h2cb, pkt_len); + if (!buf) { + ret = MACNOBUF; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + data[0] = cpu_to_le32(addr); + data[1] = cpu_to_le32(length); + PLTFM_MEMCPY(buf, (u8 *)data, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_ERASE,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (adapter->flash_info.erase_done == 1) { + adapter->flash_info.erase_done = 0; + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + //Sleep(50); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} + +u32 mac_flash_read(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0; + u32 data[2]; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + //PLTFM_MSG_TRACE("testdata = 0x%llx\n", (u64)buffer); + if (length > FLASH_H2C_SIZE) + return MACFLASHFAIL; + + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + if ((addr % 4) || (length % 4)) { + PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n" + , addr, length); + return MACFLASHFAIL; + } + // mutex + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.read_done = 0; + adapter->flash_info.reading = 1; + adapter->flash_info.buf_addr = buffer; + adapter->flash_info.read_addr = addr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; // Maybe set a timeout counter + pkt_len = LEN_FLASH_H2C_HDR; + buf = h2cb_put(h2cb, pkt_len); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + data[0] = cpu_to_le32(addr); + data[1] = cpu_to_le32(length); + PLTFM_MEMCPY(buf, (u8 *)data, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_READ,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + //PLTFM_MSG_TRACE("polling enter critical\n"); + if (adapter->flash_info.read_done == 1) { + //PLTFM_MSG_TRACE("read DONE\n"); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + //PLTFM_MSG_TRACE("polling exit critical\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + //Sleep(1); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + // end mutex + //adapter->flash_info.read_done == 0; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} + +u32 mac_flash_write(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, residue_len, pkt_len, local_timeout = 5000, no_timeout = 0, i; + u32 data[2]; + u32 waddr, wlength; + u32 *pbuf; + u32 *psource_data; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + + residue_len = length; + waddr = addr; + wlength = length; + if ((addr % 4) || (length % 4)) { + PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n" + , addr, length); + return MACFLASHFAIL; + } + while (residue_len) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.write_done = 0; + adapter->flash_info.writing = 1; + adapter->flash_info.write_addr = waddr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + if (residue_len >= FLASH_H2C_SIZE) + pkt_len = FLASH_H2C_SIZE; + else + pkt_len = residue_len; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACNPTR; // Maybe set a timeout counter + } + + buf = h2cb_put(h2cb, pkt_len + LEN_FLASH_H2C_HDR); + if (!buf) { + ret = MACNOBUF; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + data[0] = cpu_to_le32(waddr); + data[1] = cpu_to_le32(pkt_len); + PLTFM_MEMCPY(buf, (u8 *)data, LEN_FLASH_H2C_HDR); + buf += LEN_FLASH_H2C_HDR; + //copy data + pbuf = (u32 *)buf; + psource_data = (u32 *)buffer; + for (i = 0; i < (pkt_len / sizeof(u32)); i++) { + *pbuf = cpu_to_le32(*psource_data); + pbuf++; + psource_data++; + } + //PLTFM_MEMCPY(buf, buffer, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_WRITE,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + PLTFM_MSG_ERR("Write H2C, addr = 0x%x, length = %d\n", waddr, pkt_len); + + // delay for flash write + //Sleep(1000); + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (adapter->flash_info.write_done == 1) { + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + adapter->flash_info.write_done = 0; + PLTFM_MSG_TRACE("write DONE\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + //Sleep(1); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MSG_TRACE("write timeout\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + residue_len -= pkt_len; + buffer += pkt_len; + waddr += pkt_len; + } + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} + +#else +u32 mac_flash_erase(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0; + u32 data[2]; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erase_done = 0; + adapter->flash_info.erasing = 1; + adapter->flash_info.erase_addr = addr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACNPTR; // Maybe set a timeout counter + } + pkt_len = LEN_FLASH_H2C_HDR; + buf = h2cb_put(h2cb, pkt_len); + if (!buf) { + ret = MACNOBUF; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + data[0] = cpu_to_le32(addr); + data[1] = cpu_to_le32(length); + PLTFM_MEMCPY(buf, (u8 *)data, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_ERASE,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (adapter->flash_info.erase_done == 1) { + adapter->flash_info.erase_done = 0; + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + //Sleep(50); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} + +u32 mac_flash_read(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0; + u32 data[2]; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + //PLTFM_MSG_TRACE("testdata = 0x%llx\n", (u64)buffer); + if (length > FLASH_H2C_SIZE) + return MACFLASHFAIL; + + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + if ((addr % 4) || (length % 4)) { + PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n" + , addr, length); + return MACFLASHFAIL; + } + // mutex + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.read_done = 0; + adapter->flash_info.reading = 1; + adapter->flash_info.buf_addr = buffer; + adapter->flash_info.read_addr = addr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; // Maybe set a timeout counter + pkt_len = LEN_FLASH_H2C_HDR; + buf = h2cb_put(h2cb, pkt_len); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + data[0] = cpu_to_le32(addr); + data[1] = cpu_to_le32(length); + PLTFM_MEMCPY(buf, (u8 *)data, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_READ,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + //PLTFM_MSG_TRACE("polling enter critical\n"); + if (adapter->flash_info.read_done == 1) { + //PLTFM_MSG_TRACE("read DONE\n"); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + //PLTFM_MSG_TRACE("polling exit critical\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + //Sleep(1); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + adapter->flash_info.read_done = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + // end mutex + //adapter->flash_info.read_done == 0; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.reading = 0; + adapter->flash_info.buf_addr = NULL; + adapter->flash_info.read_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} + +u32 mac_flash_write(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout) +{ + u8 *buf; + u32 ret = 0, residue_len, pkt_len, local_timeout = 5000, no_timeout = 0, i; + u32 data[2]; + u32 waddr, wlength; + u32 *pbuf; + u32 *psource_data; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + if (timeout == 0) + no_timeout = 1; + else + local_timeout = timeout; + + residue_len = length; + waddr = addr; + wlength = length; + if ((addr % 4) || (length % 4)) { + PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n" + , addr, length); + return MACFLASHFAIL; + } + while (residue_len) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.write_done = 0; + adapter->flash_info.writing = 1; + adapter->flash_info.write_addr = waddr; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + if (residue_len >= FLASH_H2C_SIZE) + pkt_len = FLASH_H2C_SIZE; + else + pkt_len = residue_len; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACNPTR; // Maybe set a timeout counter + } + + buf = h2cb_put(h2cb, pkt_len + LEN_FLASH_H2C_HDR); + if (!buf) { + ret = MACNOBUF; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + data[0] = cpu_to_le32(waddr); + data[1] = cpu_to_le32(pkt_len); + PLTFM_MEMCPY(buf, (u8 *)data, LEN_FLASH_H2C_HDR); + buf += LEN_FLASH_H2C_HDR; + //copy data + pbuf = (u32 *)buf; + psource_data = (u32 *)buffer; + for (i = 0; i < (pkt_len / sizeof(u32)); i++) { + *pbuf = cpu_to_le32(*psource_data); + pbuf++; + psource_data++; + } + //PLTFM_MEMCPY(buf, buffer, pkt_len); + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FLASH, + FWCMD_H2C_FUNC_PLAT_FLASH_WRITE,/*platform auto test*/ + 0, + 0); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret); + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + h2cb_free(adapter, h2cb); + h2cb = NULL; + PLTFM_MSG_ERR("Write H2C, addr = 0x%x, length = %d\n", waddr, pkt_len); + + // delay for flash write + //Sleep(1000); + while (1) { + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (adapter->flash_info.write_done == 1) { + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + adapter->flash_info.write_done = 0; + PLTFM_MSG_TRACE("write DONE\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + break; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + //Sleep(1); + PLTFM_DELAY_MS(1); + if (no_timeout == 0) { + local_timeout--; + if (local_timeout == 0) { + ret = MACFLASHFAIL; + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MSG_TRACE("write timeout\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + goto fail; + } + } + } + residue_len -= pkt_len; + buffer += pkt_len; + waddr += pkt_len; + } + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + adapter->flash_info.writing = 0; + adapter->flash_info.write_addr = 0; + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + return MACSUCCESS; +fail: + if (h2cb) + h2cb_free(adapter, h2cb); + adapter->fw_info.h2c_seq--; + + return ret; +} +#endif + +u32 c2h_sys_flash_pkt(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 hdr0, i; + u32 func, length, addr; + u32 *pbuf; + u32 *psource_data; + + PLTFM_MSG_TRACE("%s\n", __func__); + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + //set info + info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT); + info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS); + info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC); + //info->done_ack = 0; + //info->rec_ack = 0; + info->content = buf + FWCMD_HDR_LEN; + //info->h2c_return = info->c2h_data[1]; + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + if (func == FWCMD_H2C_FUNC_PLAT_FLASH_READ) { + addr = *((u32 *)info->content); + addr = le32_to_cpu(addr); + length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR)); + length = le32_to_cpu(length); + PLTFM_MSG_TRACE("addr = 0x%x, length = 0x%x\n", addr, length); + PLTFM_MSG_TRACE("adapter->flash_info.read_addr = 0x%x\n", + adapter->flash_info.read_addr); + //PLTFM_MSG_TRACE("adapter->flash_info.buf_addr = 0x%llx\n", + //(u64)adapter->flash_info.buf_addr); + + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (addr == adapter->flash_info.read_addr && adapter->flash_info.reading == 1) { + // lost data if timeout happened + //PLTFM_MSG_TRACE("ready to read\n"); + if (adapter->flash_info.buf_addr && length <= MAX_READ_SIZE) { + PLTFM_MSG_TRACE("memcpy to buf\n"); + //PLTFM_MEMCPY(adapter->flash_info.buf_addr, + // info->content + LEN_FLASH_C2H_HDR, length); + pbuf = (u32 *)adapter->flash_info.buf_addr; + psource_data = (u32 *)(info->content + LEN_FLASH_C2H_HDR); + for (i = 0; i < length / sizeof(u32); i++) { + *pbuf = le32_to_cpu(*psource_data); + pbuf++; + psource_data++; + } + //PLTFM_MSG_TRACE("memcpy to buf end\n"); + } + } + //PLTFM_MSG_TRACE("set reading = 0\n"); + adapter->flash_info.reading = 0; + adapter->flash_info.read_done = 1; + //PLTFM_MSG_TRACE("set reading = 0 end\n"); + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + //PLTFM_MSG_TRACE("exit critical\n"); + } else if (func == FWCMD_H2C_FUNC_PLAT_FLASH_WRITE) { + addr = *((u32 *)info->content); + addr = le32_to_cpu(addr); + length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR)); + length = le32_to_cpu(length); + PLTFM_MSG_TRACE("write addr = 0x%x\n", *((u32 *)info->content)); + PLTFM_MSG_TRACE("adapter->flash_info.write_addr = 0x%x\n", + adapter->flash_info.write_addr); + PLTFM_MSG_TRACE("write length = 0x%x\n", length); + + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (addr == adapter->flash_info.write_addr && adapter->flash_info.writing == 1) { + adapter->flash_info.writing = 0; + adapter->flash_info.write_done = 1; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + } else if (func == FWCMD_H2C_FUNC_PLAT_FLASH_ERASE) { + addr = *((u32 *)info->content); + addr = le32_to_cpu(addr); + length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR)); + length = le32_to_cpu(length); + PLTFM_MSG_TRACE("erase addr = 0x%x\n", *((u32 *)info->content)); + PLTFM_MSG_TRACE("adapter->flash_info.erase_addr = 0x%x\n", + adapter->flash_info.erase_addr); + PLTFM_MSG_TRACE("erase length = 0x%x\n", length); + + PLTFM_MUTEX_LOCK(&adapter->flash_info.lock); + if (addr == adapter->flash_info.erase_addr && adapter->flash_info.erasing == 1) { + adapter->flash_info.erasing = 0; + adapter->flash_info.erase_done = 1; + } + PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock); + } + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/flash.h b/phl/hal_g6/mac/mac_ax/flash.h new file mode 100644 index 0000000..a94c0e2 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/flash.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FLASH_H_ +#define _MAC_AX_FLASH_H_ + +#include "../type.h" +#include "../mac_def.h" +#include "../mac_ax.h" +#include "fwcmd.h" +#include "trx_desc.h" +#include "trxcfg.h" +#include "dle.h" + +#define MAX_LENGTH_ENUM 7 +#define FLASH_H2C_SIZE 1984 +#define LEN_FLASH_C2H_HDR_ADDR 4 +#define LEN_FLASH_C2H_HDR_LENGTH 4 +#define LEN_FLASH_H2C_HDR 8 +#define LEN_FLASH_C2H_HDR 8 +#define MAX_READ_SIZE 1984 + +u32 mac_flash_erase(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u32 timeout); +u32 mac_flash_read(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout); +u32 mac_flash_write(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout); +u32 c2h_sys_flash_pkt(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/fwcmd.c b/phl/hal_g6/mac/mac_ax/fwcmd.c new file mode 100644 index 0000000..c3bdf3d --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwcmd.c @@ -0,0 +1,3275 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "fwcmd.h" +#include "mcc.h" + +#if MAC_AX_FEATURE_HV +#include "../hv_ax/dbgpkg_hv.h" +#endif + +/* 8852A/8852B: the format of H2C/DLFW descriptor: WD Body + * 8852C: the format of H2C/DLFW descriptor: RX Descriptor + * WD body max len: 24 bytes + * RX descriptor max len: 32 bytes + * We use the max RX descriptor size as the header size + * WD_BODY_LEN_V1 = RX descriptor max len = 32 bytes + */ + +#define H2CB_CMD_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN_V1) +#define H2CB_CMD_SIZE (H2C_CMD_LEN - FWCMD_HDR_LEN) +#define H2CB_CMD_QLEN 8 + +#define H2CB_DATA_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN_V1) +#define H2CB_DATA_SIZE (H2C_DATA_LEN - FWCMD_HDR_LEN) +#define H2CB_DATA_QLEN 4 + +#define H2CB_LONG_DATA_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN) +#define H2CB_LONG_DATA_SIZE (H2C_LONG_DATA_LEN - FWCMD_HDR_LEN) +#define H2CB_LONG_DATA_QLEN 1 + +#define FWCMD_WQ_MAX_JOB_NUM 5 + +#define FWCMD_LMT 12 + +#define MAC_AX_H2C_LMT_EN 0 + +#define FWCMD_H2CREG_BYTE0_SH 0 +#define FWCMD_H2CREG_BYTE0_MSK 0xFF +#define FWCMD_H2CREG_BYTE1_SH 8 +#define FWCMD_H2CREG_BYTE1_MSK 0xFF +#define FWCMD_H2CREG_BYTE2_SH 16 +#define FWCMD_H2CREG_BYTE2_MSK 0xFF +#define FWCMD_H2CREG_BYTE3_SH 24 +#define FWCMD_H2CREG_BYTE3_MSK 0xFF + +#define BCN_GRPIE_OFST_EN BIT(7) + +static struct h2c_buf_head h2cb_head[H2CB_CLASS_MAX]; +static struct fwcmd_wkb_head fwcmd_wq_head; + +struct fwcmd_outsrc_info { +#define MAX_OUTSRC_LEN 60 //need to extend if needed + u32 dword0[MAX_OUTSRC_LEN]; +}; + +struct c2h_event_id_proc { + u8 cat; + u8 cls; + u8 func; + u32 (*hdl)(struct mac_ax_adapter *adapter, struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, u8 *c2h_info); +}; + +static inline u32 h2cb_queue_len(struct h2c_buf_head *list) +{ + return list->qlen; +} + +static inline void __h2cb_queue_head_init(struct h2c_buf_head *list) +{ + list->prev = (struct h2c_buf *)list; + list->next = (struct h2c_buf *)list; + list->qlen = 0; + list->suspend = 0; +} + +static inline void h2cb_queue_head_init(struct mac_ax_adapter *adapter, + struct h2c_buf_head *list) +{ + PLTFM_MUTEX_INIT(&list->lock); + __h2cb_queue_head_init(list); +} + +static inline void __h2cb_insert(struct h2c_buf *new_h2cb, struct h2c_buf *prev, + struct h2c_buf *next, + struct h2c_buf_head *list) +{ + new_h2cb->next = next; + new_h2cb->prev = prev; + next->prev = new_h2cb; + prev->next = new_h2cb; + list->qlen++; +} + +static inline void __h2cb_queue_before(struct h2c_buf_head *list, + struct h2c_buf *next, + struct h2c_buf *new_h2cb) +{ + __h2cb_insert(new_h2cb, next->prev, next, list); +} + +static inline void __h2cb_queue_tail(struct h2c_buf_head *list, + struct h2c_buf *new_h2cb) +{ + __h2cb_queue_before(list, (struct h2c_buf *)list, new_h2cb); +} + +static inline void __h2cb_unlink(struct h2c_buf *h2cb, + struct h2c_buf_head *list) +{ + struct h2c_buf *next, *prev; + + list->qlen--; + next = h2cb->next; + prev = h2cb->prev; + h2cb->prev = NULL; + h2cb->next = NULL; + next->prev = prev; + prev->next = next; +} + +static inline struct h2c_buf *h2cb_peek(struct h2c_buf_head *list) +{ + struct h2c_buf *h2cb = list->next; + + if (h2cb == (struct h2c_buf *)list) + h2cb = NULL; + return h2cb; +} + +#if MAC_AX_PHL_H2C +u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb) +#else +u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb) +#endif +{ + struct mac_ax_h2c_agg_node *h2c_agg_node = NULL; + u32 ret = MACSUCCESS; + + PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock); + + if (!adapter->h2c_agg_info.h2c_agg_en) { + /* return fall and send the H2C pkt by the orginal function*/ + ret = MACNOITEM; + goto fail; + } + + h2c_agg_node = (struct mac_ax_h2c_agg_node *) + PLTFM_MALLOC(sizeof(struct mac_ax_h2c_agg_node)); + if (!h2c_agg_node) { + /* return fall and send the H2C pkt by the orginal function*/ + ret = MACBUFALLOC; + goto fail; + } + + PLTFM_MEMSET(h2c_agg_node, 0, sizeof(struct mac_ax_h2c_agg_node)); + h2c_agg_node->h2c_pkt = (u8 *)h2cb; + h2c_agg_node->next = NULL; + adapter->h2c_agg_info.h2c_agg_pkt_num++; + + if (!adapter->h2c_agg_info.h2c_agg_queue_head) { + adapter->h2c_agg_info.h2c_agg_queue_head = h2c_agg_node; + adapter->h2c_agg_info.h2c_agg_queue_last = h2c_agg_node; + } else { + adapter->h2c_agg_info.h2c_agg_queue_last->next = h2c_agg_node; + adapter->h2c_agg_info.h2c_agg_queue_last = h2c_agg_node; + } + +fail: + PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock); + return ret; +} + +#if MAC_AX_PHL_H2C +static inline u8 *h2cb_tail_pointer(const struct rtw_h2c_pkt *h2cb) +{ + return h2cb->vir_tail; +} +#else +static inline u8 *h2cb_tail_pointer(const struct h2c_buf *h2cb) +{ + return h2cb->tail; +} +#endif + +static inline struct h2c_buf *h2cb_dequeue(struct h2c_buf_head *list) +{ + struct h2c_buf *h2cb = h2cb_peek(list); + + if (h2cb) + __h2cb_unlink(h2cb, list); + return h2cb; +} + +static u8 *__h2cb_alloc_buf_pool(struct mac_ax_adapter *adapter, + struct h2c_buf_head *list, u32 size, int num) +{ + u32 block_size = (size * num); + u8 *ptr; + + ptr = (u8 *)PLTFM_MALLOC(block_size); + list->pool = ptr; + list->size = block_size; + + return ptr; +} + +static struct h2c_buf *__h2cb_alloc(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class, + u32 hdr_size, u8 *buf_ptr, int buf_size) +{ + struct h2c_buf *h2cb; + + //_ASSERT_(!buf_ptr); + + h2cb = (struct h2c_buf *)PLTFM_MALLOC(sizeof(struct h2c_buf)); + if (!h2cb) + return NULL; + PLTFM_MEMSET(h2cb, 0, sizeof(struct h2c_buf)); + + h2cb->_class_ = buf_class; + h2cb->id = 0; + h2cb->master = 0; + h2cb->len = 0; + h2cb->head = buf_ptr; + h2cb->end = h2cb->head + buf_size; + h2cb->data = h2cb->head + hdr_size; + h2cb->tail = h2cb->data; + h2cb->hdr_len = hdr_size; + h2cb->flags |= H2CB_FLAGS_FREED; + + return h2cb; +} + +static u32 __h2cb_free(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class) +{ + struct h2c_buf_head *list_head = &h2cb_head[buf_class]; + struct h2c_buf *h2cb; + + if (buf_class >= H2CB_CLASS_LAST) + return MACNOITEM; + + if (!list_head->pool) + return MACNPTR; + + if (!h2cb_queue_len(list_head)) + return MACSUCCESS; + + while ((h2cb = h2cb_dequeue(list_head))) + PLTFM_FREE(h2cb, sizeof(struct h2c_buf)); + + PLTFM_FREE(list_head->pool, list_head->size); + list_head->pool = NULL; + list_head->size = 0; + PLTFM_MUTEX_DEINIT(&list_head->lock); + + return MACSUCCESS; +} + +static u32 __h2cb_init(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class, u32 num, u32 buf_size, + u32 hdr_size, u32 tailer_size) +{ + u32 i; + u8 *ptr; + struct h2c_buf_head *list_head = &h2cb_head[buf_class]; + u32 real_size = buf_size + hdr_size + tailer_size; + struct h2c_buf *h2cb; + + if (buf_class >= H2CB_CLASS_LAST) + return MACNOITEM; + + if (h2cb_queue_len(list_head)) + return MACBUFSZ; + + h2cb_queue_head_init(adapter, list_head); + + ptr = __h2cb_alloc_buf_pool(adapter, list_head, real_size, num); + if (!ptr) + return MACNPTR; + + for (i = 0; i < num; i++) { + h2cb = __h2cb_alloc(adapter, + buf_class, hdr_size, ptr, real_size); + if (!h2cb) + goto h2cb_fail; + __h2cb_queue_tail(list_head, h2cb); + ptr += real_size; + } + + return MACSUCCESS; +h2cb_fail: + __h2cb_free(adapter, buf_class); + + return MACBUFALLOC; +} + +static inline u32 fwcmd_wkb_queue_len(struct fwcmd_wkb_head *list) +{ + return list->qlen; +}; + +static inline void __fwcmd_wkb_queue_head_init(struct fwcmd_wkb_head *list) +{ + list->prev = (struct h2c_buf *)list; + list->next = (struct h2c_buf *)list; + list->qlen = 0; +}; + +static inline void fwcmd_wkb_queue_head_init(struct mac_ax_adapter *adapter, + struct fwcmd_wkb_head *list) +{ + PLTFM_MUTEX_INIT(&list->lock); + __fwcmd_wkb_queue_head_init(list); +} + +static u32 __fwcmd_wkb_init(struct mac_ax_adapter *adapter) +{ + struct fwcmd_wkb_head *list_head = &fwcmd_wq_head; + + if (fwcmd_wkb_queue_len(list_head)) + return MACBUFSZ; + + fwcmd_wkb_queue_head_init(adapter, list_head); + + return MACSUCCESS; +} + +u32 h2cb_init(struct mac_ax_adapter *adapter) +{ + u32 ret; + + ret = __h2cb_init(adapter, H2CB_CLASS_CMD, H2CB_CMD_QLEN, + H2CB_CMD_SIZE, H2CB_CMD_HDR_SIZE, 0); + if (ret) + return ret; + + ret = __h2cb_init(adapter, H2CB_CLASS_DATA, H2CB_DATA_QLEN, + H2CB_DATA_SIZE, H2CB_DATA_HDR_SIZE, 0); + if (ret) + return ret; + + ret = __h2cb_init(adapter, H2CB_CLASS_LONG_DATA, H2CB_LONG_DATA_QLEN, + H2CB_LONG_DATA_SIZE, H2CB_LONG_DATA_HDR_SIZE, 0); + if (ret) + return ret; + + ret = __fwcmd_wkb_init(adapter); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 h2cb_exit(struct mac_ax_adapter *adapter) +{ + struct fwcmd_wkb_head *list_head = &fwcmd_wq_head; + + if (fwcmd_wkb_queue_len(list_head)) + return MACBUFSZ; + + __h2cb_free(adapter, H2CB_CLASS_CMD); + __h2cb_free(adapter, H2CB_CLASS_DATA); + __h2cb_free(adapter, H2CB_CLASS_LONG_DATA); + + return MACSUCCESS; +} + +u32 h2c_end_flow(struct mac_ax_adapter *adapter) +{ + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + + PLTFM_MUTEX_LOCK(&fwinfo->seq_lock); + fwinfo->h2c_seq++; + PLTFM_MUTEX_UNLOCK(&fwinfo->seq_lock); + + return MACSUCCESS; +} + +#if MAC_AX_PHL_H2C +struct rtw_h2c_pkt *h2cb_alloc(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class) +{ + struct rtw_h2c_pkt *h2cb; +#if MAC_AX_H2C_LMT_EN + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + u8 diff; + u8 cnt = 100; +#endif + + if (buf_class >= H2CB_CLASS_LAST) { + PLTFM_MSG_ERR("[ERR]unknown class\n"); + return NULL; + } + +#if MAC_AX_H2C_LMT_EN + while (--cnt) { + if (fwinfo->h2c_seq >= fwinfo->rec_seq) + diff = fwinfo->h2c_seq - fwinfo->rec_seq; + else + diff = (255 - fwinfo->rec_seq) + fwinfo->h2c_seq; + + if (diff < FWCMD_LMT) + break; + PLTFM_DELAY_US(100); + } + + if (diff >= FWCMD_LMT) { + PLTFM_MSG_ERR("The number of H2C has reached the limitation\n"); + PLTFM_MSG_ERR("curr: %d, rec: %d\n", + fwinfo->h2c_seq, fwinfo->rec_seq); + return NULL; + } +#endif + + h2cb = PLTFM_QUERY_H2C(buf_class); + + return h2cb; +} + +void h2cb_free(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb) +{ +} + +u8 *h2cb_push(struct rtw_h2c_pkt *h2cb, u32 len) +{ + h2cb->vir_data -= len; + h2cb->data_len += len; + + if (h2cb->vir_data < h2cb->vir_head) + return NULL; + + return h2cb->vir_data; +} + +u8 *h2cb_pull(struct rtw_h2c_pkt *h2cb, u32 len) +{ + h2cb->vir_data += len; + + if (h2cb->vir_data > h2cb->vir_end) + return NULL; + + if (h2cb->data_len < len) + return NULL; + + h2cb->data_len -= len; + + return h2cb->vir_data; +} + +u8 *h2cb_put(struct rtw_h2c_pkt *h2cb, u32 len) +{ + u8 *tmp = h2cb_tail_pointer(h2cb); + + h2cb->vir_tail += len; + h2cb->data_len += len; + + if (h2cb->vir_tail > h2cb->vir_end) + return NULL; + + return tmp; +} + +u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb, + u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack) +{ + struct fwcmd_hdr *hdr; + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACFWNONRDY; + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("%s: MAC is not ready\n", __func__); + adapter->stats.h2c_pkt_uninit++; + } + + hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN); + if (!hdr) + return MACNPTR; + + hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) | + SET_WORD(cat, H2C_HDR_CAT) | + SET_WORD(_class_, H2C_HDR_CLASS) | + SET_WORD(func, H2C_HDR_FUNC) | + SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ)); + + hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->data_len, H2C_HDR_TOTAL_LEN) | + (rack || !(fwinfo->h2c_seq & 3) ? + H2C_HDR_REC_ACK : 0) | + (dack ? H2C_HDR_DONE_ACK : 0)); + + h2cb->id = SET_FWCMD_ID(type, cat, _class_, func); + h2cb->h2c_seq = fwinfo->h2c_seq; + + return MACSUCCESS; +} + +u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter, + struct rtw_h2c_pkt *h2cb, u8 type, u8 cat, + u8 _class_, u8 func, u16 rack, u16 dack) +{ + struct fwcmd_hdr *hdr; + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + + hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN); + if (!hdr) + return MACNPTR; + + hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) | + SET_WORD(cat, H2C_HDR_CAT) | + SET_WORD(_class_, H2C_HDR_CLASS) | + SET_WORD(func, H2C_HDR_FUNC) | + SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ)); + + hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->data_len, H2C_HDR_TOTAL_LEN) | + (rack ? H2C_HDR_REC_ACK : 0) | + (dack ? H2C_HDR_DONE_ACK : 0)); + + h2cb->id = SET_FWCMD_ID(type, cat, _class_, func); + h2cb->h2c_seq = fwinfo->h2c_seq; + + return MACSUCCESS; +} + +u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb, + u8 *cmd, u32 len) +{ + u8 *buf; + + buf = h2cb_put(h2cb, len); + if (!buf) + return MACNPTR; + PLTFM_MEMCPY(buf, cmd, len); + return MACSUCCESS; +} + +u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb) +{ + u8 *buf; + u32 ret; + u32 txd_len; + struct rtw_t_meta_data info = {0}; + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + + info.type = RTW_PHL_PKT_TYPE_H2C; + info.pktlen = (u16)h2cb->data_len; + txd_len = ops->txdesc_len(adapter, &info); + if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + if (((info.pktlen + txd_len) & (512 - 1)) == 0) { + buf = h2cb_put(h2cb, 4); + if (!buf) { + PLTFM_MSG_ERR("Avoid USB 512-byte FAIL\n"); + return MACNPTR; + } + info.pktlen = (u16)h2cb->data_len; + txd_len = ops->txdesc_len(adapter, &info); + } + } + + buf = h2cb_push(h2cb, txd_len); + if (!buf) + return MACNPTR; + + ret = ops->build_txdesc(adapter, &info, buf, txd_len); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id) +{ + return MACSUCCESS; +} + +#else +struct h2c_buf *h2cb_alloc(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class) +{ + struct h2c_buf_head *list_head = &h2cb_head[buf_class]; + struct h2c_buf *h2cb; + + if (buf_class >= H2CB_CLASS_LAST) { + PLTFM_MSG_ERR("[ERR]unknown class\n"); + return NULL; + } + + PLTFM_MUTEX_LOCK(&list_head->lock); + + h2cb = h2cb_dequeue(list_head); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]allocate h2cb, class : %d\n", buf_class); + goto h2cb_fail; + } + + if (!(h2cb->flags & H2CB_FLAGS_FREED)) { + PLTFM_MSG_ERR("[ERR]not freed flag\n"); + PLTFM_FREE(h2cb, sizeof(struct h2c_buf)); + goto h2cb_fail; + } + + h2cb->flags &= ~H2CB_FLAGS_FREED; + PLTFM_MUTEX_UNLOCK(&list_head->lock); + + return h2cb; +h2cb_fail: + PLTFM_MUTEX_UNLOCK(&list_head->lock); + return NULL; +} + +void h2cb_free(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb) +{ + struct h2c_buf_head *list_head; + + if (h2cb->flags & H2CB_FLAGS_FREED) { + PLTFM_MSG_ERR("[ERR]freed flag\n"); + return; + } + + if (h2cb->_class_ >= H2CB_CLASS_LAST) { + PLTFM_MSG_ERR("[ERR]unknown class\n"); + return; + } + + list_head = &h2cb_head[h2cb->_class_]; + + h2cb->len = 0; + h2cb->data = h2cb->head + h2cb->hdr_len; + h2cb->tail = h2cb->data; + h2cb->flags |= H2CB_FLAGS_FREED; + + PLTFM_MUTEX_LOCK(&list_head->lock); + __h2cb_queue_tail(list_head, h2cb); + PLTFM_MUTEX_UNLOCK(&list_head->lock); +} + +u8 *h2cb_push(struct h2c_buf *h2cb, u32 len) +{ + h2cb->data -= len; + h2cb->len += len; + + if (h2cb->data < h2cb->head) + return NULL; + + return h2cb->data; +} + +u8 *h2cb_pull(struct h2c_buf *h2cb, u32 len) +{ + h2cb->data += len; + + if (h2cb->data > h2cb->end) + return NULL; + + if (h2cb->len < len) + return NULL; + + h2cb->len -= len; + + return h2cb->data; +} + +u8 *h2cb_put(struct h2c_buf *h2cb, u32 len) +{ + u8 *tmp = h2cb_tail_pointer(h2cb); + + h2cb->tail += len; + h2cb->len += len; + + if (h2cb->tail > h2cb->end) + return NULL; + + return tmp; +} + +u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack) +{ + struct fwcmd_hdr *hdr; + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACFWNONRDY; + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("MAC is not ready\n"); + adapter->stats.h2c_pkt_uninit++; + } + + hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN); + if (!hdr) + return MACNPTR; + + hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) | + SET_WORD(cat, H2C_HDR_CAT) | + SET_WORD(_class_, H2C_HDR_CLASS) | + SET_WORD(func, H2C_HDR_FUNC) | + SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ)); + + hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->len, H2C_HDR_TOTAL_LEN) | + (rack || !(fwinfo->h2c_seq & 3) ? + H2C_HDR_REC_ACK : 0) | + (dack ? H2C_HDR_DONE_ACK : 0)); + + h2cb->id = SET_FWCMD_ID(type, cat, _class_, func); + h2cb->h2c_seq = fwinfo->h2c_seq; + + return 0; +} + +u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter, + struct h2c_buf *h2cb, u8 type, u8 cat, + u8 _class_, u8 func, u16 rack, u16 dack) +{ + struct fwcmd_hdr *hdr; + struct mac_ax_fw_info *fwinfo = &adapter->fw_info; + + hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN); + if (!hdr) + return MACNPTR; + + hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) | + SET_WORD(cat, H2C_HDR_CAT) | + SET_WORD(_class_, H2C_HDR_CLASS) | + SET_WORD(func, H2C_HDR_FUNC) | + SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ)); + + hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->len, H2C_HDR_TOTAL_LEN) | + (rack ? H2C_HDR_REC_ACK : 0) | + (dack ? H2C_HDR_DONE_ACK : 0)); + + h2cb->id = SET_FWCMD_ID(type, cat, _class_, func); + h2cb->h2c_seq = fwinfo->h2c_seq; + + return 0; +} + +u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + u8 *cmd, u32 len) +{ + u8 *buf; + + buf = h2cb_put(h2cb, len); + if (!buf) + return MACNPTR; + PLTFM_MEMCPY(buf, cmd, len); + return MACSUCCESS; +} + +u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb) +{ + u8 *buf; + u32 ret; + u32 txd_len; + struct rtw_t_meta_data info = {0}; + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + + info.type = RTW_PHL_PKT_TYPE_H2C; + info.pktlen = (u16)h2cb->len; + txd_len = ops->txdesc_len(adapter, &info); + if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + if (((info.pktlen + txd_len) & (512 - 1)) == 0) { + buf = h2cb_put(h2cb, 4); + if (!buf) { + PLTFM_MSG_ERR("Avoid USB 512-byte FAIL\n"); + return MACNPTR; + } + info.pktlen = (u16)h2cb->len; + txd_len = ops->txdesc_len(adapter, &info); + } + } + + buf = h2cb_push(h2cb, txd_len); + if (!buf) + return MACNPTR; + + ret = ops->build_txdesc(adapter, &info, buf, txd_len); + if (ret) + return ret; + + return MACSUCCESS; +} + +static inline void __fwcmd_wq_insert(struct h2c_buf *new_h2cb, + struct h2c_buf *prev, struct h2c_buf *next, + struct fwcmd_wkb_head *list) +{ + new_h2cb->next = next; + new_h2cb->prev = prev; + next->prev = new_h2cb; + prev->next = new_h2cb; + list->qlen++; +} + +static inline void __fwcmd_wq_before(struct fwcmd_wkb_head *list, + struct h2c_buf *next, + struct h2c_buf *new_h2cb) +{ + __fwcmd_wq_insert(new_h2cb, next->prev, next, list); +} + +static inline void __fwcmd_wq_tail(struct fwcmd_wkb_head *list, + struct h2c_buf *new_h2cb) +{ + __fwcmd_wq_before(list, (struct h2c_buf *)list, new_h2cb); +} + +u32 fwcmd_wq_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb) +{ + struct fwcmd_wkb_head *list_head = &fwcmd_wq_head; + + if (list_head->qlen > FWCMD_WQ_MAX_JOB_NUM) { + PLTFM_MSG_WARN("[WARN]fwcmd work queue full\n"); + return MACBUFALLOC; + } + + /* worq queue doesn't need wd body */ + h2cb_pull(h2cb, WD_BODY_LEN); + PLTFM_MUTEX_LOCK(&list_head->lock); + __fwcmd_wq_tail(list_head, h2cb); + PLTFM_MUTEX_UNLOCK(&list_head->lock); + + return MACSUCCESS; +} + +static inline void __fwcmd_wq_unlink(struct h2c_buf *h2cb, + struct fwcmd_wkb_head *list) +{ + struct h2c_buf *next, *prev; + + list->qlen--; + next = h2cb->next; + prev = h2cb->prev; + h2cb->prev = NULL; + h2cb->next = NULL; + next->prev = prev; + prev->next = next; +} + +struct h2c_buf *fwcmd_wq_dequeue(struct mac_ax_adapter *adapter, u32 id) +{ + struct fwcmd_wkb_head *list_head = &fwcmd_wq_head; + struct h2c_buf *h2cb; + u32 hdr0; + u16 type = GET_FWCMD_TYPE(id); + u16 cat = GET_FWCMD_CAT(id); + u16 _class_ = GET_FWCMD_CLASS(id); + u16 func = GET_FWCMD_FUNC(id); + + PLTFM_MUTEX_LOCK(&list_head->lock); + + for (h2cb = list_head->next; h2cb->next != list_head->next; + h2cb = h2cb->next) { + hdr0 = ((struct fwcmd_hdr *)h2cb->data)->hdr0; + hdr0 = le32_to_cpu(hdr0); + if (type == GET_FIELD(hdr0, H2C_HDR_DEL_TYPE) && + cat == GET_FIELD(hdr0, H2C_HDR_CAT) && + _class_ == GET_FIELD(hdr0, H2C_HDR_CLASS) && + func == GET_FIELD(hdr0, H2C_HDR_FUNC)) { + __fwcmd_wq_unlink(h2cb, list_head); + PLTFM_MUTEX_UNLOCK(&list_head->lock); + return h2cb; + } + } + + PLTFM_MUTEX_UNLOCK(&list_head->lock); + + PLTFM_MSG_ERR("[ERR]cannot find wq item: %X\n", id); + + return NULL; +} + +u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id) +{ + struct fwcmd_wkb_head *list_head = &fwcmd_wq_head; + struct h2c_buf *h2cb; + + PLTFM_MUTEX_LOCK(&list_head->lock); + + for (h2cb = list_head->next; h2cb->next != list_head->next; + h2cb = h2cb->next) { + if (h2cb->id == id) { + PLTFM_MUTEX_UNLOCK(&list_head->lock); + return MACWQBUSY; + } + } + + PLTFM_MUTEX_UNLOCK(&list_head->lock); + + return MACSUCCESS; +} +#endif + +static u32 c2h_fwi_cmd_log(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ +#if MAC_AX_FEATURE_DBGDEC + u8 syntax_1 = 0, syntax_2 = 0; + + if ((len - FWCMD_HDR_LEN) >= 11) { + syntax_1 = *(buf + FWCMD_HDR_LEN); + syntax_2 = *(buf + FWCMD_HDR_LEN + 1); + } + //PLTFM_MSG_WARN("C2H encoded log syntax_1 %x, syntax_2 %x", syntax_1, syntax_2); + if (syntax_1 == 0xa5 && syntax_2 == 0xa5) { + //PLTFM_MSG_WARN("C2H encoded log"); + fw_log_dump(adapter, buf, len, info); + } else { + if (buf[len - 1] != '\0') + buf[len - 1] = '\0'; + PLTFM_MSG_WARN("C2H log: %s", (char *)(buf + FWCMD_HDR_LEN)); + } +#else + if (buf[len - 1] != '\0') + buf[len - 1] = '\0'; + PLTFM_MSG_WARN("C2H log: %s", (char *)(buf + FWCMD_HDR_LEN)); +#endif + return MACSUCCESS; +} + +static u32 c2h_wow_rcv_ack_hdl(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *info) +{ + u8 *state; + + switch (info->c2h_func) { + case FWCMD_H2C_FUNC_AOAC_REPORT_REQ: + state = &adapter->sm.aoac_rpt; + break; + + default: + return MACSUCCESS; + } + + if (*state == MAC_AX_AOAC_RPT_H2C_SENDING) + *state = MAC_AX_AOAC_RPT_H2C_RCVD; + + return MACSUCCESS; +} + +static u32 c2h_fwofld_rcv_ack_hdl(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *info) +{ + u8 *state; + + switch (info->c2h_func) { + case FWCMD_H2C_FUNC_WRITE_OFLD: + state = &adapter->sm.write_h2c; + break; + + case FWCMD_H2C_FUNC_CONF_OFLD: + state = &adapter->sm.conf_h2c; + break; + + case FWCMD_H2C_FUNC_PACKET_OFLD: + state = &adapter->sm.pkt_ofld; + break; + + case FWCMD_H2C_FUNC_READ_OFLD: + state = &adapter->sm.read_h2c; + break; + + case FWCMD_H2C_FUNC_DUMP_EFUSE: + state = &adapter->sm.efuse_ofld; + break; + case FWCMD_H2C_FUNC_CH_SWITCH: + state = &adapter->sm.ch_switch; + break; + + default: + return MACSUCCESS; + } + + if (*state == MAC_AX_OFLD_H2C_SENDING) + *state = MAC_AX_OFLD_H2C_RCVD; + + return MACSUCCESS; +} + +static u32 c2h_fwi_rev_ack(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 data = *(u32 *)(buf + FWCMD_HDR_LEN); + u32 ret; + u32 cat; + + data = le32_to_cpu(data); + + cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT); + if (cat == FWCMD_H2C_CAT_OUTSRC) + return MACSUCCESS; + + info->c2h_cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT); + info->c2h_class = GET_FIELD(data, FWCMD_C2H_REC_ACK_CLASS); + info->c2h_func = GET_FIELD(data, FWCMD_C2H_REC_ACK_FUNC); + info->h2c_seq = GET_FIELD(data, FWCMD_C2H_REC_ACK_H2C_SEQ); + adapter->fw_info.rec_seq = info->h2c_seq; + info->type_rec_ack = 1; + + if (info->c2h_cat == FWCMD_H2C_CAT_MAC) { + switch (info->c2h_class) { + case FWCMD_H2C_CL_WOW: + ret = c2h_wow_rcv_ack_hdl(adapter, info); + if (ret) + return ret; + break; + + case FWCMD_H2C_CL_FW_OFLD: + ret = c2h_fwofld_rcv_ack_hdl(adapter, info); + if (ret) + return ret; + break; + + default: + return MACSUCCESS; + } + } + + return MACSUCCESS; +} + +static u32 c2h_fwofld_done_ack_hdl(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *info) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + struct mac_ax_scanofld_info *scanofld_info = &adapter->scanofld_info; + + switch (info->c2h_func) { + case FWCMD_H2C_FUNC_WRITE_OFLD: + if (sm->write_h2c == MAC_AX_OFLD_H2C_RCVD) { + if (info->h2c_return == MACSUCCESS) + sm->write_h2c = MAC_AX_OFLD_H2C_IDLE; + else + sm->write_h2c = MAC_AX_OFLD_H2C_ERROR; + } + break; + + case FWCMD_H2C_FUNC_CONF_OFLD: + if (sm->conf_h2c == MAC_AX_OFLD_H2C_RCVD) { + if (info->h2c_return == MACSUCCESS) + sm->conf_h2c = MAC_AX_OFLD_H2C_IDLE; + else + sm->conf_h2c = MAC_AX_OFLD_H2C_ERROR; + } + break; + + case FWCMD_H2C_FUNC_PACKET_OFLD: + if (sm->pkt_ofld == MAC_AX_OFLD_H2C_RCVD) { + if (info->h2c_return == MACSUCCESS) { + if (ofld_info->last_op == PKT_OFLD_OP_READ) + sm->pkt_ofld = MAC_AX_OFLD_H2C_DONE; + else + sm->pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + } else { + sm->pkt_ofld = MAC_AX_OFLD_H2C_ERROR; + } + } else { + PLTFM_MSG_ERR("cant set pkt ofld state since no recv ack is received."); + } + break; + + case FWCMD_H2C_FUNC_READ_OFLD: + if (sm->read_h2c == MAC_AX_OFLD_H2C_RCVD) { + if (info->h2c_return == MACSUCCESS) + sm->read_h2c = MAC_AX_OFLD_H2C_DONE; + else + sm->read_h2c = MAC_AX_OFLD_H2C_ERROR; + } + break; + + case FWCMD_H2C_FUNC_DUMP_EFUSE: + if (sm->efuse_ofld == MAC_AX_OFLD_H2C_RCVD) { + if (info->h2c_return == MACSUCCESS) + sm->efuse_ofld = MAC_AX_OFLD_H2C_DONE; + else + sm->efuse_ofld = MAC_AX_OFLD_H2C_ERROR; + } + break; + case FWCMD_H2C_FUNC_ADD_SCANOFLD_CH: + if (scanofld_info->clear_drv_ch_list && scanofld_info->list->head) + mac_scanofld_ch_list_clear(adapter, scanofld_info->list); + PLTFM_MSG_TRACE("[scan] got add scanofld done ack. clear chlist busy\n"); + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + adapter->scanofld_info.drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + adapter->scanofld_info.fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + PLTFM_MSG_TRACE("[scan] drv_chlist_state = %d, fw_chlist_state = %d\n", + adapter->scanofld_info.drv_chlist_busy, + adapter->scanofld_info.fw_chlist_busy); + break; + case FWCMD_H2C_FUNC_SCANOFLD: + if (info->h2c_return != MACSUCCESS) { + PLTFM_MSG_TRACE("[scan]scan func fail, revert fwchlist and fw status\n"); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = !scanofld_info->fw_chlist_busy; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_scan_busy = !scanofld_info->fw_scan_busy; + } + PLTFM_MSG_TRACE("[scan] fw_scan_busy = %d, fw_chlist_state = %d\n", + scanofld_info->fw_scan_busy, + scanofld_info->fw_chlist_busy); + break; + default: + break; + } + return MACSUCCESS; +} + +static u32 c2h_role_done_ack_hdl(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *info) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + + if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT && + info->c2h_func == FWCMD_H2C_FUNC_FWROLE_MAINTAIN) { + if (info->h2c_return == MACSUCCESS) { + sm->role_stat = MAC_AX_ROLE_ALOC_SUCC; + } else { + PLTFM_MSG_ERR("[ERR]role_maintain: alloc failed\n"); + sm->role_stat = MAC_AX_ROLE_ALOC_FAIL; + return MACROLEALOCFL; + } + } else if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT && + info->c2h_func == FWCMD_H2C_FUNC_JOININFO) { + if (info->h2c_return == MACSUCCESS) { + sm->role_stat = MAC_AX_ROLE_INIT_SUCC; + } else { + PLTFM_MSG_ERR("[ERR]role_join: init failed\n"); + sm->role_stat = MAC_AX_ROLE_INIT_FAIL; + return MACROLEINITFL; + } + } else if (info->c2h_class == FWCMD_H2C_CL_ADDR_CAM_UPDATE && + info->c2h_func == FWCMD_H2C_FUNC_ADDRCAM_INFO) { + if (info->h2c_return == MACSUCCESS) { + sm->role_stat = MAC_AX_ROLE_HW_UPD_SUCC; + } else { + PLTFM_MSG_ERR("[ERR]ADDR_CAM: upd failed\n"); + sm->role_stat = MAC_AX_ROLE_HW_UPD_FAIL; + return MACROLEHWUPDFL; + } + } + return MACSUCCESS; +} + +static u32 c2h_ps_done_ack_hdl(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *info) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + u8 p2pid; + u32 ret; + + switch (info->c2h_func) { + case FWCMD_H2C_FUNC_P2P_ACT: + if (sm->p2p_stat != MAC_AX_P2P_ACT_BUSY) { + PLTFM_MSG_ERR("[ERR]p2p act dack stat err %d\n", + sm->p2p_stat); + return MACPROCERR; + } + + if (info->h2c_return != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p act dack ret %d\n", + info->h2c_return); + sm->p2p_stat = MAC_AX_P2P_ACT_FAIL; + break; + } + + p2pid = P2PID_INVALID; + ret = get_wait_dack_p2pid(adapter, &p2pid); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p act dack get wait id %d\n", ret); + return ret; + } + if (p2pid != P2PID_INVALID) { + if (adapter->p2p_info[p2pid].run) { + PLTFM_MEMSET(&adapter->p2p_info[p2pid], 0, + sizeof(struct mac_ax_p2p_info)); + } else { + adapter->p2p_info[p2pid].run = 1; + adapter->p2p_info[p2pid].wait_dack = 0; + } + } else { + PLTFM_MSG_ERR("[ERR]p2p act dack no wait id\n"); + } + sm->p2p_stat = MAC_AX_P2P_ACT_IDLE; + break; + case FWCMD_H2C_FUNC_P2P_MACID_CTRL: + if (sm->p2p_stat != MAC_AX_P2P_ACT_BUSY) { + PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack stat err %d\n", + sm->p2p_stat); + return MACPROCERR; + } + + if (info->h2c_return != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack ret %d\n", + info->h2c_return); + sm->p2p_stat = MAC_AX_P2P_ACT_FAIL; + break; + } + + p2pid = P2PID_INVALID; + ret = get_wait_dack_p2pid(adapter, &p2pid); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack get wait id %d\n", + ret); + return ret; + } + if (p2pid != P2PID_INVALID) { + if (adapter->p2p_info[p2pid].run) { + adapter->p2p_info[p2pid].wait_dack = 0; + } else { + PLTFM_MSG_ERR("[ERR]p2p%d macid ctrl dack not run\n", + p2pid); + } + } else { + PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack no wait id\n"); + } + sm->p2p_stat = MAC_AX_P2P_ACT_IDLE; + break; + case FWCMD_H2C_FUNC_IPS_CFG: + if (info->h2c_return != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]fwips dack ret %d\n", info->h2c_return); + break; + case FWCMD_H2C_FUNC_PS_ADVANCE_PARM: + if (info->h2c_return != MACSUCCESS) + PLTFM_MSG_ERR("[ERR]ps advanced parm dack ret %d\n", info->h2c_return); + break; + default: + break; + } + + return MACSUCCESS; +} + +static u32 c2h_fwi_done_ack(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 data = *(u32 *)(buf + FWCMD_HDR_LEN); + u32 ret; + u32 cat; + + data = le32_to_cpu(data); + + cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT); + if (cat == FWCMD_H2C_CAT_OUTSRC) + return MACSUCCESS; + + info->c2h_cat = GET_FIELD(data, FWCMD_C2H_DONE_ACK_CAT); + info->c2h_class = GET_FIELD(data, FWCMD_C2H_DONE_ACK_CLASS); + info->c2h_func = GET_FIELD(data, FWCMD_C2H_DONE_ACK_FUNC); + info->h2c_return = GET_FIELD(data, FWCMD_C2H_DONE_ACK_H2C_RETURN); + info->h2c_seq = GET_FIELD(data, FWCMD_C2H_DONE_ACK_H2C_SEQ); + info->type_done_ack = 1; + + if (info->c2h_cat == FWCMD_H2C_CAT_MAC) { + if (info->c2h_class == FWCMD_H2C_CL_FW_OFLD) { + ret = c2h_fwofld_done_ack_hdl(adapter, info); + if (ret != MACSUCCESS) + return ret; + } else if (info->c2h_class == FWCMD_H2C_CL_PS) { + ret = c2h_ps_done_ack_hdl(adapter, info); + if (ret != MACSUCCESS) + return ret; + } else if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT || + info->c2h_class == FWCMD_H2C_CL_ADDR_CAM_UPDATE) { + ret = c2h_role_done_ack_hdl(adapter, info); + if (ret != MACSUCCESS) + return ret; + } + } + + return MACSUCCESS; +} + +static u32 c2h_fwi_bcn_stats(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +static u32 c2h_fwi_bcn_csazero(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_fw_info_cmd[] = { + {FWCMD_C2H_FUNC_REC_ACK, c2h_fwi_rev_ack}, + {FWCMD_C2H_FUNC_DONE_ACK, c2h_fwi_done_ack}, + {FWCMD_C2H_FUNC_C2H_LOG, c2h_fwi_cmd_log}, + {FWCMD_C2H_FUNC_BCN_CNT, c2h_fwi_bcn_stats}, + {FWCMD_C2H_FUNC_BCN_CSAZERO, c2h_fwi_bcn_csazero}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_fw_info(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_fw_info_cmd; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: %X", func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +static u32 c2h_dump_efuse_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info; + u32 size; + + if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_RCVD) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return MACPROCERR; + } + + size = adapter->hw_info->efuse_size; + + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(size); + if (!ofld_info->buf) { + adapter->sm.efuse = MAC_AX_EFUSE_IDLE; + return MACBUFALLOC; + } + } + + PLTFM_MEMCPY(ofld_info->buf, buf + FWCMD_HDR_LEN, size); + + adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_DONE; + + return MACSUCCESS; +} + +static u32 c2h_read_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct mac_ax_read_ofld_value *value_info = &adapter->read_ofld_value; + u32 hdr1; + u16 read_len; + u8 *read_buff; + + if (value_info->buf) + PLTFM_FREE(value_info->buf, value_info->len); + + hdr1 = ((struct fwcmd_hdr *)buf)->hdr1; + hdr1 = le32_to_cpu(hdr1); + + read_len = GET_FIELD(hdr1, C2H_HDR_TOTAL_LEN) - FWCMD_HDR_LEN; + + read_buff = (u8 *)PLTFM_MALLOC(read_len); + if (!read_buff) + return MACBUFALLOC; + + PLTFM_MEMCPY(read_buff, buf + FWCMD_HDR_LEN, read_len); + + value_info->len = read_len; + value_info->buf = read_buff; + + return MACSUCCESS; +} + +static u32 c2h_pkt_ofld_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + struct mac_ax_pkt_ofld_pkt *ofld_pkt = &adapter->pkt_ofld_pkt; + u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN); + u16 pkt_len; + u8 id, pkt_op; + u8 *pkt_buff; + u8 *pkt_content; + + c2h_content = le32_to_cpu(c2h_content); + + pkt_op = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_OP); + pkt_len = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH); + id = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_ID); + + PLTFM_MSG_TRACE("get pkt ofld rsp. pkt_op: %d, pkt_len: %d, id: %d\n", pkt_op, pkt_len, id); + + switch (pkt_op) { + case PKT_OFLD_OP_ADD: + if (pkt_len != 0) { + ofld_info->id_bitmap[id >> 3] |= (1 << (id & 7)); + ofld_info->free_id_count--; + ofld_info->used_id_count++; + } + + break; + + case PKT_OFLD_OP_DEL: + if (pkt_len != 0) { + ofld_info->id_bitmap[id >> 3] &= ~(1 << (id & 7)); + ofld_info->free_id_count++; + ofld_info->used_id_count--; + } + + break; + + case PKT_OFLD_OP_READ: + if (pkt_len != 0) { + if (ofld_pkt->pkt) + PLTFM_FREE(ofld_pkt->pkt, ofld_pkt->pkt_len); + + pkt_buff = (u8 *)PLTFM_MALLOC(pkt_len); + if (!pkt_buff) + return MACBUFALLOC; + + pkt_content = buf + FWCMD_HDR_LEN; + pkt_content += sizeof(struct mac_ax_pkt_ofld_hdr); + PLTFM_MEMCPY(pkt_buff, pkt_content, pkt_len); + ofld_pkt->pkt_id = id; + ofld_pkt->pkt_len = pkt_len; + ofld_pkt->pkt = pkt_buff; + } + break; + + default: + PLTFM_MSG_ERR("[ERR]invalid packet offload op: %d", pkt_op); + break; + } + + return MACSUCCESS; +} + +static u32 c2h_beacon_resend_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +static u32 c2h_macid_pause_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +static u32 c2h_tx_duty_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + u32 content = *(u32 *)(buf + FWCMD_HDR_LEN); + struct mac_ax_tx_duty_ofld_info ofld_info; + + content = le32_to_cpu(content); + + ofld_info.timer_err = + GET_FIELD(content, FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR); + + if (ofld_info.timer_err) + PLTFM_MSG_ERR("[ERR]Tx duty FW timer error\n"); + + return MACSUCCESS; +} + +static u32 c2h_tsf32_togl_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct fwcmd_tsf32_togl_rpt rpt; + struct mac_ax_t32_togl_rpt *out_rpt; + u8 band, port; + + if (!buf) { + PLTFM_MSG_ERR("[ERR]tsf32 togl rpt no buf\n"); + return MACNPTR; + } + + rpt.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN)); + rpt.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4)); + rpt.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8)); + + band = rpt.dword0 & FWCMD_C2H_TSF32_TOGL_RPT_BAND; + if (band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d in tsf32 togl rpt\n", band); + return MACNOITEM; + } + + port = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_PORT); + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d in tsf32 togl rpt\n", port); + return MACNOITEM; + } + + out_rpt = &adapter->t32_togl_rpt[get_bp_idx(band, port)]; + out_rpt->band = band; + out_rpt->port = port; + out_rpt->status = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_STATUS); + out_rpt->early = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_EARLY); + out_rpt->tsf_l = GET_FIELD(rpt.dword1, FWCMD_C2H_TSF32_TOGL_RPT_TSF_L); + out_rpt->tsf_h = GET_FIELD(rpt.dword2, FWCMD_C2H_TSF32_TOGL_RPT_TSF_H); + out_rpt->valid = 1; + + return MACSUCCESS; +} + +static u32 c2h_cmd_ofld_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct fwcmd_cmd_ofld_rsp rsp; + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + struct mac_ax_state_mach *sm = &adapter->sm; + + if (!buf) { + PLTFM_MSG_ERR("[ERR]tsf32 togl rpt no buf\n"); + return MACNPTR; + } + + rsp.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN)); + + ofld_info->result = rsp.dword0 & FWCMD_C2H_CMD_OFLD_RSP_RESULT; + if (ofld_info->result) { + PLTFM_MSG_ERR("%s: IO offload fail!!!\n", __func__); + rsp.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4)); + rsp.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8)); + rsp.dword3 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 12)); + PLTFM_MSG_ERR("offset = %x\n", rsp.dword1); + PLTFM_MSG_ERR("expected val = %x\n", rsp.dword2); + PLTFM_MSG_ERR("read val = %x\n", rsp.dword3); + } + + if (sm->cmd_state != MAC_AX_CMD_OFLD_SENDING) + PLTFM_MSG_ERR("%s: IO offload stat err\n", __func__); + else + sm->cmd_state = MAC_AX_CMD_OFLD_RCVD; + + return MACSUCCESS; +} + +static u32 c2h_scanofld_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + struct fwcmd_scanofld_rsp rsp; + u32 *c2h_content = (u32 *)(buf + FWCMD_HDR_LEN); + u8 central_ch; + u8 scanned_ch; + u8 notify_reason; + u8 status; + u32 tsf_low; + u32 tsf_high; + u32 spent_low; + u32 spent_high; + + rsp.dword0 = le32_to_cpu(*c2h_content); + central_ch = GET_FIELD(rsp.dword0, FWCMD_C2H_SCANOFLD_RSP_CENTRAL_CH); + scanned_ch = GET_FIELD(rsp.dword0, FWCMD_C2H_SCANOFLD_RSP_SCANNED_CH); + notify_reason = GET_FIELD(rsp.dword0, FWCMD_C2H_SCANOFLD_RSP_NOTIFY_REASON); + status = GET_FIELD(rsp.dword0, FWCMD_C2H_SCANOFLD_RSP_STATUS); + tsf_low = le32_to_cpu(*(c2h_content + 1)); + tsf_high = le32_to_cpu(*(c2h_content + 2)); + spent_low = le32_to_cpu(*(c2h_content + 3)); + spent_high = le32_to_cpu(*(c2h_content + 4)); + PLTFM_MSG_TRACE("[scan rsp]cent = %d, scanned = %d, noti = %d, status = %d, tsf = %x.%x\n", + central_ch, scanned_ch, notify_reason, status, tsf_high, tsf_low); + if (notify_reason == MAC_AX_SCAN_END_SCAN_NOTIFY) { + PLTFM_MUTEX_LOCK(&adapter->scanofld_info.fw_chlist_state_lock); + adapter->scanofld_info.fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&adapter->scanofld_info.fw_chlist_state_lock); + adapter->scanofld_info.fw_scan_busy = 0; + } + return 0; +} + +static u32 c2h_ch_switch_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, + u32 len, struct rtw_c2h_info *info) +{ + u32 *content = (u32 *)(buf + FWCMD_HDR_LEN); + u8 *state; + u32 rpt_size; + struct mac_ax_ch_switch_rpt *rpt; + + state = &adapter->sm.ch_switch; + if (*state != MAC_AX_OFLD_H2C_SENDING && *state != MAC_AX_OFLD_H2C_RCVD) + return MACPROCERR; + rpt_size = sizeof(struct mac_ax_ch_switch_rpt); + if (!adapter->ch_switch_rpt) + adapter->ch_switch_rpt = (struct mac_ax_ch_switch_rpt *)PLTFM_MALLOC(rpt_size); + if (!adapter->ch_switch_rpt) + return MACPROCERR; + rpt = adapter->ch_switch_rpt; + rpt->result = (u8)GET_FIELD(le32_to_cpu(*content), FWCMD_C2H_CH_SWITCH_RPT_RESULT); + *state = MAC_AX_CH_SWITCH_GET_RPT; + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_fw_ofld_cmd[] = { + {FWCMD_C2H_FUNC_EFUSE_DUMP, c2h_dump_efuse_hdl}, + {FWCMD_C2H_FUNC_READ_RSP, c2h_read_rsp_hdl}, + {FWCMD_C2H_FUNC_PKT_OFLD_RSP, c2h_pkt_ofld_rsp_hdl}, + {FWCMD_C2H_FUNC_BEACON_RESEND, c2h_beacon_resend_hdl}, + {FWCMD_C2H_FUNC_MACID_PAUSE, c2h_macid_pause_hdl}, + {FWCMD_C2H_FUNC_TSF32_TOGL_RPT, c2h_tsf32_togl_rpt_hdl}, + {FWCMD_C2H_FUNC_CMD_OFLD_RSP, c2h_cmd_ofld_rsp_hdl}, + {FWCMD_C2H_FUNC_TX_DUTY_RPT, c2h_tx_duty_hdl}, + {FWCMD_C2H_FUNC_SCANOFLD_RSP, c2h_scanofld_rsp_hdl}, + {FWCMD_C2H_FUNC_CH_SWITCH_RPT, c2h_ch_switch_rpt_hdl}, + {FWCMD_C2H_FUNC_NULL, NULL} +}; + +u32 c2h_fw_ofld(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_fw_ofld_cmd; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: %X", func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_twt(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +u32 c2h_wow_aoac_report_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct mac_ax_wowlan_info *wowlan_info = &adapter->wowlan_info; + u8 *c2h_content = buf + FWCMD_HDR_LEN; + + if (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_H2C_RCVD) + return MACPROCERR; + + if (!wowlan_info->aoac_report) + return MACBUFALLOC; + + PLTFM_MEMCPY(wowlan_info->aoac_report, c2h_content, sizeof(struct mac_ax_aoac_report)); + + adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_H2C_DONE; + + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_wow_cmd[] = { + {FWCMD_C2H_FUNC_AOAC_REPORT, c2h_wow_aoac_report_hdl}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_wow(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_wow_cmd; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: %X", func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_mcc_rcv_ack_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN); + u8 group, h2c_func; + + c2h_content = le32_to_cpu(c2h_content); + group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_RCV_ACK_GROUP); + h2c_func = GET_FIELD(c2h_content, FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC); + + if (h2c_func <= FWCMD_H2C_FUNC_RESET_MCC_GROUP) { + PLTFM_MSG_TRACE("[TRACE]%s: MCC group H2C rcv ack\n", + __func__); + + if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_SENT) { + sm->mcc_group[group] = MAC_AX_MCC_STATE_H2C_RCVD; + + PLTFM_MSG_TRACE("[TRACE]%s: MCC group %d state: %d\n", + __func__, group, + MAC_AX_MCC_STATE_H2C_RCVD); + } + } else if (h2c_func <= FWCMD_H2C_FUNC_MCC_SET_DURATION) { + PLTFM_MSG_TRACE("[TRACE]%s: MCC request H2C rcv ack\n", + __func__); + + if (sm->mcc_request[group] == MAC_AX_MCC_REQ_H2C_SENT) { + sm->mcc_request[group] = MAC_AX_MCC_REQ_H2C_RCVD; + + PLTFM_MSG_TRACE("[TRACE]%s: MCC group %d state: %d\n", + __func__, group, + MAC_AX_MCC_REQ_H2C_RCVD); + } + } else { + PLTFM_MSG_ERR("[ERR]%s: invalid MCC H2C func %d\n", + __func__, h2c_func); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 c2h_mcc_req_ack_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN); + u8 group, h2c_func, h2c_return; + + c2h_content = le32_to_cpu(c2h_content); + group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_GROUP); + h2c_func = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC); + h2c_return = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN); + + PLTFM_MSG_TRACE("[TRACE]%s: group: %d, h2c_func: %d, h2c_return: %d\n", + __func__, group, h2c_func, h2c_return); + + if (h2c_func < FWCMD_H2C_FUNC_MCC_REQ_TSF) { + PLTFM_MSG_ERR("[ERR]%s: invalid MCC H2C func: %d\n", + __func__, h2c_func); + return MACNOITEM; + } + + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr req state: %d\n", + __func__, group, sm->mcc_request[group]); + + if (sm->mcc_request[group] == MAC_AX_MCC_REQ_H2C_RCVD) { + if (h2c_return == 0) { + if (h2c_func == FWCMD_H2C_FUNC_MCC_REQ_TSF) + sm->mcc_request[group] = MAC_AX_MCC_REQ_DONE; + else + sm->mcc_request[group] = MAC_AX_MCC_REQ_IDLE; + } else { + sm->mcc_request[group] = MAC_AX_MCC_REQ_FAIL; + PLTFM_MSG_ERR("[ERR]%s: MCC H2C func %d fail: %d\n", + __func__, h2c_func, h2c_return); + } + } + + return MACSUCCESS; +} + +u32 c2h_mcc_tsf_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info; + struct fwcmd_mcc_tsf_rpt *tsf_rpt; + u32 c2h_content; + u32 tsf; + u8 macid_x, macid_y, group; + + PLTFM_MSG_TRACE("[TRACE]%s: mcc tsf report received\n", __func__); + + tsf_rpt = (struct fwcmd_mcc_tsf_rpt *)(buf + FWCMD_HDR_LEN); + + c2h_content = tsf_rpt->dword0; + c2h_content = le32_to_cpu(c2h_content); + group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_GROUP); + macid_x = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_MACID_X); + macid_y = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_MACID_Y); + + PLTFM_MSG_TRACE("[TRACE]%s: group: %d, macid_x: %d, macid_y: %d\n", + __func__, group, macid_x, macid_y); + + mcc_info->groups[group].macid_x = macid_x; + mcc_info->groups[group].macid_y = macid_y; + + tsf = tsf_rpt->dword1; + tsf = le32_to_cpu(tsf); + mcc_info->groups[group].tsf_x_low = tsf; + + tsf = tsf_rpt->dword2; + tsf = le32_to_cpu(tsf); + mcc_info->groups[group].tsf_x_high = tsf; + + tsf = tsf_rpt->dword3; + tsf = le32_to_cpu(tsf); + mcc_info->groups[group].tsf_y_low = tsf; + + tsf = tsf_rpt->dword4; + tsf = le32_to_cpu(tsf); + mcc_info->groups[group].tsf_y_high = tsf; + + PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_high: 0x%x, tsf_x_low: 0x%x\n", + __func__, mcc_info->groups[group].tsf_x_high, + mcc_info->groups[group].tsf_x_low); + + PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_high: 0x%x, tsf_y_low: 0x%x\n", + __func__, mcc_info->groups[group].tsf_y_high, + mcc_info->groups[group].tsf_y_low); + + return MACSUCCESS; +} + +u32 c2h_mcc_status_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info; + struct mac_ax_state_mach *sm = &adapter->sm; + struct fwcmd_mcc_status_rpt *mcc_rpt; + u32 c2h_content; + u32 tsf_low; + u32 tsf_high; + u8 group, status, macid; + + PLTFM_MSG_TRACE("[TRACE]%s: mcc status report received\n", __func__); + + mcc_rpt = (struct fwcmd_mcc_status_rpt *)(buf + FWCMD_HDR_LEN); + + c2h_content = mcc_rpt->dword0; + tsf_low = mcc_rpt->dword1; + tsf_high = mcc_rpt->dword2; + + c2h_content = le32_to_cpu(c2h_content); + group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_GROUP); + macid = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_MACID); + status = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_STATUS); + + PLTFM_MSG_TRACE("[TRACE]%s: mcc group: %d, macid: %d, status: %d\n", + __func__, group, macid, status); + + switch (status) { + case MAC_AX_MCC_ADD_ROLE_OK: + if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) { + sm->mcc_group[group] = MAC_AX_MCC_ADD_DONE; + PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d add done\n", + __func__, group); + } + break; + + case MAC_AX_MCC_START_GROUP_OK: + if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) { + sm->mcc_group[group] = MAC_AX_MCC_START_DONE; + PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d start done\n", + __func__, group); + } + break; + + case MAC_AX_MCC_STOP_GROUP_OK: + sm->mcc_group[group] = MAC_AX_MCC_STOP_DONE; + PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d stop done\n", + __func__, group); + break; + + case MAC_AX_MCC_DEL_GROUP_OK: + sm->mcc_group[group] = MAC_AX_MCC_EMPTY; + PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d empty\n", + __func__, group); + break; + + case MAC_AX_MCC_RESET_GROUP_OK: + if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) { + sm->mcc_group[group] = MAC_AX_MCC_EMPTY; + PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d empty\n", + __func__, group); + } + break; + + case MAC_AX_MCC_ADD_ROLE_FAIL: + case MAC_AX_MCC_START_GROUP_FAIL: + case MAC_AX_MCC_STOP_GROUP_FAIL: + case MAC_AX_MCC_DEL_GROUP_FAIL: + case MAC_AX_MCC_RESET_GROUP_FAIL: + if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) { + PLTFM_MSG_ERR("[ERR]%s: mcc group %d fail status: %d\n", + __func__, group, status); + sm->mcc_group[group] = MAC_AX_MCC_STATE_ERROR; + } + break; + + default: + break; + } + + tsf_low = le32_to_cpu(tsf_low); + tsf_high = le32_to_cpu(tsf_high); + + mcc_info->groups[group].rpt_status = status; + mcc_info->groups[group].rpt_macid = macid; + mcc_info->groups[group].rpt_tsf_low = tsf_low; + mcc_info->groups[group].rpt_tsf_high = tsf_high; + + PLTFM_MSG_TRACE("[TRACE]%s: tsf_high: 0x%x, tsf_low: 0x%x\n", + __func__, tsf_high, tsf_low); + + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_mcc_cmd[] = { + {FWCMD_C2H_FUNC_MCC_RCV_ACK, c2h_mcc_rcv_ack_hdl}, + {FWCMD_C2H_FUNC_MCC_REQ_ACK, c2h_mcc_req_ack_hdl}, + {FWCMD_C2H_FUNC_MCC_TSF_RPT, c2h_mcc_tsf_rpt_hdl}, + {FWCMD_C2H_FUNC_MCC_STATUS_RPT, c2h_mcc_status_rpt_hdl}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_mcc(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_mcc_cmd; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + PLTFM_MSG_TRACE("[TRACE]%s: func: %d\n", __func__, func); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]%s: null func handler id: %X", + __func__, func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_rx_dbg_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + PLTFM_MSG_ERR("[ERR]%s: FW encounter Rx problem!\n", __func__); + + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_fw_dbg_cmd[] = { + {FWCMD_C2H_FUNC_RX_DBG, c2h_rx_dbg_hdl}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_fw_dbg(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_fw_dbg_cmd; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + PLTFM_MSG_TRACE("[TRACE]%s: func: %d\n", __func__, func); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]%s: null func handler id: %X", + __func__, func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_wps_rpt(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + PLTFM_MSG_TRACE("recevied wps report\n"); + return MACSUCCESS; +} + +static u32 c2h_misc_ccxrpt(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_misc[] = { + {FWCMD_C2H_FUNC_WPS_RPT, c2h_wps_rpt}, + {FWCMD_C2H_FUNC_CCXRPT, c2h_misc_ccxrpt}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +static u32 c2h_cl_misc(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_misc; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: %X", func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_fast_ch_sw_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 *c2h_content; + u32 *rpt_status; + + PLTFM_MSG_TRACE("[HM][C2H][FCS] get rpt func\n"); + adapter->fast_ch_sw_info.busy = 0; + c2h_content = (u32 *)(buf + FWCMD_HDR_LEN); + rpt_status = &adapter->fast_ch_sw_info.status; + PLTFM_MEMCPY(rpt_status, c2h_content, sizeof(u32)); + PLTFM_MSG_TRACE("[HM][C2H][FCS] Report Status: 0x%x\n", adapter->fast_ch_sw_info.status); + + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_fast_ch_sw_cmd[] = { + {FWCMD_C2H_FUNC_FCS_RPT, c2h_fast_ch_sw_rpt_hdl}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 c2h_fast_ch_sw(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + u32 hdr0; + u32 func; + u32 (*handler)(struct mac_ax_adapter *adpater, u8 *buf, + u32 len, struct rtw_c2h_info *info); + struct c2h_proc_func *proc; + + proc = c2h_proc_fast_ch_sw_cmd; + handler = NULL; + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR][%s]: sent id = %x", __func__, func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 c2h_port_init_stat(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct fwcmd_port_init_stat stat; + struct mac_ax_port_info *pinfo; + u8 band, port; + u32 ret, tmp32; + + stat.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN)); + stat.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4)); + stat.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8)); + + band = stat.dword0 & FWCMD_C2H_PORT_INIT_STAT_BAND; + if (band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d in port init stat\n", band); + return MACNOITEM; + } + + port = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_PORT); + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d in port init stat\n", port); + return MACNOITEM; + } + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + ret = GET_FIELD(stat.dword2, FWCMD_C2H_PORT_INIT_STAT_RET); + if (ret != C2H_MPORT_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d init fail: ret %d\n", + band, port, ret); + tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_STEP); + PLTFM_MSG_ERR("[ERR]B%dP%d init fail: step %d\n", + band, port, tmp32); + tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX); + PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg mbid %d\n", + band, port, tmp32); + tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE); + PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg type %d\n", + band, port, tmp32); + tmp32 = GET_FIELD(stat.dword1, FWCMD_C2H_PORT_INIT_STAT_CFG_VAL); + PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg val %d\n", + band, port, tmp32); + pinfo->h2c_sm = MAC_AX_PORT_H2C_FAIL; + } else { + pinfo->h2c_sm = MAC_AX_PORT_H2C_IDLE; + } + + return MACSUCCESS; +} + +u32 c2h_port_cfg_stat(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct fwcmd_port_cfg_stat stat; + struct mac_ax_port_info *pinfo; + u8 band, port, mbssid; + u32 ret, tmp32; + + stat.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN)); + stat.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4)); + stat.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8)); + + band = stat.dword0 & FWCMD_C2H_PORT_CFG_STAT_BAND; + if (band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d in port cfg stat\n", band); + return MACNOITEM; + } + + port = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_PORT); + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d in port cfg stat\n", port); + return MACNOITEM; + } + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + mbssid = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX); + + ret = GET_FIELD(stat.dword2, FWCMD_C2H_PORT_CFG_STAT_RET); + if (ret != C2H_MPORT_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: ret %d\n", + band, port, mbssid, ret); + tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_TYPE); + PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: type %d\n", + band, port, mbssid, tmp32); + tmp32 = GET_FIELD(stat.dword1, FWCMD_C2H_PORT_CFG_STAT_VAL); + PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: val %d\n", + band, port, mbssid, tmp32); + pinfo->h2c_sm = MAC_AX_PORT_H2C_FAIL; + } else { + pinfo->h2c_sm = MAC_AX_PORT_H2C_IDLE; + } + + return MACSUCCESS; +} + +static struct c2h_proc_func c2h_proc_mport[] = { + {FWCMD_C2H_FUNC_PORT_INIT_STAT, c2h_port_init_stat}, + {FWCMD_C2H_FUNC_PORT_CFG_STAT, c2h_port_cfg_stat}, + {FWCMD_C2H_FUNC_NULL, NULL}, +}; + +static u32 c2h_cl_mport(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) +{ + struct c2h_proc_func *proc = c2h_proc_mport; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u32 hdr0; + u32 func; + + hdr0 = ((struct fwcmd_hdr *)buf)->hdr0; + hdr0 = le32_to_cpu(hdr0); + + func = GET_FIELD(hdr0, C2H_HDR_FUNC); + + while (proc->id != FWCMD_C2H_FUNC_NULL) { + if (func == proc->id) { + handler = proc->handler; + break; + } + proc++; + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null func handler id: %X", func); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +static struct c2h_proc_class c2h_proc_sys[] = { +#if MAC_AX_FEATURE_DBGPKG + {FWCMD_C2H_CL_CMD_PATH, c2h_sys_cmd_path}, + {FWCMD_H2C_CL_PLAT_AUTO_TEST, c2h_sys_plat_autotest}, +#if MAC_AX_FEATURE_HV + {FWCMD_C2H_CL_FW_AUTO, c2h_sys_fw_autotest}, +#endif +#endif + {FWCMD_C2H_CL_FW_STATUS, c2h_fw_status}, + {FWCMD_C2H_CL_NULL, NULL}, +}; + +static struct c2h_proc_class c2h_proc_mac[] = { + {FWCMD_C2H_CL_FW_INFO, c2h_fw_info}, + {FWCMD_C2H_CL_FW_OFLD, c2h_fw_ofld}, + {FWCMD_C2H_CL_TWT, c2h_twt}, + {FWCMD_C2H_CL_WOW, c2h_wow}, + {FWCMD_C2H_CL_MCC, c2h_mcc}, + {FWCMD_C2H_CL_FW_DBG, c2h_fw_dbg}, + {FWCMD_C2H_CL_FLASH, c2h_sys_flash_pkt}, + {FWCMD_C2H_CL_MISC, c2h_cl_misc}, + {FWCMD_C2H_CL_FCS, c2h_fast_ch_sw}, + {FWCMD_C2H_CL_MPORT, c2h_cl_mport}, + {FWCMD_C2H_CL_NULL, NULL}, +}; + +static inline struct c2h_proc_class *c2h_proc_sel(u8 cat) +{ + struct c2h_proc_class *proc; + + switch (cat) { + case FWCMD_C2H_CAT_TEST: + proc = c2h_proc_sys; + break; + case FWCMD_C2H_CAT_MAC: + proc = c2h_proc_mac; + break; + default: + proc = NULL; + break; + } + + return proc; +} + +u8 c2h_field_parsing(struct fwcmd_hdr *hdr, struct rtw_c2h_info *info) +{ + u32 val; + + val = le32_to_cpu(hdr->hdr0); + info->c2h_cat = GET_FIELD(val, C2H_HDR_CAT); + info->c2h_class = GET_FIELD(val, C2H_HDR_CLASS); + info->c2h_func = GET_FIELD(val, C2H_HDR_FUNC); + + val = le32_to_cpu(hdr->hdr1); + info->content_len = GET_FIELD(val, C2H_HDR_TOTAL_LEN) - + FWCMD_HDR_LEN; + info->content = (u8 *)(hdr + 1); + + return MACSUCCESS; +} + +u32 mac_process_c2h(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + u8 *ret) +{ + u8 _class_, result; + struct c2h_proc_class *proc; + struct fwcmd_hdr *hdr; + struct rtw_c2h_info *info; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info) = NULL; + u8 cat; + u32 val; + + hdr = (struct fwcmd_hdr *)buf; + + info = (struct rtw_c2h_info *)ret; + val = le32_to_cpu(hdr->hdr0); + + result = c2h_field_parsing(hdr, info); + if (result) { + PLTFM_MSG_ERR("[ERR]parsing c2h hdr error: %X\n", val); + return MACNOITEM; + } + + if (GET_FIELD(val, C2H_HDR_DEL_TYPE) != FWCMD_TYPE_C2H) { + PLTFM_MSG_ERR("[ERR]wrong fwcmd type: %X\n", val); + return MACNOITEM; + } + + cat = (u8)GET_FIELD(val, C2H_HDR_CAT); + + if (cat == FWCMD_C2H_CAT_OUTSRC) + return MACSUCCESS; + + proc = c2h_proc_sel(cat); + if (!proc) { + PLTFM_MSG_ERR("[ERR]wrong fwcmd cat: %X\n", val); + return MACNOITEM; + } + + _class_ = GET_FIELD(val, C2H_HDR_CLASS); + + for (; proc->id != FWCMD_C2H_CL_NULL; proc++) { + if (_class_ == proc->id) { + handler = proc->handler; + break; + } + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null class handler id: %X", proc->id); + return MACNOITEM; + } + + return handler(adapter, buf, len, info); +} + +u32 mac_outsrc_h2c_common(struct mac_ax_adapter *adapter, + struct rtw_g6_h2c_hdr *hdr, u32 *pvalue) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_outsrc_info *info; + + /*temp workaround for h2cb no functionality and outsrc has its timer*/ + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + h2cb = h2cb_alloc(adapter, (enum h2c_buf_class)hdr->type); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, hdr->content_len); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + info = (struct fwcmd_outsrc_info *)buf; + PLTFM_MEMCPY(info->dword0, pvalue, hdr->content_len); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_OUTSRC, + hdr->h2c_class, + hdr->h2c_func, + hdr->rec_ack, + hdr->done_ack); + if (ret) + goto fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_fw_log_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_fw_log *log_cfg) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_log_cfg *log; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_log_cfg)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_log_cfg)); + + log = (struct fwcmd_log_cfg *)buf; + + log->dword0 = cpu_to_le32(SET_WORD(log_cfg->level, + FWCMD_H2C_LOG_CFG_DBG_LV) | + SET_WORD(log_cfg->output, + FWCMD_H2C_LOG_CFG_PATH)); + log->dword1 = cpu_to_le32(log_cfg->comp); + + log->dword2 = cpu_to_le32(log_cfg->comp_ext); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_INFO, + FWCMD_H2C_FUNC_LOG_CFG, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_send_bcn_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_bcn_info *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + struct fwcmd_bcn_upd *hdr; + u32 ret = MACSUCCESS; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_bcn_upd *) + h2cb_put(h2cb, sizeof(struct fwcmd_bcn_upd)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + info->grp_ie_ofst |= info->grp_ie_ofst ? BCN_GRPIE_OFST_EN : 0; + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->port, + FWCMD_H2C_BCN_UPD_PORT) | + SET_WORD(info->mbssid, + FWCMD_H2C_BCN_UPD_MBSSID) | + SET_WORD(info->band, + FWCMD_H2C_BCN_UPD_BAND) | + SET_WORD(info->grp_ie_ofst, + FWCMD_H2C_BCN_UPD_GRP_IE_OFST)); + + hdr->dword1 = + cpu_to_le32(SET_WORD(info->macid, + FWCMD_H2C_BCN_UPD_MACID) | + SET_WORD(info->ssn_sel, + FWCMD_H2C_BCN_UPD_SSN_SEL) | + SET_WORD(info->ssn_mode, + FWCMD_H2C_BCN_UPD_SSN_MODE) | + SET_WORD(info->rate_sel, + FWCMD_H2C_BCN_UPD_RATE) | + SET_WORD(info->txpwr, + FWCMD_H2C_BCN_UPD_TXPWR)); + + hdr->dword2 = + cpu_to_le32((info->txinfo_ctrl_en ? + FWCMD_H2C_BCN_UPD_TXINFO_CTRL_EN : 0) | + SET_WORD(info->ntx_path_en, + FWCMD_H2C_BCN_UPD_NTX_PATH_EN) | + SET_WORD(info->path_map_a, + FWCMD_H2C_BCN_UPD_PATH_MAP_A) | + SET_WORD(info->path_map_b, + FWCMD_H2C_BCN_UPD_PATH_MAP_B) | + SET_WORD(info->path_map_c, + FWCMD_H2C_BCN_UPD_PATH_MAP_C) | + SET_WORD(info->path_map_d, + FWCMD_H2C_BCN_UPD_PATH_MAP_D) | + (info->antsel_a ? + FWCMD_H2C_BCN_UPD_ANTSEL_A : 0) | + (info->antsel_b ? + FWCMD_H2C_BCN_UPD_ANTSEL_B : 0) | + (info->antsel_c ? + FWCMD_H2C_BCN_UPD_ANTSEL_C : 0) | + (info->antsel_d ? + FWCMD_H2C_BCN_UPD_ANTSEL_D : 0) | + SET_WORD(info->csa_ofst, + FWCMD_H2C_BCN_UPD_CSA_OFST)); + + buf = h2cb_put(h2cb, info->pld_len); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, info->pld_buf, info->pld_len); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_BCN_UPD, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_host_getpkt_h2c(struct mac_ax_adapter *adapter, u8 macid, u8 pkttype) +{ + //temp patch, wait for h2creg api + u32 content = 0; + u32 ret; + + content |= FWCMD_H2CREG_FUNC_GETPKT_INFORM; + content |= (1 << 8); + content |= (macid << 16); + content |= (pkttype << 24); + + ret = mac_send_h2creg(adapter, &content, 1); + + return ret; +} + +#if MAC_AX_PHL_H2C +u32 __ie_cam_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb, + struct mac_ax_ie_cam_cmd_info *info) +{ + struct fwcmd_ie_cam *cmd; + u8 *buf; + u32 ret = MACSUCCESS; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ie_cam)); + if (!buf) { + ret = MACNOBUF; + return ret; + } + + cmd = (struct fwcmd_ie_cam *)buf; + cmd->dword0 = + cpu_to_le32((info->en ? FWCMD_H2C_IE_CAM_CAM_EN : 0) | + (info->band ? FWCMD_H2C_IE_CAM_BAND : 0) | + (info->hit_en ? FWCMD_H2C_IE_CAM_HIT_FRWD_EN : 0) | + (info->miss_en ? + FWCMD_H2C_IE_CAM_MISS_FRWD_EN : 0) | + (info->rst ? FWCMD_H2C_IE_CAM_RST : 0) | + SET_WORD(info->port, FWCMD_H2C_IE_CAM_PORT) | + SET_WORD(info->hit_sel, FWCMD_H2C_IE_CAM_HIT_FRWD) | + SET_WORD(info->miss_sel, + FWCMD_H2C_IE_CAM_MISS_FRWD) | + SET_WORD(info->num, FWCMD_H2C_IE_CAM_UPD_NUM)); + + buf = h2cb_put(h2cb, info->buf_len); + if (!buf) { + ret = MACNOBUF; + return ret; + } + + PLTFM_MEMCPY(buf, info->buf, info->buf_len); + + return ret; +} + +#else +u32 __ie_cam_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + struct mac_ax_ie_cam_cmd_info *info) +{ + struct fwcmd_ie_cam *cmd; + u8 *buf; + u32 ret = MACSUCCESS; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ie_cam)); + if (!buf) { + ret = MACNOBUF; + return ret; + } + + cmd = (struct fwcmd_ie_cam *)buf; + cmd->dword0 = + cpu_to_le32((info->en ? FWCMD_H2C_IE_CAM_CAM_EN : 0) | + (info->band ? FWCMD_H2C_IE_CAM_BAND : 0) | + (info->hit_en ? FWCMD_H2C_IE_CAM_HIT_FRWD_EN : 0) | + (info->miss_en ? + FWCMD_H2C_IE_CAM_MISS_FRWD_EN : 0) | + (info->rst ? FWCMD_H2C_IE_CAM_RST : 0) | + SET_WORD(info->port, FWCMD_H2C_IE_CAM_PORT) | + SET_WORD(info->hit_sel, FWCMD_H2C_IE_CAM_HIT_FRWD) | + SET_WORD(info->miss_sel, + FWCMD_H2C_IE_CAM_MISS_FRWD) | + SET_WORD(info->num, FWCMD_H2C_IE_CAM_UPD_NUM)); + + buf = h2cb_put(h2cb, info->buf_len); + if (!buf) { + ret = MACNOBUF; + return ret; + } + + PLTFM_MEMCPY(buf, info->buf, info->buf_len); + + return ret; +} +#endif +u32 mac_ie_cam_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ie_cam_cmd_info *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u32 ret; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + ret = __ie_cam_set_cmd(adapter, h2cb, info); + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM set cmd fail %d\n", ret); + goto fail; + } + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_IE_CAM, + FWCMD_H2C_FUNC_IE_CAM, 0, 1); + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM set hdr fail %d\n", ret); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM build txd fail %d\n", ret); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM tx fail %d\n", ret); + goto fail; + } + +fail: + h2cb_free(adapter, h2cb); + + if (!ret) + h2c_end_flow(adapter); + + return ret; +} + +u32 _mac_send_h2creg(struct mac_ax_adapter *adapter, + struct mac_ax_h2creg_info *h2c) +{ +#define MAC_AX_H2CREG_CNT 100 +#define MAC_AX_H2CREG_US 200 + u32 cnt = MAC_AX_H2CREG_CNT; + u8 len, byte0, byte1, val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct fwcmd_h2creg h2creg; + + if (!h2c) + return MACSUCCESS; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("MAC is not ready\n"); + adapter->stats.h2c_reg_uninit++; + } + + do { + if (!(MAC_REG_R8(R_AX_H2CREG_CTRL) & B_AX_H2CREG_TRIGGER)) + break; + PLTFM_DELAY_US(MAC_AX_H2CREG_US); + cnt--; + } while (cnt); + + if (!cnt) { + PLTFM_MSG_ERR("FW does not process H2CREG\n"); + return MACPOLLTO; + } + + if (h2c->content_len > H2CREG_CONTENT_LEN) { + PLTFM_MSG_ERR("%s: h2creg len is TOO large\n", __func__); + return MACFUNCINPUT; + } + + len = h2c->content_len + H2CREG_HDR_LEN; + if ((h2c->content_len + H2CREG_HDR_LEN) & 3) + len = ((h2c->content_len + H2CREG_HDR_LEN) >> 2) + 1; + else + len = (h2c->content_len + H2CREG_HDR_LEN) >> 2; + + byte0 = (u8)GET_FIELD(h2c->h2c_content.dword0, FWCMD_H2CREG_BYTE2); + byte1 = (u8)GET_FIELD(h2c->h2c_content.dword0, FWCMD_H2CREG_BYTE3); + + h2creg.dword0 = SET_WORD(h2c->id, FWCMD_H2CREG_H2CREG_HDR_FUNC) | + SET_WORD(len, FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN) | + SET_WORD(byte0, FWCMD_H2CREG_BYTE2) | + SET_WORD(byte1, FWCMD_H2CREG_BYTE3); + + h2creg.dword1 = h2c->h2c_content.dword1; + h2creg.dword2 = h2c->h2c_content.dword2; + h2creg.dword3 = h2c->h2c_content.dword3; + + MAC_REG_W32(R_AX_H2CREG_DATA0, h2creg.dword0); + MAC_REG_W32(R_AX_H2CREG_DATA1, h2creg.dword1); + MAC_REG_W32(R_AX_H2CREG_DATA2, h2creg.dword2); + MAC_REG_W32(R_AX_H2CREG_DATA3, h2creg.dword3); + + val = MAC_REG_R8(R_AX_H2CREG_CTRL); + MAC_REG_W8(R_AX_H2CREG_CTRL, val | B_AX_H2CREG_TRIGGER); + + return MACSUCCESS; +} + +u32 mac_send_h2creg(struct mac_ax_adapter *adapter, u32 *content, u8 len) +{ +#define MAC_AX_H2CREG_PCNT 5 + u32 cnt = MAC_AX_H2CREG_PCNT; + u8 i; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("MAC is not ready\n"); + adapter->stats.h2c_reg_uninit++; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + do { + if (!MAC_REG_R8(R_AX_H2CREG_CTRL_V1)) + break; + PLTFM_DELAY_US(1000); + cnt--; + } while (cnt); + } else { + do { + if (!MAC_REG_R8(R_AX_H2CREG_CTRL)) + break; + PLTFM_DELAY_US(1000); + cnt--; + } while (cnt); + } + + if (!cnt) { + PLTFM_MSG_ERR("FW does not process H2CREG\n"); + return MACPOLLTO; + } + + for (i = 0; i < len; i++) + MAC_REG_W32(R_AX_H2CREG_DATA0 + i * 4, content[i]); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W8(R_AX_H2CREG_CTRL_V1, 1); + else + MAC_REG_W8(R_AX_H2CREG_CTRL, 1); + + return MACSUCCESS; +} + +u32 __recv_c2hreg(struct mac_ax_adapter *adapter, struct fwcmd_c2hreg *c2h) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + if (!(MAC_REG_R8(R_AX_C2HREG_CTRL_V1) & B_AX_C2HREG_TRIGGER)) + return MACC2HREGEMP; + + c2h->dword0 = MAC_REG_R32(R_AX_C2HREG_DATA0_V1); + c2h->dword1 = MAC_REG_R32(R_AX_C2HREG_DATA1_V1); + c2h->dword2 = MAC_REG_R32(R_AX_C2HREG_DATA2_V1); + c2h->dword3 = MAC_REG_R32(R_AX_C2HREG_DATA3_V1); + + val = MAC_REG_R8(R_AX_C2HREG_CTRL_V1); + MAC_REG_W8(R_AX_C2HREG_CTRL_V1, val & ~B_AX_C2HREG_TRIGGER); + } else { + if (!(MAC_REG_R8(R_AX_C2HREG_CTRL) & B_AX_C2HREG_TRIGGER)) + return MACC2HREGEMP; + + c2h->dword0 = MAC_REG_R32(R_AX_C2HREG_DATA0); + c2h->dword1 = MAC_REG_R32(R_AX_C2HREG_DATA1); + c2h->dword2 = MAC_REG_R32(R_AX_C2HREG_DATA2); + c2h->dword3 = MAC_REG_R32(R_AX_C2HREG_DATA3); + + val = MAC_REG_R8(R_AX_C2HREG_CTRL); + MAC_REG_W8(R_AX_C2HREG_CTRL, val & ~B_AX_C2HREG_TRIGGER); + } + + return MACSUCCESS; +} + +u32 _recv_c2hreg(struct mac_ax_adapter *adapter, u8 *buf) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 i; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + if (!(MAC_REG_R8(R_AX_C2HREG_CTRL_V1) & B_AX_C2HREG_TRIGGER)) + return MACC2HREGEMP; + } else { + if (!(MAC_REG_R8(R_AX_C2HREG_CTRL) & B_AX_C2HREG_TRIGGER)) + return MACC2HREGEMP; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + for (i = 0; i < C2HREG_LEN; i = i + 4) + *(u32 *)(buf + i) = MAC_REG_R32(R_AX_C2HREG_DATA0_V1 + i); + } else { + for (i = 0; i < C2HREG_LEN; i = i + 4) + *(u32 *)(buf + i) = MAC_REG_R32(R_AX_C2HREG_DATA0 + i); + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W8(R_AX_C2HREG_CTRL_V1, 0); + else + MAC_REG_W8(R_AX_C2HREG_CTRL, 0); + + return MACSUCCESS; +} + +u32 mac_process_c2hreg(struct mac_ax_adapter *adapter, + struct mac_ax_c2hreg_info *info) +{ + u32 ret; + struct fwcmd_c2hreg_hdr *hdr; + + info->id = FWCMD_C2H_FUNC_NULL; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("MAC is not ready\n"); + adapter->stats.c2h_reg_uninit++; + } + + ret = _recv_c2hreg(adapter, info->c2hreg); + if (ret == MACC2HREGEMP) { + return ret; + } else if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]Get C2H REG fail %d\n", ret); + return ret; + } + + hdr = (struct fwcmd_c2hreg_hdr *)info->c2hreg; + info->id = GET_FIELD(hdr->dword0, FWCMD_C2HREG_C2HREG_HDR_FUNC); + info->content = info->c2hreg + C2HREG_HDR_LEN; + info->content_len = GET_FIELD(hdr->dword0, + FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN); + info->content_len = (info->content_len << 2) - C2HREG_HDR_LEN; + + return MACSUCCESS; +} + +u32 mac_recv_c2hreg(struct mac_ax_adapter *adapter, + struct mac_ax_c2hreg_cont *cont) +{ + u32 ret; + + cont->id = FWCMD_C2H_FUNC_NULL; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) { + PLTFM_MSG_TRACE("MAC is not ready\n"); + adapter->stats.c2h_reg_uninit++; + } + + ret = __recv_c2hreg(adapter, &cont->c2h_content); + if (ret == MACC2HREGEMP) { + return ret; + } else if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]Get C2H REG fail %d\n", ret); + return ret; + } + + cont->id = GET_FIELD(cont->c2h_content.dword0, + FWCMD_C2HREG_C2HREG_HDR_FUNC); + cont->content_len = GET_FIELD(cont->c2h_content.dword0, + FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN); + cont->content_len = (cont->content_len << 2) - C2HREG_HDR_LEN; + + return MACSUCCESS; +} + +u32 mac_notify_fw_dbcc(struct mac_ax_adapter *adapter, u8 en) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u32 ret; + struct fwcmd_notify_dbcc *dbcc; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + dbcc = (struct fwcmd_notify_dbcc *) + h2cb_put(h2cb, sizeof(struct fwcmd_notify_dbcc)); + if (!dbcc) { + ret = MACNPTR; + PLTFM_MSG_ERR("%s: h2c put fail\n", __func__); + goto fail; + } + + dbcc->dword0 = en ? FWCMD_H2C_NOTIFY_DBCC_EN : 0; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_NOTIFY_DBCC, 0, 0); + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM set hdr fail %d\n", ret); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM build txd fail %d\n", ret); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("H2C IE CAM tx fail %d\n", ret); + goto fail; + } + +fail: + h2cb_free(adapter, h2cb); + + if (!ret) + h2c_end_flow(adapter); + + return ret; +} + +u32 poll_c2hreg(struct mac_ax_adapter *adapter, + struct mac_ax_c2hreg_poll *c2h) +{ + u32 cnt, poll_us, ret; + struct mac_ax_c2hreg_cont *c2hreg_cont; + struct mac_ax_drv_stats *drv_stats = &adapter->drv_stats; + + if (!c2h) + return MACSUCCESS; + + cnt = c2h->retry_cnt; + poll_us = c2h->retry_wait_us; + c2hreg_cont = &c2h->c2hreg_cont; + do { + ret = mac_recv_c2hreg(adapter, c2hreg_cont); + if (cnt == 0 || ret == MACSUCCESS) + break; + + if (drv_stats->drv_rm) { + PLTFM_MSG_ERR("%s: driver removed\n", __func__); + return MACDRVRM; + } + + if (ret != MACSUCCESS) { + if (ret == MACC2HREGEMP) { + PLTFM_DELAY_US(poll_us); + cnt--; + } else { + PLTFM_MSG_ERR("%s: c2hreg fail\n", __func__); + return ret; + } + } + } while (cnt); + + PLTFM_MSG_TRACE("%s: cnt = %d, us = %d\n", + __func__, cnt, poll_us); + + if (ret == MACSUCCESS) { + if (c2h->polling_id != FWCMD_C2H_FUNC_NULL && + c2h->polling_id != c2hreg_cont->id) { + PLTFM_MSG_ERR("%s: surprised c2h\n", __func__); + PLTFM_MSG_ERR("rev: %x\n", c2h->polling_id); + PLTFM_MSG_ERR("exp: %x\n", c2hreg_cont->id); + ret = MACBADC2HREG; + } + } else { + PLTFM_MSG_ERR("%s: polling c2hreg timeout\n", __func__); + } + + return ret; +} + +u32 proc_msg_reg(struct mac_ax_adapter *adapter, + struct mac_ax_h2creg_info *h2c, + struct mac_ax_c2hreg_poll *c2h) +{ + struct mac_ax_dbgpkg_en en = {0}; + u32 ret = MACSUCCESS; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_ERR("FW is not ready\n"); + return MACFWNONRDY; + } + + PLTFM_MUTEX_LOCK(&adapter->fw_info.msg_reg); + + ret = _mac_send_h2creg(adapter, h2c); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: send h2c reg fail: %d\n", __func__, ret); + goto END; + } + + ret = poll_c2hreg(adapter, c2h); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: poll c2h reg fail: %d\n", __func__, ret); + +END: + PLTFM_MUTEX_UNLOCK(&adapter->fw_info.msg_reg); + if (ret != MACSUCCESS) { + en.plersvd_dbg = 1; + mac_dbg_status_dump(adapter, NULL, &en); + } + return ret; +} + +static u32 get_wps_rpt_event_id(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info) +{ + struct fwcmd_wps_rpt *rpt = (struct fwcmd_wps_rpt *)c2h->content; + u32 state, val; + + val = le32_to_cpu(rpt->dword0); + state = GET_FIELD(val, FWCMD_C2H_WPS_RPT_STATE); + + if (!state) + *id = MSG_EVT_WPS_RELEASED; + else + *id = MSG_EVT_WPS_PRESSED; + + return MACSUCCESS; +} + +static u32 get_bcn_resend_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info) +{ + *id = MSG_EVT_BCN_RESEND; + + return MACSUCCESS; +} + +static u32 get_tsf32_togl_rpt_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info) +{ + *id = MSG_EVT_TSF32_TOG; + + return MACSUCCESS; +} + +static u32 get_fw_rx_dbg_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info) +{ + *id = MSG_EVT_DBG_RX_DUMP; + + return MACSUCCESS; +} + +static struct c2h_event_id_proc event_proc[] = { + /* cat, class, func, hdl */ + {FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_MISC, + FWCMD_C2H_FUNC_WPS_RPT, get_wps_rpt_event_id}, + {FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_OFLD, + FWCMD_C2H_FUNC_BEACON_RESEND, get_bcn_resend_event}, + {FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_OFLD, + FWCMD_C2H_FUNC_TSF32_TOGL_RPT, get_tsf32_togl_rpt_event}, + {FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_MISC, + FWCMD_C2H_FUNC_CCXRPT, get_ccxrpt_event}, + {FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_DBG, + FWCMD_C2H_FUNC_RX_DBG, get_fw_rx_dbg_event}, + {FWCMD_C2H_CAT_NULL, FWCMD_C2H_CL_NULL, + FWCMD_C2H_FUNC_NULL, NULL}, +}; + +u32 mac_get_c2h_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info) +{ + struct c2h_event_id_proc *proc; + u32 (*hdl)(struct mac_ax_adapter *adapter, struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, u8 *c2h_info) = NULL; + + /*for C2H ack bit no need to process*/ + if (c2h->type_done_ack == 1 || c2h->type_rec_ack == 1) + return MACSUCCESS; + + proc = event_proc; + while (proc->cat != FWCMD_C2H_CAT_NULL) { + if (proc->cat == c2h->c2h_cat && + proc->cls == c2h->c2h_class && + proc->func == c2h->c2h_func) { + hdl = proc->hdl; + return hdl(adapter, c2h, id, c2h_info); + } + proc++; + } + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/fwcmd.h b/phl/hal_g6/mac/mac_ax/fwcmd.h new file mode 100644 index 0000000..4b93c66 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwcmd.h @@ -0,0 +1,849 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FW_CMD_H_ +#define _MAC_AX_FW_CMD_H_ + +#include "../type.h" +#include "../fw_ax/inc_hdr/fwcmd_intf.h" +#include "fwcmd_intf_f2p.h" +#include "trx_desc.h" +#include "fwofld.h" +#include "p2p.h" +#include "flash.h" +#include "dbg_cmd.h" + +#define FWCMD_HDR_LEN 8 +#define C2HREG_HDR_LEN 2 +#define H2CREG_HDR_LEN 2 +#define C2HREG_CONTENT_LEN 14 +#define H2CREG_CONTENT_LEN 14 +#define C2HREG_LEN (C2HREG_HDR_LEN + C2HREG_CONTENT_LEN) +#define H2CREG_LEN (H2CREG_HDR_LEN + H2CREG_CONTENT_LEN) + +#define H2C_CMD_LEN 64 +#define H2C_DATA_LEN 256 +#define H2C_LONG_DATA_LEN 2048 + +#define SET_FWCMD_ID(_t, _ca, _cl, _f) \ + (SET_WORD(_t, H2C_HDR_DEL_TYPE) | SET_WORD(_ca, H2C_HDR_CAT) | \ + SET_WORD(_cl, H2C_HDR_CLASS) | SET_WORD(_f, H2C_HDR_FUNC)) +#define GET_FWCMD_TYPE(id) (GET_FIELD(id, C2H_HDR_DEL_TYPE)) +#define GET_FWCMD_CAT(id) (GET_FIELD(id, C2H_HDR_CAT)) +#define GET_FWCMD_CLASS(id) (GET_FIELD(id, C2H_HDR_CLASS)) +#define GET_FWCMD_FUNC(id) (GET_FIELD(id, C2H_HDR_FUNC)) + +#define FWCMD_TYPE_H2C 0 +#define FWCMD_TYPE_C2H 1 + +#define FWCMD_C2H_CL_NULL 0xFF +#define FWCMD_C2H_FUNC_NULL 0xFF +#define FWCMD_C2H_CAT_NULL 0xFF + +/** + * @struct h2c_buf_head + * @brief h2c_buf_head + * + * @var h2c_buf_head::next + * Please Place Description here. + * @var h2c_buf_head::prev + * Please Place Description here. + * @var h2c_buf_head::pool + * Please Place Description here. + * @var h2c_buf_head::size + * Please Place Description here. + * @var h2c_buf_head::qlen + * Please Place Description here. + * @var h2c_buf_head::suspend + * Please Place Description here. + * @var h2c_buf_head::lock + * Please Place Description here. + */ +struct h2c_buf_head { + /* keep first */ + struct h2c_buf *next; + struct h2c_buf *prev; + u8 *pool; + u32 size; + u32 qlen; + u8 suspend; + mac_ax_mutex lock; +}; + +/** + * @struct fwcmd_wkb_head + * @brief fwcmd_wkb_head + * + * @var fwcmd_wkb_head::next + * Please Place Description here. + * @var fwcmd_wkb_head::prev + * Please Place Description here. + * @var fwcmd_wkb_head::qlen + * Please Place Description here. + * @var fwcmd_wkb_head::lock + * Please Place Description here. + */ +struct fwcmd_wkb_head { + /* keep first */ + struct h2c_buf *next; + struct h2c_buf *prev; + u32 qlen; + mac_ax_mutex lock; +}; + +/** + * @struct h2c_buf + * @brief h2c_buf + * + * @var h2c_buf::next + * Please Place Description here. + * @var h2c_buf::prev + * Please Place Description here. + * @var h2c_buf::_class_ + * Please Place Description here. + * @var h2c_buf::id + * Please Place Description here. + * @var h2c_buf::master + * Please Place Description here. + * @var h2c_buf::len + * Please Place Description here. + * @var h2c_buf::head + * Please Place Description here. + * @var h2c_buf::end + * Please Place Description here. + * @var h2c_buf::data + * Please Place Description here. + * @var h2c_buf::tail + * Please Place Description here. + * @var h2c_buf::hdr_len + * Please Place Description here. + * @var h2c_buf::flags + * Please Place Description here. + * @var h2c_buf::h2c_seq + * Please Place Description here. + */ +struct h2c_buf { + /* keep first */ + struct h2c_buf *next; + struct h2c_buf *prev; + enum h2c_buf_class _class_; + u32 id; + u8 master; + u32 len; + u8 *head; + u8 *end; + u8 *data; + u8 *tail; + u32 hdr_len; +#define H2CB_FLAGS_FREED BIT(0) + u32 flags; + u8 h2c_seq; +}; + +/** + * @struct c2h_proc_class + * @brief c2h_proc_class + * + * @var c2h_proc_class::id + * Please Place Description here. + * @var c2h_proc_class::handler + * Please Place Description here. + */ +struct c2h_proc_class { + u16 id; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); +}; + +struct fw_status_proc_class { + u16 id; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len); +}; + +/** + * @struct c2h_proc_func + * @brief c2h_proc_func + * + * @var c2h_proc_func::id + * Please Place Description here. + * @var c2h_proc_func::handler + * Please Place Description here. + */ +struct c2h_proc_func { + u16 id; + u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + struct rtw_c2h_info *info); +}; + +/** + * @struct mac_ax_c2hreg_info + * @brief mac_ax_c2hreg_info + * + * @var mac_ax_c2hreg_info::id + * Please Place Description here. + * @var mac_ax_c2hreg_info::total_len + * Please Place Description here. + * @var mac_ax_c2hreg_info::content + * Please Place Description here. + * @var mac_ax_c2hreg_info::c2hreg + * Please Place Description here. + */ + +struct mac_ax_c2hreg_info { + u8 id; + u8 content_len; + u8 *content; + u8 c2hreg[C2HREG_LEN]; +}; + +struct mac_ax_c2hreg_cont { + u8 id; + u8 content_len; + struct fwcmd_c2hreg c2h_content; +}; + +struct mac_ax_c2hreg_poll { + u8 polling_id; + u32 retry_cnt; + u32 retry_wait_us; + struct mac_ax_c2hreg_cont c2hreg_cont; +}; + +struct mac_ax_h2creg_info { + u8 id; + u8 content_len; + struct fwcmd_h2creg h2c_content; +}; + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ +/** + * @brief h2cb_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 h2cb_init(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_exit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 h2cb_exit(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_alloc + * + * @param *adapter + * @param buf_class + * @return Please Place Description here. + * @retval rtw_h2c_pkt + */ +#if MAC_AX_PHL_H2C +struct rtw_h2c_pkt *h2cb_alloc(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_free + * + * @param *adapter + * @param *h2cb + * @return Please Place Description here. + * @retval void + */ +void h2cb_free(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_push + * + * @param *h2cb + * @param len + * @return Please Place Description here. + * @retval u8 + */ +u8 *h2cb_push(struct rtw_h2c_pkt *h2cb, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_pull + * + * @param *h2cb + * @param len + * @return Please Place Description here. + * @retval u8 + */ +u8 *h2cb_pull(struct rtw_h2c_pkt *h2cb, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_put + * + * @param *h2cb + * @param len + * @return Please Place Description here. + * @retval u8 + */ +u8 *h2cb_put(struct rtw_h2c_pkt *h2cb, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2c_pkt_set_hdr + * + * @param *adapter + * @param *h2cb + * @param type + * @param cat + * @param _class_ + * @param func + * @param rack + * @param dack + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb, + u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2c_pkt_set_hdr_fwdl + * + * @param *adapter + * @param *h2cb + * @param type + * @param cat + * @param _class_ + * @param func + * @param rack + * @param dack + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter, + struct rtw_h2c_pkt *h2cb, u8 type, u8 cat, u8 _class_, + u8 func, u16 rack, u16 dack); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2c_pkt_set_cmd + * + * @param *adapter + * @param *h2cb + * @param *cmd + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb, + u8 *cmd, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2c_agg_enqueue + * + * @param *adapter + * @param *h2cb + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb); +/** + * @} + * @} + */ + +/** + * @brief h2c_pkt_build_txd + * + * @param *adapter + * @param *h2cb + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2cb_alloc + * + * @param *adapter + * @param buf_class + * @return Please Place Description here. + * @retval h2c_buf + */ +#else +struct h2c_buf *h2cb_alloc(struct mac_ax_adapter *adapter, + enum h2c_buf_class buf_class); +/** + * @} + * @} + */ +void h2cb_free(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb); +u8 *h2cb_push(struct h2c_buf *h2cb, u32 len); +u8 *h2cb_pull(struct h2c_buf *h2cb, u32 len); +u8 *h2cb_put(struct h2c_buf *h2cb, u32 len); +u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack); +u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + u8 type, u8 cat, u8 _class_, u8 func, u16 rack, + u16 dack); +u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb, + u8 *cmd, u32 len); +u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb); +u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, h2c_buf *h2cb); + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief fwcmd_wq_enqueue + * + * @param *adapter + * @param *h2cb + * @return Please Place Description here. + * @retval u32 + */ +#endif +u32 fwcmd_wq_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief fwcmd_wq_dequeue + * + * @param *adapter + * @param id + * @return Please Place Description here. + * @retval h2c_buf + */ +struct h2c_buf *fwcmd_wq_dequeue(struct mac_ax_adapter *adapter, u32 id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief fwcmd_wq_idle + * + * @param *adapter + * @param id + * @return Please Place Description here. + * @retval u32 + */ +u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup C2H + * @{ + */ + +/** + * @brief mac_process_c2h + * + * @param *adapter + * @param *buf + * @param len + * @param *ret + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_process_c2h(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + u8 *ret); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup C2H + * @{ + */ + +/** + * @brief c2h_field_parsing + * + * @param *hdr + * @param *info + * @return Please Place Description here. + * @retval u8 + */ +u8 c2h_field_parsing(struct fwcmd_hdr *hdr, struct rtw_c2h_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup C2H + * @{ + */ + +/** + * @brief mac_fw_log_cfg + * + * @param *adapter + * @param *log_cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fw_log_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_fw_log *log_cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup Beacon + * @{ + */ + +/** + * @brief mac_send_bcn_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_send_bcn_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_bcn_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief mac_host_getpkt_h2c + * + * @param *adapter + * @param macid + * @param pkttype + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_host_getpkt_h2c(struct mac_ax_adapter *adapter, u8 macid, u8 pkttype); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief mac_outsrc_h2c_common + * + * @param *adapter + * @param *hdr + * @param *pvalue + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_outsrc_h2c_common(struct mac_ax_adapter *adapter, + struct rtw_g6_h2c_hdr *hdr, u32 *pvalue); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup Beacon + * @{ + */ + +/** + * @brief mac_ie_cam_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ie_cam_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ie_cam_cmd_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief h2c_end_flow + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 h2c_end_flow(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup H2C + * @{ + */ + +/** + * @brief mac_send_h2creg + * + * @param *adapter + * @param *content + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_send_h2creg(struct mac_ax_adapter *adapter, u32 *content, u8 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup C2H + * @{ + */ + +/** + * @brief mac_process_c2hreg + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_process_c2hreg(struct mac_ax_adapter *adapter, + struct mac_ax_c2hreg_info *info); +/** + * @} + * @} + */ + +u32 proc_msg_reg(struct mac_ax_adapter *adapter, + struct mac_ax_h2creg_info *h2c, + struct mac_ax_c2hreg_poll *c2h); + +/** + * @addtogroup Firmware + * @{ + * @addtogroup C2H + * @{ + */ + +/** + * @brief mac_get_c2h_event + * + * Get the phl_msg_evt_id from C2H packet + * + * @param *adapter + * @param *c2h + * @param *id + * @return Return 0 when getting event ID successfully. + * @retval u32 + */ + +u32 mac_get_c2h_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info); + +/** + * @} + * @} + */ + +u32 mac_notify_fw_dbcc(struct mac_ax_adapter *adapter, u8 en); + +#endif + diff --git a/phl/hal_g6/mac/mac_ax/fwcmd_intf_f2p.h b/phl/hal_g6/mac/mac_ax/fwcmd_intf_f2p.h new file mode 100644 index 0000000..ee44745 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwcmd_intf_f2p.h @@ -0,0 +1,519 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + + #ifndef _MAC_AX_FWCMD_INTF_F2P_H_ +#define _MAC_AX_FWCMD_INTF_F2P_H_ + +/* f2p test cmd para*/ +#define FWCMD_F2PTEST_ULBW_SH 0 +#define FWCMD_F2PTEST_ULBW_MSK 0x3 +#define FWCMD_F2PTEST_GILTF_SH 2 +#define FWCMD_F2PTEST_GILTF_MSK 0x3 +#define FWCMD_F2PTEST_NUMLTF_SH 4 +#define FWCMD_F2PTEST_NUMLTF_MSK 0x7 +#define FWCMD_F2PTEST_ULSTBC_SH 7 +#define FWCMD_F2PTEST_ULSTBC_MSK 0x1 +#define FWCMD_F2PTEST_DPLR_SH 8 +#define FWCMD_F2PTEST_DPLR_MSK 0x1 +#define FWCMD_F2PTEST_TXPWR_SH 9 +#define FWCMD_F2PTEST_TXPWR_MSK 0x3F +#define FWCMD_F2PTEST_USERNUM_SH 16 +#define FWCMD_F2PTEST_USERNUM_MSK 0x7 +#define FWCMD_F2PTEST_PKTNUM_SH 19 +#define FWCMD_F2PTEST_PKTNUM_MSK 0x7 +#define FWCMD_F2PTEST_BITMAP_SH 24 +#define FWCMD_F2PTEST_BITMAP_MSK 0xFF + +#define FWCMD_F2PTEST_AID12_SH 0 +#define FWCMD_F2PTEST_AID12_MSK 0xFFF +#define FWCMD_F2PTEST_ULMCS_SH 12 +#define FWCMD_F2PTEST_ULMCS_MSK 0xF +#define FWCMD_F2PTEST_MACID_SH 16 +#define FWCMD_F2PTEST_MACID_MSK 0xFF +#define FWCMD_F2PTEST_RUPOS_SH 24 +#define FWCMD_F2PTEST_RUPOS_MSK 0xFF + +#define FWCMD_F2PTEST_ULFEC_SH 0 +#define FWCMD_F2PTEST_ULFEC_MSK 0x1 +#define FWCMD_F2PTEST_ULDCM_SH 1 +#define FWCMD_F2PTEST_ULDCM_MSK 0x1 +#define FWCMD_F2PTEST_SS_ALLOC_SH 2 +#define FWCMD_F2PTEST_SS_ALLOC_MSK 0x3F +#define FWCMD_F2PTEST_UL_TGTRSSI_SH 8 +#define FWCMD_F2PTEST_UL_TGTRSSI_MSK 0x7F + +#define FWCMD_F2PTEST_PREF_AC_SH 0 +#define FWCMD_F2PTEST_PREF_AC_MSK 0x3 + +#define FWCMD_F2PTEST_DATARATE_SH 0 +#define FWCMD_F2PTEST_DATARATE_MSK 0x1FF +#define FWCMD_F2PTEST_MULPORT_SH 9 +#define FWCMD_F2PTEST_MULPORT_MSK 0x7 +#define FWCMD_F2PTEST_PWR_OFSET_SH 12 +#define FWCMD_F2PTEST_PWR_OFSET_MSK 0x7 +#define FWCMD_F2PTEST_MODE_SH 16 +#define FWCMD_F2PTEST_MODE_MSK 0x3 +#define FWCMD_F2PTEST_TYPE_SH 18 +#define FWCMD_F2PTEST_TYPE_MSK 0x3F +#define FWCMD_F2PTEST_SIGB_LEN_SH 24 +#define FWCMD_F2PTEST_SIGB_LEN_MSK 0xFF + +#define FWCMD_F2PTEST_TXCMD_ADDR_SH 0 +#define FWCMD_F2PTEST_TXCMD_ADDR_MSK 0xFF +#define FWCMD_F2PTEST_SIGB_ADDR_SH 8 +#define FWCMD_F2PTEST_SIGB_ADDR_MSK 0xFF + +/* f2p_wd*/ +/* dword0 */ +#define F2P_WD_CMD_QSEL_SH 0 +#define F2P_WD_CMD_QSEL_MSK 0x3f +#define F2P_WD_LS BIT(10) +#define F2P_WD_FS BIT(11) +#define F2P_WD_TOTAL_NUMBER_SH 12 +#define F2P_WD_TOTAL_NUMBER_MSK 0xf +#define F2P_WD_SEQ_SH 16 +#define F2P_WD_SEQ_MSK 0xff +#define F2P_WD_LENGTH_SH 24 +#define F2P_WD_LENGTH_MSK 0xff + +/* f2p_tx_cmd*/ +/* dword0 */ +#define F2P_CMD_TYPE_SH 0 +#define F2P_CMD_TYPE_MSK 0xff +#define F2P_CMD_SUB_TYPE_SH 8 +#define F2P_CMD_SUB_TYPE_MSK 0xff +#define F2P_DL_USER_NUM_SH 16 +#define F2P_DL_USER_NUM_MSK 0x1f +#define F2P_BW_SH 21 +#define F2P_BW_MSK 0x3 +#define F2P_TX_POWER_SH 23 +#define F2P_TX_POWER_MSK 0x1ff + +/* dword1 */ +#define F2P_FW_DEFINE_SH 0 +#define F2P_FW_DEFINE_MSK 0xffff +#define F2P_SS_SEL_MODE_SH 16 +#define F2P_SS_SEL_MODE_MSK 0x3 +#define F2P_NEXT_QSEL_SH 18 +#define F2P_NEXT_QSEL_MSK 0x3f +#define F2P_TWT_GROUP_SH 24 +#define F2P_TWT_GROUP_MSK 0xf +#define F2P_DIS_CHK_SLP BIT(28) +#define F2P_RU_MU_2_SU BIT(29) +#define F2P_DL_T_PE_SH 30 +#define F2P_DL_T_PE_MSK 0x3 + +/* dword2 */ +#define F2P_SIGB_CH1_LEN_SH 0 +#define F2P_SIGB_CH1_LEN_MSK 0xff +#define F2P_SIGB_CH2_LEN_SH 8 +#define F2P_SIGB_CH2_LEN_MSK 0xff +#define F2P_SIGB_SYM_NUM_SH 16 +#define F2P_SIGB_SYM_NUM_MSK 0x3f +#define F2P_SIGB_CH2_OFS_SH 22 +#define F2P_SIGB_CH2_OFS_MSK 0x1f +#define F2P_DIS_HTP_ACK BIT(27) +#define F2P_TX_TIME_REF_SH 28 +#define F2P_TX_TIME_REF_MSK 0x3 +#define F2P_PRI_USER_IDX_SH 30 +#define F2P_PRI_USER_IDX_MSK 0x3 + +/* dword3 */ +#define F2P_AMPDU_MAX_TXTIME_SH 0 +#define F2P_AMPDU_MAX_TXTIME_MSK 0x3fff +#define F2P_GROUP_ID_SH 16 +#define F2P_GROUP_ID_MSK 0x3f +#define F2P_TWT_CHK_EN BIT(28) +#define F2P_TWT_PORT_ID_SH 29 +#define F2P_TWT_PORT_ID_MSK 0x7 + +/* dword4 */ +#define F2P_TWT_START_TIME_SH 0 +#define F2P_TWT_START_TIME_MSK 0xffffffff + +/* dword5 */ +#define F2P_TWT_END_TIME_SH 0 +#define F2P_TWT_END_TIME_MSK 0xffffffff + +/* dword6 */ +#define F2P_APEP_LEN_SH 0 +#define F2P_APEP_LEN_MSK 0xfff +#define F2P_TRI_PAD_SH 12 +#define F2P_TRI_PAD_MSK 0x3 +#define F2P_UL_T_PE_SH 14 +#define F2P_UL_T_PE_MSK 0x3 +#define F2P_RF_GAIN_IDX_SH 16 +#define F2P_RF_GAIN_IDX_MSK 0x3ff +#define F2P_FIXED_GAIN_EN BIT(26) +#define F2P_UL_GI_LTF_SH 27 +#define F2P_UL_GI_LTF_MSK 0x7 +#define F2P_UL_DOPPLER BIT(30) +#define F2P_UL_STBC BIT(31) + +/* dword7 */ +#define F2P_UL_MID_PER BIT(0) +#define F2P_UL_CQI_RRP_TRI BIT(1) +#define F2P_SIGB_DCM BIT(16) +#define F2P_SIGB_COMP BIT(17) +#define F2P_DOPPLER BIT(18) +#define F2P_STBC BIT(19) +#define F2P_MID_PER BIT(20) +#define F2P_GI_LTF_SIZE_SH 21 +#define F2P_GI_LTF_SIZE_MSK 0x7 +#define F2P_SIGB_MCS_SH 24 +#define F2P_SIGB_MCS_MSK 0x7 + +/* dword8 */ +#define F2P_MACID_U0_SH 0 +#define F2P_MACID_U0_MSK 0xff +#define F2P_AC_TYPE_U0_SH 8 +#define F2P_AC_TYPE_U0_MSK 0x3 +#define F2P_MU_STA_POS_U0_SH 10 +#define F2P_MU_STA_POS_U0_MSK 0x3 +#define F2P_DL_RATE_IDX_U0_SH 12 +#define F2P_DL_RATE_IDX_U0_MSK 0x1ff +#define F2P_TX_CMD_DL_DCM_EN_U0 BIT(21) +#define F2P_RU_ALO_IDX_U0_SH 24 +#define F2P_RU_ALO_IDX_U0_MSK 0xff + +/* dword9 */ +#define F2P_PWR_BOOST_U0_SH 0 +#define F2P_PWR_BOOST_U0_MSK 0x1f +#define F2P_AGG_BMP_ALO_U0_SH 5 +#define F2P_AGG_BMP_ALO_U0_MSK 0x7 +#define F2P_AMPDU_MAX_NUM_U0_SH 8 +#define F2P_AMPDU_MAX_NUM_U0_MSK 0xff +#define F2P_USER_DEFINE_U0_SH 16 +#define F2P_USER_DEFINE_U0_MSK 0xff +#define F2P_USER_DEFINE_EXT_U0_SH 24 +#define F2P_USER_DEFINE_EXT_U0_MSK 0xff + +/* dword10 */ +#define F2P_UL_ADDR_IDX_U0_SH 0 +#define F2P_UL_ADDR_IDX_U0_MSK 0xff +#define F2P_UL_DCM_U0 BIT(8) +#define F2P_UL_FEC_COD_U0 BIT(9) +#define F2P_UL_RU_RATE_U0_SH 10 +#define F2P_UL_RU_RATE_U0_MSK 0x7f +#define F2P_UL_RU_ALO_IDX_U0_SH 24 +#define F2P_UL_RU_ALO_IDX_U0_MSK 0xff + +/* dword11 */ + +/* dword12 */ +#define F2P_MACID_U1_SH 0 +#define F2P_MACID_U1_MSK 0xff +#define F2P_AC_TYPE_U1_SH 8 +#define F2P_AC_TYPE_U1_MSK 0x3 +#define F2P_MU_STA_POS_U1_SH 10 +#define F2P_MU_STA_POS_U1_MSK 0x3 +#define F2P_DL_RATE_IDX_U1_SH 12 +#define F2P_DL_RATE_IDX_U1_MSK 0x1ff +#define F2P_TX_CMD_DL_DCM_EN_U1 BIT(21) +#define F2P_RU_ALO_IDX_U1_SH 24 +#define F2P_RU_ALO_IDX_U1_MSK 0xff + +/* dword13 */ +#define F2P_PWR_BOOST_U1_SH 0 +#define F2P_PWR_BOOST_U1_MSK 0x1f +#define F2P_AGG_BMP_ALO_U1_SH 5 +#define F2P_AGG_BMP_ALO_U1_MSK 0x7 +#define F2P_AMPDU_MAX_NUM_U1_SH 8 +#define F2P_AMPDU_MAX_NUM_U1_MSK 0xff +#define F2P_USER_DEFINE_U1_SH 16 +#define F2P_USER_DEFINE_U1_MSK 0xff +#define F2P_USER_DEFINE_EXT_U1_SH 24 +#define F2P_USER_DEFINE_EXT_U1_MSK 0xff + +/* dword14 */ +#define F2P_UL_ADDR_IDX_U1_SH 0 +#define F2P_UL_ADDR_IDX_U1_MSK 0xff +#define F2P_UL_DCM_U1 BIT(8) +#define F2P_UL_FEC_COD_U1 BIT(9) +#define F2P_UL_RU_RATE_U1_SH 10 +#define F2P_UL_RU_RATE_U1_MSK 0x7f +#define F2P_UL_RU_ALO_IDX_U1_SH 24 +#define F2P_UL_RU_ALO_IDX_U1_MSK 0xff + +/* dword15 */ + +/* dword16 */ +#define F2P_MACID_U2_SH 0 +#define F2P_MACID_U2_MSK 0xff +#define F2P_AC_TYPE_U2_SH 8 +#define F2P_AC_TYPE_U2_MSK 0x3 +#define F2P_MU_STA_POS_U2_SH 10 +#define F2P_MU_STA_POS_U2_MSK 0x3 +#define F2P_DL_RATE_IDX_U2_SH 12 +#define F2P_DL_RATE_IDX_U2_MSK 0x1ff +#define F2P_TX_CMD_DL_DCM_EN_U2 BIT(21) +#define F2P_RU_ALO_IDX_U2_SH 24 +#define F2P_RU_ALO_IDX_U2_MSK 0xff + +/* dword17 */ +#define F2P_PWR_BOOST_U2_SH 0 +#define F2P_PWR_BOOST_U2_MSK 0x1f +#define F2P_AGG_BMP_ALO_U2_SH 5 +#define F2P_AGG_BMP_ALO_U2_MSK 0x7 +#define F2P_AMPDU_MAX_NUM_U2_SH 8 +#define F2P_AMPDU_MAX_NUM_U2_MSK 0xff +#define F2P_USER_DEFINE_U2_SH 16 +#define F2P_USER_DEFINE_U2_MSK 0xff +#define F2P_USER_DEFINE_EXT_U2_SH 24 +#define F2P_USER_DEFINE_EXT_U2_MSK 0xff + +/* dword18 */ +#define F2P_UL_ADDR_IDX_U2_SH 0 +#define F2P_UL_ADDR_IDX_U2_MSK 0xff +#define F2P_UL_DCM_U2 BIT(8) +#define F2P_UL_FEC_COD_U2 BIT(9) +#define F2P_UL_RU_RATE_U2_SH 10 +#define F2P_UL_RU_RATE_U2_MSK 0x7f +#define F2P_UL_RU_ALO_IDX_U2_SH 24 +#define F2P_UL_RU_ALO_IDX_U2_MSK 0xff + +/* dword19 */ + +/* dword20 */ +#define F2P_MACID_U3_SH 0 +#define F2P_MACID_U3_MSK 0xff +#define F2P_AC_TYPE_U3_SH 8 +#define F2P_AC_TYPE_U3_MSK 0x3 +#define F2P_MU_STA_POS_U3_SH 10 +#define F2P_MU_STA_POS_U3_MSK 0x3 +#define F2P_DL_RATE_IDX_U3_SH 12 +#define F2P_DL_RATE_IDX_U3_MSK 0x1ff +#define F2P_TX_CMD_DL_DCM_EN_U3 BIT(21) +#define F2P_RU_ALO_IDX_U3_SH 24 +#define F2P_RU_ALO_IDX_U3_MSK 0xff + +/* dword21 */ +#define F2P_PWR_BOOST_U3_SH 0 +#define F2P_PWR_BOOST_U3_MSK 0x1f +#define F2P_AGG_BMP_ALO_U3_SH 5 +#define F2P_AGG_BMP_ALO_U3_MSK 0x7 +#define F2P_AMPDU_MAX_NUM_U3_SH 8 +#define F2P_AMPDU_MAX_NUM_U3_MSK 0xff +#define F2P_USER_DEFINE_U3_SH 16 +#define F2P_USER_DEFINE_U3_MSK 0xff +#define F2P_USER_DEFINE_EXT_U3_SH 24 +#define F2P_USER_DEFINE_EXT_U3_MSK 0xff + +/* dword22 */ +#define F2P_UL_ADDR_IDX_U3_SH 0 +#define F2P_UL_ADDR_IDX_U3_MSK 0xff +#define F2P_UL_DCM_U3 BIT(8) +#define F2P_UL_FEC_COD_U3 BIT(9) +#define F2P_UL_RU_RATE_U3_SH 10 +#define F2P_UL_RU_RATE_U3_MSK 0x7f +#define F2P_UL_RU_ALO_IDX_U3_SH 24 +#define F2P_UL_RU_ALO_IDX_U3_MSK 0xff + +/* dword23 */ + +/* dword24 */ +#define F2P_PKT_ID_0_SH 0 +#define F2P_PKT_ID_0_MSK 0xfff +#define F2P_VALID_0 BIT(15) +#define F2P_UL_USER_NUM_0_SH 16 +#define F2P_UL_USER_NUM_0_MSK 0xf + +/* dword25 */ +#define F2P_PKT_ID_1_SH 0 +#define F2P_PKT_ID_1_MSK 0xfff +#define F2P_VALID_1 BIT(15) +#define F2P_UL_USER_NUM_1_SH 16 +#define F2P_UL_USER_NUM_1_MSK 0xf + +/* dword26 */ +#define F2P_PKT_ID_2_SH 0 +#define F2P_PKT_ID_2_MSK 0xfff +#define F2P_VALID_2 BIT(15) +#define F2P_UL_USER_NUM_2_SH 16 +#define F2P_UL_USER_NUM_2_MSK 0xf + +/* dword27 */ +#define F2P_PKT_ID_3_SH 0 +#define F2P_PKT_ID_3_MSK 0xfff +#define F2P_VALID_3 BIT(15) +#define F2P_UL_USER_NUM_3_SH 16 +#define F2P_UL_USER_NUM_3_MSK 0xf + +/* dword28 */ +#define F2P_PKT_ID_4_SH 0 +#define F2P_PKT_ID_4_MSK 0xfff +#define F2P_VALID_4 BIT(15) +#define F2P_UL_USER_NUM_4_SH 16 +#define F2P_UL_USER_NUM_4_MSK 0xf + +/* dword29 */ +#define F2P_PKT_ID_5_SH 0 +#define F2P_PKT_ID_5_MSK 0xfff +#define F2P_VALID_5 BIT(15) +#define F2P_UL_USER_NUM_5_SH 16 +#define F2P_UL_USER_NUM_5_MSK 0xf + +/** + * @struct fwcmd_test_para + * @brief fwcmd_test_para + * + * @var fwcmd_test_para::dword0 + * Please Place Description here. + * @var fwcmd_test_para::dword1 + * Please Place Description here. + * @var fwcmd_test_para::dword2 + * Please Place Description here. + * @var fwcmd_test_para::dword3 + * Please Place Description here. + * @var fwcmd_test_para::dword4 + * Please Place Description here. + * @var fwcmd_test_para::dword5 + * Please Place Description here. + * @var fwcmd_test_para::dword6 + * Please Place Description here. + * @var fwcmd_test_para::dword7 + * Please Place Description here. + * @var fwcmd_test_para::dword8 + * Please Place Description here. + * @var fwcmd_test_para::byte9 + * Please Place Description here. + * @var fwcmd_test_para::byte10 + * Please Place Description here. + * @var fwcmd_test_para::byte11 + * Please Place Description here. + * @var fwcmd_test_para::byte12 + * Please Place Description here. + * @var fwcmd_test_para::dword13 + * Please Place Description here. + * @var fwcmd_test_para::dword14 + * Please Place Description here. + * @var fwcmd_test_para::dword15 + * Please Place Description here. + * @var fwcmd_test_para::dword16 + * Please Place Description here. + * @var fwcmd_test_para::dword17 + * Please Place Description here. + * @var fwcmd_test_para::dword18 + * Please Place Description here. + * @var fwcmd_test_para::dword19 + * Please Place Description here. + * @var fwcmd_test_para::dword20 + * Please Place Description here. + * @var fwcmd_test_para::dword21 + * Please Place Description here. + * @var fwcmd_test_para::dword22 + * Please Place Description here. + * @var fwcmd_test_para::dword23 + * Please Place Description here. + * @var fwcmd_test_para::dword24 + * Please Place Description here. + * @var fwcmd_test_para::dword25 + * Please Place Description here. + * @var fwcmd_test_para::dword26 + * Please Place Description here. + * @var fwcmd_test_para::dword27 + * Please Place Description here. + * @var fwcmd_test_para::dword28 + * Please Place Description here. + * @var fwcmd_test_para::dword29 + * Please Place Description here. + * @var fwcmd_test_para::dword30 + * Please Place Description here. + * @var fwcmd_test_para::dword31 + * Please Place Description here. + * @var fwcmd_test_para::dword32 + * Please Place Description here. + * @var fwcmd_test_para::dword33 + * Please Place Description here. + * @var fwcmd_test_para::dword34 + * Please Place Description here. + * @var fwcmd_test_para::dword35 + * Please Place Description here. + * @var fwcmd_test_para::dword36 + * Please Place Description here. + * @var fwcmd_test_para::dword37 + * Please Place Description here. + * @var fwcmd_test_para::dword38 + * Please Place Description here. + * @var fwcmd_test_para::dword39 + * Please Place Description here. + * @var fwcmd_test_para::dword40 + * Please Place Description here. + * @var fwcmd_test_para::dword41 + * Please Place Description here. + * @var fwcmd_test_para::dword42 + * Please Place Description here. + * @var fwcmd_test_para::dword43 + * Please Place Description here. + * @var fwcmd_test_para::dword44 + * Please Place Description here. + * @var fwcmd_test_para::dword45 + * Please Place Description here. + * @var fwcmd_test_para::byte46 + * Please Place Description here. + */ +struct fwcmd_test_para { +#define MAX_SIGB_LEN 64 + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u8 byte9; + u8 byte10; + u8 byte11; + u8 byte12; + u32 dword13; + u32 dword14; + u32 dword15; + u32 dword16; + u32 dword17; + u32 dword18; + u32 dword19; + u32 dword20; + u32 dword21; + u32 dword22; + u32 dword23; + u32 dword24; + u32 dword25; + u32 dword26; + u32 dword27; + u32 dword28; + u32 dword29; + u32 dword30; + u32 dword31; + u32 dword32; + u32 dword33; + u32 dword34; + u32 dword35; + u32 dword36; + u32 dword37; + u32 dword38; + u32 dword39; + u32 dword40; + u32 dword41; + u32 dword42; + u32 dword43; + u32 dword44; + u32 dword45; + u8 byte46[MAX_SIGB_LEN]; +}; + +#endif diff --git a/phl/hal_g6/mac/mac_ax/fwdl.c b/phl/hal_g6/mac/mac_ax/fwdl.c new file mode 100644 index 0000000..c7afd0f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwdl.c @@ -0,0 +1,1262 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "fwdl.h" + +#define FWDL_WAIT_CNT 400000 +#define FWDL_SECTION_MAX_NUM 10 +#define FWDL_SECTION_CHKSUM_LEN 8 +#define FWDL_SECTION_PER_PKT_LEN 2020 +#define FWDL_TRY_CNT 3 +#define FWDL_DIGEST_SIZE 0x20 + +struct fwhdr_section_info { + u8 redl; + u8 *addr; + u32 len; + u32 dladdr; +}; + +struct fw_bin_info { + u8 section_num; + u32 hdr_len; + u32 git_idx; + struct fwhdr_section_info section_info[FWDL_SECTION_MAX_NUM]; +}; + +struct hw_info { + u8 chip; + u8 cut; + u8 category; +}; + +struct fwld_info { + u32 len; + u8 *fw; +}; + +static inline void fwhdr_section_parser(struct fwhdr_section_t *section, + struct fwhdr_section_info *info) +{ + u32 hdr_val; + u32 section_len; + + hdr_val = le32_to_cpu(section->dword1); + section_len = GET_FIELD(hdr_val, SECTION_INFO_SEC_SIZE); + if (hdr_val & SECTION_INFO_CHECKSUM) + section_len += FWDL_SECTION_CHKSUM_LEN; + info->len = section_len; + info->redl = (hdr_val & SECTION_INFO_REDL) ? 1 : 0; + + info->dladdr = (GET_FIELD(le32_to_cpu(section->dword0), + SECTION_INFO_SEC_DL_ADDR)) & 0x1FFFFFFF; +} + +static inline void fwhdr_hdr_parser(struct fwhdr_hdr_t *hdr, + struct fw_bin_info *info) +{ + u32 hdr_val; + + hdr_val = le32_to_cpu(hdr->dword6); + info->section_num = GET_FIELD(hdr_val, FWHDR_SEC_NUM); + info->hdr_len = FWHDR_HDR_LEN + info->section_num * FWHDR_SECTION_LEN; + + /* fill HALMAC information */ + hdr_val = le32_to_cpu(hdr->dword7); + hdr_val = SET_CLR_WORD(hdr_val, FWDL_SECTION_PER_PKT_LEN, + FWHDR_FW_PART_SZ); + hdr->dword7 = cpu_to_le32(hdr_val); + + hdr_val = le32_to_cpu(hdr->dword2); + info->git_idx = GET_FIELD(hdr_val, FWHDR_COMMITID); +} + +static u32 fwhdr_parser(struct mac_ax_adapter *adapter, u8 *fw, u32 len, + struct fw_bin_info *info) +{ + u32 i; + u8 *fw_end = fw + len; + u8 *bin_ptr; + struct fwhdr_section_info *cur_section_info; + + if (!info) { + PLTFM_MSG_ERR("[ERR]%s: *info = NULL\n", __func__); + return MACNPTR; + } else if (!fw) { + PLTFM_MSG_ERR("[ERR]%s: *fw = NULL\n", __func__); + return MACNOITEM; + } else if (!len) { + PLTFM_MSG_ERR("[ERR]%s: len = 0\n", __func__); + return MACBUFSZ; + } + + fwhdr_hdr_parser((struct fwhdr_hdr_t *)fw, info); + bin_ptr = fw + info->hdr_len; + + /* jump to section header */ + fw += FWHDR_HDR_LEN; + cur_section_info = info->section_info; + for (i = 0; i < info->section_num; i++) { + fwhdr_section_parser((struct fwhdr_section_t *)fw, + cur_section_info); + cur_section_info->addr = bin_ptr; + bin_ptr += cur_section_info->len; + fw += FWHDR_SECTION_LEN; + cur_section_info++; + } + + if (fw_end != bin_ptr) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("fw bin size != fw size in fwhdr\n"); + return MACFWBIN; + } + + return MACSUCCESS; +} + +static inline u32 update_fw_ver(struct mac_ax_adapter *adapter, + struct fwhdr_hdr_t *hdr) +{ + u32 hdr_val; + struct mac_ax_fw_info *info = &adapter->fw_info; + + hdr_val = le32_to_cpu(hdr->dword1); + info->major_ver = GET_FIELD(hdr_val, FWHDR_MAJORVER); + info->minor_ver = GET_FIELD(hdr_val, FWHDR_MINORVER); + info->sub_ver = GET_FIELD(hdr_val, FWHDR_SUBVERSION); + info->sub_idx = GET_FIELD(hdr_val, FWHDR_SUBINDEX); + + hdr_val = le32_to_cpu(hdr->dword5); + info->build_year = GET_FIELD(hdr_val, FWHDR_YEAR); + + hdr_val = le32_to_cpu(hdr->dword4); + info->build_mon = GET_FIELD(hdr_val, FWHDR_MONTH); + info->build_date = GET_FIELD(hdr_val, FWHDR_DATE); + info->build_hour = GET_FIELD(hdr_val, FWHDR_HOUR); + info->build_min = GET_FIELD(hdr_val, FWHDR_MIN); + + info->h2c_seq = 0; + info->rec_seq = 0; + + return MACSUCCESS; +} + +static u32 __fwhdr_download(struct mac_ax_adapter *adapter, + u8 *fw, u32 hdr_len, u8 redl) +{ + u8 *buf; + u32 ret = 0; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: h2cb_alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, hdr_len); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: h2cb_put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, fw, hdr_len); + + if (redl) { + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FWDL, + FWCMD_H2C_FUNC_FWHDR_REDL, 0, 0); + } else { + ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FWDL, + FWCMD_H2C_FUNC_FWHDR_DL, 0, 0); + } + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: set h2c hdr fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: build h2c txd fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: PLTFM_TX fail\n", __func__); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + PLTFM_MSG_ERR("[ERR]%s ret: %d\n", __func__, ret); + + return ret; +} + +#if MAC_AX_PHL_H2C +static u32 __sections_build_txd(struct mac_ax_adapter *adapter, + struct rtw_h2c_pkt *h2cb) +{ + u8 *buf; + u32 ret; + u32 txd_len; + struct rtw_t_meta_data info = {0}; + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + + info.type = RTW_PHL_PKT_TYPE_FWDL; + info.pktlen = (u16)h2cb->data_len; + txd_len = ops->txdesc_len(adapter, &info); + + buf = h2cb_push(h2cb, txd_len); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: h2cb_push fail\n", __func__); + return MACNPTR; + } + + ret = ops->build_txdesc(adapter, &info, buf, txd_len); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("build_txdesc fail\n"); + return ret; + } + + return MACSUCCESS; +} + +static u32 __sections_push(struct rtw_h2c_pkt *h2cb) +{ +#define section_push_len 8 + h2cb->vir_data -= section_push_len; + h2cb->vir_tail -= section_push_len; + + return MACSUCCESS; +} + +#else +static u32 __sections_build_txd(struct mac_ax_adapter *adapter, + struct h2c_buf *h2cb) +{ + u8 *buf; + u32 ret; + u32 txd_len; + struct rtw_t_meta_data info; + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + + info.type = RTW_PHL_PKT_TYPE_FWDL; + info.pktlen = (u16)h2cb->len; + txd_len = ops->txdesc_len(adapter, &info); + + buf = h2cb_push(h2cb, txd_len); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: h2cb_push fail\n", __func__); + return MACNPTR; + } + + ret = ops->build_txdesc(adapter, &info, buf, txd_len); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("mac_build_txdesc fail\n"); + return ret; + } + + return MACSUCCESS; +} +#endif +static u32 __sections_download(struct mac_ax_adapter *adapter, + struct fwhdr_section_info *info) +{ + u8 *section = info->addr; + u32 residue_len = info->len; + u32 pkt_len; + u8 *buf; + u32 ret = 0; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + + while (residue_len) { + if (residue_len >= FWDL_SECTION_PER_PKT_LEN) + pkt_len = FWDL_SECTION_PER_PKT_LEN; + else + pkt_len = residue_len; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("h2cb_alloc fail\n"); + return MACNPTR; + } + #if MAC_AX_PHL_H2C + __sections_push(h2cb); + #endif + buf = h2cb_put(h2cb, pkt_len); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("h2cb_put fail\n"); + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, section, pkt_len); + + ret = __sections_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("__sections_build_txd fail\n"); + goto fail; + } + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: PLTFM_TX fail\n", __func__); + goto fail; + } + + h2cb_free(adapter, h2cb); + + section += pkt_len; + residue_len -= pkt_len; + } + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + PLTFM_MSG_ERR("[ERR]%s ret: %d\n", __func__, ret); + + return ret; +} + +static u32 __write_memory(struct mac_ax_adapter *adapter, + u8 *buffer, u32 addr, u32 len) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 *content = NULL; + u32 dl_size; + u32 target_addr, write_addr; + u32 seg_size, seg_bytes; + u32 val32; + u32 index = 0; + u32 ret = MACSUCCESS; + + PLTFM_MSG_WARN("%s ind access start\n", __func__); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr); + MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, 0xAAAAAAAA); + MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY + 4, 0xBBBBBBBB); + + val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY); + if (val32 != 0xAAAAAAAA) { + ret = MACMEMRO; + goto ind_aces_end; + } + + val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + 4); + if (val32 != 0xBBBBBBBB) { + ret = MACMEMRO; + goto ind_aces_end; + } + +ind_aces_end: + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access end\n", __func__); + if (ret != MACSUCCESS) + return ret; + + content = (u8 *)PLTFM_MALLOC(len); + if (!content) { + PLTFM_MSG_ERR("[ERR]%s: malloc fail\n", __func__); + return MACNOBUF; + } + + PLTFM_MEMCPY(content, buffer, len); + + dl_size = len; + target_addr = addr; + + PLTFM_MSG_WARN("%s ind access trg 0x%X start\n", __func__, target_addr); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + while (dl_size != 0) { + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, target_addr); + write_addr = R_AX_INDIR_ACCESS_ENTRY; + + if (dl_size >= ROMDL_SEG_LEN) + seg_size = ROMDL_SEG_LEN; + else + seg_size = dl_size; + + seg_bytes = seg_size; + + while (seg_bytes != 0) { + val32 = *((u32 *)(content + index)); + MAC_REG_W32(write_addr, + cpu_to_le32(val32)); + + seg_bytes -= 4; + write_addr += 4; + index += 4; + } + + target_addr += seg_size; + dl_size -= seg_size; + } + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access trg 0x%X end\n", __func__, target_addr); + + PLTFM_FREE(content, len); + + return MACSUCCESS; +} + +static u32 fwdl_phase0(struct mac_ax_adapter *adapter) +{ + u32 cnt = FWDL_WAIT_CNT; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (adapter->sm.fwdl != MAC_AX_FWDL_CPU_ON) { + PLTFM_MSG_ERR("[ERR]%s: state != CPU_ON\n", __func__); + return MACPROCERR; + } + + while (--cnt) { + if (MAC_REG_R8(R_AX_WCPU_FW_CTRL) & B_AX_H2C_PATH_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[1] = 1 fail\n", __func__); + return MACPOLLTO; + } + + adapter->sm.fwdl = MAC_AX_FWDL_H2C_PATH_RDY; + + return MACSUCCESS; +} + +static u32 fwdl_phase1(struct mac_ax_adapter *adapter, + u8 *fw, u32 hdr_len, u8 redl) +{ + u32 ret; + u32 cnt = FWDL_WAIT_CNT; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (adapter->sm.fwdl != MAC_AX_FWDL_H2C_PATH_RDY) { + PLTFM_MSG_ERR("[ERR]%s: state != H2C_PATH_RDY\n", __func__); + return MACPROCERR; + } + + ret = __fwhdr_download(adapter, fw, hdr_len, redl); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: __fwhdr_download fail\n", __func__); + return ret; + } + + while (--cnt) { + if (MAC_REG_R8(R_AX_WCPU_FW_CTRL) & B_AX_FWDL_PATH_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[2] = 1 fail\n", __func__); + return MACPOLLTO; + } + + MAC_REG_W32(R_AX_HALT_H2C_CTRL, 0); + MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0); + + adapter->sm.fwdl = MAC_AX_FWDL_PATH_RDY; + + return MACSUCCESS; +} + +static u32 check_fw_rdy(struct mac_ax_adapter *adapter) +{ + u32 val8 = FWDL_INITIAL_STATE; + u32 cnt = FWDL_WAIT_CNT; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + while (--cnt) { + val8 = GET_FIELD(MAC_REG_R8(R_AX_WCPU_FW_CTRL), + B_AX_WCPU_FWDL_STS); + if (val8 == FWDL_WCPU_FW_INIT_RDY) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[7:5] = 7 fail\n", __func__); + + switch (val8) { + case FWDL_CHECKSUM_FAIL: + return MACFWCHKSUM; + + case FWDL_SECURITY_FAIL: + return MACFWSECBOOT; + + case FWDL_CUT_NOT_MATCH: + return MACFWCUT; + + default: + return MACPOLLTO; + } + } + + adapter->sm.fwdl = MAC_AX_FWDL_INIT_RDY; + + return MACSUCCESS; +} + +static u32 fwdl_phase2(struct mac_ax_adapter *adapter, u8 *fw, + struct fw_bin_info *info, u8 redl) +{ + u32 ret; + u32 section_num = info->section_num; + struct fwhdr_section_info *section_info = info->section_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_PATH_RDY) { + PLTFM_MSG_ERR("[ERR]%s: state != FWDL_PATH_RDY\n", __func__); + return MACPROCERR; + } + + while (section_num > 0) { + if (!redl) { + ret = __sections_download(adapter, section_info); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("__sections_download fail\n"); + return ret; + } + } else { + if (section_info->redl) { + ret = __sections_download(adapter, + section_info); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("__sections_download "); + PLTFM_MSG_ERR("fail\n"); + return ret; + } + } + } + section_info++; + section_num--; + } + + PLTFM_DELAY_MS(5); + + ret = check_fw_rdy(adapter); + if (ret) { + PLTFM_MSG_ERR("%s: check_fw_rdy fail\n", __func__); + return ret; + } + + return MACSUCCESS; +} + +static void fwdl_fail_dump(struct mac_ax_adapter *adapter, + struct fw_bin_info *info, u32 ret) +{ + u32 val32, digest_addr, digest; + u16 index; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); +#if MAC_AX_FEATURE_DBGPKG + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_dbgpkg dbg_val = {0}; + struct mac_ax_dbgpkg_en dbg_en = {0}; +#endif + + PLTFM_MSG_ERR("[ERR]fwdl ret = %d\n", ret); + val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL); + PLTFM_MSG_ERR("[ERR]fwdl 0x1E0 = 0x%x\n", val32); + + val32 = MAC_REG_R32(R_AX_BOOT_DBG); + PLTFM_MSG_ERR("[ERR]fwdl 0x83F0 = 0x%x\n", val32); + + val32 = MAC_REG_R32(R_AX_UDM3); + PLTFM_MSG_ERR("[ERR]fwdl 0x1FC = 0x%x\n", val32); + + val32 = info->git_idx; + PLTFM_MSG_ERR("[ERR]fw git idx = 0x%x\n", val32); + + PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock); + adapter->hw_info->dbg_port_cnt++; + if (adapter->hw_info->dbg_port_cnt != 1) { + PLTFM_MSG_ERR("[ERR]fwdl fail dump lock cnt %d\n", + adapter->hw_info->dbg_port_cnt); + goto end; + } + + MAC_REG_W32(R_AX_DBG_CTRL, 0xf200f2); + val32 = MAC_REG_R32(R_AX_SYS_STATUS1); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0); + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + + for (index = 0; index < 15; index++) { + val32 = MAC_REG_R32(R_AX_DBG_PORT_SEL); + PLTFM_MSG_ERR("[ERR]fw PC = 0x%x\n", val32); + PLTFM_DELAY_US(10); + } + + PLTFM_MSG_WARN("%s ind access FW digest start\n", __func__); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + digest_addr = (0xB8E17C00 + 64) & ~0xA0000000; + + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, digest_addr); + PLTFM_MSG_ERR("IRAM digest:"); + for (index = 0; index < FWDL_DIGEST_SIZE; index += 4) { + digest = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + index); + PLTFM_MSG_ERR("0x%x\t", digest); + } + + PLTFM_MSG_ERR("DMEM digest:"); + for (index = 0; index < FWDL_DIGEST_SIZE; index += 4) { + digest = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + + FWDL_DIGEST_SIZE + index); + PLTFM_MSG_ERR("0x%x\t", digest); + } + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access FW digest end\n", __func__); + + pltfm_dbg_dump(adapter); + + mac_ops->dump_ple_dbg_page(adapter, 0); + +end: +#if MAC_AX_FEATURE_DBGPKG + dbg_en.ss_dbg = 0; + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.mac_dbg_port = 1; + dbg_en.plersvd_dbg = 1; + mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en); +#endif + adapter->hw_info->dbg_port_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock); +} + +u32 disable_fw_watchdog(struct mac_ax_adapter *adapter) +{ + u32 val32, ret; + + ret = mac_sram_dbg_write(adapter, R_AX_WDT_CTRL, + B_AX_WDT_CTRL_ALL_DIS, CPU_LOCAL_SEL); + if (ret) + return ret; + + val32 = mac_sram_dbg_read(adapter, R_AX_WDT_STATUS, CPU_LOCAL_SEL); + val32 = val32 | B_AX_FS_WDT_INT; + val32 = val32 & (~B_AX_FS_WDT_INT_MSK); + ret = mac_sram_dbg_write(adapter, R_AX_WDT_STATUS, val32, CPU_LOCAL_SEL); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_fwredl(struct mac_ax_adapter *adapter, u8 *fw, u32 len) +{ + u32 val32; + u32 ret; + struct fw_bin_info info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL); + val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); + val32 = SET_CLR_WORD(val32, FWDL_INITIAL_STATE, + B_AX_WCPU_FWDL_STS); + + MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32); + + ret = fwhdr_parser(adapter, fw, len, &info); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__); + goto fwdl_err; + } + + ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: update_fw_ver fail\n", __func__); + goto fwdl_err; + } + + adapter->sm.fwdl = MAC_AX_FWDL_H2C_PATH_RDY; + + ret = fwdl_phase1(adapter, fw, info.hdr_len, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwdl_phase1 fail\n", __func__); + goto fwdl_err; + } + + ret = fwdl_phase2(adapter, fw, &info, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwdl_phase2 fail\n", __func__); + goto fwdl_err; + } + + mac_scanofld_reset_state(adapter); + return MACSUCCESS; + +fwdl_err: + fwdl_fail_dump(adapter, &info, ret); + + return ret; +} + +u32 mac_fwdl(struct mac_ax_adapter *adapter, u8 *fw, u32 len) +{ + u8 retry_cnt; + u32 ret; + struct fw_bin_info info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = 0; + retry_cnt = 0; + MAC_REG_W32(R_AX_UDM1, 0); + // FWDL retry, for 025 temp workaround + while (retry_cnt < FWDL_TRY_CNT) { + if (!fw) { + PLTFM_MSG_ERR("[ERR]%s: no fw\n", __func__); + ret = MACNOFW; + PLTFM_MEMSET(&info, 0, sizeof(struct fw_bin_info)); + goto fwdl_err; + } + + ret = fwhdr_parser(adapter, fw, len, &info); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__); + goto fwdl_err; + } + + ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw); + if (ret) + goto fwdl_err; + + ret = fwdl_phase0(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwdl_phase0 fail\n", __func__); + goto fwdl_err; + } + + ret = fwdl_phase1(adapter, fw, info.hdr_len, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwdl_phase1 fail\n", __func__); + goto fwdl_err; + } + + ret = fwdl_phase2(adapter, fw, &info, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwdl_phase2 fail\n", __func__); + goto fwdl_err; + } + + return MACSUCCESS; + +fwdl_err: + retry_cnt++; + PLTFM_MSG_ERR("[ERR]%s: Retry FWDL count %d\n", __func__, retry_cnt); + // At most retry 2 times + if (retry_cnt < FWDL_TRY_CNT) { + ret = mac_disable_cpu(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_disable_cpu fail\n", __func__); + fwdl_fail_dump(adapter, &info, ret); + return ret; + } + + ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__); + fwdl_fail_dump(adapter, &info, ret); + return ret; + } + MAC_REG_W32(R_AX_UDM1, retry_cnt); + } else { + break; + } + } + + fwdl_fail_dump(adapter, &info, ret); + + return ret; +} + +u32 mac_enable_cpu(struct mac_ax_adapter *adapter, u8 boot_reason, u8 dlfw) +{ + u32 val32, ret; + u16 val16; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (MAC_REG_R32(R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) + return MACCPUSTATE; + + if (adapter->sm.fwdl != MAC_AX_FWDL_IDLE) { + PLTFM_MSG_ERR("[ERR]%s: state != FWDL_IDLE\n", __func__); + return MACPROCERR; + } + + //FW cannot support too much log. Reset R_AX_LDM for FW debug config + MAC_REG_W32(R_AX_LDM, 0); + + MAC_REG_W32(R_AX_HALT_H2C_CTRL, 0); + MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0); + + val32 = MAC_REG_R32(R_AX_UDM0); + val32 &= ~(B_AX_UDM0_DBG_MODE_CTRL | B_AX_UDM0_TRAP_LOOP_CTRL); + MAC_REG_W32(R_AX_UDM0, val32); + + MAC_REG_W32(R_AX_SYS_CLK_CTRL, + MAC_REG_R32(R_AX_SYS_CLK_CTRL) | B_AX_CPU_CLK_EN); + + val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL); + val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); + val32 = SET_CLR_WORD(val32, FWDL_INITIAL_STATE, + B_AX_WCPU_FWDL_STS); + + if (dlfw) + val32 |= B_AX_WCPU_FWDL_EN; + + MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32); + + val16 = MAC_REG_R16(R_AX_BOOT_REASON); + val16 = SET_CLR_WORD(val16, boot_reason, B_AX_BOOT_REASON); + MAC_REG_W16(R_AX_BOOT_REASON, val16); + + val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE); + MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 | B_AX_WCPU_EN); + + adapter->sm.fwdl = MAC_AX_FWDL_CPU_ON; + + if (!dlfw) { + PLTFM_DELAY_MS(5); + + ret = check_fw_rdy(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: ", __func__); + PLTFM_MSG_ERR("check_fw_rdy fail\n"); + return ret; + } + } + + // Prevent sequence number in HALMAC and FW mismatching + reset_lps_seq_num(adapter); + + return MACSUCCESS; +} + +u32 mac_disable_cpu(struct mac_ax_adapter *adapter) +{ + u32 val32, ret; + + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + adapter->sm.fwdl = MAC_AX_FWDL_IDLE; + //todo: need to check cpu in safe state before reset CPU + + val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE); + MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 & ~B_AX_WCPU_EN); + + val32 = MAC_REG_R32(R_AX_UDM0); + val32 &= ~(B_AX_UDM0_DBG_MODE_CTRL | B_AX_UDM0_TRAP_LOOP_CTRL); + MAC_REG_W32(R_AX_UDM0, val32); + + val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL); + val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); + MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32); + + val32 = MAC_REG_R32(R_AX_SYS_CLK_CTRL); + MAC_REG_W32(R_AX_SYS_CLK_CTRL, val32 & ~B_AX_CPU_CLK_EN); + + ret = disable_fw_watchdog(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: disable_fw_watchdog fail\n", __func__); + return ret; + } + + adapter->sm.plat = MAC_AX_PLAT_OFF; + + val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE); + MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 & ~B_AX_PLATFORM_EN); + + val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE); + MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 | B_AX_PLATFORM_EN); + + adapter->sm.plat = MAC_AX_PLAT_ON; + + return MACSUCCESS; +} + +u32 mac_romdl(struct mac_ax_adapter *adapter, u8 *ROM, u32 ROM_addr, u32 len) +{ + u8 *content = NULL; + u32 val32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = mac_disable_cpu(adapter); + if (ret) + return ret; + + if (!ROM) + return MACNOITEM; + + val32 = MAC_REG_R32(R_AX_SEC_CTRL); + + if (val32 & BIT(0)) { + ret = __write_memory(adapter, ROM, ROM_addr, len); + if (ret) + return ret; + } else { + PLTFM_MSG_ERR("[ERR]%s: __write_memory fail\n", __func__); + return MACSECUREON; + } + + PLTFM_FREE(content, len); + + return MACSUCCESS; +} + +u32 mac_ram_boot(struct mac_ax_adapter *adapter, u8 *fw, u32 len) +{ + u32 addr; + u32 ret, section_num; + struct fw_bin_info info; + struct fwhdr_section_info *section_info; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = mac_disable_cpu(adapter); + if (ret) + goto fwdl_err; + + ret = fwhdr_parser(adapter, fw, len, &info); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__); + goto fwdl_err; + } + + ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw); + if (ret) + goto fwdl_err; + + section_num = info.section_num; + section_info = info.section_info; + + while (section_num > 0) { + ret = __write_memory(adapter, section_info->addr, + section_info->dladdr, section_info->len); + if (ret) + goto fwdl_err; + + section_info++; + section_num--; + } + + addr = (0xb8003000 + R_AX_CPU_BOOT_ADDR) & 0x1FFFFFFF; + PLTFM_MSG_WARN("%s ind access 0x%X start\n", __func__, addr); + PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock); + adapter->hw_info->ind_aces_cnt++; + MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr); + MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, (info.section_info[0].dladdr) | + 0xA0000000); + adapter->hw_info->ind_aces_cnt--; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock); + PLTFM_MSG_WARN("%s ind access 0x%X end\n", __func__, addr); + + ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__); + goto fwdl_err; + } + + PLTFM_DELAY_MS(10); + + ret = check_fw_rdy(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: check_fw_rdy fail\n", __func__); + goto fwdl_err; + } + return MACSUCCESS; + +fwdl_err: + fwdl_fail_dump(adapter, &info, ret); + + return ret; +} + +u32 mac_enable_fw(struct mac_ax_adapter *adapter, enum rtw_fw_type cat) +{ + u32 ret = MACSUCCESS; +#if defined(PHL_FEATURE_AP) || defined(PHL_FEATURE_NIC) + u32 chip_id, cv; + u32 fw_len = 0; + u8 *fw = NULL; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + chip_id = GET_FIELD(MAC_REG_R32(R_AX_SYS_CHIPINFO), B_AX_HW_ID); + cv = GET_FIELD(MAC_REG_R32(R_AX_SYS_CFG1), B_AX_CHIP_VER); + + switch (chip_id) { +#ifdef CONFIG_RTL8852A + case RTL8852A_ID: + switch (cv) { +#ifdef MAC_FW_8852A_U2 + case FWDL_CBV: + switch (cat) { +#ifdef PHL_FEATURE_AP + case RTW_FW_AP: + fw_len = array_length_8852a_u2_ap; + fw = array_8852a_u2_ap; + break; +#endif /*PHL_FEATURE_AP*/ +#ifdef PHL_FEATURE_NIC + case RTW_FW_NIC: + fw_len = array_length_8852a_u2_nic; + fw = array_8852a_u2_nic; + break; +#ifdef CONFIG_WOWLAN + case RTW_FW_WOWLAN: + fw_len = array_length_8852a_u2_wowlan; + fw = array_8852a_u2_wowlan; + break; +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + default: + PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*MAC_FW_8852A_U2*/ +#ifdef MAC_FW_8852A_U3 + case FWDL_CCV: + switch (cat) { +#ifdef PHL_FEATURE_AP + case RTW_FW_AP: + fw_len = array_length_8852a_u3_ap; + fw = array_8852a_u3_ap; + break; +#endif /*PHL_FEATURE_AP*/ +#ifdef PHL_FEATURE_NIC + case RTW_FW_NIC: + fw_len = array_length_8852a_u3_nic; + fw = array_8852a_u3_nic; + break; +#ifdef CONFIG_WOWLAN + case RTW_FW_WOWLAN: + fw_len = array_length_8852a_u3_wowlan; + fw = array_8852a_u3_wowlan; + break; +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + default: + PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*MAC_FW_8852A_U3*/ + default: + PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*CONFIG_RTL8852A*/ +#ifdef CONFIG_RTL8852B + case RTL8852B_ID: + switch (cv) { +#ifdef MAC_FW_8852B_U1 + case FWDL_CAV: + switch (cat) { +#ifdef PHL_FEATURE_AP + case RTW_FW_AP: + fw_len = array_length_8852b_u1_ap; + fw = array_8852b_u1_ap; + break; +#endif /*PHL_FEATURE_AP*/ +#ifdef PHL_FEATURE_NIC + case RTW_FW_NIC: + fw_len = array_length_8852b_u1_nic; + fw = array_8852b_u1_nic; + break; +#ifdef CONFIG_WOWLAN + case RTW_FW_WOWLAN: + fw_len = array_length_8852b_u1_wowlan; + fw = array_8852b_u1_wowlan; + break; +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + default: + PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*MAC_FW_8852B_U1*/ +#ifdef MAC_FW_8852B_U2 + case FWDL_CBV: + switch (cat) { +#ifdef PHL_FEATURE_NIC + case RTW_FW_NIC: + fw_len = array_length_8852b_u2_nic; + fw = array_8852b_u2_nic; + break; +#ifdef CONFIG_WOWLAN + case RTW_FW_WOWLAN: + fw_len = array_length_8852b_u2_wowlan; + fw = array_8852b_u2_wowlan; + break; +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + default: + PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*MAC_FW_8852B_U2*/ + default: + PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*CONFIG_RTL8852B*/ +#ifdef CONFIG_RTL8852C + case RTL8852C_ID: + switch (cv) { +#ifdef MAC_FW_8852C_U1 + case FWDL_CAV: + switch (cat) { +#ifdef PHL_FEATURE_AP + case RTW_FW_AP: + fw_len = array_length_8852c_u1_ap; + fw = array_8852c_u1_ap; + break; +#endif /*PHL_FEATURE_AP*/ +#ifdef PHL_FEATURE_NIC + case RTW_FW_NIC: + fw_len = array_length_8852c_u1_nic; + fw = array_8852c_u1_nic; + break; +#ifdef CONFIG_WOWLAN + case RTW_FW_WOWLAN: + fw_len = array_length_8852c_u1_wowlan; + fw = array_8852c_u1_wowlan; + break; +#endif /*CONFIG_WOWLAN*/ +#endif /*PHL_FEATURE_NIC*/ + default: + PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*MAC_FW_8852C_U1*/ + default: + PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__); + fw_len = 0; + fw = 0; + break; + } + break; +#endif /*CONFIG_RTL8852C*/ + + default: + PLTFM_MSG_ERR("[ERR]%s: invalid chip\n", __func__); + fw_len = 0; + fw = 0; + break; + } + + ret = mac_disable_cpu(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_disable_cpu fail\n", __func__); + return ret; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + ret = mac_check_OTP(adapter, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_check_OTP fail\n", + __func__); + return ret; + } + } + + ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__); + return ret; + } + + ret = mac_fwdl(adapter, fw, fw_len); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__); + return ret; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + ret = mac_check_OTP(adapter, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s: mac_check_OTP fail\n", + __func__); + return ret; + } + } + +#endif /* #if defined(PHL_FEATURE_AP) || defined(PHL_FEATURE_NIC) */ + return ret; +} diff --git a/phl/hal_g6/mac/mac_ax/fwdl.h b/phl/hal_g6/mac/mac_ax/fwdl.h new file mode 100644 index 0000000..26abba7 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwdl.h @@ -0,0 +1,429 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FWDL_H_ +#define _MAC_AX_FWDL_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "trx_desc.h" +#include "trxcfg.h" +#include "dle.h" +#include "hci_fc.h" +#include "power_saving.h" + +#if MAC_AX_PCIE_SUPPORT +#include "_pcie.h" +#endif + +#if MAC_AX_8852A_SUPPORT +#include "../fw_ax/rtl8852a/hal8852a_fw.h" +#endif +#if MAC_AX_8852B_SUPPORT +#include "../fw_ax/rtl8852b/hal8852b_fw_u1.h" +#include "../fw_ax/rtl8852b/hal8852b_fw.h" +#endif + +#define FWHDR_HDR_LEN (sizeof(struct fwhdr_hdr_t)) +#define FWHDR_SECTION_LEN (sizeof(struct fwhdr_section_t)) + +#define ROMDL_SEG_LEN 0x40000 + +#define AX_BOOT_REASON_PWR_ON 0 +#define AX_BOOT_REASON_WDT 1 +#define AX_BOOT_REASON_LPS 2 + +#define RTL8852A_ID 0x50 +#define RTL8852B_ID 0x51 +#define RTL8852C_ID 0x52 +#define RTL8834A_ID 0x53 + +#define RTL8852A_ROM_ADDR 0x18900000 +#define RTL8852B_ROM_ADDR 0x18900000 +#define RTL8852C_ROM_ADDR 0x20000000 +#define RTL8192XB_ROM_ADDR 0x20000000 + +/** + * @struct fwhdr_hdr_t + * @brief fwhdr_hdr_t + * + * @var fwhdr_hdr_t::dword0 + * Please Place Description here. + * @var fwhdr_hdr_t::dword1 + * Please Place Description here. + * @var fwhdr_hdr_t::dword2 + * Please Place Description here. + * @var fwhdr_hdr_t::dword3 + * Please Place Description here. + * @var fwhdr_hdr_t::dword4 + * Please Place Description here. + * @var fwhdr_hdr_t::dword5 + * Please Place Description here. + * @var fwhdr_hdr_t::dword6 + * Please Place Description here. + * @var fwhdr_hdr_t::dword7 + * Please Place Description here. + */ +struct fwhdr_hdr_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +/** + * @struct fwhdr_section_t + * @brief fwhdr_section_t + * + * @var fwhdr_section_t::dword0 + * Please Place Description here. + * @var fwhdr_section_t::dword1 + * Please Place Description here. + * @var fwhdr_section_t::dword2 + * Please Place Description here. + * @var fwhdr_section_t::dword3 + * Please Place Description here. + */ +struct fwhdr_section_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +/** + * @enum fw_dl_status + * + * @brief fw_dl_status + * + * @var fw_dl_status::FWDL_INITIAL_STATE + * Please Place Description here. + * @var fw_dl_status::FWDL_FWDL_ONGOING + * Please Place Description here. + * @var fw_dl_status::FWDL_CHECKSUM_FAIL + * Please Place Description here. + * @var fw_dl_status::FWDL_SECURITY_FAIL + * Please Place Description here. + * @var fw_dl_status::FWDL_CUT_NOT_MATCH + * Please Place Description here. + * @var fw_dl_status::FWDL_RSVD0 + * Please Place Description here. + * @var fw_dl_status::FWDL_WCPU_FWDL_RDY + * Please Place Description here. + * @var fw_dl_status::FWDL_WCPU_FW_INIT_RDY + * Please Place Description here. + */ +enum fw_dl_status { + FWDL_INITIAL_STATE = 0, + FWDL_FWDL_ONGOING = 1, + FWDL_CHECKSUM_FAIL = 2, + FWDL_SECURITY_FAIL = 3, + FWDL_CUT_NOT_MATCH = 4, + FWDL_RSVD0 = 5, + FWDL_WCPU_FWDL_RDY = 6, + FWDL_WCPU_FW_INIT_RDY = 7 +}; + +/** + * @enum fw_dl_cv + * + * @brief fw_dl_cv + * + * @var fw_dl_chip_cut::FWDL_CAV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CBV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CCV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CDV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CEV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CFV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CGV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CHV + * Please Place Description here. + * @var fw_dl_chip_cut::FWDL_CIV + * Please Place Description here. + */ +enum fw_dl_cv { + FWDL_CAV = 0, + FWDL_CBV = 1, + FWDL_CCV, + FWDL_CDV, + FWDL_CEV, + FWDL_CFV, + FWDL_CGV, + FWDL_CHV, + FWDL_CIV, +}; + +/* === FW header === */ +/* dword0 */ +#define FWHDR_CUTID_SH 0 +#define FWHDR_CUTID_MSK 0xff +#define FWHDR_CHIPID_SH 8 +#define FWHDR_CHIPID_MSK 0xffffff + +/* dword1 */ +#define FWHDR_MAJORVER_SH 0 +#define FWHDR_MAJORVER_MSK 0xff +#define FWHDR_MINORVER_SH 8 +#define FWHDR_MINORVER_MSK 0xff +#define FWHDR_SUBVERSION_SH 16 +#define FWHDR_SUBVERSION_MSK 0xff +#define FWHDR_SUBINDEX_SH 24 +#define FWHDR_SUBINDEX_MSK 0xff + +/* dword2 */ +#define FWHDR_COMMITID_SH 0 +#define FWHDR_COMMITID_MSK 0xffffffff + +/* dword3 */ +#define FWHDR_SEC_HDR_OFFSET_SH 0 +#define FWHDR_SEC_HDR_OFFSET_MSK 0xff +#define FWHDR_SEC_HDR_SZ_SH 8 +#define FWHDR_SEC_HDR_SZ_MSK 0xff +#define FWHDR_FWHDR_SZ_SH 16 +#define FWHDR_FWHDR_SZ_MSK 0xff +#define FWHDR_FWHDR_VER_SH 24 +#define FWHDR_FWHDR_VER_MSK 0xff + +/* dword4 */ +#define FWHDR_MONTH_SH 0 +#define FWHDR_MONTH_MSK 0xff +#define FWHDR_DATE_SH 8 +#define FWHDR_DATE_MSK 0xff +#define FWHDR_HOUR_SH 16 +#define FWHDR_HOUR_MSK 0xff +#define FWHDR_MIN_SH 24 +#define FWHDR_MIN_MSK 0xff + +/* dword5 */ +#define FWHDR_YEAR_SH 0 +#define FWHDR_YEAR_MSK 0xffff + +/* dword6 */ +#define FWHDR_IMAGEFROM_SH 0 +#define FWHDR_IMAGEFROM_MSK 0x3 +#define FWHDR_BOOTFROM_SH 4 +#define FWHDR_BOOTFROM_MSK 0x3 +#define FWHDR_ROM_ONLY BIT(6) +#define FWHDR_FW_TYPE BIT(7) +#define FWHDR_SEC_NUM_SH 8 +#define FWHDR_SEC_NUM_MSK 0xff +#define FWHDR_HCI_TYPE_SH 16 +#define FWHDR_HCI_TYPE_MSK 0xf +#define FWHDR_NET_TYPE_SH 20 +#define FWHDR_NET_TYPE_MSK 0xf + +/* dword7 */ +#define FWHDR_FW_PART_SZ_SH 0 +#define FWHDR_FW_PART_SZ_MSK 0xffff +#define FWHDR_CMD_VER_SH 24 +#define FWHDR_CMD_VER_MSK 0xff + +/* === Section header === */ +/* dword0 */ +#define SECTION_INFO_SEC_DL_ADDR_SH 0 +#define SECTION_INFO_SEC_DL_ADDR_MSK 0xffffffff + +/* dword1 */ +#define SECTION_INFO_SEC_SIZE_SH 0 +#define SECTION_INFO_SEC_SIZE_MSK 0xffffff +#define SECTION_INFO_SECTIONTYPE_SH 24 +#define SECTION_INFO_SECTIONTYPE_MSK 0xf +#define SECTION_INFO_CHECKSUM BIT(28) +#define SECTION_INFO_REDL BIT(29) + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ +/** + * @brief disable_fw_watchdog + * + * @param *adapter + * @param *fw + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 disable_fw_watchdog(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ +/** + * @brief mac_fwredl + * + * @param *adapter + * @param *fw + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fwredl(struct mac_ax_adapter *adapter, u8 *fw, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_fwdl + * + * @param *adapter + * @param *fw + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_fwdl(struct mac_ax_adapter *adapter, u8 *fw, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_enable_cpu + * + * @param *adapter + * @param boot_reason + * @param dlfw + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_enable_cpu(struct mac_ax_adapter *adapter, u8 boot_reason, u8 dlfw); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_disable_cpu + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_disable_cpu(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_romdl + * + * @param *adapter + * @param *rom + * @param romaddr + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_romdl(struct mac_ax_adapter *adapter, u8 *rom, u32 romaddr, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_ram_boot + * + * @param *adapter + * @param *fw + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ram_boot(struct mac_ax_adapter *adapter, u8 *fw, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Download + * @{ + */ + +/** + * @brief mac_enable_fw + * + * @param *adapter + * @param cat + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_enable_fw(struct mac_ax_adapter *adapter, enum rtw_fw_type cat); +/** + * @} + * @} + */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/fwofld.c b/phl/hal_g6/mac/mac_ax/fwofld.c new file mode 100644 index 0000000..381339e --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwofld.c @@ -0,0 +1,2064 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "fwdl.h" +#include "fwofld.h" + +static u32 get_io_ofld_cap(struct mac_ax_adapter *adapter, u32 *val) +{ +#define MAC_AX_IO_OFLD_MAJ_VER 0 +#define MAC_AX_IO_OFLD_MIN_VER 10 +#define MAC_AX_IO_OFLD_SUB_VER 3 +#define MAC_AX_IO_OFLD_SUB_IDX 0 + struct mac_ax_fw_info *fw_info = &adapter->fw_info; + + if (fw_info->minor_ver > MAC_AX_IO_OFLD_MIN_VER) { + *val |= FW_CAP_IO_OFLD; + return MACSUCCESS; + } + + if (fw_info->minor_ver == MAC_AX_IO_OFLD_MIN_VER && + fw_info->sub_ver >= MAC_AX_IO_OFLD_SUB_VER) + *val |= FW_CAP_IO_OFLD; + + return MACSUCCESS; +} + +u32 mac_get_fw_cap(struct mac_ax_adapter *adapter, u32 *val) +{ + *val = 0; + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACFWNONRDY; + + get_io_ofld_cap(adapter, val); + + return MACSUCCESS; +} + +u32 mac_reset_fwofld_state(struct mac_ax_adapter *adapter, u8 op) +{ + switch (op) { + case FW_OFLD_OP_DUMP_EFUSE: + adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE; + break; + + case FW_OFLD_OP_PACKET_OFLD: + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + break; + + case FW_OFLD_OP_READ_OFLD: + adapter->sm.read_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE; + break; + + case FW_OFLD_OP_WRITE_OFLD: + adapter->sm.write_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.write_h2c = MAC_AX_OFLD_H2C_IDLE; + break; + + case FW_OFLD_OP_CONF_OFLD: + adapter->sm.conf_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_IDLE; + break; + case FW_OFLD_OP_CH_SWITCH: + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + break; + + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_check_fwofld_done(struct mac_ax_adapter *adapter, u8 op) +{ + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + + switch (op) { + case FW_OFLD_OP_DUMP_EFUSE: + if (adapter->sm.efuse_ofld == MAC_AX_OFLD_H2C_IDLE) + return MACSUCCESS; + break; + + case FW_OFLD_OP_PACKET_OFLD: + if (ofld_info->last_op == PKT_OFLD_OP_READ) { + if (adapter->sm.pkt_ofld == MAC_AX_OFLD_H2C_DONE) + return MACSUCCESS; + } else { + if (adapter->sm.pkt_ofld == MAC_AX_OFLD_H2C_IDLE) + return MACSUCCESS; + } + break; + case FW_OFLD_OP_READ_OFLD: + if (adapter->sm.read_h2c == MAC_AX_OFLD_H2C_DONE) + return MACSUCCESS; + break; + case FW_OFLD_OP_WRITE_OFLD: + if (adapter->sm.write_h2c == MAC_AX_OFLD_H2C_IDLE) + return MACSUCCESS; + break; + case FW_OFLD_OP_CONF_OFLD: + if (adapter->sm.conf_h2c == MAC_AX_OFLD_H2C_IDLE) + return MACSUCCESS; + break; + case FW_OFLD_OP_CH_SWITCH: + if (adapter->sm.ch_switch == MAC_AX_OFLD_H2C_IDLE || + adapter->sm.ch_switch == MAC_AX_CH_SWITCH_GET_RPT) + return MACSUCCESS; + break; + default: + return MACNOITEM; + } + + return MACPROCBUSY; +} + +static u32 cnv_write_ofld_state(struct mac_ax_adapter *adapter, u8 dest) +{ + u8 state; + + state = adapter->sm.write_request; + + if (state > MAC_AX_OFLD_REQ_CLEANED) + return MACPROCERR; + + if (dest == MAC_AX_OFLD_REQ_IDLE) { + if (state != MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CLEANED) { + if (state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CREATED) { + if (state == MAC_AX_OFLD_REQ_IDLE || + state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) { + if (state != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + } + + adapter->sm.write_request = dest; + + return MACSUCCESS; +} + +u32 mac_clear_write_request(struct mac_ax_adapter *adapter) +{ + if (adapter->sm.write_request == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + + if (cnv_write_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED) + != MACSUCCESS) + return MACPROCERR; + + PLTFM_FREE(adapter->write_ofld_info.buf, + adapter->write_ofld_info.buf_size); + adapter->write_ofld_info.buf = NULL; + adapter->write_ofld_info.buf_wptr = NULL; + adapter->write_ofld_info.last_req = NULL; + adapter->write_ofld_info.buf_size = 0; + adapter->write_ofld_info.avl_buf_size = 0; + adapter->write_ofld_info.used_size = 0; + adapter->write_ofld_info.req_num = 0; + + return MACSUCCESS; +} + +u32 mac_add_write_request(struct mac_ax_adapter *adapter, + struct mac_ax_write_req *req, u8 *value, u8 *mask) +{ + struct mac_ax_write_ofld_info *ofld_info = &adapter->write_ofld_info; + struct fwcmd_write_ofld_req *write_ptr; + u32 data_len = 0; + u8 state; + + state = adapter->sm.write_request; + + if (!(state == MAC_AX_OFLD_REQ_CREATED || + state == MAC_AX_OFLD_REQ_CLEANED)) { + return MACPROCERR; + } + + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(WRITE_OFLD_MAX_LEN); + if (!ofld_info->buf) + return MACNPTR; + ofld_info->buf_wptr = ofld_info->buf; + ofld_info->buf_size = WRITE_OFLD_MAX_LEN; + ofld_info->avl_buf_size = WRITE_OFLD_MAX_LEN; + ofld_info->used_size = 0; + ofld_info->req_num = 0; + } + + data_len = sizeof(struct mac_ax_write_req); + data_len += req->value_len; + if (req->mask_en == 1) + data_len += req->value_len; + + if (ofld_info->avl_buf_size < data_len) + return MACNOBUF; + + if (!value) + return MACNPTR; + + if (req->mask_en == 1 && !mask) + return MACNPTR; + + if (cnv_write_ofld_state(adapter, + MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS) + return MACPROCERR; + + if (ofld_info->req_num != 0) + ofld_info->last_req->ls = 0; + + ofld_info->last_req = (struct mac_ax_write_req *)ofld_info->buf_wptr; + + req->ls = 1; + + write_ptr = (struct fwcmd_write_ofld_req *)ofld_info->buf_wptr; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(req->value_len, + FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN) | + SET_WORD(req->ofld_id, + FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID) | + SET_WORD(req->entry_num, + FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM) | + req->polling | req->mask_en | req->ls + ); + + write_ptr->dword1 = + cpu_to_le32(SET_WORD(req->offset, + FWCMD_H2C_WRITE_OFLD_REQ_OFFSET) + ); + + ofld_info->buf_wptr += sizeof(struct mac_ax_write_req); + ofld_info->avl_buf_size -= sizeof(struct mac_ax_write_req); + ofld_info->used_size += sizeof(struct mac_ax_write_req); + + PLTFM_MEMCPY(ofld_info->buf_wptr, value, req->value_len); + + ofld_info->buf_wptr += req->value_len; + ofld_info->avl_buf_size -= req->value_len; + ofld_info->used_size += req->value_len; + + if (req->mask_en == 1) { + PLTFM_MEMCPY(ofld_info->buf_wptr, mask, req->value_len); + ofld_info->buf_wptr += req->value_len; + ofld_info->avl_buf_size -= req->value_len; + ofld_info->used_size += req->value_len; + } + + ofld_info->req_num++; + + return MACSUCCESS; +} + +u32 mac_write_ofld(struct mac_ax_adapter *adapter) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_write_ofld_info *ofld_info = &adapter->write_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (ofld_info->used_size + FWCMD_HDR_LEN > READ_OFLD_MAX_LEN) + return MACBUFSZ; + + if (adapter->sm.write_h2c != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + if (adapter->sm.write_request != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + + if (cnv_write_ofld_state(adapter, + MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS) + return MACPROCERR; + + adapter->sm.write_h2c = MAC_AX_OFLD_H2C_SENDING; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, ofld_info->used_size); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_WRITE_OFLD, + 1, 1); + + if (ret) + goto fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.write_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.write_h2c = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + if (cnv_write_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS) + return MACPROCERR; + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 cnv_conf_ofld_state(struct mac_ax_adapter *adapter, u8 dest) +{ + u8 state; + + state = adapter->sm.conf_request; + + if (state > MAC_AX_OFLD_REQ_CLEANED) + return MACPROCERR; + + if (dest == MAC_AX_OFLD_REQ_IDLE) { + if (state != MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CLEANED) { + if (state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CREATED) { + if (state == MAC_AX_OFLD_REQ_IDLE || + state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) { + if (state != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + } + + adapter->sm.conf_request = dest; + + return MACSUCCESS; +} + +u32 mac_clear_conf_request(struct mac_ax_adapter *adapter) +{ + if (adapter->sm.conf_request == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + + if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED) != + MACSUCCESS) + return MACPROCERR; + + PLTFM_FREE(adapter->conf_ofld_info.buf, + adapter->conf_ofld_info.buf_size); + adapter->conf_ofld_info.buf = NULL; + adapter->conf_ofld_info.buf_wptr = NULL; + adapter->conf_ofld_info.buf_size = 0; + adapter->conf_ofld_info.avl_buf_size = 0; + adapter->conf_ofld_info.used_size = 0; + adapter->conf_ofld_info.req_num = 0; + + return MACSUCCESS; +} + +u32 mac_add_conf_request(struct mac_ax_adapter *adapter, + struct mac_ax_conf_ofld_req *req) +{ + struct mac_ax_conf_ofld_info *ofld_info = &adapter->conf_ofld_info; + struct fwcmd_conf_ofld_req_cmd *write_ptr; + u8 state; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + state = adapter->sm.conf_request; + + if (!(state == MAC_AX_OFLD_REQ_CREATED || + state == MAC_AX_OFLD_REQ_CLEANED)) { + return MACPROCERR; + } + + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(CONF_OFLD_MAX_LEN); + if (!ofld_info->buf) + return MACNPTR; + ofld_info->buf_wptr = ofld_info->buf; + ofld_info->buf_size = CONF_OFLD_MAX_LEN; + ofld_info->avl_buf_size = CONF_OFLD_MAX_LEN; + ofld_info->used_size = 0; + ofld_info->req_num = 0; + } + + if (ofld_info->avl_buf_size < sizeof(struct mac_ax_conf_ofld_req)) + return MACNOBUF; + + if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS) + return MACPROCERR; + + write_ptr = (struct fwcmd_conf_ofld_req_cmd *)ofld_info->buf_wptr; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(req->device, + FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE) + ); + + write_ptr->dword1 = + cpu_to_le32(SET_WORD(req->req.hioe.hioe_op, + FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP) | + SET_WORD(req->req.hioe.inst_type, + FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE) | + SET_WORD(req->req.hioe.data_mode, + FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE) + ); + + write_ptr->dword2 = cpu_to_le32(req->req.hioe.param0.register_addr); + + write_ptr->dword3 = + cpu_to_le32(SET_WORD(req->req.hioe.param1.byte_data_h, + FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H) | + SET_WORD(req->req.hioe.param2.byte_data_l, + FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L) + ); + + ofld_info->buf_wptr += sizeof(struct mac_ax_conf_ofld_req); + ofld_info->avl_buf_size -= sizeof(struct mac_ax_conf_ofld_req); + ofld_info->used_size += sizeof(struct mac_ax_conf_ofld_req); + + ofld_info->req_num++; + + return MACSUCCESS; +} + +u32 mac_conf_ofld(struct mac_ax_adapter *adapter) +{ + u8 *buf; + u32 ret; + struct fwcmd_conf_ofld *write_ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_conf_ofld_info *ofld_info = &adapter->conf_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (ofld_info->used_size + FWCMD_HDR_LEN > CONF_OFLD_MAX_LEN) + return MACBUFSZ; + + if (adapter->sm.conf_h2c != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + if (adapter->sm.conf_request != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + + if (cnv_conf_ofld_state(adapter, + MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS) + return MACPROCERR; + + adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_SENDING; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_conf_ofld_hdr)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_conf_ofld *)buf; + + write_ptr->dword0 = + cpu_to_le32(SET_WORD(ofld_info->req_num, + FWCMD_H2C_CONF_OFLD_PATTERN_COUNT)); + + buf = h2cb_put(h2cb, ofld_info->used_size); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_CONF_OFLD, + 1, 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.conf_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS) + return MACPROCERR; + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static inline void mac_pkt_ofld_set_bitmap(u8 *bitmap, u16 index) +{ + bitmap[index >> 3] |= (1 << (index & 7)); +} + +static inline void mac_pkt_ofld_unset_bitmap(u8 *bitmap, u16 index) +{ + bitmap[index >> 3] &= ~(1 << (index & 7)); +} + +static inline u8 mac_pkt_ofld_get_bitmap(u8 *bitmap, u16 index) +{ + return bitmap[index / 8] & (1 << (index & 7)) ? 1 : 0; +} + +u32 mac_read_pkt_ofld(struct mac_ax_adapter *adapter, u8 id) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_packet_ofld *write_ptr; + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (id == PKT_OFLD_MAX_COUNT - 1) + return MACNOITEM; + + if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap, id) == 0) + return MACNOITEM; + + if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_packet_ofld *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) | + SET_WORD(PKT_OFLD_OP_READ, FWCMD_H2C_PACKET_OFLD_PKT_OP) + ); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_PACKET_OFLD, + 1, 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + ofld_info->last_op = PKT_OFLD_OP_READ; + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_del_pkt_ofld(struct mac_ax_adapter *adapter, u8 id) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_packet_ofld *write_ptr; + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (id == PKT_OFLD_MAX_COUNT - 1) + return MACNOITEM; + + if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap, id) == 0) + return MACNOITEM; + + if (ofld_info->used_id_count == 0) + return MACNOITEM; + + if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_packet_ofld *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) | + SET_WORD(PKT_OFLD_OP_DEL, FWCMD_H2C_PACKET_OFLD_PKT_OP) + ); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_PACKET_OFLD, + 1, 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + ofld_info->last_op = PKT_OFLD_OP_DEL; + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_add_pkt_ofld(struct mac_ax_adapter *adapter, u8 *pkt, u16 len, u8 *id) +{ + u8 *buf; + u16 alloc_id; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_packet_ofld *write_ptr; + struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (ofld_info->free_id_count == 0) + return MACNOBUF; + + if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING; + + for (alloc_id = 0; alloc_id < PKT_OFLD_MAX_COUNT - 1; alloc_id++) { + if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap, + alloc_id) == 0) + break; + } + + PLTFM_MSG_TRACE("pkt ofld add. alloc_id: %d, free cnt: %d, use cnt: %d\n", + alloc_id, ofld_info->free_id_count, + ofld_info->used_id_count); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_packet_ofld *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD((u8)alloc_id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) | + SET_WORD(PKT_OFLD_OP_ADD, FWCMD_H2C_PACKET_OFLD_PKT_OP) | + SET_WORD(len, FWCMD_H2C_PACKET_OFLD_PKT_LENGTH) + ); + + *id = (u8)alloc_id; + + buf = h2cb_put(h2cb, len); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, pkt, len); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_PACKET_OFLD, + 1, 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + ofld_info->last_op = PKT_OFLD_OP_ADD; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_pkt_ofld_packet(struct mac_ax_adapter *adapter, + u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id) +{ + struct mac_ax_pkt_ofld_pkt *pkt_info = &adapter->pkt_ofld_pkt; + *pkt_buf = NULL; + + if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_DONE) + return MACPROCERR; + + *pkt_buf = (u8 *)PLTFM_MALLOC(pkt_info->pkt_len); + if (!*pkt_buf) + return MACBUFALLOC; + + PLTFM_MEMCPY(*pkt_buf, pkt_info->pkt, pkt_info->pkt_len); + + *pkt_len = pkt_info->pkt_len; + *pkt_id = pkt_info->pkt_id; + + adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE; + + return MACSUCCESS; +} + +u32 mac_dump_efuse_ofld(struct mac_ax_adapter *adapter, u32 efuse_size, + bool is_hidden) +{ + u32 ret, size; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info; + u8 *buf; + struct fwcmd_dump_efuse *write_ptr; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_SENDING; + + size = efuse_size; + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(size); + if (!ofld_info->buf) + return MACBUFALLOC; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_dump_efuse *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(efuse_size, FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE) | + (is_hidden ? FWCMD_H2C_DUMP_EFUSE_IS_HIDDEN : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_DUMP_EFUSE, + 0, 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + goto fail; + } + + h2cb_free(adapter, h2cb); + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + return ret; +} + +u32 mac_efuse_ofld_map(struct mac_ax_adapter *adapter, u8 *efuse_map, + u32 efuse_size) +{ + u32 size = efuse_size; + struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info; + + if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_DONE) + return MACPROCERR; + + PLTFM_MEMCPY(efuse_map, ofld_info->buf, size); + + adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE; + + return MACSUCCESS; +} + +static u32 cnv_read_ofld_state(struct mac_ax_adapter *adapter, u8 dest) +{ + u8 state; + + state = adapter->sm.read_request; + + if (state > MAC_AX_OFLD_REQ_CLEANED) + return MACPROCERR; + + if (dest == MAC_AX_OFLD_REQ_IDLE) { + if (state != MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CLEANED) { + if (state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_CREATED) { + if (state == MAC_AX_OFLD_REQ_IDLE || + state == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + } else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) { + if (state != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + } + + adapter->sm.read_request = dest; + + return MACSUCCESS; +} + +u32 mac_clear_read_request(struct mac_ax_adapter *adapter) +{ + if (adapter->sm.read_request == MAC_AX_OFLD_REQ_H2C_SENT) + return MACPROCERR; + + if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED) + != MACSUCCESS) + return MACPROCERR; + + PLTFM_FREE(adapter->read_ofld_info.buf, + adapter->read_ofld_info.buf_size); + adapter->read_ofld_info.buf = NULL; + adapter->read_ofld_info.buf_wptr = NULL; + adapter->read_ofld_info.last_req = NULL; + adapter->read_ofld_info.buf_size = 0; + adapter->read_ofld_info.avl_buf_size = 0; + adapter->read_ofld_info.used_size = 0; + adapter->read_ofld_info.req_num = 0; + + return MACSUCCESS; +} + +u32 mac_add_read_request(struct mac_ax_adapter *adapter, + struct mac_ax_read_req *req) +{ + struct mac_ax_read_ofld_info *ofld_info = &adapter->read_ofld_info; + struct fwcmd_read_ofld_req *write_ptr; + u8 state; + + state = adapter->sm.read_request; + + if (!(state == MAC_AX_OFLD_REQ_CREATED || + state == MAC_AX_OFLD_REQ_CLEANED)) { + return MACPROCERR; + } + + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(READ_OFLD_MAX_LEN); + if (!ofld_info->buf) + return MACNPTR; + ofld_info->buf_wptr = ofld_info->buf; + ofld_info->buf_size = READ_OFLD_MAX_LEN; + ofld_info->avl_buf_size = READ_OFLD_MAX_LEN; + ofld_info->used_size = 0; + ofld_info->req_num = 0; + } + + if (ofld_info->avl_buf_size < sizeof(struct mac_ax_read_req)) + return MACNOBUF; + + if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS) + return MACPROCERR; + + if (ofld_info->req_num != 0) + ofld_info->last_req->ls = 0; + + ofld_info->last_req = (struct mac_ax_read_req *)ofld_info->buf_wptr; + + req->ls = 1; + + write_ptr = (struct fwcmd_read_ofld_req *)ofld_info->buf_wptr; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(req->value_len, + FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN) | + SET_WORD(req->ofld_id, + FWCMD_H2C_READ_OFLD_REQ_OFLD_ID) | + SET_WORD(req->entry_num, + FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM) | req->ls + ); + + write_ptr->dword1 = + cpu_to_le32(SET_WORD(req->offset, + FWCMD_H2C_READ_OFLD_REQ_OFFSET) + ); + + ofld_info->buf_wptr += sizeof(struct mac_ax_read_req); + ofld_info->avl_buf_size -= sizeof(struct mac_ax_read_req); + ofld_info->used_size += sizeof(struct mac_ax_read_req); + ofld_info->req_num++; + + return MACSUCCESS; +} + +u32 mac_read_ofld(struct mac_ax_adapter *adapter) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_read_ofld_info *ofld_info = &adapter->read_ofld_info; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + if (ofld_info->used_size + FWCMD_HDR_LEN > READ_OFLD_MAX_LEN) + return MACBUFSZ; + + if (adapter->sm.read_h2c != MAC_AX_OFLD_H2C_IDLE) + return MACPROCERR; + + if (adapter->sm.read_request != MAC_AX_OFLD_REQ_CREATED) + return MACPROCERR; + + if (cnv_read_ofld_state(adapter, + MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS) + return MACPROCERR; + + adapter->sm.read_h2c = MAC_AX_OFLD_H2C_SENDING; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, ofld_info->used_size); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_READ_OFLD, + 1, 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.read_request = MAC_AX_OFLD_REQ_IDLE; + adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE; + goto fail; + } + + h2cb_free(adapter, h2cb); + + if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS) + return MACPROCERR; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_read_ofld_value(struct mac_ax_adapter *adapter, + u8 **val_buf, u16 *val_len) +{ + struct mac_ax_read_ofld_value *value_info = &adapter->read_ofld_value; + *val_buf = NULL; + + if (adapter->sm.read_h2c != MAC_AX_OFLD_H2C_DONE) + return MACPROCERR; + + *val_buf = (u8 *)PLTFM_MALLOC(value_info->len); + if (!*val_buf) + return MACBUFALLOC; + + PLTFM_MEMCPY(*val_buf, value_info->buf, value_info->len); + + *val_len = value_info->len; + + adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE; + + return MACSUCCESS; +} + +u32 mac_general_pkt_ids(struct mac_ax_adapter *adapter, + struct mac_ax_general_pkt_ids *ids) +{ + u8 *buf; + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_general_pkt *write_ptr; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_general_pkt_ids)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + write_ptr = (struct fwcmd_general_pkt *)buf; + write_ptr->dword0 = + cpu_to_le32(SET_WORD(ids->macid, FWCMD_H2C_GENERAL_PKT_MACID) | + SET_WORD(ids->probersp, FWCMD_H2C_GENERAL_PKT_PROBRSP_ID) | + SET_WORD(ids->pspoll, FWCMD_H2C_GENERAL_PKT_PSPOLL_ID) | + SET_WORD(ids->nulldata, FWCMD_H2C_GENERAL_PKT_NULL_ID) + ); + + write_ptr->dword1 = + cpu_to_le32(SET_WORD(ids->qosnull, FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID) | + SET_WORD(ids->cts2self, FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID) | + SET_WORD(ids->probereq, FWCMD_H2C_GENERAL_PKT_PROBREQ_ID) | + SET_WORD(ids->apcsa, FWCMD_H2C_GENERAL_PKT_APCSA_ID) + ); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_INFO, + FWCMD_H2C_FUNC_GENERAL_PKT, + 1, 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 add_cmd(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd) +{ + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + u16 total_len = CMD_OFLD_SIZE; + struct fwcmd_cmd_ofld *write_ptr; + + if (!ofld_info->buf) { + ofld_info->buf = (u8 *)PLTFM_MALLOC(CMD_OFLD_MAX_LEN); + if (!ofld_info->buf) + return MACBUFALLOC; + ofld_info->buf_wptr = ofld_info->buf; + ofld_info->last_wptr = NULL; + ofld_info->buf_size = CMD_OFLD_MAX_LEN; + ofld_info->avl_buf_size = CMD_OFLD_MAX_LEN; + ofld_info->used_size = 0; + ofld_info->cmd_num = 0; + ofld_info->accu_delay = 0; + } + + write_ptr = (struct fwcmd_cmd_ofld *)ofld_info->buf_wptr; + + write_ptr->dword0 = + cpu_to_le32(SET_WORD(cmd->src, FWCMD_H2C_CMD_OFLD_SRC) | + SET_WORD(cmd->type, FWCMD_H2C_CMD_OFLD_TYPE) | + (cmd->lc ? FWCMD_H2C_CMD_OFLD_LC : 0) | + SET_WORD(cmd->rf_path, FWCMD_H2C_CMD_OFLD_PATH) | + SET_WORD(cmd->offset, FWCMD_H2C_CMD_OFLD_OFFSET) | + SET_WORD(ofld_info->cmd_num, FWCMD_H2C_CMD_OFLD_CMD_NUM) + ); + write_ptr->dword1 = + cpu_to_le32(SET_WORD(cmd->id, FWCMD_H2C_CMD_OFLD_ID)); + write_ptr->dword2 = + cpu_to_le32(SET_WORD(cmd->value, FWCMD_H2C_CMD_OFLD_VALUE)); + write_ptr->dword3 = + cpu_to_le32(SET_WORD(cmd->mask, FWCMD_H2C_CMD_OFLD_MASK)); + + ofld_info->last_wptr = ofld_info->buf_wptr; + ofld_info->buf_wptr += total_len; + ofld_info->avl_buf_size -= total_len; + ofld_info->used_size += total_len; + ofld_info->cmd_num++; + if (cmd->type == RTW_MAC_DELAY_OFLD) + ofld_info->accu_delay += cmd->value; + + return MACSUCCESS; +} + +static u32 chk_cmd_ofld_reg(struct mac_ax_adapter *adapter) +{ +#define MAC_AX_CMD_OFLD_POLL_CNT 1000 +#define MAC_AX_CMD_OFLD_POLL_US 50 + struct mac_ax_c2hreg_poll c2h; + struct fwcmd_c2hreg *c2h_content; + u32 ret, result, i, cmd_num; + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + u8 *cmd; + + c2h.polling_id = FWCMD_C2HREG_FUNC_IO_OFLD_RESULT; + c2h.retry_cnt = MAC_AX_CMD_OFLD_POLL_CNT; + c2h.retry_wait_us = MAC_AX_CMD_OFLD_POLL_US; + ret = proc_msg_reg(adapter, NULL, &c2h); + if (ret) { + PLTFM_MSG_ERR("%s: fail to wait FW done(%d)\n", __func__, ret); + return ret; + } + + c2h_content = &c2h.c2hreg_cont.c2h_content; + result = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_IO_OFLD_RESULT_RET); + if (result) { + cmd_num = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM); + cmd = ofld_info->buf + cmd_num * CMD_OFLD_SIZE; + PLTFM_MSG_ERR("%s: fail to finish IO offload\n", __func__); + PLTFM_MSG_ERR("fail offset = %x\n", c2h_content->dword1); + PLTFM_MSG_ERR("exp val = %x\n", c2h_content->dword2); + PLTFM_MSG_ERR("read val = %x\n", c2h_content->dword3); + PLTFM_MSG_ERR("fail cmd num = %d\n", cmd_num); + for (i = 0; i < CMD_OFLD_SIZE; i += 4) + PLTFM_MSG_ERR("%x\n", *((u32 *)(cmd + i))); + + return MACFIOOFLD; + } + + return MACSUCCESS; +} + +static u32 chk_cmd_ofld_pkt(struct mac_ax_adapter *adapter) +{ + u32 cnt = MAC_AX_CMD_OFLD_POLL_CNT; + struct mac_ax_state_mach *sm = &adapter->sm; + struct mac_ax_drv_stats *drv_stats = &adapter->drv_stats; + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + + while (--cnt) { + if (sm->cmd_state == MAC_AX_CMD_OFLD_RCVD) + break; + if (drv_stats->drv_rm) + return MACDRVRM; + PLTFM_DELAY_US(MAC_AX_CMD_OFLD_POLL_US); + } + + PLTFM_MSG_TRACE("%s: cnt = %d, us = %d\n", + __func__, cnt, MAC_AX_CMD_OFLD_POLL_US); + + if (!cnt) { + PLTFM_MSG_ERR("%s: polling timeout\n", __func__); + return MACPOLLTO; + } + + if (ofld_info->result) { + PLTFM_MSG_ERR("%s: ofld FAIL!!!\n", __func__); + return MACFIOOFLD; + } + + return MACSUCCESS; +} + +static u32 chk_cmd_ofld(struct mac_ax_adapter *adapter, u8 rx_ok) +{ + u32 ret; + + if (rx_ok) + ret = chk_cmd_ofld_pkt(adapter); + else + ret = chk_cmd_ofld_reg(adapter); + + return ret; +} + +static u32 cmd_ofld(struct mac_ax_adapter *adapter) +{ + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + u8 *buffer; + u8 func; + u8 rx_ok = adapter->drv_stats.rx_ok; + struct mac_ax_state_mach *sm = &adapter->sm; + + PLTFM_MSG_TRACE("%s===>\n", __func__); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buffer = h2cb_put(h2cb, ofld_info->used_size); + if (!buffer) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buffer, ofld_info->buf, ofld_info->used_size); + + func = rx_ok ? FWCMD_H2C_FUNC_CMD_OFLD_PKT : + FWCMD_H2C_FUNC_CMD_OFLD_REG; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, func, + 0, 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + goto fail; + } + + if (ofld_info->accu_delay) + PLTFM_DELAY_US(ofld_info->accu_delay); + + sm->cmd_state = MAC_AX_CMD_OFLD_SENDING; + + ret = chk_cmd_ofld(adapter, rx_ok); + if (ret) { + PLTFM_MSG_ERR("%s: check IO offload fail\n", __func__); + goto fail; + } + + h2cb_free(adapter, h2cb); + PLTFM_FREE(ofld_info->buf, CMD_OFLD_MAX_LEN); + ofld_info->buf = NULL; + + PLTFM_MSG_TRACE("%s<===\n", __func__); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + PLTFM_FREE(ofld_info->buf, CMD_OFLD_MAX_LEN); + ofld_info->buf = NULL; + + return ret; +} + +u32 mac_add_cmd_ofld(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd) +{ + struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info; + struct mac_ax_state_mach *sm = &adapter->sm; + u32 ret = MACSUCCESS; + + if (cmd->type != RTW_MAC_DELAY_OFLD && + cmd->src != RTW_MAC_RF_CMD_OFLD && cmd->offset & (4 - 1)) + return MACBADDR; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MUTEX_LOCK(&ofld_info->cmd_ofld_lock); + if (sm->cmd_state != MAC_AX_CMD_OFLD_IDLE) { + PLTFM_MSG_ERR("%s: IO offload is busy\n", __func__); + PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock); + return MACPROCERR; + } + sm->cmd_state = MAC_AX_CMD_OFLD_PROC; + PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock); + + if (ofld_info->buf && + ofld_info->avl_buf_size < CMD_OFLD_SIZE) { + if (!ofld_info->last_wptr) { + ret = MACNPTR; + PLTFM_MSG_ERR("%s: wrong pointer\n", __func__); + goto END; + } + *ofld_info->last_wptr = *ofld_info->last_wptr | + FWCMD_H2C_CMD_OFLD_LC; + ret = cmd_ofld(adapter); + if (ret) { + PLTFM_MSG_ERR("%s: send IO offload fail\n", __func__); + goto END; + } + } + + ret = add_cmd(adapter, cmd); + if (ret) + goto END; + + if (!cmd->lc) + goto END; + + ret = cmd_ofld(adapter); + +END: + PLTFM_MUTEX_LOCK(&ofld_info->cmd_ofld_lock); + sm->cmd_state = MAC_AX_CMD_OFLD_IDLE; + PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock); + + return ret; +} + +u32 write_mac_reg_ofld(struct mac_ax_adapter *adapter, + u16 offset, u32 mask, u32 val, u8 lc) +{ + struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_WRITE_OFLD, + 0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0}; + + cmd.offset = offset; + cmd.mask = mask; + cmd.value = val; + cmd.lc = lc; + + return mac_add_cmd_ofld(adapter, &cmd); +} + +u32 poll_mac_reg_ofld(struct mac_ax_adapter *adapter, + u16 offset, u32 mask, u32 val, u8 lc) +{ + struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_COMPARE_OFLD, + 0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0}; + + cmd.offset = offset; + cmd.mask = mask; + cmd.value = val; + cmd.lc = lc; + + return mac_add_cmd_ofld(adapter, &cmd); +} + +u32 delay_ofld(struct mac_ax_adapter *adapter, + u32 val) +{ + struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_DELAY_OFLD, + 0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0}; + + cmd.value = val; + + return mac_add_cmd_ofld(adapter, &cmd); +} + +u32 mac_ccxrpt_parsing(struct mac_ax_adapter *adapter, u8 *buf, struct mac_ax_ccxrpt *info) +{ + u32 val_d0; + u32 val_d3; + u32 dword0 = *((u32 *)buf); + u32 dword3 = *((u32 *)(buf + 12)); + + val_d0 = le32_to_cpu(dword0); + val_d3 = le32_to_cpu(dword3); + info->tx_state = GET_FIELD(val_d0, TXCCXRPT_TX_STATE); + info->sw_define = GET_FIELD(val_d0, TXCCXRPT_SW_DEFINE); + info->macid = GET_FIELD(val_d0, TXCCXRPT_MACID); + info->pkt_ok_num = GET_FIELD(val_d3, TXCCXRPT_PKT_OK_NUM); + info->data_txcnt = GET_FIELD(val_d3, TXCCXRPT_DATA_TX_CNT); + + return MACSUCCESS; +} + +u32 get_ccxrpt_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, u8 *c2h_info) +{ + struct mac_ax_ccxrpt *info; + u32 val_d0, val_d3; + u32 dword0 = *((u32 *)c2h->content); + u32 dword3 = *((u32 *)(c2h->content + 12)); + + info = (struct mac_ax_ccxrpt *)c2h_info; + val_d0 = le32_to_cpu(dword0); + val_d3 = le32_to_cpu(dword3); + info->tx_state = GET_FIELD(val_d0, TXCCXRPT_TX_STATE); + info->sw_define = GET_FIELD(val_d0, TXCCXRPT_SW_DEFINE); + info->macid = GET_FIELD(val_d0, TXCCXRPT_MACID); + info->pkt_ok_num = GET_FIELD(val_d3, TXCCXRPT_PKT_OK_NUM); + info->data_txcnt = GET_FIELD(val_d3, TXCCXRPT_DATA_TX_CNT); + + if (info->tx_state) + *id = MSG_EVT_CCX_REPORT_TX_FAIL; + else + *id = MSG_EVT_CCX_REPORT_TX_OK; + + return MACSUCCESS; +} + +static inline u8 scanofld_ch_list_len(struct scan_chinfo_list *list) +{ + return list->size; +} + +static inline void scanofld_ch_list_init(struct scan_chinfo_list *list) +{ + list->head = NULL; + list->tail = NULL; + list->size = 0; +} + +static inline u32 scanofld_ch_list_insert_head(struct mac_ax_adapter *adapter, + struct scan_chinfo_list *list, + struct mac_ax_scanofld_chinfo *chinfo) +{ + struct scanofld_chinfo_node *node; + + node = (struct scanofld_chinfo_node *)PLTFM_MALLOC(sizeof(struct scanofld_chinfo_node)); + if (!node) + return MACNOBUF; + node->next = list->head; + if (list->size == 0) + list->tail = node; + list->size++; + list->head = node; + node->chinfo = chinfo; + return MACSUCCESS; +} + +static inline u32 scanofld_ch_list_insert_tail(struct mac_ax_adapter *adapter, + struct scan_chinfo_list *list, + struct mac_ax_scanofld_chinfo *chinfo) +{ + struct scanofld_chinfo_node *node; + + node = (struct scanofld_chinfo_node *)PLTFM_MALLOC(sizeof(struct scanofld_chinfo_node)); + + if (!node) + return MACNOBUF; + if (list->size == 0) + list->head = node; + else + list->tail->next = node; + + list->tail = node; + node->chinfo = chinfo; + node->next = NULL; + list->size++; + return MACSUCCESS; +} + +static inline void scanofld_ch_node_print(struct mac_ax_adapter *adapter, + struct scanofld_chinfo_node *curr_node, u8 i) +{ + PLTFM_MSG_TRACE("[CH %d] - DWORD 0:%x\n", i, *((u32 *)(curr_node->chinfo))); + PLTFM_MSG_TRACE("[CH %d] -- period = %d\n", i, curr_node->chinfo->period); + PLTFM_MSG_TRACE("[CH %d] -- dwell_time = %d\n", i, curr_node->chinfo->dwell_time); + PLTFM_MSG_TRACE("[CH %d] -- central_ch = %d\n", i, curr_node->chinfo->central_ch); + PLTFM_MSG_TRACE("[CH %d] -- pri_ch = %d\n", i, curr_node->chinfo->pri_ch); + PLTFM_MSG_TRACE("[CH %d] - DWORD 1:%x\n", i, *((u32 *)(curr_node->chinfo) + 1)); + PLTFM_MSG_TRACE("[CH %d] -- bw = %d\n", i, curr_node->chinfo->bw); + PLTFM_MSG_TRACE("[CH %d] -- noti_dwell = %d\n", i, curr_node->chinfo->c2h_notify_dwell); + PLTFM_MSG_TRACE("[CH %d] -- noti_preTX = %d\n", i, curr_node->chinfo->c2h_notify_preTX); + PLTFM_MSG_TRACE("[CH %d] -- noti_postTX = %d\n", i, curr_node->chinfo->c2h_notify_postTX); + PLTFM_MSG_TRACE("[CH %d] -- noti_leaveCh = %d\n", i, curr_node->chinfo->c2h_notify_leaveCH); + PLTFM_MSG_TRACE("[CH %d] -- noti_enterCh = %d\n", i, curr_node->chinfo->c2h_notify_enterCH); + PLTFM_MSG_TRACE("[CH %d] -- numAddtionPkt = %d\n", i, curr_node->chinfo->num_addition_pkt); + PLTFM_MSG_TRACE("[CH %d] -- tx_pkt = %d\n", i, curr_node->chinfo->tx_pkt); + PLTFM_MSG_TRACE("[CH %d] -- pause_tx_data = %d\n", i, curr_node->chinfo->pause_tx_data); + PLTFM_MSG_TRACE("[CH %d] -- rsvd0 = %d\n", i, curr_node->chinfo->rsvd0); + PLTFM_MSG_TRACE("[CH %d] -- rsvd1 = %d\n", i, curr_node->chinfo->rsvd1); + PLTFM_MSG_TRACE("[CH %d] - DWORD 2:%x\n", i, *((u32 *)(curr_node->chinfo) + 2)); + PLTFM_MSG_TRACE("[CH %d] -- id 0 = %d\n", i, curr_node->chinfo->additional_pkt_id[0]); + PLTFM_MSG_TRACE("[CH %d] -- id 1 = %d\n", i, curr_node->chinfo->additional_pkt_id[1]); + PLTFM_MSG_TRACE("[CH %d] -- id 2 = %d\n", i, curr_node->chinfo->additional_pkt_id[2]); + PLTFM_MSG_TRACE("[CH %d] -- id 3 = %d\n", i, curr_node->chinfo->additional_pkt_id[3]); + PLTFM_MSG_TRACE("[CH %d] - DWORD 3:%x\n", i, *((u32 *)(curr_node->chinfo) + 3)); + PLTFM_MSG_TRACE("[CH %d] -- id 4 = %d\n", i, curr_node->chinfo->additional_pkt_id[4]); + PLTFM_MSG_TRACE("[CH %d] -- id 5 = %d\n", i, curr_node->chinfo->additional_pkt_id[5]); + PLTFM_MSG_TRACE("[CH %d] -- id 6 = %d\n", i, curr_node->chinfo->additional_pkt_id[6]); + PLTFM_MSG_TRACE("[CH %d] -- id 7 = %d\n", i, curr_node->chinfo->additional_pkt_id[7]); +} + +static inline void scanofld_ch_list_print(struct mac_ax_adapter *adapter, + struct scan_chinfo_list *list) +{ + struct scanofld_chinfo_node *curr_node = list->head; + u8 i = 0; + + PLTFM_MSG_TRACE("------------------------------------------\n"); + PLTFM_MSG_TRACE("[CH List] len = %d\n", list->size); + while (curr_node) { + scanofld_ch_node_print(adapter, curr_node, i); + PLTFM_MSG_TRACE("\n"); + curr_node = curr_node->next; + i++; + } + PLTFM_MSG_TRACE("------------------------------------------\n\n"); +} + +void mac_scanofld_ch_list_clear(struct mac_ax_adapter *adapter, + struct scan_chinfo_list *list) +{ + struct scanofld_chinfo_node *curr_node = list->head; + struct scanofld_chinfo_node *tmp; + + while (curr_node) { + tmp = curr_node; + curr_node = curr_node->next; + PLTFM_FREE(tmp->chinfo, sizeof(struct mac_ax_scanofld_chinfo)); + PLTFM_FREE(tmp, sizeof(struct scanofld_chinfo_node)); + list->size--; + } + list->head = NULL; + list->tail = NULL; + scanofld_ch_list_print(adapter, list); +} + +void mac_scanofld_reset_state(struct mac_ax_adapter *adapter) +{ + struct mac_ax_scanofld_info *scanofld_info; + + scanofld_info = &adapter->scanofld_info; + + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + + scanofld_info->fw_scan_busy = 0; +} + +u32 mac_add_scanofld_ch(struct mac_ax_adapter *adapter, struct mac_ax_scanofld_chinfo *chinfo, + u8 send_h2c, u8 clear_after_send) +{ + struct mac_ax_scanofld_info *scanofld_info; + struct scan_chinfo_list *list; + struct scanofld_chinfo_node *curr_node; + struct mac_ax_scanofld_chinfo *tmp; + u32 ret; + u8 list_size; + u8 *buf8; + u32 *buf32; + u32 *chinfo32; + u8 chinfo_dword; + struct fwcmd_add_scanofld_ch *pkt; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cbuf; + #else + struct h2c_buf *h2cbuf; + #endif + + scanofld_info = &adapter->scanofld_info; + PLTFM_MSG_TRACE("[scan] drv_chlist_busy=%d, fw_chlist_busy=%d", + scanofld_info->drv_chlist_busy, scanofld_info->fw_chlist_busy); + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + if (scanofld_info->drv_chlist_busy) { + PLTFM_MSG_ERR("[scan][add] Halmac scan list busy, abort adding.\n"); + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + return MACPROCBUSY; + } + scanofld_info->drv_chlist_busy = 1; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + + ret = MACSUCCESS; + + if (!scanofld_info->list) { + list = (struct scan_chinfo_list *)PLTFM_MALLOC(sizeof(struct scan_chinfo_list)); + scanofld_info->list = list; + scanofld_ch_list_init(adapter->scanofld_info.list); + } + list = scanofld_info->list; + + tmp = (struct mac_ax_scanofld_chinfo *)PLTFM_MALLOC(sizeof(struct mac_ax_scanofld_chinfo)); + PLTFM_MEMCPY(tmp, chinfo, sizeof(struct mac_ax_scanofld_chinfo)); + ret = scanofld_ch_list_insert_tail(adapter, list, tmp); + if (ret) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + return ret; + } + scanofld_ch_list_print(adapter, list); + + if (!send_h2c) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + return ret; + } + + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + if (scanofld_info->fw_chlist_busy) { + PLTFM_MSG_ERR("[scan][add] FW scan list busy, abort sending.\n"); + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return MACPROCBUSY; + } + adapter->scanofld_info.fw_chlist_busy = 1; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + + list_size = scanofld_ch_list_len(list); + if (list_size == 0) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return MACNOITEM; + } + + h2cbuf = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cbuf) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return MACNPTR; + } + + buf8 = h2cb_put(h2cbuf, + sizeof(struct fwcmd_add_scanofld_ch) + + list_size * sizeof(struct mac_ax_scanofld_chinfo)); + if (!buf8) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return MACNOBUF; + } + + pkt = (struct fwcmd_add_scanofld_ch *)buf8; + pkt->dword0 = cpu_to_le32(SET_WORD(list_size, FWCMD_H2C_ADD_SCANOFLD_CH_NUM_OF_CH) | + SET_WORD(sizeof(struct mac_ax_scanofld_chinfo) / 4, + FWCMD_H2C_ADD_SCANOFLD_CH_SIZE_OF_CHINFO)); + buf32 = (u32 *)(buf8 + sizeof(struct fwcmd_add_scanofld_ch)); + curr_node = list->head; + while (curr_node) { + chinfo32 = (u32 *)(curr_node->chinfo); + for (chinfo_dword = 0; + chinfo_dword < (sizeof(struct mac_ax_scanofld_chinfo) / 4); + chinfo_dword++) { + *buf32 = cpu_to_le32(*chinfo32); + buf32++; + chinfo32++; + } + curr_node = curr_node->next; + } + + ret = h2c_pkt_set_hdr(adapter, h2cbuf, FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_ADD_SCANOFLD_CH, 1, 1); + if (ret) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return ret; + } + ret = h2c_pkt_build_txd(adapter, h2cbuf); + if (ret) { + PLTFM_MUTEX_LOCK(&scanofld_info->drv_chlist_state_lock); + scanofld_info->drv_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->drv_chlist_state_lock); + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return ret; + } + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cbuf); + #else + ret = PLTFM_TX(h2cbuf->data, h2cbuf->len); + #endif + h2cb_free(adapter, h2cbuf); + if (ret) + return ret; + h2c_end_flow(adapter); + PLTFM_MSG_TRACE("[scan] drv_chlist_busy=%d, fw_chlist_busy=%d", + scanofld_info->drv_chlist_busy, scanofld_info->fw_chlist_busy); + scanofld_info->clear_drv_ch_list = clear_after_send; + return ret; +} + +u32 mac_scanofld(struct mac_ax_adapter *adapter, struct mac_ax_scanofld_param *scanParam) +{ + u8 *buf; + u32 ret; + struct mac_ax_scanofld_info *scanofld_info; + struct fwcmd_scanofld *pkt; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cbuf; + #else + struct h2c_buf *h2cbuf; + #endif + + scanofld_info = &adapter->scanofld_info; + ret = MACSUCCESS; + PLTFM_MSG_TRACE("[scan] op=%d (%d), fw_scan_busy=%d, fw_chlist_busy=%d", + scanParam->operation, !!(scanParam->operation), + scanofld_info->fw_scan_busy, scanofld_info->fw_chlist_busy); + if (!!(scanParam->operation) && scanofld_info->fw_scan_busy) { + PLTFM_MSG_ERR("[scan] Cant start scanning while scanning\n"); + return MACPROCBUSY; + } + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + if (!!(scanParam->operation) && scanofld_info->fw_chlist_busy) { + PLTFM_MSG_ERR("[scan] Cant start scanning when fw chlist busy\n"); + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + return MACPROCBUSY; + } + + scanofld_info->fw_chlist_busy = (u8)!!(scanParam->operation); + scanofld_info->fw_scan_busy = (u8)!!(scanParam->operation); + PLTFM_MSG_TRACE("[scan] fw_chlist_busy = %d, fw_scan_busy=%d", + scanofld_info->fw_chlist_busy, scanofld_info->fw_scan_busy); + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + PLTFM_MSG_TRACE("[scan] macid=%d\n", scanParam->macid); + PLTFM_MSG_TRACE("[scan] port_id=%d\n", scanParam->port_id); + PLTFM_MSG_TRACE("[scan] band=%d\n", scanParam->band); + PLTFM_MSG_TRACE("[scan] operation=%d\n", scanParam->operation); + PLTFM_MSG_TRACE("[scan] target_ch_mode=%d\n", scanParam->target_ch_mode); + PLTFM_MSG_TRACE("[scan] start_mode=%d\n", scanParam->start_mode); + PLTFM_MSG_TRACE("[scan] scan_type=%d\n", scanParam->scan_type); + PLTFM_MSG_TRACE("[scan] target_ch_bw=%d\n", scanParam->target_ch_bw); + PLTFM_MSG_TRACE("[scan] target_pri_ch=%d\n", scanParam->target_pri_ch); + PLTFM_MSG_TRACE("[scan] target_central_ch=%d\n", scanParam->target_central_ch); + PLTFM_MSG_TRACE("[scan] probe_req_pkt_id=%d\n", scanParam->probe_req_pkt_id); + PLTFM_MSG_TRACE("[scan] norm_pd=%d\n", scanParam->norm_pd); + PLTFM_MSG_TRACE("[scan] norm_cy=%d\n", scanParam->norm_cy); + PLTFM_MSG_TRACE("[scan] slow_pd=%d\n", scanParam->slow_pd); + + h2cbuf = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cbuf) { + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_scan_busy = 0; + return MACNPTR; + } + + buf = h2cb_put(h2cbuf, sizeof(struct fwcmd_scanofld)); + if (!buf) { + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = 0; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_scan_busy = 0; + return MACNOBUF; + } + + pkt = (struct fwcmd_scanofld *)buf; + pkt->dword0 = cpu_to_le32(SET_WORD(scanParam->macid, FWCMD_H2C_SCANOFLD_MACID) | + SET_WORD(scanParam->norm_cy, FWCMD_H2C_SCANOFLD_NORM_CY) | + SET_WORD(scanParam->port_id, FWCMD_H2C_SCANOFLD_PORT_ID) | + (scanParam->band ? FWCMD_H2C_SCANOFLD_BAND : 0) | + SET_WORD(scanParam->operation, FWCMD_H2C_SCANOFLD_OPERATION)); + pkt->dword1 = cpu_to_le32((scanParam->c2h_end ? FWCMD_H2C_SCANOFLD_C2H_NOTIFY_END : 0) | + (scanParam->target_ch_mode ? + FWCMD_H2C_SCANOFLD_TARGET_CH_MODE : 0) | + (scanParam->start_mode ? + FWCMD_H2C_SCANOFLD_START_MODE : 0) | + SET_WORD(scanParam->scan_type, FWCMD_H2C_SCANOFLD_SCAN_TYPE) | + SET_WORD(scanParam->target_ch_bw, + FWCMD_H2C_SCANOFLD_TARGET_CH_BW) | + SET_WORD(scanParam->target_pri_ch, + FWCMD_H2C_SCANOFLD_TARGET_PRI_CH) | + SET_WORD(scanParam->target_central_ch, + FWCMD_H2C_SCANOFLD_TARGET_CENTRAL_CH) | + SET_WORD(scanParam->probe_req_pkt_id, + FWCMD_H2C_SCANOFLD_PROBE_REQ_PKT_ID)); + pkt->dword2 = cpu_to_le32(SET_WORD(scanParam->norm_pd, FWCMD_H2C_SCANOFLD_NORM_PD) | + SET_WORD(scanParam->slow_pd, FWCMD_H2C_SCANOFLD_SLOW_PD)); + pkt->dword3 = cpu_to_le32(scanParam->tsf_high); + pkt->dword4 = cpu_to_le32(scanParam->tsf_low); + + ret = h2c_pkt_set_hdr(adapter, h2cbuf, FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_SCANOFLD, 1, 1); + if (ret) { + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = !scanofld_info->fw_chlist_busy; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_scan_busy = !scanofld_info->fw_scan_busy; + return ret; + } + ret = h2c_pkt_build_txd(adapter, h2cbuf); + if (ret) { + PLTFM_MUTEX_LOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_chlist_busy = !scanofld_info->fw_chlist_busy; + PLTFM_MUTEX_UNLOCK(&scanofld_info->fw_chlist_state_lock); + scanofld_info->fw_scan_busy = !scanofld_info->fw_scan_busy; + return ret; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cbuf); + #else + ret = PLTFM_TX(h2cbuf->data, h2cbuf->len); + #endif + h2cb_free(adapter, h2cbuf); + if (ret) + return ret; + h2c_end_flow(adapter); + return ret; +} + +u32 mac_scanofld_fw_busy(struct mac_ax_adapter *adapter) +{ + if (adapter->scanofld_info.fw_scan_busy) + return MACPROCBUSY; + else + return MACSUCCESS; +} + +u32 mac_scanofld_chlist_busy(struct mac_ax_adapter *adapter) +{ + if (adapter->scanofld_info.drv_chlist_busy || adapter->scanofld_info.fw_chlist_busy) + return MACPROCBUSY; + else + return MACSUCCESS; +} + +u32 mac_ch_switch_ofld(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_parm parm) +{ + u32 ret; + u8 *buf; + struct fwcmd_ch_switch *pkt; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cbuf; + #else + struct h2c_buf *h2cbuf; + #endif + if (adapter->sm.ch_switch != MAC_AX_OFLD_H2C_IDLE) + return MACPROCBUSY; + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_SENDING; + h2cbuf = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cbuf) { + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + return MACNOBUF; + } + buf = h2cb_put(h2cbuf, sizeof(struct fwcmd_ch_switch)); + if (!buf) { + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + return MACNOBUF; + } + pkt = (struct fwcmd_ch_switch *)buf; + pkt->dword0 = cpu_to_le32(SET_WORD(parm.pri_ch, FWCMD_H2C_CH_SWITCH_PRI_CH) | + SET_WORD(parm.central_ch, FWCMD_H2C_CH_SWITCH_CENTRAL_CH) | + SET_WORD(parm.bw, FWCMD_H2C_CH_SWITCH_BW) | + SET_WORD(parm.ch_band, FWCMD_H2C_CH_SWITCH_CH_BAND) | + (parm.band ? FWCMD_H2C_CH_SWITCH_BAND : 0) | + (parm.reload_rf ? FWCMD_H2C_CH_SWITCH_RELOAD_RF : 0)); + ret = h2c_pkt_set_hdr(adapter, h2cbuf, FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_CH_SWITCH, 1, 0); + if (ret) { + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + return ret; + } + ret = h2c_pkt_build_txd(adapter, h2cbuf); + if (ret) { + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + return ret; + } + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cbuf); + #else + ret = PLTFM_TX(h2cbuf->data, h2cbuf->len); + #endif + h2cb_free(adapter, h2cbuf); + if (ret) { + adapter->sm.ch_switch = MAC_AX_OFLD_H2C_IDLE; + return ret; + } + h2c_end_flow(adapter); + return ret; +} + +u32 mac_get_ch_switch_rpt(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_rpt *rpt) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + + if (sm->ch_switch != MAC_AX_CH_SWITCH_GET_RPT) + return MACPROCERR; + PLTFM_MEMCPY(rpt, adapter->ch_switch_rpt, sizeof(struct mac_ax_ch_switch_rpt)); + sm->ch_switch = MAC_AX_OFLD_H2C_IDLE; + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/fwofld.h b/phl/hal_g6/mac/mac_ax/fwofld.h new file mode 100644 index 0000000..8fd54fc --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/fwofld.h @@ -0,0 +1,936 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_FW_OFLD_H_ +#define _MAC_AX_FW_OFLD_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "fwofld.h" +#include "trx_desc.h" + +#define READ_OFLD_MAX_LEN 2000 +#define WRITE_OFLD_MAX_LEN 2000 +#define CONF_OFLD_MAX_LEN 2000 +#define CMD_OFLD_MAX_LEN 2000 + +#define CONF_OFLD_RESTORE 0 +#define CONF_OFLD_BACKUP 1 + +#define SCAN_OP_STOP 0 +#define SCAN_OP_START 1 +#define SCAN_OP_SETPARM 2 + +#define CMD_OFLD_SIZE sizeof(struct fwcmd_cmd_ofld) + +/* Generate 8-bit mask for a 4-byte alignment offset */ +#define GET_W8_MSK(offset) \ + (0xFF << ((offset) & 0x3 ? (8 * ((offset) & 0x3)) : 0)) + +/* Generate 16-bit mask for a 4-byte alignment offset */ +#define GET_W16_MSK(offset) \ + (0xFFFF << ((offset) & 0x2 ? 16 : 0)) + +#define MAC_REG_W8_OFLD(offset, val, lc) \ + write_mac_reg_ofld(adapter, offset & 0xFFFC, GET_W8_MSK(offset), val, lc) + +#define MAC_REG_W16_OFLD(offset, val, lc) \ + write_mac_reg_ofld(adapter, offset & 0xFFFD, GET_W16_MSK(offset), val, lc) + +#define MAC_REG_W32_OFLD(offset, val, lc) \ + write_mac_reg_ofld(adapter, offset, 0xFFFFFFFF, val, lc) + +#define MAC_REG_W_OFLD(offset, mask, val, lc) \ + write_mac_reg_ofld(adapter, offset, mask, val, lc) + +#define MAC_REG_P_OFLD(offset, mask, val, lc) \ + poll_mac_reg_ofld(adapter, offset, mask, val, lc) + +#define DELAY_OFLD(val, lc) \ + poll_mac_reg_ofld(adapter, val, lc) + +/** + * @enum PKT_OFLD_OP + * + * @brief PKT_OFLD_OP + * + * @var PKT_OFLD_OP::PKT_OFLD_OP_ADD + * Please Place Description here. + * @var PKT_OFLD_OP::PKT_OFLD_OP_DEL + * Please Place Description here. + * @var PKT_OFLD_OP::PKT_OFLD_OP_READ + * Please Place Description here. + * @var PKT_OFLD_OP::PKT_OFLD_OP_MAX + * Please Place Description here. + */ +enum PKT_OFLD_OP { + PKT_OFLD_OP_ADD = 0, + PKT_OFLD_OP_DEL = 1, + PKT_OFLD_OP_READ = 2, + PKT_OFLD_OP_MAX +}; + +/** + * @enum FW_OFLD_OP + * + * @brief FW_OFLD_OP + * + * @var FW_OFLD_OP::FW_OFLD_OP_DUMP_EFUSE + * Please Place Description here. + * @var FW_OFLD_OP::FW_OFLD_OP_PACKET_OFLD + * Please Place Description here. + * @var FW_OFLD_OP::FW_OFLD_OP_READ_OFLD + * Please Place Description here. + * @var FW_OFLD_OP::FW_OFLD_OP_WRITE_OFLD + * Please Place Description here. + * @var FW_OFLD_OP::FW_OFLD_OP_CONF_OFLD + * Please Place Description here. + * @var FW_OFLD_OP::FW_OFLD_OP_MAX + * Please Place Description here. + */ +enum FW_OFLD_OP { + FW_OFLD_OP_DUMP_EFUSE = 0, + FW_OFLD_OP_PACKET_OFLD = 1, + FW_OFLD_OP_READ_OFLD = 2, + FW_OFLD_OP_WRITE_OFLD = 3, + FW_OFLD_OP_CONF_OFLD = 4, + FW_OFLD_OP_CH_SWITCH = 5, + FW_OFLD_OP_MAX +}; + +/** + * @enum CHSW_BW + * + * @brief CHSW_BW + * + * @var CHSW_BW::CHSW_BW_20 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_40 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_80 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_160 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_80_80 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_5 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_10 + * Please Place Description here. + * @var CHSW_BW::CHSW_BW_MAX + * Please Place Description here. + */ +enum CHSW_BW { + CHSW_BW_20 = 0, + CHSW_BW_40 = 1, + CHSW_BW_80 = 2, + CHSW_BW_160 = 3, + CHSW_BW_80_80 = 4, + CHSW_BW_5 = 5, + CHSW_BW_10 = 6, + CHSW_BW_MAX +}; + +/** + * @enum CHSW_CHBAND + * + * @brief CHSW_CHBAND + * + * @var CHSW_CHBAND::CHSW_CHBAND_24G + * Please Place Description here. + * @var CHSW_CHBAND::CHSW_CHBAND_5G + * Please Place Description here. + * @var CHSW_CHBAND::CHSW_CHBAND_6G + * Please Place Description here. + * @var CHSW_CHBAND::CHSW_CHBAND_MAX + * Please Place Description here. + */ +enum CHSW_CHBAND { + CHSW_CHBAND_24G = 0, + CHSW_CHBAND_5G = 1, + CHSW_CHBAND_6G = 2, + CHSW_CHBAND_MAX +}; + +/** + * @enum CHSW_STATUS_CODE + * + * @brief CHSW_STATUS_CODE + * + * @var CHSW_STATUS_CODE::CHSW_OK + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_NOT_COMPILED_ERR + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_STOPSER_FAIL_WARN + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_BB_CTRL_BW_CH_FAIL_ERR + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_RF_RELOAD_FAIL_WARN + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_STARTSER_FAIL_WARN + * Please Place Description here. + * @var CHSW_STATUS_CODE::CHSW_MAX + * Please Place Description here. + */ +enum CHSW_STATUS_CODE { + CHSW_OK = 0, + CHSW_NOT_COMPILED_ERR = 1, + CHSW_STOPSER_FAIL_WARN = 2, + CHSW_BB_CTRL_BW_CH_FAIL_ERR = 3, + CHSW_RF_RELOAD_FAIL_WARN = 4, + CHSW_STARTSER_FAIL_WARN = 5, + CHSW_MAX +}; + +/** + * @struct mac_ax_conf_ofld_hdr + * @brief mac_ax_conf_ofld_hdr + * + * @var mac_ax_conf_ofld_hdr::pattern_count + * Please Place Description here. + * @var mac_ax_conf_ofld_hdr::rsvd + * Please Place Description here. + */ +struct mac_ax_conf_ofld_hdr { + u16 pattern_count; + u16 rsvd; +}; + +/** + * @struct mac_ax_pkt_ofld_hdr + * @brief mac_ax_pkt_ofld_hdr + * + * @var mac_ax_pkt_ofld_hdr::pkt_idx + * Please Place Description here. + * @var mac_ax_pkt_ofld_hdr::pkt_op + * Please Place Description here. + * @var mac_ax_pkt_ofld_hdr::rsvd + * Please Place Description here. + * @var mac_ax_pkt_ofld_hdr::pkt_len + * Please Place Description here. + */ +struct mac_ax_pkt_ofld_hdr { + u8 pkt_idx; + u8 pkt_op:3; + u8 rsvd:5; + u16 pkt_len; +}; + +/** + * @struct scanofld_chinfo_node + * @brief scanofld_chinfo_node + * + * @var scanofld_chinfo_node::next + * Point to next node. + * @var scanofld_chinfo_node::chinfo + * Content of this node. + */ +struct scanofld_chinfo_node { + struct scanofld_chinfo_node *next; + struct mac_ax_scanofld_chinfo *chinfo; +}; + +/** + * @struct scan_chinfo_list + * @brief scan_chinfo_list + * + * @var scan_chinfo_head::head + * Point to first node. + * @var scan_chinfo_head::tail + * Point to last node. + * @var scan_chinfo_head::size + * Size of the list + */ +struct scan_chinfo_list { + struct scanofld_chinfo_node *head; + struct scanofld_chinfo_node *tail; + u8 size; +}; + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ +/** + * @brief mac_reset_fwofld_state + * + * @param *adapter + * @param op + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_reset_fwofld_state(struct mac_ax_adapter *adapter, u8 op); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_check_fwofld_done + * + * @param *adapter + * @param op + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_fwofld_done(struct mac_ax_adapter *adapter, u8 op); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_clear_write_request + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_clear_write_request(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_write_request + * + * @param *adapter + * @param *req + * @param *value + * @param *mask + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_write_request(struct mac_ax_adapter *adapter, + struct mac_ax_write_req *req, + u8 *value, u8 *mask); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_write_ofld + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_ofld(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_clear_conf_request + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_clear_conf_request(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_conf_request + * + * @param *adapter + * @param *req + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_conf_request(struct mac_ax_adapter *adapter, + struct mac_ax_conf_ofld_req *req); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_conf_ofld + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_conf_ofld(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_read_pkt_ofld + * + * @param *adapter + * @param id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_pkt_ofld(struct mac_ax_adapter *adapter, u8 id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_del_pkt_ofld + * + * @param *adapter + * @param id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_del_pkt_ofld(struct mac_ax_adapter *adapter, u8 id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_pkt_ofld + * + * @param *adapter + * @param *pkt + * @param len + * @param *id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_pkt_ofld(struct mac_ax_adapter *adapter, u8 *pkt, u16 len, u8 *id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_pkt_ofld_packet + * + * @param *adapter + * @param **pkt_buf + * @param *pkt_len + * @param *pkt_id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pkt_ofld_packet(struct mac_ax_adapter *adapter, + u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_dump_efuse_ofld + * + * @param *adapter + * @param efuse_size + * @param is_hidden + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dump_efuse_ofld(struct mac_ax_adapter *adapter, u32 efuse_size, + bool is_hidden); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_efuse_ofld_map + * + * @param *adapter + * @param *efuse_map + * @param efuse_size + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_efuse_ofld_map(struct mac_ax_adapter *adapter, u8 *efuse_map, + u32 efuse_size); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_clear_read_request + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_clear_read_request(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_read_request + * + * @param *adapter + * @param *req + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_read_request(struct mac_ax_adapter *adapter, + struct mac_ax_read_req *req); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_read_ofld + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_ofld(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_read_ofld_value + * + * @param *adapter + * @param **val_buf + * @param *val_len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_ofld_value(struct mac_ax_adapter *adapter, + u8 **val_buf, u16 *val_len); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_general_pkt_ids + * + * @param *adapter + * @param *ids + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_general_pkt_ids(struct mac_ax_adapter *adapter, + struct mac_ax_general_pkt_ids *ids); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_cmd_ofld + * + * This is the function for FW IO offload. + * Users could call the function to add write BB/RF/MAC REG command. + * When the aggregated commands are full or the command is last, + * FW would receive a H2C containing aggreated IO command. + * + * @param *adapter + * @param *cmd + * @return 0 for success. Others are fail. + * @retval u32 + */ +u32 mac_add_cmd_ofld(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_get_fw_cap + * + * @param *adapter + * @param *val + * @return This function would set FW capability in *val. + * return fail while FW is NOT ready + * @retval u32 + */ +u32 mac_get_fw_cap(struct mac_ax_adapter *adapter, u32 *val); +/** + * @} + * @} + */ + +u32 write_mac_reg_ofld(struct mac_ax_adapter *adapter, + u16 offset, u32 mask, u32 val, u8 lc); + +u32 poll_mac_reg_ofld(struct mac_ax_adapter *adapter, + u16 offset, u32 mask, u32 val, u8 lc); + +u32 delay_ofld(struct mac_ax_adapter *adapter, u32 val); +/** + * @brief mac_ccxrpt_parsing + * + * @param *adapter + * @param *buf + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ccxrpt_parsing(struct mac_ax_adapter *adapter, + u8 *buf, struct mac_ax_ccxrpt *info); + +u32 get_ccxrpt_event(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, u8 *c2h_info); + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_scanofld_ch_list_clear + * + * Clear the scan list + + * @param *adapter + * @param *list + * @return void + * @retval void + */ +void mac_scanofld_ch_list_clear(struct mac_ax_adapter *adapter, + struct scan_chinfo_list *list); + +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_add_scanofld_ch + * + * Add a chinfo to scanlist. + * Note that the user-allocated chinfo must not be free. + * halmac will handle the free process + * + * @param *adapter + * @param *chinfo + * @param send_h2C send scanlist to fw after adding or not + * @param clear_after_send clear halmac scanlist after sending or not(available when sendH2C is set) + * @return 0 for success. Others are fail. + * @retval u32 + */ +u32 mac_add_scanofld_ch(struct mac_ax_adapter *adapter, struct mac_ax_scanofld_chinfo *chinfo, + u8 send_h2C, u8 clear_after_send); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_scanofld + * + * Start scanofld + * + * @param *adapter + * @param *scanParam + * @return 0 for success. Others are fail. + * @retval u32 + */ +void mac_scanofld_reset_state(struct mac_ax_adapter *adapter); + +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_scanofld + * + * Start scanofld + * + * @param *adapter + * @param *scanParam + * @return 0 for success. Others are fail. + * @retval u32 + */ +u32 mac_scanofld(struct mac_ax_adapter *adapter, struct mac_ax_scanofld_param *scanParam); + +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_scanofld_fw_busy + * + * Check whether FW is scanning or not + * + * @param *adapter + * @return 0 for idle. Others are busy. + * @retval u32 + */ +u32 mac_scanofld_fw_busy(struct mac_ax_adapter *adapter); + +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_scanofld_chlist_busy + * + * check whether halmac chlist or fw chlist are busy or not + * + * @param *adapter + * @return 0 for idle. Others are busy. + * @retval u32 + */ +u32 mac_scanofld_chlist_busy(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief ch_switch_ofld + * + * ch switch offload + * + * @param *adapter + * @param parm + * @return 0 for success. + * @retval ch switch offload h2c status + */ +u32 mac_ch_switch_ofld(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_parm parm); +/** + * @} + * @} + */ + +/** + * @addtogroup Firmware + * @{ + * @addtogroup FW_Offload + * @{ + */ + +/** + * @brief mac_get_ch_switch_rpt + * + * get channel switch offload report + * + * @param *adapter + * @param parm + * @return 0 for success. + * @retval ch switch offload h2c status + */ +u32 mac_get_ch_switch_rpt(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_rpt *rpt); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/gpio.c b/phl/hal_g6/mac/mac_ax/gpio.c new file mode 100644 index 0000000..815ea55 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/gpio.c @@ -0,0 +1,735 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "gpio.h" + +u32 mac_sel_uart_tx_pin(struct mac_ax_adapter *adapter, + enum mac_ax_uart_tx_pin uart_pin) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + struct mac_ax_gpio_info *info = &adapter->gpio_info; + u8 val = MAC_REG_R8(R_AX_CAL_TIMER + 3); + u32 ret = MACSUCCESS; + + switch (uart_pin) { + case MAC_AX_UART_TX_GPIO5: + val |= BIT(6); + if (!info->uart_tx_gpio5) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + case MAC_AX_UART_TX_GPIO7: + val &= ~(BIT(7) | BIT(6)); + if (!info->uart_tx_gpio7) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + case MAC_AX_UART_TX_GPIO8: + val |= BIT(7); + if (!info->uart_tx_gpio8) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + case MAC_AX_UART_TX_GPIO5_GPIO8: + val |= (BIT(6) | BIT(7)); + if (!info->uart_tx_gpio8 || !info->uart_tx_gpio5) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + default: + PLTFM_MSG_ERR("Wrong UART GPIO\n"); + ret = MACNOITEM; + break; + } + + MAC_REG_W8(R_AX_CAL_TIMER + 3, val); + + return ret; +} + +u32 mac_sel_uart_rx_pin(struct mac_ax_adapter *adapter, + enum mac_ax_uart_rx_pin uart_pin) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + struct mac_ax_gpio_info *info = &adapter->gpio_info; + u8 val = MAC_REG_R8(R_AX_CAL_TIMER + 3); + u32 ret = MACSUCCESS; + + switch (uart_pin) { + case MAC_AX_UART_RX_GPIO6: + val &= ~BIT(5); + if (!info->uart_rx_gpio6) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + case MAC_AX_UART_RX_GPIO14: + val |= BIT(5); + if (!info->uart_rx_gpio14) + PLTFM_MSG_WARN("Pinmux function is not switched\n"); + break; + default: + PLTFM_MSG_ERR("Wrong UART GPIO\n"); + ret = MACNOITEM; + break; + } + + MAC_REG_W8(R_AX_CAL_TIMER + 3, val); + + return ret; +} + +u32 mac_pinmux_switch(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func gpio_func, + const struct mac_ax_pinmux_list *list, + u32 list_size, u32 gpio_id) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + enum pinmux_name pinmux; + struct mac_ax_pinmux_list const *cur_list; + u32 i; + u8 val; + + switch (gpio_func) { + case MAC_AX_GPIO_SW_IO_0: + case MAC_AX_GPIO_SW_IO_1: + case MAC_AX_GPIO_SW_IO_2: + case MAC_AX_GPIO_SW_IO_3: + case MAC_AX_GPIO_SW_IO_4: + case MAC_AX_GPIO_SW_IO_5: + case MAC_AX_GPIO_SW_IO_6: + case MAC_AX_GPIO_SW_IO_7: + case MAC_AX_GPIO_SW_IO_8: + case MAC_AX_GPIO_SW_IO_9: + case MAC_AX_GPIO_SW_IO_10: + case MAC_AX_GPIO_SW_IO_11: + case MAC_AX_GPIO_SW_IO_12: + case MAC_AX_GPIO_SW_IO_13: + case MAC_AX_GPIO_SW_IO_14: + case MAC_AX_GPIO_SW_IO_15: + pinmux = MAC_AX_SW_IO; + break; + case MAC_AX_GPIO_UART_TX_GPIO5: + case MAC_AX_GPIO_UART_TX_GPIO7: + case MAC_AX_GPIO_UART_TX_GPIO8: + pinmux = MAC_AX_WL_UART_TX; + break; + case MAC_AX_GPIO_UART_RX_GPIO6: + case MAC_AX_GPIO_UART_RX_GPIO14: + pinmux = MAC_AX_WL_UART_RX; + break; + default: + PLTFM_MSG_ERR("Wrong GPIO function\n"); + return MACNOITEM; + } + + cur_list = list; + for (i = 0; i < list_size; i++) { + val = MAC_REG_R8(cur_list->offset); + val &= ~(cur_list->msk); + + if (pinmux == cur_list->func) { + val |= (cur_list->value & cur_list->msk); + MAC_REG_W8(cur_list->offset, val); + break; + } + + val |= (~cur_list->value & cur_list->msk); + MAC_REG_W8(cur_list->offset, val); + + cur_list++; + } + + if (i == list_size) { + PLTFM_MSG_ERR("Get pinmux function error\n"); + return MACNOITEM; + } + + switch (pinmux) { + case MAC_AX_WL_UART_TX: + case MAC_AX_WL_UART_RX: + val = MAC_REG_R8(R_AX_WCPU_FW_CTRL + 3); + MAC_REG_W8(R_AX_WCPU_FW_CTRL + 3, val | BIT(7)); + break; + default: + break; + } + + return MACSUCCESS; +} + +u32 mac_pinmux_record(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func, u8 val) +{ + struct mac_ax_gpio_info *info = &adapter->gpio_info; + + switch (func) { + case MAC_AX_GPIO_SW_IO_0: + info->sw_io_0 = val; + break; + case MAC_AX_GPIO_SW_IO_1: + info->sw_io_1 = val; + break; + case MAC_AX_GPIO_SW_IO_2: + info->sw_io_2 = val; + break; + case MAC_AX_GPIO_SW_IO_3: + info->sw_io_3 = val; + break; + case MAC_AX_GPIO_SW_IO_4: + info->sw_io_4 = val; + break; + case MAC_AX_GPIO_SW_IO_5: + info->sw_io_5 = val; + break; + case MAC_AX_GPIO_SW_IO_6: + info->sw_io_6 = val; + break; + case MAC_AX_GPIO_SW_IO_7: + info->sw_io_7 = val; + break; + case MAC_AX_GPIO_SW_IO_8: + info->sw_io_8 = val; + break; + case MAC_AX_GPIO_SW_IO_9: + info->sw_io_9 = val; + break; + case MAC_AX_GPIO_SW_IO_10: + info->sw_io_10 = val; + break; + case MAC_AX_GPIO_SW_IO_11: + info->sw_io_11 = val; + break; + case MAC_AX_GPIO_SW_IO_12: + info->sw_io_12 = val; + break; + case MAC_AX_GPIO_SW_IO_13: + info->sw_io_13 = val; + break; + case MAC_AX_GPIO_SW_IO_14: + info->sw_io_14 = val; + break; + case MAC_AX_GPIO_SW_IO_15: + info->sw_io_15 = val; + break; + case MAC_AX_GPIO_UART_TX_GPIO5: + info->uart_tx_gpio5 = val; + break; + case MAC_AX_GPIO_UART_TX_GPIO7: + info->uart_tx_gpio7 = val; + break; + case MAC_AX_GPIO_UART_TX_GPIO8: + info->uart_tx_gpio8 = val; + break; + case MAC_AX_GPIO_UART_RX_GPIO6: + info->uart_rx_gpio6 = val; + break; + case MAC_AX_GPIO_UART_RX_GPIO14: + info->uart_rx_gpio14 = val; + break; + default: + PLTFM_MSG_ERR("Wrong GPIO function\n"); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_pinmux_status(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func) +{ + struct mac_ax_gpio_info *info = &adapter->gpio_info; + u32 ret = MACSUCCESS; + + switch (func) { + case MAC_AX_GPIO_SW_IO_0: + if (info->sw_io_0) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_1: + if (info->sw_io_1) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_2: + if (info->sw_io_2) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_3: + if (info->sw_io_3) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_4: + if (info->sw_io_4) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_5: + if (info->sw_io_5 || info->uart_tx_gpio5 || + info->uart_tx_gpio7 || info->uart_tx_gpio8) + goto GPIO_USED; + break; + case MAC_AX_GPIO_UART_TX_GPIO5: + if (info->sw_io_5 || info->uart_tx_gpio5) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_6: + if (info->sw_io_6 || info->uart_rx_gpio6 || + info->uart_rx_gpio14) + goto GPIO_USED; + break; + case MAC_AX_GPIO_UART_RX_GPIO6: + if (info->sw_io_6 || info->uart_rx_gpio6) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_7: + if (info->sw_io_7 || info->uart_tx_gpio5 || + info->uart_tx_gpio7 || info->uart_tx_gpio8) + goto GPIO_USED; + break; + case MAC_AX_GPIO_UART_TX_GPIO7: + if (info->sw_io_7 || info->uart_tx_gpio7) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_8: + if (info->sw_io_8 || info->uart_tx_gpio5 || + info->uart_tx_gpio7 || info->uart_tx_gpio8) + goto GPIO_USED; + break; + case MAC_AX_GPIO_UART_TX_GPIO8: + if (info->sw_io_8 || info->uart_tx_gpio8) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_9: + if (info->sw_io_9) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_10: + if (info->sw_io_10) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_11: + if (info->sw_io_11) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_12: + if (info->sw_io_12) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_13: + if (info->sw_io_13) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_14: + if (info->sw_io_14 || info->uart_rx_gpio6 || + info->uart_rx_gpio14) + goto GPIO_USED; + break; + case MAC_AX_GPIO_UART_RX_GPIO14: + if (info->sw_io_14 || info->uart_rx_gpio14) + goto GPIO_USED; + break; + case MAC_AX_GPIO_SW_IO_15: + if (info->sw_io_15) + goto GPIO_USED; + break; + default: + ret = MACNOITEM; + PLTFM_MSG_ERR("Wrong GPIO function\n"); + } + + return ret; +GPIO_USED: + ret = MACGPIOUSED; + return ret; +} + +u32 mac_pinmux_free_func(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func) +{ + return mac_pinmux_record(adapter, func, 0); +} + +u8 get_led_gpio(u8 led_id) +{ +/* LED 0 -> GPIO8 */ + switch (led_id) { + case 0: + return 8; + default: + return 0xFF; + } +} + +u32 mac_set_led_mode(struct mac_ax_adapter *adapter, + enum mac_ax_led_mode mode, u8 led_id) +{ +#define LED_MODE_SW_CTRL 0 +#define LED_MODE_AON 1 +#define LED_MODE_TRX_ON 2 +#define LED_MODE_TRX_OFF 3 +#define LED_MODE_TX_ON 4 +#define LED_MODE_TX_OFF 5 +#define LED_MODE_RX_ON 6 +#define LED_MODE_RX_OFF 7 + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + struct mac_ax_ops *mac_ops = adapter->ops; + u32 val, ret; + u8 tmp, gpio; + + gpio = get_led_gpio(led_id); + if (gpio == 0xFF) { + PLTFM_MSG_ERR("%s: Wrong LED ID: %d", __func__, led_id); + ret = MACNOITEM; + goto END; + } + + val = MAC_REG_R32(R_AX_LED_CFG); + + switch (mode) { + case MAC_AX_LED_MODE_TRX_ON: + tmp = LED_MODE_TRX_ON; + break; + case MAC_AX_LED_MODE_TX_ON: + tmp = LED_MODE_TX_ON; + break; + case MAC_AX_LED_MODE_RX_ON: + tmp = LED_MODE_RX_ON; + break; + case MAC_AX_LED_MODE_SW_CTRL_OD: + /* use SW IO to control LED */ + ret = mac_set_sw_gpio_mode(adapter, + RTW_AX_SW_IO_MODE_OUTPUT_OD, 8); + if (ret) + PLTFM_MSG_ERR("%s: config SW GPIO fail: %d", + __func__, ret); + goto END; + case MAC_AX_LED_MODE_SW_CTRL_PP: + /* use SW IO to control LED */ + ret = mac_set_sw_gpio_mode(adapter, + RTW_AX_SW_IO_MODE_OUTPUT_PP, 8); + if (ret) + PLTFM_MSG_ERR("%s: config SW GPIO fail: %d", + __func__, ret); + goto END; + default: + PLTFM_MSG_ERR("%s: Wrong LED mode: %d", __func__, mode); + return MACNOITEM; + } + + ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_WL_LED, gpio); + if (ret) { + PLTFM_MSG_ERR("%s: Config LED pinmux fail", __func__); + goto END; + } + + val = SET_CLR_WORD(val, tmp, B_AX_LED2CM); + val = val & ~(B_AX_GPIO13_14_WL_CTRL_EN); + MAC_REG_W32(R_AX_LED_CFG, val); + +END: + return ret; +} + +u32 mac_led_ctrl(struct mac_ax_adapter *adapter, + u8 high, u8 led_id) +{ + u32 ret = MACSUCCESS; + u8 gpio; + + gpio = get_led_gpio(led_id); + if (gpio == 0xFF) { + PLTFM_MSG_ERR("%s: Wrong LED ID: %d", __func__, led_id); + ret = MACNOITEM; + goto END; + } + + /* use SW IO to control LED */ + ret = mac_sw_gpio_ctrl(adapter, high, gpio); + +END: + return ret; +} + +u32 _mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter, + u8 output, u8 gpio) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + u32 reg; + u16 val16; + u8 in_out; + + if (gpio <= 7) { + reg = R_AX_GPIO_PIN_CTRL + 2; + } else if (gpio >= 8 && gpio <= 15) { + reg = R_AX_GPIO_EXT_CTRL + 2; + gpio = gpio - 8; + } else { + PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio); + return MACNOITEM; + } + + in_out = (output == 0) ? 0 : 1; + + val16 = MAC_REG_R16(reg); + val16 = (val16 & ~((u16)BIT(gpio) | (u16)BIT(gpio + 8))) | + (u16)(in_out << gpio) | (u16)(in_out << gpio << 8); + MAC_REG_W16(reg, val16); + + return MACSUCCESS; +} + +u32 mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter, + enum rtw_gpio_mode mode, u8 gpio) +{ + struct mac_ax_ops *mac_ops = adapter->ops; + struct mac_ax_gpio_info *gpio_info = &adapter->gpio_info; + u32 ret; + + ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_SW_IO, gpio); + if (ret) { + PLTFM_MSG_ERR("%s: Config SW IO pinmux fail", __func__); + return ret; + } + + switch (mode) { + case RTW_AX_SW_IO_MODE_INPUT: + ret = _mac_set_sw_gpio_mode(adapter, 0, gpio); + break; + case RTW_AX_SW_IO_MODE_OUTPUT_OD: + ret = _mac_set_sw_gpio_mode(adapter, 0, gpio); + gpio_info->sw_io_output[gpio] = MAC_AX_SW_IO_OUT_OD; + break; + case RTW_AX_SW_IO_MODE_OUTPUT_PP: + ret = _mac_set_sw_gpio_mode(adapter, 1, gpio); + gpio_info->sw_io_output[gpio] = MAC_AX_SW_IO_OUT_PP; + break; + default: + PLTFM_MSG_ERR("%s: Wrong SW GPIO mode: %d", __func__, mode); + ret = MACNOITEM; + break; + } + + return ret; +} + +u32 mac_sw_gpio_ctrl(struct mac_ax_adapter *adapter, + u8 high, u8 gpio) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + struct mac_ax_gpio_info *gpio_info = &adapter->gpio_info; + u32 reg, ret; + u8 ctrl, val8; + + if (gpio >= MAC_AX_GPIO_NUM) { + PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio); + ret = MACNOITEM; + goto END; + } + + if (high && gpio_info->sw_io_output[gpio] == MAC_AX_SW_IO_OUT_OD) { + ret = _mac_set_sw_gpio_mode(adapter, 0, gpio); + } else { + ret = _mac_set_sw_gpio_mode(adapter, 1, gpio); + if (ret) { + PLTFM_MSG_ERR("%s: Set GPIO mode fail\n", __func__); + goto END; + } + + if (gpio <= 7) { + reg = R_AX_GPIO_PIN_CTRL + 1; + } else { + reg = R_AX_GPIO_EXT_CTRL + 1; + gpio = gpio - 8; + } + + ctrl = (high == 0) ? 0 : 1; + + val8 = MAC_REG_R8(reg); + val8 = (val8 & ~((u8)BIT(gpio))) | (u8)(ctrl << gpio); + MAC_REG_W8(reg, val8); + } + +END: + return ret; +} + +enum rtw_mac_gfunc mac_get_gpio_status(struct mac_ax_adapter *adapter, + const struct mac_ax_pin_list *list) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + u8 val; + enum rtw_mac_gfunc curr = RTW_MAC_GPIO_INVALID; + + while (list->func != RTW_MAC_GPIO_LAST) { + /* first fit list*/ + if (curr != list->func && + list->offset >= R_AX_GPIO0_7_FUNC_SEL && + list->offset <= R_AX_EECS_EESK_FUNC_SEL) { + curr = list->func; + val = MAC_REG_R8(list->offset); + if ((val & list->msk) == list->value) + return list->func; + } + list++; + } + + return RTW_MAC_GPIO_INVALID; +} + +u32 mac_cfg_wps(struct mac_ax_adapter *adapter, + struct mac_ax_cfg_wps *wps) +{ + u32 ret; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_cfg_wps *ptr; + struct mac_ax_gpio_info *info = &adapter->gpio_info; + + if (wps->gpio > RTW_MAC_GPIO_MAX) { + PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, wps->gpio); + return MACGPIONUM; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + ptr = (struct fwcmd_cfg_wps *)h2cb_put(h2cb, sizeof(*ptr)); + if (!ptr) { + ret = MACNOBUF; + goto fail; + } + PLTFM_MEMSET(ptr, 0, sizeof(*ptr)); + + ptr->dword0 = cpu_to_le32((wps->en ? FWCMD_H2C_CFG_WPS_EN : 0) | + SET_WORD(wps->gpio, + FWCMD_H2C_CFG_WPS_GPIO) | + SET_WORD(wps->interval, + FWCMD_H2C_CFG_WPS_INTL)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MISC, + FWCMD_H2C_FUNC_CFG_WPS, + 0, + 0); + + if (ret != MACSUCCESS) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + goto fail; + } + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + if (info->status[wps->gpio] != RTW_MAC_GPIO_DFLT && + info->status[wps->gpio] != RTW_MAC_GPIO_SW_IO) + PLTFM_MSG_WARN("The gpio%d is %d\n", + wps->gpio, info->status[wps->gpio]); + + info->status[wps->gpio] = RTW_MAC_GPIO_SW_IO; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_get_gpio_val(struct mac_ax_adapter *adapter, u8 gpio, u8 *val) +{ + struct mac_ax_intf_ops *ops = adapter->ops->intf_ops; + u32 reg; + + if (gpio <= 7) { + reg = R_AX_GPIO_PIN_CTRL; + } else if (gpio >= 8 && gpio <= 15) { + reg = R_AX_GPIO_EXT_CTRL; + gpio = gpio - 8; + } else { + PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio); + return MACNOITEM; + } + + *val = !!(MAC_REG_R8(reg) & BIT(gpio)); + + return MACSUCCESS; +} + +u32 mac_get_wl_dis_gpio(struct mac_ax_adapter *adapter, u8 *gpio) +{ +#define MAC_AX_HCI_SEL_SDIO_UART 0 +#define MAC_AX_HCI_SEL_USB_MULT 1 +#define MAC_AX_HCI_SEL_PCIE_UART 2 +#define MAC_AX_HCI_SEL_PCIE_USB 3 +#define MAC_AX_HCI_SEL_SDIO_MULT 4 +#define MAC_AX_HCI_SEL_PCIE_G1_UART 6 +#define MAC_AX_HCI_SEL_PCIE_G1_USB 7 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val; + + val = MAC_REG_R32(R_AX_SYS_STATUS1); + val = GET_FIELD(val, B_AX_HCI_SEL_V4); + + switch (val) { + case MAC_AX_HCI_SEL_SDIO_UART: + case MAC_AX_HCI_SEL_USB_MULT: + case MAC_AX_HCI_SEL_PCIE_UART: + case MAC_AX_HCI_SEL_PCIE_USB: + case MAC_AX_HCI_SEL_PCIE_G1_UART: + case MAC_AX_HCI_SEL_PCIE_G1_USB: + *gpio = 9; + break; + case MAC_AX_HCI_SEL_SDIO_MULT: + *gpio = 15; + break; + default: + PLTFM_MSG_ERR("%s: Wrong HCI\n", __func__); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_get_wl_dis_val(struct mac_ax_adapter *adapter, u8 *val) +{ + u8 gpio; + u32 ret; + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + + ret = mac_get_wl_dis_gpio(adapter, &gpio); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: Get WL_DIS GPIO fail\n", __func__); + return ret; + } + + ret = ops->set_sw_gpio_mode(adapter, RTW_AX_SW_IO_MODE_INPUT, gpio); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: Set SW output mode fail\n", __func__); + return ret; + } + + return mac_get_gpio_val(adapter, gpio, val); +} + diff --git a/phl/hal_g6/mac/mac_ax/gpio.h b/phl/hal_g6/mac/mac_ax/gpio.h new file mode 100644 index 0000000..722980b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/gpio.h @@ -0,0 +1,318 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_GPIO_H_ +#define _MAC_AX_GPIO_H_ + +#include "../type.h" +#include "gpio_cmd.h" + +#define DFLT_GPIO_STATE \ + {RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \ + RTW_MAC_GPIO_DFLT} + +#define DFLT_SW_IO_MODE \ + {0, 0, 0, 0, \ + 0, 0, 0, 0, \ + 0, 0, 0, 0, \ + 0, 0, 0, 0} + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ +/** + * @brief mac_sel_uart_tx_pin + * + * @param *adapter + * @param uart_pin + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sel_uart_tx_pin(struct mac_ax_adapter *adapter, + enum mac_ax_uart_tx_pin uart_pin); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_pinmux_status + * + * @param *adapter + * @param func + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pinmux_status(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_pinmux_free_func + * + * @param *adapter + * @param func + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pinmux_free_func(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_pinmux_record + * + * @param *adapter + * @param func + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pinmux_record(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func, u8 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_pinmux_switch + * + * @param *adapter + * @param gpio_func + * @param *list + * @param list_size + * @param gpio_id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pinmux_switch(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func gpio_func, + const struct mac_ax_pinmux_list *list, + u32 list_size, u32 gpio_id); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_sel_uart_rx_pin + * + * @param *adapter + * @param uart_pin + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sel_uart_rx_pin(struct mac_ax_adapter *adapter, + enum mac_ax_uart_rx_pin uart_pin); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_set_led_mode + * + * @param *adapter + * @param mode + * @param led_id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_led_mode(struct mac_ax_adapter *adapter, + enum mac_ax_led_mode mode, u8 led_id); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_led_ctrl + * + * @param *adapter + * @param high + * @param led_id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_led_ctrl(struct mac_ax_adapter *adapter, + u8 high, u8 led_id); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_sw_gpio_ctrl + * + * @param *adapter + * @param high + * @param gpio + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sw_gpio_ctrl(struct mac_ax_adapter *adapter, + u8 high, u8 gpio); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_set_sw_gpio_mode + * + * @param *adapter + * @param mode + * @param gpio + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter, + enum rtw_gpio_mode mode, u8 gpio); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_get_gpio_status + * + * @param *adapter + * @param *list + * @return Please Place Description here. + * @retval rtw_mac_gfunc + */ +enum rtw_mac_gfunc mac_get_gpio_status(struct mac_ax_adapter *adapter, + const struct mac_ax_pin_list *list); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup GPIO + * @{ + */ + +/** + * @brief mac_cfg_wps + * + * WPS is a driver feature to detect button pressed or released. + * In HW view, the feature is to check the GPIO input value is 0->1 or 1->0 + * We use FW to detect GPIO val. + * In a specified interval, if FW detects value changed, it will send a C2H + * + * @param *adapter + * @param *wps + * @return 0 for succcess, others for fail + * @retval u32 + */ +u32 mac_cfg_wps(struct mac_ax_adapter *adapter, + struct mac_ax_cfg_wps *wps); +/** + * @} + * @} + */ +u32 mac_get_gpio_val(struct mac_ax_adapter *adapter, u8 gpio, u8 *val); +u32 mac_get_wl_dis_val(struct mac_ax_adapter *adapter, u8 *val); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/gpio_cmd.h b/phl/hal_g6/mac/mac_ax/gpio_cmd.h new file mode 100644 index 0000000..41eee5c --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/gpio_cmd.h @@ -0,0 +1,321 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_GPIO_CMD_H_ +#define _MAC_AX_GPIO_CMD_H_ + +#include "../type.h" + +#define MAC_AX_GPIO_MIN 0 +#define RTW_MAC_GPIO_MAX 17 + +/** + * @enum pinmux_name + * + * @brief pinmux_name + * + * @var pinmux_name::MAC_AX_WL_HWPDN + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_HWPDN + * Please Place Description here. + * @var pinmux_name::MAC_AX_SWGPIO + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_HW_EXTWOL + * Please Place Description here. + * @var pinmux_name::MAC_AX_SIC + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_SFALSH + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_SFALSH + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_LED + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_SDIO_INT + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_SDIO_INT + * Please Place Description here. + * @var pinmux_name::MAC_AX_UART + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_JTAG + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_JTAG + * Please Place Description here. + * @var pinmux_name::MAC_AX_LTE_UART + * Please Place Description here. + * @var pinmux_name::MAC_AX_LTE_3W + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_GPIO16 + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_OSC + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_OSC + * Please Place Description here. + * @var pinmux_name::MAC_AX_GPIO13_14_WL_CTRL_EN + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_RF + * Please Place Description here. + * @var pinmux_name::MAC_AX_DBG_GNT + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_3DDLS_A + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_3DDLS_B + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_GPIO18 + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_PTA + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_PTA + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_UART_TX + * Please Place Description here. + * @var pinmux_name::MAC_AX_WL_UART_RX + * Please Place Description here. + * @var pinmux_name::MAC_AX_WLMAC_DBG + * Please Place Description here. + * @var pinmux_name::MAC_AX_WLPHY_DBG + * Please Place Description here. + * @var pinmux_name::MAC_AX_BT_DBG + * Please Place Description here. + * @var pinmux_name::MAC_AX_MAILBOX_3W + * Please Place Description here. + * @var pinmux_name::MAC_AX_MAILBOX_1W + * Please Place Description here. + * @var pinmux_name::MAC_AX_PAON_LNAON_2G_S0 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_0 + * Please Place Description here. + * @var pinmux_name::MAC_AX_PAON_LNAON_2G_S1 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_1 + * Please Place Description here. + * @var pinmux_name::MAC_AX_PAON_LNAON_5G_S0 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_2 + * Please Place Description here. + * @var pinmux_name::MAC_AX_PAON_LNAON_5G_S1 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_3 + * Please Place Description here. + * @var pinmux_name::MAC_AX_BANDSEL_5_6G + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_4 + * Please Place Description here. + * @var pinmux_name::MAC_AX_BANDSEL_5G + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_5 + * Please Place Description here. + * @var pinmux_name::MAC_AX_PAON_LNAON_6G_S1 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_7 + * Please Place Description here. + * @var pinmux_name::MAC_AX_BANDSEL_5G_G7G6 + * Please Place Description here. + * @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_8 + * Please Place Description here. + * @var pinmux_name::MAC_AX_EXT_XTAL_CLK + * Please Place Description here. + * @var pinmux_name::MAC_AX_SW_IO + * Please Place Description here. + */ +enum pinmux_name { + MAC_AX_WL_HWPDN, + MAC_AX_BT_HWPDN, + MAC_AX_SWGPIO, + MAC_AX_WL_HW_EXTWOL, + MAC_AX_SIC, + MAC_AX_BT_SFALSH, + MAC_AX_WL_SFALSH, + MAC_AX_WL_LED, + MAC_AX_WL_SDIO_INT, + MAC_AX_BT_SDIO_INT, + MAC_AX_UART, + MAC_AX_BT_JTAG, + MAC_AX_WL_JTAG, + MAC_AX_LTE_UART, + MAC_AX_LTE_3W, + MAC_AX_BT_GPIO16, + MAC_AX_WL_OSC, + MAC_AX_BT_OSC, + MAC_AX_GPIO13_14_WL_CTRL_EN, + MAC_AX_BT_RF, + MAC_AX_DBG_GNT, + MAC_AX_BT_3DDLS_A, + MAC_AX_BT_3DDLS_B, + MAC_AX_BT_GPIO18, + MAC_AX_BT_PTA, + MAC_AX_WL_PTA, + MAC_AX_WL_UART_TX, + MAC_AX_WL_UART_RX, + MAC_AX_WLMAC_DBG, + MAC_AX_WLPHY_DBG, + MAC_AX_BT_DBG, + MAC_AX_MAILBOX_3W, + MAC_AX_MAILBOX_1W, + MAC_AX_PAON_LNAON_2G_S0, + MAC_AX_RFE_WLBT_FUNC_0, + MAC_AX_PAON_LNAON_2G_S1, + MAC_AX_RFE_WLBT_FUNC_1, + MAC_AX_PAON_LNAON_5G_S0, + MAC_AX_RFE_WLBT_FUNC_2, + MAC_AX_PAON_LNAON_5G_S1, + MAC_AX_RFE_WLBT_FUNC_3, + MAC_AX_BANDSEL_5_6G, + MAC_AX_RFE_WLBT_FUNC_4, + MAC_AX_BANDSEL_5G, + MAC_AX_RFE_WLBT_FUNC_5, + MAC_AX_PAON_LNAON_6G_S1, + MAC_AX_RFE_WLBT_FUNC_7, + MAC_AX_BANDSEL_5G_G7G6, + MAC_AX_RFE_WLBT_FUNC_8, + MAC_AX_EXT_XTAL_CLK, + MAC_AX_SW_IO, +}; + +/** + * @enum pinmux_gpio + * + * @brief pinmux_gpio + * + * @var pinmux_gpio::MAC_AX_GPIO0 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO1 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO2 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO3 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO4 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO5 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO6 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO7 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO8 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO9 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO10 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO11 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO12 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO13 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO14 + * Please Place Description here. + * @var pinmux_gpio::MAC_AX_GPIO15 + * Please Place Description here. + */ +enum pinmux_gpio { + MAC_AX_GPIO0, + MAC_AX_GPIO1, + MAC_AX_GPIO2, + MAC_AX_GPIO3, + MAC_AX_GPIO4, + MAC_AX_GPIO5, + MAC_AX_GPIO6, + MAC_AX_GPIO7, + MAC_AX_GPIO8, + MAC_AX_GPIO9, + MAC_AX_GPIO10, + MAC_AX_GPIO11, + MAC_AX_GPIO12, + MAC_AX_GPIO13, + MAC_AX_GPIO14, + MAC_AX_GPIO15, +}; + +/** + * @enum pinmux_gpio_type + * + * @brief pinmux_gpio_type + * + * @var pinmux_gpio_type::MAC_AX_GPIO_IN + * Please Place Description here. + * @var pinmux_gpio_type::MAC_AX_GPIO_OUT + * Please Place Description here. + * @var pinmux_gpio_type::MAC_AX_GPIO_IN_OUT + * Please Place Description here. + */ +enum pinmux_gpio_type { + MAC_AX_GPIO_IN, + MAC_AX_GPIO_OUT, + MAC_AX_GPIO_IN_OUT, +}; + +/** + * @struct mac_ax_pinmux_list + * @brief mac_ax_pinmux_list + * + * @var mac_ax_pinmux_list::func + * Please Place Description here. + * @var mac_ax_pinmux_list::id + * Please Place Description here. + * @var mac_ax_pinmux_list::type + * Please Place Description here. + * @var mac_ax_pinmux_list::offset + * Please Place Description here. + * @var mac_ax_pinmux_list::msk + * Please Place Description here. + * @var mac_ax_pinmux_list::value + * Please Place Description here. + */ +struct mac_ax_pinmux_list { + enum pinmux_name func; + enum pinmux_gpio id; + enum pinmux_gpio_type type; + u32 offset; + u8 msk; + u8 value; +}; + +/** + * @struct mac_ax_pin_list + * @brief mac_ax_pin_list + * + * @var mac_ax_pin_list::func + * Please Place Description here. + * @var mac_ax_pin_list::offset + * Please Place Description here. + * @var mac_ax_pin_list::msk + * Please Place Description here. + * @var mac_ax_pin_list::value + * Please Place Description here. + */ +struct mac_ax_pin_list { + enum rtw_mac_gfunc func; + u32 offset; + u8 msk; + u8 value; +}; + +/** + * @struct mac_ax_gpio_func_list + * @brief mac_ax_gpio_func_list + * + * @var mac_ax_gpio_func_list::func + * Please Place Description here. + * @var mac_ax_gpio_func_list::list + * Please Place Description here. + */ +struct mac_ax_gpio_func_list { + enum rtw_mac_gfunc func; + struct mac_ax_pin_list *list; +}; +#endif diff --git a/phl/hal_g6/mac/mac_ax/h2c_agg.c b/phl/hal_g6/mac/mac_ax/h2c_agg.c new file mode 100644 index 0000000..8bbad04 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/h2c_agg.c @@ -0,0 +1,243 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "h2c_agg.h" + +static u32 mac_h2c_agg_tx_single_normal_h2c(struct mac_ax_adapter *adapter, u8 *h2cb) +{ +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *tx_h2cb = (struct rtw_h2c_pkt *)h2cb; +#else + struct h2c_buf *tx_h2cb = (struct h2c_buf *)h2cb; +#endif + u32 ret = MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, tx_h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(tx_h2cb); +#else + ret = PLTFM_TX(tx_h2cb->data, tx_h2cb->len); + if (ret) + goto fail; + h2cb_free(adapter, tx_h2cb); +#endif + +fail: + return ret; +} + +static u32 mac_h2c_agg_tx_single_agg_h2c(struct mac_ax_adapter *adapter, u8 *agg_h2cb) +{ +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *tx_h2cb = (struct rtw_h2c_pkt *)agg_h2cb; +#else + struct h2c_buf *tx_h2cb = (struct h2c_buf *)agg_h2cb; +#endif + u32 ret = MACSUCCESS; + + ret = h2c_pkt_set_hdr(adapter, + tx_h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_H2C_AGG, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, tx_h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(tx_h2cb); +#else + ret = PLTFM_TX(tx_h2cb->data, tx_h2cb->len); + if (ret) + goto fail; + h2cb_free(adapter, tx_h2cb); +#endif + +fail: + return ret; +} + +void mac_h2c_agg_enable(struct mac_ax_adapter *adapter, u8 enable) +{ + PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock); + adapter->h2c_agg_info.h2c_agg_en = enable; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock); +} + +u32 mac_h2c_agg_tx(struct mac_ax_adapter *adapter) +{ +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *agg_h2cb = NULL; + struct rtw_h2c_pkt *cur_h2cb = NULL; +#else + struct h2c_buf *agg_h2cb = NULL; + struct h2c_buf *cur_h2cb = NULL; +#endif + struct mac_ax_h2c_agg_node *cur_agg_node = NULL; + struct mac_ax_h2c_agg_node *tmp_agg_node = NULL; + u32 agg_len = 0; + u32 cur_h2cb_len = 0; + u32 cur_sub_h2c_len = 0; + u32 cur_sub_h2c_len_swap = 0; + u32 next_h2cb_len = 0; + u32 ret = MACSUCCESS; + u8 *cur_h2cb_data = NULL; + u8 *buf = NULL; + + PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock); + + if (!adapter->h2c_agg_info.h2c_agg_queue_head) + goto fail; + + cur_agg_node = adapter->h2c_agg_info.h2c_agg_queue_head; + agg_h2cb = NULL; + agg_len = 0; + + while (cur_agg_node) { +#if MAC_AX_PHL_H2C + cur_h2cb = (struct rtw_h2c_pkt *)cur_agg_node->h2c_pkt; + cur_h2cb_len = cur_h2cb->data_len; + cur_h2cb_data = cur_h2cb->vir_data; + next_h2cb_len = (!cur_agg_node->next ? 0 : + ((struct rtw_h2c_pkt *) + (cur_agg_node->next->h2c_pkt))->data_len); +#else + cur_h2cb = (struct h2c_buf *)cur_agg_node->h2c_pkt; + cur_h2cb_len = cur_h2cb->len; + cur_h2cb_data = cur_h2cb->data; + next_h2cb_len = (!cur_agg_node->next ? 0 : + ((struct h2c_buf *) + (cur_agg_node->next->h2c_pkt))->len); +#endif + + if (!agg_h2cb) { + if (!H2C_PKT_AGGREGATABLE(cur_h2cb_len) || + !cur_agg_node->next || + (cur_agg_node->next && + !H2C_PKT_AGGREGATABLE(next_h2cb_len))) { + ret = mac_h2c_agg_tx_single_normal_h2c(adapter, (u8 *)cur_h2cb); + if (ret) { + PLTFM_MSG_ERR("tx normal h2c pkt fail\n"); + goto fail; + } + + tmp_agg_node = cur_agg_node; + cur_agg_node = cur_agg_node->next; + adapter->h2c_agg_info.h2c_agg_queue_head = cur_agg_node; + PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node)); + continue; + } + + agg_h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!agg_h2cb) { + PLTFM_MSG_ERR("allocate agg_h2c fail\n"); + ret = MACNOBUF; + goto fail; + } + agg_len = WD_BODY_LEN + FWCMD_HDR_LEN; + } + + cur_sub_h2c_len = ALIGN_4_BYTE(cur_h2cb_len); + + buf = h2cb_put(agg_h2cb, cur_sub_h2c_len + H2C_AGG_SUB_HDR_LEN); + if (!buf) { + PLTFM_MSG_ERR("creat sub_h2c_buf in agg_h2cb get fail\n"); + ret = MACNOITEM; + goto fail; + } + + cur_sub_h2c_len_swap = cpu_to_le32(cur_sub_h2c_len); + PLTFM_MEMCPY(buf, &cur_sub_h2c_len_swap, H2C_AGG_SUB_HDR_LEN); + PLTFM_MEMCPY(buf + H2C_AGG_SUB_HDR_LEN, cur_h2cb_data, cur_h2cb_len); + agg_len = agg_len + cur_sub_h2c_len + H2C_AGG_SUB_HDR_LEN; + + tmp_agg_node = cur_agg_node; + cur_agg_node = cur_agg_node->next; + adapter->h2c_agg_info.h2c_agg_queue_head = cur_agg_node; + PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node)); + +#if MAC_AX_PHL_H2C + PLTFM_RECYCLE_H2C(cur_h2cb); +#else + h2cb_free(adapter, cur_h2cb); +#endif + + if (!cur_agg_node || + ((agg_len + ALIGN_4_BYTE(next_h2cb_len) + + H2C_AGG_SUB_HDR_LEN) >= H2C_LONG_DATA_LEN)) { + ret = mac_h2c_agg_tx_single_agg_h2c(adapter, (u8 *)agg_h2cb); + if (ret) { + PLTFM_MSG_ERR("tx normal agg_h2c pkt fail\n"); + goto fail; + } + agg_h2cb = NULL; + agg_len = 0; + } + } + +fail: + if (ret) { + PLTFM_MSG_ERR("h2c agg error handle\n"); + + mac_h2c_agg_flush(adapter); + + if (agg_h2cb) { +#if MAC_AX_PHL_H2C + PLTFM_RECYCLE_H2C((struct rtw_h2c_pkt *)agg_h2cb); +#else + h2cb_free(adapter, agg_h2cb); +#endif + } + } else { + adapter->h2c_agg_info.h2c_agg_queue_head = NULL; + adapter->h2c_agg_info.h2c_agg_queue_last = NULL; + adapter->h2c_agg_info.h2c_agg_pkt_num = 0; + } + PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock); + return ret; +} + +void mac_h2c_agg_flush(struct mac_ax_adapter *adapter) +{ + struct mac_ax_h2c_agg_node *cur_agg_node = NULL; + struct mac_ax_h2c_agg_node *tmp_agg_node = NULL; + + PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock); + cur_agg_node = adapter->h2c_agg_info.h2c_agg_queue_head; + + while (cur_agg_node) { +#if MAC_AX_PHL_H2C + PLTFM_RECYCLE_H2C((struct rtw_h2c_pkt *)cur_agg_node->h2c_pkt); +#else + h2cb_free(adapter, (struct h2c_buf *)cur_agg_node->h2c_pkt); +#endif + tmp_agg_node = cur_agg_node; + cur_agg_node = cur_agg_node->next; + PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node)); + } + + adapter->h2c_agg_info.h2c_agg_queue_head = NULL; + adapter->h2c_agg_info.h2c_agg_queue_last = NULL; + adapter->h2c_agg_info.h2c_agg_pkt_num = 0; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock); +} diff --git a/phl/hal_g6/mac/mac_ax/h2c_agg.h b/phl/hal_g6/mac/mac_ax/h2c_agg.h new file mode 100644 index 0000000..e036844 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/h2c_agg.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _H2C_AGG_H_ +#define _H2C_AGG_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "../fw_ax/inc_hdr/fwcmd_intf.h" + +#define ALIGN_4_BYTE(len) ((len + 0x3) & ~(0x3)) +#define H2C_AGG_SUB_HDR_LEN sizeof(u32) +#define H2C_PKT_AGGREGATABLE(len) ((ALIGN_4_BYTE(len) + \ + WD_BODY_LEN + FWCMD_HDR_LEN + \ + H2C_AGG_SUB_HDR_LEN) \ + < H2C_LONG_DATA_LEN) + +void mac_h2c_agg_flush(struct mac_ax_adapter *adapter); +u32 mac_h2c_agg_tx(struct mac_ax_adapter *adapter); +void mac_h2c_agg_enable(struct mac_ax_adapter *adapter, u8 enable); +#endif diff --git a/phl/hal_g6/mac/mac_ax/hci_fc.c b/phl/hal_g6/mac/mac_ax/hci_fc.c new file mode 100644 index 0000000..4698619 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hci_fc.c @@ -0,0 +1,1735 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "hci_fc.h" + +static u32 chcfg_size = sizeof(struct mac_ax_hfc_ch_cfg) * MAC_AX_DMA_CH_NUM; + +static u32 chinfo_size = sizeof(struct mac_ax_hfc_ch_info) * MAC_AX_DMA_CH_NUM; + +#if MAC_AX_PCIE_SUPPORT +#ifdef PHL_FEATURE_AP +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852a[] = { + {16, 3792, grp_0}, /* ACH 0 */ + {16, 3792, grp_0}, /* ACH 1 */ + {16, 3792, grp_0}, /* ACH 2 */ + {16, 3792, grp_0}, /* ACH 3 */ + {8, 3792, grp_0}, /* ACH 4 */ + {8, 3792, grp_0}, /* ACH 5 */ + {8, 3792, grp_0}, /* ACH 6 */ + {8, 3792, grp_0}, /* ACH 7 */ + {16, 3792, grp_0}, /* B0MGQ */ + {16, 3792, grp_0}, /* B0HIQ */ + {8, 3792, grp_0}, /* B1MGQ */ + {8, 3792, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; +#else // for NiC mode use +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852a[] = { + {16, 3276, grp_0}, /* ACH 0 */ + {16, 3276, grp_0}, /* ACH 1 */ + {16, 3276, grp_0}, /* ACH 2 */ + {16, 3276, grp_0}, /* ACH 3 */ + {8, 3284, grp_0}, /* ACH 4 */ + {8, 3284, grp_0}, /* ACH 5 */ + {8, 3284, grp_0}, /* ACH 6 */ + {8, 3284, grp_0}, /* ACH 7 */ + {16, 3276, grp_0}, /* B0MGQ */ + {16, 3276, grp_0}, /* B0HIQ */ + {8, 3284, grp_0}, /* B1MGQ */ + {8, 3284, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; +#endif + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852b[] = { + {16, 744, grp_0}, /* ACH 0 */ + {16, 744, grp_0}, /* ACH 1 */ + {16, 744, grp_0}, /* ACH 2 */ + {16, 744, grp_0}, /* ACH 3 */ + {0, 0, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {0, 0, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {16, 744, grp_0}, /* B0MGQ */ + {16, 744, grp_0}, /* B0HIQ */ + {0, 0, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_scc_8852c[] = { + {13, 1614, grp_0}, /* ACH 0 */ + {13, 1614, grp_0}, /* ACH 1 */ + {13, 1614, grp_0}, /* ACH 2 */ + {13, 1614, grp_0}, /* ACH 3 */ + {13, 1614, grp_1}, /* ACH 4 */ + {13, 1614, grp_1}, /* ACH 5 */ + {13, 1614, grp_1}, /* ACH 6 */ + {13, 1614, grp_1}, /* ACH 7 */ + {13, 1614, grp_0}, /* B0MGQ */ + {13, 1614, grp_0}, /* B0HIQ */ + {13, 1614, grp_1}, /* B1MGQ */ + {13, 1614, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_dbcc_8852c[] = { + {12, 1609, grp_0}, /* ACH 0 */ + {12, 1609, grp_0}, /* ACH 1 */ + {12, 1609, grp_0}, /* ACH 2 */ + {12, 1609, grp_0}, /* ACH 3 */ + {12, 1609, grp_1}, /* ACH 4 */ + {12, 1609, grp_1}, /* ACH 5 */ + {12, 1609, grp_1}, /* ACH 6 */ + {12, 1609, grp_1}, /* ACH 7 */ + {12, 1609, grp_0}, /* B0MGQ */ + {12, 1609, grp_0}, /* B0HIQ */ + {12, 1609, grp_1}, /* B1MGQ */ + {12, 1609, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_wd128_8852b[] = { + {256, 1792, grp_0}, /* ACH 0 */ + {256, 1792, grp_0}, /* ACH 1 */ + {256, 1792, grp_0}, /* ACH 2 */ + {256, 1792, grp_0}, /* ACH 3 */ + {0, 0, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {0, 0, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {256, 1792, grp_0}, /* B0MGQ */ + {256, 1792, grp_0}, /* B0HIQ */ + {0, 0, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_stf_8852a[] = { + {8, 256, grp_0}, /* ACH 0 */ + {8, 256, grp_0}, /* ACH 1 */ + {8, 256, grp_0}, /* ACH 2 */ + {8, 256, grp_0}, /* ACH 3 */ + {8, 256, grp_1}, /* ACH 4 */ + {8, 256, grp_1}, /* ACH 5 */ + {8, 256, grp_1}, /* ACH 6 */ + {8, 256, grp_1}, /* ACH 7 */ + {8, 256, grp_0}, /* B0MGQ */ + {8, 256, grp_0}, /* B0HIQ */ + {8, 256, grp_1}, /* B1MGQ */ + {8, 256, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_stf_8852b[] = { + {27, 204, grp_0}, /* ACH 0 */ + {27, 204, grp_0}, /* ACH 1 */ + {27, 204, grp_0}, /* ACH 2 */ + {27, 204, grp_0}, /* ACH 3 */ + {0, 0, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {0, 0, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {11, 204, grp_0}, /* B0MGQ */ + {11, 204, grp_0}, /* B0HIQ */ + {0, 0, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_scc_stf_8852c[] = { + {2, 108, grp_0}, /* ACH 0 */ + {2, 108, grp_0}, /* ACH 1 */ + {2, 108, grp_0}, /* ACH 2 */ + {2, 108, grp_0}, /* ACH 3 */ + {2, 108, grp_1}, /* ACH 4 */ + {2, 108, grp_1}, /* ACH 5 */ + {2, 108, grp_1}, /* ACH 6 */ + {2, 108, grp_1}, /* ACH 7 */ + {2, 108, grp_0}, /* B0MGQ */ + {2, 108, grp_0}, /* B0HIQ */ + {2, 108, grp_1}, /* B1MGQ */ + {2, 108, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_dbcc_stf_8852c[] = { + {2, 76, grp_0}, /* ACH 0 */ + {2, 76, grp_0}, /* ACH 1 */ + {2, 76, grp_0}, /* ACH 2 */ + {2, 76, grp_0}, /* ACH 3 */ + {2, 76, grp_1}, /* ACH 4 */ + {2, 76, grp_1}, /* ACH 5 */ + {2, 76, grp_1}, /* ACH 6 */ + {2, 76, grp_1}, /* ACH 7 */ + {2, 76, grp_0}, /* B0MGQ */ + {2, 76, grp_0}, /* B0HIQ */ + {2, 76, grp_1}, /* B1MGQ */ + {2, 76, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_sutp_8852a[] = { + {128, 256, grp_0}, /* ACH 0 */ + {0, 0, grp_1}, /* ACH 1 */ + {0, 0, grp_1}, /* ACH 2 */ + {0, 0, grp_1}, /* ACH 3 */ + {0, 0, grp_1}, /* ACH 4 */ + {0, 0, grp_1}, /* ACH 5 */ + {0, 0, grp_1}, /* ACH 6 */ + {0, 0, grp_1}, /* ACH 7 */ + {0, 0, grp_1}, /* B0MGQ */ + {0, 0, grp_1}, /* B0HIQ */ + {0, 0, grp_1}, /* B1MGQ */ + {0, 0, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_bcn_test_8852a[] = { + {128, 1833, grp_0}, /* ACH 0 */ + {128, 1833, grp_0}, /* ACH 1 */ + {128, 1833, grp_0}, /* ACH 2 */ + {128, 1833, grp_0}, /* ACH 3 */ + {128, 1833, grp_1}, /* ACH 4 */ + {128, 1833, grp_1}, /* ACH 5 */ + {128, 1833, grp_1}, /* ACH 6 */ + {128, 1833, grp_1}, /* ACH 7 */ + {32, 1833, grp_0}, /* B0MGQ */ + {128, 1833, grp_0}, /* B0HIQ */ + {32, 1833, grp_1}, /* B1MGQ */ + {128, 1833, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852a[] = { + {64, 586, grp_0}, /* ACH 0 */ + {64, 586, grp_0}, /* ACH 1 */ + {64, 586, grp_0}, /* ACH 2 */ + {64, 586, grp_0}, /* ACH 3 */ + {64, 586, grp_1}, /* ACH 4 */ + {64, 586, grp_1}, /* ACH 5 */ + {64, 586, grp_1}, /* ACH 6 */ + {64, 586, grp_1}, /* ACH 7 */ + {32, 586, grp_0}, /* B0MGQ */ + {64, 586, grp_0}, /* B0HIQ */ + {32, 586, grp_1}, /* B1MGQ */ + {64, 586, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852b[] = { + {10, 200, grp_0}, /* ACH 0 */ + {10, 200, grp_0}, /* ACH 1 */ + {10, 200, grp_0}, /* ACH 2 */ + {10, 200, grp_0}, /* ACH 3 */ + {0, 0, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {0, 0, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {4, 200, grp_0}, /* B0MGQ */ + {4, 200, grp_0}, /* B0HIQ */ + {0, 0, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852c[] = { + {4, 1560, grp_0}, /* ACH 0 */ + {4, 1560, grp_0}, /* ACH 1 */ + {4, 1560, grp_0}, /* ACH 2 */ + {4, 1560, grp_0}, /* ACH 3 */ + {4, 1560, grp_1}, /* ACH 4 */ + {4, 1560, grp_1}, /* ACH 5 */ + {4, 1560, grp_1}, /* ACH 6 */ + {4, 1560, grp_1}, /* ACH 7 */ + {4, 1560, grp_0}, /* B0MGQ */ + {4, 1560, grp_0}, /* B0HIQ */ + {4, 1560, grp_1}, /* B1MGQ */ + {4, 1560, grp_1}, /* B1HIQ */ + {40, 0, 0} /* FWCMDQ */ +}; + +#ifdef PHL_FEATURE_AP +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852a = { + 3792, /* Group 0 */ + 0, /* Group 1 */ + 3792, /* Public Max */ + 0 /* WP threshold */ +}; +#else //for nic mode use +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852a = { + 3792, /* Group 0 */ + 0, /* Group 1 */ + 3792, /* Public Max */ + 0 /* WP threshold */ +}; +#endif + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852b = { + 960, /* Group 0 */ + 0, /* Group 1 */ + 960, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_scc_8852c = { + 1614, /* Group 0 */ + 1614, /* Group 1 */ + 3228, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_dbcc_8852c = { + 1609, /* Group 0 */ + 1609, /* Group 1 */ + 3218, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_wd128_8852b = { + 1792, /* Group 0 */ + 0, /* Group 1 */ + 1792, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_stf_8852a = { + 256, /* Group 0 */ + 256, /* Group 1 */ + 512, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_stf_8852b = { + 204, /* Group 0 */ + 0, /* Group 1 */ + 204, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_scc_stf_8852c = { + 108, /* Group 0 */ + 108, /* Group 1 */ + 216, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_dbcc_stf_8852c = { + 76, /* Group 0 */ + 76, /* Group 1 */ + 152, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_sutp_8852a = { + 256, /* Group 0 */ + 0, /* Group 1 */ + 256, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_bcn_test_8852a = { + 1833, /* Group 0 */ + 1833, /* Group 1 */ + 3666, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852a = { + 586, /* Group 0 */ + 586, /* Group 1 */ + 1172, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852b = { + 200, /* Group 0 */ + 0, /* Group 1 */ + 200, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852c = { + 1560, /* Group 0 */ + 1560, /* Group 1 */ + 3120, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie = { + 2, /*CH 0-11 pre-cost */ + 40, /*H2C pre-cost */ + 0, /* WP CH 0-7 pre-cost */ + 0, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_wd128 = { + 2, /*CH 0-11 pre-cost */ + 40, /*H2C pre-cost */ + 0, /* WP CH 0-7 pre-cost */ + 0, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_stf = { + 1, /*CH 0-11 pre-cost */ + 40, /*H2C pre-cost */ + 64, /* WP CH 0-7 pre-cost */ + 64, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_stf_8852c = { + 1, /*CH 0-11 pre-cost */ + 40, /*H2C pre-cost */ + 48, /* WP CH 0-7 pre-cost */ + 48, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_dlfw_8852c = { + 0, /*CH 0-11 pre-cost */ + 256, /*H2C pre-cost */ + 0, /* WP CH 0-7 pre-cost */ + 0, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_la_8852c = { + 2, /*CH 0-11 pre-cost */ + 20, /*H2C pre-cost */ + 0, /* WP CH 0-7 pre-cost */ + 0, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; +#endif + +#if MAC_AX_USB_SUPPORT +static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_dbcc[] = { + {22, 212, grp_0}, /* ACH 0 */ + {0, 0, grp_0}, /* ACH 1 */ + {22, 212, grp_0}, /* ACH 2 */ + {0, 0, grp_0}, /* ACH 3 */ + {22, 212, grp_1}, /* ACH 4 */ + {0, 0, grp_1}, /* ACH 5 */ + {22, 212, grp_1}, /* ACH 6 */ + {0, 0, grp_1}, /* ACH 7 */ + {22, 212, grp_0}, /* B0MGQ */ + {0, 0, grp_0}, /* B0HIQ */ + {22, 212, grp_1}, /* B1MGQ */ + {0, 0, grp_1}, /* B1HIQ */ + {0, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_dbcc = { + 256, /* Group 0 */ + 256, /* Group 1 */ + 512, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_scc_8852a[] = { + {22, 402, grp_0}, /* ACH 0 */ + {0, 0, grp_0}, /* ACH 1 */ + {22, 402, grp_0}, /* ACH 2 */ + {0, 0, grp_0}, /* ACH 3 */ + {22, 402, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {22, 402, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {22, 402, grp_0}, /* B0MGQ */ + {0, 0, grp_0}, /* B0HIQ */ + {22, 402, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {0, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_scc_8852b[] = { + {18, 204, grp_0}, /* ACH 0 */ + {18, 204, grp_0}, /* ACH 1 */ + {18, 204, grp_0}, /* ACH 2 */ + {18, 204, grp_0}, /* ACH 3 */ + {0, 0, grp_0}, /* ACH 4 */ + {0, 0, grp_0}, /* ACH 5 */ + {0, 0, grp_0}, /* ACH 6 */ + {0, 0, grp_0}, /* ACH 7 */ + {18, 204, grp_0}, /* B0MGQ */ + {18, 204, grp_0}, /* B0HIQ */ + {0, 0, grp_0}, /* B1MGQ */ + {0, 0, grp_0}, /* B1HIQ */ + {0, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_scc_8852a = { + 512, /* Group 0 */ + 0, /* Group 1 */ + 512, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_scc_8852b = { + 204, /* Group 0 */ + 0, /* Group 1 */ + 204, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_usb_8852a = { + 11, /*CH 0-11 pre-cost */ + 32, /*H2C pre-cost */ + 76, /* WP CH 0-7 pre-cost */ + 25, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_usb_8852b = { + 9, /*CH 0-11 pre-cost */ + 32, /*H2C pre-cost */ + 76, /* WP CH 0-7 pre-cost */ + 24, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_la_8852a[] = { + {22, 84, grp_0}, /* ACH 0 */ + {0, 0, grp_0}, /* ACH 1 */ + {22, 84, grp_0}, /* ACH 2 */ + {0, 0, grp_0}, /* ACH 3 */ + {22, 84, grp_1}, /* ACH 4 */ + {0, 0, grp_1}, /* ACH 5 */ + {22, 84, grp_1}, /* ACH 6 */ + {0, 0, grp_1}, /* ACH 7 */ + {22, 84, grp_0}, /* B0MGQ */ + {0, 0, grp_0}, /* B0HIQ */ + {22, 84, grp_1}, /* B1MGQ */ + {0, 0, grp_1}, /* B1HIQ */ + {0, 0, 0} /* FWCMDQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_la_8852a = { + 128, /* Group 0 */ + 128, /* Group 1 */ + 256, /* Public Max */ + 104 /* WP threshold */ +}; +#endif + +#if MAC_AX_SDIO_SUPPORT +static struct mac_ax_hfc_ch_cfg hfc_chcfg_sdio_8852a[] = { + {2, 490, grp_0}, /* ACH 0 */ + {2, 490, grp_0}, /* ACH 1 */ + {2, 490, grp_0}, /* ACH 2 */ + {2, 490, grp_0}, /* ACH 3 */ + {2, 490, grp_0}, /* ACH 4 */ + {2, 490, grp_0}, /* ACH 5 */ + {2, 490, grp_0}, /* ACH 6 */ + {2, 490, grp_0}, /* ACH 7 */ + {2, 490, grp_0}, /* B0MGQ */ + {2, 490, grp_0}, /* B0HIQ */ + {2, 490, grp_0}, /* B1MGQ */ + {2, 490, grp_0}, /* B1HIQ */ + {40, 0, 0} /* H2CQ */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_sdio_8852b[] = { + {2, 102, grp_0}, /* ACH 0 */ + {2, 102, grp_0}, /* ACH 1 */ + {2, 102, grp_0}, /* ACH 2 */ + {2, 102, grp_0}, /* ACH 3 */ + {0, 0, grp_1}, /* ACH 4 */ + {0, 0, grp_1}, /* ACH 5 */ + {0, 0, grp_1}, /* ACH 6 */ + {0, 0, grp_1}, /* ACH 7 */ + {2, 102, grp_0}, /* B0MGQ */ + {2, 102, grp_0}, /* B0HIQ */ + {0, 0, grp_1}, /* B1MGQ */ + {0, 0, grp_1}, /* B1HIQ */ + {40, 0, 0} /* H2CQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_sdio_8852a = { + 512, /* Group 0 */ + 0, /* Group 1 */ + 512, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_sdio_8852b = { + 112, /* Group 0 */ + 0, /* Group 1 */ + 112, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_dbcc_sdio_8852a[] = { + {2, 246, grp_0}, /* ACH 0 */ + {2, 246, grp_0}, /* ACH 1 */ + {2, 246, grp_0}, /* ACH 2 */ + {2, 246, grp_0}, /* ACH 3 */ + {2, 246, grp_1}, /* ACH 4 */ + {2, 246, grp_1}, /* ACH 5 */ + {2, 246, grp_1}, /* ACH 6 */ + {2, 246, grp_1}, /* ACH 7 */ + {2, 246, grp_0}, /* B0MGQ */ + {2, 246, grp_0}, /* B0HIQ */ + {2, 246, grp_1}, /* B1MGQ */ + {2, 246, grp_1}, /* B1HIQ */ + {40, 0, 0} /* H2CQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_dbcc_sdio_8852a = { + 256, /* Group 0 */ + 256, /* Group 1 */ + 512, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_la_sdio_8852a[] = { + {2, 54, grp_0}, /* ACH 0 */ + {2, 54, grp_0}, /* ACH 1 */ + {2, 54, grp_0}, /* ACH 2 */ + {2, 54, grp_0}, /* ACH 3 */ + {2, 54, grp_1}, /* ACH 4 */ + {2, 54, grp_1}, /* ACH 5 */ + {2, 54, grp_1}, /* ACH 6 */ + {2, 54, grp_1}, /* ACH 7 */ + {2, 54, grp_0}, /* B0MGQ */ + {2, 54, grp_0}, /* B0HIQ */ + {2, 54, grp_1}, /* B1MGQ */ + {2, 54, grp_1}, /* B1HIQ */ + {40, 0, 0} /* H2CQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_la_sdio_8852a = { + 64, /* Group 0 */ + 64, /* Group 1 */ + 128, /* Public Max */ + 104 /* WP threshold */ +}; + +static struct mac_ax_hfc_ch_cfg hfc_chcfg_la_sdio_8852b[] = { + {2, 102, grp_0}, /* ACH 0 */ + {2, 102, grp_0}, /* ACH 1 */ + {2, 102, grp_0}, /* ACH 2 */ + {2, 102, grp_0}, /* ACH 3 */ + {0, 0, grp_1}, /* ACH 4 */ + {0, 0, grp_1}, /* ACH 5 */ + {0, 0, grp_1}, /* ACH 6 */ + {0, 0, grp_1}, /* ACH 7 */ + {2, 102, grp_0}, /* B0MGQ */ + {2, 102, grp_0}, /* B0HIQ */ + {0, 0, grp_1}, /* B1MGQ */ + {0, 0, grp_1}, /* B1HIQ */ + {40, 0, 0} /* H2CQ */ +}; + +static struct mac_ax_hfc_pub_cfg hfc_pubcfg_la_sdio_8852b = { + 112, /* Group 0 */ + 0, /* Group 1 */ + 112, /* Public Max */ + 0 /* WP threshold */ +}; + +static struct mac_ax_hfc_prec_cfg hfc_preccfg_sdio = { + 1, /*CH 0-11 pre-cost */ + 40, /*H2C pre-cost */ + 0, /* WP CH 0-7 pre-cost */ + 0, /* WP CH 8-11 pre-cost */ + MAC_AX_HFC_FULL_COND_X1, /* CH 0-11 full condition */ + MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */ + MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */ + MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */ +}; +#endif + +u32 hfc_reset_param(struct mac_ax_adapter *adapter) +{ + struct mac_ax_hfc_param *param; + struct mac_ax_hfc_ch_cfg *ch_cfg, *ch_cfg_ini; + struct mac_ax_hfc_ch_info *ch_info; + struct mac_ax_hfc_pub_cfg *pub_cfg, *pub_cfg_ini; + struct mac_ax_hfc_pub_info *pub_info; + struct mac_ax_hfc_prec_cfg *prec_cfg, *prec_cfg_ini; + u8 ch; + + param = adapter->hfc_param; + ch_cfg = param->ch_cfg; + ch_info = param->ch_info; + pub_cfg = param->pub_cfg; + pub_info = param->pub_info; + prec_cfg = param->prec_cfg; + + switch (adapter->hw_info->intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + param->en = 0; + param->mode = MAC_AX_HCIFC_SDIO; + prec_cfg_ini = &hfc_preccfg_sdio; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_sdio_8852a; + pub_cfg_ini = &hfc_pubcfg_sdio_8852a; + break; + case MAC_AX_QTA_DBCC: + ch_cfg_ini = hfc_chcfg_dbcc_sdio_8852a; + pub_cfg_ini = &hfc_pubcfg_dbcc_sdio_8852a; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + break; + case MAC_AX_QTA_LAMODE: + ch_cfg_ini = hfc_chcfg_la_sdio_8852a; + pub_cfg_ini = &hfc_pubcfg_la_sdio_8852a; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_sdio_8852b; + pub_cfg_ini = &hfc_pubcfg_sdio_8852b; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + break; + case MAC_AX_QTA_LAMODE: + ch_cfg_ini = hfc_chcfg_la_sdio_8852b; + pub_cfg_ini = &hfc_pubcfg_la_sdio_8852b; + break; + default: + return MACHFCCH011QTA; + } + } else { + return MACCHIPID; + } + break; +#endif +#if MAC_AX_USB_SUPPORT + case MAC_AX_INTF_USB: + param->en = 0; + param->mode = MAC_AX_HCIFC_STF; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_usb_scc_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DBCC: + ch_cfg_ini = hfc_chcfg_usb_dbcc; + pub_cfg_ini = &hfc_pubcfg_usb_dbcc; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_LAMODE: + ch_cfg_ini = hfc_chcfg_usb_la_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_la_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_usb_scc_8852b; + pub_cfg_ini = &hfc_pubcfg_usb_scc_8852b; + prec_cfg_ini = &hfc_preccfg_usb_8852b; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_usb_8852b; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_usb_scc_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DBCC: + ch_cfg_ini = hfc_chcfg_usb_dbcc; + pub_cfg_ini = &hfc_pubcfg_usb_dbcc; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_LAMODE: + ch_cfg_ini = hfc_chcfg_usb_la_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_la_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + ch_cfg_ini = hfc_chcfg_usb_scc_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DBCC: + ch_cfg_ini = hfc_chcfg_usb_dbcc; + pub_cfg_ini = &hfc_pubcfg_usb_dbcc; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_DLFW: + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + case MAC_AX_QTA_LAMODE: + ch_cfg_ini = hfc_chcfg_usb_la_8852a; + pub_cfg_ini = &hfc_pubcfg_usb_la_8852a; + prec_cfg_ini = &hfc_preccfg_usb_8852a; + break; + default: + return MACHFCCH011QTA; + } + } else { + return MACCHIPID; + } + break; +#endif +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_INTF_PCIE: + param->en = 0; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_DBCC: + case MAC_AX_QTA_SCC: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_8852a; + pub_cfg_ini = &hfc_pubcfg_pcie_8852a; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_DBCC_STF: + case MAC_AX_QTA_SCC_STF: + param->mode = MAC_AX_HCIFC_STF; + ch_cfg_ini = hfc_chcfg_pcie_stf_8852a; + pub_cfg_ini = &hfc_pubcfg_pcie_stf_8852a; + prec_cfg_ini = &hfc_preccfg_pcie_stf; + break; + case MAC_AX_QTA_SU_TP: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_sutp_8852a; + pub_cfg_ini = &hfc_pubcfg_pcie_sutp_8852a; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_DLFW: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_LAMODE: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_la_8852a; + pub_cfg_ini = &hfc_pubcfg_pcie_la_8852a; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_SCC: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_8852b; + pub_cfg_ini = &hfc_pubcfg_pcie_8852b; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_SCC_STF: + param->mode = MAC_AX_HCIFC_STF; + ch_cfg_ini = hfc_chcfg_pcie_stf_8852b; + pub_cfg_ini = &hfc_pubcfg_pcie_stf_8852b; + prec_cfg_ini = &hfc_preccfg_pcie_stf; + break; + case MAC_AX_QTA_DLFW: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_LAMODE: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_la_8852b; + pub_cfg_ini = &hfc_pubcfg_pcie_la_8852b; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + default: + return MACHFCCH011QTA; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + switch (adapter->dle_info.qta_mode) { + case MAC_AX_QTA_DBCC: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_dbcc_8852c; + pub_cfg_ini = &hfc_pubcfg_pcie_dbcc_8852c; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_SCC: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_scc_8852c; + pub_cfg_ini = &hfc_pubcfg_pcie_scc_8852c; + prec_cfg_ini = &hfc_preccfg_pcie; + break; + case MAC_AX_QTA_SCC_STF: + param->mode = MAC_AX_HCIFC_STF; + ch_cfg_ini = hfc_chcfg_pcie_scc_stf_8852c; + pub_cfg_ini = &hfc_pubcfg_pcie_scc_stf_8852c; + prec_cfg_ini = &hfc_preccfg_pcie_stf_8852c; + break; + case MAC_AX_QTA_DBCC_STF: + param->mode = MAC_AX_HCIFC_STF; + ch_cfg_ini = hfc_chcfg_pcie_dbcc_stf_8852c; + pub_cfg_ini = &hfc_pubcfg_pcie_dbcc_stf_8852c; + prec_cfg_ini = &hfc_preccfg_pcie_stf_8852c; + break; + case MAC_AX_QTA_DLFW: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = NULL; + pub_cfg_ini = NULL; + prec_cfg_ini = &hfc_preccfg_pcie_dlfw_8852c; + break; + case MAC_AX_QTA_LAMODE: + param->mode = MAC_AX_HCIFC_POH; + ch_cfg_ini = hfc_chcfg_pcie_la_8852c; + pub_cfg_ini = &hfc_pubcfg_pcie_la_8852c; + prec_cfg_ini = &hfc_preccfg_pcie_la_8852c; + break; + default: + return MACHFCCH011QTA; + } + } else { + return MACCHIPID; + } + break; +#endif + default: + return MACINTF; + } + + if (pub_cfg_ini) { + pub_cfg->group0 = pub_cfg_ini->group0; + pub_cfg->group1 = pub_cfg_ini->group1; + pub_cfg->pub_max = pub_cfg_ini->pub_max; + pub_cfg->wp_thrd = pub_cfg_ini->wp_thrd; + } + + pub_info->g0_used = 0; + pub_info->g1_used = 0; + pub_info->pub_aval = 0; + pub_info->wp_aval = 0; + + if (pub_cfg_ini) { + prec_cfg->ch011_prec = prec_cfg_ini->ch011_prec; + prec_cfg->h2c_prec = prec_cfg_ini->h2c_prec; + prec_cfg->wp_ch07_prec = prec_cfg_ini->wp_ch07_prec; + prec_cfg->wp_ch811_prec = prec_cfg_ini->wp_ch811_prec; + prec_cfg->ch011_full_cond = prec_cfg_ini->ch011_full_cond; + prec_cfg->h2c_full_cond = prec_cfg_ini->h2c_full_cond; + prec_cfg->wp_ch07_full_cond = prec_cfg_ini->wp_ch07_full_cond; + prec_cfg->wp_ch811_full_cond = prec_cfg_ini->wp_ch811_full_cond; + + adapter->hw_info->sw_amsdu_max_size = prec_cfg->wp_ch07_prec * + HFC_PAGE_UNIT; + } + + if (ch_cfg_ini) { + for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_CH_NUM; ch++) { + ch_cfg[ch].min = ch_cfg_ini[ch].min; + ch_cfg[ch].max = ch_cfg_ini[ch].max; + ch_cfg[ch].grp = ch_cfg_ini[ch].grp; + ch_info[ch].aval = 0; + ch_info[ch].used = 0; + } + } + return MACSUCCESS; +} + +static inline u32 hfc_ch_cfg_chk(struct mac_ax_adapter *adapter, u8 ch) +{ + struct mac_ax_hfc_ch_cfg *ch_cfg = adapter->hfc_param->ch_cfg; + struct mac_ax_hfc_pub_cfg *pub_cfg = adapter->hfc_param->pub_cfg; + struct mac_ax_hfc_prec_cfg *prec_cfg = adapter->hfc_param->prec_cfg; + + if (ch >= MAC_AX_DMA_CH_NUM) + return MACINTF; + + if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || + ch_cfg[ch].max > pub_cfg->pub_max) + return MACHFCCH011QTA; + if (ch_cfg[ch].grp >= grp_num) + return MACHFCCH011GRP; + + return MACSUCCESS; +} + +static inline u32 hfc_pub_info_chk(struct mac_ax_adapter *adapter) +{ + struct mac_ax_hfc_pub_cfg *cfg = adapter->hfc_param->pub_cfg; + struct mac_ax_hfc_pub_info *info = adapter->hfc_param->pub_info; + + if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + return MACSUCCESS; + else + return MACHFCPUBINFO; + } + + return MACSUCCESS; +} + +static inline u32 hfc_pub_cfg_chk(struct mac_ax_adapter *adapter) +{ + struct mac_ax_hfc_param *param = adapter->hfc_param; + struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg; + + if (pub_cfg->group0 + pub_cfg->group1 > pub_cfg->pub_max) + return MACHFCPUBQTA; + + return MACSUCCESS; +} + +u32 hfc_ch_ctrl(struct mac_ax_adapter *adapter, u8 ch) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_ch_cfg *cfg = adapter->hfc_param->ch_cfg; + u32 val32 = 0; + u32 ret = 0; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret) + return ret; + + ret = hfc_ch_cfg_chk(adapter, ch); + if (ret) + return ret; + + switch (ch) { + case MAC_AX_DMA_ACH0: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH0].min, B_AX_ACH0_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH0].max, B_AX_ACH0_MAX_PG) | + (cfg[MAC_AX_DMA_ACH0].grp ? B_AX_ACH0_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH0_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH0_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH1: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH1].min, B_AX_ACH1_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH1].max, B_AX_ACH1_MAX_PG) | + (cfg[MAC_AX_DMA_ACH1].grp ? B_AX_ACH1_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH1_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH1_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH2: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH2].min, B_AX_ACH2_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH2].max, B_AX_ACH2_MAX_PG) | + (cfg[MAC_AX_DMA_ACH2].grp ? B_AX_ACH2_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH2_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH2_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH3: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH3].min, B_AX_ACH3_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH3].max, B_AX_ACH3_MAX_PG) | + (cfg[MAC_AX_DMA_ACH3].grp ? B_AX_ACH3_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH3_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH3_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH4: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH4].min, B_AX_ACH4_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH4].max, B_AX_ACH4_MAX_PG) | + (cfg[MAC_AX_DMA_ACH4].grp ? B_AX_ACH4_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH4_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH4_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH5: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH5].min, B_AX_ACH5_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH5].max, B_AX_ACH5_MAX_PG) | + (cfg[MAC_AX_DMA_ACH5].grp ? B_AX_ACH5_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH5_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH5_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH6: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH6].min, B_AX_ACH6_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH6].max, B_AX_ACH6_MAX_PG) | + (cfg[MAC_AX_DMA_ACH6].grp ? B_AX_ACH6_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH6_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH6_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_ACH7: + val32 = SET_WORD(cfg[MAC_AX_DMA_ACH7].min, B_AX_ACH7_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_ACH7].max, B_AX_ACH7_MAX_PG) | + (cfg[MAC_AX_DMA_ACH7].grp ? B_AX_ACH7_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_ACH7_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_ACH7_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_B0MG: + val32 = SET_WORD(cfg[MAC_AX_DMA_B0MG].min, B_AX_CH8_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_B0MG].max, B_AX_CH8_MAX_PG) | + (cfg[MAC_AX_DMA_B0MG].grp ? B_AX_CH8_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_CH8_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_CH8_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_B0HI: + val32 = SET_WORD(cfg[MAC_AX_DMA_B0HI].min, B_AX_CH9_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_B0HI].max, B_AX_CH9_MAX_PG) | + (cfg[MAC_AX_DMA_B0HI].grp ? B_AX_CH9_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_CH9_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_CH9_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_B1MG: + val32 = SET_WORD(cfg[MAC_AX_DMA_B1MG].min, B_AX_CH10_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_B1MG].max, B_AX_CH10_MAX_PG) | + (cfg[MAC_AX_DMA_B1MG].grp ? B_AX_CH10_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_CH10_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_CH10_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_B1HI: + val32 = SET_WORD(cfg[MAC_AX_DMA_B1HI].min, B_AX_CH11_MIN_PG) | + SET_WORD(cfg[MAC_AX_DMA_B1HI].max, B_AX_CH11_MAX_PG) | + (cfg[MAC_AX_DMA_B1HI].grp ? B_AX_CH11_GRP : 0); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_CH11_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_CH11_PAGE_CTRL, val32); + break; + + case MAC_AX_DMA_H2C: + break; + + default: + return MACTXCHDMA; + } + + return MACSUCCESS; +} + +u32 hfc_upd_ch_info(struct mac_ax_adapter *adapter, u8 ch) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_ch_info *info = adapter->hfc_param->ch_info; + struct mac_ax_hfc_ch_cfg *cfg = adapter->hfc_param->ch_cfg; + u32 val32; + u32 ret; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret) + return ret; + + switch (ch) { + case MAC_AX_DMA_ACH0: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH0_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH0_PAGE_INFO); + info[MAC_AX_DMA_ACH0].aval = + GET_FIELD(val32, B_AX_ACH0_AVAL_PG); + info[MAC_AX_DMA_ACH0].used = + GET_FIELD(val32, B_AX_ACH0_USE_PG); + break; + + case MAC_AX_DMA_ACH1: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH1_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH1_PAGE_INFO); + info[MAC_AX_DMA_ACH1].aval = + GET_FIELD(val32, B_AX_ACH1_AVAL_PG); + info[MAC_AX_DMA_ACH1].used = + GET_FIELD(val32, B_AX_ACH1_USE_PG); + break; + + case MAC_AX_DMA_ACH2: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH2_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH2_PAGE_INFO); + info[MAC_AX_DMA_ACH2].aval = + GET_FIELD(val32, B_AX_ACH2_AVAL_PG); + info[MAC_AX_DMA_ACH2].used = + GET_FIELD(val32, B_AX_ACH2_USE_PG); + break; + + case MAC_AX_DMA_ACH3: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH3_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH3_PAGE_INFO); + info[MAC_AX_DMA_ACH3].aval = + GET_FIELD(val32, B_AX_ACH3_AVAL_PG); + info[MAC_AX_DMA_ACH3].used = + GET_FIELD(val32, B_AX_ACH3_USE_PG); + break; + + case MAC_AX_DMA_ACH4: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH4_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH4_PAGE_INFO); + info[MAC_AX_DMA_ACH4].aval = + GET_FIELD(val32, B_AX_ACH4_AVAL_PG); + info[MAC_AX_DMA_ACH4].used = + GET_FIELD(val32, B_AX_ACH4_USE_PG); + break; + + case MAC_AX_DMA_ACH5: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH5_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH5_PAGE_INFO); + info[MAC_AX_DMA_ACH5].aval = + GET_FIELD(val32, B_AX_ACH5_AVAL_PG); + info[MAC_AX_DMA_ACH5].used = + GET_FIELD(val32, B_AX_ACH5_USE_PG); + break; + + case MAC_AX_DMA_ACH6: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH6_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH6_PAGE_INFO); + info[MAC_AX_DMA_ACH6].aval = + GET_FIELD(val32, B_AX_ACH6_AVAL_PG); + info[MAC_AX_DMA_ACH6].used = + GET_FIELD(val32, B_AX_ACH6_USE_PG); + break; + + case MAC_AX_DMA_ACH7: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_ACH7_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_ACH7_PAGE_INFO); + info[MAC_AX_DMA_ACH7].aval = + GET_FIELD(val32, B_AX_ACH7_AVAL_PG); + info[MAC_AX_DMA_ACH7].used = + GET_FIELD(val32, B_AX_ACH7_USE_PG); + break; + + case MAC_AX_DMA_B0MG: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_CH8_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_CH8_PAGE_INFO); + info[MAC_AX_DMA_B0MG].aval = + GET_FIELD(val32, B_AX_CH8_AVAL_PG); + info[MAC_AX_DMA_B0MG].used = + GET_FIELD(val32, B_AX_CH8_USE_PG); + break; + + case MAC_AX_DMA_B0HI: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_CH9_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_CH9_PAGE_INFO); + info[MAC_AX_DMA_B0HI].aval = + GET_FIELD(val32, B_AX_CH9_AVAL_PG); + info[MAC_AX_DMA_B0HI].used = + GET_FIELD(val32, B_AX_CH9_USE_PG); + break; + + case MAC_AX_DMA_B1MG: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_CH10_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_CH10_PAGE_INFO); + info[MAC_AX_DMA_B1MG].aval = + GET_FIELD(val32, B_AX_CH10_AVAL_PG); + info[MAC_AX_DMA_B1MG].used = + GET_FIELD(val32, B_AX_CH10_USE_PG); + break; + + case MAC_AX_DMA_B1HI: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_CH11_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_CH11_PAGE_INFO); + info[MAC_AX_DMA_B1HI].aval = + GET_FIELD(val32, B_AX_CH11_AVAL_PG); + info[MAC_AX_DMA_B1HI].used = + GET_FIELD(val32, B_AX_CH11_USE_PG); + break; + + case MAC_AX_DMA_H2C: + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + val32 = MAC_REG_R32(R_AX_CH12_PAGE_INFO_V1); + else + val32 = MAC_REG_R32(R_AX_CH12_PAGE_INFO); + info[MAC_AX_DMA_H2C].aval = + GET_FIELD(val32, B_AX_CH12_AVAL_PG); + info[MAC_AX_DMA_H2C].used = + cfg[MAC_AX_DMA_H2C].min - info[MAC_AX_DMA_H2C].aval; + break; + + default: + return MACTXCHDMA; + } + + return MACSUCCESS; +} + +u32 hfc_pub_ctrl(struct mac_ax_adapter *adapter) +{ + u32 val32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_pub_cfg *cfg = adapter->hfc_param->pub_cfg; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret) + return ret; + + ret = hfc_pub_cfg_chk(adapter); + if (ret) + return ret; + + val32 = SET_WORD(cfg->group0, B_AX_PUBPG_G0) | + SET_WORD(cfg->group1, B_AX_PUBPG_G1); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_PUB_PAGE_CTRL1_V1, val32); + else + MAC_REG_W32(R_AX_PUB_PAGE_CTRL1, val32); + + val32 = SET_WORD(cfg->wp_thrd, B_AX_WP_THRD); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_WP_PAGE_CTRL2_V1, val32); + else + MAC_REG_W32(R_AX_WP_PAGE_CTRL2, val32); + + return MACSUCCESS; +} + +u32 hfc_upd_mix_info(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_param *param = adapter->hfc_param; + struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg; + struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg; + struct mac_ax_hfc_pub_info *info = param->pub_info; + u32 val32, ret; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO1_V1); + info->g0_used = GET_FIELD(val32, B_AX_G0_USE_PG); + info->g1_used = GET_FIELD(val32, B_AX_G1_USE_PG); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO3_V1); + info->g0_aval = GET_FIELD(val32, B_AX_G0_AVAL_PG); + info->g1_aval = GET_FIELD(val32, B_AX_G1_AVAL_PG); + info->pub_aval = + GET_FIELD(MAC_REG_R32(R_AX_PUB_PAGE_INFO2_V1), B_AX_PUB_AVAL_PG); + info->wp_aval = + GET_FIELD(MAC_REG_R32(R_AX_WP_PAGE_INFO1_V1), B_AX_WP_AVAL_PG); + + val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL_V1); + param->en = val32 & B_AX_HCI_FC_EN ? 1 : 0; + param->h2c_en = val32 & B_AX_HCI_FC_CH12_EN ? 1 : 0; + param->mode = GET_FIELD(val32, B_AX_HCI_FC_MODE); + prec_cfg->ch011_full_cond = GET_FIELD(val32, B_AX_HCI_FC_WD_FULL_COND); + prec_cfg->h2c_full_cond = GET_FIELD(val32, B_AX_HCI_FC_CH12_FULL_COND); + prec_cfg->wp_ch07_full_cond = + GET_FIELD(val32, B_AX_HCI_FC_WP_CH07_FULL_COND); + prec_cfg->wp_ch811_full_cond = + GET_FIELD(val32, B_AX_HCI_FC_WP_CH811_FULL_COND); + + val32 = MAC_REG_R32(R_AX_CH_PAGE_CTRL_V1); + prec_cfg->ch011_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH011); + prec_cfg->h2c_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH12); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL2_V1); + pub_cfg->pub_max = GET_FIELD(val32, B_AX_PUBPG_ALL); + + val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL1_V1); + prec_cfg->wp_ch07_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH07); + prec_cfg->wp_ch811_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH811); + + val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL2_V1); + pub_cfg->wp_thrd = GET_FIELD(val32, B_AX_WP_THRD); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL1_V1); + pub_cfg->group0 = GET_FIELD(val32, B_AX_PUBPG_G0); + pub_cfg->group1 = GET_FIELD(val32, B_AX_PUBPG_G1); + + ret = hfc_pub_info_chk(adapter); + if (param->en && ret) + return ret; + } else { + val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO1); + info->g0_used = GET_FIELD(val32, B_AX_G0_USE_PG); + info->g1_used = GET_FIELD(val32, B_AX_G1_USE_PG); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO3); + info->g0_aval = GET_FIELD(val32, B_AX_G0_AVAL_PG); + info->g1_aval = GET_FIELD(val32, B_AX_G1_AVAL_PG); + info->pub_aval = + GET_FIELD(MAC_REG_R32(R_AX_PUB_PAGE_INFO2), B_AX_PUB_AVAL_PG); + info->wp_aval = + GET_FIELD(MAC_REG_R32(R_AX_WP_PAGE_INFO1), B_AX_WP_AVAL_PG); + + val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL); + param->en = val32 & B_AX_HCI_FC_EN ? 1 : 0; + param->h2c_en = val32 & B_AX_HCI_FC_CH12_EN ? 1 : 0; + param->mode = GET_FIELD(val32, B_AX_HCI_FC_MODE); + prec_cfg->ch011_full_cond = GET_FIELD(val32, B_AX_HCI_FC_WD_FULL_COND); + prec_cfg->h2c_full_cond = GET_FIELD(val32, B_AX_HCI_FC_CH12_FULL_COND); + prec_cfg->wp_ch07_full_cond = + GET_FIELD(val32, B_AX_HCI_FC_WP_CH07_FULL_COND); + prec_cfg->wp_ch811_full_cond = + GET_FIELD(val32, B_AX_HCI_FC_WP_CH811_FULL_COND); + + val32 = MAC_REG_R32(R_AX_CH_PAGE_CTRL); + prec_cfg->ch011_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH011); + prec_cfg->h2c_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH12); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL2); + pub_cfg->pub_max = GET_FIELD(val32, B_AX_PUBPG_ALL); + + val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL1); + prec_cfg->wp_ch07_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH07); + prec_cfg->wp_ch811_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH811); + + val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL2); + pub_cfg->wp_thrd = GET_FIELD(val32, B_AX_WP_THRD); + + val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL1); + pub_cfg->group0 = GET_FIELD(val32, B_AX_PUBPG_G0); + pub_cfg->group1 = GET_FIELD(val32, B_AX_PUBPG_G1); + + ret = hfc_pub_info_chk(adapter); + if (param->en && ret) + return ret; + } + return MACSUCCESS; +} + +static void hfc_h2c_cfg(struct mac_ax_adapter *adapter) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_param *param = adapter->hfc_param; + //struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg; + struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg; + + val32 = SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W32(R_AX_CH_PAGE_CTRL_V1, val32); + else + MAC_REG_W32(R_AX_CH_PAGE_CTRL, val32); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL_V1), + prec_cfg->h2c_full_cond, + B_AX_HCI_FC_CH12_FULL_COND); + MAC_REG_W32((R_AX_HCI_FC_CTRL_V1), val32); + } else { + val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL), + prec_cfg->h2c_full_cond, + B_AX_HCI_FC_CH12_FULL_COND); + MAC_REG_W32(R_AX_HCI_FC_CTRL, val32); + } +} + +static void hfc_mix_cfg(struct mac_ax_adapter *adapter) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_param *param = adapter->hfc_param; + struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg; + struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = SET_WORD(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011) | + SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12); + MAC_REG_W32(R_AX_CH_PAGE_CTRL_V1, val32); + + val32 = SET_WORD(pub_cfg->pub_max, B_AX_PUBPG_ALL); + MAC_REG_W32(R_AX_PUB_PAGE_CTRL2_V1, val32); + + val32 = SET_WORD(prec_cfg->wp_ch07_prec, B_AX_PREC_PAGE_WP_CH07) | + SET_WORD(prec_cfg->wp_ch811_prec, B_AX_PREC_PAGE_WP_CH811); + MAC_REG_W32(R_AX_WP_PAGE_CTRL1_V1, val32); + + val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL_V1), + param->mode, B_AX_HCI_FC_MODE); + val32 = SET_CLR_WORD(val32, prec_cfg->ch011_full_cond, + B_AX_HCI_FC_WD_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->h2c_full_cond, + B_AX_HCI_FC_CH12_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch07_full_cond, + B_AX_HCI_FC_WP_CH07_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch811_full_cond, + B_AX_HCI_FC_WP_CH811_FULL_COND); + MAC_REG_W32(R_AX_HCI_FC_CTRL_V1, val32); + } else { + val32 = SET_WORD(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011) | + SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12); + MAC_REG_W32(R_AX_CH_PAGE_CTRL, val32); + + val32 = SET_WORD(pub_cfg->pub_max, B_AX_PUBPG_ALL); + MAC_REG_W32(R_AX_PUB_PAGE_CTRL2, val32); + + val32 = SET_WORD(prec_cfg->wp_ch07_prec, B_AX_PREC_PAGE_WP_CH07) | + SET_WORD(prec_cfg->wp_ch811_prec, B_AX_PREC_PAGE_WP_CH811); + MAC_REG_W32(R_AX_WP_PAGE_CTRL1, val32); + + val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL), + param->mode, B_AX_HCI_FC_MODE); + val32 = SET_CLR_WORD(val32, prec_cfg->ch011_full_cond, + B_AX_HCI_FC_WD_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->h2c_full_cond, + B_AX_HCI_FC_CH12_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch07_full_cond, + B_AX_HCI_FC_WP_CH07_FULL_COND); + val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch811_full_cond, + B_AX_HCI_FC_WP_CH811_FULL_COND); + MAC_REG_W32(R_AX_HCI_FC_CTRL, val32); + } +} + +static void hfc_func_en(struct mac_ax_adapter *adapter, u8 en, u8 h2c_en) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hfc_param *param = adapter->hfc_param; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL_V1); + param->en = en ? 1 : 0; + param->h2c_en = h2c_en ? 1 : 0; + val32 = en ? (val32 | B_AX_HCI_FC_EN) : (val32 & ~B_AX_HCI_FC_EN); + val32 = h2c_en ? (val32 | B_AX_HCI_FC_CH12_EN) : + (val32 & ~B_AX_HCI_FC_CH12_EN); + MAC_REG_W32(R_AX_HCI_FC_CTRL_V1, val32); + } else { + val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL); + param->en = en ? 1 : 0; + param->h2c_en = h2c_en ? 1 : 0; + val32 = en ? (val32 | B_AX_HCI_FC_EN) : (val32 & ~B_AX_HCI_FC_EN); + val32 = h2c_en ? (val32 | B_AX_HCI_FC_CH12_EN) : + (val32 & ~B_AX_HCI_FC_CH12_EN); + MAC_REG_W32(R_AX_HCI_FC_CTRL, val32); + } +} + +u32 hfc_init(struct mac_ax_adapter *adapter, u8 rst, u8 en, u8 h2c_en) +{ + u8 ch; + u32 ret = 0; + + if (rst) + ret = hfc_reset_param(adapter); + if (ret) + return ret; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret) + return ret; + + hfc_func_en(adapter, 0, 0); + + if (!en && h2c_en) { + hfc_h2c_cfg(adapter); + hfc_func_en(adapter, en, h2c_en); + return ret; + } + + for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_H2C; ch++) { + ret = hfc_ch_ctrl(adapter, ch); + if (ret) + return ret; + } + + ret = hfc_pub_ctrl(adapter); + if (ret) + return ret; + + hfc_mix_cfg(adapter); + if (en || h2c_en) { + hfc_func_en(adapter, en, h2c_en); + PLTFM_DELAY_US(10); + } + for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_H2C; ch++) { + ret = hfc_upd_ch_info(adapter, ch); + if (ret) + return ret; + } + ret = hfc_upd_mix_info(adapter); + return ret; +} + +u32 hfc_info_init(struct mac_ax_adapter *adapter) +{ + adapter->hfc_param = + (struct mac_ax_hfc_param *) + PLTFM_MALLOC(sizeof(struct mac_ax_hfc_param)); + + adapter->hfc_param->ch_cfg = + (struct mac_ax_hfc_ch_cfg *)PLTFM_MALLOC(chcfg_size); + + adapter->hfc_param->ch_info = + (struct mac_ax_hfc_ch_info *)PLTFM_MALLOC(chinfo_size); + + adapter->hfc_param->pub_cfg = + (struct mac_ax_hfc_pub_cfg *) + PLTFM_MALLOC(sizeof(struct mac_ax_hfc_pub_cfg)); + + adapter->hfc_param->pub_info = + (struct mac_ax_hfc_pub_info *) + PLTFM_MALLOC(sizeof(struct mac_ax_hfc_pub_info)); + + adapter->hfc_param->prec_cfg = + (struct mac_ax_hfc_prec_cfg *) + PLTFM_MALLOC(sizeof(struct mac_ax_hfc_prec_cfg)); + + adapter->hfc_param->en = 0; + adapter->hfc_param->h2c_en = 0; + adapter->hfc_param->mode = 0; + + return MACSUCCESS; +} + +u32 hfc_info_exit(struct mac_ax_adapter *adapter) +{ + PLTFM_FREE(adapter->hfc_param->prec_cfg, + sizeof(struct mac_ax_hfc_prec_cfg)); + + PLTFM_FREE(adapter->hfc_param->pub_info, + sizeof(struct mac_ax_hfc_pub_info)); + + PLTFM_FREE(adapter->hfc_param->pub_cfg, + sizeof(struct mac_ax_hfc_pub_cfg)); + + PLTFM_FREE(adapter->hfc_param->ch_info, chinfo_size); + PLTFM_FREE(adapter->hfc_param->ch_cfg, chcfg_size); + PLTFM_FREE(adapter->hfc_param, sizeof(struct mac_ax_hfc_param)); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/hci_fc.h b/phl/hal_g6/mac/mac_ax/hci_fc.h new file mode 100644 index 0000000..bb6b59b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hci_fc.h @@ -0,0 +1,155 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_HCIFC_H_ +#define _MAC_AX_HCIFC_H_ + +#include "../type.h" +#include "trxcfg.h" +#include "../mac_ax.h" + +#define HFC_PAGE_UNIT 64 + +/** + * @enum mac_ax_hfc_full_cond + * + * @brief mac_ax_hfc_full_cond + * + * @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X1 + * Please Place Description here. + * @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X2 + * Please Place Description here. + * @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X3 + * Please Place Description here. + * @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X4 + * Please Place Description here. + */ +enum mac_ax_hfc_full_cond { + MAC_AX_HFC_FULL_COND_X1 = 0, + MAC_AX_HFC_FULL_COND_X2, + MAC_AX_HFC_FULL_COND_X3, + MAC_AX_HFC_FULL_COND_X4 +}; + +/** + * @addtogroup HCI + * @{ + * @addtogroup HCI_FlowControl + * @{ + */ +/** + * @brief hfc_ch_ctrl + * + * @param *adapter + * @param ch + * @return Please Place Description here. + * @retval u32 + */ +u32 hfc_ch_ctrl(struct mac_ax_adapter *adapter, u8 ch); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup HCI_FlowControl + * @{ + */ + +/** + * @brief hfc_upd_ch_info + * + * @param *adapter + * @param ch + * @return Please Place Description here. + * @retval u32 + */ +u32 hfc_upd_ch_info(struct mac_ax_adapter *adapter, u8 ch); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup HCI_FlowControl + * @{ + */ + +/** + * @brief hfc_pub_ctrl + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 hfc_pub_ctrl(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup HCI_FlowControl + * @{ + */ + +/** + * @brief hfc_upd_mix_info + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 hfc_upd_mix_info(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup HCI_FlowControl + * @{ + */ + +/** + * @brief hfc_init + * + * @param *adapter + * @param rst + * @param en + * @param h2c_en + * @return Please Place Description here. + * @retval u32 + */ +u32 hfc_init(struct mac_ax_adapter *adapter, u8 rst, u8 en, u8 h2c_en); +/** + * @} + * @} + */ + +u32 hfc_info_init(struct mac_ax_adapter *adapter); + +u32 hfc_info_exit(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/hdr_conv.c b/phl/hal_g6/mac/mac_ax/hdr_conv.c new file mode 100644 index 0000000..5ee5b80 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hdr_conv.c @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "hdr_conv.h" + +#if MAC_AX_FW_REG_OFLD +u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_en_hdr_conv *content; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_hdr_conv)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + content = (struct mac_ax_en_hdr_conv *)buf; + content->enable = en_hdr_conv; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_EN_MAC_HDR_CONV, + 0, + 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif +fail: + h2cb_free(adapter, h2cb); + + return ret; +} +#else +u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv) +{ + u32 val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (en_hdr_conv) { + val = MAC_REG_R32(R_AX_HDR_SHCUT_SETTING); + val |= (B_AX_MAC_MPDU_PROC_EN | + B_AX_SHCUT_LLC_WR_LOCK | + B_AX_SHCUT_PARSE_DASA); + MAC_REG_W32(R_AX_HDR_SHCUT_SETTING, val); + } else { + val = MAC_REG_R32(R_AX_HDR_SHCUT_SETTING); + val &= (~(B_AX_MAC_MPDU_PROC_EN | + B_AX_SHCUT_LLC_WR_LOCK | + B_AX_SHCUT_PARSE_DASA)); + MAC_REG_W32(R_AX_HDR_SHCUT_SETTING, val); + } + + return MACSUCCESS; +} +#endif + diff --git a/phl/hal_g6/mac/mac_ax/hdr_conv.h b/phl/hal_g6/mac/mac_ax/hdr_conv.h new file mode 100644 index 0000000..8e197c9 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hdr_conv.h @@ -0,0 +1,56 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_HDR_CONV_H_ +#define _MAC_AX_HDR_CONV_H_ + +#include "../type.h" + +/** + * @struct mac_ax_en_hdr_conv + * @brief mac_ax_en_hdr_conv + * + * @var mac_ax_en_hdr_conv::enable + * Please Place Description here. + * @var mac_ax_en_hdr_conv::rsvd0 + * Please Place Description here. + */ +struct mac_ax_en_hdr_conv { + u32 enable: 1; + u32 rsvd0: 31; +}; + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ +/** + * @brief mac_hdr_conv + * + * @param *adapter + * @param en_hdr_conv + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/hw.c b/phl/hal_g6/mac/mac_ax/hw.c new file mode 100644 index 0000000..8ed47c3 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hw.c @@ -0,0 +1,2780 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "hw.h" +#include "coex.h" +#include "twt.h" +#include "fwofld.h" +#include "rrsr.h" + +static struct mac_ax_host_rpr_cfg rpr_cfg_poh = { + 121, /* agg */ + 255, /* tmr */ + 0, /* agg_def */ + 0, /* tmr_def */ + 0, /* rsvd */ + MAC_AX_FUNC_EN, /* txok_en */ + MAC_AX_FUNC_EN, /* rty_lmt_en */ + MAC_AX_FUNC_EN, /* lft_drop_en */ + MAC_AX_FUNC_EN /* macid_drop_en */ +}; + +static struct mac_ax_host_rpr_cfg rpr_cfg_stf = { + 121, /* agg */ + 255, /* tmr */ + 0, /* agg_def */ + 0, /* tmr_def */ + 0, /* rsvd */ + MAC_AX_FUNC_DIS, /* txok_en */ + MAC_AX_FUNC_DIS, /* rty_lmt_en */ + MAC_AX_FUNC_DIS, /* lft_drop_en */ + MAC_AX_FUNC_DIS /* macid_drop_en */ +}; + +static void get_delay_tx_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_delay_tx_cfg *cfg); +static void set_delay_tx_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_delay_tx_cfg *cfg); + +struct mac_ax_hw_info *mac_get_hw_info(struct mac_ax_adapter *adapter) +{ + return adapter->hw_info->done ? adapter->hw_info : NULL; +} + +u8 shift_mask(u32 mask) +{ + u8 i; + + for (i = 0; i < 32; i++) { + if ((mask >> i) & BIT0) + break; + } + + return i; +} + +u32 get_block_tx_sel_msk(enum mac_ax_block_tx_sel src, u32 *msk) +{ + switch (src) { + case MAC_AX_CCA: + *msk = B_AX_CCA_EN; + break; + case MAC_AX_SEC20_CCA: + *msk = B_AX_SEC20_EN; + break; + case MAC_AX_SEC40_CCA: + *msk = B_AX_SEC40_EN; + break; + case MAC_AX_SEC80_CCA: + *msk = B_AX_SEC80_EN; + break; + case MAC_AX_EDCCA: + *msk = B_AX_EDCCA_EN; + break; + case MAC_AX_BTCCA: + *msk = B_AX_BTCCA_EN; + break; + case MAC_AX_TX_NAV: + *msk = B_AX_TX_NAV_EN; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 cfg_block_tx(struct mac_ax_adapter *adapter, + enum mac_ax_block_tx_sel src, u8 band, u8 en) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val, msk, ret; + u32 reg = band == 0 ? R_AX_CCA_CFG_0 : R_AX_CCA_CFG_0_C1; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret) { + PLTFM_MSG_ERR("%s: CMAC%d is NOT enabled\n", __func__, band); + return ret; + } + + ret = get_block_tx_sel_msk(src, &msk); + if (ret) { + PLTFM_MSG_ERR("%s: %d is NOT supported\n", __func__, src); + return ret; + } + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)reg, msk, + en ? 1 : 0, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + + return ret; + } +#endif + val = MAC_REG_R32(reg); + + if (en) + val = val | msk; + else + val = val & ~msk; + MAC_REG_W32(reg, val); + + return MACSUCCESS; +} + +u32 get_block_tx(struct mac_ax_adapter *adapter, + enum mac_ax_block_tx_sel src, u8 band, u8 *en) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val, msk, ret; + u32 reg = band == 0 ? R_AX_CCA_CFG_0 : R_AX_CCA_CFG_0_C1; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret) { + PLTFM_MSG_ERR("%s: CMAC%d is NOT enabled", __func__, band); + return ret; + } + + val = MAC_REG_R32(reg); + + ret = get_block_tx_sel_msk(src, &msk); + if (ret) { + PLTFM_MSG_ERR("%s: %d is NOT supported\n", __func__, src); + return ret; + } + + *en = !!(val & msk); + + return MACSUCCESS; +} + +u32 set_enable_bb_rf(struct mac_ax_adapter *adapter, u8 enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 value32; + u8 value8; + u32 ret; + u8 wl_rfc_s0, wl_rfc_s1; + + if (enable == 1) { + value8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + value8 |= B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN; + MAC_REG_W8(R_AX_SYS_FUNC_EN, value8); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 |= B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | + B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1; + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + + value8 = PHYREG_SET_ALL_CYCLE; + MAC_REG_W8(R_AX_PHYREG_SET, value8); + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + /* RDC KS/BB suggest : write 1 then write 0 then write 1 */ + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 | B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 & ~B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 | B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s0 = (wl_rfc_s0 | 0x07); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s1 = (wl_rfc_s1 | 0x07); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + value8 = PHYREG_SET_XYN_CYCLE; + MAC_REG_W8(R_AX_PHYREG_SET, value8); + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + /* RDC KS/BB suggest : write 1 then write 0 then write 1 */ + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 | B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 & ~B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 = (value32 | B_AX_AFC_AFEDIG); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s0 = (wl_rfc_s0 | 0x07); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s1 = (wl_rfc_s1 | 0x07); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + return MACCHIPID; + } + adapter->sm.bb0_func = MAC_AX_FUNC_ON; + } else { + adapter->sm.bb0_func = MAC_AX_FUNC_OFF; + value8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + value8 &= (~(B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN)); + MAC_REG_W8(R_AX_SYS_FUNC_EN, value8); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + value32 = MAC_REG_R32(R_AX_WLRF_CTRL); + value32 &= (~(B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | + B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1)); + MAC_REG_W32(R_AX_WLRF_CTRL, value32); + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s0 = (wl_rfc_s0 & 0xF8); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + wl_rfc_s1 = (wl_rfc_s1 & 0xF8); + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + return MACSUCCESS; + } else { + return MACCHIPID; + } + } + + return MACSUCCESS; +} + +static u32 set_append_fcs(struct mac_ax_adapter *adapter, u8 enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 value8; + + value8 = MAC_REG_R8(R_AX_MPDU_PROC); + value8 = enable == 1 ? value8 | B_AX_APPEND_FCS : + value8 & ~B_AX_APPEND_FCS; + MAC_REG_W8(R_AX_MPDU_PROC, value8); + + return MACSUCCESS; +} + +static u32 set_accept_icverr(struct mac_ax_adapter *adapter, u8 enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 value8; + + value8 = MAC_REG_R8(R_AX_MPDU_PROC); + value8 = enable == 1 ? (value8 | B_AX_A_ICV_ERR) : + (value8 & ~B_AX_A_ICV_ERR); + MAC_REG_W8(R_AX_MPDU_PROC, value8); + + return MACSUCCESS; +} + +u32 set_gt3_timer(struct mac_ax_adapter *adapter, + struct mac_ax_gt3_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = (cfg->count_en ? B_AX_GT3_COUNT_EN : 0) | + (cfg->mode ? B_AX_GT3_MODE : 0) | + (cfg->gt3_en ? B_AX_GT3_EN : 0) | + (cfg->sort_en ? B_AX_GT3_SORT_EN : 0) | + SET_WORD(cfg->timeout, B_AX_GT3_DATA); + + MAC_REG_W32(R_AX_GT3_CTRL, val32); + + return MACSUCCESS; +} + +u32 set_cctl_rty_limit(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_rty_lmt_cfg *cfg) +{ +#define DFLT_DATA_RTY_LIMIT 32 +#define DFLT_RTS_RTY_LIMIT 15 + struct mac_ax_cctl_info info; + struct mac_ax_cctl_info mask; + u32 data_rty, rts_rty; + + PLTFM_MEMSET(&mask, 0, sizeof(struct mac_ax_cctl_info)); + PLTFM_MEMSET(&info, 0, sizeof(struct mac_ax_cctl_info)); + + data_rty = cfg->data_lmt_val == 0 ? + DFLT_DATA_RTY_LIMIT : cfg->data_lmt_val; + rts_rty = cfg->rts_lmt_val == 0 ? + DFLT_RTS_RTY_LIMIT : cfg->rts_lmt_val; + info.data_txcnt_lmt_sel = cfg->data_lmt_sel; + info.data_tx_cnt_lmt = data_rty; + info.rts_txcnt_lmt_sel = cfg->rts_lmt_sel; + info.rts_txcnt_lmt = rts_rty; + + mask.data_txcnt_lmt_sel = TXCNT_LMT_MSK; + mask.data_tx_cnt_lmt = FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_MSK; + mask.rts_txcnt_lmt_sel = TXCNT_LMT_MSK; + mask.rts_txcnt_lmt = FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_MSK; + + mac_upd_cctl_info(adapter, &info, &mask, cfg->macid, TBL_WRITE_OP); + + return MACSUCCESS; +} + +u32 get_data_rty_limit(struct mac_ax_adapter *adapter, + struct mac_ax_rty_lmt *rty) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + struct mac_role_tbl *role; + u32 offset; + u8 band; + + role = mac_role_srch(adapter, rty->macid); + if (!role) { + PLTFM_MSG_ERR("%s: The MACID%d does not exist\n", + __func__, rty->macid); + return MACNOITEM; + } + + if (role->info.c_info.data_txcnt_lmt_sel) { + rty->tx_cnt = role->info.c_info.data_tx_cnt_lmt; + } else { + band = role->info.wmm < 2 ? 0 : 1; + offset = band == 0 ? R_AX_TXCNT + 2 : R_AX_TXCNT_C1 + 2; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret == MACSUCCESS) + rty->tx_cnt = MAC_REG_R8(offset); + } + + return ret; +} + +u32 set_bacam_mode(struct mac_ax_adapter *adapter, u8 mode_sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL) & (~B_AX_BACAM_ENT_CFG); + + if (mode_sel) + MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32 | B_AX_BACAM_ENT_CFG); + else + MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32); + + return MACSUCCESS; +} + +u32 set_xtal_aac(struct mac_ax_adapter *adapter, u8 aac_mode) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + + val8 = MAC_REG_R8(R_AX_XTAL_ON_CTRL2); + val8 &= ~(0x30); + val8 |= ((aac_mode & B_AX_AAC_MODE_MSK) << B_AX_AAC_MODE_SH); + MAC_REG_W8(R_AX_XTAL_ON_CTRL2, val8); + + return MACSUCCESS; +} + +u32 set_partial_pld_mode(struct mac_ax_adapter *adapter, u8 enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + if (enable) { + val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL); + val32 |= B_AX_TX_PARTIAL_MODE; + MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32); + } else { + val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL); + val32 &= ~B_AX_TX_PARTIAL_MODE; + MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32); + } + + return MACSUCCESS; +} + +u32 set_nav_padding(struct mac_ax_adapter *adapter, + struct mac_ax_nav_padding *nav) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_txop = nav->band ? R_AX_PROT_0_C1 : R_AX_PROT_0; + u32 reg_cnt = nav->band ? R_AX_PROT_C1 : R_AX_PROT; + u32 ret; + u8 val8; +#if MAC_AX_FW_REG_OFLD + u16 tmp; +#endif + + ret = check_mac_en(adapter, nav->band, MAC_AX_CMAC_SEL); + if (ret) + return ret; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + tmp = nav->nav_pad_en ? nav->nav_padding : 0; + ret = MAC_REG_W16_OFLD((u16)reg_txop, + tmp, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W16_OFLD((u16)reg_cnt, + tmp, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + ret = MAC_REG_W_OFLD((u16)reg_cnt, B_AX_NAV_OVER_TXOP_EN, + nav->over_txop_en ? 1 : 0, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } + + return MACSUCCESS; + } +#endif + + if (nav->nav_pad_en) { + MAC_REG_W16(reg_txop, nav->nav_padding); + MAC_REG_W16(reg_cnt, nav->nav_padding); + val8 = MAC_REG_R8(reg_cnt + 2); + if (nav->over_txop_en) + val8 |= BIT(0); + else + val8 &= ~BIT(0); + MAC_REG_W8(reg_cnt + 2, val8); + } else { + MAC_REG_W16(reg_txop, 0); + MAC_REG_W16(reg_cnt, 0); + } + + return MACSUCCESS; +} + +static void set_delay_tx_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_delay_tx_cfg *cfg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_SS_CTRL); + SET_CLR_WORD(val32, cfg->en, B_AX_SS_DELAY_TX_BAND_SEL); + MAC_REG_W32(R_AX_SS_CTRL, val32); + + val32 = SET_WORD(cfg->vovi_to_b0, B_AX_SS_VOVI_TO_0) | + SET_WORD(cfg->bebk_to_b0, B_AX_SS_BEBK_TO_0) | + SET_WORD(cfg->vovi_to_b1, B_AX_SS_VOVI_TO_1) | + SET_WORD(cfg->bebk_to_b1, B_AX_SS_BEBK_TO_1); + MAC_REG_W32(R_AX_SS_DELAYTX_TO, val32); + + val32 = SET_WORD(cfg->vovi_len_b0, B_AX_SS_VOVI_LEN_THR_0) | + SET_WORD(cfg->bebk_len_b0, B_AX_SS_BEBK_LEN_THR_0) | + SET_WORD(cfg->vovi_len_b1, B_AX_SS_VOVI_LEN_THR_1) | + SET_WORD(cfg->bebk_len_b1, B_AX_SS_BEBK_LEN_THR_1); + MAC_REG_W32(R_AX_SS_DELAYTX_LEN_THR, val32); +} + +u32 set_core_swr_volt(struct mac_ax_adapter *adapter, + enum mac_ax_core_swr_volt volt_sel) +{ + u8 i, j, adjust = 0; + s8 sign = 0, v, val8; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val8 = adapter->hw_info->core_swr_volt_sel - volt_sel; + if (val8 == 0) { + return MACSUCCESS; + } else if (val8 > 0) { + adjust = adapter->hw_info->core_swr_volt_sel - volt_sel; + sign = -1; + } else { + adjust = volt_sel - adapter->hw_info->core_swr_volt_sel; + sign = 1; + } + + for (i = 0; i < adjust; i++) { + val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0); + v = GET_FIELD(val8, B_AX_VOL_L1); + v += sign; + if (v < CORE_SWR_VOLT_MIN) + v = CORE_SWR_VOLT_MIN; + else if (v > CORE_SWR_VOLT_MAX) + v = CORE_SWR_VOLT_MAX; + + val8 = SET_CLR_WORD(val8, v, B_AX_VOL_L1); + MAC_REG_W8(R_AX_SPSLDO_ON_CTRL0, val8); + for (j = 0; j < POLL_SWR_VOLT_CNT; j++) + PLTFM_DELAY_US(POLL_SWR_VOLT_US); + } + + if (volt_sel == MAC_AX_SWR_NORM) { + val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0); + val8 = SET_CLR_WORD(val8, adapter->hw_info->core_swr_volt, + B_AX_VOL_L1); + MAC_REG_W8(R_AX_SPSLDO_ON_CTRL0, val8); + } + + adapter->hw_info->core_swr_volt_sel = volt_sel; + + return MACSUCCESS; +} + +u32 set_macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_cfg *cfg) +{ + u32 val32; + u8 macid_sh = cfg->macid & (32 - 1); + u8 macid_grp = cfg->macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + struct mac_ax_macid_pause_grp grp = {{0}}; + + ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret) + return ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + if (cfg->pause) { + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_0); + MAC_REG_W32(R_AX_MACID_SLEEP_0, + val32 | BIT(macid_sh)); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, + val32 | BIT(macid_sh)); + break; + case 1: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_1); + MAC_REG_W32(R_AX_MACID_SLEEP_1, + val32 | BIT(macid_sh)); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, + val32 | BIT(macid_sh)); + break; + case 2: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_2); + MAC_REG_W32(R_AX_MACID_SLEEP_2, + val32 | BIT(macid_sh)); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, + val32 | BIT(macid_sh)); + break; + case 3: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_3); + MAC_REG_W32(R_AX_MACID_SLEEP_3, + val32 | BIT(macid_sh)); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, + val32 | BIT(macid_sh)); + break; + default: + break; + } + } else { + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_0); + MAC_REG_W32(R_AX_MACID_SLEEP_0, + val32 & ~(BIT(macid_sh))); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, + val32 & ~(BIT(macid_sh))); + break; + case 1: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_1); + MAC_REG_W32(R_AX_MACID_SLEEP_1, + val32 & ~(BIT(macid_sh))); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, + val32 & ~(BIT(macid_sh))); + break; + case 2: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_2); + MAC_REG_W32(R_AX_MACID_SLEEP_2, + val32 & ~(BIT(macid_sh))); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, + val32 & ~(BIT(macid_sh))); + break; + case 3: + val32 = MAC_REG_R32(R_AX_MACID_SLEEP_3); + MAC_REG_W32(R_AX_MACID_SLEEP_3, + val32 & ~(BIT(macid_sh))); + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3); + MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, + val32 & ~(BIT(macid_sh))); + break; + default: + break; + } + } + } else { + grp.mask_grp[macid_grp] = BIT(macid_sh); + grp.pause_grp[macid_grp] = cfg->pause << macid_sh; + + ret = macid_pause(adapter, &grp); + + if (ret) + return ret; + } + return MACSUCCESS; +} + +u32 macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_grp *grp) +{ + u32 ret, size; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + + ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret) + return ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + size = sizeof(struct mac_ax_macid_pause_grp); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, size); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMCPY(buf, grp, size); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_MACID_PAUSE, + 1, 0); + if (ret) + goto fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx\n"); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + return ret; +} + +u32 set_ss_quota_mode(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_mode_ctrl *ctrl) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32_wmm, val32_ul, ret; + + val32_wmm = MAC_REG_R32(R_AX_SS_DL_QUOTA_CTRL); + val32_ul = MAC_REG_R32(R_AX_SS_UL_QUOTA_CTRL); + switch (ctrl->wmm) { + case MAC_AX_SS_WMM0: + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT) + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm | B_AX_SS_QUOTA_MODE_0); + else + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm & ~B_AX_SS_QUOTA_MODE_0); + break; + case MAC_AX_SS_WMM1: + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT) + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm | B_AX_SS_QUOTA_MODE_1); + else + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm & ~B_AX_SS_QUOTA_MODE_1); + break; + case MAC_AX_SS_WMM2: + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT) + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm | B_AX_SS_QUOTA_MODE_2); + else + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm & ~B_AX_SS_QUOTA_MODE_2); + break; + case MAC_AX_SS_WMM3: + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT) + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm | B_AX_SS_QUOTA_MODE_3); + else + MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL, + val32_wmm & ~B_AX_SS_QUOTA_MODE_3); + break; + case MAC_AX_SS_UL: + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT) + MAC_REG_W32(R_AX_SS_UL_QUOTA_CTRL, + val32_ul | B_AX_SS_QUOTA_MODE_UL); + else + MAC_REG_W32(R_AX_SS_UL_QUOTA_CTRL, + val32_ul & ~B_AX_SS_QUOTA_MODE_UL); + break; + } +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + switch (ctrl->wmm) { + case MAC_AX_SS_WMM0: + case MAC_AX_SS_WMM1: + case MAC_AX_SS_UL: + ret = check_mac_en(adapter, 0, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) { + MAC_REG_W_OFLD(R_AX_PTCL_ATM, + B_AX_ATM_AIRTIME_EN, 1, 1); + } + break; + case MAC_AX_SS_WMM2: + case MAC_AX_SS_WMM3: + ret = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) { + MAC_REG_W_OFLD(R_AX_PTCL_ATM_C1, + B_AX_ATM_AIRTIME_EN, 1, 1); + } + break; + } + + return MACSUCCESS; + } +#endif + + switch (ctrl->wmm) { + case MAC_AX_SS_WMM0: + case MAC_AX_SS_WMM1: + case MAC_AX_SS_UL: + ret = check_mac_en(adapter, 0, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + val32_wmm = MAC_REG_R32(R_AX_PTCL_ATM); + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) + MAC_REG_W32(R_AX_PTCL_ATM, + val32_wmm | B_AX_ATM_AIRTIME_EN); + break; + case MAC_AX_SS_WMM2: + case MAC_AX_SS_WMM3: + ret = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + val32_wmm = MAC_REG_R32(R_AX_PTCL_ATM_C1); + if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) + MAC_REG_W32(R_AX_PTCL_ATM_C1, + val32_wmm | B_AX_ATM_AIRTIME_EN); + break; + } + + return MACSUCCESS; +} + +u32 ss_set_quotasetting(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_setting *para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 cnt = 1000; + + if (para->ul_dl == mac_ax_issue_ul) { + val32 = (B_AX_SS_OWN | + SET_WORD(SS_W_QUOTA_SETTING, B_AX_SS_CMD_SEL) | + BIT(23) | SET_WORD(para->val, B_AX_SS_VALUE) | + para->macid); + MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, val32); + } else { + val32 = (B_AX_SS_OWN | + SET_WORD(SS_W_QUOTA_SETTING, B_AX_SS_CMD_SEL) | + SET_WORD(para->ac_type, B_AX_SS_AC) | + SET_WORD(para->val, B_AX_SS_VALUE) | para->macid); + MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, val32); + } + + while (--cnt) { + val32 = MAC_REG_R32(R_AX_SS_SRAM_CTRL_1); + if ((val32 & B_AX_SS_OWN) == 0) + break; + PLTFM_DELAY_US(1); + } + + if (!cnt) { + PLTFM_MSG_ERR("SS Set quota setting fail!!\n"); + return MACPOLLTO; + } + + return MACSUCCESS; +} + +u32 scheduler_set_prebkf(struct mac_ax_adapter *adapter, + struct mac_ax_prebkf_setting *para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg, val32; +#if MAC_AX_FW_REG_OFLD + u32 ret; +#endif + + reg = para->band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 : + R_AX_PREBKF_CFG_0; +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)reg, B_AX_PREBKF_TIME_MSK, para->val, + 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + + return MACSUCCESS; + } +#endif + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, para->val, B_AX_PREBKF_TIME); + MAC_REG_W32(reg, val32); + + return MACSUCCESS; +} + +u32 mac_get_tx_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_tx_cnt *cnt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 txcnt_addr; + u32 val32; + u16 val16; + u8 sel; + + if (cnt->band != 0 && cnt->band != 1) + return MACNOITEM; + if (check_mac_en(adapter, cnt->band, MAC_AX_CMAC_SEL)) + return MACHWNOTEN; + txcnt_addr = (cnt->band == MAC_AX_BAND_0) ? + R_AX_TX_PPDU_CNT : R_AX_TX_PPDU_CNT_C1; + for (sel = 0; sel < MAC_AX_TX_ALLTYPE; sel++) { + val16 = MAC_REG_R16(txcnt_addr); + val16 = SET_CLR_WORD(val16, sel, B_AX_PPDU_CNT_IDX); + MAC_REG_W16(txcnt_addr, val16); + PLTFM_DELAY_US(1000); + val32 = MAC_REG_R32(txcnt_addr); + cnt->txcnt[sel] = GET_FIELD(val32, B_AX_TX_PPDU_CNT); + } + return MACSUCCESS; +} + +u32 cfg_wdt_isr_rst(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + + val = val & ~B_AX_APB_WRAP_EN; + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val); + + val = val | B_AX_APB_WRAP_EN; + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val); + + return MACSUCCESS; +} + +u32 mac_clr_tx_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_tx_cnt *cnt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u16 txcnt_addr; + u16 val16; + u16 to; + u8 i; + + if (cnt->band != 0 && cnt->band != 1) + return MACNOITEM; + if (check_mac_en(adapter, cnt->band, MAC_AX_CMAC_SEL)) + return MACHWNOTEN; + if (cnt->sel > MAC_AX_TX_ALLTYPE) + return MACNOITEM; + + txcnt_addr = (cnt->band == MAC_AX_BAND_0) ? + R_AX_TX_PPDU_CNT : R_AX_TX_PPDU_CNT_C1; + +#if MAC_AX_FW_REG_OFLD + u32 ret; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + for (i = 0; i < MAC_AX_TX_ALLTYPE; i++) { + if (cnt->sel == MAC_AX_TX_ALLTYPE || i == cnt->sel) { + ret = MAC_REG_W_OFLD(txcnt_addr, + B_AX_PPDU_CNT_RIDX_MSK << + B_AX_PPDU_CNT_RIDX_SH, + i, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, txcnt_addr, ret); + return ret; + } + ret = MAC_REG_W_OFLD(txcnt_addr, B_AX_RST_PPDU_CNT, + 1, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, txcnt_addr, ret); + return ret; + } + ret = MAC_REG_P_OFLD(txcnt_addr, B_AX_RST_PPDU_CNT, 0, + (cnt->sel != MAC_AX_TX_ALLTYPE || + i == MAC_AX_TX_ALLTYPE - 1) ? + 1 : 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: poll offload fail;" + "offset: %u, ret: %u\n", + __func__, txcnt_addr, ret); + return ret; + } + } + } + return MACSUCCESS; + } +#endif + to = 1000; + for (i = 0; i < MAC_AX_TX_ALLTYPE; i++) { + if (cnt->sel == MAC_AX_TX_ALLTYPE || i == cnt->sel) { + val16 = MAC_REG_R16(txcnt_addr); + val16 = SET_CLR_WORD(val16, i, B_AX_PPDU_CNT_RIDX) | + B_AX_RST_PPDU_CNT; + MAC_REG_W16(txcnt_addr, val16); + while (to--) { + val16 = MAC_REG_R16(txcnt_addr); + if (!(val16 & B_AX_RST_PPDU_CNT)) + break; + PLTFM_DELAY_US(5); + } + if (to == 0) + return MACPOLLTO; + } + } + return MACSUCCESS; +} + +u32 mac_set_hw_value(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *val) +{ + u32 ret = MACSUCCESS; + + if (!val) { + PLTFM_MSG_ERR("[ERR]: the parameter is NULL in %s\n", __func__); + return MACNPTR; + } + + switch (hw_id) { + case MAC_AX_HW_SETTING: + break; + case MAC_AX_HW_SET_ID_PAUSE: + ret = set_macid_pause(adapter, + (struct mac_ax_macid_pause_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_SET_MULTI_ID_PAUSE: + ret = macid_pause(adapter, + (struct mac_ax_macid_pause_grp *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_SET_SCH_TXEN_CFG: + ret = set_hw_sch_tx_en(adapter, + (struct mac_ax_sch_tx_en_cfg *)val); + break; + case MAC_AX_HW_SET_AMPDU_CFG: + ret = set_hw_ampdu_cfg(adapter, (struct mac_ax_ampdu_cfg *)val); + break; + case MAC_AX_HW_SET_USR_EDCA_PARAM: + ret = + set_hw_usr_edca_param(adapter, + (struct mac_ax_usr_edca_param *)val); + break; + case MAC_AX_HW_SET_USR_TX_RPT_CFG: + ret = + set_hw_usr_tx_rpt_cfg(adapter, + (struct mac_ax_usr_tx_rpt_cfg *)val); + break; + case MAC_AX_HW_SET_EDCA_PARAM: + ret = set_hw_edca_param(adapter, + (struct mac_ax_edca_param *)val); + break; + case MAC_AX_HW_SET_EDCCA_PARAM: + ret = set_hw_edcca_param(adapter, + (struct mac_ax_edcca_param *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_SET_MUEDCA_PARAM: + ret = set_hw_muedca_param(adapter, + (struct mac_ax_muedca_param *)val); + break; + case MAC_AX_HW_SET_MUEDCA_CTRL: + ret = set_hw_muedca_ctrl(adapter, + (struct mac_ax_muedca_cfg *)val); + break; + case MAC_AX_HW_SET_TBPPDU_CTRL: + ret = set_hw_tb_ppdu_ctrl(adapter, + (struct mac_ax_tb_ppdu_ctrl *)val); + break; + case MAC_AX_HW_SET_HOST_RPR: + set_host_rpr(adapter, (struct mac_ax_host_rpr_cfg *)val); + break; + case MAC_AX_HW_SET_DELAYTX_CFG: + set_delay_tx_cfg(adapter, (struct mac_ax_delay_tx_cfg *)val); + break; + case MAC_AX_HW_SET_BW_CFG: + ret = cfg_mac_bw(adapter, (struct mac_ax_cfg_bw *)val); + break; + case MAC_AX_HW_SET_CH_BUSY_STAT_CFG: + ret = set_hw_ch_busy_cnt(adapter, + (struct mac_ax_ch_busy_cnt_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_SET_LIFETIME_CFG: + ret = set_hw_lifetime_cfg(adapter, + (struct mac_ax_lifetime_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_EN_BB_RF: + ret = set_enable_bb_rf(adapter, *(u8 *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_SET_APP_FCS: + set_append_fcs(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_RX_ICVERR: + set_accept_icverr(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_CCTL_RTY_LMT: + set_cctl_rty_limit(adapter, + (struct mac_ax_cctl_rty_lmt_cfg *)val); + break; + case MAC_AX_HW_SET_COEX_GNT: + ret = mac_cfg_gnt(adapter, (struct mac_ax_coex_gnt *)val); + break; + case MAC_AX_HW_SET_SCOREBOARD: + mac_cfg_sb(adapter, *(u32 *)val); + break; + case MAC_AX_HW_SET_POLLUTED: + mac_cfg_plt(adapter, (struct mac_ax_plt *)val); + break; + case MAC_AX_HW_SET_COEX_CTRL: + mac_cfg_ctrl_path(adapter, *(u32 *)val); + break; + case MAC_AX_HW_SET_CLR_TX_CNT: + ret = mac_clr_tx_cnt(adapter, (struct mac_ax_tx_cnt *)val); + break; + case MAC_AX_HW_SET_SLOT_TIME: + mac_set_slot_time(adapter, *(enum mac_ax_slot_time *)val); + break; + case MAC_AX_HW_SET_XTAL_AAC_MODE: + set_xtal_aac(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_NAV_PADDING: + ret = set_nav_padding(adapter, (struct mac_ax_nav_padding *)val); + break; + case MAC_AX_HW_SET_MAX_TX_TIME: + ret = mac_set_cctl_max_tx_time(adapter, + (struct mac_ax_max_tx_time *) + val); + break; + case MAC_AX_HW_SET_SS_QUOTA_MODE: + ret = set_ss_quota_mode(adapter, + (struct mac_ax_ss_quota_mode_ctrl *)val); + break; + case MAC_AX_HW_SET_SS_QUOTA_SETTING: + ret = ss_set_quotasetting(adapter, + (struct mac_ax_ss_quota_setting *)val); + break; + case MAC_AX_HW_SET_SCHE_PREBKF: + ret = scheduler_set_prebkf(adapter, + (struct mac_ax_prebkf_setting *)val); + break; + case MAC_AX_HW_SET_WDT_ISR_RST: + ret = cfg_wdt_isr_rst(adapter); + break; + case MAC_AX_HW_SET_RESP_ACK: + ret = set_mac_resp_ack(adapter, (u32 *)val); + break; + case MAC_AX_HW_SET_HW_RTS_TH: + ret = mac_set_hw_rts_th(adapter, + (struct mac_ax_hw_rts_th *)val); + break; + case MAC_AX_HW_SET_TX_RU26_TB: + ret = mac_set_tx_ru26_tb(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_BACAM_MODE_SEL: + ret = set_bacam_mode(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_CORE_SWR_VOLT: + ret = set_core_swr_volt(adapter, + *(enum mac_ax_core_swr_volt *)val); + break; + case MAC_AX_HW_SET_PARTIAL_PLD_MODE: + ret = set_partial_pld_mode(adapter, *(u8 *)val); + break; + case MAC_AX_HW_SET_RRSR_CFG: + ret = mac_set_rrsr_cfg(adapter, + (struct mac_ax_rrsr_cfg *)val); + break; + case MAC_AX_HW_SET_CTS_RRSR_CFG: + ret = mac_set_cts_rrsr_cfg(adapter, + (struct mac_ax_cts_rrsr_cfg *)val); + break; + case MAC_AX_HW_SET_GT3_TIMER: + ret = set_gt3_timer(adapter, + (struct mac_ax_gt3_cfg *)val); + break; +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_HW_SDIO_INFO: + set_info_sdio(adapter, (struct mac_ax_sdio_info *)val); + break; + case MAC_AX_HW_SDIO_TX_MODE: + ret = tx_mode_cfg_sdio(adapter, + *(enum mac_ax_sdio_tx_mode *)val); + break; + case MAC_AX_HW_SDIO_RX_AGG: + rx_agg_cfg_sdio(adapter, (struct mac_ax_rx_agg_cfg *)val); + break; + case MAC_AX_HW_SDIO_TX_AGG: + ret = tx_agg_cfg_sdio(adapter, + (struct mac_ax_sdio_txagg_cfg *)val); + break; + case MAC_AX_HW_SDIO_AVAL_PAGE: + aval_page_cfg_sdio(adapter, (struct mac_ax_aval_page_cfg *)val); + break; + case MAC_AX_HW_SDIO_MON_WT: + set_wt_cfg_sdio(adapter, *(u8 *)val); + break; +#endif +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_HW_PCIE_CFGSPC_SET: + ret = cfgspc_set_pcie(adapter, + (struct mac_ax_pcie_cfgspc_param *)val); + break; + case MAC_AX_HW_PCIE_RST_BDRAM: + ret = rst_bdram_pcie(adapter, *(u8 *)val); + break; + case MAX_AX_HW_PCIE_LTR_SW_TRIGGER: + ret = ltr_sw_trigger(adapter, + *(enum mac_ax_pcie_ltr_sw_ctrl *)val); + break; + case MAX_AX_HW_PCIE_MIT: + ret = pcie_trx_mit(adapter, + (struct mac_ax_pcie_trx_mitigation *)val); + break; + case MAX_AX_HW_PCIE_L2_LEAVE: + ret = set_pcie_l2_leave(adapter, *(u8 *)val); + break; +#endif + default: + return MACNOITEM; + } + + return ret; +} + +u32 get_macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_cfg *cfg) +{ + u32 val32 = 0; + u8 macid_grp = cfg->macid >> 5; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + + ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret) + return ret; + + switch (macid_grp) { + case 0: + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0) | + MAC_REG_R32(R_AX_MACID_SLEEP_0); + break; + case 1: + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1) | + MAC_REG_R32(R_AX_MACID_SLEEP_1); + break; + case 2: + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2) | + MAC_REG_R32(R_AX_MACID_SLEEP_2); + break; + case 3: + val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3) | + MAC_REG_R32(R_AX_MACID_SLEEP_3); + break; + default: + break; + } + cfg->pause = (u8)((val32 & BIT(cfg->macid & (32 - 1))) ? 1 : 0); + + return MACSUCCESS; +} + +u32 get_ss_wmm_tbl(struct mac_ax_adapter *adapter, + struct mac_ax_ss_wmm_tbl_ctrl *ctrl) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_SS_CTRL); + switch (ctrl->wmm) { + case 0: + ctrl->wmm_mapping = + (enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_0); + break; + case 1: + ctrl->wmm_mapping = + (enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_1); + break; + case 2: + ctrl->wmm_mapping = + (enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_2); + break; + case 3: + ctrl->wmm_mapping = + (enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_3); + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +static void get_delay_tx_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_delay_tx_cfg *cfg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_SS_CTRL); + cfg->en = + (enum mac_ax_delay_tx_en)GET_FIELD(val32, + B_AX_SS_DELAY_TX_BAND_SEL); + + val32 = MAC_REG_R32(R_AX_SS_DELAYTX_TO); + cfg->vovi_to_b0 = GET_FIELD(val32, B_AX_SS_VOVI_TO_0); + cfg->bebk_to_b0 = GET_FIELD(val32, B_AX_SS_BEBK_TO_0); + cfg->vovi_to_b1 = GET_FIELD(val32, B_AX_SS_VOVI_TO_1); + cfg->bebk_to_b1 = GET_FIELD(val32, B_AX_SS_BEBK_TO_1); + + val32 = MAC_REG_R32(R_AX_SS_DELAYTX_LEN_THR); + cfg->vovi_len_b0 = GET_FIELD(val32, B_AX_SS_VOVI_LEN_THR_0); + cfg->bebk_len_b0 = GET_FIELD(val32, B_AX_SS_BEBK_LEN_THR_0); + cfg->vovi_len_b1 = GET_FIELD(val32, B_AX_SS_VOVI_LEN_THR_1); + cfg->bebk_len_b1 = GET_FIELD(val32, B_AX_SS_BEBK_LEN_THR_1); +} + +static u32 get_append_fcs(struct mac_ax_adapter *adapter, u8 *enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + *enable = MAC_REG_R8(R_AX_MPDU_PROC) & B_AX_APPEND_FCS ? 1 : 0; + + return MACSUCCESS; +} + +static u32 get_accept_icverr(struct mac_ax_adapter *adapter, u8 *enable) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + *enable = MAC_REG_R8(R_AX_MPDU_PROC) & B_AX_A_ICV_ERR ? 1 : 0; + + return MACSUCCESS; +} + +u32 get_bacam_mode(struct mac_ax_adapter *adapter, u8 *mode_sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + *mode_sel = MAC_REG_R8(R_AX_RESPBA_CAM_CTRL) & B_AX_BACAM_ENT_CFG ? 1 : 0; + + return MACSUCCESS; +} + +u32 get_pwr_state(struct mac_ax_adapter *adapter, enum mac_ax_mac_pwr_st *st) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val; + + val = GET_FIELD(MAC_REG_R32(R_AX_IC_PWR_STATE), B_AX_WLMAC_PWR_STE); + + if (val == MAC_AX_MAC_OFF) { + *st = MAC_AX_MAC_OFF; + adapter->mac_pwr_info.pwr_in_lps = 0; + adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE; + adapter->sm.pwr = MAC_AX_PWR_OFF; + adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY; + PLTFM_MSG_WARN("WL MAC is in off state.\n"); + } else if (val == MAC_AX_MAC_ON) { + *st = MAC_AX_MAC_ON; + } else if (val == MAC_AX_MAC_LPS) { + *st = MAC_AX_MAC_LPS; + } else { + PLTFM_MSG_ERR("Unexpected MAC state = 0x%X\n", val); + return MACPWRSTAT; + } + + return MACSUCCESS; +} + +void get_dflt_nav(struct mac_ax_adapter *adapter, u16 *nav) +{ + /* data NAV is consist of SIFS and ACK/BA time */ + /* currently, we use SIFS + 64-bitmap BA as default NAV */ + /* we use OFDM-6M to estimate BA time */ + /* BA time = PLCP header(20us) + 32 bytes/data_rate */ + *nav = 63; +} + +u32 mac_get_hw_value(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *val) +{ + u32 ret = MACSUCCESS; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (!val) { + PLTFM_MSG_ERR("[ERR]: the parameter is NULL in %s\n", __func__); + return MACNPTR; + } + + switch (hw_id) { + case MAC_AX_HW_MAPPING: + break; + case MAC_AX_HW_GET_EFUSE_SIZE: + *(u32 *)val = adapter->hw_info->efuse_size + + adapter->hw_info->dav_efuse_size; + break; + case MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE: + *(u32 *)val = adapter->hw_info->log_efuse_size + + adapter->hw_info->dav_log_efuse_size; + break; + case MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE: + switch (adapter->hw_info->intf) { + case MAC_AX_INTF_PCIE: + *(u32 *)val = adapter->hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + *(u32 *)val = adapter->hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + *(u32 *)val = adapter->hw_info->limit_efuse_size_sdio; + break; + default: + *(u32 *)val = adapter->hw_info->log_efuse_size; + break; + } + *(u32 *)val += adapter->hw_info->dav_log_efuse_size; + break; + case MAC_AX_HW_GET_BT_EFUSE_SIZE: + *(u32 *)val = adapter->hw_info->bt_efuse_size; + break; + case MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE: + *(u32 *)val = adapter->hw_info->bt_log_efuse_size; + break; + case MAC_AX_HW_GET_EFUSE_MASK_SIZE: + *(u32 *)val = (adapter->hw_info->log_efuse_size + + adapter->hw_info->dav_log_efuse_size) >> 4; + break; + case MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE: + switch (adapter->hw_info->intf) { + case MAC_AX_INTF_PCIE: + *(u32 *)val = adapter->hw_info->limit_efuse_size_pcie; + break; + case MAC_AX_INTF_USB: + *(u32 *)val = adapter->hw_info->limit_efuse_size_usb; + break; + case MAC_AX_INTF_SDIO: + *(u32 *)val = adapter->hw_info->limit_efuse_size_sdio; + break; + default: + *(u32 *)val = adapter->hw_info->log_efuse_size; + break; + } + *(u32 *)val += adapter->hw_info->dav_log_efuse_size; + *(u32 *)val = *(u32 *)val >> 4; + break; + case MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE: + *(u32 *)val = adapter->hw_info->bt_log_efuse_size >> 4; + break; + case MAC_AX_HW_GET_EFUSE_VERSION_SIZE: + *(u32 *)val = adapter->hw_info->efuse_version_size; + break; + case MAC_AX_HW_GET_ID_PAUSE: + ret = get_macid_pause(adapter, + (struct mac_ax_macid_pause_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_SCH_TXEN_STATUS: + ret = get_hw_sch_tx_en(adapter, + (struct mac_ax_sch_tx_en_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_EDCA_PARAM: + ret = get_hw_edca_param(adapter, + (struct mac_ax_edca_param *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_TBPPDU_CTRL: + ret = get_hw_tb_ppdu_ctrl(adapter, + (struct mac_ax_tb_ppdu_ctrl *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_DELAYTX_CFG: + get_delay_tx_cfg(adapter, (struct mac_ax_delay_tx_cfg *)val); + break; + case MAC_AX_HW_GET_SS_WMM_TBL: + ret = get_ss_wmm_tbl(adapter, + (struct mac_ax_ss_wmm_tbl_ctrl *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_CH_STAT_CNT: + ret = get_hw_ch_stat_cnt(adapter, + (struct mac_ax_ch_stat_cnt *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_LIFETIME_CFG: + ret = get_hw_lifetime_cfg(adapter, + (struct mac_ax_lifetime_cfg *)val); + if (ret != MACSUCCESS) + return ret; + break; + case MAC_AX_HW_GET_APP_FCS: + get_append_fcs(adapter, (u8 *)val); + break; + case MAC_AX_HW_GET_RX_ICVERR: + get_accept_icverr(adapter, (u8 *)val); + break; + case MAC_AX_HW_GET_PWR_STATE: + get_pwr_state(adapter, (enum mac_ax_mac_pwr_st *)val); + break; + case MAC_AX_HW_GET_SCOREBOARD: + *(u32 *)val = MAC_REG_R32(R_AX_SCOREBOARD); + break; + case MAC_AX_HW_GET_BACAM_MODE_SEL: + get_bacam_mode(adapter, (u8 *)val); + break; +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_HW_SDIO_TX_AGG_SIZE: + *(u16 *)val = adapter->sdio_info.tx_align_size; + break; +#endif + case MAC_AX_HW_GET_WAKE_REASON: + ret = get_wake_reason(adapter, (u8 *)val); + if (ret != 0) + return ret; + break; + case MAC_AX_HW_GET_COEX_GNT: + ret = mac_get_gnt(adapter, (struct mac_ax_coex_gnt *)val); + break; + case MAC_AX_HW_GET_COEX_CTRL: + mac_get_ctrl_path(adapter, (u32 *)val); + break; + case MAC_AX_HW_GET_TX_CNT: + ret = mac_get_tx_cnt(adapter, (struct mac_ax_tx_cnt *)val); + if (ret != 0) + return ret; + break; + case MAC_AX_HW_GET_TSF: + mac_get_tsf(adapter, (struct mac_ax_port_tsf *)val); + break; + case MAC_AX_HW_GET_MAX_TX_TIME: + ret = mac_get_max_tx_time(adapter, + (struct mac_ax_max_tx_time *)val); + break; + case MAC_AX_HW_GET_POLLUTED_CNT: + mac_get_bt_polt_cnt(adapter, (struct mac_ax_bt_polt_cnt *)val); + break; + case MAC_AX_HW_GET_DATA_RTY_LMT: + get_data_rty_limit(adapter, (struct mac_ax_rty_lmt *)val); + break; + case MAC_AX_HW_GET_DFLT_NAV: + get_dflt_nav(adapter, (u16 *)val); + break; + case MAC_AX_HW_GET_FW_CAP: + ret = mac_get_fw_cap(adapter, (u32 *)val); + break; + case MAC_AX_HW_GET_RRSR_CFG: + ret = mac_get_rrsr_cfg(adapter, + (struct mac_ax_rrsr_cfg *)val); + break; + case MAC_AX_HW_GET_CTS_RRSR_CFG: + ret = mac_get_cts_rrsr_cfg(adapter, + (struct mac_ax_cts_rrsr_cfg *)val); + break; + case MAC_AX_HW_GET_USB_STS: + ret = ops->get_rx_state(adapter, (u32 *)val); + break; + default: + return MACNOITEM; + } + + return ret; +} + +u32 cfg_mac_bw(struct mac_ax_adapter *adapter, struct mac_ax_cfg_bw *cfg) +{ + u32 value32 = 0; + u8 value8 = 0; + u8 chk_val8 = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct rtw_hal_com_t *hal_com = + (struct rtw_hal_com_t *)adapter->drv_adapter; + + u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; + + switch (cfg->cbw) { + case CHANNEL_WIDTH_160: + txsc80 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch, + cfg->central_ch, cfg->cbw, + CHANNEL_WIDTH_80); + /* fall through */ + case CHANNEL_WIDTH_80: + txsc40 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch, + cfg->central_ch, cfg->cbw, + CHANNEL_WIDTH_40); + /* fall through */ + case CHANNEL_WIDTH_40: + txsc20 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch, + cfg->central_ch, cfg->cbw, + CHANNEL_WIDTH_20); + break; + default: + break; + } + +#if MAC_AX_FW_REG_OFLD + u32 ret; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (cfg->band) {//BAND1 + value8 = MAC_REG_R8(R_AX_WMAC_RFMOD_C1); + chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK_C1); + } else {//BAND0 + value8 = MAC_REG_R8(R_AX_WMAC_RFMOD); + chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK); + } + value8 = value8 & (~(BIT(0) | BIT(1))); + chk_val8 = chk_val8 & (~(BIT(0) | BIT(1))); + + switch (cfg->cbw) { + case CHANNEL_WIDTH_160: + value8 = value8 | BIT(1) | BIT(0); + value32 = txsc20 | (txsc40 << 4) | (txsc80 << 8); //TXSC_160M; + break; + case CHANNEL_WIDTH_80: + value8 = value8 | BIT(1); + value32 = txsc20 | (txsc40 << 4); //TXSC_80M; + break; + case CHANNEL_WIDTH_40: + value8 = value8 | BIT(0); + value32 = txsc20; //TXSC_40M; + break; + case CHANNEL_WIDTH_20: + value32 = 0; //TXSC_20M; + break; + default: + break; + } + + if (cfg->pri_ch >= CHANNEL_5G) + chk_val8 |= B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; + + if (cfg->band) {//BAND1 + ret = MAC_REG_W_OFLD(R_AX_WMAC_RFMOD_C1, B_AX_WMAC_RFMOD_MSK, + value8, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_TXRATE_CHK_C1, 0x3, chk_val8, + 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + ret = MAC_REG_W32_OFLD(R_AX_TX_SUB_CARRIER_VALUE_C1, + value32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + } else { + ret = MAC_REG_W_OFLD(R_AX_WMAC_RFMOD, B_AX_WMAC_RFMOD_MSK, + value8, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + ret = MAC_REG_W_OFLD(R_AX_TXRATE_CHK, 0x3, chk_val8, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + ret = MAC_REG_W32_OFLD(R_AX_TX_SUB_CARRIER_VALUE, + value32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + } + + return MACSUCCESS; + } +#endif + if (cfg->band) {//BAND1 + value8 = MAC_REG_R8(R_AX_WMAC_RFMOD_C1); + chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK_C1); + } else {//BAND0 + value8 = MAC_REG_R8(R_AX_WMAC_RFMOD); + chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK); + } + value8 = value8 & (~(BIT(0) | BIT(1))); + chk_val8 = chk_val8 & (~(BIT(0) | BIT(1))); + + switch (cfg->cbw) { + case CHANNEL_WIDTH_160: + value8 = value8 | BIT(1) | BIT(0); + value32 = txsc20 | (txsc40 << 4) | (txsc80 << 8); //TXSC_160M; + break; + case CHANNEL_WIDTH_80: + value8 = value8 | BIT(1); + value32 = txsc20 | (txsc40 << 4); //TXSC_80M; + break; + case CHANNEL_WIDTH_40: + value8 = value8 | BIT(0); + value32 = txsc20; //TXSC_40M; + break; + case CHANNEL_WIDTH_20: + value32 = 0; //TXSC_20M; + break; + default: + break; + } + + if (cfg->pri_ch >= CHANNEL_5G) + chk_val8 |= B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; + + if (cfg->band) {//BAND1 + MAC_REG_W8(R_AX_WMAC_RFMOD_C1, value8); + MAC_REG_W8(R_AX_TXRATE_CHK_C1, chk_val8); + MAC_REG_W32(R_AX_TX_SUB_CARRIER_VALUE_C1, value32); + } else { + MAC_REG_W8(R_AX_WMAC_RFMOD, value8); + MAC_REG_W8(R_AX_TXRATE_CHK, chk_val8); + MAC_REG_W32(R_AX_TX_SUB_CARRIER_VALUE, value32); + } + + return MACSUCCESS; +} + +u32 mac_write_lte(struct mac_ax_adapter *adapter, + const u32 offset, u32 val) +{ + u32 cnt; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + +#if MAC_AX_FW_REG_OFLD + u32 ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + cnt = 1000; + while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte not ready(W)\n"); + return MACPOLLTO; + } + cnt--; + PLTFM_DELAY_US(50); + } + + PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock); + + MAC_REG_W32(R_AX_LTE_WDATA, val); + MAC_REG_W32(R_AX_LTE_CTRL, 0xC00F0000 | offset); + + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock); + + } else { + ret = MAC_REG_P_OFLD(R_AX_LTE_CTRL, B_AX_LTE_RDY, 1, 0); + if (ret != MACSUCCESS) + return ret; + + ret = MAC_REG_W32_OFLD(R_AX_LTE_WDATA, val, 0); + if (ret != MACSUCCESS) + return ret; + + ret = MAC_REG_W32_OFLD(R_AX_LTE_WDATA, 0xC00F0000 | offset, 1); + if (ret != MACSUCCESS) + return ret; + } +#else + cnt = 1000; + while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte not ready(W)\n"); + return MACPOLLTO; + } + cnt--; + PLTFM_DELAY_US(50); + } + + PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock); + + MAC_REG_W32(R_AX_LTE_WDATA, val); + MAC_REG_W32(R_AX_LTE_CTRL, 0xC00F0000 | offset); + + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock); +#endif + return MACSUCCESS; +} + +u32 mac_read_lte(struct mac_ax_adapter *adapter, + const u32 offset, u32 *val) +{ + u32 cnt; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cnt = 1000; + while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte not ready(W)\n"); + break; + } + cnt--; + PLTFM_DELAY_US(50); + } + + PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock); + + MAC_REG_W32(R_AX_LTE_CTRL, 0x800F0000 | offset); + *val = MAC_REG_R32(R_AX_LTE_RDATA); + + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock); + + return MACSUCCESS; +} + +u32 mac_write_xtal_si(struct mac_ax_adapter *adapter, + u8 offset, u8 val, u8 bitmask) +{ + u32 cnt = 0; + u32 write_val = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cnt = XTAL_SI_POLLING_CNT; + write_val = SET_CLR_WORD(write_val, offset, B_AX_WL_XTAL_SI_ADDR); + write_val = SET_CLR_WORD(write_val, val, B_AX_WL_XTAL_SI_DATA); + write_val = SET_CLR_WORD(write_val, bitmask, B_AX_WL_XTAL_SI_BITMASK); + write_val = SET_CLR_WORD(write_val, XTAL_SI_NORMAL_WRITE, + B_AX_WL_XTAL_SI_MODE); + write_val = (write_val | B_AX_WL_XTAL_SI_CMD_POLL); + MAC_REG_W32(R_AX_WLAN_XTAL_SI_CTRL, write_val); + + while ((MAC_REG_R32(R_AX_WLAN_XTAL_SI_CTRL) & B_AX_WL_XTAL_SI_CMD_POLL) + == B_AX_WL_XTAL_SI_CMD_POLL) { + if (!cnt) { + PLTFM_MSG_ERR("[ERR]xtal si not ready(W)\n"); + return MACPOLLTO; + } + cnt--; + PLTFM_DELAY_US(XTAL_SI_POLLING_DLY_US); + } + + return MACSUCCESS; +} + +u32 mac_read_xtal_si(struct mac_ax_adapter *adapter, + u8 offset, u8 *val) +{ + u32 cnt = 0; + u32 write_val = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cnt = XTAL_SI_POLLING_CNT; + write_val = SET_CLR_WORD(write_val, offset, B_AX_WL_XTAL_SI_ADDR); + write_val = SET_CLR_WORD(write_val, 0x00, B_AX_WL_XTAL_SI_DATA); + write_val = SET_CLR_WORD(write_val, 0x00, B_AX_WL_XTAL_SI_BITMASK); + write_val = SET_CLR_WORD(write_val, XTAL_SI_NORMAL_READ, + B_AX_WL_XTAL_SI_MODE); + write_val = (write_val | B_AX_WL_XTAL_SI_CMD_POLL); + MAC_REG_W32(R_AX_WLAN_XTAL_SI_CTRL, write_val); + + while ((MAC_REG_R32(R_AX_WLAN_XTAL_SI_CTRL) & B_AX_WL_XTAL_SI_CMD_POLL) + == B_AX_WL_XTAL_SI_CMD_POLL) { + if (!cnt) { + PLTFM_MSG_ERR("[ERR]xtal_si not ready(R)\n"); + return MACPOLLTO; + } + cnt--; + PLTFM_DELAY_US(XTAL_SI_POLLING_DLY_US); + } + + *val = MAC_REG_R8(R_AX_WLAN_XTAL_SI_CTRL + 1); + + return MACSUCCESS; +} + +u32 set_host_rpr(struct mac_ax_adapter *adapter, + struct mac_ax_host_rpr_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_host_rpr_cfg *def_cfg; + enum mac_ax_host_rpr_mode mode; + u8 is_poh; + u32 val32, nval32; + u32 ret = MACSUCCESS; + + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + ret = is_qta_poh(adapter, adapter->dle_info.qta_mode, &is_poh); + if (ret) { + PLTFM_MSG_ERR("is qta poh check fail %d\n", ret); + return ret; + } + def_cfg = is_poh ? &rpr_cfg_poh : &rpr_cfg_stf; + mode = is_poh ? MAC_AX_RPR_MODE_POH : MAC_AX_RPR_MODE_STF; + } else { + def_cfg = &rpr_cfg_stf; + mode = MAC_AX_RPR_MODE_STF; + } + + val32 = MAC_REG_R32(R_AX_WDRLS_CFG); + nval32 = SET_CLR_WORD(val32, mode, B_AX_WDRLS_MODE); + if (nval32 != val32) + MAC_REG_W32(R_AX_WDRLS_CFG, nval32); + + val32 = MAC_REG_R32(R_AX_RLSRPT0_CFG0); + nval32 = val32; + if ((cfg->txok_en == MAC_AX_FUNC_DEF && + def_cfg->txok_en == MAC_AX_FUNC_EN) || + cfg->txok_en == MAC_AX_FUNC_EN) + nval32 |= B_WDRLS_FLTR_TXOK; + else + nval32 &= ~B_WDRLS_FLTR_TXOK; + if ((cfg->rty_lmt_en == MAC_AX_FUNC_DEF && + def_cfg->rty_lmt_en == MAC_AX_FUNC_EN) || + cfg->rty_lmt_en == MAC_AX_FUNC_EN) + nval32 |= B_WDRLS_FLTR_RTYLMT; + else + nval32 &= ~B_WDRLS_FLTR_RTYLMT; + if ((cfg->lft_drop_en == MAC_AX_FUNC_DEF && + def_cfg->lft_drop_en == MAC_AX_FUNC_EN) || + cfg->lft_drop_en == MAC_AX_FUNC_EN) + nval32 |= B_WDRLS_FLTR_LIFTIM; + else + nval32 &= ~B_WDRLS_FLTR_LIFTIM; + if ((cfg->macid_drop_en == MAC_AX_FUNC_DEF && + def_cfg->macid_drop_en == MAC_AX_FUNC_EN) || + cfg->macid_drop_en == MAC_AX_FUNC_EN) + nval32 |= B_WDRLS_FLTR_MACID; + else + nval32 &= ~B_WDRLS_FLTR_MACID; + if (nval32 != val32) + MAC_REG_W32(R_AX_RLSRPT0_CFG0, nval32); + + val32 = MAC_REG_R32(R_AX_RLSRPT0_CFG1); + nval32 = SET_CLR_WORD(val32, (cfg->agg_def ? def_cfg->agg : cfg->agg), + B_AX_RLSRPT0_AGGNUM); + nval32 = SET_CLR_WORD(nval32, (cfg->tmr_def ? def_cfg->tmr : cfg->tmr), + B_AX_RLSRPT0_TO); + if (nval32 != val32) + MAC_REG_W32(R_AX_RLSRPT0_CFG1, nval32); + + return ret; +} + +u32 set_l2_status(struct mac_ax_adapter *adapter) +{ + adapter->sm.l2_st = MAC_AX_L2_EN; + + return MACSUCCESS; +} + +u32 mac_write_pwr_ofst_mode(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu) +{ +#if MAC_AX_FW_REG_OFLD + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_OFST_CTRL : + R_AX_PWR_RATE_OFST_CTRL_C1; + u32 val32 = 0; + u32 ret; + s8 *tmp = &tpu->pwr_ofst_mode[0]; + + val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]); + ret = MAC_REG_W_OFLD(cr, 0xFFFFF, val32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } +#else + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_OFST_CTRL : + R_AX_PWR_RATE_OFST_CTRL_C1; + u32 val32 = 0; + s8 *tmp = &tpu->pwr_ofst_mode[0]; + + val32 = MAC_REG_R32(cr) & ~0xFFFFF; + val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]); + MAC_REG_W32(cr, val32); +#endif + + return MACSUCCESS; +} + +u32 mac_write_pwr_ofst_bw(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu) +{ +#if MAC_AX_FW_REG_OFLD + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL : + R_AX_PWR_LMT_CTRL_C1; + u32 val32 = 0; + u32 ret; + s8 *tmp = &tpu->pwr_ofst_bw[0]; + + val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]); + ret = MAC_REG_W_OFLD(cr, 0xFFFFF, val32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } +#else + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL : + R_AX_PWR_LMT_CTRL_C1; + u32 val32 = 0; + s8 *tmp = &tpu->pwr_ofst_bw[0]; + + val32 = MAC_REG_R32(cr) & ~0xFFFFF; + val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]); + MAC_REG_W32(cr, val32); +#endif + + return MACSUCCESS; +} + +u32 mac_write_pwr_ref_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu) +{ +#if MAC_AX_FW_REG_OFLD + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL : + R_AX_PWR_RATE_CTRL_C1; + u32 val32 = 0; + u32 ret; + + val32 |= (((tpu->ref_pow_ofdm & 0x1ff) << 9) | + ((tpu->ref_pow_cck & 0x1ff))); + ret = MAC_REG_W_OFLD(cr, 0xFFFFC00, val32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } +#else + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL : + R_AX_PWR_RATE_CTRL_C1; + u32 val32 = 0; + + val32 = MAC_REG_R32(cr) & ~0xFFFFC00; + val32 |= (((tpu->ref_pow_ofdm & 0x1ff) << 19) | + ((tpu->ref_pow_cck & 0x1ff) << 10)); + MAC_REG_W32(cr, val32); +#endif + + return MACSUCCESS; +} + +u32 mac_write_pwr_limit_en(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu) +{ +#if MAC_AX_FW_REG_OFLD + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL : + R_AX_PWR_LMT_CTRL_C1; + u32 val32 = 0; + u32 ret; + + if (tpu->pwr_lmt_en) + val32 = 3; + ret = MAC_REG_W_OFLD(cr, 0x300000, val32, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } + + val32 = 0; + cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_CTRL : R_AX_PWR_RU_LMT_CTRL_C1; + if (tpu->pwr_lmt_en) + val32 = 1; + ret = MAC_REG_W_OFLD(cr, 0x40000, val32, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: config fail\n", __func__); + return ret; + } +#else + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL : + R_AX_PWR_LMT_CTRL_C1; + u32 val32 = 0; + + val32 = MAC_REG_R32(cr) & ~0x300000; + if (tpu->pwr_lmt_en) + val32 |= 0x300000; + MAC_REG_W32(cr, val32); + + cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_CTRL : R_AX_PWR_RU_LMT_CTRL_C1; + val32 = MAC_REG_R32(cr) & ~BIT18; + if (tpu->pwr_lmt_en) + val32 |= BIT18; + MAC_REG_W32(cr, val32); +#endif + + return MACSUCCESS; +} + +u32 mac_read_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + u32 access_offset = offset; + + if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) { + PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset); + return MACBADDR; + } + + if (band == MAC_AX_BAND_1) + access_offset = offset | BIT13; + + ret = mac_check_access(adapter, access_offset); + if (ret) + return ret; + + *val = MAC_REG_R32(access_offset); + + return MACSUCCESS; +} + +u32 mac_write_msk_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 mask, u32 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + u32 access_offset = offset; + u32 ori_val = 0; + u8 shift; + + if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) { + PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset); + return MACBADDR; + } + + if (band == MAC_AX_BAND_1) + access_offset = offset | BIT13; + + ret = mac_check_access(adapter, access_offset); + if (ret) { + PLTFM_MSG_ERR("[ERR]check access in %x\n", access_offset); + return ret; + } + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)access_offset, mask, val, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, + access_offset); + return ret; + } + + return MACSUCCESS; + } +#endif + + if (mask != 0xffffffff) { + shift = shift_mask(mask); + ori_val = MAC_REG_R32(offset); + val = ((ori_val) & (~mask)) | (((val << shift)) & mask); + } + MAC_REG_W32(offset, val); + + return MACSUCCESS; +} + +u32 mac_write_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + u32 access_offset = offset; + + if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) { + PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset); + return MACBADDR; + } + + if (band == MAC_AX_BAND_1) + access_offset = offset | BIT13; + + ret = mac_check_access(adapter, access_offset); + if (ret) + return ret; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W32_OFLD((u16)access_offset, val, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, + access_offset); + return ret; + } + + return MACSUCCESS; + } +#endif + + MAC_REG_W32(access_offset, val); + + return MACSUCCESS; +} + +u32 mac_write_pwr_limit_rua_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u16 cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_TABLE0 : + R_AX_PWR_RU_LMT_TABLE0_C1; + s8 *tmp; + u8 i, j; +#if MAC_AX_FW_REG_OFLD + u32 ret; +#endif + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + for (i = 0; i < HAL_MAX_PATH; i++) { + for (j = 0; j < TPU_SIZE_RUA; j++) { + tmp = &tpu->pwr_lmt_ru[i][j][0]; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2], + tmp[1], tmp[0]), + 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + cr += 4; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[7], tmp[6], + tmp[5], tmp[4]), + 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + cr += 4; + } + } + + return MACSUCCESS; + } +#endif + + for (i = 0; i < HAL_MAX_PATH; i++) { + for (j = 0; j < TPU_SIZE_RUA; j++) { + tmp = &tpu->pwr_lmt_ru[i][j][0]; + MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], tmp[0])); + cr += 4; + MAC_REG_W32(cr, BT_2_DW(tmp[7], tmp[6], tmp[5], tmp[4])); + cr += 4; + } + } + + return MACSUCCESS; +} + +u32 mac_write_pwr_limit_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_pwr_imt_info *tpu) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 base = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL : + R_AX_PWR_RATE_CTRL_C1; + u32 ss_ofst = 0; + u16 cr = 0; + s8 *tmp, *tmp_1; + u8 i, j; +#if MAC_AX_FW_REG_OFLD + u32 ret; +#endif + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + for (i = 0; i < HAL_MAX_PATH; i++) { + tmp = &tpu->pwr_lmt_cck_20m[i][0]; + tmp_1 = &tpu->pwr_lmt_cck_40m[i][0]; + cr = (base | PWR_LMT_CCK_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + tmp = &tpu->pwr_lmt_lgcy_20m[i][0]; + tmp_1 = &tpu->pwr_lmt_20m[i][0][0]; + cr = (base | PWR_LMT_LGCY_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + cr = (base | PWR_LMT_TBL2_OFFSET) + ss_ofst; + for (j = 1; j <= 5; j += 2) { + tmp = &tpu->pwr_lmt_20m[i][j][0]; + tmp_1 = &tpu->pwr_lmt_20m[i][j + 1][0]; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + cr += 4; + } + + tmp = &tpu->pwr_lmt_20m[i][7][0]; + tmp_1 = &tpu->pwr_lmt_40m[i][0][0]; + cr = (base | PWR_LMT_TBL5_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + tmp = &tpu->pwr_lmt_40m[i][1][0]; + tmp_1 = &tpu->pwr_lmt_40m[i][2][0]; + cr = (base | PWR_LMT_TBL6_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + tmp = &tpu->pwr_lmt_40m[i][3][0]; + tmp_1 = &tpu->pwr_lmt_80m[i][0][0]; + cr = (base | PWR_LMT_TBL7_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + tmp = &tpu->pwr_lmt_80m[i][1][0]; + tmp_1 = &tpu->pwr_lmt_160m[i][0]; + cr = (base | PWR_LMT_TBL8_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + tmp = &tpu->pwr_lmt_40m_0p5[i][0]; + tmp_1 = &tpu->pwr_lmt_40m_2p5[i][0]; + cr = (base | PWR_LMT_TBL9_OFFSET) + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0], + tmp[1], tmp[0]), 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + + ss_ofst += PWR_LMT_TBL_UNIT; + } + + return MACSUCCESS; + } +#endif + + for (i = 0; i < HAL_MAX_PATH; i++) { + tmp = &tpu->pwr_lmt_cck_20m[i][0]; + tmp_1 = &tpu->pwr_lmt_cck_40m[i][0]; + cr = (base | PWR_LMT_CCK_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + tmp = &tpu->pwr_lmt_lgcy_20m[i][0]; + tmp_1 = &tpu->pwr_lmt_20m[i][0][0]; + cr = (base | PWR_LMT_LGCY_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + cr = (base | PWR_LMT_TBL2_OFFSET) + ss_ofst; + for (j = 1; j <= 5; j += 2) { + tmp = &tpu->pwr_lmt_20m[i][j][0]; + tmp_1 = &tpu->pwr_lmt_20m[i][j + 1][0]; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], + tmp[0])); + cr += 4; + } + + tmp = &tpu->pwr_lmt_20m[i][7][0]; + tmp_1 = &tpu->pwr_lmt_40m[i][0][0]; + cr = (base | PWR_LMT_TBL5_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + tmp = &tpu->pwr_lmt_40m[i][1][0]; + tmp_1 = &tpu->pwr_lmt_40m[i][2][0]; + cr = (base | PWR_LMT_TBL6_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + tmp = &tpu->pwr_lmt_40m[i][3][0]; + tmp_1 = &tpu->pwr_lmt_80m[i][0][0]; + cr = (base | PWR_LMT_TBL7_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + tmp = &tpu->pwr_lmt_80m[i][1][0]; + tmp_1 = &tpu->pwr_lmt_160m[i][0]; + cr = (base | PWR_LMT_TBL8_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + tmp = &tpu->pwr_lmt_40m_0p5[i][0]; + tmp_1 = &tpu->pwr_lmt_40m_2p5[i][0]; + cr = (base | PWR_LMT_TBL9_OFFSET) + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0])); + + ss_ofst += PWR_LMT_TBL_UNIT; + } + + return MACSUCCESS; +} + +u32 mac_write_pwr_by_rate_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_pwr_by_rate_info *tpu) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 base = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL : + R_AX_PWR_RATE_CTRL_C1; + u32 ss_ofst = 0; + u16 cr = 0; + s8 *tmp; + u8 i, j; +#if MAC_AX_FW_REG_OFLD + u32 ret; +#endif + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + for (i = 0; i <= 8; i += 4) { + tmp = &tpu->pwr_by_rate_lgcy[i]; + cr = (base | PWR_BY_RATE_LGCY_OFFSET) + i; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2], + tmp[1], tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + } + + for (i = 0; i < HAL_MAX_PATH; i++) { + for (j = 0; j <= 12; j += 4) { + tmp = &tpu->pwr_by_rate[i][j]; + cr = (base | PWR_BY_RATE_OFFSET) + j + ss_ofst; + ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], + tmp[0]), 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + } + ss_ofst += 0x10; /*16*/ + } + + return MACSUCCESS; + } +#endif + + for (i = 0; i <= 8; i += 4) { + tmp = &tpu->pwr_by_rate_lgcy[i]; + cr = (base | PWR_BY_RATE_LGCY_OFFSET) + i; + MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], tmp[0])); + } + + for (i = 0; i < HAL_MAX_PATH; i++) { + for (j = 0; j <= 12; j += 4) { + tmp = &tpu->pwr_by_rate[i][j]; + cr = (base | PWR_BY_RATE_OFFSET) + j + ss_ofst; + MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], + tmp[0])); + } + ss_ofst += 0x10; /*16*/ + } + + return MACSUCCESS; +} + +u32 mac_read_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (sc_xo) { + *val = (MAC_REG_R32(R_AX_XTAL_ON_CTRL0) >> B_AX_XTAL_SC_XO_SH) & + B_AX_XTAL_SC_XO_MSK; + } else { + *val = (MAC_REG_R32(R_AX_XTAL_ON_CTRL0) >> B_AX_XTAL_SC_XI_SH) & + B_AX_XTAL_SC_XI_MSK; + } + + return MACSUCCESS; +} + +u32 mac_write_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + if (sc_xo) { + val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0); + val32 &= ~(0xFE0000); + val32 |= ((val & B_AX_XTAL_SC_XO_MSK) << B_AX_XTAL_SC_XO_SH); + MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32); + } else { + val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0); + val32 &= ~(0x1FC00); + val32 = val32 | ((val & B_AX_XTAL_SC_XI_MSK) << + B_AX_XTAL_SC_XI_SH); + MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32); + } + + return MACSUCCESS; +} + +u32 mac_read_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val) +{ + u8 xtal_si_value; + u32 ret; + + if (sc_xo) { + ret = mac_read_xtal_si(adapter, XTAL_SI_XTAL_SC_XO, &xtal_si_value); + + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + *val = xtal_si_value; + } else { + ret = mac_read_xtal_si(adapter, XTAL_SI_XTAL_SC_XI, &xtal_si_value); + + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + *val = xtal_si_value; + } + + return MACSUCCESS; +} + +u32 mac_write_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val) +{ + u8 xtal_si_value; + u32 ret; + + xtal_si_value = (u8)val; + + if (sc_xo) { + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_SC_XO, xtal_si_value, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_SC_XI, xtal_si_value, + FULL_BIT_MASK); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + return MACSUCCESS; +} + +u32 mac_write_bbrst_reg(struct mac_ax_adapter *adapter, u8 val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + + val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + if (val) + MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 | B_AX_FEN_BBRSTB); + else + MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & (~B_AX_FEN_BBRSTB)); + + return MACSUCCESS; +} + +static inline u32 _get_addr_range(struct mac_ax_adapter *adapter, u32 addr) +{ + u32 addr_idx; + +#define IOCHKRANG(chip) do { \ + if (ADDR_IS_AON_##chip(addr)) \ + addr_idx = ADDR_AON; \ + else if (ADDR_IS_HCI_##chip(addr)) \ + addr_idx = ADDR_HCI; \ + else if (ADDR_IS_DMAC_##chip(addr)) \ + addr_idx = ADDR_DMAC; \ + else if (ADDR_IS_CMAC0_##chip(addr)) \ + addr_idx = ADDR_CMAC0; \ + else if (ADDR_IS_CMAC1_##chip(addr)) \ + addr_idx = ADDR_CMAC1; \ + else if (ADDR_IS_BB0_##chip(addr)) \ + addr_idx = ADDR_BB0; \ + else if (ADDR_IS_BB1_##chip(addr)) \ + addr_idx = ADDR_BB1; \ + else if (ADDR_IS_RF_##chip(addr)) \ + addr_idx = ADDR_RF; \ + else if (ADDR_IS_IND_ACES_##chip(addr)) \ + addr_idx = ADDR_IND_ACES; \ + else if (ADDR_IS_RSVD_##chip(addr)) \ + addr_idx = ADDR_RSVD; \ + else if (ADDR_IS_PON_##chip(addr)) \ + addr_idx = ADDR_PON; \ + else \ + addr_idx = ADDR_INVALID; \ + } while (0) + + switch (adapter->hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + IOCHKRANG(8852A); + break; + case MAC_AX_CHIP_ID_8852B: + IOCHKRANG(8852B); + break; + case MAC_AX_CHIP_ID_8852C: + IOCHKRANG(8852C); + break; + case MAC_AX_CHIP_ID_8192XB: + IOCHKRANG(8192XB); + break; + default: + addr_idx = ADDR_INVALID; + break; + } + +#undef IOCHKRANG + return addr_idx; +} + +u32 mac_io_chk_access(struct mac_ax_adapter *adapter, u32 offset) +{ + switch (_get_addr_range(adapter, offset)) { + case ADDR_AON: + case ADDR_HCI: + return MACSUCCESS; + case ADDR_PON: + break; + case ADDR_DMAC: + if (adapter->sm.dmac_func != MAC_AX_FUNC_ON) + return MACIOERRDMAC; + break; + case ADDR_CMAC0: + if (adapter->sm.cmac0_func != MAC_AX_FUNC_ON) + return MACIOERRCMAC0; + break; + case ADDR_CMAC1: + if (adapter->sm.cmac1_func != MAC_AX_FUNC_ON) + return MACIOERRCMAC1; + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + return MACHWNOSUP; + break; + case ADDR_BB0: +#if CHK_BBRF_IO + if (adapter->sm.bb0_func != MAC_AX_FUNC_ON) + return MACIOERRBB0; +#endif + break; + case ADDR_BB1: +#if CHK_BBRF_IO + if (adapter->sm.bb1_func != MAC_AX_FUNC_ON) + return MACIOERRBB1; +#endif + break; + case ADDR_RF: +#if CHK_BBRF_IO + if (adapter->sm.bb0_func != MAC_AX_FUNC_ON && + adapter->sm.bb1_func != MAC_AX_FUNC_ON) + return MACIOERRRF; +#endif + break; + case ADDR_IND_ACES: + if (adapter->hw_info->ind_aces_cnt > 1) + PLTFM_MSG_ERR("[ERR]ind aces cnt %d ovf\n", + adapter->hw_info->ind_aces_cnt); + if (adapter->hw_info->ind_aces_cnt != 1) + return MACIOERRIND; + break; + case ADDR_RSVD: + return MACIOERRRSVD; + case ADDR_INVALID: + return MACHWNOSUP; + } + + if (adapter->sm.pwr != MAC_AX_PWR_ON) + return MACIOERRPWR; + + if (adapter->sm.plat != MAC_AX_PLAT_ON) + return MACIOERRPLAT; + + if (adapter->sm.io_st == MAC_AX_IO_ST_HANG) + return MACIOERRISH; + + if ((adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE || + adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) && + ADDR_NOT_ALLOW_SERL1(offset)) + return MACIOERRSERL1; + + if (adapter->sm.fw_rst == MAC_AX_FW_RESET_IDLE && + adapter->mac_pwr_info.pwr_in_lps && ADDR_NOT_ALLOW_LPS(offset)) + return MACIOERRLPS; + + return MACSUCCESS; +} + +u32 mac_watchdog(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + + ret = ops->pcie_autok_counter_avg(adapter); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/hw.h b/phl/hal_g6/mac/mac_ax/hw.h new file mode 100644 index 0000000..7f2d85b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hw.h @@ -0,0 +1,1169 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_HW_H_ +#define _MAC_AX_HW_H_ + +#define BT_2_DW(B3, B2, B1, B0) \ + (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) + +#define NIB_2_DW(B7, B6, B5, B4, B3, B2, B1, B0) \ + ((((B7) & 0xf) << 28) | (((B6) & 0xf) << 24) | \ + (((B5) & 0xf) << 20) | (((B4) & 0xf) << 16) | \ + (((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) | \ + (((B1) & 0xf) << 4) | ((B0) & 0xf)) + +#include "../type.h" +#include "status.h" +#include "wowlan.h" +#include "tblupd.h" +#include "ser.h" + +#if MAC_AX_SDIO_SUPPORT +#include "_sdio.h" +#endif + +#if MAC_AX_PCIE_SUPPORT +#include "_pcie.h" +#endif + +#if MAC_AX_USB_SUPPORT +#if MAC_AX_8852A_SUPPORT +#include "mac_8852a/_usb_8852a.h" +#endif +#if MAC_AX_8852B_SUPPORT +#include "mac_8852b/_usb_8852b.h" +#endif +#if MAC_AX_8852C_SUPPORT +#include "mac_8852c/_usb_8852c.h" +#endif +#endif +/*--------------------Define -------------------------------------------*/ + +#define BITS_WLRF_CTRL 0x82 +#define BITS_WLRF1_CTRL 0x8200 +#define PHYREG_SET_ALL_CYCLE 0xC +#define PHYREG_SET_XYN_CYCLE 0xE +#define PHYREG_SET_X_CYCLE 0x4 +#define PHYREG_SET_N_CYCLE 0x2 +#define PHYREG_SET_Y_CYCLE 0x1 + +#define TXSC_80M 0x91 +#define TXSC_40M 0x1 +#define TXSC_20M 0x0 + +#define TBL_READ_OP 0x0 +#define TBL_WRITE_OP 0x1 +#define TXCNT_LMT_MSK 0x1 + +#define CHANNEL_5G 34 + +#define CR_TXCNT_MSK 0x7FFFFFFF + +/*For XTAL_SI */ +#define XTAL_SI_POLLING_CNT 1000 +#define XTAL_SI_POLLING_DLY_US 50 +#define XTAL_SI_NORMAL_WRITE 0x00 +#define XTAL_SI_NORMAL_READ 0x01 +#define XTAL_SI_XTAL_SC_XI 0x04 +#define XTAL_SI_XTAL_SC_XO 0x05 +#define XTAL_SI_XTAL_XMD_2 0x24 +#define XTAL_SI_XTAL_XMD_4 0x26 +#define XTAL_SI_CV 0x41 +#define XTAL_SI_WL_RFC_S0 0x80 +#define XTAL_SI_WL_RFC_S1 0x81 +#define XTAL_SI_ANAPAR_WL 0x90 +#define XTAL_SI_SRAM_CTRL 0xA1 +#define FULL_BIT_MASK 0xFF + +/* For TXPWR Usage*/ +#define PWR_BY_RATE_LGCY_OFFSET 0XC0 +#define PWR_BY_RATE_OFFSET 0XCC + +#define PWR_LMT_CCK_OFFSET 0XEC +#define PWR_LMT_LGCY_OFFSET 0XF0 +#define PWR_LMT_TBL2_OFFSET 0XF4 +#define PWR_LMT_TBL5_OFFSET 0X100 +#define PWR_LMT_TBL6_OFFSET 0X104 +#define PWR_LMT_TBL7_OFFSET 0X108 +#define PWR_LMT_TBL8_OFFSET 0X10C +#define PWR_LMT_TBL9_OFFSET 0X110 + +#define PWR_LMT_TBL_UNIT 0X28 +#define PWR_BY_RATE_TBL_UNIT 0XF + +#define POLL_SWR_VOLT_CNT 2 +#define POLL_SWR_VOLT_US 50 +#define CORE_SWR_VOLT_MAX 0xE +#define CORE_SWR_VOLT_MIN 0x8 + +/* For SS SRAM access*/ +#define SS_R_QUOTA_SETTING 0 +#define SS_W_QUOTA_SETTING 1 +#define SS_R_QUOTA 2 +#define SS_W_QUOTA 3 +#define SS_R_TX_LEN 5 +#define SS_R_DL_MURU_DIS 8 +#define SS_W_DL_MURU_DIS 9 +#define SS_R_UL_TBL 10 +#define SS_W_UL_TBL 11 +#define SS_R_BSR_LEN 12 +#define SS_W_BSR_LEN 13 + +#define SS_QUOTA_SETTING_MSK 0xF +#define SS_MACID_SH 8 + +/* WDRLS filter map */ +#define B_WDRLS_FLTR_TXOK BIT(24) +#define B_WDRLS_FLTR_RTYLMT BIT(25) +#define B_WDRLS_FLTR_LIFTIM BIT(26) +#define B_WDRLS_FLTR_MACID BIT(27) + +#define CHK_BBRF_IO 0 + +/*--------------------Define Enum---------------------------------------*/ + +/** + * @enum tx_tf_info + * + * @brief tx_tf_info + * + * @var tx_tf_info::USER_INFO0_SEL + * Please Place Description here. + * @var tx_tf_info::USER_INFO1_SEL + * Please Place Description here. + * @var tx_tf_info::USER_INFO2_SEL + * Please Place Description here. + * @var tx_tf_info::USER_INFO3_SEL + * Please Place Description here. + * @var tx_tf_info::COMMON_INFO_SEL + * Please Place Description here. + */ +enum tx_tf_info { + USER_INFO0_SEL = 0, + USER_INFO1_SEL = 1, + USER_INFO2_SEL = 2, + USER_INFO3_SEL = 3, + COMMON_INFO_SEL = 4, +}; + +enum addr_rang_idx { + ADDR_AON = 0, + ADDR_HCI, + ADDR_PON, + ADDR_DMAC, + ADDR_CMAC0, + ADDR_CMAC1, + ADDR_BB0, + ADDR_BB1, + ADDR_RF, + ADDR_IND_ACES, + ADDR_RSVD, + + /* keep last */ + ADDR_LAST, + ADDR_MAX = ADDR_LAST, + ADDR_INVALID = ADDR_LAST +}; + +/*--------------------Define MACRO--------------------------------------*/ +#define ADDR_IS_AON_8852A(addr) ((addr) <= 0x4FF ? 1 : 0) +#define ADDR_IS_AON_8852B(addr) ((addr) <= 0x4FF ? 1 : 0) +#define ADDR_IS_AON_8852C(addr) ((addr) <= 0x4FF ? 1 : 0) +#define ADDR_IS_AON_8192XB(addr) ((addr) <= 0x4FF ? 1 : 0) + +#define ADDR_IS_HCI_8852A(addr) \ + ((addr) >= 0x1000 && (addr) <= 0x1FFF ? 1 : 0) +#define ADDR_IS_HCI_8852B(addr) \ + ((addr) >= 0x1000 && (addr) <= 0x1FFF ? 1 : 0) +#define ADDR_IS_HCI_8852C(addr) \ + (((addr) >= 0x2000 && (addr) <= 0x63FF) || \ + ((addr) >= 0x7C00 && (addr) <= 0x7FFF) ? 1 : 0) +#define ADDR_IS_HCI_8192XB(addr) \ + (((addr) >= 0x2000 && (addr) <= 0x63FF) || \ + ((addr) >= 0x7C00 && (addr) <= 0x7FFF) ? 1 : 0) + +#define ADDR_IS_PON_8852A(addr) \ + (((addr) >= 0x400 && (addr) <= 0xFFF) || \ + ((addr) >= 0x8000 && (addr) <= 0x8407) || \ + ((addr) >= 0xC000 && (addr) <= 0xC007) || \ + ((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0) +#define ADDR_IS_PON_8852B(addr) \ + (((addr) >= 0x400 && (addr) <= 0xFFF) || \ + ((addr) >= 0x8000 && (addr) <= 0x8407) || \ + ((addr) >= 0xC000 && (addr) <= 0xC007) ? 1 : 0) +#define ADDR_IS_PON_8852C(addr) \ + (((addr) >= 0x400 && (addr) <= 0xFFF) || \ + ((addr) >= 0x7000 && (addr) <= 0x7BFF) || \ + ((addr) >= 0x8000 && (addr) <= 0x8407) || \ + ((addr) >= 0xC000 && (addr) <= 0xC007) || \ + ((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0) +#define ADDR_IS_PON_8192XB(addr) \ + (((addr) >= 0x400 && (addr) <= 0xFFF) || \ + ((addr) >= 0x7000 && (addr) <= 0x7BFF) || \ + ((addr) >= 0x8000 && (addr) <= 0x8407) || \ + ((addr) >= 0xC000 && (addr) <= 0xC007) || \ + ((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0) + +#define ADDR_IS_DMAC_8852A(addr) \ + ((addr) >= 0x8408 && (addr) <= 0xBFFF ? 1 : 0) +#define ADDR_IS_DMAC_8852B(addr) \ + ((addr) >= 0x8408 && (addr) <= 0xBFFF ? 1 : 0) +#define ADDR_IS_DMAC_8852C(addr) \ + (((addr) >= 0x1000 && (addr) <= 0x1FFF) || \ + ((addr) >= 0x8408 && (addr) <= 0xBFFF) ? 1 : 0) +#define ADDR_IS_DMAC_8192XB(addr) \ + (((addr) >= 0x1000 && (addr) <= 0x1FFF) || \ + ((addr) >= 0x8408 && (addr) <= 0xBFFF) ? 1 : 0) + +#define ADDR_IS_CMAC0_8852A(addr) \ + ((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0) +#define ADDR_IS_CMAC0_8852B(addr) \ + ((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0) +#define ADDR_IS_CMAC0_8852C(addr) \ + ((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0) +#define ADDR_IS_CMAC0_8192XB(addr) \ + ((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0) + +#define ADDR_IS_CMAC1_8852A(addr) \ + ((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0) +#define ADDR_IS_CMAC1_8852B(addr) \ + ((addr) >= 0xE008 && (addr) <= 0xFFFF ? 0 : 0) +#define ADDR_IS_CMAC1_8852C(addr) \ + ((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0) +#define ADDR_IS_CMAC1_8192XB(addr) \ + ((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0) + +#define ADDR_IS_BB0_8852A(addr) \ + (((addr) >= 0x10000 && (addr) <= 0x125FF) || \ + ((addr) >= 0x12E00 && (addr) <= 0x138FF) || \ + ((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \ + ((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0) +#define ADDR_IS_BB0_8852B(addr) \ + (((addr) >= 0x10000 && (addr) <= 0x125FF) || \ + ((addr) >= 0x12E00 && (addr) <= 0x138FF) || \ + ((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \ + ((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0) +#define ADDR_IS_BB0_8852C(addr) \ + (((addr) >= 0x10000 && (addr) <= 0x125FF) || \ + ((addr) >= 0x12E00 && (addr) <= 0x138FF) || \ + ((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \ + ((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0) +#define ADDR_IS_BB0_8192XB(addr) \ + (((addr) >= 0x10000 && (addr) <= 0x125FF) || \ + ((addr) >= 0x12E00 && (addr) <= 0x138FF) || \ + ((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \ + ((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0) + +#define ADDR_IS_BB1_8852A(addr) \ + (((addr) >= 0x12600 && (addr) <= 0x12DFF) || \ + ((addr) >= 0x13900 && (addr) <= 0x13BFF) || \ + ((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0) +#define ADDR_IS_BB1_8852B(addr) \ + (((addr) >= 0x12600 && (addr) <= 0x12DFF) || \ + ((addr) >= 0x13900 && (addr) <= 0x13BFF) || \ + ((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0) +#define ADDR_IS_BB1_8852C(addr) \ + (((addr) >= 0x12600 && (addr) <= 0x12DFF) || \ + ((addr) >= 0x13900 && (addr) <= 0x13BFF) || \ + ((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0) +#define ADDR_IS_BB1_8192XB(addr) \ + (((addr) >= 0x12600 && (addr) <= 0x12DFF) || \ + ((addr) >= 0x13900 && (addr) <= 0x13BFF) || \ + ((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0) + +#define ADDR_IS_RF_8852A(addr) \ + ((addr) >= 0x18000 && (addr) <= 0x1DFFF ? 1 : 0) +#define ADDR_IS_RF_8852B(addr) \ + ((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0) +#define ADDR_IS_RF_8852C(addr) \ + ((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0) +#define ADDR_IS_RF_8192XB(addr) \ + ((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0) + +#define ADDR_IS_IND_ACES_8852A(addr) \ + ((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0) +#define ADDR_IS_IND_ACES_8852B(addr) \ + ((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0) +#define ADDR_IS_IND_ACES_8852C(addr) \ + ((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0) +#define ADDR_IS_IND_ACES_8192XB(addr) \ + ((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0) + +#define ADDR_IS_RSVD_8852A(addr) \ + (((addr) >= 0x2000 && (addr) <= 0x7FFF) || \ + ((addr) >= 0x1E000 && (addr) <= 0x3FFFF) || \ + (addr) >= 0x80000 ? 1 : 0) +#define ADDR_IS_RSVD_8852B(addr) \ + (((addr) >= 0x2000 && (addr) <= 0x7FFF) || \ + ((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \ + (addr) >= 0x80000 ? 1 : 0) +#define ADDR_IS_RSVD_8852C(addr) \ + (((addr) >= 0x6400 && (addr) <= 0x6FFF) || \ + ((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \ + (addr) >= 0x80000 ? 1 : 0) +#define ADDR_IS_RSVD_8192XB(addr) \ + (((addr) >= 0x6400 && (addr) <= 0x6FFF) || \ + ((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \ + (addr) >= 0x80000 ? 1 : 0) + +#define ADDR_NOT_ALLOW_SERL1(addr) \ + ((addr) != R_AX_SER_DBG_INFO && (addr) != R_AX_HCI_FUNC_EN && \ + (addr) != R_AX_HD0IMR && (addr) != R_AX_HD0ISR ? 1 : 0) + +#define ADDR_NOT_ALLOW_LPS(addr) ((addr) != R_AX_CPWM ? 1 : 0) + +/*--------------------Define Struct-------------------------------------*/ + +/*--------------------Function declaration------------------------------*/ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ +/** + * @brief mac_get_hw_info + * + * @param *adapter + * @return Please Place Description here. + * @retval mac_ax_hw_info + */ +struct mac_ax_hw_info *mac_get_hw_info(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_set_hw_value + * + * @param *adapter + * @param hw_id + * @param *val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_hw_value(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_get_hw_value + * + * @param *adapter + * @param hw_id + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_hw_value(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup LTE_COEX + * @{ + */ + +/** + * @brief mac_write_lte + * + * @param *adapter + * @param offset + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_lte(struct mac_ax_adapter *adapter, + const u32 offset, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup LTE_COEX + * @{ + */ + +/** + * @brief mac_read_lte + * + * @param *adapter + * @param offset + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_lte(struct mac_ax_adapter *adapter, + const u32 offset, u32 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_xtal_si + * + * @param *adapter + * @param offset + * @param val + * @param bitmask + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_xtal_si(struct mac_ax_adapter *adapter, + u8 offset, u8 val, u8 bitmask); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_read_xtal_si + * + * @param *adapter + * @param offset + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_xtal_si(struct mac_ax_adapter *adapter, + u8 offset, u8 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief set_host_rpr + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_host_rpr(struct mac_ax_adapter *adapter, + struct mac_ax_host_rpr_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_read_pwr_reg + * + * @param *adapter + * @param band + * @param offset + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 set_l2_status(struct mac_ax_adapter *adapter); +u32 mac_read_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_reg + * + * @param *adapter + * @param band + * @param offset + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_msk_pwr_reg + * + * @param *adapter + * @param band + * @param offset + * @param mask + * @param val + * @return write tx power reg with mask value into fw + * @retval u32 + */ +u32 mac_write_msk_pwr_reg(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 mask, u32 val); + +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_ofst_mode + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_ofst_mode(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_ofst_bw + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_ofst_bw(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_ref_reg + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_ref_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_limit_en + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_limit_en(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_limit_rua_reg + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_limit_rua_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_limit_reg + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_limit_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_pwr_imt_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_pwr_by_rate_reg + * + * @param *adapter + * @param band + * @param *tpu + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_pwr_by_rate_reg(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_pwr_by_rate_info *tpu); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** * @brief mac_read_xcap_reg + * + * @param *adapter + * @param sc_xo + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_xcap_reg + * + * @param *adapter + * @param sc_xo + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_bbrst_reg + * + * @param *adapter + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_xcap_reg + * + * @param *adapter + * @param sc_xo + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_write_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_write_bbrst_reg + * + * @param *adapter + * @param val + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_write_bbrst_reg(struct mac_ax_adapter *adapter, u8 val); +/** + * @} + * @} + */ + +/** * @brief set_macid_pause + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief macid_pause + * + * @param *adapter + * @param *grp + * @return Please Place Description here. + * @retval u32 + */ +u32 macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_grp *grp); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief get_macid_pause + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 get_macid_pause(struct mac_ax_adapter *adapter, + struct mac_ax_macid_pause_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief get_ss_wmm_tbl + * + * @param *adapter + * @param *ctrl + * @return Please Place Description here. + * @retval u32 + */ +u32 get_ss_wmm_tbl(struct mac_ax_adapter *adapter, + struct mac_ax_ss_wmm_tbl_ctrl *ctrl); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief set_enable_bb_rf + * + * @param *adapter + * @param enable + * @return Please Place Description here. + * @retval u32 + */ +u32 set_enable_bb_rf(struct mac_ax_adapter *adapter, u8 enable); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief set_cctl_rty_limit + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_cctl_rty_limit(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_rty_lmt_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief cfg_mac_bw + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 cfg_mac_bw(struct mac_ax_adapter *adapter, + struct mac_ax_cfg_bw *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief get_ss_quota_mode + * + * @param *adapter + * @param *ctrl + * @return Please Place Description here. + * @retval u32 + */ +u32 get_ss_quota_mode(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_mode_ctrl *ctrl); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief set_ss_quota_mode + * + * @param *adapter + * @param *ctrl + * @return Please Place Description here. + * @retval u32 + */ +u32 set_ss_quota_mode(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_mode_ctrl *ctrl); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief ss_get_quotasetting + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 ss_get_quotasetting(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_setting *para); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief ss_set_quotasetting + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 ss_set_quotasetting(struct mac_ax_adapter *adapter, + struct mac_ax_ss_quota_setting *para); +/** + * @} + * @} + */ + +/** + * @brief scheduler_set_prebkf + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 scheduler_set_prebkf(struct mac_ax_adapter *adapter, + struct mac_ax_prebkf_setting *para); +/** + * @} + * @} + */ + +/** + * @brief set_bacam_mode + * + * @param *adapter + * @param mode_sel + * @return Set the R_AX_RESPBA_CAM_CTRL bit 4 to be 0 or 1 which decide the + * option mode in BA CAM. + * @retval u32 + */ +u32 set_bacam_mode(struct mac_ax_adapter *adapter, u8 mode_sel); +/** + * @} + * @} + */ + +/** + * @brief scheduler_set_prebkf + * + * @param *adapter + * @param *mode_sel + * @return Get the option mode from R_AX_RESPBA_CAM_CTRL bit 4 in the BA CAM. + * @retval u32 + */ +u32 get_bacam_mode(struct mac_ax_adapter *adapter, u8 *mode_sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup HW_Related + * @{ + */ + +/** + * @brief mac_io_chk_access + * + * @param *adapter + * @param offset + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_io_chk_access(struct mac_ax_adapter *adapter, u32 offset); +/** + * @} + * @} + */ + +/** + * @brief mac_watchdog + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_watchdog(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/hw_seq.c b/phl/hal_g6/mac/mac_ax/hw_seq.c new file mode 100644 index 0000000..900b0a5 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hw_seq.c @@ -0,0 +1,110 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "hw_seq.h" + +#if MAC_AX_FW_REG_OFLD +u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter, + u8 idx, + u16 val) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_set_hwseq_reg *content; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_set_hwseq_reg)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + content = (struct mac_ax_set_hwseq_reg *)buf; + + content->reg_idx = idx; + content->seq_val = val; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_SET_HWSEQ_REG, + 0, + 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif +fail: + h2cb_free(adapter, h2cb); + + return ret; +} +#else +u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter, + u8 idx, + u16 val) +{ + u32 reg_val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (idx) { + case R_AX_HW_SEQ_0: + reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); + reg_val &= ~((u32)B_AX_HW_SEQ0_MSK << B_AX_HW_SEQ0_SH); + reg_val |= (val << B_AX_HW_SEQ0_SH); + MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); + break; + case R_AX_HW_SEQ_1: + reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1); + reg_val &= ~((u32)B_AX_HW_SEQ1_MSK << B_AX_HW_SEQ1_SH); + reg_val |= (val << B_AX_HW_SEQ1_SH); + MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val); + break; + case R_AX_HW_SEQ_2: + reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3); + reg_val &= ~((u32)B_AX_HW_SEQ2_MSK << B_AX_HW_SEQ2_SH); + reg_val |= (val << B_AX_HW_SEQ2_SH); + MAC_REG_W32(R_AX_HW_SEQ_2_3, reg_val); + break; + case R_AX_HW_SEQ_3: + reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3); + reg_val &= ~((u32)B_AX_HW_SEQ3_MSK << B_AX_HW_SEQ3_SH); + reg_val |= (val << B_AX_HW_SEQ3_SH); + MAC_REG_W32(R_AX_HW_SEQ_2_3, reg_val); + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} +#endif diff --git a/phl/hal_g6/mac/mac_ax/hw_seq.h b/phl/hal_g6/mac/mac_ax/hw_seq.h new file mode 100644 index 0000000..1d63d4b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hw_seq.h @@ -0,0 +1,70 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_HW_SEQ_H_ +#define _MAC_AX_HW_SEQ_H_ + +#include "../type.h" +#include "fwcmd.h" + +enum { + R_AX_HW_SEQ_0 = 0, + R_AX_HW_SEQ_1 = 1, + R_AX_HW_SEQ_2 = 2, + R_AX_HW_SEQ_3 = 3, +}; + +/** + * @struct mac_ax_set_hwseq_reg + * @brief mac_ax_set_hwseq_reg + * + * @var mac_ax_set_hwseq_reg::reg_idx + * Please Place Description here. + * @var mac_ax_set_hwseq_reg::seq_val + * Please Place Description here. + * @var mac_ax_set_hwseq_reg::rsvd0 + * Please Place Description here. + */ +struct mac_ax_set_hwseq_reg { + u32 reg_idx: 2; + u32 seq_val: 12; + u32 rsvd0: 18; +}; + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ +/** + * @brief mac_set_hwseq_reg + * + * @param *adapter + * @param idx + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter, + u8 idx, + u16 val); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/hwamsdu.c b/phl/hal_g6/mac/mac_ax/hwamsdu.c new file mode 100644 index 0000000..ff4db4d --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hwamsdu.c @@ -0,0 +1,226 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "hwamsdu.h" + +#if MAC_AX_FW_REG_OFLD +u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter, + u8 enable, + u8 low_th, + u16 high_th, + enum mac_ax_ex_shift aligned) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_en_amsdu_cut *content; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) + return MACNOTSUP; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) + return MACNOTSUP; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_amsdu_cut)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + content = (struct mac_ax_en_amsdu_cut *)buf; + content->enable = enable; + content->low_th = low_th; + content->high_th = high_th; + content->aligned = aligned; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_AMSDU_CUT_REG, + 0, + 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter, + u8 enable, + enum mac_ax_amsdu_pkt_num max_num, + u8 en_single_amsdu, + u8 en_last_amsdu_padding) + +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_en_hwamsdu *content; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) + return MACNOTSUP; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) + return MACNOTSUP; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_hwamsdu)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + content = (struct mac_ax_en_hwamsdu *)buf; + content->enable = enable; + content->max_num = max_num; + content->en_single_amsdu = en_single_amsdu; + content->en_last_amsdu_padding = en_last_amsdu_padding; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_HWAMSDU_REG, + 0, + 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif +fail: + h2cb_free(adapter, h2cb); + + return ret; +} +#else +u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter, + u8 enable, + u8 low_th, + u16 high_th, + enum mac_ax_ex_shift aligned) +{ + //cut AMSDU + u32 val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) + return MACNOTSUP; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) + return MACNOTSUP; + } + + if (aligned > MAC_AX_BYTE_ALIGNED_8) + return MACNOITEM; + val = MAC_REG_R32(R_AX_CUT_AMSDU_CTRL); + val = SET_CLR_WORD(val, low_th, B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH); + val = (SET_CLR_WORD(val, high_th, B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH) | + B_AX_BIT_CUT_AMSDU_CHKLEN_EN | + B_AX_BIT_EN_CUT_AMSDU); + if (!enable) + val &= ~B_AX_BIT_EN_CUT_AMSDU; + + MAC_REG_W32(R_AX_CUT_AMSDU_CTRL, val); + + //extra shift + val = 0; + val = (SET_CLR_WORD(val, aligned, B_AX_EXTRA_SHIFT)); + MAC_REG_W32(R_AX_CUT_AMSDU_CTRL_2, val); + + return MACSUCCESS; +} + +u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter, + u8 enable, + enum mac_ax_amsdu_pkt_num max_num, + u8 en_single_amsdu, + u8 en_last_amsdu_padding) +{ + u32 val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) + return MACNOTSUP; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) + return MACNOTSUP; + } + + if (max_num >= MAC_AX_AMSDU_AGG_NUM_MAX) + return MACNOITEM; + + //HW AMSDU register + val = MAC_REG_R32(R_AX_HWAMSDU_CTRL); + val = (SET_CLR_WORD(val, max_num, B_AX_MAX_AMSDU_NUM) | + B_AX_HWAMSDU_EN); + if (!enable) + val &= ~B_AX_HWAMSDU_EN; + MAC_REG_W32(R_AX_HWAMSDU_CTRL, val); + + MAC_REG_W32(R_AX_HWAMSDU_CTRL, (MAC_REG_R32(R_AX_HWAMSDU_CTRL) & + (~B_AX_SINGLE_AMSDU)) | + (en_single_amsdu ? B_AX_SINGLE_AMSDU : 0)); + + MAC_REG_W32(R_AX_DMAC_TABLE_CTRL, (MAC_REG_R32(R_AX_DMAC_TABLE_CTRL) & + (~B_AX_HWAMSDU_PADDING_MODE)) | + (en_last_amsdu_padding ? B_AX_HWAMSDU_PADDING_MODE : 0)); + + return MACSUCCESS; +} +#endif diff --git a/phl/hal_g6/mac/mac_ax/hwamsdu.h b/phl/hal_g6/mac/mac_ax/hwamsdu.h new file mode 100644 index 0000000..12bbe8a --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/hwamsdu.h @@ -0,0 +1,128 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_HWAMSDU_H_ +#define _MAC_AX_HWAMSDU_H_ + +#include "../type.h" +#include "../mac_ax.h" + +#define MAX_LENGTH_ENUM 7 + +/** + * @struct mac_ax_en_amsdu_cut + * @brief mac_ax_en_amsdu_cut + * + * @var mac_ax_en_amsdu_cut::enable + * Please Place Description here. + * @var mac_ax_en_amsdu_cut::low_th + * Please Place Description here. + * @var mac_ax_en_amsdu_cut::high_th + * Please Place Description here. + * @var mac_ax_en_amsdu_cut::aligned + * Please Place Description here. + * @var mac_ax_en_amsdu_cut::rsvd0 + * Please Place Description here. + */ +struct mac_ax_en_amsdu_cut { + /* dword0 */ + u32 enable: 1; + u32 low_th: 8; + u32 high_th: 16; + u32 aligned: 2; + u32 rsvd0: 5; +}; + +/** + * @struct mac_ax_en_hwamsdu + * @brief mac_ax_en_hwamsdu + * + * @var mac_ax_en_hwamsdu::enable + * Please Place Description here. + * @var mac_ax_en_hwamsdu::max_num + * Please Place Description here. + * @var mac_ax_en_hwamsdu::en_single_amsdu + * Please Place Description here. + * @var mac_ax_en_hwamsdu::en_last_amsdu_padding + * Please Place Description here. + * @var mac_ax_en_hwamsdu::rsvd0 + * Please Place Description here. + */ +struct mac_ax_en_hwamsdu { + /* dword0 */ + u32 enable: 1; + u32 max_num: 2; + u32 en_single_amsdu:1; + u32 en_last_amsdu_padding:1; + u32 rsvd0: 27; +}; + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ + +/** + * @brief mac_enable_cut_hwamsdu + * + * @param *adapter + * @param enable + * @param low_th + * @param high_th + * @param aligned + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter, + u8 enable, + u8 low_th, + u16 high_th, + enum mac_ax_ex_shift aligned); +/** + * @} + * @} + */ +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ + +/** + * @brief mac_enable_hwmasdu + * + * @param *adapter + * @param enable + * @param max_num + * @param en_single_amsdu + * @param en_last_amsdu_padding + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter, + u8 enable, + enum mac_ax_amsdu_pkt_num max_num, + u8 en_single_amsdu, + u8 en_last_amsdu_padding); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/init.c b/phl/hal_g6/mac/mac_ax/init.c new file mode 100644 index 0000000..9619e47 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/init.c @@ -0,0 +1,867 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "init.h" +#include "security_cam.h" +#include "hw.h" +#if MAC_AX_PCIE_SUPPORT +#include "_pcie.h" +#endif + +static void _mp_core_swr_volt(struct mac_ax_adapter *adapter, u8 init) +{ + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + enum mac_ax_core_swr_volt v; + u8 val8; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + return; + + if (init) { + val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0); + adapter->hw_info->core_swr_volt = GET_FIELD(val8, B_AX_VOL_L1); + } else { + v = MAC_AX_SWR_NORM; + mac_ops->set_hw_value(adapter, MAC_AX_HW_SET_CORE_SWR_VOLT, &v); + } +} + +#if MAC_AX_PCIE_SUPPORT +static u32 _patch_pcie_pldr_polling_fail(struct mac_ax_adapter *adapter) +{ + u32 ret = MACSUCCESS; + + if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))) + return MACSUCCESS; + + ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS); + + ret = clr_idx_all_pcie(adapter); + if (ret) + return ret; + + ret = poll_dma_all_idle_pcie(adapter); + if (ret) + return ret; + + return ret; +} +#endif + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf, + u8 chip_id, u8 cv, + void *phl_adapter, void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb) +{ + struct mac_ax_adapter *adapter = NULL; + + switch (chip_id) { +#if MAC_AX_8852A_SUPPORT + case MAC_AX_CHIP_ID_8852A: + adapter = get_mac_8852a_adapter(intf, cv, phl_adapter, + drv_adapter, pltfm_cb); + break; +#endif + default: + return NULL; + } + + return adapter; +} +#else +struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf, + u8 chip_id, u8 cv, + void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb) +{ + struct mac_ax_adapter *adapter = NULL; + + switch (chip_id) { +#if MAC_AX_8852A_SUPPORT + case MAC_AX_CHIP_ID_8852A: + adapter = get_mac_8852a_adapter(intf, cv, drv_adapter, + pltfm_cb); + break; +#endif +#if MAC_AX_8852B_SUPPORT + case MAC_AX_CHIP_ID_8852B: + adapter = get_mac_8852b_adapter(intf, cv, drv_adapter, + pltfm_cb); + break; +#endif +#if MAC_AX_8852C_SUPPORT + case MAC_AX_CHIP_ID_8852C: + adapter = get_mac_8852c_adapter(intf, cv, drv_adapter, + pltfm_cb); + break; +#endif +#if MAC_AX_8192XB_SUPPORT + case MAC_AX_CHIP_ID_8192XB: + adapter = get_mac_8192xb_adapter(intf, cv, drv_adapter, + pltfm_cb); + break; +#endif + + default: + return NULL; + } + + return adapter; +} +#endif + +u32 hci_func_en(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret = MACSUCCESS; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN) | + B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; + MAC_REG_W32(R_AX_HCI_FUNC_EN, val32); + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN) | + B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; + MAC_REG_W32(R_AX_HCI_FUNC_EN, val32); + } else { + val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN_V1) | + B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; + MAC_REG_W32(R_AX_HCI_FUNC_EN_V1, val32); + } + return ret; +} + +u32 dmac_pre_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, u8 fwdl) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | + B_AX_DISPATCHER_EN | B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN); + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); + + adapter->sm.dmac_func = MAC_AX_FUNC_ON; + + val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1); + switch (adapter->hw_info->intf) { + case MAC_AX_INTF_USB: + val32 = SET_CLR_WORD(val32, DMA_MOD_USB, + B_AX_DMA_MODE); + break; + case MAC_AX_INTF_PCIE: + val32 = SET_CLR_WORD(val32, DMA_MOD_PCIE_1B, + B_AX_DMA_MODE); + break; + case MAC_AX_INTF_SDIO: + val32 = SET_CLR_WORD(val32, DMA_MOD_SDIO, + B_AX_DMA_MODE); + break; + default: + PLTFM_MSG_ERR("[ERR]DMAC init with not support intf: %X\n", + adapter->hw_info->intf); + return MACINTF; + } + val32 = (val32 & ~B_AX_STOP_AXI_MST) | B_AX_TXHCI_EN_V1 | + B_AX_RXHCI_EN_V1; + MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32); + + val32 = MAC_REG_R32(R_AX_HAXI_DMA_STOP1) & + ~(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | + B_AX_STOP_ACH3 | B_AX_STOP_ACH4 | + B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | + B_AX_STOP_ACH7 | B_AX_STOP_CH8 | + B_AX_STOP_CH9 | B_AX_STOP_CH12); + MAC_REG_W32(R_AX_HAXI_DMA_STOP1, val32); + + val32 = MAC_REG_R32(R_AX_HAXI_DMA_STOP2) & + ~(B_AX_STOP_CH10 | B_AX_STOP_CH11); + MAC_REG_W32(R_AX_HAXI_DMA_STOP2, val32); + + val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE) | B_AX_AXIDMA_EN; + MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32); + } else { + val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | + B_AX_DISPATCHER_EN | B_AX_PKT_BUF_EN); + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); + + adapter->sm.dmac_func = MAC_AX_FUNC_ON; + } + + val32 = (B_AX_DISPATCHER_CLK_EN); + MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); + + if (!fwdl) + return MACSUCCESS; + + ret = dle_init(adapter, MAC_AX_QTA_DLFW, mode); + if (ret) { + PLTFM_MSG_ERR("[ERR]DLE pre init %d\n", ret); + return ret; + } + + ret = hfc_init(adapter, 1, 0, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]HCI FC pre init %d\n", ret); + return ret; + } + + return ret; +} + +u32 dmac_func_en(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret = 0; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | + B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | + B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN | + B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | + B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); + } else { + val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | + B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | + B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN | + B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | + B_AX_DMAC_CRPRT); + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); + } + + val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | + B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | + B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | + B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); + MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); + + adapter->sm.dmac_func = MAC_AX_FUNC_ON; + + return ret; +} + +u32 cmac_func_en(struct mac_ax_adapter *adapter, u8 band, u8 en) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32_func_en = 0; + u32 val32_ck_en = 0; + u32 val32_c1pc_en = 0; + u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; + u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; + + val32_func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | + B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | + B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | + B_AX_CMAC_CRPRT; + val32_ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | + B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | + B_AX_RMAC_CKEN; + val32_c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | + B_AX_R_SYM_WLCMAC1_P1_PC_EN | + B_AX_R_SYM_WLCMAC1_P2_PC_EN | + B_AX_R_SYM_WLCMAC1_P3_PC_EN | + B_AX_R_SYM_WLCMAC1_P4_PC_EN; + + if (band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("band %d invalid\n", band); + return MACFUNCINPUT; + } + + if (en) { + if (band == MAC_AX_BAND_1) { + MAC_REG_W32(R_AX_AFE_CTRL1, + MAC_REG_R32(R_AX_AFE_CTRL1) | + val32_c1pc_en); + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) & + ~B_AX_R_SYM_ISO_CMAC12PP); + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) | + B_AX_CMAC1_FEN); + } + MAC_REG_W32(addrl_ck_en[band], + MAC_REG_R32(addrl_ck_en[band]) | val32_ck_en); + MAC_REG_W32(addrl_func_en[band], + MAC_REG_R32(addrl_func_en[band]) | val32_func_en); + } else { + MAC_REG_W32(addrl_func_en[band], + MAC_REG_R32(addrl_func_en[band]) & ~val32_func_en); + MAC_REG_W32(addrl_ck_en[band], + MAC_REG_R32(addrl_ck_en[band]) & ~val32_ck_en); + if (band == MAC_AX_BAND_1) { + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) & + ~B_AX_CMAC1_FEN); + MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND, + MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) | + B_AX_R_SYM_ISO_CMAC12PP); + MAC_REG_W32(R_AX_AFE_CTRL1, + MAC_REG_R32(R_AX_AFE_CTRL1) & + ~val32_c1pc_en); + } + } + + if (band == MAC_AX_BAND_0) + adapter->sm.cmac0_func = en ? MAC_AX_FUNC_ON : MAC_AX_FUNC_OFF; + else + adapter->sm.cmac1_func = en ? MAC_AX_FUNC_ON : MAC_AX_FUNC_OFF; + + return MACSUCCESS; +} + +u32 chip_func_en(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + u32 val32; + u32 ret = MACSUCCESS; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + /* patch for OCP */ + val32 = MAC_REG_R32(R_AX_SPSLDO_ON_CTRL0); + val32 |= SET_WOR2(B_AX_OCP_L1_MSK, B_AX_OCP_L1_SH, + B_AX_OCP_L1_MSK); + MAC_REG_W32(R_AX_SPSLDO_ON_CTRL0, val32); + } + + return ret; +} + +u32 mac_sys_init(struct mac_ax_adapter *adapter) +{ + u32 ret; + + ret = dmac_func_en(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]DMAC en %d\n", ret); + return ret; + } + + ret = cmac_func_en(adapter, MAC_AX_BAND_0, MAC_AX_FUNC_EN); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC %d en %d %d\n", + MAC_AX_BAND_0, MAC_AX_FUNC_EN, ret); + return ret; + } + + ret = chip_func_en(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]chip en %d\n", ret); + return ret; + } + + return ret; +} + +u32 mac_hal_init(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info) +{ + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hw_info *hw_info = adapter->hw_info; +#if MAC_AX_FEATURE_DBGPKG + struct mac_ax_dbgpkg dbg_val = {0}; + struct mac_ax_dbgpkg_en dbg_en = {0}; +#endif + u32 ret; + u32 rom_addr; + u8 fwdl_en; + + _mp_core_swr_volt(adapter, 1); + + ret = mac_ops->pwr_switch(adapter, 1); + if (ret == MACALRDYON) { + ret = mac_ops->pwr_switch(adapter, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 0 fail %d\n", ret); + goto end; + } + ret = mac_ops->pwr_switch(adapter, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 0->1 fail %d\n", ret); + goto end; + } + } + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 1 fail %d\n", ret); + goto end; + } +#if MAC_AX_PCIE_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + ret = _patch_pcie_pldr_polling_fail(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]_patch_pcie_pldr_polling_fail %d\n", ret); + goto end; + } + } +#endif + ret = hci_func_en(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]hci_func_en %d\n", ret); + goto end; + } + + fwdl_en = fwdl_info->fw_en && + (fwdl_info->dlrom_en || fwdl_info->dlram_en) ? 1 : 0; + ret = dmac_pre_init(adapter, trx_info->qta_mode, fwdl_en); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]fwdl_pre_init %d\n", ret); + goto end; + } + + ret = ops->intf_pre_init(adapter, intf_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]intf_pre_init %d\n", ret); + goto end; + } + + if (fwdl_info->fw_en) { + if (fwdl_info->dlrom_en) { + switch (hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + rom_addr = RTL8852A_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8852B: + rom_addr = RTL8852B_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8852C: + rom_addr = RTL8852C_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8192XB: + rom_addr = RTL8192XB_ROM_ADDR; + break; + default: + PLTFM_MSG_ERR("[ERR]chip id\n"); + return MACNOITEM; + } + ret = mac_ops->romdl(adapter, + fwdl_info->rom_buff, + rom_addr, + fwdl_info->rom_size); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]romdl %d\n", ret); + goto end; + } + } + + if (fwdl_info->dlram_en) { + if (fwdl_info->fw_from_hdr) { + ret = mac_ops->enable_fw(adapter, + fwdl_info->fw_cat); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]enable_fw %d\n", + ret); + goto end; + } + } else { + ret = mac_ops->enable_cpu(adapter, 0, + fwdl_info->dlram_en); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]enable_cpu %d\n", + ret); + goto end; + } + + ret = mac_ops->fwdl(adapter, + fwdl_info->ram_buff, + fwdl_info->ram_size); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]fwdl %d\n", ret); + goto end; + } + } + } + } + + ret = set_enable_bb_rf(adapter, MAC_AX_FUNC_EN); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]set_enable_bb_rf %d\n", ret); + goto end; + } + + ret = mac_ops->sys_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sys_init %d\n", ret); + goto end; + } + + ret = mac_ops->trx_init(adapter, trx_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]trx_init %d\n", ret); + goto end; + } + + ret = ops->intf_init(adapter, intf_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]intf_init %d\n", ret); + goto end; + } + +end: + if (ret != MACSUCCESS) { + adapter->sm.mac_rdy = MAC_AX_MAC_INIT_ERR; + PLTFM_MSG_ERR("[ERR]hal_init fail %d\n", ret); +#if MAC_AX_FEATURE_DBGPKG + dbg_en.ss_dbg = 1; + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.mac_dbg_port = 1; + dbg_en.plersvd_dbg = 1; + mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en); +#endif + } else { + adapter->sm.mac_rdy = MAC_AX_MAC_RDY; + } + + return ret; +} + +u32 mac_hal_deinit(struct mac_ax_adapter *adapter) +{ + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *intf_ops = adapter_to_intf_ops(adapter); +#if MAC_AX_FEATURE_DBGPKG + struct mac_ax_dbgpkg dbg_val = {0}; + struct mac_ax_dbgpkg_en dbg_en = {0}; +#endif + u32 ret; + + adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY; + + _mp_core_swr_volt(adapter, 1); + + ret = rst_port_info(adapter, MAC_AX_BAND_0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]reset port info %d\n", ret); + return ret; + } + + if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + ret = rst_port_info(adapter, MAC_AX_BAND_1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]reset port info %d\n", ret); + return ret; + } + } + + ret = rst_p2p_info(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]reset p2p info %d\n", ret); + return ret; + } + + ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]remove security info tbl\n"); + return ret; + } + + ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_0, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]remove band0 role fail\n"); + return ret; + } + + ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_1, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]remove band0 role fail\n"); + return ret; + } + + ret = intf_ops->intf_deinit(adapter, NULL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]intf deinit\n"); + goto end; + } + + ret = ops->pwr_switch(adapter, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr switch off\n"); + goto end; + } + +end: + if (ret != MACSUCCESS) { + adapter->sm.mac_rdy = MAC_AX_MAC_DEINIT_ERR; + PLTFM_MSG_ERR("[ERR]hal_deinit fail %d\n", ret); +#if MAC_AX_FEATURE_DBGPKG + dbg_en.ss_dbg = 1; + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.mac_dbg_port = 1; + dbg_en.plersvd_dbg = 1; + ops->dbg_status_dump(adapter, &dbg_val, &dbg_en); +#endif + } + + return ret; +} + +u32 mac_hal_fast_init(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info) +{ + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_hw_info *hw_info = adapter->hw_info; +#if MAC_AX_FEATURE_DBGPKG + struct mac_ax_dbgpkg dbg_val = {0}; + struct mac_ax_dbgpkg_en dbg_en = {0}; +#endif + u32 rom_addr; + u32 ret; + u8 fwdl_en; + + ret = mac_ops->pwr_switch(adapter, 1); + if (ret == MACALRDYON) { + ret = mac_ops->pwr_switch(adapter, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 0 fail %d\n", ret); + goto end; + } + ret = mac_ops->pwr_switch(adapter, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 0->1 fail %d\n", ret); + goto end; + } + } + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr_switch 1 fail %d\n", ret); + goto end; + } +#if MAC_AX_PCIE_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + ret = _patch_pcie_pldr_polling_fail(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]_patch_pcie_pldr_polling_fail %d\n", ret); + goto end; + } + } +#endif + ret = hci_func_en(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]hci_func_en %d\n", ret); + goto end; + } + + fwdl_en = fwdl_info->fw_en && + (fwdl_info->dlrom_en || fwdl_info->dlram_en) ? 1 : 0; + ret = dmac_pre_init(adapter, trx_info->qta_mode, fwdl_en); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]fwdl_pre_init %d\n", ret); + goto end; + } + + ret = ops->intf_pre_init(adapter, intf_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]intf_pre_init %d\n", ret); + goto end; + } + + if (fwdl_info->fw_en) { + if (fwdl_info->dlrom_en) { + switch (hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + rom_addr = RTL8852A_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8852B: + rom_addr = RTL8852B_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8852C: + rom_addr = RTL8852C_ROM_ADDR; + break; + case MAC_AX_CHIP_ID_8192XB: + rom_addr = RTL8192XB_ROM_ADDR; + break; + default: + PLTFM_MSG_ERR("[ERR]chip id\n"); + return MACNOITEM; + } + ret = mac_ops->romdl(adapter, + fwdl_info->rom_buff, + rom_addr, + fwdl_info->rom_size); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]romdl %d\n", ret); + goto end; + } + } + + if (fwdl_info->dlram_en) { + if (fwdl_info->fw_from_hdr) { + ret = mac_ops->enable_fw(adapter, + fwdl_info->fw_cat); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]enable_fw %d\n", + ret); + goto end; + } + } else { + ret = mac_ops->enable_cpu(adapter, 0, + fwdl_info->dlram_en); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]enable_cpu %d\n", + ret); + goto end; + } + + ret = mac_ops->fwdl(adapter, + fwdl_info->ram_buff, + fwdl_info->ram_size); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]fwdl %d\n", ret); + goto end; + } + } + } + } + +end: + if (ret != MACSUCCESS) { + adapter->sm.mac_rdy = MAC_AX_MAC_FINIT_ERR; + PLTFM_MSG_ERR("[ERR]hal_fast_init fail %d\n", ret); +#if MAC_AX_FEATURE_DBGPKG + dbg_en.ss_dbg = 1; + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.mac_dbg_port = 1; + dbg_en.plersvd_dbg = 1; + mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en); +#endif + } else { + adapter->sm.mac_rdy = MAC_AX_MAC_RDY; + } + + return ret; +} + +u32 mac_hal_fast_deinit(struct mac_ax_adapter *adapter) +{ + struct mac_ax_ops *ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *intf_ops = adapter_to_intf_ops(adapter); +#if MAC_AX_FEATURE_DBGPKG + struct mac_ax_dbgpkg dbg_val = {0}; + struct mac_ax_dbgpkg_en dbg_en = {0}; +#endif + u32 ret; + + adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY; + + ret = intf_ops->intf_deinit(adapter, NULL); + if (ret) { + PLTFM_MSG_ERR("[ERR]intf deinit\n"); + goto end; + } + + ret = ops->pwr_switch(adapter, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]pwr switch off\n"); + goto end; + } +end: + if (ret != MACSUCCESS) { + adapter->sm.mac_rdy = MAC_AX_MAC_FDEINIT_ERR; + PLTFM_MSG_ERR("[ERR]hal_fast_deinit fail %d\n", ret); +#if MAC_AX_FEATURE_DBGPKG + dbg_en.ss_dbg = 1; + dbg_en.dle_dbg = 1; + dbg_en.dmac_dbg = 1; + dbg_en.cmac_dbg = 1; + dbg_en.mac_dbg_port = 1; + dbg_en.plersvd_dbg = 1; + ops->dbg_status_dump(adapter, &dbg_val, &dbg_en); +#endif + } + + return ret; +} + +u32 mac_ax_init_state(struct mac_ax_adapter *adapter) +{ + struct mac_ax_state_mach sm = MAC_AX_DFLT_SM; + + adapter->sm = sm; + adapter->fw_info.h2c_seq = 0; + adapter->fw_info.rec_seq = 0; + + return MACSUCCESS; +} + +u32 mix_info_init(struct mac_ax_adapter *adapter) +{ + PLTFM_MUTEX_INIT(&adapter->fw_info.seq_lock); + PLTFM_MUTEX_INIT(&adapter->fw_info.msg_reg); + PLTFM_MUTEX_INIT(&adapter->flash_info.lock); + PLTFM_MUTEX_INIT(&adapter->hw_info->ind_access_lock); + PLTFM_MUTEX_INIT(&adapter->hw_info->lte_rlock); + PLTFM_MUTEX_INIT(&adapter->hw_info->lte_wlock); + PLTFM_MUTEX_INIT(&adapter->hw_info->dbg_port_lock); + PLTFM_MUTEX_INIT(&adapter->cmd_ofld_info.cmd_ofld_lock); + PLTFM_MUTEX_INIT(&adapter->hw_info->err_set_lock); + PLTFM_MUTEX_INIT(&adapter->hw_info->err_get_lock); +#if MAC_AX_PCIE_SUPPORT + PLTFM_MUTEX_INIT(&adapter->hw_info->dbi_lock); + PLTFM_MUTEX_INIT(&adapter->hw_info->mdio_lock); +#endif + PLTFM_MUTEX_INIT(&adapter->h2c_agg_info.h2c_agg_lock); + PLTFM_MUTEX_INIT(&adapter->scanofld_info.drv_chlist_state_lock); + PLTFM_MUTEX_INIT(&adapter->scanofld_info.fw_chlist_state_lock); + adapter->hw_info->ind_aces_cnt = 0; + adapter->hw_info->dbg_port_cnt = 0; + + return MACSUCCESS; +} + +u32 mix_info_exit(struct mac_ax_adapter *adapter) +{ + PLTFM_MUTEX_DEINIT(&adapter->fw_info.seq_lock); + PLTFM_MUTEX_DEINIT(&adapter->fw_info.msg_reg); + PLTFM_MUTEX_DEINIT(&adapter->flash_info.lock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->ind_access_lock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->lte_rlock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->lte_wlock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->dbg_port_lock); + PLTFM_MUTEX_DEINIT(&adapter->cmd_ofld_info.cmd_ofld_lock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->err_set_lock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->err_get_lock); +#if MAC_AX_PCIE_SUPPORT + PLTFM_MUTEX_DEINIT(&adapter->hw_info->dbi_lock); + PLTFM_MUTEX_DEINIT(&adapter->hw_info->mdio_lock); +#endif + PLTFM_MUTEX_DEINIT(&adapter->h2c_agg_info.h2c_agg_lock); + PLTFM_MUTEX_DEINIT(&adapter->scanofld_info.drv_chlist_state_lock); + PLTFM_MUTEX_DEINIT(&adapter->scanofld_info.fw_chlist_state_lock); + adapter->hw_info->ind_aces_cnt = 0; + adapter->hw_info->dbg_port_cnt = 0; + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/init.h b/phl/hal_g6/mac/mac_ax/init.h new file mode 100644 index 0000000..f3bd94b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/init.h @@ -0,0 +1,260 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_INIT_H_ +#define _MAC_AX_INIT_H_ + +#include "../type.h" +#if MAC_AX_8852A_SUPPORT +#include "mac_8852a/init_8852a.h" +#endif +#if MAC_AX_8852B_SUPPORT +#include "mac_8852b/init_8852b.h" +#endif +#if MAC_AX_8852C_SUPPORT +#include "mac_8852c/init_8852c.h" +#endif +#if MAC_AX_8192XB_SUPPORT +#include "mac_8192xb/init_8192xb.h" +#endif + +#include "role.h" +#include "fwdl.h" +#include "mport.h" +#if MAC_AX_PCIE_SUPPORT +#include "_pcie.h" +#endif +/*--------------------Define -------------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +/*--------------------Define Struct-------------------------------------*/ + +#ifdef CONFIG_NEW_HALMAC_INTERFACE + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief get_mac_ax_adapter + * + * @param intf + * @param chip_id + * @param cv + * @param *phl_adapter + * @param *drv_adapter + * @param *pltfm_cb + * @return Please Place Description here. + * @retval mac_ax_adapter + */ +struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf, + u8 chip_id, u8 cv, + void *phl_adapter, void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief get_mac_ax_adapter + * + * @param intf + * @param chip_id + * @param cv + * @param *drv_adapter + * @param *pltfm_cb + * @return Please Place Description here. + * @retval mac_ax_adapter + */ +#else +struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf, + u8 chip_id, u8 cv, + void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief cmac_func_en + * + * @param *adapter + * @param band + * @param en + * @return Please Place Description here. + * @retval u32 + */ +#endif +u32 cmac_func_en(struct mac_ax_adapter *adapter, u8 band, u8 en); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_sys_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sys_init(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_hal_init + * + * @param *adapter + * @param *trx_info + * @param *fwdl_info + * @param *intf_info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_hal_init(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_hal_fast_init + * + * @param *adapter + * @param *trx_info + * @param *fwdl_info + * @param *intf_info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_hal_fast_init(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_hal_fast_deinit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_hal_fast_deinit(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_hal_deinit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_hal_deinit(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup System + * @{ + */ + +/** + * @brief mac_ax_init_state + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ax_init_state(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +u32 mix_info_init(struct mac_ax_adapter *adapter); +u32 mix_info_exit(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/la_mode.c b/phl/hal_g6/mac/mac_ax/la_mode.c new file mode 100644 index 0000000..153bf30 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/la_mode.c @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "la_mode.h" + +u32 mac_lamode_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_la_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN); + val32 |= B_AX_BBRPT_EN; + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); + + val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN); + val32 |= B_AX_BBRPT_CLK_EN; + MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); + + val32 = MAC_REG_R32(R_AX_LA_CFG); + val32 &= ~BITS_AX_LA_CFG; + val32 |= ((cfg->la_func_en ? B_AX_LA_FEN : 0) | + (cfg->la_restart_en ? B_AX_LA_RESTART_EN : 0) | + (cfg->la_timeout_en ? B_AX_LA_TO_EN : 0) | + SET_WORD(cfg->la_timeout_val, B_AX_LA_TO_VAL) | + SET_WORD(cfg->la_tgr_tu_sel, B_AX_LA_TRIG_TU_SEL) | + SET_WORD(cfg->la_tgr_time_val, B_AX_LA_TRIG_TIME_VAL)); + MAC_REG_W32(R_AX_LA_CFG, val32); + + if (cfg->la_data_loss_imr) + MAC_REG_W8(R_AX_LA_ERRFLAG, BIT0); + + return MACSUCCESS; +} + +u32 mac_lamode_buf_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_la_buf_param *param) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_LA_CFG); + val32 &= ~BITS_AX_LA_BUF_CFG; + val32 |= SET_WORD(param->la_buf_sel, B_AX_LA_BUF_SEL); + if (param->la_buf_sel == LA_BUF_SEL_256K) { /* la buf 256K */ + val32 |= SET_WORD(LA_SIZE_256K_BUF_BNDY, B_AX_LA_BUF_BNDY); + param->start_addr = LA_SIZE_256K_BUF_BNDY * DLE_BLOCK_SIZE; + param->end_addr = DLE_BUF_BNDY_8852A; + } else if (param->la_buf_sel == LA_BUF_SEL_192K) { /* la buf 192K */ + val32 |= SET_WORD(LA_SIZE_192K_BUF_BNDY, B_AX_LA_BUF_BNDY); + param->start_addr = LA_SIZE_192K_BUF_BNDY * DLE_BLOCK_SIZE; + param->end_addr = DLE_BUF_BNDY_8852A; + } else if (param->la_buf_sel == LA_BUF_SEL_128K) { /* la buf 128K */ + val32 |= SET_WORD(LA_SIZE_128K_BUF_BNDY_8852B, + B_AX_LA_BUF_BNDY); + param->start_addr = LA_SIZE_128K_BUF_BNDY_8852B * + DLE_BLOCK_SIZE; + param->end_addr = DLE_BUF_BNDY_8852B; + } else if (param->la_buf_sel == LA_BUF_SEL_64K) { /* la buf 64K */ + val32 |= SET_WORD(LA_SIZE_128K_BUF_BNDY_8852B, + B_AX_LA_BUF_BNDY); + param->start_addr = LA_SIZE_128K_BUF_BNDY_8852B * + DLE_BLOCK_SIZE; + param->end_addr = DLE_BUF_BNDY_8852B; + } else { + PLTFM_MSG_ERR("[ERR]Non support buf sel %d\n", + param->la_buf_sel); + } + + MAC_REG_W32(R_AX_LA_CFG, val32); + + return MACSUCCESS; +} + +u32 mac_lamode_trigger(struct mac_ax_adapter *adapter, u8 tgr) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 count = 3000; + u8 val8; + + if (tgr) { + val8 = MAC_REG_R8(R_AX_LA_CFG); + MAC_REG_W8(R_AX_LA_CFG, val8 | B_AX_LA_TRIG_START); + } + + val8 = MAC_REG_R8(R_AX_LA_CFG); + while (--count) { + if (!(val8 & B_AX_LA_TRIG_START)) + break; + PLTFM_DELAY_MS(1); + } + if (!count) + return MACPOLLTO; + + return MACSUCCESS; +} + +struct mac_ax_la_status mac_get_lamode_st(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + struct mac_ax_la_status info; + + info.la_buf_wptr = 0; + info.la_buf_rndup_ind = 0; + info.la_sw_fsmst = 0; + info.la_data_loss = 0; + + val32 = MAC_REG_R32(R_AX_LA_STATUS); + info.la_sw_fsmst = (val32 >> B_AX_LA_SW_FSMST_SH) & + B_AX_LA_SW_FSMST_MSK; + info.la_buf_wptr = (val32 >> B_AX_LA_BUF_WPTR_SH) & + B_AX_LA_BUF_WPTR_MSK; + info.la_buf_rndup_ind = (val32 & B_AX_LA_BUF_RNDUP) ? 1 : 0; + + val32 = MAC_REG_R32(R_AX_LA_ERRFLAG); + info.la_data_loss = (val32 & B_AX_LA_ISR_DATA_LOSS_ERR) ? 1 : 0; + + return info; +} + diff --git a/phl/hal_g6/mac/mac_ax/la_mode.h b/phl/hal_g6/mac/mac_ax/la_mode.h new file mode 100644 index 0000000..bfd856c --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/la_mode.h @@ -0,0 +1,130 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_LA_MODE_H_ +#define _MAC_AX_LA_MODE_H_ + +#include "../type.h" +#include "../mac_ax.h" + +/*--------------------Define ----------------------------------------*/ +#define BITS_AX_LA_BUF_CFG 0xFFF00 +#define BITS_AX_LA_CFG 0xFFF000FF +#define LA_SIZE_192K_BUF_BNDY 0x20 +#define LA_SIZE_256K_BUF_BNDY 0x18 +#define DLE_BLOCK_SIZE 0x2000 +#define DLE_BUF_BNDY_8852A 0x70000 +#define DLE_BUF_BNDY_8852B 0x20000 + +#define LA_BUF_SEL_256K 3 +#define LA_BUF_SEL_192K 2 +#define LA_BUF_SEL_128K 1 +#define LA_BUF_SEL_64K 0 + +#define LA_SIZE_128K_BUF_BNDY_8852B 0x8 + +/*--------------------Define Enum------------------------------------*/ +/*--------------------Define MACRO----------------------------------*/ +/*--------------------Define Struct-----------------------------------*/ +/*--------------------Export global variable----------------------------*/ +/*--------------------Function declaration-----------------------------*/ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ +/** + * @brief mac_lamode_cfg + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_lamode_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_la_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_lamode_trigger + * + * @param *adapter + * @param tgr + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_lamode_trigger(struct mac_ax_adapter *adapter, u8 tgr); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_lamode_buf_cfg + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_lamode_buf_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_la_buf_param *param); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_get_lamode_st + * + * @param *adapter + * @return Please Place Description here. + * @retval mac_ax_la_status + */ +struct mac_ax_la_status mac_get_lamode_st + (struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.c b/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.c new file mode 100644 index 0000000..dbc88ae --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.c @@ -0,0 +1,521 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "_usb_8852b.h" +#include "../../mac_ax.h" + +#if MAC_AX_USB_SUPPORT + +u8 reg_read8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr) +{ + u8 offset, count = 0; + u32 val; + + offset = addr % MAC_REG_OFFSET; + val = PLTFM_REG_R32(addr - offset); + if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) { + while (count < MAC_REG_POOL_COUNT) { + if (val != MAC_AX_R32_DEAD) + break; + + PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr + offset); + PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN); + val = PLTFM_REG_R32(addr); + count++; + } + } + + return (u8)(val >> (offset * MAC_REG_OFFSET_SH)); +} + +void reg_write8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u8 val) +{ + PLTFM_REG_W8(addr, val); +} + +u16 reg_read16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr) +{ + u8 offset, count = 0; + u32 val; + + offset = addr % MAC_REG_OFFSET; + val = PLTFM_REG_R32(addr - offset); + if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) { + while (count < MAC_REG_POOL_COUNT) { + if (val != MAC_AX_R32_DEAD) + break; + + PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr + offset); + PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN); + val = PLTFM_REG_R32(addr); + count++; + } + } + + return (u16)(val >> (offset * MAC_REG_OFFSET_SH)); +} + +void reg_write16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u16 val) +{ + PLTFM_REG_W16(addr, val); +} + +u32 reg_read32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr) +{ + u8 count = 0; + u32 val = PLTFM_REG_R32(addr); + + if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) { + while (count < MAC_REG_POOL_COUNT) { + if (val != MAC_AX_R32_DEAD) + break; + + PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr); + PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN); + val = PLTFM_REG_R32(addr); + count++; + } + } + + return val; +} + +void reg_write32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u32 val) +{ + PLTFM_REG_W32(addr, val); +} + +u8 get_bulkout_id_8852b(struct mac_ax_adapter *adapter, u8 ch_dma, u8 mode) +{ + u8 bulkout_id = 0; + + if (mode == 0 && adapter->usb_info.ep5 && adapter->usb_info.ep6 && + adapter->usb_info.ep12) { + switch (ch_dma) { + case MAC_AX_DMA_ACH0: + bulkout_id = BULKOUTID3; + break; + case MAC_AX_DMA_ACH1: + bulkout_id = BULKOUTID4; + break; + case MAC_AX_DMA_ACH2: + bulkout_id = BULKOUTID5; + break; + case MAC_AX_DMA_ACH3: + bulkout_id = BULKOUTID6; + break; + case MAC_AX_DMA_B0MG: + case MAC_AX_DMA_B0HI: + bulkout_id = BULKOUTID0; + break; + case MAC_AX_DMA_H2C: + bulkout_id = BULKOUTID2; + break; + default: + return USBEPMAPERR; + } + } else if ((mode == 1) && adapter->usb_info.ep5 && + adapter->usb_info.ep6 && adapter->usb_info.ep12) { + switch (ch_dma) { + case MAC_AX_DMA_ACH0: + bulkout_id = BULKOUTID2; + break; + case MAC_AX_DMA_ACH1: + bulkout_id = BULKOUTID3; + break; + case MAC_AX_DMA_ACH2: + bulkout_id = BULKOUTID4; + break; + case MAC_AX_DMA_ACH3: + bulkout_id = BULKOUTID5; + break; + case MAC_AX_DMA_B0MG: + case MAC_AX_DMA_B0HI: + bulkout_id = BULKOUTID0; + break; + case MAC_AX_DMA_H2C: + bulkout_id = BULKOUTID2; + break; + default: + bulkout_id = USBEPMAPERR; + } + } else { + bulkout_id = USBEPMAPERR; + } + return bulkout_id; +} + +u32 usb_pre_init_8852b(struct mac_ax_adapter *adapter, void *param) +{ + u32 val32 = 0; + + val32 = PLTFM_REG_R32(R_AX_USB_HOST_REQUEST_2) | B_AX_R_USBIO_MODE; + PLTFM_REG_W32(R_AX_USB_HOST_REQUEST_2, val32); + // fix USB IO hang suggest by chihhanli@realtek.com + val32 = PLTFM_REG_R32(R_AX_USB_WLAN0_1) & ~(B_AX_USBRX_RST | B_AX_USBTX_RST); + PLTFM_REG_W32(R_AX_USB_WLAN0_1, val32); + + val32 = PLTFM_REG_R32(R_AX_HCI_FUNC_EN); + val32 &= ~B_AX_HCI_RXDMA_EN; + val32 &= ~B_AX_HCI_TXDMA_EN; + PLTFM_REG_W32(R_AX_HCI_FUNC_EN, val32); + val32 |= B_AX_HCI_RXDMA_EN; + val32 |= B_AX_HCI_TXDMA_EN; + PLTFM_REG_W32(R_AX_HCI_FUNC_EN, val32); + // fix USB TRX hang suggest by chihhanli@realtek.com + + val32 = PLTFM_REG_R32(R_AX_USB_ENDPOINT_3); + if ((val32 & B_AX_BULKOUT0) == B_AX_BULKOUT0) + adapter->usb_info.ep5 = ENABLE; + if ((val32 & B_AX_BULKOUT1) == B_AX_BULKOUT1) + adapter->usb_info.ep6 = ENABLE; + if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) & + B_AX_AC_BULKOUT_MSK) == 1) + adapter->usb_info.ep10 = ENABLE; + if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) & + B_AX_AC_BULKOUT_MSK) == 2) { + adapter->usb_info.ep10 = ENABLE; + adapter->usb_info.ep11 = ENABLE; + } + if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) & + B_AX_AC_BULKOUT_MSK) == 3) { + adapter->usb_info.ep10 = ENABLE; + adapter->usb_info.ep11 = ENABLE; + adapter->usb_info.ep12 = ENABLE; + } + return MACSUCCESS; +} + +u32 usb_init_8852b(struct mac_ax_adapter *adapter, void *param) +{ + u32 val32; + u8 val8; + + adapter->usb_info.max_bulkout_wd_num = GET_FIELD + (PLTFM_REG_R32(R_AX_CH_PAGE_CTRL), B_AX_PREC_PAGE_CH011); + + val32 = PLTFM_REG_R32(R_AX_USB3_MAC_NPI_CONFIG_INTF_0); + val32 &= ~B_AX_SSPHY_LFPS_FILTER; + PLTFM_REG_W32(R_AX_USB3_MAC_NPI_CONFIG_INTF_0, val32); + + /* else if (is_cv(adapter, CBV) && + * is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + * val32 = PLTFM_REG_R32(R_AX_USB3_MAC_LINK_0); + * val32 &= ~B_AX_R_DIS_USB3_U1_EN; + * val32 &= ~B_AX_R_DIS_USB3_U2_EN; + * PLTFM_REG_W32(R_AX_USB3_MAC_LINK_0, val32); + *} else { + * val32 = PLTFM_REG_R32(R_AX_USB3_MAC_LINK_0); + * val32 |= B_AX_R_DIS_USB3_U1_EN; + * val32 |= B_AX_R_DIS_USB3_U2_EN; + * PLTFM_REG_W32(R_AX_USB3_MAC_LINK_0, val32); + *} + */ + val32 = get_usb_mode(adapter); + if (val32 == MAC_AX_USB3) + PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB3_BULKSIZE); + else if (val32 == MAC_AX_USB2) + PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB2_BULKSIZE); + else if (val32 == MAC_AX_USB11) + PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB11_BULKSIZE); + else + return MACHWNOSUP; + + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP5, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP6, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP7, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP9, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP10, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP11, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0); + val8 = SET_CLR_WORD(val8, EP12, B_AX_EP_IDX); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8); + PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP); + return MACSUCCESS; +} + +u32 usb_deinit_8852b(struct mac_ax_adapter *adapter, void *param) +{ + return MACSUCCESS; +} + +u32 read_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset) +{ + u32 value32 = 0; + u8 rdata = 0; + + value32 = SET_CLR_WORD(value32, offset - phyoffset, + B_AX_USB_SIE_INTF_ADDR); + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_REG_EN; + value32 |= B_AX_USB_REG_STATUS; + PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32); + + while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN) + ; + + rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB_SIE_INTF), + B_AX_USB_SIE_INTF_RD); + + //DD-Yingli suggest that shall clear it if read operation is done. + PLTFM_REG_W32(R_AX_USB_SIE_INTF, 0); + return rdata; +} + +u32 write_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 val) +{ + u32 value32 = 0; + + value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD); + value32 = SET_CLR_WORD(value32, offset, B_AX_USB_SIE_INTF_ADDR); + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_WRITE_EN; + value32 |= B_AX_USB_REG_EN; + value32 |= B_AX_USB_REG_STATUS; + + PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32); + while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN) + ; + + //DD-Yingli suggest that shall clear it if write operation is done. + PLTFM_REG_W32(R_AX_USB_SIE_INTF, 0); + + return MACSUCCESS; +} + +u32 read_usb3phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 b_sel) +{ + u32 value32 = 0; + u16 rdata = 0; + + if (is_cv(adapter, CAV)) { + value32 = (u32)offset; + value32 |= B_AX_USB3_PHY_REG_RDFLAG; + PLTFM_REG_W32(R_AX_USB3_PHY, value32); + while (PLTFM_REG_R32(R_AX_USB3_PHY) & B_AX_USB3_PHY_REG_RDFLAG) + ; + rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB3_PHY), + B_AX_USB3_PHY_RWDATA); + } else { + value32 = SET_CLR_WORD(value32, offset + USBPHYOFFSET, + B_AX_USB_SIE_INTF_ADDR); + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_REG_EN; + if (b_sel) + value32 |= B_AX_USB_PHY_BYTE_SEL; + + PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32); + while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN) + ; + + rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB_SIE_INTF), + B_AX_USB_SIE_INTF_RD); + } + + return rdata; +} + +u32 write_usb3phy_para_8852b(struct mac_ax_adapter *adapter, + u16 offset, u8 b_sel, u8 val) +{ + u32 value32 = 0; + + if (is_cv(adapter, CAV)) { + value32 = SET_CLR_WORD(value32, val, B_AX_USB3_PHY_RWDATA); + value32 |= (u32)offset; + value32 |= B_AX_USB3_PHY_REG_WRFLAG; + PLTFM_REG_W32(R_AX_USB3_PHY, value32); + while (PLTFM_REG_R32(R_AX_USB3_PHY) & B_AX_USB3_PHY_REG_WRFLAG) + ; + } else { + value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD); + value32 = SET_CLR_WORD(value32, offset + USBPHYOFFSET, + B_AX_USB_SIE_INTF_ADDR); + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_REG_SEL; + value32 |= B_AX_USB_WRITE_EN; + value32 |= B_AX_USB_REG_EN; + if (b_sel) + value32 |= B_AX_USB_PHY_BYTE_SEL; + PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32); + while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN) + ; + } + + return MACSUCCESS; +} + +u32 u2u3_switch_8852b(struct mac_ax_adapter *adapter) +{ + u32 ret = 0; + + PLTFM_REG_W8(R_AX_PAD_CTRL2 + 1, USB_SWITCH_DELAY); + ret = get_usb_mode(adapter); + if (ret == MAC_AX_USB2) + PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U2SWITCHU3); + else if (ret == MAC_AX_USB3) + PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U3SWITCHU2); + else + PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U2SWITCHU3); + + return MACSUCCESS; +} + +u32 get_usb_support_ability_8852b(struct mac_ax_adapter *adapter) +{ + u32 u2force = 0; + u32 u3force = 0; + + u2force = PLTFM_REG_R32(R_AX_USB_HOST_REQUEST_2) & + B_AX_R_FORCE_U3MAC_HS_MODE; + u3force = PLTFM_REG_R32(R_AX_PAD_CTRL2) & + B_AX_USB3_USB2_TRANSITION; + + if (u2force == B_AX_R_FORCE_U3MAC_HS_MODE) + return FORCEUSB2MODE; + else if (u3force == B_AX_USB3_USB2_TRANSITION) + return SWITCHMODE; + else + return FORCEUSB3MODE; +} + +u32 usb_tx_agg_cfg_8852b(struct mac_ax_adapter *adapter, + struct mac_ax_usb_tx_agg_cfg *agg) +{ + u32 dw1 = ((struct wd_body_usb_8852b *)agg->pkt)->dword1; + + ((struct wd_body_usb_8852b *)agg->pkt)->dword1 = + SET_CLR_WORD(dw1, agg->agg_num, AX_TXD_DMA_TXAGG_NUM); + return MACSUCCESS; +} + +u32 usb_rx_agg_cfg_8852b(struct mac_ax_adapter *adapter, + struct mac_ax_rx_agg_cfg *cfg) +{ + u8 size; + u8 timeout; + u8 agg_en; + u8 agg_mode; + u8 pkt_num; + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (cfg->mode == MAC_AX_RX_AGG_MODE_DMA) { + agg_en = ENABLE; + agg_mode = ENABLE; + } else if (cfg->mode == MAC_AX_RX_AGG_MODE_USB) { + agg_en = ENABLE; + agg_mode = DISABLE; + } else { + agg_en = DISABLE; + agg_mode = DISABLE; + } + + if (cfg->thold.drv_define == 0) { + size = RXAGGSIZE; + timeout = RXAGGTO; + pkt_num = 0; + } else { + size = cfg->thold.size; + timeout = cfg->thold.timeout; + pkt_num = cfg->thold.pkt_num; + } + + val32 = MAC_REG_R32(R_AX_RXAGG_0); + MAC_REG_W32(R_AX_RXAGG_0, (agg_en ? B_AX_RXAGG_EN : 0) | + (agg_mode ? B_AX_RXAGG_DMA_STORE : 0) | + (val32 & B_AX_RXAGG_SW_EN) | + SET_WORD(pkt_num, B_AX_RXAGG_PKTNUM_TH) | + SET_WORD(timeout, B_AX_RXAGG_TIMEOUT_TH) | + SET_WORD(size, B_AX_RXAGG_LEN_TH)); + return MACSUCCESS; +} + +u32 usb_pwr_switch_8852b(void *vadapter, u8 pre_switch, u8 on) +{ + return MACSUCCESS; +} + +u32 set_usb_wowlan_8852b(struct mac_ax_adapter *adapter, + enum mac_ax_wow_ctrl w_c) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (w_c == MAC_AX_WOW_ENTER) { + PLTFM_REG_W32(R_AX_USB2_LPM_0, PLTFM_REG_R32(R_AX_USB2_LPM_0) | + B_AX_USB_SUS_WAKEUP_EN); + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) | + B_AX_WLOCK_1C_B6); + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) | + B_AX_R_DIS_PRST); + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) & + ~B_AX_WLOCK_1C_B6); + } else if (w_c == MAC_AX_WOW_LEAVE) { + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) | + B_AX_WLOCK_1C_B6); + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) & + ~B_AX_R_DIS_PRST); + MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) & + ~B_AX_WLOCK_1C_B6); + } else { + PLTFM_MSG_ERR("[ERR] Invalid WoWLAN input.\n"); + return MACFUNCINPUT; + } + + return MACSUCCESS; +} + +u32 usb_get_txagg_num_8852b(struct mac_ax_adapter *adapter, u8 band) +{ + u32 quotanum = band ? adapter->dle_info.c1_tx_min : adapter->dle_info.c0_tx_min; + + return quotanum * PLE_PAGE_SIZE / (PINGPONG * (SINGLE_MSDU_SIZE + SEC_FCS_SIZE)); +} + +u32 usb_get_rx_state_8852b(struct mac_ax_adapter *adapter, u32 *val) +{ + u8 rxdma_cnt, ep_cnt, curr_rxdma_cnt, curr_ep_cnt; + *val = 0; + rxdma_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_DMA_COUNTER); + ep_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_ENDPOINT_COUNTER); + PLTFM_DELAY_MS(RX_POLLING_PERIOD); + curr_rxdma_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_DMA_COUNTER); + curr_ep_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_ENDPOINT_COUNTER); + if (curr_rxdma_cnt == rxdma_cnt) + return MACRXDMAHANG; + else if (curr_ep_cnt == ep_cnt) + return MACUSBRXHANG; + else + return MACSUCCESS; +} +#endif /* #if MAC_AX_USB_SUPPORT */ diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.h b/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.h new file mode 100644 index 0000000..9031189 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.h @@ -0,0 +1,509 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_USB_8852B_H_ +#define _MAC_AX_USB_8852B_H_ + +#include "../../type.h" +#include "../_usb.h" + +/** + * @struct wd_body_usb + * @brief wd_body_usb + * + * @var wd_body_usb::dword0 + * Please Place Description here. + * @var wd_body_usb::dword1 + * Please Place Description here. + * @var wd_body_usb::dword2 + * Please Place Description here. + * @var wd_body_usb::dword3 + * Please Place Description here. + * @var wd_body_usb::dword4 + * Please Place Description here. + * @var wd_body_usb::dword5 + * Please Place Description here. + */ +struct wd_body_usb_8852b { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ +/** + * @brief reg_read8_usb_8852b + * + * @param *adapter + * @param addr + * @return Please Place Description here. + * @retval u8 + */ +u8 reg_read8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ + +/** + * @brief reg_write8_usb_8852b + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval void + */ +void reg_write8_usb_8852b(struct mac_ax_adapter *adapter, + u32 addr, u8 val); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ + +/** + * @brief reg_read16_usb_8852b + * + * @param *adapter + * @param addr + * @return Please Place Description here. + * @retval u16 + */ +u16 reg_read16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ + +/** + * @brief reg_write16_usb_8852b + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval void + */ +void reg_write16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u16 val); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ + +/** + * @brief reg_read32_usb_8852b + * + * @param *adapter + * @param addr + * @return Please Place Description here. + * @retval u32 + */ +u32 reg_read32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup BasicIO + * @{ + */ + +/** + * @brief reg_write32_usb_8852b + * + * @param *adapter + * @param addr + * @param val + * @return Please Place Description here. + * @retval void + */ +void reg_write32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u32 val); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief get_bulkout_id_8852b + * + * @param *adapter + * @param ch_dma + * @param mode + * @return Please Place Description here. + * @retval u8 + */ +u8 get_bulkout_id_8852b(struct mac_ax_adapter *adapter, u8 ch_dma, u8 mode); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_pre_init_8852b + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_pre_init_8852b(struct mac_ax_adapter *adapter, void *param); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_init_8852b + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_init_8852b(struct mac_ax_adapter *adapter, void *param); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_deinit_8852b + * + * @param *adapter + * @param *param + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_deinit_8852b(struct mac_ax_adapter *adapter, void *param); + +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief read_usb2phy_para_8852b + * + * @param *adapter + * @param offset + * @return Please Place Description here. + * @retval u32 + */ +u32 read_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief write_usb2phy_para_8852b + * + * @param *adapter + * @param offset + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 write_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 val); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief read_usb3phy_para_8852b + * + * @param *adapter + * @param offset + * @param b_sel + * @return Please Place Description here. + * @retval u32 + */ +u32 read_usb3phy_para_8852b(struct mac_ax_adapter *adapter, + u16 offset, u8 b_sel); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief write_usb3phy_para_8852b + * + * @param *adapter + * @param offset + * @param b_sel + * @param val + * @return Please Place Description here. + * @retval u32 + */ +u32 write_usb3phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, + u8 b_sel, u8 val); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief u2u3_switch_8852b + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 u2u3_switch_8852b(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + + /** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief get_usb_support_ability_8852b + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 get_usb_support_ability_8852b(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_tx_agg_cfg_8852b + * + * @param *adapter + * @param *agg + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_tx_agg_cfg_8852b(struct mac_ax_adapter *adapter, + struct mac_ax_usb_tx_agg_cfg *agg); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_rx_agg_cfg_8852b + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_rx_agg_cfg_8852b(struct mac_ax_adapter *adapter, + struct mac_ax_rx_agg_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief usb_pwr_switch_8852b + * + * @param *vadapter + * @param pre_switch + * @param on + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_pwr_switch_8852b(void *vadapter, + u8 pre_switch, u8 on); +/** + * @} + * @} + */ + +/** + * @addtogroup HCI + * @{ + * @addtogroup USB + * @{ + */ + +/** + * @brief set_usb_wowlan_8852b + * + * @param *adapter + * @param w_c + * @return Please Place Description here. + * @retval u32 + */ +u32 set_usb_wowlan_8852b(struct mac_ax_adapter *adapter, + enum mac_ax_wow_ctrl w_c); +/** + * @} + * @} + */ + +/** + * @brief usb_get_txagg_num_88852b + * + * @param *adapter + * @param band + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_get_txagg_num_8852b(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + * @} + */ + +/** + * @brief usb_get_rx_state_8852b + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 usb_get_rx_state_8852b(struct mac_ax_adapter *adapter, u32 *val); +/** + * @} + * @} + */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.c b/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.c new file mode 100644 index 0000000..083df80 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.c @@ -0,0 +1,1913 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "../gpio_cmd.h" +#include "../gpio.h" +#include "../../mac_reg.h" +#include "gpio_8852b.h" + +/* GPIO0 definition */ +#define GPIO0_BT_GPIO0_8852B \ + {MAC_AX_SWGPIO, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \ + 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define GPIO0_BT_SDIO_INT_8852B \ + {MAC_AX_BT_SDIO_INT, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(5), BIT(5)} +#define GPIO0_USIN_8852B \ + {MAC_AX_SWGPIO, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO0_BT_ANT_SW0_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO0_BT_ACT_8852B \ + {MAC_AX_BT_PTA, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \ + 0x41, BIT(1), BIT(1)} +#define GPIO0_WL_ACT_8852B \ + {MAC_AX_WL_PTA, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO0_WLMAC_DBG_GPIO0_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO0_WLPHY_DBG_GPIO0_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO0_BT_DBG_GPIO0_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO0_PAON_2G_S0_8852B \ + {MAC_AX_PAON_LNAON_2G_S0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \ + 0x142, BIT(0), BIT(0)} +#define GPIO0_WL_RFE_CTRL0_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \ + 0x142, BIT(1), BIT(1)} +#define GPIO0_PAON_5G_S0_8852B \ + {MAC_AX_PAON_LNAON_5G_S0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \ + 0x142, BIT(4), BIT(4)} +#define GPIO0_WL_RFE_CTRL0_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_2, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \ + 0x142, BIT(5), BIT(5)} +#define GPIO0_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO1 definition */ +#define GPIO1_BT_GPIO1_8852B \ + {MAC_AX_SWGPIO, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \ + 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define GPIO1_USOUT_8852B \ + {MAC_AX_UART, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x66, BIT(6), BIT(6)} +#define GPIO1_BT_ANT_SW1_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO1_BT_3DD_SYNC_8852B \ + {MAC_AX_BT_3DDLS_A, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \ + 0x22, BIT(2), BIT(2)} +#define GPIO1_WL_CK_8852B \ + {MAC_AX_BT_PTA, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x41, BIT(1), BIT(1)} +#define GPIO1_BT_CK_8852B \ + {MAC_AX_WL_PTA, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO1_WLMAC_DBG_GPIO1_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO1_WLPHY_DBG_GPIO1_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO1_BT_DBG_GPIO1_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO1_LNAON_2G_S0_8852B \ + {MAC_AX_PAON_LNAON_2G_S0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \ + 0x142, BIT(0), BIT(0)} +#define GPIO1_WL_RFE_CTRL1_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \ + 0x142, BIT(1), BIT(1)} +#define GPIO1_LNAON_5G_S0_8852B \ + {MAC_AX_PAON_LNAON_5G_S0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \ + 0x142, BIT(4), BIT(4)} +#define GPIO1_WL_RFE_CTRL1_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_2, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \ + 0x142, BIT(5), BIT(5)} +#define GPIO1_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO2 definition */ +#define GPIO2_BT_GPIO2_8852B \ + {MAC_AX_SWGPIO, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \ + 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define GPIO2_BT_WAKE_8852B \ + {MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \ + 0x4E, BIT(6), BIT(6)} +#define GPIO2_BT_ANT_SW2_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO2_WL_STATE_8852B \ + {MAC_AX_BT_PTA, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \ + 0x41, BIT(1), BIT(1)} +#define GPIO2_BT_STATE_8852B \ + {MAC_AX_WL_PTA, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO2_WLMAC_DBG_GPIO2_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO2_WLPHY_DBG_GPIO2_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO2_BT_DBG_GPIO2_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO2_PAON_2G_S1_8852B \ + {MAC_AX_PAON_LNAON_2G_S1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \ + 0x142, BIT(2), BIT(2)} +#define GPIO2_WL_RFE_CTRL2_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \ + 0x142, BIT(3), BIT(3)} +#define GPIO2_PAON_5G_S1_8852B \ + {MAC_AX_PAON_LNAON_5G_S1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \ + 0x142, BIT(6), BIT(6)} +#define GPIO2_WL_RFE_CTRL2_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_3, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \ + 0x142, BIT(7), BIT(7)} +#define GPIO2_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO3 definition */ +#define GPIO3_BT_GPIO3_8852B \ + {MAC_AX_SWGPIO, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \ + 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define GPIO3_UART_WAKE_8852B \ + {MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x4E, BIT(6), BIT(6)} +#define GPIO3_BT_ANT_SW3_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO3_WL_PRI_8852B \ + {MAC_AX_BT_PTA, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x41, BIT(1), BIT(1)} +#define GPIO3_BT_PRI_8852B \ + {MAC_AX_WL_PTA, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO3_WLMAC_DBG_GPIO3_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO3_WLPHY_DBG_GPIO3_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO3_BT_DBG_GPIO3_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO3_LNAON_2G_S1_8852B \ + {MAC_AX_PAON_LNAON_2G_S1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \ + 0x142, BIT(2), BIT(2)} +#define GPIO3_WL_RFE_CTRL3_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \ + 0x142, BIT(3), BIT(3)} +#define GPIO3_LNAON_5G_S1_8852B \ + {MAC_AX_PAON_LNAON_5G_S1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \ + 0x142, BIT(6), BIT(6)} +#define GPIO3_WL_RFE_CTRL3_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_3, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \ + 0x142, BIT(7), BIT(7)} +#define GPIO3_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO4 definition */ +#define GPIO4_BT_SPI0_8852B \ + {MAC_AX_BT_SFALSH, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO4_WL_SPI0_8852B \ + {MAC_AX_WL_SFALSH, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO4_BT_JTAG_TRST_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \ + 0x67, BIT(0), BIT(0)} +#define GPIO4_WL_JTAG_TRST_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \ + 0x65, BIT(7), BIT(7)} +#define GPIO4_DBG_GNT_WL_8852B \ + {MAC_AX_DBG_GNT, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO4_WLMAC_DBG_GPIO4_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO4_WLPHY_DBG_GPIO4_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO4_BT_DBG_GPIO4_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO4_BANDSEL_5_6G_8852B \ + {MAC_AX_BANDSEL_5_6G, MAC_AX_GPIO4, MAC_AX_GPIO_IN, \ + 0x143, BIT(4), BIT(4)} +#define GPIO4_WL_RFE_CTRL4_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_4, MAC_AX_GPIO4, MAC_AX_GPIO_IN, \ + 0x144, BIT(4), BIT(4)} +#define GPIO4_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO5 definition */ +#define GPIO5_BT_SPI1_8852B \ + {MAC_AX_BT_SFALSH, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO5_WL_SPI1_8852B \ + {MAC_AX_WL_SFALSH, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO5_BT_JTAG_TDI_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO5_WL_JTAG_TDI_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x65, BIT(7), BIT(7)} +#define GPIO5_DBG_GNT_BT_8852B \ + {MAC_AX_DBG_GNT, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO5_BT_GPIO18_8852B \ + {MAC_AX_BT_GPIO18, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \ + 0x67, BIT(1), BIT(1)} +#define GPIO5_SOUT_8852B \ + {MAC_AX_WL_UART_TX, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x41, BIT(0), BIT(0)} +#define GPIO5_WLMAC_DBG_GPIO5_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO5_WLPHY_DBG_GPIO5_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO5_BT_DBG_GPIO5_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO5_I2C_INT_3W_8852B \ + {MAC_AX_MAILBOX_3W, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x4F, BIT(4), BIT(4)} +#define GPIO5_I2C_INT_1W_8852B \ + {MAC_AX_MAILBOX_1W, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x4F, BIT(7), BIT(7)} +#define GPIO5_BANDSEL_5_6G_8852B \ + {MAC_AX_BANDSEL_5_6G, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x143, BIT(4), BIT(4)} +#define GPIO5_WL_RFE_CTRL5_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_4, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \ + 0x144, BIT(4), BIT(4)} +#define GPIO5_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO6 definition */ +#define GPIO6_BT_SPI2_8852B \ + {MAC_AX_BT_SFALSH, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO6_WL_SPI2_8852B \ + {MAC_AX_WL_SFALSH, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO6_BT_JTAG_TDO_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x67, BIT(0), BIT(0)} +#define GPIO6_WL_JTAG_TDO_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x65, BIT(7), BIT(7)} +#define GPIO6_LTE_UART_IN_8852B \ + {MAC_AX_LTE_UART, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x73, BIT(2), BIT(2)} +#define GPIO6_LTE_3W_RX_IN_8852B \ + {MAC_AX_LTE_3W, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x73, BIT(2), BIT(2)} +#define GPIO6_BT_3DD_SYNC_8852B \ + {MAC_AX_BT_3DDLS_B, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x67, BIT(1), BIT(1)} +#define GPIO6_SIN_8852B \ + {MAC_AX_WL_UART_RX, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x40, BIT(2), BIT(2)} +#define GPIO6_WLMAC_DBG_GPIO6_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO6_WLPHY_DBG_GPIO6_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO6_BT_DBG_GPIO6_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO6_PAON_6G_S1_8852B \ + {MAC_AX_PAON_LNAON_6G_S1, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x143, BIT(2), BIT(2)} +#define GPIO6_WL_RFE_CTRL6_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_7, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x144, BIT(4), BIT(4)} +#define GPIO6_BANDSEL_5G_8852B \ + {MAC_AX_BANDSEL_5G, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x143, BIT(2), BIT(2)} +#define GPIO6_WL_RFE_CTRL6_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_8, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \ + 0x145, BIT(0), BIT(0)} +#define GPIO6_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO6, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO7 definition */ +#define GPIO7_BT_SPI3_8852B \ + {MAC_AX_BT_SFALSH, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO7_WL_SPI3_8852B \ + {MAC_AX_WL_SFALSH, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO7_BT_JTAG_TMS_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO7_WL_JTAG_TMS_8852B \ + {MAC_AX_BT_JTAG, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x65, BIT(7), BIT(7)} +#define GPIO7_LTE_UART_OUT_8852B \ + {MAC_AX_LTE_UART, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x73, BIT(2), BIT(2)} +#define GPIO7_LTE_3W_TX_IN_8852B \ + {MAC_AX_LTE_3W, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x73, BIT(2), BIT(2)} +#define GPIO7_BT_GPIO16_8852B \ + {MAC_AX_BT_GPIO16, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \ + 0x67, BIT(2), BIT(2)} +#define GPIO7_SOUT_8852B \ + {MAC_AX_WL_UART_TX, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \ + 0x41, BIT(0), BIT(0)} +#define GPIO7_WLMAC_DBG_GPIO7_8852B \ + {MAC_AX_WLMAC_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO7_WLPHY_DBG_GPIO7_8852B \ + {MAC_AX_WLPHY_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO7_BT_DBG_GPIO7_8852B \ + {MAC_AX_BT_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define GPIO7_LNAON_6G_S1_8852B \ + {MAC_AX_PAON_LNAON_6G_S1, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x143, BIT(2), BIT(2)} +#define GPIO7_WL_RFE_CTRL7_0_8852B \ + {MAC_AX_RFE_WLBT_FUNC_7, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x144, BIT(4), BIT(4)} +#define GPIO7_BANDSEL_5G_8852B \ + {MAC_AX_BANDSEL_5G, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x143, BIT(2), BIT(2)} +#define GPIO7_WL_RFE_CTRL7_1_8852B \ + {MAC_AX_RFE_WLBT_FUNC_8, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \ + 0x145, BIT(0), BIT(0)} +#define GPIO7_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO8 definition */ +#define GPIO8_EXT_WOL_8852B \ + {MAC_AX_WL_HW_EXTWOL, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \ + 0x4A, BIT(0), BIT(0)} +#define GPIO8_SICK_8852B \ + {MAC_AX_SIC, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \ + 0x41, BIT(4), BIT(4)} +#define GPIO8_WL_LED_8852B \ + {MAC_AX_WL_LED, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \ + 0x4E, BIT(5), BIT(5)} +#define GPIO8_SOUT_8852B \ + {MAC_AX_WL_UART_TX, MAC_AX_GPIO8, MAC_AX_GPIO_OUT, \ + 0x41, BIT(0), BIT(0)} +#define GPIO8_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO8, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO9 definition */ +#define GPIO9_DIS_WL_N_8852B \ + {MAC_AX_WL_HWPDN, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \ + 0x68, BIT(3), BIT(3)} +#define GPIO9_EXT_WOL_8852B \ + {MAC_AX_WL_HW_EXTWOL, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \ + 0x4A, BIT(0), BIT(0)} +#define GPIO9_USIN_8852B \ + {MAC_AX_UART, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO9_I2C_SD_8852B \ + {MAC_AX_MAILBOX_3W, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \ + 0x4F, BIT(4), BIT(4)} +#define GPIO9_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO9, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO10 definition */ +#define GPIO10_WL_SDIO_INT_8852B \ + {MAC_AX_WL_SDIO_INT, MAC_AX_GPIO10, MAC_AX_GPIO_OUT, \ + 0x72, BIT(2), BIT(2)} +#define GPIO10_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO10, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO11 definition */ +#define GPIO11_DIS_BT_N_8852B \ + {MAC_AX_BT_HWPDN, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \ + 0x6A, BIT(3), BIT(3)} +#define GPIO11_USOUT_8852B \ + {MAC_AX_UART, MAC_AX_GPIO11, MAC_AX_GPIO_OUT, \ + 0x66, BIT(6), BIT(6)} +#define GPIO11_BANDSEL_5G_G7G6_8852B \ + {MAC_AX_BANDSEL_5G_G7G6, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \ + 0x143, BIT(6), BIT(6)} +#define GPIO11_WL_RFE_CTRL11_8852B \ + {MAC_AX_RFE_WLBT_FUNC_5, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \ + 0x144, BIT(5), BIT(5)} +#define GPIO11_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO11, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO12 definition */ +#define GPIO12_USCTS_8852B \ + {MAC_AX_UART, MAC_AX_GPIO12, MAC_AX_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO12_LTE_PRI_OUT_8852B \ + {MAC_AX_LTE_3W, MAC_AX_GPIO12, MAC_AX_GPIO_OUT, \ + 0x73, BIT(2), BIT(2)} +#define GPIO12_I2C_CLK_8852B \ + {MAC_AX_MAILBOX_3W, MAC_AX_GPIO12, MAC_AX_GPIO_IN, \ + 0x4F, BIT(4), BIT(4)} +#define GPIO12_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO12, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO13 definition */ +#define GPIO13_BT_WAKE_8852B \ + {MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO13, MAC_AX_GPIO_IN, \ + 0x4E, BIT(6), BIT(6)} +#define GPIO13_BT_ANT_SW0_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO13, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO13_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO13, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO14 definition */ +#define GPIO14_UART_WAKE_8852B \ + {MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \ + 0x4E, BIT(6), BIT(6)} +#define GPIO14_BT_ANT_SW1_8852B \ + {MAC_AX_BT_RF, MAC_AX_GPIO14, MAC_AX_GPIO_OUT, \ + 0x4F, BIT(6), BIT(6)} +#define GPIO14_SIN_8852B \ + {MAC_AX_WL_UART_RX, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \ + 0x40, BIT(2), BIT(2)} +#define GPIO14_BANDSEL_5G_G7G6_8852B \ + {MAC_AX_BANDSEL_5G_G7G6, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \ + 0x143, BIT(6), BIT(6)} +#define GPIO14_WL_RFE_CTRL11_8852B \ + {MAC_AX_RFE_WLBT_FUNC_5, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \ + 0x144, BIT(5), BIT(5)} +#define GPIO14_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO14, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO15 definition */ +#define GPIO15_EXT_XTAL_EN_8852B \ + {MAC_AX_EXT_XTAL_CLK, MAC_AX_GPIO15, MAC_AX_GPIO_IN, \ + 0x66, BIT(7), BIT(7)} +#define GPIO15_SW_IO_8852B \ + {MAC_AX_SW_IO, MAC_AX_GPIO15, MAC_AX_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO0_8852B[] = { + GPIO0_BT_GPIO0_8852B, + GPIO0_BT_SDIO_INT_8852B, + GPIO0_USIN_8852B, + GPIO0_BT_ANT_SW0_8852B, + GPIO0_BT_ACT_8852B, + GPIO0_WL_ACT_8852B, + GPIO0_WLMAC_DBG_GPIO0_8852B, + GPIO0_WLPHY_DBG_GPIO0_8852B, + GPIO0_BT_DBG_GPIO0_8852B, + GPIO0_PAON_2G_S0_8852B, + GPIO0_WL_RFE_CTRL0_0_8852B, + GPIO0_PAON_5G_S0_8852B, + GPIO0_WL_RFE_CTRL0_1_8852B, + GPIO0_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO1_8852B[] = { + GPIO1_BT_GPIO1_8852B, + GPIO1_USOUT_8852B, + GPIO1_BT_ANT_SW1_8852B, + GPIO1_BT_3DD_SYNC_8852B, + GPIO1_WL_CK_8852B, + GPIO1_BT_CK_8852B, + GPIO1_WLMAC_DBG_GPIO1_8852B, + GPIO1_WLPHY_DBG_GPIO1_8852B, + GPIO1_BT_DBG_GPIO1_8852B, + GPIO1_LNAON_2G_S0_8852B, + GPIO1_WL_RFE_CTRL1_0_8852B, + GPIO1_LNAON_5G_S0_8852B, + GPIO1_WL_RFE_CTRL1_1_8852B, + GPIO1_SW_IO_8852B, + GPIO1_BT_3DD_SYNC_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO2_8852B[] = { + GPIO2_BT_GPIO2_8852B, + GPIO2_BT_WAKE_8852B, + GPIO2_BT_ANT_SW2_8852B, + GPIO2_WL_STATE_8852B, + GPIO2_BT_STATE_8852B, + GPIO2_WLMAC_DBG_GPIO2_8852B, + GPIO2_WLPHY_DBG_GPIO2_8852B, + GPIO2_BT_DBG_GPIO2_8852B, + GPIO2_PAON_2G_S1_8852B, + GPIO2_WL_RFE_CTRL2_0_8852B, + GPIO2_PAON_5G_S1_8852B, + GPIO2_WL_RFE_CTRL2_1_8852B, + GPIO2_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO3_8852B[] = { + GPIO3_BT_GPIO3_8852B, + GPIO3_UART_WAKE_8852B, + GPIO3_BT_ANT_SW3_8852B, + GPIO3_WL_PRI_8852B, + GPIO3_BT_PRI_8852B, + GPIO3_WLMAC_DBG_GPIO3_8852B, + GPIO3_WLPHY_DBG_GPIO3_8852B, + GPIO3_BT_DBG_GPIO3_8852B, + GPIO3_LNAON_2G_S1_8852B, + GPIO3_WL_RFE_CTRL3_0_8852B, + GPIO3_LNAON_5G_S1_8852B, + GPIO3_WL_RFE_CTRL3_1_8852B, + GPIO3_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO4_8852B[] = { + GPIO4_BT_SPI0_8852B, + GPIO4_WL_SPI0_8852B, + GPIO4_BT_JTAG_TRST_8852B, + GPIO4_WL_JTAG_TRST_8852B, + GPIO4_DBG_GNT_WL_8852B, + GPIO4_WLMAC_DBG_GPIO4_8852B, + GPIO4_WLPHY_DBG_GPIO4_8852B, + GPIO4_BT_DBG_GPIO4_8852B, + GPIO4_BANDSEL_5_6G_8852B, + GPIO4_WL_RFE_CTRL4_0_8852B, + GPIO4_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO5_8852B[] = { + GPIO5_BT_SPI1_8852B, + GPIO5_WL_SPI1_8852B, + GPIO5_BT_JTAG_TDI_8852B, + GPIO5_WL_JTAG_TDI_8852B, + GPIO5_DBG_GNT_BT_8852B, + GPIO5_BT_GPIO18_8852B, + GPIO5_SOUT_8852B, + GPIO5_WLMAC_DBG_GPIO5_8852B, + GPIO5_WLPHY_DBG_GPIO5_8852B, + GPIO5_BT_DBG_GPIO5_8852B, + GPIO5_I2C_INT_3W_8852B, + GPIO5_I2C_INT_1W_8852B, + GPIO5_BANDSEL_5_6G_8852B, + GPIO5_WL_RFE_CTRL5_0_8852B, + GPIO5_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO6_8852B[] = { + GPIO6_BT_SPI2_8852B, + GPIO6_WL_SPI2_8852B, + GPIO6_BT_JTAG_TDO_8852B, + GPIO6_WL_JTAG_TDO_8852B, + GPIO6_LTE_UART_IN_8852B, + GPIO6_LTE_3W_RX_IN_8852B, + GPIO6_SIN_8852B, + GPIO6_WLMAC_DBG_GPIO6_8852B, + GPIO6_WLPHY_DBG_GPIO6_8852B, + GPIO6_BT_DBG_GPIO6_8852B, + GPIO6_PAON_6G_S1_8852B, + GPIO6_WL_RFE_CTRL6_0_8852B, + GPIO6_BANDSEL_5G_8852B, + GPIO6_WL_RFE_CTRL6_1_8852B, + GPIO6_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO7_8852B[] = { + GPIO7_BT_SPI3_8852B, + GPIO7_WL_SPI3_8852B, + GPIO7_BT_JTAG_TMS_8852B, + GPIO7_WL_JTAG_TMS_8852B, + GPIO7_LTE_UART_OUT_8852B, + GPIO7_LTE_3W_TX_IN_8852B, + GPIO7_BT_GPIO16_8852B, + GPIO7_SOUT_8852B, + GPIO7_WLMAC_DBG_GPIO7_8852B, + GPIO7_WLPHY_DBG_GPIO7_8852B, + GPIO7_BT_DBG_GPIO7_8852B, + GPIO7_LNAON_6G_S1_8852B, + GPIO7_WL_RFE_CTRL7_0_8852B, + GPIO7_BANDSEL_5G_8852B, + GPIO7_WL_RFE_CTRL7_1_8852B, + GPIO7_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO8_8852B[] = { + GPIO8_EXT_WOL_8852B, + GPIO8_SICK_8852B, + GPIO8_WL_LED_8852B, + GPIO8_SOUT_8852B, + GPIO8_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO9_8852B[] = { + GPIO9_DIS_WL_N_8852B, + GPIO9_EXT_WOL_8852B, + GPIO9_USIN_8852B, + GPIO9_I2C_SD_8852B, + GPIO9_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO10_8852B[] = { + GPIO10_WL_SDIO_INT_8852B, + GPIO10_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO11_8852B[] = { + GPIO11_DIS_BT_N_8852B, + GPIO11_USOUT_8852B, + GPIO11_BANDSEL_5G_G7G6_8852B, + GPIO11_WL_RFE_CTRL11_8852B, + GPIO11_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO12_8852B[] = { + GPIO12_USCTS_8852B, + GPIO12_LTE_PRI_OUT_8852B, + GPIO12_I2C_CLK_8852B, + GPIO12_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO13_8852B[] = { + GPIO13_BT_WAKE_8852B, + GPIO13_BT_ANT_SW0_8852B, + GPIO13_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO14_8852B[] = { + GPIO14_UART_WAKE_8852B, + GPIO14_BT_ANT_SW1_8852B, + GPIO14_SIN_8852B, + GPIO14_BANDSEL_5G_G7G6_8852B, + GPIO14_WL_RFE_CTRL11_8852B, + GPIO14_SW_IO_8852B, +}; + +static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO15_8852B[] = { + GPIO15_EXT_XTAL_EN_8852B, + GPIO15_SW_IO_8852B, +}; + +#define PINMUX_GPIO0_BT_GPIO0_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO0_LTE_UART_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define PINMUX_GPIO0_LTE_UART_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO0_LTE_UART_IN_DIS_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO0_LTE_3W_RX_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define PINMUX_GPIO0_LTE_3W_RX_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO0_LTE_3W_RX_IN_DIS_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO0_WL_ACT_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO0_WL_ACT_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO0_BT_ACT_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO0_BT_ACT_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO0_DBG_GNT_WL_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)} +#define PINMUX_GPIO0_WL_JTAG_TRST_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO0_WL_JTAG_TRST_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO0_WL_JTAG_TRST_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO0_WL_JTAG_TRST_DIS_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO0_WL_RFE_CTRL0_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO0_DBG0_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO0_SW_IO0_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO1_BT_GPIO1_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO1_LTE_UART_OUT_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5) | BIT(4)} +#define PINMUX_GPIO1_LTE_UART_OUT_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO1_LTE_3W_TX_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6)} +#define PINMUX_GPIO1_LTE_3W_TX_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO1_LTE_3W_TX_IN_DIS_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO1_BT_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO1_BT_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO1_WL_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO1_WL_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO1_DBG_GNT_BT_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO1_WL_JTAG_TDI_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO1_WL_JTAG_TDI_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO1_WL_JTAG_TDI_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO1_WL_JTAG_TDI_DIS_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO1_WL_RFE_CTRL1_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO1_DBG1_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO1_SW_IO1_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D0, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO2_WL_PD_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), 0} +#define PINMUX_GPIO2_WL_PD_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x68, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO2_WL_PD_DIS_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO2_WL_PD_DIS_2_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO2_BT_GPIO2_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO2_LTE_3W_PRI_OUT_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define PINMUX_GPIO2_LTE_3W_PRI_OUT_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO2_BT_STA_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO2_BT_STA_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO2_WL_STA_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO2_WL_STA_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO2_DBG_GNT_WL_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)} +#define PINMUX_GPIO2_WL_JTAG_TDO_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO2_WL_JTAG_TDO_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO2_WL_JTAG_TDO_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO2_WL_JTAG_TDO_DIS_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO2_WL_RFE_CTRL2_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO2_DBG2_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO2_SW_IO02_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D1, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO3_BT_PD_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), 0} +#define PINMUX_GPIO3_BT_PD_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x6A, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO3_BT_GPIO3_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO3_BT_PRI_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO3_BT_PRI_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO3_WL_PRI_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO3_WL_PRI_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO3_DBG_GNT_BT_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO3_WL_JTAG_TMS_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO3_WL_JTAG_TMS_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO3_WL_JTAG_TMS_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO3_WL_JTAG_TMS_DIS_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO3_WL_RFE_CTRL3_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO3_DBG3_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO3_SW_IO3_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D1, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO4_BT_GPIO4_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO4_WL_FLASH0_PINEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO4_WL_FLASH0_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x42, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO4_BT_FLASH0_PINEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO4_BT_FLASH0_SECEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO4_BT_FLASH0_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x66, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO4_WL_JTAG_TRST_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO4_WL_JTAG_TRST_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO4_WL_JTAG_TRST_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO4_WL_RFE_CTRL4_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO4_DBG4_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO4_SW_IO04_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D2, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO5_BT_GPIO5_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO5_WL_FLASH1_PINEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)} +#define PINMUX_GPIO5_WL_FLASH1_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x42, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO5_BT_FLASH1_PINEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)} +#define PINMUX_GPIO5_BT_FLASH1_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x66, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO5_BT_FLASH1_SECEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO5_MAILBOX_I2C_INT_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO5_MAILBOX_I2C_INT_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO5_XTAL_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_XTAL_CLK, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO5_XTAL_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_XTAL_CLK, 0x4F, \ + BIT(5), BIT(5)} +#define PINMUX_GPIO5_WL_JTAG_TDI_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO5_WL_JTAG_TDI_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO5_WL_JTAG_TDI_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO5_WL_RFE_CTRL5_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO5_DBG5_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO5_SW_IO5_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D2, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO6_BT_PD_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), 0} +#define PINMUX_GPIO6_BT_PD_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x6A, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO6_BT_GPIO6_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO6_WL_FLASH2_PINEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO6_WL_FLASH2_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x42, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO6_BT_FLASH2_PINEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO6_BT_FLASH2_SECEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO6_BT_FLASH2_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x66, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO6_LTE_UART_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1) | BIT(0)} +#define PINMUX_GPIO6_LTE_UART_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO6_LTE_3W_RX_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)} +#define PINMUX_GPIO6_LTE_3W_RX_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO6_MAILBOX_I2C_SD_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO6_MAILBOX_I2C_SD_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO6_DBG_GNT_WL_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)} +#define PINMUX_GPIO6_WL_JTAG_TDO_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO6_WL_JTAG_TDO_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO6_WL_JTAG_TDO_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO6_WL_RFE6_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO6_DBG_GPIO6_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO6_SW_IO6_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D3, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO7_BT_PD_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), 0} +#define PINMUX_GPIO7_BT_PD_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x6A, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO7_BT_GPIO7_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO7_WL_FLASH3_PINEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)} +#define PINMUX_GPIO7_WL_FLASH3_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_FLASH, 0x42, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO7_BT_FLASH3_PINEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)} +#define PINMUX_GPIO7_BT_FLASH3_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0x66, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO7_BT_FLASH3_SECEN_8852B \ + {RTW_MAC_GPIO_BT_FLASH, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO7_LTE_UART_OUT_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5) | BIT(4)} +#define PINMUX_GPIO7_LTE_UART_OUT_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_UART, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO7_LTE_3W_TX_IN_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6)} +#define PINMUX_GPIO7_LTE_3W_TX_IN_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO7_MAILBOX_I2C_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO7_MAILBOX_I2C_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO7_DBG_GNT_BT_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO7_WL_JTAG_TMS_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO7_WL_JTAG_TMS_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO7_WL_JTAG_TMS_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO7_WL_RFE_CTRL7_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO7_DBG7_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO7_SW_IO7_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D3, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO8_EXT_WOL_PINEN_8852B \ + {RTW_MAC_GPIO_WL_EXTWOL, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), 0} +#define PINMUX_GPIO8_EXT_WOL_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_EXTWOL, 0x4A, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO8_BT_GPIO8_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO8_SIC_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_SIC, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO8_SIC_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_SIC, 0x41, \ + BIT(4) | BIT(3), BIT(4) | BIT(3)} +#define PINMUX_GPIO8_SIC_CLK_SECEN_8852B \ + {RTW_MAC_GPIO_SIC, 0xC00, \ + BIT(1), BIT(1)} +#define PINMUX_GPIO8_MAILBOX_I2C_INT_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO8_MAILBOX_I2C_INT_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO8_WL_LED_PINEN_8852B \ + {RTW_MAC_GPIO_WL_LED, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)} +#define PINMUX_GPIO8_WL_LED_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_LED, 0x4E, \ + BIT(5), BIT(5)} +#define PINMUX_GPIO8_WL_UART_TX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO8_WL_UART_TX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x41, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO8_WL_UART_TX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0xC00, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO8_WL_RFE8_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO8_DBG_GPIO8_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO8_SW_IO8_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D4, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO9_WL_PD_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), 0} +#define PINMUX_GPIO9_BT_GPIO9_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO9_MAILBOX_I2C_SD_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO9_MAILBOX_I2C_SD_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO9_DBG_GNT_WL_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO9_WL_UART_TX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO9_WL_UART_TX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x41, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO9_WL_UART_TX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0xC00, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO9_WL_RFE_CTRL9_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO9_DBG9_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO9_SW_IO9_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D4, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO10_BT_GPIO10_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO10_WL_SDIO_INT_PINEN_8852B \ + {RTW_MAC_GPIO_WL_SDIO_INT, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO10_WL_UART_RX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO10_WL_UART_RX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x40, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO10_WL_UART_RX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0xC00, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO10_WL_UART_RX_DIS_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO10_WL_UART_RX_DIS_2_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO10_WL_RFE10_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO10_DBG_GPIO10_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO10_SW_IO10_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO11_BT_PD_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PD, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), 0} +#define PINMUX_GPIO11_BT_GPIO11_PINEN_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO11_MAILBOX_I2C_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO11_MAILBOX_I2C_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_MAILBOX, 0x4F, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO11_DBG_GNT_BT_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)} +#define PINMUX_GPIO11_WL_UART_RX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO11_WL_UART_RX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0xC00, \ + BIT(4), BIT(4)} +#define PINMUX_GPIO11_WL_UART_RX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x40, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO11_WL_UART_RX_DIS_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO11_WL_UART_RX_DIS_2_8852B \ + {RTW_MAC_GPIO_WL_UART_RX, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO11_WL_RFE_CTRL11_PINEN_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO11_DBG11_PINEN_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO11_SW_IO11_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D5, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO12_BT_GPIO12_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO12_LTE_3W_PRI_OUT_PINEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)} +#define PINMUX_GPIO12_LTE_3W_PRI_OUT_FUNCEN_8852B \ + {RTW_MAC_GPIO_LTE_3W, 0x73, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO12_WL_ACT_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO12_WL_ACT_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO12_BT_ACT_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO12_BT_ACT_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO12_BT_ACT_DIS_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D0, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO12_DBG_GNT_WL_PINEN_8852B \ + {RTW_MAC_GPIO_DBG_GNT, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)} +#define PINMUX_GPIO12_SOUT_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO12_SOUT_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0xC00, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO12_SOUT_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x41, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO12_WL_RFE12_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO12_DBG_GPIO12_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO12_SW_IO12_PINEN_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D6, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO13_BT_GPIO13_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO13_WL_PTA_BT_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO13_WL_PTA_BT_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO13_BT_PTA_WL_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO13_BT_PTA_WL_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO13_WL_UART_TX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO13_WL_UART_TX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0xC00, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO13_WL_UART_TX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x41, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO13_WL_RFE_CTRL13_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO13_DBG13_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO13_SW_IO13_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D6, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO14_BT_GPIO14_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)} +#define PINMUX_GPIO14_WL_PTA_BT_STA_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO14_WL_PTA_BT_STA_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO14_BT_PTA_WL_STA_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)} +#define PINMUX_GPIO14_BT_PTA_WL_STA_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO14_WL_JTAG_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)} +#define PINMUX_GPIO14_WL_JTAG_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0x65, \ + BIT(7), BIT(7)} +#define PINMUX_GPIO14_WL_JTAG_CLK_SECEN_8852B \ + {RTW_MAC_GPIO_WL_JTAG, 0xC00, \ + BIT(2), BIT(2)} +#define PINMUX_GPIO14_WL_RFE_CTRL13_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} +#define PINMUX_GPIO14_DBG14_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)} +#define PINMUX_GPIO14_SW_IO14_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D7, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)} + +#define PINMUX_GPIO15_WL_PD_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PD, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), 0} +#define PINMUX_GPIO15_BT_GPIO15_8852B \ + {RTW_MAC_GPIO_BT_GPIO, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)} +#define PINMUX_GPIO15_WL_PTA_BT_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO15_WL_PTA_BT_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2)} +#define PINMUX_GPIO15_BT_PTA_WL_CLK_PINEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)} +#define PINMUX_GPIO15_BT_PTA_WL_CLK_FUNCEN_8852B \ + {RTW_MAC_GPIO_BT_PTA, 0x41, \ + BIT(2) | BIT(1), BIT(2) | BIT(1)} +#define PINMUX_GPIO15_WL_UART_TX_PINEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)} +#define PINMUX_GPIO15_WL_UART_TX_SECEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0xC00, \ + BIT(3), BIT(3)} +#define PINMUX_GPIO15_WL_UART_TX_FUNCEN_8852B \ + {RTW_MAC_GPIO_WL_UART_TX, 0x41, \ + BIT(0), BIT(0)} +#define PINMUX_GPIO15_WL_RFE_CTRL15_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} +#define PINMUX_GPIO15_DBG15_8852B \ + {RTW_MAC_GPIO_DBG, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)} +#define PINMUX_GPIO15_SW_IO15_8852B \ + {RTW_MAC_GPIO_SW_IO, 0x2D7, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)} + +#define PINMUX_GPIO16_WL_RFE_CTRL16_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D8, \ + BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)} + +#define PINMUX_GPIO17_WL_RFE_CTRL17_8852B \ + {RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D8, \ + BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)} + +#define PINMUX_GPIO_END_8852B \ + {RTW_MAC_GPIO_INVALID, 0, 0, 0} + +static const struct mac_ax_pin_list PIN_LIST_GPIO0_8852B[] = { + PINMUX_GPIO0_BT_GPIO0_PINEN_8852B, + PINMUX_GPIO0_LTE_UART_IN_PINEN_8852B, + PINMUX_GPIO0_LTE_UART_IN_FUNCEN_8852B, + PINMUX_GPIO0_LTE_UART_IN_DIS_8852B, + PINMUX_GPIO0_LTE_3W_RX_IN_PINEN_8852B, + PINMUX_GPIO0_LTE_3W_RX_IN_FUNCEN_8852B, + PINMUX_GPIO0_LTE_3W_RX_IN_DIS_8852B, + PINMUX_GPIO0_WL_ACT_PINEN_8852B, + PINMUX_GPIO0_WL_ACT_FUNCEN_8852B, + PINMUX_GPIO0_BT_ACT_PINEN_8852B, + PINMUX_GPIO0_BT_ACT_FUNCEN_8852B, + PINMUX_GPIO0_DBG_GNT_WL_PINEN_8852B, + PINMUX_GPIO0_WL_JTAG_TRST_PINEN_8852B, + PINMUX_GPIO0_WL_JTAG_TRST_FUNCEN_8852B, + PINMUX_GPIO0_WL_JTAG_TRST_SECEN_8852B, + PINMUX_GPIO0_WL_JTAG_TRST_DIS_8852B, + PINMUX_GPIO0_WL_RFE_CTRL0_PINEN_8852B, + PINMUX_GPIO0_DBG0_PINEN_8852B, + PINMUX_GPIO0_SW_IO0_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO1_8852B[] = { + PINMUX_GPIO1_BT_GPIO1_PINEN_8852B, + PINMUX_GPIO1_LTE_UART_OUT_PINEN_8852B, + PINMUX_GPIO1_LTE_UART_OUT_FUNCEN_8852B, + PINMUX_GPIO1_LTE_3W_TX_IN_PINEN_8852B, + PINMUX_GPIO1_LTE_3W_TX_IN_FUNCEN_8852B, + PINMUX_GPIO1_LTE_3W_TX_IN_DIS_8852B, + PINMUX_GPIO1_BT_CLK_PINEN_8852B, + PINMUX_GPIO1_BT_CLK_FUNCEN_8852B, + PINMUX_GPIO1_WL_CLK_PINEN_8852B, + PINMUX_GPIO1_WL_CLK_FUNCEN_8852B, + PINMUX_GPIO1_DBG_GNT_BT_PINEN_8852B, + PINMUX_GPIO1_WL_JTAG_TDI_PINEN_8852B, + PINMUX_GPIO1_WL_JTAG_TDI_FUNCEN_8852B, + PINMUX_GPIO1_WL_JTAG_TDI_SECEN_8852B, + PINMUX_GPIO1_WL_JTAG_TDI_DIS_8852B, + PINMUX_GPIO1_WL_RFE_CTRL1_PINEN_8852B, + PINMUX_GPIO1_DBG1_PINEN_8852B, + PINMUX_GPIO1_SW_IO1_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO2_8852B[] = { + PINMUX_GPIO2_WL_PD_PINEN_8852B, + PINMUX_GPIO2_WL_PD_FUNCEN_8852B, + PINMUX_GPIO2_WL_PD_DIS_8852B, + PINMUX_GPIO2_WL_PD_DIS_2_8852B, + PINMUX_GPIO2_BT_GPIO2_PINEN_8852B, + PINMUX_GPIO2_LTE_3W_PRI_OUT_PINEN_8852B, + PINMUX_GPIO2_LTE_3W_PRI_OUT_FUNCEN_8852B, + PINMUX_GPIO2_BT_STA_PINEN_8852B, + PINMUX_GPIO2_BT_STA_FUNCEN_8852B, + PINMUX_GPIO2_WL_STA_PINEN_8852B, + PINMUX_GPIO2_WL_STA_FUNCEN_8852B, + PINMUX_GPIO2_DBG_GNT_WL_PINEN_8852B, + PINMUX_GPIO2_WL_JTAG_TDO_PINEN_8852B, + PINMUX_GPIO2_WL_JTAG_TDO_FUNCEN_8852B, + PINMUX_GPIO2_WL_JTAG_TDO_SECEN_8852B, + PINMUX_GPIO2_WL_JTAG_TDO_DIS_8852B, + PINMUX_GPIO2_WL_RFE_CTRL2_PINEN_8852B, + PINMUX_GPIO2_DBG2_PINEN_8852B, + PINMUX_GPIO2_SW_IO02_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO3_8852B[] = { + PINMUX_GPIO3_BT_PD_PINEN_8852B, + PINMUX_GPIO3_BT_PD_FUNCEN_8852B, + PINMUX_GPIO3_BT_GPIO3_PINEN_8852B, + PINMUX_GPIO3_BT_PRI_PINEN_8852B, + PINMUX_GPIO3_BT_PRI_FUNCEN_8852B, + PINMUX_GPIO3_WL_PRI_PINEN_8852B, + PINMUX_GPIO3_WL_PRI_FUNCEN_8852B, + PINMUX_GPIO3_DBG_GNT_BT_PINEN_8852B, + PINMUX_GPIO3_WL_JTAG_TMS_PINEN_8852B, + PINMUX_GPIO3_WL_JTAG_TMS_FUNCEN_8852B, + PINMUX_GPIO3_WL_JTAG_TMS_SECEN_8852B, + PINMUX_GPIO3_WL_JTAG_TMS_DIS_8852B, + PINMUX_GPIO3_WL_RFE_CTRL3_PINEN_8852B, + PINMUX_GPIO3_DBG3_PINEN_8852B, + PINMUX_GPIO3_SW_IO3_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO4_8852B[] = { + PINMUX_GPIO4_BT_GPIO4_PINEN_8852B, + PINMUX_GPIO4_WL_FLASH0_PINEN_8852B, + PINMUX_GPIO4_WL_FLASH0_FUNCEN_8852B, + PINMUX_GPIO4_BT_FLASH0_PINEN_8852B, + PINMUX_GPIO4_BT_FLASH0_SECEN_8852B, + PINMUX_GPIO4_BT_FLASH0_FUNCEN_8852B, + PINMUX_GPIO4_WL_JTAG_TRST_PINEN_8852B, + PINMUX_GPIO4_WL_JTAG_TRST_FUNCEN_8852B, + PINMUX_GPIO4_WL_JTAG_TRST_SECEN_8852B, + PINMUX_GPIO4_WL_RFE_CTRL4_PINEN_8852B, + PINMUX_GPIO4_DBG4_PINEN_8852B, + PINMUX_GPIO4_SW_IO04_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO5_8852B[] = { + PINMUX_GPIO5_BT_GPIO5_PINEN_8852B, + PINMUX_GPIO5_WL_FLASH1_PINEN_8852B, + PINMUX_GPIO5_WL_FLASH1_FUNCEN_8852B, + PINMUX_GPIO5_BT_FLASH1_PINEN_8852B, + PINMUX_GPIO5_BT_FLASH1_FUNCEN_8852B, + PINMUX_GPIO5_BT_FLASH1_SECEN_8852B, + PINMUX_GPIO5_MAILBOX_I2C_INT_PINEN_8852B, + PINMUX_GPIO5_MAILBOX_I2C_INT_FUNCEN_8852B, + PINMUX_GPIO5_XTAL_CLK_PINEN_8852B, + PINMUX_GPIO5_XTAL_CLK_FUNCEN_8852B, + PINMUX_GPIO5_WL_JTAG_TDI_PINEN_8852B, + PINMUX_GPIO5_WL_JTAG_TDI_FUNCEN_8852B, + PINMUX_GPIO5_WL_JTAG_TDI_SECEN_8852B, + PINMUX_GPIO5_WL_RFE_CTRL5_PINEN_8852B, + PINMUX_GPIO5_DBG5_PINEN_8852B, + PINMUX_GPIO5_SW_IO5_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO6_8852B[] = { + PINMUX_GPIO6_BT_PD_PINEN_8852B, + PINMUX_GPIO6_BT_PD_FUNCEN_8852B, + PINMUX_GPIO6_BT_GPIO6_8852B, + PINMUX_GPIO6_WL_FLASH2_PINEN_8852B, + PINMUX_GPIO6_WL_FLASH2_FUNCEN_8852B, + PINMUX_GPIO6_BT_FLASH2_PINEN_8852B, + PINMUX_GPIO6_BT_FLASH2_SECEN_8852B, + PINMUX_GPIO6_BT_FLASH2_FUNCEN_8852B, + PINMUX_GPIO6_LTE_UART_IN_PINEN_8852B, + PINMUX_GPIO6_LTE_UART_IN_FUNCEN_8852B, + PINMUX_GPIO6_LTE_3W_RX_IN_PINEN_8852B, + PINMUX_GPIO6_LTE_3W_RX_IN_FUNCEN_8852B, + PINMUX_GPIO6_MAILBOX_I2C_SD_PINEN_8852B, + PINMUX_GPIO6_MAILBOX_I2C_SD_FUNCEN_8852B, + PINMUX_GPIO6_DBG_GNT_WL_PINEN_8852B, + PINMUX_GPIO6_WL_JTAG_TDO_PINEN_8852B, + PINMUX_GPIO6_WL_JTAG_TDO_FUNCEN_8852B, + PINMUX_GPIO6_WL_JTAG_TDO_SECEN_8852B, + PINMUX_GPIO6_WL_RFE6_8852B, + PINMUX_GPIO6_DBG_GPIO6_8852B, + PINMUX_GPIO6_SW_IO6_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO7_8852B[] = { + PINMUX_GPIO7_BT_PD_PINEN_8852B, + PINMUX_GPIO7_BT_PD_FUNCEN_8852B, + PINMUX_GPIO7_BT_GPIO7_PINEN_8852B, + PINMUX_GPIO7_WL_FLASH3_PINEN_8852B, + PINMUX_GPIO7_WL_FLASH3_FUNCEN_8852B, + PINMUX_GPIO7_BT_FLASH3_PINEN_8852B, + PINMUX_GPIO7_BT_FLASH3_FUNCEN_8852B, + PINMUX_GPIO7_BT_FLASH3_SECEN_8852B, + PINMUX_GPIO7_LTE_UART_OUT_PINEN_8852B, + PINMUX_GPIO7_LTE_UART_OUT_FUNCEN_8852B, + PINMUX_GPIO7_LTE_3W_TX_IN_PINEN_8852B, + PINMUX_GPIO7_LTE_3W_TX_IN_FUNCEN_8852B, + PINMUX_GPIO7_MAILBOX_I2C_CLK_PINEN_8852B, + PINMUX_GPIO7_MAILBOX_I2C_CLK_FUNCEN_8852B, + PINMUX_GPIO7_DBG_GNT_BT_PINEN_8852B, + PINMUX_GPIO7_WL_JTAG_TMS_PINEN_8852B, + PINMUX_GPIO7_WL_JTAG_TMS_FUNCEN_8852B, + PINMUX_GPIO7_WL_JTAG_TMS_SECEN_8852B, + PINMUX_GPIO7_WL_RFE_CTRL7_PINEN_8852B, + PINMUX_GPIO7_DBG7_PINEN_8852B, + PINMUX_GPIO7_SW_IO7_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO8_8852B[] = { + PINMUX_GPIO8_EXT_WOL_PINEN_8852B, + PINMUX_GPIO8_EXT_WOL_FUNCEN_8852B, + PINMUX_GPIO8_BT_GPIO8_8852B, + PINMUX_GPIO8_SIC_CLK_PINEN_8852B, + PINMUX_GPIO8_SIC_CLK_FUNCEN_8852B, + PINMUX_GPIO8_SIC_CLK_SECEN_8852B, + PINMUX_GPIO8_MAILBOX_I2C_INT_PINEN_8852B, + PINMUX_GPIO8_MAILBOX_I2C_INT_FUNCEN_8852B, + PINMUX_GPIO8_WL_LED_PINEN_8852B, + PINMUX_GPIO8_WL_LED_FUNCEN_8852B, + PINMUX_GPIO8_WL_UART_TX_PINEN_8852B, + PINMUX_GPIO8_WL_UART_TX_FUNCEN_8852B, + PINMUX_GPIO8_WL_UART_TX_SECEN_8852B, + PINMUX_GPIO8_WL_RFE8_8852B, + PINMUX_GPIO8_DBG_GPIO8_8852B, + PINMUX_GPIO8_SW_IO8_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO9_8852B[] = { + PINMUX_GPIO9_WL_PD_PINEN_8852B, + PINMUX_GPIO9_BT_GPIO9_PINEN_8852B, + PINMUX_GPIO9_MAILBOX_I2C_SD_PINEN_8852B, + PINMUX_GPIO9_MAILBOX_I2C_SD_FUNCEN_8852B, + PINMUX_GPIO9_DBG_GNT_WL_PINEN_8852B, + PINMUX_GPIO9_WL_UART_TX_PINEN_8852B, + PINMUX_GPIO9_WL_UART_TX_FUNCEN_8852B, + PINMUX_GPIO9_WL_UART_TX_SECEN_8852B, + PINMUX_GPIO9_WL_RFE_CTRL9_PINEN_8852B, + PINMUX_GPIO9_DBG9_PINEN_8852B, + PINMUX_GPIO9_SW_IO9_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO10_8852B[] = { + PINMUX_GPIO10_BT_GPIO10_8852B, + PINMUX_GPIO10_WL_SDIO_INT_PINEN_8852B, + PINMUX_GPIO10_WL_UART_RX_PINEN_8852B, + PINMUX_GPIO10_WL_UART_RX_FUNCEN_8852B, + PINMUX_GPIO10_WL_UART_RX_SECEN_8852B, + PINMUX_GPIO10_WL_UART_RX_DIS_8852B, + PINMUX_GPIO10_WL_UART_RX_DIS_2_8852B, + PINMUX_GPIO10_WL_RFE10_8852B, + PINMUX_GPIO10_DBG_GPIO10_8852B, + PINMUX_GPIO10_SW_IO10_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO11_8852B[] = { + PINMUX_GPIO11_BT_PD_PINEN_8852B, + PINMUX_GPIO11_BT_GPIO11_PINEN_8852B, + PINMUX_GPIO11_MAILBOX_I2C_CLK_PINEN_8852B, + PINMUX_GPIO11_MAILBOX_I2C_CLK_FUNCEN_8852B, + PINMUX_GPIO11_DBG_GNT_BT_PINEN_8852B, + PINMUX_GPIO11_WL_UART_RX_PINEN_8852B, + PINMUX_GPIO11_WL_UART_RX_SECEN_8852B, + PINMUX_GPIO11_WL_UART_RX_FUNCEN_8852B, + PINMUX_GPIO11_WL_UART_RX_DIS_8852B, + PINMUX_GPIO11_WL_UART_RX_DIS_2_8852B, + PINMUX_GPIO11_WL_RFE_CTRL11_PINEN_8852B, + PINMUX_GPIO11_DBG11_PINEN_8852B, + PINMUX_GPIO11_SW_IO11_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO12_8852B[] = { + PINMUX_GPIO12_BT_GPIO12_8852B, + PINMUX_GPIO12_LTE_3W_PRI_OUT_PINEN_8852B, + PINMUX_GPIO12_LTE_3W_PRI_OUT_FUNCEN_8852B, + PINMUX_GPIO12_WL_ACT_PINEN_8852B, + PINMUX_GPIO12_WL_ACT_FUNCEN_8852B, + PINMUX_GPIO12_BT_ACT_PINEN_8852B, + PINMUX_GPIO12_BT_ACT_FUNCEN_8852B, + PINMUX_GPIO12_BT_ACT_DIS_8852B, + PINMUX_GPIO12_DBG_GNT_WL_PINEN_8852B, + PINMUX_GPIO12_SOUT_PINEN_8852B, + PINMUX_GPIO12_SOUT_SECEN_8852B, + PINMUX_GPIO12_SOUT_FUNCEN_8852B, + PINMUX_GPIO12_WL_RFE12_8852B, + PINMUX_GPIO12_DBG_GPIO12_8852B, + PINMUX_GPIO12_SW_IO12_PINEN_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO13_8852B[] = { + PINMUX_GPIO13_BT_GPIO13_8852B, + PINMUX_GPIO13_WL_PTA_BT_CLK_PINEN_8852B, + PINMUX_GPIO13_WL_PTA_BT_CLK_FUNCEN_8852B, + PINMUX_GPIO13_BT_PTA_WL_CLK_PINEN_8852B, + PINMUX_GPIO13_BT_PTA_WL_CLK_FUNCEN_8852B, + PINMUX_GPIO13_WL_UART_TX_PINEN_8852B, + PINMUX_GPIO13_WL_UART_TX_SECEN_8852B, + PINMUX_GPIO13_WL_UART_TX_FUNCEN_8852B, + PINMUX_GPIO13_WL_RFE_CTRL13_8852B, + PINMUX_GPIO13_DBG13_8852B, + PINMUX_GPIO13_SW_IO13_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO14_8852B[] = { + PINMUX_GPIO14_BT_GPIO14_8852B, + PINMUX_GPIO14_WL_PTA_BT_STA_PINEN_8852B, + PINMUX_GPIO14_WL_PTA_BT_STA_FUNCEN_8852B, + PINMUX_GPIO14_BT_PTA_WL_STA_PINEN_8852B, + PINMUX_GPIO14_BT_PTA_WL_STA_FUNCEN_8852B, + PINMUX_GPIO14_WL_JTAG_CLK_PINEN_8852B, + PINMUX_GPIO14_WL_JTAG_CLK_FUNCEN_8852B, + PINMUX_GPIO14_WL_JTAG_CLK_SECEN_8852B, + PINMUX_GPIO14_WL_RFE_CTRL13_8852B, + PINMUX_GPIO14_DBG14_8852B, + PINMUX_GPIO14_SW_IO14_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO15_8852B[] = { + PINMUX_GPIO15_WL_PD_PINEN_8852B, + PINMUX_GPIO15_BT_GPIO15_8852B, + PINMUX_GPIO15_WL_PTA_BT_CLK_PINEN_8852B, + PINMUX_GPIO15_WL_PTA_BT_CLK_FUNCEN_8852B, + PINMUX_GPIO15_BT_PTA_WL_CLK_PINEN_8852B, + PINMUX_GPIO15_BT_PTA_WL_CLK_FUNCEN_8852B, + PINMUX_GPIO15_WL_UART_TX_PINEN_8852B, + PINMUX_GPIO15_WL_UART_TX_SECEN_8852B, + PINMUX_GPIO15_WL_UART_TX_FUNCEN_8852B, + PINMUX_GPIO15_WL_RFE_CTRL15_8852B, + PINMUX_GPIO15_DBG15_8852B, + PINMUX_GPIO15_SW_IO15_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO16_8852B[] = { + PINMUX_GPIO16_WL_RFE_CTRL16_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list PIN_LIST_GPIO17_8852B[] = { + PINMUX_GPIO17_WL_RFE_CTRL17_8852B, + PINMUX_GPIO_END_8852B, +}; + +static const struct mac_ax_pin_list *PIN_LIST_8852B[] = { + PIN_LIST_GPIO0_8852B, /* gpio0 */ + PIN_LIST_GPIO1_8852B, /* gpio1 */ + PIN_LIST_GPIO2_8852B, /* gpio2 */ + PIN_LIST_GPIO3_8852B, /* gpio3 */ + PIN_LIST_GPIO4_8852B, /* gpio4 */ + PIN_LIST_GPIO5_8852B, /* gpio5 */ + PIN_LIST_GPIO6_8852B, /* gpio6 */ + PIN_LIST_GPIO7_8852B, /* gpio7 */ + PIN_LIST_GPIO8_8852B, /* gpio8 */ + PIN_LIST_GPIO9_8852B, /* gpio9 */ + PIN_LIST_GPIO10_8852B, /* gpio10 */ + PIN_LIST_GPIO11_8852B, /* gpio11 */ + PIN_LIST_GPIO12_8852B, /* gpio12 */ + PIN_LIST_GPIO13_8852B, /* gpio13 */ + PIN_LIST_GPIO14_8852B, /* gpio14 */ + PIN_LIST_GPIO15_8852B, /* gpio15 */ + PIN_LIST_GPIO16_8852B, /* gpio16 */ + PIN_LIST_GPIO17_8852B, /* gpio17 */ +}; + +static u32 mac_get_pinmux_list_8852b(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func, + const struct mac_ax_pinmux_list **list, + u32 *list_size, u32 *gpio_id) +{ + switch (func) { + case MAC_AX_GPIO_SW_IO_0: + *list = PINMUX_LIST_GPIO0_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8852B); + *gpio_id = MAC_AX_GPIO0; + break; + case MAC_AX_GPIO_SW_IO_1: + *list = PINMUX_LIST_GPIO1_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8852B); + *gpio_id = MAC_AX_GPIO1; + break; + case MAC_AX_GPIO_SW_IO_2: + *list = PINMUX_LIST_GPIO2_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8852B); + *gpio_id = MAC_AX_GPIO2; + break; + case MAC_AX_GPIO_SW_IO_3: + *list = PINMUX_LIST_GPIO3_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8852B); + *gpio_id = MAC_AX_GPIO3; + break; + case MAC_AX_GPIO_SW_IO_4: + *list = PINMUX_LIST_GPIO4_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8852B); + *gpio_id = MAC_AX_GPIO4; + break; + case MAC_AX_GPIO_SW_IO_5: + case MAC_AX_GPIO_UART_TX_GPIO5: + *list = PINMUX_LIST_GPIO5_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8852B); + *gpio_id = MAC_AX_GPIO5; + break; + case MAC_AX_GPIO_SW_IO_6: + case MAC_AX_GPIO_UART_RX_GPIO6: + *list = PINMUX_LIST_GPIO6_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8852B); + *gpio_id = MAC_AX_GPIO6; + break; + case MAC_AX_GPIO_SW_IO_7: + case MAC_AX_GPIO_UART_TX_GPIO7: + *list = PINMUX_LIST_GPIO7_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8852B); + *gpio_id = MAC_AX_GPIO7; + break; + case MAC_AX_GPIO_SW_IO_8: + case MAC_AX_GPIO_UART_TX_GPIO8: + *list = PINMUX_LIST_GPIO8_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8852B); + *gpio_id = MAC_AX_GPIO8; + break; + case MAC_AX_GPIO_SW_IO_9: + *list = PINMUX_LIST_GPIO9_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8852B); + *gpio_id = MAC_AX_GPIO9; + break; + case MAC_AX_GPIO_SW_IO_10: + *list = PINMUX_LIST_GPIO10_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8852B); + *gpio_id = MAC_AX_GPIO10; + break; + case MAC_AX_GPIO_SW_IO_11: + *list = PINMUX_LIST_GPIO11_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8852B); + *gpio_id = MAC_AX_GPIO11; + break; + case MAC_AX_GPIO_SW_IO_12: + *list = PINMUX_LIST_GPIO12_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8852B); + *gpio_id = MAC_AX_GPIO12; + break; + case MAC_AX_GPIO_SW_IO_13: + *list = PINMUX_LIST_GPIO13_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8852B); + *gpio_id = MAC_AX_GPIO13; + break; + case MAC_AX_GPIO_SW_IO_14: + case MAC_AX_GPIO_UART_RX_GPIO14: + *list = PINMUX_LIST_GPIO14_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8852B); + *gpio_id = MAC_AX_GPIO14; + break; + case MAC_AX_GPIO_SW_IO_15: + *list = PINMUX_LIST_GPIO15_8852B; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8852B); + *gpio_id = MAC_AX_GPIO15; + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_pinmux_set_func_8852b(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func) +{ + const struct mac_ax_pinmux_list *list = NULL; + u32 ret; + u32 gpio_id, list_size; + + ret = mac_pinmux_status(adapter, func); + if (ret) + goto END; + + ret = mac_get_pinmux_list_8852b(adapter, func, &list, + &list_size, &gpio_id); + if (ret) + goto END; + + ret = mac_pinmux_switch(adapter, func, list, list_size, gpio_id); + if (ret) + goto END; + + ret = mac_pinmux_record(adapter, func, 1); + +END: + return ret; +} + +u32 mac_set_gpio_func_8852b(struct mac_ax_adapter *adapter, + enum rtw_mac_gfunc func, s8 gpio_cfg) +{ + const struct mac_ax_pin_list *list; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val, is_set = 0; + u8 gpio; + + if (gpio_cfg < MAC_AX_GPIO_MIN || gpio_cfg > RTW_MAC_GPIO_MAX) { + PLTFM_MSG_ERR("The GPIO number is wrong: %d", gpio_cfg); + return MACGPIONUM; + } + + gpio = gpio_cfg; + list = PIN_LIST_8852B[gpio]; + while (list && list->func != RTW_MAC_GPIO_INVALID) { + if (list->func == func) { + val = MAC_REG_R8(list->offset); + val = (val & ~(list->msk)) | list->value; + MAC_REG_W8(list->offset, val); + is_set++; + } + list++; + } + + if (!is_set) { + PLTFM_MSG_ERR("The GPIO function is NOT available in %d", gpio); + return MACNOITEM; + } + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.h b/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.h new file mode 100644 index 0000000..7fed17f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.h @@ -0,0 +1,46 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_GPIO_8852B_H_ +#define _MAC_AX_GPIO_8852B_H_ + +#include "../../type.h" + +/** + * @brief mac_pinmux_set_func_8852b + * + * @param *adapter + * @param func + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_pinmux_set_func_8852b(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func); + +/** + * @brief mac_set_gpio_func_8852b + * + * @param *adapter + * @param func + * @param gpio + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_gpio_func_8852b(struct mac_ax_adapter *adapter, + enum rtw_mac_gfunc func, s8 gpio); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.c b/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.c new file mode 100644 index 0000000..bfb3658 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.c @@ -0,0 +1,798 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "init_8852b.h" +#include "../pwr.h" +#include "../efuse.h" +#include "../init.h" +#include "../trxcfg.h" +#include "pwr_seq_8852b.h" +#include "pwr_seq_func_8852b.h" +#include "../hw.h" +#include "../security_cam.h" +#include "../trx_desc.h" +#include "../../feature_cfg.h" +#include "../fwcmd.h" +#include "../fwdl.h" +#include "../fwofld.h" +#include "../role.h" +#include "../tblupd.h" +#include "../rx_forwarding.h" +#include "../rx_filter.h" +#include "../phy_rpt.h" +#include "../hwamsdu.h" +#include "../status.h" +#include "../hdr_conv.h" +#include "../hw_seq.h" +#include "gpio_8852b.h" +#include "../gpio.h" +#include "../cpuio.h" +#include "../sounding.h" +#include "../power_saving.h" +#include "../wowlan.h" +#include "../tcpip_checksum_offload.h" +#include "../la_mode.h" +#include "../dle.h" +#include "../coex.h" +#include "../mcc.h" +#include "../twt.h" +#include "../mport.h" +#include "../p2p.h" +#include "../flash.h" +#include "../dbg_cmd.h" +#include "../phy_misc.h" +#include "../h2c_agg.h" +#include "../dbcc.h" + +#if MAC_AX_SDIO_SUPPORT +#include "../_sdio.h" +#endif +#if MAC_AX_USB_SUPPORT +#include "_usb_8852b.h" +#endif +#if MAC_AX_PCIE_SUPPORT +#include "../_pcie.h" +#endif +#if MAC_AX_FEATURE_DBGPKG +#include "../dbgpkg.h" +#include "../dbgport_hw.h" +#endif + +#if MAC_AX_SDIO_SUPPORT +static struct mac_ax_intf_ops mac8852b_sdio_ops = { + reg_read8_sdio, /* reg_read8 */ + reg_write8_sdio, /* reg_write8 */ + reg_read16_sdio, /* reg_read16 */ + reg_write16_sdio, /* reg_write16 */ + reg_read32_sdio, /* reg_read32 */ + reg_write32_sdio, /* reg_write32 */ + tx_allow_sdio, /* tx_allow_sdio */ + tx_cmd_addr_sdio, /* tx_cmd_addr_sdio */ + sdio_pre_init, /* intf_pre_init */ + sdio_init, /* intf_init */ + sdio_deinit, /* intf_init */ + reg_read_n_sdio, /* reg_read_n_sdio */ + NULL, /*get_bulkout_id*/ + NULL, /* ltr_set_pcie */ + NULL, /*u2u3_switch*/ + NULL, /*get_usb_mode*/ + NULL, /*get_usb_support_ability*/ + NULL, /*usb_tx_agg_cfg*/ + NULL, /*usb_rx_agg_cfg*/ + set_sdio_wowlan, /*set_wowlan*/ + NULL, /*ctrl_txdma_ch*/ + NULL, /*clr_idx_all*/ + NULL, /*poll_txdma_ch_idle*/ + NULL, /*poll_rxdma_ch_idle*/ + NULL, /*ctrl_txhci*/ + NULL, /*ctrl_rxhci*/ + NULL, /*ctrl_dma_io*/ + NULL, /* get_io_stat */ + sdio_get_txagg_num, /*get_txagg_num*/ + NULL, /*get_usb_rx_state*/ + sdio_autok_counter_avg, /* pcie_autok_counter_avg */ +}; +#endif + +#if MAC_AX_USB_SUPPORT +static struct mac_ax_intf_ops mac8852b_usb_ops = { + reg_read8_usb_8852b, /* reg_read8 */ + reg_write8_usb_8852b, /* reg_write8 */ + reg_read16_usb_8852b, /* reg_read16 */ + reg_write16_usb_8852b, /* reg_write16 */ + reg_read32_usb_8852b, /* reg_read32 */ + reg_write32_usb_8852b, /* reg_write32 */ + NULL, /* tx_allow_sdio */ + NULL, /* tx_cmd_addr_sdio */ + usb_pre_init_8852b, /* intf_pre_init */ + usb_init_8852b, /* intf_init */ + usb_deinit_8852b, /* intf_init */ + NULL, /* reg_read_n_sdio */ + get_bulkout_id_8852b, /*get_bulkout_id*/ + NULL, /* ltr_set_pcie */ + u2u3_switch_8852b, /*u2u3_switch*/ + get_usb_mode, /*get_usb_mode*/ + get_usb_support_ability_8852b,/*get_usb_support_ability*/ + usb_tx_agg_cfg_8852b, /*usb_tx_agg_cfg*/ + usb_rx_agg_cfg_8852b, /*usb_rx_agg_cfg*/ + set_usb_wowlan_8852b, /*set_wowlan*/ + NULL, /*ctrl_txdma_ch*/ + NULL, /*clr_idx_all*/ + NULL, /*poll_txdma_ch_idle*/ + NULL, /*poll_rxdma_ch_idle*/ + NULL, /*ctrl_txhci*/ + NULL, /*ctrl_rxhci*/ + NULL, /*ctrl_dma_io*/ + NULL, /* get_io_stat */ + usb_get_txagg_num_8852b, /*get_txagg_num*/ + usb_get_rx_state_8852b, /*get_usb_rx_state*/ + usb_autok_counter_avg, /* pcie_autok_counter_avg */ +}; +#endif + +#if MAC_AX_PCIE_SUPPORT +static struct mac_ax_intf_ops mac8852b_pcie_ops = { + reg_read8_pcie, /* reg_read8 */ + reg_write8_pcie, /* reg_write8 */ + reg_read16_pcie, /* reg_read16 */ + reg_write16_pcie, /* reg_write16 */ + reg_read32_pcie, /* reg_read32 */ + reg_write32_pcie, /* reg_write32 */ + NULL, /* tx_allow_sdio */ + NULL, /* tx_cmd_addr_sdio */ + pcie_pre_init, /* intf_pre_init */ + pcie_init, /* intf_init */ + pcie_deinit, /* intf_init */ + NULL, /* reg_read_n_sdio */ + NULL, /*get_bulkout_id*/ + ltr_set_pcie, /* ltr_set_pcie */ + NULL, /*u2u3_switch*/ + NULL, /*get_usb_mode*/ + NULL, /*get_usb_support_ability*/ + NULL, /*usb_tx_agg_cfg*/ + NULL, /*usb_rx_agg_cfg*/ + set_pcie_wowlan, /*set_wowlan*/ + ctrl_txdma_ch_pcie, /*ctrl_txdma_ch*/ + clr_idx_all_pcie, /*clr_idx_all*/ + poll_txdma_ch_idle_pcie, /*poll_txdma_ch_idle*/ + poll_rxdma_ch_idle_pcie, /*poll_rxdma_ch_idle*/ + ctrl_txhci_pcie, /*ctrl_txhci*/ + ctrl_rxhci_pcie, /*ctrl_rxhci*/ + ctrl_dma_io_pcie, /*ctrl_dma_io*/ + get_io_stat_pcie, /* get_io_stat */ + pcie_get_txagg_num, /*get_txagg_num*/ + NULL, /*get_usb_rx_state*/ + pcie_autok_counter_avg, /* pcie_autok_counter_avg */ +}; +#endif + +static struct mac_ax_ops mac8852b_ops = { + NULL, /* intf_ops */ + /*System level*/ + mac_hal_init, /* hal_init */ + mac_hal_fast_init, /* hal_fast_init */ + mac_hal_deinit, /* hal_deinit */ + mac_hal_fast_deinit, /*hal_fast_deinit*/ + mac_add_role, /* add_role */ + mac_remove_role, /* remove_role */ + mac_change_role, /* change_role */ + mac_pwr_switch, /* pwr_switch */ + mac_sys_init, /* sys_init */ + mac_trx_init, /* init */ + mac_romdl, /* romdl */ + mac_enable_cpu, /* enable_cpu */ + mac_disable_cpu, /* disable_cpu */ + mac_fwredl, /* fwredl */ + mac_fwdl, /* fwdl */ + mac_enable_fw, /* enable_fw */ + mac_lv1_rcvy, /* lv1_rcvy */ + mac_get_macaddr, + mac_build_txdesc, /* build_txdesc */ + mac_refill_txdesc, /*refill txdesc*/ + mac_parse_rxdesc, /* parse_rxdesc */ + mac_watchdog, /* watchdog */ + /*FW offload related*/ + mac_reset_fwofld_state, + mac_check_fwofld_done, + mac_read_pkt_ofld, + mac_del_pkt_ofld, + mac_add_pkt_ofld, + mac_pkt_ofld_packet, + mac_dump_efuse_ofld, + mac_efuse_ofld_map, + mac_upd_dctl_info, /*update dmac ctrl info*/ + mac_upd_cctl_info, /*update cmac ctrl info*/ + mac_ie_cam_upd, /* ie_cam_upd */ + mac_twt_info_upd_h2c, /* twt info update h2c */ + mac_twt_act_h2c, /* twt act h2c */ + mac_twt_staanno_h2c, /* twt anno h2c */ + mac_twt_wait_anno, + mac_host_getpkt_h2c, + mac_p2p_act_h2c, /* p2p_act_h2c */ + mac_p2p_macid_ctrl_h2c, /* p2p_macid_ctrl_h2c */ + mac_get_p2p_stat, /* get_p2p_stat */ + mac_tsf32_togl_h2c, /* tsf32_togl_h2c */ + mac_get_t32_togl_rpt, /* get_t32_togl_rpt */ + mac_ccxrpt_parsing, + /*Association, de-association related*/ + mac_sta_add_key, /* add station key */ + mac_sta_del_key, /* del station key */ + mac_sta_search_key_idx, /* search station key index */ + mac_sta_hw_security_support, /* control hw security support */ + mac_sta_keycam_backup, /* sta keycam backup restore control */ + mac_set_mu_table, /*set mu score table*/ + mac_ss_dl_grp_upd, /* update SS dl group info*/ + mac_ss_ul_grp_upd, /* update SS ul group info*/ + mac_ss_ul_sta_upd, /* add sta into SS ul link*/ + mac_bacam_info, /*update BA CAM info*/ + /*TRX related*/ + mac_txdesc_len, /* txdesc_len */ + mac_upd_shcut_mhdr,/*update short cut mac header*/ + mac_enable_hwmasdu, /* enable_hwmasdu */ + mac_enable_cut_hwamsdu, /* enable_cut_hwamsdu */ + mac_hdr_conv, /* hdr_conv */ + mac_set_hwseq_reg, /* set hw seq by reg */ + mac_process_c2h, /* process_c2h */ + mac_parse_dfs, /* parse_dfs */ + mac_parse_ppdu, /* parse_ppdu */ + mac_cfg_phy_rpt, /* cfg_phy_rpt */ + mac_set_rx_forwarding, /*rx_forwarding */ + mac_get_rx_fltr_opt, /* set rx fltr mac, pclp header opt */ + mac_set_rx_fltr_opt, /* get rx fltr mac, pclp header opt */ + mac_set_typ_fltr_opt, /* set machdr type fltr opt */ + mac_set_typsbtyp_fltr_opt, /* set machdr typ subtyp fltr opt */ + mac_set_typsbtyp_fltr_detail, /* set detail type subtype filter config*/ + mac_get_cfg_addr_cam, /* get addrcam setting */ + mac_get_cfg_addr_cam_dis, /* get addrcam disable default setting */ + mac_cfg_addr_cam, /* config addrcam setting */ + mac_cfg_addr_cam_dis, /* config addrcam disable default setting */ + mac_sr_update, /* set sr parameter */ + mac_two_nav_cfg, /* config 2NAV hw setting */ + mac_wde_pkt_drop, /* pkt_drop */ + mac_send_bcn_h2c, /* send beacon h2c */ + mac_tx_mode_sel, /*tx mode sel*/ + mac_tcpip_chksum_ofd, /* tcpip_chksum_ofd */ + mac_chk_rx_tcpip_chksum_ofd, /* chk_rx_tcpip_chksum_ofd */ + mac_chk_allq_empty, /*chk_allq_empty*/ + mac_is_txq_empty, /*is_txq_empty*/ + mac_is_rxq_empty, /*is_rxq_empty*/ + mac_parse_bcn_stats_c2h, /*parse tx bcn statistics*/ + mac_tx_idle_poll, /*tx_idle_poll*/ + mac_sifs_chk_cca_en, /*mac_sifs_chk_cca_en*/ + mac_patch_rx_rate, /*for patch rx rate error*/ + /*frame exchange related*/ + mac_upd_mudecision_para, /* upd_ba_infotbl */ + mac_mu_sta_upd, /* upd_mu_sta */ + mac_upd_ul_fixinfo, /* upd_ul_fixinfo */ + mac_f2p_test_cmd, /*f2p test cmd para*/ + mac_snd_test_cmd, /* f2p test cmd para */ + mac_set_fixmode_mib, /* set_fw_testmode */ + mac_dumpwlanc, + mac_dumpwlans, + mac_dumpwland, + /*outsrcing related */ + mac_outsrc_h2c_common, /* outsrc common h2c */ + mac_read_pwr_reg, /* for read tx power reg*/ + mac_write_pwr_reg, /* for write tx power reg*/ + mac_write_msk_pwr_reg, /* for write tx power reg*/ + mac_write_pwr_ofst_mode, /* for write tx power mode offset reg*/ + mac_write_pwr_ofst_bw, /* for write tx power BW offset reg*/ + mac_write_pwr_ref_reg, /* for write tx power ref reg*/ + mac_write_pwr_limit_en, /* for write tx power limit enable reg*/ + mac_write_pwr_limit_rua_reg, /* for write tx power limit rua reg*/ + mac_write_pwr_limit_reg, /* for write tx power limit reg*/ + mac_write_pwr_by_rate_reg, /* for write tx power by rate reg*/ + mac_lamode_cfg, /*cfg la mode para*/ + mac_lamode_trigger, /*trigger la mode start*/ + mac_lamode_buf_cfg, /*la mode buf size cfg */ + mac_get_lamode_st, /*get la mode status*/ + mac_read_xcap_reg_dav, /*read xcap xo/xi reg*/ + mac_write_xcap_reg_dav, /*write xcap xo/xi reg*/ + mac_write_bbrst_reg, /*write bb rst reg*/ + /*sounding related*/ + mac_get_csi_buffer_index, /* get CSI buffer index */ + mac_set_csi_buffer_index, /* set CSI buffer index */ + mac_get_snd_sts_index, /* get MACID SND status */ + mac_set_snd_sts_index, /* set SND status MACID */ + mac_init_snd_mer,/* init SND MER */ + mac_init_snd_mee,/* init SND MEE */ + mac_csi_force_rate, /*CSI fix rate reg*/ + mac_csi_rrsc, /*CSI RRSC*/ + mac_set_snd_para, /*set sound parameter*/ + mac_set_csi_para_reg, /*set reg csi para*/ + mac_set_csi_para_cctl, /*set csi para in cmac ctrl info*/ + mac_hw_snd_pause_release, /*HW SND pause release*/ + mac_bypass_snd_sts, /*bypass SND status*/ + mac_deinit_mee, /*deinit mee*/ + mac_snd_sup, /*bf entry num and SU MU buffer num*/ + mac_gidpos, /*VHT MU GID position setting*/ + /*ps related*/ + mac_cfg_lps, /*config LPS*/ + mac_ps_pwr_state, /*set or check lps power state*/ + mac_chk_leave_lps, /*check already leave protocol ps*/ + mac_cfg_ips, /*config IPS*/ + mac_chk_leave_ips, /*check already leave IPS protocol*/ + mac_ps_notify_wake, /*send RPWM to wake up HW/FW*/ + mac_cfg_ps_advance_parm, /*config advance parameter for power saving*/ + /* Wowlan related*/ + mac_cfg_wow_wake, /*config wowlan wake*/ + mac_cfg_disconnect_det, /*config disconnect det*/ + mac_cfg_keep_alive, /*config keep alive*/ + mac_cfg_gtk_ofld, /*config gtk ofld*/ + mac_cfg_arp_ofld, /*config arp ofld*/ + mac_cfg_ndp_ofld, /*config ndp ofld*/ + mac_cfg_realwow, /*config realwow*/ + mac_cfg_nlo, /*config nlo*/ + mac_cfg_dev2hst_gpio, /*config dev2hst gpio*/ + mac_cfg_uphy_ctrl, /*config uphy ctrl*/ + mac_cfg_wowcam_upd, /*config wowcam update*/ + mac_get_wow_wake_rsn, /* Get wowlan wakeup reason with reset option */ + mac_cfg_wow_sleep, /*config wowlan before sleep/after wake*/ + mac_get_wow_fw_status, /*get wowlan fw status*/ + mac_request_aoac_report, /* request_aoac_report */ + mac_read_aoac_report, /* read_aoac_report */ + mac_check_aoac_report_done, /* check_aoac_report_done */ + mac_wow_stop_trx, /* wow_stop_trx */ + /*system related*/ + mac_dbcc_enable, /*enable / disable dbcc */ + mac_dbcc_move_macid, /* dbcc_move_macid */ + mac_port_cfg, /* cofig port para */ + mac_port_init, /* init port para */ + mac_enable_imr, /* enable CMAC/DMAC IMR */ + mac_dump_efuse_map_wl_plus, /* dump_wl_efuse*/ + mac_dump_efuse_map_bt, /* dump_bt_efuse */ + mac_write_efuse_plus, /* write_wl_bt_efuse */ + mac_read_efuse_plus, /* read_wl_bt_efuse */ + mac_get_efuse_avl_size, /* get_available_efuse_size */ + mac_get_efuse_avl_size_bt, /* get_available_efuse_size_bt */ + mac_dump_log_efuse_plus, /* dump_logical_efuse */ + mac_read_log_efuse_plus, /* read_logical_efuse */ + mac_write_log_efuse_plus, /* write_logical_efuse */ + mac_dump_log_efuse_bt, /* dump_logical_efuse_bt */ + mac_read_log_efuse_bt, /* read_logical_efuse_bt */ + mac_write_log_efuse_bt, /* write_logical_efuse_bt */ + mac_pg_efuse_by_map_plus, /* program_efuse_map */ + mac_pg_efuse_by_map_bt, /* program_efuse_map_bt */ + mac_mask_log_efuse, /* mask_logical_efuse_map */ + mac_pg_sec_data_by_map, /* program_secure_data_map */ + mac_cmp_sec_data_by_map, /* compare_secure_data_map */ + mac_get_efuse_info, /* get_efuse_info */ + mac_set_efuse_info, /* set_efuse_info */ + mac_read_hidden_rpt, /* read_efuse_hidden_report */ + mac_check_efuse_autoload, /* check_efuse_autoload */ + mac_pg_simulator_plus, /* efuse pg simulator */ + mac_checksum_update, /* checksum update */ + mac_checksum_rpt, /*report checksum comparison result*/ + mac_disable_rf, /* Disable RF Offload */ + mac_set_efuse_ctrl, /*set efuse ctrl 0x30 or 0xC30*/ + mac_otp_test, /*efuse OTP test R/W to 0x7ff*/ + mac_get_ft_status, /* get_mac_ft_status */ + mac_fw_log_cfg, /* fw_log_cfg */ + mac_pinmux_set_func_8852b, /* pinmux_set_func */ + mac_pinmux_free_func, /* pinmux_free_func */ + mac_sel_uart_tx_pin, /* sel_uart_tx_pin */ + mac_sel_uart_rx_pin, /* sel_uart_rx_pin */ + mac_set_gpio_func_8852b, /* set_gpio_func */ + mac_get_hw_info, /* get_hw_info */ + mac_set_hw_value, /* set_hw_value */ + mac_get_hw_value, /* get_hw_value */ + mac_get_err_status, /* get_err_status */ + mac_set_err_status, /* set_err_status */ + mac_general_pkt_ids, /*general_pkt_ids */ + mac_coex_init, /* coex_init */ + mac_read_coex_reg, /* coex_read */ + mac_write_coex_reg, /* coex_write */ + mac_trigger_cmac_err, /*trigger_cmac_err*/ + mac_trigger_cmac1_err, /*trigger_cmac1_err*/ + mac_trigger_dmac_err, /*trigger_dmac_err*/ + mac_tsf_sync, /*tsf_sync*/ + mac_read_xtal_si, /*read_xtal_si*/ + mac_write_xtal_si, /*write_xtal_si*/ + mac_io_chk_access, /* io_chk_access */ + mac_ser_ctrl, /* ser_ctrl */ + /* mcc */ + mac_reset_mcc_group, + mac_reset_mcc_request, + mac_add_mcc, /* add_mcc */ + mac_start_mcc, /* start_mcc */ + mac_stop_mcc, /* stop_mcc */ + mac_del_mcc_group, /* del_mcc_group */ + mac_mcc_request_tsf, /* mcc_request_tsf */ + mac_mcc_macid_bitmap, /* mcc_macid_bitmap */ + mac_mcc_sync_enable, /* mcc_sync_enable */ + mac_mcc_set_duration, /* mcc_set_duration */ + mac_get_mcc_tsf_rpt, + mac_get_mcc_status_rpt, + mac_get_mcc_group, + mac_check_add_mcc_done, + mac_check_start_mcc_done, + mac_check_stop_mcc_done, + mac_check_del_mcc_group_done, + mac_check_mcc_request_tsf_done, + mac_check_mcc_macid_bitmap_done, + mac_check_mcc_sync_enable_done, + mac_check_mcc_set_duration_done, + /* not mcc */ + mac_check_access, + mac_set_led_mode, /* set_led_mode */ + mac_led_ctrl, /* led_ctrl */ + mac_set_sw_gpio_mode, /* set_sw_gpio_mode */ + mac_sw_gpio_ctrl, /* sw_gpio_ctrl */ + mac_get_c2h_event, /* get_c2h_event */ + mac_cfg_wps, /* cfg_wps */ + mac_get_wl_dis_val, /* get_wl_dis_val */ +#if MAC_AX_FEATURE_DBGPKG + mac_fwcmd_lb, /* fwcmd_lb */ + mac_mem_dump, /* sram mem dump */ + mac_get_mem_size, /* get mem size */ + mac_dbg_status_dump, /* mac dbg status dump */ + mac_reg_dump, /* debug reg dump for MAC/BB/RF*/ + mac_rx_cnt, + mac_dump_fw_rsvd_ple, + mac_dump_ple_dbg_page, /* dump_ple_dbg_page */ + mac_fw_dbg_dump, + mac_event_notify, + mac_dbgport_hw_set, /* Set debug port for LA */ +#endif +#if MAC_AX_FEATURE_HV + mac_ram_boot, /* ram_boot */ + /*fw offload related*/ + mac_clear_write_request, /* clear_write_request */ + mac_add_write_request, /* add_write_request */ + mac_write_ofld, /* write_ofld */ + mac_clear_conf_request, /* clear_conf_request */ + mac_add_conf_request, /* add_conf_request */ + mac_conf_ofld, /* conf_ofld */ + mac_clear_read_request, /* clear_read_request */ + mac_add_read_request, /* add_read_request */ + mac_read_ofld, /* read_ofld */ + mac_read_ofld_value, /* read_ofld_value */ +#endif + mac_add_cmd_ofld, /* add_cmd_ofld */ + mac_flash_erase, + mac_flash_read, + mac_flash_write, + mac_fw_status_cmd, /* fw_status_cmd */ + mac_fwc2h_ofdma_sts_parse, /* parse c2h fw sts */ + mac_fw_ofdma_sts_en, /* send fw sts en to fw */ + mac_tx_duty, /* tx_duty */ + mac_tx_duty_stop, /* tx_duty _stop */ +#if MAC_AX_FEATURE_DBGCMD + mac_halmac_cmd, /* halmac_cmd */ + mac_halmac_cmd_parser, /* halmac_cmd_parser */ +#endif + mac_fast_ch_sw, + mac_fast_ch_sw_done, + mac_get_fast_ch_sw_rpt, + mac_write_coex_mask, + mac_fw_dbg_dle_cfg, + mac_h2c_agg_enable, + mac_h2c_agg_flush, + mac_h2c_agg_tx, +#if MAC_AX_FEATURE_DBGDEC + mac_fw_log_set_array, + mac_fw_log_unset_array, +#endif + mac_get_fw_status, + mac_add_scanofld_ch, + mac_scanofld, + mac_scanofld_fw_busy, + mac_scanofld_chlist_busy, + mac_role_sync, + mac_ch_switch_ofld, + mac_get_ch_switch_rpt +}; + +static struct mac_ax_hw_info mac8852b_hw_info = { + 0, /* done */ + MAC_AX_CHIP_ID_8852B, /* chip_id */ + 0xFF, /* cv */ + MAC_AX_INTF_INVALID, /* intf */ + 19, /* tx_ch_num */ + 10, /* tx_data_ch_num */ + WD_BODY_LEN, /* wd_body_len */ + WD_INFO_LEN, /* wd_info_len */ + pwr_on_seq_8852b, /* pwr_on_seq */ + pwr_off_seq_8852b, /* pwr_off_seq */ + PWR_SEQ_VER_8852B, /* pwr_seq_ver */ + 196608, /* fifo_size */ + 32, /* macid_num */ + 5, /* port_num */ + 4, /* mbssid_num */ + 20, /* bssid_num */ + 1536, /* wl_efuse_size */ + 1216, /* wl_zone2_efuse_size */ + 2048, /* log_efuse_size */ + 1280, /* limit_efuse_size_PCIE */ + 1280, /* limit_efuse_size_USB */ + 1280, /* limit_efuse_size_SDIO */ + 512, /* bt_efuse_size */ + 1024, /* bt_log_efuse_size */ + 32, /*hidden_efuse_size*/ + 4, /* sec_ctrl_efuse_size */ + 192, /* sec_data_efuse_size */ + NULL, /* sec_cam_table_t pointer */ + NULL, /* sec_cam_table_bk pointer */ + 32, /* ple_rsvd_space */ + 24, /* payload_desc_size */ + 8, /* efuse_version_size */ + 128, /* wl_efuse_size_DAV */ + 96, /* wl_zone2_efuse_size_DAV */ + 32, /* hidden_efuse_size_DAV */ + 16, /* log_efuse_size_DAV */ + 0, /* wl_efuse_start_addr */ + 0, /* wl_efuse_start_addr_DAV */ + 0x600, /* bt_efuse_start_addr */ + 0, /* wd_checksum_en */ + 0, /* sw_amsdu_max_size */ + NULL, /* pwr_on */ + NULL, /* pwr_off */ + 0, /* ind_aces_cnt */ + 0, /* dbg_port_cnt */ + 0, /* core_swr_volt */ + MAC_AX_SWR_NORM, /* core_swr_volt_sel */ +}; + +static struct mac_ax_hw_info mac8852b_hw_info_cabv = { + 0, /* done */ + MAC_AX_CHIP_ID_8852B, /* chip_id */ + 0xFF, /* cv */ + MAC_AX_INTF_INVALID, /* intf */ + 19, /* tx_ch_num */ + 10, /* tx_data_ch_num */ + WD_BODY_LEN, /* wd_body_len */ + WD_INFO_LEN, /* wd_info_len */ + pwr_on_seq_8852b, /* pwr_on_seq */ + pwr_off_seq_8852b, /* pwr_off_seq */ + PWR_SEQ_VER_8852B, /* pwr_seq_ver */ + 131072, /* fifo_size */ + 32, /* macid_num */ + 5, /* port_num */ + 4, /* mbssid_num */ + 20, /* bssid_num */ + 1536, /* wl_efuse_size */ + 1216, /* wl_zone2_efuse_size */ + 2048, /* log_efuse_size */ + 1280, /* limit_efuse_size_PCIE */ + 1280, /* limit_efuse_size_USB */ + 1280, /* limit_efuse_size_SDIO */ + 512, /* bt_efuse_size */ + 1024, /* bt_log_efuse_size */ + 32, /*hidden_efuse_size*/ + 4, /* sec_ctrl_efuse_size */ + 192, /* sec_data_efuse_size */ + NULL, /* sec_cam_table_t pointer */ + NULL, /* sec_cam_table_bk pointer */ + 32, /* ple_rsvd_space */ + 24, /* payload_desc_size */ + 8, /* efuse_version_size */ + 128, /* wl_efuse_size_DAV */ + 96, /* wl_zone2_efuse_size_DAV */ + 32, /* hidden_efuse_size_DAV */ + 16, /* log_efuse_size_DAV */ + 0, /* wl_efuse_start_addr */ + 0, /* wl_efuse_start_addr_DAV */ + 0x600, /* bt_efuse_start_addr */ + 0, /* wd_checksum_en */ + 0, /* sw_amsdu_max_size */ + NULL, /* pwr_on */ + NULL, /* pwr_off */ + 0, /* ind_aces_cnt */ + 0, /* dbg_port_cnt */ + 0, /* core_swr_volt */ + MAC_AX_SWR_NORM, /* core_swr_volt_sel */ +}; + +struct mac_ax_ft_status mac_8852b_ft_status[] = { + {MAC_AX_FT_DUMP_EFUSE, MAC_AX_STATUS_IDLE, NULL, 0}, + {MAC_AX_FT_MAX, MAC_AX_STATUS_ERR, NULL, 0}, +}; + +static struct mac_ax_adapter mac_8852b_adapter = { + &mac8852b_ops, /* ops */ + NULL, /* drv_adapter */ + NULL, /* phl_adapter */ + NULL, /* pltfm_cb */ + MAC_AX_DFLT_SM, /* sm */ + NULL, /* hw_info */ + {0}, /* fw_info */ + {0}, /* efuse_param */ + {0}, /* mac_pwr_info */ + mac_8852b_ft_status, /* ft_stat */ + NULL, /* hfc_param */ + {MAC_AX_QTA_SCC, 64, 128, 0, 0, 0, 0, 0, 0}, /* dle_info */ + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, DFLT_GPIO_STATE}, /* gpio_info */ + NULL, /* role table */ + {NULL, NULL, NULL, 0, 0, 0, 0}, /* read_ofld_info */ + {0, 0, NULL}, /* read_ofld_value */ + {NULL, NULL, NULL, 0, 0, 0, 0}, /* write_ofld_info */ + {NULL}, /* efuse_ofld_info */ + {NULL, NULL, 0, 0, 0, 0}, /* conf_ofld_info */ + {PKT_OFLD_OP_MAX, PKT_OFLD_MAX_COUNT, 0, {0}}, /* pkt_ofld_info */ + {0, 0, 0, NULL}, /* pkt_ofld_pkt */ + {NULL, NULL, NULL, 0, 0, 0, 0, 0}, /* cmd_ofld_info */ + {{{0}, {0}, {0}, {0}}}, /* mcc_group_info */ + {NULL}, /* wowlan_info */ + NULL, /* p2p_info */ + NULL, /* t32_togl_rpt */ + NULL, /* port_info */ + {0}, /* struct mac_ax_int_stats stats */ + {0, 0}, /* struct mac_ax_drv_stats drv_stats */ + {0}, /*h2c_agg_info*/ +#if MAC_AX_SDIO_SUPPORT + {MAC_AX_SDIO_4BYTE_MODE_DISABLE, MAC_AX_SDIO_TX_MODE_AGG, + MAC_AX_SDIO_SPEC_VER_2_00, MAC_AX_SDIO_OPN_MODE_BLOCK, + 512, 1, 8, 0}, /* sdio_info */ +#endif +#if MAC_AX_USB_SUPPORT + {0}, /* usb_info */ +#endif +#if MAC_AX_PCIE_SUPPORT + {0}, /* pcie_info */ +#endif + {0, 0, 0, 0, 0, 0, 0, 0, 0, NULL}, /*flash_info */ + {0, 0}, /* fast_ch_sw_info */ +#if MAC_AX_FEATURE_HV + NULL, /*hv_ax_ops*/ + HV_AX_ASIC, /* env */ +#endif +#if MAC_AX_FEATURE_DBGCMD + {NULL}, /*fw_dbgcmd*/ +#endif +#if MAC_AX_FEATURE_DBGDEC + NULL, /*fw_log_array*/ + NULL, + 0, +#endif + {0}, /*log_cfg*/ + {NULL}, + NULL, /*ch_switch_rpt*/ +}; + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf, + u8 cv, void *phl_adapter, + void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb) +{ + struct mac_ax_adapter *adapter = NULL; + struct mac_ax_mac_pwr_info *pwr_info; + + adapter = + (struct mac_ax_adapter *)hal_mem_alloc(drv_adapter, + sizeof(struct mac_ax_adapter)); + if (!adapter) + return NULL; + + hal_mem_cpy(drv_adapter, adapter, &mac_8852b_adapter, + sizeof(struct mac_ax_adapter)); + pwr_info = &adapter->mac_pwr_info; + + adapter->phl_adapter = phl_adapter; + adapter->drv_adapter = drv_adapter; + adapter->pltfm_cb = pltfm_cb; + adapter->hw_info->cv = cv; + adapter->hw_info->intf = intf; + adapter->hw_info->done = 1; + + switch (intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + adapter->ops->intf_ops = &mac8852b_sdio_ops; + pwr_info->intf_pwr_switch = sdio_pwr_switch; + break; +#endif +#if MAC_AX_USB_SUPPORT + case MAC_AX_INTF_USB: + adapter->ops->intf_ops = &mac8852b_usb_ops; + pwr_info->intf_pwr_switch = usb_pwr_switch; + break; +#endif +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_INTF_PCIE: + adapter->ops->intf_ops = &mac8852b_pcie_ops; + pwr_info->intf_pwr_switch = pcie_pwr_switch; + break; +#endif + default: + return NULL; + } + + return adapter; +} +#else +struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf, + u8 cv, void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb) +{ + struct mac_ax_adapter *adapter = NULL; + struct mac_ax_hw_info *hw_info = NULL; + struct mac_ax_mac_pwr_info *pwr_info; + + if (!pltfm_cb) + return NULL; + + adapter = (struct mac_ax_adapter *)pltfm_cb->rtl_malloc(drv_adapter, + sizeof(struct mac_ax_adapter)); + if (!adapter) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "Malloc adapter fail\n"); + return NULL; + } + + pltfm_cb->rtl_memcpy(drv_adapter, adapter, &mac_8852b_adapter, + sizeof(struct mac_ax_adapter)); + + /*Alloc HW INFO */ + hw_info = (struct mac_ax_hw_info *)pltfm_cb->rtl_malloc(drv_adapter, + sizeof(struct mac_ax_hw_info)); + + if (!hw_info) { + pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "Malloc hw info fail\n"); + return NULL; + } + + if ((intf == MAC_AX_INTF_USB || intf == MAC_AX_INTF_PCIE) && + (cv == CAV || cv == CBV)) + pltfm_cb->rtl_memcpy(drv_adapter, hw_info, + &mac8852b_hw_info_cabv, + sizeof(struct mac_ax_hw_info)); + else + pltfm_cb->rtl_memcpy(drv_adapter, hw_info, + &mac8852b_hw_info, + sizeof(struct mac_ax_hw_info)); + + pwr_info = &adapter->mac_pwr_info; + + adapter->drv_adapter = drv_adapter; + adapter->pltfm_cb = pltfm_cb; + adapter->hw_info = hw_info; + adapter->hw_info->cv = cv; + adapter->hw_info->intf = intf; + adapter->hw_info->done = 1; + + switch (intf) { +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: + adapter->ops->intf_ops = &mac8852b_sdio_ops; + pwr_info->intf_pwr_switch = sdio_pwr_switch; + adapter->hw_info->pwr_on = mac_pwr_on_sdio_8852b; + adapter->hw_info->pwr_off = mac_pwr_off_sdio_8852b; + break; +#endif +#if MAC_AX_USB_SUPPORT + case MAC_AX_INTF_USB: + adapter->ops->intf_ops = &mac8852b_usb_ops; + pwr_info->intf_pwr_switch = usb_pwr_switch_8852b; + adapter->hw_info->pwr_on = mac_pwr_on_usb_8852b; + adapter->hw_info->pwr_off = mac_pwr_off_usb_8852b; + break; +#endif +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_INTF_PCIE: + adapter->ops->intf_ops = &mac8852b_pcie_ops; + pwr_info->intf_pwr_switch = pcie_pwr_switch; + adapter->hw_info->pwr_on = mac_pwr_on_pcie_8852b; + adapter->hw_info->pwr_off = mac_pwr_off_pcie_8852b; + break; +#endif + default: + return NULL; + } + + return adapter; +} +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.h b/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.h new file mode 100644 index 0000000..f1dd03b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.h @@ -0,0 +1,32 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_INIT_8852B_H_ +#define _MAC_AX_INIT_8852B_H_ + +#include "../../type.h" + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf, + u8 cv, void *phl_adapter, + void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb) +#else +struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf, + u8 cv, void *drv_adapter, + struct mac_ax_pltfm_cb *pltfm_cb); +#endif +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.c b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.c new file mode 100644 index 0000000..1374d73 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.c @@ -0,0 +1,1486 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../pwr.h" + +static struct mac_pwr_cfg mac_pwron_8852b[] = { + {0x1086, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), 0}, + {0x1086, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), BIT(1)}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), 0}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(2), 0}, + {0x0006, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), BIT(1)}, + {0x0006, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(0), 0}, + {0x0088, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0071, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(4), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), BIT(6)}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0001, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0001, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), 0}, + {0x0001, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), 0}, + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +static struct mac_pwr_cfg mac_pwroff_8852b[] = { + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x81}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0006, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0002, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(1), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(5), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), 0}, + {0x0091, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x0007, + PWR_CVALL_MSK, + PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(4), 0}, + {0x0007, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, + {0x0005, + PWR_CVALL_MSK, + PWR_INTF_MSK_USB | PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, + {0x1086, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x1086, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), 0}, + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +/* Power on sequence */ +struct mac_pwr_cfg *pwr_on_seq_8852b[] = { + mac_pwron_8852b, + NULL +}; + +/* Power off sequence */ +struct mac_pwr_cfg *pwr_off_seq_8852b[] = { + mac_pwroff_8852b, + NULL +}; + +#if MAC_AX_FEATURE_HV + +static struct mac_pwr_cfg mac_carddisable_seq_8852b[] = { + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +static struct mac_pwr_cfg mac_enterlps_seq_8852b[] = { + {0x0068, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), 0}, + {0x8394, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xC4}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xB4}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x41}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x42}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x43}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x7D}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x44}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x45}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x48}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(2), BIT(2)}, + {0x8398, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x8399, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x839A, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x48}, + {0x839B, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x8300, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x8322, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x8322, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), BIT(1)}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xA1}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x81}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(5), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0090, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xB0}, + {0x0091, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xA1}, + {0x0092, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0093, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0090, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xB0}, + {0x0091, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xA1}, + {0x0092, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x81}, + {0x0093, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0090, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0090, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(0), 0}, + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +static struct mac_pwr_cfg mac_leavelps_seq_8852b[] = { + {0x1083, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x10C1, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1203, + PWR_CVALL_MSK, + PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1E5, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), BIT(7)}, + {0x10, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_DELAY, PWR_DELAY_MS, PWR_DELAY_MS}, + {0x8322, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), 0}, + {0x8322, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(1), 0}, + {0x1083, + PWR_CVALL_MSK, + PWR_INTF_MSK_SDIO, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), 0}, + {0x10C1, + PWR_CVALL_MSK, + PWR_INTF_MSK_PCIE, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), 0}, + {0x1203, + PWR_CVALL_MSK, + PWR_INTF_MSK_USB, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(7), 0}, + {0x8304, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(6), BIT(6)}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0018, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x04}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x08}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x10}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x81}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0xA1}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x02}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0x0270, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0271, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0272, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x01}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_WRITE, 0xFF, 0x80}, + {0x0273, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + PWR_BASE_MAC, + PWR_CMD_POLL, BIT(7), 0}, + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +static struct mac_pwr_cfg mac_ips_seq_8852b[] = { + {0xFFFF, + PWR_CVALL_MSK, + PWR_INTF_MSK_ALL, + 0, + PWR_CMD_END, 0, 0}, +}; + +struct mac_pwr_cfg *card_disable_seq_8852b[] = { + mac_carddisable_seq_8852b, + NULL +}; + +struct mac_pwr_cfg *enter_lps_seq_8852b[] = { + mac_enterlps_seq_8852b, + NULL +}; + +struct mac_pwr_cfg *leave_lps_seq_8852b[] = { + mac_leavelps_seq_8852b, + NULL +}; + +struct mac_pwr_cfg *ips_seq_8852b[] = { + mac_ips_seq_8852b, + NULL +}; + +#endif + diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.h b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.h new file mode 100644 index 0000000..37594c0 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.h @@ -0,0 +1,30 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PWR_SEQ_8852B_H_ +#define _MAC_AX_PWR_SEQ_8852B_H_ + +//#define PWR_SEQ_VER_8852B 000 + +extern struct mac_pwr_cfg *pwr_on_seq_8852b[]; +extern struct mac_pwr_cfg *pwr_off_seq_8852b[]; +#if MAC_AX_FEATURE_HV +extern struct mac_pwr_cfg *card_disable_seq_8852b[]; +extern struct mac_pwr_cfg *enter_lps_seq_8852b[]; +extern struct mac_pwr_cfg *leave_lps_seq_8852b[]; +extern struct mac_pwr_cfg *ips_seq_8852b[]; +#endif +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.c b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.c new file mode 100644 index 0000000..305a53b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.c @@ -0,0 +1,2466 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../pwr.h" +#include "../pwr_seq_func.h" + +#if MAC_AX_8852B_SUPPORT + +#define SW_LPS_OPTION 0x0001A0B2 +#define PWR_K_CHK_OFFSET 0x5E9 +#define PWR_K_CHK_VALUE 0xAA + +u32 mac_pwr_on_sdio_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + u8 pwr_k_chk_value = 0; + u8 val8; + + /* 0x1086[0] = 0 == 0x1084[16] = 0 */ + val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL); + MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 & ~B_AX_HCI_SUS_REQ); + + /* polling 0x1086[1] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_SDIO_BUS_CTRL, B_AX_HCI_RESUME_RDY, + B_AX_HCI_RESUME_RDY); + if (ret) + return ret; + + /* 0x04[12:11] = 2'b00 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN | + B_AX_AFSM_PCIE_SUS_EN)); + + /* 0x04[18] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC); + + /* 0x90[1] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC); + + /* 0x04[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN); + + /* 0x04[10] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS); + + /* polling 0x04[17] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR, + B_AX_RDY_SYSPWR); + if (ret) + return ret; + + /* 0x20[23] = 1*/ + val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL); + MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN); + + /* polling 0x20[23] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN, + B_AX_AON_OFF_PC_EN); + if (ret) + return ret; + + /* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/ + val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); + val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); + MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32); + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x04[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC); + + /* polling 0x04[8] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0); + if (ret) + return ret; + + /* reset platform twice : 0x88[0] = 1->0->1->0 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + /* 0x88[0] = 1 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x24[6:4] = 3'b000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x26[3:0] = 4'b0000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0xCC[2] = 1 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* 0x00[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE); + + /* 0x00[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15))); + + PLTFM_DELAY_MS(1); + + /* 0x00[14] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14))); + + /* 0xCC[2] = 0 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* check power calibration is done or not */ + ret = mac_read_efuse_plus(adapter, PWR_K_CHK_OFFSET, 0x1, &pwr_k_chk_value, + MAC_AX_EFUSE_BANK_WIFI); + if (ret) + PLTFM_MSG_ERR("%s: read efuse fail\n", __func__); + + if (pwr_k_chk_value != PWR_K_CHK_VALUE) { + /* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */ + val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0); + val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); + val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); + MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32); + } + + return MACSUCCESS; +} + +u32 mac_pwr_on_usb_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + u8 pwr_k_chk_value = 0; + u8 val8; + + /* 0x04[12:11] = 2'b00 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN | + B_AX_AFSM_PCIE_SUS_EN)); + + /* 0x04[18] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC); + + /* 0x90[1] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC); + + /* 0x04[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN); + + /* 0x04[10] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS); + + /* polling 0x04[17] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR, + B_AX_RDY_SYSPWR); + if (ret) + return ret; + + /* 0x20[23] = 1*/ + val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL); + MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN); + + /* polling 0x20[23] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN, + B_AX_AON_OFF_PC_EN); + if (ret) + return ret; + + /* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/ + val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); + val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); + MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32); + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x04[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC); + + /* polling 0x04[8] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0); + if (ret) + return ret; + + /* reset platform twice : 0x88[0] = 1->0->1->0 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + /* 0x88[0] = 1 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x24[6:4] = 3'b000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x26[3:0] = 4'b0000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0xCC[2] = 1 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* 0x00[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE); + + /* 0x00[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15))); + + PLTFM_DELAY_MS(1); + + /* 0x00[14] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14))); + + /* 0xCC[2] = 0 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* check power calibration is done or not */ + ret = mac_read_efuse_plus(adapter, PWR_K_CHK_OFFSET, 0x1, &pwr_k_chk_value, + MAC_AX_EFUSE_BANK_WIFI); + if (ret) + PLTFM_MSG_ERR("%s: read efuse fail\n", __func__); + + if (pwr_k_chk_value != PWR_K_CHK_VALUE) { + /* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */ + val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0); + val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); + val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); + MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32); + } + + return MACSUCCESS; +} + +u32 mac_pwr_on_pcie_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u16 val16; + u8 xtal_si_val; + u8 pwr_k_chk_value = 0; + u8 val8; + + /* 0x04[12:11] = 2'b00 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN | + B_AX_AFSM_PCIE_SUS_EN)); + + /* 0x04[18] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC); + + /* 0x90[1] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC); + + /* 0x04[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN); + + /* 0x04[10] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS); + + /* polling 0x04[17] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR, + B_AX_RDY_SYSPWR); + if (ret) + return ret; + + /* 0x20[23] = 1*/ + val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL); + MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN); + + /* polling 0x20[23] = 1*/ + ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN, + B_AX_AON_OFF_PC_EN); + if (ret) + return ret; + + /* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/ + val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0); + val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); + val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); + MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32); + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x04[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC); + + /* polling 0x04[8] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0); + if (ret) + return ret; + + /* reset platform twice : 0x88[0] = 1->0->1->0 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN); + + /* 0x88[0] = 1 */ + val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE); + MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN); + + /* 0x70[12] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_SDIO_CTRL); + MAC_REG_W32(R_AX_SYS_SDIO_CTRL, val32 & ~B_AX_PCIE_CALIB_EN_V1); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x24[6:4] = 3'b000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x26[3:0] = 4'b0000 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0xCC[2] = 1 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* 0x00[8] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE); + + /* 0x00[15] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15))); + + PLTFM_DELAY_MS(1); + + /* 0x00[14] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL); + MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14))); + + /* 0xCC[2] = 0 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + /* check power calibration is done or not */ + ret = mac_read_efuse_plus(adapter, PWR_K_CHK_OFFSET, 0x1, &pwr_k_chk_value, + MAC_AX_EFUSE_BANK_WIFI); + if (ret) + PLTFM_MSG_ERR("%s: read efuse fail\n", __func__); + + if (pwr_k_chk_value != PWR_K_CHK_VALUE) { + /* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */ + val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0); + val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); + val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); + MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32); + + if (is_cv(adapter, CBV)) { + /* 0x7A[3:0] = 0xA and 0xCC[2]=1 */ + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | + B_AX_SYSON_DIS_PMCR_AX_WRMSK); + + val16 = MAC_REG_R16(R_AX_HCI_LDO_CTRL); + val16 = SET_CLR_WORD(val16, 0xA, B_AX_R_AX_VADJ); + MAC_REG_W16(R_AX_HCI_LDO_CTRL, val16); + + val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2); + MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & + ~B_AX_SYSON_DIS_PMCR_AX_WRMSK); + } + } + + return MACSUCCESS; +} + +u32 mac_pwr_off_sdio_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u8 val8; + u32 ret; + u8 xtal_si_val; + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x02[1:0] = 0 */ + val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB); + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x04[9] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC); + + /* polling 0x04[9] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0); + if (ret) + return ret; + + /* 0x04[28][30] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_SOP_EDSWR & + ~B_AX_SOP_EASWR); + + /* 0x04[12:11] = 2'b01 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, (val32 | B_AX_AFSM_WLSUS_EN) & + ~B_AX_AFSM_PCIE_SUS_EN); + + /* 0x1086[0] = 1 */ + val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL); + MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 | B_AX_HCI_SUS_REQ); + + #if 0 + /* polling 0x1086[1] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SDIO_BUS_CTRL, B_AX_HCI_RESUME_RDY, 0); + if (ret) + return ret; + #endif + + return MACSUCCESS; +} + +u32 mac_pwr_off_usb_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u8 val8; + u32 ret; + u8 xtal_si_val; + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x02[1:0] = 0 */ + val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB); + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x04[9] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC); + + /* polling 0x04[9] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0); + if (ret) + return ret; + + /* 0x04[28] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_SOP_EDSWR); + + /* 0x04[12:11] = 2'b01 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, (val32 | B_AX_AFSM_WLSUS_EN) & + ~B_AX_AFSM_PCIE_SUS_EN); + + return MACSUCCESS; +} + +u32 mac_pwr_off_pcie_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u8 val8; + u32 ret; + u8 xtal_si_val; + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* 0x04[16] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON); + + /* 0x02[1:0] = 0 */ + val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN); + MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB); + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x04[9] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC); + + /* polling 0x04[9] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0); + if (ret) + return ret; + + /* 0x91[0] = 0 == 0x90[8]=0 */ + //val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + //MAC_REG_W32(R_AX_WLLPS_CTRL, val32 & ~B_AX_LPSOP_DSWR); + + /* 0x90[31:0] = 0x00_01_A0_B2 */ + MAC_REG_W32(R_AX_WLLPS_CTRL, SW_LPS_OPTION); + + /* 0x04[10] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_SWLPS); + + return MACSUCCESS; +} + +#if MAC_AX_FEATURE_HV +u32 mac_enter_lps_sdio_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + + /* 0x280[6] = 1 */ + val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0); + MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS); + + /* 0x68[6] = 0 */ + val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL); + MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL); + + /* 0x8394[2] = 1 */ + val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL); + MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN); + + /* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4); + + /* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400); + + /* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004); + + /* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000); + + /* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00); + + /* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000); + + /* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001); + + /* polling 0x8398[2] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2)); + if (ret) + return ret; + + /* 0x8398[1] = 1 */ + val32 = MAC_REG_R32(R_AX_32K_CAL_REG0); + MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1)); + + /* 0x8399[7:0] = 0x00 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00); + + /* 0x839A[7:0] = 0x48 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48); + + /* 0x839B[7:0] = 0x80 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80); + + /* 0x8300[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1IMR); + MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN); + + /* 0x8322[0] = 1 == 0x8320[16] =1 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, + B_AX_TSF_CLK_STABLE); + if (ret) + return ret; + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x90[31:0] = 0x04_80_A1_B0 */ + MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0480A1B0); + + /* 0x90[0] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN); + + /* polling 0x90[0] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_enter_lps_usb_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + + /* 0x280[6] = 1 */ + val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0); + MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS); + + /* 0x68[6] = 0 */ + val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL); + MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL); + + /* 0x8394[2] = 1 */ + val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL); + MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN); + + /* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4); + + /* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400); + + /* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004); + + /* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000); + + /* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00); + + /* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000); + + /* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001); + + /* polling 0x8398[2] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2)); + if (ret) + return ret; + + /* 0x8398[1] = 1 */ + val32 = MAC_REG_R32(R_AX_32K_CAL_REG0); + MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1)); + + /* 0x8399[7:0] = 0x00 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00); + + /* 0x839A[7:0] = 0x48 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48); + + /* 0x839B[7:0] = 0x80 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80); + + /* 0x8300[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1IMR); + MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN); + + /* 0x8322[0] = 1 == 0x8320[16] =1 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, + B_AX_TSF_CLK_STABLE); + if (ret) + return ret; + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x90[31:0] = 0x04_81_A1_B0 */ + MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0481A1B0); + + /* 0x90[0] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN); + + /* polling 0x90[0] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_enter_lps_pcie_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + + /* 0x280[6] = 1 */ + val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0); + MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS); + + /* 0x68[6] = 0 */ + val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL); + MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL); + + /* 0x8394[2] = 1 */ + val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL); + MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN); + + /* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4); + + /* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400); + + /* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004); + + /* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000); + + /* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00); + + /* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000); + + /* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */ + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001); + MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001); + + /* polling 0x8398[2] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2)); + if (ret) + return ret; + + /* 0x8398[1] = 1 */ + val32 = MAC_REG_R32(R_AX_32K_CAL_REG0); + MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1)); + + /* 0x8399[7:0] = 0x00 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00); + + /* 0x839A[7:0] = 0x48 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48); + + /* 0x839B[7:0] = 0x80 */ + MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80); + + /* 0x8300[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1IMR); + MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN); + + /* 0x8322[0] = 1 == 0x8320[16] =1 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, + B_AX_TSF_CLK_STABLE); + if (ret) + return ret; + + /* DAV CAV */ + /* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[7] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[4] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x80[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 0 */ + /* XTAL_SI 0x90[5] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[6] = 0 */ + /* XTAL_SI 0x90[6] = 0 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x90[31:0] = 0x04_81_A1_B0 */ + MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0481A1B0); + + /* 0x90[0] = 1 */ + val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); + MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN); + + /* polling 0x90[0] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_leave_lps_sdio_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + u32 cnt = 320; + + /* 0x1083[7] = 1 == 0x1080[31] = 1 */ + val32 = MAC_REG_R32(R_AX_SDIO_HRPWM1); + MAC_REG_W32(R_AX_SDIO_HRPWM1, val32 | BIT(31)); + + /* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_RPWM, + B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE); + if (ret) + return ret; + + /* delay 0x10 ms */ + while (--cnt) + PLTFM_DELAY_US(50); + + /* 0x8322[0] = 0 == 0x8320[16] = 0 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0); + if (ret) + return ret; + + /* 0x1083[7] = 0 == 0x1080[31] = 0 */ + val32 = MAC_REG_R32(R_AX_SDIO_HRPWM1); + MAC_REG_W32(R_AX_SDIO_HRPWM1, val32 & ~(BIT(31))); + + /* 0x8304[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1ISR); + MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x80[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + return MACSUCCESS; +} + +u32 mac_leave_lps_usb_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + u32 cnt = 320; + + /* 0x1203[7] = 1 == 0x1200[31] = 1 */ + val32 = MAC_REG_R32(R_AX_USB_D2F_F2D_INFO); + MAC_REG_W32(R_AX_USB_D2F_F2D_INFO, val32 | BIT(31)); + + /* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_RPWM, + B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE); + if (ret) + return ret; + + /* delay 0x10 ms */ + while (--cnt) + PLTFM_DELAY_US(50); + + /* 0x8322[0] = 0 == 0x8320[16] = 0 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0); + if (ret) + return ret; + + /* 0x1203[7] = 0 == 0x1200[31] = 0 */ + val32 = MAC_REG_R32(R_AX_USB_D2F_F2D_INFO); + MAC_REG_W32(R_AX_USB_D2F_F2D_INFO, val32 & ~(BIT(31))); + + /* 0x8304[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1ISR); + MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x80[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + return MACSUCCESS; +} + +u32 mac_leave_lps_pcie_8852b(void *vadapter) +{ + struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 xtal_si_val; + u32 cnt = 320; + + /* 0x10C1[7] = 1 == 0x10C0[15] = 1 */ + val32 = MAC_REG_R32(R_AX_PCIE_HRPWM); + MAC_REG_W32(R_AX_PCIE_HRPWM, val32 | BIT(15)); + + /* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */ + ret = pwr_poll_u32(adapter, R_AX_RPWM, + B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE); + if (ret) + return ret; + + /* delay 0x10 ms */ + while (--cnt) + PLTFM_DELAY_US(50); + + /* 0x8322[0] = 0 == 0x8320[16] = 0 */ + val32 = MAC_REG_R32(R_AX_TSF_32K_SEL); + MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF); + + /* polling 0x8322[1] = 0 */ + ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0); + if (ret) + return ret; + + /* 0x10C1[7] = 0 */ + val32 = MAC_REG_R32(R_AX_PCIE_HRPWM); + MAC_REG_W32(R_AX_PCIE_HRPWM, val32 & ~(BIT(15))); + + /* 0x8304[0] = 1 */ + val32 = MAC_REG_R32(R_AX_FWD1ISR); + MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT); + + /* 0x18[6] = 1 */ + /* XTAL_SI 0x90[6] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* 0x18[5] = 1 */ + /* XTAL_SI 0x90[5] = 1 */ + val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL); + MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3); + + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + /* XTAL_SI 0x90[4] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x80[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x81[0] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0xA1[1] = 0 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* XTAL_SI 0x90[7] = 1 */ + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + + /* DAV CAV */ + /* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */ + /* DAV after CBV */ + /* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */ + ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val); + if (ret) { + PLTFM_MSG_ERR("Read XTAL_SI fail!\n"); + return ret; + } + + xtal_si_val = (xtal_si_val & 0x0F); + + if (xtal_si_val == CAV) { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } else { + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01); + if (ret) { + PLTFM_MSG_ERR("Write XTAL_SI fail!\n"); + return ret; + } + } + + return MACSUCCESS; +} + +#endif + +#endif /* #if MAC_AX_8852B_SUPPORT */ diff --git a/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.h b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.h new file mode 100644 index 0000000..c73873c --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.h @@ -0,0 +1,43 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PWR_SEQ_FUNC_8852B_H_ +#define _MAC_AX_PWR_SEQ_FUNC_8852B_H_ + +#include "../../mac_def.h" +#if MAC_AX_8852B_SUPPORT + +#define PWR_SEQ_VER_8852B 10 + +u32 mac_pwr_on_sdio_8852b(void *vadapter); +u32 mac_pwr_on_usb_8852b(void *vadapter); +u32 mac_pwr_on_pcie_8852b(void *vadapter); + +u32 mac_pwr_off_sdio_8852b(void *vadapter); +u32 mac_pwr_off_usb_8852b(void *vadapter); +u32 mac_pwr_off_pcie_8852b(void *vadapter); +#if MAC_AX_FEATURE_HV +u32 mac_enter_lps_sdio_8852b(void *vadapter); +u32 mac_enter_lps_usb_8852b(void *vadapter); +u32 mac_enter_lps_pcie_8852b(void *vadapter); + +u32 mac_leave_lps_sdio_8852b(void *vadapter); +u32 mac_leave_lps_usb_8852b(void *vadapter); +u32 mac_leave_lps_pcie_8852b(void *vadapter); + +#endif /* #if MAC_AX_FEATURE_HV */ +#endif /* #if MAC_AX_8852B_SUPPORT */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_ax_dfs.h b/phl/hal_g6/mac/mac_ax/mac_ax_dfs.h new file mode 100644 index 0000000..e7df7ab --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_ax_dfs.h @@ -0,0 +1,28 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_DFS_H_ +#define _MAC_AX_DFS_H_ + +/* dword0 */ +#define AX_DFS_DROP_NUM_SH 0 +#define AX_DFS_DROP_NUM_MSK 0xffff +#define AX_DFS_MAX_CONT_DROP_SH 16 +#define AX_DFS_MAX_CONT_DROP_MSK 0xff +#define AX_DFS_TOTAL_DROP_SH 24 +#define AX_DFS_TOTAL_DROP_MSK 0xff + +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_ax_mac_info.h b/phl/hal_g6/mac/mac_ax/mac_ax_mac_info.h new file mode 100644 index 0000000..4835eaa --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_ax_mac_info.h @@ -0,0 +1,47 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_MAC_INFO_H_ +#define _MAC_AX_MAC_INFO_H_ + +/* dword0 */ +#define AX_MAC_INFO_USR_NUM_SH 0 +#define AX_MAC_INFO_USR_NUM_MSK 0xf +#define AX_MAC_INFO_FW_DEFINE_SH 8 +#define AX_MAC_INFO_FW_DEFINE_MSK 0xff +#define AX_MAC_INFO_LSIG_LEN_SH 16 +#define AX_MAC_INFO_LSIG_LEN_MSK 0xfff +#define AX_MAC_INFO_IS_TO_SELF BIT(28) +#define AX_MAC_INFO_RX_CNT_VLD BIT(29) +#define AX_MAC_INFO_LONG_RXD_SH 30 +#define AX_MAC_INFO_LONG_RXD_MSK 0x3 + +/* dword1 */ +#define AX_MAC_INFO_SERVICE_SH 0 +#define AX_MAC_INFO_SERVICE_MSK 0xffff +#define AX_MAC_INFO_PLCP_LEN_SH 16 +#define AX_MAC_INFO_PLCP_LEN_MSK 0xff + +/* dword2 */ +#define AX_MAC_INFO_MAC_ID_VALID BIT(0) +#define AX_MAC_INFO_HAS_DATA BIT(1) +#define AX_MAC_INFO_HAS_CTRL BIT(2) +#define AX_MAC_INFO_HAS_MGNT BIT(3) +#define AX_MAC_INFO_HAS_BCN BIT(4) +#define AX_MAC_INFO_MACID_SH 8 +#define AX_MAC_INFO_MACID_MSK 0xff + +#endif diff --git a/phl/hal_g6/mac/mac_ax/mac_txccxrpt.h b/phl/hal_g6/mac/mac_ax/mac_txccxrpt.h new file mode 100644 index 0000000..a5e101a --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mac_txccxrpt.h @@ -0,0 +1,146 @@ +#ifndef _MAC_TXCCXRPT_H_ +#define _MAC_TXCCXRPT_H_ + +/* dword0 */ +#define TXCCXRPT_RPT_SEL_SH 0 +#define TXCCXRPT_RPT_SEL_MSK 0x1f +#define TXCCXRPT_POLLUTED BIT(5) +#define TXCCXRPT_TX_STATE_SH 6 +#define TXCCXRPT_TX_STATE_MSK 0x3 +#define TXCCXRPT_SW_DEFINE_SH 8 +#define TXCCXRPT_SW_DEFINE_MSK 0xf +#define TXCCXRPT_TRY_RATE BIT(14) +#define TXCCXRPT_FIXRATE BIT(15) +#define TXCCXRPT_MACID_SH 16 +#define TXCCXRPT_MACID_MSK 0x7f +#define TXCCXRPT_QSEL_SH 24 +#define TXCCXRPT_QSEL_MSK 0x3f +#define TXCCXRPT_TXOP_START BIT(31) + +/* dword1 */ +#define TXCCXRPT_QUEUE_TIME_SH 0 +#define TXCCXRPT_QUEUE_TIME_MSK 0xffff +#define TXCCXRPT_ACCTXTIME_SH 16 +#define TXCCXRPT_ACCTXTIME_MSK 0xff +#define TXCCXRPT_BMC BIT(29) +#define TXCCXRPT_BITMAP_SHORT_SH 30 +#define TXCCXRPT_BITMAP_SHORT_MSK 0x3 + +/* dword2 */ +#define TXCCXRPT_FINAL_RATE_SH 0 +#define TXCCXRPT_FINAL_RATE_MSK 0x1ff +#define TXCCXRPT_FINAL_GI_LTF_SH 9 +#define TXCCXRPT_FINAL_GI_LTF_MSK 0x7 +#define TXCCXRPT_DATA_BW_SH 12 +#define TXCCXRPT_DATA_BW_MSK 0x3 +#define TXCCXRPT_MU2SU BIT(14) +#define TXCCXRPT_MU_LMT BIT(15) +#define TXCCXRPT_FINAL_RTS_RATE_SH 16 +#define TXCCXRPT_FINAL_RTS_RATE_MSK 0x1ff +#define TXCCXRPT_FINAL_RTS_GI_LTF_SH 25 +#define TXCCXRPT_FINAL_RTS_GI_LTF_MSK 0x7 +#define TXCCXRPT_RTS_TX_STATE_SH 28 +#define TXCCXRPT_RTS_TX_STATE_MSK 0x3 +#define TXCCXRPT_COLLISION_HEAD BIT(30) +#define TXCCXRPT_COLLISION_TAIL BIT(31) + +/* dword3 */ +#define TXCCXRPT_TOTAL_PKT_NUM_SH 0 +#define TXCCXRPT_TOTAL_PKT_NUM_MSK 0xff +#define TXCCXRPT_DATA_TX_CNT_SH 8 +#define TXCCXRPT_DATA_TX_CNT_MSK 0x3f +#define TXCCXRPT_BPRI BIT(14) +#define TXCCXRPT_BBAR BIT(15) +#define TXCCXRPT_PKT_OK_NUM_SH 16 +#define TXCCXRPT_PKT_OK_NUM_MSK 0xff +#define TXCCXRPT_RTS_TX_COUNT_SH 24 +#define TXCCXRPT_RTS_TX_COUNT_MSK 0x3f + +/* dword4 */ +#define TXCCXRPT_INIT_RATE_SH 0 +#define TXCCXRPT_INIT_RATE_MSK 0x1ff +#define TXCCXRPT_INIT_GI_LTF_SH 9 +#define TXCCXRPT_INIT_GI_LTF_MSK 0x7 +#define TXCCXRPT_PPDU_TYPE_SH 12 +#define TXCCXRPT_PPDU_TYPE_MSK 0x3 +#define TXCCXRPT_HE_TB_PPDU_FLAG BIT(14) +#define TXCCXRPT_PPDU_FST_RPT BIT(15) +#define TXCCXRPT_SU_TXPWR_SH 16 +#define TXCCXRPT_SU_TXPWR_MSK 0x3f +#define TXCCXRPT_DIFF_PKT_NUM_SH 24 +#define TXCCXRPT_DIFF_PKT_NUM_MSK 0xf +#define TXCCXRPT_USER_DEFINE_EXT_L_SH 28 +#define TXCCXRPT_USER_DEFINE_EXT_L_MSK 0xf + +/* dword5 */ +#define TXCCXRPT_USER_DEFINE_SH 0 +#define TXCCXRPT_USER_DEFINE_MSK 0xff +#define TXCCXRPT_FW_DEFINE_SH 8 +#define TXCCXRPT_FW_DEFINE_MSK 0xff +#define TXCCXRPT_TXPWR_PD_SH 16 +#define TXCCXRPT_TXPWR_PD_MSK 0x1f +#define TXCCXRPT_BSR BIT(21) +#define TXCCXRPT_SR_RX_COUNT_SH 24 +#define TXCCXRPT_SR_RX_COUNT_MSK 0xf +#define TXCCXRPT_USER_DEFINE_EXT_H_SH 28 +#define TXCCXRPT_USER_DEFINE_EXT_H_MSK 0xf + +struct mac_ccxrpt { + /* dword 0 */ + u32 rpt_sel:5; + u32 polluted:1; + u32 tx_state:2; + u32 sw_define:4; + u32 rsvd0:2; + u32 try_rate:1; + u32 fixrate:1; + u32 macid:7; + u32 rsvd1:1; + u32 qsel:6; + u32 rsvd2:1; + u32 txop_start:1; + /* dword 1 */ + u32 queue_time:16; + u32 acctxtime:8; + u32 rsvd3:5; + u32 bmc:1; + u32 bitmap_short:2; + /* dword 2 */ + u32 final_rate:9; + u32 final_gi_ltf:3; + u32 data_bw:2; + u32 mu2su:1; + u32 mu_lmt:1; + u32 final_rts_rate:9; + u32 final_rts_gi_ltf:3; + u32 rts_tx_state:2; + u32 collision_head:1; + u32 collision_tail:1; + /* dword 3 */ + u32 total_pkt_num:8; + u32 data_tx_cnt:6; + u32 bpri:1; + u32 bbar:1; + u32 pkt_ok_num:8; + u32 rts_tx_count:6; + u32 rsvd4:2; + /* dword 4 */ + u32 init_rate:9; + u32 init_gi_ltf:3; + u32 ppdu_type:2; + u32 he_tb_ppdu_flag:1; + u32 ppdu_fst_rpt:1; + u32 su_txpwr:6; + u32 rsvd5:2; + u32 diff_pkt_num:4; + u32 user_define_ext_l:4; + /* dword 5 */ + u32 user_define:8; + u32 fw_define:8; + u32 txpwr_pd:5; + u32 bsr:1; + u32 rsvd6:2; + u32 sr_rx_count:4; + u32 user_define_ext_h:4; +}; +#endif diff --git a/phl/hal_g6/mac/mac_ax/mcc.c b/phl/hal_g6/mac/mac_ax/mcc.c new file mode 100644 index 0000000..cb74eef --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mcc.c @@ -0,0 +1,945 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "mcc.h" + +u32 mac_reset_mcc_group(struct mac_ax_adapter *adapter, u8 group) +{ + struct fwcmd_reset_mcc_group *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (adapter->sm.mcc_group[group] != MAC_AX_MCC_STATE_ERROR) { + PLTFM_MSG_ERR("[ERR]%s: state != error\n", __func__); + return MACPROCERR; + } + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_reset_mcc_group)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_reset_mcc_group *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_RESET_MCC_GROUP_GROUP)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_RESET_MCC_GROUP, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_reset_mcc_request(struct mac_ax_adapter *adapter, u8 group) +{ + if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_FAIL) { + PLTFM_MSG_ERR("[ERR]%s: state != req fail\n", __func__); + return MACPROCERR; + } + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_IDLE; + + return MACSUCCESS; +} + +u32 mac_add_mcc(struct mac_ax_adapter *adapter, struct mac_ax_mcc_role *info) +{ + struct fwcmd_add_mcc *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (!(adapter->sm.mcc_group[info->group] == MAC_AX_MCC_EMPTY || + adapter->sm.mcc_group[info->group] == MAC_AX_MCC_ADD_DONE)) { + PLTFM_MSG_ERR("[ERR]%s: state != empty or add done\n", + __func__); + return MACPROCERR; + } + + adapter->sm.mcc_group[info->group] = MAC_AX_MCC_STATE_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_add_mcc)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_add_mcc *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_ADD_MCC_MACID) | + SET_WORD(info->central_ch_seg0, + FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0) | + SET_WORD(info->central_ch_seg1, + FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1) | + SET_WORD(info->primary_ch, FWCMD_H2C_ADD_MCC_PRIMARY_CH)); + + ptr->dword1 = + cpu_to_le32((info->dis_tx_null ? FWCMD_H2C_ADD_MCC_DIS_TX_NULL : 0) | + (info->dis_sw_retry ? FWCMD_H2C_ADD_MCC_DIS_SW_RETRY : 0) | + (info->in_curr_ch ? FWCMD_H2C_ADD_MCC_IN_CURR_CH : 0) | + SET_WORD(info->bandwidth, FWCMD_H2C_ADD_MCC_BANDWIDTH) | + SET_WORD(info->group, FWCMD_H2C_ADD_MCC_GROUP) | + SET_WORD(info->c2h_rpt, FWCMD_H2C_ADD_MCC_C2H_RPT) | + SET_WORD(info->sw_retry_count, + FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT) | + SET_WORD(info->tx_null_early, + FWCMD_H2C_ADD_MCC_TX_NULL_EARLY) | + (info->btc_in_2g ? FWCMD_H2C_ADD_MCC_BTC_IN_2G : 0) | + (info->pta_en ? FWCMD_H2C_ADD_MCC_PTA_EN : 0) | + (info->rfk_by_pass ? FWCMD_H2C_ADD_MCC_RFK_BY_PASS : 0)); + + ptr->dword2 = + cpu_to_le32(SET_WORD(info->duration, FWCMD_H2C_ADD_MCC_DURATION)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_ADD_MCC, 0, 0); + + ptr->dword3 = + cpu_to_le32((info->courtesy_en ? FWCMD_H2C_ADD_MCC_COURTESY_EN : 0) | + SET_WORD(info->courtesy_num, + FWCMD_H2C_ADD_MCC_COURTESY_NUM) | + SET_WORD(info->courtesy_target, + FWCMD_H2C_ADD_MCC_COURTESY_TARGET)); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_start_mcc(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_start *info) +{ + struct fwcmd_start_mcc *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + u32 group = info->group; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, info->group); + return MACNOITEM; + } + + if (adapter->sm.mcc_group[info->group] != MAC_AX_MCC_ADD_DONE) { + PLTFM_MSG_ERR("[ERR]%s: state != add done\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_group[info->group] = MAC_AX_MCC_STATE_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_start_mcc)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_start_mcc *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(info->group, FWCMD_H2C_START_MCC_GROUP) | + (info->btc_in_group ? FWCMD_H2C_START_MCC_BTC_IN_GROUP : 0) | + SET_WORD(info->old_group_action, + FWCMD_H2C_START_MCC_OLD_GROUP_ACTION) | + SET_WORD(info->old_group, FWCMD_H2C_START_MCC_OLD_GROUP) | + SET_WORD(info->macid, FWCMD_H2C_START_MCC_MACID)); + + ptr->dword1 = + cpu_to_le32(SET_WORD(info->tsf_low, FWCMD_H2C_START_MCC_TSF_LOW)); + + ptr->dword2 = + cpu_to_le32(SET_WORD(info->tsf_high, FWCMD_H2C_START_MCC_TSF_HIGH)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_START_MCC, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_stop_mcc(struct mac_ax_adapter *adapter, u8 group, u8 macid, + u8 prev_groups) +{ + struct fwcmd_stop_mcc *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + if (adapter->sm.mcc_group[group] != MAC_AX_MCC_START_DONE) { + PLTFM_MSG_ERR("[ERR]%s: state != start done\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_stop_mcc)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_stop_mcc *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_STOP_MCC_GROUP) | + SET_WORD(macid, FWCMD_H2C_STOP_MCC_MACID) | + (prev_groups ? FWCMD_H2C_STOP_MCC_PREV_GROUPS : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_STOP_MCC, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_del_mcc_group(struct mac_ax_adapter *adapter, u8 group, + u8 prev_groups) +{ + struct fwcmd_del_mcc_group *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + if (!(adapter->sm.mcc_group[group] == MAC_AX_MCC_ADD_DONE || + adapter->sm.mcc_group[group] == MAC_AX_MCC_STOP_DONE)) { + PLTFM_MSG_ERR("[ERR]%s: state != add or stop done\n", + __func__); + return MACPROCERR; + } + + adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_del_mcc_group)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_del_mcc_group *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_DEL_MCC_GROUP_GROUP) | + (prev_groups ? FWCMD_H2C_DEL_MCC_GROUP_PREV_GROUPS : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_DEL_MCC_GROUP, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_mcc_request_tsf(struct mac_ax_adapter *adapter, u8 group, + u8 macid_x, u8 macid_y) +{ + struct fwcmd_mcc_req_tsf *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) { + PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_req_tsf)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_mcc_req_tsf *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_REQ_TSF_GROUP) | + SET_WORD(macid_x, FWCMD_H2C_MCC_REQ_TSF_MACID_X) | + SET_WORD(macid_y, FWCMD_H2C_MCC_REQ_TSF_MACID_Y)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_MCC_REQ_TSF, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_mcc_macid_bitmap(struct mac_ax_adapter *adapter, u8 group, + u8 macid, u8 *bitmap, u8 len) +{ + struct fwcmd_mcc_macid_bitmap *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) { + PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, len + 4); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_mcc_macid_bitmap *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_MACID_BITMAP_GROUP) | + SET_WORD(macid, FWCMD_H2C_MCC_MACID_BITMAP_MACID) | + SET_WORD(len, FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH)); + + PLTFM_MEMCPY((u8 *)ptr + sizeof(u32), bitmap, len); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_MCC_MACID_BITMAP, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx error %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_mcc_sync_enable(struct mac_ax_adapter *adapter, u8 group, + u8 source, u8 target, u8 offset) +{ + struct fwcmd_mcc_sync *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) { + PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_sync)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_mcc_sync *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_SYNC_GROUP) | + SET_WORD(source, FWCMD_H2C_MCC_SYNC_MACID_SOURCE) | + SET_WORD(target, FWCMD_H2C_MCC_SYNC_MACID_TARGET) | + SET_WORD(offset, FWCMD_H2C_MCC_SYNC_SYNC_OFFSET)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_MCC_SYNC, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx error %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_mcc_set_duration(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_duration_info *info) +{ + struct fwcmd_mcc_set_duration *ptr; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + u32 ret = 0; + + if (adapter->sm.mcc_request[info->group] != MAC_AX_MCC_REQ_IDLE) { + PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__); + return MACPROCERR; + } + + adapter->sm.mcc_request[info->group] = MAC_AX_MCC_REQ_H2C_SENT; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_set_duration)); + if (!buf) { + PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__); + ret = MACNOBUF; + goto fail; + } + + ptr = (struct fwcmd_mcc_set_duration *)buf; + ptr->dword0 = + cpu_to_le32(SET_WORD(info->group, FWCMD_H2C_MCC_SET_DURATION_GROUP) | + (info->btc_in_group ? + FWCMD_H2C_MCC_SET_DURATION_BTC_IN_GROUP : 0) | + SET_WORD(info->start_macid, + FWCMD_H2C_MCC_SET_DURATION_START_MACID) | + SET_WORD(info->macid_x, + FWCMD_H2C_MCC_SET_DURATION_MACID_X) | + SET_WORD(info->macid_y, + FWCMD_H2C_MCC_SET_DURATION_MACID_Y)); + ptr->dword1 = + cpu_to_le32(SET_WORD(info->start_tsf_low, + FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW)); + + ptr->dword2 = + cpu_to_le32(SET_WORD(info->start_tsf_high, + FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH)); + + ptr->dword3 = + cpu_to_le32(SET_WORD(info->duration_x, + FWCMD_H2C_MCC_SET_DURATION_DURATION_X)); + + ptr->dword4 = + cpu_to_le32(SET_WORD(info->duration_y, + FWCMD_H2C_MCC_SET_DURATION_DURATION_Y)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MCC, + FWCMD_H2C_FUNC_MCC_SET_DURATION, 0, 0); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]%s: platform tx err %d\n", __func__, ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_get_mcc_status_rpt(struct mac_ax_adapter *adapter, + u8 group, u8 *status, u32 *tsf_high, u32 *tsf_low) +{ + struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info; + + if (adapter->sm.mcc_group[group] == MAC_AX_MCC_EMPTY) { + PLTFM_MSG_ERR("[ERR]%s: state = empty\n", __func__); + return MACPROCERR; + } + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + *status = mcc_info->groups[group].rpt_status; + PLTFM_MSG_TRACE("[TRACE]%s: mcc status: %d\n", __func__, *status); + + *tsf_high = mcc_info->groups[group].rpt_tsf_high; + *tsf_low = mcc_info->groups[group].rpt_tsf_low; + + PLTFM_MSG_TRACE("[TRACE]%s: report tsf_high: 0x%x\n", + __func__, *tsf_high); + PLTFM_MSG_TRACE("[TRACE]%s: report tsf_low: 0x%x\n", + __func__, *tsf_low); + + return MACSUCCESS; +} + +u32 mac_get_mcc_tsf_rpt(struct mac_ax_adapter *adapter, u8 group, + u32 *tsf_x_high, u32 *tsf_x_low, + u32 *tsf_y_high, u32 *tsf_y_low) +{ + struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info; + + if (group > MCC_GROUP_ID_MAX) { + PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group); + return MACNOITEM; + } + + *tsf_x_high = mcc_info->groups[group].tsf_x_high; + *tsf_x_low = mcc_info->groups[group].tsf_x_low; + PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_high: 0x%x\n", __func__, *tsf_x_high); + PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_low: 0x%x\n", __func__, *tsf_x_low); + + *tsf_y_high = mcc_info->groups[group].tsf_y_high; + *tsf_y_low += mcc_info->groups[group].tsf_y_low; + PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_high: 0x%x\n", __func__, *tsf_y_high); + PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_low: 0x%x\n", __func__, *tsf_y_low); + + adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_IDLE; + + return MACSUCCESS; +} + +u32 mac_get_mcc_group(struct mac_ax_adapter *adapter, u8 *pget_group) +{ + struct mac_ax_state_mach *sm = &adapter->sm; + u8 group_idx; + + for (group_idx = 0; group_idx <= MCC_GROUP_ID_MAX; group_idx++) { + if (sm->mcc_group[group_idx] == MAC_AX_MCC_EMPTY) { + *pget_group = group_idx; + PLTFM_MSG_TRACE("[TRACE]%s: get mcc empty group %u\n", + __func__, *pget_group); + return MACSUCCESS; + } + } + return MACMCCGPFL; +} + +u32 mac_check_add_mcc_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_group[group] == MAC_AX_MCC_ADD_DONE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_start_mcc_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_group[group] == MAC_AX_MCC_START_DONE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_stop_mcc_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_group[group] == MAC_AX_MCC_STOP_DONE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_del_mcc_group_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_group[group] == MAC_AX_MCC_EMPTY) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_mcc_request_tsf_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_DONE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_mcc_macid_bitmap_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_mcc_sync_enable_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_check_mcc_set_duration_done(struct mac_ax_adapter *adapter, u8 group) +{ + PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__, + group, adapter->sm.mcc_group[group]); + + if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + diff --git a/phl/hal_g6/mac/mac_ax/mcc.h b/phl/hal_g6/mac/mac_ax/mcc.h new file mode 100644 index 0000000..b8d818b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mcc.h @@ -0,0 +1,413 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_MCC_H_ +#define _MAC_AX_MCC_H_ + +#include "../type.h" +#include "fwcmd.h" + +#define MCC_GROUP_ID_MAX 3 + +/** + * @addtogroup MCC + * @{ + */ +/** + * @brief mac_reset_mcc_group + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_reset_mcc_group(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_reset_mcc_request + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_reset_mcc_request(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_add_mcc + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_mcc(struct mac_ax_adapter *adapter, struct mac_ax_mcc_role *info); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_start_mcc + * + * @param *adapter + * @param group + * @param macid + * @param tsf_high + * @param tsf_low + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_start_mcc(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_start *info); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_stop_mcc + * + * @param *adapter + * @param group + * @param macid + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_stop_mcc(struct mac_ax_adapter *adapter, u8 group, u8 macid, + u8 prev_groups); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_del_mcc_group + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_del_mcc_group(struct mac_ax_adapter *adapter, u8 group, + u8 prev_groups); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_mcc_request_tsf + * + * @param *adapter + * @param group + * @param macid_x + * @param macid_y + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mcc_request_tsf(struct mac_ax_adapter *adapter, u8 group, + u8 macid_x, u8 macid_y); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_mcc_macid_bitmap + * + * @param *adapter + * @param group + * @param macid + * @param *bitmap + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mcc_macid_bitmap(struct mac_ax_adapter *adapter, u8 group, + u8 macid, u8 *bitmap, u8 len); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_mcc_sync_enable + * + * @param *adapter + * @param group + * @param source + * @param target + * @param offset + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mcc_sync_enable(struct mac_ax_adapter *adapter, u8 group, + u8 source, u8 target, u8 offset); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_mcc_set_duration + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mcc_set_duration(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_duration_info *info); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_get_mcc_status_rpt + * + * @param *adapter + * @param group + * @param *status + * @param *tsf_high + * @param *tsf_low + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_mcc_status_rpt(struct mac_ax_adapter *adapter, + u8 group, u8 *status, u32 *tsf_high, u32 *tsf_low); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_get_mcc_tsf_rpt + * + * @param *adapter + * @param group + * @param *tsf_x_high + * @param *tsf_x_low + * @param *tsf_y_high + * @param *tsf_y_low + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_mcc_tsf_rpt(struct mac_ax_adapter *adapter, u8 group, + u32 *tsf_x_high, u32 *tsf_x_low, + u32 *tsf_y_high, u32 *tsf_y_low); +/** + * @} + */ +u32 mac_get_mcc_group(struct mac_ax_adapter *adapter, u8 *pget_group); +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_add_mcc_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_add_mcc_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_start_mcc_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_start_mcc_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_stop_mcc_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_stop_mcc_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_del_mcc_group_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_del_mcc_group_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_mcc_request_tsf_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_mcc_request_tsf_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_mcc_macid_bitmap_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_mcc_macid_bitmap_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_mcc_sync_enable_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_mcc_sync_enable_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +/** + * @addtogroup MCC + * @{ + */ + +/** + * @brief mac_check_mcc_set_duration_done + * + * @param *adapter + * @param group + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_mcc_set_duration_done(struct mac_ax_adapter *adapter, u8 group); +/** + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/mport.c b/phl/hal_g6/mac/mac_ax/mport.c new file mode 100644 index 0000000..a9f1200 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mport.c @@ -0,0 +1,2688 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "mport.h" +#include "../mac_ax.h" + +#define MAX_TSF_SOURCE_PORT 7 +#define MAX_TSF_TARGET_PORT 4 +#define MAX_TSF_SYNC_OFFSET 0x3FFFF + +static u32 cfg_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_PORT_CFG_P0, R_AX_PORT_CFG_P1, R_AX_PORT_CFG_P2, + R_AX_PORT_CFG_P3, R_AX_PORT_CFG_P4}, + {R_AX_PORT_CFG_P0_C1, R_AX_PORT_CFG_P1_C1, R_AX_PORT_CFG_P2_C1, + R_AX_PORT_CFG_P3_C1, R_AX_PORT_CFG_P4_C1} +}; + +static u32 phb_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_TBTT_PROHIB_P0, R_AX_TBTT_PROHIB_P1, R_AX_TBTT_PROHIB_P1, + R_AX_TBTT_PROHIB_P1, R_AX_TBTT_PROHIB_P1}, + {R_AX_TBTT_PROHIB_P0_C1, R_AX_TBTT_PROHIB_P1_C1, R_AX_TBTT_PROHIB_P1_C1, + R_AX_TBTT_PROHIB_P1_C1, R_AX_TBTT_PROHIB_P1_C1} +}; + +static u32 ctnarea_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCN_AREA_P0, R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P1, + R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P1}, + {R_AX_BCN_AREA_P0_C1, R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P1_C1, + R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P1_C1} +}; + +static u32 mskarea_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCN_AREA_P0, R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P2, + R_AX_BCN_AREA_P3, R_AX_BCN_AREA_P4}, + {R_AX_BCN_AREA_P0_C1, R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P2_C1, + R_AX_BCN_AREA_P3_C1, R_AX_BCN_AREA_P4_C1} +}; + +static u32 tbttagg_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_TBTT_AGG_P0, R_AX_TBTT_AGG_P1, R_AX_TBTT_AGG_P2, + R_AX_TBTT_AGG_P3, R_AX_TBTT_AGG_P4}, + {R_AX_TBTT_AGG_P0_C1, R_AX_TBTT_AGG_P1_C1, R_AX_TBTT_AGG_P2_C1, + R_AX_TBTT_AGG_P3_C1, R_AX_TBTT_AGG_P4_C1} +}; + +static u32 tbttery_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_TBTTERLYINT_CFG_P0, R_AX_TBTTERLYINT_CFG_P1, + R_AX_TBTTERLYINT_CFG_P2, R_AX_TBTTERLYINT_CFG_P3, + R_AX_TBTTERLYINT_CFG_P4}, + {R_AX_TBTTERLYINT_CFG_P0_C1, R_AX_TBTTERLYINT_CFG_P1_C1, + R_AX_TBTTERLYINT_CFG_P2_C1, R_AX_TBTTERLYINT_CFG_P3_C1, + R_AX_TBTTERLYINT_CFG_P4_C1} +}; + +static u32 bcnspc_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCN_SPACE_CFG_P0, R_AX_BCN_SPACE_CFG_P1, R_AX_BCN_SPACE_CFG_P2, + R_AX_BCN_SPACE_CFG_P3, R_AX_BCN_SPACE_CFG_P4}, + {R_AX_BCN_SPACE_CFG_P0_C1, R_AX_BCN_SPACE_CFG_P1_C1, + R_AX_BCN_SPACE_CFG_P2_C1, R_AX_BCN_SPACE_CFG_P3_C1, + R_AX_BCN_SPACE_CFG_P4_C1} +}; + +static u32 tbttsht_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_TBTT_SHIFT_P0, R_AX_TBTT_SHIFT_P1, R_AX_TBTT_SHIFT_P2, + R_AX_TBTT_SHIFT_P3, R_AX_TBTT_SHIFT_P4}, + {R_AX_TBTT_SHIFT_P0_C1, R_AX_TBTT_SHIFT_P1_C1, R_AX_TBTT_SHIFT_P2_C1, + R_AX_TBTT_SHIFT_P3_C1, R_AX_TBTT_SHIFT_P4_C1} +}; + +static u32 bcndrp_regl[MAC_AX_BAND_NUM] = { + R_AX_BCN_DROP_ALL0, R_AX_BCN_DROP_ALL0_C1 +}; + +static u32 mbssid_drp_regl[MAC_AX_BAND_NUM] = { + R_AX_BCN_DROP_ALL0_P0MB, R_AX_BCN_DROP_ALL0_P0MB_C1 +}; + +static u32 bcnpsr_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCN_PSR_RPT_P0, R_AX_BCN_PSR_RPT_P1, R_AX_BCN_PSR_RPT_P2, + R_AX_BCN_PSR_RPT_P3, R_AX_BCN_PSR_RPT_P4}, + {R_AX_BCN_PSR_RPT_P0_C1, R_AX_BCN_PSR_RPT_P1_C1, R_AX_BCN_PSR_RPT_P2_C1, + R_AX_BCN_PSR_RPT_P3_C1, R_AX_BCN_PSR_RPT_P4_C1} +}; + +static u32 cnt_tmr_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCN_CNT_TMR_P0, R_AX_BCN_CNT_TMR_P1, R_AX_BCN_CNT_TMR_P2, + R_AX_BCN_CNT_TMR_P3, R_AX_BCN_CNT_TMR_P4}, + {R_AX_BCN_CNT_TMR_P0_C1, R_AX_BCN_CNT_TMR_P1_C1, R_AX_BCN_CNT_TMR_P2_C1, + R_AX_BCN_CNT_TMR_P3_C1, R_AX_BCN_CNT_TMR_P4_C1} +}; + +static u32 hiq_win_port_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, + R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, + R_AX_PORT_HGQ_WINDOW_CFG + 3}, + {R_AX_P0MB_HGQ_WINDOW_CFG_0_C1, R_AX_PORT_HGQ_WINDOW_CFG_C1, + R_AX_PORT_HGQ_WINDOW_CFG_C1 + 1, R_AX_PORT_HGQ_WINDOW_CFG_C1 + 2, + R_AX_PORT_HGQ_WINDOW_CFG_C1 + 3} +}; + +static u32 hiq_win_mbid_regl[MAC_AX_BAND_NUM][MAC_AX_P0_MBID_MAX] = { + {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_P0MB_HGQ_WINDOW_CFG_0 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_0 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_0 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_1, R_AX_P0MB_HGQ_WINDOW_CFG_1 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_1 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_2, R_AX_P0MB_HGQ_WINDOW_CFG_2 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_2 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_2 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_3, R_AX_P0MB_HGQ_WINDOW_CFG_3 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_3 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_3 + 3}, + {R_AX_P0MB_HGQ_WINDOW_CFG_0_C1, R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_1_C1, R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_2_C1, R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 3, + R_AX_P0MB_HGQ_WINDOW_CFG_3_C1, R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 1, + R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 3} +}; + +static u32 dtim_prd_port_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_DTIM_CTRL_P0 + 1, R_AX_DTIM_CTRL_P1 + 1, + R_AX_DTIM_CTRL_P2 + 1, R_AX_DTIM_CTRL_P3 + 1, + R_AX_DTIM_CTRL_P4 + 1}, + {R_AX_DTIM_CTRL_P0_C1 + 1, R_AX_DTIM_CTRL_P1_C1 + 1, + R_AX_DTIM_CTRL_P2_C1 + 1, R_AX_DTIM_CTRL_P3_C1 + 1, + R_AX_DTIM_CTRL_P4_C1 + 1} +}; + +static u32 dtim_prd_mbid_regl[MAC_AX_BAND_NUM][MAC_AX_P0_MBID_MAX] = { + {R_AX_DTIM_CTRL_P0 + 1, R_AX_DTIM_NUM0 + 1, R_AX_DTIM_NUM0 + 2, + R_AX_DTIM_NUM0 + 3, R_AX_DTIM_NUM1, R_AX_DTIM_NUM1 + 1, + R_AX_DTIM_NUM1 + 2, R_AX_DTIM_NUM1 + 3, R_AX_DTIM_NUM2, + R_AX_DTIM_NUM2 + 1, R_AX_DTIM_NUM2 + 2, R_AX_DTIM_NUM2 + 3, + R_AX_DTIM_NUM3, R_AX_DTIM_NUM3 + 1, R_AX_DTIM_NUM3 + 2, + R_AX_DTIM_NUM3 + 3}, + {R_AX_DTIM_CTRL_P0_C1 + 1, R_AX_DTIM_NUM0_C1 + 1, R_AX_DTIM_NUM0_C1 + 2, + R_AX_DTIM_NUM0_C1 + 3, R_AX_DTIM_NUM1_C1, R_AX_DTIM_NUM1_C1 + 1, + R_AX_DTIM_NUM1_C1 + 2, R_AX_DTIM_NUM1_C1 + 3, R_AX_DTIM_NUM2_C1, + R_AX_DTIM_NUM2_C1 + 1, R_AX_DTIM_NUM2_C1 + 2, R_AX_DTIM_NUM2_C1 + 3, + R_AX_DTIM_NUM3_C1, R_AX_DTIM_NUM3_C1 + 1, R_AX_DTIM_NUM3_C1 + 2, + R_AX_DTIM_NUM3_C1 + 3} +}; + +static u32 dtim_switch[MAC_AX_BAND_NUM] = { + R_AX_MD_TSFT_STMP_CTL, R_AX_MD_TSFT_STMP_CTL_C1 +}; + +static u32 hiq_nolmt_regl[MAC_AX_BAND_NUM] = { + R_AX_EN_HGQ_NOLIMIT, R_AX_EN_HGQ_NOLIMIT_C1 +}; + +static u32 mbid_ctrl_regl[MAC_AX_BAND_NUM] = { + R_AX_MBSSID_CTRL, R_AX_MBSSID_CTRL_C1 +}; + +static u32 bcn_early_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_BCNERLYINT_CFG_P0, R_AX_BCNERLYINT_CFG_P1, + R_AX_BCNERLYINT_CFG_P2, R_AX_BCNERLYINT_CFG_P3, + R_AX_BCNERLYINT_CFG_P4}, + {R_AX_BCNERLYINT_CFG_P0_C1, R_AX_BCNERLYINT_CFG_P1_C1, + R_AX_BCNERLYINT_CFG_P2_C1, R_AX_BCNERLYINT_CFG_P3_C1, + R_AX_BCNERLYINT_CFG_P4_C1} +}; + +static u32 tsfl_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_TSFTR_LOW_P0, R_AX_TSFTR_LOW_P1, R_AX_TSFTR_LOW_P2, + R_AX_TSFTR_LOW_P3, R_AX_TSFTR_LOW_P4}, + {R_AX_TSFTR_LOW_P0_C1, R_AX_TSFTR_LOW_P1_C1, R_AX_TSFTR_LOW_P2_C1, + R_AX_TSFTR_LOW_P3_C1, R_AX_TSFTR_LOW_P4_C1} +}; + +static u32 ptcl_dbg_regl[MAC_AX_BAND_NUM] = { + R_AX_PTCL_DBG, R_AX_PTCL_DBG_C1 +}; + +static u32 bss_color_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = { + {R_AX_PTCL_BSS_COLOR_0, + R_AX_PTCL_BSS_COLOR_0, + R_AX_PTCL_BSS_COLOR_0, + R_AX_PTCL_BSS_COLOR_0, + R_AX_PTCL_BSS_COLOR_1}, + {R_AX_PTCL_BSS_COLOR_0_C1, + R_AX_PTCL_BSS_COLOR_0_C1, + R_AX_PTCL_BSS_COLOR_0_C1, + R_AX_PTCL_BSS_COLOR_0_C1, + R_AX_PTCL_BSS_COLOR_1_C1} +}; + +static u32 ptcl_dbg_info_regl[MAC_AX_BAND_NUM] = { + R_AX_PTCL_DBG_INFO, R_AX_PTCL_DBG_INFO_C1 +}; + +static u32 b_en_l[MAC_AX_PORT_NUM] = { + B_AX_PORT_FUNC_EN_P0, B_AX_PORT_FUNC_EN_P1, B_AX_PORT_FUNC_EN_P2, + B_AX_PORT_FUNC_EN_P3, B_AX_PORT_FUNC_EN_P4 +}; + +static u32 b_txbcnrpt_l[MAC_AX_PORT_NUM] = { + B_AX_TXBCN_RPT_EN_P0, B_AX_TXBCN_RPT_EN_P1, B_AX_TXBCN_RPT_EN_P2, + B_AX_TXBCN_RPT_EN_P3, B_AX_TXBCN_RPT_EN_P4 +}; + +static u32 b_rxbcnrpt_l[MAC_AX_PORT_NUM] = { + B_AX_RXBCN_RPT_EN_P0, B_AX_RXBCN_RPT_EN_P1, B_AX_RXBCN_RPT_EN_P2, + B_AX_RXBCN_RPT_EN_P3, B_AX_RXBCN_RPT_EN_P4 +}; + +static u32 b_rxupd_l[MAC_AX_PORT_NUM] = { + B_AX_RX_BSSID_FIT_EN_P0, B_AX_RX_BSSID_FIT_EN_P1, + B_AX_RX_BSSID_FIT_EN_P2, B_AX_RX_BSSID_FIT_EN_P3, + B_AX_RX_BSSID_FIT_EN_P4 +}; + +static u32 b_rxtsfupd_l[MAC_AX_PORT_NUM] = { + B_AX_TSF_UDT_EN_P0, B_AX_TSF_UDT_EN_P1, B_AX_TSF_UDT_EN_P2, + B_AX_TSF_UDT_EN_P3, B_AX_TSF_UDT_EN_P4 +}; + +static u32 b_bcntxen_l[MAC_AX_PORT_NUM] = { + B_AX_BCNTX_EN_P0, B_AX_BCNTX_EN_P1, B_AX_BCNTX_EN_P2, + B_AX_BCNTX_EN_P3, B_AX_BCNTX_EN_P4 +}; + +static u32 b_phben_l[MAC_AX_PORT_NUM] = { + B_AX_TBTT_PROHIB_EN_P0, B_AX_TBTT_PROHIB_EN_P1, B_AX_TBTT_PROHIB_EN_P2, + B_AX_TBTT_PROHIB_EN_P3, B_AX_TBTT_PROHIB_EN_P4 +}; + +static u32 b_shten_l[MAC_AX_PORT_NUM] = { + B_AX_TBTT_UPD_SHIFT_SEL_P0, B_AX_TBTT_UPD_SHIFT_SEL_P1, + B_AX_TBTT_UPD_SHIFT_SEL_P2, B_AX_TBTT_UPD_SHIFT_SEL_P3, + B_AX_TBTT_UPD_SHIFT_SEL_P4 +}; + +static u32 b_brken_l[MAC_AX_PORT_NUM] = { + B_AX_BRK_SETUP_P0, B_AX_BRK_SETUP_P1, B_AX_BRK_SETUP_P2, + B_AX_BRK_SETUP_P3, B_AX_BRK_SETUP_P4 +}; + +static u32 b_rsttsf_l[MAC_AX_PORT_NUM] = { + B_AX_TSFTR_RST_P0, B_AX_TSFTR_RST_P1, B_AX_TSFTR_RST_P2, + B_AX_TSFTR_RST_P3, B_AX_TSFTR_RST_P4 +}; + +static u32 b_drpall_l[MAC_AX_PORT_NUM] = { + B_AX_BCN_DROP_ALL_P0, B_AX_BCN_DROP_ALL_P1, B_AX_BCN_DROP_ALL_P2, + B_AX_BCN_DROP_ALL_P3, B_AX_BCN_DROP_ALL_P4 +}; + +static u32 b_rptvld_l[MAC_AX_PORT_NUM] = { + B_AX_RPT_VALID_P0, B_AX_RPT_VALID_P1, B_AX_RPT_VALID_P2, + B_AX_RPT_VALID_P3, B_AX_RPT_VALID_P4 +}; + +static u32 b_timerr_l[MAC_AX_PORT_NUM] = { + B_AX_TIM_ILEGAL_P0, B_AX_TIM_ILEGAL_P1, B_AX_TIM_ILEGAL_P2, + B_AX_TIM_ILEGAL_P3, B_AX_TIM_ILEGAL_P4 +}; + +static u32 b_mbid_en_l[MAC_AX_P0_MBID_MAX - 1] = { + B_AX_P0MB1_EN, B_AX_P0MB2_EN, B_AX_P0MB3_EN, B_AX_P0MB4_EN, + B_AX_P0MB5_EN, B_AX_P0MB6_EN, B_AX_P0MB7_EN, B_AX_P0MB8_EN, + B_AX_P0MB9_EN, B_AX_P0MB10_EN, B_AX_P0MB11_EN, B_AX_P0MB12_EN, + B_AX_P0MB13_EN, B_AX_P0MB14_EN, B_AX_P0MB15_EN +}; + +static u32 b_mbid_drp_l[MAC_AX_P0_MBID_MAX - 1] = { + B_AX_BCN_DROP_ALL_P0MB1, B_AX_BCN_DROP_ALL_P0MB2, + B_AX_BCN_DROP_ALL_P0MB3, B_AX_BCN_DROP_ALL_P0MB4, + B_AX_BCN_DROP_ALL_P0MB5, B_AX_BCN_DROP_ALL_P0MB6, + B_AX_BCN_DROP_ALL_P0MB7, B_AX_BCN_DROP_ALL_P0MB8, + B_AX_BCN_DROP_ALL_P0MB9, B_AX_BCN_DROP_ALL_P0MB10, + B_AX_BCN_DROP_ALL_P0MB11, B_AX_BCN_DROP_ALL_P0MB12, + B_AX_BCN_DROP_ALL_P0MB13, B_AX_BCN_DROP_ALL_P0MB14, + B_AX_BCN_DROP_ALL_P0MB15 +}; + +static u32 b_hiq_nolmt_mbid_l[MAC_AX_P0_MBID_MAX - 1] = { + B_AX_HIQ_NO_LMT_EN_P0_VAP1, B_AX_HIQ_NO_LMT_EN_P0_VAP2, + B_AX_HIQ_NO_LMT_EN_P0_VAP3, B_AX_HIQ_NO_LMT_EN_P0_VAP4, + B_AX_HIQ_NO_LMT_EN_P0_VAP5, B_AX_HIQ_NO_LMT_EN_P0_VAP6, + B_AX_HIQ_NO_LMT_EN_P0_VAP7, B_AX_HIQ_NO_LMT_EN_P0_VAP8, + B_AX_HIQ_NO_LMT_EN_P0_VAP9, B_AX_HIQ_NO_LMT_EN_P0_VAP10, + B_AX_HIQ_NO_LMT_EN_P0_VAP11, B_AX_HIQ_NO_LMT_EN_P0_VAP12, + B_AX_HIQ_NO_LMT_EN_P0_VAP13, B_AX_HIQ_NO_LMT_EN_P0_VAP14, + B_AX_HIQ_NO_LMT_EN_P0_VAP15 +}; + +static u32 b_hiq_nolmt_port_l[MAC_AX_PORT_NUM] = { + B_AX_HIQ_NO_LMT_EN_P0_ROOT, B_AX_HIQ_NO_LMT_EN_P1, + B_AX_HIQ_NO_LMT_EN_P2, B_AX_HIQ_NO_LMT_EN_P3, B_AX_HIQ_NO_LMT_EN_P4 +}; + +static u32 mbid_idx_l[MAC_AX_P0_MBID_MAX] = { + MAC_AX_P0_ROOT, MAC_AX_P0_MBID1, MAC_AX_P0_MBID2, MAC_AX_P0_MBID3, + MAC_AX_P0_MBID4, MAC_AX_P0_MBID5, MAC_AX_P0_MBID6, MAC_AX_P0_MBID7, + MAC_AX_P0_MBID8, MAC_AX_P0_MBID9, MAC_AX_P0_MBID10, MAC_AX_P0_MBID11, + MAC_AX_P0_MBID12, MAC_AX_P0_MBID13, MAC_AX_P0_MBID14, MAC_AX_P0_MBID15 +}; + +static u32 t32_togl_rpt_size = + sizeof(struct mac_ax_t32_togl_rpt) * MAC_AX_BAND_NUM * MAC_AX_PORT_NUM; +static u32 port_info_size = + sizeof(struct mac_ax_port_info) * MAC_AX_BAND_NUM * MAC_AX_PORT_NUM; + +static u32 _get_max_mbid(struct mac_ax_adapter *adapter, u8 *mbid_max) +{ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + *mbid_max = MAC_AX_P0_MBID15; + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + *mbid_max = MAC_AX_P0_MBID3; + else + return MACCHIPID; + + return MACSUCCESS; +} + +u32 get_bp_idx(u8 band, u8 port) +{ + return (band * MAC_AX_BAND_NUM + port); +} + +u32 _get_port_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_port_cfg_type type, + struct mac_ax_port_cfg_para *para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 mbssid_idx = para->mbssid_idx; + u8 port = para->port; + u8 band = para->band; + u32 val32; + u16 val16; + u8 mbid_max; + u32 ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + band != MAC_AX_BAND_0) { + PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band); + return MACFUNCINPUT; + } + + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port); + return MACPORTCFGPORT; + } + + if (mbssid_idx) { + ret = _get_max_mbid(adapter, &mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret); + return MACPORTCFGPORT; + } + + if (mbssid_idx > (u32)mbid_max) { + PLTFM_MSG_ERR("[ERR] invalid mbssid %d\n", mbssid_idx); + return MACFUNCINPUT; + } + } + + switch (type) { + case MAC_AX_PCFG_NET_TYPE: + val32 = MAC_REG_R32(cfg_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val32, B_AX_NET_TYPE_P0); + break; + case MAC_AX_PORT_1: + para->val = GET_FIELD(val32, B_AX_NET_TYPE_P1); + break; + case MAC_AX_PORT_2: + para->val = GET_FIELD(val32, B_AX_NET_TYPE_P2); + break; + case MAC_AX_PORT_3: + para->val = GET_FIELD(val32, B_AX_NET_TYPE_P3); + break; + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_NET_TYPE_P4); + break; + } + break; + + case MAC_AX_PCFG_FUNC_SW: + val32 = MAC_REG_R32(cfg_regl[band][port]); + if (val32 & b_en_l[port]) + para->val = 1; + else + para->val = 0; + break; + + case MAC_AX_PCFG_BCN_INTV: + val32 = MAC_REG_R32(bcnspc_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = mbssid_idx ? + GET_FIELD(val32, B_AX_SUB_BCN_SPACE_P0) : + GET_FIELD(val32, B_AX_BCN_SPACE_P0); + break; + case MAC_AX_PORT_1: + para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P1); + break; + case MAC_AX_PORT_2: + para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P2); + break; + case MAC_AX_PORT_3: + para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P3); + break; + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P4); + break; + } + break; + + case MAC_AX_PCFG_BCN_HOLD_TIME: + val32 = MAC_REG_R32(phb_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val32, B_AX_TBTT_HOLD_P0); + break; + case MAC_AX_PORT_1: + case MAC_AX_PORT_2: + case MAC_AX_PORT_3: + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_TBTT_HOLD_P1); + break; + } + break; + + case MAC_AX_PCFG_BCN_ERLY: + val32 = MAC_REG_R32(bcn_early_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val32, B_AX_BCNERLY_P0); + break; + case MAC_AX_PORT_1: + para->val = GET_FIELD(val32, B_AX_BCNERLY_P1); + break; + case MAC_AX_PORT_2: + para->val = GET_FIELD(val32, B_AX_BCNERLY_P2); + break; + case MAC_AX_PORT_3: + para->val = GET_FIELD(val32, B_AX_BCNERLY_P3); + break; + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_BCNERLY_P4); + break; + } + break; + + case MAC_AX_PCFG_BCN_SETUP_TIME: + val32 = MAC_REG_R32(phb_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val32, B_AX_TBTT_SETUP_P0); + break; + case MAC_AX_PORT_1: + case MAC_AX_PORT_2: + case MAC_AX_PORT_3: + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_TBTT_SETUP_P1); + break; + } + break; + + case MAC_AX_PCFG_TBTT_ERLY: + val16 = MAC_REG_R16(tbttery_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val16, B_AX_TBTTERLY_P0); + break; + case MAC_AX_PORT_1: + para->val = GET_FIELD(val16, B_AX_TBTTERLY_P1); + break; + case MAC_AX_PORT_2: + para->val = GET_FIELD(val16, B_AX_TBTTERLY_P2); + break; + case MAC_AX_PORT_3: + para->val = GET_FIELD(val16, B_AX_TBTTERLY_P3); + break; + case MAC_AX_PORT_4: + para->val = GET_FIELD(val16, B_AX_TBTTERLY_P4); + break; + } + break; + case MAC_AX_PCFG_BCN_MASK_AREA: + val32 = MAC_REG_R32(mskarea_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P0); + break; + case MAC_AX_PORT_1: + para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P1); + break; + case MAC_AX_PORT_2: + para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P2); + break; + case MAC_AX_PORT_3: + para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P3); + break; + case MAC_AX_PORT_4: + para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P4); + break; + } + break; + default: + PLTFM_MSG_ERR("[ERR] invalid get cfg type %d\n", type); + return MACPORTCFGTYPE; + } + + return MACSUCCESS; +} + +static u32 _port_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_port_cfg_type type, + struct mac_ax_port_cfg_para *para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 set_val = para->val; + u8 port = para->port; + u8 band = para->band; + u32 val32; + u32 w_val32 = MAC_AX_R32_DEAD; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + band != MAC_AX_BAND_0) { + PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band); + return MACFUNCINPUT; + } + + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port); + return MACPORTCFGPORT; + } + + switch (type) { + case MAC_AX_PCFG_NET_TYPE: + val32 = MAC_REG_R32(cfg_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_NET_TYPE_P0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_NET_TYPE_P1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_NET_TYPE_P2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_NET_TYPE_P3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_NET_TYPE_P4); + break; + } + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + default: + PLTFM_MSG_ERR("[ERR] invalid cfg type %d\n", type); + return MACPORTCFGTYPE; + } + + return MACSUCCESS; +} + +static u32 _bcn_setup_chk(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 *set_val) +{ + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_port_info *pinfo_self, *pinfo_tmp; + u32 ret; + u32 up_lmt = 0xFFFFFFFF; + u8 port_idx; + + pinfo_self = &adapter->port_info[get_bp_idx(band, port)]; + + if (port == MAC_AX_PORT_0 && pinfo_self->stat == PORT_ST_DIS) + return MACSUCCESS; + + if (*set_val > B_AX_TBTT_SETUP_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal bcn setup time %d\n", *set_val); + return MACFUNCINPUT; + } + + for (port_idx = MAC_AX_PORT_0; port_idx < MAC_AX_PORT_NUM; port_idx++) { + pinfo_tmp = &adapter->port_info[get_bp_idx(band, port_idx)]; + if (pinfo_tmp->stat == PORT_ST_DIS) + continue; + if (port != MAC_AX_PORT_0 && port_idx == MAC_AX_PORT_0) + continue; + + cfg_para.band = band; + cfg_para.port = port_idx; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n", + ret); + return ret; + } + + if (cfg_para.val < up_lmt) + up_lmt = cfg_para.val; + + if (port == MAC_AX_PORT_0) + break; + } + + if (*set_val >= up_lmt) { + PLTFM_MSG_WARN("[WARN]setup time %d over hw limit\n", *set_val); + *set_val = up_lmt - 1; + return MACSETVALERR; + } + + return MACSUCCESS; +} + +static u32 _bcn_mask_chk(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 *set_val) +{ + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_port_info *pinfo; + u32 ret; + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + if (pinfo->stat == PORT_ST_DIS) + return MACSUCCESS; + + if (*set_val > B_AX_BCN_MSK_AREA_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal mask area %d\n", *set_val); + return MACFUNCINPUT; + } + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn hold fail %d\n", ret); + return ret; + } + if (*set_val > cfg_para.val) { + PLTFM_MSG_WARN("[WARN]mask area %d over hw limit\n", *set_val); + *set_val = cfg_para.val; + return MACSETVALERR; + } + + return MACSUCCESS; +} + +static u32 _bcn_hold_chk(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 *set_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_port_info *pinfo_self, *pinfo_tmp; + u32 ret, bcn_erly, bcn_spc, val32; + u8 port_idx; + u32 low_lmt = 0, up_lmt = 0xFFFFFFFF; + + pinfo_self = &adapter->port_info[get_bp_idx(band, port)]; + + if (port == MAC_AX_PORT_0 && pinfo_self->stat == PORT_ST_DIS) + return MACSUCCESS; + + if (*set_val > B_AX_TBTT_HOLD_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal hold time %d\n", *set_val); + return MACFUNCINPUT; + } + + for (port_idx = MAC_AX_PORT_0; port_idx < MAC_AX_PORT_NUM; port_idx++) { + pinfo_tmp = &adapter->port_info[get_bp_idx(band, port_idx)]; + if (pinfo_tmp->stat == PORT_ST_DIS) + continue; + if (port != MAC_AX_PORT_0 && port_idx == MAC_AX_PORT_0) + continue; + + cfg_para.band = band; + cfg_para.port = port_idx; + cfg_para.mbssid_idx = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, + &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg mask area fail %d\n", + ret); + return ret; + } + + if (cfg_para.val > low_lmt) + low_lmt = cfg_para.val; + + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n", + ret); + return ret; + } + bcn_erly = cfg_para.val; + + if (port == MAC_AX_PORT_0 && + GET_FIELD(MAC_REG_R32(mbid_ctrl_regl[band]), B_AX_P0MB_NUM)) + cfg_para.mbssid_idx = 1; + else + cfg_para.mbssid_idx = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn intv fail %d\n", + ret); + return ret; + } + bcn_spc = cfg_para.val; + + val32 = bcn_spc * TU_TO_BCN_SET - bcn_erly; + if (val32 < up_lmt) + up_lmt = val32; + + if (port == MAC_AX_PORT_0) + break; + } + + if (*set_val < low_lmt) { + PLTFM_MSG_WARN("[WARN]hold time %d below hw limit\n", *set_val); + *set_val = low_lmt; + return MACSETVALERR; + } + + if (*set_val >= up_lmt) { + PLTFM_MSG_WARN("[WARN]hold time %d over hw limit\n", *set_val); + *set_val = up_lmt - 1; + return MACSETVALERR; + } + + return MACSUCCESS; +} + +static u32 _bcn_erly_chk(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 *set_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_port_info *pinfo; + u32 ret, bcn_hold, bcn_spc, val32; + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + if (pinfo->stat == PORT_ST_DIS) + return MACSUCCESS; + + if (*set_val > B_AX_BCNERLY_P0_MSK || !*set_val) { + PLTFM_MSG_ERR("[ERR] illegal bcn erly %d\n", *set_val); + return MACFUNCINPUT; + } + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn setup fail %d\n", ret); + return ret; + } + if (*set_val <= cfg_para.val) { + PLTFM_MSG_WARN("[WARN]bcn erly %d below hw limit\n", *set_val); + *set_val = cfg_para.val + 1; + return MACSETVALERR; + } + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg tbtt erly fail %d\n", ret); + return ret; + } + val32 = cfg_para.val / BCN_SET_TO_US; + if (*set_val <= val32) { + PLTFM_MSG_WARN("[WARN]bcn erly %d below hw limit\n", *set_val); + *set_val = val32 + 1; + return MACSETVALERR; + } + + cfg_para.band = band; + cfg_para.port = port; + if (port == MAC_AX_PORT_0 && + GET_FIELD(MAC_REG_R32(mbid_ctrl_regl[band]), B_AX_P0MB_NUM)) + cfg_para.mbssid_idx = 1; + else + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn intv fail %d\n", ret); + return ret; + } + bcn_spc = cfg_para.val; + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get port cfg bcn hold fail %d\n", ret); + return ret; + } + bcn_hold = cfg_para.val; + + val32 = bcn_spc * TU_TO_BCN_SET - bcn_hold; + if (*set_val >= val32) { + PLTFM_MSG_WARN("[WARN]bcn erly %d over hw limit\n", *set_val); + *set_val = val32 - 1; + return MACSETVALERR; + } + + return MACSUCCESS; +} + +static u32 _tbtt_erly_chk(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 *set_val) +{ + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_port_info *pinfo; + u32 ret, val32; + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + if (pinfo->stat == PORT_ST_DIS) + return MACSUCCESS; + + if (*set_val > B_AX_TBTTERLY_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal tbtt erly %d\n", *set_val); + return MACFUNCINPUT; + } + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n", ret); + return ret; + } + val32 = cfg_para.val * BCN_SET_TO_US; + if (*set_val >= val32) { + PLTFM_MSG_WARN("[WARN] tbtt erly %d over hw limit\n", *set_val); + *set_val = val32 - 1; + return MACSETVALERR; + } + + return MACSUCCESS; +} + +static u32 _set_max_mbid_num(struct mac_ax_adapter *adapter, + struct mac_ax_port_cfg_para *para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + u8 port = para->port; + u8 band = para->band; + u32 mbid_num = para->mbssid_idx; + u32 ret; + u32 bcn_erly; + u32 hold_time; + u32 subspc; + u32 val32, w_val32; + + if (mbid_num && !(mbid_num % 2)) + mbid_num++; + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d get cfg bcn_erly fail %d\n", + band, port, ret); + return ret; + } + bcn_erly = cfg_para.val; + + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d get cfg hold_time fail %d\n", + band, port, ret); + return ret; + } + hold_time = cfg_para.val; + + subspc = para->val / (mbid_num + 1); + if (bcn_erly + hold_time > subspc * TU_TO_BCN_SET) { + PLTFM_MSG_ERR("[ERR] BcnSubspc not enough for erly and hold time\n"); + para->val = (bcn_erly + hold_time) / TU_TO_BCN_SET * (mbid_num + 1); + return MACSUBSPCERR; + } + + //set interval + cfg_para.val = para->val; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn intv fail %d\n", + band, port, ret); + return ret; + } + + //set mbssid num + val32 = MAC_REG_R32(mbid_ctrl_regl[band]); + w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); + if (val32 != w_val32) + MAC_REG_W32(mbid_ctrl_regl[band], w_val32); + + //set subspace + val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]); + if (mbid_num) + w_val32 = SET_CLR_WORD(val32, subspc, B_AX_SUB_BCN_SPACE_P0); + else + w_val32 = SET_CLR_WORD(val32, 0, B_AX_SUB_BCN_SPACE_P0); + if (w_val32 != val32) + MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], w_val32); + + return MACSUCCESS; +} + +static u32 port0_mbid_set(struct mac_ax_adapter *adapter, u8 band, u8 mbid_num, + u8 mbid_max) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, w_val32, i; + + val32 = MAC_REG_R32(mbid_ctrl_regl[band]); + w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); + + for (i = 0; i < mbid_max; i++) { + if (i >= (MAC_AX_P0_MBID_MAX - 1)) { + PLTFM_MSG_ERR("mbid en idx %d over array %d\n", i, + MAC_AX_P0_MBID_MAX - 1); + return MACCMP; + } + w_val32 &= ~b_mbid_en_l[i]; + } + + if (w_val32 != val32) + MAC_REG_W32(mbid_ctrl_regl[band], w_val32); + + return MACSUCCESS; +} + +static u32 port0_subspc_set(struct mac_ax_adapter *adapter, u8 band, + u8 mbid_num, u32 *bcn_erly, u32 *hold_time) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 subspc_u32; + u32 val32, w_val32; + u32 ret = MACSUCCESS; + + val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]); + subspc_u32 = mbid_num ? + (GET_FIELD(val32, B_AX_BCN_SPACE_P0) / (mbid_num + 1)) : 0; + if (subspc_u32 > B_AX_SUB_BCN_SPACE_P0_MSK) { + PLTFM_MSG_ERR("[ERR] sub space %d overflow\n", subspc_u32); + return MACSUBSPCERR; + } + + w_val32 = SET_CLR_WORD(val32, subspc_u32, B_AX_SUB_BCN_SPACE_P0); + if (w_val32 != val32) + MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], w_val32); + + subspc_u32 *= TU_TO_BCN_SET; + if (mbid_num && (BCN_HOLD_DEF + BCN_ERLY_DEF) > subspc_u32) { + *bcn_erly = subspc_u32 * BCN_ERLY_RATIO / BCN_ITVL_RATIO; + *hold_time = subspc_u32 * BCN_HOLD_RATIO / BCN_ITVL_RATIO; + } + + return ret; +} + +u32 dly_port_tu(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_tu) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 cnt; + u32 ori_tsf; + u32 dly_us = dly_tu * TU_UNIT; + + cnt = dly_tu * PORT_DLY_TU_CNT_LMT; + ori_tsf = MAC_REG_R32(tsfl_regl[band][port]); + PLTFM_DELAY_US(TU_UNIT); + do { + val32 = MAC_REG_R32(tsfl_regl[band][port]); + if ((val32 >= ori_tsf && + (val32 - ori_tsf) >= dly_us) || + (val32 < ori_tsf && + (ori_tsf - val32 + 1) >= dly_us)) + break; + + if (val32 == ori_tsf) { + PLTFM_MSG_ERR("B%dP%d tsf not running 0x%X\n", + band, port, val32); + return MACHWERR; + } + + PLTFM_DELAY_US(TU_UNIT); + cnt--; + } while (cnt); + + if (!cnt) + return MACPOLLTO; + + return MACSUCCESS; +} + +u32 dly_port_us(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_us) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 cnt; + u32 ori_tsf; + + cnt = dly_us * PORT_DLY_US_CNT_LMT; + ori_tsf = MAC_REG_R32(tsfl_regl[band][port]); + PLTFM_DELAY_US(10); + do { + val32 = MAC_REG_R32(tsfl_regl[band][port]); + if ((val32 >= ori_tsf && + (val32 - ori_tsf) >= dly_us) || + (val32 < ori_tsf && + (ori_tsf - val32 + 1) >= dly_us)) + break; + + if (val32 == ori_tsf) { + PLTFM_MSG_ERR("B%dP%d tsf not running 0x%X\n", + band, port, val32); + return MACHWERR; + } + + PLTFM_DELAY_US(10); + cnt--; + } while (cnt); + + if (!cnt) + return MACPOLLTO; + + return MACSUCCESS; +} + +u32 rst_port_info(struct mac_ax_adapter *adapter, u8 band) +{ + u8 p_idx; + + for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++) + PLTFM_MEMSET(&adapter->port_info[get_bp_idx(band, p_idx)], 0, + sizeof(struct mac_ax_port_info)); + + return MACSUCCESS; +} + +static u32 chk_bcnq_empty(struct mac_ax_adapter *adapter, u8 band, u8 port, + u32 bcn_spc, u8 *empty) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 bcnq_num_sh, bcnq_num_msk; + u32 cnt, emp_cont_cnt; + u32 ret; + + *empty = 1; + + val32 = MAC_REG_R32(ptcl_dbg_regl[band]); + val32 = SET_CLR_WORD(val32, PTCL_DBG_BCNQ_NUM0, B_AX_PTCL_DBG_SEL); + MAC_REG_W32(ptcl_dbg_regl[band], val32); + PLTFM_DELAY_US(PTCL_DBG_DLY_US); + + cnt = CHK_BCNQ_CNT; + emp_cont_cnt = 0; + do { + val32 = MAC_REG_R32(ptcl_dbg_info_regl[band]); + bcnq_num_sh = port * 2; + bcnq_num_msk = 3; + val32 = GET_FIEL2(val32, bcnq_num_sh, bcnq_num_msk); + + if (val32) + emp_cont_cnt = 0; + else + emp_cont_cnt++; + + if (emp_cont_cnt >= BCNQ_EMP_CONT_CNT) { + if (port == MAC_AX_PORT_0) + break; + return MACSUCCESS; + } + + ret = dly_port_tu(adapter, band, port, bcn_spc); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dly B%dP%d %d tu fail %d\n", + band, port, bcn_spc, val32); + return ret; + } + cnt--; + } while (cnt); + + if (!cnt) { + PLTFM_MSG_ERR("[ERR] chk bcnq empty0 %d timeout\n", val32); + *empty = 0; + return MACPOLLTO; + } + + val32 = MAC_REG_R32(ptcl_dbg_regl[band]); + val32 = SET_CLR_WORD(val32, PTCL_DBG_BCNQ_NUM1, B_AX_PTCL_DBG_SEL); + MAC_REG_W32(ptcl_dbg_regl[band], val32); + PLTFM_DELAY_US(PTCL_DBG_DLY_US); + + cnt = CHK_BCNQ_CNT; + emp_cont_cnt = 0; + do { + val32 = MAC_REG_R32(ptcl_dbg_info_regl[band]); + + if (val32) + emp_cont_cnt = 0; + else + emp_cont_cnt++; + + if (emp_cont_cnt >= BCNQ_EMP_CONT_CNT) + return MACSUCCESS; + + ret = dly_port_tu(adapter, band, port, bcn_spc); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] dly B%dP%d %d tu fail %d\n", + band, port, bcn_spc, val32); + return ret; + } + cnt--; + } while (cnt); + + PLTFM_MSG_ERR("[ERR] chk bcnq empty1 %d timeout\n", val32); + *empty = 0; + return MACPOLLTO; +} + +static u32 fast_bcn_drop(struct mac_ax_adapter *adapter, u8 band, u8 port) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + u32 ret = MACSUCCESS; + u32 port_drp_sel; + u32 mbid_drp_sel = 0; + u32 val32; + u32 bcn_spc; + u8 mbid_num; + u8 is_empty; + u32 i; + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + + port_drp_sel = (port == MAC_AX_PORT_0 ? B_AX_BCN_DROP_ALL_P0 : 0) | + (port == MAC_AX_PORT_1 ? B_AX_BCN_DROP_ALL_P1 : 0) | + (port == MAC_AX_PORT_2 ? B_AX_BCN_DROP_ALL_P2 : 0) | + (port == MAC_AX_PORT_3 ? B_AX_BCN_DROP_ALL_P3 : 0) | + (port == MAC_AX_PORT_4 ? B_AX_BCN_DROP_ALL_P4 : 0); + val32 = MAC_REG_R32(bcndrp_regl[band]) | port_drp_sel; + MAC_REG_W32(bcndrp_regl[band], val32); + + if (port == MAC_AX_PORT_0) { + mbid_drp_sel = B_AX_BCN_DROP_ALL_P0MB1 | + B_AX_BCN_DROP_ALL_P0MB2 | + B_AX_BCN_DROP_ALL_P0MB3; + if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + mbid_drp_sel |= B_AX_BCN_DROP_ALL_P0MB4 | + B_AX_BCN_DROP_ALL_P0MB5 | + B_AX_BCN_DROP_ALL_P0MB6 | + B_AX_BCN_DROP_ALL_P0MB7 | + B_AX_BCN_DROP_ALL_P0MB8 | + B_AX_BCN_DROP_ALL_P0MB9 | + B_AX_BCN_DROP_ALL_P0MB10 | + B_AX_BCN_DROP_ALL_P0MB11 | + B_AX_BCN_DROP_ALL_P0MB12 | + B_AX_BCN_DROP_ALL_P0MB13 | + B_AX_BCN_DROP_ALL_P0MB14 | + B_AX_BCN_DROP_ALL_P0MB15; + val32 = MAC_REG_R32(mbssid_drp_regl[band]) | mbid_drp_sel; + MAC_REG_W32(mbssid_drp_regl[band], val32); + } + + cfg_para.val = 1; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg func setup time fail %d\n", ret); + return ret; + } + + cfg_para.val = 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg func mask area fail %d\n", ret); + return ret; + } + + cfg_para.val = 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg func hold time fail %d\n", ret); + return ret; + } + + cfg_para.val = 2; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg func bcn early fail %d\n", ret); + return ret; + } + + cfg_para.val = 1; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg tbtt early fail %d\n", ret); + return ret; + } + + if (port == MAC_AX_PORT_0) { + ret = _get_max_mbid(adapter, &mbid_num); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret); + return MACPORTCFGPORT; + } + bcn_spc = (u32)(mbid_num + 1) * BCN_FAST_DRP_TBTT; + + val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]); + val32 = SET_CLR_WORD(val32, BCN_FAST_DRP_TBTT, + B_AX_SUB_BCN_SPACE_P0); + MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], val32); + val32 = SET_CLR_WORD(val32, bcn_spc, B_AX_BCN_SPACE_P0); + MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], val32); + + val32 = MAC_REG_R32(mbid_ctrl_regl[band]); + val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); + for (i = 0; i < mbid_num; i++) + val32 |= b_mbid_en_l[i]; + MAC_REG_W32(mbid_ctrl_regl[band], val32); + + } else { + bcn_spc = BCN_FAST_DRP_TBTT; + cfg_para.val = bcn_spc; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] port cfg func bcn intv fail %d\n", + ret); + return ret; + } + } + + ret = chk_bcnq_empty(adapter, band, port, bcn_spc, &is_empty); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] chk bcnq empty fail %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(bcndrp_regl[band]) & ~port_drp_sel; + MAC_REG_W32(bcndrp_regl[band], val32); + + if (port == MAC_AX_PORT_0) { + val32 = MAC_REG_R32(mbssid_drp_regl[band]) & ~mbid_drp_sel; + MAC_REG_W32(mbssid_drp_regl[band], val32); + } + + val32 = MAC_REG_R32(cfg_regl[band][port]) & ~b_phben_l[port]; + MAC_REG_W32(cfg_regl[band][port], val32); + + ret = dly_port_tu(adapter, band, port, bcn_spc + 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d dly %d tu fail %d\n", + band, port, bcn_spc + 1, ret); + return ret; + } + + return MACSUCCESS; +} + +u32 _patch_port_dis_flow(struct mac_ax_adapter *adapter, u8 band, u8 port, + struct mac_ax_port_info *pinfo) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + u32 bcn_set_bk = MAC_AX_R32_DEAD; + u32 bcn_spc; + u32 val32; + u32 ret = MACSUCCESS; + u16 val16; + u8 patch_flag, phb_bkp_flag; + u8 mbid_max; + + patch_flag = is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ? 1 : 0; + phb_bkp_flag = patch_flag && port != MAC_AX_PORT_0 ? 1 : 0; + + if (phb_bkp_flag) + bcn_set_bk = MAC_REG_R32(phb_regl[band][port]); + + if (pinfo->stat == PORT_ST_AP || pinfo->stat == PORT_ST_ADHOC) { + ret = fast_bcn_drop(adapter, band, port); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] fast bcn drop fail %d\n", + ret); + goto end; + } + } + + if (patch_flag) { + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + cfg_para.val = 0; + ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get port cfg bcn intv fail %d\n", + ret); + goto end; + } + bcn_spc = cfg_para.val; + + val32 = MAC_REG_R32(phb_regl[band][port]); + val32 = SET_CLR_WORD(val32, 0, B_AX_TBTT_SETUP_P0); + val32 = SET_CLR_WORD(val32, 1, B_AX_TBTT_HOLD_P0); + MAC_REG_W32(phb_regl[band][port], val32); + + val16 = MAC_REG_R16(tbttery_regl[band][port]); + val16 = SET_CLR_WORD(val16, 0, B_AX_TBTTERLY_P0); + MAC_REG_W16(tbttery_regl[band][port], val16); + + val16 = MAC_REG_R16(bcn_early_regl[band][port]); + val16 = SET_CLR_WORD(val16, 0, B_AX_BCNERLY_P0); + MAC_REG_W16(bcn_early_regl[band][port], val16); + + ret = dly_port_tu(adapter, band, port, bcn_spc + 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d dly %d tu fail %d\n", + band, port, bcn_spc, ret); + goto end; + } + } + + if (port == MAC_AX_PORT_0) { + ret = _get_max_mbid(adapter, &mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret); + return MACPORTCFGPORT; + } + + ret = port0_mbid_set(adapter, band, 0, mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d mbid set fail %d\n", + band, port, ret); + return ret; + } + } + + val32 = MAC_REG_R32(cfg_regl[band][port]) & + ~(b_en_l[port] | b_brken_l[port]); + MAC_REG_W32(cfg_regl[band][port], val32); + val32 |= b_rsttsf_l[port]; + MAC_REG_W32(cfg_regl[band][port], val32); + MAC_REG_W32(cnt_tmr_regl[band][port], 0); + + pinfo->stat = PORT_ST_DIS; +end: + if (phb_bkp_flag) { + if (bcn_set_bk != MAC_AX_R32_DEAD) { + MAC_REG_W32(phb_regl[band][port], bcn_set_bk); + } else { + PLTFM_MSG_ERR("[ERR]prev ret %d\n", ret); + PLTFM_MSG_ERR("[ERR]B%dP%d phb reg dead\n", band, port); + ret = MACCMP; + } + } + + return ret; +} + +u32 mac_port_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_port_cfg_type type, + struct mac_ax_port_cfg_para *para) +{ + struct mac_ax_port_info *pinfo; + u8 band = para->band; + u8 port = para->port; + +#if 0 // MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_port_cfg *hdr; + u32 ret = MACSUCCESS; + u32 cnt; + + if (para->band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d\n", para->band); + return MACFUNCINPUT; + } + + if (para->port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d\n", para->port); + return MACFUNCINPUT; + } + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + cnt = PORT_H2C_DLY_CNT; + while (pinfo->h2c_sm == MAC_AX_PORT_H2C_BUSY) { + cnt--; + if (!cnt) { + PLTFM_MSG_ERR("[ERR]B%dP%d port H2C busy\n", + band, port); + return MACPROCBUSY; + } + PLTFM_DELAY_US(PORT_H2C_DLY_US); + } + + if (pinfo->h2c_sm == MAC_AX_PORT_H2C_FAIL) { + PLTFM_MSG_ERR("[ERR]prev B%dP%d port H2C fail\n", + band, port); + return MACPROCERR; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_port_cfg *) + h2cb_put(h2cb, sizeof(struct fwcmd_port_cfg)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(type, FWCMD_H2C_PORT_CFG_TYPE) | + SET_WORD(para->mbssid_idx, + FWCMD_H2C_PORT_CFG_MBSSID_IDX) | + SET_WORD(port, FWCMD_H2C_PORT_CFG_PORT) | + (band ? FWCMD_H2C_PORT_CFG_BAND : 0)); + + hdr->dword1 = + cpu_to_le32(SET_WORD(para->val, FWCMD_H2C_PORT_CFG_VAL)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MPORT, + FWCMD_H2C_FUNC_PORT_CFG, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + pinfo->h2c_sm = MAC_AX_PORT_H2C_BUSY; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; + } +#endif + + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 mbssid_idx = para->mbssid_idx; + u32 set_val = para->val; + u8 val8, w_val8; + u16 val16; + u16 w_val16 = MAC_AX_R16_DEAD; + u32 val32; + u32 w_val32 = MAC_AX_R32_DEAD; + struct mac_ax_pkt_drop_info info; + u8 mbid_max; + u32 ret = MACSUCCESS; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + band != MAC_AX_BAND_0) { + PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band); + return MACFUNCINPUT; + } + + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port); + return MACPORTCFGPORT; + } + + if (mbssid_idx) { + ret = _get_max_mbid(adapter, &mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret); + return MACPORTCFGPORT; + } + + if (mbssid_idx > (u32)mbid_max) { + PLTFM_MSG_ERR("[ERR] invalid MBSSID number %d\n", + mbssid_idx); + return MACFUNCINPUT; + } + } + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + switch (type) { + case MAC_AX_PCFG_FUNC_SW: + if (set_val) { + PLTFM_MSG_ERR("[ERR] use port init to enable port\n"); + return MACFUNCINPUT; + } + + if (pinfo->stat == PORT_ST_DIS) { + PLTFM_MSG_WARN("[WARN]B%dP%d stat already disable\n", + band, port); + break; + } + + ret = _patch_port_dis_flow(adapter, band, port, pinfo); + break; + + case MAC_AX_PCFG_TX_SW: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_bcntxen_l[port] : + val32 & ~b_bcntxen_l[port]; + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_TX_RPT: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_txbcnrpt_l[port] : + val32 & ~b_txbcnrpt_l[port]; + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_RX_SW: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_rxupd_l[port] : + val32 & ~b_rxupd_l[port]; + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_RX_RPT: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_rxbcnrpt_l[port] : + val32 & ~b_rxbcnrpt_l[port]; + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_RX_SYNC: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_rxtsfupd_l[port] : + val32 & ~b_rxtsfupd_l[port]; + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_BCN_PRCT: + val32 = MAC_REG_R32(cfg_regl[band][port]); + w_val32 = set_val ? val32 | b_phben_l[port] | b_brken_l[port] : + val32 & ~(b_phben_l[port] | + b_brken_l[port]); + if (w_val32 != val32) + MAC_REG_W32(cfg_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_TBTT_AGG: + if (set_val > B_AX_TBTT_AGG_NUM_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal tbtt agg %d\n", set_val); + return MACFUNCINPUT; + } + + val16 = MAC_REG_R16(tbttagg_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTT_AGG_NUM_P0); + break; + case MAC_AX_PORT_1: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTT_AGG_NUM_P1); + break; + case MAC_AX_PORT_2: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTT_AGG_NUM_P2); + break; + case MAC_AX_PORT_3: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTT_AGG_NUM_P3); + break; + case MAC_AX_PORT_4: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTT_AGG_NUM_P4); + break; + } + if (w_val16 != val16 && w_val16 != MAC_AX_R16_DEAD) + MAC_REG_W16(tbttagg_regl[band][port], w_val16); + break; + + case MAC_AX_PCFG_TBTT_SHIFT: + if (set_val > B_AX_TBTT_SHIFT_OFST_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal tbtt shift %d\n", set_val); + return MACFUNCINPUT; + } + + val32 = MAC_REG_R32(tbttsht_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SHIFT_OFST_P0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SHIFT_OFST_P1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SHIFT_OFST_P2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SHIFT_OFST_P3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SHIFT_OFST_P4); + break; + } + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(tbttsht_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_RST_TSF: + val32 = MAC_REG_R32(cfg_regl[band][port]); + val32 = val32 | b_rsttsf_l[port]; + MAC_REG_W32(cfg_regl[band][port], val32); + break; + + case MAC_AX_PCFG_RST_TPR: + val32 = MAC_REG_R32(bcnpsr_regl[band][port]); + val32 |= b_rptvld_l[port]; + MAC_REG_W32(bcnpsr_regl[band][port], val32); + break; + + case MAC_AX_PCFG_HIQ_WIN: + if (set_val > B_AX_HGQWND_0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal hiq win %d\n", set_val); + return MACFUNCINPUT; + } + + if (port == MAC_AX_PORT_0) + MAC_REG_W8(hiq_win_mbid_regl[band][mbssid_idx], + (u8)set_val); + else + MAC_REG_W8(hiq_win_port_regl[band][port], + (u8)set_val); + break; + + case MAC_AX_PCFG_HIQ_DTIM: + if (set_val > B_AX_DTIM_NUM_P0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal dtim prd %d\n", set_val); + return MACFUNCINPUT; + } + + val8 = MAC_REG_R8(dtim_switch[band]); + w_val8 = val8 | B_AX_UPD_TIMIE | B_AX_UPD_HGQMD; + if (w_val8 != val8) + MAC_REG_W8(dtim_switch[band], w_val8); + + if (port == MAC_AX_PORT_0) + MAC_REG_W8(dtim_prd_mbid_regl[band][mbssid_idx], + (u8)set_val); + else + MAC_REG_W8(dtim_prd_port_regl[band][port], + (u8)set_val); + break; + + case MAC_AX_PCFG_HIQ_NOLIMIT: + val32 = MAC_REG_R32(hiq_nolmt_regl[band]); + if (port == MAC_AX_PORT_0 && mbssid_idx) + w_val32 = set_val ? + val32 | b_hiq_nolmt_mbid_l[mbssid_idx - 1] : + val32 & ~b_hiq_nolmt_mbid_l[mbssid_idx - 1]; + else + w_val32 = set_val ? + val32 | b_hiq_nolmt_port_l[port] : + val32 & ~b_hiq_nolmt_port_l[port]; + if (w_val32 != val32) + MAC_REG_W32(hiq_nolmt_regl[band], w_val32); + break; + + case MAC_AX_PCFG_BCN_SETUP_TIME: + ret = _bcn_setup_chk(adapter, band, port, ¶->val); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("[WARN]bcn setup chk %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(phb_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SETUP_P0); + break; + case MAC_AX_PORT_1: + case MAC_AX_PORT_2: + case MAC_AX_PORT_3: + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_SETUP_P1); + break; + } + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(phb_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_BCN_HOLD_TIME: + ret = _bcn_hold_chk(adapter, band, port, ¶->val); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("[WARN]bcn hold chk %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(phb_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_HOLD_P0); + break; + case MAC_AX_PORT_1: + case MAC_AX_PORT_2: + case MAC_AX_PORT_3: + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_TBTT_HOLD_P1); + break; + } + + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(phb_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_MBSSID_EN: + if (port != MAC_AX_PORT_0 || !mbssid_idx) { + PLTFM_MSG_ERR("[ERR] mbssid en invalid for P%d MB%d\n", + port, mbssid_idx); + return MACFUNCINPUT; + } + + val32 = MAC_REG_R32(mbid_ctrl_regl[band]); + if (mbssid_idx > GET_FIELD(val32, B_AX_P0MB_NUM)) { + PLTFM_MSG_ERR("[ERR] mbssid %d over %d\n", set_val, + GET_FIELD(val32, B_AX_P0MB_NUM)); + return MACFUNCINPUT; + } + + w_val32 = set_val ? val32 | b_mbid_en_l[mbssid_idx - 1] : + val32 & ~b_mbid_en_l[mbssid_idx - 1]; + + if (w_val32 != val32) + MAC_REG_W32(mbid_ctrl_regl[band], w_val32); + + info.band = band; + info.port = port; + info.mbssid = (u8)mbssid_idx; + info.sel = MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID; + ret = adapter->ops->pkt_drop(adapter, &info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] B%d P%d MB%d hiq drop %d\n", + band, port, mbssid_idx, ret); + return ret; + } + break; + + case MAC_AX_PCFG_BCN_ERLY: + ret = _bcn_erly_chk(adapter, band, port, ¶->val); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("[WARN]bcn erly chk %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(bcn_early_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P4); + break; + } + + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(bcn_early_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_BCN_MASK_AREA: + ret = _bcn_mask_chk(adapter, band, port, ¶->val); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("[WARN]bcn mask chk %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(mskarea_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_MSK_AREA_P0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_MSK_AREA_P1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_MSK_AREA_P2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_MSK_AREA_P3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_MSK_AREA_P4); + break; + } + + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(mskarea_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_TBTT_ERLY: + ret = _tbtt_erly_chk(adapter, band, port, ¶->val); + if (ret != MACSUCCESS) { + PLTFM_MSG_WARN("[WARN]tbtt erly chk %d\n", ret); + return ret; + } + + val16 = MAC_REG_R16(tbttery_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTTERLY_P0); + break; + case MAC_AX_PORT_1: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTTERLY_P1); + break; + case MAC_AX_PORT_2: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTTERLY_P2); + break; + case MAC_AX_PORT_3: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTTERLY_P3); + break; + case MAC_AX_PORT_4: + w_val16 = SET_CLR_WORD(val16, set_val, + B_AX_TBTTERLY_P4); + break; + } + + if (w_val16 != val16 && w_val16 != MAC_AX_R16_DEAD) + MAC_REG_W16(tbttery_regl[band][port], w_val16); + break; + + case MAC_AX_PCFG_BSS_CLR: + if (set_val > B_AX_BSS_COLOB_AX_PORT_0_MSK) { + PLTFM_MSG_ERR("[ERR] illegal bss color %d\n", set_val); + return MACFUNCINPUT; + } + + val32 = MAC_REG_R32(bss_color_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BSS_COLOB_AX_PORT_0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BSS_COLOB_AX_PORT_1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BSS_COLOB_AX_PORT_2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BSS_COLOB_AX_PORT_3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BSS_COLOB_AX_PORT_4); + break; + } + + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(bss_color_regl[band][port], w_val32); + break; + + case MAC_AX_PCFG_BCN_DRP_ALL: + if (port == MAC_AX_PORT_0 && mbssid_idx) { + val32 = MAC_REG_R32(mbssid_drp_regl[band]); + w_val32 = set_val ? + val32 | b_mbid_drp_l[mbssid_idx - 1] : + val32 & ~b_mbid_drp_l[mbssid_idx - 1]; + if (w_val32 != val32) + MAC_REG_W32(mbssid_drp_regl[band], w_val32); + } else { + val32 = MAC_REG_R32(bcndrp_regl[band]); + w_val32 = set_val ? val32 | b_drpall_l[port] : + val32 & ~b_drpall_l[port]; + if (w_val32 != val32) + MAC_REG_W32(bcndrp_regl[band], w_val32); + } + break; + + case MAC_AX_PCFG_MBSSID_NUM: + if (port != MAC_AX_PORT_0 || pinfo->stat != PORT_ST_AP) { + PLTFM_MSG_ERR("[ERR]port is not 0 or is not AP\n"); + return MACPORTCFGPORT; + } + _set_max_mbid_num(adapter, para); + break; + + case MAC_AX_PCFG_BCN_INTV: + if (set_val > B_AX_BCN_SPACE_P0_MSK || !set_val) { + PLTFM_MSG_ERR("[ERR] illegal bcn itvl %d\n", set_val); + return MACFUNCINPUT; + } + + val32 = MAC_REG_R32(bcnspc_regl[band][port]); + switch (port) { + case MAC_AX_PORT_0: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_SPACE_P0); + break; + case MAC_AX_PORT_1: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_SPACE_P1); + break; + case MAC_AX_PORT_2: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_SPACE_P2); + break; + case MAC_AX_PORT_3: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_SPACE_P3); + break; + case MAC_AX_PORT_4: + w_val32 = SET_CLR_WORD(val32, set_val, + B_AX_BCN_SPACE_P4); + break; + } + if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD) + MAC_REG_W32(bcnspc_regl[band][port], w_val32); + break; + + default: + PLTFM_MSG_ERR("[ERR] invalid cfg type %d\n", type); + return MACPORTCFGTYPE; + } + + return ret; +} + +u32 mac_port_init(struct mac_ax_adapter *adapter, + struct mac_ax_port_init_para *para) +{ + struct mac_ax_port_info *pinfo; + u8 band = para->band_idx; + u8 port = para->port_idx; + u8 net_type = para->net_type; + +#if 0 // MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_port_init *hdr; + u32 ret = MACSUCCESS; + u32 cnt; + + if (band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d\n", band); + return MACFUNCINPUT; + } + + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d\n", port); + return MACFUNCINPUT; + } + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + if (pinfo->h2c_sm == MAC_AX_PORT_H2C_FAIL) { + PLTFM_MSG_ERR("[ERR]prev B%dP%d port H2C fail\n", + band, port); + return MACPROCERR; + } + + cnt = PORT_H2C_DLY_CNT; + while (pinfo->h2c_sm == MAC_AX_PORT_H2C_BUSY) { + cnt--; + if (!cnt) { + PLTFM_MSG_ERR("[ERR]B%dP%d port H2C busy\n", + band, port); + return MACPROCBUSY; + } + PLTFM_DELAY_US(PORT_H2C_DLY_US); + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_port_init *) + h2cb_put(h2cb, sizeof(struct fwcmd_port_init)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(para->bss_color, + FWCMD_H2C_PORT_INIT_BSS_COLOR) | + SET_WORD(para->mbid_num, + FWCMD_H2C_PORT_INIT_MBSSID_NUM) | + SET_WORD(para->dtim_period, + FWCMD_H2C_PORT_INIT_DTIM_PRD) | + SET_WORD(net_type, + FWCMD_H2C_PORT_INIT_NET_TYPE) | + SET_WORD(port, FWCMD_H2C_PORT_INIT_PORT) | + (band ? FWCMD_H2C_PORT_INIT_BAND : 0)); + + hdr->dword1 = + cpu_to_le32(SET_WORD(para->hiq_win, + FWCMD_H2C_PORT_INIT_HIQ_WND) | + SET_WORD(para->bcn_interval, + FWCMD_H2C_PORT_INIT_BCN_ITVL)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MPORT, + FWCMD_H2C_FUNC_PORT_INIT, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + pinfo->h2c_sm = MAC_AX_PORT_H2C_BUSY; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; + } +#endif + + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_port_cfg_para cfg_para; + struct mac_ax_pkt_drop_info info; + u8 mbid_num; + u8 mbid_max; + u8 i = 0; + u32 ret = MACSUCCESS; + u32 val32; + u32 bcn_erly = BCN_ERLY_DEF; + u32 hold_time = BCN_HOLD_DEF; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + band != MAC_AX_BAND_0) { + PLTFM_MSG_ERR("[ERR]invalid band idx %d\n", band); + return MACFUNCINPUT; + } + + if (port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port idx %d\n", port); + return MACPORTCFGPORT; + } + + mbid_num = net_type == MAC_AX_NET_TYPE_AP && port == MAC_AX_BAND_0 ? + para->mbid_num : 0; + + ret = _get_max_mbid(adapter, &mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get_max_mbid %d\n", ret); + return MACPORTCFGPORT; + } + + if (mbid_num > mbid_max) { + PLTFM_MSG_ERR("[ERR]invalid MBSSID number %d\n", mbid_num); + return MACFUNCINPUT; + } + if (mbid_num && !(mbid_num % 2)) + mbid_num++; + + pinfo = &adapter->port_info[get_bp_idx(band, port)]; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]chk mac en %d\n", ret); + return ret; + } + + cfg_para.band = band; + cfg_para.port = port; + cfg_para.mbssid_idx = 0; + + if (pinfo->stat != PORT_ST_DIS) { + cfg_para.val = 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_FUNC_SW, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg func sw 0 fail %d\n", + band, port, ret); + return ret; + } + } + + cfg_para.val = 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TX_RPT, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg tx rpt fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_RPT, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx rpt fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = net_type; + ret = _port_cfg(adapter, MAC_AX_PCFG_NET_TYPE, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg net type fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = net_type == MAC_AX_NET_TYPE_NO_LINK ? 0 : 1; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_PRCT, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn prct fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = (net_type == MAC_AX_NET_TYPE_INFRA || + net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_SW, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx sw fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = (net_type == MAC_AX_NET_TYPE_INFRA || + net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_SYNC, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx sync fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = (net_type == MAC_AX_NET_TYPE_AP || + net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TX_SW, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg tx sw fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = (u32)para->bcn_interval; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn intv fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = (u32)para->bss_color; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BSS_CLR, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg bss_color fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = TBTT_AGG_DEF; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_AGG, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg tbtt agg fail %d\n", + band, port, ret); + return ret; + } + + for (i = 0; i <= mbid_num; i++) { + cfg_para.mbssid_idx = mbid_idx_l[i]; + cfg_para.val = para->hiq_win; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_HIQ_WIN, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d cfg hiq win %d\n", + band, port, cfg_para.mbssid_idx, ret); + return ret; + } + cfg_para.val = (u32)para->dtim_period; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_HIQ_DTIM, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d cfg hiq dtim %d\n", + band, port, cfg_para.mbssid_idx, ret); + return ret; + } + + info.band = band; + info.port = port; + info.mbssid = (u8)mbid_idx_l[i]; + info.sel = info.mbssid ? + MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID : + MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT; + ret = adapter->ops->pkt_drop(adapter, &info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d hiq drop %d\n", + band, port, info.mbssid, ret); + return ret; + } + } + + cfg_para.val = hold_time; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para); + if (ret == MACSETVALERR) + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, + &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg hold time fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = BCN_MASK_DEF; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, &cfg_para); + if (ret == MACSETVALERR) + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, + &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg mask area fail %d\n", + band, port, ret); + return ret; + } + + val32 = MAC_REG_R32(cfg_regl[band][port]) | b_en_l[port]; + MAC_REG_W32(cfg_regl[band][port], val32); + + switch (net_type) { + case MAC_AX_NET_TYPE_NO_LINK: + pinfo->stat = PORT_ST_NOLINK; + break; + case MAC_AX_NET_TYPE_ADHOC: + pinfo->stat = PORT_ST_ADHOC; + break; + case MAC_AX_NET_TYPE_INFRA: + pinfo->stat = PORT_ST_INFRA; + break; + case MAC_AX_NET_TYPE_AP: + pinfo->stat = PORT_ST_AP; + break; + } + + ret = dly_port_us(adapter, band, port, BCN_ERLY_SET_DLY); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d dly %d us fail %d\n", + band, port, BCN_ERLY_SET_DLY, ret); + return ret; + } + + cfg_para.val = bcn_erly; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret == MACSETVALERR) + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn early fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = BCN_SETUP_DEF; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para); + if (ret == MACSETVALERR) + ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, + &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg setup time fail %d\n", + band, port, ret); + return ret; + } + + cfg_para.val = TBTT_ERLY_DEF; + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para); + if (ret == MACSETVALERR) + ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d cfg tbtt early fail %d\n", + band, port, ret); + return ret; + } + + if (port == MAC_AX_PORT_0) { + ret = port0_mbid_set(adapter, band, mbid_num, mbid_max); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d mbid set fail %d\n", + band, port, ret); + return ret; + } + + ret = port0_subspc_set(adapter, band, mbid_num, + &bcn_erly, &hold_time); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]B%dP%d subspc set fail %d\n", + band, port, ret); + return ret; + } + } + + return ret; +} + +u32 mac_tsf_sync(struct mac_ax_adapter *adapter, u8 from_port, u8 to_port, + s32 sync_offset, enum mac_ax_tsf_sync_act action) +{ + u32 abs_sync_offset, val32, ret = MACSUCCESS; + u16 to_port_reg; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (from_port > MAX_TSF_SOURCE_PORT || to_port > MAX_TSF_TARGET_PORT || + from_port == to_port) { + PLTFM_MSG_ERR("[ERR] Invalid tsf_sync port.\n"); + return MACFUNCINPUT; + } + + abs_sync_offset = sync_offset > 0 ? sync_offset : -sync_offset; + + if (abs_sync_offset > MAX_TSF_SYNC_OFFSET) { + PLTFM_MSG_ERR("[ERR] Invalid tsf_sync offset.\n"); + return MACFUNCINPUT; + } + + if (sync_offset < 0) + abs_sync_offset |= BIT18; + + switch (to_port) { + case MAC_AX_PORT_0: + to_port_reg = R_AX_PORT_0_TSF_SYNC; + break; + case MAC_AX_PORT_1: + to_port_reg = R_AX_PORT_1_TSF_SYNC; + break; + case MAC_AX_PORT_2: + to_port_reg = R_AX_PORT_2_TSF_SYNC; + break; + case MAC_AX_PORT_3: + to_port_reg = R_AX_PORT_3_TSF_SYNC; + break; + case MAC_AX_PORT_4: + to_port_reg = R_AX_PORT_4_TSF_SYNC; + break; + default: + PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n"); + return MACFUNCINPUT; + } + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD(to_port_reg, + B_AX_P0_TSFTR_SYNC_OFFSET_MSK << + B_AX_P0_TSFTR_SYNC_OFFSET_SH, + abs_sync_offset, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, to_port_reg, ret); + return ret; + } + ret = MAC_REG_W_OFLD(to_port_reg, + B_AX_P0_SYNC_PORT_SRC_SEL_MSK << + B_AX_P0_SYNC_PORT_SRC_SEL_SH, + from_port, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, to_port_reg, ret); + return ret; + } + + switch (action) { + case MAC_AX_TSF_SYNC_NOW_ONCE: + ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_SYNC_NOW_P, + 1, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, to_port_reg, ret); + return ret; + } + ret = MAC_REG_P_OFLD(to_port_reg, B_AX_P0_SYNC_NOW_P, + 0, 1); + break; + case MAC_AX_TSF_EN_SYNC_AUTO: + ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_AUTO_SYNC, + 1, 1); + break; + case MAC_AX_TSF_DIS_SYNC_AUTO: + ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_AUTO_SYNC, + 0, 1); + break; + default: + PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n"); + return MACFUNCINPUT; + } + + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, to_port_reg, ret); + return ret; + } + + return ret; + } +#endif + val32 = MAC_REG_R32(to_port_reg); + val32 = SET_CLR_WORD(val32, abs_sync_offset, B_AX_P0_TSFTR_SYNC_OFFSET); + val32 = SET_CLR_WORD(val32, from_port, B_AX_P0_SYNC_PORT_SRC_SEL); + MAC_REG_W32(to_port_reg, val32); + + switch (action) { + case MAC_AX_TSF_SYNC_NOW_ONCE: + MAC_REG_W32(to_port_reg, val32 | B_AX_P0_SYNC_NOW_P); + break; + case MAC_AX_TSF_EN_SYNC_AUTO: + MAC_REG_W32(to_port_reg, val32 | B_AX_P0_AUTO_SYNC); + break; + case MAC_AX_TSF_DIS_SYNC_AUTO: + MAC_REG_W32(to_port_reg, val32 & ~B_AX_P0_AUTO_SYNC); + break; + default: + PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n"); + return MACFUNCINPUT; + } + + return ret; +} + +u32 mac_parse_bcn_stats_c2h(struct mac_ax_adapter *adapter, + u8 *content, struct mac_ax_bcn_cnt *val) + +{ + u32 *pdata, data0, data1; + u8 port_mbssid; + + pdata = (u32 *)content; + data0 = le32_to_cpu(*pdata); + data1 = le32_to_cpu(*(pdata + 1)); + + port_mbssid = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX); + if (port_mbssid < MAC_AX_P0_MBID_LAST) { + val->port = 0; + val->mbssid = port_mbssid; + } else { + val->port = port_mbssid - MAC_AX_P0_MBID_LAST + 1; + val->mbssid = 0; + } + val->band = data0 & FWCMD_C2H_BCN_CNT_BAND_IDX ? 1 : 0; + + val->cca_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT); + val->edcca_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT); + val->nav_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT); + val->txon_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT); + val->mac_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT); + val->others_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT); + val->lock_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT); + val->cmp_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT); + val->invalid_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT); + val->srchend_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT); + val->ok_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_OK_CNT); + + return MACSUCCESS; +} + +u32 mac_tsf32_togl_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_info *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_tsf32_togl *hdr; + u32 ret = MACSUCCESS; + + if (info->band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("[ERR]invalid band %d\n", info->band); + return MACFUNCINPUT; + } + + if (info->port >= MAC_AX_PORT_NUM) { + PLTFM_MSG_ERR("[ERR]invalid port %d\n", info->port); + return MACFUNCINPUT; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_tsf32_togl *) + h2cb_put(h2cb, sizeof(struct fwcmd_tsf32_togl)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->port, FWCMD_H2C_TSF32_TOGL_PORT) | + SET_WORD(info->early, FWCMD_H2C_TSF32_TOGL_EARLY) | + (info->band ? FWCMD_H2C_TSF32_TOGL_BAND : 0) | + (info->en ? FWCMD_H2C_TSF32_TOGL_EN : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_TSF32_TOGL, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_get_t32_togl_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_rpt *ret_rpt) +{ + struct mac_ax_t32_togl_rpt *rpt; + u8 b_idx, p_idx; + + for (b_idx = MAC_AX_BAND_0; b_idx < MAC_AX_BAND_NUM; b_idx++) { + for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++) { + rpt = &adapter->t32_togl_rpt[get_bp_idx(b_idx, p_idx)]; + if (!rpt->valid) + continue; + PLTFM_MEMCPY(ret_rpt, rpt, + sizeof(struct mac_ax_t32_togl_rpt)); + rpt->valid = 0; + return MACSUCCESS; + } + } + + PLTFM_MSG_WARN("[WARN]no tsf32 togl rpt find\n"); + return MACNOITEM; +} + +u32 mport_info_init(struct mac_ax_adapter *adapter) +{ + u8 b_idx, p_idx; + u32 idx; + + adapter->t32_togl_rpt = + (struct mac_ax_t32_togl_rpt *)PLTFM_MALLOC(t32_togl_rpt_size); + adapter->port_info = + (struct mac_ax_port_info *)PLTFM_MALLOC(port_info_size); + for (b_idx = MAC_AX_BAND_0; b_idx < MAC_AX_BAND_NUM; b_idx++) { + for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++) { + idx = get_bp_idx(b_idx, p_idx); + PLTFM_MEMSET(&adapter->t32_togl_rpt[idx], 0, + sizeof(struct mac_ax_t32_togl_rpt)); + PLTFM_MEMSET(&adapter->port_info[idx], 0, + sizeof(struct mac_ax_port_info)); + } + } + + return MACSUCCESS; +} + +u32 mport_info_exit(struct mac_ax_adapter *adapter) +{ + PLTFM_FREE(adapter->t32_togl_rpt, t32_togl_rpt_size); + PLTFM_FREE(adapter->port_info, port_info_size); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/mport.h b/phl/hal_g6/mac/mac_ax/mport.h new file mode 100644 index 0000000..01b8d5b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/mport.h @@ -0,0 +1,271 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_MPORT_H_ +#define _MAC_AX_MPORT_H_ + +#include "../type.h" + +/*--------------------Define -------------------------------------------*/ +#define BCN_ERLY_DEF 160 +#define BCN_SETUP_DEF 4 +#define BCN_HOLD_DEF 400 +#define BCN_MASK_DEF 0 +#define TBTT_ERLY_DEF 5 +#define TBTT_AGG_DEF 1 +#define BCN_SET_TO_US 32 +#define TU_TO_BCN_SET (1024 / BCN_SET_TO_US) +#define BCN_ERLY_SET_DLY 10 + +#define PTCL_DBG_BCNQ_NUM0 8 +#define PTCL_DBG_BCNQ_NUM1 9 +#define PTCL_DBG_DLY_US 100 + +#define TU_UNIT 1024 +#define MS_UNIT 1000 +#define PORT_DLY_TU_CNT_LMT 2 +#define PORT_DLY_US_CNT_LMT 2 + +#define MAX_BCN_ITVL 0x639C + +#define CHK_BCNQ_CNT 200 +#define BCNQ_EMP_CONT_CNT 2 + +#define LBK_PLCP_DLY_DEF 0x28 +#define LBK_PLCP_DLY_FPGA 0x46 + +#define BCN_FAST_DRP_TBTT 1 + +/* 50% hold time , 30% beacon early */ +#define BCN_ERLY_RATIO 3 +#define BCN_HOLD_RATIO 5 +#define BCN_ITVL_RATIO 10 + +#define PORT_H2C_DLY_US 10 +#define PORT_H2C_DLY_CNT 20000 + +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +enum port_stat { + PORT_ST_DIS = 0, + PORT_ST_NOLINK, + PORT_ST_ADHOC, + PORT_ST_INFRA, + PORT_ST_AP, +}; + +enum C2H_MPORT_RET_CODE { + C2H_MPORT_RET_SUCCESS = 0, + C2H_MPORT_RET_PENDING, + C2H_MPORT_RET_BAND_ERR, + C2H_MPORT_RET_PORT_ERR, + C2H_MPORT_RET_MBID_ERR, + C2H_MPORT_RET_NO_CONTENT, + C2H_MPORT_RET_TSF32TOG_C2H_FAIL, + C2H_MPORT_RET_CFG_TYPE_ERR, + C2H_MPORT_RET_SET_CFG_ILEGAL_EN, + C2H_MPORT_RET_SET_CFG_ARDY_DIS, + C2H_MPORT_RET_INPUT_ILEGAL, + C2H_MPORT_RET_CHK_BELW_LMT, + C2H_MPORT_RET_CHK_OVER_LMT, + C2H_MPORT_RET_SUB_SPC_ERR, + C2H_MPORT_RET_POLL_TO, + C2H_MPORT_RET_TSF_NOT_RUN, + C2H_MPORT_RET_MALLOC_FAIL, + C2H_MPORT_RET_DEINIT_FAIL, + C2H_MPORT_RET_PKT_DROP, + C2H_MPORT_RET_ADD_PSTIMER, + C2H_MPORT_RET_CHK_BCNQ_TO, + C2H_MPORT_RET_CHK_BCNQ_FAIL, + C2H_MPORT_RET_SEND_C2H_INIT, + C2H_MPORT_RET_SEND_C2H_CFG, +}; + +/*--------------------Define Struct-------------------------------------*/ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ +/** + * @brief dly_port_tu + * + * @param *adapter + * @param band + * @param port + * @param dly_tu + * @return Please Place Description here. + * @retval u32 + */ +u32 dly_port_tu(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_tu); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief dly_port_us + * + * @param *adapter + * @param band + * @param port + * @param dly_us + * @return Please Place Description here. + * @retval u32 + */ +u32 dly_port_us(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_us); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief rst_port_info + * + * @param *adapter + * @param band + * @return Please Place Description here. + * @retval u32 + */ +u32 rst_port_info(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief mac_port_cfg + * + * @param *adapter + * @param type + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_port_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_port_cfg_type type, + struct mac_ax_port_cfg_para *para); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief mac_port_init + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_port_init(struct mac_ax_adapter *adapter, + struct mac_ax_port_init_para *para); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief mac_tsf_sync + * + * @param *adapter + * @param from_port + * @param to_port + * @param sync_offset + * @param action + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_tsf_sync(struct mac_ax_adapter *adapter, u8 from_port, u8 to_port, + s32 sync_offset, enum mac_ax_tsf_sync_act action); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup MultiPort + * @{ + */ + +/** + * @brief mac_parse_bcn_stats_c2h + * + * @param *adapter + * @param *content + * @param *val + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_parse_bcn_stats_c2h(struct mac_ax_adapter *adapter, + u8 *content, struct mac_ax_bcn_cnt *val); +/** + * @} + * @} + */ + +u32 mac_tsf32_togl_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_info *info); + +u32 mac_get_t32_togl_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_rpt *ret_rpt); + +u32 get_bp_idx(u8 band, u8 port); + +u32 mport_info_init(struct mac_ax_adapter *adapter); + +u32 mport_info_exit(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/p2p.c b/phl/hal_g6/mac/mac_ax/p2p.c new file mode 100644 index 0000000..9ac1378 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/p2p.c @@ -0,0 +1,367 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "p2p.h" + +static u32 p2p_info_size = sizeof(struct mac_ax_p2p_info) * P2P_MAX_NUM; + +static u32 _get_valid_p2pid(struct mac_ax_adapter *adapter, u8 macid, u8 *p2pid) +{ + struct mac_ax_p2p_info *info = adapter->p2p_info; + u8 idx; + + for (idx = 0; idx < P2P_MAX_NUM; idx++) { + if (info[idx].run && info[idx].macid == macid) { + PLTFM_MSG_ERR("[ERR]macid %d has running p2pid %d\n", + macid, idx); + *p2pid = P2PID_INVALID; + return MACSUCCESS; + } + } + + for (idx = 0; idx < P2P_MAX_NUM; idx++) { + if (!info[idx].run && !info[idx].wait_dack) { + *p2pid = idx; + return MACSUCCESS; + } + } + + PLTFM_MSG_ERR("[ERR]no valid p2p\n"); + *p2pid = P2PID_INVALID; + return MACHWNOSUP; +} + +static u32 _get_macid_p2pid(struct mac_ax_adapter *adapter, u8 macid, u8 *p2pid) +{ + struct mac_ax_p2p_info *info = adapter->p2p_info; + u8 idx; + + for (idx = 0; idx < P2P_MAX_NUM; idx++) { + if (info[idx].run && info[idx].macid == macid) { + *p2pid = idx; + return MACSUCCESS; + } + } + + PLTFM_MSG_ERR("[ERR]no valid p2pid for macid %d\n", macid); + *p2pid = P2PID_INVALID; + return MACFUNCINPUT; +} + +u32 get_wait_dack_p2pid(struct mac_ax_adapter *adapter, u8 *p2pid) +{ + struct mac_ax_p2p_info *info = adapter->p2p_info; + u8 idx; + u8 hit = 0; + + for (idx = 0; idx < P2P_MAX_NUM; idx++) { + if (info[idx].wait_dack && !hit) { + *p2pid = idx; + hit = 1; + } else if (info[idx].wait_dack) { + PLTFM_MSG_ERR("[ERR]multiple wait dack p2p\n"); + return MACPROCERR; + } + } + + if (!hit) + *p2pid = P2PID_INVALID; + + return MACSUCCESS; +} + +u32 p2p_info_init(struct mac_ax_adapter *adapter) +{ + u32 i; + + adapter->p2p_info = + (struct mac_ax_p2p_info *)PLTFM_MALLOC(p2p_info_size); + for (i = 0; i < P2P_MAX_NUM; i++) + PLTFM_MEMSET(&adapter->p2p_info[i], 0, + sizeof(struct mac_ax_p2p_info)); + + return MACSUCCESS; +} + +u32 p2p_info_exit(struct mac_ax_adapter *adapter) +{ + PLTFM_FREE(adapter->p2p_info, p2p_info_size); + + return MACSUCCESS; +} + +u32 rst_p2p_info(struct mac_ax_adapter *adapter) +{ + PLTFM_MEMSET(adapter->p2p_info, 0, p2p_info_size); + + return MACSUCCESS; +} + +u32 mac_p2p_act_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_act_info *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_p2p_act *hdr; + u32 ret = MACSUCCESS; + u8 p2pid; + + if (info->noaid >= NOA_MAX_NUM) { + PLTFM_MSG_ERR("[ERR]invalid noaid %d\n", info->noaid); + return MACFUNCINPUT; + } + + if (info->act == P2P_ACT_INIT) { + ret = _get_valid_p2pid(adapter, info->macid, &p2pid); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get valid p2pid %d\n", ret); + return MACHWNOSUP; + } + if (p2pid == P2PID_INVALID) { + PLTFM_MSG_ERR("[ERR]get invalid p2pid\n"); + return MACNOITEM; + } + } else { + ret = _get_macid_p2pid(adapter, info->macid, &p2pid); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get macid %d p2pid %d\n", + info->macid, ret); + return MACFUNCINPUT; + } + if (p2pid == P2PID_INVALID) { + PLTFM_MSG_ERR("[ERR]get macid p2pid shall ret err\n"); + return MACCMP; + } + } + + if (adapter->sm.p2p_stat == MAC_AX_P2P_ACT_BUSY) { + PLTFM_MSG_ERR("[ERR] p2p act h2c stat busy\n"); + return MACPROCERR; + } + adapter->sm.p2p_stat = MAC_AX_P2P_ACT_BUSY; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_p2p_act *) + h2cb_put(h2cb, sizeof(struct fwcmd_p2p_act)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_P2P_ACT_MACID) | + SET_WORD(p2pid, FWCMD_H2C_P2P_ACT_P2PID) | + SET_WORD(info->noaid, FWCMD_H2C_P2P_ACT_NOAID) | + SET_WORD(info->act, FWCMD_H2C_P2P_ACT_ACT) | + (info->type ? FWCMD_H2C_P2P_ACT_TYPE : 0) | + (info->all_slep ? FWCMD_H2C_P2P_ACT_ALL_SLEP : 0)); + + hdr->dword1 = + cpu_to_le32(SET_WORD(info->srt, FWCMD_H2C_P2P_ACT_SRT)); + + hdr->dword2 = + cpu_to_le32(SET_WORD(info->itvl, FWCMD_H2C_P2P_ACT_ITVL)); + + hdr->dword3 = + cpu_to_le32(SET_WORD(info->dur, FWCMD_H2C_P2P_ACT_DUR)); + + hdr->dword4 = + cpu_to_le32(SET_WORD(info->cnt, FWCMD_H2C_P2P_ACT_CNT) | + SET_WORD(info->ctw, FWCMD_H2C_P2P_ACT_CTW)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_PS, + FWCMD_H2C_FUNC_P2P_ACT, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + if (info->act == P2P_ACT_INIT) + adapter->p2p_info[p2pid].macid = info->macid; + if (info->act == P2P_ACT_INIT || info->act == P2P_ACT_TERM) + adapter->p2p_info[p2pid].wait_dack = 1; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_p2p_macid_ctrl_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_macid_info *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_p2p_macid_ctrl *hdr; + u32 ret = MACSUCCESS; + u32 idx, bmap_ext_size, pldsize, bmap_srt_sh, bmap_last; + u32 bmap_idx_srt, bmap_idx_end, bmap_idx_diff; + u8 *curr_buf; + u8 p2pid; + + if (info->ctrl_type >= P2P_MACID_CTRL_MAX) { + PLTFM_MSG_ERR("[ERR]p2p macid ctrl invalid ctrl type %d\n", + info->ctrl_type); + return MACFUNCINPUT; + } + + ret = _get_macid_p2pid(adapter, info->main_macid, &p2pid); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]get macid %d p2pid %d\n", + info->main_macid, ret); + return MACFUNCINPUT; + } + if (p2pid == P2PID_INVALID) { + PLTFM_MSG_ERR("[ERR]get macid p2pid shall ret err\n"); + return MACNOITEM; + } + + bmap_idx_srt = 0; + for (idx = 0; idx < info->bmap_len; idx++) { + if (*(info->bitmap + idx)) + break; + if (idx && !(idx & MACID_BMAP_BYTE_MSK)) + bmap_idx_srt++; + } + + bmap_idx_end = info->bmap_len >> MACID_BMAP_BYTE_SH; + bmap_last = info->bmap_len ? (info->bmap_len - 1) : 0; + for (idx = bmap_last; idx > 0; idx--) { + if (*(info->bitmap + idx)) + break; + if (!(idx & MACID_BMAP_BYTE_MSK)) + bmap_idx_end--; + } + + if (bmap_idx_srt > bmap_idx_end) { + PLTFM_MSG_ERR("[ERR] p2p macid ctrl bitmap comp err\n"); + return MACCMP; + } + + bmap_idx_diff = bmap_idx_end - bmap_idx_srt; + bmap_ext_size = bmap_idx_diff << MACID_BMAP_BYTE_SH; + + if (adapter->sm.p2p_stat == MAC_AX_P2P_ACT_BUSY) { + PLTFM_MSG_ERR("[ERR] p2p macid ctrl h2c stat busy\n"); + return MACPROCERR; + } + adapter->sm.p2p_stat = MAC_AX_P2P_ACT_BUSY; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + pldsize = sizeof(struct fwcmd_p2p_macid_ctrl) + bmap_ext_size; + hdr = (struct fwcmd_p2p_macid_ctrl *)h2cb_put(h2cb, pldsize); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(p2pid, FWCMD_H2C_P2P_MACID_CTRL_P2PID) | + SET_WORD(info->ctrl_type, + FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE) | + SET_WORD((bmap_idx_srt << MACID_BMAP_BIT_SH), + FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT) | + SET_WORD((bmap_idx_diff + 1), + FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN)); + + for (idx = 0; idx <= ((bmap_idx_diff + 1) << MACID_BMAP_BYTE_SH); idx++) { + bmap_srt_sh = (bmap_idx_srt << MACID_BMAP_BYTE_SH) + idx; + curr_buf = (u8 *)(&hdr->dword1) + idx; + if (bmap_srt_sh < info->bmap_len) + *curr_buf = *(info->bitmap + bmap_srt_sh); + else + *curr_buf = 0; + } + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_PS, + FWCMD_H2C_FUNC_P2P_MACID_CTRL, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + adapter->p2p_info[p2pid].wait_dack = 1; + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_get_p2p_stat(struct mac_ax_adapter *adapter) +{ + switch (adapter->sm.p2p_stat) { + case MAC_AX_P2P_ACT_IDLE: + return MACSUCCESS; + case MAC_AX_P2P_ACT_BUSY: + return MACPROCBUSY; + case MAC_AX_P2P_ACT_FAIL: + default: + return MACP2PSTFAIL; + } +} + diff --git a/phl/hal_g6/mac/mac_ax/p2p.h b/phl/hal_g6/mac/mac_ax/p2p.h new file mode 100644 index 0000000..7a4fae5 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/p2p.h @@ -0,0 +1,118 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_P2P_H_ +#define _MAC_AX_P2P_H_ + +#include "../type.h" +#include "fwcmd.h" + +/*--------------------Define -------------------------------------------*/ +#define P2P_MAX_NUM 2 +#define NOA_MAX_NUM 2 +#define P2PID_INVALID 0xFF + +#define MACID_BMAP_BYTE_SH 2 /* DWORD to Byte */ +#define MACID_BMAP_BYTE_MSK 0x3 +#define MACID_BMAP_BIT_SH 5 /* DWORD to bit */ + +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +enum P2P_ACT { + P2P_ACT_INIT = 0, + P2P_ACT_UPD, + P2P_ACT_RM, + P2P_ACT_TERM +}; + +enum P2P_MACID_CTRL_TYPE { + P2P_MACID_CTRL_JOIN = 0, + P2P_MACID_CTRL_CLR, + P2P_MACID_CTRL_CLR_ALL, + P2P_MACID_CTRL_MAX +}; + +/*--------------------Define Struct-------------------------------------*/ + +/** + * @brief get_wait_dack_p2pid + * + * @param *adapter + * @param *p2pid + * @return Please Place Description here. + * @retval u32 + */ +u32 get_wait_dack_p2pid(struct mac_ax_adapter *adapter, u8 *p2pid); + +/** + * @brief p2p_info_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 p2p_info_init(struct mac_ax_adapter *adapter); + +/** + * @brief p2p_info_exit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 p2p_info_exit(struct mac_ax_adapter *adapter); + +/** + * @brief rst_p2p_info + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 rst_p2p_info(struct mac_ax_adapter *adapter); + +/** + * @brief mac_p2p_act_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_p2p_act_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_act_info *info); + +/** + * @brief mac_p2p_macid_ctrl_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_p2p_macid_ctrl_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_macid_info *info); + +/** + * @brief mac_get_p2p_stat + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_p2p_stat(struct mac_ax_adapter *adapter); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/phy_misc.c b/phl/hal_g6/mac/mac_ax/phy_misc.c new file mode 100644 index 0000000..aa40db1 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/phy_misc.c @@ -0,0 +1,116 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "phy_misc.h" + +u32 mac_fast_ch_sw(struct mac_ax_adapter *adapter, struct mac_ax_fast_ch_sw_param *fast_ch_sw_param) +{ + u8 *buf; + u32 ret = MACSUCCESS; + struct fwcmd_fcs *pkt; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cbuf; + #else + struct h2c_buf *h2cbuf; + #endif + + h2cbuf = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cbuf) + return MACNPTR; + + buf = h2cb_put(h2cbuf, sizeof(struct fwcmd_fcs)); + if (!buf) { + PLTFM_MSG_ERR("[HM][H2C][FCS] ret = %d\n", MACNOBUF); + return MACNOBUF; + } + pkt = (struct fwcmd_fcs *)buf; + pkt->dword0 = cpu_to_le32(SET_WORD(fast_ch_sw_param->ap_port_id, + FWCMD_H2C_FCS_AP_PORT_ID) | + SET_WORD(fast_ch_sw_param->ch_idx, + FWCMD_H2C_FCS_CH_IDX) | + SET_WORD(fast_ch_sw_param->thermal_idx, + FWCMD_H2C_FCS_THERMAL_IDX) | + SET_WORD(fast_ch_sw_param->pause_rel_mode, + FWCMD_H2C_FCS_PAUSE_REL_MODE) | + SET_WORD(fast_ch_sw_param->con_sta_num, + FWCMD_H2C_FCS_CON_STA_NUM) | + (fast_ch_sw_param->band ? FWCMD_H2C_FCS_BAND : 0) | + SET_WORD(fast_ch_sw_param->bandwidth, + FWCMD_H2C_FCS_BANDWIDTH)); + pkt->dword1 = cpu_to_le32(SET_WORD(fast_ch_sw_param->pri_ch, + FWCMD_H2C_FCS_PRI_CH) | + SET_WORD(fast_ch_sw_param->central_ch, + FWCMD_H2C_FCS_CENTRAL_CH)); + pkt->dword2 = cpu_to_le32(fast_ch_sw_param->rel_pause_tsfl); + pkt->dword3 = cpu_to_le32(fast_ch_sw_param->rel_pause_tsfh); + pkt->dword4 = cpu_to_le32(fast_ch_sw_param->rel_pause_delay_time); + pkt->dword5 = cpu_to_le32(SET_WORD(fast_ch_sw_param->csa_pkt_id[0], + FWCMD_H2C_FCS_CSA_PKT_ID0) | + SET_WORD(fast_ch_sw_param->csa_pkt_id[1], + FWCMD_H2C_FCS_CSA_PKT_ID1) | + SET_WORD(fast_ch_sw_param->csa_pkt_id[2], + FWCMD_H2C_FCS_CSA_PKT_ID2) | + SET_WORD(fast_ch_sw_param->csa_pkt_id[3], + FWCMD_H2C_FCS_CSA_PKT_ID3)); + ret = h2c_pkt_set_hdr(adapter, h2cbuf, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FCS, FWCMD_H2C_FUNC_FCS, 1, 1); + if (ret) { + PLTFM_MSG_ERR("[HM][H2C][FCS] error when set hdr\n"); + return ret; + } + + ret = h2c_pkt_build_txd(adapter, h2cbuf); + + if (ret) { + PLTFM_MSG_ERR("[HM][H2C][FCS] error when build txd\n"); + return ret; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cbuf); + #else + ret = PLTFM_TX(h2cbuf->data, h2cbuf->len); + #endif + + h2cb_free(adapter, h2cbuf); + + if (ret) { + PLTFM_MSG_ERR("[HM][H2C][FCS] error when h2cb free\n"); + return ret; + } + h2c_end_flow(adapter); + adapter->fast_ch_sw_info.busy = 1; + if (ret) { + PLTFM_MSG_ERR("[HM][H2C][FCS] error when h2c_end_flow\n"); + return ret; + } + PLTFM_MSG_TRACE("[HM][H2C][FCS] ret = %d\n", ret); + return ret; +} + +u32 mac_fast_ch_sw_done(struct mac_ax_adapter *adapter) +{ + if (adapter->fast_ch_sw_info.busy) + return MACPROCBUSY; + else + return MACSUCCESS; +} + +u32 mac_get_fast_ch_sw_rpt(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code) +{ + *fast_ch_sw_status_code = adapter->fast_ch_sw_info.status; + return MACSUCCESS; +} \ No newline at end of file diff --git a/phl/hal_g6/mac/mac_ax/phy_misc.h b/phl/hal_g6/mac/mac_ax/phy_misc.h new file mode 100644 index 0000000..b4ecc3f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/phy_misc.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PHY_MISC_H_ +#define _MAC_AX_PHY_MISC_H_ + +#include "../type.h" +#include "fwcmd.h" + +u32 mac_fast_ch_sw(struct mac_ax_adapter *adapter, + struct mac_ax_fast_ch_sw_param *fast_ch_sw_param); +u32 mac_fast_ch_sw_done(struct mac_ax_adapter *adapter); +u32 mac_get_fast_ch_sw_rpt(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code); +#endif // __MAC_AX_PHY_MISC_H_ \ No newline at end of file diff --git a/phl/hal_g6/mac/mac_ax/phy_rpt.c b/phl/hal_g6/mac/mac_ax/phy_rpt.c new file mode 100644 index 0000000..8418db4 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/phy_rpt.c @@ -0,0 +1,529 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "phy_rpt.h" + +#define MAC_AX_RX_CNT_SIZE 96 +#define MAC_AX_DISP_QID_HOST 0x2 +#define MAC_AX_DISP_QID_WLCPU 0xB +#define MAC_AX_DFS_HDR_SIZE 8 +#define MAC_AX_DFS_RPT_SIZE 8 +#define MAC_AX_DFS_RPT_SIZE_SH 3 +#define MAC_AX_CH_INFO_BUF 0 +#define B_AX_CH_INFO_BUF_128 0 +#define B_AX_GET_CH_INFO_TO_DIS 0 +#define B_AX_GET_CH_INFO_TO_8 2 +#define B_AX_CH_INFO_INTVL_DIS 0 +#define B_AX_CH_INFO_INTVL_1 1 +#define B_AX_CH_INFO_INTVL_2 2 +#define B_AX_CH_INFO_INTVL_4 4 +#define B_AX_CH_INFO_INTVL_7 7 +#define B_AX_CH_INFO_REQ_2 1 +#define B_AX_DFS_BUF_64 1 + +#define MAC_AX_MAC_INFO_USE_SIZE 4 +struct mac_ax_mac_info_t { + u32 dword0; + u32 dword1; +}; + +struct mac_ax_dfs_hdr_t { + u32 dword0; + u32 dword1; +}; + +static u32 is_cfg_avl(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg, + struct mac_ax_ppdu_stat *ppdu) +{ + if (cfg->dest == MAC_AX_PRPT_DEST_HOST && ppdu->dup2fw_en && + ppdu->dup2fw_len != 0) { + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) + return MACFUNCINPUT; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) + return MACFUNCINPUT; + } + } + + return MACSUCCESS; +} + +static u32 cfg_ppdu_status(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_ppdu_stat *ppdu = &cfg->u.ppdu; + u32 reg = (ppdu->band) ? R_AX_PPDU_STAT_C1 : R_AX_PPDU_STAT; + u32 val; + u32 ret = 0; + + ret = check_mac_en(adapter, ppdu->band, MAC_AX_CMAC_SEL); + if (ret) { + PLTFM_MSG_ERR("MAC%d is not ready\n", ppdu->band); + goto END; + } + + ret = is_cfg_avl(adapter, cfg, ppdu); + if (ret) { + PLTFM_MSG_ERR("The PPDU status config is INVALID\n"); + goto END; + } + + if (!cfg->en) { +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)reg, + B_AX_PPDU_STAT_RPT_EN, + 0, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + goto END; + } +#endif + val = MAC_REG_R32(reg); + val = val & ~B_AX_PPDU_STAT_RPT_EN; + MAC_REG_W32(reg, val); + goto END; + } + + val = MAC_REG_R32(R_AX_HW_RPT_FWD); + switch (cfg->dest) { + case MAC_AX_PRPT_DEST_HOST: + if (ppdu->dup2fw_en) { + MAC_REG_W32(R_AX_RX_PPDU_STATUS_FW_MODE, + B_AX_HDR_PPDU_ENQ_WLCPU_EN | + SET_WORD(ppdu->dup2fw_len, + B_AX_CDR_PPDU_2_WLCPU_LEN)); + } + + val = SET_CLR_WORD(val, MAC_AX_FWD_TO_HOST, B_AX_FWD_PPDU_STAT); + break; + case MAC_AX_PRPT_DEST_WLCPU: + val = SET_CLR_WORD(val, MAC_AX_FWD_TO_WLAN_CPU, + B_AX_FWD_PPDU_STAT); + break; + default: + PLTFM_MSG_ERR("Wrong PPDU status destination\n"); + ret = MACFUNCINPUT; + } + MAC_REG_W32(R_AX_HW_RPT_FWD, val); + + ppdu->bmp_append_info = ppdu->bmp_append_info & + (MAC_AX_PPDU_MAC_INFO | + MAC_AX_PPDU_PLCP | + MAC_AX_PPDU_RX_CNT); + ppdu->bmp_filter = ppdu->bmp_filter & + (MAC_AX_PPDU_HAS_A1M | + MAC_AX_PPDU_HAS_CRC_OK); + + val = B_AX_PPDU_STAT_RPT_EN | + ppdu->bmp_filter | + ppdu->bmp_append_info; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W32_OFLD((u16)reg, val, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + goto END; + } +#endif + + MAC_REG_W32(reg, val); + +END: + return ret; +} + +static u32 en_bbrpt(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val; + + val = MAC_REG_R32(R_AX_DMAC_CLK_EN); + if (!(val & B_AX_BBRPT_CLK_EN)) { + val = val | B_AX_BBRPT_CLK_EN; + MAC_REG_W32(R_AX_DMAC_CLK_EN, val); + } + + val = MAC_REG_R32(R_AX_DMAC_FUNC_EN); + if (!(val & B_AX_BBRPT_EN)) { + val = val | B_AX_BBRPT_EN; + MAC_REG_W32(R_AX_DMAC_FUNC_EN, val); + } + + return MACSUCCESS; +} + +static u32 stop_ch_info(struct mac_ax_adapter *adapter, u32 ch_info_reg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val; + u32 count = 3000; +#if MAC_AX_FW_REG_OFLD + u32 ret; +#endif + + val = MAC_REG_R8(R_AX_CH_INFO); + MAC_REG_W8(R_AX_CH_INFO, val | B_AX_CH_INFO_STOP_REQ); + while (!(MAC_REG_R8(R_AX_CH_INFO) & B_AX_CH_INFO_STOP)) { + count--; + if (count == 0) { + PLTFM_MSG_ERR("Polling ch info idle timeout\n"); + return MACPOLLTO; + } + } + + val = MAC_REG_R8(R_AX_CH_INFO); + MAC_REG_W8(R_AX_CH_INFO, val | B_AX_CH_INFO_EN); + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)ch_info_reg, B_AX_GET_CH_INFO_EN, 0, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } +#endif + + val = MAC_REG_R8(ch_info_reg); + MAC_REG_W8(ch_info_reg, val & ~B_AX_GET_CH_INFO_EN); + + return MACSUCCESS; +} + +static u32 cfg_ch_info(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg; + u32 val; + u32 ret = 0; + struct mac_role_tbl *role; + struct mac_ax_ch_info *chif = &cfg->u.chif; + u8 band; + u8 intvl; + + role = mac_role_srch(adapter, chif->macid); + if (!role) { + PLTFM_MSG_ERR("[ERR]cannot find macid: %d\n", chif->macid); + ret = MACNOITEM; + goto END; + } + band = role->info.band; + + en_bbrpt(adapter); + + reg = (band == MAC_AX_BAND_0) ? + R_AX_CH_INFO_QRY : R_AX_CH_INFO_QRY_C1; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret) { + PLTFM_MSG_ERR("MAC%d is not ready\n", band); + goto END; + } + + if (!cfg->en) { + ret = stop_ch_info(adapter, reg); + goto END; + } + + switch (chif->seg_size) { + case MAC_AX_CH_IFNO_SEG_128: + intvl = B_AX_CH_INFO_INTVL_1; + break; + case MAC_AX_CH_IFNO_SEG_256: + intvl = B_AX_CH_INFO_INTVL_2; + break; + case MAC_AX_CH_IFNO_SEG_512: + intvl = B_AX_CH_INFO_INTVL_4; + break; + case MAC_AX_CH_IFNO_SEG_1024: + intvl = B_AX_CH_INFO_INTVL_7; + break; + default: + PLTFM_MSG_ERR("Wrong ch info segment\n"); + ret = MACFUNCINPUT; + goto END; + } + + MAC_REG_W8(R_AX_BB_COEX_CFG, B_AX_BBRPT_COEX_EN); + + MAC_REG_W32(R_AX_CH_INFO, + SET_WORD(cfg->dest == MAC_AX_PRPT_DEST_WLCPU ? + MAC_AX_DISP_QID_WLCPU : MAC_AX_DISP_QID_HOST, + B_AX_CH_INFO_QID) | + SET_WORD(B_AX_CH_INFO_REQ_2, B_AX_CH_INFO_REQ) | + SET_WORD(chif->seg_size, B_AX_CH_INFO_SEG) | + SET_WORD(intvl, B_AX_CH_INFO_INTVL) | + (chif->dis_to ? + 0 : SET_WORD(B_AX_GET_CH_INFO_TO_8, B_AX_GET_CH_INFO_TO)) | + (band ? B_AX_CH_INFO_PHY : 0) | + SET_WORD(B_AX_CH_INFO_BUF_128, B_AX_CH_INFO_BUF) | + B_AX_CH_INFO_EN); + + switch (chif->trigger) { + case MAC_AX_CH_INFO_MACID: + case MAC_AX_CH_INFO_ACK: + val = B_AX_GET_CH_INFO_EN | + SET_WORD(MAC_AX_CH_INFO_MACID, B_AX_CH_INFO_MODE) | + SET_WORD(chif->macid, B_AX_CH_INFO_MACID) | + ((chif->bmp_filter << 16) & (B_AX_CH_INFO_CRC_FAIL | + B_AX_CH_INFO_DATA_FRM | + B_AX_CH_INFO_CTRL_FRM | + B_AX_CH_INFO_MGNT_FRM)); + break; + case MAC_AX_CH_INFO_NDP: + val = B_AX_GET_CH_INFO_EN | + SET_WORD(chif->trigger, B_AX_CH_INFO_MODE) | + SET_WORD(chif->macid, B_AX_CH_INFO_MACID); + break; + case MAC_AX_CH_INFO_SND: + val = B_AX_GET_CH_INFO_EN | + SET_WORD(chif->trigger, B_AX_CH_INFO_MODE) | + SET_WORD(chif->macid, B_AX_CH_INFO_MACID) | + ((chif->bmp_filter << 16) & (B_AX_CH_INFO_CRC_FAIL | + B_AX_CH_INFO_DATA_FRM | + B_AX_CH_INFO_CTRL_FRM | + B_AX_CH_INFO_MGNT_FRM)); + + break; + default: + PLTFM_MSG_ERR("Wrong channel info mode\n"); + ret = MACFUNCINPUT; + goto END; + } +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W32_OFLD((u16)reg, val, 1); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s: write offload fail %d", + __func__, ret); + return ret; + } +#endif + + MAC_REG_W32(reg, val); +END: + return ret; +} + +static u32 stop_dfs(struct mac_ax_adapter *adapter) +{ +#define MAC_AX_PHY_RPT_CNT 3000 + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val; + u32 count = MAC_AX_PHY_RPT_CNT; + + val = MAC_REG_R8(R_AX_DFS_CFG0); + MAC_REG_W8(R_AX_DFS_CFG0, val | B_AX_STOP_DFS); + while (!(MAC_REG_R8(R_AX_DFS_CFG0) & B_AX_DFS_IN_STOP)) { + count--; + if (count == 0) { + PLTFM_MSG_ERR("Polling ch info idle timeout\n"); + return MACPOLLTO; + } + } + + MAC_REG_W8(R_AX_DFS_CFG0, val & ~B_AX_DFS_RPT_EN); + + return MACSUCCESS; +} + +static u32 cfg_dfs(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_dfs *dfs = &cfg->u.dfs; + u32 ret = 0, val; + + en_bbrpt(adapter); + + if (!cfg->en) { + ret = stop_dfs(adapter); + goto END; + } + + switch (dfs->num_th) { + case MAC_AX_DFS_TH_29: + case MAC_AX_DFS_TH_61: + case MAC_AX_DFS_TH_93: + case MAC_AX_DFS_TH_125: + val = B_AX_DFS_RPT_EN | + SET_WORD(B_AX_DFS_BUF_64, B_AX_DFS_BUF) | + SET_WORD(dfs->num_th, B_AX_DFS_NUM_TH) | + SET_WORD(dfs->en_timeout ? 1 : 0, B_AX_DFS_TIME_TH) | + SET_WORD(cfg->dest == MAC_AX_PRPT_DEST_WLCPU ? + MAC_AX_DISP_QID_WLCPU : MAC_AX_DISP_QID_HOST, + B_AX_DFS_QID); + break; + default: + PLTFM_MSG_ERR("Wrong DFS report num threshold\n"); + ret = MACFUNCINPUT; + goto END; + } + + MAC_REG_W32(R_AX_DFS_CFG0, val); +END: + return ret; +} + +u32 mac_cfg_phy_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *rpt) +{ + u32 (*handle)(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *rpt); + + switch (rpt->type) { + case MAC_AX_PPDU_STATUS: + handle = cfg_ppdu_status; + break; + case MAC_AX_CH_INFO: + handle = cfg_ch_info; + break; + case MAC_AX_DFS: + handle = cfg_dfs; + break; + default: + PLTFM_MSG_ERR("Wrong PHY report type\n"); + return MACFUNCINPUT; + } + + return handle(adapter, rpt); +} + +static u32 parse_mac_info(struct mac_ax_adapter *adapter, + u8 *buf, u32 len, + struct mac_ax_ppdu_rpt *rpt) +{ + struct mac_ax_ppdu_usr *usr; + struct mac_ax_mac_info_t *macinfo; + u8 i; + u32 ret = MACSUCCESS; + u32 accu_size = sizeof(struct mac_ax_mac_info_t); + u32 val; + u8 *ptr; + + macinfo = (struct mac_ax_mac_info_t *)buf; + + /* dword0 */ + val = le32_to_cpu(macinfo->dword0); + rpt->usr_num = (u8)GET_FIELD(val, AX_MAC_INFO_USR_NUM); + if (rpt->usr_num > MAC_AX_PPDU_MAX_USR) { + PLTFM_MSG_ERR("The user num in mac info is invalid\n"); + ret = MACPARSEERR; + goto END; + } + rpt->fw_def = (u8)GET_FIELD(val, AX_MAC_INFO_FW_DEFINE); + rpt->lsig_len = (u16)GET_FIELD(val, AX_MAC_INFO_LSIG_LEN); + rpt->is_to_self = !!(val & AX_MAC_INFO_IS_TO_SELF); + rpt->rx_cnt_size = val & AX_MAC_INFO_RX_CNT_VLD ? + MAC_AX_RX_CNT_SIZE : 0; + + /* dowrd1 */ + val = le32_to_cpu(macinfo->dword1); + rpt->service = (u16)GET_FIELD(val, AX_MAC_INFO_SERVICE); + rpt->plcp_size = (u8)GET_FIELD(val, AX_MAC_INFO_PLCP_LEN) * 8; + + /* dword2 */ + usr = rpt->usr; + ptr = (u8 *)(macinfo + 1); + for (i = 0; i < rpt->usr_num; i++, usr++) { + val = le32_to_cpu(*((u32 *)ptr)); + usr->vld = !!(val & AX_MAC_INFO_MAC_ID_VALID); + usr->has_data = !!(val & AX_MAC_INFO_HAS_DATA); + usr->has_ctrl = !!(val & AX_MAC_INFO_HAS_CTRL); + usr->has_mgnt = !!(val & AX_MAC_INFO_HAS_MGNT); + usr->has_bcn = !!(val & AX_MAC_INFO_HAS_BCN); + usr->macid = (u8)GET_FIELD(val, AX_MAC_INFO_MACID); + accu_size += MAC_AX_MAC_INFO_USE_SIZE; + ptr += MAC_AX_MAC_INFO_USE_SIZE; + } + + /* 8-byte alignment */ + accu_size += rpt->usr_num & BIT(0) ? MAC_AX_MAC_INFO_USE_SIZE : 0; + ptr += rpt->usr_num & BIT(0) ? MAC_AX_MAC_INFO_USE_SIZE : 0; + if (rpt->rx_cnt_size) { + rpt->rx_cnt_ptr = ptr; + accu_size += rpt->rx_cnt_size; + ptr += rpt->rx_cnt_size; + } + + if (rpt->plcp_size) { + rpt->plcp_ptr = ptr; + accu_size += rpt->plcp_size; + ptr += rpt->plcp_size; + } + + if (len > accu_size) { + rpt->phy_st_ptr = ptr; + rpt->phy_st_size = len - accu_size; + } +END: + return ret; +} + +u32 mac_parse_ppdu(struct mac_ax_adapter *adapter, + u8 *buf, u32 ppdu_len, u8 mac_info, + struct mac_ax_ppdu_rpt *rpt) +{ + u32 ret = MACSUCCESS; + + PLTFM_MEMSET(rpt, 0, sizeof(struct mac_ax_ppdu_rpt)); + + if (mac_info) { + ret = parse_mac_info(adapter, buf, ppdu_len, rpt); + } else { + rpt->phy_st_ptr = buf; + rpt->phy_st_size = ppdu_len; + } + + return ret; +} + +u32 mac_parse_dfs(struct mac_ax_adapter *adapter, + u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt) +{ + struct mac_ax_dfs_hdr_t *dfs; + u32 len; + u32 msk = BIT(MAC_AX_DFS_RPT_SIZE_SH) - 1; + u32 ret = 0; + u32 val; + + dfs = (struct mac_ax_dfs_hdr_t *)buf; + + /* dword0 */ + val = le32_to_cpu(dfs->dword0); + rpt->drop_num = (u16)GET_FIELD(val, AX_DFS_DROP_NUM); + rpt->max_cont_drop = (u16)GET_FIELD(val, AX_DFS_MAX_CONT_DROP); + + /* dword1 */ + val = le32_to_cpu(dfs->dword1); + rpt->total_drop = (u16)GET_FIELD(val, AX_DFS_TOTAL_DROP); + len = dfs_len - MAC_AX_DFS_HDR_SIZE; + rpt->dfs_num = (u16)(len >> MAC_AX_DFS_RPT_SIZE_SH); + if (len & msk) { + PLTFM_MSG_ERR("The DFS report size is wrong\n"); + ret = MACPARSEERR; + } + rpt->dfs_ptr = buf + MAC_AX_DFS_HDR_SIZE; + + return ret; +} + diff --git a/phl/hal_g6/mac/mac_ax/phy_rpt.h b/phl/hal_g6/mac/mac_ax/phy_rpt.h new file mode 100644 index 0000000..e0ffebe --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/phy_rpt.h @@ -0,0 +1,98 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PHY_RPT_H_ +#define _MAC_AX_PHY_RPT_H_ + +#include "../type.h" +#include "role.h" +#include "trxcfg.h" + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_cfg_phy_rpt + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_phy_rpt(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_parse_ppdu + * + * @param *adapter + * @param *buf + * @param ppdu_len + * @param mac_info + * @param *rpt + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_parse_ppdu(struct mac_ax_adapter *adapter, + u8 *buf, u32 ppdu_len, u8 mac_info, + struct mac_ax_ppdu_rpt *rpt); +/** + * @} + * @} + */ + +/** + * @addtogroup Common + * @{ + * @addtogroup BB_Related + * @{ + */ + +/** + * @brief mac_parse_dfs + * + * @param *adapter + * @param *buf + * @param dfs_len + * @param *rpt + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_parse_dfs(struct mac_ax_adapter *adapter, + u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/power_saving.c b/phl/hal_g6/mac/mac_ax/power_saving.c new file mode 100644 index 0000000..77aa6af --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/power_saving.c @@ -0,0 +1,793 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "power_saving.h" +#include "coex.h" + +#define RPWM_SEQ_NUM_MAX 3 +#define CPWM_SEQ_NUM_MAX 3 + +//RPWM bit definition +#define PS_RPWM_TOGGLE BIT(15) +#define PS_RPWM_ACK BIT(14) +#define PS_RPWM_SEQ_NUM_SH 12 +#define PS_RPWM_SEQ_NUM_MSK 0x3 +#define PS_RPWM_NOTIFY_WAKE BIT(8) +#define PS_RPWM_STATE_SH 0 +#define PS_RPWM_STATE_MSK 0x7 + +//CPWM bit definition +#define PS_CPWM_TOGGLE BIT(15) +#define PS_CPWM_ACK BIT(14) +#define PS_CPWM_SEQ_NUM_SH 12 +#define PS_CPWM_SEQ_NUM_MSK 0x3 +#define PS_CPWM_RSP_SEQ_NUM_SH 8 +#define PS_CPWM_RSP_SEQ_NUM_MSK 0x3 +#define PS_CPWM_STATE_SH 0 +#define PS_CPWM_STATE_MSK 0x7 + +//(workaround) CPWM register is in OFF area +//LPS debug message bit definition +#define B_PS_LDM_32K_EN BIT(31) +#define B_PS_LDM_32K_EN_SH 31 + +static u32 lps_status[4] = {0}; +static u32 ips_status[4] = {0}; +static u8 rpwm_seq_num = RPWM_SEQ_NUM_MAX; +static u8 cpwm_seq_num = CPWM_SEQ_NUM_MAX; + +static u32 send_h2c_lps_parm(struct mac_ax_adapter *adapter, + struct lps_parm *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_lps_parm *fwcmd_lps; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_lps_parm)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_lps = (struct fwcmd_lps_parm *)buf; + fwcmd_lps->dword0 = + cpu_to_le32(SET_WORD(parm->macid, FWCMD_H2C_LPS_PARM_MACID) | + SET_WORD(parm->psmode, FWCMD_H2C_LPS_PARM_PSMODE) | + SET_WORD(parm->rlbm, FWCMD_H2C_LPS_PARM_RLBM) | + SET_WORD(parm->smartps, FWCMD_H2C_LPS_PARM_SMARTPS) | + SET_WORD(parm->awakeinterval, + FWCMD_H2C_LPS_PARM_AWAKEINTERVAL)); + + fwcmd_lps->dword1 = + cpu_to_le32((parm->vouapsd ? FWCMD_H2C_LPS_PARM_VOUAPSD : 0) | + (parm->viuapsd ? FWCMD_H2C_LPS_PARM_VIUAPSD : 0) | + (parm->beuapsd ? FWCMD_H2C_LPS_PARM_BEUAPSD : 0) | + (parm->bkuapsd ? FWCMD_H2C_LPS_PARM_BKUAPSD : 0) | + SET_WORD(parm->lastrpwm, FWCMD_H2C_LPS_PARM_LASTRPWM)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_PS, + FWCMD_H2C_FUNC_LPS_PARM, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static void send_rpwm(struct mac_ax_adapter *adapter, + struct ps_rpwm_parm *parm) +{ + u16 rpwm_value = 0; + u8 toggle = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (rpwm_seq_num == RPWM_SEQ_NUM_MAX) + rpwm_seq_num = 0; + else + rpwm_seq_num += 1; + + rpwm_value = MAC_REG_R16(R_AX_RPWM); + if (0 == (rpwm_value & PS_RPWM_TOGGLE)) + toggle = 1; + + if (parm->notify_wake) { + rpwm_value = (PS_RPWM_NOTIFY_WAKE | + SET_CLR_WORD(rpwm_value, rpwm_seq_num, PS_RPWM_SEQ_NUM)); + } else { + rpwm_value = (SET_WORD(parm->req_pwr_state, PS_RPWM_STATE) | + SET_WORD(rpwm_seq_num, PS_RPWM_SEQ_NUM)); + + if (parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF) + rpwm_value |= PS_RPWM_ACK; + + if (parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED) { + adapter->mac_pwr_info.pwr_in_lps = 1; + } + } + + if (toggle == 1) + rpwm_value |= PS_RPWM_TOGGLE; + else + rpwm_value &= ~PS_RPWM_TOGGLE; + + switch (adapter->hw_info->intf) { +#if MAC_AX_USB_SUPPORT + case MAC_AX_INTF_USB: +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + MAC_REG_W16(R_AX_USB_D2F_F2D_INFO + 2, rpwm_value); +#endif + +#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W16(R_AX_USB_D2F_F2D_INFO_V1 + 2, rpwm_value); +#endif + break; +#endif //MAC_AX_USB_SUPPORT + +#if MAC_AX_SDIO_SUPPORT + case MAC_AX_INTF_SDIO: +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + MAC_REG_W16(R_AX_SDIO_HRPWM1 + 2, rpwm_value); +#endif + +#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W16(R_AX_SDIO_HRPWM1_V1 + 2, rpwm_value); +#endif + + if (parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED || + parm->req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED) + adapter->sdio_info.tx_seq = 1; + break; +#endif //MAC_AX_SDIO_SUPPORT + +#if MAC_AX_PCIE_SUPPORT + case MAC_AX_INTF_PCIE: +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + MAC_REG_W16(R_AX_PCIE_HRPWM, rpwm_value); +#endif + +#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + MAC_REG_W16(R_AX_PCIE_HRPWM_V1, rpwm_value); +#endif + + break; +#endif //MAC_AX_PCIE_SUPPORT + default: + PLTFM_MSG_ERR("%s: invalid interface = %d!!\n", + __func__, adapter->hw_info->intf); + + break; + } + + PLTFM_MSG_TRACE("Send RPWM. rpwm_val=0x%x\n", rpwm_value); +} + +static u32 leave_lps(struct mac_ax_adapter *adapter, u8 macid) +{ + struct lps_parm h2c_lps_parm; + u32 ret; + + PLTFM_MEMSET(&h2c_lps_parm, 0, sizeof(struct lps_parm)); + + h2c_lps_parm.macid = macid; + h2c_lps_parm.psmode = MAC_AX_PS_MODE_ACTIVE; + h2c_lps_parm.lastrpwm = LAST_RPWM_ACTIVE; + + ret = send_h2c_lps_parm(adapter, &h2c_lps_parm); + + if (ret) + return ret; + + lps_status[(macid >> 5)] &= ~BIT(macid & 0x1F); + + return MACSUCCESS; +} + +static u32 enter_lps(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_lps_info *lps_info) +{ + struct lps_parm h2c_lps_parm; + u32 ret = 0; + + if (!lps_info) { + PLTFM_MSG_ERR("[ERR]:LPS info is null\n"); + return MACNOITEM; + } + + if (lps_status[(macid >> 5)] & BIT(macid & 0x1F)) + ret = leave_lps(adapter, macid); + + if (ret) + return ret; + + PLTFM_MEMSET(&h2c_lps_parm, 0, sizeof(struct lps_parm)); + + h2c_lps_parm.macid = macid; + h2c_lps_parm.psmode = MAC_AX_PS_MODE_LEGACY; + + if (lps_info->listen_bcn_mode > MAC_AX_RLBM_USERDEFINE) + lps_info->listen_bcn_mode = MAC_AX_RLBM_MIN; + + if (lps_info->listen_bcn_mode == MAC_AX_RLBM_USERDEFINE) { + h2c_lps_parm.rlbm = MAC_AX_RLBM_USERDEFINE; + h2c_lps_parm.awakeinterval = lps_info->awake_interval; + if (h2c_lps_parm.awakeinterval == 0) + h2c_lps_parm.awakeinterval = 1; + } else if (lps_info->listen_bcn_mode == MAC_AX_RLBM_MAX) { + h2c_lps_parm.rlbm = MAC_AX_RLBM_MAX; + h2c_lps_parm.awakeinterval = 1; + } else { + h2c_lps_parm.rlbm = MAC_AX_RLBM_MIN; + h2c_lps_parm.awakeinterval = 1; + } + + h2c_lps_parm.smartps = lps_info->smart_ps_mode; + h2c_lps_parm.lastrpwm = LAST_RPWM_PS; + + ret = send_h2c_lps_parm(adapter, &h2c_lps_parm); + + if (ret) + return ret; + + lps_status[(macid >> 5)] |= BIT(macid & 0x1F); + + return MACSUCCESS; +} + +static u32 set_req_pwr_state(struct mac_ax_adapter *adapter, + enum mac_ax_rpwm_req_pwr_state req_pwr_state) +{ + struct ps_rpwm_parm parm; + + PLTFM_MEMSET(&parm, 0, sizeof(struct ps_rpwm_parm)); + + if (req_pwr_state >= MAC_AX_RPWM_REQ_PWR_STATE_MAX) { + PLTFM_MSG_ERR("%s: invalid pwr state:%d\n", + __func__, req_pwr_state); + return MACNOITEM; + } + + parm.req_pwr_state = req_pwr_state; + parm.notify_wake = 0; + send_rpwm(adapter, &parm); + + return MACSUCCESS; +} + +static u32 _chk_cpwm_seq_num(u8 seq_num) +{ + u32 ret; + + if (cpwm_seq_num == CPWM_SEQ_NUM_MAX) { + if (seq_num == 0) { + cpwm_seq_num = seq_num; + ret = MACSUCCESS; + } else { + ret = MACCPWMSEQERR; + } + } else { + if (seq_num == (cpwm_seq_num + 1)) { + cpwm_seq_num = seq_num; + ret = MACSUCCESS; + } else { + ret = MACCPWMSEQERR; + } + } + + return ret; +} + +static u32 chk_cur_pwr_state(struct mac_ax_adapter *adapter, + enum mac_ax_rpwm_req_pwr_state req_pwr_state) +{ + u16 cpwm = 0; + u32 rpwm_32k; + u32 req_32k; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (req_pwr_state >= MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED) + req_32k = 1; + else + req_32k = 0; + + //(workaround) CPWM register is in OFF area + //Use LDM to check if FW receives RPWM + rpwm_32k = (MAC_REG_R32(R_AX_LDM) & B_PS_LDM_32K_EN) >> B_PS_LDM_32K_EN_SH; + if (req_32k != rpwm_32k) + return MACCPWMPWRSTATERR; + + //There is no CPWM if 32K state + if (req_32k) + return MACSUCCESS; + +#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + cpwm = MAC_REG_R16(R_AX_CPWM); +#endif + + PLTFM_MSG_TRACE("Read CPWM=0x%x\n", cpwm); + if (rpwm_seq_num != GET_FIELD(cpwm, PS_CPWM_RSP_SEQ_NUM)) { + PLTFM_MSG_TRACE("RPWM seq mismatch!!: expect val:%d, Rx val:%d\n", + rpwm_seq_num, GET_FIELD(cpwm, PS_CPWM_RSP_SEQ_NUM)); + return MACCPWMSEQERR; + } + + if (_chk_cpwm_seq_num(GET_FIELD(cpwm, PS_CPWM_SEQ_NUM)) == MACCPWMSEQERR) { + PLTFM_MSG_TRACE("CPWM seq mismatch!!: expect val:%d, Rx val:%d\n", + cpwm_seq_num, GET_FIELD(cpwm, PS_CPWM_SEQ_NUM)); + return MACCPWMSEQERR; + } + + if (req_pwr_state != GET_FIELD(cpwm, PS_CPWM_STATE)) + return MACCPWMSTATERR; + + adapter->mac_pwr_info.pwr_in_lps = 0; + + return MACSUCCESS; +} + +u32 mac_cfg_lps(struct mac_ax_adapter *adapter, u8 macid, + enum mac_ax_ps_mode ps_mode, struct mac_ax_lps_info *lps_info) +{ + u32 ret = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (ps_mode) { + case MAC_AX_PS_MODE_ACTIVE: + ret = leave_lps(adapter, macid); + /* patch form BT BG/LDO issue, ONLY FOR 52B CAV */ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + is_cv(adapter, CAV)) + MAC_REG_W8(R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); + break; + case MAC_AX_PS_MODE_LEGACY: + ret = enter_lps(adapter, macid, lps_info); + /* patch form BT BG/LDO issue, ONLY FOR 52B CAV */ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + is_cv(adapter, CAV)) + MAC_REG_W8(R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); + break; + case MAC_AX_PS_MODE_WMMPS: + // TODO: + break; + default: + return MACNOITEM; + } + + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_ps_pwr_state(struct mac_ax_adapter *adapter, + enum mac_ax_pwr_state_action action, + enum mac_ax_rpwm_req_pwr_state req_pwr_state) +{ + u32 ret = MACSUCCESS; + + switch (action) { + case MAC_AX_PWR_STATE_ACT_REQ: + ret = set_req_pwr_state(adapter, req_pwr_state); + break; + case MAC_AX_PWR_STATE_ACT_CHK: + ret = chk_cur_pwr_state(adapter, req_pwr_state); + break; + default: + ret = MACNOITEM; + } + + return ret; +} + +u32 mac_chk_leave_lps(struct mac_ax_adapter *adapter, u8 macid) +{ + u8 band = 0; + u8 port = 0; + u32 chk_msk = 0; + struct mac_role_tbl *role; + u16 pwrbit_set_reg[2] = {R_AX_PPWRBIT_SETTING, R_AX_PPWRBIT_SETTING_C1}; + u32 pwr_mgt_en_bit = 0xE; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_pause = 0; + u32 reg_sleep = 0; + u8 macid_grp = macid >> MACID_GRP_SH; + u8 macid_sh = macid & MACID_GRP_MASK; + + role = mac_role_srch(adapter, macid); + + if (!role) { + PLTFM_MSG_ERR("[ERR]cannot find macid: %d\n", macid); + return MACNOITEM; + } + + band = role->info.a_info.bb_sel; + port = role->info.a_info.port_int; + + chk_msk = pwr_mgt_en_bit << (PORT_SH * port); + switch (macid_grp) { + case MACID_GRP_0: + reg_sleep = R_AX_MACID_SLEEP_0; + reg_pause = R_AX_SS_MACID_PAUSE_0; + break; + case MACID_GRP_1: + reg_sleep = R_AX_MACID_SLEEP_1; + reg_pause = R_AX_SS_MACID_PAUSE_1; + break; + case MACID_GRP_2: + reg_sleep = R_AX_MACID_SLEEP_2; + reg_pause = R_AX_SS_MACID_PAUSE_2; + break; + case MACID_GRP_3: + reg_sleep = R_AX_MACID_SLEEP_3; + reg_pause = R_AX_SS_MACID_PAUSE_3; + break; + default: + return MACPSSTATFAIL; + } + + // Bypass Tx pause check during STOP SER period + if (adapter->sm.ser_ctrl_st != MAC_AX_SER_CTRL_STOP) + if (MAC_REG_R32(reg_pause) & BIT(macid_sh)) + return MACPSSTATFAIL; + + if ((MAC_REG_R32(pwrbit_set_reg[band]) & chk_msk) || + (MAC_REG_R32(reg_sleep) & BIT(macid_sh))) + return MACPSSTATFAIL; + + return MACSUCCESS; +} + +u8 _is_in_lps(struct mac_ax_adapter *adapter) +{ + u8 i; + + for (i = 0; i < 4; i++) { + if (lps_status[i] != 0) + return 1; + } + + return 0; +} + +void reset_lps_seq_num(struct mac_ax_adapter *adapter) +{ + rpwm_seq_num = RPWM_SEQ_NUM_MAX; + cpwm_seq_num = CPWM_SEQ_NUM_MAX; +} + +static u32 send_h2c_ips_cfg(struct mac_ax_adapter *adapter, + struct ips_cfg *cfg) +{ + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_ips_cfg *fwcmd_ips; + u32 ret; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ips_cfg)); + if (!buf) { + h2cb_free(adapter, h2cb); + return MACNOBUF; + } + + fwcmd_ips = (struct fwcmd_ips_cfg *)buf; + fwcmd_ips->dword0 = + cpu_to_le32(SET_WORD(cfg->macid, FWCMD_H2C_IPS_CFG_MACID) | + (cfg->enable ? FWCMD_H2C_IPS_CFG_ENABLE : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_PS, + FWCMD_H2C_FUNC_IPS_CFG, + 0, + 1); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +} + +static u32 leave_ips(struct mac_ax_adapter *adapter, u8 macid) +{ + struct ips_cfg h2c_ips_cfg; + u32 ret; + + PLTFM_MEMSET(&h2c_ips_cfg, 0, sizeof(struct ips_cfg)); + + h2c_ips_cfg.macid = macid; + h2c_ips_cfg.enable = 0; + + ret = send_h2c_ips_cfg(adapter, &h2c_ips_cfg); + if (ret != MACSUCCESS) + return ret; + + ips_status[(macid >> 5)] &= ~BIT(macid & 0x1F); + + return MACSUCCESS; +} + +static u32 enter_ips(struct mac_ax_adapter *adapter, + u8 macid) +{ + struct ips_cfg h2c_ips_cfg; + u32 ret; + + if (ips_status[(macid >> 5)] & BIT(macid & 0x1F)) { + PLTFM_MSG_ERR("[ERR]:IPS info is null\n"); + ret = leave_ips(adapter, macid); + if (ret != MACSUCCESS) + return ret; + } + + PLTFM_MEMSET(&h2c_ips_cfg, 0, sizeof(struct ips_cfg)); + + h2c_ips_cfg.macid = macid; + h2c_ips_cfg.enable = 1; + + ret = send_h2c_ips_cfg(adapter, &h2c_ips_cfg); + if (ret != MACSUCCESS) + return ret; + + ips_status[(macid >> 5)] |= BIT(macid & 0x1F); + + return MACSUCCESS; +} + +u32 mac_cfg_ips(struct mac_ax_adapter *adapter, u8 macid, + u8 enable) +{ + u32 ret; + + if (enable == 1) + ret = enter_ips(adapter, macid); + else + ret = leave_ips(adapter, macid); + + return ret; +} + +u32 mac_chk_leave_ips(struct mac_ax_adapter *adapter, u8 macid) +{ + u8 band = 0; + u8 port = 0; + u32 chk_msk = 0; + struct mac_role_tbl *role; + u32 pwr_mgt_en_bit = 0xE; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_pause = 0; + u32 reg_sleep = 0; + u8 macid_grp = macid >> MACID_GRP_SH; + u8 macid_sh = macid & MACID_GRP_MASK; + + role = mac_role_srch(adapter, macid); + + if (!role) { + PLTFM_MSG_ERR("[ERR]cannot find macid: %d\n", macid); + return MACNOITEM; + } + + band = role->info.a_info.bb_sel; + port = role->info.a_info.port_int; + + chk_msk = pwr_mgt_en_bit << (PORT_SH * port); + switch (macid_grp) { + case MACID_GRP_0: + reg_sleep = R_AX_MACID_SLEEP_0; + reg_pause = R_AX_SS_MACID_PAUSE_0; + break; + case MACID_GRP_1: + reg_sleep = R_AX_MACID_SLEEP_1; + reg_pause = R_AX_SS_MACID_PAUSE_1; + break; + case MACID_GRP_2: + reg_sleep = R_AX_MACID_SLEEP_2; + reg_pause = R_AX_SS_MACID_PAUSE_2; + break; + case MACID_GRP_3: + reg_sleep = R_AX_MACID_SLEEP_3; + reg_pause = R_AX_SS_MACID_PAUSE_3; + break; + default: + return MACPSSTATFAIL; + } + + // Bypass Tx pause check during STOP SER period + if (adapter->sm.ser_ctrl_st != MAC_AX_SER_CTRL_STOP) + if (MAC_REG_R32(reg_pause) & BIT(macid_sh)) + return MACPSSTATFAIL; + + if (MAC_REG_R32(reg_sleep) & BIT(macid_sh)) + return MACPSSTATFAIL; + + return MACSUCCESS; +} + +u8 _is_in_ips(struct mac_ax_adapter *adapter) +{ + u8 i; + + for (i = 0; i < 4; i++) { + if (ips_status[i] != 0) + return 1; + } + + return 0; +} + +u32 mac_ps_notify_wake(struct mac_ax_adapter *adapter) +{ + struct ps_rpwm_parm parm; + + PLTFM_MEMSET(&parm, 0, sizeof(struct ps_rpwm_parm)); + + if (adapter->mac_pwr_info.pwr_in_lps == 0) { + PLTFM_MSG_ERR("%s: Not in power saving!\n", __func__); + return MACPWRSTAT; + } + + parm.notify_wake = 1; + send_rpwm(adapter, &parm); + + return MACSUCCESS; +} + +u32 mac_cfg_ps_advance_parm(struct mac_ax_adapter *adapter, + struct mac_ax_ps_adv_parm *parm) +{ + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_ps_advance_parm *fwcmd_parm; + u32 ret; + + if (!parm) + return MACBADDR; + + PLTFM_MSG_ALWAYS("%s: MACID(%d), TRXTimeOutTimeSet(%d), TRXTimeOutTimeVal(%d)!\n" + , __func__, parm->macid, parm->trxtimeouttimeset, parm->trxtimeouttimeval); + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ps_advance_parm)); + if (!buf) { + h2cb_free(adapter, h2cb); + return MACNOBUF; + } + + fwcmd_parm = (struct fwcmd_ps_advance_parm *)buf; + fwcmd_parm->dword0 = + cpu_to_le32(SET_WORD(parm->macid, FWCMD_H2C_PS_ADVANCE_PARM_MACID) | + SET_WORD(parm->trxtimeouttimeset, FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMESET)); + fwcmd_parm->dword1 = + cpu_to_le32(SET_WORD(parm->trxtimeouttimeval, FWCMD_H2C_PS_ADVANCE_PARM_TRXTIMEOUTTIMEVAL)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_PS, + FWCMD_H2C_FUNC_PS_ADVANCE_PARM, + 0, + 1); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) { + h2cb_free(adapter, h2cb); + return ret; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/power_saving.h b/phl/hal_g6/mac/mac_ax/power_saving.h new file mode 100644 index 0000000..ef7729e --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/power_saving.h @@ -0,0 +1,354 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_POWER_SAVING_H_ +#define _MAC_AX_POWER_SAVING_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "role.h" + +#define MACID_GRP_SH 5 +#define MACID_GRP_MASK 0x1F +#define PORT_SH 4 + +/** + * @enum last_rpwm_mode + * + * @brief last_rpwm_mode + * + * @var last_rpwm_mode::LAST_RPWM_PS + * Please Place Description here. + * @var last_rpwm_mode::LAST_RPWM_ACTIVE + * Please Place Description here. + */ +enum last_rpwm_mode { + LAST_RPWM_PS = 0x0, + LAST_RPWM_ACTIVE = 0x6, +}; + +/** + * @struct lps_parm + * @brief lps_parm + * + * @var lps_parm::macid + * Please Place Description here. + * @var lps_parm::psmode + * Please Place Description here. + * @var lps_parm::rlbm + * Please Place Description here. + * @var lps_parm::smartps + * Please Place Description here. + * @var lps_parm::awakeinterval + * Please Place Description here. + * @var lps_parm::vouapsd + * Please Place Description here. + * @var lps_parm::viuapsd + * Please Place Description here. + * @var lps_parm::beuapsd + * Please Place Description here. + * @var lps_parm::bkuapsd + * Please Place Description here. + * @var lps_parm::rsvd + * Please Place Description here. + * @var lps_parm::lastrpwm + * Please Place Description here. + * @var lps_parm::rsvd1 + * Please Place Description here. + */ +struct lps_parm { + u32 macid:8; + u32 psmode:8; + u32 rlbm:4; + u32 smartps:4; + u32 awakeinterval:8; + u32 vouapsd:1; + u32 viuapsd:1; + u32 beuapsd:1; + u32 bkuapsd:1; + u32 rsvd:4; + u32 lastrpwm:8; + u32 rsvd1:16; +}; + +/** + * @struct ps_rpwm_parm + * @brief ps_rpwm_parm + * + * @var ps_rpwm_parm::req_pwr_state + * Please Place Description here. + * @var ps_rpwm_parm::notify_wake + * Please Place Description here. + * @var ps_rpwm_parm::rsvd0 + */ +struct ps_rpwm_parm { + enum mac_ax_rpwm_req_pwr_state req_pwr_state; + u32 notify_wake:1; + u32 rsvd0:31; +}; + +/** + * @macid_grp_list + * + * @brief macid_grp_list + * + * @var macid_grp_list::MACID_GRP_0 + * Please Place Description here. + * @var macid_grp_list::MACID_GRP_1 + * Please Place Description here. + * @var macid_grp_list::MACID_GRP_2 + * Please Place Description here. + * @var macid_grp_list::MACID_GRP_3 + * Please Place Description here. + */ +enum macid_grp_list { + MACID_GRP_0 = 0, + MACID_GRP_1 = 1, + MACID_GRP_2 = 2, + MACID_GRP_3 = 3, +}; + +/** + * @struct ips_cfg + * @brief ips_cfg + * + * @var ips_cfg::macid + * Please Place Description here. + * @var ips_cfg::enable + * Please Place Description here. + * @var ips_cfg::rsvd0 + * Please Place Description here. + */ +struct ips_cfg { + u32 macid:8; + u32 enable:1; + u32 rsvd0:23; +}; + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief mac_cfg_lps + * + * @param *adapter + * @param macid + * @param ps_mode + * @param *lps_info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_lps(struct mac_ax_adapter *adapter, u8 macid, + enum mac_ax_ps_mode ps_mode, struct mac_ax_lps_info *lps_info); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief mac_ps_pwr_state + * + * @param *adapter + * @param action + * @param req_pwr_state + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ps_pwr_state(struct mac_ax_adapter *adapter, + enum mac_ax_pwr_state_action action, + enum mac_ax_rpwm_req_pwr_state req_pwr_state); + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief mac_chk_leave_lps + * + * @param *adapter + * @param macid + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_chk_leave_lps(struct mac_ax_adapter *adapter, u8 macid); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief _is_in_lps + * + * @param *adapter + * @return Please Place Description here. + * @retval u8 + */ + +u8 _is_in_lps(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief reset_lps_seq_num + * + * @param *adapter + * @return Please Place Description here. + * @retval void + */ +void reset_lps_seq_num(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup IPS + * @{ + */ + +/** + * @brief mac_cfg_ips + * + * @param *adapter + * @param macid + * @param enable + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_ips(struct mac_ax_adapter *adapter, u8 macid, u8 enable); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup IPS + * @{ + */ + +/** + * @brief mac_chk_leave_ips + * + * @param *adapter + * @param macid + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_chk_leave_ips(struct mac_ax_adapter *adapter, u8 macid); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup IPS + * @{ + */ + +/** + * @brief _is_in_ips + * + * @param *adapter + * @return Please Place Description here. + * @retval u8 + */ +u8 _is_in_ips(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief mac_ps_notify_wake + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ps_notify_wake(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup LPS + * @{ + */ + +/** + * @brief mac_cfg_ps_advance_parm + * + * @param *adapter + * @param parm + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_ps_advance_parm(struct mac_ax_adapter *adapter, + struct mac_ax_ps_adv_parm *parm); +/** + * @} + * @} + */ + +#endif // #define _MAC_AX_POWER_SAVING_H_ + diff --git a/phl/hal_g6/mac/mac_ax/pwr.c b/phl/hal_g6/mac/mac_ax/pwr.c new file mode 100644 index 0000000..c696b64 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/pwr.c @@ -0,0 +1,373 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "pwr.h" +#include "coex.h" + +static void restore_flr_lps(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_WCPU_FW_CTRL, 0); + + MAC_REG_W32(R_AX_AFE_CTRL1, MAC_REG_R32(R_AX_AFE_CTRL1) & + ~B_AX_CMAC_CLK_SEL); + + MAC_REG_W32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, + MAC_REG_R32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN) & + ~(B_AX_GPIO8_PULL_LOW_EN | B_AX_LED1_PULL_LOW_EN)); +} + +static void clr_aon_int(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + if (adapter->hw_info->intf != MAC_AX_INTF_PCIE) + return; + + val32 = MAC_REG_R32(R_AX_FWS0IMR); + val32 &= ~B_AX_FS_GPIOA_INT_EN; + MAC_REG_W32(R_AX_FWS0IMR, val32); + + val32 = MAC_REG_R32(R_AX_FWS0ISR); + val32 |= B_AX_FS_GPIOA_INT; + MAC_REG_W32(R_AX_FWS0ISR, val32); +} + +static u32 _patch_aon_int_leave_lps(struct mac_ax_adapter *adapter) +{ + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, cnt, ret = MACSUCCESS; + + if (adapter->hw_info->intf != MAC_AX_INTF_PCIE) + return MACSUCCESS; + + restore_flr_lps(adapter); + + val32 = MAC_REG_R32(R_AX_FWS0IMR); + val32 |= B_AX_FS_GPIOA_INT_EN; + MAC_REG_W32(R_AX_FWS0IMR, val32); + + ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_SW_IO, + LPS_LEAVE_GPIO); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]set gpio fail %d\n", ret); + return ret; + } + + val32 = MAC_REG_R32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN); + val32 |= B_AX_GPIO10_PULL_HIGH_EN; + MAC_REG_W32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN, val32); + + val32 = MAC_REG_R32(R_AX_GPIO_EXT_CTRL); + val32 |= (BIT10 | BIT18 | BIT26); + MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32); + val32 &= ~BIT10; + MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32); + val32 |= BIT10; + MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32); + + cnt = LPS_POLL_CNT; + while (cnt && (GET_FIELD(MAC_REG_R32(R_AX_IC_PWR_STATE), B_AX_WLMAC_PWR_STE) == + MAC_AX_MAC_LPS)) { + cnt--; + PLTFM_DELAY_US(LPS_POLL_DLY_US); + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]Polling MAC state timeout! 0x3F0 = %X\n", + MAC_REG_R32(R_AX_IC_PWR_STATE)); + return MACPOLLTO; + } + + return MACSUCCESS; +} + +static u32 pwr_cmd_poll(struct mac_ax_adapter *adapter, struct mac_pwr_cfg *seq) +{ + u8 val = 0; + u32 addr; + u32 cnt; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + cnt = PWR_POLL_CNT; + addr = seq->addr; + + while (cnt--) { + val = MAC_REG_R8(addr); + val &= seq->msk; + if (val == (seq->val & seq->msk)) + return MACSUCCESS; + PLTFM_DELAY_US(PWR_POLL_DLY_US); + } + + PLTFM_MSG_ERR("[ERR] Polling timeout\n"); + PLTFM_MSG_ERR("[ERR] addr: %X, %X\n", addr, seq->addr); + PLTFM_MSG_ERR("[ERR] val: %X, %X\n", val, seq->val); + + return MACPOLLTO; +} + +static u32 sub_pwr_seq_start(struct mac_ax_adapter *adapter, + u8 cv_msk, u8 intf_msk, struct mac_pwr_cfg *seq) +{ + u8 val; + u32 addr; + u32 ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + while (seq->cmd != PWR_CMD_END) { + if (!(seq->intf_msk & intf_msk) || !(seq->cut_msk & cv_msk)) + goto next_seq; + + switch (seq->cmd) { + case PWR_CMD_WRITE: + addr = seq->addr; + val = MAC_REG_R8(addr); + val &= ~(seq->msk); + val |= (seq->val & seq->msk); + + MAC_REG_W8(addr, val); + break; + case PWR_CMD_POLL: + ret = pwr_cmd_poll(adapter, seq); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr cmd poll %d\n", ret); + return ret; + } + break; + case PWR_CMD_DELAY: + if (seq->val == PWR_DELAY_US) + PLTFM_DELAY_US(seq->addr); + else + PLTFM_DELAY_US(seq->addr * 1000); + break; + default: + PLTFM_MSG_ERR("[ERR]unknown pwr seq cmd %d\n", + seq->cmd); + return MACNOITEM; + } +next_seq: + seq++; + } + + return MACSUCCESS; +} + +u32 pwr_seq_start(struct mac_ax_adapter *adapter, + struct mac_pwr_cfg **seq) +{ + u8 cv; + u8 intf; + u32 ret; + struct mac_ax_hw_info *hw_info = adapter->hw_info; + struct mac_pwr_cfg *sub_seq = *seq; +#if MAC_AX_USB_SUPPORT + u32 val = 0; +#endif + + switch (hw_info->cv) { + case CAV: + cv = PWR_CAV_MSK; + break; + case CBV: + cv = PWR_CBV_MSK; + break; + case CCV: + cv = PWR_CCV_MSK; + break; + case CDV: + cv = PWR_CDV_MSK; + break; + case CEV: + cv = PWR_CEV_MSK; + break; + default: + PLTFM_MSG_ERR("[ERR]cut version\n"); + return MACNOITEM; + } + + switch (hw_info->intf) { + case MAC_AX_INTF_SDIO: + intf = PWR_INTF_MSK_SDIO; + break; + case MAC_AX_INTF_USB: +#if MAC_AX_USB_SUPPORT + val = get_usb_mode(adapter); + if (val == MAC_AX_USB3) + intf = PWR_INTF_MSK_USB3; + else + intf = PWR_INTF_MSK_USB2; + break; +#endif + case MAC_AX_INTF_PCIE: + intf = PWR_INTF_MSK_PCIE; + break; + default: + PLTFM_MSG_ERR("[ERR]interface\n"); + return MACNOITEM; + } + + while (sub_seq) { + ret = sub_pwr_seq_start(adapter, cv, intf, sub_seq); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sub pwr seq %d\n", ret); + return ret; + } + seq++; + sub_seq = *seq; + } + + return MACSUCCESS; +} + +u32 mac_pwr_switch(struct mac_ax_adapter *adapter, u8 on) +{ + u32 ret = MACSUCCESS; + u32 ret_end; + struct mac_pwr_cfg **pwr_seq; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 (*intf_pwr_switch)(void *vadapter, u8 pre_switch, u8 on); + u32 (*pwr_func)(void *vadapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_GPIO_MUXCFG) & B_AX_BOOT_MODE; + if (val32 == B_AX_BOOT_MODE) { + val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL) & ~B_AX_APFN_ONMAC; + MAC_REG_W32(R_AX_SYS_PW_CTRL, val32); + val32 = MAC_REG_R32(R_AX_SYS_STATUS1) & ~B_AX_AUTO_WLPON; + MAC_REG_W32(R_AX_SYS_STATUS1, val32); + val32 = MAC_REG_R32(R_AX_GPIO_MUXCFG) & ~B_AX_BOOT_MODE; + MAC_REG_W32(R_AX_GPIO_MUXCFG, val32); + val32 = MAC_REG_R32(R_AX_RSV_CTRL) & ~B_AX_R_DIS_PRST; + MAC_REG_W32(R_AX_RSV_CTRL, val32); + } + + val32 = MAC_REG_R32(R_AX_IC_PWR_STATE); + val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE); + if (val32 == MAC_AX_MAC_OFF && on == MAC_AX_MAC_OFF) { + PLTFM_MSG_WARN("MAC has already powered off\n"); + return MACSUCCESS; + } + + intf_pwr_switch = adapter->mac_pwr_info.intf_pwr_switch; + + if (!intf_pwr_switch) { + PLTFM_MSG_ERR("interface power switch func is NULL\n"); + ret = MACNPTR; + return ret; + } + + if (on) { + pwr_seq = adapter->hw_info->pwr_on_seq; + pwr_func = adapter->hw_info->pwr_on; + } else { + pwr_seq = adapter->hw_info->pwr_off_seq; + pwr_func = adapter->hw_info->pwr_off; + adapter->sm.pwr = MAC_AX_PWR_PRE_OFF; + adapter->sm.dmac_func = MAC_AX_FUNC_OFF; + adapter->sm.cmac0_func = MAC_AX_FUNC_OFF; + adapter->sm.cmac1_func = MAC_AX_FUNC_OFF; + adapter->sm.bb0_func = MAC_AX_FUNC_OFF; + adapter->sm.bb1_func = MAC_AX_FUNC_OFF; + adapter->sm.plat = MAC_AX_PLAT_OFF; + } + + ret = intf_pwr_switch(adapter, PWR_PRE_SWITCH, on); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("interface pre pwr switch fails %d\n", ret); + goto END; + } + + if (on) { + ret = _patch_aon_int_leave_lps(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("AON interrupt leave LPS fail %X\n", ret); + goto END; + } + + val32 = MAC_REG_R32(R_AX_IC_PWR_STATE); + val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE); + if (val32 == MAC_AX_MAC_ON) { + PLTFM_MSG_WARN("MAC has already powered on %d\n", val32); + ret = MACALRDYON; + goto END; + } else if (val32 == MAC_AX_MAC_LPS) { + PLTFM_MSG_ERR("MAC leave LPS fail %d\n", val32); + ret = MACPWRSTAT; + goto END; + } + } + + if (!pwr_func) { + ret = pwr_seq_start(adapter, pwr_seq); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr seq start %d\n", ret); + adapter->sm.pwr = MAC_AX_PWR_ERR; + goto END; + } + } else { + ret = pwr_func(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr func %d\n", ret); + adapter->sm.pwr = MAC_AX_PWR_ERR; + goto END; + } + } + + ret = intf_pwr_switch(adapter, PWR_POST_SWITCH, on); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("interface post pwr switch fails %d\n", ret); + adapter->sm.pwr = MAC_AX_PWR_ERR; + goto END; + } + + mac_ax_init_state(adapter); + + if (on) { + adapter->sm.pwr = MAC_AX_PWR_ON; + adapter->sm.plat = MAC_AX_PLAT_ON; + adapter->sm.io_st = MAC_AX_IO_ST_NORM; + adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE; + adapter->sm.l2_st = MAC_AX_L2_DIS; + adapter->mac_pwr_info.pwr_in_lps = 0; + /* patch form BT BG/LDO issue, ONLY FOR 52B CAV */ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + is_cv(adapter, CAV)) + MAC_REG_W32(R_AX_SCOREBOARD, + (u32)(MAC_AX_NOTIFY_TP_MAJOR << + MAC_AX_NOTIFY_SH)); + } else { + adapter->sm.pwr = MAC_AX_PWR_OFF; + adapter->sm.l2_st = MAC_AX_L2_DIS; + /* patch form BT BG/LDO issue, ONLY FOR 52B CAV */ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && + is_cv(adapter, CAV)) + MAC_REG_W32(R_AX_SCOREBOARD, + (u32)(MAC_AX_NOTIFY_PWR_MAJOR << + MAC_AX_NOTIFY_SH)); + } +END: + if (on) + clr_aon_int(adapter); + ret_end = intf_pwr_switch(adapter, PWR_END_SWITCH, on); + if (ret_end != MACSUCCESS) { + PLTFM_MSG_ERR("interface end pwr switch fails %d\n", ret_end); + adapter->sm.pwr = MAC_AX_PWR_ERR; + return ret_end; + } + return ret; +} diff --git a/phl/hal_g6/mac/mac_ax/pwr.h b/phl/hal_g6/mac/mac_ax/pwr.h new file mode 100644 index 0000000..79a3122 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/pwr.h @@ -0,0 +1,120 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PWR_H_ +#define _MAC_AX_PWR_H_ + +#include "../type.h" +#include "init.h" + +/** + * Power switch command description + * @PWR_CMD_WRITE: + * @PWR_CMD_POLL: + * @PWR_CMD_DELAY: + * @PWR_CMD_END: + */ +#define PWR_CMD_WRITE 0 +#define PWR_CMD_POLL 1 +#define PWR_CMD_DELAY 2 +#define PWR_CMD_END 3 + +#define PWR_CAV_MSK BIT(0) +#define PWR_CBV_MSK BIT(1) +#define PWR_CCV_MSK BIT(2) +#define PWR_CDV_MSK BIT(3) +#define PWR_CEV_MSK BIT(4) +#define PWR_CFV_MSK BIT(5) +#define PWR_CGV_MSK BIT(6) +#define PWR_CTV_MSK BIT(7) +#define PWR_CVALL_MSK 0xFF + +#define PWR_INTF_MSK_SDIO BIT(0) +#define PWR_INTF_MSK_USB2 BIT(1) +#define PWR_INTF_MSK_USB3 BIT(2) +#define PWR_INTF_MSK_USB (PWR_INTF_MSK_USB3 | PWR_INTF_MSK_USB2) +#define PWR_INTF_MSK_PCIE BIT(3) +#define PWR_INTF_MSK_ALL 0xF + +#define PWR_BASE_MAC 0 +#define PWR_BASE_USB 1 +#define PWR_BASE_PCIE 2 + +#define PWR_DELAY_US 0 +#define PWR_DELAY_MS 1 + +#define PWR_POLL_CNT 2000 +#define PWR_POLL_DLY_US 1000 + +#define LPS_LEAVE_GPIO 10 +#define LPS_POLL_CNT 10000 +#define LPS_POLL_DLY_US 50 + +#define PWR_POST_SWITCH 0 +#define PWR_PRE_SWITCH 1 +#define PWR_END_SWITCH 2 + +/** + * @struct mac_pwr_cfg + * @brief mac_pwr_cfg + * + * @var mac_pwr_cfg::addr + * Please Place Description here. + * @var mac_pwr_cfg::cut_msk + * Please Place Description here. + * @var mac_pwr_cfg::intf_msk + * Please Place Description here. + * @var mac_pwr_cfg::base + * Please Place Description here. + * @var mac_pwr_cfg::cmd + * Please Place Description here. + * @var mac_pwr_cfg::msk + * Please Place Description here. + * @var mac_pwr_cfg::val + * Please Place Description here. + */ +struct mac_pwr_cfg { + u16 addr; + u8 cut_msk; + u8 intf_msk; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 val; +}; + +/** + * @brief pwr_seq_start + * + * @param *adapter + * @param **seq + * @return Please Place Description here. + * @retval u32 + */ +u32 pwr_seq_start(struct mac_ax_adapter *adapter, struct mac_pwr_cfg **seq); + +/** + * @brief mac_pwr_switch + * + * @param *adapter + * @param on + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_pwr_switch(struct mac_ax_adapter *adapter, u8 on); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/pwr_seq_func.c b/phl/hal_g6/mac/mac_ax/pwr_seq_func.c new file mode 100644 index 0000000..b6364bc --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/pwr_seq_func.c @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "pwr_seq_func.h" +#define MAC_AX_PWR_POLL_CNT 20 +#define MAC_AX_PWR_POLL_MS 1 + +u32 pwr_poll_u32(struct mac_ax_adapter *adapter, u32 offset, + u32 mask, u32 pwr_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt = MAC_AX_PWR_POLL_CNT, val; + + while (--cnt) { + val = MAC_REG_R32(offset); + if ((val & mask) == pwr_val) + return MACSUCCESS; + PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS); + } + + PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n"); + PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset); + PLTFM_MSG_ERR("[ERR] read val: %08X, targe val: %08X\n", (val & mask), pwr_val); + + return MACPOLLTO; +} + +u32 pwr_poll_u16(struct mac_ax_adapter *adapter, u32 offset, + u16 mask, u16 pwr_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt = MAC_AX_PWR_POLL_CNT; + u16 val; + + while (--cnt) { + val = MAC_REG_R16(offset); + if ((val & mask) == pwr_val) + return MACSUCCESS; + PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS); + } + + PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n"); + PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset); + PLTFM_MSG_ERR("[ERR] read val: %04X, targe val: %04X\n", (val & mask), pwr_val); + + return MACPOLLTO; +} + +u32 pwr_poll_u8(struct mac_ax_adapter *adapter, u32 offset, + u8 mask, u8 pwr_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt = MAC_AX_PWR_POLL_CNT; + u8 val; + + while (--cnt) { + val = MAC_REG_R8(offset); + if ((val & mask) == pwr_val) + return MACSUCCESS; + PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS); + } + + PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n"); + PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset); + PLTFM_MSG_ERR("[ERR] read val: %02X, targe val: %02X\n", (val & mask), pwr_val); + + return MACPOLLTO; +} diff --git a/phl/hal_g6/mac/mac_ax/pwr_seq_func.h b/phl/hal_g6/mac/mac_ax/pwr_seq_func.h new file mode 100644 index 0000000..982cb90 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/pwr_seq_func.h @@ -0,0 +1,28 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PWR_SEQ_FUNC_H_ +#define _MAC_AX_PWR_SEQ_FUNC_H_ + +#include "../mac_def.h" + +u32 pwr_poll_u32(struct mac_ax_adapter *adapter, u32 offset, + u32 mask, u32 pwr_val); +u32 pwr_poll_u16(struct mac_ax_adapter *adapter, u32 offset, + u16 mask, u16 pwr_val); +u32 pwr_poll_u8(struct mac_ax_adapter *adapter, u32 offset, + u8 mask, u8 pwr_val); +#endif diff --git a/phl/hal_g6/mac/mac_ax/role.c b/phl/hal_g6/mac/mac_ax/role.c new file mode 100644 index 0000000..fd728f5 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/role.c @@ -0,0 +1,1199 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "role.h" + +#define MAC_AX_ACTUAL_WMM_BAND BIT(1) +#define MAC_AX_ACTUAL_WMM_DRV_WMM BIT(0) + +static inline void __role_queue_head_init(struct mac_ax_adapter *adapter, + struct mac_role_tbl_head *list) +{ + PLTFM_MUTEX_LOCK(&list->lock); + list->prev = (struct mac_role_tbl *)list; + list->next = (struct mac_role_tbl *)list; + list->qlen = 0; + PLTFM_MUTEX_UNLOCK(&list->lock); +} + +static inline void __role_insert(struct mac_ax_adapter *adapter, + struct mac_role_tbl *new_role, + struct mac_role_tbl *prev, + struct mac_role_tbl *next, + struct mac_role_tbl_head *list) +{ + PLTFM_MUTEX_LOCK(&list->lock); + new_role->next = next; + new_role->prev = prev; + next->prev = new_role; + prev->next = new_role; + list->qlen++; + PLTFM_MUTEX_UNLOCK(&list->lock); +} + +static inline void __role_queue_before(struct mac_ax_adapter *adapter, + struct mac_role_tbl_head *list, + struct mac_role_tbl *next, + struct mac_role_tbl *new_role) +{ + __role_insert(adapter, new_role, next->prev, next, list); +} + +static inline void __role_unlink(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, + struct mac_role_tbl_head *list) +{ + struct mac_role_tbl *next, *prev; + + PLTFM_MUTEX_LOCK(&list->lock); + list->qlen--; + next = role->next; + prev = role->prev; + role->prev = NULL; + role->next = NULL; + next->prev = prev; + prev->next = next; + PLTFM_MUTEX_UNLOCK(&list->lock); +} + +static inline struct mac_role_tbl *__role_peek(struct mac_role_tbl_head *list) +{ + struct mac_role_tbl *role = list->next; + + if (role == (struct mac_role_tbl *)list) + role = NULL; + return role; +} + +static struct mac_role_tbl *role_alloc(struct mac_ax_adapter *adapter) +{ + struct mac_role_tbl *role; + + role = (struct mac_role_tbl *)PLTFM_MALLOC(sizeof(struct mac_role_tbl)); + if (!role) + return NULL; + + role->macid = 0; + role->wmm = 0; + + return role; +} + +static inline u32 role_queue_len(struct mac_role_tbl_head *list) +{ + return list->qlen; +} + +static inline void role_queue_head_init(struct mac_ax_adapter *adapter, + struct mac_role_tbl_head *list) +{ + PLTFM_MUTEX_INIT(&list->lock); + __role_queue_head_init(adapter, list); +} + +static inline void role_enqueue(struct mac_ax_adapter *adapter, + struct mac_role_tbl_head *list, + struct mac_role_tbl *new_role) +{ + __role_queue_before(adapter, + list, (struct mac_role_tbl *)list, new_role); +} + +static inline struct mac_role_tbl *role_dequeue(struct mac_ax_adapter *adapter, + struct mac_role_tbl_head *list) +{ + struct mac_role_tbl *role = __role_peek(list); + + if (role) + __role_unlink(adapter, role, list); + return role; +} + +static struct mac_role_tbl *role_get(struct mac_ax_adapter *adapter) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *role_pool; + + if (adapter->role_tbl) + role_pool = adapter->role_tbl->role_tbl_pool; + else + return NULL; + + if (!role_pool->qlen) + role = NULL; + else + role = role_dequeue(adapter, role_pool); + + return role; +} + +static void role_return(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role) +{ + struct mac_role_tbl_head *role_head = adapter->role_tbl; + struct mac_role_tbl_head *role_pool = NULL; + + if (role_head) + role_pool = adapter->role_tbl->role_tbl_pool; + else + return; + + __role_unlink(adapter, role, role_head); + role_enqueue(adapter, role_pool, role); +} + +static u32 role_free(struct mac_ax_adapter *adapter) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *role_head; + struct mac_role_tbl_head *role_pool = NULL; + u32 ret = MACSUCCESS; + + role_head = adapter->role_tbl; + if (role_head) { + role_pool = role_head->role_tbl_pool; + while (role_queue_len(role_head) > 0) { + role = role_dequeue(adapter, role_head); + if (role) { + PLTFM_FREE(role, sizeof(struct mac_role_tbl)); + } else { + ret = MACMEMRO; + break; + } + } + PLTFM_MUTEX_DEINIT(&role_head->lock); + } + if (role_pool) { + while (role_queue_len(role_pool) > 0) { + role = role_dequeue(adapter, role_pool); + if (role) { + PLTFM_FREE(role, sizeof(struct mac_role_tbl)); + } else { + ret = MACMEMRO; + break; + } + } + PLTFM_MUTEX_DEINIT(&role_pool->lock); + } + + return ret; +} + +u32 role_info_valid(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + enum mac_ax_role_opmode op) +{ + // Check info is NULL or not + if (!info) { + PLTFM_MSG_ERR("role info is null\n"); + return MACNPTR; + } + + if (op == ADD) { + // check add role opmode + if (info->opmode != MAC_AX_ROLE_DISCONN) { + PLTFM_MSG_ERR("add_role, opmode should equals to:\n"); + PLTFM_MSG_ERR("MAC_AX_ROLE_DISCONN\n"); + return MACFUNCINPUT; + } + // check add role updmode + if (info->upd_mode != MAC_AX_ROLE_CREATE) { + PLTFM_MSG_ERR("add_role, updmode should equals to:\n"); + PLTFM_MSG_ERR("MAC_AX_ROLE_CREATE\n"); + return MACFUNCINPUT; + } + // Check macid exist or not + if (mac_role_srch(adapter, info->macid)) { + PLTFM_MSG_ERR("existing macid: %d\n", info->macid); + return MACSAMACID; + } + } else if (op == CHG) { + if (info->upd_mode == MAC_AX_ROLE_CREATE) { + PLTFM_MSG_ERR("change_role, updmode should not:\n"); + PLTFM_MSG_ERR("equals to MAC_AX_ROLE_CREATE\n"); + return MACFUNCINPUT; + } + if (!mac_role_srch(adapter, info->macid)) { + PLTFM_MSG_ERR("macid not exist: %d\n", info->macid); + return MACNOITEM; + } + } + + // If net_type is IFRA, self_role should only be CLIENT + if (info->net_type == MAC_AX_NET_TYPE_INFRA && + (info->self_role == MAC_AX_SELF_ROLE_AP || + info->self_role == MAC_AX_SELF_ROLE_AP_CLIENT)) { + PLTFM_MSG_ERR("net_type is INFRA, self_role can only be:\n"); + PLTFM_MSG_ERR("CLIENT\n"); + return MACFUNCINPUT; + } + + // If net_type is AP, self_role should be AP or AP_CLIENT + if (info->net_type == MAC_AX_NET_TYPE_AP && + info->self_role == MAC_AX_SELF_ROLE_CLIENT) { + PLTFM_MSG_ERR("net_type is AP, self_role should be AP:\n"); + PLTFM_MSG_ERR("or AP_CLIENT\n"); + return MACFUNCINPUT; + } + + // If self_role is AP, the SMA and TMA should equals to BSSID + if (info->self_role == MAC_AX_SELF_ROLE_AP && + info->net_type == MAC_AX_NET_TYPE_AP) { + if (PLTFM_MEMCMP(info->self_mac, info->bssid, 6) || + PLTFM_MEMCMP(info->target_mac, info->bssid, 6)) { + PLTFM_MSG_ERR("self_role is AP, the SMA and TMA:\n"); + PLTFM_MSG_ERR("should equal to BSSID\n"); + return MACFUNCINPUT; + } + } + + // If is_mulitcast_entry = 1, group bit should equals to 1 + if (!(info->is_mul_ent ^ + ((info->net_type != MAC_AX_NET_TYPE_AP && + ((info->self_mac[0] & BIT0) == 0)) || + (info->net_type == MAC_AX_NET_TYPE_AP && + ((info->bssid[0] & BIT0) == 0))))) { + PLTFM_MSG_ERR("is_mul_ent = 1, group bit should = 1\n"); + return MACFUNCINPUT; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (info->wmm >= 2) { + PLTFM_MSG_ERR("invalid wmm %d\n", info->wmm); + return MACFUNCINPUT; + } + if (info->band == MAC_AX_BAND_1) { + PLTFM_MSG_ERR("invalid band %d\n", info->band); + return MACFUNCINPUT; + } + } + + if (info->band >= MAC_AX_BAND_NUM) { + PLTFM_MSG_ERR("invalid band %d\n", info->band); + return MACFUNCINPUT; + } + + return MACSUCCESS; +} + +u32 role_tbl_init(struct mac_ax_adapter *adapter) +{ + struct mac_role_tbl *role = NULL; + struct mac_role_tbl_head *role_head; + struct mac_role_tbl_head *role_pool; + u16 a_idx; + u32 ret = 0; + + adapter->role_tbl = NULL; + adapter->role_tbl = (struct mac_role_tbl_head *) + PLTFM_MALLOC(sizeof(struct mac_role_tbl_head)); + if (!adapter->role_tbl) { + PLTFM_MSG_ERR("%s memory alloc failed\n", __func__); + return MACBUFALLOC; + } + + adapter->role_tbl->role_tbl_pool = NULL; + adapter->role_tbl->role_tbl_pool = (struct mac_role_tbl_head *) + PLTFM_MALLOC(sizeof(struct mac_role_tbl_head)); + if (!adapter->role_tbl->role_tbl_pool) { + PLTFM_MSG_ERR("%s memory alloc failed\n", __func__); + return MACBUFALLOC; + } + + role_head = adapter->role_tbl; + role_pool = adapter->role_tbl->role_tbl_pool; + + role_queue_head_init(adapter, role_head); + role_queue_head_init(adapter, role_pool); + + for (a_idx = 0; a_idx < adapter->hw_info->macid_num; a_idx++) { + role = role_alloc(adapter); + if (role) { + role_enqueue(adapter, role_pool, role); + } else { + PLTFM_MSG_ERR("%s memory alloc failed\n", __func__); + ret = MACBUFALLOC; + break; + } + } + + if (a_idx < adapter->hw_info->macid_num) + role_tbl_exit(adapter); + else + ret = MACSUCCESS; + + return ret; +} + +u32 role_tbl_exit(struct mac_ax_adapter *adapter) +{ + u32 ret = MACSUCCESS; + + ret = role_free(adapter); + if (ret != MACSUCCESS) + PLTFM_MSG_ERR("%s memory free failed\n", __func__); + + if (adapter->role_tbl) { + if (adapter->role_tbl->role_tbl_pool) { + PLTFM_FREE(adapter->role_tbl->role_tbl_pool, + sizeof(struct mac_role_tbl_head)); + adapter->role_tbl->role_tbl_pool = NULL; + } + PLTFM_FREE(adapter->role_tbl, + sizeof(struct mac_role_tbl_head)); + adapter->role_tbl = NULL; + } + return ret; +} + +u32 role_info_init(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u8 i; + + // address cam info + info->a_info.len = get_addr_cam_size(adapter); + info->a_info.offset = 0; + info->a_info.mask_sel = info->mask_sel; + info->a_info.addr_mask = info->addr_mask; + info->a_info.hit_rule = info->hit_rule; + info->a_info.bcn_hit_cond = info->bcn_hit_cond; + info->a_info.is_mul_ent = info->is_mul_ent; + info->a_info.port_int = info->port; + info->a_info.tsf_sync = info->tsf_sync; + info->a_info.lsig_txop = info->lsig_txop; + info->a_info.tgt_ind = info->tgt_ind; + info->a_info.frm_tgt_ind = info->frm_tgt_ind; + info->a_info.wol_pattern = info->wol_pattern; + info->a_info.wol_uc = info->wol_uc; + info->a_info.wol_magic = info->wol_magic; + info->a_info.bb_sel = info->band; + info->a_info.tf_trs = info->trigger; + info->a_info.aid12 = info->aid & 0xfff; + info->a_info.macid = info->macid; + info->a_info.wapi = info->wapi; + info->a_info.sec_ent_mode = info->sec_ent_mode; + info->a_info.net_type = info->net_type; + + // bssid cam info + info->b_info.len = BSSID_CAM_ENT_SIZE; + info->b_info.offset = 0; + info->b_info.valid = 1; + info->b_info.bss_color = info->bss_color; + info->b_info.bb_sel = info->band; + + for (i = 0; i < 6; i++) { + info->a_info.sma[i] = info->self_mac[i]; + info->a_info.tma[i] = info->target_mac[i]; + info->b_info.bssid[i] = info->bssid[i]; + } + + return MACSUCCESS; +} + +u32 sec_info_init(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u8 i; + + info->a_info.sec_ent_valid = 0; + for (i = 0; i < 7; i++) { + info->a_info.sec_ent_keyid[i] = 0; + info->a_info.sec_ent[i] = 0; + } + + return MACSUCCESS; +} + +u32 sec_info_deinit(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct mac_role_tbl *role) +{ + u32 i, ret; + struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table; + + if (!sec_cam_table) + return MACSUCCESS; + + ret = disconnect_flush_key(adapter, role); + if (ret != MACSUCCESS) + return ret; + + /* deinit info */ + info->a_info.sec_ent_mode = 0; + info->a_info.sec_ent_valid = 0; + for (i = 0; i < 7; i++) { + info->a_info.sec_ent_keyid[i] = 0; + info->a_info.sec_ent[i] = 0; + } + + /* deinit role */ + role->info.a_info.sec_ent_mode = 0; + role->info.a_info.sec_ent_valid = 0; + for (i = 0; i < 7; i++) { + role->info.a_info.sec_ent_keyid[i] = 0; + role->info.a_info.sec_ent[i] = 0; + } + + return MACSUCCESS; +} + +u32 role_init(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, + struct mac_ax_role_info *info) +{ + struct mac_ax_macid_pause_cfg pause; + u32 ret; + + role_info_init(adapter, info); + + pause.macid = info->macid; + pause.pause = 0; + ret = set_macid_pause(adapter, &pause); + if (ret != MACSUCCESS) + return ret; + + /* The definition of wmm is different between MAC & drivers + * MAC HW use wmm 0~3 to indicate + * phy0-wmm0, phy0-wmm1, phy1-wmm0, phy1-wmm1 correspondingly. + * Drivers use wmm 0/1 & band 0/1 + */ + role->macid = info->macid; + role->wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) | + (info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0); + role->info = *info; + + return MACSUCCESS; +} + +u32 set_role_bss_clr(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 bss_clr = 0; + + switch (info->port) { + case MAC_AX_PORT_0: + bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1); + bss_clr = SET_CLR_WORD(bss_clr, info->bss_color, + B_AX_BSS_COLOB_AX_PORT_0); + MAC_REG_W32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1, bss_clr); + break; + case MAC_AX_PORT_1: + bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1); + bss_clr = SET_CLR_WORD(bss_clr, info->bss_color, + B_AX_BSS_COLOB_AX_PORT_1); + MAC_REG_W32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1, bss_clr); + break; + case MAC_AX_PORT_2: + bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1); + bss_clr = SET_CLR_WORD(bss_clr, info->bss_color, + B_AX_BSS_COLOB_AX_PORT_2); + MAC_REG_W32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1, bss_clr); + break; + case MAC_AX_PORT_3: + bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1); + bss_clr = SET_CLR_WORD(bss_clr, info->bss_color, + B_AX_BSS_COLOB_AX_PORT_3); + MAC_REG_W32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_0 : + R_AX_PTCL_BSS_COLOR_0_C1, bss_clr); + break; + case MAC_AX_PORT_4: + bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_1 : + R_AX_PTCL_BSS_COLOR_1_C1); + bss_clr = SET_CLR_WORD(bss_clr, info->bss_color, + B_AX_BSS_COLOB_AX_PORT_4); + MAC_REG_W32((info->band == MAC_AX_BAND_0) ? + R_AX_PTCL_BSS_COLOR_1 : + R_AX_PTCL_BSS_COLOR_1_C1, bss_clr); + break; + default: + break; + } + return 0; +} + +u32 mac_add_role(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info) +{ + struct mac_role_tbl *role = NULL; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + u32 ret = MACSUCCESS; + u32 cmac_en; + + cmac_en = check_mac_en(adapter, info->band, MAC_AX_CMAC_SEL); + if (cmac_en != MACSUCCESS) + PLTFM_MSG_WARN("%s CMAC%d not enable\n", __func__, info->band); + + role = role_get(adapter); + if (!role) { + PLTFM_MSG_ERR("role get failed\n"); + return MACBUFALLOC; + } + + ret = role_info_valid(adapter, info, ADD); + if (ret != MACSUCCESS) + goto role_add_fail; + + info->a_info.valid = 1; + if (role_queue_len(list_head) > adapter->hw_info->macid_num) { + PLTFM_MSG_ERR("role list full\n"); + ret = MACMACIDFL; + goto role_add_fail; + } + + if (sec_info_init(adapter, info)) { + PLTFM_MSG_ERR("sec info change failed\n"); + return MACROLEINITFL; + } + + if (role_init(adapter, role, info)) { + PLTFM_MSG_ERR("role init failed\n"); + ret = MACROLEINITFL; + goto role_add_fail; + } + + ret = mac_fw_role_maintain(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip fw role maintain\n"); + } else { + PLTFM_MSG_ERR("mac_fw_role_maintain failed:%d\n", ret); + goto role_add_fail; + } + } + + if (info->self_role == MAC_AX_SELF_ROLE_AP) { + ret = mac_h2c_join_info(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip join info\n"); + } else { + PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret); + return ret; + } + } + } + + ret = mac_upd_addr_cam(adapter, &role->info, ADD); + + if (ret == MACADDRCAMFL) { + PLTFM_MSG_ERR("ADDRESS CAM full\n"); + ret = MACADDRCAMFL; + goto role_add_fail; + } else if (ret == MACBSSIDCAMFL) { + PLTFM_MSG_ERR("BSSID CAM full\n"); + ret = MACBSSIDCAMFL; + goto role_add_fail; + } + + role_enqueue(adapter, list_head, role); + + if (cmac_en) + set_role_bss_clr(adapter, info); + + return MACSUCCESS; + +role_add_fail: + role_enqueue(adapter, list_head->role_tbl_pool, role); + return ret; +} + +u32 mac_change_role(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + struct mac_role_tbl *role; + u32 ret; + u32 cmac_en; + + cmac_en = check_mac_en(adapter, info->band, MAC_AX_CMAC_SEL); + if (cmac_en != MACSUCCESS) + PLTFM_MSG_WARN("%s CMAC%d not enable\n", __func__, info->band); + + ret = role_info_valid(adapter, info, CHG); + if (ret != MACSUCCESS) + return ret; + + role = mac_role_srch(adapter, info->macid); + if (!role) { + PLTFM_MSG_ERR("role search failed\n"); + return MACNOITEM; + } + + info->a_info = role->info.a_info; + if (role_info_init(adapter, info)) { + PLTFM_MSG_ERR("role change failed\n"); + return MACROLEINITFL; + } + + role->macid = info->macid; + role->wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) | + (info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0); + role->info = *info; + + if (info->upd_mode == MAC_AX_ROLE_TYPE_CHANGE || + info->upd_mode == MAC_AX_ROLE_REMOVE) { + ret = mac_fw_role_maintain(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip fw role maintain\n"); + } else { + PLTFM_MSG_ERR("mac_fw_role_maintain :%d\n", + ret); + return ret; + } + } + if (info->upd_mode == MAC_AX_ROLE_TYPE_CHANGE && + info->self_role == MAC_AX_SELF_ROLE_AP) { + ret = mac_h2c_join_info(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip join info\n"); + } else { + PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", + ret); + return ret; + } + } + } + } else if (info->upd_mode == MAC_AX_ROLE_CON_DISCONN) { + if (info->opmode == MAC_AX_ROLE_DISCONN) { + ret = sec_info_deinit(adapter, info, role); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("sec info change failed\n"); + return ret; + } + } + ret = mac_h2c_join_info(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip join info\n"); + } else { + PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret); + return ret; + } + } + } else if (info->upd_mode == MAC_AX_ROLE_INFO_CHANGE) { + ret = mac_h2c_join_info(adapter, info); + if (ret != MACSUCCESS) { + if (ret == MACFWNONRDY) { + PLTFM_MSG_WARN("skip join info\n"); + } else { + PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret); + return ret; + } + } + } else { + PLTFM_MSG_ERR("role info upd_mode invalid\n"); + return ret; + } + + ret = mac_upd_addr_cam(adapter, &role->info, CHG); + if (ret == MACBSSIDCAMFL) { + PLTFM_MSG_ERR("BSSID CAM full\n"); + return MACBSSIDCAMFL; + } + + if (cmac_en) + set_role_bss_clr(adapter, info); + + return ret; +} + +u32 mac_remove_role(struct mac_ax_adapter *adapter, u8 macid) +{ + struct mac_role_tbl *role; + u32 ret; + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("no role for macid %d\n", macid); + return MACNOROLE; + } + + role->info.a_info.valid = 0; + role->info.upd_mode = MAC_AX_ROLE_REMOVE; + role->info.opmode = MAC_AX_ROLE_DISCONN; + + if (!mac_role_srch_by_bssid(adapter, role->info.a_info.bssid_cam_idx)) + role->info.b_info.valid = 0; + + ret = mac_change_role(adapter, &role->info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: %d\n", __func__, ret); + return ret; + } + + role_return(adapter, role); + + return MACSUCCESS; +} + +static u32 mac_remove_role_soft(struct mac_ax_adapter *adapter, u8 macid) +{ + /* This function should be called only before poweroff, + * because it will unlink the role without update any info to FW + */ + struct mac_role_tbl *role; + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("no role for macid %d\n", macid); + return MACNOROLE; + } + + role_return(adapter, role); + + return MACSUCCESS; +} + +u32 mac_remove_role_by_band(struct mac_ax_adapter *adapter, u8 band, u8 sw) +{ + struct mac_role_tbl *role, *curr_role; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + u32 ret = MACSUCCESS; + u32 (*_rm_role)(struct mac_ax_adapter *adapter, u8 macid); + + if (sw) + _rm_role = mac_remove_role_soft; + else + _rm_role = mac_remove_role; + + role = list_head->next; + while (role->next != list_head->next) { + curr_role = role; + role = role->next; + if (band == curr_role->info.band) { + ret = _rm_role(adapter, curr_role->macid); + if (ret && ret != MACNOROLE) + return ret; + } + } + + return MACSUCCESS; +} + +struct mac_role_tbl *mac_role_srch(struct mac_ax_adapter *adapter, u8 macid) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + + if (!list_head) + return NULL; + + role = list_head->next; + for (; role->next != list_head->next; role = role->next) { + if (macid == role->macid) + return role; + } + + return NULL; +} + +struct mac_role_tbl *mac_role_srch_by_addr_cam(struct mac_ax_adapter *adapter, + u16 addr_cam_idx) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + + if (!list_head) + return NULL; + + role = list_head->next; + for (; role->next != list_head->next; role = role->next) { + if (addr_cam_idx == role->info.a_info.addr_cam_idx && + role->info.a_info.valid) + return role; + } + + return NULL; +} + +struct mac_role_tbl *mac_role_srch_by_bssid(struct mac_ax_adapter *adapter, + u8 bssid_cam_idx) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + + if (!list_head) + return NULL; + + role = list_head->next; + for (; role->next != list_head->next; role = role->next) { + if (bssid_cam_idx == role->info.b_info.bssid_cam_idx && + role->info.a_info.valid) + return role; + } + + return NULL; +} + +u32 mac_get_macaddr(struct mac_ax_adapter *adapter, + struct mac_ax_macaddr *macaddr, + u8 role_idx) +{ + struct mac_role_tbl *role; + struct mac_role_tbl_head *list_head = adapter->role_tbl; + struct mac_ax_macaddr *macaddr_list; + u8 i; + u8 m_list_idx; + u32 ret; + + if (role_idx >= adapter->hw_info->macid_num) { + PLTFM_MSG_ERR("role_idx: %d\n", role_idx); + return MACFUNCINPUT; + } + if (!macaddr) { + PLTFM_MSG_ERR("mac_ax_macaddr is NULL\n"); + return MACFUNCINPUT; + } + + macaddr_list = (struct mac_ax_macaddr *) + PLTFM_MALLOC(sizeof(struct mac_ax_macaddr) * + adapter->hw_info->macid_num); + role = list_head->next; + for (m_list_idx = 0; role->next != list_head->next; role = role->next) { + if (!role->info.a_info.valid) + continue; + for (i = 0; i < m_list_idx; i++) { + if (!PLTFM_MEMCMP(macaddr_list + i, + role->info.a_info.sma, + sizeof(struct mac_ax_macaddr))) { + break; + } + } + if (i < m_list_idx) + continue; + PLTFM_MEMCPY(macaddr_list + m_list_idx, + role->info.a_info.sma, + sizeof(struct mac_ax_macaddr)); + if (m_list_idx == role_idx) { + PLTFM_MEMCPY(macaddr, + role->info.a_info.sma, + sizeof(struct mac_ax_macaddr)); + ret = MACSUCCESS; + goto fin; + } + m_list_idx++; + } + ret = MACNOITEM; +fin: + PLTFM_FREE(macaddr_list, sizeof(struct mac_ax_macaddr) * + adapter->hw_info->macid_num); + return ret; +} + +u32 mac_set_slot_time(struct mac_ax_adapter *adapter, enum mac_ax_slot_time st) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret = MACSUCCESS; + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + switch (st) { + case MAC_AX_SLOT_TIME_BAND0_9US: + ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG, + B_AX_SLOT_TIME_MSK << + B_AX_SLOT_TIME_SH, 9, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, R_AX_SLOTTIME_CFG, ret); + return ret; + } + break; + case MAC_AX_SLOT_TIME_BAND0_20US: + ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG, + B_AX_SLOT_TIME_MSK << + B_AX_SLOT_TIME_SH, 20, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", + __func__, R_AX_SLOTTIME_CFG, ret); + return ret; + } + break; + case MAC_AX_SLOT_TIME_BAND1_9US: + ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG_C1, + B_AX_SLOT_TIME_MSK << + B_AX_SLOT_TIME_SH, 9, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", __func__, + R_AX_SLOTTIME_CFG_C1, ret); + return ret; + } + break; + case MAC_AX_SLOT_TIME_BAND1_20US: + ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG_C1, + B_AX_SLOT_TIME_MSK << + B_AX_SLOT_TIME_SH, 20, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: write offload fail;" + "offset: %u, ret: %u\n", __func__, + R_AX_SLOTTIME_CFG_C1, ret); + return ret; + } + break; + } + + return ret; + } +#endif + switch (st) { + case MAC_AX_SLOT_TIME_BAND0_9US: + MAC_REG_W8(R_AX_SLOTTIME_CFG, 9); + break; + case MAC_AX_SLOT_TIME_BAND0_20US: + MAC_REG_W8(R_AX_SLOTTIME_CFG, 20); + break; + case MAC_AX_SLOT_TIME_BAND1_9US: + MAC_REG_W8(R_AX_SLOTTIME_CFG_C1, 9); + break; + case MAC_AX_SLOT_TIME_BAND1_20US: + MAC_REG_W8(R_AX_SLOTTIME_CFG_C1, 20); + break; + default: + ret = MACFUNCINPUT; + break; + } + + return ret; +} + +static u32 mac_h2c_join_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_joininfo *fwcmd_tbl; + struct mac_ax_sta_init_info sta; + u32 ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_WARN("%s fw not ready\n", __func__); + return MACFWNONRDY; + } + + // sta info + sta.macid = info->macid; + sta.opmode = info->opmode; + sta.band = info->band; + sta.wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) | + (info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0); + sta.trigger = info->trigger; + sta.is_hesta = info->is_hesta; + sta.dl_bw = info->dl_bw; + sta.tf_mac_padding = info->tf_mac_padding; + sta.dl_t_pe = info->dl_t_pe; + sta.port_id = info->port; + sta.net_type = info->net_type; + sta.wifi_role = info->wifi_role; + sta.self_role = info->self_role; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_joininfo)); + if (!buf) { + ret = MACNOBUF; + goto join_info_fail; + } + + fwcmd_tbl = (struct fwcmd_joininfo *)buf; + fwcmd_tbl->dword0 = + cpu_to_le32(SET_WORD(sta.macid, FWCMD_H2C_JOININFO_MACID) | + (sta.opmode ? FWCMD_H2C_JOININFO_OPMODE : 0) | + (sta.band ? FWCMD_H2C_JOININFO_BAND : 0) | + SET_WORD(sta.wmm, FWCMD_H2C_JOININFO_WMM) | + (sta.trigger ? FWCMD_H2C_JOININFO_TRIGGER : 0) | + (sta.is_hesta ? FWCMD_H2C_JOININFO_ISHESTA : 0) | + SET_WORD(sta.dl_bw, FWCMD_H2C_JOININFO_DL_BW) | + SET_WORD(sta.tf_mac_padding, + FWCMD_H2C_JOININFO_TF_MAC_PADDING) | + SET_WORD(sta.dl_t_pe, FWCMD_H2C_JOININFO_DL_T_PE) | + SET_WORD(sta.port_id, FWCMD_H2C_JOININFO_PORT_ID) | + SET_WORD(sta.net_type, FWCMD_H2C_JOININFO_NET_TYPE) | + SET_WORD(sta.wifi_role, FWCMD_H2C_JOININFO_WIFI_ROLE) | + SET_WORD(sta.self_role, FWCMD_H2C_JOININFO_SELF_ROLE)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_JOININFO, + 0, + 1); + + if (ret != MACSUCCESS) + goto join_info_fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto join_info_fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret != MACSUCCESS) + goto join_info_fail; + + h2cb_free(adapter, h2cb); + return MACSUCCESS; + +join_info_fail: + h2cb_free(adapter, h2cb); + return ret; +} + +static u32 mac_fw_role_maintain(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_fwrole_maintain *fwcmd_tbl; + struct mac_ax_fwrole_maintain fwrole_main; + u32 ret; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) { + PLTFM_MSG_WARN("%s fw not ready\n", __func__); + return MACFWNONRDY; + } + + fwrole_main.macid = info->macid; + fwrole_main.self_role = info->self_role; + fwrole_main.upd_mode = info->upd_mode; + fwrole_main.wifi_role = info->wifi_role; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_fwrole_maintain)); + if (!buf) { + ret = MACNOBUF; + goto role_maintain_fail; + } + + fwcmd_tbl = (struct fwcmd_fwrole_maintain *)buf; + fwcmd_tbl->dword0 = + cpu_to_le32(SET_WORD(fwrole_main.macid, + FWCMD_H2C_FWROLE_MAINTAIN_MACID) | + SET_WORD(fwrole_main.self_role, + FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE) | + SET_WORD(fwrole_main.upd_mode, + FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE) | + SET_WORD(fwrole_main.wifi_role, + FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_FWROLE_MAINTAIN, + 0, + 1); + + if (ret != MACSUCCESS) + goto role_maintain_fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto role_maintain_fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret != MACSUCCESS) + goto role_maintain_fail; + + h2cb_free(adapter, h2cb); + return MACSUCCESS; + +role_maintain_fail: + h2cb_free(adapter, h2cb); + return ret; +} + +u32 mac_role_sync(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info) +{ + struct mac_role_tbl *role; + u32 ret = MACSUCCESS; + + role = mac_role_srch(adapter, info->macid); + if (!role) { + PLTFM_MSG_ERR("role search failed\n"); + return MACNOITEM; + } + + ret = mac_fw_role_maintain(adapter, info); + if (ret) { + if (ret == MACFWNONRDY) + PLTFM_MSG_WARN("skip fw role sync since fw not ready\n"); + else + PLTFM_MSG_ERR("mac_fw_role_maintain failed:%d\n", ret); + return ret; + } + if (info->self_role == MAC_AX_SELF_ROLE_AP) { + ret = mac_h2c_join_info(adapter, info); + if (ret) { + if (ret == MACFWNONRDY) + PLTFM_MSG_WARN("skip join info\n"); + else + PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret); + } + } + return ret; +} diff --git a/phl/hal_g6/mac/mac_ax/role.h b/phl/hal_g6/mac/mac_ax/role.h new file mode 100644 index 0000000..cef20ad --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/role.h @@ -0,0 +1,351 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_ROLE_H_ +#define _MAC_AX_ROLE_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "addr_cam.h" +#include "security_cam.h" +#include "hw.h" +#include "trxcfg.h" + +#define CCTL_NTX_PATH_EN 3 +#define CCTL_PATH_MAP_B 1 +#define CCTL_PATH_MAP_C 2 +#define CCTL_PATH_MAP_D 3 +#define CCTRL_NC 1 +#define CCTRL_NR 1 +#define CCTRL_CB 1 +#define CCTRL_CSI_PARA_EN 1 +#define CCTRL_CSI_PARA_EN_MSK 1 + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief role_tbl_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 role_tbl_init(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief role_tbl_exit + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 role_tbl_exit(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief role_info_valid + * + * @param *adapter + * @param *info + * @param change_role + * @return Please Place Description here. + * @retval u32 + */ +u32 role_info_valid(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + enum mac_ax_role_opmode op); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_add_role + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_add_role(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_remove_role + * + * @param *adapter + * @param macid + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_remove_role(struct mac_ax_adapter *adapter, u8 macid); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_remove_role_by_band + * + * @param *adapter + * @param band + * @param sw + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_remove_role_by_band(struct mac_ax_adapter *adapter, u8 band, u8 sw); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_change_role + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_change_role(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_role_srch + * + * @param *adapter + * @param macid + * @return Please Place Description here. + * @retval mac_role_tbl + */ +struct mac_role_tbl *mac_role_srch(struct mac_ax_adapter *adapter, + u8 macid); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_role_srch_by_addr_cam + * + * @param *adapter + * @param addr_cam_idx + * @return Please Place Description here. + * @retval mac_role_tbl + */ +struct mac_role_tbl *mac_role_srch_by_addr_cam(struct mac_ax_adapter *adapter, + u16 addr_cam_idx); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_role_srch_by_bssid + * + * @param *adapter + * @param bssid_cam_idx + * @return Please Place Description here. + * @retval mac_role_tbl + */ +struct mac_role_tbl *mac_role_srch_by_bssid(struct mac_ax_adapter *adapter, + u8 bssid_cam_idx); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_get_macaddr + * + * @param *adapter + * @param *macaddr + * @param role_idx + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_macaddr(struct mac_ax_adapter *adapter, + struct mac_ax_macaddr *macaddr, + u8 role_idx); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_set_slot_time + * + * @param *adapter + * @param mac_ax_slot_time + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_slot_time(struct mac_ax_adapter *adapter, enum mac_ax_slot_time); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_h2c_join_info + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ + +static u32 mac_h2c_join_info(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ + +/** + * @brief mac_fw_role_maintain + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +static u32 mac_fw_role_maintain(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup Role_Related + * @{ + */ +/** + * @brief mac_role_sync + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_role_sync(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info); +/** + * @} + * @} + */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/rrsr.c b/phl/hal_g6/mac/mac_ax/rrsr.c new file mode 100644 index 0000000..1d4f904 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rrsr.c @@ -0,0 +1,133 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "rrsr.h" + +u32 mac_get_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_rrsr_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, rrsr_ctl_0, rrsr_ctl_1; + + val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band); + return val32; + } + + rrsr_ctl_0 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ? + R_AX_TRXPTCL_RRSR_CTL_0_C1 : R_AX_TRXPTCL_RRSR_CTL_0); + cfg->rrsr_rate_en = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RATE_EN); + cfg->doppler_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DOPPLEB_AX_EN) != 0); + cfg->dcm_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DCM_EN) != 0); + cfg->cck_cfg = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RRSB_AX_CCK); + cfg->rsc = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RSC); + cfg->ref_rate_sel = ((rrsr_ctl_0 & B_AX_WMAC_RESP_REF_RATE_SEL) != 0); + cfg->ref_rate = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_REF_RATE); + + rrsr_ctl_1 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ? + R_AX_TRXPTCL_RRSR_CTL_1_C1 : R_AX_TRXPTCL_RRSR_CTL_1_C1); + cfg->ofdm_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_OFDM); + cfg->ht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HT); + cfg->vht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_VHT); + cfg->he_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HE); + + return MACSUCCESS; +} + +u32 mac_set_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_rrsr_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, rrsr_ctl_0, rrsr_ctl_1; + + val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band); + return val32; + } + + rrsr_ctl_0 = SET_WORD(cfg->rrsr_rate_en, B_AX_WMAC_RESP_RATE_EN) | + (cfg->doppler_en ? B_AX_WMAC_RESP_DOPPLEB_AX_EN : 0) | + (cfg->dcm_en ? B_AX_WMAC_RESP_DCM_EN : 0) | + SET_WORD(cfg->cck_cfg, B_AX_WMAC_RRSB_AX_CCK) | + SET_WORD(cfg->rsc, B_AX_WMAC_RESP_RSC) | + (cfg->ref_rate_sel ? B_AX_WMAC_RESP_REF_RATE_SEL : 0) | + SET_WORD(cfg->ref_rate, B_AX_WMAC_RESP_REF_RATE); + + rrsr_ctl_1 = SET_WORD(cfg->ofdm_cfg, B_AX_WMAC_RRSR_OFDM) | + SET_WORD(cfg->ht_cfg, B_AX_WMAC_RRSR_HT) | + SET_WORD(cfg->vht_cfg, B_AX_WMAC_RRSR_VHT) | + SET_WORD(cfg->he_cfg, B_AX_WMAC_RRSR_HE); + + // add fw offload later + if (cfg->band == MAC_AX_BAND_0) { + MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0, rrsr_ctl_0); + MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1, rrsr_ctl_1); + } else { + MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0_C1, rrsr_ctl_0); + MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1_C1, rrsr_ctl_1); + } + + return MACSUCCESS; +} + +u32 mac_get_cts_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_cts_rrsr_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band); + return val32; + } + + val32 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ? + R_AX_TRXPTCL_CTS_RRSR_C1 : R_AX_TRXPTCL_CTS_RRSR); + cfg->cts_rrsr_rsc = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_RSC); + cfg->cts_rrsr_opt = ((val32 & B_AX_WMAC_CTS_RESP_OPT) != 0); + cfg->cts_rrsr_cck_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_CCK); + cfg->cts_rrsr_ofdm_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_OFDM); + + return MACSUCCESS; +} + +u32 mac_set_cts_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_cts_rrsr_cfg *cfg) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band); + return val32; + } + + val32 = SET_WORD(cfg->cts_rrsr_rsc, B_AX_WMAC_CTS_RRSR_RSC) | + (cfg->cts_rrsr_opt ? B_AX_WMAC_CTS_RESP_OPT : 0) | + SET_WORD(cfg->cts_rrsr_cck_cfg, B_AX_WMAC_CTS_RRSR_CCK) | + SET_WORD(cfg->cts_rrsr_ofdm_cfg, B_AX_WMAC_CTS_RRSR_OFDM); + + // add fw offload later + if (cfg->band == MAC_AX_BAND_0) + MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR, val32); + else + MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR_C1, val32); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/rrsr.h b/phl/hal_g6/mac/mac_ax/rrsr.h new file mode 100644 index 0000000..1b5f6c3 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rrsr.h @@ -0,0 +1,107 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_RRSR_H_ +#define _MAC_AX_RRSR_H_ +#include "../type.h" + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RRSR + * @{ + */ +/** + * @brief mac_get_rrsr_cfg + * + * @param *adapter + * @param *mac_ax_rrsr_cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_rrsr_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RRSR + * @{ + */ +/** + * @brief mac_set_rrsr_cfg + * + * @param *adapter + * @param *mac_ax_rrsr_cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_rrsr_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RRSR + * @{ + */ +/** + * @brief mac_get_rrsr_cfg + * + * @param *adapter + * @param mac_ax_cts_rrsr_cfg + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_cts_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_cts_rrsr_cfg *cfg); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RRSR + * @{ + */ +/** + * @brief mac_set_rrsr_cfg + * + * @param *adapter + * @param mac_ax_cts_rrsr_cfg + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_cts_rrsr_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_cts_rrsr_cfg *cfg); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/rx_filter.c b/phl/hal_g6/mac/mac_ax/rx_filter.c new file mode 100644 index 0000000..f5b0bdb --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rx_filter.c @@ -0,0 +1,429 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "rx_filter.h" + +/* control frames: drop, mgnt frames: to host, data frame: to host */ +static enum mac_ax_fwd_target trxcfg_rx_fltr_mgnt_frame = MAC_AX_FWD_TO_HOST; +static enum mac_ax_fwd_target trxcfg_rx_fltr_ctrl_frame = MAC_AX_FWD_TO_HOST; +static enum mac_ax_fwd_target trxcfg_rx_fltr_data_frame = MAC_AX_FWD_TO_HOST; + +static struct mac_ax_rx_fltr_ctrl_t rx_fltr_init_opt = { + 1, /* sniffer_mode */ + 1, /* acpt_a1_match_pkt */ + 1, /* acpt_bc_pkt */ + 1, /* acpt_mc_pkt */ + 1, /* uc_pkt_chk_cam_match */ + 1, /* bc_pkt_chk_cam_match */ + 0, /* mc_pkt_white_lst_mode */ + 0, /* bcn_chk_en */ + 0, /* bcn_chk_rule */ + 0, /* acpt_pwr_mngt_pkt */ + 0, /* acpt_crc32_err_pkt */ + 0, /* acpt_unsupport_pkt */ + 0, /* acpt_mac_hdr_content_err_pkt */ + 0, /* acpt_ftm_req_pkt */ + 0, /* pkt_len_fltr */ + 0, /* unsp_pkt_target */ + 3, /* uid_fltr */ + 1, /* cck_crc_chk_enable */ + 1, /* cck_sig_chk_enable */ + 1, /* lsig_parity_chk_enable */ + 1, /* siga_crc_chk_enable */ + 1, /* vht_su_sigb_crc_chk_enable */ + 1, /* vht_mu_sigb_crc_chk_enable */ + 1, /* he_sigb_crc_chk_enable */ + 0, /* min_len_chk_disable */ +}; + +u32 rx_fltr_init(struct mac_ax_adapter *adapter, enum mac_ax_band band) +{ + u32 ret; + struct mac_ax_ops *mac_ax_ops = adapter_to_mac_ops(adapter); + struct mac_ax_rx_fltr_ctrl_t opt_msk = { + 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x1, 0x1, 0x1, + 0x1, 0x1, 0x3F, 0x3, 0x3, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1 + }; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter, + MAC_AX_PKT_MGNT, + trxcfg_rx_fltr_mgnt_frame, + band); + if (ret != MACSUCCESS) + return ret; + ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter, + MAC_AX_PKT_CTRL, + trxcfg_rx_fltr_ctrl_frame, + band); + if (ret != MACSUCCESS) + return ret; + ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter, + MAC_AX_PKT_DATA, + trxcfg_rx_fltr_data_frame, + band); + if (ret != MACSUCCESS) + return ret; + ret = mac_ax_ops->set_rx_fltr_opt(adapter, + &rx_fltr_init_opt, + &opt_msk, + band); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +static void rx_fltr_opt_2_uint(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt, + u32 *mac_fltr_value, + u16 *plcp_fltr_value) +{ + u32 val32 = 0x0; + u8 val16 = 0x0; + + val32 = + ((fltr_opt->sniffer_mode) ? + B_AX_SNIFFER_MODE : 0) | + ((fltr_opt->acpt_a1_match_pkt) ? + B_AX_A_A1_MATCH : 0) | + ((fltr_opt->acpt_bc_pkt) ? + B_AX_A_BC : 0) | + ((fltr_opt->acpt_mc_pkt) ? + B_AX_A_MC : 0) | + ((fltr_opt->uc_pkt_chk_cam_match) ? + B_AX_A_UC_CAM_MATCH : 0) | + ((fltr_opt->bc_pkt_chk_cam_match) ? + B_AX_A_BC_CAM_MATCH : 0) | + ((fltr_opt->mc_pkt_white_lst_mode) ? + B_AX_A_MC_LIST_CAM_MATCH : 0) | + ((fltr_opt->bcn_chk_en) ? + B_AX_A_BCN_CHK_EN : 0) | + ((fltr_opt->acpt_pwr_mngt_pkt) ? + B_AX_A_PWR_MGNT : 0) | + ((fltr_opt->acpt_crc32_err_pkt) ? + B_AX_A_CRC32_ERR : 0) | + ((fltr_opt->acpt_mac_hdr_content_err_pkt) ? + B_AX_A_ERR_PKT : 0) | + ((fltr_opt->acpt_unsupport_pkt) ? + B_AX_A_UNSUP_PKT : 0) | + ((fltr_opt->acpt_ftm_req_pkt) ? + B_AX_A_FTM_REQ : 0) | + SET_WORD(fltr_opt->bcn_chk_rule, + RX_FLTR_BCN_CHK_RULE) | + SET_WORD(fltr_opt->pkt_len_fltr, + RX_FLTR_PKT_LEN_FLTR) | + SET_WORD(fltr_opt->unsp_pkt_target, + RX_FLTR_UNSUPPORT_PKT_FLTR) | + SET_WORD(fltr_opt->uid_fltr, + RX_FLTR_UID_FLTR); + + *mac_fltr_value = val32; + + val16 = + ((fltr_opt->cck_crc_chk_enable) ? + B_AX_CCK_CRC_CHK : 0) | + ((fltr_opt->cck_sig_chk_enable) ? + B_AX_CCK_SIG_CHK : 0) | + ((fltr_opt->lsig_parity_chk_enable) ? + B_AX_LSIG_PARITY_CHK : 0) | + ((fltr_opt->siga_crc_chk_enable) ? + B_AX_SIGA_CRC_CHK : 0) | + ((fltr_opt->vht_su_sigb_crc_chk_enable) ? + B_AX_VHT_SU_SIGB_CRC_CHK : 0) | + ((fltr_opt->vht_mu_sigb_crc_chk_enable) ? + B_AX_VHT_MU_SIGB_CRC_CHK : 0) | + ((fltr_opt->he_sigb_crc_chk_enable) ? + B_AX_HE_SIGB_CRC_CHK : 0) | + ((fltr_opt->min_len_chk_disable) ? + B_AX_DIS_CHK_MIN_LEN : 0); + + *plcp_fltr_value = val16; +} + +u32 mac_get_rx_fltr_opt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + if (!fltr_opt) { + PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__); + return MACNPTR; + } + + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_RX_FLTR_OPT_C1 : R_AX_RX_FLTR_OPT); + fltr_opt->sniffer_mode = ((val32 & B_AX_SNIFFER_MODE) != 0); + fltr_opt->acpt_a1_match_pkt = ((val32 & B_AX_A_A1_MATCH) != 0); + fltr_opt->acpt_bc_pkt = ((val32 & B_AX_A_BC) != 0); + fltr_opt->acpt_mc_pkt = ((val32 & B_AX_A_MC) != 0); + fltr_opt->uc_pkt_chk_cam_match = ((val32 & B_AX_A_UC_CAM_MATCH) != 0); + fltr_opt->bc_pkt_chk_cam_match = ((val32 & B_AX_A_BC_CAM_MATCH) != 0); + fltr_opt->mc_pkt_white_lst_mode = ((val32 & + B_AX_A_MC_LIST_CAM_MATCH) != 0); + fltr_opt->bcn_chk_en = ((val32 & B_AX_A_BCN_CHK_EN) != 0); + fltr_opt->acpt_pwr_mngt_pkt = ((val32 & B_AX_A_PWR_MGNT) != 0); + fltr_opt->acpt_crc32_err_pkt = ((val32 & B_AX_A_CRC32_ERR) != 0); + fltr_opt->acpt_mac_hdr_content_err_pkt = ((val32 & + B_AX_A_ERR_PKT) != 0); + fltr_opt->acpt_unsupport_pkt = ((val32 & B_AX_A_UNSUP_PKT) != 0); + fltr_opt->acpt_ftm_req_pkt = ((val32 & B_AX_A_FTM_REQ) != 0); + fltr_opt->bcn_chk_rule = GET_FIELD(val32, RX_FLTR_BCN_CHK_RULE); + fltr_opt->pkt_len_fltr = GET_FIELD(val32, RX_FLTR_PKT_LEN_FLTR); + fltr_opt->unsp_pkt_target = GET_FIELD(val32, + RX_FLTR_UNSUPPORT_PKT_FLTR); + fltr_opt->uid_fltr = GET_FIELD(val32, RX_FLTR_UID_FLTR); + + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_PLCP_HDR_FLTR_C1 : R_AX_PLCP_HDR_FLTR); + fltr_opt->cck_crc_chk_enable = ((val32 & B_AX_CCK_CRC_CHK) != 0); + fltr_opt->cck_sig_chk_enable = ((val32 & B_AX_CCK_SIG_CHK) != 0); + fltr_opt->lsig_parity_chk_enable = ((val32 & + B_AX_LSIG_PARITY_CHK) != 0); + fltr_opt->siga_crc_chk_enable = ((val32 & B_AX_SIGA_CRC_CHK) != 0); + fltr_opt->vht_su_sigb_crc_chk_enable = ((val32 & + B_AX_VHT_SU_SIGB_CRC_CHK) + != 0); + fltr_opt->vht_mu_sigb_crc_chk_enable = ((val32 & + B_AX_VHT_MU_SIGB_CRC_CHK) + != 0); + fltr_opt->he_sigb_crc_chk_enable = ((val32 & B_AX_HE_SIGB_CRC_CHK) + != 0); + fltr_opt->min_len_chk_disable = ((val32 & B_AX_DIS_CHK_MIN_LEN) + != 0); + return MACSUCCESS; +} + +u32 mac_set_rx_fltr_opt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt_msk, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_rx_fltr_ctrl_t opt = {0}; + u32 mac_opt; + u16 plcp_opt; + u32 mac_opt_msk; + u16 plcp_opt_msk; + u32 mac_opt_value; + u16 plcp_opt_value; + u32 ret = MACSUCCESS; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return ret; + } + + if (!fltr_opt || !fltr_opt_msk) { + PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__); + return MACNPTR; + } + + mac_get_rx_fltr_opt(adapter, &opt, band); + + rx_fltr_opt_2_uint(adapter, + fltr_opt, + &mac_opt, + &plcp_opt); + + rx_fltr_opt_2_uint(adapter, + fltr_opt_msk, + &mac_opt_msk, + &plcp_opt_msk); + + rx_fltr_opt_2_uint(adapter, + &opt, + &mac_opt_value, + &plcp_opt_value); + + mac_opt_value = (mac_opt & mac_opt_msk) | + (~(~mac_opt & mac_opt_msk) & mac_opt_value); + + plcp_opt_value = (plcp_opt & plcp_opt_msk) | + (~(~plcp_opt & plcp_opt_msk) & plcp_opt_value); + + // add fw offload later + if (band == MAC_AX_BAND_0) { + MAC_REG_W32(R_AX_RX_FLTR_OPT, mac_opt_value); + MAC_REG_W16(R_AX_PLCP_HDR_FLTR, plcp_opt_value); + } else { + MAC_REG_W32(R_AX_RX_FLTR_OPT_C1, mac_opt_value); + MAC_REG_W16(R_AX_PLCP_HDR_FLTR_C1, plcp_opt_value); + } + + return ret; +} + +u32 mac_set_typ_fltr_opt(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + switch (fwd_target) { + case MAC_AX_FWD_DONT_CARE: + val32 = RX_FLTR_FRAME_DROP; + break; + case MAC_AX_FWD_TO_HOST: + val32 = RX_FLTR_FRAME_TO_HOST; + break; + case MAC_AX_FWD_TO_WLAN_CPU: + val32 = RX_FLTR_FRAME_TO_WLCPU; + break; + default: + PLTFM_MSG_ERR("[ERR]%s fwd target err\n", __func__); + return MACNOITEM; + } + + switch (type) { + case MAC_AX_PKT_MGNT: + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR, val32); + break; + case MAC_AX_PKT_CTRL: + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR, val32); + break; + case MAC_AX_PKT_DATA: + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR, val32); + break; + default: + PLTFM_MSG_ERR("[ERR]%s type err\n", __func__); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_set_typsbtyp_fltr_opt(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + u8 subtype, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + if (fwd_target != MAC_AX_FWD_DONT_CARE && + fwd_target != MAC_AX_FWD_TO_HOST && + fwd_target != MAC_AX_FWD_TO_WLAN_CPU) { + PLTFM_MSG_ERR("[ERR]%s fwd target err\n", __func__); + return MACNOITEM; + } + + switch (type) { + case MAC_AX_PKT_MGNT: + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR); + val32 = SET_CLR_WOR2(val32, fwd_target, + ((subtype & 0xf) * 2), 0x3); + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR, val32); + break; + case MAC_AX_PKT_CTRL: + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR); + val32 = SET_CLR_WOR2(val32, fwd_target, + ((subtype & 0xf) * 2), 0x3); + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR, val32); + break; + case MAC_AX_PKT_DATA: + val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? + R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR); + val32 = SET_CLR_WOR2(val32, fwd_target, + ((subtype & 0xf) * 2), 0x3); + MAC_REG_W32((band == MAC_AX_BAND_1) ? + R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR, val32); + break; + default: + PLTFM_MSG_ERR("[ERR]%s type err\n", __func__); + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_set_typsbtyp_fltr_detail(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + struct mac_ax_rx_fltr_elem *elem, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 cmp_bit = 1; + u16 reg; + u8 idx; + + val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (val32 != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band); + return val32; + } + + switch (type) { + case MAC_AX_PKT_CTRL: + reg = (band == MAC_AX_BAND_0) ? R_AX_CTRL_FLTR : R_AX_CTRL_FLTR_C1; + break; + case MAC_AX_PKT_MGNT: + reg = (band == MAC_AX_BAND_0) ? R_AX_MGNT_FLTR : R_AX_MGNT_FLTR_C1; + break; + case MAC_AX_PKT_DATA: + reg = (band == MAC_AX_BAND_0) ? R_AX_DATA_FLTR : R_AX_DATA_FLTR_C1; + break; + default: + PLTFM_MSG_ERR("[ERR]%s type err\n", __func__); + return MACNOITEM; + } + + val32 = MAC_REG_R32(reg); + + for (idx = 0; idx < RX_FLTR_SUBTYPE_NUM; idx++) { + if ((elem->subtype_mask & cmp_bit) != 0) + val32 = SET_CLR_WOR2(val32, elem->target_arr[idx], + ENTRY_SH(idx), ENTRY_MSK); + cmp_bit = cmp_bit << ENTRY_IDX; + } + MAC_REG_W32(reg, val32); + + return MACSUCCESS; +} \ No newline at end of file diff --git a/phl/hal_g6/mac/mac_ax/rx_filter.h b/phl/hal_g6/mac/mac_ax/rx_filter.h new file mode 100644 index 0000000..e70260f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rx_filter.h @@ -0,0 +1,169 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_RX_FILTER_H_ +#define _MAC_AX_RX_FILTER_H_ +#include "trxcfg.h" +#include "../type.h" + +#define RX_FLTR_BCN_CHK_RULE_SH 8 +#define RX_FLTR_BCN_CHK_RULE_MSK 0x3 +#define RX_FLTR_PKT_LEN_FLTR_SH 16 +#define RX_FLTR_PKT_LEN_FLTR_MSK 0x7F +#define RX_FLTR_UNSUPPORT_PKT_FLTR_SH 22 +#define RX_FLTR_UNSUPPORT_PKT_FLTR_MSK 0x3 +#define RX_FLTR_UID_FLTR_SH 24 +#define RX_FLTR_UID_FLTR_MSK 0xFF + +#define RX_FLTR_FRAME_DROP 0x00000000 +#define RX_FLTR_FRAME_TO_HOST 0x55555555 +#define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA + +#define RX_FLTR_SUBTYPE_NUM 16 +#define ENTRY_MSK 0x3 +#define ENTRY_SH(_idx) (_idx * 2) +#define ENTRY_IDX 1 + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RX_Filter + * @{ + */ + +/** + * @brief mac_get_rx_fltr_opt + * + * @param *adapter + * @param *fltr_opt + * @param band + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_rx_fltr_opt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt, + enum mac_ax_band band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RX_Filter + * @{ + */ + +/** + * @brief mac_set_rx_fltr_opt + * + * @param *adapter + * @param *fltr_opt + * @param *fltr_opt_msk + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_rx_fltr_opt(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt, + struct mac_ax_rx_fltr_ctrl_t *fltr_opt_msk, + enum mac_ax_band band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RX_Filter + * @{ + */ + +/** + * @brief mac_set_typ_fltr_opt + * + * @param *adapter + * @param type + * @param fwd_target + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_typ_fltr_opt(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RX_Filter + * @{ + */ + +/** + * @brief mac_set_typsbtyp_fltr_opt + * + * @param *adapter + * @param type + * @param subtype + * @param fwd_target + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_typsbtyp_fltr_opt(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + u8 subtype, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band); +/** + * @} + * @} + */ + +u32 rx_fltr_init(struct mac_ax_adapter *adapter, + enum mac_ax_band band); + +/** + * @brief mac_set_typ_fltr_opt + * + * @param *adapter + * @param type + * @param fwd_target + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_typsbtyp_fltr_detail(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + struct mac_ax_rx_fltr_elem *elem, + enum mac_ax_band band); +/** + * @} + * @} + */ +#endif diff --git a/phl/hal_g6/mac/mac_ax/rx_forwarding.c b/phl/hal_g6/mac/mac_ax/rx_forwarding.c new file mode 100644 index 0000000..f3b27fc --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rx_forwarding.c @@ -0,0 +1,446 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "rx_forwarding.h" + +#if MAC_AX_FW_REG_OFLD +u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_rx_fwd *rx_fwd; + struct mac_ax_af_ud_ctrl_t *af_ud; + struct mac_ax_pm_cam_ctrl_t *pm_cam; + + if (!rf_ctrl_p) + return MACNPTR; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_rx_fwd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + rx_fwd = (struct fwcmd_rx_fwd *)buf; + rx_fwd->dword0 = + cpu_to_le32(SET_WORD(rf_ctrl_p->type, FWCMD_H2C_RX_FWD_TYPE) | + SET_WORD(rf_ctrl_p->frame, FWCMD_H2C_RX_FWD_FRAME) | + SET_WORD(rf_ctrl_p->fwd_tg, FWCMD_H2C_RX_FWD_FWD_TG)); + + af_ud = &rf_ctrl_p->af_ud_ctrl; + rx_fwd->dword1 = + cpu_to_le32(SET_WORD(af_ud->index, FWCMD_H2C_RX_FWD_AF_UD_INDEX) | + SET_WORD(af_ud->fwd_tg, FWCMD_H2C_RX_FWD_AF_UD_FWD_TG) | + SET_WORD(af_ud->category, FWCMD_H2C_RX_FWD_AF_UD_CATEGORY) | + SET_WORD(af_ud->action_field, + FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD)); + + pm_cam = &rf_ctrl_p->pm_cam_ctrl; + rx_fwd->dword2 = + cpu_to_le32((pm_cam->valid ? FWCMD_H2C_RX_FWD_PM_CAM_VALID : 0) | + SET_WORD(pm_cam->type, FWCMD_H2C_RX_FWD_PM_CAM_TYPE) | + SET_WORD(pm_cam->subtype, FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE) | + (pm_cam->skip_mac_iv_hdr ? + FWCMD_H2C_RX_FWD_PM_CAM_SKIP_MAC_IV_HDR : 0) | + SET_WORD(pm_cam->target_ind, + FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND) | + SET_WORD(pm_cam->entry_index, + FWCMD_H2C_RX_FWD_PM_CAM_INDEX) | + SET_WORD(pm_cam->crc16, FWCMD_H2C_RX_FWD_PM_CAM_CRC16)); + + rx_fwd->dword3 = + cpu_to_le32(SET_WORD(pm_cam->pld_mask0, + FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0)); + + rx_fwd->dword4 = + cpu_to_le32(SET_WORD(pm_cam->pld_mask1, + FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1)); + + rx_fwd->dword5 = + cpu_to_le32(SET_WORD(pm_cam->pld_mask2, + FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2)); + + rx_fwd->dword6 = + cpu_to_le32(SET_WORD(pm_cam->pld_mask3, + FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3)); + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_RX_FWD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + } else { + ret = MACFWNONRDY; + goto fail; + } + + ret = MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +#else +static inline u32 af_fwd_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_action_frame frame, + enum mac_ax_fwd_target fwd_tg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_ACTION_FWD0); + switch (frame) { + case MAC_AX_AF_CSA: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA); + break; + case MAC_AX_AF_ADDTS_REQ: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ); + break; + case MAC_AX_AF_ADDTS_RES: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES); + break; + case MAC_AX_AF_DELTS: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS); + break; + case MAC_AX_AF_ADDBA_REQ: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ); + break; + case MAC_AX_AF_ADDBA_RES: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES); + break; + case MAC_AX_AF_DELBA: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA); + break; + case MAC_AX_AF_NCW: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW); + break; + case MAC_AX_AF_GID_MGNT: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_GID_MGNT); + break; + case MAC_AX_AF_OP_MODE: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_OP_MODE); + break; + case MAC_AX_AF_CSI: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSI); + break; + case MAC_AX_AF_HT_CBFM: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_HT_CBFM); + break; + case MAC_AX_AF_VHT_CBFM: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_VHT_CBFM); + break; + default: + return MACNOITEM; + } + MAC_REG_W32(R_AX_ACTION_FWD0, val32); + return MACSUCCESS; +} + +static inline u32 af_ud_fwd_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_af_ud_ctrl_t *af_ud_ctrl_p) +{ + u32 val32; + u16 val16; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_ACTION_FWD1); + switch (af_ud_ctrl_p->index) { + case MAC_AX_AF_UD_0: + val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL0); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category, + B_AX_FWD_ACTN_CAT0); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field, + B_AX_FWD_ACTN_ACTN0); + MAC_REG_W16(R_AX_ACTION_FWD_CTRL0, val16); + val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg, + B_AX_FWD_ACTN_CTRL0); + break; + case MAC_AX_AF_UD_1: + val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL1); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category, + B_AX_FWD_ACTN_CAT1); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field, + B_AX_FWD_ACTN_ACTN1); + MAC_REG_W16(R_AX_ACTION_FWD_CTRL1, val16); + val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg, + B_AX_FWD_ACTN_CTRL1); + break; + case MAC_AX_AF_UD_2: + val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL2); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category, + B_AX_FWD_ACTN_CAT2); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field, + B_AX_FWD_ACTN_ACTN2); + MAC_REG_W16(R_AX_ACTION_FWD_CTRL2, val16); + val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg, + B_AX_FWD_ACTN_CTRL2); + break; + case MAC_AX_AF_UD_3: + val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL3); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category, + B_AX_FWD_ACTN_CAT3); + val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field, + B_AX_FWD_ACTN_ACTN3); + MAC_REG_W16(R_AX_ACTION_FWD_CTRL3, val16); + val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg, + B_AX_FWD_ACTN_CTRL3); + break; + default: + return MACNOITEM; + } + MAC_REG_W32(R_AX_ACTION_FWD1, val32); + return MACSUCCESS; +} + +static inline u32 tf_fwd_cfg(struct mac_ax_adapter *adapter, + enum mac_ax_trigger_frame frame, + enum mac_ax_fwd_target fwd_tg) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_TF_FWD); + switch (frame) { + case MAC_AX_TF_BT: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF0); + break; + case MAC_AX_TF_BFRP: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF1); + break; + case MAC_AX_TF_MU_BAR: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF2); + break; + case MAC_AX_TF_MU_RTS: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF3); + break; + case MAC_AX_TF_BSRP: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF4); + break; + case MAC_AX_TF_GCR_MU_BAR: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF5); + break; + case MAC_AX_TF_BQRP: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF6); + break; + case MAC_AX_TF_NFRP: + val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF7); + break; + default: + return MACNOITEM; + } + MAC_REG_W32(R_AX_TF_FWD, val32); + return MACSUCCESS; +} + +static inline u32 pm_cam_access_polling(struct mac_ax_adapter *adapter) +{ + u32 cnt = PM_CAM_WAIT_CNT; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + while (cnt--) { + if (!(MAC_REG_R32(R_AX_PLD_CAM_ACCESS) & B_AX_PLD_CAM_POLL)) + break; + PLTFM_DELAY_US(PM_CAM_WAIT_US); + } + + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]PM CAM access timeout\n"); + return MACPOLLTO; + } + return MACSUCCESS; +} + +static inline u32 pm_cam_indirect_r(struct mac_ax_adapter *adapter, + u32 offset) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = 0; + val32 = SET_CLR_WORD(val32, offset, B_AX_PLD_CAM_OFFSET); + val32 &= ~B_AX_PLD_CAM_CLR; + val32 &= ~B_AX_PLD_CAM_RW; + val32 |= B_AX_PLD_CAM_POLL; + MAC_REG_W32(R_AX_PLD_CAM_ACCESS, val32); + + if (pm_cam_access_polling(adapter)) { + PLTFM_MSG_ERR("[ERR]PM CAM read timeout\n"); + return MACSUCCESS; + } + + return MAC_REG_R32(R_AX_PLD_CAM_RDATA); +} + +static inline void pm_cam_indirect_w(struct mac_ax_adapter *adapter, + u32 offset, u32 data) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_PLD_CAM_WDATA, data); + + val32 = 0; + val32 = SET_CLR_WORD(val32, offset, B_AX_PLD_CAM_OFFSET); + val32 &= ~B_AX_PLD_CAM_CLR; + val32 |= B_AX_PLD_CAM_RW; + val32 |= B_AX_PLD_CAM_POLL; + MAC_REG_W32(R_AX_PLD_CAM_ACCESS, val32); + + if (pm_cam_access_polling(adapter)) + PLTFM_MSG_ERR("[ERR]PM CAM write timeout\n"); +} + +static inline u32 pm_cam_fwd_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_pm_cam_ctrl_t *pm_cam_ctrl_p) +{ + u32 val32, offset; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) { + PLTFM_MSG_ERR("[ERR]%s PM_CAM API is removed in 52C & 92XB.\n" + , __func__); + return MACSUCCESS; + } + + if (!pm_cam_ctrl_p) + return MACNPTR; + + if (pm_cam_ctrl_p->entry_index >= MAC_AX_PM_CAM_ENTRY_NUM_MAX) + return MACNOITEM; + + // Set as indirect access and enable PM CAM + val32 = MAC_REG_R32(R_AX_PLD_CAM_CTRL); + val32 = SET_CLR_WORD(val32, 0xf, B_AX_PLD_CAM_RANGE); + val32 |= B_AX_PLD_CAM_ACC; + val32 |= B_AX_PLD_CAM_EN; + MAC_REG_W32(R_AX_PLD_CAM_CTRL, val32); + + // offset unit: 4 bytes + offset = (pm_cam_ctrl_p->entry_index * + MAC_AX_PM_CAM_ENTRY_CONTENT_SIZE) / 4; + + val32 = 0; + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask0, PM_CAM_PLD_MASK0); + pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW1, val32); + if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW1)) { + PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 1\n"); + return MACRFPMCAM; + } + + val32 = 0; + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask1, PM_CAM_PLD_MASK1); + pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW2, val32); + if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW2)) { + PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 2\n"); + return MACRFPMCAM; + } + + val32 = 0; + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask2, PM_CAM_PLD_MASK2); + pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW3, val32); + if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW3)) { + PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 3\n"); + return MACRFPMCAM; + } + + val32 = 0; + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask3, PM_CAM_PLD_MASK3); + pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW4, val32); + if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW4)) { + PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 4\n"); + return MACRFPMCAM; + } + + // PMCAM is not trigger-type reg! + val32 = 0; + val32 |= (pm_cam_ctrl_p->valid ? PM_CAM_VALID : 0); + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->type, PM_CAM_TYPE); + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->subtype, PM_CAM_SUBTYPE); + val32 |= (pm_cam_ctrl_p->skip_mac_iv_hdr ? PM_CAM_SKIP_MAC_IV_HDR : 0); + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->target_ind, + PM_CAM_TARGET_IND); + val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->crc16, PM_CAM_CRC16); + pm_cam_indirect_w(adapter, offset, val32); + if (val32 != pm_cam_indirect_r(adapter, offset)) { + PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 5, %x, %x\n", + val32, pm_cam_indirect_r(adapter, offset)); + return MACRFPMCAM; + } + + return MACSUCCESS; +} + +u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p) +{ + u32 ret = 0; + + if (!rf_ctrl_p) { + PLTFM_MSG_ERR("[ERR]%s NULL pointer!\n", __func__); + return MACNPTR; + } + + switch (rf_ctrl_p->type) { + case MAC_AX_FT_ACTION: + ret = af_fwd_cfg(adapter, + (enum mac_ax_action_frame)rf_ctrl_p->frame, + (enum mac_ax_fwd_target)rf_ctrl_p->fwd_tg); + break; + case MAC_AX_FT_ACTION_UD: + ret = af_ud_fwd_cfg(adapter, &rf_ctrl_p->af_ud_ctrl); + break; + case MAC_AX_FT_TRIGGER: + ret = tf_fwd_cfg(adapter, + (enum mac_ax_trigger_frame)rf_ctrl_p->frame, + (enum mac_ax_fwd_target)rf_ctrl_p->fwd_tg); + break; + case MAC_AX_FT_PM_CAM: + // Don't suggest using indirect access. + ret = pm_cam_fwd_cfg(adapter, &rf_ctrl_p->pm_cam_ctrl); + break; + } + + return ret; +} + +#endif diff --git a/phl/hal_g6/mac/mac_ax/rx_forwarding.h b/phl/hal_g6/mac/mac_ax/rx_forwarding.h new file mode 100644 index 0000000..a6cb1be --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/rx_forwarding.h @@ -0,0 +1,113 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_RX_FORWARDING_H_ +#define _MAC_AX_RX_FORWARDING_H_ + +#include "../type.h" + +/*--------------------Define ----------------------------------------*/ +// Payload Match CAM +#define PM_CAM_OFFSET_DW0 0 +#define PM_CAM_OFFSET_DW1 1 +#define PM_CAM_OFFSET_DW2 2 +#define PM_CAM_OFFSET_DW3 3 +#define PM_CAM_OFFSET_DW4 4 + +/* dword0 */ +#define PM_CAM_VALID BIT(0) +#define PM_CAM_TYPE_SH 1 +#define PM_CAM_TYPE_MSK 0x3 +#define PM_CAM_SUBTYPE_SH 3 +#define PM_CAM_SUBTYPE_MSK 0xf +#define PM_CAM_SKIP_MAC_IV_HDR BIT(7) +#define PM_CAM_TARGET_IND_SH 8 +#define PM_CAM_TARGET_IND_MSK 0x7 +#define PM_CAM_CRC16_SH 16 +#define PM_CAM_CRC16_MSK 0xffff + +/* dword1 */ +#define PM_CAM_PLD_MASK0_SH 0 +#define PM_CAM_PLD_MASK0_MSK 0xffffffff + +/* dword2 */ +#define PM_CAM_PLD_MASK1_SH 0 +#define PM_CAM_PLD_MASK1_MSK 0xffffffff + +/* dword3 */ +#define PM_CAM_PLD_MASK2_SH 0 +#define PM_CAM_PLD_MASK2_MSK 0xffffffff + +/* dword4 */ +#define PM_CAM_PLD_MASK3_SH 0 +#define PM_CAM_PLD_MASK3_MSK 0xffffffff + +#define MAC_AX_PM_CAM_ENTRY_CONTENT_SIZE 20 +#define MAC_AX_PM_CAM_ENTRY_NUM_MAX 16 + +#define PM_CAM_WAIT_CNT 2000 +#define PM_CAM_WAIT_US 1 + +/*--------------------Define Enum------------------------------------*/ + +/*--------------------Define MACRO----------------------------------*/ + +/*--------------------Define Struct-----------------------------------*/ + +/*--------------------Export global variable----------------------------*/ + +/*--------------------Function declaration-----------------------------*/ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup RX_Forwarding + * @{ + */ + +/** + * @brief mac_set_rx_forwarding: + * Set rx forwarding feature: + * 1. MAC_AX_FT_ACTION: for action frame + * 2. MAC_AX_FT_ACTION_UD: for action frame with user define + * 3. MAC_AX_FT_TRIGGER: for trigger frame + * 4. MAC_AX_FT_PM_CAM: for Payload match CAM + * + * @param *adapter + * @param *rf_ctrl_p + * @return Please Place Description here. + * @retval u32 + * #if MAC_AX_FW_REG_OFLD + * 1. MACSUCCESS 0 + * 2. MACNPTR 5 + * 3. MACNOBUF 9 + * 4. MACFWNONRDY 80 + * #else + * 1. MACSUCCESS 0 + * 2. MACNPTR 5 + * 3. MACNOITEM 11 + * 4. MACPOLLTO 12 + * 5. MACRFPMCAM 42 + * #endif + */ +u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/security_cam.c b/phl/hal_g6/mac/mac_ax/security_cam.c new file mode 100644 index 0000000..01c7318 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/security_cam.c @@ -0,0 +1,1120 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "security_cam.h" + +#define ADDR_CAM_SECINFO_OFFSET 0x1C +#define HW_SUPPORT_ENC_TYPE_NUM 0x0A +#define OUTRANGE_KEY_INDEX 0xFF +#define NO_MACID_ROLE 0xFF +#define VALID 0x01 +#define INVALID 0x00 +#define FORCE_KEYCAM_INDEX_TYPE 0xF0 +struct addr_sec_only_info { + u32 dword0; + u32 dword1; + u32 dword2; +}; + +enum SEC_CAM_KEY_TYPE { + SEC_CAM_KEY_TYPE_UNI = 0, + SEC_CAM_KEY_TYPE_GROUP = 1, + SEC_CAM_KEY_TYPE_BIP = 2, + SEC_CAM_KEY_TYPE_DEFAULT = 3 +}; + +enum ADDR_CAM_SEC_MODE { + ADDR_CAM_SEC_MODE_ZERO = 0, + ADDR_CAM_SEC_MODE_ONE = 1, + ADDR_CAM_SEC_MODE_TWO = 2, + ADDR_CAM_SEC_MODE_THREE = 3, +}; + +enum HW_SUPPORT_ENC_TYPE { + HW_SUPPORT_ENC_TYPE_NONE = 0x0, + HW_SUPPORT_ENC_TYPE_WEP40 = 0x1, + HW_SUPPORT_ENC_TYPE_WEP104 = 0x2, + HW_SUPPORT_ENC_TYPE_TKIP = 0x3, + HW_SUPPORT_ENC_TYPE_WAPI = 0x4, + HW_SUPPORT_ENC_TYPE_GCMSMS4 = 0x5, + HW_SUPPORT_ENC_TYPE_CCMP128 = 0x6, + HW_SUPPORT_ENC_TYPE_CCMP256 = 0x7, + HW_SUPPORT_ENC_TYPE_GCMP128 = 0x8, + HW_SUPPORT_ENC_TYPE_GCMP256 = 0x9, + HW_SUPPORT_ENC_TYPE_BIP128 = 0xA, +}; + +u32 sec_info_tbl_init(struct mac_ax_adapter *adapter, u8 op_mode) +{ + u8 i = 0; + struct sec_cam_table_t **sec_cam_table; + + if (op_mode == SEC_CAM_BACKUP) + sec_cam_table = &adapter->hw_info->sec_cam_table_bk; + else + sec_cam_table = &adapter->hw_info->sec_cam_table; + + /*First time access sec cam , initial sec cam table INVALID */ + if ((*sec_cam_table) == NULL) { + (*sec_cam_table) = (struct sec_cam_table_t *)PLTFM_MALLOC + (sizeof(struct sec_cam_table_t)); + + if (!(*sec_cam_table)) + return MACNOBUF; + + for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) { + (*sec_cam_table)->sec_cam_entry[i] = + (struct sec_cam_entry_t *)PLTFM_MALLOC + (sizeof(struct sec_cam_entry_t)); + + if (!(*sec_cam_table)->sec_cam_entry[i]) + return MACNOBUF; + + (*sec_cam_table)->sec_cam_entry[i]->sec_cam_info = + (struct mac_ax_sec_cam_info *)PLTFM_MALLOC + (sizeof(struct mac_ax_sec_cam_info)); + + if (!(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info) + return MACNOBUF; + + /* initial value*/ + (*sec_cam_table)->sec_cam_entry[i]->valid = INVALID; + (*sec_cam_table)->sec_cam_entry[i]->mac_id = 0; + (*sec_cam_table)->sec_cam_entry[i]->key_id = 0; + (*sec_cam_table)->sec_cam_entry[i]->key_type = 0; + } + (*sec_cam_table)->next_cam_storage_idx = 0; + } + return MACSUCCESS; +} + +u32 free_sec_info_tbl(struct mac_ax_adapter *adapter, u8 op_mode) +{ + u8 i; + struct sec_cam_table_t *sec_cam_table; + + if (op_mode == SEC_CAM_RESTORE) + sec_cam_table = adapter->hw_info->sec_cam_table_bk; + else + sec_cam_table = adapter->hw_info->sec_cam_table; + + if (!sec_cam_table) + return MACSUCCESS; + + for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) { + PLTFM_FREE(sec_cam_table->sec_cam_entry[i]->sec_cam_info, + sizeof(struct mac_ax_sec_cam_info)); + } + for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) { + PLTFM_FREE(sec_cam_table->sec_cam_entry[i], + sizeof(struct sec_cam_entry_t)); + } + + PLTFM_FREE(sec_cam_table, sizeof(struct sec_cam_table_t)); + + if (op_mode == SEC_CAM_RESTORE) + adapter->hw_info->sec_cam_table_bk = NULL; + else + adapter->hw_info->sec_cam_table = NULL; + + return MACSUCCESS; +} + +u32 fill_sec_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *s_info, + struct fwcmd_seccam_info *sec_info, + u8 clear) +{ + if (clear == INVALID) { + sec_info->dword0 = + cpu_to_le32(SET_WORD(s_info->sec_cam_idx, FWCMD_H2C_SECCAM_INFO_IDX) | + SET_WORD(s_info->offset, FWCMD_H2C_SECCAM_INFO_OFFSET) | + SET_WORD(s_info->len, FWCMD_H2C_SECCAM_INFO_LEN)); + + sec_info->dword1 = + cpu_to_le32(SET_WORD(s_info->type, FWCMD_H2C_SECCAM_INFO_TYPE) | + ((s_info->ext_key) ? FWCMD_H2C_SECCAM_INFO_EXT_KEY : 0) | + ((s_info->spp_mode) ? FWCMD_H2C_SECCAM_INFO_SPP_MODE : 0)); + sec_info->dword2 = s_info->key[0]; + sec_info->dword3 = s_info->key[1]; + sec_info->dword4 = s_info->key[2]; + sec_info->dword5 = s_info->key[3]; + } else { + sec_info->dword0 = + cpu_to_le32(SET_WORD(s_info->sec_cam_idx, FWCMD_H2C_SECCAM_INFO_IDX) | + SET_WORD(s_info->offset, FWCMD_H2C_SECCAM_INFO_OFFSET) | + SET_WORD(s_info->len, FWCMD_H2C_SECCAM_INFO_LEN)); + + sec_info->dword1 = 0x0; + sec_info->dword2 = 0x0; + sec_info->dword3 = 0x0; + sec_info->dword4 = 0x0; + sec_info->dword5 = 0x0; + } + return MACSUCCESS; +} + +u32 fill_addr_cam_sec_only(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info, + struct addr_sec_only_info *addr_sec_info) +{ + struct mac_ax_addr_cam_info a_info; + + a_info = info->a_info; + + addr_sec_info->dword0 = + cpu_to_le32((a_info.aid12 & 0xfff) | + ((a_info.wol_pattern) ? FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN + : 0) | + ((a_info.wol_uc) ? FWCMD_H2C_ADDRCAM_INFO_WOL_UC : 0) | + ((a_info.wol_magic) ? + FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC : 0) | + ((a_info.wapi) ? FWCMD_H2C_ADDRCAM_INFO_WAPI : 0) | + SET_WORD(a_info.sec_ent_mode, + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE) | + SET_WORD(a_info.sec_ent_keyid[0], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID) | + SET_WORD(a_info.sec_ent_keyid[1], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID) | + SET_WORD(a_info.sec_ent_keyid[2], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID) | + SET_WORD(a_info.sec_ent_keyid[3], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID) | + SET_WORD(a_info.sec_ent_keyid[4], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID) | + SET_WORD(a_info.sec_ent_keyid[5], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID) | + SET_WORD(a_info.sec_ent_keyid[6], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID)); + + addr_sec_info->dword1 = + cpu_to_le32(SET_WORD(a_info.sec_ent_valid, + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID) | + SET_WORD(a_info.sec_ent[0], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0) | + SET_WORD(a_info.sec_ent[1], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1) | + SET_WORD(a_info.sec_ent[2], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2)); + + addr_sec_info->dword2 = + cpu_to_le32(SET_WORD(a_info.sec_ent[3], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3) | + SET_WORD(a_info.sec_ent[4], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4) | + SET_WORD(a_info.sec_ent[5], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5) | + SET_WORD(a_info.sec_ent[6], + FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6)); + + return MACSUCCESS; +} + +u32 mac_upd_sec_infotbl(struct mac_ax_adapter *adapter, + struct fwcmd_seccam_info *info) +{ + u32 ret = 0, s_info_tbl[6], cam_address = 0; + u8 *buf, i; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_seccam_info *tbl; + struct mac_ax_sec_cam_info *s_info; + + /*h2c access*/ + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_seccam_info)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_seccam_info *)buf; + + tbl->dword0 = info->dword0; + tbl->dword1 = info->dword1; + tbl->dword2 = info->dword2; + tbl->dword3 = info->dword3; + tbl->dword4 = info->dword4; + tbl->dword5 = info->dword5; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_SEC_CAM, + FWCMD_H2C_FUNC_SECCAM_INFO, + 0, + 1); + + if (ret != MACSUCCESS) + goto fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret != MACSUCCESS) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret != MACSUCCESS) + goto fail; + + h2cb_free(adapter, h2cb); + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + } else { + /* Indirect Access */ + s_info = (struct mac_ax_sec_cam_info *)info; + s_info_tbl[0] = info->dword0; + s_info_tbl[1] = info->dword1; + s_info_tbl[2] = info->dword2; + s_info_tbl[3] = info->dword3; + s_info_tbl[4] = info->dword4; + s_info_tbl[5] = info->dword5; + + /* Indirect write security cam */ + PLTFM_MSG_WARN("%s ind access start\n", __func__); + cam_address = s_info->sec_cam_idx * SEC_CAM_ENTRY_SIZE; + for (i = 0; i < 5; i++) + mac_sram_dbg_write(adapter, cam_address + (i * 4), + cpu_to_le32(s_info_tbl[i + 1]), + SEC_CAM_SEL); + PLTFM_MSG_WARN("%s ind access end\n", __func__); + + return MACSUCCESS; + } + + return ret; +} + +u8 check_key_index(u8 addr_cam_sec_mode, u8 key_type, u8 key_index) +{ + switch (addr_cam_sec_mode) { + case ADDR_CAM_SEC_MODE_ZERO: + switch (key_type) { + case SEC_CAM_KEY_TYPE_UNI: + if (key_index <= 6) + return MACSUCCESS; + default: + break; + } + break; + case ADDR_CAM_SEC_MODE_ONE: + switch (key_type) { + case SEC_CAM_KEY_TYPE_UNI: + if (key_index <= 6) + return MACSUCCESS; + default: + break; + } + break; + case ADDR_CAM_SEC_MODE_TWO: + switch (key_type) { + case SEC_CAM_KEY_TYPE_UNI: + if (key_index <= 1) + return MACSUCCESS; + break; + case SEC_CAM_KEY_TYPE_GROUP: + if (key_index >= 2 && key_index <= 4) + return MACSUCCESS; + break; + case SEC_CAM_KEY_TYPE_BIP: + if (key_index >= 5 && key_index <= 6) + return MACSUCCESS; + break; + default: + break; + } + break; + case ADDR_CAM_SEC_MODE_THREE: + switch (key_type) { + case SEC_CAM_KEY_TYPE_UNI: + if (key_index <= 1) + return MACSUCCESS; + break; + case SEC_CAM_KEY_TYPE_GROUP: + if (key_index >= 2 && key_index <= 5) + return MACSUCCESS; + break; + case SEC_CAM_KEY_TYPE_BIP: + if (key_index == 6) + return MACSUCCESS; + break; + default: + break; + } + break; + } + return 1; +} + +u8 decide_key_index(u8 addr_cam_sec_mode, u8 key_type) +{ + u8 key_index = 0; + + switch (addr_cam_sec_mode) { + case ADDR_CAM_SEC_MODE_ZERO: + if (key_type == SEC_CAM_KEY_TYPE_UNI) + key_index = 0; + else if (key_type == SEC_CAM_KEY_TYPE_GROUP) + return MACWNGKEYTYPE; + else if (key_type == SEC_CAM_KEY_TYPE_BIP) + return MACWNGKEYTYPE; + break; + case ADDR_CAM_SEC_MODE_ONE: + if (key_type == SEC_CAM_KEY_TYPE_UNI) + key_index = 0; + else if (key_type == SEC_CAM_KEY_TYPE_GROUP) + return MACWNGKEYTYPE; + else if (key_type == SEC_CAM_KEY_TYPE_BIP) + return MACWNGKEYTYPE; + break; + case ADDR_CAM_SEC_MODE_TWO: + if (key_type == SEC_CAM_KEY_TYPE_UNI) + key_index = 0; + else if (key_type == SEC_CAM_KEY_TYPE_GROUP) + key_index = 2; + else if (key_type == SEC_CAM_KEY_TYPE_BIP) + key_index = 5; + break; + case ADDR_CAM_SEC_MODE_THREE: + if (key_type == SEC_CAM_KEY_TYPE_UNI) + key_index = 0; + else if (key_type == SEC_CAM_KEY_TYPE_GROUP) + key_index = 2; + else if (key_type == SEC_CAM_KEY_TYPE_BIP) + key_index = 6; + break; + default: + break; + } + return key_index; +} + +u8 decide_sec_cam_index(struct mac_ax_adapter *adapter, u8 *sec_cam_idx) +{ + u8 sec_idx = 0, i = 0; + /* call by pointer */ + struct sec_cam_table_t **sec_cam_table = + &adapter->hw_info->sec_cam_table; + + /*First time access sec cam , initial sec cam table INVALID */ + if ((*sec_cam_table) == NULL) { + (*sec_cam_table) = (struct sec_cam_table_t *)PLTFM_MALLOC + (sizeof(struct sec_cam_table_t)); + + if (!(*sec_cam_table)) + return MACNOBUF; + + for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) { + (*sec_cam_table)->sec_cam_entry[i] = + (struct sec_cam_entry_t *)PLTFM_MALLOC + (sizeof(struct sec_cam_entry_t)); + + if (!(*sec_cam_table)->sec_cam_entry[i]) + return MACNOBUF; + + (*sec_cam_table)->sec_cam_entry[i]->sec_cam_info = + (struct mac_ax_sec_cam_info *)PLTFM_MALLOC + (sizeof(struct mac_ax_sec_cam_info)); + + if (!(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info) + return MACNOBUF; + + /* initial value*/ + (*sec_cam_table)->sec_cam_entry[i]->valid = INVALID; + (*sec_cam_table)->sec_cam_entry[i]->mac_id = 0; + (*sec_cam_table)->sec_cam_entry[i]->key_id = 0; + (*sec_cam_table)->sec_cam_entry[i]->key_type = 0; + } + (*sec_cam_table)->next_cam_storage_idx = 0; + } + + /*If table has been initialize, assgin the sec cam storge idx */ + sec_idx = (*sec_cam_table)->next_cam_storage_idx; + for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) { + if ((*sec_cam_table)->sec_cam_entry[sec_idx]->valid == + INVALID) { + (*sec_cam_table)->next_cam_storage_idx = + (sec_idx + 1) % SEC_CAM_ENTRY_NUM; + *sec_cam_idx = sec_idx; + return MACSUCCESS; + } + sec_idx++; + sec_idx %= SEC_CAM_ENTRY_NUM; + } + + return MACSECCAMFL; +} + +u8 delete_key_from_addr_cam(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, u8 key_type, + u8 key_id, u8 *sec_cam_idx) +{ + u32 ret = 0; + u8 key_index = 0, key_valid_byte = 0, i = 0; + u8 key_valid[7] = {0}, hit_flag = 0; + + key_valid_byte = role->info.a_info.sec_ent_valid; + + key_index = decide_key_index(role->info.a_info.sec_ent_mode, key_type); + + if (key_index == MACWNGKEYTYPE) + return MACWNGKEYTYPE; + + for (i = 0; i < 7; i++) { + key_valid[i] = key_valid_byte % 2; + key_valid_byte = key_valid_byte >> 1; + } + + /* find the key real storage idx */ + for (i = key_index; i < 7; i++) { + if (role->info.a_info.sec_ent_keyid[i] == key_id && + key_valid[i] == VALID) { + key_index = i; + hit_flag = 1; + break; + } + } + + if (hit_flag == 0) + return MACKEYNOTEXT; + + if (check_key_index(role->info.a_info.sec_ent_mode, + key_type, key_index)) { + PLTFM_MSG_TRACE("check addr key index full\n"); + return MACADDRCAMKEYFL; + } + + /*get the key cam index*/ + *sec_cam_idx = role->info.a_info.sec_ent[key_index]; + + role->info.a_info.sec_ent_keyid[key_index] = 0; + role->info.a_info.sec_ent_valid &= ~(BIT(key_index)); + role->info.a_info.sec_ent[key_index] = 0; + + /* update addr cam */ + ret = mac_upd_addr_cam(adapter, &role->info, CHG); + if (ret == MACBSSIDCAMFL) { + PLTFM_MSG_ERR("[ERR]: BSSID CAM full\n"); + return MACBSSIDCAMFL; + } + + return MACSUCCESS; +} + +u8 insert_key_to_addr_cam(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role, u8 key_type, + u8 key_id, u8 sec_cam_idx) +{ + u32 ret = 0; + u8 key_index = 0, key_valid_byte = 0, i = 0; + u8 key_valid[7] = {0}, hit_flag = 0; + + key_valid_byte = role->info.a_info.sec_ent_valid; + key_index = decide_key_index(role->info.a_info.sec_ent_mode, key_type); + + if (key_index == MACWNGKEYTYPE) + return MACWNGKEYTYPE; + + for (i = 0; i < 7; i++) { + key_valid[i] = key_valid_byte % 2; + key_valid_byte = key_valid_byte >> 1; + } + + /* find the key real storage idx */ + for (i = key_index; i < 7; i++) { + if (key_valid[i] != VALID) { + key_index = i; + hit_flag = 1; + break; + } + } + if (hit_flag == 0) + return MACADDRCAMKEYFL; + + if (check_key_index(role->info.a_info.sec_ent_mode, + key_type, key_index)) { + PLTFM_MSG_TRACE("check addr key index full\n"); + return MACADDRCAMKEYFL; + } + + role->info.a_info.sec_ent_keyid[key_index] = key_id; + role->info.a_info.sec_ent_valid |= BIT(key_index); + role->info.a_info.sec_ent[key_index] = sec_cam_idx; + + ret = mac_upd_addr_cam(adapter, &role->info, CHG); + if (ret == MACBSSIDCAMFL) { + PLTFM_MSG_ERR("[ERR]: BSSID CAM full\n"); + return MACBSSIDCAMFL; + } + + return MACSUCCESS; +} + +u32 m_security_cam_hal(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *sec_cam_info, + u8 mac_id, u8 key_id, u8 key_type, + u8 sec_cam_idx, u8 opmode) +{ + u8 i = 0; + struct sec_cam_entry_t *sec_cam_entry = NULL; + struct sec_cam_entry_t *sec_cam_bk_entry = NULL; + struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table; + struct sec_cam_table_t *sec_cam_table_bk = + adapter->hw_info->sec_cam_table_bk; + + if (!sec_cam_table) + return MACSUCCESS; + + sec_cam_entry = + adapter->hw_info->sec_cam_table->sec_cam_entry[sec_cam_idx]; + if (opmode == SEC_CAM_CLEAR) { + sec_cam_entry->valid = INVALID; + sec_cam_entry->mac_id = 0; + sec_cam_entry->key_id = 0; + sec_cam_entry->key_type = 0; + sec_cam_entry->sec_cam_info->type = 0; + sec_cam_entry->sec_cam_info->ext_key = 0; + sec_cam_entry->sec_cam_info->spp_mode = 0; + for (i = 0; i < 3; i++) + sec_cam_entry->sec_cam_info->key[i] = 0; + + } else if (opmode == SEC_CAM_BACKUP) { + if (!sec_cam_table_bk) + return MACSUCCESS; + + sec_cam_bk_entry = adapter->hw_info->sec_cam_table_bk + ->sec_cam_entry[sec_cam_idx]; + + // backup security entry in halmac + sec_cam_bk_entry->valid = sec_cam_entry->valid; + sec_cam_bk_entry->mac_id = sec_cam_entry->mac_id; + sec_cam_bk_entry->key_id = sec_cam_entry->key_id; + sec_cam_bk_entry->key_type = sec_cam_entry->key_type; + sec_cam_bk_entry->sec_cam_info->type = + sec_cam_entry->sec_cam_info->type; + sec_cam_bk_entry->sec_cam_info->ext_key = + sec_cam_entry->sec_cam_info->ext_key; + sec_cam_bk_entry->sec_cam_info->spp_mode = + sec_cam_entry->sec_cam_info->spp_mode; + + for (i = 0; i < 4; i++) + sec_cam_bk_entry->sec_cam_info->key[i] = + sec_cam_entry->sec_cam_info->key[i]; + } else { + if (!sec_cam_info) { + sec_cam_entry->valid = VALID; + sec_cam_entry->mac_id = mac_id; + sec_cam_entry->key_id = key_id; + sec_cam_entry->key_type = key_type; + sec_cam_entry->sec_cam_info->type = 0x0; + sec_cam_entry->sec_cam_info->ext_key = 0x0; + sec_cam_entry->sec_cam_info->spp_mode = 0x0; + for (i = 0; i < 4; i++) + sec_cam_entry->sec_cam_info->key[i] = 0x0; + } else { + sec_cam_entry->valid = VALID; + sec_cam_entry->mac_id = mac_id; + sec_cam_entry->key_id = key_id; + sec_cam_entry->key_type = key_type; + sec_cam_entry->sec_cam_info->type = sec_cam_info->type; + sec_cam_entry->sec_cam_info->ext_key = + sec_cam_info->ext_key; + sec_cam_entry->sec_cam_info->spp_mode = + sec_cam_info->spp_mode; + for (i = 0; i < 4; i++) + sec_cam_entry->sec_cam_info->key[i] = + sec_cam_info->key[i]; + } + } + + return MACSUCCESS; +} + +u32 disconnect_flush_key(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role) +{ + struct mac_ax_sec_cam_info *sec_cam_info = NULL; + u8 i, sec_ent_valid, mac_id, key_type, key_index; + u8 key_valid[7] = {0}, sec_cam_index[7] = {0}, sec_ent_keyid[7] = {0}; + + sec_ent_valid = role->info.a_info.sec_ent_valid; + mac_id = role->info.a_info.sec_ent_valid; + + for (i = 0; i < 7; i++) { + key_valid[i] = sec_ent_valid % 2; + sec_ent_valid = sec_ent_valid >> 1; + sec_cam_index[i] = role->info.a_info.sec_ent[i]; + sec_ent_keyid[i] = role->info.a_info.sec_ent_keyid[i]; + } + + key_type = SEC_CAM_KEY_TYPE_DEFAULT; + for (key_index = 0; key_index < 7; key_index++) { + if (key_valid[key_index] == VALID) { + m_security_cam_hal(adapter, sec_cam_info, + mac_id, sec_ent_keyid[key_index], + key_type, sec_cam_index[key_index], + SEC_CAM_CLEAR); + } + } + return MACSUCCESS; +} + +u32 mac_sta_del_key(struct mac_ax_adapter *adapter, + u8 mac_id, + u8 key_id, + u8 key_type) +{ + struct mac_ax_sec_cam_info sec_cam_info; + struct mac_role_tbl *role = NULL; + u8 sec_cam_idx = 0; + u32 sec_table[6] = {0}, ret = 0; + + role = mac_role_srch(adapter, mac_id); + + if (!role) + return MACNOROLE; + + ret = delete_key_from_addr_cam(adapter, role, key_type, + key_id, &sec_cam_idx); + if (ret != MACSUCCESS) + return ret; + + sec_cam_info.sec_cam_idx = sec_cam_idx; + sec_cam_info.offset = 0x00; + sec_cam_info.len = SEC_CAM_ENTRY_SIZE; + + fill_sec_cam_info(adapter, &sec_cam_info, + (struct fwcmd_seccam_info *)sec_table, 1); + + ret = (u8)mac_upd_sec_infotbl(adapter, + (struct fwcmd_seccam_info *)sec_table); + if (ret != MACSUCCESS) + return ret; + + m_security_cam_hal(adapter, NULL, + mac_id, key_id, key_type, + sec_cam_idx, SEC_CAM_CLEAR); + + return MACSUCCESS; +} + +u32 mac_sta_add_key(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *sec_cam_info, + u8 mac_id, + u8 key_id, + u8 key_type) +{ + u8 sec_cam_idx = 0; + u32 sec_table[6] = {0}, ret = 0; + struct mac_role_tbl *role = NULL; + + if (sec_cam_info->type > HW_SUPPORT_ENC_TYPE_NUM) + return MACWNGKEYTYPE; + + role = mac_role_srch(adapter, mac_id); + if (!role) + return MACNOROLE; + + if (sec_cam_info->offset != FORCE_KEYCAM_INDEX_TYPE) { + ret = decide_sec_cam_index(adapter, &sec_cam_idx); + if (ret != MACSUCCESS) + return ret; + } else { + sec_cam_idx = sec_cam_info->sec_cam_idx; + } + + sec_cam_info->sec_cam_idx = sec_cam_idx; + sec_cam_info->offset = 0x00; + sec_cam_info->len = SEC_CAM_ENTRY_SIZE; + ret = insert_key_to_addr_cam(adapter, role, key_type, key_id, + sec_cam_info->sec_cam_idx); + if (ret != MACSUCCESS) + return ret; + + fill_sec_cam_info(adapter, sec_cam_info, + (struct fwcmd_seccam_info *)sec_table, 0); + + ret = (u8)mac_upd_sec_infotbl(adapter, + (struct fwcmd_seccam_info *)sec_table); + if (ret != MACSUCCESS) + return ret; + m_security_cam_hal(adapter, sec_cam_info, + mac_id, key_id, key_type, + sec_cam_idx, SEC_CAM_NORMAL); + + return MACSUCCESS; +} + +u32 mac_sta_keycam_backup(struct mac_ax_adapter *adapter, u8 op_mode) +{ + u8 sec_cam_idx = 0, i = 0; + u32 ret = 0; + struct sec_cam_entry_t *s_entry = NULL; + struct mac_ax_sec_cam_info sec_cam_info; + + struct sec_cam_table_t *sec_cam_table = + adapter->hw_info->sec_cam_table; + struct sec_cam_table_t *sec_cam_table_bk = + adapter->hw_info->sec_cam_table_bk; + + if (op_mode > SEC_CAM_RESTORE) + return MACNOITEM; + + if (op_mode == SEC_CAM_BACKUP) { + /*Initial backup sec cam table */ + ret = sec_info_tbl_init(adapter, SEC_CAM_BACKUP); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret); + return ret; + } + + /*Backup sec cam table valid entry*/ + for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; + sec_cam_idx++) { + /* Only search valid entry */ + if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid == + VALID) { + m_security_cam_hal(adapter, NULL, 0, 0, 0, + sec_cam_idx, SEC_CAM_BACKUP); + } + } + + ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret); + return ret; + } + + } else if (op_mode == SEC_CAM_RESTORE) { + ret = sec_info_tbl_init(adapter, SEC_CAM_NORMAL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret); + return ret; + } + + /*Force sec cam table */ + for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; + sec_cam_idx++) { + s_entry = sec_cam_table_bk->sec_cam_entry[sec_cam_idx]; + PLTFM_MSG_ERR("sec_cam_idx %d\n", sec_cam_idx); + /* Only search valid entry */ + if (s_entry->valid == VALID) { + sec_cam_info.offset = FORCE_KEYCAM_INDEX_TYPE; + sec_cam_info.sec_cam_idx = sec_cam_idx; + sec_cam_info.type = + s_entry->sec_cam_info->type; + sec_cam_info.ext_key = + s_entry->sec_cam_info->ext_key; + sec_cam_info.spp_mode = + s_entry->sec_cam_info->spp_mode; + for (i = 0; i < 4; i++) { + sec_cam_info.key[i] = + s_entry->sec_cam_info->key[i]; + } + + mac_sta_add_key(adapter, &sec_cam_info, + s_entry->mac_id, s_entry->key_id, + s_entry->key_type); + } + } + + /*Free backup sec cam table */ + ret = free_sec_info_tbl(adapter, SEC_CAM_RESTORE); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret); + return ret; + } + } else { + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 mac_sta_search_key_idx(struct mac_ax_adapter *adapter, + u8 mac_id, u8 key_id, u8 key_type) +{ + u32 sec_cam_idx = 0; + struct sec_cam_entry_t *s_entry = NULL; + struct sec_cam_table_t *sec_cam_table = + adapter->hw_info->sec_cam_table; + + if (!sec_cam_table) + return MACNOKEYINDEX; + + /*Search SEC CAM Table */ + for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; sec_cam_idx++) { + /* Only search valid entry */ + if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid == VALID) { + s_entry = sec_cam_table->sec_cam_entry[sec_cam_idx]; + + if (s_entry->mac_id != mac_id) + continue; + if (s_entry->key_id != key_id) + continue; + if (s_entry->key_type != key_type) + continue; + + return sec_cam_idx; + } + } + return MACNOKEYINDEX; +} + +u32 mac_sta_hw_security_support(struct mac_ax_adapter *adapter, + u8 hw_security_support_type, u8 enable) +{ + u32 val32 = 0; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + switch (enable) { + case 1: + val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL); + switch (hw_security_support_type) { + case SEC_TX_ENC: + val32 |= B_AX_SEC_TX_ENC; + break; + case SEC_RX_ENC: + val32 |= B_AX_SEC_RX_DEC; + break; + case SEC_BC_ENC: + val32 |= B_AX_BC_DEC; + break; + case SEC_MC_ENC: + val32 |= B_AX_MC_DEC; + break; + case SEC_UC_MGNT_ENC: + val32 |= B_AX_UC_MGNT_DEC; + break; + case SEC_BMC_MGNT_ENC: + val32 |= B_AX_BMC_MGNT_DEC; + break; + default: + break; + } + MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32); + break; + case 0: + val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL); + switch (hw_security_support_type) { + case SEC_TX_ENC: + val32 &= ~B_AX_SEC_TX_ENC; + break; + case SEC_RX_ENC: + val32 &= ~B_AX_SEC_RX_DEC; + break; + case SEC_BC_ENC: + val32 &= ~B_AX_BC_DEC; + break; + case SEC_MC_ENC: + val32 &= ~B_AX_MC_DEC; + break; + case SEC_UC_MGNT_ENC: + val32 &= ~B_AX_UC_MGNT_DEC; + break; + case SEC_BMC_MGNT_ENC: + val32 &= ~B_AX_BMC_MGNT_DEC; + break; + default: + break; + } + + MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32); + break; + default: + break; + } + + return MACSUCCESS; +} + +u8 check_key_type(u8 addr_cam_sec_mode, u8 key_index) +{ + switch (addr_cam_sec_mode) { + case ADDR_CAM_SEC_MODE_ZERO: + if (key_index <= 6) + return SEC_CAM_KEY_TYPE_UNI; + break; + + case ADDR_CAM_SEC_MODE_ONE: + if (key_index <= 6) + return SEC_CAM_KEY_TYPE_UNI; + break; + + case ADDR_CAM_SEC_MODE_TWO: + if (key_index <= 1) + return SEC_CAM_KEY_TYPE_UNI; + + else if (key_index >= 2 && key_index <= 4) + return SEC_CAM_KEY_TYPE_GROUP; + + else if (key_index >= 5 && key_index <= 6) + return SEC_CAM_KEY_TYPE_BIP; + + else + break; + break; + + case ADDR_CAM_SEC_MODE_THREE: + if (key_index <= 1) + return SEC_CAM_KEY_TYPE_UNI; + + else if (key_index >= 2 && key_index <= 5) + return SEC_CAM_KEY_TYPE_GROUP; + + else if (key_index == 6) + return SEC_CAM_KEY_TYPE_BIP; + + else + break; + break; + } + + return MACKEYNOTEXT; +} + +u32 refresh_security_cam_info(struct mac_ax_adapter *adapter, + u8 mac_id) +{ + u32 addr_idx = 0, cam_address = 0; + u32 i = 0; + u8 key_valid[7] = {0}, key_cam_index[7] = {0}, sec_ent_keyid[7] = {0}; + u8 macid = 0, hit_flag = VALID, key_id_sh = 0, key_cam_idx_sh = 0; + u8 key_valid_byte = 0, key_valid_byte_ori = 0, key_type = 0; + u8 key_index = 0, sec_ent_mode = 0, sec_cam_idx = 0; + u32 dword[10] = {0}; + u8 addr_cam_size = get_addr_cam_size(adapter); + + struct sec_cam_entry_t *s_entry = NULL; + struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table; + struct mac_role_tbl *role = NULL; + + /*read HW key in address cam */ + for (addr_idx = 0; addr_idx < 0x80; addr_idx++) { + hit_flag = INVALID; + + PLTFM_MSG_WARN("%s ind access macid %d start\n", __func__, mac_id); + cam_address = addr_idx * addr_cam_size; + for (i = 0; i < 10; i++) + dword[i] = mac_sram_dbg_read(adapter, cam_address, + ADDR_CAM_SEL); + PLTFM_MSG_WARN("%s ind access macid %d end\n", __func__, mac_id); + + if ((dword[0] & ADDRCAM_VALID) == VALID) { + macid = (dword[6] & ADDRCAM_MACID_MSK); + + if (macid == mac_id) { + sec_ent_mode = (dword[7] >> ADDRCAM_SEC_MODE_SH) + & ADDRCAM_SECMODE_MSK; + + key_id_sh = ADDRCAM_SEC_ENT0_KEYID_SH; + for (i = 0; i < 7; i++) { + sec_ent_keyid[i] = + (dword[7] >> key_id_sh) & + ADDRCAM_KEYID_MSK; + key_id_sh += 2; + } + + key_valid_byte = + dword[8] & ADDRCAM_KEY_VALID_MSK; + key_valid_byte_ori = key_valid_byte; + + for (i = 0; i < 7; i++) { + key_valid[i] = key_valid_byte % 2; + key_valid_byte = key_valid_byte >> 1; + } + + key_cam_idx_sh = 0; + for (i = 0; i < 3; i++) { + key_cam_idx_sh = (i + 1) * 8; + key_cam_index[i] = + (dword[8] >> key_cam_idx_sh) & + ADDRCAM_KEY_CAM_IDX_MSK; + } + + key_cam_idx_sh = 0; + for (i = 3; i < 7; i++) { + key_cam_idx_sh = (i - 3) * 8; + key_cam_index[i] = + (dword[9] >> key_cam_idx_sh) & + ADDRCAM_KEY_CAM_IDX_MSK; + } + + hit_flag = VALID; + break; + } + } + } + + if (hit_flag == INVALID) { + PLTFM_MSG_TRACE("MACID : %d not exist\n", mac_id); + return MACNOROLE; + } + + // clear halmac table + for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; sec_cam_idx++) { + // Only search valid entry + if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid == VALID) { + s_entry = sec_cam_table->sec_cam_entry[sec_cam_idx]; + + if (s_entry->mac_id == mac_id) { + m_security_cam_hal(adapter, NULL, + mac_id, DEFAULT_KEYID, + DEFAULT_KEYTYPE, + sec_cam_idx, SEC_CAM_CLEAR); + } + } + } + + // insert halmac table + for (key_index = 0; key_index < 7; key_index++) { + if (key_valid[key_index] == VALID) { + key_type = check_key_type(sec_ent_mode, key_index); + m_security_cam_hal(adapter, NULL, + mac_id, sec_ent_keyid[key_index], + key_type, key_cam_index[key_index], + SEC_CAM_NORMAL); + } + } + + // write back to address cam sec part + role = mac_role_srch(adapter, mac_id); + if (!role) + return MACNOROLE; + + role->info.a_info.sec_ent_valid = key_valid_byte_ori; + for (i = 0; i < 7; i++) { + role->info.a_info.sec_ent_keyid[i] = sec_ent_keyid[i]; + role->info.a_info.sec_ent[i] = key_cam_index[i]; + } + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/security_cam.h b/phl/hal_g6/mac/mac_ax/security_cam.h new file mode 100644 index 0000000..c4b4003 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/security_cam.h @@ -0,0 +1,335 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_SEC_CAM_H_ +#define _MAC_AX_SEC_CAM_H_ + +#include "../mac_def.h" +#include "role.h" +#include "fwcmd.h" +#include "addr_cam.h" + +/*--------------------Define ----------------------------------------*/ +#ifdef PHL_FEATURE_AP + #define SEC_CAM_ENTRY_NUM 0x80 +#else + #define SEC_CAM_ENTRY_NUM 0x10 +#endif + +#define ADDRCAM_VALID BIT0 +#define ADDRCAM_SEC_MODE_SH 16 +#define ADDRCAM_SEC_ENT0_KEYID_SH 18 +#define ADDRCAM_SEC_ENT0_KEYID_SH 18 + +#define ADDRCAM_KEYID_MSK 0x3 +#define ADDRCAM_SECMODE_MSK 0x3 +#define ADDRCAM_MACID_MSK 0xFF +#define ADDRCAM_KEY_VALID_MSK 0xFF +#define ADDRCAM_KEY_CAM_IDX_MSK 0xFF + +#define ADDRCAM_VALID_BIT_OFFSET 0x00 +#define ADDRCAM_MACID_OFFSET 0x18 +#define ADDRCAM_SECMODE_OFFSET 0x1C +#define ADDRCAM_KEY_VALID_OFFSET 0x20 +#define ADDRCAM_KEY_IDX_OFFSET 0x21 + +#define SEC_CAM_ENTRY_SIZE 0x20 +#define ADDR_CAM_ENTRY_SIZE 0x40 +#define MACNOKEYINDEX 0xFF + +#define DEFAULT_KEYID 0x0 +#define DEFAULT_KEYTYPE 0x0 + +/*--------------------DSecurity cam type declaration-----------------*/ + +/** + * @struct sec_cam_entry_t + * @brief sec_cam_entry_t + * + * @var sec_cam_entry_t::valid + * Please Place Description here. + * @var sec_cam_entry_t::mac_id + * Please Place Description here. + * @var sec_cam_entry_t::key_id + * Please Place Description here. + * @var sec_cam_entry_t::key_type + * Please Place Description here. + * @var sec_cam_entry_t::sec_cam_info + * Please Place Description here. + */ +struct sec_cam_entry_t { + u8 valid; + u8 mac_id; + u8 key_id; + u8 key_type; + struct mac_ax_sec_cam_info *sec_cam_info; +}; + +/** + * @struct sec_cam_table_t + * @brief sec_cam_table_t + * + * @var sec_cam_table_t::sec_cam_entry + * Please Place Description here. + * @var sec_cam_table_t::next_cam_storage_idx + * Please Place Description here. + */ +struct sec_cam_table_t { + struct sec_cam_entry_t *sec_cam_entry[128]; + u8 next_cam_storage_idx; +}; + +/** + * @enum SEC_FUNCTION_TYPE + * + * @brief SEC_FUNCTION_TYPE + * + * @var SEC_FUNCTION_TYPE::SEC_TX_ENC + * Please Place Description here. + * @var SEC_FUNCTION_TYPE::SEC_RX_ENC + * Please Place Description here. + * @var SEC_FUNCTION_TYPE::SEC_BC_ENC + * Please Place Description here. + * @var SEC_FUNCTION_TYPE::SEC_MC_ENC + * Please Place Description here. + * @var SEC_FUNCTION_TYPE::SEC_UC_MGNT_ENC + * Please Place Description here. + * @var SEC_FUNCTION_TYPE::SEC_BMC_MGNT_ENC + * Please Place Description here. + */ +enum SEC_FUNCTION_TYPE { + SEC_TX_ENC = 0, + SEC_RX_ENC = 1, + SEC_BC_ENC = 2, + SEC_MC_ENC = 3, + SEC_UC_MGNT_ENC = 4, + SEC_BMC_MGNT_ENC = 5, +}; + +enum SEC_CAM_OP_MODE { + SEC_CAM_NORMAL = 0, + SEC_CAM_CLEAR = 1, + SEC_CAM_BACKUP = 2, + SEC_CAM_RESTORE = 3, +}; + +/*--------------------Funciton declaration----------------------------*/ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief disconnect_flush_key + * + * @param *adapter + * @param *role + * @return Please Place Description here. + * @retval u32 + */ +u32 disconnect_flush_key(struct mac_ax_adapter *adapter, + struct mac_role_tbl *role); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief sec_info_tbl_init + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ + +u32 sec_info_tbl_init(struct mac_ax_adapter *adapter, u8 op_mode); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief free_sec_info_tbl + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ + +u32 free_sec_info_tbl(struct mac_ax_adapter *adapter, u8 op_mode); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief fill_sec_cam_info + * + * @param *adapter + * @param *s_info + * @param *sec_info + * @return Please Place Description here. + * @retval u32 + */ + +u32 fill_sec_cam_info(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *s_info, + struct fwcmd_seccam_info *sec_info, + u8 op_mode); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief mac_sta_add_key + * + * @param *adapter + * @param *sec_cam_content + * @param mac_id + * @param key_id + * @param key_type + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_sta_add_key(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *sec_cam_content, + u8 mac_id, + u8 key_id, + u8 key_type); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief mac_sta_del_key + * + * @param *adapter + * @param mac_id + * @param key_id + * @param key_type + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_sta_del_key(struct mac_ax_adapter *adapter, + u8 mac_id, + u8 key_id, + u8 key_type); +/** + * @} + * @} + */ + +u32 mac_sta_keycam_backup(struct mac_ax_adapter *adapter, u8 op_mode); + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief mac_sta_search_key_idx + * + * @param *adapter + * @param mac_id + * @param key_id + * @param key_type + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_sta_search_key_idx(struct mac_ax_adapter *adapter, + u8 mac_id, u8 key_id, u8 key_type); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup Security + * @{ + */ + +/** + * @brief mac_sta_hw_security_support + * + * @param *adapter + * @param hw_security_support_type + * @param enable + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_sta_hw_security_support(struct mac_ax_adapter *adapter, + u8 hw_security_support_type, u8 enable); +/** + * @} + * @} + */ + +u32 refresh_security_cam_info(struct mac_ax_adapter *adapter, + u8 mac_id); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/ser.c b/phl/hal_g6/mac/mac_ax/ser.c new file mode 100644 index 0000000..5fa3be8 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/ser.c @@ -0,0 +1,675 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "ser.h" + +static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter); +static void dump_err_status_dmac(struct mac_ax_adapter *adapter); +static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band); + +u32 mac_trigger_cmac_err(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u16 val16; + u32 ret; + + ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN); + MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8 & (~B_AX_TMAC_EN)); + PLTFM_DELAY_MS(1); + MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8); + + val16 = MAC_REG_R16(R_AX_PTCL_IMR0) | B_AX_F2PCMD_EMPTY_ERR_INT_EN; + MAC_REG_W16(R_AX_PTCL_IMR0, val16); + MAC_REG_W16(R_AX_PTCL_IMR0, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN); + + return MACSUCCESS; +} + +u32 mac_trigger_cmac1_err(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u16 val16; + u32 ret; + + ret = check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN_C1); + MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8 & (~B_AX_TMAC_EN)); + PLTFM_DELAY_MS(1); + MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8); + + val16 = MAC_REG_R16(R_AX_PTCL_IMR0_C1) | B_AX_F2PCMD_EMPTY_ERR_INT_EN; + MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16); + MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN); + + return MACSUCCESS; +} + +u32 mac_trigger_dmac_err(struct mac_ax_adapter *adapter) +{ + struct cpuio_buf_req_t buf_req; + struct cpuio_ctrl_t ctrl_para; + u32 ret; + + // Use CPUIO to enqueue packet. + //WD + buf_req.len = 0x20; + ret = mac_dle_buf_req_wd(adapter, &buf_req); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]WDE DLE buf req\n"); + return ret; + } + + // Enqueue two pkt_id, but only has one pkt_id. + PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para)); + ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; + ctrl_para.start_pktid = buf_req.pktid; + ctrl_para.end_pktid = buf_req.pktid; + ctrl_para.pkt_num = 1; + ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; + ctrl_para.dst_qid = 4; + ret = mac_set_cpuio_wd(adapter, &ctrl_para); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]WDE DLE enqueue to head\n"); + return ret; + } + return MACSUCCESS; +} + +u32 mac_dump_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info err) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ERR("--->\n err=0x%x\n", err); + if (err == MAC_AX_ERR_L1_ERR_DMAC || + err == MAC_AX_ERR_L0_PROMOTE_TO_L1 || + err == MAC_AX_ERR_L0_ERR_CMAC0 || + err == MAC_AX_ERR_L0_ERR_CMAC1) { + PLTFM_MSG_ERR("R_AX_SER_DBG_INFO =0x%08x\n", + MAC_REG_R32(R_AX_SER_DBG_INFO)); + + dump_err_status_dmac(adapter); + dump_err_status_cmac(adapter, MAC_AX_BAND_0); + dump_err_status_cmac(adapter, MAC_AX_BAND_1); + + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + PLTFM_MSG_ERR("R_AX_DBG_ERR_FLAG=0x%08x\n", + MAC_REG_R32(R_AX_DBG_ERR_FLAG)); + PLTFM_MSG_ERR("R_AX_LBC_WATCHDOG=0x%08x\n", + MAC_REG_R32(R_AX_LBC_WATCHDOG)); + } + } + PLTFM_MSG_ERR("<---\n"); + + return MACSUCCESS; +} + +u32 mac_set_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info err) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt = MAC_SET_ERR_DLY_CNT; + u32 ret = MACSUCCESS; + + if (err > MAC_AX_SET_ERR_MAX) { + PLTFM_MSG_ERR("Bad set-err-status value\n"); + return MACFUNCINPUT; + } + + PLTFM_MUTEX_LOCK(&adapter->hw_info->err_set_lock); + + while (--cnt) { + if (!MAC_REG_R32(R_AX_HALT_H2C_CTRL)) + break; + PLTFM_DELAY_US(MAC_SET_ERR_DLY_US); + } + if (!cnt) { + PLTFM_MSG_ERR("FW does not receive previous msg\n"); + ret = MACPOLLTO; + goto end; + } + + if (err == MAC_AX_ERR_L1_DISABLE_EN) + adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV_DONE; + + MAC_REG_W32(R_AX_HALT_H2C, err); + MAC_REG_W32(R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); + +end: + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_set_lock); + return ret; +} + +u32 mac_get_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info *err) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cnt = MAC_SET_ERR_DLY_CNT; + u32 ret = MACSUCCESS; + u32 error_senario = 0; + + PLTFM_MUTEX_LOCK(&adapter->hw_info->err_get_lock); + adapter->sm.l2_st = MAC_AX_L2_DIS; + + while (--cnt) { + if (MAC_REG_R32(R_AX_HALT_C2H_CTRL)) + break; + PLTFM_DELAY_US(MAC_SET_ERR_DLY_US); + } + if (!cnt) { + PLTFM_MSG_ERR("Polling FW err status fail\n"); + ret = MACPOLLTO; + goto end; + } + + *err = (enum mac_ax_err_info)MAC_REG_R32(R_AX_HALT_C2H); + MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0); + switch (*err) { + case MAC_AX_ERR_L1_ERR_DMAC: + case MAC_AX_ERR_L0_PROMOTE_TO_L1: + adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV; + break; + case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE: + adapter->sm.fw_rst = MAC_AX_FW_RESET_PROCESS; + break; + case MAC_AX_ERR_L1_RESET_RECOVERY_DONE: + adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE; + break; + default: + break; + } + + /* Decode the error status from halc2h */ + error_senario = (*err) >> DBG_SENARIO_SH; + if (!(MAC_REG_R32(R_AX_UDM0) & (1 << B_AX_UDM0_DBG_MODE_SH))) { + if (error_senario == CPU_EXCEPTION) + *err = MAC_AX_ERR_CPU_EXCEPTION; + else if (error_senario == ASSERTION) + *err = MAC_AX_ERR_ASSERTION; + } + + //3 3. Execute Recode Normal Debug Register + if (*err == MAC_AX_ERR_L0_ERR_CMAC0 || + *err == MAC_AX_ERR_L0_ERR_CMAC1) { + pltfm_dbg_dump(adapter); + } + fw_st_dbg_dump(adapter); + mac_dump_err_status(adapter, *err); + if (*err == MAC_AX_ERR_L0_ERR_CMAC0 || + *err == MAC_AX_ERR_L0_ERR_CMAC1) { + pltfm_dbg_dump(adapter); + } + + //3 4. Execute Recode Share memory debug information + if (MAC_REG_R32(R_AX_UDM0) & (1 << B_AX_UDM0_DBG_MODE_SH)) { + /* if debug mode =1 , dump share buffer */ + if (error_senario) { + *err = (enum mac_ax_err_info)MAC_AX_DUMP_SHAREBUFF_INDICATOR; + //notify phl to print share buffer + } + } +end: + adapter->sm.l2_st = MAC_AX_L2_EN; + PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_get_lock); + return ret; +} + +u32 mac_lv1_rcvy(struct mac_ax_adapter *adapter, enum mac_ax_lv1_rcvy_step step) +{ + u32 ret = MACSUCCESS; +#if MAC_AX_PCIE_SUPPORT + u8 val8; +#endif + + switch (step) { + case MAC_AX_LV1_RCVY_STEP_1: + if (adapter->sm.fw_rst != MAC_AX_FW_RESET_RECV) { + PLTFM_MSG_ERR("The rst-flow state is wrong\n"); + return MACPROCERR; + } +#if MAC_AX_PCIE_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + val8 = 0; + ret = lv1rst_stop_dma_pcie(adapter, val8); + if (ret) { + PLTFM_MSG_ERR("lv1 rcvy pcie stop dma fail\n"); + return ret; + } + } +#endif + +#if MAC_AX_USB_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + ret = usb_flush_mode(adapter, MAC_AX_FUNC_EN); + if (ret) { + PLTFM_MSG_ERR("lv1 rcvy USB flush mode fail\n"); + return ret; + } + PLTFM_DELAY_MS(30); + } +#endif + break; + + case MAC_AX_LV1_RCVY_STEP_2: + if (adapter->sm.fw_rst != MAC_AX_FW_RESET_PROCESS) { + PLTFM_MSG_ERR("The rst-flow state is wrong\n"); + return MACPROCERR; + } +#if MAC_AX_PCIE_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + val8 = 0; + ret = lv1rst_start_dma_pcie(adapter, val8); + if (ret) { + PLTFM_MSG_ERR("lv1 rcvy pcie start dma fail\n"); + return ret; + } + } +#endif + +#if MAC_AX_USB_SUPPORT + if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + ret = 0; + ret = usb_flush_mode(adapter, MAC_AX_FUNC_DIS); + if (ret) { + PLTFM_MSG_ERR("lv1 rcvy USB norm mode fail\n"); + return ret; + } + } +#endif + break; + + default: + return MACLV1STEPERR; + } + + return ret; +} + +u32 mac_err_imr_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 v32_dmac, v32_cmac0, v32_cmac1; + u32 ret = MACSUCCESS; + u8 is_dbcc; + + v32_dmac = sw != MAC_AX_FUNC_DIS ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS; + v32_cmac0 = sw != MAC_AX_FUNC_DIS ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS; + v32_cmac1 = sw != MAC_AX_FUNC_DIS ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS; + is_dbcc = is_curr_dbcc(adapter); + +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = MAC_REG_W_OFLD((u16)R_AX_DMAC_ERR_IMR, DMAC_ERR_IMR_MASK, + v32_dmac, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("dmac err imr w ofld fail\n"); + return ret; + } + + ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR, CMAC0_ERR_IMR_MASK, + v32_cmac0, (is_dbcc ? 0 : 1)); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("cmac0 err imr w ofld fail\n"); + return ret; + } + + if (is_dbcc) { + ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR_C1, + CMAC1_ERR_IMR_MASK, + v32_cmac1, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("cmac1 err imr w ofld fail\n"); + return ret; + } + } + + return ret; + } +#endif + + MAC_REG_W32(R_AX_DMAC_ERR_IMR, v32_dmac); + MAC_REG_W32(R_AX_CMAC_ERR_IMR, v32_cmac0); + + if (is_dbcc) + MAC_REG_W32(R_AX_CMAC_ERR_IMR_C1, v32_cmac1); + + return ret; +} + +static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_ISR)); + + PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x ", + MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_ISR)); +} + +static void dump_err_status_dmac(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 dmac_err; + + dmac_err = MAC_REG_R32(R_AX_DMAC_ERR_ISR); + PLTFM_MSG_ERR("R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); + + PLTFM_MSG_ERR("R_AX_DMAC_FUNC_EN =0x%08x\n", + MAC_REG_R32(R_AX_DMAC_FUNC_EN)); + PLTFM_MSG_ERR("R_AX_DMAC_CLK_EN =0x%08x\n", + MAC_REG_R32(R_AX_DMAC_CLK_EN)); + + if (dmac_err) { + PLTFM_MSG_ERR("R_AX_WDE_ERR_FLAG_CFG =0x%08x\n", + MAC_REG_R32(R_AX_WDE_ERR_FLAG_CFG)); + PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", + MAC_REG_R32(R_AX_PLE_ERR_FLAG_CFG)); + } + + if (dmac_err & B_AX_WDRLS_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_WDRLS_ERR_IMR =0x%08x\n", + MAC_REG_R32(R_AX_WDRLS_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_WDRLS_ERR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_WDRLS_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_RPQ_RXBD_IDX =0x%08x\n", + MAC_REG_R32(R_AX_RPQ_RXBD_IDX)); + } + + if (dmac_err & B_AX_WSEC_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_SEC_ERR_IMR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_SEC_DEBUG)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D00 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_ENG_CTRL)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D04 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_MPDU_PROC)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D10 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_CAM_ACCESS)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D14 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_CAM_RDATA)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D18 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_CAM_WDATA)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D20 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_TX_DEBUG)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D24 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_RX_DEBUG)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D28 =0x%08x\n", + MAC_REG_R32(R_AX_SEC_TRX_PKT_CNT)); + PLTFM_MSG_ERR("SEC_local_Register 0x9D2C =0x%08x\n", + MAC_REG_R32(R_AX_SEC_TRX_BLK_CNT)); + } + + if (dmac_err & B_AX_MPDU_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_IMR =0x%08x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_IMR =0x%08x\n", + MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_MPDU_RX_ERR_ISR)); + } + + if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_IMR =0x%08x\n", + MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", + MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_ISR)); + } + + if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_WDE_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_WDE_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_PLE_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", + MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR)); + } + + if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR)); + PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", + MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); + } + + if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_WDE_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_WDE_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_PLE_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", + MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR)); + PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_0=0x%08x\n", + MAC_REG_R32(R_AX_WD_CPUQ_OP_0)); + PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_1=0x%08x\n", + MAC_REG_R32(R_AX_WD_CPUQ_OP_1)); + PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_2=0x%08x\n", + MAC_REG_R32(R_AX_WD_CPUQ_OP_2)); + PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", + MAC_REG_R32(R_AX_WD_CPUQ_OP_STATUS)); + PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_0=0x%08x\n", + MAC_REG_R32(R_AX_PL_CPUQ_OP_0)); + PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_1=0x%08x\n", + MAC_REG_R32(R_AX_PL_CPUQ_OP_1)); + PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_2=0x%08x\n", + MAC_REG_R32(R_AX_PL_CPUQ_OP_2)); + PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", + MAC_REG_R32(R_AX_PL_CPUQ_OP_STATUS)); + PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_0=0x%08x\n", + MAC_REG_R32(R_AX_RXDMA_PKT_INFO_0)); + PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_1=0x%08x\n", + MAC_REG_R32(R_AX_RXDMA_PKT_INFO_1)); + PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_2=0x%08x\n", + MAC_REG_R32(R_AX_RXDMA_PKT_INFO_2)); + dump_err_status_dispatcher(adapter); + } + + if (dmac_err & B_AX_PKTIN_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x\n", + MAC_REG_R32(R_AX_PKTIN_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_PKTIN_ERR_ISR)); + PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x ", + MAC_REG_R32(R_AX_PKTIN_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n", + MAC_REG_R32(R_AX_PKTIN_ERR_ISR)); + } + + if (dmac_err & B_AX_DISPATCH_ERR_FLAG) + dump_err_status_dispatcher(adapter); + + if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { + PLTFM_MSG_ERR("R_AX_CPUIO_ERR_IMR=0x%08x\n", + MAC_REG_R32(R_AX_CPUIO_ERR_IMR)); + PLTFM_MSG_ERR("R_AX_CPUIO_ERR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_CPUIO_ERR_ISR)); + } + + if (dmac_err & BIT(11)) { + PLTFM_MSG_ERR("R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", + MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR)); + } +} + +static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 cmac_err; + u32 ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return; + + PLTFM_MSG_ERR("CMAC Band =0x%02x\n", band); + + cmac_err = MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_ERR_ISR : + R_AX_CMAC_ERR_ISR_C1); + PLTFM_MSG_ERR("R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); + + PLTFM_MSG_ERR("R_AX_CMAC_FUNC_EN =0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_FUNC_EN : + R_AX_CMAC_FUNC_EN_C1)); + PLTFM_MSG_ERR("R_AX_CK_EN =0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CK_EN : + R_AX_CK_EN_C1)); + + if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { + PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_IMR=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_SCHEDULE_ERR_IMR : R_AX_SCHEDULE_ERR_IMR_C1)); + PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_ISR=0x%04x\n", + MAC_REG_R16(band == MAC_AX_BAND_0 ? + R_AX_SCHEDULE_ERR_ISR : R_AX_SCHEDULE_ERR_ISR_C1)); + } + + if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { + PLTFM_MSG_ERR("R_AX_PTCL_IMR0=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_PTCL_IMR0 : R_AX_PTCL_IMR0_C1)); + PLTFM_MSG_ERR("R_AX_PTCL_ISR0=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_PTCL_ISR0 : R_AX_PTCL_ISR0_C1)); + } + + if (cmac_err & B_AX_DMA_TOP_ERR_IND) { + PLTFM_MSG_ERR("R_AX_DLE_CTRL=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_DLE_CTRL : R_AX_DLE_CTRL_C1)); + } + + if (cmac_err & B_AX_PHYINTF_ERR_IND) { + PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n", + MAC_REG_R16(band == MAC_AX_BAND_0 ? + R_AX_PHYINFO_ERR_IMR : R_AX_PHYINFO_ERR_IMR_C1)); + } + + if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { + PLTFM_MSG_ERR("R_AX_TXPWR_IMR=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_TXPWR_IMR : R_AX_TXPWR_IMR_C1)); + PLTFM_MSG_ERR("R_AX_TXPWR_ISR=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_TXPWR_ISR : R_AX_TXPWR_ISR_C1)); + } + + if (cmac_err & B_AX_WMAC_RX_ERR_IND) { + PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1)); + PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_ISR=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_PHYINFO_ERR_ISR : R_AX_PHYINFO_ERR_ISR_C1)); + } + + if (cmac_err & B_AX_WMAC_TX_ERR_IND) { + PLTFM_MSG_ERR("R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_TMAC_ERR_IMR_ISR : R_AX_TMAC_ERR_IMR_ISR_C1)); + PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n", + MAC_REG_R32(band == MAC_AX_BAND_0 ? + R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1)); + } +} + +u32 mac_ser_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + enum mac_ax_err_info err_info; + u32 val32, ret, cnt; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && is_cv(adapter, CAV)) { + PLTFM_MSG_WARN("[WARN]SER ctrl not support\n"); + return MACSUCCESS; + } + + if (sw == MAC_AX_FUNC_EN) { + err_info = MAC_AX_ERR_L1_RCVY_START_REQ; + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_SRT; + } else if (sw == MAC_AX_FUNC_DIS) { + err_info = MAC_AX_ERR_L1_RCVY_STOP_REQ; + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_STOP; + } else { + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR; + PLTFM_MSG_ERR("[ERR]SER ctrl input err %d\n", sw); + return MACFUNCINPUT; + } + + ret = mac_set_err_status(adapter, err_info); + if (ret != MACSUCCESS) { + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR; + PLTFM_MSG_ERR("[ERR]set err for stop ser %d\n", ret); + return ret; + } + + cnt = MAC_SET_ERR_DLY_CNT; + while (cnt) { + val32 = MAC_REG_R32(R_AX_HALT_H2C_CTRL); + if (!(val32 & B_AX_HALT_H2C_TRIGGER)) + break; + PLTFM_DELAY_US(MAC_SET_ERR_DLY_US); + cnt--; + } + + if (!cnt) { + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR; + PLTFM_MSG_ERR("[ERR]FW not handle haltH2C req\n"); + ret = MACPOLLTO; + return ret; + } + + if (sw == MAC_AX_FUNC_EN) + return MACSUCCESS; + + cnt = MAC_SER_STOP_DLY_CNT; + while (cnt) { + PLTFM_DELAY_US(MAC_SER_STOP_DLY_US); + val32 = MAC_REG_R32(R_AX_UDM0); + val32 = GET_FIELD(val32, FW_ST); + if (val32 != FW_ST_ERR_IN) + break; + cnt--; + } + + if (!cnt) { + adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR; + PLTFM_MSG_ERR("[ERR]stop ser polling FW ST timeout\n"); + return MACPOLLTO; + } + + return ret; +} diff --git a/phl/hal_g6/mac/mac_ax/ser.h b/phl/hal_g6/mac/mac_ax/ser.h new file mode 100644 index 0000000..4f67562 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/ser.h @@ -0,0 +1,747 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_SER_H_ +#define _MAC_AX_SER_H_ + +#include "../type.h" + +#if MAC_AX_SDIO_SUPPORT +#include "_sdio.h" +#endif + +#if MAC_AX_PCIE_SUPPORT +#include "_pcie.h" +#endif + +#if MAC_AX_USB_SUPPORT +#include "_usb.h" +#endif + +#define SER_ENABLE 0XFFFFFFFF +#define SER_DISABLE 0X00000000 + +#if defined(PHL_FEATURE_AP) +/*--------------------CMAC ERROR ----------------------------------------*/ +/*--------------------CMAC DMA IMR --------------------------------------*/ +// 0xC800 +// bit[14] +#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE +// bit[15] +#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE +// bit[23] +#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE +// 0xC828 +// bit[31] +#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE + +/*-------------------- PTCL IMR -----------------------------------------*/ +// 0xC6C0 +// bit[0] +#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[8] +#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[9] +#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[10] +#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE +// bit[11] +#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE +// bit[12] +#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE +// bit[14] +#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE +// bit[15] +#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE +// bit[23] +#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE +// bit[24] +#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE +// bit[25] +#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE +// bit[26] +#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE +// bit[27] +#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE +// bit[28] +#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE +// bit[29] +#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE +// bit[30] +#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE +// bit[31] +#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE + +/*-------------------- Scheduler IMR ------------------------------------*/ +// 0xC3E8 : 0x00000000 +// bit[0] +#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[1] +#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE + +/*-------------------- PHY INTF IMR --------------------------------------*/ +// 0xCCFE : 0x0000 +// bit[0] +#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[1] +#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[2] +#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[3] +#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[4] +#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE + +/*-------------------- RMAC IMR -----------------------------------------*/ +// 0xCEF6 +// bit[4] +#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[6] +#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[7] +#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[8] +#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[9] +#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[11] +#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE + +/*-------------------- TMAC IMR -----------------------------------------*/ +// 0xCCEC +// bit[7] +#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE +// bit[8] +#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[9] +#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE + +#elif defined(PHL_FEATURE_STA) +/*--------------------CMAC ERROR ----------------------------------------*/ +/*--------------------CMAC DMA IMR --------------------------------------*/ +// 0xC800 +// bit[14] +#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE +// bit[15] +#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE +// bit[23] +#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE +// 0xC828 +// bit[31] +#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE + +/*-------------------- PTCL IMR -----------------------------------------*/ +// 0xC6C0 +// bit[0] +#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[8] +#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[9] +#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[10] +#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE +// bit[11] +#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE +// bit[12] +#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE +// bit[14] +#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE +// bit[15] +#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE +// bit[23] +#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE +// bit[24] +#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE +// bit[25] +#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE +// bit[26] +#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE +// bit[27] +#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE +// bit[28] +#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE +// bit[29] +#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE +// bit[30] +#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE +// bit[31] +#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE + +/*-------------------- Scheduler IMR ------------------------------------*/ +// 0xC3E8 : 0x00000000 +// bit[0] +#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[1] +#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE + +/*-------------------- PHY INTF IMR --------------------------------------*/ +// 0xCCFE : 0x0000 +// bit[0] +#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[1] +#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[2] +#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[3] +#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[4] +#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE + +/*-------------------- RMAC IMR -----------------------------------------*/ +// 0xCEF6 +// bit[4] +#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[6] +#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[7] +#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[8] +#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[9] +#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[11] +#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE + +/*-------------------- TMAC IMR -----------------------------------------*/ +// 0xCCEC +// bit[7] +#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE +// bit[8] +#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[9] +#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE + +#else +/*--------------------CMAC ERROR ----------------------------------------*/ +/*--------------------CMAC DMA IMR --------------------------------------*/ +// 0xC800 +// bit[14] +#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE +// bit[15] +#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE +// bit[23] +#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE +// 0xC828 +// bit[31] +#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE + +/*-------------------- PTCL IMR -----------------------------------------*/ +// 0xC6C0 +// bit[0] +#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[8] +#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[9] +#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE +// bit[10] +#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE +// bit[11] +#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE +// bit[12] +#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE +// bit[14] +#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE +// bit[15] +#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE +// bit[23] +#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE +// bit[24] +#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE +// bit[25] +#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE +// bit[26] +#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE +// bit[27] +#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE +// bit[28] +#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE +// bit[29] +#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE +// bit[30] +#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE +// bit[31] +#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE + +/*-------------------- Scheduler IMR ------------------------------------*/ +// 0xC3E8 : 0x00000000 +// bit[0] +#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[1] +#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE + +/*-------------------- PHY INTF IMR --------------------------------------*/ +// 0xCCFE : 0x0000 +// bit[0] +#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[1] +#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[2] +#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[3] +#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[4] +#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE + +/*-------------------- RMAC IMR -----------------------------------------*/ +// 0xCEF6 +// bit[4] +#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[5] +#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[6] +#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[7] +#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[8] +#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE +// bit[9] +#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[11] +#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE + +/*-------------------- TMAC IMR -----------------------------------------*/ +// 0xCCEC +// bit[7] +#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE +// bit[8] +#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[9] +#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE +// bit[10] +#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE +#endif + +//WDRLS 0x9430 +//bit[0] +#define DMAC_WDRLS_CTL_WDPKTID_ISNULL_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_WDRLS_CTL_PLPKTID_ISNULL_ERR_SER_EN SER_ENABLE +//bit[2] +#define DMAC_WDRLS_CTL_FRZTO_ERR_SER_EN SER_ENABLE +//bit[4] +#define DMAC_WDRLS_PLEBREQ_TO_ERR_SER_EN SER_DISABLE +//bit[5] +#define DMAC_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_SER_EN SER_ENABLE +//bit[8] +#define DMAC_WDRLS_RPT0_AGGNUM0_ERR_SER_EN SER_ENABLE +//bit[9] +#define DMAC_WDRLS_RPT0_FRZTO_ERR_SER_EN SER_ENABLE +//bit[12] +#define DMAC_WDRLS_RPT1_AGGNUM0_ERR_SER_EN SER_ENABLE +//bit[13] +#define DMAC_WDRLS_RPT1_FRZTO_ERR_SER_EN SER_ENABLE + +//SEC_DEBUG 0x9D1C +//bit[3] +#define DMAC_IMR_ERROR SER_ENABLE + +//MPDU_TX_ERR_IMR 0x9BF4 +//bit[1] +#define DMAC_TX_GET_ERRPKTID_SER_EN SER_DISABLE +//bit[2] +#define DMAC_TX_NXT_ERRPKTID_SER_EN SER_DISABLE +//bit[3] +#define DMAC_TX_MPDU_SIZE_ZERO_SER_EN SER_DISABLE +//bit[4] +#define DMAC_TX_OFFSET_ERR_SER_EN SER_DISABLE +//bit[5] +#define DMAC_TX_HDR3_SIZE_ERR_SER_EN SER_DISABLE + +//MPDU_RX_ERR_IMR 0x9CF4 +//bit[0] +#define DMAC_GETPKTID_ERR_SER_EN SER_DISABLE +//bit[1] +#define DMAC_MHDRLEN_ERR_SER_EN SER_DISABLE +//bit[3] +#define DMAC_RPT_ERR_SER_EN SER_DISABLE + +//STA_SCHEDULER_ERR_IMR 0x9EF0 +//bit[0] +#define DMAC_SEARCH_HANG_TIMEOUT_SER_EN SER_ENABLE +//bit[1] +#define DMAC_RPT_HANG_TIMEOUT_SER_EN SER_ENABLE +//bit[2] +#define DMAC_PLE_B_PKTID_ERR_SER_EN SER_ENABLE + +//TXPKTCTL_ERR_IMR_ISR 0x9F1C +//bit[0] +#define DMAC_TXPKTCTL_USRCTL_REINIT_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_TXPKTCTL_USRCTL_NOINIT_ERR_SER_EN SER_DISABLE +//bit[2] +#define DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_SER_EN SER_DISABLE +//bit[3] +#define DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_SER_EN SER_DISABLE +//bit[8] +#define DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_SER_EN SER_ENABLE +//bit[9] +#define DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_SER_EN SER_DISABLE + +//TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C +//bit[0] +#define DMAC_TXPKTCTL_USRCTL_REINIT_B1_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_TXPKTCTL_USRCTL_NOINIT_B1_ERR_SER_EN SER_ENABLE +//bit[2] +#define DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_B1_ERR_SER_EN SER_DISABLE +//bit[3] +#define DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_B1_ERR_SER_EN SER_DISABLE +//bit[8] +#define DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_B1_SER_EN SER_ENABLE +//bit[9] +#define DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_B1_SER_EN SER_ENABLE + +//WDE_ERR_IMR 0x8C38 +//bit[0] +#define DMAC_WDE_BUFREQ_QTAID_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_WDE_BUFREQ_UNAVAL_ERR_SER_EN SER_ENABLE +//bit[2] +#define DMAC_WDE_BUFRTN_INVLD_PKTID_ERR_SER_EN SER_ENABLE +//bit[3] +#define DMAC_WDE_BUFRTN_SIZE_ERR_SER_EN SER_ENABLE +//bit[4] +#define DMAC_WDE_BUFREQ_SRCHTAILPG_ERR_SER_EN SER_ENABLE +//bit[5] +#define DMAC_WDE_GETNPG_STRPG_ERR_SER_EN SER_ENABLE +//bit[6] +#define DMAC_WDE_GETNPG_PGOFST_ERR_SER_EN SER_ENABLE +//bit[7] +#define DMAC_WDE_BUFMGN_FRZTO_ERR_SER_EN SER_ENABLE +//bit[12] +#define DMAC_WDE_QUE_CMDTYPE_ERR_SER_EN SER_ENABLE +//bit[13] +#define DMAC_WDE_QUE_DSTQUEID_ERR_SER_EN SER_ENABLE +//bit[14] +#define DMAC_WDE_QUE_SRCQUEID_ERR_SER_EN SER_ENABLE +//bit[15] +#define DMAC_WDE_ENQ_PKTCNT_OVRF_ERR_SER_EN SER_ENABLE +//bit[16] +#define DMAC_WDE_ENQ_PKTCNT_NVAL_ERR_SER_EN SER_ENABLE +//bit[17] +#define DMAC_WDE_PREPKTLLT_AD_ERR_SER_EN SER_ENABLE +//bit[18] +#define DMAC_WDE_NXTPKTLL_AD_ERR_SER_EN SER_ENABLE +//bit[19] +#define DMAC_WDE_QUEMGN_FRZTO_ERR_SER_EN SER_ENABLE +//bit[24] +#define DMAC_WDE_DATCHN_ARBT_ERR_SER_EN SER_ENABLE +//bit[25] +#define DMAC_WDE_DATCHN_NULLPG_ERR_SER_EN SER_ENABLE +//bit[26] +#define DMAC_WDE_DATCHN_FRZTO_ERR_SER_EN SER_ENABLE + +//PLE_ERR_IMR 0x9038 +//bit[0] +#define DMAC_PLE_BUFREQ_QTAID_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_PLE_BUFREQ_UNAVAL_ERR_SER_EN SER_ENABLE +//bit[2] +#define DMAC_PLE_BUFRTN_INVLD_PKTID_ERR_SER_EN SER_ENABLE +//bit[3] +#define DMAC_PLE_BUFRTN_SIZE_ERR_SER_EN SER_ENABLE +//bit[4] +#define DMAC_PLE_BUFREQ_SRCHTAILPG_ERR_SER_EN SER_ENABLE +//bit[5] +#define DMAC_PLE_GETNPG_STRPG_ERR_SER_EN SER_DISABLE +//bit[6] +#define DMAC_PLE_GETNPG_PGOFST_ERR_SER_EN SER_ENABLE +//bit[7] +#define DMAC_PLE_BUFMGN_FRZTO_ERR_SER_EN SER_ENABLE +//bit[12] +#define DMAC_PLE_QUE_CMDTYPE_ERR_SER_EN SER_ENABLE +//bit[13] +#define DMAC_PLE_QUE_DSTQUEID_ERR_SER_EN SER_ENABLE +//bit[14] +#define DMAC_PLE_QUE_SRCQUEID_ERR_SER_EN SER_ENABLE +//bit[15] +#define DMAC_PLE_ENQ_PKTCNT_OVRF_ERR_SER_EN SER_ENABLE +//bit[16] +#define DMAC_PLE_ENQ_PKTCNT_NVAL_ERR_SER_EN SER_ENABLE +//bit[17] +#define DMAC_PLE_PREPKTLLT_AD_ERR_SER_EN SER_ENABLE +//bit[18] +#define DMAC_PLE_NXTPKTLL_AD_ERR_SER_EN SER_ENABLE +//bit[19] +#define DMAC_PLE_QUEMGN_FRZTO_ERR_SER_EN SER_ENABLE +//bit[24] +#define DMAC_PLE_DATCHN_ARBT_ERR_SER_EN SER_ENABLE +//bit[25] +#define DMAC_PLE_DATCHN_NULLPG_ERR_SER_EN SER_ENABLE +//bit[26] +#define DMAC_PLE_DATCHN_FRZTO_ERR_SER_EN SER_ENABLE + +//PKTIN_ERR_IMR 0x9A20 +//bit[0] +#define DMAC_PKTIN_GETPKTID_ERR_SER_EN SER_ENABLE + +//HOST_DISPATCHER_ERR_IMR 0x8850 +//bit[0] +#define DMAC_HDT_CHANNEL_DIFF_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_HDT_CHANNEL_ID_ERR_SER_EN SER_DISABLE +//bit[2] +#define DMAC_HDT_PKT_FAIL_DBG_SER_EN SER_DISABLE +//bit[3] +#define DMAC_HDT_PERMU_OVERFLOW_SER_EN SER_DISABLE +//bit[4] +#define DMAC_HDT_PERMU_UNDERFLOW_SER_EN SER_DISABLE +//bit[5] +#define DMAC_HDT_PAYLOAD_OVERFLOW_SER_EN SER_ENABLE +//bit[6] +#define DMAC_HDT_PAYLOAD_UNDERFLOW_SER_EN SER_ENABLE +//bit[7] +#define DMAC_HDT_OFFSET_UNMATCH_SER_EN SER_DISABLE +//bit[8] +#define DMAC_HDT_CHANNEL_DMA_ERR_SER_EN SER_ENABLE +//bit[9] +#define DMAC_HDT_WD_CHK_ERR_SER_EN SER_DISABLE +//bit[10] +#define DMAC_HDT_PRE_COST_ERR_SER_EN SER_DISABLE +//bit[11] +#define DMAC_HDT_TXPKTSIZE_ERR_SER_EN SER_DISABLE +//bit[12] +#define DMAC_HDT_TCP_CHK_ERR_SER_EN SER_DISABLE +//bit[13] +#define DMAC_HDT_TX_WRITE_OVERFLOW_SER_EN SER_DISABLE +//bit[14] +#define DMAC_HDT_TX_WRITE_UNDERFLOW_SER_EN SER_DISABLE +//bit[15] +#define DMAC_HDT_PLD_CMD_OVERLOW_SER_EN SER_DISABLE +//bit[16] +#define DMAC_HDT_PLD_CMD_UNDERFLOW_SER_EN SER_DISABLE +//bit[17] +#define DMAC_HDT_FLOW_CTRL_ERR_SER_EN SER_DISABLE +//bit[18] +#define DMAC_HDT_NULLPKT_ERR_SER_EN SER_DISABLE +//bit[19] +#define DMAC_HDT_BURST_NUM_ERR_SER_EN SER_DISABLE +//bit[24] +#define DMAC_HDT_RXAGG_CFG_ERR_SER_EN SER_DISABLE +//bit[25] +#define DMAC_HDT_SHIFT_EN_ERR_SER_EN SER_DISABLE +//bit[26] +#define DMAC_HDT_TOTAL_LEN_ERR_SER_EN SER_ENABLE +//bit[27] +#define DMAC_HDT_DMA_PROCESS_ERR_SER_EN SER_ENABLE +//bit[28] +#define DMAC_HDT_SHIFT_DMA_CFG_ERR_SER_EN SER_DISABLE +//bit[29] +#define DMAC_HDT_CHKSUM_FSM_ERR_SER_EN SER_DISABLE +//bit[30] +#define DMAC_HDT_RX_WRITE_OVERFLOW_SER_EN SER_DISABLE +//bit[31] +#define DMAC_HDT_RX_WRITE_UNDERFLOW_SER_EN SER_DISABLE + +//CPU_DISPATCHER_ERR_IMR 0x8854 +//bit[0] +#define DMAC_CPU_CHANNEL_DIFF_ERR_SER_EN SER_DISABLE +//bit[1] +#define DMAC_CPU_PKT_FAIL_DBG_SER_EN SER_ENABLE +//bit[2] +#define DMAC_CPU_CHANNEL_ID_ERR_SER_EN SER_DISABLE +//bit[3] +#define DMAC_CPU_PERMU_OVERFLOW_SER_EN SER_DISABLE +//bit[4] +#define DMAC_CPU_PERMU_UNDERFLOW_SER_EN SER_DISABLE +//bit[5] +#define DMAC_CPU_PAYLOAD_OVERFLOW_SER_EN SER_ENABLE +//bit[6] +#define DMAC_CPU_PAYLOAD_UNDERFLOW_SER_EN SER_ENABLE +//bit[7] +#define DMAC_CPU_PAYLOAD_CHKSUM_ERR_SER_EN SER_DISABLE +//bit[8] +#define DMAC_CPU_OFFSET_UNMATCH_SER_EN SER_DISABLE +//bit[9] +#define DMAC_CPU_CHANNEL_DMA_ERR_SER_EN SER_DISABLE +//bit[10] +#define DMAC_CPU_WD_CHK_ERR_SER_EN SER_DISABLE +//bit[11] +#define DMAC_CPU_PRE_COST_ERR_SER_EN SER_DISABLE +//bit[12] +#define DMAC_CPU_PLD_CMD_OVERLOW_SER_EN SER_DISABLE +//bit[13] +#define DMAC_CPU_PLD_CMD_UNDERFLOW_SER_EN SER_DISABLE +//bit[14] +#define DMAC_CPU_F2P_QSEL_ERR_SER_EN SER_DISABLE +//bit[15] +#define DMAC_CPU_F2P_SEQ_ERR_SER_EN SER_DISABLE +//bit[16] +#define DMAC_CPU_FLOW_CTRL_ERR_SER_EN SER_DISABLE +//bit[17] +#define DMAC_CPU_NULLPKT_ERR_SER_EN SER_DISABLE +//bit[18] +#define DMAC_CPU_BURST_NUM_ERR_SER_EN SER_DISABLE +//bit[24] +#define DMAC_CPU_RXAGG_CFG_ERR_SER_EN SER_DISABLE +//bit[25] +#define DMAC_CPU_SHIFT_EN_ERR_SER_EN SER_DISABLE +//bit[26] +#define DMAC_CPU_TOTAL_LEN_ERR_SER_EN SER_ENABLE +//bit[27] +#define DMAC_CPU_DMA_PROCESS_ERR_SER_EN SER_DISABLE +//bit[28] +#define DMAC_CPU_SHIFT_DMA_CFG_ERR_SER_EN SER_DISABLE +//bit[29] +#define DMAC_CPU_CHKSUM_FSM_ERR_SER_EN SER_DISABLE + +//OTHER_DISPATCHER_ERR_IMR 0x8858 +//bit[0] +#define DMAC_WDE_FLOW_CTRL_ERR_SER_EN SER_DISABLE +//bit[1] +#define DMAC_WDE_NULL_PKT_ERR_SER_EN SER_DISABLE +//bit[2] +#define DMAC_WDE_BURST_NUM_ERR_SER_EN SER_DISABLE +//bit[3] +#define DMAC_WDE_RESP_ERR_SER_EN SER_DISABLE +//bit[4] +#define DMAC_WDE_OUTPUT_ERR_SER_EN SER_DISABLE +//bit[8] +#define DMAC_PLE_FLOW_CTRL_ERR_SER_EN SER_DISABLE +//bit[9] +#define DMAC_PLE_NULL_PKT_ERR_SER_EN SER_DISABLE +//bit[10] +#define DMAC_PLE_BURST_NUM_ERR_SER_EN SER_DISABLE +//bit[11] +#define DMAC_PLE_RESP_ERR_SER_EN SER_DISABLE +//bit[12] +#define DMAC_PLE_OUTPUT_ERR_SER_EN SER_DISABLE +//bit[16] +#define DMAC_CPU_ADDR_INFO_LEN_ZERO_ERR_SER_EN SER_DISABLE +//bit[17] +#define DMAC_HOST_ADDR_INFO_LEN_ZERO_ERR_SER_EN SER_DISABLE +//bit[24] +#define DMAC_OTHER_STF_CMD_OVERFLOW_SER_EN SER_DISABLE +//bit[25] +#define DMAC_OTHER_STF_CMD_UNDERFLOW_SER_EN SER_DISABLE +//bit[26] +#define DMAC_OTHER_STF_WRFF_OVERFLOW_SER_EN SER_DISABLE +//bit[27] +#define DMAC_OTHER_STF_WRFF_UNDERFLOW_SER_EN SER_DISABLE +//bit[28] +#define DMAC_OTHER_STF_WROQT_OVERFLOW_SER_EN SER_DISABLE +//bit[29] +#define DMAC_OTHER_STF_WROQT_UNDERFLOW_SER_EN SER_DISABLE + +//CPUIO_ERR_IMR 0x9840 +//bit[0] +#define DMAC_WDEBUF_OP_ERR_SER_EN SER_ENABLE +//bit[4] +#define DMAC_WDEQUE_OP_ERR_SER_EN SER_ENABLE +//bit[8] +#define DMAC_PLEBUF_OP_ERR_SER_EN SER_ENABLE +//bit[12] +#define DMAC_PLEQUE_OP_ERR_SER_EN SER_ENABLE + +//BBRPT_COM_ERR_IMR_ISR 0x960C +//bit[0] +#define DMAC_BBRPT_COM_NULL_PLPKTID_ERR_SER_EN SER_ENABLE + +//BBRPT_CHINFO_ERR_IMR_ISR 0x962C +//bit[0] +#define DMAC_BBPRT_CHIF_BB_TO_ERR_SER_EN SER_ENABLE +//bit[1] +#define DMAC_BBPRT_CHIF_OVF_ERR_SER_EN SER_ENABLE +//bit[2] +#define DMAC_BBPRT_CHIF_BOVF_ERR_SER_EN SER_ENABLE +//bit[3] +#define DMAC_BBPRT_CHIF_HDRL_ERR_SER_EN SER_ENABLE +//bit[4] +#define DMAC_BBPRT_CHIF_LEFT1_ERR_SER_EN SER_ENABLE +//bit[5] +#define DMAC_BBPRT_CHIF_LEFT2_ERR_SER_EN SER_ENABLE +//bit[6] +#define DMAC_BBPRT_CHIF_NULL_ERR_SER_EN SER_ENABLE +//bit[7] +#define DMAC_BBPRT_CHIF_TO_ERR_SER_EN SER_ENABLE + +//BBRPT_DFS_ERR_IMR_ISR 0x963C +//bit[0] +#define DMAC_BBRPT_DFS_TO_ERR_SER_EN SER_ENABLE + +//LA_ERRFLAG 0x966C +//bit[0] +#define DMAC_LA_IMR_DATA_LOSS_ERR SER_ENABLE + +/*--------------------Define -------------------------------------------*/ +#define MAC_SET_ERR_DLY_CNT 200 +#define MAC_SET_ERR_DLY_US 50 + +#define DMAC_ERR_IMR_MASK 0xFFFFFFFF +#define DMAC_ERR_IMR_EN 0xFFFFFFFF +#define CMAC0_ERR_IMR_MASK 0xFFFFFFFF +#define CMAC0_ERR_IMR_EN 0xFFFFFFFF +#define CMAC1_ERR_IMR_MASK 0xFFFFFFFF +#define CMAC1_ERR_IMR_EN 0xFFFFFFFF +#define DMAC_ERR_IMR_DIS 0 +#define CMAC0_ERR_IMR_DIS 0 +#define CMAC1_ERR_IMR_DIS 0 + +#define FW_ST_MSK 0xFFFF +#define FW_ST_SH 8 +#define FW_ST_ERR_IN 0x11 + +#define MAC_SER_STOP_DLY_CNT 200 +#define MAC_SER_STOP_DLY_US 50 + +/*--------------------Define Enum---------------------------------------*/ +enum WCPU_ERR_SCENARIO { + RXI300_ERROR = 1, + CPU_EXCEPTION = 2, + ASSERTION = 3, + WDT_ALARM = 4, +}; + +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Struct-------------------------------------*/ +/*--------------------Function declaration------------------------------*/ +u32 mac_trigger_cmac_err(struct mac_ax_adapter *adapter); +u32 mac_trigger_cmac1_err(struct mac_ax_adapter *adapter); +u32 mac_trigger_dmac_err(struct mac_ax_adapter *adapter); + +u32 mac_dump_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info err); +u32 mac_set_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info err); +u32 mac_get_err_status(struct mac_ax_adapter *adapter, + enum mac_ax_err_info *err); + +u32 mac_lv1_rcvy(struct mac_ax_adapter *adapter, + enum mac_ax_lv1_rcvy_step step); + +u32 mac_err_imr_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw); +u32 mac_ser_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/sounding.c b/phl/hal_g6/mac/mac_ax/sounding.c new file mode 100644 index 0000000..905e48b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/sounding.c @@ -0,0 +1,1999 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "sounding.h" + +u32 mac_get_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band, + u8 csi_buffer_id) +{ + u32 val32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + if (csi_buffer_id > CSI_MAX_BUFFER_IDX) + return MACCSIBUFIDERR; + + val32 = MAC_REG_R32((band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 : + R_AX_BFMER_CSI_BUFF_IDX0) + CSI_SH * csi_buffer_id); + return val32; +} + +u32 mac_set_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band, + u8 macid, u16 csi_buffer_id, u16 buffer_idx) +{ + u32 val32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + +#if MAC_AX_FW_REG_OFLD + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + if (csi_buffer_id > CSI_MAX_BUFFER_IDX) + return MACCSIBUFIDERR; + + cr = (band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 : + R_AX_BFMER_CSI_BUFF_IDX0) + (CSI_SH * csi_buffer_id); + val32 = (buffer_idx & B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK) + << B_AX_MER_SND_CSI_BUFF_IDX0_SH | + (macid & B_AX_MER_CSI_BUFF_MACID_IDX0_MSK); + + ret = MAC_REG_W32_OFLD(cr, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + if (csi_buffer_id > CSI_MAX_BUFFER_IDX) + return MACCSIBUFIDERR; + + val32 = (buffer_idx & B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK) + << B_AX_MER_SND_CSI_BUFF_IDX0_SH | + (macid & B_AX_MER_CSI_BUFF_MACID_IDX0_MSK); + + MAC_REG_W32((band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 : + R_AX_BFMER_CSI_BUFF_IDX0) + CSI_SH * csi_buffer_id, val32); + + return MACSUCCESS; +} + +u32 mac_get_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 index) +{ + u32 va32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (index > SOUNDING_STS_MAX_IDX) + return MACSNDSTSIDERR; + + va32 = MAC_REG_R16((band ? R_AX_BFMER_ASSOCIATED_SU0_C1 : + R_AX_BFMER_ASSOCIATED_SU0) + SND_SH * index); + return va32; +} + +u32 mac_set_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 macid, + u8 index) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + +#if MAC_AX_FW_REG_OFLD + u16 cr, val16; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (index > SOUNDING_STS_MAX_IDX) + return MACSNDSTSIDERR; + + cr = (band ? R_AX_BFMER_ASSOCIATED_SU0_C1 : + R_AX_BFMER_ASSOCIATED_SU0) + (SND_SH * index); + val16 = B_AX_MER_SU_BFMEE0_EN | macid; + + ret = MAC_REG_W16_OFLD(cr, val16, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (index > SOUNDING_STS_MAX_IDX) + return MACSNDSTSIDERR; + + MAC_REG_W16((band ? R_AX_BFMER_ASSOCIATED_SU0_C1 : + R_AX_BFMER_ASSOCIATED_SU0) + SND_SH * index, + B_AX_MER_SU_BFMEE0_EN | macid); + return MACSUCCESS; +} + +u32 mac_init_snd_mer(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + +#if MAC_AX_FW_REG_OFLD + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0; + val32 = B_AX_BFMER_NDP_BFEN; + val32 |= HT_PAYLOAD_OFFSET << B_AX_BFMER_HT_CSI_OFFSET_SH; + val32 |= VHT_PAYLOAD_OFFSET << B_AX_BFMER_VHT_CSI_OFFSET_SH; + val32 |= HE_PAYLOAD_OFFSET << B_AX_BFMER_HE_CSI_OFFSET_SH; + + ret = MAC_REG_W32_OFLD(cr, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = B_AX_BFMER_NDP_BFEN; + val32 |= HT_PAYLOAD_OFFSET << B_AX_BFMER_HT_CSI_OFFSET_SH; + val32 |= VHT_PAYLOAD_OFFSET << B_AX_BFMER_VHT_CSI_OFFSET_SH; + val32 |= HE_PAYLOAD_OFFSET << B_AX_BFMER_HE_CSI_OFFSET_SH; + MAC_REG_W32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0, val32); + return MACSUCCESS; +} + +u32 mac_init_snd_mee(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + +#if MAC_AX_FW_REG_OFLD + u32 mask; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : R_AX_TRXPTCL_RESP_CSI_RRSC; + val32 = CSI_RRSC_BMAP; + + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = band ? R_AX_BFMEE_RESP_OPTION_C1 : R_AX_BFMEE_RESP_OPTION; + val32 = (BFRP_RX_STANDBY_TIMER << B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH); + val32 |= (NDP_RX_STANDBY_TIMER << B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH); + val32 |= (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | + B_AX_BFMEE_HE_NDPA_EN); + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + cr = band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 : + R_AX_TRXPTCL_ERROR_INDICA_MASK; + mask = B_AX_RMAC_CSI; + ret = write_mac_reg_ofld(adapter, cr, mask, 0, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", + __func__, cr); + return ret; + } + } + + cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0; + val32 = (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS | + B_AX_BFMEE_CSI_GID_SEL | B_AX_BFMEE_CSI_FORCE_RETE_EN); + ret = MAC_REG_W32_OFLD(cr, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + /*AP mode set tx gid to 63*/ + /*STA mode set tx gid to 0(default)*/ + val32 = MAC_REG_R32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0); + val32 |= B_AX_BFMER_NDP_BFEN; + MAC_REG_W32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0, val32); + + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : + R_AX_TRXPTCL_RESP_CSI_RRSC, CSI_RRSC_BMAP); + + val32 = (BFRP_RX_STANDBY_TIMER << B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH); + val32 |= (NDP_RX_STANDBY_TIMER << B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH); + val32 |= (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | + B_AX_BFMEE_HE_NDPA_EN); + MAC_REG_W32(band ? R_AX_BFMEE_RESP_OPTION_C1 : + R_AX_BFMEE_RESP_OPTION, val32); + + val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0); + val32 |= (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS | + B_AX_BFMEE_CSI_GID_SEL | B_AX_BFMEE_CSI_FORCE_RETE_EN); + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 : + R_AX_TRXPTCL_ERROR_INDICA_MASK); + val32 &= (~B_AX_RMAC_CSI); + MAC_REG_W32(band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 : + R_AX_TRXPTCL_ERROR_INDICA_MASK, val32); + } + return MACSUCCESS; +} + +u32 mac_csi_force_rate(struct mac_ax_adapter *adapter, u8 band, u8 ht_rate, + u8 vht_rate, u8 he_rate) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + +#if MAC_AX_FW_REG_OFLD + u32 mask; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : R_AX_TRXPTCL_RESP_CSI_CTRL_0; + mask = B_AX_BFMEE_CSI_FORCE_RETE_EN; + ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + mask = B_AX_BFMEE_BFPARAM_SEL; + ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = band ? R_AX_TRXPTCL_RESP_CSI_RATE_C1 : R_AX_TRXPTCL_RESP_CSI_RATE; + mask |= B_AX_BFMEE_HT_CSI_RATE_MSK; + mask |= B_AX_BFMEE_VHT_CSI_RATE_MSK << B_AX_BFMEE_VHT_CSI_RATE_SH; + mask |= B_AX_BFMEE_HE_CSI_RATE_MSK << B_AX_BFMEE_HE_CSI_RATE_SH; + val32 = ((u32)ht_rate | ((u32)vht_rate << B_AX_BFMEE_VHT_CSI_RATE_SH) | + ((u32)he_rate << B_AX_BFMEE_HE_CSI_RATE_SH)); + ret = write_mac_reg_ofld(adapter, cr, mask, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0); + val32 |= B_AX_BFMEE_CSI_FORCE_RETE_EN | B_AX_BFMEE_BFPARAM_SEL; + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32); + + val32 = ((u32)ht_rate | ((u32)vht_rate << B_AX_BFMEE_VHT_CSI_RATE_SH) | + ((u32)he_rate << B_AX_BFMEE_HE_CSI_RATE_SH)); + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RATE_C1 : + R_AX_TRXPTCL_RESP_CSI_RATE, val32); + return MACSUCCESS; +} + +u32 mac_csi_rrsc(struct mac_ax_adapter *adapter, u8 band, u32 rrsc) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + +#if MAC_AX_FW_REG_OFLD + u32 mask; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : R_AX_TRXPTCL_RESP_CSI_CTRL_0; + mask = B_AX_BFMEE_CSI_FORCE_RETE_EN; + ret = write_mac_reg_ofld(adapter, cr, mask, 0, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + mask = B_AX_BFMEE_BFPARAM_SEL; + ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : R_AX_TRXPTCL_RESP_CSI_RRSC; + val32 = rrsc; + ret = MAC_REG_W32_OFLD(cr, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0); + val32 |= B_AX_BFMEE_BFPARAM_SEL; + val32 &= (~B_AX_BFMEE_CSI_FORCE_RETE_EN); + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32); + MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : + R_AX_TRXPTCL_RESP_CSI_RRSC, rrsc); + return MACSUCCESS; +} + +u32 mac_set_mu_table(struct mac_ax_adapter *adapter, + struct mac_mu_table *mu_table) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + +#if MAC_AX_FW_REG_OFLD + u32 val32, ret; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + cr = R_AX_SS_MU_CTRL; + val32 = mu_table->mu_score_tbl_ctrl; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_0; + val32 = mu_table->mu_score_tbl_0; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_1; + val32 = mu_table->mu_score_tbl_1; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_2; + val32 = mu_table->mu_score_tbl_2; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_3; + val32 = mu_table->mu_score_tbl_3; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_4; + val32 = mu_table->mu_score_tbl_4; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = R_AX_SS_MU_TBL_5; + val32 = mu_table->mu_score_tbl_5; + ret = MAC_REG_W32_OFLD(cr, val32, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + MAC_REG_W32(R_AX_SS_MU_CTRL, mu_table->mu_score_tbl_ctrl); + MAC_REG_W32(R_AX_SS_MU_TBL_0, mu_table->mu_score_tbl_0); + MAC_REG_W32(R_AX_SS_MU_TBL_1, mu_table->mu_score_tbl_1); + MAC_REG_W32(R_AX_SS_MU_TBL_2, mu_table->mu_score_tbl_2); + MAC_REG_W32(R_AX_SS_MU_TBL_3, mu_table->mu_score_tbl_3); + MAC_REG_W32(R_AX_SS_MU_TBL_4, mu_table->mu_score_tbl_4); + MAC_REG_W32(R_AX_SS_MU_TBL_5, mu_table->mu_score_tbl_5); + return MACSUCCESS; +} + +u32 mac_set_snd_para(struct mac_ax_adapter *adapter, + struct mac_ax_fwcmd_snd *snd_info) +{ +#define MAX_FWCMD_SND_LEN 600 + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_set_snd_para *h2c; + + switch (snd_info->frexgtype) { + case FRAME_EXCHANGE_SND_N_SU: + snd_info->wd[0].txpktsize = 31; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].ndpa = 1; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].snd_pkt_sel = 2; + snd_info->wd[1].ndpa = 1; + + break; + case FRAME_EXCHANGE_SND_AC_SU: + snd_info->wd[0].txpktsize = 19; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].ndpa = 2; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].snd_pkt_sel = 2; + snd_info->wd[1].ndpa = 2; + + break; + case FRAME_EXCHANGE_SND_AC_MU_BFRP1: + snd_info->wd[0].txpktsize = 21; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].snd_pkt_sel = 1; + snd_info->wd[0].ndpa = 2; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 3; + snd_info->wd[1].ndpa = 2; + + snd_info->wd[2].txpktsize = 17; + snd_info->wd[2].stf_mode = 1; + snd_info->wd[2].disdatafb = 1; + snd_info->wd[2].data_txcnt_lmt_sel = 1; + snd_info->wd[2].data_txcnt_lmt = 1; + snd_info->wd[2].snd_pkt_sel = 5; + snd_info->wd[2].ndpa = 2; + + break; + case FRAME_EXCHANGE_SND_AC_MU_BFRP2: + snd_info->wd[0].txpktsize = 23; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].snd_pkt_sel = 1; + snd_info->wd[0].ndpa = 2; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 3; + snd_info->wd[1].ndpa = 2; + + snd_info->wd[2].txpktsize = 17; + snd_info->wd[2].stf_mode = 1; + snd_info->wd[2].disdatafb = 1; + snd_info->wd[2].data_txcnt_lmt_sel = 1; + snd_info->wd[2].data_txcnt_lmt = 1; + snd_info->wd[2].sifs_tx = 1; + snd_info->wd[2].snd_pkt_sel = 4; + snd_info->wd[2].ndpa = 2; + + snd_info->wd[3].txpktsize = 17; + snd_info->wd[3].stf_mode = 1; + snd_info->wd[3].disdatafb = 1; + snd_info->wd[3].data_txcnt_lmt_sel = 1; + snd_info->wd[3].data_txcnt_lmt = 1; + snd_info->wd[3].snd_pkt_sel = 5; + snd_info->wd[3].ndpa = 2; + + break; + case FRAME_EXCHANGE_SND_AC_MU_BFRP3: + snd_info->wd[0].txpktsize = 25; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].snd_pkt_sel = 1; + snd_info->wd[0].ndpa = 2; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 3; + snd_info->wd[1].ndpa = 2; + + snd_info->wd[2].txpktsize = 17; + snd_info->wd[2].stf_mode = 1; + snd_info->wd[2].disdatafb = 1; + snd_info->wd[2].data_txcnt_lmt_sel = 1; + snd_info->wd[2].data_txcnt_lmt = 1; + snd_info->wd[2].sifs_tx = 1; + snd_info->wd[2].snd_pkt_sel = 4; + snd_info->wd[2].ndpa = 2; + + snd_info->wd[3].txpktsize = 17; + snd_info->wd[3].stf_mode = 1; + snd_info->wd[3].disdatafb = 1; + snd_info->wd[3].data_txcnt_lmt_sel = 1; + snd_info->wd[3].data_txcnt_lmt = 1; + snd_info->wd[3].sifs_tx = 1; + snd_info->wd[3].snd_pkt_sel = 4; + snd_info->wd[3].ndpa = 2; + + snd_info->wd[4].txpktsize = 17; + snd_info->wd[4].stf_mode = 1; + snd_info->wd[4].disdatafb = 1; + snd_info->wd[4].data_txcnt_lmt_sel = 1; + snd_info->wd[4].data_txcnt_lmt = 1; + snd_info->wd[4].snd_pkt_sel = 5; + snd_info->wd[4].ndpa = 2; + + break; + case FRAME_EXCHANGE_SND_AX_SU: + snd_info->wd[0].txpktsize = 21; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].ndpa = 3; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 2; + snd_info->wd[1].ndpa = 3; + + break; + case FRAME_EXCHANGE_SND_AX_MU_BFRP1: + snd_info->wd[0].txpktsize = 17 + 4 * snd_info->bfrp0_user_num; + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].snd_pkt_sel = 1; + snd_info->wd[0].ndpa = 3; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 3; + snd_info->wd[1].ndpa = 3; + + snd_info->wd[2].txpktsize = 24 + 6 * snd_info->bfrp0_user_num; + snd_info->wd[2].stf_mode = 1; + snd_info->wd[2].disdatafb = 1; + snd_info->wd[2].data_txcnt_lmt_sel = 1; + snd_info->wd[2].data_txcnt_lmt = 1; + snd_info->wd[2].snd_pkt_sel = 5; + snd_info->wd[2].ndpa = 3; + + break; + case FRAME_EXCHANGE_SND_AX_MU_BFRP2: + snd_info->wd[0].txpktsize = 17 + 4 * (snd_info->bfrp0_user_num + + snd_info->bfrp1_user_num); + snd_info->wd[0].stf_mode = 1; + snd_info->wd[0].disdatafb = 1; + snd_info->wd[0].data_txcnt_lmt_sel = 1; + snd_info->wd[0].data_txcnt_lmt = 1; + snd_info->wd[0].sifs_tx = 1; + snd_info->wd[0].snd_pkt_sel = 1; + snd_info->wd[0].ndpa = 3; + + snd_info->wd[1].stf_mode = 1; + snd_info->wd[1].disdatafb = 1; + snd_info->wd[1].data_txcnt_lmt_sel = 1; + snd_info->wd[1].data_txcnt_lmt = 1; + snd_info->wd[1].sifs_tx = 1; + snd_info->wd[1].snd_pkt_sel = 3; + snd_info->wd[1].ndpa = 3; + + snd_info->wd[2].txpktsize = 24 + 6 * snd_info->bfrp0_user_num; + snd_info->wd[2].stf_mode = 1; + snd_info->wd[2].disdatafb = 1; + snd_info->wd[2].data_txcnt_lmt_sel = 1; + snd_info->wd[2].data_txcnt_lmt = 1; + snd_info->wd[2].sifs_tx = 1; + snd_info->wd[2].snd_pkt_sel = 4; + snd_info->wd[2].ndpa = 3; + + snd_info->wd[3].txpktsize = 24 + 6 * snd_info->bfrp1_user_num; + snd_info->wd[3].stf_mode = 1; + snd_info->wd[3].disdatafb = 1; + snd_info->wd[3].data_txcnt_lmt_sel = 1; + snd_info->wd[3].data_txcnt_lmt = 1; + snd_info->wd[3].snd_pkt_sel = 5; + snd_info->wd[3].ndpa = 3; + + break; + default: + return MACNOTSUP; + } + + // check input valid + if (snd_info->sfp.f2p_type > SNDF2P_DEL) { + PLTFM_MSG_ERR("Unrecognized SND F2P type: %d\n", snd_info->sfp.f2p_type); + return MACFUNCINPUT; + } + if (snd_info->sfp.f2p_index >= MAX_SNDTXCMDINFO_NUM) { + PLTFM_MSG_ERR("Unrecognized SND F2P index: %d\n", snd_info->sfp.f2p_index); + return MACFUNCINPUT; + } + if (snd_info->sfp.f2p_type == SNDF2P_ADD && snd_info->sfp.f2p_period == 0) { + PLTFM_MSG_ERR("Unrecognized SND F2P period: %d\n", snd_info->sfp.f2p_period); + return MACFUNCINPUT; + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, MAX_FWCMD_SND_LEN); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMSET(buf, 0, MAX_FWCMD_SND_LEN); + h2c = (struct fwcmd_set_snd_para *)buf; + + h2c->dword0 = + cpu_to_le32(SET_WORD(snd_info->frexgtype, + FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE) | + SET_WORD(snd_info->mode, FWCMD_H2C_SET_SND_PARA_MODE) | + SET_WORD(snd_info->bfrp0_user_num, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM) | + SET_WORD(snd_info->bfrp1_user_num, + FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM)); + h2c->dword1 = + cpu_to_le32(SET_WORD(snd_info->macid[0], FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->macid[1], FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->macid[2], FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->macid[3], FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword2 = + cpu_to_le32(SET_WORD(snd_info->macid[4], FWCMD_H2C_SET_SND_PARA_MACID4) | + SET_WORD(snd_info->macid[5], FWCMD_H2C_SET_SND_PARA_MACID5) | + SET_WORD(snd_info->macid[6], FWCMD_H2C_SET_SND_PARA_MACID6) | + SET_WORD(snd_info->macid[7], FWCMD_H2C_SET_SND_PARA_MACID7)); + h2c->dword3 = + cpu_to_le32(SET_WORD(snd_info->pndpa.common.frame_ctl, + FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL) | + SET_WORD(snd_info->pndpa.common.duration, + FWCMD_H2C_SET_SND_PARA_NDPA_DURATION)); + h2c->dword4 = + cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr1[0], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pndpa.common.addr1[1], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pndpa.common.addr1[2], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pndpa.common.addr1[3], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword5 = + cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr1[4], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pndpa.common.addr1[5], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pndpa.common.addr2[0], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pndpa.common.addr2[1], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword6 = + cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr2[2], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pndpa.common.addr2[3], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pndpa.common.addr2[4], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pndpa.common.addr2[5], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword7 = + cpu_to_le32((snd_info->pndpa.snd_dialog.he ? + FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_HE : 0) | + SET_WORD(snd_info->pndpa.snd_dialog.dialog, + FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG)); + h2c->dword8 = + cpu_to_le32(SET_WORD(snd_info->pndpa.ht_para.addr3[0], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pndpa.ht_para.addr3[1], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pndpa.ht_para.addr3[2], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pndpa.ht_para.addr3[3], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword9 = + cpu_to_le32(SET_WORD(snd_info->pndpa.ht_para.addr3[4], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pndpa.ht_para.addr3[5], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pndpa.ht_para.seq_control, + FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL)); + h2c->dword10 = + cpu_to_le32(SET_WORD(snd_info->pndpa.vht_para.sta_info[0].aid, + FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12) | + (snd_info->pndpa.vht_para.sta_info[0].fb_type ? + FWCMD_H2C_SET_SND_PARA_VHT_STA0_FEEDBACK_TYPE : 0) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[0].nc, + FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[1].aid, + FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12) | + (snd_info->pndpa.vht_para.sta_info[1].fb_type ? + FWCMD_H2C_SET_SND_PARA_VHT_STA1_FEEDBACK_TYPE : 0) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[1].nc, + FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC)); + h2c->dword11 = + cpu_to_le32(SET_WORD(snd_info->pndpa.vht_para.sta_info[2].aid, + FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12) | + (snd_info->pndpa.vht_para.sta_info[2].fb_type ? + FWCMD_H2C_SET_SND_PARA_VHT_STA2_FEEDBACK_TYPE : 0) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[2].nc, + FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[3].aid, + FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12) | + (snd_info->pndpa.vht_para.sta_info[3].fb_type ? + FWCMD_H2C_SET_SND_PARA_VHT_STA3_FEEDBACK_TYPE : 0) | + SET_WORD(snd_info->pndpa.vht_para.sta_info[3].nc, + FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC)); + h2c->dword12 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[0].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[0].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA0_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[0].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG) | + (snd_info->pndpa.he_para.sta_info[0].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA0_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[0].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA0_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[0].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA0_NC)); + h2c->dword13 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[1].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[1].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA1_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[1].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG) | + (snd_info->pndpa.he_para.sta_info[1].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA1_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[1].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA1_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[1].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA1_NC)); + h2c->dword14 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[2].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[2].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA2_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[2].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG) | + (snd_info->pndpa.he_para.sta_info[2].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA2_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[2].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA2_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[2].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA2_NC)); + h2c->dword15 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[3].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[3].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA3_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[3].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG) | + (snd_info->pndpa.he_para.sta_info[3].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA3_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[3].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA3_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[3].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA3_NC)); + h2c->dword16 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[4].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[4].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA4_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[4].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG) | + (snd_info->pndpa.he_para.sta_info[4].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA4_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[4].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA4_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[4].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA4_NC)); + h2c->dword17 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[5].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[5].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA5_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[5].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG) | + (snd_info->pndpa.he_para.sta_info[5].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA5_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[5].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA5_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[5].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA5_NC)); + h2c->dword18 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[6].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[6].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA6_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[6].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG) | + (snd_info->pndpa.he_para.sta_info[6].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA6_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[6].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA6_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[6].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA6_NC)); + h2c->dword19 = + cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[7].aid, + FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11) | + SET_WORD(snd_info->pndpa.he_para.sta_info[7].bw, + FWCMD_H2C_SET_SND_PARA_HE_STA7_BW) | + SET_WORD(snd_info->pndpa.he_para.sta_info[7].fb_ng, + FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG) | + (snd_info->pndpa.he_para.sta_info[7].disambiguation ? + FWCMD_H2C_SET_SND_PARA_HE_STA7_DISAMBIGUATION : 0) | + (snd_info->pndpa.he_para.sta_info[7].cb ? + FWCMD_H2C_SET_SND_PARA_HE_STA7_CB : 0) | + SET_WORD(snd_info->pndpa.he_para.sta_info[7].nc, + FWCMD_H2C_SET_SND_PARA_HE_STA7_NC)); + h2c->dword20 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].frame_ctl, + FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) | + SET_WORD(snd_info->pbfrp.hdr[0].duration, + FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION)); + h2c->dword21 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr1[0], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[0].addr1[1], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[0].addr1[2], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[0].addr1[3], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword22 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr1[4], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[0].addr1[5], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[0].addr2[0], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[0].addr2[1], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword23 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr2[2], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[0].addr2[3], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[0].addr2[4], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[0].addr2[5], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword24 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].frame_ctl, + FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) | + SET_WORD(snd_info->pbfrp.hdr[1].duration, + FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION)); + h2c->dword25 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr1[0], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[1].addr1[1], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[1].addr1[2], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[1].addr1[3], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword26 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr1[4], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[1].addr1[5], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[1].addr2[0], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[1].addr2[1], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword27 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr2[2], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[1].addr2[3], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[1].addr2[4], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[1].addr2[5], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword28 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].frame_ctl, + FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) | + SET_WORD(snd_info->pbfrp.hdr[2].duration, + FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION)); + h2c->dword29 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr1[0], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[2].addr1[1], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[2].addr1[2], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[2].addr1[3], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword30 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr1[4], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[2].addr1[5], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[2].addr2[0], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[2].addr2[1], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword31 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr2[2], + FWCMD_H2C_SET_SND_PARA_MACID0) | + SET_WORD(snd_info->pbfrp.hdr[2].addr2[3], + FWCMD_H2C_SET_SND_PARA_MACID1) | + SET_WORD(snd_info->pbfrp.hdr[2].addr2[4], + FWCMD_H2C_SET_SND_PARA_MACID2) | + SET_WORD(snd_info->pbfrp.hdr[2].addr2[5], + FWCMD_H2C_SET_SND_PARA_MACID3)); + h2c->dword32 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].common.tgr_info, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO) | + SET_WORD(snd_info->pbfrp.he_para[0].common.ul_len, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH) | + (snd_info->pbfrp.he_para[0].common.more_tf ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF : 0) | + (snd_info->pbfrp.he_para[0].common.cs_rqd ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].common.ul_bw, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW) | + SET_WORD(snd_info->pbfrp.he_para[0].common.gi_ltf, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF) | + (snd_info->pbfrp.he_para[0].common.mimo_ltfmode ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].common.num_heltf, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF) | + SET_WORD(snd_info->pbfrp.he_para[0].common.ul_pktext, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT) | + (snd_info->pbfrp.he_para[0].common.ul_stbc ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC : 0) | + (snd_info->pbfrp.he_para[0].common.ldpc_extra_sym ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL : 0) | + (snd_info->pbfrp.he_para[0].common.dplr ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER : 0)); + h2c->dword33 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].common.ap_tx_pwr, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER) | + SET_WORD(snd_info->pbfrp.he_para[0].common.ul_sr, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE)); + h2c->dword34 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[0].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[0].user[0].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[0].user[0].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[0].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[0].user[0].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[0].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword35 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[0].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[0].user[0].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword36 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[1].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[0].user[1].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[0].user[1].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[1].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[0].user[1].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[1].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword37 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[1].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[0].user[1].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword38 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[2].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[0].user[2].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[0].user[2].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[2].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[0].user[2].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[2].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword39 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[2].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[0].user[2].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword40 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[3].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[0].user[3].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[0].user[3].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[3].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[0].user[3].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[0].user[3].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword41 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[3].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[0].user[3].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword42 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].common.tgr_info, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO) | + SET_WORD(snd_info->pbfrp.he_para[1].common.ul_len, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH) | + (snd_info->pbfrp.he_para[1].common.more_tf ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF : 0) | + (snd_info->pbfrp.he_para[1].common.cs_rqd ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].common.ul_bw, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW) | + SET_WORD(snd_info->pbfrp.he_para[1].common.gi_ltf, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF) | + (snd_info->pbfrp.he_para[1].common.mimo_ltfmode ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].common.num_heltf, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF) | + SET_WORD(snd_info->pbfrp.he_para[1].common.ul_pktext, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT) | + (snd_info->pbfrp.he_para[1].common.ul_stbc ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC : 0) | + (snd_info->pbfrp.he_para[1].common.ldpc_extra_sym ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL : 0) | + (snd_info->pbfrp.he_para[1].common.dplr ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER : 0)); + h2c->dword43 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].common.ap_tx_pwr, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER) | + SET_WORD(snd_info->pbfrp.he_para[1].common.ul_sr, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE)); + h2c->dword44 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[0].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[1].user[0].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[1].user[0].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[0].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[1].user[0].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[0].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword45 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[0].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[1].user[0].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword46 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[1].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[1].user[1].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[1].user[1].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[1].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[1].user[1].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[1].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword47 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[1].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[1].user[1].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword48 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[2].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[1].user[2].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[1].user[2].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[2].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[1].user[2].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[2].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword49 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[2].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[1].user[2].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword50 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[3].aid12, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) | + SET_WORD(snd_info->pbfrp.he_para[1].user[3].ru_pos, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) | + (snd_info->pbfrp.he_para[1].user[3].ul_fec_code ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[3].ul_mcs, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) | + (snd_info->pbfrp.he_para[1].user[3].ul_dcm ? + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) | + SET_WORD(snd_info->pbfrp.he_para[1].user[3].ss_alloc, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC)); + h2c->dword51 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[3].fbseg_rexmit_bmp, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.he_para[1].user[3].ul_tgt_rssi, + FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI)); + h2c->dword52 = + cpu_to_le32(SET_WORD(snd_info->pbfrp.vht_para[0].retransmission_bitmap, + FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.vht_para[1].retransmission_bitmap, + FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT) | + SET_WORD(snd_info->pbfrp.vht_para[2].retransmission_bitmap, + FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT)); + h2c->dword53 = + cpu_to_le32(SET_WORD(snd_info->wd[0].txpktsize, + FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) | + SET_WORD(snd_info->wd[0].ndpa_duration, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0)); + h2c->dword54 = + cpu_to_le32(SET_WORD(snd_info->wd[0].datarate, + FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) | + SET_WORD(snd_info->wd[0].macid, + FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) | + (snd_info->wd[0].force_txop ? + FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) | + SET_WORD(snd_info->wd[0].data_bw, + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) | + SET_WORD(snd_info->wd[0].gi_ltf, + FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) | + (snd_info->wd[0].data_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) | + (snd_info->wd[0].data_dcm ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) | + (snd_info->wd[0].data_stbc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) | + (snd_info->wd[0].data_ldpc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) | + (snd_info->wd[0].data_bw_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) | + (snd_info->wd[0].multiport_id ? + FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) | + SET_WORD(snd_info->wd[0].mbssid, + FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0)); + h2c->dword55 = + cpu_to_le32(SET_WORD(snd_info->wd[0].signaling_ta_pkt_sc, + FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) | + SET_WORD(snd_info->wd[0].sw_define, + FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) | + SET_WORD(snd_info->wd[0].txpwr_ofset_type, + FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) | + SET_WORD(snd_info->wd[0].lifetime_sel, + FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) | + (snd_info->wd[0].stf_mode ? + FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) | + (snd_info->wd[0].disdatafb ? + FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) | + (snd_info->wd[0].data_txcnt_lmt_sel ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) | + SET_WORD(snd_info->wd[0].data_txcnt_lmt, + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) | + (snd_info->wd[0].sifs_tx ? + FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) | + SET_WORD(snd_info->wd[0].snd_pkt_sel, + FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) | + SET_WORD(snd_info->wd[0].ndpa, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0)); + h2c->dword56 = + cpu_to_le32(SET_WORD(snd_info->wd[1].txpktsize, + FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) | + SET_WORD(snd_info->wd[1].ndpa_duration, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0)); + h2c->dword57 = + cpu_to_le32(SET_WORD(snd_info->wd[1].datarate, + FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) | + SET_WORD(snd_info->wd[1].macid, + FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) | + (snd_info->wd[1].force_txop ? + FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) | + SET_WORD(snd_info->wd[1].data_bw, + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) | + SET_WORD(snd_info->wd[1].gi_ltf, + FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) | + (snd_info->wd[1].data_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) | + (snd_info->wd[1].data_dcm ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) | + (snd_info->wd[1].data_stbc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) | + (snd_info->wd[1].data_ldpc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) | + (snd_info->wd[1].data_bw_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) | + (snd_info->wd[1].multiport_id ? + FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) | + SET_WORD(snd_info->wd[1].mbssid, + FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0)); + h2c->dword58 = + cpu_to_le32(SET_WORD(snd_info->wd[1].signaling_ta_pkt_sc, + FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) | + SET_WORD(snd_info->wd[1].sw_define, + FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) | + SET_WORD(snd_info->wd[1].txpwr_ofset_type, + FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) | + SET_WORD(snd_info->wd[1].lifetime_sel, + FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) | + (snd_info->wd[1].stf_mode ? + FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) | + (snd_info->wd[1].disdatafb ? + FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) | + (snd_info->wd[1].data_txcnt_lmt_sel ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) | + SET_WORD(snd_info->wd[1].data_txcnt_lmt, + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) | + (snd_info->wd[1].sifs_tx ? + FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) | + SET_WORD(snd_info->wd[1].snd_pkt_sel, + FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) | + SET_WORD(snd_info->wd[1].ndpa, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0)); + h2c->dword59 = + cpu_to_le32(SET_WORD(snd_info->wd[2].txpktsize, + FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) | + SET_WORD(snd_info->wd[2].ndpa_duration, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0)); + h2c->dword60 = + cpu_to_le32(SET_WORD(snd_info->wd[2].datarate, + FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) | + SET_WORD(snd_info->wd[2].macid, + FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) | + (snd_info->wd[2].force_txop ? + FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) | + SET_WORD(snd_info->wd[2].data_bw, + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) | + SET_WORD(snd_info->wd[2].gi_ltf, + FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) | + (snd_info->wd[2].data_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) | + (snd_info->wd[2].data_dcm ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) | + (snd_info->wd[2].data_stbc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) | + (snd_info->wd[2].data_ldpc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) | + (snd_info->wd[2].data_bw_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) | + (snd_info->wd[2].multiport_id ? + FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) | + SET_WORD(snd_info->wd[2].mbssid, + FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0)); + h2c->dword61 = + cpu_to_le32(SET_WORD(snd_info->wd[2].signaling_ta_pkt_sc, + FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) | + SET_WORD(snd_info->wd[2].sw_define, + FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) | + SET_WORD(snd_info->wd[2].txpwr_ofset_type, + FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) | + SET_WORD(snd_info->wd[2].lifetime_sel, + FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) | + (snd_info->wd[2].stf_mode ? + FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) | + (snd_info->wd[2].disdatafb ? + FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) | + (snd_info->wd[2].data_txcnt_lmt_sel ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) | + SET_WORD(snd_info->wd[2].data_txcnt_lmt, + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) | + (snd_info->wd[2].sifs_tx ? + FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) | + SET_WORD(snd_info->wd[2].snd_pkt_sel, + FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) | + SET_WORD(snd_info->wd[2].ndpa, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0)); + h2c->dword62 = + cpu_to_le32(SET_WORD(snd_info->wd[3].txpktsize, + FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) | + SET_WORD(snd_info->wd[3].ndpa_duration, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0)); + h2c->dword63 = + cpu_to_le32(SET_WORD(snd_info->wd[3].datarate, + FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) | + SET_WORD(snd_info->wd[3].macid, + FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) | + (snd_info->wd[3].force_txop ? + FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) | + SET_WORD(snd_info->wd[3].data_bw, + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) | + SET_WORD(snd_info->wd[3].gi_ltf, + FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) | + (snd_info->wd[3].data_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) | + (snd_info->wd[3].data_dcm ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) | + (snd_info->wd[3].data_stbc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) | + (snd_info->wd[3].data_ldpc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) | + (snd_info->wd[3].data_bw_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) | + (snd_info->wd[3].multiport_id ? + FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) | + SET_WORD(snd_info->wd[3].mbssid, + FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0)); + h2c->dword64 = + cpu_to_le32(SET_WORD(snd_info->wd[3].signaling_ta_pkt_sc, + FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) | + SET_WORD(snd_info->wd[3].sw_define, + FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) | + SET_WORD(snd_info->wd[3].txpwr_ofset_type, + FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) | + SET_WORD(snd_info->wd[3].lifetime_sel, + FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) | + (snd_info->wd[3].stf_mode ? + FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) | + (snd_info->wd[3].disdatafb ? + FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) | + (snd_info->wd[3].data_txcnt_lmt_sel ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) | + SET_WORD(snd_info->wd[3].data_txcnt_lmt, + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) | + (snd_info->wd[3].sifs_tx ? + FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) | + SET_WORD(snd_info->wd[3].snd_pkt_sel, + FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) | + SET_WORD(snd_info->wd[3].ndpa, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0)); + h2c->dword65 = + cpu_to_le32(SET_WORD(snd_info->wd[4].txpktsize, + FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) | + SET_WORD(snd_info->wd[4].ndpa_duration, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0)); + h2c->dword66 = + cpu_to_le32(SET_WORD(snd_info->wd[4].datarate, + FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) | + SET_WORD(snd_info->wd[4].macid, + FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) | + (snd_info->wd[4].force_txop ? + FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) | + SET_WORD(snd_info->wd[4].data_bw, + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) | + SET_WORD(snd_info->wd[4].gi_ltf, + FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) | + (snd_info->wd[4].data_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) | + (snd_info->wd[4].data_dcm ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) | + (snd_info->wd[4].data_stbc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) | + (snd_info->wd[4].data_ldpc ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) | + (snd_info->wd[4].data_bw_er ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) | + (snd_info->wd[4].multiport_id ? + FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) | + SET_WORD(snd_info->wd[4].mbssid, + FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0)); + h2c->dword67 = + cpu_to_le32(SET_WORD(snd_info->wd[4].signaling_ta_pkt_sc, + FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) | + SET_WORD(snd_info->wd[4].sw_define, + FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) | + SET_WORD(snd_info->wd[4].txpwr_ofset_type, + FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) | + SET_WORD(snd_info->wd[4].lifetime_sel, + FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) | + (snd_info->wd[4].stf_mode ? + FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) | + (snd_info->wd[4].disdatafb ? + FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) | + (snd_info->wd[4].data_txcnt_lmt_sel ? + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) | + SET_WORD(snd_info->wd[4].data_txcnt_lmt, + FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) | + (snd_info->wd[4].sifs_tx ? + FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) | + SET_WORD(snd_info->wd[4].snd_pkt_sel, + FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) | + SET_WORD(snd_info->wd[4].ndpa, + FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0)); + h2c->dword68 = + cpu_to_le32(SET_WORD(snd_info->f2p[0].csi_len_bfrp, + FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0) | + SET_WORD(snd_info->f2p[0].tb_t_pe_bfrp, + FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0) | + SET_WORD(snd_info->f2p[0].tri_pad_bfrp, + FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0) | + (snd_info->f2p[0].ul_cqi_rpt_tri_bfrp ? + FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 : 0) | + SET_WORD(snd_info->f2p[0].rf_gain_idx_bfrp, + FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0) | + (snd_info->f2p[0].fix_gain_en_bfrp ? + FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 : 0)); + h2c->dword69 = + cpu_to_le32(SET_WORD(snd_info->f2p[1].csi_len_bfrp, + FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0) | + SET_WORD(snd_info->f2p[1].tb_t_pe_bfrp, + FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0) | + SET_WORD(snd_info->f2p[1].tri_pad_bfrp, + FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0) | + (snd_info->f2p[1].ul_cqi_rpt_tri_bfrp ? + FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 : 0) | + SET_WORD(snd_info->f2p[1].rf_gain_idx_bfrp, + FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0) | + (snd_info->f2p[1].fix_gain_en_bfrp ? + FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 : 0)); + h2c->dword70 = + cpu_to_le32(SET_WORD(snd_info->sfp.f2p_type, + FWCMD_H2C_SET_SND_PARA_F2P_TYPE) | + SET_WORD(snd_info->sfp.f2p_index, + FWCMD_H2C_SET_SND_PARA_F2P_INDEX) | + SET_WORD(snd_info->sfp.f2p_period, + FWCMD_H2C_SET_SND_PARA_F2P_PERIOD)); + h2c->dword71 = + cpu_to_le32(SET_WORD(snd_info->sfp.f2p_updcnt, + FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT) | + SET_WORD(snd_info->sfp.cr_idx, + FWCMD_H2C_SET_SND_PARA_CR_IDX)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_SOUND, + FWCMD_H2C_FUNC_SET_SND_PARA, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_set_csi_para_reg(struct mac_ax_adapter *adapter, + struct mac_reg_csi_para *csi_para) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + u16 val16; + +#if MAC_AX_FW_REG_OFLD + u32 mask; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } + + cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0; + mask = B_AX_BFMEE_BFPARAM_SEL; + ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + if (csi_para->portsel == 0) + cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0; + else + cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_1; + val16 = SET_WORD(csi_para->nc, B_AX_BFMEE_CSIINFO0_NC) | + SET_WORD(csi_para->nr, B_AX_BFMEE_CSIINFO0_NR) | + SET_WORD(csi_para->ng, B_AX_BFMEE_CSIINFO0_NG) | + SET_WORD(csi_para->cb, B_AX_BFMEE_CSIINFO0_CB) | + SET_WORD(csi_para->cs, B_AX_BFMEE_CSIINFO0_CS) | + (csi_para->ldpc_en ? B_AX_BFMEE_CSIINFO0_LDPC_EN : 0) | + (csi_para->stbc_en ? B_AX_BFMEE_CSIINFO0_STBC_EN : 0); + ret = MAC_REG_W16_OFLD(cr, val16, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } + + val32 = MAC_REG_R32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0); + val32 |= B_AX_BFMEE_BFPARAM_SEL; + MAC_REG_W32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32); + + val16 = SET_WORD(csi_para->nc, B_AX_BFMEE_CSIINFO0_NC) | + SET_WORD(csi_para->nr, B_AX_BFMEE_CSIINFO0_NR) | + SET_WORD(csi_para->ng, B_AX_BFMEE_CSIINFO0_NG) | + SET_WORD(csi_para->cb, B_AX_BFMEE_CSIINFO0_CB) | + SET_WORD(csi_para->cs, B_AX_BFMEE_CSIINFO0_CS) | + (csi_para->ldpc_en ? B_AX_BFMEE_CSIINFO0_LDPC_EN : 0) | + (csi_para->stbc_en ? B_AX_BFMEE_CSIINFO0_STBC_EN : 0); + + if (csi_para->portsel == 0) + MAC_REG_W16(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val16); + else + MAC_REG_W16(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_1, val16); + return MACSUCCESS; +} + +u32 mac_set_csi_para_cctl(struct mac_ax_adapter *adapter, + struct mac_cctl_csi_para *csi_para) +{ + struct mac_ax_cctl_info info; + struct mac_ax_cctl_info mask; + struct mac_ax_ops *ax_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret, val32; + +#if MAC_AX_FW_REG_OFLD + u32 msk; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } + + cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0; + msk = B_AX_BFMEE_BFPARAM_SEL; + ret = write_mac_reg_ofld(adapter, cr, msk, 0, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + info.nc = csi_para->nc; + info.nr = csi_para->nr; + info.ng = csi_para->ng; + info.cb = csi_para->cb; + info.cs = csi_para->cs; + //info.csi_txbf_en = csi_para->bf_en; BB HW BUG not support + info.csi_txbf_en = 0x0; + info.csi_stbc_en = csi_para->stbc_en; + info.csi_ldpc_en = csi_para->ldpc_en; + info.csi_para_en = 1; + info.csi_fix_rate = csi_para->rate; + info.csi_gi_ltf = csi_para->gi_ltf; + info.uldl = csi_para->gid_sel; + info.csi_bw = csi_para->bw; + + PLTFM_MEMSET(&mask, 0, sizeof(mask)); + mask.nc = 0x7; + mask.nr = 0x7; + mask.ng = 0x3; + mask.cb = 0x3; + mask.cs = 0x3; + mask.csi_txbf_en = 0x1; + mask.csi_stbc_en = 0x1; + mask.csi_ldpc_en = 0x1; + mask.csi_para_en = 0x1; + mask.csi_fix_rate = 0x1FF; + mask.csi_gi_ltf = 0x7; + mask.uldl = 0x1; + mask.csi_bw = 0x3; + ret = ax_ops->upd_cctl_info(adapter, &info, &mask, csi_para->macid, 1); + if (ret) + return MACCCTLWRFAIL; + + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + if (is_cv(adapter, CBV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + if (is_cv(adapter, CAV)) { + if (csi_para->ng == 3) + return MACHWNOSUP; + } + } + + val32 = MAC_REG_R32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0); + val32 &= (~B_AX_BFMEE_BFPARAM_SEL); + MAC_REG_W32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : + R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32); + + info.nc = csi_para->nc; + info.nr = csi_para->nr; + info.ng = csi_para->ng; + info.cb = csi_para->cb; + info.cs = csi_para->cs; + //info.csi_txbf_en = csi_para->bf_en; BB HW BUG not support + info.csi_txbf_en = 0x0; + info.csi_stbc_en = csi_para->stbc_en; + info.csi_ldpc_en = csi_para->ldpc_en; + info.csi_para_en = 1; + info.csi_fix_rate = csi_para->rate; + info.csi_gi_ltf = csi_para->gi_ltf; + info.uldl = csi_para->gid_sel; + info.csi_bw = csi_para->bw; + + PLTFM_MEMSET(&mask, 0, sizeof(mask)); + mask.nc = 0x7; + mask.nr = 0x7; + mask.ng = 0x3; + mask.cb = 0x3; + mask.cs = 0x3; + mask.csi_txbf_en = 0x1; + mask.csi_stbc_en = 0x1; + mask.csi_ldpc_en = 0x1; + mask.csi_para_en = 0x1; + mask.csi_fix_rate = 0x1FF; + mask.csi_gi_ltf = 0x7; + mask.uldl = 0x1; + mask.csi_bw = 0x3; + ret = ax_ops->upd_cctl_info(adapter, &info, &mask, csi_para->macid, 1); + if (ret) + return MACCCTLWRFAIL; + + return MACSUCCESS; +} + +u32 mac_hw_snd_pause_release(struct mac_ax_adapter *adapter, u8 band, + u8 pr) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 ret; + +#if MAC_AX_FW_REG_OFLD + u16 cr, val16; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN; + val16 = pr ? HW_SND_RELEASE : HW_SND_PAUSE; + ret = MAC_REG_W16_OFLD(cr, val16, 1); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + MAC_REG_W16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN, + pr ? HW_SND_RELEASE : HW_SND_PAUSE); + + return MACSUCCESS; +} + +u32 mac_bypass_snd_sts(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + +#if MAC_AX_FW_REG_OFLD + u32 mask, ret; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + cr = R_AX_AGG_BK_0; + mask = B_AX_DIS_SND_STS_CHECK; + ret = write_mac_reg_ofld(adapter, cr, mask, 1, 1); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + val8 = MAC_REG_R8(R_AX_AGG_BK_0); + MAC_REG_W8(R_AX_AGG_BK_0, val8 | B_AX_DIS_SND_STS_CHECK); + + return MACSUCCESS; +} + +u32 mac_deinit_mee(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + +#if MAC_AX_FW_REG_OFLD + u32 mask; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cr = band ? R_AX_BFMEE_RESP_OPTION_C1 : R_AX_BFMEE_RESP_OPTION; + mask = (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | + B_AX_BFMEE_HE_NDPA_EN); + ret = write_mac_reg_ofld(adapter, cr, mask, 0, 1); + + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = MAC_REG_R32(band ? R_AX_BFMEE_RESP_OPTION_C1 : + R_AX_BFMEE_RESP_OPTION); + val32 &= ~(B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | + B_AX_BFMEE_HE_NDPA_EN); + MAC_REG_W32(band ? R_AX_BFMEE_RESP_OPTION_C1 : + R_AX_BFMEE_RESP_OPTION, val32); + + return MACSUCCESS; +} + +u32 mac_snd_sup(struct mac_ax_adapter *adapter, struct mac_bf_sup *bf_sup) +{ + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + bf_sup->bf_entry_num = 16; + bf_sup->su_buffer_num = 16; + bf_sup->mu_buffer_num = 6; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + bf_sup->bf_entry_num = 16; + bf_sup->su_buffer_num = 16; + bf_sup->mu_buffer_num = 6; + } else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) { + bf_sup->bf_entry_num = 16; + bf_sup->su_buffer_num = 16; + bf_sup->mu_buffer_num = 6; + } else { + return MACNOTSUP; + } + return MACSUCCESS; +} + +u32 mac_gidpos(struct mac_ax_adapter *adapter, struct mac_gid_pos *mu_gid) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + +#if MAC_AX_FW_REG_OFLD + u32 ret, val32; + u16 cr; + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + cr = mu_gid->band ? R_AX_GID_POSITION_EN0_C1 : R_AX_GID_POSITION_EN0; + val32 = mu_gid->gid_tab[0]; + ret = MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = mu_gid->band ? R_AX_GID_POSITION_EN1_C1 : R_AX_GID_POSITION_EN1; + val32 = mu_gid->gid_tab[1]; + MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = mu_gid->band ? R_AX_GID_POSITION0_C1 : R_AX_GID_POSITION0; + val32 = mu_gid->user_pos[0]; + MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = mu_gid->band ? R_AX_GID_POSITION1_C1 : R_AX_GID_POSITION1; + val32 = mu_gid->user_pos[1]; + MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = mu_gid->band ? R_AX_GID_POSITION2_C1 : R_AX_GID_POSITION2; + val32 = mu_gid->user_pos[2]; + MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + + cr = mu_gid->band ? R_AX_GID_POSITION3_C1 : R_AX_GID_POSITION3; + val32 = mu_gid->user_pos[3]; + MAC_REG_W32_OFLD(cr, val32, 0); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr); + return ret; + } + return MACSUCCESS; + } +#endif + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION_EN0_C1 : + R_AX_GID_POSITION_EN0, mu_gid->gid_tab[0]); + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION_EN1_C1 : + R_AX_GID_POSITION_EN1, mu_gid->gid_tab[1]); + + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION0_C1 : R_AX_GID_POSITION0, + mu_gid->user_pos[0]); + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION1_C1 : R_AX_GID_POSITION1, + mu_gid->user_pos[1]); + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION2_C1 : R_AX_GID_POSITION2, + mu_gid->user_pos[2]); + MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION3_C1 : R_AX_GID_POSITION3, + mu_gid->user_pos[3]); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/sounding.h b/phl/hal_g6/mac/mac_ax/sounding.h new file mode 100644 index 0000000..36ed7d4 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/sounding.h @@ -0,0 +1,399 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_SOUNDING_H_ +#define _MAC_AX_SOUNDING_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "trxcfg.h" + +#define CSI_MAX_BUFFER_IDX 0xF +#define SOUNDING_STS_MAX_IDX 0x15 +#define CSI_RRSC_BMAP 0x29292911 +#define BFRP_RX_STANDBY_TIMER 0x0 +#define NDP_RX_STANDBY_TIMER 0xFF +#define CSI_INIT_RATE_HE 0x0 +#define CSI_INIT_RATE_VHT 0x0 +#define CSI_INIT_RATE_HT 0x0 +#define HW_SND_RELEASE 0xFFFF +#define HW_SND_PAUSE 0x0 +#define HT_PAYLOAD_OFFSET 0x10 +#define VHT_PAYLOAD_OFFSET 0x11 +#define HE_PAYLOAD_OFFSET 0x13 +#define CSI_SH 0x4 +#define SND_SH 0x2 +#define SND_MEE_CFG (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS | \ + B_AX_BFMEE_CSI_FORCE_RETE_EN | B_AX_BFMEE_BFINF0_NR | \ + B_AX_BFMEE_BFINFO0_NC) +#define MAX_SNDTXCMDINFO_NUM 0x4 + +enum FrameExchangeType { + FRAME_EXCHANGE_SND_AC_SU = 31, + FRAME_EXCHANGE_SND_AC_MU_BFRP1 = 32, + FRAME_EXCHANGE_SND_AC_MU_BFRP2 = 33, + FRAME_EXCHANGE_SND_AC_MU_BFRP3 = 34, + FRAME_EXCHANGE_SND_AX_SU = 35, + FRAME_EXCHANGE_SND_AX_MU_BFRP1 = 36, + FRAME_EXCHANGE_SND_AX_MU_BFRP2 = 37, + FRAME_EXCHANGE_SND_N_SU = 38 +}; + +enum SND_F2P_TYPE { + SNDF2P_ONCE = 0, + SNDF2P_ADD = 1, + SNDF2P_DEL = 2 +}; + +/** + * @addtogroup Sounding + * @{ + */ +/** + * @brief mac_get_csi_buffer_index + * + * @param *adapter + * @param band + * @param csi_buffer_id + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band, + u8 csi_buffer_id); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_csi_buffer_index + * + * @param *adapter + * @param band + * @param macid + * @param csi_buffer_id + * @param buffer_idx + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band, + u8 macid, u16 csi_buffer_id, u16 buffer_idx); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_get_snd_sts_index + * + * @param *adapter + * @param band + * @param index + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_get_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 index); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_snd_sts_index + * + * @param *adapter + * @param band + * @param macid + * @param index + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 macid, + u8 index); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_init_snd_mer + * + * @param *adapter + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_init_snd_mer(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_init_snd_mee + * + * @param *adapter + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_init_snd_mee(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_csi_force_rate + * + * @param *adapter + * @param band + * @param ht_rate + * @param vht_rate + * @param he_rate + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_csi_force_rate(struct mac_ax_adapter *adapter, u8 band, u8 ht_rate, + u8 vht_rate, u8 he_rate); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_csi_rrsc + * + * @param *adapter + * @param band + * @param rrsc + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_csi_rrsc(struct mac_ax_adapter *adapter, u8 band, u32 rrsc); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_mu_table + * + * @param *adapter + * @param *mu_table + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_mu_table(struct mac_ax_adapter *adapter, + struct mac_mu_table *mu_table); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_snd_para + * + * @param *adapter + * @param *snd_info + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_snd_para(struct mac_ax_adapter *adapter, + struct mac_ax_fwcmd_snd *snd_info); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_csi_para_reg + * + * @param *adapter + * @param *csi_para + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_csi_para_reg(struct mac_ax_adapter *adapter, + struct mac_reg_csi_para *csi_para); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_set_csi_para_cctl + * + * @param *adapter + * @param *csi_para + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_set_csi_para_cctl(struct mac_ax_adapter *adapter, + struct mac_cctl_csi_para *csi_para); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_hw_snd_pause_release + * + * @param *adapter + * @param band + * @param pr + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_hw_snd_pause_release(struct mac_ax_adapter *adapter, u8 band, u8 pr); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_bypass_snd_sts + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_bypass_snd_sts(struct mac_ax_adapter *adapter); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_deinit_mee + * + * @param *adapter + * @param band + * @return Please Place Description here. + * @retval u32 + */ + +u32 mac_deinit_mee(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_snd_sup + * + * @param *adapter + * @param *bf_sup + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_snd_sup(struct mac_ax_adapter *adapter, struct mac_bf_sup *bf_sup); +/** + * @} + */ + +/** + * @addtogroup Sounding + * @{ + */ + +/** + * @brief mac_gid_pos + * + * @param *adapter + * @param *mac_gid_pos + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_gidpos(struct mac_ax_adapter *adapter, struct mac_gid_pos *mu_gid); +/** + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/spatial_reuse.c b/phl/hal_g6/mac/mac_ax/spatial_reuse.c new file mode 100644 index 0000000..687c716 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/spatial_reuse.c @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ +#include "spatial_reuse.h" + +u32 mac_sr_update(struct mac_ax_adapter *adapter, + struct mac_ax_sr_info *sr_info, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u32 val32, ret, reg; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_RX_SR_CTRL_C1 : R_AX_RX_SR_CTRL; + val8 = MAC_REG_R8(reg); + val8 = (sr_info->sr_en) ? (val8 | B_AX_SR_EN) : (val8 & ~B_AX_SR_EN); + MAC_REG_W8(reg, val8); + + reg = band == MAC_AX_BAND_1 ? R_AX_TCR0_C1 : R_AX_TCR0; + val8 = MAC_REG_R8(reg); + val8 = (sr_info->sr_field_v15_allowed) ? + (val8 | B_AX_TCR_SR_VAL15_ALLOW) : + (val8 & ~B_AX_TCR_SR_VAL15_ALLOW); + MAC_REG_W8(reg, val8); + + reg = band == MAC_AX_BAND_1 ? R_AX_SR_OBSS_PD_C1 : R_AX_SR_OBSS_PD; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_min, + B_AX_NONSRG_OBSS_PD_MIN); + val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_max, + B_AX_NONSRG_OBSS_PD_MAX); + val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_min, + B_AX_SRG_OBSS_PD_MIN); + val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_max, + B_AX_SRG_OBSS_PD_MAX); + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_SR_BSSCOLOR_BITMAP_C1 : R_AX_SR_BSSCOLOR_BITMAP; + MAC_REG_W32(reg, sr_info->srg_bsscolor_bitmap_0); + MAC_REG_W32(reg + 4, sr_info->srg_bsscolor_bitmap_1); + + reg = band == MAC_AX_BAND_1 ? + R_AX_SR_PARTIAL_BSSCOLOR_BITMAP_C1 : + R_AX_SR_PARTIAL_BSSCOLOR_BITMAP; + MAC_REG_W32(reg, sr_info->srg_partbsid_bitmap_0); + MAC_REG_W32(reg + 4, sr_info->srg_partbsid_bitmap_1); + + return MACSUCCESS; +} + +u32 spatial_reuse_init(struct mac_ax_adapter *adapter, + enum mac_ax_band band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u32 ret, reg; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_RX_SR_CTRL_C1 : R_AX_RX_SR_CTRL; + val8 = MAC_REG_R8(reg) & ~B_AX_SR_EN; + MAC_REG_W8(reg, val8); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/spatial_reuse.h b/phl/hal_g6/mac/mac_ax/spatial_reuse.h new file mode 100644 index 0000000..79fe209 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/spatial_reuse.h @@ -0,0 +1,29 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_SPATIAL_REUSE_H_ +#define _MAC_AX_SPATIAL_REUSE_H_ + +#include "../type.h" + +u32 mac_sr_update(struct mac_ax_adapter *adapter, + struct mac_ax_sr_info *sr_info, + enum mac_ax_band band); + +u32 spatial_reuse_init(struct mac_ax_adapter *adapter, + enum mac_ax_band band); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/sta_sch.c b/phl/hal_g6/mac/mac_ax/sta_sch.c new file mode 100644 index 0000000..4061095 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/sta_sch.c @@ -0,0 +1,485 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "sta_sch.h" + +static u32 poll_own_chk(struct mac_ax_adapter *adapter, u32 addr) +{ + u32 cnt = 100; + u32 ck; + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (addr == R_AX_SS_SRAM_CTRL_1 || addr == R_AX_SS_LINK_INFO || + addr == R_AX_SS_SRAM_CTRL_0 || addr == R_AX_SS_LINK_ADD || + addr == R_AX_SS_LINK_DEL || addr == R_AX_SS_LINK_SEARCH) + ck = B_AX_SS_OWN; + else + ck = 0; + + while (--cnt) { + val32 = MAC_REG_R32(addr); + if ((val32 & ck) == 0) + break; + PLTFM_DELAY_US(1); + } + if (!cnt) { + PLTFM_MSG_ERR("[STASCH]poll_own fail!!\n"); + return MACPOLLTO; + } + + if (addr == R_AX_SS_SRAM_CTRL_1 || addr == R_AX_SS_LINK_INFO || + addr == R_AX_SS_LINK_ADD || addr == R_AX_SS_LINK_DEL) { + val32 = MAC_REG_R32(addr); + if (val32 & (BIT(29) | BIT(30))) { + PLTFM_MSG_ERR("[STASCH]poll status fail!!\n"); + return MACPROCERR; + } + } + return MACSUCCESS; +} + +static u32 poll_own_val(struct mac_ax_adapter *adapter, u32 addr, u32 *r_val) +{ + u32 cnt = 100; + u32 ck; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (addr == R_AX_SS_SRAM_CTRL_1 || addr == R_AX_SS_LINK_INFO || + addr == R_AX_SS_SRAM_CTRL_0 || addr == R_AX_SS_LINK_ADD || + addr == R_AX_SS_LINK_DEL || addr == R_AX_SS_LINK_SEARCH) + ck = B_AX_SS_OWN; + else + ck = 0; + + while (--cnt) { + *r_val = MAC_REG_R32(addr); + if ((*r_val & ck) == 0) + break; + PLTFM_DELAY_US(1); + } + if (!cnt) { + PLTFM_MSG_ERR("[STASCH]poll_own fail!!\n"); + return MACPOLLTO; + } + + if (addr == R_AX_SS_SRAM_CTRL_1 || addr == R_AX_SS_LINK_INFO || + addr == R_AX_SS_LINK_ADD || addr == R_AX_SS_LINK_DEL) { + if (*r_val & (BIT(29) | BIT(30))) { + PLTFM_MSG_ERR("[STASCH]poll status fail!!\n"); + return MACPROCERR; + } + } + return MACSUCCESS; +} + +static u32 sram1_ctrl_val(struct mac_ax_adapter *adapter, u32 cmd, u32 *r_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, cmd); + + return poll_own_val(adapter, R_AX_SS_SRAM_CTRL_1, r_val); +} + +static u32 get_link_info(struct mac_ax_adapter *adapter, u32 cmd, u32 *r_val) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_SS_LINK_INFO, cmd); + + return poll_own_val(adapter, R_AX_SS_LINK_INFO, r_val); +} + +static u32 add_to_link(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_SS_LINK_ADD, B_AX_SS_OWN | + (link->ul ? B_AX_SS_UL : 0) | + SET_WORD(link->wmm, B_AX_SS_WMM) | + SET_WORD(link->ac, B_AX_SS_AC) | + SET_WORD(link->macid2, B_AX_SS_MACID_2) | + SET_WORD(link->macid1, B_AX_SS_MACID_1) | + SET_WORD(link->macid0, B_AX_SS_MACID_0)); + return poll_own_chk(adapter, R_AX_SS_LINK_ADD); +} + +static u32 del_from_link(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + MAC_REG_W32(R_AX_SS_LINK_DEL, B_AX_SS_OWN | + (link->ul ? B_AX_SS_UL : 0) | + SET_WORD(link->wmm, B_AX_SS_WMM) | + SET_WORD(link->ac, B_AX_SS_AC) | + SET_WORD(link->macid2, B_AX_SS_MACID_2) | + SET_WORD(link->macid1, B_AX_SS_MACID_1) | + SET_WORD(link->macid0, B_AX_SS_MACID_0)); + return poll_own_chk(adapter, R_AX_SS_LINK_DEL); +} + +static u32 clean_sta_link(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link) +{ + u32 val32; + u8 wmm, ac; + u32 cnt = adapter->hw_info->macid_num + 1; + u32 cmd; + u32 ret; + + if (link->ul) { + wmm = 0; + ac = 0; + } else { + wmm = link->wmm; + ac = link->ac; + } + + do { + cmd = B_AX_SS_OWN | (link->ul ? B_AX_SS_UL : 0) | + SET_WORD(wmm, B_AX_SS_WMM) | SET_WORD(ac, B_AX_SS_AC); + ret = get_link_info(adapter, cmd, &val32); + if (ret != MACSUCCESS) + return ret; + + link->link_head = GET_FIELD(val32, B_AX_SS_LINK_HEAD); + link->link_tail = GET_FIELD(val32, B_AX_SS_LINK_TAIL); + link->link_len = GET_FIELD(val32, B_AX_SS_LINK_LEN); + link->macid0 = link->link_head; + + if (link->macid0 != 0xFF) { + ret = del_from_link(adapter, link); + if (ret != MACSUCCESS) + return ret; + cnt--; + } else { + break; + } + } while (link->link_len || cnt); + + if (!cnt) { + PLTFM_MSG_ERR("[STASCH]link error!!\n"); + return MACSSLINK; + } + + return MACSUCCESS; +} + +static u32 wmm_vld_chk(struct mac_ax_adapter *adapter, u8 *vld, u8 wmm) +{ + u8 wmm_num; + + switch (adapter->hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + wmm_num = STA_SCH_WMM_NUM_8852A; + break; + case MAC_AX_CHIP_ID_8852B: + wmm_num = STA_SCH_WMM_NUM_8852B; + break; + case MAC_AX_CHIP_ID_8852C: + wmm_num = STA_SCH_WMM_NUM_8852C; + break; + default: + return MACCHIPID; + } + + if (wmm < wmm_num) + *vld = 1; + else + *vld = 0; + + return MACSUCCESS; +} + +static u32 ul_vld_chk(struct mac_ax_adapter *adapter, u8 *vld) +{ + u8 ul_support; + + switch (adapter->hw_info->chip_id) { + case MAC_AX_CHIP_ID_8852A: + ul_support = STA_SCH_UL_SUPPORT_8852A; + break; + case MAC_AX_CHIP_ID_8852B: + ul_support = STA_SCH_UL_SUPPORT_8852B; + break; + case MAC_AX_CHIP_ID_8852C: + ul_support = STA_SCH_UL_SUPPORT_8852C; + break; + default: + return MACCHIPID; + } + + if (ul_support) + *vld = 1; + else + *vld = 0; + + return MACSUCCESS; +} + +static u32 get_sta_link(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link) +{ + u32 val32, i; + u8 macid, wmm, ac; + u32 ret; + u32 cmd; + u16 macid_num = adapter->hw_info->macid_num; + u16 id_empty = (macid_num << 1) - 1; + + if (link->ul) { + wmm = 0; + ac = 0; + } else { + wmm = link->wmm; + ac = link->ac; + } + + cmd = B_AX_SS_OWN | (link->ul ? B_AX_SS_UL : 0) | + SET_WORD(wmm, B_AX_SS_WMM) | SET_WORD(ac, B_AX_SS_AC); + ret = get_link_info(adapter, cmd, &val32); + if (ret != MACSUCCESS) + return ret; + + link->link_head = GET_FIELD(val32, B_AX_SS_LINK_HEAD); + link->link_tail = GET_FIELD(val32, B_AX_SS_LINK_TAIL); + link->link_len = GET_FIELD(val32, B_AX_SS_LINK_LEN); + macid = link->link_head; + + if (link->link_head == id_empty) { + if (link->link_len) { + PLTFM_MSG_ERR("empty link_len error!!"); + return MACSSLINK; + } + } else { + i = 0; + do { + link->link_list[i] = macid; + link->link_bitmap[macid] = 1; + cmd = B_AX_SS_OWN | + SET_WORD(CTRL1_R_NEXT_LINK, B_AX_SS_CMD_SEL) | + SET_WORD(ac, B_AX_SS_AC) | + (link->ul ? BIT(23) : 0) | macid; + ret = sram1_ctrl_val(adapter, cmd, &val32); + if (ret != MACSUCCESS) + return ret; + + macid = GET_FIELD(val32, B_AX_SS_VALUE); + if (macid == id_empty) { + if (link->link_list[i] != link->link_tail) { + PLTFM_MSG_ERR("[STASCH]link_tail error!!\n"); + return MACSSLINK; + } + if (i >= link->link_len) { + PLTFM_MSG_ERR("[STASCH]link_len error!!\n"); + return MACSSLINK; + } + break; + } + i++; + } while (i < SS_LINK_SIZE); + } + + return MACSUCCESS; +} + +u32 sta_link_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link, + enum mac_ax_ss_link_cfg cfg) +{ + u32 ret; + u8 vld; + + if (link->ul) { + ret = ul_vld_chk(adapter, &vld); + if (ret != MACSUCCESS) + return ret; + if (vld == 0) + return MACSUCCESS; + } + + ret = wmm_vld_chk(adapter, &vld, link->wmm); + if (ret != MACSUCCESS) + return ret; + if (vld == 0) + return MACSUCCESS; + + switch (cfg) { + case MAC_AX_SS_LINK_CFG_GET: + ret = get_sta_link(adapter, link); + break; + case MAC_AX_SS_LINK_CFG_ADD: + ret = add_to_link(adapter, link); + break; + case MAC_AX_SS_LINK_CFG_DEL: + ret = del_from_link(adapter, link); + break; + case MAC_AX_SS_LINK_CFG_CLEAN: + ret = clean_sta_link(adapter, link); + break; + } + + return ret; +} + +void set_ss_wmm_tbl(struct mac_ax_adapter *adapter, + struct mac_ax_ss_wmm_tbl_ctrl *ctrl) +{ + u32 val32; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + val32 = MAC_REG_R32(R_AX_SS_CTRL); + switch (ctrl->wmm) { + case 0: + val32 = SET_CLR_WORD(val32, ctrl->wmm_mapping, + B_AX_SS_WMM_SEL_0); + break; + case 1: + val32 = SET_CLR_WORD(val32, ctrl->wmm_mapping, + B_AX_SS_WMM_SEL_1); + break; + case 2: + val32 = SET_CLR_WORD(val32, ctrl->wmm_mapping, + B_AX_SS_WMM_SEL_2); + break; + case 3: + val32 = SET_CLR_WORD(val32, ctrl->wmm_mapping, + B_AX_SS_WMM_SEL_3); + break; + default: + break; + } + MAC_REG_W32(R_AX_SS_CTRL, val32); +} + +void ss_wmm_tbl_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_ss_wmm_tbl_ctrl *ctrl, + enum mac_ax_ss_wmm_tbl_cfg cfg) +{ + set_ss_wmm_tbl(adapter, ctrl); +} + +u32 switch_wmm_macid(struct mac_ax_adapter *adapter, + struct mac_ax_ss_link_info *link, + enum mac_ax_ss_wmm_tbl src_link, + enum mac_ax_ss_wmm_tbl dst_link) +{ + u32 ret; + + link->wmm = src_link; + ret = sta_link_cfg(adapter, link, MAC_AX_SS_LINK_CFG_DEL); + if (ret != MACSUCCESS) + return ret; + link->wmm = dst_link; + ret = sta_link_cfg(adapter, link, MAC_AX_SS_LINK_CFG_ADD); + if (ret != MACSUCCESS) + return ret; + + return MACSUCCESS; +} + +static u32 switch_wmm_link(struct mac_ax_adapter *adapter, + enum mac_ax_ss_wmm_tbl src_link, + enum mac_ax_ss_wmm_tbl dst_link, + enum mac_ax_ss_wmm src_wmm) +{ + u32 ret; + u32 i; + struct mac_ax_ss_link_info link; + struct mac_role_tbl *role; + + link.ul = 0; + for (link.ac = 0; link.ac < 4; link.ac++) { + PLTFM_MEMSET(link.link_list, 0xFF, SS_LINK_SIZE); + link.wmm = src_link; + ret = sta_link_cfg(adapter, &link, MAC_AX_SS_LINK_CFG_GET); + if (ret != MACSUCCESS) + return ret; + for (i = 0; i < link.link_len; i += 3) { + link.macid0 = link.link_list[i]; + link.macid1 = link.link_list[i + 1]; + link.macid2 = link.link_list[i + 2]; + if (link.macid0 != 0xFF) { + role = mac_role_srch(adapter, link.macid0); + if (!role) + return MACNOITEM; + if ((enum mac_ax_ss_wmm)role->wmm != src_wmm) + link.macid0 = 0xFF; + } + if (link.macid1 != 0xFF) { + role = mac_role_srch(adapter, link.macid1); + if (!role) + return MACNOITEM; + if ((enum mac_ax_ss_wmm)role->wmm != src_wmm) + link.macid1 = 0xFF; + } + if (link.macid2 != 0xFF) { + role = mac_role_srch(adapter, link.macid2); + if (!role) + return MACNOITEM; + if ((enum mac_ax_ss_wmm)role->wmm != src_wmm) + link.macid2 = 0xFF; + } + if (link.macid0 != 0xFF || link.macid1 != 0xFF || + link.macid2 != 0xFF) { + ret = switch_wmm_macid(adapter, &link, src_link, + dst_link); + if (ret != MACSUCCESS) + return ret; + } + } + } + return MACSUCCESS; +} + +u32 mac_ss_wmm_sta_move(struct mac_ax_adapter *adapter, + enum mac_ax_ss_wmm src_wmm, + enum mac_ax_ss_wmm_tbl dst_link) +{ + struct mac_ax_ss_wmm_tbl_ctrl ctrl; + u32 ret; + + switch (src_wmm) { + case MAC_AX_SS_WMM0: + ctrl.wmm = 0; + break; + case MAC_AX_SS_WMM1: + ctrl.wmm = 1; + break; + case MAC_AX_SS_WMM2: + ctrl.wmm = 2; + break; + case MAC_AX_SS_WMM3: + ctrl.wmm = 3; + break; + default: + return MACNOITEM; + } + ret = get_ss_wmm_tbl(adapter, &ctrl); + if (ret != MACSUCCESS) + return ret; + + ret = switch_wmm_link(adapter, ctrl.wmm_mapping, dst_link, src_wmm); + if (ret != MACSUCCESS) + return ret; + ctrl.wmm_mapping = dst_link; + ss_wmm_tbl_cfg(adapter, &ctrl, MAC_AX_SS_WMM_TBL_SET); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/sta_sch.h b/phl/hal_g6/mac/mac_ax/sta_sch.h new file mode 100644 index 0000000..24efdf4 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/sta_sch.h @@ -0,0 +1,103 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_STA_SCH_H_ +#define _MAC_AX_STA_SCH_H_ + +#include "../type.h" + +/*--------------------Define -------------------------------------------*/ +#define STA_SCH_WMM_NUM_8852A 4 +#define STA_SCH_WMM_NUM_8852B 2 +#define STA_SCH_WMM_NUM_8852C 4 + +#define STA_SCH_UL_SUPPORT_8852A 1 +#define STA_SCH_UL_SUPPORT_8852B 0 +#define STA_SCH_UL_SUPPORT_8852C 1 + +#define CTRL1_R_NEXT_LINK 20 + +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ + +/** + * @enum mac_ax_ss_link_cfg + * + * @brief mac_ax_ss_link_cfg + * + * @var mac_ax_ss_link_cfg::mac_AX_SS_LINK_CFG_GET + * Please Place Description here. + * @var mac_ax_ss_link_cfg::mac_AX_SS_LINK_CFG_ADD + * Please Place Description here. + * @var mac_ax_ss_link_cfg::mac_AX_SS_LINK_CFG_DEL + * Please Place Description here. + * @var mac_ax_ss_link_cfg::mac_AX_SS_LINK_CFG_CLEAN + * Please Place Description here. + */ +enum mac_ax_ss_link_cfg { + MAC_AX_SS_LINK_CFG_GET, + MAC_AX_SS_LINK_CFG_ADD, + MAC_AX_SS_LINK_CFG_DEL, + MAC_AX_SS_LINK_CFG_CLEAN, +}; + +/** + * @enum mac_ax_ss_wmm_tbl_cfg + * + * @brief mac_ax_ss_wmm_tbl_cfg + * + * @var mac_ax_ss_wmm_tbl_cfg::mac_AX_SS_WMM_TBL_SET + * Please Place Description here. + */ +enum mac_ax_ss_wmm_tbl_cfg { + MAC_AX_SS_WMM_TBL_SET, +}; + +/*--------------------Define Struct-------------------------------------*/ + +/** + * @struct mac_ax_sta_bmp_ctrl + * @brief mac_ax_sta_bmp_ctrl + * + * @var mac_ax_sta_bmp_ctrl::macid + * Please Place Description here. + * @var mac_ax_sta_bmp_ctrl::bmp + * Please Place Description here. + * @var mac_ax_sta_bmp_ctrl::mask + * Please Place Description here. + */ +struct mac_ax_sta_bmp_ctrl { + u8 macid; + u32 bmp; + u32 mask; +}; + +/*--------------------Function Prototype--------------------------------*/ + +/** + * @brief mac_ss_wmm_sta_move + * + * @param *adapter + * @param src_wmm + * @param dst_link + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ss_wmm_sta_move(struct mac_ax_adapter *adapter, + enum mac_ax_ss_wmm src_wmm, + enum mac_ax_ss_wmm_tbl dst_link); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/state_mach.h b/phl/hal_g6/mac/mac_ax/state_mach.h new file mode 100644 index 0000000..0ee9911 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/state_mach.h @@ -0,0 +1,221 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_STATE_MACH_H_ +#define _MAC_AX_STATE_MACH_H_ + +/** + * @struct mac_ax_state_mach + * @brief mac_ax_state_mach + * + * @var mac_ax_state_mach::pwr + * Please Place Description here. + * @var mac_ax_state_mach::fwdl + * Please Place Description here. + * @var mac_ax_state_mach::efuse + * Please Place Description here. + * @var mac_ax_state_mach::read_request + * Please Place Description here. + * @var mac_ax_state_mach::write_request + * Please Place Description here. + * @var mac_ax_state_mach::conf_request + * Please Place Description here. + * @var mac_ax_state_mach::write_h2c + * Please Place Description here. + * @var mac_ax_state_mach::conf_h2c + * Please Place Description here. + * @var mac_ax_state_mach::read_h2c + * Please Place Description here. + * @var mac_ax_state_mach::pkt_ofld + * Please Place Description here. + * @var mac_ax_state_mach::efuse_ofld + * Please Place Description here. + * @var mac_ax_state_mach::macid_pause + * Please Place Description here. + * @var mac_ax_state_mach::mcc_group + * Please Place Description here. + * @var mac_ax_state_mach::mcc_request + * Please Place Description here. + * @var mac_ax_state_mach::fw_rst + * Please Place Description here. + * @var mac_ax_state_mach::aoac_rpt + * Please Place Description here. + */ + +/** + * @struct mac_ax_state_mach + * @brief mac_ax_state_mach + * + * @var mac_ax_state_mach::pwr + * Please Place Description here. + * @var mac_ax_state_mach::fwdl + * Please Place Description here. + * @var mac_ax_state_mach::efuse + * Please Place Description here. + * @var mac_ax_state_mach::read_request + * Please Place Description here. + * @var mac_ax_state_mach::write_request + * Please Place Description here. + * @var mac_ax_state_mach::conf_request + * Please Place Description here. + * @var mac_ax_state_mach::write_h2c + * Please Place Description here. + * @var mac_ax_state_mach::conf_h2c + * Please Place Description here. + * @var mac_ax_state_mach::read_h2c + * Please Place Description here. + * @var mac_ax_state_mach::pkt_ofld + * Please Place Description here. + * @var mac_ax_state_mach::efuse_ofld + * Please Place Description here. + * @var mac_ax_state_mach::macid_pause + * Please Place Description here. + * @var mac_ax_state_mach::mcc_group + * Please Place Description here. + * @var mac_ax_state_mach::mcc_request + * Please Place Description here. + * @var mac_ax_state_mach::fw_rst + * Please Place Description here. + * @var mac_ax_state_mach::aoac_rpt + * Please Place Description here. + * @var mac_ax_state_mach::p2p_stat + * Please Place Description here. + */ +struct mac_ax_state_mach { +#define MAC_AX_PWR_OFF 0 +#define MAC_AX_PWR_ON 1 +#define MAC_AX_PWR_PRE_OFF 2 +#define MAC_AX_PWR_ERR 3 + u8 pwr; +#define MAC_AX_FWDL_IDLE 0 +#define MAC_AX_FWDL_CPU_ON 1 +#define MAC_AX_FWDL_H2C_PATH_RDY 2 +#define MAC_AX_FWDL_PATH_RDY 3 +#define MAC_AX_FWDL_INIT_RDY 4 + u8 fwdl; +#define MAC_AX_EFUSE_IDLE 0 +#define MAC_AX_EFUSE_PHY 1 +#define MAC_AX_EFUSE_LOG_MAP 2 +#define MAC_AX_EFUSE_LOG_MASK 3 +#define MAC_AX_EFUSE_MAX 4 + u8 efuse; +#define MAC_AX_OFLD_REQ_IDLE 0 +#define MAC_AX_OFLD_REQ_H2C_SENT 1 +#define MAC_AX_OFLD_REQ_CREATED 2 +#define MAC_AX_OFLD_REQ_CLEANED 3 + u8 read_request; + u8 write_request; + u8 conf_request; +#define MAC_AX_CMD_OFLD_IDLE 0 +#define MAC_AX_CMD_OFLD_PROC 1 +#define MAC_AX_CMD_OFLD_SENDING 2 +#define MAC_AX_CMD_OFLD_RCVD 3 + u8 cmd_state; +#define MAC_AX_OFLD_H2C_IDLE 0 +#define MAC_AX_OFLD_H2C_SENDING 1 +#define MAC_AX_OFLD_H2C_RCVD 2 +#define MAC_AX_OFLD_H2C_ERROR 4 + u8 write_h2c; + u8 conf_h2c; +#define MAC_AX_OFLD_H2C_DONE 3 + u8 read_h2c; + u8 pkt_ofld; + u8 efuse_ofld; + u8 macid_pause; +#define MAC_AX_MCC_EMPTY 0 +#define MAC_AX_MCC_STATE_H2C_SENT 1 +#define MAC_AX_MCC_STATE_H2C_RCVD 2 +#define MAC_AX_MCC_ADD_DONE 3 +#define MAC_AX_MCC_START_DONE 4 +#define MAC_AX_MCC_STOP_DONE 5 +#define MAC_AX_MCC_STATE_ERROR 6 + u8 mcc_group[4]; +#define MAC_AX_MCC_REQ_IDLE 0 +#define MAC_AX_MCC_REQ_H2C_SENT 1 +#define MAC_AX_MCC_REQ_H2C_RCVD 2 +#define MAC_AX_MCC_REQ_DONE 3 +#define MAC_AX_MCC_REQ_FAIL 4 + u8 mcc_request[4]; +#define MAC_AX_FW_RESET_IDLE 0 +#define MAC_AX_FW_RESET_RECV 1 +#define MAC_AX_FW_RESET_RECV_DONE 2 +#define MAC_AX_FW_RESET_PROCESS 3 + u8 fw_rst; +#define MAC_AX_AOAC_RPT_IDLE 0 +#define MAC_AX_AOAC_RPT_H2C_SENDING 1 +#define MAC_AX_AOAC_RPT_H2C_RCVD 2 +#define MAC_AX_AOAC_RPT_H2C_DONE 3 +#define MAC_AX_AOAC_RPT_ERROR 4 + u8 aoac_rpt; +#define MAC_AX_P2P_ACT_IDLE 0 +#define MAC_AX_P2P_ACT_BUSY 1 +#define MAC_AX_P2P_ACT_FAIL 2 + u8 p2p_stat; +#define MAC_AX_FUNC_OFF 0 +#define MAC_AX_FUNC_ON 1 + u8 dmac_func; + u8 cmac0_func; + u8 cmac1_func; + u8 bb0_func; + u8 bb1_func; +#define MAC_AX_WOW_STOPTRX_IDLE 0 +#define MAC_AX_WOW_STOPTRX_BUSY 1 +#define MAC_AX_WOW_STOPTRX_FAIL 2 + u8 wow_stoptrx_stat; +#define MAC_AX_MAC_NOT_RDY 0 +#define MAC_AX_MAC_RDY 1 +#define MAC_AX_MAC_INIT_ERR 2 +#define MAC_AX_MAC_DEINIT_ERR 3 +#define MAC_AX_MAC_FINIT_ERR 4 +#define MAC_AX_MAC_FDEINIT_ERR 5 + u8 mac_rdy; +#define MAC_AX_ROLE_ALOC_SUCC 0 +#define MAC_AX_ROLE_INIT_SUCC 1 +#define MAC_AX_ROLE_HW_UPD_SUCC 2 +#define MAC_AX_ROLE_ALOC_FAIL 3 +#define MAC_AX_ROLE_INIT_FAIL 4 +#define MAC_AX_ROLE_HW_UPD_FAIL 5 + u8 role_stat; +#define MAC_AX_PLAT_OFF 0 +#define MAC_AX_PLAT_ON 1 + u8 plat; +#define MAC_AX_IO_ST_NORM 0 +#define MAC_AX_IO_ST_HANG 1 + u8 io_st; +#define MAC_AX_L2_DIS 0 +#define MAC_AX_L2_EN 1 +#define MAC_AX_L2_TRIG 2 + u8 l2_st; +#define MAC_AX_SER_CTRL_SRT 0 +#define MAC_AX_SER_CTRL_STOP 1 +#define MAC_AX_SER_CTRL_ERR 2 + u8 ser_ctrl_st; +#define MAC_AX_CH_SWITCH_GET_RPT 4 + u8 ch_switch; +}; + +#define MAC_AX_DFLT_SM \ + {MAC_AX_PWR_OFF, MAC_AX_FWDL_IDLE, MAC_AX_EFUSE_IDLE, \ + MAC_AX_OFLD_REQ_IDLE, MAC_AX_OFLD_REQ_IDLE, MAC_AX_OFLD_REQ_IDLE, \ + MAC_AX_CMD_OFLD_IDLE, MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, \ + MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, \ + MAC_AX_OFLD_H2C_IDLE, {MAC_AX_MCC_EMPTY}, {MAC_AX_MCC_REQ_IDLE}, \ + MAC_AX_FW_RESET_IDLE, MAC_AX_AOAC_RPT_IDLE, MAC_AX_P2P_ACT_IDLE, \ + MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, \ + MAC_AX_FUNC_OFF, MAC_AX_WOW_STOPTRX_IDLE, MAC_AX_MAC_NOT_RDY, \ + MAC_AX_ROLE_ALOC_SUCC, MAC_AX_PLAT_OFF, MAC_AX_IO_ST_NORM, \ + MAC_AX_L2_EN, MAC_AX_SER_CTRL_SRT} +#endif diff --git a/phl/hal_g6/mac/mac_ax/status.c b/phl/hal_g6/mac/mac_ax/status.c new file mode 100644 index 0000000..b3024d2 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/status.c @@ -0,0 +1,149 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "status.h" + +u32 mac_get_ft_status(struct mac_ax_adapter *adapter, + enum mac_ax_feature mac_ft, enum mac_ax_status *stat, + u8 *buf, const u32 size, u32 *ret_size) + +{ + struct mac_ax_ft_status *ft_stat; + + ft_stat = mac_get_ft(adapter, mac_ft); + + if (!ft_stat) + return MACNOITEM; + + if (!buf) + return MACNPTR; + + *stat = ft_stat->status; + if (ft_stat->size) { + if (size < ft_stat->size) + return MACNOBUF; + PLTFM_MEMCMP(buf, ft_stat->buf, ft_stat->size); + *ret_size = ft_stat->size; + } + + return MACSUCCESS; +} + +struct mac_ax_ft_status *mac_get_ft(struct mac_ax_adapter *adapter, + enum mac_ax_feature mac_ft) +{ + struct mac_ax_ft_status *ft_stat = adapter->ft_stat; + + for (; ft_stat->mac_ft != MAC_AX_FT_MAX; ft_stat++) { + if (ft_stat->mac_ft == mac_ft) + return ft_stat; + } + + PLTFM_MSG_ERR("The mac feature is not supported\n"); + + return NULL; +} + +u32 set_hw_ch_busy_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_ch_busy_cnt_cfg *cfg) +{ + u8 band; + u32 ret; + u32 reg_addr; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + band = cfg->band; + reg_addr = (band ? R_AX_PTCL_ATM_C1 : R_AX_PTCL_ATM); + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + switch (cfg->cnt_ctrl) { + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN: + MAC_REG_W32(reg_addr, + MAC_REG_R32(reg_addr) | B_AX_CHNL_INFO_EN); + break; + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS: + MAC_REG_W32(reg_addr, + MAC_REG_R32(reg_addr) & ~B_AX_CHNL_INFO_EN); + break; + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST: + val32 = MAC_REG_R32(reg_addr); + MAC_REG_W32(reg_addr, val32 | B_AX_RST_CHNL_BUSY); + MAC_REG_W32(reg_addr, val32 & ~B_AX_RST_CHNL_BUSY); + break; + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST: + val32 = MAC_REG_R32(reg_addr); + MAC_REG_W32(reg_addr, val32 | B_AX_RST_CHNL_IDLE); + MAC_REG_W32(reg_addr, val32 & ~B_AX_RST_CHNL_IDLE); + break; + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_RST: + val32 = MAC_REG_R32(reg_addr); + MAC_REG_W32(reg_addr, val32 | + (B_AX_RST_CHNL_IDLE | B_AX_RST_CHNL_BUSY)); + MAC_REG_W32(reg_addr, val32 & + ~(B_AX_RST_CHNL_IDLE | B_AX_RST_CHNL_BUSY)); + break; + case MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF: + val32 = MAC_REG_R32(reg_addr) & + ~(B_AX_CHNL_REF_RX_BASIC_NAV | + B_AX_CHNL_REF_RX_INTRA_NAV | + B_AX_CHNL_REF_DATA_ON | + B_AX_CHNL_REF_EDCCA_P20 | + B_AX_CHNL_REF_CCA_P20 | + B_AX_CHNL_REF_CCA_S20 | + B_AX_CHNL_REF_CCA_S40 | + B_AX_CHNL_REF_CCA_S80 | + B_AX_CHNL_REF_PHY_TXON); + val32 |= (cfg->ref.basic_nav ? B_AX_CHNL_REF_RX_BASIC_NAV : 0) | + (cfg->ref.intra_nav ? B_AX_CHNL_REF_RX_INTRA_NAV : 0) | + (cfg->ref.data_on ? B_AX_CHNL_REF_DATA_ON : 0) | + (cfg->ref.edcca_p20 ? B_AX_CHNL_REF_EDCCA_P20 : 0) | + (cfg->ref.cca_p20 ? B_AX_CHNL_REF_CCA_P20 : 0) | + (cfg->ref.cca_s20 ? B_AX_CHNL_REF_CCA_S20 : 0) | + (cfg->ref.cca_s40 ? B_AX_CHNL_REF_CCA_S40 : 0) | + (cfg->ref.cca_s80 ? B_AX_CHNL_REF_CCA_S80 : 0) | + (cfg->ref.phy_txon ? B_AX_CHNL_REF_PHY_TXON : 0); + MAC_REG_W32(reg_addr, val32); + break; + default: + return MACNOITEM; + } + + return MACSUCCESS; +} + +u32 get_hw_ch_stat_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_ch_stat_cnt *cnt) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 band; + u32 ret; + + band = cnt->band; + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + cnt->busy_cnt = MAC_REG_R32(band ? R_AX_CHNL_BUSY_TIME_0_C1 : + R_AX_CHNL_BUSY_TIME_0); + cnt->idle_cnt = MAC_REG_R32(band ? R_AX_CHNL_IDLE_TIME_0_C1 : + R_AX_CHNL_IDLE_TIME_0); + + return MACSUCCESS; +} + diff --git a/phl/hal_g6/mac/mac_ax/status.h b/phl/hal_g6/mac/mac_ax/status.h new file mode 100644 index 0000000..af74385 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/status.h @@ -0,0 +1,73 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_STATUS_H_ +#define _MAC_AX_STATUS_H_ + +#include "../type.h" +#include "trxcfg.h" + +/** + * @brief mac_get_ft_status + * + * @param *adapter + * @param mac_ft + * @param *stat + * @param *buf + * @param size + * @param *ret_size + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_ft_status(struct mac_ax_adapter *adapter, + enum mac_ax_feature mac_ft, enum mac_ax_status *stat, + u8 *buf, const u32 size, u32 *ret_size); + +/** + * @brief mac_get_ft + * + * @param *adapter + * @param mac_ft + * @return Please Place Description here. + * @retval mac_ax_ft_status + */ + +struct mac_ax_ft_status *mac_get_ft(struct mac_ax_adapter *adapter, + enum mac_ax_feature mac_ft); + +/** + * @brief set_hw_ch_busy_cnt + * + * @param *adapter + * @param *cfg + * @return Please Place Description here. + * @retval u32 + */ +u32 set_hw_ch_busy_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_ch_busy_cnt_cfg *cfg); + +/** + * @brief get_hw_ch_stat_cnt + * + * @param *adapter + * @param *cnt + * @return Please Place Description here. + * @retval u32 + */ +u32 get_hw_ch_stat_cnt(struct mac_ax_adapter *adapter, + struct mac_ax_ch_stat_cnt *cnt); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/tblupd.c b/phl/hal_g6/mac/mac_ax/tblupd.c new file mode 100644 index 0000000..f72a733 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/tblupd.c @@ -0,0 +1,2430 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "tblupd.h" + +u32 mac_upd_mudecision_para(struct mac_ax_adapter *adapter, + struct mac_ax_mudecision_para *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_mude_para_tblud *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_mude_para_tblud)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_mude_para_tblud *)buf; + tbl->dword0 = + cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) | + SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) | + SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) | + SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) | + (info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) | + SET_WORD(CLASS_MUDECISION_PARA, + FWCMD_H2C_TBLUD_TABLE_CLASS)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->mu_thold, + FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD) | + (info->bypass_thold ? + FWCMD_H2C_MUDECISION_PARA_BYPASS_THOLD : 0) | + (info->bypass_tp ? + FWCMD_H2C_MUDECISION_PARA_BYPASS_TP : 0)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->init_rate, + FWCMD_H2C_MUDECISION_PARA_INIT_RATE) | + SET_WORD(info->retry_th, + FWCMD_H2C_MUDECISION_PARA_RETRY_TH)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_TBLUD, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_upd_ul_fixinfo(struct mac_ax_adapter *adapter, + struct mac_ax_ul_fixinfo *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_ul_fixinfo_tblud *tbl; + struct mac_ul_macid_info *sta_info; + struct mac_ul_macid_info *sta_info_2; + struct mac_ax_ulru_out_sta_ent *sta_ent; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ul_fixinfo_tblud)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_ul_fixinfo_tblud *)buf; + tbl->dword0 = + cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) | + SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) | + SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) | + SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) | + (info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) | + SET_WORD(CLASS_UL_FIXINFO, + FWCMD_H2C_TBLUD_TABLE_CLASS)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->cfg.mode, FWCMD_H2C_UL_FIXINFO_CFG_MODE) | + SET_WORD(info->cfg.interval, + FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL) | + SET_WORD(info->cfg.bsr_thold, + FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD) | + SET_WORD(info->cfg.storemode, + FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->ndpa_dur, + FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR) | + SET_WORD(info->tf_type, + FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE) | + (info->sig_ta_pkten ? + FWCMD_H2C_UL_FIXINFO_ULINFO_SIGEN : 0) | + SET_WORD(info->sig_ta_pktsc, + FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC) | + (info->murts_flag ? + FWCMD_H2C_UL_FIXINFO_ULINFO_MURTS : 0) | + SET_WORD(info->ndpa, + FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA) | + SET_WORD(info->snd_pkt_sel, + FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT) | + SET_WORD(info->gi_ltf, + FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF)); + + tbl->dword3 = + cpu_to_le32(SET_WORD(info->data_rate, + FWCMD_H2C_UL_FIXINFO_ULINFO_DATART) | + (info->data_er ? + FWCMD_H2C_UL_FIXINFO_ULINFO_DATAER : 0) | + SET_WORD(info->data_bw, + FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW) | + SET_WORD(info->data_stbc, + FWCMD_H2C_UL_FIXINFO_ULINFO_STBC) | + (info->data_ldpc ? + FWCMD_H2C_UL_FIXINFO_ULINFO_LDPC : 0) | + (info->data_dcm ? + FWCMD_H2C_UL_FIXINFO_ULINFO_DATADCM : 0) | + SET_WORD(info->apep_len, + FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN) | + (info->more_tf ? + FWCMD_H2C_UL_FIXINFO_ULINFO_MORETF : 0) | + (info->data_bw_er ? + FWCMD_H2C_UL_FIXINFO_ULINFO_DATA_VWER : 0) | + (info->istwt ? + FWCMD_H2C_UL_FIXINFO_ULINFO_ISTWT : 0)); + + tbl->dword4 = + cpu_to_le32(SET_WORD(info->multiport_id, + FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT) | + SET_WORD(info->mbssid, + FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID) | + SET_WORD(info->txpwr_mode, + FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE) | + SET_WORD(info->ulfix_usage, + FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE) | + SET_WORD(info->twtgrp_stanum_sel, + FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL) | + SET_WORD(info->store_idx, + FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX)); + + sta_info = &info->sta[0]; + sta_info_2 = &info->sta[1]; + tbl->dword5 = + cpu_to_le32(SET_WORD(sta_info->macid, + FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0) | + SET_WORD(sta_info->pref_AC, + FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0) | + SET_WORD(sta_info_2->macid, + FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1) | + SET_WORD(sta_info_2->pref_AC, + FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1)); + + sta_info = &info->sta[2]; + sta_info_2 = &info->sta[3]; + tbl->dword6 = + cpu_to_le32(SET_WORD(sta_info->macid, + FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0) | + SET_WORD(sta_info->pref_AC, + FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0) | + SET_WORD(sta_info_2->macid, + FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1) | + SET_WORD(sta_info_2->pref_AC, + FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1)); + + tbl->dword7 = + cpu_to_le32((info->ulrua.ru2su ? + FWCMD_H2C_UL_FIXINFO_ULRUA_RU2SU : 0) | + SET_WORD(info->ulrua.ppdu_bw, + FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW) | + SET_WORD(info->ulrua.gi_ltf, + FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF) | + (info->ulrua.stbc ? + FWCMD_H2C_UL_FIXINFO_ULRUA_STBC : 0) | + (info->ulrua.doppler ? + FWCMD_H2C_UL_FIXINFO_ULRUA_DOPPLER : 0) | + SET_WORD(info->ulrua.n_ltf_and_ma, + FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA) | + SET_WORD(info->ulrua.sta_num, + FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM) | + (info->ulrua.rf_gain_fix ? + FWCMD_H2C_UL_FIXINFO_ULRUA_RFGFIX : 0) | + SET_WORD(info->ulrua.rf_gain_idx, + FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX) | + SET_WORD(info->ulrua.tb_t_pe_nom, + FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM)); + + tbl->dword8 = + cpu_to_le32((info->ulrua.grp_mode ? + FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_MODE : 0) | + SET_WORD(info->ulrua.grp_id, + FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID) | + (info->ulrua.fix_mode ? + FWCMD_H2C_UL_FIXINFO_ULRUA_FIX_MODE : 0)); + + sta_ent = &info->ulrua.sta[0]; + tbl->dword9 = + cpu_to_le32((sta_ent->dropping ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) | + SET_WORD(sta_ent->tgt_rssi, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) | + SET_WORD(sta_ent->mac_id, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) | + SET_WORD(sta_ent->ru_pos, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) | + (sta_ent->coding ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) | + (sta_ent->vip_flag ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0)); + + tbl->dword10 = + cpu_to_le32(SET_WORD(sta_ent->bsr_length, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) | + (sta_ent->rate.dcm ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) | + SET_WORD(sta_ent->rate.ss, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) | + SET_WORD(sta_ent->rate.mcs, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) | + SET_WORD(sta_ent->rpt.rt_tblcol, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) | + (sta_ent->rpt.prtl_alloc ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) | + (sta_ent->rpt.rate_chg ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0)); + + sta_ent = &info->ulrua.sta[1]; + tbl->dword11 = + cpu_to_le32((sta_ent->dropping ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) | + SET_WORD(sta_ent->tgt_rssi, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) | + SET_WORD(sta_ent->mac_id, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) | + SET_WORD(sta_ent->ru_pos, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) | + (sta_ent->coding ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) | + (sta_ent->vip_flag ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0)); + tbl->dword12 = + cpu_to_le32(SET_WORD(sta_ent->bsr_length, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) | + (sta_ent->rate.dcm ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) | + SET_WORD(sta_ent->rate.ss, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) | + SET_WORD(sta_ent->rate.mcs, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) | + SET_WORD(sta_ent->rpt.rt_tblcol, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) | + (sta_ent->rpt.prtl_alloc ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) | + (sta_ent->rpt.rate_chg ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0)); + + sta_ent = &info->ulrua.sta[2]; + tbl->dword13 = + cpu_to_le32((sta_ent->dropping ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) | + SET_WORD(sta_ent->tgt_rssi, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) | + SET_WORD(sta_ent->mac_id, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) | + SET_WORD(sta_ent->ru_pos, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) | + (sta_ent->coding ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) | + (sta_ent->vip_flag ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0)); + tbl->dword14 = + cpu_to_le32(SET_WORD(sta_ent->bsr_length, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) | + (sta_ent->rate.dcm ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) | + SET_WORD(sta_ent->rate.ss, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) | + SET_WORD(sta_ent->rate.mcs, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) | + SET_WORD(sta_ent->rpt.rt_tblcol, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) | + (sta_ent->rpt.prtl_alloc ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) | + (sta_ent->rpt.rate_chg ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0)); + + sta_ent = &info->ulrua.sta[3]; + tbl->dword15 = + cpu_to_le32((sta_ent->dropping ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) | + SET_WORD(sta_ent->tgt_rssi, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) | + SET_WORD(sta_ent->mac_id, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) | + SET_WORD(sta_ent->ru_pos, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) | + (sta_ent->coding ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) | + (sta_ent->vip_flag ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0)); + + tbl->dword16 = + cpu_to_le32(SET_WORD(sta_ent->bsr_length, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) | + (sta_ent->rate.dcm ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) | + SET_WORD(sta_ent->rate.ss, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) | + SET_WORD(sta_ent->rate.mcs, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) | + SET_WORD(sta_ent->rpt.rt_tblcol, + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) | + (sta_ent->rpt.prtl_alloc ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) | + (sta_ent->rpt.rate_chg ? + FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_TBLUD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_f2p_test_cmd(struct mac_ax_adapter *adapter, + struct mac_ax_f2p_test_para *info, + struct mac_ax_f2p_wd *f2pwd, + struct mac_ax_f2p_tx_cmd *ptxcmd, + u8 *psigb_addr) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_test_para *tbl; + struct mac_ax_tf_user_para *user; + struct mac_ax_tf_depend_user_para *dep_user; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_test_para)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_test_para)); + + tbl = (struct fwcmd_test_para *)buf; + + tbl->dword0 = + cpu_to_le32(SET_WORD(info->tf_pkt.ul_bw, FWCMD_F2PTEST_ULBW) | + SET_WORD(info->tf_pkt.gi_ltf, FWCMD_F2PTEST_GILTF) | + SET_WORD(info->tf_pkt.num_he_ltf, FWCMD_F2PTEST_NUMLTF) | + SET_WORD(info->tf_pkt.ul_stbc, FWCMD_F2PTEST_ULSTBC) | + SET_WORD(info->tf_pkt.doppler, FWCMD_F2PTEST_DPLR) | + SET_WORD(info->tf_pkt.ap_tx_power, FWCMD_F2PTEST_TXPWR) | + SET_WORD(info->tf_pkt.user_num, FWCMD_F2PTEST_USERNUM) | + SET_WORD(info->tf_pkt.pktnum, FWCMD_F2PTEST_PKTNUM) | + SET_WORD(info->tf_pkt.pri20_bitmap, FWCMD_F2PTEST_BITMAP)); + + user = &info->tf_pkt.user[0]; + tbl->dword1 = + cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) | + SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) | + SET_WORD(user->macid, FWCMD_F2PTEST_MACID) | + SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) | + SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) | + SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) | + SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI)); + + user = &info->tf_pkt.user[1]; + tbl->dword3 = + cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) | + SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) | + SET_WORD(user->macid, FWCMD_F2PTEST_MACID) | + SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS)); + + tbl->dword4 = + cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) | + SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) | + SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) | + SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI)); + + user = &info->tf_pkt.user[2]; + tbl->dword5 = + cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) | + SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) | + SET_WORD(user->macid, FWCMD_F2PTEST_MACID) | + SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS)); + + tbl->dword6 = + cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) | + SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) | + SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) | + SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI)); + + user = &info->tf_pkt.user[3]; + tbl->dword7 = + cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) | + SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) | + SET_WORD(user->macid, FWCMD_F2PTEST_MACID) | + SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS)); + + tbl->dword8 = + cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) | + SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) | + SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) | + SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI)); + + dep_user = &info->tf_pkt.dep_user[0]; + tbl->byte9 = + cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC)); + + dep_user = &info->tf_pkt.dep_user[1]; + tbl->byte10 = + cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC)); + + dep_user = &info->tf_pkt.dep_user[2]; + tbl->byte11 = + cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC)); + + dep_user = &info->tf_pkt.dep_user[3]; + tbl->byte12 = + cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC)); + + tbl->dword13 = + cpu_to_le32(SET_WORD(info->tf_wd.datarate, FWCMD_F2PTEST_DATARATE) | + SET_WORD(info->tf_wd.mulport_id, FWCMD_F2PTEST_MULPORT) | + SET_WORD(info->tf_wd.pwr_ofset, FWCMD_F2PTEST_PWR_OFSET) | + SET_WORD(info->mode, FWCMD_F2PTEST_MODE) | + SET_WORD(info->frexch_type, FWCMD_F2PTEST_TYPE) | + SET_WORD(info->sigb_len, FWCMD_F2PTEST_SIGB_LEN)); + + tbl->dword14 = + cpu_to_le32(SET_WORD(f2pwd->cmd_qsel, F2P_WD_CMD_QSEL) | + (f2pwd->ls ? F2P_WD_LS : 0) | + (f2pwd->fs ? F2P_WD_FS : 0) | + SET_WORD(f2pwd->total_number, F2P_WD_TOTAL_NUMBER) | + SET_WORD(f2pwd->seq, F2P_WD_SEQ) | + SET_WORD(f2pwd->length, F2P_WD_LENGTH)); + + tbl->dword16 = + cpu_to_le32(SET_WORD(ptxcmd->cmd_type, F2P_CMD_TYPE) | + SET_WORD(ptxcmd->cmd_sub_type, F2P_CMD_SUB_TYPE) | + SET_WORD(ptxcmd->dl_user_num, F2P_DL_USER_NUM) | + SET_WORD(ptxcmd->bw, F2P_BW) | + SET_WORD(ptxcmd->tx_power, F2P_TX_POWER)); + + tbl->dword17 = + cpu_to_le32(SET_WORD(ptxcmd->fw_define, F2P_FW_DEFINE) | + SET_WORD(ptxcmd->ss_sel_mode, F2P_SS_SEL_MODE) | + SET_WORD(ptxcmd->next_qsel, F2P_NEXT_QSEL) | + SET_WORD(ptxcmd->twt_group, F2P_TWT_GROUP) | + (ptxcmd->dis_chk_slp ? F2P_DIS_CHK_SLP : 0) | + (ptxcmd->ru_mu_2_su ? F2P_RU_MU_2_SU : 0) | + SET_WORD(ptxcmd->dl_t_pe, F2P_DL_T_PE)); + + tbl->dword18 = + cpu_to_le32(SET_WORD(ptxcmd->sigb_ch1_len, F2P_SIGB_CH1_LEN) | + SET_WORD(ptxcmd->sigb_ch2_len, F2P_SIGB_CH2_LEN) | + SET_WORD(ptxcmd->sigb_sym_num, F2P_SIGB_SYM_NUM) | + SET_WORD(ptxcmd->sigb_ch2_ofs, F2P_SIGB_CH2_OFS) | + (ptxcmd->dis_htp_ack ? F2P_DIS_HTP_ACK : 0) | + SET_WORD(ptxcmd->tx_time_ref, F2P_TX_TIME_REF) | + SET_WORD(ptxcmd->pri_user_idx, F2P_PRI_USER_IDX)); + + tbl->dword19 = + cpu_to_le32(SET_WORD(ptxcmd->ampdu_max_txtime, F2P_AMPDU_MAX_TXTIME) | + SET_WORD(ptxcmd->group_id, F2P_GROUP_ID) | + (ptxcmd->twt_chk_en ? F2P_TWT_CHK_EN : 0) | + SET_WORD(ptxcmd->twt_port_id, F2P_TWT_PORT_ID)); + + tbl->dword20 = + cpu_to_le32(SET_WORD(ptxcmd->twt_start_time, F2P_TWT_START_TIME)); + + tbl->dword21 = + cpu_to_le32(SET_WORD(ptxcmd->twt_end_time, F2P_TWT_END_TIME)); + + tbl->dword22 = + cpu_to_le32(SET_WORD(ptxcmd->apep_len, F2P_APEP_LEN) | + SET_WORD(ptxcmd->tri_pad, F2P_TRI_PAD) | + SET_WORD(ptxcmd->ul_t_pe, F2P_UL_T_PE) | + SET_WORD(ptxcmd->rf_gain_idx, F2P_RF_GAIN_IDX) | + (ptxcmd->fixed_gain_en ? F2P_FIXED_GAIN_EN : 0) | + SET_WORD(ptxcmd->ul_gi_ltf, F2P_UL_GI_LTF) | + (ptxcmd->ul_doppler ? F2P_UL_DOPPLER : 0) | + (ptxcmd->ul_stbc ? F2P_UL_STBC : 0)); + + tbl->dword23 = + cpu_to_le32((ptxcmd->ul_mid_per ? F2P_UL_MID_PER : 0) | + (ptxcmd->ul_cqi_rrp_tri ? F2P_UL_CQI_RRP_TRI : 0) | + (ptxcmd->sigb_dcm ? F2P_SIGB_DCM : 0) | + (ptxcmd->sigb_comp ? F2P_SIGB_COMP : 0) | + (ptxcmd->doppler ? F2P_DOPPLER : 0) | + (ptxcmd->stbc ? F2P_STBC : 0) | + (ptxcmd->mid_per ? F2P_MID_PER : 0) | + SET_WORD(ptxcmd->gi_ltf_size, F2P_GI_LTF_SIZE) | + SET_WORD(ptxcmd->sigb_mcs, F2P_SIGB_MCS)); + + tbl->dword24 = + cpu_to_le32(SET_WORD(ptxcmd->macid_u0, F2P_MACID_U0) | + SET_WORD(ptxcmd->ac_type_u0, F2P_AC_TYPE_U0) | + SET_WORD(ptxcmd->mu_sta_pos_u0, F2P_MU_STA_POS_U0) | + SET_WORD(ptxcmd->dl_rate_idx_u0, F2P_DL_RATE_IDX_U0) | + (ptxcmd->dl_dcm_en_u0 ? F2P_TX_CMD_DL_DCM_EN_U0 : 0) | + SET_WORD(ptxcmd->ru_alo_idx_u0, F2P_RU_ALO_IDX_U0) | + (ptxcmd->rsvd6 ? BIT(22) : 0)); + + tbl->dword25 = + cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u0, F2P_PWR_BOOST_U0) | + SET_WORD(ptxcmd->agg_bmp_alo_u0, F2P_AGG_BMP_ALO_U0) | + SET_WORD(ptxcmd->ampdu_max_txnum_u0, F2P_AMPDU_MAX_NUM_U0) | + SET_WORD(ptxcmd->user_define_u0, F2P_USER_DEFINE_U0) | + SET_WORD(ptxcmd->user_define_ext_u0, F2P_USER_DEFINE_EXT_U0) + ); + + tbl->dword26 = + cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u0, F2P_UL_ADDR_IDX_U0) | + (ptxcmd->ul_dcm_u0 ? F2P_UL_DCM_U0 : 0) | + (ptxcmd->ul_fec_cod_u0 ? F2P_UL_FEC_COD_U0 : 0) | + SET_WORD(ptxcmd->ul_ru_rate_u0, F2P_UL_RU_RATE_U0) | + SET_WORD(ptxcmd->ul_ru_alo_idx_u0, F2P_UL_RU_ALO_IDX_U0)); + + tbl->dword28 = + cpu_to_le32(SET_WORD(ptxcmd->macid_u1, F2P_MACID_U1) | + SET_WORD(ptxcmd->ac_type_u1, F2P_AC_TYPE_U1) | + SET_WORD(ptxcmd->mu_sta_pos_u1, F2P_MU_STA_POS_U1) | + SET_WORD(ptxcmd->dl_rate_idx_u1, F2P_DL_RATE_IDX_U1) | + (ptxcmd->dl_dcm_en_u1 ? F2P_TX_CMD_DL_DCM_EN_U1 : 0) | + SET_WORD(ptxcmd->ru_alo_idx_u1, F2P_RU_ALO_IDX_U1) | + (ptxcmd->rsvd10 ? BIT(22) : 0)); + + tbl->dword29 = + cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u1, F2P_PWR_BOOST_U1) | + SET_WORD(ptxcmd->agg_bmp_alo_u1, F2P_AGG_BMP_ALO_U1) | + SET_WORD(ptxcmd->ampdu_max_txnum_u1, F2P_AMPDU_MAX_NUM_U1) | + SET_WORD(ptxcmd->user_define_u1, F2P_USER_DEFINE_U1) | + SET_WORD(ptxcmd->user_define_ext_u1, F2P_USER_DEFINE_EXT_U1) + ); + + tbl->dword30 = + cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u1, F2P_UL_ADDR_IDX_U1) | + (ptxcmd->ul_dcm_u1 ? F2P_UL_DCM_U1 : 0) | + (ptxcmd->ul_fec_cod_u1 ? F2P_UL_FEC_COD_U1 : 0) | + SET_WORD(ptxcmd->ul_ru_rate_u1, F2P_UL_RU_RATE_U1) | + SET_WORD(ptxcmd->ul_ru_alo_idx_u1, F2P_UL_RU_ALO_IDX_U1)); + + tbl->dword32 = + cpu_to_le32(SET_WORD(ptxcmd->macid_u2, F2P_MACID_U2) | + SET_WORD(ptxcmd->ac_type_u2, F2P_AC_TYPE_U2) | + SET_WORD(ptxcmd->mu_sta_pos_u2, F2P_MU_STA_POS_U2) | + SET_WORD(ptxcmd->dl_rate_idx_u2, F2P_DL_RATE_IDX_U2) | + (ptxcmd->dl_dcm_en_u2 ? F2P_TX_CMD_DL_DCM_EN_U2 : 0) | + SET_WORD(ptxcmd->ru_alo_idx_u2, F2P_RU_ALO_IDX_U2) | + (ptxcmd->rsvd14 ? BIT(22) : 0)); + + tbl->dword33 = + cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u2, F2P_PWR_BOOST_U2) | + SET_WORD(ptxcmd->agg_bmp_alo_u2, F2P_AGG_BMP_ALO_U2) | + SET_WORD(ptxcmd->ampdu_max_txnum_u2, F2P_AMPDU_MAX_NUM_U2) | + SET_WORD(ptxcmd->user_define_u2, F2P_USER_DEFINE_U2) | + SET_WORD(ptxcmd->user_define_ext_u2, F2P_USER_DEFINE_EXT_U2) + ); + + tbl->dword34 = + cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u2, F2P_UL_ADDR_IDX_U2) | + (ptxcmd->ul_dcm_u2 ? F2P_UL_DCM_U2 : 0) | + (ptxcmd->ul_fec_cod_u2 ? F2P_UL_FEC_COD_U2 : 0) | + SET_WORD(ptxcmd->ul_ru_rate_u2, F2P_UL_RU_RATE_U2) | + SET_WORD(ptxcmd->ul_ru_alo_idx_u2, F2P_UL_RU_ALO_IDX_U2)); + + tbl->dword36 = + cpu_to_le32(SET_WORD(ptxcmd->macid_u3, F2P_MACID_U3) | + SET_WORD(ptxcmd->ac_type_u3, F2P_AC_TYPE_U3) | + SET_WORD(ptxcmd->mu_sta_pos_u3, F2P_MU_STA_POS_U3) | + SET_WORD(ptxcmd->dl_rate_idx_u3, F2P_DL_RATE_IDX_U3) | + (ptxcmd->dl_dcm_en_u3 ? F2P_TX_CMD_DL_DCM_EN_U3 : 0) | + SET_WORD(ptxcmd->ru_alo_idx_u3, F2P_RU_ALO_IDX_U3) | + (ptxcmd->rsvd18 ? BIT(22) : 0)); + + tbl->dword37 = + cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u3, F2P_PWR_BOOST_U3) | + SET_WORD(ptxcmd->agg_bmp_alo_u3, F2P_AGG_BMP_ALO_U3) | + SET_WORD(ptxcmd->ampdu_max_txnum_u3, F2P_AMPDU_MAX_NUM_U3) | + SET_WORD(ptxcmd->user_define_u3, F2P_USER_DEFINE_U3) | + SET_WORD(ptxcmd->user_define_ext_u3, F2P_USER_DEFINE_EXT_U3) + ); + + tbl->dword38 = + cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u3, F2P_UL_ADDR_IDX_U3) | + (ptxcmd->ul_dcm_u3 ? F2P_UL_DCM_U3 : 0) | + (ptxcmd->ul_fec_cod_u3 ? F2P_UL_FEC_COD_U3 : 0) | + SET_WORD(ptxcmd->ul_ru_rate_u3, F2P_UL_RU_RATE_U3) | + SET_WORD(ptxcmd->ul_ru_alo_idx_u3, F2P_UL_RU_ALO_IDX_U3)); + + tbl->dword40 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_0, F2P_PKT_ID_0) | + (ptxcmd->valid_0 ? F2P_VALID_0 : 0) | + SET_WORD(ptxcmd->ul_user_num_0, F2P_UL_USER_NUM_0)); + + tbl->dword41 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_1, F2P_PKT_ID_1) | + (ptxcmd->valid_1 ? F2P_VALID_1 : 0) | + SET_WORD(ptxcmd->ul_user_num_1, F2P_UL_USER_NUM_1)); + + tbl->dword42 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_2, F2P_PKT_ID_2) | + (ptxcmd->valid_2 ? F2P_VALID_2 : 0) | + SET_WORD(ptxcmd->ul_user_num_2, F2P_UL_USER_NUM_2)); + + tbl->dword43 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_3, F2P_PKT_ID_3) | + (ptxcmd->valid_3 ? F2P_VALID_3 : 0) | + SET_WORD(ptxcmd->ul_user_num_3, F2P_UL_USER_NUM_3)); + + tbl->dword44 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_4, F2P_PKT_ID_4) | + (ptxcmd->valid_4 ? F2P_VALID_4 : 0) | + SET_WORD(ptxcmd->ul_user_num_4, F2P_UL_USER_NUM_4)); + + tbl->dword45 = + cpu_to_le32(SET_WORD(ptxcmd->pkt_id_5, F2P_PKT_ID_5) | + (ptxcmd->valid_5 ? F2P_VALID_5 : 0) | + SET_WORD(ptxcmd->ul_user_num_5, F2P_UL_USER_NUM_5)); + + PLTFM_MEMCPY(tbl->byte46, psigb_addr, info->sigb_len); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_F2P_TEST, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_snd_test_cmd(struct mac_ax_adapter *adapter, + u8 *cmd_buf) +{ + return MACSUCCESS; +} + +u32 mac_upd_dctl_info(struct mac_ax_adapter *adapter, + struct mac_ax_dctl_info *info, + struct mac_ax_dctl_info *mask, u8 macid, u8 operation) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_dctlinfo_ud *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_dctlinfo_ud)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_dctlinfo_ud *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(macid, FWCMD_H2C_DCTLINFO_UD_MACID) | + (operation ? FWCMD_H2C_DCTLINFO_UD_OP : 0)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->qos_field_h, FWCMD_H2C_DCTRL_QOS_FIELD_H) | + SET_WORD(info->hw_exseq_macid, FWCMD_H2C_DCTRL_HW_EXSEQ_MACID) | + (info->qos_field_h_en ? FWCMD_H2C_DCTRL_QOS_FIELD_H_EN : 0) | + SET_WORD(info->aes_iv_l, FWCMD_H2C_DCTRL_AES_IV_L)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->aes_iv_h, FWCMD_H2C_DCTRL_AES_IV_H)); + + tbl->dword3 = + cpu_to_le32(SET_WORD(info->seq0, FWCMD_H2C_DCTRL_SEQ0) | + SET_WORD(info->seq1, FWCMD_H2C_DCTRL_SEQ1) | + SET_WORD(info->amsdu_max_length, FWCMD_H2C_DCTRL_AMSDU_MAX_LEN) | + (info->sta_amsdu_en ? FWCMD_H2C_DCTRL_STA_AMSDU_EN : 0) | + (info->chksum_offload_en ? FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN : 0) | + (info->with_llc ? FWCMD_H2C_DCTRL_WITH_LLC : 0) | + (info->sec_hw_enc ? FWCMD_H2C_DCTRL_SEC_HW_ENC : 0)); + + tbl->dword4 = + cpu_to_le32(SET_WORD(info->seq2, FWCMD_H2C_DCTRL_SEQ2) | + SET_WORD(info->seq3, FWCMD_H2C_DCTRL_SEQ3) | + SET_WORD(info->sec_cam_idx, FWCMD_H2C_DCTRL_SEC_CAM_IDX)); + + tbl->dword5 = + cpu_to_le32(SET_WORD(mask->qos_field_h, FWCMD_H2C_DCTRL_QOS_FIELD_H) | + SET_WORD(mask->hw_exseq_macid, FWCMD_H2C_DCTRL_HW_EXSEQ_MACID) | + (mask->qos_field_h_en ? FWCMD_H2C_DCTRL_QOS_FIELD_H_EN : 0) | + SET_WORD(mask->aes_iv_l, FWCMD_H2C_DCTRL_AES_IV_L)); + + tbl->dword6 = + cpu_to_le32(SET_WORD(mask->aes_iv_h, FWCMD_H2C_DCTRL_AES_IV_H)); + + tbl->dword7 = + cpu_to_le32(SET_WORD(mask->seq0, FWCMD_H2C_DCTRL_SEQ0) | + SET_WORD(mask->seq1, FWCMD_H2C_DCTRL_SEQ1) | + SET_WORD(mask->amsdu_max_length, FWCMD_H2C_DCTRL_AMSDU_MAX_LEN) | + (mask->sta_amsdu_en ? FWCMD_H2C_DCTRL_STA_AMSDU_EN : 0) | + (mask->chksum_offload_en ? FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN : 0) | + (mask->with_llc ? FWCMD_H2C_DCTRL_WITH_LLC : 0) | + (mask->sec_hw_enc ? FWCMD_H2C_DCTRL_SEC_HW_ENC : 0)); + + tbl->dword8 = + cpu_to_le32(SET_WORD(mask->seq2, FWCMD_H2C_DCTRL_SEQ2) | + SET_WORD(mask->seq3, FWCMD_H2C_DCTRL_SEQ3) | + SET_WORD(mask->sec_cam_idx, FWCMD_H2C_DCTRL_SEC_CAM_IDX)); + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_DCTLINFO_UD, + 0, + 1); + if (ret) + goto fail; + + // return MACSUCCESS if h2c aggregation is enabled and enqueued successfully. + // H2C shall be sent by mac_h2c_agg_tx. + ret = h2c_agg_enqueue(adapter, h2cb); + if (ret == MACSUCCESS) + return MACSUCCESS; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + } else { +#if MAC_AX_FEATURE_DBGPKG + if (operation) + dctl_info_debug_write(adapter, macid, + (struct fwcmd_dctlinfo_ud *)buf); +#else + return MACFWNONRDY; +#endif + } + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_upd_shcut_mhdr(struct mac_ax_adapter *adapter, + struct mac_ax_shcut_mhdr *info, u8 shcut_camid) +{ + u32 ret = 0; + u32 i; + u8 *buf; + u32 *src, *dest; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_shcut_update *tbl; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) + return MACNOTSUP; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_shcut_update)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_shcut_update *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(shcut_camid, FWCMD_H2C_DCTLINFO_UD_MACID)); + src = (u32 *)info; + dest = (u32 *)(&tbl->dword1); + for (i = 0; i < (sizeof(struct mac_ax_shcut_mhdr) / 4); i++) + *(dest++) = *(src++); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_SHCUT_UPDATE, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +void _set_role_cctrl(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_info *info, + struct mac_ax_cctl_info *mask, + struct mac_ax_cctl_info *cctrl) +{ + cctrl->datarate = (cctrl->datarate & ~mask->datarate) | + (mask->datarate & info->datarate); + cctrl->force_txop = (cctrl->force_txop & ~mask->force_txop) | + (mask->force_txop & info->force_txop); + cctrl->data_bw = (cctrl->data_bw & ~mask->data_bw) | + (mask->data_bw & info->data_bw); + cctrl->data_gi_ltf = (cctrl->data_gi_ltf & ~mask->data_gi_ltf) | + (mask->data_gi_ltf & info->data_gi_ltf); + cctrl->darf_tc_index = (cctrl->darf_tc_index & ~mask->darf_tc_index) | + (mask->darf_tc_index & info->darf_tc_index); + cctrl->arfr_ctrl = (cctrl->arfr_ctrl & ~mask->arfr_ctrl) | + (mask->arfr_ctrl & info->arfr_ctrl); + cctrl->acq_rpt_en = (cctrl->acq_rpt_en & ~mask->acq_rpt_en) | + (mask->acq_rpt_en & info->acq_rpt_en); + cctrl->mgq_rpt_en = (cctrl->mgq_rpt_en & ~mask->mgq_rpt_en) | + (mask->mgq_rpt_en & info->mgq_rpt_en); + cctrl->ulq_rpt_en = (cctrl->ulq_rpt_en & ~mask->ulq_rpt_en) | + (mask->ulq_rpt_en & info->ulq_rpt_en); + cctrl->twtq_rpt_en = (cctrl->twtq_rpt_en & ~mask->twtq_rpt_en) | + (mask->twtq_rpt_en & info->twtq_rpt_en); + cctrl->disrtsfb = (cctrl->disrtsfb & ~mask->disrtsfb) | + (mask->disrtsfb & info->disrtsfb); + cctrl->disdatafb = (cctrl->disdatafb & ~mask->disdatafb) | + (mask->disdatafb & info->disdatafb); + cctrl->tryrate = (cctrl->tryrate & ~mask->tryrate) | + (mask->tryrate & info->tryrate); + cctrl->ampdu_density = (cctrl->ampdu_density & ~mask->ampdu_density) | + (mask->ampdu_density & info->ampdu_density); + + cctrl->data_rty_lowest_rate = + (cctrl->data_rty_lowest_rate & + ~mask->data_rty_lowest_rate) | + (mask->data_rty_lowest_rate & + info->data_rty_lowest_rate); + cctrl->ampdu_time_sel = (cctrl->ampdu_time_sel & + ~mask->ampdu_time_sel) | + (mask->ampdu_time_sel & info->ampdu_time_sel); + cctrl->ampdu_len_sel = (cctrl->ampdu_len_sel & ~mask->ampdu_len_sel) | + (mask->ampdu_len_sel & info->ampdu_len_sel); + cctrl->rts_txcnt_lmt_sel = + (cctrl->rts_txcnt_lmt_sel & ~mask->rts_txcnt_lmt_sel) | + (mask->rts_txcnt_lmt_sel & info->rts_txcnt_lmt_sel); + cctrl->rts_txcnt_lmt = (cctrl->rts_txcnt_lmt & ~mask->rts_txcnt_lmt) | + (mask->rts_txcnt_lmt & info->rts_txcnt_lmt); + cctrl->rtsrate = (cctrl->rtsrate & ~mask->rtsrate) | + (mask->rtsrate & info->rtsrate); + cctrl->vcs_stbc = (cctrl->vcs_stbc & ~mask->vcs_stbc) | + (mask->vcs_stbc & info->vcs_stbc); + cctrl->rts_rty_lowest_rate = + (cctrl->rts_rty_lowest_rate & + ~mask->rts_rty_lowest_rate) | + (mask->rts_rty_lowest_rate & info->rts_rty_lowest_rate); + + cctrl->data_tx_cnt_lmt = + (cctrl->data_tx_cnt_lmt & ~mask->data_tx_cnt_lmt) | + (mask->data_tx_cnt_lmt & info->data_tx_cnt_lmt); + cctrl->data_txcnt_lmt_sel = + (cctrl->data_txcnt_lmt_sel & + ~mask->data_txcnt_lmt_sel) | + (mask->data_txcnt_lmt_sel & info->data_txcnt_lmt_sel); + cctrl->max_agg_num_sel = (cctrl->max_agg_num_sel & + ~mask->max_agg_num_sel) | + (mask->max_agg_num_sel & info->max_agg_num_sel); + cctrl->rts_en = (cctrl->rts_en & ~mask->rts_en) | + (mask->rts_en & info->rts_en); + cctrl->cts2self_en = (cctrl->cts2self_en & ~mask->cts2self_en) | + (mask->cts2self_en & info->cts2self_en); + cctrl->cca_rts = (cctrl->cca_rts & ~mask->cca_rts) | + (mask->cca_rts & info->cca_rts); + cctrl->hw_rts_en = (cctrl->hw_rts_en & ~mask->hw_rts_en) | + (mask->hw_rts_en & info->hw_rts_en); + cctrl->rts_drop_data_mode = + (cctrl->rts_drop_data_mode & + ~mask->rts_drop_data_mode) | + (mask->rts_drop_data_mode & info->rts_drop_data_mode); + cctrl->ampdu_max_len = (cctrl->ampdu_max_len & ~mask->ampdu_max_len) | + (mask->ampdu_max_len & info->ampdu_max_len); + cctrl->ul_mu_dis = (cctrl->ul_mu_dis & ~mask->ul_mu_dis) | + (mask->ul_mu_dis & info->ul_mu_dis); + cctrl->ampdu_max_time = (cctrl->ampdu_max_time & + ~mask->ampdu_max_time) | + (mask->ampdu_max_time & info->ampdu_max_time); + + cctrl->max_agg_num = (cctrl->ampdu_max_time & ~mask->max_agg_num) | + (mask->ampdu_max_time & info->max_agg_num); + cctrl->ba_bmap = (cctrl->ba_bmap & ~mask->ba_bmap) | + (mask->ba_bmap & info->ba_bmap); + cctrl->vo_lftime_sel = (cctrl->vo_lftime_sel & ~mask->vo_lftime_sel) | + (mask->vo_lftime_sel & info->vo_lftime_sel); + cctrl->vi_lftime_sel = (cctrl->vi_lftime_sel & ~mask->vi_lftime_sel) | + (mask->vi_lftime_sel & info->vi_lftime_sel); + cctrl->be_lftime_sel = (cctrl->be_lftime_sel & ~mask->be_lftime_sel) | + (mask->be_lftime_sel & info->be_lftime_sel); + cctrl->bk_lftime_sel = (cctrl->bk_lftime_sel & ~mask->bk_lftime_sel) | + (mask->bk_lftime_sel & info->bk_lftime_sel); + cctrl->sectype = (cctrl->bk_lftime_sel & ~mask->sectype) | + (mask->bk_lftime_sel & info->sectype); + + cctrl->multi_port_id = (cctrl->multi_port_id & ~mask->multi_port_id) | + (mask->multi_port_id & info->multi_port_id); + cctrl->bmc = (cctrl->multi_port_id & ~mask->bmc) | + (mask->multi_port_id & info->bmc); + cctrl->mbssid = (cctrl->mbssid & ~mask->mbssid) | + (mask->mbssid & info->mbssid); + cctrl->navusehdr = (cctrl->navusehdr & ~mask->navusehdr) | + (mask->navusehdr & info->navusehdr); + cctrl->txpwr_mode = (cctrl->txpwr_mode & ~mask->txpwr_mode) | + (mask->txpwr_mode & info->txpwr_mode); + cctrl->data_dcm = (cctrl->data_dcm & ~mask->data_dcm) | + (mask->data_dcm & info->data_dcm); + cctrl->data_er = (cctrl->data_er & ~mask->data_er) | + (mask->data_er & info->data_er); + cctrl->data_ldpc = (cctrl->data_ldpc & ~mask->data_ldpc) | + (mask->data_ldpc & info->data_ldpc); + cctrl->data_stbc = (cctrl->data_stbc & ~mask->data_stbc) | + (mask->data_stbc & info->data_stbc); + cctrl->a_ctrl_bqr = (cctrl->a_ctrl_bqr & ~mask->a_ctrl_bqr) | + (mask->a_ctrl_bqr & info->a_ctrl_bqr); + cctrl->a_ctrl_uph = (cctrl->a_ctrl_uph & ~mask->a_ctrl_uph) | + (mask->a_ctrl_uph & info->a_ctrl_uph); + cctrl->a_ctrl_bsr = (cctrl->a_ctrl_bsr & ~mask->a_ctrl_bsr) | + (mask->a_ctrl_bsr & info->a_ctrl_bsr); + cctrl->a_ctrl_cas = (cctrl->a_ctrl_cas & ~mask->a_ctrl_cas) | + (mask->a_ctrl_cas & info->a_ctrl_cas); + cctrl->data_bw_er = (cctrl->data_bw_er & ~mask->data_bw_er) | + (mask->data_bw_er & info->data_bw_er); + cctrl->lsig_txop_en = (cctrl->lsig_txop_en & ~mask->lsig_txop_en) | + (mask->lsig_txop_en & info->lsig_txop_en); + cctrl->ctrl_cnt_vld = (cctrl->ctrl_cnt_vld & ~mask->ctrl_cnt_vld) | + (mask->ctrl_cnt_vld & info->ctrl_cnt_vld); + cctrl->ctrl_cnt = (cctrl->ctrl_cnt & ~mask->ctrl_cnt) | + (mask->ctrl_cnt & info->ctrl_cnt); + + cctrl->resp_ref_rate = (cctrl->resp_ref_rate & ~mask->resp_ref_rate) | + (mask->resp_ref_rate & info->resp_ref_rate); + cctrl->all_ack_support = + (cctrl->all_ack_support & ~mask->all_ack_support) | + (mask->all_ack_support & info->all_ack_support); + cctrl->bsr_queue_size_format = + (cctrl->bsr_queue_size_format & + ~mask->bsr_queue_size_format) | + (mask->bsr_queue_size_format & + info->bsr_queue_size_format); + cctrl->ntx_path_en = (cctrl->ntx_path_en & ~mask->ntx_path_en) | + (mask->ntx_path_en & info->ntx_path_en); + cctrl->path_map_a = (cctrl->ntx_path_en & ~mask->path_map_a) | + (mask->ntx_path_en & info->path_map_a); + cctrl->path_map_b = (cctrl->path_map_b & ~mask->path_map_b) | + (mask->path_map_b & info->path_map_b); + cctrl->path_map_c = (cctrl->path_map_c & ~mask->path_map_c) | + (mask->path_map_c & info->path_map_c); + cctrl->path_map_d = (cctrl->path_map_d & ~mask->path_map_d) | + (mask->path_map_d & info->path_map_d); + cctrl->antsel_a = (cctrl->antsel_a & ~mask->antsel_a) | + (mask->antsel_a & info->antsel_a); + cctrl->antsel_b = (cctrl->antsel_b & ~mask->antsel_b) | + (mask->antsel_b & info->antsel_b); + cctrl->antsel_c = (cctrl->antsel_c & ~mask->antsel_c) | + (mask->antsel_c & info->antsel_c); + cctrl->antsel_d = (cctrl->antsel_d & ~mask->antsel_d) | + (mask->antsel_d & info->antsel_d); + + cctrl->addr_cam_index = (cctrl->addr_cam_index & + ~mask->addr_cam_index) | + (mask->addr_cam_index & info->addr_cam_index); + cctrl->paid = (cctrl->paid & ~mask->paid) | + (mask->paid & info->paid); + cctrl->uldl = (cctrl->uldl & ~mask->uldl) | + (mask->uldl & info->uldl); + cctrl->doppler_ctrl = (cctrl->doppler_ctrl & ~mask->doppler_ctrl) | + (mask->doppler_ctrl & info->doppler_ctrl); + cctrl->nominal_pkt_padding = + (cctrl->nominal_pkt_padding & + ~mask->nominal_pkt_padding) | + (mask->nominal_pkt_padding & info->nominal_pkt_padding); + cctrl->nominal_pkt_padding40 = + (cctrl->nominal_pkt_padding40 & + ~mask->nominal_pkt_padding40) | + (mask->nominal_pkt_padding40 & + info->nominal_pkt_padding40); + cctrl->nominal_pkt_padding80 = + (cctrl->nominal_pkt_padding80 & + ~mask->nominal_pkt_padding80) | + (mask->nominal_pkt_padding80 & + info->nominal_pkt_padding80); + cctrl->txpwr_tolerence = + (cctrl->txpwr_tolerence & ~mask->txpwr_tolerence) | + (mask->txpwr_tolerence & info->txpwr_tolerence); + + cctrl->nc = (cctrl->nc & ~mask->nc) | + (mask->nc & info->nc); + cctrl->nr = (cctrl->nr & ~mask->nr) | + (mask->nr & info->nr); + cctrl->ng = (cctrl->ng & ~mask->ng) | + (mask->ng & info->ng); + cctrl->cb = (cctrl->cb & ~mask->cb) | + (mask->cb & info->cb); + cctrl->cs = (cctrl->cs & ~mask->cs) | + (mask->cs & info->cs); + cctrl->csi_txbf_en = (cctrl->csi_txbf_en & ~mask->csi_txbf_en) | + (mask->csi_txbf_en & info->csi_txbf_en); + cctrl->csi_stbc_en = (cctrl->csi_stbc_en & ~mask->csi_stbc_en) | + (mask->csi_stbc_en & info->csi_stbc_en); + cctrl->csi_ldpc_en = (cctrl->csi_ldpc_en & ~mask->csi_ldpc_en) | + (mask->csi_ldpc_en & info->csi_ldpc_en); + cctrl->csi_para_en = (cctrl->csi_para_en & ~mask->csi_para_en) | + (mask->csi_para_en & info->csi_para_en); + cctrl->csi_fix_rate = (cctrl->csi_fix_rate & ~mask->csi_fix_rate) | + (mask->csi_fix_rate & info->csi_fix_rate); + cctrl->csi_gi_ltf = (cctrl->csi_gi_ltf & ~mask->csi_gi_ltf) | + (mask->csi_gi_ltf & info->csi_gi_ltf); + cctrl->nominal_pkt_padding160 = + (cctrl->nominal_pkt_padding160 & + ~mask->nominal_pkt_padding160) | + (mask->nominal_pkt_padding160 & + info->nominal_pkt_padding160); + cctrl->csi_bw = (cctrl->csi_bw & ~mask->csi_bw) | + (mask->csi_bw & info->csi_bw); +} + +void mac_upd_role_cctrl(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_info *info, + struct mac_ax_cctl_info *mask, u8 macid) +{ + struct mac_role_tbl *role; + + role = mac_role_srch(adapter, macid); + if (!role) { + PLTFM_MSG_ERR("role search failed\n"); + return; + } + _set_role_cctrl(adapter, info, mask, &role->info.c_info); +} + +u32 mac_upd_cctl_info(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_info *info, + struct mac_ax_cctl_info *mask, u8 macid, u8 operation) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_cctlinfo_ud *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_cctlinfo_ud)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_cctlinfo_ud *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(macid, FWCMD_H2C_CCTLINFO_UD_MACID) | + (operation ? FWCMD_H2C_CCTLINFO_UD_OP : 0)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->datarate, FWCMD_H2C_CCTRL_DATARATE) | + (info->force_txop ? FWCMD_H2C_CCTRL_FORCE_TXOP : 0) | + SET_WORD(info->data_bw, FWCMD_H2C_CCTRL_DATA_BW) | + SET_WORD(info->data_gi_ltf, FWCMD_H2C_CCTRL_DATA_GI_LTF) | + (info->darf_tc_index ? FWCMD_H2C_CCTRL_DARF_TC_INDEX : 0) | + SET_WORD(info->arfr_ctrl, FWCMD_H2C_CCTRL_ARFR_CTRL) | + (info->acq_rpt_en ? FWCMD_H2C_CCTRL_ACQ_RPT_EN : 0) | + (info->mgq_rpt_en ? FWCMD_H2C_CCTRL_MGQ_RPT_EN : 0) | + (info->ulq_rpt_en ? FWCMD_H2C_CCTRL_ULQ_RPT_EN : 0) | + (info->twtq_rpt_en ? FWCMD_H2C_CCTRL_TWTQ_RPT_EN : 0) | + (info->disrtsfb ? FWCMD_H2C_CCTRL_DISRTSFB : 0) | + (info->disdatafb ? FWCMD_H2C_CCTRL_DISDATAFB : 0) | + (info->tryrate ? FWCMD_H2C_CCTRL_TRYRATE : 0) | + SET_WORD(info->ampdu_density, FWCMD_H2C_CCTRL_AMPDU_DENSITY)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->data_rty_lowest_rate, + FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE) | + (info->ampdu_time_sel ? FWCMD_H2C_CCTRL_AMPDU_TIME_SEL : 0) | + (info->ampdu_len_sel ? FWCMD_H2C_CCTRL_AMPDU_LEN_SEL : 0) | + (info->rts_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL : + 0) | + SET_WORD(info->rts_txcnt_lmt, FWCMD_H2C_CCTRL_RTS_TXCNT_LMT) | + SET_WORD(info->rtsrate, FWCMD_H2C_CCTRL_RTSRATE) | + (info->vcs_stbc ? FWCMD_H2C_CCTRL_VCS_STBC : 0) | + SET_WORD(info->rts_rty_lowest_rate, + FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE)); + + tbl->dword3 = + cpu_to_le32(SET_WORD(info->data_tx_cnt_lmt, FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT) | + (info->data_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL : + 0) | + (info->max_agg_num_sel ? FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL : 0) | + (info->rts_en ? FWCMD_H2C_CCTRL_RTS_EN : 0) | + (info->cts2self_en ? FWCMD_H2C_CCTRL_CTS2SELF_EN : 0) | + SET_WORD(info->cca_rts, FWCMD_H2C_CCTRL_CCA_RTS) | + (info->hw_rts_en ? FWCMD_H2C_CCTRL_HW_RTS_EN : 0) | + SET_WORD(info->rts_drop_data_mode, + FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE) | + SET_WORD(info->ampdu_max_len, FWCMD_H2C_CCTRL_AMPDU_MAX_LEN) | + (info->ul_mu_dis ? FWCMD_H2C_CCTRL_UL_MU_DIS : 0) | + SET_WORD(info->ampdu_max_time, FWCMD_H2C_CCTRL_AMPDU_MAX_TIME)); + + tbl->dword4 = + cpu_to_le32(SET_WORD(info->max_agg_num, FWCMD_H2C_CCTRL_MAX_AGG_NUM) | + SET_WORD(info->ba_bmap, FWCMD_H2C_CCTRL_BA_BMAP) | + SET_WORD(info->vo_lftime_sel, FWCMD_H2C_CCTRL_VO_LFTIME_SEL) | + SET_WORD(info->vi_lftime_sel, FWCMD_H2C_CCTRL_VI_LFTIME_SEL) | + SET_WORD(info->be_lftime_sel, FWCMD_H2C_CCTRL_BE_LFTIME_SEL) | + SET_WORD(info->bk_lftime_sel, FWCMD_H2C_CCTRL_BK_LFTIME_SEL) | + SET_WORD(info->sectype, FWCMD_H2C_CCTRL_SECTYPE)); + + tbl->dword5 = + cpu_to_le32(SET_WORD(info->multi_port_id, FWCMD_H2C_CCTRL_MULTI_PORT_ID) | + (info->bmc ? FWCMD_H2C_CCTRL_BMC : 0) | + SET_WORD(info->mbssid, FWCMD_H2C_CCTRL_MBSSID) | + (info->navusehdr ? FWCMD_H2C_CCTRL_NAVUSEHDR : 0) | + SET_WORD(info->txpwr_mode, FWCMD_H2C_CCTRL_TXPWR_MODE) | + (info->data_dcm ? FWCMD_H2C_CCTRL_DATA_DCM : 0) | + (info->data_er ? FWCMD_H2C_CCTRL_DATA_ER : 0) | + (info->data_ldpc ? FWCMD_H2C_CCTRL_DATA_LDPC : 0) | + (info->data_stbc ? FWCMD_H2C_CCTRL_DATA_STBC : 0) | + (info->a_ctrl_bqr ? FWCMD_H2C_CCTRL_A_CTRL_BQR : 0) | + (info->a_ctrl_uph ? FWCMD_H2C_CCTRL_A_CTRL_UPH : 0) | + (info->a_ctrl_bsr ? FWCMD_H2C_CCTRL_A_CTRL_BSR : 0) | + (info->a_ctrl_cas ? FWCMD_H2C_CCTRL_A_CTRL_CAS : 0) | + (info->data_bw_er ? FWCMD_H2C_CCTRL_DATA_BW_ER : 0) | + (info->lsig_txop_en ? FWCMD_H2C_CCTRL_LSIG_TXOP_EN : 0) | + (info->ctrl_cnt_vld ? FWCMD_H2C_CCTRL_CTRL_CNT_VLD : 0) | + SET_WORD(info->ctrl_cnt, FWCMD_H2C_CCTRL_CTRL_CNT)); + + tbl->dword6 = + cpu_to_le32(SET_WORD(info->resp_ref_rate, FWCMD_H2C_CCTRL_RESP_REF_RATE) | + (info->all_ack_support ? FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT : 0) | + (info->bsr_queue_size_format ? + FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT : 0) | + SET_WORD(info->ntx_path_en, FWCMD_H2C_CCTRL_NTX_PATH_EN) | + SET_WORD(info->path_map_a, FWCMD_H2C_CCTRL_PATH_MAP_A) | + SET_WORD(info->path_map_b, FWCMD_H2C_CCTRL_PATH_MAP_B) | + SET_WORD(info->path_map_c, FWCMD_H2C_CCTRL_PATH_MAP_C) | + SET_WORD(info->path_map_d, FWCMD_H2C_CCTRL_PATH_MAP_D) | + (info->antsel_a ? FWCMD_H2C_CCTRL_ANTSEL_A : 0) | + (info->antsel_b ? FWCMD_H2C_CCTRL_ANTSEL_B : 0) | + (info->antsel_c ? FWCMD_H2C_CCTRL_ANTSEL_C : 0) | + (info->antsel_d ? FWCMD_H2C_CCTRL_ANTSEL_D : 0)); + + tbl->dword7 = + cpu_to_le32(SET_WORD(info->addr_cam_index, FWCMD_H2C_CCTRL_ADDR_CAM_INDEX) | + SET_WORD(info->paid, FWCMD_H2C_CCTRL_PAID) | + (info->uldl ? FWCMD_H2C_CCTRL_ULDL : 0) | + SET_WORD(info->doppler_ctrl, FWCMD_H2C_CCTRL_DOPPLER_CTRL) | + SET_WORD(info->nominal_pkt_padding, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING) | + SET_WORD(info->nominal_pkt_padding40, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40) | + SET_WORD(info->nominal_pkt_padding80, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80) | + SET_WORD(info->txpwr_tolerence, FWCMD_H2C_CCTRL_TXPWR_TOLERENCE)); + + tbl->dword8 = + cpu_to_le32(SET_WORD(info->nc, FWCMD_H2C_CCTRL_NC) | + SET_WORD(info->nr, FWCMD_H2C_CCTRL_NR) | + SET_WORD(info->ng, FWCMD_H2C_CCTRL_NG) | + SET_WORD(info->cb, FWCMD_H2C_CCTRL_CB) | + SET_WORD(info->cs, FWCMD_H2C_CCTRL_CS) | + (info->csi_txbf_en ? FWCMD_H2C_CCTRL_CSI_TXBF_EN : 0) | + (info->csi_stbc_en ? FWCMD_H2C_CCTRL_CSI_STBC_EN : 0) | + (info->csi_ldpc_en ? FWCMD_H2C_CCTRL_CSI_LDPC_EN : 0) | + (info->csi_para_en ? FWCMD_H2C_CCTRL_CSI_PARA_EN : 0) | + SET_WORD(info->csi_fix_rate, FWCMD_H2C_CCTRL_CSI_FIX_RATE) | + SET_WORD(info->csi_gi_ltf, FWCMD_H2C_CCTRL_CSI_GI_LTF) | + SET_WORD(info->nominal_pkt_padding160, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160) | + SET_WORD(info->csi_bw, FWCMD_H2C_CCTRL_CSI_BW)); + + tbl->dword9 = + cpu_to_le32(SET_WORD(mask->datarate, FWCMD_H2C_CCTRL_DATARATE) | + (mask->force_txop ? FWCMD_H2C_CCTRL_FORCE_TXOP : 0) | + SET_WORD(mask->data_bw, FWCMD_H2C_CCTRL_DATA_BW) | + SET_WORD(mask->data_gi_ltf, FWCMD_H2C_CCTRL_DATA_GI_LTF) | + (mask->darf_tc_index ? FWCMD_H2C_CCTRL_DARF_TC_INDEX : 0) | + SET_WORD(mask->arfr_ctrl, FWCMD_H2C_CCTRL_ARFR_CTRL) | + (mask->acq_rpt_en ? FWCMD_H2C_CCTRL_ACQ_RPT_EN : 0) | + (mask->mgq_rpt_en ? FWCMD_H2C_CCTRL_MGQ_RPT_EN : 0) | + (mask->ulq_rpt_en ? FWCMD_H2C_CCTRL_ULQ_RPT_EN : 0) | + (mask->twtq_rpt_en ? FWCMD_H2C_CCTRL_TWTQ_RPT_EN : 0) | + (mask->disrtsfb ? FWCMD_H2C_CCTRL_DISRTSFB : 0) | + (mask->disdatafb ? FWCMD_H2C_CCTRL_DISDATAFB : 0) | + (mask->tryrate ? FWCMD_H2C_CCTRL_TRYRATE : 0) | + SET_WORD(mask->ampdu_density, FWCMD_H2C_CCTRL_AMPDU_DENSITY)); + + tbl->dword10 = + cpu_to_le32(SET_WORD(mask->data_rty_lowest_rate, + FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE) | + (mask->ampdu_time_sel ? FWCMD_H2C_CCTRL_AMPDU_TIME_SEL : 0) | + (mask->ampdu_len_sel ? FWCMD_H2C_CCTRL_AMPDU_LEN_SEL : 0) | + (mask->rts_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL : + 0) | + SET_WORD(mask->rts_txcnt_lmt, FWCMD_H2C_CCTRL_RTS_TXCNT_LMT) | + SET_WORD(mask->rtsrate, FWCMD_H2C_CCTRL_RTSRATE) | + (mask->vcs_stbc ? FWCMD_H2C_CCTRL_VCS_STBC : 0) | + SET_WORD(mask->rts_rty_lowest_rate, + FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE)); + + tbl->dword11 = + cpu_to_le32(SET_WORD(mask->data_tx_cnt_lmt, FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT) | + (mask->data_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL : + 0) | + (mask->max_agg_num_sel ? FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL : 0) | + (mask->rts_en ? FWCMD_H2C_CCTRL_RTS_EN : 0) | + (mask->cts2self_en ? FWCMD_H2C_CCTRL_CTS2SELF_EN : 0) | + SET_WORD(mask->cca_rts, FWCMD_H2C_CCTRL_CCA_RTS) | + (mask->hw_rts_en ? FWCMD_H2C_CCTRL_HW_RTS_EN : 0) | + SET_WORD(mask->rts_drop_data_mode, + FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE) | + SET_WORD(mask->ampdu_max_len, FWCMD_H2C_CCTRL_AMPDU_MAX_LEN) | + (mask->ul_mu_dis ? FWCMD_H2C_CCTRL_UL_MU_DIS : 0) | + SET_WORD(mask->ampdu_max_time, FWCMD_H2C_CCTRL_AMPDU_MAX_TIME)); + + tbl->dword12 = + cpu_to_le32(SET_WORD(mask->max_agg_num, FWCMD_H2C_CCTRL_MAX_AGG_NUM) | + SET_WORD(mask->ba_bmap, FWCMD_H2C_CCTRL_BA_BMAP) | + SET_WORD(mask->vo_lftime_sel, FWCMD_H2C_CCTRL_VO_LFTIME_SEL) | + SET_WORD(mask->vi_lftime_sel, FWCMD_H2C_CCTRL_VI_LFTIME_SEL) | + SET_WORD(mask->be_lftime_sel, FWCMD_H2C_CCTRL_BE_LFTIME_SEL) | + SET_WORD(mask->bk_lftime_sel, FWCMD_H2C_CCTRL_BK_LFTIME_SEL) | + SET_WORD(mask->sectype, FWCMD_H2C_CCTRL_SECTYPE)); + + tbl->dword13 = + cpu_to_le32(SET_WORD(mask->multi_port_id, FWCMD_H2C_CCTRL_MULTI_PORT_ID) | + (mask->bmc ? FWCMD_H2C_CCTRL_BMC : 0) | + SET_WORD(mask->mbssid, FWCMD_H2C_CCTRL_MBSSID) | + (mask->navusehdr ? FWCMD_H2C_CCTRL_NAVUSEHDR : 0) | + SET_WORD(mask->txpwr_mode, FWCMD_H2C_CCTRL_TXPWR_MODE) | + (mask->data_dcm ? FWCMD_H2C_CCTRL_DATA_DCM : 0) | + (mask->data_er ? FWCMD_H2C_CCTRL_DATA_ER : 0) | + (mask->data_ldpc ? FWCMD_H2C_CCTRL_DATA_LDPC : 0) | + (mask->data_stbc ? FWCMD_H2C_CCTRL_DATA_STBC : 0) | + (mask->a_ctrl_bqr ? FWCMD_H2C_CCTRL_A_CTRL_BQR : 0) | + (mask->a_ctrl_uph ? FWCMD_H2C_CCTRL_A_CTRL_UPH : 0) | + (mask->a_ctrl_bsr ? FWCMD_H2C_CCTRL_A_CTRL_BSR : 0) | + (mask->a_ctrl_cas ? FWCMD_H2C_CCTRL_A_CTRL_CAS : 0) | + (mask->data_bw_er ? FWCMD_H2C_CCTRL_DATA_BW_ER : 0) | + (mask->lsig_txop_en ? FWCMD_H2C_CCTRL_LSIG_TXOP_EN : 0) | + (mask->ctrl_cnt_vld ? FWCMD_H2C_CCTRL_CTRL_CNT_VLD : 0) | + SET_WORD(mask->ctrl_cnt, FWCMD_H2C_CCTRL_CTRL_CNT)); + + tbl->dword14 = + cpu_to_le32(SET_WORD(mask->resp_ref_rate, FWCMD_H2C_CCTRL_RESP_REF_RATE) | + (mask->all_ack_support ? FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT : 0) | + (mask->bsr_queue_size_format ? + FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT : 0) | + SET_WORD(mask->ntx_path_en, FWCMD_H2C_CCTRL_NTX_PATH_EN) | + SET_WORD(mask->path_map_a, FWCMD_H2C_CCTRL_PATH_MAP_A) | + SET_WORD(mask->path_map_b, FWCMD_H2C_CCTRL_PATH_MAP_B) | + SET_WORD(mask->path_map_c, FWCMD_H2C_CCTRL_PATH_MAP_C) | + SET_WORD(mask->path_map_d, FWCMD_H2C_CCTRL_PATH_MAP_D) | + (mask->antsel_a ? FWCMD_H2C_CCTRL_ANTSEL_A : 0) | + (mask->antsel_b ? FWCMD_H2C_CCTRL_ANTSEL_B : 0) | + (mask->antsel_c ? FWCMD_H2C_CCTRL_ANTSEL_C : 0) | + (mask->antsel_d ? FWCMD_H2C_CCTRL_ANTSEL_D : 0)); + + tbl->dword15 = + cpu_to_le32(SET_WORD(mask->addr_cam_index, FWCMD_H2C_CCTRL_ADDR_CAM_INDEX) | + SET_WORD(mask->paid, FWCMD_H2C_CCTRL_PAID) | + (mask->uldl ? FWCMD_H2C_CCTRL_ULDL : 0) | + SET_WORD(mask->doppler_ctrl, FWCMD_H2C_CCTRL_DOPPLER_CTRL) | + SET_WORD(mask->nominal_pkt_padding, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING) | + SET_WORD(mask->nominal_pkt_padding40, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40) | + SET_WORD(mask->nominal_pkt_padding80, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80) | + SET_WORD(mask->txpwr_tolerence, + FWCMD_H2C_CCTRL_TXPWR_TOLERENCE)); + + tbl->dword16 = + cpu_to_le32(SET_WORD(mask->nc, FWCMD_H2C_CCTRL_NC) | + SET_WORD(mask->nr, FWCMD_H2C_CCTRL_NR) | + SET_WORD(mask->ng, FWCMD_H2C_CCTRL_NG) | + SET_WORD(mask->cb, FWCMD_H2C_CCTRL_CB) | + SET_WORD(mask->cs, FWCMD_H2C_CCTRL_CS) | + (mask->csi_txbf_en ? FWCMD_H2C_CCTRL_CSI_TXBF_EN : 0) | + (mask->csi_stbc_en ? FWCMD_H2C_CCTRL_CSI_STBC_EN : 0) | + (mask->csi_ldpc_en ? FWCMD_H2C_CCTRL_CSI_LDPC_EN : 0) | + (mask->csi_para_en ? FWCMD_H2C_CCTRL_CSI_PARA_EN : 0) | + SET_WORD(mask->csi_fix_rate, FWCMD_H2C_CCTRL_CSI_FIX_RATE) | + SET_WORD(mask->csi_gi_ltf, FWCMD_H2C_CCTRL_CSI_GI_LTF) | + SET_WORD(mask->nominal_pkt_padding160, + FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160) | + SET_WORD(mask->csi_bw, FWCMD_H2C_CCTRL_CSI_BW)); + + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_CCTLINFO_UD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + } else { +#if MAC_AX_FEATURE_DBGPKG + if (operation) + cctl_info_debug_write(adapter, macid, + (struct fwcmd_cctlinfo_ud *)buf); +#else + return MACFWNONRDY; +#endif + } + + h2cb_free(adapter, h2cb); + + mac_upd_role_cctrl(adapter, info, mask, macid); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_set_fixmode_mib(struct mac_ax_adapter *adapter, + struct mac_ax_fixmode_para *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_fixmode_para_tblud *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_fixmode_para_tblud)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_fixmode_para_tblud)); + + tbl = (struct fwcmd_fixmode_para_tblud *)buf; + tbl->dword0 = + cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) | + SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) | + SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) | + SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) | + (info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) | + SET_WORD(CLASS_F2P_FIXMODE_PARA, + FWCMD_H2C_TBLUD_TABLE_CLASS)); + + tbl->dword1 = + cpu_to_le32((info->force_sumuru_en ? + FWCMD_H2C_FIXMODE_PARA_FORCE_SUMURU_EN : 0) | + (info->forcesu ? + FWCMD_H2C_FIXMODE_PARA_FORCESU : 0) | + (info->forcemu ? + FWCMD_H2C_FIXMODE_PARA_FORCEMU : 0) | + (info->forceru ? + FWCMD_H2C_FIXMODE_PARA_FORCERU : 0) | + (info->fix_fe_su_en ? + FWCMD_H2C_FIXMODE_PARA_FIX_FE_SU_EN : 0) | + (info->fix_fe_vhtmu_en ? + FWCMD_H2C_FIXMODE_PARA_FIX_FE_VHTMU_EN : 0) | + (info->fix_fe_hemu_en ? + FWCMD_H2C_FIXMODE_PARA_FIX_FE_HEMU_EN : 0) | + (info->fix_fe_heru_en ? + FWCMD_H2C_FIXMODE_PARA_FIX_FE_HERU_EN : 0) | + (info->fix_fe_ul_en ? + FWCMD_H2C_FIXMODE_PARA_FIX_FE_UL_EN : 0) | + (info->fix_frame_seq_su ? + FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_SU : 0) | + (info->fix_frame_seq_vhtmu ? + FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_VHTMU : 0) | + (info->fix_frame_seq_hemu ? + FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HEMU : 0) | + (info->fix_frame_seq_heru ? + FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HERU : 0) | + (info->fix_frame_seq_ul ? + FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_UL : 0) | + (info->is_dlruhwgrp ? + FWCMD_H2C_FIXMODE_PARA_IS_DLRUHWGRP : 0) | + (info->is_ulruhwgrp ? + FWCMD_H2C_FIXMODE_PARA_IS_ULRUHWGRP : 0) | + SET_WORD(info->prot_type_su, + FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU) | + SET_WORD(info->prot_type_vhtmu, + FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU) | + SET_WORD(info->resp_type_vhtmu, + FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU) | + SET_WORD(info->prot_type_hemu, + FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->resp_type_hemu, + FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU) | + SET_WORD(info->prot_type_heru, + FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU) | + SET_WORD(info->resp_type_heru, + FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU) | + SET_WORD(info->ul_prot_type, + FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE) | + SET_WORD(info->rugrpid, + FWCMD_H2C_FIXMODE_PARA_RUGRPID) | + SET_WORD(info->mugrpid, + FWCMD_H2C_FIXMODE_PARA_MUGRPID) | + SET_WORD(info->ulgrpid, + FWCMD_H2C_FIXMODE_PARA_ULGRPID)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_TBLUD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 rst_bacam(struct mac_ax_adapter *adapter, struct rst_bacam_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, cnt; + + val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL); + switch (info->type) { + case BACAM_RST_ALL: + val32 = SET_CLR_WORD(val32, S_AX_BACAM_RST_ALL, B_AX_BACAM_RST); + break; + case BACAM_RST_ENT: + val32 = SET_CLR_WORD(val32, info->ent, B_AX_SRC_ENTRY_IDX); + MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32); + + val32 = SET_CLR_WORD(val32, S_AX_BACAM_RST_ENT, B_AX_BACAM_RST); + break; + } + MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32); + + cnt = BACAM_RST_DLY_CNT; + while (cnt) { + val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL); + if (GET_FIELD(val32, B_AX_BACAM_RST) == S_AX_BACAM_RST_DONE) + break; + PLTFM_DELAY_US(BACAM_RST_DLY_US); + cnt--; + } + + if (!cnt) { + PLTFM_MSG_ERR("[ERR]bacam rst timeout %X\n", val32); + return MACPOLLTO; + } + + return MACSUCCESS; +} + +u32 mac_bacam_info(struct mac_ax_adapter *adapter, + struct mac_ax_bacam_info *info) +{ + u32 ret = MACSUCCESS; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_ba_cam *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) { + PLTFM_MSG_ERR("[ERR]h2cb_alloc\n"); + return MACNPTR; + } + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ba_cam)); + if (!buf) { + ret = MACNOBUF; + PLTFM_MSG_ERR("[ERR]h2cb_put %d\n", ret); + goto fail; + } + + tbl = (struct fwcmd_ba_cam *)buf; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + tbl->dword0 = + cpu_to_le32((info->valid ? FWCMD_H2C_BA_CAM_VALID : 0) | + (info->init_req ? FWCMD_H2C_BA_CAM_INIT_REQ : 0) | + SET_WORD(info->entry_idx, FWCMD_H2C_BA_CAM_ENTRY_IDX) | + SET_WORD(info->tid, FWCMD_H2C_BA_CAM_TID) | + SET_WORD(info->macid, FWCMD_H2C_BA_CAM_MACID) | + SET_WORD(info->bmap_size, FWCMD_H2C_BA_CAM_BMAP_SIZE) | + SET_WORD(info->ssn, FWCMD_H2C_BA_CAM_SSN) + ); + } else { + //8852C + if (info->entry_idx) { + PLTFM_MSG_ERR("[ERR]entry_idx is replaced by entry_idx_v1 in 52C\n"); + return MACNOITEM; + } + tbl->dword0 = + cpu_to_le32((info->valid ? FWCMD_H2C_BA_CAM_VALID : 0) | + (info->init_req ? FWCMD_H2C_BA_CAM_INIT_REQ : 0) | + SET_WORD(info->tid, FWCMD_H2C_BA_CAM_TID) | + SET_WORD(info->macid, FWCMD_H2C_BA_CAM_MACID) | + SET_WORD(info->bmap_size, FWCMD_H2C_BA_CAM_BMAP_SIZE) | + SET_WORD(info->ssn, FWCMD_H2C_BA_CAM_SSN) + ); + tbl->dword1 = + cpu_to_le32(SET_WORD(info->uid_value, FWCMD_H2C_BA_CAM_UID_VALUE) | + (info->std_entry_en ? FWCMD_H2C_BA_CAM_STD_ENTRY_EN : 0) | + (info->band_sel ? FWCMD_H2C_BA_CAM_BAND_SEL : 0) | + SET_WORD(info->entry_idx_v1, FWCMD_H2C_BA_CAM_ENTRY_IDX_V1) + ); + } + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_BA_CAM, + FWCMD_H2C_FUNC_BA_CAM, + 0, + 1); + + if (ret) { + PLTFM_MSG_ERR("[ERR]h2c_pkt_set_hdr %d\n", ret); + goto fail; + } + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) { + PLTFM_MSG_ERR("[ERR]h2c_pkt_build_txd %d\n", ret); + goto fail; + } + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) { + PLTFM_MSG_ERR("[ERR]PLTFM_TX %d\n", ret); + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_ss_dl_grp_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_dl_grp_upd *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_dl_grp_upd *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_dl_grp_upd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_dl_grp_upd *)buf; + tbl->dword0 = + cpu_to_le32((info->grp_valid ? FWCMD_H2C_DL_GRP_UPD_GRP_VALID : 0) | + SET_WORD(info->grp_id, FWCMD_H2C_DL_GRP_UPD_GRP_ID) | + (info->is_hwgrp ? FWCMD_H2C_DL_GRP_UPD_IS_HWGRP : 0) | + SET_WORD(info->macid_u0, FWCMD_H2C_DL_GRP_UPD_MACID_U0) | + SET_WORD(info->macid_u1, FWCMD_H2C_DL_GRP_UPD_MACID_U1) | + SET_WORD(info->macid_u2, FWCMD_H2C_DL_GRP_UPD_MACID_U2)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->macid_u3, FWCMD_H2C_DL_GRP_UPD_MACID_U3) | + SET_WORD(info->macid_u4, FWCMD_H2C_DL_GRP_UPD_MACID_U4) | + SET_WORD(info->macid_u5, FWCMD_H2C_DL_GRP_UPD_MACID_U5) | + SET_WORD(info->macid_u6, FWCMD_H2C_DL_GRP_UPD_MACID_U6)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->macid_u7, FWCMD_H2C_DL_GRP_UPD_MACID_U7) | + SET_WORD(info->ac_bitmap_u0, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0) | + SET_WORD(info->ac_bitmap_u1, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1) | + SET_WORD(info->ac_bitmap_u2, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2) | + SET_WORD(info->ac_bitmap_u3, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3) | + SET_WORD(info->ac_bitmap_u4, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4) | + SET_WORD(info->ac_bitmap_u5, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5)); + + tbl->dword3 = + cpu_to_le32(SET_WORD(info->ac_bitmap_u6, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6) | + SET_WORD(info->ac_bitmap_u7, + FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7) | + SET_WORD(info->next_protecttype, + FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE) | + SET_WORD(info->next_rsptype, + FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_DL_GRP_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_ss_ul_grp_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_grp_upd *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_ul_grp_upd *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ul_grp_upd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_ul_grp_upd *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(info->macid_u0, FWCMD_H2C_UL_GRP_UPD_MACID_U0) | + SET_WORD(info->macid_u1, FWCMD_H2C_UL_GRP_UPD_MACID_U1) | + SET_WORD(info->grp_bitmap, + FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_UL_GRP_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_ss_ul_sta_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_sta_upd *info) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct fwcmd_ss_ulsta_upd *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ss_ulsta_upd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_ss_ulsta_upd *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(info->mode, FWCMD_H2C_SS_ULSTA_UPD_MODE)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->macid[0], FWCMD_H2C_SS_ULSTA_UPD_MACID_U0) | + SET_WORD(info->macid[1], FWCMD_H2C_SS_ULSTA_UPD_MACID_U1) | + SET_WORD(info->macid[2], FWCMD_H2C_SS_ULSTA_UPD_MACID_U2) | + SET_WORD(info->macid[3], FWCMD_H2C_SS_ULSTA_UPD_MACID_U3)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->bsr_len[0], + FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0) | + SET_WORD(info->bsr_len[1], + FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_SS_ULSTA_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_mu_sta_upd(struct mac_ax_adapter *adapter, + struct mac_ax_mu_sta_upd *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_mu_sta_upd *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_mu_sta_upd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_mu_sta_upd *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_MU_STA_UPD_MACID) | + SET_WORD(info->mu_idx, FWCMD_H2C_MU_STA_UPD_MU_IDX) | + SET_WORD(info->prot_rsp_type[0].u.byte_type, + FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0) | + SET_WORD(info->prot_rsp_type[1].u.byte_type, + FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->prot_rsp_type[2].u.byte_type, + FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2) | + SET_WORD(info->prot_rsp_type[3].u.byte_type, + FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3) | + SET_WORD(info->prot_rsp_type[4].u.byte_type, + FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4) | + SET_WORD(info->mugrp_bitmap, + FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP) | + (info->dis_256q ? + FWCMD_H2C_MU_STA_UPD_DIS_256Q : 0) | + (info->dis_1024q ? + FWCMD_H2C_MU_STA_UPD_DIS_1024Q : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_MEDIA_RPT, + FWCMD_H2C_FUNC_MU_STA_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_wlaninfo_get(struct mac_ax_adapter *adapter, + struct mac_ax_wlaninfo_get *info) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_wlaninfo_get *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_wlaninfo_get)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct fwcmd_wlaninfo_get *)buf; + tbl->dword0 = + cpu_to_le32(SET_WORD(info->info_sel, FWCMD_H2C_WLANINFO_GET_INFO_SEL) | + SET_WORD(info->argv0, FWCMD_H2C_WLANINFO_GET_ARGV0) | + SET_WORD(info->argv1, + FWCMD_H2C_WLANINFO_GET_ARGV1) | + SET_WORD(info->argv2, + FWCMD_H2C_WLANINFO_GET_ARGV2)); + + tbl->dword1 = + cpu_to_le32(SET_WORD(info->argv3, + FWCMD_H2C_WLANINFO_GET_ARGV3) | + SET_WORD(info->argv4, + FWCMD_H2C_WLANINFO_GET_ARGV4) | + SET_WORD(info->argv5, + FWCMD_H2C_WLANINFO_GET_ARGV5) | + SET_WORD(info->argv6, + FWCMD_H2C_WLANINFO_GET_ARGV6)); + + tbl->dword2 = + cpu_to_le32(SET_WORD(info->argv7, + FWCMD_H2C_WLANINFO_GET_ARGV7)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_WLANINFO_GET, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_dumpwlanc(struct mac_ax_adapter *adapter, struct mac_ax_dumpwlanc *para) +{ + struct mac_ax_wlaninfo_get info; + u32 ret = 0; + + info.info_sel = DUMPWLANC; + info.argv0 = para->cmdid; + info.argv1 = 0; + info.argv2 = 0; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + ret = mac_wlaninfo_get(adapter, &info); + + return ret; +} + +u32 mac_dumpwlans(struct mac_ax_adapter *adapter, struct mac_ax_dumpwlans *para) +{ + struct mac_ax_wlaninfo_get info; + u32 ret = 0; + + info.info_sel = DUMPWLANS; + info.argv0 = para->cmdid; + info.argv1 = para->macid_grp; + info.argv2 = 0; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + ret = mac_wlaninfo_get(adapter, &info); + + return ret; +} + +u32 mac_dumpwland(struct mac_ax_adapter *adapter, struct mac_ax_dumpwland *para) +{ + u32 ret = 0; + struct mac_ax_wlaninfo_get info; + + info.argv0 = 0; + info.argv1 = 0; + info.argv2 = 0; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + + info.info_sel = DUMPWLAND; + info.argv0 = para->cmdid; + if (para->cmdid == DLDECISION_SU_FORCEMU_FAIL) { + info.argv1 = para->macid[0]; + info.argv2 = para->macid[1]; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_SU_FORCERU_FAIL) { + info.argv1 = para->grp_type; + info.argv2 = para->grp_id; + info.argv3 = para->macid[0]; + info.argv4 = para->macid[1]; + info.argv5 = para->macid[2]; + info.argv6 = para->macid[3]; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT) { + info.argv1 = para->macid[0]; + info.argv2 = para->macid[1]; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT) { + info.argv1 = para->grp_type; + info.argv2 = para->grp_id; + info.argv3 = para->macid[0]; + info.argv4 = para->macid[1]; + info.argv5 = para->macid[2]; + info.argv6 = para->macid[3]; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_MU_TPCOMPARE_RST) { + info.argv1 = para->macid[0]; + info.argv2 = para->macid[1]; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_RU_TPCOMPARE_RST) { + info.argv1 = para->grp_type; + info.argv2 = para->grp_id; + info.argv3 = para->macid[0]; + info.argv4 = para->macid[1]; + info.argv5 = para->macid[2]; + info.argv6 = para->macid[3]; + info.argv7 = 0; + } else if (para->cmdid == DLDECISION_SU_TPCOMPARE_RST) { + if (para->muru == 0) { + info.argv1 = para->macid[0]; + info.argv2 = para->macid[1]; + info.argv3 = 0; + info.argv4 = 0; + info.argv5 = 0; + info.argv6 = 0; + info.argv7 = 0; + } else { + info.argv1 = para->grp_type; + info.argv2 = para->grp_id; + info.argv3 = para->macid[0]; + info.argv4 = para->macid[1]; + info.argv5 = para->macid[2]; + info.argv6 = para->macid[3]; + info.argv7 = 0; + } + } + ret = mac_wlaninfo_get(adapter, &info); + + return ret; +} + +#if MAC_AX_FEATURE_DBGPKG +u32 cctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid, + struct fwcmd_cctlinfo_ud *tbl) +{ + u32 val; + u32 *data = &tbl->dword1, *msk = &tbl->dword9; + u8 i; + + for (i = 0; i < (CCTL_INFO_SIZE >> 2); i++) { + val = mac_sram_dbg_read(adapter, macid * CCTL_INFO_SIZE + i * 4, + CMAC_TBL_SEL); + val = (val & ~(*(msk + i))) | ((*(data + i)) & (*(msk + i))); + mac_sram_dbg_write(adapter, macid * CCTL_INFO_SIZE + i * 4, val, + CMAC_TBL_SEL); + } + + return MACSUCCESS; +} + +u32 dctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid, + struct fwcmd_dctlinfo_ud *tbl) +{ + mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE, tbl->dword1, + DMAC_TBL_SEL); + mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 4, tbl->dword2, + DMAC_TBL_SEL); + mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 8, tbl->dword3, + DMAC_TBL_SEL); + mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 12, tbl->dword4, + DMAC_TBL_SEL); + + return MACSUCCESS; +} +#endif +u32 mac_fw_status_cmd(struct mac_ax_adapter *adapter, + struct mac_ax_fwstatus_payload *info) +{ + u32 ret = 0; + u32 i; + u8 *buf; + u32 *src, *dest; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_fwstatus_payload *tbl; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_fwstatus_payload)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + tbl = (struct mac_ax_fwstatus_payload *)buf; + src = (u32 *)info; + dest = (u32 *)tbl; + for (i = 0; i < (sizeof(struct mac_ax_fwstatus_payload) / 4); i++) + *(dest++) = cpu_to_le32(*(src++)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_TEST, + FWCMD_H2C_CL_FW_STATUS_TEST, + 0, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_fwc2h_ofdma_sts_parse(struct mac_ax_adapter *adapter, + struct mac_ax_fwc2h_sts *fw_c2h_sts, + u32 *content) +{ + u32 val; + u8 i; + + if (!fw_c2h_sts || !content) { + PLTFM_MSG_ERR("[ERR]fwc2h_sts is null\n"); + return MACNPTR; + } + + val = le32_to_cpu(*(content++)); + fw_c2h_sts->tfsts.user_num = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM); + fw_c2h_sts->tfsts.ru_su_per = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER); + + for (i = 0; i < fw_c2h_sts->tfsts.user_num; i++) { + val = le32_to_cpu(*(content++)); + fw_c2h_sts->tfsts.tf_user_sts[i].macid = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_MACID); + fw_c2h_sts->tfsts.tf_user_sts[i].tb_rate = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE); + fw_c2h_sts->tfsts.tf_user_sts[i].tb_fail_per = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER); + fw_c2h_sts->tfsts.tf_user_sts[i].avg_tb_rssi = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI); + val = le32_to_cpu(*(content++)); + fw_c2h_sts->tfsts.tf_user_sts[i].cca_miss_per = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER); + fw_c2h_sts->tfsts.tf_user_sts[i].avg_uph = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH); + fw_c2h_sts->tfsts.tf_user_sts[i].minflag_per = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER); + fw_c2h_sts->tfsts.tf_user_sts[i].avg_tb_evm = + GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM); + } + + return MACSUCCESS; +} + +u32 mac_fw_ofdma_sts_en(struct mac_ax_adapter *adapter, + struct mac_ax_fwsts_para *fwsts_para) +{ + u32 ret = 0; + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u32 *para; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(u32)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + para = (u32 *)buf; + (*para) = cpu_to_le32((fwsts_para->en ? FWCMD_H2C_FW_STS_PARA_EN : 0) | + SET_WORD(fwsts_para->intvl_ms, + FWCMD_H2C_FW_STS_PARA_INTVL_MS)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FR_EXCHG, + FWCMD_H2C_FUNC_FW_STS_PARA, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) + goto fail; + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + diff --git a/phl/hal_g6/mac/mac_ax/tblupd.h b/phl/hal_g6/mac/mac_ax/tblupd.h new file mode 100644 index 0000000..9cf05d1 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/tblupd.h @@ -0,0 +1,629 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _TABLEUPD_H2C_H_ +#define _TABLEUPD_H2C_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "trx_desc.h" +#include "addr_cam.h" + +/*--------------------Define MACRO--------------------------------------*/ +#define DLRU_CLASS_GRP_TBL 0 +#define ULRU_CLASS_GRP_TBL 1 +#define CLASS_RUSTA_INFO 2 +#define DLRU_CLASS_FIXED_TBL 3 +#define ULRU_CLASS_FIXED_TBL 4 +#define CLASS_BA_INFOTBL 5 +#define CLASS_MUDECISION_PARA 6 +#define CLASS_UL_FIXINFO 7 +#define CLASS_F2P_FIXMODE_PARA 8 + +#define BACAM_RST_DLY_CNT 1000 +#define BACAM_RST_DLY_US 1 +/*--------------------Define Enum---------------------------------------*/ + +/** + * @enum H2C_WLANINFO_SEL + * + * @brief H2C_WLANINFO_SEL + * + * @var H2C_WLANINFO_SEL::DUMPWLANC + * Please Place Description here. + * @var H2C_WLANINFO_SEL::DUMPWLANS + * Please Place Description here. + * @var H2C_WLANINFO_SEL::DUMPWLAND + * Please Place Description here. + */ +enum H2C_WLANINFO_SEL { + DUMPWLANC = BIT0, + DUMPWLANS = BIT1, + DUMPWLAND = BIT2 +}; + +/** + * @enum DLDECISION_RESULT_TYPE + * + * @brief DLDECISION_RESULT_TYPE + * + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCESU + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_MU_FORCEMU + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCEMU_FAIL + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCERU_FAIL + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCERU_RUARST_RU2SU + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_RU_FORCERU_RUSRST_FIXTBL + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_RU_FORCERU + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_WDINFO_USERATE + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_PRINULLWD + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_MU_BYPASS_MUTPCOMPARE + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_RUARST_RU2SU + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_RU_RUARST_FIXTBL + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_MU_TPCOMPARE_RST + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_RU_TPCOMPARE_RST + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_SU_TPCOMPARE_RST + * Please Place Description here. + * @var DLDECISION_RESULT_TYPE::DLDECISION_MAX + * Please Place Description here. + */ +enum DLDECISION_RESULT_TYPE { + DLDECISION_SU_FORCESU = 0, + DLDECISION_MU_FORCEMU = 1, + DLDECISION_SU_FORCEMU_FAIL = 2, + DLDECISION_SU_FORCERU_FAIL = 3, + DLDECISION_SU_FORCERU_RUARST_RU2SU = 4, + DLDECISION_RU_FORCERU_RUSRST_FIXTBL = 5, + DLDECISION_RU_FORCERU = 6, + DLDECISION_SU_WDINFO_USERATE = 7, + DLDECISION_SU_PRINULLWD = 8, + DLDECISION_MU_BYPASS_MUTPCOMPARE = 9, + DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT = 10, + DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT = 11, + DLDECISION_SU_RUARST_RU2SU = 12, + DLDECISION_RU_RUARST_FIXTBL = 13, + DLDECISION_MU_TPCOMPARE_RST = 14, + DLDECISION_RU_TPCOMPARE_RST = 15, + DLDECISION_SU_TPCOMPARE_RST = 16, + DLDECISION_MAX = 17 +}; + +enum S_AX_BACAM_RST { + S_AX_BACAM_RST_DONE = 0, + S_AX_BACAM_RST_ENT, + S_AX_BACAM_RST_ALL, + S_AX_BACAM_RST_RSVD +}; + +enum BACAM_RST_TYPE { + BACAM_RST_ALL = 0, + BACAM_RST_ENT, +}; + +/*--------------------Define Struct-------------------------------------*/ + +struct rst_bacam_info { + enum BACAM_RST_TYPE type; + u8 ent; +}; + +/** + * @addtogroup Association + * @{ + * @addtogroup BA_Info + * @{ + */ +/** + * @brief mac_upd_ba_infotbl + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_ba_infotbl(struct mac_ax_adapter *adapter, + struct mac_ax_ba_infotbl *info); +/** + * @} + * @} + */ +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup MU + * @{ + */ + +/** + * @brief mac_upd_mudecision_para + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_mudecision_para(struct mac_ax_adapter *adapter, + struct mac_ax_mudecision_para *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup UL + * @{ + */ + +/** + * @brief mac_upd_ul_fixinfo + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_ul_fixinfo(struct mac_ax_adapter *adapter, + struct mac_ax_ul_fixinfo *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup F2P_TestCmd + * @{ + */ + +/** + * @brief mac_f2p_test_cmd + * + * @param *adapter + * @param *info + * @param *f2pwd + * @param *ptxcmd + * @param *psigb_addr + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_f2p_test_cmd(struct mac_ax_adapter *adapter, + struct mac_ax_f2p_test_para *info, + struct mac_ax_f2p_wd *f2pwd, + struct mac_ax_f2p_tx_cmd *ptxcmd, + u8 *psigb_addr); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup DMAC_Table + * @{ + */ + +/** + * @brief mac_upd_dctl_info + * + * @param *adapter + * @param *info + * @param *mask + * @param macid + * @param operation + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_dctl_info(struct mac_ax_adapter *adapter, + struct mac_ax_dctl_info *info, + struct mac_ax_dctl_info *mask, u8 macid, u8 operation); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ + +/** + * @brief mac_upd_shcut_mhdr + * + * @param *adapter + * @param *info + * @param macid + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_shcut_mhdr(struct mac_ax_adapter *adapter, + struct mac_ax_shcut_mhdr *info, u8 macid); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup CMAC_Table + * @{ + */ + +/** + * @brief mac_upd_cctl_info + * + * @param *adapter + * @param *info + * @param *mask + * @param macid + * @param operation + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_upd_cctl_info(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_info *info, + struct mac_ax_cctl_info *mask, u8 macid, u8 operation); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup FW_CommonInfo + * @{ + */ + +/** + * @brief mac_set_fixmode_mib + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_set_fixmode_mib(struct mac_ax_adapter *adapter, + struct mac_ax_fixmode_para *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup F2P_TestCmd + * @{ + */ + +/** + * @brief mac_snd_test_cmd + * + * @param *adapter + * @param *cmd_buf + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_snd_test_cmd(struct mac_ax_adapter *adapter, + u8 *cmd_buf); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup BA_Info + * @{ + */ + +/** + * @brief rst_bacam + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 rst_bacam(struct mac_ax_adapter *adapter, struct rst_bacam_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Association + * @{ + * @addtogroup BA_Info + * @{ + */ + +/** + * @brief mac_bacam_info + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_bacam_info(struct mac_ax_adapter *adapter, + struct mac_ax_bacam_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup SU + * @{ + */ + +/** + * @brief mac_ss_dl_grp_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ss_dl_grp_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_dl_grp_upd *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup UL + * @{ + */ + +/** + * @brief mac_ss_ul_grp_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ss_ul_grp_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_grp_upd *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup UL + * @{ + */ + +/** + * @brief mac_ss_ul_sta_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_ss_ul_sta_upd(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_sta_upd *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup MU + * @{ + */ + +/** + * @brief mac_mu_sta_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_mu_sta_upd(struct mac_ax_adapter *adapter, + struct mac_ax_mu_sta_upd *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup FW_CommonInfo + * @{ + */ + +/** + * @brief mac_wlaninfo_get + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_wlaninfo_get(struct mac_ax_adapter *adapter, + struct mac_ax_wlaninfo_get *info); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup FW_CommonInfo + * @{ + */ + +/** + * @brief mac_dumpwlanc + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dumpwlanc(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwlanc *para); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup FW_CommonInfo + * @{ + */ + +/** + * @brief mac_dumpwlans + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dumpwlans(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwlans *para); +/** + * @} + * @} + */ + +/** + * @addtogroup FrameExchange + * @{ + * @addtogroup FW_CommonInfo + * @{ + */ + +/** + * @brief mac_dumpwland + * + * @param *adapter + * @param *para + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_dumpwland(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwland *para); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup CMAC_Table + * @{ + */ + +/** + * @brief cctl_info_debug_write + * + * @param *adapter + * @param macid + * @param *tbl + * @return Please Place Description here. + * @retval u32 + */ + +#if MAC_AX_FEATURE_DBGPKG +u32 cctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid, + struct fwcmd_cctlinfo_ud *tbl); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup DMAC_Table + * @{ + */ + +/** + * @brief dctl_info_debug_write + * + * @param *adapter + * @param macid + * @param *tbl + * @return Please Place Description here. + * @retval u32 + */ +u32 dctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid, + struct fwcmd_dctlinfo_ud *tbl); +/** + * @} + * @} + */ + +#endif +u32 mac_fw_status_cmd(struct mac_ax_adapter *adapter, + struct mac_ax_fwstatus_payload *info); + +u32 mac_fwc2h_ofdma_sts_parse(struct mac_ax_adapter *adapter, + struct mac_ax_fwc2h_sts *fw_c2h_sts, + u32 *content); + +u32 mac_fw_ofdma_sts_en(struct mac_ax_adapter *adapter, + struct mac_ax_fwsts_para *fwsts_para); + +#endif diff --git a/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.c b/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.c new file mode 100644 index 0000000..267d758 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.c @@ -0,0 +1,124 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "tcpip_checksum_offload.h" +#if MAC_AX_FW_REG_OFLD +u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter, + u8 en_tx_chksum_ofd, u8 en_rx_chksum_ofd) +{ + u32 ret = 0; + u8 *buf; +#if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; +#else + struct h2c_buf *h2cb; +#endif + struct mac_ax_en_tcpipchksum *content; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_tcpipchksum)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + content = (struct mac_ax_en_tcpipchksum *)buf; + content->en_tx_chksum_ofd = en_tx_chksum_ofd; + content->en_rx_chksum_ofd = en_rx_chksum_ofd; + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_FW_OFLD, + FWCMD_H2C_FUNC_TCPIP_CHKSUM_OFFLOAD_REG, + 0, + 1); + + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif +fail: + h2cb_free(adapter, h2cb); + + return ret; +} +#else +u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter, + u8 en_tx_chksum_ofd, u8 en_rx_chksum_ofd) +{ + u32 val; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (en_tx_chksum_ofd) { + val = MAC_REG_R32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION); + val |= B_AX_HDT_TCPIP_CHKSUM_EN; + MAC_REG_W32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION, val); + } else { + val = MAC_REG_R32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION); + val &= (~B_AX_HDT_TCPIP_CHKSUM_EN); + MAC_REG_W32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION, val); + } + + if (en_rx_chksum_ofd) { + val = MAC_REG_R32(R_AX_RX_TCPIP_CHECKSUM_FUNCTION); + val |= B_AX_HDR_TCPIP_CHKSUM_EN; + MAC_REG_W32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION), val); + } else { + val = MAC_REG_R32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION)); + val &= (~B_AX_HDR_TCPIP_CHKSUM_EN); + MAC_REG_W32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION), val); + } + + return MACSUCCESS; +} +#endif +u32 mac_chk_rx_tcpip_chksum_ofd(struct mac_ax_adapter *adapter, + u8 chksum_status) +{ + u8 chk_val = (chksum_status & 0xF0); + + if (!(chk_val & MAC_AX_CHKOFD_TCP_CHKSUM_VLD)) + return MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT; + + if (chk_val & MAC_AX_CHKOFD_TCP_CHKSUM_ERR) + return MAC_AX_CHKSUM_OFD_CHKSUM_ERR; + + if (!(chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) && + !(chk_val & MAC_AX_CHKOFD_RX_IPV)) + return MAC_AX_CHKSUM_OFD_IPV4_TCP_OK; + + if (!(chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) && + (chk_val & MAC_AX_CHKOFD_RX_IPV)) + return MAC_AX_CHKSUM_OFD_IPV6_TCP_OK; + + if ((chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) && + !(chk_val & MAC_AX_CHKOFD_RX_IPV)) + return MAC_AX_CHKSUM_OFD_IPV4_UDP_OK; + + return MAC_AX_CHKSUM_OFD_IPV6_UDP_OK; +} + diff --git a/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.h b/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.h new file mode 100644 index 0000000..5ee6f04 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.h @@ -0,0 +1,94 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TCPIP_CHECKSUM_OFFLOAD_H_ +#define _MAC_AX_TCPIP_CHECKSUM_OFFLOAD_H_ + +#include "../type.h" +#include "../mac_ax.h" + +/** + * @struct mac_ax_en_tcpipchksum + * @brief mac_ax_en_tcpipchksum + * + * @var mac_ax_en_tcpipchksum::en_tx_chksum_ofd + * Please Place Description here. + * @var mac_ax_en_tcpipchksum::en_rx_chksum_ofd + * Please Place Description here. + * @var mac_ax_en_tcpipchksum::rsvd0 + * Please Place Description here. + */ +struct mac_ax_en_tcpipchksum { + /* dword0 */ + u32 en_tx_chksum_ofd: 1; + u32 en_rx_chksum_ofd: 1; + u32 rsvd0: 30; +}; + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ +/** + * @brief mac_tcpip_chksum_ofd + * + * @param *adapter + * @param en_tx_chksum_ofd + * @param en_rx_chksum_ofd + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter, + u8 en_tx_chksum_ofd, + u8 en_rx_chksum_ofd); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_ShortCut + * @{ + */ + +/** + * @brief mac_chk_rx_tcpip_chksum_ofd + * + * @param *adapter + * @param chksum_status + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_chk_rx_tcpip_chksum_ofd(struct mac_ax_adapter *adapter, + u8 chksum_status); +/** + * @} + * @} + */ + +#define MAC_AX_CHKSUM_OFD_TX 0x1 +#define MAC_AX_CHKSUM_OFD_RX 0x2 + +#define MAC_AX_CHKOFD_TCP_CHKSUM_ERR BIT(4) +#define MAC_AX_CHKOFD_RX_IS_TCP_UDP BIT(6) +#define MAC_AX_CHKOFD_RX_IPV BIT(5) +#define MAC_AX_CHKOFD_TCP_CHKSUM_VLD BIT(7) + +#endif diff --git a/phl/hal_g6/mac/mac_ax/trx_desc.c b/phl/hal_g6/mac/mac_ax/trx_desc.c new file mode 100644 index 0000000..fd3138b --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/trx_desc.c @@ -0,0 +1,632 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "trx_desc.h" + +#define RXD_RPKT_TYPE_INVALID 0xFF +#define TXD_AC_TYPE_MSK 0x3 +#define TXD_TID_IND_SH 2 +#define TID_MAX_NUM 8 + +#define TID_0_QSEL 0 +#define TID_1_QSEL 1 +#define TID_2_QSEL 1 +#define TID_3_QSEL 0 +#define TID_4_QSEL 2 +#define TID_5_QSEL 2 +#define TID_6_QSEL 3 +#define TID_7_QSEL 3 +#define TID_0_IND 0 +#define TID_1_IND 0 +#define TID_2_IND 1 +#define TID_3_IND 1 +#define TID_4_IND 0 +#define TID_5_IND 1 +#define TID_6_IND 0 +#define TID_7_IND 1 + +enum wd_info_pkt_type { + WD_INFO_PKT_NORMAL, + + /* keep last */ + WD_INFO_PKT_LAST, + WD_INFO_PKT_MAX = WD_INFO_PKT_LAST, +}; + +static u8 qsel_l[TID_MAX_NUM] = { + TID_0_QSEL, TID_1_QSEL, TID_2_QSEL, TID_3_QSEL, + TID_4_QSEL, TID_5_QSEL, TID_6_QSEL, TID_7_QSEL +}; + +static u8 tid_ind[TID_MAX_NUM] = { + TID_0_IND, TID_1_IND, TID_2_IND, TID_3_IND, + TID_4_IND, TID_5_IND, TID_6_IND, TID_7_IND +}; + +u32 mac_txdesc_len(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info) +{ + u32 len; + enum rtw_packet_type pkt_type = info->type; + + len = WD_BODY_LEN; + + if (pkt_type != RTW_PHL_PKT_TYPE_H2C && + pkt_type != RTW_PHL_PKT_TYPE_FWDL && + info->wdinfo_en != 0) + len += WD_INFO_LEN; + + return len; +} + +static u32 txdes_proc_h2c_fwdl(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len) +{ + struct wd_body_t *wdb; + + if (len != mac_txdesc_len(adapter, info)) { + PLTFM_MSG_ERR("[ERR] illegal len %d\n", len); + return MACBUFSZ; + } + + if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) { + PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen); + return MACFUNCINPUT; + } + + wdb = (struct wd_body_t *)buf; + wdb->dword0 = cpu_to_le32(SET_WORD(MAC_AX_DMA_H2C, AX_TXD_CH_DMA) | + (info->type == RTW_PHL_PKT_TYPE_FWDL ? AX_TXD_FWDL_EN : 0)); + wdb->dword1 = 0; + wdb->dword2 = cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE)); + wdb->dword3 = 0; + wdb->dword4 = 0; + wdb->dword5 = 0; + + return MACSUCCESS; +} + +#if MAC_AX_FEATURE_HV +static u32 txdes_proc_hv(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, + struct wd_body_t *wdb, + struct wd_info_t *wdi) +{ + struct hv_txpkt_info *hv_info = (struct hv_txpkt_info *)info->mac_priv; + + wdb->dword0 |= cpu_to_le32((hv_info->chk_en ? AX_TXD_CHK_EN : 0)); + wdi->dword3 |= cpu_to_le32((hv_info->null_1 ? AX_TXD_NULL_1 : 0) | + (hv_info->null_0 ? AX_TXD_NULL_0 : 0) | + (hv_info->tri_frame ? AX_TXD_TRI_FRAME : 0) | + (hv_info->ht_data_snd ? AX_TXD_HT_DATA_SND : 0)); + wdi->dword5 |= cpu_to_le32(SET_WORD(hv_info->ndpa_dur, AX_TXD_NDPA_DURATION)); + + return MACSUCCESS; +} +#endif + +static u32 txdes_proc_data(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len) +{ + struct wd_body_t *wdb; + struct wd_info_t *wdi; + u8 wd_info_tmpl[WD_INFO_PKT_MAX][24] = {{0}}; + u32 ret; + u8 ch, qsel; + + if (len != mac_txdesc_len(adapter, info)) { + PLTFM_MSG_ERR("[ERR] illegal len %d\n", len); + return MACBUFSZ; + } + + if (info->dma_ch > MAC_AX_DATA_HIQ) { + PLTFM_MSG_ERR("[ERR] txd ch %d illegal\n", info->dma_ch); + return MACTXCHDMA; + } + + if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) { + PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen); + return MACFUNCINPUT; + } + + wdb = (struct wd_body_t *)buf; + if (adapter->hw_info->intf == MAC_AX_INTF_SDIO) { + wdb->dword0 = + cpu_to_le32(AX_TXD_STF_MODE); + } else if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + wdb->dword0 = + cpu_to_le32(AX_TXD_STF_MODE | + (info->usb_pkt_ofst ? + AX_TXD_PKT_OFFSET : 0)); + } else if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + wdb->dword0 = + cpu_to_le32((info->wd_page_size ? AX_TXD_WD_PAGE : 0) | + (adapter->dle_info.qta_mode == + MAC_AX_QTA_SCC_STF || + adapter->dle_info.qta_mode == + MAC_AX_QTA_DBCC_STF ? + AX_TXD_STF_MODE : 0)); + } else { + PLTFM_MSG_ERR("[ERR] unknown intf %d\n", + adapter->hw_info->intf); + return MACINTF; + } + + if (info->dma_ch == MAC_AX_DATA_HIQ && + adapter->hw_info->intf == MAC_AX_INTF_USB) + ch = info->band ? MAC_AX_DMA_B1MG : MAC_AX_DMA_B0MG; + else if (info->dma_ch == MAC_AX_DATA_HIQ) + ch = info->band ? MAC_AX_DMA_B1HI : MAC_AX_DMA_B0HI; + else + ch = info->dma_ch; + + wdb->dword0 |= + cpu_to_le32(SET_WORD(info->hw_seq_mode, + AX_TXD_EN_HWSEQ_MODE) | + SET_WORD(info->hw_ssn_sel, + AX_TXD_HW_SSN_SEL) | + SET_WORD(info->hdr_len, + AX_TXD_HDR_LLC_LEN) | + SET_WORD(ch, AX_TXD_CH_DMA) | + (info->hw_amsdu ? AX_TXD_HWAMSDU : 0) | + (info->smh_en ? AX_TXD_SMH_EN : 0) | + (info->hw_sec_iv ? AX_TXD_HW_AES_IV : 0) | + (info->wdinfo_en ? AX_TXD_WDINFO_EN : 0) | + SET_WORD(info->wp_offset, + AX_TXD_WP_OFFSET)); + wdb->dword1 = + cpu_to_le32(SET_WORD(info->shcut_camid, AX_TXD_SHCUT_CAMID)); + /* Get bb and qsel from qsel by according MAC ID */ + if (info->dma_ch == MAC_AX_DATA_HIQ) + qsel = info->band ? MAC_AX_HI1_SEL : MAC_AX_HI0_SEL; + else + qsel = (info->band << 3) | (info->wmm << 2) | qsel_l[info->tid]; + wdb->dword2 = + cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE) | + SET_WORD(qsel, AX_TXD_QSEL) | + (tid_ind[info->tid] ? AX_TXD_TID_IND : 0) | + SET_WORD(info->macid, AX_TXD_MACID)); + + wdb->dword3 = cpu_to_le32(SET_WORD(info->sw_seq, + AX_TXD_WIFI_SEQ) | + (info->ampdu_en ? AX_TXD_AGG_EN : 0) | + ((info->bk || info->ack_ch_info) ? + AX_TXD_BK : 0)); + wdb->dword4 = 0; + wdb->dword5 = 0; + + wdi = (struct wd_info_t *)wd_info_tmpl[WD_INFO_PKT_NORMAL]; + wdi->dword0 = + cpu_to_le32((info->userate_sel ? AX_TXD_USERATE_SEL : 0) | + SET_WORD(info->f_rate, AX_TXD_DATARATE) | + SET_WORD(info->f_bw, AX_TXD_DATA_BW) | + (info->data_bw_er ? AX_TXD_DATA_BW_ER : 0) | + SET_WORD(info->f_gi_ltf, AX_TXD_GI_LTF) | + (info->f_er ? AX_TXD_DATA_ER : 0) | + (info->f_dcm ? AX_TXD_DATA_DCM : 0) | + (info->f_stbc ? AX_TXD_DATA_STBC : 0) | + (info->f_ldpc ? AX_TXD_DATA_LDPC : 0) | + (info->dis_data_rate_fb ? AX_TXD_DISDATAFB : 0) | + (info->dis_rts_rate_fb ? AX_TXD_DISRTSFB : 0) | + SET_WORD(info->hal_port, + AX_TXD_MULTIPORT_ID) | + SET_WORD(info->mbssid, AX_TXD_MBSSID) | + (info->ack_ch_info ? AX_TXD_ACK_CH_INFO : 0)); + wdi->dword1 = + cpu_to_le32(SET_WORD(info->max_agg_num, AX_TXD_MAX_AGG_NUM) | + SET_WORD(info->data_tx_cnt_lmt, AX_TXD_DATA_TXCNT_LMT) | + (info->data_tx_cnt_lmt_en ? + AX_TXD_DATA_TXCNT_LMT_SEL : 0) | + (info->bc || info->mc ? AX_TXD_BMC : 0) | + (info->nav_use_hdr ? AX_TXD_NAVUSEHDR : 0) | + (info->bc || info->mc ? AX_TXD_BMC : 0) | + (info->a_ctrl_uph ? AX_TXD_A_CTRL_UPH : 0) | + (info->a_ctrl_bsr ? AX_TXD_A_CTRL_BSR : 0) | + (info->a_ctrl_cas ? AX_TXD_A_CTRL_CAS : 0) | + SET_WORD(info->data_rty_lowest_rate, + AX_TXD_DATA_RTY_LOWEST_RATE)); + wdi->dword2 = + cpu_to_le32(SET_WORD(info->life_time_sel, AX_TXD_LIFETIME_SEL) | + SET_WORD(info->sec_type, AX_TXD_SECTYPE) | + (info->sec_hw_enc ? AX_TXD_SEC_HW_ENC : 0) | + SET_WORD(info->sec_cam_idx, AX_TXD_SEC_CAM_IDX) | + SET_WORD(info->ampdu_density, + AX_TXD_AMPDU_DENSITY)); + + wdi->dword3 = + cpu_to_le32((info->sifs_tx ? AX_TXD_SIFS_TX : 0) | + SET_WORD(info->ndpa, AX_TXD_NDPA) | + SET_WORD(info->snd_pkt_sel, AX_TXD_SND_PKT_SEL) | + (info->rtt_en ? AX_TXD_RTT_EN : 0) | + (info->spe_rpt ? AX_TXD_SPE_RPT : 0)); + + wdi->dword4 = + cpu_to_le32((info->rts_en ? AX_TXD_RTS_EN : 0) | + (info->cts2self ? AX_TXD_CTS2SELF : 0) | + SET_WORD(info->rts_cca_mode, AX_TXD_CCA_RTS) | + (info->hw_rts_en ? AX_TXD_HW_RTS_EN : 0) | + SET_WORD(info->sw_define, AX_TXD_SW_DEFINE)); + + wdi->dword5 = 0; + +#if MAC_AX_FEATURE_HV + txdes_proc_hv(adapter, info, wdb, wdi); +#endif + + if (info->wdinfo_en) + PLTFM_MEMCPY(buf + WD_BODY_LEN, (u8 *)wdi, WD_INFO_LEN); + + if (adapter->hw_info->wd_checksum_en) { + ret = mac_wd_checksum(adapter, info, buf); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret); + return ret; + } + } + + return MACSUCCESS; +} + +static u32 txdes_proc_mgnt(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len) +{ + struct wd_body_t *wdb; + struct wd_info_t *wdi; + u8 wd_info_tmpl[WD_INFO_PKT_MAX][24] = {{0}}; + u32 ret; + + if (len != mac_txdesc_len(adapter, info)) { + PLTFM_MSG_ERR("[ERR] illegal len %d\n", len); + return MACBUFSZ; + } + + if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) { + PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen); + return MACFUNCINPUT; + } + + wdb = (struct wd_body_t *)buf; + if (adapter->hw_info->intf == MAC_AX_INTF_SDIO) { + wdb->dword0 = + cpu_to_le32(AX_TXD_STF_MODE); + } else if (adapter->hw_info->intf == MAC_AX_INTF_USB) { + wdb->dword0 = + cpu_to_le32(AX_TXD_STF_MODE | + (info->usb_pkt_ofst ? + AX_TXD_PKT_OFFSET : 0)); + } else if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + wdb->dword0 = + cpu_to_le32((info->wd_page_size ? AX_TXD_WD_PAGE : 0) | + (adapter->dle_info.qta_mode == + MAC_AX_QTA_SCC_STF || + adapter->dle_info.qta_mode == + MAC_AX_QTA_DBCC_STF ? + AX_TXD_STF_MODE : 0)); + } else { + PLTFM_MSG_ERR("[ERR] unknown intf %d\n", + adapter->hw_info->intf); + return MACINTF; + } + + wdb->dword0 |= + cpu_to_le32(SET_WORD(info->hw_seq_mode, + AX_TXD_EN_HWSEQ_MODE) | + SET_WORD(info->hw_ssn_sel, + AX_TXD_HW_SSN_SEL) | + SET_WORD(info->hdr_len, + AX_TXD_HDR_LLC_LEN) | + (info->wdinfo_en ? AX_TXD_WDINFO_EN : 0)); + + wdb->dword0 |= + cpu_to_le32(SET_WORD((info->band ? + MAC_AX_DMA_B1MG : + MAC_AX_DMA_B0MG), + AX_TXD_CH_DMA)); + + wdb->dword1 = 0; + /* Get bb and qsel from qsel by according MAC ID */ + wdb->dword2 = + cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE) | + SET_WORD((info->band ? + MAC_AX_MG1_SEL : MAC_AX_MG0_SEL), + AX_TXD_QSEL) | + SET_WORD(info->macid, AX_TXD_MACID)); + wdb->dword3 = cpu_to_le32(SET_WORD(info->sw_seq, + AX_TXD_WIFI_SEQ) | + (info->bk ? AX_TXD_BK : 0)); + wdb->dword4 = 0; + wdb->dword5 = 0; + + wdi = (struct wd_info_t *)wd_info_tmpl[WD_INFO_PKT_NORMAL]; + wdi->dword0 = + cpu_to_le32((info->userate_sel ? AX_TXD_USERATE_SEL : 0) | + SET_WORD(info->f_rate, AX_TXD_DATARATE) | + SET_WORD(info->f_bw, AX_TXD_DATA_BW) | + (info->data_bw_er ? AX_TXD_DATA_BW_ER : 0) | + SET_WORD(info->f_gi_ltf, AX_TXD_GI_LTF) | + (info->f_er ? AX_TXD_DATA_ER : 0) | + (info->f_dcm ? AX_TXD_DATA_DCM : 0) | + (info->f_stbc ? AX_TXD_DATA_STBC : 0) | + (info->f_ldpc ? AX_TXD_DATA_LDPC : 0) | + (info->dis_data_rate_fb ? AX_TXD_DISDATAFB : 0) | + (info->dis_rts_rate_fb ? AX_TXD_DISRTSFB : 0) | + SET_WORD(info->hal_port, AX_TXD_MULTIPORT_ID) | + SET_WORD(info->mbssid, AX_TXD_MBSSID)); + wdi->dword1 = + cpu_to_le32(SET_WORD(info->max_agg_num, AX_TXD_MAX_AGG_NUM) | + SET_WORD(info->data_tx_cnt_lmt, AX_TXD_DATA_TXCNT_LMT) | + (info->data_tx_cnt_lmt_en ? + AX_TXD_DATA_TXCNT_LMT_SEL : 0) | + (info->bc || info->mc ? AX_TXD_BMC : 0) | + (info->nav_use_hdr ? AX_TXD_NAVUSEHDR : 0)); + wdi->dword2 = + cpu_to_le32(SET_WORD(info->life_time_sel, AX_TXD_LIFETIME_SEL) | + SET_WORD(info->sec_type, AX_TXD_SECTYPE) | + (info->sec_hw_enc ? AX_TXD_SEC_HW_ENC : 0) | + SET_WORD(info->sec_cam_idx, AX_TXD_SEC_CAM_IDX) | + SET_WORD(info->ampdu_density, + AX_TXD_AMPDU_DENSITY)); + + wdi->dword3 = + cpu_to_le32((info->sifs_tx ? AX_TXD_SIFS_TX : 0) | + SET_WORD(info->ndpa, AX_TXD_NDPA) | + SET_WORD(info->snd_pkt_sel, AX_TXD_SND_PKT_SEL) | + (info->rtt_en ? AX_TXD_RTT_EN : 0) | + (info->spe_rpt ? AX_TXD_SPE_RPT : 0)); + + wdi->dword4 = + cpu_to_le32((info->rts_en ? AX_TXD_RTS_EN : 0) | + (info->cts2self ? AX_TXD_CTS2SELF : 0) | + SET_WORD(info->rts_cca_mode, AX_TXD_CCA_RTS) | + (info->hw_rts_en ? AX_TXD_HW_RTS_EN : 0) | + SET_WORD(info->sw_define, AX_TXD_SW_DEFINE)); + + wdi->dword5 = 0; + +#if MAC_AX_FEATURE_HV + txdes_proc_hv(adapter, info, wdb, wdi); +#endif + + if (info->wdinfo_en) + PLTFM_MEMCPY(buf + WD_BODY_LEN, (u8 *)wdi, WD_INFO_LEN); + + if (adapter->hw_info->wd_checksum_en) { + ret = mac_wd_checksum(adapter, info, buf); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret); + return ret; + } + } + + return MACSUCCESS; +} + +static struct txd_proc_type txdes_proc_mac[] = { + {RTW_PHL_PKT_TYPE_H2C, txdes_proc_h2c_fwdl}, + {RTW_PHL_PKT_TYPE_FWDL, txdes_proc_h2c_fwdl}, + {RTW_PHL_PKT_TYPE_DATA, txdes_proc_data}, + {RTW_PHL_PKT_TYPE_MGNT, txdes_proc_mgnt}, + {RTW_PHL_PKT_TYPE_MAX, NULL}, +}; + +u32 mac_build_txdesc(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len) +{ + struct txd_proc_type *proc = txdes_proc_mac; + enum rtw_packet_type pkt_type = info->type; + u32 (*handler)(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len) = NULL; + + for (; proc->type != RTW_PHL_PKT_TYPE_MAX; proc++) { + if (pkt_type == proc->type) { + handler = proc->handler; + break; + } + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null type handler type: %X\n", proc->type); + return MACNOITEM; + } + + return handler(adapter, info, buf, len); +} + +u32 mac_refill_txdesc(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *txpkt_info, + struct mac_ax_refill_info *mask, + struct mac_ax_refill_info *info) +{ + u32 dw0 = ((struct wd_body_t *)info->pkt)->dword0; + u32 dw1 = ((struct wd_body_t *)info->pkt)->dword1; + u32 ret; + + if (mask->packet_offset) + ((struct wd_body_t *)info->pkt)->dword0 = + dw0 | (info->packet_offset ? AX_TXD_PKT_OFFSET : 0); + + if (mask->agg_num == AX_TXD_DMA_TXAGG_NUM_MSK) + ((struct wd_body_t *)info->pkt)->dword1 = + SET_CLR_WORD(dw1, info->agg_num, AX_TXD_DMA_TXAGG_NUM); + + if (adapter->hw_info->wd_checksum_en) { + ret = mac_wd_checksum(adapter, txpkt_info, info->pkt); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret); + return ret; + } + } + + return MACSUCCESS; +} + +static u32 rxdes_parse_comm(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf) +{ + u32 hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0); + + info->rxdlen = hdr_val & AX_RXD_LONG_RXD ? RXD_LONG_LEN : RXD_SHORT_LEN; + info->pktsize = GET_FIELD(hdr_val, AX_RXD_RPKT_LEN); + info->shift = (u8)GET_FIELD(hdr_val, AX_RXD_SHIFT); + info->drvsize = (u8)GET_FIELD(hdr_val, AX_RXD_DRV_INFO_SIZE); + + return MACSUCCESS; +} + +static u32 rxdes_parse_wifi(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + u32 hdr_val; + + info->type = MAC_AX_PKT_DATA; + + hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword3); + info->u.data.crc_err = !!(hdr_val & AX_RXD_CRC32_ERR); + info->u.data.icv_err = !!(hdr_val & AX_RXD_ICV_ERR); + + return MACSUCCESS; +} + +static u32 rxdes_parse_c2h(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + info->type = MAC_AX_PKT_C2H; + + return MACSUCCESS; +} + +static u32 rxdes_parse_ch_info(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + info->type = MAC_AX_PKT_CH_INFO; + + return MACSUCCESS; +} + +static u32 rxdes_parse_dfs(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + info->type = MAC_AX_PKT_DFS; + + return MACSUCCESS; +} + +static u32 rxdes_parse_ppdu(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + u32 hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0); + + info->type = MAC_AX_PKT_PPDU; + info->u.ppdu.mac_info = !!(hdr_val & AX_RXD_MAC_INFO_VLD); + + return MACSUCCESS; +} + +static struct rxd_parse_type rxdes_parse_mac[] = { + {RXD_S_RPKT_TYPE_WIFI, rxdes_parse_wifi}, + {RXD_S_RPKT_TYPE_C2H, rxdes_parse_c2h}, + {RXD_S_RPKT_TYPE_PPDU, rxdes_parse_ppdu}, + {RXD_S_RPKT_TYPE_CH_INFO, rxdes_parse_ch_info}, + {RXD_S_RPKT_TYPE_DFS_RPT, rxdes_parse_dfs}, + {RXD_RPKT_TYPE_INVALID, NULL}, +}; + +u32 mac_parse_rxdesc(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) +{ + struct rxd_parse_type *parse = rxdes_parse_mac; + u8 rpkt_type; + u32 hdr_val; + u32 (*handler)(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) = NULL; + + hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0); + rpkt_type = (u8)GET_FIELD(hdr_val, AX_RXD_RPKT_TYPE); + + rxdes_parse_comm(adapter, info, buf); + + for (; parse->type != RXD_RPKT_TYPE_INVALID; parse++) { + if (rpkt_type == parse->type) { + handler = parse->handler; + break; + } + } + + if (!handler) { + PLTFM_MSG_ERR("[ERR]null type handler type: %X\n", parse->type); + return MACNOITEM; + } + + return handler(adapter, info, buf, len); +} + +u32 mac_wd_checksum(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *wddesc) +{ + u16 chksum = 0; + u32 wddesc_size; + u16 *data; + u32 i, dw4; + + if (!wddesc) { + PLTFM_MSG_ERR("[ERR]null pointer\n"); + return MACNPTR; + } + + if (adapter->hw_info->wd_checksum_en != 1) + PLTFM_MSG_TRACE("[TRACE]chksum disable\n"); + + dw4 = ((struct wd_body_t *)wddesc)->dword4; + + ((struct wd_body_t *)wddesc)->dword4 = + SET_CLR_WORD(dw4, 0x0, AX_TXD_TXDESC_CHECKSUM); + + data = (u16 *)(wddesc); + /*unit : 4 bytes*/ + wddesc_size = mac_txdesc_len(adapter, info) >> 2; + for (i = 0; i < wddesc_size; i++) + chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1))); + + /* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/ + /* Process eniadn issue after checksum calculation */ + ((struct wd_body_t *)wddesc)->dword4 = + SET_CLR_WORD(dw4, (u16)(chksum), AX_TXD_TXDESC_CHECKSUM); + return MACSUCCESS; +} + +u32 mac_patch_rx_rate(struct mac_ax_adapter *adapter, + struct rtw_r_meta_data *info) +{ + u32 nss; + + if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + return MACSUCCESS; + + if (is_cv(adapter, CBV)) { + if (info->rpkt_type != RX_8852A_DESC_PKT_T_WIFI || + info->ppdu_type != RX_8852A_DESC_PPDU_T_HE_SU || + info->rx_gi_ltf != RX_8852A_DESC_RX_GI_LTF_4X_0_8) + return MACSUCCESS; + + nss = GET_NSS_FROM_RX_RATE(info->rx_rate); + + if (nss == NSS_1) /* real nss = 2 */ + info->rx_rate = SET_NSS_TO_RX_RATE(info->rx_rate, NSS_2); + else if (nss == NSS_8) /* real nss = 1 */ + info->rx_rate = SET_NSS_TO_RX_RATE(info->rx_rate, NSS_1); + } + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/trx_desc.h b/phl/hal_g6/mac/mac_ax/trx_desc.h new file mode 100644 index 0000000..93dd861 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/trx_desc.h @@ -0,0 +1,226 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TRX_DESC_H_ +#define _MAC_AX_TRX_DESC_H_ + +#include "../type.h" +#include "role.h" +#if MAC_AX_8852C_SUPPORT +#include "mac_8852c/trx_desc_8852c.h" +#endif +#if MAC_AX_8192XB_SUPPORT +#include "mac_8192xb/trx_desc_8192xb.h" +#endif + +/* VHT/HE nss = rx_rate[6:4] */ +#define GET_NSS_FROM_RX_RATE(rate) (((rate) & 0x70) >> 4) +#define SET_NSS_TO_RX_RATE(rate, nss) (((rate) & 0xFF8F) | (((nss) & 0x7) << 4)) +/** + * 0000: WIFI packet + * 0001: PPDU status + * 0010: channel info + * 0011: BB scope mode + * 0100: F2P TX CMD report + * 0101: SS2FW report + * 0110: TX report + * 0111: TX payload release to host + * 1000: DFS report + * 1001: TX payload release to WLCPU + * 1010: C2H packet + */ +#define RX_8852A_DESC_PKT_T_WIFI 0 +#define RX_8852A_DESC_PKT_T_PPDU_STATUS 1 +#define RX_8852A_DESC_PKT_T_CHANNEL_INFO 2 +#define RX_8852A_DESC_PKT_T_BB_SCOPE 3 +#define RX_8852A_DESC_PKT_T_F2P_TX_CMD_RPT 4 +#define RX_8852A_DESC_PKT_T_SS2FW_RPT 5 +#define RX_8852A_DESC_PKT_T_TX_RPT 6 +#define RX_8852A_DESC_PKT_T_TX_PD_RELEASE_HOST 7 +#define RX_8852A_DESC_PKT_T_DFS_RPT 8 +#define RX_8852A_DESC_PKT_T_TX_PD_RELEASE_WLCPU 9 +#define RX_8852A_DESC_PKT_T_C2H 10 + +#define RX_8852A_DESC_PPDU_T_LCCK 0 +#define RX_8852A_DESC_PPDU_T_SCCK 1 +#define RX_8852A_DESC_PPDU_T_OFDM 2 +#define RX_8852A_DESC_PPDU_T_HT 3 +#define RX_8852A_DESC_PPDU_T_HTGF 4 +#define RX_8852A_DESC_PPDU_T_VHT_SU 5 +#define RX_8852A_DESC_PPDU_T_VHT_MU 6 +#define RX_8852A_DESC_PPDU_T_HE_SU 7 +#define RX_8852A_DESC_PPDU_T_HE_ERSU 8 +#define RX_8852A_DESC_PPDU_T_HE_MU 9 +#define RX_8852A_DESC_PPDU_T_HE_TB 10 +#define RX_8852A_DESC_PPDU_T_UNKNOWN 15 + +#define RX_8852A_DESC_RX_GI_LTF_4X_3_2 0 +#define RX_8852A_DESC_RX_GI_LTF_4X_0_8 1 +#define RX_8852A_DESC_RX_GI_LTF_2X_1_6 2 +#define RX_8852A_DESC_RX_GI_LTF_2X_0_8 3 +#define RX_8852A_DESC_RX_GI_LTF_1X_1_6 4 +#define RX_8852A_DESC_RX_GI_LTF_1X_0_8 5 + +#define NSS_8 7 +#define NSS_7 6 +#define NSS_6 5 +#define NSS_5 4 +#define NSS_4 3 +#define NSS_3 2 +#define NSS_2 1 +#define NSS_1 0 + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ +/** + * @brief mac_txdesc_len + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_txdesc_len(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_build_txdesc + * + * @param *adapter + * @param *info + * @param *buf + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_build_txdesc(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_refill_txdesc + * + * @param *adapter + * @param *txpkt_info + * @param *mask + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_refill_txdesc(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *txpkt_info, + struct mac_ax_refill_info *mask, + struct mac_ax_refill_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_parse_rxdesc + * + * @param *adapter + * @param *info + * @param *buf + * @param len + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_parse_rxdesc(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_wd_checksum + * + * @param *adapter + * @param *info + * @param *wddesc + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_wd_checksum(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *wddesc); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_patch_rx_rate + * + * @param *adapter + * @param *rtw_r_meta_data + * @return For RMAC rate patch func + * @retval u32 + */ +u32 mac_patch_rx_rate(struct mac_ax_adapter *adapter, + struct rtw_r_meta_data *info); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/trxcfg.c b/phl/hal_g6/mac/mac_ax/trxcfg.c new file mode 100644 index 0000000..2ed5f2f --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/trxcfg.c @@ -0,0 +1,1842 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "trxcfg.h" + +inline u32 check_mac_en(struct mac_ax_adapter *adapter, u8 band, + enum mac_ax_hwmod_sel sel) +{ + if (adapter->sm.pwr != MAC_AX_PWR_ON) + return MACPROCERR; + + if (sel == MAC_AX_DMAC_SEL) { + if (adapter->sm.dmac_func != MAC_AX_FUNC_ON) + return MACIOERRDMAC; + } else if (sel == MAC_AX_CMAC_SEL && band == MAC_AX_BAND_0) { + if (adapter->sm.cmac0_func != MAC_AX_FUNC_ON) + return MACIOERRCMAC0; + } else if (sel == MAC_AX_CMAC_SEL && band == MAC_AX_BAND_1) { + if (adapter->sm.cmac1_func != MAC_AX_FUNC_ON) + return MACIOERRCMAC1; + } else { + PLTFM_MSG_ERR("[ERR] mac sel: %d\n", sel); + return MACNOITEM; + } + + return MACSUCCESS; +} + +static u32 scheduler_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + + reg = band == MAC_AX_BAND_0 ? + R_AX_SCHEDULE_ERR_IMR : R_AX_SCHEDULE_ERR_IMR_C1; + val32 = MAC_REG_R32(reg); + val32 &= ~(B_AX_SORT_NON_IDLE_ERR_INT_EN | + B_AX_FSM_TIMEOUT_ERR_INT_EN); + val32 |= ((B_AX_SORT_NON_IDLE_ERR_INT_EN & + SCHEDULER_SORT_NON_IDLE_ERR_SER_EN) | + (B_AX_FSM_TIMEOUT_ERR_INT_EN & + SCHEDULER_FSM_TIMEOUT_ERR_SER_EN)); + MAC_REG_W32(reg, val32); + return 0; +} + +static u32 ptcl_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + + reg = band == MAC_AX_BAND_0 ? + R_AX_PTCL_IMR0 : R_AX_PTCL_IMR0_C1; + val32 = 0; + val32 &= ~(B_AX_FSM_TIMEOUT_ERR_INT_EN | + B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | + B_AX_TXPRT_FULL_DROP_ERR_INT_EN | + B_AX_D_PKTID_ERR_INT_EN | + B_AX_Q_PKTID_ERR_INT_EN | + B_AX_BCNQ_ORDER_ERR_INT_EN | + B_AX_TWTSP_QSEL_ERR_INT_EN | + B_AX_F2PCMD_EMPTY_ERR_INT_EN | + B_AX_TX_RECORD_PKTID_ERR_INT_EN | + B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | + B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | + B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | + B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | + B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | + B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | + B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | + B_AX_F2PCMD_PKTID_ERR_INT_EN); + + val32 |= ((B_AX_FSM_TIMEOUT_ERR_INT_EN & + PTCL_FSM_TIMEOUT_ERR_SER_EN) | + (B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN & + PTCL_F2PCMDRPT_FULL_DROP_SER_EN) | + (B_AX_TXPRT_FULL_DROP_ERR_INT_EN & + PTCL_TXRPT_FULL_DROP_SER_EN) | + (B_AX_D_PKTID_ERR_INT_EN & + PTCL_D_PKTID_ERR_SER_EN) | + (B_AX_Q_PKTID_ERR_INT_EN & + PTCL_Q_PKTID_ERR_SER_EN) | + (B_AX_BCNQ_ORDER_ERR_INT_EN & + PTCL_BCNQ_ORDER_ERR_SER_EN) | + (B_AX_TWTSP_QSEL_ERR_INT_EN & + PTCL_TWTSP_QSEL_ERR_SER_EN) | + (B_AX_F2PCMD_EMPTY_ERR_INT_EN & + PTCL_F2PCMD_EMPTY_ERR_SER_EN) | + (B_AX_TX_RECORD_PKTID_ERR_INT_EN & + PTCL_TX_RECORD_PKTID_ERR_SER_EN) | + (B_AX_TX_SPF_U3_PKTID_ERR_INT_EN & + PTCL_TX_SPF_U3_PKTID_ERR_SER_EN) | + (B_AX_TX_SPF_U2_PKTID_ERR_INT_EN & + PTCL_TX_SPF_U2_PKTID_ERR_SER_EN) | + (B_AX_TX_SPF_U1_PKTID_ERR_INT_EN & + PTCL_TX_SPF_U1_PKTID_ERR_SER_EN) | + (B_AX_RX_SPF_U0_PKTID_ERR_INT_EN & + PTCL_TX_SPF_U0_PKTID_ERR_SER_EN) | + (B_AX_F2PCMD_USER_ALLC_ERR_INT_EN & + PTCL_F2PCMD_USER_ALLC_ERR_SER_EN) | + (B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN & + PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN) | + (B_AX_F2PCMD_RD_PKTID_ERR_INT_EN & + PTCL_F2PCMD_RD_PKTID_ERR_SER_EN) | + (B_AX_F2PCMD_PKTID_ERR_INT_EN & + PTCL_F2PCMD_PKTID_ERR_SER_EN)); + MAC_REG_W32(reg, val32); + + return 0; +} + +static u32 _patch_cdma_fa(struct mac_ax_adapter *adapter) +{ + if (adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852A && + adapter->hw_info->cv <= CBV) +/* + * AP Disable B_AX_STS_FSM_HANG_ERROR_IMR + * STA Enable B_AX_STS_FSM_HANG_ERROR_IMR (Wait for "Scan+SER L0") + */ + return 0; + else if (adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852B && + adapter->hw_info->cv == CAV) + return B_AX_RXSTS_FSM_HANG_ERROR_IMR | + B_AX_RXDATA_FSM_HANG_ERROR_IMR; + return B_AX_RXSTS_FSM_HANG_ERROR_IMR | B_AX_RXDATA_FSM_HANG_ERROR_IMR; +} + +static u32 cdma_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + + reg = band == MAC_AX_BAND_0 ? R_AX_DLE_CTRL : R_AX_DLE_CTRL_C1; + val32 = MAC_REG_R32(reg); + val32 &= ~(B_AX_RXSTS_FSM_HANG_ERROR_IMR | + B_AX_RXDATA_FSM_HANG_ERROR_IMR | + B_AX_NO_RESERVE_PAGE_ERR_IMR); + val32 |= ((B_AX_RXSTS_FSM_HANG_ERROR_IMR & + CMAC_DMA_RXSTS_FSM_HANG_SER_EN) | + (B_AX_RXDATA_FSM_HANG_ERROR_IMR & + CMAC_DMA_RXDATA_FSM_HANG_SER_EN) | + (B_AX_NO_RESERVE_PAGE_ERR_IMR & + CMAC_DMA_NO_RSVD_PAGE_SER_EN)); + val32 |= _patch_cdma_fa(adapter); + MAC_REG_W32(reg, val32); + return 0; +} + +static u32 phy_intf_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u16 val16; + u32 reg; + + reg = band == MAC_AX_BAND_0 ? + R_AX_PHYINFO_ERR_IMR : R_AX_PHYINFO_ERR_IMR_C1; + val16 = MAC_REG_R16(reg); + val16 &= ~(B_AXC_PHY_TXON_TIMEOUT_INT_EN | + B_AX_CCK_CCA_TIMEOUT_INT_EN | + B_AX_OFDM_CCA_TIMEOUT_INT_EN | + B_AX_DATA_ON_TIMEOUT_INT_EN | + B_AX_STS_ON_TIMEOUT_INT_EN | + B_AX_CSI_ON_TIMEOUT_INT_EN); + + val16 |= ((B_AXC_PHY_TXON_TIMEOUT_INT_EN & + PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN) | + (B_AX_CCK_CCA_TIMEOUT_INT_EN & + PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN) | + (B_AX_OFDM_CCA_TIMEOUT_INT_EN & + PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN) | + (B_AX_DATA_ON_TIMEOUT_INT_EN & + PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN) | + (B_AX_STS_ON_TIMEOUT_INT_EN & + PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN) | + (B_AX_CSI_ON_TIMEOUT_INT_EN & + PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN)); + MAC_REG_W16(reg, val16); + return 0; +} + +static u32 rmac_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + + reg = band == MAC_AX_BAND_0 ? + R_AX_RMAC_ERR_ISR : R_AX_RMAC_ERR_ISR_C1; + val32 = MAC_REG_R32(reg); + val32 &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | + B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | + B_AX_RMAC_DMA_TIMEOUT_INT_EN | + B_AX_RMAC_CCA_TIMEOUT_INT_EN | + B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | + B_AX_RMAC_CSI_TIMEOUT_INT_EN | + B_AX_RMAC_RX_TIMEOUT_INT_EN | + B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN); + + val32 |= ((B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN & + RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN & + RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_DMA_TIMEOUT_INT_EN & + RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_CCA_TIMEOUT_INT_EN & + RMAC_CCA_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN & + RMAC_DATA_ON_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_CSI_TIMEOUT_INT_EN & + RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_RX_TIMEOUT_INT_EN & + RMAC_RX_FSM_TIMEOUT_ERR_SER_EN) | + (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN & + RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN)); + MAC_REG_W32(reg, val32); + return 0; +} + +static u32 tmac_imr_enable(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + + reg = band == MAC_AX_BAND_0 ? + R_AX_TMAC_ERR_IMR_ISR : R_AX_TMAC_ERR_IMR_ISR_C1; + val32 = MAC_REG_R32(reg); + val32 &= ~(B_AX_TMAC_MACTX_INT_EN | + B_AX_TMAC_TXCTL_INT_EN | + B_AX_TMAC_RESP_INT_EN | + B_AX_TMAC_TXPLCP_INT_EN); + + val32 |= ((B_AX_TMAC_MACTX_INT_EN & + TMAC_MACTX_TIME_ERR_SER_EN) | + (B_AX_TMAC_TXCTL_INT_EN & + TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN) | + (B_AX_TMAC_RESP_INT_EN & + TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN) | + (B_AX_TMAC_TXPLCP_INT_EN & + TMAC_TX_PLCP_INFO_ERR_SER_EN)); + MAC_REG_W32(reg, val32); + return 0; +} + +static u32 wdrls_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_WDRLS_ERR_IMR); + val32 &= ~(B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | + B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | + B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | + B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | + B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | + B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | + B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | + B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | + B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN); + + val32 |= ((B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN & + DMAC_WDRLS_CTL_WDPKTID_ISNULL_ERR_SER_EN) | + (B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN & + DMAC_WDRLS_CTL_PLPKTID_ISNULL_ERR_SER_EN) | + (B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN & + DMAC_WDRLS_CTL_FRZTO_ERR_SER_EN) | + (B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN & + DMAC_WDRLS_PLEBREQ_TO_ERR_SER_EN) | + (B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN & + DMAC_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_SER_EN) | + (B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN & + DMAC_WDRLS_RPT0_AGGNUM0_ERR_SER_EN) | + (B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN & + DMAC_WDRLS_RPT0_FRZTO_ERR_SER_EN) | + (B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN & + DMAC_WDRLS_RPT1_AGGNUM0_ERR_SER_EN) | + (B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN & + DMAC_WDRLS_RPT1_FRZTO_ERR_SER_EN)); + MAC_REG_W32(R_AX_WDRLS_ERR_IMR, val32); + return 0; +} + +static u32 wsec_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_SEC_DEBUG); + val32 &= ~(B_AX_IMR_ERROR); + + val32 |= ((B_AX_IMR_ERROR & + DMAC_IMR_ERROR)); + MAC_REG_W32(R_AX_SEC_DEBUG, val32); + return 0; +} + +static u32 mpdu_trx_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + /* MDPU Processor TX */ + val32 = MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR); + val32 &= ~(B_AX_TX_GET_ERRPKTID_INT_EN | + B_AX_TX_NXT_ERRPKTID_INT_EN | + B_AX_TX_MPDU_SIZE_ZERO_INT_EN | + B_AX_TX_OFFSET_ERR_INT_EN | + B_AX_TX_HDR3_SIZE_ERR_INT_EN); + + val32 |= ((B_AX_TX_GET_ERRPKTID_INT_EN & + DMAC_TX_GET_ERRPKTID_SER_EN) | + (B_AX_TX_NXT_ERRPKTID_INT_EN & + DMAC_TX_NXT_ERRPKTID_SER_EN) | + (B_AX_TX_MPDU_SIZE_ZERO_INT_EN & + DMAC_TX_MPDU_SIZE_ZERO_SER_EN) | + (B_AX_TX_OFFSET_ERR_INT_EN & + DMAC_TX_OFFSET_ERR_SER_EN) | + (B_AX_TX_HDR3_SIZE_ERR_INT_EN & + DMAC_TX_HDR3_SIZE_ERR_SER_EN)); + MAC_REG_W32(R_AX_MPDU_TX_ERR_IMR, val32); + + /* MDPU Processor RX */ + val32 = MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR); + val32 &= ~(B_AX_GETPKTID_ERR_INT_EN | + B_AX_MHDRLEN_ERR_INT_EN | + B_AX_RPT_ERR_INT_EN); + + val32 |= ((B_AX_GETPKTID_ERR_INT_EN & + DMAC_GETPKTID_ERR_SER_EN) | + (B_AX_MHDRLEN_ERR_INT_EN & + DMAC_MHDRLEN_ERR_SER_EN) | + (B_AX_RPT_ERR_INT_EN & + DMAC_RPT_ERR_SER_EN)); + MAC_REG_W32(R_AX_MPDU_RX_ERR_IMR, val32); + return 0; +} + +static u32 sta_sch_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + /* MDPU Processor TX */ + val32 = MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR); + val32 &= ~(B_AX_SEARCH_HANG_TIMEOUT_INT_EN | + B_AX_RPT_HANG_TIMEOUT_INT_EN | + B_AX_PLE_B_PKTID_ERR_INT_EN); + + val32 |= ((B_AX_SEARCH_HANG_TIMEOUT_INT_EN & + DMAC_SEARCH_HANG_TIMEOUT_SER_EN) | + (B_AX_RPT_HANG_TIMEOUT_INT_EN & + DMAC_RPT_HANG_TIMEOUT_SER_EN) | + (B_AX_PLE_B_PKTID_ERR_INT_EN & + DMAC_PLE_B_PKTID_ERR_SER_EN)); + MAC_REG_W32(R_AX_STA_SCHEDULER_ERR_IMR, val32); + return 0; +} + +static u32 txpktctl_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR); + val32 &= ~(B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | + B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | + B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); + + val32 |= ((B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_REINIT_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_NOINIT_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_SER_EN) | + (B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN & + DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_SER_EN) | + (B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN & + DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_SER_EN)); + MAC_REG_W32(R_AX_TXPKTCTL_ERR_IMR_ISR, val32); + + val32 = MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1); + val32 &= ~(B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | + B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | + B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | + B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); + + val32 |= ((B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_REINIT_B1_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_NOINIT_B1_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_B1_ERR_SER_EN) | + (B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN & + DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_B1_ERR_SER_EN) | + (B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN & + DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_B1_SER_EN) | + (B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN & + DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_B1_SER_EN)); + MAC_REG_W32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1, val32); + return 0; +} + +static u32 wde_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_WDE_ERR_IMR); + val32 &= ~(B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | + B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | + B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | + B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | + B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | + B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | + B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | + B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | + B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | + B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | + B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | + B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | + B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | + B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | + B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | + B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | + B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | + B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | + B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN); + + val32 |= ((B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN & + DMAC_WDE_BUFREQ_QTAID_ERR_SER_EN) | + (B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN & + DMAC_WDE_BUFREQ_UNAVAL_ERR_SER_EN) | + (B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN & + DMAC_WDE_BUFRTN_INVLD_PKTID_ERR_SER_EN) | + (B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN & + DMAC_WDE_BUFRTN_SIZE_ERR_SER_EN) | + (B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN & + DMAC_WDE_BUFREQ_SRCHTAILPG_ERR_SER_EN) | + (B_AX_WDE_GETNPG_STRPG_ERR_INT_EN & + DMAC_WDE_GETNPG_STRPG_ERR_SER_EN) | + (B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN & + DMAC_WDE_GETNPG_PGOFST_ERR_SER_EN) | + (B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN & + DMAC_WDE_BUFMGN_FRZTO_ERR_SER_EN) | + (B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN & + DMAC_WDE_QUE_CMDTYPE_ERR_SER_EN) | + (B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN & + DMAC_WDE_QUE_DSTQUEID_ERR_SER_EN) | + (B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN & + DMAC_WDE_QUE_SRCQUEID_ERR_SER_EN) | + (B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN & + DMAC_WDE_ENQ_PKTCNT_OVRF_ERR_SER_EN) | + (B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN & + DMAC_WDE_ENQ_PKTCNT_NVAL_ERR_SER_EN) | + (B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN & + DMAC_WDE_PREPKTLLT_AD_ERR_SER_EN) | + (B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN & + DMAC_WDE_NXTPKTLL_AD_ERR_SER_EN) | + (B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN & + DMAC_WDE_QUEMGN_FRZTO_ERR_SER_EN) | + (B_AX_WDE_DATCHN_ARBT_ERR_INT_EN & + DMAC_WDE_DATCHN_ARBT_ERR_SER_EN) | + (B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN & + DMAC_WDE_DATCHN_NULLPG_ERR_SER_EN) | + (B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN & + DMAC_WDE_DATCHN_FRZTO_ERR_SER_EN)); + MAC_REG_W32(R_AX_WDE_ERR_IMR, val32); + return 0; +} + +static u32 ple_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_PLE_ERR_IMR); + val32 &= ~(B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | + B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | + B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | + B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | + B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | + B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | + B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | + B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | + B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | + B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | + B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | + B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | + B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | + B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | + B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | + B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | + B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | + B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | + B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN); + + val32 |= ((B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN & + DMAC_PLE_BUFREQ_QTAID_ERR_SER_EN) | + (B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN & + DMAC_PLE_BUFREQ_UNAVAL_ERR_SER_EN) | + (B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN & + DMAC_PLE_BUFRTN_INVLD_PKTID_ERR_SER_EN) | + (B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN & + DMAC_PLE_BUFRTN_SIZE_ERR_SER_EN) | + (B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN & + DMAC_PLE_BUFREQ_SRCHTAILPG_ERR_SER_EN) | + (B_AX_PLE_GETNPG_STRPG_ERR_INT_EN & + DMAC_PLE_GETNPG_STRPG_ERR_SER_EN) | + (B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN & + DMAC_PLE_GETNPG_PGOFST_ERR_SER_EN) | + (B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN & + DMAC_PLE_BUFMGN_FRZTO_ERR_SER_EN) | + (B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN & + DMAC_PLE_QUE_CMDTYPE_ERR_SER_EN) | + (B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN & + DMAC_PLE_QUE_DSTQUEID_ERR_SER_EN) | + (B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN & + DMAC_PLE_QUE_SRCQUEID_ERR_SER_EN) | + (B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN & + DMAC_PLE_ENQ_PKTCNT_OVRF_ERR_SER_EN) | + (B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN & + DMAC_PLE_ENQ_PKTCNT_NVAL_ERR_SER_EN) | + (B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN & + DMAC_PLE_PREPKTLLT_AD_ERR_SER_EN) | + (B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN & + DMAC_PLE_NXTPKTLL_AD_ERR_SER_EN) | + (B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN & + DMAC_PLE_QUEMGN_FRZTO_ERR_SER_EN) | + (B_AX_PLE_DATCHN_ARBT_ERR_INT_EN & + DMAC_PLE_DATCHN_ARBT_ERR_SER_EN) | + (B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN & + DMAC_PLE_DATCHN_NULLPG_ERR_SER_EN) | + (B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN & + DMAC_PLE_DATCHN_FRZTO_ERR_SER_EN)); + MAC_REG_W32(R_AX_PLE_ERR_IMR, val32); + return 0; +} + +static u32 pktin_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_PKTIN_ERR_IMR); + val32 &= ~(B_AX_PKTIN_GETPKTID_ERR_INT_EN); + + val32 |= ((B_AX_PKTIN_GETPKTID_ERR_INT_EN & + DMAC_PKTIN_GETPKTID_ERR_SER_EN)); + MAC_REG_W32(R_AX_PKTIN_ERR_IMR, val32); + return 0; +} + +static u32 dispatcher_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR); + val32 &= ~(B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | + B_AX_HDT_CHANNEL_ID_ERR_INT_EN | + B_AX_HDT_PKT_FAIL_DBG_INT_EN | + B_AX_HDT_PERMU_OVERFLOW_INT_EN | + B_AX_HDT_PERMU_UNDERFLOW_INT_EN | + B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | + B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | + B_AX_HDT_OFFSET_UNMATCH_INT_EN | + B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | + B_AX_HDT_WD_CHK_ERR_INT_EN | + B_AX_HDT_PRE_COST_ERR_INT_EN | + B_AX_HDT_TXPKTSIZE_ERR_INT_EN | + B_AX_HDT_TCP_CHK_ERR_INT_EN | + B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | + B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | + B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | + B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | + B_AX_HDT_FLOW_CTRL_ERR_INT_EN | + B_AX_HDT_NULLPKT_ERR_INT_EN | + B_AX_HDT_BURST_NUM_ERR_INT_EN | + B_AX_HDT_RXAGG_CFG_ERR_INT_EN | + B_AX_HDT_SHIFT_EN_ERR_INT_EN | + B_AX_HDT_TOTAL_LEN_ERR_INT_EN | + B_AX_HDT_DMA_PROCESS_ERR_INT_EN | + B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | + B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | + B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | + B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN); + + val32 |= ((B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN & + DMAC_HDT_CHANNEL_DIFF_ERR_SER_EN) | + (B_AX_HDT_CHANNEL_ID_ERR_INT_EN & + DMAC_HDT_CHANNEL_ID_ERR_SER_EN) | + (B_AX_HDT_PKT_FAIL_DBG_INT_EN & + DMAC_HDT_PKT_FAIL_DBG_SER_EN) | + (B_AX_HDT_PERMU_OVERFLOW_INT_EN & + DMAC_HDT_PERMU_OVERFLOW_SER_EN) | + (B_AX_HDT_PERMU_UNDERFLOW_INT_EN & + DMAC_HDT_PERMU_UNDERFLOW_SER_EN) | + (B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN & + DMAC_HDT_PAYLOAD_OVERFLOW_SER_EN) | + (B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN & + DMAC_HDT_PAYLOAD_UNDERFLOW_SER_EN) | + (B_AX_HDT_OFFSET_UNMATCH_INT_EN & + DMAC_HDT_OFFSET_UNMATCH_SER_EN) | + (B_AX_HDT_CHANNEL_DMA_ERR_INT_EN & + DMAC_HDT_CHANNEL_DMA_ERR_SER_EN) | + (B_AX_HDT_WD_CHK_ERR_INT_EN & + DMAC_HDT_WD_CHK_ERR_SER_EN) | + (B_AX_HDT_PRE_COST_ERR_INT_EN & + DMAC_HDT_PRE_COST_ERR_SER_EN) | + (B_AX_HDT_TXPKTSIZE_ERR_INT_EN & + DMAC_HDT_TXPKTSIZE_ERR_SER_EN) | + (B_AX_HDT_TCP_CHK_ERR_INT_EN & + DMAC_HDT_TCP_CHK_ERR_SER_EN) | + (B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN & + DMAC_HDT_TX_WRITE_OVERFLOW_SER_EN) | + (B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN & + DMAC_HDT_TX_WRITE_UNDERFLOW_SER_EN) | + (B_AX_HDT_PLD_CMD_OVERLOW_INT_EN & + DMAC_HDT_PLD_CMD_OVERLOW_SER_EN) | + (B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN & + DMAC_HDT_PLD_CMD_UNDERFLOW_SER_EN) | + (B_AX_HDT_FLOW_CTRL_ERR_INT_EN & + DMAC_HDT_FLOW_CTRL_ERR_SER_EN) | + (B_AX_HDT_NULLPKT_ERR_INT_EN & + DMAC_HDT_NULLPKT_ERR_SER_EN) | + (B_AX_HDT_BURST_NUM_ERR_INT_EN & + DMAC_HDT_BURST_NUM_ERR_SER_EN) | + (B_AX_HDT_RXAGG_CFG_ERR_INT_EN & + DMAC_HDT_RXAGG_CFG_ERR_SER_EN) | + (B_AX_HDT_SHIFT_EN_ERR_INT_EN & + DMAC_HDT_SHIFT_EN_ERR_SER_EN) | + (B_AX_HDT_TOTAL_LEN_ERR_INT_EN & + DMAC_HDT_TOTAL_LEN_ERR_SER_EN) | + (B_AX_HDT_DMA_PROCESS_ERR_INT_EN & + DMAC_HDT_DMA_PROCESS_ERR_SER_EN) | + (B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN & + DMAC_HDT_SHIFT_DMA_CFG_ERR_SER_EN) | + (B_AX_HDT_CHKSUM_FSM_ERR_INT_EN & + DMAC_HDT_CHKSUM_FSM_ERR_SER_EN) | + (B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN & + DMAC_HDT_RX_WRITE_OVERFLOW_SER_EN) | + (B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN & + DMAC_HDT_RX_WRITE_UNDERFLOW_SER_EN)); + MAC_REG_W32(R_AX_HOST_DISPATCHER_ERR_IMR, val32); + + val32 = MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR); + val32 &= ~(B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | + B_AX_CPU_PKT_FAIL_DBG_INT_EN | + B_AX_CPU_CHANNEL_ID_ERR_INT_EN | + B_AX_CPU_PERMU_OVERFLOW_INT_EN | + B_AX_CPU_PERMU_UNDERFLOW_INT_EN | + B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | + B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | + B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | + B_AX_CPU_OFFSET_UNMATCH_INT_EN | + B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | + B_AX_CPU_WD_CHK_ERR_INT_EN | + B_AX_CPU_PRE_COST_ERR_INT_EN | + B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | + B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | + B_AX_CPU_F2P_QSEL_ERR_INT_EN | + B_AX_CPU_F2P_SEQ_ERR_INT_EN | + B_AX_CPU_FLOW_CTRL_ERR_INT_EN | + B_AX_CPU_NULLPKT_ERR_INT_EN | + B_AX_CPU_BURST_NUM_ERR_INT_EN | + B_AX_CPU_RXAGG_CFG_ERR_INT_EN | + B_AX_CPU_SHIFT_EN_ERR_INT_EN | + B_AX_CPU_TOTAL_LEN_ERR_INT_EN | + B_AX_CPU_DMA_PROCESS_ERR_INT_EN | + B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | + B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | + B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | + B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN); + + val32 |= ((B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN & + DMAC_CPU_CHANNEL_DIFF_ERR_SER_EN) | + (B_AX_CPU_PKT_FAIL_DBG_INT_EN & + DMAC_CPU_PKT_FAIL_DBG_SER_EN) | + (B_AX_CPU_CHANNEL_ID_ERR_INT_EN & + DMAC_CPU_CHANNEL_ID_ERR_SER_EN) | + (B_AX_CPU_PERMU_OVERFLOW_INT_EN & + DMAC_CPU_PERMU_OVERFLOW_SER_EN) | + (B_AX_CPU_PERMU_UNDERFLOW_INT_EN & + DMAC_CPU_PERMU_UNDERFLOW_SER_EN) | + (B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN & + DMAC_CPU_PAYLOAD_OVERFLOW_SER_EN) | + (B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN & + DMAC_CPU_PAYLOAD_UNDERFLOW_SER_EN) | + (B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN & + DMAC_CPU_PAYLOAD_CHKSUM_ERR_SER_EN) | + (B_AX_CPU_OFFSET_UNMATCH_INT_EN & + DMAC_CPU_OFFSET_UNMATCH_SER_EN) | + (B_AX_CPU_CHANNEL_DMA_ERR_INT_EN & + DMAC_CPU_CHANNEL_DMA_ERR_SER_EN) | + (B_AX_CPU_WD_CHK_ERR_INT_EN & + DMAC_CPU_WD_CHK_ERR_SER_EN) | + (B_AX_CPU_PRE_COST_ERR_INT_EN & + DMAC_CPU_PRE_COST_ERR_SER_EN) | + (B_AX_CPU_PLD_CMD_OVERLOW_INT_EN & + DMAC_CPU_PLD_CMD_OVERLOW_SER_EN) | + (B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN & + DMAC_CPU_PLD_CMD_UNDERFLOW_SER_EN) | + (B_AX_CPU_F2P_QSEL_ERR_INT_EN & + DMAC_CPU_F2P_QSEL_ERR_SER_EN) | + (B_AX_CPU_F2P_SEQ_ERR_INT_EN & + DMAC_CPU_F2P_SEQ_ERR_SER_EN) | + (B_AX_CPU_FLOW_CTRL_ERR_INT_EN & + DMAC_CPU_FLOW_CTRL_ERR_SER_EN) | + (B_AX_CPU_NULLPKT_ERR_INT_EN & + DMAC_CPU_NULLPKT_ERR_SER_EN) | + (B_AX_CPU_BURST_NUM_ERR_INT_EN & + DMAC_CPU_BURST_NUM_ERR_SER_EN) | + (B_AX_CPU_RXAGG_CFG_ERR_INT_EN & + DMAC_CPU_RXAGG_CFG_ERR_SER_EN) | + (B_AX_CPU_SHIFT_EN_ERR_INT_EN & + DMAC_CPU_SHIFT_EN_ERR_SER_EN) | + (B_AX_CPU_TOTAL_LEN_ERR_INT_EN & + DMAC_CPU_TOTAL_LEN_ERR_SER_EN) | + (B_AX_CPU_DMA_PROCESS_ERR_INT_EN & + DMAC_CPU_DMA_PROCESS_ERR_SER_EN) | + (B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN & + DMAC_CPU_SHIFT_DMA_CFG_ERR_SER_EN) | + (B_AX_CPU_CHKSUM_FSM_ERR_INT_EN & + DMAC_CPU_CHKSUM_FSM_ERR_SER_EN)); + MAC_REG_W32(R_AX_CPU_DISPATCHER_ERR_IMR, val32); + + val32 = MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR); + val32 &= ~(B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | + B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | + B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | + B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | + B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | + B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | + B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | + B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | + B_AX_PLE_OUTPUT_ERR_INT_EN | + B_AX_PLE_RESP_ERR_INT_EN | + B_AX_PLE_BURST_NUM_ERR_INT_EN | + B_AX_PLE_NULL_PKT_ERR_INT_EN | + B_AX_PLE_FLOW_CTRL_ERR_INT_EN | + B_AX_WDE_OUTPUT_ERR_INT_EN | + B_AX_WDE_RESP_ERR_INT_EN | + B_AX_WDE_BURST_NUM_ERR_INT_EN | + B_AX_WDE_NULL_PKT_ERR_INT_EN | + B_AX_WDE_FLOW_CTRL_ERR_INT_EN); + + val32 |= ((B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN & + DMAC_OTHER_STF_WROQT_UNDERFLOW_SER_EN) | + (B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN & + DMAC_OTHER_STF_WROQT_OVERFLOW_SER_EN) | + (B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN & + DMAC_OTHER_STF_WRFF_UNDERFLOW_SER_EN) | + (B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN & + DMAC_OTHER_STF_WRFF_OVERFLOW_SER_EN) | + (B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN & + DMAC_OTHER_STF_CMD_UNDERFLOW_SER_EN) | + (B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN & + DMAC_OTHER_STF_CMD_OVERFLOW_SER_EN) | + (B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN & + DMAC_HOST_ADDR_INFO_LEN_ZERO_ERR_SER_EN) | + (B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN & + DMAC_CPU_ADDR_INFO_LEN_ZERO_ERR_SER_EN) | + (B_AX_PLE_OUTPUT_ERR_INT_EN & + DMAC_PLE_OUTPUT_ERR_SER_EN) | + (B_AX_PLE_RESP_ERR_INT_EN & + DMAC_PLE_RESP_ERR_SER_EN) | + (B_AX_PLE_BURST_NUM_ERR_INT_EN & + DMAC_PLE_BURST_NUM_ERR_SER_EN) | + (B_AX_PLE_NULL_PKT_ERR_INT_EN & + DMAC_PLE_NULL_PKT_ERR_SER_EN) | + (B_AX_PLE_FLOW_CTRL_ERR_INT_EN & + DMAC_PLE_FLOW_CTRL_ERR_SER_EN) | + (B_AX_WDE_OUTPUT_ERR_INT_EN & + DMAC_WDE_OUTPUT_ERR_SER_EN) | + (B_AX_WDE_RESP_ERR_INT_EN & + DMAC_WDE_RESP_ERR_SER_EN) | + (B_AX_WDE_BURST_NUM_ERR_INT_EN & + DMAC_WDE_BURST_NUM_ERR_SER_EN) | + (B_AX_WDE_NULL_PKT_ERR_INT_EN & + DMAC_WDE_NULL_PKT_ERR_SER_EN) | + (B_AX_WDE_FLOW_CTRL_ERR_INT_EN & + DMAC_WDE_FLOW_CTRL_ERR_SER_EN)); + MAC_REG_W32(R_AX_OTHER_DISPATCHER_ERR_IMR, val32); + return 0; +} + +static u32 cpuio_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_CPUIO_ERR_IMR); + val32 &= ~(B_AX_WDEBUF_OP_ERR_INT_EN | + B_AX_WDEQUE_OP_ERR_INT_EN | + B_AX_PLEBUF_OP_ERR_INT_EN | + B_AX_PLEQUE_OP_ERR_INT_EN); + + val32 |= ((B_AX_WDEBUF_OP_ERR_INT_EN & + DMAC_WDEBUF_OP_ERR_SER_EN) | + (B_AX_WDEQUE_OP_ERR_INT_EN & + DMAC_WDEQUE_OP_ERR_SER_EN) | + (B_AX_PLEBUF_OP_ERR_INT_EN & + DMAC_PLEBUF_OP_ERR_SER_EN) | + (B_AX_PLEQUE_OP_ERR_INT_EN & + DMAC_PLEQUE_OP_ERR_SER_EN)); + MAC_REG_W32(R_AX_CPUIO_ERR_IMR, val32); + return 0; +} + +static u32 bbrpt_imr_enable(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + + val32 = MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR); + val32 &= ~(B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); + + val32 |= ((B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN & + DMAC_BBRPT_COM_NULL_PLPKTID_ERR_SER_EN)); + MAC_REG_W32(R_AX_BBRPT_COM_ERR_IMR_ISR, val32); + + val32 = MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR); + val32 &= ~(B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | + B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | + B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | + B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | + B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | + B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | + B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | + B_AX_BBPRT_CHIF_TO_ERR_INT_EN); + + val32 |= ((B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN & + DMAC_BBPRT_CHIF_BB_TO_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_OVF_ERR_INT_EN & + DMAC_BBPRT_CHIF_OVF_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN & + DMAC_BBPRT_CHIF_BOVF_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN & + DMAC_BBPRT_CHIF_HDRL_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN & + DMAC_BBPRT_CHIF_LEFT1_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN & + DMAC_BBPRT_CHIF_LEFT2_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_NULL_ERR_INT_EN & + DMAC_BBPRT_CHIF_NULL_ERR_SER_EN) | + (B_AX_BBPRT_CHIF_TO_ERR_INT_EN & + DMAC_BBPRT_CHIF_TO_ERR_SER_EN)); + MAC_REG_W32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR, val32); + + val32 = MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR_ISR); + val32 &= ~(B_AX_BBRPT_DFS_TO_ERR_INT_EN); + + val32 |= ((B_AX_BBRPT_DFS_TO_ERR_INT_EN & + DMAC_BBRPT_DFS_TO_ERR_SER_EN)); + MAC_REG_W32(R_AX_BBRPT_DFS_ERR_IMR_ISR, val32); + + val32 = MAC_REG_R32(R_AX_LA_ERRFLAG); + val32 &= ~(B_AX_LA_IMR_DATA_LOSS_ERR); + + val32 |= ((B_AX_LA_IMR_DATA_LOSS_ERR & + DMAC_LA_IMR_DATA_LOSS_ERR)); + MAC_REG_W32(R_AX_LA_ERRFLAG, val32); + return 0; +} + +static u32 sta_sch_init(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val8; + u32 cnt, ret, val32; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val8 = MAC_REG_R8(R_AX_SS_CTRL); + val8 |= B_AX_SS_EN; + MAC_REG_W8(R_AX_SS_CTRL, val8); + + cnt = TRXCFG_WAIT_CNT; + while (cnt--) { + if (MAC_REG_R32(R_AX_SS_CTRL) & B_AX_SS_INIT_DONE_1) + break; + PLTFM_DELAY_US(TRXCFG_WAIT_US); + } + + if (!++cnt) { + PLTFM_MSG_ERR("[ERR]STA scheduler init\n"); + return MACPOLLTO; + } + + MAC_REG_W32(R_AX_SS_CTRL, + MAC_REG_R32(R_AX_SS_CTRL) | B_AX_SS_WARM_INIT_FLG); + + val32 = MAC_REG_R32(R_AX_SS_CTRL); + if (info->trx_mode == MAC_AX_TRX_SW_MODE) + val32 |= B_AX_SS_NONEMPTY_SS2FINFO_EN; + else + val32 &= ~B_AX_SS_NONEMPTY_SS2FINFO_EN; + MAC_REG_W32(R_AX_SS_CTRL, val32); + + return MACSUCCESS; +} + +static u32 scheduler_init(struct mac_ax_adapter *adapter, u8 band) +{ + u32 reg, val32, ret; + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct mac_ax_edca_param edca_para; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_1_C1 : R_AX_PREBKF_CFG_1; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, SIFS_MACTXEN_T1, B_AX_SIFS_MACTXEN_T1); + MAC_REG_W32(reg, val32); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + reg = band == MAC_AX_BAND_1 ? + R_AX_SCH_EXT_CTRL_C1 : R_AX_SCH_EXT_CTRL; + val32 = MAC_REG_R32(reg) | B_AX_PORT_RST_TSF_ADV; + MAC_REG_W32(reg, val32); + } + +#if MAC_AX_ASIC_TEMP + reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CFG_0_C1 : R_AX_CCA_CFG_0; + val32 = MAC_REG_R32(reg) & ~(B_AX_BTCCA_EN); + MAC_REG_W32(reg, val32); +#endif + +#ifdef PHL_FEATURE_AP + reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 : R_AX_PREBKF_CFG_0; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, SCH_PREBKF_16US, B_AX_PREBKF_TIME); + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_CCA_CFG_0_C1 : R_AX_CCA_CFG_0; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, 0x6a, B_AX_R_SIFS_AGGR_TIME); + MAC_REG_W32(reg, val32); + +#else /*for NIC mode setting*/ + reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 : R_AX_PREBKF_CFG_0; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, SCH_PREBKF_24US, B_AX_PREBKF_TIME); + MAC_REG_W32(reg, val32); +#endif + edca_para.band = band; + edca_para.path = MAC_AX_CMAC_PATH_SEL_BCN; + edca_para.ecw_min = 0; + edca_para.ecw_max = 1; + edca_para.aifs_us = BCN_IFS_25US; + ret = set_hw_edca_param(adapter, &edca_para); + + return ret; +} + +static u32 mpdu_proc_init(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + MAC_REG_W32(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); + MAC_REG_W32(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); + val32 = MAC_REG_R32(R_AX_MPDU_PROC); + val32 |= (B_AX_APPEND_FCS | B_AX_A_ICV_ERR); + MAC_REG_W32(R_AX_MPDU_PROC, val32); + MAC_REG_W32(R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); + + return MACSUCCESS; +} + +static u32 sec_eng_init(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32 = 0; + u32 ret; + + ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL); + // init clock + val32 |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); + // init TX encryption + val32 |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); + val32 |= (B_AX_MC_DEC | B_AX_BC_DEC); + val32 |= (B_AX_BMC_MGNT_DEC | B_AX_UC_MGNT_DEC); + val32 &= ~B_AX_TX_PARTIAL_MODE; + MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32); + + //init MIC ICV append + val32 = MAC_REG_R32(R_AX_SEC_MPDU_PROC); + val32 |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); + + // option init + MAC_REG_W32(R_AX_SEC_MPDU_PROC, val32); + + return MACSUCCESS; +} + +static u32 tmac_init(struct mac_ax_adapter *adapter, u8 band, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg, val32, ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_MAC_LOOPBACK_C1 : R_AX_MAC_LOOPBACK; + val32 = MAC_REG_R32(reg); + if (info->trx_mode == MAC_AX_TRX_LOOPBACK) + val32 |= B_AX_MACLBK_EN; + else + val32 &= ~B_AX_MACLBK_EN; + MAC_REG_W32(reg, val32); +#if MAC_AX_FPGA_TEST + reg = band == MAC_AX_BAND_1 ? R_AX_MAC_LOOPBACK_C1 : R_AX_MAC_LOOPBACK; + val32 = MAC_REG_R32(reg); + if (info->trx_mode == MAC_AX_TRX_LOOPBACK) + val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_FPGA, + B_AX_MACLBK_PLCP_DLY); + else + val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_DEF, + B_AX_MACLBK_PLCP_DLY); + MAC_REG_W32(reg, val32); +#endif + return MACSUCCESS; +} + +static u32 trxptcl_init(struct mac_ax_adapter *adapter, u8 band, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg, val32, ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? + R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_CCK, + B_AX_WMAC_SPEC_SIFS_CCK); + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) + val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52A, + B_AX_WMAC_SPEC_SIFS_OFDM); + else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52B, + B_AX_WMAC_SPEC_SIFS_OFDM); + else + val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52C, + B_AX_WMAC_SPEC_SIFS_OFDM); + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_RXTRIG_TEST_USER_2_C1 : R_AX_RXTRIG_TEST_USER_2; + val32 = MAC_REG_R32(reg); + val32 |= B_AX_RXTRIG_FCSCHK_EN; + MAC_REG_W32(reg, val32); + + return MACSUCCESS; +} + +static u32 rmac_init(struct mac_ax_adapter *adapter, u8 band, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + struct rst_bacam_info rst_info; + u32 ret; + u8 val8; + u16 val16; + u32 val32, rx_max_len, rx_max_pg, reg; + u32 rx_min_qta, rx_max_lenb; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (band == MAC_AX_BAND_0) { + rst_info.type = BACAM_RST_ALL; + rst_info.ent = 0; + ret = rst_bacam(adapter, &rst_info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]bacam rst %d\n", ret); + return ret; + } + } + + reg = band == MAC_AX_BAND_1 ? + R_AX_RESPBA_CAM_CTRL_C1 : R_AX_RESPBA_CAM_CTRL; + val8 = MAC_REG_R8(reg) | B_AX_SSN_SEL; + MAC_REG_W8(reg, val8); + + reg = band == MAC_AX_BAND_1 ? + R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL; + val16 = MAC_REG_R16(reg); + val16 = SET_CLR_WORD(val16, TRXCFG_RMAC_DATA_TO, + B_AX_RX_DLK_DATA_TIME); + val16 = SET_CLR_WORD(val16, TRXCFG_RMAC_CCA_TO, + B_AX_RX_DLK_CCA_TIME); + val16 |= B_AX_RX_DLK_RST_EN; + MAC_REG_W16(reg, val16); + + reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR; + val8 = MAC_REG_R8(reg); + if (band == MAC_AX_BAND_0 && info->trx_mode == MAC_AX_TRX_SW_MODE) + val8 = SET_CLR_WORD(val8, 0xF, B_AX_CH_EN); + else + val8 = SET_CLR_WORD(val8, 0x1, B_AX_CH_EN); + MAC_REG_W8(reg, val8); + + rx_min_qta = band == MAC_AX_BAND_1 ? + adapter->dle_info.c1_rx_qta : adapter->dle_info.c0_rx_qta; + rx_max_pg = rx_min_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_min_qta; + rx_max_lenb = rx_max_pg * adapter->dle_info.ple_pg_size; + if (rx_max_lenb < RX_SPEC_MAX_LEN) + PLTFM_MSG_ERR("[ERR]B%dRX max len %d illegal\n", + band, rx_max_lenb); + else + rx_max_lenb = RX_SPEC_MAX_LEN; + + /* rx_max_len shall not be larger than B_AX_RX_MPDU_MAX_LEN_MSK */ + rx_max_len = rx_max_lenb / RX_MAX_LEN_UNIT; + + reg = band == MAC_AX_BAND_1 ? R_AX_RX_FLTR_OPT_C1 : R_AX_RX_FLTR_OPT; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, rx_max_len, B_AX_RX_MPDU_MAX_LEN); + MAC_REG_W32(reg, val32); + + if (is_cv(adapter, CBV) && + is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) { + reg = band == MAC_AX_BAND_1 ? + R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL; + val16 = MAC_REG_R16(reg); + val16 = SET_CLR_WORD(val16, 0x0, B_AX_RX_DLK_CCA_TIME); + MAC_REG_W16(reg, val16); + + reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR; + val16 = MAC_REG_R16(reg); + MAC_REG_W16(reg, val16 | BIT12); + } else { + //cut_ver_checker + } + + /* Add drv_info dbg size as dummy (SDIO) */ + if (adapter->hw_info->intf == MAC_AX_INTF_SDIO && + adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852A) { + val16 = MAC_REG_R16(R_AX_RCR); + MAC_REG_W16(R_AX_RCR, val16 | + SET_WORD(SDIO_DRV_INFO_SIZE, B_AX_DRV_INFO_SIZE)); + } + + /* NOT ALL vendors calculate VHT SIG-B's CRC */ + reg = band == MAC_AX_BAND_1 ? + R_AX_PLCP_HDR_FLTR_C1 : R_AX_PLCP_HDR_FLTR; + val8 = MAC_REG_R8(reg) & ~B_AX_VHT_SU_SIGB_CRC_CHK; + MAC_REG_W8(reg, val8); + + return MACSUCCESS; +} + +static u32 cmac_com_init(struct mac_ax_adapter *adapter, u8 band, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + u32 ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? + R_AX_TX_SUB_CARRIER_VALUE_C1 : R_AX_TX_SUB_CARRIER_VALUE; + val32 = MAC_REG_R32(reg); + if (info->trx_mode == MAC_AX_TRX_LOOPBACK) { + val32 = SET_CLR_WORD(val32, S_AX_TXSC_20M_4, B_AX_TXSC_20M); + val32 = SET_CLR_WORD(val32, S_AX_TXSC_40M_4, B_AX_TXSC_40M); + val32 = SET_CLR_WORD(val32, S_AX_TXSC_80M_4, B_AX_TXSC_80M); + } else { + val32 = SET_CLR_WORD(val32, S_AX_TXSC_20M_0, B_AX_TXSC_20M); + val32 = SET_CLR_WORD(val32, S_AX_TXSC_40M_0, B_AX_TXSC_40M); + val32 = SET_CLR_WORD(val32, S_AX_TXSC_80M_0, B_AX_TXSC_80M); + } + MAC_REG_W32(reg, val32); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + reg = band == MAC_AX_BAND_1 ? + R_AX_PTCL_RRSR1_C1 : R_AX_PTCL_RRSR1; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, RRSR_OFDM_CCK_EN, + B_AX_RRSR_RATE_EN); + MAC_REG_W32(reg, val32); + } + + return MACSUCCESS; +} + +static void _patch_vht_ampdu_max_len(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 reg; + + if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) && + !is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) + return; + + reg = band == MAC_AX_BAND_1 ? + R_AX_AGG_LEN_VHT_0_C1 : R_AX_AGG_LEN_VHT_0; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, AMPDU_MAX_LEN_VHT_262K, + B_AX_AMPDU_MAX_LEN_VHT); + MAC_REG_W32(reg, val32); +} + +static u32 ptcl_init(struct mac_ax_adapter *adapter, u8 band, + struct mac_ax_trx_info *info) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32; + u32 ret; + u8 val8; + u32 reg; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) { + ret = is_qta_poh(adapter, info->qta_mode, &val8); + if (ret) + return ret; + if (val8) { + reg = band == MAC_AX_BAND_1 ? + R_AX_SIFS_SETTING_C1 : R_AX_SIFS_SETTING; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, S_AX_CTS2S_TH_1K, + B_AX_HW_CTS2SELF_PKT_LEN_TH); + val32 = SET_CLR_WORD(val32, S_AX_CTS2S_TH_SEC_256B, + B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW); + val32 |= B_AX_HW_CTS2SELF_EN; + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_PTCL_FSM_MON_C1 : R_AX_PTCL_FSM_MON; + val32 = MAC_REG_R32(reg); + val32 = SET_CLR_WORD(val32, S_AX_PTCL_TO_2MS, + B_AX_PTCL_TX_ARB_TO_THR); + val32 &= ~B_AX_PTCL_TX_ARB_TO_MODE; + MAC_REG_W32(reg, val32); + } + } + + if (band == MAC_AX_BAND_0) { + val8 = MAC_REG_R8(R_AX_PTCL_COMMON_SETTING_0); + if (info->trx_mode == MAC_AX_TRX_SW_MODE) { + val8 &= ~(B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); + val8 |= B_AX_PTCL_TRIGGER_SS_EN_0 | + B_AX_PTCL_TRIGGER_SS_EN_1 | + B_AX_PTCL_TRIGGER_SS_EN_UL; + } else { + val8 |= B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1; + val8 &= ~(B_AX_PTCL_TRIGGER_SS_EN_0 | + B_AX_PTCL_TRIGGER_SS_EN_1 | + B_AX_PTCL_TRIGGER_SS_EN_UL); + } + MAC_REG_W8(R_AX_PTCL_COMMON_SETTING_0, val8); + + val8 = MAC_REG_R8(R_AX_PTCLRPT_FULL_HDL); + val8 = SET_CLR_WORD(val8, FWD_TO_WLCPU, B_AX_SPE_RPT_PATH); + MAC_REG_W8(R_AX_PTCLRPT_FULL_HDL, val8); + } else if (band == MAC_AX_BAND_1) { + val8 = MAC_REG_R8(R_AX_PTCLRPT_FULL_HDL_C1); + val8 = SET_CLR_WORD(val8, FWD_TO_WLCPU, B_AX_SPE_RPT_PATH); + MAC_REG_W8(R_AX_PTCLRPT_FULL_HDL_C1, val8); + } + + _patch_vht_ampdu_max_len(adapter, band); + + return MACSUCCESS; +} + +static u32 cmac_dma_init(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_rx_ctrl; + u32 ret; + u8 val8, rx_full_mode; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + rx_full_mode = B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | + B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | + B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE; + + reg_rx_ctrl = (band == MAC_AX_BAND_1) ? + R_AX_RXDMA_CTRL_0_C1 : R_AX_RXDMA_CTRL_0; + val8 = MAC_REG_R8(reg_rx_ctrl) & ~rx_full_mode; + MAC_REG_W8(reg_rx_ctrl, val8); + } else { + return MACSUCCESS; + } + + return MACSUCCESS; +} + +static void _patch_dis_resp_chk(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg, val32; + u32 b_rsp_chk_nav, b_rsp_chk_cca; + + b_rsp_chk_nav = B_AX_RSP_CHK_TX_NAV | B_AX_RSP_CHK_INTRA_NAV | + B_AX_RSP_CHK_BASIC_NAV; + + b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | + B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | + B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + reg = band == MAC_AX_BAND_1 ? + R_AX_RSP_CHK_SIG_C1 : R_AX_RSP_CHK_SIG; + val32 = MAC_REG_R32(reg) & ~b_rsp_chk_nav; + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0; + val32 = MAC_REG_R32(reg) & ~b_rsp_chk_cca; + MAC_REG_W32(reg, val32); + } else { + reg = band == MAC_AX_BAND_1 ? + R_AX_RSP_CHK_SIG_C1 : R_AX_RSP_CHK_SIG; + val32 = MAC_REG_R32(reg) | b_rsp_chk_nav; + MAC_REG_W32(reg, val32); + + reg = band == MAC_AX_BAND_1 ? + R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0; + val32 = MAC_REG_R32(reg) | b_rsp_chk_cca; + MAC_REG_W32(reg, val32); + } +} + +static u32 cca_ctrl_init(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + u32 ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CONTROL_C1 : R_AX_CCA_CONTROL; + val32 = MAC_REG_R32(reg); + val32 |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | + B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | + B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | + B_AX_CTN_CHK_INTRA_NAV | + B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | + B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | + B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | + B_AX_CTN_CHK_CCA_P20); + val32 &= (~B_AX_TB_CHK_TX_NAV & ~B_AX_TB_CHK_CCA_S80 & + ~B_AX_TB_CHK_CCA_S40 & ~B_AX_TB_CHK_CCA_S20 & + ~B_AX_SIFS_CHK_CCA_S80 & ~B_AX_SIFS_CHK_CCA_S40 & + ~B_AX_SIFS_CHK_CCA_S20 & ~B_AX_SIFS_CHK_EDCCA & + ~B_AX_CTN_CHK_TXNAV); + MAC_REG_W32(reg, val32); + + _patch_dis_resp_chk(adapter, band); + + return MACSUCCESS; +} + +u32 mac_sifs_chk_cca_en(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, reg; + u32 ret; + + ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CONTROL_C1 : R_AX_CCA_CONTROL; + val32 = MAC_REG_R32(reg); + val32 |= (B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | + B_AX_SIFS_CHK_CCA_S20 | B_AX_SIFS_CHK_EDCCA); + MAC_REG_W32(reg, val32); + + return MACSUCCESS; +} + +static u32 nav_ctrl_init(struct mac_ax_adapter *adapter, u8 band) +{ + struct mac_ax_2nav_info info; + u32 ret; + + info.plcp_upd_nav_en = 1; + info.tgr_fram_upd_nav_en = 1; + info.nav_up = NAV_12MS; + ret = mac_two_nav_cfg(adapter, &info); + + return MACSUCCESS; +} + +u32 dmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info, + enum mac_ax_band band) +{ + u32 ret = 0; + + ret = dle_init(adapter, info->qta_mode, MAC_AX_QTA_INVALID); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]DLE init %d\n", ret); + return ret; + } + + ret = hfc_init(adapter, 1, 1, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]HCI FC init %d\n", ret); + return ret; + } + + ret = sta_sch_init(adapter, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]STA SCH init %d\n", ret); + return ret; + } + + ret = mpdu_proc_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]MPDU Proc init %d\n", ret); + return ret; + } + + ret = sec_eng_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]Security Engine init %d\n", ret); + return ret; + } + + return ret; +} + +u32 cmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info, + enum mac_ax_band band) +{ + u32 ret; + + ret = scheduler_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d SCH init %d\n", band, ret); + return ret; + } + + ret = rst_port_info(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d rst port info %d\n", band, ret); + return ret; + } + + ret = addr_cam_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d ADDR_CAM reset %d\n", band, ret); + return ret; + } + + ret = rx_fltr_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d RX filter init %d\n", band, ret); + return ret; + } + + ret = cca_ctrl_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d CCA CTRL init %d\n", band, ret); + return ret; + } + + ret = nav_ctrl_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d NAV CTRL init %d\n", band, ret); + return ret; + } + + ret = spatial_reuse_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d Spatial Reuse init %d\n", band, ret); + return ret; + } + + ret = tmac_init(adapter, band, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d TMAC init %d\n", band, ret); + return ret; + } + + ret = trxptcl_init(adapter, band, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d TRXPTCL init %d\n", band, ret); + return ret; + } + + ret = rmac_init(adapter, band, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d RMAC init %d\n", band, ret); + return ret; + } + + ret = cmac_com_init(adapter, band, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d Com init %d\n", band, ret); + return ret; + } + + ret = ptcl_init(adapter, band, info); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d PTCL init %d\n", band, ret); + return ret; + } + + ret = cmac_dma_init(adapter, band); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d DMA init %d\n", band, ret); + return ret; + } + + return ret; +} + +u32 mac_check_access(struct mac_ax_adapter *adapter, u32 offset) +{ + if (offset >= CMAC1_START_ADDR && offset <= CMAC1_END_ADDR) { + if (adapter->dle_info.qta_mode == MAC_AX_QTA_SCC) + return MACHWNOTEN; + else if (adapter->dle_info.qta_mode == MAC_AX_QTA_SCC_STF) + return MACHWNOTEN; + else + return MACSUCCESS; + } else { + return MACSUCCESS; + } +} + +u32 mac_enable_imr(struct mac_ax_adapter *adapter, u8 band, + enum mac_ax_hwmod_sel sel) +{ + u32 ret; + + ret = check_mac_en(adapter, band, sel); + if (ret) { + PLTFM_MSG_ERR("MAC%d band%d is not ready\n", sel, band); + return ret; + } + + if (sel == MAC_AX_DMAC_SEL) { + ret = wdrls_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]wdrls_imr_enable %d\n", ret); + return ret; + } + + ret = wsec_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]wsec_imr_enable %d\n", ret); + return ret; + } + + ret = mpdu_trx_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]mpdu_trx_imr_enable %d\n", ret); + return ret; + } + + ret = sta_sch_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]sta_sch_imr_enable %d\n", ret); + return ret; + } + + ret = txpktctl_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]txpktctl_imr_enable %d\n", ret); + return ret; + } + + ret = wde_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]wde_imr_enable %d\n", ret); + return ret; + } + + ret = ple_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]ple_imr_enable %d\n", ret); + return ret; + } + + ret = pktin_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]pktin_imr_enable %d\n", ret); + return ret; + } + + ret = dispatcher_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]dispatcher_imr_enable %d\n", ret); + return ret; + } + + ret = cpuio_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]cpuio_imr_enable %d\n", ret); + return ret; + } + + ret = bbrpt_imr_enable(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]bbrpt_imr_enable %d\n", ret); + return ret; + } + } else if (sel == MAC_AX_CMAC_SEL) { + ret = scheduler_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]scheduler_imr_enable %d\n", ret); + return ret; + } + + ret = ptcl_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]ptcl_imr_enable %d\n", ret); + return ret; + } + + ret = cdma_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]cdma_imr_enable %d\n", ret); + return ret; + } + + ret = phy_intf_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]phy_intf_imr_enable %d\n", ret); + return ret; + } + + ret = rmac_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]rmac_imr_enable %d\n", ret); + return ret; + } + + ret = tmac_imr_enable(adapter, band); + if (ret) { + PLTFM_MSG_ERR("[ERR]tmac_imr_enable %d\n", ret); + return ret; + } + } else { + PLTFM_MSG_ERR("illegal sel %d\n", sel); + return MACNOITEM; + } + return MACSUCCESS; +} + +#if MAC_AX_COEX_INIT_EN +static u32 coex_mac_init(struct mac_ax_adapter *adapter) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u8 val; + u32 ret; + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) { + ret = mac_write_lte(adapter, R_AX_LTECOEX_CTRL, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Write LTE REG fail\n"); + return ret; + } + + ret = mac_write_lte(adapter, R_AX_LTECOEX_CTRL_2, 0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("Write LTE REG fail\n"); + return ret; + } + + val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3); + MAC_REG_W8(R_AX_SYS_SDIO_CTRL + 3, val | BIT(2)); + } else { + MAC_REG_W32(R_AX_GNT_SW_CTRL, 0); + } + + return MACSUCCESS; +} +#endif + +u32 mac_trx_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info) +{ + u32 ret = 0; + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + u8 val8; + + /* Check TRX status is idle later. */ + ret = dmac_init(adapter, info, MAC_AX_BAND_0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]DMAC init %d\n", ret); + return ret; + } + + ret = cmac_init(adapter, info, MAC_AX_BAND_0); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]CMAC%d init %d\n", MAC_AX_BAND_0, ret); + return ret; + } + +#if MAC_AX_COEX_INIT_EN + ret = coex_mac_init(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] update coex setting %d\n", ret); + return ret; + } +#endif + + ret = is_qta_dbcc(adapter, info->qta_mode, &val8); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] is_qta_dbcc %d\n", ret); + return ret; + } + if (val8) { + ret = mac_ops->dbcc_enable(adapter, info, 1); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]dbcc_enable init %d\n", ret); + return ret; + } + } + + ret = mac_enable_imr(adapter, MAC_AX_BAND_0, MAC_AX_DMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] enable DMAC IMR %d\n", ret); + return ret; + } + + ret = mac_enable_imr(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR] enable CMAC0 IMR %d\n", ret); + return ret; + } + + ret = mac_err_imr_ctrl(adapter, MAC_AX_FUNC_EN); + if (ret) { + PLTFM_MSG_ERR("[ERR] enable err IMR %d\n", ret); + return ret; + } + + ret = set_host_rpr(adapter, info->rpr_cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]set host rpr %d\n", ret); + return ret; + } + + ret = set_l2_status(adapter); + if (ret) { + PLTFM_MSG_ERR("[ERR]%s %d\n", __func__, ret); + return ret; + } + + return MACSUCCESS; +} + +u32 mac_tx_mode_sel(struct mac_ax_adapter *adapter, + struct mac_ax_mac_tx_mode_sel *mode_sel) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32, ret; + + ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL); + if (ret != MACSUCCESS) + return ret; + + val32 = MAC_REG_R32(R_AX_SS_DL_RPT_CRTL); + val32 &= ~(B_AX_SS_TXOP_MODE_0 | B_AX_SS_TXOP_MODE_1 | + B_AX_SS_TXOP_MODE_2 | B_AX_SS_TXOP_MODE_3); + val32 |= (mode_sel->txop_rot_wmm0_en ? B_AX_SS_TXOP_MODE_0 : 0) | + (mode_sel->txop_rot_wmm1_en ? B_AX_SS_TXOP_MODE_1 : 0) | + (mode_sel->txop_rot_wmm2_en ? B_AX_SS_TXOP_MODE_2 : 0) | + (mode_sel->txop_rot_wmm3_en ? B_AX_SS_TXOP_MODE_3 : 0); + MAC_REG_W32(R_AX_SS_DL_RPT_CRTL, val32); + + return MACSUCCESS; +} + +u32 mac_two_nav_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_2nav_info *info) + +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 val32 = 0; + + val32 = MAC_REG_R32(R_AX_WMAC_NAV_CTL); + val32 |= ((info->plcp_upd_nav_en == 1 ? 1 : 0) << 17) | + ((info->tgr_fram_upd_nav_en == 1 ? 1 : 0) << 16) | + (info->nav_up << 8); + MAC_REG_W32(R_AX_WMAC_NAV_CTL, val32); + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/trxcfg.h b/phl/hal_g6/mac/mac_ax/trxcfg.h new file mode 100644 index 0000000..9c899dd --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/trxcfg.h @@ -0,0 +1,276 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TRXCFG_H_ +#define _MAC_AX_TRXCFG_H_ + +#include "../type.h" +#include "hw.h" +#include "init.h" +#include "role.h" +#include "cmac_tx.h" +#include "rx_filter.h" +#include "dle.h" +#include "hci_fc.h" +#include "mport.h" +#include "spatial_reuse.h" + +/*--------------------Define -------------------------------------------*/ +#define TRXCFG_WAIT_CNT 2000 +#define TRXCFG_WAIT_US 1 + +/* MPDU Processor Control */ +#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 +#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 +#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 + +/* RMAC timeout control */ +#define TRXCFG_RMAC_CCA_TO 32 +#define TRXCFG_RMAC_DATA_TO 15 + +#define S_AX_TXSC_20M_0 0 +#define S_AX_TXSC_20M_4 4 +#define S_AX_TXSC_40M_0 0 +#define S_AX_TXSC_40M_4 4 +#define S_AX_TXSC_80M_0 0 +#define S_AX_TXSC_80M_4 4 + +#define RRSR_OFDM_CCK_EN 3 + +/* TRXPTCL SIFS TIME*/ +#define WMAC_SPEC_SIFS_OFDM_52A 0x15 +#define WMAC_SPEC_SIFS_OFDM_52B 0x11 +#define WMAC_SPEC_SIFS_OFDM_52C 0x11 +#define WMAC_SPEC_SIFS_CCK 0xA + +/* SRAM fifo address */ +#define CMAC_TBL_BASE_ADDR 0x18840000 + +#define CMAC1_START_ADDR 0xE000 +#define CMAC1_END_ADDR 0xFFFF + +#if MAC_AX_ASIC_TEMP +#define R_AX_LTECOEX_CTRL 0x38 +#define R_AX_LTECOEX_CTRL_2 0x3C +#endif + +#define S_AX_CTS2S_TH_1K 4 +#define S_AX_CTS2S_TH_SEC_256B 1 + +#define S_AX_PTCL_TO_2MS 0x3F + +#define LBK_PLCP_DLY_DEF 0x28 +#define LBK_PLCP_DLY_FPGA 0x46 + +#define PLD_RLS_MAX_PG 127 +#define RX_MAX_LEN_UNIT 512 +/* if spec max len is not align to rx max len unit, add 1 unit */ +#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) + +#define SCH_PREBKF_24US 0x18 +#define SCH_PREBKF_16US 0x10 + +#define BCN_IFS_25US 0x19 +#define SIFS_MACTXEN_T1 0x47 + +#define SDIO_DRV_INFO_SIZE 2 + +#define DMA_MOD_PCIE_1B 0x0 +#define DMA_MOD_PCIE_4B 0x1 +#define DMA_MOD_USB 0x2 +#define DMA_MOD_SDIO 0x3 + +#define NAV_12MS 0xBC // (12ms, unit: 64us) + +#define FWD_TO_HOST 0 +#define FWD_TO_WLCPU 1 +#define FWD_TO_DATACPU 2 + +#define AMPDU_MAX_LEN_VHT_262K 0x3FF80 + +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +/*--------------------Define Struct-------------------------------------*/ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_enable_imr + * + * @param *adapter + * @param band + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_enable_imr(struct mac_ax_adapter *adapter, u8 band, + enum mac_ax_hwmod_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief check_mac_en + * + * @param *adapter + * @param band + * @param sel + * @return Please Place Description here. + * @retval u32 + */ +u32 check_mac_en(struct mac_ax_adapter *adapter, u8 band, + enum mac_ax_hwmod_sel sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_check_access + * + * @param *adapter + * @param offset + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_access(struct mac_ax_adapter *adapter, u32 offset); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief cmac_init + * + * @param *adapter + * @param *info + * @param band + * @return Please Place Description here. + * @retval u32 + */ +u32 cmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info, + enum mac_ax_band band); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_trx_init + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_trx_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_tx_mode_sel + * + * @param *adapter + * @param *mode_sel + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_tx_mode_sel(struct mac_ax_adapter *adapter, + struct mac_ax_mac_tx_mode_sel *mode_sel); +/** + * @} + * @} + */ + +/** + * @addtogroup Basic_TRX + * @{ + * @addtogroup TX_Config + * @{ + */ + +/** + * @brief mac_two_nav_cfg + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_two_nav_cfg(struct mac_ax_adapter *adapter, + struct mac_ax_2nav_info *info); +/** + * @} + * @} + + *//** + * @brief mac_sifs_chk_edcca_en + * + * @param *adapter + * @param *band + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_sifs_chk_cca_en(struct mac_ax_adapter *adapter, u8 band); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/twt.c b/phl/hal_g6/mac/mac_ax/twt.c new file mode 100644 index 0000000..1820605 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/twt.c @@ -0,0 +1,286 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "twt.h" + +u32 mac_twt_info_upd_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twt_para *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_twtinfo_upd *hdr; + u32 ret = MACSUCCESS; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_twtinfo_upd *) + h2cb_put(h2cb, sizeof(struct fwcmd_twtinfo_upd)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + /* port 4 not support */ + if (info->port >= MAC_AX_PORT_4) { + PLTFM_MSG_ERR("[ERR] twt info upd h2c port %d\n", info->port); + return MACFUNCINPUT; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->nego_tp, + FWCMD_H2C_TWTINFO_UPD_NEGOTYPE) | + SET_WORD(info->act, FWCMD_H2C_TWTINFO_UPD_ACT) | + (info->trig ? FWCMD_H2C_TWTINFO_UPD_TRIGGER : 0) | + (info->flow_tp ? + FWCMD_H2C_TWTINFO_UPD_FLOWTYPE : 0) | + (info->impt ? FWCMD_H2C_TWTINFO_UPD_IMPT : 0) | + (info->wake_unit ? + FWCMD_H2C_TWTINFO_UPD_WAKEDURUNIT : 0) | + (info->rsp_pm ? FWCMD_H2C_TWTINFO_UPD_RSPPM : 0) | + (info->proct ? FWCMD_H2C_TWTINFO_UPD_PROT : 0) | + SET_WORD(info->flow_id, + FWCMD_H2C_TWTINFO_UPD_FLOWID) | + SET_WORD(info->id, FWCMD_H2C_TWTINFO_UPD_ID) | + (info->band ? FWCMD_H2C_TWTINFO_UPD_BAND : 0) | + SET_WORD(info->port, FWCMD_H2C_TWTINFO_UPD_PORT)); + + hdr->dword1 = + cpu_to_le32(SET_WORD(info->wake_exp, + FWCMD_H2C_TWTINFO_UPD_WAKE_EXP) | + SET_WORD(info->wake_man, + FWCMD_H2C_TWTINFO_UPD_WAKE_MAN) | + SET_WORD(info->twtulfixmode, + FWCMD_H2C_TWTINFO_UPD_ULFIXMODE) | + SET_WORD(info->dur, + FWCMD_H2C_TWTINFO_UPD_DUR)); + + hdr->dword2 = + cpu_to_le32(SET_WORD(info->trgt_l, + FWCMD_H2C_TWTINFO_UPD_TGT_L)); + + hdr->dword3 = + cpu_to_le32(SET_WORD(info->trgt_h, + FWCMD_H2C_TWTINFO_UPD_TGT_H)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_TWT, + FWCMD_H2C_FUNC_TWTINFO_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_twt_act_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twtact_para *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_twt_stansp_upd *hdr; + u32 ret = MACSUCCESS; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_twt_stansp_upd *) + h2cb_put(h2cb, sizeof(struct fwcmd_twt_stansp_upd)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->macid, + FWCMD_H2C_TWT_STANSP_UPD_MACID) | + SET_WORD(info->id, + FWCMD_H2C_TWT_STANSP_UPD_ID) | + SET_WORD(info->act, + FWCMD_H2C_TWT_STANSP_UPD_ACT)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_TWT, + FWCMD_H2C_FUNC_TWT_STANSP_UPD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_twt_staanno_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twtanno_para *info) +{ + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_twt_announce_upd *hdr; + u32 ret = MACSUCCESS; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + hdr = (struct fwcmd_twt_announce_upd *)h2cb_put(h2cb, + sizeof(struct fwcmd_twt_announce_upd)); + if (!hdr) { + ret = MACNOBUF; + goto fail; + } + + hdr->dword0 = + cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_TWT, + FWCMD_H2C_FUNC_TWT_ANNOUNCE_UPD, + 1, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + h2c_end_flow(adapter); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +void mac_twt_wait_anno(struct mac_ax_adapter *adapter, + u8 *c2h_content, u8 *upd_addr) +{ + u32 plat_c2h_content = *(u32 *)(c2h_content); + struct mac_ax_twtanno_c2hpara *para = + (struct mac_ax_twtanno_c2hpara *)upd_addr; + + para->wait_case = GET_FIELD(plat_c2h_content, + FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE); + para->macid0 = GET_FIELD(plat_c2h_content, + FWCMD_C2H_WAIT_ANNOUNCE_MACID0); + para->macid1 = GET_FIELD(plat_c2h_content, + FWCMD_C2H_WAIT_ANNOUNCE_MACID1); + para->macid2 = GET_FIELD(plat_c2h_content, + FWCMD_C2H_WAIT_ANNOUNCE_MACID2); +} + +void mac_get_tsf(struct mac_ax_adapter *adapter, + struct mac_ax_port_tsf *tsf) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + u32 reg_l = 0; + u32 reg_h = 0; + + switch (tsf->port) { + case 0: + reg_h = R_AX_TSFTR_HIGH_P0; + reg_l = R_AX_TSFTR_LOW_P0; + break; + case 1: + reg_h = R_AX_TSFTR_HIGH_P1; + reg_l = R_AX_TSFTR_LOW_P1; + break; + case 2: + reg_h = R_AX_TSFTR_HIGH_P2; + reg_l = R_AX_TSFTR_LOW_P2; + break; + case 3: + reg_h = R_AX_TSFTR_HIGH_P3; + reg_l = R_AX_TSFTR_LOW_P3; + break; + default: + reg_h = R_AX_TSFTR_HIGH_P0; + reg_l = R_AX_TSFTR_LOW_P0; + break; + } + + tsf->tsf_h = MAC_REG_R32(reg_h); + tsf->tsf_l = MAC_REG_R32(reg_l); +} + diff --git a/phl/hal_g6/mac/mac_ax/twt.h b/phl/hal_g6/mac/mac_ax/twt.h new file mode 100644 index 0000000..4df9db6 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/twt.h @@ -0,0 +1,134 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TWT_H_ +#define _MAC_AX_TWT_H_ + +#include "../type.h" +#include "fwcmd.h" + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup TWT + * @{ + */ + +/** + * @brief mac_twt_info_upd_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_twt_info_upd_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twt_para *info); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup TWT + * @{ + */ + +/** + * @brief mac_twt_act_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_twt_act_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twtact_para *info); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup TWT + * @{ + */ + +/** + * @brief mac_twt_staanno_h2c + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_twt_staanno_h2c(struct mac_ax_adapter *adapter, + struct mac_ax_twtanno_para *info); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup TWT + * @{ + */ + +/** + * @brief mac_twt_wait_anno + * + * @param *adapter + * @param *c2h_content + * @param *upd_addr + * @return Please Place Description here. + * @retval void + */ +void mac_twt_wait_anno(struct mac_ax_adapter *adapter, + u8 *c2h_content, u8 *upd_addr); +/** + * @} + * @} + */ + +/** + * @addtogroup PowerSaving + * @{ + * @addtogroup TWT + * @{ + */ + +/** + * @brief mac_get_tsf + * + * @param *adapter + * @param *tsf + * @return Please Place Description here. + * @retval void + */ +void mac_get_tsf(struct mac_ax_adapter *adapter, + struct mac_ax_port_tsf *tsf); +/** + * @} + * @} + */ + +#endif diff --git a/phl/hal_g6/mac/mac_ax/wowlan.c b/phl/hal_g6/mac/mac_ax/wowlan.c new file mode 100644 index 0000000..915f695 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/wowlan.c @@ -0,0 +1,1775 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "wowlan.h" + +static u32 wow_bk_status[4] = {0}; +static u32 tgt_ind_orig; +static u32 frm_tgt_ind_orig; +static u32 wol_pattern_orig; +static u32 wol_uc_orig; +static u32 wol_magic_orig; +static u8 nlo_enable_record; + +static u32 send_h2c_keep_alive(struct mac_ax_adapter *adapter, + struct keep_alive *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_keep_alive *fwcmd_kalive; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_keep_alive)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_kalive = (struct fwcmd_keep_alive *)buf; + fwcmd_kalive->dword0 = + cpu_to_le32((parm->keepalive_en ? + FWCMD_H2C_KEEP_ALIVE_KEEPALIVE_EN : 0) | + SET_WORD(parm->packet_id, FWCMD_H2C_KEEP_ALIVE_PACKET_ID) | + SET_WORD(parm->period, FWCMD_H2C_KEEP_ALIVE_PERIOD) | + SET_WORD(parm->mac_id, FWCMD_H2C_KEEP_ALIVE_MAC_ID)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_KEEP_ALIVE, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_disconnect_detect(struct mac_ax_adapter *adapter, + struct disconnect_detect *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_disconnect_detect *fwcmd_disconnect_det; + u32 ret = 0; + u32 tmp; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_disconnect_detect)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_disconnect_det = (struct fwcmd_disconnect_detect *)buf; + fwcmd_disconnect_det->dword0 = + cpu_to_le32((parm->disconnect_detect_en ? + FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_DETECT_EN : 0) | + (parm->tryok_bcnfail_count_en ? + FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN : 0) | + (parm->disconnect_en ? FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_EN : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_DISCONNECT_DETECT_MAC_ID) | + SET_WORD(parm->check_period, FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD) | + SET_WORD(parm->try_pkt_count, + FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT)); + + tmp = SET_WORD(parm->tryok_bcnfail_count_limit, + FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT); + fwcmd_disconnect_det->dword1 = cpu_to_le32(tmp); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_DISCONNECT_DETECT, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_wow_global(struct mac_ax_adapter *adapter, + struct wow_global *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_wow_global *fwcmd_wow_glo; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_wow_global) + + sizeof(struct mac_ax_remotectrl_info_parm_) - 4); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_wow_glo = (struct fwcmd_wow_global *)buf; + fwcmd_wow_glo->dword0 = + cpu_to_le32((parm->wow_en ? FWCMD_H2C_WOW_GLOBAL_WOW_EN : 0) | + (parm->drop_all_pkt ? FWCMD_H2C_WOW_GLOBAL_DROP_ALL_PKT : 0) | + (parm->rx_parse_after_wake ? + FWCMD_H2C_WOW_GLOBAL_RX_PARSE_AFTER_WAKE : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_WOW_GLOBAL_MAC_ID) | + SET_WORD(parm->pairwise_sec_algo, + FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO) | + SET_WORD(parm->group_sec_algo, + FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO)); + + //fwcmd_wow_glo->dword1 = + // cpu_to_le32(parm->remotectrl_info_content); + PLTFM_MEMCPY(&fwcmd_wow_glo->dword1, &parm->remotectrl_info_content, + sizeof(struct mac_ax_remotectrl_info_parm_)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_WOW_GLOBAL, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_gtk_ofld(struct mac_ax_adapter *adapter, + struct gtk_ofld *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_gtk_ofld *fwcmd_gtk_ofl; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_gtk_ofld) + + sizeof(struct mac_ax_gtk_info_parm_) - 4); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_gtk_ofl = (struct fwcmd_gtk_ofld *)buf; + fwcmd_gtk_ofl->dword0 = + cpu_to_le32((parm->gtk_en ? FWCMD_H2C_GTK_OFLD_GTK_EN : 0) | + (parm->tkip_en ? FWCMD_H2C_GTK_OFLD_TKIP_EN : 0) | + (parm->ieee80211w_en ? FWCMD_H2C_GTK_OFLD_IEEE80211W_EN : 0) | + (parm->pairwise_wakeup ? + FWCMD_H2C_GTK_OFLD_PAIRWISE_WAKEUP : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_GTK_OFLD_MAC_ID) | + SET_WORD(parm->gtk_rsp_id, FWCMD_H2C_GTK_OFLD_GTK_RSP_ID)); + + fwcmd_gtk_ofl->dword1 = + cpu_to_le32(SET_WORD(parm->pmf_sa_query_id, FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID) | + SET_WORD(parm->bip_sec_algo, FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO) | + SET_WORD(parm->algo_akm_suit, FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT)); + + PLTFM_MEMCPY(&fwcmd_gtk_ofl->dword2, &parm->gtk_info_content, + sizeof(struct mac_ax_gtk_info_parm_)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_GTK_OFLD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_arp_ofld(struct mac_ax_adapter *adapter, + struct arp_ofld *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_arp_ofld *fwcmd_arp_ofl; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_arp_ofld)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_arp_ofl = (struct fwcmd_arp_ofld *)buf; + fwcmd_arp_ofl->dword0 = + cpu_to_le32((parm->arp_en ? FWCMD_H2C_ARP_OFLD_ARP_EN : 0) | + (parm->arp_action ? FWCMD_H2C_ARP_OFLD_ARP_ACTION : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_ARP_OFLD_MAC_ID) | + SET_WORD(parm->arp_rsp_id, FWCMD_H2C_ARP_OFLD_ARP_RSP_ID)); + + fwcmd_arp_ofl->dword1 = + cpu_to_le32(parm->arp_info_content); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_ARP_OFLD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_ndp_ofld(struct mac_ax_adapter *adapter, + struct ndp_ofld *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_ndp_ofld *fwcmd_ndp_ofl; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_ndp_ofld) + 2 * + sizeof(struct mac_ax_ndp_info_parm_) - 4); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_ndp_ofl = (struct fwcmd_ndp_ofld *)buf; + fwcmd_ndp_ofl->dword0 = + cpu_to_le32((parm->ndp_en ? FWCMD_H2C_NDP_OFLD_NDP_EN : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_NDP_OFLD_MAC_ID) | + SET_WORD(parm->na_id, FWCMD_H2C_NDP_OFLD_NA_ID)); + + PLTFM_MEMCPY(&fwcmd_ndp_ofl->dword1, &parm->ndp_info_content, 2 * + sizeof(struct mac_ax_ndp_info_parm_)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_NDP_OFLD, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_realwow(struct mac_ax_adapter *adapter, + struct realwow *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_realwow *fwcmd_realw; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_realwow) + + sizeof(struct mac_ax_realwowv2_info_parm_) - 4); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_realw = (struct fwcmd_realwow *)buf; + fwcmd_realw->dword0 = + cpu_to_le32((parm->realwow_en ? FWCMD_H2C_REALWOW_REALWOW_EN : 0) | + (parm->auto_wakeup ? FWCMD_H2C_REALWOW_AUTO_WAKEUP : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_REALWOW_MAC_ID)); + + fwcmd_realw->dword1 = + cpu_to_le32(SET_WORD(parm->keepalive_id, + FWCMD_H2C_REALWOW_KEEPALIVE_ID) | + SET_WORD(parm->wakeup_pattern_id, FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID) | + SET_WORD(parm->ack_pattern_id, FWCMD_H2C_REALWOW_ACK_PATTERN_ID)); + + fwcmd_realw->dword2 = + cpu_to_le32(parm->realwow_info_content); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_REALWOW, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_nlo(struct mac_ax_adapter *adapter, + struct nlo *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u32 ret = 0; + u32 *h2cb_u32; + u32 *nlo_parm_u32; + u8 sh; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_nlo) + + sizeof(struct mac_ax_nlo_networklist_parm_) - 4); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + nlo_parm_u32 = &parm->nlo_networklistinfo_content; + h2cb_u32 = (u32 *)buf; + *h2cb_u32 = cpu_to_le32((parm->nlo_en ? FWCMD_H2C_NLO_NLO_EN : 0) | + (parm->nlo_32k_en ? FWCMD_H2C_NLO_NLO_32K_EN : 0) | + (parm->ignore_cipher_type ? FWCMD_H2C_NLO_IGNORE_CIPHER_TYPE : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_NLO_MAC_ID)); + h2cb_u32++; + + *h2cb_u32 = cpu_to_le32(*nlo_parm_u32); + h2cb_u32++; + nlo_parm_u32 = parm->nlo_networklistinfo_more; + + for (sh = 0; sh < (sizeof(struct mac_ax_nlo_networklist_parm_) / 4 - 1); sh++) + *(h2cb_u32 + sh) = cpu_to_le32(*(nlo_parm_u32 + sh)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_NLO, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_wakeup_ctrl(struct mac_ax_adapter *adapter, + struct wakeup_ctrl *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_wakeup_ctrl *fwcmd_wakeup_ctr; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_wakeup_ctrl)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_wakeup_ctr = (struct fwcmd_wakeup_ctrl *)buf; + fwcmd_wakeup_ctr->dword0 = + cpu_to_le32((parm->pattern_match_en ? + FWCMD_H2C_WAKEUP_CTRL_PATTERN_MATCH_EN : 0) | + (parm->magic_en ? FWCMD_H2C_WAKEUP_CTRL_MAGIC_EN : 0) | + (parm->hw_unicast_en ? FWCMD_H2C_WAKEUP_CTRL_HW_UNICAST_EN : 0) | + (parm->fw_unicast_en ? FWCMD_H2C_WAKEUP_CTRL_FW_UNICAST_EN : 0) | + (parm->deauth_wakeup ? FWCMD_H2C_WAKEUP_CTRL_DEAUTH_WAKEUP : 0) | + (parm->rekey_wakeup ? FWCMD_H2C_WAKEUP_CTRL_REKEY_WAKEUP : 0) | + (parm->eap_wakeup ? FWCMD_H2C_WAKEUP_CTRL_EAP_WAKEUP : 0) | + (parm->all_data_wakeup ? FWCMD_H2C_WAKEUP_CTRL_ALL_DATA_WAKEUP : 0) | + SET_WORD(parm->mac_id, FWCMD_H2C_WAKEUP_CTRL_MAC_ID)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_WAKEUP_CTRL, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_negative_pattern(struct mac_ax_adapter *adapter, + struct negative_pattern *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_negative_pattern *fwcmd_negative_patter; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_negative_pattern)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_negative_patter = (struct fwcmd_negative_pattern *)buf; + + fwcmd_negative_patter->dword0 = + cpu_to_le32((parm->negative_pattern_en ? + FWCMD_H2C_NEGATIVE_PATTERN_NEGATIVE_PATTERN_EN : 0) | + SET_WORD(parm->pattern_count, + FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT) | + SET_WORD(parm->mac_id, FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID)); + + fwcmd_negative_patter->dword1 = + cpu_to_le32(parm->pattern_content); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_NEGATIVE_PATTERN, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_cfg_dev2hst_gpio(struct mac_ax_adapter *adapter, + struct mac_ax_dev2hst_gpio_info *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_dev2hst_gpio *fwcmd_dev2hst_gpi; + u32 ret = 0; + + if (parm->gpio_output_input == MAC_AX_DEV2HST_GPIO_INPUT && + parm->toggle_pulse == MAC_AX_DEV2HST_PULSE) { + PLTFM_MSG_ERR("pulse mode not supported under input mode"); + return MACNOITEM; + } + if (parm->gpio_num > MAC_AX_GPIO15) { + PLTFM_MSG_ERR("gpio num > 15"); + return MACNOITEM; + } + if (parm->toggle_pulse == MAC_AX_DEV2HST_PULSE) { + if (parm->gpio_pulse_dura == 0) { + PLTFM_MSG_ERR("gpio pulse duration cant be 0"); + return MACNOITEM; + } + if (parm->gpio_pulse_period <= parm->gpio_pulse_dura) { + PLTFM_MSG_ERR("gpio pulse period can less than duration"); + return MACNOITEM; + } + if (!parm->gpio_pulse_nonstop && parm->gpio_pulse_count == 0) { + PLTFM_MSG_ERR("gpio pulse count cant be 0"); + return MACNOITEM; + } + } + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_dev2hst_gpio)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + fwcmd_dev2hst_gpi = (struct fwcmd_dev2hst_gpio *)buf; + fwcmd_dev2hst_gpi->dword0 = + cpu_to_le32((parm->dev2hst_gpio_en ? FWCMD_H2C_DEV2HST_GPIO_DEV2HST_GPIO_EN : 0) | + (parm->disable_inband ? FWCMD_H2C_DEV2HST_GPIO_DISABLE_INBAND : 0) | + (parm->gpio_output_input ? FWCMD_H2C_DEV2HST_GPIO_GPIO_OUTPUT_INPUT : 0) | + (parm->gpio_active ? FWCMD_H2C_DEV2HST_GPIO_GPIO_ACTIVE : 0) | + (parm->toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_TOGGLE_PULSE : 0) | + (parm->data_pin_wakeup ? FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP : 0) | + (parm->data_pin_wakeup ? FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP : 0) | + (parm->gpio_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_NONSTOP : 0) | + (parm->gpio_time_unit ? FWCMD_H2C_DEV2HST_GPIO_GPIO_TIME_UNIT : 0) | + SET_WORD(parm->gpio_num, FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM) | + SET_WORD(parm->gpio_pulse_dura, FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION) | + SET_WORD(parm->gpio_pulse_period, FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD)); + + fwcmd_dev2hst_gpi->dword1 = + cpu_to_le32(SET_WORD(parm->gpio_pulse_count, + FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT)); + + fwcmd_dev2hst_gpi->dword2 = + cpu_to_le32(SET_WORD(parm->customer_id, + FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID)); + + fwcmd_dev2hst_gpi->dword3 = + cpu_to_le32((parm->rsn_a_en ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_EN : 0) | + (parm->rsn_a_toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_TOGGLE_PULSE : 0) | + (parm->rsn_a_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_NONSTOP : 0) | + (parm->rsn_a_time_unit ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_TIME_UNIT : 0)); + + fwcmd_dev2hst_gpi->dword4 = + cpu_to_le32(SET_WORD(parm->rsn_a, FWCMD_H2C_DEV2HST_GPIO_RSN_A) | + SET_WORD(parm->rsn_a_pulse_duration, + FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION) | + SET_WORD(parm->rsn_a_pulse_period, FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD) | + SET_WORD(parm->rsn_a_pulse_count, FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT)); + + fwcmd_dev2hst_gpi->dword5 = + cpu_to_le32((parm->rsn_b_en ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_EN : 0) | + (parm->rsn_b_toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_TOGGLE_PULSE : 0) | + (parm->rsn_b_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_NONSTOP : 0) | + (parm->rsn_b_time_unit ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_TIME_UNIT : 0)); + + fwcmd_dev2hst_gpi->dword6 = + cpu_to_le32(SET_WORD(parm->rsn_b, FWCMD_H2C_DEV2HST_GPIO_RSN_B) | + SET_WORD(parm->rsn_b_pulse_duration, + FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION) | + SET_WORD(parm->rsn_b_pulse_period, FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD) | + SET_WORD(parm->rsn_b_pulse_count, FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_DEV2HST_GPIO, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + PLTFM_MSG_TRACE("ok"); + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + return ret; +} + +static u32 send_h2c_uphy_ctrl(struct mac_ax_adapter *adapter, + struct uphy_ctrl *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_uphy_ctrl *fwcmd_uphy_ctr; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_uphy_ctrl)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_uphy_ctr = (struct fwcmd_uphy_ctrl *)buf; + fwcmd_uphy_ctr->dword0 = + cpu_to_le32((parm->disable_uphy ? + FWCMD_H2C_UPHY_CTRL_DISABLE_UPHY : 0) | + SET_WORD(parm->handshake_mode, FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE) | + (parm->rise_hst2dev_dis_uphy ? FWCMD_H2C_UPHY_CTRL_RISE_HST2DEV_DIS_UPHY + : 0) | + (parm->uphy_dis_delay_unit ? FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_UNIT + : 0) | + (parm->pdn_as_uphy_dis ? FWCMD_H2C_UPHY_CTRL_PDN_AS_UPHY_DIS : 0) | + (parm->pdn_to_enable_uphy ? FWCMD_H2C_UPHY_CTRL_PDN_TO_ENABLE_UPHY + : 0) | + SET_WORD(parm->hst2dev_gpio_num, FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM) | + SET_WORD(parm->uphy_dis_delay_count, + FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_UPHY_CTRL, + 0, + 1); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +static u32 send_h2c_wowcam_upd(struct mac_ax_adapter *adapter, + struct wowcam_upd *parm) +{ + u8 *buf; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + struct fwcmd_wow_cam_upd *fwcmd_wowcam_upd; + u32 ret = 0; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD); + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_wow_cam_upd)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_wowcam_upd = (struct fwcmd_wow_cam_upd *)buf; + fwcmd_wowcam_upd->dword0 = + cpu_to_le32((parm->r_w ? FWCMD_H2C_WOW_CAM_UPD_R_W : 0) | + SET_WORD(parm->idx, FWCMD_H2C_WOW_CAM_UPD_IDX)); + + fwcmd_wowcam_upd->dword1 = + cpu_to_le32(parm->wkfm1); + + fwcmd_wowcam_upd->dword2 = + cpu_to_le32(parm->wkfm2); + + fwcmd_wowcam_upd->dword3 = + cpu_to_le32(parm->wkfm3); + + fwcmd_wowcam_upd->dword4 = + cpu_to_le32(parm->wkfm4); + + fwcmd_wowcam_upd->dword5 = + cpu_to_le32(SET_WORD(parm->crc, FWCMD_H2C_WOW_CAM_UPD_CRC) | + (parm->negative_pattern_match ? FWCMD_H2C_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH : 0) | + (parm->skip_mac_hdr ? FWCMD_H2C_WOW_CAM_UPD_SKIP_MAC_HDR : 0) | + (parm->uc ? FWCMD_H2C_WOW_CAM_UPD_UC : 0) | + (parm->mc ? FWCMD_H2C_WOW_CAM_UPD_MC : 0) | + (parm->bc ? FWCMD_H2C_WOW_CAM_UPD_BC : 0) | + (parm->valid ? FWCMD_H2C_WOW_CAM_UPD_VALID : 0)); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, + FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, + FWCMD_H2C_FUNC_WOW_CAM_UPD, + 0, + 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + + #if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); + #else + ret = PLTFM_TX(h2cb->data, h2cb->len); + #endif + if (ret) + goto fail; + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 mac_cfg_wow_wake(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_wow_wake_info *info, + struct mac_ax_remotectrl_info_parm_ *content) +{ + u32 ret = 0; + struct wow_global parm1; + struct wakeup_ctrl parm2; + struct mac_role_tbl *role; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + parm2.pattern_match_en = info->pattern_match_en; + parm2.magic_en = info->magic_en; + parm2.hw_unicast_en = info->hw_unicast_en; + parm2.fw_unicast_en = info->fw_unicast_en; + parm2.deauth_wakeup = info->deauth_wakeup; + parm2.rekey_wakeup = info->rekey_wakeup; + parm2.eap_wakeup = info->eap_wakeup; + parm2.all_data_wakeup = info->all_data_wakeup; + parm2.mac_id = macid; + ret = send_h2c_wakeup_ctrl(adapter, &parm2); + if (ret) { + PLTFM_MSG_ERR("send h2c wakeup ctrl failed\n"); + return ret; + } + + parm1.wow_en = info->wow_en; + parm1.drop_all_pkt = info->drop_all_pkt; + parm1.rx_parse_after_wake = info->rx_parse_after_wake; + parm1.mac_id = macid; + parm1.pairwise_sec_algo = info->pairwise_sec_algo; + parm1.group_sec_algo = info->group_sec_algo; + //parm1.remotectrl_info_content = + //info->remotectrl_info_content; + if (content) + PLTFM_MEMCPY(&parm1.remotectrl_info_content, + content, + sizeof(struct mac_ax_remotectrl_info_parm_)); + + if (info->wow_en) { + role = mac_role_srch(adapter, macid); + if (role) { + tgt_ind_orig = role->info.tgt_ind; + frm_tgt_ind_orig = role->info.frm_tgt_ind; + wol_pattern_orig = role->info.wol_pattern; + wol_uc_orig = role->info.wol_uc; + wol_magic_orig = role->info.wol_magic; + wow_bk_status[(macid >> 5)] |= BIT(macid & 0x1F); + role->info.wol_pattern = (u8)parm2.pattern_match_en; + role->info.wol_uc = info->hw_unicast_en; + role->info.wol_magic = info->magic_en; + + ret = mac_change_role(adapter, &role->info); + if (ret) { + PLTFM_MSG_ERR("role change failed\n"); + return ret; + } + } else { + PLTFM_MSG_ERR("role search failed\n"); + return MACNOITEM; + } + } else { + if (wow_bk_status[(macid >> 5)] & BIT(macid & 0x1F)) { + //restore address cam + role = mac_role_srch(adapter, macid); + if (role) { + role->info.tgt_ind = (u8)tgt_ind_orig; + role->info.frm_tgt_ind = (u8)frm_tgt_ind_orig; + role->info.wol_pattern = (u8)wol_pattern_orig; + role->info.wol_uc = (u8)wol_uc_orig; + role->info.wol_magic = (u8)wol_magic_orig; + ret = mac_change_role(adapter, &role->info); + if (ret) { + PLTFM_MSG_ERR("role change failed\n"); + return ret; + } + } + wow_bk_status[(macid >> 5)] &= ~BIT(macid & 0x1F); + } else { + PLTFM_MSG_ERR("role search failed\n"); + return MACNOITEM; + } + } + + ret = send_h2c_wow_global(adapter, &parm1); + if (ret) + PLTFM_MSG_ERR("set wow global failed\n"); + + return ret; +} + +u32 mac_cfg_disconnect_det(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_disconnect_det_info *info) +{ + u32 ret = 0; + struct disconnect_detect parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + parm.disconnect_detect_en = info->disconnect_detect_en; + parm.tryok_bcnfail_count_en = + info->tryok_bcnfail_count_en; + parm.disconnect_en = info->disconnect_en; + parm.mac_id = macid; + parm.check_period = info->check_period; + parm.try_pkt_count = info->try_pkt_count; + parm.tryok_bcnfail_count_limit = + info->tryok_bcnfail_count_limit; + + ret = send_h2c_disconnect_detect(adapter, &parm); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_cfg_keep_alive(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_keep_alive_info *info) +{ + u32 ret = 0; + struct keep_alive parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + parm.keepalive_en = info->keepalive_en; + parm.packet_id = info->packet_id; + parm.period = info->period; + parm.mac_id = macid; + + ret = send_h2c_keep_alive(adapter, &parm); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_cfg_gtk_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_gtk_ofld_info *info, + struct mac_ax_gtk_info_parm_ *content) +{ + u32 ret = 0; + struct gtk_ofld parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + parm.gtk_en = info->gtk_en; + parm.tkip_en = info->tkip_en; + parm.ieee80211w_en = info->ieee80211w_en; + parm.pairwise_wakeup = info->pairwise_wakeup; + parm.mac_id = macid; + parm.gtk_rsp_id = info->gtk_rsp_id; + parm.pmf_sa_query_id = info->pmf_sa_query_id; + parm.bip_sec_algo = info->bip_sec_algo; + parm.algo_akm_suit = info->algo_akm_suit; + + if (content) + PLTFM_MEMCPY(&parm.gtk_info_content, content, + sizeof(struct mac_ax_gtk_info_parm_)); + + ret = send_h2c_gtk_ofld(adapter, &parm); + if (ret) + return ret; + return MACSUCCESS; +} + +u32 mac_cfg_arp_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_arp_ofld_info *info, + void *parp_info_content) +{ + u32 ret = 0; + struct arp_ofld parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MEMSET(&parm, 0, sizeof(struct arp_ofld)); + parm.arp_en = info->arp_en; + parm.arp_action = info->arp_action; + parm.mac_id = macid; + parm.arp_rsp_id = info->arp_rsp_id; + + //if (parp_info_content) + // PLTFM_MEMCPY(&parm.ndp_info_content, parp_info_content, + // sizeof(struct _arp_info_parm_) * 2); + + ret = send_h2c_arp_ofld(adapter, &parm); + if (ret) + return ret; + return MACSUCCESS; +} + +u32 mac_cfg_ndp_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_ndp_ofld_info *info, + struct mac_ax_ndp_info_parm_ *content) +{ + u32 ret = 0; + struct ndp_ofld parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MEMSET(&parm, 0, sizeof(struct ndp_ofld)); + parm.ndp_en = info->ndp_en; + parm.na_id = info->na_id; + parm.mac_id = macid; + + if (content) + PLTFM_MEMCPY(&parm.ndp_info_content, content, + sizeof(struct mac_ax_ndp_info_parm_) * 2); + + ret = send_h2c_ndp_ofld(adapter, &parm); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 mac_cfg_realwow(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_realwow_info *info, + struct mac_ax_realwowv2_info_parm_ *content) +{ + u32 ret = 0; + struct realwow parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MEMSET(&parm, 0, sizeof(struct realwow)); + parm.realwow_en = info->realwow_en; + parm.auto_wakeup = info->auto_wakeup; + parm.mac_id = macid; + parm.keepalive_id = info->keepalive_id; + parm.wakeup_pattern_id = info->wakeup_pattern_id; + parm.ack_pattern_id = info->ack_pattern_id; + if (content) + PLTFM_MEMCPY(&parm.realwow_info_content, content, + sizeof(struct mac_ax_realwowv2_info_parm_)); + + ret = send_h2c_realwow(adapter, &parm); + if (ret) + return ret; + return MACSUCCESS; +} + +u32 mac_cfg_nlo(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_nlo_info *info, + struct mac_ax_nlo_networklist_parm_ *content) +{ + u32 ret = 0; + struct nlo parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MEMSET(&parm, 0, sizeof(struct nlo)); + parm.nlo_en = info->nlo_en; + parm.nlo_32k_en = info->nlo_32k_en; + parm.ignore_cipher_type = info->ignore_cipher_type; + parm.mac_id = macid; + + if (content) + PLTFM_MEMCPY(&parm.nlo_networklistinfo_content, + content, + sizeof(struct mac_ax_nlo_networklist_parm_)); + + ret = send_h2c_nlo(adapter, &parm); + if (ret) + return ret; + if (info->nlo_en) + nlo_enable_record = 1; + return MACSUCCESS; +} + +u32 mac_cfg_uphy_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_uphy_ctrl_info *info) +{ + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + return MACSUCCESS; +} + +u32 mac_cfg_wowcam_upd(struct mac_ax_adapter *adapter, + struct mac_ax_wowcam_upd_info *info) +{ + u32 ret = 0; + struct wowcam_upd parm; + + if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) + return MACNOFW; + + PLTFM_MEMSET(&parm, 0, sizeof(struct wowcam_upd)); + parm.r_w = info->r_w; + parm.idx = info->idx; + parm.wkfm1 = info->wkfm1; + parm.wkfm2 = info->wkfm2; + parm.wkfm3 = info->wkfm3; + parm.wkfm4 = info->wkfm4; + parm.crc = info->crc; + parm.negative_pattern_match = info->negative_pattern_match; + parm.skip_mac_hdr = info->skip_mac_hdr; + parm.uc = info->uc; + parm.mc = info->mc; + parm.bc = info->bc; + parm.valid = info->valid; + + ret = send_h2c_wowcam_upd(adapter, &parm); + if (ret) + return ret; + + return MACSUCCESS; +} + +u32 get_wake_reason(struct mac_ax_adapter *adapter, u8 *wowlan_wake_reason) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) || + is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) + *wowlan_wake_reason = MAC_REG_R8(R_AX_C2HREG_DATA3_V1 + 3); + else + *wowlan_wake_reason = MAC_REG_R8(R_AX_C2HREG_DATA3 + 3); + + return MACSUCCESS; +} + +u32 mac_get_wow_wake_rsn(struct mac_ax_adapter *adapter, u8 *wake_rsn, + u8 *reset) +{ + u32 ret = MACSUCCESS; + + ret = get_wake_reason(adapter, wake_rsn); + if (ret != MACSUCCESS) + return ret; + + switch (*wake_rsn) { + case MAC_AX_WOW_DMAC_ERROR_OCCURRED: + case MAC_AX_WOW_EXCEPTION_OCCURRED: + case MAC_AX_WOW_L0_TO_L1_ERROR_OCCURRED: + case MAC_AX_WOW_ASSERT_OCCURRED: + case MAC_AX_WOW_L2_ERROR_OCCURRED: + case MAC_AX_WOW_WDT_TIMEOUT_WAKE: + *reset = 1; + break; + default: + *reset = 0; + break; + } + + return MACSUCCESS; +} + +u32 mac_cfg_wow_sleep(struct mac_ax_adapter *adapter, + u8 sleep) +{ + u32 ret; + u32 val32; + u8 dbg_page; + struct mac_ax_phy_rpt_cfg cfg; + struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter); + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + PLTFM_MEMSET(&cfg, 0, sizeof(struct mac_ax_phy_rpt_cfg)); +#if MAC_AX_FW_REG_OFLD + if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) { + if (sleep) { + ret = _patch_redu_rx_qta(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]patch reduce rx qta %d\n", ret); + return ret; + } + + cfg.type = MAC_AX_PPDU_STATUS; + cfg.en = 0; + ret = mac_ops->cfg_phy_rpt(adapter, &cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret); + return ret; + } + + ret = MAC_REG_W_OFLD(R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP, 1, 0); + if (ret) + return ret; + if (nlo_enable_record == 0) { + ret = MAC_REG_W_OFLD(R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE, 0, 0); + } else { + ret = MAC_REG_W_OFLD(R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE, 1, 0); + PLTFM_MSG_TRACE("Enable sniffer mode since nlo enable"); + nlo_enable_record = 0; + } + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD0, 0x00000000, 0); + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD1, 0x00000000, 0); + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_TF_FWD, 0x00000000, 0); + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_HW_RPT_FWD, 0x00000000, 1); + if (ret) + return ret; + } else { + ret = _patch_restr_rx_qta(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]patch resume rx qta %d\n", ret); + return ret; + } + + ret = MAC_REG_W_OFLD(R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP, 0, 0); + if (ret) + return ret; + ret = MAC_REG_W_OFLD(R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE, 1, 0); + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD, 0); + if (ret) + return ret; + ret = MAC_REG_W32_OFLD(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD, 1); + if (ret) + return ret; + + cfg.type = MAC_AX_PPDU_STATUS; + cfg.en = 1; + ret = mac_ops->cfg_phy_rpt(adapter, &cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret); + return ret; + } + } + return MACSUCCESS; + } +#endif + if (sleep) { + ret = _patch_redu_rx_qta(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]patch reduce rx qta %d\n", ret); + return ret; + } + val32 = MAC_REG_R32(R_AX_RX_FUNCTION_STOP); + val32 |= B_AX_HDR_RX_STOP; + MAC_REG_W32(R_AX_RX_FUNCTION_STOP, val32); + + if (nlo_enable_record == 0) { + val32 = MAC_REG_R32(R_AX_RX_FLTR_OPT); + val32 &= ~B_AX_SNIFFER_MODE; + MAC_REG_W32(R_AX_RX_FLTR_OPT, val32); + } else { + val32 = MAC_REG_R32(R_AX_RX_FLTR_OPT); + val32 |= B_AX_SNIFFER_MODE; + MAC_REG_W32(R_AX_RX_FLTR_OPT, val32); + PLTFM_MSG_TRACE("enable sniffer for nlo\n"); + nlo_enable_record = 0; + } + + cfg.type = MAC_AX_PPDU_STATUS; + cfg.en = 0; + ret = mac_ops->cfg_phy_rpt(adapter, &cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret); + return ret; + } + + MAC_REG_W32(R_AX_ACTION_FWD0, 0x00000000); + MAC_REG_W32(R_AX_ACTION_FWD1, 0x00000000); + MAC_REG_W32(R_AX_TF_FWD, 0x00000000); + MAC_REG_W32(R_AX_HW_RPT_FWD, 0x00000000); + } else { + ret = _patch_restr_rx_qta(adapter); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]patch resume rx qta %d\n", ret); + return ret; + } + val32 = MAC_REG_R32(R_AX_RX_FUNCTION_STOP); + val32 &= ~B_AX_HDR_RX_STOP; + MAC_REG_W32(R_AX_RX_FUNCTION_STOP, val32); + val32 = MAC_REG_R32(R_AX_RX_FLTR_OPT); + MAC_REG_W32(R_AX_RX_FLTR_OPT, val32); + + cfg.type = MAC_AX_PPDU_STATUS; + cfg.en = 1; + ret = mac_ops->cfg_phy_rpt(adapter, &cfg); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret); + return ret; + } + + MAC_REG_W32(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); + MAC_REG_W32(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); + + PLTFM_MSG_ERR("[wow] Start to dump PLE debug pages\n"); + for (dbg_page = 0; dbg_page < 4; dbg_page++) + mac_ops->dump_ple_dbg_page(adapter, dbg_page); + } + + return MACSUCCESS; +} + +u32 mac_get_wow_fw_status(struct mac_ax_adapter *adapter, u8 *status, + u8 func_en) +{ + struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter); + + if (func_en) + func_en = 1; + + *status = !!((MAC_REG_R8(R_AX_WOW_CTRL) & B_AX_WOW_WOWEN)); + + if (func_en == *status) + *status = 1; + else + *status = 0; + + return MACSUCCESS; +} + +u32 _mac_request_aoac_report_rx_rdy(struct mac_ax_adapter *adapter) +{ + u32 ret; + #if MAC_AX_PHL_H2C + struct rtw_h2c_pkt *h2cb; + #else + struct h2c_buf *h2cb; + #endif + u8 *buf; + struct fwcmd_aoac_report_req *fwcmd_aoac_rpt_req; + + h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA); + + if (!h2cb) + return MACNPTR; + + buf = h2cb_put(h2cb, sizeof(struct fwcmd_aoac_report_req)); + if (!buf) { + ret = MACNOBUF; + goto fail; + } + + fwcmd_aoac_rpt_req = (struct fwcmd_aoac_report_req *)buf; + fwcmd_aoac_rpt_req->dword0 = + cpu_to_le32(FWCMD_H2C_AOAC_REPORT_REQ_RX_READY); + + ret = h2c_pkt_set_hdr(adapter, h2cb, + FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC, + FWCMD_H2C_CL_WOW, FWCMD_H2C_FUNC_AOAC_REPORT_REQ, + 1, 0); + if (ret) + goto fail; + + ret = h2c_pkt_build_txd(adapter, h2cb); + if (ret) + goto fail; + +#if MAC_AX_PHL_H2C + ret = PLTFM_TX(h2cb); +#else + ret = PLTFM_TX(h2cb->data, h2cb->len); +#endif + if (ret) { + PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret); + adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_ERROR; + goto fail; + } + + h2cb_free(adapter, h2cb); + + return MACSUCCESS; +fail: + h2cb_free(adapter, h2cb); + + return ret; +} + +u32 _mac_request_aoac_report_rx_not_rdy(struct mac_ax_adapter *adapter) +{ + struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info; + struct mac_ax_aoac_report *aoac_rpt = (struct mac_ax_aoac_report *)wow_info->aoac_report; + struct mac_ax_h2creg_info h2c_info = {0}; + struct mac_ax_c2hreg_poll c2h_poll = {0}; + struct fwcmd_c2hreg *c2h_content = &c2h_poll.c2hreg_cont.c2h_content; + u32 ret; + u8 *p_iv; + + h2c_info.id = FWCMD_H2CREG_FUNC_AOAC_RPT_1; + h2c_info.content_len = sizeof(struct fwcmd_aoac_rpt_1); + + c2h_poll.polling_id = FWCMD_C2HREG_FUNC_AOAC_RPT_1; + c2h_poll.retry_cnt = WOW_GET_AOAC_RPT_C2H_CNT; + c2h_poll.retry_wait_us = WOW_GET_AOAC_RPT_C2H_DLY; + + ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: get aoac rpt(%d) fail: %d\n", + __func__, FWCMD_C2HREG_FUNC_AOAC_RPT_1, ret); + return ret; + } + + aoac_rpt->key_idx = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX); + aoac_rpt->rekey_ok = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK); + p_iv = (&aoac_rpt->gtk_rx_iv_0[0] + (aoac_rpt->key_idx * IV_LENGTH)); + p_iv[0] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_1_IV_0); + p_iv[1] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_1_IV_1); + p_iv[2] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_1_IV_2); + p_iv[3] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_1_IV_3); + p_iv[4] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_1_IV_4); + p_iv[5] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_1_IV_5); + p_iv[6] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_1_IV_6); + p_iv[7] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_1_IV_7); + aoac_rpt->ptk_rx_iv[0] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0); + aoac_rpt->ptk_rx_iv[1] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1); + aoac_rpt->ptk_rx_iv[2] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2); + aoac_rpt->ptk_rx_iv[3] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3); + + h2c_info.id = FWCMD_H2CREG_FUNC_AOAC_RPT_2; + h2c_info.content_len = sizeof(struct fwcmd_aoac_rpt_2); + + c2h_poll.polling_id = FWCMD_C2HREG_FUNC_AOAC_RPT_2; + c2h_poll.retry_cnt = WOW_GET_AOAC_RPT_C2H_CNT; + c2h_poll.retry_wait_us = WOW_GET_AOAC_RPT_C2H_DLY; + ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("%s: get aoac rpt(%d) fail: %d\n", + __func__, FWCMD_C2HREG_FUNC_AOAC_RPT_2, ret); + return ret; + } + + aoac_rpt->ptk_rx_iv[4] = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4); + aoac_rpt->ptk_rx_iv[5] = GET_FIELD(c2h_content->dword0, + FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5); + aoac_rpt->ptk_rx_iv[6] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6); + aoac_rpt->ptk_rx_iv[7] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7); + aoac_rpt->igtk_ipn[0] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0); + aoac_rpt->igtk_ipn[1] = GET_FIELD(c2h_content->dword1, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1); + aoac_rpt->igtk_ipn[2] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2); + aoac_rpt->igtk_ipn[3] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3); + aoac_rpt->igtk_ipn[4] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4); + aoac_rpt->igtk_ipn[5] = GET_FIELD(c2h_content->dword2, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5); + aoac_rpt->igtk_ipn[6] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6); + aoac_rpt->igtk_ipn[7] = GET_FIELD(c2h_content->dword3, + FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7); + + return MACSUCCESS; +} + +u32 mac_request_aoac_report(struct mac_ax_adapter *adapter, + u8 rx_ready) +{ + u32 ret; + struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info; + + if (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_IDLE) + return MACPROCERR; + + if (wow_info->aoac_report) { + PLTFM_FREE(wow_info->aoac_report, + sizeof(struct mac_ax_aoac_report)); + } + wow_info->aoac_report = (u8 *)PLTFM_MALLOC(sizeof(struct mac_ax_aoac_report)); + if (!wow_info->aoac_report) { + PLTFM_MSG_ERR("%s: malloc fail\n", __func__); + return MACBUFALLOC; + } + + adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_H2C_SENDING; + + if (rx_ready) + ret = _mac_request_aoac_report_rx_rdy(adapter); + else + ret = _mac_request_aoac_report_rx_not_rdy(adapter); + + return ret; +} + +u32 mac_read_aoac_report(struct mac_ax_adapter *adapter, + struct mac_ax_aoac_report *rpt_buf, u8 rx_ready) +{ + struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info; + u32 ret = MACSUCCESS; + u8 cnt = 100; + + while ((rx_ready) && (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_H2C_DONE)) { + PLTFM_DELAY_MS(1); + if (--cnt == 0) { + PLTFM_MSG_ERR("[ERR] read aoac report(%d) fail\n", + adapter->sm.aoac_rpt); + adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_IDLE; + return MACPOLLTO; + } + } + + if (wow_info->aoac_report) { + PLTFM_MEMCPY(rpt_buf, wow_info->aoac_report, + sizeof(struct mac_ax_aoac_report)); + PLTFM_FREE(wow_info->aoac_report, + sizeof(struct mac_ax_aoac_report)); + wow_info->aoac_report = NULL; + } else { + PLTFM_MSG_ERR("[ERR] aoac report memory allocate fail\n"); + ret = MACBUFALLOC; + } + + adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_IDLE; + + return ret; +} + +u32 mac_check_aoac_report_done(struct mac_ax_adapter *adapter) +{ + PLTFM_MSG_TRACE("[TRACE]%s: curr state: %d\n", __func__, + adapter->sm.aoac_rpt); + + if (adapter->sm.aoac_rpt == MAC_AX_AOAC_RPT_H2C_DONE) + return MACSUCCESS; + else + return MACPROCBUSY; +} + +u32 mac_wow_stop_trx(struct mac_ax_adapter *adapter) +{ + struct mac_ax_h2creg_info h2c_info; + struct mac_ax_c2hreg_poll c2h_poll; + u32 ret; + + if (adapter->sm.wow_stoptrx_stat == MAC_AX_WOW_STOPTRX_BUSY) { + PLTFM_MSG_ERR("[ERR]wow stop trx busy\n"); + return MACPROCERR; + } else if (adapter->sm.wow_stoptrx_stat == MAC_AX_WOW_STOPTRX_FAIL) { + PLTFM_MSG_WARN("[WARN]prev wow stop trx fail\n"); + } + + adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_BUSY; + + h2c_info.id = FWCMD_H2CREG_FUNC_WOW_TRX_STOP; + h2c_info.content_len = 0; + h2c_info.h2c_content.dword0 = 0; + h2c_info.h2c_content.dword1 = 0; + h2c_info.h2c_content.dword2 = 0; + h2c_info.h2c_content.dword3 = 0; + + c2h_poll.polling_id = FWCMD_C2HREG_FUNC_WOW_TRX_STOP; + c2h_poll.retry_cnt = WOW_GET_STOP_TRX_C2H_CNT; + c2h_poll.retry_wait_us = WOW_GET_STOP_TRX_C2H_DLY; + + ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll); + if (ret != MACSUCCESS) { + PLTFM_MSG_ERR("[ERR]wow stoptrx proc msg reg %d\n", ret); + adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_FAIL; + return ret; + } + + adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_IDLE; + + return MACSUCCESS; +} + +u32 free_aoac_report(struct mac_ax_adapter *adapter) +{ + struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info; + + if (wow_info->aoac_report) { + PLTFM_FREE(wow_info->aoac_report, + sizeof(struct mac_ax_aoac_report)); + wow_info->aoac_report = NULL; + } else { + PLTFM_MSG_ERR("[ERR] aoac report pointer null\n"); + } + + return MACSUCCESS; +} diff --git a/phl/hal_g6/mac/mac_ax/wowlan.h b/phl/hal_g6/mac/mac_ax/wowlan.h new file mode 100644 index 0000000..f5a1b19 --- /dev/null +++ b/phl/hal_g6/mac/mac_ax/wowlan.h @@ -0,0 +1,836 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_WOWLAN_H_ +#define _MAC_AX_WOWLAN_H_ + +#include "../type.h" +#include "fwcmd.h" +#include "role.h" +#include "gpio_cmd.h" + +#define WOW_GET_STOP_TRX_C2H_CNT 10000 +#define WOW_GET_STOP_TRX_C2H_DLY 10 + +#define WOW_GET_AOAC_RPT_C2H_CNT 1000 +#define WOW_GET_AOAC_RPT_C2H_DLY 100 + +#define WOW_STOPTRX_H2CREG_DW_SIZE 1 /* mapping to struct wow_stoptrx_h2creg */ + +/** + * @struct keep_alive + * @brief keep_alive + * + * @var keep_alive::keepalive_en + * Please Place Description here. + * @var keep_alive::rsvd0 + * Please Place Description here. + * @var keep_alive::packet_id + * Please Place Description here. + * @var keep_alive::period + * Please Place Description here. + * @var keep_alive::mac_id + * Please Place Description here. + */ +struct keep_alive { + u32 keepalive_en:1; + u32 rsvd0:7; + u32 packet_id:8; + u32 period:8; + u32 mac_id:8; +}; + +/** + * @struct disconnect_detect + * @brief disconnect_detect + * + * @var disconnect_detect::disconnect_detect_en + * Please Place Description here. + * @var disconnect_detect::tryok_bcnfail_count_en + * Please Place Description here. + * @var disconnect_detect::disconnect_en + * Please Place Description here. + * @var disconnect_detect::rsvd0 + * Please Place Description here. + * @var disconnect_detect::mac_id + * Please Place Description here. + * @var disconnect_detect::check_period + * Please Place Description here. + * @var disconnect_detect::try_pkt_count + * Please Place Description here. + * @var disconnect_detect::tryok_bcnfail_count_limit + * Please Place Description here. + * @var disconnect_detect::rsvd1 + * Please Place Description here. + */ +struct disconnect_detect { + u32 disconnect_detect_en:1; + u32 tryok_bcnfail_count_en:1; + u32 disconnect_en:1; + u32 rsvd0:5; + u32 mac_id:8; + u32 check_period:8; + u32 try_pkt_count:8; + u32 tryok_bcnfail_count_limit:8; + u32 rsvd1:24; +}; + +/** + * @struct wow_global + * @brief wow_global + * + * @var wow_global::wow_en + * Please Place Description here. + * @var wow_global::drop_all_pkt + * Please Place Description here. + * @var wow_global::rx_parse_after_wake + * Please Place Description here. + * @var wow_global::rsvd0 + * Please Place Description here. + * @var wow_global::mac_id + * Please Place Description here. + * @var wow_global::pairwise_sec_algo + * Please Place Description here. + * @var wow_global::group_sec_algo + * Please Place Description here. + * @var wow_global::remotectrl_info_content + * Please Place Description here. + * @var wow_global::remotectrl_info_more + * Please Place Description here. + */ +struct wow_global { + u32 wow_en:1; + u32 drop_all_pkt:1; + u32 rx_parse_after_wake:1; + u32 rsvd0:5; + u32 mac_id:8; + u32 pairwise_sec_algo:8; + u32 group_sec_algo:8; + u32 remotectrl_info_content; + u32 remotectrl_info_more[sizeof(struct + mac_ax_remotectrl_info_parm_) / 4 - 1]; +}; + +/** + * @struct gtk_ofld + * @brief gtk_ofld + * + * @var gtk_ofld::gtk_en + * Please Place Description here. + * @var gtk_ofld::tkip_en + * Please Place Description here. + * @var gtk_ofld::ieee80211w_en + * Please Place Description here. + * @var gtk_ofld::pairwise_wakeup + * Please Place Description here. + * @var gtk_ofld::rsvd0 + * Please Place Description here. + * @var gtk_ofld::aoac_rep_id + * Please Place Description here. + * @var gtk_ofld::mac_id + * Please Place Description here. + * @var gtk_ofld::gtk_rsp_id + * Please Place Description here. + * @var gtk_ofld::pmf_sa_query_id + * Please Place Description here. + * @var gtk_ofld::bip_sec_algo + * Please Place Description here. + * @var gtk_ofld::rsvd1 + * Please Place Description here. + * @var gtk_ofld::gtk_info_content + * Please Place Description here. + * @var gtk_ofld::gtk_info_more + * Please Place Description here. + */ +struct gtk_ofld { + u32 gtk_en:1; + u32 tkip_en:1; + u32 ieee80211w_en:1; + u32 pairwise_wakeup:1; + u32 rsvd0:4; + u32 aoac_rep_id:8; + u32 mac_id:8; + u32 gtk_rsp_id:8; + u32 pmf_sa_query_id:8; + u32 bip_sec_algo:2; + u32 algo_akm_suit: 8; + u32 rsvd1: 14; + + u32 gtk_info_content; + //u32 gtk_info_more[30]; + u32 gtk_info_more[sizeof(struct mac_ax_gtk_info_parm_) / 4 - 1]; +}; + +/** + * @struct arp_ofld + * @brief arp_ofld + * + * @var arp_ofld::arp_en + * Please Place Description here. + * @var arp_ofld::arp_action + * Please Place Description here. + * @var arp_ofld::rsvd0 + * Please Place Description here. + * @var arp_ofld::mac_id + * Please Place Description here. + * @var arp_ofld::arp_rsp_id + * Please Place Description here. + * @var arp_ofld::arp_info_content + * Please Place Description here. + */ +struct arp_ofld { + u32 arp_en:1; + u32 arp_action:1; + u32 rsvd0:14; + u32 mac_id:8; + u32 arp_rsp_id:8; + u32 arp_info_content:32; +}; + +/** + * @struct ndp_ofld + * @brief ndp_ofld + * + * @var ndp_ofld::ndp_en + * Please Place Description here. + * @var ndp_ofld::rsvd0 + * Please Place Description here. + * @var ndp_ofld::mac_id + * Please Place Description here. + * @var ndp_ofld::na_id + * Please Place Description here. + * @var ndp_ofld::ndp_info_content + * Please Place Description here. + * @var ndp_ofld::ndp_info_more + * Please Place Description here. + */ +struct ndp_ofld { + u32 ndp_en:1; + u32 rsvd0:15; + u32 mac_id:8; + u32 na_id:8; + u32 ndp_info_content; + //u32 ndp_info_more[27]; + u32 ndp_info_more[2 * sizeof(struct mac_ax_ndp_info_parm_) / 4 - 1]; +}; + +/** + * @struct realwow + * @brief realwow + * + * @var realwow::realwow_en + * Please Place Description here. + * @var realwow::auto_wakeup + * Please Place Description here. + * @var realwow::rsvd0 + * Please Place Description here. + * @var realwow::mac_id + * Please Place Description here. + * @var realwow::keepalive_id + * Please Place Description here. + * @var realwow::wakeup_pattern_id + * Please Place Description here. + * @var realwow::ack_pattern_id + * Please Place Description here. + * @var realwow::rsvd1 + * Please Place Description here. + * @var realwow::realwow_info_content + * Please Place Description here. + * @var realwow::realwow_info_more + * Please Place Description here. + */ +struct realwow { + u32 realwow_en:1; + u32 auto_wakeup:1; + u32 rsvd0:22; + u32 mac_id:8; + u32 keepalive_id:8; + u32 wakeup_pattern_id:8; + u32 ack_pattern_id:8; + u32 rsvd1:8; + u32 realwow_info_content; + u32 realwow_info_more[sizeof(struct mac_ax_realwowv2_info_parm_) + / 4 - 1]; +}; + +/** + * @struct nlo + * @brief nlo + * + * @var nlo::nlo_en + * Please Place Description here. + * @var nlo::nlo_32k_en + * Please Place Description here. + * @var nlo::ignore_cipher_type + * Please Place Description here. + * @var nlo::rsvd0 + * Please Place Description here. + * @var nlo::mac_id + * Please Place Description here. + * @var nlo::nlo_networklistinfo_content + * Please Place Description here. + * @var nlo::nlo_networklistinfo_more + * Please Place Description here. + */ +struct nlo { + u32 nlo_en:1; + u32 nlo_32k_en:1; + u32 ignore_cipher_type:1; + u32 rsvd0:21; + u32 mac_id:8; + u32 nlo_networklistinfo_content; + u32 nlo_networklistinfo_more[sizeof(struct mac_ax_nlo_networklist_parm_) + / 4 - 1]; +}; + +/** + * @struct wakeup_ctrl + * @brief wakeup_ctrl + * + * @var wakeup_ctrl::pattern_match_en + * Please Place Description here. + * @var wakeup_ctrl::magic_en + * Please Place Description here. + * @var wakeup_ctrl::hw_unicast_en + * Please Place Description here. + * @var wakeup_ctrl::fw_unicast_en + * Please Place Description here. + * @var wakeup_ctrl::deauth_wakeup + * Please Place Description here. + * @var wakeup_ctrl::rekey_wakeup + * Please Place Description here. + * @var wakeup_ctrl::eap_wakeup + * Please Place Description here. + * @var wakeup_ctrl::all_data_wakeup + * Please Place Description here. + * @var wakeup_ctrl::rsvd0 + * Please Place Description here. + * @var wakeup_ctrl::rsvd1 + * Please Place Description here. + * @var wakeup_ctrl::mac_id + * Please Place Description here. + */ +struct wakeup_ctrl { + u32 pattern_match_en:1; + u32 magic_en:1; + u32 hw_unicast_en:1; + u32 fw_unicast_en:1; + u32 deauth_wakeup:1; + u32 rekey_wakeup:1; + u32 eap_wakeup:1; + u32 all_data_wakeup:1; + u32 rsvd0:1; + u32 rsvd1:15; + u32 mac_id:8; +}; + +/** + * @struct negative_pattern + * @brief negative_pattern + * + * @var negative_pattern::negative_pattern_en + * Please Place Description here. + * @var negative_pattern::rsvd0 + * Please Place Description here. + * @var negative_pattern::pattern_count + * Please Place Description here. + * @var negative_pattern::mac_id + * Please Place Description here. + * @var negative_pattern::pattern_content + * Please Place Description here. + */ +struct negative_pattern { + u32 negative_pattern_en:1; + u32 rsvd0:19; + u32 pattern_count:4; + u32 mac_id:8; + u32 pattern_content:32; +}; + +/** + * @struct uphy_ctrl + * @brief uphy_ctrl + * + * @var uphy_ctrl::disable_uphy + * Please Place Description here. + * @var uphy_ctrl::handshake_mode + * Please Place Description here. + * @var uphy_ctrl::rsvd0 + * Please Place Description here. + * @var uphy_ctrl::rise_hst2dev_dis_uphy + * Please Place Description here. + * @var uphy_ctrl::uphy_dis_delay_unit + * Please Place Description here. + * @var uphy_ctrl::pdn_as_uphy_dis + * Please Place Description here. + * @var uphy_ctrl::pdn_to_enable_uphy + * Please Place Description here. + * @var uphy_ctrl::rsvd1 + * Please Place Description here. + * @var uphy_ctrl::hst2dev_gpio_num + * Please Place Description here. + * @var uphy_ctrl::uphy_dis_delay_count + * Please Place Description here. + */ +struct uphy_ctrl { + u32 disable_uphy:1; + u32 handshake_mode:3; + u32 rsvd0:4; + u32 rise_hst2dev_dis_uphy:1; + u32 uphy_dis_delay_unit:1; + u32 pdn_as_uphy_dis:1; + u32 pdn_to_enable_uphy:1; + u32 rsvd1:4; + u32 hst2dev_gpio_num:8; + u32 uphy_dis_delay_count:8; +}; + +/** + * @struct wowcam_upd + * @brief wowcam_upd + * + * @var wowcam_upd::r_w + * Please Place Description here. + * @var wowcam_upd::idx + * Please Place Description here. + * @var wowcam_upd::rsvd0 + * Please Place Description here. + * @var wowcam_upd::wkfm1 + * Please Place Description here. + * @var wowcam_upd::wkfm2 + * Please Place Description here. + * @var wowcam_upd::wkfm3 + * Please Place Description here. + * @var wowcam_upd::wkfm4 + * Please Place Description here. + * @var wowcam_upd::crc + * Please Place Description here. + * @var wowcam_upd::rsvd1 + * Please Place Description here. + * @var wowcam_upd::negative_pattern_match + * Please Place Description here. + * @var wowcam_upd::skip_mac_hdr + * Please Place Description here. + * @var wowcam_upd::uc + * Please Place Description here. + * @var wowcam_upd::mc + * Please Place Description here. + * @var wowcam_upd::bc + * Please Place Description here. + * @var wowcam_upd::rsvd2 + * Please Place Description here. + * @var wowcam_upd::valid + * Please Place Description here. + */ +struct wowcam_upd { + u32 r_w: 1; + u32 idx: 7; + u32 rsvd0: 24; + u32 wkfm1: 32; + u32 wkfm2: 32; + u32 wkfm3: 32; + u32 wkfm4: 32; + u32 crc: 16; + u32 rsvd1: 6; + u32 negative_pattern_match: 1; + u32 skip_mac_hdr: 1; + u32 uc: 1; + u32 mc: 1; + u32 bc: 1; + u32 rsvd2: 4; + u32 valid: 1; +}; + +struct wow_stoptrx_h2creg { + u32 func:7; + u32 ack:1; + u32 total_len:4; + u32 seq_num:4; + u32 rsvd:16; +}; + +/** + * @addtogroup WakeOnWlan + * @{ + */ +/** + * @brief mac_cfg_wow_wake + * + * @param *adapter + * @param macid + * @param *info + * @param *content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_wow_wake(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_wow_wake_info *info, + struct mac_ax_remotectrl_info_parm_ *content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_disconnect_det + * + * @param *adapter + * @param macid + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_disconnect_det(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_disconnect_det_info *info); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_keep_alive + * + * @param *adapter + * @param macid + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_keep_alive(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_keep_alive_info *info); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief get_wake_reason + * + * @param *adapter + * @param *wowlan_wake_reason + * @return Please Place Description here. + * @retval u32 + */ + +u32 get_wake_reason(struct mac_ax_adapter *adapter, + u8 *wowlan_wake_reason); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_gtk_ofld + * + * @param *adapter + * @param macid + * @param *info + * @param *content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_gtk_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_gtk_ofld_info *info, + struct mac_ax_gtk_info_parm_ *content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_arp_ofld + * + * @param *adapter + * @param macid + * @param *info + * @param *parp_info_content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_arp_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_arp_ofld_info *info, + void *parp_info_content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_ndp_ofld + * + * @param *adapter + * @param macid + * @param *info + * @param *content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_ndp_ofld(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_ndp_ofld_info *info, + struct mac_ax_ndp_info_parm_ *content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_realwow + * + * @param *adapter + * @param macid + * @param *info + * @param *content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_realwow(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_realwow_info *info, + struct mac_ax_realwowv2_info_parm_ *content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_nlo + * + * @param *adapter + * @param macid + * @param *info + * @param *content + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_nlo(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_nlo_info *info, + struct mac_ax_nlo_networklist_parm_ *content); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_dev2hst_gpio + * + * @param *adapter + * @param *parm + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_dev2hst_gpio(struct mac_ax_adapter *adapter, + struct mac_ax_dev2hst_gpio_info *parm); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_uphy_ctrl + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_uphy_ctrl(struct mac_ax_adapter *adapter, + struct mac_ax_uphy_ctrl_info *info); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_wowcam_upd + * + * @param *adapter + * @param *info + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_wowcam_upd(struct mac_ax_adapter *adapter, + struct mac_ax_wowcam_upd_info *info); +/** + * @} + */ + +u32 mac_get_wow_wake_rsn(struct mac_ax_adapter *adapter, u8 *wake_rsn, + u8 *reset); + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_cfg_wow_sleep + * + * @param *adapter + * @param sleep + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_cfg_wow_sleep(struct mac_ax_adapter *adapter, + u8 sleep); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_get_wow_fw_status + * + * @param *adapter + * @param *status + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_get_wow_fw_status(struct mac_ax_adapter *adapter, + u8 *status, u8 func_en); +/** + * @} + */ + +static u32 read_aoac_c2hreg(struct mac_ax_adapter *adapter, + struct mac_ax_aoac_report *aoac_rpt); + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_request_aoac_report + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_request_aoac_report(struct mac_ax_adapter *adapter, + u8 rx_ready); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_read_aoac_report + * + * @param *adapter + * @param **rpt_buf + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_read_aoac_report(struct mac_ax_adapter *adapter, + struct mac_ax_aoac_report *rpt_buf, u8 rx_ready); +/** + * @} + */ + +/** + * @addtogroup WakeOnWlan + * @{ + */ + +/** + * @brief mac_check_aoac_report_done + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 mac_check_aoac_report_done(struct mac_ax_adapter *adapter); +/** + * @} + */ + +u32 mac_wow_stop_trx(struct mac_ax_adapter *adapter); + +u32 mac_wow_get_stoptrx_st(struct mac_ax_adapter *adapter); + +/** + * @brief free_aoac_report + * + * @param *adapter + * @return Please Place Description here. + * @retval u32 + */ +u32 free_aoac_report(struct mac_ax_adapter *adapter); +/** + * @} + * @} + */ + +#endif // #define _MAC_AX_WOWLAN_H_ diff --git a/phl/hal_g6/mac/mac_def.h b/phl/hal_g6/mac/mac_def.h new file mode 100644 index 0000000..8e056cc --- /dev/null +++ b/phl/hal_g6/mac/mac_def.h @@ -0,0 +1,15212 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_MAC_DEF_H_ +#define _MAC_AX_MAC_DEF_H_ + +#include "pltfm_cfg.h" +#include "feature_cfg.h" +#include "chip_cfg.h" +#include "mac_ax/state_mach.h" +#include "errors.h" + +#if MAC_AX_FEATURE_HV +#include "hv_type.h" +#endif + +/*--------------------Define -------------------------------------------*/ +#ifdef CONFIG_NEW_HALMAC_INTERFACE +#define PLTFM_SDIO_CMD52_R8(addr) \ + hal_sdio_cmd52_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R8(addr) \ + hal_sdio_cmd53_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R16(addr) \ + hal_sdio_cmd53_r16(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R32(addr) \ + hal_sdio_cmd53_r32(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_RN(addr, size, val) \ + hal_sdio_cmd53_rn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_W8(addr, val) \ + hal_sdio_cmd52_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W8(addr, val) \ + hal_sdio_cmd53_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_WN(addr, size, val) \ + hal_sdio_cmd53_wn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD53_W16(addr, val) \ + hal_sdio_cmd53_w16(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W32(addr, val) \ + hal_sdio_cmd53_w32(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD52_CIA_R8(addr) \ + hal_sdio_read_cia_r8(adapter->drv_adapter, addr) + +#define PLTFM_TX(buf, len) \ + hal_tx(adapter->drv_adapter, buf, len) + +#define PLTFM_FREE(buf, size) \ + hal_mem_free(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + hal_mem_alloc(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + hal_mem_cpy(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + hal_mem_set(adapter->drv_adapter, addr, value, size) +#define PLTFM_MEMCMP(ptr1, ptr2, num) \ + hal_mem_cmp(adapter->drv_adapter, ptr1, ptr2, num) + +#define PLTFM_DELAY_US(us) \ + hal_udelay(adapter->drv_adapter, us) +#define PLTFM_DELAY_MS(ms) \ + hal_mdelay(adapter->drv_adapter, ms) +#define PLTFM_MUTEX_INIT(mutex) \ + hal_mutex_init(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + hal_mutex_deinit(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + hal_mutex_lock(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + hal_mutex_unlock(adapter->drv_adapter, mutex) + +#define PLTFM_MSG_PRINT(...) \ + hal_mac_msg_print(drv_adapter, __VA_ARGS__) + +#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops)) +#define adapter_to_intf_ops(adapter) \ + ((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops)) + +#define PLTFM_REG_R8(addr) \ + hal_read8(adapter->drv_adapter, addr) +#define PLTFM_REG_R16(addr) \ + hal_read16(adapter->drv_adapter, addr) +#define PLTFM_REG_R32(addr) \ + hal_read32(adapter->drv_adapter, addr) +#define PLTFM_REG_W8(addr, val) \ + hal_write8(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W16(addr, val) \ + hal_write16(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W32(addr, val) \ + hal_write32(adapter->drv_adapter, addr, val) + +#define MAC_REG_R8(addr) hal_read8(adapter->drv_adapter, addr) +#define MAC_REG_R16(addr) hal_read16(adapter->drv_adapter, addr) +#define MAC_REG_R32(addr) hal_read32(adapter->drv_adapter, addr) +#define MAC_REG_W8(addr, val) hal_write8(adapter->drv_adapter, addr, val) +#define MAC_REG_W16(addr, val) hal_write16(adapter->drv_adapter, addr, val) +#define MAC_REG_W32(addr, val) hal_write32(adapter->drv_adapter, addr, val) + +#if MAC_AX_FEATURE_DBGCMD +#define PLTFM_SNPRINTF(s, sz, fmt, ...) \ + hal_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__) +#define PLTFM_STRCMP(s1, s2) \ + hal_strcmp(adapter->drv_adapter, s1, s2) +#define PLTFM_STRSEP(s, ct) \ + hal_strsep(adapter->drv_adapter, s, ct) +#define PLTFM_STRLEN(s) \ + hal_strlen(adapter->drv_adapter, s) +#define PLTFM_STRCPY(dest, src) \ + hal_strcpy(adapter->drv_adapter, dest, src) +#define PLTFM_STRPBRK(cs, ct) \ + hal_strpbrk(adapter->drv_adapter, cs, ct) +#define PLTFM_STRTOUL(buf, base) \ + hal_strtoul(adapter->drv_adapter, buf, base) + +#endif +#else + +/* platform callback */ +#define PLTFM_SDIO_CMD52_R8(addr) \ + adapter->pltfm_cb->sdio_cmd52_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R8(addr) \ + adapter->pltfm_cb->sdio_cmd53_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R16(addr) \ + adapter->pltfm_cb->sdio_cmd53_r16(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R32(addr) \ + adapter->pltfm_cb->sdio_cmd53_r32(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_RN(addr, size, val) \ + adapter->pltfm_cb->sdio_cmd53_rn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_W8(addr, val) \ + adapter->pltfm_cb->sdio_cmd52_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W8(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W16(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w16(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W32(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w32(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_WN(addr, size, val) \ + adapter->pltfm_cb->sdio_cmd53_wn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_CIA_R8(addr) \ + adapter->pltfm_cb->sdio_cmd52_cia_r8(adapter->drv_adapter, addr) + +#define PLTFM_REG_R8(addr) \ + adapter->pltfm_cb->reg_r8(adapter->drv_adapter, addr) +#define PLTFM_REG_R16(addr) \ + adapter->pltfm_cb->reg_r16(adapter->drv_adapter, addr) +#define PLTFM_REG_R32(addr) \ + adapter->pltfm_cb->reg_r32(adapter->drv_adapter, addr) +#define PLTFM_REG_W8(addr, val) \ + adapter->pltfm_cb->reg_w8(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W16(addr, val) \ + adapter->pltfm_cb->reg_w16(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W32(addr, val) \ + adapter->pltfm_cb->reg_w32(adapter->drv_adapter, addr, val) + +#if MAC_AX_PHL_H2C +#define PLTFM_TX(buf) \ + adapter->pltfm_cb->tx(adapter->phl_adapter, adapter->drv_adapter, buf) +#define PLTFM_QUERY_H2C(type) \ + adapter->pltfm_cb->rtl_query_h2c(adapter->phl_adapter, \ + adapter->drv_adapter, type) +#define PLTFM_RECYCLE_H2C(buf) \ + adapter->pltfm_cb->rtl_recycle_h2c(adapter->phl_adapter, buf) +#else +#define PLTFM_TX(buf, len) \ + adapter->pltfm_cb->tx(adapter->drv_adapter, buf, len) +#endif +#define PLTFM_FREE(buf, size) \ + adapter->pltfm_cb->rtl_free(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + adapter->pltfm_cb->rtl_malloc(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + adapter->pltfm_cb->rtl_memcpy(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + adapter->pltfm_cb->rtl_memset(adapter->drv_adapter, addr, value, size) +#define PLTFM_MEMCMP(ptr1, ptr2, num) \ + adapter->pltfm_cb->rtl_memcmp(adapter->drv_adapter, ptr1, ptr2, num) +#define PLTFM_DELAY_US(us) \ + adapter->pltfm_cb->rtl_delay_us(adapter->drv_adapter, us) +#define PLTFM_DELAY_MS(ms) \ + adapter->pltfm_cb->rtl_delay_ms(adapter->drv_adapter, ms) + +#define PLTFM_MUTEX_INIT(mutex) \ + adapter->pltfm_cb->rtl_mutex_init(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + adapter->pltfm_cb->rtl_mutex_deinit(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + adapter->pltfm_cb->rtl_mutex_lock(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + adapter->pltfm_cb->rtl_mutex_unlock(adapter->drv_adapter, mutex) + +#define PLTFM_EVENT_NOTIFY(mac_ft, stat, buf, size) \ + adapter->pltfm_cb->event_notify(adapter->drv_adapter, mac_ft, stat, \ + buf, size) +#define PLTFM_L2_NOTIFY(void) \ + adapter->pltfm_cb->ser_l2_notify(adapter->phl_adapter, adapter->drv_adapter) + +#define PLTFM_LD_FW_SYMBOL(name, buf, buf_size) \ + adapter->pltfm_cb->ld_fw_symbol(adapter->phl_adapter, adapter->drv_adapter,\ + name, buf, buf_size) + +#define PLTFM_MSG_PRINT(...) \ + adapter->pltfm_cb->msg_print(drv_adapter, u8 dbg_level, __VA_ARGS__) + +#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops)) +#define adapter_to_intf_ops(adapter) \ + ((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops)) + +#define MAC_REG_R8(addr) ops->reg_read8(adapter, addr) +#define MAC_REG_R16(addr) ops->reg_read16(adapter, addr) +#define MAC_REG_R32(addr) ops->reg_read32(adapter, addr) +#define MAC_REG_W8(addr, val) ops->reg_write8(adapter, addr, val) +#define MAC_REG_W16(addr, val) ops->reg_write16(adapter, addr, val) +#define MAC_REG_W32(addr, val) ops->reg_write32(adapter, addr, val) + +#if MAC_AX_FEATURE_DBGCMD +#define PLTFM_SNPRINTF(s, sz, fmt, ...) \ + adapter->pltfm_cb->rtl_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__) +#define PLTFM_STRCMP(s1, s2) \ + adapter->pltfm_cb->rtl_strcmp(adapter->drv_adapter, s1, s2) +#define PLTFM_STRSEP(s, ct) \ + adapter->pltfm_cb->rtl_strsep(adapter->drv_adapter, s, ct) +#define PLTFM_STRLEN(s) \ + adapter->pltfm_cb->rtl_strlen(adapter->drv_adapter, s) +#define PLTFM_STRCPY(dest, src) \ + adapter->pltfm_cb->rtl_strcpy(adapter->drv_adapter, dest, src) +#define PLTFM_STRPBRK(cs, ct) \ + adapter->pltfm_cb->rtl_strpbrk(adapter->drv_adapter, cs, ct) +#define PLTFM_STRTOUL(buf, base) \ + adapter->pltfm_cb->rtl_strtoul(adapter->drv_adapter, buf, base) +#endif + +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +/*--------------------Define MACRO--------------------------------------*/ +#define MAC_AX_MAX_RU_NUM 4 +#define WLAN_ADDR_LEN 6 +#define MAX_VHT_SUPPORT_SOUND_STA 4 +#define MAX_HE_SUPPORT_SOUND_STA 8 +#define MAC_AX_BCN_INTERVAL_DEFAULT 100 +#define MAC_RX_USB_AGG_MODE_UNIT 4096 +#define MAC_RX_DMA_AGG_MODE_UNIT 1024 +#define MAC_MAX_ARGC 20 +#define MAC_MAX_ARGV 16 +#define MAC_AX_DP_SEL_NUM 2 + +#ifdef PHL_FEATURE_AP +#define MAC_STA_NUM 128 +#else /*for NIC mode setting*/ +#define MAC_STA_NUM 32 +#endif + +#define MAC_AX_FAST_CH_SW_MAX_STA_NUM 4 +#define UL_PER_STA_DBGINFO_NUM 0x10 +#define SCANOFLD_MAX_ADDITION_PKT_NUM 8 + +#define SS_LINK_SIZE 256 +#define lps_pwr_state ps_pwr_state //temp, should remove + +/*--------------------Define Enum---------------------------------------*/ + +/** + * @enum mac_ax_intf + * + * @brief mac_ax_intf + * + * @var mac_ax_intf::MAC_AX_INTF_USB + * Please Place Description here. + * @var mac_ax_intf::MAC_AX_INTF_SDIO + * Please Place Description here. + * @var mac_ax_intf::MAC_AX_INTF_PCIE + * Please Place Description here. + * @var mac_ax_intf::MAC_AX_INTF_LAST + * Please Place Description here. + * @var mac_ax_intf::MAC_AX_INTF_MAX + * Please Place Description here. + * @var mac_ax_intf::MAC_AX_INTF_INVALID + * Please Place Description here. + */ +enum mac_ax_intf { + MAC_AX_INTF_USB, + MAC_AX_INTF_SDIO, + MAC_AX_INTF_PCIE, + + /* keep last */ + MAC_AX_INTF_LAST, + MAC_AX_INTF_MAX = MAC_AX_INTF_LAST, + MAC_AX_INTF_INVALID = MAC_AX_INTF_LAST, +}; + +/** + * @enum mac_ax_feature + * + * @brief mac_ax_feature + * + * @var mac_ax_feature::MAC_AX_FT_DUMP_EFUSE + * Please Place Description here. + * @var mac_ax_feature::MAC_AX_FT_LAST + * Please Place Description here. + * @var mac_ax_feature::MAC_AX_FT_MAX + * Please Place Description here. + * @var mac_ax_feature::MAC_AX_FT_INVALID + * Please Place Description here. + */ +enum mac_ax_feature { + MAC_AX_FT_DUMP_EFUSE, + + /* keep last */ + MAC_AX_FT_LAST, + MAC_AX_FT_MAX = MAC_AX_FT_LAST, + MAC_AX_FT_INVALID = MAC_AX_FT_LAST, +}; + +/** + * @enum mac_ax_status + * + * @brief mac_ax_status + * + * @var mac_ax_status::MAC_AX_STATUS_IDLE + * Please Place Description here. + * @var mac_ax_status::MAC_AX_STATUS_PROC + * Please Place Description here. + * @var mac_ax_status::MAC_AX_STATUS_DONE + * Please Place Description here. + * @var mac_ax_status::MAC_AX_STATUS_ERR + * Please Place Description here. + */ +enum mac_ax_status { + MAC_AX_STATUS_IDLE, + MAC_AX_STATUS_PROC, + MAC_AX_STATUS_DONE, + MAC_AX_STATUS_ERR, +}; + +/** + * @enum mac_ax_sdio_4byte_mode + * + * @brief mac_ax_sdio_4byte_mode + * + * @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_DISABLE + * Please Place Description here. + * @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_RW + * Please Place Description here. + * @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_LAST + * Please Place Description here. + * @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_MAX + * Please Place Description here. + * @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_sdio_4byte_mode { + MAC_AX_SDIO_4BYTE_MODE_DISABLE, + MAC_AX_SDIO_4BYTE_MODE_RW, + + /* keep last */ + MAC_AX_SDIO_4BYTE_MODE_LAST, + MAC_AX_SDIO_4BYTE_MODE_MAX = MAC_AX_SDIO_4BYTE_MODE_LAST, + MAC_AX_SDIO_4BYTE_MODE_INVALID = MAC_AX_SDIO_4BYTE_MODE_LAST, +}; + +/** + * @enum mac_ax_sdio_tx_mode + * + * @brief mac_ax_sdio_tx_mode + * + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_AGG + * Please Place Description here. + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_DUMMY_BLOCK + * Please Place Description here. + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_DUMMY_AUTO + * Please Place Description here. + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_LAST + * Please Place Description here. + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_MAX + * Please Place Description here. + * @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_sdio_tx_mode { + MAC_AX_SDIO_TX_MODE_AGG, + MAC_AX_SDIO_TX_MODE_DUMMY_BLOCK, + MAC_AX_SDIO_TX_MODE_DUMMY_AUTO, + + /* keep last */ + MAC_AX_SDIO_TX_MODE_LAST, + MAC_AX_SDIO_TX_MODE_MAX = MAC_AX_SDIO_TX_MODE_LAST, + MAC_AX_SDIO_TX_MODE_INVALID = MAC_AX_SDIO_TX_MODE_LAST, +}; + +/** + * @enum mac_ax_sdio_opn_mode + * + * @brief mac_ax_sdio_opn_mode + * + * @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_BYTE + * Please Place Description here. + * @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_BLOCK + * Please Place Description here. + * @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_UNKNOWN + * Please Place Description here. + */ +enum mac_ax_sdio_opn_mode { + MAC_AX_SDIO_OPN_MODE_BYTE = 0, + MAC_AX_SDIO_OPN_MODE_BLOCK, + MAC_AX_SDIO_OPN_MODE_UNKNOWN, +}; + +/** + * @enum mac_ax_sdio_spec_ver + * + * @brief mac_ax_sdio_spec_ver + * + * @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_2_00 + * Please Place Description here. + * @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_3_00 + * Please Place Description here. + * @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_LAST + * Please Place Description here. + * @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_MAX + * Please Place Description here. + * @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_INVALID + * Please Place Description here. + */ +enum mac_ax_sdio_spec_ver { + MAC_AX_SDIO_SPEC_VER_2_00, + MAC_AX_SDIO_SPEC_VER_3_00, + + /* keep last */ + MAC_AX_SDIO_SPEC_VER_LAST, + MAC_AX_SDIO_SPEC_VER_MAX = MAC_AX_SDIO_SPEC_VER_LAST, + MAC_AX_SDIO_SPEC_VER_INVALID = MAC_AX_SDIO_SPEC_VER_LAST, +}; + +/** + * @enum mac_ax_use_ver + * + * @brief mac_ax_use_ver + * + * @var mac_ax_use_ver::MAC_AX_USB11 + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB2 + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB3 + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_LAST + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_MAX + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_INVALID + * Please Place Description here. + */ +enum mac_ax_use_ver { + MAC_AX_USB10, + MAC_AX_USB11, + MAC_AX_USB2, + MAC_AX_USB3, + + MAC_AX_USB_LAST, + MAC_AX_USB_MAX = MAC_AX_USB_LAST, + MAC_AX_USB_INVALID = MAC_AX_USB_LAST, +}; + +/** + * @enum mac_ax_use_mode + * + * @brief mac_ax_use_mode + * + * @var mac_ax_use_ver::MAC_AX_USB_NORM + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_AUTOINSTALL + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_LAST + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_MAX + * Please Place Description here. + * @var mac_ax_use_ver::MAC_AX_USB_INVALID + * Please Place Description here. + */ +enum mac_ax_use_mode { + MAC_AX_USB_NORM, + MAC_AX_USB_AUTOINSTALL, + + MAC_AX_USB_MODE_LAST, + MAC_AX_USB_MODE_MAX = MAC_AX_USB_LAST, + MAC_AX_USB_MODE_INVALID = MAC_AX_USB_LAST, +}; + +/** + * @enum mac_ax_lv1_rcvy_step + * + * @brief mac_ax_lv1_rcvy_step + * + * @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_1 + * Please Place Description here. + * @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_2 + * Please Place Description here. + * @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_LAST + * Please Place Description here. + * @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_MAX + * Please Place Description here. + * @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_INVALID + * Please Place Description here. + */ +enum mac_ax_lv1_rcvy_step { + MAC_AX_LV1_RCVY_STEP_1 = 0, + MAC_AX_LV1_RCVY_STEP_2, + + /* keep last */ + MAC_AX_LV1_RCVY_STEP_LAST, + MAC_AX_LV1_RCVY_STEP_MAX = MAC_AX_LV1_RCVY_STEP_LAST, + MAC_AX_LV1_RCVY_STEP_INVALID = MAC_AX_LV1_RCVY_STEP_LAST, +}; + +/** + * @enum mac_ax_ex_shift + * + * @brief mac_ax_ex_shift + * + * @var mac_ax_ex_shift::MAC_AX_NO_SHIFT + * Please Place Description here. + * @var mac_ax_ex_shift::MAC_AX_BYTE_ALIGNED_4 + * Please Place Description here. + * @var mac_ax_ex_shift::MAC_AX_BYTE_ALIGNED_8 + * Please Place Description here. + */ +enum mac_ax_ex_shift { + MAC_AX_NO_SHIFT = 0, + MAC_AX_BYTE_ALIGNED_4 = 1, + MAC_AX_BYTE_ALIGNED_8 = 2 +}; + +/** + * @enum mac_ax_ps_mode + * + * @brief mac_ax_ps_mode + * + * @var mac_ax_ps_mode::MAC_AX_PS_MODE_ACTIVE + * Please Place Description here. + * @var mac_ax_ps_mode::MAC_AX_PS_MODE_LEGACY + * Please Place Description here. + * @var mac_ax_ps_mode::MAC_AX_PS_MODE_WMMPS + * Please Place Description here. + * @var mac_ax_ps_mode::MAC_AX_PS_MODE_MAX + * Please Place Description here. + */ +enum mac_ax_ps_mode { + MAC_AX_PS_MODE_ACTIVE = 0, + MAC_AX_PS_MODE_LEGACY = 1, + MAC_AX_PS_MODE_WMMPS = 2, + MAC_AX_PS_MODE_MAX = 3, +}; + +/** + * @enum mac_ax_pwr_state_action + * + * @brief mac_ax_pwr_state_action + * + * @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_REQ + * Please Place Description here. + * @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_CHK + * Please Place Description here. + * @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_MAX + * Please Place Description here. + */ +enum mac_ax_pwr_state_action { + MAC_AX_PWR_STATE_ACT_REQ = 0, + MAC_AX_PWR_STATE_ACT_CHK = 1, + MAC_AX_PWR_STATE_ACT_MAX, +}; + +/** + * @enum mac_ax_rpwm_req_pwr_state + * + * @brief mac_ax_rpwm_req_pwr_state + * + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED + * Please Place Description here. + * @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_MAX + * Please Place Description here. + */ +enum mac_ax_rpwm_req_pwr_state { + MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE = 0, + MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, + MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, + MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, + MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, + MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED = 5, + MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED = 6, + MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, + MAC_AX_RPWM_REQ_PWR_STATE_MAX, +}; + +/** + * @enum mac_ax_port_cfg_type + * + * @brief mac_ax_port_cfg_type + * + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_FUNC_SW + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_TX_SW + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_TX_RPT + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_SW + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_RPT + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_SYNC + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_PRCT + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_AGG + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_SHIFT + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_RST_TSF + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_RST_TPR + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCAID + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_WIN + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_DTIM + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_NOLIMIT + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_NET_TYPE + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_INTV + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_SETUP_TIME + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_HOLD_TIME + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_MBSSID_EN + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_ERLY + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_MASK_AREA + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_ERLY + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BSS_CLR + * Please Place Description here. + * @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_DRP_ALL + * Please Place Description here. + */ +enum mac_ax_port_cfg_type { + MAC_AX_PCFG_FUNC_SW = 0, + MAC_AX_PCFG_TX_SW, + MAC_AX_PCFG_TX_RPT, + MAC_AX_PCFG_RX_SW, + MAC_AX_PCFG_RX_RPT, + MAC_AX_PCFG_RX_SYNC, + MAC_AX_PCFG_BCN_PRCT, + MAC_AX_PCFG_TBTT_AGG, + MAC_AX_PCFG_TBTT_SHIFT, + MAC_AX_PCFG_RST_TSF, + MAC_AX_PCFG_RST_TPR, + MAC_AX_PCFG_BCAID, + MAC_AX_PCFG_HIQ_WIN, + MAC_AX_PCFG_HIQ_DTIM, + MAC_AX_PCFG_HIQ_NOLIMIT, + MAC_AX_PCFG_NET_TYPE, + MAC_AX_PCFG_BCN_INTV, + MAC_AX_PCFG_BCN_SETUP_TIME, + MAC_AX_PCFG_BCN_HOLD_TIME, + MAC_AX_PCFG_MBSSID_EN, + MAC_AX_PCFG_BCN_ERLY, + MAC_AX_PCFG_BCN_MASK_AREA, + MAC_AX_PCFG_TBTT_ERLY, + MAC_AX_PCFG_BSS_CLR, + MAC_AX_PCFG_MBSSID_NUM, + MAC_AX_PCFG_BCN_DRP_ALL, +}; + +/** + * @enum mac_ax_band + * + * @brief mac_ax_band + * + * @var mac_ax_band::MAC_AX_BAND_0 + * Please Place Description here. + * @var mac_ax_band::MAC_AX_BAND_1 + * Please Place Description here. + * @var mac_ax_band::MAC_AX_BAND_NUM + * Please Place Description here. + */ +enum mac_ax_band { + MAC_AX_BAND_0 = 0, + MAC_AX_BAND_1 = 1, + MAC_AX_BAND_NUM = 2 +}; + +/** + * @enum mac_ax_port + * + * @brief mac_ax_port + * + * @var mac_ax_port::MAC_AX_PORT_0 + * Please Place Description here. + * @var mac_ax_port::MAC_AX_PORT_1 + * Please Place Description here. + * @var mac_ax_port::MAC_AX_PORT_2 + * Please Place Description here. + * @var mac_ax_port::MAC_AX_PORT_3 + * Please Place Description here. + * @var mac_ax_port::MAC_AX_PORT_4 + * Please Place Description here. + * @var mac_ax_port::MAC_AX_PORT_NUM + * Please Place Description here. + */ +enum mac_ax_port { + MAC_AX_PORT_0 = 0, + MAC_AX_PORT_1 = 1, + MAC_AX_PORT_2 = 2, + MAC_AX_PORT_3 = 3, + MAC_AX_PORT_4 = 4, + MAC_AX_PORT_NUM +}; + +/** + * @enum mac_ax_addr_msk_sel + * + * @brief mac_ax_addr_msk_sel + * + * @var mac_ax_addr_msk_sel::MAC_AX_NO_MSK + * Please Place Description here. + * @var mac_ax_addr_msk_sel::MAC_AX_SMA_MSK + * Please Place Description here. + * @var mac_ax_addr_msk_sel::MAC_AX_TMA_MSK + * Please Place Description here. + * @var mac_ax_addr_msk_sel::MAC_AX_BSSID_MSK + * Please Place Description here. + */ +enum mac_ax_addr_msk_sel { + MAC_AX_NO_MSK, + MAC_AX_SMA_MSK, + MAC_AX_TMA_MSK, + MAC_AX_BSSID_MSK +}; + +/** + * @enum mac_ax_addr_msk + * + * @brief mac_ax_addr_msk + * + * @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE5 + * Please Place Description here. + * @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE4 + * Please Place Description here. + * @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE3 + * Please Place Description here. + * @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE2 + * Please Place Description here. + * @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE1 + * Please Place Description here. + */ +enum mac_ax_addr_msk { + MAC_AX_MSK_NONE = 0x3f, + MAC_AX_BYTE5 = 0x1f, + MAC_AX_BYTE5_TO_BYTE4 = 0xf, + MAC_AX_BYTE5_TO_BYTE3 = 0x7, + MAC_AX_BYTE5_TO_BYTE2 = 0x3, + MAC_AX_BYTE5_TO_BYTE1 = 0x1, + MAC_AX_MSK_ALL = 0x0 +}; + +/** + * @enum mac_ax_mbssid_idx + * + * @brief mac_ax_mbssid_idx + * + * @var mac_ax_mbssid_idx::MAC_AX_P0_ROOT + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID1 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID2 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID3 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID4 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID5 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID6 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID7 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID8 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID9 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID10 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID11 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID12 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID13 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID14 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID15 + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_LAST + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_MAX + * Please Place Description here. + * @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_INVALID + * Please Place Description here. + */ +enum mac_ax_mbssid_idx { + MAC_AX_P0_ROOT = 0, + MAC_AX_P0_MBID1, + MAC_AX_P0_MBID2, + MAC_AX_P0_MBID3, + MAC_AX_P0_MBID4, + MAC_AX_P0_MBID5, + MAC_AX_P0_MBID6, + MAC_AX_P0_MBID7, + MAC_AX_P0_MBID8, + MAC_AX_P0_MBID9, + MAC_AX_P0_MBID10, + MAC_AX_P0_MBID11, + MAC_AX_P0_MBID12, + MAC_AX_P0_MBID13, + MAC_AX_P0_MBID14, + MAC_AX_P0_MBID15, + + /* keep last */ + MAC_AX_P0_MBID_LAST, + MAC_AX_P0_MBID_MAX = MAC_AX_P0_MBID_LAST, + MAC_AX_P0_MBID_INVALID = MAC_AX_P0_MBID_LAST, +}; + +/** + * @enum mac_ax_hwmod_sel + * + * @brief mac_ax_hwmod_sel + * + * @var mac_ax_hwmod_sel::MAC_AX_DMAC_SEL + * Please Place Description here. + * @var mac_ax_hwmod_sel::MAC_AX_CMAC_SEL + * Please Place Description here. + * @var mac_ax_hwmod_sel::MAC_AX_MAC_LAST + * Please Place Description here. + * @var mac_ax_hwmod_sel::MAC_AX_MAC_MAX + * Please Place Description here. + * @var mac_ax_hwmod_sel::MAC_AX_MAC_INVALID + * Please Place Description here. + */ +enum mac_ax_hwmod_sel { + MAC_AX_DMAC_SEL = 0, + MAC_AX_CMAC_SEL = 1, + + /* keep last */ + MAC_AX_MAC_LAST, + MAC_AX_MAC_MAX = MAC_AX_MAC_LAST, + MAC_AX_MAC_INVALID = MAC_AX_MAC_LAST, +}; + +/** + * @enum mac_ax_ss_wmm + * + * @brief mac_ax_ss_wmm + * + * @var mac_ax_ss_wmm::MAC_AX_SS_WMM0 + * Please Place Description here. + * @var mac_ax_ss_wmm::MAC_AX_SS_WMM1 + * Please Place Description here. + * @var mac_ax_ss_wmm::MAC_AX_SS_WMM2 + * Please Place Description here. + * @var mac_ax_ss_wmm::MAC_AX_SS_WMM3 + * Please Place Description here. + * @var mac_ax_ss_wmm::MAC_AX_SS_UL + * Please Place Description here. + */ +enum mac_ax_ss_wmm { + MAC_AX_SS_WMM0, + MAC_AX_SS_WMM1, + MAC_AX_SS_WMM2, + MAC_AX_SS_WMM3, + MAC_AX_SS_UL, +}; + +/** + * @enum mac_ax_ss_quota_mode + * + * @brief mac_ax_ss_quota_mode + * + * @var mac_ax_ss_quota_mode::MAC_AX_SS_QUOTA_MODE_TIME + * Please Place Description here. + * @var mac_ax_ss_quota_mode::MAC_AX_SS_QUOTA_MODE_CNT + * Please Place Description here. + */ +enum mac_ax_ss_quota_mode { + MAC_AX_SS_QUOTA_MODE_TIME = 0, + MAC_AX_SS_QUOTA_MODE_CNT = 1, +}; + +/** + * @enum mac_ax_issue_uldl_type + * + * @brief mac_ax_issue_uldl_type + * + * @var mac_ax_issue_uldl_type::mac_ax_issue_dl + * Please Place Description here. + * @var mac_ax_issue_uldl_type::mac_ax_issue_ul + * Please Place Description here. + */ +enum mac_ax_issue_uldl_type { + mac_ax_issue_dl = 0, + mac_ax_issue_ul = 1, +}; + +/** + * @enum mac_ax_hw_id + * + * @brief mac_ax_hw_id + * + * @var mac_ax_hw_id::MAC_AX_HW_MAPPING + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_INT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_CNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_AGG_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_AMPDU_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_EDCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_EDCCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_TIMER + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_TBPPDU_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_DELAYTX_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_SS_WMM_TBL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_EFUSE_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_BT_EFUSE_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_EFUSE_MASK_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_CH_STAT_CNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_LIFETIME_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_APP_FCS + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_RX_ICVERR + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_PWR_STATE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_WAKE_REASON + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_SCOREBOARD + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_COEX_GNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_RRSR + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_COEX_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_TX_CNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_TX_TF_INFO + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_TSF + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_MAX_TX_TIME + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_SS_QUOTA_MODE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_SS_QUOTA_SETTING + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_POLLUTED_CNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_DATA_RTY_LMT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_DFLT_NAV + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_GET_BACAM_MODE_SEL + * To get the BACAM option mode. + * @var mac_ax_hw_id::MAC_AX_HW_GET_RRSR_CFG + * for Get Response rate cfg + * @var mac_ax_hw_id::MAC_AX_HW_GET_CTS_RRSR_CFG + * for Get CTS Response rate cfg + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_INFO + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_MODE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_RX_AGG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_AGG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_AVAL_PAGE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_WT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_CLK + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_PCIE_CFGSPC_SET + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_PCIE_RST_BDRAM + * Please Place Description here. + * @var mac_ax_hw_id::MAX_AX_HW_PCIE_LTR_SW_TRIGGER + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_ID_PAUSE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_AMPDU_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_USR_EDCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_EDCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_EDCCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_MUEDCA_PARAM + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_TBPPDU_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_SCH_TXEN_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_HOST_RPR + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_MUEDCA_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_DELAYTX_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_BW_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_BT_BLOCK_TX + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_LIFETIME_CFG + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_EN_BB_RF + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_APP_FCS + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_RX_ICVERR + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_CCTL_RTY_LMT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_COEX_GNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_SCOREBOARD + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_POLLUTED + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_COEX_CTRL + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_CLR_TX_CNT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_SLOT_TIME + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_XTAL_AAC_MODE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_NAV_PADDING + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_MAX_TX_TIME + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_SS_QUOTA_MODE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_SS_QUOTA_SETTING + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_TX_RU26_TB + * To enable or disable responding TB in RU26 + * @var mac_ax_hw_id::MAC_AX_HW_SET_BACAM_MODE_SEL + * To change the BACAM option mode + * @var mac_ax_hw_id::MAC_AX_HW_SET_CORE_SWR_VOLT + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_PARTIAL_PLD_MODE + * Please Place Description here. + * @var mac_ax_hw_id::MAC_AX_HW_SET_RRSR_CFG + * for Response rate cfg + * @var mac_ax_hw_id::MAC_AX_HW_SET_CTS_RRSR_CFG + * for CTS Response rate cfg + */ +enum mac_ax_hw_id { + /* Get HW value */ + MAC_AX_HW_MAPPING = 0x00, + MAC_AX_HW_SDIO_MON_INT, + MAC_AX_HW_SDIO_MON_CNT, + MAC_AX_HW_GET_ID_PAUSE, + MAC_AX_HW_SDIO_TX_AGG_SIZE, + MAC_AX_HW_GET_EDCA_PARAM, + MAC_AX_HW_GET_TBPPDU_CTRL, + MAC_AX_HW_GET_SCH_TXEN_STATUS, + MAC_AX_HW_GET_DELAYTX_CFG, + MAC_AX_HW_GET_SS_WMM_TBL, + MAC_AX_HW_GET_EFUSE_SIZE, + MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE, + MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE, + MAC_AX_HW_GET_BT_EFUSE_SIZE, + MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE, + MAC_AX_HW_GET_EFUSE_MASK_SIZE, + MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE, + MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE, + MAC_AX_HW_GET_EFUSE_VERSION_SIZE, + MAC_AX_HW_GET_CH_STAT_CNT, + MAC_AX_HW_GET_LIFETIME_CFG, + MAC_AX_HW_GET_APP_FCS, + MAC_AX_HW_GET_RX_ICVERR, + MAC_AX_HW_GET_PWR_STATE, + MAC_AX_HW_GET_WAKE_REASON, + MAC_AX_HW_GET_SCOREBOARD, + MAC_AX_HW_GET_COEX_GNT, + MAC_AX_HW_GET_COEX_CTRL, + MAC_AX_HW_GET_TX_CNT, + MAC_AX_HW_GET_TSF, + MAC_AX_HW_GET_MAX_TX_TIME, + MAC_AX_HW_GET_POLLUTED_CNT, + MAC_AX_HW_GET_DATA_RTY_LMT, + MAC_AX_HW_GET_DFLT_NAV, + MAC_AX_HW_GET_SCHE_PREBKF, + MAC_AX_HW_GET_FW_CAP, + MAC_AX_HW_GET_BACAM_MODE_SEL, + MAC_AX_HW_GET_RRSR_CFG, + MAC_AX_HW_GET_CTS_RRSR_CFG, + MAC_AX_HW_GET_USB_STS, + /* Set HW value */ + MAC_AX_HW_SETTING = 0x60, + MAC_AX_HW_SDIO_INFO, + MAC_AX_HW_SDIO_TX_MODE, + MAC_AX_HW_SDIO_RX_AGG, + MAC_AX_HW_SDIO_TX_AGG, + MAC_AX_HW_SDIO_AVAL_PAGE, + MAC_AX_HW_SDIO_MON_WT, + MAC_AX_HW_SDIO_MON_CLK, + MAC_AX_HW_PCIE_CFGSPC_SET, + MAC_AX_HW_PCIE_RST_BDRAM, + MAX_AX_HW_PCIE_LTR_SW_TRIGGER, + MAX_AX_HW_PCIE_MIT, + MAX_AX_HW_PCIE_L2_LEAVE, + MAC_AX_HW_SET_ID_PAUSE, + MAC_AX_HW_SET_MULTI_ID_PAUSE, + MAC_AX_HW_SET_AMPDU_CFG, + MAC_AX_HW_SET_USR_EDCA_PARAM, + MAC_AX_HW_SET_USR_TX_RPT_CFG, + MAC_AX_HW_SET_EDCA_PARAM, + MAC_AX_HW_SET_EDCCA_PARAM, + MAC_AX_HW_SET_MUEDCA_PARAM, + MAC_AX_HW_SET_TBPPDU_CTRL, + MAC_AX_HW_SET_SCH_TXEN_CFG, + MAC_AX_HW_SET_HOST_RPR, + MAC_AX_HW_SET_MUEDCA_CTRL, + MAC_AX_HW_SET_DELAYTX_CFG, + MAC_AX_HW_SET_BW_CFG, + MAC_AX_HW_SET_CH_BUSY_STAT_CFG, + MAC_AX_HW_SET_LIFETIME_CFG, + MAC_AX_HW_EN_BB_RF, + MAC_AX_HW_SET_APP_FCS, + MAC_AX_HW_SET_RX_ICVERR, + MAC_AX_HW_SET_CCTL_RTY_LMT, + MAC_AX_HW_SET_COEX_GNT, + MAC_AX_HW_SET_SCOREBOARD, + MAC_AX_HW_SET_POLLUTED, + MAC_AX_HW_SET_COEX_CTRL, + MAC_AX_HW_SET_CLR_TX_CNT, + MAC_AX_HW_SET_SLOT_TIME, + MAC_AX_HW_SET_XTAL_AAC_MODE, + MAC_AX_HW_SET_NAV_PADDING, + MAC_AX_HW_SET_MAX_TX_TIME, + MAC_AX_HW_SET_SS_QUOTA_MODE, + MAC_AX_HW_SET_SS_QUOTA_SETTING, + MAC_AX_HW_SET_SCHE_PREBKF, + MAC_AX_HW_SET_WDT_ISR_RST, + MAC_AX_HW_SET_RESP_ACK, + MAC_AX_HW_SET_HW_RTS_TH, + MAC_AX_HW_SET_TX_RU26_TB, + MAC_AX_HW_SET_BACAM_MODE_SEL, + MAC_AX_HW_SET_CORE_SWR_VOLT, + MAC_AX_HW_SET_PARTIAL_PLD_MODE, + MAC_AX_HW_SET_RRSR_CFG, + MAC_AX_HW_SET_CTS_RRSR_CFG, + MAC_AX_HW_SET_GT3_TIMER, +}; + +/** + * @enum mac_ax_rx_agg_mode + * + * @brief mac_ax_rx_agg_mode + * + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_NONE + * Please Place Description here. + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_DMA + * Please Place Description here. + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_USB + * Please Place Description here. + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_LAST + * Please Place Description here. + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_MAX + * Please Place Description here. + * @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_rx_agg_mode { + MAC_AX_RX_AGG_MODE_NONE, + MAC_AX_RX_AGG_MODE_DMA, + MAC_AX_RX_AGG_MODE_USB, + + /* keep last */ + MAC_AX_RX_AGG_MODE_LAST, + MAC_AX_RX_AGG_MODE_MAX = MAC_AX_RX_AGG_MODE_LAST, + MAC_AX_RX_AGG_MODE_INVALID = MAC_AX_RX_AGG_MODE_LAST, +}; + +/** + * @enum mac_ax_usr_tx_rpt_mode + * + * @brief mac_ax_usr_tx_rpt_mode + * + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_DIS + * disable report + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_PERIOD + * period mode + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_LAST_PKT + * report after last packet Tx + */ +enum mac_ax_usr_tx_rpt_mode { + MAC_AX_USR_TX_RPT_DIS = 0, + MAC_AX_USR_TX_RPT_PERIOD = 1, + MAC_AX_USR_TX_RPT_LAST_PKT = 2, +}; + +/** + * @enum mac_ax_usr_tx_rpt_mode + * + * @brief mac_ax_usr_tx_rpt_mode + * + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_DIS + * disable report + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_PERIOD + * period mode + * @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_LAST_PKT + * report after last packet Tx + */ +enum mac_ax_ofld_mode { + MAC_AX_OFLD_MODE_DU_DIS = 0, + MAC_AX_OFLD_MODE_DU_VAL = 1, +}; + +/** + * @enum mac_ax_cmac_ac_sel + * + * @brief mac_ax_cmac_ac_sel + * + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_BE + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_BK + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_VI + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_VO + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_LAST + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_MAX + * Please Place Description here. + * @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_cmac_ac_sel { + MAC_AX_CMAC_AC_SEL_BE = 0, + MAC_AX_CMAC_AC_SEL_BK = 1, + MAC_AX_CMAC_AC_SEL_VI = 2, + MAC_AX_CMAC_AC_SEL_VO = 3, + + /* keep last */ + MAC_AX_CMAC_AC_SEL_LAST, + MAC_AX_CMAC_AC_SEL_MAX = MAC_AX_CMAC_AC_SEL_LAST, + MAC_AX_CMAC_AC_SEL_INVALID = MAC_AX_CMAC_AC_SEL_LAST, +}; + +/** + * @enum mac_ax_cmac_path_sel + * + * @brief mac_ax_cmac_path_sel + * + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BE0 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BK0 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VI0 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VO0 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BE1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BK1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VI1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VO1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MG0_1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MG2 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BCN + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TF + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TWT0 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TWT1 + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_LAST + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MAX + * Please Place Description here. + * @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_cmac_path_sel { + MAC_AX_CMAC_PATH_SEL_BE0, + MAC_AX_CMAC_PATH_SEL_BK0, + MAC_AX_CMAC_PATH_SEL_VI0, + MAC_AX_CMAC_PATH_SEL_VO0, + MAC_AX_CMAC_PATH_SEL_BE1, + MAC_AX_CMAC_PATH_SEL_BK1, + MAC_AX_CMAC_PATH_SEL_VI1, + MAC_AX_CMAC_PATH_SEL_VO1, + MAC_AX_CMAC_PATH_SEL_MG0_1, + MAC_AX_CMAC_PATH_SEL_MG2, + MAC_AX_CMAC_PATH_SEL_BCN, + MAC_AX_CMAC_PATH_SEL_TF, + MAC_AX_CMAC_PATH_SEL_TWT0, + MAC_AX_CMAC_PATH_SEL_TWT1, + + /* keep last */ + MAC_AX_CMAC_PATH_SEL_LAST, + MAC_AX_CMAC_PATH_SEL_MAX = MAC_AX_CMAC_PATH_SEL_LAST, + MAC_AX_CMAC_PATH_SEL_INVALID = MAC_AX_CMAC_PATH_SEL_LAST, +}; + +/** + * @enum mac_ax_cmac_usr_edca_idx + * + * @brief mac_ax_cmac_usr_edca_idx + * + * @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_0 + * Please Place Description here. + * @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_1 + * Please Place Description here. + * @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_2 + * Please Place Description here. + * @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_3 + * Please Place Description here. + */ +enum mac_ax_cmac_usr_edca_idx { + MAC_AX_CMAC_USR_EDCA_IDX_0 = 0, + MAC_AX_CMAC_USR_EDCA_IDX_1 = 1, + MAC_AX_CMAC_USR_EDCA_IDX_2 = 2, + MAC_AX_CMAC_USR_EDCA_IDX_3 = 3, +}; + +/** + * @enum mac_ax_cmac_wmm_sel + * + * @brief mac_ax_cmac_wmm_sel + * + * @var mac_ax_cmac_wmm_sel::MAC_AX_CMAC_WMM0_SEL + * Please Place Description here. + * @var mac_ax_cmac_wmm_sel::MAC_AX_CMAC_WMM1_SEL + * Please Place Description here. + */ +enum mac_ax_cmac_wmm_sel { + MAC_AX_CMAC_WMM0_SEL = 0, + MAC_AX_CMAC_WMM1_SEL = 1, +}; + +/** + * @enum mac_ax_ss_wmm_tbl + * + * @brief mac_ax_ss_wmm_tbl + * + * @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C0_WMM0 + * Please Place Description here. + * @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C0_WMM1 + * Please Place Description here. + * @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C1_WMM0 + * Please Place Description here. + * @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C1_WMM1 + * Please Place Description here. + */ +enum mac_ax_ss_wmm_tbl { + MAC_AX_SS_WMM_TBL_C0_WMM0 = 0, + MAC_AX_SS_WMM_TBL_C0_WMM1 = 1, + MAC_AX_SS_WMM_TBL_C1_WMM0 = 2, + MAC_AX_SS_WMM_TBL_C1_WMM1 = 3, +}; + +enum mac_ax_tx_idle_poll_sel { + MAC_AX_TX_IDLE_POLL_SEL_BAND, +}; + +/** + * @enum mac_ax_mcc_status + * + * @brief mac_ax_mcc_status + * + * @var mac_ax_mcc_status::MAC_AX_MCC_ADD_ROLE_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_START_GROUP_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_STOP_GROUP_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_DEL_GROUP_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_RESET_GROUP_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_CH_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL0_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL1_OK + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_EARLY + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_TBTT + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_DURATION_START + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_DURATION_END + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_ADD_ROLE_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_START_GROUP_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_STOP_GROUP_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_DEL_GROUP_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_RESET_GROUP_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_CH_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL0_FAIL + * Please Place Description here. + * @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL1_FAIL + * Please Place Description here. + */ +enum mac_ax_mcc_status { + MAC_AX_MCC_ADD_ROLE_OK = 0, + MAC_AX_MCC_START_GROUP_OK = 1, + MAC_AX_MCC_STOP_GROUP_OK = 2, + MAC_AX_MCC_DEL_GROUP_OK = 3, + MAC_AX_MCC_RESET_GROUP_OK = 4, + MAC_AX_MCC_SWITCH_CH_OK = 5, + MAC_AX_MCC_TXNULL0_OK = 6, + MAC_AX_MCC_TXNULL1_OK = 7, + + MAC_AX_MCC_SWITCH_EARLY = 10, + MAC_AX_MCC_TBTT = 11, + MAC_AX_MCC_DURATION_START = 12, + MAC_AX_MCC_DURATION_END = 13, + + MAC_AX_MCC_ADD_ROLE_FAIL = 20, + MAC_AX_MCC_START_GROUP_FAIL = 21, + MAC_AX_MCC_STOP_GROUP_FAIL = 22, + MAC_AX_MCC_DEL_GROUP_FAIL = 23, + MAC_AX_MCC_RESET_GROUP_FAIL = 24, + MAC_AX_MCC_SWITCH_CH_FAIL = 25, + MAC_AX_MCC_TXNULL0_FAIL = 26, + MAC_AX_MCC_TXNULL1_FAIL = 27, +}; + +/** + * @enum mac_ax_trx_mitigation_timer_unit + * + * @brief mac_ax_trx_mitigation_timer_unit + * + * @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_64US + * Please Place Description here. + * @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_128US + * Please Place Description here. + * @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_256US + * Please Place Description here. + * @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_512US + * Please Place Description here. + */ +enum mac_ax_trx_mitigation_timer_unit { + MAC_AX_MIT_64US, + MAC_AX_MIT_128US, + MAC_AX_MIT_256US, + MAC_AX_MIT_512US +}; + +/** + * @enum mac_ax_wow_wake_reason + * + * @brief mac_ax_wow_wake_reason + * + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_PAIRWISEKEY + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_GTK + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_FOURWAY_HANDSHAKE + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DISASSOC + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DEAUTH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_ARP_REQUEST + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_NS + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_EAPREQ_IDENTIFY + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_FW_DECISION_DISCONNECT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_MAGIC_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_UNICAST_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_PATTERN_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTD3_SSID_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DATA_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SSDP_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_WSD_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SLP_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_LLTD_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_MDNS_MATCH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_WAKEUP_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_ACK_LOST + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_TX_KAPKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_ENABLE_FAIL_DMA_IDLE + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_ENABLE_FAIL_DMA_PAUSE + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTIME_FAIL_DMA_IDLE + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTIME_FAIL_DMA_PAUSE + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SNMP_MISMATCHED_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DESIGNATED_MAC_PKT + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_NLO_SSID_MACH + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_AP_OFFLOAD_WAKEUP + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_DMAC_ERROR_OCCURRED + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_EXCEPTION_OCCURRED + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_CLK_32K_UNLOCK + * Please Place Description here. + * @var mac_ax_wow_wake_reason::MAC_AX_WOW_CLK_32K_LOCK + * Please Place Description here. + */ +enum mac_ax_wow_wake_reason { + MAC_AX_WOW_RX_PAIRWISEKEY = 0x01, + MAC_AX_WOW_RX_GTK = 0x02, + MAC_AX_WOW_RX_FOURWAY_HANDSHAKE = 0x03, + MAC_AX_WOW_RX_DISASSOC = 0x04, + MAC_AX_WOW_RX_DEAUTH = 0x08, + MAC_AX_WOW_RX_ARP_REQUEST = 0x09, + MAC_AX_WOW_RX_NS = 0x0A, + MAC_AX_WOW_RX_EAPREQ_IDENTIFY = 0x0B, + MAC_AX_WOW_FW_DECISION_DISCONNECT = 0x10, + MAC_AX_WOW_RX_MAGIC_PKT = 0x21, + MAC_AX_WOW_RX_UNICAST_PKT = 0x22, + MAC_AX_WOW_RX_PATTERN_PKT = 0x23, + MAC_AX_WOW_RTD3_SSID_MATCH = 0x24, + MAC_AX_WOW_RX_DATA_PKT = 0x25, + MAC_AX_WOW_RX_SSDP_MATCH = 0x26, + MAC_AX_WOW_RX_WSD_MATCH = 0x27, + MAC_AX_WOW_RX_SLP_MATCH = 0x28, + MAC_AX_WOW_RX_LLTD_MATCH = 0x29, + MAC_AX_WOW_RX_MDNS_MATCH = 0x2A, + MAC_AX_WOW_RX_REALWOW_V2_WAKEUP_PKT = 0x30, + MAC_AX_WOW_RX_REALWOW_V2_ACK_LOST = 0x31, + MAC_AX_WOW_RX_REALWOW_V2_TX_KAPKT = 0x32, + MAC_AX_WOW_ENABLE_FAIL_DMA_IDLE = 0x40, + MAC_AX_WOW_ENABLE_FAIL_DMA_PAUSE = 0x41, + MAC_AX_WOW_RTIME_FAIL_DMA_IDLE = 0x42, + MAC_AX_WOW_RTIME_FAIL_DMA_PAUSE = 0x43, + MAC_AX_WOW_RX_SNMP_MISMATCHED_PKT = 0x50, + MAC_AX_WOW_RX_DESIGNATED_MAC_PKT = 0x51, + MAC_AX_WOW_NLO_SSID_MACH = 0x55, + MAC_AX_WOW_AP_OFFLOAD_WAKEUP = 0x66, + MAC_AX_WOW_DMAC_ERROR_OCCURRED = 0x70, + MAC_AX_WOW_EXCEPTION_OCCURRED = 0x71, + MAC_AX_WOW_L0_TO_L1_ERROR_OCCURRED = 0x72, + MAC_AX_WOW_ASSERT_OCCURRED = 0x73, + MAC_AX_WOW_L2_ERROR_OCCURRED = 0x74, + MAC_AX_WOW_WDT_TIMEOUT_WAKE = 0x75, + MAC_AX_WOW_RX_ACTION = 0xD0, + MAC_AX_WOW_CLK_32K_UNLOCK = 0xFD, + MAC_AX_WOW_CLK_32K_LOCK = 0xFE +}; + +/** + * @enum mac_ax_wow_fw_status + * + * @brief mac_ax_wow_fw_status + * + * @var mac_ax_wow_fw_status::MAC_AX_WOW_NOT_READY + * Please Place Description here. + * @var mac_ax_wow_fw_status::MAC_AX_WOW_SLEEP + * Please Place Description here. + * @var mac_ax_wow_fw_status::MAC_AX_WOW_RESUME + * Please Place Description here. + */ +enum mac_ax_wow_fw_status { + MAC_AX_WOW_NOT_READY, + MAC_AX_WOW_SLEEP, + MAC_AX_WOW_RESUME +}; + +/** + * @enum mac_ax_wow_ctrl + * + * @brief mac_ax_wow_ctrl + * + * @var mac_ax_wow_ctrl::MAC_AX_WOW_ENTER + * Please Place Description here. + * @var mac_ax_wow_ctrl::MAC_AX_WOW_LEAVE + * Please Place Description here. + */ +enum mac_ax_wow_ctrl { + MAC_AX_WOW_ENTER, + MAC_AX_WOW_LEAVE +}; + +/** + * @enum mac_ax_mac_pwr_st + * + * @brief mac_ax_mac_pwr_st + * + * @var mac_ax_mac_pwr_st::MAC_AX_MAC_OFF + * Please Place Description here. + * @var mac_ax_mac_pwr_st::MAC_AX_MAC_ON + * Please Place Description here. + * @var mac_ax_mac_pwr_st::MAC_AX_MAC_LPS + * Please Place Description here. + */ +enum mac_ax_mac_pwr_st { + MAC_AX_MAC_OFF = 0, + MAC_AX_MAC_ON = 1, + MAC_AX_MAC_LPS = 2 +}; + +/** + * @enum mac_ax_core_swr_volt + * + * @brief mac_ax_core_swr_volt + * + * @var mac_ax_core_swr_volt::MAC_AX_SWR_LOW + * Please Place Description here. + * @var mac_ax_core_swr_volt::MAC_AX_SWR_NORM + * Please Place Description here. + * @var mac_ax_core_swr_volt::MAC_AX_SWR_HIGH + * Please Place Description here. + */ +enum mac_ax_core_swr_volt { + MAC_AX_SWR_LOW = 0, + MAC_AX_SWR_NORM = 3, + MAC_AX_SWR_HIGH = 6 +}; + +/*--------------------Define DBG and recovery related enum--------------------*/ + +/** + * @enum mac_ax_err_info + * + * @brief mac_ax_err_info + * + * @var mac_ax_err_info::MAC_AX_ERR_L0_ERR_CMAC0 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_ERR_CMAC1 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_RESET_DONE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_PROMOTE_TO_L1 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_ERR_DMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_RESET_RECOVERY_DONE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_PROMOTE_TO_L2 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_DMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_HCI + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_RLX4081 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_RX4281 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_DMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_HCI + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L2_RESET_DONE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_GET_ERR_MAX + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_DISABLE_EN + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L1_RCVY_EN + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_NOTIFY + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_DIS_NOTIFY + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_HANDSHAKE + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_ERR_L0_RCVY_EN + * Please Place Description here. + * @var mac_ax_err_info::MAC_AX_SET_ERR_MAX + * Please Place Description here. + */ +enum mac_ax_err_info { + // Get error info + // L0 + MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, + MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, + MAC_AX_ERR_L0_RESET_DONE = 0x0003, + MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, + // L1 + MAC_AX_ERR_L1_ERR_DMAC = 0x1000, + MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, + MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, + MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, + MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, + // L2 + // address hole (master) + MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, + MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, + MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, + MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, + MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, + MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, + MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, + MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, + // AHB bridge timeout (master) + MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, + MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, + MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, + MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, + MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, + MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, + MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, + MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, + // APB_SA bridge timeout (master + slave) + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, + MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, + MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, + MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, + MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, + MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, + // APB_BBRF bridge timeout (master) + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, + MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, + MAC_AX_ERR_L2_RESET_DONE = 0x2400, + MAC_AX_ERR_CPU_EXCEPTION = 0x3000, + MAC_AX_ERR_ASSERTION = 0x4000, + MAC_AX_GET_ERR_MAX, + //Use the special code to indicate phl should dump share buffer + MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, + // set error info + MAC_AX_ERR_L1_DISABLE_EN = 0x0001, + MAC_AX_ERR_L1_RCVY_EN = 0x0002, + MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, + MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, + MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, + MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, + MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, + MAC_AX_ERR_L0_RCVY_EN = 0x0013, + MAC_AX_SET_ERR_MAX, +}; + +/** + * @enum mac_ax_mem_sel + * + * @brief mac_ax_mem_sel + * + * @var mac_ax_mem_sel::MAC_AX_MEM_AXIDMA + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_SHARED_BUF + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_DMAC_TBL + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_SHCUT_MACHDR + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_STA_SCHED + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_RXPLD_FLTR_CAM + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_SECURITY_CAM + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_WOW_CAM + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_CMAC_TBL + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_ADDR_CAM + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_BA_CAM + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_BCN_IE_CAM0 + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_BCN_IE_CAM1 + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_TXD_FIFO_0 + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_TXD_FIFO_1 + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_LAST + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_MAX + * Please Place Description here. + * @var mac_ax_mem_sel::MAC_AX_MEM_INVALID + * Please Place Description here. + */ +enum mac_ax_mem_sel { + MAC_AX_MEM_CPU_LOCAL, + MAC_AX_MEM_AXIDMA, + MAC_AX_MEM_SHARED_BUF, + MAC_AX_MEM_DMAC_TBL, + MAC_AX_MEM_SHCUT_MACHDR, + MAC_AX_MEM_STA_SCHED, + MAC_AX_MEM_RXPLD_FLTR_CAM, + MAC_AX_MEM_SECURITY_CAM, + MAC_AX_MEM_WOW_CAM, + MAC_AX_MEM_CMAC_TBL, + MAC_AX_MEM_ADDR_CAM, + MAC_AX_MEM_BA_CAM, + MAC_AX_MEM_BCN_IE_CAM0, + MAC_AX_MEM_BCN_IE_CAM1, + MAC_AX_MEM_TXD_FIFO_0, + MAC_AX_MEM_TXD_FIFO_1, + + /* keep last */ + MAC_AX_MEM_LAST, + MAC_AX_MEM_MAX = MAC_AX_MEM_LAST, + MAC_AX_MEM_INVALID = MAC_AX_MEM_LAST, +}; + +/** + * @enum mac_ax_reg_sel + * + * @brief mac_ax_reg_sel + * + * @var mac_ax_reg_sel::MAC_AX_REG_MAC + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_BB + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_IQK + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_RFC + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_LAST + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_MAX + * Please Place Description here. + * @var mac_ax_reg_sel::MAC_AX_REG_INVALID + * Please Place Description here. + */ +enum mac_ax_reg_sel { + MAC_AX_REG_MAC, + MAC_AX_REG_BB, + MAC_AX_REG_IQK, + MAC_AX_REG_RFC, + + /* keep last */ + MAC_AX_REG_LAST, + MAC_AX_REG_MAX = MAC_AX_REG_LAST, + MAC_AX_REG_INVALID = MAC_AX_REG_LAST, +}; + +/*--------------------Define GPIO related enum-------------------------------*/ + +/** + * @enum mac_ax_gpio_func + * + * @brief mac_ax_gpio_func + * + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_0 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_1 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_2 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_3 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_4 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_5 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_6 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_7 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_8 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_9 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_10 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_11 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_12 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_13 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_14 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_15 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO5 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO7 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO8 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_UART_RX_GPIO6 + * Please Place Description here. + * @var mac_ax_gpio_func::MAC_AX_GPIO_UART_RX_GPIO14 + * Please Place Description here. + */ +enum mac_ax_gpio_func { + MAC_AX_GPIO_SW_IO_0, + MAC_AX_GPIO_SW_IO_1, + MAC_AX_GPIO_SW_IO_2, + MAC_AX_GPIO_SW_IO_3, + MAC_AX_GPIO_SW_IO_4, + MAC_AX_GPIO_SW_IO_5, + MAC_AX_GPIO_SW_IO_6, + MAC_AX_GPIO_SW_IO_7, + MAC_AX_GPIO_SW_IO_8, + MAC_AX_GPIO_SW_IO_9, + MAC_AX_GPIO_SW_IO_10, + MAC_AX_GPIO_SW_IO_11, + MAC_AX_GPIO_SW_IO_12, + MAC_AX_GPIO_SW_IO_13, + MAC_AX_GPIO_SW_IO_14, + MAC_AX_GPIO_SW_IO_15, + MAC_AX_GPIO_UART_TX_GPIO5, + MAC_AX_GPIO_UART_TX_GPIO7, + MAC_AX_GPIO_UART_TX_GPIO8, + MAC_AX_GPIO_UART_RX_GPIO6, + MAC_AX_GPIO_UART_RX_GPIO14, +}; + +/** + * @enum mac_ax_uart_tx_pin + * + * @brief mac_ax_uart_tx_pin + * + * @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO5 + * Please Place Description here. + * @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO7 + * Please Place Description here. + * @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO8 + * Please Place Description here. + * @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO5_GPIO8 + * Please Place Description here. + */ +enum mac_ax_uart_tx_pin { + MAC_AX_UART_TX_GPIO5, + MAC_AX_UART_TX_GPIO7, + MAC_AX_UART_TX_GPIO8, + MAC_AX_UART_TX_GPIO5_GPIO8, +}; + +/** + * @enum mac_ax_uart_rx_pin + * + * @brief mac_ax_uart_rx_pin + * + * @var mac_ax_uart_rx_pin::MAC_AX_UART_RX_GPIO6 + * Please Place Description here. + * @var mac_ax_uart_rx_pin::MAC_AX_UART_RX_GPIO14 + * Please Place Description here. + */ +enum mac_ax_uart_rx_pin { + MAC_AX_UART_RX_GPIO6, + MAC_AX_UART_RX_GPIO14, +}; + +/** + * @enum mac_ax_led_mode + * + * @brief mac_ax_led_mode + * + * @var mac_ax_led_mode::MAC_AX_LED_MODE_TRX_ON + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_TX_ON + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_RX_ON + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_SW_CTRL_OD + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_SW_CTRL_PP + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_LAST + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_MAX + * Please Place Description here. + * @var mac_ax_led_mode::MAC_AX_LED_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_led_mode { + MAC_AX_LED_MODE_TRX_ON, + MAC_AX_LED_MODE_TX_ON, + MAC_AX_LED_MODE_RX_ON, + MAC_AX_LED_MODE_SW_CTRL_OD, + MAC_AX_LED_MODE_SW_CTRL_PP, + + /* keep last */ + MAC_AX_LED_MODE_LAST, + MAC_AX_LED_MODE_MAX = MAC_AX_LED_MODE_LAST, + MAC_AX_LED_MODE_INVALID = MAC_AX_LED_MODE_LAST, +}; + +/** + * @enum mac_ax_sw_io_mode + * + * @brief mac_ax_sw_io_mode + * + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_INPUT + * Please Place Description here. + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_OUTPUT_OD + * Please Place Description here. + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_OUTPUT_PP + * Please Place Description here. + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_LAST + * Please Place Description here. + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_MAX + * Please Place Description here. + * @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_sw_io_mode { + MAC_AX_SW_IO_MODE_INPUT, + MAC_AX_SW_IO_MODE_OUTPUT_OD, + MAC_AX_SW_IO_MODE_OUTPUT_PP, + + /* keep last */ + MAC_AX_SW_IO_MODE_LAST, + MAC_AX_SW_IO_MODE_MAX = MAC_AX_SW_IO_MODE_LAST, + MAC_AX_SW_IO_MODE_INVALID = MAC_AX_SW_IO_MODE_LAST, +}; + +/*--------------------Define Efuse related enum-------------------------------*/ + +/** + * @enum mac_ax_efuse_read_cfg + * + * @brief mac_ax_efuse_read_cfg + * + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_AUTO + * Please Place Description here. + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_DRV + * Please Place Description here. + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_FW + * Please Place Description here. + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_LAST + * Please Place Description here. + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_MAX + * Please Place Description here. + * @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_INVALID + * Please Place Description here. + */ +enum mac_ax_efuse_read_cfg { + MAC_AX_EFUSE_R_AUTO, + MAC_AX_EFUSE_R_DRV, + MAC_AX_EFUSE_R_FW, + + /* keep last */ + MAC_AX_EFUSE_R_LAST, + MAC_AX_EFUSE_R_MAX = MAC_AX_EFUSE_R_LAST, + MAC_AX_EFUSE_R_INVALID = MAC_AX_EFUSE_R_LAST, +}; + +/** + * @enum mac_ax_efuse_bank + * + * @brief mac_ax_efuse_bank + * + * @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_WIFI + * Please Place Description here. + * @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_BT + * Please Place Description here. + * @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_LAST + * Please Place Description here. + * @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_MAX + * Please Place Description here. + * @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_INVALID + * Please Place Description here. + */ +enum mac_ax_efuse_bank { + MAC_AX_EFUSE_BANK_WIFI, + MAC_AX_EFUSE_BANK_BT, + + /* keep last */ + MAC_AX_EFUSE_BANK_LAST, + MAC_AX_EFUSE_BANK_MAX = MAC_AX_EFUSE_BANK_LAST, + MAC_AX_EFUSE_BANK_INVALID = MAC_AX_EFUSE_BANK_LAST, +}; + +/** + * @enum mac_ax_efuse_parser_cfg + * + * @brief mac_ax_efuse_parser_cfg + * + * @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MAP + * Please Place Description here. + * @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MASK + * Please Place Description here. + * @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_LAST + * Please Place Description here. + * @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MAX + * Please Place Description here. + * @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_INVALID + * Please Place Description here. + */ +enum mac_ax_efuse_parser_cfg { + MAC_AX_EFUSE_PARSER_MAP, + MAC_AX_EFUSE_PARSER_MASK, + + /* keep last */ + MAC_AX_EFUSE_PARSER_LAST, + MAC_AX_EFUSE_PARSER_MAX = MAC_AX_EFUSE_PARSER_LAST, + MAC_AX_EFUSE_PARSER_INVALID = MAC_AX_EFUSE_PARSER_LAST, +}; + +/** + * @enum mac_ax_efuse_feature_id + * + * @brief mac_ax_efuse_feature_id + * + * @var mac_ax_efuse_feature_id::MAC_AX_DUMP_PHYSICAL_EFUSE + * Please Place Description here. + * @var mac_ax_efuse_feature_id::MAC_AX_DUMP_LOGICAL_EFUSE + * Please Place Description here. + * @var mac_ax_efuse_feature_id::MAC_AX_DUMP_LOGICAL_EFUSE_MASK + * Please Place Description here. + */ +enum mac_ax_efuse_feature_id { + MAC_AX_DUMP_PHYSICAL_EFUSE, /* Support */ + MAC_AX_DUMP_LOGICAL_EFUSE, /* Support */ + MAC_AX_DUMP_LOGICAL_EFUSE_MASK, /* Support */ +}; + +/*--------------------Define TRX PKT INFO/RPT related enum--------------------*/ + +/** + * @enum mac_ax_trx_mode + * + * @brief mac_ax_trx_mode + * + * @var mac_ax_trx_mode::MAC_AX_TRX_SW_MODE + * Please Place Description here. + * @var mac_ax_trx_mode::MAC_AX_TRX_HW_MODE + * Please Place Description here. + * @var mac_ax_trx_mode::MAC_AX_TRX_LOOPBACK + * Please Place Description here. + * @var mac_ax_trx_mode::MAC_AX_TRX_LAST + * Please Place Description here. + * @var mac_ax_trx_mode::MAC_AX_TRX_MAX + * Please Place Description here. + * @var mac_ax_trx_mode::MAC_AX_TRX_INVALID + * Please Place Description here. + */ +enum mac_ax_trx_mode { + MAC_AX_TRX_SW_MODE, + MAC_AX_TRX_HW_MODE, + MAC_AX_TRX_LOOPBACK, + + MAC_AX_TRX_NORMAL, /* shall remove when v0_22 release, Rick */ + + /* keep last */ + MAC_AX_TRX_LAST, + MAC_AX_TRX_MAX = MAC_AX_TRX_LAST, + MAC_AX_TRX_INVALID = MAC_AX_TRX_LAST, +}; + +/** + * @enum mac_ax_qta_mode + * + * @brief mac_ax_qta_mode + * + * @var mac_ax_qta_mode::MAC_AX_QTA_SCC + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_DBCC + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_SCC_STF + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_DBCC_STF + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_SU_TP + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_DLFW + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_BCN_TEST + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_LAMODE + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_LAST + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_MAX + * Please Place Description here. + * @var mac_ax_qta_mode::MAC_AX_QTA_INVALID + * Please Place Description here. + */ +enum mac_ax_qta_mode { + MAC_AX_QTA_SCC, + MAC_AX_QTA_DBCC, + MAC_AX_QTA_SCC_STF, + MAC_AX_QTA_DBCC_STF, + MAC_AX_QTA_SU_TP, + MAC_AX_QTA_DLFW, + MAC_AX_QTA_BCN_TEST, + MAC_AX_QTA_LAMODE, + + /* keep last */ + MAC_AX_QTA_LAST, + MAC_AX_QTA_MAX = MAC_AX_QTA_LAST, + MAC_AX_QTA_INVALID = MAC_AX_QTA_LAST, +}; + +/** + * @enum mac_ax_pkt_t + * + * @brief mac_ax_pkt_t + * + * @var mac_ax_pkt_t::MAC_AX_PKT_DATA + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_MGNT + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_CTRL + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_8023 + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_H2C + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_FWDL + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_C2H + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_PPDU + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_CH_INFO + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_DFS + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_LAST + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_MAX + * Please Place Description here. + * @var mac_ax_pkt_t::MAC_AX_PKT_INVALID + * Please Place Description here. + */ +enum mac_ax_pkt_t { + MAC_AX_PKT_DATA, + MAC_AX_PKT_MGNT, + MAC_AX_PKT_CTRL, + MAC_AX_PKT_8023, + MAC_AX_PKT_H2C, + MAC_AX_PKT_FWDL, + MAC_AX_PKT_C2H, + MAC_AX_PKT_PPDU, + MAC_AX_PKT_CH_INFO, + MAC_AX_PKT_DFS, + + /* keep last */ + MAC_AX_PKT_LAST, + MAC_AX_PKT_MAX = MAC_AX_PKT_LAST, + MAC_AX_PKT_INVALID = MAC_AX_PKT_LAST, +}; + +/** + * @enum mac_ax_amsdu_pkt_num + * + * @brief mac_ax_amsdu_pkt_num + * + * @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_1 + * Please Place Description here. + * @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_2 + * Please Place Description here. + * @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_3 + * Please Place Description here. + * @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_4 + * Please Place Description here. + * @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_MAX + * Please Place Description here. + */ +enum mac_ax_amsdu_pkt_num { + MAC_AX_AMSDU_AGG_NUM_1 = 0, + MAC_AX_AMSDU_AGG_NUM_2 = 1, + MAC_AX_AMSDU_AGG_NUM_3 = 2, + MAC_AX_AMSDU_AGG_NUM_4 = 3, + MAC_AX_AMSDU_AGG_NUM_MAX +}; + +/** + * @enum mac_ax_phy_rpt + * + * @brief mac_ax_phy_rpt + * + * @var mac_ax_phy_rpt::MAC_AX_PPDU_STATUS + * Please Place Description here. + * @var mac_ax_phy_rpt::MAC_AX_CH_INFO + * Please Place Description here. + * @var mac_ax_phy_rpt::MAC_AX_DFS + * Please Place Description here. + */ +enum mac_ax_phy_rpt { + MAC_AX_PPDU_STATUS, + MAC_AX_CH_INFO, + MAC_AX_DFS, +}; + +/** + * @enum mac_ax_pkt_drop_sel + * + * @brief mac_ax_pkt_drop_sel + * + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_ALL + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MG0_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_ONCE + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_PORT + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_MBSSID + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_BAND + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_MACID + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_LAST + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MAX + * Please Place Description here. + * @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_pkt_drop_sel { + MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE, + MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE, + MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE, + MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE, + MAC_AX_PKT_DROP_SEL_MACID_ALL, + MAC_AX_PKT_DROP_SEL_MG0_ONCE, + MAC_AX_PKT_DROP_SEL_HIQ_ONCE, + MAC_AX_PKT_DROP_SEL_HIQ_PORT, + MAC_AX_PKT_DROP_SEL_HIQ_MBSSID, + MAC_AX_PKT_DROP_SEL_BAND, + MAC_AX_PKT_DROP_SEL_BAND_ONCE, + MAC_AX_PKT_DROP_SEL_REL_MACID, + MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT, + MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID, + + /* keep last */ + MAC_AX_PKT_DROP_SEL_LAST, + MAC_AX_PKT_DROP_SEL_MAX = MAC_AX_PKT_DROP_SEL_LAST, + MAC_AX_PKT_DROP_SEL_INVALID = MAC_AX_PKT_DROP_SEL_LAST, +}; + +/*need to check and move to other */ + +/** + * @enum mac_ax_fwd_target + * + * @brief mac_ax_fwd_target + * + * @var mac_ax_fwd_target::MAC_AX_FWD_DONT_CARE + * Please Place Description here. + * @var mac_ax_fwd_target::MAC_AX_FWD_TO_HOST + * Please Place Description here. + * @var mac_ax_fwd_target::MAC_AX_FWD_TO_WLAN_CPU + * Please Place Description here. + */ +enum mac_ax_fwd_target { + MAC_AX_FWD_DONT_CARE = 0, + MAC_AX_FWD_TO_HOST = 1, + MAC_AX_FWD_TO_WLAN_CPU = 2 +}; + +/** + * @enum mac_ax_action_frame + * + * @brief mac_ax_action_frame + * + * @var mac_ax_action_frame::MAC_AX_AF_CSA + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_ADDTS_REQ + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_ADDTS_RES + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_DELTS + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_ADDBA_REQ + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_ADDBA_RES + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_DELBA + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_NCW + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_GID_MGNT + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_OP_MODE + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_CSI + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_HT_CBFM + * Please Place Description here. + * @var mac_ax_action_frame::MAC_AX_AF_VHT_CBFM + * Please Place Description here. + */ +enum mac_ax_action_frame { + MAC_AX_AF_CSA = 0, + MAC_AX_AF_ADDTS_REQ = 1, + MAC_AX_AF_ADDTS_RES = 2, + MAC_AX_AF_DELTS = 3, + MAC_AX_AF_ADDBA_REQ = 4, + MAC_AX_AF_ADDBA_RES = 5, + MAC_AX_AF_DELBA = 6, + MAC_AX_AF_NCW = 7, + MAC_AX_AF_GID_MGNT = 8, + MAC_AX_AF_OP_MODE = 9, + MAC_AX_AF_CSI = 10, + MAC_AX_AF_HT_CBFM = 11, + MAC_AX_AF_VHT_CBFM = 12 +}; + +/** + * @enum mac_ax_af_user_define_index + * + * @brief mac_ax_af_user_define_index + * + * @var mac_ax_af_user_define_index::MAC_AX_AF_UD_0 + * Please Place Description here. + * @var mac_ax_af_user_define_index::MAC_AX_AF_UD_1 + * Please Place Description here. + * @var mac_ax_af_user_define_index::MAC_AX_AF_UD_2 + * Please Place Description here. + * @var mac_ax_af_user_define_index::MAC_AX_AF_UD_3 + * Please Place Description here. + */ +enum mac_ax_af_user_define_index { + MAC_AX_AF_UD_0 = 0, + MAC_AX_AF_UD_1 = 1, + MAC_AX_AF_UD_2 = 2, + MAC_AX_AF_UD_3 = 3 +}; + +/** + * @enum mac_ax_trigger_frame + * + * @brief mac_ax_trigger_frame + * + * @var mac_ax_trigger_frame::MAC_AX_TF_BT + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_BFRP + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_MU_BAR + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_MU_RTS + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_BSRP + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_GCR_MU_BAR + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_BQRP + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_NFRP + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF8 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF9 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF10 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF11 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF12 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF13 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF14 + * Please Place Description here. + * @var mac_ax_trigger_frame::MAC_AX_TF_TF15 + * Please Place Description here. + */ +enum mac_ax_trigger_frame { + MAC_AX_TF_BT = 0, + MAC_AX_TF_BFRP = 1, + MAC_AX_TF_MU_BAR = 2, + MAC_AX_TF_MU_RTS = 3, + MAC_AX_TF_BSRP = 4, + MAC_AX_TF_GCR_MU_BAR = 5, + MAC_AX_TF_BQRP = 6, + MAC_AX_TF_NFRP = 7, + MAC_AX_TF_TF8 = 8, + MAC_AX_TF_TF9 = 9, + MAC_AX_TF_TF10 = 10, + MAC_AX_TF_TF11 = 11, + MAC_AX_TF_TF12 = 12, + MAC_AX_TF_TF13 = 13, + MAC_AX_TF_TF14 = 14, + MAC_AX_TF_TF15 = 15 +}; + +/** + * @enum mac_ax_frame_type + * + * @brief mac_ax_frame_type + * + * @var mac_ax_frame_type::MAC_AX_FT_ACTION + * Please Place Description here. + * @var mac_ax_frame_type::MAC_AX_FT_ACTION_UD + * Please Place Description here. + * @var mac_ax_frame_type::MAC_AX_FT_TRIGGER + * Please Place Description here. + * @var mac_ax_frame_type::MAC_AX_FT_PM_CAM + * Please Place Description here. + */ +enum mac_ax_frame_type { + MAC_AX_FT_ACTION = 0, + MAC_AX_FT_ACTION_UD = 1, + MAC_AX_FT_TRIGGER = 2, + MAC_AX_FT_PM_CAM = 3 +}; + +/** + * @enum mac_ax_bd_trunc_mode + * + * @brief mac_ax_bd_trunc_mode + * + * @var mac_ax_bd_trunc_mode::MAC_AX_BD_NORM + * Please Place Description here. + * @var mac_ax_bd_trunc_mode::MAC_AX_BD_TRUNC + * Please Place Description here. + * @var mac_ax_bd_trunc_mode::MAC_AX_BD_DEF + * Please Place Description here. + */ +enum mac_ax_bd_trunc_mode { + MAC_AX_BD_NORM, + MAC_AX_BD_TRUNC, + MAC_AX_BD_DEF = 0xFE +}; + +/** + * @enum mac_ax_rxbd_mode + * + * @brief mac_ax_rxbd_mode + * + * @var mac_ax_rxbd_mode::MAC_AX_RXBD_PKT + * Please Place Description here. + * @var mac_ax_rxbd_mode::MAC_AX_RXBD_SEP + * Please Place Description here. + * @var mac_ax_rxbd_mode::MAC_AX_RXBD_DEF + * Please Place Description here. + */ +enum mac_ax_rxbd_mode { + MAC_AX_RXBD_PKT, + MAC_AX_RXBD_SEP, + MAC_AX_RXBD_DEF = 0xFE +}; + +/** + * @enum mac_ax_tag_mode + * + * @brief mac_ax_tag_mode + * + * @var mac_ax_tag_mode::MAC_AX_TAG_SGL + * Please Place Description here. + * @var mac_ax_tag_mode::MAC_AX_TAG_MULTI + * Please Place Description here. + * @var mac_ax_tag_mode::MAC_AX_TAG_DEF + * Please Place Description here. + */ +enum mac_ax_tag_mode { + MAC_AX_TAG_SGL, + MAC_AX_TAG_MULTI, + MAC_AX_TAG_DEF = 0xFE +}; + +/** + * @enum mac_ax_rx_fecth + * + * @brief mac_ax_rx_fecth + * + * @var mac_ax_rx_fecth::MAC_AX_RX_NORM_FETCH + * Please Place Description here. + * @var mac_ax_rx_fecth::MAC_AX_RX_PRE_FETCH + * Please Place Description here. + * @var mac_ax_rx_fecth::MAC_AX_RX_FETCH_DEF + * Please Place Description here. + */ +enum mac_ax_rx_fecth { + MAC_AX_RX_NORM_FETCH, + MAC_AX_RX_PRE_FETCH, + MAC_AX_RX_FETCH_DEF = 0xFE +}; + +/** + * @enum mac_ax_tx_burst + * + * @brief mac_ax_tx_burst + * + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_16B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_32B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_64B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_128B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_256B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_512B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_1024B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_2048B + * Please Place Description here. + * @var mac_ax_tx_burst::MAC_AX_TX_BURST_DEF + * Please Place Description here. + */ +enum mac_ax_tx_burst { + MAC_AX_TX_BURST_16B = 0, + MAC_AX_TX_BURST_32B = 1, + MAC_AX_TX_BURST_64B = 2, + MAC_AX_TX_BURST_V1_64B = 0, + MAC_AX_TX_BURST_128B = 3, + MAC_AX_TX_BURST_V1_128B = 1, + MAC_AX_TX_BURST_256B = 4, + MAC_AX_TX_BURST_V1_256B = 2, + MAC_AX_TX_BURST_512B = 5, + MAC_AX_TX_BURST_1024B = 6, + MAC_AX_TX_BURST_2048B = 7, + MAC_AX_TX_BURST_DEF = 0xFE +}; + +/** + * @enum mac_ax_rx_burst + * + * @brief mac_ax_rx_burst + * + * @var mac_ax_rx_burst::MAC_AX_RX_BURST_16B + * Please Place Description here. + * @var mac_ax_rx_burst::MAC_AX_RX_BURST_32B + * Please Place Description here. + * @var mac_ax_rx_burst::MAC_AX_RX_BURST_64B + * Please Place Description here. + * @var mac_ax_rx_burst::MAC_AX_RX_BURST_128B + * Please Place Description here. + * @var mac_ax_rx_burst::MAC_AX_RX_BURST_DEF + * Please Place Description here. + */ +enum mac_ax_rx_burst { + MAC_AX_RX_BURST_16B = 0, + MAC_AX_RX_BURST_32B = 1, + MAC_AX_RX_BURST_64B = 2, + MAC_AX_RX_BURST_V1_64B = 0, + MAC_AX_RX_BURST_128B = 3, + MAC_AX_RX_BURST_V1_128B = 1, + MAC_AX_RX_BURST_V1_256B = 0, + MAC_AX_RX_BURST_DEF = 0xFE +}; + +/** + * @enum mac_ax_wd_dma_intvl + * + * @brief mac_ax_wd_dma_intvl + * + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_0S + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_256NS + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_512NS + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_768NS + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_1US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_1_5US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_2US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_4US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_8US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_16US + * Please Place Description here. + * @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_DEF + * Please Place Description here. + */ +enum mac_ax_wd_dma_intvl { + MAC_AX_WD_DMA_INTVL_0S, + MAC_AX_WD_DMA_INTVL_256NS, + MAC_AX_WD_DMA_INTVL_512NS, + MAC_AX_WD_DMA_INTVL_768NS, + MAC_AX_WD_DMA_INTVL_1US, + MAC_AX_WD_DMA_INTVL_1_5US, + MAC_AX_WD_DMA_INTVL_2US, + MAC_AX_WD_DMA_INTVL_4US, + MAC_AX_WD_DMA_INTVL_8US, + MAC_AX_WD_DMA_INTVL_16US, + MAC_AX_WD_DMA_INTVL_DEF = 0xFE +}; + +/** + * @enum mac_ax_multi_tag_num + * + * @brief mac_ax_multi_tag_num + * + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_1 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_2 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_3 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_4 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_5 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_6 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_7 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_8 + * Please Place Description here. + * @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_DEF + * Please Place Description here. + */ +enum mac_ax_multi_tag_num { + MAC_AX_TAG_NUM_1, + MAC_AX_TAG_NUM_2, + MAC_AX_TAG_NUM_3, + MAC_AX_TAG_NUM_4, + MAC_AX_TAG_NUM_5, + MAC_AX_TAG_NUM_6, + MAC_AX_TAG_NUM_7, + MAC_AX_TAG_NUM_8, + MAC_AX_TAG_NUM_DEF = 0xFE +}; + +/** + * @enum mac_ax_rx_adv_pref + * + * @brief mac_ax_rx_adv_pref + * + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_1BD + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_2BD + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_4BD + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_8BD + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_LAST + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_MAX + * Please Place Description here. + * @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_INVALID + * Please Place Description here. + */ +enum mac_ax_rx_adv_pref { + MAC_AX_RX_APREF_1BD = 0, + MAC_AX_RX_APREF_2BD, + MAC_AX_RX_APREF_4BD, + MAC_AX_RX_APREF_8BD, + /* keep last */ + MAC_AX_RX_APREF_LAST, + MAC_AX_RX_APREF_MAX = MAC_AX_RX_APREF_LAST, + MAC_AX_RX_APREF_INVALID = MAC_AX_RX_APREF_LAST, +}; + +/** + * @enum mac_ax_lbc_tmr + * + * @brief mac_ax_lbc_tmr + * + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_8US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_16US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_32US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_64US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_128US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_256US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_512US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_1MS + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_2MS + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_4MS + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_8MS + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_DEF + * Please Place Description here. + */ +enum mac_ax_lbc_tmr { + MAC_AX_LBC_TMR_8US = 0, + MAC_AX_LBC_TMR_16US, + MAC_AX_LBC_TMR_32US, + MAC_AX_LBC_TMR_64US, + MAC_AX_LBC_TMR_128US, + MAC_AX_LBC_TMR_256US, + MAC_AX_LBC_TMR_512US, + MAC_AX_LBC_TMR_1MS, + MAC_AX_LBC_TMR_2MS, + MAC_AX_LBC_TMR_4MS, + MAC_AX_LBC_TMR_8MS, + MAC_AX_LBC_TMR_DEF = 0xFE +}; + +/** + * @enum mac_ax_io_rcv_tmr + * + * @brief mac_ax_io_rcv_tmr + * + * @var mac_ax_lbc_tmr::MAC_AX_IO_RCV_ANA_TMR_200US + * Please Place Description here. + * @var mac_ax_lbc_tmr::MAC_AX_IO_RCV_ANA_TMR_300US + * Please Place Description here. + */ +enum mac_ax_io_rcy_tmr { + MAC_AX_IO_RCY_ANA_TMR_20US = 240, + MAC_AX_IO_RCY_ANA_TMR_40US = 480, + MAC_AX_IO_RCY_ANA_TMR_60US = 720, + MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE +}; + +/*END need to check and move to other */ + +/** + * @enum mac_ax_edcca_sel + * + * @brief mac_ax_edcca_sel + * + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_TB_CHK + * Please Place Description here. + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_SIFS_CHK + * Please Place Description here. + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_CTN_CHK + * Please Place Description here. + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_LAST + * Please Place Description here. + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_MAX + * Please Place Description here. + * @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_edcca_sel { + MAC_AX_EDCCA_IN_TB_CHK, + MAC_AX_EDCCA_IN_SIFS_CHK, + MAC_AX_EDCCA_IN_CTN_CHK, + + /* keep last */ + MAC_AX_EDCCA_SEL_LAST, + MAC_AX_EDCCA_SEL_MAX = MAC_AX_EDCCA_SEL_LAST, + MAC_AX_EDCCA_SEL_INVALID = MAC_AX_EDCCA_SEL_LAST, +}; + +/** + * @enum mac_ax_chip_id + * + * @brief mac_ax_chip_id + * + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852A + * Please Place Description here. + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852B + * Please Place Description here. + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852C + * Please Place Description here. + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_LAST + * Please Place Description here. + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_MAX + * Please Place Description here. + * @var mac_ax_chip_id::MAC_AX_CHIP_ID_INVALID + * Please Place Description here. + */ +enum mac_ax_chip_id { + MAC_AX_CHIP_ID_8852A = 0, + MAC_AX_CHIP_ID_8852B, + MAC_AX_CHIP_ID_8852C, + MAC_AX_CHIP_ID_8192XB, + + /* keep last */ + MAC_AX_CHIP_ID_LAST, + MAC_AX_CHIP_ID_MAX = MAC_AX_CHIP_ID_LAST, + MAC_AX_CHIP_ID_INVALID = MAC_AX_CHIP_ID_LAST, +}; + +/** + * @enum mac_ax_wdbk_mode + * + * @brief mac_ax_wdbk_mode + * + * @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_SINGLE_BK + * Please Place Description here. + * @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_GRP_BK + * Please Place Description here. + * @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_LAST + * Please Place Description here. + * @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_MAX + * Please Place Description here. + * @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_wdbk_mode { + MAC_AX_WDBK_MODE_SINGLE_BK = 0, + MAC_AX_WDBK_MODE_GRP_BK = 1, + + /* keep last */ + MAC_AX_WDBK_MODE_LAST, + MAC_AX_WDBK_MODE_MAX = MAC_AX_WDBK_MODE_LAST, + MAC_AX_WDBK_MODE_INVALID = MAC_AX_WDBK_MODE_LAST, +}; + +/** + * @enum mac_ax_rty_bk_mode + * + * @brief mac_ax_rty_bk_mode + * + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_AGG + * Please Place Description here. + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_RATE_FB + * Please Place Description here. + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_BK + * Please Place Description here. + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_LAST + * Please Place Description here. + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_MAX + * Please Place Description here. + * @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_rty_bk_mode { + MAC_AX_RTY_BK_MODE_AGG = 0x0, + MAC_AX_RTY_BK_MODE_RATE_FB = 0x1, + MAC_AX_RTY_BK_MODE_BK = 0x2, + + /* keep last */ + MAC_AX_RTY_BK_MODE_LAST, + MAC_AX_RTY_BK_MODE_MAX = MAC_AX_RTY_BK_MODE_LAST, + MAC_AX_RTY_BK_MODE_INVALID = MAC_AX_RTY_BK_MODE_LAST, +}; + +/** + * @enum mac_ax_ch_busy_cnt_ctrl + * + * @brief mac_ax_ch_busy_cnt_ctrl + * + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_LAST + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_MAX + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_INVALID + * Please Place Description here. + */ +enum mac_ax_ch_busy_cnt_ctrl { + MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF, + MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST, + MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST, + MAC_AX_CH_BUSY_CNT_CTRL_CNT_RST, + MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN, + MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS, + + /* keep last */ + MAC_AX_CH_BUSY_CNT_CTRL_LAST, + MAC_AX_CH_BUSY_CNT_CTRL_MAX = MAC_AX_CH_BUSY_CNT_CTRL_LAST, + MAC_AX_CH_BUSY_CNT_CTRL_INVALID = MAC_AX_CH_BUSY_CNT_CTRL_LAST, +}; + +/** + * @enum mac_ax_func_sw + * + * @brief mac_ax_func_sw + * + * @var mac_ax_func_sw::MAC_AX_FUNC_DIS + * Please Place Description here. + * @var mac_ax_func_sw::MAC_AX_FUNC_EN + * Please Place Description here. + * @var mac_ax_func_sw::MAC_AX_FUNC_DEF + * Please Place Description here. + */ +enum mac_ax_func_sw { + MAC_AX_FUNC_DIS = 0, + MAC_AX_FUNC_EN, + MAC_AX_FUNC_DEF +}; + +/** + * @enum mac_ax_twt_nego_tp + * + * @brief mac_ax_twt_nego_tp + * + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_IND + * Please Place Description here. + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_WAKE + * Please Place Description here. + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_BRC + * Please Place Description here. + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_LAST + * Please Place Description here. + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_MAX + * Please Place Description here. + * @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_INVALID + * Please Place Description here. + */ +enum mac_ax_twt_nego_tp { + MAC_AX_TWT_NEGO_TP_IND, + MAC_AX_TWT_NEGO_TP_WAKE, + MAC_AX_TWT_NEGO_TP_BRC, + + /* keep last */ + MAC_AX_TWT_NEGO_TP_LAST, + MAC_AX_TWT_NEGO_TP_MAX = MAC_AX_TWT_NEGO_TP_LAST, + MAC_AX_TWT_NEGO_TP_INVALID = MAC_AX_TWT_NEGO_TP_LAST, +}; + +/** + * @enum mac_ax_twt_act_tp + * + * @brief mac_ax_twt_act_tp + * + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_ADD + * Please Place Description here. + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_DEL + * Please Place Description here. + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_MOD + * Please Place Description here. + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_LAST + * Please Place Description here. + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_MAX + * Please Place Description here. + * @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_INVALID + * Please Place Description here. + */ +enum mac_ax_twt_act_tp { + MAC_AX_TWT_ACT_TP_ADD, + MAC_AX_TWT_ACT_TP_DEL, + MAC_AX_TWT_ACT_TP_MOD, + + /* keep last */ + MAC_AX_TWT_ACT_TP_LAST, + MAC_AX_TWT_ACT_TP_MAX = MAC_AX_TWT_ACT_TP_LAST, + MAC_AX_TWT_ACT_TP_INVALID = MAC_AX_TWT_ACT_TP_LAST, +}; + +/** + * @enum mac_ax_twtact_act_tp + * + * @brief mac_ax_twtact_act_tp + * + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_ADD + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_DEL + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_TRMNT + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_SUS + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_RSUM + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_LAST + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_MAX + * Please Place Description here. + * @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_INVALID + * Please Place Description here. + */ +enum mac_ax_twtact_act_tp { + MAC_AX_TWTACT_ACT_TP_ADD, + MAC_AX_TWTACT_ACT_TP_DEL, + MAC_AX_TWTACT_ACT_TP_TRMNT, + MAC_AX_TWTACT_ACT_TP_SUS, + MAC_AX_TWTACT_ACT_TP_RSUM, + + /* keep last */ + MAC_AX_TWTACT_ACT_TP_LAST, + MAC_AX_TWTACT_ACT_TP_MAX = MAC_AX_TWTACT_ACT_TP_LAST, + MAC_AX_TWTACT_ACT_TP_INVALID = MAC_AX_TWTACT_ACT_TP_LAST, +}; + +/** + * @enum mac_ax_twt_waitanno_tp + * + * @brief mac_ax_twt_waitanno_tp + * + * @var mac_ax_twt_waitanno_tp::MAC_AX_TWT_ANNOWAIT_DIS_MACID + * Please Place Description here. + * @var mac_ax_twt_waitanno_tp::MAC_AX_TWT_ANNOWAIT_EN_MACID + * Please Place Description here. + */ +enum mac_ax_twt_waitanno_tp { + MAC_AX_TWT_ANNOWAIT_DIS_MACID, + MAC_AX_TWT_ANNOWAIT_EN_MACID, +}; + +/** + * @enum mac_ax_tsf_sync_act + * + * @brief mac_ax_tsf_sync_act + * + * @var mac_ax_tsf_sync_act::MAC_AX_TSF_SYNC_NOW_ONCE + * Please Place Description here. + * @var mac_ax_tsf_sync_act::MAC_AX_TSF_EN_SYNC_AUTO + * Please Place Description here. + * @var mac_ax_tsf_sync_act::MAC_AX_TSF_DIS_SYNC_AUTO + * Please Place Description here. + */ +enum mac_ax_tsf_sync_act { + MAC_AX_TSF_SYNC_NOW_ONCE, + MAC_AX_TSF_EN_SYNC_AUTO, + MAC_AX_TSF_DIS_SYNC_AUTO +}; + +/** + * @enum mac_ax_slot_time + * + * @brief mac_ax_slot_time + * + * @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND0_9US + * Please Place Description here. + * @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND0_20US + * Please Place Description here. + * @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND1_9US + * Please Place Description here. + * @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND1_20US + * Please Place Description here. + */ +enum mac_ax_slot_time { + MAC_AX_SLOT_TIME_BAND0_9US, + MAC_AX_SLOT_TIME_BAND0_20US, + MAC_AX_SLOT_TIME_BAND1_9US, + MAC_AX_SLOT_TIME_BAND1_20US, +}; + +/*------------------------Define HCI related enum ----------------------------*/ + +/** + * @enum mac_ax_pcie_func_ctrl + * + * @brief mac_ax_pcie_func_ctrl + * + * @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_DISABLE + * Please Place Description here. + * @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_ENABLE + * Please Place Description here. + * @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_DEFAULT + * Please Place Description here. + * @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_func_ctrl { + MAC_AX_PCIE_DISABLE = 0, + MAC_AX_PCIE_ENABLE = 1, + MAC_AX_PCIE_DEFAULT = 0xFE, + MAC_AX_PCIE_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_pcie_clkdly + * + * @brief mac_ax_pcie_clkdly + * + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_0 + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_5US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_6US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_11US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_15US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_19US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_25US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_30US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_38US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_50US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_64US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_100US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_128US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_150US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_192US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_200US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_300US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_400US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_500US + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_1MS + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_3MS + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_5MS + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_10MS + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_R_ERR + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_DEF + * Please Place Description here. + * @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_clkdly { + MAC_AX_PCIE_CLKDLY_0 = 0, + MAC_AX_PCIE_CLKDLY_5US = 1, + MAC_AX_PCIE_CLKDLY_6US = 2, + MAC_AX_PCIE_CLKDLY_11US = 3, + MAC_AX_PCIE_CLKDLY_15US = 4, + MAC_AX_PCIE_CLKDLY_19US = 5, + MAC_AX_PCIE_CLKDLY_25US = 6, + MAC_AX_PCIE_CLKDLY_30US = 7, + MAC_AX_PCIE_CLKDLY_38US = 8, + MAC_AX_PCIE_CLKDLY_50US = 9, + MAC_AX_PCIE_CLKDLY_64US = 10, + MAC_AX_PCIE_CLKDLY_100US = 11, + MAC_AX_PCIE_CLKDLY_128US = 12, + MAC_AX_PCIE_CLKDLY_150US = 13, + MAC_AX_PCIE_CLKDLY_192US = 14, + MAC_AX_PCIE_CLKDLY_200US = 15, + MAC_AX_PCIE_CLKDLY_300US = 16, + MAC_AX_PCIE_CLKDLY_400US = 17, + MAC_AX_PCIE_CLKDLY_500US = 18, + MAC_AX_PCIE_CLKDLY_1MS = 19, + MAC_AX_PCIE_CLKDLY_3MS = 20, + MAC_AX_PCIE_CLKDLY_5MS = 21, + MAC_AX_PCIE_CLKDLY_10MS = 22, + MAC_AX_PCIE_CLKDLY_R_ERR = 0xFD, + MAC_AX_PCIE_CLKDLY_DEF = 0xFE, + MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_rx_ch + * + * @brief mac_ax_rx_ch + * + * @var mac_ax_rx_ch::MAC_AX_RX_CH_RXQ + * Please Place Description here. + * @var mac_ax_rx_ch::MAC_AX_RX_CH_RPQ + * Please Place Description here. + * @var mac_ax_rx_ch::MAC_AX_RX_CH_NUM + * Please Place Description here. + */ +enum mac_ax_rx_ch { + MAC_AX_RX_CH_RXQ = 0, + MAC_AX_RX_CH_RPQ, + MAC_AX_RX_CH_NUM +}; + +/** + * @enum mac_ax_pcie_l1dly + * + * @brief mac_ax_pcie_l1dly + * + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_16US + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_32US + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_64US + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_INFI + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_R_ERR + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_DEF + * Please Place Description here. + * @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_l1dly { + MAC_AX_PCIE_L1DLY_16US = 0, + MAC_AX_PCIE_L1DLY_32US = 1, + MAC_AX_PCIE_L1DLY_64US = 2, + MAC_AX_PCIE_L1DLY_INFI = 3, + MAC_AX_PCIE_L1DLY_R_ERR = 0xFD, + MAC_AX_PCIE_L1DLY_DEF = 0xFE, + MAC_AX_PCIE_L1DLY_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_pcie_l0sdly + * + * @brief mac_ax_pcie_l0sdly + * + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_1US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_2US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_3US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_4US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_5US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_6US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_7US + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_R_ERR + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_DEF + * Please Place Description here. + * @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_l0sdly { + MAC_AX_PCIE_L0SDLY_1US = 0, + MAC_AX_PCIE_L0SDLY_2US = 1, + MAC_AX_PCIE_L0SDLY_3US = 2, + MAC_AX_PCIE_L0SDLY_4US = 3, + MAC_AX_PCIE_L0SDLY_5US = 4, + MAC_AX_PCIE_L0SDLY_6US = 5, + MAC_AX_PCIE_L0SDLY_7US = 6, + MAC_AX_PCIE_L0SDLY_R_ERR = 0xFD, + MAC_AX_PCIE_L0SDLY_DEF = 0xFE, + MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_pcie_ltr_spc + * + * @brief mac_ax_pcie_ltr_spc + * + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_10US + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_100US + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_500US + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_1MS + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_R_ERR + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_DEF + * Please Place Description here. + * @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_ltr_spc { + MAC_AX_PCIE_LTR_SPC_10US = 0, + MAC_AX_PCIE_LTR_SPC_100US = 1, + MAC_AX_PCIE_LTR_SPC_500US = 2, + MAC_AX_PCIE_LTR_SPC_1MS = 3, + MAC_AX_PCIE_LTR_SPC_R_ERR = 0xFD, + MAC_AX_PCIE_LTR_SPC_DEF = 0xFE, + MAC_AX_PCIE_LTR_SPC_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_pcie_ltr_idle_timer + * + * @brief mac_ax_pcie_ltr_idle_timer + * + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_1US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_10US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_100US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_200US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_400US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_800US + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_1_6MS + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_R_ERR + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_DEF + * Please Place Description here. + * @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE + * Please Place Description here. + */ +enum mac_ax_pcie_ltr_idle_timer { + MAC_AX_PCIE_LTR_IDLE_TIMER_1US = 0, + MAC_AX_PCIE_LTR_IDLE_TIMER_10US = 1, + MAC_AX_PCIE_LTR_IDLE_TIMER_100US = 2, + MAC_AX_PCIE_LTR_IDLE_TIMER_200US = 3, + MAC_AX_PCIE_LTR_IDLE_TIMER_400US = 4, + MAC_AX_PCIE_LTR_IDLE_TIMER_800US = 5, + MAC_AX_PCIE_LTR_IDLE_TIMER_1_6MS = 6, + MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS = 7, + MAC_AX_PCIE_LTR_IDLE_TIMER_R_ERR = 0xFD, + MAC_AX_PCIE_LTR_IDLE_TIMER_DEF = 0xFE, + MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE = 0xFF +}; + +/** + * @enum mac_ax_pcie_ltr_sw_ctrl + * + * @brief mac_ax_pcie_ltr_sw_ctrl + * + * @var mac_ax_pcie_ltr_sw_ctrl::MAC_AX_PCIE_LTR_SW_ACT + * Please Place Description here. + * @var mac_ax_pcie_ltr_sw_ctrl::MAC_AX_PCIE_LTR_SW_IDLE + * Please Place Description here. + */ +enum mac_ax_pcie_ltr_sw_ctrl { + MAC_AX_PCIE_LTR_SW_ACT, + MAC_AX_PCIE_LTR_SW_IDLE +}; + +/** + * @enum mac_ax_sdio_clk_mon + * + * @brief mac_ax_sdio_clk_mon + * + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_SHORT + * Please Place Description here. + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_LONG + * Please Place Description here. + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_USER_DEFINE + * Please Place Description here. + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_LAST + * Please Place Description here. + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_MAX + * Please Place Description here. + * @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_INVALID + * Please Place Description here. + */ +enum mac_ax_sdio_clk_mon { + MAC_AX_SDIO_CLK_MON_SHORT, + MAC_AX_SDIO_CLK_MON_LONG, + MAC_AX_SDIO_CLK_MON_USER_DEFINE, + + /* keep last */ + MAC_AX_SDIO_CLK_MON_LAST, + MAC_AX_SDIO_CLK_MON_MAX = MAC_AX_SDIO_CLK_MON_LAST, + MAC_AX_SDIO_CLK_MON_INVALID = MAC_AX_SDIO_CLK_MON_LAST, +}; + +/** + * @enum mac_ax_rx_ppdu_type + * + * @brief mac_ax_rx_ppdu_type + * + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_CCK + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_OFDM + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_HT + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_VHT_SU + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_VHT_MU + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_SU + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_MU + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_TB + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_LAST + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_MAX + * Please Place Description here. + * @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_INVLAID + * Please Place Description here. + */ +enum mac_ax_rx_ppdu_type { + MAC_AX_RX_CCK, + MAC_AX_RX_OFDM, + MAC_AX_RX_HT, + MAC_AX_RX_VHT_SU, + MAC_AX_RX_VHT_MU, + MAC_AX_RX_HE_SU, + MAC_AX_RX_HE_MU, + MAC_AX_RX_HE_TB, + + MAC_AX_RX_PPDU_LAST, + MAC_AX_RX_PPDU_MAX = MAC_AX_RX_PPDU_LAST, + MAC_AX_RX_PPDU_INVLAID = MAC_AX_RX_PPDU_LAST, +}; + +/** + * @enum mac_ax_net_type + * + * @brief mac_ax_net_type + * + * @var mac_ax_net_type::MAC_AX_NET_TYPE_NO_LINK + * Please Place Description here. + * @var mac_ax_net_type::MAC_AX_NET_TYPE_ADHOC + * Please Place Description here. + * @var mac_ax_net_type::MAC_AX_NET_TYPE_INFRA + * Please Place Description here. + * @var mac_ax_net_type::MAC_AX_NET_TYPE_AP + * Please Place Description here. + */ +enum mac_ax_net_type { + MAC_AX_NET_TYPE_NO_LINK, + MAC_AX_NET_TYPE_ADHOC, + MAC_AX_NET_TYPE_INFRA, + MAC_AX_NET_TYPE_AP +}; + +/** + * @enum mac_ax_disable_rf_func + * + * @brief mac_ax_disable_rf_func + * + * @var mac_ax_disable_rf_func::MAC_AX_DISABLE_RF_FUNC_FBVR + * Please Place Description here. + * @var mac_ax_disable_rf_func::MAC_AX_DISABLE_RF_FUNC_MAX + * Please Place Description here. + */ +enum mac_ax_disable_rf_func { + MAC_AX_DISABLE_RF_FUNC_FBVR, + MAC_AX_DISABLE_RF_FUNC_MAX +}; + +/** + * @enum mac_ax_self_role + * + * @brief mac_ax_self_role + * + * @var mac_ax_self_role::MAC_AX_SELF_ROLE_CLIENT + * Please Place Description here. + * @var mac_ax_self_role::MAC_AX_SELF_ROLE_AP + * Please Place Description here. + * @var mac_ax_self_role::MAC_AX_SELF_ROLE_AP_CLIENT + * Please Place Description here. + */ +enum mac_ax_self_role { + MAC_AX_SELF_ROLE_CLIENT, + MAC_AX_SELF_ROLE_AP, + MAC_AX_SELF_ROLE_AP_CLIENT +}; + +/** + * @enum mac_ax_wifi_role + * + * @brief mac_ax_wifi_role + * + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_NONE + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_STATION + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_AP + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_VAP + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_ADHOC + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_ADHOC_MASTER + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MESH + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MONITOR + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_DEVICE + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_GC + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_GO + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_NAN + * Please Place Description here. + * @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MLME_MAX + * Please Place Description here. + */ +enum mac_ax_wifi_role { + MAC_AX_WIFI_ROLE_NONE, + MAC_AX_WIFI_ROLE_STATION, + MAC_AX_WIFI_ROLE_AP, + MAC_AX_WIFI_ROLE_VAP, + MAC_AX_WIFI_ROLE_ADHOC, + MAC_AX_WIFI_ROLE_ADHOC_MASTER, + MAC_AX_WIFI_ROLE_MESH, + MAC_AX_WIFI_ROLE_MONITOR, + MAC_AX_WIFI_ROLE_P2P_DEVICE, + MAC_AX_WIFI_ROLE_P2P_GC, + MAC_AX_WIFI_ROLE_P2P_GO, + MAC_AX_WIFI_ROLE_NAN, + MAC_AX_WIFI_ROLE_MLME_MAX +}; + +/** + * @enum mac_ax_opmode + * + * @brief mac_ax_opmode + * + * @var mac_ax_opmode::MAC_AX_ROLE_CONNECT + * Please Place Description here. + * @var mac_ax_opmode::MAC_AX_ROLE_DISCONN + * Please Place Description here. + */ +enum mac_ax_opmode { + MAC_AX_ROLE_CONNECT, + MAC_AX_ROLE_DISCONN +}; + +/** + * @enum mac_ax_upd_mode + * + * @brief mac_ax_upd_mode + * + * @var mac_ax_upd_mode::MAC_AX_ROLE_CREATE + * Please Place Description here. + * @var mac_ax_upd_mode::MAC_AX_ROLE_REMOVE + * Please Place Description here. + * @var mac_ax_upd_mode::MAC_AX_ROLE_TYPE_CHANGE + * Please Place Description here. + * @var mac_ax_upd_mode::MAC_AX_ROLE_INFO_CHANGE + * Please Place Description here. + * @var mac_ax_upd_mode::MAC_AX_ROLE_CON_DISCONN + * Please Place Description here. + */ +enum mac_ax_upd_mode { + MAC_AX_ROLE_CREATE, + MAC_AX_ROLE_REMOVE, + MAC_AX_ROLE_TYPE_CHANGE, + MAC_AX_ROLE_INFO_CHANGE, + MAC_AX_ROLE_CON_DISCONN +}; + +/** + * @enum mac_ax_host_rpr_mode + * + * @brief mac_ax_host_rpr_mode + * + * @var mac_ax_host_rpr_mode::MAC_AX_RPR_MODE_POH + * Please Place Description here. + * @var mac_ax_host_rpr_mode::MAC_AX_RPR_MODE_STF + * Please Place Description here. + */ +enum mac_ax_host_rpr_mode { + MAC_AX_RPR_MODE_POH = 0, + MAC_AX_RPR_MODE_STF +}; + +#ifndef CONFIG_FW_IO_OFLD_SUPPORT +/** + * @enum rtw_mac_src_cmd_ofld + * + * @brief rtw_mac_src_cmd_ofld + * + * @var rtw_mac_src_cmd_ofld::MAC_AX_BB_CMD_OFLD + * Please Place Description here. + * @var rtw_mac_src_cmd_ofld::MAC_AX_RF_CMD_OFLD + * Please Place Description here. + * @var rtw_mac_src_cmd_ofld::MAC_AX_MAC_CMD_OFLD + * Please Place Description here. + * @var rtw_mac_src_cmd_ofld::MAC_AX_OTHER_CMD_OFLD + * Please Place Description here. + */ +enum rtw_mac_src_cmd_ofld { + RTW_MAC_BB_CMD_OFLD = 0, + RTW_MAC_RF_CMD_OFLD, + RTW_MAC_MAC_CMD_OFLD, + RTW_MAC_OTHER_CMD_OFLD +}; + +/** + * @enum rtw_mac_cmd_type_ofld + * + * @brief rtw_mac_cmd_type_ofld + * + * @var rtw_mac_cmd_type_ofld::MAC_AX_WRITE_OFLD + * Please Place Description here. + * @var rtw_mac_cmd_type_ofld::MAC_AX_POLLING_OFLD + * Please Place Description here. + * @var rtw_mac_cmd_type_ofld::MAC_AX_DELAY_OFLD + * Please Place Description here. + */ +enum rtw_mac_cmd_type_ofld { + RTW_MAC_WRITE_OFLD = 0, + RTW_MAC_COMPARE_OFLD, + RTW_MAC_DELAY_OFLD +}; + +/** + * @enum mac_ax_cmd_id + * + * @brief mac_ax_cmd_id + * + * @var mac_ax_host_rpr_mode::MAC_AX_ID_0 + * Please Place Description here. + * @var mac_ax_host_rpr_mode::MAC_AX_ID_1 + * Please Place Description here. + */ +enum mac_ax_cmd_id { + MAC_AX_ID_0 = 0, + MAC_AX_ID_1 +}; + +/** + * @enum rtw_mac_rf_path + * + * @brief rtw_mac_rf_path + * + * @var rtw_mac_rf_path::RF_PATH_A + * Please Place Description here. + * @var rtw_mac_rf_path::RF_PATH_B + * Please Place Description here. + * @var rtw_mac_rf_path::RF_PATH_C + * Please Place Description here. + * @var rtw_mac_rf_path::RF_PATH_D + * Please Place Description here. + */ +enum rtw_mac_rf_path { + RTW_MAC_RF_PATH_A = 0, //Radio Path A + RTW_MAC_RF_PATH_B, //Radio Path B + RTW_MAC_RF_PATH_C, //Radio Path C + RTW_MAC_RF_PATH_D, //Radio Path D +}; + +enum rtw_fw_cap { + FW_CAP_IO_OFLD = BIT(0), +}; + +#endif + +/** + * @struct mac_ax_role_opmode + * @brief mac_ax_role_opmode + * + * @var mac_ax_role_opmode::ADD + * Please Place Description here. + * @var mac_ax_role_opmode::CHG + * Please Place Description here. + * @var mac_ax_role_opmode::RMV + * Please Place Description here. + */ +enum mac_ax_role_opmode { + ADD = 0, + CHG, + RMV +}; + +/*--------------------Define FAST_CH_SW related enum-------------------------------------*/ +/** + * @struct mac_ax_fast_ch_sw_status_code + * @brief mac_ax_fast_ch_sw_status_code + * + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_OK + * FAST_CH_SW done without error + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_MALLOC_FAIL + * fail when malloc pkt for part of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_MALLOC_FAIL + * fail when malloc pkt for all of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_READOFLD_FAIL + * fail when reading offloaded pkt for part of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_READOFLD_FAIL + * fail when reading offloaded pkt for all of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_SENDPKT_FAIL + * fail when sending pkt to part of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_SENDPKT_FAIL + * fail when sending pkt to all of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_NO_ACK + * not receiving ack from part of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_NO_ACK + * not receiving ack from all of stas + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_SWITCH_CH_FAIL + * AP fail to switch channel + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_RF_PARAM_ERR + * AP fail to restore RF params + * @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_MAX + * Please Place Description here. + */ +enum mac_ax_fast_ch_sw_status_code { + MAC_AX_FAST_CH_SW_STATUS_OK = 0, + MAC_AX_FAST_CH_SW_STATUS_PART_MALLOC_FAIL = 1, + MAC_AX_FAST_CH_SW_STATUS_ALL_MALLOC_FAIL = 2, + MAC_AX_FAST_CH_SW_STATUS_PART_READOFLD_FAIL = 3, + MAC_AX_FAST_CH_SW_STATUS_ALL_READOFLD_FAIL = 4, + MAC_AX_FAST_CH_SW_STATUS_PART_SENDPKT_FAIL = 5, + MAC_AX_FAST_CH_SW_STATUS_ALL_SENDPKT_FAIL = 6, + MAC_AX_FAST_CH_SW_STATUS_PART_NO_ACK = 7, + MAC_AX_FAST_CH_SW_STATUS_ALL_NO_ACK = 8, + MAC_AX_FAST_CH_SW_STATUS_SWITCH_CH_FAIL = 9, + MAC_AX_FAST_CH_SW_STATUS_RF_PARAM_ERR = 10, + MAC_AX_FAST_CH_SW_STATUS_MAX +}; + +enum mac_ax_fw_state { + FS_SLEEP_IN = 0x10, + FS_ERRHDL_IN = 0x11, + FS_ASSERT_IN = 0x12, + FS_EXCEP_IN = 0x13, + FS_L2ERR_IN = 0x14, + FS_L2ERR_CPU_IN = 0x15,//CPU address hole + FS_L2ERR_HCI_IN = 0x16,//HCI timeout + FS_L2ERR_ELSE_IN = 0x17, + FS_WOW_FWDL_IN = 0x18, + + FS_SLEEP_OUT = 0x80, + FS_ERRHDL_OUT = 0x81, + FS_ASSERT_OUT = 0x82, + //rsvd: 0xFFFFFF83 + FS_L2ERR_OUT = 0x84, + + // Defeature + FS_DEFEA_RXNSS = 0xEA01, + FS_DEFEA_BW5 = 0xEA02, + FS_DEFEA_BW10 = 0xEA03, + FS_DEFEA_BW20 = 0xEA04, + FS_DEFEA_BW40 = 0xEA05, + FS_DEFEA_BW80 = 0xEA06, + FS_DEFEA_BW160 = 0xEA07, + FS_DEFEA_TXNSS = 0xEA08, + FS_DEFEA_PTCL = 0xEA09, + FS_DEFEA_DBLABORT = 0xEA0A, +}; + +enum mac_ax_dev2hst_gpio { + MAC_AX_DEV2HST_GPIO_OUTPUT = 0, + MAC_AX_DEV2HST_GPIO_INPUT = 1, + MAC_AX_DEV2HST_GPIO_MAX +}; + +enum mac_ax_dev2hst_active { + MAC_AX_DEV2HST_LOW_ACTIVE = 0, + MAC_AX_DEV2HST_HIGH_ACTIVE = 1, + MAC_AX_DEV2HST_ACTIVE_MAX +}; + +enum mac_ax_dev2hst_toggle_pulse { + MAC_AX_DEV2HST_TOGGLE = 0, + MAC_AX_DEV2HST_PULSE = 1, + MAC_AX_DEV2HST_TOGGLE_PULSE_MAX +}; + +enum mac_ax_dev2hst_time_unit { + MAC_AX_DEV2HST_US = 0, + MAC_AX_DEV2HST_MS = 1, + MAC_AX_DEV2HST_TIME_UNIT_MAX +}; + +/** + * @enum h2c_buf_class + * + * @brief h2c_buf_class + * + * @var h2c_buf_class::H2CB_CLASS_CMD + * Please Place Description here. + * @var h2c_buf_class::H2CB_CLASS_DATA + * Please Place Description here. + * @var h2c_buf_class::H2CB_CLASS_LONG_DATA + * Please Place Description here. + * @var h2c_buf_class::H2CB_CLASS_LAST + * Please Place Description here. + * @var h2c_buf_class::H2CB_CLASS_MAX + * Please Place Description here. + * @var h2c_buf_class::H2CB_CLASS_INVALID + * Please Place Description here. + */ +enum h2c_buf_class { + H2CB_CLASS_CMD, /* FW command */ + H2CB_CLASS_DATA, /* FW command + data */ + H2CB_CLASS_LONG_DATA, /* FW command + long data */ + + /* keep last */ + H2CB_CLASS_LAST, + H2CB_CLASS_MAX = H2CB_CLASS_LAST, + H2CB_CLASS_INVALID = H2CB_CLASS_LAST, +}; + +/*--------------------Define Power Saving related enum-------------------------------------*/ +/** + * @enum mac_ax_listern_bcn_mode + * + * @brief mac_ax_listern_bcn_mode + * + * @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_MIN + * Please Place Description here. + * @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_MAX + * Please Place Description here. + * @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_USERDEFINE + * Please Place Description here. + */ +enum mac_ax_listern_bcn_mode { + MAC_AX_RLBM_MIN = 0, + MAC_AX_RLBM_MAX = 1, + MAC_AX_RLBM_USERDEFINE = 2, +}; + +/** + * @enum mac_ax_smart_ps_mode + * + * @brief mac_ax_smart_ps_mode + * + * @var mac_ax_smart_ps_mode::MAC_AX_SMART_PS_MODE_LEGACY_PWR1 + * Please Place Description here. + * @var mac_ax_smart_ps_mode::MAC_AX_SMART_PS_MODE_TRX_PWR0 + * Please Place Description here. + */ +enum mac_ax_smart_ps_mode { + MAC_AX_SMART_PS_MODE_LEGACY_PWR1 = 0, + MAC_AX_SMART_PS_MODE_TRX_PWR0 = 1, +}; + +/** + * @enum mac_ax_ps_advance_parm_op + * + * @brief mac_ax_ps_advance_parm_op + * + * @var mac_ax_ps_advance_parm_op::PS_ADVANCE_PARM_OP_NO_CHANGE + * Please Place Description here. + * @var mac_ax_ps_advance_parm_op::PS_ADVANCE_PARM_OP_SET + * Please Place Description here. + * @var mac_ax_ps_advance_parm_op::PS_ADVANCE_PARM_OP_DEFAULT + * Please Place Description here. + */ +enum mac_ax_ps_advance_parm_op{ + PS_ADVANCE_PARM_OP_NO_CHANGE = 0, + PS_ADVANCE_PARM_OP_SET = 1, + PS_ADVANCE_PARM_OP_DEFAULT = 2, +}; + +/** + * @struct mac_ax_scanofld_notify_reason + * @brief mac_ax_scanofld_notify_reason + * + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_DWELL_NOTIFY + * channel dwell due to rcv bcn + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_PRE_TX_NOTIFY + * before tx pkt + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_POST_TX_NOTIFY + * after tx pkt + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_ENTER_CH_NOTIFY + * enter ch + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_LEAVE_CH_NOTIFY + * leace ch + * @var mac_ax_scanofld_notify_reason::MAC_AX_SCAN_END_SCAN_NOTIFY + * scan stop + */ +enum mac_ax_scanofld_notify_reason { + MAC_AX_SCAN_DWELL_NOTIFY = 0, + MAC_AX_SCAN_PRE_TX_NOTIFY = 1, + MAC_AX_SCAN_POST_TX_NOTIFY = 2, + MAC_AX_SCAN_ENTER_CH_NOTIFY = 3, + MAC_AX_SCAN_LEAVE_CH_NOTIFY = 4, + MAC_AX_SCAN_END_SCAN_NOTIFY = 5, +}; + +/** + * @struct mac_ax_scan_ofld_op + * @brief mac_ax_scan_ofld_op + * + * @var mac_ax_scan_ofld_op::MAC_AX_SCAN_OP_STOP + * stop scan + * @var mac_ax_scan_ofld_op::MAC_AX_SCAN_OP_START + * start scan + * @var mac_ax_scan_ofld_op::MAC_AX_SCAN_OP_SETPARM + * set parameter only + * @var mac_ax_scan_ofld_op::MAC_AX_SCAN_OP_MAX + * max + */ +enum mac_ax_scan_ofld_op { + MAC_AX_SCAN_OP_STOP = 0, + MAC_AX_SCAN_OP_START = 1, + MAC_AX_SCAN_OP_SETPARM = 2, + MAC_AX_SCAN_OP_MAX +}; + +/** + * @struct mac_ax_scan_ofld_scantype + * @brief mac_ax_scan_ofld_scantype + * + * @var mac_ax_scan_ofld_scantype::MAC_AX_SCAN_TYPE_SCANONCE + * scan once + * @var mac_ax_scan_ofld_scantype::MAC_AX_SCAN_TYPE_NORMAL + * repeat. period=normal pd + * @var mac_ax_scan_ofld_scantype::MAC_AX_SCAN_TYPE_NORMAL_SLOW + * repeat. normal pd * normal cycle + slow pd + * @var mac_ax_scan_ofld_scantype::MAC_AX_SCAN_TYPE_SEAMLESS + * repeat seamless + * @var mac_ax_scan_ofld_scantype::MAC_AX_SCAN_TYPE_MAX + * max + */ +enum mac_ax_scan_ofld_scantype { + MAC_AX_SCAN_TYPE_SCANONCE = 0, + MAC_AX_SCAN_TYPE_NORMAL = 1, + MAC_AX_SCAN_TYPE_NORMAL_SLOW = 2, + MAC_AX_SCAN_TYPE_SEAMLESS = 3, + MAC_AX_SCAN_TYPE_MAX +}; + +/** + * @struct mac_ax_scanofld_start_mode + * @brief mac_ax_scanofld_start_mode + * + * @var mac_ax_scanofld_start_mode::MAC_AX_SCAN_START_NOW + * start now + * @var mac_ax_scanofld_start_mode::MAC_AX_SCAN_START_TSF + * start at assigned tsf + * @var mac_ax_scanofld_start_mode::MAC_AX_SCAN_START_MAX + * max + */ +enum mac_ax_scanofld_start_mode { + MAC_AX_SCAN_START_NOW = 0, + MAC_AX_SCAN_START_TSF = 1, + MAC_AX_SCAN_START_MAX +}; + +/*--------------------Define Struct-------------------------------------*/ + +/** + * @struct mac_ax_sch_tx_en + * @brief mac_ax_sch_tx_en + * + * @var mac_ax_sch_tx_en::be0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::bk0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::vi0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::vo0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::be1 + * Please Place Description here. + * @var mac_ax_sch_tx_en::bk1 + * Please Place Description here. + * @var mac_ax_sch_tx_en::vi1 + * Please Place Description here. + * @var mac_ax_sch_tx_en::vo1 + * Please Place Description here. + * @var mac_ax_sch_tx_en::mg0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::mg1 + * Please Place Description here. + * @var mac_ax_sch_tx_en::mg2 + * Please Place Description here. + * @var mac_ax_sch_tx_en::hi + * Please Place Description here. + * @var mac_ax_sch_tx_en::bcn + * Please Place Description here. + * @var mac_ax_sch_tx_en::ul + * Please Place Description here. + * @var mac_ax_sch_tx_en::twt0 + * Please Place Description here. + * @var mac_ax_sch_tx_en::twt1 + * Please Place Description here. + */ +struct mac_ax_sch_tx_en { + u8 be0:1; + u8 bk0:1; + u8 vi0:1; + u8 vo0:1; + u8 be1:1; + u8 bk1:1; + u8 vi1:1; + u8 vo1:1; + u8 mg0:1; + u8 mg1:1; + u8 mg2:1; + u8 hi:1; + u8 bcn:1; + u8 ul:1; + u8 twt0:1; + u8 twt1:1; +}; + +/** + * @struct mac_ax_hw_info + * @brief mac_ax_hw_info + * + * @var mac_ax_hw_info::done + * Please Place Description here. + * @var mac_ax_hw_info::chip_id + * Please Place Description here. + * @var mac_ax_hw_info::cv + * Please Place Description here. + * @var mac_ax_hw_info::intf + * Please Place Description here. + * @var mac_ax_hw_info::tx_ch_num + * Please Place Description here. + * @var mac_ax_hw_info::tx_data_ch_num + * Please Place Description here. + * @var mac_ax_hw_info::wd_body_len + * Please Place Description here. + * @var mac_ax_hw_info::wd_info_len + * Please Place Description here. + * @var mac_ax_hw_info::pwr_on_seq + * Please Place Description here. + * @var mac_ax_hw_info::pwr_off_seq + * Please Place Description here. + * @var mac_ax_hw_info::pwr_seq_ver + * Please Place Description here. + * @var mac_ax_hw_info::fifo_size + * Please Place Description here. + * @var mac_ax_hw_info::macid_num + * Please Place Description here. + * @var mac_ax_hw_info::bssid_num + * Please Place Description here. + * @var mac_ax_hw_info::wl_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::log_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::limit_efuse_size_pcie + * Please Place Description here. + * @var mac_ax_hw_info::limit_efuse_size_usb + * Please Place Description here. + * @var mac_ax_hw_info::limit_efuse_size_sdio + * Please Place Description here. + * @var mac_ax_hw_info::bt_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::bt_log_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::hidden_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::sec_ctrl_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::sec_data_efuse_size + * Please Place Description here. + * @var mac_ax_hw_info::sec_cam_table + * Please Place Description here. + * @var mac_ax_hw_info::ple_rsvd_space + * Please Place Description here. + * @var mac_ax_hw_info::payload_desc_size + * Please Place Description here. + * @var mac_ax_hw_info::wd_checksum_en + * Please Place Description here. + * @var mac_ax_hw_info::sw_amsdu_max_size + * Please Place Description here. + * @var mac_ax_hw_info::core_swr_volt + * Please Place Description here. + * @var mac_ax_hw_info::core_swr_volt_sel + * Please Place Description here. + */ +struct mac_ax_hw_info { + u8 done; + u8 chip_id; + u8 cv; + enum mac_ax_intf intf; + u8 tx_ch_num; + u8 tx_data_ch_num; + u8 wd_body_len; + u8 wd_info_len; + struct mac_pwr_cfg **pwr_on_seq; + struct mac_pwr_cfg **pwr_off_seq; + u8 pwr_seq_ver; + u32 fifo_size; + u16 macid_num; + u8 port_num; + u8 mbssid_num; + u8 bssid_num; + u32 wl_efuse_size; + u32 efuse_size; + u32 log_efuse_size; + u32 limit_efuse_size_pcie; + u32 limit_efuse_size_usb; + u32 limit_efuse_size_sdio; + u32 bt_efuse_size; + u32 bt_log_efuse_size; + u8 hidden_efuse_size; + u32 sec_ctrl_efuse_size; + u32 sec_data_efuse_size; + struct sec_cam_table_t *sec_cam_table; + struct sec_cam_table_t *sec_cam_table_bk; + u8 ple_rsvd_space; + u8 payload_desc_size; + u8 efuse_version_size; + u32 dav_full_efuse_size; + u32 dav_efuse_size; + u32 dav_hidden_efuse_size; + u32 dav_log_efuse_size; + u32 wl_efuse_start_addr; + u32 dav_efuse_start_addr; + u32 bt_efuse_start_addr; + u8 wd_checksum_en; + u32 sw_amsdu_max_size; + u32 (*pwr_on)(void *vadapter); + u32 (*pwr_off)(void *vadapter); + u32 ind_aces_cnt; + u32 dbg_port_cnt; + u8 core_swr_volt; + enum mac_ax_core_swr_volt core_swr_volt_sel; + mac_ax_mutex ind_access_lock; + mac_ax_mutex lte_rlock; + mac_ax_mutex lte_wlock; + mac_ax_mutex dbg_port_lock; + mac_ax_mutex err_set_lock; + mac_ax_mutex err_get_lock; + mac_ax_mutex dbi_lock; + mac_ax_mutex mdio_lock; +}; + +/** + * @struct mac_ax_fw_info + * @brief mac_ax_fw_info + * + * @var mac_ax_fw_info::major_ver + * Please Place Description here. + * @var mac_ax_fw_info::minor_ver + * Please Place Description here. + * @var mac_ax_fw_info::sub_ver + * Please Place Description here. + * @var mac_ax_fw_info::sub_idx + * Please Place Description here. + * @var mac_ax_fw_info::build_year + * Please Place Description here. + * @var mac_ax_fw_info::build_mon + * Please Place Description here. + * @var mac_ax_fw_info::build_date + * Please Place Description here. + * @var mac_ax_fw_info::build_hour + * Please Place Description here. + * @var mac_ax_fw_info::build_min + * Please Place Description here. + * @var mac_ax_fw_info::h2c_seq + * Please Place Description here. + * @var mac_ax_fw_info::rec_seq + * Please Place Description here. + * @var mac_ax_fw_info::seq_lock + * Please Place Description here. + */ +struct mac_ax_fw_info { + u8 major_ver; + u8 minor_ver; + u8 sub_ver; + u8 sub_idx; + u16 build_year; + u16 build_mon; + u16 build_date; + u16 build_hour; + u16 build_min; + u8 h2c_seq; + u8 rec_seq; + mac_ax_mutex seq_lock; + mac_ax_mutex msg_reg; +}; + +/** + * @struct mac_ax_h2c_agg_node + * @brief mac_ax_h2c_agg_node + * + * @var mac_ax_h2c_agg_node::next + * Please Place Description here. + * @var mac_ax_h2c_agg_node::h2c_pkt + * Please Place Description here. + */ +struct mac_ax_h2c_agg_node { + struct mac_ax_h2c_agg_node *next; + u8 *h2c_pkt; +}; + +/** + * @struct mac_ax_h2c_agg_info + * @brief mac_ax_h2c_agg_info + * + * @var mac_ax_h2c_agg_info::h2c_agg_en + * Please Place Description here. + * @var mac_ax_h2c_agg_info::h2c_agg_pkt_num + * Please Place Description here. + * @var mac_ax_h2c_agg_info::h2c_agg_queue_head + * Please Place Description here. + * @var mac_ax_h2c_agg_info::h2c_agg_queue_last + * Please Place Description here. + * @var mac_ax_h2c_agg_info::h2c_agg_lock + * Please Place Description here. + */ +struct mac_ax_h2c_agg_info { + u8 h2c_agg_en; + u32 h2c_agg_pkt_num; + struct mac_ax_h2c_agg_node *h2c_agg_queue_head; + struct mac_ax_h2c_agg_node *h2c_agg_queue_last; + mac_ax_mutex h2c_agg_lock; +}; + +/** + * @struct mac_ax_mac_pwr_info + * @brief mac_ax_mac_pwr_info + * + * @var mac_ax_mac_pwr_info::pwr_seq_proc + * Please Place Description here. + * @var mac_ax_mac_pwr_info::pwr_in_lps + * Please Place Description here. + * @var mac_ax_mac_pwr_info::intf_pwr_switch + * Please Place Description here. + */ +struct mac_ax_mac_pwr_info { + u8 pwr_seq_proc; + u8 pwr_in_lps; + u32 (*intf_pwr_switch)(void *vadapter, + u8 pre_switch, u8 on); +}; + +/** + * @struct mac_ax_ft_status + * @brief mac_ax_ft_status + * + * @var mac_ax_ft_status::mac_ft + * Please Place Description here. + * @var mac_ax_ft_status::status + * Please Place Description here. + * @var mac_ax_ft_status::buf + * Please Place Description here. + * @var mac_ax_ft_status::size + * Please Place Description here. + */ +struct mac_ax_ft_status { + enum mac_ax_feature mac_ft; + enum mac_ax_status status; + u8 *buf; + u32 size; +}; + +/** + * @struct mac_ax_dle_info + * @brief mac_ax_dle_info + * + * @var mac_ax_dle_info::qta_mode + * Please Place Description here. + * @var mac_ax_dle_info::wde_pg_size + * Please Place Description here. + * @var mac_ax_dle_info::ple_pg_size + * Please Place Description here. + * @var mac_ax_dle_info::c0_rx_qta + * Please Place Description here. + * @var mac_ax_dle_info::c1_rx_qta + * Please Place Description here. + */ +struct mac_ax_dle_info { + enum mac_ax_qta_mode qta_mode; + u16 wde_pg_size; + u16 ple_pg_size; + u16 c0_rx_qta; + u16 c1_rx_qta; + u16 c0_ori_max; + u16 c1_ori_max; + u16 c0_tx_min; + u16 c1_tx_min; +}; + +/** + * @struct mac_ax_gpio_info + * @brief mac_ax_gpio_info + * + * @var mac_ax_gpio_info::sw_io_0 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_1 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_2 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_3 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_4 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_5 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_6 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_7 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_8 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_9 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_10 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_11 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_12 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_13 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_14 + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_15 + * Please Place Description here. + * @var mac_ax_gpio_info::uart_tx_gpio5 + * Please Place Description here. + * @var mac_ax_gpio_info::uart_tx_gpio7 + * Please Place Description here. + * @var mac_ax_gpio_info::uart_tx_gpio8 + * Please Place Description here. + * @var mac_ax_gpio_info::uart_rx_gpio6 + * Please Place Description here. + * @var mac_ax_gpio_info::uart_rx_gpio14 + * Please Place Description here. + * @var mac_ax_gpio_info::status + * Please Place Description here. + * @var mac_ax_gpio_info::sw_io_output + * Please Place Description here. + */ +struct mac_ax_gpio_info { +#define MAC_AX_GPIO_NUM 19 + /* byte0 */ + u8 sw_io_0:1; + u8 sw_io_1:1; + u8 sw_io_2:1; + u8 sw_io_3:1; + u8 sw_io_4:1; + u8 sw_io_5:1; + u8 sw_io_6:1; + u8 sw_io_7:1; + /* byte1 */ + u8 sw_io_8:1; + u8 sw_io_9:1; + u8 sw_io_10:1; + u8 sw_io_11:1; + u8 sw_io_12:1; + u8 sw_io_13:1; + u8 sw_io_14:1; + u8 sw_io_15:1; + /* byte2 */ + u8 uart_tx_gpio5:1; + u8 uart_tx_gpio7:1; + u8 uart_tx_gpio8:1; + u8 uart_rx_gpio6:1; + u8 uart_rx_gpio14:1; + enum rtw_mac_gfunc status[MAC_AX_GPIO_NUM]; +#define MAC_AX_SW_IO_OUT_PP 0 +#define MAC_AX_SW_IO_OUT_OD 1 + u8 sw_io_output[MAC_AX_GPIO_NUM]; +}; + +/** + * @struct mac_ax_trx_info + * @brief mac_ax_trx_info + * + * @var mac_ax_trx_info::trx_mode + * Please Place Description here. + * @var mac_ax_trx_info::qta_mode + * Please Place Description here. + * @var mac_ax_trx_info::rpr_cfg + * Please Place Description here. + */ +struct mac_ax_trx_info { + enum mac_ax_trx_mode trx_mode; + enum mac_ax_qta_mode qta_mode; + struct mac_ax_host_rpr_cfg *rpr_cfg; +}; + +/** + * @struct mac_ax_fwdl_info + * @brief mac_ax_fwdl_info + * + * @var mac_ax_fwdl_info::fw_en + * Please Place Description here. + * @var mac_ax_fwdl_info::dlrom_en + * Please Place Description here. + * @var mac_ax_fwdl_info::dlram_en + * Please Place Description here. + * @var mac_ax_fwdl_info::fw_from_hdr + * Please Place Description here. + * @var mac_ax_fwdl_info::fw_cat + * Please Place Description here. + * @var mac_ax_fwdl_info::rom_buff + * Please Place Description here. + * @var mac_ax_fwdl_info::rom_size + * Please Place Description here. + * @var mac_ax_fwdl_info::ram_buff + * Please Place Description here. + * @var mac_ax_fwdl_info::ram_size + * Please Place Description here. + */ +struct mac_ax_fwdl_info { + u8 fw_en; + u8 dlrom_en; + u8 dlram_en; + u8 fw_from_hdr; + enum rtw_fw_type fw_cat; + u8 *rom_buff; + u32 rom_size; + u8 *ram_buff; + u32 ram_size; +}; + +/** + * @struct mac_ax_txdma_ch_map + * @brief mac_ax_txdma_ch_map + * + * @var mac_ax_txdma_ch_map::ch0 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch1 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch2 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch3 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch4 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch5 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch6 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch7 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch8 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch9 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch10 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch11 + * Please Place Description here. + * @var mac_ax_txdma_ch_map::ch12 + * Please Place Description here. + */ +struct mac_ax_txdma_ch_map { + enum mac_ax_pcie_func_ctrl ch0; + enum mac_ax_pcie_func_ctrl ch1; + enum mac_ax_pcie_func_ctrl ch2; + enum mac_ax_pcie_func_ctrl ch3; + enum mac_ax_pcie_func_ctrl ch4; + enum mac_ax_pcie_func_ctrl ch5; + enum mac_ax_pcie_func_ctrl ch6; + enum mac_ax_pcie_func_ctrl ch7; + enum mac_ax_pcie_func_ctrl ch8; + enum mac_ax_pcie_func_ctrl ch9; + enum mac_ax_pcie_func_ctrl ch10; + enum mac_ax_pcie_func_ctrl ch11; + enum mac_ax_pcie_func_ctrl ch12; +}; + +/** + * @struct mac_ax_rxdma_ch_map + * @brief mac_ax_rxdma_ch_map + * + * @var mac_ax_rxdma_ch_map::rxq + * Please Place Description here. + * @var mac_ax_rxdma_ch_map::rpq + * Please Place Description here. + */ +struct mac_ax_rxdma_ch_map { + enum mac_ax_pcie_func_ctrl rxq; + enum mac_ax_pcie_func_ctrl rpq; +}; + +/** + * @struct mac_ax_intf_info + * @brief mac_ax_intf_info + * + * @var mac_ax_intf_info::txbd_trunc_mode + * Please Place Description here. + * @var mac_ax_intf_info::rxbd_trunc_mode + * Please Place Description here. + * @var mac_ax_intf_info::rxbd_mode + * Please Place Description here. + * @var mac_ax_intf_info::tag_mode + * Please Place Description here. + * @var mac_ax_intf_info::tx_burst + * Please Place Description here. + * @var mac_ax_intf_info::rx_burst + * Please Place Description here. + * @var mac_ax_intf_info::wd_dma_idle_intvl + * Please Place Description here. + * @var mac_ax_intf_info::wd_dma_act_intvl + * Please Place Description here. + * @var mac_ax_intf_info::multi_tag_num + * Please Place Description here. + * @var mac_ax_intf_info::rx_sep_append_len + * Please Place Description here. + * @var mac_ax_intf_info::txbd_buf + * Please Place Description here. + * @var mac_ax_intf_info::rxbd_buf + * Please Place Description here. + * @var mac_ax_intf_info::skip_all + * Please Place Description here. + * @var mac_ax_intf_info::txch_map + * Please Place Description here. + * @var mac_ax_intf_info::lbc_en + * Please Place Description here. + * @var mac_ax_intf_info::lbc_tmr + * Please Place Description here. + * @var mac_ax_intf_info::autok_en + * Please Place Description here. + */ +struct mac_ax_intf_info { + enum mac_ax_bd_trunc_mode txbd_trunc_mode; + enum mac_ax_bd_trunc_mode rxbd_trunc_mode; + enum mac_ax_rxbd_mode rxbd_mode; + enum mac_ax_tag_mode tag_mode; + enum mac_ax_tx_burst tx_burst; + enum mac_ax_rx_burst rx_burst; + enum mac_ax_wd_dma_intvl wd_dma_idle_intvl; + enum mac_ax_wd_dma_intvl wd_dma_act_intvl; + enum mac_ax_multi_tag_num multi_tag_num; + u16 rx_sep_append_len; + u8 *txbd_buf; + u8 *rxbd_buf; + u8 skip_all; + struct mac_ax_txdma_ch_map *txch_map; + enum mac_ax_pcie_func_ctrl lbc_en; + enum mac_ax_lbc_tmr lbc_tmr; + enum mac_ax_pcie_func_ctrl autok_en; + enum mac_ax_pcie_func_ctrl io_rcy_en; + enum mac_ax_io_rcy_tmr io_rcy_tmr; +}; + +/** + * @struct mac_ax_pcie_trx_mitigation + * @brief mac_ax_pcie_trx_mitigation + * + * @var mac_ax_pcie_trx_mitigation::txch_map + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::tx_timer_unit + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::tx_timer + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::tx_counter + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::rxch_map + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::rx_timer_unit + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::rx_timer + * Please Place Description here. + * @var mac_ax_pcie_trx_mitigation::rx_counter + * Please Place Description here. + */ +struct mac_ax_pcie_trx_mitigation { + struct mac_ax_txdma_ch_map *txch_map; + enum mac_ax_trx_mitigation_timer_unit tx_timer_unit; + u8 tx_timer; + u8 tx_counter; + struct mac_ax_rxdma_ch_map *rxch_map; + enum mac_ax_trx_mitigation_timer_unit rx_timer_unit; + u8 rx_timer; + u8 rx_counter; +}; + +/** + * @struct mac_mu_table + * @brief mac_mu_table + * + * @var mac_mu_table::mu_score_tbl_ctrl + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_0 + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_1 + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_2 + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_3 + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_4 + * Please Place Description here. + * @var mac_mu_table::mu_score_tbl_5 + * Please Place Description here. + */ +struct mac_mu_table { + u32 mu_score_tbl_ctrl; + u32 mu_score_tbl_0; + u32 mu_score_tbl_1; + u32 mu_score_tbl_2; + u32 mu_score_tbl_3; + u32 mu_score_tbl_4; + u32 mu_score_tbl_5; +}; + +/** + * @struct mac_ax_ss_dl_grp_upd + * @brief mac_ax_ss_dl_grp_upd + * + * @var mac_ax_ss_dl_grp_upd::grp_valid + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::grp_id + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::is_hwgrp + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::rsvd + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u0 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u1 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u2 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u3 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u4 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u5 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u6 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::macid_u7 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u0 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u1 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u2 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u3 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u4 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u5 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u6 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::ac_bitmap_u7 + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::next_protecttype + * Please Place Description here. + * @var mac_ax_ss_dl_grp_upd::next_rsptype + * Please Place Description here. + */ +struct mac_ax_ss_dl_grp_upd { + u8 grp_valid:1; //0: non valid 1: valid + u8 grp_id:5; //grp 0~16 + u8 is_hwgrp:1; + u8 rsvd:1; + u8 macid_u0; + u8 macid_u1; + u8 macid_u2; + u8 macid_u3; + u8 macid_u4; + u8 macid_u5; + u8 macid_u6; + u8 macid_u7; + u8 ac_bitmap_u0:4; + u8 ac_bitmap_u1:4; + u8 ac_bitmap_u2:4; + u8 ac_bitmap_u3:4; + u8 ac_bitmap_u4:4; + u8 ac_bitmap_u5:4; + u8 ac_bitmap_u6:4; + u8 ac_bitmap_u7:4; + u8 next_protecttype:4; + u8 next_rsptype:4; +}; + +/** + * @struct mac_ax_ss_ul_grp_upd + * @brief mac_ax_ss_ul_grp_upd + * + * @var mac_ax_ss_ul_grp_upd::macid_u0 + * Please Place Description here. + * @var mac_ax_ss_ul_grp_upd::macid_u1 + * Please Place Description here. + * @var mac_ax_ss_ul_grp_upd::grp_bitmap + * Please Place Description here. + */ +struct mac_ax_ss_ul_grp_upd { + u8 macid_u0; + u8 macid_u1; + u16 grp_bitmap; +}; + +/** + * @struct mac_ax_ss_ul_sta_upd + * @brief mac_ax_ss_ul_sta_upd + * + * @var mac_ax_ss_ul_sta_upd::mode + * Please Place Description here. + * @var mac_ax_ss_ul_sta_upd::rsvd + * Please Place Description here. + * @var mac_ax_ss_ul_sta_upd::macid + * Please Place Description here. + * @var mac_ax_ss_ul_sta_upd::bsr_len + * Please Place Description here. + */ +struct mac_ax_ss_ul_sta_upd { + u32 mode:8; //0:del; 1: add + u32 rsvd:24; + u8 macid[4]; + u16 bsr_len[2]; +}; + +/** + * @struct mac_ax_2nav_info + * @brief mac_ax_2nav_info + * + * @var mac_ax_2nav_info::plcp_upd_nav_en + * Please Place Description here. + * @var mac_ax_2nav_info::tgr_fram_upd_nav_en + * Please Place Description here. + * @var mac_ax_2nav_info::nav_up + * Please Place Description here. + */ +struct mac_ax_2nav_info { + u8 plcp_upd_nav_en; + u8 tgr_fram_upd_nav_en; + u8 nav_up; +}; + +/** + * @struct mac_ax_bcn_info + * @brief mac_ax_bcn_info + * + * @var mac_ax_bcn_info::port + * Please Place Description here. + * @var mac_ax_bcn_info::mbssid + * Please Place Description here. + * @var mac_ax_bcn_info::band + * Please Place Description here. + * @var mac_ax_bcn_info::grp_ie_ofst + * Please Place Description here. + * @var mac_ax_bcn_info::macid + * Please Place Description here. + * @var mac_ax_bcn_info::ssn_sel + * Please Place Description here. + * @var mac_ax_bcn_info::ssn_mode + * Please Place Description here. + * @var mac_ax_bcn_info::rate_sel + * Please Place Description here. + * @var mac_ax_bcn_info::txpwr + * Please Place Description here. + * @var mac_ax_bcn_info::txinfo_ctrl_en + * Please Place Description here. + * @var mac_ax_bcn_info::ntx_path_en + * Please Place Description here. + * @var mac_ax_bcn_info::path_map_a + * Please Place Description here. + * @var mac_ax_bcn_info::path_map_b + * Please Place Description here. + * @var mac_ax_bcn_info::path_map_c + * Please Place Description here. + * @var mac_ax_bcn_info::path_map_d + * Please Place Description here. + * @var mac_ax_bcn_info::antsel_a + * Please Place Description here. + * @var mac_ax_bcn_info::antsel_b + * Please Place Description here. + * @var mac_ax_bcn_info::antsel_c + * Please Place Description here. + * @var mac_ax_bcn_info::antsel_d + * Please Place Description here. + * @var mac_ax_bcn_info::sw_tsf + * Please Place Description here. + * @var mac_ax_bcn_info::pld_buf + * Please Place Description here. + * @var mac_ax_bcn_info::pld_len + * Please Place Description here. + * @var mac_ax_bcn_info::csa_ofst + * Please Place Description here. + */ +struct mac_ax_bcn_info { + u8 port; + u8 mbssid; + u8 band; + u8 grp_ie_ofst; + u8 macid; + u8 ssn_sel; + u8 ssn_mode; + u16 rate_sel; + u8 txpwr; + u8 txinfo_ctrl_en; + u8 ntx_path_en; + u8 path_map_a; + u8 path_map_b; + u8 path_map_c; + u8 path_map_d; + u8 antsel_a; + u8 antsel_b; + u8 antsel_c; + u8 antsel_d; + u8 sw_tsf; + u8 *pld_buf; + u16 pld_len; + u16 csa_ofst; +}; + +/** + * @struct mac_ax_twt_para + * @brief mac_ax_twt_para + * + * @var mac_ax_twt_para::nego_tp + * Please Place Description here. + * @var mac_ax_twt_para::act + * Please Place Description here. + * @var mac_ax_twt_para::trig + * Please Place Description here. + * @var mac_ax_twt_para::flow_tp + * Please Place Description here. + * @var mac_ax_twt_para::proct + * Please Place Description here. + * @var mac_ax_twt_para::flow_id + * Please Place Description here. + * @var mac_ax_twt_para::id + * Please Place Description here. + * @var mac_ax_twt_para::wake_exp + * Please Place Description here. + * @var mac_ax_twt_para::band + * Please Place Description here. + * @var mac_ax_twt_para::port + * Please Place Description here. + * @var mac_ax_twt_para::rsp_pm + * Please Place Description here. + * @var mac_ax_twt_para::wake_unit + * Please Place Description here. + * @var mac_ax_twt_para::impt + * Please Place Description here. + * @var mac_ax_twt_para::twtulfixmode + * Please Place Description here. + * @var mac_ax_twt_para::rsvd + * Please Place Description here. + * @var mac_ax_twt_para::wake_man + * Please Place Description here. + * @var mac_ax_twt_para::dur + * Please Place Description here. + * @var mac_ax_twt_para::trgt_l + * Please Place Description here. + * @var mac_ax_twt_para::trgt_h + * Please Place Description here. + */ +struct mac_ax_twt_para { + enum mac_ax_twt_nego_tp nego_tp; + enum mac_ax_twt_act_tp act; + u32 trig:1; + u32 flow_tp:1; + u32 proct:1; + u32 flow_id:3; + u32 id:3; + u32 wake_exp:5; + u32 band:1; + u32 port:3; + u32 rsp_pm:1; + u32 wake_unit:1; + u32 impt:1; + u32 twtulfixmode:3; + u32 rsvd:8; + + u16 wake_man; + u8 dur; + u32 trgt_l; + u32 trgt_h; +}; + +/** + * @struct mac_ax_twtact_para + * @brief mac_ax_twtact_para + * + * @var mac_ax_twtact_para::act + * Please Place Description here. + * @var mac_ax_twtact_para::macid + * Please Place Description here. + * @var mac_ax_twtact_para::id + * Please Place Description here. + * @var mac_ax_twtact_para::rsvd + * Please Place Description here. + */ +struct mac_ax_twtact_para { + enum mac_ax_twtact_act_tp act; + u16 macid; + u8 id:3; + u8 rsvd:5; +}; + +/** + * @struct mac_ax_twtanno_para + * @brief mac_ax_twtanno_para + * + * @var mac_ax_twtanno_para::macid + * Please Place Description here. + */ +struct mac_ax_twtanno_para { + u8 macid; +}; + +/** + * @struct mac_ax_twtanno_c2hpara + * @brief mac_ax_twtanno_c2hpara + * + * @var mac_ax_twtanno_c2hpara::wait_case + * Please Place Description here. + * @var mac_ax_twtanno_c2hpara::rsvd + * Please Place Description here. + * @var mac_ax_twtanno_c2hpara::macid0 + * Please Place Description here. + * @var mac_ax_twtanno_c2hpara::macid1 + * Please Place Description here. + * @var mac_ax_twtanno_c2hpara::macid2 + * Please Place Description here. + */ +struct mac_ax_twtanno_c2hpara { + u32 wait_case:4; + u32 rsvd:4; + u32 macid0:8; + u32 macid1:8; + u32 macid2:8; +}; + +/** + * @struct mac_ax_port_cfg_para + * @brief mac_ax_port_cfg_para + * + * @var mac_ax_port_cfg_para::mbssid_idx + * Please Place Description here. + * @var mac_ax_port_cfg_para::val + * Please Place Description here. + * @var mac_ax_port_cfg_para::port + * Please Place Description here. + * @var mac_ax_port_cfg_para::band + * Please Place Description here. + */ +struct mac_ax_port_cfg_para { + u32 mbssid_idx; + u32 val; + u8 port; + u8 band; +}; + +/** + * @struct mac_ax_port_init_para + * @brief mac_ax_port_init_para + * + * @var mac_ax_port_init_para::port_idx + * Please Place Description here. + * @var mac_ax_port_init_para::band_idx + * Please Place Description here. + * @var mac_ax_port_init_para::net_type + * Please Place Description here. + * @var mac_ax_port_init_para::dtim_period + * Please Place Description here. + * @var mac_ax_port_init_para::mbid_num + * Please Place Description here. + * @var mac_ax_port_init_para::bss_color + * Please Place Description here. + * @var mac_ax_port_init_para::bcn_interval + * Please Place Description here. + * @var mac_ax_port_init_para::hiq_win + * Please Place Description here. + */ +struct mac_ax_port_init_para { + enum mac_ax_port port_idx; + enum mac_ax_band band_idx; + enum mac_ax_net_type net_type; + u8 dtim_period; + u8 mbid_num; + u8 bss_color; + u16 bcn_interval; + u32 hiq_win; +}; + +/** + * @struct mac_ax_fw_log + * @brief mac_ax_fw_log + * + * @var mac_ax_fw_log::level + * Please Place Description here. + * @var mac_ax_fw_log::output + * Please Place Description here. + * @var mac_ax_fw_log::comp + * Please Place Description here. + * @var mac_ax_fw_log::comp_ext + * Please Place Description here. + */ +struct mac_ax_fw_log { +#define MAC_AX_FL_LV_OFF 0 +#define MAC_AX_FL_LV_CRT 1 +#define MAC_AX_FL_LV_SER 2 +#define MAC_AX_FL_LV_WARN 3 +#define MAC_AX_FL_LV_LOUD 4 +#define MAC_AX_FL_LV_TR 5 + u32 level; +#define MAC_AX_FL_LV_UART BIT(0) +#define MAC_AX_FL_LV_C2H BIT(1) +#define MAC_AX_FL_LV_SNI BIT(2) + u32 output; +#define MAC_AX_FL_COMP_VER BIT(0) +#define MAC_AX_FL_COMP_INIT BIT(1) +#define MAC_AX_FL_COMP_TASK BIT(2) +#define MAC_AX_FL_COMP_CNS BIT(3) +#define MAC_AX_FL_COMP_H2C BIT(4) +#define MAC_AX_FL_COMP_C2H BIT(5) +#define MAC_AX_FL_COMP_TX BIT(6) +#define MAC_AX_FL_COMP_RX BIT(7) +#define MAC_AX_FL_COMP_IPSEC BIT(8) +#define MAC_AX_FL_COMP_TIMER BIT(9) +#define MAC_AX_FL_COMP_DBGPKT BIT(10) +#define MAC_AX_FL_COMP_PS BIT(11) +#define MAC_AX_FL_COMP_ERROR BIT(12) +#define MAC_AX_FL_COMP_WOWLAN BIT(13) +#define MAC_AX_FL_COMP_SECURE_BOOT BIT(14) +#define MAC_AX_FL_COMP_BTC BIT(15) +#define MAC_AX_FL_COMP_BB BIT(16) +#define MAC_AX_FL_COMP_TWT BIT(17) +#define MAC_AX_FL_COMP_RF BIT(18) +#define MAC_AX_FL_COMP_MCC BIT(20) + u32 comp; + u32 comp_ext; +}; + +/** + * @struct mac_ax_dbgpkg + * @brief mac_ax_dbgpkg + * + * @var mac_ax_dbgpkg::ss_dbg_0 + * Please Place Description here. + * @var mac_ax_dbgpkg::ss_dbg_1 + * Please Place Description here. + */ +struct mac_ax_dbgpkg { + u32 ss_dbg_0; + u32 ss_dbg_1; +}; + +/** + * @struct mac_ax_dbgport_hw_en + * @brief mac_ax_dbgport_hw_en + * + * @var mac_ax_dbgport_hw_en::system + * Please Place Description here. + * @var mac_ax_dbgport_hw_en::wl_cpu + * Please Place Description here. + */ +struct mac_ax_dbgport_hw_en { + u8 system:1; + u8 pinmux:1; + u8 loader:1; + u8 hmux:1; + u8 pcie:1; + u8 usb:1; + u8 sdio:1; + u8 bt:1; + + // WLAN_MAC + u8 axidma:1; + u8 wlphydbg_gpio:1; + u8 btcoexist:1; + u8 ltecoex:1; + u8 wlphydbg:1; + u8 wlan_mac_reg:1; + u8 wlan_mac_pmc:1; + u8 calib_top:1; + + //DMAC + u16 dispatcher_top:1; + u16 wde_dle:1; + u16 ple_dle:1; + u16 wdrls:1; + u16 dle_cpuio:1; + u16 bbrpt:1; + u16 txpktctl:1; + u16 pktbuffer:1; + + u16 dmac_table:1; + u16 sta_scheduler:1; + u16 dmac_pktin:1; + u16 wsec_top:1; + u16 mpdu_processor:1; + u16 dmac_apb_bridge:1; + u16 ltr_ctrl:1; + u16 rsvd0:1; + + //CMAC 0 + u8 cmac0_cmac_dma_top:1; + u8 cmac0_ptcltop:1; + u8 cmac0_schedulertop:1; + u8 cmac0_txpwr_ctrl:1; + u8 cmac0_cmac_apb_bridge:1; + u8 cmac0_mactx:1; + u8 cmac0_macrx:1; + u8 cmac0_wmac_trxptcl:1; + + //CMAC 1 + u8 cmac1_cmac_dma_top:1; + u8 cmac1_ptcltop:1; + u8 cmac1_schedulertop:1; + u8 cmac1_txpwr_ctrl:1; + u8 cmac1_cmac_apb_bridge:1; + u8 cmac1_mactx:1; + u8 cmac1_macrx:1; + u8 cmac1_wmac_trxptcl:1; + + //others + u8 cmac_share:1; + u8 wl_cpu:1; + u8 rsvd1:6; +}; + +/** + * @struct mac_ax_dbgpkg_en + * @brief mac_ax_dbgpkg_en + * + * @var mac_ax_dbgpkg_en::ss_dbg + * Please Place Description here. + * @var mac_ax_dbgpkg_en::dle_dbg + * Please Place Description here. + * @var mac_ax_dbgpkg_en::dmac_dbg + * Please Place Description here. + * @var mac_ax_dbgpkg_en::cmac_dbg + * Please Place Description here. + * @var mac_ax_dbgpkg_en::mac_dbg_port + * Please Place Description here. + * @var mac_ax_dbgpkg_en::plersvd_dbg + * Please Place Description here. + * @var mac_ax_dbgpkg_en::dp_hw_en + * Please Place Description here. + */ +struct mac_ax_dbgpkg_en { + u8 ss_dbg:1; + u8 dle_dbg:1; + u8 dmac_dbg:1; + u8 cmac_dbg:1; + u8 mac_dbg_port:1; + u8 plersvd_dbg:1; + u8 tx_flow_dbg:1; + u8 rsvd:1; + struct mac_ax_dbgport_hw_en dp_hw_en; +}; + +/** + * @struct mac_ax_dbgport_hw + * @brief mac_ax_dbgport_hw + * + * @var mac_ax_dbgport_hw::dbg_sel + * valid value: enum mac_ax_dbgport_sel + * @var mac_ax_dbgport_hw::dbg_sel_16b + * valid value: enum mac_ax_dbgport_sel0_16b + * enum mac_ax_dbgport_sel1_16b + * @var mac_ax_dbgport_hw::dbg_sel_4b + * valid value: enum mac_ax_dbgport_sel_4b + * @var mac_ax_dbgport_hw::intn_idx + * valid value: #define MAC_AX_DP_INTN_IDX_XXX_XXX + * @var mac_ax_dbgport_hw::mode + * 0x0: for dump mode + * 0x1: for LA mode + * @var mac_ax_dbgport_hw::rsp_val + * return value: debug port info + */ +struct mac_ax_dbgport_hw { + // input + u8 dbg_sel[MAC_AX_DP_SEL_NUM]; + u8 dbg_sel_16b[MAC_AX_DP_SEL_NUM]; + u8 dbg_sel_4b[MAC_AX_DP_SEL_NUM]; + u8 intn_idx[MAC_AX_DP_SEL_NUM]; + u8 mode; + // output + u32 rsp_val; +}; + +/** + * @struct mac_ax_fwdbg_en + * @brief mac_ax_fwdbg_en + * + * @var mac_ax_fwdbg_en::status_dbg + * Please Place Description here. + * @var mac_ax_fwdbg_en::rsv_ple_dbg + * Please Place Description here. + * @var mac_ax_fwdbg_en::ps_dbg + * Please Place Description here. + */ +struct mac_ax_fwdbg_en { + u8 status_dbg:1; + u8 rsv_ple_dbg:1; + u8 ps_dbg:1; +}; + +union mac_conf_ofld_hioe_param0 { + u32 register_addr; + u32 delay_value; +}; + +union mac_conf_ofld_hioe_param1 { + u16 byte_data_h; + u16 bit_mask; +}; + +union mac_conf_ofld_hioe_param2 { + u16 byte_data_l; + u16 bit_data; +}; + +/** + * @struct mac_conf_ofld_hioe + * @brief mac_conf_ofld_hioe + * + * @var mac_conf_ofld_hioe::hioe_op + * Please Place Description here. + * @var mac_conf_ofld_hioe::inst_type + * Please Place Description here. + * @var mac_conf_ofld_hioe::rsvd + * Please Place Description here. + * @var mac_conf_ofld_hioe::data_mode + * Please Place Description here. + * @var mac_conf_ofld_hioe::param0 + * Please Place Description here. + * @var mac_conf_ofld_hioe::param1 + * Please Place Description here. + * @var mac_conf_ofld_hioe::param2 + * Please Place Description here. + */ +struct mac_conf_ofld_hioe { +#define CONF_OFLD_HIOE_OP_RESTORE 0 +#define CONF_OFLD_HIOE_OP_BACKUP 1 +#define CONF_OFLD_HIOE_OP_BOTH 2 + u8 hioe_op; +#define CONF_OFLD_HIOE_INST_IO 0 +#define CONF_OFLD_HIOE_INST_POLLING 1 +#define CONF_OFLD_HIOE_INST_DELAY 2 + u8 inst_type; + u8 rsvd; +#define CONF_OFLD_HIOE_INST_DATA_BYTE 0 +#define CONF_OFLD_HIOE_INST_DATA_BIT 3 + u8 data_mode; + union mac_conf_ofld_hioe_param0 param0; + union mac_conf_ofld_hioe_param1 param1; + union mac_conf_ofld_hioe_param2 param2; +}; + +/** + * @struct mac_conf_ofld_ddma + * @brief mac_conf_ofld_ddma + * + * @var mac_conf_ofld_ddma::ddma_mode + * Please Place Description here. + * @var mac_conf_ofld_ddma::finish + * Please Place Description here. + * @var mac_conf_ofld_ddma::dma_len + * Please Place Description here. + * @var mac_conf_ofld_ddma::dma_src_addr + * Please Place Description here. + * @var mac_conf_ofld_ddma::dma_dst_addr + * Please Place Description here. + */ +struct mac_conf_ofld_ddma { +#define CONF_OFLD_DDMA_OP_RESTORE 0 +#define CONF_OFLD_DDMA_OP_BACKUP 1 +#define CONF_OFLD_DDMA_OP_BOTH 2 + u8 ddma_mode; + u8 finish; + u16 dma_len; + u32 dma_src_addr; + u32 dma_dst_addr; +}; + +union mac_conf_ofld_req_bd { + struct mac_conf_ofld_hioe hioe; + struct mac_conf_ofld_ddma ddma; +}; + +/** + * @struct mac_ax_conf_ofld_req + * @brief mac_ax_conf_ofld_req + * + * @var mac_ax_conf_ofld_req::device + * Please Place Description here. + * @var mac_ax_conf_ofld_req::rsvd + * Please Place Description here. + * @var mac_ax_conf_ofld_req::req + * Please Place Description here. + */ +struct mac_ax_conf_ofld_req { +#define CONF_OFLD_DEVICE_HIOE 0 +#define CONF_OFLD_DEVICE_DDMA 1 + u32 device:8; + u32 rsvd:24; + union mac_conf_ofld_req_bd req; +}; + +/** + * @struct mac_defeature_value + * @brief mac_defeature_value + * + * @var mac_defeature_value::rx_spatial_stream + * Please Place Description here. + * @var mac_defeature_value::bandwidth + * Please Place Description here. + * @var mac_defeature_value::tx_spatial_stream + * Please Place Description here. + * @var mac_defeature_value::protocol_80211 + * Please Place Description here. + * @var mac_defeature_value::NIC_router + * Please Place Description here. + * @var mac_defeature_value::wl_func_support + * Please Place Description here. + * @var mac_defeature_value::hw_special_type + * Please Place Description here. + * @var mac_defeature_value::uuid + * Please Place Description here. + */ +struct mac_defeature_value { + u8 rx_spatial_stream; + u8 bandwidth; + u8 tx_spatial_stream; + u8 protocol_80211; + u8 NIC_router; + u8 wl_func_support; + u8 hw_special_type; + u32 uuid; +}; + +/** + * @struct mac_ax_wowlan_info + * @brief mac_ax_wowlan_info + * + * @var mac_ax_wowlan_info::aoac_report + * Please Place Description here. + */ +struct mac_ax_wowlan_info { + u8 *aoac_report; +}; + +/** + * @struct mac_ax_p2p_info + * @brief mac_ax_p2p_info + * + * @var mac_ax_p2p_info::macid + * Please Place Description here. + * @var mac_ax_p2p_info::p2pid + * Please Place Description here. + */ +struct mac_ax_p2p_info { + u8 macid; + + u8 run:1; + u8 wait_dack:1; + u8 rsvd:6; +}; + +/** + * @struct mac_ax_p2p_act_info + * @brief mac_ax_p2p_act_info + * + * @var mac_ax_p2p_act_info::macid + * Please Place Description here. + * @var mac_ax_p2p_act_info::noaid + * Please Place Description here. + * @var mac_ax_p2p_act_info::act + * Please Place Description here. + * @var mac_ax_p2p_act_info::type + * Please Place Description here. + * @var mac_ax_p2p_act_info::all_slep + * Please Place Description here. + * @var mac_ax_p2p_act_info::srt + * Please Place Description here. + * @var mac_ax_p2p_act_info::itvl + * Please Place Description here. + * @var mac_ax_p2p_act_info::dur + * Please Place Description here. + * @var mac_ax_p2p_act_info::cnt + * Please Place Description here. + * @var mac_ax_p2p_act_info::ctw + * Please Place Description here. + */ +struct mac_ax_p2p_act_info { + u8 macid; + u8 noaid; + u8 act; + u8 type; + u8 all_slep; + u32 srt; + u32 itvl; + u32 dur; + u8 cnt; + u16 ctw; +}; + +struct mac_ax_p2p_macid_info { + u8 main_macid; + u8 ctrl_type; + u8 *bitmap; + u32 bmap_len; +}; + +struct mac_ax_t32_togl_info { + u8 band; + u8 port; + u8 en; + u16 early; +}; + +struct mac_ax_t32_togl_rpt { + u8 band; + u8 port; + u8 valid; + u16 early; + u16 status; + u32 tsf_l; + u32 tsf_h; +}; + +struct mac_ax_port_info { + u8 stat; +#define MAC_AX_PORT_H2C_IDLE 0 +#define MAC_AX_PORT_H2C_BUSY 1 +#define MAC_AX_PORT_H2C_FAIL 2 + u8 h2c_sm; +}; + +struct mac_ax_int_stats { + u32 h2c_reg_uninit; + u32 h2c_pkt_uninit; + u32 c2h_reg_uninit; +}; + +/*-------------------- Define Struct needed to be moved-----------------------*/ + +/** + * @struct mac_ax_tbl_hdr + * @brief mac_ax_tbl_hdr + * + * @var mac_ax_tbl_hdr::rw + * Please Place Description here. + * @var mac_ax_tbl_hdr::idx + * Please Place Description here. + * @var mac_ax_tbl_hdr::offset + * Please Place Description here. + * @var mac_ax_tbl_hdr::len + * Please Place Description here. + * @var mac_ax_tbl_hdr::type + * Please Place Description here. + */ +struct mac_ax_tbl_hdr { + u8 rw:1; + u8 idx:7; + u16 offset:5; + u16 len:10; + u16 type:1; +}; + +/** + * @struct mac_ax_ru_rate_ent + * @brief mac_ax_ru_rate_ent + * + * @var mac_ax_ru_rate_ent::dcm + * Please Place Description here. + * @var mac_ax_ru_rate_ent::ss + * Please Place Description here. + * @var mac_ax_ru_rate_ent::mcs + * Please Place Description here. + */ +struct mac_ax_ru_rate_ent { + u8 dcm:1; + u8 ss:3; + u8 mcs:4; +}; + +/** + * @struct mac_ax_dl_fix_sta_ent + * @brief mac_ax_dl_fix_sta_ent + * + * @var mac_ax_dl_fix_sta_ent::mac_id + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::ru_pos + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::fix_rate + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::fix_coding + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::fix_txbf + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::fix_pwr_fac + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::rsvd0 + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::rate + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::txbf + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::coding + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::pwr_boost_fac + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::rsvd1 + * Please Place Description here. + * @var mac_ax_dl_fix_sta_ent::rsvd2 + * Please Place Description here. + */ +struct mac_ax_dl_fix_sta_ent { + u8 mac_id; + u8 ru_pos[3]; + u8 fix_rate:1; + u8 fix_coding:1; + u8 fix_txbf:1; + u8 fix_pwr_fac:1; + u8 rsvd0: 4; + struct mac_ax_ru_rate_ent rate; + u8 txbf:1; + u8 coding:1; + u8 pwr_boost_fac:5; + u8 rsvd1: 1; + u8 rsvd2; +}; + +/** + * @struct mac_ax_dlru_fixtbl + * @brief mac_ax_dlru_fixtbl + * + * @var mac_ax_dlru_fixtbl::tbl_hdr + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::max_sta_num + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::min_sta_num + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::doppler + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::stbc + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::gi_ltf + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::ma_type + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::fixru_flag + * Please Place Description here. + * @var mac_ax_dlru_fixtbl::sta + * Please Place Description here. + */ +struct mac_ax_dlru_fixtbl { + struct mac_ax_tbl_hdr tbl_hdr; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 doppler:1; + u8 stbc:1; + u8 gi_ltf:3; + u8 ma_type:1; + u8 fixru_flag:1; + struct mac_ax_dl_fix_sta_ent sta[MAC_AX_MAX_RU_NUM]; +}; + +/** + * @struct mac_ax_ul_fix_sta_ent + * @brief mac_ax_ul_fix_sta_ent + * + * @var mac_ax_ul_fix_sta_ent::mac_id + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::ru_pos + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::tgt_rssi + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::fix_tgt_rssi + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::fix_rate + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::fix_coding + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::coding + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::rsvd1 + * Please Place Description here. + * @var mac_ax_ul_fix_sta_ent::rate + * Please Place Description here. + */ +struct mac_ax_ul_fix_sta_ent { + u8 mac_id; + u8 ru_pos[3]; + u8 tgt_rssi[3]; + u8 fix_tgt_rssi: 1; + u8 fix_rate: 1; + u8 fix_coding: 1; + u8 coding: 1; + u8 rsvd1: 4; + struct mac_ax_ru_rate_ent rate; +}; + +/** + * @struct mac_ax_ulru_fixtbl + * @brief mac_ax_ulru_fixtbl + * + * @var mac_ax_ulru_fixtbl::tbl_hdr + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::max_sta_num + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::min_sta_num + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::doppler + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::ma_type + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::gi_ltf + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::stbc + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::fix_tb_t_pe_nom + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::tb_t_pe_nom + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::fixru_flag + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::rsvd + * Please Place Description here. + * @var mac_ax_ulru_fixtbl::sta + * Please Place Description here. + */ +struct mac_ax_ulru_fixtbl { + struct mac_ax_tbl_hdr tbl_hdr; + u8 max_sta_num: 3; + u8 min_sta_num: 3; + u8 doppler: 1; + u8 ma_type: 1; + u8 gi_ltf: 3; + u8 stbc: 1; + u8 fix_tb_t_pe_nom: 1; + u8 tb_t_pe_nom: 2; + u8 fixru_flag: 1; + u16 rsvd; + struct mac_ax_ul_fix_sta_ent sta[MAC_AX_MAX_RU_NUM]; +}; + +/** + * @struct mac_ax_scanofld_chinfo + * @brief mac_ax_scanofld_chinfo + * + * @var mac_ax_scanofld_chinfo::period + * how long to stay on this ch. unit: ms + * @var mac_ax_scanofld_chinfo::dwell_time + * dwell time if recv bcn. unit: ms. set 0 to disable dwell + * @var mac_ax_scanofld_chinfo::central_ch + * central ch + * @var mac_ax_scanofld_chinfo::pri_ch + * pri ch + * @var mac_ax_scanofld_chinfo::bw + * bandwidth + * @var mac_ax_scanofld_chinfo::c2h_notify_dwell + * notify if dwell + * @var mac_ax_scanofld_chinfo::c2h_notify_preTX + * notify before tx pkt + * @var mac_ax_scanofld_chinfo::c2h_notify_postTX + * notify after tx pkt + * @var mac_ax_scanofld_chinfo::c2h_notify_enterCH + * notify when entering ch + * @var mac_ax_scanofld_chinfo::c2h_notify_leaveCH + * notify when leaving ch + * @var mac_ax_scanofld_chinfo::num_addition_pkt + * num of additional pkt to send. Max=8 + * @var mac_ax_scanofld_chinfo::tx_pkt + * whether tx probe req + additional pkt or not + * @var mac_ax_scanofld_chinfo::pause_tx_data + * wherther disable tx (except manage pkt) after sending probe req + * @var mac_ax_scanofld_chinfo::rsvd0 + * Please Place Description here. + * @var mac_ax_scanofld_chinfo::rsvd1 + * Please Place Description here. + * @var mac_ax_scanofld_chinfo::additional_pkt_id + * id of additional pkts to send + */ +#pragma pack(push) +#pragma pack(1) +struct mac_ax_scanofld_chinfo { + /* dword 0 */ + u8 period; + u8 dwell_time; + u8 central_ch; + u8 pri_ch; + /* dword 1 */ + u8 bw: 3; + u8 c2h_notify_dwell: 1; + u8 c2h_notify_preTX: 1; + u8 c2h_notify_postTX: 1; + u8 c2h_notify_enterCH: 1; + u8 c2h_notify_leaveCH: 1; + u8 num_addition_pkt:4; + u8 tx_pkt: 1; + u8 pause_tx_data: 1; + u8 rsvd0: 2; + u16 rsvd1; + /* dword 2 2*/ + u8 additional_pkt_id[SCANOFLD_MAX_ADDITION_PKT_NUM]; +}; + +#pragma pack(pop) + +/** + * @struct mac_ax_scanofld_param + * @brief mac_ax_scanofld_param + * + * @var mac_ax_scanofld_param::macid + * macid + * @var mac_ax_scanofld_param::norm_cy + * normal cycle. available when scan_type=2 + * @var mac_ax_scanofld_param::port_id + * port id + * @var mac_ax_scanofld_param::band + * band + * @var mac_ax_scanofld_param::operation + * 1: start scanning. 0: stop. 2: set param + * @var mac_ax_scanofld_param::rsvd0 + * rsvd + * @var mac_ax_scanofld_param::c2h_end + * whether notify when scan end + * @var mac_ax_scanofld_param::target_ch_mode + * whether switch to target (op) channel after walking through list. available when scan_type!=3 + * @var mac_ax_scanofld_param::start_mode + * 0: start immediatly. 1: start at assigned TSF + * @var mac_ax_scanofld_param::scan_type + * 0: scan once. + * 1: normal repeat mode. period = normal_pd. + * 2: normal_slow repeat mode. normal_pd for norm_cy times, then slow_pd + * 3: seamless repeat mode + * @var mac_ax_scanofld_param::target_ch_bw + * BW of target (op) channel. available when target_ch_mode = 1 + * @var mac_ax_scanofld_param::target_pri_ch + * pri ch of target (op) channel. available when target_ch_mode = 1 + * @var mac_ax_scanofld_param::target_central_ch + * central ch of target (op) channel. available when target_ch_mode = 1 + * @var mac_ax_scanofld_param::probe_req_pkt_id + * offloaded pkt id of probe request + * @var mac_ax_scanofld_param::norm_pd + * normal period. available when scan_type = 1,2 + * @var mac_ax_scanofld_param::slow_pd + * slow period. available when scan_type = 2 + * @var mac_ax_scanofld_param::tsf_high + * higher 32 bit of start tsf. available when start_mode = 1 + * @var mac_ax_scanofld_param::tsf_low + * lower 32 bit of start tsf. available when start_mode = 1 + */ +struct mac_ax_scanofld_param { + /* dword0 */ + u32 macid:8; + u32 norm_cy:8; + u32 port_id:3; + u32 band:1; + u32 operation:2; + u32 rsvd0:10; + /* dword1 */ + u32 c2h_end:1; + u32 target_ch_mode:1; + u32 start_mode:1; + u32 scan_type:2; + u32 target_ch_bw:3; + u32 target_pri_ch:8; + u32 target_central_ch:8; + u32 probe_req_pkt_id:8; + /* dword2 */ + u32 norm_pd:16; + u32 slow_pd:16; + /* dword3 */ + u32 tsf_high; + /* dword4 */ + u32 tsf_low; +}; + +/** + * @struct mac_ax_scanofld_info + * @brief mac_ax_scanofld_info + * + * @var mac_ax_scanofld_info::list + * halmac-hold CHlist + * @var mac_ax_scanofld_info::HalmacChListBusy + * halmac CHlist is busy or not + * @var mac_ax_scanofld_info::FwChListBusy + * fw CHlist is busy or not + * @var mac_ax_scanofld_info::clearHalmacList + * clear halmac-hold CHlist after sending to fw or not + * @var mac_ax_scanofld_info::scanBusy + * fw scanning or not + */ +struct mac_ax_scanofld_info{ + struct scan_chinfo_list *list; + mac_ax_mutex drv_chlist_state_lock; + mac_ax_mutex fw_chlist_state_lock; + u8 drv_chlist_busy; + u8 fw_chlist_busy; + u8 clear_drv_ch_list; + u8 fw_scan_busy; +}; + +/*--------------------END Define Struct needed to be moved--------------------*/ +/*--------------------Define HCI related structure----------------------------*/ + +/** + * @struct mac_ax_hfc_ch_cfg + * @brief mac_ax_hfc_ch_cfg + * + * @var mac_ax_hfc_ch_cfg::min + * Please Place Description here. + * @var mac_ax_hfc_ch_cfg::max + * Please Place Description here. + * @var mac_ax_hfc_ch_cfg::grp + * Please Place Description here. + */ +struct mac_ax_hfc_ch_cfg { + u16 min; + u16 max; +#define grp_0 0 +#define grp_1 1 +#define grp_num 2 + u8 grp; +}; + +/** + * @struct mac_ax_hfc_ch_info + * @brief mac_ax_hfc_ch_info + * + * @var mac_ax_hfc_ch_info::aval + * Please Place Description here. + * @var mac_ax_hfc_ch_info::used + * Please Place Description here. + */ +struct mac_ax_hfc_ch_info { + u16 aval; + u16 used; +}; + +/** + * @struct mac_ax_hfc_pub_cfg + * @brief mac_ax_hfc_pub_cfg + * + * @var mac_ax_hfc_pub_cfg::group0 + * Please Place Description here. + * @var mac_ax_hfc_pub_cfg::group1 + * Please Place Description here. + * @var mac_ax_hfc_pub_cfg::pub_max + * Please Place Description here. + * @var mac_ax_hfc_pub_cfg::wp_thrd + * Please Place Description here. + */ +struct mac_ax_hfc_pub_cfg { + u16 group0; + u16 group1; + u16 pub_max; + u16 wp_thrd; +}; + +/** + * @struct mac_ax_hfc_pub_info + * @brief mac_ax_hfc_pub_info + * + * @var mac_ax_hfc_pub_info::g0_used + * Please Place Description here. + * @var mac_ax_hfc_pub_info::g1_used + * Please Place Description here. + * @var mac_ax_hfc_pub_info::g0_aval + * Please Place Description here. + * @var mac_ax_hfc_pub_info::g1_aval + * Please Place Description here. + * @var mac_ax_hfc_pub_info::pub_aval + * Please Place Description here. + * @var mac_ax_hfc_pub_info::wp_aval + * Please Place Description here. + */ +struct mac_ax_hfc_pub_info { + u16 g0_used; + u16 g1_used; + u16 g0_aval; + u16 g1_aval; + u16 pub_aval; + u16 wp_aval; +}; + +/** + * @struct mac_ax_hfc_prec_cfg + * @brief mac_ax_hfc_prec_cfg + * + * @var mac_ax_hfc_prec_cfg::ch011_prec + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::h2c_prec + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::wp_ch07_prec + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::wp_ch811_prec + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::ch011_full_cond + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::h2c_full_cond + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::wp_ch07_full_cond + * Please Place Description here. + * @var mac_ax_hfc_prec_cfg::wp_ch811_full_cond + * Please Place Description here. + */ +struct mac_ax_hfc_prec_cfg { + u16 ch011_prec; + u16 h2c_prec; + u16 wp_ch07_prec; + u16 wp_ch811_prec; + u8 ch011_full_cond; + u8 h2c_full_cond; + u8 wp_ch07_full_cond; + u8 wp_ch811_full_cond; +}; + +/** + * @struct mac_ax_hfc_param + * @brief mac_ax_hfc_param + * + * @var mac_ax_hfc_param::en + * Please Place Description here. + * @var mac_ax_hfc_param::h2c_en + * Please Place Description here. + * @var mac_ax_hfc_param::mode + * Please Place Description here. + * @var mac_ax_hfc_param::ch_cfg + * Please Place Description here. + * @var mac_ax_hfc_param::ch_info + * Please Place Description here. + * @var mac_ax_hfc_param::pub_cfg + * Please Place Description here. + * @var mac_ax_hfc_param::pub_info + * Please Place Description here. + * @var mac_ax_hfc_param::prec_cfg + * Please Place Description here. + */ +struct mac_ax_hfc_param { + u8 en; + u8 h2c_en; + u8 mode; + struct mac_ax_hfc_ch_cfg *ch_cfg; + struct mac_ax_hfc_ch_info *ch_info; + struct mac_ax_hfc_pub_cfg *pub_cfg; + struct mac_ax_hfc_pub_info *pub_info; + struct mac_ax_hfc_prec_cfg *prec_cfg; +}; + +/** + * @struct mac_ax_sdio_tx_info + * @brief mac_ax_sdio_tx_info + * + * @var mac_ax_sdio_tx_info::total_size + * Please Place Description here. + * @var mac_ax_sdio_tx_info::dma_txagg_num + * Please Place Description here. + * @var mac_ax_sdio_tx_info::ch_dma + * Please Place Description here. + * @var mac_ax_sdio_tx_info::pkt_size + * Please Place Description here. + * @var mac_ax_sdio_tx_info::wp_offset + * Please Place Description here. + * @var mac_ax_sdio_tx_info::chk_cnt + * Please Place Description here. + * @var mac_ax_sdio_tx_info::wde_rqd_num + * Please Place Description here. + * @var mac_ax_sdio_tx_info::ple_rqd_num + * Please Place Description here. + */ +struct mac_ax_sdio_tx_info { + u32 total_size; + u8 dma_txagg_num; + u8 ch_dma; + u8 *pkt_size; + u8 *wp_offset; + u8 chk_cnt; + u16 wde_rqd_num; + u16 ple_rqd_num; +}; + +/** + * @struct mac_ax_sdio_clk_mon_cfg + * @brief mac_ax_sdio_clk_mon_cfg + * + * @var mac_ax_sdio_clk_mon_cfg::mon + * Please Place Description here. + * @var mac_ax_sdio_clk_mon_cfg::cycle + * Please Place Description here. + */ +struct mac_ax_sdio_clk_mon_cfg { + enum mac_ax_sdio_clk_mon mon; + u32 cycle; +}; + +/** + * @struct mac_ax_pcie_ltr_rx_th_ctrl + * @brief mac_ax_pcie_ltr_rx_th_ctrl + * + * @var mac_ax_pcie_ltr_rx_th_ctrl::ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_rx_th_ctrl::val + * Please Place Description here. + */ +struct mac_ax_pcie_ltr_rx_th_ctrl { + enum mac_ax_pcie_func_ctrl ctrl; + u16 val; +}; + +/** + * @struct mac_ax_pcie_ltr_lat_ctrl + * @brief mac_ax_pcie_ltr_lat_ctrl + * + * @var mac_ax_pcie_ltr_lat_ctrl::ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_lat_ctrl::val + * Please Place Description here. + */ +struct mac_ax_pcie_ltr_lat_ctrl { + enum mac_ax_pcie_func_ctrl ctrl; + u32 val; +}; + +/** + * @struct mac_ax_pcie_ltr_param + * @brief mac_ax_pcie_ltr_param + * + * @var mac_ax_pcie_ltr_param::write + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::read + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_hw_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_spc_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_idle_timer_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_rx0_th_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_rx1_th_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_idle_lat_ctrl + * Please Place Description here. + * @var mac_ax_pcie_ltr_param::ltr_act_lat_ctrl + * Please Place Description here. + */ +struct mac_ax_pcie_ltr_param { + u8 write; + u8 read; + enum mac_ax_pcie_func_ctrl ltr_ctrl; + enum mac_ax_pcie_func_ctrl ltr_hw_ctrl; + enum mac_ax_pcie_ltr_spc ltr_spc_ctrl; + enum mac_ax_pcie_ltr_idle_timer ltr_idle_timer_ctrl; + struct mac_ax_pcie_ltr_rx_th_ctrl ltr_rx0_th_ctrl; + struct mac_ax_pcie_ltr_rx_th_ctrl ltr_rx1_th_ctrl; + struct mac_ax_pcie_ltr_lat_ctrl ltr_idle_lat_ctrl; + struct mac_ax_pcie_ltr_lat_ctrl ltr_act_lat_ctrl; +}; + +/** + * @struct mac_ax_usb_tx_agg_cfg + * @brief mac_ax_usb_tx_agg_cfg + * + * @var mac_ax_usb_tx_agg_cfg::pkt + * Please Place Description here. + * @var mac_ax_usb_tx_agg_cfg::agg_num + * Please Place Description here. + */ +struct mac_ax_usb_tx_agg_cfg { + u8 *pkt; + u32 agg_num; +}; + +/** + * @struct mac_ax_pcie_cfgspc_param + * @brief mac_ax_pcie_cfgspc_param + * + * @var mac_ax_pcie_cfgspc_param::write + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::read + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::l0s_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::l1_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::l1ss_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::wake_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::crq_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::clkdly_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::l0sdly_ctrl + * Please Place Description here. + * @var mac_ax_pcie_cfgspc_param::l1dly_ctrl + * Please Place Description here. + */ +struct mac_ax_pcie_cfgspc_param { + u8 write; + u8 read; + enum mac_ax_pcie_func_ctrl l0s_ctrl; + enum mac_ax_pcie_func_ctrl l1_ctrl; + enum mac_ax_pcie_func_ctrl l1ss_ctrl; + enum mac_ax_pcie_func_ctrl wake_ctrl; + enum mac_ax_pcie_func_ctrl crq_ctrl; + enum mac_ax_pcie_clkdly clkdly_ctrl; + enum mac_ax_pcie_l0sdly l0sdly_ctrl; + enum mac_ax_pcie_l1dly l1dly_ctrl; +}; + +/** + * @struct mac_ax_rx_agg_thold + * @brief mac_ax_rx_agg_thold + * + * @var mac_ax_rx_agg_thold::drv_define + * Please Place Description here. + * @var mac_ax_rx_agg_thold::timeout + * Please Place Description here. + * @var mac_ax_rx_agg_thold::size + * Please Place Description here. + * @var mac_ax_rx_agg_thold::pkt_num + * Please Place Description here. + */ +struct mac_ax_rx_agg_thold { + u8 drv_define; + u8 timeout; + u8 size; + u8 pkt_num; +}; + +/** + * @struct mac_ax_lifetime_en + * @brief mac_ax_lifetime_en + * + * @var mac_ax_lifetime_en::acq_en + * Please Place Description here. + * @var mac_ax_lifetime_en::mgq_en + * Please Place Description here. + */ +struct mac_ax_lifetime_en { + u8 acq_en; + u8 mgq_en; +}; + +/** + * @struct mac_ax_lifetime_val + * @brief mac_ax_lifetime_val + * + * @var mac_ax_lifetime_val::acq_val_1 + * Please Place Description here. + * @var mac_ax_lifetime_val::acq_val_2 + * Please Place Description here. + * @var mac_ax_lifetime_val::acq_val_3 + * Please Place Description here. + * @var mac_ax_lifetime_val::acq_val_4 + * Please Place Description here. + * @var mac_ax_lifetime_val::mgq_val + * Please Place Description here. + */ +struct mac_ax_lifetime_val { + u16 acq_val_1; + u16 acq_val_2; + u16 acq_val_3; + u16 acq_val_4; + u16 mgq_val; +}; + +/** + * @struct mac_ax_cfg_bw + * @brief mac_ax_cfg_bw + * + * @var mac_ax_cfg_bw::pri_ch + * Please Place Description here. + * @var mac_ax_cfg_bw::central_ch + * Please Place Description here. + * @var mac_ax_cfg_bw::band + * Please Place Description here. + * @var mac_ax_cfg_bw::rsvd + * Please Place Description here. + * @var mac_ax_cfg_bw::cbw + * Please Place Description here. + */ +struct mac_ax_cfg_bw { + u8 pri_ch; + u8 central_ch; + u16 band: 1; + u16 rsvd: 15; + enum channel_width cbw; +}; + +/*-------------------- Define Efuse related structure ------------------------*/ + +/** + * @struct mac_ax_pg_efuse_info + * @brief mac_ax_pg_efuse_info + * + * @var mac_ax_pg_efuse_info::efuse_map + * Please Place Description here. + * @var mac_ax_pg_efuse_info::efuse_map_size + * Please Place Description here. + * @var mac_ax_pg_efuse_info::efuse_mask + * Please Place Description here. + * @var mac_ax_pg_efuse_info::efuse_mask_size + * Please Place Description here. + */ +struct mac_ax_pg_efuse_info { + u8 *efuse_map; + u32 efuse_map_size; + u8 *efuse_mask; + u32 efuse_mask_size; +}; + +/** + * @struct mac_ax_efuse_param + * @brief mac_ax_efuse_param + * + * @var mac_ax_efuse_param::efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::bt_efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::log_efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::bt_log_efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::efuse_end + * Please Place Description here. + * @var mac_ax_efuse_param::bt_efuse_end + * Please Place Description here. + * @var mac_ax_efuse_param::efuse_map_valid + * Please Place Description here. + * @var mac_ax_efuse_param::bt_efuse_map_valid + * Please Place Description here. + * @var mac_ax_efuse_param::log_efuse_map_valid + * Please Place Description here. + * @var mac_ax_efuse_param::bt_log_efuse_map_valid + * Please Place Description here. + * @var mac_ax_efuse_param::auto_ck_en + * Please Place Description here. + * @var mac_ax_efuse_param::dav_efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::dav_log_efuse_map + * Please Place Description here. + * @var mac_ax_efuse_param::dav_efuse_end + * Please Place Description here. + * @var mac_ax_efuse_param::dav_efuse_map_valid + * Please Place Description here. + * @var mac_ax_efuse_param::dav_log_efuse_map_valid + * Please Place Description here. + */ +struct mac_ax_efuse_param { + u8 *efuse_map; + u8 *bt_efuse_map; + u8 *log_efuse_map; + u8 *bt_log_efuse_map; + u32 efuse_end; + u32 bt_efuse_end; + u8 efuse_map_valid; + u8 bt_efuse_map_valid; + u8 log_efuse_map_valid; + u8 bt_log_efuse_map_valid; + u8 auto_ck_en; + u8 *dav_efuse_map; + u8 *dav_log_efuse_map; + u32 dav_efuse_end; + u8 dav_efuse_map_valid; + u8 dav_log_efuse_map_valid; +}; + +/*-------------------- Define offload related Struct -------------------------*/ + +/** + * @struct mac_ax_read_req + * @brief mac_ax_read_req + * + * @var mac_ax_read_req::value_len + * Please Place Description here. + * @var mac_ax_read_req::rsvd0 + * Please Place Description here. + * @var mac_ax_read_req::ls + * Please Place Description here. + * @var mac_ax_read_req::ofld_id + * Please Place Description here. + * @var mac_ax_read_req::entry_num + * Please Place Description here. + * @var mac_ax_read_req::offset + * Please Place Description here. + * @var mac_ax_read_req::rsvd1 + * Please Place Description here. + */ +struct mac_ax_read_req { + u16 value_len:11; + u16 rsvd0: 4; + u16 ls: 1; + u8 ofld_id; + u8 entry_num; + u16 offset; + u16 rsvd1; +}; + +/** + * @struct mac_ax_read_ofld_info + * @brief mac_ax_read_ofld_info + * + * @var mac_ax_read_ofld_info::buf + * Please Place Description here. + * @var mac_ax_read_ofld_info::buf_wptr + * Please Place Description here. + * @var mac_ax_read_ofld_info::last_req + * Please Place Description here. + * @var mac_ax_read_ofld_info::buf_size + * Please Place Description here. + * @var mac_ax_read_ofld_info::avl_buf_size + * Please Place Description here. + * @var mac_ax_read_ofld_info::used_size + * Please Place Description here. + * @var mac_ax_read_ofld_info::req_num + * Please Place Description here. + */ +struct mac_ax_read_ofld_info { + u8 *buf; + u8 *buf_wptr; + struct mac_ax_read_req *last_req; + u32 buf_size; + u32 avl_buf_size; + u32 used_size; + u32 req_num; +}; + +/** + * @struct mac_ax_read_ofld_value + * @brief mac_ax_read_ofld_value + * + * @var mac_ax_read_ofld_value::len + * Please Place Description here. + * @var mac_ax_read_ofld_value::rsvd + * Please Place Description here. + * @var mac_ax_read_ofld_value::buf + * Please Place Description here. + */ +struct mac_ax_read_ofld_value { + u16 len; + u16 rsvd; + u8 *buf; +}; + +/** + * @struct mac_ax_efuse_ofld_info + * @brief mac_ax_efuse_ofld_info + * + * @var mac_ax_efuse_ofld_info::buf + * Please Place Description here. + */ +struct mac_ax_efuse_ofld_info { + u8 *buf; +}; + +/** + * @struct mac_ax_write_req + * @brief mac_ax_write_req + * + * @var mac_ax_write_req::value_len + * Please Place Description here. + * @var mac_ax_write_req::rsvd0 + * Please Place Description here. + * @var mac_ax_write_req::polling + * Please Place Description here. + * @var mac_ax_write_req::mask_en + * Please Place Description here. + * @var mac_ax_write_req::ls + * Please Place Description here. + * @var mac_ax_write_req::ofld_id + * Please Place Description here. + * @var mac_ax_write_req::entry_num + * Please Place Description here. + * @var mac_ax_write_req::offset + * Please Place Description here. + * @var mac_ax_write_req::rsvd1 + * Please Place Description here. + */ +struct mac_ax_write_req { + u16 value_len:11; + u16 rsvd0: 2; + u16 polling: 1; + u16 mask_en: 1; + u16 ls: 1; + u8 ofld_id; + u8 entry_num; + u16 offset; + u16 rsvd1; +}; + +/** + * @struct mac_ax_write_ofld_info + * @brief mac_ax_write_ofld_info + * + * @var mac_ax_write_ofld_info::buf + * Please Place Description here. + * @var mac_ax_write_ofld_info::buf_wptr + * Please Place Description here. + * @var mac_ax_write_ofld_info::last_req + * Please Place Description here. + * @var mac_ax_write_ofld_info::buf_size + * Please Place Description here. + * @var mac_ax_write_ofld_info::avl_buf_size + * Please Place Description here. + * @var mac_ax_write_ofld_info::used_size + * Please Place Description here. + * @var mac_ax_write_ofld_info::req_num + * Please Place Description here. + */ +struct mac_ax_write_ofld_info { + u8 *buf; + u8 *buf_wptr; + struct mac_ax_write_req *last_req; + u32 buf_size; + u32 avl_buf_size; + u32 used_size; + u32 req_num; +}; + +/** + * @struct mac_ax_conf_ofld_info + * @brief mac_ax_conf_ofld_info + * + * @var mac_ax_conf_ofld_info::buf + * Please Place Description here. + * @var mac_ax_conf_ofld_info::buf_wptr + * Please Place Description here. + * @var mac_ax_conf_ofld_info::buf_size + * Please Place Description here. + * @var mac_ax_conf_ofld_info::avl_buf_size + * Please Place Description here. + * @var mac_ax_conf_ofld_info::used_size + * Please Place Description here. + * @var mac_ax_conf_ofld_info::req_num + * Please Place Description here. + */ +struct mac_ax_conf_ofld_info { + u8 *buf; + u8 *buf_wptr; + u32 buf_size; + u32 avl_buf_size; + u32 used_size; + u16 req_num; +}; + +/** + * @struct mac_ax_pkt_ofld_info + * @brief mac_ax_pkt_ofld_info + * + * @var mac_ax_pkt_ofld_info::last_op + * Please Place Description here. + * @var mac_ax_pkt_ofld_info::free_id_count + * Please Place Description here. + * @var mac_ax_pkt_ofld_info::used_id_count + * Please Place Description here. + * @var mac_ax_pkt_ofld_info::id_bitmap + * Please Place Description here. + */ +struct mac_ax_pkt_ofld_info { +#define PKT_OFLD_MAX_COUNT 256 + u8 last_op; + u16 free_id_count; + u16 used_id_count; + u8 id_bitmap[PKT_OFLD_MAX_COUNT >> 3]; +}; + +/** + * @struct mac_ax_pkt_ofld_pkt + * @brief mac_ax_pkt_ofld_pkt + * + * @var mac_ax_pkt_ofld_pkt::pkt_id + * Please Place Description here. + * @var mac_ax_pkt_ofld_pkt::rsvd + * Please Place Description here. + * @var mac_ax_pkt_ofld_pkt::pkt_len + * Please Place Description here. + * @var mac_ax_pkt_ofld_pkt::pkt + * Please Place Description here. + */ +struct mac_ax_pkt_ofld_pkt { + u8 pkt_id; + u8 rsvd; + u16 pkt_len; + u8 *pkt; +}; + +/** + * @struct mac_ax_general_pkt_ids + * @brief mac_ax_general_pkt_ids + * + * @var mac_ax_general_pkt_ids::macid + * Please Place Description here. + * @var mac_ax_general_pkt_ids::probersp + * Please Place Description here. + * @var mac_ax_general_pkt_ids::pspoll + * Please Place Description here. + * @var mac_ax_general_pkt_ids::nulldata + * Please Place Description here. + * @var mac_ax_general_pkt_ids::qosnull + * Please Place Description here. + * @var mac_ax_general_pkt_ids::cts2self + * Please Place Description here. + * @var mac_ax_general_pkt_ids::probereq + * offloaded probe request pkt id + * @var mac_ax_general_pkt_ids::apcsa + * offloaded CSA frame id + */ +struct mac_ax_general_pkt_ids { + u8 macid; + u8 probersp; + u8 pspoll; + u8 nulldata; + u8 qosnull; + u8 cts2self; + u8 probereq; + u8 apcsa; +}; + +#ifndef CONFIG_FW_IO_OFLD_SUPPORT +/** + * @struct rtw_mac_cmd + * @brief rtw_mac_cmd + * + * @var rtw_mac_cmd::src + * Please Place Description here. + * @var rtw_mac_cmd::type + * Please Place Description here. + * @var rtw_mac_cmd::lc + * Please Place Description here. + * @var rtw_mac_cmd::rf_path + * Please Place Description here. + * @var rtw_mac_cmd::offset + * Please Place Description here. + * @var rtw_mac_cmd::id + * Please Place Description here. + * @var rtw_mac_cmd::value + * Please Place Description here. + * @var rtw_mac_cmd::mask + * Please Place Description here. + */ +struct rtw_mac_cmd { + enum rtw_mac_src_cmd_ofld src; + enum rtw_mac_cmd_type_ofld type; + u8 lc; + enum rtw_mac_rf_path rf_path; + u16 offset; + u16 id; + u32 value; + u32 mask; +}; + +#endif + +/** + * @struct mac_ax_cmd_ofld_info + * @brief mac_ax_cmd_ofld_info + * + * @var mac_ax_cmd_ofld_info::buf + * Please Place Description here. + * @var mac_ax_cmd_ofld_info::end_ptr + * Please Place Description here. + * @var mac_ax_cmd_ofld_info::buf_size + * Please Place Description here. + * @var mac_ax_cmd_ofld_info::avl_buf_size + * Please Place Description here. + * @var mac_ax_cmd_ofld_info::used_size + * Please Place Description here. + * @var mac_ax_cmd_ofld_info::cmd_num + * Please Place Description here. + */ +struct mac_ax_cmd_ofld_info { + u8 *buf; + u8 *buf_wptr; + u8 *last_wptr; + u16 buf_size; + u16 avl_buf_size; + u16 used_size; + u8 cmd_num; + u8 result; + u32 accu_delay; + mac_ax_mutex cmd_ofld_lock; +}; + +/** + * @struct mac_ax_tx_duty_ofld_info + * @brief mac_ax_tx_duty_ofld_info + * + * @var mac_ax_tx_duty_ofld_info::timer_err + * Please Place Description here. + */ +struct mac_ax_tx_duty_ofld_info { + u8 timer_err; +}; + +/*--------------------Define OutSrc related ----------------------------------*/ + +/** + * @struct mac_ax_la_cfg + * @brief mac_ax_la_cfg + * + * @var mac_ax_la_cfg::la_func_en + * Please Place Description here. + * @var mac_ax_la_cfg::la_restart_en + * Please Place Description here. + * @var mac_ax_la_cfg::la_timeout_en + * Please Place Description here. + * @var mac_ax_la_cfg::la_timeout_val + * Please Place Description here. + * @var mac_ax_la_cfg::la_data_loss_imr + * Please Place Description here. + * @var mac_ax_la_cfg::la_tgr_tu_sel + * Please Place Description here. + * @var mac_ax_la_cfg::la_tgr_time_val + * Please Place Description here. + * @var mac_ax_la_cfg::rsvd + * Please Place Description here. + */ +struct mac_ax_la_cfg { + u32 la_func_en:1; + u32 la_restart_en:1; + u32 la_timeout_en:1; + /* 2'h0: 1s, 2'h1: 2s, 2'h2: 4s, 2'h3: 8s */ + u32 la_timeout_val:2; + /*Error flag mask bit for LA data loss due to pktbuffer busy */ + u32 la_data_loss_imr:1; + /* TU (time unit) = 2^ B_AX_LA_TRIG_TU_SEL */ + u32 la_tgr_tu_sel:4; + /* 6'h0: No delay, 6'h1: 1 TU, 6'h2: 2TU, ??*/ + u32 la_tgr_time_val:7; + u32 rsvd:15; +}; + +/** + * @struct mac_ax_la_status + * @brief mac_ax_la_status + * + * @var mac_ax_la_status::la_buf_wptr + * Please Place Description here. + * @var mac_ax_la_status::la_buf_rndup_ind + * Please Place Description here. + * @var mac_ax_la_status::la_sw_fsmst + * Please Place Description here. + * @var mac_ax_la_status::la_data_loss + * Please Place Description here. + */ +struct mac_ax_la_status { + /* LA data dump finish address = (la_buf_wptr -1) */ + u16 la_buf_wptr; + /*1: round up, 0: No round up */ + u8 la_buf_rndup_ind:1; + /*3'h0: LA idle ; 3'h1: LA start; 3'h2: LA finish stop;*/ + /*3'h3:LA finish timeout; 3'h4: LA re-start*/ + u8 la_sw_fsmst:3; + /* LA data loss due to pktbuffer busy */ + u8 la_data_loss:1; +}; + +/** + * @struct mac_ax_la_buf_param + * @brief mac_ax_la_buf_param + * + * @var mac_ax_la_buf_param::start_addr + * Please Place Description here. + * @var mac_ax_la_buf_param::end_addr + * Please Place Description here. + * @var mac_ax_la_buf_param::la_buf_sel + * Please Place Description here. + */ +struct mac_ax_la_buf_param { + u32 start_addr; + u32 end_addr; + u8 la_buf_sel; /*0: 64KB; 1: 128KB; 2: 192KB; 3: 256KB; 4: 320KB*/ +}; + +/*--------------------Define TRX PKT INFO/RPT---------------------------------*/ + +/** + * @struct mac_ax_pkt_data + * @brief mac_ax_pkt_data + * + * @var mac_ax_pkt_data::wifi_seq + * Please Place Description here. + * @var mac_ax_pkt_data::hw_ssn_sel + * Please Place Description here. + * @var mac_ax_pkt_data::hw_seq_mode + * Please Place Description here. + * @var mac_ax_pkt_data::chk_en + * Please Place Description here. + * @var mac_ax_pkt_data::hw_amsdu + * Please Place Description here. + * @var mac_ax_pkt_data::shcut_camid + * Please Place Description here. + * @var mac_ax_pkt_data::headerwllc_len + * Please Place Description here. + * @var mac_ax_pkt_data::smh_en + * Please Place Description here. + * @var mac_ax_pkt_data::wd_page + * Please Place Description here. + * @var mac_ax_pkt_data::wp_offset + * Please Place Description here. + * @var mac_ax_pkt_data::wdinfo_en + * Please Place Description here. + * @var mac_ax_pkt_data::hw_aes_iv + * Please Place Description here. + * @var mac_ax_pkt_data::hdr_len + * Please Place Description here. + * @var mac_ax_pkt_data::ch + * Please Place Description here. + * @var mac_ax_pkt_data::macid + * Please Place Description here. + * @var mac_ax_pkt_data::agg_en + * Please Place Description here. + * @var mac_ax_pkt_data::bk + * Please Place Description here. + * @var mac_ax_pkt_data::max_agg_num + * Please Place Description here. + * @var mac_ax_pkt_data::bmc + * Please Place Description here. + * @var mac_ax_pkt_data::lifetime_sel + * Please Place Description here. + * @var mac_ax_pkt_data::ampdu_density + * Please Place Description here. + * @var mac_ax_pkt_data::userate + * Please Place Description here. + * @var mac_ax_pkt_data::data_rate + * Please Place Description here. + * @var mac_ax_pkt_data::data_bw + * Please Place Description here. + * @var mac_ax_pkt_data::er_bw + * Please Place Description here. + * @var mac_ax_pkt_data::data_gi_ltf + * Please Place Description here. + * @var mac_ax_pkt_data::data_er + * Please Place Description here. + * @var mac_ax_pkt_data::data_dcm + * Please Place Description here. + * @var mac_ax_pkt_data::data_stbc + * Please Place Description here. + * @var mac_ax_pkt_data::data_ldpc + * Please Place Description here. + * @var mac_ax_pkt_data::hw_sec_en + * Please Place Description here. + * @var mac_ax_pkt_data::sec_cam_idx + * Please Place Description here. + * @var mac_ax_pkt_data::sec_type + * Please Place Description here. + * @var mac_ax_pkt_data::dis_data_fb + * Please Place Description here. + * @var mac_ax_pkt_data::dis_rts_fb + * Please Place Description here. + * @var mac_ax_pkt_data::tid + * Please Place Description here. + * @var mac_ax_pkt_data::rts_en + * Please Place Description here. + * @var mac_ax_pkt_data::cts2self + * Please Place Description here. + * @var mac_ax_pkt_data::cca_rts + * Please Place Description here. + * @var mac_ax_pkt_data::hw_rts_en + * Please Place Description here. + * @var mac_ax_pkt_data::ndpa + * Please Place Description here. + * @var mac_ax_pkt_data::snd_pkt_sel + * Please Place Description here. + * @var mac_ax_pkt_data::sifs_tx + * Please Place Description here. + * @var mac_ax_pkt_data::tx_cnt_lmt_sel + * Please Place Description here. + * @var mac_ax_pkt_data::tx_cnt_lmt + * Please Place Description here. + * @var mac_ax_pkt_data::ndpa_dur + * Please Place Description here. + * @var mac_ax_pkt_data::nav_use_hdr + * Please Place Description here. + * @var mac_ax_pkt_data::multiport_id + * Please Place Description here. + * @var mac_ax_pkt_data::mbssid + * Please Place Description here. + * @var mac_ax_pkt_data::null_0 + * Please Place Description here. + * @var mac_ax_pkt_data::null_1 + * Please Place Description here. + * @var mac_ax_pkt_data::tri_frame + * Please Place Description here. + * @var mac_ax_pkt_data::ack_ch_info + * Please Place Description here. + * @var mac_ax_pkt_data::pkt_offset + * Please Place Description here. + * @var mac_ax_pkt_data::a_ctrl_uph + * Please Place Description here. + * @var mac_ax_pkt_data::a_ctrl_bsr + * Please Place Description here. + * @var mac_ax_pkt_data::a_ctrl_cas + * Please Place Description here. + * @var mac_ax_pkt_data::rtt + * Please Place Description here. + * @var mac_ax_pkt_data::ht_data_snd + * Please Place Description here. + * @var mac_ax_pkt_data::no_ack + * Please Place Description here. + * @var mac_ax_pkt_data::sw_define + * Please Place Description here. + */ +struct mac_ax_pkt_data { + u16 wifi_seq; + u8 hw_ssn_sel; + u8 hw_seq_mode; + u8 chk_en; + u8 hw_amsdu; + u8 shcut_camid; + u8 headerwllc_len; + u8 smh_en; + u8 wd_page; + u8 wp_offset; + u8 wdinfo_en; + u8 hw_aes_iv; + u8 hdr_len; + u8 ch; + u8 macid; + u8 wmm; + u8 band; + u8 agg_en; + u8 bk; + u8 max_agg_num; + u8 bmc; + u8 lifetime_sel; + u8 ampdu_density; + u8 userate; + u16 data_rate; + u8 data_bw; + u8 er_bw; + u8 data_gi_ltf; + u8 data_er; + u8 data_dcm; + u8 data_stbc; + u8 data_ldpc; + u8 hw_sec_en; + u8 sec_cam_idx; + u8 sec_type; + u8 dis_data_fb; + u8 dis_rts_fb; + u8 tid; + u8 rts_en; + u8 cts2self; + u8 cca_rts; + u8 hw_rts_en; + u8 ndpa; + u8 snd_pkt_sel; + u8 sifs_tx; + u8 tx_cnt_lmt_sel; + u8 tx_cnt_lmt; + u16 ndpa_dur; + u8 nav_use_hdr; + u8 multiport_id; + u8 mbssid; + u8 null_0; + u8 null_1; + u8 tri_frame; + u8 ack_ch_info; + u8 pkt_offset; + u8 a_ctrl_uph; + u8 a_ctrl_bsr; + u8 a_ctrl_cas; + u8 rtt; + u8 ht_data_snd; + u8 no_ack; + u8 sw_define; + u8 addr_info_num; + u8 reuse_start_num; + u8 reuse_size; + u8 reuse_num; + u8 hw_sec_iv; + u8 sw_sec_iv; + u8 sec_keyid; + u8 rls_to_cpuio; + u8 force_key_en; + u8 upd_wlan_hdr; + u16 data_rty_lowest_rate; + u8 spe_rpt; +}; + +/** + * @struct mac_ax_pkt_mgnt + * @brief mac_ax_pkt_mgnt + * + * @var mac_ax_pkt_mgnt::wifi_seq + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_ssn_sel + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_seq_mode + * Please Place Description here. + * @var mac_ax_pkt_mgnt::chk_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_amsdu + * Please Place Description here. + * @var mac_ax_pkt_mgnt::shcut_camid + * Please Place Description here. + * @var mac_ax_pkt_mgnt::headerwllc_len + * Please Place Description here. + * @var mac_ax_pkt_mgnt::smh_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::wd_page + * Please Place Description here. + * @var mac_ax_pkt_mgnt::wp_offset + * Please Place Description here. + * @var mac_ax_pkt_mgnt::wdinfo_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_aes_iv + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hdr_len + * Please Place Description here. + * @var mac_ax_pkt_mgnt::rsvd0 + * Please Place Description here. + * @var mac_ax_pkt_mgnt::macid + * Please Place Description here. + * @var mac_ax_pkt_mgnt::rsvd1 + * Please Place Description here. + * @var mac_ax_pkt_mgnt::bk + * Please Place Description here. + * @var mac_ax_pkt_mgnt::max_agg_num + * Please Place Description here. + * @var mac_ax_pkt_mgnt::bmc + * Please Place Description here. + * @var mac_ax_pkt_mgnt::lifetime_sel + * Please Place Description here. + * @var mac_ax_pkt_mgnt::ampdu_density + * Please Place Description here. + * @var mac_ax_pkt_mgnt::userate + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_rate + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_bw + * Please Place Description here. + * @var mac_ax_pkt_mgnt::er_bw + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_gi_ltf + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_er + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_dcm + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_stbc + * Please Place Description here. + * @var mac_ax_pkt_mgnt::data_ldpc + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_sec_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::sec_cam_idx + * Please Place Description here. + * @var mac_ax_pkt_mgnt::sec_type + * Please Place Description here. + * @var mac_ax_pkt_mgnt::dis_data_fb + * Please Place Description here. + * @var mac_ax_pkt_mgnt::dis_rts_fb + * Please Place Description here. + * @var mac_ax_pkt_mgnt::tid + * Please Place Description here. + * @var mac_ax_pkt_mgnt::rts_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::cts2self + * Please Place Description here. + * @var mac_ax_pkt_mgnt::cca_rts + * Please Place Description here. + * @var mac_ax_pkt_mgnt::hw_rts_en + * Please Place Description here. + * @var mac_ax_pkt_mgnt::ndpa + * Please Place Description here. + * @var mac_ax_pkt_mgnt::snd_pkt_sel + * Please Place Description here. + * @var mac_ax_pkt_mgnt::sifs_tx + * Please Place Description here. + * @var mac_ax_pkt_mgnt::tx_cnt_lmt_sel + * Please Place Description here. + * @var mac_ax_pkt_mgnt::tx_cnt_lmt + * Please Place Description here. + * @var mac_ax_pkt_mgnt::ndpa_dur + * Please Place Description here. + * @var mac_ax_pkt_mgnt::nav_use_hdr + * Please Place Description here. + * @var mac_ax_pkt_mgnt::multiport_id + * Please Place Description here. + * @var mac_ax_pkt_mgnt::mbssid + * Please Place Description here. + * @var mac_ax_pkt_mgnt::null_0 + * Please Place Description here. + * @var mac_ax_pkt_mgnt::null_1 + * Please Place Description here. + * @var mac_ax_pkt_mgnt::tri_frame + * Please Place Description here. + * @var mac_ax_pkt_mgnt::ack_ch_info + * Please Place Description here. + * @var mac_ax_pkt_mgnt::pkt_offset + * Please Place Description here. + * @var mac_ax_pkt_mgnt::a_ctrl_bsr + * Please Place Description here. + * @var mac_ax_pkt_mgnt::rtt + * Please Place Description here. + * @var mac_ax_pkt_mgnt::ht_data_snd + * Please Place Description here. + * @var mac_ax_pkt_mgnt::no_ack + * Please Place Description here. + */ +struct mac_ax_pkt_mgnt { + u16 wifi_seq; + u8 hw_ssn_sel; + u8 hw_seq_mode; + u8 chk_en; + u8 hw_amsdu; + u8 shcut_camid; + u8 headerwllc_len; + u8 smh_en; + u8 wd_page; + u8 wp_offset; + u8 wdinfo_en; + u8 hw_aes_iv; + u8 hdr_len; + u8 ch; + u8 macid; + u8 wmm; + u8 band; + u8 agg_en; + u8 bk; + u8 max_agg_num; + u8 bmc; + u8 lifetime_sel; + u8 ampdu_density; + u8 userate; + u16 data_rate; + u8 data_bw; + u8 er_bw; + u8 data_gi_ltf; + u8 data_er; + u8 data_dcm; + u8 data_stbc; + u8 data_ldpc; + u8 hw_sec_en; + u8 sec_cam_idx; + u8 sec_type; + u8 dis_data_fb; + u8 dis_rts_fb; + u8 tid; + u8 rts_en; + u8 cts2self; + u8 cca_rts; + u8 hw_rts_en; + u8 ndpa; + u8 snd_pkt_sel; + u8 sifs_tx; + u8 tx_cnt_lmt_sel; + u8 tx_cnt_lmt; + u16 ndpa_dur; + u8 nav_use_hdr; + u8 multiport_id; + u8 mbssid; + u8 null_0; + u8 null_1; + u8 tri_frame; + u8 ack_ch_info; + u8 pkt_offset; + u8 a_ctrl_uph; + u8 a_ctrl_bsr; + u8 a_ctrl_cas; + u8 rtt; + u8 ht_data_snd; + u8 no_ack; + u8 sw_define; + u8 addr_info_num; + u8 reuse_start_num; + u8 reuse_size; + u8 reuse_num; + u8 hw_sec_iv; + u8 sw_sec_iv; + u8 sec_keyid; + u8 rls_to_cpuio; + u8 force_key_en; + u8 upd_wlan_hdr; + u16 data_rty_lowest_rate; + u8 spe_rpt; +}; + +/** + * @struct mac_ax_rpkt_data + * @brief mac_ax_rpkt_data + * + * @var mac_ax_rpkt_data::crc_err + * Please Place Description here. + * @var mac_ax_rpkt_data::icv_err + * Please Place Description here. + */ +struct mac_ax_rpkt_data { + u8 crc_err; + u8 icv_err; +}; + +/** + * @struct mac_ax_txpkt_info + * @brief mac_ax_txpkt_info + * + * @var mac_ax_txpkt_info::type + * Please Place Description here. + * @var mac_ax_txpkt_info::pktsize + * Please Place Description here. + * @var mac_ax_txpkt_info::data + * Please Place Description here. + * @var mac_ax_txpkt_info::mgnt + * Please Place Description here. + * @var mac_ax_txpkt_info::u + * Please Place Description here. + */ +struct mac_ax_txpkt_info { + enum mac_ax_pkt_t type; + u32 pktsize; + union { + struct mac_ax_pkt_data data; + struct mac_ax_pkt_mgnt mgnt; + } u; +}; + +/** + * @struct mac_ax_bcn_cnt + * @brief mac_ax_bcn_cnt + * + * @var mac_ax_bcn_cnt::port + * Please Place Description here. + * @var mac_ax_bcn_cnt::mbssid + * Please Place Description here. + * @var mac_ax_bcn_cnt::ok_cnt + * Please Place Description here. + * @var mac_ax_bcn_cnt::fail_cnt + * Please Place Description here. + */ +struct mac_ax_bcn_cnt { + u8 port; + u8 mbssid; + u8 band; + u8 ok_cnt; + u8 cca_cnt; + u8 edcca_cnt; + u8 nav_cnt; + u8 txon_cnt; + u8 mac_cnt; + u8 others_cnt; + u8 lock_cnt; + u8 cmp_cnt; + u8 invalid_cnt; + u8 srchend_cnt; +}; + +/** + * @struct mac_ax_refill_info + * @brief mac_ax_refill_info + * + * @var mac_ax_refill_info::pkt + * Please Place Description here. + * @var mac_ax_refill_info::agg_num + * Please Place Description here. + * @var mac_ax_refill_info::packet_offset + * Please Place Description here. + */ +struct mac_ax_refill_info { + u8 *pkt; + u32 agg_num; + u8 packet_offset; +}; + +/** + * @struct mac_ax_rpkt_ppdu + * @brief mac_ax_rpkt_ppdu + * + * @var mac_ax_rpkt_ppdu::mac_info + * Please Place Description here. + */ +struct mac_ax_rpkt_ppdu { + u8 mac_info; +}; + +/** + * @struct mac_ax_mac_tx_mode_sel + * @brief mac_ax_mac_tx_mode_sel + * + * @var mac_ax_mac_tx_mode_sel::txop_rot_wmm0_en + * Please Place Description here. + * @var mac_ax_mac_tx_mode_sel::txop_rot_wmm1_en + * Please Place Description here. + * @var mac_ax_mac_tx_mode_sel::txop_rot_wmm2_en + * Please Place Description here. + * @var mac_ax_mac_tx_mode_sel::txop_rot_wmm3_en + * Please Place Description here. + */ +struct mac_ax_mac_tx_mode_sel { + u8 txop_rot_wmm0_en; + u8 txop_rot_wmm1_en; + u8 txop_rot_wmm2_en; + u8 txop_rot_wmm3_en; + + u8 sw_mode_band0_en; /* shall remove when v0_22 release, Rick */ +}; + +/** + * @struct mac_ax_rxpkt_info + * @brief mac_ax_rxpkt_info + * + * @var mac_ax_rxpkt_info::type + * Please Place Description here. + * @var mac_ax_rxpkt_info::rxdlen + * Please Place Description here. + * @var mac_ax_rxpkt_info::drvsize + * Please Place Description here. + * @var mac_ax_rxpkt_info::shift + * Please Place Description here. + * @var mac_ax_rxpkt_info::pktsize + * Please Place Description here. + * @var mac_ax_rxpkt_info::data + * Please Place Description here. + * @var mac_ax_rxpkt_info::ppdu + * Please Place Description here. + * @var mac_ax_rxpkt_info::u + * Please Place Description here. + */ +struct mac_ax_rxpkt_info { + enum mac_ax_pkt_t type; + u16 rxdlen; + u8 drvsize; + u8 shift; + u32 pktsize; + union { + struct mac_ax_rpkt_data data; + struct mac_ax_rpkt_ppdu ppdu; + } u; +}; + +/** + * @struct mac_ax_pm_cam_ctrl_t + * @brief mac_ax_pm_cam_ctrl_t + * + * @var mac_ax_pm_cam_ctrl_t::pld_mask0 + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::pld_mask1 + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::pld_mask2 + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::pld_mask3 + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::entry_index + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::valid + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::type + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::subtype + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::skip_mac_iv_hdr + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::target_ind + * Please Place Description here. + * @var mac_ax_pm_cam_ctrl_t::crc16 + * Please Place Description here. + */ +struct mac_ax_pm_cam_ctrl_t { + u32 pld_mask0; + u32 pld_mask1; + u32 pld_mask2; + u32 pld_mask3; + u8 entry_index; + u8 valid; + u8 type; + u8 subtype; + u8 skip_mac_iv_hdr; + u8 target_ind; + u16 crc16; +}; + +/** + * @struct mac_ax_af_ud_ctrl_t + * @brief mac_ax_af_ud_ctrl_t + * + * @var mac_ax_af_ud_ctrl_t::index + * Please Place Description here. + * @var mac_ax_af_ud_ctrl_t::fwd_tg + * Please Place Description here. + * @var mac_ax_af_ud_ctrl_t::category + * Please Place Description here. + * @var mac_ax_af_ud_ctrl_t::action_field + * Please Place Description here. + */ +struct mac_ax_af_ud_ctrl_t { + u8 index; + u8 fwd_tg; + u8 category; + u8 action_field; +}; + +/** + * @struct mac_ax_rx_fwd_ctrl_t + * @brief mac_ax_rx_fwd_ctrl_t + * + * @var mac_ax_rx_fwd_ctrl_t::pm_cam_ctrl + * Please Place Description here. + * @var mac_ax_rx_fwd_ctrl_t::af_ud_ctrl + * Please Place Description here. + * @var mac_ax_rx_fwd_ctrl_t::type + * Please Place Description here. + * @var mac_ax_rx_fwd_ctrl_t::frame + * Please Place Description here. + * @var mac_ax_rx_fwd_ctrl_t::fwd_tg + * Please Place Description here. + */ +struct mac_ax_rx_fwd_ctrl_t { + struct mac_ax_pm_cam_ctrl_t pm_cam_ctrl; + struct mac_ax_af_ud_ctrl_t af_ud_ctrl; + u8 type; + u8 frame; + u8 fwd_tg; +}; + +/** + * @struct mac_ax_rx_fltr_ctrl_t + * @brief mac_ax_rx_fltr_ctrl_t + * + * @var mac_ax_rx_fltr_ctrl_t::sniffer_mode + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_a1_match_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_bc_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_mc_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::uc_pkt_chk_cam_match + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::bc_pkt_chk_cam_match + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::mc_pkt_white_lst_mode + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::bcn_chk_en + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::bcn_chk_rule + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_pwr_mngt_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_crc32_err_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_unsupport_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_mac_hdr_content_err_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::acpt_ftm_req_pkt + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::pkt_len_fltr + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::unsp_pkt_target + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::uid_fltr + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::cck_crc_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::cck_sig_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::lsig_parity_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::siga_crc_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::vht_su_sigb_crc_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::vht_mu_sigb_crc_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::he_sigb_crc_chk_enable + * Please Place Description here. + * @var mac_ax_rx_fltr_ctrl_t::min_len_chk_disable + * Please Place Description here. + */ +struct mac_ax_rx_fltr_ctrl_t { + // mac fltr + u8 sniffer_mode:1; + u8 acpt_a1_match_pkt:1; + u8 acpt_bc_pkt:1; + u8 acpt_mc_pkt:1; + u8 uc_pkt_chk_cam_match:1; + u8 bc_pkt_chk_cam_match:1; + u8 mc_pkt_white_lst_mode:1; + u8 bcn_chk_en:1; + u8 bcn_chk_rule:2; + u8 acpt_pwr_mngt_pkt:1; + u8 acpt_crc32_err_pkt:1; + u8 acpt_unsupport_pkt:1; + u8 acpt_mac_hdr_content_err_pkt:1; + u8 acpt_ftm_req_pkt:1; + u8 pkt_len_fltr:6; + u8 unsp_pkt_target:2; + u8 uid_fltr:2; + // plcp fltr + u8 cck_crc_chk_enable:1; + u8 cck_sig_chk_enable:1; + u8 lsig_parity_chk_enable:1; + u8 siga_crc_chk_enable:1; + u8 vht_su_sigb_crc_chk_enable:1; + u8 vht_mu_sigb_crc_chk_enable:1; + u8 he_sigb_crc_chk_enable:1; + u8 min_len_chk_disable:1; +}; + +struct mac_ax_rx_fltr_elem { + u16 subtype_mask; + enum mac_ax_fwd_target target_arr[16]; +}; + +/** + * @struct mac_ax_addrcam_ctrl_t + * @brief mac_ax_addrcam_ctrl_t + */ +struct mac_ax_addrcam_ctrl_t { + u8 addrcam_en:1; + u8 srch_per_mpdu:1; + u8 a2_bit0_cmp_en:1; + u8 rsvd1:5; + u8 clr_all_content:1; + u8 rsvd2:3; + u8 srch_time_lmt:4; + u8 srch_range_lmt; + u8 rsvd3; +}; + +/** + * @struct mac_ax_addrcam_dis_ctrl_t + * @brief mac_ax_addrcam_dis_ctrl_t + * + */ +struct mac_ax_addrcam_dis_ctrl_t { + u8 def_hit_idx; + u8 def_hit_result : 1; + u8 def_a1_hit_result : 1; + u8 def_a2_hit_result : 1; + u8 def_a3_hit_result : 1; + u8 def_port : 3; + u8 rsvd : 1; + u8 def_sec_idx; + u8 def_macid; +}; + +/** + * @struct mac_ax_dfs_rpt + * @brief mac_ax_dfs_rpt + * + * @var mac_ax_dfs_rpt::dfs_ptr + * Please Place Description here. + * @var mac_ax_dfs_rpt::drop_num + * Please Place Description here. + * @var mac_ax_dfs_rpt::max_cont_drop + * Please Place Description here. + * @var mac_ax_dfs_rpt::total_drop + * Please Place Description here. + * @var mac_ax_dfs_rpt::dfs_num + * Please Place Description here. + */ +struct mac_ax_dfs_rpt { + u8 *dfs_ptr; + u16 drop_num; + u16 max_cont_drop; + u16 total_drop; + u16 dfs_num; +}; + +/** + * @struct mac_ax_ppdu_usr + * @brief mac_ax_ppdu_usr + * + * @var mac_ax_ppdu_usr::vld + * Please Place Description here. + * @var mac_ax_ppdu_usr::has_data + * Please Place Description here. + * @var mac_ax_ppdu_usr::has_ctrl + * Please Place Description here. + * @var mac_ax_ppdu_usr::has_mgnt + * Please Place Description here. + * @var mac_ax_ppdu_usr::has_bcn + * Please Place Description here. + * @var mac_ax_ppdu_usr::macid + * Please Place Description here. + */ +struct mac_ax_ppdu_usr { + u8 vld:1; + u8 has_data:1; + u8 has_ctrl:1; + u8 has_mgnt:1; + u8 has_bcn:1; + u8 macid; +}; + +/** + * @struct mac_ax_ppdu_stat + * @brief mac_ax_ppdu_stat + * + * @var mac_ax_ppdu_stat::band + * Please Place Description here. + * @var mac_ax_ppdu_stat::bmp_append_info + * Please Place Description here. + * @var mac_ax_ppdu_stat::bmp_filter + * Please Place Description here. + * @var mac_ax_ppdu_stat::dup2fw_en + * Please Place Description here. + * @var mac_ax_ppdu_stat::dup2fw_len + * Please Place Description here. + */ +struct mac_ax_ppdu_stat { + u8 band; +#define MAC_AX_PPDU_MAC_INFO BIT(1) +#define MAC_AX_PPDU_PLCP BIT(3) +#define MAC_AX_PPDU_RX_CNT BIT(2) + u8 bmp_append_info; +#define MAC_AX_PPDU_HAS_A1M BIT(4) +#define MAC_AX_PPDU_HAS_CRC_OK BIT(5) + u8 bmp_filter; + u8 dup2fw_en; + u8 dup2fw_len; +}; + +/** + * @struct mac_ax_ch_info + * @brief mac_ax_ch_info + * + * @var mac_ax_ch_info::trigger + * Please Place Description here. + * @var mac_ax_ch_info::macid + * Please Place Description here. + * @var mac_ax_ch_info::bmp_filter + * Please Place Description here. + * @var mac_ax_ch_info::dis_to + * Please Place Description here. + * @var mac_ax_ch_info::seg_size + * Please Place Description here. + */ +struct mac_ax_ch_info { +#define MAC_AX_CH_INFO_MACID 0 +#define MAC_AX_CH_INFO_NDP 1 +#define MAC_AX_CH_INFO_SND 2 +#define MAC_AX_CH_INFO_ACK 3 + u8 trigger; + u8 macid; +#define MAC_AX_CH_INFO_CRC_FAIL BIT(0) +#define MAC_AX_CH_INFO_DATA_FRM BIT(1) +#define MAC_AX_CH_INFO_CTRL_FRM BIT(2) +#define MAC_AX_CH_INFO_MGNT_FRM BIT(3) + u8 bmp_filter; + u8 dis_to; +#define MAC_AX_CH_IFNO_SEG_128 0 +#define MAC_AX_CH_IFNO_SEG_256 1 +#define MAC_AX_CH_IFNO_SEG_512 2 +#define MAC_AX_CH_IFNO_SEG_1024 3 + u8 seg_size; +}; + +/** + * @struct mac_ax_dfs + * @brief mac_ax_dfs + * + * @var mac_ax_dfs::num_th + * Please Place Description here. + * @var mac_ax_dfs::en_timeout + * Please Place Description here. + */ +struct mac_ax_dfs { +#define MAC_AX_DFS_TH_29 0 +#define MAC_AX_DFS_TH_61 1 +#define MAC_AX_DFS_TH_93 2 +#define MAC_AX_DFS_TH_125 3 + u8 num_th; + u8 en_timeout; +}; + +/** + * @struct mac_ax_ppdu_rpt + * @brief mac_ax_ppdu_rpt + * + * @var mac_ax_ppdu_rpt::rx_cnt_ptr + * Please Place Description here. + * @var mac_ax_ppdu_rpt::plcp_ptr + * Please Place Description here. + * @var mac_ax_ppdu_rpt::phy_st_ptr + * Please Place Description here. + * @var mac_ax_ppdu_rpt::phy_st_size + * Please Place Description here. + * @var mac_ax_ppdu_rpt::rx_cnt_size + * Please Place Description here. + * @var mac_ax_ppdu_rpt::lsig_len + * Please Place Description here. + * @var mac_ax_ppdu_rpt::service + * Please Place Description here. + * @var mac_ax_ppdu_rpt::usr_num + * Please Place Description here. + * @var mac_ax_ppdu_rpt::fw_def + * Please Place Description here. + * @var mac_ax_ppdu_rpt::is_to_self + * Please Place Description here. + * @var mac_ax_ppdu_rpt::plcp_size + * Please Place Description here. + * @var mac_ax_ppdu_rpt::usr + * Please Place Description here. + */ +struct mac_ax_ppdu_rpt { +#define MAC_AX_PPDU_MAX_USR 4 + u8 *rx_cnt_ptr; + u8 *plcp_ptr; + u8 *phy_st_ptr; + u32 phy_st_size; + u32 rx_cnt_size; + u16 lsig_len; + u16 service; + u8 usr_num; + u8 fw_def; + u8 is_to_self; + u8 plcp_size; + struct mac_ax_ppdu_usr usr[MAC_AX_PPDU_MAX_USR]; +}; + +/** + * @struct mac_ax_phy_rpt_cfg + * @brief mac_ax_phy_rpt_cfg + * + * @var mac_ax_phy_rpt_cfg::type + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::en + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::dest + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::ppdu + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::chif + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::dfs + * Please Place Description here. + * @var mac_ax_phy_rpt_cfg::u + * Please Place Description here. + */ +struct mac_ax_phy_rpt_cfg { + enum mac_ax_phy_rpt type; + u8 en; +#define MAC_AX_PRPT_DEST_HOST 0 +#define MAC_AX_PRPT_DEST_WLCPU 1 + u8 dest; + union { + struct mac_ax_ppdu_stat ppdu; + struct mac_ax_ch_info chif; + struct mac_ax_dfs dfs; + } u; +}; + +/** + * @struct mac_ax_pkt_drop_info + * @brief mac_ax_pkt_drop_info + * + * @var mac_ax_pkt_drop_info::sel + * Please Place Description here. + * @var mac_ax_pkt_drop_info::macid + * Please Place Description here. + * @var mac_ax_pkt_drop_info::band + * Please Place Description here. + * @var mac_ax_pkt_drop_info::port + * Please Place Description here. + * @var mac_ax_pkt_drop_info::mbssid + * Please Place Description here. + */ +struct mac_ax_pkt_drop_info { + enum mac_ax_pkt_drop_sel sel; + u8 macid; + u8 band; + u8 port; + u8 mbssid; +}; + +/** + * @struct mac_ax_ch_busy_cnt_ref + * @brief mac_ax_ch_busy_cnt_ref + * + * @var mac_ax_ch_busy_cnt_ref::basic_nav + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::intra_nav + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::data_on + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::edcca_p20 + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::cca_p20 + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::cca_s20 + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::cca_s40 + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_ref::cca_s80 + * Please Place Description here. + */ +struct mac_ax_ch_busy_cnt_ref { + u16 basic_nav:1; + u16 intra_nav:1; + u16 data_on:1; + u16 edcca_p20:1; + u16 cca_p20:1; + u16 cca_s20:1; + u16 cca_s40:1; + u16 cca_s80:1; + u16 phy_txon:1; + u16 rsvd:7; +}; + +/** + * @struct mac_ax_tx_queue_empty + * @brief mac_ax_tx_queue_empty + * + * @var mac_ax_tx_queue_empty::macid_txq_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::band0_mgnt_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::band1_mgnt_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::fw_txq_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::h2c_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::others_empty + * Please Place Description here. + * @var mac_ax_tx_queue_empty::rsvd + * Please Place Description here. + */ +struct mac_ax_tx_queue_empty { +#define WDE_QEMPTY_ACQ_NUM_MAX 16 /* shall be the max num of all chip */ + u8 macid_txq_empty[WDE_QEMPTY_ACQ_NUM_MAX]; + u8 band0_mgnt_empty:1; + u8 band1_mgnt_empty:1; + u8 fw_txq_empty:1; + u8 h2c_empty:1; + u8 others_empty:1; + u8 rsvd:3; +}; + +/** + * @struct mac_ax_rx_queue_empty + * @brief mac_ax_rx_queue_empty + * + * @var mac_ax_rx_queue_empty::band0_rxq_empty + * Please Place Description here. + * @var mac_ax_rx_queue_empty::band1_rxq_empty + * Please Place Description here. + * @var mac_ax_rx_queue_empty::c2h_empty + * Please Place Description here. + * @var mac_ax_rx_queue_empty::others_empty + * Please Place Description here. + * @var mac_ax_rx_queue_empty::rsvd + * Please Place Description here. + */ +struct mac_ax_rx_queue_empty { + u8 band0_rxq_empty:1; + u8 band1_rxq_empty:1; + u8 c2h_empty:1; + u8 others_empty:1; + u8 rsvd:4; +}; + +/*--------------------Define TF2PCMD related struct --------------------------*/ + +/** + * @struct mac_ax_rura_report + * @brief mac_ax_rura_report + * + * @var mac_ax_rura_report::rt_tblcol + * Please Place Description here. + * @var mac_ax_rura_report::prtl_alloc + * Please Place Description here. + * @var mac_ax_rura_report::rate_chg + * Please Place Description here. + */ +struct mac_ax_rura_report { + u8 rt_tblcol: 6; + u8 prtl_alloc: 1; + u8 rate_chg: 1; +}; + +//for ul rua output + +/** + * @struct mac_ax_ulru_out_sta_ent + * @brief mac_ax_ulru_out_sta_ent + * + * @var mac_ax_ulru_out_sta_ent::dropping + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::tgt_rssi + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::mac_id + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::ru_pos + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::coding + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::vip_flag + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::rsvd1 + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::bsr_length + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::rsvd2 + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::rate + * Please Place Description here. + * @var mac_ax_ulru_out_sta_ent::rpt + * Please Place Description here. + */ +struct mac_ax_ulru_out_sta_ent { + u8 dropping: 1; + u8 tgt_rssi: 7; + u8 mac_id; + u8 ru_pos; + u8 coding: 1; + u8 vip_flag: 1; + u8 rsvd1: 6; + u16 bsr_length: 15; + u16 rsvd2: 1; + struct mac_ax_ru_rate_ent rate; + struct mac_ax_rura_report rpt; +}; + +/** + * @struct mac_ax_ulrua_output + * @brief mac_ax_ulrua_output + * + * @var mac_ax_ulrua_output::ru2su + * Please Place Description here. + * @var mac_ax_ulrua_output::ppdu_bw + * Please Place Description here. + * @var mac_ax_ulrua_output::gi_ltf + * Please Place Description here. + * @var mac_ax_ulrua_output::stbc + * Please Place Description here. + * @var mac_ax_ulrua_output::doppler + * Please Place Description here. + * @var mac_ax_ulrua_output::n_ltf_and_ma + * Please Place Description here. + * @var mac_ax_ulrua_output::sta_num + * Please Place Description here. + * @var mac_ax_ulrua_output::rsvd1 + * Please Place Description here. + * @var mac_ax_ulrua_output::rf_gain_fix + * Please Place Description here. + * @var mac_ax_ulrua_output::rf_gain_idx + * Please Place Description here. + * @var mac_ax_ulrua_output::tb_t_pe_nom + * Please Place Description here. + * @var mac_ax_ulrua_output::rsvd2 + * Please Place Description here. + * @var mac_ax_ulrua_output::grp_mode + * Please Place Description here. + * @var mac_ax_ulrua_output::grp_id + * Please Place Description here. + * @var mac_ax_ulrua_output::fix_mode + * Please Place Description here. + * @var mac_ax_ulrua_output::rsvd3 + * Please Place Description here. + * @var mac_ax_ulrua_output::sta + * Please Place Description here. + */ +struct mac_ax_ulrua_output { + u8 ru2su: 1; + u8 ppdu_bw: 2; + u8 gi_ltf: 3; + u8 stbc: 1; + u8 doppler: 1; + u8 n_ltf_and_ma: 3; + u8 sta_num: 4; + u8 rsvd1: 1; + u16 rf_gain_fix: 1; + u16 rf_gain_idx: 10; + u16 tb_t_pe_nom: 2; + u16 rsvd2: 3; + + u32 grp_mode: 1; + u32 grp_id: 6; + u32 fix_mode: 1; + u32 rsvd3: 24; + struct mac_ax_ulru_out_sta_ent sta[MAC_AX_MAX_RU_NUM]; +}; + +/** + * @struct mac_ul_macid_info + * @brief mac_ul_macid_info + * + * @var mac_ul_macid_info::macid + * Please Place Description here. + * @var mac_ul_macid_info::pref_AC + * Please Place Description here. + * @var mac_ul_macid_info::rsvd + * Please Place Description here. + */ +struct mac_ul_macid_info { + u8 macid; + u8 pref_AC:2; + u8 rsvd:6; +}; + +/** + * @struct mac_ul_mode_cfg + * @brief mac_ul_mode_cfg + * + * @var mac_ul_mode_cfg::mode + * Please Place Description here. + * @var mac_ul_mode_cfg::interval + * Please Place Description here. + * @var mac_ul_mode_cfg::bsr_thold + * Please Place Description here. + * @var mac_ul_mode_cfg::storemode + * Please Place Description here. + * @var mac_ul_mode_cfg::rsvd + * Please Place Description here. + */ +struct mac_ul_mode_cfg { + u32 mode:2; /* 0: peoridic ; 1: normal ; 2: non_tgr */ + u32 interval:6; /* unit: sec */ + u32 bsr_thold:8; + u32 storemode:2; + u32 rsvd:14; +}; + +/** + * @struct mac_ax_ul_fixinfo + * @brief mac_ax_ul_fixinfo + * + * @var mac_ax_ul_fixinfo::tbl_hdr + * Please Place Description here. + * @var mac_ax_ul_fixinfo::cfg + * Please Place Description here. + * @var mac_ax_ul_fixinfo::ndpa_dur + * Please Place Description here. + * @var mac_ax_ul_fixinfo::tf_type + * Please Place Description here. + * @var mac_ax_ul_fixinfo::sig_ta_pkten + * Please Place Description here. + * @var mac_ax_ul_fixinfo::sig_ta_pktsc + * Please Place Description here. + * @var mac_ax_ul_fixinfo::murts_flag + * Please Place Description here. + * @var mac_ax_ul_fixinfo::ndpa + * Please Place Description here. + * @var mac_ax_ul_fixinfo::snd_pkt_sel + * Please Place Description here. + * @var mac_ax_ul_fixinfo::gi_ltf + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_rate + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_er + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_bw + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_stbc + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_ldpc + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_dcm + * Please Place Description here. + * @var mac_ax_ul_fixinfo::apep_len + * Please Place Description here. + * @var mac_ax_ul_fixinfo::more_tf + * Please Place Description here. + * @var mac_ax_ul_fixinfo::data_bw_er + * Please Place Description here. + * @var mac_ax_ul_fixinfo::istwt + * Please Place Description here. + * @var mac_ax_ul_fixinfo::rsvd0 + * Please Place Description here. + * @var mac_ax_ul_fixinfo::multiport_id + * Please Place Description here. + * @var mac_ax_ul_fixinfo::mbssid + * Please Place Description here. + * @var mac_ax_ul_fixinfo::txpwr_mode + * Please Place Description here. + * @var mac_ax_ul_fixinfo::ulfix_usage + * Please Place Description here. + * @var mac_ax_ul_fixinfo::twtgrp_stanum_sel + * Please Place Description here. + * @var mac_ax_ul_fixinfo::store_idx + * Please Place Description here. + * @var mac_ax_ul_fixinfo::rsvd1 + * Please Place Description here. + * @var mac_ax_ul_fixinfo::sta + * Please Place Description here. + * @var mac_ax_ul_fixinfo::ulrua + * Please Place Description here. + */ +struct mac_ax_ul_fixinfo { + struct mac_ax_tbl_hdr tbl_hdr; + struct mac_ul_mode_cfg cfg; + + u32 ndpa_dur:16; + u32 tf_type:3; + u32 sig_ta_pkten:1; + u32 sig_ta_pktsc:4; + u32 murts_flag:1; + u32 ndpa:2; + u32 snd_pkt_sel:2; + u32 gi_ltf:3; + + u32 data_rate:9; + u32 data_er:1; + u32 data_bw:2; + u32 data_stbc:2; + u32 data_ldpc:1; + u32 data_dcm:1; + u32 apep_len:12; + u32 more_tf:1; + u32 data_bw_er:1; + u32 istwt:1; + u32 rsvd0:1; + + u32 multiport_id:3; + u32 mbssid:4; + u32 txpwr_mode:3; + u32 ulfix_usage:3; + u32 twtgrp_stanum_sel:2; + u32 store_idx:4; + u32 rsvd1:13; + struct mac_ul_macid_info sta[4]; + struct mac_ax_ulrua_output ulrua; +}; + +/** + * @struct mac_ax_mudecision_para + * @brief mac_ax_mudecision_para + * + * @var mac_ax_mudecision_para::tbl_hdr + * Please Place Description here. + * @var mac_ax_mudecision_para::mu_thold + * Please Place Description here. + * @var mac_ax_mudecision_para::bypass_thold + * Please Place Description here. + * @var mac_ax_mudecision_para::bypass_tp + * Please Place Description here. + */ +struct mac_ax_mudecision_para { + struct mac_ax_tbl_hdr tbl_hdr; + u32 mu_thold:30; + u32 bypass_thold:1; //macid bypass tx time thold check + u32 bypass_tp:1; //T1 unit:us + u32 init_rate: 4; + u32 retry_th: 3; + u32 rsvd: 25; +}; + +/** + * @struct mac_ax_protect_rsp_field + * @brief mac_ax_protect_rsp_field + * + * @var mac_ax_protect_rsp_field::protect + * Please Place Description here. + * @var mac_ax_protect_rsp_field::rsp + * Please Place Description here. + */ +struct mac_ax_protect_rsp_field { + u8 protect: 4; + u8 rsp: 4; +}; + +/** + * @struct mac_ax_mu_protect_rsp_type + * @brief mac_ax_mu_protect_rsp_type + * + * @var mac_ax_mu_protect_rsp_type::byte_type + * Please Place Description here. + * @var mac_ax_mu_protect_rsp_type::feld_type + * Please Place Description here. + * @var mac_ax_mu_protect_rsp_type::u + * Please Place Description here. + */ +struct mac_ax_mu_protect_rsp_type { + union { + u8 byte_type; + struct mac_ax_protect_rsp_field feld_type; + } u; +}; + +/** + * @struct mac_ax_mu_sta_upd + * @brief mac_ax_mu_sta_upd + * + * @var mac_ax_mu_sta_upd::macid + * Please Place Description here. + * @var mac_ax_mu_sta_upd::mu_idx + * Please Place Description here. + * @var mac_ax_mu_sta_upd::prot_rsp_type + * Please Place Description here. + * @var mac_ax_mu_sta_upd::mugrp_bitmap + * Please Place Description here. + * @var mac_ax_mu_sta_upd::dis_256q + * Please Place Description here. + * @var mac_ax_mu_sta_upd::dis_1024q + * Please Place Description here. + * @var mac_ax_mu_sta_upd::rsvd + * Please Place Description here. + */ +struct mac_ax_mu_sta_upd { + u8 macid; + u8 mu_idx; + struct mac_ax_mu_protect_rsp_type prot_rsp_type[5]; + u8 mugrp_bitmap: 5; + u8 dis_256q: 1; + u8 dis_1024q: 1; + u8 rsvd: 1; +}; + +/** + * @struct mac_ax_wlaninfo_get + * @brief mac_ax_wlaninfo_get + * + * @var mac_ax_wlaninfo_get::info_sel + * Please Place Description here. + * @var mac_ax_wlaninfo_get::rsvd0 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv0 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv1 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv2 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv3 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv4 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv5 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv6 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::argv7 + * Please Place Description here. + * @var mac_ax_wlaninfo_get::rsvd1 + * Please Place Description here. + */ +struct mac_ax_wlaninfo_get { + u32 info_sel:4; + u32 rsvd0:4; + u32 argv0:8; + u32 argv1:8; + u32 argv2:8; + u32 argv3:8; + u32 argv4:8; + u32 argv5:8; + u32 argv6:8; + u32 argv7:8; + u32 rsvd1:24; +}; + +/** + * @struct mac_ax_ccxrpt + * @brief mac_ax_ccxrpt + * + * @var mac_ax_ccxrpt::macid + * Please Place Description here. + * @var mac_ax_ccxrpt::tx_state + * Please Place Description here. + * @var mac_ax_ccxrpt::sw_define + * Please Place Description here. + * @var mac_ax_ccxrpt::pkt_ok_num + * Please Place Description here. + * @var mac_ax_ccxrpt::rsvd0 + * Please Place Description here. + */ +struct mac_ax_ccxrpt { + u32 macid:7; + u32 tx_state:2; + u32 sw_define:4; + u32 pkt_ok_num:8; + u32 data_txcnt:6; + u32 rsvd0:5; +}; + +/** + * @struct mac_ax_dumpwlanc + * @brief mac_ax_dumpwlanc + * + * @var mac_ax_dumpwlanc::cmdid + * Please Place Description here. + * @var mac_ax_dumpwlanc::rsvd0 + * Please Place Description here. + */ +struct mac_ax_dumpwlanc { + u32 cmdid:8; + u32 rsvd0:24; +}; + +/** + * @struct mac_ax_dumpwlans + * @brief mac_ax_dumpwlans + * + * @var mac_ax_dumpwlans::cmdid + * Please Place Description here. + * @var mac_ax_dumpwlans::macid_grp + * Please Place Description here. + * @var mac_ax_dumpwlans::rsvd0 + * Please Place Description here. + */ +struct mac_ax_dumpwlans { + u32 cmdid:8; + u32 macid_grp:8; + u32 rsvd0:16; +}; + +/** + * @struct mac_ax_dumpwland + * @brief mac_ax_dumpwland + * + * @var mac_ax_dumpwland::cmdid + * Please Place Description here. + * @var mac_ax_dumpwland::grp_type + * Please Place Description here. + * @var mac_ax_dumpwland::grp_id + * Please Place Description here. + * @var mac_ax_dumpwland::muru + * Please Place Description here. + * @var mac_ax_dumpwland::macid + * Please Place Description here. + */ +struct mac_ax_dumpwland { + u32 cmdid:8; + u32 grp_type:8; + u32 grp_id:8; + u32 muru:8; + u8 macid[4]; +}; + +/** + * @struct mac_ax_fixmode_para + * @brief mac_ax_fixmode_para + * + * @var mac_ax_fixmode_para::tbl_hdr + * Please Place Description here. + * @var mac_ax_fixmode_para::force_sumuru_en + * Please Place Description here. + * @var mac_ax_fixmode_para::forcesu + * Please Place Description here. + * @var mac_ax_fixmode_para::forcemu + * Please Place Description here. + * @var mac_ax_fixmode_para::forceru + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_fe_su_en + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_fe_vhtmu_en + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_fe_hemu_en + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_fe_heru_en + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_fe_ul_en + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_frame_seq_su + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_frame_seq_vhtmu + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_frame_seq_hemu + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_frame_seq_heru + * Please Place Description here. + * @var mac_ax_fixmode_para::fix_frame_seq_ul + * Please Place Description here. + * @var mac_ax_fixmode_para::is_dlruhwgrp + * Please Place Description here. + * @var mac_ax_fixmode_para::is_ulruhwgrp + * Please Place Description here. + * @var mac_ax_fixmode_para::prot_type_su + * Please Place Description here. + * @var mac_ax_fixmode_para::prot_type_vhtmu + * Please Place Description here. + * @var mac_ax_fixmode_para::resp_type_vhtmu + * Please Place Description here. + * @var mac_ax_fixmode_para::prot_type_hemu + * Please Place Description here. + * @var mac_ax_fixmode_para::resp_type_hemu + * Please Place Description here. + * @var mac_ax_fixmode_para::prot_type_heru + * Please Place Description here. + * @var mac_ax_fixmode_para::resp_type_heru + * Please Place Description here. + * @var mac_ax_fixmode_para::ul_prot_type + * Please Place Description here. + * @var mac_ax_fixmode_para::rugrpid + * Please Place Description here. + * @var mac_ax_fixmode_para::mugrpid + * Please Place Description here. + * @var mac_ax_fixmode_para::ulgrpid + * Please Place Description here. + * @var mac_ax_fixmode_para::rsvd1 + * Please Place Description here. + */ +struct mac_ax_fixmode_para { + struct mac_ax_tbl_hdr tbl_hdr; + u32 force_sumuru_en: 1; + u32 forcesu: 1; + u32 forcemu: 1; + u32 forceru: 1; + u32 fix_fe_su_en:1; + u32 fix_fe_vhtmu_en:1; + u32 fix_fe_hemu_en:1; + u32 fix_fe_heru_en:1; + u32 fix_fe_ul_en:1; + u32 fix_frame_seq_su: 1; + u32 fix_frame_seq_vhtmu: 1; + u32 fix_frame_seq_hemu: 1; + u32 fix_frame_seq_heru: 1; + u32 fix_frame_seq_ul: 1; + u32 is_dlruhwgrp: 1; + u32 is_ulruhwgrp:1; + u32 prot_type_su: 4; + u32 prot_type_vhtmu: 4; + u32 resp_type_vhtmu: 4; + u32 prot_type_hemu: 4; + u32 resp_type_hemu: 4; + u32 prot_type_heru: 4; + u32 resp_type_heru: 4; + u32 ul_prot_type: 4; + u32 rugrpid: 5; + u32 mugrpid:5; + u32 ulgrpid:5; + u32 rsvd1:1; +}; + +/** + * @struct mac_ax_tf_ba + * @brief mac_ax_tf_ba + * + * @var mac_ax_tf_ba::fix_ba + * Please Place Description here. + * @var mac_ax_tf_ba::ru_psd + * Please Place Description here. + * @var mac_ax_tf_ba::tf_rate + * Please Place Description here. + * @var mac_ax_tf_ba::rf_gain_fix + * Please Place Description here. + * @var mac_ax_tf_ba::rf_gain_idx + * Please Place Description here. + * @var mac_ax_tf_ba::tb_ppdu_bw + * Please Place Description here. + * @var mac_ax_tf_ba::rate + * Please Place Description here. + * @var mac_ax_tf_ba::gi_ltf + * Please Place Description here. + * @var mac_ax_tf_ba::doppler + * Please Place Description here. + * @var mac_ax_tf_ba::stbc + * Please Place Description here. + * @var mac_ax_tf_ba::sta_coding + * Please Place Description here. + * @var mac_ax_tf_ba::tb_t_pe_nom + * Please Place Description here. + * @var mac_ax_tf_ba::pr20_bw_en + * Please Place Description here. + * @var mac_ax_tf_ba::ma_type + * Please Place Description here. + * @var mac_ax_tf_ba::rsvd1 + * Please Place Description here. + */ +struct mac_ax_tf_ba { + u32 fix_ba:1; + u32 ru_psd:9; + u32 tf_rate:9; + u32 rf_gain_fix:1; + u32 rf_gain_idx:10; + u32 tb_ppdu_bw:2; + struct mac_ax_ru_rate_ent rate; + u8 gi_ltf:3; + u8 doppler:1; + u8 stbc:1; + u8 sta_coding:1; + u8 tb_t_pe_nom:2; + u8 pr20_bw_en:1; + u8 ma_type: 1; + u8 rsvd1: 6; +}; + +/** + * @struct mac_ax_ba_infotbl + * @brief mac_ax_ba_infotbl + * + * @var mac_ax_ba_infotbl::tbl_hdr + * Please Place Description here. + * @var mac_ax_ba_infotbl::tfba + * Please Place Description here. + */ +struct mac_ax_ba_infotbl { + struct mac_ax_tbl_hdr tbl_hdr; + struct mac_ax_tf_ba tfba; +}; + +/** + * @struct mac_ax_dl_ru_grptbl + * @brief mac_ax_dl_ru_grptbl + * + * @var mac_ax_dl_ru_grptbl::tbl_hdr + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::ppdu_bw + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::tx_pwr + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::pwr_boost_fac + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::fix_mode_flag + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::rsvd1 + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::rsvd + * Please Place Description here. + * @var mac_ax_dl_ru_grptbl::tf + * Please Place Description here. + */ +struct mac_ax_dl_ru_grptbl { + struct mac_ax_tbl_hdr tbl_hdr; + u16 ppdu_bw:2; + u16 tx_pwr:9; + u16 pwr_boost_fac:5; + u8 fix_mode_flag:1; + u8 rsvd1:7; + u8 rsvd; + struct mac_ax_tf_ba tf; +}; + +/** + * @struct mac_ax_ul_ru_grptbl + * @brief mac_ax_ul_ru_grptbl + * + * @var mac_ax_ul_ru_grptbl::tbl_hdr + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::grp_psd_max + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::grp_psd_min + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::tf_rate + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::fix_tf_rate + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::rsvd2 + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::ppdu_bw + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::rf_gain_fix + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::rf_gain_idx + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::fix_mode_flag + * Please Place Description here. + * @var mac_ax_ul_ru_grptbl::rsvd1 + * Please Place Description here. + */ +struct mac_ax_ul_ru_grptbl { + struct mac_ax_tbl_hdr tbl_hdr; + u32 grp_psd_max: 9; + u32 grp_psd_min: 9; + u32 tf_rate: 9; + u32 fix_tf_rate: 1; + u32 rsvd2: 4; + u16 ppdu_bw: 2; + u16 rf_gain_fix: 1; + u16 rf_gain_idx: 10; + u16 fix_mode_flag: 1; + u16 rsvd1: 2; +}; + +/** + * @struct mac_ax_bb_stainfo + * @brief mac_ax_bb_stainfo + * + * @var mac_ax_bb_stainfo::tbl_hdr + * Please Place Description here. + * @var mac_ax_bb_stainfo::gi_ltf_48spt + * Please Place Description here. + * @var mac_ax_bb_stainfo::gi_ltf_18spt + * Please Place Description here. + * @var mac_ax_bb_stainfo::rsvd3 + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_info_en + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_bw + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_gi_ltf + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_doppler_ctrl + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_coding + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_txbf + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_stbc + * Please Place Description here. + * @var mac_ax_bb_stainfo::dl_fwcqi_flag + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlru_ratetbl_ridx + * Please Place Description here. + * @var mac_ax_bb_stainfo::csi_info_bitmap + * Please Place Description here. + * @var mac_ax_bb_stainfo::dl_swgrp_bitmap + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_dcm + * Please Place Description here. + * @var mac_ax_bb_stainfo::rsvd1 + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_rate + * Please Place Description here. + * @var mac_ax_bb_stainfo::dlsu_pwr + * Please Place Description here. + * @var mac_ax_bb_stainfo::rsvd2 + * Please Place Description here. + * @var mac_ax_bb_stainfo::rsvd4 + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_info_en + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_bw + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_gi_ltf + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_doppler_ctrl + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_dcm + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_ss + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_mcs + * Please Place Description here. + * @var mac_ax_bb_stainfo::ul_fwcqi_flag + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulru_ratetbl_ridx + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_stbc + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_coding + * Please Place Description here. + * @var mac_ax_bb_stainfo::ulsu_rssi_m + * Please Place Description here. + * @var mac_ax_bb_stainfo::ul_swgrp_bitmap + * Please Place Description here. + */ +struct mac_ax_bb_stainfo { + struct mac_ax_tbl_hdr tbl_hdr; +//sta capability + u8 gi_ltf_48spt:1; + u8 gi_ltf_18spt:1; + u8 rsvd3:6; +//downlink su + u8 dlsu_info_en:1; + u8 dlsu_bw:2; + u8 dlsu_gi_ltf:3; + u8 dlsu_doppler_ctrl:2; + u8 dlsu_coding:1; + u8 dlsu_txbf:1; + u8 dlsu_stbc:1; + u8 dl_fwcqi_flag:1; + u8 dlru_ratetbl_ridx:4; + u8 csi_info_bitmap; + u32 dl_swgrp_bitmap; + u16 dlsu_dcm:1; + u16 rsvd1:6; + u16 dlsu_rate:9; + u8 dlsu_pwr:6; + u8 rsvd2:2; + u8 rsvd4; +//uplink su + u8 ulsu_info_en:1; + u8 ulsu_bw:2; + u8 ulsu_gi_ltf:3; + u8 ulsu_doppler_ctrl:2; + u8 ulsu_dcm:1; + u8 ulsu_ss:3; + u8 ulsu_mcs:4; + u16 ul_fwcqi_flag:1; + u16 ulru_ratetbl_ridx:4; + u16 ulsu_stbc:1; + u16 ulsu_coding:1; + u16 ulsu_rssi_m:9; + u32 ul_swgrp_bitmap; +//tb info +}; + +/** + * @struct mac_ax_tf_depend_user_para + * @brief mac_ax_tf_depend_user_para + * + * @var mac_ax_tf_depend_user_para::pref_AC + * Please Place Description here. + * @var mac_ax_tf_depend_user_para::rsvd + * Please Place Description here. + */ +struct mac_ax_tf_depend_user_para { + u8 pref_AC: 2; + u8 rsvd: 6; +}; + +/** + * @struct mac_ax_tf_user_para + * @brief mac_ax_tf_user_para + * + * @var mac_ax_tf_user_para::aid12 + * Please Place Description here. + * @var mac_ax_tf_user_para::ul_mcs + * Please Place Description here. + * @var mac_ax_tf_user_para::macid + * Please Place Description here. + * @var mac_ax_tf_user_para::ru_pos + * Please Place Description here. + * @var mac_ax_tf_user_para::ul_fec_code + * Please Place Description here. + * @var mac_ax_tf_user_para::ul_dcm + * Please Place Description here. + * @var mac_ax_tf_user_para::ss_alloc + * Please Place Description here. + * @var mac_ax_tf_user_para::ul_tgt_rssi + * Please Place Description here. + * @var mac_ax_tf_user_para::rsvd + * Please Place Description here. + * @var mac_ax_tf_user_para::rsvd2 + * Please Place Description here. + */ +struct mac_ax_tf_user_para { + u16 aid12: 12; + u16 ul_mcs: 4; + u8 macid; + u8 ru_pos; + + u8 ul_fec_code: 1; + u8 ul_dcm: 1; + u8 ss_alloc: 6; + u8 ul_tgt_rssi: 7; + u8 rsvd: 1; + u16 rsvd2; +}; + +/** + * @struct mac_ax_tf_pkt_para + * @brief mac_ax_tf_pkt_para + * + * @var mac_ax_tf_pkt_para::ul_bw + * Please Place Description here. + * @var mac_ax_tf_pkt_para::gi_ltf + * Please Place Description here. + * @var mac_ax_tf_pkt_para::num_he_ltf + * Please Place Description here. + * @var mac_ax_tf_pkt_para::ul_stbc + * Please Place Description here. + * @var mac_ax_tf_pkt_para::doppler + * Please Place Description here. + * @var mac_ax_tf_pkt_para::ap_tx_power + * Please Place Description here. + * @var mac_ax_tf_pkt_para::rsvd0 + * Please Place Description here. + * @var mac_ax_tf_pkt_para::user_num + * Please Place Description here. + * @var mac_ax_tf_pkt_para::pktnum + * Please Place Description here. + * @var mac_ax_tf_pkt_para::rsvd1 + * Please Place Description here. + * @var mac_ax_tf_pkt_para::pri20_bitmap + * Please Place Description here. + * @var mac_ax_tf_pkt_para::user + * Please Place Description here. + * @var mac_ax_tf_pkt_para::dep_user + * Please Place Description here. + */ +struct mac_ax_tf_pkt_para { + u8 ul_bw: 2; + u8 gi_ltf: 2; + u8 num_he_ltf: 3; + u8 ul_stbc: 1; + u8 doppler: 1; + u8 ap_tx_power: 6; + u8 rsvd0: 1; + u8 user_num: 3; + u8 pktnum: 3; + u8 rsvd1: 2; + u8 pri20_bitmap; + + struct mac_ax_tf_user_para user[MAC_AX_MAX_RU_NUM]; + struct mac_ax_tf_depend_user_para dep_user[MAC_AX_MAX_RU_NUM]; +}; + +/** + * @struct mac_ax_tf_wd_para + * @brief mac_ax_tf_wd_para + * + * @var mac_ax_tf_wd_para::datarate + * Please Place Description here. + * @var mac_ax_tf_wd_para::mulport_id + * Please Place Description here. + * @var mac_ax_tf_wd_para::pwr_ofset + * Please Place Description here. + * @var mac_ax_tf_wd_para::rsvd + * Please Place Description here. + */ +struct mac_ax_tf_wd_para { + u16 datarate: 9; + u16 mulport_id: 3; + u16 pwr_ofset: 3; + u16 rsvd: 1; +}; + +/** + * @struct mac_ax_f2p_test_para + * @brief mac_ax_f2p_test_para + * + * @var mac_ax_f2p_test_para::tf_pkt + * Please Place Description here. + * @var mac_ax_f2p_test_para::tf_wd + * Please Place Description here. + * @var mac_ax_f2p_test_para::mode + * Please Place Description here. + * @var mac_ax_f2p_test_para::frexch_type + * Please Place Description here. + * @var mac_ax_f2p_test_para::sigb_len + * Please Place Description here. + */ +struct mac_ax_f2p_test_para { + struct mac_ax_tf_pkt_para tf_pkt; + struct mac_ax_tf_wd_para tf_wd; + u8 mode: 2; + u8 frexch_type: 6; + u8 sigb_len; +}; + +/** + * @struct mac_ax_f2p_wd + * @brief mac_ax_f2p_wd + * + * @var mac_ax_f2p_wd::cmd_qsel + * Please Place Description here. + * @var mac_ax_f2p_wd::rsvd0 + * Please Place Description here. + * @var mac_ax_f2p_wd::rsvd1 + * Please Place Description here. + * @var mac_ax_f2p_wd::ls + * Please Place Description here. + * @var mac_ax_f2p_wd::fs + * Please Place Description here. + * @var mac_ax_f2p_wd::total_number + * Please Place Description here. + * @var mac_ax_f2p_wd::seq + * Please Place Description here. + * @var mac_ax_f2p_wd::length + * Please Place Description here. + * @var mac_ax_f2p_wd::rsvd2 + * Please Place Description here. + */ +struct mac_ax_f2p_wd { + /* dword 0 */ + u32 cmd_qsel:6; + u32 rsvd0:2; + u32 rsvd1:2; + u32 ls:1; + u32 fs:1; + u32 total_number:4; + u32 seq:8; + u32 length:8; + /* dword 1 */ + u32 rsvd2; +}; + +/** + * @struct mac_ax_f2p_tx_cmd + * @brief mac_ax_f2p_tx_cmd + * + * @var mac_ax_f2p_tx_cmd::cmd_type + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::cmd_sub_type + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_user_num + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::bw + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::tx_power + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::fw_define + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ss_sel_mode + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::next_qsel + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::twt_group + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dis_chk_slp + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ru_mu_2_su + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_t_pe + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_ch1_len + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_ch2_len + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_sym_num + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_ch2_ofs + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dis_htp_ack + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::tx_time_ref + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pri_user_idx + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ampdu_max_txtime + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::group_id + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::twt_chk_en + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::twt_port_id + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::twt_start_time + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::twt_end_time + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::apep_len + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::tri_pad + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_t_pe + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rf_gain_idx + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::fixed_gain_en + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_gi_ltf + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_doppler + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_stbc + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_mid_per + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_cqi_rrp_tri + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd4 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_dcm + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_comp + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::doppler + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::stbc + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::mid_per + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::gi_ltf_size + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::sigb_mcs + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd5 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::macid_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ac_type_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::mu_sta_pos_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_rate_idx_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_dcm_en_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd6 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ru_alo_idx_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pwr_boost_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_ext_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_addr_idx_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_dcm_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_fec_cod_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_rate_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd8 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd9 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::macid_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ac_type_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::mu_sta_pos_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_rate_idx_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_dcm_en_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd10 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ru_alo_idx_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pwr_boost_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_ext_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_addr_idx_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_dcm_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_fec_cod_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_rate_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd12 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd13 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::macid_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ac_type_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::mu_sta_pos_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_rate_idx_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_dcm_en_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd14 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ru_alo_idx_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pwr_boost_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_ext_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_addr_idx_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_dcm_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_fec_cod_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_rate_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd16 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd17 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::macid_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ac_type_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::mu_sta_pos_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_rate_idx_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::dl_dcm_en_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd18 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ru_alo_idx_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pwr_boost_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::user_define_ext_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_addr_idx_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_dcm_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_fec_cod_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_rate_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd20 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd21 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd22 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_0 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd23 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd24 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_1 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd25 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd26 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_2 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd27 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd28 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_3 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd29 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_4 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd30 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_4 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_4 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd31 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::pkt_id_5 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd32 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::valid_5 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::ul_user_num_5 + * Please Place Description here. + * @var mac_ax_f2p_tx_cmd::rsvd33 + * Please Place Description here. + */ +struct mac_ax_f2p_tx_cmd { + /* dword 0 */ + u32 cmd_type:8; + u32 cmd_sub_type:8; + u32 dl_user_num:5; + u32 bw:2; + u32 tx_power:9; + /* dword 1 */ + u32 fw_define:16; + u32 ss_sel_mode:2; + u32 next_qsel:6; + u32 twt_group:4; + u32 dis_chk_slp:1; + u32 ru_mu_2_su:1; + u32 dl_t_pe:2; + /* dword 2 */ + u32 sigb_ch1_len:8; + u32 sigb_ch2_len:8; + u32 sigb_sym_num:6; + u32 sigb_ch2_ofs:5; + u32 dis_htp_ack:1; + u32 tx_time_ref:2; + u32 pri_user_idx:2; + /* dword 3 */ + u32 ampdu_max_txtime:14; + u32 rsvd0:2; + u32 group_id:6; + u32 rsvd1:2; + u32 rsvd2:4; + u32 twt_chk_en:1; + u32 twt_port_id:3; + /* dword 4 */ + u32 twt_start_time:32; + /* dword 5 */ + u32 twt_end_time:32; + /* dword 6 */ + u32 apep_len:12; + u32 tri_pad:2; + u32 ul_t_pe:2; + u32 rf_gain_idx:10; + u32 fixed_gain_en:1; + u32 ul_gi_ltf:3; + u32 ul_doppler:1; + u32 ul_stbc:1; + /* dword 7 */ + u32 ul_mid_per:1; + u32 ul_cqi_rrp_tri:1; + u32 rsvd3:6; + u32 rsvd4:8; + u32 sigb_dcm:1; + u32 sigb_comp:1; + u32 doppler:1; + u32 stbc:1; + u32 mid_per:1; + u32 gi_ltf_size:3; + u32 sigb_mcs:3; + u32 rsvd5:5; + /* dword 8 */ + u32 macid_u0:8; + u32 ac_type_u0:2; + u32 mu_sta_pos_u0:2; + u32 dl_rate_idx_u0:9; + u32 dl_dcm_en_u0:1; + u32 rsvd6:2; + u32 ru_alo_idx_u0:8; + /* dword 9 */ + u32 pwr_boost_u0:5; + u32 agg_bmp_alo_u0:3; + u32 ampdu_max_txnum_u0:8; + u32 user_define_u0:8; + u32 user_define_ext_u0:8; + /* dword 10 */ + u32 ul_addr_idx_u0:8; + u32 ul_dcm_u0:1; + u32 ul_fec_cod_u0:1; + u32 ul_ru_rate_u0:7; + u32 rsvd8:7; + u32 ul_ru_alo_idx_u0:8; + /* dword 11 */ + u32 rsvd9:32; + /* dword 12 */ + u32 macid_u1:8; + u32 ac_type_u1:2; + u32 mu_sta_pos_u1:2; + u32 dl_rate_idx_u1:9; + u32 dl_dcm_en_u1:1; + u32 rsvd10:2; + u32 ru_alo_idx_u1:8; + /* dword 13 */ + u32 pwr_boost_u1:5; + u32 agg_bmp_alo_u1:3; + u32 ampdu_max_txnum_u1:8; + u32 user_define_u1:8; + u32 user_define_ext_u1:8; + /* dword 14 */ + u32 ul_addr_idx_u1:8; + u32 ul_dcm_u1:1; + u32 ul_fec_cod_u1:1; + u32 ul_ru_rate_u1:7; + u32 rsvd12:7; + u32 ul_ru_alo_idx_u1:8; + /* dword 15 */ + u32 rsvd13:32; + /* dword 16 */ + u32 macid_u2:8; + u32 ac_type_u2:2; + u32 mu_sta_pos_u2:2; + u32 dl_rate_idx_u2:9; + u32 dl_dcm_en_u2:1; + u32 rsvd14:2; + u32 ru_alo_idx_u2:8; + /* dword 17 */ + u32 pwr_boost_u2:5; + u32 agg_bmp_alo_u2:3; + u32 ampdu_max_txnum_u2:8; + u32 user_define_u2:8; + u32 user_define_ext_u2:8; + /* dword 18 */ + u32 ul_addr_idx_u2:8; + u32 ul_dcm_u2:1; + u32 ul_fec_cod_u2:1; + u32 ul_ru_rate_u2:7; + u32 rsvd16:7; + u32 ul_ru_alo_idx_u2:8; + /* dword 19 */ + u32 rsvd17:32; + /* dword 20 */ + u32 macid_u3:8; + u32 ac_type_u3:2; + u32 mu_sta_pos_u3:2; + u32 dl_rate_idx_u3:9; + u32 dl_dcm_en_u3:1; + u32 rsvd18:2; + u32 ru_alo_idx_u3:8; + /* dword 21 */ + u32 pwr_boost_u3:5; + u32 agg_bmp_alo_u3:3; + u32 ampdu_max_txnum_u3:8; + u32 user_define_u3:8; + u32 user_define_ext_u3:8; + /* dword 22 */ + u32 ul_addr_idx_u3:8; + u32 ul_dcm_u3:1; + u32 ul_fec_cod_u3:1; + u32 ul_ru_rate_u3:7; + u32 rsvd20:7; + u32 ul_ru_alo_idx_u3:8; + /* dword 23 */ + u32 rsvd21:32; + /* dword 24 */ + u32 pkt_id_0:12; + u32 rsvd22:3; + u32 valid_0:1; + u32 ul_user_num_0:4; + u32 rsvd23:12; + /* dword 25 */ + u32 pkt_id_1:12; + u32 rsvd24:3; + u32 valid_1:1; + u32 ul_user_num_1:4; + u32 rsvd25:12; + /* dword 26 */ + u32 pkt_id_2:12; + u32 rsvd26:3; + u32 valid_2:1; + u32 ul_user_num_2:4; + u32 rsvd27:12; + /* dword 27 */ + u32 pkt_id_3:12; + u32 rsvd28:3; + u32 valid_3:1; + u32 ul_user_num_3:4; + u32 rsvd29:12; + /* dword 28 */ + u32 pkt_id_4:12; + u32 rsvd30:3; + u32 valid_4:1; + u32 ul_user_num_4:4; + u32 rsvd31:12; + /* dword 29 */ + u32 pkt_id_5:12; + u32 rsvd32:3; + u32 valid_5:1; + u32 ul_user_num_5:4; + u32 rsvd33:12; +}; + +/*--------------------Define Sounding related struct -------------------------*/ + +/** + * @struct mac_reg_csi_para + * @brief mac_reg_csi_para + * + * @var mac_reg_csi_para::band + * Please Place Description here. + * @var mac_reg_csi_para::portsel + * Please Place Description here. + * @var mac_reg_csi_para::nc + * Please Place Description here. + * @var mac_reg_csi_para::nr + * Please Place Description here. + * @var mac_reg_csi_para::ng + * Please Place Description here. + * @var mac_reg_csi_para::cb + * Please Place Description here. + * @var mac_reg_csi_para::cs + * Please Place Description here. + * @var mac_reg_csi_para::ldpc_en + * Please Place Description here. + * @var mac_reg_csi_para::stbc_en + * Please Place Description here. + * @var mac_reg_csi_para::bf_en + * Please Place Description here. + */ +struct mac_reg_csi_para { + u32 band: 1; + u32 portsel: 1; + u32 nc: 3; + u32 nr: 3; + u32 ng: 2; + u32 cb: 2; + u32 cs: 2; + u32 ldpc_en: 1; + u32 stbc_en: 1; + u32 bf_en: 1; +}; + +/** + * @struct mac_cctl_csi_para + * @brief mac_cctl_csi_para + * + * @var mac_cctl_csi_para::macid + * Please Place Description here. + * @var mac_cctl_csi_para::band + * Please Place Description here. + * @var mac_cctl_csi_para::nc + * Please Place Description here. + * @var mac_cctl_csi_para::nr + * Please Place Description here. + * @var mac_cctl_csi_para::ng + * Please Place Description here. + * @var mac_cctl_csi_para::cb + * Please Place Description here. + * @var mac_cctl_csi_para::cs + * Please Place Description here. + * @var mac_cctl_csi_para::bf_en + * Please Place Description here. + * @var mac_cctl_csi_para::stbc_en + * Please Place Description here. + * @var mac_cctl_csi_para::ldpc_en + * Please Place Description here. + * @var mac_cctl_csi_para::rate + * Please Place Description here. + * @var mac_cctl_csi_para::gi_ltf + * Please Place Description here. + * @var mac_cctl_csi_para::gid_sel + * Please Place Description here. + * @var mac_cctl_csi_para::bw + * Please Place Description here. + */ +struct mac_cctl_csi_para { + u8 macid; + u32 band: 1; + u32 nc: 3; + u32 nr: 3; + u32 ng: 2; + u32 cb: 2; + u32 cs: 2; + u32 bf_en: 1; + u32 stbc_en: 1; + u32 ldpc_en: 1; + u32 rate: 9; + u32 gi_ltf: 3; + u32 gid_sel: 1; + u32 bw: 2; +}; + +/** + * @struct mac_bf_sup + * @brief mac_bf_sup + * + * @var mac_bf_sup::bf_entry_num + * Please Place Description here. + * @var mac_bf_sup::su_buffer_num + * Please Place Description here. + * @var mac_bf_sup::mu_buffer_num + * Please Place Description here. + */ +struct mac_bf_sup { + u32 bf_entry_num; + u32 su_buffer_num; + u32 mu_buffer_num; +}; + +/** + * @struct mac_gid_pos + * @brief mac_gid_pos + * + * @var mac_gid_pos::gid_en + * Please Place Description here. + * @var mac_gid_pos::gid_pos + * Please Place Description here. + */ +struct mac_gid_pos { + u32 band; + u32 gid_tab[2]; + u32 user_pos[4]; +}; + +/** + * @struct mac_ax_ndpa_hdr + * @brief mac_ax_ndpa_hdr + * + * @var mac_ax_ndpa_hdr::frame_ctl + * Please Place Description here. + * @var mac_ax_ndpa_hdr::duration + * Please Place Description here. + * @var mac_ax_ndpa_hdr::addr1 + * Please Place Description here. + * @var mac_ax_ndpa_hdr::addr2 + * Please Place Description here. + */ +struct mac_ax_ndpa_hdr { + u16 frame_ctl; + u16 duration; + u8 addr1[6]; + u8 addr2[6]; +}; + +/** + * @struct mac_ax_snd_dialog + * @brief mac_ax_snd_dialog + * + * @var mac_ax_snd_dialog::he + * Please Place Description here. + * @var mac_ax_snd_dialog::dialog + * Please Place Description here. + * @var mac_ax_snd_dialog::rsvd + * Please Place Description here. + */ +struct mac_ax_snd_dialog { + u32 he: 1; + u32 dialog: 6; + u32 rsvd: 25; +}; + +/** + * @struct mac_ax_ht_ndpa_para + * @brief mac_ax_ht_ndpa_para + * + * @var mac_ax_ht_ndpa_para::addr3 + * Please Place Description here. + * @var mac_ax_ht_ndpa_para::seq_control + * Please Place Description here. + */ +struct mac_ax_ht_ndpa_para { + u8 addr3[WLAN_ADDR_LEN]; + u16 seq_control; +}; + +/** + * @struct mac_ax_vht_ndpa_sta_info + * @brief mac_ax_vht_ndpa_sta_info + * + * @var mac_ax_vht_ndpa_sta_info::aid + * Please Place Description here. + * @var mac_ax_vht_ndpa_sta_info::fb_type + * Please Place Description here. + * @var mac_ax_vht_ndpa_sta_info::nc + * Please Place Description here. + */ +struct mac_ax_vht_ndpa_sta_info { + u16 aid: 12; + u16 fb_type: 1; + u16 nc: 3; +}; + +/** + * @struct mac_ax_vht_ndpa_para + * @brief mac_ax_vht_ndpa_para + * + * @var mac_ax_vht_ndpa_para::sta_info + * Please Place Description here. + */ +struct mac_ax_vht_ndpa_para { + struct mac_ax_vht_ndpa_sta_info sta_info[MAX_VHT_SUPPORT_SOUND_STA]; +}; + +/** + * @struct mac_ax_he_ndpa_sta_info + * @brief mac_ax_he_ndpa_sta_info + * + * @var mac_ax_he_ndpa_sta_info::aid + * Please Place Description here. + * @var mac_ax_he_ndpa_sta_info::bw + * Please Place Description here. + * @var mac_ax_he_ndpa_sta_info::fb_ng + * Please Place Description here. + * @var mac_ax_he_ndpa_sta_info::disambiguation + * Please Place Description here. + * @var mac_ax_he_ndpa_sta_info::cb + * Please Place Description here. + * @var mac_ax_he_ndpa_sta_info::nc + * Please Place Description here. + */ +struct mac_ax_he_ndpa_sta_info { + u32 aid: 11; + u32 bw: 14; + u32 fb_ng: 2; + u32 disambiguation: 1; + u32 cb: 1; + u32 nc: 3; +}; + +/** + * @struct mac_ax_he_ndpa_para + * @brief mac_ax_he_ndpa_para + * + * @var mac_ax_he_ndpa_para::sta_info + * Please Place Description here. + */ +struct mac_ax_he_ndpa_para { + struct mac_ax_he_ndpa_sta_info sta_info[MAX_HE_SUPPORT_SOUND_STA]; +}; + +/** + * @struct mac_ax_ndpa_para + * @brief mac_ax_ndpa_para + * + * @var mac_ax_ndpa_para::common + * Please Place Description here. + * @var mac_ax_ndpa_para::snd_dialog + * Please Place Description here. + * @var mac_ax_ndpa_para::ht_para + * Please Place Description here. + * @var mac_ax_ndpa_para::vht_para + * Please Place Description here. + * @var mac_ax_ndpa_para::he_para + * Please Place Description here. + */ +struct mac_ax_ndpa_para { + struct mac_ax_ndpa_hdr common; + struct mac_ax_snd_dialog snd_dialog; + struct mac_ax_ht_ndpa_para ht_para; + struct mac_ax_vht_ndpa_para vht_para; + struct mac_ax_he_ndpa_para he_para; +}; + +/** + * @struct mac_ax_bfrp_hdr + * @brief mac_ax_bfrp_hdr + * + * @var mac_ax_bfrp_hdr::frame_ctl + * Please Place Description here. + * @var mac_ax_bfrp_hdr::duration + * Please Place Description here. + * @var mac_ax_bfrp_hdr::addr1 + * Please Place Description here. + * @var mac_ax_bfrp_hdr::addr2 + * Please Place Description here. + */ +struct mac_ax_bfrp_hdr { + u16 frame_ctl; + u16 duration; + u8 addr1[WLAN_ADDR_LEN]; + u8 addr2[WLAN_ADDR_LEN]; +}; + +/** + * @struct mac_ax_vht_bfrp_para + * @brief mac_ax_vht_bfrp_para + * + * @var mac_ax_vht_bfrp_para::retransmission_bitmap + * Please Place Description here. + */ +struct mac_ax_vht_bfrp_para { + u8 retransmission_bitmap; +}; + +/** + * @struct mac_ax_he_bfrp_common + * @brief mac_ax_he_bfrp_common + * + * @var mac_ax_he_bfrp_common::tgr_info + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_len + * Please Place Description here. + * @var mac_ax_he_bfrp_common::more_tf + * Please Place Description here. + * @var mac_ax_he_bfrp_common::cs_rqd + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_bw + * Please Place Description here. + * @var mac_ax_he_bfrp_common::gi_ltf + * Please Place Description here. + * @var mac_ax_he_bfrp_common::mimo_ltfmode + * Please Place Description here. + * @var mac_ax_he_bfrp_common::num_heltf + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_pktext + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_stbc + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ldpc_extra_sym + * Please Place Description here. + * @var mac_ax_he_bfrp_common::dplr + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ap_tx_pwr + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_sr + * Please Place Description here. + * @var mac_ax_he_bfrp_common::ul_siga2_rsvd + * Please Place Description here. + * @var mac_ax_he_bfrp_common::rsvd + * Please Place Description here. + */ +struct mac_ax_he_bfrp_common { + u32 tgr_info: 4; + u32 ul_len: 12; + u32 more_tf: 1; + u32 cs_rqd: 1; + u32 ul_bw: 2; + u32 gi_ltf: 2; + u32 mimo_ltfmode: 1; + u32 num_heltf: 3; + u32 ul_pktext: 3; + u32 ul_stbc: 1; + u32 ldpc_extra_sym: 1; + u32 dplr: 1; + + u32 ap_tx_pwr: 6; + u32 ul_sr: 16; + u32 ul_siga2_rsvd: 9; + u32 rsvd: 1; +}; + +/** + * @struct mac_ax_he_bfrp_user + * @brief mac_ax_he_bfrp_user + * + * @var mac_ax_he_bfrp_user::aid12 + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ru_pos + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ul_fec_code + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ul_mcs + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ul_dcm + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ss_alloc + * Please Place Description here. + * @var mac_ax_he_bfrp_user::fbseg_rexmit_bmp + * Please Place Description here. + * @var mac_ax_he_bfrp_user::ul_tgt_rssi + * Please Place Description here. + * @var mac_ax_he_bfrp_user::rsvd + * Please Place Description here. + */ +struct mac_ax_he_bfrp_user { + u32 aid12: 12; + u32 ru_pos: 8; + u32 ul_fec_code: 1; + u32 ul_mcs: 4; + u32 ul_dcm: 1; + u32 ss_alloc: 6; + + u32 fbseg_rexmit_bmp: 8; + u32 ul_tgt_rssi: 7; + u32 rsvd: 17; +}; + +/** + * @struct mac_ax_he_bfrp_para + * @brief mac_ax_he_bfrp_para + * + * @var mac_ax_he_bfrp_para::common + * Please Place Description here. + * @var mac_ax_he_bfrp_para::user + * Please Place Description here. + */ +struct mac_ax_he_bfrp_para { + struct mac_ax_he_bfrp_common common; + struct mac_ax_he_bfrp_user user[4]; +}; + +/** + * @struct mac_ax_bfrp_para + * @brief mac_ax_bfrp_para + * + * @var mac_ax_bfrp_para::hdr + * Please Place Description here. + * @var mac_ax_bfrp_para::he_para + * Please Place Description here. + * @var mac_ax_bfrp_para::vht_para + * Please Place Description here. + * @var mac_ax_bfrp_para::rsvd + * Please Place Description here. + */ +struct mac_ax_bfrp_para { + struct mac_ax_bfrp_hdr hdr[3]; + struct mac_ax_he_bfrp_para he_para[2]; + struct mac_ax_vht_bfrp_para vht_para[3]; + u8 rsvd; +}; + +/** + * @struct mac_ax_snd_wd_para + * @brief mac_ax_snd_wd_para + * + * @var mac_ax_snd_wd_para::txpktsize + * Please Place Description here. + * @var mac_ax_snd_wd_para::ndpa_duration + * Please Place Description here. + * @var mac_ax_snd_wd_para::datarate + * Please Place Description here. + * @var mac_ax_snd_wd_para::macid + * Please Place Description here. + * @var mac_ax_snd_wd_para::force_txop + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_bw + * Please Place Description here. + * @var mac_ax_snd_wd_para::gi_ltf + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_er + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_dcm + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_stbc + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_ldpc + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_bw_er + * Please Place Description here. + * @var mac_ax_snd_wd_para::multiport_id + * Please Place Description here. + * @var mac_ax_snd_wd_para::mbssid + * Please Place Description here. + * @var mac_ax_snd_wd_para::signaling_ta_pkt_sc + * Please Place Description here. + * @var mac_ax_snd_wd_para::sw_define + * Please Place Description here. + * @var mac_ax_snd_wd_para::txpwr_ofset_type + * Please Place Description here. + * @var mac_ax_snd_wd_para::lifetime_sel + * Please Place Description here. + * @var mac_ax_snd_wd_para::stf_mode + * Please Place Description here. + * @var mac_ax_snd_wd_para::disdatafb + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_txcnt_lmt_sel + * Please Place Description here. + * @var mac_ax_snd_wd_para::data_txcnt_lmt + * Please Place Description here. + * @var mac_ax_snd_wd_para::sifs_tx + * Please Place Description here. + * @var mac_ax_snd_wd_para::snd_pkt_sel + * Please Place Description here. + * @var mac_ax_snd_wd_para::ndpa + * Please Place Description here. + * @var mac_ax_snd_wd_para::rsvd + * Please Place Description here. + */ +struct mac_ax_snd_wd_para { + u16 txpktsize; + u16 ndpa_duration; + + u16 datarate: 9; + u16 macid: 7;//wd + u8 force_txop: 1; + u8 data_bw: 2; + u8 gi_ltf: 3; + u8 data_er: 1; + u8 data_dcm: 1; + u8 data_stbc: 1; + u8 data_ldpc: 1; + u8 data_bw_er : 1; + u8 multiport_id: 1; + u8 mbssid: 4; + + u8 signaling_ta_pkt_sc: 4; + u8 sw_define: 4; + u8 txpwr_ofset_type: 3; + u8 lifetime_sel: 3; + u8 stf_mode: 1; + u8 disdatafb: 1; + u8 data_txcnt_lmt_sel: 1; + u8 data_txcnt_lmt: 6; + u8 sifs_tx: 1; + u8 snd_pkt_sel: 3; + u8 ndpa: 2; + u8 rsvd: 3; +}; + +/** + * @struct mac_ax_snd_f2P + * @brief mac_ax_snd_f2P + * + * @var mac_ax_snd_f2P::csi_len_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::tb_t_pe_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::tri_pad_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::ul_cqi_rpt_tri_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::rf_gain_idx_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::fix_gain_en_bfrp + * Please Place Description here. + * @var mac_ax_snd_f2P::rsvd + * Please Place Description here. + */ +struct mac_ax_snd_f2P { + u16 csi_len_bfrp: 12; + u16 tb_t_pe_bfrp: 2; + u16 tri_pad_bfrp: 2; + + u16 ul_cqi_rpt_tri_bfrp: 1; + u16 rf_gain_idx_bfrp: 10; + u16 fix_gain_en_bfrp: 1; + u16 rsvd: 4; +}; + +/** + * @struct mac_ax_snd_f2P_info + * @brief mac_ax_snd_f2P_info + * + * @var mac_ax_snd_f2p_info::f2p_type + * Please Place Description here. + * @var mac_ax_snd_f2p_info::f2p_index + * Please Place Description here. + * @var mac_ax_snd_f2p_info::f2p_period + * Please Place Description here. + * @var mac_ax_snd_f2p_info::f2p_updcnt + * Please Place Description here. + * @var mac_ax_snd_f2p_info:cr_idx + * Please Place Description here. + * @var mac_ax_snd_f2p_info::rsvd + * Please Place Description here.. + */ +struct mac_ax_snd_f2p_info { + u16 f2p_type: 8; + u16 f2p_index: 8; + u16 f2p_period; + + u32 f2p_updcnt: 8; + u32 cr_idx: 22; + u32 rsvd: 2; +}; + +/** + * @struct mac_ax_fwcmd_snd + * @brief mac_ax_fwcmd_snd + * + * @var mac_ax_fwcmd_snd::frexgtype + * Please Place Description here. + * @var mac_ax_fwcmd_snd::mode + * Please Place Description here. + * @var mac_ax_fwcmd_snd::bfrp0_user_num + * Please Place Description here. + * @var mac_ax_fwcmd_snd::bfrp1_user_num + * Please Place Description here. + * @var mac_ax_fwcmd_snd::rsvd + * Please Place Description here. + * @var mac_ax_fwcmd_snd::macid + * Please Place Description here. + * @var mac_ax_fwcmd_snd::pndpa + * Please Place Description here. + * @var mac_ax_fwcmd_snd::pbfrp + * Please Place Description here. + * @var mac_ax_fwcmd_snd::wd + * Please Place Description here. + * @var mac_ax_fwcmd_snd::f2p + * Please Place Description here. + */ +struct mac_ax_fwcmd_snd { + u32 frexgtype: 6; + u32 mode: 2; + u32 bfrp0_user_num: 3; + u32 bfrp1_user_num: 3; + u32 rsvd: 18; + u8 macid[8]; + struct mac_ax_ndpa_para pndpa; + struct mac_ax_bfrp_para pbfrp; + struct mac_ax_snd_wd_para wd[5]; + struct mac_ax_snd_f2P f2p[2]; + struct mac_ax_snd_f2p_info sfp; +}; + +/** + * @struct mac_ax_ie_cam_info + * @brief mac_ax_ie_cam_info + * + * @var mac_ax_ie_cam_info::type + * Please Place Description here. + * @var mac_ax_ie_cam_info::ienum_ie + * Please Place Description here. + * @var mac_ax_ie_cam_info::ie_ofst_len + * Please Place Description here. + * @var mac_ax_ie_cam_info::ie_msk_crc + * Please Place Description here. + * @var mac_ax_ie_cam_info::ie_val + * Please Place Description here. + * @var mac_ax_ie_cam_info::rsvd0 + * Please Place Description here. + * @var mac_ax_ie_cam_info::rsvd1 + * Please Place Description here. + * @var mac_ax_ie_cam_info::rsvd2 + * Please Place Description here. + */ +struct mac_ax_ie_cam_info { + u8 type; + u8 ienum_ie; + u8 ie_ofst_len; + u8 ie_msk_crc; + u8 ie_val; + u8 rsvd0; + u8 rsvd1; + u8 rsvd2; +}; + +/*--------------------Define wowlan related struct ---------------------------*/ + +/** + * @struct mac_ax_keep_alive_info + * @brief mac_ax_keep_alive_info + * + * @var mac_ax_keep_alive_info::keepalive_en + * Please Place Description here. + * @var mac_ax_keep_alive_info::rsvd + * Please Place Description here. + * @var mac_ax_keep_alive_info::packet_id + * Please Place Description here. + * @var mac_ax_keep_alive_info::period + * Please Place Description here. + */ +struct mac_ax_keep_alive_info { + u8 keepalive_en: 1; + u8 rsvd: 7; + u8 packet_id; + u8 period; +}; + +/** + * @struct mac_ax_disconnect_det_info + * @brief mac_ax_disconnect_det_info + * + * @var mac_ax_disconnect_det_info::disconnect_detect_en + * Please Place Description here. + * @var mac_ax_disconnect_det_info::tryok_bcnfail_count_en + * Please Place Description here. + * @var mac_ax_disconnect_det_info::disconnect_en + * Please Place Description here. + * @var mac_ax_disconnect_det_info::rsvd + * Please Place Description here. + * @var mac_ax_disconnect_det_info::check_period + * Please Place Description here. + * @var mac_ax_disconnect_det_info::try_pkt_count + * Please Place Description here. + * @var mac_ax_disconnect_det_info::tryok_bcnfail_count_limit + * Please Place Description here. + */ +struct mac_ax_disconnect_det_info { + u8 disconnect_detect_en: 1; + u8 tryok_bcnfail_count_en: 1; + u8 disconnect_en: 1; + u8 rsvd: 5; + u8 check_period; + u8 try_pkt_count; + u8 tryok_bcnfail_count_limit; +}; + +/** + * @enum mac_ax_enc_alg + * + * @brief mac_ax_enc_alg + * + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_NONE + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WEP40 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WEP104 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_TKIP + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WAPI + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMSMS4 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_CCMP + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_CCMP256 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMP + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMP256 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_BIP_CCMP128 + * Please Place Description here. + * @var mac_ax_enc_alg::MAC_AX_RTW_ENC_MAX + * Please Place Description here. + */ +enum mac_ax_enc_alg { + MAC_AX_RTW_ENC_NONE = 0, + MAC_AX_RTW_ENC_WEP40 = 1, + MAC_AX_RTW_ENC_WEP104, + MAC_AX_RTW_ENC_TKIP, + MAC_AX_RTW_ENC_WAPI, + MAC_AX_RTW_ENC_GCMSMS4, + MAC_AX_RTW_ENC_CCMP, + MAC_AX_RTW_ENC_CCMP256, + MAC_AX_RTW_ENC_GCMP, + MAC_AX_RTW_ENC_GCMP256, + MAC_AX_RTW_ENC_BIP_CCMP128, + MAC_AX_RTW_ENC_MAX +}; + +/** + * @enum bip_sec_algo_type + * + * @brief bip_sec_algo_type + * + * @var bip_sec_algo_type::BIP_CMAC_128 + * Please Place Description here. + * @var bip_sec_algo_type::BIP_CMAC_256 + * Please Place Description here. + * @var bip_sec_algo_type::BIP_GMAC_128 + * Please Place Description here. + * @var bip_sec_algo_type::BIP_GMAC_256 + * Please Place Description here. + */ +enum bip_sec_algo_type { + BIP_CMAC_128 = 0, + BIP_CMAC_256 = 1, + BIP_GMAC_128 = 2, + BIP_GMAC_256 = 3 +}; + +/** + * @struct mac_ax_wow_wake_info + * @brief mac_ax_wow_wake_info + * + * @var mac_ax_wow_wake_info::wow_en + * Please Place Description here. + * @var mac_ax_wow_wake_info::drop_all_pkt + * Please Place Description here. + * @var mac_ax_wow_wake_info::rx_parse_after_wake + * Please Place Description here. + * @var mac_ax_wow_wake_info::rsvd + * Please Place Description here. + * @var mac_ax_wow_wake_info::pairwise_sec_algo + * Please Place Description here. + * @var mac_ax_wow_wake_info::group_sec_algo + * Please Place Description here. + * @var mac_ax_wow_wake_info::remotectrl_info_content + * Please Place Description here. + * @var mac_ax_wow_wake_info::pattern_match_en + * Please Place Description here. + * @var mac_ax_wow_wake_info::magic_en + * Please Place Description here. + * @var mac_ax_wow_wake_info::hw_unicast_en + * Please Place Description here. + * @var mac_ax_wow_wake_info::fw_unicast_en + * Please Place Description here. + * @var mac_ax_wow_wake_info::deauth_wakeup + * Please Place Description here. + * @var mac_ax_wow_wake_info::rekey_wakeup + * Please Place Description here. + * @var mac_ax_wow_wake_info::eap_wakeup + * Please Place Description here. + * @var mac_ax_wow_wake_info::all_data_wakeup + * Please Place Description here. + */ +struct mac_ax_wow_wake_info { + u8 wow_en: 1; + u8 drop_all_pkt: 1; + u8 rx_parse_after_wake: 1; + u8 rsvd: 5; + enum mac_ax_enc_alg pairwise_sec_algo; + enum mac_ax_enc_alg group_sec_algo; + u32 remotectrl_info_content; + u8 pattern_match_en: 1; + u8 magic_en: 1; + u8 hw_unicast_en: 1; + u8 fw_unicast_en: 1; + u8 deauth_wakeup: 1; + u8 rekey_wakeup: 1; + u8 eap_wakeup: 1; + u8 all_data_wakeup: 1; +}; + +#define IV_LENGTH 8 + +/** + * @struct mac_ax_remotectrl_info_parm_ + * @brief mac_ax_remotectrl_info_parm_ + * + * @var mac_ax_remotectrl_info_parm_::ptktxiv + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::validcheck + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::symbolchecken + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::lastkeyid + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rsvd + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rxptkiv + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rxgtkiv_0 + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rxgtkiv_1 + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rxgtkiv_2 + * Please Place Description here. + * @var mac_ax_remotectrl_info_parm_::rxgtkiv_3 + * Please Place Description here. + */ +struct mac_ax_remotectrl_info_parm_ { + u8 ptktxiv[IV_LENGTH]; + /* value = 0xdd */ + u8 validcheck; + /* bit0 : check ptk, bit1 : check gtk */ + u8 symbolchecken; + /* the last gtk index used by driver */ + u8 lastkeyid; + u8 rsvd[5]; + /* unicast iv */ + u8 rxptkiv[IV_LENGTH]; + /* broadcast/mulicast iv, 4 gtk index */ + u8 rxgtkiv_0[IV_LENGTH]; + u8 rxgtkiv_1[IV_LENGTH]; + u8 rxgtkiv_2[IV_LENGTH]; + u8 rxgtkiv_3[IV_LENGTH]; +}; + +/** + * @struct mac_ax_wake_ctrl_info + * @brief mac_ax_wake_ctrl_info + * + * @var mac_ax_wake_ctrl_info::pattern_match_en + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::magic_en + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::hw_unicast_en + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::fw_unicast_en + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::deauth_wakeup + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::rekey_wakeup + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::eap_wakeup + * Please Place Description here. + * @var mac_ax_wake_ctrl_info::all_data_wakeup + * Please Place Description here. + */ +struct mac_ax_wake_ctrl_info { + u8 pattern_match_en: 1; + u8 magic_en: 1; + u8 hw_unicast_en: 1; + u8 fw_unicast_en: 1; + u8 deauth_wakeup: 1; + u8 rekey_wakeup: 1; + u8 eap_wakeup: 1; + u8 all_data_wakeup: 1; +}; + +/** + * @struct mac_ax_gtk_ofld_info + * @brief mac_ax_gtk_ofld_info + * + * @var mac_ax_gtk_ofld_info::gtk_en + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::tkip_en + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::ieee80211w_en + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::pairwise_wakeup + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::bip_sec_algo + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::rsvd + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::gtk_rsp_id + * Please Place Description here. + * @var mac_ax_gtk_ofld_info::pmf_sa_query_id + * Please Place Description here. + */ +struct mac_ax_gtk_ofld_info { + u8 gtk_en: 1; + u8 tkip_en: 1; + u8 ieee80211w_en: 1; + u8 pairwise_wakeup: 1; + u8 bip_sec_algo: 2; + u8 rsvd: 2; + u8 gtk_rsp_id: 8; + u8 pmf_sa_query_id: 8; + u8 algo_akm_suit: 8; +}; + +#define AOAC_REPORT_VERSION 1 + +/** + * @struct mac_ax_aoac_report + * @brief mac_ax_aoac_report + * + * @var mac_ax_aoac_report::rpt_ver + * Please Place Description here. + * @var mac_ax_aoac_report::sec_type + * Please Place Description here. + * @var mac_ax_aoac_report::key_idx + * Please Place Description here. + * @var mac_ax_aoac_report::pattern_idx + * Please Place Description here. + * @var mac_ax_aoac_report::rekey_ok + * Please Place Description here. + * @var mac_ax_aoac_report::rsvd0 + * Please Place Description here. + * @var mac_ax_aoac_report::rsvd1 + * Please Place Description here. + * @var mac_ax_aoac_report::ptk_tx_iv + * Please Place Description here. + * @var mac_ax_aoac_report::eapol_key_replay_count + * Please Place Description here. + * @var mac_ax_aoac_report::gtk + * Please Place Description here. + * @var mac_ax_aoac_report::ptk_rx_iv + * Please Place Description here. + * @var mac_ax_aoac_report::gtk_rx_iv_0 + * Please Place Description here. + * @var mac_ax_aoac_report::gtk_rx_iv_1 + * Please Place Description here. + * @var mac_ax_aoac_report::gtk_rx_iv_2 + * Please Place Description here. + * @var mac_ax_aoac_report::gtk_rx_iv_3 + * Please Place Description here. + * @var mac_ax_aoac_report::igtk_key_id + * Please Place Description here. + * @var mac_ax_aoac_report::igtk_ipn + * Please Place Description here. + * @var mac_ax_aoac_report::igtk + * Please Place Description here. + */ +struct mac_ax_aoac_report { + u8 rpt_ver; + u8 sec_type; + u8 key_idx; + u8 pattern_idx; + u8 rekey_ok: 1; + u8 rsvd0: 7; + u8 rsvd1[3]; + u8 ptk_tx_iv[IV_LENGTH]; + u8 eapol_key_replay_count[8]; + u8 gtk[32]; + u8 ptk_rx_iv[IV_LENGTH]; + u8 gtk_rx_iv_0[IV_LENGTH]; + u8 gtk_rx_iv_1[IV_LENGTH]; + u8 gtk_rx_iv_2[IV_LENGTH]; + u8 gtk_rx_iv_3[IV_LENGTH]; + u8 igtk_key_id[8]; + u8 igtk_ipn[8]; + u8 igtk[32]; +}; + +#define EAPOL_KCK_LENGTH 32 +#define EAPOL_KEK_LENGTH 32 +#define TKIP_TK_LENGTH 16 +#define TKIP_MIC_KEY_LENGTH 8 +#define IGTK_KEY_ID_LENGTH 4 +#define IGTK_PKT_NUM_LENGTH 8 +#define IGTK_LENGTH 16 +#define IGTK_OFFSET 4 + +union keytype { + u8 SKEY[32]; + u32 LKEY[4]; +}; + +/** + * @struct mac_ax_gtk_info_parm_ + * @brief mac_ax_gtk_info_parm_ + * + * @var mac_ax_gtk_info_parm_::kck + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::kek + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::tk1 + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::txmickey + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::rxmickey + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::igtk_keyid + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::ipn + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::igtk + * Please Place Description here. + * @var mac_ax_gtk_info_parm_::sk + * Please Place Description here. + */ +struct mac_ax_gtk_info_parm_ { + /* eapol - key confirmation key (kck) */ + u8 kck[EAPOL_KCK_LENGTH]; + /* eapol - key encryption key (kek) */ + u8 kek[EAPOL_KEK_LENGTH]; + /* temporal key 1 (tk1) */ + u8 tk1[TKIP_TK_LENGTH]; + u8 txmickey[TKIP_MIC_KEY_LENGTH]; + u8 rxmickey[TKIP_MIC_KEY_LENGTH]; + u8 igtk_keyid[IGTK_KEY_ID_LENGTH]; + u8 ipn[IGTK_PKT_NUM_LENGTH]; + union keytype igtk[2]; + union keytype sk[1]; +}; + +/** + * @struct mac_ax_arp_ofld_info + * @brief mac_ax_arp_ofld_info + * + * @var mac_ax_arp_ofld_info::arp_en + * Please Place Description here. + * @var mac_ax_arp_ofld_info::arp_action + * Please Place Description here. + * @var mac_ax_arp_ofld_info::rsvd + * Please Place Description here. + * @var mac_ax_arp_ofld_info::arp_rsp_id + * Please Place Description here. + */ +struct mac_ax_arp_ofld_info { + u8 arp_en: 1; + u8 arp_action: 1; + u8 rsvd: 6; + u8 arp_rsp_id: 8; +}; + +/** + * @struct mac_ax_ndp_ofld_info + * @brief mac_ax_ndp_ofld_info + * + * @var mac_ax_ndp_ofld_info::ndp_en + * Please Place Description here. + * @var mac_ax_ndp_ofld_info::rsvd + * Please Place Description here. + * @var mac_ax_ndp_ofld_info::na_id + * Please Place Description here. + */ +struct mac_ax_ndp_ofld_info { + u8 ndp_en: 1; + u8 rsvd: 7; + u8 na_id: 8; +}; + +#define MAC_ADDRESS_LENGTH 6 +#define IPV6_ADDRESS_LENGTH 16 + +/** + * @struct mac_ax_ndp_info_parm_ + * @brief mac_ax_ndp_info_parm_ + * + * @var mac_ax_ndp_info_parm_::enable + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::checkremoveip + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::rsvd + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::numberoftargetip + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::targetlinkaddress + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::remoteipv6address + * Please Place Description here. + * @var mac_ax_ndp_info_parm_::targetip + * Please Place Description here. + */ +struct mac_ax_ndp_info_parm_ { + u8 enable: 1; + /* need to check sender ip or not */ + u8 checkremoveip: 1; + /* need to check sender ip or not */ + u8 rsvd: 6; + /* number of check ip which na query ip */ + u8 numberoftargetip; + /* maybe support change mac address !! */ + u8 targetlinkaddress[MAC_ADDRESS_LENGTH]; + /* just respond ip */ + u8 remoteipv6address[IPV6_ADDRESS_LENGTH]; + /* target ip */ + u8 targetip[2][IPV6_ADDRESS_LENGTH]; +}; + +/** + * @struct mac_ax_realwow_info + * @brief mac_ax_realwow_info + * + * @var mac_ax_realwow_info::realwow_en + * Please Place Description here. + * @var mac_ax_realwow_info::auto_wakeup + * Please Place Description here. + * @var mac_ax_realwow_info::rsvd0 + * Please Place Description here. + * @var mac_ax_realwow_info::keepalive_id + * Please Place Description here. + * @var mac_ax_realwow_info::wakeup_pattern_id + * Please Place Description here. + * @var mac_ax_realwow_info::ack_pattern_id + * Please Place Description here. + */ +struct mac_ax_realwow_info { + u8 realwow_en: 1; + u8 auto_wakeup: 1; + u8 rsvd0: 6; + u8 keepalive_id: 8; + u8 wakeup_pattern_id: 8; + u8 ack_pattern_id: 8; +}; + +/** + * @struct mac_ax_realwowv2_info_parm_ + * @brief mac_ax_realwowv2_info_parm_ + * + * @var mac_ax_realwowv2_info_parm_::interval + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::kapktsize + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::acklostlimit + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::ackpatternsize + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::wakeuppatternsize + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::rsvd + * Please Place Description here. + * @var mac_ax_realwowv2_info_parm_::wakeupsecnum + * Please Place Description here. + */ +struct mac_ax_realwowv2_info_parm_ { + u16 interval; /*unit : 1 ms */ + u16 kapktsize; + u16 acklostlimit; + u16 ackpatternsize; + u16 wakeuppatternsize; + u16 rsvd; + u32 wakeupsecnum; +}; + +/** + * @struct mac_ax_nlo_info + * @brief mac_ax_nlo_info + * + * @var mac_ax_nlo_info::nlo_en + * Please Place Description here. + * @var mac_ax_nlo_info::nlo_32k_en + * Please Place Description here. + * @var mac_ax_nlo_info::ignore_cipher_type + * Please Place Description here. + * @var mac_ax_nlo_info::rsvd + * Please Place Description here. + */ +struct mac_ax_nlo_info { + u8 nlo_en: 1; + u8 nlo_32k_en: 1; + u8 ignore_cipher_type: 1; + u8 rsvd: 5; +}; + +#define MAX_SUPPORT_NL_NUM 16 +#define MAX_PROBE_REQ_NUM 8 +#define SSID_MAX_LEN 32 + +/** + * @struct mac_ax_nlo_networklist_parm_ + * @brief mac_ax_nlo_networklist_parm_ + * + * @var mac_ax_nlo_networklist_parm_::numofentries + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::numofhiddenap + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::rsvd + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::patterncheck + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::rsvd1 + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::rsvd2 + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::ssidlen + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::chipertype + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::rsvd3 + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::locprobereq + * Please Place Description here. + * @var mac_ax_nlo_networklist_parm_::ssid + * Please Place Description here. + */ +struct mac_ax_nlo_networklist_parm_ { + u8 numofentries; + u8 numofhiddenap; + u8 rsvd[2]; + u32 patterncheck; + u32 rsvd1; + u32 rsvd2; + u8 ssidlen[MAX_SUPPORT_NL_NUM]; + u8 chipertype[MAX_SUPPORT_NL_NUM]; + u8 rsvd3[MAX_SUPPORT_NL_NUM]; + u8 locprobereq[MAX_PROBE_REQ_NUM]; + u8 ssid[MAX_SUPPORT_NL_NUM][SSID_MAX_LEN]; +}; + +/** + * @struct mac_ax_negative_pattern_info + * @brief mac_ax_negative_pattern_info + * + * @var mac_ax_negative_pattern_info::negative_pattern_en + * Please Place Description here. + * @var mac_ax_negative_pattern_info::rsvd + * Please Place Description here. + * @var mac_ax_negative_pattern_info::pattern_count + * Please Place Description here. + */ +struct mac_ax_negative_pattern_info { + u8 negative_pattern_en: 1; + u8 rsvd: 3; + u8 pattern_count: 4; +}; + +/** + * @struct mac_ax_dev2hst_gpio_info + * @brief mac_ax_dev2hst_gpio_info + * + * @var mac_ax_dev2hst_gpio_info::dev2hst_gpio_en + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::disable_inband + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_output_input + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_active + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::toggle_pulse + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::data_pin_wakeup + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_time_unit + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_num + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_dura + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_period + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_count + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::rsvd0 + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::customer_id + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::rsvd1 + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_en_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_duration_unit_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::rsvd2 + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::special_reason_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_duration_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_count_a + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_en_b + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_duration_unit_b + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop_b + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::rsvd3 + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::special_reason_b + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_duration_b + * Please Place Description here. + * @var mac_ax_dev2hst_gpio_info::gpio_pulse_count_b + * Please Place Description here. + */ +struct mac_ax_dev2hst_gpio_info { + /* dword0 */ + u32 dev2hst_gpio_en:1; + u32 disable_inband:1; + u32 gpio_output_input:1; + u32 gpio_active:1; + u32 toggle_pulse:1; + u32 data_pin_wakeup:1; + u32 gpio_pulse_nonstop:1; + u32 gpio_time_unit:1; + u32 gpio_num:8; + u32 gpio_pulse_dura:8; + u32 gpio_pulse_period:8; + /* dword1 */ + u32 gpio_pulse_count:8; + u32 rsvd0:24; + /* dword2 */ + u32 customer_id:8; + u32 rsvd1:24; + /* dword3 */ + u32 rsn_a_en:1; + u32 rsn_a_toggle_pulse:1; + u32 rsn_a_pulse_nonstop:1; + u32 rsn_a_time_unit:1; + u32 rsvd2:28; + /* dword4 */ + u32 rsn_a:8; + u32 rsn_a_pulse_duration:8; + u32 rsn_a_pulse_period:8; + u32 rsn_a_pulse_count:8; + /* dword5 */ + u32 rsn_b_en:1; + u32 rsn_b_toggle_pulse:1; + u32 rsn_b_pulse_nonstop:1; + u32 rsn_b_time_unit:1; + u32 rsvd3:28; + /* dword6 */ + u32 rsn_b:8; + u32 rsn_b_pulse_duration:8; + u32 rsn_b_pulse_period:8; + u32 rsn_b_pulse_count:8; + /* dword7 */ + u32 gpio_pulse_en_a:8; /*deprecated*/ + u32 gpio_duration_unit_a:8; /*deprecated*/ + u32 gpio_pulse_nonstop_a:8; /*deprecated*/ + u32 special_reason_a:8; /*deprecated*/ + u32 gpio_duration_a:8; /*deprecated*/ + u32 gpio_pulse_count_a:8; /*deprecated*/ + +}; + +/** + * @struct mac_ax_uphy_ctrl_info + * @brief mac_ax_uphy_ctrl_info + * + * @var mac_ax_uphy_ctrl_info::disable_uphy + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::handshake_mode + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::rsvd0 + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::rise_hst2dev_dis_uphy + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::uphy_dis_delay_unit + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::pdn_as_uphy_dis + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::pdn_to_enable_uphy + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::rsvd1 + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::hst2dev_gpio_num + * Please Place Description here. + * @var mac_ax_uphy_ctrl_info::uphy_dis_delay_count + * Please Place Description here. + */ +struct mac_ax_uphy_ctrl_info { + u8 disable_uphy: 1; + u8 handshake_mode: 3; + u8 rsvd0: 4; + u8 rise_hst2dev_dis_uphy: 1; + u8 uphy_dis_delay_unit: 1; + u8 pdn_as_uphy_dis: 1; + u8 pdn_to_enable_uphy: 1; + u8 rsvd1: 4; + u8 hst2dev_gpio_num: 8; + u8 uphy_dis_delay_count: 8; +}; + +/** + * @struct mac_ax_wowcam_upd_info + * @brief mac_ax_wowcam_upd_info + * + * @var mac_ax_wowcam_upd_info::r_w + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::idx + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::rsvd0 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::wkfm1 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::wkfm2 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::wkfm3 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::wkfm4 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::crc + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::rsvd1 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::negative_pattern_match + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::skip_mac_hdr + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::uc + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::mc + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::bc + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::rsvd2 + * Please Place Description here. + * @var mac_ax_wowcam_upd_info::valid + * Please Place Description here. + */ +struct mac_ax_wowcam_upd_info { + u8 r_w: 1; + u8 idx: 7; + u8 rsvd0[3]; + u32 wkfm1: 32; + u32 wkfm2: 32; + u32 wkfm3: 32; + u32 wkfm4: 32; + u16 crc: 16; + u8 rsvd1: 6; + u8 negative_pattern_match: 1; + u8 skip_mac_hdr: 1; + u8 uc: 1; + u8 mc: 1; + u8 bc: 1; + u8 rsvd2: 4; + u8 valid: 1; +}; + +/*--------------------Define SET/GET HW VALUE struct -------------------------*/ + +/** + * @struct mac_ax_sdio_info + * @brief mac_ax_sdio_info + * + * @var mac_ax_sdio_info::sdio_4byte + * Please Place Description here. + * @var mac_ax_sdio_info::tx_mode + * Please Place Description here. + * @var mac_ax_sdio_info::spec_ver + * Please Place Description here. + * @var mac_ax_sdio_info::block_size + * Please Place Description here. + * @var mac_ax_sdio_info::tx_seq + * Please Place Description here. + * @var mac_ax_sdio_info::tx_align_size + * Please Place Description here. + * @var mac_ax_sdio_info::rpwm_bak + * Please Place Description here. + */ +struct mac_ax_sdio_info { + enum mac_ax_sdio_4byte_mode sdio_4byte; + enum mac_ax_sdio_tx_mode tx_mode; + enum mac_ax_sdio_spec_ver spec_ver; + enum mac_ax_sdio_opn_mode opn_mode; + u16 block_size; + u8 tx_seq; + u16 tx_align_size; + u32 rpwm_bak; +}; + +/** + * @struct mac_ax_sdio_txagg_cfg + * @brief mac_ax_sdio_txagg_cfg + * + * @var mac_ax_sdio_txagg_cfg::en + * Please Place Description here. + * @var mac_ax_sdio_txagg_cfg::align_size + * Please Place Description here. + */ +struct mac_ax_sdio_txagg_cfg { + u8 en; + u16 align_size; +}; + +/** + * @struct mac_ax_usb_info + * @brief mac_ax_usb_info + * + * @var mac_ax_usb_info::ep5 + * Please Place Description here. + * @var mac_ax_usb_info::ep6 + * Please Place Description here. + * @var mac_ax_usb_info::ep10 + * Please Place Description here. + * @var mac_ax_usb_info::ep11 + * Please Place Description here. + * @var mac_ax_usb_info::ep12 + * Please Place Description here. + * @var mac_ax_usb_info::max_bulkout_wd_num + * Please Place Description here. + * @var mac_ax_usb_info::usb_mode + * Please Place Description here. + */ +struct mac_ax_usb_info { + u8 ep5; + u8 ep6; + u8 ep10; + u8 ep11; + u8 ep12; + u8 max_bulkout_wd_num; + enum mac_ax_use_mode usb_mode; +}; + +/** + * @struct mac_ax_pcie_info + * @brief mac_ax_pcie_info + * + * @var mac_ax_pcie_info::autok_total + * @var mac_ax_pcie_info::autok_2s_cnt + * Please Place Description here. + */ +struct mac_ax_pcie_info { + u32 autok_total; + u8 autok_2s_cnt; +}; + +struct mac_ax_flash_info { + u8 read_done; + u8 reading; + u32 read_addr; + u8 write_done; + u8 writing; + u32 write_addr; + u8 erasing; + u8 erase_done; + u32 erase_addr; + u8 *buf_addr; + mac_ax_mutex lock; +}; + +/** + * @struct mac_ax_fw_dbgcmd + * @brief mac_ax_fw_dbgcmd + * + * @var mac_ax_fw_dbgcmd::buf + * Please Place Description here. + * @var mac_ax_fw_dbgcmd::out_len + * Please Place Description here. + * @var mac_ax_fw_dbgcmd::used + * Please Place Description here. + * @var mac_ax_fw_dbgcmd::cmd_idle + * Please Place Description here. + * @var mac_ax_fw_dbgcmd::lock + * Please Place Description here. + */ +struct mac_ax_fw_dbgcmd { + char *buf; + u32 out_len; + u32 used; + u32 cmd_idle; + mac_ax_mutex lock; +}; + +/** + * @struct mac_ax_aval_page_cfg + * @brief mac_ax_aval_page_cfg + * + * @var mac_ax_aval_page_cfg::thold_wd + * Please Place Description here. + * @var mac_ax_aval_page_cfg::thold_wp + * Please Place Description here. + * @var mac_ax_aval_page_cfg::ch_dma + * Please Place Description here. + * @var mac_ax_aval_page_cfg::en + * Please Place Description here. + */ +struct mac_ax_aval_page_cfg { + u32 thold_wd; + u32 thold_wp; + u8 ch_dma; + u8 en; +}; + +/** + * @struct mac_ax_rx_agg_cfg + * @brief mac_ax_rx_agg_cfg + * + * @var mac_ax_rx_agg_cfg::mode + * Please Place Description here. + * @var mac_ax_rx_agg_cfg::thold + * Please Place Description here. + */ +struct mac_ax_rx_agg_cfg { + enum mac_ax_rx_agg_mode mode; + struct mac_ax_rx_agg_thold thold; +}; + +/** + * @struct mac_ax_usr_tx_rpt_cfg + * @brief mac_ax_usr_tx_rpt_cfg + * + * @var mac_ax_usr_tx_rpt_cfg::mode + * sel report mode + * @var mac_ax_usr_tx_rpt_cfg::rpt_start + * flag of first packet + * @var mac_ax_usr_tx_rpt_cfg::macid + * target macid + * @var mac_ax_usr_tx_rpt_cfg::rpt_period_us + * period of report, unit:us + */ +struct mac_ax_usr_tx_rpt_cfg { + enum mac_ax_usr_tx_rpt_mode mode; + u8 rpt_start; + u8 macid; + u8 band; + u8 port; + u32 rpt_period_us; +}; + +/** + * @struct mac_ax_ofld_cfg + * @brief disable ofld feature + * + * @var mac_ax_ofld_cfg::usr_edca_dis + * 1: disable; 0:enable + */ +struct mac_ax_ofld_cfg { + enum mac_ax_ofld_mode mode; + u8 usr_txop_be; + u16 usr_txop_be_val; +}; + +/** + * @struct mac_ax_ac_edca_param + * @brief mac_ax_ac_edca_param + * + * @var mac_ax_ac_edca_param::txop_32us + * Please Place Description here. + * @var mac_ax_ac_edca_param::ecw_max + * Please Place Description here. + * @var mac_ax_ac_edca_param::ecw_min + * Please Place Description here. + * @var mac_ax_ac_edca_param::aifs_us + * Please Place Description here. + */ +struct mac_ax_ac_edca_param { + u16 txop_32us; + u8 ecw_max; + u8 ecw_min; + u8 aifs_us; +}; + +/** + * @struct mac_ax_usr_edca_param + * @brief mac_ax_usr_edca_param + * + * @var mac_ax_usr_edca_param::idx + * Please Place Description here. + * @var mac_ax_usr_edca_param::enable + * Please Place Description here. + * @var mac_ax_usr_edca_param::band + * Please Place Description here. + * @var mac_ax_usr_edca_param::wmm + * Please Place Description here. + * @var mac_ax_usr_edca_param::ac + * Please Place Description here. + * @var mac_ax_usr_edca_param::aggressive + * Please Place Description here. + * @var mac_ax_usr_edca_param::moderate + * Please Place Description here. + */ +struct mac_ax_usr_edca_param { + enum mac_ax_cmac_usr_edca_idx idx; + u8 enable; + u8 band; + enum mac_ax_cmac_wmm_sel wmm; + enum mac_ax_cmac_ac_sel ac; + struct mac_ax_ac_edca_param aggressive; + struct mac_ax_ac_edca_param moderate; +}; + +/** + * @struct mac_ax_edca_param + * @brief mac_ax_edca_param + * + * @var mac_ax_edca_param::band + * Please Place Description here. + * @var mac_ax_edca_param::path + * Please Place Description here. + * @var mac_ax_edca_param::txop_32us + * Please Place Description here. + * @var mac_ax_edca_param::ecw_max + * Please Place Description here. + * @var mac_ax_edca_param::ecw_min + * Please Place Description here. + * @var mac_ax_edca_param::aifs_us + * Please Place Description here. + */ +struct mac_ax_edca_param { + u8 band; + enum mac_ax_cmac_path_sel path; + u16 txop_32us; + u8 ecw_max; + u8 ecw_min; + u8 aifs_us; +}; + +/** + * @struct mac_ax_muedca_param + * @brief mac_ax_muedca_param + * + * @var mac_ax_muedca_param::band + * Please Place Description here. + * @var mac_ax_muedca_param::ac + * Please Place Description here. + * @var mac_ax_muedca_param::muedca_timer_32us + * Please Place Description here. + * @var mac_ax_muedca_param::ecw_max + * Please Place Description here. + * @var mac_ax_muedca_param::ecw_min + * Please Place Description here. + * @var mac_ax_muedca_param::aifs_us + * Please Place Description here. + */ +struct mac_ax_muedca_param { + u8 band; + enum mac_ax_cmac_ac_sel ac; + u16 muedca_timer_32us; + u8 ecw_max; + u8 ecw_min; + u8 aifs_us; +}; + +/** + * @struct mac_ax_muedca_timer + * @brief mac_ax_muedca_timer + * + * @var mac_ax_muedca_timer::band + * Please Place Description here. + * @var mac_ax_muedca_timer::ac + * Please Place Description here. + * @var mac_ax_muedca_timer::muedca_timer_32us + * Please Place Description here. + */ +struct mac_ax_muedca_timer { + u8 band; + enum mac_ax_cmac_ac_sel ac; + u16 muedca_timer_32us; +}; + +/** + * @struct mac_ax_muedca_cfg + * @brief mac_ax_muedca_cfg + * + * @var mac_ax_muedca_cfg::band + * Please Place Description here. + * @var mac_ax_muedca_cfg::wmm_sel + * Please Place Description here. + * @var mac_ax_muedca_cfg::countdown_en + * Please Place Description here. + * @var mac_ax_muedca_cfg::tb_update_en + * Please Place Description here. + */ +struct mac_ax_muedca_cfg { + u8 band; + enum mac_ax_cmac_wmm_sel wmm_sel; + u8 countdown_en; + u8 tb_update_en; +}; + +/** + * @struct mac_ax_sch_tx_en_cfg + * @brief mac_ax_sch_tx_en_cfg + * + * @var mac_ax_sch_tx_en_cfg::band + * Please Place Description here. + * @var mac_ax_sch_tx_en_cfg::tx_en + * Please Place Description here. + * @var mac_ax_sch_tx_en_cfg::tx_en_mask + * Please Place Description here. + */ +struct mac_ax_sch_tx_en_cfg { + u8 band; + struct mac_ax_sch_tx_en tx_en; + struct mac_ax_sch_tx_en tx_en_mask; +}; + +struct mac_ax_tx_idle_poll_cfg { + u8 band; + enum mac_ax_tx_idle_poll_sel sel; +}; + +/** + * @struct mac_ax_lifetime_cfg + * @brief mac_ax_lifetime_cfg + * + * @var mac_ax_lifetime_cfg::band + * Please Place Description here. + * @var mac_ax_lifetime_cfg::en + * Please Place Description here. + * @var mac_ax_lifetime_cfg::val + * Please Place Description here. + */ +struct mac_ax_lifetime_cfg { + u8 band; + struct mac_ax_lifetime_en en; + struct mac_ax_lifetime_val val; +}; + +/** + * @struct mac_ax_tb_ppdu_ctrl + * @brief mac_ax_tb_ppdu_ctrl + * + * @var mac_ax_tb_ppdu_ctrl::band + * Please Place Description here. + * @var mac_ax_tb_ppdu_ctrl::pri_ac + * Please Place Description here. + * @var mac_ax_tb_ppdu_ctrl::be_dis + * Please Place Description here. + * @var mac_ax_tb_ppdu_ctrl::bk_dis + * Please Place Description here. + * @var mac_ax_tb_ppdu_ctrl::vi_dis + * Please Place Description here. + * @var mac_ax_tb_ppdu_ctrl::vo_dis + * Please Place Description here. + */ +struct mac_ax_tb_ppdu_ctrl { + u8 band; + enum mac_ax_cmac_ac_sel pri_ac; + u8 be_dis; + u8 bk_dis; + u8 vi_dis; + u8 vo_dis; +}; + +/** + * @struct macid_tx_bak + * @brief macid_tx_bak + * + * @var macid_tx_bak::sch_bak + * Please Place Description here. + * @var macid_tx_bak::ac_dis_bak + * Please Place Description here. + */ +struct macid_tx_bak { + struct mac_ax_sch_tx_en_cfg sch_bak; + struct mac_ax_tb_ppdu_ctrl ac_dis_bak; +}; + +/** + * @struct mac_ax_edcca_param + * @brief mac_ax_edcca_param + * + * @var mac_ax_edcca_param::band + * Please Place Description here. + * @var mac_ax_edcca_param::tb_check_en + * Please Place Description here. + * @var mac_ax_edcca_param::sifs_check_en + * Please Place Description here. + * @var mac_ax_edcca_param::ctn_check_en + * Please Place Description here. + * @var mac_ax_edcca_param::rsvd + * Please Place Description here. + * @var mac_ax_edcca_param::sel + * Please Place Description here. + */ +struct mac_ax_edcca_param { + u8 band:1; + u8 tb_check_en:1; + u8 sifs_check_en:1; + u8 ctn_check_en:1; + u8 rsvd:4; + enum mac_ax_edcca_sel sel; +}; + +/** + * @struct mac_ax_host_rpr_cfg + * @brief mac_ax_host_rpr_cfg + * + * @var mac_ax_host_rpr_cfg::agg + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::tmr + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::agg_def + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::tmr_def + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::rsvd + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::txok_en + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::rty_lmt_en + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::lft_drop_en + * Please Place Description here. + * @var mac_ax_host_rpr_cfg::macid_drop_en + * Please Place Description here. + */ +struct mac_ax_host_rpr_cfg { + u8 agg; + u8 tmr; + u8 agg_def:1; + u8 tmr_def:1; + u8 rsvd:5; + enum mac_ax_func_sw txok_en; + enum mac_ax_func_sw rty_lmt_en; + enum mac_ax_func_sw lft_drop_en; + enum mac_ax_func_sw macid_drop_en; +}; + +/** + * @struct mac_ax_macid_pause_cfg + * @brief mac_ax_macid_pause_cfg + * + * @var mac_ax_macid_pause_cfg::macid + * Please Place Description here. + * @var mac_ax_macid_pause_cfg::pause + * Please Place Description here. + */ +struct mac_ax_macid_pause_cfg { + u8 macid; + u8 pause; +}; + +/** + * @struct mac_ax_macid_pause_grp + * @brief mac_ax_macid_pause_grp + * + * @var mac_ax_macid_pause_grp::pause_grp + * Please Place Description here. + * @var mac_ax_macid_pause_grp::mask_grp + * Please Place Description here. + */ +struct mac_ax_macid_pause_grp { + u32 pause_grp[4]; + u32 mask_grp[4]; +}; + +/** + * @struct mac_ax_ampdu_cfg + * @brief mac_ax_ampdu_cfg + * + * @var mac_ax_ampdu_cfg::band + * Please Place Description here. + * @var mac_ax_ampdu_cfg::wdbk_mode + * Please Place Description here. + * @var mac_ax_ampdu_cfg::rty_bk_mode + * Please Place Description here. + * @var mac_ax_ampdu_cfg::max_agg_num + * Please Place Description here. + * @var mac_ax_ampdu_cfg::max_agg_time_32us + * Please Place Description here. + */ +struct mac_ax_ampdu_cfg { + u8 band; + enum mac_ax_wdbk_mode wdbk_mode; + enum mac_ax_rty_bk_mode rty_bk_mode; + u16 max_agg_num; + u8 max_agg_time_32us; +}; + +/** + * @struct mac_ax_ch_stat_cnt + * @brief mac_ax_ch_stat_cnt + * + * @var mac_ax_ch_stat_cnt::band + * Please Place Description here. + * @var mac_ax_ch_stat_cnt::busy_cnt + * Please Place Description here. + * @var mac_ax_ch_stat_cnt::idle_cnt + * Please Place Description here. + */ +struct mac_ax_ch_stat_cnt { + u8 band; + u32 busy_cnt; + u32 idle_cnt; +}; + +/** + * @struct mac_ax_ch_busy_cnt_cfg + * @brief mac_ax_ch_busy_cnt_cfg + * + * @var mac_ax_ch_busy_cnt_cfg::band + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_cfg::cnt_ctrl + * Please Place Description here. + * @var mac_ax_ch_busy_cnt_cfg::ref + * Please Place Description here. + */ +struct mac_ax_ch_busy_cnt_cfg { + u8 band; + enum mac_ax_ch_busy_cnt_ctrl cnt_ctrl; + struct mac_ax_ch_busy_cnt_ref ref; +}; + +/** + * @struct mac_ax_ss_wmm_tbl_ctrl + * @brief mac_ax_ss_wmm_tbl_ctrl + * + * @var mac_ax_ss_wmm_tbl_ctrl::wmm + * Please Place Description here. + * @var mac_ax_ss_wmm_tbl_ctrl::wmm_mapping + * Please Place Description here. + */ +struct mac_ax_ss_wmm_tbl_ctrl { + u8 wmm; + enum mac_ax_ss_wmm_tbl wmm_mapping; +}; + +/** + * @struct mac_ax_bt_block_tx + * @brief mac_ax_bt_block_tx + * + * @var mac_ax_bt_block_tx::band + * Please Place Description here. + * @var mac_ax_bt_block_tx::en + * Please Place Description here. + */ +struct mac_ax_block_tx { + u8 band; + u8 en; +}; + +/** + * @struct mac_ax_gt3_cfg + * @brief mac_ax_gt3_cfg + * + * @var mac_ax_gt3_cfg::count_en + * Please Place Description here. + * @var mac_ax_gt3_cfg::mode + * Please Place Description here. + * @var mac_ax_gt3_cfg::gt3_en + * Please Place Description here. + * @var mac_ax_gt3_cfg::sort_en + * Please Place Description here. + * @var mac_ax_gt3_cfg::timeout + * Please Place Description here. + */ +struct mac_ax_gt3_cfg { + u32 count_en:1; + u32 mode:1; /*0 = counter mode; 1 = timer mode"*/ + u32 gt3_en:1; /*HW clear when count down to zero in counter mode."*/ + u32 sort_en:1; + u32 timeout:28; +}; + +/** + * @struct mac_ax_rty_lmt + * @brief mac_ax_rty_lmt + * + * @var mac_ax_rty_lmt::tx_cnt + * Please Place Description here. + * @var mac_ax_rty_lmt::macid + * Please Place Description here. + */ +struct mac_ax_rty_lmt { + u32 tx_cnt; + u8 macid; +}; + +/** + * @struct mac_ax_cctl_rty_lmt_cfg + * @brief mac_ax_cctl_rty_lmt_cfg + * + * @var mac_ax_cctl_rty_lmt_cfg::macid + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::data_lmt_sel + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::data_lmt_val + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::rsvd0 + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::rts_lmt_sel + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::rts_lmt_val + * Please Place Description here. + * @var mac_ax_cctl_rty_lmt_cfg::rsvd1 + * Please Place Description here. + */ +struct mac_ax_cctl_rty_lmt_cfg { + u8 macid; + u8 data_lmt_sel:1; + u8 data_lmt_val:6; + u8 rsvd0:1; + u8 rts_lmt_sel:1; + u8 rts_lmt_val:4; + u8 rsvd1:3; +}; + +/** + * @struct mac_ax_cr_rty_lmt_cfg + * @brief mac_ax_cr_rty_lmt_cfg + * + * @var mac_ax_cr_rty_lmt_cfg::long_tx_cnt_lmt + * Please Place Description here. + * @var mac_ax_cr_rty_lmt_cfg::short_tx_cnt_lmt + * Please Place Description here. + * @var mac_ax_cr_rty_lmt_cfg::band + * Please Place Description here. + */ +struct mac_ax_cr_rty_lmt_cfg { + u16 long_tx_cnt_lmt:6; /*CR: long rty*/ + u16 short_tx_cnt_lmt:6; /*CR: short rty*/ + enum mac_ax_band band; +}; + +/** + * @struct mac_ax_rrsr_cfg + * @brief mac_ax_rrsr_cfg + * + * @var mac_ax_rrsr_cfg::rrsr_rate_en + * Please Place Description here. + * @var mac_ax_rrsr_cfg::rsc + * Please Place Description here. + * @var mac_ax_rrsr_cfg::doppler_en + * Please Place Description here. + * @var mac_ax_rrsr_cfg::dcm_en + * Please Place Description here. + * @var mac_ax_rrsr_cfg::ref_rate_sel + * Please Place Description here. + * @var mac_ax_rrsr_cfg::ref_rate + * Please Place Description here. + * @var mac_ax_rrsr_cfg::cck_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::rsvd + * Please Place Description here. + * @var mac_ax_rrsr_cfg::ofdm_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::ht_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::vht_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::he_cfg + * Please Place Description here. + */ +struct mac_ax_rrsr_cfg { + u32 rrsr_rate_en:4; + u32 rsc:2; + u32 doppler_en:1; + u32 dcm_en:1; + u32 ref_rate_sel:1; + u32 ref_rate:9; + u32 cck_cfg:4; + u32 rsvd:10; + + u32 ofdm_cfg:8; + u32 ht_cfg:8; + u32 vht_cfg:8; + u32 he_cfg:8; + u8 band; +}; + +/** + * @struct mac_ax_cts_rrsr_cfg + * @brief mac_ax_cts_rrsr_cfg + * + * @var mac_ax_rrsr_cfg::cts_rrsr_rsc + * Please Place Description here. + * @var mac_ax_rrsr_cfg::cts_rrsr_opt + * Please Place Description here. + * @var mac_ax_rrsr_cfg::cts_rrsr_cck_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::cts_rrsr_ofdm_cfg + * Please Place Description here. + * @var mac_ax_rrsr_cfg::rsvd + * Please Place Description here. + */ +struct mac_ax_cts_rrsr_cfg { + u32 cts_rrsr_rsc:2; + u32 cts_rrsr_opt:1; + u32 cts_rrsr_cck_cfg:4; + u32 cts_rrsr_ofdm_cfg:8; + u32 rsvd:17; + u8 band; +}; + +/** + * @struct mac_ax_ss_quota_mode_ctrl + * @brief mac_ax_ss_quota_mode_ctrl + * + * @var mac_ax_ss_quota_mode_ctrl::wmm + * Please Place Description here. + * @var mac_ax_ss_quota_mode_ctrl::mode + * Please Place Description here. + */ +struct mac_ax_ss_quota_mode_ctrl { + enum mac_ax_ss_wmm wmm; + enum mac_ax_ss_quota_mode mode; +}; + +/** + * @struct mac_ax_ss_quota_setting + * @brief mac_ax_ss_quota_setting + * + * @var mac_ax_ss_quota_setting::macid + * Please Place Description here. + * @var mac_ax_ss_quota_setting::ac_type + * Please Place Description here. + * @var mac_ax_ss_quota_setting::val + * Please Place Description here. + * @var mac_ax_ss_quota_setting::ul_dl + * Please Place Description here. + */ +struct mac_ax_ss_quota_setting { + u8 macid; + u8 ac_type; + u8 val; + enum mac_ax_issue_uldl_type ul_dl; +}; + +/** + * @struct mac_ax_bt_polt_cnt + * @brief mac_ax_bt_polt_cnt + * + * @var mac_ax_bt_polt_cnt::band + * Please Place Description here. + * @var mac_ax_bt_polt_cnt::cnt + * Please Place Description here. + */ +struct mac_ax_bt_polt_cnt { + u8 band; + u16 cnt; +}; + +/** + * @struct mac_ax_prebkf_setting + * @brief mac_ax_prebkf_setting + * + * @var mac_ax_prebkf_setting::band + * Please Place Description here. + * @var mac_ax_prebkf_setting::val + * Please Place Description here. + */ +struct mac_ax_prebkf_setting { + u8 band; + u8 val; +}; + +/*--------------------Define SRAM FIFO ---------------------------------------*/ + +/** + * @struct mac_ax_bacam_info + * @brief mac_ax_bacam_info + * + * @var mac_ax_bacam_info::valid + * Please Place Description here. + * @var mac_ax_bacam_info::init_req + * Please Place Description here. + * @var mac_ax_bacam_info::entry_idx + * Tha var is only for 8852A. + * @var mac_ax_bacam_info::tid + * Please Place Description here. + * @var mac_ax_bacam_info::macid + * Please Place Description here. + * @var mac_ax_bacam_info::bmap_size + * Please Place Description here. + * @var mac_ax_bacam_info::ssn + * Please Place Description here. + * @var mac_ax_bacam_info::uid_value + * The var is for 8852C. + * @var mac_ax_bacam_info::std_entry_en + * The var is for 8852C. + * @var mac_ax_bacam_info::band_sel + * The var is for 8852C. + * @var mac_ax_bacam_info::entry_idx_v1 + * The var is for 8852C. + */ +struct mac_ax_bacam_info { + u32 valid: 1; + u32 init_req: 1; + u32 entry_idx: 2; + u32 tid: 4; + u32 macid: 8; + u32 bmap_size: 4; + u32 ssn: 12; + u32 uid_value: 8; + u32 std_entry_en: 1; + u32 band_sel: 1; + u32 rsvd: 18; + u32 entry_idx_v1: 4; +}; + +/** + * @struct mac_ax_shcut_mhdr + * @brief mac_ax_shcut_mhdr + * + * @var mac_ax_shcut_mhdr::mac_header_length + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword0 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword1 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword2 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword3 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword4 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword5 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword6 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword7 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword8 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword9 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword10 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword11 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword12 + * Please Place Description here. + * @var mac_ax_shcut_mhdr::dword13 + * Please Place Description here. + */ +struct mac_ax_shcut_mhdr {/*need to revise note by kkbomb 0204*/ +// dword 0 + u32 mac_header_length:8; + u32 dword0:24; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; + u32 dword12; + u32 dword13; +}; + +/** + * @struct mac_ax_fwstatus_payload + * @brief mac_ax_fwstatus_payload + * + * @var mac_ax_fwstatus_payload::dword0 + * Please Place Description here. + * @var mac_ax_fwstatus_payload::dword1 + * Please Place Description here. + */ +struct mac_ax_fwstatus_payload { + u32 dword0; + u32 dword1; +}; + +/** + * @struct mac_ax_ie_cam_cmd_info + * @brief mac_ax_ie_cam_cmd_info + * + * @var mac_ax_ie_cam_cmd_info::en + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::band + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::port + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::hit_en + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::miss_en + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::rst + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::hit_sel + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::miss_sel + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::rsvd0 + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::num + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::rsvd1 + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::buf + * Please Place Description here. + * @var mac_ax_ie_cam_cmd_info::buf_len + * Please Place Description here. + */ +struct mac_ax_ie_cam_cmd_info { + u8 en:1; + u8 band:1; + u8 port:3; + u8 hit_en:1; + u8 miss_en:1; + u8 rst:1; + u8 hit_sel:2; + u8 miss_sel:2; + u8 rsvd0:4; + u8 num:5; + u8 rsvd1:3; + u8 *buf; + u32 buf_len; +}; + +/** + * @struct mac_ax_addr_cam_info + * @brief mac_ax_addr_cam_info + * + * @var mac_ax_addr_cam_info::addr_cam_idx + * Please Place Description here. + * @var mac_ax_addr_cam_info::offset + * Please Place Description here. + * @var mac_ax_addr_cam_info::len + * Please Place Description here. + * @var mac_ax_addr_cam_info::valid + * Please Place Description here. + * @var mac_ax_addr_cam_info::net_type + * Please Place Description here. + * @var mac_ax_addr_cam_info::bcn_hit_cond + * Please Place Description here. + * @var mac_ax_addr_cam_info::hit_rule + * Please Place Description here. + * @var mac_ax_addr_cam_info::bb_sel + * Please Place Description here. + * @var mac_ax_addr_cam_info::addr_mask + * Please Place Description here. + * @var mac_ax_addr_cam_info::mask_sel + * Please Place Description here. + * @var mac_ax_addr_cam_info::bssid_cam_idx + * Please Place Description here. + * @var mac_ax_addr_cam_info::is_mul_ent + * Please Place Description here. + * @var mac_ax_addr_cam_info::sma + * Please Place Description here. + * @var mac_ax_addr_cam_info::tma + * Please Place Description here. + * @var mac_ax_addr_cam_info::macid + * Please Place Description here. + * @var mac_ax_addr_cam_info::port_int + * Please Place Description here. + * @var mac_ax_addr_cam_info::tsf_sync + * Please Place Description here. + * @var mac_ax_addr_cam_info::tf_trs + * Please Place Description here. + * @var mac_ax_addr_cam_info::lsig_txop + * Please Place Description here. + * @var mac_ax_addr_cam_info::tgt_ind + * Please Place Description here. + * @var mac_ax_addr_cam_info::frm_tgt_ind + * Please Place Description here. + * @var mac_ax_addr_cam_info::aid12 + * Please Place Description here. + * @var mac_ax_addr_cam_info::wol_pattern + * Please Place Description here. + * @var mac_ax_addr_cam_info::wol_uc + * Please Place Description here. + * @var mac_ax_addr_cam_info::wol_magic + * Please Place Description here. + * @var mac_ax_addr_cam_info::wapi + * Please Place Description here. + * @var mac_ax_addr_cam_info::sec_ent_mode + * Please Place Description here. + * @var mac_ax_addr_cam_info::sec_ent_keyid + * Please Place Description here. + * @var mac_ax_addr_cam_info::sec_ent_valid + * Please Place Description here. + * @var mac_ax_addr_cam_info::sec_ent + * Please Place Description here. + */ +struct mac_ax_addr_cam_info { + u8 addr_cam_idx; /* Addr cam entry index */ + u8 offset; /* Offset */ + u8 len; /* Length */ + u8 valid : 1; + u8 net_type : 2; + u8 bcn_hit_cond : 2; + u8 hit_rule : 2; + u8 bb_sel : 1; + u8 addr_mask : 6; + u8 mask_sel : 2; + u8 bssid_cam_idx : 6; + u8 is_mul_ent : 1; + u8 sma[6]; + u8 tma[6]; + u8 macid; + u8 port_int: 3; + u8 tsf_sync: 3; + u8 tf_trs: 1; + u8 lsig_txop: 1; + u8 tgt_ind: 3; + u8 frm_tgt_ind: 3; + u16 aid12: 12; + u8 wol_pattern: 1; + u8 wol_uc: 1; + u8 wol_magic: 1; + u8 wapi: 1; + u8 sec_ent_mode: 2; + u8 sec_ent_keyid[7]; + u8 sec_ent_valid; + u8 sec_ent[7]; +}; + +/** + * @struct mac_ax_bssid_cam_info + * @brief mac_ax_bssid_cam_info + * + * @var mac_ax_bssid_cam_info::bssid_cam_idx + * Please Place Description here. + * @var mac_ax_bssid_cam_info::offset + * Please Place Description here. + * @var mac_ax_bssid_cam_info::len + * Please Place Description here. + * @var mac_ax_bssid_cam_info::valid + * Please Place Description here. + * @var mac_ax_bssid_cam_info::bb_sel + * Please Place Description here. + * @var mac_ax_bssid_cam_info::bss_color + * Please Place Description here. + * @var mac_ax_bssid_cam_info::bssid + * Please Place Description here. + */ +struct mac_ax_bssid_cam_info { + u8 bssid_cam_idx; /* BSSID cam entry index */ + u8 offset; /* Offset */ + u8 len; /* Length */ + u8 valid : 1; + u8 bb_sel : 1; + u8 addr_mask : 6; + u8 bss_color : 7; + u8 bssid[6]; +}; + +/** + * @struct mac_ax_sec_cam_info + * @brief mac_ax_sec_cam_info + * + * @var mac_ax_sec_cam_info::sec_cam_idx + * Please Place Description here. + * @var mac_ax_sec_cam_info::offset + * Please Place Description here. + * @var mac_ax_sec_cam_info::len + * Please Place Description here. + * @var mac_ax_sec_cam_info::type + * Please Place Description here. + * @var mac_ax_sec_cam_info::ext_key + * Please Place Description here. + * @var mac_ax_sec_cam_info::spp_mode + * Please Place Description here. + * @var mac_ax_sec_cam_info::key + * Please Place Description here. + */ +struct mac_ax_sec_cam_info { + u8 sec_cam_idx; /* Security cam entry index */ + u8 offset; /* Offset */ + u8 len; /* Length */ + u8 type : 4; + u8 ext_key : 1; + u8 spp_mode : 1; + u32 key[4]; +}; + +/** + * @struct mac_ax_macaddr + * @brief mac_ax_macaddr + * + * @var mac_ax_macaddr::macaddr + * Please Place Description here. + */ +struct mac_ax_macaddr { + u8 macaddr[6]; +}; + +/** + * @struct mac_ax_sta_init_info + * @brief mac_ax_sta_init_info + * + * @var mac_ax_sta_init_info::macid + * Please Place Description here. + * @var mac_ax_sta_init_info::opmode + * Please Place Description here. + * @var mac_ax_sta_init_info::band + * Please Place Description here. + * @var mac_ax_sta_init_info::wmm + * Please Place Description here. + * @var mac_ax_sta_init_info::trigger + * Please Place Description here. + * @var mac_ax_sta_init_info::is_hesta + * Please Place Description here. + * @var mac_ax_sta_init_info::dl_bw + * Please Place Description here. + * @var mac_ax_sta_init_info::tf_mac_padding + * Please Place Description here. + * @var mac_ax_sta_init_info::dl_t_pe + * Please Place Description here. + * @var mac_ax_sta_init_info::port_id + * Please Place Description here. + * @var mac_ax_sta_init_info::net_type + * Please Place Description here. + * @var mac_ax_sta_init_info::wifi_role + * Please Place Description here. + * @var mac_ax_sta_init_info::self_role + * Please Place Description here. + */ +struct mac_ax_sta_init_info { + u8 macid; + u8 opmode:1; + u8 band:1; + u8 wmm:2; + u8 trigger:1; + u8 is_hesta: 1; + u8 dl_bw: 2; + u8 tf_mac_padding:2; + u8 dl_t_pe:3; + u8 port_id:3; + u8 net_type:2; + u8 wifi_role:4; + u8 self_role:2; +}; + +/** + * @struct mac_ax_fwrole_maintain + * @brief mac_ax_fwrole_maintain + * + * @var mac_ax_fwrole_maintain::macid + * Please Place Description here. + * @var mac_ax_fwrole_maintain::self_role + * Please Place Description here. + * @var mac_ax_fwrole_maintain::upd_mode + * Please Place Description here. + * @var mac_ax_fwrole_maintain::wifi_role + * Please Place Description here. + */ +struct mac_ax_fwrole_maintain { + u8 macid; + u8 self_role : 2; + u8 upd_mode : 3; + u8 wifi_role : 4; +}; + +/** + * @struct mac_ax_cctl_info + * @brief mac_ax_cctl_info + * + * @var mac_ax_cctl_info::datarate + * Please Place Description here. + * @var mac_ax_cctl_info::force_txop + * Please Place Description here. + * @var mac_ax_cctl_info::data_bw + * Please Place Description here. + * @var mac_ax_cctl_info::data_gi_ltf + * Please Place Description here. + * @var mac_ax_cctl_info::darf_tc_index + * Please Place Description here. + * @var mac_ax_cctl_info::arfr_ctrl + * Please Place Description here. + * @var mac_ax_cctl_info::acq_rpt_en + * Please Place Description here. + * @var mac_ax_cctl_info::mgq_rpt_en + * Please Place Description here. + * @var mac_ax_cctl_info::ulq_rpt_en + * Please Place Description here. + * @var mac_ax_cctl_info::twtq_rpt_en + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd0 + * Please Place Description here. + * @var mac_ax_cctl_info::disrtsfb + * Please Place Description here. + * @var mac_ax_cctl_info::disdatafb + * Please Place Description here. + * @var mac_ax_cctl_info::tryrate + * Please Place Description here. + * @var mac_ax_cctl_info::ampdu_density + * Please Place Description here. + * @var mac_ax_cctl_info::data_rty_lowest_rate + * Please Place Description here. + * @var mac_ax_cctl_info::ampdu_time_sel + * Please Place Description here. + * @var mac_ax_cctl_info::ampdu_len_sel + * Please Place Description here. + * @var mac_ax_cctl_info::rts_txcnt_lmt_sel + * Please Place Description here. + * @var mac_ax_cctl_info::rts_txcnt_lmt + * Please Place Description here. + * @var mac_ax_cctl_info::rtsrate + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd1 + * Please Place Description here. + * @var mac_ax_cctl_info::vcs_stbc + * Please Place Description here. + * @var mac_ax_cctl_info::rts_rty_lowest_rate + * Please Place Description here. + * @var mac_ax_cctl_info::data_tx_cnt_lmt + * Please Place Description here. + * @var mac_ax_cctl_info::data_txcnt_lmt_sel + * Please Place Description here. + * @var mac_ax_cctl_info::max_agg_num_sel + * Please Place Description here. + * @var mac_ax_cctl_info::rts_en + * Please Place Description here. + * @var mac_ax_cctl_info::cts2self_en + * Please Place Description here. + * @var mac_ax_cctl_info::cca_rts + * Please Place Description here. + * @var mac_ax_cctl_info::hw_rts_en + * Please Place Description here. + * @var mac_ax_cctl_info::rts_drop_data_mode + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd2 + * Please Place Description here. + * @var mac_ax_cctl_info::ampdu_max_len + * Please Place Description here. + * @var mac_ax_cctl_info::ul_mu_dis + * Please Place Description here. + * @var mac_ax_cctl_info::ampdu_max_time + * Please Place Description here. + * @var mac_ax_cctl_info::max_agg_num + * Please Place Description here. + * @var mac_ax_cctl_info::ba_bmap + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd3 + * Please Place Description here. + * @var mac_ax_cctl_info::vo_lftime_sel + * Please Place Description here. + * @var mac_ax_cctl_info::vi_lftime_sel + * Please Place Description here. + * @var mac_ax_cctl_info::be_lftime_sel + * Please Place Description here. + * @var mac_ax_cctl_info::bk_lftime_sel + * Please Place Description here. + * @var mac_ax_cctl_info::sectype + * Please Place Description here. + * @var mac_ax_cctl_info::multi_port_id + * Please Place Description here. + * @var mac_ax_cctl_info::bmc + * Please Place Description here. + * @var mac_ax_cctl_info::mbssid + * Please Place Description here. + * @var mac_ax_cctl_info::navusehdr + * Please Place Description here. + * @var mac_ax_cctl_info::txpwr_mode + * Please Place Description here. + * @var mac_ax_cctl_info::data_dcm + * Please Place Description here. + * @var mac_ax_cctl_info::data_er + * Please Place Description here. + * @var mac_ax_cctl_info::data_ldpc + * Please Place Description here. + * @var mac_ax_cctl_info::data_stbc + * Please Place Description here. + * @var mac_ax_cctl_info::a_ctrl_bqr + * Please Place Description here. + * @var mac_ax_cctl_info::a_ctrl_uph + * Please Place Description here. + * @var mac_ax_cctl_info::a_ctrl_bsr + * Please Place Description here. + * @var mac_ax_cctl_info::a_ctrl_cas + * Please Place Description here. + * @var mac_ax_cctl_info::data_bw_er + * Please Place Description here. + * @var mac_ax_cctl_info::lsig_txop_en + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd4 + * Please Place Description here. + * @var mac_ax_cctl_info::ctrl_cnt_vld + * Please Place Description here. + * @var mac_ax_cctl_info::ctrl_cnt + * Please Place Description here. + * @var mac_ax_cctl_info::resp_ref_rate + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd5 + * Please Place Description here. + * @var mac_ax_cctl_info::all_ack_support + * Please Place Description here. + * @var mac_ax_cctl_info::bsr_queue_size_format + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd6 + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd7 + * Please Place Description here. + * @var mac_ax_cctl_info::ntx_path_en + * Please Place Description here. + * @var mac_ax_cctl_info::path_map_a + * Please Place Description here. + * @var mac_ax_cctl_info::path_map_b + * Please Place Description here. + * @var mac_ax_cctl_info::path_map_c + * Please Place Description here. + * @var mac_ax_cctl_info::path_map_d + * Please Place Description here. + * @var mac_ax_cctl_info::antsel_a + * Please Place Description here. + * @var mac_ax_cctl_info::antsel_b + * Please Place Description here. + * @var mac_ax_cctl_info::antsel_c + * Please Place Description here. + * @var mac_ax_cctl_info::antsel_d + * Please Place Description here. + * @var mac_ax_cctl_info::addr_cam_index + * Please Place Description here. + * @var mac_ax_cctl_info::paid + * Please Place Description here. + * @var mac_ax_cctl_info::uldl + * Please Place Description here. + * @var mac_ax_cctl_info::doppler_ctrl + * Please Place Description here. + * @var mac_ax_cctl_info::nominal_pkt_padding + * Please Place Description here. + * @var mac_ax_cctl_info::nominal_pkt_padding40 + * Please Place Description here. + * @var mac_ax_cctl_info::txpwr_tolerence + * Please Place Description here. + * @var mac_ax_cctl_info::rsvd9 + * Please Place Description here. + * @var mac_ax_cctl_info::nominal_pkt_padding80 + * Please Place Description here. + * @var mac_ax_cctl_info::nc + * Please Place Description here. + * @var mac_ax_cctl_info::nr + * Please Place Description here. + * @var mac_ax_cctl_info::ng + * Please Place Description here. + * @var mac_ax_cctl_info::cb + * Please Place Description here. + * @var mac_ax_cctl_info::cs + * Please Place Description here. + * @var mac_ax_cctl_info::csi_txbf_en + * Please Place Description here. + * @var mac_ax_cctl_info::csi_stbc_en + * Please Place Description here. + * @var mac_ax_cctl_info::csi_ldpc_en + * Please Place Description here. + * @var mac_ax_cctl_info::csi_para_en + * Please Place Description here. + * @var mac_ax_cctl_info::csi_fix_rate + * Please Place Description here. + * @var mac_ax_cctl_info::csi_gi_ltf + * Please Place Description here. + * @var mac_ax_cctl_info::nominal_pkt_padding160 + * Please Place Description here. + * @var mac_ax_cctl_info::csi_bw + * Please Place Description here. + */ +struct mac_ax_cctl_info { + /* dword 0 */ + u32 datarate:9; + u32 force_txop:1; + u32 data_bw:2; + u32 data_gi_ltf:3; + u32 darf_tc_index:1; + u32 arfr_ctrl:4; + u32 acq_rpt_en:1; + u32 mgq_rpt_en:1; + u32 ulq_rpt_en:1; + u32 twtq_rpt_en:1; + u32 rsvd0:1; + u32 disrtsfb:1; + u32 disdatafb:1; + u32 tryrate:1; + u32 ampdu_density:4; + /* dword 1 */ + u32 data_rty_lowest_rate:9; + u32 ampdu_time_sel:1; + u32 ampdu_len_sel:1; + u32 rts_txcnt_lmt_sel:1; + u32 rts_txcnt_lmt:4; + u32 rtsrate:9; + u32 rsvd1:2; + u32 vcs_stbc:1; + u32 rts_rty_lowest_rate:4; + /* dword 2 */ + u32 data_tx_cnt_lmt:6; + u32 data_txcnt_lmt_sel:1; + u32 max_agg_num_sel:1; + u32 rts_en:1; + u32 cts2self_en:1; + u32 cca_rts:2; + u32 hw_rts_en:1; + u32 rts_drop_data_mode:2; + u32 rsvd2:1; + u32 ampdu_max_len:11; + u32 ul_mu_dis:1; + u32 ampdu_max_time:4; + /* dword 3 */ + u32 max_agg_num:8; + u32 ba_bmap:2; + u32 rsvd3:6; + u32 vo_lftime_sel:3; + u32 vi_lftime_sel:3; + u32 be_lftime_sel:3; + u32 bk_lftime_sel:3; + u32 sectype:4; + /* dword 4 */ + u32 multi_port_id:3; + u32 bmc:1; + u32 mbssid:4; + u32 navusehdr:1; + u32 txpwr_mode:3; + u32 data_dcm:1; + u32 data_er:1; + u32 data_ldpc:1; + u32 data_stbc:1; + u32 a_ctrl_bqr:1; + u32 a_ctrl_uph:1; + u32 a_ctrl_bsr:1; + u32 a_ctrl_cas:1; + u32 data_bw_er:1; + u32 lsig_txop_en:1; + u32 rsvd4:5; + u32 ctrl_cnt_vld:1; + u32 ctrl_cnt:4; + /* dword 5 */ + u32 resp_ref_rate:9; + u32 rsvd5:3; + u32 all_ack_support:1; + u32 bsr_queue_size_format:1; + u32 rsvd6:1; + u32 rsvd7:1; + u32 ntx_path_en:4; + u32 path_map_a:2; + u32 path_map_b:2; + u32 path_map_c:2; + u32 path_map_d:2; + u32 antsel_a:1; + u32 antsel_b:1; + u32 antsel_c:1; + u32 antsel_d:1; + /* dword 6 */ + u32 addr_cam_index:8; + u32 paid:9; + u32 uldl:1; + u32 doppler_ctrl:2; + u32 nominal_pkt_padding:2; + u32 nominal_pkt_padding40:2; + u32 txpwr_tolerence:4; + u32 rsvd9:2; + u32 nominal_pkt_padding80:2; + /* dword 7 */ + u32 nc:3; + u32 nr:3; + u32 ng:2; + u32 cb:2; + u32 cs:2; + u32 csi_txbf_en:1; + u32 csi_stbc_en:1; + u32 csi_ldpc_en:1; + u32 csi_para_en:1; + u32 csi_fix_rate:9; + u32 csi_gi_ltf:3; + u32 nominal_pkt_padding160:2; + u32 csi_bw:2; +}; + +/** + * @struct mac_ax_dctl_info + * @brief mac_ax_dctl_info + * + * @var mac_ax_dctl_info::qos_field_h + * Please Place Description here. + * @var mac_ax_dctl_info::hw_exseq_macid + * Please Place Description here. + * @var mac_ax_dctl_info::qos_field_h_en + * Please Place Description here. + * @var mac_ax_dctl_info::aes_iv_l + * Please Place Description here. + * @var mac_ax_dctl_info::aes_iv_h + * Please Place Description here. + * @var mac_ax_dctl_info::seq0 + * Please Place Description here. + * @var mac_ax_dctl_info::seq1 + * Please Place Description here. + * @var mac_ax_dctl_info::amsdu_max_length + * Please Place Description here. + * @var mac_ax_dctl_info::sta_amsdu_en + * Please Place Description here. + * @var mac_ax_dctl_info::chksum_offload_en + * Please Place Description here. + * @var mac_ax_dctl_info::with_llc + * Please Place Description here. + * @var mac_ax_dctl_info::rsvd0 + * Please Place Description here. + * @var mac_ax_dctl_info::sec_hw_enc + * Please Place Description here. + * @var mac_ax_dctl_info::seq2 + * Please Place Description here. + * @var mac_ax_dctl_info::seq3 + * Please Place Description here. + * @var mac_ax_dctl_info::sec_cam_idx + * Please Place Description here. + */ +struct mac_ax_dctl_info { + /* dword 0 */ + u32 qos_field_h:8; + u32 hw_exseq_macid:7; + u32 qos_field_h_en:1; + u32 aes_iv_l:16; + /* dword 1 */ + u32 aes_iv_h:32; + /* dword 2 */ + u32 seq0:12; + u32 seq1:12; + u32 amsdu_max_length:3; + u32 sta_amsdu_en:1; + u32 chksum_offload_en:1; + u32 with_llc:1; + u32 rsvd0:1; + u32 sec_hw_enc:1; + /* dword 3 */ + u32 seq2:12; + u32 seq3:12; + u32 sec_cam_idx:8; +}; + +/** + * struct mac_ax_role_info - role information + * @macid: MAC ID. + * @band: Band selection, band0 or band1. + * @wmm: WMM selection, wmm0 ow wmm1. + * There are four sets about band and wmm, + * band0+wmm0, band0+wmm1, band1+wmm0,band1+wmm1. + */ + +/** + * @struct mac_ax_role_info + * @brief mac_ax_role_info + * + * @var mac_ax_role_info::self_role + * Please Place Description here. + * @var mac_ax_role_info::wifi_role + * Please Place Description here. + * @var mac_ax_role_info::net_type + * Please Place Description here. + * @var mac_ax_role_info::upd_mode + * Please Place Description here. + * @var mac_ax_role_info::opmode + * Please Place Description here. + * @var mac_ax_role_info::band + * Please Place Description here. + * @var mac_ax_role_info::port + * Please Place Description here. + * @var mac_ax_role_info::macid + * Please Place Description here. + * @var mac_ax_role_info::wmm + * Please Place Description here. + * @var mac_ax_role_info::self_mac + * Please Place Description here. + * @var mac_ax_role_info::target_mac + * Please Place Description here. + * @var mac_ax_role_info::bssid + * Please Place Description here. + * @var mac_ax_role_info::bss_color + * Please Place Description here. + * @var mac_ax_role_info::bcn_hit_cond + * Please Place Description here. + * @var mac_ax_role_info::hit_rule + * Please Place Description here. + * @var mac_ax_role_info::is_mul_ent + * Please Place Description here. + * @var mac_ax_role_info::tsf_sync + * Please Place Description here. + * @var mac_ax_role_info::trigger + * Please Place Description here. + * @var mac_ax_role_info::lsig_txop + * Please Place Description here. + * @var mac_ax_role_info::tgt_ind + * Please Place Description here. + * @var mac_ax_role_info::frm_tgt_ind + * Please Place Description here. + * @var mac_ax_role_info::wol_pattern + * Please Place Description here. + * @var mac_ax_role_info::wol_uc + * Please Place Description here. + * @var mac_ax_role_info::wol_magic + * Please Place Description here. + * @var mac_ax_role_info::wapi + * Please Place Description here. + * @var mac_ax_role_info::sec_ent_mode + * Please Place Description here. + * @var mac_ax_role_info::is_hesta + * Please Place Description here. + * @var mac_ax_role_info::dl_bw + * Please Place Description here. + * @var mac_ax_role_info::tf_mac_padding + * Please Place Description here. + * @var mac_ax_role_info::dl_t_pe + * Please Place Description here. + * @var mac_ax_role_info::aid + * Please Place Description here. + * @var mac_ax_role_info::a_info + * Please Place Description here. + * @var mac_ax_role_info::b_info + * Please Place Description here. + * @var mac_ax_role_info::s_info + * Please Place Description here. + * @var mac_ax_role_info::c_info + * Please Place Description here. + */ +struct mac_ax_role_info { + enum mac_ax_self_role self_role; + enum mac_ax_wifi_role wifi_role; + enum mac_ax_net_type net_type; + enum mac_ax_upd_mode upd_mode; + enum mac_ax_opmode opmode; + enum mac_ax_band band; + enum mac_ax_port port; + enum mac_ax_addr_msk_sel mask_sel; + enum mac_ax_addr_msk addr_mask; + u8 macid; + u8 wmm:2; + u8 self_mac[6]; + u8 target_mac[6]; + u8 bssid[6]; + u8 bss_color:6; + u8 bcn_hit_cond:2; + u8 hit_rule:2; + u8 is_mul_ent:1; + u8 tsf_sync:3; + u8 trigger:1; + u8 lsig_txop:1; + u8 tgt_ind:3; + u8 frm_tgt_ind:3; + u8 wol_pattern:1; + u8 wol_uc:1; + u8 wol_magic:1; + u8 wapi:1; + u8 sec_ent_mode:2; + u8 is_hesta:1; + u8 dl_bw:2; + u8 tf_mac_padding:2; + u8 dl_t_pe: 3; + u16 aid; + struct mac_ax_addr_cam_info a_info; + struct mac_ax_bssid_cam_info b_info; + struct mac_ax_sec_cam_info s_info; + struct mac_ax_cctl_info c_info; +}; + +/** + * @struct mac_role_tbl + * @brief mac_role_tbl + * + * @var mac_role_tbl::next + * Please Place Description here. + * @var mac_role_tbl::prev + * Please Place Description here. + * @var mac_role_tbl::info + * Please Place Description here. + * @var mac_role_tbl::macid + * Please Place Description here. + * @var mac_role_tbl::wmm + * Please Place Description here. + */ +struct mac_role_tbl { + /* keep first */ + struct mac_role_tbl *next; + struct mac_role_tbl *prev; + struct mac_ax_role_info info; + u8 macid; + u8 wmm; +}; + +/** + * @struct mac_role_tbl_head + * @brief mac_role_tbl_head + * + * @var mac_role_tbl_head::next + * Please Place Description here. + * @var mac_role_tbl_head::prev + * Please Place Description here. + * @var mac_role_tbl_head::role_tbl_pool + * Please Place Description here. + * @var mac_role_tbl_head::qlen + * Please Place Description here. + * @var mac_role_tbl_head::lock + * Please Place Description here. + */ +struct mac_role_tbl_head { + /* keep first */ + struct mac_role_tbl *next; + struct mac_role_tbl *prev; + struct mac_role_tbl_head *role_tbl_pool; + u32 qlen; + mac_ax_mutex lock; +}; + +/** + * @struct mac_ax_coex + * @brief mac_ax_coex + * + * @var mac_ax_coex::pta_mode + * Please Place Description here. + * @var mac_ax_coex::direction + * Please Place Description here. + */ +struct mac_ax_coex { +#define MAC_AX_COEX_RTK_MODE 0 +#define MAC_AX_COEX_CSR_MODE 1 + u8 pta_mode; +#define MAC_AX_COEX_INNER 0 +#define MAC_AX_COEX_OUTPUT 1 +#define MAC_AX_COEX_INPUT 2 + u8 direction; +}; + +/** + * @struct mac_ax_port_tsf + * @brief mac_ax_port_tsf + * + * @var mac_ax_port_tsf::tsf_l + * Please Place Description here. + * @var mac_ax_port_tsf::tsf_h + * Please Place Description here. + * @var mac_ax_port_tsf::port + * Please Place Description here. + */ +struct mac_ax_port_tsf { + u32 tsf_l; + u32 tsf_h; + u8 port; +}; + +/** + * @struct mac_ax_gnt + * @brief mac_ax_gnt + * + * @var mac_ax_gnt::gnt_bt_sw_en + * Please Place Description here. + * @var mac_ax_gnt::gnt_bt + * Please Place Description here. + * @var mac_ax_gnt::gnt_wl_sw_en + * Please Place Description here. + * @var mac_ax_gnt::gnt_wl + * Please Place Description here. + */ +struct mac_ax_gnt { + u8 gnt_bt_sw_en; + u8 gnt_bt; + u8 gnt_wl_sw_en; + u8 gnt_wl; +}; + +/** + * @struct mac_ax_coex_gnt + * @brief mac_ax_coex_gnt + * + * @var mac_ax_coex_gnt::band0 + * Please Place Description here. + * @var mac_ax_coex_gnt::band1 + * Please Place Description here. + */ +struct mac_ax_coex_gnt { + struct mac_ax_gnt band0; + struct mac_ax_gnt band1; +}; + +/** + * @struct mac_ax_plt + * @brief mac_ax_plt + * + * @var mac_ax_plt::band + * Please Place Description here. + * @var mac_ax_plt::tx + * Please Place Description here. + * @var mac_ax_plt::rx + * Please Place Description here. + */ +struct mac_ax_plt { +#define MAC_AX_PLT_LTE_RX BIT(0) +#define MAC_AX_PLT_GNT_BT_TX BIT(1) +#define MAC_AX_PLT_GNT_BT_RX BIT(2) +#define MAC_AX_PLT_GNT_WL BIT(3) + u8 band; + u8 tx; + u8 rx; +}; + +/** + * @struct mac_ax_rx_cnt + * @brief mac_ax_rx_cnt + * + * @var mac_ax_rx_cnt::type + * Please Place Description here. + * @var mac_ax_rx_cnt::op + * Please Place Description here. + * @var mac_ax_rx_cnt::idx + * Please Place Description here. + * @var mac_ax_rx_cnt::band + * Please Place Description here. + * @var mac_ax_rx_cnt::buf + * Please Place Description here. + */ +struct mac_ax_rx_cnt { +#define MAC_AX_RX_CRC_OK 0 +#define MAC_AX_RX_CRC_FAIL 1 +#define MAC_AX_RX_FA 2 +#define MAC_AX_RX_PPDU 3 +#define MAC_AX_RX_IDX 4 + u8 type; +#define MAC_AX_RXCNT_R 0 +#define MAC_AX_RXCNT_RST_ALL 1 + u8 op; + u8 idx; + u8 band; + u16 *buf; +}; + +/** + * @struct mac_ax_tx_cnt + * @brief mac_ax_tx_cnt + * + * @var mac_ax_tx_cnt::band + * Please Place Description here. + * @var mac_ax_tx_cnt::sel + * Please Place Description here. + * @var mac_ax_tx_cnt::txcnt + * Please Place Description here. + */ +struct mac_ax_tx_cnt { +#define MAC_AX_TX_LCCK 0 +#define MAC_AX_TX_SCCK 1 +#define MAC_AX_TX_OFDM 2 +#define MAC_AX_TX_HT 3 +#define MAC_AX_TX_HTGF 4 +#define MAC_AX_TX_VHTSU 5 +#define MAC_AX_TX_VHTMU 6 +#define MAC_AX_TX_HESU 7 +#define MAC_AX_TX_HEERSU 8 +#define MAC_AX_TX_HEMU 9 +#define MAC_AX_TX_HETB 10 +#define MAC_AX_TX_ALLTYPE 11 + u8 band; + u8 sel; + u16 txcnt[MAC_AX_TX_ALLTYPE]; +}; + +/** + * @struct mac_ax_mcc_role + * @brief mac_ax_mcc_role + * + * @var mac_ax_mcc_role::macid + * Please Place Description here. + * @var mac_ax_mcc_role::central_ch_seg0 + * Please Place Description here. + * @var mac_ax_mcc_role::central_ch_seg1 + * Please Place Description here. + * @var mac_ax_mcc_role::primary_ch + * Please Place Description here. + * @var mac_ax_mcc_role::bandwidth + * Please Place Description here. + * @var mac_ax_mcc_role::group + * Please Place Description here. + * @var mac_ax_mcc_role::c2h_rpt + * Please Place Description here. + * @var mac_ax_mcc_role::dis_tx_null + * Please Place Description here. + * @var mac_ax_mcc_role::dis_sw_retry + * Please Place Description here. + * @var mac_ax_mcc_role::in_curr_ch + * Please Place Description here. + * @var mac_ax_mcc_role::sw_retry_count + * Please Place Description here. + * @var mac_ax_mcc_role::tx_null_early + * Please Place Description here. + * @var mac_ax_mcc_role::rsvd0 + * Please Place Description here. + * @var mac_ax_mcc_role::duration + * Please Place Description here. + */ +struct mac_ax_mcc_role { + /* dword0 */ + u32 macid: 8; + u32 central_ch_seg0: 8; + u32 central_ch_seg1: 8; + u32 primary_ch: 8; + /* dword1 */ + enum channel_width bandwidth: 4; + u32 group: 2; +#define MCC_C2H_RPT_OFF 0 +#define MCC_C2H_RPT_FAIL_ONLY 1 +#define MCC_C2H_RPT_ALL 2 + u32 c2h_rpt: 2; + u32 dis_tx_null: 1; + u32 dis_sw_retry: 1; + u32 in_curr_ch: 1; + u32 sw_retry_count: 3; + u32 tx_null_early: 4; + u32 btc_in_2g: 1; + u32 pta_en: 1; + u32 rfk_by_pass: 1; + u32 rsvd0: 11; + /* dword2 */ + u32 duration: 32; + /* dword3 */ + u8 courtesy_en; + u8 courtesy_num; + u8 courtesy_target; + u8 rsvd1; +}; + +struct mac_ax_mcc_start { + /* dword0 */ + u32 group: 2; + u32 btc_in_group: 1; + u32 old_group_action: 2; + u32 old_group:2; + u32 rsvd0: 17; + u32 macid: 8; + /* dword1 */ + u32 tsf_low; + /* dword2 */ + u32 tsf_high; +}; + +/** + * @struct mac_ax_mcc_duration_info + * @brief mac_ax_mcc_duration_info + * + * @var mac_ax_mcc_duration_info::group + * Please Place Description here. + * @var mac_ax_mcc_duration_info::rsvd0 + * Please Place Description here. + * @var mac_ax_mcc_duration_info::start_macid + * Please Place Description here. + * @var mac_ax_mcc_duration_info::macid_x + * Please Place Description here. + * @var mac_ax_mcc_duration_info::macid_y + * Please Place Description here. + * @var mac_ax_mcc_duration_info::start_tsf_low + * Please Place Description here. + * @var mac_ax_mcc_duration_info::start_tsf_high + * Please Place Description here. + * @var mac_ax_mcc_duration_info::duration_x + * Please Place Description here. + * @var mac_ax_mcc_duration_info::duration_y + * Please Place Description here. + */ +struct mac_ax_mcc_duration_info { + /* dword0 */ + u32 group: 2; + u32 btc_in_group:1; + u32 rsvd0: 5; + u32 start_macid: 8; + u32 macid_x: 8; + u32 macid_y: 8; + /* dword1 */ + u32 start_tsf_low; + /* dword2 */ + u32 start_tsf_high; + /* dword3 */ + u32 duration_x; + /* dword4 */ + u32 duration_y; +}; + +/** + * @struct mac_ax_mcc_group + * @brief mac_ax_mcc_group + * + * @var mac_ax_mcc_group::rpt_status + * Please Place Description here. + * @var mac_ax_mcc_group::rpt_macid + * Please Place Description here. + * @var mac_ax_mcc_group::macid_x + * Please Place Description here. + * @var mac_ax_mcc_group::macid_y + * Please Place Description here. + * @var mac_ax_mcc_group::rpt_tsf_high + * Please Place Description here. + * @var mac_ax_mcc_group::rpt_tsf_low + * Please Place Description here. + * @var mac_ax_mcc_group::tsf_x_high + * Please Place Description here. + * @var mac_ax_mcc_group::tsf_x_low + * Please Place Description here. + * @var mac_ax_mcc_group::tsf_y_high + * Please Place Description here. + * @var mac_ax_mcc_group::tsf_y_low + * Please Place Description here. + */ +struct mac_ax_mcc_group { + u8 rpt_status; + u8 rpt_macid; + u8 macid_x; + u8 macid_y; + u32 rpt_tsf_high; + u32 rpt_tsf_low; + u32 tsf_x_high; + u32 tsf_x_low; + u32 tsf_y_high; + u32 tsf_y_low; +}; + +/** + * @struct mac_ax_mcc_group_info + * @brief mac_ax_mcc_group_info + * + * @var mac_ax_mcc_group_info::groups + * Please Place Description here. + */ +struct mac_ax_mcc_group_info { + struct mac_ax_mcc_group groups[4]; +}; + +/** + * @struct mac_ax_tx_tf_info + * @brief mac_ax_tx_tf_info + * + * @var mac_ax_tx_tf_info::tx_tf_infol + * Please Place Description here. + * @var mac_ax_tx_tf_info::tx_tf_infoh + * Please Place Description here. + * @var mac_ax_tx_tf_info::tx_tf_infosel + * Please Place Description here. + */ +struct mac_ax_tx_tf_info { + u32 tx_tf_infol; + u32 tx_tf_infoh; + u8 tx_tf_infosel;//4:common info; 0~3: user0 ~ user3 info +}; + +/** + * @struct mac_ax_sr_info + * @brief mac_ax_sr_info + * + * @var mac_ax_sr_info::sr_en + * Please Place Description here. + * @var mac_ax_sr_info::sr_field_v15_allowed + * Please Place Description here. + * @var mac_ax_sr_info::srg_obss_pd_min + * Please Place Description here. + * @var mac_ax_sr_info::srg_obss_pd_max + * Please Place Description here. + * @var mac_ax_sr_info::non_srg_obss_pd_min + * Please Place Description here. + * @var mac_ax_sr_info::non_srg_obss_pd_max + * Please Place Description here. + * @var mac_ax_sr_info::srg_bsscolor_bitmap_0 + * Please Place Description here. + * @var mac_ax_sr_info::srg_bsscolor_bitmap_1 + * Please Place Description here. + * @var mac_ax_sr_info::srg_partbsid_bitmap_0 + * Please Place Description here. + * @var mac_ax_sr_info::srg_partbsid_bitmap_1 + * Please Place Description here. + */ +struct mac_ax_sr_info { + u8 sr_en: 1; + u8 sr_field_v15_allowed: 1; + u8 srg_obss_pd_min; + u8 srg_obss_pd_max; + u8 non_srg_obss_pd_min; + u8 non_srg_obss_pd_max; + u32 srg_bsscolor_bitmap_0; + u32 srg_bsscolor_bitmap_1; + u32 srg_partbsid_bitmap_0; + u32 srg_partbsid_bitmap_1; +}; + +/** + * @struct mac_ax_nav_padding + * @brief mac_ax_nav_padding + * + * @var mac_ax_nav_padding::band + * Please Place Description here. + * @var mac_ax_nav_padding::nav_pad_en + * Please Place Description here. + * @var mac_ax_nav_padding::over_txop_en + * Please Place Description here. + * @var mac_ax_nav_padding::nav_padding + * Please Place Description here. + */ +struct mac_ax_nav_padding { + u8 band; + u8 nav_pad_en; + u8 over_txop_en; + u16 nav_padding; +}; + +/** + * @struct mac_ax_max_tx_time + * @brief mac_ax_max_tx_time + * + * @var mac_ax_max_tx_time::macid + * Please Place Description here. + * @var mac_ax_max_tx_time::is_cctrl + * Please Place Description here. + * @var mac_ax_max_tx_time::max_tx_time + * Please Place Description here. + */ +struct mac_ax_max_tx_time { + u8 macid; + u8 is_cctrl; + u32 max_tx_time; /* us */ +}; + +/** + * @struct mac_ax_hw_rts_th + * @brief Config HW RTS time/len threshold + * + * @var mac_ax_hw_rts_th::band + * the mac_band to setup/query + * @var mac_ax_hw_rts_th::time_th + * HW RTS time threshold + * @var mac_ax_hw_rts_th::time_th + * HW RTS length threshold + */ +struct mac_ax_hw_rts_th { + u8 band; + u16 time_th; /* us */ + u16 len_th; /* byte */ +}; + +/** + * @struct mac_ax_io_stat + * @brief Get IO state from HCI (PCIE: LBC) + * + * @var mac_ax_io_stat::to_flag + * timeout flag is set + * @var mac_ax_io_stat::io_st + * IO state from sm.io_st + * @var mac_ax_io_stat::rsvd + * reserved + * @var mac_ax_io_stat::addr + * the last timeout addr when timeout flag is set + */ +struct mac_ax_io_stat { + u8 to_flag:1; + u8 io_st:1; + u8 rsvd:6; + u32 addr; +}; + +/** + * @struct mac_ax_drv_stats + * @brief + * + * The driver status in halmac + * + * @var mac_ax_drv_stats::rx_ok + * RX status + * @var mac_ax_drv_stats::drv_rm + * Driver is removed + */ +struct mac_ax_drv_stats { + u8 rx_ok; + u8 drv_rm; +}; + +/** + * @struct mac_ax_wps_cfg + * @brief + * + * WPS is a driver feature to detect button pressed or released. + * In HW view, the feature is to check the GPIO input value is 0->1 or 1->0 + * We use FW to detect GPIO val. + * In a specified interval, if FW detects value changed, it will send a C2H + * + * @var mac_ax_wps_cfg::en + * Enable WPS function i.e, Enable FW reports C2H + * @var mac_ax_wps_cfg::gpio + * The GPIO to be detected + * @var mac_ax_wps_cfg::interval + * The detecting interval in ms + */ +struct mac_ax_cfg_wps { + u8 en; + u8 gpio; + u8 interval; /* ms */ +}; + +/** + * @struct mac_fw_msg + * @brief + * + * fw message encode/decode table + * + * @var mac_fw_msg::msgno + * @var mac_fw_msg::msg + */ +struct mac_fw_msg { + u32 msgno; + char *msg; +}; + +/** + * @struct mac_ax_ss_link_info + * @brief mac_ax_ss_link_info + * + * @var mac_ax_ss_link_info::wmm + * Please Place Description here. + * @var mac_ax_ss_link_info::ac + * Please Place Description here. + * @var mac_ax_ss_link_info::ul + * Please Place Description here. + * @var mac_ax_ss_link_info::link_list + * Please Place Description here. + * @var mac_ax_ss_link_info::link_head + * Please Place Description here. + * @var mac_ax_ss_link_info::link_tail + * Please Place Description here. + * @var mac_ax_ss_link_info::link_len + * Please Place Description here. + * @var mac_ax_ss_link_info::macid0 + * Please Place Description here. + * @var mac_ax_ss_link_info::macid1 + * Please Place Description here. + * @var mac_ax_ss_link_info::macid2 + * Please Place Description here. + * @var mac_ax_ss_link_info::link_bitmap + * Please Place Description here. + */ +struct mac_ax_ss_link_info { + u8 wmm; + u8 ac; + u8 ul; + u8 link_list[SS_LINK_SIZE]; + u8 link_head; + u8 link_tail; + u8 link_len; + u8 macid0; + u8 macid1; + u8 macid2; + u8 link_bitmap[SS_LINK_SIZE]; +}; + +/*------------------- Define FAST_CH_SW related structure ---------------------------*/ + +/** + * @struct mac_ax_fast_ch_sw_param + * @brief + * + * FAST_CH_SW H2C params in driver + * + * @var mac_ax_fast_ch_sw_param::ap_port_id + * ap port id + * @var mac_ax_fast_ch_sw_param::ch_idx + * mapped channel idx for restoring rf param + * @var mac_ax_fast_ch_sw_param::thermal_idx + * thermal idx for restoring rf param + * @var mac_ax_fast_ch_sw_param::pause_rel_mode + * pause and release mode + * @var mac_ax_fast_ch_sw_param::con_sta_num + * num of connected sta currently + * @var mac_ax_fast_ch_sw_param::band + * PHY band + * @var mac_ax_fast_ch_sw_param::bandwidth + * bw of 20/40/80 + * @var mac_ax_fast_ch_sw_param::pri_ch + * pri channel of target channel + * @var mac_ax_fast_ch_sw_param::central_ch + * central channel of target channel + * @var mac_ax_fast_ch_sw_param::rel_pause_tsfl + * release pause tsfl + * @var mac_ax_fast_ch_sw_param::rel_pause_tsfh + * release pause tsfh + * @var mac_ax_fast_ch_sw_param::rel_pause_delay_time + * release pause delay time + * @var mac_ax_fast_ch_sw_param::csa_pkt_id[MAC_AX_FAST_CH_SW_MAX_STA_NUM] + * offloaded CSA packet id for at most 4 stas + */ +struct mac_ax_fast_ch_sw_param { + /* dword0 */ + u8 ap_port_id:4; + u8 ch_idx:4; + u8 thermal_idx:4; + u8 pause_rel_mode:4; + u8 con_sta_num; + u8 band:1; + u8 bandwidth:2; + u8 rsvd0:5; + /* dword1 */ + u8 pri_ch; + u8 central_ch; + u16 rsvd1; + /* dword2 */ + u32 rel_pause_tsfl; + /* dword3 */ + u32 rel_pause_tsfh; + /* dword4 */ + u32 rel_pause_delay_time; + /* dword5 */ + u8 csa_pkt_id[MAC_AX_FAST_CH_SW_MAX_STA_NUM]; +}; + +/** + * @struct mac_ax_fast_ch_sw_info + * @brief + * + * FAST_CH_SW status in driver + * + * @var mac_ax_fast_ch_sw_info::busy + * FW handling or not + * @var mac_ax_fast_ch_sw_info::status + * Last status of FCS + */ +struct mac_ax_fast_ch_sw_info{ + bool busy; + u32 status; +}; + +/*------------------- END Define FAST_CH_SW related structure ---------------------------*/ + +/*------------------- Define ch_switch related structure ---------------------------*/ +/** + * @struct ch_switch_rpt + * @brief ch_switch_rpt + * + * @var ch_switch_rpt::result + * result + * @var ch_switch_rpt::mac_time + * mac_time + * @var ch_switch_rpt::bb_time + * bb_time + * @var ch_switch_rpt::rf_time + * rf_time + * @var ch_switch_rpt::rf_reload_time + * rf_reload_time + * @var ch_switch_rpt::total_time + * total_time + */ +struct mac_ax_ch_switch_rpt { + u8 result; +}; + +/** + * @struct ch_switch_parm + * @brief ch_switch_parm + * + * @var ch_switch_parm::pri_ch + * pri ch + * @var ch_switch_parm::central_ch + * central ch + * @var ch_switch_parm::port + * port + * @var ch_switch_parm::bw + * bw + * @var ch_switch_parm::ch_band + * ch_band + * @var ch_switch_parm::band + * band + * @var ch_switch_parm::reload_rf + * reload rf + * @var ch_switch_parm::c2h_rpt + * c2h report + * @var ch_switch_parm::rsvd + * rsvd + */ +struct mac_ax_ch_switch_parm { + u8 pri_ch; + u8 central_ch; + u8 bw:3; + u8 ch_band:2; + u8 band:1; + u8 reload_rf:1; + u16 rsvd:9; +}; + +/*------------------- ENDDefine ch_switch related structure ---------------------------*/ + +struct mac_ax_tf_user_sts { + u8 macid; + u8 tb_rate; + u8 tb_fail_per; + u8 avg_tb_rssi; + u8 cca_miss_per; + u8 avg_uph; + u8 minflag_per; + u8 avg_tb_evm; +}; + +struct mac_ax_tf_sts { + u8 user_num; + u8 ru_su_per; + u16 rsvd; + struct mac_ax_tf_user_sts tf_user_sts[UL_PER_STA_DBGINFO_NUM]; +}; + +struct mac_ax_fwc2h_sts { + struct mac_ax_tf_sts tfsts; +}; + +struct mac_ax_fwsts_para { + u16 en:1; + u16 rsvd:15; + u16 intvl_ms; +}; + +/*--------------------Define power saving related struct -------------------------*/ +/** + * @struct mac_ax_lps_info + * @brief mac_ax_lps_info + * + * @var mac_ax_lps_info::listen_bcn_mode + * Please Place Description here. + * @var mac_ax_lps_info::awake_interval + * Please Place Description here. + * @var mac_ax_lps_info::smart_ps_mode + * Please Place Description here. + */ +struct mac_ax_lps_info { + enum mac_ax_listern_bcn_mode listen_bcn_mode; + u8 awake_interval; + enum mac_ax_smart_ps_mode smart_ps_mode; +}; + +/** + * @struct mac_ax_ps_adv_parm + * @brief mac_ax_ps_adv_parm + * + * @var mac_ax_ps_adv_parm::macid + * Please Place Description here. + * @var mac_ax_ps_adv_parm::TRXTimeOutTimeSet + * Please Place Description here. + * @var mac_ax_ps_adv_parm::rsvd0 + * Please Place Description here. + * @var mac_ax_ps_adv_parm::TRXTimeOutTimeVal + * Please Place Description here. + * @var mac_ax_ps_adv_parm::rsvd1 + * Please Place Description here. + */ +struct mac_ax_ps_adv_parm { + u32 macid:8; + u32 trxtimeouttimeset:2; + u32 rsvd0:22; + u32 trxtimeouttimeval:8; + u32 rsvd1:24; +}; + +/*--------------------Define Adapter & OPs------------------------------------*/ +#ifndef CONFIG_NEW_HALMAC_INTERFACE + +/** + * @struct mac_ax_pltfm_cb + * @brief mac_ax_pltfm_cb + * + * @var mac_ax_pltfm_cb::sdio_cmd52_r8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_r8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_r16 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_r32 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_rn + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd52_w8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_w8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_w16 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_w32 + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd53_wn + * Please Place Description here. + * @var mac_ax_pltfm_cb::sdio_cmd52_cia_r8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_r8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_r16 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_r32 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_w8 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_w16 + * Please Place Description here. + * @var mac_ax_pltfm_cb::reg_w32 + * Please Place Description here. + * @var mac_ax_pltfm_cb::tx + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_query_h2c + * Please Place Description here. + * @var mac_ax_pltfm_cb::tx + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_free + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_malloc + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_memcpy + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_memset + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_memcmp + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_delay_us + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_delay_ms + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_mutex_init + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_mutex_deinit + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_mutex_lock + * Please Place Description here. + * @var mac_ax_pltfm_cb::rtl_mutex_unlock + * Please Place Description here. + * @var mac_ax_pltfm_cb::msg_print + * Please Place Description here. + * @var mac_ax_pltfm_cb::event_notify + * Please Place Description here. + */ +struct mac_ax_pltfm_cb { +#if MAC_AX_SDIO_SUPPORT + u8 (*sdio_cmd52_r8)(void *drv_adapter, u32 addr); + u8 (*sdio_cmd53_r8)(void *drv_adapter, u32 addr); + u16 (*sdio_cmd53_r16)(void *drv_adapter, u32 addr); + u32 (*sdio_cmd53_r32)(void *drv_adapter, u32 addr); + u8 (*sdio_cmd53_rn)(void *drv_adapter, u32 addr, u32 size, u8 *val); + void (*sdio_cmd52_w8)(void *drv_adapter, u32 addr, u8 val); + void (*sdio_cmd53_w8)(void *drv_adapter, u32 addr, u8 val); + void (*sdio_cmd53_w16)(void *drv_adapter, u32 addr, u16 val); + void (*sdio_cmd53_w32)(void *drv_adapter, u32 addr, u32 val); + u8 (*sdio_cmd53_wn)(void *drv_adapter, u32 addr, u32 size, u8 *val); + u8 (*sdio_cmd52_cia_r8)(void *drv_adapter, u32 addr); +#endif +#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT) + u8 (*reg_r8)(void *drv_adapter, u32 addr); + u16 (*reg_r16)(void *drv_adapter, u32 addr); + u32 (*reg_r32)(void *drv_adapter, u32 addr); + void (*reg_w8)(void *drv_adapter, u32 addr, u8 val); + void (*reg_w16)(void *drv_adapter, u32 addr, u16 val); + void (*reg_w32)(void *drv_adapter, u32 addr, u32 val); +#endif +#if MAC_AX_PHL_H2C + enum rtw_hal_status (*tx)(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, + struct rtw_h2c_pkt *pkt); + struct rtw_h2c_pkt *(*rtl_query_h2c)(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, + enum h2c_buf_class type); + enum rtw_hal_status (*rtl_recycle_h2c)(struct rtw_phl_com_t *phl_com, + struct rtw_h2c_pkt *h2c_pkt); +#else + u32 (*tx)(void *drv_adapter, u8 *buf, u32 len); +#endif + void (*rtl_free)(void *drv_adapter, void *buf, u32 size); + void* (*rtl_malloc)(void *drv_adapter, u32 size); + void (*rtl_memcpy)(void *drv_adapter, void *dest, void *src, u32 size); + void (*rtl_memset)(void *drv_adapter, void *addr, u8 val, u32 size); + s32 (*rtl_memcmp)(void *drv_adapter, void *ptr1, void *ptr2, u32 num); + void (*rtl_delay_us)(void *drv_adapter, u32 us); + void (*rtl_delay_ms)(void *drv_adapter, u32 ms); + + void (*rtl_mutex_init)(void *drv_adapter, mac_ax_mutex *mutex); + void (*rtl_mutex_deinit)(void *drv_adapter, mac_ax_mutex *mutex); + void (*rtl_mutex_lock)(void *drv_adapter, mac_ax_mutex *mutex); + void (*rtl_mutex_unlock)(void *drv_adapter, mac_ax_mutex *mutex); + void (*msg_print)(void *drv_adapter, u8 dbg_level, s8 *fmt, ...); + void (*event_notify)(void *drv_adapter, + enum mac_ax_feature mac_ft, + enum mac_ax_status stat, u8 *buf, u32 size); +#if MAC_AX_FEATURE_DBGCMD + s32 (*rtl_sprintf)(void *drv_adapter, char *buf, size_t size, const char *fmt, ...); + s32 (*rtl_strcmp)(void *drv_adapter, const char *s1, const char *s2); + char* (*rtl_strsep)(void *drv_adapter, char **s, const char *ct); + u32 (*rtl_strlen)(void *drv_adapter, char *buf); + char* (*rtl_strcpy)(void *drv_adapter, char *dest, const char *src); + char* (*rtl_strpbrk)(void *drv_adapter, const char *cs, const char *ct); + u32 (*rtl_strtoul)(void *drv_adapter, const char *buf, u32 base); +#endif + void (*ser_l2_notify)(void *phl_com, + void *hal_com); + + u8 (*ld_fw_symbol)(void *phl_adapter, void *drv_adapter, + const char *name, u8 **buf, u32 *buf_size); +}; +#endif/*CONFIG_NEW_HALMAC_INTERFACE*/ + +/** + * @struct mac_ax_adapter + * @brief mac_ax_adapter + * + * @var mac_ax_adapter::ops + * Please Place Description here. + * @var mac_ax_adapter::drv_adapter + * Please Place Description here. + * @var mac_ax_adapter::phl_adapter + * Please Place Description here. + * @var mac_ax_adapter::pltfm_cb + * Please Place Description here. + * @var mac_ax_adapter::sm + * Please Place Description here. + * @var mac_ax_adapter::hw_info + * Please Place Description here. + * @var mac_ax_adapter::fw_info + * Please Place Description here. + * @var mac_ax_adapter::efuse_param + * Please Place Description here. + * @var mac_ax_adapter::mac_pwr_info + * Please Place Description here. + * @var mac_ax_adapter::ft_stat + * Please Place Description here. + * @var mac_ax_adapter::hfc_param + * Please Place Description here. + * @var mac_ax_adapter::dle_info + * Please Place Description here. + * @var mac_ax_adapter::gpio_info + * Please Place Description here. + * @var mac_ax_adapter::role_tbl + * Please Place Description here. + * @var mac_ax_adapter::read_ofld_info + * Please Place Description here. + * @var mac_ax_adapter::read_ofld_value + * Please Place Description here. + * @var mac_ax_adapter::write_ofld_info + * Please Place Description here. + * @var mac_ax_adapter::efuse_ofld_info + * Please Place Description here. + * @var mac_ax_adapter::conf_ofld_info + * Please Place Description here. + * @var mac_ax_adapter::pkt_ofld_info + * Please Place Description here. + * @var mac_ax_adapter::pkt_ofld_pkt + * Please Place Description here. + * @var mac_ax_adapter::mcc_group_info + * Please Place Description here. + * @var mac_ax_adapter::wowlan_info + * Please Place Description here. + * @var mac_ax_adapter::sdio_info + * Please Place Description here. + * @var mac_ax_adapter::usb_info + * Please Place Description here. + * @var mac_ax_adapter::hv_ops + * Please Place Description here. + */ +struct mac_ax_adapter { + struct mac_ax_ops *ops; + void *drv_adapter; //hal_com adapter + void *phl_adapter; //phl_com adapter + struct mac_ax_pltfm_cb *pltfm_cb; + struct mac_ax_state_mach sm; + struct mac_ax_hw_info *hw_info; + struct mac_ax_fw_info fw_info; + struct mac_ax_efuse_param efuse_param; + struct mac_ax_mac_pwr_info mac_pwr_info; + struct mac_ax_ft_status *ft_stat; + struct mac_ax_hfc_param *hfc_param; + struct mac_ax_dle_info dle_info; + struct mac_ax_gpio_info gpio_info; + struct mac_role_tbl_head *role_tbl; + struct mac_ax_read_ofld_info read_ofld_info; + struct mac_ax_read_ofld_value read_ofld_value; + struct mac_ax_write_ofld_info write_ofld_info; + struct mac_ax_efuse_ofld_info efuse_ofld_info; + struct mac_ax_conf_ofld_info conf_ofld_info; + struct mac_ax_pkt_ofld_info pkt_ofld_info; + struct mac_ax_pkt_ofld_pkt pkt_ofld_pkt; + struct mac_ax_cmd_ofld_info cmd_ofld_info; + struct mac_ax_mcc_group_info mcc_group_info; + struct mac_ax_wowlan_info wowlan_info; + struct mac_ax_p2p_info *p2p_info; + struct mac_ax_t32_togl_rpt *t32_togl_rpt; + struct mac_ax_port_info *port_info; + struct mac_ax_int_stats stats; + struct mac_ax_drv_stats drv_stats; + struct mac_ax_h2c_agg_info h2c_agg_info; +#if MAC_AX_SDIO_SUPPORT + struct mac_ax_sdio_info sdio_info; +#endif +#if MAC_AX_USB_SUPPORT + struct mac_ax_usb_info usb_info; +#endif +#if MAC_AX_PCIE_SUPPORT + struct mac_ax_pcie_info pcie_info; +#endif + struct mac_ax_flash_info flash_info; + struct mac_ax_fast_ch_sw_info fast_ch_sw_info; +#if MAC_AX_FEATURE_HV + struct hv_ax_ops *hv_ops; + u8 env; +#endif +#if MAC_AX_FEATURE_DBGCMD + struct mac_ax_fw_dbgcmd fw_dbgcmd; +#endif +#if MAC_AX_FEATURE_DBGDEC + struct mac_fw_msg *fw_log_array; + struct mac_fw_msg *fw_log_array_dl; + u32 fw_log_array_dl_size; +#endif + struct mac_ax_fw_log log_cfg; + struct mac_ax_scanofld_info scanofld_info; + struct mac_ax_ch_switch_rpt *ch_switch_rpt; +}; + +/** + * mac_ax_intf_ops - interface related callbacks + * @reg_read8: + * @reg_write8: + * @reg_read16: + * @reg_write16: + * @reg_read32: + * @reg_write32: + * @tx_allow_sdio: + * @tx_cmd_addr_sdio: + * @init_intf: + * @reg_read_n_sdio: + * @get_bulkout_id: + */ + +/** + * @struct mac_ax_intf_ops + * @brief mac_ax_intf_ops + * + * @var mac_ax_intf_ops::reg_read8 + * Please Place Description here. + * @var mac_ax_intf_ops::reg_write8 + * Please Place Description here. + * @var mac_ax_intf_ops::reg_read16 + * Please Place Description here. + * @var mac_ax_intf_ops::reg_write16 + * Please Place Description here. + * @var mac_ax_intf_ops::reg_read32 + * Please Place Description here. + * @var mac_ax_intf_ops::reg_write32 + * Please Place Description here. + * @var mac_ax_intf_ops::tx_allow_sdio + * Please Place Description here. + * @var mac_ax_intf_ops::tx_cmd_addr_sdio + * Please Place Description here. + * @var mac_ax_intf_ops::intf_pre_init + * Please Place Description here. + * @var mac_ax_intf_ops::intf_init + * Please Place Description here. + * @var mac_ax_intf_ops::intf_deinit + * Please Place Description here. + * @var mac_ax_intf_ops::reg_read_n_sdio + * Please Place Description here. + * @var mac_ax_intf_ops::get_bulkout_id + * Please Place Description here. + * @var mac_ax_intf_ops::ltr_set_pcie + * Please Place Description here. + * @var mac_ax_intf_ops::u2u3_switch + * Please Place Description here. + * @var mac_ax_intf_ops::get_usb_mode + * Please Place Description here. + * @var mac_ax_intf_ops::get_usb_support_ability + * Please Place Description here. + * @var mac_ax_intf_ops::usb_tx_agg_cfg + * Please Place Description here. + * @var mac_ax_intf_ops::usb_rx_agg_cfg + * Please Place Description here. + * @var mac_ax_intf_ops::set_wowlan + * Please Place Description here. + */ +struct mac_ax_intf_ops { + u8 (*reg_read8)(struct mac_ax_adapter *adapter, u32 addr); + void (*reg_write8)(struct mac_ax_adapter *adapter, u32 addr, u8 val); + u16 (*reg_read16)(struct mac_ax_adapter *adapter, u32 addr); + void (*reg_write16)(struct mac_ax_adapter *adapter, u32 addr, u16 val); + u32 (*reg_read32)(struct mac_ax_adapter *adapter, u32 addr); + void (*reg_write32)(struct mac_ax_adapter *adapter, u32 addr, u32 val); + /** + * @tx_allow_sdio + * Only support SDIO interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*tx_allow_sdio)(struct mac_ax_adapter *adapter, + struct mac_ax_sdio_tx_info *info); + /** + * @tx_cmd_addr_sdio + * Only support SDIO interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*tx_cmd_addr_sdio)(struct mac_ax_adapter *adapter, + struct mac_ax_sdio_tx_info *info, + u32 *cmd_addr); + u32 (*intf_pre_init)(struct mac_ax_adapter *adapter, void *param); + u32 (*intf_init)(struct mac_ax_adapter *adapter, void *param); + u32 (*intf_deinit)(struct mac_ax_adapter *adapter, void *param); + /** + * @reg_read_n_sdio + * Only support SDIO interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*reg_read_n_sdio)(struct mac_ax_adapter *adapter, u32 addr, + u32 size, u8 *val); + /** + * @get_bulkout_id + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u8 (*get_bulkout_id)(struct mac_ax_adapter *adapter, u8 ch_dma, + u8 mode); + /** + * @ltr_set_pcie + * Only support PCIe interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*ltr_set_pcie)(struct mac_ax_adapter *adapter, + struct mac_ax_pcie_ltr_param *param); + /** + * @u2u3_switch + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*u2u3_switch)(struct mac_ax_adapter *adapter); + /** + * @get_usb_mode + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*get_usb_mode)(struct mac_ax_adapter *adapter); + /** + * @get_usb_support_ability + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*get_usb_support_ability)(struct mac_ax_adapter *adapter); + /** + * @usb_tx_agg_cfg + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*usb_tx_agg_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_usb_tx_agg_cfg *agg); + /** + * @usb_rx_agg_cfg + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*usb_rx_agg_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_agg_cfg *cfg); + + u32 (*set_wowlan)(struct mac_ax_adapter *adapter, + enum mac_ax_wow_ctrl w_c); + /** + * @ctrl_txdma_ch + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*ctrl_txdma_ch)(struct mac_ax_adapter *adapter, + struct mac_ax_txdma_ch_map *ch_map); + /** + * @clr_idx_all + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*clr_idx_all)(struct mac_ax_adapter *adapter); + /** + * @poll_txdma_ch_idle + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*poll_txdma_ch_idle)(struct mac_ax_adapter *adapter, + struct mac_ax_txdma_ch_map *ch_map); + /** + * @poll_rxdma_ch_idle + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*poll_rxdma_ch_idle)(struct mac_ax_adapter *adapter, + struct mac_ax_rxdma_ch_map *ch_map); + /** + * @ctrl_txhci + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*ctrl_txhci)(struct mac_ax_adapter *adapter, + enum mac_ax_func_sw en); + /** + * @ctrl_rxhci + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*ctrl_rxhci)(struct mac_ax_adapter *adapter, + enum mac_ax_func_sw en); + /** + * @ctrl_dma_io + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*ctrl_dma_io)(struct mac_ax_adapter *adapter, + enum mac_ax_func_sw en); + /** + * @get_io_stat + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*get_io_stat)(struct mac_ax_adapter *adapter, + struct mac_ax_io_stat *out_st); + /** + * @get_txagg_num + */ + u32 (*get_txagg_num)(struct mac_ax_adapter *adapter, + u8 band); + /** + * @get_rx_state + * Only support USB interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*get_rx_state)(struct mac_ax_adapter *adapter, u32 *val); + + /** + * @pcie_autok_counter_avg + * Only support PCIE interface. Using this API in other interface + * may cause system crash or segmentation fault. + */ + u32 (*pcie_autok_counter_avg)(struct mac_ax_adapter *adapter); +}; + +/** + * struct mac_ax_ops - callbacks for mac control + * All callbacks can be used after initializing mac_ax_ops by mac_ax_ops_init. + * @intf_ops: interface related callbacks, refer struct mac_ax_intf_ops to get + * more deatails. + * @get_hw_info: get mac hardware information + * @mac_txdesc_len: + * @build_mac_txdesc: + */ + +/** + * @struct mac_ax_ops + * @brief mac_ax_ops + * + * @var mac_ax_ops::intf_ops + * Please Place Description here. + * @var mac_ax_ops::hal_init + * Please Place Description here. + * @var mac_ax_ops::hal_fast_init + * Please Place Description here. + * @var mac_ax_ops::hal_deinit + * Please Place Description here. + * @var mac_ax_ops::hal_fast_deinit + * Please Place Description here. + * @var mac_ax_ops::add_role + * Please Place Description here. + * @var mac_ax_ops::remove_role + * Please Place Description here. + * @var mac_ax_ops::change_role + * Please Place Description here. + * @var mac_ax_ops::pwr_switch + * Please Place Description here. + * @var mac_ax_ops::sys_init + * Please Place Description here. + * @var mac_ax_ops::trx_init + * Please Place Description here. + * @var mac_ax_ops::romdl + * Please Place Description here. + * @var mac_ax_ops::enable_cpu + * Please Place Description here. + * @var mac_ax_ops::disable_cpu + * Please Place Description here. + * @var mac_ax_ops::fwredl + * Please Place Description here. + * @var mac_ax_ops::fwdl + * Please Place Description here. + * @var mac_ax_ops::enable_fw + * Please Place Description here. + * @var mac_ax_ops::lv1_rcvy + * Please Place Description here. + * @var mac_ax_ops::get_macaddr + * Please Place Description here. + * @var mac_ax_ops::build_txdesc + * Please Place Description here. + * @var mac_ax_ops::refill_txdesc + * Please Place Description here. + * @var mac_ax_ops::parse_rxdesc + * Please Place Description here. + * @var mac_ax_ops::reset_fwofld_state + * Please Place Description here. + * @var mac_ax_ops::check_fwofld_done + * Please Place Description here. + * @var mac_ax_ops::read_pkt_ofld + * Please Place Description here. + * @var mac_ax_ops::del_pkt_ofld + * Please Place Description here. + * @var mac_ax_ops::add_pkt_ofld + * Please Place Description here. + * @var mac_ax_ops::pkt_ofld_packet + * Please Place Description here. + * @var mac_ax_ops::dump_efuse_ofld + * Please Place Description here. + * @var mac_ax_ops::efuse_ofld_map + * Please Place Description here. + * @var mac_ax_ops::upd_dctl_info + * Please Place Description here. + * @var mac_ax_ops::upd_cctl_info + * Please Place Description here. + * @var mac_ax_ops::ie_cam_upd + * Please Place Description here. + * @var mac_ax_ops::twt_info_upd_h2c + * Please Place Description here. + * @var mac_ax_ops::twt_act_h2c + * Please Place Description here. + * @var mac_ax_ops::twt_anno_h2c + * Please Place Description here. + * @var mac_ax_ops::twt_wait_anno + * Please Place Description here. + * @var mac_ax_ops::mac_host_getpkt_h2c + * Please Place Description here. + * @var mac_ax_ops::p2p_act_h2c + * Please Place Description here. + * @var mac_ax_ops::sta_add_key + * Please Place Description here. + * @var mac_ax_ops::sta_del_key + * Please Place Description here. + * @var mac_ax_ops::sta_search_key_idx + * Please Place Description here. + * @var mac_ax_ops::sta_hw_security_support + * Please Place Description here. + * @var mac_ax_ops::set_mu_table + * Please Place Description here. + * @var mac_ax_ops::ss_dl_grp_upd + * Please Place Description here. + * @var mac_ax_ops::ss_ul_grp_upd + * Please Place Description here. + * @var mac_ax_ops::ss_ul_sta_upd + * Please Place Description here. + * @var mac_ax_ops::bacam_info + * Please Place Description here. + * @var mac_ax_ops::txdesc_len + * Please Place Description here. + * @var mac_ax_ops::upd_shcut_mhdr + * Please Place Description here. + * @var mac_ax_ops::enable_hwmasdu + * Please Place Description here. + * @var mac_ax_ops::enable_cut_hwamsdu + * Please Place Description here. + * @var mac_ax_ops::hdr_conv + * Please Place Description here. + * @var mac_ax_ops::set_hwseq_reg + * Please Place Description here. + * @var mac_ax_ops::process_c2h + * Please Place Description here. + * @var mac_ax_ops::parse_dfs + * Please Place Description here. + * @var mac_ax_ops::parse_ppdu + * Please Place Description here. + * @var mac_ax_ops::cfg_phy_rpt + * Please Place Description here. + * @var mac_ax_ops::set_rx_forwarding + * Please Place Description here. + * @var mac_ax_ops::get_rx_fltr_opt + * Please Place Description here. + * @var mac_ax_ops::set_rx_fltr_opt + * Please Place Description here. + * @var mac_ax_ops::set_rx_fltr_typ_opt + * Please Place Description here. + * @var mac_ax_ops::set_rx_fltr_typstyp_opt + * Please Place Description here. + * @var mac_ax_ops::sr_update + * Please Place Description here. + * @var mac_ax_ops::two_nav_cfg + * Please Place Description here. + * @var mac_ax_ops::pkt_drop + * Please Place Description here. + * @var mac_ax_ops::send_bcn_h2c + * Please Place Description here. + * @var mac_ax_ops::tx_mode_sel + * Please Place Description here. + * @var mac_ax_ops::tcpip_chksum_ofd + * Please Place Description here. + * @var mac_ax_ops::chk_rx_tcpip_chksum_ofd + * Please Place Description here. + * @var mac_ax_ops::chk_allq_empty + * Please Place Description here. + * @var mac_ax_ops::is_txq_empty + * Please Place Description here. + * @var mac_ax_ops::is_rxq_empty + * Please Place Description here. + * @var mac_ax_ops::parse_bcn_stats_c2h + * Please Place Description here. + * @var mac_ax_ops::upd_mudecision_para + * Please Place Description here. + * @var mac_ax_ops::mu_sta_upd + * Please Place Description here. + * @var mac_ax_ops::upd_ul_fixinfo + * Please Place Description here. + * @var mac_ax_ops::f2p_test_cmd + * Please Place Description here. + * @var mac_ax_ops::snd_test_cmd + * Please Place Description here. + * @var mac_ax_ops::set_fw_fixmode + * Please Place Description here. + * @var mac_ax_ops::mac_dumpwlanc + * Please Place Description here. + * @var mac_ax_ops::mac_dumpwlans + * Please Place Description here. + * @var mac_ax_ops::mac_dumpwland + * Please Place Description here. + * @var mac_ax_ops::outsrc_h2c_common + * Please Place Description here. + * @var mac_ax_ops::read_pwr_reg + * Please Place Description here. + * @var mac_ax_ops::write_pwr_reg + * Please Place Description here. + * @var mac_ax_ops::write_msk_pwr_reg + * Please Place Description here. + * @var mac_ax_ops::write_pwr_ofst_mode + * Please Place Description here. + * @var mac_ax_ops::write_pwr_ofst_bw + * Please Place Description here. + * @var mac_ax_ops::write_pwr_ref_reg + * Please Place Description here. + * @var mac_ax_ops::write_pwr_limit_en + * Please Place Description here. + * @var mac_ax_ops::write_pwr_limit_rua_reg + * Please Place Description here. + * @var mac_ax_ops::write_pwr_limit_reg + * Please Place Description here. + * @var mac_ax_ops::write_pwr_by_rate_reg + * Please Place Description here. + * @var mac_ax_ops::lamode_cfg + * Please Place Description here. + * @var mac_ax_ops::lamode_trigger + * Please Place Description here. + * @var mac_ax_ops::lamode_buf_cfg + * Please Place Description here. + * @var mac_ax_ops::get_lamode_st + * Please Place Description here. + * @var mac_ax_ops::read_xcap_reg + * Please Place Description here. + * @var mac_ax_ops::write_xcap_reg + * Please Place Description here. + * @var mac_ax_ops::write_bbrst_reg + * Please Place Description here. + * @var mac_ax_ops::get_csi_buffer_index + * Please Place Description here. + * @var mac_ax_ops::set_csi_buffer_index + * Please Place Description here. + * @var mac_ax_ops::get_snd_sts_index + * Please Place Description here. + * @var mac_ax_ops::set_snd_sts_index + * Please Place Description here. + * @var mac_ax_ops::init_snd_mer + * Please Place Description here. + * @var mac_ax_ops::init_snd_mee + * Please Place Description here. + * @var mac_ax_ops::csi_force_rate + * Please Place Description here. + * @var mac_ax_ops::csi_rrsc + * Please Place Description here. + * @var mac_ax_ops::set_snd_para + * Please Place Description here. + * @var mac_ax_ops::set_csi_para_reg + * Please Place Description here. + * @var mac_ax_ops::set_csi_para_cctl + * Please Place Description here. + * @var mac_ax_ops::hw_snd_pause_release + * Please Place Description here. + * @var mac_ax_ops::bypass_snd_sts + * Please Place Description here. + * @var mac_ax_ops::deinit_mee + * Please Place Description here. + * @var mac_ax_ops::cfg_lps + * Please Place Description here. + * @var mac_ax_ops::ps_pwr_state + * Please Place Description here. + * @var mac_ax_ops::chk_leave_lps + * Please Place Description here. + * @var mac_ax_ops::cfg_ips + * Please Place Description here. + * @var mac_ax_ops::chk_leave_ips + * Please Place Description here. + * @var mac_ax_ops::lps_chk_access + * Please Place Description here. + * @var mac_ax_ops::cfg_wow_wake + * Please Place Description here. + * @var mac_ax_ops::cfg_disconnect_det + * Please Place Description here. + * @var mac_ax_ops::cfg_keepalive + * Please Place Description here. + * @var mac_ax_ops::cfg_gtk_ofld + * Please Place Description here. + * @var mac_ax_ops::cfg_arp_ofld + * Please Place Description here. + * @var mac_ax_ops::cfg_ndp_ofld + * Please Place Description here. + * @var mac_ax_ops::cfg_realwow + * Please Place Description here. + * @var mac_ax_ops::cfg_nlo + * Please Place Description here. + * @var mac_ax_ops::cfg_dev2hst_gpio + * Please Place Description here. + * @var mac_ax_ops::cfg_uphy_ctrl + * Please Place Description here. + * @var mac_ax_ops::cfg_wowcam_upd + * Please Place Description here. + * @var mac_ax_ops::cfg_wow_sleep + * Please Place Description here. + * @var mac_ax_ops::get_wow_fw_status + * Please Place Description here. + * @var mac_ax_ops::request_aoac_report + * Please Place Description here. + * @var mac_ax_ops::read_aoac_report + * Please Place Description here. + * @var mac_ax_ops::check_aoac_report_done + * Please Place Description here. + * @var mac_ax_ops::dbcc_enable + * Please Place Description here. + * @var mac_ax_ops::port_cfg + * Please Place Description here. + * @var mac_ax_ops::port_init + * Please Place Description here. + * @var mac_ax_ops::enable_imr + * Please Place Description here. + * @var mac_ax_ops::dump_efuse_map_wl + * Please Place Description here. + * @var mac_ax_ops::dump_efuse_map_bt + * Please Place Description here. + * @var mac_ax_ops::write_efuse + * Please Place Description here. + * @var mac_ax_ops::read_efuse + * Please Place Description here. + * @var mac_ax_ops::get_efuse_avl_size + * Please Place Description here. + * @var mac_ax_ops::get_efuse_avl_size_bt + * Please Place Description here. + * @var mac_ax_ops::dump_log_efuse + * Please Place Description here. + * @var mac_ax_ops::read_log_efuse + * Please Place Description here. + * @var mac_ax_ops::write_log_efuse + * Please Place Description here. + * @var mac_ax_ops::dump_log_efuse_bt + * Please Place Description here. + * @var mac_ax_ops::read_log_efuse_bt + * Please Place Description here. + * @var mac_ax_ops::write_log_efuse_bt + * Please Place Description here. + * @var mac_ax_ops::pg_efuse_by_map + * Please Place Description here. + * @var mac_ax_ops::pg_efuse_by_map_bt + * Please Place Description here. + * @var mac_ax_ops::mask_log_efuse + * Please Place Description here. + * @var mac_ax_ops::pg_sec_data_by_map + * Please Place Description here. + * @var mac_ax_ops::cmp_sec_data_by_map + * Please Place Description here. + * @var mac_ax_ops::get_efuse_info + * Please Place Description here. + * @var mac_ax_ops::set_efuse_info + * Please Place Description here. + * @var mac_ax_ops::read_hidden_rpt + * Please Place Description here. + * @var mac_ax_ops::check_efuse_autoload + * Please Place Description here. + * @var mac_ax_ops::pg_simulator + * Please Place Description here. + * @var mac_ax_ops::checksum_update + * Please Place Description here. + * @var mac_ax_ops::checksum_rpt + * Please Place Description here. + * @var mac_ax_ops::set_efuse_ctrl + * Please Place Description here. + * @var mac_ax_ops::otp_test + * Please Place Description here. + * @var mac_ax_ops::get_mac_ft_status + * Please Place Description here. + * @var mac_ax_ops::fw_log_cfg + * Please Place Description here. + * @var mac_ax_ops::pinmux_set_func + * Please Place Description here. + * @var mac_ax_ops::pinmux_free_func + * Please Place Description here. + * @var mac_ax_ops::sel_uart_tx_pin + * Please Place Description here. + * @var mac_ax_ops::sel_uart_rx_pin + * Please Place Description here. + * @var mac_ax_ops::set_gpio_func + * Please Place Description here. + * @var mac_ax_ops::get_hw_info + * Please Place Description here. + * @var mac_ax_ops::set_hw_value + * Please Place Description here. + * @var mac_ax_ops::get_hw_value + * Please Place Description here. + * @var mac_ax_ops::get_err_status + * Please Place Description here. + * @var mac_ax_ops::set_err_status + * Please Place Description here. + * @var mac_ax_ops::general_pkt_ids + * Please Place Description here. + * @var mac_ax_ops::coex_init + * Please Place Description here. + * @var mac_ax_ops::coex_read + * Please Place Description here. + * @var mac_ax_ops::coex_write + * Please Place Description here. + * @var mac_ax_ops::trigger_cmac_err + * Please Place Description here. + * @var mac_ax_ops::trigger_cmac1_err + * Please Place Description here. + * @var mac_ax_ops::trigger_dmac_err + * Please Place Description here. + * @var mac_ax_ops::tsf_sync + * Please Place Description here. + * @var mac_ax_ops::reset_mcc_group + * Please Place Description here. + * @var mac_ax_ops::reset_mcc_request + * Please Place Description here. + * @var mac_ax_ops::add_mcc + * Please Place Description here. + * @var mac_ax_ops::start_mcc + * Please Place Description here. + * @var mac_ax_ops::stop_mcc + * Please Place Description here. + * @var mac_ax_ops::del_mcc_group + * Please Place Description here. + * @var mac_ax_ops::mcc_request_tsf + * Please Place Description here. + * @var mac_ax_ops::mcc_macid_bitmap + * Please Place Description here. + * @var mac_ax_ops::mcc_sync_enable + * Please Place Description here. + * @var mac_ax_ops::mcc_set_duration + * Please Place Description here. + * @var mac_ax_ops::get_mcc_tsf_rpt + * Please Place Description here. + * @var mac_ax_ops::get_mcc_status_rpt + * Please Place Description here. + * @var mac_ax_ops::check_add_mcc_done + * Please Place Description here. + * @var mac_ax_ops::check_start_mcc_done + * Please Place Description here. + * @var mac_ax_ops::check_stop_mcc_done + * Please Place Description here. + * @var mac_ax_ops::check_del_mcc_group_done + * Please Place Description here. + * @var mac_ax_ops::check_mcc_request_tsf_done + * Please Place Description here. + * @var mac_ax_ops::check_mcc_macid_bitmap_done + * Please Place Description here. + * @var mac_ax_ops::check_mcc_sync_enable_done + * Please Place Description here. + * @var mac_ax_ops::check_mcc_set_duration_done + * Please Place Description here. + * @var mac_ax_ops::check_access + * Please Place Description here. + * @var mac_ax_ops::set_led_mode + * Please Place Description here. + * @var mac_ax_ops::led_ctrl + * Please Place Description here. + * @var mac_ax_ops::set_sw_gpio_mode + * Please Place Description here. + * @var mac_ax_ops::sw_gpio_ctrl + * Please Place Description here. + * @var mac_ax_ops::fwcmd_lb + * Please Place Description here. + * @var mac_ax_ops::mem_dump + * Please Place Description here. + * @var mac_ax_ops::get_mem_size + * Please Place Description here. + * @var mac_ax_ops::dbg_status_dump + * Please Place Description here. + * @var mac_ax_ops::reg_dump + * Please Place Description here. + * @var mac_ax_ops::rx_cnt + * Please Place Description here. + * @var mac_ax_ops::dump_fw_rsvd_ple + * Please Place Description here. + * @var mac_ax_ops::fw_dbg_dump + * Please Place Description here. + * @var mac_ax_ops::event_notify + * Please Place Description here. + * @var mac_ax_ops::ram_boot + * Please Place Description here. + * @var mac_ax_ops::clear_write_request + * Please Place Description here. + * @var mac_ax_ops::add_write_request + * Please Place Description here. + * @var mac_ax_ops::write_ofld + * Please Place Description here. + * @var mac_ax_ops::clear_conf_request + * Please Place Description here. + * @var mac_ax_ops::add_conf_request + * Please Place Description here. + * @var mac_ax_ops::conf_ofld + * Please Place Description here. + * @var mac_ax_ops::clear_read_request + * Please Place Description here. + * @var mac_ax_ops::add_read_request + * Please Place Description here. + * @var mac_ax_ops::read_ofld + * Please Place Description here. + * @var mac_ax_ops::read_ofld_value + * Please Place Description here. + * @var mac_ax_ops::get_fw_status + * Please Place Description here. + */ +struct mac_ax_ops { + struct mac_ax_intf_ops *intf_ops; + /*System level*/ + u32 (*hal_init)(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info); + u32 (*hal_fast_init)(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *trx_info, + struct mac_ax_fwdl_info *fwdl_info, + struct mac_ax_intf_info *intf_info); + u32 (*hal_deinit)(struct mac_ax_adapter *adapter); + u32 (*hal_fast_deinit)(struct mac_ax_adapter *adapter); + u32 (*add_role)(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info); + u32 (*remove_role)(struct mac_ax_adapter *adapter, u8 macid); + u32 (*change_role)(struct mac_ax_adapter *adapter, + struct mac_ax_role_info *info); + u32 (*pwr_switch)(struct mac_ax_adapter *adapter, u8 on); + u32 (*sys_init)(struct mac_ax_adapter *adapter); + u32 (*trx_init)(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info); + u32 (*romdl)(struct mac_ax_adapter *adapter, u8 *rom, u32 romaddr, + u32 len); + u32 (*enable_cpu)(struct mac_ax_adapter *adapter, + u8 boot_reason, u8 dlfw); + u32 (*disable_cpu)(struct mac_ax_adapter *adapter); + u32 (*fwredl)(struct mac_ax_adapter *adapter, u8 *fw, u32 len); + u32 (*fwdl)(struct mac_ax_adapter *adapter, u8 *fw, u32 len); + u32 (*enable_fw)(struct mac_ax_adapter *adapter, + enum rtw_fw_type cat); + u32 (*lv1_rcvy)(struct mac_ax_adapter *adapter, + enum mac_ax_lv1_rcvy_step step); + u32 (*get_macaddr)(struct mac_ax_adapter *adapter, + struct mac_ax_macaddr *macaddr, + u8 role_idx); + u32 (*build_txdesc)(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len); + u32 (*refill_txdesc)(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *txpkt_info, + struct mac_ax_refill_info *mask, + struct mac_ax_refill_info *info); + u32 (*parse_rxdesc)(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len); + u32 (*watchdog)(struct mac_ax_adapter *adapter); + /*FW offload related*/ + u32 (*reset_fwofld_state)(struct mac_ax_adapter *adapter, u8 op); + u32 (*check_fwofld_done)(struct mac_ax_adapter *adapter, u8 op); + u32 (*read_pkt_ofld)(struct mac_ax_adapter *adapter, u8 id); + u32 (*del_pkt_ofld)(struct mac_ax_adapter *adapter, u8 id); + u32 (*add_pkt_ofld)(struct mac_ax_adapter *adapter, u8 *pkt, + u16 len, u8 *id); + u32 (*pkt_ofld_packet)(struct mac_ax_adapter *adapter, + u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id); + u32 (*dump_efuse_ofld)(struct mac_ax_adapter *adapter, u32 efuse_size, + bool is_hidden); + u32 (*efuse_ofld_map)(struct mac_ax_adapter *adapter, u8 *efuse_map, + u32 efuse_size); + u32 (*upd_dctl_info)(struct mac_ax_adapter *adapter, + struct mac_ax_dctl_info *info, + struct mac_ax_dctl_info *mask, u8 macid, + u8 operation); + u32 (*upd_cctl_info)(struct mac_ax_adapter *adapter, + struct mac_ax_cctl_info *info, + struct mac_ax_cctl_info *mask, u8 macid, + u8 operation); + u32 (*ie_cam_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_ie_cam_cmd_info *info); + u32 (*twt_info_upd_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_twt_para *info); + u32 (*twt_act_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_twtact_para *info); + u32 (*twt_anno_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_twtanno_para *info); + void (*twt_wait_anno)(struct mac_ax_adapter *adapter, + u8 *c2h_content, u8 *upd_addr); + u32 (*mac_host_getpkt_h2c)(struct mac_ax_adapter *adapter, + u8 macid, u8 pkttype); + u32 (*p2p_act_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_act_info *info); + u32 (*p2p_macid_ctrl_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_p2p_macid_info *info); + u32 (*get_p2p_stat)(struct mac_ax_adapter *adapter); + u32 (*tsf32_togl_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_info *info); + u32 (*get_t32_togl_rpt)(struct mac_ax_adapter *adapter, + struct mac_ax_t32_togl_rpt *ret_rpt); + u32 (*ccxrpt_parsing)(struct mac_ax_adapter *adapter, + u8 *buf, struct mac_ax_ccxrpt *info); + /*Association, de-association related*/ + u32 (*sta_add_key)(struct mac_ax_adapter *adapter, + struct mac_ax_sec_cam_info *sec_cam_content, + u8 mac_id, u8 key_id, u8 key_type); + u32 (*sta_del_key)(struct mac_ax_adapter *adapter, + u8 mac_id, u8 key_id, u8 key_type); + u32 (*sta_search_key_idx)(struct mac_ax_adapter *adapter, + u8 mac_id, u8 key_id, u8 key_type); + u32 (*sta_hw_security_support)(struct mac_ax_adapter *adapter, + u8 hw_security_support_type, u8 enable); + u32 (*sta_keycam_backup)(struct mac_ax_adapter *adapter, + u8 op_mode); + u32 (*set_mu_table)(struct mac_ax_adapter *adapter, + struct mac_mu_table *mu_table); + u32 (*ss_dl_grp_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_ss_dl_grp_upd *info); + u32 (*ss_ul_grp_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_grp_upd *info); + u32 (*ss_ul_sta_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_ss_ul_sta_upd *info); + u32 (*bacam_info)(struct mac_ax_adapter *adapter, + struct mac_ax_bacam_info *info); + /*TRX related*/ + u32 (*txdesc_len)(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info); + u32 (*upd_shcut_mhdr)(struct mac_ax_adapter *adapter, + struct mac_ax_shcut_mhdr *info, u8 macid); + u32 (*enable_hwmasdu)(struct mac_ax_adapter *adapter, + u8 enable, + enum mac_ax_amsdu_pkt_num max_num, + u8 en_single_amsdu, + u8 en_last_amsdu_padding); + u32 (*enable_cut_hwamsdu)(struct mac_ax_adapter *adapter, + u8 enable, + u8 low_th, + u16 high_th, + enum mac_ax_ex_shift aligned); + u32 (*hdr_conv)(struct mac_ax_adapter *adapter, + u8 en_hdr_conv); + u32 (*set_hwseq_reg)(struct mac_ax_adapter *adapter, + u8 reg_seq_idx, + u16 reg_seq_val); + u32 (*process_c2h)(struct mac_ax_adapter *adapter, u8 *buf, u32 len, + u8 *ret); + u32 (*parse_dfs)(struct mac_ax_adapter *adapter, + u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt); + u32 (*parse_ppdu)(struct mac_ax_adapter *adapter, + u8 *buf, u32 ppdu_len, u8 mac_info, + struct mac_ax_ppdu_rpt *rpt); + u32 (*cfg_phy_rpt)(struct mac_ax_adapter *adapter, + struct mac_ax_phy_rpt_cfg *cfg); + u32 (*set_rx_forwarding)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p); + u32 (*get_rx_fltr_opt)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *opt, + enum mac_ax_band band); + u32 (*set_rx_fltr_opt)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_fltr_ctrl_t *opt, + struct mac_ax_rx_fltr_ctrl_t *opt_msk, + enum mac_ax_band band); + u32 (*set_rx_fltr_typ_opt)(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band); + u32 (*set_rx_fltr_typstyp_opt)(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + u8 subtype, + enum mac_ax_fwd_target fwd_target, + enum mac_ax_band band); + u32 (*set_typsbtyp_fltr_detail)(struct mac_ax_adapter *adapter, + enum mac_ax_pkt_t type, + struct mac_ax_rx_fltr_elem *elem, + enum mac_ax_band band); + u32 (*get_cfg_addr_cam)(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *opt, + enum mac_ax_band band); + u32 (*get_cfg_addr_cam_dis)(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *opt, + enum mac_ax_band band); + u32 (*cfg_addr_cam)(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_ctrl_t *ctl_opt, + struct mac_ax_addrcam_ctrl_t *ctl_msk, + enum mac_ax_band band); + u32 (*cfg_addr_cam_dis)(struct mac_ax_adapter *adapter, + struct mac_ax_addrcam_dis_ctrl_t *ctl_opt, + struct mac_ax_addrcam_dis_ctrl_t *ctl_msk, + enum mac_ax_band band); + u32 (*sr_update)(struct mac_ax_adapter *adapter, + struct mac_ax_sr_info *sr_info, + enum mac_ax_band band); + u32 (*two_nav_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_2nav_info *info); + u32 (*pkt_drop)(struct mac_ax_adapter *adapter, + struct mac_ax_pkt_drop_info *info); + u32 (*send_bcn_h2c)(struct mac_ax_adapter *adapter, + struct mac_ax_bcn_info *info); + u32 (*tx_mode_sel)(struct mac_ax_adapter *adapter, + struct mac_ax_mac_tx_mode_sel *mode_sel); + u32 (*tcpip_chksum_ofd)(struct mac_ax_adapter *adapter, + u8 en_tx_chksum_ofd, + u8 en_rx_chksum_ofd); + u32 (*chk_rx_tcpip_chksum_ofd)(struct mac_ax_adapter *adapter, + u8 chksum_status); + u32 (*chk_allq_empty)(struct mac_ax_adapter *adapter, u8 *empty); + u32 (*is_txq_empty)(struct mac_ax_adapter *adapter, + struct mac_ax_tx_queue_empty *val); + u32 (*is_rxq_empty)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_queue_empty *val); + u32 (*parse_bcn_stats_c2h)(struct mac_ax_adapter *adapter, + u8 *content, + struct mac_ax_bcn_cnt *val); + u32 (*tx_idle_poll)(struct mac_ax_adapter *adapter, + struct mac_ax_tx_idle_poll_cfg *poll_cfg); + u32 (*sifs_chk_cca_en)(struct mac_ax_adapter *adapter, + u8 band); + u32 (*patch_rx_rate)(struct mac_ax_adapter *adapter, + struct rtw_r_meta_data *info); + /*frame exchange related*/ + u32 (*upd_mudecision_para)(struct mac_ax_adapter *adapter, + struct mac_ax_mudecision_para *info); + u32 (*mu_sta_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_mu_sta_upd *info); + u32 (*upd_ul_fixinfo)(struct mac_ax_adapter *adapter, + struct mac_ax_ul_fixinfo *info); + u32 (*f2p_test_cmd)(struct mac_ax_adapter *adapter, + struct mac_ax_f2p_test_para *info, + struct mac_ax_f2p_wd *f2pwd, + struct mac_ax_f2p_tx_cmd *ptxcmd, + u8 *psigb_addr); + u32 (*snd_test_cmd)(struct mac_ax_adapter *adapter, + u8 *cmd_buf); + u32 (*set_fw_fixmode)(struct mac_ax_adapter *adapter, + struct mac_ax_fixmode_para *info); + u32 (*mac_dumpwlanc)(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwlanc *para); + u32 (*mac_dumpwlans)(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwlans *para); + u32 (*mac_dumpwland)(struct mac_ax_adapter *adapter, + struct mac_ax_dumpwland *para); + /*outsrcing related */ + u32 (*outsrc_h2c_common)(struct mac_ax_adapter *adapter, + struct rtw_g6_h2c_hdr *hdr, + u32 *pvalue); + u32 (*read_pwr_reg)(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 *val); + u32 (*write_pwr_reg)(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 val); + u32 (*write_msk_pwr_reg)(struct mac_ax_adapter *adapter, u8 band, + const u32 offset, u32 mask, u32 val); + u32 (*write_pwr_ofst_mode)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); + u32 (*write_pwr_ofst_bw)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); + u32 (*write_pwr_ref_reg)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); + u32 (*write_pwr_limit_en)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); + u32 (*write_pwr_limit_rua_reg)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_info *tpu); + u32 (*write_pwr_limit_reg)(struct mac_ax_adapter *adapter, + u8 band, struct rtw_tpu_pwr_imt_info *tpu); + u32 (*write_pwr_by_rate_reg)(struct mac_ax_adapter *adapter, + u8 band, + struct rtw_tpu_pwr_by_rate_info *tpu); + u32 (*lamode_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_la_cfg *cfg); + u32 (*lamode_trigger)(struct mac_ax_adapter *adapter, u8 tgr); + u32 (*lamode_buf_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_la_buf_param *param); + struct mac_ax_la_status (*get_lamode_st) + (struct mac_ax_adapter *adapter); + u32 (*read_xcap_reg)(struct mac_ax_adapter *adapter, u8 sc_xo, + u32 *val); + u32 (*write_xcap_reg)(struct mac_ax_adapter *adapter, u8 sc_xo, + u32 val); + u32 (*write_bbrst_reg)(struct mac_ax_adapter *adapter, u8 val); + /*sounding related*/ + u32 (*get_csi_buffer_index)(struct mac_ax_adapter *adapter, u8 band, + u8 csi_buffer_id); + u32 (*set_csi_buffer_index)(struct mac_ax_adapter *adapter, u8 band, + u8 macid, u16 csi_buffer_id, + u16 buffer_idx); + u32 (*get_snd_sts_index)(struct mac_ax_adapter *adapter, u8 band, + u8 index); + u32 (*set_snd_sts_index)(struct mac_ax_adapter *adapter, u8 band, + u8 macid, u8 index); + u32 (*init_snd_mer)(struct mac_ax_adapter *adapter, u8 band); + u32 (*init_snd_mee)(struct mac_ax_adapter *adapter, u8 band); + u32 (*csi_force_rate)(struct mac_ax_adapter *adapter, u8 band, + u8 ht_rate, u8 vht_rate, u8 he_rate); + u32 (*csi_rrsc)(struct mac_ax_adapter *adapter, u8 band, u32 rrsc); + u32 (*set_snd_para)(struct mac_ax_adapter *adapter, + struct mac_ax_fwcmd_snd *snd_info); + u32 (*set_csi_para_reg)(struct mac_ax_adapter *adapter, + struct mac_reg_csi_para *csi_para); + u32 (*set_csi_para_cctl)(struct mac_ax_adapter *adapter, + struct mac_cctl_csi_para *csi_para); + u32 (*hw_snd_pause_release)(struct mac_ax_adapter *adapter, + u8 band, u8 pr); + u32 (*bypass_snd_sts)(struct mac_ax_adapter *adapter); + u32 (*deinit_mee)(struct mac_ax_adapter *adapter, u8 band); + u32 (*snd_sup)(struct mac_ax_adapter *adapter, + struct mac_bf_sup *bf_sup); + u32 (*gidpos)(struct mac_ax_adapter *adapter, + struct mac_gid_pos *mu_gid); + /*lps related*/ + u32 (*cfg_lps)(struct mac_ax_adapter *adapter, + u8 macid, + enum mac_ax_ps_mode ps_mode, + struct mac_ax_lps_info *lps_info); + u32 (*ps_pwr_state)(struct mac_ax_adapter *adapter, + enum mac_ax_pwr_state_action action, + enum mac_ax_rpwm_req_pwr_state req_pwr_state); + u32 (*chk_leave_lps)(struct mac_ax_adapter *adapter, u8 macid); + u32 (*cfg_ips)(struct mac_ax_adapter *adapter, + u8 macid, + u8 enable); + u32 (*chk_leave_ips)(struct mac_ax_adapter *adapter, u8 macid); + u32 (*ps_notify_wake)(struct mac_ax_adapter *adapter); + u32 (*cfg_ps_advance_parm)(struct mac_ax_adapter *adapter, + struct mac_ax_ps_adv_parm *parm); + /*Wowlan related*/ + u32 (*cfg_wow_wake)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_wow_wake_info *info, + struct mac_ax_remotectrl_info_parm_ *content); + u32 (*cfg_disconnect_det)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_disconnect_det_info *info); + u32 (*cfg_keepalive)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_keep_alive_info *info); + u32 (*cfg_gtk_ofld)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_gtk_ofld_info *info, + struct mac_ax_gtk_info_parm_ *content); + u32 (*cfg_arp_ofld)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_arp_ofld_info *info, + void *parp_info_content); + u32 (*cfg_ndp_ofld)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_ndp_ofld_info *info, + struct mac_ax_ndp_info_parm_ *content); + u32 (*cfg_realwow)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_realwow_info *info, + struct mac_ax_realwowv2_info_parm_ *content); + u32 (*cfg_nlo)(struct mac_ax_adapter *adapter, + u8 macid, + struct mac_ax_nlo_info *info, + struct mac_ax_nlo_networklist_parm_ *content); + u32 (*cfg_dev2hst_gpio)(struct mac_ax_adapter *adapter, + struct mac_ax_dev2hst_gpio_info *parm); + u32 (*cfg_uphy_ctrl)(struct mac_ax_adapter *adapter, + struct mac_ax_uphy_ctrl_info *info); + u32 (*cfg_wowcam_upd)(struct mac_ax_adapter *adapter, + struct mac_ax_wowcam_upd_info *info); + u32 (*get_wow_wake_rsn)(struct mac_ax_adapter *adapter, u8 *wake_rsn, + u8 *reset); + u32 (*cfg_wow_sleep)(struct mac_ax_adapter *adapter, + u8 sleep); + u32 (*get_wow_fw_status)(struct mac_ax_adapter *adapter, + u8 *status, u8 func_en); + u32 (*request_aoac_report)(struct mac_ax_adapter *adapter, + u8 rx_ready); + u32 (*read_aoac_report)(struct mac_ax_adapter *adapter, + struct mac_ax_aoac_report *rpt_buf, u8 rx_ready); + u32 (*check_aoac_report_done)(struct mac_ax_adapter *adapter); + u32 (*wow_stop_trx)(struct mac_ax_adapter *adapter); + /*system related*/ + u32 (*dbcc_enable)(struct mac_ax_adapter *adapter, + struct mac_ax_trx_info *info, u8 dbcc_en); + u32 (*dbcc_move_macid)(struct mac_ax_adapter *adapter, + u8 macid, u8 dbcc_en); + u32 (*port_cfg)(struct mac_ax_adapter *adapter, + enum mac_ax_port_cfg_type type, + struct mac_ax_port_cfg_para *para); + u32 (*port_init)(struct mac_ax_adapter *adapter, + struct mac_ax_port_init_para *para); + u32 (*enable_imr)(struct mac_ax_adapter *adapter, u8 band, + enum mac_ax_hwmod_sel sel); + u32 (*dump_efuse_map_wl)(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map); + u32 (*dump_efuse_map_bt)(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map); + u32 (*write_efuse)(struct mac_ax_adapter *adapter, u32 addr, u8 val, + enum mac_ax_efuse_bank bank); + u32 (*read_efuse)(struct mac_ax_adapter *adapter, u32 addr, u32 size, + u8 *val, enum mac_ax_efuse_bank bank); + u32 (*get_efuse_avl_size)(struct mac_ax_adapter *adapter, u32 *size); + u32 (*get_efuse_avl_size_bt)(struct mac_ax_adapter *adapter, u32 *size); + u32 (*dump_log_efuse)(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map, bool is_limit); + u32 (*read_log_efuse)(struct mac_ax_adapter *adapter, u32 addr, + u32 size, u8 *val); + u32 (*write_log_efuse)(struct mac_ax_adapter *adapter, u32 addr, + u8 val); + u32 (*dump_log_efuse_bt)(struct mac_ax_adapter *adapter, + enum mac_ax_efuse_parser_cfg parser_cfg, + enum mac_ax_efuse_read_cfg cfg, + u8 *efuse_map); + u32 (*read_log_efuse_bt)(struct mac_ax_adapter *adapter, u32 addr, + u32 size, u8 *val); + u32 (*write_log_efuse_bt)(struct mac_ax_adapter *adapter, u32 addr, + u8 val); + u32 (*pg_efuse_by_map)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg, + bool part, bool is_limit); + u32 (*pg_efuse_by_map_bt)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, + enum mac_ax_efuse_read_cfg cfg); + u32 (*mask_log_efuse)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); + u32 (*pg_sec_data_by_map)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); + u32 (*cmp_sec_data_by_map)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info); + u32 (*get_efuse_info)(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, + u32 length, u8 *autoload_status); + u32 (*set_efuse_info)(struct mac_ax_adapter *adapter, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length); + u32 (*read_hidden_rpt)(struct mac_ax_adapter *adapter, + struct mac_defeature_value *rpt); + u32 (*check_efuse_autoload)(struct mac_ax_adapter *adapter, + u8 *autoload_status); + u32 (*pg_simulator)(struct mac_ax_adapter *adapter, + struct mac_ax_pg_efuse_info *info, u8 *phy_map); + u32 (*checksum_update)(struct mac_ax_adapter *adapter); + u32 (*checksum_rpt)(struct mac_ax_adapter *adapter, u16 *chksum); + u32 (*disable_rf)(struct mac_ax_adapter *adapter, + enum mac_ax_disable_rf_func func, + enum mac_ax_net_type type); + void (*set_efuse_ctrl)(struct mac_ax_adapter *adapter, u8 is_secure); + u32 (*otp_test)(struct mac_ax_adapter *adapter, bool is_OTP_test); + u32 (*get_mac_ft_status)(struct mac_ax_adapter *adapter, + enum mac_ax_feature mac_ft, + enum mac_ax_status *stat, u8 *buf, + const u32 size, u32 *ret_size); + u32 (*fw_log_cfg)(struct mac_ax_adapter *adapter, + struct mac_ax_fw_log *log_cfg); + u32 (*pinmux_set_func)(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func); + u32 (*pinmux_free_func)(struct mac_ax_adapter *adapter, + enum mac_ax_gpio_func func); + u32 (*sel_uart_tx_pin)(struct mac_ax_adapter *adapter, + enum mac_ax_uart_tx_pin uart_pin); + u32 (*sel_uart_rx_pin)(struct mac_ax_adapter *adapter, + enum mac_ax_uart_rx_pin uart_pin); + u32 (*set_gpio_func)(struct mac_ax_adapter *adapter, + enum rtw_mac_gfunc func, s8 gpio); + struct mac_ax_hw_info* (*get_hw_info)(struct mac_ax_adapter *adapter); + u32 (*set_hw_value)(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *value); + u32 (*get_hw_value)(struct mac_ax_adapter *adapter, + enum mac_ax_hw_id hw_id, void *value); + u32 (*get_err_status)(struct mac_ax_adapter *adapter, + enum mac_ax_err_info *err); + u32 (*set_err_status)(struct mac_ax_adapter *adapter, + enum mac_ax_err_info err); + u32 (*general_pkt_ids)(struct mac_ax_adapter *adapter, + struct mac_ax_general_pkt_ids *ids); + u32 (*coex_init)(struct mac_ax_adapter *adapter, + struct mac_ax_coex *coex); + u32 (*coex_read)(struct mac_ax_adapter *adapter, + const u32 offset, u32 *val); + u32 (*coex_write)(struct mac_ax_adapter *adapter, + const u32 offset, const u32 val); + u32 (*trigger_cmac_err)(struct mac_ax_adapter *adapter); + u32 (*trigger_cmac1_err)(struct mac_ax_adapter *adapter); + u32 (*trigger_dmac_err)(struct mac_ax_adapter *adapter); + u32 (*tsf_sync)(struct mac_ax_adapter *adapter, u8 from_port, + u8 to_port, s32 sync_offset, + enum mac_ax_tsf_sync_act action); + u32 (*read_xtal_si)(struct mac_ax_adapter *adapter, u8 offset, u8 *val); + u32 (*write_xtal_si)(struct mac_ax_adapter *adapter, u8 offset, u8 val, + u8 bitmask); + u32 (*io_chk_access)(struct mac_ax_adapter *adapter, u32 offset); + u32 (*ser_ctrl)(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw); + /* mcc */ + u32 (*reset_mcc_group)(struct mac_ax_adapter *adapter, u8 group); + u32 (*reset_mcc_request)(struct mac_ax_adapter *adapter, u8 group); + u32 (*add_mcc)(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_role *info); + u32 (*start_mcc)(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_start *info); + u32 (*stop_mcc)(struct mac_ax_adapter *adapter, u8 group, u8 macid, + u8 prev_groups); + u32 (*del_mcc_group)(struct mac_ax_adapter *adapter, u8 group, + u8 prev_groups); + u32 (*mcc_request_tsf)(struct mac_ax_adapter *adapter, u8 group, + u8 macid_x, u8 macid_y); + u32 (*mcc_macid_bitmap)(struct mac_ax_adapter *adapter, u8 group, + u8 macid, u8 *bitmap, u8 len); + u32 (*mcc_sync_enable)(struct mac_ax_adapter *adapter, u8 group, + u8 source, u8 target, u8 offset); + u32 (*mcc_set_duration)(struct mac_ax_adapter *adapter, + struct mac_ax_mcc_duration_info *info); + u32 (*get_mcc_tsf_rpt)(struct mac_ax_adapter *adapter, u8 group, + u32 *tsf_x_high, u32 *tsf_x_low, + u32 *tsf_y_high, u32 *tsf_y_low); + u32 (*get_mcc_status_rpt)(struct mac_ax_adapter *adapter, u8 group, + u8 *status, u32 *tsf_high, u32 *tsf_low); + u32 (*get_mcc_group)(struct mac_ax_adapter *adapter, u8 *pget_group); + u32 (*check_add_mcc_done)(struct mac_ax_adapter *adapter, u8 group); + u32 (*check_start_mcc_done)(struct mac_ax_adapter *adapter, u8 group); + u32 (*check_stop_mcc_done)(struct mac_ax_adapter *adapter, u8 group); + u32 (*check_del_mcc_group_done)(struct mac_ax_adapter *adapter, + u8 group); + u32 (*check_mcc_request_tsf_done)(struct mac_ax_adapter *adapter, + u8 group); + u32 (*check_mcc_macid_bitmap_done)(struct mac_ax_adapter *adapter, + u8 group); + u32 (*check_mcc_sync_enable_done)(struct mac_ax_adapter *adapter, + u8 group); + u32 (*check_mcc_set_duration_done)(struct mac_ax_adapter *adapter, + u8 group); + /* not mcc */ + u32 (*check_access)(struct mac_ax_adapter *adapter, u32 offset); + u32 (*set_led_mode)(struct mac_ax_adapter *adapter, + enum mac_ax_led_mode mode, u8 led_id); + u32 (*led_ctrl)(struct mac_ax_adapter *adapter, u8 high, u8 led_id); + u32 (*set_sw_gpio_mode)(struct mac_ax_adapter *adapter, + enum rtw_gpio_mode mode, u8 gpio); + u32 (*sw_gpio_ctrl)(struct mac_ax_adapter *adapter, u8 high, u8 gpio); + u32 (*get_c2h_event)(struct mac_ax_adapter *adapter, + struct rtw_c2h_info *c2h, + enum phl_msg_evt_id *id, + u8 *c2h_info); + u32 (*cfg_wps)(struct mac_ax_adapter *adapter, + struct mac_ax_cfg_wps *wps); + u32 (*get_wl_dis_val)(struct mac_ax_adapter *adapter, u8 *val); +#if MAC_AX_FEATURE_DBGPKG + u32 (*fwcmd_lb)(struct mac_ax_adapter *adapter, u32 len, u8 burst); + u32 (*mem_dump)(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel, + u32 strt_addr, u8 *data, u32 size, u32 dbg_path); + u32 (*get_mem_size)(struct mac_ax_adapter *adapter, + enum mac_ax_mem_sel sel); + void (*dbg_status_dump)(struct mac_ax_adapter *adapter, + struct mac_ax_dbgpkg *val, + struct mac_ax_dbgpkg_en *en); + u32 (*reg_dump)(struct mac_ax_adapter *adapter, + enum mac_ax_reg_sel sel); + u32 (*rx_cnt)(struct mac_ax_adapter *adapter, + struct mac_ax_rx_cnt *rxcnt); + u32 (*dump_fw_rsvd_ple)(struct mac_ax_adapter *adapter, u8 **buf); + void (*dump_ple_dbg_page)(struct mac_ax_adapter *adapter, u8 page_num); + u32 (*fw_dbg_dump)(struct mac_ax_adapter *adapter, + u8 **buf, + struct mac_ax_fwdbg_en *en); + u32 (*event_notify)(struct mac_ax_adapter *adapter, + enum phl_msg_evt_id id, u8 band); + u32 (*dbgport_hw_set)(struct mac_ax_adapter *adapter, + struct mac_ax_dbgport_hw *dp_hw); +#endif +#if MAC_AX_FEATURE_HV + u32 (*ram_boot)(struct mac_ax_adapter *adapter, u8 *fw, u32 len); + /*fw offload related*/ + u32 (*clear_write_request)(struct mac_ax_adapter *adapter); + u32 (*add_write_request)(struct mac_ax_adapter *adapter, + struct mac_ax_write_req *req, + u8 *value, u8 *mask); + u32 (*write_ofld)(struct mac_ax_adapter *adapter); + u32 (*clear_conf_request)(struct mac_ax_adapter *adapter); + u32 (*add_conf_request)(struct mac_ax_adapter *adapter, + struct mac_ax_conf_ofld_req *req); + u32 (*conf_ofld)(struct mac_ax_adapter *adapter); + u32 (*clear_read_request)(struct mac_ax_adapter *adapter); + u32 (*add_read_request)(struct mac_ax_adapter *adapter, + struct mac_ax_read_req *req); + u32 (*read_ofld)(struct mac_ax_adapter *adapter); + u32 (*read_ofld_value)(struct mac_ax_adapter *adapter, + u8 **val_buf, u16 *val_len); +#endif + u32 (*add_cmd_ofld)(struct mac_ax_adapter *adapter, + struct rtw_mac_cmd *cmd); + /* flash related*/ + u32 (*flash_erase)(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u32 timeout); + u32 (*flash_read)(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout); + u32 (*flash_write)(struct mac_ax_adapter *adapter, + u32 addr, + u32 length, + u8 *buffer, + u32 timeout); + u32 (*fw_status_cmd)(struct mac_ax_adapter *adapter, + struct mac_ax_fwstatus_payload *info); + u32 (*fwc2h_ofdma_sts_parse)(struct mac_ax_adapter *adapter, + struct mac_ax_fwc2h_sts *fw_c2h_sts, + u32 *content); + u32 (*fw_ofdma_sts_en)(struct mac_ax_adapter *adapter, + struct mac_ax_fwsts_para *fwsts_para); + u32 (*tx_duty)(struct mac_ax_adapter *adapter, + u16 pause_intvl, u16 tx_intvl); + u32 (*tx_duty_stop)(struct mac_ax_adapter *adapter); +#if MAC_AX_FEATURE_DBGCMD + s32 (*halmac_cmd)(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len); + void (*halmac_cmd_parser)(struct mac_ax_adapter *adapter, + char input[][MAC_MAX_ARGV], u32 input_num, char *output, + u32 out_len); +#endif + /* FAST_CH_SW */ + u32 (*fast_ch_sw)(struct mac_ax_adapter *adapter, + struct mac_ax_fast_ch_sw_param *fast_ch_sw_param); + u32 (*fast_ch_sw_done)(struct mac_ax_adapter *adapter); + u32 (*get_fast_ch_sw_rpt)(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code); + u32 (*write_coex_mask)(struct mac_ax_adapter *adapter, + u32 offset, u32 mask, u32 val); + u32 (*fw_dbg_dle_cfg)(struct mac_ax_adapter *adapter, bool lock); + void (*h2c_agg_en)(struct mac_ax_adapter *adapter, u8 enable); + void (*h2c_agg_flush)(struct mac_ax_adapter *adapter); + u32 (*h2c_agg_tx)(struct mac_ax_adapter *adapter); +#if MAC_AX_FEATURE_DBGDEC + u32 (*fw_log_set_array)(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size); + u32 (*fw_log_unset_array)(struct mac_ax_adapter *adapter); +#endif + u32 (*get_fw_status)(struct mac_ax_adapter *adapter); + u32 (*add_scanofld_ch)(struct mac_ax_adapter *adapter, + struct mac_ax_scanofld_chinfo *chinfo, + u8 send_h2c, u8 clear_after_send); + u32 (*scanofld)(struct mac_ax_adapter *adapter, struct mac_ax_scanofld_param *scanParam); + u32 (*scanofld_fw_busy)(struct mac_ax_adapter *adapter); + u32 (*scanofld_chlist_busy)(struct mac_ax_adapter *adapter); + u32 (*role_sync)(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info); + u32 (*ch_switch_ofld)(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_parm parm); + u32 (*get_ch_switch_rpt)(struct mac_ax_adapter *adapter, struct mac_ax_ch_switch_rpt *rpt); +}; + +#endif diff --git a/phl/hal_g6/mac/mac_hw_info.h b/phl/hal_g6/mac/mac_hw_info.h new file mode 100644 index 0000000..0a7633a --- /dev/null +++ b/phl/hal_g6/mac/mac_hw_info.h @@ -0,0 +1,75 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __MAC_HW_INFO_H +#define __MAC_HW_INFO_H +/*--------------------Define -------------------------------------------*/ +/*--------------------Define MACRO--------------------------------------*/ +/*--------------------Define Enum---------------------------------------*/ +// TRX Desc related +// MAC_REG related +// F2P CMD related + +/** + * @enum mac_ax_snd_pkt_sel + * + * @brief mac_ax_snd_pkt_sel + * + * @var mac_ax_snd_pkt_sel::MAC_AX_UNICAST_NDPA + * Please Place Description here. + * @var mac_ax_snd_pkt_sel::MAC_AX_BROADCAST_NDPA + * Please Place Description here. + * @var mac_ax_snd_pkt_sel::MAC_AX_LAST_NDPA + * Please Place Description here. + * @var mac_ax_snd_pkt_sel::MAC_AX_MIDDLE_NDPA + * Please Place Description here. + * @var mac_ax_snd_pkt_sel::MAC_AX_BF_REPORT_POLL + * Please Place Description here. + * @var mac_ax_snd_pkt_sel::MAC_AX_FINAL_BFRP + * Please Place Description here. + */ +enum mac_ax_snd_pkt_sel { + MAC_AX_UNICAST_NDPA = 0, + MAC_AX_BROADCAST_NDPA = 1, + MAC_AX_LAST_NDPA = 2, + MAC_AX_MIDDLE_NDPA = 3, + MAC_AX_BF_REPORT_POLL = 4, + MAC_AX_FINAL_BFRP = 5, +}; + +/** + * @enum mac_ax_ndpa_pkt + * + * @brief mac_ax_ndpa_pkt + * + * @var mac_ax_ndpa_pkt::MAC_AX_NORMAL_PKT + * Please Place Description here. + * @var mac_ax_ndpa_pkt::MAC_AX_HT_PKT + * Please Place Description here. + * @var mac_ax_ndpa_pkt::MAC_AX_VHT_PKT + * Please Place Description here. + * @var mac_ax_ndpa_pkt::MAC_AX_HE_PKT + * Please Place Description here. + */ +enum mac_ax_ndpa_pkt { + MAC_AX_NORMAL_PKT = 0, + MAC_AX_HT_PKT = 1, + MAC_AX_VHT_PKT = 2, + MAC_AX_HE_PKT = 2, +}; + +/*--------------------Define Struct-------------------------------------*/ +#endif diff --git a/phl/hal_g6/mac/mac_reg.h b/phl/hal_g6/mac/mac_reg.h new file mode 100644 index 0000000..2d7b112 --- /dev/null +++ b/phl/hal_g6/mac/mac_reg.h @@ -0,0 +1,18433 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_MAC_REG_H +#define __INC_MAC_REG_H + +// +// WL_AX_REG_DMAC.xls +// + +// +// TOP_OFF +// + +#define R_AX_GT0_CTRL 0x8000 +#define B_AX_GT0_COUNT_EN BIT(31) +#define B_AX_GT0_MODE BIT(30) +#define B_AX_GT0_EN BIT(29) +#define B_AX_GT0_SORT_EN BIT(28) +#define B_AX_GT0_DATA_SH 0 +#define B_AX_GT0_DATA_MSK 0xfffffff + +#define R_AX_GT0_CNT 0x8004 +#define B_AX_GT0_CNT_SH 0 +#define B_AX_GT0_CNT_MSK 0x1fffffff + +#define R_AX_GT1_CTRL 0x8008 +#define B_AX_GT1_COUNT_EN BIT(31) +#define B_AX_GT1_MODE BIT(30) +#define B_AX_GT1_EN BIT(29) +#define B_AX_GT1_SORT_EN BIT(28) +#define B_AX_GT1_DATA_SH 0 +#define B_AX_GT1_DATA_MSK 0xfffffff + +#define R_AX_GT1_CNT 0x800C +#define B_AX_GT1_CNT_SH 0 +#define B_AX_GT1_CNT_MSK 0x1fffffff + +#define R_AX_GT2_CTRL 0x8010 +#define B_AX_GT2_COUNT_EN BIT(31) +#define B_AX_GT2_MODE BIT(30) +#define B_AX_GT2_EN BIT(29) +#define B_AX_GT2_SORT_EN BIT(28) +#define B_AX_GT2_DATA_SH 0 +#define B_AX_GT2_DATA_MSK 0xfffffff + +#define R_AX_GT2_CNT 0x8014 +#define B_AX_GT2_CNT_SH 0 +#define B_AX_GT2_CNT_MSK 0x1fffffff + +#define R_AX_GT3_CTRL 0x8018 +#define B_AX_GT3_COUNT_EN BIT(31) +#define B_AX_GT3_MODE BIT(30) +#define B_AX_GT3_EN BIT(29) +#define B_AX_GT3_SORT_EN BIT(28) +#define B_AX_GT3_DATA_SH 0 +#define B_AX_GT3_DATA_MSK 0xfffffff + +#define R_AX_GT3_CNT 0x801C +#define B_AX_GT3_CNT_SH 0 +#define B_AX_GT3_CNT_MSK 0x1fffffff + +#define R_AX_SORT_CTRL 0x8024 +#define B_AX_CMAC1_SORT_EN BIT(1) +#define B_AX_CMAC0_SORT_EN BIT(0) + +#define R_AX_PHYREG_SET 0x8040 +#define B_AX_PHYREG_SET_SH 0 +#define B_AX_PHYREG_SET_MSK 0xf + +#define R_AX_FWD0IMR 0x8100 +#define B_AX_FS_H2C_INT_EN BIT(8) +#define B_AX_FS_HIOE_ERR_INT_EN BIT(7) +#define B_AX_FS_SW_PLL_LEAVE_32K_INT_EN BIT(6) +#define B_AX_FS_MAILBOX_OUT_EMPTY_INT_EN BIT(5) +#define B_AX_FS_LTE_COEX_INT_EN BIT(4) +#define B_AX_FS_GT3_INT_EN BIT(3) +#define B_AX_FS_GT2_INT_EN BIT(2) +#define B_AX_FS_GT1_INT_EN BIT(1) +#define B_AX_FS_GT0_INT_EN BIT(0) + +#define R_AX_FWD0ISR 0x8104 +#define B_AX_FS_H2C_INT BIT(8) +#define B_AX_FS_HIOE_ERR_INT BIT(7) +#define B_AX_FS_SW_PLL_LEAVE_32K_INT BIT(6) +#define B_AX_FS_MAILBOX_OUT_EMPTY_INT BIT(5) +#define B_AX_FS_LTE_COEX_INT BIT(4) +#define B_AX_FS_GT3_INT BIT(3) +#define B_AX_FS_GT2_INT BIT(2) +#define B_AX_FS_GT1_INT BIT(1) +#define B_AX_FS_GT0_INT BIT(0) + +#define R_AX_HD0IMR 0x8110 +#define B_AX_WDT_PTFM_INT_EN BIT(5) +#define B_AX_CPWM_INT_EN BIT(2) +#define B_AX_GT3_INT_EN BIT(1) +#define B_AX_C2H_INT_EN BIT(0) + +#define R_AX_HD0ISR 0x8114 +#define B_AX_WDT_PTFM_INT BIT(5) +#define B_AX_CPWM_INT BIT(2) +#define B_AX_GT3_INT BIT(1) +#define B_AX_C2H_INT BIT(0) + +#define R_AX_H2CREG_DATA0 0x8140 +#define B_AX_H2CREG_D0_SH 0 +#define B_AX_H2CREG_D0_MSK 0xffffffffL + +#define R_AX_H2CREG_DATA1 0x8144 +#define B_AX_H2CREG_D1_SH 0 +#define B_AX_H2CREG_D1_MSK 0xffffffffL + +#define R_AX_H2CREG_DATA2 0x8148 +#define B_AX_H2CREG_D2_SH 0 +#define B_AX_H2CREG_D2_MSK 0xffffffffL + +#define R_AX_H2CREG_DATA3 0x814C +#define B_AX_H2CREG_D3_SH 0 +#define B_AX_H2CREG_D3_MSK 0xffffffffL + +#define R_AX_C2HREG_DATA0 0x8150 +#define B_AX_C2HREG_D0_SH 0 +#define B_AX_C2HREG_D0_MSK 0xffffffffL + +#define R_AX_C2HREG_DATA1 0x8154 +#define B_AX_C2HREG_D1_SH 0 +#define B_AX_C2HREG_D1_MSK 0xffffffffL + +#define R_AX_C2HREG_DATA2 0x8158 +#define B_AX_C2HREG_D2_SH 0 +#define B_AX_C2HREG_D2_MSK 0xffffffffL + +#define R_AX_C2HREG_DATA3 0x815C +#define B_AX_C2HREG_D3_SH 0 +#define B_AX_C2HREG_D3_MSK 0xffffffffL + +#define R_AX_H2CREG_CTRL 0x8160 +#define B_AX_H2CREG_TRIGGER BIT(0) + +#define R_AX_C2HREG_CTRL 0x8164 +#define B_AX_C2HREG_TRIGGER BIT(0) + +#define R_AX_CPWM 0x8170 +#define B_AX_CPWM_TOGGLE BIT(15) +#define B_AX_CPWM_VAL_SH 0 +#define B_AX_CPWM_VAL_MSK 0x7fff + +// +// 8852C TOP_OFF +// + +#define R_AX_GT0_CTRL_V1 0x7000 + +#define R_AX_GT0_CNT_V1 0x7004 + +#define R_AX_GT1_CTRL_V1 0x7008 + +#define R_AX_GT1_CNT_V1 0x700C + +#define R_AX_GT2_CTRL_V1 0x7010 + +#define R_AX_GT2_CNT_V1 0x7014 + +#define R_AX_GT3_CTRL_V1 0x7018 + +#define R_AX_GT3_CNT_V1 0x701C + +#define R_AX_SORT_CTRL_V1 0x7024 + +#define R_AX_PHYREG_SET_V1 0x7040 + +#define R_AX_FWD0IMR_V1 0x7100 + +#define R_AX_FWD0ISR_V1 0x7104 + +#define R_AX_HD0IMR_V1 0x7110 + +#define R_AX_HD0ISR_V1 0x7114 + +#define R_AX_H2CREG_DATA0_V1 0x7140 + +#define R_AX_H2CREG_DATA1_V1 0x7144 + +#define R_AX_H2CREG_DATA2_V1 0x7148 + +#define R_AX_H2CREG_DATA3_V1 0x714C + +#define R_AX_C2HREG_DATA0_V1 0x7150 + +#define R_AX_C2HREG_DATA1_V1 0x7154 + +#define R_AX_C2HREG_DATA2_V1 0x7158 + +#define R_AX_C2HREG_DATA3_V1 0x715C + +#define R_AX_H2CREG_CTRL_V1 0x7160 + +#define R_AX_C2HREG_CTRL_V1 0x7164 + +#define R_AX_CPWM_V1 0x7170 + +// +// WL_PON +// + +#define R_AX_FWD1IMR 0x8300 +#define B_AX_FS_TM_WAKE_INT_EN BIT(16) +#define B_AX_FS_BT_MAILBOX_INT_EN BIT(1) +#define B_AX_FS_RPWM_INT_EN BIT(0) + +#define R_AX_FWD1ISR 0x8304 +#define B_AX_FS_TM_WAKE_INT BIT(16) +#define B_AX_FS_BT_MAILBOX_INT BIT(1) +#define B_AX_FS_RPWM_INT BIT(0) + +#define R_AX_FSMIMR 0x8308 +#define B_AX_FSM_RP_END_EVENT_IMR BIT(6) +#define B_AX_FSM_RX_BCN_TO_CNT_EVENT_IMR BIT(5) +#define B_AX_FSM_RX_MATCH_EVENT_IMR BIT(4) +#define B_AX_FSM_HIOE_ERR_EVENT_IMR BIT(3) +#define B_AX_FSM_OTHERS_WAKE_EVENT_IMR BIT(2) +#define B_AX_FSM_TIMER_TO_EVENT_IMR BIT(1) + +#define R_AX_FSMISR 0x830C +#define B_AX_FSM_RP_END_EVENT_ISR BIT(6) +#define B_AX_FSM_RX_BCN_TO_CNT_EVENT_ISR BIT(5) +#define B_AX_FSM_RX_MATCH_EVENT_ISR BIT(4) +#define B_AX_FSM_HIOE_ERR_EVENT_ISR BIT(3) +#define B_AX_FSM_OTHERS_WAKE_EVENT_ISR BIT(2) +#define B_AX_FSM_TIMER_TO_EVENT_ISR BIT(1) + +#define R_AX_TM_BKP_RES_CTRL 0x8310 +#define B_AX_TM_WAKE_IND BIT(7) +#define B_AX_TM_BKP_EN_STS BIT(6) +#define B_AX_PRE_CHK_DONE BIT(3) +#define B_AX_PRE_CHK_VALID BIT(2) +#define B_AX_TM_RES_EN BIT(1) +#define B_AX_TM_BKP_EN_TRIGGER BIT(0) + +#define R_AX_PRE_CHK_CTRL 0x8314 +#define B_AX_PRE_CHK_THD_SH 16 +#define B_AX_PRE_CHK_THD_MSK 0xffff +#define B_AX_PRE_WAKE_TIME_SH 0 +#define B_AX_PRE_WAKE_TIME_MSK 0xffff + +#define R_AX_LPS_WTM_SC 0x8318 +#define B_AX_LPS_WTM_SC_SH 0 +#define B_AX_LPS_WTM_SC_MSK 0xffffffffL + +#define R_AX_LPS_WTM_CNT 0x831C + +#define R_AX_TSF_32K_SEL 0x8320 +#define B_AX_TSF_CLK_STABLE BIT(17) +#define B_AX_CKSL_WLTSF BIT(16) +#define B_AX_32K_SRC_SEL BIT(8) +#define B_AX_US_TIME_VALUE_SH 0 +#define B_AX_US_TIME_VALUE_MSK 0xff + +#define R_AX_HIOE_END_ADDR 0x8340 +#define B_AX_HIOE_END_ADDR_SH 0 +#define B_AX_HIOE_END_ADDR_MSK 0xffffffffL + +#define R_AX_HIOE_STR_ADDR 0x8344 +#define B_AX_HIOE_STR_ADDR_SH 0 +#define B_AX_HIOE_STR_ADDR_MSK 0xffffffffL + +#define R_AX_BKP_HIOE_CTRL 0x8348 +#define B_AX_BKP_HIOE_CTRL_SH 0 +#define B_AX_BKP_HIOE_CTRL_MSK 0xffffffffL + +#define R_AX_RES_HIOE_CTRL 0x834C +#define B_AX_RES_HIOE_CTRL_SH 0 +#define B_AX_RES_HIOE_CTRL_MSK 0xffffffffL + +#define R_AX_HCI_FUNC_EN 0x8380 +#define B_AX_HCI_RXDMA_EN BIT(1) +#define B_AX_HCI_TXDMA_EN BIT(0) + +#define R_AX_OSC_32K_CTRL 0x8394 +#define B_AX_LPOSC32K_OK BIT(31) +#define B_AX_CAL_32K_DBG_SEL BIT(3) +#define B_AX_CAL32K_XTAL_EN BIT(2) +#define B_AX_CAL32K_OSC_EN BIT(1) +#define B_AX_WL_POW_32KOSC BIT(0) + +#define R_AX_32K_CAL_REG0 0x8398 +#define B_AX_CAL_32K_REG_WR BIT(31) +#define B_AX_CAL_OSC_XTAL_SEL BIT(22) +#define B_AX_CAL_32K_REG_ADDR_SH 16 +#define B_AX_CAL_32K_REG_ADDR_MSK 0x3f +#define B_AX_CAL_32K_REG_DATA_SH 0 +#define B_AX_CAL_32K_REG_DATA_MSK 0xffff + +#define R_AX_BOOT_DBG 0x83F0 +#define B_AX_BOOT_STATUS_SH 16 +#define B_AX_BOOT_STATUS_MSK 0xffff +#define B_AX_SECUREBOOT_STATUS_SH 0 +#define B_AX_SECUREBOOT_STATUS_MSK 0xffff + +// +// 8852C WL_PON +// + +#define R_AX_FWD1IMR_V1 0x7800 + +#define R_AX_FWD1ISR_V1 0x7804 + +#define R_AX_FSMIMR_V1 0x7808 + +#define R_AX_FSMISR_V1 0x780C + +#define R_AX_TM_BKP_RES_CTRL_V1 0x7810 + +#define R_AX_PRE_CHK_CTRL_V1 0x7814 + +#define R_AX_LPS_WTM_SC_V1 0x7818 + +#define R_AX_LPS_WTM_CNT_V1 0x781C + +#define R_AX_TSF_32K_SEL_V1 0x7820 + +#define R_AX_HIOE_END_ADDR_V1 0x7840 + +#define R_AX_HIOE_STR_ADDR_V1 0x7844 + +#define R_AX_BKP_HIOE_CTRL_V1 0x7848 + +#define R_AX_RES_HIOE_CTRL_V1 0x784C + +#define R_AX_HCI_FUNC_EN_V1 0x7880 + +#define R_AX_OSC_32K_CTRL_V1 0x7894 + +#define R_AX_32K_CAL_REG0_V1 0x7898 + +#define R_AX_BOOT_DBG_V1 0x78F0 +// +// COMMON +// + +#define R_AX_DMAC_FUNC_EN 0x8400 +#define B_AX_DMAC_CRPRT BIT(31) +#define B_AX_MAC_FUNC_EN BIT(30) +#define B_AX_DMAC_FUNC_EN BIT(29) +#define B_AX_MPDU_PROC_EN BIT(28) +#define B_AX_WD_RLS_EN BIT(27) +#define B_AX_DLE_WDE_EN BIT(26) +#define B_AX_TXPKT_CTRL_EN BIT(25) +#define B_AX_STA_SCH_EN BIT(24) +#define B_AX_DLE_PLE_EN BIT(23) +#define B_AX_PKT_BUF_EN BIT(22) +#define B_AX_DMAC_TBL_EN BIT(21) +#define B_AX_PKT_IN_EN BIT(20) +#define B_AX_DLE_CPUIO_EN BIT(19) +#define B_AX_DISPATCHER_EN BIT(18) +#define B_AX_BBRPT_EN BIT(17) +#define B_AX_MAC_SEC_EN BIT(16) +#define B_AX_H_AXIDMA_EN BIT(14) +#define B_AX_DMAC_SER_PS BIT(13) +#define B_AX_CMAC_SER_PS BIT(12) + +#define R_AX_DMAC_CLK_EN 0x8404 +#define B_AX_MAC_CKEN BIT(30) +#define B_AX_DMAC_CKEN BIT(29) +#define B_AX_MPDU_CKEN BIT(28) +#define B_AX_WD_RLS_CLK_EN BIT(27) +#define B_AX_DLE_WDE_CLK_EN BIT(26) +#define B_AX_TXPKT_CTRL_CLK_EN BIT(25) +#define B_AX_STA_SCH_CLK_EN BIT(24) +#define B_AX_DLE_PLE_CLK_EN BIT(23) +#define B_AX_PKT_IN_CLK_EN BIT(20) +#define B_AX_DLE_CPUIO_CLK_EN BIT(19) +#define B_AX_DISPATCHER_CLK_EN BIT(18) +#define B_AX_BBRPT_CLK_EN BIT(17) +#define B_AX_MAC_SEC_CLK_EN BIT(16) + +#define R_AX_LTR_CTRL_0 0x8410 +#define B_AX_LTR_SPACE_IDX_SH 12 +#define B_AX_LTR_SPACE_IDX_MSK 0x3 +#define B_AX_LTR_IDLE_TIMER_IDX_SH 8 +#define B_AX_LTR_IDLE_TIMER_IDX_MSK 0x7 +#define B_AX_LTR_WD_NOEMP_CHK BIT(6) +#define B_AX_APP_LTR_ACT BIT(5) +#define B_AX_APP_LTR_IDLE BIT(4) +#define B_AX_LTR_EN BIT(1) +#define B_AX_LTR_HW_EN BIT(0) + +#define R_AX_LTR_CTRL_1 0x8414 +#define B_AX_LTR_RX0_TH_SH 16 +#define B_AX_LTR_RX0_TH_MSK 0xfff +#define B_AX_LTR_RX1_TH_SH 0 +#define B_AX_LTR_RX1_TH_MSK 0xfff + +#define R_AX_LTR_IDLE_LATENCY 0x8418 +#define B_AX_LTR_IDLE_LTCY_SH 0 +#define B_AX_LTR_IDLE_LTCY_MSK 0xffffffffL + +#define R_AX_LTR_ACTIVE_LATENCY 0x841C +#define B_AX_LTR_ACT_LTCY_SH 0 +#define B_AX_LTR_ACT_LTCY_MSK 0xffffffffL + +#define R_AX_DMAC_TABLE_CTRL 0x8420 +#define B_AX_HWAMSDU_PADDING_MODE BIT(31) +#define B_AX_MACID_MPDU_PROCESSOR_OFFSET_SH 16 +#define B_AX_MACID_MPDU_PROCESSOR_OFFSET_MSK 0x7ff +#define B_AX_DMAC_CTRL_INFO_OFFSET_SH 0 +#define B_AX_DMAC_CTRL_INFO_OFFSET_MSK 0x7ff + +#define R_AX_SER_DBG_INFO 0x8424 + +#define R_AX_DLE_EMPTY0 0x8430 +#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) +#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) +#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) +#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) +#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) +#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) +#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) +#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) +#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) +#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) +#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) +#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) +#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) +#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) +#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) +#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) +#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) +#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) +#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) +#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) + +#define R_AX_DLE_EMPTY1 0x8434 +#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20) +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19) +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18) +#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17) +#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16) +#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5) +#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4) +#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3) +#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2) +#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1) +#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0) + +#define R_AX_FWD2IMR 0x8500 +#define B_AX_FS_TXPKTIN_INT_EN BIT(5) +#define B_AX_FS_WWLAN_INT_EN BIT(4) +#define B_AX_FS_PLD_CPU_IO_PORT_Q1_INT_EN BIT(3) +#define B_AX_FS_PLD_CPU_IO_PORT_Q0_INT_EN BIT(2) +#define B_AX_FS_WD_CPU_IO_PORT_Q1_INT_EN BIT(1) +#define B_AX_FS_WD_CPU_IO_PORT_Q0_INT_EN BIT(0) + +#define R_AX_FWD2ISR 0x8504 +#define B_AX_FS_TXPKTIN_INT BIT(5) +#define B_AX_FS_WWLAN_INT BIT(4) +#define B_AX_FS_PLD_CPU_IO_PORT_Q1_INT BIT(3) +#define B_AX_FS_PLD_CPU_IO_PORT_Q0_INT BIT(2) +#define B_AX_FS_WD_CPU_IO_PORT_Q1_INT BIT(1) +#define B_AX_FS_WD_CPU_IO_PORT_Q0_INT BIT(0) + +#define R_AX_DMAC_ERR_IMR 0x8520 +#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10) +#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9) +#define B_AX_DISPATCH_ERR_INT_EN BIT(8) +#define B_AX_PKTIN_ERR_INT_EN BIT(7) +#define B_AX_PLE_DLE_ERR_INT_EN BIT(6) +#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5) +#define B_AX_WDE_DLE_ERR_INT_EN BIT(4) +#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3) +#define B_AX_MPDU_ERR_INT_EN BIT(2) +#define B_AX_WSEC_ERR_INT_EN BIT(1) +#define B_AX_WDRLS_ERR_INT_EN BIT(0) + +#define R_AX_DMAC_ERR_ISR 0x8524 +#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) +#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) +#define B_AX_DISPATCH_ERR_FLAG BIT(8) +#define B_AX_PKTIN_ERR_FLAG BIT(7) +#define B_AX_PLE_DLE_ERR_FLAG BIT(6) +#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) +#define B_AX_WDE_DLE_ERR_FLAG BIT(4) +#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) +#define B_AX_MPDU_ERR_FLAG BIT(2) +#define B_AX_WSEC_ERR_FLAG BIT(1) +#define B_AX_WDRLS_ERR_FLAG BIT(0) + +#define R_AX_BIST_CTRL 0x8600 +#define B_AX_BIST_DYN_READ_EN BIT(14) +#define B_AX_BIST_LOOP_MODE BIT(13) +#define B_AX_BIST_LVDRF_CLKDIS BIT(12) +#define B_AX_BIST_DRF_RESUME BIT(3) +#define B_AX_BIST_DRF_MODE BIT(2) +#define B_AX_BIST_MODE BIT(1) +#define B_AX_BIST_RSTN_ALL BIT(0) + +#define R_AX_SYS_CTRL 0x8604 +#define B_AX_SYM_MEM_RMV_FABDBG_SH 30 +#define B_AX_SYM_MEM_RMV_FABDBG_MSK 0x3 +#define B_AX_SYM_MEM_RMV_SIGN BIT(29) +#define B_AX_SYM_MEM_RMV_2PRF BIT(27) +#define B_AX_SYM_MEM_RMV_1PRF BIT(26) +#define B_AX_SYM_MEM_RMV_1PSR BIT(25) +#define B_AX_SYM_MEM_RMV_ROM BIT(24) +#define B_AX_SYM_MEM_RMV_WL_SH 4 +#define B_AX_SYM_MEM_RMV_WL_MSK 0xf + +#define R_AX_BIST_CTRL_1 0x8610 +#define B_AX_BIST_RSTN_N_DMAC_SH 0 +#define B_AX_BIST_RSTN_N_DMAC_MSK 0xfffffff + +#define R_AX_BIST_CTRL_2 0x8614 +#define B_AX_BIST_DONE_DMAC_SH 0 +#define B_AX_BIST_DONE_DMAC_MSK 0xfffffff + +#define R_AX_BIST_CTRL_3 0x8618 +#define B_AX_BIST_FAIL_DMAC_SH 0 +#define B_AX_BIST_FAIL_DMAC_MSK 0xfffffff + +#define R_AX_BIST_CTRL_4 0x861C +#define B_AX_BIST_DRF_PAUSE_DMAC_SH 0 +#define B_AX_BIST_DRF_PAUSE_DMAC_MSK 0xfffffff + +// +// Dispatcher +// + +#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 +#define B_AX_PL_PAGE_128B_SEL BIT(9) +#define B_AX_WD_PAGE_64B_SEL BIT(8) +#define B_AX_CDR_GATTING_DISABLE BIT(3) +#define B_AX_CDT_GATTING_DISABLE BIT(2) +#define B_AX_HDR_GATTING_DISABLE BIT(1) +#define B_AX_HDT_GATTING_DISABLE BIT(0) + +#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 +#define B_AX_OTHER_STF_WROQT_UNDERFLOW BIT(29) +#define B_AX_OTHER_STF_WROQT_OVERFLOW BIT(28) +#define B_AX_OTHER_STF_WRFF_UNDERFLOW BIT(27) +#define B_AX_OTHER_STF_WRFF_OVERFLOW BIT(26) +#define B_AX_OTHER_STF_CMD_UNDERFLOW BIT(25) +#define B_AX_OTHER_STF_CMD_OVERFLOW BIT(24) +#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR BIT(17) +#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR BIT(16) +#define B_AX_PLE_OUTPUT_ERR BIT(12) +#define B_AX_PLE_RESP_ERR BIT(11) +#define B_AX_PLE_BURST_NUM_ERR BIT(10) +#define B_AX_PLE_NULL_PKT_ERR BIT(9) +#define B_AX_PLE_FLOW_CTRL_ERR BIT(8) +#define B_AX_WDE_OUTPUT_ERR BIT(4) +#define B_AX_WDE_RESP_ERR BIT(3) +#define B_AX_WDE_BURST_NUM_ERR BIT(2) +#define B_AX_WDE_NULL_PKT_ERR BIT(1) +#define B_AX_WDE_FLOW_CTRL_ERR BIT(0) + +#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 +#define B_AX_HDT_RX_WRITE_UNDERFLOW BIT(31) +#define B_AX_HDT_RX_WRITE_OVERFLOW BIT(30) +#define B_AX_HDT_CHKSUM_FSM_ERR BIT(29) +#define B_AX_HDT_SHIFT_DMA_CFG_ERR BIT(28) +#define B_AX_HDT_DMA_PROCESS_ERR BIT(27) +#define B_AX_HDT_TOTAL_LEN_ERR BIT(26) +#define B_AX_HDT_SHIFT_EN_ERR BIT(25) +#define B_AX_HDT_RXAGG_CFG_ERR BIT(24) +#define B_AX_HDT_OUTPUT_ERR BIT(21) +#define B_AX_HDT_RESP_ERR BIT(20) +#define B_AX_HDT_BURST_NUM_ERR BIT(19) +#define B_AX_HDT_NULLPKT_ERR BIT(18) +#define B_AX_HDT_FLOW_CTRL_ERR BIT(17) +#define B_AX_HDT_PLD_CMD_UNDERFLOW BIT(16) +#define B_AX_HDT_PLD_CMD_OVERLOW BIT(15) +#define B_AX_HDT_TX_WRITE_UNDERFLOW BIT(14) +#define B_AX_HDT_TX_WRITE_OVERFLOW BIT(13) +#define B_AX_HDT_TCP_CHK_ERR BIT(12) +#define B_AX_HDT_TXPKTSIZE_ERR BIT(11) +#define B_AX_HDT_PRE_COST_ERR BIT(10) +#define B_AX_HDT_WD_CHK_ERR BIT(9) +#define B_AX_HDT_CHANNEL_DMA_ERR BIT(8) +#define B_AX_HDT_OFFSET_UNMATCH BIT(7) +#define B_AX_HDT_PAYLOAD_UNDERFLOW BIT(6) +#define B_AX_HDT_PAYLOAD_OVERFLOW BIT(5) +#define B_AX_HDT_PERMU_UNDERFLOW BIT(4) +#define B_AX_HDT_PERMU_OVERFLOW BIT(3) +#define B_AX_HDT_PKT_FAIL_DBG BIT(2) +#define B_AX_HDT_CHANNEL_ID_ERR BIT(1) +#define B_AX_HDT_CHANNEL_DIFF_ERR BIT(0) + +#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C +#define B_AX_CPU_RX_WRITE_UNDERFLOW BIT(31) +#define B_AX_CPU_RX_WRITE_OVERFLOW BIT(30) +#define B_AX_CPU_CHKSUM_FSM_ERR BIT(29) +#define B_AX_CPU_SHIFT_DMA_CFG_ERR BIT(28) +#define B_AX_CPU_DMA_PROCESS_ERR BIT(27) +#define B_AX_CPU_TOTAL_LEN_ERR BIT(26) +#define B_AX_CPU_SHIFT_EN_ERR BIT(25) +#define B_AX_CPU_RXAGG_CFG_ERR BIT(24) +#define B_AX_CPU_OUTPUT_ERR BIT(20) +#define B_AX_CPU_RESP_ERR BIT(19) +#define B_AX_CPU_BURST_NUM_ERR BIT(18) +#define B_AX_CPU_NULLPKT_ERR BIT(17) +#define B_AX_CPU_FLOW_CTRL_ERR BIT(16) +#define B_AX_CPU_F2P_SEQ_ERR BIT(15) +#define B_AX_CPU_F2P_QSEL_ERR BIT(14) +#define B_AX_CPU_PLD_CMD_UNDERFLOW BIT(13) +#define B_AX_CPU_PLD_CMD_OVERLOW BIT(12) +#define B_AX_CPU_PRE_COST_ERR BIT(11) +#define B_AX_CPU_WD_CHK_ERR BIT(10) +#define B_AX_CPU_CHANNEL_DMA_ERR BIT(9) +#define B_AX_CPU_OFFSET_UNMATCH BIT(8) +#define B_AX_CPU_PAYLOAD_CHKSUM_ERR BIT(7) +#define B_AX_CPU_PAYLOAD_UNDERFLOW BIT(6) +#define B_AX_CPU_PAYLOAD_OVERFLOW BIT(5) +#define B_AX_CPU_PERMU_UNDERFLOW BIT(4) +#define B_AX_CPU_PERMU_OVERFLOW BIT(3) +#define B_AX_CPU_CHANNEL_ID_ERR BIT(2) +#define B_AX_CPU_PKT_FAIL_DBG BIT(1) +#define B_AX_CPU_CHANNEL_DIFF_ERR BIT(0) + +#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 +#define B_AX_CPU_ADDR_INFO_8B_SEL BIT(8) +#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) + +#define R_AX_TX_TCPIP_CHECKSUM_FUNCTION 0x8814 +#define B_AX_HDT_TCPIP_CHKSUM_EN BIT(0) + +#define R_AX_TXAGG_ALIGN_CFG 0x8818 +#define B_AX_TXAGG_ALIGN_SIZE_EN BIT(31) +#define B_AX_TXAGG_ALIGN_SIZE_SH 0 +#define B_AX_TXAGG_ALIGN_SIZE_MSK 0xfff + +#define R_AX_TX_PASTE_TIMESTAMP_SETTING 0x881C +#define B_AX_HDT_TIMESTAMP_EN BIT(0) + +#define R_AX_CPU_PORT_DEBUG_SETTING 0x8820 +#define B_AX_CDT_F2P_CPU_PORT_EN BIT(9) +#define B_AX_CDT_AC_CPU_PORT_EN BIT(8) +#define B_AX_HDT_AC_CPU_PORT_EN BIT(0) + +#define R_AX_TX_CHECK_OFFSET_SETTING 0x8824 +#define B_AX_CDT_CHK_OFFSET_EN BIT(24) +#define B_AX_CDT_CHK_OFFSET_SH 16 +#define B_AX_CDT_CHK_OFFSET_MSK 0xff +#define B_AX_HDT_CHK_OFFSET_EN BIT(8) +#define B_AX_HDT_CHK_OFFSET_SH 0 +#define B_AX_HDT_CHK_OFFSET_MSK 0xff + +#define R_AX_TX_QUEUE_CLEAR_SETTING 0x8828 +#define B_AX_HDT_TXQUE_CLR_EN BIT(0) + +#define R_AX_TX_ERROR_STOP_DEBUG_SETTING 0x882C +#define B_AX_CDT_ERROR_STOP BIT(8) +#define B_AX_HDT_ERROR_STOP BIT(0) + +#define R_AX_WD_CHECKSUM_FUNCTION_ENABLE 0x8830 +#define B_AX_CDT_WD_CHKSUM_EN BIT(8) +#define B_AX_HDT_WD_CHKSUM_EN BIT(0) + +#define R_AX_TX_DTAT_DROP_DEBUG_SETTING 0x8834 +#define B_AX_CDT_DATA_DROP_EN BIT(8) +#define B_AX_HDT_DATA_DROP_EN BIT(0) + +#define R_AX_REQUEST_PLE_BUFFER_SETTING 0x8838 +#define B_AX_AMSDU_PADDING_SPACE_SH 8 +#define B_AX_AMSDU_PADDING_SPACE_MSK 0xff +#define B_AX_RSV_PLD_SPACE_SH 0 +#define B_AX_RSV_PLD_SPACE_MSK 0xff + +#define R_AX_DMAC_MACID_DROP_0 0x8840 +#define B_AX_DMAC_MACID31_0_DROP_SH 0 +#define B_AX_DMAC_MACID31_0_DROP_MSK 0xffffffffL + +#define R_AX_DMAC_MACID_DROP_1 0x8844 +#define B_AX_DMAC_MACID63_32_DROP_SH 0 +#define B_AX_DMAC_MACID63_32_DROP_MSK 0xffffffffL + +#define R_AX_DMAC_MACID_DROP_2 0x8848 +#define B_AX_DMAC_MACID95_64_DROP_SH 0 +#define B_AX_DMAC_MACID95_64_DROP_MSK 0xffffffffL + +#define R_AX_DMAC_MACID_DROP_3 0x884C +#define B_AX_DMAC_MACID127_96_DROP_SH 0 +#define B_AX_DMAC_MACID127_96_DROP_MSK 0xffffffffL + +#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 +#define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31) +#define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30) +#define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29) +#define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) +#define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27) +#define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26) +#define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25) +#define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24) +#define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21) +#define B_AX_HDT_RES_ERR_INT_EN BIT(20) +#define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19) +#define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18) +#define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17) +#define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16) +#define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15) +#define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14) +#define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13) +#define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12) +#define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11) +#define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10) +#define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9) +#define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8) +#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) +#define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6) +#define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5) +#define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4) +#define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3) +#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) +#define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1) +#define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0) + +#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 +#define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31) +#define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30) +#define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29) +#define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) +#define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27) +#define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26) +#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) +#define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24) +#define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20) +#define B_AX_CPU_RESP_ERR_INT_EN BIT(19) +#define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18) +#define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17) +#define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16) +#define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15) +#define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14) +#define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13) +#define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12) +#define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11) +#define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10) +#define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9) +#define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8) +#define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) +#define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6) +#define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5) +#define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4) +#define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3) +#define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2) +#define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1) +#define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0) + +#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 +#define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29) +#define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28) +#define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27) +#define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26) +#define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25) +#define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24) +#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17) +#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16) +#define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12) +#define B_AX_PLE_RESP_ERR_INT_EN BIT(11) +#define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10) +#define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9) +#define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8) +#define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4) +#define B_AX_WDE_RESP_ERR_INT_EN BIT(3) +#define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2) +#define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1) +#define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0) + +#define R_AX_DISPATCHER_DBG_PORT 0x8860 +#define B_AX_DISPATCHER_DBG_SEL_SH 8 +#define B_AX_DISPATCHER_DBG_SEL_MSK 0xf +#define B_AX_DISPATCHER_INTN_SEL_SH 4 +#define B_AX_DISPATCHER_INTN_SEL_MSK 0xf +#define B_AX_DISPATCHER_CH_SEL_SH 0 +#define B_AX_DISPATCHER_CH_SEL_MSK 0xf + +#define R_AX_HDP_DBG_INFO_4 0x8890 +#define B_AX_ADDR_INFO_CS_SH 28 +#define B_AX_ADDR_INFO_CS_MSK 0xf +#define B_AX_HCI_WP_FF_FULL BIT(27) +#define B_AX_AXI_WP_FF_FULL BIT(26) +#define B_AX_HFC_CH_FULL_SH 13 +#define B_AX_HFC_CH_FULL_MSK 0x1fff +#define B_AX_HFC_CH_REQ_SH 0 +#define B_AX_HFC_CH_REQ_MSK 0x1fff + +#define R_AX_HDP_DBG_INFO_10 0x88A8 +#define B_AX_DMA_ST_HDR_HDP_SH 20 +#define B_AX_DMA_ST_HDR_HDP_MSK 0x7 +#define B_AX_RX_ST_HDR_HDP_SH 16 +#define B_AX_RX_ST_HDR_HDP_MSK 0x7 + +#define R_AX_RXAGG_0 0x8900 +#define B_AX_RXAGG_EN BIT(31) +#define B_AX_RXAGG_DMA_STORE BIT(30) +#define B_AX_RXAGG_SW_EN BIT(29) +#define B_AX_RXAGG_SW_TRIG BIT(28) +#define B_AX_RXAGG_PKTNUM_TH_SH 16 +#define B_AX_RXAGG_PKTNUM_TH_MSK 0xff +#define B_AX_RXAGG_TIMEOUT_TH_SH 8 +#define B_AX_RXAGG_TIMEOUT_TH_MSK 0xff +#define B_AX_RXAGG_LEN_TH_SH 0 +#define B_AX_RXAGG_LEN_TH_MSK 0xff + +#define R_AX_RXAGG_1 0x8904 +#define B_AX_RXAGG_SML_PKT_SIZE_SH 8 +#define B_AX_RXAGG_SML_PKT_SIZE_MSK 0x7 +#define B_AX_RXAGG_SML_PKTNUM_TH_SH 0 +#define B_AX_RXAGG_SML_PKTNUM_TH_MSK 0x1f + +#define R_AX_RXDMA_SETTING 0x8908 +#define B_AX_PLE_BURST_READ BIT(24) +#define B_AX_REQ_DEPTH_SH 16 +#define B_AX_REQ_DEPTH_MSK 0x3 +#define B_AX_BULK_TH_OPT BIT(10) +#define B_AX_BURST_CNT_SH 8 +#define B_AX_BURST_CNT_MSK 0x3 +#define B_AX_BULK_SIZE_SH 0 +#define B_AX_BULK_SIZE_MSK 0x3 + +#define R_AX_FWDL_CHECKSUM 0x890C +#define B_AX_FWDL_CHKSUM_SH 16 +#define B_AX_FWDL_CHKSUM_MSK 0xffff +#define B_AX_FWDL_CHKSUM_VALID BIT(2) +#define B_AX_FWDL_CHKSUM_RESULT BIT(1) +#define B_AX_FWDL_CHKSUM_EN BIT(0) + +#define R_AX_H2C_SETTING 0x8910 +#define B_AX_CDR_REMOVE_H2C_WD BIT(0) + +#define R_AX_RX_PPDU_STATUS_FW_MODE 0x8914 +#define B_AX_HDR_PPDU_ENQ_WLCPU_EN BIT(31) +#define B_AX_CDR_PPDU_2_WLCPU_LEN_SH 0 +#define B_AX_CDR_PPDU_2_WLCPU_LEN_MSK 0x3fff + +#define R_AX_RX_TCPIP_CHECKSUM_FUNCTION 0x8918 +#define B_AX_HDR_TCPIP_CHKSUM_EN BIT(0) + +#define R_AX_RX_FC_BD_VALID_MASK 0x891C +#define B_AX_CDR_BD_MASK_SH 8 +#define B_AX_CDR_BD_MASK_MSK 0x1f +#define B_AX_HDR_BD_MASK_SH 0 +#define B_AX_HDR_BD_MASK_MSK 0x3 + +#define R_AX_RX_FUNCTION_STOP 0x8920 +#define B_AX_HDR_RX_STOP BIT(0) + +#define R_AX_HCI_FC_CTRL 0x8A00 +#define B_AX_HCI_FC_CH12_FULL_COND_SH 10 +#define B_AX_HCI_FC_CH12_FULL_COND_MSK 0x3 +#define B_AX_HCI_FC_WP_CH811_FULL_COND_SH 8 +#define B_AX_HCI_FC_WP_CH811_FULL_COND_MSK 0x3 +#define B_AX_HCI_FC_WP_CH07_FULL_COND_SH 6 +#define B_AX_HCI_FC_WP_CH07_FULL_COND_MSK 0x3 +#define B_AX_HCI_FC_WD_FULL_COND_SH 4 +#define B_AX_HCI_FC_WD_FULL_COND_MSK 0x3 +#define B_AX_HCI_FC_CH12_EN BIT(3) +#define B_AX_HCI_FC_MODE_SH 1 +#define B_AX_HCI_FC_MODE_MSK 0x3 +#define B_AX_HCI_FC_EN BIT(0) + +#define R_AX_CH_PAGE_CTRL 0x8A04 +#define B_AX_PREC_PAGE_CH12_SH 16 +#define B_AX_PREC_PAGE_CH12_MSK 0xff +#define B_AX_PREC_PAGE_CH011_SH 0 +#define B_AX_PREC_PAGE_CH011_MSK 0xff + +#define R_AX_ACH011_INTRPT_STAT 0x8A08 +#define B_AX_ACH11_INTRPT_STAT BIT(11) +#define B_AX_ACH10_INTRPT_STAT BIT(10) +#define B_AX_ACH9_INTRPT_STAT BIT(9) +#define B_AX_ACH8_INTRPT_STAT BIT(8) +#define B_AX_ACH7_INTRPT_STAT BIT(7) +#define B_AX_ACH6_INTRPT_STAT BIT(6) +#define B_AX_ACH5_INTRPT_STAT BIT(5) +#define B_AX_ACH4_INTRPT_STAT BIT(4) +#define B_AX_ACH3_INTRPT_STAT BIT(3) +#define B_AX_ACH2_INTRPT_STAT BIT(2) +#define B_AX_ACH1_INTRPT_STAT BIT(1) +#define B_AX_ACH0_INTRPT_STAT BIT(0) + +#define R_AX_HCI_FC_ERR_FLAG 0x8A0C +#define B_AX_PUB_AVAL_PG_OFW BIT(10) +#define B_AX_PUB_AVAL_PG_UFW BIT(9) +#define B_AX_PUB_USE_PG_OFW BIT(8) +#define B_AX_PUB_USE_PG_UFW BIT(7) +#define B_AX_CH011_USE_PG_OFW BIT(6) +#define B_AX_CH011_USE_PG_UFW BIT(5) +#define B_AX_CH011_AVAL_PG_OFW BIT(4) +#define B_AX_CH011_AVAL_PG_UFW BIT(3) +#define B_AX_WP_REQ_PG_ERR BIT(2) +#define B_AX_CH12_REQ_PG_ERR BIT(1) +#define B_AX_CH011_REQ_PG_ERR BIT(0) + +#define R_AX_ACH0_PAGE_CTRL 0x8A10 +#define B_AX_ACH0_GRP BIT(31) +#define B_AX_ACH0_MAX_PG_SH 16 +#define B_AX_ACH0_MAX_PG_MSK 0xfff +#define B_AX_ACH0_MIN_PG_SH 0 +#define B_AX_ACH0_MIN_PG_MSK 0xfff + +#define R_AX_ACH1_PAGE_CTRL 0x8A14 +#define B_AX_ACH1_GRP BIT(31) +#define B_AX_ACH1_MAX_PG_SH 16 +#define B_AX_ACH1_MAX_PG_MSK 0xfff +#define B_AX_ACH1_MIN_PG_SH 0 +#define B_AX_ACH1_MIN_PG_MSK 0xfff + +#define R_AX_ACH2_PAGE_CTRL 0x8A18 +#define B_AX_ACH2_GRP BIT(31) +#define B_AX_ACH2_MAX_PG_SH 16 +#define B_AX_ACH2_MAX_PG_MSK 0xfff +#define B_AX_ACH2_MIN_PG_SH 0 +#define B_AX_ACH2_MIN_PG_MSK 0xfff + +#define R_AX_ACH3_PAGE_CTRL 0x8A1C +#define B_AX_ACH3_GRP BIT(31) +#define B_AX_ACH3_MAX_PG_SH 16 +#define B_AX_ACH3_MAX_PG_MSK 0xfff +#define B_AX_ACH3_MIN_PG_SH 0 +#define B_AX_ACH3_MIN_PG_MSK 0xfff + +#define R_AX_ACH4_PAGE_CTRL 0x8A20 +#define B_AX_ACH4_GRP BIT(31) +#define B_AX_ACH4_MAX_PG_SH 16 +#define B_AX_ACH4_MAX_PG_MSK 0xfff +#define B_AX_ACH4_MIN_PG_SH 0 +#define B_AX_ACH4_MIN_PG_MSK 0xfff + +#define R_AX_ACH5_PAGE_CTRL 0x8A24 +#define B_AX_ACH5_GRP BIT(31) +#define B_AX_ACH5_MAX_PG_SH 16 +#define B_AX_ACH5_MAX_PG_MSK 0xfff +#define B_AX_ACH5_MIN_PG_SH 0 +#define B_AX_ACH5_MIN_PG_MSK 0xfff + +#define R_AX_ACH6_PAGE_CTRL 0x8A28 +#define B_AX_ACH6_GRP BIT(31) +#define B_AX_ACH6_MAX_PG_SH 16 +#define B_AX_ACH6_MAX_PG_MSK 0xfff +#define B_AX_ACH6_MIN_PG_SH 0 +#define B_AX_ACH6_MIN_PG_MSK 0xfff + +#define R_AX_ACH7_PAGE_CTRL 0x8A2C +#define B_AX_ACH7_GRP BIT(31) +#define B_AX_ACH7_MAX_PG_SH 16 +#define B_AX_ACH7_MAX_PG_MSK 0xfff +#define B_AX_ACH7_MIN_PG_SH 0 +#define B_AX_ACH7_MIN_PG_MSK 0xfff + +#define R_AX_CH8_PAGE_CTRL 0x8A30 +#define B_AX_CH8_GRP BIT(31) +#define B_AX_CH8_MAX_PG_SH 16 +#define B_AX_CH8_MAX_PG_MSK 0xfff +#define B_AX_CH8_MIN_PG_SH 0 +#define B_AX_CH8_MIN_PG_MSK 0xfff + +#define R_AX_CH9_PAGE_CTRL 0x8A34 +#define B_AX_CH9_GRP BIT(31) +#define B_AX_CH9_MAX_PG_SH 16 +#define B_AX_CH9_MAX_PG_MSK 0xfff +#define B_AX_CH9_MIN_PG_SH 0 +#define B_AX_CH9_MIN_PG_MSK 0xfff + +#define R_AX_CH10_PAGE_CTRL 0x8A38 +#define B_AX_CH10_GRP BIT(31) +#define B_AX_CH10_MAX_PG_SH 16 +#define B_AX_CH10_MAX_PG_MSK 0xfff +#define B_AX_CH10_MIN_PG_SH 0 +#define B_AX_CH10_MIN_PG_MSK 0xfff + +#define R_AX_CH11_PAGE_CTRL 0x8A3C +#define B_AX_CH11_GRP BIT(31) +#define B_AX_CH11_MAX_PG_SH 16 +#define B_AX_CH11_MAX_PG_MSK 0xfff +#define B_AX_CH11_MIN_PG_SH 0 +#define B_AX_CH11_MIN_PG_MSK 0xfff + +#define R_AX_ACH0_PAGE_INFO 0x8A50 +#define B_AX_ACH0_AVAL_PG_SH 16 +#define B_AX_ACH0_AVAL_PG_MSK 0xfff +#define B_AX_ACH0_USE_PG_SH 0 +#define B_AX_ACH0_USE_PG_MSK 0xfff + +#define R_AX_ACH1_PAGE_INFO 0x8A54 +#define B_AX_ACH1_AVAL_PG_SH 16 +#define B_AX_ACH1_AVAL_PG_MSK 0xfff +#define B_AX_ACH1_USE_PG_SH 0 +#define B_AX_ACH1_USE_PG_MSK 0xfff + +#define R_AX_ACH2_PAGE_INFO 0x8A58 +#define B_AX_ACH2_AVAL_PG_SH 16 +#define B_AX_ACH2_AVAL_PG_MSK 0xfff +#define B_AX_ACH2_USE_PG_SH 0 +#define B_AX_ACH2_USE_PG_MSK 0xfff + +#define R_AX_ACH3_PAGE_INFO 0x8A5C +#define B_AX_ACH3_AVAL_PG_SH 16 +#define B_AX_ACH3_AVAL_PG_MSK 0xfff +#define B_AX_ACH3_USE_PG_SH 0 +#define B_AX_ACH3_USE_PG_MSK 0xfff + +#define R_AX_ACH4_PAGE_INFO 0x8A60 +#define B_AX_ACH4_AVAL_PG_SH 16 +#define B_AX_ACH4_AVAL_PG_MSK 0xfff +#define B_AX_ACH4_USE_PG_SH 0 +#define B_AX_ACH4_USE_PG_MSK 0xfff + +#define R_AX_ACH5_PAGE_INFO 0x8A64 +#define B_AX_ACH5_AVAL_PG_SH 16 +#define B_AX_ACH5_AVAL_PG_MSK 0xfff +#define B_AX_ACH5_USE_PG_SH 0 +#define B_AX_ACH5_USE_PG_MSK 0xfff + +#define R_AX_ACH6_PAGE_INFO 0x8A68 +#define B_AX_ACH6_AVAL_PG_SH 16 +#define B_AX_ACH6_AVAL_PG_MSK 0xfff +#define B_AX_ACH6_USE_PG_SH 0 +#define B_AX_ACH6_USE_PG_MSK 0xfff + +#define R_AX_ACH7_PAGE_INFO 0x8A6C +#define B_AX_ACH7_AVAL_PG_SH 16 +#define B_AX_ACH7_AVAL_PG_MSK 0xfff +#define B_AX_ACH7_USE_PG_SH 0 +#define B_AX_ACH7_USE_PG_MSK 0xfff + +#define R_AX_CH8_PAGE_INFO 0x8A70 +#define B_AX_CH8_AVAL_PG_SH 16 +#define B_AX_CH8_AVAL_PG_MSK 0xfff +#define B_AX_CH8_USE_PG_SH 0 +#define B_AX_CH8_USE_PG_MSK 0xfff + +#define R_AX_CH9_PAGE_INFO 0x8A74 +#define B_AX_CH9_AVAL_PG_SH 16 +#define B_AX_CH9_AVAL_PG_MSK 0xfff +#define B_AX_CH9_USE_PG_SH 0 +#define B_AX_CH9_USE_PG_MSK 0xfff + +#define R_AX_CH10_PAGE_INFO 0x8A78 +#define B_AX_CH10_AVAL_PG_SH 16 +#define B_AX_CH10_AVAL_PG_MSK 0xfff +#define B_AX_CH10_USE_PG_SH 0 +#define B_AX_CH10_USE_PG_MSK 0xfff + +#define R_AX_CH11_PAGE_INFO 0x8A7C +#define B_AX_CH11_AVAL_PG_SH 16 +#define B_AX_CH11_AVAL_PG_MSK 0xfff +#define B_AX_CH11_USE_PG_SH 0 +#define B_AX_CH11_USE_PG_MSK 0xfff + +#define R_AX_CH12_PAGE_INFO 0x8A80 +#define B_AX_CH12_AVAL_PG_SH 16 +#define B_AX_CH12_AVAL_PG_MSK 0xfff + +#define R_AX_PUB_PAGE_INFO3 0x8A8C +#define B_AX_G1_AVAL_PG_SH 16 +#define B_AX_G1_AVAL_PG_MSK 0x1fff +#define B_AX_G0_AVAL_PG_SH 0 +#define B_AX_G0_AVAL_PG_MSK 0x1fff + +#define R_AX_PUB_PAGE_CTRL1 0x8A90 +#define B_AX_PUBPG_G1_SH 16 +#define B_AX_PUBPG_G1_MSK 0x1fff +#define B_AX_PUBPG_G0_SH 0 +#define B_AX_PUBPG_G0_MSK 0x1fff + +#define R_AX_PUB_PAGE_CTRL2 0x8A94 +#define B_AX_PUBPG_ALL_SH 0 +#define B_AX_PUBPG_ALL_MSK 0x1fff + +#define R_AX_PUB_PAGE_INFO1 0x8A98 +#define B_AX_G1_USE_PG_SH 16 +#define B_AX_G1_USE_PG_MSK 0x1fff +#define B_AX_G0_USE_PG_SH 0 +#define B_AX_G0_USE_PG_MSK 0x1fff + +#define R_AX_PUB_PAGE_INFO2 0x8A9C +#define B_AX_PUB_AVAL_PG_SH 0 +#define B_AX_PUB_AVAL_PG_MSK 0x1fff + +#define R_AX_WP_PAGE_CTRL1 0x8AA0 +#define B_AX_PREC_PAGE_WP_CH811_SH 16 +#define B_AX_PREC_PAGE_WP_CH811_MSK 0x1ff +#define B_AX_PREC_PAGE_WP_CH07_SH 0 +#define B_AX_PREC_PAGE_WP_CH07_MSK 0x1ff + +#define R_AX_WP_PAGE_CTRL2 0x8AA4 +#define B_AX_WP_THRD_SH 0 +#define B_AX_WP_THRD_MSK 0x1fff + +#define R_AX_WP_PAGE_INFO1 0x8AA8 +#define B_AX_WP_AVAL_PG_SH 16 +#define B_AX_WP_AVAL_PG_MSK 0x1fff + +#define R_AX_ACH0_THR 0x8AB0 +#define B_AX_ACH0_INTRPT_EN BIT(31) +#define B_AX_ACH0_THR_WP_SH 16 +#define B_AX_ACH0_THR_WP_MSK 0xfff +#define B_AX_ACH0_THR_WD_SH 0 +#define B_AX_ACH0_THR_WD_MSK 0xfff + +#define R_AX_ACH1_THR 0x8AB4 +#define B_AX_ACH1_INTRPT_EN BIT(31) +#define B_AX_ACH1_THR_WP_SH 16 +#define B_AX_ACH1_THR_WP_MSK 0xfff +#define B_AX_ACH1_THR_WD_SH 0 +#define B_AX_ACH1_THR_WD_MSK 0xfff + +#define R_AX_ACH2_THR 0x8AB8 +#define B_AX_ACH2_INTRPT_EN BIT(31) +#define B_AX_ACH2_THR_WP_SH 16 +#define B_AX_ACH2_THR_WP_MSK 0xfff +#define B_AX_ACH2_THR_WD_SH 0 +#define B_AX_ACH2_THR_WD_MSK 0xfff + +#define R_AX_ACH3_THR 0x8ABC +#define B_AX_ACH3_INTRPT_EN BIT(31) +#define B_AX_ACH3_THR_WP_SH 16 +#define B_AX_ACH3_THR_WP_MSK 0xfff +#define B_AX_ACH3_THR_WD_SH 0 +#define B_AX_ACH3_THR_WD_MSK 0xfff + +#define R_AX_ACH4_THR 0x8AC0 +#define B_AX_ACH4_INTRPT_EN BIT(31) +#define B_AX_ACH4_THR_WP_SH 16 +#define B_AX_ACH4_THR_WP_MSK 0xfff +#define B_AX_ACH4_THR_WD_SH 0 +#define B_AX_ACH4_THR_WD_MSK 0xfff + +#define R_AX_ACH5_THR 0x8AC4 +#define B_AX_ACH5_INTRPT_EN BIT(31) +#define B_AX_ACH5_THR_WP_SH 16 +#define B_AX_ACH5_THR_WP_MSK 0xfff +#define B_AX_ACH5_THR_WD_SH 0 +#define B_AX_ACH5_THR_WD_MSK 0xfff + +#define R_AX_ACH6_THR 0x8AC8 +#define B_AX_ACH6_INTRPT_EN BIT(31) +#define B_AX_ACH6_THR_WP_SH 16 +#define B_AX_ACH6_THR_WP_MSK 0xfff +#define B_AX_ACH6_THR_WD_SH 0 +#define B_AX_ACH6_THR_WD_MSK 0xfff + +#define R_AX_ACH7_THR 0x8ACC +#define B_AX_ACH7_INTRPT_EN BIT(31) +#define B_AX_ACH7_THR_WP_SH 16 +#define B_AX_ACH7_THR_WP_MSK 0xfff +#define B_AX_ACH7_THR_WD_SH 0 +#define B_AX_ACH7_THR_WD_MSK 0xfff + +#define R_AX_CH8_THR 0x8AD0 +#define B_AX_CH8_INTRPT_EN BIT(31) +#define B_AX_CH8_THR_WP_SH 16 +#define B_AX_CH8_THR_WP_MSK 0xfff +#define B_AX_CH8_THR_WD_SH 0 +#define B_AX_CH8_THR_WD_MSK 0xfff + +#define R_AX_CH9_THR 0x8AD4 +#define B_AX_CH9_INTRPT_EN BIT(31) +#define B_AX_CH9_THR_WP_SH 16 +#define B_AX_CH9_THR_WP_MSK 0xfff +#define B_AX_CH9_THR_WD_SH 0 +#define B_AX_CH9_THR_WD_MSK 0xfff + +#define R_AX_CH10_THR 0x8AD8 +#define B_AX_CH10_INTRPT_EN BIT(31) +#define B_AX_CH10_THR_WP_SH 16 +#define B_AX_CH10_THR_WP_MSK 0xfff +#define B_AX_CH10_THR_WD_SH 0 +#define B_AX_CH10_THR_WD_MSK 0xfff + +#define R_AX_CH11_THR 0x8ADC +#define B_AX_CH11_INTRPT_EN BIT(31) +#define B_AX_CH11_THR_WP_SH 16 +#define B_AX_CH11_THR_WP_MSK 0xfff +#define B_AX_CH11_THR_WD_SH 0 +#define B_AX_CH11_THR_WD_MSK 0xfff + +// +// HCI FC 8852C +// +#define R_AX_HCI_FC_CTRL_V1 0x1700 + +#define R_AX_CH_PAGE_CTRL_V1 0x1704 + +#define R_AX_ACH011_INTRPT_STAT_V1 0x1708 + +#define R_AX_HCI_FC_ERR_FLAG_V1 0x170C + +#define R_AX_ACH0_PAGE_CTRL_V1 0x1710 + +#define R_AX_ACH1_PAGE_CTRL_V1 0x1714 + +#define R_AX_ACH2_PAGE_CTRL_V1 0x1718 + +#define R_AX_ACH3_PAGE_CTRL_V1 0x171C + +#define R_AX_ACH4_PAGE_CTRL_V1 0x1720 + +#define R_AX_ACH5_PAGE_CTRL_V1 0x1724 + +#define R_AX_ACH6_PAGE_CTRL_V1 0x1728 + +#define R_AX_ACH7_PAGE_CTRL_V1 0x172C + +#define R_AX_CH8_PAGE_CTRL_V1 0x1730 + +#define R_AX_CH9_PAGE_CTRL_V1 0x1734 + +#define R_AX_CH10_PAGE_CTRL_V1 0x1738 + +#define R_AX_CH11_PAGE_CTRL_V1 0x173C + +#define R_AX_ACH0_PAGE_INFO_V1 0x1750 + +#define R_AX_ACH1_PAGE_INFO_V1 0x1754 + +#define R_AX_ACH2_PAGE_INFO_V1 0x1758 + +#define R_AX_ACH3_PAGE_INFO_V1 0x175C + +#define R_AX_ACH4_PAGE_INFO_V1 0x1760 + +#define R_AX_ACH5_PAGE_INFO_V1 0x1764 + +#define R_AX_ACH6_PAGE_INFO_V1 0x1768 + +#define R_AX_ACH7_PAGE_INFO_V1 0x176C + +#define R_AX_CH8_PAGE_INFO_V1 0x1770 + +#define R_AX_CH9_PAGE_INFO_V1 0x1774 + +#define R_AX_CH10_PAGE_INFO_V1 0x1778 + +#define R_AX_CH11_PAGE_INFO_V1 0x177C + +#define R_AX_CH12_PAGE_INFO_V1 0x1780 + +#define R_AX_PUB_PAGE_INFO3_V1 0x178C + +#define R_AX_PUB_PAGE_CTRL1_V1 0x1790 + +#define R_AX_PUB_PAGE_CTRL2_V1 0x1794 + +#define R_AX_PUB_PAGE_INFO1_V1 0x1798 + +#define R_AX_PUB_PAGE_INFO2_V1 0x179C + +#define R_AX_WP_PAGE_CTRL1_V1 0x17A0 + +#define R_AX_WP_PAGE_CTRL2_V1 0x17A4 + +#define R_AX_WP_PAGE_INFO1_V1 0x17A8 + +#define R_AX_ACH0_THR_V1 0x17B0 + +#define R_AX_ACH1_THR_V1 0x17B4 + +#define R_AX_ACH2_THR_V1 0x17B8 + +#define R_AX_ACH3_THR_V1 0x17BC + +#define R_AX_ACH4_THR_V1 0x17C0 + +#define R_AX_ACH5_THR_V1 0x17C4 + +#define R_AX_ACH6_THR_V1 0x17C8 + +#define R_AX_ACH7_THR_V1 0x17CC + +#define R_AX_CH8_THR_V1 0x17D0 + +#define R_AX_CH9_THR_V1 0x17D4 + +#define R_AX_CH10_THR_V1 0x17D8 + +#define R_AX_CH11_THR_V1 0x17DC + +// +// WDE_DLE +// + +#define R_AX_WDE_PKTBUF_CFG 0x8C08 +#define B_AX_WDE_FREE_PAGE_NUM_SH 16 +#define B_AX_WDE_FREE_PAGE_NUM_MSK 0x1fff +#define B_AX_WDE_START_BOUND_SH 8 +#define B_AX_WDE_START_BOUND_MSK 0x3f +#define B_AX_WDE_PAGE_SEL_SH 0 +#define B_AX_WDE_PAGE_SEL_MSK 0x3 + +#define R_AX_WDE_ERR_FLAG_CFG 0x8C34 +#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2) +#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1) +#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0) + +#define R_AX_WDE_ERR_IMR 0x8C38 +#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) +#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) +#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) +#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) +#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) +#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) +#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) +#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) +#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) +#define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13) +#define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12) +#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) +#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6) +#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5) +#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) +#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3) +#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) +#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) +#define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0) + +#define R_AX_WDE_ERR_ISR 0x8C3C +#define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26) +#define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25) +#define B_AX_WDE_DATCHN_ARBT_ERR BIT(24) +#define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19) +#define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18) +#define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17) +#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16) +#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15) +#define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14) +#define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13) +#define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12) +#define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7) +#define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6) +#define B_AX_WDE_GETNPG_STRPG_ERR BIT(5) +#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4) +#define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3) +#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2) +#define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1) +#define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0) + +#define R_AX_WDE_QTA0_CFG 0x8C40 +#define B_AX_WDE_Q0_MAX_SIZE_SH 16 +#define B_AX_WDE_Q0_MAX_SIZE_MSK 0xfff +#define B_AX_WDE_Q0_MIN_SIZE_SH 0 +#define B_AX_WDE_Q0_MIN_SIZE_MSK 0xfff + +#define R_AX_WDE_QTA1_CFG 0x8C44 +#define B_AX_WDE_Q1_MAX_SIZE_SH 16 +#define B_AX_WDE_Q1_MAX_SIZE_MSK 0xfff +#define B_AX_WDE_Q1_MIN_SIZE_SH 0 +#define B_AX_WDE_Q1_MIN_SIZE_MSK 0xfff + +#define R_AX_WDE_QTA2_CFG 0x8C48 +#define B_AX_WDE_Q2_MAX_SIZE_SH 16 +#define B_AX_WDE_Q2_MAX_SIZE_MSK 0xfff +#define B_AX_WDE_Q2_MIN_SIZE_SH 0 +#define B_AX_WDE_Q2_MIN_SIZE_MSK 0xfff + +#define R_AX_WDE_QTA3_CFG 0x8C4C +#define B_AX_WDE_Q3_MAX_SIZE_SH 16 +#define B_AX_WDE_Q3_MAX_SIZE_MSK 0xfff +#define B_AX_WDE_Q3_MIN_SIZE_SH 0 +#define B_AX_WDE_Q3_MIN_SIZE_MSK 0xfff + +#define R_AX_WDE_QTA4_CFG 0x8C50 +#define B_AX_WDE_Q4_MAX_SIZE_SH 16 +#define B_AX_WDE_Q4_MAX_SIZE_MSK 0xfff +#define B_AX_WDE_Q4_MIN_SIZE_SH 0 +#define B_AX_WDE_Q4_MIN_SIZE_MSK 0xfff + +#define R_AX_WDE_QTA5_CFG 0x8C54 + +#define R_AX_WDE_QTA6_CFG 0x8C58 + +#define R_AX_WDE_QTA7_CFG 0x8C5C + +#define R_AX_WDE_QTA8_CFG 0x8C60 + +#define R_AX_WDE_QTA9_CFG 0x8C64 + +#define R_AX_WDE_QTA10_CFG 0x8C68 + +#define R_AX_WDE_QTA11_CFG 0x8C6C + +#define R_AX_WDE_QTA12_CFG 0x8C70 + +#define R_AX_WDE_QTA13_CFG 0x8C74 + +#define R_AX_WDE_QTA14_CFG 0x8C78 + +#define R_AX_WDE_QTA15_CFG 0x8C7C + +#define R_AX_WDE_INI_STATUS 0x8D00 +#define B_AX_WDE_Q_MGN_INI_RDY BIT(1) +#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) + +#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 +#define B_AX_WDE_DFI_ACTIVE BIT(31) +#define B_AX_WDE_DFI_TRGSEL_SH 16 +#define B_AX_WDE_DFI_TRGSEL_MSK 0xf +#define B_AX_WDE_DFI_ADDR_SH 0 +#define B_AX_WDE_DFI_ADDR_MSK 0xffff + +#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 +#define B_AX_WDE_DFI_DATA_SH 0 +#define B_AX_WDE_DFI_DATA_MSK 0xffffffffL + +#define R_AX_WDE_DBG_CTL 0x8D18 +#define B_AX_WDE_DBG1_SEL_SH 8 +#define B_AX_WDE_DBG1_SEL_MSK 0xff +#define B_AX_WDE_DBG0_SEL_SH 0 +#define B_AX_WDE_DBG0_SEL_MSK 0xff + +#define R_AX_DBG_OUT 0x8D1C +#define B_AX_WDE_DBG1_OUT_SH 16 +#define B_AX_WDE_DBG1_OUT_MSK 0xffff +#define B_AX_WDE_DBG0_OUT_SH 0 +#define B_AX_WDE_DBG0_OUT_MSK 0xffff + +#define R_AX_WDE_Q_STATUS_CFG 0x8D80 +#define B_AX_WDE_Q_STATUS_SEL_SH 0 +#define B_AX_WDE_Q_STATUS_SEL_MSK 0x7 + +#define R_AX_WDE_Q_STATUS_VAL 0x8D84 +#define B_AX_WDE_Q_STATUS_VAL_SH 0 +#define B_AX_WDE_Q_STATUS_VAL_MSK 0xffffffffL + +// +// PLE_DLE +// + +#define R_AX_PLE_PKTBUF_CFG 0x9008 +#define B_AX_PLE_FREE_PAGE_NUM_SH 16 +#define B_AX_PLE_FREE_PAGE_NUM_MSK 0x1fff +#define B_AX_PLE_START_BOUND_SH 8 +#define B_AX_PLE_START_BOUND_MSK 0x3f +#define B_AX_PLE_PAGE_SEL_SH 0 +#define B_AX_PLE_PAGE_SEL_MSK 0x3 + +#define R_AX_PLE_ERR_FLAG_CFG 0x9034 +#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2) +#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1) +#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0) + +#define R_AX_PLE_ERR_IMR 0x9038 +#define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26) +#define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25) +#define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24) +#define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) +#define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18) +#define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17) +#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) +#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) +#define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14) +#define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13) +#define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12) +#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) +#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6) +#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) +#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3) +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) +#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) +#define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0) + +#define R_AX_PLE_ERR_FLAG_ISR 0x903C +#define B_AX_PLE_DATCHN_FRZTO_ERR BIT(26) +#define B_AX_PLE_DATCHN_NULLPG_ERR BIT(25) +#define B_AX_PLE_DATCHN_ARBT_ERR BIT(24) +#define B_AX_PLE_QUEMGN_FRZTO_ERR BIT(19) +#define B_AX_PLE_NXTPKTLL_AD_ERR BIT(18) +#define B_AX_PLE_PREPKTLLT_AD_ERR BIT(17) +#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR BIT(16) +#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR BIT(15) +#define B_AX_PLE_QUE_SRCQUEID_ERR BIT(14) +#define B_AX_PLE_QUE_DSTQUEID_ERR BIT(13) +#define B_AX_PLE_QUE_CMDTYPE_ERR BIT(12) +#define B_AX_PLE_BUFMGN_FRZTO_ERR BIT(7) +#define B_AX_PLE_GETNPG_PGOFST_ERR BIT(6) +#define B_AX_PLE_GETNPG_STRPG_ERR BIT(5) +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR BIT(4) +#define B_AX_PLE_BUFRTN_SIZE_ERR BIT(3) +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR BIT(2) +#define B_AX_PLE_BUFREQ_UNAVAL_ERR BIT(1) +#define B_AX_PLE_BUFREQ_QTAID_ERR BIT(0) + +#define R_AX_PLE_QTA0_CFG 0x9040 +#define B_AX_PLE_Q0_MAX_SIZE_SH 16 +#define B_AX_PLE_Q0_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q0_MIN_SIZE_SH 0 +#define B_AX_PLE_Q0_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA1_CFG 0x9044 +#define B_AX_PLE_Q1_MAX_SIZE_SH 16 +#define B_AX_PLE_Q1_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q1_MIN_SIZE_SH 0 +#define B_AX_PLE_Q1_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA2_CFG 0x9048 +#define B_AX_PLE_Q2_MAX_SIZE_SH 16 +#define B_AX_PLE_Q2_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q2_MIN_SIZE_SH 0 +#define B_AX_PLE_Q2_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA3_CFG 0x904C +#define B_AX_PLE_Q3_MAX_SIZE_SH 16 +#define B_AX_PLE_Q3_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q3_MIN_SIZE_SH 0 +#define B_AX_PLE_Q3_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA4_CFG 0x9050 +#define B_AX_PLE_Q4_MAX_SIZE_SH 16 +#define B_AX_PLE_Q4_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q4_MIN_SIZE_SH 0 +#define B_AX_PLE_Q4_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA5_CFG 0x9054 +#define B_AX_PLE_Q5_MAX_SIZE_SH 16 +#define B_AX_PLE_Q5_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q5_MIN_SIZE_SH 0 +#define B_AX_PLE_Q5_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA6_CFG 0x9058 +#define B_AX_PLE_Q6_MAX_SIZE_SH 16 +#define B_AX_PLE_Q6_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q6_MIN_SIZE_SH 0 +#define B_AX_PLE_Q6_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA7_CFG 0x905C +#define B_AX_PLE_Q7_MAX_SIZE_SH 16 +#define B_AX_PLE_Q7_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q7_MIN_SIZE_SH 0 +#define B_AX_PLE_Q7_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA8_CFG 0x9060 +#define B_AX_PLE_Q8_MAX_SIZE_SH 16 +#define B_AX_PLE_Q8_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q8_MIN_SIZE_SH 0 +#define B_AX_PLE_Q8_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA9_CFG 0x9064 +#define B_AX_PLE_Q9_MAX_SIZE_SH 16 +#define B_AX_PLE_Q9_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q9_MIN_SIZE_SH 0 +#define B_AX_PLE_Q9_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA10_CFG 0x9068 +#define B_AX_PLE_Q10_MAX_SIZE_SH 16 +#define B_AX_PLE_Q10_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q10_MIN_SIZE_SH 0 +#define B_AX_PLE_Q10_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA11_CFG 0x906C +#define B_AX_PLE_Q11_MAX_SIZE_SH 16 +#define B_AX_PLE_Q11_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q11_MIN_SIZE_SH 0 +#define B_AX_PLE_Q11_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA12_CFG 0x9070 +#define B_AX_PLE_Q12_MAX_SIZE_SH 16 +#define B_AX_PLE_Q12_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q12_MIN_SIZE_SH 0 +#define B_AX_PLE_Q12_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA13_CFG 0x9074 +#define B_AX_PLE_Q13_MAX_SIZE_SH 16 +#define B_AX_PLE_Q13_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q13_MIN_SIZE_SH 0 +#define B_AX_PLE_Q13_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA14_CFG 0x9078 +#define B_AX_PLE_Q14_MAX_SIZE_SH 16 +#define B_AX_PLE_Q14_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q14_MIN_SIZE_SH 0 +#define B_AX_PLE_Q14_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_QTA15_CFG 0x907C +#define B_AX_PLE_Q15_MAX_SIZE_SH 16 +#define B_AX_PLE_Q15_MAX_SIZE_MSK 0xfff +#define B_AX_PLE_Q15_MIN_SIZE_SH 0 +#define B_AX_PLE_Q15_MIN_SIZE_MSK 0xfff + +#define R_AX_PLE_INI_STATUS 0x9100 +#define B_AX_PLE_Q_MGN_INI_RDY BIT(1) +#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) + +#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 +#define B_AX_PLE_DFI_ACTIVE BIT(31) +#define B_AX_PLE_DFI_TRGSEL_SH 16 +#define B_AX_PLE_DFI_TRGSEL_MSK 0xf +#define B_AX_PLE_DFI_ADDR_SH 0 +#define B_AX_PLE_DFI_ADDR_MSK 0xffff + +#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 +#define B_AX_PLE_DFI_DATA_SH 0 +#define B_AX_PLE_DFI_DATA_MSK 0xffffffffL + +#define R_AX_PLE_DBG_CTL 0x9118 +#define B_AX_PLE_DBG1_SEL_SH 8 +#define B_AX_PLE_DBG1_SEL_MSK 0xff +#define B_AX_PLE_DBG0_SEL_SH 0 +#define B_AX_PLE_DBG0_SEL_MSK 0xff + +#define R_AX_PLE_DBG_OUT 0x911C +#define B_AX_PLE_DBG1_OUT_SH 16 +#define B_AX_PLE_DBG1_OUT_MSK 0xffff +#define B_AX_PLE_DBG0_OUT_SH 0 +#define B_AX_PLE_DBG0_OUT_MSK 0xffff + +// +// WDRLS +// + +#define R_AX_WDRLS_CFG 0x9408 +#define B_AX_RLSRPT_BUFREQ_TO_SH 8 +#define B_AX_RLSRPT_BUFREQ_TO_MSK 0xff +#define B_AX_WDRLS_MODE_SH 0 +#define B_AX_WDRLS_MODE_MSK 0x3 + +#define R_AX_RLSRPT0_CFG0 0x9410 +#define B_AX_RLSRPT0_FLTR_MAP_SH 24 +#define B_AX_RLSRPT0_FLTR_MAP_MSK 0xf +#define B_AX_RLSRPT0_PKTTYPE_SH 16 +#define B_AX_RLSRPT0_PKTTYPE_MSK 0xf +#define B_AX_RLSRPT0_PID_SH 8 +#define B_AX_RLSRPT0_PID_MSK 0x7 +#define B_AX_RLSRPT0_QID_SH 0 +#define B_AX_RLSRPT0_QID_MSK 0x3f + +#define R_AX_RLSRPT0_CFG1 0x9414 +#define B_AX_RLSRPT0_TO_SH 16 +#define B_AX_RLSRPT0_TO_MSK 0xff +#define B_AX_RLSRPT0_AGGNUM_SH 0 +#define B_AX_RLSRPT0_AGGNUM_MSK 0xff + +#define R_AX_RLSRPT1_CFG0 0x9420 +#define B_AX_RLSRPT1_FLTR_MAP_SH 24 +#define B_AX_RLSRPT1_FLTR_MAP_MSK 0xf +#define B_AX_RLSRPT1_PKTTYPE_SH 16 +#define B_AX_RLSRPT1_PKTTYPE_MSK 0xf +#define B_AX_RLSRPT1_PID_SH 8 +#define B_AX_RLSRPT1_PID_MSK 0x7 +#define B_AX_RLSRPT1_QID_SH 0 +#define B_AX_RLSRPT1_QID_MSK 0x3f + +#define R_AX_RLSRPT1_CFG1 0x9424 +#define B_AX_RLSRPT1_TO_SH 16 +#define B_AX_RLSRPT1_TO_MSK 0xff +#define B_AX_RLSRPT1_AGGNUM_SH 0 +#define B_AX_RLSRPT1_AGGNUM_MSK 0xff + +#define R_AX_WDRLS_ERR_IMR 0x9430 +#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) +#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) +#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) +#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) +#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) +#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) +#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) +#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) +#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) + +#define R_AX_WDRLS_ERR_ISR 0x9434 +#define B_AX_WDRLS_RPT1_FRZTO_ERR BIT(13) +#define B_AX_WDRLS_RPT1_AGGNUM_ERR BIT(12) +#define B_AX_WDRLS_RPT0_FRZTO_ERR BIT(9) +#define B_AX_WDRLS_RPT0_AGGNUM0_ERR BIT(8) +#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR BIT(5) +#define B_AX_WDRLS_PLEBREQ_TO_ERR BIT(4) +#define B_AX_WDRLS_CTL_FRZTO_ERR BIT(2) +#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR BIT(1) +#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR BIT(0) + +#define R_AX_DBG_CTL_WDRLS 0x9438 +#define B_AX_DBG1_SEL_SH 8 +#define B_AX_DBG1_SEL_MSK 0xff +#define B_AX_DBG0_SEL_SH 0 +#define B_AX_DBG0_SEL_MSK 0xff + +#define R_AX_DBG_OUT_WDRLS 0x943C +#define B_AX_DBG1_OUT_SH 16 +#define B_AX_DBG1_OUT_MSK 0xffff +#define B_AX_DBG0_OUT_SH 0 +#define B_AX_DBG0_OUT_MSK 0xffff + +// +// BBRPT +// + +#define R_AX_COM_CFG 0x9600 + +#define R_AX_BB_COEX_CFG 0x9604 +#define B_AX_DFS_THR_SH 8 +#define B_AX_DFS_THR_MSK 0xf +#define B_AX_BBRPT_COEX_EN BIT(0) + +#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C +#define B_AX_BBRPT_COM__NULL_PLPKTID_ERR BIT(16) +#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) + +#define R_AX_CH_INFO 0x9620 +#define B_AX_CH_INFO_QID_SH 24 +#define B_AX_CH_INFO_QID_MSK 0x3f +#define B_AX_CH_INFO_PRTID_SH 20 +#define B_AX_CH_INFO_PRTID_MSK 0x7 +#define B_AX_CH_INFO_REQ_SH 18 +#define B_AX_CH_INFO_REQ_MSK 0x3 +#define B_AX_CH_INFO_SEG_SH 16 +#define B_AX_CH_INFO_SEG_MSK 0x3 +#define B_AX_CH_INFO_INTVL_SH 12 +#define B_AX_CH_INFO_INTVL_MSK 0xf +#define B_AX_GET_CH_INFO_TO_SH 9 +#define B_AX_GET_CH_INFO_TO_MSK 0x7 +#define B_AX_CH_INFO_PHY BIT(8) +#define B_AX_CH_INFO_BUF_SH 6 +#define B_AX_CH_INFO_BUF_MSK 0x3 +#define B_AX_CH_INFO_STOP BIT(5) +#define B_AX_CH_INFO_STOP_REQ BIT(4) +#define B_AX_CH_INFO_ON BIT(3) +#define B_AX_CH_INFO_EN BIT(0) + +#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C +#define B_AX_BBPRT_CHIF_TO_ERR BIT(23) +#define B_AX_BBPRT_CHIF_NULL_ERR BIT(22) +#define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21) +#define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20) +#define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19) +#define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18) +#define B_AX_BBPRT_CHIF_OVF_ERR BIT(17) +#define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16) +#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) +#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) +#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) +#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) +#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) +#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) +#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) +#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) + +#define R_AX_DFS_CFG0 0x9630 +#define B_AX_DFS_QID_SH 24 +#define B_AX_DFS_QID_MSK 0x3f +#define B_AX_DFS_PRTID_SH 20 +#define B_AX_DFS_PRTID_MSK 0x7 +#define B_AX_DFS_TIME_TH_SH 10 +#define B_AX_DFS_TIME_TH_MSK 0x3 +#define B_AX_DFS_NUM_TH_SH 8 +#define B_AX_DFS_NUM_TH_MSK 0x3 +#define B_AX_DFS_BUF_SH 6 +#define B_AX_DFS_BUF_MSK 0x3 +#define B_AX_DFS_IN_STOP BIT(5) +#define B_AX_STOP_DFS BIT(4) +#define B_AX_DFS_RPT_EN BIT(0) + +#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C +#define B_AX_BBRPT_DFS_TO_ERR BIT(16) +#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) + +#define R_AX_LA_CFG 0x9660 +#define B_AX_LA_TRIG_TIME_VAL_SH 24 +#define B_AX_LA_TRIG_TIME_VAL_MSK 0x7f +#define B_AX_LA_TRIG_TU_SEL_SH 20 +#define B_AX_LA_TRIG_TU_SEL_MSK 0xf +#define B_AX_LA_BUF_SEL_SH 16 +#define B_AX_LA_BUF_SEL_MSK 0xf +#define B_AX_LA_BUF_BNDY_SH 8 +#define B_AX_LA_BUF_BNDY_MSK 0x3f +#define B_AX_LA_TO_VAL_SH 6 +#define B_AX_LA_TO_VAL_MSK 0x3 +#define B_AX_LA_TO_EN BIT(5) +#define B_AX_LA_RESTART_EN BIT(4) +#define B_AX_LA_TRIG_START BIT(3) +#define B_AX_LA_FEN BIT(0) + +#define R_AX_LA_STATUS 0x9664 +#define B_AX_LA_SW_FSMST_SH 17 +#define B_AX_LA_SW_FSMST_MSK 0x7 +#define B_AX_LA_BUF_RNDUP BIT(16) +#define B_AX_LA_BUF_WPTR_SH 0 +#define B_AX_LA_BUF_WPTR_MSK 0xFFFF + +#define R_AX_LA_ERRFLAG 0x966C +#define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16) +#define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0) + +// +// CPUIO +// + +#define R_AX_WD_BUF_REQ 0x9800 +#define B_AX_WD_BUF_REQ_EXEC BIT(31) +#define B_AX_WD_BUF_REQ_QUOTA_ID_SH 16 +#define B_AX_WD_BUF_REQ_QUOTA_ID_MSK 0xff +#define B_AX_WD_BUF_REQ_LEN_SH 0 +#define B_AX_WD_BUF_REQ_LEN_MSK 0xffff + +#define R_AX_WD_BUF_STATUS 0x9804 +#define B_AX_WD_BUF_STAT_DONE BIT(31) +#define B_AX_WD_BUF_STAT_PKTID_SH 0 +#define B_AX_WD_BUF_STAT_PKTID_MSK 0xfff + +#define R_AX_WD_QUOTA_STATUS 0x9808 + +#define R_AX_WD_CPUQ_OP_0 0x9810 +#define B_AX_WD_CPUQ_OP_EXEC BIT(31) +#define B_AX_WD_CPUQ_OP_CMD_TYPE_SH 24 +#define B_AX_WD_CPUQ_OP_CMD_TYPE_MSK 0xf +#define B_AX_WD_CPUQ_OP_MACID_SH 16 +#define B_AX_WD_CPUQ_OP_MACID_MSK 0xff +#define B_AX_WD_CPUQ_OP_PKTNUM_SH 0 +#define B_AX_WD_CPUQ_OP_PKTNUM_MSK 0xff + +#define R_AX_WD_CPUQ_OP_1 0x9814 +#define B_AX_WD_CPUQ_OP_SRC_PID_SH 22 +#define B_AX_WD_CPUQ_OP_SRC_PID_MSK 0x7 +#define B_AX_WD_CPUQ_OP_SRC_QID_SH 16 +#define B_AX_WD_CPUQ_OP_SRC_QID_MSK 0x3f +#define B_AX_WD_CPUQ_OP_DST_PID_SH 6 +#define B_AX_WD_CPUQ_OP_DST_PID_MSK 0x7 +#define B_AX_WD_CPUQ_OP_DST_QID_SH 0 +#define B_AX_WD_CPUQ_OP_DST_QID_MSK 0x3f + +#define R_AX_WD_CPUQ_OP_2 0x9818 +#define B_AX_WD_CPUQ_OP_STRT_PKTID_SH 16 +#define B_AX_WD_CPUQ_OP_STRT_PKTID_MSK 0xfff +#define B_AX_WD_CPUQ_OP_END_PKTID_SH 0 +#define B_AX_WD_CPUQ_OP_END_PKTID_MSK 0xfff + +#define R_AX_WD_CPUQ_OP_STATUS 0x981C +#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) +#define B_AX_WD_CPUQ_OP_PKTID_SH 0 +#define B_AX_WD_CPUQ_OP_PKTID_MSK 0xfff + +#define R_AX_PL_BUF_REQ 0x9820 +#define B_AX_PL_BUF_REQ_EXEC BIT(31) +#define B_AX_PL_BUF_REQ_QUOTA_ID_SH 16 +#define B_AX_PL_BUF_REQ_QUOTA_ID_MSK 0xf +#define B_AX_PL_BUF_REQ_LEN_SH 0 +#define B_AX_PL_BUF_REQ_LEN_MSK 0xffff + +#define R_AX_PL_BUF_STATUS 0x9824 +#define B_AX_PL_BUF_STAT_DONE BIT(31) +#define B_AX_PL_BUF_STAT_PKTID_SH 0 +#define B_AX_PL_BUF_STAT_PKTID_MSK 0xfff + +#define R_AX_PL_QUOTA_STATUS 0x9828 + +#define R_AX_PL_CPUQ_OP_0 0x9830 +#define B_AX_PL_CPUQ_OP_EXEC BIT(31) +#define B_AX_PL_CPUQ_OP_CMD_TYPE_SH 24 +#define B_AX_PL_CPUQ_OP_CMD_TYPE_MSK 0xf +#define B_AX_PL_CPUQ_OP_MACID_SH 16 +#define B_AX_PL_CPUQ_OP_MACID_MSK 0xff +#define B_AX_PL_CPUQ_OP_PKTNUM_SH 0 +#define B_AX_PL_CPUQ_OP_PKTNUM_MSK 0xff + +#define R_AX_PL_CPUQ_OP_1 0x9834 +#define B_AX_PL_CPUQ_OP_SRC_PID_SH 22 +#define B_AX_PL_CPUQ_OP_SRC_PID_MSK 0x7 +#define B_AX_PL_CPUQ_OP_SRC_QID_SH 16 +#define B_AX_PL_CPUQ_OP_SRC_QID_MSK 0x3f +#define B_AX_PL_CPUQ_OP_DST_PID_SH 6 +#define B_AX_PL_CPUQ_OP_DST_PID_MSK 0x7 +#define B_AX_PL_CPUQ_OP_DST_QID_SH 0 +#define B_AX_PL_CPUQ_OP_DST_QID_MSK 0x3f + +#define R_AX_PL_CPUQ_OP_2 0x9838 +#define B_AX_PL_CPUQ_OP_STRT_PKTID_SH 16 +#define B_AX_PL_CPUQ_OP_STRT_PKTID_MSK 0xfff +#define B_AX_PL_CPUQ_OP_END_PKTID_SH 0 +#define B_AX_PL_CPUQ_OP_END_PKTID_MSK 0xfff + +#define R_AX_PL_CPUQ_OP_STATUS 0x983C +#define B_AX_PL_CPUQ_OP_STAT_DONE BIT(31) +#define B_AX_PL_CPUQ_OP_PKTID_SH 0 +#define B_AX_PL_CPUQ_OP_PKTID_MSK 0xfff + +#define R_AX_CPUIO_ERR_IMR 0x9840 +#define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12) +#define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8) +#define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4) +#define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0) + +#define R_AX_CPUIO_ERR_ISR 0x9844 +#define B_AX_PLEQUE_OP_ERR BIT(12) +#define B_AX_PLEBUF_OP_ERR BIT(8) +#define B_AX_ERR_WDEQUE_OP_ERR BIT(4) +#define B_AX_ERR_WDEBUF_OP_ERR BIT(0) + +#define R_AX_SEC_ERR_IMR_ISR 0x991C +#define B_AX_SEC_TRX_TIMEOUT_INT_EN BIT(3) +#define B_AX_SEC_RX_TIMEOUT_ISR BIT(2) +#define B_AX_SEC_TX_TIMEOUT_ISR BIT(1) + +// +// PKTIN +// + +#define R_AX_PKTIN_SETTING 0x9A00 +#define B_AX_WD_ADDR_INFO_LENGTH BIT(1) +#define B_AX_PKTIN_CLK_GATING_DIS BIT(0) + +#define R_AX_HWAMSDU_CTRL 0x9A04 +#define B_AX_MAX_AMSDU_NUM_SH 3 +#define B_AX_MAX_AMSDU_NUM_MSK 0x3 +#define B_AX_SINGLE_AMSDU BIT(2) +#define B_AX_HWAMSDU_EN BIT(0) + +#define R_AX_HWAMSDU_STATUS 0x9A08 +#define B_AX_AMSDU_PKT_SIZE_ERR BIT(31) +#define B_AX_AMSDU_EN_ERR BIT(30) +#define B_AX_AMSDU_ADDR_INFO_ERR BIT(29) + +#define R_AX_HW_SEQ_0_1 0x9A0C +#define B_AX_HW_SEQ1_SH 16 +#define B_AX_HW_SEQ1_MSK 0xfff +#define B_AX_HW_SEQ0_SH 0 +#define B_AX_HW_SEQ0_MSK 0xfff + +#define R_AX_HW_SEQ_2_3 0x9A10 +#define B_AX_HW_SEQ3_SH 16 +#define B_AX_HW_SEQ3_MSK 0xfff +#define B_AX_HW_SEQ2_SH 0 +#define B_AX_HW_SEQ2_MSK 0xfff + +#define R_AX_TXPKTIN_CTRL 0x9A14 +#define B_AX_C1P4_TXPKTIN_STS BIT(25) +#define B_AX_C1P3_TXPKTIN_STS BIT(24) +#define B_AX_C1P2_TXPKTIN_STS BIT(23) +#define B_AX_C1P1_TXPKTIN_STS BIT(22) +#define B_AX_C1P0_TXPKTIN_STS BIT(21) +#define B_AX_C0P4_TXPKTIN_STS BIT(20) +#define B_AX_C0P3_TXPKTIN_STS BIT(19) +#define B_AX_C0P2_TXPKTIN_STS BIT(18) +#define B_AX_C0P1_TXPKTIN_STS BIT(17) +#define B_AX_C0P0_TXPKTIN_STS BIT(16) +#define B_AX_TXPKTIN_CTRL_EN BIT(15) +#define B_AX_C1P4_TXPKTIN_EN BIT(9) +#define B_AX_C1P3_TXPKTIN_EN BIT(8) +#define B_AX_C1P2_TXPKTIN_EN BIT(7) +#define B_AX_C1P1_TXPKTIN_EN BIT(6) +#define B_AX_C1P0_TXPKTIN_EN BIT(5) +#define B_AX_C0P4_TXPKTIN_EN BIT(4) +#define B_AX_C0P3_TXPKTIN_EN BIT(3) +#define B_AX_C0P2_TXPKTIN_EN BIT(2) +#define B_AX_C0P1_TXPKTIN_EN BIT(1) +#define B_AX_C0P0_TXPKTIN_EN BIT(0) + +#define R_AX_TXPKTIN_DBG_SEL 0x9A18 +#define B_AX_TXPKTIN_DBG_SEL_SH 0 +#define B_AX_TXPKTIN_DBG_SEL_MSK 0xf + +#define R_AX_PKTIN_ERR_IMR 0x9A20 +#define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0) + +#define R_AX_PKTIN_ERR_ISR 0x9A24 +#define B_AX_PKTIN_GETPKTID_ERR_ISR BIT(0) + +// +// MPDU_Processor_1 +// + +#define R_AX_HDR_SHCUT_SETTING 0x9B00 +#define B_AX_MAC_MPDU_PROC_EN BIT(2) +#define B_AX_SHCUT_LLC_WR_LOCK BIT(1) +#define B_AX_SHCUT_PARSE_DASA BIT(0) + +#define R_AX_SHCUT_LLC_ETH_TYPE0 0x9B04 +#define B_AX_SHUT_ETH_TYPE1_SH 16 +#define B_AX_SHUT_ETH_TYPE1_MSK 0xffff +#define B_AX_SHUT_ETH_TYPE0_SH 0 +#define B_AX_SHUT_ETH_TYPE0_MSK 0xffff + +#define R_AX_SHCUT_LLC_ETH_TYPE1 0x9B08 +#define B_AX_SHUT_ETH_TYPE2_SH 0 +#define B_AX_SHUT_ETH_TYPE2_MSK 0xffff + +#define R_AX_SHCUT_LLC_OUI0 0x9B0C +#define B_AX_SHUT_ENABLE_OUI0 BIT(24) +#define B_AX_SHUT_ETH_OUI0_SH 0 +#define B_AX_SHUT_ETH_OUI0_MSK 0xffffff + +#define R_AX_SHCUT_LLC_OUI1 0x9B10 +#define B_AX_SHUT_ENABLE_OUI1 BIT(24) +#define B_AX_SHUT_ETH_OUI1_SH 0 +#define B_AX_SHUT_ETH_OUI1_MSK 0xffffff + +#define R_AX_SHCUT_LLC_OUI2 0x9B14 +#define B_AX_SHUT_ENABLE_OUI2 BIT(24) +#define B_AX_SHUT_ETH_OUI2_SH 0 +#define B_AX_SHUT_ETH_OUI2_MSK 0xffffff + +#define R_AX_SHCUT_LLC_OUI3 0x9B18 +#define B_AX_SHUT_ENABLE_OUI3 BIT(24) +#define B_AX_SHUT_ETH_OUI3_SH 0 +#define B_AX_SHUT_ETH_OUI3_MSK 0xffffff + +#define R_AX_TX_PTK_CNT 0x9BEC +#define B_AX_TX_PTKOUT_CNT_SH 16 +#define B_AX_TX_PTKOUT_CNT_MSK 0xffff +#define B_AX_TX_PKTIN_CNT_SH 0 +#define B_AX_TX_PKTIN_CNT_MSK 0xffff + +#define R_AX_MPDU_TX_ERR_ISR 0x9BF0 +#define B_AX_TX_HDR3_SIZE_ERR BIT(5) +#define B_AX_TX_OFFSET_ERR BIT(4) +#define B_AX_TX_MPDU_SIZE_ZERO_ERR BIT(3) +#define B_AX_TX_NXT_ERRPKTID_ERR BIT(2) +#define B_AX_TX_GET_ERRPKTID_ERR BIT(1) + +#define R_AX_MPDU_TX_ERR_IMR 0x9BF4 +#define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5) +#define B_AX_TX_OFFSET_ERR_INT_EN BIT(4) +#define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3) +#define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2) +#define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1) + +#define R_AX_MPDU_TX_DBG 0x9BFC +#define B_AX_MPDU_TX_DBGEN BIT(8) +#define B_AX_MPDU_TX_DLAST BIT(0) + +// +// MPDU_Processor_2 +// + +#define R_AX_MPDU_PROC 0x9C00 +#define B_AX_A_ICV_ERR BIT(1) +#define B_AX_APPEND_FCS BIT(0) + +#define R_AX_ACTION_FWD0 0x9C04 +#define B_AX_FWD_VHT_CBFM_SH 24 +#define B_AX_FWD_VHT_CBFM_MSK 0x3 +#define B_AX_FWD_HT_CBFM_SH 22 +#define B_AX_FWD_HT_CBFM_MSK 0x3 +#define B_AX_FWD_CSI_SH 20 +#define B_AX_FWD_CSI_MSK 0x3 +#define B_AX_FWD_OP_MODE_SH 18 +#define B_AX_FWD_OP_MODE_MSK 0x3 +#define B_AX_FWD_GID_MGNT_SH 16 +#define B_AX_FWD_GID_MGNT_MSK 0x3 +#define B_AX_FWD_NCW_SH 14 +#define B_AX_FWD_NCW_MSK 0x3 +#define B_AX_FWD_DELBA_SH 12 +#define B_AX_FWD_DELBA_MSK 0x3 +#define B_AX_FWD_ADDBA_RES_SH 10 +#define B_AX_FWD_ADDBA_RES_MSK 0x3 +#define B_AX_FWD_ADDBA_REQ_SH 8 +#define B_AX_FWD_ADDBA_REQ_MSK 0x3 +#define B_AX_FWD_DELTS_SH 6 +#define B_AX_FWD_DELTS_MSK 0x3 +#define B_AX_FWD_ADDTS_RES_SH 4 +#define B_AX_FWD_ADDTS_RES_MSK 0x3 +#define B_AX_FWD_ADDTS_REQ_SH 2 +#define B_AX_FWD_ADDTS_REQ_MSK 0x3 +#define B_AX_FWD_CSA_SH 0 +#define B_AX_FWD_CSA_MSK 0x3 + +#define R_AX_ACTION_FWD1 0x9C08 +#define B_AX_FWD_ACTN_CTRL3_SH 6 +#define B_AX_FWD_ACTN_CTRL3_MSK 0x3 +#define B_AX_FWD_ACTN_CTRL2_SH 4 +#define B_AX_FWD_ACTN_CTRL2_MSK 0x3 +#define B_AX_FWD_ACTN_CTRL1_SH 2 +#define B_AX_FWD_ACTN_CTRL1_MSK 0x3 +#define B_AX_FWD_ACTN_CTRL0_SH 0 +#define B_AX_FWD_ACTN_CTRL0_MSK 0x3 + +#define R_AX_ACTION_FWD_CTRL0 0x9C0C +#define B_AX_FWD_ACTN_ACTN0_SH 8 +#define B_AX_FWD_ACTN_ACTN0_MSK 0xff +#define B_AX_FWD_ACTN_CAT0_SH 0 +#define B_AX_FWD_ACTN_CAT0_MSK 0xff + +#define R_AX_ACTION_FWD_CTRL1 0x9C0E +#define B_AX_FWD_ACTN_ACTN1_SH 8 +#define B_AX_FWD_ACTN_ACTN1_MSK 0xff +#define B_AX_FWD_ACTN_CAT1_SH 0 +#define B_AX_FWD_ACTN_CAT1_MSK 0xff + +#define R_AX_ACTION_FWD_CTRL2 0x9C10 +#define B_AX_FWD_ACTN_ACTN2_SH 8 +#define B_AX_FWD_ACTN_ACTN2_MSK 0xff +#define B_AX_FWD_ACTN_CAT2_SH 0 +#define B_AX_FWD_ACTN_CAT2_MSK 0xff + +#define R_AX_ACTION_FWD_CTRL3 0x9C12 +#define B_AX_FWD_ACTN_ACTN3_SH 8 +#define B_AX_FWD_ACTN_ACTN3_MSK 0xff +#define B_AX_FWD_ACTN_CAT3_SH 0 +#define B_AX_FWD_ACTN_CAT3_MSK 0xff + +#define R_AX_TF_FWD 0x9C14 +#define B_AX_FWD_TF15_SH 30 +#define B_AX_FWD_TF15_MSK 0x3 +#define B_AX_FWD_TF14_SH 28 +#define B_AX_FWD_TF14_MSK 0x3 +#define B_AX_FWD_TF13_SH 26 +#define B_AX_FWD_TF13_MSK 0x3 +#define B_AX_FWD_TF12_SH 24 +#define B_AX_FWD_TF12_MSK 0x3 +#define B_AX_FWD_TF11_SH 22 +#define B_AX_FWD_TF11_MSK 0x3 +#define B_AX_FWD_TF10_SH 20 +#define B_AX_FWD_TF10_MSK 0x3 +#define B_AX_FWD_TF9_SH 18 +#define B_AX_FWD_TF9_MSK 0x3 +#define B_AX_FWD_TF8_SH 16 +#define B_AX_FWD_TF8_MSK 0x3 +#define B_AX_FWD_TF7_SH 14 +#define B_AX_FWD_TF7_MSK 0x3 +#define B_AX_FWD_TF6_SH 12 +#define B_AX_FWD_TF6_MSK 0x3 +#define B_AX_FWD_TF5_SH 10 +#define B_AX_FWD_TF5_MSK 0x3 +#define B_AX_FWD_TF4_SH 8 +#define B_AX_FWD_TF4_MSK 0x3 +#define B_AX_FWD_TF3_SH 6 +#define B_AX_FWD_TF3_MSK 0x3 +#define B_AX_FWD_TF2_SH 4 +#define B_AX_FWD_TF2_MSK 0x3 +#define B_AX_FWD_TF1_SH 2 +#define B_AX_FWD_TF1_MSK 0x3 +#define B_AX_FWD_TF0_SH 0 +#define B_AX_FWD_TF0_MSK 0x3 + +#define R_AX_HW_RPT_FWD 0x9C18 +#define B_AX_FWD_TX_PLD_REL_WCPU_SH 16 +#define B_AX_FWD_TX_PLD_REL_WCPU_MSK 0x3 +#define B_AX_FWD_DFS_RPT_SH 14 +#define B_AX_FWD_DFS_RPT_MSK 0x3 +#define B_AX_FWD_TX_PLD_REL_HOST_SH 12 +#define B_AX_FWD_TX_PLD_REL_HOST_MSK 0x3 +#define B_AX_FWD_TX_RPT_SH 10 +#define B_AX_FWD_TX_RPT_MSK 0x3 +#define B_AX_FWD_SS2FW_RPT_SH 8 +#define B_AX_FWD_SS2FW_RPT_MSK 0x3 +#define B_AX_FWD_F2P_TX_CMD_RPT_SH 6 +#define B_AX_FWD_F2P_TX_CMD_RPT_MSK 0x3 +#define B_AX_FWD_BB_SCOPE_MODE_SH 4 +#define B_AX_FWD_BB_SCOPE_MODE_MSK 0x3 +#define B_AX_FWD_CH_INFO_SH 2 +#define B_AX_FWD_CH_INFO_MSK 0x3 +#define B_AX_FWD_PPDU_STAT_SH 0 +#define B_AX_FWD_PPDU_STAT_MSK 0x3 + +#define R_AX_PLD_CAM_CTRL 0x9C1C +#define B_AX_PLD_CAM_EN BIT(7) +#define B_AX_PLD_CAM_ACC BIT(4) +#define B_AX_PLD_CAM_RANGE_SH 0 +#define B_AX_PLD_CAM_RANGE_MSK 0xf + +#define R_AX_PLD_CAM_ACCESS 0x9C20 +#define B_AX_PLD_CAM_POLL BIT(31) +#define B_AX_PLD_CAM_RW BIT(30) +#define B_AX_PLD_CAM_CLR BIT(29) +#define B_AX_PLD_CAM_OFFSET_SH 0 +#define B_AX_PLD_CAM_OFFSET_MSK 0xffff + +#define R_AX_PLD_CAM_RDATA 0x9C24 +#define B_AX_PLD_CAM_RDATA_SH 0 +#define B_AX_PLD_CAM_RDATA_MSK 0xffffffffL + +#define R_AX_PLD_CAM_WDATA 0x9C28 +#define B_PLD_CAM_WDATA_SH 0 +#define B_PLD_CAM_WDATA_MSK 0xffffffffL + +#define R_AX_CUT_AMSDU_CTRL 0x9C40 +#define B_AX_BIT_EN_CUT_AMSDU BIT(30) +#define B_AX_BIT_CUT_AMSDU_CHKLEN_EN BIT(24) +#define B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH_SH 16 +#define B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH_MSK 0xff +#define B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH_SH 0 +#define B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH_MSK 0xffff + +#define R_AX_CUT_AMSDU_CTRL_2 0x9C44 +#define B_AX_MSDU_DROP_SEQUENCE_NUMBER_SH 20 +#define B_AX_MSDU_DROP_SEQUENCE_NUMBER_MSK 0xfff +#define B_AX_MSDU_DROP BIT(19) +#define B_AX_EXTRA_SHIFT_SH 17 +#define B_AX_EXTRA_SHIFT_MSK 0x3 + +#define R_AX_REG_ERROR_MON 0x9C48 +#define B_AX_BIT_MACRX_ERR_5 BIT(21) + +#define R_AX_WOW_CTRL 0x9C50 +#define B_AX_WOW_HCI BIT(5) +#define B_AX_WOW_DROP BIT(2) +#define B_AX_WOW_WOWEN BIT(1) +#define B_AX_WOW_WOWEN_SH 1 +#define B_AX_WOW_FORCE_WAKEUP BIT(0) + +#define R_AX_MPDU_RX_PKTCNT 0x9CE8 +#define B_AX_RX_PKTOUT_CNT_SH 16 +#define B_AX_RX_PKTOUT_CNT_MSK 0xffff +#define B_AX_RX_PKTIN_CNT_SH 0 +#define B_AX_RX_PKTIN_CNT_MSK 0xffff + +#define R_AX_MPDU_DROP_PKTCNT 0x9CEC +#define B_AX_DROP_PKTCNT_SH 0 +#define B_AX_DROP_PKTCNT_MSK 0xffff + +#define R_AX_MPDU_RX_ERR_ISR 0x9CF0 +#define B_AX_RPT_ERR_ISR BIT(3) +#define B_AX_MHDRLEN_ERR_ISR BIT(1) +#define B_AX_GETPKTID_ERR_ISR BIT(0) + +#define R_AX_MPDU_RX_ERR_IMR 0x9CF4 +#define B_AX_RPT_ERR_INT_EN BIT(3) +#define B_AX_MHDRLEN_ERR_INT_EN BIT(1) +#define B_AX_GETPKTID_ERR_INT_EN BIT(0) + +#define R_AX_MPDU_RX_DBG 0x9CF8 +#define B_AX_MPDU_RX_CKEN_DIS BIT(15) +#define B_AX_MPDU_RX_DBG_EN BIT(8) +#define B_AX_MPDU_RX_D_LAST_EN BIT(0) + +// +// SEC_ENG +// + +#define R_AX_SEC_ENG_CTRL 0x9D00 +#define B_AX_SEC_ENG_EN BIT(31) +#define B_AX_CCMP_SPP_MIC BIT(30) +#define B_AX_CCMP_SPP_CTR BIT(29) +#define B_AX_SEC_CAM_ACC BIT(28) +#define B_AX_SEC_CAM_CLK BIT(15) +#define B_AX_SEC_ENG_CLK BIT(14) +#define B_AX_RX_ICV_ERR BIT(13) +#define B_AX_TX_PARTIAL_MODE BIT(11) +#define B_AX_CLK_EN_CGCMP BIT(10) +#define B_AX_CLK_EN_WAPI BIT(9) +#define B_AX_CLK_EN_WEP_TKIP BIT(8) +#define B_AX_BMC_MGNT_DEC BIT(5) +#define B_AX_UC_MGNT_DEC BIT(4) +#define B_AX_MC_DEC BIT(3) +#define B_AX_BC_DEC BIT(2) +#define B_AX_SEC_RX_DEC BIT(1) +#define B_AX_SEC_TX_ENC BIT(0) + +#define R_AX_SEC_MPDU_PROC 0x9D04 +#define B_AX_APPEND_ICV BIT(1) +#define B_AX_APPEND_MIC BIT(0) + +#define R_AX_SEC_CAM_ACCESS 0x9D10 +#define B_AX_SEC_CAM_POLL BIT(15) +#define B_AX_SEC_CAM_RW BIT(14) +#define B_AX_SEC_CAM_ACC_FAIL BIT(13) +#define B_AX_SEC_CAM_OFFSET_SH 0 +#define B_AX_SEC_CAM_OFFSET_MSK 0x3ff + +#define R_AX_SEC_CAM_RDATA 0x9D14 +#define B_AX_SEC_CAM_RDATA_SH 0 +#define B_AX_SEC_CAM_RDATA_MSK 0xffffffffL + +#define R_AX_SEC_CAM_WDATA 0x9D18 +#define B_AX_SEC_CAM_WDATA_SH 0 +#define B_AX_SEC_CAM_WDATA_MSK 0xffffffffL + +#define R_AX_SEC_DEBUG 0x9D1C +#define B_AX_NON_SEC_SH 30 +#define B_AX_NON_SEC_MSK 0x3 +#define B_AX_TX_AMSDU_WAPI_SH 28 +#define B_AX_TX_AMSDU_WAPI_MSK 0x3 +#define B_AX__TX_AMSDU_RC4_SH 26 +#define B_AX__TX_AMSDU_RC4_MSK 0x3 +#define B_AX__TX_AMSDU__CCMP_GCMP_SH 24 +#define B_AX__TX_AMSDU__CCMP_GCMP_MSK 0x3 +#define B_AX_TX_WAPI_SH 22 +#define B_AX_TX_WAPI_MSK 0x3 +#define B_AX_TX_RC4_SH 20 +#define B_AX_TX_RC4_MSK 0x3 +#define B_AX_TX_CCMP_GCMP_SH 18 +#define B_AX_TX_CCMP_GCMP_MSK 0x3 +#define B_AX_RX_WAPI_SH 16 +#define B_AX_RX_WAPI_MSK 0x3 +#define B_AX_RX_RC4_SH 14 +#define B_AX_RX_RC4_MSK 0x3 +#define B_AX_RX_CCMP_GCMP_SH 12 +#define B_AX_RX_CCMP_GCMP_MSK 0x3 +#define B_AX_RX_PARSER_FSM_SH 8 +#define B_AX_RX_PARSER_FSM_MSK 0xf +#define B_AX_TX_PARSER_FSM_SH 4 +#define B_AX_TX_PARSER_FSM_MSK 0xf +#define B_AX_IMR_ERROR BIT(3) +#define B_AX_RX_HANG_ERROR BIT(2) +#define B_AX_TX_HANG_ERROR BIT(1) +#define B_AX_BYPASS_PKT BIT(0) + +#define R_AX_SEC_TX_DEBUG 0x9D20 +#define B_AX_TX_HANG BIT(22) +#define B_AX_TX_ENC_CLOCK_SH 6 +#define B_AX_TX_ENC_CLOCK_MSK 0xffff +#define B_AX_TX_SEC_TYPE_SH 2 +#define B_AX_TX_SEC_TYPE_MSK 0xf +#define B_AX_TX_EXKEY_ERROR BIT(1) +#define B_AX_TX_ENCRYPT BIT(0) + +#define R_AX_SEC_RX_DEBUG 0x9D24 +#define B_AX_RX_HANG BIT(31) +#define B_AX_RX_ENC_CLOCK_SH 15 +#define B_AX_RX_ENC_CLOCK_MSK 0xffff +#define B_AX_RX_SEC_TYPE_SH 11 +#define B_AX_RX_SEC_TYPE_MSK 0xf +#define B_AX_RX_MIC_ERROR BIT(10) +#define B_AX_RX_ICV_ERROR BIT(9) +#define B_AX_RX_EXKEY_INDEX_SH 1 +#define B_AX_RX_EXKEY_INDEX_MSK 0x7f +#define B_AX_RX_ENCRYPT BIT(0) + +#define R_AX_SEC_TRX_PKT_CNT 0x9D28 +#define B_AX_TX_PKT_CLR BIT(31) +#define B_AX_TX_PKT_CNT_SH 16 +#define B_AX_TX_PKT_CNT_MSK 0x7fff +#define B_AX_RX_PKT_CLR BIT(15) +#define B_AX_RX_PKT_CNT_SH 0 +#define B_AX_RX_PKT_CNT_MSK 0x7fff + +#define R_AX_SEC_TRX_BLK_CNT 0x9D2C +#define B_AX_TX_BLK_CNT_SH 16 +#define B_AX_TX_BLK_CNT_MSK 0xffff +#define B_AX_RX_BLK_CNT_SH 0 +#define B_AX_RX_BLK_CNT_MSK 0xffff + +// +// STA scheduler +// + +#define R_AX_SS_DBG_0 0x9E00 +#define B_AX_SS_PARAM_STAT_SH 24 +#define B_AX_SS_PARAM_STAT_MSK 0x7f +#define B_AX_SS_PC_STAT_SH 16 +#define B_AX_SS_PC_STAT_MSK 0x3f +#define B_AX_SS_SA_STAT_SH 8 +#define B_AX_SS_SA_STAT_MSK 0x3f +#define B_AX_SS_SS_INIT_DONE_0 BIT(7) +#define B_AX_SS_LM_STAT_SH 0 +#define B_AX_SS_LM_STAT_MSK 0x7f + +#define R_AX_SS_DBG_1 0x9E04 +#define B_AX_SS_DEL_STAT_SH 28 +#define B_AX_SS_DEL_STAT_MSK 0x3 +#define B_AX_SS_ADD_STAT_SH 24 +#define B_AX_SS_ADD_STAT_MSK 0x3 +#define B_AX_SS_ULRU_STAT_SH 16 +#define B_AX_SS_ULRU_STAT_MSK 0xf +#define B_AX_SS_DLTX_STAT_SH 8 +#define B_AX_SS_DLTX_STAT_MSK 0x1f +#define B_AX_SS_LEN_STAT_SH 0 +#define B_AX_SS_LEN_STAT_MSK 0x7f + +#define R_AX_SS_DBG_2 0x9E08 +#define B_AX_SS_PLEA_STAT_SH 24 +#define B_AX_SS_PLEA_STAT_MSK 0xf +#define B_AX_SS_WDEA_STAT_SH 16 +#define B_AX_SS_WDEA_STAT_MSK 0xf +#define B_AX_SS_RPTA_STAT_SH 8 +#define B_AX_SS_RPTA_STAT_MSK 0x3f +#define B_AX_SS_FWTX_STAT_SH 0 +#define B_AX_SS_FWTX_STAT_MSK 0x1f + +#define R_AX_SS_DBG_3 0x9E0C +#define B_AX_SS_CLK_GATE_DIS_SH 30 +#define B_AX_SS_CLK_GATE_DIS_MSK 0x3 +#define B_AX_SS_HW_ADD_LEN_OVF BIT(26) +#define B_AX_SS_SW_DECR_LEN_UDN BIT(25) +#define B_AX_SS_HW_DECR_LEN_UDN BIT(24) +#define B_AX_SS_ATM_ERR BIT(18) +#define B_AX_SS_DEL_STA_ERR BIT(17) +#define B_AX_SS_ADD_STA_ERR BIT(16) +#define B_AX_SS_LEN_INIT_DONE BIT(10) +#define B_AX_SS_PARAM_INIT_DONE BIT(9) +#define B_AX_SS_LINK_INIT_DONE BIT(8) +#define B_AX_SS_MOD_DBG_SEL_SH 4 +#define B_AX_SS_MOD_DBG_SEL_MSK 0x3 +#define B_AX_SS_TOP_DBG_SEL_SH 0 +#define B_AX_SS_TOP_DBG_SEL_MSK 0xf + +#define R_AX_SS_CTRL 0x9E10 +#define B_AX_SS_INIT_DONE_1 BIT(31) +#define B_AX_SS_HW_STA_DIS BIT(30) +#define B_AX_SS_WARM_INIT_FLG BIT(29) +#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28) +#define B_AX_SS_DELAY_TX_BAND_SEL_SH 24 +#define B_AX_SS_DELAY_TX_BAND_SEL_MSK 0x3 +#define B_AX_SS_WMM_SEL_3_SH 22 +#define B_AX_SS_WMM_SEL_3_MSK 0x3 +#define B_AX_SS_WMM_SEL_2_SH 20 +#define B_AX_SS_WMM_SEL_2_MSK 0x3 +#define B_AX_SS_WMM_SEL_1_SH 18 +#define B_AX_SS_WMM_SEL_1_MSK 0x3 +#define B_AX_SS_WMM_SEL_0_SH 16 +#define B_AX_SS_WMM_SEL_0_MSK 0x3 +#define B_AX_SS_HW_LEN_EN BIT(2) +#define B_AX_SS_HW_PARAM_EN BIT(1) +#define B_AX_SS_EN BIT(0) + +#define R_AX_SS_DL_QUOTA_CTRL 0x9E14 +#define B_AX_SS_QUOTA_MODE_3 BIT(31) +#define B_AX_SS_QUOTA_MODE_2 BIT(30) +#define B_AX_SS_QUOTA_MODE_1 BIT(29) +#define B_AX_SS_QUOTA_MODE_0 BIT(28) +#define B_AX_SS_DL_QUOTA_LOWER_LIMIT_SH 8 +#define B_AX_SS_DL_QUOTA_LOWER_LIMIT_MSK 0xff +#define B_AX_SS_DL_QUOTA_INIT_SH 0 +#define B_AX_SS_DL_QUOTA_INIT_MSK 0xf + +#define R_AX_SS_UL_QUOTA_CTRL 0x9E18 +#define B_AX_SS_QUOTA_MODE_UL BIT(31) +#define B_AX_SS_UL_QUOTA_LOWER_LIMIT_SH 8 +#define B_AX_SS_UL_QUOTA_LOWER_LIMIT_MSK 0xff +#define B_AX_SS_UL_QUOTA_INIT_SH 0 +#define B_AX_SS_UL_QUOTA_INIT_MSK 0xf + +#define R_AX_SS_BSR_CTRL 0x9E1C +#define B_AX_SS_BSR_THR_1_SH 16 +#define B_AX_SS_BSR_THR_1_MSK 0x3fff +#define B_AX_SS_BSR_THR_0_SH 0 +#define B_AX_SS_BSR_THR_0_MSK 0x3fff + +#define R_AX_SS_DL_RPT_CRTL 0x9E20 +#define B_AX_SS_TXOP_MODE_3 BIT(30) +#define B_AX_SS_TXOP_MODE_2 BIT(22) +#define B_AX_SS_TXOP_MODE_1 BIT(14) +#define B_AX_SS_TWT_MAX_SU_NUM_1_SH 11 +#define B_AX_SS_TWT_MAX_SU_NUM_1_MSK 0x7 +#define B_AX_SS_MAX_SU_NUM_1_SH 8 +#define B_AX_SS_MAX_SU_NUM_1_MSK 0x7 +#define B_AX_SS_TXOP_MODE_0 BIT(6) +#define B_AX_SS_TWT_MAX_SU_NUM_0_SH 3 +#define B_AX_SS_TWT_MAX_SU_NUM_0_MSK 0x7 +#define B_AX_SS_MAX_SU_NUM_0_SH 0 +#define B_AX_SS_MAX_SU_NUM_0_MSK 0x7 + +#define R_AX_SS_UL_RPT_CRTL 0x9E24 +#define B_AX_SS_MAX_RU_NUM_UL_SH 16 +#define B_AX_SS_MAX_RU_NUM_UL_MSK 0x3 +#define B_AX_SS_UL_WMM_SH 8 +#define B_AX_SS_UL_WMM_MSK 0x3 +#define B_AX_SS_TWT_MAX_SU_NUM_UL_SH 3 +#define B_AX_SS_TWT_MAX_SU_NUM_UL_MSK 0x7 +#define B_AX_SS_MAX_SU_NUM_UL_SH 0 +#define B_AX_SS_MAX_SU_NUM_UL_MSK 0x7 + +#define R_AX_SS_SEARCH_TO 0x9E28 +#define B_AX_SS_SEARCH_TO_SH 0 +#define B_AX_SS_SEARCH_TO_MSK 0xff + +#define R_AX_SS_SEARCH_LVL 0x9E2C +#define B_AX_SS_NEG_CNT_SH 16 +#define B_AX_SS_NEG_CNT_MSK 0xff +#define B_AX_SS_NEG_LVL_SH 0 +#define B_AX_SS_NEG_LVL_MSK 0xff + +#define R_AX_SS_SRAM_DATA 0x9E30 +#define B_AX_SS_SRAM_DATA_SH 0 +#define B_AX_SS_SRAM_DATA_MSK 0xffffffffL + +#define R_AX_SS_SRAM_W_EN 0x9E34 +#define B_AX_SS_SRAM_W_EN_SH 0 +#define B_AX_SS_SRAM_W_EN_MSK 0xffffffffL + +#define R_AX_SS_SRAM_CTRL_0 0x9E38 +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_RW BIT(23) +#define B_AX_SS_CMD_SH 20 +#define B_AX_SS_CMD_MSK 0x7 +#define B_AX_SS_OFFSET_SH 8 +#define B_AX_SS_OFFSET_MSK 0x3 +#define B_AX_SS_PARAM_SEL_SH 0 +#define B_AX_SS_PARAM_SEL_MSK 0xff + +#define R_AX_SS_LINK_INFO 0x9E3C +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_STATUS_SH 29 +#define B_AX_SS_STATUS_MSK 0x3 +#define B_AX_SS_UL BIT(28) +#define B_AX_SS_WMM_SH 26 +#define B_AX_SS_WMM_MSK 0x3 +#define B_AX_SS_AC_SH 24 +#define B_AX_SS_AC_MSK 0x3 +#define B_AX_SS_LINK_LEN_SH 16 +#define B_AX_SS_LINK_LEN_MSK 0xff +#define B_AX_SS_LINK_TAIL_SH 8 +#define B_AX_SS_LINK_TAIL_MSK 0xff +#define B_AX_SS_LINK_HEAD_SH 0 +#define B_AX_SS_LINK_HEAD_MSK 0xff + +#define R_AX_SS_LINK_ADD 0x9E40 +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_UL BIT(28) +#define B_AX_SS_MACID_2_SH 16 +#define B_AX_SS_MACID_2_MSK 0xff +#define B_AX_SS_MACID_1_SH 8 +#define B_AX_SS_MACID_1_MSK 0xff +#define B_AX_SS_MACID_0_SH 0 +#define B_AX_SS_MACID_0_MSK 0xff + +#define R_AX_SS_LINK_DEL 0x9E44 +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_UL BIT(28) + +#define R_AX_SS_LINK_SEARCH 0x9E48 +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_UL BIT(28) +#define B_AX_SS_TWT_GROUP_SH 20 +#define B_AX_SS_TWT_GROUP_MSK 0xf +#define B_AX_SS_MODE_SEL_SH 16 +#define B_AX_SS_MODE_SEL_MSK 0x3 + +#define R_AX_SS_SRAM_CTRL_1 0x9E4C +#define B_AX_SS_OWN BIT(31) +#define B_AX_SS_CMD_SEL_SH 26 +#define B_AX_SS_CMD_SEL_MSK 0x1f +#define B_AX_SS_VALUE_SH 8 +#define B_AX_SS_VALUE_MSK 0xffff + +#define R_AX_SS2FINFO_PATH 0x9E50 +#define B_AX_SS_UL_REL BIT(31) +#define B_AX_SS_REL_QUEUE_SH 24 +#define B_AX_SS_REL_QUEUE_MSK 0x3f +#define B_AX_SS_REL_PORT_SH 16 +#define B_AX_SS_REL_PORT_MSK 0x7 +#define B_AX_SS_DEST_QUEUE_SH 8 +#define B_AX_SS_DEST_QUEUE_MSK 0x3f +#define B_AX_SS_DEST_PORT_SH 0 +#define B_AX_SS_DEST_PORT_MSK 0x7 + +#define R_AX_WMM_LINK_EMPTY 0x9E54 +#define B_AX_WMM3_VO_LINK_EMPTY BIT(15) +#define B_AX_WMM3_VI_LINK_EMPTY BIT(14) +#define B_AX_WMM3_BK_LINK_EMPTY BIT(13) +#define B_AX_WMM3_BE_LINK_EMPTY BIT(12) +#define B_AX_WMM2_VO_LINK_EMPTY BIT(11) +#define B_AX_WMM2_VI_LINK_EMPTY BIT(10) +#define B_AX_WMM2_BK_LINK_EMPTY BIT(9) +#define B_AX_WMM2_BE_LINK_EMPTY BIT(8) +#define B_AX_WMM1_VO_LINK_EMPTY BIT(7) +#define B_AX_WMM1_VI_LINK_EMPTY BIT(6) +#define B_AX_WMM1_BK_LINK_EMPTY BIT(5) +#define B_AX_WMM1_BE_LINK_EMPTY BIT(4) +#define B_AX_WMM0_VO_LINK_EMPTY BIT(3) +#define B_AX_WMM0_VI_LINK_EMPTY BIT(2) +#define B_AX_WMM0_BK_LINK_EMPTY BIT(1) +#define B_AX_WMM0_BE_LINK_EMPTY BIT(0) + +#define R_AX_SS_DELAYTX_TO 0x9E60 +#define B_AX_SS_BEBK_TO_1_SH 24 +#define B_AX_SS_BEBK_TO_1_MSK 0xff +#define B_AX_SS_VOVI_TO_1_SH 16 +#define B_AX_SS_VOVI_TO_1_MSK 0xff +#define B_AX_SS_BEBK_TO_0_SH 8 +#define B_AX_SS_BEBK_TO_0_MSK 0xff +#define B_AX_SS_VOVI_TO_0_SH 0 +#define B_AX_SS_VOVI_TO_0_MSK 0xff + +#define R_AX_SS_DELAYTX_LEN_THR 0x9E70 +#define B_AX_SS_BEBK_LEN_THR_1_SH 24 +#define B_AX_SS_BEBK_LEN_THR_1_MSK 0xff +#define B_AX_SS_VOVI_LEN_THR_1_SH 16 +#define B_AX_SS_VOVI_LEN_THR_1_MSK 0xff +#define B_AX_SS_BEBK_LEN_THR_0_SH 8 +#define B_AX_SS_BEBK_LEN_THR_0_MSK 0xff +#define B_AX_SS_VOVI_LEN_THR_0_SH 0 +#define B_AX_SS_VOVI_LEN_THR_0_MSK 0xff + +#define R_AX_SS_MU_CTRL 0x9E80 +#define B_AX_SS_DLRU_STATE_SH 28 +#define B_AX_SS_DLRU_STATE_MSK 0xf +#define B_AX_SS_DLMU_STATE_SH 24 +#define B_AX_SS_DLMU_STATE_MSK 0xf +#define B_AX_SS_MU_OPT BIT(2) +#define B_AX_SS_SCORE_THR_SH 0 +#define B_AX_SS_SCORE_THR_MSK 0x3 + +#define R_AX_SS_MU_TBL_0 0x9E84 +#define B_AX_SS_MU_MACID_SH 11 +#define B_AX_SS_MU_MACID_MSK 0x7f +#define B_AX_SS_TBL_VLD BIT(10) +#define B_AX_SS_SCORE_0_SH 8 +#define B_AX_SS_SCORE_0_MSK 0x3 +#define B_AX_SS_SCORE_1_SH 6 +#define B_AX_SS_SCORE_1_MSK 0x3 +#define B_AX_SS_SCORE_2_SH 4 +#define B_AX_SS_SCORE_2_MSK 0x3 +#define B_AX_SS_SCORE_3_SH 2 +#define B_AX_SS_SCORE_3_MSK 0x3 +#define B_AX_SS_SCORE_4_SH 0 +#define B_AX_SS_SCORE_4_MSK 0x3 + +#define R_AX_SS_MU_TBL_1 0x9E88 +#define B_AX_SS_TBL_VLD BIT(10) + +#define R_AX_SS_MU_TBL_2 0x9E8C +#define B_AX_SS_TBL_VLD BIT(10) + +#define R_AX_SS_MU_TBL_3 0x9E90 +#define B_AX_SS_TBL_VLD BIT(10) + +#define R_AX_SS_MU_TBL_4 0x9E94 +#define B_AX_SS_TBL_VLD BIT(10) + +#define R_AX_SS_MU_TBL_5 0x9E98 +#define B_AX_SS_TBL_VLD BIT(10) + +#define R_AX_SS_DL_MU_RPT_CRTL 0x9E9C +#define B_AX_SS_TWT_MAX_MU_NUM_1_SH 12 +#define B_AX_SS_TWT_MAX_MU_NUM_1_MSK 0xf +#define B_AX_SS_MAX_MU_NUM_1_SH 8 +#define B_AX_SS_MAX_MU_NUM_1_MSK 0xf +#define B_AX_SS_TWT_MAX_MU_NUM_0_SH 4 +#define B_AX_SS_TWT_MAX_MU_NUM_0_MSK 0xf +#define B_AX_SS_MAX_MU_NUM_0_SH 0 +#define B_AX_SS_MAX_MU_NUM_0_MSK 0xf + +#define R_AX_SS_RU_CTRL 0x9EA0 +#define B_AX_SS_GROUP_VLD_SH 16 +#define B_AX_SS_GROUP_VLD_MSK 0xffff +#define B_AX_SS_RU_SEARCH_MODE_SH 0 +#define B_AX_SS_RU_SEARCH_MODE_MSK 0xf + +#define R_AX_SS_DL_RU_RPT_CRTL 0x9EA4 +#define B_AX_SS_TWT_MAX_RU_NUM_1_SH 12 +#define B_AX_SS_TWT_MAX_RU_NUM_1_MSK 0xf +#define B_AX_SS_MAX_RU_NUM_1_SH 8 +#define B_AX_SS_MAX_RU_NUM_1_MSK 0xf +#define B_AX_SS_TWT_MAX_RU_NUM_0_SH 4 +#define B_AX_SS_TWT_MAX_RU_NUM_0_MSK 0xf +#define B_AX_SS_MAX_RU_NUM_0_SH 0 +#define B_AX_SS_MAX_RU_NUM_0_MSK 0xf + +#define R_AX_SS_MACID_PAUSE_0 0x9EB0 +#define B_AX_SS_MACID31_0_PAUSE_SH 0 +#define B_AX_SS_MACID31_0_PAUSE_MSK 0xffffffffL + +#define R_AX_SS_MACID_PAUSE_1 0x9EB4 +#define B_AX_SS_MACID63_32_PAUSE_SH 0 +#define B_AX_SS_MACID63_32_PAUSE_MSK 0xffffffffL + +#define R_AX_SS_MACID_PAUSE_2 0x9EB8 +#define B_AX_SS_MACID95_64_PAUSE_SH 0 +#define B_AX_SS_MACID95_64_PAUSE_MSK 0xffffffffL + +#define R_AX_SS_MACID_PAUSE_3 0x9EBC +#define B_AX_SS_MACID127_96_PAUSE_SH 0 +#define B_AX_SS_MACID127_96_PAUSE_MSK 0xffffffffL + +#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 +#define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2) +#define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1) +#define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0) + +#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 +#define B_AX_PLE_B_PKTID_ERR_ISR BIT(2) +#define B_AX_RPT_HANG_TIMEOUT_ISR BIT(1) +#define B_AX_SEARCH_HANG_TIMEOUT_ISR BIT(0) + +// +// Tx Packet Controller +// + +#define R_AX_B0_CFG 0x9F10 +#define B_AX_B0_ATCPAR_REFTU_VAL_SH 8 +#define B_AX_B0_ATCPAR_REFTU_VAL_MSK 0xff +#define B_AX_B0_ATCTMR_REFTU_CYC_SH 4 +#define B_AX_B0_ATCTMR_REFTU_CYC_MSK 0x7 +#define B_AX_B0_DIS_ACGC BIT(0) + +#define R_AX_B0_CTL 0x9F14 +#define B_AX_B0_CMDPSR_CTLST_REQPS BIT(7) +#define B_AX_CMDPSR_CTLST_NXTST_SH 0 +#define B_AX_CMDPSR_CTLST_NXTST_MSK 0x1f + +#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C +#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25) +#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24) +#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19) +#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18) +#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17) +#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16) +#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) +#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8) +#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) +#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) +#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) +#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0) +#define B_AX_B1_ATCPAR_REFTU_VAL_SH 8 +#define B_AX_B1_ATCPAR_REFTU_VAL_MSK 0xff +#define B_AX_B1_ATCTMR_REFTU_CYC_SH 4 +#define B_AX_B1_ATCTMR_REFTU_CYC_MSK 0x7 +#define B_AX_B1_DIS_ACGC BIT(0) +#define B_AX_B1_CMDPSR_CTLST_REQPS BIT(7) +#define B_AX_B1_CMDPSR_CTLST_NXTST_SH 0 +#define B_AX_B1_CMDPSR_CTLST_NXTST_MSK 0x1f + +#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C +#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25) +#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24) +#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19) +#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18) +#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17) +#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16) +#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) +#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8) +#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) +#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) +#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) +#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0) + +#define R_AX_DBG_FUN_INTF_CTL 0x9F30 +#define B_AX_DFI_ACTIVE BIT(31) +#define B_AX_DFI_TRGSEL_SH 16 +#define B_AX_DFI_TRGSEL_MSK 0xf +#define B_AX_DFI_ADDR_SH 0 +#define B_AX_DFI_ADDR_MSK 0xffff + +#define R_AX_DBG_FUN_INTF_DATA 0x9F34 +#define B_AX_DFI_DATA_SH 0 +#define B_AX_DFI_DATA_MSK 0xffffffffL + +#define R_AX_DBG_CTL_TXPKT 0x9F38 +#define B_AX_TPC_DBG1_SEL_SH 16 +#define B_AX_TPC_DBG1_SEL_MSK 0xffff +#define B_AX_TPC_DBG0_SEL_SH 0 +#define B_AX_TPC_DBG0_SEL_MSK 0xffff + +#define R_AX_TPC_DBG_OUT 0x9F3C +#define B_AX_DBG1_OUT_SH 16 +#define B_AX_DBG1_OUT_MSK 0xffff +#define B_AX_DBG0_OUT_SH 0 +#define B_AX_DBG0_OUT_MSK 0xffff + +#define R_AX_TXPKTCTL_B0_CTL 0x9F44 +#define B_AX_B0_CTLST_IDLE BIT(1) +#define B_AX_B0_STOP_REQ BIT(0) + +#define R_AX_TXPKTCTL_B1_CTL 0x9F84 +#define B_AX_B1_CTLST_IDLE BIT(1) +#define B_AX_B1_STOP_REQ BIT(0) + +// +// WL_AX_Reg_AON.xls +// + +// +// AON +// + +#define R_AX_SYS_ISO_CTRL 0x0000 +#define B_AX_PWC_EV2EF_SH 14 +#define B_AX_PWC_EV2EF_MSK 0x3 +#define B_AX_PA33V_EN BIT(13) +#define B_AX_PA12V_EN BIT(12) +#define B_AX_UA33V_EN BIT(11) +#define B_AX_UA12V_EN BIT(10) +#define B_AX_ISO_RFDIO BIT(9) +#define B_AX_ISO_EB2CORE BIT(8) +#define B_AX_ISO_DIOE BIT(7) +#define B_AX_ISO_WLPON2PP BIT(6) +#define B_AX_ISO_IP2MAC_WA2PP BIT(5) +#define B_AX_ISO_PD2CORE BIT(4) +#define B_AX_ISO_PA2PCIE BIT(3) +#define B_AX_ISO_UD2CORE BIT(2) +#define B_AX_ISO_UA2USB BIT(1) +#define B_AX_ISO_WD2PP BIT(0) + +#define R_AX_SYS_FUNC_EN 0x0002 +#define B_AX_FEN_MREGEN BIT(15) +#define B_AX_FEN_HWPDN BIT(14) +#define B_AX_FEN_ELDR BIT(12) +#define B_AX_FEN_DCORE BIT(11) +#define B_AX_FEN_CPUEN BIT(10) +#define B_AX_FEN_DIOE BIT(9) +#define B_AX_FEN_PCIED BIT(8) +#define B_AX_FEN_PPLL BIT(7) +#define B_AX_FEN_PCIEA BIT(6) +#define B_AX_FEN_USBD BIT(4) +#define B_AX_FEN_UPLL BIT(3) +#define B_AX_FEN_USBA BIT(2) +#define B_AX_FEN_BB_GLB_RSTN BIT(1) +#define B_AX_FEN_BBRSTB BIT(0) + +#define R_AX_SYS_PW_CTRL 0x0004 +#define B_AX_SOP_ASWRM BIT(31) +#define B_AX_SOP_EASWR BIT(30) +#define B_AX_SOP_PWMM_DSWR BIT(29) +#define B_AX_SOP_EDSWR BIT(28) +#define B_AX_SOP_ACKF BIT(27) +#define B_AX_SOP_ERCK BIT(26) +#define B_AX_SOP_ANA_CLK_DIVISION_2 BIT(25) +#define B_AX_SOP_EXTL BIT(24) +#define B_AX_ROP_SWPR BIT(21) +#define B_AX_DIS_HW_LPLDM BIT(20) +#define B_AX_RDY_SYSPWR BIT(17) +#define B_AX_EN_WLON BIT(16) +#define B_AX_APDM_HPDN BIT(15) +#define B_AX_PSUS_OFF_CAPC_EN BIT(14) +#define B_AX_AFSM_PCIE_SUS_EN BIT(12) +#define B_AX_AFSM_WLSUS_EN BIT(11) +#define B_AX_APFM_SWLPS BIT(10) +#define B_AX_APFM_OFFMAC BIT(9) +#define B_AX_APFN_ONMAC BIT(8) +#define B_AX_CHIP_PDN_EN BIT(7) +#define B_AX_RDY_MACDIS BIT(6) +#define B_AX_SW_AFE_MODE BIT(4) +#define B_AX_PFM_WOWL BIT(3) +#define B_AX_WL_HCI_ALD BIT(1) +#define B_AX_EFUSE_LDALL BIT(0) + +#define R_AX_SYS_CLK_CTRL 0x0008 +#define B_AX_CPU_IDMEM_CLK_EN BIT(15) +#define B_AX_CPU_CLK_EN BIT(14) +#define B_AX_SYMR_AX_CLK_EN BIT(13) +#define B_AX_MAC_CLK_EN BIT(11) +#define B_AX_EXT_32K_EN BIT(8) +#define B_AX_WL_CLK_TEST BIT(7) +#define B_AX_LOADER_CLK_EN BIT(5) +#define B_AX_ANA_CLK_DIVISION_2 BIT(1) +#define B_AX_CNTD16V_EN BIT(0) + +#define R_AX_SYS_EEPROM_CTRL 0x000A +#define B_AX_AUTOLOAD_SUS BIT(5) + +#define R_AX_SYS_SWR_CTRL1 0x0010 +#define B_AX_SYM_CTRL_SPSANA_PWMFREQ BIT(11) +#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10) +#define B_AX_HW_AUTO_CTRL_EXT_SWR BIT(9) +#define B_AX_USE_INTERNAL_SWR_AND_LDO BIT(8) +#define B_AX_MAC_ID_EN BIT(7) +#define B_AX_OPTION_DIS_XTAL_BG BIT(2) + +#define R_AX_ANAPARSW_POW_MAC 0x0014 +#define B_AX_POW_LDO15 BIT(2) +#define B_AX_POW_SW_SPSANA BIT(1) +#define B_AX_POW_LDO14_SPSANA BIT(0) + +#define R_AX_ANAPARLDO_POW_MAC 0x0015 +#define B_AX_R_PD12_N_LDO BIT(5) +#define B_AX_POW_SW_SPSDIG BIT(1) +#define B_AX_POW_LDO14_SPSDIG BIT(0) + +#define R_AX_ANAPAR_POW_MAC 0x0016 +#define B_AX_POW_PC_LDO_PORT1 BIT(3) +#define B_AX_POW_PC_LDO_PORT0 BIT(2) +#define B_AX_POW_PLL_V1 BIT(1) +#define B_AX_POW_POWER_CUT_POW_LDO BIT(0) + +#define R_AX_ANAPAR_POW_XTAL 0x0017 +#define B_AX_POW_XTAL BIT(1) +#define B_AX_POW_BG BIT(0) + +#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018 +#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5) +#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6) + +#define R_AX_RSV_CTRL 0x001C +#define B_AX_HR_AX_DBG BIT(23) +#define B_AX_R_EN_HRST_PWRON BIT(8) +#define B_AX_LOCK_ALL_EN BIT(7) +#define B_AX_R_DIS_PRST BIT(6) +#define B_AX_WLOCK_1C_B6 BIT(5) +#define B_AX_WLOCK_40 BIT(4) +#define B_AX_WLOCK_08 BIT(3) +#define B_AX_WLOCK_04 BIT(2) +#define B_AX_WLOCK_00 BIT(1) +#define B_AX_WLOCK_ALL BIT(0) + +#define R_AX_RF_CTRL 0x001F +#define B_AX_S0_RFC_WO_0 BIT(7) +#define B_AX_S0_RFC_WT_0 BIT(6) +#define B_AX_S0_RFC_RSTB BIT(1) + +#define R_AX_AFE_LDO_CTRL 0x0020 +#define B_AX_R_SYM_WLPOFF_P4_PC_EN BIT(28) +#define B_AX_R_SYM_WLPOFF_P3_PC_EN BIT(27) +#define B_AX_R_SYM_WLPOFF_P2_PC_EN BIT(26) +#define B_AX_R_SYM_WLPOFF_P1_PC_EN BIT(25) +#define B_AX_R_SYM_WLPOFF_PC_EN BIT(24) +#define B_AX_AON_OFF_PC_EN BIT(23) +#define B_AX_R_SYM_WLPON_P3_PC_EN BIT(21) +#define B_AX_R_SYM_WLPON_P2_PC_EN BIT(20) +#define B_AX_R_SYM_WLPON_P1_PC_EN BIT(19) +#define B_AX_R_SYM_WLPON_PC_EN BIT(18) +#define B_AX_R_SYM_DIS_WPHYBBOFF_PC BIT(10) +#define B_AX_R_SYM_WLBBOFF1_P4_PC_EN BIT(9) +#define B_AX_R_SYM_WLBBOFF1_P3_PC_EN BIT(8) +#define B_AX_R_SYM_WLBBOFF1_P2_PC_EN BIT(7) +#define B_AX_R_SYM_WLBBOFF1_P1_PC_EN BIT(6) +#define B_AX_R_SYM_WLBBOFF_P4_PC_EN BIT(4) +#define B_AX_R_SYM_WLBBOFF_P3_PC_EN BIT(3) +#define B_AX_R_SYM_WLBBOFF_P2_PC_EN BIT(2) +#define B_AX_R_SYM_WLBBOFF_P1_PC_EN BIT(1) +#define B_AX_R_SYM_WLBBOFF_PC_EN BIT(0) + +#define R_AX_AFE_CTRL1 0x0024 +#define B_AX_WLCPU_CLK_SEL_SH 22 +#define B_AX_WLCPU_CLK_SEL_MSK 0x3 +#define B_AX_CMAC_CLK_SEL BIT(21) +#define B_AX_PLL_DIV_SEL BIT(20) +#define B_AX_DMEM3_PC_EN BIT(15) +#define B_AX_DMEM2_PC_EN BIT(14) +#define B_AX_DMEM1_PC_EN BIT(13) +#define B_AX_IMEM4_PC_EN BIT(12) +#define B_AX_IMEM3_PC_EN BIT(11) +#define B_AX_IMEM2_PC_EN BIT(10) +#define B_AX_IMEM1_PC_EN BIT(9) +#define B_AX_IMEM0_PC_EN BIT(8) +#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) +#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) +#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) +#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) +#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) + +#define R_AX_SYS_OCP_CTRL 0x0028 +#define B_AX_SPS_OCP_DIS BIT(31) +#define B_AX_SPS_OCP_TH_SH 16 +#define B_AX_SPS_OCP_TH_MSK 0x7fff +#define B_AX_OCP_WINDOW_SH 0 +#define B_AX_OCP_WINDOW_MSK 0xffff + +#define R_AX_SYSANA_OCP_CTRL 0x002C +#define B_AX_SPSANA_OCP_DIS BIT(31) +#define B_AX_SPSANA_OCP_TH_SH 16 +#define B_AX_SPSANA_OCP_TH_MSK 0x7fff +#define B_AX_OCPANA_WINDOW_SH 0 +#define B_AX_OCPANA_WINDOW_MSK 0xffff + +#define R_AX_EFUSE_CTRL 0x0030 +#define B_AX_EF_MODE_SEL_SH 30 +#define B_AX_EF_MODE_SEL_MSK 0x3 +#define B_AX_EF_RDY BIT(29) +#define B_AX_EF_COMP_RESULT BIT(28) +#define B_AX_EF_ADDR_SH 16 +#define B_AX_EF_ADDR_MSK 0x7ff +#define B_AX_EF_DATA_SH 0 +#define B_AX_EF_DATA_MSK 0xffff + +#define R_AX_EFUSE_TEST 0x0034 +#define B_AX_EF_CRES_SEL BIT(31) +#define B_AX_EF_SCAN_SADR_SH 19 +#define B_AX_EF_SCAN_SADR_MSK 0x7ff +#define B_AX_EF_SCAN_EADR_SH 8 +#define B_AX_EF_SCAN_EADR_MSK 0x7ff +#define B_AX_EF_SCAN_TRPT BIT(7) +#define B_AX_EF_SCAN_FTHR_SH 0 +#define B_AX_EF_SCAN_FTHR_MSK 0x7f + +#define R_AX_EFUSE_CTRL_1 0x0038 +#define B_AX_EF_PGPD_SH 28 +#define B_AX_EF_PGPD_MSK 0x7 +#define B_AX_EF_RDT BIT(27) +#define B_AX_EF_VDDQST_SH 24 +#define B_AX_EF_VDDQST_MSK 0x7 +#define B_AX_EF_PGTS_SH 20 +#define B_AX_EF_PGTS_MSK 0xf +#define B_AX_EF_PD_DIS BIT(11) +#define B_AX_EF_POR BIT(10) +#define B_AX_EF_CELL_SEL_SH 8 +#define B_AX_EF_CELL_SEL_MSK 0x3 + +#define R_AX_EFUSE_CTRL_1_V1 0x0038 +#define B_AX_EF_ENT BIT(31) +#define B_AX_EF_BURST BIT(19) +#define B_AX_EF_TEST_SEL_SH 16 +#define B_AX_EF_TEST_SEL_MSK 0x7 +#define B_AX_EF_TROW_EN BIT(15) +#define B_AX_EF_ERR_FLAG BIT(14) +#define B_AX_EF_DSB_EN BIT(11) +#define B_AX_PCIE_CALIB_EN_V1 BIT(12) +#define B_AX_WDT_WAKE_PCIE_EN BIT(10) +#define B_AX_WDT_WAKE_USB_EN BIT(9) + +#define R_AX_GPIO_MUXCFG 0x0040 +#define B_AX_BOOT_MODE BIT(19) +#define B_AX_WL_EECS_EXT_32K_SEL BIT(18) +#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) +#define B_AX_SECSIC_SEL BIT(16) +#define B_AX_ENHTP BIT(14) +#define B_AX_BT_AOD_GPIO3 BIT(13) +#define B_AX_ENSIC BIT(12) +#define B_AX_SIC_SWRST BIT(11) +#define B_AX_PO_WIFI_PTA_PINS BIT(10) +#define B_AX_PO_BT_PTA_PINS BIT(9) +#define B_AX_ENUARTTX BIT(8) +#define B_AX_BTMODE_SH 6 +#define B_AX_BTMODE_MSK 0x3 +#define B_AX_ENBT BIT(5) +#define B_AX_EROM_EN BIT(4) +#define B_AX_ENUARTRX BIT(2) +#define B_AX_GPIOSEL_SH 0 +#define B_AX_GPIOSEL_MSK 0x3 + +#define R_AX_GPIO_PIN_CTRL 0x0044 +#define B_AX_GPIO_MOD_7_TO_0_SH 24 +#define B_AX_GPIO_MOD_7_TO_0_MSK 0xff +#define B_AX_GPIO_IO_SEL_7_TO_0_SH 16 +#define B_AX_GPIO_IO_SEL_7_TO_0_MSK 0xff +#define B_AX_GPIO_OUT_7_TO_0_SH 8 +#define B_AX_GPIO_OUT_7_TO_0_MSK 0xff +#define B_AX_GPIO_IN_7_TO_0_SH 0 +#define B_AX_GPIO_IN_7_TO_0_MSK 0xff + +#define R_AX_GPIO_INTM 0x0048 +#define B_AX_EXTWOL_SEL BIT(17) +#define B_AX_EXTWOL_EN BIT(16) +#define B_AX_GPIOF_INT_MD BIT(15) +#define B_AX_GPIOE_INT_MD BIT(14) +#define B_AX_GPIOD_INT_MD BIT(13) +#define B_AX_GPIOC_INT_MD BIT(12) +#define B_AX_GPIOB_INT_MD BIT(11) +#define B_AX_GPIOA_INT_MD BIT(10) +#define B_AX_GPIO9_INT_MD BIT(9) +#define B_AX_GPIO8_INT_MD BIT(8) +#define B_AX_GPIO7_INT_MD BIT(7) +#define B_AX_GPIO6_INT_MD BIT(6) +#define B_AX_GPIO5_INT_MD BIT(5) +#define B_AX_GPIO4_INT_MD BIT(4) +#define B_AX_GPIO3_INT_MD BIT(3) +#define B_AX_GPIO2_INT_MD BIT(2) +#define B_AX_GPIO1_INT_MD BIT(1) +#define B_AX_GPIO0_INT_MD BIT(0) + +#define R_AX_LED_CFG 0x004C +#define B_AX_MAILBOX_1WIRE_GPIO_CFG BIT(31) +#define B_AX_BT_RF_GPIO_CFG BIT(30) +#define B_AX_BT_SDIO_INT_GPIO_CFG BIT(29) +#define B_AX_MAILBOX_3WIRE_GPIO_CFG BIT(28) +#define B_AX_GPIO13_14_WL_CTRL_EN BIT(22) +#define B_AX_LED2DIS BIT(21) +#define B_AX_LED2PL BIT(20) +#define B_AX_LED2SV BIT(19) +#define B_AX_LED2CM_SH 16 +#define B_AX_LED2CM_MSK 0x7 +#define B_AX_LED0LED1_RD_ONLY_SH 13 +#define B_AX_LED0LED1_RD_ONLY_MSK 0x3 + +#define R_AX_PWR_OPTION_CTRL 0x0050 +#define B_AX_DIS_LPS_WT_PDNSUS BIT(24) +#define B_AX_SYSON_DBG_PAD_E2 BIT(11) +#define B_AX_SYSON_LED_PAD_E2 BIT(10) +#define B_AX_SYSON_GPEE_PAD_E2 BIT(9) +#define B_AX_SYSON_PCI_PAD_E2 BIT(8) +#define B_AX_SYSON_WLPC_IDX_SH 6 +#define B_AX_SYSON_WLPC_IDX_MSK 0x3 +#define B_AX_SYSON_SPS0WWV_WT_SH 4 +#define B_AX_SYSON_SPS0WWV_WT_MSK 0x3 +#define B_AX_SYSON_SPS0LDO_WT_SH 2 +#define B_AX_SYSON_SPS0LDO_WT_MSK 0x3 +#define B_AX_SYSON_RCLK_SCALE_SH 0 +#define B_AX_SYSON_RCLK_SCALE_MSK 0x3 + +#define R_AX_CAL_TIMER 0x0054 +#define B_AX_UART_TX_SEL_SH 30 +#define B_AX_UART_TX_SEL_MSK 0x3 +#define B_AX_UART_RX_SEL BIT(29) +#define B_AX_CAL_SCAL_SH 0 +#define B_AX_CAL_SCAL_MSK 0xffff + +#define R_AX_DBG_CTRL 0x0058 +#define B_AX_DBG_SEL1_4BIT_SH 30 +#define B_AX_DBG_SEL1_4BIT_MSK 0x3 +#define B_AX_DBG_SEL1_16BIT BIT(27) +#define B_AX_DBG_SEL1_SH 16 +#define B_AX_DBG_SEL1_MSK 0xff +#define B_AX_DBG_SEL0_4BIT_SH 14 +#define B_AX_DBG_SEL0_4BIT_MSK 0x3 +#define B_AX_DBG_SEL0_16BIT BIT(11) +#define B_AX_DBG_SEL0_SH 0 +#define B_AX_DBG_SEL0_MSK 0xff + +#define R_AX_PWR_CUT_CTRL 0x005C +#define B_AX_WLBBPC1_WT_SH 24 +#define B_AX_WLBBPC1_WT_MSK 0xff +#define B_AX_WLBBPC0_WT_SH 16 +#define B_AX_WLBBPC0_WT_MSK 0xff +#define B_AX_WLMACPC1_WT_SH 12 +#define B_AX_WLMACPC1_WT_MSK 0xf +#define B_AX_WLMACPC0_WT_SH 8 +#define B_AX_WLMACPC0_WT_MSK 0xf +#define B_AX_WLPONPC1_WT_SH 4 +#define B_AX_WLPONPC1_WT_MSK 0xf +#define B_AX_WLPONPC0_WT_SH 0 +#define B_AX_WLPONPC0_WT_MSK 0xf + +#define R_AX_GPIO_EXT_CTRL 0x0060 +#define B_AX_GPIO_MOD_15_TO_8_SH 24 +#define B_AX_GPIO_MOD_15_TO_8_MSK 0xff +#define B_AX_GPIO_IO_SEL_15_TO_8_SH 16 +#define B_AX_GPIO_IO_SEL_15_TO_8_MSK 0xff +#define B_AX_GPIO_OUT_15_TO_8_SH 8 +#define B_AX_GPIO_OUT_15_TO_8_MSK 0xff +#define B_AX_GPIO_IN_15_TO_8_SH 0 +#define B_AX_GPIO_IN_15_TO_8_MSK 0xff + +#define R_AX_PAD_CTRL1 0x0064 +#define B_AX_BT_BQB_GPIO_SEL BIT(27) +#define B_AX_BTGP_GPG3_FEN BIT(26) +#define B_AX_BTGP_GPG2_FEN BIT(25) +#define B_AX_BTGP_JTAG_EN BIT(24) +#define B_AX_XTAL_CLK_EXTARNAL_EN BIT(23) +#define B_AX_BTGP_UART0_EN BIT(22) +#define B_AX_BTGP_UART1_EN BIT(21) +#define B_AX_BTGP_SPI_EN BIT(20) +#define B_AX_BTGP_GPIO_E2 BIT(19) +#define B_AX_BTGP_GPIO_EN BIT(18) +#define B_AX_BTGP_GPIO_SL_SH 16 +#define B_AX_BTGP_GPIO_SL_MSK 0x3 +#define B_AX_WL_JTAG_EN BIT(15) +#define B_AX_PAD_SDIO_SR BIT(14) +#define B_AX_GPIO14_OUTPUT_PL BIT(13) +#define B_AX_HOST_WAKE_PAD_PULL_EN BIT(12) +#define B_AX_HOST_WAKE_PAD_SL BIT(11) + +#define R_AX_WL_BT_PWR_CTRL 0x0068 +#define B_AX_ISO_BD2PP BIT(31) +#define B_AX_LDOV12B_EN BIT(30) +#define B_AX_CKEN_BT BIT(29) +#define B_AX_FEN_BT BIT(28) +#define B_AX_BTCPU_BOOTSEL BIT(27) +#define B_AX_SPI_SPEEDUP BIT(26) +#define B_AX_BT_LDO_MODE BIT(25) +#define B_AX_DEVWAKE_PAD_TYPE_SEL BIT(24) +#define B_AX_CLKREQ_PAD_TYPE_SEL BIT(23) +#define B_AX_ISO_BTPON2PP BIT(22) +#define B_AX_BT_HWROF_EN BIT(19) +#define B_AX_BT_FUNC_EN BIT(18) +#define B_AX_BT_HWPDN_SL BIT(17) +#define B_AX_BT_DISN_EN BIT(16) +#define B_AX_BT_PDN_PULL_EN BIT(15) +#define B_AX_WL_PDN_PULL_EN BIT(14) +#define B_AX_EXTERNAL_REQUEST_PL BIT(13) +#define B_AX_GPIO0_2_3_PULL_LOW_EN BIT(12) +#define B_AX_ISO_BA2PP BIT(11) +#define B_AX_BT_AFE_LDO_EN BIT(10) +#define B_AX_BT_AFE_PLL_EN BIT(9) +#define B_AX_BT_DIG_CLK_EN BIT(8) +#define B_AX_WLAN_32K_SEL BIT(6) +#define B_AX_WL_DRV_EXIST_IDX BIT(5) +#define B_AX_DOP_EHPAD BIT(4) +#define B_AX_WL_HWROF_EN BIT(3) +#define B_AX_WL_FUNC_EN BIT(2) +#define B_AX_WL_HWPDN_SL BIT(1) +#define B_AX_WL_HWPDN_EN BIT(0) + +#define R_AX_SDM_DEBUG 0x006C +#define B_AX_GPIO_IE_V18 BIT(10) +#define B_AX_PCIE_IE_V18 BIT(9) +#define B_AX_UART_IE_V18 BIT(8) + +#define R_AX_SYS_SDIO_CTRL 0x0070 +#define B_AX_DBG_GNT_WL_BT BIT(27) +#define B_AX_LTE_MUX_CTRL_PATH BIT(26) +#define B_AX_LTE_COEX_UART BIT(25) +#define B_AX_3W_LTE_WL_GPIO BIT(24) +#define B_AX_SDIO_INT_POLARITY BIT(19) +#define B_AX_SDIO_INT BIT(18) +#define B_AX_SDIO_OFF_EN BIT(17) +#define B_AX_SDIO_ON_EN BIT(16) +#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) +#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) +#define B_AX_PCIE_FORCE_PWR_NGAT BIT(13) +#define B_AX_PCIE_CALIB_EN_V1 BIT(12) +#define B_AX_PCIE_AUXCLK_GATE BIT(11) +#define B_AX_PCIE_WAIT_TIMEOUT_EVENT BIT(10) +#define B_AX_PCIE_WAIT_TIME BIT(9) +#define B_AX_USBA_FORCE_PWR_NGAT BIT(7) +#define B_AX_USBD_FORCE_PWR_NGAT BIT(6) +#define B_AX_BT_CTRL_USB_PWR BIT(5) +#define B_AX_USB_D_STATE_HOLD BIT(4) +#define B_AX_R_AX_FORCE_DP BIT(3) +#define B_AX_R_AX_DP_MODE BIT(2) +#define B_AX_RES_USB_MASS_STORAGE_DESC BIT(1) +#define B_AX_USB_WAIT_TIME BIT(0) + +#define R_AX_HCI_OPT_CTRL 0x0074 +#define B_AX_PCIE_CPHY_CCK_XTAL_SEL BIT(20) +#define B_AX_SDIO_DATA_PAD_SMT BIT(19) +#define B_AX_SDIO_PAD_E5 BIT(18) +#define B_AX_NOPWR_CTRL_SEL BIT(13) +#define B_AX_USB_HOST_PWR_OFF_EN BIT(12) +#define B_AX_SYM_LPS_BLOCK_EN BIT(11) +#define B_AX_USB_LPM_ACT_EN BIT(10) +#define B_AX_USB_LPM_NY BIT(9) +#define B_AX_USB_SUS_DIS BIT(8) +#define B_AX_SDIO_PAD_E_SH 5 +#define B_AX_SDIO_PAD_E_MSK 0x7 +#define B_AX_USB_LPPLL_EN BIT(4) +#define B_AX_USB1_1_USB2_0_DECISION BIT(3) +#define B_AX_ROP_SW15 BIT(2) +#define B_AX_PCI_CKRDY_OPT BIT(1) +#define B_AX_PCI_VAUX_EN BIT(0) + +#define R_AX_HCI_BG_CTRL 0x0078 +#define B_AX_IBX_EN_VALUE BIT(15) +#define B_AX_IB_EN_VALUE BIT(14) +#define B_AX_FORCED_IB_EN BIT(4) +#define B_AX_EN_REGBG BIT(3) +#define B_AX_R_AX_BG_LPF BIT(2) +#define B_AX_R_AX_BG_SH 0 +#define B_AX_R_AX_BG_MSK 0x3 + +#define R_AX_HCI_LDO_CTRL 0x007A +#define B_AX_EN_LW_PWR BIT(6) +#define B_AX_EN_REGU BIT(5) +#define B_AX_EN_PC BIT(4) +#define B_AX_R_AX_VADJ_SH 0 +#define B_AX_R_AX_VADJ_MSK 0xf + +#define R_AX_LDO_SWR_CTRL 0x007C +#define B_AX_DIG_ZCD_HW_AUTO_EN BIT(27) +#define B_AX_DIG_ZCD_REGSEL BIT(26) +#define B_AX_DIG_AUTO_ZCD_IN_CODE_SH 21 +#define B_AX_DIG_AUTO_ZCD_IN_CODE_MSK 0x1f +#define B_AX_DIG_ZCD_CODE_IN_L_SH 16 +#define B_AX_DIG_ZCD_CODE_IN_L_MSK 0x1f +#define B_AX_ANA_ZCD_HW_AUTO_EN BIT(11) +#define B_AX_ANA_ZCD_REGSEL BIT(10) +#define B_AX_ANA_AUTO_ZCD_IN_CODE_SH 5 +#define B_AX_ANA_AUTO_ZCD_IN_CODE_MSK 0x1f +#define B_AX_ANA_ZCD_CODE_IN_L_SH 0 +#define B_AX_ANA_ZCD_CODE_IN_L_MSK 0x1f + +#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 +#define B_AX_R_SYM_FEN_WLMACOFF BIT(31) +#define B_AX_CMAC1_FEN BIT(30) +#define B_AX_R_SYM_ISO_DMEM32PP BIT(28) +#define B_AX_R_SYM_ISO_DMEM22PP BIT(27) +#define B_AX_R_SYM_ISO_DMEM12PP BIT(26) +#define B_AX_R_SYM_ISO_IMEM42PP BIT(22) +#define B_AX_R_SYM_ISO_IMEM32PP BIT(21) +#define B_AX_R_SYM_ISO_IMEM22PP BIT(20) +#define B_AX_R_SYM_ISO_IMEM12PP BIT(19) +#define B_AX_R_SYM_ISO_IMEM02PP BIT(18) +#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) +#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) +#define B_AX_R_SYM_ISO_AON_OFF2PP BIT(15) +#define B_AX_R_SYM_PWC_PD12V BIT(12) +#define B_AX_R_SYM_PWC_UD12V BIT(11) +#define B_AX_R_SYM_LDOBTSDIO_EN BIT(9) +#define B_AX_R_SYM_LDOSPDIO_EN BIT(8) +#define B_AX_R_SYM_ISO_BB2PP BIT(7) +#define B_AX_R_SYM_ISO_DENG2PP BIT(6) +#define B_AX_R_SYM_ISO_CMAC12PP BIT(5) +#define B_AX_R_SYM_ISO_BTSDIO2PP BIT(1) +#define B_AX_R_SYM_ISO_SPDIO2PP BIT(0) + +#define R_AX_PLATFORM_ENABLE 0x0088 +#define B_AX_SYM_WLPLT_MEM_MUX_EN BIT(10) +#define B_AX_WCPU_WARM_EN BIT(9) +#define B_AX_SPIC_EN BIT(8) +#define B_AX_UART_EN BIT(7) +#define B_AX_IDDMA_EN BIT(6) +#define B_AX_IPSEC_EN BIT(5) +#define B_AX_HIOE_EN BIT(4) +#define B_AX_AXIDMA_EN BIT(3) +#define B_AX_APB_WRAP_EN BIT(2) +#define B_AX_WCPU_EN BIT(1) +#define B_AX_PLATFORM_EN BIT(0) + +#define R_AX_WLLPS_CTRL 0x0090 +#define B_AX_LPSOP_BBOFF BIT(29) +#define B_AX_LPSOP_MACOFF BIT(28) +#define B_AX_LPSOP_MEM_DS BIT(26) +#define B_AX_LPSOP_XTALM_LPS BIT(23) +#define B_AX_LPSOP_XTAL BIT(22) +#define B_AX_LPSOP_ACLK_DIV_2 BIT(21) +#define B_AX_LPSOP_ACLK_SEL BIT(20) +#define B_AX_LPSOP_ASWRM BIT(17) +#define B_AX_LPSOP_ASWR BIT(16) +#define B_AX_LPSOP_DSWR_ADJ_SH 12 +#define B_AX_LPSOP_DSWR_ADJ_MSK 0xf +#define B_AX_LPSOP_DSWRSD BIT(10) +#define B_AX_LPSOP_DSWRM BIT(9) +#define B_AX_LPSOP_DSWR BIT(8) +#define B_AX_LPSOP_OLD_ADJ_SH 4 +#define B_AX_LPSOP_OLD_ADJ_MSK 0xf +#define B_AX_FORCE_LEAVE_LPS BIT(3) +#define B_AX_LPSOP_OLDSD BIT(2) +#define B_AX_LPSOP_OLDM BIT(1) +#define B_AX_WL_LPS_EN BIT(0) + +#define R_AX_WLRESUME_CTRL 0x0094 +#define B_AX_LPSROP_CMAC1 BIT(20) +#define B_AX_LPSROP_XTALM BIT(19) +#define B_AX_LPSROP_AFEM BIT(18) +#define B_AX_LPSROP_HIOE BIT(17) +#define B_AX_LPSROP_CPU BIT(16) +#define B_AX_LPSROP_DSWRSD_SEL_SH 4 +#define B_AX_LPSROP_DSWRSD_SEL_MSK 0x3 + +#define R_AX_GPIO_DEBOUNCE_CTRL 0x0098 +#define B_AX_WLGP_DBC1EN BIT(15) +#define B_AX_WLGP_DBC1_SH 8 +#define B_AX_WLGP_DBC1_MSK 0xf +#define B_AX_WLGP_DBC0EN BIT(7) +#define B_AX_WLGP_DBC0_SH 0 +#define B_AX_WLGP_DBC0_MSK 0xf + +#define R_AX_SYSON_FSM_MON 0x00A0 +#define B_AX_FSM_MON_SEL_SH 24 +#define B_AX_FSM_MON_SEL_MSK 0x7 +#define B_AX_DOP_ELDO BIT(23) +#define B_AX_FSM_MON_UPD BIT(15) +#define B_AX_FSM_PAR_SH 0 +#define B_AX_FSM_PAR_MSK 0x7fff + +#define R_AX_PMC_DBG_CTRL1 0x00A8 +#define B_AX_PMC_WR_OVF BIT(8) +#define B_AX_WLPMC_ERRINT_SH 0 +#define B_AX_WLPMC_ERRINT_MSK 0xff + +#define R_AX_SCOREBOARD 0x00AC +#define B_AX_TOGGLE BIT(31) +#define B_AX_DATA_LINE_SH 0 +#define B_AX_DATA_LINE_MSK 0x7fffffffL + +#define R_AX_DBG_PORT_SEL 0x00C0 +#define B_AX_DEBUG_ST_SH 0 +#define B_AX_DEBUG_ST_MSK 0xffffffffL + +#define R_AX_PAD_CTRL2 0x00C4 +#define B_AX_FORCE_CLK_U2 BIT(25) +#define B_AX_FORCE_U2_CK BIT(24) +#define B_AX_FORCE_U3_CK BIT(23) +#define B_AX_USB2_FORCE BIT(22) +#define B_AX_USB3_FORCE BIT(21) +#define B_AX_USB3_USB2_TRANSITION BIT(20) +#define B_AX_USB23_SW_MODE_V1_SH 18 +#define B_AX_USB23_SW_MODE_V1_MSK 0x3 +#define B_AX_NO_PDN_CHIPOFF_V1 BIT(17) +#define B_AX_RSM_EN_V1 BIT(16) +#define B_AX_MATCH_CNT_SH 8 +#define B_AX_MATCH_CNT_MSK 0xff +#define B_AX_LD_B12V_EN BIT(7) +#define B_AX_EECS_IOSEL_V1 BIT(6) +#define B_AX_EECS_DATA_O_V1 BIT(5) +#define B_AX_EECS_DATA_I_V1 BIT(4) +#define B_AX_EESK_IOSEL_V1 BIT(2) +#define B_AX_EESK_DATA_O_V1 BIT(1) +#define B_AX_EESK_DATA_I_V1 BIT(0) + +#define R_AX_PMC_DBG_CTRL2 0x00CC +#define B_AX_EFUSE_BURN_GNT_SH 24 +#define B_AX_EFUSE_BURN_GNT_MSK 0xff +#define B_AX_DIS_IOWRAP_TIMEOUT BIT(16) +#define B_AX_STOP_WL_PMC BIT(9) +#define B_AX_STOP_SYM_PMC BIT(8) +#define B_AX_BT_ACCESS_WL_PAGE0 BIT(6) +#define B_AX_R_AX_RST_WLPMC BIT(5) +#define B_AX_R_AX_RST_PD12N BIT(4) +#define B_AX_SYSON_DIS_WLR_AX_WRMSK BIT(3) +#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2) +#define B_AX_SYSON_R_AX_ARB_SH 0 +#define B_AX_SYSON_R_AX_ARB_MSK 0x3 + +#define R_AX_MEM_PWR_CTRL 0x00D0 +#define B_AX_MEM_BB_SD BIT(17) +#define B_AX_MEM_BB_DS BIT(16) +#define B_AX_MEM_BT_DS BIT(10) +#define B_AX_MEM_SDIO_LS BIT(9) +#define B_AX_MEM_SDIO_DS BIT(8) +#define B_AX_MEM_USB_LS BIT(7) +#define B_AX_MEM_USB_DS BIT(6) +#define B_AX_MEM_PCI_LS BIT(5) +#define B_AX_MEM_PCI_DS BIT(4) +#define B_AX_MEM_WLMAC_LS BIT(3) +#define B_AX_MEM_WLMAC_DS BIT(2) +#define B_AX_MEM_WLMCU_LS BIT(1) +#define B_AX_MEM_WLMCU_DS BIT(0) + +#define R_AX_INDIR_ADR_SDIO 0x00D4 +#define B_AX_INDIR_READY_SDIO BIT(17) +#define B_AX_INDIR_R_SDIO BIT(16) +#define B_AX_INDIR_ADR_SDIO_SH 0 +#define B_AX_INDIR_ADR_SDIO_MSK 0xffff + +#define R_AX_INDIR_DATA_SDIO 0x00D8 +#define B_AX_INDIR_DATA_SDIO_SH 0 +#define B_AX_INDIR_DATA_SDIO_MSK 0xffffffffL + +#define R_AX_USB_SIE_INTF 0x00E0 +#define B_AX_USB_REG_SEL BIT(31) +#define B_AX_USB_WRITE_EN BIT(30) +#define B_AX_USB_REG_EN BIT(29) +#define B_AX_USB_SIE_SEL BIT(28) +#define B_AX_USB_REG_STATUS BIT(27) +#define B_AX_USB_PHY_BYTE_SEL BIT(26) +#define B_AX_USB_SIE_INTF_ADDR_SH 16 +#define B_AX_USB_SIE_INTF_ADDR_MSK 0x3ff +#define B_AX_USB_SIE_INTF_RD_SH 8 +#define B_AX_USB_SIE_INTF_RD_MSK 0xff +#define B_AX_USB_SIE_INTF_WD_SH 0 +#define B_AX_USB_SIE_INTF_WD_MSK 0xff + +#define R_AX_PCIE_MIO_INTF 0x00E4 +#define B_AX_PCIE_MIO_ADDR_PAGE_SH 16 +#define B_AX_PCIE_MIO_ADDR_PAGE_MSK 0x3 +#define B_AX_PCIE_MIO_BYIOREG BIT(13) +#define B_AX_PCIE_MIO_RE BIT(12) +#define B_AX_PCIE_MIO_WE_SH 8 +#define B_AX_PCIE_MIO_WE_MSK 0xf +#define B_AX_PCIE_MIO_ADDR_SH 0 +#define B_AX_PCIE_MIO_ADDR_MSK 0xff + +#define R_AX_PCIE_MIO_INTD 0x00E8 +#define B_AX_PCIE_MIO_DATA_SH 0 +#define B_AX_PCIE_MIO_DATA_MSK 0xffffffffL + +#define R_AX_WLRF1 0x00EC +#define B_AX_S1_RFC_WO_0 BIT(31) +#define B_AX_S1_RFC_WT_0 BIT(30) +#define B_AX_S1_RFC_RSTB BIT(25) + +#define R_AX_SYS_CFG1 0x00F0 +#define B_AX_TRP_ICFG_SH 28 +#define B_AX_TRP_ICFG_MSK 0xf +#define B_AX_RF_TYPE_ID BIT(27) +#define B_AX_BD_HCI_SEL BIT(26) +#define B_AX_BD_PKG_SEL BIT(25) +#define B_AX_RTL_ID BIT(23) +#define B_AX_PAD_HWPD_IDN BIT(22) +#define B_AX_TESTMODE BIT(20) +#define B_AX_VENDOR_ID_SH 16 +#define B_AX_VENDOR_ID_MSK 0xf +#define B_AX_CHIP_VER_SH 12 +#define B_AX_CHIP_VER_MSK 0xf +#define B_AX_BD_MAC3 BIT(11) +#define B_AX_BD_MAC1 BIT(10) +#define B_AX_BD_MAC2 BIT(9) +#define B_AX_SIC_IDLE BIT(8) +#define B_AX_ANA_SPS_OCP_SHUTDN BIT(7) +#define B_AX_DIG_SPS_OCP_SHUTDN BIT(6) +#define B_AX_V15_VLD BIT(5) +#define B_AX_PCIRSTB BIT(4) +#define B_AX_PCLK_VLD BIT(3) +#define B_AX_UCLK_VLD BIT(2) +#define B_AX_ACLK_VLD BIT(1) +#define B_AX_XCLK_VLD BIT(0) + +#define R_AX_SYS_STATUS1 0x00F4 +#define B_AX_RF_RL_ID_SH 28 +#define B_AX_RF_RL_ID_MSK 0xf +#define B_AX_BT_LPS_EN BIT(27) +#define B_AX_WLAN_LPS_EN BIT(26) +#define B_AX_HPHY_ICFG BIT(19) +#define B_AX_SEL_0XC0_SH 16 +#define B_AX_SEL_0XC0_MSK 0x3 +#define B_AX_HCI_SEL_V4_SH 13 +#define B_AX_HCI_SEL_V4_MSK 0x7 +#define B_AX_USB_OPERATION_MODE BIT(12) +#define B_AX_BT_PDN BIT(11) +#define B_AX_AUTO_WLPON BIT(10) +#define B_AX_WL_MODE_SH 8 +#define B_AX_WL_MODE_MSK 0x3 +#define B_AX_PKG_SEL_HCI BIT(6) +#define B_AX_PAD_HCI_SEL_V2_SH 3 +#define B_AX_PAD_HCI_SEL_V2_MSK 0x7 +#define B_AX_EFS_HCI_SEL_V1_SH 0 +#define B_AX_EFS_HCI_SEL_V1_MSK 0x7 + +#define R_AX_SYS_STATUS2 0x00F8 +#define B_AX_SIC_ON_TIMEOUT BIT(22) +#define B_AX_CPU_ON_TIMEOUT BIT(21) +#define B_AX_HCI_ON_TIMEOUT BIT(20) +#define B_AX_SIO_ALDN BIT(19) +#define B_AX_USB_ALDN BIT(18) +#define B_AX_PCI_ALDN BIT(17) +#define B_AX_SYS_ALDN BIT(16) +#define B_AX_EPVID1_SH 8 +#define B_AX_EPVID1_MSK 0xff +#define B_AX_EPVID0_SH 0 +#define B_AX_EPVID0_MSK 0xff + +#define R_AX_SYS_CHIPINFO 0x00FC +#define B_AX_USB2_SEL BIT(31) +#define B_AX_U3PHY_RST_V1 BIT(30) +#define B_AX_U3_TERM_DETECT BIT(29) +#define B_AX_HW_ID_SH 0 +#define B_AX_HW_ID_MSK 0xff + +#define R_AX_SYS_CFG3 0x0100 + +#define R_AX_ANAPARSW_MAC_0 0x0110 +#define B_AX_OCP_L BIT(31) +#define B_AX_POWOCP_L BIT(30) +#define B_AX_CF_L_V2_SH 28 +#define B_AX_CF_L_V2_MSK 0x3 +#define B_AX_CFC_L_V2_SH 26 +#define B_AX_CFC_L_V2_MSK 0x3 +#define B_AX_R3_L_V2_SH 24 +#define B_AX_R3_L_V2_MSK 0x3 +#define B_AX_R2_L_SH 22 +#define B_AX_R2_L_MSK 0x3 +#define B_AX_R1_L_SH 20 +#define B_AX_R1_L_MSK 0x3 +#define B_AX_C3_L_SH 18 +#define B_AX_C3_L_MSK 0x3 +#define B_AX_C2_L_SH 16 +#define B_AX_C2_L_MSK 0x3 +#define B_AX_C1_L_V2_SH 14 +#define B_AX_C1_L_V2_MSK 0x3 +#define B_AX_R_AX_OCPS_L_V2 BIT(13) +#define B_AX_R_AX_PWM_L BIT(12) +#define B_AX_V15ADJ_L_SH 9 +#define B_AX_V15ADJ_L_MSK 0x7 +#define B_AX_IN_L_SH 6 +#define B_AX_IN_L_MSK 0x7 +#define B_AX_STD_L_SH 4 +#define B_AX_STD_L_MSK 0x3 +#define B_AX_VOL_L_SH 0 +#define B_AX_VOL_L_MSK 0xf + +#define R_AX_ANAPARSW_MAC_1 0x0114 +#define B_AX_OCP_L_PFM_SH 29 +#define B_AX_OCP_L_PFM_MSK 0x7 +#define B_AX_CFC_L_PFM_SH 27 +#define B_AX_CFC_L_PFM_MSK 0x3 +#define B_AX_R_AX_FREQ_L_V1_SH 20 +#define B_AX_R_AX_FREQ_L_V1_MSK 0x7 +#define B_AX_EN_DUTY BIT(19) +#define B_AX_R_AX_MODE_V2_SH 17 +#define B_AX_R_AX_MODE_V2_MSK 0x3 +#define B_AX_EN_SP BIT(16) +#define B_AX_R_AX_AUTO_L_V2 BIT(15) +#define B_AX_R_AX_LDOF_L_V2 BIT(14) +#define B_AX_R_AX_TYPE_L_V2 BIT(13) +#define B_AX_VO15_V1P05_H BIT(12) +#define B_AX_ARENB_L_V2 BIT(11) +#define B_AX_TBOX_L1_V2_SH 9 +#define B_AX_TBOX_L1_V2_MSK 0x3 +#define B_AX_R_AX_DELAY_L_SH 7 +#define B_AX_R_AX_DELAY_L_MSK 0x3 +#define B_AX_R_AX_CLAMP_D_L BIT(6) +#define B_AX_R_AX_BYPASS_L_V2 BIT(5) +#define B_AX_R_AX_AUTOZCD_L BIT(4) +#define B_AX_POW_ZCD_L_V2 BIT(3) +#define B_AX_R_AX_HALF_L BIT(2) +#define B_AX_OCP_L_V2_SH 0 +#define B_AX_OCP_L_V2_MSK 0x3 + +#define R_AX_ANAPAR_MAC_0 0x0118 +#define B_AX_R_AX_LPF_R3_SH 29 +#define B_AX_R_AX_LPF_R3_MSK 0x7 +#define B_AX_R_AX_LPF_R2_SH 24 +#define B_AX_R_AX_LPF_R2_MSK 0x1f +#define B_AX_R_AX_LPF_C3_SH 21 +#define B_AX_R_AX_LPF_C3_MSK 0x7 +#define B_AX_R_AX_LPF_C2_SH 18 +#define B_AX_R_AX_LPF_C2_MSK 0x7 +#define B_AX_R_AX_LPF_C1_SH 15 +#define B_AX_R_AX_LPF_C1_MSK 0x7 +#define B_AX_R_AX_LDO_SEL_V1_SH 13 +#define B_AX_R_AX_LDO_SEL_V1_MSK 0x3 +#define B_AX_R_AX_CP_ICPX2 BIT(12) +#define B_AX_R_AX_CP_ICP_SEL_FAST_SH 9 +#define B_AX_R_AX_CP_ICP_SEL_FAST_MSK 0x7 +#define B_AX_R_AX_CP_ICP_SEL_SH 6 +#define B_AX_R_AX_CP_ICP_SEL_MSK 0x7 +#define B_AX_R_AX_IB_PI_SH 4 +#define B_AX_R_AX_IB_PI_MSK 0x3 +#define B_AX_LDO2PWRCUT BIT(3) +#define B_AX_VPULSE_LDO BIT(2) +#define B_AX_LDO_VSEL_SH 0 +#define B_AX_LDO_VSEL_MSK 0x3 + +#define R_AX_ANAPAR_MAC_1 0x011C +#define B_AX_R_AX_CK_MON_SEL_SH 29 +#define B_AX_R_AX_CK_MON_SEL_MSK 0x7 +#define B_AX_R_AX_CK_MON_EN BIT(28) +#define B_AX_R_AX_XTAL_FREQ_SEL BIT(27) +#define B_AX_R_AX_XTAL_EDGE_SEL BIT(26) +#define B_AX_R_AX_VCO_KVCO BIT(25) +#define B_AX_R_AX_SDM_EDGE_SEL BIT(24) +#define B_AX_R_AX_SDM_CK_SEL BIT(23) +#define B_AX_R_AX_SDM_CK_GATED BIT(22) +#define B_AX_R_AX_PFD_RESET_GATED BIT(21) +#define B_AX_R_AX_LPF_R3_FAST_SH 16 +#define B_AX_R_AX_LPF_R3_FAST_MSK 0x1f +#define B_AX_R_AX_LPF_R2_FAST_SH 11 +#define B_AX_R_AX_LPF_R2_FAST_MSK 0x1f +#define B_AX_R_AX_LPF_C3_FAST_SH 8 +#define B_AX_R_AX_LPF_C3_FAST_MSK 0x7 +#define B_AX_R_AX_LPF_C2_FAST_SH 5 +#define B_AX_R_AX_LPF_C2_FAST_MSK 0x7 +#define B_AX_R_AX_LPF_C1_FAST_SH 2 +#define B_AX_R_AX_LPF_C1_FAST_MSK 0x7 +#define B_AX_R_AX_LPF_R3_V1_SH 0 +#define B_AX_R_AX_LPF_R3_V1_MSK 0x3 + +#define R_AX_ANAPAR_MAC_2 0x0120 +#define B_AX_AGPIO_DRV_V1_SH 30 +#define B_AX_AGPIO_DRV_V1_MSK 0x3 +#define B_AX_AGPIO_GPO_V1 BIT(29) +#define B_AX_AGPIO_GPE_V1 BIT(28) +#define B_AX_SEL_CLK BIT(27) +#define B_AX_LS_XTAL_SEL_SH 23 +#define B_AX_LS_XTAL_SEL_MSK 0xf +#define B_AX_LS_SDM_ORDER_V1 BIT(22) +#define B_AX_LS_DELAY_PH BIT(21) +#define B_AX_DIVIDER_SEL BIT(20) +#define B_AX_PCODE_SH 15 +#define B_AX_PCODE_MSK 0x1f +#define B_AX_NCODE_SH 7 +#define B_AX_NCODE_MSK 0xff +#define B_AX_R_AX_BEACON BIT(6) +#define B_AX_R_AX_MBIASE BIT(5) +#define B_AX_R_AX_FAST_SEL_SH 3 +#define B_AX_R_AX_FAST_SEL_MSK 0x3 +#define B_AX_R_AX_CK960M_EN BIT(2) +#define B_AX_R_AX_CK320M_EN BIT(1) +#define B_AX_R_AX_CK_5M_EN BIT(0) + +#define R_AX_RFE_PINMUX_CTRL 0x0140 +#define B_AX__BANDSELN_5G_SEL BIT(31) +#define B_AX__BANDSELN_5G_EN BIT(30) +#define B_AX_BANDSELN_5_6G_SEL BIT(29) +#define B_AX_BANDSELN_5_6G_EN BIT(28) +#define B_AX_PAON_LNAON_6G_S1_SEL BIT(27) +#define B_AX_PAON_LNAON_6G_S1_EN BIT(26) +#define B_AX_PAON_LNAON_6G_S0_SEL BIT(25) +#define B_AX_PAON_LNAON_6G_S0_EN BIT(24) +#define B_AX_PAON_LNAON_5G_S1_SEL BIT(23) +#define B_AX_PAON_LNAON_5G_S1_EN BIT(22) +#define B_AX_PAON_LNAON_5G_S0_SEL BIT(21) +#define B_AX_PAON_LNAON_5G_S0_EN BIT(20) +#define B_AX_PAON_LNAON_2G_S1_SEL BIT(19) +#define B_AX_PAON_LNAON_2G_S1_EN BIT(18) +#define B_AX_PAON_LNAON_2G_S0_SEL BIT(17) +#define B_AX_PAON_LNAON_2G_S0_EN BIT(16) +#define B_AX__BANDSELN_5G_G7G6_SEL BIT(15) +#define B_AX__BANDSELN_5G_G7G6_EN BIT(14) + +#define R_AX_RFE_PINMUX_SEL_FUNC 0x0144 +#define B_AX_RFE_WLBT_FUNC_8_SEL_EN BIT(8) +#define B_AX_RFE_WLBT_FUNC_7_SEL_EN BIT(7) +#define B_AX_RFE_WLBT_FUNC_6_SEL_EN BIT(6) +#define B_AX_RFE_WLBT_FUNC_5_SEL_EN BIT(5) +#define B_AX_RFE_WLBT_FUNC_4_SEL_EN BIT(4) +#define B_AX_RFE_WLBT_FUNC_3_SEL_EN BIT(3) +#define B_AX_RFE_WLBT_FUNC_2_SEL_EN BIT(2) +#define B_AX_RFE_WLBT_FUNC_1_SEL_EN BIT(1) +#define B_AX_RFE_WLBT_FUNC_0_SEL_EN BIT(0) + +#define R_AX_GPIO_EESK_EECS_HIGH_PRI_PINMUX 0x0148 +#define B_AX_STD_EECS_PINMUX_HIGH_PRI_EN BIT(17) +#define B_AX_STD_EESK_PINMUX_HIGH_PRI_EN BIT(16) +#define B_AX_STD_GPIO15_PINMUX_HIGH_PRI_EN BIT(15) +#define B_AX_STD_GPIO14_PINMUX_HIGH_PRI_EN BIT(14) +#define B_AX_STD_GPIO13_PINMUX_HIGH_PRI_EN BIT(13) +#define B_AX_STD_GPIO12_PINMUX_HIGH_PRI_EN BIT(12) +#define B_AX_STD_GPIO11_PINMUX_HIGH_PRI_EN BIT(11) +#define B_AX_STD_GPIO10_PINMUX_HIGH_PRI_EN BIT(10) +#define B_AX_STD_GPIO9_PINMUX_HIGH_PRI_EN BIT(9) +#define B_AX_STD_GPIO8_PINMUX_HIGH_PRI_EN BIT(8) +#define B_AX_STD_GPIO7_PINMUX_HIGH_PRI_EN BIT(7) +#define B_AX_STD_GPIO6_PINMUX_HIGH_PRI_EN BIT(6) +#define B_AX_STD_GPIO5_PINMUX_HIGH_PRI_EN BIT(5) +#define B_AX_STD_GPIO4_PINMUX_HIGH_PRI_EN BIT(4) +#define B_AX_STD_GPIO3_PINMUX_HIGH_PRI_EN BIT(3) +#define B_AX_STD_GPIO2_PINMUX_HIGH_PRI_EN BIT(2) +#define B_AX_STD_GPIO1_PINMUX_HIGH_PRI_EN BIT(1) +#define B_AX_STD_GPIO0_PINMUX_HIGH_PRI_EN BIT(0) + +#define R_AX_RFE_CTRL 0x014C +#define B_AX_SW_LNAON_6G_S1_SEL_DATA BIT(13) +#define B_AX_SW_PAON_6G_S1_SEL_DATA BIT(12) +#define B_AX_BANDSELP_5G_SEL_DATA BIT(11) +#define B_AX_BANDSELP_5 BIT(10) +#define B_AX_SW_LNAON_6G_S0_SEL_DATA BIT(9) +#define B_AX_SW_PAON_6G_S0_SEL_DATA BIT(8) +#define B_AX_SW_LNAON_5G_S1_SEL_DATA BIT(7) +#define B_AX_SW_PAON_5G_S1_SEL_DATA BIT(6) +#define B_AX_SW_LNAON_5G_S0_SEL_DATA BIT(5) +#define B_AX_SW_PAON_5G_S0_SEL_DATA BIT(4) +#define B_AX_SW_LNAON_2G_S1_SEL_DATA BIT(3) +#define B_AX_SW_PAON_2G_S1_SEL_DATA BIT(2) +#define B_AX_SW_LNAON_2G_S0_SEL_DATA BIT(1) +#define B_AX_SW_PAON_2G_S0_SEL_DATA BIT(0) + +#define R_AX_ANAPAR_XTAL_AACK_0 0x0154 + +#define R_AX_ANAPAR_XTAL_AACK_1 0x0158 + +#define R_AX_HALT_H2C_CTRL 0x0160 +#define B_AX_HALT_H2C_TRIGGER BIT(0) + +#define R_AX_HALT_C2H_CTRL 0x0164 +#define B_AX_HALT_C2H_TRIGGER BIT(0) + +#define R_AX_HALT_H2C 0x0168 +#define B_AX_HALT_H2C_SH 0 +#define B_AX_HALT_H2C_MSK 0xffffffffL + +#define R_AX_HALT_C2H 0x016C +#define DBG_SENARIO_SH 28 +#define B_AX_HALT_C2H_SH 0 +#define B_AX_HALT_C2H_MSK 0xffffffffL + +#define R_AX_SYS_CFG5 0x0170 +#define B_AX_LPS_STATUS BIT(3) +#define B_AX_HCI_TXDMA_BUSY BIT(2) +#define B_AX_HCI_TXDMA_ALLOW BIT(1) +#define B_AX_FW_CTRL_HCI_TXDMA_EN BIT(0) + +#define R_AX_ANACK_CAL_CTRL 0x0180 +#define B_AX_CLK_CAL_EN BIT(31) +#define B_AX_CLK_SEL_SH 24 +#define B_AX_CLK_SEL_MSK 0x3 +#define B_AX_CLK_CAL_RPT_SH 0 +#define B_AX_CLK_CAL_RPT_MSK 0xffff + +#define R_AX_FWS0IMR 0x0190 +#define B_AX_FS_HALT_H2C_INT_EN BIT(31) +#define B_AX_FS_FSM_HIOE_TO_EVENT_INT_EN BIT(30) +#define B_AX_FS_HCI_SUS_INT_EN BIT(29) +#define B_AX_FS_HCI_RES_INT_EN BIT(28) +#define B_AX_FS_HCI_RESET_INT_EN BIT(27) +#define B_AX_FS_USB_SCSI_CMD_INT_EN BIT(26) +#define B_AX_FS_ACT2RECOVERY_INT_EN BIT(25) +#define B_AX_FS_GEN1GEN2_SWITCH_INT_EN BIT(24) +#define B_AX_FS_HCI_TXDMA_REQ_INT_EN BIT(23) +#define B_AX_FS_USB_LPMRSM_INT_EN BIT(22) +#define B_AX_FS_USB_LPMINT_INT_EN BIT(21) +#define B_AX_FS_PWMERR_INT_EN BIT(20) +#define B_AX_FS_PDNINT_EN BIT(19) +#define B_AX_FS_SPSA_OCP_INT_EN BIT(18) +#define B_AX_FS_SPSD_OCP_INT_EN BIT(17) +#define B_AX_FS_BT_SB_INT_EN BIT(16) +#define B_AX_FS_GPIOF_INT_EN BIT(15) +#define B_AX_FS_GPIOE_INT_EN BIT(14) +#define B_AX_FS_GPIOD_INT_EN BIT(13) +#define B_AX_FS_GPIOC_INT_EN BIT(12) +#define B_AX_FS_GPIOB_INT_EN BIT(11) +#define B_AX_FS_GPIOA_INT_EN BIT(10) +#define B_AX_FS_GPIO9_INT_EN BIT(9) +#define B_AX_FS_GPIO8_INT_EN BIT(8) +#define B_AX_FS_GPIO7_INT_EN BIT(7) +#define B_AX_FS_GPIO6_INT_EN BIT(6) +#define B_AX_FS_GPIO5_INT_EN BIT(5) +#define B_AX_FS_GPIO4_INT_EN BIT(4) +#define B_AX_FS_GPIO3_INT_EN BIT(3) +#define B_AX_FS_GPIO2_INT_EN BIT(2) +#define B_AX_FS_GPIO1_INT_EN BIT(1) +#define B_AX_FS_GPIO0_INT_EN BIT(0) + +#define R_AX_FWS0ISR 0x0194 +#define B_AX_FS_HALT_H2C_INT BIT(31) +#define B_AX_FS_FSM_HIOE_TO_EVENT_INT BIT(30) +#define B_AX_FS_HCI_SUS_INT BIT(29) +#define B_AX_FS_HCI_RES_INT BIT(28) +#define B_AX_FS_HCI_RESET_INT BIT(27) +#define B_AX_FS_USB_SCSI_CMD_INT BIT(26) +#define B_AX_FS_ACT2RECOVERY_INT BIT(25) +#define B_AX_FS_GEN1GEN2_SWITCH_INT BIT(24) +#define B_AX_FS_HCI_TXDMA_REQ_INT BIT(23) +#define B_AX_FS_USB_LPMRSM_INT BIT(22) +#define B_AX_FS_USB_LPMINT_INT BIT(21) +#define B_AX_FS_PWMERR_INT BIT(20) +#define B_AX_FS_PDNINT BIT(19) +#define B_AX_FS_SPSA_OCP_INT BIT(18) +#define B_AX_FS_SPSD_OCP_INT BIT(17) +#define B_AX_FS_BT_SB_INT BIT(16) +#define B_AX_FS_GPIOF_INT BIT(15) +#define B_AX_FS_GPIOE_INT BIT(14) +#define B_AX_FS_GPIOD_INT BIT(13) +#define B_AX_FS_GPIOC_INT BIT(12) +#define B_AX_FS_GPIOB_INT BIT(11) +#define B_AX_FS_GPIOA_INT BIT(10) +#define B_AX_FS_GPIO9_INT BIT(9) +#define B_AX_FS_GPIO8_INT BIT(8) +#define B_AX_FS_GPIO7_INT BIT(7) +#define B_AX_FS_GPIO6_INT BIT(6) +#define B_AX_FS_GPIO5_INT BIT(5) +#define B_AX_FS_GPIO4_INT BIT(4) +#define B_AX_FS_GPIO3_INT BIT(3) +#define B_AX_FS_GPIO2_INT BIT(2) +#define B_AX_FS_GPIO1_INT BIT(1) +#define B_AX_FS_GPIO0_INT BIT(0) + +#define R_AX_HSIMR 0x0198 + +#define R_AX_HSISR 0x019C + +#define R_AX_HIMR0 0x01A0 +#define B_AX_HALT_C2H_INT_EN BIT(21) +#define B_AX_RON_INT_EN BIT(20) +#define B_AX_PDNINT_EN BIT(19) +#define B_AX_SPSANA_OCP_INT_EN BIT(18) +#define B_AX_SPS_OCP_INT_EN BIT(17) +#define B_AX_BTON_STS_UPDATE_INT_EN BIT(16) +#define B_AX_GPIOF_INT_EN BIT(15) +#define B_AX_GPIOE_INT_EN BIT(14) +#define B_AX_GPIOD_INT_EN BIT(13) +#define B_AX_GPIOC_INT_EN BIT(12) +#define B_AX_GPIOB_INT_EN BIT(11) +#define B_AX_GPIOA_INT_EN BIT(10) +#define B_AX_GPIO9_INT_EN BIT(9) +#define B_AX_GPIO8_INT_EN BIT(8) +#define B_AX_GPIO7_INT_EN BIT(7) +#define B_AX_GPIO6_INT_EN BIT(6) +#define B_AX_GPIO5_INT_EN BIT(5) +#define B_AX_GPIO4_INT_EN BIT(4) +#define B_AX_GPIO3_INT_EN BIT(3) +#define B_AX_GPIO2_INT_EN BIT(2) +#define B_AX_GPIO1_INT_EN BIT(1) +#define B_AX_GPIO0_INT_EN BIT(0) + +#define R_AX_HISR0 0x01A4 +#define B_AX_HALT_C2H_INT BIT(21) +#define B_AX_RON_INT BIT(20) +#define B_AX_PDNINT BIT(19) +#define B_AX_SPSANA_OCP_INT BIT(18) +#define B_AX_SPS_OCP_INT BIT(17) +#define B_AX_BTON_STS_UPDATE_INT BIT(16) +#define B_AX_GPIOF_INT BIT(15) +#define B_AX_GPIOE_INT BIT(14) +#define B_AX_GPIOD_INT BIT(13) +#define B_AX_GPIOC_INT BIT(12) +#define B_AX_GPIOB_INT BIT(11) +#define B_AX_GPIOA_INT BIT(10) +#define B_AX_GPIO9_INT BIT(9) +#define B_AX_GPIO8_INT BIT(8) +#define B_AX_GPIO7_INT BIT(7) +#define B_AX_GPIO6_INT BIT(6) +#define B_AX_GPIO5_INT BIT(5) +#define B_AX_GPIO4_INT BIT(4) +#define B_AX_GPIO3_INT BIT(3) +#define B_AX_GPIO2_INT BIT(2) +#define B_AX_GPIO1_INT BIT(1) +#define B_AX_GPIO0_INT BIT(0) + +#define R_AX_HIMR1 0x01A8 + +#define R_AX_HISR1 0x01AC + +#define R_AX_HIMR2 0x01B0 + +#define R_AX_HISR2 0x01B4 + +#define R_AX_HIMR3 0x01B8 + +#define R_AX_HISR3 0x01BC + +#define R_AX_SW_MDIO 0x01C0 +#define B_AX_DIS_TIMEOUT_IO BIT(24) + +#define R_AX_H2C_PKT_READADDR 0x01D0 +#define B_AX_H2C_PKT_READADDR_SH 0 +#define B_AX_H2C_PKT_READADDR_MSK 0x3ffff + +#define R_AX_H2C_PKT_WRITEADDR 0x01D4 +#define B_AX_H2C_PKT_WRITEADDR_SH 0 +#define B_AX_H2C_PKT_WRITEADDR_MSK 0x3ffff + +#define R_AX_MEM_PWR_CRTL 0x01D8 +#define B_AX_MEM_BB_SD BIT(17) +#define B_AX_MEM_BB_DS BIT(16) +#define B_AX_MEM_BT_DS BIT(10) +#define B_AX_MEM_SDIO_LS BIT(9) +#define B_AX_MEM_SDIO_DS BIT(8) +#define B_AX_MEM_USB_LS BIT(7) +#define B_AX_MEM_USB_DS BIT(6) +#define B_AX_MEM_PCI_LS BIT(5) +#define B_AX_MEM_PCI_DS BIT(4) +#define B_AX_MEM_WLMAC_LS BIT(3) +#define B_AX_MEM_WLMAC_DS BIT(2) +#define B_AX_MEM_WLMCU_LS BIT(1) +#define B_AX_MEM_WLMCU_DS BIT(0) + +#define R_AX_WCPU_FW_CTRL 0x01E0 +#define B_AX_WCPU_ROM_ENUART BIT(31) +#define B_AX_WCPU_ROM_CUT_REQ BIT(30) +#define B_AX_WCPU_ROM_CUT_SH 8 +#define B_AX_WCPU_ROM_CUT_MSK 0xff +#define B_AX_WCPU_FWDL_STS_SH 5 +#define B_AX_WCPU_FWDL_STS_MSK 0x7 +#define B_AX_FWDL_PATH_RDY BIT(2) +#define B_AX_H2C_PATH_RDY BIT(1) +#define B_AX_WCPU_FWDL_EN BIT(0) + +#define R_AX_BOOT_REASON 0x01E6 +#define B_AX_BOOT_REASON_SH 0 +#define B_AX_BOOT_REASON_MSK 0x7 + +#define R_AX_RPWM 0x01E4 +#define B_AX_RPWM_TOGGLE BIT(15) +#define B_AX_RPWM_VAL_SH 0 +#define B_AX_RPWM_VAL_MSK 0x7fff + +#define R_AX_LDM 0x01E8 +#define B_AX_LDM_SH 0 +#define B_AX_LDM_MSK 0xffffffffL + +#define R_AX_UDM0 0x01F0 +#define B_AX_UDM0_SH 0 +#define B_AX_UDM0_MSK 0xffffffffL +#define B_AX_UDM0_DBG_MODE_SH 0 +#define B_AX_UDM0_FS_CODE_SH 8 +#define B_AX_UDM0_FS_CODE_MSK 0xffff +#define B_AX_UDM0_TRAP_LOOP_CTRL BIT(2) +#define B_AX_UDM0_DBG_MODE_CTRL BIT(0) + +#define R_AX_UDM1 0x01F4 +#define B_AX_UDM1_SH 0 +#define B_AX_UDM1_MSK 0xffffffffL + +#define R_AX_UDM2 0x01F8 +#define B_AX_UDM2_SH 0 +#define B_AX_UDM2_MSK 0xffffffffL + +#define R_AX_UDM3 0x01FC +#define B_AX_UDM3_SH 0 +#define B_AX_UDM3_MSK 0xffffffffL + +#define R_AX_SPSLDO_ON_CTRL0 0x0200 +#define B_AX_PFMCMP_IQ BIT(31) +#define B_AX_OFF_END_SEL BIT(29) +#define B_AX_POW_MINOFF_L BIT(28) +#define B_AX_COT_I_L_SH 26 +#define B_AX_COT_I_L_MSK 0x3 +#define B_AX_VREFPFM_L_SH 22 +#define B_AX_VREFPFM_L_MSK 0xf +#define B_AX_FORCE_ZCD_BIAS BIT(21) +#define B_AX_ZCD_SDZ_L_SH 19 +#define B_AX_ZCD_SDZ_L_MSK 0x3 +#define B_AX_REG_ZCDC_H_SH 17 +#define B_AX_REG_ZCDC_H_MSK 0x3 +#define B_AX_POW_ZCD_L BIT(16) +#define B_AX_OCP_L1_SH 13 +#define B_AX_OCP_L1_MSK 0x7 +#define B_AX_POWOCP_L1 BIT(12) +#define B_AX_SAW_FREQ_L_SH 8 +#define B_AX_SAW_FREQ_L_MSK 0xf +#define B_AX_REG_BYPASS_L BIT(7) +#define B_AX_FPWM_L1 BIT(6) +#define B_AX_STD_L1_SH 4 +#define B_AX_STD_L1_MSK 0x3 +#define B_AX_VOL_L1_SH 0 +#define B_AX_VOL_L1_MSK 0xf + +#define R_AX_SPSLDO_ON_CTRL1 0x0204 +#define B_AX_SN_N_L_SH 28 +#define B_AX_SN_N_L_MSK 0xf +#define B_AX_SP_N_L_SH 24 +#define B_AX_SP_N_L_MSK 0xf +#define B_AX_SN_P_L_SH 20 +#define B_AX_SN_P_L_MSK 0xf +#define B_AX_SP_P_L_SH 16 +#define B_AX_SP_P_L_MSK 0xf +#define B_AX_VO_DISCHG_PWM_H BIT(15) +#define B_AX_REG_MODE_PREDRIVER BIT(14) +#define B_AX_REG_ADJSLDO_L_SH 10 +#define B_AX_REG_ADJSLDO_L_MSK 0xf +#define B_AX_REG_LDOR_L BIT(9) +#define B_AX_PWM_FORCE BIT(8) +#define B_AX_PFM_PD_RST BIT(7) +#define B_AX_VC_PFM_RSTB BIT(6) +#define B_AX_PFM_IN_SEL BIT(5) +#define B_AX_VC_RSTB BIT(4) +#define B_AX_FPWMDELAY BIT(3) +#define B_AX_ENFPWMDELAY_H BIT(2) +#define B_AX_REG_MOS_HALF_L BIT(1) +#define B_AX_CURRENT_SENSE_MOS BIT(0) +#define B_AX_SPS_PFM_ZCDC_H_PFM_SH 4 +#define B_AX_SPS_PFM_ZCDC_H_PFM_MSK 0x3 +#define B_AX_SPS_PFM_OCP_L_PFM_SH 0 +#define B_AX_SPS_PFM_OCP_L_PFM_MSK 0x7 + +#define R_AX_LDO_AON_CTRL0 0x0218 +#define B_AX_CK12M_EN BIT(11) +#define B_AX_CK12M_SEL BIT(10) +#define B_AX_EN_SLEEP BIT(8) +#define B_AX_LDOH12_V12ADJ_L_SH 4 +#define B_AX_LDOH12_V12ADJ_L_MSK 0xf +#define B_AX_LDOE25_V12ADJ_L_SH 0 +#define B_AX_LDOE25_V12ADJ_L_MSK 0xf + +#define R_AX_SPSANA_ON_CTRL0 0x0220 +#define B_AX_PFMCMP_IQ BIT(31) +#define B_AX_REG_EXTERNAL_CLK_SEL_L BIT(30) +#define B_AX_OFF_END_SEL BIT(29) +#define B_AX_POW_MINOFF_L BIT(28) +#define B_AX_FORCE_ZCD_BIAS BIT(21) +#define B_AX_POW_ZCD_L BIT(16) +#define B_AX_POWOCP_L1 BIT(12) +#define B_AX_REG_BYPASS_L BIT(7) +#define B_AX_FPWM_L1 BIT(6) + +#define R_AX_SPSANA_ON_CTRL1 0x0224 +#define B_AX_VO_DISCHG_PWM_H BIT(15) +#define B_AX_REG_MODE_PREDRIVER BIT(14) +#define B_AX_REG_LDOR_L BIT(9) +#define B_AX_PWM_FORCE BIT(8) +#define B_AX_PFM_PD_RST BIT(7) +#define B_AX_VC_PFM_RSTB BIT(6) +#define B_AX_PFM_IN_SEL BIT(5) +#define B_AX_VC_RSTB BIT(4) +#define B_AX_FPWMDELAY BIT(3) +#define B_AX_ENFPWMDELAY_H BIT(2) +#define B_AX_REG_MOS_HALF_L BIT(1) +#define B_AX_CURRENT_SENSE_MOS BIT(0) +#define B_AX_SPS_ANA_PFM_ZCDC_H_SH 4 +#define B_AX_SPS_ANA_PFM_ZCDC_H_MSK 0x3 +#define B_AX_SPS_ANA_PFM_OCP_L_SH 0 +#define B_AX_SPS_ANA_PFM_OCP_L_MSK 0x7 + +#define R_AX_AFE_ON_CTRL0 0x0240 +#define B_AX_REG_LPF_R3_SH 29 +#define B_AX_REG_LPF_R3_MSK 0x7 +#define B_AX_REG_LPF_R2_SH 24 +#define B_AX_REG_LPF_R2_MSK 0x1f +#define B_AX_REG_LPF_C3_SH 21 +#define B_AX_REG_LPF_C3_MSK 0x7 +#define B_AX_REG_LPF_C2_SH 18 +#define B_AX_REG_LPF_C2_MSK 0x7 +#define B_AX_REG_LPF_C1_SH 15 +#define B_AX_REG_LPF_C1_MSK 0x7 +#define B_AX_REG_LDO_SEL_SH 13 +#define B_AX_REG_LDO_SEL_MSK 0x3 +#define B_AX_REG_CP_ICPX2 BIT(12) +#define B_AX_REG_CP_ICP_SEL_FAST_SH 9 +#define B_AX_REG_CP_ICP_SEL_FAST_MSK 0x7 +#define B_AX_REG_CP_ICP_SEL_SH 6 +#define B_AX_REG_CP_ICP_SEL_MSK 0x7 +#define B_AX_REG_IB_PI_SH 4 +#define B_AX_REG_IB_PI_MSK 0x3 +#define B_AX_LDO2PWRCUT BIT(3) +#define B_AX_VPULSE_LDO BIT(2) + +#define R_AX_AFE_ON_CTRL1 0x0244 +#define B_AX_REG_CK_MON_SEL_SH 29 +#define B_AX_REG_CK_MON_SEL_MSK 0x7 +#define B_AX_REG_CK_MON_EN BIT(28) +#define B_AX_REG_XTAL_FREQ_SEL BIT(27) +#define B_AX_REG_XTAL_EDGE_SEL BIT(26) +#define B_AX_REG_VCO_KVCO BIT(25) +#define B_AX_REG_SDM_EDGE_SEL BIT(24) +#define B_AX_REG_SDM_CK_SEL BIT(23) +#define B_AX_REG_SDM_CK_GATED BIT(22) +#define B_AX_REG_PFD_RESET_GATED BIT(21) +#define B_AX_REG_LPF_R3_FAST_SH 16 +#define B_AX_REG_LPF_R3_FAST_MSK 0x1f +#define B_AX_REG_LPF_R2_FAST_SH 11 +#define B_AX_REG_LPF_R2_FAST_MSK 0x1f +#define B_AX_REG_LPF_C3_FAST_SH 8 +#define B_AX_REG_LPF_C3_FAST_MSK 0x7 +#define B_AX_REG_LPF_C2_FAST_SH 5 +#define B_AX_REG_LPF_C2_FAST_MSK 0x7 +#define B_AX_REG_LPF_C1_FAST_SH 2 +#define B_AX_REG_LPF_C1_FAST_MSK 0x7 +#define B_AX_REG_LPF_R3__SH 0 +#define B_AX_REG_LPF_R3__MSK 0x3 + +#define R_AX_AFE_ON_CTRL2 0x0248 +#define B_AX_AGPIO_DRV_SH 30 +#define B_AX_AGPIO_DRV_MSK 0x3 +#define B_AX_AGPIO_GPO BIT(29) +#define B_AX_AGPIO_GPE BIT(28) +#define B_AX_SEL_CLK BIT(27) +#define B_AX_LS_SDM_ORDER BIT(22) +#define B_AX_LS_DELAY_PH BIT(21) +#define B_AX_DIVIDER_SEL BIT(20) +#define B_AX_REG_BEACON BIT(6) +#define B_AX_REG_MBIASE BIT(5) +#define B_AX_REG_FAST_SEL_SH 3 +#define B_AX_REG_FAST_SEL_MSK 0x3 +#define B_AX_REG_CK480M_EN BIT(2) +#define B_AX_REG_CK320M_EN BIT(1) +#define B_AX_REG_CK_5M_EN BIT(0) + +#define R_AX_AFE_ON_CTRL3 0x024C +#define B_AX_REG_CK640M_EN BIT(0) + +#define R_AX_WLAN_XTAL_SI_CTRL 0x0270 +#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31) +#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30) +#define B_AX_WL_XTAL_GNT BIT(29) +#define B_AX_BT_XTAL_GNT BIT(28) +#define B_AX_WL_XTAL_SI_MODE_SH 24 +#define B_AX_WL_XTAL_SI_MODE_MSK 0x3 +#define B_AX_WL_XTAL_SI_BITMASK_SH 16 +#define B_AX_WL_XTAL_SI_BITMASK_MSK 0xff +#define B_AX_WL_XTAL_SI_DATA_SH 8 +#define B_AX_WL_XTAL_SI_DATA_MSK 0xff +#define B_AX_WL_XTAL_SI_ADDR_SH 0 +#define B_AX_WL_XTAL_SI_ADDR_MSK 0xff +#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274 +#define B_AX_XTAL_SI_CLK_DIV2 BIT(1) +#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0) + +#define R_AX_XTAL_ON_CTRL0 0x0280 +#define B_AX_XTAL_SC_LPS BIT(31) +#define B_AX_XTAL_SC_INIT_SH 24 +#define B_AX_XTAL_SC_INIT_MSK 0x7f +#define B_AX_XTAL_SC_XO_SH 17 +#define B_AX_XTAL_SC_XO_MSK 0x7f +#define B_AX_XTAL_SC_XI_SH 10 +#define B_AX_XTAL_SC_XI_MSK 0x7f +#define B_AX_XTAL_GMN_SH 5 +#define B_AX_XTAL_GMN_MSK 0x1f +#define B_AX_XTAL_GMP_SH 0 +#define B_AX_XTAL_GMP_MSK 0x1f +#define B_AX_EN_XBUF_DRV_LPS BIT(6) + +#define R_AX_XTAL_ON_CTRL1 0x0284 +#define B_AX_XTAL_VREF_SEL_SH 29 +#define B_AX_XTAL_VREF_SEL_MSK 0x7 +#define B_AX_XTAL_LPS_DIVISOR BIT(28) +#define B_AX_XTAL_CKDIGI_SEL BIT(27) +#define B_AX_EN_XTAL_SCHMITT BIT(26) +#define B_AX_XTAL_SEL_TOK_SH 23 +#define B_AX_XTAL_SEL_TOK_MSK 0x7 +#define B_AX_EN_XTAL_LPS_CLK BIT(22) +#define B_AX_XTAL_AAC_OPCUR_SH 20 +#define B_AX_XTAL_AAC_OPCUR_MSK 0x3 +#define B_AX_XTAL_LDO_VREF_SH 17 +#define B_AX_XTAL_LDO_VREF_MSK 0x7 +#define B_AX_EN_XTAL_DRV_BT BIT(16) +#define B_AX_EN_XTAL_DRV_BCN BIT(15) +#define B_AX_EN_XTAL_DRV_IQK BIT(14) +#define B_AX_EN_XTAL_DRV_LPS BIT(13) +#define B_AX_EN_XTAL_DRV_DIGI BIT(12) +#define B_AX_EN_XTAL_DRV_USB BIT(11) +#define B_AX_EN_XTAL_DRV_AFE BIT(10) +#define B_AX_XTAL_DRV_RF2N_RELAY BIT(9) +#define B_AX_XTAL_DRV_RF2P_RELAY BIT(8) +#define B_AX_EN_XTAL_DRV_RF2 BIT(7) +#define B_AX_EN_XTAL_DRV_RF1 BIT(6) +#define B_AX_XTAL_SC_LPS_SH 0 +#define B_AX_XTAL_SC_LPS_MSK 0x3f + +#define R_AX_XTAL_ON_CTRL2 0x0288 +#define B_AX_XTAL_VREF_SEL__SH 6 +#define B_AX_XTAL_VREF_SEL__MSK 0x3 +#define B_AX_AAC_MODE_SH 4 +#define B_AX_AAC_MODE_MSK 0x3 +#define B_AX_XTAL_CFIX_SH 0 +#define B_AX_XTAL_CFIX_MSK 0xf + +#define R_AX_SYM_ANAPAR_XTAL_MODE_DECODER 0x02A0 +#define B_AX_WIFI_FORCE_XTAL_HPMODE BIT(31) +#define B_AX_XTAL_LDO_LPS_SH 21 +#define B_AX_XTAL_LDO_LPS_MSK 0x7 +#define B_AX_XTAL_WAIT_CYC_SH 15 +#define B_AX_XTAL_WAIT_CYC_MSK 0x3f +#define B_AX_XTAL_LDO_OK_SH 12 +#define B_AX_XTAL_LDO_OK_MSK 0x7 +#define B_AX_XTAL_MD_LPOW BIT(11) +#define B_AX_XTAL_OV_RATIO_SH 9 +#define B_AX_XTAL_OV_RATIO_MSK 0x3 +#define B_AX_XTAL_OV_UNIT_SH 6 +#define B_AX_XTAL_OV_UNIT_MSK 0x7 +#define B_AX_XTAL_MODE_MANUAL_SH 4 +#define B_AX_XTAL_MODE_MANUAL_MSK 0x3 +#define B_AX_XTAL_MANU_SEL BIT(3) +#define B_AX_XTAL_MODE BIT(1) +#define B_AX_RESET_N_ BIT(0) + +#define R_AX_GPIO0_7_FUNC_SEL 0x02D0 +#define B_AX_PINMUX_GPIO7_FUNC_SEL_SH 28 +#define B_AX_PINMUX_GPIO7_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO6_FUNC_SEL_SH 24 +#define B_AX_PINMUX_GPIO6_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO5_FUNC_SEL_SH 20 +#define B_AX_PINMUX_GPIO5_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO4_FUNC_SEL_SH 16 +#define B_AX_PINMUX_GPIO4_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO3_FUNC_SEL_SH 12 +#define B_AX_PINMUX_GPIO3_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO2_FUNC_SEL_SH 8 +#define B_AX_PINMUX_GPIO2_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO1_FUNC_SEL_SH 4 +#define B_AX_PINMUX_GPIO1_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO0_FUNC_SEL_SH 0 +#define B_AX_PINMUX_GPIO0_FUNC_SEL_MSK 0xf + +#define R_AX_GPIO8_15_FUNC_SEL 0x02D4 +#define B_AX_PINMUX_GPIO15_FUNC_SEL_SH 28 +#define B_AX_PINMUX_GPIO15_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO14_FUNC_SEL_SH 24 +#define B_AX_PINMUX_GPIO14_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO13_FUNC_SEL_SH 20 +#define B_AX_PINMUX_GPIO13_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO12_FUNC_SEL_SH 16 +#define B_AX_PINMUX_GPIO12_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO11_FUNC_SEL_SH 12 +#define B_AX_PINMUX_GPIO11_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO10_FUNC_SEL_SH 8 +#define B_AX_PINMUX_GPIO10_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO9_FUNC_SEL_SH 4 +#define B_AX_PINMUX_GPIO9_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_GPIO8_FUNC_SEL_SH 0 +#define B_AX_PINMUX_GPIO8_FUNC_SEL_MSK 0xf + +#define R_AX_EECS_EESK_FUNC_SEL 0x02D8 +#define B_AX_PINMUX_LED1_FUNC_SEL_SH 8 +#define B_AX_PINMUX_LED1_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_EESK_FUNC_SEL_SH 4 +#define B_AX_PINMUX_EESK_FUNC_SEL_MSK 0xf +#define B_AX_PINMUX_EECS_FUNC_SEL_SH 0 +#define B_AX_PINMUX_EECS_FUNC_SEL_MSK 0xf + +#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN 0x02E0 +#define B_AX_LED1_PULL_HIGH_EN BIT(18) +#define B_AX_EESK_PULL_HIGH_EN BIT(17) +#define B_AX_EECS_PULL_HIGH_EN BIT(16) +#define B_AX_GPIO15_PULL_HIGH_EN BIT(15) +#define B_AX_GPIO14_PULL_HIGH_EN BIT(14) +#define B_AX_GPIO13_PULL_HIGH_EN BIT(13) +#define B_AX_GPIO12_PULL_HIGH_EN BIT(12) +#define B_AX_GPIO11_PULL_HIGH_EN BIT(11) +#define B_AX_GPIO10_PULL_HIGH_EN BIT(10) +#define B_AX_GPIO9_PULL_HIGH_EN BIT(9) +#define B_AX_GPIO8_PULL_HIGH_EN BIT(8) +#define B_AX_GPIO7_PULL_HIGH_EN BIT(7) +#define B_AX_GPIO6_PULL_HIGH_EN BIT(6) +#define B_AX_GPIO5_PULL_HIGH_EN BIT(5) +#define B_AX_GPIO4_PULL_HIGH_EN BIT(4) +#define B_AX_GPIO3_PULL_HIGH_EN BIT(3) +#define B_AX_GPIO2_PULL_HIGH_EN BIT(2) +#define B_AX_GPIO1_PULL_HIGH_EN BIT(1) +#define B_AX_GPIO0_PULL_HIGH_EN BIT(0) + +#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 +#define B_AX_LED1_PULL_LOW_EN BIT(18) +#define B_AX_EESK_PULL_LOW_EN BIT(17) +#define B_AX_EECS_PULL_LOW_EN BIT(16) +#define B_AX_GPIO15_PULL_LOW_EN BIT(15) +#define B_AX_GPIO14_PULL_LOW_EN BIT(14) +#define B_AX_GPIO13_PULL_LOW_EN BIT(13) +#define B_AX_GPIO12_PULL_LOW_EN BIT(12) +#define B_AX_GPIO11_PULL_LOW_EN BIT(11) +#define B_AX_GPIO10_PULL_LOW_EN BIT(10) +#define B_AX_GPIO9_PULL_LOW_EN BIT(9) +#define B_AX_GPIO8_PULL_LOW_EN BIT(8) +#define B_AX_GPIO7_PULL_LOW_EN BIT(7) +#define B_AX_GPIO6_PULL_LOW_EN BIT(6) +#define B_AX_GPIO5_PULL_LOW_EN BIT(5) +#define B_AX_GPIO4_PULL_LOW_EN BIT(4) +#define B_AX_GPIO3_PULL_LOW_EN BIT(3) +#define B_AX_GPIO2_PULL_LOW_EN BIT(2) +#define B_AX_GPIO1_PULL_LOW_EN BIT(1) +#define B_AX_GPIO0_PULL_LOW_EN BIT(0) + +#define R_AX_WLRF_CTRL 0x02F0 +#define B_AX_AFC_AFEDIG BIT(17) +#define B_AX_WLRF1_CTRL_7 BIT(15) +#define B_AX_WLRF1_CTRL_6 BIT(14) +#define B_AX_WLRF1_CTRL_5 BIT(13) +#define B_AX_WLRF1_CTRL_4 BIT(12) +#define B_AX_WLRF1_CTRL_3 BIT(11) +#define B_AX_WLRF1_CTRL_2 BIT(10) +#define B_AX_WLRF1_CTRL_1 BIT(9) +#define B_AX_WLRF1_CTRL_0 BIT(8) +#define B_AX_WLRF_CTRL_7 BIT(7) +#define B_AX_WLRF_CTRL_6 BIT(6) +#define B_AX_WLRF_CTRL_5 BIT(5) +#define B_AX_WLRF_CTRL_4 BIT(4) +#define B_AX_WLRF_CTRL_3 BIT(3) +#define B_AX_WLRF_CTRL_2 BIT(2) +#define B_AX_WLRF_CTRL_1 BIT(1) +#define B_AX_WLRF_CTRL_0 BIT(0) + +#define R_AX_TMETER 0x0390 +#define B_AX_TEMP_VALID BIT(31) +#define B_AX_TEMP_VALUE_SH 24 +#define B_AX_TEMP_VALUE_MSK 0x3f +#define B_AX_REG_TMETER_TIMER_SH 8 +#define B_AX_REG_TMETER_TIMER_MSK 0xfff +#define B_AX_REG_TEMP_DELTA_SH 2 +#define B_AX_REG_TEMP_DELTA_MSK 0x3f +#define B_AX_REG_TMETER_EN BIT(0) +#define B_AX_OSC_32K_CLKGEN_0_SH 16 +#define B_AX_OSC_32K_CLKGEN_0_MSK 0xffff +#define B_AX_OSC_32K_RES_COMP_SH 4 +#define B_AX_OSC_32K_RES_COMP_MSK 0x3 +#define B_AX_OSC_32K_OUT_SEL BIT(3) +#define B_AX_ISO_WL_2_OSC_32K BIT(1) +#define B_AX_POW_CKGEN BIT(0) +#define B_AX_CAL_32K_DBGMOD BIT(28) +#define B_AX_CAL32K_WR BIT(23) +#define B_AX_CAL_OSC_XTAL_SEL BIT(22) + +#define R_AX_32K_CAL_REG1 0x039C +#define B_AX_OSC32K_RCAL_SEL BIT(31) +#define B_AX_OSC32K_RCAL_RPT_SH 16 +#define B_AX_OSC32K_RCAL_RPT_MSK 0x7fff +#define B_AX_OSC32K_RCAL_SH 0 +#define B_AX_OSC32K_RCAL_MSK 0x7fff + +#define R_AX_IC_PWR_STATE 0x03F0 +#define B_AX_WHOLE_SYS_PWR_STE_SH 16 +#define B_AX_WHOLE_SYS_PWR_STE_MSK 0x3ff +#define B_AX_WLMAC_PWR_STE_SH 8 +#define B_AX_WLMAC_PWR_STE_MSK 0x3 +#define B_AX_UART_HCISYS_PWR_STE_SH 6 +#define B_AX_UART_HCISYS_PWR_STE_MSK 0x3 +#define B_AX_SDIO_HCISYS_PWR_STE_SH 4 +#define B_AX_SDIO_HCISYS_PWR_STE_MSK 0x3 +#define B_AX_USB_HCISYS_PWR_STE_SH 2 +#define B_AX_USB_HCISYS_PWR_STE_MSK 0x3 +#define B_AX_PCIE_HCISYS_PWR_STE_SH 0 +#define B_AX_PCIE_HCISYS_PWR_STE_MSK 0x3 + +#define R_AX_SPS_DIG_OFF_CTRL0 0x0400 +#define B_AX_SDZN_L_SH 30 +#define B_AX_SDZN_L_MSK 0x3 +#define B_AX_REG_AUTOZCD_L BIT(29) +#define B_AX_REG_VOFB_SEL BIT(28) +#define B_AX_TBOX_L1_SH 26 +#define B_AX_TBOX_L1_MSK 0x3 +#define B_AX_ENOCPMUX_L BIT(25) +#define B_AX_FORCE_LDOS BIT(24) +#define B_AX_VO_DISCHG BIT(23) +#define B_AX_LDO_OC_CLAMP BIT(22) +#define B_AX_MINOFF_LIQ BIT(21) +#define B_AX_MINON_LIQ BIT(20) +#define B_AX_POW_AUTO_L BIT(19) +#define B_AX_ARENB_H BIT(18) +#define B_AX_NO_OFFTIME_L BIT(17) +#define B_AX_EN_ON_END_L BIT(16) +#define B_AX_ENCOT_L BIT(15) +#define B_AX_REG_CLK_SEL_SH 13 +#define B_AX_REG_CLK_SEL_MSK 0x3 +#define B_AX_REG_TYPE_L BIT(12) +#define B_AX_R3_L1_SH 10 +#define B_AX_R3_L1_MSK 0x3 +#define B_AX_R2_L1_SH 8 +#define B_AX_R2_L1_MSK 0x3 +#define B_AX_R1_L1_SH 6 +#define B_AX_R1_L1_MSK 0x3 +#define B_AX_C3_L1_SH 4 +#define B_AX_C3_L1_MSK 0x3 +#define B_AX_C2_L1_SH 2 +#define B_AX_C2_L1_MSK 0x3 +#define B_AX_C1_L1_SH 0 +#define B_AX_C1_L1_MSK 0x3 + +#define R_AX_SPS_DIG_OFF_CTRL1 0x0404 +#define B_AX_REG_NMOS_OFF_L BIT(5) +#define B_AX_REG_MUX_PI_L BIT(4) +#define B_AX_REG_PWM_CTRL_L BIT(3) +#define B_AX_ENSR_L BIT(2) +#define B_AX_SDZP_L_SH 0 +#define B_AX_SDZP_L_MSK 0x3 + +#define R_AX_SPSLDO_OFF_CTRL0 0x0400 +#define B_AX_SDZN_L_SH 30 +#define B_AX_SDZN_L_MSK 0x3 +#define B_AX_REG_AUTOZCD_L BIT(29) +#define B_AX_REG_VOFB_SEL BIT(28) +#define B_AX_TBOX_L1_SH 26 +#define B_AX_TBOX_L1_MSK 0x3 +#define B_AX_ENOCPMUX_L BIT(25) +#define B_AX_FORCE_LDOS BIT(24) +#define B_AX_VO_DISCHG BIT(23) +#define B_AX_LDO_OC_CLAMP BIT(22) +#define B_AX_MINOFF_LIQ BIT(21) +#define B_AX_MINON_LIQ BIT(20) +#define B_AX_POW_AUTO_L BIT(19) +#define B_AX_ARENB_H BIT(18) +#define B_AX_NO_OFFTIME_L BIT(17) +#define B_AX_EN_ON_END_L BIT(16) +#define B_AX_ENCOT_L BIT(15) +#define B_AX_REG_CLK_SEL_SH 13 +#define B_AX_REG_CLK_SEL_MSK 0x3 +#define B_AX_REG_TYPE_L BIT(12) +#define B_AX_R3_L1_SH 10 +#define B_AX_R3_L1_MSK 0x3 +#define B_AX_R2_L1_SH 8 +#define B_AX_R2_L1_MSK 0x3 +#define B_AX_R1_L1_SH 6 +#define B_AX_R1_L1_MSK 0x3 +#define B_AX_C3_L1_SH 4 +#define B_AX_C3_L1_MSK 0x3 +#define B_AX_C2_L1_SH 2 +#define B_AX_C2_L1_MSK 0x3 +#define B_AX_C1_L1_SH 0 +#define B_AX_C1_L1_MSK 0x3 + +#define R_AX_SPSLDO_OFF_CTRL1 0x0404 +#define B_AX_REG_NMOS_OFF_L BIT(5) +#define B_AX_REG_MUX_PI_L BIT(4) +#define B_AX_REG_PWM_CTRL_L BIT(3) +#define B_AX_ENSR_L BIT(2) +#define B_AX_SDZP_L_SH 0 +#define B_AX_SDZP_L_MSK 0x3 + +#define R_AX_SPSANA_OFF_CTRL0 0x0420 +#define B_AX_REG_AUTOZCD_L BIT(29) +#define B_AX_REG_VOFB_SEL BIT(28) +#define B_AX_ENOCPMUX_L BIT(25) +#define B_AX_FORCE_LDOS BIT(24) +#define B_AX_VO_DISCHG BIT(23) +#define B_AX_LDO_OC_CLAMP BIT(22) +#define B_AX_MINOFF_LIQ BIT(21) +#define B_AX_MINON_LIQ BIT(20) +#define B_AX_POW_AUTO_L BIT(19) +#define B_AX_ARENB_H BIT(18) +#define B_AX_NO_OFFTIME_L BIT(17) +#define B_AX_EN_ON_END_L BIT(16) +#define B_AX_ENCOT_L BIT(15) +#define B_AX_REG_TYPE_L BIT(12) + +#define R_AX_SPSANA_OFF_CTRL1 0x0424 +#define B_AX_REG_NMOS_OFF_L BIT(5) +#define B_AX_REG_MUX_PI_L BIT(4) +#define B_AX_REG_PWM_CTRL_L BIT(3) +#define B_AX_ENSR_L BIT(2) + +#define R_AX_AFE_OFF_CTRL0 0x0440 +#define B_AX_S1_AD0_LDO2PWRCUT BIT(31) +#define B_AX_S1_AD_SEL_Q_SH 27 +#define B_AX_S1_AD_SEL_Q_MSK 0xf +#define B_AX_S1_AD_SEL_I_SH 23 +#define B_AX_S1_AD_SEL_I_MSK 0xf +#define B_AX_S0_DA1_LDO_VSEL_SH 21 +#define B_AX_S0_DA1_LDO_VSEL_MSK 0x3 +#define B_AX_S0_DA1_LDO2PWRCUT BIT(20) +#define B_AX_S0_DA0_LDO_VSEL_SH 18 +#define B_AX_S0_DA0_LDO_VSEL_MSK 0x3 +#define B_AX_S0_DA0_LDO2PWRCUT BIT(17) +#define B_AX_S0_AD2_LDO_VSEL_SH 15 +#define B_AX_S0_AD2_LDO_VSEL_MSK 0x3 +#define B_AX_S0_AD2_LDO2PWRCUT BIT(14) +#define B_AX_S0_AD1_LDO_VSEL_SH 12 +#define B_AX_S0_AD1_LDO_VSEL_MSK 0x3 +#define B_AX_S0_AD1_LDO2PWRCUT BIT(11) +#define B_AX_S0_AD0_LDO_VSEL_SH 9 +#define B_AX_S0_AD0_LDO_VSEL_MSK 0x3 +#define B_AX_S0_AD0_LDO2PWRCUT BIT(8) +#define B_AX_S0_AD_SEL_Q_SH 4 +#define B_AX_S0_AD_SEL_Q_MSK 0xf +#define B_AX_S0_AD_SEL_I_SH 0 +#define B_AX_S0_AD_SEL_I_MSK 0xf + +#define R_AX_AFE_OFF_CTRL1 0x0444 +#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL_SH 24 +#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL_MSK 0x3 +#define B_AX_S1_DAI2V_LDO2PWRCUT BIT(23) +#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL__SH 21 +#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL__MSK 0x3 +#define B_AX_S0_DAI2V_LDO2PWRCUT BIT(20) +#define B_AX_S0_RXBB__LDO_VSEL_SH 18 +#define B_AX_S0_RXBB__LDO_VSEL_MSK 0x3 +#define B_AX_S0_RXBB__LDO2PWRCUT BIT(17) +#define B_AX_S0_RXBB__LDO_VSEL__SH 15 +#define B_AX_S0_RXBB__LDO_VSEL__MSK 0x3 +#define B_AX_S0_RXBB_LDO2PWRCUT BIT(14) +#define B_AX_S1_DA1_LDO_VSEL_SH 12 +#define B_AX_S1_DA1_LDO_VSEL_MSK 0x3 +#define B_AX_S1_DA1_LDO2PWRCUT BIT(11) +#define B_AX_S1_DA0_LDO_VSEL_SH 9 +#define B_AX_S1_DA0_LDO_VSEL_MSK 0x3 +#define B_AX_S1_DA0_LDO2PWRCUT BIT(8) +#define B_AX_S1_AD2_LDO_VSEL_SH 6 +#define B_AX_S1_AD2_LDO_VSEL_MSK 0x3 +#define B_AX_S1_AD2_LDO2PWRCUT BIT(5) +#define B_AX_S1_AD1_LDO_VSEL_SH 3 +#define B_AX_S1_AD1_LDO_VSEL_MSK 0x3 +#define B_AX_S1_AD1_LDO2PWRCUT BIT(2) +#define B_AX_S1_AD0_LDO_VSEL_SH 0 +#define B_AX_S1_AD0_LDO_VSEL_MSK 0x3 + +#define R_AX_XTAL_OFF_CTRL0 0x0480 +#define B_AX_XTAL_PK_SEL_OFFSET BIT(31) +#define B_AX_XTAL_MANU_PK_SEL_SH 29 +#define B_AX_XTAL_MANU_PK_SEL_MSK 0x3 +#define B_AX_XTAL_AACK_PK_MANU BIT(28) +#define B_AX_EN_XTAL_AAC_PKDET BIT(27) +#define B_AX_EN_XTAL_AAC_GM BIT(26) +#define B_AX_XTAL_LDO_OPVB_SEL BIT(25) +#define B_AX_XTAL_LDO_NC BIT(24) +#define B_AX_XTAL_LPMODE BIT(23) +#define B_AX_XTAL_DELAY_DIGI BIT(22) +#define B_AX_XTAL_DELAY_USB BIT(21) +#define B_AX_XTAL_DELAY_AFE BIT(20) +#define B_AX_XTAL_DRV_BT_SH 18 +#define B_AX_XTAL_DRV_BT_MSK 0x3 +#define B_AX_XTAL_DRV_DIGI_SH 16 +#define B_AX_XTAL_DRV_DIGI_MSK 0x3 +#define B_AX_XTAL_DRV_USB_SH 14 +#define B_AX_XTAL_DRV_USB_MSK 0x3 +#define B_AX_XTAL_DRV_AFE_SH 12 +#define B_AX_XTAL_DRV_AFE_MSK 0x3 +#define B_AX_XTAL_DRV_RF2_RELAY_SH 10 +#define B_AX_XTAL_DRV_RF2_RELAY_MSK 0x3 +#define B_AX_XTAL_DRV_RF2_SH 8 +#define B_AX_XTAL_DRV_RF2_MSK 0x3 +#define B_AX_XTAL_DRV_RF1_SH 6 +#define B_AX_XTAL_DRV_RF1_MSK 0x3 +#define B_AX_XTAL_DRV_RF_LATCH BIT(5) +#define B_AX_XTAL_GM_SEP BIT(4) +#define B_AX_XQSEL_RF_AWAKE BIT(3) +#define B_AX_XQSEL_RF_INITIAL BIT(2) +#define B_AX_XQSEL BIT(1) +#define B_AX_GATED_XTAL_OK0 BIT(0) + +#define R_AX_XTAL_OFF_CTRL1 0x0484 +#define B_AX_XTAL_LDO_VREF_UP_SH 14 +#define B_AX_XTAL_LDO_VREF_UP_MSK 0x7 +#define B_AX_XTAL_EN_LNBUF BIT(13) +#define B_AX_XTAL__AAC_TIE_MID BIT(12) +#define B_AX_XTAL_AAC_IOFFSET_SH 10 +#define B_AX_XTAL_AAC_IOFFSET_MSK 0x3 +#define B_AX_XTAL_AAC_CAP_SH 8 +#define B_AX_XTAL_AAC_CAP_MSK 0x3 +#define B_AX_XTAL_PDSW_SH 6 +#define B_AX_XTAL_PDSW_MSK 0x3 +#define B_AX_XTAL_LPS_BUF_VB_SH 4 +#define B_AX_XTAL_LPS_BUF_VB_MSK 0x3 +#define B_AX_XTAL_PDCK_MANU BIT(3) +#define B_AX_XTAL_PDCK_OK_MANU BIT(2) +#define B_AX_EN_XTAL_PDCK_VREF BIT(1) +#define B_AX_XTAL_SEL_PWR BIT(0) + +#define R_AX_SYM_ANAPAR_XTAL_AAC_0 0x04A0 +#define B_AX_XAAC_LPOW BIT(31) +#define B_AX_AAC_MODE__SH 29 +#define B_AX_AAC_MODE__MSK 0x3 +#define B_AX_EN_XTAL_AAC_TRIG BIT(28) +#define B_AX_EN_XTAL_AAC BIT(27) +#define B_AX_EN_XTAL_AAC_DIGI BIT(26) +#define B_AX_GM_MANUAL_SH 21 +#define B_AX_GM_MANUAL_MSK 0x1f +#define B_AX_GM_STUP_SH 16 +#define B_AX_GM_STUP_MSK 0x1f +#define B_AX_XTAL_CK_SET_SH 13 +#define B_AX_XTAL_CK_SET_MSK 0x7 +#define B_AX_GM_INIT_SH 8 +#define B_AX_GM_INIT_MSK 0x1f +#define B_AX_GM_STEP BIT(7) +#define B_AX_XAAC_GM_OFFSET_SH 2 +#define B_AX_XAAC_GM_OFFSET_MSK 0x1f +#define B_AX_OFFSET_PLUS BIT(1) +#define B_AX_RESET_N BIT(0) + +#define R_AX_SYM_ANAPAR_XTAL_AAC_1 0x04A4 +#define B_AX_PK_END_AR_SH 2 +#define B_AX_PK_END_AR_MSK 0x3 +#define B_AX_PK_START_AR_SH 0 +#define B_AX_PK_START_AR_MSK 0x3 + +#define R_AX_SYM_ANAPAR_XTAL_PDCK 0x04C0 +#define B_AX_EN_XTAL_PDCK_DIGI_SH 17 +#define B_AX_EN_XTAL_PDCK_DIGI_MSK 0x1f +#define B_AX_PDCK_SEARCH_MODE_SH 15 +#define B_AX_PDCK_SEARCH_MODE_MSK 0x3 +#define B_AX_PDCK_WAIT_CYC_SH 10 +#define B_AX_PDCK_WAIT_CYC_MSK 0x1f +#define B_AX_VREF_MANUAL_SH 5 +#define B_AX_VREF_MANUAL_MSK 0x1f +#define B_AX_VREF_INIT_SH 3 +#define B_AX_VREF_INIT_MSK 0x3 +#define B_AX_XTAL_PDCK_UNIT BIT(2) +#define B_AX_XPDCK_VREF_SEL BIT(1) +#define B_AX_PDCK_LPOW BIT(0) + +// +// AON_C +// + +#define R_AX_SEC_CTRL 0x0C00 +#define B_AX_SEC_IDMEM_SIZE_CONFIG_SH 16 +#define B_AX_SEC_IDMEM_SIZE_CONFIG_MSK 0x3 +#define B_AX_SEC_BT_SEC1_DIS BIT(15) +#define B_AX_SEC_BT_SEC0_DIS BIT(14) +#define B_AX_SEC_UART_RX_EN BIT(4) +#define B_AX_SEC_UART_TX_EN BIT(3) +#define B_AX_SEC_JTAG_EN BIT(2) +#define B_AX_SEC_SIC_EN BIT(1) +#define B_AX_SEC_SEC_DIS BIT(0) + +#define R_AX_FILTER_MODEL_ADDR 0x0C04 +#define B_AX_SEC_FILTER_MODEL_ADDR_SH 0 +#define B_AX_SEC_FILTER_MODEL_ADDR_MSK 0xffffffffL + +#define R_AX_EFUSE_CTRL_S 0x0C30 +#define B_AX_EF_MODE_SEL_S_SH 30 +#define B_AX_EF_MODE_SEL_S_MSK 0x3 +#define B_AX_EF_RDY_S BIT(29) +#define B_AX_EF_ADDR_S_SH 16 +#define B_AX_EF_ADDR_S_MSK 0x7ff +#define B_AX_EF_DATA_S_SH 0 +#define B_AX_EF_DATA_S_MSK 0xffff + +#define R_AX_EFUSE_TEST_S 0x0C34 +#define B_AX_EF_CRES_SEL_S BIT(31) +#define B_AX_EF_SCAN_SADR_S_SH 19 +#define B_AX_EF_SCAN_SADR_S_MSK 0x7ff +#define B_AX_EF_SCAN_EADR_S_SH 8 +#define B_AX_EF_SCAN_EADR_S_MSK 0x7ff +#define B_AX_EF_SCAN_TRPT_S BIT(7) +#define B_AX_EF_SCAN_FTHR_S_SH 0 +#define B_AX_EF_SCAN_FTHR_S_MSK 0x7f + +// +// WL_AX_Reg_AXIDMA.xls +// + +// +// AXIDMA_Reg_Spec +// + +#define R_PL_AXIDMA_INIT_CFG1 0x0000 +#define B_PL_AXIDMA__MASTER_STOP BIT(20) +#define B_PL_AXIDMA_RESET_KEEP_REG BIT(19) +#define B_PL_AXIDMA_RX_EN BIT(13) +#define B_PL_AXIDMA_TX_EN BIT(11) + +#define R_PL_AXIDMA_DMA_STOP 0x0004 +#define B_PL_AXIDMA_WPDMA_STOP BIT(12) +#define B_PL_AXIDMA_CH3_TX_STOP BIT(11) +#define B_PL_AXIDMA_CH2_TX_STOP BIT(10) +#define B_PL_AXIDMA_CH1_TX_STOP BIT(9) +#define B_PL_AXIDMA_CH0_TX_STOP BIT(8) + +#define R_PL_AXIDMA_INIT_CFG2 0x0008 +#define B_PL_AXIDMA_WD_ITVL_ACT_SH 24 +#define B_PL_AXIDMA_WD_ITVL_ACT_MSK 0xff +#define B_PL_AXIDMA_WD_ITVL_IDLE_SH 16 +#define B_PL_AXIDMA_WD_ITVL_IDLE_MSK 0xff + +#define R_PL_AXIDMA_INFO 0x0100 +#define B_PL_AXIDMA_MASTER_IDLE BIT(16) +#define B_PL_AXIDMA_RX_IDLE BIT(1) +#define B_PL_AXIDMA_TX_IDLE BIT(0) + +#define R_PL_AXIDMA_BUSY 0x0104 +#define B_PL_AXIDMA_WPDMA_BUSY BIT(12) +#define B_PL_AXIDMA_CH3_TX_BUSY BIT(11) +#define B_PL_AXIDMA_CH2_TX_BUSY BIT(10) +#define B_PL_AXIDMA_CH1_TX_BUSY BIT(9) +#define B_PL_AXIDMA_CH0_TX_BUSY BIT(8) +#define B_PL_AXIDMA_CH5_RX_BUSY BIT(5) +#define B_PL_AXIDMA_CH4_RX_BUSY BIT(4) +#define B_PL_AXIDMA_CH3_RX_BUSY BIT(3) +#define B_PL_AXIDMA_CH2_RX_BUSY BIT(2) +#define B_PL_AXIDMA_CH1_RX_BUSY BIT(1) +#define B_PL_AXIDMA_CH0_RX_BUSY BIT(0) + +#define R_PL_AXIDMA_INT_MIT_TX 0x0200 +#define B_PL_AXIDMA_TXMIT_CH3_SEL BIT(22) +#define B_PL_AXIDMA_TXMIT_CH2_SEL BIT(21) +#define B_PL_AXIDMA_TXMIT_CH1_SEL BIT(20) +#define B_PL_AXIDMA_TXMIT_CH0_SEL BIT(19) +#define B_PL_AXIDMA_TXTIMER_UNIT_SH 16 +#define B_PL_AXIDMA_TXTIMER_UNIT_MSK 0x3 +#define B_PL_AXIDMA_TXCOUNTER_MATCH_SH 8 +#define B_PL_AXIDMA_TXCOUNTER_MATCH_MSK 0xff +#define B_PL_AXIDMA_TXTIMER_MATCH_SH 0 +#define B_PL_AXIDMA_TXTIMER_MATCH_MSK 0xff + +#define R_PL_AXIDMA_INT_MIT_RX 0x0204 +#define B_PL_AXIDMA_RXMIT_CH5_SEL BIT(24) +#define B_PL_AXIDMA_RXMIT_CH4_SEL BIT(23) +#define B_PL_AXIDMA_RXMIT_CH3_SEL BIT(22) +#define B_PL_AXIDMA_RXMIT_CH2_SEL BIT(21) +#define B_PL_AXIDMA_RXMIT_CH1_SEL BIT(20) +#define B_PL_AXIDMA_RXMIT_CH0_SEL BIT(19) +#define B_PL_AXIDMA_RXTIMER_UNIT_SH 16 +#define B_PL_AXIDMA_RXTIMER_UNIT_MSK 0x3 +#define B_PL_AXIDMA_RXCOUNTER_MATCH_SH 8 +#define B_PL_AXIDMA_RXCOUNTER_MATCH_MSK 0xff +#define B_PL_AXIDMA_RXTIMER_MATCH_SH 0 +#define B_PL_AXIDMA_RXTIMER_MATCH_MSK 0xff + +#define R_PL_AXIDMA_CH0_RXBD_NUM 0x0300 +#define B_PL_AXIDMA_CH0_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH0_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH1_RXBD_NUM 0x0302 +#define B_PL_AXIDMA_CH1_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH1_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH2_RXBD_NUM 0x0304 +#define B_PL_AXIDMA_CH2_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH2_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH3_RXBD_NUM 0x0306 +#define B_PL_AXIDMA_CH3_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH3_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH4_RXBD_NUM 0x0308 +#define B_PL_AXIDMA_CH4_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH4_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH5_RXBD_NUM 0x030A +#define B_PL_AXIDMA_CH5_RXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH5_RXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH0_TXBD_NUM 0x0320 +#define B_PL_AXIDMA_CH0_TXBD_FLAG BIT(14) +#define B_PL_AXIDMA_CH0_TXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH0_TXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH1_TXBD_NUM 0x0322 +#define B_PL_AXIDMA_CH1_TXBD_FLAG BIT(14) +#define B_PL_AXIDMA_CH1_TXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH1_TXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH2_TXBD_NUM 0x0324 +#define B_PL_AXIDMA_CH2_TXBD_FLAG BIT(14) +#define B_PL_AXIDMA_CH2_TXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH2_TXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH3_TXBD_NUM 0x0326 +#define B_PL_AXIDMA_CH3_TXBD_FLAG BIT(14) +#define B_PL_AXIDMA_CH3_TXBD_NUM_SH 0 +#define B_PL_AXIDMA_CH3_TXBD_NUM_MSK 0xfff + +#define R_PL_AXIDMA_CH0_RXBD_IDX 0x0400 +#define B_PL_AXIDMA_CH0_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH0_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH0_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH0_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH1_RXBD_IDX 0x0404 +#define B_PL_AXIDMA_CH1_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH1_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH1_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH1_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH2_RXBD_IDX 0x0408 +#define B_PL_AXIDMA_CH2_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH2_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH2_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH2_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH3_RXBD_IDX 0x040C +#define B_PL_AXIDMA_CH3_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH3_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH3_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH3_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH4_RXBD_IDX 0x0410 +#define B_PL_AXIDMA_CH4_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH4_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH4_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH4_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH5_RXBD_IDX 0x0414 +#define B_PL_AXIDMA_CH5_RX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH5_RX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH5_RX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH5_RX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH0_TXBD_IDX 0x0420 +#define B_PL_AXIDMA_CH0_TX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH0_TX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH0_TX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH0_TX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH1_TXBD_IDX 0x0424 +#define B_PL_AXIDMA_CH1_TX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH1_TX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH1_TX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH1_TX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH2_TXBD_IDX 0x0428 +#define B_PL_AXIDMA_CH2_TX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH2_TX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH2_TX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH2_TX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_CH3_TXBD_IDX 0x042C +#define B_PL_AXIDMA_CH3_TX_HW_IDX_SH 16 +#define B_PL_AXIDMA_CH3_TX_HW_IDX_MSK 0xfff +#define B_PL_AXIDMA_CH3_TX_HOST_IDX_SH 0 +#define B_PL_AXIDMA_CH3_TX_HOST_IDX_MSK 0xfff + +#define R_PL_AXIDMA_TXBD_RWPTR_CLR 0x0430 +#define B_PL_AXIDMA_CLR_CH3_TX_IDX BIT(3) +#define B_PL_AXIDMA_CLR_CH2_TX_IDX BIT(2) +#define B_PL_AXIDMA_CLR_CH1_TX_IDX BIT(1) +#define B_PL_AXIDMA_CLR_CH0_TX_IDX BIT(0) + +#define R_PL_AXIDMA_RXBD_RWPTR_CLR 0x0434 +#define B_PL_AXIDMA_CLR_CH5_RX_IDX BIT(5) +#define B_PL_AXIDMA_CLR_CH4_RX_IDX BIT(4) +#define B_PL_AXIDMA_CLR_CH3_RX_IDX BIT(3) +#define B_PL_AXIDMA_CLR_CH2_RX_IDX BIT(2) +#define B_PL_AXIDMA_CLR_CH1_RX_IDX BIT(1) +#define B_PL_AXIDMA_CLR_CH0_RX_IDX BIT(0) + +#define R_PL_AXIDMA_DBG_CTRL 0x0500 +#define B_PL_AXIDMA_DBG_SEL_SH 16 +#define B_PL_AXIDMA_DBG_SEL_MSK 0x1ff +#define B_PL_AXIDMA_SEC_ACCESS BIT(2) +#define B_PL_AXIDMA_EN_STUCK_DBG BIT(0) + +#define R_PL_AXIDMA_DBG_ERR_FLAG 0x0504 +#define B_PL_AXIDMA_CH1_RX_FULL BIT(29) +#define B_PL_AXIDMA_CH0_RX_FULL BIT(28) +#define B_PL_AXIDMA_RX_STUCK BIT(22) +#define B_PL_AXIDMA_TX_STUCK BIT(21) +#define B_PL_AXIDMA_DBG_TXERR BIT(16) +#define B_PL_AXIDMA_CH5_RX_FULL BIT(5) +#define B_PL_AXIDMA_CH4_RX_FULL BIT(4) +#define B_PL_AXIDMA_CH3_RX_FULL BIT(3) +#define B_PL_AXIDMA_CH2_RX_FULL BIT(2) +#define B_PL_AXIDMA_TXBD_LEN0 BIT(1) +#define B_PL_AXIDMA_TXBD_4KBOUD_LENERR BIT(0) + +#define R_PL_AXIDMA_CH0_RXBD_DESA_L 0x0600 +#define B_PL_AXIDMA_CH0_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH0_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH1_RXBD_DESA_L 0x0608 +#define B_PL_AXIDMA_CH1_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH1_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH2_RXBD_DESA_L 0x0610 +#define B_PL_AXIDMA_CH2_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH2_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH3_RXBD_DESA_L 0x0618 +#define B_PL_AXIDMA_CH3_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH3_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH4_RXBD_DESA_L 0x0620 +#define B_PL_AXIDMA_CH4_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH4_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH5_RXBD_DESA_L 0x0628 +#define B_PL_AXIDMA_CH5_RXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH5_RXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH0_TXBD_DESA_L 0x0640 +#define B_PL_AXIDMA_CH0_TXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH0_TXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH1_TXBD_DESA_L 0x0648 +#define B_PL_AXIDMA_CH1_TXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH1_TXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH2_TXBD_DESA_L 0x0650 +#define B_PL_AXIDMA_CH2_TXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH2_TXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_CH3_TXBD_DESA_L 0x0658 +#define B_PL_AXIDMA_CH3_TXBD_DESA_L_SH 0 +#define B_PL_AXIDMA_CH3_TXBD_DESA_L_MSK 0xffffffffL + +#define R_PL_AXIDMA_FC_CTRL1 0x0700 +#define B_PL_AXIDMA_FC_MODE BIT(2) +#define B_PL_AXIDMA_SET1_FC_EN BIT(1) +#define B_PL_AXIDMA_SET0_FC_EN BIT(0) + +#define R_PL_AXIDMA_FC_CTRL2 0x0704 +#define B_PL_AXIDMA_SET1_PREC_PAGE_SH 16 +#define B_PL_AXIDMA_SET1_PREC_PAGE_MSK 0x1ff +#define B_PL_AXIDMA_SET0_PREC_PAGE_SH 0 +#define B_PL_AXIDMA_SET0_PREC_PAGE_MSK 0x1ff + +#define R_PL_AXIDMA_CH1_PAGE_CTRL 0x0710 +#define B_PL_AXIDMA_CH1_GRP BIT(31) +#define B_PL_AXIDMA_CH1_MAX_PG_SH 16 +#define B_PL_AXIDMA_CH1_MAX_PG_MSK 0x1fff +#define B_PL_AXIDMA_CH1_MIN_PG_SH 0 +#define B_PL_AXIDMA_CH1_MIN_PG_MSK 0x1fff + +#define R_PL_AXIDMA_CH3_PAGE_CTRL 0x0714 +#define B_PL_AXIDMA_CH3_GRP BIT(31) +#define B_PL_AXIDMA_CH3_MAX_PG_SH 16 +#define B_PL_AXIDMA_CH3_MAX_PG_MSK 0x1fff +#define B_PL_AXIDMA_CH3_MIN_PG_SH 0 +#define B_PL_AXIDMA_CH3_MIN_PG_MSK 0x1fff + +#define R_PL_AXIDMA_CH1_PAGE_INFO 0x0720 +#define B_PL_AXIDMA_CH1_AVAIL_PG_SH 16 +#define B_PL_AXIDMA_CH1_AVAIL_PG_MSK 0x1fff +#define B_PL_AXIDMA_CH1_USE_PG_SH 0 +#define B_PL_AXIDMA_CH1_USE_PG_MSK 0x1fff + +#define R_PL_AXIDMA_CH3_PAGE_INFO 0x0724 +#define B_PL_AXIDMA_CH3_AVAIL_PG_SH 16 +#define B_PL_AXIDMA_CH3_AVAIL_PG_MSK 0x1fff +#define B_PL_AXIDMA_CH3_USE_PG_SH 0 +#define B_PL_AXIDMA_CH3_USE_PG_MSK 0x1fff + +#define R_PL_AXIDMA_SET0_PUB_PAGE_INFO 0x0730 +#define B_PL_AXIDMA_SET0_AVAL_PUBPG_SH 0 +#define B_PL_AXIDMA_SET0_AVAL_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_SET1_PUB_PAGE_CTRL1 0x0740 +#define B_PL_AXIDMA_SET1_G1_MAX_PUBPG_SH 16 +#define B_PL_AXIDMA_SET1_G1_MAX_PUBPG_MSK 0x1fff +#define B_PL_AXIDMA_SET1_G0_MAX_PUBPG_SH 0 +#define B_PL_AXIDMA_SET1_G0_MAX_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_SET1_PUB_PAGE_CTRL2 0x0744 +#define B_PL_AXIDMA_SET1_ALL_MAX_PUBPG_SH 0 +#define B_PL_AXIDMA_SET1_ALL_MAX_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO1 0x0748 +#define B_PL_AXIDMA_SET1_G1_USE_PUBPG_SH 16 +#define B_PL_AXIDMA_SET1_G1_USE_PUBPG_MSK 0x1fff +#define B_PL_AXIDMA_SET1_G0_USE_PUBPG_SH 0 +#define B_PL_AXIDMA_SET1_G0_USE_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO2 0x074C +#define B_PL_AXIDMA_SET1_AVAL_PUBPG_SH 0 +#define B_PL_AXIDMA_SET1_AVAL_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO3 0x0750 +#define B_PL_AXIDMA_SET1_G1_AVAL_PUBPG_SH 16 +#define B_PL_AXIDMA_SET1_G1_AVAL_PUBPG_MSK 0x1fff +#define B_PL_AXIDMA_SET1_G0_AVAL_PUBPG_SH 0 +#define B_PL_AXIDMA_SET1_G0_AVAL_PUBPG_MSK 0x1fff + +#define R_PL_AXIDMA_WP_PAGE_CTRL1 0x0760 +#define B_PL_AXIDMA_PREC_PAGE_WP_SH 16 +#define B_PL_AXIDMA_PREC_PAGE_WP_MSK 0x1ff + +#define R_PL_AXIDMA_WP_PAGE_CTRL2 0x0764 +#define B_PL_AXIDMA_WP_THRD_SH 0 +#define B_PL_AXIDMA_WP_THRD_MSK 0x1fff + +#define R_PL_AXIDMA_WP_PAGE_INFO 0x0768 +#define B_PL_AXIDMA_WP_AVAL_PG_SH 16 +#define B_PL_AXIDMA_WP_AVAL_PG_MSK 0x1fff + +#define R_PL_AXIDMA_FC_ERR_FLAG 0x0770 +#define B_PL_AXIDMA_SET1_PUB_USE_PG_OFW BIT(24) +#define B_PL_AXIDMA_SET1_PUB_USE_PG_UFW BIT(23) +#define B_PL_AXIDMA_SET1_USE_PG_OFW BIT(22) +#define B_PL_AXIDMA_SET1_USE_PG_UFW BIT(21) +#define B_PL_AXIDMA_SET1_AVAL_PG_OFW BIT(20) +#define B_PL_AXIDMA_SET1_AVAL_PG_UFW BIT(19) +#define B_PL_AXIDMA_SET1_WP_REQ_PG_ERR BIT(18) +#define B_PL_AXIDMA_SET1_REQ_PG_ERR BIT(16) +#define B_PL_AXIDMA_SET0_REQ_PG_ERR BIT(0) + +#define R_PL_AXIDMA_FWIMR0 0x0900 +#define B_PL_AXIDMA_CH5_RX_RDU_MSK BIT(21) +#define B_PL_AXIDMA_CH4_RX_RDU_MSK BIT(20) +#define B_PL_AXIDMA_CH3_RX_RDU_MSK BIT(19) +#define B_PL_AXIDMA_CH2_RX_RDU_MSK BIT(18) +#define B_PL_AXIDMA_CH1_RX_RDU_MSK BIT(17) +#define B_PL_AXIDMA_CH0_RX_RDU_MSK BIT(16) +#define B_PL_AXIDMA_CH5_RX_DERR_MSK BIT(13) +#define B_PL_AXIDMA_CH4_RX_DERR_MSK BIT(12) +#define B_PL_AXIDMA_CH3_RX_DERR_MSK BIT(11) +#define B_PL_AXIDMA_CH2_RX_DERR_MSK BIT(10) +#define B_PL_AXIDMA_CH1_RX_DERR_MSK BIT(9) +#define B_PL_AXIDMA_CH0_RX_DERR_MSK BIT(8) +#define B_PL_AXIDMA_CH5_RX_DOK_MSK BIT(5) +#define B_PL_AXIDMA_CH4_RX_DOK_MSK BIT(4) +#define B_PL_AXIDMA_CH3_RX_DOK_MSK BIT(3) +#define B_PL_AXIDMA_CH2_RX_DOK_MSK BIT(2) +#define B_PL_AXIDMA_CH1_RX_DOK_MSK BIT(1) +#define B_PL_AXIDMA_CH0_RX_DOK_MSK BIT(0) + +#define R_PL_AXIDMA_FWIMR1 0x0904 +#define B_PL_AXIDMA_CH3_TX_DERR_MSK BIT(11) +#define B_PL_AXIDMA_CH2_TX_DERR_MSK BIT(10) +#define B_PL_AXIDMA_CH1_TX_DERR_MSK BIT(9) +#define B_PL_AXIDMA_CH0_TX_DERR_MSK BIT(8) +#define B_PL_AXIDMA_CH3_TX_DOK_MSK BIT(3) +#define B_PL_AXIDMA_CH2_TX_DOK_MSK BIT(2) +#define B_PL_AXIDMA_CH1_TX_DOK_MSK BIT(1) +#define B_PL_AXIDMA_CH0_TX_DOK_MSK BIT(0) + +#define R_PL_AXIDMA_FWISR0 0x0908 +#define B_PL_AXIDMA_CH5_RX_RDU BIT(21) +#define B_PL_AXIDMA_CH4_RX_RDU BIT(20) +#define B_PL_AXIDMA_CH3_RX_RDU BIT(19) +#define B_PL_AXIDMA_CH2_RX_RDU BIT(18) +#define B_PL_AXIDMA_CH1_RX_RDU BIT(17) +#define B_PL_AXIDMA_CH0_RX_RDU BIT(16) +#define B_PL_AXIDMA_CH5_RX_DERR BIT(13) +#define B_PL_AXIDMA_CH4_RX_DERR BIT(12) +#define B_PL_AXIDMA_CH3_RX_DERR BIT(11) +#define B_PL_AXIDMA_CH2_RX_DERR BIT(10) +#define B_PL_AXIDMA_CH1_RX_DERR BIT(9) +#define B_PL_AXIDMA_CH0_RX_DERR BIT(8) +#define B_PL_AXIDMA_CH5_RX_DOK BIT(5) +#define B_PL_AXIDMA_CH4_RX_DOK BIT(4) +#define B_PL_AXIDMA_CH3_RX_DOK BIT(3) +#define B_PL_AXIDMA_CH2_RX_DOK BIT(2) +#define B_PL_AXIDMA_CH1_RX_DOK BIT(1) +#define B_PL_AXIDMA_CH0_RX_DOK BIT(0) + +#define R_PL_AXIDMA_FWISR1 0x090C +#define B_PL_AXIDMA_CH3_TX_DOK BIT(3) +#define B_PL_AXIDMA_CH2_TX_DOK BIT(2) +#define B_PL_AXIDMA_CH1_TX_DOK BIT(1) +#define B_PL_AXIDMA_CH0_TX_DOK BIT(0) + +// +// WL_AX_Reg_CMAC_0.xls +// + +// +// COMMON +// + +#define R_AX_CMAC_FUNC_EN 0xC000 +#define R_AX_CMAC_FUNC_EN_C1 0xE000 +#define B_AX_CMAC_CRPRT BIT(31) +#define B_AX_CMAC_EN BIT(30) +#define B_AX_CMAC_TXEN BIT(29) +#define B_AX_CMAC_RXEN BIT(28) +#define B_AX_FORCE_CMACREG_GCKEN BIT(15) +#define B_AX_PHYINTF_EN BIT(5) +#define B_AX_CMAC_DMA_EN BIT(4) +#define B_AX_PTCLTOP_EN BIT(3) +#define B_AX_SCHEDULER_EN BIT(2) +#define B_AX_TMAC_EN BIT(1) +#define B_AX_RMAC_EN BIT(0) + +#define R_AX_CK_EN 0xC004 +#define R_AX_CK_EN_C1 0xE004 +#define B_AX_CMAC_CKEN BIT(30) +#define B_AX_PHYINTF_CKEN BIT(5) +#define B_AX_CMAC_DMA_CKEN BIT(4) +#define B_AX_PTCLTOP_CKEN BIT(3) +#define B_AX_SCHEDULER_CKEN BIT(2) +#define B_AX_TMAC_CKEN BIT(1) +#define B_AX_RMAC_CKEN BIT(0) + +#define R_AX_WMAC_RFMOD 0xC010 +#define R_AX_WMAC_RFMOD_C1 0xE010 +#define B_AX_WMAC_RFMOD_SH 0 +#define B_AX_WMAC_RFMOD_MSK 0x3 + +#define R_AX_R_BIST_CTRL 0xC040 +#define R_AX_R_BIST_CTRL_C1 0xE040 +#define B_AX_R_BIST_DYN_READ_EN BIT(14) +#define B_AX_R_BIST_LOOP_MODE BIT(13) +#define B_AX_R_BIST_LVDRF_CLKDIS BIT(12) +#define B_AX_R_BIST_DRF_RESUME BIT(3) +#define B_AX_R_BIST_DRF_MODE BIT(2) +#define B_AX_R_BIST_MODE BIT(1) +#define B_AX_R_BIST_RSTN_ALL BIT(0) + +#define R_AX_SYM_MEM_RM_CTRL 0xC044 +#define R_AX_SYM_MEM_RM_CTRL_C1 0xE044 +#define B_AX_R_SYM_MEM_RMV_FABDBG_SH 30 +#define B_AX_R_SYM_MEM_RMV_FABDBG_MSK 0x3 +#define B_AX_R_SYM_MEM_RMV_SIGN BIT(29) +#define B_AX_R_SYM_MEM_RMV_2PRF BIT(27) +#define B_AX_R_SYM_MEM_RMV_1PRF BIT(26) +#define B_AX_R_SYM_MEM_RMV_1PSR BIT(25) +#define B_AX_R_SYM_MEM_RMV_ROM BIT(24) +#define B_AX_R_SYM_MEM_RME_WL_SH 4 +#define B_AX_R_SYM_MEM_RME_WL_MSK 0xf + +#define R_AX_PARAM_CMAC_BIST_RSTN 0xC050 +#define R_AX_PARAM_CMAC_BIST_RSTN_C1 0xE050 +#define B_AX_R_BIST_RST_N_CMAC_SH 0 +#define B_AX_R_BIST_RST_N_CMAC_MSK 0x1ff + +#define R_AX_PARAM_CMAC_BIST_DONE 0xC054 +#define R_AX_PARAM_CMAC_BIST_DONE_C1 0xE054 +#define B_AX_BIST_DONE_CMAC_SH 0 +#define B_AX_BIST_DONE_CMAC_MSK 0x1ff + +#define R_AX_PARAM_CMAC_BIST_FAIL 0xC058 +#define R_AX_PARAM_CMAC_BIST_FAIL_C1 0xE058 +#define B_AX_BIST_FAIL_CMAC_SH 0 +#define B_AX_BIST_FAIL_CMAC_MSK 0x1ff + +#define R_AX_PARAM_CMAC_DRF_PAUSE 0xC05C +#define R_AX_PARAM_CMAC_DRF_PAUSE_C1 0xE05C +#define B_AX_BIST_DRF_PAUSE_CMAC_SH 0 +#define B_AX_BIST_DRF_PAUSE_CMAC_MSK 0x1ff + +#define R_AX_PARAM_CMAC_BIST_RSTN_SHARE 0xC060 +#define R_AX_PARAM_CMAC_BIST_RSTN_SHARE_C1 0xE060 +#define B_AX_R_BIST_RST_N_CMAC_SHARE_SH 0 +#define B_AX_R_BIST_RST_N_CMAC_SHARE_MSK 0x7 + +#define R_AX_PARAM_CMAC_BIST_DONE_SHARE 0xC064 +#define R_AX_PARAM_CMAC_BIST_DONE_SHARE_C1 0xE064 +#define B_AX_BIST_DONE_CMAC_SHARE_SH 0 +#define B_AX_BIST_DONE_CMAC_SHARE_MSK 0x7 + +#define R_AX_PARAM_CMAC_BIST_FAIL_SHARE 0xC068 +#define R_AX_PARAM_CMAC_BIST_FAIL_SHARE_C1 0xE068 +#define B_AX_BIST_FAIL_CMAC_SHARE_SH 0 +#define B_AX_BIST_FAIL_CMAC_SHARE_MSK 0x7 + +#define R_AX_PARAM_CMAC_DRF_PAUSE_SHARE 0xC06C +#define R_AX_PARAM_CMAC_DRF_PAUSE_SHARE_C1 0xE06C +#define B_AX_BIST_DRF_PAUSE_CMAC_SHARE_SH 0 +#define B_AX_BIST_DRF_PAUSE_CMAC_SHARE_MSK 0x7 + +#define R_AX_GID_POSITION0 0xC070 +#define R_AX_GID_POSITION0_C1 0xE070 +#define B_AX_GID_15_POSITION_SH 30 +#define B_AX_GID_15_POSITION_MSK 0x3 +#define B_AX_GID_14_POSITION_SH 28 +#define B_AX_GID_14_POSITION_MSK 0x3 +#define B_AX_GID_13_POSITION_SH 26 +#define B_AX_GID_13_POSITION_MSK 0x3 +#define B_AX_GID_12_POSITION_SH 24 +#define B_AX_GID_12_POSITION_MSK 0x3 +#define B_AX_GID_11_POSITION_SH 22 +#define B_AX_GID_11_POSITION_MSK 0x3 +#define B_AX_GID_10_POSITION_SH 20 +#define B_AX_GID_10_POSITION_MSK 0x3 +#define B_AX_GID_9_POSITION_SH 18 +#define B_AX_GID_9_POSITION_MSK 0x3 +#define B_AX_GID_8_POSITION_SH 16 +#define B_AX_GID_8_POSITION_MSK 0x3 +#define B_AX_GID_7_POSITION_SH 14 +#define B_AX_GID_7_POSITION_MSK 0x3 +#define B_AX_GID_6_POSITION_SH 12 +#define B_AX_GID_6_POSITION_MSK 0x3 +#define B_AX_GID_5_POSITION_SH 10 +#define B_AX_GID_5_POSITION_MSK 0x3 +#define B_AX_GID_4_POSITION_SH 8 +#define B_AX_GID_4_POSITION_MSK 0x3 +#define B_AX_GID_3_POSITION_SH 6 +#define B_AX_GID_3_POSITION_MSK 0x3 +#define B_AX_GID_2_POSITION_SH 4 +#define B_AX_GID_2_POSITION_MSK 0x3 +#define B_AX_GID_1_POSITION_SH 2 +#define B_AX_GID_1_POSITION_MSK 0x3 +#define B_AX_GID_0_POSITION_SH 0 +#define B_AX_GID_0_POSITION_MSK 0x3 + +#define R_AX_GID_POSITION1 0xC074 +#define R_AX_GID_POSITION1_C1 0xE074 +#define B_AX_GID_31_POSITION_SH 30 +#define B_AX_GID_31_POSITION_MSK 0x3 +#define B_AX_GID_30_POSITION_SH 28 +#define B_AX_GID_30_POSITION_MSK 0x3 +#define B_AX_GID_29_POSITION_SH 26 +#define B_AX_GID_29_POSITION_MSK 0x3 +#define B_AX_GID_28_POSITION_SH 24 +#define B_AX_GID_28_POSITION_MSK 0x3 +#define B_AX_GID_27_POSITION_SH 22 +#define B_AX_GID_27_POSITION_MSK 0x3 +#define B_AX_GID_26_POSITION_SH 20 +#define B_AX_GID_26_POSITION_MSK 0x3 +#define B_AX_GID_25_POSITION_SH 18 +#define B_AX_GID_25_POSITION_MSK 0x3 +#define B_AX_GID_24_POSITION_SH 16 +#define B_AX_GID_24_POSITION_MSK 0x3 +#define B_AX_GID_23_POSITION_SH 14 +#define B_AX_GID_23_POSITION_MSK 0x3 +#define B_AX_GID_22_POSITION_SH 12 +#define B_AX_GID_22_POSITION_MSK 0x3 +#define B_AX_GID_21_POSITION_SH 10 +#define B_AX_GID_21_POSITION_MSK 0x3 +#define B_AX_GID_20_POSITION_SH 8 +#define B_AX_GID_20_POSITION_MSK 0x3 +#define B_AX_GID_19_POSITION_SH 6 +#define B_AX_GID_19_POSITION_MSK 0x3 +#define B_AX_GID_18_POSITION_SH 4 +#define B_AX_GID_18_POSITION_MSK 0x3 +#define B_AX_GID_17_POSITION_SH 2 +#define B_AX_GID_17_POSITION_MSK 0x3 +#define B_AX_GID_16_POSITION_SH 0 +#define B_AX_GID_16_POSITION_MSK 0x3 + +#define R_AX_GID_POSITION2 0xC078 +#define R_AX_GID_POSITION2_C1 0xE078 +#define B_AX_GID_47_POSITION_SH 30 +#define B_AX_GID_47_POSITION_MSK 0x3 +#define B_AX_GID_46_POSITION_SH 28 +#define B_AX_GID_46_POSITION_MSK 0x3 +#define B_AX_GID_45_POSITION_SH 26 +#define B_AX_GID_45_POSITION_MSK 0x3 +#define B_AX_GID_44_POSITION_SH 24 +#define B_AX_GID_44_POSITION_MSK 0x3 +#define B_AX_GID_43_POSITION_SH 22 +#define B_AX_GID_43_POSITION_MSK 0x3 +#define B_AX_GID_42_POSITION_SH 20 +#define B_AX_GID_42_POSITION_MSK 0x3 +#define B_AX_GID_41_POSITION_SH 18 +#define B_AX_GID_41_POSITION_MSK 0x3 +#define B_AX_GID_40_POSITION_SH 16 +#define B_AX_GID_40_POSITION_MSK 0x3 +#define B_AX_GID_39_POSITION_SH 14 +#define B_AX_GID_39_POSITION_MSK 0x3 +#define B_AX_GID_38_POSITION_SH 12 +#define B_AX_GID_38_POSITION_MSK 0x3 +#define B_AX_GID_37_POSITION_SH 10 +#define B_AX_GID_37_POSITION_MSK 0x3 +#define B_AX_GID_36_POSITION_SH 8 +#define B_AX_GID_36_POSITION_MSK 0x3 +#define B_AX_GID_35_POSITION_SH 6 +#define B_AX_GID_35_POSITION_MSK 0x3 +#define B_AX_GID_34_POSITION_SH 4 +#define B_AX_GID_34_POSITION_MSK 0x3 +#define B_AX_GID_33_POSITION_SH 2 +#define B_AX_GID_33_POSITION_MSK 0x3 +#define B_AX_GID_32_POSITION_SH 0 +#define B_AX_GID_32_POSITION_MSK 0x3 + +#define R_AX_GID_POSITION3 0xC07C +#define R_AX_GID_POSITION3_C1 0xE07C +#define B_AX_GID_63_POSITION_SH 30 +#define B_AX_GID_63_POSITION_MSK 0x3 +#define B_AX_GID_62_POSITION_SH 28 +#define B_AX_GID_62_POSITION_MSK 0x3 +#define B_AX_GID_61_POSITION_SH 26 +#define B_AX_GID_61_POSITION_MSK 0x3 +#define B_AX_GID_60_POSITION_SH 24 +#define B_AX_GID_60_POSITION_MSK 0x3 +#define B_AX_GID_59_POSITION_SH 22 +#define B_AX_GID_59_POSITION_MSK 0x3 +#define B_AX_GID_58_POSITION_SH 20 +#define B_AX_GID_58_POSITION_MSK 0x3 +#define B_AX_GID_57_POSITION_SH 18 +#define B_AX_GID_57_POSITION_MSK 0x3 +#define B_AX_GID_56_POSITION_SH 16 +#define B_AX_GID_56_POSITION_MSK 0x3 +#define B_AX_GID_55_POSITION_SH 14 +#define B_AX_GID_55_POSITION_MSK 0x3 +#define B_AX_GID_54_POSITION_SH 12 +#define B_AX_GID_54_POSITION_MSK 0x3 +#define B_AX_GID_53_POSITION_SH 10 +#define B_AX_GID_53_POSITION_MSK 0x3 +#define B_AX_GID_52_POSITION_SH 8 +#define B_AX_GID_52_POSITION_MSK 0x3 +#define B_AX_GID_51_POSITION_SH 6 +#define B_AX_GID_51_POSITION_MSK 0x3 +#define B_AX_GID_50_POSITION_SH 4 +#define B_AX_GID_50_POSITION_MSK 0x3 +#define B_AX_GID_49_POSITION_SH 2 +#define B_AX_GID_49_POSITION_MSK 0x3 +#define B_AX_GID_48_POSITION_SH 0 +#define B_AX_GID_48_POSITION_MSK 0x3 + +#define R_AX_GID_POSITION_EN0 0xC080 +#define R_AX_GID_POSITION_EN0_C1 0xE080 +#define B_AX_GID_31_POSITION_EN BIT(31) +#define B_AX_GID_30_POSITION_EN BIT(30) +#define B_AX_GID_29_POSITION_EN BIT(29) +#define B_AX_GID_28_POSITION_EN BIT(28) +#define B_AX_GID_27_POSITION_EN BIT(27) +#define B_AX_GID_26_POSITION_EN BIT(26) +#define B_AX_GID_25_POSITION_EN BIT(25) +#define B_AX_GID_24_POSITION_EN BIT(24) +#define B_AX_GID_23_POSITION_EN BIT(23) +#define B_AX_GID_22_POSITION_EN BIT(22) +#define B_AX_GID_21_POSITION_EN BIT(21) +#define B_AX_GID_20_POSITION_EN BIT(20) +#define B_AX_GID_19_POSITION_EN BIT(19) +#define B_AX_GID_18_POSITION_EN BIT(18) +#define B_AX_GID_17_POSITION_EN BIT(17) +#define B_AX_GID_16_POSITION_EN BIT(16) +#define B_AX_GID_15_POSITION_EN BIT(15) +#define B_AX_GID_14_POSITION_EN BIT(14) +#define B_AX_GID_13_POSITION_EN BIT(13) +#define B_AX_GID_12_POSITION_EN BIT(12) +#define B_AX_GID_11_POSITION_EN BIT(11) +#define B_AX_GID_10_POSITION_EN BIT(10) +#define B_AX_GID_9_POSITION_EN BIT(9) +#define B_AX_GID_8_POSITION_EN BIT(8) +#define B_AX_GID_7_POSITION_EN BIT(7) +#define B_AX_GID_6_POSITION_EN BIT(6) +#define B_AX_GID_5_POSITION_EN BIT(5) +#define B_AX_GID_4_POSITION_EN BIT(4) +#define B_AX_GID_3_POSITION_EN BIT(3) +#define B_AX_GID_2_POSITION_EN BIT(2) +#define B_AX_GID_1_POSITION_EN BIT(1) +#define B_AX_GID_0_POSITION_EN BIT(0) + +#define R_AX_GID_POSITION_EN1 0xC084 +#define R_AX_GID_POSITION_EN1_C1 0xE084 +#define B_AX_GID_63_POSITION_EN BIT(31) +#define B_AX_GID_62_POSITION_EN BIT(30) +#define B_AX_GID_61_POSITION_EN BIT(29) +#define B_AX_GID_60_POSITION_EN BIT(28) +#define B_AX_GID_59_POSITION_EN BIT(27) +#define B_AX_GID_58_POSITION_EN BIT(26) +#define B_AX_GID_57_POSITION_EN BIT(25) +#define B_AX_GID_56_POSITION_EN BIT(24) +#define B_AX_GID_55_POSITION_EN BIT(23) +#define B_AX_GID_54_POSITION_EN BIT(22) +#define B_AX_GID_53_POSITION_EN BIT(21) +#define B_AX_GID_52_POSITION_EN BIT(20) +#define B_AX_GID_51_POSITION_EN BIT(19) +#define B_AX_GID_50_POSITION_EN BIT(18) +#define B_AX_GID_49_POSITION_EN BIT(17) +#define B_AX_GID_48_POSITION_EN BIT(16) +#define B_AX_GID_47_POSITION_EN BIT(15) +#define B_AX_GID_46_POSITION_EN BIT(14) +#define B_AX_GID_45_POSITION_EN BIT(13) +#define B_AX_GID_44_POSITION_EN BIT(12) +#define B_AX_GID_43_POSITION_EN BIT(11) +#define B_AX_GID_42_POSITION_EN BIT(10) +#define B_AX_GID_41_POSITION_EN BIT(9) +#define B_AX_GID_40_POSITION_EN BIT(8) +#define B_AX_GID_39_POSITION_EN BIT(7) +#define B_AX_GID_38_POSITION_EN BIT(6) +#define B_AX_GID_37_POSITION_EN BIT(5) +#define B_AX_GID_36_POSITION_EN BIT(4) +#define B_AX_GID_35_POSITION_EN BIT(3) +#define B_AX_GID_34_POSITION_EN BIT(2) +#define B_AX_GID_33_POSITION_EN BIT(1) +#define B_AX_GID_32_POSITION_EN BIT(0) + +#define R_AX_TX_SUB_CARRIER_VALUE 0xC088 +#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 +#define B_AX_TXSC_80M_SH 8 +#define B_AX_TXSC_80M_MSK 0xf +#define B_AX_TXSC_40M_SH 4 +#define B_AX_TXSC_40M_MSK 0xf +#define B_AX_TXSC_20M_SH 0 +#define B_AX_TXSC_20M_MSK 0xf + +#define R_AX_RRSR0 0xC08C +#define R_AX_RRSR0_C1 0xE08C +#define B_AX_RRSR_HE_SH 24 +#define B_AX_RRSR_HE_MSK 0xff +#define B_AX_RRSR_VHT_SH 16 +#define B_AX_RRSR_VHT_MSK 0xff +#define B_AX_RRSR_HT_SH 8 +#define B_AX_RRSR_HT_MSK 0xff +#define B_AX_RRSR_OFDM_SH 0 +#define B_AX_RRSR_OFDM_MSK 0xff + +#define R_AX_PTCL_RRSR1 0xC090 +#define R_AX_PTCL_RRSR1_C1 0xE090 +#define B_AX_RRSR_RATE_EN_SH 8 +#define B_AX_RRSR_RATE_EN_MSK 0xf +#define B_AX_RSC_SH 6 +#define B_AX_RSC_MSK 0x3 +#define B_AX_RRSR_CCK_SH 0 +#define B_AX_RRSR_CCK_MSK 0xf + +#define R_AX_FWC00IMR 0xC100 +#define R_AX_FWC00IMR_C1 0xE100 +#define B_AX_FS_SND_RDY_INT_EN BIT(29) +#define B_AX_FS_RP_END_INT_EN BIT(28) +#define B_AX_FS_RXBCN_TO_CNT_INT_EN BIT(27) +#define B_AX_FS_RXBCN_HIT_INT_EN BIT(26) +#define B_AX_FS_RX_MATCH_RTT_INT_EN BIT(25) +#define B_AX_FS_BCNQ_LOCK_INT_EN BIT(24) +#define B_AX_FS_P2P1_CTWEND_INT_EN BIT(23) +#define B_AX_FS_P2P1_TSF32_TOGGLE_INT_EN BIT(22) +#define B_AX_FS_P2P1_RFON_INT_EN BIT(21) +#define B_AX_FS_P2P1_RFOFF_INT_EN BIT(20) +#define B_AX_FS_P2P0_CTWEND_INT_EN BIT(19) +#define B_AX_FS_P2P0_TSF32_TOGGLE_INT_EN BIT(18) +#define B_AX_FS_P2P0_RFON_INT_EN BIT(17) +#define B_AX_FS_P2P0_RFOFF_INT_EN BIT(16) +#define B_AX_FS_MACID_PWRCHANGE3_INT_EN BIT(15) +#define B_AX_FS_MACID_PWRCHANGE2_INT_EN BIT(14) +#define B_AX_FS_MACID_PWRCHANGE1_INT_EN BIT(13) +#define B_AX_FS_MACID_PWRCHANGE0_INT_EN BIT(12) +#define B_AX_FS_RXFTMREQ_INT_EN BIT(11) +#define B_AX_FS_RXFTM_INT_EN BIT(10) +#define B_AX_FS_FTM_PTT_EN BIT(9) +#define B_AX_FS_TXFTM_INT_EN BIT(8) +#define B_AX_FS_SOUND_DONE_INT_EN BIT(7) +#define B_AX_FS_RXDONE_INT_EN BIT(6) +#define B_AX_FS_PSTIMER_5_INT_EN BIT(5) +#define B_AX_FS_PSTIMER_4_INT_EN BIT(4) +#define B_AX_FS_PSTIMER_3_INT_EN BIT(3) +#define B_AX_FS_PSTIMER_2_INT_EN BIT(2) +#define B_AX_FS_PSTIMER_1_INT_EN BIT(1) +#define B_AX_FS_PSTIMER_0_INT_EN BIT(0) + +#define R_AX_FWC00ISR 0xC104 +#define R_AX_FWC00ISR_C1 0xE104 +#define B_AX_FS_SND_RDY_INT BIT(29) +#define B_AX_FS_RP_END_INT BIT(28) +#define B_AX_FS_RXBCN_TO_CNT_INT BIT(27) +#define B_AX_FS_RXBCN_HIT_INT BIT(26) +#define B_AX_FS_RX_MATCH_RTT_INT BIT(25) +#define B_AX_FS_BCNQ_LOCK_INT BIT(24) +#define B_AX_FS_P2P1_CTWEND_INT BIT(23) +#define B_AX_FS_P2P1_TSF32_TOGGLE_INT BIT(22) +#define B_AX_FS_P2P1_RFON_INT BIT(21) +#define B_AX_FS_P2P1_RFOFF_INT BIT(20) +#define B_AX_FS_P2P0_CTWEND_INT BIT(19) +#define B_AX_FS_P2P0_TSF32_TOGGLE_INT BIT(18) +#define B_AX_FS_P2P0_RFON_INT BIT(17) +#define B_AX_FS_P2P0_RFOFF_INT BIT(16) +#define B_AX_FS_MACID_PWRCHANGE3_INT BIT(15) +#define B_AX_FS_MACID_PWRCHANGE2_INT BIT(14) +#define B_AX_FS_MACID_PWRCHANGE1_INT BIT(13) +#define B_AX_FS_MACID_PWRCHANGE0_INT BIT(12) +#define B_AX_FS_RXFTMREQ_INT BIT(11) +#define B_AX_FS_RXFTM_INT BIT(10) +#define B_AX_FS_FTM_PTT_INT BIT(9) +#define B_AX_FS_TXFTM_INT BIT(8) +#define B_AX_FS_SOUND_DONE_INT BIT(7) +#define B_AX_FS_RXDONE_INT BIT(6) +#define B_AX_FS_PSTIMER_5_INT BIT(5) +#define B_AX_FS_PSTIMER_4_INT BIT(4) +#define B_AX_FS_PSTIMER_3_INT BIT(3) +#define B_AX_FS_PSTIMER_2_INT BIT(2) +#define B_AX_FS_PSTIMER_1_INT BIT(1) +#define B_AX_FS_PSTIMER_0_INT BIT(0) + +#define R_AX_FWC01IMR 0xC108 +#define R_AX_FWC01IMR_C1 0xE108 +#define B_AX_FS_P0_RXBCN_NOHIT_INT_EN BIT(22) +#define B_AX_FS_P0_RXMTF1MRR0_INT_EN BIT(21) +#define B_AX_FS_P0_RXMTF0_INT_EN BIT(20) +#define B_AX_FS_P0_RX_UAPSDMD1_INT_EN BIT(19) +#define B_AX_FS_P0_RX_UAPSDMD0_INT_EN BIT(18) +#define B_AX_FS_P0_TRIGGER_PKT_INT_EN BIT(17) +#define B_AX_FS_P0_EOSP_INT_EN BIT(16) +#define B_AX_FS_P0_TXPKTIN_EN BIT(15) +#define B_AX_FS_P0_TX_NULL1_INT_EN BIT(14) +#define B_AX_FS_P0_TX_NULL0_INT_EN BIT(13) +#define B_AX_FS_P0_RX_UMD0_INT_EN BIT(12) +#define B_AX_FS_P0_RX_UMD1_INT_EN BIT(11) +#define B_AX_FS_P0_RX_BMD0_INT_EN BIT(10) +#define B_AX_FS_P0_RX_BMD1_INT_EN BIT(9) +#define B_AX_FS_P0_RXBCNOK_INT_EN BIT(8) +#define B_AX_FS_P0MB0_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P0MB0_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P0MB0_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P0MB0_TBTT_INT_EN BIT(2) +#define B_AX_FS_P0MB0_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P0MB0_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC01ISR 0xC10C +#define R_AX_FWC01ISR_C1 0xE10C +#define B_AX_FS_P0_RXBCN_NOHIT_INT BIT(22) +#define B_AX_FS_P0_RXMTF1MRR0_INT BIT(21) +#define B_AX_FS_P0_RXMTF0_INT BIT(20) +#define B_AX_FS_P0_RX_UAPSDMD1_INT BIT(19) +#define B_AX_FS_P0_RX_UAPSDMD0_INT BIT(18) +#define B_AX_FS_P0_TRIGGER_PKT_INT BIT(17) +#define B_AX_FS_P0_EOSP_INT BIT(16) +#define B_AX_FS_P0_TXPKTIN_INT BIT(15) +#define B_AX_FS_P0_TX_NULL1_INT BIT(14) +#define B_AX_FS_P0_TX_NULL0_INT BIT(13) +#define B_AX_FS_P0_RX_UMD0_INT BIT(12) +#define B_AX_FS_P0_RX_UMD1_INT BIT(11) +#define B_AX_FS_P0_RX_BMD0_INT BIT(10) +#define B_AX_FS_P0_RX_BMD1_INT BIT(9) +#define B_AX_FS_P0_RXBCNOK_INT BIT(8) +#define B_AX_FS_P0MB0_TXBCNERR_INT BIT(5) +#define B_AX_FS_P0MB0_TXBCNOK_INT BIT(4) +#define B_AX_FS_P0MB0_HIQWND_INT BIT(3) +#define B_AX_FS_P0MB0_TBTT_INT BIT(2) +#define B_AX_FS_P0MB0_TBTTERLY_INT BIT(1) +#define B_AX_FS_P0MB0_BCNERLY_INT BIT(0) + +#define R_AX_FWC02IMR 0xC110 +#define R_AX_FWC02IMR_C1 0xE110 +#define B_AX_FS_P1_RXBCN_NOHIT_INT_EN BIT(22) +#define B_AX_FS_P1_RXMTF1MRR0_INT_EN BIT(21) +#define B_AX_FS_P1_RXMTF0_INT_EN BIT(20) +#define B_AX_FS_P1_RX_UAPSDMD1_INT_EN BIT(19) +#define B_AX_FS_P1_RX_UAPSDMD0_INT_EN BIT(18) +#define B_AX_FS_P1_TRIGGER_PKT_INT_EN BIT(17) +#define B_AX_FS_P1_EOSP_INT_EN BIT(16) +#define B_AX_FS_P1_TXPKTIN_INT_EN BIT(15) +#define B_AX_FS_P1_TX_NULL1_INT_EN BIT(14) +#define B_AX_FS_P1_TX_NULL0_INT_EN BIT(13) +#define B_AX_FS_P1_RX_UMD0_INT_EN BIT(12) +#define B_AX_FS_P1_RX_UMD1_INT_EN BIT(11) +#define B_AX_FS_P1_RX_BMD0_INT_EN BIT(10) +#define B_AX_FS_P1_RX_BMD1_INT_EN BIT(9) +#define B_AX_FS_P1_RXBCNOK_INT_EN BIT(8) +#define B_AX_FS_P1_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P1_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P1_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P1_TBTT_INT_EN BIT(2) +#define B_AX_FS_P1_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P1_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC02ISR 0xC114 +#define R_AX_FWC02ISR_C1 0xE114 +#define B_AX_FS_P1_RXBCN_NOHIT_INT BIT(22) +#define B_AX_FS_P1_RXMTF1MRR0_INT BIT(21) +#define B_AX_FS_P1_RXMTF0_INT BIT(20) +#define B_AX_FS_P1_RX_UAPSDMD1_INT BIT(19) +#define B_AX_FS_P1_RX_UAPSDMD0_INT BIT(18) +#define B_AX_FS_P1_TRIGGER_PKT_INT BIT(17) +#define B_AX_FS_P1_EOSP_INT BIT(16) +#define B_AX_FS_P1_TXPKTIN_INT BIT(15) +#define B_AX_FS_P1_TX_NULL1_INT BIT(14) +#define B_AX_FS_P1_TX_NULL0_INT BIT(13) +#define B_AX_FS_P1_RX_UMD0_INT BIT(12) +#define B_AX_FS_P1_RX_UMD1_INT BIT(11) +#define B_AX_FS_P1_RX_BMD0_INT BIT(10) +#define B_AX_FS_P1_RX_BMD1_INT BIT(9) +#define B_AX_FS_P1_RXBCNOK_INT BIT(8) +#define B_AX_FS_P1_TXBCNERR_INT BIT(5) +#define B_AX_FS_P1_TXBCNOK_INT BIT(4) +#define B_AX_FS_P1_HIQWND_INT BIT(3) +#define B_AX_FS_P1_TBTT_INT BIT(2) +#define B_AX_FS_P1_TBTTERLY_INT BIT(1) +#define B_AX_FS_P1_BCNERLY_INT BIT(0) + +#define R_AX_FWC03IMR 0xC118 +#define R_AX_FWC03IMR_C1 0xE118 +#define B_AX_FS_P2_RXBCN_NOHIT_INT_EN BIT(22) +#define B_AX_FS_P2_RXMTF1MRR0_INT_EN BIT(21) +#define B_AX_FS_P2_RXMTF0_INT_EN BIT(20) +#define B_AX_FS_P2_RX_UAPSDMD1_INT_EN BIT(19) +#define B_AX_FS_P2_RX_UAPSDMD0_INT_EN BIT(18) +#define B_AX_FS_P2_TRIGGER_PKT_INT_EN BIT(17) +#define B_AX_FS_P2_EOSP_INT_EN BIT(16) +#define B_AX_FS_P2_TXPKTIN_INT_EN BIT(15) +#define B_AX_FS_P2_TX_NULL1_INT_EN BIT(14) +#define B_AX_FS_P2_TX_NULL0_INT_EN BIT(13) +#define B_AX_FS_P2_RX_UMD0_INT_EN BIT(12) +#define B_AX_FS_P2_RX_UMD1_INT_EN BIT(11) +#define B_AX_FS_P2_RX_BMD0_INT_EN BIT(10) +#define B_AX_FS_P2_RX_BMD1_INT_EN BIT(9) +#define B_AX_FS_P2_RXBCNOK_INT_EN BIT(8) +#define B_AX_FS_P2_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P2_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P2_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P2_TBTT_INT_EN BIT(2) +#define B_AX_FS_P2_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P2_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC03ISR 0xC11C +#define R_AX_FWC03ISR_C1 0xE11C +#define B_AX_FS_P2_RXBCN_NOHIT_INT BIT(22) +#define B_AX_FS_P2_RXMTF1MRR0_INT BIT(21) +#define B_AX_FS_P2_RXMTF0_INT BIT(20) +#define B_AX_FS_P2_RX_UAPSDMD1_INT BIT(19) +#define B_AX_FS_P2_RX_UAPSDMD0_INT BIT(18) +#define B_AX_FS_P2_TRIGGER_PKT_INT BIT(17) +#define B_AX_FS_P2_EOSP_INT BIT(16) +#define B_AX_FS_P2_TXPKTIN_INT BIT(15) +#define B_AX_FS_P2_TX_NULL1_INT BIT(14) +#define B_AX_FS_P2_TX_NULL0_INT BIT(13) +#define B_AX_FS_P2_RX_UMD0_INT BIT(12) +#define B_AX_FS_P2_RX_UMD1_INT BIT(11) +#define B_AX_FS_P2_RX_BMD0_INT BIT(10) +#define B_AX_FS_P2_RX_BMD1_INT BIT(9) +#define B_AX_FS_P2_RXBCNOK_INT BIT(8) +#define B_AX_FS_P2_TXBCNERR_INT BIT(5) +#define B_AX_FS_P2_TXBCNOK_INT BIT(4) +#define B_AX_FS_P2_HIQWND_INT BIT(3) +#define B_AX_FS_P2_TBTT_INT BIT(2) +#define B_AX_FS_P2_TBTTERLY_INT BIT(1) +#define B_AX_FS_P2_BCNERLY_INT BIT(0) + +#define R_AX_FWC04IMR 0xC120 +#define R_AX_FWC04IMR_C1 0xE120 +#define B_AX_FS_P3_RXBCN_NOHIT_INT_EN BIT(22) +#define B_AX_FS_P3_RXMTF1MRR0_INT_EN BIT(21) +#define B_AX_FS_P3_RXMTF0_INT_EN BIT(20) +#define B_AX_FS_P3_RX_UAPSDMD1_INT_EN BIT(19) +#define B_AX_FS_P3_RX_UAPSDMD0_INT_EN BIT(18) +#define B_AX_FS_P3_TRIGGER_PKT_INT_EN BIT(17) +#define B_AX_FS_P3_EOSP_INT_EN BIT(16) +#define B_AX_FS_P3_TXPKTIN_INT_EN BIT(15) +#define B_AX_FS_P3_TX_NULL1_INT_EN BIT(14) +#define B_AX_FS_P3_TX_NULL0_INT_EN BIT(13) +#define B_AX_FS_P3_RX_UMD0_INT_EN BIT(12) +#define B_AX_FS_P3_RX_UMD1_INT_EN BIT(11) +#define B_AX_FS_P3_RX_BMD0_INT_EN BIT(10) +#define B_AX_FS_P3_RX_BMD1_INT_EN BIT(9) +#define B_AX_FS_P3_RXBCNOK_INT_EN BIT(8) +#define B_AX_FS_P3_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P3_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P3_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P3_TBTT_INT_EN BIT(2) +#define B_AX_FS_P3_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P3_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC04ISR 0xC124 +#define R_AX_FWC04ISR_C1 0xE124 +#define B_AX_FS_P3_RXBCN_NOHIT_INT BIT(22) +#define B_AX_FS_P3_RXMTF1MRR0_INT BIT(21) +#define B_AX_FS_P3_RXMTF0_INT BIT(20) +#define B_AX_FS_P3_RX_UAPSDMD1_INT BIT(19) +#define B_AX_FS_P3_RX_UAPSDMD0_INT BIT(18) +#define B_AX_FS_P3_TRIGGER_PKT_INT BIT(17) +#define B_AX_FS_P3_EOSP_INT BIT(16) +#define B_AX_FS_P3_TXPKTIN_INT BIT(15) +#define B_AX_FS_P3_TX_NULL1_INT BIT(14) +#define B_AX_FS_P3_TX_NULL0_INT BIT(13) +#define B_AX_FS_P3_RX_UMD0_INT BIT(12) +#define B_AX_FS_P3_RX_UMD1_INT BIT(11) +#define B_AX_FS_P3_RX_BMD0_INT BIT(10) +#define B_AX_FS_P3_RX_BMD1_INT BIT(9) +#define B_AX_FS_P3_RXBCNOK_INT BIT(8) +#define B_AX_FS_P3_TXBCNERR_INT BIT(5) +#define B_AX_FS_P3_TXBCNOK_INT BIT(4) +#define B_AX_FS_P3_HIQWND_INT BIT(3) +#define B_AX_FS_P3_TBTT_INT BIT(2) +#define B_AX_FS_P3_TBTTERLY_INT BIT(1) +#define B_AX_FS_P3_BCNERLY_INT BIT(0) + +#define R_AX_FWC05IMR 0xC128 +#define R_AX_FWC05IMR_C1 0xE128 +#define B_AX_FS_P4_RXBCN_NOHIT_INT_EN BIT(22) +#define B_AX_FS_P4_RXMTF1MRR0_INT_EN BIT(21) +#define B_AX_FS_P4_RXMTF0_INT_EN BIT(20) +#define B_AX_FS_P4_RX_UAPSDMD1_INT_EN BIT(19) +#define B_AX_FS_P4_RX_UAPSDMD0_INT_EN BIT(18) +#define B_AX_FS_P4_TRIGGER_PKT_INT_EN BIT(17) +#define B_AX_FS_P4_EOSP_INT_EN BIT(16) +#define B_AX_FS_P4_TXPKTIN_INT_EN BIT(15) +#define B_AX_FS_P4_TX_NULL1_INT_EN BIT(14) +#define B_AX_FS_P4_TX_NULL0_INT_EN BIT(13) +#define B_AX_FS_P4_RX_UMD0_INT_EN BIT(12) +#define B_AX_FS_P4_RX_UMD1_INT_EN BIT(11) +#define B_AX_FS_P4_RX_BMD0_INT_EN BIT(10) +#define B_AX_FS_P4_RX_BMD1_INT_EN BIT(9) +#define B_AX_FS_P4_RXBCNOK_INT_EN BIT(8) +#define B_AX_FS_P4_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P4_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P4_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P4_TBTT_INT_EN BIT(2) +#define B_AX_FS_P4_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P4_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC05ISR 0xC12C +#define R_AX_FWC05ISR_C1 0xE12C +#define B_AX_FS_P4_RXBCN_NOHIT_INT BIT(22) +#define B_AX_FS_P4_RXMTF1MRR0_INT BIT(21) +#define B_AX_FS_P4_RXMTF0_INT BIT(20) +#define B_AX_FS_P4_RX_UAPSDMD1_INT BIT(19) +#define B_AX_FS_P4_RX_UAPSDMD0_INT BIT(18) +#define B_AX_FS_P4_TRIGGER_PKT_INT BIT(17) +#define B_AX_FS_P4_EOSP_INT BIT(16) +#define B_AX_FS_P4_TXPKTIN_INT BIT(15) +#define B_AX_FS_P4_TX_NULL1_INT BIT(14) +#define B_AX_FS_P4_TX_NULL0_INT BIT(13) +#define B_AX_FS_P4_RX_UMD0_INT BIT(12) +#define B_AX_FS_P4_RX_UMD1_INT BIT(11) +#define B_AX_FS_P4_RX_BMD0_INT BIT(10) +#define B_AX_FS_P4_RX_BMD1_INT BIT(9) +#define B_AX_FS_P4_RXBCNOK_INT BIT(8) +#define B_AX_FS_P4_TXBCNERR_INT BIT(5) +#define B_AX_FS_P4_TXBCNOK_INT BIT(4) +#define B_AX_FS_P4_HIQWND_INT BIT(3) +#define B_AX_FS_P4_TBTT_INT BIT(2) +#define B_AX_FS_P4_TBTTERLY_INT BIT(1) +#define B_AX_FS_P4_BCNERLY_INT BIT(0) + +#define R_AX_FWC06IMR 0xC130 +#define R_AX_FWC06IMR_C1 0xE130 +#define B_AX_FS_P0MB4_TXBCNERR_INT_EN BIT(29) +#define B_AX_FS_P0MB4_TXBCNOK_INT_EN BIT(28) +#define B_AX_FS_P0MB4_HIQWND_INT_EN BIT(27) +#define B_AX_FS_P0MB4_TBTT_INT_EN BIT(26) +#define B_AX_FS_P0MB4_TBTTERLY_INT_EN BIT(25) +#define B_AX_FS_P0MB4_BCNERLY_INT_EN BIT(24) +#define B_AX_FS_P0MB3_TXBCNERR_INT_EN BIT(21) +#define B_AX_FS_P0MB3_TXBCNOK_INT_EN BIT(20) +#define B_AX_FS_P0MB3_HIQWND_INT_EN BIT(19) +#define B_AX_FS_P0MB3_TBTT_INT_EN BIT(18) +#define B_AX_FS_P0MB3_TBTTERLY_INT_EN BIT(17) +#define B_AX_FS_P0MB3_BCNERLY_INT_EN BIT(16) +#define B_AX_FS_P0MB2_TXBCNERR_INT_EN BIT(13) +#define B_AX_FS_P0MB2_TXBCNOK_INT_EN BIT(12) +#define B_AX_FS_P0MB2_HIQWND_INT_EN BIT(11) +#define B_AX_FS_P0MB2_TBTT_INT_EN BIT(10) +#define B_AX_FS_P0MB2_TBTTERLY_INT_EN BIT(9) +#define B_AX_FS_P0MB2_BCNERLY_INT_EN BIT(8) +#define B_AX_FS_P0MB1_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P0MB1_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P0MB1_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P0MB1_TBTT_INT_EN BIT(2) +#define B_AX_FS_P0MB1_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P0MB1_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC06ISR 0xC134 +#define R_AX_FWC06ISR_C1 0xE134 +#define B_AX_FS_P0MB4_TXBCNERR_INT BIT(29) +#define B_AX_FS_P0MB4_TXBCNOK_INT BIT(28) +#define B_AX_FS_P0MB4_HIQWND_INT BIT(27) +#define B_AX_FS_P0MB4_TBTT_INT BIT(26) +#define B_AX_FS_P0MB4_TBTTERLY_INT BIT(25) +#define B_AX_FS_P0MB4_BCNERLY_INT BIT(24) +#define B_AX_FS_P0MB3_TXBCNERR_INT BIT(21) +#define B_AX_FS_P0MB3_TXBCNOK_INT BIT(20) +#define B_AX_FS_P0MB3_HIQWND_INT BIT(19) +#define B_AX_FS_P0MB3_TBTT_INT BIT(18) +#define B_AX_FS_P0MB3_TBTTERLY_INT BIT(17) +#define B_AX_FS_P0MB3_BCNERLY_INT BIT(16) +#define B_AX_FS_P0MB2_TXBCNERR_INT BIT(13) +#define B_AX_FS_P0MB2_TXBCNOK_INT BIT(12) +#define B_AX_FS_P0MB2_HIQWND_INT BIT(11) +#define B_AX_FS_P0MB2_TBTT_INT BIT(10) +#define B_AX_FS_P0MB2_TBTTERLY_INT BIT(9) +#define B_AX_FS_P0MB2_BCNERLY_INT BIT(8) +#define B_AX_FS_P0MB1_TXBCNERR_INT BIT(5) +#define B_AX_FS_P0MB1_TXBCNOK_INT BIT(4) +#define B_AX_FS_P0MB1_HIQWND_INT BIT(3) +#define B_AX_FS_P0MB1_TBTT_INT BIT(2) +#define B_AX_FS_P0MB1_TBTTERLY_INT BIT(1) +#define B_AX_FS_P0MB1_BCNERLY_INT BIT(0) + +#define R_AX_FWC07IMR 0xC138 +#define R_AX_FWC07IMR_C1 0xE138 +#define B_AX_FS_P0MB8_TXBCNERR_INT_EN BIT(29) +#define B_AX_FS_P0MB8_TXBCNOK_INT_EN BIT(28) +#define B_AX_FS_P0MB8_HIQWND_INT_EN BIT(27) +#define B_AX_FS_P0MB8_TBTT_INT_EN BIT(26) +#define B_AX_FS_P0MB8_TBTTERLY_INT_EN BIT(25) +#define B_AX_FS_P0MB8_BCNERLY_INT_EN BIT(24) +#define B_AX_FS_P0MB7_TXBCNERR_INT_EN BIT(21) +#define B_AX_FS_P0MB7_TXBCNOK_INT_EN BIT(20) +#define B_AX_FS_P0MB7_HIQWND_INT_EN BIT(19) +#define B_AX_FS_P0MB7_TBTT_INT_EN BIT(18) +#define B_AX_FS_P0MB7_TBTTERLY_INT_EN BIT(17) +#define B_AX_FS_P0MB7_BCNERLY_INT_EN BIT(16) +#define B_AX_FS_P0MB6_TXBCNERR_INT_EN BIT(13) +#define B_AX_FS_P0MB6_TXBCNOK_INT_EN BIT(12) +#define B_AX_FS_P0MB6_HIQWND_INT_EN BIT(11) +#define B_AX_FS_P0MB6_TBTT_INT_EN BIT(10) +#define B_AX_FS_P0MB6_TBTTERLY_INT_EN BIT(9) +#define B_AX_FS_P0MB6_BCNERLY_INT_EN BIT(8) +#define B_AX_FS_P0MB5_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P0MB5_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P0MB5_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P0MB5_TBTT_INT_EN BIT(2) +#define B_AX_FS_P0MB5_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P0MB5_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC07ISR 0xC13C +#define R_AX_FWC07ISR_C1 0xE13C +#define B_AX_FS_P0MB8_TXBCNERR_INT BIT(29) +#define B_AX_FS_P0MB8_TXBCNOK_INT BIT(28) +#define B_AX_FS_P0MB8_HIQWND_INT BIT(27) +#define B_AX_FS_P0MB8_TBTT_INT BIT(26) +#define B_AX_FS_P0MB8_TBTTERLY_INT BIT(25) +#define B_AX_FS_P0MB8_BCNERLY_INT BIT(24) +#define B_AX_FS_P0MB7_TXBCNERR_INT BIT(21) +#define B_AX_FS_P0MB7_TXBCNOK_INT BIT(20) +#define B_AX_FS_P0MB7_HIQWND_INT BIT(19) +#define B_AX_FS_P0MB7_TBTT_INT BIT(18) +#define B_AX_FS_P0MB7_TBTTERLY_INT BIT(17) +#define B_AX_FS_P0MB7_BCNERLY_INT BIT(16) +#define B_AX_FS_P0MB6_TXBCNERR_INT BIT(13) +#define B_AX_FS_P0MB6_TXBCNOK_INT BIT(12) +#define B_AX_FS_P0MB6_HIQWND_INT BIT(11) +#define B_AX_FS_P0MB6_TBTT_INT BIT(10) +#define B_AX_FS_P0MB6_TBTTERLY_INT BIT(9) +#define B_AX_FS_P0MB6_BCNERLY_INT BIT(8) +#define B_AX_FS_P0MB5_TXBCNERR_INT BIT(5) +#define B_AX_FS_P0MB5_TXBCNOK_INT BIT(4) +#define B_AX_FS_P0MB5_HIQWND_INT BIT(3) +#define B_AX_FS_P0MB5_TBTT_INT BIT(2) +#define B_AX_FS_P0MB5_TBTTERLY_INT BIT(1) +#define B_AX_FS_P0MB5_BCNERLY_INT BIT(0) + +#define R_AX_FWC08IMR 0xC140 +#define R_AX_FWC08IMR_C1 0xE140 +#define B_AX_FS_P0MB12_TXBCNERR_INT_EN BIT(29) +#define B_AX_FS_P0MB12_TXBCNOK_INT_EN BIT(28) +#define B_AX_FS_P0MB12_HIQWND_INT_EN BIT(27) +#define B_AX_FS_P0MB12_TBTT_INT_EN BIT(26) +#define B_AX_FS_P0MB12_TBTTERLY_INT_EN BIT(25) +#define B_AX_FS_P0MB12_BCNERLY_INT_EN BIT(24) +#define B_AX_FS_P0MB11_TXBCNERR_INT_EN BIT(21) +#define B_AX_FS_P0MB11_TXBCNOK_INT_EN BIT(20) +#define B_AX_FS_P0MB11_HIQWND_INT_EN BIT(19) +#define B_AX_FS_P0MB11_TBTT_INT_EN BIT(18) +#define B_AX_FS_P0MB11_TBTTERLY_INT_EN BIT(17) +#define B_AX_FS_P0MB11_BCNERLY_INT_EN BIT(16) +#define B_AX_FS_P0MB10_TXBCNERR_INT_EN BIT(13) +#define B_AX_FS_P0MB10_TXBCNOK_INT_EN BIT(12) +#define B_AX_FS_P0MB10_HIQWND_INT_EN BIT(11) +#define B_AX_FS_P0MB10_TBTT_INT_EN BIT(10) +#define B_AX_FS_P0MB10_TBTTERLY_INT_EN BIT(9) +#define B_AX_FS_P0MB10_BCNERLY_INT_EN BIT(8) +#define B_AX_FS_P0MB9_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P0MB9_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P0MB9_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P0MB9_TBTT_INT_EN BIT(2) +#define B_AX_FS_P0MB9_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P0MB9_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC08ISR 0xC144 +#define R_AX_FWC08ISR_C1 0xE144 +#define B_AX_FS_P0MB12_TXBCNERR_INT BIT(29) +#define B_AX_FS_P0MB12_TXBCNOK_INT BIT(28) +#define B_AX_FS_P0MB12_HIQWND_INT BIT(27) +#define B_AX_FS_P0MB12_TBTT_INT BIT(26) +#define B_AX_FS_P0MB12_TBTTERLY_INT BIT(25) +#define B_AX_FS_P0MB12_BCNERLY_INT BIT(24) +#define B_AX_FS_P0MB11_TXBCNERR_INT BIT(21) +#define B_AX_FS_P0MB11_TXBCNOK_INT BIT(20) +#define B_AX_FS_P0MB11_HIQWND_INT BIT(19) +#define B_AX_FS_P0MB11_TBTT_INT BIT(18) +#define B_AX_FS_P0MB11_TBTTERLY_INT BIT(17) +#define B_AX_FS_P0MB11_BCNERLY_INT BIT(16) +#define B_AX_FS_P0MB10_TXBCNERR_INT BIT(13) +#define B_AX_FS_P0MB10_TXBCNOK_INT BIT(12) +#define B_AX_FS_P0MB10_HIQWND_INT BIT(11) +#define B_AX_FS_P0MB10_TBTT_INT BIT(10) +#define B_AX_FS_P0MB10_TBTTERLY_INT BIT(9) +#define B_AX_FS_P0MB10_BCNERLY_INT BIT(8) +#define B_AX_FS_P0MB9_TXBCNERR_INT BIT(5) +#define B_AX_FS_P0MB9_TXBCNOK_INT BIT(4) +#define B_AX_FS_P0MB9_HIQWND_INT BIT(3) +#define B_AX_FS_P0MB9_TBTT_INT BIT(2) +#define B_AX_FS_P0MB9_TBTTERLY_INT BIT(1) +#define B_AX_FS_P0MB9_BCNERLY_INT BIT(0) + +#define R_AX_FWC09IMR 0xC148 +#define R_AX_FWC09IMR_C1 0xE148 +#define B_AX_FS_P0MB15_TXBCNERR_INT_EN BIT(21) +#define B_AX_FS_P0MB15_TXBCNOK_INT_EN BIT(20) +#define B_AX_FS_P0MB15_HIQWND_INT_EN BIT(19) +#define B_AX_FS_P0MB15_TBTT_INT_EN BIT(18) +#define B_AX_FS_P0MB15_TBTTERLY_INT_EN BIT(17) +#define B_AX_FS_P0MB15_BCNERLY_INT_EN BIT(16) +#define B_AX_FS_P0MB14_TXBCNERR_INT_EN BIT(13) +#define B_AX_FS_P0MB14_TXBCNOK_INT_EN BIT(12) +#define B_AX_FS_P0MB14_HIQWND_INT_EN BIT(11) +#define B_AX_FS_P0MB14_TBTT_INT_EN BIT(10) +#define B_AX_FS_P0MB14_TBTTERLY_INT_EN BIT(9) +#define B_AX_FS_P0MB14_BCNERLY_INT_EN BIT(8) +#define B_AX_FS_P0MB13_TXBCNERR_INT_EN BIT(5) +#define B_AX_FS_P0MB13_TXBCNOK_INT_EN BIT(4) +#define B_AX_FS_P0MB13_HIQWND_INT_EN BIT(3) +#define B_AX_FS_P0MB13_TBTT_INT_EN BIT(2) +#define B_AX_FS_P0MB13_TBTTERLY_INT_EN BIT(1) +#define B_AX_FS_P0MB13_BCNERLY_INT_EN BIT(0) + +#define R_AX_FWC09ISR 0xC14C +#define R_AX_FWC09ISR_C1 0xE14C +#define B_AX_FS_P0MB15_TXBCNERR_INT BIT(21) +#define B_AX_FS_P0MB15_TXBCNOK_INT BIT(20) +#define B_AX_FS_P0MB15_HIQWND_INT BIT(19) +#define B_AX_FS_P0MB15_TBTT_INT BIT(18) +#define B_AX_FS_P0MB15_TBTTERLY_INT BIT(17) +#define B_AX_FS_P0MB15_BCNERLY_INT BIT(16) +#define B_AX_FS_P0MB14_TXBCNERR_INT BIT(13) +#define B_AX_FS_P0MB14_TXBCNOK_INT BIT(12) +#define B_AX_FS_P0MB14_HIQWND_INT BIT(11) +#define B_AX_FS_P0MB14_TBTT_INT BIT(10) +#define B_AX_FS_P0MB14_TBTTERLY_INT BIT(9) +#define B_AX_FS_P0MB14_BCNERLY_INT BIT(8) +#define B_AX_FS_P0MB13_TXBCNERR_INT BIT(5) +#define B_AX_FS_P0MB13_TXBCNOK_INT BIT(4) +#define B_AX_FS_P0MB13_HIQWND_INT BIT(3) +#define B_AX_FS_P0MB13_TBTT_INT BIT(2) +#define B_AX_FS_P0MB13_TBTTERLY_INT BIT(1) +#define B_AX_FS_P0MB13_BCNERLY_INT BIT(0) + +#define R_AX_CMAC_ERR_IMR 0xC160 +#define R_AX_CMAC_ERR_IMR_C1 0xE160 +#define B_AX_WMAC_TX_ERR_IND_EN BIT(7) +#define B_AX_WMAC_RX_ERR_IND_EN BIT(6) +#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5) +#define B_AX_PHYINTF_ERR_IND_EN BIT(4) +#define B_AX_DMA_TOP_ERR_IND_EN BIT(3) +#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1) +#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0) + +#define R_AX_CMAC_ERR_ISR 0xC164 +#define R_AX_CMAC_ERR_ISR_C1 0xE164 +#define B_AX_WMAC_TX_ERR_IND BIT(7) +#define B_AX_WMAC_RX_ERR_IND BIT(6) +#define B_AX_TXPWR_CTRL_ERR_IND BIT(5) +#define B_AX_PHYINTF_ERR_IND BIT(4) +#define B_AX_DMA_TOP_ERR_IND BIT(3) +#define B_AX_PTCL_TOP_ERR_IND BIT(1) +#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) + +#define R_AX_HC00IMR 0xC180 +#define R_AX_HC00IMR_C1 0xE180 +#define B_AX_TBTT_B0P4_INT_EN BIT(16) +#define B_AX_TBTT_B0P3_INT_EN BIT(15) +#define B_AX_TBTT_B0P2_INT_EN BIT(14) +#define B_AX_TBTT_B0P1_INT_EN BIT(13) +#define B_AX_TBTT_B0P0_INT_EN BIT(12) +#define B_AX_PKT_INFO_ERR_INT_EN BIT(11) +#define B_AX_BB_STOPRX_INT_EN BIT(10) +#define B_AX_TXERR_INT_EN BIT(9) +#define B_AX_RXERR_INT_EN BIT(8) +#define B_AX_P2P1_TSF32_TOGG_INT_EN BIT(7) +#define B_AX_P2P0_TSF32_TOGG_INT_EN BIT(6) +#define B_AX_PWR_127TO96_INT_EN BIT(5) +#define B_AX_PWR_95TO64_INT_EN BIT(4) +#define B_AX_PWR_63TO32_INT_EN BIT(3) +#define B_AX_PWR_31TO0_INT_EN BIT(2) +#define B_AX_PSTIMER_5_INT_EN BIT(1) +#define B_AX_PSTIMER_4_INT_EN BIT(0) + +#define R_AX_HC00ISR 0xC184 +#define R_AX_HC00ISR_C1 0xE184 +#define B_AX_TBTT_B0P4_INT BIT(16) +#define B_AX_TBTT_B0P3_INT BIT(15) +#define B_AX_TBTT_B0P2_INT BIT(14) +#define B_AX_TBTT_B0P1_INT BIT(13) +#define B_AX_TBTT_B0P0_INT BIT(12) +#define B_AX_PKT_INFO_ERR_INT BIT(11) +#define B_AX_BB_STOPRX_INT BIT(10) +#define B_AX_TXERR_INT BIT(9) +#define B_AX_RXERR_INT BIT(8) +#define B_AX_P2P1_TSF32_TOGG_INT BIT(7) +#define B_AX_P2P0_TSF32_TOGG_INT BIT(6) +#define B_AX_PWR_127TO96_INT BIT(5) +#define B_AX_PWR_95TO64_INT BIT(4) +#define B_AX_PWR_63TO32_INT BIT(3) +#define B_AX_PWR_31TO0_INT BIT(2) +#define B_AX_PSTIMER_5_INT BIT(1) +#define B_AX_PSTIMER_4_INT BIT(0) + +// +// SCH +// + +#define R_AX_PPS0_CTRL 0xC200 +#define R_AX_PPS0_CTRL_C1 0xE200 +#define B_AX_PPS0_PWR_RST1 BIT(31) +#define B_AX_PPS0_PWR_RST0 BIT(30) +#define B_AX_PPS0_CTWIN_SH 16 +#define B_AX_PPS0_CTWIN_MSK 0xfff +#define B_AX_PPS0_TXOP_BRK_EN BIT(15) +#define B_AX_PPS0_AGG_BRK_EN BIT(14) +#define B_AX_PPS0_POF_AND_EN BIT(13) +#define B_AX_PPS0_PSWIND_EN BIT(12) +#define B_AX_PPS0_TSFB32_RST_EN BIT(11) +#define B_AX_PPS0_PORT_SEL_SH 8 +#define B_AX_PPS0_PORT_SEL_MSK 0x7 +#define B_AX_PPS0_ALLSLEEP_EN BIT(7) +#define B_AX_PPS0_OFF_DISTX_EN BIT(6) +#define B_AX_PPS0_CTWIN_EN BIT(5) +#define B_AX_PPS0_BCNAREA_EN BIT(4) +#define B_AX_PPS0_WITHBCNERY BIT(3) +#define B_AX_PPS0_POF1_EN BIT(2) +#define B_AX_PPS0_POF0_EN BIT(1) +#define B_AX_PPS0_PWR_MGT_EN BIT(0) + +#define R_AX_PPS0_SPEC_STATE 0xC204 +#define R_AX_PPS0_SPEC_STATE_C1 0xE204 +#define B_AX_PPS0_SPEC_POW_STATE BIT(7) +#define B_AX_PPS0_SPEC_CTWIN_ON BIT(6) +#define B_AX_PPS0_SPEC_BCNAREA_ON BIT(5) +#define B_AX_PPS0_SPEC_BCNERLY BIT(4) +#define B_AX_PPS0_SPEC_POF1_OFF_PERD BIT(3) +#define B_AX_PPS0_SPEC_FORCE_DOZE1 BIT(2) +#define B_AX_PPS0_SPEC_POF0_OFF_PERD BIT(1) +#define B_AX_PPS0_SPEC_FORCE_DOZE0 BIT(0) + +#define R_AX_PPS0_STATE 0xC205 +#define R_AX_PPS0_STATE_C1 0xE205 +#define B_AX_PPS0_POW_STATE BIT(7) +#define B_AX_PPS0_CTWIN_ON BIT(6) +#define B_AX_PPS0_BCNAREA_ON BIT(5) +#define B_AX_PPS0_BCNERLY BIT(4) +#define B_AX_PPS0_POF1_OFF_PERD BIT(3) +#define B_AX_PPS0_FORCE_DOZE1 BIT(2) +#define B_AX_PPS0_POF0_OFF_PERD BIT(1) +#define B_AX_PPS0_FORCE_DOZE0 BIT(0) + +#define R_AX_PPS0_PAUSE_CTRL0 0xC206 +#define R_AX_PPS0_PAUSE_CTRL0_C1 0xE206 +#define B_AX_PPS0_POF_STOP_TX_HANG BIT(15) +#define B_AX_PPS0_MGQ_PAUSE_EN BIT(11) +#define B_AX_PPS0_HIQ_PAUSE_EN BIT(10) +#define B_AX_PPS0_BCNQ_PAUSE_EN BIT(9) +#define B_AX_PPS0_MACID_PAUSE_EN BIT(8) +#define B_AX_PPS0_PAUSE_MACID_SH 0 +#define B_AX_PPS0_PAUSE_MACID_MSK 0xff + +#define R_AX_PPS0_PAUSE_CTRL1 0xC208 +#define R_AX_PPS0_PAUSE_CTRL1_C1 0xE208 +#define B_AX_PPS0_POWON_DISTX_SH 16 +#define B_AX_PPS0_POWON_DISTX_MSK 0xffff +#define B_AX_PPS0_POWOFF_DISTX_SH 0 +#define B_AX_PPS0_POWOFF_DISTX_MSK 0xffff + +#define R_AX_PPS0_PAUSE_CTRL2 0xC20C +#define R_AX_PPS0_PAUSE_CTRL2_C1 0xE20C +#define B_AX_PPS0_POWOFF_ERLY_SH 16 +#define B_AX_PPS0_POWOFF_ERLY_MSK 0xffff +#define B_AX_PPS0_POWON_ERLY_SH 0 +#define B_AX_PPS0_POWON_ERLY_MSK 0xffff + +#define R_AX_PPS0_POF0_PARAM0 0xC210 +#define R_AX_PPS0_POF0_PARAM0_C1 0xE210 +#define B_AX_PPS0_POF0_DUR_SH 0 +#define B_AX_PPS0_POF0_DUR_MSK 0xffffffffL + +#define R_AX_PPS0_POF0_PARAM1 0xC214 +#define R_AX_PPS0_POF0_PARAM1_C1 0xE214 +#define B_AX_PPS0_POF0_ITVL_SH 0 +#define B_AX_PPS0_POF0_ITVL_MSK 0xffffffffL + +#define R_AX_PPS0_POF0_PARAM2 0xC218 +#define R_AX_PPS0_POF0_PARAM2_C1 0xE218 +#define B_AX_PPS0_POF0_START_SH 0 +#define B_AX_PPS0_POF0_START_MSK 0xffffffffL + +#define R_AX_PPS0_POF0_PARAM3 0xC21C +#define R_AX_PPS0_POF0_PARAM3_C1 0xE21C +#define B_AX_PPS0_POF0_CUR_CNT_SH 8 +#define B_AX_PPS0_POF0_CUR_CNT_MSK 0xff +#define B_AX_PPS0_POF0_CNT_SH 0 +#define B_AX_PPS0_POF0_CNT_MSK 0xff + +#define R_AX_PPS0_POF1_PARAM0 0xC220 +#define R_AX_PPS0_POF1_PARAM0_C1 0xE220 +#define B_AX_PPS0_POF1_DUR_SH 0 +#define B_AX_PPS0_POF1_DUR_MSK 0xffffffffL + +#define R_AX_PPS0_POF1_PARAM1 0xC224 +#define R_AX_PPS0_POF1_PARAM1_C1 0xE224 +#define B_AX_PPS0_POF1_ITVL_SH 0 +#define B_AX_PPS0_POF1_ITVL_MSK 0xffffffffL + +#define R_AX_PPS0_POF1_PARAM2 0xC228 +#define R_AX_PPS0_POF1_PARAM2_C1 0xE228 +#define B_AX_PPS0_POF1_START_SH 0 +#define B_AX_PPS0_POF1_START_MSK 0xffffffffL + +#define R_AX_PPS0_POF1_PARAM3 0xC22C +#define R_AX_PPS0_POF1_PARAM3_C1 0xE22C +#define B_AX_PPS0_POF1_CUR_CNT_SH 8 +#define B_AX_PPS0_POF1_CUR_CNT_MSK 0xff +#define B_AX_PPS0_POF1_CNT_SH 0 +#define B_AX_PPS0_POF1_CNT_MSK 0xff + +#define R_AX_PPS0_CURR_DOZE0 0xC230 +#define R_AX_PPS0_CURR_DOZE0_C1 0xE230 +#define B_AX_PPS0_POF0_CURR_DOZE_SH 0 +#define B_AX_PPS0_POF0_CURR_DOZE_MSK 0xffffffffL + +#define R_AX_PPS0_CURR_DOZE1 0xC234 +#define R_AX_PPS0_CURR_DOZE1_C1 0xE234 +#define B_AX_PPS0_POF1_CURR_DOZE_SH 0 +#define B_AX_PPS0_POF1_CURR_DOZE_MSK 0xffffffffL + +#define R_AX_PPS1_CTRL 0xC240 +#define R_AX_PPS1_CTRL_C1 0xE240 +#define B_AX_PPS1_PWR_RST1 BIT(31) +#define B_AX_PPS1_PWR_RST0 BIT(30) +#define B_AX_PPS1_CTWIN_SH 16 +#define B_AX_PPS1_CTWIN_MSK 0xfff +#define B_AX_PPS1_TXOP_BRK_EN BIT(15) +#define B_AX_PPS1_AGG_BRK_EN BIT(14) +#define B_AX_PPS1_POF_AND_EN BIT(13) +#define B_AX_PPS1_PSWIND_EN BIT(12) +#define B_AX_PPS1_TSFB32_RST_EN BIT(11) +#define B_AX_PPS1_PORT_SEL_SH 8 +#define B_AX_PPS1_PORT_SEL_MSK 0x7 +#define B_AX_PPS1_ALLSLEEP_EN BIT(7) +#define B_AX_PPS1_OFF_DISTX_EN BIT(6) +#define B_AX_PPS1_CTWIN_EN BIT(5) +#define B_AX_PPS1_BCNAREA_EN BIT(4) +#define B_AX_PPS1_WITHBCNERY BIT(3) +#define B_AX_PPS1_POF1_EN BIT(2) +#define B_AX_PPS1_POF0_EN BIT(1) +#define B_AX_PPS1_PWR_MGT_EN BIT(0) + +#define R_AX_PPS1_SPEC_STATE 0xC244 +#define R_AX_PPS1_SPEC_STATE_C1 0xE244 +#define B_AX_PPS1_SPEC_POW_STATE BIT(7) +#define B_AX_PPS1_SPEC_CTWIN_ON BIT(6) +#define B_AX_PPS1_SPEC_BCNAREA_ON BIT(5) +#define B_AX_PPS1_SPEC_BCNERLY BIT(4) +#define B_AX_PPS1_SPEC_POF1_OFF_PERD BIT(3) +#define B_AX_PPS1_SPEC_FORCE_DOZE1 BIT(2) +#define B_AX_PPS1_SPEC_POF0_OFF_PERD BIT(1) +#define B_AX_PPS1_SPEC_FORCE_DOZE0 BIT(0) + +#define R_AX_PPS1_STATE 0xC245 +#define R_AX_PPS1_STATE_C1 0xE245 +#define B_AX_PPS1_POW_STATE BIT(7) +#define B_AX_PPS1_CTWIN_ON BIT(6) +#define B_AX_PPS1_BCNAREA_ON BIT(5) +#define B_AX_PPS1_BCNERLY BIT(4) +#define B_AX_PPS1_POF1_OFF_PERD BIT(3) +#define B_AX_PPS1_FORCE_DOZE1 BIT(2) +#define B_AX_PPS1_POF0_OFF_PERD BIT(1) +#define B_AX_PPS1_FORCE_DOZE0 BIT(0) + +#define R_AX_PPS1_PAUSE_CTRL0 0xC246 +#define R_AX_PPS1_PAUSE_CTRL0_C1 0xE246 +#define B_AX_PPS1_POF_STOP_TX_HANG BIT(15) +#define B_AX_PPS1_POF1_MGQ_PAUSE_EN BIT(14) +#define B_AX_PPS1_POF1_HIQ_PAUSE_EN BIT(13) +#define B_AX_PPS1_POF1_BCNQ_PAUSE_EN BIT(12) +#define B_AX_PPS1_POF0_MGQ_PAUSE_EN BIT(11) +#define B_AX_PPS1_POF0_HIQ_PAUSE_EN BIT(10) +#define B_AX_PPS1_POF0_BCNQ_PAUSE_EN BIT(9) +#define B_AX_PPS1_MACID_PAUSE_EN BIT(8) +#define B_AX_PPS1_PAUSE_MACID_SH 0 +#define B_AX_PPS1_PAUSE_MACID_MSK 0xff + +#define R_AX_PPS1_PAUSE_CTRL1 0xC248 +#define R_AX_PPS1_PAUSE_CTRL1_C1 0xE248 +#define B_AX_PPS1_POWON_DISTX_SH 16 +#define B_AX_PPS1_POWON_DISTX_MSK 0xffff +#define B_AX_PPS1_POWOFF_DISTX_SH 0 +#define B_AX_PPS1_POWOFF_DISTX_MSK 0xffff + +#define R_AX_PPS1_PAUSE_CTRL2 0xC24C +#define R_AX_PPS1_PAUSE_CTRL2_C1 0xE24C +#define B_AX_PPS1_POWOFF_ERLY_SH 16 +#define B_AX_PPS1_POWOFF_ERLY_MSK 0xffff +#define B_AX_PPS1_POWON_ERLY_SH 0 +#define B_AX_PPS1_POWON_ERLY_MSK 0xffff + +#define R_AX_PPS1_POF0_PARAM0 0xC250 +#define R_AX_PPS1_POF0_PARAM0_C1 0xE250 +#define B_AX_PPS1_POF0_DUR_SH 0 +#define B_AX_PPS1_POF0_DUR_MSK 0xffffffffL + +#define R_AX_PPS1_POF0_PARAM1 0xC254 +#define R_AX_PPS1_POF0_PARAM1_C1 0xE254 +#define B_AX_PPS1_POF0_ITVL_SH 0 +#define B_AX_PPS1_POF0_ITVL_MSK 0xffffffffL + +#define R_AX_PPS1_POF0_PARAM2 0xC258 +#define R_AX_PPS1_POF0_PARAM2_C1 0xE258 +#define B_AX_PPS1_POF0_START_SH 0 +#define B_AX_PPS1_POF0_START_MSK 0xffffffffL + +#define R_AX_PPS1_POF0_PARAM3 0xC25C +#define R_AX_PPS1_POF0_PARAM3_C1 0xE25C +#define B_AX_PPS1_POF0_CUR_CNT_SH 8 +#define B_AX_PPS1_POF0_CUR_CNT_MSK 0xff +#define B_AX_PPS1_POF0_CNT_SH 0 +#define B_AX_PPS1_POF0_CNT_MSK 0xff + +#define R_AX_PPS1_POF1_PARAM0 0xC260 +#define R_AX_PPS1_POF1_PARAM0_C1 0xE260 +#define B_AX_PPS1_POF1_DUR_SH 0 +#define B_AX_PPS1_POF1_DUR_MSK 0xffffffffL + +#define R_AX_PPS1_POF1_PARAM1 0xC264 +#define R_AX_PPS1_POF1_PARAM1_C1 0xE264 +#define B_AX_PPS1_POF1_ITVL_SH 0 +#define B_AX_PPS1_POF1_ITVL_MSK 0xffffffffL + +#define R_AX_PPS1_POF1_PARAM2 0xC268 +#define R_AX_PPS1_POF1_PARAM2_C1 0xE268 +#define B_AX_PPS1_POF1_START_SH 0 +#define B_AX_PPS1_POF1_START_MSK 0xffffffffL + +#define R_AX_PPS1_POF1_PARAM3 0xC26C +#define R_AX_PPS1_POF1_PARAM3_C1 0xE26C +#define B_AX_PPS1_POF1_CUR_CNT_SH 8 +#define B_AX_PPS1_POF1_CUR_CNT_MSK 0xff +#define B_AX_PPS1_POF1_CNT_SH 0 +#define B_AX_PPS1_POF1_CNT_MSK 0xffffffffL + +#define R_AX_PPS1_CURR_DOZE0 0xC270 +#define R_AX_PPS1_CURR_DOZE0_C1 0xE270 +#define B_AX_PPS1_POF0_CURR_DOZE_SH 0 +#define B_AX_PPS1_POF0_CURR_DOZE_MSK 0xffffffffL + +#define R_AX_PPS1_CURR_DOZE1 0xC274 +#define R_AX_PPS1_CURR_DOZE1_C1 0xE274 +#define B_AX_PPS1_POF1_CURR_DOZE_SH 0 +#define B_AX_PPS1_POF1_CURR_DOZE_MSK 0xffffffffL + +#define R_AX_PORT_0_TSF_SYNC 0xC2A0 +#define R_AX_PORT_0_TSF_SYNC_C1 0xE2A0 +#define B_AX_P0_SYNC_NOW_P BIT(30) +#define B_AX_P0_SYNC_ONCE_P BIT(29) +#define B_AX_P0_AUTO_SYNC BIT(28) +#define B_AX_P0_SYNC_PORT_SRC_SEL_SH 24 +#define B_AX_P0_SYNC_PORT_SRC_SEL_MSK 0x7 +#define B_AX_P0_TSFTR_SYNC_OFFSET_SH 0 +#define B_AX_P0_TSFTR_SYNC_OFFSET_MSK 0x7ffff + +#define R_AX_PORT_1_TSF_SYNC 0xC2A4 +#define R_AX_PORT_1_TSF_SYNC_C1 0xE2A4 +#define B_AX_P1_SYNC_NOW_P BIT(30) +#define B_AX_P1_SYNC_ONCE_P BIT(29) +#define B_AX_P1_AUTO_SYNC BIT(28) +#define B_AX_P1_SYNC_PORT_SRC_SEL_SH 24 +#define B_AX_P1_SYNC_PORT_SRC_SEL_MSK 0x7 +#define B_AX_P1_TSFTR_SYNC_OFFSET_SH 0 +#define B_AX_P1_TSFTR_SYNC_OFFSET_MSK 0x7ffff + +#define R_AX_PORT_2_TSF_SYNC 0xC2A8 +#define R_AX_PORT_2_TSF_SYNC_C1 0xE2A8 +#define B_AX_P2_SYNC_NOW_P BIT(30) +#define B_AX_P2_SYNC_ONCE_P BIT(29) +#define B_AX_P2_AUTO_SYNC BIT(28) +#define B_AX_P2_SYNC_PORT_SRC_SEL_SH 24 +#define B_AX_P2_SYNC_PORT_SRC_SEL_MSK 0x7 +#define B_AX_P2_TSFTR_SYNC_OFFSET_SH 0 +#define B_AX_P2_TSFTR_SYNC_OFFSET_MSK 0x7ffff + +#define R_AX_PORT_3_TSF_SYNC 0xC2AC +#define R_AX_PORT_3_TSF_SYNC_C1 0xE2AC +#define B_AX_P3_SYNC_NOW_P BIT(30) +#define B_AX_P3_SYNC_ONCE_P BIT(29) +#define B_AX_P3_AUTO_SYNC BIT(28) +#define B_AX_P3_SYNC_PORT_SRC_SEL_SH 24 +#define B_AX_P3_SYNC_PORT_SRC_SEL_MSK 0x7 +#define B_AX_P3_TSFTR_SYNC_OFFSET_SH 0 +#define B_AX_P3_TSFTR_SYNC_OFFSET_MSK 0x7ffff + +#define R_AX_PORT_4_TSF_SYNC 0xC2B0 +#define R_AX_PORT_4_TSF_SYNC_C1 0xE2B0 +#define B_AX_P4_SYNC_NOW_P BIT(30) +#define B_AX_P4_SYNC_ONCE_P BIT(29) +#define B_AX_P4_AUTO_SYNC BIT(28) +#define B_AX_P4_SYNC_PORT_SRC_SEL_SH 24 +#define B_AX_P4_SYNC_PORT_SRC_SEL_MSK 0x7 +#define B_AX_P4_TSFTR_SYNC_OFFSET_SH 0 +#define B_AX_P4_TSFTR_SYNC_OFFSET_MSK 0x7ffff + +#define R_AX_MACID_SLEEP_0 0xC2C0 +#define R_AX_MACID_SLEEP_0_C1 0xE2C0 +#define B_AX_MACID31_0_SLEEP_SH 0 +#define B_AX_MACID31_0_SLEEP_MSK 0xffffffffL + +#define R_AX_MACID_SLEEP_1 0xC2C4 +#define R_AX_MACID_SLEEP_1_C1 0xE2C4 +#define B_AX_MACID63_32_SLEEP_SH 0 +#define B_AX_MACID63_32_SLEEP_MSK 0xffffffffL + +#define R_AX_MACID_SLEEP_2 0xC2C8 +#define R_AX_MACID_SLEEP_2_C1 0xE2C8 +#define B_AX_MACID95_64_SLEEP_SH 0 +#define B_AX_MACID95_64_SLEEP_MSK 0xffffffffL + +#define R_AX_MACID_SLEEP_3 0xC2CC +#define R_AX_MACID_SLEEP_3_C1 0xE2CC +#define B_AX_MACID127_96_SLEEP_SH 0 +#define B_AX_MACID127_96_SLEEP_MSK 0xffffffffL + +#define R_AX_CMAC_MACID_DROP_0 0xC2E0 +#define R_AX_CMAC_MACID_DROP_0_C1 0xE2E0 +#define B_AX_CMAC_MACID31_0_DROP_SH 0 +#define B_AX_CMAC_MACID31_0_DROP_MSK 0xffffffffL + +#define R_AX_CMAC_MACID_DROP_1 0xC2E4 +#define R_AX_CMAC_MACID_DROP_1_C1 0xE2E4 +#define B_AX_CMAC_MACID63_32_DROP_SH 0 +#define B_AX_CMAC_MACID63_32_DROP_MSK 0xffffffffL + +#define R_AX_CMAC_MACID_DROP_2 0xC2E8 +#define R_AX_CMAC_MACID_DROP_2_C1 0xE2E8 +#define B_AX_CMAC_MACID95_64_DROP_SH 0 +#define B_AX_CMAC_MACID95_64_DROP_MSK 0xffffffffL + +#define R_AX_CMAC_MACID_DROP_3 0xC2EC +#define R_AX_CMAC_MACID_DROP_3_C1 0xE2EC +#define B_AX_CMAC_MACID127_96_DROP_SH 0 +#define B_AX_CMAC_MACID127_96_DROP_MSK 0xffffffffL + +#define R_AX_EDCA_BE_PARAM_0 0xC300 +#define R_AX_EDCA_BE_PARAM_0_C1 0xE300 +#define B_AX_BE_0_TXOPLMT_SH 16 +#define B_AX_BE_0_TXOPLMT_MSK 0x7ff +#define B_AX_BE_0_CW_SH 8 +#define B_AX_BE_0_CW_MSK 0xff +#define B_AX_BE_0_AIFS_SH 0 +#define B_AX_BE_0_AIFS_MSK 0xff + +#define R_AX_EDCA_BK_PARAM_0 0xC304 +#define R_AX_EDCA_BK_PARAM_0_C1 0xE304 +#define B_AX_BK_0_TXOPLMT_SH 16 +#define B_AX_BK_0_TXOPLMT_MSK 0x7ff +#define B_AX_BK_0_CW_SH 8 +#define B_AX_BK_0_CW_MSK 0xff +#define B_AX_BK_0_AIFS_SH 0 +#define B_AX_BK_0_AIFS_MSK 0xff + +#define R_AX_EDCA_VI_PARAM_0 0xC308 +#define R_AX_EDCA_VI_PARAM_0_C1 0xE308 +#define B_AX_VI_0_TXOPLMT_SH 16 +#define B_AX_VI_0_TXOPLMT_MSK 0x7ff +#define B_AX_VI_0_CW_SH 8 +#define B_AX_VI_0_CW_MSK 0xff +#define B_AX_VI_0_AIFS_SH 0 +#define B_AX_VI_0_AIFS_MSK 0xff + +#define R_AX_EDCA_VO_PARAM_0 0xC30C +#define R_AX_EDCA_VO_PARAM_0_C1 0xE30C +#define B_AX_VO_0_TXOPLMT_SH 16 +#define B_AX_VO_0_TXOPLMT_MSK 0x7ff +#define B_AX_VO_0_CW_SH 8 +#define B_AX_VO_0_CW_MSK 0xff +#define B_AX_VO_0_AIFS_SH 0 +#define B_AX_VO_0_AIFS_MSK 0xff + +#define R_AX_EDCA_BE_PARAM_1 0xC310 +#define R_AX_EDCA_BE_PARAM_1_C1 0xE310 +#define B_AX_BE_1_TXOPLMT_SH 16 +#define B_AX_BE_1_TXOPLMT_MSK 0x7ff +#define B_AX_BE_1_CW_SH 8 +#define B_AX_BE_1_CW_MSK 0xff +#define B_AX_BE_1_AIFS_SH 0 +#define B_AX_BE_1_AIFS_MSK 0xff + +#define R_AX_EDCA_BK_PARAM_1 0xC314 +#define R_AX_EDCA_BK_PARAM_1_C1 0xE314 +#define B_AX_BK_1_TXOPLMT_SH 16 +#define B_AX_BK_1_TXOPLMT_MSK 0x7ff +#define B_AX_BK_1_CW_SH 8 +#define B_AX_BK_1_CW_MSK 0xff +#define B_AX_BK_1_AIFS_SH 0 +#define B_AX_BK_1_AIFS_MSK 0xff + +#define R_AX_EDCA_VI_PARAM_1 0xC318 +#define R_AX_EDCA_VI_PARAM_1_C1 0xE318 +#define B_AX_VI_1_TXOPLMT_SH 16 +#define B_AX_VI_1_TXOPLMT_MSK 0x7ff +#define B_AX_VI_1_CW_SH 8 +#define B_AX_VI_1_CW_MSK 0xff +#define B_AX_VI_1_AIFS_SH 0 +#define B_AX_VI_1_AIFS_MSK 0xff + +#define R_AX_EDCA_VO_PARAM_1 0xC31C +#define R_AX_EDCA_VO_PARAM_1_C1 0xE31C +#define B_AX_VO_1_TXOPLMT_SH 16 +#define B_AX_VO_1_TXOPLMT_MSK 0x7ff +#define B_AX_VO_1_CW_SH 8 +#define B_AX_VO_1_CW_MSK 0xff +#define B_AX_VO_1_AIFS_SH 0 +#define B_AX_VO_1_AIFS_MSK 0xff + +#define R_AX_EDCA_MGQ_PARAM 0xC320 +#define R_AX_EDCA_MGQ_PARAM_C1 0xE320 +#define B_AX_CPUMGQ_CW_SH 24 +#define B_AX_CPUMGQ_CW_MSK 0xff +#define B_AX_CPUMGQ_AIFS_SH 16 +#define B_AX_CPUMGQ_AIFS_MSK 0xff +#define B_AX_MGQ_CW_SH 8 +#define B_AX_MGQ_CW_MSK 0xff +#define B_AX_MGQ_AIFS_SH 0 +#define B_AX_MGQ_AIFS_MSK 0xff + +#define R_AX_EDCA_BCNQ_PARAM 0xC324 +#define R_AX_EDCA_BCNQ_PARAM_C1 0xE324 +#define B_AX_BCNQ_CW_SH 24 +#define B_AX_BCNQ_CW_MSK 0xff +#define B_AX_BCNQ_AIFS_SH 16 +#define B_AX_BCNQ_AIFS_MSK 0xff +#define B_AX_FORCE_BCN_IFS_SH 8 +#define B_AX_FORCE_BCN_IFS_MSK 0xff +#define B_AX_PIFS_SH 0 +#define B_AX_PIFS_MSK 0xff + +#define R_AX_EDCA_ULQ_PARAM 0xC328 +#define R_AX_EDCA_ULQ_PARAM_C1 0xE328 +#define B_AX_ULQ_TXOPLMT_SH 16 +#define B_AX_ULQ_TXOPLMT_MSK 0x7ff +#define B_AX_ULQ_CW_SH 8 +#define B_AX_ULQ_CW_MSK 0xff +#define B_AX_ULQ_AIFS_SH 0 +#define B_AX_ULQ_AIFS_MSK 0xff + +#define R_AX_EDCA_TWT_PARAM_0 0xC32C +#define R_AX_EDCA_TWT_PARAM_0_C1 0xE32C +#define B_AX_TWT_0_TXOPLMT_SH 16 +#define B_AX_TWT_0_TXOPLMT_MSK 0x7ff +#define B_AX_TWT_0_CW_SH 8 +#define B_AX_TWT_0_CW_MSK 0xff +#define B_AX_TWT_0_AIFS_SH 0 +#define B_AX_TWT_0_AIFS_MSK 0xff + +#define R_AX_EDCA_TWT_PARAM_1 0xC330 +#define R_AX_EDCA_TWT_PARAM_1_C1 0xE330 +#define B_AX_TWT_1_TXOPLMT_SH 16 +#define B_AX_TWT_1_TXOPLMT_MSK 0x7ff +#define B_AX_TWT_1_CW_SH 8 +#define B_AX_TWT_1_CW_MSK 0xff +#define B_AX_TWT_1_AIFS_SH 0 +#define B_AX_TWT_1_AIFS_MSK 0xff + +#define R_AX_SLOTTIME_CFG 0xC334 +#define R_AX_SLOTTIME_CFG_C1 0xE334 +#define B_AX_SLOT_TIME_SH 0 +#define B_AX_SLOT_TIME_MSK 0xff + +#define R_AX_PREBKF_CFG_0 0xC338 +#define R_AX_PREBKF_CFG_0_C1 0xE338 +#define B_AX_100NS_TIME_SH 24 +#define B_AX_100NS_TIME_MSK 0x1f +#define B_AX_RX_AIR_END_TIME_SH 16 +#define B_AX_RX_AIR_END_TIME_MSK 0x7f +#define B_AX_MACTX_LATENCY_SH 8 +#define B_AX_MACTX_LATENCY_MSK 0x3f +#define B_AX_PREBKF_TIME_SH 0 +#define B_AX_PREBKF_TIME_MSK 0xff + +#define R_AX_PREBKF_CFG_1 0xC33C +#define R_AX_PREBKF_CFG_1_C1 0xE33C +#define B_AX_SIFS_PREBKF_SH 16 +#define B_AX_SIFS_PREBKF_MSK 0xff +#define B_AX_SIFS_TIMEOUT_T2_SH 8 +#define B_AX_SIFS_TIMEOUT_T2_MSK 0x7f +#define B_AX_SIFS_MACTXEN_T1_SH 0 +#define B_AX_SIFS_MACTXEN_T1_MSK 0x7f + +#define R_AX_CCA_CFG_0 0xC340 +#define R_AX_CCA_CFG_0_C1 0xE340 +#define B_AX_R_SIFS_AGGR_TIME_SH 24 +#define B_AX_R_SIFS_AGGR_TIME_MSK 0x7f +#define B_AX_BTCCA_BRK_TXOP_EN BIT(9) +#define B_AX_NAV_BRK_TXOP_EN BIT(8) +#define B_AX_TX_NAV_EN BIT(7) +#define B_AX_BCN_IGNORE_EDCCA BIT(6) +#define B_AX_BTCCA_EN BIT(5) +#define B_AX_EDCCA_EN BIT(4) +#define B_AX_SEC80_EN BIT(3) +#define B_AX_SEC40_EN BIT(2) +#define B_AX_SEC20_EN BIT(1) +#define B_AX_CCA_EN BIT(0) + +#define R_AX_MISC_0 0xC344 +#define R_AX_MISC_0_C1 0xE344 +#define B_AX_RST_FREERUN_P BIT(15) +#define B_AX_EN_FREERUN BIT(8) +#define B_AX_EN_TBTT_AREA_FOR_AX_BB BIT(0) + +#define R_AX_CTN_TXEN 0xC348 +#define R_AX_CTN_TXEN_C1 0xE348 +#define B_AX_CTN_TXEN_TWT_1 BIT(15) +#define B_AX_CTN_TXEN_TWT_0 BIT(14) +#define B_AX_CTN_TXEN_ULQ BIT(13) +#define B_AX_CTN_TXEN_BCNQ BIT(12) +#define B_AX_CTN_TXEN_HGQ BIT(11) +#define B_AX_CTN_TXEN_CPUMGQ BIT(10) +#define B_AX_CTN_TXEN_MGQ1 BIT(9) +#define B_AX_CTN_TXEN_MGQ BIT(8) +#define B_AX_CTN_TXEN_VO_1 BIT(7) +#define B_AX_CTN_TXEN_VI_1 BIT(6) +#define B_AX_CTN_TXEN_BK_1 BIT(5) +#define B_AX_CTN_TXEN_BE_1 BIT(4) +#define B_AX_CTN_TXEN_VO_0 BIT(3) +#define B_AX_CTN_TXEN_VI_0 BIT(2) +#define B_AX_CTN_TXEN_BK_0 BIT(1) +#define B_AX_CTN_TXEN_BE_0 BIT(0) + +#define R_AX_CTN_CFG_0 0xC34C +#define R_AX_CTN_CFG_0_C1 0xE34C +#define B_AX_NAV_BLK_HGQ BIT(1) +#define B_AX_NAV_BLK_MGQ BIT(0) + +#define R_AX_MUEDCA_BE_PARAM_0 0xC350 +#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 +#define B_AX_MUEDCA_BE_PARAM_0_TIMER_SH 16 +#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MSK 0xffff +#define B_AX_MUEDCA_BE_PARAM_0_CW_SH 8 +#define B_AX_MUEDCA_BE_PARAM_0_CW_MSK 0xff +#define B_AX_MUEDCA_BE_PARAM_0_AIFS_SH 0 +#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MSK 0xff + +#define R_AX_MUEDCA_BK_PARAM_0 0xC354 +#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 +#define B_AX_MUEDCA_BK_PARAM_0_TIMER_SH 16 +#define B_AX_MUEDCA_BK_PARAM_0_TIMER_MSK 0xffff +#define B_AX_MUEDCA_BK_PARAM_0_CW_SH 8 +#define B_AX_MUEDCA_BK_PARAM_0_CW_MSK 0xff +#define B_AX_MUEDCA_BK_PARAM_0_AIFS_SH 0 +#define B_AX_MUEDCA_BK_PARAM_0_AIFS_MSK 0xff + +#define R_AX_MUEDCA_VI_PARAM_0 0xC358 +#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 +#define B_AX_MUEDCA_VI_PARAM_0_TIMER_SH 16 +#define B_AX_MUEDCA_VI_PARAM_0_TIMER_MSK 0xffff +#define B_AX_MUEDCA_VI_PARAM_0_CW_SH 8 +#define B_AX_MUEDCA_VI_PARAM_0_CW_MSK 0xff +#define B_AX_MUEDCA_VI_PARAM_0_AIFS_SH 0 +#define B_AX_MUEDCA_VI_PARAM_0_AIFS_MSK 0xff + +#define R_AX_MUEDCA_VO_PARAM_0 0xC35C +#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C +#define B_AX_MUEDCA_VO_PARAM_0_TIMER_SH 16 +#define B_AX_MUEDCA_VO_PARAM_0_TIMER_MSK 0xffff +#define B_AX_MUEDCA_VO_PARAM_0_CW_SH 8 +#define B_AX_MUEDCA_VO_PARAM_0_CW_MSK 0xff +#define B_AX_MUEDCA_VO_PARAM_0_AIFS_SH 0 +#define B_AX_MUEDCA_VO_PARAM_0_AIFS_MSK 0xff + +#define R_AX_MUEDCA_EN 0xC370 +#define R_AX_MUEDCA_EN_C1 0xE370 +#define B_AX_MUEDCA_WMM_SEL BIT(8) +#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) +#define B_AX_MUEDCA_EN_0 BIT(0) + +#define R_AX_RAND_SCR_BIT 0xC374 +#define R_AX_RAND_SCR_BIT_C1 0xE374 +#define B_AX_RAND_SCBITS_SH 0 +#define B_AX_RAND_SCBITS_MSK 0x7fffff + +#define R_AX_RANDOM_CFG 0xC378 +#define R_AX_RANDOM_CFG_C1 0xE378 +#define B_AX_RAND_SET_SH 0 +#define B_AX_RAND_SET_MSK 0xffffff + +#define R_AX_MUEDCATIMER_0 0xC380 +#define R_AX_MUEDCATIMER_0_C1 0xE380 +#define B_AX_MUEDCATIMER_BK_0_SH 16 +#define B_AX_MUEDCATIMER_BK_0_MSK 0xffff +#define B_AX_MUEDCATIMER_BE_0_SH 0 +#define B_AX_MUEDCATIMER_BE_0_MSK 0xffff + +#define R_AX_MUEDCATIMER_1 0xC384 +#define R_AX_MUEDCATIMER_1_C1 0xE384 +#define B_AX_MUEDCATIMER_VO_0_SH 16 +#define B_AX_MUEDCATIMER_VO_0_MSK 0xffff +#define B_AX_MUEDCATIMER_VI_0_SH 0 +#define B_AX_MUEDCATIMER_VI_0_MSK 0xffff + +#define R_AX_CCA_CONTROL 0xC390 +#define R_AX_CCA_CONTROL_C1 0xE390 +#define B_AX_TB_CHK_TX_NAV BIT(31) +#define B_AX_TB_CHK_BASIC_NAV BIT(30) +#define B_AX_TB_CHK_BTCCA BIT(29) +#define B_AX_TB_CHK_EDCCA BIT(28) +#define B_AX_TB_CHK_CCA_S80 BIT(27) +#define B_AX_TB_CHK_CCA_S40 BIT(26) +#define B_AX_TB_CHK_CCA_S20 BIT(25) +#define B_AX_TB_CHK_CCA_P20 BIT(24) +#define B_AX_SIFS_CHK_BTCCA BIT(21) +#define B_AX_SIFS_CHK_EDCCA BIT(20) +#define B_AX_SIFS_CHK_CCA_S80 BIT(19) +#define B_AX_SIFS_CHK_CCA_S40 BIT(18) +#define B_AX_SIFS_CHK_CCA_S20 BIT(17) +#define B_AX_SIFS_CHK_CCA_P20 BIT(16) +#define B_AX_CTN_CHK_TXNAV BIT(8) +#define B_AX_CTN_CHK_INTRA_NAV BIT(7) +#define B_AX_CTN_CHK_BASIC_NAV BIT(6) +#define B_AX_CTN_CHK_BTCCA BIT(5) +#define B_AX_CTN_CHK_EDCCA BIT(4) +#define B_AX_CTN_CHK_CCA_S80 BIT(3) +#define B_AX_CTN_CHK_CCA_S40 BIT(2) +#define B_AX_CTN_CHK_CCA_S20 BIT(1) +#define B_AX_CTN_CHK_CCA_P20 BIT(0) + +#define R_AX_SCHEDULE_ERR_IMR 0xC3E8 +#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 +#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) +#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) + +#define R_AX_SCHEDULE_ERR_ISR 0xC3EC +#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC +#define B_AX_SORT_NON_IDLE_ERR_INT BIT(1) +#define B_AX_FSM_TIMEOUT_ERR_INT BIT(0) + +#define R_AX_SCH_DBG_SEL 0xC3F4 +#define R_AX_SCH_DBG_SEL_C1 0xE3F4 +#define B_AX_SCH_DBG_EN BIT(16) +#define B_AX_SCH_CFG_CMD_SEL_SH 8 +#define B_AX_SCH_CFG_CMD_SEL_MSK 0xff +#define B_AX_SCH_DBG_SEL_SH 0 +#define B_AX_SCH_DBG_SEL_MSK 0xff + +#define R_AX_SCH_DBG 0xC3F8 +#define R_AX_SCH_DBG_C1 0xE3F8 +#define B_AX_SCHEDULER_DBG_SH 0 +#define B_AX_SCHEDULER_DBG_MSK 0xffffffffL + +#define R_AX_SCH_EXT_CTRL 0xC3FC +#define R_AX_SCH_EXT_CTRL_C1 0xE3FC +#define B_AX_PORT_RST_TSF_ADV BIT(1) +#define B_AX_SCH_RESP_CTRL BIT(0) + +#define R_AX_PORT_CFG_P0 0xC400 +#define R_AX_PORT_CFG_P0_C1 0xE400 +#define B_AX_BRK_SETUP_P0 BIT(16) +#define B_AX_TBTT_UPD_SHIFT_SEL_P0 BIT(15) +#define B_AX_BCN_DROP_ALLOW_P0 BIT(14) +#define B_AX_TBTT_PROHIB_EN_P0 BIT(13) +#define B_AX_BCNTX_EN_P0 BIT(12) +#define B_AX_NET_TYPE_P0_SH 10 +#define B_AX_NET_TYPE_P0_MSK 0x3 +#define B_AX_BCN_FORCETX_EN_P0 BIT(9) +#define B_AX_TXBCN_BTCCA_EN_P0 BIT(8) +#define B_AX_BCNERR_CNT_EN_P0 BIT(7) +#define B_AX_BCN_AGRES_P0 BIT(6) +#define B_AX_TSFTR_RST_P0 BIT(5) +#define B_AX_RX_BSSID_FIT_EN_P0 BIT(4) +#define B_AX_TSF_UDT_EN_P0 BIT(3) +#define B_AX_PORT_FUNC_EN_P0 BIT(2) +#define B_AX_TXBCN_RPT_EN_P0 BIT(1) +#define B_AX_RXBCN_RPT_EN_P0 BIT(0) + +#define R_AX_TBTT_PROHIB_P0 0xC404 +#define R_AX_TBTT_PROHIB_P0_C1 0xE404 +#define B_AX_TBTT_HOLD_P0_SH 16 +#define B_AX_TBTT_HOLD_P0_MSK 0xfff +#define B_AX_TBTT_SETUP_P0_SH 0 +#define B_AX_TBTT_SETUP_P0_MSK 0xff + +#define R_AX_BCN_AREA_P0 0xC408 +#define R_AX_BCN_AREA_P0_C1 0xE408 +#define B_AX_BCN_MSK_AREA_P0_SH 16 +#define B_AX_BCN_MSK_AREA_P0_MSK 0xfff +#define B_AX_BCN_CTN_AREA_P0_SH 0 +#define B_AX_BCN_CTN_AREA_P0_MSK 0xfff + +#define R_AX_BCNERLYINT_CFG_P0 0xC40C +#define R_AX_BCNERLYINT_CFG_P0_C1 0xE40C +#define B_AX_BCNERLY_P0_SH 0 +#define B_AX_BCNERLY_P0_MSK 0xfff + +#define R_AX_TBTTERLYINT_CFG_P0 0xC40E +#define R_AX_TBTTERLYINT_CFG_P0_C1 0xE40E +#define B_AX_TBTTERLY_P0_SH 0 +#define B_AX_TBTTERLY_P0_MSK 0xfff + +#define R_AX_TBTT_AGG_P0 0xC412 +#define R_AX_TBTT_AGG_P0_C1 0xE412 +#define B_AX_TBTT_AGG_NUM_P0_SH 8 +#define B_AX_TBTT_AGG_NUM_P0_MSK 0xff + +#define R_AX_BCN_SPACE_CFG_P0 0xC414 +#define R_AX_BCN_SPACE_CFG_P0_C1 0xE414 +#define B_AX_SUB_BCN_SPACE_P0_SH 16 +#define B_AX_SUB_BCN_SPACE_P0_MSK 0xff +#define B_AX_BCN_SPACE_P0_SH 0 +#define B_AX_BCN_SPACE_P0_MSK 0xffff + +#define R_AX_BCN_FORCETX_P0 0xC418 +#define R_AX_BCN_FORCETX_P0_C1 0xE418 +#define B_AX_FORCE_BCN_CURRCNT_P0_SH 16 +#define B_AX_FORCE_BCN_CURRCNT_P0_MSK 0xff +#define B_AX_FORCE_BCN_NUM_P0_SH 8 +#define B_AX_FORCE_BCN_NUM_P0_MSK 0xff +#define B_AX_BCN_MAX_ERR_P0_SH 0 +#define B_AX_BCN_MAX_ERR_P0_MSK 0xff + +#define R_AX_BCN_ERR_CNT_P0 0xC420 +#define R_AX_BCN_ERR_CNT_P0_C1 0xE420 +#define B_AX_BCN_ERR_CNT_SUM_P0_SH 24 +#define B_AX_BCN_ERR_CNT_SUM_P0_MSK 0xff +#define B_AX_BCN_ERR_CNT_NAV_P0_SH 16 +#define B_AX_BCN_ERR_CNT_NAV_P0_MSK 0xff +#define B_AX_BCN_ERR_CNT_EDCCA_P0_SH 8 +#define B_AX_BCN_ERR_CNT_EDCCA_P0_MSK 0xff +#define B_AX_BCN_ERR_CNT_CCA_P0_SH 0 +#define B_AX_BCN_ERR_CNT_CCA_P0_MSK 0xff + +#define R_AX_BCN_ERR_FLAG_P0 0xC424 +#define R_AX_BCN_ERR_FLAG_P0_C1 0xE424 +#define B_AX_BCN_ERR_FLAG_OTHERS_P0 BIT(6) +#define B_AX_BCN_ERR_FLAG_MAC_P0 BIT(5) +#define B_AX_BCN_ERR_FLAG_TXON_P0 BIT(4) +#define B_AX_BCN_ERR_FLAG_SRCHEND_P0 BIT(3) +#define B_AX_BCN_ERR_FLAG_INVALID_P0 BIT(2) +#define B_AX_BCN_ERR_FLAG_CMP_P0 BIT(1) +#define B_AX_BCN_ERR_FLAG_LOCK_P0 BIT(0) + +#define R_AX_DTIM_CTRL_P0 0xC426 +#define R_AX_DTIM_CTRL_P0_C1 0xE426 +#define B_AX_DTIM_NUM_P0_SH 8 +#define B_AX_DTIM_NUM_P0_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0_SH 0 +#define B_AX_DTIM_CURRCNT_P0_MSK 0xff + +#define R_AX_TBTT_SHIFT_P0 0xC428 +#define R_AX_TBTT_SHIFT_P0_C1 0xE428 +#define B_AX_TBTT_SHIFT_OFST_P0_SH 0 +#define B_AX_TBTT_SHIFT_OFST_P0_MSK 0xfff + +#define R_AX_BCN_CNT_TMR_P0 0xC434 +#define R_AX_BCN_CNT_TMR_P0_C1 0xE434 +#define B_AX_BCN_CNT_TMR_P0_SH 0 +#define B_AX_BCN_CNT_TMR_P0_MSK 0xffffffffL + +#define R_AX_TSFTR_LOW_P0 0xC438 +#define R_AX_TSFTR_LOW_P0_C1 0xE438 +#define B_AX_TSFTR_LOW_P0_SH 0 +#define B_AX_TSFTR_LOW_P0_MSK 0xffffffffL + +#define R_AX_TSFTR_HIGH_P0 0xC43C +#define R_AX_TSFTR_HIGH_P0_C1 0xE43C +#define B_AX_TSFTR_HIGH_P0_SH 0 +#define B_AX_TSFTR_HIGH_P0_MSK 0xffffffffL + +#define R_AX_PORT_CFG_P1 0xC440 +#define R_AX_PORT_CFG_P1_C1 0xE440 +#define B_AX_BRK_SETUP_P1 BIT(16) +#define B_AX_TBTT_UPD_SHIFT_SEL_P1 BIT(15) +#define B_AX_BCN_DROP_ALLOW_P1 BIT(14) +#define B_AX_TBTT_PROHIB_EN_P1 BIT(13) +#define B_AX_BCNTX_EN_P1 BIT(12) +#define B_AX_NET_TYPE_P1_SH 10 +#define B_AX_NET_TYPE_P1_MSK 0x3 +#define B_AX_BCN_FORCETX_EN_P1 BIT(9) +#define B_AX_TXBCN_BTCCA_EN_P1 BIT(8) +#define B_AX_BCNERR_CNT_EN_P1 BIT(7) +#define B_AX_BCN_AGRES_P1 BIT(6) +#define B_AX_TSFTR_RST_P1 BIT(5) +#define B_AX_RX_BSSID_FIT_EN_P1 BIT(4) +#define B_AX_TSF_UDT_EN_P1 BIT(3) +#define B_AX_PORT_FUNC_EN_P1 BIT(2) +#define B_AX_TXBCN_RPT_EN_P1 BIT(1) +#define B_AX_RXBCN_RPT_EN_P1 BIT(0) + +#define R_AX_TBTT_PROHIB_P1 0xC444 +#define R_AX_TBTT_PROHIB_P1_C1 0xE444 +#define B_AX_TBTT_HOLD_P1_SH 16 +#define B_AX_TBTT_HOLD_P1_MSK 0xfff +#define B_AX_TBTT_SETUP_P1_SH 0 +#define B_AX_TBTT_SETUP_P1_MSK 0xff + +#define R_AX_BCN_AREA_P1 0xC448 +#define R_AX_BCN_AREA_P1_C1 0xE448 +#define B_AX_BCN_MSK_AREA_P1_SH 16 +#define B_AX_BCN_MSK_AREA_P1_MSK 0xfff +#define B_AX_BCN_CTN_AREA_P1_SH 0 +#define B_AX_BCN_CTN_AREA_P1_MSK 0xfff + +#define R_AX_BCNERLYINT_CFG_P1 0xC44C +#define R_AX_BCNERLYINT_CFG_P1_C1 0xE44C +#define B_AX_BCNERLY_P1_SH 0 +#define B_AX_BCNERLY_P1_MSK 0xfff + +#define R_AX_TBTTERLYINT_CFG_P1 0xC44E +#define R_AX_TBTTERLYINT_CFG_P1_C1 0xE44E +#define B_AX_TBTTERLY_P1_SH 0 +#define B_AX_TBTTERLY_P1_MSK 0xfff + +#define R_AX_TBTT_AGG_P1 0xC452 +#define R_AX_TBTT_AGG_P1_C1 0xE452 +#define B_AX_TBTT_AGG_NUM_P1_SH 8 +#define B_AX_TBTT_AGG_NUM_P1_MSK 0xff + +#define R_AX_BCN_SPACE_CFG_P1 0xC454 +#define R_AX_BCN_SPACE_CFG_P1_C1 0xE454 +#define B_AX_BCN_SPACE_P1_SH 0 +#define B_AX_BCN_SPACE_P1_MSK 0xffff + +#define R_AX_BCN_FORCETX_P1 0xC458 +#define R_AX_BCN_FORCETX_P1_C1 0xE458 +#define B_AX_FORCE_BCN_CURRCNT_P1_SH 16 +#define B_AX_FORCE_BCN_CURRCNT_P1_MSK 0xff +#define B_AX_FORCE_BCN_NUM_P1_SH 8 +#define B_AX_FORCE_BCN_NUM_P1_MSK 0xff +#define B_AX_BCN_MAX_ERR_P1_SH 0 +#define B_AX_BCN_MAX_ERR_P1_MSK 0xff + +#define R_AX_BCN_ERR_CNT_P1 0xC460 +#define R_AX_BCN_ERR_CNT_P1_C1 0xE460 +#define B_AX_BCN_ERR_CNT_SUM_P1_SH 24 +#define B_AX_BCN_ERR_CNT_SUM_P1_MSK 0xff +#define B_AX_BCN_ERR_CNT_NAV_P1_SH 16 +#define B_AX_BCN_ERR_CNT_NAV_P1_MSK 0xff +#define B_AX_BCN_ERR_CNT_EDCCA_P1_SH 8 +#define B_AX_BCN_ERR_CNT_EDCCA_P1_MSK 0xff +#define B_AX_BCN_ERR_CNT_CCA_P1_SH 0 +#define B_AX_BCN_ERR_CNT_CCA_P1_MSK 0xff + +#define R_AX_BCN_ERR_FLAG_P1 0xC464 +#define R_AX_BCN_ERR_FLAG_P1_C1 0xE464 +#define B_AX_BCN_ERR_FLAG_OTHERS_P1 BIT(6) +#define B_AX_BCN_ERR_FLAG_MAC_P1 BIT(5) +#define B_AX_BCN_ERR_FLAG_TXON_P1 BIT(4) +#define B_AX_BCN_ERR_FLAG_SRCHEND_P1 BIT(3) +#define B_AX_BCN_ERR_FLAG_INVALID_P1 BIT(2) +#define B_AX_BCN_ERR_FLAG_CMP_P1 BIT(1) +#define B_AX_BCN_ERR_FLAG_LOCK_P1 BIT(0) + +#define R_AX_DTIM_CTRL_P1 0xC466 +#define R_AX_DTIM_CTRL_P1_C1 0xE466 +#define B_AX_DTIM_NUM_P1_SH 8 +#define B_AX_DTIM_NUM_P1_MSK 0xff +#define B_AX_DTIM_CURRCNT_P1_SH 0 +#define B_AX_DTIM_CURRCNT_P1_MSK 0xff + +#define R_AX_TBTT_SHIFT_P1 0xC468 +#define R_AX_TBTT_SHIFT_P1_C1 0xE468 +#define B_AX_TBTT_SHIFT_OFST_P1_SH 0 +#define B_AX_TBTT_SHIFT_OFST_P1_MSK 0xfff + +#define R_AX_BCN_CNT_TMR_P1 0xC474 +#define R_AX_BCN_CNT_TMR_P1_C1 0xE474 +#define B_AX_BCN_CNT_TMR_P1_SH 0 +#define B_AX_BCN_CNT_TMR_P1_MSK 0xffffffffL + +#define R_AX_TSFTR_LOW_P1 0xC478 +#define R_AX_TSFTR_LOW_P1_C1 0xE478 +#define B_AX_TSFTR_LOW_P1_SH 0 +#define B_AX_TSFTR_LOW_P1_MSK 0xffffffffL + +#define R_AX_TSFTR_HIGH_P1 0xC47C +#define R_AX_TSFTR_HIGH_P1_C1 0xE47C +#define B_AX_TSFTR_HIGH_P1_SH 0 +#define B_AX_TSFTR_HIGH_P1_MSK 0xffffffffL + +#define R_AX_PORT_CFG_P2 0xC480 +#define R_AX_PORT_CFG_P2_C1 0xE480 +#define B_AX_BRK_SETUP_P2 BIT(16) +#define B_AX_TBTT_UPD_SHIFT_SEL_P2 BIT(15) +#define B_AX_BCN_DROP_ALLOW_P2 BIT(14) +#define B_AX_TBTT_PROHIB_EN_P2 BIT(13) +#define B_AX_BCNTX_EN_P2 BIT(12) +#define B_AX_NET_TYPE_P2_SH 10 +#define B_AX_NET_TYPE_P2_MSK 0x3 +#define B_AX_BCN_FORCETX_EN_P2 BIT(9) +#define B_AX_TXBCN_BTCCA_EN_P2 BIT(8) +#define B_AX_BCNERR_CNT_EN_P2 BIT(7) +#define B_AX_BCN_AGRES_P2 BIT(6) +#define B_AX_TSFTR_RST_P2 BIT(5) +#define B_AX_RX_BSSID_FIT_EN_P2 BIT(4) +#define B_AX_TSF_UDT_EN_P2 BIT(3) +#define B_AX_PORT_FUNC_EN_P2 BIT(2) +#define B_AX_TXBCN_RPT_EN_P2 BIT(1) +#define B_AX_RXBCN_RPT_EN_P2 BIT(0) + +#define R_AX_BCN_AREA_P2 0xC488 +#define R_AX_BCN_AREA_P2_C1 0xE488 +#define B_AX_BCN_MSK_AREA_P2_SH 16 +#define B_AX_BCN_MSK_AREA_P2_MSK 0xfff + +#define R_AX_BCNERLYINT_CFG_P2 0xC48C +#define R_AX_BCNERLYINT_CFG_P2_C1 0xE48C +#define B_AX_BCNERLY_P2_SH 0 +#define B_AX_BCNERLY_P2_MSK 0xfff + +#define R_AX_TBTTERLYINT_CFG_P2 0xC48E +#define R_AX_TBTTERLYINT_CFG_P2_C1 0xE48E +#define B_AX_TBTTERLY_P2_SH 0 +#define B_AX_TBTTERLY_P2_MSK 0xfff + +#define R_AX_TBTT_AGG_P2 0xC492 +#define R_AX_TBTT_AGG_P2_C1 0xE492 +#define B_AX_TBTT_AGG_NUM_P2_SH 8 +#define B_AX_TBTT_AGG_NUM_P2_MSK 0xff + +#define R_AX_BCN_SPACE_CFG_P2 0xC494 +#define R_AX_BCN_SPACE_CFG_P2_C1 0xE494 +#define B_AX_BCN_SPACE_P2_SH 0 +#define B_AX_BCN_SPACE_P2_MSK 0xffff + +#define R_AX_BCN_FORCETX_P2 0xC498 +#define R_AX_BCN_FORCETX_P2_C1 0xE498 +#define B_AX_FORCE_BCN_CURRCNT_P2_SH 16 +#define B_AX_FORCE_BCN_CURRCNT_P2_MSK 0xff +#define B_AX_FORCE_BCN_NUM_P2_SH 8 +#define B_AX_FORCE_BCN_NUM_P2_MSK 0xff +#define B_AX_BCN_MAX_ERR_P2_SH 0 +#define B_AX_BCN_MAX_ERR_P2_MSK 0xff + +#define R_AX_BCN_ERR_CNT_P2 0xC4A0 +#define R_AX_BCN_ERR_CNT_P2_C1 0xE4A0 +#define B_AX_BCN_ERR_CNT_SUM_P2_SH 24 +#define B_AX_BCN_ERR_CNT_SUM_P2_MSK 0xff +#define B_AX_BCN_ERR_CNT_NAV_P2_SH 16 +#define B_AX_BCN_ERR_CNT_NAV_P2_MSK 0xff +#define B_AX_BCN_ERR_CNT_EDCCA_P2_SH 8 +#define B_AX_BCN_ERR_CNT_EDCCA_P2_MSK 0xff +#define B_AX_BCN_ERR_CNT_CCA_P2_SH 0 +#define B_AX_BCN_ERR_CNT_CCA_P2_MSK 0xff + +#define R_AX_BCN_ERR_FLAG_P2 0xC4A4 +#define R_AX_BCN_ERR_FLAG_P2_C1 0xE4A4 +#define B_AX_BCN_ERR_FLAG_OTHERS_P2 BIT(6) +#define B_AX_BCN_ERR_FLAG_MAC_P2 BIT(5) +#define B_AX_BCN_ERR_FLAG_TXON_P2 BIT(4) +#define B_AX_BCN_ERR_FLAG_SRCHEND_P2 BIT(3) +#define B_AX_BCN_ERR_FLAG_INVALID_P2 BIT(2) +#define B_AX_BCN_ERR_FLAG_CMP_P2 BIT(1) +#define B_AX_BCN_ERR_FLAG_LOCK_P2 BIT(0) + +#define R_AX_DTIM_CTRL_P2 0xC4A6 +#define R_AX_DTIM_CTRL_P2_C1 0xE4A6 +#define B_AX_DTIM_NUM_P2_SH 8 +#define B_AX_DTIM_NUM_P2_MSK 0xff +#define B_AX_DTIM_CURRCNT_P2_SH 0 +#define B_AX_DTIM_CURRCNT_P2_MSK 0xff + +#define R_AX_TBTT_SHIFT_P2 0xC4A8 +#define R_AX_TBTT_SHIFT_P2_C1 0xE4A8 +#define B_AX_TBTT_SHIFT_OFST_P2_SH 0 +#define B_AX_TBTT_SHIFT_OFST_P2_MSK 0xfff + +#define R_AX_BCN_CNT_TMR_P2 0xC4B4 +#define R_AX_BCN_CNT_TMR_P2_C1 0xE4B4 +#define B_AX_BCN_CNT_TMR_P2_SH 0 +#define B_AX_BCN_CNT_TMR_P2_MSK 0xffffffffL + +#define R_AX_TSFTR_LOW_P2 0xC4B8 +#define R_AX_TSFTR_LOW_P2_C1 0xE4B8 +#define B_AX_TSFTR_LOW_P2_SH 0 +#define B_AX_TSFTR_LOW_P2_MSK 0xffffffffL + +#define R_AX_TSFTR_HIGH_P2 0xC4BC +#define R_AX_TSFTR_HIGH_P2_C1 0xE4BC +#define B_AX_TSFTR_HIGH_P2_SH 0 +#define B_AX_TSFTR_HIGH_P2_MSK 0xffffffffL + +#define R_AX_PORT_CFG_P3 0xC4C0 +#define R_AX_PORT_CFG_P3_C1 0xE4C0 +#define B_AX_BRK_SETUP_P3 BIT(16) +#define B_AX_TBTT_UPD_SHIFT_SEL_P3 BIT(15) +#define B_AX_BCN_DROP_ALLOW_P3 BIT(14) +#define B_AX_TBTT_PROHIB_EN_P3 BIT(13) +#define B_AX_BCNTX_EN_P3 BIT(12) +#define B_AX_NET_TYPE_P3_SH 10 +#define B_AX_NET_TYPE_P3_MSK 0x3 +#define B_AX_BCN_FORCETX_EN_P3 BIT(9) +#define B_AX_TXBCN_BTCCA_EN_P3 BIT(8) +#define B_AX_BCNERR_CNT_EN_P3 BIT(7) +#define B_AX_BCN_AGRES_P3 BIT(6) +#define B_AX_TSFTR_RST_P3 BIT(5) +#define B_AX_RX_BSSID_FIT_EN_P3 BIT(4) +#define B_AX_TSF_UDT_EN_P3 BIT(3) +#define B_AX_PORT_FUNC_EN_P3 BIT(2) +#define B_AX_TXBCN_RPT_EN_P3 BIT(1) +#define B_AX_RXBCN_RPT_EN_P3 BIT(0) + +#define R_AX_BCN_AREA_P3 0xC4C8 +#define R_AX_BCN_AREA_P3_C1 0xE4C8 +#define B_AX_BCN_MSK_AREA_P3_SH 16 +#define B_AX_BCN_MSK_AREA_P3_MSK 0xfff + +#define R_AX_BCNERLYINT_CFG_P3 0xC4CC +#define R_AX_BCNERLYINT_CFG_P3_C1 0xE4CC +#define B_AX_BCNERLY_P3_SH 0 +#define B_AX_BCNERLY_P3_MSK 0xfff + +#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE +#define R_AX_TBTTERLYINT_CFG_P3_C1 0xE4CE +#define B_AX_TBTTERLY_P3_SH 0 +#define B_AX_TBTTERLY_P3_MSK 0xfff + +#define R_AX_TBTT_AGG_P3 0xC4D2 +#define R_AX_TBTT_AGG_P3_C1 0xE4D2 +#define B_AX_TBTT_AGG_NUM_P3_SH 8 +#define B_AX_TBTT_AGG_NUM_P3_MSK 0xff + +#define R_AX_BCN_SPACE_CFG_P3 0xC4D4 +#define R_AX_BCN_SPACE_CFG_P3_C1 0xE4D4 +#define B_AX_BCN_SPACE_P3_SH 0 +#define B_AX_BCN_SPACE_P3_MSK 0xffff + +#define R_AX_BCN_FORCETX_P3 0xC4D8 +#define R_AX_BCN_FORCETX_P3_C1 0xE4D8 +#define B_AX_FORCE_BCN_CURRCNT_P3_SH 16 +#define B_AX_FORCE_BCN_CURRCNT_P3_MSK 0xff +#define B_AX_FORCE_BCN_NUM_P3_SH 8 +#define B_AX_FORCE_BCN_NUM_P3_MSK 0xff +#define B_AX_BCN_MAX_ERR_P3_SH 0 +#define B_AX_BCN_MAX_ERR_P3_MSK 0xff + +#define R_AX_BCN_ERR_CNT_P3 0xC4E0 +#define R_AX_BCN_ERR_CNT_P3_C1 0xE4E0 +#define B_AX_BCN_ERR_CNT_SUM_P3_SH 24 +#define B_AX_BCN_ERR_CNT_SUM_P3_MSK 0xff +#define B_AX_BCN_ERR_CNT_NAV_P3_SH 16 +#define B_AX_BCN_ERR_CNT_NAV_P3_MSK 0xff +#define B_AX_BCN_ERR_CNT_EDCCA_P3_SH 8 +#define B_AX_BCN_ERR_CNT_EDCCA_P3_MSK 0xff +#define B_AX_BCN_ERR_CNT_CCA_P3_SH 0 +#define B_AX_BCN_ERR_CNT_CCA_P3_MSK 0xff + +#define R_AX_BCN_ERR_FLAG_P3 0xC4E4 +#define R_AX_BCN_ERR_FLAG_P3_C1 0xE4E4 +#define B_AX_BCN_ERR_FLAG_OTHERS_P3 BIT(6) +#define B_AX_BCN_ERR_FLAG_MAC_P3 BIT(5) +#define B_AX_BCN_ERR_FLAG_TXON_P3 BIT(4) +#define B_AX_BCN_ERR_FLAG_SRCHEND_P3 BIT(3) +#define B_AX_BCN_ERR_FLAG_INVALID_P3 BIT(2) +#define B_AX_BCN_ERR_FLAG_CMP_P3 BIT(1) +#define B_AX_BCN_ERR_FLAG_LOCK_P3 BIT(0) + +#define R_AX_DTIM_CTRL_P3 0xC4E6 +#define R_AX_DTIM_CTRL_P3_C1 0xE4E6 +#define B_AX_DTIM_NUM_P3_SH 8 +#define B_AX_DTIM_NUM_P3_MSK 0xff +#define B_AX_DTIM_CURRCNT_P3_SH 0 +#define B_AX_DTIM_CURRCNT_P3_MSK 0xff + +#define R_AX_TBTT_SHIFT_P3 0xC4E8 +#define R_AX_TBTT_SHIFT_P3_C1 0xE4E8 +#define B_AX_TBTT_SHIFT_OFST_P3_SH 0 +#define B_AX_TBTT_SHIFT_OFST_P3_MSK 0xfff + +#define R_AX_BCN_CNT_TMR_P3 0xC4F4 +#define R_AX_BCN_CNT_TMR_P3_C1 0xE4F4 +#define B_AX_BCN_CNT_TMR_P3_SH 0 +#define B_AX_BCN_CNT_TMR_P3_MSK 0xffffffffL + +#define R_AX_TSFTR_LOW_P3 0xC4F8 +#define R_AX_TSFTR_LOW_P3_C1 0xE4F8 +#define B_AX_TSFTR_LOW_P3_SH 0 +#define B_AX_TSFTR_LOW_P3_MSK 0xffffffffL + +#define R_AX_TSFTR_HIGH_P3 0xC4FC +#define R_AX_TSFTR_HIGH_P3_C1 0xE4FC +#define B_AX_TSFTR_HIGH_P3_SH 0 +#define B_AX_TSFTR_HIGH_P3_MSK 0xffffffffL + +#define R_AX_PORT_CFG_P4 0xC500 +#define R_AX_PORT_CFG_P4_C1 0xE500 +#define B_AX_BRK_SETUP_P4 BIT(16) +#define B_AX_TBTT_UPD_SHIFT_SEL_P4 BIT(15) +#define B_AX_BCN_DROP_ALLOW_P4 BIT(14) +#define B_AX_TBTT_PROHIB_EN_P4 BIT(13) +#define B_AX_BCNTX_EN_P4 BIT(12) +#define B_AX_NET_TYPE_P4_SH 10 +#define B_AX_NET_TYPE_P4_MSK 0x3 +#define B_AX_BCN_FORCETX_EN_P4 BIT(9) +#define B_AX_TXBCN_BTCCA_EN_P4 BIT(8) +#define B_AX_BCNERR_CNT_EN_P4 BIT(7) +#define B_AX_BCN_AGRES_P4 BIT(6) +#define B_AX_TSFTR_RST_P4 BIT(5) +#define B_AX_RX_BSSID_FIT_EN_P4 BIT(4) +#define B_AX_TSF_UDT_EN_P4 BIT(3) +#define B_AX_PORT_FUNC_EN_P4 BIT(2) +#define B_AX_TXBCN_RPT_EN_P4 BIT(1) +#define B_AX_RXBCN_RPT_EN_P4 BIT(0) + +#define R_AX_BCN_AREA_P4 0xC508 +#define R_AX_BCN_AREA_P4_C1 0xE508 +#define B_AX_BCN_MSK_AREA_P4_SH 16 +#define B_AX_BCN_MSK_AREA_P4_MSK 0xfff + +#define R_AX_BCNERLYINT_CFG_P4 0xC50C +#define R_AX_BCNERLYINT_CFG_P4_C1 0xE50C +#define B_AX_BCNERLY_P4_SH 0 +#define B_AX_BCNERLY_P4_MSK 0xfff + +#define R_AX_TBTTERLYINT_CFG_P4 0xC50E +#define R_AX_TBTTERLYINT_CFG_P4_C1 0xE50E +#define B_AX_TBTTERLY_P4_SH 0 +#define B_AX_TBTTERLY_P4_MSK 0xfff + +#define R_AX_TBTT_AGG_P4 0xC512 +#define R_AX_TBTT_AGG_P4_C1 0xE512 +#define B_AX_TBTT_AGG_NUM_P4_SH 8 +#define B_AX_TBTT_AGG_NUM_P4_MSK 0xff + +#define R_AX_BCN_SPACE_CFG_P4 0xC514 +#define R_AX_BCN_SPACE_CFG_P4_C1 0xE514 +#define B_AX_BCN_SPACE_P4_SH 0 +#define B_AX_BCN_SPACE_P4_MSK 0xffff + +#define R_AX_BCN_FORCETX_P4 0xC518 +#define R_AX_BCN_FORCETX_P4_C1 0xE518 +#define B_AX_FORCE_BCN_CURRCNT_P4_SH 16 +#define B_AX_FORCE_BCN_CURRCNT_P4_MSK 0xff +#define B_AX_FORCE_BCN_NUM_P4_SH 8 +#define B_AX_FORCE_BCN_NUM_P4_MSK 0xff +#define B_AX_BCN_MAX_ERR_P4_SH 0 +#define B_AX_BCN_MAX_ERR_P4_MSK 0xff + +#define R_AX_BCN_ERR_CNT_P4 0xC520 +#define R_AX_BCN_ERR_CNT_P4_C1 0xE520 +#define B_AX_BCN_ERR_CNT_SUM_P4_SH 24 +#define B_AX_BCN_ERR_CNT_SUM_P4_MSK 0xff +#define B_AX_BCN_ERR_CNT_NAV_P4_SH 16 +#define B_AX_BCN_ERR_CNT_NAV_P4_MSK 0xff +#define B_AX_BCN_ERR_CNT_EDCCA_P4_SH 8 +#define B_AX_BCN_ERR_CNT_EDCCA_P4_MSK 0xff +#define B_AX_BCN_ERR_CNT_CCA_P4_SH 0 +#define B_AX_BCN_ERR_CNT_CCA_P4_MSK 0xff + +#define R_AX_BCN_ERR_FLAG_P4 0xC524 +#define R_AX_BCN_ERR_FLAG_P4_C1 0xE524 +#define B_AX_BCN_ERR_FLAG_OTHERS_P4 BIT(6) +#define B_AX_BCN_ERR_FLAG_MAC_P4 BIT(5) +#define B_AX_BCN_ERR_FLAG_TXON_P4 BIT(4) +#define B_AX_BCN_ERR_FLAG_SRCHEND_P4 BIT(3) +#define B_AX_BCN_ERR_FLAG_INVALID_P4 BIT(2) +#define B_AX_BCN_ERR_FLAG_CMP_P4 BIT(1) +#define B_AX_BCN_ERR_FLAG_LOCK_P4 BIT(0) + +#define R_AX_DTIM_CTRL_P4 0xC526 +#define R_AX_DTIM_CTRL_P4_C1 0xE526 +#define B_AX_DTIM_NUM_P4_SH 8 +#define B_AX_DTIM_NUM_P4_MSK 0xff +#define B_AX_DTIM_CURRCNT_P4_SH 0 +#define B_AX_DTIM_CURRCNT_P4_MSK 0xff + +#define R_AX_TBTT_SHIFT_P4 0xC528 +#define R_AX_TBTT_SHIFT_P4_C1 0xE528 +#define B_AX_TBTT_SHIFT_OFST_P4_SH 0 +#define B_AX_TBTT_SHIFT_OFST_P4_MSK 0xfff + +#define R_AX_BCN_CNT_TMR_P4 0xC534 +#define R_AX_BCN_CNT_TMR_P4_C1 0xE534 +#define B_AX_BCN_CNT_TMR_P4_SH 0 +#define B_AX_BCN_CNT_TMR_P4_MSK 0xffffffffL + +#define R_AX_TSFTR_LOW_P4 0xC538 +#define R_AX_TSFTR_LOW_P4_C1 0xE538 +#define B_AX_TSFTR_LOW_P4_SH 0 +#define B_AX_TSFTR_LOW_P4_MSK 0xffffffffL + +#define R_AX_TSFTR_HIGH_P4 0xC53C +#define R_AX_TSFTR_HIGH_P4_C1 0xE53C +#define B_AX_TSFTR_HIGH_P4_SH 0 +#define B_AX_TSFTR_HIGH_P4_MSK 0xffffffffL + +#define R_AX_DTIM_NUM0 0xC540 +#define R_AX_DTIM_NUM0_C1 0xE540 +#define B_AX_DTIM_NUM_P0MB3_SH 24 +#define B_AX_DTIM_NUM_P0MB3_MSK 0xff +#define B_AX_DTIM_NUM_P0MB2_SH 16 +#define B_AX_DTIM_NUM_P0MB2_MSK 0xff +#define B_AX_DTIM_NUM_P0MB1_SH 8 +#define B_AX_DTIM_NUM_P0MB1_MSK 0xff + +#define R_AX_DTIM_NUM1 0xC544 +#define R_AX_DTIM_NUM1_C1 0xE544 +#define B_AX_DTIM_NUM_P0MB7_SH 24 +#define B_AX_DTIM_NUM_P0MB7_MSK 0xff +#define B_AX_DTIM_NUM_P0MB6_SH 16 +#define B_AX_DTIM_NUM_P0MB6_MSK 0xff +#define B_AX_DTIM_NUM_P0MB5_SH 8 +#define B_AX_DTIM_NUM_P0MB5_MSK 0xff +#define B_AX_DTIM_NUM_P0MB4_SH 0 +#define B_AX_DTIM_NUM_P0MB4_MSK 0xff + +#define R_AX_DTIM_NUM2 0xC548 +#define R_AX_DTIM_NUM2_C1 0xE548 +#define B_AX_DTIM_NUM_P0MB11_SH 24 +#define B_AX_DTIM_NUM_P0MB11_MSK 0xff +#define B_AX_DTIM_NUM_P0MB10_SH 16 +#define B_AX_DTIM_NUM_P0MB10_MSK 0xff +#define B_AX_DTIM_NUM_P0MB9_SH 8 +#define B_AX_DTIM_NUM_P0MB9_MSK 0xff +#define B_AX_DTIM_NUM_P0MB8_SH 0 +#define B_AX_DTIM_NUM_P0MB8_MSK 0xff + +#define R_AX_DTIM_NUM3 0xC54C +#define R_AX_DTIM_NUM3_C1 0xE54C +#define B_AX_DTIM_NUM_P0MB15_SH 24 +#define B_AX_DTIM_NUM_P0MB15_MSK 0xff +#define B_AX_DTIM_NUM_P0MB14_SH 16 +#define B_AX_DTIM_NUM_P0MB14_MSK 0xff +#define B_AX_DTIM_NUM_P0MB13_SH 8 +#define B_AX_DTIM_NUM_P0MB13_MSK 0xff +#define B_AX_DTIM_NUM_P0MB12_SH 0 +#define B_AX_DTIM_NUM_P0MB12_MSK 0xff + +#define R_AX_DTIM_CURRCNT0 0xC550 +#define R_AX_DTIM_CURRCNT0_C1 0xE550 +#define B_AX_DTIM_CURRCNT_P0MB3_SH 24 +#define B_AX_DTIM_CURRCNT_P0MB3_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB2_SH 16 +#define B_AX_DTIM_CURRCNT_P0MB2_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB1_SH 8 +#define B_AX_DTIM_CURRCNT_P0MB1_MSK 0xff + +#define R_AX_DTIM_CURRCNT1 0xC554 +#define R_AX_DTIM_CURRCNT1_C1 0xE554 +#define B_AX_DTIM_CURRCNT_P0MB7_SH 24 +#define B_AX_DTIM_CURRCNT_P0MB7_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB6_SH 16 +#define B_AX_DTIM_CURRCNT_P0MB6_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB5_SH 8 +#define B_AX_DTIM_CURRCNT_P0MB5_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB4_SH 0 +#define B_AX_DTIM_CURRCNT_P0MB4_MSK 0xff + +#define R_AX_DTIM_CURRCNT2 0xC558 +#define R_AX_DTIM_CURRCNT2_C1 0xE558 +#define B_AX_DTIM_CURRCNT_P0MB11_SH 24 +#define B_AX_DTIM_CURRCNT_P0MB11_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB10_SH 16 +#define B_AX_DTIM_CURRCNT_P0MB10_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB9_SH 8 +#define B_AX_DTIM_CURRCNT_P0MB9_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB8_SH 0 +#define B_AX_DTIM_CURRCNT_P0MB8_MSK 0xff + +#define R_AX_DTIM_CURRCNT3 0xC55C +#define R_AX_DTIM_CURRCNT3_C1 0xE55C +#define B_AX_DTIM_CURRCNT_P0MB15_SH 24 +#define B_AX_DTIM_CURRCNT_P0MB15_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB14_SH 16 +#define B_AX_DTIM_CURRCNT_P0MB14_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB13_SH 8 +#define B_AX_DTIM_CURRCNT_P0MB13_MSK 0xff +#define B_AX_DTIM_CURRCNT_P0MB12_SH 0 +#define B_AX_DTIM_CURRCNT_P0MB12_MSK 0xff + +#define R_AX_BCN_DROP_ALL0 0xC560 +#define R_AX_BCN_DROP_ALL0_C1 0xE560 +#define B_AX_BCN_DROP_ALL_P4 BIT(4) +#define B_AX_BCN_DROP_ALL_P3 BIT(3) +#define B_AX_BCN_DROP_ALL_P2 BIT(2) +#define B_AX_BCN_DROP_ALL_P1 BIT(1) +#define B_AX_BCN_DROP_ALL_P0 BIT(0) + +#define R_AX_BCN_DROP_ALL0_P0MB 0xC564 +#define R_AX_BCN_DROP_ALL0_P0MB_C1 0xE564 +#define B_AX_BCN_DROP_ALL_P0MB15 BIT(15) +#define B_AX_BCN_DROP_ALL_P0MB14 BIT(14) +#define B_AX_BCN_DROP_ALL_P0MB13 BIT(13) +#define B_AX_BCN_DROP_ALL_P0MB12 BIT(12) +#define B_AX_BCN_DROP_ALL_P0MB11 BIT(11) +#define B_AX_BCN_DROP_ALL_P0MB10 BIT(10) +#define B_AX_BCN_DROP_ALL_P0MB9 BIT(9) +#define B_AX_BCN_DROP_ALL_P0MB8 BIT(8) +#define B_AX_BCN_DROP_ALL_P0MB7 BIT(7) +#define B_AX_BCN_DROP_ALL_P0MB6 BIT(6) +#define B_AX_BCN_DROP_ALL_P0MB5 BIT(5) +#define B_AX_BCN_DROP_ALL_P0MB4 BIT(4) +#define B_AX_BCN_DROP_ALL_P0MB3 BIT(3) +#define B_AX_BCN_DROP_ALL_P0MB2 BIT(2) +#define B_AX_BCN_DROP_ALL_P0MB1 BIT(1) + +#define R_AX_MBSSID_CTRL 0xC568 +#define R_AX_MBSSID_CTRL_C1 0xE568 +#define B_AX_P0MB_NUM_SH 16 +#define B_AX_P0MB_NUM_MSK 0xff +#define B_AX_P0MB15_EN BIT(15) +#define B_AX_P0MB14_EN BIT(14) +#define B_AX_P0MB13_EN BIT(13) +#define B_AX_P0MB12_EN BIT(12) +#define B_AX_P0MB11_EN BIT(11) +#define B_AX_P0MB10_EN BIT(10) +#define B_AX_P0MB9_EN BIT(9) +#define B_AX_P0MB8_EN BIT(8) +#define B_AX_P0MB7_EN BIT(7) +#define B_AX_P0MB6_EN BIT(6) +#define B_AX_P0MB5_EN BIT(5) +#define B_AX_P0MB4_EN BIT(4) +#define B_AX_P0MB3_EN BIT(3) +#define B_AX_P0MB2_EN BIT(2) +#define B_AX_P0MB1_EN BIT(1) + +#define R_AX_RXTSF_OFST 0xC570 +#define R_AX_RXTSF_OFST_C1 0xE570 +#define B_AX_RXTSF_OFST_OFDM_SH 8 +#define B_AX_RXTSF_OFST_OFDM_MSK 0xff +#define B_AX_RXTSF_OFST_CCK_SH 0 +#define B_AX_RXTSF_OFST_CCK_MSK 0xff + +#define R_AX_RXBCN_TIME_CTRL 0xC574 +#define R_AX_RXBCN_TIME_CTRL_C1 0xE574 +#define B_AX_RXBCN_TIME_PORT_SH 28 +#define B_AX_RXBCN_TIME_PORT_MSK 0x7 +#define B_AX_RXBCN_TIME_VLD BIT(17) +#define B_AX_RXBCN_TIME_UDFW BIT(16) +#define B_AX_RXBCN_TIME_DIFF_SH 0 +#define B_AX_RXBCN_TIME_DIFF_MSK 0xffff + +#define R_AX_RXBCN_TIME_SYNC 0xC578 +#define R_AX_RXBCN_TIME_SYNC_C1 0xE578 +#define B_AX_RXBCN_TIME_SYNC_SH 0 +#define B_AX_RXBCN_TIME_SYNC_MSK 0xffffffffL + +#define R_AX_TBTT_TSF_INFO 0xC57C +#define R_AX_TBTT_TSF_INFO_C1 0xE57C +#define B_AX_TBTT_TSF_INFO_SH 0 +#define B_AX_TBTT_TSF_INFO_MSK 0xffffffffL + +#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590 +#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590 +#define B_AX_HGQWND_3_SH 24 +#define B_AX_HGQWND_3_MSK 0xff +#define B_AX_HGQWND_2_SH 16 +#define B_AX_HGQWND_2_MSK 0xff +#define B_AX_HGQWND_1_SH 8 +#define B_AX_HGQWND_1_MSK 0xff +#define B_AX_HGQWND_0_SH 0 +#define B_AX_HGQWND_0_MSK 0xff + +#define R_AX_P0MB_HGQ_WINDOW_CFG_1 0xC594 +#define R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 0xE594 +#define B_AX_HGQWND_7_SH 24 +#define B_AX_HGQWND_7_MSK 0xff +#define B_AX_HGQWND_6_SH 16 +#define B_AX_HGQWND_6_MSK 0xff +#define B_AX_HGQWND_5_SH 8 +#define B_AX_HGQWND_5_MSK 0xff +#define B_AX_HGQWND_4_SH 0 +#define B_AX_HGQWND_4_MSK 0xff + +#define R_AX_P0MB_HGQ_WINDOW_CFG_2 0xC598 +#define R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 0xE598 +#define B_AX_HGQWND_11_SH 24 +#define B_AX_HGQWND_11_MSK 0xff +#define B_AX_HGQWND_10_SH 16 +#define B_AX_HGQWND_10_MSK 0xff +#define B_AX_HGQWND_9_SH 8 +#define B_AX_HGQWND_9_MSK 0xff +#define B_AX_HGQWND_8_SH 0 +#define B_AX_HGQWND_8_MSK 0xff + +#define R_AX_P0MB_HGQ_WINDOW_CFG_3 0xC59C +#define R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 0xE59C +#define B_AX_HGQWND_15_SH 24 +#define B_AX_HGQWND_15_MSK 0xff +#define B_AX_HGQWND_14_SH 16 +#define B_AX_HGQWND_14_MSK 0xff +#define B_AX_HGQWND_13_SH 8 +#define B_AX_HGQWND_13_MSK 0xff +#define B_AX_HGQWND_12_SH 0 +#define B_AX_HGQWND_12_MSK 0xff + +#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0 +#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0 +#define B_AX_HGQWND_19_SH 24 +#define B_AX_HGQWND_19_MSK 0xff +#define B_AX_HGQWND_18_SH 16 +#define B_AX_HGQWND_18_MSK 0xff +#define B_AX_HGQWND_17_SH 8 +#define B_AX_HGQWND_17_MSK 0xff +#define B_AX_HGQWND_16_SH 0 +#define B_AX_HGQWND_16_MSK 0xff + +#define R_AX_EN_HGQ_NOLIMIT 0xC5A4 +#define R_AX_EN_HGQ_NOLIMIT_C1 0xE5A4 +#define B_AX_HIQ_NO_LMT_EN_P4 BIT(19) +#define B_AX_HIQ_NO_LMT_EN_P3 BIT(18) +#define B_AX_HIQ_NO_LMT_EN_P2 BIT(17) +#define B_AX_HIQ_NO_LMT_EN_P1 BIT(16) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP15 BIT(15) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP14 BIT(14) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP13 BIT(13) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP12 BIT(12) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP11 BIT(11) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP10 BIT(10) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP9 BIT(9) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP8 BIT(8) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP7 BIT(7) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP6 BIT(6) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP5 BIT(5) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP4 BIT(4) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP3 BIT(3) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP2 BIT(2) +#define B_AX_HIQ_NO_LMT_EN_P0_VAP1 BIT(1) +#define B_AX_HIQ_NO_LMT_EN_P0_ROOT BIT(0) + +#define R_AX_LPS_RX_PERIOD_CTRL 0xC5B8 +#define R_AX_LPS_RX_PERIOD_CTRL_C1 0xE5B8 +#define B_AX_RXBCN_PERIOD_SH 16 +#define B_AX_RXBCN_PERIOD_MSK 0xff +#define B_AX_CAT_PERIOD_SH 8 +#define B_AX_CAT_PERIOD_MSK 0xff +#define B_AX_LPS_RX_CTRL_EN BIT(3) +#define B_AX_LPS_PORT_SEL_SH 0 +#define B_AX_LPS_PORT_SEL_MSK 0x7 + +#define R_AX_LPS_BCN_CNT 0xC5BC +#define R_AX_LPS_BCN_CNT_C1 0xE5BC +#define B_AX_BCN_TO_ACC_CNT_SH 24 +#define B_AX_BCN_TO_ACC_CNT_MSK 0xff +#define B_AX_BCN_OK_ACC_CNT_SH 16 +#define B_AX_BCN_OK_ACC_CNT_MSK 0xff +#define B_AX_BCN_TO_CNT_THD_SH 8 +#define B_AX_BCN_TO_CNT_THD_MSK 0xff +#define B_AX_BCN_TO_CNT_SH 0 +#define B_AX_BCN_TO_CNT_MSK 0xff + +#define R_AX_FREERUN_CNT_LOW 0xC5C0 +#define R_AX_FREERUN_CNT_LOW_C1 0xE5C0 +#define B_AX_FREERUN_CNT_LOW_SH 0 +#define B_AX_FREERUN_CNT_LOW_MSK 0xffffffffL + +#define R_AX_FREERUN_CNT_HIGH 0xC5C4 +#define R_AX_FREERUN_CNT_HIGH_C1 0xE5C4 +#define B_AX_FREERUN_CNT_HIGH_SH 0 +#define B_AX_FREERUN_CNT_HIGH_MSK 0xffffffffL + +#define R_AX_PSTIMER0 0xC5CC +#define R_AX_PSTIMER0_C1 0xE5CC +#define B_AX_PSTIMER0_VAL_SH 0 +#define B_AX_PSTIMER0_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER1 0xC23D +#define R_AX_PSTIMER1_C1 0xE23D +#define B_AX_PSTIMER1_VAL_SH 0 +#define B_AX_PSTIMER1_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER2 0xC5D4 +#define R_AX_PSTIMER2_C1 0xE5D4 +#define B_AX_PSTIMER2_VAL_SH 0 +#define B_AX_PSTIMER2_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER3 0xC5D8 +#define R_AX_PSTIMER3_C1 0xE5D8 +#define B_AX_PSTIMER3_VAL_SH 0 +#define B_AX_PSTIMER3_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER4 0xC5DC +#define R_AX_PSTIMER4_C1 0xE5DC +#define B_AX_PSTIMER4_VAL_SH 0 +#define B_AX_PSTIMER4_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER5 0xC5E0 +#define R_AX_PSTIMER5_C1 0xE5E0 +#define B_AX_PSTIMER5_VAL_SH 0 +#define B_AX_PSTIMER5_VAL_MSK 0xffffffffL + +#define R_AX_PSTIMER_CTRL 0xC5E4 +#define R_AX_PSTIMER_CTRL_C1 0xE5E4 +#define B_AX_PSTIMER5_EN BIT(23) +#define B_AX_PSTIMER5_SEL_SH 20 +#define B_AX_PSTIMER5_SEL_MSK 0x7 +#define B_AX_PSTIMER4_EN BIT(19) +#define B_AX_PSTIMER4_SEL_SH 16 +#define B_AX_PSTIMER4_SEL_MSK 0x7 +#define B_AX_PSTIMER3_EN BIT(15) +#define B_AX_PSTIMER3_SEL_SH 12 +#define B_AX_PSTIMER3_SEL_MSK 0x7 +#define B_AX_PSTIMER2_EN BIT(11) +#define B_AX_PSTIMER2_SEL_SH 8 +#define B_AX_PSTIMER2_SEL_MSK 0x7 +#define B_AX_PSTIMER1_EN BIT(7) +#define B_AX_PSTIMER1_SEL_SH 4 +#define B_AX_PSTIMER1_SEL_MSK 0x7 +#define B_AX_PSTIMER0_EN BIT(3) +#define B_AX_PSTIMER0_SEL_SH 0 +#define B_AX_PSTIMER0_SEL_MSK 0x7 + +#define R_AX_TIMER_COMPARE 0xC5E8 +#define R_AX_TIMER_COMPARE_C1 0xE5E8 +#define B_AX_X_COMP_Y_TSFT_P BIT(7) +#define B_AX_Y_COMP_SEL_SH 4 +#define B_AX_Y_COMP_SEL_MSK 0x7 +#define B_AX_X_COMP_Y_OVER BIT(3) +#define B_AX_X_COMP_SEL_SH 0 +#define B_AX_X_COMP_SEL_MSK 0x7 + +#define R_AX_TIMER_COMPARE_VALUE_LOW 0xC5EC +#define R_AX_TIMER_COMPARE_VALUE_LOW_C1 0xE5EC +#define B_AX_X_COMP_Y_VAL_LOW_SH 0 +#define B_AX_X_COMP_Y_VAL_LOW_MSK 0xffffffffL + +#define R_AX_TIMER_COMPARE_VALUE_HIGH 0xC5F0 +#define R_AX_TIMER_COMPARE_VALUE_HIGH_C1 0xE5F0 +#define B_AX_X_COMP_Y_VAL_HIGH_SH 0 +#define B_AX_X_COMP_Y_VAL_HIGH_MSK 0xffffffffL + +// +// PTCL +// + +#define R_AX_PTCL_COMMON_SETTING_0 0xC600 +#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600 +#define B_AX_CPUMGQ_LIFETIME_EN BIT(8) +#define B_AX_MGQ_LIFETIME_EN BIT(7) +#define B_AX_LIFETIME_EN BIT(6) +#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4) +#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3) +#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2) +#define B_AX_CMAC_TX_MODE_1 BIT(1) +#define B_AX_CMAC_TX_MODE_0 BIT(0) + +#define R_AX_AGG_BK_0 0xC604 +#define R_AX_AGG_BK_0_C1 0xE604 +#define B_AX_DIS_SND_STS_CHECK BIT(7) +#define B_AX_NAV_PAUS_PHB_EN BIT(6) +#define B_AX_TXOP_SHT_PHB_EN BIT(5) +#define B_AX_AGG_BRK_PHB_EN BIT(4) +#define B_AX_DIS_SSN_CHK BIT(3) +#define B_AX_WDBK_CFG BIT(2) +#define B_AX_EN_RTY_BK BIT(1) +#define B_AX_EN_RTY_BK_COD BIT(0) + +#define R_AX_TX_CTRL 0xC608 +#define R_AX_TX_CTRL_C1 0xE608 +#define B_AX_DROP_CHK_MAX_NUM_SH 24 +#define B_AX_DROP_CHK_MAX_NUM_MSK 0xff +#define B_AX_DROP_CHK_TIMEOUT_SH 20 +#define B_AX_DROP_CHK_TIMEOUT_MSK 0xf +#define B_AX_FWD_SRCH_TIMEOUT_SH 16 +#define B_AX_FWD_SRCH_TIMEOUT_MSK 0xf +#define B_AX_PTCL_STOP_WMM BIT(7) +#define B_AX_TXOP_DELAY_TX_SH 0 +#define B_AX_TXOP_DELAY_TX_MSK 0x1f + +#define R_AX_TB_PPDU_CTRL 0xC60C +#define R_AX_TB_PPDU_CTRL_C1 0xE60C +#define B_AX_TB_PPDU_BK_DIS BIT(15) +#define B_AX_TB_PPDU_BE_DIS BIT(14) +#define B_AX_TB_PPDU_VI_DIS BIT(13) +#define B_AX_TB_PPDU_VO_DIS BIT(12) +#define B_AX_TB_BYPASS_TXPWR BIT(2) +#define B_AX_SW_PREFER_AC_SH 0 +#define B_AX_SW_PREFER_AC_MSK 0x3 + +#define R_AX_AMPDU_AGG_LIMIT 0xC610 +#define R_AX_AMPDU_AGG_LIMIT_C1 0xE610 +#define B_AX_AMPDU_MAX_TIME_SH 24 +#define B_AX_AMPDU_MAX_TIME_MSK 0xff +#define B_AX_RA_TRY_RATE_AGG_LMT_SH 16 +#define B_AX_RA_TRY_RATE_AGG_LMT_MSK 0xff +#define B_AX_RTS_MAX_AGG_NUM_SH 8 +#define B_AX_RTS_MAX_AGG_NUM_MSK 0xff +#define B_AX_MAX_AGG_NUM_SH 0 +#define B_AX_MAX_AGG_NUM_MSK 0xff + +#define R_AX_AGG_LEN_HT_0 0xC614 +#define R_AX_AGG_LEN_HT_0_C1 0xE614 +#define B_AX_AMPDU_MAX_LEN_HT_SH 16 +#define B_AX_AMPDU_MAX_LEN_HT_MSK 0xffff +#define B_AX_RTS_TXTIME_TH_SH 8 +#define B_AX_RTS_TXTIME_TH_MSK 0xff +#define B_AX_RTS_LEN_TH_SH 0 +#define B_AX_RTS_LEN_TH_MSK 0xff + +#define R_AX_AGG_LEN_VHT_0 0xC618 +#define R_AX_AGG_LEN_VHT_0_C1 0xE618 +#define B_AX_AMPDU_MAX_LEN_VHT_SH 0 +#define B_AX_AMPDU_MAX_LEN_VHT_MSK 0xfffff + +#define R_AX_AGG_LEN_HE_0 0xC61C +#define R_AX_AGG_LEN_HE_0_C1 0xE61C +#define B_AX_AMPDU_MAX_LEN_HE_SH 0 +#define B_AX_AMPDU_MAX_LEN_HE_MSK 0x7fffff + +#define R_AX_SPECIAL_TX_SETTING 0xC620 +#define R_AX_SPECIAL_TX_SETTING_C1 0xE620 +#define B_AX_USE_DATA_BW BIT(29) +#define B_AX_BW_SIGTA_SH 27 +#define B_AX_BW_SIGTA_MSK 0x3 +#define B_AX_BMC_NAV_PROTECT BIT(26) +#define B_AX_STBC_CFEND_SH 18 +#define B_AX_STBC_CFEND_MSK 0x3 +#define B_AX_STBC_CFEND_RATE_SH 9 +#define B_AX_STBC_CFEND_RATE_MSK 0x1ff +#define B_AX_BASIC_CFEND_RATE_SH 0 +#define B_AX_BASIC_CFEND_RATE_MSK 0x1ff + +#define R_AX_SIFS_SETTING 0xC624 +#define R_AX_SIFS_SETTING_C1 0xE624 +#define B_AX_HW_CTS2SELF_PKT_LEN_TH_SH 24 +#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MSK 0xff +#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_SH 18 +#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MSK 0x3f +#define B_AX_HW_CTS2SELF_EN BIT(16) +#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 +#define B_AX_SPEC_SIFS_OFDM_PTCL_MSK 0xff +#define B_AX_SPEC_SIFS_CCK_PTCL_SH 0 +#define B_AX_SPEC_SIFS_CCK_PTCL_MSK 0xff + +#define R_AX_TXRATE_CHK 0xC628 +#define R_AX_TXRATE_CHK_C1 0xE628 +#define B_AX_DEFT_RATE_SH 7 +#define B_AX_DEFT_RATE_MSK 0x1ff +#define B_AX_BAND_MODE BIT(4) +#define B_AX_MAX_TXNSS_SH 2 +#define B_AX_MAX_TXNSS_MSK 0x3 +#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) +#define B_AX_CHECK_CCK_EN BIT(0) + +#define R_AX_TXCNT 0xC62C +#define R_AX_TXCNT_C1 0xE62C +#define B_AX_ADD_TXCNT_BY BIT(31) +#define B_AX_S_TXCNT_LMT_SH 24 +#define B_AX_S_TXCNT_LMT_MSK 0x3f +#define B_AX_L_TXCNT_LMT_SH 16 +#define B_AX_L_TXCNT_LMT_MSK 0x3f + +#define R_AX_LIFETIME_0 0xC630 +#define R_AX_LIFETIME_0_C1 0xE630 +#define B_AX_PKT_LIFETIME_2_SH 16 +#define B_AX_PKT_LIFETIME_2_MSK 0xffff +#define B_AX_PKT_LIFETIME_1_SH 0 +#define B_AX_PKT_LIFETIME_1_MSK 0xffff + +#define R_AX_LIFETIME_1 0xC634 +#define R_AX_LIFETIME_1_C1 0xE634 +#define B_AX_PKT_LIFETIME_4_SH 16 +#define B_AX_PKT_LIFETIME_4_MSK 0xffff +#define B_AX_PKT_LIFETIME_3_SH 0 +#define B_AX_PKT_LIFETIME_3_MSK 0xffff + +#define R_AX_LIFETIME_2 0xC638 +#define R_AX_LIFETIME_2_C1 0xE638 +#define B_AX_CPUMGQ_LIFETIME_SH 16 +#define B_AX_CPUMGQ_LIFETIME_MSK 0xffff +#define B_AX_MGQ_LIFETIME_SH 0 +#define B_AX_MGQ_LIFETIME_MSK 0xffff + +#define R_AX_MBSSID_DROP_0 0xC63C +#define R_AX_MBSSID_DROP_0_C1 0xE63C +#define B_AX_GI_LTF_FB_SEL BIT(30) +#define B_AX_RATE_SEL_SH 24 +#define B_AX_RATE_SEL_MSK 0x3f +#define B_AX_PORT_DROP_4_0_SH 16 +#define B_AX_PORT_DROP_4_0_MSK 0x1f +#define B_AX_MBSSID_DROP_15_0_SH 0 +#define B_AX_MBSSID_DROP_15_0_MSK 0xffff + +#define R_AX_ARFR_WT_0 0xC640 +#define R_AX_ARFR_WT_0_C1 0xE640 +#define B_AX_RATE7_WEIGHTING_SH 28 +#define B_AX_RATE7_WEIGHTING_MSK 0xf +#define B_AX_RATE6_WEIGHTING_SH 24 +#define B_AX_RATE6_WEIGHTING_MSK 0xf +#define B_AX_RATE5_WEIGHTING_SH 20 +#define B_AX_RATE5_WEIGHTING_MSK 0xf +#define B_AX_RATE4_WEIGHTING_SH 16 +#define B_AX_RATE4_WEIGHTING_MSK 0xf +#define B_AX_RATE3_WEIGHTING_SH 12 +#define B_AX_RATE3_WEIGHTING_MSK 0xf +#define B_AX_RATE2_WEIGHTING_SH 8 +#define B_AX_RATE2_WEIGHTING_MSK 0xf +#define B_AX_RATE1_WEIGHTING_SH 4 +#define B_AX_RATE1_WEIGHTING_MSK 0xf +#define B_AX_RATE0_WEIGHTING_SH 0 +#define B_AX_RATE0_WEIGHTING_MSK 0xf + +#define R_AX_DARF_TC 0xC648 +#define R_AX_DARF_TC_C1 0xE648 +#define B_AX_DARF_TC9_SH 28 +#define B_AX_DARF_TC9_MSK 0xf +#define B_AX_DARF_TC8_SH 24 +#define B_AX_DARF_TC8_MSK 0xf +#define B_AX_DARF_TC7_SH 20 +#define B_AX_DARF_TC7_MSK 0xf +#define B_AX_DARF_TC6_SH 16 +#define B_AX_DARF_TC6_MSK 0xf +#define B_AX_DARF_TC5_SH 12 +#define B_AX_DARF_TC5_MSK 0xf +#define B_AX_DARF_TC4_SH 8 +#define B_AX_DARF_TC4_MSK 0xf +#define B_AX_DARF_TC3_SH 4 +#define B_AX_DARF_TC3_MSK 0xf +#define B_AX_DARF_TC2_SH 0 +#define B_AX_DARF_TC2_MSK 0xf + +#define R_AX_DARF1_TC 0xC64C +#define R_AX_DARF1_TC_C1 0xE64C +#define B_AX_DARF1_TC9_SH 28 +#define B_AX_DARF1_TC9_MSK 0xf +#define B_AX_DARF1_TC8_SH 24 +#define B_AX_DARF1_TC8_MSK 0xf +#define B_AX_DARF1_TC7_SH 20 +#define B_AX_DARF1_TC7_MSK 0xf +#define B_AX_DARF1_TC6_SH 16 +#define B_AX_DARF1_TC6_MSK 0xf +#define B_AX_DARF1_TC5_SH 12 +#define B_AX_DARF1_TC5_MSK 0xf +#define B_AX_DARF1_TC4_SH 8 +#define B_AX_DARF1_TC4_MSK 0xf +#define B_AX_DARF1_TC3_SH 4 +#define B_AX_DARF1_TC3_MSK 0xf +#define B_AX_DARF1_TC2_SH 0 +#define B_AX_DARF1_TC2_MSK 0xf + +#define R_AX_RARF_TC 0xC650 +#define R_AX_RARF_TC_C1 0xE650 +#define B_AX_RARF_TC9_SH 28 +#define B_AX_RARF_TC9_MSK 0xf +#define B_AX_RARF_TC8_SH 24 +#define B_AX_RARF_TC8_MSK 0xf +#define B_AX_RARF_TC7_SH 20 +#define B_AX_RARF_TC7_MSK 0xf +#define B_AX_RARF_TC6_SH 16 +#define B_AX_RARF_TC6_MSK 0xf +#define B_AX_RARF_TC5_SH 12 +#define B_AX_RARF_TC5_MSK 0xf +#define B_AX_RARF_TC4_SH 8 +#define B_AX_RARF_TC4_MSK 0xf +#define B_AX_RARF_TC3_SH 4 +#define B_AX_RARF_TC3_MSK 0xf +#define B_AX_RARF_TC2_SH 0 +#define B_AX_RARF_TC2_MSK 0xf + +#define R_AX_PTCL_ATM 0xC654 +#define R_AX_PTCL_ATM_C1 0xE654 +#define B_AX_CHNL_REF_RX_BASIC_NAV BIT(31) +#define B_AX_CHNL_REF_RX_INTRA_NAV BIT(30) +#define B_AX_CHNL_REF_DATA_ON BIT(29) +#define B_AX_CHNL_REF_EDCCA_P20 BIT(28) +#define B_AX_CHNL_REF_CCA_P20 BIT(27) +#define B_AX_CHNL_REF_CCA_S20 BIT(26) +#define B_AX_CHNL_REF_CCA_S40 BIT(25) +#define B_AX_CHNL_REF_CCA_S80 BIT(24) +#define B_AX_CHNL_REF_PHY_TXON BIT(23) +#define B_AX_RST_CHNL_BUSY BIT(19) +#define B_AX_RST_CHNL_IDLE BIT(18) +#define B_AX_CHNL_INFO_EN BIT(17) +#define B_AX_ATM_AIRTIME_EN BIT(16) +#define B_AX_ATM_TF_UD BIT(12) +#define B_AX_ATM_SR_UD_1_SH 10 +#define B_AX_ATM_SR_UD_1_MSK 0x3 +#define B_AX_ATM_SR_UD_0_SH 8 +#define B_AX_ATM_SR_UD_0_MSK 0x3 +#define B_AX_ATM_TB_UD_1_SH 6 +#define B_AX_ATM_TB_UD_1_MSK 0x3 +#define B_AX_ATM_TB_UD_0_SH 4 +#define B_AX_ATM_TB_UD_0_MSK 0x3 +#define B_AX_ATM_TX_UD_1_SH 2 +#define B_AX_ATM_TX_UD_1_MSK 0x3 +#define B_AX_ATM_TX_UD_0_SH 0 +#define B_AX_ATM_TX_UD_0_MSK 0x3 + +#define R_AX_CHNL_IDLE_TIME_0 0xC658 +#define R_AX_CHNL_IDLE_TIME_0_C1 0xE658 +#define B_AX_CHNL_IDLE_TIME_SH 0 +#define B_AX_CHNL_IDLE_TIME_MSK 0xffffffffL + +#define R_AX_CHNL_BUSY_TIME_0 0xC65C +#define R_AX_CHNL_BUSY_TIME_0_C1 0xE65C +#define B_AX_CHNL_BUSY_TIME_SH 0 +#define B_AX_CHNL_BUSY_TIME_MSK 0xffffffffL + +#define R_AX_PTCLRPT_FULL_HDL 0xC660 +#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660 +#define B_AX_F2PCMD_RPT_EN BIT(8) +#define B_AX_BCN_RPT_PATH_SH 6 +#define B_AX_BCN_RPT_PATH_MSK 0x3 +#define B_AX_SPE_RPT_PATH_SH 4 +#define B_AX_SPE_RPT_PATH_MSK 0x3 +#define B_AX_TX_RPT_PATH_SH 2 +#define B_AX_TX_RPT_PATH_MSK 0x3 +#define B_AX_F2PCMDRPT_FULL_DROP BIT(1) +#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0) + +#define R_AX_PTCL_TXOP_BK 0xC670 +#define R_AX_PTCL_TXOP_BK_C1 0xE670 +#define B_AX_DIS_TXOP_CFE BIT(31) +#define B_AX_DIS_LSIG_CFE BIT(30) +#define B_AX_TXOP_BK_PKT_NUM_SH 12 +#define B_AX_TXOP_BK_PKT_NUM_MSK 0x3f +#define B_AX_TXOP_BK_TX_TIME_SH 4 +#define B_AX_TXOP_BK_TX_TIME_MSK 0xff +#define B_AX_TXOP_BK_EN_SH 0 +#define B_AX_TXOP_BK_EN_MSK 0xf +#define B_AX_SPEC_MBA_HE_PTCL_SH 16 +#define B_AX_SPEC_MBA_HE_PTCL_MSK 0xffff +#define B_AX_NAV_PROT_LEN_SH 0 +#define B_AX_NAV_PROT_LEN_MSK 0xffff + +#define R_AX_PROT_0 0xC674 +#define R_AX_PROT_0_C1 0xE674 +#define B_AX_SPEC_MBA_HE_PTCL_SH 16 +#define B_AX_SPEC_MBA_HE_PTCL_MSK 0xffff +#define B_AX_NAV_PROT_LEN_SH 0 +#define B_AX_NAV_PROT_LEN_MSK 0xffff + +#define R_AX_PROT 0xC678 +#define R_AX_PROT_C1 0xE678 +#define B_AX_NAV_OVER_TXOP_EN BIT(16) +#define B_AX_NAV_PROT_LEN_CTN_MODE_SH 0 +#define B_AX_NAV_PROT_LEN_CTN_MODE_MSK 0xffff + +#define R_AX_BT_PLT 0xC67C +#define R_AX_BT_PLT_C1 0xE67C +#define B_AX_BT_PLT_PKT_CNT_SH 16 +#define B_AX_BT_PLT_PKT_CNT_MSK 0xffff +#define B_AX_BT_PLT_RST BIT(9) +#define B_AX_PLT_EN BIT(8) +#define B_AX_RX_PLT_GNT_LTE_RX BIT(7) +#define B_AX_RX_PLT_GNT_BT_RX BIT(6) +#define B_AX_RX_PLT_GNT_BT_TX BIT(5) +#define B_AX_RX_PLT_GNT_WL BIT(4) +#define B_AX_TX_PLT_GNT_LTE_RX BIT(3) +#define B_AX_TX_PLT_GNT_BT_RX BIT(2) +#define B_AX_TX_PLT_GNT_BT_TX BIT(1) +#define B_AX_TX_PLT_GNT_WL BIT(0) + +#define R_AX_TWTQ_CTRL1 0xC680 +#define R_AX_TWTQ_CTRL1_C1 0xE680 +#define B_AX_TWTQ_ULTRHD_SH 16 +#define B_AX_TWTQ_ULTRHD_MSK 0xffff +#define B_AX_TWTQ_TXOPTRHD_SH 0 +#define B_AX_TWTQ_TXOPTRHD_MSK 0xffff + +#define R_AX_TWTQ_CTRL2 0xC684 +#define R_AX_TWTQ_CTRL2_C1 0xE684 +#define B_AX_TWTQ_AGGTRHD_SH 0 +#define B_AX_TWTQ_AGGTRHD_MSK 0xffff + +#define R_AX_BCNQ_CTRL 0xC690 +#define R_AX_BCNQ_CTRL_C1 0xE690 +#define B_AX_BCNQ_LOCK_STUS BIT(31) +#define B_AX_BCNQ_LOCK BIT(0) + +#define R_AX_PTCL_BSS_COLOR_0 0xC6A0 +#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 +#define B_AX_BSS_COLOB_AX_PORT_3_SH 24 +#define B_AX_BSS_COLOB_AX_PORT_3_MSK 0x3f +#define B_AX_BSS_COLOB_AX_PORT_2_SH 16 +#define B_AX_BSS_COLOB_AX_PORT_2_MSK 0x3f +#define B_AX_BSS_COLOB_AX_PORT_1_SH 8 +#define B_AX_BSS_COLOB_AX_PORT_1_MSK 0x3f +#define B_AX_BSS_COLOB_AX_PORT_0_SH 0 +#define B_AX_BSS_COLOB_AX_PORT_0_MSK 0x3f + +#define R_AX_PTCL_BSS_COLOR_1 0xC6A4 +#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 +#define B_AX_BSS_COLOB_AX_PORT_4_SH 0 +#define B_AX_BSS_COLOB_AX_PORT_4_MSK 0x3f + +#define R_AX_PTCL_F2P_TX_SETTING 0xC6B0 +#define R_AX_PTCL_F2P_TX_SETTING_C1 0xE6B0 +#define B_AX_TF_DATA_TF_LENGTH_SH 0 +#define B_AX_TF_DATA_TF_LENGTH_MSK 0xff + +#define R_AX_PTCL_IMR0 0xC6C0 +#define R_AX_PTCL_IMR0_C1 0xE6C0 +#define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31) +#define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30) +#define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29) +#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) +#define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27) +#define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26) +#define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25) +#define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24) +#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) +#define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15) +#define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14) +#define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12) +#define B_AX_Q_PKTID_ERR_INT_EN BIT(11) +#define B_AX_D_PKTID_ERR_INT_EN BIT(10) +#define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9) +#define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8) +#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) + +#define R_AX_PTCL_ISR0 0xC6C4 +#define R_AX_PTCL_ISR0_C1 0xE6C4 +#define B_AX_F2PCMD_PKTID_ERR BIT(31) +#define B_AX_F2PCMD_RD_PKTID_ERR BIT(30) +#define B_AX_F2PCMD_ASSIGN_PKTID_ERR BIT(29) +#define B_AX_F2PCMD_USER_ALLC_ERR BIT(28) +#define B_AX_RX_SPF_U0_PKTID_ERR BIT(27) +#define B_AX_TX_SPF_U1_PKTID_ERR BIT(26) +#define B_AX_TX_SPF_U2_PKTID_ERR BIT(25) +#define B_AX_TX_SPF_U3_PKTID_ERR BIT(24) +#define B_AX_TX_RECORD_PKTID_ERR BIT(23) +#define B_AX_F2PCMD_EMPTY_ERR BIT(15) +#define B_AX_TWTSP_QSEL_ERR BIT(14) +#define B_AX_BCNQ_ORDER_ERR BIT(12) +#define B_AX_Q_PKTID_ERR BIT(11) +#define B_AX_D_PKTID_ERR BIT(10) +#define B_AX_TXPRT_FULL_DROP_ERR BIT(9) +#define B_AX_F2PCMDRPT_FULL_DROP_ERR BIT(8) +#define B_AX_FSM_TIMEOUT_ERR BIT(0) + +#define R_AX_PTCL_RST_CTRL 0xC6E0 +#define R_AX_PTCL_RST_CTRL_C1 0xE6E0 +#define B_AX_PTCL_TX_FINISH_REQ_STATUS BIT(24) +#define B_AX_PTCL_WDE_EN BIT(1) +#define B_AX_PTCL_TX_FINISH_REQ BIT(0) + +#define R_AX_PTCL_FSM_MON 0xC6E8 +#define R_AX_PTCL_FSM_MON_C1 0xE6E8 +#define B_AX_PTCL_FSM2_TO_MODE BIT(30) +#define B_AX_PTCL_FSM2_TO_THR_SH 24 +#define B_AX_PTCL_FSM2_TO_THR_MSK 0x3f +#define B_AX_PTCL_FSM1_TO_MODE BIT(22) +#define B_AX_PTCL_FSM1_TO_THR_SH 16 +#define B_AX_PTCL_FSM1_TO_THR_MSK 0x3f +#define B_AX_PTCL_FSM0_TO_MODE BIT(14) +#define B_AX_PTCL_FSM0_TO_THR_SH 8 +#define B_AX_PTCL_FSM0_TO_THR_MSK 0x3f +#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) +#define B_AX_PTCL_TX_ARB_TO_THR_SH 0 +#define B_AX_PTCL_TX_ARB_TO_THR_MSK 0x3f + +#define R_AX_PTCL_TX_CTN_SEL 0xC6EC +#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC +#define B_AX_PTCL_TX_ON_STAT BIT(7) +#define B_AX_PTCL_DROP BIT(5) +#define B_AX_PTCL_TX_QUEUE_IDX_SH 0 +#define B_AX_PTCL_TX_QUEUE_IDX_MSK 0x1f + +#define R_AX_PTCL_DBG_INFO 0xC6F0 +#define R_AX_PTCL_DBG_INFO_C1 0xE6F0 +#define B_AX_PTCL_DBG_INFO_SH 0 +#define B_AX_PTCL_DBG_INFO_MSK 0xffffffffL + +#define R_AX_NULL_PKT_STATUS 0xC6F6 +#define R_AX_NULL_PKT_STATUS_C1 0xE6F6 +#define B_AX_P4_NULL_1_STATUS BIT(9) +#define B_AX_P4_NULL_0_STATUS BIT(8) +#define B_AX_P3_NULL_1_STATUS BIT(7) +#define B_AX_P3_NULL_0_STATUS BIT(6) +#define B_AX_P2_NULL_1_STATUS BIT(5) +#define B_AX_P2_NULL_0_STATUS BIT(4) +#define B_AX_P1_NULL_1_STATUS BIT(3) +#define B_AX_P1_NULL_0_STATUS BIT(2) +#define B_AX_P0_NULL_1_STATUS BIT(1) +#define B_AX_P0_NULL_0_STATUS BIT(0) + +#define R_AX_PTCL_DBG 0xC6F4 +#define R_AX_PTCL_DBG_C1 0xE6F4 +#define B_AX_PTCL_DBG_EN BIT(8) +#define B_AX_PTCL_DBG_SEL_SH 0 +#define B_AX_PTCL_DBG_SEL_MSK 0xff + +#define R_AX_PTCL_TX_MACID_0 0xC6FC +#define R_AX_PTCL_TX_MACID_0_C1 0xE6FC +#define B_AX_TX_MACID_3_SH 24 +#define B_AX_TX_MACID_3_MSK 0xff +#define B_AX_TX_MACID_2_SH 16 +#define B_AX_TX_MACID_2_MSK 0xff +#define B_AX_TX_MACID_1_SH 8 +#define B_AX_TX_MACID_1_MSK 0xff +#define B_AX_TX_MACID_0_SH 0 +#define B_AX_TX_MACID_0_MSK 0xff + +// +// CMAC_DMA 8852C +// + +#define R_AX_RX_CTRL2 0xC810 +#define R_AX_RX_CTRL2_C1 0xE810 +#define B_AX_DLE_WDE_STATE_V1_SH 30 +#define B_AX_DLE_WDE_STATE_V1_MSK 0x3 +#define B_AX_DLE_PLE_STATE_V1_SH 28 +#define B_AX_DLE_PLE_STATE_V1_MSK 0x3 +#define B_AX_DLE_REQ_BUF_STATE_SH 26 +#define B_AX_DLE_REQ_BUF_STATE_MSK 0x3 +#define B_AX_DLE_ENQ_STATE_V1 BIT(25) +#define B_AX_RX_DBG_SEL_SH 19 +#define B_AX_RX_DBG_SEL_MSK 0x3f +#define B_AX_MACRX_CS_SH 14 +#define B_AX_MACRX_CS_MSK 0x1f +#define B_AX_RXSTS_CS_SH 9 +#define B_AX_RXSTS_CS_MSK 0x1f +#define B_AX_ERR_INDICATOR BIT(5) +#define B_AX_TXRPT_CS_SH 0 +#define B_AX_TXRPT_CS_MSK 0x1f + +#define R_AX_RX_INFO_RU0RU1 0xC814 +#define R_AX_RX_INFO_RU0RU1_C1 0xE814 +#define B_AX_RU1_IS_IDLE BIT(31) +#define B_AX_RU1_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU1_IS_REQ_BUF BIT(29) +#define B_AX_RU1_IS_ENQ BIT(28) +#define B_AX_RU1_WR_PKT_ID_SH 16 +#define B_AX_RU1_WR_PKT_ID_MSK 0xfff +#define B_AX_RU0_IS_IDLE BIT(15) +#define B_AX_RU0_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU0_IS_REQ_BUF BIT(13) +#define B_AX_RU0_IS_ENQ BIT(12) +#define B_AX_RU0_WR_PKT_ID_SH 0 +#define B_AX_RU0_WR_PKT_ID_MSK 0xfff + +#define R_AX_RX_INFO_RU2RU3 0xC818 +#define R_AX_RX_INFO_RU2RU3_C1 0xE818 +#define B_AX_RU3_IS_IDLE BIT(31) +#define B_AX_RU3_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU3_IS_REQ_BUF BIT(29) +#define B_AX_RU3_IS_ENQ BIT(28) +#define B_AX_RU3_WR_PKT_ID_SH 16 +#define B_AX_RU3_WR_PKT_ID_MSK 0xfff +#define B_AX_RU2_IS_IDLE BIT(15) +#define B_AX_RU2_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU2_IS_REQ_BUF BIT(13) +#define B_AX_RU2_IS_ENQ BIT(12) +#define B_AX_RU2_WR_PKT_ID_SH 0 +#define B_AX_RU2_WR_PKT_ID_MSK 0xfff + +#define R_AX_RX_INFO_RU4RU5 0xC81C +#define R_AX_RX_INFO_RU4RU5_C1 0xE81C +#define B_AX_RU5_IS_IDLE BIT(31) +#define B_AX_RU5_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU5_IS_REQ_BUF BIT(29) +#define B_AX_RU5_IS_ENQ BIT(28) +#define B_AX_RU5_WR_PKT_ID_SH 16 +#define B_AX_RU5_WR_PKT_ID_MSK 0xfff +#define B_AX_RU4_IS_IDLE BIT(15) +#define B_AX_RU4_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU4_IS_REQ_BUF BIT(13) +#define B_AX_RU4_IS_ENQ BIT(12) +#define B_AX_RU4_WR_PKT_ID_SH 0 +#define B_AX_RU4_WR_PKT_ID_MSK 0xfff + +#define R_AX_RX_INFO_RU6RU7 0xC820 +#define R_AX_RX_INFO_RU6RU7_C1 0xE820 +#define B_AX_RU7_IS_IDLE BIT(31) +#define B_AX_RU7_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU7_IS_REQ_BUF BIT(29) +#define B_AX_RU7_IS_ENQ BIT(28) +#define B_AX_RU7_WR_PKT_ID_SH 16 +#define B_AX_RU7_WR_PKT_ID_MSK 0xfff +#define B_AX_RU6_IS_IDLE BIT(15) +#define B_AX_RU6_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU6_IS_REQ_BUF BIT(13) +#define B_AX_RU6_IS_ENQ BIT(12) +#define B_AX_RU6_WR_PKT_ID_SH 0 +#define B_AX_RU6_WR_PKT_ID_MSK 0xfff + +#define R_AX_RX_INFO_F2P_TXRPT 0xC824 +#define R_AX_RX_INFO_F2P_TXRPT_C1 0xE824 +#define B_AX_F2PCMD_IS_IDLE_V1 BIT(31) +#define B_AX_F2PCMD_RXDATA_RECOVER_MANNUL_V1 BIT(30) +#define B_AX_F2PCMD_IS_REQ_BUF BIT(29) +#define B_AX_F2PCMD_IS_ENQ BIT(28) +#define B_AX_F2PCMD_WR_PKT_ID_V1_SH 16 +#define B_AX_F2PCMD_WR_PKT_ID_V1_MSK 0xfff +#define B_AX_TXRPT_IS_IDLE_V1 BIT(15) +#define B_AX_TXRPT_RXDATA_RECOVER_MANNUL_V1 BIT(14) +#define B_AX_TXRPT_IS_REQ_BUF BIT(13) +#define B_AX_TXRPT_IS_ENQ BIT(12) +#define B_AX_TXRPT_WR_PKT_ID_V1_SH 0 +#define B_AX_TXRPT_WR_PKT_ID_V1_MSK 0xfff + +#define R_AX_RX_INFO_RXSTS 0xC828 +#define R_AX_RX_INFO_RXSTS_C1 0xE828 +#define B_AX_ENQ_FIFO_EMPTY BIT(31) +#define B_AX_CSI_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RXSTS_IS_IDLE BIT(15) +#define B_AX_RXSTS_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RXSTS_IS_REQ_BUF BIT(13) +#define B_AX_RXSTS_IS_ENQ BIT(12) +#define B_AX_RXSTS_WR_PKT_ID_SH 0 +#define B_AX_RXSTS_WR_PKT_ID_MSK 0xfff + +#define R_AX_RX_INFO_CSI 0xC82C +#define R_AX_RX_INFO_CSI_C1 0xE82C +#define B_AX_CSI_PKTID_1_VALID_V1 BIT(31) +#define B_AX_CSI_PKTID_1_V1_SH 16 +#define B_AX_CSI_PKTID_1_V1_MSK 0xfff +#define B_AX_CSI_PKTID_0_VALID_V1 BIT(15) +#define B_AX_CSI_PKTID_0_V1_SH 0 +#define B_AX_CSI_PKTID_0_V1_MSK 0xfff + +// +// CMAC_DMA +// + +#define R_AX_DLE_CTRL 0xC800 +#define R_AX_DLE_CTRL_C1 0xE800 +#define B_AX_NO_RESERVE_PAGE_ERR BIT(31) +#define B_AX_SET_NULL_PKT_ERROR BIT(30) +#define B_AX_PLE_SET_BURST_NUM_ERROR BIT(29) +#define B_AX_PLE_RESPONSE_ERROR BIT(28) +#define B_AX_PLE_OUTPUT_ERROR BIT(27) +#define B_AX_WDE_SET_BURST_NUM_ERROR BIT(26) +#define B_AX_WDE_RESPONSE_ERROR BIT(25) +#define B_AX_WDE_OUTPUT_ERROR BIT(24) +#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) +#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) +#define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14) +#define B_AX_DLE_WDE_STATE_SH 11 +#define B_AX_DLE_WDE_STATE_MSK 0x3 +#define B_AX_DLE_PLE_STATE_SH 9 +#define B_AX_DLE_PLE_STATE_MSK 0x3 +#define B_AX_DLE_REQUEST_BUFF_STATE_SH 7 +#define B_AX_DLE_REQUEST_BUFF_STATE_MSK 0x3 +#define B_AX_DLE_ENQ_STATE BIT(6) +#define B_AX_RECOVERY_INDICATOR BIT(5) +#define B_AX_DLE_CLOCK_FORCE BIT(4) +#define B_AX_TXDMA_CLOCK_FORCE BIT(3) +#define B_AX_RXDMA_CLOCK_FORCE BIT(2) +#define B_AX_DMA_DBG_SEL BIT(1) +#define B_AX_PL_PAGE_128B BIT(0) + +#define R_AX_RXDMA_CTRL_0 0xC804 +#define R_AX_RXDMA_CTRL_0_C1 0xE804 +#define B_AX_RXDMA_DBGOUT_EN BIT(31) +#define B_AX_RXDMA_DBG_SEL_SH 29 +#define B_AX_RXDMA_DBG_SEL_MSK 0x3 +#define B_AX_RXDMA_FIFO_DBG_SEL_SH 25 +#define B_AX_RXDMA_FIFO_DBG_SEL_MSK 0xf +#define B_AX_RXDMA_BUFF_REQ_PRI_SH 19 +#define B_AX_RXDMA_BUFF_REQ_PRI_MSK 0x3 +#define B_AX_RXDMA_TGT_QUEID_SH 13 +#define B_AX_RXDMA_TGT_QUEID_MSK 0x3f +#define B_AX_RXDMA_TGT_PRID_SH 10 +#define B_AX_RXDMA_TGT_PRID_MSK 0x7 +#define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9) +#define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7) +#define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6) +#define B_AX_RXSTS_PTR_FULL_MODE BIT(5) +#define B_AX_CSI_PTR_FULL_MODE BIT(4) +#define B_AX_RU3_PTR_FULL_MODE BIT(3) +#define B_AX_RU2_PTR_FULL_MODE BIT(2) +#define B_AX_RU1_PTR_FULL_MODE BIT(1) +#define B_AX_RU0_PTR_FULL_MODE BIT(0) + +#define R_AX_RXDMA_CTRL_1 0xC808 +#define R_AX_RXDMA_CTRL_1_C1 0xE808 +#define B_AX_F2PCMD_FULL_RSV_DEPTH_SH 28 +#define B_AX_F2PCMD_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_TXRPT_FULL_RSV_DEPTH_SH 24 +#define B_AX_TXRPT_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_RXSTS_FULL_RSV_DEPTH_SH 20 +#define B_AX_RXSTS_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_CSI_FULL_RSV_DEPTH_SH 16 +#define B_AX_CSI_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_RU3_FULL_RSV_DEPTH_SH 12 +#define B_AX_RU3_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_RU2_FULL_RSV_DEPTH_SH 8 +#define B_AX_RU2_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_RU1_FULL_RSV_DEPTH_SH 4 +#define B_AX_RU1_FULL_RSV_DEPTH_MSK 0xf +#define B_AX_RU0_FULL_RSV_DEPTH_SH 0 +#define B_AX_RU0_FULL_RSV_DEPTH_MSK 0xf + +#define R_AX_RXDMA_ERR_FLG_0 0xC80C +#define R_AX_RXDMA_ERR_FLG_0_C1 0xE80C +#define B_AX_RXDMA_ORDER_FIFO_FULL BIT(14) +#define B_AX_RXDMA_F2PCMD_PTR_OVERFLOW BIT(12) +#define B_AX_RXDMA_TXRPT_PTR_OVERFLOW BIT(11) +#define B_AX_RXDMA_RXSTS_PTR_OVERFLOW BIT(10) +#define B_AX_RXDMA_RU3_PTR_OVERFLOW BIT(9) +#define B_AX_RXDMA_RU2_PTR_OVERFLOW BIT(8) +#define B_AX_RXDMA_RU1_PTR_OVERFLOW BIT(7) +#define B_AX_RXDMA_RU0_PTR_OVERFLOW BIT(6) +#define B_AX_RXDMA_RXSTS_PTR_ERROR BIT(5) +#define B_AX_RXDMA_CSI_PTR_ERROR BIT(4) +#define B_AX_RXDMA_RU3_PTR_ERROR BIT(3) +#define B_AX_RXDMA_RU2_PTR_ERROR BIT(2) +#define B_AX_RXDMA_RU1_PTR_ERROR BIT(1) +#define B_AX_RXDMA_RU0_PTR_ERROR BIT(0) + +#define R_AX_RXDMA_ERR_FLG_1 0xC810 +#define R_AX_RXDMA_ERR_FLG_1_C1 0xE810 +#define B_AX_F2PCMD_PKT_ERR_TYPE2 BIT(27) +#define B_AX_F2PCMD_PKT_ERR_TYPE1 BIT(26) +#define B_AX_F2PCMD_DMA_ERR_TYPE2 BIT(25) +#define B_AX_F2PCMD_DMA_ERR_TYPE1 BIT(24) +#define B_AX_TXRPT_PKT_ERR_TYPE2 BIT(23) +#define B_AX_TXRPT_PKT_ERR_TYPE1 BIT(22) +#define B_AX_TXRPT_DMA_ERR_TYPE2 BIT(21) +#define B_AX_TXRPT_DMA_ERR_TYPE1 BIT(20) +#define B_AX_RXSTS_PKT_ERR_TYPE2 BIT(19) +#define B_AX_RXSTS_PKT_ERR_TYPE1 BIT(18) +#define B_AX_RXSTS_DMA_ERR_TYPE2 BIT(17) +#define B_AX_RXSTS_DMA_ERR_TYPE1 BIT(16) +#define B_AX_RU3_PKT_ERR_TYPE2 BIT(15) +#define B_AX_RU3_PKT_ERR_TYPE1 BIT(14) +#define B_AX_RU3_DMA_ERR_TYPE2 BIT(13) +#define B_AX_RU3_DMA_ERR_TYPE1 BIT(12) +#define B_AX_RU2_PKT_ERR_TYPE2 BIT(11) +#define B_AX_RU2_PKT_ERR_TYPE1 BIT(10) +#define B_AX_RU2_DMA_ERR_TYPE2 BIT(9) +#define B_AX_RU2_DMA_ERR_TYPE1 BIT(8) +#define B_AX_RU1_PKT_ERR_TYPE2 BIT(7) +#define B_AX_RU1_PKT_ERR_TYPE1 BIT(6) +#define B_AX_RU1_DMA_ERR_TYPE2 BIT(5) +#define B_AX_RU1_DMA_ERR_TYPE1 BIT(4) +#define B_AX_RU0_PKT_ERR_TYPE2 BIT(3) +#define B_AX_RU0_PKT_ERR_TYPE1 BIT(2) +#define B_AX_RU0_DMA_ERR_TYPE2 BIT(1) +#define B_AX_RU0_DMA_ERR_TYPE1 BIT(0) + +#define R_AX_RXDMA_PKT_INFO_0 0xC814 +#define R_AX_RXDMA_PKT_INFO_0_C1 0xE814 +#define B_AX_RU1_IS_IDLE BIT(31) +#define B_AX_RU1_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU1_WR_PKT_ID_SH 16 +#define B_AX_RU1_WR_PKT_ID_MSK 0xfff +#define B_AX_RU0_IS_IDLE BIT(15) +#define B_AX_RU0_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU0_WR_PKT_ID_SH 0 +#define B_AX_RU0_WR_PKT_ID_MSK 0xfff + +#define R_AX_RXDMA_PKT_INFO_1 0xC818 +#define R_AX_RXDMA_PKT_INFO_1_C1 0xE818 +#define B_AX_RU3_IS_IDLE BIT(31) +#define B_AX_RU3_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_RU3_WR_PKT_ID_SH 16 +#define B_AX_RU3_WR_PKT_ID_MSK 0xfff +#define B_AX_RU2_IS_IDLE BIT(15) +#define B_AX_RU2_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RU2_WR_PKT_ID_SH 0 +#define B_AX_RU2_WR_PKT_ID_MSK 0xfff + +#define R_AX_RXDMA_PKT_INFO_2 0xC81C +#define R_AX_RXDMA_PKT_INFO_2_C1 0xE81C +#define B_AX_TXRPT_IS_IDLE BIT(31) +#define B_AX_TXRPT_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_TXRPT_WR_PKT_ID_SH 16 +#define B_AX_TXRPT_WR_PKT_ID_MSK 0xfff +#define B_AX_RXSTS_IS_IDLE BIT(15) +#define B_AX_RXSTS_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_RXSTS_WR_PKT_ID_SH 0 +#define B_AX_RXSTS_WR_PKT_ID_MSK 0xfff + +#define R_AX_RXDMA_PKT_INFO_3 0xC820 +#define R_AX_RXDMA_PKT_INFO_3_C1 0xE820 +#define B_AX_CSI_ENQ_FIFO_EMPTY BIT(31) +#define B_AX_CSI_RXDATA_RECOVER_MANNUL BIT(30) +#define B_AX_F2PCMD_IS_IDLE BIT(15) +#define B_AX_F2PCMD_RXDATA_RECOVER_MANNUL BIT(14) +#define B_AX_F2PCMD_WR_PKT_ID_SH 0 +#define B_AX_F2PCMD_WR_PKT_ID_MSK 0xfff + +#define R_AX_RXDMA_PKT_INFO_4 0xC824 +#define R_AX_RXDMA_PKT_INFO_4_C1 0xE824 +#define B_AX_CSI_PKTID_1_VALID BIT(31) +#define B_AX_CSI_PKTID_1_SH 16 +#define B_AX_CSI_PKTID_1_MSK 0xfff +#define B_AX_CSI_PKTID_0_VALID BIT(15) +#define B_AX_CSI_PKTID_0_SH 0 +#define B_AX_CSI_PKTID_0_MSK 0xfff + +#define R_AX_TXDMA_FIFO_INFO_0 0xC834 +#define R_AX_TXDMA_FIFO_INFO_0_C1 0xE834 +#define B_AX_MACTX_ALLOT_DEPTH_1_SH 0 +#define B_AX_MACTX_ALLOT_DEPTH_1_MSK 0x3fffffff + +#define R_AX_TXDMA_FIFO_INFO_1 0xC838 +#define R_AX_TXDMA_FIFO_INFO_1_C1 0xE838 +#define B_AX_RU1_TXFIFO_COUNT_SH 20 +#define B_AX_RU1_TXFIFO_COUNT_MSK 0x3ff +#define B_AX_RU0_TXFIFO_COUNT_SH 10 +#define B_AX_RU0_TXFIFO_COUNT_MSK 0x3ff +#define B_AX_MACTX_ALLOT_DEPTH_2_SH 0 +#define B_AX_MACTX_ALLOT_DEPTH_2_MSK 0x3ff + +#define R_AX_TXDMA_FIFO_INFO_2 0xC83C +#define R_AX_TXDMA_FIFO_INFO_2_C1 0xE83C +#define B_AX_RU3_TXFIFO_COUNT_SH 10 +#define B_AX_RU3_TXFIFO_COUNT_MSK 0x3ff +#define B_AX_RU2_TXFIFO_COUNT_SH 0 +#define B_AX_RU2_TXFIFO_COUNT_MSK 0x3ff + +#define R_AX_TXDMA_DBG 0xC840 +#define R_AX_TXDMA_DBG_C1 0xE840 +#define B_AX_TXDMA_DBG_SEL_SH 27 +#define B_AX_TXDMA_DBG_SEL_MSK 0x1f +#define B_AX_TXDMA_DBG_EN BIT(26) +#define B_AX_TX_FINISH_REQ BIT(6) +#define B_AX_PL_ARB_RU_SH 4 +#define B_AX_PL_ARB_RU_MSK 0x3 +#define B_AX_WD_ARB_RU_SH 2 +#define B_AX_WD_ARB_RU_MSK 0x3 +#define B_AX_REQ_WD_PLD_ID_CS_SH 0 +#define B_AX_REQ_WD_PLD_ID_CS_MSK 0x3 + +#define R_AX_TXDMA_RU_INFO_0 0xC844 +#define R_AX_TXDMA_RU_INFO_0_C1 0xE844 +#define B_AX_RU0_CUR_WD_ID_SH 18 +#define B_AX_RU0_CUR_WD_ID_MSK 0xfff +#define B_AX_RU0_CUR_PL_ID_SH 6 +#define B_AX_RU0_CUR_PL_ID_MSK 0xfff +#define B_AX_RU0_READ_CS_SH 3 +#define B_AX_RU0_READ_CS_MSK 0x7 +#define B_AX_RU0_WRITE_CS_SH 0 +#define B_AX_RU0_WRITE_CS_MSK 0x7 + +#define R_AX_TXDMA_RU_INFO_1 0xC848 +#define R_AX_TXDMA_RU_INFO_1_C1 0xE848 +#define B_AX_RU1_CUR_WD_ID_SH 18 +#define B_AX_RU1_CUR_WD_ID_MSK 0xfff +#define B_AX_RU1_CUR_PL_ID_SH 6 +#define B_AX_RU1_CUR_PL_ID_MSK 0xfff +#define B_AX_RU1_READ_CS_SH 3 +#define B_AX_RU1_READ_CS_MSK 0x7 +#define B_AX_RU1_WRITE_CS_SH 0 +#define B_AX_RU1_WRITE_CS_MSK 0x7 + +#define R_AX_TXDMA_RU_INFO_2 0xC84C +#define R_AX_TXDMA_RU_INFO_2_C1 0xE84C +#define B_AX_RU2_CUR_WD_ID_SH 18 +#define B_AX_RU2_CUR_WD_ID_MSK 0xfff +#define B_AX_RU2_CUR_PL_ID_SH 6 +#define B_AX_RU2_CUR_PL_ID_MSK 0xfff +#define B_AX_RU2_READ_CS_SH 3 +#define B_AX_RU2_READ_CS_MSK 0x7 +#define B_AX_RU2_WRITE_CS_SH 0 +#define B_AX_RU2_WRITE_CS_MSK 0x7 + +#define R_AX_TXDMA_RU_INFO_3 0xC850 +#define R_AX_TXDMA_RU_INFO_3_C1 0xE850 +#define B_AX_RU3_CUR_WD_ID_SH 18 +#define B_AX_RU3_CUR_WD_ID_MSK 0xfff +#define B_AX_RU3_CUR_PL_ID_SH 6 +#define B_AX_RU3_CUR_PL_ID_MSK 0xfff +#define B_AX_RU3_READ_CS_SH 3 +#define B_AX_RU3_READ_CS_MSK 0x7 +#define B_AX_RU3_WRITE_CS_SH 0 +#define B_AX_RU3_WRITE_CS_MSK 0x7 + +// +// TMAC +// + +#define R_AX_TCR0 0xCA00 +#define R_AX_TCR0_C1 0xEA00 +#define B_AX_TCR_ZLD_NUM_SH 24 +#define B_AX_TCR_ZLD_NUM_MSK 0xff +#define B_AX_TCR_UDF_EN BIT(23) +#define B_AX_TCR_UDF_THSD_SH 16 +#define B_AX_TCR_UDF_THSD_MSK 0x7f +#define B_AX_TCR_ERRSTEN_SH 10 +#define B_AX_TCR_ERRSTEN_MSK 0x3f +#define B_AX_TCR_VHTSIGA1_TXPS BIT(9) +#define B_AX_TCR_PLCP_ERRHDL_EN BIT(8) +#define B_AX_TCR_PADSEL BIT(7) +#define B_AX_TCR_MASK_SIGBCRC BIT(6) +#define B_AX_TCR_SR_VAL15_ALLOW BIT(5) +#define B_AX_TCR_EN_EOF BIT(4) +#define B_AX_TCR_EN_SCRAM_INC BIT(3) +#define B_AX_TCR_EN_20MST BIT(2) +#define B_AX_TCR_CRC BIT(1) +#define B_AX_TCR_DISGCLK BIT(0) + +#define R_AX_TCR1 0xCA04 +#define R_AX_TCR1_C1 0xEA04 +#define B_AX_TXDFIFO_THRESHOLD_SH 28 +#define B_AX_TXDFIFO_THRESHOLD_MSK 0xf +#define B_AX_TCR_CCK_LOCK_CLK BIT(27) +#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) +#define B_AX_TCR_USTIME_SH 16 +#define B_AX_TCR_USTIME_MSK 0xff +#define B_AX_TCR_SMOOTH_VAL BIT(15) +#define B_AX_TCR_SMOOTH_CTRL BIT(14) +#define B_AX_CS_REQ_VAL BIT(13) +#define B_AX_CS_REQ_SEL BIT(12) +#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON_SH 8 +#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON_MSK 0xf +#define B_AX_TCR_TXTIMEOUT_SH 0 +#define B_AX_TCR_TXTIMEOUT_MSK 0xff + +#define R_AX_MD_TSFT_STMP_CTL 0xCA08 +#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08 +#define B_AX_TSFT_OFS_SH 16 +#define B_AX_TSFT_OFS_MSK 0xffff +#define B_AX_STMP_THSD_SH 8 +#define B_AX_STMP_THSD_MSK 0xff +#define B_AX_UPD_HGQMD BIT(1) +#define B_AX_UPD_TIMIE BIT(0) + +#define R_AX_PPWRBIT_SETTING 0xCA0C +#define R_AX_PPWRBIT_SETTING_C1 0xEA0C +#define B_AX_P4_PWRMGT_CTRL_EN BIT(19) +#define B_AX_P4_PWRMGT_DATA_EN BIT(18) +#define B_AX_P4_PWRMGT_ACT_EN BIT(17) +#define B_AX_P4_PWR_ST BIT(16) +#define B_AX_P3_PWRMGT_CTRL_EN BIT(15) +#define B_AX_P3_PWRMGT_DATA_EN BIT(14) +#define B_AX_P3_PWRMGT_ACT_EN BIT(13) +#define B_AX_P3_PWR_ST BIT(12) +#define B_AX_P2_PWRMGT_CTRL_EN BIT(11) +#define B_AX_P2_PWRMGT_DATA_EN BIT(10) +#define B_AX_P2_PWRMGT_ACT_EN BIT(9) +#define B_AX_P2_PWR_ST BIT(8) +#define B_AX_P1_PWRMGT_CTRL_EN BIT(7) +#define B_AX_P1_PWRMGT_DATA_EN BIT(6) +#define B_AX_P1_PWRMGT_ACT_EN BIT(5) +#define B_AX_P1_PWR_ST BIT(4) +#define B_AX_P0_PWRMGT_CTRL_EN BIT(3) +#define B_AX_P0_PWRMGT_DATA_EN BIT(2) +#define B_AX_P0_PWRMGT_ACT_EN BIT(1) +#define B_AX_P0_PWR_ST BIT(0) + +#define R_AX_HTC 0xCA10 +#define R_AX_HTC_C1 0xEA10 +#define B_AX_MHDR_HTC_SH 0 +#define B_AX_MHDR_HTC_MSK 0xffffffffL + +#define R_AX_SOUNDING 0xCA14 +#define R_AX_SOUNDING_C1 0xEA14 +#define B_AX_USE_NSTS BIT(22) +#define B_AX_RETRY_BFRPT_SEQ_UPD BIT(21) +#define B_AX_TXNDP_SIGB_SH 0 +#define B_AX_TXNDP_SIGB_MSK 0x1fffff + +#define R_AX_BSR_CTRL 0xCA18 +#define R_AX_BSR_CTRL_C1 0xEA18 +#define B_AX_RO_MIN_TX_PWR_FLAG BIT(21) +#define B_AX_RO_UPH_SH 16 +#define B_AX_RO_UPH_MSK 0x1f +#define B_AX_BSR_BK_TID_SEL BIT(4) +#define B_AX_BSR_BE_TID_SEL BIT(3) +#define B_AX_BSR_VI_TID_SEL BIT(2) +#define B_AX_BSR_VO_TID_SEL BIT(1) +#define B_AX_BSR_QOS_SEL BIT(0) + +#define R_AX_TXD_FIFO_CTRL 0xCA1C +#define R_AX_TXD_FIFO_CTRL_C1 0xEA1C +#define B_AX_TXDFIFO_HIGH_MCS_THRE_SH 12 +#define B_AX_TXDFIFO_HIGH_MCS_THRE_MSK 0xf +#define B_AX_TXDFIFO_LOW_MCS_THRE_SH 8 +#define B_AX_TXDFIFO_LOW_MCS_THRE_MSK 0xf +#define B_AX_HIGH_MCS_PHY_RATE_SH 4 +#define B_AX_HIGH_MCS_PHY_RATE_MSK 0xf +#define B_AX_BW_PHY_RATE_SH 0 +#define B_AX_BW_PHY_RATE_MSK 0x3 + +#define R_AX_MACTX_DBG_SEL_CNT 0xCA20 +#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 +#define B_AX_MACTX_MPDU_CNT_SH 24 +#define B_AX_MACTX_MPDU_CNT_MSK 0xff +#define B_AX_MACTX_DMA_CNT_SH 16 +#define B_AX_MACTX_DMA_CNT_MSK 0xff +#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) +#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) +#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) +#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) +#define B_AX_DBGSEL_MACTX_SH 0 +#define B_AX_DBGSEL_MACTX_MSK 0x3f + +#define R_AX_DEBUG_ZLD_COUNTER_U0_U1 0xCA24 +#define R_AX_DEBUG_ZLD_COUNTER_U0_U1_C1 0xEA24 +#define B_AX_ZLD_CNT_USER1_SH 16 +#define B_AX_ZLD_CNT_USER1_MSK 0x3ff +#define B_AX_ZLD_CNT_USER0_SH 0 +#define B_AX_ZLD_CNT_USER0_MSK 0x3ff + +#define R_AX_DEBUG_ZLD_COUNTER_U2_U3 0xCA28 +#define R_AX_DEBUG_ZLD_COUNTER_U2_U3_C1 0xEA28 +#define B_AX_ZLD_CNT_USER3_SH 16 +#define B_AX_ZLD_CNT_USER3_MSK 0x3ff +#define B_AX_ZLD_CNT_USER2_SH 0 +#define B_AX_ZLD_CNT_USER2_MSK 0x3ff + +#define R_AX_TX_PPDU_CNT 0xCAE0 +#define R_AX_TX_PPDU_CNT_C1 0xEAE0 +#define B_AX_TX_PPDU_CNT_SH 16 +#define B_AX_TX_PPDU_CNT_MSK 0xffff +#define B_AX_RST_PPDU_CNT BIT(12) +#define B_AX_PPDU_CNT_RIDX_SH 8 +#define B_AX_PPDU_CNT_RIDX_MSK 0xf +#define B_AX_PPDU_CNT_IDX_SH 0 +#define B_AX_PPDU_CNT_IDX_MSK 0xf + +#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 +#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 +#define B_AX_TX_CTRL_DEBUG_SEL_SH 0 +#define B_AX_TX_CTRL_DEBUG_SEL_MSK 0xf + +#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 +#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 +#define B_AX_TX_CTRL_INFO_P0_SH 0 +#define B_AX_TX_CTRL_INFO_P0_MSK 0xffffffffL + +#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC +#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC +#define B_AX_TX_CTRL_INFO_P1_SH 0 +#define B_AX_TX_CTRL_INFO_P1_MSK 0xffffffffL + +// +// TRXPTCL +// + +#define R_AX_RSP_CHK_SIG 0xCC00 +#define R_AX_RSP_CHK_SIG_C1 0xEC00 +#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) +#define B_AX_RSP_CHK_BASIC_NAV BIT(21) +#define B_AX_RSP_CHK_INTRA_NAV BIT(20) +#define B_AX_RSP_CHK_TX_NAV BIT(19) +#define B_AX_TXDATA_END_PS_OPT BIT(18) +#define B_AX_CHECK_SOUNDING_SEQ BIT(17) +#define B_AX_RXBA_IGNOREA2 BIT(16) +#define B_AX_ACKTO_CCK_SH 8 +#define B_AX_ACKTO_CCK_MSK 0xff +#define B_AX_ACKTO_SH 0 +#define B_AX_ACKTO_MSK 0xff + +#define R_AX_TRXPTCL_RESP_0 0xCC04 +#define R_AX_TRXPTCL_RESP_0_C1 0xEC04 +#define B_AX_WMAC_RESP_STBC_EN BIT(31) +#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) +#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) +#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) +#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) +#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) +#define B_AX_RSP_CHK_BTCCA BIT(25) +#define B_AX_RSP_CHK_EDCCA BIT(24) +#define B_AX_RSP_CHK_CCA BIT(23) +#define B_AX_WMAC_LDPC_EN BIT(22) +#define B_AX_WMAC_SGIEN BIT(21) +#define B_AX_WMAC_SPLCPEN BIT(20) +#define B_AX_WMAC_BESP_CHNBUSY_SH 18 +#define B_AX_WMAC_BESP_CHNBUSY_MSK 0x3 +#define B_AX_WMAC_BESP_EABLY_TXBA BIT(17) +#define B_AX_WMAC_EN_TXACKBA_INTXOP BIT(16) +#define B_AX_WMAC_SPEC_SIFS_OFDM_SH 8 +#define B_AX_WMAC_SPEC_SIFS_OFDM_MSK 0xff +#define B_AX_WMAC_SPEC_SIFS_CCK_SH 0 +#define B_AX_WMAC_SPEC_SIFS_CCK_MSK 0xff + +#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08 +#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08 +#define B_AX_FTM_RRSR_RATE_EN_SH 24 +#define B_AX_FTM_RRSR_RATE_EN_MSK 0xf +#define B_AX_NESS_SH 22 +#define B_AX_NESS_MSK 0x3 +#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21) +#define B_AX_WMAC_RESP_DCM_EN BIT(20) +#define B_AX_WMAC_RRSB_AX_CCK_SH 16 +#define B_AX_WMAC_RRSB_AX_CCK_MSK 0xf +#define B_AX_WMAC_RESP_RATE_EN_SH 12 +#define B_AX_WMAC_RESP_RATE_EN_MSK 0xf +#define B_AX_WMAC_RESP_RSC_SH 10 +#define B_AX_WMAC_RESP_RSC_MSK 0x3 +#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9) +#define B_AX_WMAC_RESP_REF_RATE_SH 0 +#define B_AX_WMAC_RESP_REF_RATE_MSK 0x1ff + +#define R_AX_TRXPTCL_RRSR_CTL_1 0xCC0C +#define R_AX_TRXPTCL_RRSR_CTL_1_C1 0xEC0C +#define B_AX_WMAC_RRSR_HE_SH 24 +#define B_AX_WMAC_RRSR_HE_MSK 0xff +#define B_AX_WMAC_RRSR_VHT_SH 16 +#define B_AX_WMAC_RRSR_VHT_MSK 0xff +#define B_AX_WMAC_RRSR_HT_SH 8 +#define B_AX_WMAC_RRSR_HT_MSK 0xff +#define B_AX_WMAC_RRSR_OFDM_SH 0 +#define B_AX_WMAC_RRSR_OFDM_MSK 0xff + +#define R_AX_TRXPTCL_RESP_TX_ABORT_COUNTER 0xCC1C +#define R_AX_TRXPTCL_RESP_TX_ABORT_COUNTER_C1 0xEC1C +#define B_AX_WMAC_RMAC_BUSY_ABORT_RESP_TX_SH 24 +#define B_AX_WMAC_RMAC_BUSY_ABORT_RESP_TX_MSK 0xff +#define B_AX_WMAC_NAV_ABORT_RESP_TX_SH 16 +#define B_AX_WMAC_NAV_ABORT_RESP_TX_MSK 0xff +#define B_AX_WMAC_SEC_CCA_ABORT_RESP_TX_SH 8 +#define B_AX_WMAC_SEC_CCA_ABORT_RESP_TX_MSK 0xff +#define B_AX_WMAC_CCA_ABORT_RESP_TX_SH 0 +#define B_AX_WMAC_CCA_ABORT_RESP_TX_MSK 0xff + +#define R_AX_MAC_LOOPBACK 0xCC20 +#define R_AX_MAC_LOOPBACK_C1 0xEC20 +#define B_AX_MACLBK_RDY_PERIOD_SH 17 +#define B_AX_MACLBK_RDY_PERIOD_MSK 0xfff +#define B_AX_MACLBK_PLCP_DLY_SH 8 +#define B_AX_MACLBK_PLCP_DLY_MSK 0x1ff +#define B_AX_MACLBK_RDY_NUM_SH 3 +#define B_AX_MACLBK_RDY_NUM_MSK 0x1f +#define B_AX_MACLBK_EN BIT(0) + +#define R_AX_TRXPTCL_CTS_RRSR 0xCC24 +#define R_AX_TRXPTCL_CTS_RRSR_C1 0xEC24 +#define B_AX_WMAC_CTS_RRSR_RSC_SH 14 +#define B_AX_WMAC_CTS_RRSR_RSC_MSK 0x3 +#define B_AX_WMAC_CTS_RESP_OPT BIT(12) +#define B_AX_WMAC_CTS_RRSR_CCK_SH 8 +#define B_AX_WMAC_CTS_RRSR_CCK_MSK 0xf +#define B_AX_WMAC_CTS_RRSR_OFDM_SH 0 +#define B_AX_WMAC_CTS_RRSR_OFDM_MSK 0xff + +#define R_AX_MAC_LOOPBACK_COUNT 0xCC28 +#define R_AX_MAC_LOOPBACK_COUNT_C1 0xEC28 +#define B_AX_MACLBK_COUNT_CLR BIT(0) + +#define R_AX_CLIENT_OM_CTRL 0xCC40 +#define R_AX_CLIENT_OM_CTRL_C1 0xEC40 +#define B_AX_WMAC_DIS_SIGTA BIT(16) +#define B_AX_UL_DATA_DIS_SH 0 +#define B_AX_UL_DATA_DIS_MSK 0x1f + +#define R_AX_WMAC_FTM_CTL 0xCC50 +#define R_AX_WMAC_FTM_CTL_C1 0xEC50 +#define B_AX_FTM_RPT_ERROR BIT(15) +#define B_AX_FTM_TIMEOUT_BYPASS BIT(14) +#define B_AX_RXFTM_EN BIT(2) +#define B_AX_RXFTMREQ_EN BIT(1) +#define B_AX_FTM_EN BIT(0) + +#define R_AX_GET_RTT 0xCC54 +#define R_AX_GET_RTT_C1 0xEC54 +#define B_AX_ACTION_FIELD_SH 16 +#define B_AX_ACTION_FIELD_MSK 0xff +#define B_AX_CATEGORY_FIELD_SH 8 +#define B_AX_CATEGORY_FIELD_MSK 0xff +#define B_AX_RTT_TYPE_SUBTYPE_SH 1 +#define B_AX_RTT_TYPE_SUBTYPE_MSK 0x3f +#define B_AX_RTT_FILTER_EN BIT(0) + +#define R_AX_FTM_PTT 0xCC58 +#define R_AX_FTM_PTT_C1 0xEC58 +#define B_AX_FTM_PTT_TSF_R2T_SEL_SH 3 +#define B_AX_FTM_PTT_TSF_R2T_SEL_MSK 0x7 +#define B_AX_FTM_PTT_TSF_T2R_SEL_SH 0 +#define B_AX_FTM_PTT_TSF_T2R_SEL_MSK 0x7 + +#define R_AX_FTM_TSF 0xCC5C +#define R_AX_FTM_TSF_C1 0xEC5C +#define B_AX_FTM_T2_TSF_SH 16 +#define B_AX_FTM_T2_TSF_MSK 0xffff +#define B_AX_FTM_T1_TSF_SH 0 +#define B_AX_FTM_T1_TSF_MSK 0xffff + +#define R_AX_MD_CTRL 0xCC72 +#define R_AX_MD_CTRL_C1 0xEC72 +#define B_AX_BC_MD_EN BIT(1) +#define B_AX_UC_MD_EN BIT(0) + +#define R_AX_WMMPS_UAPSD_TID 0xCC70 +#define R_AX_WMMPS_UAPSD_TID_C1 0xEC70 +#define B_AX_WMMPS_UAPSD_TID7 BIT(7) +#define B_AX_WMMPS_UAPSD_TID6 BIT(6) +#define B_AX_WMMPS_UAPSD_TID5 BIT(5) +#define B_AX_WMMPS_UAPSD_TID4 BIT(4) +#define B_AX_WMMPS_UAPSD_TID3 BIT(3) +#define B_AX_WMMPS_UAPSD_TID2 BIT(2) +#define B_AX_WMMPS_UAPSD_TID1 BIT(1) +#define B_AX_WMMPS_UAPSD_TID0 BIT(0) + +#define R_AX_WMAC_NAV_CTL 0xCC80 +#define R_AX_WMAC_NAV_CTL_C1 0xEC80 + +#define R_AX_WMAC_NAV_UP_INFO 0xCC84 +#define R_AX_WMAC_NAV_UP_INFO_C1 0xEC84 + +#define R_AX_RXTRIG_TEST_COMM_0 0xCCA0 +#define R_AX_RXTRIG_TEST_COMM_0_C1 0xECA0 + +#define R_AX_RXTRIG_TEST_COMM_1 0xCCA4 +#define R_AX_RXTRIG_TEST_COMM_1_C1 0xECA4 + +#define R_AX_RXTRIG_TEST_USER_0 0xCCA8 +#define R_AX_RXTRIG_TEST_USER_0_C1 0xECA8 + +#define R_AX_RXTRIG_TEST_USER_1 0xCCAC +#define R_AX_RXTRIG_TEST_USER_1_C1 0xECAC + +#define R_AX_RXTRIG_TEST_USER_2 0xCCB0 +#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 +#define B_AX_RXTRIG_MACID_SH 24 +#define B_AX_RXTRIG_MACID_MSK 0xff +#define B_AX_RXTRIG_RU26_DIS BIT(21) +#define B_AX_RXTRIG_FCSCHK_EN BIT(20) +#define B_AX_RXTRIG_PORT_SEL_SH 17 +#define B_AX_RXTRIG_PORT_SEL_MSK 0x7 +#define B_AX_RXTRIG_EN BIT(16) +#define B_AX_RXTRIG_USERINFO_2_SH 0 +#define B_AX_RXTRIG_USERINFO_2_MSK 0xffff + +#define R_AX_RXTRIG_TEST_CTRL1 0xCCB4 +#define R_AX_RXTRIG_TEST_CTRL1_C1 0xECB4 + +#define R_AX_SR_CONTROL_DBG 0xCCB8 +#define R_AX_SR_CONTROL_DBG_C1 0xECB8 + +#define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC +#define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC +#define B_AX_WMAC_MODE BIT(22) +#define B_AX_WMAC_TIMETOUT_THR_SH 16 +#define B_AX_WMAC_TIMETOUT_THR_MSK 0x3f +#define B_AX_RMAC_FTM BIT(8) +#define B_AX_RMAC_CSI BIT(7) +#define B_AX_TMAC_MIMO_CTRL BIT(6) +#define B_AX_TMAC_RXTB BIT(5) +#define B_AX_TMAC_HWSIGB_GEN BIT(4) +#define B_AX_TMAC_TXPLCP BIT(3) +#define B_AX_TMAC_RESP BIT(2) +#define B_AX_TMAC_TXCTL BIT(1) +#define B_AX_TMAC_MACTX BIT(0) + +#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 +#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 +#define B_AX_WMAC_TX_TF_INFO_SEL_SH 0 +#define B_AX_WMAC_TX_TF_INFO_SEL_MSK 0x7 + +#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 +#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 +#define B_AX_WMAC_TX_TF_INFO_P0_SH 0 +#define B_AX_WMAC_TX_TF_INFO_P0_MSK 0xffffffffL + +#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 +#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 +#define B_AX_WMAC_TX_TF_INFO_P1_SH 0 +#define B_AX_WMAC_TX_TF_INFO_P1_MSK 0xffffffffL + +#define R_AX_CTRL_FRAME_CNT_CTRL 0xCCE0 +#define R_AX_CTRL_FRAME_CNT_CTRL_C1 0xECE0 +#define B_AX_WMAC_ALLCNT_RST BIT(16) +#define B_AX_CTRL_SUBTYPE_SH 12 +#define B_AX_CTRL_SUBTYPE_MSK 0xf +#define B_AX_WMAC_WDATA_EN BIT(9) +#define B_AX_WMAC_ALLCNT_EN BIT(8) +#define B_AX_WMAC_CTRL_CNT_IDX_SH 0 +#define B_AX_WMAC_CTRL_CNT_IDX_MSK 0xf + +#define R_AX_CTRL_FRAME_CNT_SUBCTRL 0xCCE4 +#define R_AX_CTRL_FRAME_CNT_SUBCTRL_C1 0xECE4 +#define B_AX_CNT_INDEX_SH 8 +#define B_AX_CNT_INDEX_MSK 0xf +#define B_AX_CNTRST BIT(1) +#define B_AX_CNTEN BIT(0) + +#define R_AX_CTRL_FRAME_CNT_RPT 0xCCE8 +#define R_AX_CTRL_FRAME_CNT_RPT_C1 0xECE8 +#define B_AX_RX_CTRL_FRAME_CNT_SH 16 +#define B_AX_RX_CTRL_FRAME_CNT_MSK 0xffff +#define B_AX_TX_CTRL_FRAME_CNT_SH 0 +#define B_AX_TX_CTRL_FRAME_CNT_MSK 0xffff + +#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC +#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC +#define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19) +#define B_AX_TMAC_RESP_ERR_CLR BIT(18) +#define B_AX_TMAC_TXCTL_ERR_CLR BIT(17) +#define B_AX_TMAC_MACTX_ERR_CLR BIT(16) +#define B_AX_TMAC_TXPLCP_ERR BIT(14) +#define B_AX_TMAC_RESP_ERR BIT(13) +#define B_AX_TMAC_TXCTL_ERR BIT(12) +#define B_AX_TMAC_MACTX_ERR BIT(11) +#define B_AX_TMAC_TXPLCP_INT_EN BIT(10) +#define B_AX_TMAC_RESP_INT_EN BIT(9) +#define B_AX_TMAC_TXCTL_INT_EN BIT(8) +#define B_AX_TMAC_MACTX_INT_EN BIT(7) +#define B_AX_TMAC_MODE_INT_EN BIT(6) +#define B_AX_TMAC_TIMETOUT_THR_SH 0 +#define B_AX_TMAC_TIMETOUT_THR_MSK 0x3f + +#define R_AX_WMAC_DEBUG_PORT 0xCCF0 +#define R_AX_WMAC_DEBUG_PORT_C1 0xECF0 +#define B_AX_WMAC_DEBUG_SH 0 +#define B_AX_WMAC_DEBUG_MSK 0xffffffffL + +#define R_AX_DBGSEL_TRXPTCL 0xCCF4 +#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 +#define B_AX_DBGSEL_TRXPTCL_SH 0 +#define B_AX_DBGSEL_TRXPTCL_MSK 0x3f + +#define R_AX_PHYINFO_ERR_IMR 0xCCFE +#define R_AX_PHYINFO_ERR_IMR_C1 0xECFE +#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(5) +#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(4) +#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(3) +#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(2) +#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(1) +#define B_AXC_PHY_TXON_TIMEOUT_INT_EN BIT(0) + +#define R_AX_PHYINFO_ERR_ISR 0xCCFF +#define R_AX_PHYINFO_ERR_ISR_C1 0xECFF +#define B_AX_CSI_ON_TIMEOUT BIT(5) +#define B_AX_STS_ON_TIMEOUT BIT(4) +#define B_AX_DATA_ON_TIMEOUT BIT(3) +#define B_AX_OFDM_CCA_TIMEOUT BIT(2) +#define B_AX_CCK_CCA_TIMEOUT BIT(1) +#define B_AXC_PHY_TXON_TIMEOUT BIT(0) + +#define R_AX_BFMER_ASSOCIATED_SU0 0xCD00 +#define R_AX_BFMER_ASSOCIATED_SU0_C1 0xED00 +#define B_AX_MER_IGNORE_SU_BFMEE1_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE1_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE1_EN BIT(24) +#define B_AX_MER_SU_BFMEE1_MACID_SH 16 +#define B_AX_MER_SU_BFMEE1_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE0_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE0_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE0_EN BIT(8) +#define B_AX_MER_SU_BFMEE0_MACID_SH 0 +#define B_AX_MER_SU_BFMEE0_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU2 0xCD04 +#define R_AX_BFMER_ASSOCIATED_SU2_C1 0xED04 +#define B_AX_MER_IGNORE_SU_BFMEE3_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE3_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE3_EN BIT(24) +#define B_AX_MER_SU_BFMEE3_MACID_SH 16 +#define B_AX_MER_SU_BFMEE3_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE2_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE2_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE2_EN BIT(8) +#define B_AX_MER_SU_BFMEE2_MACID_SH 0 +#define B_AX_MER_SU_BFMEE2_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU4 0xCD08 +#define R_AX_BFMER_ASSOCIATED_SU4_C1 0xED08 +#define B_AX_MER_IGNORE_SU_BFMEE5_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE5_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE5_EN BIT(24) +#define B_AX_MER_SU_BFMEE5_MACID_SH 16 +#define B_AX_MER_SU_BFMEE5_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE4_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE4_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE4_EN BIT(8) +#define B_AX_MER_SU_BFMEE4_MACID_SH 0 +#define B_AX_MER_SU_BFMEE4_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU6 0xCD0C +#define R_AX_BFMER_ASSOCIATED_SU6_C1 0xED0C +#define B_AX_MER_IGNORE_SU_BFMEE7_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE7_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE7_EN BIT(24) +#define B_AX_MER_SU_BFMEE7_MACID_SH 16 +#define B_AX_MER_SU_BFMEE7_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE6_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE6_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE6_EN BIT(8) +#define B_AX_MER_SU_BFMEE6_MACID_SH 0 +#define B_AX_MER_SU_BFMEE6_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU8 0xCD10 +#define R_AX_BFMER_ASSOCIATED_SU8_C1 0xED10 +#define B_AX_MER_IGNORE_SU_BFMEE9_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE9_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE9_EN BIT(24) +#define B_AX_MER_SU_BFMEE9_MACID_SH 16 +#define B_AX_MER_SU_BFMEE9_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE8_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE8_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE8_EN BIT(8) +#define B_AX_MER_SU_BFMEE8_MACID_SH 0 +#define B_AX_MER_SU_BFMEE8_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU10 0xCD14 +#define R_AX_BFMER_ASSOCIATED_SU10_C1 0xED14 +#define B_AX_MER_IGNORE_SU_BFMEE11_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE11_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE11_EN BIT(24) +#define B_AX_MER_SU_BFMEE11_MACID_SH 16 +#define B_AX_MER_SU_BFMEE11_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE10_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE10_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE10_EN BIT(8) +#define B_AX_MER_SU_BFMEE10_MACID_SH 0 +#define B_AX_MER_SU_BFMEE10_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU12 0xCD18 +#define R_AX_BFMER_ASSOCIATED_SU12_C1 0xED18 +#define B_AX_MER_IGNORE_SU_BFMEE13_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE13_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE13_EN BIT(24) +#define B_AX_MER_SU_BFMEE13_MACID_SH 16 +#define B_AX_MER_SU_BFMEE13_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE12_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE12_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE12_EN BIT(8) +#define B_AX_MER_SU_BFMEE12_MACID_SH 0 +#define B_AX_MER_SU_BFMEE12_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_SU14 0xCD1C +#define R_AX_BFMER_ASSOCIATED_SU14_C1 0xED1C +#define B_AX_MER_IGNORE_SU_BFMEE15_SND_STS BIT(26) +#define B_AX_MER_SU_BFMEE15_SND_STS BIT(25) +#define B_AX_MER_SU_BFMEE15_EN BIT(24) +#define B_AX_MER_SU_BFMEE15_MACID_SH 16 +#define B_AX_MER_SU_BFMEE15_MACID_MSK 0xff +#define B_AX_MER_IGNORE_SU_BFMEE14_SND_STS BIT(10) +#define B_AX_MER_SU_BFMEE14_SND_STS BIT(9) +#define B_AX_MER_SU_BFMEE14_EN BIT(8) +#define B_AX_MER_SU_BFMEE14_MACID_SH 0 +#define B_AX_MER_SU_BFMEE14_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_MU0 0xCD20 +#define R_AX_BFMER_ASSOCIATED_MU0_C1 0xED20 +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE1 BIT(27) +#define B_AX_MER_IGNORE_MU_BFMEE1_SND_STS BIT(26) +#define B_AX_MER_MU_BFMEE1_SND_STS BIT(25) +#define B_AX_MER_MU_BFMEE1_EN BIT(24) +#define B_AX_MER_MU_BFMEE1_MACID_SH 16 +#define B_AX_MER_MU_BFMEE1_MACID_MSK 0xff +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE0 BIT(11) +#define B_AX_MER_IGNORE_MU_BFMEE0_SND_STS BIT(10) +#define B_AX_MER_MU_BFMEE0_SND_STS BIT(9) +#define B_AX_MER_MU_BFMEE0_EN BIT(8) +#define B_AX_MER_MU_BFMEE0_MACID_SH 0 +#define B_AX_MER_MU_BFMEE0_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_MU2 0xCD24 +#define R_AX_BFMER_ASSOCIATED_MU2_C1 0xED24 +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE3 BIT(27) +#define B_AX_MER_IGNORE_MU_BFMEE3_SND_STS BIT(26) +#define B_AX_MER_MU_BFMEE3_SND_STS BIT(25) +#define B_AX_MER_MU_BFMEE3_EN BIT(24) +#define B_AX_MER_MU_BFMEE3_MACID_SH 16 +#define B_AX_MER_MU_BFMEE3_MACID_MSK 0xff +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE2 BIT(11) +#define B_AX_MER_IGNORE_MU_BFMEE2_SND_STS BIT(10) +#define B_AX_MER_MU_BFMEE2_SND_STS BIT(9) +#define B_AX_MER_MU_BFMEE2_EN BIT(8) +#define B_AX_MER_MU_BFMEE2_MACID_SH 0 +#define B_AX_MER_MU_BFMEE2_MACID_MSK 0xff + +#define R_AX_BFMER_ASSOCIATED_MU4 0xCD28 +#define R_AX_BFMER_ASSOCIATED_MU4_C1 0xED28 +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE5 BIT(27) +#define B_AX_MER_IGNORE_MU_BFMEE5_SND_STS BIT(26) +#define B_AX_MER_MU_BFMEE5_SND_STS BIT(25) +#define B_AX_MER_MU_BFMEE5_EN BIT(24) +#define B_AX_MER_MU_BFMEE5_MACID_SH 16 +#define B_AX_MER_MU_BFMEE5_MACID_MSK 0xff +#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE4 BIT(11) +#define B_AX_MER_IGNORE_MU_BFMEE4_SND_STS BIT(10) +#define B_AX_MER_MU_BFMEE4_SND_STS BIT(9) +#define B_AX_MER_MU_BFMEE4_EN BIT(8) +#define B_AX_MER_MU_BFMEE4_MACID_SH 0 +#define B_AX_MER_MU_BFMEE4_MACID_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX0 0xCD2C +#define R_AX_BFMER_CSI_BUFF_IDX0_C1 0xED2C +#define B_AX_MER_TXBF_CSI_BUFF_IDX0_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX0_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX0_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX0_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX0_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX1 0xCD30 +#define R_AX_BFMER_CSI_BUFF_IDX1_C1 0xED30 +#define B_AX_MER_TXBF_CSI_BUFF_IDX1_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX1_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX1_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX1_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX1_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX1_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX2 0xCD34 +#define R_AX_BFMER_CSI_BUFF_IDX2_C1 0xED34 +#define B_AX_MER_TXBF_CSI_BUFF_IDX2_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX2_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX2_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX2_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX2_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX2_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX3 0xCD38 +#define R_AX_BFMER_CSI_BUFF_IDX3_C1 0xED38 +#define B_AX_MER_TXBF_CSI_BUFF_IDX3_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX3_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX3_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX3_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX3_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX3_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX4 0xCD3C +#define R_AX_BFMER_CSI_BUFF_IDX4_C1 0xED3C +#define B_AX_MER_TXBF_CSI_BUFF_IDX4_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX4_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX4_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX4_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX4_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX4_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX5 0xCD40 +#define R_AX_BFMER_CSI_BUFF_IDX5_C1 0xED40 +#define B_AX_MER_TXBF_CSI_BUFF_IDX5_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX5_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX5_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX5_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX5_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX5_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX6 0xCD44 +#define R_AX_BFMER_CSI_BUFF_IDX6_C1 0xED44 +#define B_AX_MER_TXBF_CSI_BUFF_IDX6_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX6_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX6_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX6_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX6_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX6_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX7 0xCD48 +#define R_AX_BFMER_CSI_BUFF_IDX7_C1 0xED48 +#define B_AX_MER_TXBF_CSI_BUFF_IDX7_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX7_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX7_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX7_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX7_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX7_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX8 0xCD4C +#define R_AX_BFMER_CSI_BUFF_IDX8_C1 0xED4C +#define B_AX_MER_TXBF_CSI_BUFF_IDX8_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX8_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX8_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX8_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX8_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX8_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX9 0xCD50 +#define R_AX_BFMER_CSI_BUFF_IDX9_C1 0xED50 +#define B_AX_MER_TXBF_CSI_BUFF_IDX9_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX9_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX9_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX9_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX9_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX9_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX10 0xCD54 +#define R_AX_BFMER_CSI_BUFF_IDX10_C1 0xED54 +#define B_AX_MER_TXBF_CSI_BUFF_IDX10_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX10_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX10_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX10_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX10_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX10_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX11 0xCD58 +#define R_AX_BFMER_CSI_BUFF_IDX11_C1 0xED58 +#define B_AX_MER_TXBF_CSI_BUFF_IDX11_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX11_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX11_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX11_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX11_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX11_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX12 0xCD5C +#define R_AX_BFMER_CSI_BUFF_IDX12_C1 0xED5C +#define B_AX_MER_TXBF_CSI_BUFF_IDX12_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX12_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX12_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX12_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX12_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX12_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX13 0xCD60 +#define R_AX_BFMER_CSI_BUFF_IDX13_C1 0xED60 +#define B_AX_MER_TXBF_CSI_BUFF_IDX13_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX13_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX13_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX13_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX13_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX13_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX14 0xCD64 +#define R_AX_BFMER_CSI_BUFF_IDX14_C1 0xED64 +#define B_AX_MER_TXBF_CSI_BUFF_IDX14_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX14_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX14_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX14_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX14_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX14_MSK 0xff + +#define R_AX_BFMER_CSI_BUFF_IDX15 0xCD68 +#define R_AX_BFMER_CSI_BUFF_IDX15_C1 0xED68 +#define B_AX_MER_TXBF_CSI_BUFF_IDX15_SH 20 +#define B_AX_MER_TXBF_CSI_BUFF_IDX15_MSK 0xfff +#define B_AX_MER_SND_CSI_BUFF_IDX15_SH 8 +#define B_AX_MER_SND_CSI_BUFF_IDX15_MSK 0xfff +#define B_AX_MER_CSI_BUFF_MACID_IDX15_SH 0 +#define B_AX_MER_CSI_BUFF_MACID_IDX15_MSK 0xff + +#define R_AX_BFMER_SND_DEBUG_CNT 0xCD6C +#define R_AX_BFMER_SND_DEBUG_CNT_C1 0xED6C +#define B_AX_SND_DNGCNT_RST BIT(20) +#define B_AX_MER_SND_DNGCNT_SH 0 +#define B_AX_MER_SND_DNGCNT_MSK 0xffff + +#define R_AX_BFMER_UPD_MEE_PARA 0xCD70 +#define R_AX_BFMER_UPD_MEE_PARA_C1 0xED70 +#define B_AX_MER_UPDMEE_OPTION BIT(31) +#define B_AX_MER_UPDMEE_USERID_SH 16 +#define B_AX_MER_UPDMEE_USERID_MSK 0xf +#define B_AX_MER_UPDMEE_FT_SH 12 +#define B_AX_MER_UPDMEE_FT_MSK 0x3 +#define B_AX_MER_UPDMEE_BW_SH 10 +#define B_AX_MER_UPDMEE_BW_MSK 0x3 +#define B_AX_MER_UPDMEE_CB_SH 8 +#define B_AX_MER_UPDMEE_CB_MSK 0x3 +#define B_AX_MER_UPDMEE_NG_SH 6 +#define B_AX_MER_UPDMEE_NG_MSK 0x3 +#define B_AX_MER_UPDMEE_NR_SH 3 +#define B_AX_MER_UPDMEE_NR_MSK 0x7 +#define B_AX_MER_UPDMEE_NC_SH 0 +#define B_AX_MER_UPDMEE_NC_MSK 0x7 + +#define R_AX_BFMER_RO_MEE_PARA 0xCD74 +#define R_AX_BFMER_RO_MEE_PARA_C1 0xED74 +#define B_AX_BFMER_RO_MEE_PARA_FT_SH 12 +#define B_AX_BFMER_RO_MEE_PARA_FT_MSK 0x3 +#define B_AX_BFMER_RO_MEE_PARA_BW_SH 10 +#define B_AX_BFMER_RO_MEE_PARA_BW_MSK 0x3 +#define B_AX_BFMER_RO_MEE_PARA_CB_SH 8 +#define B_AX_BFMER_RO_MEE_PARA_CB_MSK 0x3 +#define B_AX_BFMER_RO_MEE_PARA_NG_SH 6 +#define B_AX_BFMER_RO_MEE_PARA_NG_MSK 0x3 +#define B_AX_BFMER_RO_MEE_PARA_NR_SH 3 +#define B_AX_BFMER_RO_MEE_PARA_NR_MSK 0x7 +#define B_AX_BFMER_RO_MEE_PARA_NC_SH 0 +#define B_AX_BFMER_RO_MEE_PARA_NC_MSK 0x7 + +#define R_AX_BFMER_CTRL_0 0xCD78 +#define R_AX_BFMER_CTRL_0_C1 0xED78 +#define B_AX_BFMER_HE_CSI_OFFSET_SH 24 +#define B_AX_BFMER_HE_CSI_OFFSET_MSK 0xff +#define B_AX_BFMER_VHT_CSI_OFFSET_SH 16 +#define B_AX_BFMER_VHT_CSI_OFFSET_MSK 0xff +#define B_AX_BFMER_HT_CSI_OFFSET_SH 8 +#define B_AX_BFMER_HT_CSI_OFFSET_MSK 0xff +#define B_AX_BFMER_NDP_BFEN BIT(2) +#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) + +#define R_AX_BFMER_CTRL_1 0xCD7C +#define R_AX_BFMER_CTRL_1_C1 0xED7C +#define B_AX_BFMER_CTRLINFO_MACID_SH 0 +#define B_AX_BFMER_CTRLINFO_MACID_MSK 0xff + +#define R_AX_BFMEE_RESP_OPTION 0xCD80 +#define R_AX_BFMEE_RESP_OPTION_C1 0xED80 +#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH 24 +#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MSK 0xff +#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH 20 +#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MSK 0xf +#define B_AX_MU_BFRPTSEG_SEL_SH 17 +#define B_AX_MU_BFRPTSEG_SEL_MSK 0x3 +#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) + +#define R_AX_BFMEE_OPTION 0xCD84 +#define R_AX_BFMEE_OPTION_C1 0xED84 +#define B_AX_BFMEE_MU_BFEE_DIS BIT(7) +#define B_AX_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6) +#define B_AX_BFMEE_NOCHK_BFPOLL_BMP BIT(5) +#define B_AX_BFMEE_HE_NDPA_EN BIT(2) +#define B_AX_BFMEE_VHT_NDPA_EN BIT(1) +#define B_AX_BFMEE_HT_NDPA_EN BIT(0) + +#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 +#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 +#define B_AX_BFMEE_CSISEQ_SEL BIT(29) +#define B_AX_BFMEE_BFPARAM_SEL BIT(28) +#define B_AX_BFMEE_OFDM_LEN_TH_SH 24 +#define B_AX_BFMEE_OFDM_LEN_TH_MSK 0xf +#define B_AX_BFMEE_BF_PORT_SEL BIT(23) +#define B_AX_BFMEE_USE_NSTS BIT(22) +#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) +#define B_AX_BFMEE_CSI_GID_SEL BIT(20) +#define B_AX_BFMEE_CSI_RSC_SH 18 +#define B_AX_BFMEE_CSI_RSC_MSK 0x3 +#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) +#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) +#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) +#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) +#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) +#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) +#define B_AX_BFMEE_CSIINFO0_CS_SH 10 +#define B_AX_BFMEE_CSIINFO0_CS_MSK 0x3 +#define B_AX_BFMEE_CSIINFO0_CB_SH 8 +#define B_AX_BFMEE_CSIINFO0_CB_MSK 0x3 +#define B_AX_BFMEE_CSIINFO0_NG_SH 6 +#define B_AX_BFMEE_CSIINFO0_NG_MSK 0x3 +#define B_AX_BFMEE_CSIINFO0_NR_SH 3 +#define B_AX_BFMEE_CSIINFO0_NR_MSK 0x7 +#define B_AX_BFMEE_CSIINFO0_NC_SH 0 +#define B_AX_BFMEE_CSIINFO0_NC_MSK 0x7 + +#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C +#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C +#define B_AX_BFMEE_CSI_RRSC_BMAP_SH 0 +#define B_AX_BFMEE_CSI_RRSC_BMAP_MSK 0xffffffffL + +#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 +#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 +#define B_AX_BFMEE_HE_CSI_RATE_SH 16 +#define B_AX_BFMEE_HE_CSI_RATE_MSK 0x7f +#define B_AX_BFMEE_VHT_CSI_RATE_SH 8 +#define B_AX_BFMEE_VHT_CSI_RATE_MSK 0x7f +#define B_AX_BFMEE_HT_CSI_RATE_SH 0 +#define B_AX_BFMEE_HT_CSI_RATE_MSK 0x7f + +#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 +#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 +#define B_AX_BFMEE_CSIINFO1_BF_EN BIT(14) +#define B_AX_BFMEE_CSIINFO1_STBC_EN BIT(13) +#define B_AX_BFMEE_CSIINFO1_LDPC_EN BIT(12) +#define B_AX_BFMEE_CSIINFO1_CS_SH 10 +#define B_AX_BFMEE_CSIINFO1_CS_MSK 0x3 +#define B_AX_BFMEE_CSIINFO1_CB_SH 8 +#define B_AX_BFMEE_CSIINFO1_CB_MSK 0x3 +#define B_AX_BFMEE_CSIINFO1_NG_SH 6 +#define B_AX_BFMEE_CSIINFO1_NG_MSK 0x3 +#define B_AX_BFMEE_CSIINFO1_NR_SH 3 +#define B_AX_BFMEE_CSIINFO1_NR_MSK 0x7 +#define B_AX_BFMEE_CSIINFO1_NC_SH 0 +#define B_AX_BFMEE_CSIINFO1_NC_MSK 0x7 + +// +// RMAC +// + +#define R_AX_RCR 0xCE00 +#define R_AX_RCR_C1 0xEE00 +#define B_AX_STOP_RX_IN BIT(11) +#define B_AX_DRV_INFO_SIZE_SH 8 +#define B_AX_DRV_INFO_SIZE_MSK 0x7 +#define B_AX_CH_EN_SH 0 +#define B_AX_CH_EN_MSK 0xf + +#define R_AX_DLK_PROTECT_CTL 0xCE02 +#define R_AX_DLK_PROTECT_CTL_C1 0xEE02 +#define B_AX_RX_DLK_CCA_TIME_SH 8 +#define B_AX_RX_DLK_CCA_TIME_MSK 0xff +#define B_AX_RX_DLK_DATA_TIME_SH 4 +#define B_AX_RX_DLK_DATA_TIME_MSK 0xf +#define B_AX_RX_DLK_RST_EN BIT(1) +#define B_AX_RX_DLK_INT_EN BIT(0) + +#define R_AX_PLCP_HDR_FLTR 0xCE04 +#define R_AX_PLCP_HDR_FLTR_C1 0xEE04 +#define B_AX_DIS_CHK_MIN_LEN BIT(8) +#define B_AX_HE_SIGB_CRC_CHK BIT(6) +#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) +#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) +#define B_AX_SIGA_CRC_CHK BIT(3) +#define B_AX_LSIG_PARITY_CHK BIT(2) +#define B_AX_CCK_SIG_CHK BIT(1) +#define B_AX_CCK_CRC_CHK BIT(0) + +#define R_AX_RXGCK_CTRL 0xCE06 +#define R_AX_RXGCK_CTRL_C1 0xEE06 +#define B_AX_RXGCK_GCK_RATE_LIMIT_SH 8 +#define B_AX_RXGCK_GCK_RATE_LIMIT_MSK 0x3 +#define B_AX_RXGCK_ENTRY_DELAY_SH 4 +#define B_AX_RXGCK_ENTRY_DELAY_MSK 0x7 +#define B_AX_RXGCK_GCK_CYCLE_SH 2 +#define B_AX_RXGCK_GCK_CYCLE_MSK 0x3 +#define B_AX_RXGCK_CCA_EN BIT(1) +#define B_AX_DISGCLK BIT(0) + +#define R_AX_RXPSF_CTRL 0xCE08 +#define R_AX_RXPSF_CTRL_C1 0xEE08 +#define B_AX_RXPSF_PKTLENTHR_SH 16 +#define B_AX_RXPSF_PKTLENTHR_MSK 0x7 +#define B_AX_RXPSF_ERRTHR_SH 12 +#define B_AX_RXPSF_ERRTHR_MSK 0x7 +#define B_AX_INVALID_WIDTH_SH 8 +#define B_AX_INVALID_WIDTH_MSK 0x3 +#define B_AX_RXPSF_PLCP_CHKEN BIT(4) +#define B_AX_RXPSF_BSS_CHKEN BIT(3) +#define B_AX_RXPSF_MHCHKEN BIT(2) +#define B_AX_RXPSF_CONT_ERRCHKEN BIT(1) + +#define R_AX_RXPSF_MGT_TYPE 0xCE0E +#define R_AX_RXPSF_MGT_TYPE_C1 0xEE0E +#define B_AX_RXPSF_MGT15_PRSV BIT(15) +#define B_AX_RXPSF_MGT14_PRSV BIT(14) +#define B_AX_RXPSF_MGT13_PRSV BIT(13) +#define B_AX_RXPSF_MGT12_PRSV BIT(12) +#define B_AX_RXPSF_MGT11_PRSV BIT(11) +#define B_AX_RXPSF_MGT10_PRSV BIT(10) +#define B_AX_RXPSF_MGT9_PRSV BIT(9) +#define B_AX_RXPSF_MGT8_PRSV BIT(8) +#define B_AX_RXPSF_MGT7_PRSV BIT(7) +#define B_AX_RXPSF_MGT6_PRSV BIT(6) +#define B_AX_RXPSF_MGT5_PRSV BIT(5) +#define B_AX_RXPSF_MGT4_PRSV BIT(4) +#define B_AX_RXPSF_MGT3_PRSV BIT(3) +#define B_AX_RXPSF_MGT2_PRSV BIT(2) +#define B_AX_RXPSF_MGT1_PRSV BIT(1) +#define B_AX_RXPSF_MGT0_PRSV BIT(0) + +#define R_AX_RXPSF_DATA_TYPE 0xCE0C +#define R_AX_RXPSF_DATA_TYPE_C1 0xEE0C +#define B_AX_RXPSF_DATA15_PRSV BIT(15) +#define B_AX_RXPSF_DATA14_PRSV BIT(14) +#define B_AX_RXPSF_DATA13_PRSV BIT(13) +#define B_AX_RXPSF_DATA12_PRSV BIT(12) +#define B_AX_RXPSF_DATA11_PRSV BIT(11) +#define B_AX_RXPSF_DATA10_PRSV BIT(10) +#define B_AX_RXPSF_DATA9_PRSV BIT(9) +#define B_AX_RXPSF_DATA8_PRSV BIT(8) +#define B_AX_RXPSF_DATA7_PRSV BIT(7) +#define B_AX_RXPSF_DATA6_PRSV BIT(6) +#define B_AX_RXPSF_DATA5_PRSV BIT(5) +#define B_AX_RXPSF_DATA4_PRSV BIT(4) +#define B_AX_RXPSF_DATA3_PRSV BIT(3) +#define B_AX_RXPSF_DATA2_PRSV BIT(2) +#define B_AX_RXPSF_DATA1_PRSV BIT(1) +#define B_AX_RXPSF_DATA_PRSV BIT(0) + +#define R_AX_RXPSF_CTRL_TYPE 0xCE10 +#define R_AX_RXPSF_CTRL_TYPE_C1 0xEE10 +#define B_AX_RXPSF_CTRL_PRSV BIT(0) + +#define R_AX_RXPSF_RATE 0xCE12 +#define R_AX_RXPSF_RATE_C1 0xEE12 +#define B_AX_RXPSF_HETB_PRSV BIT(8) +#define B_AX_RXPSF_HEMU_PRSV BIT(7) +#define B_AX_RXPSF_HEERSU_PRSV BIT(6) +#define B_AX_RXPSF_HESU_PRSV BIT(5) +#define B_AX_RXPSF_VHTMU_PRSV BIT(4) +#define B_AX_RXPSF_VHTSU_PRSV BIT(3) +#define B_AX_RXPSF_HT_PRSV BIT(2) +#define B_AX_RXPSF_OFDM_PRSV BIT(1) +#define B_AX_RXPSF_CCK_PRSV BIT(0) + +#define R_AX_RXAI_CTRL 0xCE14 +#define R_AX_RXAI_CTRL_C1 0xEE14 +#define B_AX_RXAI_INFO_RST BIT(7) +#define B_AX_RXAI_PRTCT_REL BIT(6) +#define B_AX_RXAI_PRTCT_VIO BIT(5) +#define B_AX_RXAI_PRTCT_SEL BIT(1) +#define B_AX_RXAI_PRTCT_EN BIT(0) + +#define R_AX_RX_FIFO_CTRL 0xCE1C +#define R_AX_RX_FIFO_CTRL_C1 0xEE1C +#define B_AX_RXD_FIFO_MAX_LEV_CLR BIT(23) +#define B_AX_RXD_FIFO_MAX_LEV_SH 8 +#define B_AX_RXD_FIFO_MAX_LEV_MSK 0xff +#define B_AX_RXD_FIFO_FULL_TH_SH 0 +#define B_AX_RXD_FIFO_FULL_TH_MSK 0xff + +#define R_AX_RX_FLTR_OPT 0xCE20 +#define R_AX_RX_FLTR_OPT_C1 0xEE20 +#define B_AX_UID_FILTER_SH 24 +#define B_AX_UID_FILTER_MSK 0xff +#define B_AX_UNSPT_FILTER_SH 22 +#define B_AX_UNSPT_FILTER_MSK 0x3 +#define B_AX_RX_MPDU_MAX_LEN_SH 16 +#define B_AX_RX_MPDU_MAX_LEN_MSK 0x3f +#define B_AX_A_FTM_REQ BIT(14) +#define B_AX_A_ERR_PKT BIT(13) +#define B_AX_A_UNSUP_PKT BIT(12) +#define B_AX_A_CRC32_ERR BIT(11) +#define B_AX_A_PWR_MGNT BIT(10) +#define B_AX_A_BCN_CHK_RULE_SH 8 +#define B_AX_A_BCN_CHK_RULE_MSK 0x3 +#define B_AX_A_BCN_CHK_EN BIT(7) +#define B_AX_A_MC_LIST_CAM_MATCH BIT(6) +#define B_AX_A_BC_CAM_MATCH BIT(5) +#define B_AX_A_UC_CAM_MATCH BIT(4) +#define B_AX_A_MC BIT(3) +#define B_AX_A_BC BIT(2) +#define B_AX_A_A1_MATCH BIT(1) +#define B_AX_SNIFFER_MODE BIT(0) + +#define R_AX_CTRL_FLTR 0xCE24 +#define R_AX_CTRL_FLTR_C1 0xEE24 +#define B_AX_A_CTRL15_SH 30 +#define B_AX_A_CTRL15_MSK 0x3 +#define B_AX_A_CTRL14_SH 28 +#define B_AX_A_CTRL14_MSK 0x3 +#define B_AX_A_CTRL13_SH 26 +#define B_AX_A_CTRL13_MSK 0x3 +#define B_AX_A_CTRL12_SH 24 +#define B_AX_A_CTRL12_MSK 0x3 +#define B_AX_A_CTRL11_SH 22 +#define B_AX_A_CTRL11_MSK 0x3 +#define B_AX_A_CTRL10_SH 20 +#define B_AX_A_CTRL10_MSK 0x3 +#define B_AX_A_CTRL9_SH 18 +#define B_AX_A_CTRL9_MSK 0x3 +#define B_AX_A_CTRL8_SH 16 +#define B_AX_A_CTRL8_MSK 0x3 +#define B_AX_A_CTRL7_SH 14 +#define B_AX_A_CTRL7_MSK 0x3 +#define B_AX_A_CTRL6_SH 12 +#define B_AX_A_CTRL6_MSK 0x3 +#define B_AX_A_CTRL5_SH 10 +#define B_AX_A_CTRL5_MSK 0x3 +#define B_AX_A_CTRL4_SH 8 +#define B_AX_A_CTRL4_MSK 0x3 +#define B_AX_A_CTRL3_SH 6 +#define B_AX_A_CTRL3_MSK 0x3 +#define B_AX_A_CTRL2_SH 4 +#define B_AX_A_CTRL2_MSK 0x3 +#define B_AX_A_CTRL1_SH 2 +#define B_AX_A_CTRL1_MSK 0x3 +#define B_AX_A_CTRL0_SH 0 +#define B_AX_A_CTRL0_MSK 0x3 + +#define R_AX_MGNT_FLTR 0xCE28 +#define R_AX_MGNT_FLTR_C1 0xEE28 +#define B_AX_A_MGNT15_SH 30 +#define B_AX_A_MGNT15_MSK 0x3 +#define B_AX_A_MGNT14_SH 28 +#define B_AX_A_MGNT14_MSK 0x3 +#define B_AX_A_MGNT13_SH 26 +#define B_AX_A_MGNT13_MSK 0x3 +#define B_AX_A_MGNT12_SH 24 +#define B_AX_A_MGNT12_MSK 0x3 +#define B_AX_A_MGNT11_SH 22 +#define B_AX_A_MGNT11_MSK 0x3 +#define B_AX_A_MGNT10_SH 20 +#define B_AX_A_MGNT10_MSK 0x3 +#define B_AX_A_MGNT9_SH 18 +#define B_AX_A_MGNT9_MSK 0x3 +#define B_AX_A_MGNT8_SH 16 +#define B_AX_A_MGNT8_MSK 0x3 +#define B_AX_A_MGNT7_SH 14 +#define B_AX_A_MGNT7_MSK 0x3 +#define B_AX_A_MGNT6_SH 12 +#define B_AX_A_MGNT6_MSK 0x3 +#define B_AX_A_MGNT5_SH 10 +#define B_AX_A_MGNT5_MSK 0x3 +#define B_AX_A_MGNT4_SH 8 +#define B_AX_A_MGNT4_MSK 0x3 +#define B_AX_A_MGNT3_SH 6 +#define B_AX_A_MGNT3_MSK 0x3 +#define B_AX_A_MGNT2_SH 4 +#define B_AX_A_MGNT2_MSK 0x3 +#define B_AX_A_MGNT1_SH 2 +#define B_AX_A_MGNT1_MSK 0x3 +#define B_AX_A_MGNT0_SH 0 +#define B_AX_A_MGNT0_MSK 0x3 + +#define R_AX_DATA_FLTR 0xCE2C +#define R_AX_DATA_FLTR_C1 0xEE2C +#define B_AX_A_DATA15_SH 30 +#define B_AX_A_DATA15_MSK 0x3 +#define B_AX_A_DATA14_SH 28 +#define B_AX_A_DATA14_MSK 0x3 +#define B_AX_A_DATA13_SH 26 +#define B_AX_A_DATA13_MSK 0x3 +#define B_AX_A_DATA12_SH 24 +#define B_AX_A_DATA12_MSK 0x3 +#define B_AX_A_DATA11_SH 22 +#define B_AX_A_DATA11_MSK 0x3 +#define B_AX_A_DATA10_SH 20 +#define B_AX_A_DATA10_MSK 0x3 +#define B_AX_A_DATA9_SH 18 +#define B_AX_A_DATA9_MSK 0x3 +#define B_AX_A_DATA8_SH 16 +#define B_AX_A_DATA8_MSK 0x3 +#define B_AX_A_DATA7_SH 14 +#define B_AX_A_DATA7_MSK 0x3 +#define B_AX_A_DATA6_SH 12 +#define B_AX_A_DATA6_MSK 0x3 +#define B_AX_A_DATA5_SH 10 +#define B_AX_A_DATA5_MSK 0x3 +#define B_AX_A_DATA4_SH 8 +#define B_AX_A_DATA4_MSK 0x3 +#define B_AX_A_DATA3_SH 6 +#define B_AX_A_DATA3_MSK 0x3 +#define B_AX_A_DATA2_SH 4 +#define B_AX_A_DATA2_MSK 0x3 +#define B_AX_A_DATA1_SH 2 +#define B_AX_A_DATA1_MSK 0x3 +#define B_AX_A_DATA0_SH 0 +#define B_AX_A_DATA0_MSK 0x3 + +#define R_AX_ZLENDEL_COUNT 0xCE30 +#define R_AX_ZLENDEL_COUNT_C1 0xEE30 +#define B_AX_RXD_DELI_NUM_SH 8 +#define B_AX_RXD_DELI_NUM_MSK 0xff +#define B_AX_RXD_DELI_NUM_SEL_SH 4 +#define B_AX_RXD_DELI_NUM_SEL_MSK 0xf +#define B_AX_RXD_DELI_UNIT_SH 1 +#define B_AX_RXD_DELI_UNIT_MSK 0x3 +#define B_AX_RXD_DELI_EN BIT(0) + +#define R_AX_ADDR_CAM_CTRL 0xCE34 +#define R_AX_ADDR_CAM_CTRL_C1 0xEE34 +#define B_AX_ADDR_CAM_RANGE_SH 16 +#define B_AX_ADDR_CAM_RANGE_MSK 0xff +#define B_AX_ADDR_CAM_CMPLIMT_SH 12 +#define B_AX_ADDR_CAM_CMPLIMT_MSK 0xf +#define B_AX_ADDR_CAM_CLR BIT(8) +#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) +#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) +#define B_AX_ADDR_CAM_EN BIT(0) + +#define R_AX_ADDR_CAM_DIS_INFO 0xCE38 +#define R_AX_ADDR_CAM_DIS_INFO_C1 0xEE38 +#define B_AX_ADDR_CAM_DIS_MACID_SH 24 +#define B_AX_ADDR_CAM_DIS_MACID_MSK 0xff +#define B_AX_ADDR_CAM_DIS_SEC_IDX_SH 16 +#define B_AX_ADDR_CAM_DIS_SEC_IDX_MSK 0xff +#define B_AX_ADDR_CAM_DIS_PORT_SH 12 +#define B_AX_ADDR_CAM_DIS_PORT_MSK 0x7 +#define B_AX_ADDR_CAM_DIS_A3_HIT BIT(11) +#define B_AX_ADDR_CAM_DIS_A2_HIT BIT(10) +#define B_AX_ADDR_CAM_DIS_A1_HIT BIT(9) +#define B_AX_ADDR_CAM_DIS_CAM_HIT BIT(8) +#define B_AX_ADDR_CAM_DIS_IDX_SH 0 +#define B_AX_ADDR_CAM_DIS_IDX_MSK 0xff + +#define R_AX_RESPBA_CAM_CTRL 0xCE3C +#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C +#define B_AX_DEST_ENTRY_IDX_SH 12 +#define B_AX_DEST_ENTRY_IDX_MSK 0xf +#define B_AX_SRC_ENTRY_IDX_SH 8 +#define B_AX_SRC_ENTRY_IDX_MSK 0xf +#define B_AX_BACAM_SHIFT_POLL BIT(7) +#define B_AX_BACAM_ENT_CFG BIT(4) +#define B_AX_COMPL_VAL BIT(3) +#define B_AX_SSN_SEL BIT(2) +#define B_AX_BACAM_RST_SH 0 +#define B_AX_BACAM_RST_MSK 0x3 + +#define R_AX_PPDU_STAT 0xCE40 +#define R_AX_PPDU_STAT_C1 0xEE40 +#define B_AX_PPDU_STAT_RPT_TRIG BIT(8) +#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) +#define B_AX_PPDU_STAT_RPT_A1M BIT(4) +#define B_AX_APP_PLCP_HDR_RPT BIT(3) +#define B_AX_APP_RX_CNT_RPT BIT(2) +#define B_AX_APP_MAC_INFO_RPT BIT(1) +#define B_AX_PPDU_STAT_RPT_EN BIT(0) + +#define R_AX_PPDU_STAT_ERR 0xCE42 +#define R_AX_PPDU_STAT_ERR_C1 0xEE42 +#define B_AX_PPDU_STAT_ERR_3_CLR BIT(6) +#define B_AX_PPDU_STAT_ERR_2_CLR BIT(5) +#define B_AX_PPDU_STAT_ERR_1_CLR BIT(4) +#define B_AX_PPDU_STAT_ERR_3 BIT(2) +#define B_AX_PPDU_STAT_ERR_2 BIT(1) +#define B_AX_PPDU_STAT_ERR_1 BIT(0) + +#define R_AX_CH_INFO_QRY 0xCE44 +#define R_AX_CH_INFO_QRY_C1 0xEE44 +#define B_AX_CH_INFO_TIME_SH 24 +#define B_AX_CH_INFO_TIME_MSK 0xff +#define B_AX_CH_INFO_CNT_SH 21 +#define B_AX_CH_INFO_CNT_MSK 0x7 +#define B_AX_CH_INFO_REQUSTING BIT(20) +#define B_AX_CH_INFO_MGNT_FRM BIT(19) +#define B_AX_CH_INFO_CTRL_FRM BIT(18) +#define B_AX_CH_INFO_DATA_FRM BIT(17) +#define B_AX_CH_INFO_CRC_FAIL BIT(16) +#define B_AX_CH_INFO_MACID_SH 8 +#define B_AX_CH_INFO_MACID_MSK 0xff +#define B_AX_CH_INFO_MODE_SH 1 +#define B_AX_CH_INFO_MODE_MSK 0x7 +#define B_AX_GET_CH_INFO_EN BIT(0) + +#define R_AX_MACID_MATCH 0xCE48 +#define R_AX_MACID_MATCH_C1 0xEE48 +#define B_AX_MACID_MATCH_SH 8 +#define B_AX_MACID_MATCH_MSK 0xff +#define B_AX_MACID_MATCH_MODE BIT(1) +#define B_AX_MACID_MATCH_EN BIT(0) + +#define R_AX_RX_SR_CTRL 0xCE4A +#define R_AX_RX_SR_CTRL_C1 0xEE4A +#define B_AX_SR_OP_MODE_SH 4 +#define B_AX_SR_OP_MODE_MSK 0x3 +#define B_AX_SRG_CHK_EN BIT(2) +#define B_AX_SR_CTRL_PLCP_EN BIT(1) +#define B_AX_SR_EN BIT(0) + +#define R_AX_BSSID_SRC_CTRL 0xCE4B +#define R_AX_BSSID_SRC_CTRL_C1 0xEE4B +#define B_AX_BSSID_MATCH BIT(3) +#define B_AX_PARTIAL_AID_MATCH BIT(2) +#define B_AX_BSSCOLOR_MATCH BIT(1) +#define B_AX_PLCP_SRC_EN BIT(0) + +#define R_AX_SR_OBSS_PD 0xCE4C +#define R_AX_SR_OBSS_PD_C1 0xEE4C +#define B_AX_SRG_OBSS_PD_MAX_SH 24 +#define B_AX_SRG_OBSS_PD_MAX_MSK 0xff +#define B_AX_SRG_OBSS_PD_MIN_SH 16 +#define B_AX_SRG_OBSS_PD_MIN_MSK 0xff +#define B_AX_NONSRG_OBSS_PD_MAX_SH 8 +#define B_AX_NONSRG_OBSS_PD_MAX_MSK 0xff +#define B_AX_NONSRG_OBSS_PD_MIN_SH 0 +#define B_AX_NONSRG_OBSS_PD_MIN_MSK 0xff + +#define R_AX_SR_BSSCOLOR_BITMAP 0xCE50 +#define R_AX_SR_BSSCOLOR_BITMAP_C1 0xEE50 +#define B_AX_BSSCOLOR_BITMAP_SH 0 +#define B_AX_BSSCOLOR_BITMAP_MSK 0xffffffffffffffffL + +#define R_AX_SR_PARTIAL_BSSCOLOR_BITMAP 0xCE58 +#define R_AX_SR_PARTIAL_BSSCOLOR_BITMAP_C1 0xEE58 +#define B_AX_PARTIAL_BSSID_BITMAP_SH 0 +#define B_AX_PARTIAL_BSSID_BITMAP_MSK 0xffffffffffffffffL + +#define R_AX_SEGMENT_CTRL 0xCE60 +#define R_AX_SEGMENT_CTRL_C1 0xEE60 +#define B_AX_SEG_LENGTH_SH 4 +#define B_AX_SEG_LENGTH_MSK 0xf +#define B_AX_SEG_APP_ZERO BIT(1) +#define B_AX_SEG_EN BIT(0) +#define B_AX_CSIRPT_CHKSUM_ERROR BIT(31) +#define B_AX_CSIRPT_BBLEN_LT_MAC BIT(30) +#define B_AX_CSIRPT_BBLEN_GT_MAC BIT(29) +#define B_AX_CSIRPT_FIFO_RESUME_THR_SH 16 +#define B_AX_CSIRPT_FIFO_RESUME_THR_MSK 0xff +#define B_AX_CSIRPT_FIFO_PAUSE_THR_SH 8 +#define B_AX_CSIRPT_FIFO_PAUSE_THR_MSK 0xff +#define B_AX_CSIRPT_CHECKSUM_DIS BIT(2) +#define B_AX_CSIRPT_EMPTY_APPZERO BIT(1) +#define B_AX_CSIRPT_NDPPLCP_CHK_EN BIT(0) +#define B_AX_QSIZE_UPD BIT(0) + +#define R_AX_BCN_PSR_CTRL 0xCE80 +#define R_AX_BCN_PSR_CTRL_C1 0xEE80 +#define B_AX_BCN_HIT_INT_PORT_SH 4 +#define B_AX_BCN_HIT_INT_PORT_MSK 0xf +#define B_AX_BCAID_HIT_INT_EN BIT(3) +#define B_AX_UNIAID_HIT_INT_EN BIT(2) +#define B_AX_IE_HIT_INT_EN BIT(1) +#define B_AX_TIM_PARSER_EN BIT(0) + +#define R_AX_BCN_IECAM_CTRL 0xCE82 +#define R_AX_BCN_IECAM_CTRL_C1 0xEE82 +#define B_AX_BCN_PSR_BUSY BIT(15) +#define B_AX_BCN_IECAM_IORST BIT(14) +#define B_AX_BCN_IE_NOHIT_FRWD_SH 10 +#define B_AX_BCN_IE_NOHIT_FRWD_MSK 0x3 +#define B_AX_BCN_IE_HIT_FRWD_SH 8 +#define B_AX_BCN_IE_HIT_FRWD_MSK 0x3 +#define B_AX_BCN_IECAM_PORT_SH 4 +#define B_AX_BCN_IECAM_PORT_MSK 0xf +#define B_AX_BCN_IECAM_CLR BIT(3) +#define B_AX_BCN_IE_NOHIT_FRWD_EN BIT(2) +#define B_AX_BCN_IE_HIT_FRWD_EN BIT(1) +#define B_AX_BCN_IECAM_EN BIT(0) + +#define R_AX_BCN_PSR_RPT_P0 0xCE84 +#define R_AX_BCN_PSR_RPT_P0_C1 0xEE84 +#define B_AX_DTIM_CNT_P0_SH 24 +#define B_AX_DTIM_CNT_P0_MSK 0xff +#define B_AX_DTIM_PERIOD_P0_SH 16 +#define B_AX_DTIM_PERIOD_P0_MSK 0xff +#define B_AX_BCAID_HIT_P0 BIT(15) +#define B_AX_UNIAID_HIT_P0 BIT(14) +#define B_AX_IE_HIT_P0 BIT(13) +#define B_AX_TIM_ILEGAL_P0 BIT(12) +#define B_AX_RPT_VALID_P0 BIT(11) +#define B_AX_BCAID_P0_SH 0 +#define B_AX_BCAID_P0_MSK 0x7ff + +#define R_AX_BCN_PSR_RPT_P1 0xCE88 +#define R_AX_BCN_PSR_RPT_P1_C1 0xEE88 +#define B_AX_DTIM_CNT_P1_SH 24 +#define B_AX_DTIM_CNT_P1_MSK 0xff +#define B_AX_DTIM_PERIOD_P1_SH 16 +#define B_AX_DTIM_PERIOD_P1_MSK 0xff +#define B_AX_BCAID_HIT_P1 BIT(15) +#define B_AX_UNIAID_HIT_P1 BIT(14) +#define B_AX_IE_HIT_P1 BIT(13) +#define B_AX_TIM_ILEGAL_P1 BIT(12) +#define B_AX_RPT_VALID_P1 BIT(11) +#define B_AX_BCAID_P1_SH 0 +#define B_AX_BCAID_P1_MSK 0x7ff + +#define R_AX_BCN_PSR_RPT_P2 0xCE8C +#define R_AX_BCN_PSR_RPT_P2_C1 0xEE8C +#define B_AX_DTIM_CNT_P2_SH 24 +#define B_AX_DTIM_CNT_P2_MSK 0xff +#define B_AX_DTIM_PERIOD_P2_SH 16 +#define B_AX_DTIM_PERIOD_P2_MSK 0xff +#define B_AX_BCAID_HIT_P2 BIT(15) +#define B_AX_UNIAID_HIT_P2 BIT(14) +#define B_AX_IE_HIT_P2 BIT(13) +#define B_AX_TIM_ILEGAL_P2 BIT(12) +#define B_AX_RPT_VALID_P2 BIT(11) +#define B_AX_BCAID_P2_SH 0 +#define B_AX_BCAID_P2_MSK 0x7ff + +#define R_AX_BCN_PSR_RPT_P3 0xCE90 +#define R_AX_BCN_PSR_RPT_P3_C1 0xEE90 +#define B_AX_DTIM_CNT_P3_SH 24 +#define B_AX_DTIM_CNT_P3_MSK 0xff +#define B_AX_DTIM_PERIOD_P3_SH 16 +#define B_AX_DTIM_PERIOD_P3_MSK 0xff +#define B_AX_BCAID_HIT_P3 BIT(15) +#define B_AX_UNIAID_HIT_P3 BIT(14) +#define B_AX_IE_HIT_P3 BIT(13) +#define B_AX_TIM_ILEGAL_P3 BIT(12) +#define B_AX_RPT_VALID_P3 BIT(11) +#define B_AX_BCAID_P3_SH 0 +#define B_AX_BCAID_P3_MSK 0x7ff + +#define R_AX_BCN_PSR_RPT_P4 0xCE94 +#define R_AX_BCN_PSR_RPT_P4_C1 0xEE94 +#define B_AX_DTIM_CNT_P4_SH 24 +#define B_AX_DTIM_CNT_P4_MSK 0xff +#define B_AX_DTIM_PERIOD_P4_SH 16 +#define B_AX_DTIM_PERIOD_P4_MSK 0xff +#define B_AX_BCAID_HIT_P4 BIT(15) +#define B_AX_UNIAID_HIT_P4 BIT(14) +#define B_AX_IE_HIT_P4 BIT(13) +#define B_AX_TIM_ILEGAL_P4 BIT(12) +#define B_AX_RPT_VALID_P4 BIT(11) +#define B_AX_BCAID_P4_SH 0 +#define B_AX_BCAID_P4_MSK 0x7ff + +#define R_AX_PS_RXINFO 0xCEA0 +#define R_AX_PS_RXINFO_C1 0xEEA0 +#define B_AX_P4_RXCTRL BIT(14) +#define B_AX_P4_RXMGT BIT(13) +#define B_AX_P4_RXDATA BIT(12) +#define B_AX_P3_RXCTRL BIT(11) +#define B_AX_P3_RXMGT BIT(10) +#define B_AX_P3_RXDATA BIT(9) +#define B_AX_P2_RXCTRL BIT(8) +#define B_AX_P2_RXMGT BIT(7) +#define B_AX_P2_RXDATA BIT(6) +#define B_AX_P1_RXCTRL BIT(5) +#define B_AX_P1_RXMGT BIT(4) +#define B_AX_P1_RXDATA BIT(3) +#define B_AX_P0_RXCTRL BIT(2) +#define B_AX_P0_RXMGT BIT(1) +#define B_AX_P0_RXDATA BIT(0) + +#define R_AX_PWRINT_CTRL 0xCEAC +#define R_AX_PWRINT_CTRL_C1 0xEEAC +#define B_AX_SEQNUM_MACID_SH 16 +#define B_AX_SEQNUM_MACID_MSK 0xffff +#define B_AX_REF_MACID_SH 8 +#define B_AX_REF_MACID_MSK 0x7f +#define B_AX_PWRINT_EN BIT(0) + +#define R_AX_SPWR0 0xCEB0 +#define R_AX_SPWR0_C1 0xEEB0 +#define B_AX_MID_31TO0_SH 0 +#define B_AX_MID_31TO0_MSK 0xffffffffL + +#define R_AX_SPWR1 0xCEB4 +#define R_AX_SPWR1_C1 0xEEB4 +#define B_AX_MID_63TO32_SH 0 +#define B_AX_MID_63TO32_MSK 0xffffffffL + +#define R_AX_SPWR2 0xCEB8 +#define R_AX_SPWR2_C1 0xEEB8 +#define B_AX_MID_95O64_SH 0 +#define B_AX_MID_95O64_MSK 0xffffffffL + +#define R_AX_SPWR3 0xCEBC +#define R_AX_SPWR3_C1 0xEEBC +#define B_AX_MID_127TO96_SH 0 +#define B_AX_MID_127TO96_MSK 0xffffffffL + +#define R_AX_SNIFFER_MODE_CTRL 0xCEC0 +#define R_AX_SNIFFER_MODE_CTRL_C1 0xEEC0 +#define B_AX_AID3_ENABLE BIT(3) +#define B_AX_AID2_ENABLE BIT(2) +#define B_AX_AID1_ENABLE BIT(1) +#define B_AX_AID0_ENABLE BIT(0) + +#define R_AX_SNIFFER_MODE_AID0 0xCEC4 +#define R_AX_SNIFFER_MODE_AID0_C1 0xEEC4 +#define B_AX_SNIFFER_MODE_AID1_SH 16 +#define B_AX_SNIFFER_MODE_AID1_MSK 0xfff +#define B_AX_SNIFFER_MODE_AID0_SH 0 +#define B_AX_SNIFFER_MODE_AID0_MSK 0xfff + +#define R_AX_SNIFFER_MODE_AID1 0xCEC8 +#define R_AX_SNIFFER_MODE_AID1_C1 0xEEC8 +#define B_AX_SNIFFER_MODE_AID3_SH 16 +#define B_AX_SNIFFER_MODE_AID3_MSK 0xfff +#define B_AX_SNIFFER_MODE_AID2_SH 0 +#define B_AX_SNIFFER_MODE_AID2_MSK 0xfff + +#define R_AX_RX_DBG_CNT_SEL 0xCEE0 +#define R_AX_RX_DBG_CNT_SEL_C1 0xEEE0 +#define B_AX_RX_DBG_CNT_SH 16 +#define B_AX_RX_DBG_CNT_MSK 0xffff +#define B_AX_RXERR_RPT_RST BIT(8) +#define B_AX_RX_CNT_IDX_SH 0 +#define B_AX_RX_CNT_IDX_MSK 0x3f + +#define R_AX_RX_DBG_CNT_UD 0xCEE4 +#define R_AX_RX_DBG_CNT_UD_C1 0xEEE4 +#define B_AX_UD_W1S BIT(31) +#define B_AX_UD_MSK_RUTONE BIT(30) +#define B_AX_UD_MSK_RATE BIT(29) +#define B_AX_UD_MSK_BSSID BIT(28) +#define B_AX_UD_MSK_FC BIT(27) +#define B_AX_UD_RUTONE_SH 24 +#define B_AX_UD_RUTONE_MSK 0x7 +#define B_AX_UD_GI_TYPE_SH 20 +#define B_AX_UD_GI_TYPE_MSK 0x7 +#define B_AX_UD_RATE_SH 11 +#define B_AX_UD_RATE_MSK 0x1ff +#define B_AX_UD_SELECT_BSSID_SH 8 +#define B_AX_UD_SELECT_BSSID_MSK 0x7 +#define B_AX_UD_SUB_TYPE_SH 2 +#define B_AX_UD_SUB_TYPE_MSK 0xf +#define B_AX_UD_TYPE_SH 0 +#define B_AX_UD_TYPE_MSK 0x3 + +#define R_AX_RX_TIME_MON 0xCEEC +#define R_AX_RX_TIME_MON_C1 0xEEEC +#define B_AX_DMA_WR_TIME_SH 20 +#define B_AX_DMA_WR_TIME_MSK 0xf +#define B_AX_DMA_WR_TIMEOUT_SH 16 +#define B_AX_DMA_WR_TIMEOUT_MSK 0xf +#define B_AX_LATENCY_TIME_SH 8 +#define B_AX_LATENCY_TIME_MSK 0xf +#define B_AX_CCA2DAT_TIME_SH 0 +#define B_AX_CCA2DAT_TIME_MSK 0xff + +#define R_AX_RX_STATE_MONITOR 0xCEF0 +#define R_AX_RX_STATE_MONITOR_C1 0xEEF0 +#define B_AX_STATE_CUR_SH 16 +#define B_AX_STATE_CUR_MSK 0xffff +#define B_AX_STATE_NXT_SH 8 +#define B_AX_STATE_NXT_MSK 0x3f +#define B_AX_STATE_UPD BIT(7) +#define B_AX_STATE_SEL_SH 0 +#define B_AX_STATE_SEL_MSK 0x1f + +#define R_AX_RMAC_ERR_ISR 0xCEF4 +#define R_AX_RMAC_ERR_ISR_C1 0xEEF4 +#define B_AX_RXERR_INTPS_EN BIT(31) +#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) +#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) +#define B_AX_RMAC_CSI_TIMEOUT_INT_EN (17) +#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) +#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) +#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) +#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) +#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) +#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) +#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) +#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) +#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) +#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) +#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) +#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) +#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) + +#define R_AX_RMAC_PLCP_MON 0xCEF8 +#define R_AX_RMAC_PLCP_MON_C1 0xEEF8 +#define B_AX_PCLP_MON_SEL_SH 28 +#define B_AX_PCLP_MON_SEL_MSK 0xf +#define B_AX_PCLP_MON_CONT_SH 0 +#define B_AX_PCLP_MON_CONT_MSK 0xfffffff + +#define R_AX_RX_DEBUG_SELECT 0xCEFC +#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC +#define B_AX_DEBUG_SEL_SH 0 +#define B_AX_DEBUG_SEL_MSK 0xff + +// +// PWR +// + +#define R_AX_PWR_RATE_CTRL 0xD200 +#define R_AX_PWR_RATE_CTRL_C1 0xF200 +#define B_AX_TXPWR_CTRL_CLR BIT(31) +#define B_AX_FORCE_MODE_IDX_SH 28 +#define B_AX_FORCE_MODE_IDX_MSK 0x7 +#define B_AX_TXAGC_OFDM_REF_SH 19 +#define B_AX_TXAGC_OFDM_REF_MSK 0x1ff +#define B_AX_TXAGC_CCK_REF_SH 10 +#define B_AX_TXAGC_CCK_REF_MSK 0x1ff +#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) +#define B_AX_FORCE_PWR_BY_RATE_VALUE_SH 0 +#define B_AX_FORCE_PWR_BY_RATE_VALUE_MSK 0x1ff + +#define R_AX_PWR_RATE_OFST_CTRL 0xD204 +#define R_AX_PWR_RATE_OFST_CTRL_C1 0xF204 +#define B_AX_TXAGC_TBL_RD BIT(26) +#define B_AX_TXAGC_TBL_RA_SH 20 +#define B_AX_TXAGC_TBL_RA_MSK 0x3f +#define B_AX_TXAGC_CCK_HT_OFFSET_SH 16 +#define B_AX_TXAGC_CCK_HT_OFFSET_MSK 0xf +#define B_AX_TXAGC_LEGACY_HT_OFFSET_SH 12 +#define B_AX_TXAGC_LEGACY_HT_OFFSET_MSK 0xf +#define B_AX_TXAGC_HT_OFFSET_SH 8 +#define B_AX_TXAGC_HT_OFFSET_MSK 0xf +#define B_AX_TXAGC_VHT_HT_OFFSET_SH 4 +#define B_AX_TXAGC_VHT_HT_OFFSET_MSK 0xf +#define B_AX_TXAGC_HE_HT_OFFSET_SH 0 +#define B_AX_TXAGC_HE_HT_OFFSET_MSK 0xf + +#define R_AX_PWR_LMT_CTRL 0xD208 +#define R_AX_PWR_LMT_CTRL_C1 0xF208 +#define B_AX_FORCE_NORM_RSP_HE_TB_EN_ON BIT(24) +#define B_AX_FORCE_PWR_BY_LIMIT_BF0_EN BIT(23) +#define B_AX_FORCE_PWR_BY_LIMIT_BF1_EN BIT(22) +#define B_AX_TXAGC_PWR_LIM_BF0_EN BIT(21) +#define B_AX_TXAGC_PWR_LIM_BF1_EN BIT(20) +#define B_AX_TXAGC_BW20_BW40_OFFSET_SH 16 +#define B_AX_TXAGC_BW20_BW40_OFFSET_MSK 0xf +#define B_AX_TXAGC_RFBW_40M_OFFSET_SH 12 +#define B_AX_TXAGC_RFBW_40M_OFFSET_MSK 0xf +#define B_AX_TXAGC_BW80_BW40_OFFSET_SH 8 +#define B_AX_TXAGC_BW80_BW40_OFFSET_MSK 0xf +#define B_AX_TXAGC_BW160_BW40_OFFSET_SH 4 +#define B_AX_TXAGC_BW160_BW40_OFFSET_MSK 0xf +#define B_AX_TXAGC_BW80_80_BW40_OFFSET_SH 0 +#define B_AX_TXAGC_BW80_80_BW40_OFFSET_MSK 0xf + +#define R_AX_PWR_MACID_CTRL 0xD20C +#define R_AX_PWR_MACID_CTRL_C1 0xF20C +#define B_AX_TXAGC_PWR_BY_MACID_EN BIT(29) +#define B_AX_FORCE_CCA_PWR_TH_VALUE_EN BIT(28) +#define B_AX_FORCE_CCA_PWR_TH_VALUE_SH 20 +#define B_AX_FORCE_CCA_PWR_TH_VALUE_MSK 0xff +#define B_AX_FORCE_CCA_PWR_TH_EN BIT(17) +#define B_AX_FORCE_PWR_BY_MACID_EN BIT(16) +#define B_AX_FORCE_PWR_BY_MACID_VALUE_SH 8 +#define B_AX_FORCE_PWR_BY_MACID_VALUE_MSK 0xff +#define B_AX_FORCE_PWR_BY_MACID_VALUE_EN BIT(7) +#define B_AX_TXPWR_LIM_TBL_RD BIT(6) +#define B_AX_TXPWR_LIM_TBL_RA_SH 0 +#define B_AX_TXPWR_LIM_TBL_RA_MSK 0x3f + +#define R_AX_PWR_BF_CTRL 0xD210 +#define R_AX_PWR_BF_CTRL_C1 0xF210 +#define B_AX_TXAGC_BF_PWR_BOOST_EN BIT(31) +#define B_AX_HE_ER_SU_PWR_REDUCE_VAL_SH 19 +#define B_AX_HE_ER_SU_PWR_REDUCE_VAL_MSK 0x1f +#define B_AX_HE_ER_SU_PWR_REDUCE_EN BIT(18) +#define B_AX_FORCE_PWR_BY_LIMIT_BFOFF_VALUE_SH 9 +#define B_AX_FORCE_PWR_BY_LIMIT_BFOFF_VALUE_MSK 0x1ff +#define B_AX_FORCE_PWR_BY_LIMIT_BFON_VALUE_SH 0 +#define B_AX_FORCE_PWR_BY_LIMIT_BFON_VALUE_MSK 0x1ff + +#define R_AX_PWR_MACID_REG 0xD214 +#define R_AX_PWR_MACID_REG_C1 0xF214 +#define B_AX_TXPWR_REG3_SH 24 +#define B_AX_TXPWR_REG3_MSK 0xff +#define B_AX_TXPWR_REG2_SH 16 +#define B_AX_TXPWR_REG2_MSK 0xff +#define B_AX_TXPWR_REG1_SH 8 +#define B_AX_TXPWR_REG1_MSK 0xff +#define B_AX_TXPWR_REG0_SH 0 +#define B_AX_TXPWR_REG0_MSK 0xff + +#define R_AX_PWR_MACID_REG2 0xD218 +#define R_AX_PWR_MACID_REG2_C1 0xF218 +#define B_AX_TXPWR_BY_MACID_TBL_RD BIT(31) +#define B_AX_TXPWR_BY_MACID_TBL_RA_SH 24 +#define B_AX_TXPWR_BY_MACID_TBL_RA_MSK 0x7f +#define B_AX_TXPWR_REG5_EN BIT(21) +#define B_AX_TXPWR_REG4_EN BIT(20) +#define B_AX_TXPWR_REG3_EN BIT(19) +#define B_AX_TXPWR_REG2_EN BIT(18) +#define B_AX_TXPWR_REG1_EN BIT(17) +#define B_AX_TXPWR_REG0_EN BIT(16) +#define B_AX_TXPWR_REG5_SH 8 +#define B_AX_TXPWR_REG5_MSK 0xff +#define B_AX_TXPWR_REG4_SH 0 +#define B_AX_TXPWR_REG4_MSK 0xff + +#define R_AX_PWR_RU_LMT_CTRL 0xD21C +#define R_AX_PWR_RU_LMT_CTRL_C1 0xF21C +#define B_AX_TXAGC_LTE_SH 18 +#define B_AX_TXAGC_LTE_MSK 0x1ff +#define B_AX_TXPWR_RU_LIM_EN BIT(17) +#define B_AX_TXPWR_RU_LIM_TBL_RD BIT(16) +#define B_AX_TXPWR_RU_LIM_TBL_RA_SH 11 +#define B_AX_TXPWR_RU_LIM_TBL_RA_MSK 0x1f +#define B_AX_FORCE_PWR_BY_RU_LIMIT_EN BIT(10) +#define B_AX_FORCE_PWR_BY_RU_LIMIT_EN_VALUE BIT(9) +#define B_AX_FORCE_PWR_BY_RU_LIMIT_VALUE_SH 0 +#define B_AX_FORCE_PWR_BY_RU_LIMIT_VALUE_MSK 0x1ff + +#define R_AX_PWR_COEXT_CTRL 0xD220 +#define R_AX_PWR_COEXT_CTRL_C1 0xF220 +#define B_AX_CCK_NORM_TERM_SH 18 +#define B_AX_CCK_NORM_TERM_MSK 0x7f +#define B_AX_TXPWR_MAC_MAX_BND_SH 12 +#define B_AX_TXPWR_MAC_MAX_BND_MSK 0x3f +#define B_AX_TXAGC_BT_SH 3 +#define B_AX_TXAGC_BT_MSK 0x1ff +#define B_AX_TXAGC_LTE_EN BIT(2) +#define B_AX_TXAGC_BT_EN BIT(1) + +#define R_AX_PWR_SWING_LEG_CTRL 0xD224 +#define R_AX_PWR_SWING_LEG_CTRL_C1 0xF224 +#define B_AX_TXBIAS_LEGACY_BELOW_TH_VAL_SH 29 +#define B_AX_TXBIAS_LEGACY_BELOW_TH_VAL_MSK 0x3 +#define B_AX_TXBIAS_LEGACY_OV_TH_VAL_SH 27 +#define B_AX_TXBIAS_LEGACY_OV_TH_VAL_MSK 0x3 +#define B_AX_TXBBSWING_LEGACY_BELOW_TH_VAL_SH 23 +#define B_AX_TXBBSWING_LEGACY_BELOW_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_LEGACY_OV_TH_VAL_SH 19 +#define B_AX_TXBBSWING_LEGACY_OV_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_TXBIAS_LEGACY_TH_SH 15 +#define B_AX_TXBBSWING_TXBIAS_LEGACY_TH_MSK 0xf +#define B_AX_TXBIAS_CCK_BELOW_TH_VAL_SH 13 +#define B_AX_TXBIAS_CCK_BELOW_TH_VAL_MSK 0x3 +#define B_AX_TXBIAS_CCK_OV_TH_VAL_SH 11 +#define B_AX_TXBIAS_CCK_OV_TH_VAL_MSK 0x3 +#define B_AX_TXBBSWING_CCK_BELOW_TH_VAL_SH 7 +#define B_AX_TXBBSWING_CCK_BELOW_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_CCK_OV_TH_VAL_SH 3 +#define B_AX_TXBBSWING_CCK_OV_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_TXBIAS_CCK_TH_SH 0 +#define B_AX_TXBBSWING_TXBIAS_CCK_TH_MSK 0x7 + +#define R_AX_PWR_SWING_VHT_CTRL 0xD228 +#define R_AX_PWR_SWING_VHT_CTRL_C1 0xF228 +#define B_AX_TXBIAS_VHT_OV_TH_VAL_SH 30 +#define B_AX_TXBIAS_VHT_OV_TH_VAL_MSK 0x3 +#define B_AX_TXBBSWING_VHT_BELOW_TH_VAL_SH 26 +#define B_AX_TXBBSWING_VHT_BELOW_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_VHT_OV_TH_VAL_SH 22 +#define B_AX_TXBBSWING_VHT_OV_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_TXBIAS_VHT_TH_SH 18 +#define B_AX_TXBBSWING_TXBIAS_VHT_TH_MSK 0xf +#define B_AX_TXBIAS_HT_BELOW_TH_VAL_SH 16 +#define B_AX_TXBIAS_HT_BELOW_TH_VAL_MSK 0x3 +#define B_AX_TXBIAS_HT_OV_TH_VAL_SH 14 +#define B_AX_TXBIAS_HT_OV_TH_VAL_MSK 0x3 +#define B_AX_TXBBSWING_HT_BELOW_TH_VAL_SH 10 +#define B_AX_TXBBSWING_HT_BELOW_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_HT_OV_TH_VAL_SH 6 +#define B_AX_TXBBSWING_HT_OV_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_TXBIAS_HT_TH_SH 2 +#define B_AX_TXBBSWING_TXBIAS_HT_TH_MSK 0xf + +#define R_AX_PWR_SWING_HE_CTRL 0xD22C +#define R_AX_PWR_SWING_HE_CTRL_C1 0xF22C +#define B_AX_CFIR_BY_RATE_OFF_LEGACY_BELOW_TH_VAL BIT(28) +#define B_AX_CFIR_BY_RATE_OFF_LEGACY_OV_TH_VAL BIT(27) +#define B_AX_CFIR_BY_RATE_OFF_LEGACY_TH_SH 23 +#define B_AX_CFIR_BY_RATE_OFF_LEGACY_TH_MSK 0xf +#define B_AX_CFIR_BY_RATE_OFF_CCK_BELOW_TH_VAL BIT(22) +#define B_AX_CFIR_BY_RATE_OFF_CCK_OV_TH_VAL BIT(21) +#define B_AX_CFIR_BY_RATE_OFF_CCK_TH_SH 18 +#define B_AX_CFIR_BY_RATE_OFF_CCK_TH_MSK 0x7 +#define B_AX_TXBIAS_HE_BELOW_TH_VAL_SH 16 +#define B_AX_TXBIAS_HE_BELOW_TH_VAL_MSK 0x3 +#define B_AX_TXBIAS_HE_OV_TH_VAL_SH 14 +#define B_AX_TXBIAS_HE_OV_TH_VAL_MSK 0x3 +#define B_AX_TXBBSWING_HE_BELOW_TH_VAL_SH 10 +#define B_AX_TXBBSWING_HE_BELOW_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_HE_OV_TH_VAL_SH 6 +#define B_AX_TXBBSWING_HE_OV_TH_VAL_MSK 0xf +#define B_AX_TXBBSWING_TXBIAS_HE_TH_SH 2 +#define B_AX_TXBBSWING_TXBIAS_HE_TH_MSK 0xf +#define B_AX_TXBIAS_VHT_BELOW_TH_VAL_SH 0 +#define B_AX_TXBIAS_VHT_BELOW_TH_VAL_MSK 0x3 + +#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230 +#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230 +#define B_AX_DPD_BY_RATE_OFF_LEGACY_BELOW_TH_VAL BIT(28) +#define B_AX_DPD_BY_RATE_OFF_LEGACY_OV_TH_VAL BIT(27) +#define B_AX_DPD_BY_RATE_OFF_LEGACY_TH_SH 23 +#define B_AX_DPD_BY_RATE_OFF_LEGACY_TH_MSK 0xf +#define B_AX_DPD_BY_RATE_OFF_CCK_BELOW_TH_VAL BIT(22) +#define B_AX_DPD_BY_RATE_OFF_CCK_OV_TH_VAL BIT(21) +#define B_AX_DPD_BY_RATE_OFF_CCK_TH_SH 18 +#define B_AX_DPD_BY_RATE_OFF_CCK_TH_MSK 0x7 +#define B_AX_CFIR_BY_RATE_OFF_HE_BELOW_TH_VAL BIT(17) +#define B_AX_CFIR_BY_RATE_OFF_HE_OV_TH_VAL BIT(16) +#define B_AX_CFIR_BY_RATE_OFF_HE_TH_SH 12 +#define B_AX_CFIR_BY_RATE_OFF_HE_TH_MSK 0xf +#define B_AX_CFIR_BY_RATE_OFF_VHT_BELOW_TH_VAL BIT(11) +#define B_AX_CFIR_BY_RATE_OFF_VHT_OV_TH_VAL BIT(10) +#define B_AX_CFIR_BY_RATE_OFF_VHT_TH_SH 6 +#define B_AX_CFIR_BY_RATE_OFF_VHT_TH_MSK 0xf +#define B_AX_CFIR_BY_RATE_OFF_HT_BELOW_TH_VAL BIT(5) +#define B_AX_CFIR_BY_RATE_OFF_HT_OV_TH_VAL BIT(4) +#define B_AX_CFIR_BY_RATE_OFF_HT_TH_SH 0 +#define B_AX_CFIR_BY_RATE_OFF_HT_TH_MSK 0xf + +#define R_AX_PWR_SWING_OTHER_CTRL1 0xD234 +#define R_AX_PWR_SWING_OTHER_CTRL1_C1 0xF234 +#define B_AX_DPD_BY_RATE_OFF_SR_DONT_APPLY BIT(30) +#define B_AX_CFIR_BY_RATE_OFF_SR_DONT_APPLY BIT(29) +#define B_AX_TXBBSWING_TXBIAS_SR_DONT_APPLY BIT(28) +#define B_AX_DPD_BY_RATE_OFF_HE_BELOW_TH_VAL BIT(17) +#define B_AX_DPD_BY_RATE_OFF_HE_OV_TH_VAL BIT(16) +#define B_AX_DPD_BY_RATE_OFF_HE_TH_SH 12 +#define B_AX_DPD_BY_RATE_OFF_HE_TH_MSK 0xf +#define B_AX_DPD_BY_RATE_OFF_VHT_BELOW_TH_VAL BIT(11) +#define B_AX_DPD_BY_RATE_OFF_VHT_OV_TH_VAL BIT(10) +#define B_AX_DPD_BY_RATE_OFF_VHT_TH_SH 6 +#define B_AX_DPD_BY_RATE_OFF_VHT_TH_MSK 0xf +#define B_AX_DPD_BY_RATE_OFF_HT_BELOW_TH_VAL BIT(5) +#define B_AX_DPD_BY_RATE_OFF_HT_OV_TH_VAL BIT(4) +#define B_AX_DPD_BY_RATE_OFF_HT_TH_SH 0 +#define B_AX_DPD_BY_RATE_OFF_HT_TH_MSK 0xf + +#define R_AX_PWR_SR_CTRL0 0xD238 +#define R_AX_PWR_SR_CTRL0_C1 0xF238 +#define B_AX_SR_PWR_CTRL_DBG_EN BIT(31) +#define B_AX_SR_RATE_TBL_RD_MCS_TXDIFF_SH 20 +#define B_AX_SR_RATE_TBL_RD_MCS_TXDIFF_MSK 0x1f +#define B_AX_SR_RATE_MAP_TBL_RD_MCS_SEL BIT(19) +#define B_AX_TXPWR_SR_FORCE_OFF BIT(18) +#define B_AX_TXPWR_STA_UL_FORCE_OFF BIT(17) +#define B_AX_SR_TXPWR_PD_WITH_PD_MACID BIT(16) +#define B_AX_SR_RATE_MAP_TBL_RD BIT(15) +#define B_AX_SR_RATE_MAP_TBL_RD_MCS_SH 11 +#define B_AX_SR_RATE_MAP_TBL_RD_MCS_MSK 0xf +#define B_AX_TXPWR_CTRL_NORM_RESP_DBG_EN BIT(10) +#define B_AX_TXAGC_PSEUDO_PWR_EN BIT(9) +#define B_AX_TXAGC_PSEUDO_PWR_SH 0 +#define B_AX_TXAGC_PSEUDO_PWR_MSK 0x1ff + +#define R_AX_PWR_SR_CTRL1 0xD23C +#define R_AX_PWR_SR_CTRL1_C1 0xF23C +#define B_AX_MCS_TH_HE_SH 24 +#define B_AX_MCS_TH_HE_MSK 0xf +#define B_AX_MCS_TH_VHT_SH 20 +#define B_AX_MCS_TH_VHT_MSK 0xf +#define B_AX_MCS_TH_HT_MOD8_SH 16 +#define B_AX_MCS_TH_HT_MOD8_MSK 0xf +#define B_AX_MCS_TH_LEGACY_SH 12 +#define B_AX_MCS_TH_LEGACY_MSK 0xf +#define B_AX_MCS_TH_CCK_SH 8 +#define B_AX_MCS_TH_CCK_MSK 0xf +#define B_AX_TXPWR_REF_SH 0 +#define B_AX_TXPWR_REF_MSK 0x7f + +#define R_AX_PWR_UL_CTRL0 0xD240 +#define R_AX_PWR_UL_CTRL0_C1 0xF240 +#define B_AX_PL_TOLER_RANGE_SH 20 +#define B_AX_PL_TOLER_RANGE_MSK 0x1ff +#define B_AX_PWR_BB_MIN_DBM_SH 9 +#define B_AX_PWR_BB_MIN_DBM_MSK 0x1ff +#define B_AX_PWR_ERROR_TOLER_SH 0 +#define B_AX_PWR_ERROR_TOLER_MSK 0xff + +#define R_AX_PWR_UL_CTRL1 0xD244 +#define R_AX_PWR_UL_CTRL1_C1 0xF244 +#define B_AX_MACID3_SH 24 +#define B_AX_MACID3_MSK 0x7f +#define B_AX_MACID2_SH 16 +#define B_AX_MACID2_MSK 0x7f +#define B_AX_MACID1_SH 8 +#define B_AX_MACID1_MSK 0x7f +#define B_AX_MACID0_SH 0 +#define B_AX_MACID0_MSK 0x7f + +#define R_AX_PWR_UL_CTRL2 0xD248 +#define R_AX_PWR_UL_CTRL2_C1 0xF248 +#define B_AX_CFO_COMP_SR_SH 24 +#define B_AX_CFO_COMP_SR_MSK 0x7 +#define B_AX_CFO_COMP_NORM_RESP_SH 20 +#define B_AX_CFO_COMP_NORM_RESP_MSK 0x7 +#define B_AX_CFO_COMP4_SH 16 +#define B_AX_CFO_COMP4_MSK 0x7 +#define B_AX_CFO_COMP3_SH 12 +#define B_AX_CFO_COMP3_MSK 0x7 +#define B_AX_CFO_COMP2_SH 8 +#define B_AX_CFO_COMP2_MSK 0x7 +#define B_AX_CFO_COMP1_SH 4 +#define B_AX_CFO_COMP1_MSK 0x7 +#define B_AX_CFO_COMP0_SH 0 +#define B_AX_CFO_COMP0_MSK 0x7 + +#define R_AX_PWR_UL_CTRL3 0xD24C +#define R_AX_PWR_UL_CTRL3_C1 0xF24C +#define B_AX_TF_RDY_TXBF_FORCE_OFF BIT(22) +#define B_AX_FORCE_PL_UPPER_EN_EQUL_N_TX_DIVIDE2 BIT(21) +#define B_AX_FORCE_N_TX_DIVIDE2_OFF BIT(20) +#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MAX_SH 11 +#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MAX_MSK 0x1ff +#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MIN_SH 0 +#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MIN_MSK 0x1ff + +#define R_AX_PWR_UL_CTRL4 0xD250 +#define R_AX_PWR_UL_CTRL4_C1 0xF250 +#define B_AX_STA_PWR_CTRL_RPL_LIM_MIN_SH 16 +#define B_AX_STA_PWR_CTRL_RPL_LIM_MIN_MSK 0x3ff +#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MAX_SH 8 +#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MAX_MSK 0xff +#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MIN_SH 0 +#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MIN_MSK 0xff + +#define R_AX_PWR_UL_CTRL5 0xD254 +#define R_AX_PWR_UL_CTRL5_C1 0xF254 +#define B_AX_FORCE_PL_UPPER_EN_VAL BIT(23) +#define B_AX_FORCE_PL_UPPER_EN_ON BIT(22) +#define B_AX_SR_TXPWR_RESP_RDY_FORCE_OFF BIT(15) +#define B_AX_SR_TXPWR_PD_RDY_FORCE_OFF BIT(14) +#define B_AX_SR_TXPWR_RATE_RDY_FORCE_OFF BIT(13) +#define B_AX_TF_RDY_FORCE_OFF BIT(12) +#define B_AX_TXCTRL_INFO_RDY_FORCE_OFF BIT(11) +#define B_AX_STA_PWR_CTRL_DBG_EN BIT(10) +#define B_AX_STA_PWR_CTRL_RPL_LIM_MAX_SH 0 +#define B_AX_STA_PWR_CTRL_RPL_LIM_MAX_MSK 0x3ff + +#define R_AX_PWR_UL_CTRL6 0xD258 +#define R_AX_PWR_UL_CTRL6_C1 0xF258 +#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MIN_SH 24 +#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MIN_MSK 0x7f +#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MAX_SH 16 +#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MAX_MSK 0x7f +#define B_AX_TXPWR_FORCE_RATE_EN BIT(12) +#define B_AX_TXPWR_FORCE_RATE_SH 0 +#define B_AX_TXPWR_FORCE_RATE_MSK 0xfff + +#define R_AX_PWR_NORM_FORCE0 0xD25C +#define R_AX_PWR_NORM_FORCE0_C1 0xF25C +#define B_AX_FORCE_MACID_EN BIT(30) +#define B_AX_FORCE_MACID_VALUE_SH 23 +#define B_AX_FORCE_MACID_VALUE_MSK 0x7f +#define B_AX_FORCE_BW80P80_EN_EN BIT(22) +#define B_AX_FORCE_BW80P80_EN_VALUE BIT(21) +#define B_AX_FORCE_RF_BW_IDX_EN BIT(20) +#define B_AX_FORCE_RF_BW_IDX_VALUE_SH 18 +#define B_AX_FORCE_RF_BW_IDX_VALUE_MSK 0x3 +#define B_AX_FORCE_DCM_EN BIT(17) +#define B_AX_FORCE_DCM_VALUE BIT(16) +#define B_AX_FORCE_DBW_IDX_EN BIT(15) +#define B_AX_FORCE_DBW_IDX_VALUE_SH 13 +#define B_AX_FORCE_DBW_IDX_VALUE_MSK 0x3 +#define B_AX_FORCE_MAX_RATE_EN BIT(12) +#define B_AX_FORCE_MAX_RATE_VALUE_SH 0 +#define B_AX_FORCE_MAX_RATE_VALUE_MSK 0xfff + +#define R_AX_PWR_NORM_FORCE1 0xD260 +#define R_AX_PWR_NORM_FORCE1_C1 0xF260 +#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29) +#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_SH 24 +#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MSK 0x1f +#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23) +#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22) +#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21) +#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20) +#define B_AX_FORCE_BT_GRANT_EN BIT(19) +#define B_AX_FORCE_BT_GRANT_VALUE BIT(18) +#define B_AX_FORCE_RX_LTE_EN BIT(17) +#define B_AX_FORCE_RX_LTE_VALUE BIT(16) +#define B_AX_FORCE_TXBF_EN_EN BIT(15) +#define B_AX_FORCE_TXBF_EN_VALUE BIT(14) +#define B_AX_FORCE_TXSC_EN BIT(13) +#define B_AX_FORCE_TXSC_VALUE_SH 9 +#define B_AX_FORCE_TXSC_VALUE_MSK 0xf +#define B_AX_FORCE_NTX_EN BIT(6) +#define B_AX_FORCE_NTX_VALUE BIT(5) +#define B_AX_FORCE_PWR_MODE_EN BIT(3) +#define B_AX_FORCE_PWR_MODE_VALUE_SH 0 +#define B_AX_FORCE_PWR_MODE_VALUE_MSK 0x7 + +#define R_AX_PWR_SR_FORCE0 0xD264 +#define R_AX_PWR_SR_FORCE0_C1 0xF264 +#define B_AX_FORCE_SR_RESP_DCM_EN BIT(30) +#define B_AX_FORCE_SR_RESP_DCM_VALUE BIT(29) +#define B_AX_FORCE_SR_RATE_DCM_EN BIT(28) +#define B_AX_FORCE_SR_RATE_DCM_VALUE BIT(27) +#define B_AX_FORCE_SR_TXPWR_PD_EN BIT(26) +#define B_AX_FORCE_SR_TXPWR_PD_VALUE_SH 20 +#define B_AX_FORCE_SR_TXPWR_PD_VALUE_MSK 0x3f +#define B_AX_FORCE_SR_RATE_IDX_EN BIT(19) +#define B_AX_FORCE_SR_RATE_IDX_VALUE_SH 7 +#define B_AX_FORCE_SR_RATE_IDX_VALUE_MSK 0xfff +#define B_AX_FORCE_SR_TXPWR_TOLERANCE_EN BIT(6) +#define B_AX_FORCE_SR_TXPWR_TOLERANCE_VALUE_SH 0 +#define B_AX_FORCE_SR_TXPWR_TOLERANCE_VALUE_MSK 0x3f + +#define R_AX_PWR_SR_FORCE1 0xD268 +#define R_AX_PWR_SR_FORCE1_C1 0xF268 +#define B_AX_FORCE_RPL_EN BIT(29) +#define B_AX_FORCE_RPL_VALUE_SH 20 +#define B_AX_FORCE_RPL_VALUE_MSK 0x1ff +#define B_AX_FORCE_SR_RESP_RATE_IDX_EN BIT(19) +#define B_AX_FORCE_SR_RESP_RATE_IDX_VALUE_SH 7 +#define B_AX_FORCE_SR_RESP_RATE_IDX_VALUE_MSK 0xfff +#define B_AX_FORCE_SR_RESP_TXPWR_PD_EN BIT(6) +#define B_AX_FORCE_SR_RESP_TXPWR_PD_VALUE_SH 0 +#define B_AX_FORCE_SR_RESP_TXPWR_PD_VALUE_MSK 0x3f + +#define R_AX_PWR_SR_FORCE2 0xD26C +#define R_AX_PWR_SR_FORCE2_C1 0xF26C +#define B_AX_FORCE_TF_AP_TX_PWR_EN BIT(31) +#define B_AX_FORCE_TF_AP_TX_PWR_VALUE_SH 25 +#define B_AX_FORCE_TF_AP_TX_PWR_VALUE_MSK 0x3f +#define B_AX_FORCE_TF_RATE_IDX_EN BIT(24) +#define B_AX_FORCE_TF_RATE_IDX_VALUE_SH 12 +#define B_AX_FORCE_TF_RATE_IDX_VALUE_MSK 0xfff +#define B_AX_FORCE_RPL_UPPER_EN_EN BIT(11) +#define B_AX_FORCE_RPL_UPPER_EN_VALUE BIT(10) +#define B_AX_FORCE_RPL_UPPER_EN BIT(9) +#define B_AX_FORCE_RPL_UPPER_VALUE_SH 0 +#define B_AX_FORCE_RPL_UPPER_VALUE_MSK 0x1ff + +#define R_AX_PWR_UL_FORCE0 0xD270 +#define R_AX_PWR_UL_FORCE0_C1 0xF270 +#define B_AX_FORCE_RU_ALLOC_EN BIT(24) +#define B_AX_FORCE_RU_ALLOC_VALUE_SH 16 +#define B_AX_FORCE_RU_ALLOC_VALUE_MSK 0xff +#define B_AX_FORCE_TF_MACID_EN BIT(15) +#define B_AX_FORCE_TF_MACID_VALUE_SH 8 +#define B_AX_FORCE_TF_MACID_VALUE_MSK 0x7f +#define B_AX_FORCE_TF_RSSI_TARGET_EN BIT(7) +#define B_AX_FORCE_TF_RSSI_TARGET_VALUE_SH 0 +#define B_AX_FORCE_TF_RSSI_TARGET_VALUE_MSK 0x7f + +#define R_AX_PWR_NORM_FORCE2 0xD274 +#define R_AX_PWR_NORM_FORCE2_C1 0xF274 +#define B_AX_FORCE_OUT_CCA_PWR_TH_EN_ON BIT(18) +#define B_AX_FORCE_OUT_CCA_PWR_TH_EN BIT(17) +#define B_AX_FORCE_OUT_CCA_PWR_TH_ON BIT(16) +#define B_AX_FORCE_OUT_CCA_PWR_TH_SH 8 +#define B_AX_FORCE_OUT_CCA_PWR_TH_MSK 0xff +#define B_AX_TXPWR_CTRL_DBG_SEL_SH 0 +#define B_AX_TXPWR_CTRL_DBG_SEL_MSK 0x3f + +#define R_AX_PWR_UL_FORCE1 0xD278 +#define R_AX_PWR_UL_FORCE1_C1 0xF278 +#define B_AX_FORCE_OUT_CFO_COMP_ON BIT(31) +#define B_AX_FORCE_OUT_CFO_COMP_SH 28 +#define B_AX_FORCE_OUT_CFO_COMP_MSK 0x7 +#define B_AX_FORCE_OUT_ABORT_TX_IDX_ON BIT(27) +#define B_AX_FORCE_OUT_ABORT_TX_IDX_SH 25 +#define B_AX_FORCE_OUT_ABORT_TX_IDX_MSK 0x3 +#define B_AX_FORCE_OUT_MIN_TX_PWR_FLAG_ON BIT(24) +#define B_AX_FORCE_OUT_MIN_TX_PWR_FLAG BIT(23) +#define B_AX_FORCE_OUT_UPH_ON BIT(22) +#define B_AX_FORCE_OUT_UPH_SH 17 +#define B_AX_FORCE_OUT_UPH_MSK 0x1f +#define B_AX_FORCE_OUT_STA_TXPWR_MAC_ON BIT(16) +#define B_AX_FORCE_OUT_STA_TXPWR_MAC_SH 10 +#define B_AX_FORCE_OUT_STA_TXPWR_MAC_MSK 0x3f +#define B_AX_FORCE_OUT_STA_TXPWR_BB_ON BIT(9) +#define B_AX_FORCE_OUT_STA_TXPWR_BB_SH 0 +#define B_AX_FORCE_OUT_STA_TXPWR_BB_MSK 0x1ff + +#define R_AX_PWR_NORM_FORCE3 0xD27C +#define R_AX_PWR_NORM_FORCE3_C1 0xF27C +#define B_AX_FORCE_OUT_TXAGC_BBSWING_ON BIT(31) +#define B_AX_FORCE_OUT_TXAGC_BBSWING_SH 27 +#define B_AX_FORCE_OUT_TXAGC_BBSWING_MSK 0xf +#define B_AX_FORCE_OUT_TXBIAS_ON BIT(26) +#define B_AX_FORCE_OUT_TXBIAS_SH 24 +#define B_AX_FORCE_OUT_TXBIAS_MSK 0x3 +#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_ON BIT(23) +#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_SH 18 +#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_MSK 0x1f +#define B_AX_FORCE_OUT_TXPWR_BB_ON BIT(17) +#define B_AX_FORCE_OUT_TXPWR_BB_SH 8 +#define B_AX_FORCE_OUT_TXPWR_BB_MSK 0x1ff +#define B_AX_FORCE_OUT_TXPWR_MAC_ON BIT(6) +#define B_AX_FORCE_OUT_TXPWR_MAC_SH 0 +#define B_AX_FORCE_OUT_TXPWR_MAC_MSK 0x3f + +#define R_AX_PWR_NORM_FORCE4 0xD280 +#define R_AX_PWR_NORM_FORCE4_C1 0xF280 +#define B_AX_FORCE_OUT_SR_DCM_ON BIT(25) +#define B_AX_FORCE_OUT_SR_DCM BIT(24) +#define B_AX_FORCE_OUT_SR_MCS_ON BIT(23) +#define B_AX_FORCE_OUT_SR_MCS_SH 11 +#define B_AX_FORCE_OUT_SR_MCS_MSK 0xfff +#define B_AX_FORCE_OUT_SR_PD_THREHOLD_ON BIT(10) +#define B_AX_FORCE_OUT_SR_PD_THREHOLD_SH 4 +#define B_AX_FORCE_OUT_SR_PD_THREHOLD_MSK 0x3f +#define B_AX_FORCE_OUT_CFIR_BY_RATE_OFF_ON BIT(3) +#define B_AX_FORCE_OUT_CFIR_BY_RATE_OFF BIT(2) +#define B_AX_FORCE_OUT_DPD_BY_RATE_OFF_ON BIT(1) +#define B_AX_FORCE_OUT_DPD_BY_RATE_OFF BIT(0) + +#define R_AX_PWR_RATE_TABLE0 0xD2C0 +#define R_AX_PWR_RATE_TABLE0_C1 0xF2C0 +#define B_AX_TXAGC_CCK11M_SH 24 +#define B_AX_TXAGC_CCK11M_MSK 0x1f +#define B_AX_TXAGC_CCK5P5M_SH 16 +#define B_AX_TXAGC_CCK5P5M_MSK 0x1f +#define B_AX_TXAGC_CCK2M_SH 8 +#define B_AX_TXAGC_CCK2M_MSK 0xf +#define B_AX_TXAGC_CCK1M_SH 0 +#define B_AX_TXAGC_CCK1M_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE1 0xD2C4 +#define R_AX_PWR_RATE_TABLE1_C1 0xF2C4 +#define B_AX_TXAGC_LEGACY18M_SH 24 +#define B_AX_TXAGC_LEGACY18M_MSK 0x1f +#define B_AX_TXAGC_LEGACY12M_SH 16 +#define B_AX_TXAGC_LEGACY12M_MSK 0x1f +#define B_AX_TXAGC_LEGACY9M_SH 8 +#define B_AX_TXAGC_LEGACY9M_MSK 0xf +#define B_AX_TXAGC_LEGACY6M_SH 0 +#define B_AX_TXAGC_LEGACY6M_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE2 0xD2C8 +#define R_AX_PWR_RATE_TABLE2_C1 0xF2C8 +#define B_AX_TXAGC_LEGACY54M_SH 24 +#define B_AX_TXAGC_LEGACY54M_MSK 0x1f +#define B_AX_TXAGC_LEGACY48M_SH 16 +#define B_AX_TXAGC_LEGACY48M_MSK 0x1f +#define B_AX_TXAGC_LEGACY36M_SH 8 +#define B_AX_TXAGC_LEGACY36M_MSK 0xf +#define B_AX_TXAGC_LEGACY24M_SH 0 +#define B_AX_TXAGC_LEGACY24M_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE3 0xD2CC +#define R_AX_PWR_RATE_TABLE3_C1 0xF2CC +#define B_AX_TXAGC_NONLEGACY_MCS3_NSS1_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS3_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS2_NSS1_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS2_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS1_NSS1_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS1_NSS1_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS0_NSS1_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS0_NSS1_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE4 0xD2D0 +#define R_AX_PWR_RATE_TABLE4_C1 0xF2D0 +#define B_AX_TXAGC_NONLEGACY_MCS7_NSS1_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS7_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS6_NSS1_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS6_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS5_NSS1_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS5_NSS1_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS4_NSS1_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS4_NSS1_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE5 0xD2D4 +#define R_AX_PWR_RATE_TABLE5_C1 0xF2D4 +#define B_AX_TXAGC_NONLEGACY_MCS11_NSS1_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS11_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS10_NSS1_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS10_NSS1_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS9_NSS1_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS9_NSS1_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS8_NSS1_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS8_NSS1_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE6 0xD2D8 +#define R_AX_PWR_RATE_TABLE6_C1 0xF2D8 +#define B_AX_TXAGC_DCM_MCS4_NSS1_SH 24 +#define B_AX_TXAGC_DCM_MCS4_NSS1_MSK 0x1f +#define B_AX_TXAGC_DCM_MCS3_NSS1_SH 16 +#define B_AX_TXAGC_DCM_MCS3_NSS1_MSK 0x1f +#define B_AX_TXAGC_DCM_MCS1_NSS1_SH 8 +#define B_AX_TXAGC_DCM_MCS1_NSS1_MSK 0xf +#define B_AX_TXAGC_DCM_MCS0_NSS1_SH 0 +#define B_AX_TXAGC_DCM_MCS0_NSS1_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE7 0xD2DC +#define R_AX_PWR_RATE_TABLE7_C1 0xF2DC +#define B_AX_TXAGC_NONLEGACY_MCS3_NSS2_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS3_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS2_NSS2_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS2_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS1_NSS2_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS1_NSS2_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS0_NSS2_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS0_NSS2_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE8 0xD2E0 +#define R_AX_PWR_RATE_TABLE8_C1 0xF2E0 +#define B_AX_TXAGC_NONLEGACY_MCS7_NSS2_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS7_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS6_NSS2_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS6_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS5_NSS2_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS5_NSS2_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS4_NSS2_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS4_NSS2_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE9 0xD2E4 +#define R_AX_PWR_RATE_TABLE9_C1 0xF2E4 +#define B_AX_TXAGC_NONLEGACY_MCS11_NSS2_SH 24 +#define B_AX_TXAGC_NONLEGACY_MCS11_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS10_NSS2_SH 16 +#define B_AX_TXAGC_NONLEGACY_MCS10_NSS2_MSK 0x1f +#define B_AX_TXAGC_NONLEGACY_MCS9_NSS2_SH 8 +#define B_AX_TXAGC_NONLEGACY_MCS9_NSS2_MSK 0xf +#define B_AX_TXAGC_NONLEGACY_MCS8_NSS2_SH 0 +#define B_AX_TXAGC_NONLEGACY_MCS8_NSS2_MSK 0x1f + +#define R_AX_PWR_RATE_TABLE10 0xD2E8 +#define R_AX_PWR_RATE_TABLE10_C1 0xF2E8 +#define B_AX_TXAGC_DCM_MCS4_NSS2_SH 24 +#define B_AX_TXAGC_DCM_MCS4_NSS2_MSK 0x1f +#define B_AX_TXAGC_DCM_MCS3_NSS2_SH 16 +#define B_AX_TXAGC_DCM_MCS3_NSS2_MSK 0x1f +#define B_AX_TXAGC_DCM_MCS1_NSS2_SH 8 +#define B_AX_TXAGC_DCM_MCS1_NSS2_MSK 0xf +#define B_AX_TXAGC_DCM_MCS0_NSS2_SH 0 +#define B_AX_TXAGC_DCM_MCS0_NSS2_MSK 0x1f + +#define R_AX_PWR_LMT_TABLE0 0xD2EC +#define R_AX_PWR_LMT_TABLE0_C1 0xF2EC +#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW40M_SH 24 +#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW40M_MSK 0x7f +#define B_AX_TXAGC_MAX_CCK_1TX_BW40M_SH 15 +#define B_AX_TXAGC_MAX_CCK_1TX_BW40M_MSK 0x7f +#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW20M_SH 8 +#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW20M_MSK 0x3f +#define B_AX_TXAGC_MAX_CCK_1TX_BW20M_SH 0 +#define B_AX_TXAGC_MAX_CCK_1TX_BW20M_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE1 0xD2F0 +#define R_AX_PWR_LMT_TABLE1_C1 0xF2F0 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_0_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW20_0_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW20_0_MSK 0x7f +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_1TX_SH 8 +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_1TX_MSK 0x3f +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_1TX_SH 0 +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_1TX_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE2 0xD2F4 +#define R_AX_PWR_LMT_TABLE2_C1 0xF2F4 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_2_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_2_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW20_2_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW20_2_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW20_1_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_1_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW20_1_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW20_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE3 0xD2F8 +#define R_AX_PWR_LMT_TABLE3_C1 0xF2F8 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_4_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_4_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW20_4_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW20_4_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW20_3_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_3_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW20_3_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW20_3_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE4 0xD2FC +#define R_AX_PWR_LMT_TABLE4_C1 0xF2FC +#define B_AX_TXAGC_MAX_1TX_BF_BW20_6_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_6_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW20_6_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW20_6_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW20_5_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_5_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW20_5_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW20_5_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE5 0xD300 +#define R_AX_PWR_LMT_TABLE5_C1 0xF300 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_0_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW40_0_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW40_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW20_7_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW20_7_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW20_7_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW20_7_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE6 0xD304 +#define R_AX_PWR_LMT_TABLE6_C1 0xF304 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_2_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_2_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW40_2_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW40_2_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW40_1_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_1_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW40_1_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW40_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE7 0xD308 +#define R_AX_PWR_LMT_TABLE7_C1 0xF308 +#define B_AX_TXAGC_MAX_1TX_BF_BW80_0_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW80_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW80_0_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW80_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW40_3_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_3_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW40_3_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW40_3_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE8 0xD30C +#define R_AX_PWR_LMT_TABLE8_C1 0xF30C +#define B_AX_TXAGC_MAX_1TX_BF_BW160_0_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW160_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW160_0_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW160_0_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW80_1_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW80_1_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW80_1_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW80_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE9 0xD310 +#define R_AX_PWR_LMT_TABLE9_C1 0xF310 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_2P5_SH 24 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_2P5_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BW40_2P5_SH 15 +#define B_AX_TXAGC_MAX_1TX_BW40_2P5_MSK 0x7f +#define B_AX_TXAGC_MAX_1TX_BF_BW40_0P5_SH 8 +#define B_AX_TXAGC_MAX_1TX_BF_BW40_0P5_MSK 0x3f +#define B_AX_TXAGC_MAX_1TX_BW40_0P5_SH 0 +#define B_AX_TXAGC_MAX_1TX_BW40_0P5_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE10 0xD314 +#define R_AX_PWR_LMT_TABLE10_C1 0xF314 +#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW40M_SH 24 +#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW40M_MSK 0x7f +#define B_AX_TXAGC_MAX_CCK_2TX_BW40M_SH 15 +#define B_AX_TXAGC_MAX_CCK_2TX_BW40M_MSK 0x7f +#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW20M_SH 8 +#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW20M_MSK 0x3f +#define B_AX_TXAGC_MAX_CCK_2TX_BW20M_SH 0 +#define B_AX_TXAGC_MAX_CCK_2TX_BW20M_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE11 0xD318 +#define R_AX_PWR_LMT_TABLE11_C1 0xF318 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_0_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW20_0_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW20_0_MSK 0x7f +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_2TX_SH 8 +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_2TX_MSK 0x3f +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_2TX_SH 0 +#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_2TX_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE12 0xD31C +#define R_AX_PWR_LMT_TABLE12_C1 0xF31C +#define B_AX_TXAGC_MAX_2TX_BF_BW20_2_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_2_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW20_2_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW20_2_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW20_1_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_1_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW20_1_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW20_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE13 0xD320 +#define R_AX_PWR_LMT_TABLE13_C1 0xF320 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_4_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_4_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW20_4_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW20_4_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW20_3_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_3_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW20_3_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW20_3_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE14 0xD324 +#define R_AX_PWR_LMT_TABLE14_C1 0xF324 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_6_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_6_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW20_6_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW20_6_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW20_5_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_5_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW20_5_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW20_5_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE15 0xD328 +#define R_AX_PWR_LMT_TABLE15_C1 0xF328 +#define B_AX_TXAGC_MAX_2TX_BF_BW40_0_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW40_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW40_0_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW40_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW20_7_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW20_7_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW20_7_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW20_7_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE16 0xD32C +#define R_AX_PWR_LMT_TABLE16_C1 0xF32C +#define B_AX_TXAGC_MAX_2TX_BF_BW40_2_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW40_2_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW40_2_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW40_2_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW40_1_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW40_1_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW40_1_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW40_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE17 0xD330 +#define R_AX_PWR_LMT_TABLE17_C1 0xF330 +#define B_AX_TXAGC_MAX_2TX_BF_BW80_0_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW80_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW80_0_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW80_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW40_3_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW40_3_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW40_3_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW40_3_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE18 0xD334 +#define R_AX_PWR_LMT_TABLE18_C1 0xF334 +#define B_AX_TXAGC_MAX_2TX_BF_BW160_0_SH 24 +#define B_AX_TXAGC_MAX_2TX_BF_BW160_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BW160_0_SH 15 +#define B_AX_TXAGC_MAX_2TX_BW160_0_MSK 0x7f +#define B_AX_TXAGC_MAX_2TX_BF_BW80_1_SH 8 +#define B_AX_TXAGC_MAX_2TX_BF_BW80_1_MSK 0x3f +#define B_AX_TXAGC_MAX_2TX_BW80_1_SH 0 +#define B_AX_TXAGC_MAX_2TX_BW80_1_MSK 0x7f + +#define R_AX_PWR_LMT_TABLE19 0xD338 +#define R_AX_PWR_LMT_TABLE19_C1 0xF338 + +#define R_AX_PWR_RU_LMT_TABLE0 0xD33C +#define R_AX_PWR_RU_LMT_TABLE0_C1 0xF33C +#define B_AX_TXAGC_RU_1TX_RFBW80_0_SH 24 +#define B_AX_TXAGC_RU_1TX_RFBW80_0_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW40_1_SH 15 +#define B_AX_TXAGC_RU_1TX_RFBW40_1_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW40_0_SH 8 +#define B_AX_TXAGC_RU_1TX_RFBW40_0_MSK 0x3f +#define B_AX_TXAGC_RU_1TX_RFBW20_0_SH 0 +#define B_AX_TXAGC_RU_1TX_RFBW20_0_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE1 0xD340 +#define R_AX_PWR_RU_LMT_TABLE1_C1 0xF340 +#define B_AX_TXAGC_RU_1TX_RFBW160_0_SH 24 +#define B_AX_TXAGC_RU_1TX_RFBW160_0_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW80_3_SH 15 +#define B_AX_TXAGC_RU_1TX_RFBW80_3_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW80_2_SH 8 +#define B_AX_TXAGC_RU_1TX_RFBW80_2_MSK 0x3f +#define B_AX_TXAGC_RU_1TX_RFBW80_1_SH 0 +#define B_AX_TXAGC_RU_1TX_RFBW80_1_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE2 0xD344 +#define R_AX_PWR_RU_LMT_TABLE2_C1 0xF344 +#define B_AX_TXAGC_RU_1TX_RFBW160_4_SH 24 +#define B_AX_TXAGC_RU_1TX_RFBW160_4_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW160_3_SH 15 +#define B_AX_TXAGC_RU_1TX_RFBW160_3_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW160_2_SH 8 +#define B_AX_TXAGC_RU_1TX_RFBW160_2_MSK 0x3f +#define B_AX_TXAGC_RU_1TX_RFBW160_1_SH 0 +#define B_AX_TXAGC_RU_1TX_RFBW160_1_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE3 0xD348 +#define R_AX_PWR_RU_LMT_TABLE3_C1 0xF348 +#define B_AX_TXAGC_RU_2TX_RFBW20_0_SH 24 +#define B_AX_TXAGC_RU_2TX_RFBW20_0_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW160_7_SH 15 +#define B_AX_TXAGC_RU_1TX_RFBW160_7_MSK 0x7f +#define B_AX_TXAGC_RU_1TX_RFBW160_6_SH 8 +#define B_AX_TXAGC_RU_1TX_RFBW160_6_MSK 0x3f +#define B_AX_TXAGC_RU_1TX_RFBW160_5_SH 0 +#define B_AX_TXAGC_RU_1TX_RFBW160_5_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE4 0xD34C +#define R_AX_PWR_RU_LMT_TABLE4_C1 0xF34C +#define B_AX_TXAGC_RU_2TX_RFBW80_2_SH 24 +#define B_AX_TXAGC_RU_2TX_RFBW80_2_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW80_1_SH 15 +#define B_AX_TXAGC_RU_2TX_RFBW80_1_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW80_0_SH 8 +#define B_AX_TXAGC_RU_2TX_RFBW80_0_MSK 0x3f +#define B_AX_TXAGC_RU_2TX_RFBW40_1_SH 0 +#define B_AX_TXAGC_RU_2TX_RFBW40_1_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE5 0xD350 +#define R_AX_PWR_RU_LMT_TABLE5_C1 0xF350 +#define B_AX_TXAGC_RU_2TX_RFBW160_2_SH 24 +#define B_AX_TXAGC_RU_2TX_RFBW160_2_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW160_1_SH 15 +#define B_AX_TXAGC_RU_2TX_RFBW160_1_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW160_0_SH 8 +#define B_AX_TXAGC_RU_2TX_RFBW160_0_MSK 0x3f +#define B_AX_TXAGC_RU_2TX_RFBW80_3_SH 0 +#define B_AX_TXAGC_RU_2TX_RFBW80_3_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE6 0xD354 +#define R_AX_PWR_RU_LMT_TABLE6_C1 0xF354 +#define B_AX_TXAGC_RU_2TX_RFBW160_6_SH 24 +#define B_AX_TXAGC_RU_2TX_RFBW160_6_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW160_5_SH 15 +#define B_AX_TXAGC_RU_2TX_RFBW160_5_MSK 0x7f +#define B_AX_TXAGC_RU_2TX_RFBW160_4_SH 8 +#define B_AX_TXAGC_RU_2TX_RFBW160_4_MSK 0x3f +#define B_AX_TXAGC_RU_2TX_RFBW160_3_SH 0 +#define B_AX_TXAGC_RU_2TX_RFBW160_3_MSK 0x7f + +#define R_AX_PWR_RU_LMT_TABLE7 0xD358 +#define R_AX_PWR_RU_LMT_TABLE7_C1 0xF358 +#define B_AX_TXAGC_RU_2TX_RFBW160_7_SH 0 +#define B_AX_TXAGC_RU_2TX_RFBW160_7_MSK 0x7f + +#define R_AX_PWR_MACID_TABLE0 0xD35C +#define R_AX_PWR_MACID_TABLE0_C1 0xF35C +#define B_AX_MACID_0_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_0_TXPWR1_EN BIT(25) +#define B_AX_MACID_0_TXPWR0_EN BIT(24) +#define B_AX_MACID_0_CCA_PWR_TH_SH 16 +#define B_AX_MACID_0_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_0_TXPWR1_SH 8 +#define B_AX_MACID_0_TXPWR1_MSK 0xff +#define B_AX_MACID_0_TXPWR0_SH 0 +#define B_AX_MACID_0_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE1 0xD360 +#define R_AX_PWR_MACID_TABLE1_C1 0xF360 +#define B_AX_MACID_1_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_1_TXPWR1_EN BIT(25) +#define B_AX_MACID_1_TXPWR0_EN BIT(24) +#define B_AX_MACID_1_CCA_PWR_TH_SH 16 +#define B_AX_MACID_1_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_1_TXPWR1_SH 8 +#define B_AX_MACID_1_TXPWR1_MSK 0xff +#define B_AX_MACID_1_TXPWR0_SH 0 +#define B_AX_MACID_1_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE2 0xD364 +#define R_AX_PWR_MACID_TABLE2_C1 0xF364 +#define B_AX_MACID_2_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_2_TXPWR1_EN BIT(25) +#define B_AX_MACID_2_TXPWR0_EN BIT(24) +#define B_AX_MACID_2_CCA_PWR_TH_SH 16 +#define B_AX_MACID_2_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_2_TXPWR1_SH 8 +#define B_AX_MACID_2_TXPWR1_MSK 0xff +#define B_AX_MACID_2_TXPWR0_SH 0 +#define B_AX_MACID_2_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE3 0xD368 +#define R_AX_PWR_MACID_TABLE3_C1 0xF368 +#define B_AX_MACID_3_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_3_TXPWR1_EN BIT(25) +#define B_AX_MACID_3_TXPWR0_EN BIT(24) +#define B_AX_MACID_3_CCA_PWR_TH_SH 16 +#define B_AX_MACID_3_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_3_TXPWR1_SH 8 +#define B_AX_MACID_3_TXPWR1_MSK 0xff +#define B_AX_MACID_3_TXPWR0_SH 0 +#define B_AX_MACID_3_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE4 0xD36C +#define R_AX_PWR_MACID_TABLE4_C1 0xF36C +#define B_AX_MACID_4_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_4_TXPWR1_EN BIT(25) +#define B_AX_MACID_4_TXPWR0_EN BIT(24) +#define B_AX_MACID_4_CCA_PWR_TH_SH 16 +#define B_AX_MACID_4_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_4_TXPWR1_SH 8 +#define B_AX_MACID_4_TXPWR1_MSK 0xff +#define B_AX_MACID_4_TXPWR0_SH 0 +#define B_AX_MACID_4_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE5 0xD370 +#define R_AX_PWR_MACID_TABLE5_C1 0xF370 +#define B_AX_MACID_5_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_5_TXPWR1_EN BIT(25) +#define B_AX_MACID_5_TXPWR0_EN BIT(24) +#define B_AX_MACID_5_CCA_PWR_TH_SH 16 +#define B_AX_MACID_5_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_5_TXPWR1_SH 8 +#define B_AX_MACID_5_TXPWR1_MSK 0xff +#define B_AX_MACID_5_TXPWR0_SH 0 +#define B_AX_MACID_5_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE6 0xD374 +#define R_AX_PWR_MACID_TABLE6_C1 0xF374 +#define B_AX_MACID_6_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_6_TXPWR1_EN BIT(25) +#define B_AX_MACID_6_TXPWR0_EN BIT(24) +#define B_AX_MACID_6_CCA_PWR_TH_SH 16 +#define B_AX_MACID_6_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_6_TXPWR1_SH 8 +#define B_AX_MACID_6_TXPWR1_MSK 0xff +#define B_AX_MACID_6_TXPWR0_SH 0 +#define B_AX_MACID_6_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE7 0xD378 +#define R_AX_PWR_MACID_TABLE7_C1 0xF378 +#define B_AX_MACID_7_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_7_TXPWR1_EN BIT(25) +#define B_AX_MACID_7_TXPWR0_EN BIT(24) +#define B_AX_MACID_7_CCA_PWR_TH_SH 16 +#define B_AX_MACID_7_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_7_TXPWR1_SH 8 +#define B_AX_MACID_7_TXPWR1_MSK 0xff +#define B_AX_MACID_7_TXPWR0_SH 0 +#define B_AX_MACID_7_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE8 0xD37C +#define R_AX_PWR_MACID_TABLE8_C1 0xF37C +#define B_AX_MACID_8_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_8_TXPWR1_EN BIT(25) +#define B_AX_MACID_8_TXPWR0_EN BIT(24) +#define B_AX_MACID_8_CCA_PWR_TH_SH 16 +#define B_AX_MACID_8_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_8_TXPWR1_SH 8 +#define B_AX_MACID_8_TXPWR1_MSK 0xff +#define B_AX_MACID_8_TXPWR0_SH 0 +#define B_AX_MACID_8_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE9 0xD380 +#define R_AX_PWR_MACID_TABLE9_C1 0xF380 +#define B_AX_MACID_9_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_9_TXPWR1_EN BIT(25) +#define B_AX_MACID_9_TXPWR0_EN BIT(24) +#define B_AX_MACID_9_CCA_PWR_TH_SH 16 +#define B_AX_MACID_9_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_9_TXPWR1_SH 8 +#define B_AX_MACID_9_TXPWR1_MSK 0xff +#define B_AX_MACID_9_TXPWR0_SH 0 +#define B_AX_MACID_9_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE10 0xD384 +#define R_AX_PWR_MACID_TABLE10_C1 0xF384 +#define B_AX_MACID_10_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_10_TXPWR1_EN BIT(25) +#define B_AX_MACID_10_TXPWR0_EN BIT(24) +#define B_AX_MACID_10_CCA_PWR_TH_SH 16 +#define B_AX_MACID_10_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_10_TXPWR1_SH 8 +#define B_AX_MACID_10_TXPWR1_MSK 0xff +#define B_AX_MACID_10_TXPWR0_SH 0 +#define B_AX_MACID_10_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE11 0xD388 +#define R_AX_PWR_MACID_TABLE11_C1 0xF388 +#define B_AX_MACID_11_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_11_TXPWR1_EN BIT(25) +#define B_AX_MACID_11_TXPWR0_EN BIT(24) +#define B_AX_MACID_11_CCA_PWR_TH_SH 16 +#define B_AX_MACID_11_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_11_TXPWR1_SH 8 +#define B_AX_MACID_11_TXPWR1_MSK 0xff +#define B_AX_MACID_11_TXPWR0_SH 0 +#define B_AX_MACID_11_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE12 0xD38C +#define R_AX_PWR_MACID_TABLE12_C1 0xF38C +#define B_AX_MACID_12_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_12_TXPWR1_EN BIT(25) +#define B_AX_MACID_12_TXPWR0_EN BIT(24) +#define B_AX_MACID_12_CCA_PWR_TH_SH 16 +#define B_AX_MACID_12_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_12_TXPWR1_SH 8 +#define B_AX_MACID_12_TXPWR1_MSK 0xff +#define B_AX_MACID_12_TXPWR0_SH 0 +#define B_AX_MACID_12_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE13 0xD390 +#define R_AX_PWR_MACID_TABLE13_C1 0xF390 +#define B_AX_MACID_13_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_13_TXPWR1_EN BIT(25) +#define B_AX_MACID_13_TXPWR0_EN BIT(24) +#define B_AX_MACID_13_CCA_PWR_TH_SH 16 +#define B_AX_MACID_13_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_13_TXPWR1_SH 8 +#define B_AX_MACID_13_TXPWR1_MSK 0xff +#define B_AX_MACID_13_TXPWR0_SH 0 +#define B_AX_MACID_13_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE14 0xD394 +#define R_AX_PWR_MACID_TABLE14_C1 0xF394 +#define B_AX_MACID_14_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_14_TXPWR1_EN BIT(25) +#define B_AX_MACID_14_TXPWR0_EN BIT(24) +#define B_AX_MACID_14_CCA_PWR_TH_SH 16 +#define B_AX_MACID_14_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_14_TXPWR1_SH 8 +#define B_AX_MACID_14_TXPWR1_MSK 0xff +#define B_AX_MACID_14_TXPWR0_SH 0 +#define B_AX_MACID_14_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE15 0xD398 +#define R_AX_PWR_MACID_TABLE15_C1 0xF398 +#define B_AX_MACID_15_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_15_TXPWR1_EN BIT(25) +#define B_AX_MACID_15_TXPWR0_EN BIT(24) +#define B_AX_MACID_15_CCA_PWR_TH_SH 16 +#define B_AX_MACID_15_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_15_TXPWR1_SH 8 +#define B_AX_MACID_15_TXPWR1_MSK 0xff +#define B_AX_MACID_15_TXPWR0_SH 0 +#define B_AX_MACID_15_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE16 0xD39C +#define R_AX_PWR_MACID_TABLE16_C1 0xF39C +#define B_AX_MACID_16_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_16_TXPWR1_EN BIT(25) +#define B_AX_MACID_16_TXPWR0_EN BIT(24) +#define B_AX_MACID_16_CCA_PWR_TH_SH 16 +#define B_AX_MACID_16_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_16_TXPWR1_SH 8 +#define B_AX_MACID_16_TXPWR1_MSK 0xff +#define B_AX_MACID_16_TXPWR0_SH 0 +#define B_AX_MACID_16_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE17 0xD3A0 +#define R_AX_PWR_MACID_TABLE17_C1 0xF3A0 +#define B_AX_MACID_17_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_17_TXPWR1_EN BIT(25) +#define B_AX_MACID_17_TXPWR0_EN BIT(24) +#define B_AX_MACID_17_CCA_PWR_TH_SH 16 +#define B_AX_MACID_17_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_17_TXPWR1_SH 8 +#define B_AX_MACID_17_TXPWR1_MSK 0xff +#define B_AX_MACID_17_TXPWR0_SH 0 +#define B_AX_MACID_17_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE18 0xD3A4 +#define R_AX_PWR_MACID_TABLE18_C1 0xF3A4 +#define B_AX_MACID_18_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_18_TXPWR1_EN BIT(25) +#define B_AX_MACID_18_TXPWR0_EN BIT(24) +#define B_AX_MACID_18_CCA_PWR_TH_SH 16 +#define B_AX_MACID_18_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_18_TXPWR1_SH 8 +#define B_AX_MACID_18_TXPWR1_MSK 0xff +#define B_AX_MACID_18_TXPWR0_SH 0 +#define B_AX_MACID_18_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE19 0xD3A8 +#define R_AX_PWR_MACID_TABLE19_C1 0xF3A8 +#define B_AX_MACID_19_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_19_TXPWR1_EN BIT(25) +#define B_AX_MACID_19_TXPWR0_EN BIT(24) +#define B_AX_MACID_19_CCA_PWR_TH_SH 16 +#define B_AX_MACID_19_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_19_TXPWR1_SH 8 +#define B_AX_MACID_19_TXPWR1_MSK 0xff +#define B_AX_MACID_19_TXPWR0_SH 0 +#define B_AX_MACID_19_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE20 0xD3AC +#define R_AX_PWR_MACID_TABLE20_C1 0xF3AC +#define B_AX_MACID_20_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_20_TXPWR1_EN BIT(25) +#define B_AX_MACID_20_TXPWR0_EN BIT(24) +#define B_AX_MACID_20_CCA_PWR_TH_SH 16 +#define B_AX_MACID_20_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_20_TXPWR1_SH 8 +#define B_AX_MACID_20_TXPWR1_MSK 0xff +#define B_AX_MACID_20_TXPWR0_SH 0 +#define B_AX_MACID_20_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE21 0xD3B0 +#define R_AX_PWR_MACID_TABLE21_C1 0xF3B0 +#define B_AX_MACID_21_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_21_TXPWR1_EN BIT(25) +#define B_AX_MACID_21_TXPWR0_EN BIT(24) +#define B_AX_MACID_21_CCA_PWR_TH_SH 16 +#define B_AX_MACID_21_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_21_TXPWR1_SH 8 +#define B_AX_MACID_21_TXPWR1_MSK 0xff +#define B_AX_MACID_21_TXPWR0_SH 0 +#define B_AX_MACID_21_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE22 0xD3B4 +#define R_AX_PWR_MACID_TABLE22_C1 0xF3B4 +#define B_AX_MACID_22_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_22_TXPWR1_EN BIT(25) +#define B_AX_MACID_22_TXPWR0_EN BIT(24) +#define B_AX_MACID_22_CCA_PWR_TH_SH 16 +#define B_AX_MACID_22_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_22_TXPWR1_SH 8 +#define B_AX_MACID_22_TXPWR1_MSK 0xff +#define B_AX_MACID_22_TXPWR0_SH 0 +#define B_AX_MACID_22_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE23 0xD3B8 +#define R_AX_PWR_MACID_TABLE23_C1 0xF3B8 +#define B_AX_MACID_23_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_23_TXPWR1_EN BIT(25) +#define B_AX_MACID_23_TXPWR0_EN BIT(24) +#define B_AX_MACID_23_CCA_PWR_TH_SH 16 +#define B_AX_MACID_23_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_23_TXPWR1_SH 8 +#define B_AX_MACID_23_TXPWR1_MSK 0xff +#define B_AX_MACID_23_TXPWR0_SH 0 +#define B_AX_MACID_23_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE24 0xD3BC +#define R_AX_PWR_MACID_TABLE24_C1 0xF3BC +#define B_AX_MACID_24_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_24_TXPWR1_EN BIT(25) +#define B_AX_MACID_24_TXPWR0_EN BIT(24) +#define B_AX_MACID_24_CCA_PWR_TH_SH 16 +#define B_AX_MACID_24_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_24_TXPWR1_SH 8 +#define B_AX_MACID_24_TXPWR1_MSK 0xff +#define B_AX_MACID_24_TXPWR0_SH 0 +#define B_AX_MACID_24_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE25 0xD3C0 +#define R_AX_PWR_MACID_TABLE25_C1 0xF3C0 +#define B_AX_MACID_25_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_25_TXPWR1_EN BIT(25) +#define B_AX_MACID_25_TXPWR0_EN BIT(24) +#define B_AX_MACID_25_CCA_PWR_TH_SH 16 +#define B_AX_MACID_25_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_25_TXPWR1_SH 8 +#define B_AX_MACID_25_TXPWR1_MSK 0xff +#define B_AX_MACID_25_TXPWR0_SH 0 +#define B_AX_MACID_25_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE26 0xD3C4 +#define R_AX_PWR_MACID_TABLE26_C1 0xF3C4 +#define B_AX_MACID_26_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_26_TXPWR1_EN BIT(25) +#define B_AX_MACID_26_TXPWR0_EN BIT(24) +#define B_AX_MACID_26_CCA_PWR_TH_SH 16 +#define B_AX_MACID_26_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_26_TXPWR1_SH 8 +#define B_AX_MACID_26_TXPWR1_MSK 0xff +#define B_AX_MACID_26_TXPWR0_SH 0 +#define B_AX_MACID_26_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE27 0xD3C8 +#define R_AX_PWR_MACID_TABLE27_C1 0xF3C8 +#define B_AX_MACID_27_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_27_TXPWR1_EN BIT(25) +#define B_AX_MACID_27_TXPWR0_EN BIT(24) +#define B_AX_MACID_27_CCA_PWR_TH_SH 16 +#define B_AX_MACID_27_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_27_TXPWR1_SH 8 +#define B_AX_MACID_27_TXPWR1_MSK 0xff +#define B_AX_MACID_27_TXPWR0_SH 0 +#define B_AX_MACID_27_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE28 0xD3CC +#define R_AX_PWR_MACID_TABLE28_C1 0xF3CC +#define B_AX_MACID_28_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_28_TXPWR1_EN BIT(25) +#define B_AX_MACID_28_TXPWR0_EN BIT(24) +#define B_AX_MACID_28_CCA_PWR_TH_SH 16 +#define B_AX_MACID_28_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_28_TXPWR1_SH 8 +#define B_AX_MACID_28_TXPWR1_MSK 0xff +#define B_AX_MACID_28_TXPWR0_SH 0 +#define B_AX_MACID_28_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE29 0xD3D0 +#define R_AX_PWR_MACID_TABLE29_C1 0xF3D0 +#define B_AX_MACID_29_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_29_TXPWR1_EN BIT(25) +#define B_AX_MACID_29_TXPWR0_EN BIT(24) +#define B_AX_MACID_29_CCA_PWR_TH_SH 16 +#define B_AX_MACID_29_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_29_TXPWR1_SH 8 +#define B_AX_MACID_29_TXPWR1_MSK 0xff +#define B_AX_MACID_29_TXPWR0_SH 0 +#define B_AX_MACID_29_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE30 0xD3D4 +#define R_AX_PWR_MACID_TABLE30_C1 0xF3D4 +#define B_AX_MACID_30_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_30_TXPWR1_EN BIT(25) +#define B_AX_MACID_30_TXPWR0_EN BIT(24) +#define B_AX_MACID_30_CCA_PWR_TH_SH 16 +#define B_AX_MACID_30_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_30_TXPWR1_SH 8 +#define B_AX_MACID_30_TXPWR1_MSK 0xff +#define B_AX_MACID_30_TXPWR0_SH 0 +#define B_AX_MACID_30_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE31 0xD3D8 +#define R_AX_PWR_MACID_TABLE31_C1 0xF3D8 +#define B_AX_MACID_31_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_31_TXPWR1_EN BIT(25) +#define B_AX_MACID_31_TXPWR0_EN BIT(24) +#define B_AX_MACID_31_CCA_PWR_TH_SH 16 +#define B_AX_MACID_31_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_31_TXPWR1_SH 8 +#define B_AX_MACID_31_TXPWR1_MSK 0xff +#define B_AX_MACID_31_TXPWR0_SH 0 +#define B_AX_MACID_31_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE32 0xD3DC +#define R_AX_PWR_MACID_TABLE32_C1 0xF3DC +#define B_AX_MACID_32_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_32_TXPWR1_EN BIT(25) +#define B_AX_MACID_32_TXPWR0_EN BIT(24) +#define B_AX_MACID_32_CCA_PWR_TH_SH 16 +#define B_AX_MACID_32_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_32_TXPWR1_SH 8 +#define B_AX_MACID_32_TXPWR1_MSK 0xff +#define B_AX_MACID_32_TXPWR0_SH 0 +#define B_AX_MACID_32_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE33 0xD3E0 +#define R_AX_PWR_MACID_TABLE33_C1 0xF3E0 +#define B_AX_MACID_33_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_33_TXPWR1_EN BIT(25) +#define B_AX_MACID_33_TXPWR0_EN BIT(24) +#define B_AX_MACID_33_CCA_PWR_TH_SH 16 +#define B_AX_MACID_33_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_33_TXPWR1_SH 8 +#define B_AX_MACID_33_TXPWR1_MSK 0xff +#define B_AX_MACID_33_TXPWR0_SH 0 +#define B_AX_MACID_33_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE34 0xD3E4 +#define R_AX_PWR_MACID_TABLE34_C1 0xF3E4 +#define B_AX_MACID_34_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_34_TXPWR1_EN BIT(25) +#define B_AX_MACID_34_TXPWR0_EN BIT(24) +#define B_AX_MACID_34_CCA_PWR_TH_SH 16 +#define B_AX_MACID_34_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_34_TXPWR1_SH 8 +#define B_AX_MACID_34_TXPWR1_MSK 0xff +#define B_AX_MACID_34_TXPWR0_SH 0 +#define B_AX_MACID_34_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE35 0xD3E8 +#define R_AX_PWR_MACID_TABLE35_C1 0xF3E8 +#define B_AX_MACID_35_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_35_TXPWR1_EN BIT(25) +#define B_AX_MACID_35_TXPWR0_EN BIT(24) +#define B_AX_MACID_35_CCA_PWR_TH_SH 16 +#define B_AX_MACID_35_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_35_TXPWR1_SH 8 +#define B_AX_MACID_35_TXPWR1_MSK 0xff +#define B_AX_MACID_35_TXPWR0_SH 0 +#define B_AX_MACID_35_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE36 0xD3EC +#define R_AX_PWR_MACID_TABLE36_C1 0xF3EC +#define B_AX_MACID_36_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_36_TXPWR1_EN BIT(25) +#define B_AX_MACID_36_TXPWR0_EN BIT(24) +#define B_AX_MACID_36_CCA_PWR_TH_SH 16 +#define B_AX_MACID_36_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_36_TXPWR1_SH 8 +#define B_AX_MACID_36_TXPWR1_MSK 0xff +#define B_AX_MACID_36_TXPWR0_SH 0 +#define B_AX_MACID_36_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE37 0xD3F0 +#define R_AX_PWR_MACID_TABLE37_C1 0xF3F0 +#define B_AX_MACID_37_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_37_TXPWR1_EN BIT(25) +#define B_AX_MACID_37_TXPWR0_EN BIT(24) +#define B_AX_MACID_37_CCA_PWR_TH_SH 16 +#define B_AX_MACID_37_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_37_TXPWR1_SH 8 +#define B_AX_MACID_37_TXPWR1_MSK 0xff +#define B_AX_MACID_37_TXPWR0_SH 0 +#define B_AX_MACID_37_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE38 0xD3F4 +#define R_AX_PWR_MACID_TABLE38_C1 0xF3F4 +#define B_AX_MACID_38_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_38_TXPWR1_EN BIT(25) +#define B_AX_MACID_38_TXPWR0_EN BIT(24) +#define B_AX_MACID_38_CCA_PWR_TH_SH 16 +#define B_AX_MACID_38_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_38_TXPWR1_SH 8 +#define B_AX_MACID_38_TXPWR1_MSK 0xff +#define B_AX_MACID_38_TXPWR0_SH 0 +#define B_AX_MACID_38_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE39 0xD3F8 +#define R_AX_PWR_MACID_TABLE39_C1 0xF3F8 +#define B_AX_MACID_39_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_39_TXPWR1_EN BIT(25) +#define B_AX_MACID_39_TXPWR0_EN BIT(24) +#define B_AX_MACID_39_CCA_PWR_TH_SH 16 +#define B_AX_MACID_39_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_39_TXPWR1_SH 8 +#define B_AX_MACID_39_TXPWR1_MSK 0xff +#define B_AX_MACID_39_TXPWR0_SH 0 +#define B_AX_MACID_39_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE40 0xD3FC +#define R_AX_PWR_MACID_TABLE40_C1 0xF3FC +#define B_AX_MACID_40_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_40_TXPWR1_EN BIT(25) +#define B_AX_MACID_40_TXPWR0_EN BIT(24) +#define B_AX_MACID_40_CCA_PWR_TH_SH 16 +#define B_AX_MACID_40_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_40_TXPWR1_SH 8 +#define B_AX_MACID_40_TXPWR1_MSK 0xff +#define B_AX_MACID_40_TXPWR0_SH 0 +#define B_AX_MACID_40_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE41 0xD400 +#define R_AX_PWR_MACID_TABLE41_C1 0xF400 +#define B_AX_MACID_41_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_41_TXPWR1_EN BIT(25) +#define B_AX_MACID_41_TXPWR0_EN BIT(24) +#define B_AX_MACID_41_CCA_PWR_TH_SH 16 +#define B_AX_MACID_41_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_41_TXPWR1_SH 8 +#define B_AX_MACID_41_TXPWR1_MSK 0xff +#define B_AX_MACID_41_TXPWR0_SH 0 +#define B_AX_MACID_41_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE42 0xD404 +#define R_AX_PWR_MACID_TABLE42_C1 0xF404 +#define B_AX_MACID_42_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_42_TXPWR1_EN BIT(25) +#define B_AX_MACID_42_TXPWR0_EN BIT(24) +#define B_AX_MACID_42_CCA_PWR_TH_SH 16 +#define B_AX_MACID_42_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_42_TXPWR1_SH 8 +#define B_AX_MACID_42_TXPWR1_MSK 0xff +#define B_AX_MACID_42_TXPWR0_SH 0 +#define B_AX_MACID_42_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE43 0xD408 +#define R_AX_PWR_MACID_TABLE43_C1 0xF408 +#define B_AX_MACID_43_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_43_TXPWR1_EN BIT(25) +#define B_AX_MACID_43_TXPWR0_EN BIT(24) +#define B_AX_MACID_43_CCA_PWR_TH_SH 16 +#define B_AX_MACID_43_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_43_TXPWR1_SH 8 +#define B_AX_MACID_43_TXPWR1_MSK 0xff +#define B_AX_MACID_43_TXPWR0_SH 0 +#define B_AX_MACID_43_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE44 0xD40C +#define R_AX_PWR_MACID_TABLE44_C1 0xF40C +#define B_AX_MACID_44_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_44_TXPWR1_EN BIT(25) +#define B_AX_MACID_44_TXPWR0_EN BIT(24) +#define B_AX_MACID_44_CCA_PWR_TH_SH 16 +#define B_AX_MACID_44_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_44_TXPWR1_SH 8 +#define B_AX_MACID_44_TXPWR1_MSK 0xff +#define B_AX_MACID_44_TXPWR0_SH 0 +#define B_AX_MACID_44_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE45 0xD410 +#define R_AX_PWR_MACID_TABLE45_C1 0xF410 +#define B_AX_MACID_45_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_45_TXPWR1_EN BIT(25) +#define B_AX_MACID_45_TXPWR0_EN BIT(24) +#define B_AX_MACID_45_CCA_PWR_TH_SH 16 +#define B_AX_MACID_45_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_45_TXPWR1_SH 8 +#define B_AX_MACID_45_TXPWR1_MSK 0xff +#define B_AX_MACID_45_TXPWR0_SH 0 +#define B_AX_MACID_45_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE46 0xD414 +#define R_AX_PWR_MACID_TABLE46_C1 0xF414 +#define B_AX_MACID_46_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_46_TXPWR1_EN BIT(25) +#define B_AX_MACID_46_TXPWR0_EN BIT(24) +#define B_AX_MACID_46_CCA_PWR_TH_SH 16 +#define B_AX_MACID_46_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_46_TXPWR1_SH 8 +#define B_AX_MACID_46_TXPWR1_MSK 0xff +#define B_AX_MACID_46_TXPWR0_SH 0 +#define B_AX_MACID_46_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE47 0xD418 +#define R_AX_PWR_MACID_TABLE47_C1 0xF418 +#define B_AX_MACID_47_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_47_TXPWR1_EN BIT(25) +#define B_AX_MACID_47_TXPWR0_EN BIT(24) +#define B_AX_MACID_47_CCA_PWR_TH_SH 16 +#define B_AX_MACID_47_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_47_TXPWR1_SH 8 +#define B_AX_MACID_47_TXPWR1_MSK 0xff +#define B_AX_MACID_47_TXPWR0_SH 0 +#define B_AX_MACID_47_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE48 0xD41C +#define R_AX_PWR_MACID_TABLE48_C1 0xF41C +#define B_AX_MACID_48_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_48_TXPWR1_EN BIT(25) +#define B_AX_MACID_48_TXPWR0_EN BIT(24) +#define B_AX_MACID_48_CCA_PWR_TH_SH 16 +#define B_AX_MACID_48_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_48_TXPWR1_SH 8 +#define B_AX_MACID_48_TXPWR1_MSK 0xff +#define B_AX_MACID_48_TXPWR0_SH 0 +#define B_AX_MACID_48_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE49 0xD420 +#define R_AX_PWR_MACID_TABLE49_C1 0xF420 +#define B_AX_MACID_49_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_49_TXPWR1_EN BIT(25) +#define B_AX_MACID_49_TXPWR0_EN BIT(24) +#define B_AX_MACID_49_CCA_PWR_TH_SH 16 +#define B_AX_MACID_49_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_49_TXPWR1_SH 8 +#define B_AX_MACID_49_TXPWR1_MSK 0xff +#define B_AX_MACID_49_TXPWR0_SH 0 +#define B_AX_MACID_49_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE50 0xD424 +#define R_AX_PWR_MACID_TABLE50_C1 0xF424 +#define B_AX_MACID_50_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_50_TXPWR1_EN BIT(25) +#define B_AX_MACID_50_TXPWR0_EN BIT(24) +#define B_AX_MACID_50_CCA_PWR_TH_SH 16 +#define B_AX_MACID_50_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_50_TXPWR1_SH 8 +#define B_AX_MACID_50_TXPWR1_MSK 0xff +#define B_AX_MACID_50_TXPWR0_SH 0 +#define B_AX_MACID_50_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE51 0xD428 +#define R_AX_PWR_MACID_TABLE51_C1 0xF428 +#define B_AX_MACID_51_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_51_TXPWR1_EN BIT(25) +#define B_AX_MACID_51_TXPWR0_EN BIT(24) +#define B_AX_MACID_51_CCA_PWR_TH_SH 16 +#define B_AX_MACID_51_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_51_TXPWR1_SH 8 +#define B_AX_MACID_51_TXPWR1_MSK 0xff +#define B_AX_MACID_51_TXPWR0_SH 0 +#define B_AX_MACID_51_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE52 0xD42C +#define R_AX_PWR_MACID_TABLE52_C1 0xF42C +#define B_AX_MACID_52_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_52_TXPWR1_EN BIT(25) +#define B_AX_MACID_52_TXPWR0_EN BIT(24) +#define B_AX_MACID_52_CCA_PWR_TH_SH 16 +#define B_AX_MACID_52_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_52_TXPWR1_SH 8 +#define B_AX_MACID_52_TXPWR1_MSK 0xff +#define B_AX_MACID_52_TXPWR0_SH 0 +#define B_AX_MACID_52_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE53 0xD430 +#define R_AX_PWR_MACID_TABLE53_C1 0xF430 +#define B_AX_MACID_53_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_53_TXPWR1_EN BIT(25) +#define B_AX_MACID_53_TXPWR0_EN BIT(24) +#define B_AX_MACID_53_CCA_PWR_TH_SH 16 +#define B_AX_MACID_53_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_53_TXPWR1_SH 8 +#define B_AX_MACID_53_TXPWR1_MSK 0xff +#define B_AX_MACID_53_TXPWR0_SH 0 +#define B_AX_MACID_53_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE54 0xD434 +#define R_AX_PWR_MACID_TABLE54_C1 0xF434 +#define B_AX_MACID_54_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_54_TXPWR1_EN BIT(25) +#define B_AX_MACID_54_TXPWR0_EN BIT(24) +#define B_AX_MACID_54_CCA_PWR_TH_SH 16 +#define B_AX_MACID_54_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_54_TXPWR1_SH 8 +#define B_AX_MACID_54_TXPWR1_MSK 0xff +#define B_AX_MACID_54_TXPWR0_SH 0 +#define B_AX_MACID_54_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE55 0xD438 +#define R_AX_PWR_MACID_TABLE55_C1 0xF438 +#define B_AX_MACID_55_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_55_TXPWR1_EN BIT(25) +#define B_AX_MACID_55_TXPWR0_EN BIT(24) +#define B_AX_MACID_55_CCA_PWR_TH_SH 16 +#define B_AX_MACID_55_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_55_TXPWR1_SH 8 +#define B_AX_MACID_55_TXPWR1_MSK 0xff +#define B_AX_MACID_55_TXPWR0_SH 0 +#define B_AX_MACID_55_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE56 0xD43C +#define R_AX_PWR_MACID_TABLE56_C1 0xF43C +#define B_AX_MACID_56_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_56_TXPWR1_EN BIT(25) +#define B_AX_MACID_56_TXPWR0_EN BIT(24) +#define B_AX_MACID_56_CCA_PWR_TH_SH 16 +#define B_AX_MACID_56_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_56_TXPWR1_SH 8 +#define B_AX_MACID_56_TXPWR1_MSK 0xff +#define B_AX_MACID_56_TXPWR0_SH 0 +#define B_AX_MACID_56_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE57 0xD440 +#define R_AX_PWR_MACID_TABLE57_C1 0xF440 +#define B_AX_MACID_57_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_57_TXPWR1_EN BIT(25) +#define B_AX_MACID_57_TXPWR0_EN BIT(24) +#define B_AX_MACID_57_CCA_PWR_TH_SH 16 +#define B_AX_MACID_57_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_57_TXPWR1_SH 8 +#define B_AX_MACID_57_TXPWR1_MSK 0xff +#define B_AX_MACID_57_TXPWR0_SH 0 +#define B_AX_MACID_57_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE58 0xD444 +#define R_AX_PWR_MACID_TABLE58_C1 0xF444 +#define B_AX_MACID_58_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_58_TXPWR1_EN BIT(25) +#define B_AX_MACID_58_TXPWR0_EN BIT(24) +#define B_AX_MACID_58_CCA_PWR_TH_SH 16 +#define B_AX_MACID_58_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_58_TXPWR1_SH 8 +#define B_AX_MACID_58_TXPWR1_MSK 0xff +#define B_AX_MACID_58_TXPWR0_SH 0 +#define B_AX_MACID_58_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE59 0xD448 +#define R_AX_PWR_MACID_TABLE59_C1 0xF448 +#define B_AX_MACID_59_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_59_TXPWR1_EN BIT(25) +#define B_AX_MACID_59_TXPWR0_EN BIT(24) +#define B_AX_MACID_59_CCA_PWR_TH_SH 16 +#define B_AX_MACID_59_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_59_TXPWR1_SH 8 +#define B_AX_MACID_59_TXPWR1_MSK 0xff +#define B_AX_MACID_59_TXPWR0_SH 0 +#define B_AX_MACID_59_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE60 0xD44C +#define R_AX_PWR_MACID_TABLE60_C1 0xF44C +#define B_AX_MACID_60_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_60_TXPWR1_EN BIT(25) +#define B_AX_MACID_60_TXPWR0_EN BIT(24) +#define B_AX_MACID_60_CCA_PWR_TH_SH 16 +#define B_AX_MACID_60_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_60_TXPWR1_SH 8 +#define B_AX_MACID_60_TXPWR1_MSK 0xff +#define B_AX_MACID_60_TXPWR0_SH 0 +#define B_AX_MACID_60_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE61 0xD450 +#define R_AX_PWR_MACID_TABLE61_C1 0xF450 +#define B_AX_MACID_61_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_61_TXPWR1_EN BIT(25) +#define B_AX_MACID_61_TXPWR0_EN BIT(24) +#define B_AX_MACID_61_CCA_PWR_TH_SH 16 +#define B_AX_MACID_61_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_61_TXPWR1_SH 8 +#define B_AX_MACID_61_TXPWR1_MSK 0xff +#define B_AX_MACID_61_TXPWR0_SH 0 +#define B_AX_MACID_61_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE62 0xD454 +#define R_AX_PWR_MACID_TABLE62_C1 0xF454 +#define B_AX_MACID_62_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_62_TXPWR1_EN BIT(25) +#define B_AX_MACID_62_TXPWR0_EN BIT(24) +#define B_AX_MACID_62_CCA_PWR_TH_SH 16 +#define B_AX_MACID_62_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_62_TXPWR1_SH 8 +#define B_AX_MACID_62_TXPWR1_MSK 0xff +#define B_AX_MACID_62_TXPWR0_SH 0 +#define B_AX_MACID_62_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE63 0xD458 +#define R_AX_PWR_MACID_TABLE63_C1 0xF458 +#define B_AX_MACID_63_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_63_TXPWR1_EN BIT(25) +#define B_AX_MACID_63_TXPWR0_EN BIT(24) +#define B_AX_MACID_63_CCA_PWR_TH_SH 16 +#define B_AX_MACID_63_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_63_TXPWR1_SH 8 +#define B_AX_MACID_63_TXPWR1_MSK 0xff +#define B_AX_MACID_63_TXPWR0_SH 0 +#define B_AX_MACID_63_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE64 0xD45C +#define R_AX_PWR_MACID_TABLE64_C1 0xF45C +#define B_AX_MACID_64_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_64_TXPWR1_EN BIT(25) +#define B_AX_MACID_64_TXPWR0_EN BIT(24) +#define B_AX_MACID_64_CCA_PWR_TH_SH 16 +#define B_AX_MACID_64_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_64_TXPWR1_SH 8 +#define B_AX_MACID_64_TXPWR1_MSK 0xff +#define B_AX_MACID_64_TXPWR0_SH 0 +#define B_AX_MACID_64_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE65 0xD460 +#define R_AX_PWR_MACID_TABLE65_C1 0xF460 +#define B_AX_MACID_65_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_65_TXPWR1_EN BIT(25) +#define B_AX_MACID_65_TXPWR0_EN BIT(24) +#define B_AX_MACID_65_CCA_PWR_TH_SH 16 +#define B_AX_MACID_65_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_65_TXPWR1_SH 8 +#define B_AX_MACID_65_TXPWR1_MSK 0xff +#define B_AX_MACID_65_TXPWR0_SH 0 +#define B_AX_MACID_65_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE66 0xD464 +#define R_AX_PWR_MACID_TABLE66_C1 0xF464 +#define B_AX_MACID_66_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_66_TXPWR1_EN BIT(25) +#define B_AX_MACID_66_TXPWR0_EN BIT(24) +#define B_AX_MACID_66_CCA_PWR_TH_SH 16 +#define B_AX_MACID_66_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_66_TXPWR1_SH 8 +#define B_AX_MACID_66_TXPWR1_MSK 0xff +#define B_AX_MACID_66_TXPWR0_SH 0 +#define B_AX_MACID_66_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE67 0xD468 +#define R_AX_PWR_MACID_TABLE67_C1 0xF468 +#define B_AX_MACID_67_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_67_TXPWR1_EN BIT(25) +#define B_AX_MACID_67_TXPWR0_EN BIT(24) +#define B_AX_MACID_67_CCA_PWR_TH_SH 16 +#define B_AX_MACID_67_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_67_TXPWR1_SH 8 +#define B_AX_MACID_67_TXPWR1_MSK 0xff +#define B_AX_MACID_67_TXPWR0_SH 0 +#define B_AX_MACID_67_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE68 0xD46C +#define R_AX_PWR_MACID_TABLE68_C1 0xF46C +#define B_AX_MACID_68_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_68_TXPWR1_EN BIT(25) +#define B_AX_MACID_68_TXPWR0_EN BIT(24) +#define B_AX_MACID_68_CCA_PWR_TH_SH 16 +#define B_AX_MACID_68_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_68_TXPWR1_SH 8 +#define B_AX_MACID_68_TXPWR1_MSK 0xff +#define B_AX_MACID_68_TXPWR0_SH 0 +#define B_AX_MACID_68_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE69 0xD470 +#define R_AX_PWR_MACID_TABLE69_C1 0xF470 +#define B_AX_MACID_69_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_69_TXPWR1_EN BIT(25) +#define B_AX_MACID_69_TXPWR0_EN BIT(24) +#define B_AX_MACID_69_CCA_PWR_TH_SH 16 +#define B_AX_MACID_69_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_69_TXPWR1_SH 8 +#define B_AX_MACID_69_TXPWR1_MSK 0xff +#define B_AX_MACID_69_TXPWR0_SH 0 +#define B_AX_MACID_69_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE70 0xD474 +#define R_AX_PWR_MACID_TABLE70_C1 0xF474 +#define B_AX_MACID_70_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_70_TXPWR1_EN BIT(25) +#define B_AX_MACID_70_TXPWR0_EN BIT(24) +#define B_AX_MACID_70_CCA_PWR_TH_SH 16 +#define B_AX_MACID_70_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_70_TXPWR1_SH 8 +#define B_AX_MACID_70_TXPWR1_MSK 0xff +#define B_AX_MACID_70_TXPWR0_SH 0 +#define B_AX_MACID_70_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE71 0xD478 +#define R_AX_PWR_MACID_TABLE71_C1 0xF478 +#define B_AX_MACID_71_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_71_TXPWR1_EN BIT(25) +#define B_AX_MACID_71_TXPWR0_EN BIT(24) +#define B_AX_MACID_71_CCA_PWR_TH_SH 16 +#define B_AX_MACID_71_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_71_TXPWR1_SH 8 +#define B_AX_MACID_71_TXPWR1_MSK 0xff +#define B_AX_MACID_71_TXPWR0_SH 0 +#define B_AX_MACID_71_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE72 0xD47C +#define R_AX_PWR_MACID_TABLE72_C1 0xF47C +#define B_AX_MACID_72_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_72_TXPWR1_EN BIT(25) +#define B_AX_MACID_72_TXPWR0_EN BIT(24) +#define B_AX_MACID_72_CCA_PWR_TH_SH 16 +#define B_AX_MACID_72_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_72_TXPWR1_SH 8 +#define B_AX_MACID_72_TXPWR1_MSK 0xff +#define B_AX_MACID_72_TXPWR0_SH 0 +#define B_AX_MACID_72_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE73 0xD480 +#define R_AX_PWR_MACID_TABLE73_C1 0xF480 +#define B_AX_MACID_73_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_73_TXPWR1_EN BIT(25) +#define B_AX_MACID_73_TXPWR0_EN BIT(24) +#define B_AX_MACID_73_CCA_PWR_TH_SH 16 +#define B_AX_MACID_73_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_73_TXPWR1_SH 8 +#define B_AX_MACID_73_TXPWR1_MSK 0xff +#define B_AX_MACID_73_TXPWR0_SH 0 +#define B_AX_MACID_73_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE74 0xD484 +#define R_AX_PWR_MACID_TABLE74_C1 0xF484 +#define B_AX_MACID_74_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_74_TXPWR1_EN BIT(25) +#define B_AX_MACID_74_TXPWR0_EN BIT(24) +#define B_AX_MACID_74_CCA_PWR_TH_SH 16 +#define B_AX_MACID_74_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_74_TXPWR1_SH 8 +#define B_AX_MACID_74_TXPWR1_MSK 0xff +#define B_AX_MACID_74_TXPWR0_SH 0 +#define B_AX_MACID_74_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE75 0xD488 +#define R_AX_PWR_MACID_TABLE75_C1 0xF488 +#define B_AX_MACID_75_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_75_TXPWR1_EN BIT(25) +#define B_AX_MACID_75_TXPWR0_EN BIT(24) +#define B_AX_MACID_75_CCA_PWR_TH_SH 16 +#define B_AX_MACID_75_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_75_TXPWR1_SH 8 +#define B_AX_MACID_75_TXPWR1_MSK 0xff +#define B_AX_MACID_75_TXPWR0_SH 0 +#define B_AX_MACID_75_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE76 0xD48C +#define R_AX_PWR_MACID_TABLE76_C1 0xF48C +#define B_AX_MACID_76_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_76_TXPWR1_EN BIT(25) +#define B_AX_MACID_76_TXPWR0_EN BIT(24) +#define B_AX_MACID_76_CCA_PWR_TH_SH 16 +#define B_AX_MACID_76_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_76_TXPWR1_SH 8 +#define B_AX_MACID_76_TXPWR1_MSK 0xff +#define B_AX_MACID_76_TXPWR0_SH 0 +#define B_AX_MACID_76_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE77 0xD490 +#define R_AX_PWR_MACID_TABLE77_C1 0xF490 +#define B_AX_MACID_77_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_77_TXPWR1_EN BIT(25) +#define B_AX_MACID_77_TXPWR0_EN BIT(24) +#define B_AX_MACID_77_CCA_PWR_TH_SH 16 +#define B_AX_MACID_77_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_77_TXPWR1_SH 8 +#define B_AX_MACID_77_TXPWR1_MSK 0xff +#define B_AX_MACID_77_TXPWR0_SH 0 +#define B_AX_MACID_77_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE78 0xD494 +#define R_AX_PWR_MACID_TABLE78_C1 0xF494 +#define B_AX_MACID_78_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_78_TXPWR1_EN BIT(25) +#define B_AX_MACID_78_TXPWR0_EN BIT(24) +#define B_AX_MACID_78_CCA_PWR_TH_SH 16 +#define B_AX_MACID_78_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_78_TXPWR1_SH 8 +#define B_AX_MACID_78_TXPWR1_MSK 0xff +#define B_AX_MACID_78_TXPWR0_SH 0 +#define B_AX_MACID_78_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE79 0xD498 +#define R_AX_PWR_MACID_TABLE79_C1 0xF498 +#define B_AX_MACID_79_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_79_TXPWR1_EN BIT(25) +#define B_AX_MACID_79_TXPWR0_EN BIT(24) +#define B_AX_MACID_79_CCA_PWR_TH_SH 16 +#define B_AX_MACID_79_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_79_TXPWR1_SH 8 +#define B_AX_MACID_79_TXPWR1_MSK 0xff +#define B_AX_MACID_79_TXPWR0_SH 0 +#define B_AX_MACID_79_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE80 0xD49C +#define R_AX_PWR_MACID_TABLE80_C1 0xF49C +#define B_AX_MACID_80_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_80_TXPWR1_EN BIT(25) +#define B_AX_MACID_80_TXPWR0_EN BIT(24) +#define B_AX_MACID_80_CCA_PWR_TH_SH 16 +#define B_AX_MACID_80_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_80_TXPWR1_SH 8 +#define B_AX_MACID_80_TXPWR1_MSK 0xff +#define B_AX_MACID_80_TXPWR0_SH 0 +#define B_AX_MACID_80_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE81 0xD4A0 +#define R_AX_PWR_MACID_TABLE81_C1 0xF4A0 +#define B_AX_MACID_81_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_81_TXPWR1_EN BIT(25) +#define B_AX_MACID_81_TXPWR0_EN BIT(24) +#define B_AX_MACID_81_CCA_PWR_TH_SH 16 +#define B_AX_MACID_81_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_81_TXPWR1_SH 8 +#define B_AX_MACID_81_TXPWR1_MSK 0xff +#define B_AX_MACID_81_TXPWR0_SH 0 +#define B_AX_MACID_81_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE82 0xD4A4 +#define R_AX_PWR_MACID_TABLE82_C1 0xF4A4 +#define B_AX_MACID_82_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_82_TXPWR1_EN BIT(25) +#define B_AX_MACID_82_TXPWR0_EN BIT(24) +#define B_AX_MACID_82_CCA_PWR_TH_SH 16 +#define B_AX_MACID_82_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_82_TXPWR1_SH 8 +#define B_AX_MACID_82_TXPWR1_MSK 0xff +#define B_AX_MACID_82_TXPWR0_SH 0 +#define B_AX_MACID_82_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE83 0xD4A8 +#define R_AX_PWR_MACID_TABLE83_C1 0xF4A8 +#define B_AX_MACID_83_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_83_TXPWR1_EN BIT(25) +#define B_AX_MACID_83_TXPWR0_EN BIT(24) +#define B_AX_MACID_83_CCA_PWR_TH_SH 16 +#define B_AX_MACID_83_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_83_TXPWR1_SH 8 +#define B_AX_MACID_83_TXPWR1_MSK 0xff +#define B_AX_MACID_83_TXPWR0_SH 0 +#define B_AX_MACID_83_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE84 0xD4AC +#define R_AX_PWR_MACID_TABLE84_C1 0xF4AC +#define B_AX_MACID_84_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_84_TXPWR1_EN BIT(25) +#define B_AX_MACID_84_TXPWR0_EN BIT(24) +#define B_AX_MACID_84_CCA_PWR_TH_SH 16 +#define B_AX_MACID_84_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_84_TXPWR1_SH 8 +#define B_AX_MACID_84_TXPWR1_MSK 0xff +#define B_AX_MACID_84_TXPWR0_SH 0 +#define B_AX_MACID_84_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE85 0xD4B0 +#define R_AX_PWR_MACID_TABLE85_C1 0xF4B0 +#define B_AX_MACID_85_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_85_TXPWR1_EN BIT(25) +#define B_AX_MACID_85_TXPWR0_EN BIT(24) +#define B_AX_MACID_85_CCA_PWR_TH_SH 16 +#define B_AX_MACID_85_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_85_TXPWR1_SH 8 +#define B_AX_MACID_85_TXPWR1_MSK 0xff +#define B_AX_MACID_85_TXPWR0_SH 0 +#define B_AX_MACID_85_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE86 0xD4B4 +#define R_AX_PWR_MACID_TABLE86_C1 0xF4B4 +#define B_AX_MACID_86_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_86_TXPWR1_EN BIT(25) +#define B_AX_MACID_86_TXPWR0_EN BIT(24) +#define B_AX_MACID_86_CCA_PWR_TH_SH 16 +#define B_AX_MACID_86_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_86_TXPWR1_SH 8 +#define B_AX_MACID_86_TXPWR1_MSK 0xff +#define B_AX_MACID_86_TXPWR0_SH 0 +#define B_AX_MACID_86_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE87 0xD4B8 +#define R_AX_PWR_MACID_TABLE87_C1 0xF4B8 +#define B_AX_MACID_87_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_87_TXPWR1_EN BIT(25) +#define B_AX_MACID_87_TXPWR0_EN BIT(24) +#define B_AX_MACID_87_CCA_PWR_TH_SH 16 +#define B_AX_MACID_87_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_87_TXPWR1_SH 8 +#define B_AX_MACID_87_TXPWR1_MSK 0xff +#define B_AX_MACID_87_TXPWR0_SH 0 +#define B_AX_MACID_87_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE88 0xD4BC +#define R_AX_PWR_MACID_TABLE88_C1 0xF4BC +#define B_AX_MACID_88_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_88_TXPWR1_EN BIT(25) +#define B_AX_MACID_88_TXPWR0_EN BIT(24) +#define B_AX_MACID_88_CCA_PWR_TH_SH 16 +#define B_AX_MACID_88_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_88_TXPWR1_SH 8 +#define B_AX_MACID_88_TXPWR1_MSK 0xff +#define B_AX_MACID_88_TXPWR0_SH 0 +#define B_AX_MACID_88_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE89 0xD4C0 +#define R_AX_PWR_MACID_TABLE89_C1 0xF4C0 +#define B_AX_MACID_89_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_89_TXPWR1_EN BIT(25) +#define B_AX_MACID_89_TXPWR0_EN BIT(24) +#define B_AX_MACID_89_CCA_PWR_TH_SH 16 +#define B_AX_MACID_89_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_89_TXPWR1_SH 8 +#define B_AX_MACID_89_TXPWR1_MSK 0xff +#define B_AX_MACID_89_TXPWR0_SH 0 +#define B_AX_MACID_89_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE90 0xD4C4 +#define R_AX_PWR_MACID_TABLE90_C1 0xF4C4 +#define B_AX_MACID_90_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_90_TXPWR1_EN BIT(25) +#define B_AX_MACID_90_TXPWR0_EN BIT(24) +#define B_AX_MACID_90_CCA_PWR_TH_SH 16 +#define B_AX_MACID_90_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_90_TXPWR1_SH 8 +#define B_AX_MACID_90_TXPWR1_MSK 0xff +#define B_AX_MACID_90_TXPWR0_SH 0 +#define B_AX_MACID_90_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE91 0xD4C8 +#define R_AX_PWR_MACID_TABLE91_C1 0xF4C8 +#define B_AX_MACID_91_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_91_TXPWR1_EN BIT(25) +#define B_AX_MACID_91_TXPWR0_EN BIT(24) +#define B_AX_MACID_91_CCA_PWR_TH_SH 16 +#define B_AX_MACID_91_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_91_TXPWR1_SH 8 +#define B_AX_MACID_91_TXPWR1_MSK 0xff +#define B_AX_MACID_91_TXPWR0_SH 0 +#define B_AX_MACID_91_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE92 0xD4CC +#define R_AX_PWR_MACID_TABLE92_C1 0xF4CC +#define B_AX_MACID_92_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_92_TXPWR1_EN BIT(25) +#define B_AX_MACID_92_TXPWR0_EN BIT(24) +#define B_AX_MACID_92_CCA_PWR_TH_SH 16 +#define B_AX_MACID_92_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_92_TXPWR1_SH 8 +#define B_AX_MACID_92_TXPWR1_MSK 0xff +#define B_AX_MACID_92_TXPWR0_SH 0 +#define B_AX_MACID_92_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE93 0xD4D0 +#define R_AX_PWR_MACID_TABLE93_C1 0xF4D0 +#define B_AX_MACID_93_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_93_TXPWR1_EN BIT(25) +#define B_AX_MACID_93_TXPWR0_EN BIT(24) +#define B_AX_MACID_93_CCA_PWR_TH_SH 16 +#define B_AX_MACID_93_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_93_TXPWR1_SH 8 +#define B_AX_MACID_93_TXPWR1_MSK 0xff +#define B_AX_MACID_93_TXPWR0_SH 0 +#define B_AX_MACID_93_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE94 0xD4D4 +#define R_AX_PWR_MACID_TABLE94_C1 0xF4D4 +#define B_AX_MACID_94_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_94_TXPWR1_EN BIT(25) +#define B_AX_MACID_94_TXPWR0_EN BIT(24) +#define B_AX_MACID_94_CCA_PWR_TH_SH 16 +#define B_AX_MACID_94_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_94_TXPWR1_SH 8 +#define B_AX_MACID_94_TXPWR1_MSK 0xff +#define B_AX_MACID_94_TXPWR0_SH 0 +#define B_AX_MACID_94_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE95 0xD4D8 +#define R_AX_PWR_MACID_TABLE95_C1 0xF4D8 +#define B_AX_MACID_95_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_95_TXPWR1_EN BIT(25) +#define B_AX_MACID_95_TXPWR0_EN BIT(24) +#define B_AX_MACID_95_CCA_PWR_TH_SH 16 +#define B_AX_MACID_95_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_95_TXPWR1_SH 8 +#define B_AX_MACID_95_TXPWR1_MSK 0xff +#define B_AX_MACID_95_TXPWR0_SH 0 +#define B_AX_MACID_95_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE96 0xD4DC +#define R_AX_PWR_MACID_TABLE96_C1 0xF4DC +#define B_AX_MACID_96_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_96_TXPWR1_EN BIT(25) +#define B_AX_MACID_96_TXPWR0_EN BIT(24) +#define B_AX_MACID_96_CCA_PWR_TH_SH 16 +#define B_AX_MACID_96_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_96_TXPWR1_SH 8 +#define B_AX_MACID_96_TXPWR1_MSK 0xff +#define B_AX_MACID_96_TXPWR0_SH 0 +#define B_AX_MACID_96_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE97 0xD4E0 +#define R_AX_PWR_MACID_TABLE97_C1 0xF4E0 +#define B_AX_MACID_97_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_97_TXPWR1_EN BIT(25) +#define B_AX_MACID_97_TXPWR0_EN BIT(24) +#define B_AX_MACID_97_CCA_PWR_TH_SH 16 +#define B_AX_MACID_97_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_97_TXPWR1_SH 8 +#define B_AX_MACID_97_TXPWR1_MSK 0xff +#define B_AX_MACID_97_TXPWR0_SH 0 +#define B_AX_MACID_97_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE98 0xD4E4 +#define R_AX_PWR_MACID_TABLE98_C1 0xF4E4 +#define B_AX_MACID_98_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_98_TXPWR1_EN BIT(25) +#define B_AX_MACID_98_TXPWR0_EN BIT(24) +#define B_AX_MACID_98_CCA_PWR_TH_SH 16 +#define B_AX_MACID_98_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_98_TXPWR1_SH 8 +#define B_AX_MACID_98_TXPWR1_MSK 0xff +#define B_AX_MACID_98_TXPWR0_SH 0 +#define B_AX_MACID_98_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE99 0xD4E8 +#define R_AX_PWR_MACID_TABLE99_C1 0xF4E8 +#define B_AX_MACID_99_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_99_TXPWR1_EN BIT(25) +#define B_AX_MACID_99_TXPWR0_EN BIT(24) +#define B_AX_MACID_99_CCA_PWR_TH_SH 16 +#define B_AX_MACID_99_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_99_TXPWR1_SH 8 +#define B_AX_MACID_99_TXPWR1_MSK 0xff +#define B_AX_MACID_99_TXPWR0_SH 0 +#define B_AX_MACID_99_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE100 0xD4EC +#define R_AX_PWR_MACID_TABLE100_C1 0xF4EC +#define B_AX_MACID_100_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_100_TXPWR1_EN BIT(25) +#define B_AX_MACID_100_TXPWR0_EN BIT(24) +#define B_AX_MACID_100_CCA_PWR_TH_SH 16 +#define B_AX_MACID_100_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_100_TXPWR1_SH 8 +#define B_AX_MACID_100_TXPWR1_MSK 0xff +#define B_AX_MACID_100_TXPWR0_SH 0 +#define B_AX_MACID_100_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE101 0xD4F0 +#define R_AX_PWR_MACID_TABLE101_C1 0xF4F0 +#define B_AX_MACID_101_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_101_TXPWR1_EN BIT(25) +#define B_AX_MACID_101_TXPWR0_EN BIT(24) +#define B_AX_MACID_101_CCA_PWR_TH_SH 16 +#define B_AX_MACID_101_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_101_TXPWR1_SH 8 +#define B_AX_MACID_101_TXPWR1_MSK 0xff +#define B_AX_MACID_101_TXPWR0_SH 0 +#define B_AX_MACID_101_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE102 0xD4F4 +#define R_AX_PWR_MACID_TABLE102_C1 0xF4F4 +#define B_AX_MACID_102_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_102_TXPWR1_EN BIT(25) +#define B_AX_MACID_102_TXPWR0_EN BIT(24) +#define B_AX_MACID_102_CCA_PWR_TH_SH 16 +#define B_AX_MACID_102_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_102_TXPWR1_SH 8 +#define B_AX_MACID_102_TXPWR1_MSK 0xff +#define B_AX_MACID_102_TXPWR0_SH 0 +#define B_AX_MACID_102_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE103 0xD4F8 +#define R_AX_PWR_MACID_TABLE103_C1 0xF4F8 +#define B_AX_MACID_103_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_103_TXPWR1_EN BIT(25) +#define B_AX_MACID_103_TXPWR0_EN BIT(24) +#define B_AX_MACID_103_CCA_PWR_TH_SH 16 +#define B_AX_MACID_103_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_103_TXPWR1_SH 8 +#define B_AX_MACID_103_TXPWR1_MSK 0xff +#define B_AX_MACID_103_TXPWR0_SH 0 +#define B_AX_MACID_103_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE104 0xD4FC +#define R_AX_PWR_MACID_TABLE104_C1 0xF4FC +#define B_AX_MACID_104_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_104_TXPWR1_EN BIT(25) +#define B_AX_MACID_104_TXPWR0_EN BIT(24) +#define B_AX_MACID_104_CCA_PWR_TH_SH 16 +#define B_AX_MACID_104_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_104_TXPWR1_SH 8 +#define B_AX_MACID_104_TXPWR1_MSK 0xff +#define B_AX_MACID_104_TXPWR0_SH 0 +#define B_AX_MACID_104_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE105 0xD500 +#define R_AX_PWR_MACID_TABLE105_C1 0xF500 +#define B_AX_MACID_105_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_105_TXPWR1_EN BIT(25) +#define B_AX_MACID_105_TXPWR0_EN BIT(24) +#define B_AX_MACID_105_CCA_PWR_TH_SH 16 +#define B_AX_MACID_105_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_105_TXPWR1_SH 8 +#define B_AX_MACID_105_TXPWR1_MSK 0xff +#define B_AX_MACID_105_TXPWR0_SH 0 +#define B_AX_MACID_105_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE106 0xD504 +#define R_AX_PWR_MACID_TABLE106_C1 0xF504 +#define B_AX_MACID_106_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_106_TXPWR1_EN BIT(25) +#define B_AX_MACID_106_TXPWR0_EN BIT(24) +#define B_AX_MACID_106_CCA_PWR_TH_SH 16 +#define B_AX_MACID_106_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_106_TXPWR1_SH 8 +#define B_AX_MACID_106_TXPWR1_MSK 0xff +#define B_AX_MACID_106_TXPWR0_SH 0 +#define B_AX_MACID_106_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE107 0xD508 +#define R_AX_PWR_MACID_TABLE107_C1 0xF508 +#define B_AX_MACID_107_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_107_TXPWR1_EN BIT(25) +#define B_AX_MACID_107_TXPWR0_EN BIT(24) +#define B_AX_MACID_107_CCA_PWR_TH_SH 16 +#define B_AX_MACID_107_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_107_TXPWR1_SH 8 +#define B_AX_MACID_107_TXPWR1_MSK 0xff +#define B_AX_MACID_107_TXPWR0_SH 0 +#define B_AX_MACID_107_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE108 0xD50C +#define R_AX_PWR_MACID_TABLE108_C1 0xF50C +#define B_AX_MACID_108_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_108_TXPWR1_EN BIT(25) +#define B_AX_MACID_108_TXPWR0_EN BIT(24) +#define B_AX_MACID_108_CCA_PWR_TH_SH 16 +#define B_AX_MACID_108_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_108_TXPWR1_SH 8 +#define B_AX_MACID_108_TXPWR1_MSK 0xff +#define B_AX_MACID_108_TXPWR0_SH 0 +#define B_AX_MACID_108_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE109 0xD510 +#define R_AX_PWR_MACID_TABLE109_C1 0xF510 +#define B_AX_MACID_109_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_109_TXPWR1_EN BIT(25) +#define B_AX_MACID_109_TXPWR0_EN BIT(24) +#define B_AX_MACID_109_CCA_PWR_TH_SH 16 +#define B_AX_MACID_109_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_109_TXPWR1_SH 8 +#define B_AX_MACID_109_TXPWR1_MSK 0xff +#define B_AX_MACID_109_TXPWR0_SH 0 +#define B_AX_MACID_109_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE110 0xD514 +#define R_AX_PWR_MACID_TABLE110_C1 0xF514 +#define B_AX_MACID_110_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_110_TXPWR1_EN BIT(25) +#define B_AX_MACID_110_TXPWR0_EN BIT(24) +#define B_AX_MACID_110_CCA_PWR_TH_SH 16 +#define B_AX_MACID_110_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_110_TXPWR1_SH 8 +#define B_AX_MACID_110_TXPWR1_MSK 0xff +#define B_AX_MACID_110_TXPWR0_SH 0 +#define B_AX_MACID_110_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE111 0xD518 +#define R_AX_PWR_MACID_TABLE111_C1 0xF518 +#define B_AX_MACID_111_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_111_TXPWR1_EN BIT(25) +#define B_AX_MACID_111_TXPWR0_EN BIT(24) +#define B_AX_MACID_111_CCA_PWR_TH_SH 16 +#define B_AX_MACID_111_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_111_TXPWR1_SH 8 +#define B_AX_MACID_111_TXPWR1_MSK 0xff +#define B_AX_MACID_111_TXPWR0_SH 0 +#define B_AX_MACID_111_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE112 0xD51C +#define R_AX_PWR_MACID_TABLE112_C1 0xF51C +#define B_AX_MACID_112_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_112_TXPWR1_EN BIT(25) +#define B_AX_MACID_112_TXPWR0_EN BIT(24) +#define B_AX_MACID_112_CCA_PWR_TH_SH 16 +#define B_AX_MACID_112_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_112_TXPWR1_SH 8 +#define B_AX_MACID_112_TXPWR1_MSK 0xff +#define B_AX_MACID_112_TXPWR0_SH 0 +#define B_AX_MACID_112_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE113 0xD520 +#define R_AX_PWR_MACID_TABLE113_C1 0xF520 +#define B_AX_MACID_113_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_113_TXPWR1_EN BIT(25) +#define B_AX_MACID_113_TXPWR0_EN BIT(24) +#define B_AX_MACID_113_CCA_PWR_TH_SH 16 +#define B_AX_MACID_113_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_113_TXPWR1_SH 8 +#define B_AX_MACID_113_TXPWR1_MSK 0xff +#define B_AX_MACID_113_TXPWR0_SH 0 +#define B_AX_MACID_113_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE114 0xD524 +#define R_AX_PWR_MACID_TABLE114_C1 0xF524 +#define B_AX_MACID_114_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_114_TXPWR1_EN BIT(25) +#define B_AX_MACID_114_TXPWR0_EN BIT(24) +#define B_AX_MACID_114_CCA_PWR_TH_SH 16 +#define B_AX_MACID_114_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_114_TXPWR1_SH 8 +#define B_AX_MACID_114_TXPWR1_MSK 0xff +#define B_AX_MACID_114_TXPWR0_SH 0 +#define B_AX_MACID_114_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE115 0xD528 +#define R_AX_PWR_MACID_TABLE115_C1 0xF528 +#define B_AX_MACID_115_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_115_TXPWR1_EN BIT(25) +#define B_AX_MACID_115_TXPWR0_EN BIT(24) +#define B_AX_MACID_115_CCA_PWR_TH_SH 16 +#define B_AX_MACID_115_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_115_TXPWR1_SH 8 +#define B_AX_MACID_115_TXPWR1_MSK 0xff +#define B_AX_MACID_115_TXPWR0_SH 0 +#define B_AX_MACID_115_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE116 0xD52C +#define R_AX_PWR_MACID_TABLE116_C1 0xF52C +#define B_AX_MACID_116_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_116_TXPWR1_EN BIT(25) +#define B_AX_MACID_116_TXPWR0_EN BIT(24) +#define B_AX_MACID_116_CCA_PWR_TH_SH 16 +#define B_AX_MACID_116_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_116_TXPWR1_SH 8 +#define B_AX_MACID_116_TXPWR1_MSK 0xff +#define B_AX_MACID_116_TXPWR0_SH 0 +#define B_AX_MACID_116_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE117 0xD530 +#define R_AX_PWR_MACID_TABLE117_C1 0xF530 +#define B_AX_MACID_117_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_117_TXPWR1_EN BIT(25) +#define B_AX_MACID_117_TXPWR0_EN BIT(24) +#define B_AX_MACID_117_CCA_PWR_TH_SH 16 +#define B_AX_MACID_117_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_117_TXPWR1_SH 8 +#define B_AX_MACID_117_TXPWR1_MSK 0xff +#define B_AX_MACID_117_TXPWR0_SH 0 +#define B_AX_MACID_117_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE118 0xD534 +#define R_AX_PWR_MACID_TABLE118_C1 0xF534 +#define B_AX_MACID_118_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_118_TXPWR1_EN BIT(25) +#define B_AX_MACID_118_TXPWR0_EN BIT(24) +#define B_AX_MACID_118_CCA_PWR_TH_SH 16 +#define B_AX_MACID_118_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_118_TXPWR1_SH 8 +#define B_AX_MACID_118_TXPWR1_MSK 0xff +#define B_AX_MACID_118_TXPWR0_SH 0 +#define B_AX_MACID_118_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE119 0xD538 +#define R_AX_PWR_MACID_TABLE119_C1 0xF538 +#define B_AX_MACID_119_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_119_TXPWR1_EN BIT(25) +#define B_AX_MACID_119_TXPWR0_EN BIT(24) +#define B_AX_MACID_119_CCA_PWR_TH_SH 16 +#define B_AX_MACID_119_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_119_TXPWR1_SH 8 +#define B_AX_MACID_119_TXPWR1_MSK 0xff +#define B_AX_MACID_119_TXPWR0_SH 0 +#define B_AX_MACID_119_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE120 0xD53C +#define R_AX_PWR_MACID_TABLE120_C1 0xF53C +#define B_AX_MACID_120_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_120_TXPWR1_EN BIT(25) +#define B_AX_MACID_120_TXPWR0_EN BIT(24) +#define B_AX_MACID_120_CCA_PWR_TH_SH 16 +#define B_AX_MACID_120_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_120_TXPWR1_SH 8 +#define B_AX_MACID_120_TXPWR1_MSK 0xff +#define B_AX_MACID_120_TXPWR0_SH 0 +#define B_AX_MACID_120_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE121 0xD540 +#define R_AX_PWR_MACID_TABLE121_C1 0xF540 +#define B_AX_MACID_121_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_121_TXPWR1_EN BIT(25) +#define B_AX_MACID_121_TXPWR0_EN BIT(24) +#define B_AX_MACID_121_CCA_PWR_TH_SH 16 +#define B_AX_MACID_121_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_121_TXPWR1_SH 8 +#define B_AX_MACID_121_TXPWR1_MSK 0xff +#define B_AX_MACID_121_TXPWR0_SH 0 +#define B_AX_MACID_121_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE122 0xD544 +#define R_AX_PWR_MACID_TABLE122_C1 0xF544 +#define B_AX_MACID_122_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_122_TXPWR1_EN BIT(25) +#define B_AX_MACID_122_TXPWR0_EN BIT(24) +#define B_AX_MACID_122_CCA_PWR_TH_SH 16 +#define B_AX_MACID_122_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_122_TXPWR1_SH 8 +#define B_AX_MACID_122_TXPWR1_MSK 0xff +#define B_AX_MACID_122_TXPWR0_SH 0 +#define B_AX_MACID_122_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE123 0xD548 +#define R_AX_PWR_MACID_TABLE123_C1 0xF548 +#define B_AX_MACID_123_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_123_TXPWR1_EN BIT(25) +#define B_AX_MACID_123_TXPWR0_EN BIT(24) +#define B_AX_MACID_123_CCA_PWR_TH_SH 16 +#define B_AX_MACID_123_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_123_TXPWR1_SH 8 +#define B_AX_MACID_123_TXPWR1_MSK 0xff +#define B_AX_MACID_123_TXPWR0_SH 0 +#define B_AX_MACID_123_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE124 0xD54C +#define R_AX_PWR_MACID_TABLE124_C1 0xF54C +#define B_AX_MACID_124_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_124_TXPWR1_EN BIT(25) +#define B_AX_MACID_124_TXPWR0_EN BIT(24) +#define B_AX_MACID_124_CCA_PWR_TH_SH 16 +#define B_AX_MACID_124_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_124_TXPWR1_SH 8 +#define B_AX_MACID_124_TXPWR1_MSK 0xff +#define B_AX_MACID_124_TXPWR0_SH 0 +#define B_AX_MACID_124_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE125 0xD550 +#define R_AX_PWR_MACID_TABLE125_C1 0xF550 +#define B_AX_MACID_125_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_125_TXPWR1_EN BIT(25) +#define B_AX_MACID_125_TXPWR0_EN BIT(24) +#define B_AX_MACID_125_CCA_PWR_TH_SH 16 +#define B_AX_MACID_125_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_125_TXPWR1_SH 8 +#define B_AX_MACID_125_TXPWR1_MSK 0xff +#define B_AX_MACID_125_TXPWR0_SH 0 +#define B_AX_MACID_125_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE126 0xD554 +#define R_AX_PWR_MACID_TABLE126_C1 0xF554 +#define B_AX_MACID_126_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_126_TXPWR1_EN BIT(25) +#define B_AX_MACID_126_TXPWR0_EN BIT(24) +#define B_AX_MACID_126_CCA_PWR_TH_SH 16 +#define B_AX_MACID_126_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_126_TXPWR1_SH 8 +#define B_AX_MACID_126_TXPWR1_MSK 0xff +#define B_AX_MACID_126_TXPWR0_SH 0 +#define B_AX_MACID_126_TXPWR0_MSK 0xff + +#define R_AX_PWR_MACID_TABLE127 0xD558 +#define R_AX_PWR_MACID_TABLE127_C1 0xF558 +#define B_AX_MACID_127_CCA_PWR_TH_EN BIT(26) +#define B_AX_MACID_127_TXPWR1_EN BIT(25) +#define B_AX_MACID_127_TXPWR0_EN BIT(24) +#define B_AX_MACID_127_CCA_PWR_TH_SH 16 +#define B_AX_MACID_127_CCA_PWR_TH_MSK 0xff +#define B_AX_MACID_127_TXPWR1_SH 8 +#define B_AX_MACID_127_TXPWR1_MSK 0xff +#define B_AX_MACID_127_TXPWR0_SH 0 +#define B_AX_MACID_127_TXPWR0_MSK 0xff + +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE0 0xD55C +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE0_C1 0xF55C +#define B_AX_MCS0_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS0_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS0_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS0_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS0_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS0_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE1 0xD560 +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE1_C1 0xF560 +#define B_AX_MCS0_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS0_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS0_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS0_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS0_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS0_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE2 0xD564 +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE2_C1 0xF564 +#define B_AX_MCS0_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS0_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS0_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS0_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS0_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS0_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE3 0xD568 +#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE3_C1 0xF568 +#define B_AX_MCS0_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS0_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS0_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS0_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS0_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS0_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS0_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE0 0xD56C +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE0_C1 0xF56C +#define B_AX_MCS1_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS1_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS1_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS1_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS1_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS1_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE1 0xD570 +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE1_C1 0xF570 +#define B_AX_MCS1_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS1_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS1_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS1_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS1_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS1_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE2 0xD574 +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE2_C1 0xF574 +#define B_AX_MCS1_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS1_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS1_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS1_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS1_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS1_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE3 0xD578 +#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE3_C1 0xF578 +#define B_AX_MCS1_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS1_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS1_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS1_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS1_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS1_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS1_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE0 0xD57C +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE0_C1 0xF57C +#define B_AX_MCS2_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS2_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS2_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS2_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS2_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS2_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE1 0xD580 +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE1_C1 0xF580 +#define B_AX_MCS2_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS2_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS2_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS2_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS2_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS2_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE2 0xD584 +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE2_C1 0xF584 +#define B_AX_MCS2_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS2_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS2_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS2_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS2_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS2_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE3 0xD588 +#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE3_C1 0xF588 +#define B_AX_MCS2_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS2_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS2_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS2_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS2_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS2_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS2_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE0 0xD58C +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE0_C1 0xF58C +#define B_AX_MCS3_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS3_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS3_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS3_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS3_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS3_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE1 0xD590 +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE1_C1 0xF590 +#define B_AX_MCS3_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS3_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS3_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS3_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS3_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS3_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE2 0xD594 +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE2_C1 0xF594 +#define B_AX_MCS3_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS3_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS3_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS3_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS3_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS3_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE3 0xD598 +#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE3_C1 0xF598 +#define B_AX_MCS3_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS3_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS3_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS3_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS3_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS3_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS3_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE0 0xD59C +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE0_C1 0xF59C +#define B_AX_MCS4_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS4_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS4_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS4_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS4_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS4_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE1 0xD5A0 +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE1_C1 0xF5A0 +#define B_AX_MCS4_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS4_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS4_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS4_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS4_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS4_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE2 0xD5A4 +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE2_C1 0xF5A4 +#define B_AX_MCS4_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS4_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS4_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS4_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS4_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS4_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE3 0xD5A8 +#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE3_C1 0xF5A8 +#define B_AX_MCS4_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS4_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS4_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS4_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS4_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS4_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS4_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE0 0xD5AC +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE0_C1 0xF5AC +#define B_AX_MCS5_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS5_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS5_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS5_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS5_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS5_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE1 0xD5B0 +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE1_C1 0xF5B0 +#define B_AX_MCS5_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS5_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS5_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS5_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS5_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS5_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE2 0xD5B4 +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE2_C1 0xF5B4 +#define B_AX_MCS5_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS5_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS5_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS5_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS5_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS5_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE3 0xD5B8 +#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE3_C1 0xF5B8 +#define B_AX_MCS5_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS5_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS5_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS5_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS5_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS5_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS5_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE0 0xD5BC +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE0_C1 0xF5BC +#define B_AX_MCS6_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS6_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS6_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS6_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS6_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS6_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE1 0xD5C0 +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE1_C1 0xF5C0 +#define B_AX_MCS6_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS6_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS6_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS6_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS6_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS6_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE2 0xD5C4 +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE2_C1 0xF5C4 +#define B_AX_MCS6_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS6_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS6_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS6_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS6_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS6_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE3 0xD5C8 +#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE3_C1 0xF5C8 +#define B_AX_MCS6_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS6_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS6_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS6_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS6_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS6_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS6_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE0 0xD5CC +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE0_C1 0xF5CC +#define B_AX_MCS7_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS7_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS7_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS7_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS7_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS7_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE1 0xD5D0 +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE1_C1 0xF5D0 +#define B_AX_MCS7_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS7_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS7_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS7_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS7_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS7_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE2 0xD5D4 +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE2_C1 0xF5D4 +#define B_AX_MCS7_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS7_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS7_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS7_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS7_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS7_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE3 0xD5D8 +#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE3_C1 0xF5D8 +#define B_AX_MCS7_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS7_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS7_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS7_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS7_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS7_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS7_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE0 0xD5DC +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE0_C1 0xF5DC +#define B_AX_MCS8_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS8_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS8_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS8_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS8_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS8_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE1 0xD5E0 +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE1_C1 0xF5E0 +#define B_AX_MCS8_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS8_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS8_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS8_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS8_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS8_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE2 0xD5E4 +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE2_C1 0xF5E4 +#define B_AX_MCS8_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS8_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS8_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS8_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS8_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS8_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE3 0xD5E8 +#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE3_C1 0xF5E8 +#define B_AX_MCS8_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS8_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS8_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS8_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS8_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS8_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS8_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE0 0xD5EC +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE0_C1 0xF5EC +#define B_AX_MCS9_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS9_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS9_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS9_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS9_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS9_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE1 0xD5F0 +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE1_C1 0xF5F0 +#define B_AX_MCS9_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS9_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS9_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS9_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS9_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS9_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE2 0xD5F4 +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE2_C1 0xF5F4 +#define B_AX_MCS9_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS9_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS9_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS9_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS9_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS9_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE3 0xD5F8 +#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE3_C1 0xF5F8 +#define B_AX_MCS9_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS9_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS9_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS9_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS9_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS9_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS9_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE0 0xD5FC +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE0_C1 0xF5FC +#define B_AX_MCS10_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS10_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS10_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS10_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS10_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS10_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE1 0xD600 +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE1_C1 0xF600 +#define B_AX_MCS10_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS10_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS10_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS10_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS10_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS10_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE2 0xD604 +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE2_C1 0xF604 +#define B_AX_MCS10_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS10_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS10_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS10_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS10_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS10_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE3 0xD608 +#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE3_C1 0xF608 +#define B_AX_MCS10_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS10_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS10_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS10_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS10_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS10_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS10_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE0 0xD60C +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE0_C1 0xF60C +#define B_AX_MCS11_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_MCS11_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_MCS11_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_MCS11_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_MCS11_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_MCS11_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE1 0xD610 +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE1_C1 0xF610 +#define B_AX_MCS11_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_MCS11_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_MCS11_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_MCS11_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_MCS11_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_MCS11_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE2 0xD614 +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE2_C1 0xF614 +#define B_AX_MCS11_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_MCS11_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_MCS11_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_MCS11_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_MCS11_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_MCS11_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE3 0xD618 +#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE3_C1 0xF618 +#define B_AX_MCS11_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_MCS11_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_MCS11_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_MCS11_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_MCS11_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_MCS11_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_MCS11_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE0 0xD61C +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE0_C1 0xF61C +#define B_AX_CCK1M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_CCK1M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_CCK1M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_CCK1M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_CCK1M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_CCK1M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE1 0xD620 +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE1_C1 0xF620 +#define B_AX_CCK1M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_CCK1M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_CCK1M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_CCK1M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_CCK1M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_CCK1M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE2 0xD624 +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE2_C1 0xF624 +#define B_AX_CCK1M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_CCK1M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_CCK1M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_CCK1M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_CCK1M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_CCK1M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE3 0xD628 +#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE3_C1 0xF628 +#define B_AX_CCK1M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_CCK1M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_CCK1M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_CCK1M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_CCK1M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK1M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_CCK1M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE0 0xD62C +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE0_C1 0xF62C +#define B_AX_CCK2M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_CCK2M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_CCK2M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_CCK2M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_CCK2M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_CCK2M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE1 0xD630 +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE1_C1 0xF630 +#define B_AX_CCK2M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_CCK2M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_CCK2M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_CCK2M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_CCK2M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_CCK2M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE2 0xD634 +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE2_C1 0xF634 +#define B_AX_CCK2M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_CCK2M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_CCK2M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_CCK2M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_CCK2M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_CCK2M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE3 0xD638 +#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE3_C1 0xF638 +#define B_AX_CCK2M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_CCK2M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_CCK2M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_CCK2M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_CCK2M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK2M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_CCK2M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE0 0xD63C +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE0_C1 0xF63C +#define B_AX_CCK5P5M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_CCK5P5M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_CCK5P5M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_CCK5P5M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_CCK5P5M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_CCK5P5M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE1 0xD640 +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE1_C1 0xF640 +#define B_AX_CCK5P5M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_CCK5P5M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_CCK5P5M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_CCK5P5M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_CCK5P5M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_CCK5P5M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE2 0xD644 +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE2_C1 0xF644 +#define B_AX_CCK5P5M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_CCK5P5M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_CCK5P5M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_CCK5P5M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_CCK5P5M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_CCK5P5M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE3 0xD648 +#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE3_C1 0xF648 +#define B_AX_CCK5P5M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_CCK5P5M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_CCK5P5M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_CCK5P5M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_CCK5P5M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK5P5M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_CCK5P5M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE0 0xD64C +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE0_C1 0xF64C +#define B_AX_CCK11M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_CCK11M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_CCK11M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_CCK11M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_CCK11M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_CCK11M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE1 0xD650 +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE1_C1 0xF650 +#define B_AX_CCK11M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_CCK11M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_CCK11M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_CCK11M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_CCK11M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_CCK11M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE2 0xD654 +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE2_C1 0xF654 +#define B_AX_CCK11M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_CCK11M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_CCK11M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_CCK11M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_CCK11M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_CCK11M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE3 0xD658 +#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE3_C1 0xF658 +#define B_AX_CCK11M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_CCK11M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_CCK11M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_CCK11M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_CCK11M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_CCK11M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_CCK11M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE0 0xD65C +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE0_C1 0xF65C +#define B_AX_LEGACY6M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY6M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY6M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY6M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY6M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY6M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE1 0xD660 +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE1_C1 0xF660 +#define B_AX_LEGACY6M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY6M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY6M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY6M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY6M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY6M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE2 0xD664 +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE2_C1 0xF664 +#define B_AX_LEGACY6M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY6M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY6M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY6M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY6M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY6M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE3 0xD668 +#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE3_C1 0xF668 +#define B_AX_LEGACY6M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY6M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY6M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY6M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY6M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY6M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY6M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE0 0xD66C +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE0_C1 0xF66C +#define B_AX_LEGACY9M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY9M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY9M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY9M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY9M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY9M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE1 0xD670 +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE1_C1 0xF670 +#define B_AX_LEGACY9M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY9M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY9M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY9M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY9M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY9M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE2 0xD674 +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE2_C1 0xF674 +#define B_AX_LEGACY9M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY9M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY9M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY9M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY9M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY9M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE3 0xD678 +#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE3_C1 0xF678 +#define B_AX_LEGACY9M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY9M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY9M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY9M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY9M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY9M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY9M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE0 0xD67C +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE0_C1 0xF67C +#define B_AX_LEGACY12M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY12M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY12M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY12M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY12M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY12M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE1 0xD680 +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE1_C1 0xF680 +#define B_AX_LEGACY12M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY12M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY12M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY12M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY12M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY12M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE2 0xD684 +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE2_C1 0xF684 +#define B_AX_LEGACY12M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY12M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY12M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY12M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY12M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY12M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE3 0xD688 +#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE3_C1 0xF688 +#define B_AX_LEGACY12M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY12M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY12M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY12M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY12M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY12M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY12M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE0 0xD68C +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE0_C1 0xF68C +#define B_AX_LEGACY18M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY18M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY18M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY18M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY18M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY18M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE1 0xD690 +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE1_C1 0xF690 +#define B_AX_LEGACY18M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY18M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY18M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY18M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY18M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY18M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE2 0xD694 +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE2_C1 0xF694 +#define B_AX_LEGACY18M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY18M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY18M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY18M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY18M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY18M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE3 0xD698 +#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE3_C1 0xF698 +#define B_AX_LEGACY18M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY18M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY18M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY18M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY18M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY18M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY18M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE0 0xD69C +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE0_C1 0xF69C +#define B_AX_LEGACY24M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY24M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY24M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY24M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY24M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY24M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE1 0xD6A0 +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE1_C1 0xF6A0 +#define B_AX_LEGACY24M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY24M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY24M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY24M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY24M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY24M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE2 0xD6A4 +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE2_C1 0xF6A4 +#define B_AX_LEGACY24M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY24M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY24M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY24M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY24M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY24M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE3 0xD6A8 +#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE3_C1 0xF6A8 +#define B_AX_LEGACY24M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY24M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY24M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY24M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY24M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY24M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY24M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE0 0xD6AC +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE0_C1 0xF6AC +#define B_AX_LEGACY36M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY36M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY36M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY36M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY36M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY36M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE1 0xD6B0 +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE1_C1 0xF6B0 +#define B_AX_LEGACY36M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY36M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY36M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY36M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY36M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY36M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE2 0xD6B4 +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE2_C1 0xF6B4 +#define B_AX_LEGACY36M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY36M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY36M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY36M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY36M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY36M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE3 0xD6B8 +#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE3_C1 0xF6B8 +#define B_AX_LEGACY36M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY36M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY36M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY36M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY36M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY36M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY36M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE0 0xD6BC +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE0_C1 0xF6BC +#define B_AX_LEGACY48M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY48M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY48M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY48M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY48M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY48M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE1 0xD6C0 +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE1_C1 0xF6C0 +#define B_AX_LEGACY48M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY48M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY48M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY48M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY48M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY48M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE2 0xD6C4 +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE2_C1 0xF6C4 +#define B_AX_LEGACY48M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY48M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY48M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY48M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY48M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY48M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE3 0xD6C8 +#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE3_C1 0xF6C8 +#define B_AX_LEGACY48M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY48M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY48M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY48M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY48M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY48M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY48M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE0 0xD6CC +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE0_C1 0xF6CC +#define B_AX_LEGACY54M_TXDIFF_5DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY54M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_4DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY54M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_3DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY54M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_2DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY54M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_1DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY54M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE1 0xD6D0 +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE1_C1 0xF6D0 +#define B_AX_LEGACY54M_TXDIFF_10DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY54M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_9DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY54M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_8DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY54M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_7DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY54M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_6DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY54M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE2 0xD6D4 +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE2_C1 0xF6D4 +#define B_AX_LEGACY54M_TXDIFF_15DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY54M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_14DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY54M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_13DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY54M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_12DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY54M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_11DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY54M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf + +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE3 0xD6D8 +#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE3_C1 0xF6D8 +#define B_AX_LEGACY54M_TXDIFF_20DB_MCS_OFFSET_SH 16 +#define B_AX_LEGACY54M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_19DB_MCS_OFFSET_SH 12 +#define B_AX_LEGACY54M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_18DB_MCS_OFFSET_SH 8 +#define B_AX_LEGACY54M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_17DB_MCS_OFFSET_SH 4 +#define B_AX_LEGACY54M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf +#define B_AX_LEGACY54M_TXDIFF_16DB_MCS_OFFSET_SH 0 +#define B_AX_LEGACY54M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf + +#define R_AX_TXPWR_IMR 0xD9E0 +#define R_AX_TXPWR_IMR_C1 0xF9E0 +#define B_AX_TXPWR_FSM_TIMEOUT_INT_EN BIT(0) + +#define R_AX_TXPWR_ISR 0xD9E4 +#define R_AX_TXPWR_ISR_C1 0xF9E4 +#define B_AX_TXPWR_FSM_TIMEOUT_ISR BIT(0) + +#define R_AX_TXPWR_DBG_CFG 0xD9F8 +#define R_AX_TXPWR_DBG_CFG_C1 0xF9F8 +#define B_AX_TXPWR_DBG_SEL_SH 24 +#define B_AX_TXPWR_DBG_SEL_MSK 0xff +#define B_AX_TXPWR_DBG_EN BIT(17) +#define B_AX_TXPWR_CLK_GATING_DIS BIT(16) +#define B_AX_TXPWR_TB_NTX BIT(8) + +#define R_AX_TXPWR_DBG 0xD9FC +#define R_AX_TXPWR_DBG_C1 0xF9FC +#define B_AX_TXPWR_CTRL_DBG_SH 0 +#define B_AX_TXPWR_CTRL_DBG_MSK 0xffffffffL + +// +// BTCOEX +// + +#define R_AX_BTC_CFG 0xDA00 +#define R_AX_BTC_CFG_C1 0xFA00 +#define B_AX_DIS_BTC_CLK_G BIT(2) +#define B_AX_GNT_WL_RX_CTRL BIT(1) +#define B_AX_WL_SRC BIT(0) + +#define R_AX_WL_PRI_MSK 0xDA10 +#define R_AX_WL_PRI_MSK_C1 0xFA10 +#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) +#define B_AX_PTA_WL_PRI_MASK_HIQ BIT(7) +#define B_AX_PTA_WL_PRI_MASK_CPUMGQ BIT(6) +#define B_AX_PTA_WL_PRI_MASK_PSMGQ BIT(5) +#define B_AX_PTA_WL_PRI_MASK_MGQ BIT(4) +#define B_AX_PTA_WL_PRI_MASK_BK BIT(3) +#define B_AX_PTA_WL_PRI_MASK_BE BIT(2) +#define B_AX_PTA_WL_PRI_MASK_VI BIT(1) +#define B_AX_PTA_WL_PRI_MASK_VO BIT(0) + +#define R_AX_BTC_FUNC_EN 0xDA20 +#define R_AX_BTC_FUNC_EN_C1 0xFA20 +#define B_AX_PTA_EDCCA_EN BIT(1) +#define B_AX_PTA_WL_TX_EN BIT(0) + +#define R_AX_COEX_TABLE_1 0xDA24 +#define R_AX_COEX_TABLE_1_C1 0xFA24 +#define B_AX_COEX_TABLE_1_SH 0 +#define B_AX_COEX_TABLE_1_MSK 0xffffffffL + +#define R_AX_COEX_TABLE_2 0xDA28 +#define R_AX_COEX_TABLE_2_C1 0xFA28 +#define B_AX_COEX_TABLE_2_SH 0 +#define B_AX_COEX_TABLE_2_MSK 0xffffffffL + +#define R_AX_BREAK_TABLE 0xDA2C +#define R_AX_BREAK_TABLE_C1 0xFA2C +#define B_AX_COEX_BREAK_TABLE_2_SH 16 +#define B_AX_COEX_BREAK_TABLE_2_MSK 0xffff +#define B_AX_COEX_BREAK_TABLE_1_SH 0 +#define B_AX_COEX_BREAK_TABLE_1_MSK 0xffff + +#define R_AX_BT_COEX_MSK_TABLE 0xDA30 +#define R_AX_BT_COEX_MSK_TABLE_C1 0xFA30 +#define B_AX_PRI_MASK_RX_RESP_V1 BIT(30) +#define B_AX_PRI_MASK_RXOFDM_V1 BIT(29) +#define B_AX_PRI_MASK_RXCCK_V1 BIT(28) +#define B_AX_PRI_MASK_TXAC_SH 21 +#define B_AX_PRI_MASK_TXAC_MSK 0x7f +#define B_AX_PRI_MASK_NAV_SH 13 +#define B_AX_PRI_MASK_NAV_MSK 0xff +#define B_AX_PRI_MASK_CCK_V1 BIT(12) +#define B_AX_PRI_MASK_OFDM_V1 BIT(11) +#define B_AX_PRI_MASK_RTY_V1 BIT(10) +#define B_AX_PRI_MASK_NUM_SH 6 +#define B_AX_PRI_MASK_NUM_MSK 0xf +#define B_AX_PRI_MASK_TYPE_SH 2 +#define B_AX_PRI_MASK_TYPE_MSK 0xf +#define B_AX_OOB_V1 BIT(1) +#define B_AX_ANT_SEL_V1 BIT(0) + +#define R_AX_BT_COEX_CFG_2 0xDA34 +#define R_AX_BT_COEX_CFG_2_C1 0xFA34 +#define B_AX_GNT_BT_POLARITY BIT(12) +#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(8) +#define B_AX_TIMER_SH 0 +#define B_AX_TIMER_MSK 0xff + +#define R_AX_BT_COEX_CFG_3 0xDA38 +#define R_AX_BT_COEX_CFG_3_C1 0xFA38 +#define B_AX_R_BT_CNT_THREN BIT(8) +#define B_AX_R_BT_CNT_THR_SH 0 +#define B_AX_R_BT_CNT_THR_MSK 0xff + +#define R_AX_BT_COEX_CFG_4 0xDA3C +#define R_AX_BT_COEX_CFG_4_C1 0xFA3C +#define B_AX_ANT_DIVERSITY_SEL_1 BIT(9) +#define B_AX_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) +#define B_AX_WLACT_LOW_GNTWL_EN_1 BIT(2) +#define B_AX_WLACT_HIGH_GNTBT_EN_1 BIT(1) +#define B_AX_NAV_UPPER_1_V1 BIT(0) + +#define R_AX_CSR_MODE 0xDA40 +#define R_AX_CSR_MODE_C1 0xFA40 +#define B_AX_BT_CNT_REST BIT(16) +#define B_AX_BT_STAT_DELAY_SH 12 +#define B_AX_BT_STAT_DELAY_MSK 0xf +#define B_AX_BT_TRX_INIT_DETECT_SH 8 +#define B_AX_BT_TRX_INIT_DETECT_MSK 0xf +#define B_AX_BT_PRI_DETECT_TO_SH 4 +#define B_AX_BT_PRI_DETECT_TO_MSK 0xf +#define B_AX_WL_ACT_MSK BIT(3) +#define B_AX_STATIS_BT_EN BIT(2) +#define B_AX_WL_ACT_MASK_ENABLE BIT(1) +#define B_AX_ENHANCED_BT BIT(0) + +#define R_AX_BT_STAST_HIGH 0xDA44 +#define R_AX_BT_STAST_HIGH_C1 0xFA44 +#define B_AX_STATIS_BT_HI_RX_SH 16 +#define B_AX_STATIS_BT_HI_RX_MSK 0xffff +#define B_AX_STATIS_BT_HI_TX_SH 0 +#define B_AX_STATIS_BT_HI_TX_MSK 0xffff + +#define R_AX_GNT_SW_CTRL 0xDA48 +#define R_AX_BT_STAST_LOW 0xDA48 +#define R_AX_BT_STAST_LOW_C1 0xFA48 +#define B_AX_STATIS_BT_LO_RX_1_SH 16 +#define B_AX_STATIS_BT_LO_RX_1_MSK 0xffff +#define B_AX_STATIS_BT_LO_TX_1_SH 0 +#define B_AX_STATIS_BT_LO_TX_1_MSK 0xffff + +#define R_AX_TDMA_MODE 0xDA4C +#define R_AX_TDMA_MODE_C1 0xFA4C +#define B_AX_R_BT_CMD_RPT_SH 16 +#define B_AX_R_BT_CMD_RPT_MSK 0xffff +#define B_AX_R_RPT_FROM_BT_SH 8 +#define B_AX_R_RPT_FROM_BT_MSK 0xff +#define B_AX_BT_HID_ISR_SET_SH 6 +#define B_AX_BT_HID_ISR_SET_MSK 0x3 +#define B_AX_TDMA_BT_START_NOTIFY BIT(5) +#define B_AX_ENABLE_TDMA_FW_MODE BIT(4) +#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) +#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) +#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) +#define B_AX_RTK_BT_ENABLE BIT(0) + +#define R_AX_RTK_MODE_RPT 0xDA50 +#define R_AX_RTK_MODE_RPT_C1 0xFA50 +#define B_AX_BT_PROFILE_SH 24 +#define B_AX_BT_PROFILE_MSK 0xff +#define B_AX_BT_POWER_SH 16 +#define B_AX_BT_POWER_MSK 0xff +#define B_AX_BT_PREDECT_STATUS_SH 8 +#define B_AX_BT_PREDECT_STATUS_MSK 0xff +#define B_AX_BT_CMD_INFO_SH 0 +#define B_AX_BT_CMD_INFO_MSK 0xff + +#define R_AX_RTK_MODE_CFG 0xDA54 +#define R_AX_RTK_MODE_CFG_C1 0xFA54 +#define B_AX_EN_MAC_NULL_PKT_NOTIFY BIT(31) +#define B_AX_EN_WLAN_RPT_AND_BT_QUERY BIT(30) +#define B_AX_EN_BT_STSTUS_RPT BIT(29) +#define B_AX_EN_BT_POWER BIT(28) +#define B_AX_EN_BT_CHANNEL BIT(27) +#define B_AX_EN_BT_SLOT_CHANGE BIT(26) +#define B_AX_EN_BT_PROFILE_OR_HID BIT(25) +#define B_AX_WLAN_RPT_NOTIFY BIT(24) +#define B_AX_WLAN_RPT_DATA_SH 16 +#define B_AX_WLAN_RPT_DATA_MSK 0xff +#define B_AX_CMD_ID_SH 8 +#define B_AX_CMD_ID_MSK 0xff +#define B_AX_BT_DATA_SH 0 +#define B_AX_BT_DATA_MSK 0xff + +#define R_AX_RTK_MODE_TO 0xDA58 +#define R_AX_RTK_MODE_TO_C1 0xFA58 +#define B_AX_WLAN_RPT_TO_SH 0 +#define B_AX_WLAN_RPT_TO_MSK 0xff + +#define R_AX_BT_COEX_ISO 0xDA5C +#define R_AX_BT_COEX_ISO_C1 0xFA5C +#define B_AX_ISOLATION_CHK_0_SH 1 +#define B_AX_ISOLATION_CHK_0_MSK 0x7fffff +#define B_AX_ISOLATION_EN BIT(0) + +#define R_AX_BT_COEX_ISO_CHK_1 0xDA60 +#define R_AX_BT_COEX_ISO_CHK_1_C1 0xFA60 +#define B_AX_ISOLATION_CHK_1_SH 0 +#define B_AX_ISOLATION_CHK_1_MSK 0xffffffffL + +#define R_AX_BT_COEX_ISO_CHK_2 0xDA64 +#define R_AX_BT_COEX_ISO_CHK_2_C1 0xFA64 +#define B_AX_BT_HID_ISR BIT(31) +#define B_AX_BT_QUERY_ISR BIT(30) +#define B_AX_MAC_NULL_PKT_NOTIFY_ISR BIT(29) +#define B_AX_WLAN_RPT_ISR BIT(28) +#define B_AX_BT_POWER_ISR BIT(27) +#define B_AX_BT_CHANNEL_ISR BIT(26) +#define B_AX_BT_SLOT_CHANGE_ISR BIT(25) +#define B_AX_BT_PROFILE_ISR BIT(24) +#define B_AX_ISOLATION_CHK_2_SH 0 +#define B_AX_ISOLATION_CHK_2_MSK 0xffffff + +#define R_AX_BT_COEX_CFG_5 0xDA6C +#define R_AX_BT_COEX_CFG_5_C1 0xFA6C +#define B_AX_BT_TIME_SH 6 +#define B_AX_BT_TIME_MSK 0x3ffffff +#define B_AX_BT_RPT_SAMPLE_RATE_SH 0 +#define B_AX_BT_RPT_SAMPLE_RATE_MSK 0x3f + +#define R_AX_BT_ACT_CFG 0xDA70 +#define R_AX_BT_ACT_CFG_C1 0xFA70 +#define B_AX_BT_EISR_EN_SH 16 +#define B_AX_BT_EISR_EN_MSK 0xff +#define B_AX_BT_ACT_FALLING_ISR BIT(10) +#define B_AX_BT_ACT_RISING_ISR BIT(9) +#define B_AX_TDMA_TO_ISR BIT(8) +#define B_AX_BT_CH_SH 0 +#define B_AX_BT_CH_MSK 0x7f + +#define R_AX_BT_TIME_CNT 0xDA74 +#define R_AX_BT_TIME_CNT_C1 0xFA74 +#define B_AX_BT_TIME_CNT_SH 0 +#define B_AX_BT_TIME_CNT_MSK 0xff + +#define R_AX_WLACT_MASK_CTRL 0xDA7C +#define R_AX_WLACT_MASK_CTRL_C1 0xFA7C +#define B_AX_RX_RTS_NAV_SH 8 +#define B_AX_RX_RTS_NAV_MSK 0xff +#define B_AX_RESET_RTS_SH 0 +#define B_AX_RESET_RTS_MSK 0xff + +#define R_AX_LTE_CTRL 0xDAF0 +#define R_AX_LTE_CTRL_C1 0xFAF0 +#define B_AX_LTE_SET BIT(31) +#define B_AX_LTE_RW BIT(30) +#define B_AX_LTE_RDY BIT(29) +#define B_AX_LTE_BYTE_EN_SH 16 +#define B_AX_LTE_BYTE_EN_MSK 0xf +#define B_AX_LTE_ADDR_SH 0 +#define B_AX_LTE_ADDR_MSK 0xffff + +#define R_AX_LTE_WDATA 0xDAF4 +#define R_AX_LTE_WDATA_C1 0xFAF4 +#define B_AX_LTE_WDATA_SH 0 +#define B_AX_LTE_WDATA_MSK 0xffffffffL + +#define R_AX_LTE_RDATA 0xDAF8 +#define R_AX_LTE_RDATA_C1 0xFAF8 +#define B_AX_LTE_RDATA_SH 0 +#define B_AX_LTE_RDATA_MSK 0xffffffffL + +// +// LTECOEX +// + +#define R_AX_LTE_SW_CFG_1 0x0038 +#define R_AX_LTE_SW_CFG_1_C1 0x2038 +#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) +#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) +#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) +#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) +#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) +#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) +#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) +#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) +#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) +#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) +#define B_AX_LTE_PATTERN_2_EN BIT(17) +#define B_AX_LTE_PATTERN_1_EN BIT(16) +#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) +#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) +#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) +#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) +#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) +#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) +#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) +#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) +#define B_AX_LTECOEX_FUN_EN BIT(7) +#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) +#define B_AX_LTECOEX_OP_MODE_SEL_SH 4 +#define B_AX_LTECOEX_OP_MODE_SEL_MSK 0x3 +#define B_AX_LTECOEX_UART_MUX BIT(3) +#define B_AX_LTECOEX_UART_MODE_SEL_SH 0 +#define B_AX_LTECOEX_UART_MODE_SEL_MSK 0x7 + +#define R_AX_LTE_SW_CFG_2 0x003C +#define R_AX_LTE_SW_CFG_2_C1 0x203C +#define B_AX_WL_RX_CTRL BIT(8) +#define B_AX_GNT_WL_RX_SW_VAL BIT(7) +#define B_AX_GNT_WL_RX_SW_CTRL BIT(6) +#define B_AX_GNT_WL_TX_SW_VAL BIT(5) +#define B_AX_GNT_WL_TX_SW_CTRL BIT(4) +#define B_AX_GNT_BT_RX_SW_VAL BIT(3) +#define B_AX_GNT_BT_RX_SW_CTRL BIT(2) +#define B_AX_GNT_BT_TX_SW_VAL BIT(1) +#define B_AX_GNT_BT_TX_SW_CTRL BIT(0) + +// +// WL_AX_Reg_HIOE.xls +// + +// +// HIOE_Reg_Spec +// + +#define R_PL_HIOE_CTRL 0x0000 +#define B_PL_HIOE_RESTORE_REQ BIT(31) +#define B_PL_HIOE_RETAIN_REQ BIT(30) +#define B_PL_HIOE_DDMA_CH1_REQ BIT(29) +#define B_PL_HIOE_DDMA_CH2_REQ BIT(28) +#define B_PL_HIOE_DDMA_CH1_CHKSUM_STATUS BIT(27) +#define B_PL_HIOE_DDMA_CH2_CHKSUM_STATUS BIT(26) +#define B_PL_HIOE_INST_FORMAT_ERR BIT(25) +#define B_PL_HIOE_OP_TIMEOUT_ERR BIT(24) +#define B_PL_HIOE_OP_TIMEOUT_SH 16 +#define B_PL_HIOE_OP_TIMEOUT_MSK 0xff +#define B_PL_HIOE_ADDR_CHECKSUM_SH 0 +#define B_PL_HIOE_ADDR_CHECKSUM_MSK 0xffff + +#define R_PL_HIOE_CFG_FILE_START 0x0004 +#define B_PL_HIOE_CFG_FILE_START_SH 0 +#define B_PL_HIOE_CFG_FILE_START_MSK 0xffffffffL + +#define R_PL_HIOE_CFG_FILE_END 0x0008 +#define B_PL_HIOE_CFG_FILE_END_SH 0 +#define B_PL_HIOE_CFG_FILE_END_MSK 0xffffffffL + +#define R_PL_HIOE_CUR_INST_ADDR 0x000C +#define B_PL_HIOE_CUR_INST_ADDR_SH 0 +#define B_PL_HIOE_CUR_INST_ADDR_MSK 0xffffffffL + +// +// WL_AX_Reg_IDDMA.xls +// + +// +// IDDMA_Reg_Spec +// + +#define R_PL_IDDMA_CH0_SA 0x0000 +#define B_PL_IDDMA_CH0_SA_SH 0 +#define B_PL_IDDMA_CH0_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH0_DA 0x0004 +#define B_PL_IDDMA_CH0_DA_SH 0 +#define B_PL_IDDMA_CH0_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH0_CTRL 0x0008 +#define B_PL_IDDMA_CH0_OWN BIT(31) +#define B_PL_IDDMA_CH0_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH0_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH0_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH0_CHKSUM_CONT BIT(24) +#define B_PL_IDDMA_CH0_DLEN_SH 0 +#define B_PL_IDDMA_CH0_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_CH1_SA 0x0010 +#define B_PL_IDDMA_CH1_SA_SH 0 +#define B_PL_IDDMA_CH1_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH1_DA 0x0014 +#define B_PL_IDDMA_CH1_DA_SH 0 +#define B_PL_IDDMA_CH1_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH1_CTRL 0x0018 +#define B_PL_IDDMA_CH1_OWN BIT(31) +#define B_PL_IDDMA_CH1_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH1_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH1_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH1_DLEN_SH 0 +#define B_PL_IDDMA_CH1_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_CH2_SA 0x0020 +#define B_PL_IDDMA_CH2_SA_SH 0 +#define B_PL_IDDMA_CH2_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH2_DA 0x0024 +#define B_PL_IDDMA_CH2_DA_SH 0 +#define B_PL_IDDMA_CH2_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH2_CTRL 0x0028 +#define B_PL_IDDMA_CH2_OWN BIT(31) +#define B_PL_IDDMA_CH2_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH2_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH2_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH2_DLEN_SH 0 +#define B_PL_IDDMA_CH2_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_CH3_SA 0x0030 +#define B_PL_IDDMA_CH3_SA_SH 0 +#define B_PL_IDDMA_CH3_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH3_DA 0x0034 +#define B_PL_IDDMA_CH3_DA_SH 0 +#define B_PL_IDDMA_CH3_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH3_CTRL 0x0038 +#define B_PL_IDDMA_CH3_OWN BIT(31) +#define B_PL_IDDMA_CH3_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH3_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH3_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH3_DLEN_SH 0 +#define B_PL_IDDMA_CH3_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_CH4_SA 0x0040 +#define B_PL_IDDMA_CH4_SA_SH 0 +#define B_PL_IDDMA_CH4_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH4_DA 0x0044 +#define B_PL_IDDMA_CH4_DA_SH 0 +#define B_PL_IDDMA_CH4_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH4_CTRL 0x0048 +#define B_PL_IDDMA_CH4_OWN BIT(31) +#define B_PL_IDDMA_CH4_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH4_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH4_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH4_DLEN_SH 0 +#define B_PL_IDDMA_CH4_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_CH5_SA 0x0050 +#define B_PL_IDDMA_CH5_SA_SH 0 +#define B_PL_IDDMA_CH5_SA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH5_DA 0x0054 +#define B_PL_IDDMA_CH5_DA_SH 0 +#define B_PL_IDDMA_CH5_DA_MSK 0xffffffffL + +#define R_PL_IDDMA_CH5_CTRL 0x0058 +#define B_PL_IDDMA_CH5_OWN BIT(31) +#define B_PL_IDDMA_CH5_CHKSUM_EN BIT(29) +#define B_PL_IDDMA_CH5_DA_W_DISABLE BIT(28) +#define B_PL_IDDMA_CH5_CHKSUM_STATUS BIT(27) +#define B_PL_IDDMA_CH5_DLEN_SH 0 +#define B_PL_IDDMA_CH5_DLEN_MSK 0x3ffff + +#define R_PL_IDDMA_FWIMR 0x00E0 +#define B_PL_IDDMA_CH5_INT_MSK BIT(5) +#define B_PL_IDDMA_CH4_INT_MSK BIT(4) +#define B_PL_IDDMA_CH3_INT_MSK BIT(3) +#define B_PL_IDDMA_CH2_INT_MSK BIT(2) +#define B_PL_IDDMA_CH1_INT_MSK BIT(1) +#define B_PL_IDDMA_CH0_INT_MSK BIT(0) + +#define R_PL_IDDMA_FWISR 0x00E4 +#define B_PL_IDDMA_CH5_INT BIT(5) +#define B_PL_IDDMA_CH4_INT BIT(4) +#define B_PL_IDDMA_CH3_INT BIT(3) +#define B_PL_IDDMA_CH2_INT BIT(2) +#define B_PL_IDDMA_CH1_INT BIT(1) +#define B_PL_IDDMA_CH0_INT BIT(0) + +#define R_PL_IDDMA_CH_STATUS 0x00E8 +#define B_PL_IDDMA_CH5_BUSY BIT(5) +#define B_PL_IDDMA_CH4_BUSY BIT(4) +#define B_PL_IDDMA_CH3_BUSY BIT(3) +#define B_PL_IDDMA_CH2_BUSY BIT(2) +#define B_PL_IDDMA_CH1_BUSY BIT(1) +#define B_PL_IDDMA_CH0_BUSY BIT(0) + +#define R_PL_IDDMA_CHKSUM_CONTROL 0x00EC +#define B_PL_IDDMA_CHKSUM_RESET BIT(0) + +#define R_PL_IDDMA_CHKSUM 0x00F0 +#define B_PL_IDDMA_CHKSUM_RESULT_SH 0 +#define B_PL_IDDMA_CHKSUM_RESULT_MSK 0xffff + +#define R_PL_IDDMA_MONITOR 0x00FC +#define B_PL_IDDMA_CH5_DOK BIT(21) +#define B_PL_IDDMA_CH4_DOK BIT(20) +#define B_PL_IDDMA_CH3_DOK BIT(19) +#define B_PL_IDDMA_CH2_DOK BIT(18) +#define B_PL_IDDMA_CH1_DOK BIT(17) +#define B_PL_IDDMA_CH0_DOK BIT(16) +#define B_PL_IDDMA_DATA_UNDERFLOW BIT(14) +#define B_PL_IDDMA_FIFO_UNDERFLOW BIT(13) +#define B_PL_IDDMA_FIFO_OVERFLOW BIT(12) +#define B_PL_IDDMA_CH5_ERROR BIT(5) +#define B_PL_IDDMA_CH4_ERROR BIT(4) +#define B_PL_IDDMA_CH3_ERROR BIT(3) +#define B_PL_IDDMA_CH2_ERROR BIT(2) +#define B_PL_IDDMA_CH1_ERROR BIT(1) +#define B_PL_IDDMA_CH0_ERROR BIT(0) + +// +// WL_AX_Reg_IPSec.xls +// + +// +// IPSec_Reg +// + +#define R_PL_REG_SDSR 0x0000 +#define B_PL_SRC_RST BIT(31) +#define B_PL_PK_UP BIT(30) +#define B_PL_SRC_FAIL_STATUS_SH 25 +#define B_PL_SRC_FAIL_STATUS_MSK 0x3 +#define B_PL_SRC_FAIL BIT(24) +#define B_PL_SRPTR_SH 16 +#define B_PL_SRPTR_MSK 0xff +#define B_PL_SWPTR_SH 8 +#define B_PL_SWPTR_MSK 0xff +#define B_PL_FIFO_EMPTY_CNT_SH 0 +#define B_PL_FIFO_EMPTY_CNT_MSK 0xff + +#define R_PL_REG_SDFWR 0x0004 +#define B_PL_SDFW_SH 0 +#define B_PL_SDFW_MSK 0xffffffffL + +#define R_PL_REG_SDSWR 0x0008 +#define B_PL_SDSW_SH 0 +#define B_PL_SDSW_MSK 0xffffffffL + +#define R_PL_REG_IPSCSR_RSTEACONFISR 0x0010 +#define B_PL_IPSEC_RST BIT(31) +#define B_PL_CLEAR_OK_INT_NUM_SH 16 +#define B_PL_CLEAR_OK_INT_NUM_MSK 0xff +#define B_PL_OK_INTR_CNT_SH 8 +#define B_PL_OK_INTR_CNT_MSK 0xff +#define B_PL_INTR_MODE BIT(7) +#define B_PL_CMD_OK BIT(4) +#define B_PL_DMA_BUSY BIT(3) +#define B_PL_SOFT_RST BIT(0) + +#define R_PL_REG_IPSCSR_INTM 0x0014 +#define B_PL_DES_ERR5_M BIT(18) +#define B_PL_DES_ERR4_M BIT(17) +#define B_PL_DES_ERR3_M BIT(16) +#define B_PL_DES_ERR2_M BIT(15) +#define B_PL_DES_ERR1_M BIT(14) +#define B_PL_DES_ERR0_M BIT(13) +#define B_PL_SRC_ERR9_M BIT(12) +#define B_PL_SRC_ERR8_M BIT(11) +#define B_PL_SRC_ERR7_M BIT(10) +#define B_PL_SRC_ERR6_M BIT(9) +#define B_PL_SRC_ERR5_M BIT(8) +#define B_PL_SRC_ERR4_M BIT(7) +#define B_PL_SRC_ERR3_M BIT(6) +#define B_PL_SRC_ERR2_M BIT(5) +#define B_PL_SRC_ERR1_M BIT(4) +#define B_PL_SRC_ERR0_M BIT(3) +#define B_PL_DES_FAIL_M BIT(2) +#define B_PL_SRC_FAIL_M BIT(1) +#define B_PL_CMD_OK_M BIT(0) + +#define R_PL_REG_IPSCSR_DBG 0x0018 +#define B_PL_DEBUG_WB BIT(31) +#define B_PL_MST_BAD_SEL_SH 28 +#define B_PL_MST_BAD_SEL_MSK 0x3 +#define B_PL_ENGINE_CLK_EN BIT(24) +#define B_PL_DEBUG_PORT_SEL_SH 20 +#define B_PL_DEBUG_PORT_SEL_MSK 0xf +#define B_PL_ARBITER_MODE BIT(16) +#define B_PL_DMA_WAIT_CYCLE_SH 0 +#define B_PL_DMA_WAIT_CYCLE_MSK 0xffff + +#define R_PL_REG_IPSCSR_ERR_INT 0x001C +#define B_PL_DES_ERR5 BIT(15) +#define B_PL_DES_ERR4 BIT(14) +#define B_PL_DES_ERR3 BIT(13) +#define B_PL_DES_ERR2 BIT(12) +#define B_PL_DES_ERR1 BIT(11) +#define B_PL_DES_ERR0 BIT(10) +#define B_PL_SRC_ERR9 BIT(9) +#define B_PL_SRC_ERR8 BIT(8) +#define B_PL_SRC_ERR7 BIT(7) +#define B_PL_SRC_ERR6 BIT(6) +#define B_PL_SRC_ERR5 BIT(5) +#define B_PL_SRC_ERR4 BIT(4) +#define B_PL_SRC_ERR3 BIT(3) +#define B_PL_SRC_ERR2 BIT(2) +#define B_PL_SRC_ERR1 BIT(1) +#define B_PL_SRC_ERR0 BIT(0) + +#define R_PL_REG_IPSCSR_SAADLR 0x0020 +#define B_PL_A2EO_SUM_SH 0 +#define B_PL_A2EO_SUM_MSK 0x7ff + +#define R_PL_REG_IPSCSR_SENLR 0x0024 +#define B_PL_ENL_SUM_SH 0 +#define B_PL_ENL_SUM_MSK 0xffffff + +#define R_PL_REG_IPSCSR_SAPLR 0x0028 +#define B_PL_APL_SUM_SH 0 +#define B_PL_APL_SUM_MSK 0xfff + +#define R_PL_REG_IPSCSR_SEPLR 0x002C +#define B_PL_EPL_SUM_SH 0 +#define B_PL_EPL_SUM_MSK 0x3f + +#define R_PL_REG_IPSCSR_SWAPABURSTR 0x0030 +#define B_PL_MD5_INPUT_DATA_BYTE_SWAP BIT(25) +#define B_PL_MD5_OUTPUT_DATA_BYTE_SWAP BIT(24) +#define B_PL_DMA_BURST_LENGTH_SH 16 +#define B_PL_DMA_BURST_LENGTH_MSK 0x3f +#define B_PL_AUTO_PADDING_SWAP BIT(13) +#define B_PL_TX_WD_SWAP BIT(12) +#define B_PL_RX_WD_SWAP BIT(11) +#define B_PL_MAC_OUT_LITTLE_ENDIAN BIT(10) +#define B_PL_DATA_OUT_LITTLE_ENDIAN BIT(9) +#define B_PL_TX_BYTE_SWAP BIT(8) +#define B_PL_DATA_IN_LITTLE_ENDIAN BIT(4) +#define B_PL_HASH_INITIAL_VALUE_SWAP BIT(3) +#define B_PL_KEY_PAD_SWAP BIT(2) +#define B_PL_KEY_IV_SWAP BIT(1) +#define B_PL_SET_SWAP BIT(0) + +#define R_PL_REG_DDSR 0x1000 +#define B_PL_DES_RST BIT(31) +#define B_PL_DES_FAIL_STATUS_SH 25 +#define B_PL_DES_FAIL_STATUS_MSK 0x3 +#define B_PL_DES_FAIL BIT(24) +#define B_PL_DRPTR_SH 16 +#define B_PL_DRPTR_MSK 0xff +#define B_PL_DWPTR_SH 8 +#define B_PL_DWPTR_MSK 0xff + +#define R_PL_REG_DDFWR 0x1004 +#define B_PL_DDFW_SH 0 +#define B_PL_DDFW_MSK 0xffffffffL + +#define R_PL_REG_DDSWR 0x1008 +#define B_PL_DDSW_SH 0 +#define B_PL_DDSW_MSK 0xffffffffL + +#define R_PL_REG_DES_PKTCONF 0x100C +#define B_PL_DBG_DPTR_SH 8 +#define B_PL_DBG_DPTR_MSK 0xff +#define B_PL_DBG_SPTR_SH 0 +#define B_PL_DBG_SPTR_MSK 0xff + +#define R_PL_REG_DBGSDR 0x1010 +#define B_PL_DBG_SD_SH 0 +#define B_PL_DBG_SD_MSK 0xffffffffL + +#define R_PL_REG_DBGDDR 0x1014 +#define B_PL_DBG_DD_SH 0 +#define B_PL_DBG_DD_MSK 0xffffffffL + +// +// WL_AX_Reg_HAXIDMA.xls +// + +// +// PCIE +// + +#define R_AX_HAXI_INIT_CFG1 0x1000 +#define B_AX_WD_ITVL_IDLE_V1_SH 28 +#define B_AX_WD_ITVL_IDLE_V1_MSK 0xf +#define B_AX_WD_ITVL_ACT_V1_SH 24 +#define B_AX_WD_ITVL_ACT_V1_MSK 0xf +#define B_AX_DMA_MODE_SH 18 +#define B_AX_DMA_MODE_MSK 0x3 +#define B_AX_STOP_AXI_MST BIT(17) +#define B_AX_HAXI_RST_KEEP_REG BIT(16) +#define B_AX_RXHCI_EN_V1 BIT(15) +#define B_AX_RXBD_MODE_V1 BIT(14) +#define B_AX_HAXI_MAX_RXDMA_SH 8 +#define B_AX_HAXI_MAX_RXDMA_MSK 0x3 +#define B_AX_TXHCI_EN_V1 BIT(7) +#define B_AX_FLUSH_AXI_MST BIT(4) +#define B_AX_RST_BDRAM BIT(3) +#define B_AX_HAXI_MAX_TXDMA_SH 0 +#define B_AX_HAXI_MAX_TXDMA_MSK 0x3 + +#define R_AX_HAXI_DMA_STOP1 0x1010 +#define B_AX_STOP_WPDMA BIT(19) +#define B_AX_STOP_CH12 BIT(18) +#define B_AX_STOP_CH9 BIT(17) +#define B_AX_STOP_CH8 BIT(16) +#define B_AX_STOP_ACH7 BIT(15) +#define B_AX_STOP_ACH6 BIT(14) +#define B_AX_STOP_ACH5 BIT(13) +#define B_AX_STOP_ACH4 BIT(12) +#define B_AX_STOP_ACH3 BIT(11) +#define B_AX_STOP_ACH2 BIT(10) +#define B_AX_STOP_ACH1 BIT(9) +#define B_AX_STOP_ACH0 BIT(8) + +#define R_AX_TXBD_RWPTR_CLR1 0x1014 +#define B_AX_CLR_CH12_IDX BIT(10) +#define B_AX_CLR_CH9_IDX BIT(9) +#define B_AX_CLR_CH8_IDX BIT(8) +#define B_AX_CLR_ACH7_IDX BIT(7) +#define B_AX_CLR_ACH6_IDX BIT(6) +#define B_AX_CLR_ACH5_IDX BIT(5) +#define B_AX_CLR_ACH4_IDX BIT(4) +#define B_AX_CLR_ACH3_IDX BIT(3) +#define B_AX_CLR_ACH2_IDX BIT(2) +#define B_AX_CLR_ACH1_IDX BIT(1) +#define B_AX_CLR_ACH0_IDX BIT(0) + +#define R_AX_HAXI_DMA_BUSY1 0x101C +#define B_AX_HAXIIO_BUSY BIT(20) +#define B_AX_WPDMA_BUSY BIT(19) +#define B_AX_CH12_BUSY BIT(18) +#define B_AX_CH9_BUSY BIT(17) +#define B_AX_CH8_BUSY BIT(16) +#define B_AX_ACH7_BUSY BIT(15) +#define B_AX_ACH6_BUSY BIT(14) +#define B_AX_ACH5_BUSY BIT(13) +#define B_AX_ACH4_BUSY BIT(12) +#define B_AX_ACH3_BUSY BIT(11) +#define B_AX_ACH2_BUSY BIT(10) +#define B_AX_ACH1_BUSY BIT(9) +#define B_AX_ACH0_BUSY BIT(8) + +#define R_AX_HAXI_DMA_STOP2 0x11C0 +#define B_AX_STOP_CH11 BIT(1) +#define B_AX_STOP_CH10 BIT(0) + +#define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4 +#define B_AX_CLR_CH11_IDX BIT(1) +#define B_AX_CLR_CH10_IDX BIT(0) + +#define R_AX_HAXI_DMA_BUSY2 0x11C8 +#define B_AX_CH11_BUSY BIT(1) +#define B_AX_CH10_BUSY BIT(0) + +#define R_AX_RXBD_RWPTR_CLR_V1 0x1200 +#define B_AX_CLR_RPQ_IDX BIT(1) +#define B_AX_CLR_RXQ_IDX BIT(0) + +#define R_AX_HAXI_EXP_CTRL 0x1204 +#define B_AX_MAX_TAG_NUM_V1_SH 0 +#define B_AX_MAX_TAG_NUM_V1_MSK 0x7 + +#define R_AX_HAXI_DMA_BUSY3 0x1208 +#define B_AX_RPQ_BUSY BIT(1) +#define B_AX_RXQ_BUSY BIT(0) + +#define R_AX_RXQ_RXBD_NUM_V1 0x1210 + +#define R_AX_RPQ_RXBD_NUM_V1 0x1212 + +#define R_AX_RXQ_RXBD_IDX_V1 0x1218 + +#define R_AX_RPQ_RXBD_IDX_V1 0x121C + +#define R_AX_RXQ_RXBD_DESA_L_V1 0x1220 + +#define R_AX_RXQ_RXBD_DESA_H_V1 0x1224 + +#define R_AX_RPQ_RXBD_DESA_L_V1 0x1228 + +#define R_AX_RPQ_RXBD_DESA_H_V1 0x122C + +#define R_AX_ACH0_TXBD_DESA_L_V1 0x1230 + +#define R_AX_ACH0_TXBD_DESA_H_V1 0x1234 + +#define R_AX_ACH1_TXBD_DESA_L_V1 0x1238 + +#define R_AX_ACH1_TXBD_DESA_H_V1 0x123C + +#define R_AX_ACH2_TXBD_DESA_L_V1 0x1240 + +#define R_AX_ACH2_TXBD_DESA_H_V1 0x1244 + +#define R_AX_ACH3_TXBD_DESA_L_V1 0x1248 + +#define R_AX_ACH3_TXBD_DESA_H_V1 0x124C + +#define R_AX_ACH4_TXBD_DESA_L_V1 0x1250 + +#define R_AX_ACH4_TXBD_DESA_H_V1 0x1254 + +#define R_AX_ACH5_TXBD_DESA_L_V1 0x1258 + +#define R_AX_ACH5_TXBD_DESA_H_V1 0x125C + +#define R_AX_ACH6_TXBD_DESA_L_V1 0x1260 + +#define R_AX_ACH6_TXBD_DESA_H_V1 0x1264 + +#define R_AX_ACH7_TXBD_DESA_L_V1 0x1268 + +#define R_AX_ACH7_TXBD_DESA_H_V1 0x126C + +#define R_AX_CH8_TXBD_DESA_L_V1 0x1270 + +#define R_AX_CH8_TXBD_DESA_H_V1 0x1274 + +#define R_AX_CH9_TXBD_DESA_L_V1 0x1278 + +#define R_AX_CH9_TXBD_DESA_H_V1 0x127C + +#define R_AX_CH12_TXBD_DESA_L_V1 0x1280 + +#define R_AX_CH12_TXBD_DESA_H_V1 0x1284 + +#define R_AX_ACH0_BDRAM_CTRL_V1 0x1300 + +#define R_AX_ACH1_BDRAM_CTRL_V1 0x1304 + +#define R_AX_ACH2_BDRAM_CTRL_V1 0x1308 + +#define R_AX_ACH3_BDRAM_CTRL_V1 0x130C + +#define R_AX_ACH4_BDRAM_CTRL_V1 0x1310 + +#define R_AX_ACH5_BDRAM_CTRL_V1 0x1314 + +#define R_AX_ACH6_BDRAM_CTRL_V1 0x1318 + +#define R_AX_ACH7_BDRAM_CTRL_V1 0x131C + +#define R_AX_CH8_BDRAM_CTRL_V1 0x1320 + +#define R_AX_CH9_BDRAM_CTRL_V1 0x1324 + +#define R_AX_CH12_BDRAM_CTRL_V1 0x1328 + +#define R_AX_CH10_BDRAM_CTRL_V1 0x1420 + +#define R_AX_CH11_BDRAM_CTRL_V1 0x1424 + +#define R_AX_CH10_TXBD_NUM_V1 0x1438 + +#define R_AX_CH11_TXBD_NUM_V1 0x143A + +#define R_AX_CH10_TXBD_DESA_L_V1 0x1458 + +#define R_AX_CH10_TXBD_DESA_H_V1 0x145C + +#define R_AX_CH11_TXBD_DESA_L_V1 0x1460 + +#define R_AX_CH11_TXBD_DESA_H_V1 0x1464 + +// +// WL_AX_Reg_PCIE.xls +// + +// +// PCIE +// + +#define R_AX_PCIE_INIT_CFG1 0x1000 +#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) +#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) +#define B_AX_PCIE_PERST_KEEP_REG BIT(21) +#define B_AX_PCIE_FLR_KEEP_REG BIT(20) +#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) +#define B_AX_RXBD_MODE BIT(18) +#define B_AX_PCIE_MAX_RXDMA_SH 14 +#define B_AX_PCIE_MAX_RXDMA_MSK 0x7 +#define B_AX_RXHCI_EN BIT(13) +#define B_AX_LATENCY_CONTROL BIT(12) +#define B_AX_TXHCI_EN BIT(11) +#define B_AX_PCIE_MAX_TXDMA_SH 8 +#define B_AX_PCIE_MAX_TXDMA_MSK 0x7 +#define B_AX_TX_TRUNC_MODE BIT(5) +#define B_AX_RX_TRUNC_MODE BIT(4) +#define B_AX_RST_BDRAM BIT(3) +#define B_AX_DIS_RXDMA_PRE BIT(2) + +#define R_AX_PCIE_INIT_CFG2 0x1004 +#define B_AX_WD_ITVL_IDLE_SH 24 +#define B_AX_WD_ITVL_IDLE_MSK 0xf +#define B_AX_WD_ITVL_ACT_SH 16 +#define B_AX_WD_ITVL_ACT_MSK 0xf +#define B_AX_PCIE_RX_APPLEN_SH 0 +#define B_AX_PCIE_RX_APPLEN_MSK 0x3fff + +#define R_AX_PCIE_PS_CTRL 0x1008 +#define B_AX_TXON_EXIT_L1_EN BIT(7) +#define B_AX_WD_NO_EMP_EXIT_L1_EN BIT(6) +#define B_AX_L1OFF_PWR_OFF_EN BIT(5) +#define B_AX_PCIE_FORCE_L0 BIT(4) +#define B_AX_TXFLAG_EXIT_L1_EN BIT(3) +#define B_AX_EN_HWENTR_L1 BIT(2) +#define B_AX_PCIE_EN_SWENT_L23 BIT(1) +#define B_AX_PCIE_EN_HWEXT_L1 BIT(0) + +#define R_AX_PCIE_MIX_CFG 0x100C +#define B_AX_PCIE_T3_TIME_SH 22 +#define B_AX_PCIE_T3_TIME_MSK 0x3 +#define B_AX_PCIE_T2_TIME_SH 20 +#define B_AX_PCIE_T2_TIME_MSK 0x3 +#define B_AX_HOTRST_EN BIT(19) +#define B_AX_MDIO_MODE BIT(18) +#define B_AX_CHANGE_PCIE_SPEED BIT(16) +#define B_AX_GEN1_GEN2_SH 14 +#define B_AX_GEN1_GEN2_MSK 0x3 +#define B_AX_HPS_CLKR_PCIE_SH 12 +#define B_AX_HPS_CLKR_PCIE_MSK 0x3 +#define B_AX_PCIE_INT BIT(11) +#define B_AX_PCIEIO_PERSTB_SEL BIT(10) +#define B_AX_EPHY_RX50_EN BIT(8) +#define B_AX_MSI_TIMEOUT_ID_V1_SH 5 +#define B_AX_MSI_TIMEOUT_ID_V1_MSK 0x7 +#define B_AX_RADDR_RD BIT(4) +#define B_AX_ECRC_EN BIT(3) +#define B_AX_EN_SLOW_MAC_TX BIT(2) +#define B_AX_EN_SLOW_MAC_RX BIT(1) +#define B_AX_EN_SLOW_MAC_HW BIT(0) + +#define R_AX_PCIE_DMA_STOP1 0x1010 +#define B_AX_STOP_PCIEIO BIT(20) +#define B_AX_STOP_WPDMA BIT(19) +#define B_AX_STOP_CH12 BIT(18) +#define B_AX_STOP_CH9 BIT(17) +#define B_AX_STOP_CH8 BIT(16) +#define B_AX_STOP_ACH7 BIT(15) +#define B_AX_STOP_ACH6 BIT(14) +#define B_AX_STOP_ACH5 BIT(13) +#define B_AX_STOP_ACH4 BIT(12) +#define B_AX_STOP_ACH3 BIT(11) +#define B_AX_STOP_ACH2 BIT(10) +#define B_AX_STOP_ACH1 BIT(9) +#define B_AX_STOP_ACH0 BIT(8) + +#define R_AX_TXBD_RWPTR_CLR1 0x1014 +#define B_AX_CLR_CH12_IDX BIT(10) +#define B_AX_CLR_CH9_IDX BIT(9) +#define B_AX_CLR_CH8_IDX BIT(8) +#define B_AX_CLR_ACH7_IDX BIT(7) +#define B_AX_CLR_ACH6_IDX BIT(6) +#define B_AX_CLR_ACH5_IDX BIT(5) +#define B_AX_CLR_ACH4_IDX BIT(4) +#define B_AX_CLR_ACH3_IDX BIT(3) +#define B_AX_CLR_ACH2_IDX BIT(2) +#define B_AX_CLR_ACH1_IDX BIT(1) +#define B_AX_CLR_ACH0_IDX BIT(0) + +#define R_AX_RXBD_RWPTR_CLR 0x1018 +#define B_AX_CLR_RPQ_IDX BIT(1) +#define B_AX_CLR_RXQ_IDX BIT(0) + +#define R_AX_PCIE_DMA_BUSY1 0x101C +#define B_AX_PCIEIO_RX_BUSY BIT(22) +#define B_AX_PCIEIO_TX_BUSY BIT(21) +#define B_AX_PCIEIO_BUSY BIT(20) +#define B_AX_WPDMA_BUSY BIT(19) +#define B_AX_CH12_BUSY BIT(18) +#define B_AX_CH9_BUSY BIT(17) +#define B_AX_CH8_BUSY BIT(16) +#define B_AX_ACH7_BUSY BIT(15) +#define B_AX_ACH6_BUSY BIT(14) +#define B_AX_ACH5_BUSY BIT(13) +#define B_AX_ACH4_BUSY BIT(12) +#define B_AX_ACH3_BUSY BIT(11) +#define B_AX_ACH2_BUSY BIT(10) +#define B_AX_ACH1_BUSY BIT(9) +#define B_AX_ACH0_BUSY BIT(8) +#define B_AX_RPQ_BUSY BIT(1) +#define B_AX_RXQ_BUSY BIT(0) + +#define R_AX_RXQ_RXBD_NUM 0x1020 +#define B_AX_RXQ_DESC_NUM_SH 0 +#define B_AX_RXQ_DESC_NUM_MSK 0xfff + +#define R_AX_RPQ_RXBD_NUM 0x1022 +#define B_AX_RPQ_DESC_NUM_SH 0 +#define B_AX_RPQ_DESC_NUM_MSK 0xfff + +#define R_AX_ACH0_TXBD_NUM 0x1024 +#define B_AX_PCIE_ACH0_FLAG BIT(14) +#define B_AX_ACH0_DESC_NUM_SH 0 +#define B_AX_ACH0_DESC_NUM_MSK 0xfff + +#define R_AX_ACH1_TXBD_NUM 0x1026 +#define B_AX_PCIE_ACH1_FLAG BIT(14) +#define B_AX_ACH1_DESC_NUM_SH 0 +#define B_AX_ACH1_DESC_NUM_MSK 0xfff + +#define R_AX_ACH2_TXBD_NUM 0x1028 +#define B_AX_PCIE_ACH2_FLAG BIT(14) +#define B_AX_ACH2_DESC_NUM_SH 0 +#define B_AX_ACH2_DESC_NUM_MSK 0xfff + +#define R_AX_ACH3_TXBD_NUM 0x102A +#define B_AX_PCIE_ACH3_FLAG BIT(14) +#define B_AX_ACH3_DESC_NUM_SH 0 +#define B_AX_ACH3_DESC_NUM_MSK 0xfff + +#define R_AX_ACH4_TXBD_NUM 0x102C +#define B_AX_PCIE_ACH4_FLAG BIT(14) +#define B_AX_ACH4_DESC_NUM_SH 0 +#define B_AX_ACH4_DESC_NUM_MSK 0xfff + +#define R_AX_ACH5_TXBD_NUM 0x102E +#define B_AX_PCIE_ACH5_FLAG BIT(14) +#define B_AX_ACH5_DESC_NUM_SH 0 +#define B_AX_ACH5_DESC_NUM_MSK 0xfff + +#define R_AX_ACH6_TXBD_NUM 0x1030 +#define B_AX_PCIE_ACH6_FLAG BIT(14) +#define B_AX_ACH6_DESC_NUM_SH 0 +#define B_AX_ACH6_DESC_NUM_MSK 0xfff + +#define R_AX_ACH7_TXBD_NUM 0x1032 +#define B_AX_PCIE_ACH7_FLAG BIT(14) +#define B_AX_ACH7_DESC_NUM_SH 0 +#define B_AX_ACH7_DESC_NUM_MSK 0xfff + +#define R_AX_CH8_TXBD_NUM 0x1034 +#define B_AX_PCIE_CH8_FLAG BIT(14) +#define B_AX_CH8_DESC_NUM_SH 0 +#define B_AX_CH8_DESC_NUM_MSK 0xfff + +#define R_AX_CH9_TXBD_NUM 0x1036 +#define B_AX_PCIE_CH9_FLAG BIT(14) +#define B_AX_CH9_DESC_NUM_SH 0 +#define B_AX_CH9_DESC_NUM_MSK 0xfff + +#define R_AX_CH12_TXBD_NUM 0x1038 +#define B_AX_PCIE_CH12_FLAG BIT(14) +#define B_AX_CH12_DESC_NUM_SH 0 +#define B_AX_CH12_DESC_NUM_MSK 0xfff + +#define R_AX_RXQ_RXBD_IDX 0x1050 +#define B_AX_RXQ_HW_IDX_SH 16 +#define B_AX_RXQ_HW_IDX_MSK 0xfff +#define B_AX_RXQ_HOST_IDX_SH 0 +#define B_AX_RXQ_HOST_IDX_MSK 0xfff + +#define R_AX_RPQ_RXBD_IDX 0x1054 +#define B_AX_RPQ_HW_IDX_SH 16 +#define B_AX_RPQ_HW_IDX_MSK 0xfff +#define B_AX_RPQ_HOST_IDX_SH 0 +#define B_AX_RPQ_HOST_IDX_MSK 0xfff + +#define R_AX_ACH0_TXBD_IDX 0x1058 +#define B_AX_ACH0_HW_IDX_SH 16 +#define B_AX_ACH0_HW_IDX_MSK 0xfff +#define B_AX_ACH0_HOST_IDX_SH 0 +#define B_AX_ACH0_HOST_IDX_MSK 0xfff + +#define R_AX_ACH1_TXBD_IDX 0x105C +#define B_AX_ACH1_HW_IDX_SH 16 +#define B_AX_ACH1_HW_IDX_MSK 0xfff +#define B_AX_ACH1_HOST_IDX_SH 0 +#define B_AX_ACH1_HOST_IDX_MSK 0xfff + +#define R_AX_ACH2_TXBD_IDX 0x1060 +#define B_AX_ACH2_HW_IDX_SH 16 +#define B_AX_ACH2_HW_IDX_MSK 0xfff +#define B_AX_ACH2_HOST_IDX_SH 0 +#define B_AX_ACH2_HOST_IDX_MSK 0xfff + +#define R_AX_ACH3_TXBD_IDX 0x1064 +#define B_AX_ACH3_HW_IDX_SH 16 +#define B_AX_ACH3_HW_IDX_MSK 0xfff +#define B_AX_ACH3_HOST_IDX_SH 0 +#define B_AX_ACH3_HOST_IDX_MSK 0xfff + +#define R_AX_ACH4_TXBD_IDX 0x1068 +#define B_AX_ACH4_HW_IDX_SH 16 +#define B_AX_ACH4_HW_IDX_MSK 0xfff +#define B_AX_ACH4_HOST_IDX_SH 0 +#define B_AX_ACH4_HOST_IDX_MSK 0xfff + +#define R_AX_ACH5_TXBD_IDX 0x106C +#define B_AX_ACH5_HW_IDX_SH 16 +#define B_AX_ACH5_HW_IDX_MSK 0xfff +#define B_AX_ACH5_HOST_IDX_SH 0 +#define B_AX_ACH5_HOST_IDX_MSK 0xfff + +#define R_AX_ACH6_TXBD_IDX 0x1070 +#define B_AX_ACH6_HW_IDX_SH 16 +#define B_AX_ACH6_HW_IDX_MSK 0xfff +#define B_AX_ACH6_HOST_IDX_SH 0 +#define B_AX_ACH6_HOST_IDX_MSK 0xfff + +#define R_AX_ACH7_TXBD_IDX 0x1074 +#define B_AX_ACH7_HW_IDX_SH 16 +#define B_AX_ACH7_HW_IDX_MSK 0xfff +#define B_AX_ACH7_HOST_IDX_SH 0 +#define B_AX_ACH7_HOST_IDX_MSK 0xfff + +#define R_AX_CH8_TXBD_IDX 0x1078 +#define B_AX_CH8_HW_IDX_SH 16 +#define B_AX_CH8_HW_IDX_MSK 0xfff +#define B_AX_CH8_HOST_IDX_SH 0 +#define B_AX_CH8_HOST_IDX_MSK 0xfff + +#define R_AX_CH9_TXBD_IDX 0x107C +#define B_AX_CH9_HW_IDX_SH 16 +#define B_AX_CH9_HW_IDX_MSK 0xfff +#define B_AX_CH9_HOST_IDX_SH 0 +#define B_AX_CH9_HOST_IDX_MSK 0xfff + +#define R_AX_CH12_TXBD_IDX 0x1080 +#define B_AX_CH12_HW_IDX_SH 16 +#define B_AX_CH12_HW_IDX_MSK 0xfff +#define B_AX_CH12_HOST_IDX_SH 0 +#define B_AX_CH12_HOST_IDX_MSK 0xfff + +#define R_AX_DBI_FLAG 0x1090 +#define B_AX_DBI_RFLAG BIT(17) +#define B_AX_DBI_WFLAG BIT(16) +#define B_AX_DBI_WREN_SH 12 +#define B_AX_DBI_WREN_MSK 0xf +#define B_AX_DBI_ADDR_SH 0 +#define B_AX_DBI_ADDR_MSK 0xfff + +#define R_AX_DBI_WDATA 0x1094 +#define B_AX_DBI_WDATA_SH 0 +#define B_AX_DBI_WDATA_MSK 0xffffffffL + +#define R_AX_DBI_RDATA 0x1098 +#define B_AX_DBI_RDATA_SH 0 +#define B_AX_DBI_RDATA_MSK 0xffffffffL + +#define R_AX_MDIO_CFG 0x10A0 +#define B_AX_MDIO_PHY_ADDR_SH 12 +#define B_AX_MDIO_PHY_ADDR_MSK 0x3 +#define B_AX_MDIO_RFLAG BIT(9) +#define B_AX_MDIO_WFLAG BIT(8) +#define B_AX_MDIO_ADDR_SH 0 +#define B_AX_MDIO_ADDR_MSK 0x1f + +#define R_AX_MDIO_WDATA 0x10A4 +#define B_AX_MDIO_WDATA_SH 0 +#define B_AX_MDIO_WDATA_MSK 0xffff + +#define R_AX_MDIO_RDATA 0x10A6 +#define B_AX_MDIO_RDATA_SH 0 +#define B_AX_MDIO_RDATA_MSK 0xffff + +#define R_AX_PCIE_HIMR00 0x10B0 +#define B_AX_HC00ISR_IND_INT_EN BIT(27) +#define B_AX_HD1ISR_IND_INT_EN BIT(26) +#define B_AX_HD0ISR_IND_INT_EN BIT(25) +#define B_AX_HS0ISR_IND_INT_EN BIT(24) +#define B_AX_RETRAIN_INT_EN BIT(21) +#define B_AX_RPQBD_FULL_INT_EN BIT(20) +#define B_AX_RDU_INT_EN BIT(19) +#define B_AX_RXDMA_STUCK_INT_EN BIT(18) +#define B_AX_TXDMA_STUCK_INT_EN BIT(17) +#define B_AX_PCIE_HOTRST_INT_EN BIT(16) +#define B_AX_PCIE_FLR_INT_EN BIT(15) +#define B_AX_PCIE_PERST_INT_EN BIT(14) +#define B_AX_TXDMA_CH12_INT_EN BIT(13) +#define B_AX_TXDMA_CH9_INT_EN BIT(12) +#define B_AX_TXDMA_CH8_INT_EN BIT(11) +#define B_AX_TXDMA_ACH7_INT_EN BIT(10) +#define B_AX_TXDMA_ACH6_INT_EN BIT(9) +#define B_AX_TXDMA_ACH5_INT_EN BIT(8) +#define B_AX_TXDMA_ACH4_INT_EN BIT(7) +#define B_AX_TXDMA_ACH3_INT_EN BIT(6) +#define B_AX_TXDMA_ACH2_INT_EN BIT(5) +#define B_AX_TXDMA_ACH1_INT_EN BIT(4) +#define B_AX_TXDMA_ACH0_INT_EN BIT(3) +#define B_AX_RPQDMA_INT_EN BIT(2) +#define B_AX_RXP1DMA_INT_EN BIT(1) +#define B_AX_RXDMA_INT_EN BIT(0) + +#define R_AX_PCIE_HISR00 0x10B4 +#define B_AX_HC00ISR_IND_INT BIT(27) +#define B_AX_HD1ISR_IND_INT BIT(26) +#define B_AX_HD0ISR_IND_INT BIT(25) +#define B_AX_HS0ISR_IND_INT BIT(24) +#define B_AX_RETRAIN_INT BIT(21) +#define B_AX_RPQBD_FULL_INT BIT(20) +#define B_AX_RDU_INT BIT(19) +#define B_AX_RXDMA_STUCK_INT BIT(18) +#define B_AX_TXDMA_STUCK_INT BIT(17) +#define B_AX_PCIE_HOTRST_INT BIT(16) +#define B_AX_PCIE_FLR_INT BIT(15) +#define B_AX_PCIE_PERST_INT BIT(14) +#define B_AX_TXDMA_CH12_INT BIT(13) +#define B_AX_TXDMA_CH9_INT BIT(12) +#define B_AX_TXDMA_CH8_INT BIT(11) +#define B_AX_TXDMA_ACH7_INT BIT(10) +#define B_AX_TXDMA_ACH6_INT BIT(9) +#define B_AX_TXDMA_ACH5_INT BIT(8) +#define B_AX_TXDMA_ACH4_INT BIT(7) +#define B_AX_TXDMA_ACH3_INT BIT(6) +#define B_AX_TXDMA_ACH2_INT BIT(5) +#define B_AX_TXDMA_ACH1_INT BIT(4) +#define B_AX_TXDMA_ACH0_INT BIT(3) +#define B_AX_RPQDMA_INT BIT(2) +#define B_AX_RXP1DMA_INT BIT(1) +#define B_AX_RXDMA_INT BIT(0) + +#define R_AX_PCIE_HRPWM 0x10C0 +#define B_AX_PCIE_HRPWM_SH 0 +#define B_AX_PCIE_HRPWM_MSK 0xffff + +#define R_AX_INT_MIT_TX 0x10D0 +#define B_AX_TXMIT_CH12_SEL BIT(31) +#define B_AX_TXMIT_CH11_SEL BIT(30) +#define B_AX_TXMIT_CH10_SEL BIT(29) +#define B_AX_TXMIT_CH9_SEL BIT(28) +#define B_AX_TXMIT_CH8_SEL BIT(27) +#define B_AX_TXMIT_ACH7_SEL BIT(26) +#define B_AX_TXMIT_ACH6_SEL BIT(25) +#define B_AX_TXMIT_ACH5_SEL BIT(24) +#define B_AX_TXMIT_ACH4_SEL BIT(23) +#define B_AX_TXMIT_ACH3_SEL BIT(22) +#define B_AX_TXMIT_ACH2_SEL BIT(21) +#define B_AX_TXMIT_ACH1_SEL BIT(20) +#define B_AX_TXMIT_ACH0_SEL BIT(19) +#define B_AX_TXTIMER_UNIT_SH 16 +#define B_AX_TXTIMER_UNIT_MSK 0x3 +#define B_AX_TXCOUNTER_MATCH_SH 8 +#define B_AX_TXCOUNTER_MATCH_MSK 0xff +#define B_AX_TXTIMER_MATCH_SH 0 +#define B_AX_TXTIMER_MATCH_MSK 0xff + +#define R_AX_INT_MIT_RX 0x10D4 +#define B_AX_RXMIT_RXP2_SEL BIT(19) +#define B_AX_RXMIT_RXP1_SEL BIT(18) +#define B_AX_RXTIMER_UNIT_SH 16 +#define B_AX_RXTIMER_UNIT_MSK 0x3 +#define B_AX_RXCOUNTER_MATCH_SH 8 +#define B_AX_RXCOUNTER_MATCH_MSK 0xff +#define B_AX_RXTIMER_MATCH_SH 0 +#define B_AX_RXTIMER_MATCH_MSK 0xff + +#define R_AX_TXDMA_ADDR_H 0x10F0 +#define B_AX_TXDMA_ADDR_H_SH 0 +#define B_AX_TXDMA_ADDR_H_MSK 0xffffffffL + +#define R_AX_RXDMA_ADDR_H 0x10F4 +#define B_AX_RXDMA_ADDR_H_SH 0 +#define B_AX_RXDMA_ADDR_H_MSK 0xffffffffL + +#define R_AX_PCIE_INFO 0x10F8 +#define B_AX_HOST_GEN2_SUPPORT BIT(4) +#define B_AX_ACT_LINK_OFF BIT(2) +#define B_AX_PCIERX_IDLE BIT(1) +#define B_AX_PCIETX_IDLE BIT(0) + +#define R_AX_TSFTIMER_HCI 0x10FC +#define B_AX_TSFT2_HCI_SH 16 +#define B_AX_TSFT2_HCI_MSK 0xffff +#define B_AX_TSFT1_HCI_SH 0 +#define B_AX_TSFT1_HCI_MSK 0xffff + +#define R_AX_RXQ_RXBD_DESA_L 0x1100 +#define B_AX_RXQ_RXBD_DESA_L_SH 0 +#define B_AX_RXQ_RXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_RXQ_RXBD_DESA_H 0x1104 +#define B_AX_RXQ_RXBD_DESA_H_SH 0 +#define B_AX_RXQ_RXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_RPQ_RXBD_DESA_L 0x1108 +#define B_AX_RPQ_RXBD_DESA_L_SH 0 +#define B_AX_RPQ_RXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_RPQ_RXBD_DESA_H 0x110C +#define B_AX_RPQ_RXBD_DESA_H_SH 0 +#define B_AX_RPQ_RXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH0_TXBD_DESA_L 0x1110 +#define B_AX_ACH0_TXBD_DESA_L_SH 0 +#define B_AX_ACH0_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH0_TXBD_DESA_H 0x1114 +#define B_AX_ACH0_TXBD_DESA_H_SH 0 +#define B_AX_ACH0_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH1_TXBD_DESA_L 0x1118 +#define B_AX_ACH1_TXBD_DESA_L_SH 0 +#define B_AX_ACH1_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH1_TXBD_DESA_H 0x111C +#define B_AX_ACH1_TXBD_DESA_H_SH 0 +#define B_AX_ACH1_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH2_TXBD_DESA_L 0x1120 +#define B_AX_ACH2_TXBD_DESA_L_SH 0 +#define B_AX_ACH2_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH2_TXBD_DESA_H 0x1124 +#define B_AX_ACH2_TXBD_DESA_H_SH 0 +#define B_AX_ACH2_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH3_TXBD_DESA_L 0x1128 +#define B_AX_ACH3_TXBD_DESA_L_SH 0 +#define B_AX_ACH3_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH3_TXBD_DESA_H 0x112C +#define B_AX_ACH3_TXBD_DESA_H_SH 0 +#define B_AX_ACH3_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH4_TXBD_DESA_L 0x1130 +#define B_AX_ACH4_TXBD_DESA_L_SH 0 +#define B_AX_ACH4_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH4_TXBD_DESA_H 0x1134 +#define B_AX_ACH4_TXBD_DESA_H_SH 0 +#define B_AX_ACH4_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH5_TXBD_DESA_L 0x1138 +#define B_AX_ACH5_TXBD_DESA_L_SH 0 +#define B_AX_ACH5_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH5_TXBD_DESA_H 0x113C +#define B_AX_ACH5_TXBD_DESA_H_SH 0 +#define B_AX_ACH5_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH6_TXBD_DESA_L 0x1140 +#define B_AX_ACH6_TXBD_DESA_L_SH 0 +#define B_AX_ACH6_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH6_TXBD_DESA_H 0x1144 +#define B_AX_ACH6_TXBD_DESA_H_SH 0 +#define B_AX_ACH6_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_ACH7_TXBD_DESA_L 0x1148 +#define B_AX_ACH7_TXBD_DESA_L_SH 0 +#define B_AX_ACH7_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_ACH7_TXBD_DESA_H 0x114C +#define B_AX_ACH7_TXBD_DESA_H_SH 0 +#define B_AX_ACH7_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_CH8_TXBD_DESA_L 0x1150 +#define B_AX_CH8_TXBD_DESA_L_SH 0 +#define B_AX_CH8_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_CH8_TXBD_DESA_H 0x1154 +#define B_AX_CH8_TXBD_DESA_H_SH 0 +#define B_AX_CH8_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_CH9_TXBD_DESA_L 0x1158 +#define B_AX_CH9_TXBD_DESA_L_SH 0 +#define B_AX_CH9_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_CH9_TXBD_DESA_H 0x115C +#define B_AX_CH9_TXBD_DESA_H_SH 0 +#define B_AX_CH9_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_CH12_TXBD_DESA_L 0x1160 +#define B_AX_CH12_TXBD_DESA_L_SH 0 +#define B_AX_CH12_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_CH12_TXBD_DESA_H 0x1164 +#define B_AX_CH12_TXBD_DESA_H_SH 0 +#define B_AX_CH12_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_PCIE_DBG_CTRL 0x11C0 +#define B_AX_DBG_DUMMY_SH 16 +#define B_AX_DBG_DUMMY_MSK 0xff +#define B_AX_DBG_SEL_SH 13 +#define B_AX_DBG_SEL_MSK 0x7 +#define B_AX_PCIE_DBG_SEL BIT(12) +#define B_AX_MRD_TIMEOUT_EN BIT(10) +#define B_AX_ASFF_FULL_NO_STK BIT(1) +#define B_AX_EN_STUCK_DBG BIT(0) + +#define R_AX_DBG_ERR_FLAG 0x11C4 +#define B_AX_PCIE_RPQ_FULL BIT(29) +#define B_AX_PCIE_RXQ_FULL BIT(28) +#define B_AX_CPL_STATUS_SH 25 +#define B_AX_CPL_STATUS_MSK 0x7 +#define B_AX_RX_STUCK BIT(22) +#define B_AX_TX_STUCK BIT(21) +#define B_AX_PCIEDBG_TXERR0 BIT(16) +#define B_AX_PCIE_RXP1_ERR0 BIT(4) +#define B_AX_PCIE_TXBD_LEN0 BIT(1) +#define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) + +#define R_AX_PCIE_LPWR_DBG 0x11C8 +#define B_AX_PCIE_L1_COND_CFG_SPC BIT(10) +#define B_AX_PCIE_L1_COND_MAC_REG BIT(9) +#define B_AX_PCIE_L1_COND_HISR BIT(8) +#define B_AX_PCIE_L1_COND_RX BIT(7) +#define B_AX_PCIE_L1_COND_TX BIT(6) +#define B_AX_PCIE_L1_COND_HDP_RX BIT(5) +#define B_AX_PCIE_L1_COND_LTR BIT(4) +#define B_AX_PCIE_L1_COND_FORC_L0 BIT(3) +#define B_AX_PCIE_L1_COND_WD_EMPY BIT(2) +#define B_AX_PCIE_L1_COND_TXFLAG1 BIT(1) +#define B_AX_PCIE_L1_COND_TXFLAG0 BIT(0) + +#define R_AX_STC_INT_CS 0x11D0 +#define B_AX_STC_INT_EN BIT(31) +#define B_AX_STC_INT_FLAG_SH 16 +#define B_AX_STC_INT_FLAG_MSK 0xff +#define B_AX_STC_INT_IDX_SH 8 +#define B_AX_STC_INT_IDX_MSK 0x7 +#define B_AX_STC_INT_REALTIME_CS_SH 0 +#define B_AX_STC_INT_REALTIME_CS_MSK 0x3f + +#define R_AX_ST_INT_CFG 0x11D4 +#define B_AX_STC_INT_GRP_EN BIT(31) +#define B_AX_STC_INT_EXPECT_LS_SH 8 +#define B_AX_STC_INT_EXPECT_LS_MSK 0x3f +#define B_AX_STC_INT_EXPECT_CS_SH 0 +#define B_AX_STC_INT_EXPECT_CS_MSK 0x3f + +#define R_AX_LBC_WATCHDOG 0x11D8 +#define B_AX_LBC_ADDR_SH 10 +#define B_AX_LBC_ADDR_MSK 0x3ffff +#define B_AX_LBC_TIMER_SH 4 +#define B_AX_LBC_TIMER_MSK 0xf +#define B_AX_LBC_FLAG BIT(1) +#define B_AX_LBC_EN BIT(0) + +#define R_AX_DEBUG_STATE1 0x11E0 +#define B_AX_DEBUG_STATE1_SH 0 +#define B_AX_DEBUG_STATE1_MSK 0xffffffffL + +#define R_AX_DEBUG_STATE2 0x11E4 +#define B_AX_DEBUG_STATE2_SH 0 +#define B_AX_DEBUG_STATE2_MSK 0xffffffffL + +#define R_AX_DEBUG_STATE3 0x11E8 +#define B_AX_DEBUG_STATE3_SH 0 +#define B_AX_DEBUG_STATE3_MSK 0xffffffffL + +#define R_AX_ACH0_BDRAM_CTRL 0x1200 +#define B_AX_ACH0_BDRAM_MIN_SH 16 +#define B_AX_ACH0_BDRAM_MIN_MSK 0xff +#define B_AX_ACH0_BDRAM_MAX_SH 8 +#define B_AX_ACH0_BDRAM_MAX_MSK 0xff +#define B_AX_ACH0_BDRAM_SIDX_SH 0 +#define B_AX_ACH0_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH1_BDRAM_CTRL 0x1204 +#define B_AX_ACH1_BDRAM_MIN_SH 16 +#define B_AX_ACH1_BDRAM_MIN_MSK 0xff +#define B_AX_ACH1_BDRAM_MAX_SH 8 +#define B_AX_ACH1_BDRAM_MAX_MSK 0xff +#define B_AX_ACH1_BDRAM_SIDX_SH 0 +#define B_AX_ACH1_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH2_BDRAM_CTRL 0x1208 +#define B_AX_ACH2_BDRAM_MIN_SH 16 +#define B_AX_ACH2_BDRAM_MIN_MSK 0xff +#define B_AX_ACH2_BDRAM_MAX_SH 8 +#define B_AX_ACH2_BDRAM_MAX_MSK 0xff +#define B_AX_ACH2_BDRAM_SIDX_SH 0 +#define B_AX_ACH2_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH3_BDRAM_CTRL 0x120C +#define B_AX_ACH3_BDRAM_MIN_SH 16 +#define B_AX_ACH3_BDRAM_MIN_MSK 0xff +#define B_AX_ACH3_BDRAM_MAX_SH 8 +#define B_AX_ACH3_BDRAM_MAX_MSK 0xff +#define B_AX_ACH3_BDRAM_SIDX_SH 0 +#define B_AX_ACH3_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH4_BDRAM_CTRL 0x1210 +#define B_AX_ACH4_BDRAM_MIN_SH 16 +#define B_AX_ACH4_BDRAM_MIN_MSK 0xff +#define B_AX_ACH4_BDRAM_MAX_SH 8 +#define B_AX_ACH4_BDRAM_MAX_MSK 0xff +#define B_AX_ACH4_BDRAM_SIDX_SH 0 +#define B_AX_ACH4_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH5_BDRAM_CTRL 0x1214 +#define B_AX_ACH5_BDRAM_MIN_SH 16 +#define B_AX_ACH5_BDRAM_MIN_MSK 0xff +#define B_AX_ACH5_BDRAM_MAX_SH 8 +#define B_AX_ACH5_BDRAM_MAX_MSK 0xff +#define B_AX_ACH5_BDRAM_SIDX_SH 0 +#define B_AX_ACH5_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH6_BDRAM_CTRL 0x1218 +#define B_AX_ACH6_BDRAM_MIN_SH 16 +#define B_AX_ACH6_BDRAM_MIN_MSK 0xff +#define B_AX_ACH6_BDRAM_MAX_SH 8 +#define B_AX_ACH6_BDRAM_MAX_MSK 0xff +#define B_AX_ACH6_BDRAM_SIDX_SH 0 +#define B_AX_ACH6_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH7_BDRAM_CTRL 0x121C +#define B_AX_ACH7_BDRAM_MIN_SH 16 +#define B_AX_ACH7_BDRAM_MIN_MSK 0xff +#define B_AX_ACH7_BDRAM_MAX_SH 8 +#define B_AX_ACH7_BDRAM_MAX_MSK 0xff +#define B_AX_ACH7_BDRAM_SIDX_SH 0 +#define B_AX_ACH7_BDRAM_SIDX_MSK 0xff + +#define R_AX_CH8_BDRAM_CTRL 0x1220 +#define B_AX_CH8_BDRAM_MIN_SH 16 +#define B_AX_CH8_BDRAM_MIN_MSK 0xff +#define B_AX_CH8_BDRAM_MAX_SH 8 +#define B_AX_CH8_BDRAM_MAX_MSK 0xff +#define B_AX_CH8_BDRAM_SIDX_SH 0 +#define B_AX_CH8_BDRAM_SIDX_MSK 0xff + +#define R_AX_CH9_BDRAM_CTRL 0x1224 +#define B_AX_CH9_BDRAM_MIN_SH 16 +#define B_AX_CH9_BDRAM_MIN_MSK 0xff +#define B_AX_CH9_BDRAM_MAX_SH 8 +#define B_AX_CH9_BDRAM_MAX_MSK 0xff +#define B_AX_CH9_BDRAM_SIDX_SH 0 +#define B_AX_CH9_BDRAM_SIDX_MSK 0xff + +#define R_AX_CH12_BDRAM_CTRL 0x1228 +#define B_AX_CH12_BDRAM_MIN_SH 16 +#define B_AX_CH12_BDRAM_MIN_MSK 0xff +#define B_AX_CH12_BDRAM_MAX_SH 8 +#define B_AX_CH12_BDRAM_MAX_MSK 0xff +#define B_AX_CH12_BDRAM_SIDX_SH 0 +#define B_AX_CH12_BDRAM_SIDX_MSK 0xff + +#define R_AX_ACH0_BDRAM_RWPTR 0x1230 +#define B_AX_ACH0_BDRAM_WPTR_SH 8 +#define B_AX_ACH0_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH0_BDRAM_RPTR_SH 0 +#define B_AX_ACH0_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH1_BDRAM_RWPTR 0x1232 +#define B_AX_ACH1_BDRAM_WPTR_SH 8 +#define B_AX_ACH1_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH1_BDRAM_RPTR_SH 0 +#define B_AX_ACH1_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH2_BDRAM_RWPTR 0x1234 +#define B_AX_ACH2_BDRAM_WPTR_SH 8 +#define B_AX_ACH2_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH2_BDRAM_RPTR_SH 0 +#define B_AX_ACH2_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH3_BDRAM_RWPTR 0x1236 +#define B_AX_ACH3_BDRAM_WPTR_SH 8 +#define B_AX_ACH3_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH3_BDRAM_RPTR_SH 0 +#define B_AX_ACH3_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH4_BDRAM_RWPTR 0x1238 +#define B_AX_ACH4_BDRAM_WPTR_SH 8 +#define B_AX_ACH4_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH4_BDRAM_RPTR_SH 0 +#define B_AX_ACH4_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH5_BDRAM_RWPTR 0x123A +#define B_AX_ACH5_BDRAM_WPTR_SH 8 +#define B_AX_ACH5_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH5_BDRAM_RPTR_SH 0 +#define B_AX_ACH5_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH6_BDRAM_RWPTR 0x123C +#define B_AX_ACH6_BDRAM_WPTR_SH 8 +#define B_AX_ACH6_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH6_BDRAM_RPTR_SH 0 +#define B_AX_ACH6_BDRAM_RPTR_MSK 0xff + +#define R_AX_ACH7_BDRAM_RWPTR 0x123E +#define B_AX_ACH7_BDRAM_WPTR_SH 8 +#define B_AX_ACH7_BDRAM_WPTR_MSK 0xff +#define B_AX_ACH7_BDRAM_RPTR_SH 0 +#define B_AX_ACH7_BDRAM_RPTR_MSK 0xff + +#define R_AX_CH8_BDRAM_RWPTR 0x1240 +#define B_AX_CH8_BDRAM_WPTR_SH 8 +#define B_AX_CH8_BDRAM_WPTR_MSK 0xff +#define B_AX_CH8_BDRAM_RPTR_SH 0 +#define B_AX_CH8_BDRAM_RPTR_MSK 0xff + +#define R_AX_CH9_BDRAM_RWPTR 0x1242 +#define B_AX_CH9_BDRAM_WPTR_SH 8 +#define B_AX_CH9_BDRAM_WPTR_MSK 0xff +#define B_AX_CH9_BDRAM_RPTR_SH 0 +#define B_AX_CH9_BDRAM_RPTR_MSK 0xff + +#define R_AX_CH12_BDRAM_RWPTR 0x1244 +#define B_AX_CH12_BDRAM_WPTR_SH 8 +#define B_AX_CH12_BDRAM_WPTR_MSK 0xff +#define B_AX_CH12_BDRAM_RPTR_SH 0 +#define B_AX_CH12_BDRAM_RPTR_MSK 0xff + +#define R_AX_PCIE_DMA_STOP2 0x1310 +#define B_AX_STOP_CH11 BIT(1) +#define B_AX_STOP_CH10 BIT(0) + +#define R_AX_TXBD_RWPTR_CLR2 0x1314 +#define B_AX_CLR_CH11_IDX BIT(1) +#define B_AX_CLR_CH10_IDX BIT(0) + +#define R_AX_PCIE_DMA_BUSY2 0x131C +#define B_AX_CH11_BUSY BIT(1) +#define B_AX_CH10_BUSY BIT(0) + +#define R_AX_CH10_BDRAM_CTRL 0x1320 +#define B_AX_CH10_BDRAM_MIN_SH 16 +#define B_AX_CH10_BDRAM_MIN_MSK 0xff +#define B_AX_CH10_BDRAM_MAX_SH 8 +#define B_AX_CH10_BDRAM_MAX_MSK 0xff +#define B_AX_CH10_BDRAM_SIDX_SH 0 +#define B_AX_CH10_BDRAM_SIDX_MSK 0xff + +#define R_AX_CH11_BDRAM_CTRL 0x1324 +#define B_AX_CH11_BDRAM_MIN_SH 16 +#define B_AX_CH11_BDRAM_MIN_MSK 0xff +#define B_AX_CH11_BDRAM_MAX_SH 8 +#define B_AX_CH11_BDRAM_MAX_MSK 0xff +#define B_AX_CH11_BDRAM_SIDX_SH 0 +#define B_AX_CH11_BDRAM_SIDX_MSK 0xff + +#define R_AX_CH10_BDRAM_RWPTR 0x1340 +#define B_AX_CH10_BDRAM_WPTR_SH 8 +#define B_AX_CH10_BDRAM_WPTR_MSK 0xff +#define B_AX_CH10_BDRAM_RPTR_SH 0 +#define B_AX_CH10_BDRAM_RPTR_MSK 0xff + +#define R_AX_CH11_BDRAM_RWPTR 0x1342 +#define B_AX_CH11_BDRAM_WPTR_SH 8 +#define B_AX_CH11_BDRAM_WPTR_MSK 0xff +#define B_AX_CH11_BDRAM_RPTR_SH 0 +#define B_AX_CH11_BDRAM_RPTR_MSK 0xff + +#define R_AX_CH10_TXBD_NUM 0x1338 +#define B_AX_PCIE_CH10_FLAG BIT(14) +#define B_AX_CH10_DESC_NUM_SH 0 +#define B_AX_CH10_DESC_NUM_MSK 0xfff + +#define R_AX_CH11_TXBD_NUM 0x133A +#define B_AX_PCIE_CH11_FLAG BIT(14) +#define B_AX_CH11_DESC_NUM_SH 0 +#define B_AX_CH11_DESC_NUM_MSK 0xfff + +#define R_AX_CH10_TXBD_DESA_L 0x1358 +#define B_AX_CH10_TXBD_DESA_L_SH 0 +#define B_AX_CH10_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_CH10_TXBD_DESA_H 0x135C +#define B_AX_CH10_TXBD_DESA_H_SH 0 +#define B_AX_CH10_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_CH11_TXBD_DESA_L 0x1360 +#define B_AX_CH11_TXBD_DESA_L_SH 0 +#define B_AX_CH11_TXBD_DESA_L_MSK 0xffffffffL + +#define R_AX_CH11_TXBD_DESA_H 0x1364 +#define B_AX_CH11_TXBD_DESA_H_SH 0 +#define B_AX_CH11_TXBD_DESA_H_MSK 0xffffffffL + +#define R_AX_CH10_TXBD_IDX 0x137C +#define B_AX_CH10_HW_IDX_SH 16 +#define B_AX_CH10_HW_IDX_MSK 0xfff +#define B_AX_CH10_HOST_IDX_SH 0 +#define B_AX_CH10_HOST_IDX_MSK 0xfff + +#define R_AX_CH11_TXBD_IDX 0x1380 +#define B_AX_CH11_HW_IDX_SH 16 +#define B_AX_CH11_HW_IDX_MSK 0xfff +#define B_AX_CH11_HOST_IDX_SH 0 +#define B_AX_CH11_HOST_IDX_MSK 0xfff + +#define R_AX_PCIE_HIMR10 0x13B0 +#define B_AX_HC10ISR_IND_INT_EN BIT(28) +#define B_AX_TXDMA_CH11_INT_EN BIT(12) +#define B_AX_TXDMA_CH10_INT_EN BIT(11) + +#define R_AX_PCIE_HISR10 0x13B4 +#define B_AX_HC10ISR_IND_INT BIT(28) +#define B_AX_TXDMA_CH11_INT BIT(12) +#define B_AX_TXDMA_CH10_INT BIT(11) + +#define R_AX_PCIE_EXP_CTRL 0x13F0 +#define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) +#define B_AX_MAX_TAG_NUM_SH 16 +#define B_AX_MAX_TAG_NUM_MSK 0x7 +#define B_AX_RET_STICKY_RST_N_KEEP_REG_PERST BIT(14) +#define B_AX_RET_NON_STICKY_RST_N_KEEP_REG_PERST BIT(13) +#define B_AX_RET_NON_STICKY_RST_N_KEEP_REG_LINKRST BIT(12) +#define B_AX_EN_LAT_PHYSTATUS BIT(11) +#define B_AX_EN_OLD_WAKE_MODE BIT(10) +#define B_AX_EN_TIMEOUT_T_PCLKACK BIT(9) +#define B_AX_EN_DIS_IO_MEM_EN BIT(8) +#define B_AX_FORCE_REG_CLK_EN BIT(5) +#define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) +#define B_AX_DIS_L1_2_SUS BIT(3) +#define B_AX_IB_EN_FORCE BIT(2) +#define B_AX_PCIE_ACTIVE_FORCE BIT(1) + +#define R_AX_PCIE_RX_PREF_ADV 0x13F4 +#define B_AX_RXDMA_PREF_ADV_TH_SH 1 +#define B_AX_RXDMA_PREF_ADV_TH_MSK 0x3 +#define B_AX_RXDMA_PREF_ADV_EN BIT(0) + +#define R_AX_PCIE_IO_RCY_M1 0x3100 +#define B_AX_PCIE_IO_RCY_P_M1 BIT(5) +#define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4) +#define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3) +#define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0) + +#define R_AX_PCIE_WDT_TIMER_M1 0x3104 +#define B_AX_PCIE_WDT_TIMER_M1_SH 0 +#define B_AX_PCIE_WDT_TIMER_M1_MSK 0xffffffffL + +#define R_AX_PCIE_PADDR_M1 0x3108 +#define B_AX_PCIE_PADDR_M1_SH 0 +#define B_AX_PCIE_PADDR_M1_MSK 0xffffffffL + +#define R_AX_PCIE_IO_RCY_M2 0x310C +#define B_AX_PCIE_IO_RCY_P_M2 BIT(5) +#define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4) +#define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3) +#define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0) + +#define R_AX_PCIE_WDT_TIMER_M2 0x3110 +#define B_AX_PCIE_WDT_TIMER_M2_SH 0 +#define B_AX_PCIE_WDT_TIMER_M2_MSK 0xffffffffL + +#define R_AX_PCIE_PADDR_M2 0x3114 +#define B_AX_PCIE_PADDR_M2_SH 0 +#define B_AX_PCIE_PADDR_M2_MSK 0xffffffffL + +#define R_AX_PCIE_IO_RCY_E0 0x3118 +#define B_AX_PCIE_IO_RCY_P_E0 BIT(5) +#define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4) +#define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3) +#define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0) + +#define R_AX_PCIE_WDT_TIMER_E0 0x311C +#define B_AX_PCIE_WDT_TIMER_E0_SH 0 +#define B_AX_PCIE_WDT_TIMER_E0_MSK 0xffffffffL + +#define R_AX_PCIE_PADDR_E0 0x3120 +#define B_AX_PCIE_PADDR_E0_SH 0 +#define B_AX_PCIE_PADDR_E0_MSK 0xffffffffL + +#define R_AX_PCIE_IO_RCY_S1 0x3124 +#define B_AX_PCIE_IO_RCY_RP_S1 BIT(7) +#define B_AX_PCIE_IO_RCY_WP_S1 BIT(6) +#define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5) +#define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4) +#define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3) +#define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1) +#define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0) + +#define R_AX_PCIE_WDT_TIMER_S1 0x3128 +#define B_AX_PCIE_WDT_TIMER_S1_SH 0 +#define B_AX_PCIE_WDT_TIMER_S1_MSK 0xffffffffL + +#define R_AX_PCIE_PADDR_W_S1 0x312C +#define B_AX_PCIE_PADDR_W_S1_SH 0 +#define B_AX_PCIE_PADDR_W_S1_MSK 0xffffffffL + +#define R_AX_PCIE_PADDR_R_S1 0x3130 +#define B_AX_PCIE_PADDR_R_S1_SH 0 +#define B_AX_PCIE_PADDR_R_S1_MSK 0xffffffffL + +// +// WL_AX_Reg_Page_SDIO.xls +// + +// +// SDIO_Local_Reg_Spec +// + +#define R_AX_SDIO_TX_CTRL 0x1000 +#define B_AX_SDIO_INT_TIMEOUT_SH 16 +#define B_AX_SDIO_INT_TIMEOUT_MSK 0xffff +#define B_AX_IO_ERR_STATUS BIT(15) +#define B_AX_CMD53_W_MIX BIT(14) +#define B_AX_CMD53_TX_FORMAT BIT(13) +#define B_AX_CMD53_R_TIMEOUT_MASK BIT(12) +#define B_AX_CMD53_R_TIMEOUT_UNIT_SH 10 +#define B_AX_CMD53_R_TIMEOUT_UNIT_MSK 0x3 +#define B_AX_REPLY_ERRCRC_IN_DATA BIT(9) +#define B_AX_EN_CMD53_OVERLAP BIT(8) +#define B_AX_REPLY_ERR_IN_R5 BIT(7) +#define B_AX_R18A_EN BIT(6) +#define B_AX_SDIO_CMD_FORCE_VLD BIT(5) +#define B_AX_INIT_CMD_EN BIT(4) +#define B_AX_RXINT_READ_MASK_DIS BIT(3) +#define B_AX_EN_RXDMA_MASK_INT BIT(2) +#define B_AX_EN_MASK_TIMER BIT(1) +#define B_AX_CMD_ERR_STOP_INT_EN BIT(0) + +#define R_AX_SDIO_CTRL 0x1004 +#define B_AX_SDIO_DRV_TYPE_D_SH 28 +#define B_AX_SDIO_DRV_TYPE_D_MSK 0xf +#define B_AX_SDIO_DRV_TYPE_C_SH 24 +#define B_AX_SDIO_DRV_TYPE_C_MSK 0xf +#define B_AX_SDIO_DRV_TYPE_B_SH 20 +#define B_AX_SDIO_DRV_TYPE_B_MSK 0xf +#define B_AX_SDIO_DRV_TYPE_A_SH 16 +#define B_AX_SDIO_DRV_TYPE_A_MSK 0xf +#define B_AX_SIG_OUT_PH BIT(8) +#define B_AX_CMD11_SEQ_END_DELAY_SH 4 +#define B_AX_CMD11_SEQ_END_DELAY_MSK 0xf +#define B_AX_CMD11_SEQ_SAMPLE_INTERVAL_SH 1 +#define B_AX_CMD11_SEQ_SAMPLE_INTERVAL_MSK 0x7 +#define B_AX_CMD11_SEQ_EN BIT(0) + +#define R_AX_SDIO_MONITOR 0x1008 +#define B_AX_SDIO_INT_START_SH 0 +#define B_AX_SDIO_INT_START_MSK 0xffffffffL + +#define R_AX_SDIO_MONITOR_2 0x100C +#define B_AX_CMD53_WT_EN BIT(23) +#define B_AX_SDIO_CLK_MONITOR_SH 21 +#define B_AX_SDIO_CLK_MONITOR_MSK 0x3 +#define B_AX_SDIO_CLK_CNT_SH 0 +#define B_AX_SDIO_CLK_CNT_MSK 0x1fffff + +#define R_AX_SDIO_CTRL_2 0x1010 +#define B_AX_SDIO_CLK_SMT BIT(1) +#define B_AX_SDIO_DATA_SMT BIT(0) + +#define R_AX_SDIO_MONITOR_3 0x1014 +#define B_AX_SDIO_USER_DEF_SH 0 +#define B_AX_SDIO_USER_DEF_MSK 0xffffffffL + +#define R_AX_SDIO_HTSFR_INFO 0x1030 +#define B_AX_HTSFR0_SH 0 +#define B_AX_HTSFR0_MSK 0xffff + +#define R_AX_SDIO_INDIRECT_ADDR 0x1040 +#define B_AX_INDIRECT_RDY BIT(31) +#define B_AX_INDIRECT_ADDR_SH 0 +#define B_AX_INDIRECT_ADDR_MSK 0x7fffffffL + +#define R_AX_SDIO_INDIRECT_DATA 0x1044 +#define B_AX_INDIRECT_DATA_SH 0 +#define B_AX_INDIRECT_DATA_MSK 0xffffffffL + +#define R_AX_SDIO_INDIRECT_CTRL 0x1048 +#define B_AX_INDIRECT_REG_R BIT(3) +#define B_AX_INDIRECT_REG_W BIT(2) +#define B_AX_INDIRECT_REG_SIZE_SH 0 +#define B_AX_INDIRECT_REG_SIZE_MSK 0x3 + +#define R_AX_SDIO_HRPWM1 0x1080 +#define B_AX_HRPWM_SH 16 +#define B_AX_HRPWM_MSK 0xffff + +#define R_AX_SDIO_BUS_CTRL 0x1084 +#define B_AX_SPI_PHASE BIT(21) +#define B_AX_INTR_CTRL BIT(20) +#define B_AX_SDIO_VOLTAGE BIT(19) +#define B_AX_BYPASS_INIT BIT(18) +#define B_AX_HCI_RESUME_RDY BIT(17) +#define B_AX_HCI_SUS_REQ BIT(16) +#define B_AX_CMD53_RDATA_EARLY BIT(14) +#define B_AX_HISR_W_CLR_EN BIT(13) +#define B_AX_INT_MASK_DIS BIT(12) +#define B_AX_PAD_CLK_XHGE_EN BIT(11) +#define B_AX_INTER_CLK_EN BIT(10) +#define B_AX_EN_RPT_TXCRC BIT(9) +#define B_AX_DIS_RXDMA_STS BIT(8) + +#define R_AX_SDIO_RESPONSE_TIMER 0x1088 +#define B_AX_SDIO_CMD_CRC_SH 16 +#define B_AX_SDIO_CMD_CRC_MSK 0xff +#define B_AX_CMDIN_2RESP_TIMER_SH 0 +#define B_AX_CMDIN_2RESP_TIMER_MSK 0xffff + +#define R_AX_SDIO_HSISR 0x1090 +#define B_AX_HISR_MASK BIT(8) +#define B_AX_DRV_WLAN_INT_CLR BIT(1) +#define B_AX_DRV_WLAN_INT BIT(0) + +#define R_AX_SDIO_EXTEND_RBLOK_GAP 0x1094 +#define B_AX_EXTEND_RBLOCK_GAP_SH 0 +#define B_AX_EXTEND_RBLOCK_GAP_MSK 0x3f + +#define R_AX_SDIO_DIOERR_RPT 0x10C0 +#define B_AX_DATA_CRC_ERR_CNT_SH 24 +#define B_AX_DATA_CRC_ERR_CNT_MSK 0xff +#define B_AX_CMD_CRC_ERR_CNT_SH 16 +#define B_AX_CMD_CRC_ERR_CNT_MSK 0xff +#define B_AX_SDIO_PAGE_ERR BIT(0) + +#define R_AX_SDIO_CMD_ERR_CONTENT_L 0x10C4 +#define B_AX_SDIO_CMD_ERR_CONTENT_L_SH 0 +#define B_AX_SDIO_CMD_ERR_CONTENT_L_MSK 0xffffffffL + +#define R_AX_SDIO_CMD_ERR_CONTENT 0x10C8 +#define B_AX_SDIO_DATA_CRC_SH 16 +#define B_AX_SDIO_DATA_CRC_MSK 0xffff +#define B_AX_FN1_WDATA_TO_FLG BIT(15) +#define B_AX_FN1_WDATA_LEN_SHORT_FLG BIT(14) +#define B_AX_D3_CRC_ERR BIT(12) +#define B_AX_D2_CRC_ERR BIT(11) +#define B_AX_D1_CRC_ERR BIT(10) +#define B_AX_D0_CRC_ERR BIT(9) +#define B_AX_CMD_CRC_ERR BIT(8) +#define B_AX_SDIO_CMD_ERR_CONTENT_H_SH 0 +#define B_AX_SDIO_CMD_ERR_CONTENT_H_MSK 0xff + +//#define R_AX_SDIO_TRANS_FIFO_STATUS 0x10CC +//#define B_AX_TRANS_FIFO_UNDERFLOW BIT(1) +//#define B_AX_TRANS_FIFO_OVERFLOW BIT(0) +#define R_AX_SDIO_TXDMA_FIFO_STATUS 0x10CC +#define B_AX_TXDMA_FIFO_UNDERFLOW BIT(4) +#define B_AX_TXDMA_FIFO_OVERFLOW BIT(3) + +#define R_AX_SDIO_HIMR 0x1100 +#define B_AX_SDIO_BT_INT_EN BIT(24) +#define B_AX_SDIO_HS0ISR_IND_EN BIT(16) +#define B_AX_SDIO_HC10ISR_IND_EN BIT(9) +#define B_AX_SDIO_HC00ISR_IND_EN BIT(8) +#define B_AX_SDIO_HD1ISR_IND_EN BIT(3) +#define B_AX_SDIO_HD0ISR_IND_EN BIT(2) +#define B_AX_SDIO_AVAL_INT_EN BIT(1) +#define B_AX_RX_REQUEST_INT_EN BIT(0) + +#define R_AX_SDIO_HISR 0x1104 +#define B_AX_SDIO_BT_INT BIT(24) +#define B_AX_SDIO_HS0ISR_IND BIT(16) +#define B_AX_SDIO_HC10ISR_IND BIT(9) +#define B_AX_SDIO_HC00ISR_IND BIT(8) +#define B_AX_SDIO_HD1ISR_IND BIT(3) +#define B_AX_SDIO_HD0ISR_IND BIT(2) +#define B_AX_SDIO_AVAL_INT BIT(1) +#define B_AX_RX_REQUEST_INT BIT(0) + +#define R_AX_SDIO_RX_REQ_LEN 0x1108 +#define B_AX_RX_REQ_LEN_SH 0 +#define B_AX_RX_REQ_LEN_MSK 0x3ffff + +#define R_AX_SDIO_AVAL_INTRPT_STAT 0x110C +#define B_AX_SDIO_ACH11_INTRPT_STAT BIT(11) +#define B_AX_SDIO_ACH10_INTRPT_STAT BIT(10) +#define B_AX_SDIO_ACH9_INTRPT_STAT BIT(9) +#define B_AX_SDIO_ACH8_INTRPT_STAT BIT(8) +#define B_AX_SDIO_ACH7_INTRPT_STAT BIT(7) +#define B_AX_SDIO_ACH6_INTRPT_STAT BIT(6) +#define B_AX_SDIO_ACH5_INTRPT_STAT BIT(5) +#define B_AX_SDIO_ACH4_INTRPT_STAT BIT(4) +#define B_AX_SDIO_ACH3_INTRPT_STAT BIT(3) +#define B_AX_SDIO_ACH2_INTRPT_STAT BIT(2) +#define B_AX_SDIO_ACH1_INTRPT_STAT BIT(1) +#define B_AX_SDIO_ACH0_INTRPT_STAT BIT(0) + +#define R_AX_SDIO_TXPG_WP 0x1110 +#define B_AX_SDIO_ACH12_AVAL_PG_SH 16 +#define B_AX_SDIO_ACH12_AVAL_PG_MSK 0x1fff +#define B_AX_SDIO_WP_AVAL_PG_SH 0 +#define B_AX_SDIO_WP_AVAL_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_0 0x1114 +#define B_AX_SDIO_ACH1_USE_PG_SH 16 +#define B_AX_SDIO_ACH1_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH0_USE_PG_SH 0 +#define B_AX_SDIO_ACH0_USE_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_1 0x1118 +#define B_AX_SDIO_ACH3_USE_PG_SH 16 +#define B_AX_SDIO_ACH3_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH2_USE_PG_SH 0 +#define B_AX_SDIO_ACH2_USE_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_2 0x111C +#define B_AX_SDIO_ACH5_USE_PG_SH 16 +#define B_AX_SDIO_ACH5_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH4_USE_PG_SH 0 +#define B_AX_SDIO_ACH4_USE_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_3 0x1120 +#define B_AX_SDIO_ACH7_USE_PG_SH 16 +#define B_AX_SDIO_ACH7_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH6_USE_PG_SH 0 +#define B_AX_SDIO_ACH6_USE_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_4 0x1124 +#define B_AX_SDIO_ACH9_USE_PG_SH 16 +#define B_AX_SDIO_ACH9_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH8_USE_PG_SH 0 +#define B_AX_SDIO_ACH8_USE_PG_MSK 0x1fff + +#define R_AX_SDIO_TXPG_5 0x1128 +#define B_AX_SDIO_ACH11_USE_PG_SH 16 +#define B_AX_SDIO_ACH11_USE_PG_MSK 0x1fff +#define B_AX_SDIO_ACH10_USE_PG_SH 0 +#define B_AX_SDIO_ACH10_USE_PG_MSK 0x1fff + +// +// WL_AX_Reg_RXI300.xls +// + +// +// RXI300 +// + +#define R_AX_RXI300_NAME 0x0000 +#define B_AX_RXI300_NAME_SH 0 +#define B_AX_RXI300_NAME_MSK 0xffffffffL + +#define R_AX_RXI300_VER 0x0004 +#define B_AX_RXI300_VER_SH 0 +#define B_AX_RXI300_VER_MSK 0xffffffffL + +#define R_AX_RXI300_REV 0x0008 +#define B_AX_RXI300_REV_SH 0 +#define B_AX_RXI300_REV_MSK 0xffffffffL + +#define R_AX_RXI300_INST 0x000C +#define B_AX_RXI300_INST_SH 0 +#define B_AX_RXI300_INST_MSK 0xffffffffL + +#define R_AX_RXI300_IMPL_Y 0x0010 +#define B_AX_RXI300_IMPL_Y_SH 0 +#define B_AX_RXI300_IMPL_Y_MSK 0xffffffffL + +#define R_AX_RXI300_IMPL_D 0x0014 +#define B_AX_RXI300_IMPL_D_SH 0 +#define B_AX_RXI300_IMPL_D_MSK 0xffffffffL + +#define R_AX_RXI300_DEV 0x0018 +#define B_AX_RXI300_DEV_SH 0 +#define B_AX_RXI300_DEV_MSK 0xffffffffL + +#define R_AX_RXI300_PRO_NUM 0x001C +#define B_AX_RXI300_PRO_NUM_SH 0 +#define B_AX_RXI300_PRO_NUM_MSK 0xffffffffL + +#define R_AX_RXI300_ELR_0_PLD0 0x0200 +#define B_AX_ERR_BSTINDEX_SH 24 +#define B_AX_ERR_BSTINDEX_MSK 0xff +#define B_AX_ERR_BSTLEN_SH 16 +#define B_AX_ERR_BSTLEN_MSK 0xff +#define B_AX_ERR_BSTTYPE_SH 11 +#define B_AX_ERR_BSTTYPE_MSK 0x7 +#define B_AX_ERR_CMD_SH 8 +#define B_AX_ERR_CMD_MSK 0x7 +#define B_AX_ERR_SRC_SH 0 +#define B_AX_ERR_SRC_MSK 0xff + +#define R_AX_RXI300_ELR_0_PLD1 0x0204 +#define B_AX_ERR_MREQINFO_SH 23 +#define B_AX_ERR_MREQINFO_MSK 0x1ff +#define B_AX_ERR_SIZE_SH 16 +#define B_AX_ERR_SIZE_MSK 0x7 +#define B_AX_ERR_BYTEEN_SH 0 +#define B_AX_ERR_BYTEEN_MSK 0xffff + +#define R_AX_RXI300_ELR_0_ID 0x0208 +#define B_AX_ERR_ID_SH 0 +#define B_AX_ERR_ID_MSK 0xffffffffL + +#define R_AX_RXI300_ELR_0_ADR0 0x020C +#define B_AX_ERR_ADR0_SH 0 +#define B_AX_ERR_ADR0_MSK 0xffffffffL + +#define R_AX_RXI300_ELR_0_ADR1 0x0210 +#define B_AX_ERR_ADR1_SH 0 +#define B_AX_ERR_ADR1_MSK 0xffffffffL + +#define R_AX_RXI300_ELR_0_CODE 0x0230 +#define B_AX_ELR_CODE_SH 0 +#define B_AX_ELR_CODE_MSK 0xff + +#define R_AX_RXI300_ELR_0_INTR_CLR 0x023C +#define B_AX_ELR_INTR_CLR BIT(0) + +#define R_AX_RXI300_ICG_CTRL0 0x0300 +#define B_AX_RXI300_ICG_CTRL0_SH 0 +#define B_AX_RXI300_ICG_CTRL0_MSK 0xffffffffL + +#define R_AX_RXI300_ICG_CTRL1 0x0304 +#define B_AX_RXI300_ICG_CTRL1_SH 0 +#define B_AX_RXI300_ICG_CTRL1_MSK 0xffffffffL + +#define R_AX_RXI300_TIME_MON 0x0308 +#define B_AX_RXI300_TM_AXI_APB_BBRF_RST BIT(26) +#define B_AX_RXI300_TM_AXI_APB_SA_RST BIT(25) +#define B_AX_RXI300_TM_AXI2AHB_RST BIT(24) +#define B_AX_RXI300_TM_AXI_APB_BBRF_EN BIT(18) +#define B_AX_RXI300_TM_AXI_APB_SA_EN BIT(17) +#define B_AX_RXI300_TM_AXI2AHB_EN BIT(16) +#define B_AX_RXI300_TM_GRADE_SH 8 +#define B_AX_RXI300_TM_GRADE_MSK 0xf +#define B_AX_RXI300_TM_TRSH_SH 0 +#define B_AX_RXI300_TM_TRSH_MSK 0xff + +#define R_AX_RXI300_ICG_STAT0 0x0320 +#define B_AX_RXI300_ICG_STAT0_SH 0 +#define B_AX_RXI300_ICG_STAT0_MSK 0xffffffffL + +#define R_AX_RXI300_ICG_STAT1 0x0324 +#define B_AX_RXI300_ICG_STAT1_SH 0 +#define B_AX_RXI300_ICG_STAT1_MSK 0xffffffffL + +// +// WL_AX_Reg_SPIC.xls +// + +// +// SPIC +// + +#define R_AX_SPIC_CTRLR0 0x0000 +#define B_AX_PRM_2ND_PHASE BIT(31) +#define B_AX_DDR_EN_SH 28 +#define B_AX_DDR_EN_MSK 0x7 +#define B_AX_CK_MTIMES_SH 23 +#define B_AX_CK_MTIMES_MSK 0x1f +#define B_AX_FAST_RD BIT(22) +#define B_AX_CMD_CH_SH 20 +#define B_AX_CMD_CH_MSK 0x3 +#define B_AX_DATA_CH_SH 18 +#define B_AX_DATA_CH_MSK 0x3 +#define B_AX_ADDR_CH_SH 16 +#define B_AX_ADDR_CH_MSK 0x3 +#define B_AX_TMOD_SH 8 +#define B_AX_TMOD_MSK 0x3 +#define B_AX_SCPOL BIT(7) +#define B_AX_SCPH BIT(6) + +#define R_AX_SPIC_CTRLR1 0x0004 +#define B_AX_NDF_SH 0 +#define B_AX_NDF_MSK 0xffff + +#define R_AX_SPIC_SSIENR 0x0008 +#define B_AX_PGM_RST_TEST_EN BIT(4) +#define B_AX_ATCK_CMD BIT(1) +#define B_AX_SPIC_FUNC_EN BIT(0) + +#define R_AX_SPIC_SER 0x0010 +#define B_AX_SER_SH 0 +#define B_AX_SER_MSK 0xffffffffL + +#define R_AX_SPIC_BAUDR 0x0014 +#define B_AX_SCKDV_SH 0 +#define B_AX_SCKDV_MSK 0xfff + +#define R_AX_SPIC_TXFTLR 0x0018 +#define B_AX_TFT_SH 0 +#define B_AX_TFT_MSK 0xffffffffL + +#define R_AX_SPIC_RXFTLR 0x001C +#define B_AX_RFT_SH 0 +#define B_AX_RFT_MSK 0xffffffffL + +#define R_AX_SPIC_TXFLR 0x0020 +#define B_AX_TXFLR_SH 0 +#define B_AX_TXFLR_MSK 0xffffffffL + +#define R_AX_SPIC_RXFLR 0x0024 +#define B_AX_RXFLR_SH 0 +#define B_AX_RXFLR_MSK 0xffffffffL + +#define R_AX_SPIC_SR 0x0028 +#define B_AX_BOOT_FIN BIT(7) +#define B_AX_DCOL BIT(6) +#define B_AX_TXE BIT(5) +#define B_AX_RFF BIT(4) +#define B_AX_RFNE BIT(3) +#define B_AX_TFE BIT(2) +#define B_AX_TFNF BIT(1) +#define B_AX_BUSY BIT(0) + +#define R_AX_SPIC_IMR 0x002C +#define B_AX_ACSIM BIT(11) +#define B_AX_RXSIM BIT(10) +#define B_AX_TXSIM BIT(9) +#define B_AX_ACEIM BIT(8) +#define B_AX_BYEIM BIT(7) +#define B_AX_WBEIM BIT(6) +#define B_AX_FSEIM BIT(5) +#define B_AX_RXFIM BIT(4) +#define B_AX_RXOIM BIT(3) +#define B_AX_RXUIM BIT(2) +#define B_AX_TXOIM BIT(1) +#define B_AX_TXEIM BIT(0) + +#define R_AX_SPIC_ISR 0x0030 +#define B_AX_ACSIS BIT(11) +#define B_AX_RXSIS BIT(10) +#define B_AX_TXSIS BIT(9) +#define B_AX_ACEIS BIT(8) +#define B_AX_BYEIS BIT(7) +#define B_AX_WBEIS BIT(6) +#define B_AX_FSEIS BIT(5) +#define B_AX_RXFIS BIT(4) +#define B_AX_RXOIS BIT(3) +#define B_AX_RXUIS BIT(2) +#define B_AX_TXOIS BIT(1) +#define B_AX_TXEIS BIT(0) + +#define R_AX_SPIC_RISR 0x0034 +#define B_AX_ACSIR BIT(11) +#define B_AX_RXSIR BIT(10) +#define B_AX_TXSIR BIT(9) +#define B_AX_ACEIR BIT(8) +#define B_AX_BYEIR BIT(7) +#define B_AX_WBEIR BIT(6) +#define B_AX_FSEIR BIT(5) +#define B_AX_RXFIR BIT(4) +#define B_AX_RXOIR BIT(3) +#define B_AX_RXUIR BIT(2) +#define B_AX_TXOIR BIT(1) +#define B_AX_TXEIR BIT(0) + +#define R_AX_SPIC_TXOICR 0x0038 +#define B_AX_TXOICR BIT(0) + +#define R_AX_SPIC_RXOICR 0x003C +#define B_AX_RXOICR BIT(0) + +#define R_AX_SPIC_RXUICR 0x0040 +#define B_AX_RXUICR BIT(0) + +#define R_AX_SPIC_MSTICR 0x0044 +#define B_AX_MSTICR BIT(0) + +#define R_AX_SPIC_ICR 0x0048 +#define B_AX_ICR BIT(0) + +#define R_AX_SPIC_DMACR 0x004C +#define B_AX_TX_DMAC_EN BIT(1) +#define B_AX_RX_DMAC_EN BIT(0) + +#define R_AX_SPIC_DMATDLR 0x0050 +#define B_AX_DMATDL_SH 0 +#define B_AX_DMATDL_MSK 0xffffffffL + +#define R_AX_SPIC_DMARDLR 0x0054 +#define B_AX_DMARDL_SH 0 +#define B_AX_DMARDL_MSK 0xffffffffL + +#define R_AX_SPIC_IDR 0x0058 +#define B_AX_IDCODE_SH 0 +#define B_AX_IDCODE_MSK 0xffffffffL + +#define R_AX_SPIC_VERSION 0x005C +#define B_AX_SPIC_VERSION_SH 0 +#define B_AX_SPIC_VERSION_MSK 0xffffffffL + +#define R_AX_SPIC_DR_WORD 0x0060 +#define B_AX_DR_WORD_SH 0 +#define B_AX_DR_WORD_MSK 0xffffffffL + +#define R_AX_SPIC_DR_HALF_WORD 0x0060 +#define B_AX_DR_HALF_WORD_SH 0 +#define B_AX_DR_HALF_WORD_MSK 0xffff + +#define R_AX_SPIC_DR_BYTE 0x0060 +#define B_AX_DR_BYTE_SH 0 +#define B_AX_DR_BYTE_MSK 0xff + +#define R_AX_SPIC_READ_FAST_SINGLE 0x00E0 +#define B_AX_FRD_CMD_SH 0 +#define B_AX_FRD_CMD_MSK 0xffff + +#define R_AX_SPIC_READ_DUAL_DATA 0x00E4 +#define B_AX_RD_DUAL_O_CMD_SH 0 +#define B_AX_RD_DUAL_O_CMD_MSK 0xff + +#define R_AX_SPIC_READ_DUAL_ADDR_DATA 0x00E8 +#define B_AX_RD_DUAL_IO_CMD_SH 0 +#define B_AX_RD_DUAL_IO_CMD_MSK 0xff + +#define R_AX_SPIC_READ_QUAD_DATA 0x00EC +#define B_AX_RD_QUAD_O_CMD_SH 0 +#define B_AX_RD_QUAD_O_CMD_MSK 0xff + +#define R_AX_SPIC_READ_QUAD_ADDR_DATA 0x00F0 +#define B_AX_SPIC_PRM_VALUE_SH 16 +#define B_AX_SPIC_PRM_VALUE_MSK 0xff +#define B_AX_RD_QUAD_IO_CMD_SH 0 +#define B_AX_RD_QUAD_IO_CMD_MSK 0xff + +#define R_AX_SPIC_WRITE_SINGLE 0x00F4 +#define B_AX_WR_CMD_SH 0 +#define B_AX_WR_CMD_MSK 0xffff + +#define R_AX_SPIC_WRITE_DUAL_DATA 0x00F8 +#define B_AX_WR_DUAL_I_CMD_SH 0 +#define B_AX_WR_DUAL_I_CMD_MSK 0xff + +#define R_AX_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC +#define B_AX_SPIC_WR_DUAL_II_CMD_SH 0 +#define B_AX_SPIC_WR_DUAL_II_CMD_MSK 0xff + +#define R_AX_SPIC_WRITE_QUAD_DATA 0x0100 +#define B_AX_WR_QUAD_I_CMD_SH 0 +#define B_AX_WR_QUAD_I_CMD_MSK 0xff + +#define R_AX_SPIC_WRITE_QUAD_ADDR_DATA 0x0104 +#define B_AX_WR_QUAD_II_CMD_SH 0 +#define B_AX_WR_QUAD_II_CMD_MSK 0xff + +#define R_AX_SPIC_WRITE_ENABLE 0x0108 +#define B_AX_WR_EN_CMD_SH 0 +#define B_AX_WR_EN_CMD_MSK 0xffff + +#define R_AX_SPIC_READ_STATUS 0x010C +#define B_AX_ADDR_EN BIT(31) +#define B_AX_ADDR_LEN_SH 29 +#define B_AX_ADDR_LEN_MSK 0x3 +#define B_AX_ADDR_SEL BIT(28) +#define B_AX_INTERVAL_EN BIT(27) +#define B_AX_RD_ST_CMD_SH 0 +#define B_AX_RD_ST_CMD_MSK 0xffff + +#define R_AX_SPIC_CTRLR2 0x0110 +#define B_AX_CS_ACTIVE_HOLD_SH 12 +#define B_AX_CS_ACTIVE_HOLD_MSK 0x3 +#define B_AX_RX_FIFO_ENTRY_SH 8 +#define B_AX_RX_FIFO_ENTRY_MSK 0xf +#define B_AX_FIFO_ENTRY_SH 4 +#define B_AX_FIFO_ENTRY_MSK 0xf +#define B_AX_SEQ_EN BIT(3) +#define B_AX_WPN_DNUM BIT(2) +#define B_AX_WPN_SET BIT(1) +#define B_AX_SO_DNUM BIT(0) + +#define R_AX_SPIC_FBAUDR 0x0114 +#define B_AX_FSCKDV_SH 0 +#define B_AX_FSCKDV_MSK 0xfff + +#define R_AX_SPIC_ADDR_LENGTH 0x0118 +#define B_AX_ADDR_PHASE_LENGTH_SH 0 +#define B_AX_ADDR_PHASE_LENGTH_MSK 0x7 + +#define R_AX_SPIC_AUTO_LENGTH 0x011C +#define B_AX_ADDR_CS_H_WR_DUM_LEN_SH 28 +#define B_AX_ADDR_CS_H_WR_DUM_LEN_MSK 0xf +#define B_AX_ADDR_CS_H_RD_DUM_LEN_SH 26 +#define B_AX_ADDR_CS_H_RD_DUM_LEN_MSK 0x3 +#define B_AX_ADDR_AUTO_DUM_LEN_SH 18 +#define B_AX_ADDR_AUTO_DUM_LEN_MSK 0xff +#define B_AX_ADDR_AUTO_ADDR_LENGTH_SH 16 +#define B_AX_ADDR_AUTO_ADDR_LENGTH_MSK 0x3 +#define B_AX_ADDR_IN_PHYSICAL_CYC_SH 12 +#define B_AX_ADDR_IN_PHYSICAL_CYC_MSK 0xf + +#define R_AX_SPIC_VALID_CMD 0x0120 +#define B_AX_ADDR_SEQ_TRANS_EN BIT(14) +#define B_AX_ADDR_CTRLR0_CH BIT(12) +#define B_AX_ADDR_PRM_EN BIT(11) +#define B_AX_ADDR_WR_BLOCKING BIT(9) +#define B_AX_ADDR_WR_QUAD_II BIT(8) +#define B_AX_ADDR_WR_QUAD_I BIT(7) +#define B_AX_ADDR_WR_DUAL_II BIT(6) +#define B_AX_ADDR_WR_DUAL_I BIT(5) +#define B_AX_ADDR_RD_QUAD_IO BIT(4) +#define B_AX_ADDR_RD_QUAD_O BIT(3) +#define B_AX_ADDR_RD_DUAL_IO BIT(2) +#define B_AX_ADDR_RD_DUAL_I BIT(1) +#define B_AX_ADDR_FRD_SINGEL BIT(0) + +#define R_AX_SPIC_FLASH_SIZE 0x0124 +#define B_AX_FLASH_SIZE_SH 0 +#define B_AX_FLASH_SIZE_MSK 0xfff + +#define R_AX_SPIC_FLUSH_FIFO 0x0128 +#define B_AX_FLUSH_PGM_RST_FIFO BIT(1) +#define B_AX_FLUSH_FIFO BIT(0) + +#define R_AX_SPIC_PGM_RST_FIFO 0x0140 +#define B_AX_PGM_RST_FIFO_SH 0 +#define B_AX_PGM_RST_FIFO_MSK 0xffff + +// +// WL_AX_Reg_UART.xls +// + +// +// UART +// + +#define R_AX_UART_RBR 0x0000 +#define B_AX_RBR_SH 0 +#define B_AX_RBR_MSK 0xff + +#define R_AX_UART_THR 0x0000 +#define B_AX_THR_SH 0 +#define B_AX_THR_MSK 0xff + +#define R_AX_UART_DLH 0x0004 +#define B_AX_DLH_SH 0 +#define B_AX_DLH_MSK 0xff + +#define R_AX_UART_DLL 0x0000 +#define B_AX_DLL_SH 0 +#define B_AX_DLL_MSK 0xff + +#define R_AX_UART_IER 0x0004 +#define B_AX_IER_PTIME BIT(7) +#define B_AX_IER_EDSSI BIT(3) +#define B_AX_IER_ELSI BIT(2) +#define B_AX_IER_ETBEI BIT(1) +#define B_AX_IER_ERBFI BIT(0) + +#define R_AX_UART_IIR 0x0008 +#define B_AX_FIFOSE_SH 6 +#define B_AX_FIFOSE_MSK 0x3 +#define B_AX_IID_SH 0 +#define B_AX_IID_MSK 0xf + +#define R_AX_UART_FCR 0x0008 +#define B_AX_RT_SH 6 +#define B_AX_RT_MSK 0x3 +#define B_AX_TET_SH 4 +#define B_AX_TET_MSK 0x3 +#define B_AX_DMAM BIT(3) +#define B_AX_XFIFOR BIT(2) +#define B_AX_RFIFOR BIT(1) +#define B_AX_FIFOE BIT(0) + +#define R_AX_UART_LCR 0x000C +#define B_AX_DLAB BIT(7) +#define B_AX_BC BIT(6) +#define B_AX_EPS BIT(4) +#define B_AX_PEN BIT(3) +#define B_AX_STOP BIT(2) +#define B_AX_DLS_SH 0 +#define B_AX_DLS_MSK 0x3 + +#define R_AX_UART_MCR 0x0010 +#define B_AX_SIRE BIT(6) +#define B_AX_AFCE BIT(5) +#define B_AX_LB BIT(4) +#define B_AX_OUT2 BIT(3) +#define B_AX_OUT1 BIT(2) +#define B_AX_RTS BIT(1) +#define B_AX_DTR BIT(0) + +#define R_AX_UART_LSR 0x0014 +#define B_AX_RFE BIT(7) +#define B_AX_TEMT BIT(6) +#define B_AX_THRE BIT(5) +#define B_AX_BI BIT(4) +#define B_AX_FE BIT(3) +#define B_AX_PE BIT(2) +#define B_AX_OE BIT(1) +#define B_AX_DR BIT(0) + +#define R_AX_UART_MSR 0x0018 +#define B_AX_DCD BIT(7) +#define B_AX_RI BIT(6) +#define B_AX_DSR BIT(5) +#define B_AX_CTS BIT(4) +#define B_AX_DDCD BIT(3) +#define B_AX_TERI BIT(2) +#define B_AX_DDSR BIT(1) +#define B_AX_DCTS BIT(0) + +#define R_AX_UART_SCR 0x001C +#define B_AX_SCR_SH 0 +#define B_AX_SCR_MSK 0xff + +#define R_AX_UART_LPDLL 0x001C +#define B_AX_LPDLL_SH 0 +#define B_AX_LPDLL_MSK 0xff + +#define R_AX_UART_LPDLH 0x001C +#define B_AX_LPDLH_SH 0 +#define B_AX_LPDLH_MSK 0xff + +#define R_AX_UART_FAR 0x0070 +#define B_AX_FAR BIT(0) + +#define R_AX_UART_TFR 0x0074 +#define B_AX_TFR_SH 0 +#define B_AX_TFR_MSK 0xff + +#define R_AX_UART_RFW 0x0078 +#define B_AX_RFFE BIT(9) +#define B_AX_RFPE BIT(8) +#define B_AX_RFWD_SH 0 +#define B_AX_RFWD_MSK 0xff + +#define R_AX_UART_USR 0x007C +#define B_AX_RFF BIT(4) +#define B_AX_RFNE BIT(3) +#define B_AX_TFE BIT(2) +#define B_AX_TFNF BIT(1) +#define B_AX_BUSY BIT(0) + +#define R_AX_UART_TFL 0x0080 +#define B_AX_TFL_SH 0 +#define B_AX_TFL_MSK 0xffffffffL + +#define R_AX_UART_RFL 0x0084 +#define B_AX_RFL_SH 0 +#define B_AX_RFL_MSK 0xffffffffL + +#define R_AX_UART_SRR 0x0088 +#define B_AX_XFR BIT(2) +#define B_AX_RFR BIT(1) +#define B_AX_UR BIT(0) + +#define R_AX_UART_HTX 0x00A4 +#define B_AX_HTX BIT(0) + +#define R_AX_UART_DMASA 0x00A8 +#define B_AX_DMASA BIT(0) + +#define R_AX_UART_CPR 0x00F4 +#define B_AX_FIFO_MODE_SH 16 +#define B_AX_FIFO_MODE_MSK 0xff +#define B_AX_DMA_EXTRA BIT(13) +#define B_AX_UART_ADD_ENCODED_PARAMS BIT(12) +#define B_AX_SHADOW BIT(11) +#define B_AX_FIFO_STAT BIT(10) +#define B_AX_FIFO_ACCESS BIT(9) +#define B_AX_ADDITIONAL_FEAT BIT(8) +#define B_AX_SIR_LP_MODE BIT(7) +#define B_AX_SIR_MODE BIT(6) +#define B_AX_THRE_MODE BIT(5) +#define B_AX_AFCE_MODE BIT(4) +#define B_AX_APB_DATA_WIDTH_SH 0 +#define B_AX_APB_DATA_WIDTH_MSK 0x3 + +#define R_AX_UART_UCV 0x00F8 +#define B_AX_UCV_SH 0 +#define B_AX_UCV_MSK 0xffffffffL + +#define R_AX_UART_CTR 0x00FC +#define B_AX_PID_SH 0 +#define B_AX_PID_MSK 0xffffffffL + +// +// WL_AX_Reg_USB.xlsx +// + +// +// USB_REG +// + +#define R_AX_USB2_MAC_0 0x1000 +#define B_AX_TOUT_DELAY_FS_SH 24 +#define B_AX_TOUT_DELAY_FS_MSK 0xff +#define B_AX_TOUT_DELAY_HS_SH 16 +#define B_AX_TOUT_DELAY_HS_MSK 0xff +#define B_AX_TOUT_DIS BIT(15) +#define B_AX_CRC_CHK_OPT BIT(14) +#define B_AX_FORCE_PCERST BIT(13) +#define B_AX_FORCE_TOGL BIT(12) +#define B_AX_FORCE_TOGLSEL BIT(11) +#define B_AX_FORCE_PIDSW BIT(10) +#define B_AX_FORCE_PCE_IN BIT(9) +#define B_AX_FORCE_PCE_OUT BIT(8) +#define B_AX_PID_FORCE_SH 0 +#define B_AX_PID_FORCE_MSK 0xff + +#define R_AX_USB2_MAC_1 0x1004 +#define B_AX_FORCE_PCE_CMD BIT(31) + +#define R_AX_USB2_LINK_PORT 0x1008 +#define B_AX_R_HOST_PWR_CTRL BIT(23) +#define B_AX_R_USB2_CLR_TXVLD BIT(22) +#define B_AX_R_USB2_SE0 BIT(21) +#define B_AX_HOST_RESUME_EDGE_EN BIT(20) +#define B_AX_RESUME_SEL_SH 16 +#define B_AX_RESUME_SEL_MSK 0xf +#define B_AX_DELAY_CHIRP_K_SH 14 +#define B_AX_DELAY_CHIRP_K_MSK 0x3 +#define B_AX_FORCE_TXVLD1 BIT(13) +#define B_AX_FORCE_TXVLD0 BIT(12) +#define B_AX_DORCE_DAT1 BIT(11) +#define B_AX_FORCE_DAT0 BIT(10) +#define B_AX_LS_TEST BIT(9) +#define B_AX_LS_CHANGE BIT(8) +#define B_AX_FORCE_HS_SW BIT(7) +#define B_AX_FORCE_FS_SW BIT(6) +#define B_AX_FORCE_HSXCVR BIT(5) +#define B_AX_FORCE_FSXCVR BIT(4) +#define B_AX_FORCE_HSTERM BIT(3) +#define B_AX_FORCE_FSTERM BIT(2) +#define B_AX_FORCE_NORM_SW BIT(1) +#define B_AX_FORCE_DBSN BIT(0) + +#define R_AX_USB2_LPM_0 0x1010 +#define B_AX_USBPHY_PLL_ALIVE BIT(17) +#define B_AX_USB_LPM_MAX_EN BIT(16) +#define B_AX_USB_LPM_MIN_EN BIT(15) +#define B_AX_BESL_EN BIT(14) +#define B_AX_USB_LPM_NYET_EN BIT(13) +#define B_AX_USB_LPM_MAX_ACK BIT(12) +#define B_AX_USB_LPM_EN BIT(11) +#define B_AX_USB2_SUSB BIT(10) +#define B_AX_LPM_PLL_ALIVE BIT(9) +#define B_AX_USB_LPS_OUT BIT(8) +#define B_AX_USB_LPM_WAKEUP_EN BIT(6) +#define B_AX_NEVER_SUSPEND BIT(5) +#define B_AX_SUSPND_EN BIT(4) +#define B_AX_WAKEUP_EN BIT(3) +#define B_AX_USB_SUS_WAKEUP_EN BIT(2) +#define B_AX_RESUME_SND BIT(1) +#define B_AX_CONNECT_EN BIT(0) + +#define R_AX_USB2_LPM_1 0x1014 +#define B_AX_USB_LPM_MAX_SH 20 +#define B_AX_USB_LPM_MAX_MSK 0xf +#define B_AX_USB_LPM_MIN_SH 16 +#define B_AX_USB_LPM_MIN_MSK 0xf +#define B_AX_R_WAKE_HOST_WT_H_SH 8 +#define B_AX_R_WAKE_HOST_WT_H_MSK 0xff +#define B_AX_R_WAKE_HOST_WT_L_SH 0 +#define B_AX_R_WAKE_HOST_WT_L_MSK 0xff + +#define R_AX_USB2_MACRO_TEST_MODE 0x1018 +#define B_AX_TXRDY_SLB_SEL BIT(14) +#define B_AX_SLB_EN BIT(13) +#define B_AX_SLB_RST BIT(12) +#define B_AX_SLB_FAIL BIT(11) +#define B_AX_SLB_DONE BIT(10) +#define B_AX_SLB_PS1_SW_SH 8 +#define B_AX_SLB_PS1_SW_MSK 0x3 +#define B_AX_PHY_LOOP_TEST BIT(3) +#define B_AX_USBTMOD_SH 0 +#define B_AX_USBTMOD_MSK 0x7 + +#define R_AX_USB2_PHY_REG_0 0x1020 +#define B_AX_USB2PHY_REG_EN BIT(17) +#define B_AX_VLPADM BIT(16) +#define B_AX_VSTATUS_IN_SH 8 +#define B_AX_VSTATUS_IN_MSK 0xff +#define B_AX_VCONTROL_SH 0 +#define B_AX_VCONTROL_MSK 0xff + +#define R_AX_USB2_PHY_REG_1 0x1024 +#define B_AX_USB2PHY_DELAY_SH 8 +#define B_AX_USB2PHY_DELAY_MSK 0xff +#define B_AX_VSTATUS_OUT_SH 0 +#define B_AX_VSTATUS_OUT_MSK 0xff + +#define R_AX_USB2_PHY_REG_2 0x1028 +#define B_AX_USB2_PHY_P0_E3_SH 24 +#define B_AX_USB2_PHY_P0_E3_MSK 0xff +#define B_AX_USB2_PHY_P0_E2_SH 16 +#define B_AX_USB2_PHY_P0_E2_MSK 0xff +#define B_AX_USB2_PHY_P0_E1_SH 8 +#define B_AX_USB2_PHY_P0_E1_MSK 0xff +#define B_AX_USB2_PHY_P0_E0_SH 0 +#define B_AX_USB2_PHY_P0_E0_MSK 0xff + +#define R_AX_USB2_PHY_REG_3 0x102C +#define B_AX_USB2_PHY_P0_E7_SH 24 +#define B_AX_USB2_PHY_P0_E7_MSK 0xff +#define B_AX_USB2_PHY_P0_E6_SH 16 +#define B_AX_USB2_PHY_P0_E6_MSK 0xff +#define B_AX_USB2_PHY_P0_E5_SH 8 +#define B_AX_USB2_PHY_P0_E5_MSK 0xff +#define B_AX_USB2_PHY_P0_E4_SH 0 +#define B_AX_USB2_PHY_P0_E4_MSK 0xff + +#define R_AX_USB2_PHY_REG_4 0x1030 +#define B_AX_USB2_PHY_P1_E3_SH 24 +#define B_AX_USB2_PHY_P1_E3_MSK 0xff +#define B_AX_USB2_PHY_P1_E2_SH 16 +#define B_AX_USB2_PHY_P1_E2_MSK 0xff +#define B_AX_USB2_PHY_P1_E1_SH 8 +#define B_AX_USB2_PHY_P1_E1_MSK 0xff +#define B_AX_USB2_PHY_P1_E0_SH 0 +#define B_AX_USB2_PHY_P1_E0_MSK 0xff + +#define R_AX_USB2_PHY_REG_5 0x1034 +#define B_AX_USB2_PHY_P1_E7_SH 24 +#define B_AX_USB2_PHY_P1_E7_MSK 0xff +#define B_AX_USB2_PHY_P1_E6_SH 16 +#define B_AX_USB2_PHY_P1_E6_MSK 0xff +#define B_AX_USB2_PHY_P1_E5_SH 8 +#define B_AX_USB2_PHY_P1_E5_MSK 0xff +#define B_AX_USB2_PHY_P1_E4_SH 0 +#define B_AX_USB2_PHY_P1_E4_MSK 0xff + +#define R_AX_USB2_PHY_REG_6 0x1038 +#define B_AX_USB2_PHY_F3_SH 24 +#define B_AX_USB2_PHY_F3_MSK 0xff +#define B_AX_USB2_PHY_F2_SH 16 +#define B_AX_USB2_PHY_F2_MSK 0xff +#define B_AX_USB2_PHY_F1_SH 8 +#define B_AX_USB2_PHY_F1_MSK 0xff +#define B_AX_USB2_PHY_F0_SH 0 +#define B_AX_USB2_PHY_F0_MSK 0xff + +#define R_AX_USB2_PHY_REG_7 0x103C +#define B_AX_USB2_PHY_F7_SH 24 +#define B_AX_USB2_PHY_F7_MSK 0xff +#define B_AX_USB2_PHY_F6_SH 16 +#define B_AX_USB2_PHY_F6_MSK 0xff +#define B_AX_USB2_PHY_F5_SH 8 +#define B_AX_USB2_PHY_F5_MSK 0xff +#define B_AX_USB2_PHY_F4_SH 0 +#define B_AX_USB2_PHY_F4_MSK 0xff + +#define R_AX_USB2_PHY_REG_8 0x1040 + +#define R_AX_USB2_INTERRUPT_0 0x1050 +#define B_AX_IE_ATTACHF BIT(30) +#define B_AX_IE_INITF BIT(29) +#define B_AX_IE_SE0RSTF BIT(28) +#define B_AX_IE_RESUMEF BIT(27) +#define B_AX_IE_SUSPNDF BIT(26) +#define B_AX_IE_EP0CSF BIT(25) +#define B_AX_IE_SOFF BIT(24) +#define B_AX_I_ATTACHF BIT(22) +#define B_AX_I_INITF BIT(21) +#define B_AX_I_SE0RSTF BIT(20) +#define B_AX_I_RESUMEF BIT(19) +#define B_AX_I_SUSPNDF BIT(18) +#define B_AX_I_EP0CSF BIT(17) +#define B_AX_I_SOFF BIT(16) +#define B_AX_IE_SETUP BIT(11) +#define B_AX_IE_EXREG_DMA BIT(10) +#define B_AX_I_SETUPF BIT(9) +#define B_AX_I_EXREG_DMA BIT(8) +#define B_AX_I_STANDARD_REQ BIT(7) +#define B_AX_I_CLASS_REQ BIT(6) +#define B_AX_I_DWEN_REQ BIT(5) +#define B_AX_I_VEND_REQ BIT(4) +#define B_AX_IE_STANDARD_REQ BIT(3) +#define B_AX_IE_CLASS_REQ BIT(2) +#define B_AX_IE_DWEN_REQ BIT(1) +#define B_AX_IE_VEND_REQ BIT(0) + +#define R_AX_USB2_INTERRUPT_1 0x1054 +#define B_AX_USB2_IB_LDO_DELAY_TIME_SH 8 +#define B_AX_USB2_IB_LDO_DELAY_TIME_MSK 0xff +#define B_AX_VENDOR_INDEX_SH 0 +#define B_AX_VENDOR_INDEX_MSK 0xff + +#define R_AX_USB_ENDPOINT_0 0x1060 +#define B_AX_EP_MAXPKT_SH 16 +#define B_AX_EP_MAXPKT_MSK 0x3ff +#define B_AX_EP_EN BIT(15) +#define B_AX_EP_TYPE_SH 13 +#define B_AX_EP_TYPE_MSK 0x3 +#define B_AX_EP_ISTALL BIT(12) +#define B_AX_EP_OSTALL BIT(11) +#define B_AX_EP_STREAMEN BIT(10) +#define B_AX_EP_OUT BIT(9) +#define B_AX_EP_IN BIT(8) +#define B_AX_BT_INTR_SEL BIT(5) +#define B_AX_R_SIE_INIT_DONE BIT(4) +#define B_AX_EP_IDX_SH 0 +#define B_AX_EP_IDX_MSK 0xf + +#define R_AX_USB_ENDPOINT_1 0x1064 +#define B_AX_EP_MAX_STREAM_SH 16 +#define B_AX_EP_MAX_STREAM_MSK 0xff +#define B_AX_EP_MAX_BURST_SH 8 +#define B_AX_EP_MAX_BURST_MSK 0xff +#define B_AX_EP_INT_INTERVAL_SH 0 +#define B_AX_EP_INT_INTERVAL_MSK 0xff + +#define R_AX_USB_ENDPOINT_2 0x1068 +#define B_AX_EP_BPI_SH 16 +#define B_AX_EP_BPI_MSK 0xffff +#define B_AX_USB3_EP_IN_ST_SH 8 +#define B_AX_USB3_EP_IN_ST_MSK 0xff +#define B_AX_USB3_EP_OUT_ST_SH 0 +#define B_AX_USB3_EP_OUT_ST_MSK 0xff + +#define R_AX_USB_ENDPOINT_3 0x106C +#define B_AX_EP12_PAUSE_STATE BIT(31) +#define B_AX_EP11_PAUSE_STATE BIT(30) +#define B_AX_EP10_PAUSE_STATE BIT(29) +#define B_AX_EP9_PAUSE_STATE BIT(28) +#define B_AX_EP8_PAUSE_STATE BIT(27) +#define B_AX_EP7_PAUSE_STATE BIT(26) +#define B_AX_EP6_PAUSE_STATE BIT(25) +#define B_AX_EP5_PAUSE_STATE BIT(24) +#define B_AX_EP4_PAUSE_STATE BIT(23) +#define B_AX_EP12_TX_PAUSE BIT(22) +#define B_AX_EP11_TX_PAUSE BIT(21) +#define B_AX_EP10_TX_PAUSE BIT(20) +#define B_AX_EP9_TX_PAUSE BIT(19) +#define B_AX_EP8_RX_PAUSE BIT(18) +#define B_AX_EP7_TX_PAUSE BIT(17) +#define B_AX_EP6_TX_PAUSE BIT(16) +#define B_AX_EP5_TX_PAUSE BIT(15) +#define B_AX_EP4_RX_PAUSE BIT(14) +#define B_AX_INTERRUPT_BULK_IN BIT(11) +#define B_AX_BULKOUT1 BIT(9) +#define B_AX_BULKOUT0 BIT(8) +#define B_AX_AC_BULKOUT_SH 10 +#define B_AX_AC_BULKOUT_MSK 0x3 +#define B_AX_INTERRUPT_INTERVAL_SH 0 +#define B_AX_INTERRUPT_INTERVAL_MSK 0xf + +// +// 8852C ENDPOINT +// +#define R_AX_USB_ENDPOINT_3_V1 0x506C + +#define R_AX_USB_HOST_REQUEST_0 0x1070 +#define B_AX_ERR_STR2_LEN_SH 24 +#define B_AX_ERR_STR2_LEN_MSK 0xff +#define B_AX_ERR_STR1_LEN_SH 8 +#define B_AX_ERR_STR1_LEN_MSK 0xffff +#define B_AX_DEVADDR_SH 0 +#define B_AX_DEVADDR_MSK 0x7f + +#define R_AX_USB_HOST_REQUEST_1 0x1074 +#define B_AX_USB_PID_SH 16 +#define B_AX_USB_PID_MSK 0xffff +#define B_AX_USB_VID_SH 0 +#define B_AX_USB_VID_MSK 0xffff + +#define R_AX_USB_HOST_REQUEST_2 0x1078 +#define B_AX_MAC_ADDR_1_SH 24 +#define B_AX_MAC_ADDR_1_MSK 0xff +#define B_AX_MAC_ADDR_0_SH 16 +#define B_AX_MAC_ADDR_0_MSK 0xff +#define B_AX_FORCE_LPM_BCD201 BIT(15) +#define B_AX_SELF_POWER_EN BIT(14) +#define B_AX_R_FORCE_U3MAC_HS_MODE BIT(13) +#define B_AX_LOAD_LTM_CAP BIT(12) +#define B_AX_USB3_DEV_CAP_DESC_EN BIT(11) +#define B_AX_AUTOLOAD_STRING_EN BIT(10) +#define B_AX_REMOTE_WAKEUP BIT(9) +#define B_AX_SQNUM_ROM BIT(8) +#define B_AX_ERR_STR2_LEN_FLAG BIT(7) +#define B_AX_ERR_STR1_LEN_FLAG_1 BIT(6) +#define B_AX_ERR_STR1_LEN_FLAG_0 BIT(5) +#define B_AX_R_USBIO_MODE BIT(4) +#define B_AX_EXREG_TO_EN BIT(3) +#define B_AX_EXREG_TO_SEL_SH 0 +#define B_AX_EXREG_TO_SEL_MSK 0x7 + +#define R_AX_USB_HOST_REQUEST_3 0x107C +#define B_AX_MAC_ADDR_5_SH 24 +#define B_AX_MAC_ADDR_5_MSK 0xff +#define B_AX_MAC_ADDR_4_SH 16 +#define B_AX_MAC_ADDR_4_MSK 0xff +#define B_AX_MAC_ADDR_3_SH 8 +#define B_AX_MAC_ADDR_3_MSK 0xff +#define B_AX_MAC_ADDR_2_SH 0 +#define B_AX_MAC_ADDR_2_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_4 0x1080 +#define B_AX__MANUFACTURE_STRING_3_SH 24 +#define B_AX__MANUFACTURE_STRING_3_MSK 0xff +#define B_AX__MANUFACTURE_STRING_2_SH 16 +#define B_AX__MANUFACTURE_STRING_2_MSK 0xff +#define B_AX__MANUFACTURE_STRING_1_SH 8 +#define B_AX__MANUFACTURE_STRING_1_MSK 0xff +#define B_AX__MANUFACTURE_STRING_0_SH 0 +#define B_AX__MANUFACTURE_STRING_0_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_5 0x1084 +#define B_AX_MANUFACTURE_STRING_7_SH 24 +#define B_AX_MANUFACTURE_STRING_7_MSK 0xff +#define B_AX_MANUFACTURE_STRING_6_SH 16 +#define B_AX_MANUFACTURE_STRING_6_MSK 0xff +#define B_AX_MANUFACTURE_STRING_5_SH 8 +#define B_AX_MANUFACTURE_STRING_5_MSK 0xff +#define B_AX_MANUFACTURE_STRING_4_SH 0 +#define B_AX_MANUFACTURE_STRING_4_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_6 0x1088 +#define B_AX_MANUFACTURE_STRING_B_SH 24 +#define B_AX_MANUFACTURE_STRING_B_MSK 0xff +#define B_AX_MANUFACTURE_STRING_A_SH 16 +#define B_AX_MANUFACTURE_STRING_A_MSK 0xff +#define B_AX_MANUFACTURE_STRING_9_SH 8 +#define B_AX_MANUFACTURE_STRING_9_MSK 0xff +#define B_AX_MANUFACTURE_STRING_8_SH 0 +#define B_AX_MANUFACTURE_STRING_8_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_7 0x108C +#define B_AX_MANUFACTURE_STRING_F_SH 24 +#define B_AX_MANUFACTURE_STRING_F_MSK 0xff +#define B_AX_MANUFACTURE_STRING_E_SH 16 +#define B_AX_MANUFACTURE_STRING_E_MSK 0xff +#define B_AX_MANUFACTURE_STRING_D_SH 8 +#define B_AX_MANUFACTURE_STRING_D_MSK 0xff +#define B_AX_MANUFACTURE_STRING_C_SH 0 +#define B_AX_MANUFACTURE_STRING_C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_8 0x1090 +#define B_AX_MANUFACTURE_STRING_13_SH 24 +#define B_AX_MANUFACTURE_STRING_13_MSK 0xff +#define B_AX_MANUFACTURE_STRING_12_SH 16 +#define B_AX_MANUFACTURE_STRING_12_MSK 0xff +#define B_AX_MANUFACTURE_STRING_11_SH 8 +#define B_AX_MANUFACTURE_STRING_11_MSK 0xff +#define B_AX_MANUFACTURE_STRING_10_SH 0 +#define B_AX_MANUFACTURE_STRING_10_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_9 0x1094 +#define B_AX_MANUFACTURE_STRING_17_SH 24 +#define B_AX_MANUFACTURE_STRING_17_MSK 0xff +#define B_AX_MANUFACTURE_STRING_16_SH 16 +#define B_AX_MANUFACTURE_STRING_16_MSK 0xff +#define B_AX_MANUFACTURE_STRING_15_SH 8 +#define B_AX_MANUFACTURE_STRING_15_MSK 0xff +#define B_AX_MANUFACTURE_STRING_14_SH 0 +#define B_AX_MANUFACTURE_STRING_14_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_A 0x1098 +#define B_AX_MANUFACTURE_STRING_1B_SH 24 +#define B_AX_MANUFACTURE_STRING_1B_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1A_SH 16 +#define B_AX_MANUFACTURE_STRING_1A_MSK 0xff +#define B_AX_MANUFACTURE_STRING_19_SH 8 +#define B_AX_MANUFACTURE_STRING_19_MSK 0xff +#define B_AX_MANUFACTURE_STRING_18_SH 0 +#define B_AX_MANUFACTURE_STRING_18_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_B 0x109C +#define B_AX_MANUFACTURE_STRING_1F_SH 24 +#define B_AX_MANUFACTURE_STRING_1F_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1E_SH 16 +#define B_AX_MANUFACTURE_STRING_1E_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1D_SH 8 +#define B_AX_MANUFACTURE_STRING_1D_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1C_SH 0 +#define B_AX_MANUFACTURE_STRING_1C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_C 0x10A0 +#define B_AX_PRODUCT_STRING_3_SH 24 +#define B_AX_PRODUCT_STRING_3_MSK 0xff +#define B_AX_PRODUCT_STRING_2_SH 16 +#define B_AX_PRODUCT_STRING_2_MSK 0xff +#define B_AX_PRODUCT_STRING_1_SH 8 +#define B_AX_PRODUCT_STRING_1_MSK 0xff +#define B_AX_PRODUCT_STRING_0_SH 0 +#define B_AX_PRODUCT_STRING_0_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_D 0x10A4 +#define B_AX_PRODUCT_STRING_7_SH 24 +#define B_AX_PRODUCT_STRING_7_MSK 0xff +#define B_AX_PRODUCT_STRING_6_SH 16 +#define B_AX_PRODUCT_STRING_6_MSK 0xff +#define B_AX_PRODUCT_STRING_5_SH 8 +#define B_AX_PRODUCT_STRING_5_MSK 0xff +#define B_AX_PRODUCT_STRING_4_SH 0 +#define B_AX_PRODUCT_STRING_4_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_E 0x10A8 +#define B_AX_PRODUCT_STRING_B_SH 24 +#define B_AX_PRODUCT_STRING_B_MSK 0xff +#define B_AX_PRODUCT_STRING_A_SH 16 +#define B_AX_PRODUCT_STRING_A_MSK 0xff +#define B_AX_PRODUCT_STRING_9_SH 8 +#define B_AX_PRODUCT_STRING_9_MSK 0xff +#define B_AX_PRODUCT_STRING_8_SH 0 +#define B_AX_PRODUCT_STRING_8_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_F 0x10AC +#define B_AX_PRODUCT_STRING_F_SH 24 +#define B_AX_PRODUCT_STRING_F_MSK 0xff +#define B_AX_PRODUCT_STRING_E_SH 16 +#define B_AX_PRODUCT_STRING_E_MSK 0xff +#define B_AX_PRODUCT_STRING_D_SH 8 +#define B_AX_PRODUCT_STRING_D_MSK 0xff +#define B_AX_PRODUCT_STRING_C_SH 0 +#define B_AX_PRODUCT_STRING_C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_10 0x10B0 +#define B_AX_PRODUCT_STRING_13_SH 24 +#define B_AX_PRODUCT_STRING_13_MSK 0xff +#define B_AX_PRODUCT_STRING_12_SH 16 +#define B_AX_PRODUCT_STRING_12_MSK 0xff +#define B_AX_PRODUCT_STRING_11_SH 8 +#define B_AX_PRODUCT_STRING_11_MSK 0xff +#define B_AX_PRODUCT_STRING_10_SH 0 +#define B_AX_PRODUCT_STRING_10_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_11 0x10B4 +#define B_AX_PRODUCT_STRING_17_SH 24 +#define B_AX_PRODUCT_STRING_17_MSK 0xff +#define B_AX_PRODUCT_STRING_16_SH 16 +#define B_AX_PRODUCT_STRING_16_MSK 0xff +#define B_AX_PRODUCT_STRING_15_SH 8 +#define B_AX_PRODUCT_STRING_15_MSK 0xff +#define B_AX_PRODUCT_STRING_14_SH 0 +#define B_AX_PRODUCT_STRING_14_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_12 0x10B8 +#define B_AX_PRODUCT_STRING_1B_SH 24 +#define B_AX_PRODUCT_STRING_1B_MSK 0xff +#define B_AX_PRODUCT_STRING_1A_SH 16 +#define B_AX_PRODUCT_STRING_1A_MSK 0xff +#define B_AX_PRODUCT_STRING_19_SH 8 +#define B_AX_PRODUCT_STRING_19_MSK 0xff +#define B_AX_PRODUCT_STRING_18_SH 0 +#define B_AX_PRODUCT_STRING_18_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_13 0x10BC +#define B_AX_PRODUCT_STRING_1F_SH 24 +#define B_AX_PRODUCT_STRING_1F_MSK 0xff +#define B_AX_PRODUCT_STRING_1E_SH 16 +#define B_AX_PRODUCT_STRING_1E_MSK 0xff +#define B_AX_PRODUCT_STRING_1D_SH 8 +#define B_AX_PRODUCT_STRING_1D_MSK 0xff +#define B_AX_PRODUCT_STRING_1C_SH 0 +#define B_AX_PRODUCT_STRING_1C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_14 0x10C0 +#define B_AX_PRODUCT_STRING_23_SH 24 +#define B_AX_PRODUCT_STRING_23_MSK 0xff +#define B_AX_PRODUCT_STRING_22_SH 16 +#define B_AX_PRODUCT_STRING_22_MSK 0xff +#define B_AX_PRODUCT_STRING_21_SH 8 +#define B_AX_PRODUCT_STRING_21_MSK 0xff +#define B_AX_PRODUCT_STRING_20_SH 0 +#define B_AX_PRODUCT_STRING_20_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_15 0x10C4 +#define B_AX_PRODUCT_STRING_27_SH 24 +#define B_AX_PRODUCT_STRING_27_MSK 0xff +#define B_AX_PRODUCT_STRING_26_SH 16 +#define B_AX_PRODUCT_STRING_26_MSK 0xff +#define B_AX_PRODUCT_STRING_25_SH 8 +#define B_AX_PRODUCT_STRING_25_MSK 0xff +#define B_AX_PRODUCT_STRING_24_SH 0 +#define B_AX_PRODUCT_STRING_24_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_16 0x10C8 +#define B_AX_PRODUCT_STRING_2B_SH 24 +#define B_AX_PRODUCT_STRING_2B_MSK 0xff +#define B_AX_PRODUCT_STRING_2A_SH 16 +#define B_AX_PRODUCT_STRING_2A_MSK 0xff +#define B_AX_PRODUCT_STRING_29_SH 8 +#define B_AX_PRODUCT_STRING_29_MSK 0xff +#define B_AX_PRODUCT_STRING_28_SH 0 +#define B_AX_PRODUCT_STRING_28_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_17 0x10CC +#define B_AX_PRODUCT_STRING_2F_SH 24 +#define B_AX_PRODUCT_STRING_2F_MSK 0xff +#define B_AX_PRODUCT_STRING_2E_SH 16 +#define B_AX_PRODUCT_STRING_2E_MSK 0xff +#define B_AX_PRODUCT_STRING_2D_SH 8 +#define B_AX_PRODUCT_STRING_2D_MSK 0xff +#define B_AX_PRODUCT_STRING_2C_SH 0 +#define B_AX_PRODUCT_STRING_2C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_18 0x10D0 +#define B_AX_SERIAL_NUMBER_STRING_3_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_3_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_2_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_2_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_1_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_0_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_0_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_19 0x10D4 +#define B_AX_SERIAL_NUMBER_STRING_7_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_7_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_6_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_6_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_5_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_5_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_4_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_4_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1A 0x10D8 +#define B_AX_SERIAL_NUMBER_STRING_B_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_B_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_A_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_A_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_9_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_9_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_8_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_8_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1B 0x10DC +#define B_AX_SERIAL_NUMBER_STRING_F_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_F_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_E_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_E_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_D_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_D_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_C_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_C_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1C 0x10E0 +#define B_AX_USB3_U2SEL_SH 16 +#define B_AX_USB3_U2SEL_MSK 0xffff +#define B_AX_USB3_U1PEL_SH 0 +#define B_AX_USB3_U1PEL_MSK 0xffff + +#define R_AX_USB_HOST_REQUEST_1D 0x10E4 +#define B_AX_HW_VENDOR_INDEX_SH 16 +#define B_AX_HW_VENDOR_INDEX_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1E 0x10E8 +#define B_AX_DIS_STALL_FUNC_WAKE BIT(24) +#define B_AX_USB3_U2_DEV_EXIT_LAT_SH 8 +#define B_AX_USB3_U2_DEV_EXIT_LAT_MSK 0xffff +#define B_AX_USB3_U1_DEV_EXIT_LAT_SH 0 +#define B_AX_USB3_U1_DEV_EXIT_LAT_MSK 0xff + +#define R_AX_USB3_MAC_LINK_0 0x1100 +#define B_AX_INTS_USB3_HRESET_EN BIT(31) +#define B_AX_INTS_USB3_RECOV_EN BIT(30) +#define B_AX_INTS_USB3_LPBK_EN BIT(29) +#define B_AX_INTS_USB3_RXDET_EN BIT(28) +#define B_AX_INTS_USB3_POLL_EN BIT(27) +#define B_AX_INTS_USB3_U3_EN BIT(26) +#define B_AX_INTS_USB3_U1U2_EN BIT(25) +#define B_AX_INTS_USB3_U0_EN BIT(24) +#define B_AX_INTS_USB3_RECOV2U0_EN BIT(23) +#define B_AX_INTS_USB3_SSINACT_EN BIT(22) +#define B_AX_INTS_USB3_SSDIS_EN BIT(21) +#define B_AX_INTS_USB3_CMPLY_EN BIT(20) +#define B_AX_INTS_USB3_RECOV2U0 BIT(19) +#define B_AX_INTS_USB3_SSINACT BIT(18) +#define B_AX_INTS_USB3_SSDIS BIT(17) +#define B_AX_INTS_USB3_CMPLY BIT(16) +#define B_AX_INTS_USB3_HRESET BIT(15) +#define B_AX_INTS_USB3_RECOV BIT(14) +#define B_AX_INTS_USB3_LPBK BIT(13) +#define B_AX_INTS_USB3_RXDET BIT(12) +#define B_AX_INTS_USB3_POLL BIT(11) +#define B_AX_INTS_USB3_U3 BIT(10) +#define B_AX_INTS_USB3_U1U2 BIT(9) +#define B_AX_INTS_USB3_U0 BIT(8) +#define B_AX_EN_ROVIDLE_TIMEOUT BIT(6) +#define B_AX_EN_UNFIN_RTY BIT(5) +#define B_AX_SSPHY_U1_QUICK_LFPS BIT(4) +#define B_AX_USB3_DIS_ISOC_TIME_GT BIT(3) +#define B_AX_R_DIS_USB3_U2_EN BIT(2) +#define B_AX_R_DIS_USB3_U1_EN BIT(1) +#define B_AX_LINK_ST_DETECT_TERM BIT(0) + +#define R_AX_USB3_MAC_LINK_1 0x1104 +#define B_AX_WARM_RESET_TIME_SH 0 +#define B_AX_WARM_RESET_TIME_MSK 0x3 + +#define R_AX_USB3_MAC_PIU 0x1108 +#define B_AX_SSPHY_CLR_TERM BIT(1) +#define B_AX_SSPHY_SET_TERM BIT(0) + +#define R_AX_USB3_MAC_PTL 0x110C +#define B_AX_WLAN0_BUF_NUMP_EN BIT(1) +#define B_AX_IGNORE_RETRY_BIT BIT(0) + +#define R_AX_USB3_MAC_PRTSM 0x1110 +#define B_AX_EN_IMMED_POP_CREDIT BIT(0) + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0 0x1114 +#define B_AX_SSPHY_LFPS_FILTER BIT(31) +#define B_AX_SSPHY_TX_SWING BIT(30) +#define B_AX_SSPHY_TXMARGIN_SH 27 +#define B_AX_SSPHY_TXMARGIN_MSK 0x7 +#define B_AX_SSPHY_TXDEEMPHASIS_SH 25 +#define B_AX_SSPHY_TXDEEMPHASIS_MSK 0x3 +#define B_AX_SSPHY_ELASTIC_BUF BIT(24) +#define B_AX_HIRD_THR_SH 19 +#define B_AX_HIRD_THR_MSK 0x1f +#define B_AX_DEV_SPEED_SH 16 +#define B_AX_DEV_SPEED_MSK 0x7 +#define B_AX_U1_ACTIVE_TIMEOUT_SH 8 +#define B_AX_U1_ACTIVE_TIMEOUT_MSK 0xff +#define B_AX_USB3_TARGET_LINK_STATE_SH 4 +#define B_AX_USB3_TARGET_LINK_STATE_MSK 0xf +#define B_AX_APPL1RSP BIT(3) +#define B_AX_LPM_CAPABLE BIT(2) +#define B_AX_USB3_EOF_SH 0 +#define B_AX_USB3_EOF_MSK 0x3 + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_1 0x1118 +#define B_AX_NPI_SCALEDOWN_MODE_SH 24 +#define B_AX_NPI_SCALEDOWN_MODE_MSK 0x3 +#define B_AX_SSPHY_POWERDOWN_SCALE_SH 8 +#define B_AX_SSPHY_POWERDOWN_SCALE_MSK 0x1fff +#define B_AX_SSPHY_U1_FAST_OUT BIT(7) +#define B_AX_SSPHY_P3_FOR_P2 BIT(6) +#define B_AX_SSPHY_U1_RXVALID BIT(5) +#define B_AX_SSPHY_DIS_SCAMBLE BIT(4) +#define B_AX_SSPHY_SKIP_RXDETECT BIT(3) +#define B_AX_SSPHY_LFPS_P0_ALIGN BIT(2) +#define B_AX_SSPHY_P3P2_TRANS BIT(1) +#define B_AX_SSPHY_P3_EXITIN_P2 BIT(0) + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_2 0x111C +#define B_AX_SSPHY_U2EXIT_LPFS BIT(18) +#define B_AX_SSPHY_PHYSOFTRST BIT(17) +#define B_AX_SSPHY_HSTPRTCMPL BIT(16) +#define B_AX_SSPHY_U2SSINACTP3OK BIT(15) +#define B_AX_SSPHY_DISRXDETP3 BIT(14) +#define B_AX_SSPHY_UX_EXIT_IN_PX BIT(13) +#define B_AX_SSPHY_PING_ENH_EN BIT(12) +#define B_AX_SSPHY_U1U2EXITFAIL_TO_RECOV BIT(11) +#define B_AX_SSPHY_ALWAYS_REQ BIT(10) +#define B_AX_SSPHY_START_RX_DET BIT(9) +#define B_AX_SSPHY_DIS_RX_DET BIT(8) +#define B_AX_SSPHY_DELAY_P1P2P3_SH 5 +#define B_AX_SSPHY_DELAY_P1P2P3_MSK 0x7 +#define B_AX_SSPHY_SUSPEND_EN BIT(4) +#define B_AX_SSPHY_DATWIDTH_SH 2 +#define B_AX_SSPHY_DATWIDTH_MSK 0x3 +#define B_AX_SSPHY_ABORTRXDETLNU2 BIT(1) +#define B_AX_SSPHY_RX_DETECT_LPFS BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_0 0x1120 +#define B_AX_U3_LTM_EN BIT(28) +#define B_AX_LINK_STATE_REQ_SH 24 +#define B_AX_LINK_STATE_REQ_MSK 0xf +#define B_AX_SUSCLK_RATIO_SH 8 +#define B_AX_SUSCLK_RATIO_MSK 0x1fff +#define B_AX_TEST_CTRL_SH 4 +#define B_AX_TEST_CTRL_MSK 0xf +#define B_AX_UFRAME_SCALE_SH 2 +#define B_AX_UFRAME_SCALE_MSK 0x3 +#define B_AX_LOCAL_LBK BIT(1) +#define B_AX_USB_EN_SLEEP BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_1 0x1124 +#define B_AX_WAKE_WAIT_XTAL BIT(27) +#define B_AX_WAKE_WAIT_CURRENT BIT(26) +#define B_AX_WAKEUP_NEG_SEL BIT(25) +#define B_AX_SSPHY_USB3_ATTEMPT BIT(24) +#define B_AX_WAIT_IDLE_TIME_SH 20 +#define B_AX_WAIT_IDLE_TIME_MSK 0xf +#define B_AX_U2_EN_MAC_IDLE BIT(18) +#define B_AX_U1_EN_MAC_IDLE BIT(17) +#define B_AX_SWITCH_CLK_EN BIT(16) +#define B_AX_USB3_SAMPLE_RXELECIDLE_SH 8 +#define B_AX_USB3_SAMPLE_RXELECIDLE_MSK 0xff +#define B_AX_U3_INIT_U2 BIT(7) +#define B_AX_U3_INIT_U1 BIT(6) +#define B_AX_SET_U3_WAKE BIT(5) +#define B_AX_U3_U2_EN BIT(4) +#define B_AX_U3_U1_EN BIT(3) +#define B_AX_U3_INIT_U2_EN BIT(2) +#define B_AX_U3_INIT_U1_EN BIT(1) +#define B_AX_USB3_RUN BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_2 0x1128 +#define B_AX_NPI_LINK_STATE_LATCH_SH 16 +#define B_AX_NPI_LINK_STATE_LATCH_MSK 0xff +#define B_AX_NPI_HOST_RESUME_DETECTED BIT(15) +#define B_AX_NPI_DEV_CONNECT_SPEED_SH 12 +#define B_AX_NPI_DEV_CONNECT_SPEED_MSK 0x7 +#define B_AX_NPI_LINK_STATE_SH 8 +#define B_AX_NPI_LINK_STATE_MSK 0xf +#define B_AX_POLL_EN BIT(7) +#define B_AX_POLL_SAMPLE_ON BIT(6) +#define B_AX_POLL_ACT_SH 4 +#define B_AX_POLL_ACT_MSK 0x3 +#define B_AX_POLL_NOACT_SH 0 +#define B_AX_POLL_NOACT_MSK 0xf + +#define R_AX_USB3_MAC_NPI_POWER_3 0x112C +#define B_AX_R_CNT_SWITCH_USB32_PARA_SH 0 +#define B_AX_R_CNT_SWITCH_USB32_PARA_MSK 0xffff + +#define R_AX_USB3_MAC_NPI_STATUS 0x1130 +#define B_AX_NPI_DEV_CONNECTED BIT(0) + +#define R_AX_USB3_MAC_NPI_DEVICE_NOTIFICATION 0x1134 +#define B_AX_DEVNOTE_BIA_SH 16 +#define B_AX_DEVNOTE_BIA_MSK 0xffff +#define B_AX_DEVNOTE_BELT_SH 0 +#define B_AX_DEVNOTE_BELT_MSK 0xfff + +#define R_AX_USB3_MAC_NPI_TRANSMIT 0x1138 +#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_SH 0 +#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_MSK 0xf + +#define R_AX_USB3_MAC_NPI_OTHERS 0x113C +#define B_AX_EN_FIX_RX_ABORT BIT(8) +#define B_AX_FLADJ_30MHZ_REG_SH 0 +#define B_AX_FLADJ_30MHZ_REG_MSK 0x3f + +#define R_AX_USB3_WRAP_0 0x1140 +#define B_AX_U1TOU2_TIMER_SH 24 +#define B_AX_U1TOU2_TIMER_MSK 0xff +#define B_AX_WAKE_ST_DBG_SH 20 +#define B_AX_WAKE_ST_DBG_MSK 0xf +#define B_AX_ARB_ST_DBG_SH 18 +#define B_AX_ARB_ST_DBG_MSK 0x3 +#define B_AX_BIA_REQ BIT(17) +#define B_AX_BELT_REQ BIT(16) +#define B_AX_USB3_VENDOR_LEN_TH_SH 0 +#define B_AX_USB3_VENDOR_LEN_TH_MSK 0xffff + +#define R_AX_USB3_WRAP_1 0x1144 +#define B_AX_DIS_PKT_FUNC_WAKE BIT(0) + +#define R_AX_USB3_PHY 0x1148 +#define B_AX_USB3_PHY_RWDATA_SH 16 +#define B_AX_USB3_PHY_RWDATA_MSK 0xffff +#define B_AX_USB3_PHY_ADR_SH 8 +#define B_AX_USB3_PHY_ADR_MSK 0x1f +#define B_AX_USB3_PHY_REG_WRFLAG BIT(7) +#define B_AX_USB3_PHY_REG_RDFLAG BIT(6) +#define B_AX_USB3_PHY_REG_ADR_SH 0 +#define B_AX_USB3_PHY_REG_ADR_MSK 0x1f + +#define R_AX_USB3_OTHERS 0x1150 +#define B_AX_R_REATTACH_TIMER_SH 28 +#define B_AX_R_REATTACH_TIMER_MSK 0xf +#define B_AX_R_CNT_MS_SEL_SH 24 +#define B_AX_R_CNT_MS_SEL_MSK 0x7 +#define B_AX_VENDOR_LPM_TEST_SH 16 +#define B_AX_VENDOR_LPM_TEST_MSK 0xff +#define B_AX_ISOC_DELAY_VALUE_SH 0 +#define B_AX_ISOC_DELAY_VALUE_MSK 0xffff + +#define R_AX_USB_APPLICATION_BT_0 0x1160 +#define B_AX_BTRX0_BUFFER_WADDR_SH 24 +#define B_AX_BTRX0_BUFFER_WADDR_MSK 0xff +#define B_AX_USB_INTOKEN_TIMEOUT_SH 20 +#define B_AX_USB_INTOKEN_TIMEOUT_MSK 0x7 +#define B_AX_BRX_BUF_CHK_SH 16 +#define B_AX_BRX_BUF_CHK_MSK 0x7 +#define B_AX_BTRX0_RPKT_SIZE_SH 0 +#define B_AX_BTRX0_RPKT_SIZE_MSK 0xffff + +#define R_AX_USB_APPLICATION_BT_1 0x1164 +#define B_AX_USB2BT_PWR_INFO_REG_MASK_SH 20 +#define B_AX_USB2BT_PWR_INFO_REG_MASK_MSK 0xf +#define B_AX_FUNCTION_SUSB_EN_BT BIT(19) +#define B_AX_LOWPOWER_BT BIT(18) +#define B_AX_FUNCTION_WAKE_EN_BT BIT(17) +#define B_AX_FUNCTION_WAKE_CAPABLE_BT BIT(16) +#define B_AX_BT_ISO_ZERO_EN BIT(14) +#define B_AX_R_RXDMA_MODE_SH 12 +#define B_AX_R_RXDMA_MODE_MSK 0x3 +#define B_AX_GPS_USB_ACTIVE BIT(11) +#define B_AX_BT_TXQ_STOP_SH 8 +#define B_AX_BT_TXQ_STOP_MSK 0x7 + +#define R_AX_USB_APPLICATION_BT_2 0x1168 +#define B_AX_BT_TX BIT(17) +#define B_AX_BT_RX BIT(16) +#define B_AX_BTTX_FIFO_OVER_EP3 BIT(13) +#define B_AX_BTTX_FIFO_OVER_EP2 BIT(12) +#define B_AX_BTTX_FIFO_OVER_EP0 BIT(11) +#define B_AX_BTRX_FIFO_OVER_EP3 BIT(10) +#define B_AX_BTRX_FIFO_OVER_EP2 BIT(9) +#define B_AX_BTRX_FIFO_OVER_EP1 BIT(8) +#define B_AX_BTTX_FIFO_UNDR_EP3 BIT(5) +#define B_AX_BTTX_FIFO_UNDR_EP2 BIT(4) +#define B_AX_BTTX_FIFO_UNDR_EP0 BIT(3) +#define B_AX_BTRX_FIFO_UNDR_EP3 BIT(2) +#define B_AX_BTRX_FIFO_UNDR_EP2 BIT(1) +#define B_AX_BTRX_FIFO_UNDR_EP1 BIT(0) + +#define R_AX_USB_APPLICATION_BT_3 0x116C +#define B_AX_DBG_BTRX_WADDR_SH 16 +#define B_AX_DBG_BTRX_WADDR_MSK 0xfff +#define B_AX_DBG_BTRX_RPKT_SIZE_SH 0 +#define B_AX_DBG_BTRX_RPKT_SIZE_MSK 0xffff + +#define R_AX_USB_WLAN0_0 0x1170 +#define B_AX_WLAN_INT_LEN_SH 16 +#define B_AX_WLAN_INT_LEN_MSK 0xffff +#define B_AX_WLAN0_TXQ_STALL_DIS BIT(4) +#define B_AX_FUNCTION_SUSB_EN_WLAN0 BIT(3) +#define B_AX_LOWPOWER_WLAN0 BIT(2) +#define B_AX_FUNCTION_WAKE_EN_WLAN0 BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN0 BIT(0) + +#define R_AX_USB_WLAN0_1 0x1174 +#define B_AX_USBRX_RST BIT(9) +#define B_AX_USBTX_RST BIT(8) +#define B_AX_R_USBRX_SRAM_LS BIT(7) +#define B_AX_R_USBRX_SRAM_DS BIT(6) +#define B_AX_R_USBTX_SRAM_LS BIT(5) +#define B_AX_R_USBTX_SRAM_DS BIT(4) +#define B_AX_WLRX_FIFO_OVER_SH 2 +#define B_AX_WLRX_FIFO_OVER_MSK 0x3 +#define B_AX_WLRX_FIFO_UNDR_SH 0 +#define B_AX_WLRX_FIFO_UNDR_MSK 0x3 + +#define R_AX_USB_AUTO_INSTALL_0 0x1180 +#define B_AX_AINST_POLL_1 BIT(28) +#define B_AX_AINST_POLL_0 BIT(27) +#define B_AX_AINST_TX1_CLR_BUF BIT(26) +#define B_AX_AINST_TX0_CLR_BUF BIT(25) +#define B_AX_WLAN_FW_RDY BIT(24) +#define B_AX_RECONF_USBEP BIT(23) +#define B_AX_RECONF_USBEP_EN BIT(22) +#define B_AX_BULK_ONLY_MASS_STORAGE_RESET BIT(21) +#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_EN BIT(20) +#define B_AX_AINST_RXLEN_SH 8 +#define B_AX_AINST_RXLEN_MSK 0xfff +#define B_AX_AINST_RX1_INTR BIT(7) +#define B_AX_AINST_RX0_INTR BIT(6) +#define B_AX_AINXT_TX1_INTR BIT(5) +#define B_AX_AINST_TX0_INTR BIT(4) +#define B_AX_AUTO_INST_TXQ_STALL_DIS BIT(3) +#define B_AX_LOWPOWER_AINST BIT(2) +#define B_AX_FUNCTION_WANE_EN_AINST BIT(1) + +#define R_AX_USB_AUTO_INSTALL_1 0x1184 +#define B_AX_AINST_TX1LEN_SH 16 +#define B_AX_AINST_TX1LEN_MSK 0xfff +#define B_AX_AINST_TX0LEN_SH 0 +#define B_AX_AINST_TX0LEN_MSK 0xfff + +#define R_AX_USB_AUTO_INSTALL_2 0x1188 +#define B_AX_AINST_PID_SH 16 +#define B_AX_AINST_PID_MSK 0xffff +#define B_AX_AINST_VID_SH 0 +#define B_AX_AINST_VID_MSK 0xffff + +#define R_AX_USB_AUTO_INSTALL_3 0x118C +#define B_AX_AINST_TXSTATUS_SH 8 +#define B_AX_AINST_TXSTATUS_MSK 0xff +#define B_AX_AINST_RXSTATUS_SH 0 +#define B_AX_AINST_RXSTATUS_MSK 0xff + +#define R_AX_USB_BRIDGE_UART_0 0x1190 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_SH 20 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_MSK 0xfff +#define B_AX_BRIDGE_XFACTOR_SH 16 +#define B_AX_BRIDGE_XFACTOR_MSK 0xf +#define B_AX_BRIDGE_BAUD_USB2_SH 0 +#define B_AX_BRIDGE_BAUD_USB2_MSK 0xfff + +#define R_AX_USB_BRIDGE_UART_1 0x1194 +#define B_AX_BRIDGE_WAKEUP_EN_SH 30 +#define B_AX_BRIDGE_WAKEUP_EN_MSK 0x3 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_SH 16 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_MSK 0xfff +#define B_AX_BRIDGE_LE_CON_HAN_VLD BIT(9) +#define B_AX_BRIDGE_LE_ON BIT(8) +#define B_AX_BRIDGE_DEBUG_PKTCNT_EN BIT(6) +#define B_AX_BRIDGE_RESET_RCV_SEL BIT(5) +#define B_AX_BRIDGE_WLS0 BIT(4) +#define B_AX_BRIDGE_STB BIT(3) +#define B_AX_BRIDGE_PEN BIT(2) +#define B_AX_BRIDGE_EPS BIT(1) +#define B_AX_BRIDGE_STKP BIT(0) + +#define R_AX_USB_BRIDGE_UART_2 0x1198 +#define B_AX_BRIDGE_DEBUG_SEL_SH 24 +#define B_AX_BRIDGE_DEBUG_SEL_MSK 0xff +#define B_AX_R_BRIDGE_UARTEN BIT(23) +#define B_AX_BRIDGE_LPM_EN BIT(22) +#define B_AX_BRIDGE_TXSCO_TIME_INTERVAL_EN BIT(21) +#define B_AX_BRIDGE_TXSCO_PKT_LEN_MAT_EN BIT(20) +#define B_AX_BRIDGE_TXSCO_CON_HAN_MAT_EN BIT(19) +#define B_AX_BRIDGE_USB_TX_HCICMDLEN_SEL BIT(18) +#define B_AX_R_BRIDGE_JCIRXEN BIT(17) +#define B_AX_R_BRIDGE_HCITXEN BIT(16) +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_SH 0 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_MSK 0xfff + +#define R_AX_USB_BRIDGE_UART_3 0x119C +#define B_AX_BRIDGE_URT_RXINDIC_ERR BIT(31) +#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_SH 24 +#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_MSK 0x7f +#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_SH 16 +#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_MSK 0xff +#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_SH 8 +#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_MSK 0xff +#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_SH 0 +#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_MSK 0xff + +#define R_AX_USB_BRIDGE_UART_4 0x11A0 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_SH 20 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_MSK 0xfff +#define B_AX_BRIDGE_XFACTOR_USB3_SH 16 +#define B_AX_BRIDGE_XFACTOR_USB3_MSK 0xf +#define B_AX_BRIDGE_BAUD_USB3_SH 0 +#define B_AX_BRIDGE_BAUD_USB3_MSK 0xfff + +#define R_AX_USB_BT_BRIDGE 0x11A8 +#define B_AX_R_DIS_BTBRI_SS_SYSON BIT(2) +#define B_AX_R_DIS_BTBRI_SS_STS BIT(1) +#define B_AX_R_DIS_BTBRI_L1U2_STS BIT(0) + +#define R_AX_USB_DMA_WRAPPER 0x11B0 +#define B_AX_PKT_BASE_EN BIT(11) +#define B_AX_FUNCTION_SUSB_OPT BIT(8) +#define B_AX_TX7LEN_MISMATCH BIT(7) +#define B_AX_TX6LEN_MISMATCH BIT(6) +#define B_AX_TX5LEN_MISMATCH BIT(5) +#define B_AX_TX4LEN_MISMATCH BIT(4) +#define B_AX_TX3LEN_MISMATCH BIT(3) +#define B_AX_TX2LEN_MISMATCH BIT(2) +#define B_AX_TX1LEN_MISMATCH BIT(1) +#define B_AX_TX0LEN_MISMATCH BIT(0) + +#define R_AX_USB_WLAN1 0x11B8 +#define B_AX_WLAN_TX BIT(12) +#define B_AX_WLAN_RX BIT(11) +#define B_AX_WLAN1_TXQ_STALL_DIS BIT(10) +#define B_AX_WLAN1_RXQ_STOP_SH 8 +#define B_AX_WLAN1_RXQ_STOP_MSK 0x3 +#define B_AX_WLAN1_TXQ_STOP_SH 4 +#define B_AX_WLAN1_TXQ_STOP_MSK 0xf +#define B_AX_FUNCTION_SUSB_EN_WLAN1 BIT(3) +#define B_AX_LOWPOWER_WLAN1 BIT(2) +#define B_AX_FUNCTION_WAKE_EN_WLAN1 BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN1 BIT(0) + +#define R_AX_USB_GPS 0x11C0 +#define B_AX_FUNCTION_SUSB_EN_GPS BIT(3) +#define B_AX_LOWPOWER_GPS BIT(2) +#define B_AX_FUNCTION_WAKE_EN_GPS BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_GPS BIT(0) + +#define R_AX_USB_DEBUG_0 0x11D0 +#define B_AX_SLEEP_GNT_BT BIT(17) +#define B_AX_SLEEP_REQ_BT BIT(16) +#define B_AX_DEBUG_SIGNAL_001_SH 8 +#define B_AX_DEBUG_SIGNAL_001_MSK 0xff +#define B_AX_USB_DBGO_SEL_SH 0 +#define B_AX_USB_DBGO_SEL_MSK 0xff + +#define R_AX_USB_DEBUG_1 0x11D4 +#define B_AX_RXDMA_ENDPOINT_COUNTER_SH 24 +#define B_AX_RXDMA_ENDPOINT_COUNTER_MSK 0xff +#define B_AX_RXDMA_DMA_COUNTER_SH 16 +#define B_AX_RXDMA_DMA_COUNTER_MSK 0xff +#define B_AX_TXDMA_ENDPOINT_COUNTER_SH 8 +#define B_AX_TXDMA_ENDPOINT_COUNTER_MSK 0xff +#define B_AX_TXDMA_DMA_COUNTER_SH 0 +#define B_AX_TXDMA_DMA_COUNTER_MSK 0xff + +#define R_AX_USB_DEBUG_2 0x11D8 +#define B_AX_REGISTER_READ_COUNTER_SH 8 +#define B_AX_REGISTER_READ_COUNTER_MSK 0xff +#define B_AX_REGISTER_WRITE_COUNTER_SH 0 +#define B_AX_REGISTER_WRITE_COUNTER_MSK 0xff + +#define R_AX_USB_DEBUG_3 0x11DC +#define B_AX_RX_PATH_STATE_MACHINE_SH 24 +#define B_AX_RX_PATH_STATE_MACHINE_MSK 0xff +#define B_AX_TX_PATH_STATE_MACHINE_SH 16 +#define B_AX_TX_PATH_STATE_MACHINE_MSK 0xff +#define B_AX_IO_PATH_STATE_MACHINE_SH 8 +#define B_AX_IO_PATH_STATE_MACHINE_MSK 0xffffff +#define B_AX_TXVLD_TOGGLE_VAL_SH 8 +#define B_AX_TXVLD_TOGGLE_VAL_MSK 0xf +#define B_AX_TXVLD_TOUT_VAL_SH 0 +#define B_AX_TXVLD_TOUT_VAL_MSK 0xff + +#define R_AX_USB_STATUS 0x11F0 +#define B_AX_USB_EP_NUM_SH 4 +#define B_AX_USB_EP_NUM_MSK 0xf +#define B_AX_R_SSIC_EN BIT(2) +#define B_AX_R_USB2_SEL BIT(1) +#define B_AX_MODE_HS BIT(0) + +#define R_AX_USB_D2F_F2D_INFO 0x1200 +#define B_AX_HRPWM2_SH 16 +#define B_AX_HRPWM2_MSK 0xffff +#define B_AX_CPWM2_SH 0 +#define B_AX_CPWM2_MSK 0xffff + +#define R_AX_USB3 0x1220 +#define B_AX_U3_STATE_SH 12 +#define B_AX_U3_STATE_MSK 0xf +#define B_AX_U3_SUB_STATE_SH 8 +#define B_AX_U3_SUB_STATE_MSK 0xf +#define B_AX_HPS_CLKR_USB_SH 0 +#define B_AX_HPS_CLKR_USB_MSK 0xff + +#define R_AX_USB_OTHERS_0 0x1230 +#define B_AX_USBTX_EP3IF_OK_CNT_SH 24 +#define B_AX_USBTX_EP3IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP2IF_OK_CNT_SH 16 +#define B_AX_USBTX_EP2IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP1IF_OK_CNT_SH 8 +#define B_AX_USBTX_EP1IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP0IF_OK_CNT_SH 0 +#define B_AX_USBTX_EP0IF_OK_CNT_MSK 0xff + +#define R_AX_USB_OTHERS_1 0x1234 +#define B_AX_USBTX_EP7IF_OK_CNT_SH 24 +#define B_AX_USBTX_EP7IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP6IF_OK_CNT_SH 16 +#define B_AX_USBTX_EP6IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP5IF_OK_CNT_SH 8 +#define B_AX_USBTX_EP5IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP4IF_OK_CNT_SH 0 +#define B_AX_USBTX_EP4IF_OK_CNT_MSK 0xff + +#define R_AX_USB_OTHERS_2 0x1238 +#define B_AX_USBRX_DMAIF_OK_CNT_SH 24 +#define B_AX_USBRX_DMAIF_OK_CNT_MSK 0xff +#define B_AX_USBRX_EPIF_OK_CNT_SH 16 +#define B_AX_USBRX_EPIF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP9IF_OK_CNT_SH 8 +#define B_AX_USBTX_EP9IF_OK_CNT_MSK 0xff +#define B_AX_USBTX_EP8IF_OK_CNT_SH 0 +#define B_AX_USBTX_EP8IF_OK_CNT_MSK 0xff + +#define R_AX_USB_OTHERS_3 0x123C +#define B_AX_VENDOR_LMP_LATCH_DATA_L_SH 0 +#define B_AX_VENDOR_LMP_LATCH_DATA_L_MSK 0xffffffffL + +#define R_AX_USB_OTHERS_4 0x1240 +#define B_AX_VENDOR_LMP_LATCH_DATA_H_SH 0 +#define B_AX_VENDOR_LMP_LATCH_DATA_H_MSK 0xffffffffL + +#define R_AX_USB_OTHERS_5 0x1244 +#define B_AX_APPEND_ZERO_PKT_SH 24 +#define B_AX_APPEND_ZERO_PKT_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_7_SH 21 +#define B_AX_USB_AUTO_LOAD_EXTE_7_MSK 0x3 +#define B_AX_USB_AUTO_LOAD_EXTE_0_SH 16 +#define B_AX_USB_AUTO_LOAD_EXTE_0_MSK 0x1f +#define B_AX_USB_AUTO_LOAD_EXTE_2_SH 8 +#define B_AX_USB_AUTO_LOAD_EXTE_2_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_1_SH 0 +#define B_AX_USB_AUTO_LOAD_EXTE_1_MSK 0xff + +#define R_AX_USB_OTHERS_6 0x1248 +#define B_AX_USB_AUTO_LOAD_STRING_3_SH 24 +#define B_AX_USB_AUTO_LOAD_STRING_3_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_2_SH 16 +#define B_AX_USB_AUTO_LOAD_STRING_2_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_1_SH 8 +#define B_AX_USB_AUTO_LOAD_STRING_1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_0_SH 0 +#define B_AX_USB_AUTO_LOAD_STRING_0_MSK 0xff + +#define R_AX_USB_OTHERS_7 0x124C +#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_SH 22 +#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_SH 14 +#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_FLAG BIT(13) +#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_SH 7 +#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_MSK 0x3f +#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_SH 0 +#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_MSK 0x7f + +#define R_AX_USB_WATCHDOG 0x1260 +#define B_AX_USBIO_WD_FLAG BIT(31) +#define B_AX_USBIO_WD_EN BIT(30) +#define B_AX_USBIO_WD_TIMER_SH 24 +#define B_AX_USBIO_WD_TIMER_MSK 0xf +#define B_AX_USBIO_WD_ADDR_SH 0 +#define B_AX_USBIO_WD_ADDR_MSK 0xffffff + +#define R_AX_HUSBIMR 0x1270 +#define B_AX_HD1ISR_B00_IND_INT_EN BIT(26) +#define B_AX_USBRX_INT_EN BIT(7) +#define B_AX_PUSBTX_CH12_INT_EN BIT(6) +#define B_AX_USBTX_CH10_INT_EN BIT(5) +#define B_AX_USBTX_CH8_INT_EN BIT(4) +#define B_AX_USBTX_ACH6_INT_EN BIT(3) +#define B_AX_USBTX_ACH4_INT_EN BIT(2) +#define B_AX_USBTX_ACH2_INT_EN BIT(1) +#define B_AX_USBTX_ACH0_INT_EN BIT(0) + +#define R_AX_HUSBISR 0x1274 +#define B_AX_HD1ISR_B00_IND_INT BIT(26) +#define B_AX_USBRX_INT BIT(7) +#define B_AX_PUSBTX_CH12_INT BIT(6) +#define B_AX_USBTX_CH10_INT BIT(5) +#define B_AX_USBTX_CH8_INT BIT(4) +#define B_AX_USBTX_ACH6_INT BIT(3) +#define B_AX_USBTX_ACH4_INT BIT(2) +#define B_AX_USBTX_ACH2_INT BIT(1) +#define B_AX_USBTX_ACH0_INT BIT(0) + +// +// WL_AX_Reg_USB.xls +// + +// +// 8852C USB_REG +// + +#define R_AX_USB2_MAC_0_V1 0x5000 +#define B_AX_TOUT_DELAY_FS_V1_SH 24 +#define B_AX_TOUT_DELAY_FS_V1_MSK 0xff +#define B_AX_TOUT_DELAY_HS_V1_SH 16 +#define B_AX_TOUT_DELAY_HS_V1_MSK 0xff +#define B_AX_TOUT_DIS_V1 BIT(15) +#define B_AX_CRC_CHK_OPT_V1 BIT(14) +#define B_AX_FORCE_PCERST_V1 BIT(13) +#define B_AX_FORCE_TOGL_V1 BIT(12) +#define B_AX_FORCE_TOGLSEL_V1 BIT(11) +#define B_AX_FORCE_PIDSW_V1 BIT(10) +#define B_AX_FORCE_PCE_IN_V1 BIT(9) +#define B_AX_FORCE_PCE_OUT_V1 BIT(8) +#define B_AX_PID_FORCE_V1_SH 0 +#define B_AX_PID_FORCE_V1_MSK 0xff + +#define R_AX_USB2_MAC_1_V1 0x5004 +#define B_AX_FORCE_PCE_CMD_V1 BIT(31) + +#define R_AX_USB2_LINK_PORT_V1 0x5008 +#define B_AX_R_HOST_PWR_CTRL_V1 BIT(23) +#define B_AX_R_USB2_CLR_TXVLD_V1 BIT(22) +#define B_AX_R_USB2_SE0_V1 BIT(21) +#define B_AX_HOST_RESUME_EDGE_EN_V1 BIT(20) +#define B_AX_RESUME_SEL_V1_SH 16 +#define B_AX_RESUME_SEL_V1_MSK 0xf +#define B_AX_DELAY_CHIRP_K_V1_SH 14 +#define B_AX_DELAY_CHIRP_K_V1_MSK 0x3 +#define B_AX_FORCE_TXVLD1_V1 BIT(13) +#define B_AX_FORCE_TXVLD0_V1 BIT(12) +#define B_AX_DORCE_DAT1_V1 BIT(11) +#define B_AX_FORCE_DAT0_V1 BIT(10) +#define B_AX_LS_TEST_V1 BIT(9) +#define B_AX_LS_CHANGE_V1 BIT(8) +#define B_AX_FORCE_HS_SW_V1 BIT(7) +#define B_AX_FORCE_FS_SW_V1 BIT(6) +#define B_AX_FORCE_HSXCVR_V1 BIT(5) +#define B_AX_FORCE_FSXCVR_V1 BIT(4) +#define B_AX_FORCE_HSTERM_V1 BIT(3) +#define B_AX_FORCE_FSTERM_V1 BIT(2) +#define B_AX_FORCE_NORM_SW_V1 BIT(1) +#define B_AX_FORCE_DBSN_V1 BIT(0) + +#define R_AX_USB2_LPM_0_V1 0x5010 +#define B_AX_USBPHY_PLL_ALIVE_V1 BIT(17) +#define B_AX_USB_LPM_MAX_EN_V1 BIT(16) +#define B_AX_USB_LPM_MIN_EN_V1 BIT(15) +#define B_AX_BESL_EN_V1 BIT(14) +#define B_AX_USB_LPM_NYET_EN_V1 BIT(13) +#define B_AX_USB_LPM_MAX_ACK_V1 BIT(12) +#define B_AX_USB_LPM_EN_V1 BIT(11) +#define B_AX_USB2_SUSB_V1 BIT(10) +#define B_AX_LPM_PLL_ALIVE_V1 BIT(9) +#define B_AX_USB_LPS_OUT_V1 BIT(8) +#define B_AX_USB_LPM_WAKEUP_EN_V1 BIT(6) +#define B_AX_NEVER_SUSPEND_V1 BIT(5) +#define B_AX_SUSPND_EN_V1 BIT(4) +#define B_AX_WAKEUP_EN_V1 BIT(3) +#define B_AX_USB_SUS_WAKEUP_EN_V1 BIT(2) +#define B_AX_RESUME_SND_V1 BIT(1) +#define B_AX_CONNECT_EN_V1 BIT(0) + +#define R_AX_USB2_LPM_1_V1 0x5014 +#define B_AX_USB_LPM_MAX_V1_SH 20 +#define B_AX_USB_LPM_MAX_V1_MSK 0xf +#define B_AX_USB_LPM_MIN_V1_SH 16 +#define B_AX_USB_LPM_MIN_V1_MSK 0xf +#define B_AX_R_WAKE_HOST_WT_H_V1_SH 8 +#define B_AX_R_WAKE_HOST_WT_H_V1_MSK 0xff +#define B_AX_R_WAKE_HOST_WT_L_V1_SH 0 +#define B_AX_R_WAKE_HOST_WT_L_V1_MSK 0xff + +#define R_AX_USB2_MACRO_TEST_MODE_V1 0x5018 +#define B_AX_TXRDY_SLB_SEL_V1 BIT(14) +#define B_AX_SLB_EN_V1 BIT(13) +#define B_AX_SLB_RST_V1 BIT(12) +#define B_AX_SLB_FAIL_V1 BIT(11) +#define B_AX_SLB_DONE_V1 BIT(10) +#define B_AX_SLB_PS1_SW_V1_SH 8 +#define B_AX_SLB_PS1_SW_V1_MSK 0x3 +#define B_AX_PHY_LOOP_TEST_V1 BIT(3) +#define B_AX_USBTMOD_V1_SH 0 +#define B_AX_USBTMOD_V1_MSK 0x7 + +#define R_AX_USB2_PHY_REG_0_V1 0x5020 +#define B_AX_USB2PHY_REG_EN_V1 BIT(17) +#define B_AX_VLPADM_V1 BIT(16) +#define B_AX_VSTATUS_IN_V1_SH 8 +#define B_AX_VSTATUS_IN_V1_MSK 0xff +#define B_AX_VCONTROL_V1_SH 0 +#define B_AX_VCONTROL_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_1_V1 0x5024 +#define B_AX_USB2PHY_DELAY_V1_SH 8 +#define B_AX_USB2PHY_DELAY_V1_MSK 0xff +#define B_AX_VSTATUS_OUT_V1_SH 0 +#define B_AX_VSTATUS_OUT_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_2_V1 0x5028 +#define B_AX_USB2_PHY_P0_E3_V1_SH 24 +#define B_AX_USB2_PHY_P0_E3_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E2_V1_SH 16 +#define B_AX_USB2_PHY_P0_E2_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E1_V1_SH 8 +#define B_AX_USB2_PHY_P0_E1_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E0_V1_SH 0 +#define B_AX_USB2_PHY_P0_E0_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_3_V1 0x502C +#define B_AX_USB2_PHY_P0_E7_V1_SH 24 +#define B_AX_USB2_PHY_P0_E7_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E6_V1_SH 16 +#define B_AX_USB2_PHY_P0_E6_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E5_V1_SH 8 +#define B_AX_USB2_PHY_P0_E5_V1_MSK 0xff +#define B_AX_USB2_PHY_P0_E4_V1_SH 0 +#define B_AX_USB2_PHY_P0_E4_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_4_V1 0x5030 +#define B_AX_USB2_PHY_P1_E3_V1_SH 24 +#define B_AX_USB2_PHY_P1_E3_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E2_V1_SH 16 +#define B_AX_USB2_PHY_P1_E2_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E1_V1_SH 8 +#define B_AX_USB2_PHY_P1_E1_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E0_V1_SH 0 +#define B_AX_USB2_PHY_P1_E0_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_5_V1 0x5034 +#define B_AX_USB2_PHY_P1_E7_V1_SH 24 +#define B_AX_USB2_PHY_P1_E7_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E6_V1_SH 16 +#define B_AX_USB2_PHY_P1_E6_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E5_V1_SH 8 +#define B_AX_USB2_PHY_P1_E5_V1_MSK 0xff +#define B_AX_USB2_PHY_P1_E4_V1_SH 0 +#define B_AX_USB2_PHY_P1_E4_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_6_V1 0x5038 +#define B_AX_USB2_PHY_F3_V1_SH 24 +#define B_AX_USB2_PHY_F3_V1_MSK 0xff +#define B_AX_USB2_PHY_F2_V1_SH 16 +#define B_AX_USB2_PHY_F2_V1_MSK 0xff +#define B_AX_USB2_PHY_F1_V1_SH 8 +#define B_AX_USB2_PHY_F1_V1_MSK 0xff +#define B_AX_USB2_PHY_F0_V1_SH 0 +#define B_AX_USB2_PHY_F0_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_7_V1 0x503C +#define B_AX_USB2_PHY_F7_V1_SH 24 +#define B_AX_USB2_PHY_F7_V1_MSK 0xff +#define B_AX_USB2_PHY_F6_V1_SH 16 +#define B_AX_USB2_PHY_F6_V1_MSK 0xff +#define B_AX_USB2_PHY_F5_V1_SH 8 +#define B_AX_USB2_PHY_F5_V1_MSK 0xff +#define B_AX_USB2_PHY_F4_V1_SH 0 +#define B_AX_USB2_PHY_F4_V1_MSK 0xff + +#define R_AX_USB2_PHY_REG_8_V1 0x5040 +#define B_AX_USB2PHY_UPDATE_2_V1_SH 16 +#define B_AX_USB2PHY_UPDATE_2_V1_MSK 0xff +#define B_AX_USB2PHY_UPDATE_1_V1_SH 8 +#define B_AX_USB2PHY_UPDATE_1_V1_MSK 0xff +#define B_AX_USB2PHY_UPDATE_0_V1_SH 0 +#define B_AX_USB2PHY_UPDATE_0_V1_MSK 0xff + +#define R_AX_USB_ENDPOINT_0_V1 0x5060 +#define B_AX_EP_MAXPKT_V1_SH 16 +#define B_AX_EP_MAXPKT_V1_MSK 0x3ff +#define B_AX_EP_EN_V1 BIT(15) +#define B_AX_EP_TYPE_V1_SH 13 +#define B_AX_EP_TYPE_V1_MSK 0x3 +#define B_AX_EP_ISTALL_V1 BIT(12) +#define B_AX_EP_OSTALL_V1 BIT(11) +#define B_AX_EP_STREAMEN_V1 BIT(10) +#define B_AX_EP_OUT_V1 BIT(9) +#define B_AX_EP_IN_V1 BIT(8) +#define B_AX_BT_INTR_SEL_V1 BIT(5) +#define B_AX_R_SIE_INIT_DONE_V1 BIT(4) +#define B_AX_EP_IDX_V1_SH 0 +#define B_AX_EP_IDX_V1_MSK 0xf + +#define R_AX_USB_ENDPOINT_1_V1 0x5064 +#define B_AX_EP_MAX_STREAM_V1_SH 16 +#define B_AX_EP_MAX_STREAM_V1_MSK 0xff +#define B_AX_EP_MAX_BURST_V1_SH 8 +#define B_AX_EP_MAX_BURST_V1_MSK 0xff +#define B_AX_EP_INT_INTERVAL_V1_SH 0 +#define B_AX_EP_INT_INTERVAL_V1_MSK 0xff + +#define R_AX_USB_ENDPOINT_2_V1 0x5068 +#define B_AX_EP_BPI_V1_SH 16 +#define B_AX_EP_BPI_V1_MSK 0xffff +#define B_AX_USB3_EP_IN_ST_V1_SH 8 +#define B_AX_USB3_EP_IN_ST_V1_MSK 0xff +#define B_AX_USB3_EP_OUT_ST_V1_SH 0 +#define B_AX_USB3_EP_OUT_ST_V1_MSK 0xff + +#define R_AX_USB_ENDPOINT_3_V1 0x506C +#define B_AX_EP12_PAUSE_STATE_V1 BIT(31) +#define B_AX_EP11_PAUSE_STATE_V1 BIT(30) +#define B_AX_EP10_PAUSE_STATE_V1 BIT(29) +#define B_AX_EP9_PAUSE_STATE_V1 BIT(28) +#define B_AX_EP8_PAUSE_STATE_V1 BIT(27) +#define B_AX_EP7_PAUSE_STATE_V1 BIT(26) +#define B_AX_EP6_PAUSE_STATE_V1 BIT(25) +#define B_AX_EP5_PAUSE_STATE_V1 BIT(24) +#define B_AX_EP4_PAUSE_STATE_V1 BIT(23) +#define B_AX_EP12_TX_PAUSE_V1 BIT(22) +#define B_AX_EP11_TX_PAUSE_V1 BIT(21) +#define B_AX_EP10_TX_PAUSE_V1 BIT(20) +#define B_AX_EP9_TX_PAUSE_V1 BIT(19) +#define B_AX_EP8_RX_PAUSE_V1 BIT(18) +#define B_AX_EP7_TX_PAUSE_V1 BIT(17) +#define B_AX_EP6_TX_PAUSE_V1 BIT(16) +#define B_AX_EP5_TX_PAUSE_V1 BIT(15) +#define B_AX_EP4_RX_PAUSE_V1 BIT(14) +#define B_AX_INTERRUPT_BULK_IN_V1 BIT(12) +#define B_AX_AC_BULKOUT_V1_SH 10 +#define B_AX_AC_BULKOUT_V1_MSK 0x3 +#define B_AX_BULKOUT1_V1 BIT(9) +#define B_AX_BULKOUT0_V1 BIT(8) +#define B_AX_INTERRUPT_INTERVAL_V1_SH 0 +#define B_AX_INTERRUPT_INTERVAL_V1_MSK 0xf + +#define R_AX_USB_HOST_REQUEST_0_V1 0x5070 +#define B_AX_ERR_STR2_LEN_V1_SH 24 +#define B_AX_ERR_STR2_LEN_V1_MSK 0xff +#define B_AX_ERR_STR1_LEN_V1_SH 8 +#define B_AX_ERR_STR1_LEN_V1_MSK 0xffff +#define B_AX_DEVADDR_V1_SH 0 +#define B_AX_DEVADDR_V1_MSK 0x7f + +#define R_AX_USB_HOST_REQUEST_1_V1 0x5074 +#define B_AX_USB_PID_V1_SH 16 +#define B_AX_USB_PID_V1_MSK 0xffff +#define B_AX_USB_VID_V1_SH 0 +#define B_AX_USB_VID_V1_MSK 0xffff + +#define R_AX_USB_HOST_REQUEST_2_V1 0x5078 +#define B_AX_MAC_ADDR_1_V1_SH 24 +#define B_AX_MAC_ADDR_1_V1_MSK 0xff +#define B_AX_MAC_ADDR_0_V1_SH 16 +#define B_AX_MAC_ADDR_0_V1_MSK 0xff +#define B_AX_FORCE_LPM_BCD201_V1 BIT(15) +#define B_AX_SELF_POWER_EN_V1 BIT(14) +#define B_AX_R_FORCE_U3MAC_HS_MODE_V1 BIT(13) +#define B_AX_LOAD_LTM_CAP_V1 BIT(12) +#define B_AX_USB3_DEV_CAP_DESC_EN_V1 BIT(11) +#define B_AX_AUTOLOAD_STRING_EN_V1 BIT(10) +#define B_AX_REMOTE_WAKEUP_V1 BIT(9) +#define B_AX_SQNUM_ROM_V1 BIT(8) +#define B_AX_ERR_STR2_LEN_FLAG_V1 BIT(7) +#define B_AX_ERR_STR1_LEN_FLAG_V1 BIT(6) +#define B_AX_ERR_STR0_LEN_FLAG_V1 BIT(5) +#define B_AX_R_USBIO_MODE_V1 BIT(4) +#define B_AX_EXREG_TO_EN_V1 BIT(3) +#define B_AX_EXREG_TO_SEL_V1_SH 0 +#define B_AX_EXREG_TO_SEL_V1_MSK 0x7 + +#define R_AX_USB_HOST_REQUEST_3_V1 0x507C +#define B_AX_MAC_ADDR_5_V1_SH 24 +#define B_AX_MAC_ADDR_5_V1_MSK 0xff +#define B_AX_MAC_ADDR_4_V1_SH 16 +#define B_AX_MAC_ADDR_4_V1_MSK 0xff +#define B_AX_MAC_ADDR_3_V1_SH 8 +#define B_AX_MAC_ADDR_3_V1_MSK 0xff +#define B_AX_MAC_ADDR_2_V1_SH 0 +#define B_AX_MAC_ADDR_2_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_4_V1 0x5080 +#define B_AX__MANUFACTURE_STRING_3_V1_SH 24 +#define B_AX__MANUFACTURE_STRING_3_V1_MSK 0xff +#define B_AX__MANUFACTURE_STRING_2_V1_SH 16 +#define B_AX__MANUFACTURE_STRING_2_V1_MSK 0xff +#define B_AX__MANUFACTURE_STRING_1_V1_SH 8 +#define B_AX__MANUFACTURE_STRING_1_V1_MSK 0xff +#define B_AX__MANUFACTURE_STRING_0_V1_SH 0 +#define B_AX__MANUFACTURE_STRING_0_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_5_V1 0x5084 +#define B_AX_MANUFACTURE_STRING_7_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_7_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_6_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_6_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_5_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_5_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_4_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_4_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_6_V1 0x5088 +#define B_AX_MANUFACTURE_STRING_B_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_B_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_A_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_A_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_9_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_9_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_8_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_8_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_7_V1 0x508C +#define B_AX_MANUFACTURE_STRING_F_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_F_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_E_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_E_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_D_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_D_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_C_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_8_V1 0x5090 +#define B_AX_MANUFACTURE_STRING_13_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_13_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_12_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_12_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_11_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_11_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_10_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_10_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_9_V1 0x5094 +#define B_AX_MANUFACTURE_STRING_17_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_17_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_16_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_16_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_15_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_15_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_14_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_14_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_A_V1 0x5098 +#define B_AX_MANUFACTURE_STRING_1B_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_1B_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1A_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_1A_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_19_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_19_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_18_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_18_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_B_V1 0x509C +#define B_AX_MANUFACTURE_STRING_1F_V1_SH 24 +#define B_AX_MANUFACTURE_STRING_1F_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1E_V1_SH 16 +#define B_AX_MANUFACTURE_STRING_1E_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1D_V1_SH 8 +#define B_AX_MANUFACTURE_STRING_1D_V1_MSK 0xff +#define B_AX_MANUFACTURE_STRING_1C_V1_SH 0 +#define B_AX_MANUFACTURE_STRING_1C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_C_V1 0x50A0 +#define B_AX_PRODUCT_STRING_3_V1_SH 24 +#define B_AX_PRODUCT_STRING_3_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_2_V1_SH 16 +#define B_AX_PRODUCT_STRING_2_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_1_V1_SH 8 +#define B_AX_PRODUCT_STRING_1_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_0_V1_SH 0 +#define B_AX_PRODUCT_STRING_0_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_D_V1 0x50A4 +#define B_AX_PRODUCT_STRING_7_V1_SH 24 +#define B_AX_PRODUCT_STRING_7_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_6_V1_SH 16 +#define B_AX_PRODUCT_STRING_6_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_5_V1_SH 8 +#define B_AX_PRODUCT_STRING_5_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_4_V1_SH 0 +#define B_AX_PRODUCT_STRING_4_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_E_V1 0x50A8 +#define B_AX_PRODUCT_STRING_B_V1_SH 24 +#define B_AX_PRODUCT_STRING_B_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_A_V1_SH 16 +#define B_AX_PRODUCT_STRING_A_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_9_V1_SH 8 +#define B_AX_PRODUCT_STRING_9_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_8_V1_SH 0 +#define B_AX_PRODUCT_STRING_8_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_F_V1 0x50AC +#define B_AX_PRODUCT_STRING_F_V1_SH 24 +#define B_AX_PRODUCT_STRING_F_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_E_V1_SH 16 +#define B_AX_PRODUCT_STRING_E_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_D_V1_SH 8 +#define B_AX_PRODUCT_STRING_D_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_C_V1_SH 0 +#define B_AX_PRODUCT_STRING_C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_10_V1 0x50B0 +#define B_AX_PRODUCT_STRING_13_V1_SH 24 +#define B_AX_PRODUCT_STRING_13_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_12_V1_SH 16 +#define B_AX_PRODUCT_STRING_12_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_11_V1_SH 8 +#define B_AX_PRODUCT_STRING_11_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_10_V1_SH 0 +#define B_AX_PRODUCT_STRING_10_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_11_V1 0x50B4 +#define B_AX_PRODUCT_STRING_17_V1_SH 24 +#define B_AX_PRODUCT_STRING_17_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_16_V1_SH 16 +#define B_AX_PRODUCT_STRING_16_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_15_V1_SH 8 +#define B_AX_PRODUCT_STRING_15_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_14_V1_SH 0 +#define B_AX_PRODUCT_STRING_14_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_12_V1 0x50B8 +#define B_AX_PRODUCT_STRING_1B_V1_SH 24 +#define B_AX_PRODUCT_STRING_1B_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_1A_V1_SH 16 +#define B_AX_PRODUCT_STRING_1A_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_19_V1_SH 8 +#define B_AX_PRODUCT_STRING_19_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_18_V1_SH 0 +#define B_AX_PRODUCT_STRING_18_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_13_V1 0x50BC +#define B_AX_PRODUCT_STRING_1F_V1_SH 24 +#define B_AX_PRODUCT_STRING_1F_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_1E_V1_SH 16 +#define B_AX_PRODUCT_STRING_1E_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_1D_V1_SH 8 +#define B_AX_PRODUCT_STRING_1D_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_1C_V1_SH 0 +#define B_AX_PRODUCT_STRING_1C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_14_V1 0x50C0 +#define B_AX_PRODUCT_STRING_23_V1_SH 24 +#define B_AX_PRODUCT_STRING_23_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_22_V1_SH 16 +#define B_AX_PRODUCT_STRING_22_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_21_V1_SH 8 +#define B_AX_PRODUCT_STRING_21_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_20_V1_SH 0 +#define B_AX_PRODUCT_STRING_20_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_15_V1 0x50C4 +#define B_AX_PRODUCT_STRING_27_V1_SH 24 +#define B_AX_PRODUCT_STRING_27_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_26_V1_SH 16 +#define B_AX_PRODUCT_STRING_26_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_25_V1_SH 8 +#define B_AX_PRODUCT_STRING_25_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_24_V1_SH 0 +#define B_AX_PRODUCT_STRING_24_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_16_V1 0x50C8 +#define B_AX_PRODUCT_STRING_2B_V1_SH 24 +#define B_AX_PRODUCT_STRING_2B_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_2A_V1_SH 16 +#define B_AX_PRODUCT_STRING_2A_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_29_V1_SH 8 +#define B_AX_PRODUCT_STRING_29_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_28_V1_SH 0 +#define B_AX_PRODUCT_STRING_28_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_17_V1 0x50CC +#define B_AX_PRODUCT_STRING_2F_V1_SH 24 +#define B_AX_PRODUCT_STRING_2F_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_2E_V1_SH 16 +#define B_AX_PRODUCT_STRING_2E_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_2D_V1_SH 8 +#define B_AX_PRODUCT_STRING_2D_V1_MSK 0xff +#define B_AX_PRODUCT_STRING_2C_V1_SH 0 +#define B_AX_PRODUCT_STRING_2C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_18_V1 0x50D0 +#define B_AX_SERIAL_NUMBER_STRING_3_V1_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_3_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_2_V1_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_2_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_1_V1_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_1_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_0_V1_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_0_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_19_V1 0x50D4 +#define B_AX_SERIAL_NUMBER_STRING_7_V1_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_7_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_6_V1_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_6_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_5_V1_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_5_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_4_V1_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_4_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1A_V1 0x50D8 +#define B_AX_SERIAL_NUMBER_STRING_B_V1_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_B_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_A_V1_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_A_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_9_V1_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_9_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_8_V1_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_8_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1B_V1 0x50DC +#define B_AX_SERIAL_NUMBER_STRING_F_V1_SH 24 +#define B_AX_SERIAL_NUMBER_STRING_F_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_E_V1_SH 16 +#define B_AX_SERIAL_NUMBER_STRING_E_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_D_V1_SH 8 +#define B_AX_SERIAL_NUMBER_STRING_D_V1_MSK 0xff +#define B_AX_SERIAL_NUMBER_STRING_C_V1_SH 0 +#define B_AX_SERIAL_NUMBER_STRING_C_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1C_V1 0x50E0 +#define B_AX_USB3_U2SEL_V1_SH 16 +#define B_AX_USB3_U2SEL_V1_MSK 0xffff +#define B_AX_USB3_U1PEL_V1_SH 0 +#define B_AX_USB3_U1PEL_V1_MSK 0xffff + +#define R_AX_USB_HOST_REQUEST_1D_V1 0x50E4 +#define B_AX_HW_VENDOR_INDEX_V1_SH 16 +#define B_AX_HW_VENDOR_INDEX_V1_MSK 0xff + +#define R_AX_USB_HOST_REQUEST_1E_V1 0x50E8 +#define B_AX_DIS_STALL_FUNC_WAKE_V1 BIT(24) +#define B_AX_USB3_U2_DEV_EXIT_LAT_V1_SH 8 +#define B_AX_USB3_U2_DEV_EXIT_LAT_V1_MSK 0xffff +#define B_AX_USB3_U1_DEV_EXIT_LAT_V1_SH 0 +#define B_AX_USB3_U1_DEV_EXIT_LAT_V1_MSK 0xff + +#define R_AX_USB3_MAC_LINK_0_V1 0x5100 +#define B_AX_INTS_USB3_HRESET_EN_V1 BIT(31) +#define B_AX_INTS_USB3_RECOV_EN_V1 BIT(30) +#define B_AX_INTS_USB3_LPBK_EN_V1 BIT(29) +#define B_AX_INTS_USB3_RXDET_EN_V1 BIT(28) +#define B_AX_INTS_USB3_POLL_EN_V1 BIT(27) +#define B_AX_INTS_USB3_U3_EN_V1 BIT(26) +#define B_AX_INTS_USB3_U1U2_EN_V1 BIT(25) +#define B_AX_INTS_USB3_U0_EN_V1 BIT(24) +#define B_AX_INTS_USB3_RECOV2U0_EN_V1 BIT(23) +#define B_AX_INTS_USB3_SSINACT_EN_V1 BIT(22) +#define B_AX_INTS_USB3_SSDIS_EN_V1 BIT(21) +#define B_AX_INTS_USB3_CMPLY_EN_V1 BIT(20) +#define B_AX_INTS_USB3_RECOV2U0_V1 BIT(19) +#define B_AX_INTS_USB3_SSINACT_V1 BIT(18) +#define B_AX_INTS_USB3_SSDIS_V1 BIT(17) +#define B_AX_INTS_USB3_CMPLY_V1 BIT(16) +#define B_AX_INTS_USB3_HRESET_V1 BIT(15) +#define B_AX_INTS_USB3_RECOV_V1 BIT(14) +#define B_AX_INTS_USB3_LPBK_V1 BIT(13) +#define B_AX_INTS_USB3_RXDET_V1 BIT(12) +#define B_AX_INTS_USB3_POLL_V1 BIT(11) +#define B_AX_INTS_USB3_U3_V1 BIT(10) +#define B_AX_INTS_USB3_U1U2_V1 BIT(9) +#define B_AX_INTS_USB3_U0_V1 BIT(8) +#define B_AX_EN_ROVIDLE_TIMEOUT_V1 BIT(6) +#define B_AX_EN_UNFIN_RTY_V1 BIT(5) +#define B_AX_SSPHY_U1_QUICK_LFPS_V1 BIT(4) +#define B_AX_USB3_DIS_ISOC_TIME_GT_V1 BIT(3) +#define B_AX_R_DIS_USB3_U2_EN_V1 BIT(2) +#define B_AX_R_DIS_USB3_U1_EN_V1 BIT(1) +#define B_AX_LINK_ST_DETECT_TERM_V1 BIT(0) + +#define R_AX_USB3_MAC_LINK_1_V1 0x5104 +#define B_AX_WARM_RESET_TIME_V1_SH 0 +#define B_AX_WARM_RESET_TIME_V1_MSK 0x3 + +#define R_AX_USB3_MAC_PIU_V1 0x5108 +#define B_AX_SSPHY_CLR_TERM_V1 BIT(1) +#define B_AX_SSPHY_SET_TERM_V1 BIT(0) + +#define R_AX_USB3_MAC_PTL_V1 0x510C +#define B_AX_BCDVALUE_V1_SH 2 +#define B_AX_BCDVALUE_V1_MSK 0x3 +#define B_AX_WLAN0_BUF_NUMP_EN_V1 BIT(1) +#define B_AX_IGNORE_RETRY_BIT_V1 BIT(0) + +#define R_AX_USB3_MAC_PRTSM_V1 0x5110 +#define B_AX_EN_IMMED_POP_CREDIT_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1 0x5114 +#define B_AX_SSPHY_LFPS_FILTER_V1 BIT(31) +#define B_AX_SSPHY_TX_SWING_V1 BIT(30) +#define B_AX_SSPHY_TXMARGIN_V1_SH 27 +#define B_AX_SSPHY_TXMARGIN_V1_MSK 0x7 +#define B_AX_SSPHY_TXDEEMPHASIS_V1_SH 25 +#define B_AX_SSPHY_TXDEEMPHASIS_V1_MSK 0x3 +#define B_AX_SSPHY_ELASTIC_BUF_V1 BIT(24) +#define B_AX_HIRD_THR_V1_SH 19 +#define B_AX_HIRD_THR_V1_MSK 0x1f +#define B_AX_DEV_SPEED_V1_SH 16 +#define B_AX_DEV_SPEED_V1_MSK 0x7 +#define B_AX_U1_ACTIVE_TIMEOUT_V1_SH 8 +#define B_AX_U1_ACTIVE_TIMEOUT_V1_MSK 0xff +#define B_AX_USB3_TARGET_LINK_STATE_V1_SH 4 +#define B_AX_USB3_TARGET_LINK_STATE_V1_MSK 0xf +#define B_AX_APPL1RSP_V1 BIT(3) +#define B_AX_LPM_CAPABLE_V1 BIT(2) +#define B_AX_USB3_EOF_V1_SH 0 +#define B_AX_USB3_EOF_V1_MSK 0x3 + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_1_V1 0x5118 +#define B_AX_NPI_SCALEDOWN_MODE_V1_SH 24 +#define B_AX_NPI_SCALEDOWN_MODE_V1_MSK 0x3 +#define B_AX_SSPHY_POWERDOWN_SCALE_V1_SH 8 +#define B_AX_SSPHY_POWERDOWN_SCALE_V1_MSK 0x1fff +#define B_AX_SSPHY_U1_FAST_OUT_V1 BIT(7) +#define B_AX_SSPHY_P3_FOR_P2_V1 BIT(6) +#define B_AX_SSPHY_U1_RXVALID_V1 BIT(5) +#define B_AX_SSPHY_DIS_SCAMBLE_V1 BIT(4) +#define B_AX_SSPHY_SKIP_RXDETECT_V1 BIT(3) +#define B_AX_SSPHY_LFPS_P0_ALIGN_V1 BIT(2) +#define B_AX_SSPHY_P3P2_TRANS_V1 BIT(1) +#define B_AX_SSPHY_P3_EXITIN_P2_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_CONFIG_INTF_2_V1 0x511C +#define B_AX_SSPHY_U2EXIT_LPFS_V1 BIT(18) +#define B_AX_SSPHY_PHYSOFTRST_V1 BIT(17) +#define B_AX_SSPHY_HSTPRTCMPL_V1 BIT(16) +#define B_AX_SSPHY_U2SSINACTP3OK_V1 BIT(15) +#define B_AX_SSPHY_DISRXDETP3_V1 BIT(14) +#define B_AX_SSPHY_UX_EXIT_IN_PX_V1 BIT(13) +#define B_AX_SSPHY_PING_ENH_EN_V1 BIT(12) +#define B_AX_SSPHY_U1U2EXITFAIL_TO_RECOV_V1 BIT(11) +#define B_AX_SSPHY_ALWAYS_REQ_V1 BIT(10) +#define B_AX_SSPHY_START_RX_DET_V1 BIT(9) +#define B_AX_SSPHY_DIS_RX_DET_V1 BIT(8) +#define B_AX_SSPHY_DELAY_P1P2P3_V1_SH 5 +#define B_AX_SSPHY_DELAY_P1P2P3_V1_MSK 0x7 +#define B_AX_SSPHY_SUSPEND_EN_V1 BIT(4) +#define B_AX_SSPHY_DATWIDTH_V1_SH 2 +#define B_AX_SSPHY_DATWIDTH_V1_MSK 0x3 +#define B_AX_SSPHY_ABORTRXDETLNU2_V1 BIT(1) +#define B_AX_SSPHY_RX_DETECT_LPFS_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_0_V1 0x5120 +#define B_AX_U3_LTM_EN_V1 BIT(28) +#define B_AX_LINK_STATE_REQ_V1_SH 24 +#define B_AX_LINK_STATE_REQ_V1_MSK 0xf +#define B_AX_SUSCLK_RATIO_V1_SH 8 +#define B_AX_SUSCLK_RATIO_V1_MSK 0x1fff +#define B_AX_TEST_CTRL_V1_SH 4 +#define B_AX_TEST_CTRL_V1_MSK 0xf +#define B_AX_UFRAME_SCALE_V1_SH 2 +#define B_AX_UFRAME_SCALE_V1_MSK 0x3 +#define B_AX_LOCAL_LBK_V1 BIT(1) +#define B_AX_EN_SLEEP_USB_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_1_V1 0x5124 +#define B_AX_WAKE_WAIT_XTAL_V1 BIT(27) +#define B_AX_WAKE_WAIT_CURRENT_V1 BIT(26) +#define B_AX_WAKEUP_NEG_SEL_V1 BIT(25) +#define B_AX_SSPHY_USB3_ATTEMPT_V1 BIT(24) +#define B_AX_WAIT_IDLE_TIME_V1_SH 20 +#define B_AX_WAIT_IDLE_TIME_V1_MSK 0xf +#define B_AX_U2_EN_MAC_IDLE_V1 BIT(18) +#define B_AX_U1_EN_MAC_IDLE_V1 BIT(17) +#define B_AX_SWITCH_CLK_EN_V1 BIT(16) +#define B_AX_USB3_SAMPLE_RXELECIDLE_V1_SH 8 +#define B_AX_USB3_SAMPLE_RXELECIDLE_V1_MSK 0xff +#define B_AX_U3_INIT_U2_V1 BIT(7) +#define B_AX_U3_INIT_U1_V1 BIT(6) +#define B_AX_SET_U3_WAKE_V1 BIT(5) +#define B_AX_U3_U2_EN_V1 BIT(4) +#define B_AX_U3_U1_EN_V1 BIT(3) +#define B_AX_U3_INIT_U2_EN_V1 BIT(2) +#define B_AX_U3_INIT_U1_EN_V1 BIT(1) +#define B_AX_USB3_RUN_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_POWER_2_V1 0x5128 +#define B_AX_NPI_LINK_STATE_LATCH_V1_SH 16 +#define B_AX_NPI_LINK_STATE_LATCH_V1_MSK 0xff +#define B_AX_NPI_HOST_RESUME_DETECTED_V1 BIT(15) +#define B_AX_NPI_DEV_CONNECT_SPEED_V1_SH 12 +#define B_AX_NPI_DEV_CONNECT_SPEED_V1_MSK 0x7 +#define B_AX_NPI_LINK_STATE_V1_SH 8 +#define B_AX_NPI_LINK_STATE_V1_MSK 0xf +#define B_AX_POLL_EN_V1 BIT(7) +#define B_AX_POLL_SAMPLE_ON_V1 BIT(6) +#define B_AX_POLL_ACT_V1_SH 4 +#define B_AX_POLL_ACT_V1_MSK 0x3 +#define B_AX_POLL_NOACT_V1_SH 0 +#define B_AX_POLL_NOACT_V1_MSK 0xf + +#define R_AX_USB3_MAC_NPI_POWER_3_V1 0x512C +#define B_AX_R_CNT_SWITCH_USB32_PARA_V1_SH 0 +#define B_AX_R_CNT_SWITCH_USB32_PARA_V1_MSK 0xffff + +#define R_AX_USB3_MAC_NPI_STATUS_V1 0x5130 +#define B_AX_NPI_DEV_CONNECTED_V1 BIT(0) + +#define R_AX_USB3_MAC_NPI_DEVICE_NOTIFICATION_V1 0x5134 +#define B_AX_DEVNOTE_BIA_V1_SH 16 +#define B_AX_DEVNOTE_BIA_V1_MSK 0xffff +#define B_AX_DEVNOTE_BELT_V1_SH 0 +#define B_AX_DEVNOTE_BELT_V1_MSK 0xfff + +#define R_AX_USB3_MAC_NPI_TRANSMIT_V1 0x5138 +#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_V1_SH 0 +#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_V1_MSK 0xf + +#define R_AX_USB3_MAC_NPI_OTHERS_V1 0x513C +#define B_AX_EN_FIX_RX_ABORT_V1 BIT(8) +#define B_AX_FLADJ_30MHZ_REG_V1_SH 0 +#define B_AX_FLADJ_30MHZ_REG_V1_MSK 0x3f + +#define R_AX_USB3_WRAP_0_V1 0x5140 +#define B_AX_U1TOU2_TIMER_V1_SH 24 +#define B_AX_U1TOU2_TIMER_V1_MSK 0xff +#define B_AX_WAKE_ST_DBG_V1_SH 20 +#define B_AX_WAKE_ST_DBG_V1_MSK 0xf +#define B_AX_ARB_ST_DBG_V1_SH 18 +#define B_AX_ARB_ST_DBG_V1_MSK 0x3 +#define B_AX_BIA_REQ_V1 BIT(17) +#define B_AX_BELT_REQ_V1 BIT(16) +#define B_AX_USB3_VENDOR_LEN_TH_V1_SH 0 +#define B_AX_USB3_VENDOR_LEN_TH_V1_MSK 0xffff + +#define R_AX_USB3_WRAP_1_V1 0x5144 +#define B_AX_DIS_PKT_FUNC_WAKE_V1 BIT(0) + +#define R_AX_USB3_PHY_V1 0x5148 +#define B_AX_USB3_PHY_RWDATA_V1_SH 16 +#define B_AX_USB3_PHY_RWDATA_V1_MSK 0xffff +#define B_AX_USB3_PHY_ADR_V1_SH 8 +#define B_AX_USB3_PHY_ADR_V1_MSK 0x1f +#define B_AX_USB3_PHY_REG_WRFLAG_V1 BIT(7) +#define B_AX_USB3_PHY_REG_RDFLAG_V1 BIT(6) +#define B_AX_USB3_PHY_REG_ADR_V1_SH 0 +#define B_AX_USB3_PHY_REG_ADR_V1_MSK 0x1f + +#define R_AX_USB3_OTHERS_V1 0x5150 +#define B_AX_R_REATTACH_TIMER_V1_SH 28 +#define B_AX_R_REATTACH_TIMER_V1_MSK 0xf +#define B_AX_R_CNT_MS_SEL_V1_SH 24 +#define B_AX_R_CNT_MS_SEL_V1_MSK 0x7 +#define B_AX_VENDOR_LPM_TEST_V1_SH 16 +#define B_AX_VENDOR_LPM_TEST_V1_MSK 0xff +#define B_AX_ISOC_DELAY_VALUE_V1_SH 0 +#define B_AX_ISOC_DELAY_VALUE_V1_MSK 0xffff + +#define R_AX_USB_APPLICATION_BT_0_V1 0x5160 +#define B_AX_BTRX0_BUFFER_WADDR_V1_SH 24 +#define B_AX_BTRX0_BUFFER_WADDR_V1_MSK 0xff +#define B_AX_USB_INTOKEN_TIMEOUT_V1_SH 20 +#define B_AX_USB_INTOKEN_TIMEOUT_V1_MSK 0x7 +#define B_AX_BRX_BUF_CHK_V1_SH 16 +#define B_AX_BRX_BUF_CHK_V1_MSK 0x7 +#define B_AX_BTRX0_RPKT_SIZE_V1_SH 0 +#define B_AX_BTRX0_RPKT_SIZE_V1_MSK 0xffff + +#define R_AX_USB_APPLICATION_BT_1_V1 0x5164 +#define B_AX_USB2BT_PWR_INFO_REG_MASK_V1_SH 20 +#define B_AX_USB2BT_PWR_INFO_REG_MASK_V1_MSK 0xf +#define B_AX_FUNCTION_SUSB_EN_BT_V1 BIT(19) +#define B_AX_LOWPOWER_BT_V1 BIT(18) +#define B_AX_FUNCTION_WAKE_EN_BT_V1 BIT(17) +#define B_AX_FUNCTION_WAKE_CAPABLE_BT_V1 BIT(16) +#define B_AX_BT_ISO_ZERO_EN_V1 BIT(14) +#define B_AX_R_RXDMA_MODE_V1_SH 12 +#define B_AX_R_RXDMA_MODE_V1_MSK 0x3 +#define B_AX_GPS_USB_ACTIVE_V1 BIT(11) +#define B_AX_BT_TXQ_STOP_V1_SH 8 +#define B_AX_BT_TXQ_STOP_V1_MSK 0x7 + +#define R_AX_USB_APPLICATION_BT_2_V1 0x5168 +#define B_AX_BT_TX_V1 BIT(17) +#define B_AX_BT_RX_V1 BIT(16) +#define B_AX_BTTX_FIFO_OVER_EP3_V1 BIT(13) +#define B_AX_BTTX_FIFO_OVER_EP2_V1 BIT(12) +#define B_AX_BTTX_FIFO_OVER_EP0_V1 BIT(11) +#define B_AX_BTRX_FIFO_OVER_EP3_V1 BIT(10) +#define B_AX_BTRX_FIFO_OVER_EP2_V1 BIT(9) +#define B_AX_BTRX_FIFO_OVER_EP1_V1 BIT(8) +#define B_AX_BTTX_FIFO_UNDR_EP3_V1 BIT(5) +#define B_AX_BTTX_FIFO_UNDR_EP2_V1 BIT(4) +#define B_AX_BTTX_FIFO_UNDR_EP0_V1 BIT(3) +#define B_AX_BTRX_FIFO_UNDR_EP3_V1 BIT(2) +#define B_AX_BTRX_FIFO_UNDR_EP2_V1 BIT(1) +#define B_AX_BTRX_FIFO_UNDR_EP1_V1 BIT(0) + +#define R_AX_USB_APPLICATION_BT_3_V1 0x516C +#define B_AX_DBG_BTRX_WADDR_V1_SH 16 +#define B_AX_DBG_BTRX_WADDR_V1_MSK 0xfff +#define B_AX_DBG_BTRX_RPKT_V1_SH 0 +#define B_AX_DBG_BTRX_RPKT_V1_MSK 0xffff + +#define R_AX_USB_WLAN0_0_V1 0x5170 +#define B_AX_WLAN_INT_LEN_V1_SH 16 +#define B_AX_WLAN_INT_LEN_V1_MSK 0xffff +#define B_AX_WLAN0_TXQ_STALL_DIS_V1 BIT(4) +#define B_AX_FUNCTION_SUSB_EN_WLAN0_V1 BIT(3) +#define B_AX_LOWPOWER_WLAN0_V1 BIT(2) +#define B_AX_FUNCTION_WAKE_EN_WLAN0_V1 BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN0_V1 BIT(0) + +#define R_AX_USB_WLAN0_1_V1 0x5174 +#define B_AX_USBRX_RST_V1 BIT(9) +#define B_AX_USBTX_RST_V1 BIT(8) +#define B_AX_R_USBRX_SRAM_LS_V1 BIT(7) +#define B_AX_R_USBRX_SRAM_DS_V1 BIT(6) +#define B_AX_R_USBTX_SRAM_LS_V1 BIT(5) +#define B_AX_R_USBTX_SRAM_DS_V1 BIT(4) +#define B_AX_WLRX_FIFO_OVER_V1_SH 2 +#define B_AX_WLRX_FIFO_OVER_V1_MSK 0x3 +#define B_AX_WLRX_FIFO_UNDR_V1_SH 0 +#define B_AX_WLRX_FIFO_UNDR_V1_MSK 0x3 + +#define R_AX_USB_AUTO_INSTALL_0_V1 0x5180 +#define B_AX_AINST_POLL_1_V1 BIT(28) +#define B_AX_AINST_POLL_0_V1 BIT(27) +#define B_AX_AINST_TX1_CLR_BUF_V1 BIT(26) +#define B_AX_AINST_TX0_CLR_BUF_V1 BIT(25) +#define B_AX_WLAN_FW_RDY_V1 BIT(24) +#define B_AX_RECONF_USBEP_V1 BIT(23) +#define B_AX_RECONF_USBEP_EN_V1 BIT(22) +#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_V1 BIT(21) +#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_EN_V1 BIT(20) +#define B_AX_AINST_RXLEN_V1_SH 8 +#define B_AX_AINST_RXLEN_V1_MSK 0xfff +#define B_AX_AINST_RX1_INTR_V1 BIT(7) +#define B_AX_AINST_RX0_INTR_V1 BIT(6) +#define B_AX_AINXT_TX1_INTR_V1 BIT(5) +#define B_AX_AINST_TX0_INTR_V1 BIT(4) +#define B_AX_AUTO_INST_TXQ_STALL_DIS_V1 BIT(3) +#define B_AX_LOWPOWER_AINST_V1 BIT(2) +#define B_AX_FUNCTION_WANE_EN_AINST_V1 BIT(1) + +#define R_AX_USB_AUTO_INSTALL_1_V1 0x5184 +#define B_AX_AINST_TX1LEN_V1_SH 16 +#define B_AX_AINST_TX1LEN_V1_MSK 0xfff +#define B_AX_AINST_TX0LEN_V1_SH 0 +#define B_AX_AINST_TX0LEN_V1_MSK 0xfff + +#define R_AX_USB_AUTO_INSTALL_2_V1 0x5188 +#define B_AX_AINST_PID_V1_SH 16 +#define B_AX_AINST_PID_V1_MSK 0xffff +#define B_AX_AINST_VID_V1_SH 0 +#define B_AX_AINST_VID_V1_MSK 0xffff + +#define R_AX_USB_AUTO_INSTALL_3_V1 0x518C +#define B_AX_AINST_TXSTATUS_V1_SH 8 +#define B_AX_AINST_TXSTATUS_V1_MSK 0xff +#define B_AX_AINST_RXSTATUS_V1_SH 0 +#define B_AX_AINST_RXSTATUS_V1_MSK 0xff + +#define R_AX_USB_BRIDGE_UART_0_V1 0x5190 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_V1_SH 20 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_V1_MSK 0xfff +#define B_AX_BRIDGE_XFACTOR_V1_SH 16 +#define B_AX_BRIDGE_XFACTOR_V1_MSK 0xf +#define B_AX_BRIDGE_BAUD_USB2_V1_SH 0 +#define B_AX_BRIDGE_BAUD_USB2_V1_MSK 0xfff + +#define R_AX_USB_BRIDGE_UART_1_V1 0x5194 +#define B_AX_BRIDGE_WAKEUP_EN_V1_SH 30 +#define B_AX_BRIDGE_WAKEUP_EN_V1_MSK 0x3 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_V1_SH 16 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_V1_MSK 0xfff +#define B_AX_BRIDGE_LE_CON_HAN_VLD_V1 BIT(9) +#define B_AX_BRIDGE_LE_ON_V1 BIT(8) +#define B_AX_BRIDGE_DEBUG_PKTCNT_EN_V1 BIT(6) +#define B_AX_BRIDGE_RESET_RCV_SEL_V1 BIT(5) +#define B_AX_BRIDGE_WLS0_V1 BIT(4) +#define B_AX_BRIDGE_STB_V1 BIT(3) +#define B_AX_BRIDGE_PEN_V1 BIT(2) +#define B_AX_BRIDGE_EPS_V1 BIT(1) +#define B_AX_BRIDGE_STKP_V1 BIT(0) + +#define R_AX_USB_BRIDGE_UART_2_V1 0x5198 +#define B_AX_BRIDGE_DEBUG_SEL_V1_SH 24 +#define B_AX_BRIDGE_DEBUG_SEL_V1_MSK 0xff +#define B_AX_R_BRIDGE_UARTEN_V1 BIT(23) +#define B_AX_BRIDGE_LPM_EN_V1 BIT(22) +#define B_AX_BRIDGE_TXSCO_TIME_INTERVAL_EN_V1 BIT(21) +#define B_AX_BRIDGE_TXSCO_PKT_LEN_MAT_EN_V1 BIT(20) +#define B_AX_BRIDGE_TXSCO_CON_HAN_MAT_EN_V1 BIT(19) +#define B_AX_BRIDGE_USB_TX_HCICMDLEN_SEL_V1 BIT(18) +#define B_AX_R_BRIDGE_JCIRXEN_V1 BIT(17) +#define B_AX_R_BRIDGE_HCITXEN_V1 BIT(16) +#define B_AX_BRIDGE_RXSCOBUF_FLOW_SEL_V1_SH 12 +#define B_AX_BRIDGE_RXSCOBUF_FLOW_SEL_V1_MSK 0xf +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_V1_SH 0 +#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_V1_MSK 0xfff + +#define R_AX_USB_BRIDGE_UART_3_V1 0x519C +#define B_AX_BRIDGE_URT_RXINDIC_ERR_V1 BIT(31) +#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_V1_SH 24 +#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_V1_MSK 0x7f +#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_V1_SH 16 +#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_V1_MSK 0xff +#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_V1_SH 8 +#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_V1_MSK 0xff +#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_V1_SH 0 +#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_V1_MSK 0xff + +#define R_AX_USB_BRIDGE_UART_4_V1 0x51A0 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_V1_SH 20 +#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_V1_MSK 0xfff +#define B_AX_BRIDGE_XFACTOR_USB3_V1_SH 16 +#define B_AX_BRIDGE_XFACTOR_USB3_V1_MSK 0xf +#define B_AX_BRIDGE_BAUD_USB3_V1_SH 0 +#define B_AX_BRIDGE_BAUD_USB3_V1_MSK 0xfff + +#define R_AX_USB_BT_BRIDGE_V1 0x51A8 +#define B_AX_R_DIS_BTBRI_SS_SYSON_V1 BIT(2) +#define B_AX_R_DIS_BTBRI_SS_STS_V1 BIT(1) +#define B_AX_R_DIS_BTBRI_L1U2_STS_V1 BIT(0) + +#define R_AX_USB_DMA_WRAPPER_V1 0x51B0 +#define B_AX_PKT_BASE_EN_V1 BIT(11) +#define B_AX_FUNCTION_SUSB_OPT_V1 BIT(8) +#define B_AX_TX7LEN_MISMATCH_V1 BIT(7) +#define B_AX_TX6LEN_MISMATCH_V1 BIT(6) +#define B_AX_TX5LEN_MISMATCH_V1 BIT(5) +#define B_AX_TX4LEN_MISMATCH_V1 BIT(4) +#define B_AX_TX3LEN_MISMATCH_V1 BIT(3) +#define B_AX_TX2LEN_MISMATCH_V1 BIT(2) +#define B_AX_TX1LEN_MISMATCH_V1 BIT(1) +#define B_AX_TX0LEN_MISMATCH_V1 BIT(0) + +#define R_AX_USB_WLAN1_V1 0x51B8 +#define B_AX_WLAN_TX_V1 BIT(12) +#define B_AX_WLAN_RX_V1 BIT(11) +#define B_AX_WLAN1_TXQ_STALL_DIS_V1 BIT(10) +#define B_AX_WLAN1_RXQ_STOP_V1_SH 8 +#define B_AX_WLAN1_RXQ_STOP_V1_MSK 0x3 +#define B_AX_WLAN1_TXQ_STOP_V1_SH 4 +#define B_AX_WLAN1_TXQ_STOP_V1_MSK 0xf +#define B_AX_FUNCTION_SUSB_EN_WLAN1_V1 BIT(3) +#define B_AX_LOWPOWER_WLAN1_V1 BIT(2) +#define B_AX_FUNCTION_WAKE_EN_WLAN1_V1 BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN1_V1 BIT(0) + +#define R_AX_USB_GPS_V1 0x51C0 +#define B_AX_FUNCTION_SUSB_EN_GPS_V1 BIT(3) +#define B_AX_LOWPOWER_GPS_V1 BIT(2) +#define B_AX_FUNCTION_WAKE_EN_GPS_V1 BIT(1) +#define B_AX_FUNCTION_WAKE_CAPABLE_GPS_V1 BIT(0) + +#define R_AX_USB_DEBUG_0_V1 0x51D0 +#define B_AX_SLEEP_GNT_BT_V1 BIT(17) +#define B_AX_SLEEP_REQ_BT_V1 BIT(16) +#define B_AX_DEBUG_SIGNAL_001_V1_SH 8 +#define B_AX_DEBUG_SIGNAL_001_V1_MSK 0xff +#define B_AX_USB_DBGO_SEL_V1_SH 0 +#define B_AX_USB_DBGO_SEL_V1_MSK 0xff + +#define R_AX_USB_DEBUG_1_V1 0x51D4 +#define B_AX_EP7_COUNTER_V1_SH 28 +#define B_AX_EP7_COUNTER_V1_MSK 0xf +#define B_AX_EP6_COUNTER_V1_SH 24 +#define B_AX_EP6_COUNTER_V1_MSK 0xf +#define B_AX_EP5_COUNTER_V1_SH 20 +#define B_AX_EP5_COUNTER_V1_MSK 0xf +#define B_AX_EP4_COUNTER_V1_SH 16 +#define B_AX_EP4_COUNTER_V1_MSK 0xf +#define B_AX_EP3_COUNTER_V1_SH 12 +#define B_AX_EP3_COUNTER_V1_MSK 0xf +#define B_AX_EP2_COUNTER_V1_SH 8 +#define B_AX_EP2_COUNTER_V1_MSK 0xf +#define B_AX_EP1_COUNTER_V1_SH 4 +#define B_AX_EP1_COUNTER_V1_MSK 0xf +#define B_AX_EP0_COUNTER_V1_SH 0 +#define B_AX_EP0_COUNTER_V1_MSK 0xf + +#define R_AX_USB_DEBUG_2_V1 0x51D8 +#define B_AX_EP15_COUNTER_V1_SH 28 +#define B_AX_EP15_COUNTER_V1_MSK 0xf +#define B_AX_EP14_COUNTER_V1_SH 24 +#define B_AX_EP14_COUNTER_V1_MSK 0xf +#define B_AX_EP13_COUNTER_V1_SH 20 +#define B_AX_EP13_COUNTER_V1_MSK 0xf +#define B_AX_EP12_COUNTER_V1_SH 16 +#define B_AX_EP12_COUNTER_V1_MSK 0xf +#define B_AX_EP11_COUNTER_V1_SH 12 +#define B_AX_EP11_COUNTER_V1_MSK 0xf +#define B_AX_EP10_COUNTER_V1_SH 8 +#define B_AX_EP10_COUNTER_V1_MSK 0xf +#define B_AX_EP9_COUNTER_V1_SH 4 +#define B_AX_EP9_COUNTER_V1_MSK 0xf +#define B_AX_EP8_COUNTER_V1_SH 0 +#define B_AX_EP8_COUNTER_V1_MSK 0xf + +#define R_AX_USB_DEBUG_3_V1 0x51DC +#define B_AX_RX_STATE_MACHINE_V1_SH 24 +#define B_AX_RX_STATE_MACHINE_V1_MSK 0xff +#define B_AX_TX_STATE_MACHINE_V1_SH 16 +#define B_AX_TX_STATE_MACHINE_V1_MSK 0xff +#define B_AX_IO_STATE_MACHINE_V1_SH 8 +#define B_AX_IO_STATE_MACHINE_V1_MSK 0xff +#define B_AX_REG_WRITE_COUNTER_V1_SH 4 +#define B_AX_REG_WRITE_COUNTER_V1_MSK 0xf +#define B_AX_REG_READ_COUNTER_V1_SH 0 +#define B_AX_REG_READ_COUNTER_V1_MSK 0xf + +#define R_AX_USB_DEBUG_4_V1 0x51E0 +#define B_AX_EP15_CNT_DIRECT_V1 BIT(31) +#define B_AX_EP14_CNT_DIRECT_V1 BIT(30) +#define B_AX_EP13_CNT_DIRECT_V1 BIT(29) +#define B_AX_EP12_CNT_DIRECT_V1 BIT(28) +#define B_AX_EP11_CNT_DIRECT_V1 BIT(27) +#define B_AX_EP10_CNT_DIRECT_V1 BIT(26) +#define B_AX_EP9_CNT_DIRECT_V1 BIT(25) +#define B_AX_EP8_CNT_DIRECT_V1 BIT(24) +#define B_AX_EP7_CNT_DIRECT_V1 BIT(23) +#define B_AX_EP6_CNT_DIRECT_V1 BIT(22) +#define B_AX_EP5_CNT_DIRECT_V1 BIT(21) +#define B_AX_EP4_CNT_DIRECT_V1 BIT(20) +#define B_AX_EP3_CNT_DIRECT_V1 BIT(19) +#define B_AX_EP2_CNT_DIRECT_V1 BIT(18) +#define B_AX_EP1_CNT_DIRECT_V1 BIT(17) +#define B_AX_EP0_CNT_DIRECT_V1 BIT(16) +#define B_AX_HW_TXVLD_TOGGLE_EN_V1 BIT(15) +#define B_AX_HW_FORCE_TXRDY_EN_V1 BIT(14) +#define B_AX_TXVLD_TOGGLE_VAL_V1_SH 8 +#define B_AX_TXVLD_TOGGLE_VAL_V1_MSK 0xf +#define B_AX_TXVLD_TOUT_VAL_V1_SH 0 +#define B_AX_TXVLD_TOUT_VAL_V1_MSK 0xff + +#define R_AX_USB_DEBUG_5_V1 0x51E4 +#define B_AX_ON_IOH_ADDR_V1_SH 8 +#define B_AX_ON_IOH_ADDR_V1_MSK 0xffffff +#define B_AX_ON_IOH_TIMER_V1_SH 4 +#define B_AX_ON_IOH_TIMER_V1_MSK 0xf +#define B_AX_ON_IOH_EMPTY_V1 BIT(2) +#define B_AX_ON_IOH_FLAG_V1 BIT(1) +#define B_AX_ON_IOH_EN_V1 BIT(0) + +#define R_AX_USB_DEBUG_6_V1 0x51E8 +#define B_AX_OFF_IOH_ADDR_V1_SH 8 +#define B_AX_OFF_IOH_ADDR_V1_MSK 0xffffff +#define B_AX_OFF_IOH_TIMER_V1_SH 4 +#define B_AX_OFF_IOH_TIMER_V1_MSK 0xf +#define B_AX_OFF_IOH_FLAG_V1 BIT(1) +#define B_AX_OFF_IOH_EN_V1 BIT(0) + +#define R_AX_USB_STATUS_V1 0x51F0 +#define B_AX_USB_EP_NUM_V1_SH 4 +#define B_AX_USB_EP_NUM_V1_MSK 0xf +#define B_AX_R_SSIC_EN_V1 BIT(2) +#define B_AX_R_USB2_SEL_V1 BIT(1) +#define B_AX_MODE_HS_V1 BIT(0) + +#define R_AX_USB_D2F_F2D_INFO_V1 0x5200 +#define B_AX_HRPWM2_V1_SH 16 +#define B_AX_HRPWM2_V1_MSK 0xffff +#define B_AX_CPWM2_V1_SH 0 +#define B_AX_CPWM2_V1_MSK 0xffff + +#define R_AX_USB3_V1 0x5220 +#define B_AX_U3_STATE_V1_SH 12 +#define B_AX_U3_STATE_V1_MSK 0xf +#define B_AX_U3_SUB_STATE_V1_SH 8 +#define B_AX_U3_SUB_STATE_V1_MSK 0xf +#define B_AX_HPS_CLKR_USB_V1_SH 0 +#define B_AX_HPS_CLKR_USB_V1_MSK 0xff + +#define R_AX_USB_OTHERS_0_V1 0x5230 +#define B_AX_USBTX_EP3IF_OK_CNT_V1_SH 24 +#define B_AX_USBTX_EP3IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP2IF_OK_CNT_V1_SH 16 +#define B_AX_USBTX_EP2IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP1IF_OK_CNT_V1_SH 8 +#define B_AX_USBTX_EP1IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP0IF_OK_CNT_V1_SH 0 +#define B_AX_USBTX_EP0IF_OK_CNT_V1_MSK 0xff + +#define R_AX_USB_OTHERS_1_V1 0x5234 +#define B_AX_USBTX_EP7IF_OK_CNT_V1_SH 24 +#define B_AX_USBTX_EP7IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP6IF_OK_CNT_V1_SH 16 +#define B_AX_USBTX_EP6IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP5IF_OK_CNT_V1_SH 8 +#define B_AX_USBTX_EP5IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP4IF_OK_CNT_V1_SH 0 +#define B_AX_USBTX_EP4IF_OK_CNT_V1_MSK 0xff + +#define R_AX_USB_OTHERS_2_V1 0x5238 +#define B_AX_USBRX_DMAIF_OK_CNT_V1_SH 24 +#define B_AX_USBRX_DMAIF_OK_CNT_V1_MSK 0xff +#define B_AX_USBRX_EPIF_OK_CNT_V1_SH 16 +#define B_AX_USBRX_EPIF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP9IF_OK_CNT_V1_SH 8 +#define B_AX_USBTX_EP9IF_OK_CNT_V1_MSK 0xff +#define B_AX_USBTX_EP8IF_OK_CNT_V1_SH 0 +#define B_AX_USBTX_EP8IF_OK_CNT_V1_MSK 0xff + +#define R_AX_USB_OTHERS_3_V1 0x523C +#define B_AX_VENDOR_LMP_LATCH_DATA_L_V1_SH 0 +#define B_AX_VENDOR_LMP_LATCH_DATA_L_V1_MSK 0xffffffffL + +#define R_AX_USB_OTHERS_4_V1 0x5240 +#define B_AX_VENDOR_LMP_LATCH_DATA_H_V1_SH 0 +#define B_AX_VENDOR_LMP_LATCH_DATA_H_V1_MSK 0xffffffffL + +#define R_AX_USB_OTHERS_5_V1 0x5244 +#define B_AX_APPEND_ZERO_PKT_V1_SH 24 +#define B_AX_APPEND_ZERO_PKT_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_7_V1_SH 21 +#define B_AX_USB_AUTO_LOAD_EXTE_7_V1_MSK 0x3 +#define B_AX_USB_AUTO_LOAD_EXTE_0_V1_SH 16 +#define B_AX_USB_AUTO_LOAD_EXTE_0_V1_MSK 0x1f +#define B_AX_USB_AUTO_LOAD_EXTE_2_V1_SH 8 +#define B_AX_USB_AUTO_LOAD_EXTE_2_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_1_V1_SH 0 +#define B_AX_USB_AUTO_LOAD_EXTE_1_V1_MSK 0xff + +#define R_AX_USB_OTHERS_6_V1 0x5248 +#define B_AX_USB_AUTO_LOAD_STRING_3_V1_SH 24 +#define B_AX_USB_AUTO_LOAD_STRING_3_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_2_V1_SH 16 +#define B_AX_USB_AUTO_LOAD_STRING_2_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_1_V1_SH 8 +#define B_AX_USB_AUTO_LOAD_STRING_1_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_0_V1_SH 0 +#define B_AX_USB_AUTO_LOAD_STRING_0_V1_MSK 0xff + +#define R_AX_USB_OTHERS_7_V1 0x524C +#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_V1_SH 22 +#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_V1_SH 14 +#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_V1_MSK 0xff +#define B_AX_USB_AUTO_LOAD_STRING_FLAG_V1 BIT(13) +#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_V1_SH 7 +#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_V1_MSK 0x3f +#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_V1_SH 0 +#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_V1_MSK 0x7f + +#define R_AX_USB_WATCHDOG_V1 0x5260 +#define B_AX_USBIO_WD_FLAG_V1 BIT(31) +#define B_AX_USBIO_WD_EN_V1 BIT(30) +#define B_AX_USBIO_WD_TIMER_V1_SH 24 +#define B_AX_USBIO_WD_TIMER_V1_MSK 0xf +#define B_AX_USBIO_WD_ADDR_V1_SH 0 +#define B_AX_USBIO_WD_ADDR_V1_MSK 0xffffff + +#define R_AX_HUSBIMR_V1 0x5270 +#define B_AX_USB_CPUIO_TIMEOUT_INT_EN_V1 BIT(29) +#define B_AX_USB_HC1ISR_IDCT_INT_EN_V1 BIT(28) +#define B_AX_USB_HC0ISR_IDCT_INT_EN_V1 BIT(27) +#define B_AX_USB_HD1ISR_IDCT_INT_EN_V1 BIT(26) +#define B_AX_USB_HD0ISR_IDCT_INT_EN_V1 BIT(25) +#define B_AX_USB_HS1ISR_IDCT_INT_EN_V1 BIT(24) +#define B_AX_USB_HS0ISR_IDCT_INT_EN_V1 BIT(23) +#define B_AX_USB_TX_CH12_INT_EN_V1 BIT(7) +#define B_AX_USB_TX_CH10_INT_EN_V1 BIT(6) +#define B_AX_USB_TX_CH8_INT_EN_V1 BIT(5) +#define B_AX_USB_TX_CH6_INT_EN_V1 BIT(4) +#define B_AX_USB_TX_CH4_INT_EN_V1 BIT(3) +#define B_AX_USB_TX_CH2_INT_EN_V1 BIT(2) +#define B_AX_USB_TX_CH0_INT_EN_V1 BIT(1) +#define B_AX_USB_RX_INT_EN_V1 BIT(0) + +#define R_AX_HUSBISR_V1 0x5274 +#define B_AX_USB_CPUIO_TIMEOUT_INT_V1 BIT(29) +#define B_AX_USB_HC1ISR_IDCT_INT_V1 BIT(28) +#define B_AX_USB_HC0ISR_IDCT_INT_V1 BIT(27) +#define B_AX_USB_HD1ISR_IDCT_INT_V1 BIT(26) +#define B_AX_USB_HD0ISR_IDCT_INT_V1 BIT(25) +#define B_AX_USB_HS1ISR_IDCT_INT_V1 BIT(24) +#define B_AX_USB_HS0ISR_IDCT_INT_V1 BIT(23) +#define B_AX_USB_TX_CH12_INT_V1 BIT(7) +#define B_AX_USB_TX_CH10_INT_V1 BIT(6) +#define B_AX_USB_TX_CH8_INT_V1 BIT(5) +#define B_AX_USB_TX_CH6_INT_V1 BIT(4) +#define B_AX_USB_TX_CH4_INT_V1 BIT(3) +#define B_AX_USB_TX_CH2_INT_V1 BIT(2) +#define B_AX_USB_TX_CH0_INT_V1 BIT(1) +#define B_AX_USB_RX_INT_V1 BIT(0) +// +// WL_AX_Reg_WLCPU_Local.xls +// + +// +// WLCPU_Local_Reg +// + +#define R_AX_MAILBOX_WIFI2BT_DATA_L 0x0000 +#define B_AX_MBOX_WIFI2BT_DATA_L_SH 0 +#define B_AX_MBOX_WIFI2BT_DATA_L_MSK 0xffffffffL + +#define R_AX_MAILBOX_WIFI2BT_DATA_H 0x0004 +#define B_AX_MBOX_WIFI2BT_DATA_H_SH 0 +#define B_AX_MBOX_WIFI2BT_DATA_H_MSK 0xffffffffL + +#define R_AX_MAILBOX_WIFI2BT_READY 0x0008 +#define B_AX_MBOX_OUT_ABORT BIT(7) +#define B_AX_MBOX_ACK_WIFI2BT BIT(0) + +#define R_AX_MAILBOX_BT2WIFI_DATA_L 0x0010 +#define B_AX_MBOX_BT2WIFI_DATA_L_SH 0 +#define B_AX_MBOX_BT2WIFI_DATA_L_MSK 0xffffffffL + +#define R_AX_MAILBOX_BT2WIFI_DATA_H 0x0014 +#define B_AX_MBOX_BT2WIFI_DATA_H_SH 0 +#define B_AX_MBOX_BT2WIFI_DATA_H_MSK 0xffffffffL + +#define R_AX_MAILBOX_CTRL 0x0018 +#define B_AX_I2C_MAILBOX_EN BIT(31) + +#define R_AX_EXC_JUMP_ADDR 0x0020 +#define B_AX_WLCPU_EXC_JUMP_ADDR_SH 0 +#define B_AX_WLCPU_EXC_JUMP_ADDR_MSK 0xffffffffL + +#define R_AX_CPU_BOOT_ADDR 0x0024 +#define B_AX_WLCPU_BOOT_ADDR_SH 0 +#define B_AX_WLCPU_BOOT_ADDR_MSK 0xffffffffL + +#define R_AX_CPU_IDMEM_TO_CNT 0x0030 +#define B_AX_CPU_DMEM_TO_CNT_TH_SH 16 +#define B_AX_CPU_DMEM_TO_CNT_TH_MSK 0xffff +#define B_AX_CPU_IMEM_TO_CNT_TH_SH 0 +#define B_AX_CPU_IMEM_TO_CNT_TH_MSK 0xffff + +#define R_AX_WDT_CTRL 0x0040 +#define B_AX_WDT_EN BIT(31) +#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29) +#define B_AX_WDT_CLR BIT(16) +#define B_AX_WDT_COUNT_SH 0 +#define B_AX_WDT_COUNT_MSK 0xffff +#define B_AX_WDT_CTRL_ALL_DIS 0 + +#define R_AX_WDT_STATUS 0x0044 +#define B_AX_FS_WDT_INT BIT(8) +#define B_AX_FS_WDT_INT_MSK BIT(0) + +#define R_AX_WDT_CDC 0x0048 +#define B_AX_WDT_CDC_SH 0 +#define B_AX_WDT_CDC_MSK 0xffff + +#define R_AX_INT1_CTRL_IND 0x0050 +#define B_AX_FWC_INT_IND_SH 0 +#define B_AX_FWC_INT_IND_MSK 0xfffff + +#define R_AX_INT2_CTRL_IND 0x0054 +#define B_AX_FWD_INT_IND_SH 0 +#define B_AX_FWD_INT_IND_MSK 0x7 + +#define R_AX_INT3_CTRL_IND 0x0058 +#define B_AX_FWS_INT_IND BIT(0) + +#define R_AX_INT4_CTRL_IND 0x005C +#define B_AX_FWDA_INT_IND_SH 0 +#define B_AX_FWDA_INT_IND_MSK 0x7 + +#define R_AX_INT5_CTRL_IND 0x0060 +#define B_AX_SUB_SYS_ERR_IND_SH 29 +#define B_AX_SUB_SYS_ERR_IND_MSK 0x7 +#define B_AX_FWP_INT_IND_SH 0 +#define B_AX_FWP_INT_IND_MSK 0x7 + +#define R_AX_USB_CTRL 0x0080 +#define B_AX_USB2_SUSB_STS BIT(7) +#define B_AX_USB3_SUSB_STS BIT(6) +#define B_AX_ALLOW_WAKE_HOST BIT(5) +#define B_AX_WLCPU_WAKE_USB BIT(4) + +#define B_AX_PD_REGU_L BIT(16) +#define B_AX_XTAL_OFF_A_DIE BIT(22) +#define B_AX_R_SYM_ISO_DMEM62PP BIT(29) +#define B_AX_R_SYM_ISO_DMEM52PP BIT(28) +#define B_AX_R_SYM_ISO_DMEM42PP BIT(27) +#define B_AX_R_SYM_ISO_DMEM32PP_V1 BIT(26) +#define B_AX_R_SYM_ISO_DMEM22PP_V1 BIT(25) +#define B_AX_R_SYM_ISO_DMEM12PP_V1 BIT(24) + +#define R_AX_SDIO_HRPWM1_V1 0x4080 + +#define R_AX_FWD1ISR_V1 0x7804 + +#define R_AX_PCIE_HRPWM_V1 0x30C0 + +#define R_AX_PCIE_CRPWM 0x30C4 + +#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18) +#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) + +#define R_AX_SPSLDO_ON_CTRL0 0x0200 +#define B_AX_PFMCMP_IQ BIT(31) +#define B_AX_OFF_END_SEL BIT(29) +#define B_AX_POW_MINOFF_L BIT(28) +#define B_AX_COT_I_L_SH 26 +#define B_AX_COT_I_L_MSK 0x3 +#define B_AX_VREFPFM_L_SH 22 +#define B_AX_VREFPFM_L_MSK 0xf +#define B_AX_FORCE_ZCD_BIAS BIT(21) +#define B_AX_ZCD_SDZ_L_SH 19 +#define B_AX_ZCD_SDZ_L_MSK 0x3 +#define B_AX_REG_ZCDC_H_SH 17 +#define B_AX_REG_ZCDC_H_MSK 0x3 +#define B_AX_POW_ZCD_L BIT(16) +#define B_AX_OCP_L1_SH 13 +#define B_AX_OCP_L1_MSK 0x7 +#define B_AX_POWOCP_L1 BIT(12) +#define B_AX_SAW_FREQ_L_SH 8 +#define B_AX_SAW_FREQ_L_MSK 0xf +#define B_AX_REG_BYPASS_L BIT(7) +#define B_AX_FPWM_L1 BIT(6) +#define B_AX_STD_L1_SH 4 +#define B_AX_STD_L1_MSK 0x3 +#define B_AX_VOL_L1_SH 0 +#define B_AX_VOL_L1_MSK 0xf + +#define R_AX_SPS_DIG_ON_CTRL0 0x0200 +#define B_AX_REG_BG_H BIT(30) + +#endif diff --git a/phl/hal_g6/mac/pcie_reg.h b/phl/hal_g6/mac/pcie_reg.h new file mode 100644 index 0000000..b7e7d1c --- /dev/null +++ b/phl/hal_g6/mac/pcie_reg.h @@ -0,0 +1,95 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __HALMAC_PCIE_REG_H__ +#define __HALMAC_PCIE_REG_H__ + +/* PCIE PHY register */ +#define RAC_CTRL_PPR 0x00 +#define RAC_ANA10 0x10 +#define RAC_ANA19 0x19 + +#define RAC_REG_REV2 0x1B +#define BAC_CMU_EN_DLY_SH 12 +#define BAC_CMU_EN_DLY_MSK 0xF + +#define RAC_REG_FLD_0 0x1D +#define BAC_AUTOK_N_SH 2 +#define BAC_AUTOK_N_MSK 0x3 + +#define RAC_ANA1F 0x1F +#define RAC_SET_PPR 0x20 +#define RAC_TRG_PPR 0x21 +#define RAC_ANA24 0x24 +#define RAC_ANA26 0x26 + +#define RAC_CTRL_PPR_V1 0x30 +#define BAC_AUTOK_DIV_SH 14 +#define BAC_AUTOK_DIV_MSK 0x3 +#define BAC_AUTOK_EN BIT(13) +#define BAC_AUTOK_ONCE_EN BIT(12) +#define BAC_AUTOK_HW_TAR_SH 0 +#define BAC_AUTOK_HW_TAR_MSK 0xFFF + +#define RAC_SET_PPR_V1 0x31 +#define BAC_AUTOK_MGN_SH 12 +#define BAC_AUTOK_MGN_MSK 0xF +#define BAC_AUTOK_TAR_SH 0 +#define BAC_AUTOK_TAR_MSK 0xFFF + +/* PCIE CFG register */ +#define PCIE_L1_STS 0x80 +#define PCIE_PHY_RATE 0x82 +#define PCIE_L1SS_CTRL 0x718 +#define PCIE_L1_CTRL 0x719 +#define PCIE_ACK_NFTS 0x70D +#define PCIE_COM_CLK_NFTS 0x70E +#define PCIE_FTS 0x80C +#define PCIE_ASPM_CTRL 0x70F +#define PCIE_CLK_CTRL 0x725 +#define CFG_RST_MSTATE 0xB48 +#define PCIE_L1SS_CAP 0x160 +#define PCIE_L1SS_SUP 0x164 +#define PCIE_L1SS_STS 0x168 + +/* PCIE CFG bit */ +#define PCIE_BIT_STS_L0S BIT(0) +#define PCIE_BIT_STS_L1 BIT(1) +#define PCIE_BIT_WAKE BIT(2) +#define PCIE_BIT_L1 BIT(3) +#define PCIE_BIT_CLK BIT(4) +#define PCIE_BIT_L0S BIT(7) +#define PCIE_BIT_L1SS BIT(5) +#define PCIE_BIT_L1SSSUP BIT(4) + +/* PCIE ASPM mask*/ +#define SHFT_L1DLY 3 +#define SHFT_L0SDLY 0 +#define PCIE_ASPMDLY_MASK 0x07 +#define PCIE_L1SS_MASK 0x0F + +/* PCIE Capability */ +#define PCIE_L1SS_ID 0x001E + +/* PCIE MAC register */ +#define LINK_CTRL2_REG_OFFSET 0xA0 +#define GEN2_CTRL_OFFSET 0x80C +#define LINK_STATUS_REG_OFFSET 0x82 + +#define PCIE_GEN1_SPEED 0x01 +#define PCIE_GEN2_SPEED 0x02 + +#endif/* __HALMAC_PCIE_REG_H__ */ diff --git a/phl/hal_g6/mac/pltfm_cfg.h b/phl/hal_g6/mac/pltfm_cfg.h new file mode 100644 index 0000000..a022635 --- /dev/null +++ b/phl/hal_g6/mac/pltfm_cfg.h @@ -0,0 +1,161 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PLTFM_H_ +#define _MAC_AX_PLTFM_H_ + +#ifndef __cplusplus /* for win/linux driver */ + +/* Include header file which contain the following definitions, */ +/* or modify this file to meet your platform */ +/*[Driver] use their own header files*/ +#include "../hal_headers_le.h" + +/*[Driver] provide the define of NULL, u8, u16, u32*/ +#ifndef NULL +#define NULL ((void *)0) +#endif + +/*[Driver] provide the type mutex*/ +/* Mutex type */ +#define mac_ax_mutex _os_mutex + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + +#define _ASSERT_ BUG_ON + +/* 1: enable MAC debug messages */ +/* 0: disable MAC debug messages */ +#define MAC_AX_DBG_MSG_EN 1 + +/* Set debug message level */ +#define MAC_AX_MSG_LEVEL_TRACE 3 +#define MAC_AX_MSG_LEVEL_WARNING 2 +#define MAC_AX_MSG_LEVEL_ERR 1 +#define MAC_AX_MSG_LEVEL_ALWAYS 0 +#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE + +#define SET_CLR_WORD(_w, _v, _f) \ + (((_w) & ~((_f##_MSK) << (_f##_SH))) | \ + (((_v) & (_f##_MSK)) << (_f##_SH))) +#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH)) +#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK)) + +#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \ + (((_v) & _msk) << _sh)) +#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh) +#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk) + +#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH)) + +#else /* for WD1 test program */ + +/* Include header file which contain the following definitions, */ +/* or modify this file to meet your platform */ +#include // critical_section +#include + +#define BIT(x) (1 << (x)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +typedef unsigned char u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef char s8; +typedef int16_t s16; +typedef int32_t s32; + +#include "../hal_headers_le.h" + +typedef u16 __le16; +typedef u32 __le32; +typedef u16 __be16; +typedef u32 __be32; + +typedef CRITICAL_SECTION mac_ax_mutex; + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +/* 1: the platform is Little Endian. */ +/* 0: the platform is Big Endian. */ +#define MAC_AX_IS_LITTLE_ENDIAN 1 + +/* 1: enable MAC debug messages */ +/* 0: disable MAC debug messages */ +#define MAC_AX_DBG_MSG_EN 1 + +/* Set debug message level */ +#define MAC_AX_MSG_LEVEL_TRACE 3 +#define MAC_AX_MSG_LEVEL_WARNING 2 +#define MAC_AX_MSG_LEVEL_ERR 1 +#define MAC_AX_MSG_LEVEL_ALWAYS 0 +#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE + +#define SET_CLR_WORD(_w, _v, _f) \ + (((_w) & ~((_f##_MSK) << (_f##_SH))) | \ + (((_v) & (_f##_MSK)) << (_f##_SH))) +#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH)) +#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK)) + +#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \ + (((_v) & _msk) << _sh)) +#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh) +#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk) + +#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH)) + +#define SWAP32(x) \ + ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) + +#define SWAP16(x) \ + ((u16)((((u16)(x) & (u16)0x00ff) << 8) | \ + (((u16)(x) & (u16)0xff00) >> 8))) + +#if MAC_AX_IS_LITTLE_ENDIAN +#define cpu_to_le32(x) ((u32)(x)) +#define le32_to_cpu(x) ((u32)(x)) +#define cpu_to_le16(x) ((u16)(x)) +#define le16_to_cpu(x) ((u16)(x)) +#define cpu_to_be32(x) SWAP32((x)) +#define be32_to_cpu(x) SWAP32((x)) +#define cpu_to_be16(x) SWAP16((x)) +#define be16_to_cpu(x) SWAP16((x)) +#else +#define cpu_to_le32(x) SWAP32((x)) +#define le32_to_cpu(x) SWAP32((x)) +#define cpu_to_le16(x) SWAP16((x)) +#define le16_to_cpu(x) SWAP16((x)) +#define cpu_to_be32(x) ((u32)(x)) +#define be32_to_cpu(x) ((u32)(x)) +#define cpu_to_be16(x) ((u16)(x)) +#define be16_to_cpu(x) ((u16)(x)) +#endif + +#ifndef __func__ +#define __func__ __FUNCTION__ +#endif + +#endif // end of #else /* for WD1 test program */ + +#endif diff --git a/phl/hal_g6/mac/pltfm_cfg_drv.h b/phl/hal_g6/mac/pltfm_cfg_drv.h new file mode 100644 index 0000000..56d39a0 --- /dev/null +++ b/phl/hal_g6/mac/pltfm_cfg_drv.h @@ -0,0 +1,69 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_PLTFM_H_ +#define _MAC_AX_PLTFM_H_ + +/* Include header file which contain the following definitions, */ +/* or modify this file to meet your platform */ +/*[Driver] use their own header files*/ +#include "../hal_headers_le.h" + +/*[Driver] provide the define of NULL, u8, u16, u32*/ +#ifndef NULL +#define NULL ((void *)0) +#endif + +/*[Driver] provide the type mutex*/ +/* Mutex type */ +#define mac_ax_mutex _os_mutex + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + +#define _ASSERT_ BUG_ON + +typedef u16 __le16; +typedef u32 __le32; +typedef u16 __be16; +typedef u32 __be32; + +/* 1: enable MAC debug messages */ +/* 0: disable MAC debug messages */ +#define MAC_AX_DBG_MSG_EN 1 + +/* Set debug message level */ +#define MAC_AX_MSG_LEVEL_TRACE 3 +#define MAC_AX_MSG_LEVEL_WARNING 2 +#define MAC_AX_MSG_LEVEL_ERR 1 +#define MAC_AX_MSG_LEVEL_ALWAYS 0 +#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE + +#define SET_CLR_WORD(_w, _v, _f) \ + (((_w) & ~((_f##_MSK) << (_f##_SH))) | \ + (((_v) & (_f##_MSK)) << (_f##_SH))) +#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH)) +#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK)) + +#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \ + (((_v) & _msk) << _sh)) +#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh) +#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk) + +#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH)) + +#endif diff --git a/phl/hal_g6/mac/rxdesc.h b/phl/hal_g6/mac/rxdesc.h new file mode 100644 index 0000000..38d6485 --- /dev/null +++ b/phl/hal_g6/mac/rxdesc.h @@ -0,0 +1,152 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_RXDESC_H_ +#define _MAC_AX_RXDESC_H_ + +/* dword0 */ +#define AX_RXD_RPKT_LEN_SH 0 +#define AX_RXD_RPKT_LEN_MSK 0x3fff +#define AX_RXD_SHIFT_SH 14 +#define AX_RXD_SHIFT_MSK 0x3 +#define AX_RXD_WL_HD_IV_LEN_SH 16 +#define AX_RXD_WL_HD_IV_LEN_MSK 0x3f +#define AX_RXD_BB_SEL BIT(22) +#define AX_RXD_MAC_INFO_VLD BIT(23) +#define AX_RXD_RPKT_TYPE_SH 24 +#define AX_RXD_RPKT_TYPE_MSK 0xf +#define AX_RXD_DRV_INFO_SIZE_SH 28 +#define AX_RXD_DRV_INFO_SIZE_MSK 0x7 +#define AX_RXD_LONG_RXD BIT(31) + +/* dword1 */ +#define AX_RXD_PPDU_TYPE_SH 0 +#define AX_RXD_PPDU_TYPE_MSK 0xf +#define AX_RXD_PPDU_CNT_SH 4 +#define AX_RXD_PPDU_CNT_MSK 0x7 +#define AX_RXD_SR_EN BIT(7) +#define AX_RXD_USER_ID_SH 8 +#define AX_RXD_USER_ID_MSK 0xff +#define AX_RXD_USER_ID_v1_SH 8 +#define AX_RXD_USER_ID_v1_MSK 0x3f +#define AX_RXD_RX_DATARATE_SH 16 +#define AX_RXD_RX_DATARATE_MSK 0x1ff +#define AX_RXD_RX_GI_LTF_SH 25 +#define AX_RXD_RX_GI_LTF_MSK 0x7 +#define AX_RXD_NON_SRG_PPDU BIT(28) +#define AX_RXD_INTER_PPDU BIT(29) +#define AX_RXD_NON_SRG_PPDU_v1 BIT(14) +#define AX_RXD_INTER_PPDU_v1 BIT(15) +#define AX_RXD_BW_SH 30 +#define AX_RXD_BW_MSK 0x3 +#define AX_RXD_BW_v1_SH 29 +#define AX_RXD_BW_v1_MSK 0x7 + +/* dword2 */ +#define AX_RXD_FREERUN_CNT_SH 0 +#define AX_RXD_FREERUN_CNT_MSK 0xffffffff + +/* dword3 */ +#define AX_RXD_A1_MATCH BIT(0) +#define AX_RXD_SW_DEC BIT(1) +#define AX_RXD_HW_DEC BIT(2) +#define AX_RXD_AMPDU BIT(3) +#define AX_RXD_AMPDU_END_PKT BIT(4) +#define AX_RXD_AMSDU BIT(5) +#define AX_RXD_AMSDU_CUT BIT(6) +#define AX_RXD_LAST_MSDU BIT(7) +#define AX_RXD_BYPASS BIT(8) +#define AX_RXD_CRC32_ERR BIT(9) +#define AX_RXD_ICV_ERR BIT(10) +#define AX_RXD_MAGIC_WAKE BIT(11) +#define AX_RXD_UNICAST_WAKE BIT(12) +#define AX_RXD_PATTERN_WAKE BIT(13) +#define AX_RXD_GET_CH_INFO_SH 14 +#define AX_RXD_GET_CH_INFO_MSK 0x3 +#define AX_RXD_PATTERN_IDX_SH 16 +#define AX_RXD_PATTERN_IDX_MSK 0x1f +#define AX_RXD_TARGET_IDC_SH 21 +#define AX_RXD_TARGET_IDC_MSK 0x7 +#define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) +#define AX_RXD_WITH_LLC BIT(25) +#define AX_RXD_RX_STATISTICS BIT(26) + +/* dword4 */ +#define AX_RXD_TYPE_SH 0 +#define AX_RXD_TYPE_MSK 0x3 +#define AX_RXD_MC BIT(2) +#define AX_RXD_BC BIT(3) +#define AX_RXD_MD BIT(4) +#define AX_RXD_MF BIT(5) +#define AX_RXD_PWR BIT(6) +#define AX_RXD_QOS BIT(7) +#define AX_RXD_TID_SH 8 +#define AX_RXD_TID_MSK 0xf +#define AX_RXD_EOSP BIT(12) +#define AX_RXD_HTC BIT(13) +#define AX_RXD_QNULL BIT(14) +#define AX_RXD_SEQ_SH 16 +#define AX_RXD_SEQ_MSK 0xfff +#define AX_RXD_FRAG_SH 28 +#define AX_RXD_FRAG_MSK 0xf + +/* dword5 */ +#define AX_RXD_SEC_CAM_IDX_SH 0 +#define AX_RXD_SEC_CAM_IDX_MSK 0xff +#define AX_RXD_ADDR_CAM_SH 8 +#define AX_RXD_ADDR_CAM_MSK 0xff +#define AX_RXD_MAC_ID_SH 16 +#define AX_RXD_MAC_ID_MSK 0xff +#define AX_RXD_RX_PL_ID_SH 24 +#define AX_RXD_RX_PL_ID_MSK 0xf +#define AX_RXD_ADDR_CAM_VLD BIT(28) +#define AX_RXD_ADDR_FWD_EN BIT(29) +#define AX_RXD_RX_PL_MATCH BIT(30) + +/* dword6 */ +#define AX_RXD_MAC_ADDR_SH 0 +#define AX_RXD_MAC_ADDR_MSK 0xffffffff + +/* dword7 */ +#define AX_RXD_MAC_ADDR_H_SH 0 +#define AX_RXD_MAC_ADDR_H_MSK 0xffff +#define AX_RXD_SMART_ANT BIT(16) +#define AX_RXD_SEC_TYPE_SH 17 +#define AX_RXD_SEC_TYPE_MSK 0xf +#define AX_RXD_HDR_CNV BIT(21) +#define AX_RXD_HDR_OFFSET_SH 22 +#define AX_RXD_HDR_OFFSET_MSK 0x1f +#define AX_RXD_BIP_KEYID BIT(27) +#define AX_RXD_BIP_ENC BIT(28) + +#define RXD_S_RPKT_TYPE_WIFI 0 +#define RXD_S_RPKT_TYPE_PPDU 1 +#define RXD_S_RPKT_TYPE_CH_INFO 2 +#define RXD_S_RPKT_TYPE_BB_SCORE 3 +#define RXD_S_RPKT_TYPE_TXCMD_RPT 4 +#define RXD_S_RPKT_TYPE_SS2FW_RPT 5 +#define RXD_S_RPKT_TYPE_TXRPT 6 +#define RXD_S_RPKT_TYPE_PLDREL_HOST 7 +#define RXD_S_RPKT_TYPE_DFS_RPT 8 +#define RXD_S_RPKT_TYPE_PLDREL_WLCPU 9 +#define RXD_S_RPKT_TYPE_C2H 10 +#define RXD_S_RPKT_TYPE_CSI 11 +#define RXD_S_RPKT_TYPE_CQI 12 +#define RXD_S_RPKT_TYPE_H2C 13 +#define RXD_S_RPKT_TYPE_FWDL 14 + +#endif + diff --git a/phl/hal_g6/mac/txdesc.h b/phl/hal_g6/mac/txdesc.h new file mode 100644 index 0000000..227bcc9 --- /dev/null +++ b/phl/hal_g6/mac/txdesc.h @@ -0,0 +1,565 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TXDESC_H_ +#define _MAC_AX_TXDESC_H_ + +#if MAC_AX_8852A_SUPPORT +/* dword0 */ +#define AX_TXD_WP_OFFSET_SH 24 +#define AX_TXD_WP_OFFSET_MSK 0xff +#define AX_TXD_MOREDATA BIT(23) +#define AX_TXD_WDINFO_EN BIT(22) +#define AX_TXD_PKT_OFFSET BIT(21) +#define AX_TXD_FWDL_EN BIT(20) +#define AX_TXD_CH_DMA_SH 16 +#define AX_TXD_CH_DMA_MSK 0xf +#define AX_TXD_HDR_LLC_LEN_SH 11 +#define AX_TXD_HDR_LLC_LEN_MSK 0x1f +#define AX_TXD_STF_MODE BIT(10) +#define AX_TXD_WP_INT BIT(9) +#define AX_TXD_CHK_EN BIT(8) +#define AX_TXD_WD_PAGE BIT(7) +#define AX_TXD_HW_AES_IV BIT(6) +#define AX_TXD_HWAMSDU BIT(5) +#define AX_TXD_SMH_EN BIT(4) +#define AX_TXD_HW_SSN_SEL_SH 2 +#define AX_TXD_HW_SSN_SEL_MSK 0x3 +#define AX_TXD_EN_HWSEQ_MODE_SH 0 +#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3 + +/* dword1 */ +#define AX_TXD_PLD_SH 16 +#define AX_TXD_PLD_MSK 0xffff +#define AX_TXD_DMA_TXAGG_NUM_SH 8 +#define AX_TXD_DMA_TXAGG_NUM_MSK 0xff +#define AX_TXD_SHCUT_CAMID_SH 0 +#define AX_TXD_SHCUT_CAMID_MSK 0xff + +/* dword2 */ +#define AX_TXD_MACID_SH 24 +#define AX_TXD_MACID_MSK 0x7f +#define AX_TXD_TID_IND BIT(23) +#define AX_TXD_QSEL_SH 17 +#define AX_TXD_QSEL_MSK 0x3f +#define AX_TXD_RU_TC_SH 14 +#define AX_TXD_RU_TC_MSK 0x7 +#define AX_TXD_TXPKTSIZE_SH 0 +#define AX_TXD_TXPKTSIZE_MSK 0x3fff + +/* dword3 */ +#define AX_TXD_MU_TC_SH 29 +#define AX_TXD_MU_TC_MSK 0x7 +#define AX_TXD_MU_2ND_TC_SH 26 +#define AX_TXD_MU_2ND_TC_MSK 0x7 +#define AX_TXD_DATA_TC_SH 20 +#define AX_TXD_DATA_TC_MSK 0x3f +#define AX_TXD_RTS_TC_SH 14 +#define AX_TXD_RTS_TC_MSK 0x3f +#define AX_TXD_BK BIT(13) +#define AX_TXD_AGG_EN BIT(12) +#define AX_TXD_WIFI_SEQ_SH 0 +#define AX_TXD_WIFI_SEQ_MSK 0xfff + +/* dword4 */ +#define AX_TXD_AES_IV_L_SH 16 +#define AX_TXD_AES_IV_L_MSK 0xffff +#define AX_TXD_TXDESC_CHECKSUM_SH 0 +#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff + +/* dword5 */ +#define AX_TXD_AES_IV_H_SH 0 +#define AX_TXD_AES_IV_H_MSK 0xffffffff + +/* dword6 */ +#define AX_TXD_ACK_CH_INFO BIT(31) +#define AX_TXD_USERATE_SEL BIT(30) +#define AX_TXD_DATA_BW_SH 28 +#define AX_TXD_DATA_BW_MSK 0x3 +#define AX_TXD_GI_LTF_SH 25 +#define AX_TXD_GI_LTF_MSK 0x7 +#define AX_TXD_DATARATE_SH 16 +#define AX_TXD_DATARATE_MSK 0x1ff +#define AX_TXD_DATA_ER BIT(15) +#define AX_TXD_DATA_DCM BIT(14) +#define AX_TXD_DATA_STBC BIT(12) +#define AX_TXD_DATA_LDPC BIT(11) +#define AX_TXD_DISDATAFB BIT(10) +#define AX_TXD_DISRTSFB BIT(9) +#define AX_TXD_DATA_BW_ER BIT(8) +#define AX_TXD_MULTIPORT_ID_SH 4 +#define AX_TXD_MULTIPORT_ID_MSK 0x7 +#define AX_TXD_MBSSID_SH 0 +#define AX_TXD_MBSSID_MSK 0xf + +/* dword7 */ +#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31) +#define AX_TXD_DATA_TXCNT_LMT_SH 25 +#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f +#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16 +#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff +#define AX_TXD_A_CTRL_CAS BIT(15) +#define AX_TXD_A_CTRL_BSR BIT(14) +#define AX_TXD_A_CTRL_UPH BIT(13) +#define AX_TXD_A_CTRL_BQR BIT(12) +#define AX_TXD_BMC BIT(11) +#define AX_TXD_NAVUSEHDR BIT(10) +#define AX_TXD_BCN_SRCH_SEQ_SH 8 +#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3 +#define AX_TXD_MAX_AGG_NUM_SH 0 +#define AX_TXD_MAX_AGG_NUM_MSK 0xff + +/* dword8 */ +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26 +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf +#define AX_TXD_TXPWR_OFSET_TYPE_SH 22 +#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7 +#define AX_TXD_LSIG_TXOP_EN BIT(21) +#define AX_TXD_AMPDU_DENSITY_SH 18 +#define AX_TXD_AMPDU_DENSITY_MSK 0x7 +#define AX_TXD_FORCE_TXOP BIT(17) +#define AX_TXD_LIFETIME_SEL_SH 13 +#define AX_TXD_LIFETIME_SEL_MSK 0x7 +#define AX_TXD_SECTYPE_SH 9 +#define AX_TXD_SECTYPE_MSK 0xf +#define AX_TXD_SEC_HW_ENC BIT(8) +#define AX_TXD_SEC_CAM_IDX_SH 0 +#define AX_TXD_SEC_CAM_IDX_MSK 0xff + +/* dword9 */ +#define AX_TXD_FORCE_BSS_CLR BIT(31) +#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27 +#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf +#define AX_TXD_BCNPKT_TSF_CTRL BIT(26) +#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16 +#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff +#define AX_TXD_RAW BIT(15) +#define AX_TXD_NULL_1 BIT(14) +#define AX_TXD_NULL_0 BIT(13) +#define AX_TXD_TRI_FRAME BIT(12) +#define AX_TXD_BT_NULL BIT(11) +#define AX_TXD_SPE_RPT BIT(10) +#define AX_TXD_RTT_EN BIT(9) +#define AX_TXD_HT_DATA_SND BIT(7) +#define AX_TXD_SIFS_TX BIT(6) +#define AX_TXD_SND_PKT_SEL_SH 3 +#define AX_TXD_SND_PKT_SEL_MSK 0x7 +#define AX_TXD_NDPA_SH 1 +#define AX_TXD_NDPA_MSK 0x3 +#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0) + +/* dword10 */ +#define AX_TXD_HW_RTS_EN BIT(31) +#define AX_TXD_CCA_RTS_SH 29 +#define AX_TXD_CCA_RTS_MSK 0x3 +#define AX_TXD_CTS2SELF BIT(28) +#define AX_TXD_RTS_EN BIT(27) +#define AX_TXD_SW_DEFINE_SH 0 +#define AX_TXD_SW_DEFINE_MSK 0xf + +/* dword11 */ +#define AX_TXD_NDPA_DURATION_SH 16 +#define AX_TXD_NDPA_DURATION_MSK 0xffff + +/* dword12 */ +#define AX_TXD_VALID_1 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_1_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff +#define AX_TXD_VALID_0 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_0_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff + +/* dword13 */ +#define AX_TXD_VALID_3 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_3_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff +#define AX_TXD_VALID_2 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_2_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff + +#endif + +#if MAC_AX_8852B_SUPPORT +/* dword0 */ +#define AX_TXD_WP_OFFSET_SH 24 +#define AX_TXD_WP_OFFSET_MSK 0xff +#define AX_TXD_MOREDATA BIT(23) +#define AX_TXD_WDINFO_EN BIT(22) +#define AX_TXD_PKT_OFFSET BIT(21) +#define AX_TXD_FWDL_EN BIT(20) +#define AX_TXD_CH_DMA_SH 16 +#define AX_TXD_CH_DMA_MSK 0xf +#define AX_TXD_HDR_LLC_LEN_SH 11 +#define AX_TXD_HDR_LLC_LEN_MSK 0x1f +#define AX_TXD_STF_MODE BIT(10) +#define AX_TXD_WP_INT BIT(9) +#define AX_TXD_CHK_EN BIT(8) +#define AX_TXD_WD_PAGE BIT(7) +#define AX_TXD_HW_AES_IV BIT(6) +#define AX_TXD_HWAMSDU BIT(5) +#define AX_TXD_SMH_EN BIT(4) +#define AX_TXD_HW_SSN_SEL_SH 2 +#define AX_TXD_HW_SSN_SEL_MSK 0x3 +#define AX_TXD_EN_HWSEQ_MODE_SH 0 +#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3 + +/* dword1 */ +#define AX_TXD_PLD_SH 16 +#define AX_TXD_PLD_MSK 0xffff +#define AX_TXD_DMA_TXAGG_NUM_SH 8 +#define AX_TXD_DMA_TXAGG_NUM_MSK 0xff +#define AX_TXD_SHCUT_CAMID_SH 0 +#define AX_TXD_SHCUT_CAMID_MSK 0xff + +/* dword2 */ +#define AX_TXD_MACID_SH 24 +#define AX_TXD_MACID_MSK 0x7f +#define AX_TXD_TID_IND BIT(23) +#define AX_TXD_QSEL_SH 17 +#define AX_TXD_QSEL_MSK 0x3f +#define AX_TXD_RU_TC_SH 14 +#define AX_TXD_RU_TC_MSK 0x7 +#define AX_TXD_TXPKTSIZE_SH 0 +#define AX_TXD_TXPKTSIZE_MSK 0x3fff + +/* dword3 */ +#define AX_TXD_MU_TC_SH 29 +#define AX_TXD_MU_TC_MSK 0x7 +#define AX_TXD_MU_2ND_TC_SH 26 +#define AX_TXD_MU_2ND_TC_MSK 0x7 +#define AX_TXD_DATA_TC_SH 20 +#define AX_TXD_DATA_TC_MSK 0x3f +#define AX_TXD_RTS_TC_SH 14 +#define AX_TXD_RTS_TC_MSK 0x3f +#define AX_TXD_BK BIT(13) +#define AX_TXD_AGG_EN BIT(12) +#define AX_TXD_WIFI_SEQ_SH 0 +#define AX_TXD_WIFI_SEQ_MSK 0xfff + +/* dword4 */ +#define AX_TXD_AES_IV_L_SH 16 +#define AX_TXD_AES_IV_L_MSK 0xffff +#define AX_TXD_TXDESC_CHECKSUM_SH 0 +#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff + +/* dword5 */ +#define AX_TXD_AES_IV_H_SH 0 +#define AX_TXD_AES_IV_H_MSK 0xffffffff + +/* dword6 */ +#define AX_TXD_ACK_CH_INFO BIT(31) +#define AX_TXD_USERATE_SEL BIT(30) +#define AX_TXD_DATA_BW_SH 28 +#define AX_TXD_DATA_BW_MSK 0x3 +#define AX_TXD_GI_LTF_SH 25 +#define AX_TXD_GI_LTF_MSK 0x7 +#define AX_TXD_DATARATE_SH 16 +#define AX_TXD_DATARATE_MSK 0x1ff +#define AX_TXD_DATA_ER BIT(15) +#define AX_TXD_DATA_DCM BIT(14) +#define AX_TXD_DATA_STBC BIT(12) +#define AX_TXD_DATA_LDPC BIT(11) +#define AX_TXD_DISDATAFB BIT(10) +#define AX_TXD_DISRTSFB BIT(9) +#define AX_TXD_DATA_BW_ER BIT(8) +#define AX_TXD_MULTIPORT_ID_SH 4 +#define AX_TXD_MULTIPORT_ID_MSK 0x7 +#define AX_TXD_MBSSID_SH 0 +#define AX_TXD_MBSSID_MSK 0xf + +/* dword7 */ +#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31) +#define AX_TXD_DATA_TXCNT_LMT_SH 25 +#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f +#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16 +#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff +#define AX_TXD_A_CTRL_CAS BIT(15) +#define AX_TXD_A_CTRL_BSR BIT(14) +#define AX_TXD_A_CTRL_UPH BIT(13) +#define AX_TXD_A_CTRL_BQR BIT(12) +#define AX_TXD_BMC BIT(11) +#define AX_TXD_NAVUSEHDR BIT(10) +#define AX_TXD_BCN_SRCH_SEQ_SH 8 +#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3 +#define AX_TXD_MAX_AGG_NUM_SH 0 +#define AX_TXD_MAX_AGG_NUM_MSK 0xff + +/* dword8 */ +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26 +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf +#define AX_TXD_TXPWR_OFSET_TYPE_SH 22 +#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7 +#define AX_TXD_LSIG_TXOP_EN BIT(21) +#define AX_TXD_AMPDU_DENSITY_SH 18 +#define AX_TXD_AMPDU_DENSITY_MSK 0x7 +#define AX_TXD_FORCE_TXOP BIT(17) +#define AX_TXD_LIFETIME_SEL_SH 13 +#define AX_TXD_LIFETIME_SEL_MSK 0x7 +#define AX_TXD_SECTYPE_SH 9 +#define AX_TXD_SECTYPE_MSK 0xf +#define AX_TXD_SEC_HW_ENC BIT(8) +#define AX_TXD_SEC_CAM_IDX_SH 0 +#define AX_TXD_SEC_CAM_IDX_MSK 0xff + +/* dword9 */ +#define AX_TXD_FORCE_BSS_CLR BIT(31) +#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27 +#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf +#define AX_TXD_BCNPKT_TSF_CTRL BIT(26) +#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16 +#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff +#define AX_TXD_RAW BIT(15) +#define AX_TXD_NULL_1 BIT(14) +#define AX_TXD_NULL_0 BIT(13) +#define AX_TXD_TRI_FRAME BIT(12) +#define AX_TXD_BT_NULL BIT(11) +#define AX_TXD_SPE_RPT BIT(10) +#define AX_TXD_RTT_EN BIT(9) +#define AX_TXD_HT_DATA_SND BIT(7) +#define AX_TXD_SIFS_TX BIT(6) +#define AX_TXD_SND_PKT_SEL_SH 3 +#define AX_TXD_SND_PKT_SEL_MSK 0x7 +#define AX_TXD_NDPA_SH 1 +#define AX_TXD_NDPA_MSK 0x3 +#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0) + +/* dword10 */ +#define AX_TXD_HW_RTS_EN BIT(31) +#define AX_TXD_CCA_RTS_SH 29 +#define AX_TXD_CCA_RTS_MSK 0x3 +#define AX_TXD_CTS2SELF BIT(28) +#define AX_TXD_RTS_EN BIT(27) +#define AX_TXD_SW_DEFINE_SH 0 +#define AX_TXD_SW_DEFINE_MSK 0xf + +/* dword11 */ +#define AX_TXD_NDPA_DURATION_SH 16 +#define AX_TXD_NDPA_DURATION_MSK 0xffff + +/* dword12 */ +#define AX_TXD_VALID_1 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_1_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff +#define AX_TXD_VALID_0 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_0_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff + +/* dword13 */ +#define AX_TXD_VALID_3 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_3_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff +#define AX_TXD_VALID_2 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_2_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff + +#endif + +#if MAC_AX_8852C_SUPPORT +/* dword0 */ +#define AX_TXD_NO_ACK BIT(31) +#define AX_TXD_UPD_WLAN_HDR BIT(30) +#define AX_TXD_WP_OFFSET_V1_SH 24 +#define AX_TXD_WP_OFFSET_V1_MSK 0x1f +#define AX_TXD_MOREDATA BIT(23) +#define AX_TXD_WDINFO_EN BIT(22) +#define AX_TXD_PKT_OFFSET BIT(21) +#define AX_TXD_FWDL_EN BIT(20) +#define AX_TXD_CH_DMA_SH 16 +#define AX_TXD_CH_DMA_MSK 0xf +#define AX_TXD_HDR_LLC_LEN_SH 11 +#define AX_TXD_HDR_LLC_LEN_MSK 0x1f +#define AX_TXD_STF_MODE BIT(10) +#define AX_TXD_WP_INT BIT(9) +#define AX_TXD_CHK_EN BIT(8) +#define AX_TXD_WD_PAGE BIT(7) +#define AX_TXD_HW_SEC_IV BIT(6) +#define AX_TXD_HWAMSDU BIT(5) +#define AX_TXD_SMH_EN BIT(4) +#define AX_TXD_HW_SSN_SEL_SH 2 +#define AX_TXD_HW_SSN_SEL_MSK 0x3 +#define AX_TXD_EN_HWSEQ_MODE_SH 0 +#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3 + +/* dword1 */ +#define AX_TXD_ADDR_INFO_NUM_SH 26 +#define AX_TXD_ADDR_INFO_NUM_MSK 0x3f +#define AX_TXD_REUSE_START_NUM_SH 24 +#define AX_TXD_REUSE_START_NUM_MSK 0x3 +#define AX_TXD_REUSE_SIZE_SH 20 +#define AX_TXD_REUSE_SIZE_MSK 0xf +#define AX_TXD_DMA_TXAGG_NUM_V1_SH 8 +#define AX_TXD_DMA_TXAGG_NUM_V1_MSK 0x7f +#define AX_TXD_SW_SEC_IV BIT(6) +#define AX_TXD_SEC_KEYID_SH 4 +#define AX_TXD_SEC_KEYID_MSK 0x3 +#define AX_TXD_SEC_TYPE_SH 0 +#define AX_TXD_SEC_TYPE_MSK 0xf + +/* dword2 */ +#define AX_TXD_MACID_SH 24 +#define AX_TXD_MACID_MSK 0x7f +#define AX_TXD_TID_IND BIT(23) +#define AX_TXD_QSEL_SH 17 +#define AX_TXD_QSEL_MSK 0x3f +#define AX_TXD_MU_2ND_RTY BIT(16) +#define AX_TXD_MU_PRI_RTY BIT(15) +#define AX_TXD_RU_RTY BIT(14) +#define AX_TXD_TXPKTSIZE_SH 0 +#define AX_TXD_TXPKTSIZE_MSK 0x3fff + +/* dword3 */ +#define AX_TXD_TB_SR_RTY BIT(31) +#define AX_TXD_DATA_TC_SH 20 +#define AX_TXD_DATA_TC_MSK 0x3f +#define AX_TXD_RTS_TC_SH 14 +#define AX_TXD_RTS_TC_MSK 0x3f +#define AX_TXD_BK BIT(13) +#define AX_TXD_AGG_EN BIT(12) +#define AX_TXD_WIFI_SEQ_SH 0 +#define AX_TXD_WIFI_SEQ_MSK 0xfff + +/* dword4 */ +#define AX_TXD_SEC_IV_L_SH 16 +#define AX_TXD_SEC_IV_L_MSK 0xffff +#define AX_TXD_TXDESC_CHECKSUM_SH 0 +#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff + +/* dword5 */ +#define AX_TXD_SEC_IV_H_SH 0 +#define AX_TXD_SEC_IV_H_MSK 0xffffffff + +/* dword6 */ +#define AX_TXD_RU_POS_SH 24 +#define AX_TXD_RU_POS_MSK 0xff +#define AX_TXD_S_IDX_SH 16 +#define AX_TXD_S_IDX_MSK 0xff +#define AX_TXD_RU_TC_V1_SH 5 +#define AX_TXD_RU_TC_V1_MSK 0x1f +#define AX_TXD_MU_TC_V1_SH 0 +#define AX_TXD_MU_TC_V1_MSK 0x1f + +/* dword7 */ +#define AX_TXD_USERATE_SEL_V1 BIT(31) +#define AX_TXD_DATA_DCM_V1 BIT(30) +#define AX_TXD_DATA_BW_SH 28 +#define AX_TXD_DATA_BW_MSK 0x3 +#define AX_TXD_GI_LTF_SH 25 +#define AX_TXD_GI_LTF_MSK 0x7 +#define AX_TXD_DATARATE_SH 16 +#define AX_TXD_DATARATE_MSK 0x1ff + +/* dword8 */ +#define AX_TXD_ACK_CH_INFO BIT(31) +#define AX_TXD_RLS_TO_CPUIO BIT(30) +#define AX_TXD_GI_LTF_SH 25 +#define AX_TXD_GI_LTF_MSK 0x7 +#define AX_TXD_DATA_ER BIT(15) +#define AX_TXD_DATA_STBC BIT(12) +#define AX_TXD_DATA_LDPC BIT(11) +#define AX_TXD_DISDATAFB BIT(10) +#define AX_TXD_DISRTSFB BIT(9) +#define AX_TXD_DATA_BW_ER BIT(8) +#define AX_TXD_MULTIPORT_ID_SH 4 +#define AX_TXD_MULTIPORT_ID_MSK 0x7 +#define AX_TXD_MBSSID_SH 0 +#define AX_TXD_MBSSID_MSK 0xf + +/* dword9 */ +#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31) +#define AX_TXD_DATA_TXCNT_LMT_SH 25 +#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f +#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16 +#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff +#define AX_TXD_A_CTRL_CAS BIT(15) +#define AX_TXD_A_CTRL_BSR BIT(14) +#define AX_TXD_A_CTRL_UPH BIT(13) +#define AX_TXD_A_CTRL_BQR BIT(12) +#define AX_TXD_BMC BIT(11) +#define AX_TXD_NAVUSEHDR BIT(10) +#define AX_TXD_BCN_SRCH_SEQ_SH 8 +#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3 +#define AX_TXD_MAX_AGG_NUM_SH 0 +#define AX_TXD_MAX_AGG_NUM_MSK 0xff + +/* dword10 */ +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26 +#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf +#define AX_TXD_TXPWR_OFSET_TYPE_SH 22 +#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7 +#define AX_TXD_LSIG_TXOP_EN BIT(21) +#define AX_TXD_AMPDU_DENSITY_SH 18 +#define AX_TXD_AMPDU_DENSITY_MSK 0x7 +#define AX_TXD_FORCE_TXOP BIT(17) +#define AX_TXD_LIFETIME_SEL_SH 13 +#define AX_TXD_LIFETIME_SEL_MSK 0x7 +#define AX_TXD_FORCE_KEY_EN BIT(8) +#define AX_TXD_SEC_CAM_IDX_SH 0 +#define AX_TXD_SEC_CAM_IDX_MSK 0xff + +/* dword11 */ +#define AX_TXD_FORCE_BSS_CLR BIT(31) +#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27 +#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf +#define AX_TXD_BCNPKT_TSF_CTRL BIT(26) +#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16 +#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff +#define AX_TXD_RAW BIT(15) +#define AX_TXD_NULL_1 BIT(14) +#define AX_TXD_NULL_0 BIT(13) +#define AX_TXD_TRI_FRAME BIT(12) +#define AX_TXD_BT_NULL BIT(11) +#define AX_TXD_SPE_RPT BIT(10) +#define AX_TXD_RTT_EN BIT(9) +#define AX_TXD_HT_DATA_SND BIT(7) +#define AX_TXD_SIFS_TX BIT(6) +#define AX_TXD_SND_PKT_SEL_SH 3 +#define AX_TXD_SND_PKT_SEL_MSK 0x7 +#define AX_TXD_NDPA_SH 1 +#define AX_TXD_NDPA_MSK 0x3 +#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0) + +/* dword12 */ +#define AX_TXD_HW_RTS_EN BIT(31) +#define AX_TXD_CCA_RTS_SH 29 +#define AX_TXD_CCA_RTS_MSK 0x3 +#define AX_TXD_CTS2SELF BIT(28) +#define AX_TXD_RTS_EN BIT(27) +#define AX_TXD_SW_DEFINE_SH 0 +#define AX_TXD_SW_DEFINE_MSK 0xf + +/* dword13 */ +#define AX_TXD_NDPA_DURATION_SH 16 +#define AX_TXD_NDPA_DURATION_MSK 0xffff + +/* dword14 */ +#define AX_TXD_VALID_1 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_1_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff +#define AX_TXD_VALID_0 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_0_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff + +/* dword15 */ +#define AX_TXD_VALID_3 BIT(31) +#define AX_TXD_PCIE_SEQ_NUM_3_SH 16 +#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff +#define AX_TXD_VALID_2 BIT(15) +#define AX_TXD_PCIE_SEQ_NUM_2_SH 0 +#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff + +#endif + +#endif diff --git a/phl/hal_g6/mac/type.h b/phl/hal_g6/mac/type.h new file mode 100644 index 0000000..aa75cc2 --- /dev/null +++ b/phl/hal_g6/mac/type.h @@ -0,0 +1,1873 @@ +/** @file */ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _MAC_AX_TYPE_H_ +#define _MAC_AX_TYPE_H_ + +#include "mac_def.h" +#include "mac_reg.h" +#include "mac_hw_info.h" +#include "txdesc.h" +#include "rxdesc.h" + +#include "mac_ax/mac_ax_dfs.h" +#include "mac_ax/mac_ax_mac_info.h" +#include "mac_ax/mac_txccxrpt.h" + +#if MAC_AX_FEATURE_DBGPKG +#include "mac_ax/dbgpkg.h" +#endif + +#if MAC_AX_FEATURE_HV +#include "hv_type.h" +#endif + +/*--------------------Define -------------------------------------------*/ + +#ifdef CONFIG_NEW_HALMAC_INTERFACE +#define PLTFM_SDIO_CMD52_R8(addr) \ + hal_sdio_cmd52_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R8(addr) \ + hal_sdio_cmd53_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R16(addr) \ + hal_sdio_cmd53_r16(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R32(addr) \ + hal_sdio_cmd53_r32(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_RN(addr, size, val) \ + hal_sdio_cmd53_rn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_W8(addr, val) \ + hal_sdio_cmd52_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W8(addr, val) \ + hal_sdio_cmd53_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_WN(addr, size, val) \ + hal_sdio_cmd53_wn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD53_W16(addr, val) \ + hal_sdio_cmd53_w16(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W32(addr, val) \ + hal_sdio_cmd53_w32(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD52_CIA_R8(addr) \ + hal_sdio_read_cia_r8(adapter->drv_adapter, addr) + +#define PLTFM_TX(buf, len) \ + hal_tx(adapter->drv_adapter, buf, len) + +#define PLTFM_FREE(buf, size) \ + hal_mem_free(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + hal_mem_alloc(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + hal_mem_cpy(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + hal_mem_set(adapter->drv_adapter, addr, value, size) +#define PLTFM_MEMCMP(ptr1, ptr2, num) \ + hal_mem_cmp(adapter->drv_adapter, ptr1, ptr2, num) + +#define PLTFM_DELAY_US(us) \ + hal_udelay(adapter->drv_adapter, us) +#define PLTFM_DELAY_MS(ms) \ + hal_mdelay(adapter->drv_adapter, ms) +#define PLTFM_MUTEX_INIT(mutex) \ + hal_mutex_init(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + hal_mutex_deinit(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + hal_mutex_lock(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + hal_mutex_unlock(adapter->drv_adapter, mutex) + +#define PLTFM_MSG_PRINT(...) \ + hal_mac_msg_print(drv_adapter, __VA_ARGS__) + +#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops)) +#define adapter_to_intf_ops(adapter) \ + ((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops)) + +#define PLTFM_REG_R8(addr) \ + hal_read8(adapter->drv_adapter, addr) +#define PLTFM_REG_R16(addr) \ + hal_read16(adapter->drv_adapter, addr) +#define PLTFM_REG_R32(addr) \ + hal_read32(adapter->drv_adapter, addr) +#define PLTFM_REG_W8(addr, val) \ + hal_write8(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W16(addr, val) \ + hal_write16(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W32(addr, val) \ + hal_write32(adapter->drv_adapter, addr, val) + +#define MAC_REG_R8(addr) hal_read8(adapter->drv_adapter, addr) +#define MAC_REG_R16(addr) hal_read16(adapter->drv_adapter, addr) +#define MAC_REG_R32(addr) hal_read32(adapter->drv_adapter, addr) +#define MAC_REG_W8(addr, val) hal_write8(adapter->drv_adapter, addr, val) +#define MAC_REG_W16(addr, val) hal_write16(adapter->drv_adapter, addr, val) +#define MAC_REG_W32(addr, val) hal_write32(adapter->drv_adapter, addr, val) + +#if MAC_AX_FEATURE_DBGCMD +#define PLTFM_SNPRINTF(s, sz, fmt, ...) \ + hal_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__) +#define PLTFM_STRCMP(s1, s2) \ + hal_strcmp(adapter->drv_adapter, s1, s2) +#define PLTFM_STRSEP(s, ct) \ + hal_strsep(adapter->drv_adapter, s, ct) +#define PLTFM_STRLEN(s) \ + hal_strlen(adapter->drv_adapter, s) +#define PLTFM_STRCPY(dest, src) \ + hal_strcpy(adapter->drv_adapter, dest, src) +#define PLTFM_STRPBRK(cs, ct) \ + hal_strpbrk(adapter->drv_adapter, cs, ct) +#define PLTFM_STRTOUL(buf, base) \ + hal_strtoul(adapter->drv_adapter, buf, base) +#endif +#else + +/* platform callback */ +#define PLTFM_SDIO_CMD52_R8(addr) \ + adapter->pltfm_cb->sdio_cmd52_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R8(addr) \ + adapter->pltfm_cb->sdio_cmd53_r8(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R16(addr) \ + adapter->pltfm_cb->sdio_cmd53_r16(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_R32(addr) \ + adapter->pltfm_cb->sdio_cmd53_r32(adapter->drv_adapter, addr) +#define PLTFM_SDIO_CMD53_RN(addr, size, val) \ + adapter->pltfm_cb->sdio_cmd53_rn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_W8(addr, val) \ + adapter->pltfm_cb->sdio_cmd52_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W8(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w8(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W16(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w16(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_W32(addr, val) \ + adapter->pltfm_cb->sdio_cmd53_w32(adapter->drv_adapter, addr, val) +#define PLTFM_SDIO_CMD53_WN(addr, size, val) \ + adapter->pltfm_cb->sdio_cmd53_wn(adapter->drv_adapter, addr, size, val) +#define PLTFM_SDIO_CMD52_CIA_R8(addr) \ + adapter->pltfm_cb->sdio_cmd52_cia_r8(adapter->drv_adapter, addr) + +#define PLTFM_REG_R8(addr) \ + adapter->pltfm_cb->reg_r8(adapter->drv_adapter, addr) +#define PLTFM_REG_R16(addr) \ + adapter->pltfm_cb->reg_r16(adapter->drv_adapter, addr) +#define PLTFM_REG_R32(addr) \ + adapter->pltfm_cb->reg_r32(adapter->drv_adapter, addr) +#define PLTFM_REG_W8(addr, val) \ + adapter->pltfm_cb->reg_w8(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W16(addr, val) \ + adapter->pltfm_cb->reg_w16(adapter->drv_adapter, addr, val) +#define PLTFM_REG_W32(addr, val) \ + adapter->pltfm_cb->reg_w32(adapter->drv_adapter, addr, val) + +#if MAC_AX_PHL_H2C +#define PLTFM_TX(buf) \ + adapter->pltfm_cb->tx(adapter->phl_adapter, adapter->drv_adapter, buf) +#define PLTFM_QUERY_H2C(type) \ + adapter->pltfm_cb->rtl_query_h2c(adapter->phl_adapter, \ + adapter->drv_adapter, type) +#else +#define PLTFM_TX(buf, len) \ + adapter->pltfm_cb->tx(adapter->drv_adapter, buf, len) +#endif +#define PLTFM_FREE(buf, size) \ + adapter->pltfm_cb->rtl_free(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + adapter->pltfm_cb->rtl_malloc(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + adapter->pltfm_cb->rtl_memcpy(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + adapter->pltfm_cb->rtl_memset(adapter->drv_adapter, addr, value, size) +#define PLTFM_MEMCMP(ptr1, ptr2, num) \ + adapter->pltfm_cb->rtl_memcmp(adapter->drv_adapter, ptr1, ptr2, num) +#define PLTFM_DELAY_US(us) \ + adapter->pltfm_cb->rtl_delay_us(adapter->drv_adapter, us) +#define PLTFM_DELAY_MS(ms) \ + adapter->pltfm_cb->rtl_delay_ms(adapter->drv_adapter, ms) + +#define PLTFM_MUTEX_INIT(mutex) \ + adapter->pltfm_cb->rtl_mutex_init(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + adapter->pltfm_cb->rtl_mutex_deinit(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + adapter->pltfm_cb->rtl_mutex_lock(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + adapter->pltfm_cb->rtl_mutex_unlock(adapter->drv_adapter, mutex) +#define PLTFM_EVENT_NOTIFY(mac_ft, stat, buf, size) \ + adapter->pltfm_cb->event_notify(adapter->drv_adapter, mac_ft, stat, \ + buf, size) +#define PLTFM_L2_NOTIFY(void) \ + adapter->pltfm_cb->ser_l2_notify(adapter->phl_adapter, adapter->drv_adapter) + +#define PLTFM_LD_FW_SYMBOL(name, buf, buf_size) \ + adapter->pltfm_cb->ld_fw_symbol(adapter->phl_adapter, adapter->drv_adapter,\ + name, buf, buf_size) + +#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops)) +#define adapter_to_intf_ops(adapter) \ + ((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops)) + +#define MAC_REG_R8(addr) ops->reg_read8(adapter, addr) +#define MAC_REG_R16(addr) ops->reg_read16(adapter, addr) +#define MAC_REG_R32(addr) ops->reg_read32(adapter, addr) +#define MAC_REG_W8(addr, val) ops->reg_write8(adapter, addr, val) +#define MAC_REG_W16(addr, val) ops->reg_write16(adapter, addr, val) +#define MAC_REG_W32(addr, val) ops->reg_write32(adapter, addr, val) + +#if MAC_AX_FEATURE_DBGCMD +#define PLTFM_SNPRINTF(s, sz, fmt, ...) \ + adapter->pltfm_cb->rtl_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__) +#define PLTFM_STRCMP(s1, s2) \ + adapter->pltfm_cb->rtl_strcmp(adapter->drv_adapter, s1, s2) +#define PLTFM_STRSEP(s, ct) \ + adapter->pltfm_cb->rtl_strsep(adapter->drv_adapter, s, ct) +#define PLTFM_STRLEN(s) \ + adapter->pltfm_cb->rtl_strlen(adapter->drv_adapter, s) +#define PLTFM_STRCPY(dest, src) \ + adapter->pltfm_cb->rtl_strcpy(adapter->drv_adapter, dest, src) +#define PLTFM_STRPBRK(cs, ct) \ + adapter->pltfm_cb->rtl_strpbrk(adapter->drv_adapter, cs, ct) +#define PLTFM_STRTOUL(buf, base) \ + adapter->pltfm_cb->rtl_strtoul(adapter->drv_adapter, buf, base) +#endif +#endif /*CONFIG_NEW_HALMAC_INTERFACE*/ + +#define MAC_AX_WMM0_SEL 0 +#define MAC_AX_WMM1_SEL 1 +#define MAC_AX_WMM2_SEL 2 +#define MAC_AX_WMM3_SEL 3 + +#define MAC_AX_HI0_SEL 17 +#define MAC_AX_MG0_SEL 18 +#define MAC_AX_HI1_SEL 25 +#define MAC_AX_MG1_SEL 26 + +#define MAC_AX_HFC_CH_NUM 12 +#define MAC_AX_IECAM_NUM 12 + +#define MAC_AX_R32_EA 0xEAEAEAEA +#define MAC_AX_R32_DEAD 0xDEADBEEF +#define MAC_AX_R32_DEAD2 0xDEADDEAD +#define MAC_AX_R32_FF 0xFFFFFFFF +#define MAC_AX_R16_DEAD 0xDEAD + +#define MAC_REG_POOL_COUNT 10 +#define MAC_REG_OFFSET16 2 +#define MAC_REG_OFFSET 4 +#define MAC_REG_OFFSET_SH 8 +#define MAC_REG_OFFSET_SH_2 3 +#define R_AX_CMAC_REG_END 0xFFFF + +/* SRAM mem dump */ +#define R_AX_INDIR_ACCESS_ENTRY 0x40000 +#define MAC_MEM_DUMP_PAGE_SIZE 0x40000 + +#define CPU_LOCAL_BASE_ADDR 0x18003000 +#define AXIDMA_BASE_ADDR 0x18006000 +#define STA_SCHED_BASE_ADDR 0x18808000 +#define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 +#define SEC_CAM_BASE_ADDR 0x18814000 +#define WOW_CAM_BASE_ADDR 0x18815000 +#define CMAC_TBL_BASE_ADDR 0x18840000 +#define ADDR_CAM_BASE_ADDR 0x18850000 +#define BSSID_CAM_BASE_ADDR 0x18853000 +#define BA_CAM_BASE_ADDR 0x18854000 +#define BCN_IE_CAM0_BASE_ADDR 0x18855000 +#define SHARED_BUF_BASE_ADDR 0x18700000 +#define DMAC_TBL_BASE_ADDR 0x18800000 +#define SHCUT_MACHDR_BASE_ADDR 0x18800800 +#define BCN_IE_CAM1_BASE_ADDR 0x188A0000 +#define TXD_FIFO_0_BASE_ADDR 0x18856200 +#define TXD_FIFO_1_BASE_ADDR 0x188A1080 + +#define CCTL_INFO_SIZE 32 +#define DCTL_INFO_SIZE 16 +#define DCTL_INFO_SIZE_V1 32 +#define MACHDR_SIZE 56 +#define BA_CAM_SIZE 64 +#define BA_CAM_NUM_SH 3 +#define BCN_IE_CAM_SIZE 8 +#define BCN_IE_CAM_NUM 12 +#define AXIDMA_REG_SIZE 0x1000 + +/*--------------------Define Enum---------------------------------------*/ + +/** + * @enum mac_ax_dma_ch + * + * @brief mac_ax_dma_ch + * + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH0 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH1 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH2 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH3 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH4 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH5 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH6 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_ACH7 + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_B0MG + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_B0HI + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_B1MG + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_B1HI + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_H2C + * Please Place Description here. + * @var mac_ax_dma_ch::MAC_AX_DMA_CH_NUM + * Please Place Description here. + */ +enum mac_ax_dma_ch { + MAC_AX_DMA_ACH0 = 0, + MAC_AX_DMA_ACH1, + MAC_AX_DMA_ACH2, + MAC_AX_DMA_ACH3, + MAC_AX_DMA_ACH4, + MAC_AX_DMA_ACH5, + MAC_AX_DMA_ACH6, + MAC_AX_DMA_ACH7, + MAC_AX_DMA_B0MG, + MAC_AX_DMA_B0HI, + MAC_AX_DMA_B1MG, + MAC_AX_DMA_B1HI, + MAC_AX_DMA_H2C, + MAC_AX_DMA_CH_NUM +}; + +/** + * @enum mac_ax_data_ch + * + * @brief mac_ax_data_ch + * + * @var mac_ax_data_ch::MAC_AX_DATA_CH0 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH1 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH2 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH3 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH4 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH5 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH6 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH7 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_HIQ + * Please Place Description here. + */ + +/** + * @enum mac_ax_data_ch + * + * @brief mac_ax_data_ch + * + * @var mac_ax_data_ch::MAC_AX_DATA_CH0 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH1 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH2 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH3 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH4 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH5 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH6 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_CH7 + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_MGN + * Please Place Description here. + * @var mac_ax_data_ch::MAC_AX_DATA_HIQ + * Please Place Description here. + */ +enum mac_ax_data_ch { + MAC_AX_DATA_CH0 = 0, + MAC_AX_DATA_CH1 = 1, + MAC_AX_DATA_CH2 = 2, + MAC_AX_DATA_CH3 = 3, + MAC_AX_DATA_CH4 = 4, + MAC_AX_DATA_CH5 = 5, + MAC_AX_DATA_CH6 = 6, + MAC_AX_DATA_CH7 = 7, + MAC_AX_DATA_MGN = 8, + MAC_AX_DATA_HIQ = 9 +}; + +/** + * @enum mac_ax_pcie_phy + * + * @brief mac_ax_pcie_phy + * + * @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN1 + * Please Place Description here. + * @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN2 + * Please Place Description here. + * @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN1_UNDEFINE + * Please Place Description here. + */ +enum mac_ax_pcie_phy { + MAC_AX_PCIE_PHY_GEN1, + MAC_AX_PCIE_PHY_GEN2, + MAC_AX_PCIE_PHY_GEN1_UNDEFINE = 0x7F, +}; + +/** + * @enum mac_ax_data_rate + * + * @brief mac_ax_data_rate + * + * @var mac_ax_data_rate::MAC_AX_CCK1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_CCK2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_CCK5_5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_CCK11 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM12 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM18 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM24 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM36 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM48 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_OFDM54 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS10 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS11 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS12 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS13 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS14 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS15 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS16 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS17 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS18 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS19 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS20 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS21 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS22 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS23 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS24 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS25 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS26 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS27 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS28 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS29 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS30 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_MCS31 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS10 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS11 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS10 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS11 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS10 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS11 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS0 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS1 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS2 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS3 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS4 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS5 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS6 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS7 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS8 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS9 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS10 + * Please Place Description here. + * @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS11 + * Please Place Description here. + */ +enum mac_ax_data_rate { + MAC_AX_CCK1 = 0x0, + MAC_AX_CCK2 = 0x1, + MAC_AX_CCK5_5 = 0x2, + MAC_AX_CCK11 = 0x3, + MAC_AX_OFDM6 = 0x4, + MAC_AX_OFDM9 = 0x5, + MAC_AX_OFDM12 = 0x6, + MAC_AX_OFDM18 = 0x7, + MAC_AX_OFDM24 = 0x8, + MAC_AX_OFDM36 = 0x9, + MAC_AX_OFDM48 = 0xA, + MAC_AX_OFDM54 = 0xB, + MAC_AX_MCS0 = 0x80, + MAC_AX_MCS1 = 0x81, + MAC_AX_MCS2 = 0x82, + MAC_AX_MCS3 = 0x83, + MAC_AX_MCS4 = 0x84, + MAC_AX_MCS5 = 0x85, + MAC_AX_MCS6 = 0x86, + MAC_AX_MCS7 = 0x87, + MAC_AX_MCS8 = 0x88, + MAC_AX_MCS9 = 0x89, + MAC_AX_MCS10 = 0x8A, + MAC_AX_MCS11 = 0x8B, + MAC_AX_MCS12 = 0x8C, + MAC_AX_MCS13 = 0x8D, + MAC_AX_MCS14 = 0x8E, + MAC_AX_MCS15 = 0x8F, + MAC_AX_MCS16 = 0x90, + MAC_AX_MCS17 = 0x91, + MAC_AX_MCS18 = 0x92, + MAC_AX_MCS19 = 0x93, + MAC_AX_MCS20 = 0x94, + MAC_AX_MCS21 = 0x95, + MAC_AX_MCS22 = 0x96, + MAC_AX_MCS23 = 0x97, + MAC_AX_MCS24 = 0x98, + MAC_AX_MCS25 = 0x99, + MAC_AX_MCS26 = 0x9A, + MAC_AX_MCS27 = 0x9B, + MAC_AX_MCS28 = 0x9C, + MAC_AX_MCS29 = 0x9D, + MAC_AX_MCS30 = 0x9E, + MAC_AX_MCS31 = 0x9F, + MAC_AX_VHT_NSS1_MCS0 = 0x100, + MAC_AX_VHT_NSS1_MCS1 = 0x101, + MAC_AX_VHT_NSS1_MCS2 = 0x102, + MAC_AX_VHT_NSS1_MCS3 = 0x103, + MAC_AX_VHT_NSS1_MCS4 = 0x104, + MAC_AX_VHT_NSS1_MCS5 = 0x105, + MAC_AX_VHT_NSS1_MCS6 = 0x106, + MAC_AX_VHT_NSS1_MCS7 = 0x107, + MAC_AX_VHT_NSS1_MCS8 = 0x108, + MAC_AX_VHT_NSS1_MCS9 = 0x109, + MAC_AX_VHT_NSS2_MCS0 = 0x110, + MAC_AX_VHT_NSS2_MCS1 = 0x111, + MAC_AX_VHT_NSS2_MCS2 = 0x112, + MAC_AX_VHT_NSS2_MCS3 = 0x113, + MAC_AX_VHT_NSS2_MCS4 = 0x114, + MAC_AX_VHT_NSS2_MCS5 = 0x115, + MAC_AX_VHT_NSS2_MCS6 = 0x116, + MAC_AX_VHT_NSS2_MCS7 = 0x117, + MAC_AX_VHT_NSS2_MCS8 = 0x118, + MAC_AX_VHT_NSS2_MCS9 = 0x119, + MAC_AX_VHT_NSS3_MCS0 = 0x120, + MAC_AX_VHT_NSS3_MCS1 = 0x121, + MAC_AX_VHT_NSS3_MCS2 = 0x122, + MAC_AX_VHT_NSS3_MCS3 = 0x123, + MAC_AX_VHT_NSS3_MCS4 = 0x124, + MAC_AX_VHT_NSS3_MCS5 = 0x125, + MAC_AX_VHT_NSS3_MCS6 = 0x126, + MAC_AX_VHT_NSS3_MCS7 = 0x127, + MAC_AX_VHT_NSS3_MCS8 = 0x128, + MAC_AX_VHT_NSS3_MCS9 = 0x129, + MAC_AX_VHT_NSS4_MCS0 = 0x130, + MAC_AX_VHT_NSS4_MCS1 = 0x131, + MAC_AX_VHT_NSS4_MCS2 = 0x132, + MAC_AX_VHT_NSS4_MCS3 = 0x133, + MAC_AX_VHT_NSS4_MCS4 = 0x134, + MAC_AX_VHT_NSS4_MCS5 = 0x135, + MAC_AX_VHT_NSS4_MCS6 = 0x136, + MAC_AX_VHT_NSS4_MCS7 = 0x137, + MAC_AX_VHT_NSS4_MCS8 = 0x138, + MAC_AX_VHT_NSS4_MCS9 = 0x139, + MAC_AX_HE_NSS1_MCS0 = 0x180, + MAC_AX_HE_NSS1_MCS1 = 0x181, + MAC_AX_HE_NSS1_MCS2 = 0x182, + MAC_AX_HE_NSS1_MCS3 = 0x183, + MAC_AX_HE_NSS1_MCS4 = 0x184, + MAC_AX_HE_NSS1_MCS5 = 0x185, + MAC_AX_HE_NSS1_MCS6 = 0x186, + MAC_AX_HE_NSS1_MCS7 = 0x187, + MAC_AX_HE_NSS1_MCS8 = 0x188, + MAC_AX_HE_NSS1_MCS9 = 0x189, + MAC_AX_HE_NSS1_MCS10 = 0x18A, + MAC_AX_HE_NSS1_MCS11 = 0x18B, + MAC_AX_HE_NSS2_MCS0 = 0x190, + MAC_AX_HE_NSS2_MCS1 = 0x191, + MAC_AX_HE_NSS2_MCS2 = 0x192, + MAC_AX_HE_NSS2_MCS3 = 0x193, + MAC_AX_HE_NSS2_MCS4 = 0x194, + MAC_AX_HE_NSS2_MCS5 = 0x195, + MAC_AX_HE_NSS2_MCS6 = 0x196, + MAC_AX_HE_NSS2_MCS7 = 0x197, + MAC_AX_HE_NSS2_MCS8 = 0x198, + MAC_AX_HE_NSS2_MCS9 = 0x199, + MAC_AX_HE_NSS2_MCS10 = 0x19A, + MAC_AX_HE_NSS2_MCS11 = 0x19B, + MAC_AX_HE_NSS3_MCS0 = 0x1A0, + MAC_AX_HE_NSS3_MCS1 = 0x1A1, + MAC_AX_HE_NSS3_MCS2 = 0x1A2, + MAC_AX_HE_NSS3_MCS3 = 0x1A3, + MAC_AX_HE_NSS3_MCS4 = 0x1A4, + MAC_AX_HE_NSS3_MCS5 = 0x1A5, + MAC_AX_HE_NSS3_MCS6 = 0x1A6, + MAC_AX_HE_NSS3_MCS7 = 0x1A7, + MAC_AX_HE_NSS3_MCS8 = 0x1A8, + MAC_AX_HE_NSS3_MCS9 = 0x1A9, + MAC_AX_HE_NSS3_MCS10 = 0x1AA, + MAC_AX_HE_NSS3_MCS11 = 0x1AB, + MAC_AX_HE_NSS4_MCS0 = 0x1B0, + MAC_AX_HE_NSS4_MCS1 = 0x1B1, + MAC_AX_HE_NSS4_MCS2 = 0x1B2, + MAC_AX_HE_NSS4_MCS3 = 0x1B3, + MAC_AX_HE_NSS4_MCS4 = 0x1B4, + MAC_AX_HE_NSS4_MCS5 = 0x1B5, + MAC_AX_HE_NSS4_MCS6 = 0x1B6, + MAC_AX_HE_NSS4_MCS7 = 0x1B7, + MAC_AX_HE_NSS4_MCS8 = 0x1B8, + MAC_AX_HE_NSS4_MCS9 = 0x1B9, + MAC_AX_HE_NSS4_MCS10 = 0x1BA, + MAC_AX_HE_NSS4_MCS11 = 0x1BB +}; + +/** + * @struct wd_body_t + * @brief wd_body_t + * + * @var wd_body_t::dword0 + * Please Place Description here. + * @var wd_body_t::dword1 + * Please Place Description here. + * @var wd_body_t::dword2 + * Please Place Description here. + * @var wd_body_t::dword3 + * Please Place Description here. + * @var wd_body_t::dword4 + * Please Place Description here. + * @var wd_body_t::dword5 + * Please Place Description here. + */ +struct wd_body_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +/** + * @struct wd_info_t + * @brief wd_info_t + * + * @var wd_info_t::dword0 + * Please Place Description here. + * @var wd_info_t::dword1 + * Please Place Description here. + * @var wd_info_t::dword2 + * Please Place Description here. + * @var wd_info_t::dword3 + * Please Place Description here. + * @var wd_info_t::dword4 + * Please Place Description here. + * @var wd_info_t::dword5 + * Please Place Description here. + */ +struct wd_info_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +#define WD_BODY_LEN (sizeof(struct wd_body_t)) +#define WD_INFO_LEN (sizeof(struct wd_info_t)) + +/** + * @struct wd_body_t_v1 + * @brief wd_body_t_v1 + * + * @var wd_body_t::dword0 + * Please Place Description here. + * @var wd_body_t::dword1 + * Please Place Description here. + * @var wd_body_t::dword2 + * Please Place Description here. + * @var wd_body_t::dword3 + * Please Place Description here. + * @var wd_body_t::dword4 + * Please Place Description here. + * @var wd_body_t::dword5 + * Please Place Description here. + * @var wd_body_t::dword6 + * Please Place Description here. + * @var wd_body_t::dword7 + * Please Place Description here. + */ +struct wd_body_t_v1 { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +#define WD_BODY_LEN_V1 (sizeof(struct wd_body_t_v1)) + +/** + * @struct rxd_short_t + * @brief rxd_short_t + * + * @var rxd_short_t::dword0 + * Please Place Description here. + * @var rxd_short_t::dword1 + * Please Place Description here. + * @var rxd_short_t::dword2 + * Please Place Description here. + * @var rxd_short_t::dword3 + * Please Place Description here. + */ +struct rxd_short_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; +}; + +/** + * @struct rxd_long_t + * @brief rxd_long_t + * + * @var rxd_long_t::dword0 + * Please Place Description here. + * @var rxd_long_t::dword1 + * Please Place Description here. + * @var rxd_long_t::dword2 + * Please Place Description here. + * @var rxd_long_t::dword3 + * Please Place Description here. + * @var rxd_long_t::dword4 + * Please Place Description here. + * @var rxd_long_t::dword5 + * Please Place Description here. + * @var rxd_long_t::dword6 + * Please Place Description here. + * @var rxd_long_t::dword7 + * Please Place Description here. + */ +struct rxd_long_t { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; +}; + +#define RXD_SHORT_LEN (sizeof(struct rxd_short_t)) +#define RXD_LONG_LEN (sizeof(struct rxd_long_t)) + +/** + * @struct txd_proc_type + * @brief txd_proc_type + * + * @var txd_proc_type::type + * Please Place Description here. + * @var txd_proc_type::handler + * Please Place Description here. + */ +struct txd_proc_type { + enum rtw_packet_type type; + u32 (*handler)(struct mac_ax_adapter *adapter, + struct rtw_t_meta_data *info, u8 *buf, u32 len); +}; + +/** + * @struct rxd_parse_type + * @brief rxd_parse_type + * + * @var rxd_parse_type::type + * Please Place Description here. + * @var rxd_parse_type::handler + * Please Place Description here. + */ +struct rxd_parse_type { + u8 type; + u32 (*handler)(struct mac_ax_adapter *adapter, + struct mac_ax_rxpkt_info *info, u8 *buf, u32 len); +}; + +/** + * @enum mac_ax_bw + * + * @brief mac_ax_bw + * + * @var mac_ax_bw::MAC_AX_BW_20M + * Please Place Description here. + * @var mac_ax_bw::MAC_AX_BW_40M + * Please Place Description here. + * @var mac_ax_bw::MAC_AX_BW_80M + * Please Place Description here. + * @var mac_ax_bw::MAC_AX_BW_160M + * Please Place Description here. + * @var mac_ax_bw::MAC_AX_BW_UNDEFINE + * Please Place Description here. + */ +enum mac_ax_bw { + MAC_AX_BW_20M = 0, + MAC_AX_BW_40M = 1, + MAC_AX_BW_80M = 2, + MAC_AX_BW_160M = 3, + MAC_AX_BW_UNDEFINE = 0x7F +}; + +/** + * @enum mac_ax_gi_ltf + * + * @brief mac_ax_gi_ltf + * + * @var mac_ax_gi_ltf::MAC_AX_LGI_4XHE32 + * Please Place Description here. + * @var mac_ax_gi_ltf::MAC_AX_SGI_4XHE08 + * Please Place Description here. + * @var mac_ax_gi_ltf::MAC_AX_2XHE16 + * Please Place Description here. + * @var mac_ax_gi_ltf::MAC_AX_2XHE08 + * Please Place Description here. + * @var mac_ax_gi_ltf::MAC_AX_1XHE16 + * Please Place Description here. + * @var mac_ax_gi_ltf::MAC_AX_1XHE08 + * Please Place Description here. + */ +enum mac_ax_gi_ltf { + MAC_AX_LGI_4XHE32 = 0, + MAC_AX_SGI_4XHE08 = 1, + MAC_AX_2XHE16 = 2, + MAC_AX_2XHE08 = 3, + MAC_AX_1XHE16 = 4, + MAC_AX_1XHE08 = 5 +}; + +/** + * @enum mac_ax_stbc + * + * @brief mac_ax_stbc + * + * @var mac_ax_stbc::MAC_AX_STBC_DIS + * Please Place Description here. + * @var mac_ax_stbc::MAC_AX_STBC_EN + * Please Place Description here. + * @var mac_ax_stbc::MAC_AX_STBC_HT2 + * Please Place Description here. + */ +enum mac_ax_stbc { + MAC_AX_STBC_DIS = 0, + MAC_AX_STBC_EN = 1, + MAC_AX_STBC_HT2 = 2 +}; + +/** + * @enum mac_ax_delay_tx_en + * + * @brief mac_ax_delay_tx_en + * + * @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_DIS + * Please Place Description here. + * @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_B0 + * Please Place Description here. + * @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_B1 + * Please Place Description here. + * @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_BOTH + * Please Place Description here. + */ +enum mac_ax_delay_tx_en { + MAC_AX_DELAY_TX_DIS = 0, + MAC_AX_DELAY_TX_B0 = 1, + MAC_AX_DELAY_TX_B1 = 2, + MAC_AX_DELAY_TX_BOTH = 3, +}; + +/** + * @enum mac_ax_hcifc_mode + * + * @brief mac_ax_hcifc_mode + * + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_POH + * Please Place Description here. + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_STF + * Please Place Description here. + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_SDIO + * Please Place Description here. + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_LAST + * Please Place Description here. + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_MODE_MAX + * Please Place Description here. + * @var mac_ax_hcifc_mode::MAC_AX_HCIFC_MODE_INVALID + * Please Place Description here. + */ +enum mac_ax_hcifc_mode { + MAC_AX_HCIFC_POH = 0, + MAC_AX_HCIFC_STF = 1, + MAC_AX_HCIFC_SDIO = 2, + + /* keep last */ + MAC_AX_HCIFC_LAST, + MAC_AX_HCIFC_MODE_MAX = MAC_AX_HCIFC_LAST, + MAC_AX_HCIFC_MODE_INVALID = MAC_AX_HCIFC_LAST, +}; + +/** + * @enum mac_ax_bcn_hit_rule + * + * @brief mac_ax_bcn_hit_rule + * + * @var mac_ax_bcn_hit_rule::MAC_AX_A3 + * Please Place Description here. + * @var mac_ax_bcn_hit_rule::MAC_AX_A2 + * Please Place Description here. + * @var mac_ax_bcn_hit_rule::MAC_AX_A2_AND_A3 + * Please Place Description here. + * @var mac_ax_bcn_hit_rule::MAC_AX_A2_OR_A3 + * Please Place Description here. + */ +enum mac_ax_bcn_hit_rule { + MAC_AX_A3, + MAC_AX_A2, + MAC_AX_A2_AND_A3, + MAC_AX_A2_OR_A3 +}; + +/** + * @enum mac_ax_hit_rule + * + * @brief mac_ax_hit_rule + * + * @var mac_ax_hit_rule::MAC_AX_A1_AND_A2 + * Please Place Description here. + * @var mac_ax_hit_rule::MAC_AX_A1_AND_A3 + * Please Place Description here. + */ +enum mac_ax_hit_rule { + MAC_AX_A1_AND_A2, + MAC_AX_A1_AND_A3 +}; + +/** + * @enum mac_ax_bb_sel + * + * @brief mac_ax_bb_sel + * + * @var mac_ax_bb_sel::MAC_AX_PHY_0 + * Please Place Description here. + * @var mac_ax_bb_sel::MAC_AX_PHY_1 + * Please Place Description here. + */ +enum mac_ax_bb_sel { + MAC_AX_PHY_0, + MAC_AX_PHY_1 +}; + +/** + * @enum mac_ax_pps_sel + * + * @brief mac_ax_pps_sel + * + * @var mac_ax_pps_sel::MAC_AX_PPS_0 + * Please Place Description here. + * @var mac_ax_pps_sel::MAC_AX_PPS_1 + * Please Place Description here. + * @var mac_ax_pps_sel::MAC_AX_PPS_LAST + * Please Place Description here. + * @var mac_ax_pps_sel::MAC_AX_PPS_MAX + * Please Place Description here. + * @var mac_ax_pps_sel::MAC_AX_PPS_INVALID + * Please Place Description here. + */ +enum mac_ax_pps_sel { + MAC_AX_PPS_0 = 0, + MAC_AX_PPS_1, + + /* keep last */ + MAC_AX_PPS_LAST, + MAC_AX_PPS_MAX = MAC_AX_PPS_LAST, + MAC_AX_PPS_INVALID = MAC_AX_PPS_LAST, +}; + +/** + * @enum mac_ax_tgt_ind + * + * @brief mac_ax_tgt_ind + * + * @var mac_ax_tgt_ind::MAC_AX_TO_HOST + * Please Place Description here. + * @var mac_ax_tgt_ind::MAC_AX_TO_WLAN_CPU + * Please Place Description here. + * @var mac_ax_tgt_ind::MAC_AX_TO_DRIVER + * Please Place Description here. + */ +enum mac_ax_tgt_ind { + MAC_AX_TO_HOST, + MAC_AX_TO_WLAN_CPU, + MAC_AX_TO_DRIVER +}; + +/** + * @enum mac_ax_frm_tgt_ind + * + * @brief mac_ax_frm_tgt_ind + * + * @var mac_ax_frm_tgt_ind::MAC_AX_DIS_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_MGT_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_CTL_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_MGT_CTL_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_DATA_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_MGT_DATA_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_CTL_DATA_FRAM_TGT + * Please Place Description here. + * @var mac_ax_frm_tgt_ind::MAC_AX_MGT_CTL_DATA_FRAM_TGT + * Please Place Description here. + */ +enum mac_ax_frm_tgt_ind { + MAC_AX_DIS_FRAM_TGT, + MAC_AX_MGT_FRAM_TGT, + MAC_AX_CTL_FRAM_TGT, + MAC_AX_MGT_CTL_FRAM_TGT, + MAC_AX_DATA_FRAM_TGT, + MAC_AX_MGT_DATA_FRAM_TGT, + MAC_AX_CTL_DATA_FRAM_TGT, + MAC_AX_MGT_CTL_DATA_FRAM_TGT, +}; + +/** + * @enum mac_ax_txcnt_sel + * + * @brief mac_ax_txcnt_sel + * + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_LCCK + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_SCCK + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_OFDM + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HT + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HTGF + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_VHTSU + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_VHTMU + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HESU + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HEERSU + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HEMU + * Please Place Description here. + * @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HETB + * Please Place Description here. + */ +enum mac_ax_txcnt_sel { + MAC_AX_TXCNT_LCCK = 0, + MAC_AX_TXCNT_SCCK = 1, + MAC_AX_TXCNT_OFDM = 2, + MAC_AX_TXCNT_HT = 3, + MAC_AX_TXCNT_HTGF = 4, + MAC_AX_TXCNT_VHTSU = 5, + MAC_AX_TXCNT_VHTMU = 6, + MAC_AX_TXCNT_HESU = 7, + MAC_AX_TXCNT_HEERSU = 8, + MAC_AX_TXCNT_HEMU = 9, + MAC_AX_TXCNT_HETB = 0xA +}; + +/** + * @enum mac_ax_rxcnt_sel + * + * @brief mac_ax_rxcnt_sel + * + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_FAIL + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_PPDU + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_FAM + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_INVD + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_RECCA + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_FULLDRP + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_FULLDRP_PKT + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_RXDMA + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER0 + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER1 + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER2 + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER3 + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CONT_FCS + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_PKTFLTR_DRP + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CSIPKT_DMA_OK + * Please Place Description here. + * @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CSIPKT_DMA_DROP + * Please Place Description here. + */ +enum mac_ax_rxcnt_sel { + MAC_AX_RXCNT_OFDM_OK = 0, + MAC_AX_RXCNT_OFDM_FAIL = 1, + MAC_AX_RXCNT_OFDM_FAM = 2, + MAC_AX_RXCNT_CCK_OK = 3, + MAC_AX_RXCNT_CCK_FAIL = 4, + MAC_AX_RXCNT_CCK_FAM = 5, + MAC_AX_RXCNT_HT_OK = 6, + MAC_AX_RXCNT_HT_FAIL = 7, + MAC_AX_RXCNT_HT_PPDU = 8, + MAC_AX_RXCNT_HT_FAM = 9, + MAC_AX_RXCNT_VHTSU_OK = 0xA, + MAC_AX_RXCNT_VHTSU_FAIL = 0xB, + MAC_AX_RXCNT_VHTSU_PPDU = 0xC, + MAC_AX_RXCNT_VHTSU_FAM = 0xD, + MAC_AX_RXCNT_VHTMU_OK = 0xE, + MAC_AX_RXCNT_VHTMU_FAIL = 0xF, + MAC_AX_RXCNT_VHTMU_PPDU = 0x10, + MAC_AX_RXCNT_VHTMU_FAM = 0x11, + MAC_AX_RXCNT_HESU_OK = 0x12, + MAC_AX_RXCNT_HESU_FAIL = 0x13, + MAC_AX_RXCNT_HESU_PPDU = 0x14, + MAC_AX_RXCNT_HESU_FAM = 0x15, + MAC_AX_RXCNT_HEMU_OK = 0x16, + MAC_AX_RXCNT_HEMU_FAIL = 0x17, + MAC_AX_RXCNT_HEMU_PPDU = 0x18, + MAC_AX_RXCNT_HEMU_FAM = 0x19, + MAC_AX_RXCNT_HETB_OK = 0x1A, + MAC_AX_RXCNT_HETB_FAIL = 0x1B, + MAC_AX_RXCNT_HETB_PPDU = 0x1C, + MAC_AX_RXCNT_HETB_FAM = 0x1D, + MAC_AX_RXCNT_INVD = 0x1E, + MAC_AX_RXCNT_RECCA = 0x1F, + MAC_AX_RXCNT_FULLDRP = 0x20, + MAC_AX_RXCNT_FULLDRP_PKT = 0x21, + MAC_AX_RXCNT_RXDMA = 0x22, + MAC_AX_RXCNT_USER0 = 0x23, + MAC_AX_RXCNT_USER1 = 0x24, + MAC_AX_RXCNT_USER2 = 0x25, + MAC_AX_RXCNT_USER3 = 0x26, + MAC_AX_RXCNT_CONT_FCS = 0x27, + MAC_AX_RXCNT_PKTFLTR_DRP = 0x28, + MAC_AX_RXCNT_CSIPKT_DMA_OK = 0x29, + MAC_AX_RXCNT_CSIPKT_DMA_DROP = 0x2A +}; + +/** + * @enum mac_ax_wde_pg_size + * + * @brief mac_ax_wde_pg_size + * + * @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_64 + * Please Place Description here. + * @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_128 + * Please Place Description here. + * @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_256 + * Please Place Description here. + */ +enum mac_ax_wde_pg_size { + MAC_AX_WDE_PG_64 = 64, + MAC_AX_WDE_PG_128 = 128, + MAC_AX_WDE_PG_256 = 256 +}; + +/** + * @enum mac_ax_ple_pg_size + * + * @brief mac_ax_ple_pg_size + * + * @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_64 + * Please Place Description here. + * @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_128 + * Please Place Description here. + * @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_256 + * Please Place Description here. + */ +enum mac_ax_ple_pg_size { + MAC_AX_PLE_PG_64 = 64, + MAC_AX_PLE_PG_128 = 128, + MAC_AX_PLE_PG_256 = 256 +}; + +/** + * @enum mac_ax_iecam_type + * + * @brief mac_ax_iecam_type + * + * @var mac_ax_iecam_type::MAC_AX_IECAM_UNAVAL + * Please Place Description here. + * @var mac_ax_iecam_type::MAC_AX_IECAM_IESHW + * Please Place Description here. + * @var mac_ax_iecam_type::MAC_AX_IECAM_SPEOFT + * Please Place Description here. + * @var mac_ax_iecam_type::MAC_AX_IECAM_CRC + * Please Place Description here. + */ +enum mac_ax_iecam_type { + MAC_AX_IECAM_UNAVAL = 0, + MAC_AX_IECAM_IESHW = 1, + MAC_AX_IECAM_SPEOFT = 2, + MAC_AX_IECAM_CRC = 3 +}; + +/** + * @enum mac_ax_tcpip_chksum_ofd_status + * + * @brief mac_ax_tcpip_chksum_ofd_status + * + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV4_TCP_OK + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV6_TCP_OK + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV4_UDP_OK + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV6_UDP_OK + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_CHKSUM_ERR + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT + * Please Place Description here. + * @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_INVALID + * Please Place Description here. + */ +enum mac_ax_tcpip_chksum_ofd_status { + MAC_AX_CHKSUM_OFD_IPV4_TCP_OK = 0, + MAC_AX_CHKSUM_OFD_IPV6_TCP_OK = 1, + MAC_AX_CHKSUM_OFD_IPV4_UDP_OK = 2, + MAC_AX_CHKSUM_OFD_IPV6_UDP_OK = 3, + MAC_AX_CHKSUM_OFD_CHKSUM_ERR = 4, + MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT = 5, + MAC_AX_CHKSUM_OFD_INVALID = 6, +}; + +/** + * @enum mac_ax_io_byte_sel + * + * @brief mac_ax_io_byte_sel + * + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_1 + * Please Place Description here. + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_2 + * Please Place Description here. + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_4 + * Please Place Description here. + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_LAST + * Please Place Description here. + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_MAX + * Please Place Description here. + * @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_INVALID + * Please Place Description here. + */ +enum mac_ax_io_byte_sel { + MAC_AX_BYTE_SEL_1 = 0, + MAC_AX_BYTE_SEL_2, + MAC_AX_BYTE_SEL_4, + + /* keep last */ + MAC_AX_BYTE_SEL_LAST, + MAC_AX_BYTE_SEL_MAX = MAC_AX_BYTE_SEL_LAST, + MAC_AX_BYTE_SEL_INVALID = MAC_AX_BYTE_SEL_LAST, +}; + +/** + * @enum RW_OFLD_BLOCK_ID + * + * @brief RW_OFLD_BLOCK_ID + * + * @var RW_OFLD_BLOCK_ID::RW_OFLD_UART + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_CPU_LOCAL + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_SPIC + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_RXI300 + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_AXIDMA + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_HIOE + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_IDDMA + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_IPSEC + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_DMAC_CTRL + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_SCR_MACHDR + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_SCH_AIRTIME + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_SCH_CAP + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_DL_GRP_TBL + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_UL_GRP_TBL + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_RX_FILTER_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_SEC_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_WOW_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_CMAC_CTRL + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_ADDR_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_BSSID_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_BA_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_BCN_IE_CAM + * Please Place Description here. + * @var RW_OFLD_BLOCK_ID::RW_OFLD_MAX + * Please Place Description here. + */ +enum RW_OFLD_BLOCK_ID { + RW_OFLD_UART = 0, + RW_OFLD_CPU_LOCAL = 1, + RW_OFLD_SPIC, + RW_OFLD_RXI300, + RW_OFLD_AXIDMA, + RW_OFLD_HIOE, + RW_OFLD_IDDMA, + RW_OFLD_IPSEC, + RW_OFLD_DMAC_CTRL, + RW_OFLD_SCR_MACHDR, + RW_OFLD_STA_SCH_AIRTIME, + RW_OFLD_STA_SCH_CAP, + RW_OFLD_STA_DL_GRP_TBL, + RW_OFLD_STA_UL_GRP_TBL, + RW_OFLD_RX_FILTER_CAM, + RW_OFLD_SEC_CAM, + RW_OFLD_WOW_CAM, + RW_OFLD_CMAC_CTRL, + RW_OFLD_ADDR_CAM, + RW_OFLD_BSSID_CAM, + RW_OFLD_BA_CAM, + RW_OFLD_BCN_IE_CAM, + RW_OFLD_MAX +}; + +/** + * @enum mac_ax_cca + * + * @brief mac_ax_cca + * + * @var mac_ax_cca::MAC_AX_CCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_SEC20_CCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_SEC40_CCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_SEC80_CCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_EDCCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_BTCCA + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_CCA_LAST + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_CCA_MAX + * Please Place Description here. + * @var mac_ax_cca::MAC_AX_CCA_INVALID + * Please Place Description here. + */ +enum mac_ax_block_tx_sel { + MAC_AX_CCA, + MAC_AX_SEC20_CCA, + MAC_AX_SEC40_CCA, + MAC_AX_SEC80_CCA, + MAC_AX_EDCCA, + MAC_AX_BTCCA, + MAC_AX_TX_NAV, + + /* keep last */ + MAC_AX_CCA_LAST, + MAC_AX_CCA_MAX = MAC_AX_CCA_LAST, + MAC_AX_CCA_INVALID = MAC_AX_CCA_LAST, +}; + +/** + * struct mac_ax_pkt_data - packet information of data type + * @hdr_len: Length of header+LLC. + * For example, + * 1. 802.11 MPDU without encryption + * HEADERwLLC_LEN = (MAC header (without IV ) + LLC ) / 2 + * 2. 802.11 MPDU encryption without HW_AES_IV + * HEADERwLLC_LEN = (MAC header (without IV ) + LLC ) / 2 + * 3.802.11MPDU encryption with HW_AES_IV + * HEADERwLLC_LEN = (MAC header(reserved IV length)+LLC)/2 + * 4.ETHERNET II MSDU without encryption + * HEADERwLLC_LEN = (DA+SA+TYPE) /2 + * 5.ETHERNET II MSDU encryption without HW_AES_IV + * HEADERwLLC_LEN = (DA+SA+TYPE) /2 + * 6.ETHERNET II MSDU encryption with HW_AES_IV + * HEADERwLLC_LEN = (DA+SA+TYPE) /2 + * 7.SNAP MSDU without encryption + * HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2 + * 8.SNAP MSDU encryption without HW_AES_IV + * HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2 + * 9.SNAP MSDU encryption with HW_AES_IV + * HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2 + * @ch: Channel index, MAC_AX_CH_DMA_CH0~MAC_AX_CH_DMA_CH11. + * @macid: MAC ID. + */ +/*--------------------Define Struct-------------------------------------*/ + +/** + * @struct sec_checker + * @brief sec_checker + * + * @var sec_checker::rx_desc_hw_dec + * Please Place Description here. + * @var sec_checker::rx_desc_sec_type + * Please Place Description here. + * @var sec_checker::rx_desc_icv_err + * Please Place Description here. + */ +struct sec_checker { + u8 rx_desc_hw_dec; + u8 rx_desc_sec_type; + u8 rx_desc_icv_err; +}; + +/** + * @struct mac_ax_delay_tx_cfg + * @brief mac_ax_delay_tx_cfg + * + * @var mac_ax_delay_tx_cfg::en + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::vovi_to_b0 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::bebk_to_b0 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::vovi_to_b1 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::bebk_to_b1 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::vovi_len_b0 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::bebk_len_b0 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::vovi_len_b1 + * Please Place Description here. + * @var mac_ax_delay_tx_cfg::bebk_len_b1 + * Please Place Description here. + */ +struct mac_ax_delay_tx_cfg { + enum mac_ax_delay_tx_en en; + u8 vovi_to_b0; + u8 bebk_to_b0; + u8 vovi_to_b1; + u8 bebk_to_b1; + u8 vovi_len_b0; + u8 bebk_len_b0; + u8 vovi_len_b1; + u8 bebk_len_b1; +}; + +/** + * @struct mac_ax_ofld_hdr + * @brief mac_ax_ofld_hdr + * + * @var mac_ax_ofld_hdr::ls + * Please Place Description here. + * @var mac_ax_ofld_hdr::masken + * Please Place Description here. + * @var mac_ax_ofld_hdr::polling + * Please Place Description here. + * @var mac_ax_ofld_hdr::rsvd1 + * Please Place Description here. + * @var mac_ax_ofld_hdr::value_len + * Please Place Description here. + * @var mac_ax_ofld_hdr::ofld_id + * Please Place Description here. + * @var mac_ax_ofld_hdr::entry_num + * Please Place Description here. + * @var mac_ax_ofld_hdr::offset + * Please Place Description here. + * @var mac_ax_ofld_hdr::rsvd2 + * Please Place Description here. + */ +struct mac_ax_ofld_hdr { +//Segment Hdr + u16 ls:1; + u16 masken:1; + u16 polling:1; + u16 rsvd1:2; + u16 value_len:11; + u8 ofld_id; + u8 entry_num; + u16 offset; + u16 rsvd2; +}; + +/** + * @struct mac_ax_outsrc_h2c_hdr + * @brief mac_ax_outsrc_h2c_hdr + * + * @var mac_ax_outsrc_h2c_hdr::h2c_class + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::h2c_func + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::seq_valid + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::seq + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::seq_stop + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::rec_ack + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::done_ack + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::rsvd1 + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::content_len + * Please Place Description here. + * @var mac_ax_outsrc_h2c_hdr::rsvd2 + * Please Place Description here. + */ +struct mac_ax_outsrc_h2c_hdr { + u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC + u8 h2c_func; + u8 seq_valid:1; + u8 seq:3; + u8 seq_stop:1; + u8 rec_ack:1; //Ack when receive H2C + u8 done_ack:1; //Ack when FW execute H2C cmd done + u8 rsvd1:1; + u16 content_len:12; + u16 rsvd2:4; +}; + +/** + * @struct mac_ax_wmmps_info + * @brief mac_ax_wmmps_info + * + * @var mac_ax_wmmps_info::listen_bcn_mode + * Please Place Description here. + * @var mac_ax_wmmps_info::awake_interval + * Please Place Description here. + * @var mac_ax_wmmps_info::vo_uapsd_en + * Please Place Description here. + * @var mac_ax_wmmps_info::vi_uapsd_en + * Please Place Description here. + * @var mac_ax_wmmps_info::be_uapsd_en + * Please Place Description here. + * @var mac_ax_wmmps_info::bk_uapsd_en + * Please Place Description here. + * @var mac_ax_wmmps_info::rsvd + * Please Place Description here. + */ +struct mac_ax_wmmps_info { + enum mac_ax_listern_bcn_mode listen_bcn_mode; + u8 awake_interval; + u8 vo_uapsd_en: 1; + u8 vi_uapsd_en: 1; + u8 be_uapsd_en: 1; + u8 bk_uapsd_en: 1; + u8 rsvd: 4; +}; + +/** + * @struct mac_ax_err_status + * @brief mac_ax_err_status + * + * @var mac_ax_err_status::err + * Please Place Description here. + * @var mac_ax_err_status::rst_en + * Please Place Description here. + */ +struct mac_ax_err_status { + enum mac_ax_err_info err; + u8 rst_en; +}; + +#endif diff --git a/phl/hal_g6/phy/bb/bb.mk b/phl/hal_g6/phy/bb/bb.mk new file mode 100644 index 0000000..6b45d08 --- /dev/null +++ b/phl/hal_g6/phy/bb/bb.mk @@ -0,0 +1,95 @@ +# All needed files would be added to _HAL_INTFS_FILES, and it would include +# hal_g6/phy/bb and all related files in directory hal_g6/phy/bb/. +# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC +# (CONFIG_RTL*) setting are all ready! + +HAL = hal_g6 + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/hal_g6 +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := hal_g6 +phl_path_d1 := $(src)/$(HAL) +endif + +# Base directory +path_halbb_d1 := $(phl_path)/phy/bb + +halbb-y += $(path_halbb_d1)/halbb.o \ + $(path_halbb_d1)/halbb_api.o \ + $(path_halbb_d1)/halbb_rua_tbl.o \ + $(path_halbb_d1)/halbb_auto_dbg.o\ + $(path_halbb_d1)/halbb_cfo_trk.o \ + $(path_halbb_d1)/halbb_ch_info.o \ + $(path_halbb_d1)/halbb_cmn_rpt.o \ + $(path_halbb_d1)/halbb_dbcc.o \ + $(path_halbb_d1)/halbb_dbg.o \ + $(path_halbb_d1)/halbb_dbg_cmd.o \ + $(path_halbb_d1)/halbb_dfs.o \ + $(path_halbb_d1)/halbb_edcca.o \ + $(path_halbb_d1)/halbb_env_mntr.o \ + $(path_halbb_d1)/halbb_hw_cfg.o \ + $(path_halbb_d1)/halbb_init.o \ + $(path_halbb_d1)/halbb_interface.o \ + $(path_halbb_d1)/halbb_la_mode.o \ + $(path_halbb_d1)/halbb_math_lib.o \ + $(path_halbb_d1)/halbb_mp.o \ + $(path_halbb_d1)/halbb_plcp_gen.o \ + $(path_halbb_d1)/halbb_plcp_tx.o \ + $(path_halbb_d1)/halbb_pmac_setting.o \ + $(path_halbb_d1)/halbb_psd.o \ + $(path_halbb_d1)/halbb_physts.o \ + $(path_halbb_d1)/halbb_pwr_ctrl.o \ + $(path_halbb_d1)/halbb_ra.o \ + $(path_halbb_d1)/halbb_statistics.o \ + $(path_halbb_d1)/halbb_ant_div.o \ + $(path_halbb_d1)/halbb_dig.o \ + $(path_halbb_d1)/halbb_fwofld.o \ + $(path_halbb_d1)/halbb_dyn_csi_rsp.o + +ifeq ($(CONFIG_RTL8852A), y) +ic := 8852a +# Level 2 directory +path_halbb_8852a := $(path_halbb_d1)/halbb_$(ic) + +halbb-y += $(path_halbb_8852a)/halbb_8852a.o \ + $(path_halbb_8852a)/halbb_8852a_api.o \ + $(path_halbb_8852a)/halbb_hwimg_8852a.o \ + $(path_halbb_8852a)/halbb_reg_cfg_8852a.o +endif + +ifeq ($(CONFIG_RTL8852A), y) +ic := 8852a_2 +# Level 2 directory +path_halbb_8852a_2 := $(path_halbb_d1)/halbb_$(ic) + +halbb-y += $(path_halbb_8852a_2)/halbb_8852a_2.o \ + $(path_halbb_8852a_2)/halbb_8852a_2_api.o \ + $(path_halbb_8852a_2)/halbb_hwimg_8852a_2.o \ + $(path_halbb_8852a_2)/halbb_reg_cfg_8852a_2.o +endif + +ifeq ($(CONFIG_RTL8852B), y) +ic := 8852b +# Level 2 directory +path_halbb_8852b := $(path_halbb_d1)/halbb_$(ic) + +halbb-y += $(path_halbb_8852b)/halbb_8852b.o \ + $(path_halbb_8852b)/halbb_8852b_api.o \ + $(path_halbb_8852b)/halbb_hwimg_8852b.o \ + $(path_halbb_8852b)/halbb_reg_cfg_8852b.o +endif + +ifeq ($(CONFIG_RTL8852C), y) +ic := 8852c +# Level 2 directory +path_halbb_8852c := $(path_halbb_d1)/halbb_$(ic) + +halbb-y += $(path_halbb_8852c)/halbb_8852c.o \ + $(path_halbb_8852c)/halbb_8852c_api.o \ + $(path_halbb_8852c)/halbb_hwimg_8852c.o \ + $(path_halbb_8852c)/halbb_reg_cfg_8852c.o +endif + +_HAL_BB_FILES += $(halbb-y) diff --git a/phl/hal_g6/phy/bb/halbb.c b/phl/hal_g6/phy/bb/halbb.c new file mode 100644 index 0000000..5905936 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb.c @@ -0,0 +1,1061 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u64 pre_support_ability, one = 1; + u64 comp = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + + pre_support_ability = bb->support_ability; + comp = bb->support_ability; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n================================\n"); + + if (val[0] == 100) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[Supportability] Selection\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "00. (( %s ))RA\n", + ((comp & BB_RA) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "01. (( %s ))FA_CNT\n", + ((comp & BB_FA_CNT) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "02. (( %s ))RSSI_MNTR\n", + ((comp & HALBB_FUN_RSVD_2) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "03. (( %s ))DFS\n", + ((comp & BB_DFS) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "04. (( %s ))EDCCA\n", + ((comp & BB_EDCCA) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "05. (( %s ))ENV_MNTR\n", + ((comp & BB_ENVMNTR) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "06. (( %s ))CFO_TRK\n", + ((comp & BB_CFO_TRK) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "07. (( %s ))PWR_CTRL\n", + ((comp & BB_PWR_CTRL) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "10. (( %s ))ANT_DIV\n", + ((comp & DBG_ANT_DIV) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "11. (( %s ))DIG\n", + ((comp & BB_DIG) ? ("V") : ("."))); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "31. (( %s ))Dyn CSI RSP\n", + ((comp & BB_DCR) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (val[0] == 101) { + bb->support_ability = 0; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Disable all support_ability components\n"); + } else { + if (val[1] == 1) { /* @enable */ + bb->support_ability |= (one << val[0]); + } else if (val[1] == 2) {/* @disable */ + bb->support_ability &= ~(one << val[0]); + } else { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[Warning!!!] 1:enable, 2:disable\n"); + } + } + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "pre-supportability = 0x%llx\n", pre_support_ability); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Cur-supportability = 0x%llx\n", bb->support_ability); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; +} + +bool halbb_sta_info_init(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info) +{ + struct bb_sta_info *bb_sta; + + if (!bb) { + BB_WARNING("[%s]*bb = NULL\n", __func__); + return false; + } + + if (!phl_sta_info) + return false; + + if (!phl_sta_info->hal_sta) + return false; + + bb_sta = halbb_mem_alloc(bb, sizeof(struct bb_sta_info)); + + if (!bb_sta) { + BB_WARNING("*bb_sta = NULL\n"); + return RTW_HAL_STATUS_BB_INIT_FAILURE; + } + phl_sta_info->hal_sta->bb_sta = (void *)bb_sta; + + return true; +} + +bool halbb_sta_info_deinit(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info) +{ + if (!bb) { + BB_WARNING("*bb = NULL\n"); + return false; + } + + if (!phl_sta_info) + return false; + + if (!phl_sta_info->hal_sta) + return false; + + if (!phl_sta_info->hal_sta->bb_sta) + return false; + + halbb_mem_free(bb, phl_sta_info->hal_sta->bb_sta, sizeof(struct bb_sta_info)); + return true; +} + +bool halbb_sta_info_add_entry(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info) +{ + if (!bb) { + BB_WARNING("[%s]*bb = NULL\n", __func__); + return false; + } + + if (!phl_sta_info) + return false; + + if ((phl_sta_info->macid) >= PHL_MAX_STA_NUM) + return false; + + bb->phl2bb_macid_table[phl_sta_info->macid] = (u8)phl_sta_info->macid; + bb->phl_sta_info[phl_sta_info->macid] = phl_sta_info; + + return true; +} + +bool halbb_sta_info_delete_entry(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info) +{ + if (!bb) { + BB_WARNING("*bb = NULL\n"); + return false; + } + + if (!phl_sta_info) + return false; + + if ((phl_sta_info->macid) >= PHL_MAX_STA_NUM) + return false; + + if (!phl_sta_info->hal_sta) + return false; + + if (!phl_sta_info->hal_sta->bb_sta) + return false; + + bb->sta_exist[phl_sta_info->macid] = false; + bb->phl_sta_info[phl_sta_info->macid] = NULL; + + return true; +} + +void halbb_media_status_update(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info, + bool is_connected) +{ + bb->sta_exist[phl_sta_info->macid] = is_connected; + + /*Reset MA RSSI*/ + if (!is_connected) { + phl_sta_info->hal_sta->rssi_stat.rssi = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ma = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[0] = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[1] = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[2] = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[3] = 0; + phl_sta_info->hal_sta->rssi_stat.pkt_cnt_data = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_bcn = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_bcn_ma = 0; + phl_sta_info->hal_sta->rssi_stat.pkt_cnt_bcn = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_ofdm = 0; + phl_sta_info->hal_sta->rssi_stat.rssi_cck = 0; + phl_sta_info->hal_sta->rssi_stat.snr_ma = 0; + } else { + phl_sta_info->hal_sta->rssi_stat.ma_factor = RSSI_MA_L; + phl_sta_info->hal_sta->rssi_stat.ma_factor_bcn = RSSI_MA_L; + } +} + +void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal = bb->hal_com; + struct rtw_phl_stainfo_t *phl_sta; + struct rtw_rssi_info *rssi_t = NULL; + struct rtw_ra_sta_info *ra; + char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + u32 val[10] = {0}; + u32 tmp = 0; + u16 curr_tx_rt = 0; + u8 i = 0, j = 0; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "all\n"); + return; + } + + if (_os_strcmp(input[1], "all") == 0) { + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + " Assoc_sta_cnt=%d\n\n", hal->assoc_sta_cnt); + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!bb->sta_exist[i]) + continue; + + phl_sta = bb->phl_sta_info[i]; + + if (!is_sta_active(phl_sta)) + continue; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%d][active=%d] PHL_macid=%d =====================\n", + i, phl_sta->active, phl_sta->macid); + + rssi_t = &phl_sta->hal_sta->rssi_stat; + + halbb_print_sign_frac_digit(bb, rssi_t->rssi_ma, 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Data] rssi_avg=%s, MA=1/%02d\n", + dbg_buf, 1 << rssi_t->ma_factor); + + for (j = 0; j < HALBB_MAX_PATH; j++) { + halbb_print_sign_frac_digit(bb, rssi_t->rssi_ma_path[j], 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + " rssi[%d]= %s\n", j, dbg_buf); + } + + halbb_print_sign_frac_digit(bb, rssi_t->rssi_bcn_ma, 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Bcn] rssi_avg=%s, MA=1/%02d\n", + dbg_buf, 1 << rssi_t->ma_factor_bcn); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rssi_cck=%02d.%d, rssi_ofdm=%02d.%d\n", + rssi_t->rssi_cck >> 1, (rssi_t->rssi_cck & 1) * 5, + rssi_t->rssi_ofdm >> 1, (rssi_t->rssi_ofdm & 1) * 5); + + halbb_print_sign_frac_digit(bb, rssi_t->snr_ma, 16, 4, dbg_buf, HALBB_SNPRINT_SIZE_S); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "SNR_avg=%s dB\n", dbg_buf); + + ra = &phl_sta->hal_sta->ra_info; + curr_tx_rt = (u16)(ra->rpt_rt_i.mcs_ss_idx) | ((u16)(ra->rpt_rt_i.mode) << 7); + + halbb_print_rate_2_buff(bb, curr_tx_rt, ra->rpt_rt_i.gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Tx_Rate=%s (0x%x-%d), PER=(%d), TXBW=(%d)\n", + bb->dbg_buf, curr_tx_rt, ra->rpt_rt_i.gi_ltf, + ra->curr_retry_ratio, (20 << ra->rpt_rt_i.bw)); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "======================================\n"); + + } + } +} + +void halbb_traffic_load_decision(struct bb_info *bb) +{ + struct rtw_stats *stat = &bb->phl_com->phl_stats; + struct bb_link_info *link = &bb->bb_link_i; + u32 max_tp; /*Mbps*/ + + /*@---TP & Trafic-load caln---*/ + link->tx_tp = KB_2_MB(stat->tx_tp_kbits); + link->rx_tp = KB_2_MB(stat->rx_tp_kbits); + link->total_tp = link->tx_tp + link->rx_tp; + max_tp = MAX_2(link->tx_tp, link->rx_tp); /*Mbps*/ + + BB_DBG(bb, DBG_COMMON_FLOW, + "byte_uni{tx,rx}={%llu,%llu}, byte_total{tx,rx}={%llu,%llu}\n", + stat->tx_byte_uni, stat->rx_byte_uni, + stat->tx_byte_total, stat->rx_byte_total); + + BB_DBG(bb, DBG_COMMON_FLOW, + "TP_kbit{tx,rx}={%d,%d}, TP_MA{tx,rx}={%d,%d}\n", + stat->tx_tp_kbits, stat->rx_tp_kbits, + stat->tx_moving_average_tp, stat->rx_moving_average_tp); + + /*@[Calculate TX/RX state]*/ + if (link->tx_tp > (link->rx_tp << 1)) + link->txrx_state_all = BB_TX_STATE; + else if (link->rx_tp > (link->tx_tp << 1)) + link->txrx_state_all = BB_RX_STATE; + else + link->txrx_state_all = BB_BI_DIR_STATE; + + /*@[Traffic load decision]*/ + link->traffic_load_pre = link->traffic_load; + + if (max_tp > 20) { + link->traffic_load = TRAFFIC_HIGH; + } else if (max_tp > 5) { + link->traffic_load = TRAFFIC_MID; + } else if (max_tp > 1) { + link->traffic_load = TRAFFIC_LOW; + } else if (stat->tx_tp_kbits > 100 || stat->rx_tp_kbits > 100) { /*100Kb*/ + link->traffic_load = TRAFFIC_ULTRA_LOW; + } else { + link->traffic_load = TRAFFIC_NO_TP; + } + + /*@[Calculate consecutive idlel time]*/ + if (link->traffic_load == TRAFFIC_NO_TP) + link->consecutive_idle_time = 0; + else + link->consecutive_idle_time += HALBB_WATCHDOG_PERIOD; +} + +void halbb_cmn_info_self_reset(struct bb_info *bb) { + + struct bb_link_info *link = &bb->bb_link_i; + + bb->bb_ch_i.rssi_max = 0; + bb->bb_ch_i.rssi_min = 0; + + link->is_one_entry_only = false; + link->one_entry_macid = 0; + link->one_entry_tp = 0; + link->one_entry_tp_active_occur = false; + link->one_entry_tp_pre = 0; + link->num_linked_client_pre = 0; + link->num_active_client_pre = 0; + link->num_linked_client = 0; + link->num_active_client = 0; +} + +u8 halbb_get_rssi_min(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal = bb->hal_com; + struct rtw_phl_stainfo_t *sta; + struct rtw_rssi_info *sta_rssi = NULL; + u8 sta_cnt = 0; + u8 rssi_min = 0xff, rssi_curr = 0; + u32 i = 0; + + if (hal->assoc_sta_cnt == 0) { + BB_WARNING("[%s] assoc_sta_cnt=0\n", __func__); + return 0; + } + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!bb->sta_exist[i]) + continue; + + sta = bb->phl_sta_info[i]; + + if (!is_sta_active(sta)) + continue; + + BB_DBG(bb, DBG_COMMON_FLOW, "[%d] macid=%d\n", i, sta->macid); + + sta_cnt++; + + sta_rssi = &sta->hal_sta->rssi_stat; + + if (sta_rssi->rssi != 0) + rssi_curr = sta_rssi->rssi; + else + rssi_curr = sta_rssi->rssi_bcn; + + /*[RSSI min]*/ + if (rssi_curr <= rssi_min) { + rssi_min = rssi_curr; + } + + BB_DBG(bb, DBG_COMMON_FLOW, + "rssi_min = %d", rssi_min); + + if (sta_cnt >= hal->assoc_sta_cnt) + break; + } + + if (sta_cnt == 0) { + BB_WARNING("[%s] sta_cnt=0\n", __func__); + return 0; + } + + return rssi_min; +} + +void halbb_cmn_info_self_update(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal = bb->hal_com; + struct bb_link_info *link = &bb->bb_link_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + struct rtw_phl_stainfo_t *sta; + struct rtw_rssi_info *sta_rssi = NULL; + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + u8 sta_cnt = 0, num_active_client = 0; + u8 rssi_min = 0xff, rssi_max = 0, rssi_curr = 0; + u8 mcc_rssi_min[MCC_BAND_NUM], mcc_sta_cnt[MCC_BAND_NUM]; + u8 j = 0, band_idx = MCC_BAND_NUM, role_ch = 0; + u32 i = 0, one_entry_macid_tmp = 0; + u32 trx_tp = 0; + u32 tp_diff = 0; + + /*[Link Status Check]*/ + link->is_linked = (hal->assoc_sta_cnt != 0) ? true : false; + link->first_connect = link->is_linked && !link->is_linked_pre; + link->first_disconnect = !link->is_linked && link->is_linked_pre; + link->is_linked_pre = link->is_linked; + + BB_DBG(bb, DBG_COMMON_FLOW, "is_linked = %d, 1st_connect=%d, 1st_disconnect=%d, assoc_sta_cnt=%d\n", + link->is_linked, link->first_connect, + link->first_disconnect, hal->assoc_sta_cnt); + + /*[Traffic load information]*/ + halbb_traffic_load_decision(bb); + + link->rx_rate_plurality = halbb_get_plurality_rx_rate_su(bb); + link->rx_rate_plurality_mu = halbb_get_plurality_rx_rate_mu(bb); + + if (!link->is_linked) { + if (link->first_disconnect) + halbb_cmn_info_self_reset(bb); + + return; + } + + if (mcc_dm->mcc_status_en) { + for (i = 0; i < MCC_BAND_NUM; i++) { + mcc_rssi_min[i] = rssi_min; + mcc_sta_cnt[i] = 0; + } + } + + bb->bb_ch_i.pre_rssi_min = bb->bb_ch_i.rssi_min; + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!bb->sta_exist[i]) + continue; + + sta = bb->phl_sta_info[i]; + + if (!is_sta_active(sta)) + continue; + + if ((dev->rfe_type >= 50) && (sta->macid == 0)) + continue; + + BB_DBG(bb, DBG_COMMON_FLOW, "[%d] macid=%d\n", i, sta->macid); + + sta_cnt++; + + if (sta_cnt == 1) + one_entry_macid_tmp = i; + + trx_tp = KB_2_MB(sta->stats.tx_tp_kbits + + sta->stats.rx_tp_kbits); /*Mbit*/ + + sta_rssi = &sta->hal_sta->rssi_stat; + + if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) { + rssi_curr = sta_rssi->rssi_bcn; + } else { + if (sta_rssi->rssi == 0 && sta_rssi->rssi_bcn != 0) + rssi_curr = sta_rssi->rssi_bcn; + else + rssi_curr = sta_rssi->rssi; + } + + if (sta_rssi->pkt_cnt_data > 100) + sta_rssi->ma_factor = RSSI_MA_H; + else if (sta_rssi->pkt_cnt_data > 20) + sta_rssi->ma_factor = RSSI_MA_M; + else if (sta_rssi->pkt_cnt_data > 5) + sta_rssi->ma_factor = RSSI_MA_L; + else + sta_rssi->ma_factor = RSSI_MA_UL; + + if (sta_rssi->pkt_cnt_bcn > 5) + sta_rssi->ma_factor_bcn = RSSI_MA_L; + else + sta_rssi->ma_factor_bcn = RSSI_MA_UL; + + BB_DBG(bb, DBG_COMMON_FLOW, + "pkt_cnt_data=%d, pkt_cnt_bcn=%d, ma_factor=%d, ma_factor_bcn=%d\n", + sta_rssi->pkt_cnt_data, sta_rssi->pkt_cnt_bcn, + sta_rssi->ma_factor, sta_rssi->ma_factor_bcn); + + sta_rssi->pkt_cnt_data = 0; + sta_rssi->pkt_cnt_bcn = 0; + + BB_DBG(bb, DBG_COMMON_FLOW, + "rssi = %d, rssi_ma = %d", + sta->hal_sta->rssi_stat.rssi, + sta->hal_sta->rssi_stat.rssi_ma); + + /*[RSSI min]*/ + if (rssi_curr <= rssi_min) { + bb->bb_ch_i.rssi_min = rssi_curr; + bb->bb_ch_i.rssi_min_macid = sta->macid; + rssi_min = rssi_curr; + } + /*[RSSI max]*/ + if (rssi_curr >= rssi_max) { + bb->bb_ch_i.rssi_max = rssi_curr; + bb->bb_ch_i.rssi_max_macid = sta->macid; + rssi_max = rssi_curr; + } + + //BB_DBG(bb, DBG_COMMON_FLOW, "TP: TRX=%d Mb/sec\n", trx_tp); + + //BB_DBG(bb, DBG_COMMON_FLOW, "TP: TX=%d, RX=%d, kb/sec\n", + // sta->stats.tx_tp_kbits, sta->stats.rx_tp_kbits); + + BB_DBG(bb, DBG_COMMON_FLOW, + "rssi_min = %d, rssi_max = %d", rssi_min, rssi_max); + + if (mcc_dm->mcc_status_en) { + if (i == mcc_dm->softap_macid) + continue; + + band_idx = MCC_BAND_NUM; + role_ch = sta->wrole->chandef.center_ch; + + for (j = 0; j < MCC_BAND_NUM; j++) { + if (mcc_dm->mcc_rf_ch[j].center_ch == role_ch) { + band_idx = j; + break; + } + } + + if (band_idx == MCC_BAND_NUM) { + BB_WARNING("%s, band_idx = %d", __func__, + band_idx); + continue; + } + + if (rssi_curr <= mcc_rssi_min[band_idx]) + mcc_rssi_min[band_idx] = rssi_curr; + + mcc_sta_cnt[band_idx]++; + } + + if (trx_tp > ACTIVE_TP_THRESHOLD) + num_active_client++; + + if (sta_cnt >= bb->hal_com->assoc_sta_cnt) + break; + } + + if (mcc_dm->mcc_status_en) { + for (i = 0; i < MCC_BAND_NUM; i++) { + mcc_dm->rssi_min[i] = mcc_rssi_min[i]; + mcc_dm->sta_cnt[i] = mcc_sta_cnt[i]; + } + } + + + link->is_one_entry_only = (hal->assoc_sta_cnt == 1) ? true : false; + + if (link->is_one_entry_only) { + link->one_entry_macid = one_entry_macid_tmp; + link->one_entry_tp = trx_tp; + link->one_entry_tp_active_occur = false; + + //BB_DBG(bb, DBG_COMMON_FLOW, "one_entry_tp=((%d)), one_entry_tp_pre=((%d))\n", + // link->one_entry_tp, link->one_entry_tp_pre); + + if (link->one_entry_tp > link->one_entry_tp_pre && + link->one_entry_tp_pre <= 2) { + tp_diff = link->one_entry_tp - link->one_entry_tp_pre; + + if (tp_diff > link->tp_active_th) + link->one_entry_tp_active_occur = true; + } + + link->one_entry_tp_pre = link->one_entry_tp; + } + + link->num_linked_client_pre = link->num_linked_client; + link->num_active_client_pre = link->num_active_client; + link->num_linked_client = sta_cnt; + link->num_active_client = num_active_client; +} + +void halbb_watchdog_reset(struct bb_info *bb) +{ + +} + +void halbb_update_hal_info(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal = bb->hal_com; + + hal->trx_stat.rx_rate_plurality = bb->bb_link_i.rx_rate_plurality; +} + +void halbb_store_data(struct bb_info *bb) +{ + halbb_cmn_info_rpt_store_data(bb); +} + +void halbb_reset(struct bb_info *bb) +{ + halbb_store_data(bb); + #ifdef HALBB_STATISTICS_SUPPORT + halbb_statistics_reset(bb); + #endif + halbb_cmn_info_rpt_reset(bb); +} + +void halbb_watchdog_normal(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + halbb_cmn_info_self_update(bb); + halbb_ic_hw_setting(bb); + #ifdef HALBB_ENV_MNTR_SUPPORT + halbb_env_mntr(bb); + #endif + #ifdef HALBB_DIG_SUPPORT + halbb_dig(bb); + #endif + #ifdef HALBB_STATISTICS_SUPPORT + halbb_statistics(bb); + #endif + halbb_basic_dbg_message(bb); + halbb_physts_watchdog(bb); + + if (!bb->adv_bb_dm_en) { + BB_DBG(bb, DBG_COMMON_FLOW, "Disable adv halbb dm\n"); + halbb_reset(bb); + return; + } + + #ifdef HALBB_EDCCA_SUPPORT + halbb_edcca(bb); + #endif + #ifdef HALBB_DFS_SUPPORT + halbb_dfs(bb); + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_watchdog(bb); + #endif + #ifdef HALBB_RA_SUPPORT + halbb_ra_watchdog(bb); + #endif + #ifdef HALBB_PWR_CTRL_SUPPORT + halbb_pwr_ctrl(bb); + #endif + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_re_trig_watchdog(bb); + #endif + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antenna_diversity(bb); + #endif + halbb_update_hal_info(bb); + #ifdef HALBB_DIG_MCC_SUPPORT + halbb_mccdm_switch(bb); + #endif + /*[Rest all counter]*/ + halbb_reset(bb); +} + +void halbb_watchdog_low_io(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + halbb_cmn_info_self_update(bb); + halbb_ic_hw_setting_low_io(bb); + halbb_basic_dbg_message(bb); + #ifdef HALBB_DIG_SUPPORT + halbb_dig_lps(bb); + #endif + + #if 0//def HALBB_EDCCA_SUPPORT + halbb_edcca(bb); + #endif + + #if 0//def HALBB_DFS_SUPPORT + halbb_dfs(bb); + #endif + /*[Rest all counter]*/ + halbb_reset(bb); +} + +void halbb_watchdog_non_io(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + halbb_cmn_info_self_update(bb); + halbb_ic_hw_setting_non_io(bb); + halbb_basic_dbg_message(bb); + /*[Rest all counter]*/ + halbb_reset(bb); +} + +void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode, enum phl_phy_idx phy_idx) +{ + +#ifdef HALBB_DBCC_SUPPORT + #ifdef HALBB_DBCC_DVLP_FLAG + if (phy_idx == HW_PHY_1) + return; + #endif + bb = halbb_get_curr_bb_pointer(bb, phy_idx); + BB_DBG(bb, DBG_COMMON_FLOW, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); +#endif + + bb->bb_sys_up_time += BB_WATCH_DOG_PERIOD; + + if ((bb->bb_sys_up_time % bb->bb_watchdog_period) != 0) + return; + + if (bb->bb_dbg_i.cr_recorder_en) + BB_TRACE("[%s] up_time:%d \n", __func__, bb->bb_sys_up_time); + + bb->bb_watchdog_mode = mode; + BB_DBG(bb, DBG_COMMON_FLOW, "mode=%s\n", + ((mode == BB_WATCHDOG_NORMAL) ? "Normal" : + ((mode == BB_WATCHDOG_LOW_IO) ? "LowIO" : "NonIO"))); + + /*=== [HALBB Watchdog] ===============================================*/ + + if (mode == BB_WATCHDOG_NORMAL) { + if(phl_is_mp_mode(bb->phl_com)) { + BB_WARNING("[%s] mode=%d", __func__, + bb->phl_com->drv_mode); + return; + } + halbb_watchdog_normal(bb, phy_idx); + } else if (mode == BB_WATCHDOG_LOW_IO) { + halbb_watchdog_low_io(bb, phy_idx); + } else { /*if (mode == BB_WATCHDOG_NON_IO)*/ + halbb_watchdog_non_io(bb, phy_idx); + } + + if (bb->bb_dbg_i.cr_recorder_en) + BB_TRACE("[%s] end\n", __func__); +} + +void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx) +{ + enum halbb_event_idx_t event_idx = *((enum halbb_event_idx_t *)bb_cmd); + + BB_DBG(bb, DBG_COMMON_FLOW, "[%s][phy_idx=%d] event_idx=%d\n", __func__, phy_idx, event_idx); + + if (event_idx == BB_EVENT_TIMER_DIG) { + #ifdef HALBB_DIG_TDMA_SUPPORT + halbb_tdmadig_io_en(bb); + #endif + } else if (event_idx == BB_EVENT_TIMER_CFO) { + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_acc_io_en(bb); + #endif + } else if (event_idx == BB_EVENT_TIMER_ANTDIV) { + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antdiv_io_en(bb); + #endif + } else if (event_idx == BB_EVENT_TIMER_TDMA_CR) { + #ifdef HALBB_TDMA_CR_SUPPORT + halbb_tdma_cr_sel_io_en(bb); + #endif + } else if (event_idx == BB_EVENT_TIMER_LA) { + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_io_en(bb); + #endif + } else { + BB_WARNING("[%s] event_idx=%d\n", __func__, event_idx); + } +} + +u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func, + enum halbb_pause_type pause_type, + enum halbb_pause_lv_type lv, + u8 val_lehgth, + u32 *val_buf) +{ + struct bb_func_hooker_info *func_t = &bb->bb_cmn_hooker->bb_func_hooker_i; + s8 *pause_lv_pre = &bb->u8_dummy; + u32 *bkp_val = &bb->u32_dummy; + u32 ori_val[5] = {0}; + u64 pause_func_bitmap = (u64)BIT(pause_func); + u8 i = 0; + u8 pause_result = PAUSE_FAIL; + + BB_DBG(bb, DBG_DBG_API, "[%s][%s] LV=%d, Len=%d\n", __func__, + ((pause_type == HALBB_PAUSE) ? "Pause" : + ((pause_type == HALBB_RESUME) ? "Resume" : + ((pause_type == HALBB_PAUSE_NO_SET) ? "Pause no_set" : "Resume_no_recovery"))), + lv, val_lehgth); + + if (lv >= HALBB_PAUSE_MAX_NUM) { + BB_WARNING("[%s] LV=%d\n", __func__, lv); + return PAUSE_FAIL; + } + if (pause_func == F_CFO_TRK) { + BB_DBG(bb, DBG_DBG_API, "[CFO]\n"); + + if (val_lehgth > 1) { + BB_WARNING("CFO length > 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(bb->bb_cfo_trk_i.crystal_cap); //which value? + pause_lv_pre = &bb->pause_lv_table.lv_cfo; + bkp_val = (u32 *)(&bb->bb_cfo_trk_i.rvrt_val); + /*@function pointer hook*/ + func_t->pause_bb_dm_handler = halbb_set_cfo_pause_val; + } +#ifdef HALBB_DIG_SUPPORT + else if (pause_func == F_DIG) { + BB_DBG(bb, DBG_DBG_API, "[DIG]\n"); + + if (val_lehgth > DIG_PAUSE_INFO_SIZE) { + BB_WARNING("DIG length > %d\n", DIG_PAUSE_INFO_SIZE); + return PAUSE_FAIL; + } + /* {equivalent_rssi, en_pause_by_igi, en_pause_by_pd_low} */ + ori_val[0] = (u32)(RSSI_MAX - bb->bb_dig_i.p_cur_dig_unit->igi_fa_rssi); + ori_val[1] = val_buf[1]; + pause_lv_pre = &bb->pause_lv_table.lv_dig; + bkp_val = (u32 *)(&bb->bb_dig_i.rvrt_val); + /*@function pointer hook*/ + func_t->pause_bb_dm_handler = halbb_set_dig_pause_val; + } +#endif +#ifdef HALBB_EDCCA_SUPPORT + else if (pause_func == F_EDCCA) { + BB_DBG(bb, DBG_DBG_API, "[EDCCA]\n"); + + if (val_lehgth > 1) { + BB_WARNING("EDCCA length > 1\n"); + return PAUSE_FAIL; + } + ori_val[0] = (u32)(bb->bb_edcca_i.th_h); + pause_lv_pre = &bb->pause_lv_table.lv_edcca; + bkp_val = (u32 *)(&bb->bb_edcca_i.rvrt_val); + /*@function pointer hook*/ + func_t->pause_bb_dm_handler = halbb_set_edcca_pause_val; + } +#endif + else { + BB_WARNING("Error func idx\n"); + return PAUSE_FAIL; + } + + BB_DBG(bb, DBG_DBG_API, "Pause_LV{new , pre} = {%d ,%d}\n", + lv, *pause_lv_pre); + + if (pause_type == HALBB_PAUSE || pause_type == HALBB_PAUSE_NO_SET) { + if (lv <= *pause_lv_pre) { + BB_DBG(bb, DBG_DBG_API, "[PAUSE FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if (!(bb->pause_ability & pause_func_bitmap)) { + for (i = 0; i < val_lehgth; i++) + bkp_val[i] = ori_val[i]; + } + + bb->pause_ability |= pause_func_bitmap; + BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability); + + if (pause_type == HALBB_PAUSE) { + for (i = 0; i < val_lehgth; i++) + BB_DBG(bb, DBG_DBG_API, + "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n", + i, val_buf[i], bkp_val[i]); + + func_t->pause_bb_dm_handler(bb, val_buf, val_lehgth); + } else { + for (i = 0; i < val_lehgth; i++) + BB_DBG(bb, DBG_DBG_API, + "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n", + i, bkp_val[i]); + } + + *pause_lv_pre = lv; + pause_result = PAUSE_SUCCESS; + } else if (pause_type == HALBB_RESUME) { + if (lv < *pause_lv_pre) { + BB_DBG(bb, DBG_DBG_API, "[Resume FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if ((bb->pause_ability & pause_func_bitmap) == 0) { + BB_DBG(bb, DBG_DBG_API, "[RESUME] No Need to Revert\n"); + return PAUSE_SUCCESS; + } + + bb->pause_ability &= ~pause_func_bitmap; + BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability); + + *pause_lv_pre = HALBB_PAUSE_RELEASE; + + for (i = 0; i < val_lehgth; i++) { + BB_DBG(bb, DBG_DBG_API, + "[RESUME] val_idx[%d]={0x%x}\n", i, bkp_val[i]); + } + + func_t->pause_bb_dm_handler(bb, bkp_val, val_lehgth); + + pause_result = PAUSE_SUCCESS; + } else if (pause_type == HALBB_RESUME_NO_RECOVERY) { + if (lv < *pause_lv_pre) { + BB_DBG(bb, DBG_DBG_API, "[Resume FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if ((bb->pause_ability & pause_func_bitmap) == 0) { + BB_DBG(bb, DBG_DBG_API, "[RESUME] No Need to Revert\n"); + return PAUSE_SUCCESS; + } + + bb->pause_ability &= ~pause_func_bitmap; + BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability); + + *pause_lv_pre = HALBB_PAUSE_RELEASE; + + pause_result = PAUSE_SUCCESS; + } else { + BB_WARNING("error pause_type\n"); + pause_result = PAUSE_FAIL; + } + + return pause_result; +} + +void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 i; + u8 len = 0; + u32 buf[5] = {0}; + u8 pause_result = 0; + enum halbb_pause_type type = 0; + enum halbb_pause_lv_type lv = 0; + u8 halbb_ary_size = bb->bb_cmn_hooker->bb_dm_number; + enum habb_fun_t id = F_DEFAULT; + + /* ==== [Help] ====]*/ + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{Func} {p:pause, pn:pause_no_set, r:Resume, rnc: Resume_no_recov} {lv:0~3} Val[0],...,Val[5]\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{dig} {p/pn/r} {lv} {Pwr(|dBm|),hex} {0:apply to ofdm, 1:apply to cck and ofdm}\n"); + for (i = 0; i < halbb_ary_size; i++) + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "*%s\n", halbb_func_i[i].name); + return; + } + /* ==== [Function] ====]*/ + for (i = 0; i < halbb_ary_size; i++) { + if (_os_strcmp(halbb_func_i[i].name, input[1]) == 0) { + id = halbb_func_i[i].id; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%s]===>\n", halbb_func_i[i].name); + break; + } + } + + if (i == halbb_ary_size) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Func not found!\n"); + return; + } + /* ==== [Type] ====]*/ + if (_os_strcmp(input[2], "p") == 0) { + type = HALBB_PAUSE; + } else if (_os_strcmp(input[2], "pn") == 0) { + type = HALBB_PAUSE_NO_SET; + } else if (_os_strcmp(input[2], "r") == 0) { + type = HALBB_RESUME; + } else if (_os_strcmp(input[2], "rnc") == 0) { + type = HALBB_RESUME_NO_RECOVERY; + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + + for (i = 1; i < 10; i++) { + HALBB_SCAN(input[i + 1], DCMD_HEX, &val[i]); + } + + lv = (enum halbb_pause_lv_type)val[2]; + + for (i = 0; i < 5; i++) + buf[i] = val[3 + i]; + + if (id == F_CFO_TRK) { + len = 1; + } else if (id == F_DIG) { + len = DIG_PAUSE_INFO_SIZE; + } else if (id == F_EDCCA) { + len = 1; + } else { + return; + } + + if (len) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{%s in lv=%d}, pause_val = {%d, %d}\n", + ((type == HALBB_PAUSE) ? "Pause" : + ((type == HALBB_RESUME) ? "Resume" : "Pause no set")), + lv, val[3], val[4]); + + pause_result = halbb_pause_func(bb, id, type, lv, len, buf); + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set %s\n", (pause_result) ? "Success" : "Fail"); +} diff --git a/phl/hal_g6/phy/bb/halbb.h b/phl/hal_g6/phy/bb/halbb.h new file mode 100644 index 0000000..75e2a79 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb.h @@ -0,0 +1,395 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALBB_H__ +#define __HALBB_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +#define ACTIVE_TP_THRESHOLD 1 +#define BB_WATCH_DOG_PERIOD 2 /*sec*/ +#define is_sta_active(sta) ((sta) && (sta->active)) +#define HALBB_SNPRINT_SIZE 200 +#define HALBB_SNPRINT_SIZE_S 20 + +#define BB_EFUSE_BAND_NUM 5 +#define IC_LNA_NUM 7 +#define IC_TIA_NUM 2 +#define EFUSE_OFST_NUM 1 + +/*@--------------------------[Enum]------------------------------------------*/ + +enum bb_trx_state_t { + BB_TX_STATE = 0, + BB_RX_STATE = 1, + BB_BI_DIR_STATE = 2 +}; + +enum bb_trafic_t { + TRAFFIC_NO_TP = 0, + TRAFFIC_ULTRA_LOW = 1, + TRAFFIC_LOW = 2, + TRAFFIC_MID = 3, + TRAFFIC_HIGH = 4 +}; + +enum efuse_bit_mask { + LOW_MASK = 0, + HIGH_MASK = 1 +}; +/*@--------------------------[Structure]-------------------------------------*/ + +struct halbb_pause_lv { + s8 lv_dig; + s8 lv_cfo; + s8 lv_edcca; +}; + +struct bb_func_hooker_info { + void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len); +}; + +struct bb_iot_info { + u8 is_linked_cmw500:1; + u8 patch_id_00000000:1; + u8 rsvd:6; +}; + +struct bb_path_info { + /*[Path info]*/ + u8 tx_path_en; /*TX path enable*/ + u8 rx_path_en; /*RX path enable*/ + #ifdef HALBB_COMPILE_ABOVE_4SS + enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/ + #endif + #ifdef HALBB_COMPILE_ABOVE_3SS + enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/ + #endif + #ifdef HALBB_COMPILE_ABOVE_2SS + enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/ + #endif + enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/ +}; + +struct bb_link_info { + /*[Link Info]*/ + bool is_linked; + bool is_linked_pre; + bool first_connect; + bool first_disconnect; + enum bb_trx_state_t txrx_state_all; + /*[One Entry TP Info]*/ + bool is_one_entry_only; + u32 one_entry_macid; + u32 one_entry_tp; + u32 one_entry_tp_pre; + u16 tp_active_th; + bool one_entry_tp_active_occur; + bool is_match_bssid; + /*[Client Number]*/ + u8 num_linked_client; + u8 num_linked_client_pre; + u8 num_active_client; + u8 num_active_client_pre; + /*[TP & Traffic]*/ + u8 traffic_load; + u8 traffic_load_pre; + u16 tx_rate; + u16 rx_rate_plurality; + u16 rx_rate_plurality_mu; + u32 tx_tp; /*@Mbps*/ + u32 rx_tp; /*@Mbps*/ + u32 total_tp; /*@Mbps*/ + u16 consecutive_idle_time; /*@unit: second*/ +}; + +struct bb_ch_info { + u8 rssi_min; + u16 rssi_min_macid; + u8 pre_rssi_min; + u8 rssi_max; + u16 rssi_max_macid; + u8 rxsc_160; + u8 rxsc_80; + u8 rxsc_40; + u8 rxsc_20; + u8 rxsc_l; + u8 is_noisy; + u8 rf_central_ch_cfg; /*report in phy-sts*/ +}; + +struct bb_cmn_backup_info { + u8 cur_tx_path; + u8 cur_rx_path; + s16 cur_tx_pwr; + u8 cur_pd_lower_bound; + u8 last_rssi; + struct rssi_physts last_rssi_rpt; + struct rxevm_physts last_rxevm_rpt; +}; + +struct bb_gain_info { + s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM]; + s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM]; + s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM]; + s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH]; + s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40]; + s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80]; +}; + +struct bb_efuse_info{ + bool normal_efuse_check; + bool hidden_efuse_check; + s8 gain_offset[HALBB_MAX_PATH][BB_EFUSE_BAND_NUM]; // S(8,0) + s8 gain_cs[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0) + s8 gain_cg[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0) + + s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2) + s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2) + + s8 frontend_loss[HALBB_MAX_PATH]; + s8 rpl_bias_comp[HALBB_MAX_PATH]; + s8 rssi_bias_comp[HALBB_MAX_PATH]; + + s8 efuse_ofst; // 8852A:S(5,2) 8852B:S(8,4) + s8 efuse_ofst_tb; // 8852A:S(7,4) 8852B:S(8,4) +}; + +struct bb_cmn_info { + u8 bb_dm_number; +#ifdef HALBB_PSD_SUPPORT + struct bb_psd_info bb_psd_i; +#endif +#ifdef HALBB_LA_MODE_SUPPORT + struct bb_la_mode_info bb_la_mode_i; +#endif +#ifdef HALBB_DYN_CSI_RSP_SUPPORT + struct bf_ch_raw_info bf_ch_raw_i; +#endif + struct bb_echo_cmd_info bb_echo_cmd_i; + struct bb_func_hooker_info bb_func_hooker_i; +}; + +#ifdef HALBB_DIG_MCC_SUPPORT +#define PD_IDX_MIN 0 +#define NUM_MAX_IGI_CNT 7 +#define INVALID_INIT_VAL 0xff + +/*For 2G/5G/6G*/ +enum mcc_band { + MCC_BAND_1 = 0, + MCC_BAND_2, + MCC_BAND_NUM +}; + +struct halbb_mcc_dm { + bool mcc_pre_status_en; + u8 mcc_reg_id[NUM_MAX_IGI_CNT]; + u8 sta_cnt[MCC_BAND_NUM]; + u16 mcc_dm_reg[NUM_MAX_IGI_CNT]; + u16 mcc_dm_mask[NUM_MAX_IGI_CNT]; + u16 mcc_dm_val[NUM_MAX_IGI_CNT][MCC_BAND_NUM]; + /*mcc DIG*/ + u8 rssi_min[MCC_BAND_NUM]; + + /* need to be config by driver*/ + bool mcc_status_en; + u8 softap_macid; + struct rtw_chan_def mcc_rf_ch[MCC_BAND_NUM]; + +}; +/** + * @struct _mcc_h2c_ + * @brief _mcc_h2c_ + * + */ + struct mcc_h2c_reg_content { + // MCCDM + u8 addr_lsb; + u8 addr_msb; + u8 bmask_lsb; + u8 bmask_msb; + u8 val_lsb; + u8 val_msb; +}; + +struct mcc_h2c { + // MCCDM + u8 reg_cnt; + u8 mcc_dm_en: 1; + u8 mcc_ch_idx: 1; + u8 mcc_set: 1; + u8 phy0_en: 1; + u8 phy1_en: 1; + u8 rsvd0: 3; + u8 ch_lsb; + u8 ch_msb; + struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_IGI_CNT]; +}; +#endif + +struct bb_info { + struct rtw_phl_com_t *phl_com; + struct rtw_hal_com_t *hal_com; + struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM]; + u8 phl2bb_macid_table[PHL_MAX_STA_NUM]; + bool sta_exist[PHL_MAX_STA_NUM]; + /*[DBCC]*/ +#ifdef HALBB_DBCC_SUPPORT + struct bb_info *bb_phy_hooker; +#endif + enum phl_phy_idx bb_phy_idx; + struct bb_cmn_info *bb_cmn_hooker; + /*[Common Info]*/ + struct bb_gain_info bb_gain_i; + struct bb_efuse_info bb_efuse_i; + enum bb_ic_t ic_type; + enum bb_cr_t cr_type; + u8 num_rf_path; + /*[System Info]*/ + enum bb_watchdog_mode_t bb_watchdog_mode; + bool bb_cmn_info_init_ready; + bool bb_dm_init_ready; + u32 bb_sys_up_time; + bool bb_watchdog_en; + u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/ + bool bb_ic_api_en; + u8 pre_dbg_priority; + char dbg_buf[HALBB_SNPRINT_SIZE]; + /*[DM Info]*/ + bool is_noisy; + bool adv_bb_dm_en; + u64 support_ability; /*HALBB function Supportability*/ + u64 manual_support_ability; + u64 pause_ability; /*HALBB function pause Supportability*/ + struct halbb_pause_lv pause_lv_table; + /*[FW Info]*/ + u8 fwofld_last_cmd; + u64 fw_dbg_component; + /*[Drv Dbg Info]*/ + u64 dbg_component; + u8 cmn_dbg_msg_period; + u8 cmn_dbg_msg_cnt; + bool is_disable_phy_api; + /*[Dummy]*/ + bool bool_dummy; + u8 u8_dummy; + u16 u16_dummy; + u32 u32_dummy; + /*[Link Info]*/ + enum rf_path tx_path; /*PMAC Tx Path*/ + enum rf_path rx_path; + + /*@=== [HALBB Structure] ============================================*/ +#ifdef BB_8852A_CAV_SUPPORT + struct bb_8852a_info bb_8852a_i; +#endif +#ifdef BB_8852A_2_SUPPORT + struct bb_8852a_2_info bb_8852a_2_i; + struct bb_h2c_fw_cmw bb_fw_cmw_i; +#endif +#ifdef HALBB_RA_SUPPORT + struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM]; +#endif +#ifdef HALBB_ENV_MNTR_SUPPORT + struct bb_env_mntr_info bb_env_mntr_i; +#endif +#ifdef HALBB_EDCCA_SUPPORT + struct bb_edcca_info bb_edcca_i; +#endif +#ifdef HALBB_DFS_SUPPORT + struct bb_dfs_info bb_dfs_i; +#endif +#ifdef HALBB_STATISTICS_SUPPORT + struct bb_stat_info bb_stat_i; +#endif +#ifdef HALBB_DIG_SUPPORT + struct bb_dig_info bb_dig_i; +#endif +#ifdef HALBB_CFO_TRK_SUPPORT + struct bb_cfo_trk_info bb_cfo_trk_i; +#endif +#ifdef HALBB_PHYSTS_PARSING_SUPPORT + struct bb_physts_info bb_physts_i; +#endif +#ifdef HALBB_LA_MODE_SUPPORT + struct bb_la_mode_info bb_la_mode_i; +#endif + +#ifdef HALBB_PWR_CTRL_SUPPORT + struct bb_pwr_ctrl_info bb_pwr_ctrl_i; + struct bb_dyncca_info bb_dyncca_i; +#endif + +#ifdef HALBB_PMAC_TX_SUPPORT + struct bb_plcp_info bb_plcp_i; +#endif + struct bb_link_info bb_link_i; + struct bb_path_info bb_path_i; + struct bb_ch_info bb_ch_i; + struct bb_api_info bb_api_i; + struct bb_iot_info bb_iot_i; + struct bb_dbg_info bb_dbg_i; + struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i; + struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i; + struct bb_h2c_fw_edcca bb_fw_edcca_i; + struct bb_h2c_he_sigb bb_h2c_he_sigb_i; + struct bb_fw_dbg_cmn_info bb_fwdbg_i; + struct bb_cmn_rpt_info bb_cmn_rpt_i; + struct bb_rpt_info bb_rpt_i; + struct rxevm_physts rxevm; + struct bb_cmn_backup_info bb_cmn_backup_i; +#ifdef HALBB_CH_INFO_SUPPORT + struct bb_ch_rpt_info bb_ch_rpt_i; +#endif +#ifdef HALBB_AUTO_DBG_SUPPORT + struct bb_auto_dbg_info bb_auto_dbg_i; +#endif +#ifdef HALBB_ANT_DIV_SUPPORT + struct bb_antdiv_info bb_ant_div_i; +#endif +#ifdef HALBB_DYN_L2H_SUPPORT + struct bb_dyn_l2h_info bb_dyn_l2h_i; +#endif + /*@=== [HALBB Timer] ================================================*/ +#ifdef HALBB_RUA_SUPPORT + /*struct rtw_rua_tbl rtw_rua_t;*/ +#endif +#ifdef HALBB_DIG_MCC_SUPPORT + struct halbb_mcc_dm mcc_dm; +#endif +}; + + +/*@--------------------------[Prptotype]-------------------------------------*/ +u8 halbb_get_rssi_min(struct bb_info *bb); +void halbb_cmn_info_self_reset(struct bb_info *bb); +void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.c b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.c new file mode 100644 index 0000000..dc8b81a --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.c @@ -0,0 +1,327 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halbb_precomp.h" + +#ifdef BB_8852B_SUPPORT + +bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver) +{ + bool valid = true; + +#if 0 + if (bb_ver >= X && rf_ver >= Y) + valid = true; + else if (bb_ver < X && rf_ver < Y) + valid = true; + else + valid = false; +#endif + + if (!valid) { + /*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/ + BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n", + __func__, bb_ver, rf_ver); + } + + return valid; +} + + +void halbb_stop_pmac_tx_8852b(struct bb_info *bb, + struct halbb_pmac_info *tx_info, + enum phl_phy_idx phy_idx) +{ + if (tx_info->is_cck) { // CCK + if (tx_info->mode == CONT_TX) { + halbb_set_reg(bb, 0x2300, BIT(26), 1); + halbb_set_reg(bb, 0x2338, BIT(17), 0); + halbb_set_reg(bb, 0x2300, BIT(28), 0); + halbb_set_reg(bb, 0x2300, BIT(26), 0); + } else if (tx_info->mode == PKTS_TX) { + halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); + } + } else { // OFDM + if (tx_info->mode == CONT_TX) + halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx); + else if (tx_info->mode == PKTS_TX) + halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); + } +} + + +void halbb_start_pmac_tx_8852b(struct bb_info *bb, + struct halbb_pmac_info *tx_info, + enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period, + enum phl_phy_idx phy_idx) +{ + if (mode == CONT_TX) { + if (tx_info->is_cck) { + halbb_set_reg(bb, 0x2338, BIT(17), 1); + halbb_set_reg(bb, 0x2300, BIT(28), 0); + } else { + halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx); + } + } else if (mode == PKTS_TX) { + /*Tx_N_PACKET_EN */ + halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); + /*Tx_N_PERIOD */ + halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx); + /*Tx_N_PACKET */ + halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx); + } else if (mode == CCK_CARRIER_SIPPRESSION_TX) { + if (tx_info->is_cck) { + /*Carrier Suppress Tx*/ + halbb_set_reg(bb, 0x2338, BIT(18), 1); + /*Disable scrambler at payload part*/ + halbb_set_reg(bb, 0x2304, BIT(26), 1); + } else { + return; + } + /*Tx_N_PACKET_EN */ + halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); + /*Tx_N_PERIOD */ + halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx); + /*Tx_N_PACKET */ + halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx); + } + /*Tx_EN */ + halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx); + halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx); +} + + +void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info, + enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (!tx_info->en_pmac_tx) { + halbb_stop_pmac_tx_8852b(bb, tx_info, phy_idx); + /* PD hit enable */ + halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx); + halbb_set_reg(bb, 0x2344, BIT(31), 0); + return; + } + /*Turn on PMAC */ + /* Tx */ + halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx); + /* Rx */ + halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx); + halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx); + + /* PD hit enable */ + halbb_set_reg(bb, 0x704, BIT(1), 0); + halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx); + halbb_set_reg(bb, 0x2344, BIT(31), 1); + halbb_set_reg(bb, 0x704, BIT(1), 1); + + halbb_start_pmac_tx_8852b(bb, tx_info, tx_info->mode, tx_info->tx_cnt, + tx_info->period, phy_idx); +} + +void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + /* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/ + /* Turn on TMAC */ + halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx); + halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx); + halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx); + halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx); + + // PDP bypass from TMAC + halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx); + // TMAC Tx path + halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx); + // TMAC Tx power + halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx); +} + +void halbb_ic_hw_setting_init_8852b(struct bb_info *bb) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if(phl_is_mp_mode(bb->phl_com)) { + // r_en_sound_wo_ndp + halbb_set_reg(bb, 0xd7c, BIT(1), 1); + halbb_set_reg(bb, 0x2d7c, BIT(1), 1); + } else { + // r_en_sound_wo_ndp + halbb_set_reg(bb, 0xd7c, BIT(1), 0); + halbb_set_reg(bb, 0x2d7c, BIT(1), 0); + } +} + +bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound, + enum channel_width bw, + enum phl_phy_idx phy_idx) +{ + /* + Range of bound value: + BW20: 95~33 + BW40: 92~30 + BW80: 89~27 + */ + u8 bw_attenuation = 0; + u8 subband_filter_atteniation = 7; + u8 bound_idx = 0; + bool rpt = true; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (bound == 0) { + halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Set Boundary to default!\n"); + return true; + } + + bb->bb_cmn_backup_i.cur_pd_lower_bound = bound; + + if (bw == CHANNEL_WIDTH_20) { + bw_attenuation = 0; + } else if (bw == CHANNEL_WIDTH_40) { + bw_attenuation = 3; + } else if (bw == CHANNEL_WIDTH_80) { + bw_attenuation = 6; + } else { + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Only support BW20/40/80 !\n"); + return false; + } + + bound += (bw_attenuation + subband_filter_atteniation); + // If Boundary dbm is odd, set it to even number + bound = bound % 2 ? bound + 1 : bound; + + if (bound < 40) { + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Threshold too high, set to highest level!\n"); + bound = 40; + rpt = false; + } + + if (bound > 102) { + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Threshold too low, disable PD lower bound function!\n"); + halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx); + return true; + } + + bound_idx = (102 - bound) >> 1; + + halbb_set_reg_cmn(bb, 0x4860, 0x7c0, bound_idx, phy_idx); + halbb_set_reg_cmn(bb, 0x4860, BIT(30), 1, phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n"); + + return rpt; +} + +bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound, + enum channel_width bw, + enum phl_phy_idx phy_idx) +{ + u8 bw_attenuation = 0; + u8 subband_filter_atteniation = 5; + s8 bound_tmp = 0; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (bb->hal_com->cv < CBV) { + BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] CCK pd_lower_bound CV not support!\n"); + return false; + } + + if (bound == 0) { + halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 0, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Set Boundary to default!\n"); + return true; + } + + if (bw == CHANNEL_WIDTH_20) { + bw_attenuation = 0; + } + else if (bw == CHANNEL_WIDTH_40) { + bw_attenuation = 3; + } + else if (bw == CHANNEL_WIDTH_80) { + bw_attenuation = 6; + } + else { + BB_DBG(bb, DBG_PHY_CONFIG, + "[PD Bound] Only support BW20/40/80 !\n"); + return true; + } + + bound += (bw_attenuation + subband_filter_atteniation); + bound_tmp = (-1) * MIN_2(bound, 128); + + halbb_set_reg_cmn(bb, 0x23b0, 0xff000000, bound_tmp, phy_idx); + halbb_set_reg_cmn(bb, 0x23b4, 0xff000000, 0x7f, phy_idx); + halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 1, phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n"); + + return true; +} + +u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx) +{ + u8 tmp; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (get_en_info) + tmp = (u8)halbb_get_reg_cmn(bb, 0x4860, BIT(30), phy_idx); + else + tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound; + + return tmp; +} + +void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (en) { + halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 1, phy_idx); + + } else { + halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 0, phy_idx); + } +} + +bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + bool en; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + en = (bool)halbb_get_reg_cmn(bb, 0x47D4, BIT(8), phy_idx); + + return en; +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.h new file mode 100644 index 0000000..efd3df3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_8852B_H__ +#define __HALBB_8852B_H__ +#ifdef BB_8852B_SUPPORT + +#include "../halbb_pmac_setting_ex.h" + +struct bb_info; + +bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver); +void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info, + enum phl_phy_idx phy_idx); + +void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_ic_hw_setting_init_8852b(struct bb_info *bb); + +bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound, + enum channel_width bw, + enum phl_phy_idx phy_idx); +bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound, + enum channel_width bw, + enum phl_phy_idx phy_idx); +u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info, + enum phl_phy_idx phy_idx); +void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx); +bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); +#endif +#endif /* __HALBB_8852b_H__ */ diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.c b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.c new file mode 100644 index 0000000..917538a --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.c @@ -0,0 +1,2116 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halbb_precomp.h" + +#ifdef BB_8852B_SUPPORT + +bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb, + s16 pw_ofst, enum phl_phy_idx phy_idx) +{ + /*S(5,0) for 8852A/8852B*/ + if (pw_ofst < -16 || pw_ofst > 15) { + BB_WARNING("[%s] ofst=%d\n", __func__, pw_ofst); + return false; + } + + /*ECO en*/ + rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); + + /*1 TX*/ + rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); + + /*2 TX*/ + if (pw_ofst < -13) + pw_ofst = -13; + rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); + + return true; +} + +void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx, + enum phl_phy_idx phy_idx) { + + halbb_set_reg(bb, 0x4494, 0x3000000, shape_idx); + /*0:0dB 1:-4dB 2:-5dB 3:-6dB*/ +} + +void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx, + enum phl_phy_idx phy_idx) { + + u32 para_flat[8] = {0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, + 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5}; + u32 para_sharp[8] = {0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, + 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5}; + u32 para_sharp_14[8] = {0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, + 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A}; + u32 *para = NULL; + u8 i = 0; + + BB_DBG(bb, DBG_DBG_API, "[%s] ch=%d, shape_idx=%d\n", __func__, ch, shape_idx); + + if (ch > 14) + return; + + if (ch == 14) { + para = para_sharp_14; + } else { + if (shape_idx == 0) { + /*flat CH1~14*/ + para = para_flat; + } else { + /*Sharp( b mode tx dfir)*/ + para = para_sharp; + } + } + + for (i = 0; i < 8; i++) { + halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx); + BB_DBG(bb, DBG_DBG_API, "Reg0x%08x = 0x%08x\n", 0x2300 + (i << 2), para[i]); + } +} + +void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + // === [TSSI protect on] === // + halbb_set_reg(bb, 0x58dc, BIT(30), 0x1); + halbb_set_reg(bb, 0x5818, BIT(30), 0x1); + halbb_set_reg(bb, 0x78dc, BIT(30), 0x1); + halbb_set_reg(bb, 0x7818, BIT(30), 0x1); + // === [BB reset] === // + halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); + halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx); + halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); + // === [TSSI protect off] === // + halbb_set_reg(bb, 0x58dc, BIT(30), 0x0); + halbb_set_reg(bb, 0x5818, BIT(30), 0x0); + halbb_set_reg(bb, 0x78dc, BIT(30), 0x0); + halbb_set_reg(bb, 0x7818, BIT(30), 0x0); +} + +void halbb_dfs_en_8852b(struct bb_info *bb, bool en) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + if (en) + halbb_set_reg(bb, 0x0, BIT(31), 1); + else + halbb_set_reg(bb, 0x0, BIT(31), 0); +} + +void halbb_adc_en_8852b(struct bb_info *bb, bool en) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + if (en) + halbb_set_reg(bb, 0x20fc, 0xff000000, 0x0); + else + halbb_set_reg(bb, 0x20fc, 0xff000000, 0xf); +} + +void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path) +{ + u32 tssi_trk_man[2] = {0x5818, 0x7818}; + + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + if (en) { + halbb_set_reg(bb, tssi_trk_man[path], BIT(30), 0x0); + rtw_hal_rf_tssi_scan_ch(bb->hal_com, HW_PHY_0, path); + } else { + halbb_set_reg(bb, tssi_trk_man[path], BIT(30), 0x1); + } +} +void halbb_bb_reset_all_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + //Protest SW-SI + halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx); + halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx); + halbb_delay_us(bb, 1); + // === [BB reset] === // + halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); + halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx); + halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx); + halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx); + + halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); +} + +void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + if (en) { + halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx); + halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx); + halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); + //PD Enable + if(bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) + halbb_set_reg(bb,0x2344, BIT(31), 0x0); + halbb_set_reg(bb,0xc3c, BIT(9), 0x0); + } else { + //PD Disable + halbb_set_reg(bb,0x2344, BIT(31), 0x1); + halbb_set_reg(bb,0xc3c, BIT(9), 0x1); + //Protest SW-SI + halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx); + halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx); + halbb_delay_us(bb, 1); + halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx); + } +} + +u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask) +{ + u8 path_tmp=0; + u32 i = 0, j = 0, readback_value = INVALID_RF_DATA, r_reg = 0; + bool is_r_busy = true, is_w_busy = true, is_r_done = false; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + while (is_w_busy || is_r_busy) { + is_w_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(24)); + is_r_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(25)); + halbb_delay_us(bb, 1); + /*BB_WARNING("[%s] is_w_busy = %d, is_r_busy = %d\n", + __func__, is_w_busy, is_r_busy);*/ + i++; + if (i > 30) + break; + } + if (is_w_busy || is_r_busy) { + BB_WARNING("[%s] is_w_busy = (%d), is_r_busy = (%d)\n", + __func__, is_w_busy, is_r_busy); + return INVALID_RF_DATA; + } + + + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return INVALID_RF_DATA; + } + + /*==== Calculate offset ====*/ + path_tmp = (u8)path & 0x7; + reg_addr &= 0xff; + + /*==== RF register only has 20bits ====*/ + bit_mask &= RFREGOFFSETMASK; + + r_reg = (path_tmp << 8 | reg_addr) & 0x7ff; + halbb_set_reg(bb, 0x378, 0x7ff, r_reg); + halbb_delay_us(bb, 2); + + + /*==== Read RF register ====*/ + while (!is_r_done) { + is_r_done = (bool)halbb_get_reg(bb, 0x174c, BIT(26)); + halbb_delay_us(bb, 1); + j++; + if (j > 30) + break; + } + if (is_r_done) { + readback_value = halbb_get_reg(bb, 0x174c, bit_mask); + } else { + BB_WARNING("[%s] is_r_done = (%d)\n", __func__, is_r_done); + return INVALID_RF_DATA; + } + BB_DBG(bb, DBG_PHY_CONFIG, "A die RF-%d 0x%x = 0x%x, bit mask = 0x%x, i=%x, j =%x\n", + path_tmp, reg_addr, readback_value, bit_mask,i,j); + return readback_value; +} + +u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask) +{ + u32 readback_value = 0, direct_addr = 0; + u32 offset_read_rf[2] = {0xe000, 0xf000}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return INVALID_RF_DATA; + } + + /*==== Calculate offset ====*/ + reg_addr &= 0xff; + direct_addr = offset_read_rf[path] + (reg_addr << 2); + + /*==== RF register only has 20bits ====*/ + bit_mask &= RFREGOFFSETMASK; + + /*==== Read RF register directly ====*/ + readback_value = halbb_get_reg(bb, direct_addr, bit_mask); + BB_DBG(bb, DBG_PHY_CONFIG, "D die RF-%d 0x100%x = 0x%x, bit mask = 0x%x\n", + path, reg_addr, readback_value, bit_mask); + return readback_value; +} + +u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr, + u32 bit_mask) +{ + u32 readback_value = INVALID_RF_DATA; + enum rtw_dv_sel ad_sel = (enum rtw_dv_sel)((reg_addr & 0x10000) >> 16); + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return INVALID_RF_DATA; + } + + if (ad_sel == DAV) { + readback_value = halbb_read_rf_reg_8852b_a(bb, path, reg_addr, + bit_mask); + /*BB_DBG(bb, DBG_PHY_CONFIG, "A-die RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + path, reg_addr, readback_value, bit_mask);*/ + } else if (ad_sel == DDV) { + readback_value = halbb_read_rf_reg_8852b_d(bb, path, reg_addr, + bit_mask); + /*BB_DBG(bb, DBG_PHY_CONFIG, "D-die RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + path, reg_addr, readback_value, bit_mask);*/ + } else { + BB_DBG(bb, DBG_PHY_CONFIG, "Fail Read RF RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + path, reg_addr, readback_value, bit_mask); + return INVALID_RF_DATA; + } + return readback_value; +} + +void halbb_5m_mask_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx) +{ + bool mask_5m_low = false; + bool mask_5m_en = false; + + switch (bw) { + case CHANNEL_WIDTH_40: + /* Prich=1 : Mask 5M High + Prich=2 : Mask 5M Low */ + mask_5m_en = true; + mask_5m_low = pri_ch == 2 ? true : false; + break; + case CHANNEL_WIDTH_80: + /* Prich=3 : Mask 5M High + Prich=4 : Mask 5M Low + Else : Mask 5M Disable */ + mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)) ? true : false; + mask_5m_low = pri_ch == 4 ? true : false; + break; + default: + mask_5m_en = false; + break; + } + + BB_DBG(bb, DBG_PHY_CONFIG, "[5M Mask] pri_ch = %d, bw = %d", pri_ch, bw); + + if (!mask_5m_en) { + halbb_set_reg(bb, 0x46f8, BIT(12), 0x0); + halbb_set_reg(bb, 0x47b8, BIT(12), 0x0); + halbb_set_reg_cmn(bb, 0x4440, BIT(31), 0x0, phy_idx); + } else { + if (mask_5m_low) { + halbb_set_reg(bb, 0x46f8, 0x3f, 0x4); + halbb_set_reg(bb, 0x46f8, BIT(12), 0x1); + halbb_set_reg(bb, 0x46f8, BIT(8), 0x0); + halbb_set_reg(bb, 0x46f8, BIT(6), 0x1); + halbb_set_reg(bb, 0x47b8, 0x3f, 0x4); + halbb_set_reg(bb, 0x47b8, BIT(12), 0x1); + halbb_set_reg(bb, 0x47b8, BIT(8), 0x0); + halbb_set_reg(bb, 0x47b8, BIT(6), 0x1); + } else { + halbb_set_reg(bb, 0x46f8, 0x3f, 0x4); + halbb_set_reg(bb, 0x46f8, BIT(12), 0x1); + halbb_set_reg(bb, 0x46f8, BIT(8), 0x1); + halbb_set_reg(bb, 0x46f8, BIT(6), 0x0); + halbb_set_reg(bb, 0x47b8, 0x3f, 0x4); + halbb_set_reg(bb, 0x47b8, BIT(12), 0x1); + halbb_set_reg(bb, 0x47b8, BIT(8), 0x1); + halbb_set_reg(bb, 0x47b8, BIT(6), 0x0); + } + halbb_set_reg_cmn(bb, 0x4440, BIT(31), 0x1, phy_idx); + } +} + +u8 halbb_sco_mapping_8852b(struct bb_info *bb, u8 central_ch) +{ + /*=== SCO compensate : (BIT(0) << 18) / central_ch ===*/ + if (central_ch == 1) + /*=== 2G ===*/ + return 109; + else if (central_ch >= 2 && central_ch <= 6) + return 108; + else if (central_ch >= 7 && central_ch <= 10) + return 107; + else if (central_ch >= 11 && central_ch <= 14) + return 106; + else if (central_ch == 36 || central_ch == 38) + return 51; + else if (central_ch >= 40 && central_ch <= 58) + return 50; + else if (central_ch >= 60 && central_ch <= 64) + return 49; + else if (central_ch == 100 || central_ch == 102) + return 48; + else if (central_ch >= 104 && central_ch <= 126) + return 47; + else if (central_ch >= 128 && central_ch <= 151) + return 46; + else if (central_ch >= 153 && central_ch <= 177) + return 45; + else + return 0; +} + +bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch) +{ + u32 sco_barker_threshold[14] = {0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, + 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, + 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, + 0x1db75, 0x1ddc4}; + u32 sco_cck_threshold[14] = {0x27de3, 0x27f35, 0x28088, 0x281da, + 0x2832d, 0x2847f, 0x285d2, 0x28724, + 0x28877, 0x289c9, 0x28b1c, 0x28c6e, + 0x28dc1, 0x290ed}; + + if (pri_ch > 14) { + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Fail]"); + return false; + } + + halbb_set_reg(bb, 0x23b0, 0x7ffff, sco_barker_threshold[pri_ch - 1]); + halbb_set_reg(bb, 0x23b4, 0x7ffff, sco_cck_threshold[pri_ch - 1]); + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Success]"); + return true; +} + +bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data) +{ + u8 path_tmp = 0, b_msk_en = 0, bit_shift = 0; + u32 i =0, w_reg = 0; + bool is_r_busy = true, is_w_busy = true; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + while (is_w_busy || is_r_busy) { + is_w_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(24)); + is_r_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(25)); + halbb_delay_us(bb, 1); + /*BB_WARNING("[%s] is_w_busy = %d, is_r_busy = %d\n", + __func__, is_w_busy, is_r_busy);*/ + i++; + if (i > 30) + break; + } + if (is_w_busy || is_r_busy) { + BB_WARNING("[%s] is_w_busy = (%d), is_r_busy = (%d)\n", + __func__, is_w_busy, is_r_busy); + return false; + } + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return false; + } + + /*==== Calculate offset ====*/ + path_tmp = (u8)path & 0x7; + reg_addr &= 0xff; + + /*==== RF register only has 20bits ====*/ + data &= RFREGOFFSETMASK; + bit_mask &= RFREGOFFSETMASK; + + /*==== Check if mask needed ====*/ + if (bit_mask != RFREGOFFSETMASK) { + b_msk_en = 1; + halbb_set_reg(bb, 0x374, RFREGOFFSETMASK, bit_mask); + for (bit_shift = 0; bit_shift <= 19; bit_shift++) { + if ((bit_mask >> bit_shift) & 0x1) + break; + } + data = (data << bit_shift) & RFREGOFFSETMASK; + } + + w_reg = b_msk_en << 31 | path_tmp << 28 | reg_addr << 20 | data; + + /*==== Write RF register ====*/ + halbb_set_reg(bb, 0x370, MASKDWORD, w_reg); + //halbb_delay_us(bb, 5); + + BB_DBG(bb, DBG_PHY_CONFIG, "A die RF-%d 0x%x = 0x%x , bit mask = 0x%x, i=%x\n", + path_tmp, reg_addr, data, bit_mask,i); + + return true; +} + +bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data) +{ + u32 direct_addr = 0; + u32 offset_write_rf[2] = {0xe000, 0xf000}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return false; + } + + /*==== Calculate offset ====*/ + reg_addr &= 0xff; + direct_addr = offset_write_rf[path] + (reg_addr << 2); + + /*==== RF register only has 20bits ====*/ + bit_mask &= RFREGOFFSETMASK; + + /*==== Write RF register directly ====*/ + halbb_set_reg(bb, direct_addr, bit_mask, data); + + halbb_delay_us(bb, 1); + + BB_DBG(bb, DBG_PHY_CONFIG, "D die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n", + path, reg_addr, data, bit_mask); + + return true; +} + +bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data) +{ + u8 path_tmp = 0, b_msk_en = 0; + u32 w_reg = 0; + bool rpt = true; + enum rtw_dv_sel ad_sel = (enum rtw_dv_sel)((reg_addr & 0x10000) >> 16); + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== Error handling ====*/ + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return false; + } + + if (ad_sel == DAV) { + rpt = halbb_write_rf_reg_8852b_a(bb, path, reg_addr, bit_mask, + data); + /*BB_DBG(bb, DBG_PHY_CONFIG, "A-die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n", + path, reg_addr, data, bit_mask);*/ + } else if (ad_sel == DDV) { + rpt = halbb_write_rf_reg_8852b_d(bb, path, reg_addr, bit_mask, + data); + /*BB_DBG(bb, DBG_PHY_CONFIG, "D-die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n", + path, reg_addr, data, bit_mask);*/ + } else { + rpt = false; + BB_DBG(bb, DBG_PHY_CONFIG, "Fail Write RF-%d 0x%x = 0x%x , bit mask = 0x%x\n", + path, reg_addr, data, bit_mask); + } + + return rpt; +} +void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg) +{ + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if(bb->hal_com->band[0].cur_chandef.band != BAND_ON_24G) + return; + + if (btg) { + // Path A + halbb_set_reg(bb, 0x4738, BIT(19), 0x1); + halbb_set_reg(bb, 0x4738, BIT(22), 0x0); + // Path B + halbb_set_reg(bb, 0x4AA4, BIT(19), 0x1); + halbb_set_reg(bb, 0x4AA4, BIT(22), 0x1); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n"); + // Apply Grant BT by TMAC Setting + halbb_set_reg(bb, 0x980, 0x1e0000, 0x0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n"); + // Add BT share + halbb_set_reg(bb, 0x49C4, BIT(14), 0x1); + halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x2); + /* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */ + halbb_set_reg(bb, 0x4420, BIT(31), 0x1); + halbb_set_reg(bb, 0xc6c, BIT(21), 0x1); + } else { + // Path A + halbb_set_reg(bb, 0x4738, BIT(19), 0x0); + halbb_set_reg(bb, 0x4738, BIT(22), 0x0); + // Path B + halbb_set_reg(bb, 0x4AA4, BIT(19), 0x0); + halbb_set_reg(bb, 0x4AA4, BIT(22), 0x0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n"); + // Ignore Grant BT by PMAC Setting + halbb_set_reg(bb, 0x980, 0x1e0000, 0x0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n"); + // Reset BT share + halbb_set_reg(bb, 0x49C4, BIT(14), 0x0); + halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x0); + /* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */ + halbb_set_reg(bb, 0x4420, BIT(31), 0x1); + halbb_set_reg(bb, 0xc6c, BIT(21), 0x0); + } +} + +void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (bt_en) { + // DFIR Corner + halbb_set_reg(bb, 0x46D0, BIT(1) | BIT(0), 0x3); + halbb_set_reg(bb, 0x4790, BIT(1) | BIT(0), 0x3); + // LNA Backoff at Normal + halbb_set_reg(bb, 0x46a0, 0x3f, 0x8); + halbb_set_reg(bb, 0x49f4, 0x3f, 0x8); + // LNA, TIA, ADC backoff at BT TX + halbb_set_reg(bb, 0x4ae4, 0xffffff, 0x78899e); + halbb_set_reg(bb, 0x4aec, 0xffffff, 0x78899e); + } else { + // DFIR Corner + halbb_set_reg(bb, 0x46D0, BIT(1) | BIT(0), 0x0); + halbb_set_reg(bb, 0x4790, BIT(1) | BIT(0), 0x0); + // LNA Backoff at Normal + halbb_set_reg(bb, 0x46a0, 0x3f, 0x1e); + halbb_set_reg(bb, 0x49f4, 0x3f, 0x1e); + // LNA, TIA, ADC backoff at BT TX + halbb_set_reg(bb, 0x4ae4, 0xffffff, 0x4d34d2); + halbb_set_reg(bb, 0x4aec, 0xffffff, 0x4d34d2); + } +} +bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw, + enum rf_path path) +{ + u32 rf_reg18 = 0; + u32 adc_sel[2] = {0xC0EC, 0xC1EC}; + u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; + + //rf_reg18 = halbb_read_rf_reg_8852b(bb, path, 0x18, RFREGOFFSETMASK); + /*==== [Error handling] ====*/ + //if (rf_reg18 == INVALID_RF_DATA) { + // BB_WARNING("Invalid RF_0x18 for Path-%d\n", path); + // return false; + //} + //rf_reg18 &= ~(BIT(11) | BIT(10)); + /*==== [Switch bandwidth] ====*/ + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + if (bw == CHANNEL_WIDTH_5) { + /*ADC clock = 20M & WB ADC clock = 40M for BW5 */ + halbb_set_reg(bb, adc_sel[path], 0x6000, 0x1); + halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x0); + } else if (bw == CHANNEL_WIDTH_10) { + /*ADC clock = 40M & WB ADC clock = 80M for BW10 */ + halbb_set_reg(bb, adc_sel[path], 0x6000, 0x2); + halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x1); + } else if (bw == CHANNEL_WIDTH_20) { + /*ADC clock = 80M & WB ADC clock = 160M for BW20 */ + halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0); + halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2); + } + + /*RF bandwidth */ + //rf_reg18 |= (BIT(11) | BIT(10)); + + break; + case CHANNEL_WIDTH_40: + /*ADC clock = 80M & WB ADC clock = 160M for BW40 */ + halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0); + halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2); + + /*RF bandwidth */ + //rf_reg18 |= BIT(11); + + break; + case CHANNEL_WIDTH_80: + /*ADC clock = 160M & WB ADC clock = 160M for BW40 */ + halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0); + halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2); + + /*RF bandwidth */ + //rf_reg18 |= BIT(10); + + break; + default: + BB_WARNING("Fail to set ADC\n"); + } + + /*==== [Write RF register] ====*/ + //Already Move to RF API + + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success][bw_setting] ADC setting for Path-%d\n", path); + return true; +} + +bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (bb->is_disable_phy_api) { + BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__); + return true; + } + + /*==== Error handling ====*/ + if (bw >= CHANNEL_WIDTH_MAX || (bw == CHANNEL_WIDTH_40 && pri_ch > 2) || + (bw == CHANNEL_WIDTH_80 && pri_ch > 4)) { + BB_WARNING("Fail to switch bw(bw:%d, pri ch:%d)\n", bw, + pri_ch); + return false; + } + + /*==== Switch bandwidth ====*/ + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + if (bw == CHANNEL_WIDTH_5) { + /*RF_BW:[31:30]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0, + phy_idx); + /*small BW:[13:12]=0x1 */ + halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x1, phy_idx); + /*Pri ch:[11:8]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx); + } else if (bw == CHANNEL_WIDTH_10) { + /*RF_BW:[31:30]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0, + phy_idx); + /*small BW:[13:12]=0x2 */ + halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x2, phy_idx); + /*Pri ch:[11:8]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx); + } else if (bw == CHANNEL_WIDTH_20) { + /*RF_BW:[31:30]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0, + phy_idx); + /*small BW:[13:12]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx); + /*Pri ch:[11:8]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx); + } + + break; + case CHANNEL_WIDTH_40: + /*RF_BW:[31:30]=0x1 */ + halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x1, phy_idx); + /*small BW:[13:12]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx); + /*Pri ch:[11:8] */ + halbb_set_reg_cmn(bb, 0x49C4, 0xf00, pri_ch, phy_idx); + /*CCK primary channel */ + if (pri_ch == 1) + halbb_set_reg(bb, 0x237c, BIT(0), 1); + else + halbb_set_reg(bb, 0x237c, BIT(0), 0); + + break; + case CHANNEL_WIDTH_80: + /*RF_BW:[31:30]=0x2 */ + halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x2, phy_idx); + /*small BW:[13:12]=0x0 */ + halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx); + /*Pri ch:[11:8] */ + halbb_set_reg_cmn(bb, 0x49C4, 0xf00, pri_ch, phy_idx); + + break; + default: + BB_WARNING("Fail to switch bw (bw:%d, pri ch:%d)\n", bw, + pri_ch); + } + + + /*============== [Path A] ==============*/ + halbb_bw_setting_8852b(bb, bw, RF_PATH_A); + /*============== [Path B] ==============*/ + halbb_bw_setting_8852b(bb, bw, RF_PATH_B); + + + BB_DBG(bb, DBG_PHY_CONFIG, + "[Switch BW Success] BW: %d for PHY%d\n", bw, phy_idx); + + return true; +} + +bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path, + bool *is_2g_ch) +{ + u32 rf_reg18 = 0; + + *is_2g_ch = (central_ch <= 14) ? true : false; + //RF_18 R/W already move to RF API + BB_DBG(bb, DBG_PHY_CONFIG, "[Success][ch_setting] CH: %d for Path-%d\n", + central_ch, path); + return true; +} + +bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, + enum phl_phy_idx phy_idx) +{ + u8 sco_comp; + bool is_2g_ch; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (bb->is_disable_phy_api) { + BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__); + return true; + } + /*==== Error handling ====*/ + if ((central_ch > 14 && central_ch < 36) || + (central_ch > 64 && central_ch < 100) || + (central_ch > 144 && central_ch < 149) || + central_ch > 177 || + central_ch== 0) { + BB_WARNING("Invalid CH:%d for PHY%d\n", central_ch, + phy_idx); + return false; + } + + + /*============== [Path A] ==============*/ + halbb_ch_setting_8852b(bb, central_ch, RF_PATH_A, &is_2g_ch); + //------------- [Mode Sel - Path A] ------------// + if (is_2g_ch) + halbb_set_reg_cmn(bb, 0x4738, BIT(17), 1, phy_idx); + else + halbb_set_reg_cmn(bb, 0x4738, BIT(17), 0, phy_idx); + + /*============== [Path B] ==============*/ + + halbb_ch_setting_8852b(bb, central_ch, RF_PATH_B, &is_2g_ch); + //------------- [Mode Sel - Path B] ------------// + if (is_2g_ch) + halbb_set_reg_cmn(bb, 0x4AA4, BIT(17), 1, phy_idx); + else + halbb_set_reg_cmn(bb, 0x4AA4, BIT(17), 0, phy_idx); + + /*==== [SCO compensate fc setting] ====*/ + sco_comp = halbb_sco_mapping_8852b(bb, central_ch); + halbb_set_reg_cmn(bb, 0x49C0, 0x7f, sco_comp, phy_idx); + + /* === CCK Parameters === */ + if (central_ch == 14) { + halbb_set_reg(bb, 0x2300, 0xffffff, 0x3b13ff); + halbb_set_reg(bb, 0x2304, 0xffffff, 0x1c42de); + halbb_set_reg(bb, 0x2308, 0xffffff, 0xfdb0ad); + halbb_set_reg(bb, 0x230c, 0xffffff, 0xf60f6e); + halbb_set_reg(bb, 0x2310, 0xffffff, 0xfd8f92); + halbb_set_reg(bb, 0x2314, 0xffffff, 0x2d011); + halbb_set_reg(bb, 0x2318, 0xffffff, 0x1c02c); + halbb_set_reg(bb, 0x231c, 0xffffff, 0xfff00a); + } else { + halbb_set_reg(bb, 0x2300, 0xffffff, 0x3d23ff); + halbb_set_reg(bb, 0x2304, 0xffffff, 0x29b354); + halbb_set_reg(bb, 0x2308, 0xffffff, 0xfc1c8); + halbb_set_reg(bb, 0x230c, 0xffffff, 0xfdb053); + halbb_set_reg(bb, 0x2310, 0xffffff, 0xf86f9a); + halbb_set_reg(bb, 0x2314, 0xffffff, 0xfaef92); + halbb_set_reg(bb, 0x2318, 0xffffff, 0xfe5fcc); + halbb_set_reg(bb, 0x231c, 0xffffff, 0xffdff5); + } + /* === Set Gain Error === */ + halbb_set_gain_error_8852b(bb, central_ch); + /* === Set Efuse === */ + halbb_set_efuse_8852b(bb, central_ch, HW_PHY_0); + /* === Set RXSC RPL Comp === */ + halbb_set_rxsc_rpl_comp_8852b(bb, central_ch); + + /* === Set Ch idx report in phy-sts === */ + halbb_set_reg_cmn(bb, 0x0734, 0x0ff0000, central_ch, phy_idx); + bb->bb_ch_i.rf_central_ch_cfg = central_ch; + + BB_DBG(bb, DBG_PHY_CONFIG, "[Switch CH Success] CH: %d for PHY%d\n", + central_ch, phy_idx); + return true; +} + +void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en, + enum phl_phy_idx phy_idx) +{ + if (cck_en) { + //halbb_set_reg(bb, 0x2300, BIT(27), 0); + halbb_set_reg(bb, 0x700, BIT(5), 1); + halbb_set_reg(bb, 0x2344, BIT(31), 0); + } else { + //halbb_set_reg(bb, 0x2300, BIT(27), 1); + halbb_set_reg(bb, 0x700, BIT(5), 0); + halbb_set_reg(bb, 0x2344, BIT(31), 1); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx); +} + +bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width bw, enum band_type band, + enum phl_phy_idx phy_idx) +{ + bool rpt = true; + bool cck_en = false; + u8 pri_ch_idx = 0; + bool is_2g_ch; + + is_2g_ch = (band == BAND_ON_24G) ? true : false; + /*==== [Set pri_ch idx] ====*/ + if (central_ch <= 14) { +#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA + /*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/ + halbb_set_reg(bb, 0x4498, BIT(30), 1); +#endif + + // === 2G === // + switch (bw) { + case CHANNEL_WIDTH_20: + break; + + case CHANNEL_WIDTH_40: + pri_ch_idx = pri_ch > central_ch ? 1 : 2; + break; + + default: + break; + } + + /*==== [CCK SCO Compesate] ====*/ + rpt &= halbb_ctrl_sco_cck_8852b(bb, pri_ch); + + cck_en = true; + } else { + // === 5G === // + switch (bw) { + case CHANNEL_WIDTH_20: +#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA + /*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/ + halbb_set_reg(bb, 0x4498, BIT(30), 1); +#endif + break; + case CHANNEL_WIDTH_40: + case CHANNEL_WIDTH_80: + if (pri_ch > central_ch) + pri_ch_idx = (pri_ch - central_ch) >> 1; + else + pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1; +#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA + /*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/ + halbb_set_reg(bb, 0x4498, BIT(30), 0); +#endif + break; + + default: + break; + } + cck_en = false; + } + + /*==== [Switch CH] ====*/ + rpt &= halbb_ctrl_ch_8852b(bb, central_ch, phy_idx); + /*==== [Switch BW] ====*/ + rpt &= halbb_ctrl_bw_8852b(bb, pri_ch_idx, bw, phy_idx); + /*==== [CCK Enable / Disable] ====*/ + halbb_ctrl_cck_en_8852b(bb, cck_en, phy_idx); + /*==== [Spur elimination] ====*/ + //TBD + if (is_2g_ch && ((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB))){ + halbb_ctrl_btg_8852b(bb, true); + } else if (is_2g_ch && (bb->rx_path == RF_PATH_A)) { + halbb_ctrl_btg_8852b(bb, false); + } else { + // Path A + halbb_set_reg(bb, 0x4738, BIT(19), 0x0); + halbb_set_reg(bb, 0x4738, BIT(22), 0x0); + // Path B + halbb_set_reg(bb, 0x4AA4, BIT(19), 0x0); + halbb_set_reg(bb, 0x4AA4, BIT(22), 0x0); + // Ignore Grant BT by PMAC Setting + halbb_set_reg(bb, 0x980, 0x1e0000, 0xf); + // Reset BT share + halbb_set_reg(bb, 0x49C4, BIT(14), 0x0); + halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x0); + /* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */ + halbb_set_reg(bb, 0x4420, BIT(31), 0x0); + halbb_set_reg(bb, 0xc6c, BIT(21), 0x0); + } + + /* Dynamic 5M Mask Setting */ + halbb_5m_mask_8852b(bb, pri_ch, bw, phy_idx); + + /*==== [BB reset] ====*/ + halbb_bb_reset_all_8852b(bb, phy_idx); + + return rpt; +} + +bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path) +{ + u32 ofdm_rx = 0x0; + + ofdm_rx = (u32)rx_path; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + bb->rx_path = rx_path; + + if (ofdm_rx == RF_PATH_A) { + halbb_set_reg(bb, 0x49C4, 0xf, 0x1); + /*==== 1rcca ====*/ + halbb_set_reg(bb, 0x49C0, 0x3C000, 1); + halbb_set_reg(bb, 0x49C0, 0x3C0000, 1); + /*==== Rx HT nss_limit / mcs_limit ====*/ + halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0); + halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0); + /*==== Rx HE n_user_max / tb_max_nss ====*/ + halbb_set_reg(bb, 0xd80, 0x3fc0, 4); + halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0); + halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0); + } else if (ofdm_rx == RF_PATH_B) { + halbb_set_reg(bb, 0x49C4, 0xf, 0x2); + /*==== 1rcca ====*/ + halbb_set_reg(bb, 0x49C0, 0x3C000, 0x2); + halbb_set_reg(bb, 0x49C0, 0x3C0000, 0x2); + /*==== Rx HT nss_limit / mcs_limit ====*/ + halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0); + halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0); + /*==== Rx HE n_user_max / tb_max_nss ====*/ + halbb_set_reg(bb, 0xd80, 0x3fc0, 4); + halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0); + halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0); + } else if (ofdm_rx == RF_PATH_AB) { + halbb_set_reg(bb, 0x49C4, 0xf, 0x3); + /*==== 1rcca ====*/ + halbb_set_reg(bb, 0x49C0, 0x3C000, 0x3); + halbb_set_reg(bb, 0x49C0, 0x3C0000, 0x3); + /*==== Rx HT nss_limit / mcs_limit ====*/ + halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 1); + halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 1); + /*==== Rx HE n_user_max / tb_max_nss ====*/ + halbb_set_reg(bb, 0xd80, 0x3fc0, 4); + halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 1); + halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 1); + } + /*==== [Set Efuse] =====*/ + halbb_set_efuse_8852b(bb, bb->hal_com->band[0].cur_chandef.center_ch, HW_PHY_0); + + /* === [BTG setting] === */ + if ((bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) && ((rx_path == RF_PATH_B) || (rx_path == RF_PATH_AB))) + halbb_ctrl_btg_8852b(bb, true); + else + halbb_ctrl_btg_8852b(bb, false); + + /*==== [TSSI reset] ====*/ + if (rx_path == RF_PATH_A) { + halbb_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1); + halbb_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3); + } else { + halbb_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1); + halbb_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3); + } + + /*==== [BB reset] ====*/ + //halbb_bb_reset_all_8852b(bb, HW_PHY_0); + BB_DBG(bb, DBG_PHY_CONFIG, "[Rx Success]RX_en=%x\n", rx_path); + return true; + +} + +bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + /*==== [P-MAC] Path & Path_map Enable ====*/ + halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x7, HW_PHY_0); + halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x7, HW_PHY_1); + + + if (tx_path == RF_PATH_A) { + halbb_set_reg(bb, 0x458C, 0xf0000000, 0x1); + halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0); + } else if (tx_path == RF_PATH_B) { + halbb_set_reg(bb, 0x458C, 0xf0000000, 0x2); + halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0); + } else if (tx_path == RF_PATH_AB) { + halbb_set_reg(bb, 0x458C, 0xf0000000, 0x3); + halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x4); + } else { + BB_WARNING("Invalid Tx Path\n"); + return false; + } + + /*==== [BB reset] ====*/ + halbb_bb_reset_all_8852b(bb, HW_PHY_0); + BB_DBG(bb, DBG_PHY_CONFIG, "[Success] [P-MAC] Tx Path Config\n"); + return true; +} + +void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode) +{ + if (mode == RF_MODE_STANDBY) { + halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x1111111); + halbb_set_reg(bb, 0x12b0, 0xfff, 0x111); + halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x1111111); + halbb_set_reg(bb, 0x32b0, 0xfff, 0x111); + } else if (mode == RF_MODE_SHUTDOWN) { + halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x0); + halbb_set_reg(bb, 0x12b0, 0xfff, 0x0); + halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x0); + halbb_set_reg(bb, 0x32b0, 0xfff, 0x0); + } else { + halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x233302); + halbb_set_reg(bb, 0x12b0, 0xfff, 0x333); + halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x233302); + halbb_set_reg(bb, 0x32b0, 0xfff, 0x333); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[RF Mode] Mode = %d", mode); +} + +u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + // Return CMAC [OFST 20] Tx settings // + /* [19:16] path_en[3:0] || + || [21:20] map_a[1:0] || + || [23:22] map_b[1:0] || + || [25:24] map_c[1:0] || + || [27:26] map_d[1:0] || + || [28] ant_sel_a[0] || + || [29] ant_sel_b[0] || + || [30] ant_sel_c[0] || + || [31] ant_sel_d[0] */ + u16 cmac_tx_info = 0; + + if (tx_path == RF_PATH_A) { + cmac_tx_info = 0x1; + } else if (tx_path == RF_PATH_B) { + cmac_tx_info = 0x2; + } else if (tx_path == RF_PATH_AB) { + cmac_tx_info = 0x43; + } else { + cmac_tx_info = 0xffff; + BB_WARNING("Invalid Tx Path: %d\n", tx_path); + } + return cmac_tx_info; + +} + +void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path, + u8 tx_nss, enum rf_path rx_path, u8 rx_nss) +{ + // Rx Config + halbb_ctrl_rx_path_8852b(bb, rx_path); + + if ((rx_nss > 2) || (tx_nss > 2)) { + BB_WARNING("[Invalid Nss]Tx Nss: %d, Rx Nss: %d\n", tx_nss, + rx_nss); + return; + } + + if (rx_nss == 1) { + /*==== [PHY0] Rx HT nss_limit / mcs_limit ====*/ + halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0); + halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0); + /*==== [PHY0] Rx HE n_user_max / tb_max_nss ====*/ + halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0); + halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0); + } else { + /*==== [PHY0] Rx HT nss_limit / mcs_limit ====*/ + halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 1); + halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 1); + /*==== [PHY0] Rx HE n_user_max / tb_max_nss ====*/ + halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 1); + halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 1); + } + + // Tx Config (to do) + // Need to Add MP flag for Tx_path API since Normal Drv will also call this function + // ==== [T-MAC] Path & Path_map Enable ==== // + halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x0, HW_PHY_0); + +} + +void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx) +{ + if (cca_en) { + halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx); + halbb_set_reg(bb, 0x2344, BIT(31), 0); + } else { + halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx); + halbb_set_reg(bb, 0x2344, BIT(31), 1); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[Rx CCA] CCA_EN = %d\n", cca_en); +} + +void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en, + enum phl_phy_idx phy_idx) +{ + if (ofdm_en) + halbb_set_reg_cmn(bb, 0x700, BIT(4), 1, phy_idx); + else + halbb_set_reg_cmn(bb, 0x700, BIT(4), 0, phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[OFDM Enable for PHY%d]\n", phy_idx); +} + + + +// =================== [Power Module] =================== // +bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm, + enum phl_phy_idx phy_idx) +{ + bool tmp = false; + + power_dbm &= 0x1ff; + halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 1, phy_idx); + halbb_set_reg_cmn(bb, 0x4594, 0x7fc00000, power_dbm, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] Set Tx pwr(dBm) for [PHY-%d] : %d\n", phy_idx, + power_dbm); + tmp = true; + return tmp; +} + +s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + u32 txpwr_dbm; + s16 output; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + txpwr_dbm = halbb_get_reg_cmn(bb, 0x4594, 0x7fc00000, phy_idx); + output = (s16)halbb_cnvrt_2_sign(txpwr_dbm, 9); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] Get Tx pwr(dBm) for [PHY-%d] : %d\n", phy_idx, + output); + return output; +} + +s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb) +{ + u32 txpwr_dbm; + s16 output; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + txpwr_dbm = halbb_get_reg(bb, 0x1804, 0x7FC0000); + output = (s16)halbb_cnvrt_2_sign(txpwr_dbm, 9); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] Get TxInfo pwr(dBm) : %d\n", output); + return output; +} + +bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx, + enum rf_path tx_path) +{ + u32 pwr_idx_addr[2] = {0x5808, 0x7808}; + + /*==== Power index Check ====*/ + if ((power_idx & ~0x1ff) != 0) { + BB_WARNING("Power Idx: %x\n", power_idx); + return false; + } + /*==== Tx Path Check ====*/ + if (tx_path > RF_PATH_B) { + BB_WARNING("Invalid Tx Path for CCK Txpwr_idx setting (52A)\n"); + return false; + } + halbb_set_reg(bb, pwr_idx_addr[tx_path], 0x3fe00, power_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [CCK] Set Tx pwr idx for [Path-%d] : %x\n", + tx_path, power_idx); + return true; +} + +u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + u16 cck_pwr_idx; + u32 pwr_idx_addr[2] = {0x5808, 0x7808}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + cck_pwr_idx = (u16)halbb_get_reg(bb, pwr_idx_addr[tx_path], 0x3fe00); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [CCK] Get Tx pwr idx for [Path-%d] : %x\n", + tx_path, cck_pwr_idx); + return cck_pwr_idx; +} + +s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + u32 cck_ref_dbm; + u32 pwr_ref_addr[2] = {0x5808, 0x7808}; + s16 output; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + cck_ref_dbm = halbb_get_reg(bb, pwr_ref_addr[tx_path], 0x1ff); + output = (s16)halbb_cnvrt_2_sign(cck_ref_dbm, 9); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [CCK] Get Tx ref pwr(dBm) for [Path-%d] : %d\n", + tx_path, output); + return output; +} + +bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx, + enum rf_path tx_path) +{ + u32 pwr_idx_addr[2] = {0x5804, 0x7804}; + + /*==== Power index Check ====*/ + if ((power_idx & ~0x1ff) != 0) { + BB_WARNING("Power Idx: %x\n", power_idx); + return false; + } + /*==== Tx Path Check ====*/ + if (tx_path > RF_PATH_B) { + BB_WARNING("Invalid Tx Path for CCK Txpwr_idx setting (52A)\n"); + return false; + } + + halbb_set_reg(bb, pwr_idx_addr[tx_path], 0x3fe00, power_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [OFDM] Set Tx pwr idx for [Path-%d] : %x\n", + tx_path, power_idx); + return true; +} + +u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + u16 ofdm_pwr_idx; + u32 pwr_idx_addr[2] = {0x5804, 0x7804}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + ofdm_pwr_idx = (u16)halbb_get_reg(bb, pwr_idx_addr[tx_path], 0x3fe00); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [OFDM] Get Tx pwr idx for [Path-%d] : %x\n", + tx_path, ofdm_pwr_idx); + return ofdm_pwr_idx; +} + +s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path) +{ + u32 ofdm_ref_dbm; + u32 pwr_ref_addr[2] = {0x5804, 0x7804}; + s16 output; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + ofdm_ref_dbm = halbb_get_reg(bb, pwr_ref_addr[tx_path], 0x1ff); + output = (s16)halbb_cnvrt_2_sign(ofdm_ref_dbm, 9); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [OFDM] Get Tx ref pwr(dBm) for [Path-%d] : %d\n", + tx_path, output); + return output; +} + +void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb) +{ + + /*@ Reset all counter*/ + halbb_set_reg(bb, 0x730, BIT(0), 1); + halbb_set_reg(bb, 0x730, BIT(0), 0); + +} + +void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + /*==== This Backup info is for RF TSSI calibration =====*/ + bb->bb_cmn_backup_i.cur_tx_path = (u8)halbb_get_reg_cmn(bb, 0x458c, 0xf0000000, phy_idx); + bb->bb_cmn_backup_i.cur_rx_path = (u8)halbb_get_reg_cmn(bb, 0x49c4, 0xf, phy_idx); + bb->bb_cmn_backup_i.cur_tx_pwr = halbb_get_txpwr_dbm_8852b(bb, phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Backup Info] [PHY%d] Tx path = %x\n", phy_idx, bb->bb_cmn_backup_i.cur_tx_path); + BB_DBG(bb, DBG_PHY_CONFIG, "[Backup Info] [PHY%d] Tx pwr = %x\n", phy_idx, (u16)bb->bb_cmn_backup_i.cur_tx_pwr); +} + +void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + /*==== This Restore info is for RF TSSI calibration =====*/ + halbb_set_reg_cmn(bb, 0x458c, 0xf0000000, bb->bb_cmn_backup_i.cur_tx_path, phy_idx); + if (bb->bb_cmn_backup_i.cur_tx_path == 0x3) { + halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x4); + } else { + halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0); + } + halbb_set_reg_cmn(bb, 0x49c4, 0xf, bb->bb_cmn_backup_i.cur_rx_path, phy_idx); + halbb_set_txpwr_dbm_8852b(bb, bb->bb_cmn_backup_i.cur_tx_pwr, phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Restore Info] [PHY%d] Tx path = %x\n", phy_idx, bb->bb_cmn_backup_i.cur_tx_path); + BB_DBG(bb, DBG_PHY_CONFIG, "[Restore Info] [PHY%d] Tx pwr = %x\n", phy_idx, (u16)bb->bb_cmn_backup_i.cur_tx_pwr); +} + +bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx) +{ + /*==== txsc Check ====*/ + if ((txsc & ~0xf) != 0) { + BB_WARNING("TXSC: %x\n", txsc); + return false; + } + halbb_set_reg_cmn(bb, 0x45ac, 0x7800000, txsc, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [P-MAC] TXSC for [PHY-%d] : %x\n", phy_idx, + txsc); + return true; +} + +#if 0 +void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (btg) { + // Path A + halbb_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x1); + // Path B + halbb_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x3); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n"); + // Apply Grant BT by TMAC Setting + halbb_set_reg(bb, 0x980, 0x1e0000, 0x0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n"); + } else { + // Path A + halbb_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x0); + // Path B + halbb_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n"); + // Ignore Grant BT by PMAC Setting + halbb_set_reg(bb, 0x980, 0x1e0000, 0xf); + halbb_set_reg(bb, 0x980, 0x3c000000, 0x4); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n"); + } +} +#endif +bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color, + enum phl_phy_idx phy_idx) +{ + /*==== BSS color Check ====*/ + if ((bss_color & ~0x3f) != 0) { + BB_WARNING("BSS color: %x\n", bss_color); + return false; + } + //=== [Enable BSS color mapping] ===// + halbb_set_reg_cmn(bb, 0x43b0, BIT(28), 0x1, phy_idx); + halbb_set_reg_cmn(bb, 0x43b0, 0xfc00000, bss_color, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [P-MAC] BSS Color for [PHY-%d] : %x\n", phy_idx, + bss_color); + return true; +} + +bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id, + enum phl_phy_idx phy_idx) +{ + /*==== Station ID Check ====*/ + if ((sta_id & ~0x7ff) != 0) { + BB_WARNING("Station ID: %x\n", sta_id); + return false; + } + //=== [Set Station ID] ===// + halbb_set_reg_cmn(bb, 0x43b0, 0x3ff800, sta_id, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Success] [P-MAC] Station ID for [PHY-%d] : %x\n", phy_idx, + sta_id); + + return true; +} + +void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx, + u8 rxbb_idx, enum rf_path path) +{ + u8 lna = 0; + bool tia = 0; + u8 rxbb = 0; + + u32 lna_addr[2] = {0x472c, 0x4a80}; + u32 tia_addr[2] = {0x473c, 0x4aa8}; + u32 rxbb_addr[2] = {0x46a8, 0x4a5c}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + halbb_set_reg(bb, lna_addr[path], 0x7000000, lna_idx); + halbb_set_reg(bb, tia_addr[path], BIT(9), tia_idx); + halbb_set_reg(bb, rxbb_addr[path], 0x7c00, rxbb_idx); + + lna = (u8)halbb_get_reg(bb, lna_addr[path], BIT(26) | BIT(25) | BIT(24)); + tia = (bool)halbb_get_reg(bb, tia_addr[path], BIT(9)); + rxbb = (u8)halbb_get_reg(bb, rxbb_addr[path], 0x7c00); + + BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] LNA for [Path-%d] : %d\n", path, lna); + BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] TIA for [Path-%d] : %d\n", path, tia); + BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] RxBB for [Path-%d] : %d\n", path, rxbb); +} + +void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm, /*s(9,2)*/ + s16 pw_dbm_cck, s8 ofst, + u8 base_cw_0db, u16 tssi_16dBm_cw, + u16 *ofdm_cw, u16 *cck_cw, + enum phl_phy_idx phy_idx) +{ + s16 rf_pw_cw = 0; + u32 pw_cw = 0; + u32 val = 0; + s16 pw_s10_3 = 0; + u32 tssi_ofst_cw = 0; + + /*OFDM*/ + pw_s10_3 = (pw_dbm_ofdm * 2) + (s16)(ofst) + (s16)(base_cw_0db * 8); + + + pw_cw = pw_s10_3; + rf_pw_cw = (pw_s10_3 & 0x1F8) >> 3; + + if (rf_pw_cw > 63) + pw_cw = (63 << 3) | (pw_s10_3 & 0x7); /*upper bound (+24dBm)*/ + else if (rf_pw_cw < 15) + pw_cw = (15 << 3) | (pw_s10_3 & 0x7); /*lower bound (-24dBm)*/ + + /* ===[Set TSSI Offset]===============================================*/ + /* + 172 = 300 - (55 - 39) * 8; + tssi_ofst_cw = tssi_16dBm_cw - (tx_pow_16dBm_ref_cw - tx_pow_ref_cw) * 8; + = tssi_16dBm_cw + tx_pow_ref * 8 - tx_pow_16dBm_ref * 8 + */ + tssi_ofst_cw = (u32)((s16)tssi_16dBm_cw + (pw_dbm_ofdm * 2) - (16 * 8)); + + BB_DBG(bb, DBG_DBG_API, "[OFDM]tssi_ofst_cw=%d, rf_cw=0x%x, bb_cw=0x%x\n", tssi_ofst_cw, pw_cw >> 3, pw_cw & 0x7); + + *ofdm_cw = (u16)pw_cw; + val = tssi_ofst_cw << 18 | pw_cw << 9 | (u32)(pw_dbm_ofdm & 0x1ff); + halbb_set_reg_cmn(bb, 0x5804, 0x7FFFFFF, val, phy_idx); + halbb_set_reg_cmn(bb, 0x7804, 0x7FFFFFF, val, phy_idx); + + /*CCK*/ + pw_s10_3 = (pw_dbm_cck * 2) + (s16)(ofst) + (s16)(base_cw_0db * 8); + + pw_cw = pw_s10_3; + rf_pw_cw = (pw_s10_3 & 0x1F8) >> 3; + + if (rf_pw_cw > 63) + pw_cw = (63 << 3) | (pw_s10_3 & 0x7); /*upper bound (+24dBm)*/ + else if (rf_pw_cw < 15) + pw_cw = (15 << 3) | (pw_s10_3 & 0x7); /*lower bound (-24dBm)*/ + + /* ===[Set TSSI Offset]===============================================*/ + /* + 172 = 300 - (55 - 39) * 8; + tssi_ofst_cw = tssi_16dBm_cw - (tx_pow_16dBm_ref_cw - tx_pow_ref_cw) * 8; + = tssi_16dBm_cw + tx_pow_ref * 8 - tx_pow_16dBm_ref * 8 + */ + tssi_ofst_cw = (u32)((s16)tssi_16dBm_cw + (pw_dbm_cck * 2) - (16 * 8)); + + BB_DBG(bb, DBG_DBG_API, "[CCK] tssi_ofst_cw=%d, rf_cw=0x%x, bb_cw=0x%x\n", tssi_ofst_cw, pw_cw >> 3, pw_cw & 0x7); + + *cck_cw = (u16)pw_cw; + val = tssi_ofst_cw << 18 | pw_cw << 9 | (u32)(pw_dbm_cck & 0x1ff); + halbb_set_reg_cmn(bb, 0x5808, 0x7FFFFFF, val, phy_idx); + halbb_set_reg_cmn(bb, 0x7808, 0x7FFFFFF, val, phy_idx); + +} + +void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len, bool dump_2_buff) +{ + u32 i = 0, addr = 0; + u32 cr_start = 0, cr_end = 0; + u32 dump_cr_table[][2] = {{0x0000, 0x04FC}, + {0x0600, 0x0DFC}, + {0x1000, 0x10FC}, + {0x1200, 0x13FC}, + {0x1700, 0x20FC}, + {0x2200, 0x24FC}, + {0x2600, 0x2DFC}, + {0x3000, 0x30FC}, + {0x3200, 0x33FC}, + {0x3900, 0x4FFC}, + {0x5800, 0x6FFC}, + {0x7800, 0x7FFC}}; + u32 table_len = sizeof(dump_cr_table)/(sizeof(u32) * 2); + + BB_TRACE("BBCR: dump all ==>\n"); + BB_TRACE("table_len=%d\n", table_len); + + for (i = 0; i < table_len; i ++) { + if (dump_2_buff) + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%02d] Reg[0x%04x ~ 0x%04x]\n\n", + i, dump_cr_table[i][0], dump_cr_table[i][1]); + else + BB_TRACE("[%02d] Reg[0x%04x ~ 0x%04x]\n\n", + i, dump_cr_table[i][0], dump_cr_table[i][1]); + + } + + for (i = 0; i < table_len; i ++) { + cr_start = dump_cr_table[i][0]; + cr_end = dump_cr_table[i][1]; + for (addr = cr_start; addr <= cr_end; addr += 4) { + if (dump_2_buff) + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "0x%04x 0x%08x\n", + addr, halbb_get_reg(bb, addr, MASKDWORD)); + else + BB_TRACE("0x%04x 0x%08x\n", + addr, halbb_get_reg(bb, addr, MASKDWORD)); + } + } +} + +void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len) +{ + const u32 dump_dbgport_table[][3] = { + {DBGPORT_IP_TD, 0x001, 0x026}, + {DBGPORT_IP_TD, 0x200, 0x2ff}, + {DBGPORT_IP_TD, 0xb01, 0xb27}, + {DBGPORT_IP_RX_INNER, 0x0, 0x29}, + {DBGPORT_IP_TX_INNER, 0x0, 0x8}, + {DBGPORT_IP_OUTER, 0x0, 0xaa}, + {DBGPORT_IP_OUTER, 0xc0, 0xc4}, + {DBGPORT_IP_INTF, 0x0, 0x40}, + {DBGPORT_IP_CCK, 0x0, 0x3e}, + {DBGPORT_IP_BF, 0x0, 0x59}, + {DBGPORT_IP_RX_OUTER, 0x00, 0x63}, + {DBGPORT_IP_RX_OUTER, 0x90, 0x98}, + {DBGPORT_IP_RX_OUTER, 0xc0, 0xc3}, + {DBGPORT_IP_RX_OUTER, 0xe0, 0xe3}}; + u32 table_len; + u32 dp = 0; /*debug port value*/ + u8 i; + u32 j; + u32 dbg_start = 0, dbg_end = 0; + + table_len = sizeof(dump_dbgport_table) / (sizeof(u32) * 3); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "BB DBG Port: dump all ==>\n"); + + for (i = 0; i < table_len; i++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%02d][IP=%02d] Dbgport[0x%03x ~ 0x%03x]\n", + i, dump_dbgport_table[i][0], + dump_dbgport_table[i][1], dump_dbgport_table[i][2]); + } + + for (i = 0; i < table_len; i++) { + halbb_set_bb_dbg_port_ip(bb, dump_dbgport_table[i][0]); + dbg_start = dump_dbgport_table[i][1]; + dbg_end = dump_dbgport_table[i][2]; + for (j = dbg_start; j <= dbg_end; j ++) { + halbb_set_bb_dbg_port(bb, j); + dp = halbb_get_bb_dbg_port_val(bb); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[0x%02x, 0x%03x] = 0x%08x\n", + dump_dbgport_table[i][0], j, dp); + } + } + halbb_release_bb_dbg_port(bb); +} + +void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable, + enum phl_phy_idx phy_idx) +{ + u32 val32 = (enable) ? 0 : 0x3; + + halbb_set_reg_cmn(bb, 0x0738, 0xC, 0x3, phy_idx); +} + +bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data) +{ + u32 page = (addr & 0xff00) >> 8; + + if (page != 0x0c && page != 0x20 && page != 0x2c && + page != 0x58 && page != 0x78 && + addr != 0x0700 && addr != 0x12a0 && addr != 0x12b8 && + addr != 0x2320 && addr != 0x2700 && + addr != 0x32a0 && addr != 0x32b8) { + return false; + } + + halbb_set_reg(bb, addr, mask, data); + return true; +} + +void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable) +{ + u8 en = 0; + + en = (enable == true) ? 1 : 0; + halbb_set_reg(bb, 0x4730, BIT(31), en); + halbb_set_reg(bb, 0x4A9C, BIT(31), en); + + BB_DBG(bb, DBG_DBG_API, "PreAGC en: 0x4730C[31]=(0x%x),0x4A9C[31]=(0x%x)\n", + en, en); +} + +s8 halbb_efuse_exchange_8852b(struct bb_info *bb, u8 value, + enum efuse_bit_mask mask) +{ + s8 tmp = 0; + + if (mask == LOW_MASK) { + tmp = value & 0xf; + + if (tmp & BIT(3)) + tmp = tmp | 0xf0; + } else { + tmp = (value & 0xf0) >> 4; + + if (tmp & BIT(3)) + tmp = tmp | 0xf0; + } + + return tmp; +} + +void halbb_get_normal_efuse_init_8852b(struct bb_info *bb) +{ + struct bb_efuse_info *gain = &bb->bb_efuse_i; + u8 tmp; + u8 tmp_ofst; + u32 check_tmp = 0, i, j; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + tmp_ofst = (u8)halbb_get_reg(bb, 0x49B0, 0xff); + bb->bb_efuse_i.efuse_ofst = (s8)halbb_cnvrt_2_sign(tmp_ofst, 8); + tmp_ofst = (u8)halbb_get_reg(bb, 0x4A00, 0xff); + bb->bb_efuse_i.efuse_ofst_tb = (s8)halbb_cnvrt_2_sign(tmp_ofst, 8); + + halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK, &tmp, 1); + gain->gain_offset[RF_PATH_A][0] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK); + gain->gain_offset[RF_PATH_B][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD, &tmp, 1); + gain->gain_offset[RF_PATH_A][1] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK); + gain->gain_offset[RF_PATH_B][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GL, &tmp, 1); + gain->gain_offset[RF_PATH_A][2] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK); + gain->gain_offset[RF_PATH_B][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GM, &tmp, 1); + gain->gain_offset[RF_PATH_A][3] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK); + gain->gain_offset[RF_PATH_B][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GH, &tmp, 1); + gain->gain_offset[RF_PATH_A][4] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK); + gain->gain_offset[RF_PATH_B][4] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + for (i = 0; i < HALBB_MAX_PATH; i++) { + for (j = 0; j < BB_EFUSE_BAND_NUM; j++) { + BB_DBG(bb, DBG_INIT, "[Efuse]gain->gain_offset[%d][%d]=0x%x\n", i, j, gain->gain_offset[i][j]); + if ((gain->gain_offset[i][j] & 0xf) == 0xf) + check_tmp++; + } + } + + BB_DBG(bb, DBG_INIT, "[Efuse]check_tmp = %d\n", check_tmp); + BB_DBG(bb, DBG_INIT, "[Efuse]HALBB_MAX_PATH * BB_EFUSE_BAND_NUM = %d\n", HALBB_MAX_PATH * BB_EFUSE_BAND_NUM); + + if (check_tmp == HALBB_MAX_PATH * BB_EFUSE_BAND_NUM) + bb->bb_efuse_i.normal_efuse_check = false; + else + bb->bb_efuse_i.normal_efuse_check = true; +/* + BB_DBG(bb, DBG_INIT, + "[Efuse][Gain 2G][CCK] Path-A: %d, Path-B: %d\n", + gain->gain_offset[RF_PATH_A][0], gain->gain_offset[RF_PATH_B][0]); + BB_DBG(bb, DBG_INIT, + "[Efuse][Gain 2G][OFDM] Path-A: %d, Path-B: %d\n", + gain->gain_offset[RF_PATH_A][1], gain->gain_offset[RF_PATH_B][1]); + BB_DBG(bb, DBG_INIT, + "[Efuse][Gain 5GL] Path-A: %d, Path-B: %d\n", + gain->gain_offset[RF_PATH_A][2], gain->gain_offset[RF_PATH_B][2]); + BB_DBG(bb, DBG_INIT, + "[Efuse][Gain 5GM] Path-A: %d, Path-B: %d\n", + gain->gain_offset[RF_PATH_A][3], gain->gain_offset[RF_PATH_B][3]); + BB_DBG(bb, DBG_INIT, + "[Efuse][Gain 5GH] Path-A: %d, Path-B: %d\n", + gain->gain_offset[RF_PATH_A][4], gain->gain_offset[RF_PATH_B][4]); +*/ +} + +void halbb_get_hide_efuse_init_8852b(struct bb_info *bb) +{ + struct bb_efuse_info *gain = &bb->bb_efuse_i; + u8 tmp; + u32 check_tmp = 0, i , j; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_2G_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_A][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GL_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_A][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GM_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_A][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GH_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_A][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_2G_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_B][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GL_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_B][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GM_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_B][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GH_8852B, 1, &tmp); + gain->gain_cs[RF_PATH_B][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK); + + for (i = 0; i < HALBB_MAX_PATH; i++) { + for (j = 0; j < BB_GAIN_BAND_NUM; j++) { + BB_DBG(bb, DBG_INIT, "[Efuse]gain->gain_cs[%d][%d]=0x%x\n", i, j, gain->gain_cs[i][j]); + if ((gain->gain_cs[i][j] & 0xf) == 0xf) + check_tmp++; + } + } + + BB_DBG(bb, DBG_INIT, "[Efuse]check_tmp = %d\n", check_tmp); + BB_DBG(bb, DBG_INIT, "[Efuse]HALBB_MAX_PATH * BB_GAIN_BAND_NUM = %d\n", HALBB_MAX_PATH * BB_GAIN_BAND_NUM); + + if (check_tmp == HALBB_MAX_PATH * BB_GAIN_BAND_NUM) + bb->bb_efuse_i.hidden_efuse_check = false; + else + bb->bb_efuse_i.hidden_efuse_check = true; + + +/* + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 2G][Path-A] CS: %d , %d, %x\n", + gain->gain_cs[RF_PATH_A][0],gain->gain_cs[RF_PATH_A][0]<<2,gain->gain_cs[RF_PATH_A][0]<<2); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GL][Path-A] CS: %d, %d, %x\n", + gain->gain_cs[RF_PATH_A][1],gain->gain_cs[RF_PATH_A][1]<<2,gain->gain_cs[RF_PATH_A][1]<<2); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GM][Path-A] CS: %d, %d, %x\n", + gain->gain_cs[RF_PATH_A][2],gain->gain_cs[RF_PATH_A][2]<<2,gain->gain_cs[RF_PATH_A][2]<<2); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GH][Path-A] CS: %d, %d, %x\n", + gain->gain_cs[RF_PATH_A][3],gain->gain_cs[RF_PATH_A][3]<<2,gain->gain_cs[RF_PATH_A][3]<<2); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 2G][Path-B] CS: %d\n", + gain->gain_cs[RF_PATH_B][0]); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GL][Path-B] CS: %d\n", + gain->gain_cs[RF_PATH_B][1]); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GM][Path-B] CS: %d\n", + gain->gain_cs[RF_PATH_B][2]); + BB_DBG(bb, DBG_PHY_CONFIG, + "[Hidden Efuse][Gain 5GH][Path-B] CS: %d\n", + gain->gain_cs[RF_PATH_B][3]); +*/ + +} + +void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx) +{ + u8 band; + u8 gain_val = 0; + s32 hidden_efuse = 0, normal_efuse = 0, normal_efuse_cck = 0; + s32 tmp = 0; + u8 path = 0; + u32 gain_err_addr[2] = {0x4ACC, 0x4AD8}; //Wait for Bcut Def + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // 2G Band: (0) + // 5G Band: (1):Low, (2): Mid, (3):High + if (central_ch >= 0 && central_ch <= 14) + band = 0; + else if (central_ch >= 36 && central_ch <= 64) + band = 1; + else if (central_ch >= 100 && central_ch <= 144) + band = 2; + else if (central_ch >= 149 && central_ch <= 177) + band = 3; + else + band = 0; + + // === [Set hidden efuse] === // + if (bb->bb_efuse_i.hidden_efuse_check) { + for (path = RF_PATH_A; path < BB_PATH_MAX_8852B; path++) { + gain_val = bb->bb_efuse_i.gain_cs[path][band] << 2; + halbb_set_reg(bb, gain_err_addr[path], 0xff, gain_val); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Hidden efuse dynamic setting!!\n"); + + } else { + BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Values of hidden efuse are all 0xff, bypass dynamic setting!!\n"); + } + + // === [Set normal efuse] === // + if (bb->bb_efuse_i.normal_efuse_check) { + if ((bb->rx_path == RF_PATH_A) || (bb->rx_path == RF_PATH_AB)) { + normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_A][band + 1]; + normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_A][0]; + } else if (bb->rx_path == RF_PATH_B) { + normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_B][band + 1]; + normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_B][0]; + } + normal_efuse *= (-1); + normal_efuse_cck *= (-1); + + // OFDM normal efuse + // r_1_rpl_bias_comp + tmp = (normal_efuse << 4) + bb->bb_efuse_i.efuse_ofst; + halbb_set_reg_cmn(bb, 0x49B0, 0xff, (tmp & 0xff), phy_idx); + // r_tb_rssi_bias_comp + tmp = (normal_efuse << 4) + bb->bb_efuse_i.efuse_ofst_tb; + halbb_set_reg_cmn(bb, 0x4A00, 0xff, (tmp & 0xff), phy_idx); + // CCK normal efuse + if (band == 0) { + tmp = (normal_efuse_cck << 3) + (bb->bb_efuse_i.efuse_ofst >>1); + halbb_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f)); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Normal efuse dynamic setting!!\n"); + } else { + BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Values of normal efuse are all 0xff, bypass dynamic setting!!\n"); + } +} + +void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch) +{ + struct bb_gain_info *gain = &bb->bb_gain_i; + + u8 band; + u8 path = 0, lna_idx = 0, tia_idx = 0; + s32 tmp = 0; + u32 lna_gain_g[BB_PATH_MAX_8852B][7] = {{0x4678, 0x4678, 0x467C, + 0x467C, 0x467C, 0x467C, + 0x4680}, {0x475C, 0x475C, + 0x4760, 0x4760, 0x4760, + 0x4760, 0x4764}}; + u32 lna_gain_a[BB_PATH_MAX_8852B][7] = {{0x45DC, 0x45DC, 0x4660, + 0x4660, 0x4660, 0x4660, + 0x4664}, {0x4740, 0x4740, + 0x4744, 0x4744, 0x4744, + 0x4744, 0x4748}}; + u32 lna_gain_mask[7] = {0x00ff0000, 0xff000000, 0x000000ff, + 0x0000ff00, 0x00ff0000, 0xff000000, + 0x000000ff}; + u32 tia_gain_g[BB_PATH_MAX_8852B][2] = {{0x4680, 0x4680}, {0x4764, + 0x4764}}; + u32 tia_gain_a[BB_PATH_MAX_8852B][2] = {{0x4664, 0x4664}, {0x4748, + 0x4748}}; + u32 tia_gain_mask[2] = {0x00ff0000, 0xff000000}; + + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // 2G Band: (0) + // 5G Band: (1):Low, (2): Mid, (3):High + if (central_ch >= 0 && central_ch <= 14) + band = 0; + else if (central_ch >= 36 && central_ch <= 64) + band = 1; + else if (central_ch >= 100 && central_ch <= 144) + band = 2; + else if (central_ch >= 149 && central_ch <= 177) + band = 3; + else + band = 0; + + for (path = RF_PATH_A; path < BB_PATH_MAX_8852B; path++) { + for (lna_idx = 0; lna_idx < 7; lna_idx++) { + if (central_ch >= 0 && central_ch <= 14) { + tmp = gain->lna_gain[band][path][lna_idx]; + halbb_set_reg(bb, lna_gain_g[path][lna_idx], lna_gain_mask[lna_idx], tmp); + } else { + tmp = gain->lna_gain[band][path][lna_idx]; + halbb_set_reg(bb, lna_gain_a[path][lna_idx], lna_gain_mask[lna_idx], tmp); + } + } + + for (tia_idx = 0; tia_idx < 2; tia_idx++) { + if (central_ch >= 0 && central_ch <= 14) { + tmp = gain->tia_gain[band][path][tia_idx]; + halbb_set_reg(bb, tia_gain_g[path][tia_idx], tia_gain_mask[tia_idx], tmp); + } else { + tmp = gain->tia_gain[band][path][tia_idx]; + halbb_set_reg(bb, tia_gain_a[path][tia_idx], tia_gain_mask[tia_idx], tmp); + } + } + } + +} + +void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch) +{ + struct bb_gain_info *gain = &bb->bb_gain_i; + u8 band; + u8 path = 0; + u8 i = 0; + u8 rxsc = 0; + s8 ofst = 0; + s8 bw20_avg = 0; + s8 bw40_avg = 0, bw40_avg_1 = 0, bw40_avg_2 = 0; + s8 bw80_avg = 0; + s8 bw80_avg_1 = 0, bw80_avg_2 = 0, bw80_avg_3 = 0, bw80_avg_4 = 0; + s8 bw80_avg_9 = 0, bw80_avg_10 = 0; + u32 tmp_val1 = 0, tmp_val2 = 0, tmp_val3 = 0; + + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (central_ch >= 0 && central_ch <= 14) { + band = 0; + } else if (central_ch >= 36 && central_ch <= 64) { + band = 1; + } else if (central_ch >= 100 && central_ch <= 144) { + band = 2; + } else if (central_ch >= 149 && central_ch <= 177) { + band = 3; + } else { + band = 0; + } + //20M RPL + bw20_avg = (gain->rpl_ofst_20[band][RF_PATH_A] + + gain->rpl_ofst_20[band][RF_PATH_B]) >> 1; + tmp_val1 |= (((u32)bw20_avg & 0xff) << 8); + //40M RPL + bw40_avg = (gain->rpl_ofst_40[band][RF_PATH_A][0] + + gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1; + tmp_val1 |= (((u32)bw40_avg & 0xff) << 16); + bw40_avg_1 = (gain->rpl_ofst_40[band][RF_PATH_A][1] + + gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1; + tmp_val1 |= (((u32)bw40_avg_1 & 0xff) << 24); + + bw40_avg_2 = (gain->rpl_ofst_40[band][RF_PATH_A][2] + + gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1; + tmp_val2 |= ((u32)bw40_avg_2 & 0xff); + //80M RPL + bw80_avg = (gain->rpl_ofst_80[band][RF_PATH_A][0] + + gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1; + tmp_val2 |= ((u32)(bw80_avg & 0xff) << 8); + bw80_avg_1 = (gain->rpl_ofst_80[band][RF_PATH_A][1] + + gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1; + tmp_val2 |= (((u32)bw80_avg_1 & 0xff) << 16); + bw80_avg_10 = (gain->rpl_ofst_80[band][RF_PATH_A][10] + + gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1; + tmp_val2 |= (((u32)bw80_avg_10 & 0xff) << 24); + + bw80_avg_2 = (gain->rpl_ofst_80[band][RF_PATH_A][2] + + gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1; + tmp_val3 |= ((u32)bw80_avg_2 & 0xff); + bw80_avg_3 = (gain->rpl_ofst_80[band][RF_PATH_A][3] + + gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1; + tmp_val3 |= (((u32)bw80_avg_3 & 0xff) << 8); + bw80_avg_4 = (gain->rpl_ofst_80[band][RF_PATH_A][4] + + gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1; + tmp_val3 |= (((u32)bw80_avg_4 & 0xff) << 16); + bw80_avg_9 = (gain->rpl_ofst_80[band][RF_PATH_A][9] + + gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1; + tmp_val3 |= (((u32)bw80_avg_9 & 0xff) << 24); + + + BB_DBG(bb, DBG_PHY_CONFIG, "[20M RPL] gain ofst = 0x%2x\n", + bw20_avg&0xff); + BB_DBG(bb, DBG_PHY_CONFIG, "[40M RPL] gain ofst = 0x%2x, 0x%2x, 0x%2x\n", + bw40_avg&0xff, bw40_avg_1&0xff, bw40_avg_2&0xff); + BB_DBG(bb, DBG_PHY_CONFIG, "[80M RPL] gain ofst = 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x\n", + bw80_avg&0xff,bw80_avg_1&0xff,bw80_avg_2&0xff,bw80_avg_3&0xff,bw80_avg_4&0xff,bw80_avg_9&0xff,bw80_avg_10&0xff); + BB_DBG(bb, DBG_PHY_CONFIG, "tmp1 = 0x%x, tmp2 = 0x%x, tmp3 = 0x%x\n", + tmp_val1, tmp_val2, tmp_val3); + + halbb_set_reg(bb, 0x49b0, 0xffffff00, tmp_val1 >> 8); + halbb_set_reg(bb, 0x4a00, 0xffffff00, tmp_val1 >> 8); + halbb_set_reg(bb, 0x49b4, MASKDWORD, tmp_val2); + halbb_set_reg(bb, 0x4a04, MASKDWORD, tmp_val2); + halbb_set_reg(bb, 0x49b8, MASKDWORD, tmp_val3); + halbb_set_reg(bb, 0x4a08, MASKDWORD, tmp_val3); +} + +void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx) +{ + s32 normal_efuse = 0; + s32 tmp = 0; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] rx_gain_offset = %d\n", + rx_gain_offset); + + rx_gain_offset *= (-1); + + // === [Set normal efuse] === // + // r_1_rpl_bias_comp + tmp = (rx_gain_offset << 4) + bb->bb_efuse_i.efuse_ofst; + halbb_set_reg_cmn(bb, 0x49B0, 0xff, (tmp & 0xff), phy_idx); + // r_tb_rssi_bias_comp + tmp = (rx_gain_offset << 4) + bb->bb_efuse_i.efuse_ofst_tb; + halbb_set_reg_cmn(bb, 0x4A00, 0xff, (bb->bb_efuse_i.efuse_ofst_tb & 0xff), phy_idx); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x49B0[7:0] = 0x%x\n", + halbb_get_reg(bb, 0x49B0, 0xff)); + BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x4A00[7:0] = 0x%x\n", + halbb_get_reg(bb, 0x4A00, 0xff)); + +} + +void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx) +{ + s32 tmp = 0; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + rx_gain_offset *= (-1); + tmp = (rx_gain_offset << 3) + (bb->bb_efuse_i.efuse_ofst >>1); + halbb_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f)); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] gain ofst = 0x%x\n", + rx_gain_offset); + BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x23ac[6:0] = 0x%x\n", + halbb_get_reg(bb, 0x23ac, 0x7f)); +} +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.h new file mode 100644 index 0000000..1a526b8 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_8852B_API_H__ +#define __HALBB_8852B_API_H__ +#ifdef BB_8852B_SUPPORT +#ifdef HALBB_CONFIG_RUN_IN_DRV +#include "../halbb_api.h" +#endif + +/*@--------------------------[Define]-------------------------------------*/ +#define INVALID_RF_DATA 0xffffffff +#define BB_PATH_MAX_8852B 2 +#define GAIN_HIDE_EFUSE_A_2G_8852B 0x5BB +#define GAIN_HIDE_EFUSE_A_5GL_8852B 0x5BA +#define GAIN_HIDE_EFUSE_A_5GM_8852B 0x5B9 +#define GAIN_HIDE_EFUSE_A_5GH_8852B 0x5B8 +#define GAIN_HIDE_EFUSE_B_2G_8852B 0x590 +#define GAIN_HIDE_EFUSE_B_5GL_8852B 0x58F +#define GAIN_HIDE_EFUSE_B_5GM_8852B 0x58E +#define GAIN_HIDE_EFUSE_B_5GH_8852B 0x58D + +/*@--------------------------[Enum]------------------------------------------*/ +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb, + s16 pw_ofst, enum phl_phy_idx phy_idx); +void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx, + enum phl_phy_idx phy_idx); +void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx, + enum phl_phy_idx phy_idx); +bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width bw, enum band_type band, + enum phl_phy_idx phy_idx); + +bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path); + +bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path); + +#ifdef HALBB_CONFIG_RUN_IN_DRV + +void halbb_gpio_ctrl_dump_8852b(struct bb_info *bb); + +void halbb_gpio_rfm_8852b(struct bb_info *bb, enum bb_path path, + enum bb_rfe_src_sel src, bool dis_tx_gnt_wl, + bool active_tx_opt, bool act_bt_en, u8 rfm_output_val); + +void halbb_gpio_trsw_table_8852b(struct bb_info *bb, enum bb_path path, + bool path_en, bool trsw_tx, + bool trsw_rx, bool trsw, bool trsw_b); + +void halbb_gpio_setting_8852b(struct bb_info *bb, u8 gpio_idx, + enum bb_path path, bool inv, + enum bb_rfe_src_sel src); + +void halbb_gpio_setting_all_8852b(struct bb_info *bb, u8 rfe_idx); + +void halbb_gpio_setting_init_8852b(struct bb_info *bb); + +void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_dfs_en_8852b(struct bb_info *bb, bool en); + +void halbb_adc_en_8852b(struct bb_info *bb, bool en); + +void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path); + +void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx); + +u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask); + +u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask); + +u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr, + u32 bit_mask); + +bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data); + +bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data); + +bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr, + u32 bit_mask, u32 data); + +bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx); + +bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, + enum phl_phy_idx phy_idx); + +void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en, + enum phl_phy_idx phy_idx); + +void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path, + u8 tx_nss, enum rf_path rx_path, u8 rx_nss); + +void halbb_tssi_bb_reset_8852b(struct bb_info *bb); + +u8 halbb_sco_mapping_8852b(struct bb_info *bb, u8 central_ch); + +bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch); + +bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw, + enum rf_path path); + +bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path, + bool *is_2g_ch); + +void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode); + +bool halbb_ctrl_ch2_80p80_8852b(struct bb_info *bb, u8 central_ch); + +void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx); + +void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en, + enum phl_phy_idx phy_idx); +bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm, + enum phl_phy_idx phy_idx); + +void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb); + +s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); + +s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb); + +bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx, + enum rf_path tx_path); +u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path); + +s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path); + +bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx, + enum rf_path tx_path); + +u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path); + +s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path); + +void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg); + +void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en); + +bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx); + +bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color, + enum phl_phy_idx phy_idx); + +bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id, + enum phl_phy_idx phy_idx); + +void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx, + u8 rxbb_idx, enum rf_path path); +void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm, + s16 pw_dbm_cck, s8 ofst, + u8 base_cw_0db, u16 tssi_16dBm_cw, + u16 *ofdm_cw, u16 *cck_cw, + enum phl_phy_idx phy_idx); +void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len, bool dump_2_buff); +void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len); +void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable, + enum phl_phy_idx phy_idx); + +bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data); + +void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable); + +void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch); +void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx); +void halbb_get_normal_efuse_init_8852b(struct bb_info *bb); +void halbb_get_hide_efuse_init_8852b(struct bb_info *bb); +void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch); +void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx); +void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx); +#endif +#endif +#endif /* __INC_PHYDM_API_H_8852A__ */ diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api_ex.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api_ex.h new file mode 100644 index 0000000..0a883b9 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api_ex.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_8852B_API_EX_H__ +#define __HALBB_8852B_API_EX_H__ +#ifdef BB_8852B_SUPPORT + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; + +u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path); + +#endif +#endif /* __INC_PHYDM_API_H_8852A__ */ diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_cr_info_8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_cr_info_8852b.h new file mode 100644 index 0000000..31aee6a --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_cr_info_8852b.h @@ -0,0 +1,13825 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_CR_INFO_8852B_H_ +#define _HALBB_CR_INFO_8852B_H_ + +#define DIS_UPD_5MHZ_SYNC_EN_C 0x0000 +#define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1 +#define UPD_5MHZ_CNT_EN_C 0x0000 +#define UPD_5MHZ_CNT_EN_C_M 0x2 +#define CLK_640M_EN_C 0x0000 +#define CLK_640M_EN_C_M 0x4 +#define RFC_CK_PHASE_SEL_C 0x0000 +#define RFC_CK_PHASE_SEL_C_M 0x8 +#define RFC_CKEN_C 0x0000 +#define RFC_CKEN_C_M 0x10 +#define DFS_PATH1_EN_C 0x0000 +#define DFS_PATH1_EN_C_M 0x80 +#define UPD_5MHZ_PHASE_SEL_P0_C 0x0000 +#define UPD_5MHZ_PHASE_SEL_P0_C_M 0x7F00 +#define UPD_5MHZ_PHASE_SEL_P0_EN_C 0x0000 +#define UPD_5MHZ_PHASE_SEL_P0_EN_C_M 0x8000 +#define UPD_5MHZ_PHASE_SEL_P1_C 0x0000 +#define UPD_5MHZ_PHASE_SEL_P1_C_M 0x7F0000 +#define UPD_5MHZ_PHASE_SEL_P1_EN_C 0x0000 +#define UPD_5MHZ_PHASE_SEL_P1_EN_C_M 0x800000 +#define CLK_640M_P0_EN_C 0x0000 +#define CLK_640M_P0_EN_C_M 0x1000000 +#define CLK_640M_P1_EN_C 0x0000 +#define CLK_640M_P1_EN_C_M 0x2000000 +#define UPD_TOP_CNT_P0_EN_C 0x0000 +#define UPD_TOP_CNT_P0_EN_C_M 0x4000000 +#define UPD_TOP_CNT_P1_EN_C 0x0000 +#define UPD_TOP_CNT_P1_EN_C_M 0x8000000 +#define P0_SMALL_BW_EN_C 0x0000 +#define P0_SMALL_BW_EN_C_M 0x10000000 +#define P1_SMALL_BW_EN_C 0x0000 +#define P1_SMALL_BW_EN_C_M 0x20000000 +#define EN_UPD_5MHZ_INV_C 0x0000 +#define EN_UPD_5MHZ_INV_C_M 0x40000000 +#define DFS_EN_C 0x0000 +#define DFS_EN_C_M 0x80000000 +#define UPD_TD_PHASE_SEL_P0_C 0x0004 +#define UPD_TD_PHASE_SEL_P0_C_M 0x1F +#define UPD_TD_PHASE_SEL_P0_EN_C 0x0004 +#define UPD_TD_PHASE_SEL_P0_EN_C_M 0x80 +#define UPD_TD_PHASE_SEL_P1_C 0x0004 +#define UPD_TD_PHASE_SEL_P1_C_M 0x1F00 +#define UPD_TD_PHASE_SEL_P1_EN_C 0x0004 +#define UPD_TD_PHASE_SEL_P1_EN_C_M 0x8000 +#define UPD_IN_PHASE_SEL_P0_C 0x0004 +#define UPD_IN_PHASE_SEL_P0_C_M 0x1F0000 +#define UPD_IN_PHASE_SEL_P0_EN_C 0x0004 +#define UPD_IN_PHASE_SEL_P0_EN_C_M 0x800000 +#define UPD_IN_PHASE_SEL_P1_C 0x0004 +#define UPD_IN_PHASE_SEL_P1_C_M 0x1F000000 +#define UPD_IN_PHASE_SEL_P1_EN_C 0x0004 +#define UPD_IN_PHASE_SEL_P1_EN_C_M 0x80000000 +#define UPD_OUT_PHASE_SEL_P0_C 0x0008 +#define UPD_OUT_PHASE_SEL_P0_C_M 0x1F +#define UPD_OUT_PHASE_SEL_P0_EN_C 0x0008 +#define UPD_OUT_PHASE_SEL_P0_EN_C_M 0x80 +#define UPD_OUT_PHASE_SEL_P1_C 0x0008 +#define UPD_OUT_PHASE_SEL_P1_C_M 0x1F00 +#define UPD_OUT_PHASE_SEL_P1_EN_C 0x0008 +#define UPD_OUT_PHASE_SEL_P1_EN_C_M 0x8000 +#define UPD_MCU_PHASE_SEL_P0_C 0x0008 +#define UPD_MCU_PHASE_SEL_P0_C_M 0x1F0000 +#define UPD_MCU_PHASE_SEL_P0_EN_C 0x0008 +#define UPD_MCU_PHASE_SEL_P0_EN_C_M 0x800000 +#define UPD_MCU_PHASE_SEL_P1_C 0x0008 +#define UPD_MCU_PHASE_SEL_P1_C_M 0x1F000000 +#define UPD_MCU_PHASE_SEL_P1_EN_C 0x0008 +#define UPD_MCU_PHASE_SEL_P1_EN_C_M 0x80000000 +#define RSTB_WATCH_DOG_P0_EN_C 0x000C +#define RSTB_WATCH_DOG_P0_EN_C_M 0x1 +#define RSTB_WATCH_DOG_P1_EN_C 0x000C +#define RSTB_WATCH_DOG_P1_EN_C_M 0x2 +#define MAC_RST_P0_EN_C 0x000C +#define MAC_RST_P0_EN_C_M 0x4 +#define MAC_RST_P1_EN_C 0x000C +#define MAC_RST_P1_EN_C_M 0x8 +#define WMAC_RST_P0_EN_C 0x000C +#define WMAC_RST_P0_EN_C_M 0x10 +#define WMAC_RST_P1_EN_C 0x000C +#define WMAC_RST_P1_EN_C_M 0x20 +#define P0_PATH_EN_C 0x0010 +#define P0_PATH_EN_C_M 0xF +#define P1_PATH_EN_C 0x0010 +#define P1_PATH_EN_C_M 0xF0 +#define DBG_CKEN_C 0x0010 +#define DBG_CKEN_C_M 0x100 +#define RX_CKEN_CCK_P0_C 0x0010 +#define RX_CKEN_CCK_P0_C_M 0x200 +#define RX_CKEN_CCK_P1_C 0x0010 +#define RX_CKEN_CCK_P1_C_M 0x400 +#define TX_CKEN_CCK_P0_C 0x0010 +#define TX_CKEN_CCK_P0_C_M 0x800 +#define TX_CKEN_CCK_P1_C 0x0010 +#define TX_CKEN_CCK_P1_C_M 0x1000 +#define RX_TD_CKEN_OFDM_P0_C 0x0010 +#define RX_TD_CKEN_OFDM_P0_C_M 0x2000 +#define RX_TD_CKEN_OFDM_P1_C 0x0010 +#define RX_TD_CKEN_OFDM_P1_C_M 0x4000 +#define TX_TD_CKEN_OFDM_P0_C 0x0010 +#define TX_TD_CKEN_OFDM_P0_C_M 0x8000 +#define TX_TD_CKEN_OFDM_P1_C 0x0010 +#define TX_TD_CKEN_OFDM_P1_C_M 0x10000 +#define FORCE_GNT_WL_ON_C 0x0010 +#define FORCE_GNT_WL_ON_C_M 0x20000 +#define FORCE_GNT_WL_VAL_C 0x0010 +#define FORCE_GNT_WL_VAL_C_M 0x40000 +#define LA_CKEN_C 0x0014 +#define LA_CKEN_C_M 0x1 +#define PSD_CKEN_C 0x0014 +#define PSD_CKEN_C_M 0x2 +#define CCX_CKEN_C 0x0014 +#define CCX_CKEN_C_M 0x4 +#define IFS_CKEN_C 0x0014 +#define IFS_CKEN_C_M 0x8 +#define DFS_CKEN_C 0x0014 +#define DFS_CKEN_C_M 0x10 +#define FTM_CKEN_P0_C 0x0014 +#define FTM_CKEN_P0_C_M 0x20 +#define FTM_CKEN_P1_C 0x0014 +#define FTM_CKEN_P1_C_M 0x40 +#define TX_IN_CKEN_P0_C 0x0014 +#define TX_IN_CKEN_P0_C_M 0x80 +#define TX_IN_CKEN_P1_C 0x0014 +#define TX_IN_CKEN_P1_C_M 0x100 +#define BF_CKEN_P0_C 0x0014 +#define BF_CKEN_P0_C_M 0x200 +#define BF_CKEN_P1_C 0x0014 +#define BF_CKEN_P1_C_M 0x400 +#define SW_SI_CKEN_C 0x0014 +#define SW_SI_CKEN_C_M 0x800 +#define SW_SI_CK_PHASE_SEL_C 0x0014 +#define SW_SI_CK_PHASE_SEL_C_M 0x1000 +#define FTM_CKEN_C 0x0014 +#define FTM_CKEN_C_M 0x2000 +#define SNDCCA_S80_TIE1_C 0x0014 +#define SNDCCA_S80_TIE1_C_M 0x80000000 +#define PAGE00_18_DUMMY_C 0x0018 +#define PAGE00_18_DUMMY_C_M 0xFFFFFFFF +#define PAGE00_1C_DUMMY_C 0x001C +#define PAGE00_1C_DUMMY_C_M 0xFFFFFFFF +#define RSTN_ADC_FIFO_PATH0_C 0x0020 +#define RSTN_ADC_FIFO_PATH0_C_M 0xFFFF +#define PAGE00_20_RSV_C 0x0020 +#define PAGE00_20_RSV_C_M 0xFFFF0000 +#define RSTN_ADC_FIFO_PATH1_C 0x0024 +#define RSTN_ADC_FIFO_PATH1_C_M 0xFFFF +#define PAGE00_24_RSV_C 0x0024 +#define PAGE00_24_RSV_C_M 0xFFFF0000 +#define RSTN_ADC_FIFO_PATH2_C 0x0028 +#define RSTN_ADC_FIFO_PATH2_C_M 0xFFFF +#define PAGE00_28_RSV_C 0x0028 +#define PAGE00_28_RSV_C_M 0xFFFF0000 +#define RSTN_ADC_FIFO_PATH3_C 0x002C +#define RSTN_ADC_FIFO_PATH3_C_M 0xFFFF +#define PAGE00_2C_RSV_C 0x002C +#define PAGE00_2C_RSV_C_M 0xFFFF0000 +#define VERSION0_C 0x00F0 +#define VERSION0_C_M 0xFFFFFFFF +#define VERSION1_C 0x00F4 +#define VERSION1_C_M 0xFFFFFFFF +#define VERSION2_C 0x00F8 +#define VERSION2_C_M 0xFFFFFFFF +#define VERSION3_C 0x00FC +#define VERSION3_C_M 0xFFFFFFFF +#define TOP1_ALL_C 0x0100 +#define TOP1_ALL_C_M 0xFFFFFFFF +#define INTF_R_MAC_SEL_DMA_C 0x0200 +#define INTF_R_MAC_SEL_DMA_C_M 0x3 +#define INTF_R_PMAC_CH_INFO_ON_C 0x0200 +#define INTF_R_PMAC_CH_INFO_ON_C_M 0x10 +#define INTF_R_PMAC_CH_INFO_C 0x0200 +#define INTF_R_PMAC_CH_INFO_C_M 0x100 +#define INTF_R_INTF_RPT_SEL_P1_C 0x0200 +#define INTF_R_INTF_RPT_SEL_P1_C_M 0x1000 +#define INTF_R_CH_INFO_EN_P0_C 0x025C +#define INTF_R_CH_INFO_EN_P0_C_M 0x1 +#define INTF_R_CH_INFO_EN_P1_C 0x025C +#define INTF_R_CH_INFO_EN_P1_C_M 0x2 +#define INTF_R_CH_INFO_DATA_SRC_C 0x025C +#define INTF_R_CH_INFO_DATA_SRC_C_M 0x4 +#define INTF_R_COMPRESSION_C 0x025C +#define INTF_R_COMPRESSION_C_M 0x8 +#define INTF_R_GRP_NUM_NON_HE_C 0x025C +#define INTF_R_GRP_NUM_NON_HE_C_M 0x30 +#define INTF_R_GRP_NUM_HE_C 0x025C +#define INTF_R_GRP_NUM_HE_C_M 0xC0 +#define INTF_R_BLOCK_START_IDX_C 0x025C +#define INTF_R_BLOCK_START_IDX_C_M 0xF00 +#define INTF_R_BLOCK_END_IDX_C 0x025C +#define INTF_R_BLOCK_END_IDX_C_M 0xF000 +#define INTF_R_TEST_CH_INFO_EN_C 0x025C +#define INTF_R_TEST_CH_INFO_EN_C_M 0x10000 +#define INTF_R_TEST_SEG_LEN_C 0x025C +#define INTF_R_TEST_SEG_LEN_C_M 0x60000 +#define INTF_R_TEST_SEG_NUM_C 0x025C +#define INTF_R_TEST_SEG_NUM_C_M 0x3F80000 +#define INTF_R_TEST_VLD_BIT_C 0x025C +#define INTF_R_TEST_VLD_BIT_C_M 0x4000000 +#define INTF_R_TEST_DFS_EN_C 0x025C +#define INTF_R_TEST_DFS_EN_C_M 0x8000000 +#define INTF_R_TEST_DFS_PERIOD_C 0x025C +#define INTF_R_TEST_DFS_PERIOD_C_M 0xF0000000 +#define INTF_R_ELE_BITMAP_C 0x0260 +#define INTF_R_ELE_BITMAP_C_M 0xFFFFFFFF +#define INTF_R_TEST_DFS_START_DATA_31_0__C 0x0264 +#define INTF_R_TEST_DFS_START_DATA_31_0__C_M 0xFFFFFFFF +#define INTF_R_TEST_DFS_START_DATA_63_32__C 0x0268 +#define INTF_R_TEST_DFS_START_DATA_63_32__C_M 0xFFFFFFFF +#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C 0x026C +#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C_M 0xFFFFFFFF +#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C 0x0270 +#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C_M 0xFFFFFFFF +#define ANAPAR_PW_0_C 0x0300 +#define ANAPAR_PW_0_C_M 0xFF +#define ANAPAR_PW_1_C 0x0300 +#define ANAPAR_PW_1_C_M 0xFF00 +#define ANAPAR_PW_2_C 0x0300 +#define ANAPAR_PW_2_C_M 0xFF0000 +#define ANAPAR_PW_3_C 0x0300 +#define ANAPAR_PW_3_C_M 0xFF000000 +#define ANAPAR_PW_4_C 0x0304 +#define ANAPAR_PW_4_C_M 0xFF +#define ANAPAR_PW_5_C 0x0304 +#define ANAPAR_PW_5_C_M 0xFF00 +#define ANAPAR_PW_6_C 0x0304 +#define ANAPAR_PW_6_C_M 0xFF0000 +#define ANAPAR_PW_7_C 0x0304 +#define ANAPAR_PW_7_C_M 0xFF000000 +#define ANAPAR_PW_8_C 0x0308 +#define ANAPAR_PW_8_C_M 0xFF +#define ANAPAR_PW_9_C 0x0308 +#define ANAPAR_PW_9_C_M 0xFF00 +#define ANAPAR_PW_10_C 0x0308 +#define ANAPAR_PW_10_C_M 0xFF0000 +#define ANAPAR_PW_11_C 0x0308 +#define ANAPAR_PW_11_C_M 0xFF000000 +#define ANAPAR_PW_12_C 0x030C +#define ANAPAR_PW_12_C_M 0xFF +#define ANAPAR_PW_13_C 0x030C +#define ANAPAR_PW_13_C_M 0xFF00 +#define ANAPAR_PW_14_C 0x030C +#define ANAPAR_PW_14_C_M 0xFF0000 +#define ANAPAR_PW_15_C 0x030C +#define ANAPAR_PW_15_C_M 0xFF000000 +#define ANAPAR_0_C 0x0310 +#define ANAPAR_0_C_M 0xFFFF +#define ANAPAR_1_C 0x0310 +#define ANAPAR_1_C_M 0xFFFF0000 +#define ANAPAR_2_C 0x0314 +#define ANAPAR_2_C_M 0xFFFF +#define ANAPAR_3_C 0x0314 +#define ANAPAR_3_C_M 0xFFFF0000 +#define ANAPAR_4_C 0x0318 +#define ANAPAR_4_C_M 0xFFFF +#define ANAPAR_5_C 0x0318 +#define ANAPAR_5_C_M 0xFFFF0000 +#define ANAPAR_6_C 0x031C +#define ANAPAR_6_C_M 0xFFFF +#define ANAPAR_7_C 0x031C +#define ANAPAR_7_C_M 0xFFFF0000 +#define ANAPAR_8_C 0x0320 +#define ANAPAR_8_C_M 0xFFFF +#define ANAPAR_9_C 0x0320 +#define ANAPAR_9_C_M 0xFFFF0000 +#define ANAPAR_10_C 0x0324 +#define ANAPAR_10_C_M 0xFFFF +#define ANAPAR_11_C 0x0324 +#define ANAPAR_11_C_M 0xFFFF0000 +#define ANAPAR_12_C 0x0328 +#define ANAPAR_12_C_M 0xFFFF +#define ANAPAR_13_C 0x0328 +#define ANAPAR_13_C_M 0xFFFF0000 +#define ANAPAR_14_C 0x032C +#define ANAPAR_14_C_M 0xFFFF +#define ANAPAR_15_C 0x032C +#define ANAPAR_15_C_M 0xFFFF0000 +#define RFE_E_C 0x0334 +#define RFE_E_C_M 0xFFFFFFFF +#define RFE_O_SEL_DBG_C 0x0338 +#define RFE_O_SEL_DBG_C_M 0xFFFFFFFF +#define RFE_SEL_PATH_31_0__C 0x033C +#define RFE_SEL_PATH_31_0__C_M 0xFFFFFFFF +#define RFE_SEL_PATH_63_32__C 0x0340 +#define RFE_SEL_PATH_63_32__C_M 0xFFFFFFFF +#define RFE_SEL_DBG_MAC1_C 0x0344 +#define RFE_SEL_DBG_MAC1_C_M 0xFFFFFFFF +#define DLYSEL0_PINMUX_I_C 0x034C +#define DLYSEL0_PINMUX_I_C_M 0xFFFF +#define DLYSEL1_PINMUX_I_C 0x034C +#define DLYSEL1_PINMUX_I_C_M 0xFFFF0000 +#define DLYSEL0_PINMUX_O_C 0x0350 +#define DLYSEL0_PINMUX_O_C_M 0xFFFF +#define DLYSEL1_PINMUX_O_C 0x0350 +#define DLYSEL1_PINMUX_O_C_M 0xFFFF0000 +#define DBG_GPIO_SEL_P0_C 0x0354 +#define DBG_GPIO_SEL_P0_C_M 0xF +#define DBG_GPIO_SEL_P1_C 0x0354 +#define DBG_GPIO_SEL_P1_C_M 0xF0 +#define DBG_GPIO_MAC_SEL_C 0x0354 +#define DBG_GPIO_MAC_SEL_C_M 0xFF00 +#define TEST_PIN_OE_C 0x0354 +#define TEST_PIN_OE_C_M 0xFFFF0000 +#define PINMUX_SEL_C 0x0358 +#define PINMUX_SEL_C_M 0x1F +#define AFE_DEB_INFILTER_MSB_LSB_C 0x0358 +#define AFE_DEB_INFILTER_MSB_LSB_C_M 0x20 +#define AFE_DEB_PREFILTER_MSB_LSB_C 0x0358 +#define AFE_DEB_PREFILTER_MSB_LSB_C_M 0x40 +#define MBIST_PINMUX_SEL_C 0x0358 +#define MBIST_PINMUX_SEL_C_M 0x1F00 +#define AFE_UPD80_PHASE_C 0x0358 +#define AFE_UPD80_PHASE_C_M 0x2000 +#define AFE_DBG_SRAM_FREQ_C 0x0358 +#define AFE_DBG_SRAM_FREQ_C_M 0xC000 +#define LO_SEL_80P80_C 0x035C +#define LO_SEL_80P80_C_M 0x3 +#define LO_SEL_2X2_C 0x035C +#define LO_SEL_2X2_C_M 0xC +#define LO_SEL_1X1_C 0x035C +#define LO_SEL_1X1_C_M 0x30 +#define LO_SEL_DBCC_C 0x035C +#define LO_SEL_DBCC_C_M 0xC0 +#define LO_SEL_HWEN_C 0x035C +#define LO_SEL_HWEN_C_M 0x100 +#define LO_SEL_SW_C 0x035C +#define LO_SEL_SW_C_M 0xC00 +#define LO_SEL_CH20_INV_C 0x035C +#define LO_SEL_CH20_INV_C_M 0x1000 +#define DIS_CCK_CCA_TO_RFC_C 0x035C +#define DIS_CCK_CCA_TO_RFC_C_M 0x10000 +#define DIS_OFDM_CCA_TO_RFC_C 0x035C +#define DIS_OFDM_CCA_TO_RFC_C_M 0x20000 +#define RSTB_AFC_3WIRE_C 0x0360 +#define RSTB_AFC_3WIRE_C_M 0x1 +#define AFC_SI_WADDR_C 0x0360 +#define AFC_SI_WADDR_C_M 0x3FF0 +#define RST_AFC_SI_CONFLICT_CNT_C 0x0360 +#define RST_AFC_SI_CONFLICT_CNT_C_M 0x80000000 +#define AFC_SI_RADDR_C 0x0364 +#define AFC_SI_RADDR_C_M 0x3FF +#define AFC_SI_WDATA_C 0x0368 +#define AFC_SI_WDATA_C_M 0xFFFFFFFF +#define HW_SI_CLK_START_PHASE_C 0x036C +#define HW_SI_CLK_START_PHASE_C_M 0x1 +#define RSTB_HW_SI_CLK_C 0x036C +#define RSTB_HW_SI_CLK_C_M 0x2 +#define HW_SI_HALF_SPEED_EN_C 0x036C +#define HW_SI_HALF_SPEED_EN_C_M 0x10 +#define SW_SI_HALF_SPEED_EN_C 0x036C +#define SW_SI_HALF_SPEED_EN_C_M 0x20 +#define SW_SI_DATA_C 0x0370 +#define SW_SI_DATA_C_M 0xFFFFFFFF +#define SW_SI_BIT_MASK_C 0x0374 +#define SW_SI_BIT_MASK_C_M 0xFFFFF +#define RSTB_SW_SI_C 0x0374 +#define RSTB_SW_SI_C_M 0x100000 +#define SW_SI_CLK_START_PHASE_C 0x0374 +#define SW_SI_CLK_START_PHASE_C_M 0x200000 +#define SW_SI_DATA_E_INV_C 0x0374 +#define SW_SI_DATA_E_INV_C_M 0x400000 +#define SW_SI_ZERO_PADDING_EN_C 0x0374 +#define SW_SI_ZERO_PADDING_EN_C_M 0x800000 +#define SW_SI_ZERO_PADDING_NUM_C 0x0374 +#define SW_SI_ZERO_PADDING_NUM_C_M 0x3F000000 +#define RST_SW_SI_CONFLICT_CNT_C 0x0374 +#define RST_SW_SI_CONFLICT_CNT_C_M 0x80000000 +#define SW_SI_READ_ADDR_C 0x0378 +#define SW_SI_READ_ADDR_C_M 0x7FF +#define SW_SI_WAIT_TIMING_C 0x037C +#define SW_SI_WAIT_TIMING_C_M 0xF +#define SW_SI_READ_EDGE_OPT_C 0x037C +#define SW_SI_READ_EDGE_OPT_C_M 0x30 +#define SW_SI_DIS_W_TRIG_C 0x037C +#define SW_SI_DIS_W_TRIG_C_M 0x1000 +#define SW_SI_DIS_R_TRIG_C 0x037C +#define SW_SI_DIS_R_TRIG_C_M 0x2000 +#define HWSI_KEEPER_RSTB_C 0x0380 +#define HWSI_KEEPER_RSTB_C_M 0x1 +#define SWSI_KEEPER_RSTB_C 0x0380 +#define SWSI_KEEPER_RSTB_C_M 0x2 +#define HWSI_KEEPER_SEL_PATH_C 0x0380 +#define HWSI_KEEPER_SEL_PATH_C_M 0x30 +#define CCA_MASK_EN_C 0x0600 +#define CCA_MASK_EN_C_M 0xFFFFFFFF +#define TIME_CCA_MASK_RX_I_C 0x0604 +#define TIME_CCA_MASK_RX_I_C_M 0x3F +#define TIME_CCA_MASK_BRK_I_C 0x0604 +#define TIME_CCA_MASK_BRK_I_C_M 0x3F00 +#define TIME_CCA_MASK_BRK_CCK_I_C 0x0604 +#define TIME_CCA_MASK_BRK_CCK_I_C_M 0x3F0000 +#define TIME_CCA_MASK_RIFS_I_C 0x0604 +#define TIME_CCA_MASK_RIFS_I_C_M 0x3F000000 +#define TIME_CCA_MASK_HT_I_C 0x0608 +#define TIME_CCA_MASK_HT_I_C_M 0x3F +#define TIME_CCA_MASK_T2R_I_C 0x0608 +#define TIME_CCA_MASK_T2R_I_C_M 0x3F00 +#define TIME_CCA_MASK_T2R_TB_I_C 0x0608 +#define TIME_CCA_MASK_T2R_TB_I_C_M 0x3F0000 +#define TIME_CCA_MASK_T2R_TXTP_I_C 0x0608 +#define TIME_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000 +#define TIME_CCA_MASK_RX_NDP_I_C 0x060C +#define TIME_CCA_MASK_RX_NDP_I_C_M 0x3F +#define CCA_MASK_T2R_TXTP_I_C 0x060C +#define CCA_MASK_T2R_TXTP_I_C_M 0x3F0000 +#define CCA_MASK_T2R_EN_I_C 0x060C +#define CCA_MASK_T2R_EN_I_C_M 0x400000 +#define CCA_MASK_T2R_TB_EN_I_C 0x060C +#define CCA_MASK_T2R_TB_EN_I_C_M 0x800000 +#define CCA_MASK_T2R_MURTS_EN_I_C 0x060C +#define CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000 +#define CCA_MASK_T2R_TXTP_EN_I_C 0x060C +#define CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000 +#define CCA_MASK_BRK_EN_I_C 0x060C +#define CCA_MASK_BRK_EN_I_C_M 0x4000000 +#define CCA_MASK_BRK_CCK_EN_I_C 0x060C +#define CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000 +#define CCA_MASK_SEARCH_FAILED_EN_I_C 0x060C +#define CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000 +#define CCA_MASK_RIFS_EN_I_C 0x060C +#define CCA_MASK_RIFS_EN_I_C_M 0x20000000 +#define CCA_MASK_HT_EN_I_C 0x060C +#define CCA_MASK_HT_EN_I_C_M 0x40000000 +#define R1B_CCA_MASK_EN_C 0x0610 +#define R1B_CCA_MASK_EN_C_M 0xFFFFFFFF +#define TIME_B_CCA_MASK_RX_I_C 0x0614 +#define TIME_B_CCA_MASK_RX_I_C_M 0x3F +#define TIME_B_CCA_MASK_BRK_I_C 0x0614 +#define TIME_B_CCA_MASK_BRK_I_C_M 0x3F00 +#define TIME_B_CCA_MASK_BRK_CCK_I_C 0x0614 +#define TIME_B_CCA_MASK_BRK_CCK_I_C_M 0x3F0000 +#define TIME_B_CCA_MASK_RIFS_I_C 0x0614 +#define TIME_B_CCA_MASK_RIFS_I_C_M 0x3F000000 +#define TIME_B_CCA_MASK_HT_I_C 0x0618 +#define TIME_B_CCA_MASK_HT_I_C_M 0x3F +#define TIME_B_CCA_MASK_T2R_I_C 0x0618 +#define TIME_B_CCA_MASK_T2R_I_C_M 0x3F00 +#define TIME_B_CCA_MASK_T2R_TB_I_C 0x0618 +#define TIME_B_CCA_MASK_T2R_TB_I_C_M 0x3F0000 +#define TIME_B_CCA_MASK_T2R_TXTP_I_C 0x0618 +#define TIME_B_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000 +#define TIME_B_CCA_MASK_RX_NDP_I_C 0x061C +#define TIME_B_CCA_MASK_RX_NDP_I_C_M 0x3F +#define R1B_CCA_MASK_T2R_TXTP_I_C 0x061C +#define R1B_CCA_MASK_T2R_TXTP_I_C_M 0x3F0000 +#define R1B_CCA_MASK_T2R_EN_I_C 0x061C +#define R1B_CCA_MASK_T2R_EN_I_C_M 0x400000 +#define R1B_CCA_MASK_T2R_TB_EN_I_C 0x061C +#define R1B_CCA_MASK_T2R_TB_EN_I_C_M 0x800000 +#define R1B_CCA_MASK_T2R_MURTS_EN_I_C 0x061C +#define R1B_CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000 +#define R1B_CCA_MASK_T2R_TXTP_EN_I_C 0x061C +#define R1B_CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000 +#define R1B_CCA_MASK_BRK_EN_I_C 0x061C +#define R1B_CCA_MASK_BRK_EN_I_C_M 0x4000000 +#define R1B_CCA_MASK_BRK_CCK_EN_I_C 0x061C +#define R1B_CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000 +#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C 0x061C +#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000 +#define R1B_CCA_MASK_RIFS_EN_I_C 0x061C +#define R1B_CCA_MASK_RIFS_EN_I_C_M 0x20000000 +#define R1B_CCA_MASK_HT_EN_I_C 0x061C +#define R1B_CCA_MASK_HT_EN_I_C_M 0x40000000 +#define EN_RXHP_H2L_C 0x0620 +#define EN_RXHP_H2L_C_M 0x1 +#define EN_KEEP_AGC_FOR_RIFS_C 0x0620 +#define EN_KEEP_AGC_FOR_RIFS_C_M 0x2 +#define PWSAV_RIFS_C 0x0620 +#define PWSAV_RIFS_C_M 0x4 +#define EN_TB_FAIL_C 0x0620 +#define EN_TB_FAIL_C_M 0x8 +#define RFON_END_CCK_C 0x0620 +#define RFON_END_CCK_C_M 0xF0 +#define RFON_END_OFDM_C 0x0620 +#define RFON_END_OFDM_C_M 0x3F00 +#define RIFS_END_C 0x0620 +#define RIFS_END_C_M 0x3F0000 +#define TIME_TX_TO_RX_END_C 0x0624 +#define TIME_TX_TO_RX_END_C_M 0x3F +#define TIME_RXHP_H2L_C 0x0624 +#define TIME_RXHP_H2L_C_M 0x3F00 +#define TIME_RX_NDP_END_C 0x0624 +#define TIME_RX_NDP_END_C_M 0x3F0000 +#define TIME_RX_CCK_END_C 0x0624 +#define TIME_RX_CCK_END_C_M 0x3F000000 +#define TIME_RX_OFDM_END_C 0x0628 +#define TIME_RX_OFDM_END_C_M 0x3F +#define TIME_RX_BRK_END_C 0x0628 +#define TIME_RX_BRK_END_C_M 0x3F00 +#define TIME_RX2RX_HE_TB_END_C 0x0628 +#define TIME_RX2RX_HE_TB_END_C_M 0x3F0000 +#define TIME_HE_PE04U_I_C 0x062C +#define TIME_HE_PE04U_I_C_M 0x7FF +#define TIME_HE_PE08U_I_C 0x062C +#define TIME_HE_PE08U_I_C_M 0x7FF0000 +#define TIME_HE_PE12U_I_C 0x0630 +#define TIME_HE_PE12U_I_C_M 0x7FF +#define TIME_HE_PE16U_I_C 0x0630 +#define TIME_HE_PE16U_I_C_M 0x7FF0000 +#define RX_TD_CKEN_C 0x0634 +#define RX_TD_CKEN_C_M 0xFFFF +#define RX_T2F_CKEN_C 0x0634 +#define RX_T2F_CKEN_C_M 0xFFFF0000 +#define RX_IN_CKEN_C 0x0638 +#define RX_IN_CKEN_C_M 0x1 +#define RX_OUT_CKEN_C 0x0638 +#define RX_OUT_CKEN_C_M 0x2 +#define TX_CKEN_CCK_C 0x0638 +#define TX_CKEN_CCK_C_M 0x4 +#define TX_CKEN_OFDM_C 0x0638 +#define TX_CKEN_OFDM_C_M 0x8 +#define TX_OFDM_DLY_C 0x063C +#define TX_OFDM_DLY_C_M 0xF +#define TX_CCK_DLY_C 0x063C +#define TX_CCK_DLY_C_M 0xF0 +#define TX_OFDM_RF_DLY_160_C 0x0640 +#define TX_OFDM_RF_DLY_160_C_M 0x7F +#define TX_OFDM_RF_DLY_80_C 0x0640 +#define TX_OFDM_RF_DLY_80_C_M 0x7F00 +#define TX_OFDM_RF_DLY_40_C 0x0640 +#define TX_OFDM_RF_DLY_40_C_M 0x7F0000 +#define TX_OFDM_RF_DLY_20_C 0x0640 +#define TX_OFDM_RF_DLY_20_C_M 0x7F000000 +#define TX_OFDM_PATH_DLY_160_C 0x0644 +#define TX_OFDM_PATH_DLY_160_C_M 0x7F +#define TX_OFDM_PATH_DLY_80_C 0x0644 +#define TX_OFDM_PATH_DLY_80_C_M 0x7F00 +#define TX_OFDM_PATH_DLY_40_C 0x0644 +#define TX_OFDM_PATH_DLY_40_C_M 0x7F0000 +#define TX_OFDM_PATH_DLY_20_C 0x0644 +#define TX_OFDM_PATH_DLY_20_C_M 0x7F000000 +#define TX_CCK_RF_DLY_160_C 0x0648 +#define TX_CCK_RF_DLY_160_C_M 0x7F +#define TX_CCK_RF_DLY_80_C 0x0648 +#define TX_CCK_RF_DLY_80_C_M 0x7F00 +#define TX_CCK_RF_DLY_40_C 0x0648 +#define TX_CCK_RF_DLY_40_C_M 0x7F0000 +#define TX_CCK_RF_DLY_20_C 0x0648 +#define TX_CCK_RF_DLY_20_C_M 0x7F000000 +#define TX_CCK_PATH_DLY_160_C 0x064C +#define TX_CCK_PATH_DLY_160_C_M 0x7F +#define TX_CCK_PATH_DLY_80_C 0x064C +#define TX_CCK_PATH_DLY_80_C_M 0x7F00 +#define TX_CCK_PATH_DLY_40_C 0x064C +#define TX_CCK_PATH_DLY_40_C_M 0x7F0000 +#define TX_CCK_PATH_DLY_20_C 0x064C +#define TX_CCK_PATH_DLY_20_C_M 0x7F000000 +#define AFE_DATA_MASK_EN_C 0x0650 +#define AFE_DATA_MASK_EN_C_M 0xFFFFFFFF +#define AFE_DATA_MASK_TH_SEL_C 0x0654 +#define AFE_DATA_MASK_TH_SEL_C_M 0xFFFFFFFF +#define AFE_DATA_MASK_TH0_C 0x0658 +#define AFE_DATA_MASK_TH0_C_M 0xFF +#define AFE_DATA_MASK_TH1_C 0x0658 +#define AFE_DATA_MASK_TH1_C_M 0xFF00 +#define AFE_DATA_MASK_TH2_C 0x0658 +#define AFE_DATA_MASK_TH2_C_M 0xFF0000 +#define AFE_DATA_MASK_TH3_C 0x0658 +#define AFE_DATA_MASK_TH3_C_M 0xFF000000 +#define MONITOR_SEL0_C 0x065C +#define MONITOR_SEL0_C_M 0xF +#define MONITOR_SEL1_C 0x065C +#define MONITOR_SEL1_C_M 0xF0 +#define MONITOR_KEEP_C 0x065C +#define MONITOR_KEEP_C_M 0x80000000 +#define REDUCE_PEAK_PW_EN_C 0x0660 +#define REDUCE_PEAK_PW_EN_C_M 0x1 +#define STOP_CLK_C 0x0700 +#define STOP_CLK_C_M 0x1 +#define SYNC_UPD_5MHZ_C 0x0700 +#define SYNC_UPD_5MHZ_C_M 0x2 +#define SMALL_BW_C 0x0700 +#define SMALL_BW_C_M 0xC +#define ENABLE_OFDM_C 0x0700 +#define ENABLE_OFDM_C_M 0x10 +#define ENABLE_CCK_C 0x0700 +#define ENABLE_CCK_C_M 0x20 +#define ENABKE_LPS_CCK_C 0x0700 +#define ENABKE_LPS_CCK_C_M 0x40 +#define ENABLE_LPS_OFDM_C 0x0700 +#define ENABLE_LPS_OFDM_C_M 0x80 +#define R55MHZ_PHASE_C 0x0700 +#define R55MHZ_PHASE_C_M 0x7F00 +#define DIS_CLK_SOURCE_C 0x0700 +#define DIS_CLK_SOURCE_C_M 0xFF0000 +#define UPD_CLK_ADC_FORCE_ON_C 0x0700 +#define UPD_CLK_ADC_FORCE_ON_C_M 0x1000000 +#define UPD_CLK_ADC_FORCE_VAL_C 0x0700 +#define UPD_CLK_ADC_FORCE_VAL_C_M 0x6000000 +#define TD_UPD_GEN_FORCE_ON_C 0x0700 +#define TD_UPD_GEN_FORCE_ON_C_M 0x8000000 +#define RSTN_EARLY_RELEASE_C 0x0700 +#define RSTN_EARLY_RELEASE_C_M 0xF0000000 +#define RSTB_ASYNC_UPDGEN_C 0x0704 +#define RSTB_ASYNC_UPDGEN_C_M 0x1 +#define RSTB_ASYNC_ALL_C 0x0704 +#define RSTB_ASYNC_ALL_C_M 0x2 +#define RSTB_ASYNC_RXTD_C 0x0704 +#define RSTB_ASYNC_RXTD_C_M 0x4 +#define RSTB_ASYNC_TXTD_C 0x0704 +#define RSTB_ASYNC_TXTD_C_M 0x8 +#define RSTB_ASYNC_RXFD_C 0x0704 +#define RSTB_ASYNC_RXFD_C_M 0x10 +#define RSTB_ASYNC_TXFD_C 0x0704 +#define RSTB_ASYNC_TXFD_C_M 0x20 +#define RSTB_ASYNC_TX_OUT_C 0x0704 +#define RSTB_ASYNC_TX_OUT_C_M 0x40 +#define RSTB_ASYNC_RX_OUT_C 0x0704 +#define RSTB_ASYNC_RX_OUT_C_M 0x80 +#define UPD_CLK_ADC_TX_C 0x0704 +#define UPD_CLK_ADC_TX_C_M 0x300 +#define FTM_LBK_RFTXEN_CTL_EN_C 0x0704 +#define FTM_LBK_RFTXEN_CTL_EN_C_M 0x400 +#define RFTXEN_START_DLY_50NS_EN_C 0x0704 +#define RFTXEN_START_DLY_50NS_EN_C_M 0x800 +#define RST_HIT_ON_TX_EN_C 0x0704 +#define RST_HIT_ON_TX_EN_C_M 0x1000 +#define RSTN_DAC_FIFO_C 0x0704 +#define RSTN_DAC_FIFO_C_M 0xFFFF0000 +#define EN_POP_PRD_RST_ADC_FIFO_I_C 0x0708 +#define EN_POP_PRD_RST_ADC_FIFO_I_C_M 0x1 +#define RSTB_ASYNC_DAC_C 0x070C +#define RSTB_ASYNC_DAC_C_M 0xFFFFFFFF +#define PERIOD_CNT_EN_C 0x0710 +#define PERIOD_CNT_EN_C_M 0x1 +#define PERIOD_CNT_RST_C 0x0710 +#define PERIOD_CNT_RST_C_M 0x2 +#define PERIOD_UNIT_SEL_S1_C 0x0710 +#define PERIOD_UNIT_SEL_S1_C_M 0x30 +#define PERIOD_UNIT_SEL_S2_C 0x0710 +#define PERIOD_UNIT_SEL_S2_C_M 0xC0 +#define PERIOD_UNIT_SEL_S3_C 0x0710 +#define PERIOD_UNIT_SEL_S3_C_M 0x300 +#define PERIOD_UNIT_SEL_S4_C 0x0710 +#define PERIOD_UNIT_SEL_S4_C_M 0xC00 +#define PERIOD_KEEP_COND_S1_C 0x0710 +#define PERIOD_KEEP_COND_S1_C_M 0x1000 +#define PERIOD_KEEP_COND_S2_C 0x0710 +#define PERIOD_KEEP_COND_S2_C_M 0x2000 +#define PERIOD_KEEP_COND_S3_C 0x0710 +#define PERIOD_KEEP_COND_S3_C_M 0x4000 +#define PERIOD_KEEP_COND_S4_C 0x0710 +#define PERIOD_KEEP_COND_S4_C_M 0x8000 +#define RSTN_ADC_FIFO_C 0x0710 +#define RSTN_ADC_FIFO_C_M 0xFFFF0000 +#define IDX_EN_BY_MUX_ST_C 0x0714 +#define IDX_EN_BY_MUX_ST_C_M 0x3F +#define EN_BY_MUX_ST_C 0x0714 +#define EN_BY_MUX_ST_C_M 0x40 +#define FILL_EN_BY_MUX_ST_C 0x0714 +#define FILL_EN_BY_MUX_ST_C_M 0x80 +#define VAL_EN_BY_MUX_ST_C 0x0714 +#define VAL_EN_BY_MUX_ST_C_M 0xFF00 +#define APPLY_MUX_ST_C 0x0714 +#define APPLY_MUX_ST_C_M 0x10000 +#define LBK_C 0x0714 +#define LBK_C_M 0x20000 +#define LBK_MODE_C 0x0714 +#define LBK_MODE_C_M 0x40000 +#define ST_CCA_BYPASS_C 0x0714 +#define ST_CCA_BYPASS_C_M 0x80000 +#define PMAC_MOD_C 0x0714 +#define PMAC_MOD_C_M 0x100000 +#define PMAC_C 0x0714 +#define PMAC_C_M 0x200000 +#define PMAC_CORX_C 0x0714 +#define PMAC_CORX_C_M 0x400000 +#define PMAC_TX_C 0x0714 +#define PMAC_TX_C_M 0x800000 +#define PERIOD_R2R_C 0x0714 +#define PERIOD_R2R_C_M 0xFF000000 +#define DLY_EN_BY_MUX_ST_C 0x0718 +#define DLY_EN_BY_MUX_ST_C_M 0xFFFFFFFF +#define SYMB_NUM_PKT_FMT_C 0x071C +#define SYMB_NUM_PKT_FMT_C_M 0xFF +#define SAMPLE_NUM_PKT_FMT_C 0x071C +#define SAMPLE_NUM_PKT_FMT_C_M 0xFF00 +#define SYMB_NUM_CCA_C 0x071C +#define SYMB_NUM_CCA_C_M 0xFF0000 +#define SAMPLE_NUM_CCA_C 0x071C +#define SAMPLE_NUM_CCA_C_M 0xFF000000 +#define DBG_FPGA_C 0x0720 +#define DBG_FPGA_C_M 0xFFF +#define RSTB_FPGA_C 0x0720 +#define RSTB_FPGA_C_M 0x1000 +#define CBW_FPGA_C 0x0720 +#define CBW_FPGA_C_M 0xE000 +#define PRICH_FPGA_C 0x0720 +#define PRICH_FPGA_C_M 0xF0000 +#define PATH_EN_FPGA_C 0x0720 +#define PATH_EN_FPGA_C_M 0xF00000 +#define PATH_EN_1RCCA_FPGA_C 0x0720 +#define PATH_EN_1RCCA_FPGA_C_M 0xF000000 +#define INVERSE_ADC_SIGN_BIT_C 0x0720 +#define INVERSE_ADC_SIGN_BIT_C_M 0x10000000 +#define INVERSE_WB_ADC_SIGN_BIT_C 0x0720 +#define INVERSE_WB_ADC_SIGN_BIT_C_M 0x20000000 +#define CHANGE_PHASE_FPGA_ADC_C 0x0720 +#define CHANGE_PHASE_FPGA_ADC_C_M 0x40000000 +#define CHANGE_PHASE_FPGA_WB_ADC_C 0x0720 +#define CHANGE_PHASE_FPGA_WB_ADC_C_M 0x80000000 +#define RFTXEN_START_C 0x0724 +#define RFTXEN_START_C_M 0xF +#define RFTXEN_END_C 0x0724 +#define RFTXEN_END_C_M 0xF0 +#define PAPE_START_C 0x0724 +#define PAPE_START_C_M 0xF00 +#define PAPE_END_C 0x0724 +#define PAPE_END_C_M 0xF000 +#define TRSW_START_C 0x0724 +#define TRSW_START_C_M 0xF0000 +#define TRSW_END_C 0x0724 +#define TRSW_END_C_M 0xF00000 +#define LNAOFF_START_C 0x0724 +#define LNAOFF_START_C_M 0xF000000 +#define LNAOFF_END_C 0x0724 +#define LNAOFF_END_C_M 0xF0000000 +#define TRSW_TX_EXTEND_C 0x0728 +#define TRSW_TX_EXTEND_C_M 0xF +#define PMAC_GNT_BT_C 0x0728 +#define PMAC_GNT_BT_C_M 0x10 +#define GNT_BT_C 0x0728 +#define GNT_BT_C_M 0x20 +#define GNT_BT_TX_C 0x0728 +#define GNT_BT_TX_C_M 0x40 +#define GNT_WL_C 0x0728 +#define GNT_WL_C_M 0x80 +#define RFAFE_PWSAV_EN_C 0x0728 +#define RFAFE_PWSAV_EN_C_M 0x100 +#define RFAFE_PWSAV_SEL_SLEEP_C 0x0728 +#define RFAFE_PWSAV_SEL_SLEEP_C_M 0x200 +#define RSTB_STANDBY_C 0x0728 +#define RSTB_STANDBY_C_M 0x400 +#define CCAMASK_TXDIS_C 0x0728 +#define CCAMASK_TXDIS_C_M 0x800 +#define HW_ANTSW_DIS_BY_GNT_BT_C 0x0728 +#define HW_ANTSW_DIS_BY_GNT_BT_C_M 0x1000 +#define NOTRSW_BT_C 0x0728 +#define NOTRSW_BT_C_M 0x2000 +#define IGNORE_MAC_ID_C 0x0728 +#define IGNORE_MAC_ID_C_M 0x4000 +#define ANTSEL_WATCHDOG_EN_C 0x0728 +#define ANTSEL_WATCHDOG_EN_C_M 0x8000 +#define ANTSEL_WATCHDOG_OPT_C 0x0728 +#define ANTSEL_WATCHDOG_OPT_C_M 0x30000 +#define ANTSEL_WATCHDOG_TH_EXT_C 0x0728 +#define ANTSEL_WATCHDOG_TH_EXT_C_M 0xC0000 +#define ANTSEL_WATCHDOG_TH_C 0x0728 +#define ANTSEL_WATCHDOG_TH_C_M 0x300000 +#define MAC_ID_MATCH_C 0x0728 +#define MAC_ID_MATCH_C_M 0x400000 +#define LTE_RX_C 0x0728 +#define LTE_RX_C_M 0x800000 +#define CCK_HIGHPW_C 0x0728 +#define CCK_HIGHPW_C_M 0x1000000 +#define AAGC_BY_TABLE_C 0x0728 +#define AAGC_BY_TABLE_C_M 0x2000000 +#define EN_LNA_TRSW_C 0x0728 +#define EN_LNA_TRSW_C_M 0x4000000 +#define EN_ANTSEL_CCK_C 0x0728 +#define EN_ANTSEL_CCK_C_M 0x8000000 +#define IBADC_SHIFT_FPGA_C 0x0728 +#define IBADC_SHIFT_FPGA_C_M 0x30000000 +#define WBADC_SHIFT_FPGA_C 0x0728 +#define WBADC_SHIFT_FPGA_C_M 0xC0000000 +#define BT_TRXMODE_C 0x072C +#define BT_TRXMODE_C_M 0xFFFF +#define BT_TXMODE_C 0x072C +#define BT_TXMODE_C_M 0xFFFF0000 +#define RST_ALL_CNT_C 0x0730 +#define RST_ALL_CNT_C_M 0x1 +#define ENABLE_ALL_CNT_C 0x0730 +#define ENABLE_ALL_CNT_C_M 0x2 +#define PERIOD_KEEP_EN_S1_C 0x0730 +#define PERIOD_KEEP_EN_S1_C_M 0x10 +#define PERIOD_KEEP_EN_S2_C 0x0730 +#define PERIOD_KEEP_EN_S2_C_M 0x20 +#define PERIOD_KEEP_EN_S3_C 0x0730 +#define PERIOD_KEEP_EN_S3_C_M 0x40 +#define PERIOD_KEEP_EN_S4_C 0x0730 +#define PERIOD_KEEP_EN_S4_C_M 0x80 +#define BRK_SEL_FOR_CNT_C 0x0730 +#define BRK_SEL_FOR_CNT_C_M 0xFF00 +#define CNT_PWDB_TH_C 0x0730 +#define CNT_PWDB_TH_C_M 0xFFFF0000 +#define MAC_PIN_SEL_C 0x0734 +#define MAC_PIN_SEL_C_M 0xFFFF +#define CH_IDX_SEG0_C 0x0734 +#define CH_IDX_SEG0_C_M 0xFF0000 +#define CH_IDX_SEG1_C 0x0734 +#define CH_IDX_SEG1_C_M 0xFF000000 +#define PLCP_HISTOGRAM_EN_C 0x0738 +#define PLCP_HISTOGRAM_EN_C_M 0x1 +#define PLCP_HIST_TYPE_SEL_C 0x0738 +#define PLCP_HIST_TYPE_SEL_C_M 0x2 +#define STS_DIS_TRIG_BY_BRK_C 0x0738 +#define STS_DIS_TRIG_BY_BRK_C_M 0x4 +#define STS_DIS_TRIG_BY_FAIL_C 0x0738 +#define STS_DIS_TRIG_BY_FAIL_C_M 0x8 +#define STS_KEEPER_EN_C 0x0738 +#define STS_KEEPER_EN_C_M 0x10 +#define STS_KEEPER_READ_C 0x0738 +#define STS_KEEPER_READ_C_M 0x20 +#define STS_KEEPER_TRIG_COND_C 0x0738 +#define STS_KEEPER_TRIG_COND_C_M 0xC0 +#define STS_KEEPER_ADDR_C 0x0738 +#define STS_KEEPER_ADDR_C_M 0xFF00 +#define DATAON_TO_STS_FLAG_C 0x0738 +#define DATAON_TO_STS_FLAG_C_M 0xF0000 +#define STS_FLAG_GUARD_C 0x0738 +#define STS_FLAG_GUARD_C_M 0xF00000 +#define PHYSTS_INCR_DBG_EN_C 0x0738 +#define PHYSTS_INCR_DBG_EN_C_M 0x1000000 +#define STS_USER_SEL_C 0x0738 +#define STS_USER_SEL_C_M 0x6000000 +#define STS_SEG_SEL_C 0x0738 +#define STS_SEG_SEL_C_M 0x8000000 +#define STS_DBG_SEL_C 0x0738 +#define STS_DBG_SEL_C_M 0x70000000 +#define STS_TRIG_BY_FEQ_END_IN_NDP_C 0x0738 +#define STS_TRIG_BY_FEQ_END_IN_NDP_C_M 0x80000000 +#define PHY_STS_BITMAP_SEARCH_FAIL_C 0x073C +#define PHY_STS_BITMAP_SEARCH_FAIL_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_R2T_C 0x0740 +#define PHY_STS_BITMAP_R2T_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_CCA_SPOOF_C 0x0744 +#define PHY_STS_BITMAP_CCA_SPOOF_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_OFDM_BRK_C 0x0748 +#define PHY_STS_BITMAP_OFDM_BRK_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_CCK_BRK_C 0x074C +#define PHY_STS_BITMAP_CCK_BRK_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_DL_MU_SPOOF_C 0x0750 +#define PHY_STS_BITMAP_DL_MU_SPOOF_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_HE_MU_C 0x0754 +#define PHY_STS_BITMAP_HE_MU_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_VHT_MU_C 0x0758 +#define PHY_STS_BITMAP_VHT_MU_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_UL_TB_SPOOF_C 0x075C +#define PHY_STS_BITMAP_UL_TB_SPOOF_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_TRIGBASE_C 0x0760 +#define PHY_STS_BITMAP_TRIGBASE_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_CCK_C 0x0764 +#define PHY_STS_BITMAP_CCK_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_LEGACY_C 0x0768 +#define PHY_STS_BITMAP_LEGACY_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_HT_C 0x076C +#define PHY_STS_BITMAP_HT_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_VHT_C 0x0770 +#define PHY_STS_BITMAP_VHT_C_M 0xFFFFFFFF +#define PHY_STS_BITMAP_HE_C 0x0774 +#define PHY_STS_BITMAP_HE_C_M 0xFFFFFFFF +#define PW_CUT_R2T_C 0x0778 +#define PW_CUT_R2T_C_M 0xFF +#define PW_CUT_TXON_C 0x0778 +#define PW_CUT_TXON_C_M 0xFF00 +#define PW_CUT_WAIT_CCA_C 0x0778 +#define PW_CUT_WAIT_CCA_C_M 0xFF0000 +#define PW_CUT_RX_LEGACY_C 0x0778 +#define PW_CUT_RX_LEGACY_C_M 0xFF000000 +#define PW_CUT_RX_HTDATA_TIME_C 0x077C +#define PW_CUT_RX_HTDATA_TIME_C_M 0xFF +#define PW_CUT_RX_HTDATA_IORD_BCC_C 0x077C +#define PW_CUT_RX_HTDATA_IORD_BCC_C_M 0xFF00 +#define PW_CUT_RX_HTDATA_IORD_LDPC_C 0x077C +#define PW_CUT_RX_HTDATA_IORD_LDPC_C_M 0xFF0000 +#define PW_CUT_RX_HTDATA_CSI_RPT_C 0x077C +#define PW_CUT_RX_HTDATA_CSI_RPT_C_M 0xFF000000 +#define SEL_V_COLUMN_VAL_EN_C 0x0800 +#define SEL_V_COLUMN_VAL_EN_C_M 0x1 +#define SEL_V_COLUMN_VAL_C 0x0800 +#define SEL_V_COLUMN_VAL_C_M 0x3E +#define TXBF_SCAL_FCTR_C 0x0800 +#define TXBF_SCAL_FCTR_C_M 0xFFC0 +#define TXBF_SCAL_FCTR_EN_C 0x0800 +#define TXBF_SCAL_FCTR_EN_C_M 0x10000 +#define RST_BFER_EDGE_CNT_C 0x0800 +#define RST_BFER_EDGE_CNT_C_M 0x20000 +#define RST_BFEE_EDGE_CNT_C 0x0800 +#define RST_BFEE_EDGE_CNT_C_M 0x40000 +#define CSI_PARA_SEL_TO_RPT_C 0x0800 +#define CSI_PARA_SEL_TO_RPT_C_M 0x7F80000 +#define DIS_MU_GOUPING_TRIG_FB_CHK_C 0x0800 +#define DIS_MU_GOUPING_TRIG_FB_CHK_C_M 0x8000000 +#define GRPING_SEARCH_NUM_C 0x0804 +#define GRPING_SEARCH_NUM_C_M 0xFF +#define GRP_USER_EN_C 0x0804 +#define GRP_USER_EN_C_M 0x3FF00 +#define DIS_MU_GRPING_C 0x0804 +#define DIS_MU_GRPING_C_M 0x40000 +#define DIS_BF_USER_CHK_C 0x0804 +#define DIS_BF_USER_CHK_C_M 0x80000 +#define SOUND_DONE_MUX_C 0x0804 +#define SOUND_DONE_MUX_C_M 0x300000 +#define ALWAYS_LAT_GRP_GMER_C 0x0804 +#define ALWAYS_LAT_GRP_GMER_C_M 0x400000 +#define BFEE_NR_NSTS_SEL_C 0x0808 +#define BFEE_NR_NSTS_SEL_C_M 0x1 +#define CAL_FEEDBACK_CSI_EN_C 0x0808 +#define CAL_FEEDBACK_CSI_EN_C_M 0x2 +#define RST_TXBF_COMPRESSOR_C 0x0808 +#define RST_TXBF_COMPRESSOR_C_M 0x4 +#define EN_SNR_RPT_COMP_C 0x0808 +#define EN_SNR_RPT_COMP_C_M 0x8 +#define TXBF_SNR_RPT_LIMT_EN_C 0x0808 +#define TXBF_SNR_RPT_LIMT_EN_C_M 0x10 +#define EN_DEF_SNR_C 0x0808 +#define EN_DEF_SNR_C_M 0x20 +#define DIS_BFEE_GCLK_C 0x0808 +#define DIS_BFEE_GCLK_C_M 0x40 +#define DIS_MAC_P_C 0x0808 +#define DIS_MAC_P_C_M 0x80 +#define DIS_CSI_CHKSUM_C 0x0808 +#define DIS_CSI_CHKSUM_C_M 0x100 +#define DIS_BFEE_CB_LMT_C 0x0808 +#define DIS_BFEE_CB_LMT_C_M 0x200 +#define BFMX_NDP_TRIG_SEL_C 0x0808 +#define BFMX_NDP_TRIG_SEL_C_M 0x400 +#define NDP_STANDBY_MUX_C 0x0808 +#define NDP_STANDBY_MUX_C_M 0x1800 +#define CSI_RPT_RATE_SEL_C 0x0808 +#define CSI_RPT_RATE_SEL_C_M 0xE000 +#define DIS_BFER_GCLK_C 0x0808 +#define DIS_BFER_GCLK_C_M 0x10000 +#define CSI_PARA_DBG_SEL_C 0x0808 +#define CSI_PARA_DBG_SEL_C_M 0xFE0000 +#define DIS_BF_CLK_C 0x0808 +#define DIS_BF_CLK_C_M 0x1000000 +#define DEF_DSNR_C 0x080C +#define DEF_DSNR_C_M 0xFFFF +#define BF_MIMO_BUS_DBG_EN_C 0x080C +#define BF_MIMO_BUS_DBG_EN_C_M 0x7F0000 +#define BF_MIMO_BUS_DBG_SEL_C 0x080C +#define BF_MIMO_BUS_DBG_SEL_C_M 0x800000 +#define DEF_SNR0_C 0x0810 +#define DEF_SNR0_C_M 0xFF +#define DEF_SNR1_C 0x0810 +#define DEF_SNR1_C_M 0xFF00 +#define DEF_SNR2_C 0x0810 +#define DEF_SNR2_C_M 0xFF0000 +#define DEF_SNR3_C 0x0810 +#define DEF_SNR3_C_M 0xFF000000 +#define CSI_PARA_USER_EN_0_C 0x0814 +#define CSI_PARA_USER_EN_0_C_M 0xFFFFFFFF +#define CSI_PARA_USER_EN_1_C 0x0818 +#define CSI_PARA_USER_EN_1_C_M 0xFFFFFFFF +#define CSI_PARA_USER_EN_2_C 0x081C +#define CSI_PARA_USER_EN_2_C_M 0xFFFFFFFF +#define CSI_PARA_USER_EN_3_C 0x0820 +#define CSI_PARA_USER_EN_3_C_M 0xFFFFFFFF +#define CSI_PARA_PARA_EN_C 0x0824 +#define CSI_PARA_PARA_EN_C_M 0xFFFF +#define CSI_PARA_USE_EN_C 0x0824 +#define CSI_PARA_USE_EN_C_M 0xF0000 +#define CSI_PARA_READY_TIMEOUT_C 0x0824 +#define CSI_PARA_READY_TIMEOUT_C_M 0x700000 +#define CSI_PARA_END_SEL_C 0x0824 +#define CSI_PARA_END_SEL_C_M 0x3800000 +#define BFEE_CSI_DEF_MODE_C 0x0824 +#define BFEE_CSI_DEF_MODE_C_M 0xC000000 +#define CSI_PARA_IDX_0_C 0x0828 +#define CSI_PARA_IDX_0_C_M 0xFFFFFFFF +#define CSI_PARA_IDX_1_C 0x082C +#define CSI_PARA_IDX_1_C_M 0xFFFF +#define CSI_PARA_C 0x082C +#define CSI_PARA_C_M 0xFFFF0000 +#define BFEE_CSI_DEF_VAL_C 0x0830 +#define BFEE_CSI_DEF_VAL_C_M 0xFFFFFFFF +#define DIS_BFEE_RST_CRTL_C 0x0834 +#define DIS_BFEE_RST_CRTL_C_M 0xFF +#define CSI_RDRDY_TIME_OUT_SEL_C 0x0834 +#define CSI_RDRDY_TIME_OUT_SEL_C_M 0xF00 +#define INTF_R_CNT_RATE_C 0x0900 +#define INTF_R_CNT_RATE_C_M 0xF +#define INTF_R_CNT_MCS_C 0x0900 +#define INTF_R_CNT_MCS_C_M 0x7F0 +#define INTF_R_CNT_VHT_MCS_C 0x0900 +#define INTF_R_CNT_VHT_MCS_C_M 0x7800 +#define INTF_R_CNT_HE_MCS_C 0x0900 +#define INTF_R_CNT_HE_MCS_C_M 0x78000 +#define INTF_R_CNT_VHT_NSS_C 0x0900 +#define INTF_R_CNT_VHT_NSS_C_M 0x180000 +#define INTF_R_CNT_HE_NSS_C 0x0900 +#define INTF_R_CNT_HE_NSS_C_M 0x600000 +#define INTF_R_MAC_HDR_TYPE_C 0x0900 +#define INTF_R_MAC_HDR_TYPE_C_M 0x1F800000 +#define INTF_R_PKT_TYPE_C 0x0904 +#define INTF_R_PKT_TYPE_C_M 0xF +#define INTF_R_CRC32_TARGET_UID_C 0x0904 +#define INTF_R_CRC32_TARGET_UID_C_M 0xFF0 +#define INTF_R_CRC32_TARGET_UID_EN_C 0x0904 +#define INTF_R_CRC32_TARGET_UID_EN_C_M 0x1000 +#define INTF_R_RX_LBK_MODE_USER_EN_C 0x0904 +#define INTF_R_RX_LBK_MODE_USER_EN_C_M 0x2000 +#define INTF_R_RX_LBK_MODE_N_USER_C 0x0904 +#define INTF_R_RX_LBK_MODE_N_USER_C_M 0x1C000 +#define INTF_R_RX_LBK_MODE_AMPDU_EN_C 0x0904 +#define INTF_R_RX_LBK_MODE_AMPDU_EN_C_M 0x20000 +#define INTF_R_DIS_TB_BRK_PROTECT_C 0x0908 +#define INTF_R_DIS_TB_BRK_PROTECT_C_M 0x1 +#define INTF_R_DIS_TB_FIFO_CLR_C 0x0908 +#define INTF_R_DIS_TB_FIFO_CLR_C_M 0x2 +#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C 0x0908 +#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C_M 0xF0 +#define INTF_R_PMAC_TB_RSSI_C 0x0908 +#define INTF_R_PMAC_TB_RSSI_C_M 0x7F00 +#define INTF_R_TX_PMAC_EN_C 0x0980 +#define INTF_R_TX_PMAC_EN_C_M 0x1 +#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C 0x0980 +#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C_M 0x30 +#define INTF_R_PMAC_TXD_PHASE_OPT_C 0x0980 +#define INTF_R_PMAC_TXD_PHASE_OPT_C_M 0xC0 +#define INTF_R_PMAC_TX_INFO_DLY_CNT_C 0x0980 +#define INTF_R_PMAC_TX_INFO_DLY_CNT_C_M 0x700 +#define INTF_R_PMAC_TDRDY_EXT_CNT_C 0x0980 +#define INTF_R_PMAC_TDRDY_EXT_CNT_C_M 0x7000 +#define INTF_R_MAC_SEL_C 0x0980 +#define INTF_R_MAC_SEL_C_M 0xFF0000 +#define INTF_R_PMAC_TBTT_C 0x0980 +#define INTF_R_PMAC_TBTT_C_M 0x1000000 +#define INTF_R_PMAC_PMAC_MOD_C 0x0980 +#define INTF_R_PMAC_PMAC_MOD_C_M 0x2000000 +#define INTF_R_PMAC_GNT_BT_C 0x0980 +#define INTF_R_PMAC_GNT_BT_C_M 0x4000000 +#define INTF_R_PMAC_GNT_BT_TX_C 0x0980 +#define INTF_R_PMAC_GNT_BT_TX_C_M 0x8000000 +#define INTF_R_PMAC_GNT_WL_C 0x0980 +#define INTF_R_PMAC_GNT_WL_C_M 0x10000000 +#define INTF_R_PMAC_LTE_RX_C 0x0980 +#define INTF_R_PMAC_LTE_RX_C_M 0x20000000 +#define INTF_R_PMAC_RXPKT_OK_C 0x0980 +#define INTF_R_PMAC_RXPKT_OK_C_M 0x40000000 +#define INTF_R_PMAC_RXPKT_FAIL_C 0x0980 +#define INTF_R_PMAC_RXPKT_FAIL_C_M 0x80000000 +#define INTF_R_MAC_SEL_FTM_C 0x0984 +#define INTF_R_MAC_SEL_FTM_C_M 0x3 +#define INTF_R_PMAC_FTM_EN_C 0x0984 +#define INTF_R_PMAC_FTM_EN_C_M 0x10 +#define INTF_R_PMAC_FTM_RPT_TRIG_C 0x0984 +#define INTF_R_PMAC_FTM_RPT_TRIG_C_M 0x100 +#define INTF_R_MAC_SEL_RXD_C 0x0988 +#define INTF_R_MAC_SEL_RXD_C_M 0x3F +#define INTF_R_RX_PMAC_EN_C 0x0988 +#define INTF_R_RX_PMAC_EN_C_M 0x100 +#define INTF_R_PMAC_RX_INVLD_PKT_C 0x0988 +#define INTF_R_PMAC_RX_INVLD_PKT_C_M 0x200 +#define INTF_R_PMAC_RX_ID_MATCH_C 0x0988 +#define INTF_R_PMAC_RX_ID_MATCH_C_M 0x400 +#define INTF_R_PMAC_DONT_RST_MAC_C 0x0988 +#define INTF_R_PMAC_DONT_RST_MAC_C_M 0x800 +#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C 0x0988 +#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C_M 0x1000 +#define INTF_R_PMAC_RX_TB_EN_C 0x0988 +#define INTF_R_PMAC_RX_TB_EN_C_M 0x2000 +#define INTF_R_MAC_RXD_PHASE_OPT_C 0x0988 +#define INTF_R_MAC_RXD_PHASE_OPT_C_M 0xC000 +#define INTF_R_TIME_RX_AIR_END_C 0x0988 +#define INTF_R_TIME_RX_AIR_END_C_M 0x3F0000 +#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C 0x0988 +#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C_M 0x3F000000 +#define INTF_R_PMAC_RX_TB_BUS_31_0_C 0x098C +#define INTF_R_PMAC_RX_TB_BUS_31_0_C_M 0xFFFFFFFF +#define INTF_R_PMAC_RX_TB_BUS_63_32_C 0x0990 +#define INTF_R_PMAC_RX_TB_BUS_63_32_C_M 0xFFFFFFFF +#define INTF_R_MAC_SEL_BFMU_C 0x0994 +#define INTF_R_MAC_SEL_BFMU_C_M 0xFF +#define INTF_R_PMAC_CSI_DATA_PAUSE_C 0x0994 +#define INTF_R_PMAC_CSI_DATA_PAUSE_C_M 0x100 +#define INTF_R_PMAC_NDP_STANDBY_C 0x0994 +#define INTF_R_PMAC_NDP_STANDBY_C_M 0x200 +#define INTF_R_PMAC_CSI_STANDBY_C 0x0994 +#define INTF_R_PMAC_CSI_STANDBY_C_M 0x400 +#define INTF_R_PMAC_SOUND_DONE_C 0x0994 +#define INTF_R_PMAC_SOUND_DONE_C_M 0x800 +#define INTF_R_PMAC_VHT_MU_USER_IDX_C 0x0994 +#define INTF_R_PMAC_VHT_MU_USER_IDX_C_M 0x3000 +#define INTF_R_PMAC_MIMO_PARA_EN_C 0x0994 +#define INTF_R_PMAC_MIMO_PARA_EN_C_M 0x10000 +#define INTF_R_PMAC_MIMO_FIELD_31_0_C 0x0998 +#define INTF_R_PMAC_MIMO_FIELD_31_0_C_M 0xFFFFFFFF +#define INTF_R_PMAC_MIMO_FIELD_63_32_C 0x099C +#define INTF_R_PMAC_MIMO_FIELD_63_32_C_M 0xFFFFFFFF +#define INTF_R_PMAC_MIMO_FIELD_66_64_C 0x09A0 +#define INTF_R_PMAC_MIMO_FIELD_66_64_C_M 0xFFFFFFFF +#define INTF_R_MAC_SEL_TXINFO_C 0x09A4 +#define INTF_R_MAC_SEL_TXINFO_C_M 0xFFFFFFFF +#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C 0x09A8 +#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C_M 0xFF +#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C 0x09A8 +#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C_M 0xFF00 +#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C 0x09A8 +#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C_M 0xFF0000 +#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C 0x09A8 +#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C_M 0xFF000000 +#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C 0x09AC +#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C_M 0xFF +#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C 0x09AC +#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C_M 0xFF00 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C 0x09AC +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C_M 0xFF0000 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C 0x09AC +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C_M 0xFF000000 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C 0x09B0 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C_M 0xFF +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C 0x09B0 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C_M 0xFF00 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C 0x09B0 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C_M 0xFF0000 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C 0x09B0 +#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C_M 0xFF000000 +#define INTF_R_TIME_RX_AIR_END_BW005_I_C 0x09B4 +#define INTF_R_TIME_RX_AIR_END_BW005_I_C_M 0xFF +#define INTF_R_TIME_RX_AIR_END_BW010_I_C 0x09B4 +#define INTF_R_TIME_RX_AIR_END_BW010_I_C_M 0xFF00 +#define INTF_R_TIME_RX_AIR_END_BW020_I_C 0x09B4 +#define INTF_R_TIME_RX_AIR_END_BW020_I_C_M 0xFF0000 +#define INTF_R_TIME_RX_AIR_END_BW040_I_C 0x09B4 +#define INTF_R_TIME_RX_AIR_END_BW040_I_C_M 0xFF000000 +#define INTF_R_TIME_RX_AIR_END_BW080_I_C 0x09B8 +#define INTF_R_TIME_RX_AIR_END_BW080_I_C_M 0xFF +#define INTF_R_TIME_RX_AIR_END_BW160_I_C 0x09B8 +#define INTF_R_TIME_RX_AIR_END_BW160_I_C_M 0xFF00 +#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C 0x09B8 +#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C_M 0x10000 +#define INTF_R_EN_CCA_OPT_I_C 0x09B8 +#define INTF_R_EN_CCA_OPT_I_C_M 0x20000 +#define INTF_R_EN_RECCA_I_C 0x09B8 +#define INTF_R_EN_RECCA_I_C_M 0x40000 +#define INTF_R_PMAC_TRIG_TB_C 0x09BC +#define INTF_R_PMAC_TRIG_TB_C_M 0x1 +#define INTF_R_PMAC_TB_TRIG_MODE_C 0x09BC +#define INTF_R_PMAC_TB_TRIG_MODE_C_M 0x6 +#define INTF_R_MAC_INFO_RPT_SEL_C 0x09BC +#define INTF_R_MAC_INFO_RPT_SEL_C_M 0x10 +#define INTF_R_TX_EN_C 0x09C0 +#define INTF_R_TX_EN_C_M 0x1 +#define INTF_R_TX_CONTINUOUS_EN_C 0x09C4 +#define INTF_R_TX_CONTINUOUS_EN_C_M 0x1 +#define INTF_R_TX_ACK_EN_C 0x09C4 +#define INTF_R_TX_ACK_EN_C_M 0x2 +#define INTF_R_TX_N_PACKET_EN_C 0x09C4 +#define INTF_R_TX_N_PACKET_EN_C_M 0x10 +#define INTF_R_TX_N_PACKET_PERIOD_50NS_C 0x09C4 +#define INTF_R_TX_N_PACKET_PERIOD_50NS_C_M 0xFFFFFF00 +#define INTF_R_TX_N_PACKET_C 0x09C8 +#define INTF_R_TX_N_PACKET_C_M 0xFFFFFFFF +#define INTF_R_TAR_TXINFO_TXTP_EN_C 0x09CC +#define INTF_R_TAR_TXINFO_TXTP_EN_C_M 0x1 +#define INTF_R_TAR_TXINFO_TXTP_C 0x09CC +#define INTF_R_TAR_TXINFO_TXTP_C_M 0x3F0 +#define INTF_R_TX_20M_MODE_EN_C 0x09D0 +#define INTF_R_TX_20M_MODE_EN_C_M 0x1 +#define INTF_R_TXBF_DIS_C 0x09D0 +#define INTF_R_TXBF_DIS_C_M 0x10 +#define NOT_SUPPORT_STBC_NSS_LMT_C 0x0A00 +#define NOT_SUPPORT_STBC_NSS_LMT_C_M 0xF +#define NOT_SUPPORT_DCM_NSS_LMT_C 0x0A00 +#define NOT_SUPPORT_DCM_NSS_LMT_C_M 0xF0 +#define NOT_SUPPORT_NSS_LMT_C 0x0A00 +#define NOT_SUPPORT_NSS_LMT_C_M 0xF00 +#define NOT_SUPPORT_MU_BCC_NSS_LMT_C 0x0A00 +#define NOT_SUPPORT_MU_BCC_NSS_LMT_C_M 0xF000 +#define EN_LDPC_RX_IN_C 0x0A00 +#define EN_LDPC_RX_IN_C_M 0x10000 +#define HEMUR_MUMIMO_EN_C 0x0A00 +#define HEMUR_MUMIMO_EN_C_M 0x20000 +#define BYPASS_HE_ERR_BCC_UP242_C 0x0A00 +#define BYPASS_HE_ERR_BCC_UP242_C_M 0x40000 +#define BYPASS_HE_ERR_BCC_MCS_C 0x0A00 +#define BYPASS_HE_ERR_BCC_MCS_C_M 0x80000 +#define BYPASS_HE_ERR_MCS_C 0x0A00 +#define BYPASS_HE_ERR_MCS_C_M 0x100000 +#define BYPASS_HE_ERR_NSTS_TOT_C 0x0A00 +#define BYPASS_HE_ERR_NSTS_TOT_C_M 0x200000 +#define BYPASS_HE_ERR_SPATIAL_CONFIG_C 0x0A00 +#define BYPASS_HE_ERR_SPATIAL_CONFIG_C_M 0x400000 +#define BYPASS_HE_ERR_STBC_MIMO_C 0x0A00 +#define BYPASS_HE_ERR_STBC_MIMO_C_M 0x800000 +#define BYPASS_HE_ERR_DCM_MIMO_C 0x0A00 +#define BYPASS_HE_ERR_DCM_MIMO_C_M 0x1000000 +#define BYPASS_HE_ERR_STBC_DCM_C 0x0A00 +#define BYPASS_HE_ERR_STBC_DCM_C_M 0x2000000 +#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C 0x0A00 +#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C_M 0x4000000 +#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C 0x0A00 +#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C_M 0x8000000 +#define BYPASS_HE_NOT_SUPPORT_NSS_C 0x0A00 +#define BYPASS_HE_NOT_SUPPORT_NSS_C_M 0x10000000 +#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C 0x0A00 +#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C_M 0x20000000 +#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C 0x0A00 +#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C_M 0x40000000 +#define BYPASS_SMO_NDP_SEL_C 0x0A04 +#define BYPASS_SMO_NDP_SEL_C_M 0x1 +#define FORCE_LS_NDP_C 0x0A04 +#define FORCE_LS_NDP_C_M 0x2 +#define CQI_DD_OPT_C 0x0A04 +#define CQI_DD_OPT_C_M 0x3FC +#define EN_PILOT_TRACKING_ONLY_C 0x0A04 +#define EN_PILOT_TRACKING_ONLY_C_M 0x800 +#define HE_SIGB_STF_DELAY_SPACING_C 0x0A04 +#define HE_SIGB_STF_DELAY_SPACING_C_M 0xFF000 +#define TB_LTF_TRACK_CNT_START_VAL_C 0x0A04 +#define TB_LTF_TRACK_CNT_START_VAL_C_M 0x700000 +#define PILOT_DC_ALIGN_SEL_C 0x0A04 +#define PILOT_DC_ALIGN_SEL_C_M 0x800000 +#define RESERVED_C 0x0A04 +#define RESERVED_C_M 0xFF000000 +#define STS_NDP_KEEP_COND_IN_IN_C 0x0A08 +#define STS_NDP_KEEP_COND_IN_IN_C_M 0x1 +#define FTM_T_OFF_PKT_CNT_TO_BRK_C 0x0A08 +#define FTM_T_OFF_PKT_CNT_TO_BRK_C_M 0x3800 +#define CCX_EN_C 0x0C00 +#define CCX_EN_C_M 0x1 +#define CCX_TRIG_OPT_C 0x0C00 +#define CCX_TRIG_OPT_C_M 0x2 +#define MEASUREMENT_TRIG_C 0x0C00 +#define MEASUREMENT_TRIG_C_M 0x4 +#define CCX_EDCCA_OPT_C 0x0C00 +#define CCX_EDCCA_OPT_C_M 0x70 +#define CCX_TXON_OPT_C 0x0C00 +#define CCX_TXON_OPT_C_M 0x80 +#define CLM_COUNTER_UNIT_C 0x0C00 +#define CLM_COUNTER_UNIT_C_M 0xC00 +#define CLM_EN_C 0x0C00 +#define CLM_EN_C_M 0x1000 +#define CLM_CCA_OPT_C 0x0C00 +#define CLM_CCA_OPT_C_M 0xE000 +#define CLM_PERIOD_C 0x0C00 +#define CLM_PERIOD_C_M 0xFFFF0000 +#define CLM_EDCCA_PERIOD_C 0x0C04 +#define CLM_EDCCA_PERIOD_C_M 0xFFFF +#define CLM_EDCCA_COUNTER_UNIT_C 0x0C04 +#define CLM_EDCCA_COUNTER_UNIT_C_M 0x30000 +#define CLM_EDCCA_EN_C 0x0C04 +#define CLM_EDCCA_EN_C_M 0x40000 +#define CLM_FROM_DBG_SEL_C 0x0C04 +#define CLM_FROM_DBG_SEL_C_M 0x3F00000 +#define NHM_PERIOD_C 0x0C08 +#define NHM_PERIOD_C_M 0xFFFF +#define NHM_COUNTER_UNIT_C 0x0C08 +#define NHM_COUNTER_UNIT_C_M 0x30000 +#define NHM_EN_C 0x0C08 +#define NHM_EN_C_M 0x40000 +#define NHM_IGNORE_CCA_C 0x0C08 +#define NHM_IGNORE_CCA_C_M 0x80000 +#define NHM_TH0_C 0x0C08 +#define NHM_TH0_C_M 0xFF000000 +#define NHM_TH1_C 0x0C0C +#define NHM_TH1_C_M 0xFF +#define NHM_TH2_C 0x0C0C +#define NHM_TH2_C_M 0xFF00 +#define NHM_TH3_C 0x0C0C +#define NHM_TH3_C_M 0xFF0000 +#define NHM_TH4_C 0x0C0C +#define NHM_TH4_C_M 0xFF000000 +#define NHM_TH5_C 0x0C10 +#define NHM_TH5_C_M 0xFF +#define NHM_TH6_C 0x0C10 +#define NHM_TH6_C_M 0xFF00 +#define NHM_TH7_C 0x0C10 +#define NHM_TH7_C_M 0xFF0000 +#define NHM_TH8_C 0x0C10 +#define NHM_TH8_C_M 0xFF000000 +#define NHM_TH9_C 0x0C14 +#define NHM_TH9_C_M 0xFF +#define NHM_TH10_C 0x0C14 +#define NHM_TH10_C_M 0xFF00 +#define NHM_PWDB_METHOD_SEL_C 0x0C14 +#define NHM_PWDB_METHOD_SEL_C_M 0x30000 +#define NHM_PWDB_PATH_SEL_C 0x0C14 +#define NHM_PWDB_PATH_SEL_C_M 0xF00000 +#define AVG_IDLE_PW_IDX_C 0x0C14 +#define AVG_IDLE_PW_IDX_C_M 0x7000000 +#define T2F_BRK_CNT_END_C 0x0C14 +#define T2F_BRK_CNT_END_C_M 0x38000000 +#define T2F_IDLE_CNT_BRK_SWITCH_C 0x0C14 +#define T2F_IDLE_CNT_BRK_SWITCH_C_M 0x40000000 +#define T2F_HE_CDD_SKIP_EN_C 0x0C14 +#define T2F_HE_CDD_SKIP_EN_C_M 0x80000000 +#define FAHM_EN_C 0x0C18 +#define FAHM_EN_C_M 0x1 +#define FAHM_EN_OFDM_C 0x0C18 +#define FAHM_EN_OFDM_C_M 0x2 +#define FAHM_EN_CCK_C 0x0C18 +#define FAHM_EN_CCK_C_M 0x4 +#define FAHM_NUM_CANDIDATE_C 0x0C18 +#define FAHM_NUM_CANDIDATE_C_M 0x38 +#define FAHM_DEN_CANDIDATE_C 0x0C18 +#define FAHM_DEN_CANDIDATE_C_M 0x1C0 +#define FAHM_EN_TH_LMT_C 0x0C18 +#define FAHM_EN_TH_LMT_C_M 0x200 +#define FAHM_COUNTER_UNIT_C 0x0C18 +#define FAHM_COUNTER_UNIT_C_M 0xC00 +#define FAHM_TH_UP_LMT_C 0x0C18 +#define FAHM_TH_UP_LMT_C_M 0xF000 +#define FAHM_PERIOD_C 0x0C18 +#define FAHM_PERIOD_C_M 0xFFFF0000 +#define FAHM_CRC32_ERR_LEGACY_C 0x0C1C +#define FAHM_CRC32_ERR_LEGACY_C_M 0x1 +#define FAHM_AMPDU_CRC32_OPT_C 0x0C1C +#define FAHM_AMPDU_CRC32_OPT_C_M 0x2 +#define RX_TD_CKEN_OFDM_C 0x0C1C +#define RX_TD_CKEN_OFDM_C_M 0x4 +#define FAHM_PWDB_SEL_C 0x0C1C +#define FAHM_PWDB_SEL_C_M 0x70 +#define FAHM_TH0_C 0x0C1C +#define FAHM_TH0_C_M 0xFF0000 +#define FAHM_TH1_C 0x0C1C +#define FAHM_TH1_C_M 0xFF000000 +#define FAHM_TH2_C 0x0C20 +#define FAHM_TH2_C_M 0xFF +#define FAHM_TH3_C 0x0C20 +#define FAHM_TH3_C_M 0xFF00 +#define FAHM_TH4_C 0x0C20 +#define FAHM_TH4_C_M 0xFF0000 +#define FAHM_TH5_C 0x0C20 +#define FAHM_TH5_C_M 0xFF000000 +#define FAHM_TH6_C 0x0C24 +#define FAHM_TH6_C_M 0xFF +#define FAHM_TH7_C 0x0C24 +#define FAHM_TH7_C_M 0xFF00 +#define FAHM_TH8_C 0x0C24 +#define FAHM_TH8_C_M 0xFF0000 +#define FAHM_TH9_C 0x0C24 +#define FAHM_TH9_C_M 0xFF000000 +#define FAHM_TH10_C 0x0C28 +#define FAHM_TH10_C_M 0xFF +#define FAHM_DIS_COUNT_EACH_MPDU_C 0x0C28 +#define FAHM_DIS_COUNT_EACH_MPDU_C_M 0x100 +#define IFS_COLLECT_EN_C 0x0C28 +#define IFS_COLLECT_EN_C_M 0x1000 +#define IFS_COUNTER_CLR_C 0x0C28 +#define IFS_COUNTER_CLR_C_M 0x2000 +#define IFS_COUNTER_UNIT_C 0x0C28 +#define IFS_COUNTER_UNIT_C_M 0xC000 +#define IFS_COLLECT_TOTAL_TIME_C 0x0C28 +#define IFS_COLLECT_TOTAL_TIME_C_M 0xFFFF0000 +#define IFS_T1_TH_LOW_C 0x0C2C +#define IFS_T1_TH_LOW_C_M 0x7FFF +#define IFS_T1_EN_C 0x0C2C +#define IFS_T1_EN_C_M 0x8000 +#define IFS_T1_TH_HIGH_C 0x0C2C +#define IFS_T1_TH_HIGH_C_M 0xFFFF0000 +#define IFS_T2_TH_LOW_C 0x0C30 +#define IFS_T2_TH_LOW_C_M 0x7FFF +#define IFS_T2_EN_C 0x0C30 +#define IFS_T2_EN_C_M 0x8000 +#define IFS_T2_TH_HIGH_C 0x0C30 +#define IFS_T2_TH_HIGH_C_M 0xFFFF0000 +#define IFS_T3_TH_LOW_C 0x0C34 +#define IFS_T3_TH_LOW_C_M 0x7FFF +#define IFS_T3_EN_C 0x0C34 +#define IFS_T3_EN_C_M 0x8000 +#define IFS_T3_TH_HIGH_C 0x0C34 +#define IFS_T3_TH_HIGH_C_M 0xFFFF0000 +#define IFS_T4_TH_LOW_C 0x0C38 +#define IFS_T4_TH_LOW_C_M 0x7FFF +#define IFS_T4_EN_C 0x0C38 +#define IFS_T4_EN_C_M 0x8000 +#define IFS_T4_TH_HIGH_C 0x0C38 +#define IFS_T4_TH_HIGH_C_M 0xFFFF0000 +#define EN_AGC_C 0x0C3C +#define EN_AGC_C_M 0x1 +#define EN_DFIR_TMP_C 0x0C3C +#define EN_DFIR_TMP_C_M 0x2 +#define EN_ACI_DET_TMP_C 0x0C3C +#define EN_ACI_DET_TMP_C_M 0x4 +#define EN_DCCL_TMP_C 0x0C3C +#define EN_DCCL_TMP_C_M 0x8 +#define EN_NBIFLT_TMP_C 0x0C3C +#define EN_NBIFLT_TMP_C_M 0x10 +#define EN_SUBFLT_TMP_C 0x0C3C +#define EN_SUBFLT_TMP_C_M 0x20 +#define OPT_PW_C 0x0C3C +#define OPT_PW_C_M 0x40 +#define DC_EN_C 0x0C3C +#define DC_EN_C_M 0x80 +#define SMF_EN_C 0x0C3C +#define SMF_EN_C_M 0x100 +#define DIS_PD_FLAG_C 0x0C3C +#define DIS_PD_FLAG_C_M 0x200 +#define DBG_OPT_SYNC_C 0x0C3C +#define DBG_OPT_SYNC_C_M 0x400 +#define DIS_GATE_SYNC_PATH_BY_TXON_C 0x0C3C +#define DIS_GATE_SYNC_PATH_BY_TXON_C_M 0x800 +#define DIS_RST_SYNC_PATH_BY_TXON_C 0x0C3C +#define DIS_RST_SYNC_PATH_BY_TXON_C_M 0x1000 +#define EN_2ND20_C 0x0C3C +#define EN_2ND20_C_M 0x2000 +#define SYNC_RST_OPT_C 0x0C3C +#define SYNC_RST_OPT_C_M 0xC000 +#define BYPASS_BW20_INDICATE_C 0x0C3C +#define BYPASS_BW20_INDICATE_C_M 0x10000 +#define FORCE_RXSC_EN_C 0x0C3C +#define FORCE_RXSC_EN_C_M 0x20000 +#define FORCE_RXSC_C 0x0C3C +#define FORCE_RXSC_C_M 0x40000 +#define FINE_TUNE_PROCESS_DELAY_EXT_C 0x0C3C +#define FINE_TUNE_PROCESS_DELAY_EXT_C_M 0x80000 +#define FINE_TUNE_STOP_LMT_EXT_C 0x0C3C +#define FINE_TUNE_STOP_LMT_EXT_C_M 0x100000 +#define DIS_RST_CR_OFST_BY_RFGC_C 0x0C3C +#define DIS_RST_CR_OFST_BY_RFGC_C_M 0x200000 +#define LONG_CFO_EST_EN_C 0x0C3C +#define LONG_CFO_EST_EN_C_M 0x400000 +#define LONG_CFO_EST_SEL_C 0x0C3C +#define LONG_CFO_EST_SEL_C_M 0x800000 +#define RST_AGC_DCNF_BY_TRIG_C 0x0C3C +#define RST_AGC_DCNF_BY_TRIG_C_M 0x1000000 +#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C 0x0C3C +#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C_M 0x2000000 +#define SYNC_ALWAYS_ON_C 0x0C3C +#define SYNC_ALWAYS_ON_C_M 0x4000000 +#define SBFLT5M_EN_TMP_C 0x0C3C +#define SBFLT5M_EN_TMP_C_M 0x8000000 +#define SBDFT_FINE_CFO_EN_C 0x0C3C +#define SBDFT_FINE_CFO_EN_C_M 0x10000000 +#define CFO_ANT_SUM_RTL_C 0x0C3C +#define CFO_ANT_SUM_RTL_C_M 0x20000000 +#define MANUAL_COARSE_CFO_EN_C 0x0C3C +#define MANUAL_COARSE_CFO_EN_C_M 0x40000000 +#define MANUAL_FINE_CFO_EN_C 0x0C3C +#define MANUAL_FINE_CFO_EN_C_M 0x80000000 +#define CDD0_COUNT_LMT_RTL_C 0x0C40 +#define CDD0_COUNT_LMT_RTL_C_M 0x1F +#define CDD0_JUMP_SUB_TUNE_RTL_C 0x0C40 +#define CDD0_JUMP_SUB_TUNE_RTL_C_M 0x3E0 +#define CDD0_DELAY_SPREAD_SIZE_RTL_C 0x0C40 +#define CDD0_DELAY_SPREAD_SIZE_RTL_C_M 0x3C00 +#define SYNC_DATA_DELAY_DIFF_C 0x0C40 +#define SYNC_DATA_DELAY_DIFF_C_M 0x1FC000 +#define MANUAL_COARSE_CFO_C 0x0C40 +#define MANUAL_COARSE_CFO_C_M 0xFFE00000 +#define L1_L2_PROCESS_DELAY_CFO_C 0x0C44 +#define L1_L2_PROCESS_DELAY_CFO_C_M 0xF +#define SYNC_DATA_DELAY_DIFF_CFO_C 0x0C44 +#define SYNC_DATA_DELAY_DIFF_CFO_C_M 0x7F0 +#define FIX_SYNC_DGAIN_EN_C 0x0C44 +#define FIX_SYNC_DGAIN_EN_C_M 0x800 +#define OFST_SYNC_DAGC_C 0x0C44 +#define OFST_SYNC_DAGC_C_M 0xF000 +#define SYNC_DAGC_FREE_RUN_C 0x0C44 +#define SYNC_DAGC_FREE_RUN_C_M 0x10000 +#define FIX_SYNC_DGAIN_PWDB_C 0x0C44 +#define FIX_SYNC_DGAIN_PWDB_C_M 0xFE0000 +#define FIX_SYNC_DGAIN_C 0x0C44 +#define FIX_SYNC_DGAIN_C_M 0xFF000000 +#define MANUAL_FINE_CFO_C 0x0C48 +#define MANUAL_FINE_CFO_C_M 0x3FFF +#define L1_CFO_CMP_EN_RTL_C 0x0C48 +#define L1_CFO_CMP_EN_RTL_C_M 0x4000 +#define DIS_CCA_MASK_C 0x0C48 +#define DIS_CCA_MASK_C_M 0x8000 +#define FOLLOW_MAC_NDP_C 0x0C48 +#define FOLLOW_MAC_NDP_C_M 0x10000 +#define EN_LDPC_RX_C 0x0C48 +#define EN_LDPC_RX_C_M 0x20000 +#define VHTLEN_USE_LSIG_RX_BCC_C 0x0C48 +#define VHTLEN_USE_LSIG_RX_BCC_C_M 0x40000 +#define VHTLEN_USE_LSIG_RX_LDPC_C 0x0C48 +#define VHTLEN_USE_LSIG_RX_LDPC_C_M 0x80000 +#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C 0x0C48 +#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C_M 0x300000 +#define EN_SYNCDAGC_RFGCUP_C 0x0C48 +#define EN_SYNCDAGC_RFGCUP_C_M 0x400000 +#define RST_AGC_RPT_C 0x0C48 +#define RST_AGC_RPT_C_M 0x800000 +#define EN_AGC_RPT_C 0x0C48 +#define EN_AGC_RPT_C_M 0x1000000 +#define EN_FREERUN_C 0x0C48 +#define EN_FREERUN_C_M 0x2000000 +#define OPT_FREERUN_C 0x0C48 +#define OPT_FREERUN_C_M 0x4000000 +#define SIZE_PWCAL_FREERUN_C 0x0C48 +#define SIZE_PWCAL_FREERUN_C_M 0x18000000 +#define HE_TB_RTL_C 0x0C48 +#define HE_TB_RTL_C_M 0x20000000 +#define SNDCCA_GNTBT_EN_C 0x0C48 +#define SNDCCA_GNTBT_EN_C_M 0x40000000 +#define DIS_RST_BY_OFDM_ENABLE_C 0x0C48 +#define DIS_RST_BY_OFDM_ENABLE_C_M 0x80000000 +#define NCLKWAIT_LGY_C 0x0C4C +#define NCLKWAIT_LGY_C_M 0x3F +#define NCLKWAIT_HE_C 0x0C4C +#define NCLKWAIT_HE_C_M 0xFC0 +#define NCLKWAIT_ANTSW_C 0x0C4C +#define NCLKWAIT_ANTSW_C_M 0x3F000 +#define NCLKWAIT_CCK_C 0x0C4C +#define NCLKWAIT_CCK_C_M 0xFC0000 +#define NCLKWAIT_PRE_C 0x0C4C +#define NCLKWAIT_PRE_C_M 0x3F000000 +#define NCLKWAIT_MANUAL_EN_C 0x0C4C +#define NCLKWAIT_MANUAL_EN_C_M 0x40000000 +#define NCLKPW_MANUAL_EN_C 0x0C4C +#define NCLKPW_MANUAL_EN_C_M 0x80000000 +#define NCLKWAIT_TIAEXTRA_C 0x0C50 +#define NCLKWAIT_TIAEXTRA_C_M 0x3F +#define NCLKPW_MANUAL_PRE0_C 0x0C50 +#define NCLKPW_MANUAL_PRE0_C_M 0xC0 +#define NCLKPW_MANUAL_PRE1_C 0x0C50 +#define NCLKPW_MANUAL_PRE1_C_M 0x300 +#define MASK_POP_START_C 0x0C50 +#define MASK_POP_START_C_M 0x1C00 +#define MASK_POP_STOP_C 0x0C50 +#define MASK_POP_STOP_C_M 0xFE000 +#define DLY_FINETUNE_STF_C 0x0C50 +#define DLY_FINETUNE_STF_C_M 0xFF00000 +#define CG_RSSI_C 0x0C54 +#define CG_RSSI_C_M 0x1 +#define CG_SYNC_COMM_C 0x0C54 +#define CG_SYNC_COMM_C_M 0x2 +#define CG_BY_B_CCA_0_C 0x0C54 +#define CG_BY_B_CCA_0_C_M 0x4 +#define CG_BY_B_CCA_1_C 0x0C54 +#define CG_BY_B_CCA_1_C_M 0x8 +#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C 0x0C54 +#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C_M 0x10 +#define EN_PPDU_FIX_GAIN_C 0x0C54 +#define EN_PPDU_FIX_GAIN_C_M 0x20 +#define EN_CCA_PW_TH_C 0x0C54 +#define EN_CCA_PW_TH_C_M 0x40 +#define DIS_1RCCA_CCK_C 0x0C54 +#define DIS_1RCCA_CCK_C_M 0x80 +#define PATH_EN_NOT_FIND_80P80_C 0x0C54 +#define PATH_EN_NOT_FIND_80P80_C_M 0xF00 +#define DIS_CHANGE_PATH_80P80_C 0x0C54 +#define DIS_CHANGE_PATH_80P80_C_M 0x1000 +#define DIS_BRK_NOT_FIND_80P80_C 0x0C54 +#define DIS_BRK_NOT_FIND_80P80_C_M 0x2000 +#define BW80P80_C 0x0C54 +#define BW80P80_C_M 0x1C000 +#define HALT_WAIT_80P80_BY_RFGC_SEG0_C 0x0C54 +#define HALT_WAIT_80P80_BY_RFGC_SEG0_C_M 0x20000 +#define HALT_WAIT_80P80_BY_RFGC_SEG1_C 0x0C54 +#define HALT_WAIT_80P80_BY_RFGC_SEG1_C_M 0x40000 +#define DIS_1RCCA_OFDM_C 0x0C54 +#define DIS_1RCCA_OFDM_C_M 0x80000 +#define NSS_DEFINE_OPT_C 0x0C54 +#define NSS_DEFINE_OPT_C_M 0x100000 +#define BRK_RXTD_OPT_C 0x0C54 +#define BRK_RXTD_OPT_C_M 0xFE00000 +#define EN_SBDFT_C 0x0C54 +#define EN_SBDFT_C_M 0x10000000 +#define DIS_RST_BY_DIS_PD_FLAG_C 0x0C54 +#define DIS_RST_BY_DIS_PD_FLAG_C_M 0x20000000 +#define EN_RST_CHANGE_CORNER_C 0x0C54 +#define EN_RST_CHANGE_CORNER_C_M 0x40000000 +#define EN_POP_WHEN_TB_C 0x0C54 +#define EN_POP_WHEN_TB_C_M 0x80000000 +#define MASK_LSB_RXDFIR_C 0x0C58 +#define MASK_LSB_RXDFIR_C_M 0xF +#define MASK_LSB_SYNC_PATH_C 0x0C58 +#define MASK_LSB_SYNC_PATH_C_M 0xF0 +#define TB_STS_ON_C 0x0C58 +#define TB_STS_ON_C_M 0xFF00 +#define SEL_RPTREG_C 0x0C58 +#define SEL_RPTREG_C_M 0x30000 +#define PW_HIT_OPT_C 0x0C58 +#define PW_HIT_OPT_C_M 0x40000 +#define PREAGC_RPT_OPT_C 0x0C58 +#define PREAGC_RPT_OPT_C_M 0x80000 +#define PATH_EN_FIX_C 0x0C58 +#define PATH_EN_FIX_C_M 0x100000 +#define TB_SYNC_PATH_END_OPT_C 0x0C58 +#define TB_SYNC_PATH_END_OPT_C_M 0x200000 +#define EN_SYNC_WHEN_TB_FIX_MODE_C 0x0C58 +#define EN_SYNC_WHEN_TB_FIX_MODE_C_M 0x400000 +#define TB_BW_COMB_OPT_C 0x0C58 +#define TB_BW_COMB_OPT_C_M 0x800000 +#define ELNA_INIT_IDX_C 0x0C58 +#define ELNA_INIT_IDX_C_M 0x1000000 +#define DIS_CCA_SPOOF_C 0x0C58 +#define DIS_CCA_SPOOF_C_M 0x2000000 +#define FORCE_CCA_SPOOF_C 0x0C58 +#define FORCE_CCA_SPOOF_C_M 0x4000000 +#define OPT_TB_KEEP_C 0x0C58 +#define OPT_TB_KEEP_C_M 0x8000000 +#define ON_SYNC_PATH_COMM_C 0x0C58 +#define ON_SYNC_PATH_COMM_C_M 0x10000000 +#define CONTI_CCA_PW_TH_C 0x0C58 +#define CONTI_CCA_PW_TH_C_M 0x20000000 +#define OPT_LMT_CCA_PW_TH_C 0x0C58 +#define OPT_LMT_CCA_PW_TH_C_M 0xC0000000 +#define LMT_PPDU_FIX_GAIN_C 0x0C5C +#define LMT_PPDU_FIX_GAIN_C_M 0xFF +#define LMT_CCA_PW_TH_C 0x0C5C +#define LMT_CCA_PW_TH_C_M 0xFF00 +#define AGC_BT_SEL_PATH0_C 0x0C5C +#define AGC_BT_SEL_PATH0_C_M 0x30000 +#define AGC_BT_SEL_PATH1_C 0x0C5C +#define AGC_BT_SEL_PATH1_C_M 0xC0000 +#define AGC_BT_SEL_PATH2_C 0x0C5C +#define AGC_BT_SEL_PATH2_C_M 0x300000 +#define AGC_BT_SEL_PATH3_C 0x0C5C +#define AGC_BT_SEL_PATH3_C_M 0xC00000 +#define EN_TB_CCA_LMT_C 0x0C5C +#define EN_TB_CCA_LMT_C_M 0x1000000 +#define TB_CCA_LMT_C 0x0C5C +#define TB_CCA_LMT_C_M 0xFE000000 +#define IQK_DPK_CLK_ON_C 0x0C60 +#define IQK_DPK_CLK_ON_C_M 0x1 +#define EN_IOQ_IQK_DPK_C 0x0C60 +#define EN_IOQ_IQK_DPK_C_M 0x2 +#define IQK_OFDM_CCA_FORCE_ON_C 0x0C60 +#define IQK_OFDM_CCA_FORCE_ON_C_M 0x4 +#define IQK_CCK_CCA_FORCE_ON_C 0x0C60 +#define IQK_CCK_CCA_FORCE_ON_C_M 0x8 +#define RST_COMM_3_0__C 0x0C60 +#define RST_COMM_3_0__C_M 0xF0 +#define RST_COMM_SYNC_3_0__C 0x0C60 +#define RST_COMM_SYNC_3_0__C_M 0xF00 +#define RST_SYNC_3_0__C 0x0C60 +#define RST_SYNC_3_0__C_M 0xF000 +#define RST_COMM_5_4__C 0x0C60 +#define RST_COMM_5_4__C_M 0x30000 +#define RST_COMM_SYNC_5_4__C 0x0C60 +#define RST_COMM_SYNC_5_4__C_M 0xC0000 +#define RST_SYNC_5_4__C 0x0C60 +#define RST_SYNC_5_4__C_M 0x300000 +#define DLY_DET_OUT_C 0x0C60 +#define DLY_DET_OUT_C_M 0xC00000 +#define DLY_NORMAL_DET_OUT_C 0x0C60 +#define DLY_NORMAL_DET_OUT_C_M 0x3000000 +#define SNIFFER_MODE_C 0x0C60 +#define SNIFFER_MODE_C_M 0x3C000000 +#define OPT_LMT_PPDU_FIX_GAIN_C 0x0C60 +#define OPT_LMT_PPDU_FIX_GAIN_C_M 0xC0000000 +#define RFC_TX_CCK_IND_DIS_SEL_C 0x0C64 +#define RFC_TX_CCK_IND_DIS_SEL_C_M 0xF +#define OPT_EN_CCA_PW_TH_C 0x0C64 +#define OPT_EN_CCA_PW_TH_C_M 0x30 +#define EN_2ND20_BW_C 0x0C64 +#define EN_2ND20_BW_C_M 0x40 +#define CG_BY_OFDM_ENABLE_0_C 0x0C64 +#define CG_BY_OFDM_ENABLE_0_C_M 0x80 +#define CG_BY_OFDM_ENABLE_1_C 0x0C64 +#define CG_BY_OFDM_ENABLE_1_C_M 0x100 +#define DIS_SBDFT_C 0x0C64 +#define DIS_SBDFT_C_M 0x200 +#define FPGA_OPT_PRD_C 0x0C64 +#define FPGA_OPT_PRD_C_M 0xC00 +#define MUX_ST_POP_C 0x0C64 +#define MUX_ST_POP_C_M 0xF000 +#define MUX_ST_VLD_POP_C 0x0C64 +#define MUX_ST_VLD_POP_C_M 0xF0000 +#define EN_CFIR_MODEL_C 0x0C64 +#define EN_CFIR_MODEL_C_M 0x100000 +#define LOCK_NBIFLT_C 0x0C64 +#define LOCK_NBIFLT_C_M 0x200000 +#define MANUAL_EN_CCA_PW_TH_C 0x0C64 +#define MANUAL_EN_CCA_PW_TH_C_M 0x400000 +#define CCA_PW_TH_C 0x0C64 +#define CCA_PW_TH_C_M 0x7F800000 +#define CCA_PW_TH_PRIORITY_C 0x0C64 +#define CCA_PW_TH_PRIORITY_C_M 0x80000000 +#define MAX_CNT_POP_C 0x0C68 +#define MAX_CNT_POP_C_M 0xFF +#define CCA_MASK_CNT_POP_C 0x0C68 +#define CCA_MASK_CNT_POP_C_M 0xFF00 +#define OPT_ANT_EN_RSSI_C 0x0C68 +#define OPT_ANT_EN_RSSI_C_M 0x10000 +#define EN_NCLKWAIT_BY_IDX_C 0x0C68 +#define EN_NCLKWAIT_BY_IDX_C_M 0x20000 +#define OPT_MASK_POP_C 0x0C68 +#define OPT_MASK_POP_C_M 0x40000 +#define SYNCDLY_OFST_C 0x0C68 +#define SYNCDLY_OFST_C_M 0xF80000 +#define EN_SYNCDLY_OFST_PRIM_C 0x0C68 +#define EN_SYNCDLY_OFST_PRIM_C_M 0x1000000 +#define EN_SYNCDLY_OFST_DFE_C 0x0C68 +#define EN_SYNCDLY_OFST_DFE_C_M 0x2000000 +#define EN_SYNCDLY_OFST_DCCL_C 0x0C68 +#define EN_SYNCDLY_OFST_DCCL_C_M 0x4000000 +#define EN_SYNCDLY_OFST_SYNC_C 0x0C68 +#define EN_SYNCDLY_OFST_SYNC_C_M 0x8000000 +#define SBD_FAIL_OPT_C 0x0C68 +#define SBD_FAIL_OPT_C_M 0x10000000 +#define EN_POP_CFOE_LATE_C 0x0C68 +#define EN_POP_CFOE_LATE_C_M 0x20000000 +#define DIS_POP_CFOE_C 0x0C68 +#define DIS_POP_CFOE_C_M 0x40000000 +#define FORCE_SBD_BY_SYNC_DAGC_C 0x0C68 +#define FORCE_SBD_BY_SYNC_DAGC_C_M 0x80000000 +#define IQK_DPK_COM_RST_C 0x0C6C +#define IQK_DPK_COM_RST_C_M 0x1 +#define FAGCRDY_DLY_C 0x0C6C +#define FAGCRDY_DLY_C_M 0x1E +#define INITRST_BY_BACKINIT_C 0x0C6C +#define INITRST_BY_BACKINIT_C_M 0x20 +#define POP_MISS_BRK_EN_C 0x0C6C +#define POP_MISS_BRK_EN_C_M 0x40 +#define RPT_CNT_OPT_C 0x0C6C +#define RPT_CNT_OPT_C_M 0x380 +#define OPT_VLD_POP_C 0x0C6C +#define OPT_VLD_POP_C_M 0x400 +#define CH_MUX_ST_MANUAL_C 0x0C6C +#define CH_MUX_ST_MANUAL_C_M 0x800 +#define BT_GNT_SEG_OPT_C 0x0C6C +#define BT_GNT_SEG_OPT_C_M 0x3000 +#define EN_PRERDY_BY_MAXITER_C 0x0C6C +#define EN_PRERDY_BY_MAXITER_C_M 0x4000 +#define RXTD_RESERVED_1_C 0x0C6C +#define RXTD_RESERVED_1_C_M 0xFFFF8000 +#define IQK_COM_TX_PATH_EN_FORCE_VAL_C 0x0C70 +#define IQK_COM_TX_PATH_EN_FORCE_VAL_C_M 0xF +#define IQK_COM_TX_PATH_EN_FORCE_ON_C 0x0C70 +#define IQK_COM_TX_PATH_EN_FORCE_ON_C_M 0x10 +#define IQK_COM_RX_PATH_EN_FORCE_VAL_C 0x0C70 +#define IQK_COM_RX_PATH_EN_FORCE_VAL_C_M 0x1E0 +#define IQK_COM_RX_PATH_EN_FORCE_ON_C 0x0C70 +#define IQK_COM_RX_PATH_EN_FORCE_ON_C_M 0x200 +#define COLLISION_DET_EN_C 0x0C70 +#define COLLISION_DET_EN_C_M 0x400 +#define COLLISION_R2T_TH_C 0x0C70 +#define COLLISION_R2T_TH_C_M 0xF800 +#define COLLISION_R2T_PW_TIMING_C 0x0C70 +#define COLLISION_R2T_PW_TIMING_C_M 0x30000 +#define COLLISION_T2R_PW_TIMING_C 0x0C70 +#define COLLISION_T2R_PW_TIMING_C_M 0x40000 +#define COLLISION_PRIMARY_FLAG_C 0x0C70 +#define COLLISION_PRIMARY_FLAG_C_M 0x80000 +#define TX_COLLISION_T2R_ST_C 0x0C70 +#define TX_COLLISION_T2R_ST_C_M 0x3F00000 +#define TX_COLLISION_R2T_ST_C 0x0C70 +#define TX_COLLISION_R2T_ST_C_M 0xFC000000 +#define COLLISION_T2R_TH_MCS0_C 0x0C74 +#define COLLISION_T2R_TH_MCS0_C_M 0x1F +#define COLLISION_T2R_TH_MCS1_C 0x0C74 +#define COLLISION_T2R_TH_MCS1_C_M 0x3E0 +#define COLLISION_T2R_TH_MCS2_C 0x0C74 +#define COLLISION_T2R_TH_MCS2_C_M 0x7C00 +#define COLLISION_T2R_TH_MCS3_C 0x0C74 +#define COLLISION_T2R_TH_MCS3_C_M 0xF8000 +#define COLLISION_T2R_TH_MCS4_C 0x0C74 +#define COLLISION_T2R_TH_MCS4_C_M 0x1F00000 +#define COLLISION_T2R_TH_MCS5_C 0x0C74 +#define COLLISION_T2R_TH_MCS5_C_M 0x3E000000 +#define TX_COLLISION_OR_CCA_MASK_C 0x0C74 +#define TX_COLLISION_OR_CCA_MASK_C_M 0x80000000 +#define COLLISION_T2R_TH_MCS6_C 0x0C78 +#define COLLISION_T2R_TH_MCS6_C_M 0x1F +#define COLLISION_T2R_TH_MCS7_C 0x0C78 +#define COLLISION_T2R_TH_MCS7_C_M 0x3E0 +#define COLLISION_T2R_TH_MCS8_C 0x0C78 +#define COLLISION_T2R_TH_MCS8_C_M 0x7C00 +#define COLLISION_T2R_TH_MCS9_C 0x0C78 +#define COLLISION_T2R_TH_MCS9_C_M 0xF8000 +#define COLLISION_T2R_TH_MCS10_C 0x0C78 +#define COLLISION_T2R_TH_MCS10_C_M 0x1F00000 +#define COLLISION_T2R_TH_MCS11_C 0x0C78 +#define COLLISION_T2R_TH_MCS11_C_M 0x3E000000 +#define TXDAGC_DEF_N_RU0_3_C 0x0C78 +#define TXDAGC_DEF_N_RU0_3_C_M 0x80000000 +#define COLLISION_T2R_TH_CCK_C 0x0C7C +#define COLLISION_T2R_TH_CCK_C_M 0x1F +#define TXDAGC_DBG_EN_C 0x0C7C +#define TXDAGC_DBG_EN_C_M 0x20 +#define DPD_OFF_BY_TXPW_TH_C 0x0C7C +#define DPD_OFF_BY_TXPW_TH_C_M 0x7FC0 +#define DPD_OFF_BY_TXPW_OV_C 0x0C7C +#define DPD_OFF_BY_TXPW_OV_C_M 0x8000 +#define DPD_OFF_BY_TXPW_BELOW_C 0x0C7C +#define DPD_OFF_BY_TXPW_BELOW_C_M 0x10000 +#define T2F_ST_HANG_PROTECT_C 0x0C7C +#define T2F_ST_HANG_PROTECT_C_M 0x100000 +#define TXRFC_RSTB_C 0x0C7C +#define TXRFC_RSTB_C_M 0x200000 +#define DIS_TXRFC_IOWE_C 0x0C7C +#define DIS_TXRFC_IOWE_C_M 0x400000 +#define DIS_TXRFC_IOQ_C 0x0C7C +#define DIS_TXRFC_IOQ_C_M 0x800000 +#define T2F_BRK_PDHIT_AT_SAME_TIME_C 0x0C7C +#define T2F_BRK_PDHIT_AT_SAME_TIME_C_M 0x1000000 +#define T2F_NEG_GI2OFST_CNT_TH_C 0x0C7C +#define T2F_NEG_GI2OFST_CNT_TH_C_M 0xFE000000 +#define BRK_R_HT_BW020_1SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW020_1SS_BOUND_C_M 0xF +#define BRK_R_HT_BW020_2SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW020_2SS_BOUND_C_M 0xF0 +#define BRK_R_HT_BW020_3SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW020_3SS_BOUND_C_M 0xF00 +#define BRK_R_HT_BW020_4SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW020_4SS_BOUND_C_M 0xF000 +#define BRK_R_HT_BW040_1SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW040_1SS_BOUND_C_M 0xF0000 +#define BRK_R_HT_BW040_2SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW040_2SS_BOUND_C_M 0xF00000 +#define BRK_R_HT_BW040_3SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW040_3SS_BOUND_C_M 0xF000000 +#define BRK_R_HT_BW040_4SS_BOUND_C 0x0D00 +#define BRK_R_HT_BW040_4SS_BOUND_C_M 0xF0000000 +#define BRK_R_VHT_BW020_1SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW020_1SS_BOUND_C_M 0xF +#define BRK_R_VHT_BW020_2SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW020_2SS_BOUND_C_M 0xF0 +#define BRK_R_VHT_BW020_3SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW020_3SS_BOUND_C_M 0xF00 +#define BRK_R_VHT_BW020_4SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW020_4SS_BOUND_C_M 0xF000 +#define BRK_R_VHT_BW040_1SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW040_1SS_BOUND_C_M 0xF0000 +#define BRK_R_VHT_BW040_2SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW040_2SS_BOUND_C_M 0xF00000 +#define BRK_R_VHT_BW040_3SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW040_3SS_BOUND_C_M 0xF000000 +#define BRK_R_VHT_BW040_4SS_BOUND_C 0x0D04 +#define BRK_R_VHT_BW040_4SS_BOUND_C_M 0xF0000000 +#define BRK_R_VHT_BW080_1SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW080_1SS_BOUND_C_M 0xF +#define BRK_R_VHT_BW080_2SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW080_2SS_BOUND_C_M 0xF0 +#define BRK_R_VHT_BW080_3SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW080_3SS_BOUND_C_M 0xF00 +#define BRK_R_VHT_BW080_4SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW080_4SS_BOUND_C_M 0xF000 +#define BRK_R_VHT_BW160_1SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW160_1SS_BOUND_C_M 0xF0000 +#define BRK_R_VHT_BW160_2SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW160_2SS_BOUND_C_M 0xF00000 +#define BRK_R_VHT_BW160_3SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW160_3SS_BOUND_C_M 0xF000000 +#define BRK_R_VHT_BW160_4SS_BOUND_C 0x0D08 +#define BRK_R_VHT_BW160_4SS_BOUND_C_M 0xF0000000 +#define BRK_R_CHK_NDP_LSIG_VHT_C 0x0D0C +#define BRK_R_CHK_NDP_LSIG_VHT_C_M 0x1 +#define BRK_R_CHK_NDP_LSIG_N_C 0x0D0C +#define BRK_R_CHK_NDP_LSIG_N_C_M 0x2 +#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C 0x0D0C +#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C_M 0x4 +#define BRK_R_CHK_NDP_LSIG_N_34SS_C 0x0D0C +#define BRK_R_CHK_NDP_LSIG_N_34SS_C_M 0x8 +#define BRK_R_VHT_MU_NSTS_LMT_C 0x0D0C +#define BRK_R_VHT_MU_NSTS_LMT_C_M 0x70 +#define BRK_R_NSTS_SPEC_MU_SEL_C 0x0D0C +#define BRK_R_NSTS_SPEC_MU_SEL_C_M 0x780 +#define BRK_R_L_LEN_OVER_TH_C 0x0D10 +#define BRK_R_L_LEN_OVER_TH_C_M 0xFFF +#define BRK_R_L_LEN_UNDER_TH_C 0x0D10 +#define BRK_R_L_LEN_UNDER_TH_C_M 0xF000 +#define BRK_R_HT_LEN_UNDER_TH_C 0x0D10 +#define BRK_R_HT_LEN_UNDER_TH_C_M 0xF0000 +#define BRK_R_VHT_LEN_UNDER_TH_C 0x0D10 +#define BRK_R_VHT_LEN_UNDER_TH_C_M 0xF00000 +#define BRK_R_VHT_BW_SUPPORT_C 0x0D10 +#define BRK_R_VHT_BW_SUPPORT_C_M 0x3000000 +#define BRK_R_VHT_BW_SUPPORT_FORCE_C 0x0D10 +#define BRK_R_VHT_BW_SUPPORT_FORCE_C_M 0x4000000 +#define BRK_R_RX_SUPPORT_BW_C 0x0D10 +#define BRK_R_RX_SUPPORT_BW_C_M 0x38000000 +#define BRK_R_BRK_SEL_FOR_CNT_C 0x0D14 +#define BRK_R_BRK_SEL_FOR_CNT_C_M 0xFF +#define BRK_R_HT_LEN_MAX_C 0x0D14 +#define BRK_R_HT_LEN_MAX_C_M 0xFF00 +#define BRK_R_VHT_LEN_MAX_C 0x0D14 +#define BRK_R_VHT_LEN_MAX_C_M 0x3FFF0000 +#define BRK_R_LRATE_DIS_C 0x0D18 +#define BRK_R_LRATE_DIS_C_M 0xFF +#define BRK_R_HT_MCS_LMT_C 0x0D18 +#define BRK_R_HT_MCS_LMT_C_M 0x300 +#define BRK_R_EN_HT_MCS32_C 0x0D18 +#define BRK_R_EN_HT_MCS32_C_M 0x400 +#define BRK_R_EN_LDPC_RX_C 0x0D18 +#define BRK_R_EN_LDPC_RX_C_M 0x800 +#define BRK_R_EN_HT_SHORTGI_C 0x0D18 +#define BRK_R_EN_HT_SHORTGI_C_M 0x1000 +#define BRK_R_DIS_MASK_ILL_RATE_C 0x0D18 +#define BRK_R_DIS_MASK_ILL_RATE_C_M 0x2000 +#define BRK_R_EN_VHT_SHORTGI_C 0x0D18 +#define BRK_R_EN_VHT_SHORTGI_C_M 0x8000 +#define BRK_R_EN_VHT_LEN_LMT_C 0x0D18 +#define BRK_R_EN_VHT_LEN_LMT_C_M 0x10000 +#define BRK_R_HT_NOT_SUPPORT_C 0x0D18 +#define BRK_R_HT_NOT_SUPPORT_C_M 0x20000 +#define BRK_R_VHT_NOT_SUPPORT_C 0x0D18 +#define BRK_R_VHT_NOT_SUPPORT_C_M 0x40000 +#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C 0x0D18 +#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C_M 0x180000 +#define BRK_R_VHT_NSS_LMT_C 0x0D18 +#define BRK_R_VHT_NSS_LMT_C_M 0x600000 +#define BRK_R_EN_HT_STBC_1SS_C 0x0D18 +#define BRK_R_EN_HT_STBC_1SS_C_M 0x10000000 +#define BRK_R_EN_HT_STBC_2SS_C 0x0D18 +#define BRK_R_EN_HT_STBC_2SS_C_M 0x20000000 +#define BRK_R_EN_VHT_STBC_1SS_C 0x0D18 +#define BRK_R_EN_VHT_STBC_1SS_C_M 0x40000000 +#define BRK_R_EN_VHT_STBC_2SS_C 0x0D18 +#define BRK_R_EN_VHT_STBC_2SS_C_M 0x80000000 +#define BRK_R_ILL_ST0_C 0x0D20 +#define BRK_R_ILL_ST0_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST1_C 0x0D24 +#define BRK_R_ILL_ST1_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST2_C 0x0D28 +#define BRK_R_ILL_ST2_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST3_C 0x0D2C +#define BRK_R_ILL_ST3_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST0_EN_C 0x0D30 +#define BRK_R_ILL_ST0_EN_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST1_EN_C 0x0D34 +#define BRK_R_ILL_ST1_EN_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST2_EN_C 0x0D38 +#define BRK_R_ILL_ST2_EN_C_M 0xFFFFFFFF +#define BRK_R_ILL_ST3_EN_C 0x0D3C +#define BRK_R_ILL_ST3_EN_C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_31_0__C 0x0D40 +#define BRK_R_BRK_OPT_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_63_32__C 0x0D44 +#define BRK_R_BRK_OPT_63_32__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_95_64__C 0x0D48 +#define BRK_R_BRK_OPT_95_64__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_127_96__C 0x0D4C +#define BRK_R_BRK_OPT_127_96__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_NDP_31_0__C 0x0D50 +#define BRK_R_BRK_OPT_NDP_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_NDP_63_32__C 0x0D54 +#define BRK_R_BRK_OPT_NDP_63_32__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_NDP_95_64__C 0x0D58 +#define BRK_R_BRK_OPT_NDP_95_64__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_NDP_127_96__C 0x0D5C +#define BRK_R_BRK_OPT_NDP_127_96__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT5_C 0x0D60 +#define BRK_R_BRK_OPT5_C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT5_NDP_C 0x0D64 +#define BRK_R_BRK_OPT5_NDP_C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT_MU_C 0x0D70 +#define BRK_R_BRK_OPT_MU_C_M 0xFFFFFFFF +#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C 0x0D78 +#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C_M 0x3 +#define BRK_R_T2F_PFD3_ST_LMT_IDX_C 0x0D78 +#define BRK_R_T2F_PFD3_ST_LMT_IDX_C_M 0x4 +#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C 0x0D78 +#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C_M 0x10 +#define BRK_R_EN_HT_N_ESS_C 0x0D7C +#define BRK_R_EN_HT_N_ESS_C_M 0x1 +#define BRK_R_EN_SOUND_WO_NDP_C 0x0D7C +#define BRK_R_EN_SOUND_WO_NDP_C_M 0x2 +#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C 0x0D7C +#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C_M 0x4 +#define BRK_R_WATCH_DOG_STBC_EXT_US_C 0x0D7C +#define BRK_R_WATCH_DOG_STBC_EXT_US_C_M 0x8 +#define BRK_R_NORMAL_CCA_LMT_C 0x0D7C +#define BRK_R_NORMAL_CCA_LMT_C_M 0x7F0 +#define BRK_R_EXTEND_CCA_LMT_C 0x0D7C +#define BRK_R_EXTEND_CCA_LMT_C_M 0x7F000 +#define BRK_R_SPOOF_IVLD_PKT_EN_C 0x0D7C +#define BRK_R_SPOOF_IVLD_PKT_EN_C_M 0x80000 +#define BRK_R_SPOOF_RXTD_EN_C 0x0D7C +#define BRK_R_SPOOF_RXTD_EN_C_M 0x100000 +#define BRK_R_WATCH_DOG_NDP_EXT_US_C 0x0D7C +#define BRK_R_WATCH_DOG_NDP_EXT_US_C_M 0x800000 +#define BRK_R_NDP_CCA_LMT_C 0x0D7C +#define BRK_R_NDP_CCA_LMT_C_M 0x7F000000 +#define BRK_R_HE_SU_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_SU_NOT_SUPPORT_C_M 0x1 +#define BRK_R_HE_MU_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_MU_NOT_SUPPORT_C_M 0x2 +#define BRK_R_HE_ERSU_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_ERSU_NOT_SUPPORT_C_M 0x4 +#define BRK_R_HE_TB_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_TB_NOT_SUPPORT_C_M 0x8 +#define BRK_R_HE_STBC_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_STBC_NOT_SUPPORT_C_M 0x10 +#define BRK_R_HE_DCM_NOT_SUPPORT_C 0x0D80 +#define BRK_R_HE_DCM_NOT_SUPPORT_C_M 0x20 +#define BRK_R_HE_N_USER_MAX_C 0x0D80 +#define BRK_R_HE_N_USER_MAX_C_M 0x3FC0 +#define BRK_R_HE_MAX_NSS_C 0x0D80 +#define BRK_R_HE_MAX_NSS_C_M 0x1C000 +#define BRK_R_HE_STBC_NSS_LMT_C 0x0D80 +#define BRK_R_HE_STBC_NSS_LMT_C_M 0xE0000 +#define BRK_R_HE_DCM_NSS_LMT_C 0x0D80 +#define BRK_R_HE_DCM_NSS_LMT_C_M 0x700000 +#define BRK_R_TB_MAX_NSS_C 0x0D80 +#define BRK_R_TB_MAX_NSS_C_M 0x3800000 +#define BRK_R_TB_STBC_NSS_LMT_C 0x0D80 +#define BRK_R_TB_STBC_NSS_LMT_C_M 0x1C000000 +#define BRK_R_TB_DCM_NSS_LMT_C 0x0D80 +#define BRK_R_TB_DCM_NSS_LMT_C_M 0xE0000000 +#define BRK_R_EN_HE_GI_0P8_C 0x0D84 +#define BRK_R_EN_HE_GI_0P8_C_M 0x1 +#define BRK_R_EN_HE_GI_1P6_C 0x0D84 +#define BRK_R_EN_HE_GI_1P6_C_M 0x2 +#define BRK_R_EN_HE_GI_3P2_C 0x0D84 +#define BRK_R_EN_HE_GI_3P2_C_M 0x4 +#define BRK_R_EN_HE_DOPPLER_C 0x0D84 +#define BRK_R_EN_HE_DOPPLER_C_M 0x8 +#define BRK_R_HE_MU_BCC_NSS_LMT_C 0x0D84 +#define BRK_R_HE_MU_BCC_NSS_LMT_C_M 0x70 +#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C 0x0D84 +#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C_M 0x80 +#define BRK_R_TB_MUMIMO_EN_C 0x0D84 +#define BRK_R_TB_MUMIMO_EN_C_M 0x100 +#define BRK_R_EN_HE_BEAM_CHANGE_C 0x0D84 +#define BRK_R_EN_HE_BEAM_CHANGE_C_M 0x200 +#define BRK_R_EN_HE_PREAMBLE_PUNC_C 0x0D84 +#define BRK_R_EN_HE_PREAMBLE_PUNC_C_M 0x400 +#define BRK_R_EN_HE_ZERO_USER_C 0x0D84 +#define BRK_R_EN_HE_ZERO_USER_C_M 0x800 +#define BRK_R_EN_HESU_TB_TYPE_C 0x0D84 +#define BRK_R_EN_HESU_TB_TYPE_C_M 0x1000 +#define BRK_R_CHK_20M_RU_ALLOC_EN_C 0x0D84 +#define BRK_R_CHK_20M_RU_ALLOC_EN_C_M 0x2000 +#define BRK_R_EN_NDP_NEG_CLR_COND_C 0x0D84 +#define BRK_R_EN_NDP_NEG_CLR_COND_C_M 0x4000 +#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C 0x0D84 +#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C_M 0x8000 +#define BRK_R_CHK_ST_IDX_T2F_C 0x0D88 +#define BRK_R_CHK_ST_IDX_T2F_C_M 0x3F +#define BRK_R_ST_HANG_LMT_T2F_C 0x0D88 +#define BRK_R_ST_HANG_LMT_T2F_C_M 0x7F00 +#define BRK_R_CHK_ST_IDX_RX_FEQ_C 0x0D88 +#define BRK_R_CHK_ST_IDX_RX_FEQ_C_M 0x1F0000 +#define BRK_R_ST_HANG_LMT_RX_FEQ_C 0x0D88 +#define BRK_R_ST_HANG_LMT_RX_FEQ_C_M 0x7F000000 +#define BRK_R_BRK_OPT6_HE_USER_31_0__C 0x0D90 +#define BRK_R_BRK_OPT6_HE_USER_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C 0x0D94 +#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT8_TB_USER_31_0__C 0x0D98 +#define BRK_R_BRK_OPT8_TB_USER_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C 0x0D9C +#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C 0x0DA0 +#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C 0x0DA4 +#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C 0x0DA8 +#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C 0x0DAC +#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C 0x0DC0 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C 0x0DC4 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C 0x0DC8 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C 0x0DCC +#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C 0x0DD0 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C 0x0DD4 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C 0x0DD8 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C 0x0DDC +#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C 0x0DE0 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C_M 0xFFFFFFFF +#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C 0x0DE4 +#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C_M 0xFFFFFFFF +#define PATH0_R_DAC_QINV_C 0x1000 +#define PATH0_R_DAC_QINV_C_M 0x1 +#define PATH0_R_FIFO_CLR_ENB_C 0x1000 +#define PATH0_R_FIFO_CLR_ENB_C_M 0x10 +#define PATH0_R_T2F_FREERUN_BUF_EN_C 0x1004 +#define PATH0_R_T2F_FREERUN_BUF_EN_C_M 0x1 +#define PATH0_R_T2F_L1_LATE_EN_C 0x1004 +#define PATH0_R_T2F_L1_LATE_EN_C_M 0x2 +#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x1004 +#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10 +#define PATH0_R_T2F_DCCL_FILT_EN_C 0x1004 +#define PATH0_R_T2F_DCCL_FILT_EN_C_M 0x100 +#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C 0x1004 +#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000 +#define PATH0_R_TD_CLK_GCK_EN_C 0x1008 +#define PATH0_R_TD_CLK_GCK_EN_C_M 0x1 +#define PATH0_R_1RCCA_CLK_GCK_ON_C 0x1008 +#define PATH0_R_1RCCA_CLK_GCK_ON_C_M 0x10 +#define PATH0_R_SYNC_RST_EN_TD_PATH_C 0x100C +#define PATH0_R_SYNC_RST_EN_TD_PATH_C_M 0x1 +#define PATH0_R_SYNC_RST_EN_FFT_C 0x100C +#define PATH0_R_SYNC_RST_EN_FFT_C_M 0x10 +#define PATH0_R_SYNC_RST_EN_TXBUF_C 0x100C +#define PATH0_R_SYNC_RST_EN_TXBUF_C_M 0x100 +#define PATH0_R_SYNC_RST_EN_RXBUF_C 0x100C +#define PATH0_R_SYNC_RST_EN_RXBUF_C_M 0x1000 +#define PATH0_R_SYNC_RST_EN_DCCL_C 0x100C +#define PATH0_R_SYNC_RST_EN_DCCL_C_M 0x10000 +#define PATH0_R_SYNC_RST_EN_T2F_C 0x100C +#define PATH0_R_SYNC_RST_EN_T2F_C_M 0x100000 +#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C 0x100C +#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000 +#define PATH0_R_DCCL_CFO_TH_EN_C 0x1010 +#define PATH0_R_DCCL_CFO_TH_EN_C_M 0x1 +#define PATH0_R_DCCL_52B_SYMB_TH_EN_C 0x1010 +#define PATH0_R_DCCL_52B_SYMB_TH_EN_C_M 0x10 +#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C 0x1010 +#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20 +#define PATH0_R_TX_STO_TRIG_SELECT_C 0x1014 +#define PATH0_R_TX_STO_TRIG_SELECT_C_M 0x1 +#define PATH0_R_TX_STO_FIRST_PE_SELECT_C 0x1014 +#define PATH0_R_TX_STO_FIRST_PE_SELECT_C_M 0x2 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x1018 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C 0x101C +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x101C +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10 +#define PATH0_R_STO_INT_SEL_L_C 0x101C +#define PATH0_R_STO_INT_SEL_L_C_M 0x20 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x101C +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x101C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x101C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x101C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x1020 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x1024 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x1024 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10 +#define PATH0_R_STO_INT_SEL_HT_C 0x1024 +#define PATH0_R_STO_INT_SEL_HT_C_M 0x20 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x1024 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x1024 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x1024 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x1024 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x1028 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x102C +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x102C +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10 +#define PATH0_R_STO_INT_SEL_VHT_C 0x102C +#define PATH0_R_STO_INT_SEL_VHT_C_M 0x20 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x102C +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x102C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x102C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x102C +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x1030 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x1034 +#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x1034 +#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10 +#define PATH0_R_STO_INT_SEL_HE_C 0x1034 +#define PATH0_R_STO_INT_SEL_HE_C_M 0x20 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x1034 +#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x1034 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x1034 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x1034 +#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000 +#define PATH0_R_HW_SI_READ_ADDR_C 0x1200 +#define PATH0_R_HW_SI_READ_ADDR_C_M 0xFF +#define PATH0_R_HW_SI_READ_EDGE_OPT_C 0x1200 +#define PATH0_R_HW_SI_READ_EDGE_OPT_C_M 0x300 +#define PATH0_R_HW_SI_ZERO_PADDING_EN_C 0x1200 +#define PATH0_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000 +#define PATH0_R_HW_SI_BYPASS_ST_MASK_C 0x1200 +#define PATH0_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000 +#define PATH0_R_HW_SI_DATA_E_INV_C 0x1200 +#define PATH0_R_HW_SI_DATA_E_INV_C_M 0x20000 +#define PATH0_R_HW_SI_SEL_DBG_C 0x1200 +#define PATH0_R_HW_SI_SEL_DBG_C_M 0xC0000 +#define PATH0_R_HW_SI_DBG_MODE_C 0x1200 +#define PATH0_R_HW_SI_DBG_MODE_C_M 0x100000 +#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C 0x1200 +#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000 +#define PATH0_R_HW_SI_DBG_TX_TRIG_C 0x1200 +#define PATH0_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000 +#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C 0x1200 +#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000 +#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C 0x1200 +#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000 +#define PATH0_R_HW_SI_DIS_R_TRIG_C 0x1200 +#define PATH0_R_HW_SI_DIS_R_TRIG_C_M 0x40000000 +#define PATH0_R_HW_SI_DBG_RX_CMD_0_C 0x1204 +#define PATH0_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF +#define PATH0_R_HW_SI_DBG_RX_CMD_1_C 0x1204 +#define PATH0_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000 +#define PATH0_R_HW_SI_DBG_TX_CMD_0_C 0x1208 +#define PATH0_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF +#define PATH0_R_HW_SI_DBG_TX_CMD_1_C 0x1208 +#define PATH0_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000 +#define PATH0_R_ANAPAR_ST1P5_SEL_C 0x120C +#define PATH0_R_ANAPAR_ST1P5_SEL_C_M 0xF +#define PATH0_R_ANAPAR_ST3P5_SEL_C 0x120C +#define PATH0_R_ANAPAR_ST3P5_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x120C +#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000 +#define PATH0_R_RFMODE_RSTB_EQ0_EN_C 0x1210 +#define PATH0_R_RFMODE_RSTB_EQ0_EN_C_M 0x1 +#define PATH0_R_PW_RSTB_EQ0_EN_C 0x1210 +#define PATH0_R_PW_RSTB_EQ0_EN_C_M 0x2 +#define PATH0_R_RSTB_EQ0_EN_C 0x1210 +#define PATH0_R_RSTB_EQ0_EN_C_M 0x4 +#define PATH0_R_RFMODE_RSTB_EQ0_C 0x1210 +#define PATH0_R_RFMODE_RSTB_EQ0_C_M 0xF0 +#define PATH0_R_PW_RSTB_EQ0_C 0x1210 +#define PATH0_R_PW_RSTB_EQ0_C_M 0xFF00 +#define PATH0_R_RSTB_EQ0_C 0x1210 +#define PATH0_R_RSTB_EQ0_C_M 0xFFFF0000 +#define PATH0_R_RFC_SI_SEL_0_C 0x1214 +#define PATH0_R_RFC_SI_SEL_0_C_M 0x1 +#define PATH0_R_RFC_SI_SEL_1_C 0x1214 +#define PATH0_R_RFC_SI_SEL_1_C_M 0x10 +#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x1218 +#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1 +#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x1218 +#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2 +#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C 0x1218 +#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4 +#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C 0x1218 +#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0 +#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C 0x1218 +#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00 +#define PATH0_R_HW_SI_R_TRIG_DLY_C 0x1218 +#define PATH0_R_HW_SI_R_TRIG_DLY_C_M 0xF000 +#define PATH0_R_ANAPAR_RST_SEL_C 0x12A0 +#define PATH0_R_ANAPAR_RST_SEL_C_M 0xF +#define PATH0_R_ANAPAR_RST_TX_SEL_C 0x12A0 +#define PATH0_R_ANAPAR_RST_TX_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_CTSDM_131_128__C 0x12A0 +#define PATH0_R_ANAPAR_CTSDM_131_128__C_M 0xF00 +#define PATH0_R_TXCK_FORCE_VAL_C 0x12A0 +#define PATH0_R_TXCK_FORCE_VAL_C_M 0x7000 +#define PATH0_R_TXCK_FORCE_ON_C 0x12A0 +#define PATH0_R_TXCK_FORCE_ON_C_M 0x8000 +#define PATH0_R_RXCK_FORCE_VAL_C 0x12A0 +#define PATH0_R_RXCK_FORCE_VAL_C_M 0x70000 +#define PATH0_R_RXCK_FORCE_ON_C 0x12A0 +#define PATH0_R_RXCK_FORCE_ON_C_M 0x80000 +#define PATH0_R_RXCK_RFBW0_C 0x12A0 +#define PATH0_R_RXCK_RFBW0_C_M 0x700000 +#define PATH0_R_RXCK_RFBW1_C 0x12A0 +#define PATH0_R_RXCK_RFBW1_C_M 0x3800000 +#define PATH0_R_RXCK_RFBW2_C 0x12A0 +#define PATH0_R_RXCK_RFBW2_C_M 0x1C000000 +#define PATH0_R_RXCK_RFBW3_C 0x12A0 +#define PATH0_R_RXCK_RFBW3_C_M 0xE0000000 +#define PATH0_R_RXCK_RFBW4_C 0x12A4 +#define PATH0_R_RXCK_RFBW4_C_M 0x7 +#define PATH0_R_RXCK_RFBW5_C 0x12A4 +#define PATH0_R_RXCK_RFBW5_C_M 0x38 +#define PATH0_R_RXCK_RFBW6_C 0x12A4 +#define PATH0_R_RXCK_RFBW6_C_M 0x1C0 +#define PATH0_R_TXCK_RFBW0_C 0x12A4 +#define PATH0_R_TXCK_RFBW0_C_M 0x3800 +#define PATH0_R_TXCK_RFBW1_C 0x12A4 +#define PATH0_R_TXCK_RFBW1_C_M 0x1C000 +#define PATH0_R_TXCK_RFBW2_C 0x12A4 +#define PATH0_R_TXCK_RFBW2_C_M 0xE0000 +#define PATH0_R_TXCK_RFBW3_C 0x12A4 +#define PATH0_R_TXCK_RFBW3_C_M 0x700000 +#define PATH0_R_TXCK_RFBW4_C 0x12A4 +#define PATH0_R_TXCK_RFBW4_C_M 0x3800000 +#define PATH0_R_TXCK_RFBW5_C 0x12A4 +#define PATH0_R_TXCK_RFBW5_C_M 0x1C000000 +#define PATH0_R_TXCK_RFBW6_C 0x12A4 +#define PATH0_R_TXCK_RFBW6_C_M 0xE0000000 +#define PATH0_R_EN_RXCK_TX_C 0x12A8 +#define PATH0_R_EN_RXCK_TX_C_M 0x1 +#define PATH0_R_RXCK_TX_C 0x12A8 +#define PATH0_R_RXCK_TX_C_M 0xE +#define PATH0_R_RXCK_TX_FTM_C 0x12A8 +#define PATH0_R_RXCK_TX_FTM_C_M 0x70 +#define PATH0_R_CLK_RFC_GCK_EN_C 0x12A8 +#define PATH0_R_CLK_RFC_GCK_EN_C_M 0x80 +#define PATH0_R_RF0_GEN_DBG_SEL_C 0x12A8 +#define PATH0_R_RF0_GEN_DBG_SEL_C_M 0x300 +#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x12A8 +#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800 +#define PATH0_R_RFAFE_PWSAV_EN_C 0x12A8 +#define PATH0_R_RFAFE_PWSAV_EN_C_M 0xF000 +#define PATH0_R_RFMODE_ORI_RXB_OFF_C 0x12A8 +#define PATH0_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000 +#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C 0x12A8 +#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000 +#define PATH0_R_RFMODE_FTM_RXB_OFF_C 0x12A8 +#define PATH0_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000 +#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C 0x12A8 +#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000 +#define PATH0_R_RSTB_3WIRE_C 0x12AC +#define PATH0_R_RSTB_3WIRE_C_M 0x1 +#define PATH0_R_EN_NRBW_AT_TX_C 0x12AC +#define PATH0_R_EN_NRBW_AT_TX_C_M 0x4 +#define PATH0_R_RFMODE_ORI_TX_C 0x12AC +#define PATH0_R_RFMODE_ORI_TX_C_M 0xF0 +#define PATH0_R_RFMODE_ORI_TX_TXOFF_C 0x12AC +#define PATH0_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00 +#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C 0x12AC +#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000 +#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C 0x12AC +#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000 +#define PATH0_R_RFMODE_ORI_RX_IDLE_C 0x12AC +#define PATH0_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000 +#define PATH0_R_RFMODE_FTM_TX_C 0x12AC +#define PATH0_R_RFMODE_FTM_TX_C_M 0xF000000 +#define PATH0_R_RFMODE_FTM_TX_TXOFF_C 0x12AC +#define PATH0_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000 +#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C 0x12B0 +#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF +#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C 0x12B0 +#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0 +#define PATH0_R_RFMODE_FTM_RX_IDLE_C 0x12B0 +#define PATH0_R_RFMODE_FTM_RX_IDLE_C_M 0xF00 +#define PATH0_R_RXB_IDX_AT_TX_C 0x12B0 +#define PATH0_R_RXB_IDX_AT_TX_C_M 0x1F000 +#define PATH0_R_TIA_IDX_AT_TX_C 0x12B0 +#define PATH0_R_TIA_IDX_AT_TX_C_M 0x20000 +#define PATH0_R_LNA_IDX_AT_TX_C 0x12B0 +#define PATH0_R_LNA_IDX_AT_TX_C_M 0x1C0000 +#define PATH0_R_TIA_EXT_BW_AT_TX_C 0x12B0 +#define PATH0_R_TIA_EXT_BW_AT_TX_C_M 0x200000 +#define PATH0_R_SI_RADDR_C 0x12B0 +#define PATH0_R_SI_RADDR_C_M 0x3FC00000 +#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C 0x12B0 +#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000 +#define PATH0_R_SOFT3WIRE_DATA_C 0x12B4 +#define PATH0_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF +#define PATH0_R_TXAGC_AT_SLEEP_C 0x12B8 +#define PATH0_R_TXAGC_AT_SLEEP_C_M 0x3F +#define PATH0_R_RXB_IDX_AT_SLEEP_C 0x12B8 +#define PATH0_R_RXB_IDX_AT_SLEEP_C_M 0x7C0 +#define PATH0_R_TIA_IDX_AT_SLEEP_C 0x12B8 +#define PATH0_R_TIA_IDX_AT_SLEEP_C_M 0x800 +#define PATH0_R_LNA_IDX_AT_SLEEP_C 0x12B8 +#define PATH0_R_LNA_IDX_AT_SLEEP_C_M 0x7000 +#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C 0x12B8 +#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000 +#define PATH0_R_EN_NRBW_AT_SLEEP_C 0x12B8 +#define PATH0_R_EN_NRBW_AT_SLEEP_C_M 0x10000 +#define PATH0_R_RFMODE_AT_SLEEP_C 0x12B8 +#define PATH0_R_RFMODE_AT_SLEEP_C_M 0x1E0000 +#define PATH0_R_TXAGC_BYPASS_C 0x12B8 +#define PATH0_R_TXAGC_BYPASS_C_M 0x200000 +#define PATH0_R_RXB_BYPASS_C 0x12B8 +#define PATH0_R_RXB_BYPASS_C_M 0x400000 +#define PATH0_R_TIA_BYPASS_C 0x12B8 +#define PATH0_R_TIA_BYPASS_C_M 0x800000 +#define PATH0_R_LNA_BYPASS_C 0x12B8 +#define PATH0_R_LNA_BYPASS_C_M 0x1000000 +#define PATH0_R_TIA_EXT_BYPASS_C 0x12B8 +#define PATH0_R_TIA_EXT_BYPASS_C_M 0x2000000 +#define PATH0_R_EN_NRBW_BYPASS_C 0x12B8 +#define PATH0_R_EN_NRBW_BYPASS_C_M 0x4000000 +#define PATH0_R_RFREG_DIS_GATING_C 0x12B8 +#define PATH0_R_RFREG_DIS_GATING_C_M 0x8000000 +#define PATH0_R_RSTB_ANAPAR_C 0x12B8 +#define PATH0_R_RSTB_ANAPAR_C_M 0x10000000 +#define PATH0_R_ANAPAR_SEL_OPT_C 0x12B8 +#define PATH0_R_ANAPAR_SEL_OPT_C_M 0x20000000 +#define PATH0_R_ANAPAR_DBG_MODE_C 0x12B8 +#define PATH0_R_ANAPAR_DBG_MODE_C_M 0x40000000 +#define PATH0_R_ANAPAR_DIS_GATING_C 0x12B8 +#define PATH0_R_ANAPAR_DIS_GATING_C_M 0x80000000 +#define PATH0_R_ANAPAR_ST0_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST0_SEL_C_M 0xF +#define PATH0_R_ANAPAR_ST1_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST1_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_ST2_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST2_SEL_C_M 0xF00 +#define PATH0_R_ANAPAR_ST3_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST3_SEL_C_M 0xF000 +#define PATH0_R_ANAPAR_ST4_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST4_SEL_C_M 0xF0000 +#define PATH0_R_ANAPAR_ST5_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST5_SEL_C_M 0xF00000 +#define PATH0_R_ANAPAR_ST6_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST6_SEL_C_M 0xF000000 +#define PATH0_R_ANAPAR_ST7_SEL_C 0x12BC +#define PATH0_R_ANAPAR_ST7_SEL_C_M 0xF0000000 +#define PATH0_R_ANAPAR_ST8_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST8_SEL_C_M 0xF +#define PATH0_R_ANAPAR_ST9_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST9_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_ST10_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST10_SEL_C_M 0xF00 +#define PATH0_R_ANAPAR_ST11_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST11_SEL_C_M 0xF000 +#define PATH0_R_ANAPAR_ST12_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST12_SEL_C_M 0xF0000 +#define PATH0_R_ANAPAR_ST13_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST13_SEL_C_M 0xF00000 +#define PATH0_R_ANAPAR_ST14_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST14_SEL_C_M 0xF000000 +#define PATH0_R_ANAPAR_ST15_SEL_C 0x12C0 +#define PATH0_R_ANAPAR_ST15_SEL_C_M 0xF0000000 +#define PATH0_R_ANAPAR_ST16_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST16_SEL_C_M 0xF +#define PATH0_R_ANAPAR_ST17_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST17_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_ST18_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST18_SEL_C_M 0xF00 +#define PATH0_R_ANAPAR_ST19_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST19_SEL_C_M 0xF000 +#define PATH0_R_ANAPAR_ST20_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST20_SEL_C_M 0xF0000 +#define PATH0_R_ANAPAR_ST21_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST21_SEL_C_M 0xF00000 +#define PATH0_R_ANAPAR_ST22_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST22_SEL_C_M 0xF000000 +#define PATH0_R_ANAPAR_ST23_SEL_C 0x12C4 +#define PATH0_R_ANAPAR_ST23_SEL_C_M 0xF0000000 +#define PATH0_R_ANAPAR_ST24_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST24_SEL_C_M 0xF +#define PATH0_R_ANAPAR_ST25_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST25_SEL_C_M 0xF0 +#define PATH0_R_ANAPAR_ST26_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST26_SEL_C_M 0xF00 +#define PATH0_R_ANAPAR_ST27_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST27_SEL_C_M 0xF000 +#define PATH0_R_ANAPAR_ST28_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST28_SEL_C_M 0xF0000 +#define PATH0_R_ANAPAR_ST29_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST29_SEL_C_M 0xF00000 +#define PATH0_R_ANAPAR_ST30_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST30_SEL_C_M 0xF000000 +#define PATH0_R_ANAPAR_ST31_SEL_C 0x12C8 +#define PATH0_R_ANAPAR_ST31_SEL_C_M 0xF0000000 +#define PATH0_R_ANAPAR_CTSDM_31_0__C 0x12CC +#define PATH0_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_CTSDM_63_32__C 0x12D0 +#define PATH0_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_CTSDM_95_64__C 0x12D4 +#define PATH0_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_CTSDM_127_96__C 0x12D8 +#define PATH0_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_31_0__C 0x12DC +#define PATH0_R_ANAPAR_31_0__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_63_32__C 0x12E0 +#define PATH0_R_ANAPAR_63_32__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_95_64__C 0x12E4 +#define PATH0_R_ANAPAR_95_64__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_127_96__C 0x12E8 +#define PATH0_R_ANAPAR_127_96__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_143_128__C 0x12EC +#define PATH0_R_ANAPAR_143_128__C_M 0xFFFF +#define PATH0_R_ANAPAR_LBK_15_0__C 0x12EC +#define PATH0_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000 +#define PATH0_R_ANAPAR_LBK_47_16__C 0x12F0 +#define PATH0_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_LBK_79_48__C 0x12F4 +#define PATH0_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_LBK_111_80__C 0x12F8 +#define PATH0_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF +#define PATH0_R_ANAPAR_LBK_143_112__C 0x12FC +#define PATH0_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF +#define CNT_LA_TRIG_C 0x1700 +#define CNT_LA_TRIG_C_M 0xFFFF +#define CNT_CCKTXEN_C 0x1700 +#define CNT_CCKTXEN_C_M 0xFFFF0000 +#define CNT_CCKTXON_C 0x1704 +#define CNT_CCKTXON_C_M 0xFFFF +#define CNT_DBG_BIT_C 0x1704 +#define CNT_DBG_BIT_C_M 0xFFFF0000 +#define CNT_CCK_CCA_P0_C 0x1710 +#define CNT_CCK_CCA_P0_C_M 0xFFFF +#define CNT_CCK_CRC16FAIL_P0_C 0x1710 +#define CNT_CCK_CRC16FAIL_P0_C_M 0xFFFF0000 +#define CNT_CCK_CRC32OK_P0_C 0x1714 +#define CNT_CCK_CRC32OK_P0_C_M 0xFFFF +#define CNT_CCK_CRC32FAIL_P0_C 0x1714 +#define CNT_CCK_CRC32FAIL_P0_C_M 0xFFFF0000 +#define CNT_CCK_CCA_P1_C 0x1718 +#define CNT_CCK_CCA_P1_C_M 0xFFFF +#define CNT_CCK_CRC16FAIL_P1_C 0x1718 +#define CNT_CCK_CRC16FAIL_P1_C_M 0xFFFF0000 +#define CNT_CCK_CRC32OK_P1_C 0x171C +#define CNT_CCK_CRC32OK_P1_C_M 0xFFFF +#define CNT_CCK_CRC32FAIL_P1_C 0x171C +#define CNT_CCK_CRC32FAIL_P1_C_M 0xFFFF0000 +#define AXTOP_BIST_C 0x1720 +#define AXTOP_BIST_C_M 0xFFFFFFFF +#define AXRX_IN_BIST_C 0x1724 +#define AXRX_IN_BIST_C_M 0xFFFFFFFF +#define AXTD_BIST_C 0x1728 +#define AXTD_BIST_C_M 0xFFFFFFFF +#define AXOUT_BIST_C 0x172C +#define AXOUT_BIST_C_M 0xFFFFFFFF +#define DBG32_D_C 0x1730 +#define DBG32_D_C_M 0xFFFFFFFF +#define PSD_PW_C 0x1734 +#define PSD_PW_C_M 0x1FFFFFF +#define PSD_OK_FLAG_C 0x1734 +#define PSD_OK_FLAG_C_M 0x2000000 +#define EDCCA_IOQ_P0_A_C 0x1738 +#define EDCCA_IOQ_P0_A_C_M 0xFFFFFFFF +#define EDCCA_IOQ_P0_B_C 0x173C +#define EDCCA_IOQ_P0_B_C_M 0xFFFFFFFF +#define EDCCA_IOQ_P1_A_C 0x1740 +#define EDCCA_IOQ_P1_A_C_M 0xFFFFFFFF +#define EDCCA_IOQ_P1_B_C 0x1744 +#define EDCCA_IOQ_P1_B_C_M 0xFFFFFFFF +#define RO_SI_R_DATA_AFC_C 0x1748 +#define RO_SI_R_DATA_AFC_C_M 0xFFFFFFFF +#define SW_SI_READ_DATA_C 0x174C +#define SW_SI_READ_DATA_C_M 0xFFFFF +#define SW_SI_CNT_CONFLICT_C 0x174C +#define SW_SI_CNT_CONFLICT_C_M 0xF00000 +#define SW_SI_W_BUSY_C 0x174C +#define SW_SI_W_BUSY_C_M 0x1000000 +#define SW_SI_R_BUSY_C 0x174C +#define SW_SI_R_BUSY_C_M 0x2000000 +#define SW_SI_READ_DATA_DONE_C 0x174C +#define SW_SI_READ_DATA_DONE_C_M 0x4000000 +#define CNT_SW_SI_R_C 0x1750 +#define CNT_SW_SI_R_C_M 0xFFFF +#define CNT_SW_SI_W_C 0x1750 +#define CNT_SW_SI_W_C_M 0xFFFF0000 +#define SWSI_RECORD_1ST_C 0x1758 +#define SWSI_RECORD_1ST_C_M 0x3FFFFF +#define SWSI_RECORD_2ND_C 0x1760 +#define SWSI_RECORD_2ND_C_M 0x3FFFFF +#define SWSI_CMD_CNT_C 0x1764 +#define SWSI_CMD_CNT_C_M 0x3F +#define SWSI_NOW_IS_1ST_C 0x1764 +#define SWSI_NOW_IS_1ST_C_M 0x40000000 +#define SWSI_NOW_IS_2ND_C 0x1764 +#define SWSI_NOW_IS_2ND_C_M 0x80000000 +#define HWSI_RECORD_1ST_0_C 0x1768 +#define HWSI_RECORD_1ST_0_C_M 0x1FFF +#define HWSI_RECORD_1ST_1_C 0x1768 +#define HWSI_RECORD_1ST_1_C_M 0x1FFF0000 +#define HWSI_RECORD_2ND_0_C 0x176C +#define HWSI_RECORD_2ND_0_C_M 0x1FFF +#define HWSI_RECORD_2ND_1_C 0x176C +#define HWSI_RECORD_2ND_1_C_M 0x1FFF0000 +#define HWSI_RECORD_3RD_0_C 0x1770 +#define HWSI_RECORD_3RD_0_C_M 0x1FFF +#define HWSI_RECORD_3RD_1_C 0x1770 +#define HWSI_RECORD_3RD_1_C_M 0x1FFF0000 +#define HWSI_RECORD_4TH_0_C 0x1774 +#define HWSI_RECORD_4TH_0_C_M 0x1FFF +#define HWSI_RECORD_4TH_1_C 0x1774 +#define HWSI_RECORD_4TH_1_C_M 0x1FFF0000 +#define HWSI_CMD_CNT_C 0x1778 +#define HWSI_CMD_CNT_C_M 0x3F +#define HWSI_NOW_IS_1ST_C 0x1778 +#define HWSI_NOW_IS_1ST_C_M 0x10000000 +#define HWSI_NOW_IS_2ND_C 0x1778 +#define HWSI_NOW_IS_2ND_C_M 0x20000000 +#define HWSI_NOW_IS_3RD_C 0x1778 +#define HWSI_NOW_IS_3RD_C_M 0x40000000 +#define HWSI_NOW_IS_4TH_C 0x1778 +#define HWSI_NOW_IS_4TH_C_M 0x80000000 +#define WLS0_RFMODE_C 0x177C +#define WLS0_RFMODE_C_M 0xF +#define WLS0_TSSI_OFST_C 0x177C +#define WLS0_TSSI_OFST_C_M 0x1F0 +#define WLS0_TX_CCK_IND_C 0x177C +#define WLS0_TX_CCK_IND_C_M 0x200 +#define WLS0_TX_GAIN_C 0x177C +#define WLS0_TX_GAIN_C_M 0xFC00 +#define WLS0_EN_PAD_GAPK_C 0x177C +#define WLS0_EN_PAD_GAPK_C_M 0x10000 +#define WLS0_EN_PA_GAPK_C 0x177C +#define WLS0_EN_PA_GAPK_C_M 0x20000 +#define WLS0_PAD_GAPK_IDX_C 0x177C +#define WLS0_PAD_GAPK_IDX_C_M 0x1FC0000 +#define WLS0_PA_GAPK_IDX_C 0x177C +#define WLS0_PA_GAPK_IDX_C_M 0x7E000000 +#define WLS1_RFMODE_C 0x1780 +#define WLS1_RFMODE_C_M 0xF +#define WLS1_TSSI_OFST_C 0x1780 +#define WLS1_TSSI_OFST_C_M 0x1F0 +#define WLS1_TX_CCK_IND_C 0x1780 +#define WLS1_TX_CCK_IND_C_M 0x200 +#define WLS1_TX_GAIN_C 0x1780 +#define WLS1_TX_GAIN_C_M 0xFC00 +#define WLS1_EN_PAD_GAPK_C 0x1780 +#define WLS1_EN_PAD_GAPK_C_M 0x10000 +#define WLS1_EN_PA_GAPK_C 0x1780 +#define WLS1_EN_PA_GAPK_C_M 0x20000 +#define WLS1_PAD_GAPK_IDX_C 0x1780 +#define WLS1_PAD_GAPK_IDX_C_M 0x1FC0000 +#define WLS1_PA_GAPK_IDX_C 0x1780 +#define WLS1_PA_GAPK_IDX_C_M 0x7E000000 +#define BW_TXS0_C 0x1784 +#define BW_TXS0_C_M 0x7 +#define DAC_0P5DB_S0_C 0x1784 +#define DAC_0P5DB_S0_C_M 0x8 +#define GAIN_TX_S0_C 0x1784 +#define GAIN_TX_S0_C_M 0x1F0 +#define GAIN_TX_GAPK_S0_C 0x1784 +#define GAIN_TX_GAPK_S0_C_M 0x1E00 +#define BW_TXS1_C 0x1784 +#define BW_TXS1_C_M 0x70000 +#define DAC_0P5DB_S1_C 0x1784 +#define DAC_0P5DB_S1_C_M 0x80000 +#define GAIN_TX_S1_C 0x1784 +#define GAIN_TX_S1_C_M 0x1F00000 +#define GAIN_TX_GAPK_S1_C 0x1784 +#define GAIN_TX_GAPK_S1_C_M 0x1E000000 +#define LO_SEL_C 0x1784 +#define LO_SEL_C_M 0xC0000000 +#define INTF_TXINFO_PPDU_TYPE_3_0__C 0x1800 +#define INTF_TXINFO_PPDU_TYPE_3_0__C_M 0xF +#define INTF_TXINFO_CH20_WITH_DATA_7_0__C 0x1800 +#define INTF_TXINFO_CH20_WITH_DATA_7_0__C_M 0xFF0 +#define INTF_TXINFO_PATH_EN_3_0__C 0x1800 +#define INTF_TXINFO_PATH_EN_3_0__C_M 0xF000 +#define INTF_TXINFO_PATH_MAP_A_1_0__C 0x1800 +#define INTF_TXINFO_PATH_MAP_A_1_0__C_M 0x30000 +#define INTF_TXINFO_PATH_MAP_B_1_0__C 0x1800 +#define INTF_TXINFO_PATH_MAP_B_1_0__C_M 0xC0000 +#define INTF_TXINFO_PATH_MAP_C_1_0__C 0x1800 +#define INTF_TXINFO_PATH_MAP_C_1_0__C_M 0x300000 +#define INTF_TXINFO_PATH_MAP_D_1_0__C 0x1800 +#define INTF_TXINFO_PATH_MAP_D_1_0__C_M 0xC00000 +#define INTF_TXINFO_TXCMD_TXTP_5_0__C 0x1800 +#define INTF_TXINFO_TXCMD_TXTP_5_0__C_M 0x3F000000 +#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C 0x1800 +#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C_M 0xC0000000 +#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C 0x1804 +#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C_M 0x3 +#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C 0x1804 +#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C_M 0x4 +#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C 0x1804 +#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C_M 0x8 +#define INTF_TXINFO_TXSC_3_0__C 0x1804 +#define INTF_TXINFO_TXSC_3_0__C_M 0xF0 +#define INTF_TXINFO_TX_SWING_3_0__C 0x1804 +#define INTF_TXINFO_TX_SWING_3_0__C_M 0xF00 +#define INTF_TXINFO_RATE_BIAS_1_0__C 0x1804 +#define INTF_TXINFO_RATE_BIAS_1_0__C_M 0x3000 +#define INTF_TXINFO_DBW_IDX_1_0__C 0x1804 +#define INTF_TXINFO_DBW_IDX_1_0__C_M 0x30000 +#define INTF_TXINFO_TX_PW_DBM_8_0__C 0x1804 +#define INTF_TXINFO_TX_PW_DBM_8_0__C_M 0x7FC0000 +#define INTF_TXINFO_CFO_COMP_2_0__C 0x1804 +#define INTF_TXINFO_CFO_COMP_2_0__C_M 0x38000000 +#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C 0x1808 +#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C_M 0x1 +#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C 0x1808 +#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C_M 0x2 +#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C 0x1808 +#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C_M 0x4 +#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C 0x1808 +#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C_M 0x8 +#define INTF_TXINFO_N_USR_7_0__C 0x1808 +#define INTF_TXINFO_N_USR_7_0__C_M 0xFF0 +#define INTF_TXINFO_CCA_PW_TH_7_0__C 0x1808 +#define INTF_TXINFO_CCA_PW_TH_7_0__C_M 0xFF000 +#define INTF_TXINFO_CCA_PW_TH_EN_0__C 0x1808 +#define INTF_TXINFO_CCA_PW_TH_EN_0__C_M 0x100000 +#define INTF_TXINFO_RF_GAIN_IDX_9_0__C 0x1808 +#define INTF_TXINFO_RF_GAIN_IDX_9_0__C_M 0x7FE00000 +#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C 0x1808 +#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C_M 0x80000000 +#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C 0x180C +#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C_M 0x1 +#define INTF_TXCOMCT_STBC_EN_0__C 0x1810 +#define INTF_TXCOMCT_STBC_EN_0__C_M 0x1 +#define INTF_TXCOMCT_DOPPLER_EN_0__C 0x1810 +#define INTF_TXCOMCT_DOPPLER_EN_0__C_M 0x4 +#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C 0x1810 +#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C_M 0x8 +#define INTF_TXCOMCT_GI_TYPE_1_0__C 0x1810 +#define INTF_TXCOMCT_GI_TYPE_1_0__C_M 0x30 +#define INTF_TXCOMCT_LTF_TYPE_1_0__C 0x1810 +#define INTF_TXCOMCT_LTF_TYPE_1_0__C_M 0xC0 +#define INTF_TXCOMCT_N_LTF_2_0__C 0x1810 +#define INTF_TXCOMCT_N_LTF_2_0__C_M 0x700 +#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C 0x1810 +#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C_M 0x800 +#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C 0x1814 +#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C_M 0x8 +#define INTF_TXCOMCT_NDP_0__C 0x1814 +#define INTF_TXCOMCT_NDP_0__C_M 0x10 +#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C 0x1814 +#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C_M 0x20 +#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C 0x1814 +#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C_M 0x40 +#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C 0x1814 +#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C_M 0x380 +#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C 0x1814 +#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C_M 0x400 +#define INTF_TXUSRCT0_U_ID_7_0__C 0x1818 +#define INTF_TXUSRCT0_U_ID_7_0__C_M 0xFF +#define INTF_TXUSRCT0_RU_ALLOC_7_0__C 0x1818 +#define INTF_TXUSRCT0_RU_ALLOC_7_0__C_M 0xFF00 +#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C 0x1818 +#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C_M 0x70000 +#define INTF_TXUSRCT0_STRT_STS_2_0__C 0x1818 +#define INTF_TXUSRCT0_STRT_STS_2_0__C_M 0xE00000 +#define INTF_TXUSRCT0_N_STS_2_0__C 0x1818 +#define INTF_TXUSRCT0_N_STS_2_0__C_M 0x7000000 +#define INTF_TXUSRCT0_FEC_TYPE_0__C 0x1818 +#define INTF_TXUSRCT0_FEC_TYPE_0__C_M 0x8000000 +#define INTF_TXUSRCT0_MCS_3_0__C 0x1818 +#define INTF_TXUSRCT0_MCS_3_0__C_M 0xF0000000 +#define INTF_TXUSRCT0_MCS_5_4__C 0x181C +#define INTF_TXUSRCT0_MCS_5_4__C_M 0x3 +#define INTF_TXUSRCT0_DCM_EN_0__C 0x181C +#define INTF_TXUSRCT0_DCM_EN_0__C_M 0x4 +#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C 0x181C +#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C_M 0x3FF8 +#define INTF_TXUSRCT0_TXBF_EN_0__C 0x181C +#define INTF_TXUSRCT0_TXBF_EN_0__C_M 0x4000 +#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C 0x181C +#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000 +#define INTF_TXUSRCT1_U_ID_7_0__C 0x1820 +#define INTF_TXUSRCT1_U_ID_7_0__C_M 0xFF +#define INTF_TXUSRCT1_RU_ALLOC_7_0__C 0x1820 +#define INTF_TXUSRCT1_RU_ALLOC_7_0__C_M 0xFF00 +#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C 0x1820 +#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C_M 0x70000 +#define INTF_TXUSRCT1_STRT_STS_2_0__C 0x1820 +#define INTF_TXUSRCT1_STRT_STS_2_0__C_M 0xE00000 +#define INTF_TXUSRCT1_N_STS_2_0__C 0x1820 +#define INTF_TXUSRCT1_N_STS_2_0__C_M 0x7000000 +#define INTF_TXUSRCT1_FEC_TYPE_0__C 0x1820 +#define INTF_TXUSRCT1_FEC_TYPE_0__C_M 0x8000000 +#define INTF_TXUSRCT1_MCS_3_0__C 0x1820 +#define INTF_TXUSRCT1_MCS_3_0__C_M 0xF0000000 +#define INTF_TXUSRCT1_MCS_5_4__C 0x1824 +#define INTF_TXUSRCT1_MCS_5_4__C_M 0x3 +#define INTF_TXUSRCT1_DCM_EN_0__C 0x1824 +#define INTF_TXUSRCT1_DCM_EN_0__C_M 0x4 +#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C 0x1824 +#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C_M 0x3FF8 +#define INTF_TXUSRCT1_TXBF_EN_0__C 0x1824 +#define INTF_TXUSRCT1_TXBF_EN_0__C_M 0x4000 +#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C 0x1824 +#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000 +#define INTF_TXUSRCT2_U_ID_7_0__C 0x1828 +#define INTF_TXUSRCT2_U_ID_7_0__C_M 0xFF +#define INTF_TXUSRCT2_RU_ALLOC_7_0__C 0x1828 +#define INTF_TXUSRCT2_RU_ALLOC_7_0__C_M 0xFF00 +#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C 0x1828 +#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C_M 0x70000 +#define INTF_TXUSRCT2_STRT_STS_2_0__C 0x1828 +#define INTF_TXUSRCT2_STRT_STS_2_0__C_M 0xE00000 +#define INTF_TXUSRCT2_N_STS_2_0__C 0x1828 +#define INTF_TXUSRCT2_N_STS_2_0__C_M 0x7000000 +#define INTF_TXUSRCT2_FEC_TYPE_0__C 0x1828 +#define INTF_TXUSRCT2_FEC_TYPE_0__C_M 0x8000000 +#define INTF_TXUSRCT2_MCS_3_0__C 0x1828 +#define INTF_TXUSRCT2_MCS_3_0__C_M 0xF0000000 +#define INTF_TXUSRCT2_MCS_5_4__C 0x182C +#define INTF_TXUSRCT2_MCS_5_4__C_M 0x3 +#define INTF_TXUSRCT2_DCM_EN_0__C 0x182C +#define INTF_TXUSRCT2_DCM_EN_0__C_M 0x4 +#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C 0x182C +#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C_M 0x3FF8 +#define INTF_TXUSRCT2_TXBF_EN_0__C 0x182C +#define INTF_TXUSRCT2_TXBF_EN_0__C_M 0x4000 +#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C 0x182C +#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000 +#define INTF_TXUSRCT3_U_ID_7_0__C 0x1830 +#define INTF_TXUSRCT3_U_ID_7_0__C_M 0xFF +#define INTF_TXUSRCT3_RU_ALLOC_7_0__C 0x1830 +#define INTF_TXUSRCT3_RU_ALLOC_7_0__C_M 0xFF00 +#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C 0x1830 +#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C_M 0x70000 +#define INTF_TXUSRCT3_STRT_STS_2_0__C 0x1830 +#define INTF_TXUSRCT3_STRT_STS_2_0__C_M 0xE00000 +#define INTF_TXUSRCT3_N_STS_2_0__C 0x1830 +#define INTF_TXUSRCT3_N_STS_2_0__C_M 0x7000000 +#define INTF_TXUSRCT3_FEC_TYPE_0__C 0x1830 +#define INTF_TXUSRCT3_FEC_TYPE_0__C_M 0x8000000 +#define INTF_TXUSRCT3_MCS_3_0__C 0x1830 +#define INTF_TXUSRCT3_MCS_3_0__C_M 0xF0000000 +#define INTF_TXUSRCT3_MCS_5_4__C 0x1834 +#define INTF_TXUSRCT3_MCS_5_4__C_M 0x3 +#define INTF_TXUSRCT3_DCM_EN_0__C 0x1834 +#define INTF_TXUSRCT3_DCM_EN_0__C_M 0x4 +#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C 0x1834 +#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C_M 0x3FF8 +#define INTF_TXUSRCT3_TXBF_EN_0__C 0x1834 +#define INTF_TXUSRCT3_TXBF_EN_0__C_M 0x4000 +#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C 0x1834 +#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000 +#define INTF_TXTIMCT_N_SYM_10_0__C 0x1838 +#define INTF_TXTIMCT_N_SYM_10_0__C_M 0x7FF +#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C 0x1838 +#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C_M 0x3F0000 +#define INTF_TXTIMCT_LDPC_EXTR_0__C 0x1838 +#define INTF_TXTIMCT_LDPC_EXTR_0__C_M 0x1000000 +#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C 0x1838 +#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C_M 0xE000000 +#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C 0x1838 +#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C_M 0x30000000 +#define INTF_TX_LSIG_LATCH_31_0__C 0x1840 +#define INTF_TX_LSIG_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_LSIG_LATCH_63_32__C 0x1844 +#define INTF_TX_LSIG_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_SIGA_LATCH_31_0__C 0x1848 +#define INTF_TX_SIGA_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_SIGA_LATCH_63_32__C 0x184C +#define INTF_TX_SIGA_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_VHT_SIGB0_LATCH_31_0__C 0x1850 +#define INTF_TX_VHT_SIGB0_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_VHT_SIGB0_LATCH_63_32__C 0x1854 +#define INTF_TX_VHT_SIGB0_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_VHT_SIGB1_LATCH_31_0__C 0x1858 +#define INTF_TX_VHT_SIGB1_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_VHT_SIGB1_LATCH_63_32__C 0x185C +#define INTF_TX_VHT_SIGB1_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C 0x1860 +#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C 0x1864 +#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C 0x1868 +#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C 0x186C +#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C 0x1870 +#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C 0x1874 +#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C 0x1878 +#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C 0x187C +#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C 0x1880 +#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C 0x1884 +#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C 0x1888 +#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C 0x188C +#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C 0x1890 +#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C 0x1894 +#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C 0x1898 +#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C 0x189C +#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C 0x18A0 +#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C 0x18A4 +#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C 0x18A8 +#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C 0x18AC +#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C 0x18B0 +#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C 0x18B4 +#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C 0x18B8 +#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C 0x18BC +#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C 0x18C0 +#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C 0x18C4 +#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C 0x18C8 +#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C 0x18CC +#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C 0x18D0 +#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C 0x18D4 +#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C 0x18D8 +#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C_M 0xFFFFFFFF +#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C 0x18DC +#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C_M 0xFFFFFFFF +#define INTF_MAC_PHY_TXEN_C 0x18E0 +#define INTF_MAC_PHY_TXEN_C_M 0x1 +#define INTF_MAC_PHY_TXON_C 0x18E0 +#define INTF_MAC_PHY_TXON_C_M 0x10 +#define CNT_CCA_SPOOFING_C 0x1A00 +#define CNT_CCA_SPOOFING_C_M 0xFFFF +#define CNT_LSIG_BRK_S_TH_C 0x1A00 +#define CNT_LSIG_BRK_S_TH_C_M 0xFFFF0000 +#define CNT_LSIG_BRK_L_TH_C 0x1A04 +#define CNT_LSIG_BRK_L_TH_C_M 0xFFFF +#define CNT_HTSIG_CRC8_ERR_S_TH_C 0x1A04 +#define CNT_HTSIG_CRC8_ERR_S_TH_C_M 0xFFFF0000 +#define CNT_HTSIG_CRC8_ERR_L_TH_C 0x1A08 +#define CNT_HTSIG_CRC8_ERR_L_TH_C_M 0xFFFF +#define CNT_BRK_C 0x1A08 +#define CNT_BRK_C_M 0xFFFF0000 +#define CNT_BRK_SEL_C 0x1A0C +#define CNT_BRK_SEL_C_M 0xFFFF +#define CNT_RXL_ERR_PARITY_C 0x1A0C +#define CNT_RXL_ERR_PARITY_C_M 0xFFFF0000 +#define CNT_RXL_ERR_RATE_C 0x1A10 +#define CNT_RXL_ERR_RATE_C_M 0xFFFF +#define CNT_HT_ERR_CRC8_C 0x1A10 +#define CNT_HT_ERR_CRC8_C_M 0xFFFF0000 +#define CNT_VHT_ERR_SIGA_CRC8_C 0x1A14 +#define CNT_VHT_ERR_SIGA_CRC8_C_M 0xFFFF +#define CNT_HT_NOT_SUPPORT_MCS_C 0x1A18 +#define CNT_HT_NOT_SUPPORT_MCS_C_M 0xFFFF +#define CNT_VHT_NOT_SUPPORT_MCS_C 0x1A18 +#define CNT_VHT_NOT_SUPPORT_MCS_C_M 0xFFFF0000 +#define CNT_ERR_DURING_BT_TX_C 0x1A1C +#define CNT_ERR_DURING_BT_TX_C_M 0xFFFF +#define CNT_ERR_DURING_BT_RX_C 0x1A1C +#define CNT_ERR_DURING_BT_RX_C_M 0xFFFF0000 +#define CNT_EDGE_MURX_NSTS0_C 0x1A20 +#define CNT_EDGE_MURX_NSTS0_C_M 0xFFFF +#define CNT_SEARCH_FAIL_C 0x1A20 +#define CNT_SEARCH_FAIL_C_M 0xFFFF0000 +#define CNT_OFDM_CCA_C 0x1A24 +#define CNT_OFDM_CCA_C_M 0xFFFF +#define CNT_OFDM_CCA_S20_C 0x1A24 +#define CNT_OFDM_CCA_S20_C_M 0xFFFF0000 +#define CNT_OFDM_CCA_S40_C 0x1A28 +#define CNT_OFDM_CCA_S40_C_M 0xFFFF +#define CNT_OFDM_CCA_S80_C 0x1A28 +#define CNT_OFDM_CCA_S80_C_M 0xFFFF0000 +#define CNT_INVLD_CCA1_CCK_PKT_C 0x1A2C +#define CNT_INVLD_CCA1_CCK_PKT_C_M 0xFFFF +#define CNT_INVLD_CCA1_OFDM_PKT_C 0x1A2C +#define CNT_INVLD_CCA1_OFDM_PKT_C_M 0xFFFF0000 +#define CNT_INVLD_PKT_C 0x1A30 +#define CNT_INVLD_PKT_C_M 0xFFFF +#define CNT_INVLD_CCA0_PKT_C 0x1A30 +#define CNT_INVLD_CCA0_PKT_C_M 0xFFFF0000 +#define CNT_OFDM_CCA_MAC_C 0x1A34 +#define CNT_OFDM_CCA_MAC_C_M 0xFFFF +#define CNT_CCK_CCA_MAC_C 0x1A34 +#define CNT_CCK_CCA_MAC_C_M 0xFFFF0000 +#define CNT_MAC_PIN_C 0x1A38 +#define CNT_MAC_PIN_C_M 0xFFFF +#define CNT_GNT_CONFLICT_TX_C 0x1A38 +#define CNT_GNT_CONFLICT_TX_C_M 0xFFFF0000 +#define CNT_GNT_CONFLICT_RX_C 0x1A3C +#define CNT_GNT_CONFLICT_RX_C_M 0xFFFF +#define CNT_FTM_LBK_C 0x1A3C +#define CNT_FTM_LBK_C_M 0xFFFF0000 +#define CNT_OFDMTXON_C 0x1A40 +#define CNT_OFDMTXON_C_M 0xFFFF +#define CNT_OFDMTXEN_C 0x1A40 +#define CNT_OFDMTXEN_C_M 0xFFFF0000 +#define CNT_DROP_TRIG_C 0x1A44 +#define CNT_DROP_TRIG_C_M 0xFFFF +#define CNT_POP_TRIG_C 0x1A44 +#define CNT_POP_TRIG_C_M 0xFFFF0000 +#define CNT_TX_CONFLICT_C 0x1A48 +#define CNT_TX_CONFLICT_C_M 0xFFFF +#define CNT_WMAC_RSTB_C 0x1A48 +#define CNT_WMAC_RSTB_C_M 0xFFFF0000 +#define CNT_EN_TB_PPDU_FIX_GAIN_C 0x1A4C +#define CNT_EN_TB_PPDU_FIX_GAIN_C_M 0xFFFF +#define CNT_EN_TB_CCA_PW_TH_C 0x1A4C +#define CNT_EN_TB_CCA_PW_TH_C_M 0xFFFF0000 +#define CNT_TB_FAIL_FREERUN_C 0x1A50 +#define CNT_TB_FAIL_FREERUN_C_M 0xFFFF +#define CNT_TB_PD_HIT_SEG0_C 0x1A50 +#define CNT_TB_PD_HIT_SEG0_C_M 0xFFFF0000 +#define CNT_TB_SBDRDY_SEG0_C 0x1A54 +#define CNT_TB_SBDRDY_SEG0_C_M 0xFFFF +#define CNT_FAIL_FORCE_CCA_PW_TB_C 0x1A54 +#define CNT_FAIL_FORCE_CCA_PW_TB_C_M 0xFF0000 +#define CNT_FAIL_FORCE_GAIN_TB_C 0x1A54 +#define CNT_FAIL_FORCE_GAIN_TB_C_M 0xFF000000 +#define CNT_HE_CRC_OK_C 0x1A58 +#define CNT_HE_CRC_OK_C_M 0xFFFF +#define CNT_HE_CRC_ERR_C 0x1A58 +#define CNT_HE_CRC_ERR_C_M 0xFFFF0000 +#define CNT_VHT_CRC_OK_C 0x1A5C +#define CNT_VHT_CRC_OK_C_M 0xFFFF +#define CNT_VHT_CRC_ERR_C 0x1A5C +#define CNT_VHT_CRC_ERR_C_M 0xFFFF0000 +#define CNT_HT_CRC_OK_C 0x1A60 +#define CNT_HT_CRC_OK_C_M 0xFFFF +#define CNT_HT_CRC_ERR_C 0x1A60 +#define CNT_HT_CRC_ERR_C_M 0xFFFF0000 +#define CNT_L_CRC_OK_C 0x1A64 +#define CNT_L_CRC_OK_C_M 0xFFFF +#define CNT_L_CRC_ERR_C 0x1A64 +#define CNT_L_CRC_ERR_C_M 0xFFFF0000 +#define CNT_HE_CRC_OK2_C 0x1A68 +#define CNT_HE_CRC_OK2_C_M 0xFFFF +#define CNT_HE_CRC_ERR2_C 0x1A68 +#define CNT_HE_CRC_ERR2_C_M 0xFFFF0000 +#define CNT_VHT_CRC_OK2_C 0x1A6C +#define CNT_VHT_CRC_OK2_C_M 0xFFFF +#define CNT_VHT_CRC_ERR2_C 0x1A6C +#define CNT_VHT_CRC_ERR2_C_M 0xFFFF0000 +#define CNT_HT_CRC_OK2_C 0x1A70 +#define CNT_HT_CRC_OK2_C_M 0xFFFF +#define CNT_HT_CRC_ERR2_C 0x1A70 +#define CNT_HT_CRC_ERR2_C_M 0xFFFF0000 +#define CNT_L_CRC_OK2_C 0x1A74 +#define CNT_L_CRC_OK2_C_M 0xFFFF +#define CNT_L_CRC_ERR2_C 0x1A74 +#define CNT_L_CRC_ERR2_C_M 0xFFFF0000 +#define CNT_L_CRC_OK3_C 0x1A78 +#define CNT_L_CRC_OK3_C_M 0xFFFF +#define CNT_L_CRC_ERR3_C 0x1A78 +#define CNT_L_CRC_ERR3_C_M 0xFFFF0000 +#define CNT_AMPDU_RXON_C 0x1A7C +#define CNT_AMPDU_RXON_C_M 0xFFFF +#define CNT_AMPDU_MISS_C 0x1A7C +#define CNT_AMPDU_MISS_C_M 0xFFFF0000 +#define CNT_AMPDU_RX_CRC32_OK_C 0x1A80 +#define CNT_AMPDU_RX_CRC32_OK_C_M 0xFFFF +#define CNT_AMPDU_RX_CRC32_ERR_C 0x1A80 +#define CNT_AMPDU_RX_CRC32_ERR_C_M 0xFFFF0000 +#define CNT_PKT_FMT_MATCH_C 0x1A84 +#define CNT_PKT_FMT_MATCH_C_M 0xFFFF +#define CNT_LA_FRAME_CTRL_MATCH_C 0x1A84 +#define CNT_LA_FRAME_CTRL_MATCH_C_M 0xFFFF0000 +#define NHM_CNT0_C 0x1A88 +#define NHM_CNT0_C_M 0xFFFF +#define NHM_CNT1_C 0x1A88 +#define NHM_CNT1_C_M 0xFFFF0000 +#define NHM_CNT2_C 0x1A8C +#define NHM_CNT2_C_M 0xFFFF +#define NHM_CNT3_C 0x1A8C +#define NHM_CNT3_C_M 0xFFFF0000 +#define NHM_CNT4_C 0x1A90 +#define NHM_CNT4_C_M 0xFFFF +#define NHM_CNT5_C 0x1A90 +#define NHM_CNT5_C_M 0xFFFF0000 +#define NHM_CNT6_C 0x1A94 +#define NHM_CNT6_C_M 0xFFFF +#define NHM_CNT7_C 0x1A94 +#define NHM_CNT7_C_M 0xFFFF0000 +#define NHM_CNT8_C 0x1A98 +#define NHM_CNT8_C_M 0xFFFF +#define NHM_CNT9_C 0x1A98 +#define NHM_CNT9_C_M 0xFFFF0000 +#define NHM_CNT10_C 0x1A9C +#define NHM_CNT10_C_M 0xFFFF +#define NHM_CNT11_C 0x1A9C +#define NHM_CNT11_C_M 0xFFFF0000 +#define NHM_CCA_CNT_C 0x1AA0 +#define NHM_CCA_CNT_C_M 0xFFFF +#define NHM_TXON_CNT_C 0x1AA0 +#define NHM_TXON_CNT_C_M 0xFFFF0000 +#define NHM_IDLE_CNT_C 0x1AA4 +#define NHM_IDLE_CNT_C_M 0xFFFF +#define NHM_RDY_C 0x1AA4 +#define NHM_RDY_C_M 0x10000 +#define RO_FAHM_NUM0_C 0x1AA8 +#define RO_FAHM_NUM0_C_M 0xFFFF +#define RO_FAHM_NUM1_C 0x1AA8 +#define RO_FAHM_NUM1_C_M 0xFFFF0000 +#define RO_FAHM_NUM2_C 0x1AAC +#define RO_FAHM_NUM2_C_M 0xFFFF +#define RO_FAHM_NUM3_C 0x1AAC +#define RO_FAHM_NUM3_C_M 0xFFFF0000 +#define RO_FAHM_NUM4_C 0x1AB0 +#define RO_FAHM_NUM4_C_M 0xFFFF +#define RO_FAHM_NUM5_C 0x1AB0 +#define RO_FAHM_NUM5_C_M 0xFFFF0000 +#define RO_FAHM_NUM6_C 0x1AB4 +#define RO_FAHM_NUM6_C_M 0xFFFF +#define RO_FAHM_NUM7_C 0x1AB4 +#define RO_FAHM_NUM7_C_M 0xFFFF0000 +#define RO_FAHM_NUM8_C 0x1AB8 +#define RO_FAHM_NUM8_C_M 0xFFFF +#define RO_FAHM_NUM9_C 0x1AB8 +#define RO_FAHM_NUM9_C_M 0xFFFF0000 +#define RO_FAHM_NUM10_C 0x1ABC +#define RO_FAHM_NUM10_C_M 0xFFFF +#define RO_FAHM_NUM11_C 0x1ABC +#define RO_FAHM_NUM11_C_M 0xFFFF0000 +#define RO_FAHM_DEN_C 0x1AC0 +#define RO_FAHM_DEN_C_M 0xFFFF +#define RO_FAHM_RDY_C 0x1AC0 +#define RO_FAHM_RDY_C_M 0x10000 +#define RO_CLM_RESULT_C 0x1AC4 +#define RO_CLM_RESULT_C_M 0xFFFF +#define RO_CLM_RDY_C 0x1AC4 +#define RO_CLM_RDY_C_M 0x10000 +#define RO_CLM_EDCCA_RESULT_C 0x1AC8 +#define RO_CLM_EDCCA_RESULT_C_M 0xFFFF +#define RO_CLM_EDCCA_RDY_C 0x1AC8 +#define RO_CLM_EDCCA_RDY_C_M 0x10000 +#define IFSCNT_CNT_TX_C 0x1ACC +#define IFSCNT_CNT_TX_C_M 0xFFFF +#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C 0x1ACC +#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C_M 0xFFFF0000 +#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C 0x1AD0 +#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C_M 0xFFFF +#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C 0x1AD0 +#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C_M 0xFFFF0000 +#define IFSCNT_CNT_CCKFA_C 0x1AD4 +#define IFSCNT_CNT_CCKFA_C_M 0xFFFF +#define IFSCNT_CNT_OFDMFA_C 0x1AD4 +#define IFSCNT_CNT_OFDMFA_C_M 0xFFFF0000 +#define IFS_T1_AVG_C 0x1ADC +#define IFS_T1_AVG_C_M 0xFFFF +#define IFS_T2_AVG_C 0x1ADC +#define IFS_T2_AVG_C_M 0xFFFF0000 +#define IFS_T3_AVG_C 0x1AE0 +#define IFS_T3_AVG_C_M 0xFFFF +#define IFS_T4_AVG_C 0x1AE0 +#define IFS_T4_AVG_C_M 0xFFFF0000 +#define IFS_T1_CLM_C 0x1AE4 +#define IFS_T1_CLM_C_M 0xFFFF +#define IFS_T2_CLM_C 0x1AE4 +#define IFS_T2_CLM_C_M 0xFFFF0000 +#define IFS_T3_CLM_C 0x1AE8 +#define IFS_T3_CLM_C_M 0xFFFF +#define IFS_T4_CLM_C 0x1AE8 +#define IFS_T4_CLM_C_M 0xFFFF0000 +#define IFS_TOTAL_C 0x1AEC +#define IFS_TOTAL_C_M 0xFFFF +#define IFSCNT_DONE_C 0x1AEC +#define IFSCNT_DONE_C_M 0x10000 +#define IFS_COUNTING_C 0x1AEC +#define IFS_COUNTING_C_M 0x20000 +#define STS_KEEPER_DATA_C 0x1AF0 +#define STS_KEEPER_DATA_C_M 0xFFFFFFFF +#define PERIOD_S1_C 0x1AF4 +#define PERIOD_S1_C_M 0xFFFF +#define PERIOD_S2_C 0x1AF4 +#define PERIOD_S2_C_M 0xFFFF0000 +#define PERIOD_S3_C 0x1AF8 +#define PERIOD_S3_C_M 0xFFFF +#define PERIOD_S4_C 0x1AF8 +#define PERIOD_S4_C_M 0xFFFF0000 +#define OFDM_CRC32_OK_OR_C 0x1AFC +#define OFDM_CRC32_OK_OR_C_M 0xFFFF +#define CNT_NO_DATA_RECEIVED_C 0x1AFC +#define CNT_NO_DATA_RECEIVED_C_M 0xFFFF0000 +#define CNT_HESU_ERR_SIG_A_CRC4_C 0x1B00 +#define CNT_HESU_ERR_SIG_A_CRC4_C_M 0xFFFF +#define CNT_HEERSU_ERR_SIG_A_CRC4_C 0x1B00 +#define CNT_HEERSU_ERR_SIG_A_CRC4_C_M 0xFFFF0000 +#define CNT_HEMU_ERR_SIG_A_CRC4_C 0x1B04 +#define CNT_HEMU_ERR_SIG_A_CRC4_C_M 0xFFFF +#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C 0x1B04 +#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C_M 0xFFFF0000 +#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C 0x1B08 +#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C_M 0xFFFF +#define CNT_HE_U0_ERR_BCC_MCS_C 0x1B08 +#define CNT_HE_U0_ERR_BCC_MCS_C_M 0xFFFF0000 +#define CNT_HE_U0_ERR_MCS_C 0x1B0C +#define CNT_HE_U0_ERR_MCS_C_M 0xFFFF +#define CNT_HE_U0_ERR_DCM_MCS_C 0x1B0C +#define CNT_HE_U0_ERR_DCM_MCS_C_M 0xFFFF0000 +#define MONITOR0_C 0x1B10 +#define MONITOR0_C_M 0xFFFFFFFF +#define MONITOR1_C 0x1B14 +#define MONITOR1_C_M 0xFFFFFFFF +#define CNT_TXINFO_TXTP_MATCH_C 0x1B18 +#define CNT_TXINFO_TXTP_MATCH_C_M 0xFFFF +#define CNT_RX_PMAC_CRC32_OK_USER0_C 0x1B1C +#define CNT_RX_PMAC_CRC32_OK_USER0_C_M 0xFFFF +#define CNT_RX_PMAC_CRC32_OK_USER1_C 0x1B1C +#define CNT_RX_PMAC_CRC32_OK_USER1_C_M 0xFFFF0000 +#define CNT_RX_PMAC_CRC32_OK_USER2_C 0x1B20 +#define CNT_RX_PMAC_CRC32_OK_USER2_C_M 0xFFFF +#define CNT_RX_PMAC_CRC32_OK_USER3_C 0x1B20 +#define CNT_RX_PMAC_CRC32_OK_USER3_C_M 0xFFFF0000 +#define CNT_PFD_STAGE2B_MISS_C 0x1B24 +#define CNT_PFD_STAGE2B_MISS_C_M 0xFF +#define CNT_PFD_STAGE2A_MISS_C 0x1B24 +#define CNT_PFD_STAGE2A_MISS_C_M 0xFF00 +#define CNT_PFD_STAGE0_MISS_C 0x1B24 +#define CNT_PFD_STAGE0_MISS_C_M 0xFF0000 +#define CNT_RX_IN_HT_DET_C 0x1B28 +#define CNT_RX_IN_HT_DET_C_M 0xFFFF +#define CNT_RX_IN_NHT_DET_C 0x1B28 +#define CNT_RX_IN_NHT_DET_C_M 0xFFFF0000 +#define CNT_RX_IN_HE_DET_C 0x1B2C +#define CNT_RX_IN_HE_DET_C_M 0xFFFF +#define CNT_RX_IN_VHT_DET_C 0x1B2C +#define CNT_RX_IN_VHT_DET_C_M 0xFFFF0000 +#define CNT_BRK_IN_HE_TB_C 0x1B30 +#define CNT_BRK_IN_HE_TB_C_M 0xFFFF +#define CNT_NEG_GI2_OFST_OCCUR_C 0x1B34 +#define CNT_NEG_GI2_OFST_OCCUR_C_M 0xFFFF +#define P0_L_TOT_PW_DBFS_RX0_C 0x1B38 +#define P0_L_TOT_PW_DBFS_RX0_C_M 0xFFF +#define P0_L_TOT_PW_DBFS_RX1_C 0x1B38 +#define P0_L_TOT_PW_DBFS_RX1_C_M 0xFFF000 +#define P0_ANT_GAIN_DBM_RX_0_C 0x1B3C +#define P0_ANT_GAIN_DBM_RX_0_C_M 0x3FF +#define P0_ANT_GAIN_DBM_RX_1_C 0x1B3C +#define P0_ANT_GAIN_DBM_RX_1_C_M 0xFFC00 +#define P0_PWINFO_RPL_DBM_TO_RPT_C 0x1B3C +#define P0_PWINFO_RPL_DBM_TO_RPT_C_M 0x1FF00000 +#define P0_TOT_PW_DBFS_RX0_C 0x1B40 +#define P0_TOT_PW_DBFS_RX0_C_M 0xFFF +#define P0_TOT_PW_DBFS_RX1_C 0x1B40 +#define P0_TOT_PW_DBFS_RX1_C_M 0xFFF000 +#define P0_RPL_COM_TERM_C 0x1B44 +#define P0_RPL_COM_TERM_C_M 0x3FFF +#define P0_TB_RSSI_COM_TERM_C 0x1B44 +#define P0_TB_RSSI_COM_TERM_C_M 0xFFFC000 +#define P0_L_TOT_PW_DBM_RX0_C 0x1B48 +#define P0_L_TOT_PW_DBM_RX0_C_M 0x1FFF +#define P0_L_TOT_PW_DBM_RX1_C 0x1B48 +#define P0_L_TOT_PW_DBM_RX1_C_M 0x3FFE000 +#define P0_TX_TD_CFO_C 0x1B4C +#define P0_TX_TD_CFO_C_M 0xFFF +#define IFS_T1_HIS_C 0x1B50 +#define IFS_T1_HIS_C_M 0xFFFF +#define IFS_T2_HIS_C 0x1B50 +#define IFS_T2_HIS_C_M 0xFFFF0000 +#define IFS_T3_HIS_C 0x1B54 +#define IFS_T3_HIS_C_M 0xFFFF +#define IFS_T4_HIS_C 0x1B54 +#define IFS_T4_HIS_C_M 0xFFFF0000 +#define PATH0_TSSI_DBG_PORT_C 0x1C00 +#define PATH0_TSSI_DBG_PORT_C_M 0xFFFFFFFF +#define PATH0_DCK_AUTO_AVG_DC_C 0x1C04 +#define PATH0_DCK_AUTO_AVG_DC_C_M 0xFFF000 +#define PATH0_HE_LSTF_PW_OFST_C 0x1C04 +#define PATH0_HE_LSTF_PW_OFST_C_M 0xFF000000 +#define PATH0_DCK_AUTO_MAX_DC_C 0x1C08 +#define PATH0_DCK_AUTO_MAX_DC_C_M 0xFFF +#define PATH0_DCK_AUTO_MIN_DC_C 0x1C08 +#define PATH0_DCK_AUTO_MIN_DC_C_M 0xFFF000 +#define PATH0_TMETER_F_C 0x1C08 +#define PATH0_TMETER_F_C_M 0xFF000000 +#define PATH0_TSSI_AVG_R_C 0x1C10 +#define PATH0_TSSI_AVG_R_C_M 0xFFF +#define PATH0_TSSI_MAX_R_C 0x1C10 +#define PATH0_TSSI_MAX_R_C_M 0xFFF000 +#define PATH0_TSSI_F_NOW_C 0x1C10 +#define PATH0_TSSI_F_NOW_C_M 0xFF000000 +#define PATH0_TSSI_MID_R_C 0x1C14 +#define PATH0_TSSI_MID_R_C_M 0xFFF +#define PATH0_TSSI_LAST_R_C 0x1C14 +#define PATH0_TSSI_LAST_R_C_M 0xFFF000 +#define PATH0_GAIN_TX_IPA_MX_C 0x1C14 +#define PATH0_GAIN_TX_IPA_MX_C_M 0x7000000 +#define PATH0_TSSI_VAL_AVG_C 0x1C18 +#define PATH0_TSSI_VAL_AVG_C_M 0x3FF +#define PATH0_TSSI_VAL_AVG_OUT_VLD_C 0x1C18 +#define PATH0_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000 +#define PATH0_ADC_RE_C 0x1C18 +#define PATH0_ADC_RE_C_M 0xFFF00000 +#define PATH0_TSSI_VAL_D00_C 0x1C1C +#define PATH0_TSSI_VAL_D00_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_0_C 0x1C1C +#define PATH0_TSSI_VAL_VLD_IDX_0_C_M 0x8000 +#define PATH0_TSSI_VAL_D01_C 0x1C1C +#define PATH0_TSSI_VAL_D01_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_1_C 0x1C1C +#define PATH0_TSSI_VAL_VLD_IDX_1_C_M 0x80000000 +#define PATH0_TSSI_VAL_D02_C 0x1C20 +#define PATH0_TSSI_VAL_D02_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_2_C 0x1C20 +#define PATH0_TSSI_VAL_VLD_IDX_2_C_M 0x8000 +#define PATH0_TSSI_VAL_D03_C 0x1C20 +#define PATH0_TSSI_VAL_D03_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_3_C 0x1C20 +#define PATH0_TSSI_VAL_VLD_IDX_3_C_M 0x80000000 +#define PATH0_TSSI_VAL_D04_C 0x1C24 +#define PATH0_TSSI_VAL_D04_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_4_C 0x1C24 +#define PATH0_TSSI_VAL_VLD_IDX_4_C_M 0x8000 +#define PATH0_TSSI_VAL_D05_C 0x1C24 +#define PATH0_TSSI_VAL_D05_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_5_C 0x1C24 +#define PATH0_TSSI_VAL_VLD_IDX_5_C_M 0x80000000 +#define PATH0_TSSI_VAL_D06_C 0x1C28 +#define PATH0_TSSI_VAL_D06_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_6_C 0x1C28 +#define PATH0_TSSI_VAL_VLD_IDX_6_C_M 0x8000 +#define PATH0_TSSI_VAL_D07_C 0x1C28 +#define PATH0_TSSI_VAL_D07_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_7_C 0x1C28 +#define PATH0_TSSI_VAL_VLD_IDX_7_C_M 0x80000000 +#define PATH0_TSSI_VAL_D08_C 0x1C2C +#define PATH0_TSSI_VAL_D08_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_8_C 0x1C2C +#define PATH0_TSSI_VAL_VLD_IDX_8_C_M 0x8000 +#define PATH0_TSSI_VAL_D09_C 0x1C2C +#define PATH0_TSSI_VAL_D09_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_9_C 0x1C2C +#define PATH0_TSSI_VAL_VLD_IDX_9_C_M 0x80000000 +#define PATH0_TSSI_VAL_D10_C 0x1C30 +#define PATH0_TSSI_VAL_D10_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_10_C 0x1C30 +#define PATH0_TSSI_VAL_VLD_IDX_10_C_M 0x8000 +#define PATH0_TSSI_VAL_D11_C 0x1C30 +#define PATH0_TSSI_VAL_D11_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_11_C 0x1C30 +#define PATH0_TSSI_VAL_VLD_IDX_11_C_M 0x80000000 +#define PATH0_TSSI_VAL_D12_C 0x1C34 +#define PATH0_TSSI_VAL_D12_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_12_C 0x1C34 +#define PATH0_TSSI_VAL_VLD_IDX_12_C_M 0x8000 +#define PATH0_TSSI_VAL_D13_C 0x1C34 +#define PATH0_TSSI_VAL_D13_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_13_C 0x1C34 +#define PATH0_TSSI_VAL_VLD_IDX_13_C_M 0x80000000 +#define PATH0_TSSI_VAL_D14_C 0x1C38 +#define PATH0_TSSI_VAL_D14_C_M 0x3FF +#define PATH0_TSSI_VAL_VLD_IDX_14_C 0x1C38 +#define PATH0_TSSI_VAL_VLD_IDX_14_C_M 0x8000 +#define PATH0_TSSI_VAL_D15_C 0x1C38 +#define PATH0_TSSI_VAL_D15_C_M 0x3FF0000 +#define PATH0_TSSI_VAL_VLD_IDX_15_C 0x1C38 +#define PATH0_TSSI_VAL_VLD_IDX_15_C_M 0x80000000 +#define PATH0_TSSI_OSCILLATION_CNT_C 0x1C3C +#define PATH0_TSSI_OSCILLATION_CNT_C_M 0xFFFF +#define PATH0_TSSI_VAL_VLD_IDX_C 0x1C3C +#define PATH0_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000 +#define PATH0_PRE_TXAGC_OFST_C 0x1C40 +#define PATH0_PRE_TXAGC_OFST_C_M 0xFF00 +#define PATH0_DELTA_TSSI_PW_C 0x1C40 +#define PATH0_DELTA_TSSI_PW_C_M 0xFF0000 +#define PATH0SWING_MIN_C 0x1C40 +#define PATH0SWING_MIN_C_M 0xF000000 +#define PATH0SWING_MAX_C 0x1C40 +#define PATH0SWING_MAX_C_M 0xF0000000 +#define PATH0_TSSI_C_RAW0_C 0x1C44 +#define PATH0_TSSI_C_RAW0_C_M 0x1FF000 +#define PATH0_TSSI_F_C 0x1C48 +#define PATH0_TSSI_F_C_M 0xFF +#define PATH0_TSSI_G_C 0x1C48 +#define PATH0_TSSI_G_C_M 0x3FF00 +#define PATH0_TSSI_S_C 0x1C48 +#define PATH0_TSSI_S_C_M 0x1FF00000 +#define PATH0_AVG_R_SQUARE_C 0x1C4C +#define PATH0_AVG_R_SQUARE_C_M 0xFFFFFF +#define PATH0_TSSI_F_RDY_C 0x1C4C +#define PATH0_TSSI_F_RDY_C_M 0x20000000 +#define PATH0_TSSI_G_RDY_C 0x1C4C +#define PATH0_TSSI_G_RDY_C_M 0x40000000 +#define PATH0_TSSI_C_RDY_C 0x1C4C +#define PATH0_TSSI_C_RDY_C_M 0x80000000 +#define PATH0_IN_R_SQUARE_MAX_C 0x1C50 +#define PATH0_IN_R_SQUARE_MAX_C_M 0xFFFFFF +#define PATH0_SPEC_IDX_C 0x1C50 +#define PATH0_SPEC_IDX_C_M 0x7000000 +#define PATH0_IN_R_SQUARE_MIN_C 0x1C54 +#define PATH0_IN_R_SQUARE_MIN_C_M 0xFFFFFF +#define PATH0_AVG_R_RMS_C 0x1C58 +#define PATH0_AVG_R_RMS_C_M 0xFFF +#define PATH0_AVG_R_RMS_RDY_C 0x1C58 +#define PATH0_AVG_R_RMS_RDY_C_M 0x80000000 +#define PATH0_DAC_GAIN_COMP_TBL_IDX_C 0x1C5C +#define PATH0_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF +#define PATH0_DAC_GAIN_COMP_DBG_C 0x1C5C +#define PATH0_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00 +#define PATH0_TXAGC_RF_C 0x1C60 +#define PATH0_TXAGC_RF_C_M 0x3F +#define PATH0_TSSI_OFST_C 0x1C60 +#define PATH0_TSSI_OFST_C_M 0x1F00 +#define PATH0_TXAGC_C 0x1C60 +#define PATH0_TXAGC_C_M 0xFF0000 +#define PATH0_TXAGC_ORIG_C 0x1C64 +#define PATH0_TXAGC_ORIG_C_M 0x1FF +#define PATH0_TXAGC_ORIG_RAW_C 0x1C64 +#define PATH0_TXAGC_ORIG_RAW_C_M 0x1FF000 +#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C 0x1C64 +#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000 +#define PATH0_TXAGC_TO_TSSI_CW_RPT_C 0x1C68 +#define PATH0_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF +#define PATH0_TSSI_C_RAW1_C 0x1C6C +#define PATH0_TSSI_C_RAW1_C_M 0x1FF +#define PATH0_DAC_GAIN_COMP_MX_C 0x1C70 +#define PATH0_DAC_GAIN_COMP_MX_C_M 0xFF0000 +#define PATH0_TSSI_CW_COMP_MX_C 0x1C70 +#define PATH0_TSSI_CW_COMP_MX_C_M 0xFF000000 +#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x1C74 +#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF +#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x1C74 +#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000 +#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74 +#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000 +#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74 +#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000 +#define PATH0_RFC_PREAMLE_PW_TYPE_C 0x1C74 +#define PATH0_RFC_PREAMLE_PW_TYPE_C_M 0x70000000 +#define PATH0_TXPW_C 0x1C78 +#define PATH0_TXPW_C_M 0x1FF +#define PATH0_TXAGCSWING_C 0x1C78 +#define PATH0_TXAGCSWING_C_M 0x1E00 +#define PATH0_HE_ER_SU_EN_C 0x1C78 +#define PATH0_HE_ER_SU_EN_C_M 0x2000 +#define PATH0_HE_TB_EN_C 0x1C78 +#define PATH0_HE_TB_EN_C_M 0x4000 +#define PATH0_CCK_PPDU_C 0x1C78 +#define PATH0_CCK_PPDU_C_M 0x8000 +#define PATH0_TXINFO_CH_WITH_DATA_C 0x1C78 +#define PATH0_TXINFO_CH_WITH_DATA_C_M 0xFF0000 +#define PATH0_TXSC_C 0x1C78 +#define PATH0_TXSC_C_M 0xF000000 +#define PATH0_RF_BW_IDX_C 0x1C78 +#define PATH0_RF_BW_IDX_C_M 0x30000000 +#define PATH0_ISOFDM_PREAMBLE_C 0x1C78 +#define PATH0_ISOFDM_PREAMBLE_C_M 0x40000000 +#define PATH0_ISCCK_PREAMBLE_C 0x1C78 +#define PATH0_ISCCK_PREAMBLE_C_M 0x80000000 +#define PATH0_TXAGC_OFST_MX_C 0x1C7C +#define PATH0_TXAGC_OFST_MX_C_M 0xFF +#define PATH0_TXAGC_OFST_C 0x1C7C +#define PATH0_TXAGC_OFST_C_M 0xFF00 +#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C 0x1C7C +#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000 +#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x1C7C +#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000 +#define PATH0_BYPASS_TSSI_BY_C_C 0x1C7C +#define PATH0_BYPASS_TSSI_BY_C_C_M 0x40000 +#define PATH0_ADC_VARIATION_C 0x1C7C +#define PATH0_ADC_VARIATION_C_M 0xFFF00000 +#define PATH0_DBG_IQK_PATH_C 0x1C80 +#define PATH0_DBG_IQK_PATH_C_M 0xFFFFFFFF +#define PATH0_FTM_RFLBK_BYPASS_C 0x1C84 +#define PATH0_FTM_RFLBK_BYPASS_C_M 0x1 +#define PATH0_FTM_LBK_BYPASS_C 0x1C84 +#define PATH0_FTM_LBK_BYPASS_C_M 0x2 +#define PATH0_FTM_A2A_AFELBK_BYPASS_C 0x1C84 +#define PATH0_FTM_A2A_AFELBK_BYPASS_C_M 0x4 +#define PATH0_GNT_BT_TX_BYPASS_C 0x1C84 +#define PATH0_GNT_BT_TX_BYPASS_C_M 0x8 +#define PATH0_GNT_BT_BYPASS_C 0x1C84 +#define PATH0_GNT_BT_BYPASS_C_M 0x10 +#define PATH0_GNT_WL_BYPASS_C 0x1C84 +#define PATH0_GNT_WL_BYPASS_C_M 0x20 +#define PATH0_LTE_RX_BYPASS_C 0x1C84 +#define PATH0_LTE_RX_BYPASS_C_M 0x40 +#define PATH0_TSSI_BYPASS_TXPW_MIN_C 0x1C84 +#define PATH0_TSSI_BYPASS_TXPW_MIN_C_M 0x80 +#define PATH0_TSSI_BYPASS_TXPW_MAX_C 0x1C84 +#define PATH0_TSSI_BYPASS_TXPW_MAX_C_M 0x100 +#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200 +#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400 +#define PATH0_BYPASS_TSSI_BY_RATE_HT_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HT_C_M 0x800 +#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000 +#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000 +#define PATH0_BYPASS_TSSI_BY_TXBF_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_TXBF_C_M 0x80000 +#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x1C84 +#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000 +#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x1C84 +#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000 +#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x1C84 +#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000 +#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x1C84 +#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000 +#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x1C84 +#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000 +#define PATH0_BYPASS_TSSI_C 0x1C84 +#define PATH0_BYPASS_TSSI_C_M 0x80000000 +#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C 0x1C88 +#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF +#define PATH0_DIGI_AGC_C 0x1C88 +#define PATH0_DIGI_AGC_C_M 0x3FF0 +#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x1C88 +#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000 +#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x1C88 +#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000 +#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C 0x1C88 +#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000 +#define PATH0_RX_CFIR_TAP_DEC_C 0x1C88 +#define PATH0_RX_CFIR_TAP_DEC_C_M 0x40000000 +#define PATH0_CLK_HIGH_RATE_MX_C 0x1C88 +#define PATH0_CLK_HIGH_RATE_MX_C_M 0x80000000 +#define PATH0_CFIR_OUT_IM_DBG_C 0x1C8C +#define PATH0_CFIR_OUT_IM_DBG_C_M 0xFFF +#define PATH0_CFIR_OUT_RE_DBG_C 0x1C8C +#define PATH0_CFIR_OUT_RE_DBG_C_M 0xFFF000 +#define PATH0_EN_RX_CFIR_C 0x1C8C +#define PATH0_EN_RX_CFIR_C_M 0x1000000 +#define PATH0_CLK_HIGH_RATE_C 0x1C8C +#define PATH0_CLK_HIGH_RATE_C_M 0x2000000 +#define PATH0_EN_TX_CFIR_C 0x1C8C +#define PATH0_EN_TX_CFIR_C_M 0x4000000 +#define PATH0_TX_CCK_IND_C 0x1C8C +#define PATH0_TX_CCK_IND_C_M 0x8000000 +#define PATH0_CFIR_IN_IM_DBG_C 0x1C90 +#define PATH0_CFIR_IN_IM_DBG_C_M 0xFFF +#define PATH0_CFIR_IN_RE_DBG_C 0x1C90 +#define PATH0_CFIR_IN_RE_DBG_C_M 0xFFF000 +#define PATH0_CCK_CCA_C 0x1C90 +#define PATH0_CCK_CCA_C_M 0x80000000 +#define PATH0_RX_C 0x1C94 +#define PATH0_RX_C_M 0x1F +#define PATH0_LNA_SETTING_C 0x1C94 +#define PATH0_LNA_SETTING_C_M 0x700 +#define PATH0_TIA_C 0x1C94 +#define PATH0_TIA_C_M 0x1000 +#define PATH0_DB2FLT_O_C 0x1C94 +#define PATH0_DB2FLT_O_C_M 0x7FF8000 +#define PATH0_LSTF_SUM_LINEAR_PW_C 0x1C98 +#define PATH0_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF +#define PATH0_LSTF_MAX_LINEAR_PW_C 0x1C9C +#define PATH0_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF +#define PATH0_TSSI_C_C 0x1CA0 +#define PATH0_TSSI_C_C_M 0x1FF +#define PATH0_TSSI_C_SRC_C 0x1CA0 +#define PATH0_TSSI_C_SRC_C_M 0x3FF000 +#define PATH0_TXAGC_TP_C 0x1CA0 +#define PATH0_TXAGC_TP_C_M 0xFF000000 +#define PATH0_LOG_VAL_O_C 0x1CA4 +#define PATH0_LOG_VAL_O_C_M 0xFFFFF +#define PATH0_TXAGC_OFST_ADJ_C 0x1CA4 +#define PATH0_TXAGC_OFST_ADJ_C_M 0xFF000000 +#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x1CA8 +#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF +#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x1CA8 +#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00 +#define PATH0_TMETER_TX_C 0x1CAC +#define PATH0_TMETER_TX_C_M 0x3F +#define PATH0_TMETER_CCA_POS_C 0x1CAC +#define PATH0_TMETER_CCA_POS_C_M 0x3F00 +#define PATH0_TMETER_CCA_NEG_C 0x1CAC +#define PATH0_TMETER_CCA_NEG_C_M 0x3F0000 +#define PATH0_AFE_ANAPAR_PW_O_C 0x1CB0 +#define PATH0_AFE_ANAPAR_PW_O_C_M 0xFF +#define PATH0_AFE_ANAPAR_CTRL_O_C 0x1CB0 +#define PATH0_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00 +#define PATH0_MUX_ST_PATH_C 0x1CB0 +#define PATH0_MUX_ST_PATH_C_M 0xF000000 +#define PATH0_TSSI_J_CCK_C 0x1CB4 +#define PATH0_TSSI_J_CCK_C_M 0x3FF +#define PATH0_TSSI_J_OFDM_C 0x1CB4 +#define PATH0_TSSI_J_OFDM_C_M 0xFFC00 +#define PATH0_TSSI_CURVE_C 0x1CB4 +#define PATH0_TSSI_CURVE_C_M 0x70000000 +#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C 0x1CB8 +#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF +#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C 0x1CB8 +#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000 +#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C 0x1E00 +#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF +#define PATH0_RO_SI_R_DATA_P_C 0x1E04 +#define PATH0_RO_SI_R_DATA_P_C_M 0xFFFFF +#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C 0x1E08 +#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7 +#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08 +#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38 +#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x1E08 +#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0 +#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08 +#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00 +#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C 0x1E08 +#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000 +#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C 0x1E08 +#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000 +#define PATH0_NRBW_AT_AGC_RDY_C 0x1E08 +#define PATH0_NRBW_AT_AGC_RDY_C_M 0x4000 +#define PATH0_TIA_SHRINK_AT_AGC_RDY_C 0x1E08 +#define PATH0_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000 +#define PATH0_P_DIFF_AT_AGC_RDY_C 0x1E08 +#define PATH0_P_DIFF_AT_AGC_RDY_C_M 0xFF0000 +#define PATH0_ELNA_IDX_AT_AGC_RDY_C 0x1E0C +#define PATH0_ELNA_IDX_AT_AGC_RDY_C_M 0x1 +#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2 +#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4 +#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8 +#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10 +#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20 +#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0 +#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000 +#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000 +#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000 +#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C +#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000 +#define PATH0_ELNA_IDX_AT_PD_HIT_C 0x1E10 +#define PATH0_ELNA_IDX_AT_PD_HIT_C_M 0x2 +#define PATH0_TIA_SAT_DET_AT_PD_HIT_C 0x1E10 +#define PATH0_TIA_SAT_DET_AT_PD_HIT_C_M 0x4 +#define PATH0_LNA_SAT_DET_AT_PD_HIT_C 0x1E10 +#define PATH0_LNA_SAT_DET_AT_PD_HIT_C_M 0x8 +#define PATH0_NRBW_AT_PD_HIT_C 0x1E10 +#define PATH0_NRBW_AT_PD_HIT_C_M 0x10 +#define PATH0_TIA_SHRINK_AT_PD_HIT_C 0x1E10 +#define PATH0_TIA_SHRINK_AT_PD_HIT_C_M 0x20 +#define PATH0_P_DIFF_AT_PD_HIT_C 0x1E10 +#define PATH0_P_DIFF_AT_PD_HIT_C_M 0x7FC0 +#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C 0x1E10 +#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000 +#define PATH0_RXIDX_AT_PD_HIT_C 0x1E10 +#define PATH0_RXIDX_AT_PD_HIT_C_M 0xF800000 +#define PATH0_TIA_IDX_AT_PD_HIT_C 0x1E10 +#define PATH0_TIA_IDX_AT_PD_HIT_C_M 0x10000000 +#define PATH0_LNA_IDX_AT_PD_HIT_C 0x1E10 +#define PATH0_LNA_IDX_AT_PD_HIT_C_M 0xE0000000 +#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2 +#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4 +#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8 +#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10 +#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20 +#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0 +#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000 +#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000 +#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000 +#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14 +#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000 +#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2 +#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4 +#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8 +#define PATH0_NRBW_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_NRBW_AT_NLGC_AGC_RDY_C_M 0x10 +#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20 +#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0 +#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000 +#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000 +#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000 +#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18 +#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000 +#define PATH0_RSSI_AT_AGC_RDY_C 0x1E1C +#define PATH0_RSSI_AT_AGC_RDY_C_M 0x3FF +#define PATH0_G_TOTAL_AT_AGC_RDY_C 0x1E1C +#define PATH0_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00 +#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C 0x1E1C +#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000 +#define PATH0_TIA_IDX_AT_AGC_RDY_C 0x1E1C +#define PATH0_TIA_IDX_AT_AGC_RDY_C_M 0x10000000 +#define PATH0_LNA_IDX_AT_AGC_RDY_C 0x1E1C +#define PATH0_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000 +#define PATH0_RSSI_ALWAYS_RUN_C 0x1E20 +#define PATH0_RSSI_ALWAYS_RUN_C_M 0x3FF +#define PATH0_TIA_SAT_DET_C 0x1E20 +#define PATH0_TIA_SAT_DET_C_M 0x400 +#define PATH0_LNA_SAT_DET_C 0x1E20 +#define PATH0_LNA_SAT_DET_C_M 0x800 +#define PATH0_NRBW_C 0x1E20 +#define PATH0_NRBW_C_M 0x1000 +#define PATH0_TIA_SHRINK_C 0x1E20 +#define PATH0_TIA_SHRINK_C_M 0x2000 +#define PATH0_G_LGC_DAGC_C 0x1E20 +#define PATH0_G_LGC_DAGC_C_M 0x3FC000 +#define PATH0_G_TOTAL_C 0x1E20 +#define PATH0_G_TOTAL_C_M 0xFFC00000 +#define PATH0_HW_SI_READ_DATA_C 0x1E24 +#define PATH0_HW_SI_READ_DATA_C_M 0xFFFFF +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x1E28 +#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800 +#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x1E2C +#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF +#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x1E2C +#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000 +#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C 0x1E30 +#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF +#define RFMOD_C 0x2000 +#define RFMOD_C_M 0x3 +#define DFS_MASK_RX_OPT_C 0x2000 +#define DFS_MASK_RX_OPT_C_M 0xC +#define DFS_MASK_TRANSIENT_OPT_C 0x2000 +#define DFS_MASK_TRANSIENT_OPT_C_M 0xF0 +#define PXP_SEL_SNR_C 0x2000 +#define PXP_SEL_SNR_C_M 0x3F00 +#define CH_INFO_TYPE_C 0x2000 +#define CH_INFO_TYPE_C_M 0x4000 +#define DFS_MASK_TRANSIENT_EN_C 0x2000 +#define DFS_MASK_TRANSIENT_EN_C_M 0x8000 +#define DFS_MASK_TRANSIENT_TH_C 0x2000 +#define DFS_MASK_TRANSIENT_TH_C_M 0xFF0000 +#define DFS_CHIRP_FLAG_ACC_TH_C 0x2000 +#define DFS_CHIRP_FLAG_ACC_TH_C_M 0xFF000000 +#define BIST_SEL_C 0x2004 +#define BIST_SEL_C_M 0x1F +#define TX_CKEN_BOTH_PATH_FORCE_VAL_C 0x2008 +#define TX_CKEN_BOTH_PATH_FORCE_VAL_C_M 0xF +#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C 0x2008 +#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C_M 0xF0 +#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C 0x2008 +#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C_M 0xF00 +#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C 0x2008 +#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C_M 0xF000 +#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C 0x2008 +#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C_M 0xF0000 +#define TX_CKEN_BOTH_PATH_FORCE_ON_C 0x2008 +#define TX_CKEN_BOTH_PATH_FORCE_ON_C_M 0x100000 +#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C 0x2008 +#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C_M 0x200000 +#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C 0x2008 +#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C_M 0x400000 +#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C 0x2008 +#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C_M 0x800000 +#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C 0x2008 +#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C_M 0x1000000 +#define CH_INFO_SEG_LEN_C 0x2008 +#define CH_INFO_SEG_LEN_C_M 0x6000000 +#define CH_INFO_MASK_OPT_C 0x2008 +#define CH_INFO_MASK_OPT_C_M 0x8000000 +#define BIST_RSTB_C 0x200C +#define BIST_RSTB_C_M 0x2 +#define TEST_RESUME_C 0x200C +#define TEST_RESUME_C_M 0x10 +#define BIST_VDDR_TEST_C 0x200C +#define BIST_VDDR_TEST_C_M 0x100 +#define BIST_EN_7_0__C 0x200C +#define BIST_EN_7_0__C_M 0xFF000000 +#define BIST_MOD_31_0__C 0x2010 +#define BIST_MOD_31_0__C_M 0xFFFFFFFF +#define BIST_MOD_63_32__C 0x2014 +#define BIST_MOD_63_32__C_M 0xFFFFFFFF +#define BIST_MOD_95_64__C 0x2018 +#define BIST_MOD_95_64__C_M 0xFFFFFFFF +#define BIST_MOD_127_96__C 0x201C +#define BIST_MOD_127_96__C_M 0xFFFFFFFF +#define BIST_MOD_159_128__C 0x2020 +#define BIST_MOD_159_128__C_M 0xFFFFFFFF +#define BIST_MOD_191_160__C 0x2024 +#define BIST_MOD_191_160__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_31_0__C 0x2028 +#define DRF_BIST_MOD_31_0__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_63_32__C 0x202C +#define DRF_BIST_MOD_63_32__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_95_64__C 0x2030 +#define DRF_BIST_MOD_95_64__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_127_96__C 0x2034 +#define DRF_BIST_MOD_127_96__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_159_128__C 0x2038 +#define DRF_BIST_MOD_159_128__C_M 0xFFFFFFFF +#define DRF_BIST_MOD_191_160__C 0x203C +#define DRF_BIST_MOD_191_160__C_M 0xFFFFFFFF +#define BIST_DVSE_31_0__C 0x2040 +#define BIST_DVSE_31_0__C_M 0xFFFFFFFF +#define BIST_DVSE_63_32__C 0x2044 +#define BIST_DVSE_63_32__C_M 0xFFFFFFFF +#define BIST_DVSE_95_64__C 0x2048 +#define BIST_DVSE_95_64__C_M 0xFFFFFFFF +#define BIST_DVSE_127_96__C 0x204C +#define BIST_DVSE_127_96__C_M 0xFFFFFFFF +#define BIST_DVSE_159_128__C 0x2050 +#define BIST_DVSE_159_128__C_M 0xFFFFFFFF +#define BIST_DVSE_191_160__C 0x2054 +#define BIST_DVSE_191_160__C_M 0xFFFFFFFF +#define BIST_DVS_31_0__C 0x2058 +#define BIST_DVS_31_0__C_M 0xFFFFFFFF +#define BIST_DVS_63_32__C 0x205C +#define BIST_DVS_63_32__C_M 0xFFFFFFFF +#define BIST_DVS_95_64__C 0x2060 +#define BIST_DVS_95_64__C_M 0xFFFFFFFF +#define BIST_DVS_127_96__C 0x2064 +#define BIST_DVS_127_96__C_M 0xFFFFFFFF +#define BIST_DVS_159_128__C 0x2068 +#define BIST_DVS_159_128__C_M 0xFFFFFFFF +#define BIST_DVS_191_160__C 0x206C +#define BIST_DVS_191_160__C_M 0xFFFFFFFF +#define BIST_TEST1_31_0__C 0x2070 +#define BIST_TEST1_31_0__C_M 0xFFFFFFFF +#define BIST_TEST1_63_32__C 0x2074 +#define BIST_TEST1_63_32__C_M 0xFFFFFFFF +#define BIST_TEST1_95_64__C 0x2078 +#define BIST_TEST1_95_64__C_M 0xFFFFFFFF +#define BIST_TEST1_127_96__C 0x207C +#define BIST_TEST1_127_96__C_M 0xFFFFFFFF +#define BIST_TEST1_159_128__C 0x2080 +#define BIST_TEST1_159_128__C_M 0xFFFFFFFF +#define BIST_TEST1_191_160__C 0x2084 +#define BIST_TEST1_191_160__C_M 0xFFFFFFFF +#define BIST_GRP_EN_31_0__C 0x2088 +#define BIST_GRP_EN_31_0__C_M 0xFFFFFFFF +#define BIST_GRP_EN_63_32__C 0x208C +#define BIST_GRP_EN_63_32__C_M 0xFFFFFFFF +#define LA_EN_C 0x2090 +#define LA_EN_C_M 0x1 +#define LA_DBGPORT_BASE_N_C 0x2090 +#define LA_DBGPORT_BASE_N_C_M 0x3E +#define LA_TYPEA_PATH_SEL_C 0x2090 +#define LA_TYPEA_PATH_SEL_C_M 0xC0 +#define LA_TYPEB_PATH_SEL_C 0x2090 +#define LA_TYPEB_PATH_SEL_C_M 0x300 +#define LA_TYPEC_PATH_SEL_C 0x2090 +#define LA_TYPEC_PATH_SEL_C_M 0xC00 +#define LA_TYPED_PATH_SEL_C 0x2090 +#define LA_TYPED_PATH_SEL_C_M 0x3000 +#define LA_TYPEA_SRC_SEL_C 0x2090 +#define LA_TYPEA_SRC_SEL_C_M 0x1C000 +#define LA_TYPEB_SRC_SEL_C 0x2090 +#define LA_TYPEB_SRC_SEL_C_M 0xE0000 +#define LA_TYPEC_SRC_SEL_C 0x2090 +#define LA_TYPEC_SRC_SEL_C_M 0x700000 +#define LA_TYPED_SRC_SEL_C 0x2090 +#define LA_TYPED_SRC_SEL_C_M 0x3800000 +#define LA_SMP_RT_SEL_C 0x2090 +#define LA_SMP_RT_SEL_C_M 0x1C000000 +#define LA_RDRDY_3PHASE_EN_C 0x2090 +#define LA_RDRDY_3PHASE_EN_C_M 0x20000000 +#define LA_EDGE_SEL_C 0x2090 +#define LA_EDGE_SEL_C_M 0x40000000 +#define LA_HDR_SEL_63_C 0x2094 +#define LA_HDR_SEL_63_C_M 0xF +#define LA_HDR_SEL_62_C 0x2094 +#define LA_HDR_SEL_62_C_M 0xF0 +#define LA_HDR_SEL_61_C 0x2094 +#define LA_HDR_SEL_61_C_M 0xF00 +#define LA_HDR_SEL_60_C 0x2094 +#define LA_HDR_SEL_60_C_M 0xF000 +#define LA_TYPEA_CK160_DLY_EN_C 0x2094 +#define LA_TYPEA_CK160_DLY_EN_C_M 0x10000 +#define LA_TYPEB_CK160_DLY_EN_C 0x2094 +#define LA_TYPEB_CK160_DLY_EN_C_M 0x20000 +#define LA_DBGPORT_SRC_SEL_C 0x2094 +#define LA_DBGPORT_SRC_SEL_C_M 0x40000 +#define LA_DATA_C 0x2094 +#define LA_DATA_C_M 0x1F80000 +#define LA_RDRDY_C 0x2094 +#define LA_RDRDY_C_M 0x6000000 +#define LA_IQSHFT_C 0x2094 +#define LA_IQSHFT_C_M 0x18000000 +#define LA_MONITOR_SEL_C 0x2094 +#define LA_MONITOR_SEL_C_M 0x60000000 +#define LA_SEL_P1_C 0x2094 +#define LA_SEL_P1_C_M 0x80000000 +#define LA_TRIG_C 0x2098 +#define LA_TRIG_C_M 0x1F +#define LA_TRIG_CNT_C 0x2098 +#define LA_TRIG_CNT_C_M 0x1FE0 +#define LA_TRIG_NEW_ONLY_C 0x2098 +#define LA_TRIG_NEW_ONLY_C_M 0x2000 +#define LA_TRIG_AND1_INV_C 0x2098 +#define LA_TRIG_AND1_INV_C_M 0x4000 +#define LA_TRIG_AND2_EN_C 0x2098 +#define LA_TRIG_AND2_EN_C_M 0x8000 +#define LA_TRIG_AND2_INV_C 0x2098 +#define LA_TRIG_AND2_INV_C_M 0x10000 +#define LA_TRIG_AND3_EN_C 0x2098 +#define LA_TRIG_AND3_EN_C_M 0x20000 +#define LA_TRIG_AND3_INV_C 0x2098 +#define LA_TRIG_AND3_INV_C_M 0x40000 +#define LA_TRIG_AND4_EN_C 0x2098 +#define LA_TRIG_AND4_EN_C_M 0x80000 +#define LA_TRIG_AND4_VAL_C 0x2098 +#define LA_TRIG_AND4_VAL_C_M 0x1FF00000 +#define LA_TRIG_AND4_INV_C 0x2098 +#define LA_TRIG_AND4_INV_C_M 0x20000000 +#define LA_TRIG_AND1_BIT_EN_C 0x209C +#define LA_TRIG_AND1_BIT_EN_C_M 0xFFFFFFFF +#define LA_TRIG_AND1_VAL_C 0x20A0 +#define LA_TRIG_AND1_VAL_C_M 0xFFFFFFFF +#define LA_TRIG_AND2_MASK_C 0x20A4 +#define LA_TRIG_AND2_MASK_C_M 0xFFFFFFFF +#define LA_TRIG_AND2_VAL_C 0x20A8 +#define LA_TRIG_AND2_VAL_C_M 0xFFFFFFFF +#define LA_TRIG_AND3_MASK_C 0x20AC +#define LA_TRIG_AND3_MASK_C_M 0xFFFFFFFF +#define LA_TRIG_AND3_VAL_C 0x20B0 +#define LA_TRIG_AND3_VAL_C_M 0xFFFFFFFF +#define LA_TRIG_AND5_C 0x20B4 +#define LA_TRIG_AND5_C_M 0xF +#define LA_TRIG_AND5_VAL_C 0x20B4 +#define LA_TRIG_AND5_VAL_C_M 0x1F0 +#define LA_TRIG_AND5_INV_C 0x20B4 +#define LA_TRIG_AND5_INV_C_M 0x200 +#define LA_TRIG_AND6_C 0x20B4 +#define LA_TRIG_AND6_C_M 0x3C00 +#define LA_TRIG_AND6_VAL_C 0x20B4 +#define LA_TRIG_AND6_VAL_C_M 0x7C000 +#define LA_TRIG_AND6_INV_C 0x20B4 +#define LA_TRIG_AND6_INV_C_M 0x80000 +#define LA_TRIG_AND7_C 0x20B4 +#define LA_TRIG_AND7_C_M 0xF00000 +#define LA_TRIG_AND7_VAL_C 0x20B4 +#define LA_TRIG_AND7_VAL_C_M 0x1F000000 +#define LA_TRIG_AND7_INV_C 0x20B4 +#define LA_TRIG_AND7_INV_C_M 0x20000000 +#define LA_M_AND1_EN_C 0x20B4 +#define LA_M_AND1_EN_C_M 0x40000000 +#define LA_M_AND2_EN_C 0x20B4 +#define LA_M_AND2_EN_C_M 0x80000000 +#define LA_DBG_EN_C 0x20B8 +#define LA_DBG_EN_C_M 0x1 +#define LA_DBG_POLARITY_C 0x20B8 +#define LA_DBG_POLARITY_C_M 0x2 +#define LA_DBG_TRIG_SEL_C 0x20B8 +#define LA_DBG_TRIG_SEL_C_M 0xFC +#define LA_DBG_INTERVAL_C 0x20B8 +#define LA_DBG_INTERVAL_C_M 0x700 +#define LA_DBG_SEL_0_C 0x20B8 +#define LA_DBG_SEL_0_C_M 0x7FF800 +#define LA_M_AND0_SEL_C 0x20B8 +#define LA_M_AND0_SEL_C_M 0x3800000 +#define LA_M_AND0_EN_C 0x20B8 +#define LA_M_AND0_EN_C_M 0x4000000 +#define LA_SIGN2_C 0x20B8 +#define LA_SIGN2_C_M 0x18000000 +#define LA_SIGN3_C 0x20B8 +#define LA_SIGN3_C_M 0x60000000 +#define LA_DBG_SEL_1_C 0x20BC +#define LA_DBG_SEL_1_C_M 0xFFF +#define LA_DBG_SEL_2_C 0x20BC +#define LA_DBG_SEL_2_C_M 0xFFF000 +#define LA_DBG_SEL_3_C 0x20C0 +#define LA_DBG_SEL_3_C_M 0xFFF +#define LA_DBG_SEL_4_C 0x20C0 +#define LA_DBG_SEL_4_C_M 0xFFF000 +#define WIFI_LOC_P1_C 0x20C0 +#define WIFI_LOC_P1_C_M 0xFF000000 +#define LA_DBG_SEL_5_C 0x20C4 +#define LA_DBG_SEL_5_C_M 0xFFF +#define LA_DBG_SEL_6_C 0x20C4 +#define LA_DBG_SEL_6_C_M 0xFFF000 +#define WIFI_LOC_C 0x20C4 +#define WIFI_LOC_C_M 0xFF000000 +#define LA_DBG_SEL_7_C 0x20C8 +#define LA_DBG_SEL_7_C_M 0xFFF +#define LA_RE_INIT_POLARITY_C 0x20C8 +#define LA_RE_INIT_POLARITY_C_M 0x1000 +#define LA_RE_INIT_AND1_C 0x20C8 +#define LA_RE_INIT_AND1_C_M 0x1E000 +#define LA_RE_INIT_AND1_VAL_C 0x20C8 +#define LA_RE_INIT_AND1_VAL_C_M 0x3E0000 +#define LA_RE_INIT_AND1_INV_C 0x20C8 +#define LA_RE_INIT_AND1_INV_C_M 0x400000 +#define PSD_DD_OPT_C 0x20C8 +#define PSD_DD_OPT_C_M 0xFF800000 +#define EDCCA_RPTREG_SEL_P0_C 0x20CC +#define EDCCA_RPTREG_SEL_P0_C_M 0x7 +#define EDCCA_RPTREG_SEL_P1_C 0x20CC +#define EDCCA_RPTREG_SEL_P1_C_M 0x38 +#define FTM_C 0x20CC +#define FTM_C_M 0xFF0000 +#define DIS_IOQ_RFC_C 0x20D0 +#define DIS_IOQ_RFC_C_M 0x1 +#define DIS_IOQ_AFE_C 0x20D0 +#define DIS_IOQ_AFE_C_M 0x2 +#define BT_WL_RF_MODEAGH_C 0x20D0 +#define BT_WL_RF_MODEAGH_C_M 0xC +#define FTM_T_LBK_FORCE_EN_C 0x20D0 +#define FTM_T_LBK_FORCE_EN_C_M 0x2000 +#define FTM_T_LBK_FORCE_VAL_C 0x20D0 +#define FTM_T_LBK_FORCE_VAL_C_M 0xFFFFC000 +#define MAC0_PIN_SEL_C 0x20D4 +#define MAC0_PIN_SEL_C_M 0xFFFF +#define MAC1_PIN_SEL_C 0x20D4 +#define MAC1_PIN_SEL_C_M 0xFFFF0000 +#define PWDB_CNT_TH_P0_C 0x20D8 +#define PWDB_CNT_TH_P0_C_M 0xFF +#define PWDB_CNT_TH_P1_C 0x20D8 +#define PWDB_CNT_TH_P1_C_M 0xFF00 +#define LBK_SEL_C 0x20EC +#define LBK_SEL_C_M 0x7 +#define MUX_ST_BYPASS_TXEN_C 0x20EC +#define MUX_ST_BYPASS_TXEN_C_M 0x10 +#define DUMMY_P09_EC_C 0x20EC +#define DUMMY_P09_EC_C_M 0xFFFFFFE0 +#define DBG_PORT_SEL_C 0x20F0 +#define DBG_PORT_SEL_C_M 0xFFFF +#define DBG_PORT_IP_SEL_C 0x20F0 +#define DBG_PORT_IP_SEL_C_M 0xFF0000 +#define DUMMY_P09_F0_C 0x20F0 +#define DUMMY_P09_F0_C_M 0xFF000000 +#define DBG_CNT_SEL_C 0x20F4 +#define DBG_CNT_SEL_C_M 0x1F +#define DUMMY_P09_F4_0_C 0x20F4 +#define DUMMY_P09_F4_0_C_M 0xE0 +#define DBG_PORT_REF_CLK_SEL_C 0x20F4 +#define DBG_PORT_REF_CLK_SEL_C_M 0xFF00 +#define DBG_PORT_REF_CLK_RATE_C 0x20F4 +#define DBG_PORT_REF_CLK_RATE_C_M 0xFF0000 +#define DBG_PORT_REF_CLK_EN_C 0x20F4 +#define DBG_PORT_REF_CLK_EN_C_M 0x1000000 +#define DBG32_UPD_SEL_C 0x20F4 +#define DBG32_UPD_SEL_C_M 0x6000000 +#define DBG_PORT_REF_CLK_SYNC_EN_C 0x20F4 +#define DBG_PORT_REF_CLK_SYNC_EN_C_M 0x8000000 +#define DUMMY_P09_F4_1_C 0x20F4 +#define DUMMY_P09_F4_1_C_M 0xF0000000 +#define DUMMY_P09_F8_C 0x20F8 +#define DUMMY_P09_F8_C_M 0x7FFFFFFF +#define DBG_PORT_EN_C 0x20F8 +#define DBG_PORT_EN_C_M 0x80000000 +#define DBG_PORT_CKEN_TOP_C 0x20FC +#define DBG_PORT_CKEN_TOP_C_M 0x1 +#define DBG_PORT_CKEN_TD_C 0x20FC +#define DBG_PORT_CKEN_TD_C_M 0x10 +#define DBG_PORT_CKEN_IN_C 0x20FC +#define DBG_PORT_CKEN_IN_C_M 0x100 +#define DBG_PORT_CKEN_OUT_C 0x20FC +#define DBG_PORT_CKEN_OUT_C_M 0x1000 +#define DA2AD_SEL_C 0x20FC +#define DA2AD_SEL_C_M 0x2000 +#define FORCE_DAC_FIFO_PATH_RST_ON_C 0x20FC +#define FORCE_DAC_FIFO_PATH_RST_ON_C_M 0xF0000 +#define FORCE_DAC_FIFO_PATH_RST_C 0x20FC +#define FORCE_DAC_FIFO_PATH_RST_C_M 0xF00000 +#define FORCE_ADC_FIFO_PATH_RST_ON_C 0x20FC +#define FORCE_ADC_FIFO_PATH_RST_ON_C_M 0xF000000 +#define FORCE_ADC_FIFO_PATH_RST_C 0x20FC +#define FORCE_ADC_FIFO_PATH_RST_C_M 0xF0000000 +#define TXBF_MEM_C 0x2214 +#define TXBF_MEM_C_M 0xFFFFFFFF +#define TXBF_MEM_DIN_C 0x2218 +#define TXBF_MEM_DIN_C_M 0xFFFFFFFF +#define TXBF_MEM_ADDR_C 0x221C +#define TXBF_MEM_ADDR_C_M 0xFFFFFFFF +#define TXBF_MEM_EN_C 0x2220 +#define TXBF_MEM_EN_C_M 0xFFFFFFFF +#define R1B_TX_FIR_COEF0_C 0x2300 +#define R1B_TX_FIR_COEF0_C_M 0xFFF +#define R1B_TX_FIR_COEF1_C 0x2300 +#define R1B_TX_FIR_COEF1_C_M 0xFFF000 +#define R1B_TX_FIR_SCALE_OPT_C 0x2300 +#define R1B_TX_FIR_SCALE_OPT_C_M 0x3000000 +#define R1B_TX_STOP_TX_C 0x2300 +#define R1B_TX_STOP_TX_C_M 0x4000000 +#define R1B_TX_BLOCK_TX_C 0x2300 +#define R1B_TX_BLOCK_TX_C_M 0x8000000 +#define R1B_TX_CONTINUOUS_TX_C 0x2300 +#define R1B_TX_CONTINUOUS_TX_C_M 0x10000000 +#define R1B_TX_TERMINATE_OPT_C 0x2300 +#define R1B_TX_TERMINATE_OPT_C_M 0xE0000000 +#define R1B_TX_FIR_COEF2_C 0x2304 +#define R1B_TX_FIR_COEF2_C_M 0xFFF +#define R1B_TX_FIR_COEF3_C 0x2304 +#define R1B_TX_FIR_COEF3_C_M 0xFFF000 +#define R1B_TX_DUMMY_TDRDY64_OPT_C 0x2304 +#define R1B_TX_DUMMY_TDRDY64_OPT_C_M 0x3000000 +#define R1B_TX_DIS_SCRAMBLER_C 0x2304 +#define R1B_TX_DIS_SCRAMBLER_C_M 0x4000000 +#define R1B_TX_IFMOD_5M_OPT_C 0x2304 +#define R1B_TX_IFMOD_5M_OPT_C_M 0x18000000 +#define R1B_TX_FIR_COEF4_C 0x2308 +#define R1B_TX_FIR_COEF4_C_M 0xFFF +#define R1B_TX_FIR_COEF5_C 0x2308 +#define R1B_TX_FIR_COEF5_C_M 0xFFF000 +#define R1B_TX_SCRAMBLER_OPT_C 0x2308 +#define R1B_TX_SCRAMBLER_OPT_C_M 0xFF000000 +#define R1B_TX_FIR_COEF6_C 0x230C +#define R1B_TX_FIR_COEF6_C_M 0xFFF +#define R1B_TX_FIR_COEF7_C 0x230C +#define R1B_TX_FIR_COEF7_C_M 0xFFF000 +#define R1B_TX_FORCE_PATH_EN_ON_C 0x230C +#define R1B_TX_FORCE_PATH_EN_ON_C_M 0x1000000 +#define R1B_TX_FORCE_PATH_EN_PATH0_C 0x230C +#define R1B_TX_FORCE_PATH_EN_PATH0_C_M 0x2000000 +#define R1B_TX_FORCE_PATH_EN_PATH1_C 0x230C +#define R1B_TX_FORCE_PATH_EN_PATH1_C_M 0x4000000 +#define R1B_TX_FORCE_PATH_EN_PATH2_C 0x230C +#define R1B_TX_FORCE_PATH_EN_PATH2_C_M 0x8000000 +#define R1B_TX_FORCE_PATH_EN_PATH3_C 0x230C +#define R1B_TX_FORCE_PATH_EN_PATH3_C_M 0x10000000 +#define R1B_TX_FIR_COEF8_C 0x2310 +#define R1B_TX_FIR_COEF8_C_M 0xFFF +#define R1B_TX_FIR_COEF9_C 0x2310 +#define R1B_TX_FIR_COEF9_C_M 0xFFF000 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C 0x2310 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C_M 0x3000000 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C 0x2310 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C_M 0xC000000 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C 0x2310 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C_M 0x30000000 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C 0x2310 +#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C_M 0xC0000000 +#define R1B_TX_FIR_COEFA_C 0x2314 +#define R1B_TX_FIR_COEFA_C_M 0xFFF +#define R1B_TX_FIR_COEFB_C 0x2314 +#define R1B_TX_FIR_COEFB_C_M 0xFFF000 +#define R1B_TX_NORM_FCTR_C 0x2314 +#define R1B_TX_NORM_FCTR_C_M 0x3F000000 +#define R1B_TX_FIR_COEFC_C 0x2318 +#define R1B_TX_FIR_COEFC_C_M 0xFFF +#define R1B_TX_FIR_COEFD_C 0x2318 +#define R1B_TX_FIR_COEFD_C_M 0xFFF000 +#define R1B_TX_FIR_COEFE_C 0x231C +#define R1B_TX_FIR_COEFE_C_M 0xFFF +#define R1B_TX_FIR_COEFF_C 0x231C +#define R1B_TX_FIR_COEFF_C_M 0xFFF000 +#define R1B_TX_PMAC_HEADER_0_C 0x2320 +#define R1B_TX_PMAC_HEADER_0_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_HEADER_1_C 0x2324 +#define R1B_TX_PMAC_HEADER_1_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_HEADER_2_C 0x2328 +#define R1B_TX_PMAC_HEADER_2_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_HEADER_3_C 0x232C +#define R1B_TX_PMAC_HEADER_3_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_HEADER_4_C 0x2330 +#define R1B_TX_PMAC_HEADER_4_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_HEADER_5_C 0x2334 +#define R1B_TX_PMAC_HEADER_5_C_M 0xFFFFFFFF +#define R1B_TX_PMAC_PSDU_BYTE_C 0x2338 +#define R1B_TX_PMAC_PSDU_BYTE_C_M 0x1FFFF +#define R1B_TX_PMAC_CONTINUOUS_TX_C 0x2338 +#define R1B_TX_PMAC_CONTINUOUS_TX_C_M 0x20000 +#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C 0x2338 +#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C_M 0x40000 +#define R1B_TX_PMAC_PPDU_TYPE_C 0x2338 +#define R1B_TX_PMAC_PPDU_TYPE_C_M 0x80000 +#define R1B_TX_PMAC_PSDU_RATE_C 0x2338 +#define R1B_TX_PMAC_PSDU_RATE_C_M 0x300000 +#define R1B_TX_PMAC_SERVICE_BIT2_C 0x2338 +#define R1B_TX_PMAC_SERVICE_BIT2_C_M 0x400000 +#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C 0x2338 +#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C_M 0x7F800000 +#define R1B_FPGA_LBK_EN_C 0x2338 +#define R1B_FPGA_LBK_EN_C_M 0x80000000 +#define R1B_RX_CS_RATIO_BW20_1R_C 0x233C +#define R1B_RX_CS_RATIO_BW20_1R_C_M 0x1F +#define R1B_RX_CS_RATIO_BW20_2R_C 0x233C +#define R1B_RX_CS_RATIO_BW20_2R_C_M 0x3E0 +#define R1B_RX_CS_RATIO_BW20_3R_C 0x233C +#define R1B_RX_CS_RATIO_BW20_3R_C_M 0x7C00 +#define R1B_RX_CS_RATIO_BW20_4R_C 0x233C +#define R1B_RX_CS_RATIO_BW20_4R_C_M 0xF8000 +#define R1B_RX_CCA_IN_SHIFT_C 0x233C +#define R1B_RX_CCA_IN_SHIFT_C_M 0x1E00000 +#define R1B_RX_PRECCA_WGT_EN_C 0x233C +#define R1B_RX_PRECCA_WGT_EN_C_M 0x2000000 +#define R1B_RX_FORCE_PRECCA_WGT_EN_C 0x233C +#define R1B_RX_FORCE_PRECCA_WGT_EN_C_M 0x4000000 +#define R1B_RX_CCA_SMEN_C 0x233C +#define R1B_RX_CCA_SMEN_C_M 0x8000000 +#define R1B_RX_MBC_RATIO_C 0x233C +#define R1B_RX_MBC_RATIO_C_M 0x30000000 +#define R1B_RX_MDC_RATIO_C 0x233C +#define R1B_RX_MDC_RATIO_C_M 0xC0000000 +#define R1B_RX_CS_RATIO_BW40_1R_C 0x2340 +#define R1B_RX_CS_RATIO_BW40_1R_C_M 0x1F +#define R1B_RX_CS_RATIO_BW40_2R_C 0x2340 +#define R1B_RX_CS_RATIO_BW40_2R_C_M 0x3E0 +#define R1B_RX_CS_RATIO_BW40_3R_C 0x2340 +#define R1B_RX_CS_RATIO_BW40_3R_C_M 0x7C00 +#define R1B_RX_CS_RATIO_BW40_4R_C 0x2340 +#define R1B_RX_CS_RATIO_BW40_4R_C_M 0xF8000 +#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C 0x2340 +#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C_M 0x700000 +#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C 0x2340 +#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C_M 0x3800000 +#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C 0x2340 +#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C_M 0x1C000000 +#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C 0x2340 +#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C_M 0xE0000000 +#define R1B_RX_DC_RATIO_BW20_1R_C 0x2344 +#define R1B_RX_DC_RATIO_BW20_1R_C_M 0x1F +#define R1B_RX_DC_RATIO_BW20_2R_C 0x2344 +#define R1B_RX_DC_RATIO_BW20_2R_C_M 0x3E0 +#define R1B_RX_DC_RATIO_BW20_3R_C 0x2344 +#define R1B_RX_DC_RATIO_BW20_3R_C_M 0x7C00 +#define R1B_RX_DC_RATIO_BW20_4R_C 0x2344 +#define R1B_RX_DC_RATIO_BW20_4R_C_M 0xF8000 +#define R1B_RX_FORCE_DC_CMP_EN_C 0x2344 +#define R1B_RX_FORCE_DC_CMP_EN_C_M 0x100000 +#define R1B_RX_FORCE_DC_CMP_C 0x2344 +#define R1B_RX_FORCE_DC_CMP_C_M 0x1FE00000 +#define R1B_RX_MBC_WIN_C 0x2344 +#define R1B_RX_MBC_WIN_C_M 0x60000000 +#define R1B_RX_DIS_CCA_C 0x2344 +#define R1B_RX_DIS_CCA_C_M 0x80000000 +#define R1B_RX_DC_RATIO_BW40_1R_C 0x2348 +#define R1B_RX_DC_RATIO_BW40_1R_C_M 0x1F +#define R1B_RX_DC_RATIO_BW40_2R_C 0x2348 +#define R1B_RX_DC_RATIO_BW40_2R_C_M 0x3E0 +#define R1B_RX_DC_RATIO_BW40_3R_C 0x2348 +#define R1B_RX_DC_RATIO_BW40_3R_C_M 0x7C00 +#define R1B_RX_DC_RATIO_BW40_4R_C 0x2348 +#define R1B_RX_DC_RATIO_BW40_4R_C_M 0xF8000 +#define R1B_RX_CCA_PIN_DET_OPT_C 0x2348 +#define R1B_RX_CCA_PIN_DET_OPT_C_M 0x100000 +#define R1B_RX_CCA_PIN_DET_TH_C 0x2348 +#define R1B_RX_CCA_PIN_DET_TH_C_M 0x1FE00000 +#define R1B_RX_CCS_MODE_C 0x2348 +#define R1B_RX_CCS_MODE_C_M 0xE0000000 +#define R1B_RX_PD_TH_BW20_1R_C 0x234C +#define R1B_RX_PD_TH_BW20_1R_C_M 0x1F +#define R1B_RX_PD_TH_BW20_2R_C 0x234C +#define R1B_RX_PD_TH_BW20_2R_C_M 0x3E0 +#define R1B_RX_PD_TH_BW20_3R_C 0x234C +#define R1B_RX_PD_TH_BW20_3R_C_M 0x7C00 +#define R1B_RX_PD_TH_BW20_4R_C 0x234C +#define R1B_RX_PD_TH_BW20_4R_C_M 0xF8000 +#define R1B_RX_FORCE_PD_CMP_EN_C 0x234C +#define R1B_RX_FORCE_PD_CMP_EN_C_M 0x100000 +#define R1B_RX_FORCE_PD_CMP_C 0x234C +#define R1B_RX_FORCE_PD_CMP_C_M 0x1FE00000 +#define R1B_RX_MF_OPT_C 0x234C +#define R1B_RX_MF_OPT_C_M 0xE0000000 +#define R1B_RX_PD_TH_BW40_1R_C 0x2350 +#define R1B_RX_PD_TH_BW40_1R_C_M 0x1F +#define R1B_RX_PD_TH_BW40_2R_C 0x2350 +#define R1B_RX_PD_TH_BW40_2R_C_M 0x3E0 +#define R1B_RX_PD_TH_BW40_3R_C 0x2350 +#define R1B_RX_PD_TH_BW40_3R_C_M 0x7C00 +#define R1B_RX_PD_TH_BW40_4R_C 0x2350 +#define R1B_RX_PD_TH_BW40_4R_C_M 0xF8000 +#define R1B_RX_FORCE_ANT_CCA_EN_C 0x2350 +#define R1B_RX_FORCE_ANT_CCA_EN_C_M 0x100000 +#define R1B_RX_FORCE_ANT_CCA_PATH0_C 0x2350 +#define R1B_RX_FORCE_ANT_CCA_PATH0_C_M 0x200000 +#define R1B_RX_FORCE_ANT_CCA_PATH1_C 0x2350 +#define R1B_RX_FORCE_ANT_CCA_PATH1_C_M 0x400000 +#define R1B_RX_FORCE_ANT_CCA_PATH2_C 0x2350 +#define R1B_RX_FORCE_ANT_CCA_PATH2_C_M 0x800000 +#define R1B_RX_FORCE_ANT_CCA_PATH3_C 0x2350 +#define R1B_RX_FORCE_ANT_CCA_PATH3_C_M 0x1000000 +#define R1B_RX_CCA_TRIG_DLY_C 0x2350 +#define R1B_RX_CCA_TRIG_DLY_C_M 0x1E000000 +#define R1B_RX_NULL_POINT_IDX_OFST_C 0x2350 +#define R1B_RX_NULL_POINT_IDX_OFST_C_M 0xE0000000 +#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C 0x2354 +#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C_M 0x1F +#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C 0x2354 +#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C_M 0x3E0 +#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C 0x2354 +#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C_M 0x7C00 +#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C 0x2354 +#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C_M 0xF8000 +#define R1B_RX_BTTX_CCA_TH_EN_C 0x2354 +#define R1B_RX_BTTX_CCA_TH_EN_C_M 0x80000000 +#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C 0x2358 +#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C_M 0x1F +#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C 0x2358 +#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C_M 0x3E0 +#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C 0x2358 +#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C_M 0x7C00 +#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C 0x2358 +#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C_M 0xF8000 +#define R1B_RX_CCA_DIS_5M_EN_C 0x2358 +#define R1B_RX_CCA_DIS_5M_EN_C_M 0x100000 +#define R1B_RX_CCA_DIS_TB_OFF_C 0x2358 +#define R1B_RX_CCA_DIS_TB_OFF_C_M 0x200000 +#define R1B_RX_CCA_DIS_NDP_OFF_C 0x2358 +#define R1B_RX_CCA_DIS_NDP_OFF_C_M 0x400000 +#define R1B_RX_DAGC_TARGET_LVL_C 0x235C +#define R1B_RX_DAGC_TARGET_LVL_C_M 0x1F +#define R1B_RX_DAGC_MIN_VAL_C 0x235C +#define R1B_RX_DAGC_MIN_VAL_C_M 0x3E0 +#define R1B_RX_DAGC_MAX_VAL_C 0x235C +#define R1B_RX_DAGC_MAX_VAL_C_M 0x7C00 +#define R1B_RX_DAGC_STANDBY_OPT_C 0x235C +#define R1B_RX_DAGC_STANDBY_OPT_C_M 0xF8000 +#define R1B_RX_DAGC_FORCE_VAL_C 0x235C +#define R1B_RX_DAGC_FORCE_VAL_C_M 0x1F00000 +#define R1B_RX_DAGC_FORCE_EN_C 0x235C +#define R1B_RX_DAGC_FORCE_EN_C_M 0x2000000 +#define R1B_RX_DAGC_EN_C 0x235C +#define R1B_RX_DAGC_EN_C_M 0x4000000 +#define R1B_RX_DAGC_OPT_C 0x235C +#define R1B_RX_DAGC_OPT_C_M 0x8000000 +#define R1B_RX_DAGC_TWO_STAGE_EN_C 0x235C +#define R1B_RX_DAGC_TWO_STAGE_EN_C_M 0x10000000 +#define R1B_RX_SBD_SYMBOL_OPT_C 0x2360 +#define R1B_RX_SBD_SYMBOL_OPT_C_M 0x3 +#define R1B_RX_SBD_SMOOTH_EN_C 0x2360 +#define R1B_RX_SBD_SMOOTH_EN_C_M 0x4 +#define R1B_RX_SBD_SQUARE_EN_C 0x2360 +#define R1B_RX_SBD_SQUARE_EN_C_M 0x8 +#define R1B_RX_SBD_FINE_TUNE_OPT_C 0x2360 +#define R1B_RX_SBD_FINE_TUNE_OPT_C_M 0x30 +#define R1B_RX_SBD_FINE_TUNE_MODE_C 0x2360 +#define R1B_RX_SBD_FINE_TUNE_MODE_C_M 0xC0 +#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C 0x2360 +#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C_M 0xFF00 +#define R1B_RX_DAGC_TO_SBD_C 0x2360 +#define R1B_RX_DAGC_TO_SBD_C_M 0x3F0000 +#define R1B_RX_SBD_MODE_C 0x2360 +#define R1B_RX_SBD_MODE_C_M 0x400000 +#define R1B_RX_SBD_ANALYZER_EN_C 0x2360 +#define R1B_RX_SBD_ANALYZER_EN_C_M 0x800000 +#define R1B_RX_SBD_SMOOTH_FCTR_C 0x2360 +#define R1B_RX_SBD_SMOOTH_FCTR_C_M 0x3000000 +#define R1B_RX_SBD_ANALYZER_OPT_C 0x2360 +#define R1B_RX_SBD_ANALYZER_OPT_C_M 0x4000000 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C_M 0x1F +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C_M 0x3E0 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C_M 0x7C00 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C_M 0xF8000 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C_M 0x1F00000 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C 0x2364 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C_M 0x3E000000 +#define R1B_RX_ANT_WGT_EN_C 0x2364 +#define R1B_RX_ANT_WGT_EN_C_M 0x40000000 +#define R1B_RX_ANT_WGT_MODE_C 0x2364 +#define R1B_RX_ANT_WGT_MODE_C_M 0x80000000 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C 0x2368 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C_M 0x1F +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C 0x2368 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C_M 0x3E0 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C 0x2368 +#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C_M 0x7C00 +#define R1B_RX_RSSI_HIGH_PIN_TH_C 0x2368 +#define R1B_RX_RSSI_HIGH_PIN_TH_C_M 0x7F8000 +#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C 0x2368 +#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C_M 0x7F800000 +#define R1B_RX_ANT_WGT_EQUAL_EN_C 0x2368 +#define R1B_RX_ANT_WGT_EQUAL_EN_C_M 0x80000000 +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C 0x236C +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C_M 0x1FF +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C 0x236C +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C_M 0x3FE00 +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C 0x236C +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C_M 0x7FC0000 +#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C 0x236C +#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C_M 0x8000000 +#define R1B_RX_ANT_WGT_FORCE_EN_C 0x236C +#define R1B_RX_ANT_WGT_FORCE_EN_C_M 0x10000000 +#define R1B_RX_ANT_PW_SAVE_EN_C 0x236C +#define R1B_RX_ANT_PW_SAVE_EN_C_M 0x20000000 +#define R1B_RX_MRC_OPT_C 0x236C +#define R1B_RX_MRC_OPT_C_M 0xC0000000 +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C 0x2370 +#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C_M 0x1FF +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C 0x2370 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C_M 0x3FE00 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C 0x2370 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C_M 0x7FC0000 +#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C 0x2370 +#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C_M 0x78000000 +#define R1B_RX_I_ONLY_EN_C 0x2370 +#define R1B_RX_I_ONLY_EN_C_M 0x80000000 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C 0x2374 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C_M 0x1FF +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C 0x2374 +#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C_M 0x3FE00 +#define R1B_RX_RSSI_OFST_C 0x2374 +#define R1B_RX_RSSI_OFST_C_M 0x3FC0000 +#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C 0x2374 +#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C_M 0xC000000 +#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C 0x2374 +#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C_M 0x10000000 +#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C 0x2378 +#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C_M 0xFF +#define R1B_RX_LPF1_EN_C 0x2378 +#define R1B_RX_LPF1_EN_C_M 0x100 +#define R1B_RX_LPF1_MODE_BEFORE_CCA_C 0x2378 +#define R1B_RX_LPF1_MODE_BEFORE_CCA_C_M 0x600 +#define R1B_RX_LPF1_MODE_AFTER_CCA_C 0x2378 +#define R1B_RX_LPF1_MODE_AFTER_CCA_C_M 0x1800 +#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C 0x2378 +#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C_M 0xFF0000 +#define R1B_RX_INTP_UPD044_OPT_C 0x2378 +#define R1B_RX_INTP_UPD044_OPT_C_M 0x1F000000 +#define R1B_RX_INTP_SCO_DELAY_EN_C 0x2378 +#define R1B_RX_INTP_SCO_DELAY_EN_C_M 0x20000000 +#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C 0x2378 +#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C_M 0x40000000 +#define R1B_RX_RXSC_C 0x237C +#define R1B_RX_RXSC_C_M 0x1 +#define R1B_RX_DCEST_EN_C 0x237C +#define R1B_RX_DCEST_EN_C_M 0x2 +#define R1B_RX_DCCOMP_EN_C 0x237C +#define R1B_RX_DCCOMP_EN_C_M 0x4 +#define R1B_RX_AAGC_DONE_TO_DCEST_C 0x237C +#define R1B_RX_AAGC_DONE_TO_DCEST_C_M 0x18 +#define R1B_RX_DCNF_EN_C 0x237C +#define R1B_RX_DCNF_EN_C_M 0x10000 +#define R1B_RX_DCNF_MODE_1_C 0x237C +#define R1B_RX_DCNF_MODE_1_C_M 0xE0000 +#define R1B_RX_DCNF_MODE_2_C 0x237C +#define R1B_RX_DCNF_MODE_2_C_M 0x700000 +#define R1B_RX_DCNF_MODE_3_C 0x237C +#define R1B_RX_DCNF_MODE_3_C_M 0x3800000 +#define R1B_RX_LF_K1_HD_C 0x2380 +#define R1B_RX_LF_K1_HD_C_M 0xFF +#define R1B_RX_LF_K1_PD_C 0x2380 +#define R1B_RX_LF_K1_PD_C_M 0xFF00 +#define R1B_RX_LF_K0_HD_C 0x2380 +#define R1B_RX_LF_K0_HD_C_M 0xFF0000 +#define R1B_RX_LF_K0_PD_C 0x2380 +#define R1B_RX_LF_K0_PD_C_M 0xFF000000 +#define R1B_RX_FREQ_EST_NUM_C 0x2384 +#define R1B_RX_FREQ_EST_NUM_C_M 0x3 +#define R1B_RX_DC_WIN_EN_C 0x2384 +#define R1B_RX_DC_WIN_EN_C_M 0x4 +#define R1B_RX_PHASE_COMP_EN_C 0x2384 +#define R1B_RX_PHASE_COMP_EN_C_M 0x8 +#define R1B_RX_PHROT_IDX_BKC_C 0x2384 +#define R1B_RX_PHROT_IDX_BKC_C_M 0xF0 +#define R1B_RX_PHROT_IDX_CCK_C 0x2384 +#define R1B_RX_PHROT_IDX_CCK_C_M 0xF00 +#define R1B_RX_SCO_QWQ_C 0x2384 +#define R1B_RX_SCO_QWQ_C_M 0x8000 +#define R1B_RX_SCO_EN_C 0x2384 +#define R1B_RX_SCO_EN_C_M 0x10000 +#define R1B_RX_SBD_TO_SCO_C 0x2384 +#define R1B_RX_SBD_TO_SCO_C_M 0x60000 +#define R1B_RX_SCO_PLCP_MODE_C 0x2384 +#define R1B_RX_SCO_PLCP_MODE_C_M 0x80000 +#define R1B_RX_SCO_PSDU_MODE_C 0x2384 +#define R1B_RX_SCO_PSDU_MODE_C_M 0x300000 +#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C 0x2384 +#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C_M 0x7C00000 +#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C 0x2384 +#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C_M 0xF8000000 +#define R1B_RX_CHEST_TARGET_TH_C 0x2388 +#define R1B_RX_CHEST_TARGET_TH_C_M 0xFF +#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C 0x2388 +#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C_M 0x1F00 +#define R1B_RX_RAKE_EN_C 0x2388 +#define R1B_RX_RAKE_EN_C_M 0x2000 +#define R1B_RX_EQISI_EN_C 0x2388 +#define R1B_RX_EQISI_EN_C_M 0x4000 +#define R1B_RX_RPT_RST_C 0x2388 +#define R1B_RX_RPT_RST_C_M 0x8000 +#define R1B_TRX_DBG_SEL_C 0x2388 +#define R1B_TRX_DBG_SEL_C_M 0x3F0000 +#define R1B_DBG_PORT_SWITCH_C 0x2388 +#define R1B_DBG_PORT_SWITCH_C_M 0x400000 +#define R1B_RR_SEL_C 0x2388 +#define R1B_RR_SEL_C_M 0x1800000 +#define R1B_RXIN_MUL_OPT_C 0x2388 +#define R1B_RXIN_MUL_OPT_C_M 0x6000000 +#define R1B_RX_CHEST_MULTIPLY_OPT_C 0x2388 +#define R1B_RX_CHEST_MULTIPLY_OPT_C_M 0x18000000 +#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C 0x2388 +#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C_M 0x20000000 +#define R1B_RX_EDCCA_EN_C 0x238C +#define R1B_RX_EDCCA_EN_C_M 0x1 +#define R1B_RX_FORCE_EDCCA_PATH_EN_C 0x238C +#define R1B_RX_FORCE_EDCCA_PATH_EN_C_M 0x2 +#define R1B_RX_FORCE_EDCCA_PATH_C 0x238C +#define R1B_RX_FORCE_EDCCA_PATH_C_M 0xC +#define R1B_RX_EDCCA_PERIOD_C 0x238C +#define R1B_RX_EDCCA_PERIOD_C_M 0x30 +#define R1B_RX_EDCCA_VLD_TH_C 0x238C +#define R1B_RX_EDCCA_VLD_TH_C_M 0xC0 +#define R1B_RX_EDCCA_ENERGY_TH_C 0x238C +#define R1B_RX_EDCCA_ENERGY_TH_C_M 0xFF00 +#define R1B_RX_EDCCA_OFST_C 0x238C +#define R1B_RX_EDCCA_OFST_C_M 0x1F0000 +#define R1B_RX_EDCCA_WGTSEL_EN_C 0x238C +#define R1B_RX_EDCCA_WGTSEL_EN_C_M 0x200000 +#define R1B_RX_EDCCA_BTTX_OFF_C 0x238C +#define R1B_RX_EDCCA_BTTX_OFF_C_M 0x400000 +#define R1B_RX_EVM_TH_5M_1R_C 0x2390 +#define R1B_RX_EVM_TH_5M_1R_C_M 0x1F +#define R1B_RX_EVM_TH_5M_2R_C 0x2390 +#define R1B_RX_EVM_TH_5M_2R_C_M 0x3E0 +#define R1B_RX_EVM_TH_5M_3R_C 0x2390 +#define R1B_RX_EVM_TH_5M_3R_C_M 0x7C00 +#define R1B_RX_EVM_TH_5M_4R_C 0x2390 +#define R1B_RX_EVM_TH_5M_4R_C_M 0xF8000 +#define R1B_RX_EVM_SIG_OPT_C 0x2390 +#define R1B_RX_EVM_SIG_OPT_C_M 0x300000 +#define R1B_RX_EVM_DATA_OPT_C 0x2390 +#define R1B_RX_EVM_DATA_OPT_C_M 0xC00000 +#define R1B_RX_EVM_SYM_C 0x2390 +#define R1B_RX_EVM_SYM_C_M 0x7000000 +#define R1B_RX_EVM_SCALE_C 0x2390 +#define R1B_RX_EVM_SCALE_C_M 0x38000000 +#define R1B_RX_EVM_ABANDON_EN_C 0x2390 +#define R1B_RX_EVM_ABANDON_EN_C_M 0x40000000 +#define R1B_RX_EVM_TH_11M_1R_C 0x2394 +#define R1B_RX_EVM_TH_11M_1R_C_M 0x1F +#define R1B_RX_EVM_TH_11M_2R_C 0x2394 +#define R1B_RX_EVM_TH_11M_2R_C_M 0x3E0 +#define R1B_RX_EVM_TH_11M_3R_C 0x2394 +#define R1B_RX_EVM_TH_11M_3R_C_M 0x7C00 +#define R1B_RX_EVM_TH_11M_4R_C 0x2394 +#define R1B_RX_EVM_TH_11M_4R_C_M 0xF8000 +#define R1B_RX_EVM_BCC_OFST_C 0x2394 +#define R1B_RX_EVM_BCC_OFST_C_M 0x1F00000 +#define R1B_RX_EVM_CCK_OFST_C 0x2394 +#define R1B_RX_EVM_CCK_OFST_C_M 0x3E000000 +#define R1B_RX_DUMMY_RDRDY_OPT_C 0x2398 +#define R1B_RX_DUMMY_RDRDY_OPT_C_M 0x3 +#define R1B_RX_SFD_SEARCH_OPT_C 0x2398 +#define R1B_RX_SFD_SEARCH_OPT_C_M 0xC +#define R1B_RX_SUPPORT_RATE_C 0x2398 +#define R1B_RX_SUPPORT_RATE_C_M 0xF0 +#define R1B_RX_SPOOF_LEN_C 0x2398 +#define R1B_RX_SPOOF_LEN_C_M 0xFFFFF00 +#define R1B_RX_SUPPORT_MAX_LEN_C 0x239C +#define R1B_RX_SUPPORT_MAX_LEN_C_M 0xFFFF +#define R1B_RX_SUPPORT_MIN_LEN_C 0x239C +#define R1B_RX_SUPPORT_MIN_LEN_C_M 0xFFFF0000 +#define R1B_RX_SCOREBOARD_LEN_0_C 0x23A0 +#define R1B_RX_SCOREBOARD_LEN_0_C_M 0xFFFF +#define R1B_RX_SCOREBOARD_LEN_1_C 0x23A0 +#define R1B_RX_SCOREBOARD_LEN_1_C_M 0xFFFF0000 +#define R1B_RX_SCOREBOARD_LEN_2_C 0x23A4 +#define R1B_RX_SCOREBOARD_LEN_2_C_M 0xFFFF +#define R1B_RX_SCOREBOARD_LEN_3_C 0x23A4 +#define R1B_RX_SCOREBOARD_LEN_3_C_M 0xFFFF0000 +#define R1B_RX_SUICIDE_OPT_C 0x23A8 +#define R1B_RX_SUICIDE_OPT_C_M 0xFF +#define R1B_RX_AIR_DELAY_BCC_C 0x23A8 +#define R1B_RX_AIR_DELAY_BCC_C_M 0x7F00 +#define R1B_RX_IDLE_HANG_LEN_C 0x23A8 +#define R1B_RX_IDLE_HANG_LEN_C_M 0x3F8000 +#define R1B_RX_SYNC_RST_LEN_C 0x23A8 +#define R1B_RX_SYNC_RST_LEN_C_M 0x3C00000 +#define R1B_RX_CCA_RST_LEN_C 0x23A8 +#define R1B_RX_CCA_RST_LEN_C_M 0x3C000000 +#define R1B_RX_RPL_OFST_C 0x23AC +#define R1B_RX_RPL_OFST_C_M 0x7F +#define R1B_RX_RPL_BW_OFST_C 0x23AC +#define R1B_RX_RPL_BW_OFST_C_M 0x180 +#define R1B_RX_AGC_CCA_ILLEGAL_EN_C 0x23AC +#define R1B_RX_AGC_CCA_ILLEGAL_EN_C_M 0x200 +#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C 0x23AC +#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C_M 0x3C00 +#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C 0x23AC +#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C_M 0x3C000 +#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C 0x23AC +#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C_M 0x3C0000 +#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C 0x23AC +#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C_M 0x3C00000 +#define R1B_RX_POP_MASK_SRC_OPT_C 0x23AC +#define R1B_RX_POP_MASK_SRC_OPT_C_M 0x4000000 +#define R1B_RX_FAGCRDY_FIX_OFF_C 0x23AC +#define R1B_RX_FAGCRDY_FIX_OFF_C_M 0x8000000 +#define R1B_RX_SCO_BC_SYNC_MODE_TH_C 0x23B0 +#define R1B_RX_SCO_BC_SYNC_MODE_TH_C_M 0x7FFFF +#define R1B_RX_SCO_FPGA_DOWNRATE4_C 0x23B0 +#define R1B_RX_SCO_FPGA_DOWNRATE4_C_M 0x80000 +#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C 0x23B4 +#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C_M 0x7FFFF +#define HOLD_LDPC_MIN_TIME_C 0x2400 +#define HOLD_LDPC_MIN_TIME_C_M 0x3FF +#define HOLD_LDPC_MIN_TIME_EN_C 0x2400 +#define HOLD_LDPC_MIN_TIME_EN_C_M 0x10000 +#define RXVB_OFF_PKT_END_C 0x2404 +#define RXVB_OFF_PKT_END_C_M 0x1 +#define LDPC_LBK_MODE_C 0x2404 +#define LDPC_LBK_MODE_C_M 0x2 +#define TX_OUT_BUFFER_FSM_RD_COND_C 0x2404 +#define TX_OUT_BUFFER_FSM_RD_COND_C_M 0x4 +#define RX_PHY_ST_DELAY_C 0x2408 +#define RX_PHY_ST_DELAY_C_M 0xFF +#define HE_TB_PLCP_BYPASS_I_C 0x2408 +#define HE_TB_PLCP_BYPASS_I_C_M 0x100 +#define LDPC_0_CLOCK_EN_C 0x240C +#define LDPC_0_CLOCK_EN_C_M 0x1 +#define LDPC_1_CLOCK_EN_C 0x240C +#define LDPC_1_CLOCK_EN_C_M 0x2 +#define DIS_NEW_REPT_ERROR_FIX_C 0x2410 +#define DIS_NEW_REPT_ERROR_FIX_C_M 0x1 +#define USER_TXBF_TYPE_C 0x2410 +#define USER_TXBF_TYPE_C_M 0x10 +#define DIS_TX_HE_RU26_FLAG_C 0x2410 +#define DIS_TX_HE_RU26_FLAG_C_M 0x100 +#define TX_HE_RU26_ACTIVE_FLAG_C 0x2410 +#define TX_HE_RU26_ACTIVE_FLAG_C_M 0x1000 +#define PATH1_R_DAC_QINV_C 0x3000 +#define PATH1_R_DAC_QINV_C_M 0x1 +#define PATH1_R_FIFO_CLR_ENB_C 0x3000 +#define PATH1_R_FIFO_CLR_ENB_C_M 0x10 +#define PATH1_R_T2F_FREERUN_BUF_EN_C 0x3004 +#define PATH1_R_T2F_FREERUN_BUF_EN_C_M 0x1 +#define PATH1_R_T2F_L1_LATE_EN_C 0x3004 +#define PATH1_R_T2F_L1_LATE_EN_C_M 0x2 +#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x3004 +#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10 +#define PATH1_R_T2F_DCCL_FILT_EN_C 0x3004 +#define PATH1_R_T2F_DCCL_FILT_EN_C_M 0x100 +#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C 0x3004 +#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000 +#define PATH1_R_TD_CLK_GCK_EN_C 0x3008 +#define PATH1_R_TD_CLK_GCK_EN_C_M 0x1 +#define PATH1_R_1RCCA_CLK_GCK_ON_C 0x3008 +#define PATH1_R_1RCCA_CLK_GCK_ON_C_M 0x10 +#define PATH1_R_SYNC_RST_EN_TD_PATH_C 0x300C +#define PATH1_R_SYNC_RST_EN_TD_PATH_C_M 0x1 +#define PATH1_R_SYNC_RST_EN_FFT_C 0x300C +#define PATH1_R_SYNC_RST_EN_FFT_C_M 0x10 +#define PATH1_R_SYNC_RST_EN_TXBUF_C 0x300C +#define PATH1_R_SYNC_RST_EN_TXBUF_C_M 0x100 +#define PATH1_R_SYNC_RST_EN_RXBUF_C 0x300C +#define PATH1_R_SYNC_RST_EN_RXBUF_C_M 0x1000 +#define PATH1_R_SYNC_RST_EN_DCCL_C 0x300C +#define PATH1_R_SYNC_RST_EN_DCCL_C_M 0x10000 +#define PATH1_R_SYNC_RST_EN_T2F_C 0x300C +#define PATH1_R_SYNC_RST_EN_T2F_C_M 0x100000 +#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C 0x300C +#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000 +#define PATH1_R_DCCL_CFO_TH_EN_C 0x3010 +#define PATH1_R_DCCL_CFO_TH_EN_C_M 0x1 +#define PATH1_R_DCCL_52B_SYMB_TH_EN_C 0x3010 +#define PATH1_R_DCCL_52B_SYMB_TH_EN_C_M 0x10 +#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C 0x3010 +#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20 +#define PATH1_R_TX_STO_TRIG_SELECT_C 0x3014 +#define PATH1_R_TX_STO_TRIG_SELECT_C_M 0x1 +#define PATH1_R_TX_STO_FIRST_PE_SELECT_C 0x3014 +#define PATH1_R_TX_STO_FIRST_PE_SELECT_C_M 0x2 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x3018 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C 0x301C +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x301C +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10 +#define PATH1_R_STO_INT_SEL_L_C 0x301C +#define PATH1_R_STO_INT_SEL_L_C_M 0x20 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x301C +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x301C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x301C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x301C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x3020 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x3024 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x3024 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10 +#define PATH1_R_STO_INT_SEL_HT_C 0x3024 +#define PATH1_R_STO_INT_SEL_HT_C_M 0x20 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x3024 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x3024 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x3024 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x3024 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x3028 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x302C +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x302C +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10 +#define PATH1_R_STO_INT_SEL_VHT_C 0x302C +#define PATH1_R_STO_INT_SEL_VHT_C_M 0x20 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x302C +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x302C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x302C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x302C +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x3030 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x3034 +#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x3034 +#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10 +#define PATH1_R_STO_INT_SEL_HE_C 0x3034 +#define PATH1_R_STO_INT_SEL_HE_C_M 0x20 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x3034 +#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x3034 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x3034 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x3034 +#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000 +#define PATH1_R_HW_SI_READ_ADDR_C 0x3200 +#define PATH1_R_HW_SI_READ_ADDR_C_M 0xFF +#define PATH1_R_HW_SI_READ_EDGE_OPT_C 0x3200 +#define PATH1_R_HW_SI_READ_EDGE_OPT_C_M 0x300 +#define PATH1_R_HW_SI_ZERO_PADDING_EN_C 0x3200 +#define PATH1_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000 +#define PATH1_R_HW_SI_BYPASS_ST_MASK_C 0x3200 +#define PATH1_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000 +#define PATH1_R_HW_SI_DATA_E_INV_C 0x3200 +#define PATH1_R_HW_SI_DATA_E_INV_C_M 0x20000 +#define PATH1_R_HW_SI_SEL_DBG_C 0x3200 +#define PATH1_R_HW_SI_SEL_DBG_C_M 0xC0000 +#define PATH1_R_HW_SI_DBG_MODE_C 0x3200 +#define PATH1_R_HW_SI_DBG_MODE_C_M 0x100000 +#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C 0x3200 +#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000 +#define PATH1_R_HW_SI_DBG_TX_TRIG_C 0x3200 +#define PATH1_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000 +#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C 0x3200 +#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000 +#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C 0x3200 +#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000 +#define PATH1_R_HW_SI_DIS_R_TRIG_C 0x3200 +#define PATH1_R_HW_SI_DIS_R_TRIG_C_M 0x40000000 +#define PATH1_R_HW_SI_DBG_RX_CMD_0_C 0x3204 +#define PATH1_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF +#define PATH1_R_HW_SI_DBG_RX_CMD_1_C 0x3204 +#define PATH1_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000 +#define PATH1_R_HW_SI_DBG_TX_CMD_0_C 0x3208 +#define PATH1_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF +#define PATH1_R_HW_SI_DBG_TX_CMD_1_C 0x3208 +#define PATH1_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000 +#define PATH1_R_ANAPAR_ST1P5_SEL_C 0x320C +#define PATH1_R_ANAPAR_ST1P5_SEL_C_M 0xF +#define PATH1_R_ANAPAR_ST3P5_SEL_C 0x320C +#define PATH1_R_ANAPAR_ST3P5_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x320C +#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000 +#define PATH1_R_RFMODE_RSTB_EQ0_EN_C 0x3210 +#define PATH1_R_RFMODE_RSTB_EQ0_EN_C_M 0x1 +#define PATH1_R_PW_RSTB_EQ0_EN_C 0x3210 +#define PATH1_R_PW_RSTB_EQ0_EN_C_M 0x2 +#define PATH1_R_RSTB_EQ0_EN_C 0x3210 +#define PATH1_R_RSTB_EQ0_EN_C_M 0x4 +#define PATH1_R_RFMODE_RSTB_EQ0_C 0x3210 +#define PATH1_R_RFMODE_RSTB_EQ0_C_M 0xF0 +#define PATH1_R_PW_RSTB_EQ0_C 0x3210 +#define PATH1_R_PW_RSTB_EQ0_C_M 0xFF00 +#define PATH1_R_RSTB_EQ0_C 0x3210 +#define PATH1_R_RSTB_EQ0_C_M 0xFFFF0000 +#define PATH1_R_RFC_SI_SEL_0_C 0x3214 +#define PATH1_R_RFC_SI_SEL_0_C_M 0x1 +#define PATH1_R_RFC_SI_SEL_1_C 0x3214 +#define PATH1_R_RFC_SI_SEL_1_C_M 0x10 +#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x3218 +#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1 +#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x3218 +#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2 +#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C 0x3218 +#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4 +#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C 0x3218 +#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0 +#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C 0x3218 +#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00 +#define PATH1_R_HW_SI_R_TRIG_DLY_C 0x3218 +#define PATH1_R_HW_SI_R_TRIG_DLY_C_M 0xF000 +#define PATH1_R_ANAPAR_RST_SEL_C 0x32A0 +#define PATH1_R_ANAPAR_RST_SEL_C_M 0xF +#define PATH1_R_ANAPAR_RST_TX_SEL_C 0x32A0 +#define PATH1_R_ANAPAR_RST_TX_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_CTSDM_131_128__C 0x32A0 +#define PATH1_R_ANAPAR_CTSDM_131_128__C_M 0xF00 +#define PATH1_R_TXCK_FORCE_VAL_C 0x32A0 +#define PATH1_R_TXCK_FORCE_VAL_C_M 0x7000 +#define PATH1_R_TXCK_FORCE_ON_C 0x32A0 +#define PATH1_R_TXCK_FORCE_ON_C_M 0x8000 +#define PATH1_R_RXCK_FORCE_VAL_C 0x32A0 +#define PATH1_R_RXCK_FORCE_VAL_C_M 0x70000 +#define PATH1_R_RXCK_FORCE_ON_C 0x32A0 +#define PATH1_R_RXCK_FORCE_ON_C_M 0x80000 +#define PATH1_R_RXCK_RFBW0_C 0x32A0 +#define PATH1_R_RXCK_RFBW0_C_M 0x700000 +#define PATH1_R_RXCK_RFBW1_C 0x32A0 +#define PATH1_R_RXCK_RFBW1_C_M 0x3800000 +#define PATH1_R_RXCK_RFBW2_C 0x32A0 +#define PATH1_R_RXCK_RFBW2_C_M 0x1C000000 +#define PATH1_R_RXCK_RFBW3_C 0x32A0 +#define PATH1_R_RXCK_RFBW3_C_M 0xE0000000 +#define PATH1_R_RXCK_RFBW4_C 0x32A4 +#define PATH1_R_RXCK_RFBW4_C_M 0x7 +#define PATH1_R_RXCK_RFBW5_C 0x32A4 +#define PATH1_R_RXCK_RFBW5_C_M 0x38 +#define PATH1_R_RXCK_RFBW6_C 0x32A4 +#define PATH1_R_RXCK_RFBW6_C_M 0x1C0 +#define PATH1_R_TXCK_RFBW0_C 0x32A4 +#define PATH1_R_TXCK_RFBW0_C_M 0x3800 +#define PATH1_R_TXCK_RFBW1_C 0x32A4 +#define PATH1_R_TXCK_RFBW1_C_M 0x1C000 +#define PATH1_R_TXCK_RFBW2_C 0x32A4 +#define PATH1_R_TXCK_RFBW2_C_M 0xE0000 +#define PATH1_R_TXCK_RFBW3_C 0x32A4 +#define PATH1_R_TXCK_RFBW3_C_M 0x700000 +#define PATH1_R_TXCK_RFBW4_C 0x32A4 +#define PATH1_R_TXCK_RFBW4_C_M 0x3800000 +#define PATH1_R_TXCK_RFBW5_C 0x32A4 +#define PATH1_R_TXCK_RFBW5_C_M 0x1C000000 +#define PATH1_R_TXCK_RFBW6_C 0x32A4 +#define PATH1_R_TXCK_RFBW6_C_M 0xE0000000 +#define PATH1_R_EN_RXCK_TX_C 0x32A8 +#define PATH1_R_EN_RXCK_TX_C_M 0x1 +#define PATH1_R_RXCK_TX_C 0x32A8 +#define PATH1_R_RXCK_TX_C_M 0xE +#define PATH1_R_RXCK_TX_FTM_C 0x32A8 +#define PATH1_R_RXCK_TX_FTM_C_M 0x70 +#define PATH1_R_CLK_RFC_GCK_EN_C 0x32A8 +#define PATH1_R_CLK_RFC_GCK_EN_C_M 0x80 +#define PATH1_R_RF0_GEN_DBG_SEL_C 0x32A8 +#define PATH1_R_RF0_GEN_DBG_SEL_C_M 0x300 +#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x32A8 +#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800 +#define PATH1_R_RFAFE_PWSAV_EN_C 0x32A8 +#define PATH1_R_RFAFE_PWSAV_EN_C_M 0xF000 +#define PATH1_R_RFMODE_ORI_RXB_OFF_C 0x32A8 +#define PATH1_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000 +#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C 0x32A8 +#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000 +#define PATH1_R_RFMODE_FTM_RXB_OFF_C 0x32A8 +#define PATH1_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000 +#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C 0x32A8 +#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000 +#define PATH1_R_RSTB_3WIRE_C 0x32AC +#define PATH1_R_RSTB_3WIRE_C_M 0x1 +#define PATH1_R_EN_NRBW_AT_TX_C 0x32AC +#define PATH1_R_EN_NRBW_AT_TX_C_M 0x4 +#define PATH1_R_RFMODE_ORI_TX_C 0x32AC +#define PATH1_R_RFMODE_ORI_TX_C_M 0xF0 +#define PATH1_R_RFMODE_ORI_TX_TXOFF_C 0x32AC +#define PATH1_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00 +#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C 0x32AC +#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000 +#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C 0x32AC +#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000 +#define PATH1_R_RFMODE_ORI_RX_IDLE_C 0x32AC +#define PATH1_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000 +#define PATH1_R_RFMODE_FTM_TX_C 0x32AC +#define PATH1_R_RFMODE_FTM_TX_C_M 0xF000000 +#define PATH1_R_RFMODE_FTM_TX_TXOFF_C 0x32AC +#define PATH1_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000 +#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C 0x32B0 +#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF +#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C 0x32B0 +#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0 +#define PATH1_R_RFMODE_FTM_RX_IDLE_C 0x32B0 +#define PATH1_R_RFMODE_FTM_RX_IDLE_C_M 0xF00 +#define PATH1_R_RXB_IDX_AT_TX_C 0x32B0 +#define PATH1_R_RXB_IDX_AT_TX_C_M 0x1F000 +#define PATH1_R_TIA_IDX_AT_TX_C 0x32B0 +#define PATH1_R_TIA_IDX_AT_TX_C_M 0x20000 +#define PATH1_R_LNA_IDX_AT_TX_C 0x32B0 +#define PATH1_R_LNA_IDX_AT_TX_C_M 0x1C0000 +#define PATH1_R_TIA_EXT_BW_AT_TX_C 0x32B0 +#define PATH1_R_TIA_EXT_BW_AT_TX_C_M 0x200000 +#define PATH1_R_SI_RADDR_C 0x32B0 +#define PATH1_R_SI_RADDR_C_M 0x3FC00000 +#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C 0x32B0 +#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000 +#define PATH1_R_SOFT3WIRE_DATA_C 0x32B4 +#define PATH1_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF +#define PATH1_R_TXAGC_AT_SLEEP_C 0x32B8 +#define PATH1_R_TXAGC_AT_SLEEP_C_M 0x3F +#define PATH1_R_RXB_IDX_AT_SLEEP_C 0x32B8 +#define PATH1_R_RXB_IDX_AT_SLEEP_C_M 0x7C0 +#define PATH1_R_TIA_IDX_AT_SLEEP_C 0x32B8 +#define PATH1_R_TIA_IDX_AT_SLEEP_C_M 0x800 +#define PATH1_R_LNA_IDX_AT_SLEEP_C 0x32B8 +#define PATH1_R_LNA_IDX_AT_SLEEP_C_M 0x7000 +#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C 0x32B8 +#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000 +#define PATH1_R_EN_NRBW_AT_SLEEP_C 0x32B8 +#define PATH1_R_EN_NRBW_AT_SLEEP_C_M 0x10000 +#define PATH1_R_RFMODE_AT_SLEEP_C 0x32B8 +#define PATH1_R_RFMODE_AT_SLEEP_C_M 0x1E0000 +#define PATH1_R_TXAGC_BYPASS_C 0x32B8 +#define PATH1_R_TXAGC_BYPASS_C_M 0x200000 +#define PATH1_R_RXB_BYPASS_C 0x32B8 +#define PATH1_R_RXB_BYPASS_C_M 0x400000 +#define PATH1_R_TIA_BYPASS_C 0x32B8 +#define PATH1_R_TIA_BYPASS_C_M 0x800000 +#define PATH1_R_LNA_BYPASS_C 0x32B8 +#define PATH1_R_LNA_BYPASS_C_M 0x1000000 +#define PATH1_R_TIA_EXT_BYPASS_C 0x32B8 +#define PATH1_R_TIA_EXT_BYPASS_C_M 0x2000000 +#define PATH1_R_EN_NRBW_BYPASS_C 0x32B8 +#define PATH1_R_EN_NRBW_BYPASS_C_M 0x4000000 +#define PATH1_R_RFREG_DIS_GATING_C 0x32B8 +#define PATH1_R_RFREG_DIS_GATING_C_M 0x8000000 +#define PATH1_R_RSTB_ANAPAR_C 0x32B8 +#define PATH1_R_RSTB_ANAPAR_C_M 0x10000000 +#define PATH1_R_ANAPAR_SEL_OPT_C 0x32B8 +#define PATH1_R_ANAPAR_SEL_OPT_C_M 0x20000000 +#define PATH1_R_ANAPAR_DBG_MODE_C 0x32B8 +#define PATH1_R_ANAPAR_DBG_MODE_C_M 0x40000000 +#define PATH1_R_ANAPAR_DIS_GATING_C 0x32B8 +#define PATH1_R_ANAPAR_DIS_GATING_C_M 0x80000000 +#define PATH1_R_ANAPAR_ST0_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST0_SEL_C_M 0xF +#define PATH1_R_ANAPAR_ST1_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST1_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_ST2_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST2_SEL_C_M 0xF00 +#define PATH1_R_ANAPAR_ST3_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST3_SEL_C_M 0xF000 +#define PATH1_R_ANAPAR_ST4_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST4_SEL_C_M 0xF0000 +#define PATH1_R_ANAPAR_ST5_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST5_SEL_C_M 0xF00000 +#define PATH1_R_ANAPAR_ST6_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST6_SEL_C_M 0xF000000 +#define PATH1_R_ANAPAR_ST7_SEL_C 0x32BC +#define PATH1_R_ANAPAR_ST7_SEL_C_M 0xF0000000 +#define PATH1_R_ANAPAR_ST8_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST8_SEL_C_M 0xF +#define PATH1_R_ANAPAR_ST9_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST9_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_ST10_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST10_SEL_C_M 0xF00 +#define PATH1_R_ANAPAR_ST11_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST11_SEL_C_M 0xF000 +#define PATH1_R_ANAPAR_ST12_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST12_SEL_C_M 0xF0000 +#define PATH1_R_ANAPAR_ST13_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST13_SEL_C_M 0xF00000 +#define PATH1_R_ANAPAR_ST14_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST14_SEL_C_M 0xF000000 +#define PATH1_R_ANAPAR_ST15_SEL_C 0x32C0 +#define PATH1_R_ANAPAR_ST15_SEL_C_M 0xF0000000 +#define PATH1_R_ANAPAR_ST16_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST16_SEL_C_M 0xF +#define PATH1_R_ANAPAR_ST17_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST17_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_ST18_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST18_SEL_C_M 0xF00 +#define PATH1_R_ANAPAR_ST19_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST19_SEL_C_M 0xF000 +#define PATH1_R_ANAPAR_ST20_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST20_SEL_C_M 0xF0000 +#define PATH1_R_ANAPAR_ST21_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST21_SEL_C_M 0xF00000 +#define PATH1_R_ANAPAR_ST22_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST22_SEL_C_M 0xF000000 +#define PATH1_R_ANAPAR_ST23_SEL_C 0x32C4 +#define PATH1_R_ANAPAR_ST23_SEL_C_M 0xF0000000 +#define PATH1_R_ANAPAR_ST24_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST24_SEL_C_M 0xF +#define PATH1_R_ANAPAR_ST25_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST25_SEL_C_M 0xF0 +#define PATH1_R_ANAPAR_ST26_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST26_SEL_C_M 0xF00 +#define PATH1_R_ANAPAR_ST27_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST27_SEL_C_M 0xF000 +#define PATH1_R_ANAPAR_ST28_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST28_SEL_C_M 0xF0000 +#define PATH1_R_ANAPAR_ST29_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST29_SEL_C_M 0xF00000 +#define PATH1_R_ANAPAR_ST30_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST30_SEL_C_M 0xF000000 +#define PATH1_R_ANAPAR_ST31_SEL_C 0x32C8 +#define PATH1_R_ANAPAR_ST31_SEL_C_M 0xF0000000 +#define PATH1_R_ANAPAR_CTSDM_31_0__C 0x32CC +#define PATH1_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_CTSDM_63_32__C 0x32D0 +#define PATH1_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_CTSDM_95_64__C 0x32D4 +#define PATH1_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_CTSDM_127_96__C 0x32D8 +#define PATH1_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_31_0__C 0x32DC +#define PATH1_R_ANAPAR_31_0__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_63_32__C 0x32E0 +#define PATH1_R_ANAPAR_63_32__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_95_64__C 0x32E4 +#define PATH1_R_ANAPAR_95_64__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_127_96__C 0x32E8 +#define PATH1_R_ANAPAR_127_96__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_143_128__C 0x32EC +#define PATH1_R_ANAPAR_143_128__C_M 0xFFFF +#define PATH1_R_ANAPAR_LBK_15_0__C 0x32EC +#define PATH1_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000 +#define PATH1_R_ANAPAR_LBK_47_16__C 0x32F0 +#define PATH1_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_LBK_79_48__C 0x32F4 +#define PATH1_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_LBK_111_80__C 0x32F8 +#define PATH1_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF +#define PATH1_R_ANAPAR_LBK_143_112__C 0x32FC +#define PATH1_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF +#define PATH1_TSSI_DBG_PORT_C 0x3C00 +#define PATH1_TSSI_DBG_PORT_C_M 0xFFFFFFFF +#define PATH1_DCK_AUTO_AVG_DC_C 0x3C04 +#define PATH1_DCK_AUTO_AVG_DC_C_M 0xFFF000 +#define PATH1_HE_LSTF_PW_OFST_C 0x3C04 +#define PATH1_HE_LSTF_PW_OFST_C_M 0xFF000000 +#define PATH1_DCK_AUTO_MAX_DC_C 0x3C08 +#define PATH1_DCK_AUTO_MAX_DC_C_M 0xFFF +#define PATH1_DCK_AUTO_MIN_DC_C 0x3C08 +#define PATH1_DCK_AUTO_MIN_DC_C_M 0xFFF000 +#define PATH1_TMETER_F_C 0x3C08 +#define PATH1_TMETER_F_C_M 0xFF000000 +#define PATH1_TSSI_AVG_R_C 0x3C10 +#define PATH1_TSSI_AVG_R_C_M 0xFFF +#define PATH1_TSSI_MAX_R_C 0x3C10 +#define PATH1_TSSI_MAX_R_C_M 0xFFF000 +#define PATH1_TSSI_F_NOW_C 0x3C10 +#define PATH1_TSSI_F_NOW_C_M 0xFF000000 +#define PATH1_TSSI_MID_R_C 0x3C14 +#define PATH1_TSSI_MID_R_C_M 0xFFF +#define PATH1_TSSI_LAST_R_C 0x3C14 +#define PATH1_TSSI_LAST_R_C_M 0xFFF000 +#define PATH1_GAIN_TX_IPA_MX_C 0x3C14 +#define PATH1_GAIN_TX_IPA_MX_C_M 0x7000000 +#define PATH1_TSSI_VAL_AVG_C 0x3C18 +#define PATH1_TSSI_VAL_AVG_C_M 0x3FF +#define PATH1_TSSI_VAL_AVG_OUT_VLD_C 0x3C18 +#define PATH1_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000 +#define PATH1_ADC_RE_C 0x3C18 +#define PATH1_ADC_RE_C_M 0xFFF00000 +#define PATH1_TSSI_VAL_D00_C 0x3C1C +#define PATH1_TSSI_VAL_D00_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_0_C 0x3C1C +#define PATH1_TSSI_VAL_VLD_IDX_0_C_M 0x8000 +#define PATH1_TSSI_VAL_D01_C 0x3C1C +#define PATH1_TSSI_VAL_D01_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_1_C 0x3C1C +#define PATH1_TSSI_VAL_VLD_IDX_1_C_M 0x80000000 +#define PATH1_TSSI_VAL_D02_C 0x3C20 +#define PATH1_TSSI_VAL_D02_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_2_C 0x3C20 +#define PATH1_TSSI_VAL_VLD_IDX_2_C_M 0x8000 +#define PATH1_TSSI_VAL_D03_C 0x3C20 +#define PATH1_TSSI_VAL_D03_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_3_C 0x3C20 +#define PATH1_TSSI_VAL_VLD_IDX_3_C_M 0x80000000 +#define PATH1_TSSI_VAL_D04_C 0x3C24 +#define PATH1_TSSI_VAL_D04_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_4_C 0x3C24 +#define PATH1_TSSI_VAL_VLD_IDX_4_C_M 0x8000 +#define PATH1_TSSI_VAL_D05_C 0x3C24 +#define PATH1_TSSI_VAL_D05_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_5_C 0x3C24 +#define PATH1_TSSI_VAL_VLD_IDX_5_C_M 0x80000000 +#define PATH1_TSSI_VAL_D06_C 0x3C28 +#define PATH1_TSSI_VAL_D06_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_6_C 0x3C28 +#define PATH1_TSSI_VAL_VLD_IDX_6_C_M 0x8000 +#define PATH1_TSSI_VAL_D07_C 0x3C28 +#define PATH1_TSSI_VAL_D07_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_7_C 0x3C28 +#define PATH1_TSSI_VAL_VLD_IDX_7_C_M 0x80000000 +#define PATH1_TSSI_VAL_D08_C 0x3C2C +#define PATH1_TSSI_VAL_D08_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_8_C 0x3C2C +#define PATH1_TSSI_VAL_VLD_IDX_8_C_M 0x8000 +#define PATH1_TSSI_VAL_D09_C 0x3C2C +#define PATH1_TSSI_VAL_D09_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_9_C 0x3C2C +#define PATH1_TSSI_VAL_VLD_IDX_9_C_M 0x80000000 +#define PATH1_TSSI_VAL_D10_C 0x3C30 +#define PATH1_TSSI_VAL_D10_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_10_C 0x3C30 +#define PATH1_TSSI_VAL_VLD_IDX_10_C_M 0x8000 +#define PATH1_TSSI_VAL_D11_C 0x3C30 +#define PATH1_TSSI_VAL_D11_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_11_C 0x3C30 +#define PATH1_TSSI_VAL_VLD_IDX_11_C_M 0x80000000 +#define PATH1_TSSI_VAL_D12_C 0x3C34 +#define PATH1_TSSI_VAL_D12_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_12_C 0x3C34 +#define PATH1_TSSI_VAL_VLD_IDX_12_C_M 0x8000 +#define PATH1_TSSI_VAL_D13_C 0x3C34 +#define PATH1_TSSI_VAL_D13_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_13_C 0x3C34 +#define PATH1_TSSI_VAL_VLD_IDX_13_C_M 0x80000000 +#define PATH1_TSSI_VAL_D14_C 0x3C38 +#define PATH1_TSSI_VAL_D14_C_M 0x3FF +#define PATH1_TSSI_VAL_VLD_IDX_14_C 0x3C38 +#define PATH1_TSSI_VAL_VLD_IDX_14_C_M 0x8000 +#define PATH1_TSSI_VAL_D15_C 0x3C38 +#define PATH1_TSSI_VAL_D15_C_M 0x3FF0000 +#define PATH1_TSSI_VAL_VLD_IDX_15_C 0x3C38 +#define PATH1_TSSI_VAL_VLD_IDX_15_C_M 0x80000000 +#define PATH1_TSSI_OSCILLATION_CNT_C 0x3C3C +#define PATH1_TSSI_OSCILLATION_CNT_C_M 0xFFFF +#define PATH1_TSSI_VAL_VLD_IDX_C 0x3C3C +#define PATH1_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000 +#define PATH1_PRE_TXAGC_OFST_C 0x3C40 +#define PATH1_PRE_TXAGC_OFST_C_M 0xFF00 +#define PATH1_DELTA_TSSI_PW_C 0x3C40 +#define PATH1_DELTA_TSSI_PW_C_M 0xFF0000 +#define PATH1SWING_MIN_C 0x3C40 +#define PATH1SWING_MIN_C_M 0xF000000 +#define PATH1SWING_MAX_C 0x3C40 +#define PATH1SWING_MAX_C_M 0xF0000000 +#define PATH1_TSSI_C_RAW0_C 0x3C44 +#define PATH1_TSSI_C_RAW0_C_M 0x1FF000 +#define PATH1_TSSI_F_C 0x3C48 +#define PATH1_TSSI_F_C_M 0xFF +#define PATH1_TSSI_G_C 0x3C48 +#define PATH1_TSSI_G_C_M 0x3FF00 +#define PATH1_TSSI_S_C 0x3C48 +#define PATH1_TSSI_S_C_M 0x1FF00000 +#define PATH1_AVG_R_SQUARE_C 0x3C4C +#define PATH1_AVG_R_SQUARE_C_M 0xFFFFFF +#define PATH1_TSSI_F_RDY_C 0x3C4C +#define PATH1_TSSI_F_RDY_C_M 0x20000000 +#define PATH1_TSSI_G_RDY_C 0x3C4C +#define PATH1_TSSI_G_RDY_C_M 0x40000000 +#define PATH1_TSSI_C_RDY_C 0x3C4C +#define PATH1_TSSI_C_RDY_C_M 0x80000000 +#define PATH1_IN_R_SQUARE_MAX_C 0x3C50 +#define PATH1_IN_R_SQUARE_MAX_C_M 0xFFFFFF +#define PATH1_SPEC_IDX_C 0x3C50 +#define PATH1_SPEC_IDX_C_M 0x7000000 +#define PATH1_IN_R_SQUARE_MIN_C 0x3C54 +#define PATH1_IN_R_SQUARE_MIN_C_M 0xFFFFFF +#define PATH1_AVG_R_RMS_C 0x3C58 +#define PATH1_AVG_R_RMS_C_M 0xFFF +#define PATH1_AVG_R_RMS_RDY_C 0x3C58 +#define PATH1_AVG_R_RMS_RDY_C_M 0x80000000 +#define PATH1_DAC_GAIN_COMP_TBL_IDX_C 0x3C5C +#define PATH1_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF +#define PATH1_DAC_GAIN_COMP_DBG_C 0x3C5C +#define PATH1_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00 +#define PATH1_TXAGC_RF_C 0x3C60 +#define PATH1_TXAGC_RF_C_M 0x3F +#define PATH1_TSSI_OFST_C 0x3C60 +#define PATH1_TSSI_OFST_C_M 0x1F00 +#define PATH1_TXAGC_C 0x3C60 +#define PATH1_TXAGC_C_M 0xFF0000 +#define PATH1_TXAGC_ORIG_C 0x3C64 +#define PATH1_TXAGC_ORIG_C_M 0x1FF +#define PATH1_TXAGC_ORIG_RAW_C 0x3C64 +#define PATH1_TXAGC_ORIG_RAW_C_M 0x1FF000 +#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C 0x3C64 +#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000 +#define PATH1_TXAGC_TO_TSSI_CW_RPT_C 0x3C68 +#define PATH1_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF +#define PATH1_TSSI_C_RAW1_C 0x3C6C +#define PATH1_TSSI_C_RAW1_C_M 0x1FF +#define PATH1_DAC_GAIN_COMP_MX_C 0x3C70 +#define PATH1_DAC_GAIN_COMP_MX_C_M 0xFF0000 +#define PATH1_TSSI_CW_COMP_MX_C 0x3C70 +#define PATH1_TSSI_CW_COMP_MX_C_M 0xFF000000 +#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x3C74 +#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF +#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x3C74 +#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000 +#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74 +#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000 +#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74 +#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000 +#define PATH1_RFC_PREAMLE_PW_TYPE_C 0x3C74 +#define PATH1_RFC_PREAMLE_PW_TYPE_C_M 0x70000000 +#define PATH1_TXPW_C 0x3C78 +#define PATH1_TXPW_C_M 0x1FF +#define PATH1_TXAGCSWING_C 0x3C78 +#define PATH1_TXAGCSWING_C_M 0x1E00 +#define PATH1_HE_ER_SU_EN_C 0x3C78 +#define PATH1_HE_ER_SU_EN_C_M 0x2000 +#define PATH1_HE_TB_EN_C 0x3C78 +#define PATH1_HE_TB_EN_C_M 0x4000 +#define PATH1_CCK_PPDU_C 0x3C78 +#define PATH1_CCK_PPDU_C_M 0x8000 +#define PATH1_TXINFO_CH_WITH_DATA_C 0x3C78 +#define PATH1_TXINFO_CH_WITH_DATA_C_M 0xFF0000 +#define PATH1_TXSC_C 0x3C78 +#define PATH1_TXSC_C_M 0xF000000 +#define PATH1_RF_BW_IDX_C 0x3C78 +#define PATH1_RF_BW_IDX_C_M 0x30000000 +#define PATH1_ISOFDM_PREAMBLE_C 0x3C78 +#define PATH1_ISOFDM_PREAMBLE_C_M 0x40000000 +#define PATH1_ISCCK_PREAMBLE_C 0x3C78 +#define PATH1_ISCCK_PREAMBLE_C_M 0x80000000 +#define PATH1_TXAGC_OFST_MX_C 0x3C7C +#define PATH1_TXAGC_OFST_MX_C_M 0xFF +#define PATH1_TXAGC_OFST_C 0x3C7C +#define PATH1_TXAGC_OFST_C_M 0xFF00 +#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C 0x3C7C +#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000 +#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x3C7C +#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000 +#define PATH1_BYPASS_TSSI_BY_C_C 0x3C7C +#define PATH1_BYPASS_TSSI_BY_C_C_M 0x40000 +#define PATH1_ADC_VARIATION_C 0x3C7C +#define PATH1_ADC_VARIATION_C_M 0xFFF00000 +#define PATH1_DBG_IQK_PATH_C 0x3C80 +#define PATH1_DBG_IQK_PATH_C_M 0xFFFFFFFF +#define PATH1_FTM_RFLBK_BYPASS_C 0x3C84 +#define PATH1_FTM_RFLBK_BYPASS_C_M 0x1 +#define PATH1_FTM_LBK_BYPASS_C 0x3C84 +#define PATH1_FTM_LBK_BYPASS_C_M 0x2 +#define PATH1_FTM_A2A_AFELBK_BYPASS_C 0x3C84 +#define PATH1_FTM_A2A_AFELBK_BYPASS_C_M 0x4 +#define PATH1_GNT_BT_TX_BYPASS_C 0x3C84 +#define PATH1_GNT_BT_TX_BYPASS_C_M 0x8 +#define PATH1_GNT_BT_BYPASS_C 0x3C84 +#define PATH1_GNT_BT_BYPASS_C_M 0x10 +#define PATH1_GNT_WL_BYPASS_C 0x3C84 +#define PATH1_GNT_WL_BYPASS_C_M 0x20 +#define PATH1_LTE_RX_BYPASS_C 0x3C84 +#define PATH1_LTE_RX_BYPASS_C_M 0x40 +#define PATH1_TSSI_BYPASS_TXPW_MIN_C 0x3C84 +#define PATH1_TSSI_BYPASS_TXPW_MIN_C_M 0x80 +#define PATH1_TSSI_BYPASS_TXPW_MAX_C 0x3C84 +#define PATH1_TSSI_BYPASS_TXPW_MAX_C_M 0x100 +#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200 +#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400 +#define PATH1_BYPASS_TSSI_BY_RATE_HT_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HT_C_M 0x800 +#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000 +#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000 +#define PATH1_BYPASS_TSSI_BY_TXBF_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_TXBF_C_M 0x80000 +#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x3C84 +#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000 +#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x3C84 +#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000 +#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x3C84 +#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000 +#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x3C84 +#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000 +#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x3C84 +#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000 +#define PATH1_BYPASS_TSSI_C 0x3C84 +#define PATH1_BYPASS_TSSI_C_M 0x80000000 +#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C 0x3C88 +#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF +#define PATH1_DIGI_AGC_C 0x3C88 +#define PATH1_DIGI_AGC_C_M 0x3FF0 +#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x3C88 +#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000 +#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x3C88 +#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000 +#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C 0x3C88 +#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000 +#define PATH1_RX_CFIR_TAP_DEC_C 0x3C88 +#define PATH1_RX_CFIR_TAP_DEC_C_M 0x40000000 +#define PATH1_CLK_HIGH_RATE_MX_C 0x3C88 +#define PATH1_CLK_HIGH_RATE_MX_C_M 0x80000000 +#define PATH1_CFIR_OUT_IM_DBG_C 0x3C8C +#define PATH1_CFIR_OUT_IM_DBG_C_M 0xFFF +#define PATH1_CFIR_OUT_RE_DBG_C 0x3C8C +#define PATH1_CFIR_OUT_RE_DBG_C_M 0xFFF000 +#define PATH1_EN_RX_CFIR_C 0x3C8C +#define PATH1_EN_RX_CFIR_C_M 0x1000000 +#define PATH1_CLK_HIGH_RATE_C 0x3C8C +#define PATH1_CLK_HIGH_RATE_C_M 0x2000000 +#define PATH1_EN_TX_CFIR_C 0x3C8C +#define PATH1_EN_TX_CFIR_C_M 0x4000000 +#define PATH1_TX_CCK_IND_C 0x3C8C +#define PATH1_TX_CCK_IND_C_M 0x8000000 +#define PATH1_CFIR_IN_IM_DBG_C 0x3C90 +#define PATH1_CFIR_IN_IM_DBG_C_M 0xFFF +#define PATH1_CFIR_IN_RE_DBG_C 0x3C90 +#define PATH1_CFIR_IN_RE_DBG_C_M 0xFFF000 +#define PATH1_CCK_CCA_C 0x3C90 +#define PATH1_CCK_CCA_C_M 0x80000000 +#define PATH1_RX_C 0x3C94 +#define PATH1_RX_C_M 0x1F +#define PATH1_LNA_SETTING_C 0x3C94 +#define PATH1_LNA_SETTING_C_M 0x700 +#define PATH1_TIA_C 0x3C94 +#define PATH1_TIA_C_M 0x1000 +#define PATH1_DB2FLT_O_C 0x3C94 +#define PATH1_DB2FLT_O_C_M 0x7FF8000 +#define PATH1_LSTF_SUM_LINEAR_PW_C 0x3C98 +#define PATH1_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF +#define PATH1_LSTF_MAX_LINEAR_PW_C 0x3C9C +#define PATH1_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF +#define PATH1_TSSI_C_C 0x3CA0 +#define PATH1_TSSI_C_C_M 0x1FF +#define PATH1_TSSI_C_SRC_C 0x3CA0 +#define PATH1_TSSI_C_SRC_C_M 0x3FF000 +#define PATH1_TXAGC_TP_C 0x3CA0 +#define PATH1_TXAGC_TP_C_M 0xFF000000 +#define PATH1_LOG_VAL_O_C 0x3CA4 +#define PATH1_LOG_VAL_O_C_M 0xFFFFF +#define PATH1_TXAGC_OFST_ADJ_C 0x3CA4 +#define PATH1_TXAGC_OFST_ADJ_C_M 0xFF000000 +#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x3CA8 +#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF +#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x3CA8 +#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00 +#define PATH1_TMETER_TX_C 0x3CAC +#define PATH1_TMETER_TX_C_M 0x3F +#define PATH1_TMETER_CCA_POS_C 0x3CAC +#define PATH1_TMETER_CCA_POS_C_M 0x3F00 +#define PATH1_TMETER_CCA_NEG_C 0x3CAC +#define PATH1_TMETER_CCA_NEG_C_M 0x3F0000 +#define PATH1_AFE_ANAPAR_PW_O_C 0x3CB0 +#define PATH1_AFE_ANAPAR_PW_O_C_M 0xFF +#define PATH1_AFE_ANAPAR_CTRL_O_C 0x3CB0 +#define PATH1_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00 +#define PATH1_MUX_ST_PATH_C 0x3CB0 +#define PATH1_MUX_ST_PATH_C_M 0xF000000 +#define PATH1_TSSI_J_CCK_C 0x3CB4 +#define PATH1_TSSI_J_CCK_C_M 0x3FF +#define PATH1_TSSI_J_OFDM_C 0x3CB4 +#define PATH1_TSSI_J_OFDM_C_M 0xFFC00 +#define PATH1_TSSI_CURVE_C 0x3CB4 +#define PATH1_TSSI_CURVE_C_M 0x70000000 +#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C 0x3CB8 +#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF +#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C 0x3CB8 +#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000 +#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C 0x3E00 +#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF +#define PATH1_RO_SI_R_DATA_P_C 0x3E04 +#define PATH1_RO_SI_R_DATA_P_C_M 0xFFFFF +#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C 0x3E08 +#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7 +#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08 +#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38 +#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x3E08 +#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0 +#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08 +#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00 +#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C 0x3E08 +#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000 +#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C 0x3E08 +#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000 +#define PATH1_NRBW_AT_AGC_RDY_C 0x3E08 +#define PATH1_NRBW_AT_AGC_RDY_C_M 0x4000 +#define PATH1_TIA_SHRINK_AT_AGC_RDY_C 0x3E08 +#define PATH1_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000 +#define PATH1_P_DIFF_AT_AGC_RDY_C 0x3E08 +#define PATH1_P_DIFF_AT_AGC_RDY_C_M 0xFF0000 +#define PATH1_ELNA_IDX_AT_AGC_RDY_C 0x3E0C +#define PATH1_ELNA_IDX_AT_AGC_RDY_C_M 0x1 +#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2 +#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4 +#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8 +#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10 +#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20 +#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0 +#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000 +#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000 +#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000 +#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C +#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000 +#define PATH1_ELNA_IDX_AT_PD_HIT_C 0x3E10 +#define PATH1_ELNA_IDX_AT_PD_HIT_C_M 0x2 +#define PATH1_TIA_SAT_DET_AT_PD_HIT_C 0x3E10 +#define PATH1_TIA_SAT_DET_AT_PD_HIT_C_M 0x4 +#define PATH1_LNA_SAT_DET_AT_PD_HIT_C 0x3E10 +#define PATH1_LNA_SAT_DET_AT_PD_HIT_C_M 0x8 +#define PATH1_NRBW_AT_PD_HIT_C 0x3E10 +#define PATH1_NRBW_AT_PD_HIT_C_M 0x10 +#define PATH1_TIA_SHRINK_AT_PD_HIT_C 0x3E10 +#define PATH1_TIA_SHRINK_AT_PD_HIT_C_M 0x20 +#define PATH1_P_DIFF_AT_PD_HIT_C 0x3E10 +#define PATH1_P_DIFF_AT_PD_HIT_C_M 0x7FC0 +#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C 0x3E10 +#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000 +#define PATH1_RXIDX_AT_PD_HIT_C 0x3E10 +#define PATH1_RXIDX_AT_PD_HIT_C_M 0xF800000 +#define PATH1_TIA_IDX_AT_PD_HIT_C 0x3E10 +#define PATH1_TIA_IDX_AT_PD_HIT_C_M 0x10000000 +#define PATH1_LNA_IDX_AT_PD_HIT_C 0x3E10 +#define PATH1_LNA_IDX_AT_PD_HIT_C_M 0xE0000000 +#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2 +#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4 +#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8 +#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10 +#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20 +#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0 +#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000 +#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000 +#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000 +#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14 +#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000 +#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2 +#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4 +#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8 +#define PATH1_NRBW_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_NRBW_AT_NLGC_AGC_RDY_C_M 0x10 +#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20 +#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0 +#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000 +#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000 +#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000 +#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18 +#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000 +#define PATH1_RSSI_AT_AGC_RDY_C 0x3E1C +#define PATH1_RSSI_AT_AGC_RDY_C_M 0x3FF +#define PATH1_G_TOTAL_AT_AGC_RDY_C 0x3E1C +#define PATH1_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00 +#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C 0x3E1C +#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000 +#define PATH1_TIA_IDX_AT_AGC_RDY_C 0x3E1C +#define PATH1_TIA_IDX_AT_AGC_RDY_C_M 0x10000000 +#define PATH1_LNA_IDX_AT_AGC_RDY_C 0x3E1C +#define PATH1_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000 +#define PATH1_RSSI_ALWAYS_RUN_C 0x3E20 +#define PATH1_RSSI_ALWAYS_RUN_C_M 0x3FF +#define PATH1_TIA_SAT_DET_C 0x3E20 +#define PATH1_TIA_SAT_DET_C_M 0x400 +#define PATH1_LNA_SAT_DET_C 0x3E20 +#define PATH1_LNA_SAT_DET_C_M 0x800 +#define PATH1_NRBW_C 0x3E20 +#define PATH1_NRBW_C_M 0x1000 +#define PATH1_TIA_SHRINK_C 0x3E20 +#define PATH1_TIA_SHRINK_C_M 0x2000 +#define PATH1_G_LGC_DAGC_C 0x3E20 +#define PATH1_G_LGC_DAGC_C_M 0x3FC000 +#define PATH1_G_TOTAL_C 0x3E20 +#define PATH1_G_TOTAL_C_M 0xFFC00000 +#define PATH1_HW_SI_READ_DATA_C 0x3E24 +#define PATH1_HW_SI_READ_DATA_C_M 0xFFFFF +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x3E28 +#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800 +#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x3E2C +#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF +#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x3E2C +#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000 +#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C 0x3E30 +#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF +#define TX_ACC_EN_C 0x4000 +#define TX_ACC_EN_C_M 0x1 +#define BWD_SNR_THD_1_C 0x4004 +#define BWD_SNR_THD_1_C_M 0x3FF +#define BWD_SNR_THD_2_C 0x4004 +#define BWD_SNR_THD_2_C_M 0xFFC00 +#define BWD_SNR_THD_3_C 0x4004 +#define BWD_SNR_THD_3_C_M 0x3FF00000 +#define BWD_SEL_CONSERVE_EN_C 0x4004 +#define BWD_SEL_CONSERVE_EN_C_M 0x40000000 +#define DATA_BW_FLAG_S0_C 0x4004 +#define DATA_BW_FLAG_S0_C_M 0x80000000 +#define BWD_SNR_THD_4_C 0x4008 +#define BWD_SNR_THD_4_C_M 0x3FF +#define BWD_THD_1_C 0x4008 +#define BWD_THD_1_C_M 0xFFC00 +#define BWD_THD_2_C 0x4008 +#define BWD_THD_2_C_M 0x3FF00000 +#define DATA_BW_FLAG_S1_C 0x4008 +#define DATA_BW_FLAG_S1_C_M 0x40000000 +#define DATA_BW_FLAG_S2_C 0x4008 +#define DATA_BW_FLAG_S2_C_M 0x80000000 +#define BWD_THD_3_C 0x400C +#define BWD_THD_3_C_M 0x3FF +#define BWD_THD_4_C 0x400C +#define BWD_THD_4_C_M 0xFFC00 +#define BWD_THD_5_C 0x400C +#define BWD_THD_5_C_M 0x3FF00000 +#define DATA_BW_FLAG_S3_C 0x400C +#define DATA_BW_FLAG_S3_C_M 0x40000000 +#define MANUAL_DATA_BW_EN_C 0x400C +#define MANUAL_DATA_BW_EN_C_M 0x80000000 +#define BWD_RESERVED_1_C 0x4010 +#define BWD_RESERVED_1_C_M 0x3FF +#define BWD_RESERVED_2_C 0x4010 +#define BWD_RESERVED_2_C_M 0xFFC00 +#define BWD_RESERVED_3_C 0x4010 +#define BWD_RESERVED_3_C_M 0x3FF00000 +#define BWD_RESERVED_4_C 0x4014 +#define BWD_RESERVED_4_C_M 0x3FF +#define BWD_RESERVED_5_C 0x4014 +#define BWD_RESERVED_5_C_M 0xFFC00 +#define BWD_RESERVED_6_C 0x4014 +#define BWD_RESERVED_6_C_M 0x3FF00000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C 0x4018 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C 0x4018 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C 0x4018 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C 0x4018 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C 0x401C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C 0x401C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C 0x401C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C 0x401C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C 0x4020 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C 0x4020 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C 0x4020 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C 0x4020 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C 0x4024 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C 0x4024 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C 0x4024 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C 0x4024 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C 0x4028 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C 0x4028 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C 0x4028 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C 0x4028 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C 0x402C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C 0x402C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C 0x402C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C 0x402C +#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C 0x4030 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C 0x4030 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C 0x4030 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C 0x4030 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C 0x4034 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C 0x4034 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C 0x4034 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C 0x4034 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C 0x4038 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C 0x4038 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C 0x4038 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C 0x4038 +#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C 0x403C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C 0x403C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C 0x403C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C 0x403C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C 0x4040 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C 0x4040 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C 0x4040 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C 0x4040 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C 0x4044 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C 0x4044 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C 0x4044 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C 0x4044 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C 0x4048 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C 0x4048 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C 0x4048 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C 0x4048 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C 0x404C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C 0x404C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C 0x404C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C 0x404C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C 0x4050 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C 0x4050 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C 0x4050 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C 0x4050 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C 0x4054 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C 0x4054 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C 0x4054 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C 0x4054 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C 0x4058 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C 0x4058 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C 0x4058 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C 0x4058 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C 0x405C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C 0x405C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C 0x405C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C 0x405C +#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C 0x4060 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C 0x4060 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C 0x4060 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C 0x4060 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C 0x4064 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C 0x4064 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C 0x4064 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C 0x4064 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C 0x4068 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C 0x4068 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C 0x4068 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C 0x4068 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C 0x406C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C 0x406C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C 0x406C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C 0x406C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C 0x4070 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C 0x4070 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C 0x4070 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C 0x4070 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C 0x4074 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C 0x4074 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C 0x4074 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C 0x4074 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C 0x4078 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C 0x4078 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C 0x4078 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C 0x4078 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C 0x407C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C 0x407C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C 0x407C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C 0x407C +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C 0x4080 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C 0x4080 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C 0x4080 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C 0x4080 +#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C 0x4084 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C 0x4084 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C 0x4084 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C 0x4084 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C 0x4088 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C 0x4088 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C 0x4088 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C 0x4088 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C 0x408C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C 0x408C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C 0x408C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C 0x408C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C 0x4090 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C 0x4090 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C 0x4090 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C 0x4090 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C 0x4094 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C 0x4094 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C 0x4094 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C 0x4094 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C 0x4098 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C 0x4098 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C 0x4098 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C 0x4098 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C 0x409C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C 0x409C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C 0x409C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C 0x409C +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C 0x40A0 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C 0x40A0 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C 0x40A0 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C 0x40A0 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C 0x40A4 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C 0x40A4 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C 0x40A4 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C 0x40A4 +#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C 0x40A8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C 0x40A8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C 0x40A8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C 0x40A8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C 0x40AC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C 0x40AC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C 0x40AC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C 0x40AC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C 0x40B0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C 0x40B0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C 0x40B0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C 0x40B0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C 0x40B4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C 0x40B4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C 0x40B4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C 0x40B4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C 0x40B8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C 0x40B8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C 0x40B8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C 0x40B8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C 0x40BC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C 0x40BC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C 0x40BC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C 0x40BC +#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C 0x40C0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C 0x40C0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C 0x40C0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C 0x40C0 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C 0x40C4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C 0x40C4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C 0x40C4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C 0x40C4 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C 0x40C8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C 0x40C8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C 0x40C8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C 0x40C8 +#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C 0x40CC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C 0x40CC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C 0x40CC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C 0x40CC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C 0x40D0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C 0x40D0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C 0x40D0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C 0x40D0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C 0x40D4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C 0x40D4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C 0x40D4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C 0x40D4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C 0x40D8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C 0x40D8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C 0x40D8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C 0x40D8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C 0x40DC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C 0x40DC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C 0x40DC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C 0x40DC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C 0x40E0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C 0x40E0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C 0x40E0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C 0x40E0 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C 0x40E4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C 0x40E4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C 0x40E4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C 0x40E4 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C 0x40E8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C 0x40E8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C 0x40E8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C 0x40E8 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C_M 0xFF000000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C 0x40EC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C_M 0xFF +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C 0x40EC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C_M 0xFF00 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C 0x40EC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C_M 0xFF0000 +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C 0x40EC +#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C_M 0xFF000000 +#define NOISE_EST_COUNT_THR_C 0x40F0 +#define NOISE_EST_COUNT_THR_C_M 0x3F +#define ZERO_HOLD_FOR_1X_EN_C 0x40F0 +#define ZERO_HOLD_FOR_1X_EN_C_M 0x40 +#define ZERO_HOLD_FOR_2X_EN_C 0x40F0 +#define ZERO_HOLD_FOR_2X_EN_C_M 0x80 +#define SMOOTH_COEFF_SEL_C 0x40F4 +#define SMOOTH_COEFF_SEL_C_M 0x3 +#define V_MATRIX_INTPL_EN_C 0x40F4 +#define V_MATRIX_INTPL_EN_C_M 0x4 +#define V_MATRIX_SMO_EN_C 0x40F4 +#define V_MATRIX_SMO_EN_C_M 0x8 +#define MUIC_EN_C 0x40F8 +#define MUIC_EN_C_M 0x1 +#define DEV1_TH_NG1_BW20_C 0x40FC +#define DEV1_TH_NG1_BW20_C_M 0x3F +#define DEV1_TH_NG1_BW40_C 0x40FC +#define DEV1_TH_NG1_BW40_C_M 0xFC0 +#define DEV1_TH_NG1_BW80_C 0x40FC +#define DEV1_TH_NG1_BW80_C_M 0x3F000 +#define DEV1_TH_NG2_BW20_C 0x40FC +#define DEV1_TH_NG2_BW20_C_M 0xFC0000 +#define DEV1_TH_NG2_BW40_C 0x40FC +#define DEV1_TH_NG2_BW40_C_M 0x3F000000 +#define NONCON160M_C 0x40FC +#define NONCON160M_C_M 0x40000000 +#define AVGSNR_DIFF_EN_C 0x40FC +#define AVGSNR_DIFF_EN_C_M 0x80000000 +#define DEV1_TH_NG2_BW80_C 0x4100 +#define DEV1_TH_NG2_BW80_C_M 0x3F +#define DEV1_TH_NG4_BW20_C 0x4100 +#define DEV1_TH_NG4_BW20_C_M 0xFC0 +#define DEV1_TH_NG4_BW40_C 0x4100 +#define DEV1_TH_NG4_BW40_C_M 0x3F000 +#define DEV1_TH_NG4_BW80_C 0x4100 +#define DEV1_TH_NG4_BW80_C_M 0xFC0000 +#define DEV2_TH_NG1_BW20_C 0x4100 +#define DEV2_TH_NG1_BW20_C_M 0x3F000000 +#define BADTONE_COUNT_TH_SRC_GRPING_C 0x4100 +#define BADTONE_COUNT_TH_SRC_GRPING_C_M 0x40000000 +#define DEV2_TH_NG1_BW40_C 0x4104 +#define DEV2_TH_NG1_BW40_C_M 0x3F +#define DEV2_TH_NG1_BW80_C 0x4104 +#define DEV2_TH_NG1_BW80_C_M 0xFC0 +#define DEV2_TH_NG2_BW20_C 0x4104 +#define DEV2_TH_NG2_BW20_C_M 0x3F000 +#define DEV2_TH_NG2_BW40_C 0x4104 +#define DEV2_TH_NG2_BW40_C_M 0xFC0000 +#define DEV2_TH_NG2_BW80_C 0x4104 +#define DEV2_TH_NG2_BW80_C_M 0x3F000000 +#define DEV2_TH_NG4_BW20_C 0x4108 +#define DEV2_TH_NG4_BW20_C_M 0x3F +#define DEV2_TH_NG4_BW40_C 0x4108 +#define DEV2_TH_NG4_BW40_C_M 0xFC0 +#define DEV2_TH_NG4_BW80_C 0x4108 +#define DEV2_TH_NG4_BW80_C_M 0x3F000 +#define HE_DEV1_TH_NG16_BW20_C 0x4108 +#define HE_DEV1_TH_NG16_BW20_C_M 0xFC0000 +#define HE_DEV1_TH_NG16_BW40_C 0x4108 +#define HE_DEV1_TH_NG16_BW40_C_M 0x3F000000 +#define HE_DEV1_TH_NG16_BW80_C 0x410C +#define HE_DEV1_TH_NG16_BW80_C_M 0x3F +#define HE_DEV1_TH_NG4_BW20_C 0x410C +#define HE_DEV1_TH_NG4_BW20_C_M 0xFC0 +#define HE_DEV1_TH_NG4_BW40_C 0x410C +#define HE_DEV1_TH_NG4_BW40_C_M 0x3F000 +#define HE_DEV1_TH_NG4_BW80_C 0x410C +#define HE_DEV1_TH_NG4_BW80_C_M 0xFC0000 +#define HE_DEV2_TH_NG16_BW20_C 0x410C +#define HE_DEV2_TH_NG16_BW20_C_M 0x3F000000 +#define HE_DEV2_TH_NG16_BW40_C 0x4110 +#define HE_DEV2_TH_NG16_BW40_C_M 0x3F +#define HE_DEV2_TH_NG16_BW80_C 0x4110 +#define HE_DEV2_TH_NG16_BW80_C_M 0xFC0 +#define HE_DEV2_TH_NG4_BW20_C 0x4110 +#define HE_DEV2_TH_NG4_BW20_C_M 0x3F000 +#define HE_DEV2_TH_NG4_BW40_C 0x4110 +#define HE_DEV2_TH_NG4_BW40_C_M 0xFC0000 +#define HE_DEV2_TH_NG4_BW80_C 0x4110 +#define HE_DEV2_TH_NG4_BW80_C_M 0x3F000000 +#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C 0x4114 +#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C_M 0x3F +#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C 0x4114 +#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C_M 0xFC0 +#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C 0x4114 +#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C_M 0x3F000 +#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C 0x4114 +#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000 +#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C 0x4114 +#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000 +#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C 0x4118 +#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F +#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C 0x4118 +#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C_M 0xFC0 +#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C 0x4118 +#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C_M 0x3F000 +#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C 0x4118 +#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C_M 0xFC0000 +#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C 0x4118 +#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000000 +#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C 0x411C +#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C_M 0x3F +#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C 0x411C +#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C_M 0xFC0 +#define SNR1_MIN_CNT_TH_NG1_BW20_C 0x411C +#define SNR1_MIN_CNT_TH_NG1_BW20_C_M 0x3F000 +#define SNR1_MIN_CNT_TH_NG1_BW40_C 0x411C +#define SNR1_MIN_CNT_TH_NG1_BW40_C_M 0xFC0000 +#define SNR1_MIN_CNT_TH_NG1_BW80_C 0x411C +#define SNR1_MIN_CNT_TH_NG1_BW80_C_M 0x3F000000 +#define SNR1_MIN_CNT_TH_NG2_BW20_C 0x4120 +#define SNR1_MIN_CNT_TH_NG2_BW20_C_M 0x3F +#define SNR1_MIN_CNT_TH_NG2_BW40_C 0x4120 +#define SNR1_MIN_CNT_TH_NG2_BW40_C_M 0xFC0 +#define SNR1_MIN_CNT_TH_NG2_BW80_C 0x4120 +#define SNR1_MIN_CNT_TH_NG2_BW80_C_M 0x3F000 +#define SNR1_MIN_CNT_TH_NG4_BW20_C 0x4120 +#define SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000 +#define SNR1_MIN_CNT_TH_NG4_BW40_C 0x4120 +#define SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000 +#define SNR1_MIN_CNT_TH_NG4_BW80_C 0x4124 +#define SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F +#define SNR2_MIN_CNT_TH_NG1_BW20_C 0x4124 +#define SNR2_MIN_CNT_TH_NG1_BW20_C_M 0xFC0 +#define SNR2_MIN_CNT_TH_NG1_BW40_C 0x4124 +#define SNR2_MIN_CNT_TH_NG1_BW40_C_M 0x3F000 +#define SNR2_MIN_CNT_TH_NG1_BW80_C 0x4124 +#define SNR2_MIN_CNT_TH_NG1_BW80_C_M 0xFC0000 +#define SNR2_MIN_CNT_TH_NG2_BW20_C 0x4124 +#define SNR2_MIN_CNT_TH_NG2_BW20_C_M 0x3F000000 +#define SNR2_MIN_CNT_TH_NG2_BW40_C 0x4128 +#define SNR2_MIN_CNT_TH_NG2_BW40_C_M 0x3F +#define SNR2_MIN_CNT_TH_NG2_BW80_C 0x4128 +#define SNR2_MIN_CNT_TH_NG2_BW80_C_M 0xFC0 +#define SNR2_MIN_CNT_TH_NG4_BW20_C 0x4128 +#define SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000 +#define SNR2_MIN_CNT_TH_NG4_BW40_C 0x4128 +#define SNR2_MIN_CNT_TH_NG4_BW40_C_M 0xFC0000 +#define SNR2_MIN_CNT_TH_NG4_BW80_C 0x4128 +#define SNR2_MIN_CNT_TH_NG4_BW80_C_M 0x3F000000 +#define SNRLOSS_WGT_C 0x412C +#define SNRLOSS_WGT_C_M 0x1F +#define HE_SNR1_TH_NG16_BW20_C 0x412C +#define HE_SNR1_TH_NG16_BW20_C_M 0x1E0 +#define HE_SNR1_TH_NG16_BW40_C 0x412C +#define HE_SNR1_TH_NG16_BW40_C_M 0x1E00 +#define HE_SNR1_TH_NG16_BW80_C 0x412C +#define HE_SNR1_TH_NG16_BW80_C_M 0x1E000 +#define HE_SNR1_TH_NG4_BW20_C 0x412C +#define HE_SNR1_TH_NG4_BW20_C_M 0x1E0000 +#define HE_SNR1_TH_NG4_BW40_C 0x412C +#define HE_SNR1_TH_NG4_BW40_C_M 0x1E00000 +#define HE_SNR1_TH_NG4_BW80_C 0x412C +#define HE_SNR1_TH_NG4_BW80_C_M 0x1E000000 +#define HE_SNR2_TH_NG16_BW20_C 0x4130 +#define HE_SNR2_TH_NG16_BW20_C_M 0xF +#define HE_SNR2_TH_NG16_BW40_C 0x4130 +#define HE_SNR2_TH_NG16_BW40_C_M 0xF0 +#define HE_SNR2_TH_NG16_BW80_C 0x4130 +#define HE_SNR2_TH_NG16_BW80_C_M 0xF00 +#define HE_SNR2_TH_NG4_BW20_C 0x4130 +#define HE_SNR2_TH_NG4_BW20_C_M 0xF000 +#define HE_SNR2_TH_NG4_BW40_C 0x4130 +#define HE_SNR2_TH_NG4_BW40_C_M 0xF0000 +#define HE_SNR2_TH_NG4_BW80_C 0x4130 +#define HE_SNR2_TH_NG4_BW80_C_M 0xF00000 +#define SNR1_TH_NG1_BW20_C 0x4130 +#define SNR1_TH_NG1_BW20_C_M 0xF000000 +#define SNR1_TH_NG1_BW40_C 0x4130 +#define SNR1_TH_NG1_BW40_C_M 0xF0000000 +#define SNR1_TH_NG1_BW80_C 0x4134 +#define SNR1_TH_NG1_BW80_C_M 0xF +#define SNR1_TH_NG2_BW20_C 0x4134 +#define SNR1_TH_NG2_BW20_C_M 0xF0 +#define SNR1_TH_NG2_BW40_C 0x4134 +#define SNR1_TH_NG2_BW40_C_M 0xF00 +#define SNR1_TH_NG2_BW80_C 0x4134 +#define SNR1_TH_NG2_BW80_C_M 0xF000 +#define SNR1_TH_NG4_BW20_C 0x4134 +#define SNR1_TH_NG4_BW20_C_M 0xF0000 +#define SNR1_TH_NG4_BW40_C 0x4134 +#define SNR1_TH_NG4_BW40_C_M 0xF00000 +#define SNR1_TH_NG4_BW80_C 0x4134 +#define SNR1_TH_NG4_BW80_C_M 0xF000000 +#define SNR2_TH_NG1_BW20_C 0x4134 +#define SNR2_TH_NG1_BW20_C_M 0xF0000000 +#define SNR2_TH_NG1_BW40_C 0x4138 +#define SNR2_TH_NG1_BW40_C_M 0xF +#define SNR2_TH_NG1_BW80_C 0x4138 +#define SNR2_TH_NG1_BW80_C_M 0xF0 +#define SNR2_TH_NG2_BW20_C 0x4138 +#define SNR2_TH_NG2_BW20_C_M 0xF00 +#define SNR2_TH_NG2_BW40_C 0x4138 +#define SNR2_TH_NG2_BW40_C_M 0xF000 +#define SNR2_TH_NG2_BW80_C 0x4138 +#define SNR2_TH_NG2_BW80_C_M 0xF0000 +#define SNR2_TH_NG4_BW20_C 0x4138 +#define SNR2_TH_NG4_BW20_C_M 0xF00000 +#define SNR2_TH_NG4_BW40_C 0x4138 +#define SNR2_TH_NG4_BW40_C_M 0xF000000 +#define SNR2_TH_NG4_BW80_C 0x4138 +#define SNR2_TH_NG4_BW80_C_M 0xF0000000 +#define AVGSNR_DIFF_TH_C 0x413C +#define AVGSNR_DIFF_TH_C_M 0xF +#define OTHERSNR_WGT_C 0x413C +#define OTHERSNR_WGT_C_M 0xF0 +#define PDP_AWGN_FLAG_SUB_TUNE_C 0x4140 +#define PDP_AWGN_FLAG_SUB_TUNE_C_M 0x3FF +#define PDP_SNR_SHIFT_FOR_NONLEGACY_C 0x4140 +#define PDP_SNR_SHIFT_FOR_NONLEGACY_C_M 0xFFC00 +#define PDP_CORR_DIST1_W0_C 0x4140 +#define PDP_CORR_DIST1_W0_C_M 0x3FF00000 +#define GI_COMB_EN_C 0x4140 +#define GI_COMB_EN_C_M 0x40000000 +#define PDP_ALL_COMBINE_EN_C 0x4140 +#define PDP_ALL_COMBINE_EN_C_M 0x80000000 +#define PDP_CORR_DIST1_W1_C 0x4144 +#define PDP_CORR_DIST1_W1_C_M 0x3FF +#define PDP_CORR_DIST1_W10_C 0x4144 +#define PDP_CORR_DIST1_W10_C_M 0xFFC00 +#define PDP_CORR_DIST1_W11_C 0x4144 +#define PDP_CORR_DIST1_W11_C_M 0x3FF00000 +#define MANUAL_GD_PHASE_EN_C 0x4144 +#define MANUAL_GD_PHASE_EN_C_M 0x40000000 +#define MANUAL_SNR_IDX_EN_C 0x4144 +#define MANUAL_SNR_IDX_EN_C_M 0x80000000 +#define PDP_CORR_DIST1_W12_C 0x4148 +#define PDP_CORR_DIST1_W12_C_M 0x3FF +#define PDP_CORR_DIST1_W13_C 0x4148 +#define PDP_CORR_DIST1_W13_C_M 0xFFC00 +#define PDP_CORR_DIST1_W14_C 0x4148 +#define PDP_CORR_DIST1_W14_C_M 0x3FF00000 +#define MANUAL_TMAX_IDX_EN_C 0x4148 +#define MANUAL_TMAX_IDX_EN_C_M 0x40000000 +#define PDP_CORR_DIST1_W15_C 0x414C +#define PDP_CORR_DIST1_W15_C_M 0x3FF +#define PDP_CORR_DIST1_W16_C 0x414C +#define PDP_CORR_DIST1_W16_C_M 0xFFC00 +#define PDP_CORR_DIST1_W17_C 0x414C +#define PDP_CORR_DIST1_W17_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W18_C 0x4150 +#define PDP_CORR_DIST1_W18_C_M 0x3FF +#define PDP_CORR_DIST1_W19_C 0x4150 +#define PDP_CORR_DIST1_W19_C_M 0xFFC00 +#define PDP_CORR_DIST1_W2_C 0x4150 +#define PDP_CORR_DIST1_W2_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W20_C 0x4154 +#define PDP_CORR_DIST1_W20_C_M 0x3FF +#define PDP_CORR_DIST1_W21_C 0x4154 +#define PDP_CORR_DIST1_W21_C_M 0xFFC00 +#define PDP_CORR_DIST1_W22_C 0x4154 +#define PDP_CORR_DIST1_W22_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W23_C 0x4158 +#define PDP_CORR_DIST1_W23_C_M 0x3FF +#define PDP_CORR_DIST1_W24_C 0x4158 +#define PDP_CORR_DIST1_W24_C_M 0xFFC00 +#define PDP_CORR_DIST1_W25_C 0x4158 +#define PDP_CORR_DIST1_W25_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W26_C 0x415C +#define PDP_CORR_DIST1_W26_C_M 0x3FF +#define PDP_CORR_DIST1_W27_C 0x415C +#define PDP_CORR_DIST1_W27_C_M 0xFFC00 +#define PDP_CORR_DIST1_W28_C 0x415C +#define PDP_CORR_DIST1_W28_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W29_C 0x4160 +#define PDP_CORR_DIST1_W29_C_M 0x3FF +#define PDP_CORR_DIST1_W3_C 0x4160 +#define PDP_CORR_DIST1_W3_C_M 0xFFC00 +#define PDP_CORR_DIST1_W30_C 0x4160 +#define PDP_CORR_DIST1_W30_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W31_C 0x4164 +#define PDP_CORR_DIST1_W31_C_M 0x3FF +#define PDP_CORR_DIST1_W32_C 0x4164 +#define PDP_CORR_DIST1_W32_C_M 0xFFC00 +#define PDP_CORR_DIST1_W33_C 0x4164 +#define PDP_CORR_DIST1_W33_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W34_C 0x4168 +#define PDP_CORR_DIST1_W34_C_M 0x3FF +#define PDP_CORR_DIST1_W35_C 0x4168 +#define PDP_CORR_DIST1_W35_C_M 0xFFC00 +#define PDP_CORR_DIST1_W36_C 0x4168 +#define PDP_CORR_DIST1_W36_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W37_C 0x416C +#define PDP_CORR_DIST1_W37_C_M 0x3FF +#define PDP_CORR_DIST1_W38_C 0x416C +#define PDP_CORR_DIST1_W38_C_M 0xFFC00 +#define PDP_CORR_DIST1_W39_C 0x416C +#define PDP_CORR_DIST1_W39_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W4_C 0x4170 +#define PDP_CORR_DIST1_W4_C_M 0x3FF +#define PDP_CORR_DIST1_W40_C 0x4170 +#define PDP_CORR_DIST1_W40_C_M 0xFFC00 +#define PDP_CORR_DIST1_W41_C 0x4170 +#define PDP_CORR_DIST1_W41_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W42_C 0x4174 +#define PDP_CORR_DIST1_W42_C_M 0x3FF +#define PDP_CORR_DIST1_W43_C 0x4174 +#define PDP_CORR_DIST1_W43_C_M 0xFFC00 +#define PDP_CORR_DIST1_W44_C 0x4174 +#define PDP_CORR_DIST1_W44_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W45_C 0x4178 +#define PDP_CORR_DIST1_W45_C_M 0x3FF +#define PDP_CORR_DIST1_W46_C 0x4178 +#define PDP_CORR_DIST1_W46_C_M 0xFFC00 +#define PDP_CORR_DIST1_W47_C 0x4178 +#define PDP_CORR_DIST1_W47_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W5_C 0x417C +#define PDP_CORR_DIST1_W5_C_M 0x3FF +#define PDP_CORR_DIST1_W6_C 0x417C +#define PDP_CORR_DIST1_W6_C_M 0xFFC00 +#define PDP_CORR_DIST1_W7_C 0x417C +#define PDP_CORR_DIST1_W7_C_M 0x3FF00000 +#define PDP_CORR_DIST1_W8_C 0x4180 +#define PDP_CORR_DIST1_W8_C_M 0x3FF +#define PDP_CORR_DIST1_W9_C 0x4180 +#define PDP_CORR_DIST1_W9_C_M 0xFFC00 +#define PDP_CORR_DIST2_W0_C 0x4180 +#define PDP_CORR_DIST2_W0_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W1_C 0x4184 +#define PDP_CORR_DIST2_W1_C_M 0x3FF +#define PDP_CORR_DIST2_W10_C 0x4184 +#define PDP_CORR_DIST2_W10_C_M 0xFFC00 +#define PDP_CORR_DIST2_W11_C 0x4184 +#define PDP_CORR_DIST2_W11_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W12_C 0x4188 +#define PDP_CORR_DIST2_W12_C_M 0x3FF +#define PDP_CORR_DIST2_W13_C 0x4188 +#define PDP_CORR_DIST2_W13_C_M 0xFFC00 +#define PDP_CORR_DIST2_W14_C 0x4188 +#define PDP_CORR_DIST2_W14_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W15_C 0x418C +#define PDP_CORR_DIST2_W15_C_M 0x3FF +#define PDP_CORR_DIST2_W16_C 0x418C +#define PDP_CORR_DIST2_W16_C_M 0xFFC00 +#define PDP_CORR_DIST2_W17_C 0x418C +#define PDP_CORR_DIST2_W17_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W18_C 0x4190 +#define PDP_CORR_DIST2_W18_C_M 0x3FF +#define PDP_CORR_DIST2_W19_C 0x4190 +#define PDP_CORR_DIST2_W19_C_M 0xFFC00 +#define PDP_CORR_DIST2_W2_C 0x4190 +#define PDP_CORR_DIST2_W2_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W20_C 0x4194 +#define PDP_CORR_DIST2_W20_C_M 0x3FF +#define PDP_CORR_DIST2_W21_C 0x4194 +#define PDP_CORR_DIST2_W21_C_M 0xFFC00 +#define PDP_CORR_DIST2_W22_C 0x4194 +#define PDP_CORR_DIST2_W22_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W23_C 0x4198 +#define PDP_CORR_DIST2_W23_C_M 0x3FF +#define PDP_CORR_DIST2_W24_C 0x4198 +#define PDP_CORR_DIST2_W24_C_M 0xFFC00 +#define PDP_CORR_DIST2_W25_C 0x4198 +#define PDP_CORR_DIST2_W25_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W26_C 0x419C +#define PDP_CORR_DIST2_W26_C_M 0x3FF +#define PDP_CORR_DIST2_W27_C 0x419C +#define PDP_CORR_DIST2_W27_C_M 0xFFC00 +#define PDP_CORR_DIST2_W28_C 0x419C +#define PDP_CORR_DIST2_W28_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W29_C 0x41A0 +#define PDP_CORR_DIST2_W29_C_M 0x3FF +#define PDP_CORR_DIST2_W3_C 0x41A0 +#define PDP_CORR_DIST2_W3_C_M 0xFFC00 +#define PDP_CORR_DIST2_W30_C 0x41A0 +#define PDP_CORR_DIST2_W30_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W31_C 0x41A4 +#define PDP_CORR_DIST2_W31_C_M 0x3FF +#define PDP_CORR_DIST2_W32_C 0x41A4 +#define PDP_CORR_DIST2_W32_C_M 0xFFC00 +#define PDP_CORR_DIST2_W33_C 0x41A4 +#define PDP_CORR_DIST2_W33_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W34_C 0x41A8 +#define PDP_CORR_DIST2_W34_C_M 0x3FF +#define PDP_CORR_DIST2_W35_C 0x41A8 +#define PDP_CORR_DIST2_W35_C_M 0xFFC00 +#define PDP_CORR_DIST2_W36_C 0x41A8 +#define PDP_CORR_DIST2_W36_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W37_C 0x41AC +#define PDP_CORR_DIST2_W37_C_M 0x3FF +#define PDP_CORR_DIST2_W38_C 0x41AC +#define PDP_CORR_DIST2_W38_C_M 0xFFC00 +#define PDP_CORR_DIST2_W39_C 0x41AC +#define PDP_CORR_DIST2_W39_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W4_C 0x41B0 +#define PDP_CORR_DIST2_W4_C_M 0x3FF +#define PDP_CORR_DIST2_W40_C 0x41B0 +#define PDP_CORR_DIST2_W40_C_M 0xFFC00 +#define PDP_CORR_DIST2_W41_C 0x41B0 +#define PDP_CORR_DIST2_W41_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W42_C 0x41B4 +#define PDP_CORR_DIST2_W42_C_M 0x3FF +#define PDP_CORR_DIST2_W43_C 0x41B4 +#define PDP_CORR_DIST2_W43_C_M 0xFFC00 +#define PDP_CORR_DIST2_W44_C 0x41B4 +#define PDP_CORR_DIST2_W44_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W45_C 0x41B8 +#define PDP_CORR_DIST2_W45_C_M 0x3FF +#define PDP_CORR_DIST2_W46_C 0x41B8 +#define PDP_CORR_DIST2_W46_C_M 0xFFC00 +#define PDP_CORR_DIST2_W47_C 0x41B8 +#define PDP_CORR_DIST2_W47_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W5_C 0x41BC +#define PDP_CORR_DIST2_W5_C_M 0x3FF +#define PDP_CORR_DIST2_W6_C 0x41BC +#define PDP_CORR_DIST2_W6_C_M 0xFFC00 +#define PDP_CORR_DIST2_W7_C 0x41BC +#define PDP_CORR_DIST2_W7_C_M 0x3FF00000 +#define PDP_CORR_DIST2_W8_C 0x41C0 +#define PDP_CORR_DIST2_W8_C_M 0x3FF +#define PDP_CORR_DIST2_W9_C 0x41C0 +#define PDP_CORR_DIST2_W9_C_M 0xFFC00 +#define PDP_CORR_DIST3_W0_C 0x41C0 +#define PDP_CORR_DIST3_W0_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W1_C 0x41C4 +#define PDP_CORR_DIST3_W1_C_M 0x3FF +#define PDP_CORR_DIST3_W10_C 0x41C4 +#define PDP_CORR_DIST3_W10_C_M 0xFFC00 +#define PDP_CORR_DIST3_W11_C 0x41C4 +#define PDP_CORR_DIST3_W11_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W12_C 0x41C8 +#define PDP_CORR_DIST3_W12_C_M 0x3FF +#define PDP_CORR_DIST3_W13_C 0x41C8 +#define PDP_CORR_DIST3_W13_C_M 0xFFC00 +#define PDP_CORR_DIST3_W14_C 0x41C8 +#define PDP_CORR_DIST3_W14_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W15_C 0x41CC +#define PDP_CORR_DIST3_W15_C_M 0x3FF +#define PDP_CORR_DIST3_W16_C 0x41CC +#define PDP_CORR_DIST3_W16_C_M 0xFFC00 +#define PDP_CORR_DIST3_W17_C 0x41CC +#define PDP_CORR_DIST3_W17_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W18_C 0x41D0 +#define PDP_CORR_DIST3_W18_C_M 0x3FF +#define PDP_CORR_DIST3_W19_C 0x41D0 +#define PDP_CORR_DIST3_W19_C_M 0xFFC00 +#define PDP_CORR_DIST3_W2_C 0x41D0 +#define PDP_CORR_DIST3_W2_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W20_C 0x41D4 +#define PDP_CORR_DIST3_W20_C_M 0x3FF +#define PDP_CORR_DIST3_W21_C 0x41D4 +#define PDP_CORR_DIST3_W21_C_M 0xFFC00 +#define PDP_CORR_DIST3_W22_C 0x41D4 +#define PDP_CORR_DIST3_W22_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W23_C 0x41D8 +#define PDP_CORR_DIST3_W23_C_M 0x3FF +#define PDP_CORR_DIST3_W24_C 0x41D8 +#define PDP_CORR_DIST3_W24_C_M 0xFFC00 +#define PDP_CORR_DIST3_W25_C 0x41D8 +#define PDP_CORR_DIST3_W25_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W26_C 0x41DC +#define PDP_CORR_DIST3_W26_C_M 0x3FF +#define PDP_CORR_DIST3_W27_C 0x41DC +#define PDP_CORR_DIST3_W27_C_M 0xFFC00 +#define PDP_CORR_DIST3_W28_C 0x41DC +#define PDP_CORR_DIST3_W28_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W29_C 0x41E0 +#define PDP_CORR_DIST3_W29_C_M 0x3FF +#define PDP_CORR_DIST3_W3_C 0x41E0 +#define PDP_CORR_DIST3_W3_C_M 0xFFC00 +#define PDP_CORR_DIST3_W30_C 0x41E0 +#define PDP_CORR_DIST3_W30_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W31_C 0x41E4 +#define PDP_CORR_DIST3_W31_C_M 0x3FF +#define PDP_CORR_DIST3_W32_C 0x41E4 +#define PDP_CORR_DIST3_W32_C_M 0xFFC00 +#define PDP_CORR_DIST3_W33_C 0x41E4 +#define PDP_CORR_DIST3_W33_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W34_C 0x41E8 +#define PDP_CORR_DIST3_W34_C_M 0x3FF +#define PDP_CORR_DIST3_W35_C 0x41E8 +#define PDP_CORR_DIST3_W35_C_M 0xFFC00 +#define PDP_CORR_DIST3_W36_C 0x41E8 +#define PDP_CORR_DIST3_W36_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W37_C 0x41EC +#define PDP_CORR_DIST3_W37_C_M 0x3FF +#define PDP_CORR_DIST3_W38_C 0x41EC +#define PDP_CORR_DIST3_W38_C_M 0xFFC00 +#define PDP_CORR_DIST3_W39_C 0x41EC +#define PDP_CORR_DIST3_W39_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W4_C 0x41F0 +#define PDP_CORR_DIST3_W4_C_M 0x3FF +#define PDP_CORR_DIST3_W40_C 0x41F0 +#define PDP_CORR_DIST3_W40_C_M 0xFFC00 +#define PDP_CORR_DIST3_W41_C 0x41F0 +#define PDP_CORR_DIST3_W41_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W42_C 0x41F4 +#define PDP_CORR_DIST3_W42_C_M 0x3FF +#define PDP_CORR_DIST3_W43_C 0x41F4 +#define PDP_CORR_DIST3_W43_C_M 0xFFC00 +#define PDP_CORR_DIST3_W44_C 0x41F4 +#define PDP_CORR_DIST3_W44_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W45_C 0x41F8 +#define PDP_CORR_DIST3_W45_C_M 0x3FF +#define PDP_CORR_DIST3_W46_C 0x41F8 +#define PDP_CORR_DIST3_W46_C_M 0xFFC00 +#define PDP_CORR_DIST3_W47_C 0x41F8 +#define PDP_CORR_DIST3_W47_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W5_C 0x41FC +#define PDP_CORR_DIST3_W5_C_M 0x3FF +#define PDP_CORR_DIST3_W6_C 0x41FC +#define PDP_CORR_DIST3_W6_C_M 0xFFC00 +#define PDP_CORR_DIST3_W7_C 0x41FC +#define PDP_CORR_DIST3_W7_C_M 0x3FF00000 +#define PDP_CORR_DIST3_W8_C 0x4200 +#define PDP_CORR_DIST3_W8_C_M 0x3FF +#define PDP_CORR_DIST3_W9_C 0x4200 +#define PDP_CORR_DIST3_W9_C_M 0xFFC00 +#define GD_PHASE_LEG_R0S0_C 0x4200 +#define GD_PHASE_LEG_R0S0_C_M 0xFF00000 +#define TMAX_IDX_LEG_R0_C 0x4200 +#define TMAX_IDX_LEG_R0_C_M 0xF0000000 +#define GD_PHASE_LEG_R0S1_C 0x4204 +#define GD_PHASE_LEG_R0S1_C_M 0xFF +#define GD_PHASE_LEG_R0S2_C 0x4204 +#define GD_PHASE_LEG_R0S2_C_M 0xFF00 +#define GD_PHASE_LEG_R0S3_C 0x4204 +#define GD_PHASE_LEG_R0S3_C_M 0xFF0000 +#define GD_PHASE_LEG_R1S0_C 0x4204 +#define GD_PHASE_LEG_R1S0_C_M 0xFF000000 +#define GD_PHASE_LEG_R1S1_C 0x4208 +#define GD_PHASE_LEG_R1S1_C_M 0xFF +#define GD_PHASE_LEG_R1S2_C 0x4208 +#define GD_PHASE_LEG_R1S2_C_M 0xFF00 +#define GD_PHASE_LEG_R1S3_C 0x4208 +#define GD_PHASE_LEG_R1S3_C_M 0xFF0000 +#define GD_PHASE_NON_LEG_R0S0_C 0x4208 +#define GD_PHASE_NON_LEG_R0S0_C_M 0xFF000000 +#define GD_PHASE_NON_LEG_R0S1_C 0x420C +#define GD_PHASE_NON_LEG_R0S1_C_M 0xFF +#define GD_PHASE_NON_LEG_R1S0_C 0x420C +#define GD_PHASE_NON_LEG_R1S0_C_M 0xFF00 +#define GD_PHASE_NON_LEG_R1S1_C 0x420C +#define GD_PHASE_NON_LEG_R1S1_C_M 0xFF0000 +#define GI_FCTR_LEGACY_0_C 0x420C +#define GI_FCTR_LEGACY_0_C_M 0x7F000000 +#define GI_FCTR_LEGACY_1_C 0x4210 +#define GI_FCTR_LEGACY_1_C_M 0x7F +#define GI_FCTR_LEGACY_2_C 0x4210 +#define GI_FCTR_LEGACY_2_C_M 0x3F80 +#define GI_FCTR_LEGACY_3_C 0x4210 +#define GI_FCTR_LEGACY_3_C_M 0x1FC000 +#define GI_FCTR_LEGACY_4_C 0x4210 +#define GI_FCTR_LEGACY_4_C_M 0xFE00000 +#define TMAX_IDX_LEG_R1_C 0x4210 +#define TMAX_IDX_LEG_R1_C_M 0xF0000000 +#define GI_FCTR_LEGACY_5_C 0x4214 +#define GI_FCTR_LEGACY_5_C_M 0x7F +#define GI_FCTR_NONLEGACY_0_C 0x4214 +#define GI_FCTR_NONLEGACY_0_C_M 0x3F80 +#define GI_FCTR_NONLEGACY_1_C 0x4214 +#define GI_FCTR_NONLEGACY_1_C_M 0x1FC000 +#define GI_FCTR_NONLEGACY_2_C 0x4214 +#define GI_FCTR_NONLEGACY_2_C_M 0xFE00000 +#define TMAX_IDX_NON_LEG_R0_C 0x4214 +#define TMAX_IDX_NON_LEG_R0_C_M 0xF0000000 +#define GI_FCTR_NONLEGACY_3_C 0x4218 +#define GI_FCTR_NONLEGACY_3_C_M 0x7F +#define GI_FCTR_NONLEGACY_4_C 0x4218 +#define GI_FCTR_NONLEGACY_4_C_M 0x3F80 +#define GI_FCTR_NONLEGACY_5_C 0x4218 +#define GI_FCTR_NONLEGACY_5_C_M 0x1FC000 +#define SNR_LVL_0_C 0x4218 +#define SNR_LVL_0_C_M 0x7E00000 +#define HE_NUM_BAND_EDGE_TONE_C 0x4218 +#define HE_NUM_BAND_EDGE_TONE_C_M 0xF8000000 +#define SNR_LVL_1_C 0x421C +#define SNR_LVL_1_C_M 0x3F +#define SNR_LVL_2_C 0x421C +#define SNR_LVL_2_C_M 0xFC0 +#define SNR_LVL_3_C 0x421C +#define SNR_LVL_3_C_M 0x3F000 +#define SNR_LVL_4_C 0x421C +#define SNR_LVL_4_C_M 0xFC0000 +#define SNR_LVL_5_C 0x421C +#define SNR_LVL_5_C_M 0x3F000000 +#define SNR_SMO_THR_C 0x4220 +#define SNR_SMO_THR_C_M 0x3F +#define SNR_SMO_THR_1XLTF_C 0x4220 +#define SNR_SMO_THR_1XLTF_C_M 0xFC0 +#define SNR_SMO_THR_2XLTF_C 0x4220 +#define SNR_SMO_THR_2XLTF_C_M 0x3F000 +#define PDP_INSIDE_PHASE_ROTATE_C 0x4220 +#define PDP_INSIDE_PHASE_ROTATE_C_M 0x7C0000 +#define PDP_WGT_DIST_1X_C 0x4220 +#define PDP_WGT_DIST_1X_C_M 0xF800000 +#define TMAX_IDX_NON_LEG_R0S0_C 0x4220 +#define TMAX_IDX_NON_LEG_R0S0_C_M 0xF0000000 +#define PDP_WGT_DIST_2X_C 0x4224 +#define PDP_WGT_DIST_2X_C_M 0x1F +#define PDP_WGT_DIST_3X_C 0x4224 +#define PDP_WGT_DIST_3X_C_M 0x3E0 +#define TMAX_IDX_NON_LEG_R0S1_C 0x4224 +#define TMAX_IDX_NON_LEG_R0S1_C_M 0x3C00 +#define TMAX_IDX_NON_LEG_R1S0_C 0x4224 +#define TMAX_IDX_NON_LEG_R1S0_C_M 0x3C000 +#define TMAX_IDX_NON_LEG_R1S1_C 0x4224 +#define TMAX_IDX_NON_LEG_R1S1_C_M 0x3C0000 +#define SNR_IDX_LEG_R0_C 0x4224 +#define SNR_IDX_LEG_R0_C_M 0x1C00000 +#define SNR_IDX_LEG_R1_C 0x4224 +#define SNR_IDX_LEG_R1_C_M 0xE000000 +#define SNR_IDX_NON_LEG_R0S0_C 0x4224 +#define SNR_IDX_NON_LEG_R0S0_C_M 0x70000000 +#define SNR_IDX_NON_LEG_R0S1_C 0x4228 +#define SNR_IDX_NON_LEG_R0S1_C_M 0x7 +#define SNR_IDX_NON_LEG_R1S0_C 0x4228 +#define SNR_IDX_NON_LEG_R1S0_C_M 0x38 +#define SNR_IDX_NON_LEG_R1S1_C 0x4228 +#define SNR_IDX_NON_LEG_R1S1_C_M 0x1C0 +#define NUM_BAND_EDGE_TONE_C 0x4228 +#define NUM_BAND_EDGE_TONE_C_M 0xE00 +#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C 0x4228 +#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C_M 0x7000 +#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C 0x4228 +#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C_M 0x38000 +#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C 0x4228 +#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C_M 0x1C0000 +#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C 0x4228 +#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C_M 0xE00000 +#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C 0x4228 +#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C_M 0x7000000 +#define PSD_FFT_IDX_C 0x422C +#define PSD_FFT_IDX_C_M 0x7FF +#define PSD_IQ_SEL_C 0x422C +#define PSD_IQ_SEL_C_M 0x1800 +#define PSD_L_AVG_C 0x422C +#define PSD_L_AVG_C_M 0x6000 +#define PSD_N_DFT_C 0x422C +#define PSD_N_DFT_C_M 0x18000 +#define PSD_IN_PATH_SEL_C 0x422C +#define PSD_IN_PATH_SEL_C_M 0x60000 +#define PSD_IN_SOURCE_SEL_C 0x422C +#define PSD_IN_SOURCE_SEL_C_M 0x180000 +#define PSD_START_C 0x422C +#define PSD_START_C_M 0x200000 +#define PSD_ENABLE_C 0x422C +#define PSD_ENABLE_C_M 0x400000 +#define K_SEL_1024QAM_SNR_TH1_C 0x4230 +#define K_SEL_1024QAM_SNR_TH1_C_M 0x3F +#define K_SEL_1024QAM_SNR_TH2_C 0x4230 +#define K_SEL_1024QAM_SNR_TH2_C_M 0xFC0 +#define K_SEL_1024QAM_SNR_TH3_C 0x4230 +#define K_SEL_1024QAM_SNR_TH3_C_M 0x3F000 +#define K_SEL_1024QAM_SNR_TH4_C 0x4230 +#define K_SEL_1024QAM_SNR_TH4_C_M 0xFC0000 +#define K_SEL_1024QAM_SNR_TH5_C 0x4230 +#define K_SEL_1024QAM_SNR_TH5_C_M 0x3F000000 +#define K_SEL_EN_C 0x4230 +#define K_SEL_EN_C_M 0x40000000 +#define K_SEL_USE_CONDNUM_EN_C 0x4230 +#define K_SEL_USE_CONDNUM_EN_C_M 0x80000000 +#define K_SEL_16QAM_SNR_TH1_C 0x4234 +#define K_SEL_16QAM_SNR_TH1_C_M 0x3F +#define K_SEL_16QAM_SNR_TH2_C 0x4234 +#define K_SEL_16QAM_SNR_TH2_C_M 0xFC0 +#define K_SEL_16QAM_SNR_TH3_C 0x4234 +#define K_SEL_16QAM_SNR_TH3_C_M 0x3F000 +#define K_SEL_256QAM_SNR_TH1_C 0x4234 +#define K_SEL_256QAM_SNR_TH1_C_M 0xFC0000 +#define K_SEL_256QAM_SNR_TH2_C 0x4234 +#define K_SEL_256QAM_SNR_TH2_C_M 0x3F000000 +#define MANUAL_SET_K_FCTR_C 0x4234 +#define MANUAL_SET_K_FCTR_C_M 0x40000000 +#define K_SEL_256QAM_SNR_TH3_C 0x4238 +#define K_SEL_256QAM_SNR_TH3_C_M 0x3F +#define K_SEL_256QAM_SNR_TH4_C 0x4238 +#define K_SEL_256QAM_SNR_TH4_C_M 0xFC0 +#define K_SEL_256QAM_SNR_TH5_C 0x4238 +#define K_SEL_256QAM_SNR_TH5_C_M 0x3F000 +#define K_SEL_64QAM_SNR_TH1_C 0x4238 +#define K_SEL_64QAM_SNR_TH1_C_M 0xFC0000 +#define K_SEL_64QAM_SNR_TH2_C 0x4238 +#define K_SEL_64QAM_SNR_TH2_C_M 0x3F000000 +#define K_SEL_64QAM_SNR_TH3_C 0x423C +#define K_SEL_64QAM_SNR_TH3_C_M 0x3F +#define K_SEL_64QAM_SNR_TH4_C 0x423C +#define K_SEL_64QAM_SNR_TH4_C_M 0xFC0 +#define K_SEL_64QAM_SNR_TH5_C 0x423C +#define K_SEL_64QAM_SNR_TH5_C_M 0x3F000 +#define K_SEL_1024QAM_CH_C 0x423C +#define K_SEL_1024QAM_CH_C_M 0x1C0000 +#define K_SEL_1024QAM_L1_C 0x423C +#define K_SEL_1024QAM_L1_C_M 0xE00000 +#define K_SEL_1024QAM_L2_C 0x423C +#define K_SEL_1024QAM_L2_C_M 0x7000000 +#define K_SEL_1024QAM_L3_C 0x423C +#define K_SEL_1024QAM_L3_C_M 0x38000000 +#define K_SEL_1024QAM_L4_C 0x4240 +#define K_SEL_1024QAM_L4_C_M 0x7 +#define K_SEL_1024QAM_L5_C 0x4240 +#define K_SEL_1024QAM_L5_C_M 0x38 +#define K_SEL_1024QAM_CONDNUM_TH_C 0x4240 +#define K_SEL_1024QAM_CONDNUM_TH_C_M 0x1C0 +#define K_SEL_16QAM_CH_C 0x4240 +#define K_SEL_16QAM_CH_C_M 0xE00 +#define K_SEL_16QAM_L1_C 0x4240 +#define K_SEL_16QAM_L1_C_M 0x7000 +#define K_SEL_16QAM_L2_C 0x4240 +#define K_SEL_16QAM_L2_C_M 0x38000 +#define K_SEL_16QAM_L3_C 0x4240 +#define K_SEL_16QAM_L3_C_M 0x1C0000 +#define K_SEL_16QAM_CONDNUM_TH_C 0x4240 +#define K_SEL_16QAM_CONDNUM_TH_C_M 0xE00000 +#define K_SEL_256QAM_CH_C 0x4240 +#define K_SEL_256QAM_CH_C_M 0x7000000 +#define K_SEL_256QAM_L1_C 0x4240 +#define K_SEL_256QAM_L1_C_M 0x38000000 +#define K_SEL_256QAM_L2_C 0x4244 +#define K_SEL_256QAM_L2_C_M 0x7 +#define K_SEL_256QAM_L3_C 0x4244 +#define K_SEL_256QAM_L3_C_M 0x38 +#define K_SEL_256QAM_L4_C 0x4244 +#define K_SEL_256QAM_L4_C_M 0x1C0 +#define K_SEL_256QAM_L5_C 0x4244 +#define K_SEL_256QAM_L5_C_M 0xE00 +#define K_SEL_256QAM_CONDNUM_TH_C 0x4244 +#define K_SEL_256QAM_CONDNUM_TH_C_M 0x7000 +#define K_SEL_64QAM_CH_C 0x4244 +#define K_SEL_64QAM_CH_C_M 0x38000 +#define K_SEL_64QAM_L1_C 0x4244 +#define K_SEL_64QAM_L1_C_M 0x1C0000 +#define K_SEL_64QAM_L2_C 0x4244 +#define K_SEL_64QAM_L2_C_M 0xE00000 +#define K_SEL_64QAM_L3_C 0x4244 +#define K_SEL_64QAM_L3_C_M 0x7000000 +#define K_SEL_64QAM_L4_C 0x4244 +#define K_SEL_64QAM_L4_C_M 0x38000000 +#define K_SEL_64QAM_L5_C 0x4248 +#define K_SEL_64QAM_L5_C_M 0x7 +#define K_SEL_64QAM_CONDNUM_TH_C 0x4248 +#define K_SEL_64QAM_CONDNUM_TH_C_M 0x38 +#define INDI_QBPSK_CHK_EN_C 0x424C +#define INDI_QBPSK_CHK_EN_C_M 0x1 +#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C 0x4250 +#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C_M 0x1 +#define MPDU_OK_CNT_USR0_TAR_CONTENT_C 0x4258 +#define MPDU_OK_CNT_USR0_TAR_CONTENT_C_M 0xFFFF +#define MPDU_OK_CNT_USR1_TAR_CONTENT_C 0x4258 +#define MPDU_OK_CNT_USR1_TAR_CONTENT_C_M 0xFFFF0000 +#define MPDU_OK_CNT_USR2_TAR_CONTENT_C 0x425C +#define MPDU_OK_CNT_USR2_TAR_CONTENT_C_M 0xFFFF +#define MPDU_OK_CNT_USR3_TAR_CONTENT_C 0x425C +#define MPDU_OK_CNT_USR3_TAR_CONTENT_C_M 0xFFFF0000 +#define TARGET_FRAME_TYPE_C 0x4260 +#define TARGET_FRAME_TYPE_C_M 0xFF +#define TARGET_MAC_ADDRESS_8BITS_C 0x4260 +#define TARGET_MAC_ADDRESS_8BITS_C_M 0xFF00 +#define MPDU_OK_CNT_MODE_C 0x4260 +#define MPDU_OK_CNT_MODE_C_M 0x70000 +#define VHT_USR_POSITION_C 0x4260 +#define VHT_USR_POSITION_C_M 0x180000 +#define MPDU_OK_CNT_USR0_EN_C 0x4260 +#define MPDU_OK_CNT_USR0_EN_C_M 0x200000 +#define MPDU_OK_CNT_USR1_EN_C 0x4260 +#define MPDU_OK_CNT_USR1_EN_C_M 0x400000 +#define MPDU_OK_CNT_USR2_EN_C 0x4260 +#define MPDU_OK_CNT_USR2_EN_C_M 0x800000 +#define MPDU_OK_CNT_USR3_EN_C 0x4260 +#define MPDU_OK_CNT_USR3_EN_C_M 0x1000000 +#define TARGET_FRAME_TYPE_EN_C 0x4260 +#define TARGET_FRAME_TYPE_EN_C_M 0x2000000 +#define TARGET_MAC_ADDRESS_LSB_EN_C 0x4260 +#define TARGET_MAC_ADDRESS_LSB_EN_C_M 0x4000000 +#define MANUAL_TD_CFO_SEG0_C 0x426C +#define MANUAL_TD_CFO_SEG0_C_M 0xFFF +#define MANUAL_TD_CFO_SEG1_C 0x426C +#define MANUAL_TD_CFO_SEG1_C_M 0xFFF000 +#define SBDRDY_WINDOW_LEN_C 0x426C +#define SBDRDY_WINDOW_LEN_C_M 0x7000000 +#define MANUAL_TD_CFO_EN_C 0x426C +#define MANUAL_TD_CFO_EN_C_M 0x8000000 +#define EARLY_TERMINATION_TH_0_C 0x4270 +#define EARLY_TERMINATION_TH_0_C_M 0xF +#define EARLY_TERMINATION_TH_1_C 0x4270 +#define EARLY_TERMINATION_TH_1_C_M 0xF0 +#define EARLY_TERMINATION_TH_2_C 0x4270 +#define EARLY_TERMINATION_TH_2_C_M 0xF00 +#define EARLY_TERMINATION_TH_3_C 0x4270 +#define EARLY_TERMINATION_TH_3_C_M 0xF000 +#define ED_C1_TH_C 0x4270 +#define ED_C1_TH_C_M 0xF0000 +#define ED_C0_TH_C 0x4270 +#define ED_C0_TH_C_M 0x700000 +#define LDPC_SCAL_FCTR_C 0x4270 +#define LDPC_SCAL_FCTR_C_M 0x1800000 +#define EARLY_TERMINATION_BACKWARD_STEP_C 0x4270 +#define EARLY_TERMINATION_BACKWARD_STEP_C_M 0x6000000 +#define EARLY_TERMINATION_FORWARD_STEP_C 0x4270 +#define EARLY_TERMINATION_FORWARD_STEP_C_M 0x18000000 +#define LLR_SYNDROME_CHK_EN_C 0x4270 +#define LLR_SYNDROME_CHK_EN_C_M 0x20000000 +#define EARLY_DROP_C0_EN_C 0x4270 +#define EARLY_DROP_C0_EN_C_M 0x40000000 +#define EARLY_DROP_C1_EN_C 0x4270 +#define EARLY_DROP_C1_EN_C_M 0x80000000 +#define EARLY_DROP_C2_EN_C 0x4274 +#define EARLY_DROP_C2_EN_C_M 0x1 +#define EARLY_TERMINATION_EN_C 0x4274 +#define EARLY_TERMINATION_EN_C_M 0x2 +#define TBCOMCT_RXTIME_C 0x4278 +#define TBCOMCT_RXTIME_C_M 0x7FFF +#define TBCOMCT_N_SYM_C 0x4278 +#define TBCOMCT_N_SYM_C_M 0x3FF8000 +#define TBUSRCT0_MCS_C 0x4278 +#define TBUSRCT0_MCS_C_M 0x3C000000 +#define TBCOMCT_DBW_IDX_C 0x4278 +#define TBCOMCT_DBW_IDX_C_M 0xC0000000 +#define TBCOMCT_N_USR_C 0x427C +#define TBCOMCT_N_USR_C_M 0xFF +#define TBUSRCT0_RU_ALLOC_C 0x427C +#define TBUSRCT0_RU_ALLOC_C_M 0xFF00 +#define TBUSRCT0_U_ID_C 0x427C +#define TBUSRCT0_U_ID_C_M 0xFF0000 +#define TBUSRCT1_RU_ALLOC_C 0x427C +#define TBUSRCT1_RU_ALLOC_C_M 0xFF000000 +#define TBUSRCT1_U_ID_C 0x4280 +#define TBUSRCT1_U_ID_C_M 0xFF +#define TBUSRCT2_RU_ALLOC_C 0x4280 +#define TBUSRCT2_RU_ALLOC_C_M 0xFF00 +#define TBUSRCT2_U_ID_C 0x4280 +#define TBUSRCT2_U_ID_C_M 0xFF0000 +#define TBUSRCT3_RU_ALLOC_C 0x4280 +#define TBUSRCT3_RU_ALLOC_C_M 0xFF000000 +#define TBUSRCT3_U_ID_C 0x4284 +#define TBUSRCT3_U_ID_C_M 0xFF +#define TBUSRCT1_MCS_C 0x4284 +#define TBUSRCT1_MCS_C_M 0xF00 +#define TBUSRCT2_MCS_C 0x4284 +#define TBUSRCT2_MCS_C_M 0xF000 +#define TBUSRCT3_MCS_C 0x4284 +#define TBUSRCT3_MCS_C_M 0xF0000 +#define TBCOMCT_N_LTF_C 0x4284 +#define TBCOMCT_N_LTF_C_M 0x700000 +#define TBCOMCT_PKT_EXT_IDX_C 0x4284 +#define TBCOMCT_PKT_EXT_IDX_C_M 0x3800000 +#define TBUSRCT0_N_STS_C 0x4284 +#define TBUSRCT0_N_STS_C_M 0x1C000000 +#define TBUSRCT0_N_STS_RU_TOT_C 0x4284 +#define TBUSRCT0_N_STS_RU_TOT_C_M 0xE0000000 +#define TBUSRCT0_STRT_STS_C 0x4288 +#define TBUSRCT0_STRT_STS_C_M 0x7 +#define TBUSRCT1_N_STS_C 0x4288 +#define TBUSRCT1_N_STS_C_M 0x38 +#define TBUSRCT1_N_STS_RU_TOT_C 0x4288 +#define TBUSRCT1_N_STS_RU_TOT_C_M 0x1C0 +#define TBUSRCT1_STRT_STS_C 0x4288 +#define TBUSRCT1_STRT_STS_C_M 0xE00 +#define TBUSRCT2_N_STS_C 0x4288 +#define TBUSRCT2_N_STS_C_M 0x7000 +#define TBUSRCT2_N_STS_RU_TOT_C 0x4288 +#define TBUSRCT2_N_STS_RU_TOT_C_M 0x38000 +#define TBUSRCT2_STRT_STS_C 0x4288 +#define TBUSRCT2_STRT_STS_C_M 0x1C0000 +#define TBUSRCT3_N_STS_C 0x4288 +#define TBUSRCT3_N_STS_C_M 0xE00000 +#define TBUSRCT3_N_STS_RU_TOT_C 0x4288 +#define TBUSRCT3_N_STS_RU_TOT_C_M 0x7000000 +#define TBUSRCT3_STRT_STS_C 0x4288 +#define TBUSRCT3_STRT_STS_C_M 0x38000000 +#define TBCOMCT_GI_TYPE_C 0x4288 +#define TBCOMCT_GI_TYPE_C_M 0xC0000000 +#define TBCOMCT_LTF_TYPE_C 0x428C +#define TBCOMCT_LTF_TYPE_C_M 0x3 +#define TBCOMCT_PRE_FEC_FCTR_C 0x428C +#define TBCOMCT_PRE_FEC_FCTR_C_M 0xC +#define PPDU_STANDBY_C 0x428C +#define PPDU_STANDBY_C_M 0x10 +#define TBCOMCT_DOPPLER_EN_C 0x428C +#define TBCOMCT_DOPPLER_EN_C_M 0x20 +#define TBCOMCT_LDPC_EXTR_C 0x428C +#define TBCOMCT_LDPC_EXTR_C_M 0x40 +#define TBCOMCT_MIDAMBLE_MODE_C 0x428C +#define TBCOMCT_MIDAMBLE_MODE_C_M 0x80 +#define TBCOMCT_MUMIMO_LTF_MODE_EN_C 0x428C +#define TBCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x100 +#define TBCOMCT_NDP_C 0x428C +#define TBCOMCT_NDP_C_M 0x200 +#define TBCOMCT_STBC_EN_C 0x428C +#define TBCOMCT_STBC_EN_C_M 0x400 +#define TBUSRCT0_DCM_EN_C 0x428C +#define TBUSRCT0_DCM_EN_C_M 0x800 +#define TBUSRCT0_FEC_TYPE_C 0x428C +#define TBUSRCT0_FEC_TYPE_C_M 0x1000 +#define TBUSRCT1_DCM_EN_C 0x428C +#define TBUSRCT1_DCM_EN_C_M 0x2000 +#define TBUSRCT1_FEC_TYPE_C 0x428C +#define TBUSRCT1_FEC_TYPE_C_M 0x4000 +#define TBUSRCT2_DCM_EN_C 0x428C +#define TBUSRCT2_DCM_EN_C_M 0x8000 +#define TBUSRCT2_FEC_TYPE_C 0x428C +#define TBUSRCT2_FEC_TYPE_C_M 0x10000 +#define TBUSRCT3_DCM_EN_C 0x428C +#define TBUSRCT3_DCM_EN_C_M 0x20000 +#define TBUSRCT3_FEC_TYPE_C 0x428C +#define TBUSRCT3_FEC_TYPE_C_M 0x40000 +#define COLLISION_USR_SNR_DET_TH_C 0x429C +#define COLLISION_USR_SNR_DET_TH_C_M 0x3FF +#define COLLISION_USR_PW_DET_TH_C 0x429C +#define COLLISION_USR_PW_DET_TH_C_M 0x7FC00 +#define EMPTY_USR_PW_DET_TH_C 0x429C +#define EMPTY_USR_PW_DET_TH_C_M 0xFF80000 +#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C 0x429C +#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C_M 0xF0000000 +#define LLR_NVAR_SCAL_C 0x42A0 +#define LLR_NVAR_SCAL_C_M 0x3F +#define HE_20M_STA_CH_ALLOC_C 0x42A0 +#define HE_20M_STA_CH_ALLOC_C_M 0x3C0 +#define BWD_S80_THD_C 0x42A0 +#define BWD_S80_THD_C_M 0x1C00 +#define LLR_NVAR_SEL_C 0x42A0 +#define LLR_NVAR_SEL_C_M 0x6000 +#define CHSMO_EN_C 0x42A0 +#define CHSMO_EN_C_M 0x8000 +#define CHSMO_IDX_MOD_EN_C 0x42A0 +#define CHSMO_IDX_MOD_EN_C_M 0x10000 +#define HE_20M_STA_EN_C 0x42A0 +#define HE_20M_STA_EN_C_M 0x20000 +#define HE_TB_STF_CFO_EST_EN_C 0x42A0 +#define HE_TB_STF_CFO_EST_EN_C_M 0x40000 +#define L2_CFO_TRACKING_EN_C 0x42A0 +#define L2_CFO_TRACKING_EN_C_M 0x80000 +#define LNA_BASED_TRK_UPD_EN_C 0x42A0 +#define LNA_BASED_TRK_UPD_EN_C_M 0x100000 +#define COLLISION_USR_STAT_DET_EN_C 0x42A0 +#define COLLISION_USR_STAT_DET_EN_C_M 0x200000 +#define EMPTY_USR_PW_DET_NON_TB_EN_C 0x42A0 +#define EMPTY_USR_PW_DET_NON_TB_EN_C_M 0x400000 +#define SIGVAL_RPT_EN_C 0x42A0 +#define SIGVAL_RPT_EN_C_M 0x800000 +#define STBC_CH_CONSIST_EN_C 0x42A0 +#define STBC_CH_CONSIST_EN_C_M 0x1000000 +#define TRK_UPD_EN_PLCP_FORCE_ON_C 0x42A0 +#define TRK_UPD_EN_PLCP_FORCE_ON_C_M 0x2000000 +#define RU_END_IDX_C 0x42A4 +#define RU_END_IDX_C_M 0x7F +#define RU_START_IDX_C 0x42A4 +#define RU_START_IDX_C_M 0x3F80 +#define RX_NR_C 0x42A4 +#define RX_NR_C_M 0x1C000 +#define HT_CB_C 0x42A4 +#define HT_CB_C_M 0x60000 +#define NDPA_FEEDBACK_TYPE_C 0x42A4 +#define NDPA_FEEDBACK_TYPE_C_M 0x180000 +#define RX_NG_C 0x42A4 +#define RX_NG_C_M 0x600000 +#define RX_NC_C 0x42A4 +#define RX_NC_C_M 0x800000 +#define VHT_HE_CB_C 0x42A4 +#define VHT_HE_CB_C_M 0x1000000 +#define CSI_PARA_EN_C 0x42A4 +#define CSI_PARA_EN_C_M 0x2000000 +#define SEG0_SET1_CSI_WGT_TONE_IDX_C 0x42B0 +#define SEG0_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF +#define SEG0_SET2_CSI_WGT_TONE_IDX_C 0x42B0 +#define SEG0_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800 +#define CFO_CSI_WGT_TH_C 0x42B0 +#define CFO_CSI_WGT_TH_C_M 0x1C00000 +#define CFO_CSI_WGT_VAL_C 0x42B0 +#define CFO_CSI_WGT_VAL_C_M 0xE000000 +#define CSI_MASK_TH_C 0x42B0 +#define CSI_MASK_TH_C_M 0x70000000 +#define CFO_CSI_WGT_EN_C 0x42B0 +#define CFO_CSI_WGT_EN_C_M 0x80000000 +#define SEG1_SET1_CSI_WGT_TONE_IDX_C 0x42B4 +#define SEG1_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF +#define SEG1_SET2_CSI_WGT_TONE_IDX_C 0x42B4 +#define SEG1_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800 +#define CSI_WGT_RSSI_TH_C 0x42B4 +#define CSI_WGT_RSSI_TH_C_M 0x1C00000 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C 0x42B4 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C_M 0xE000000 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C 0x42B4 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C_M 0x70000000 +#define CSI_WGT_4X_MORE_EN_C 0x42B4 +#define CSI_WGT_4X_MORE_EN_C_M 0x80000000 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C 0x42B8 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C_M 0x7 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C 0x42B8 +#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C_M 0x38 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C 0x42B8 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C 0x42B8 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C_M 0xE00 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C 0x42B8 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C_M 0x7000 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C 0x42B8 +#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C_M 0x38000 +#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C 0x42B8 +#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x1C0000 +#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C 0x42B8 +#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C_M 0xE00000 +#define SEG0_SET1_CSI_WGT_VAL_TONE0_C 0x42B8 +#define SEG0_SET1_CSI_WGT_VAL_TONE0_C_M 0x7000000 +#define SEG0_SET1_CSI_WGT_VAL_TONE1_C 0x42B8 +#define SEG0_SET1_CSI_WGT_VAL_TONE1_C_M 0x38000000 +#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C 0x42B8 +#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000 +#define SEG0_SET1_CSI_WGT_VAL_TONE2_C 0x42BC +#define SEG0_SET1_CSI_WGT_VAL_TONE2_C_M 0x7 +#define SEG0_SET1_CSI_WGT_VAL_TONE3_C 0x42BC +#define SEG0_SET1_CSI_WGT_VAL_TONE3_C_M 0x38 +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C 0x42BC +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C_M 0x1C0 +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C 0x42BC +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C_M 0xE00 +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C 0x42BC +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C_M 0x7000 +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C 0x42BC +#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C_M 0x38000 +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C 0x42BC +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0000 +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C 0x42BC +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C_M 0xE00000 +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C 0x42BC +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C_M 0x7000000 +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C 0x42BC +#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C_M 0x38000000 +#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C 0x42BC +#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C_M 0xC0000000 +#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C 0x42C0 +#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x7 +#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C 0x42C0 +#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C_M 0x38 +#define SEG0_SET2_CSI_WGT_VAL_TONE0_C 0x42C0 +#define SEG0_SET2_CSI_WGT_VAL_TONE0_C_M 0x1C0 +#define SEG0_SET2_CSI_WGT_VAL_TONE1_C 0x42C0 +#define SEG0_SET2_CSI_WGT_VAL_TONE1_C_M 0xE00 +#define SEG0_SET2_CSI_WGT_VAL_TONE2_C 0x42C0 +#define SEG0_SET2_CSI_WGT_VAL_TONE2_C_M 0x7000 +#define SEG0_SET2_CSI_WGT_VAL_TONE3_C 0x42C0 +#define SEG0_SET2_CSI_WGT_VAL_TONE3_C_M 0x38000 +#define SEG1_SET1_CSI_WGT_VAL_TONE0_C 0x42C0 +#define SEG1_SET1_CSI_WGT_VAL_TONE0_C_M 0x1C0000 +#define SEG1_SET1_CSI_WGT_VAL_TONE1_C 0x42C0 +#define SEG1_SET1_CSI_WGT_VAL_TONE1_C_M 0xE00000 +#define SEG1_SET1_CSI_WGT_VAL_TONE2_C 0x42C0 +#define SEG1_SET1_CSI_WGT_VAL_TONE2_C_M 0x7000000 +#define SEG1_SET1_CSI_WGT_VAL_TONE3_C 0x42C0 +#define SEG1_SET1_CSI_WGT_VAL_TONE3_C_M 0x38000000 +#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C0 +#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC0000000 +#define SEG1_SET2_CSI_WGT_VAL_TONE0_C 0x42C4 +#define SEG1_SET2_CSI_WGT_VAL_TONE0_C_M 0x7 +#define SEG1_SET2_CSI_WGT_VAL_TONE1_C 0x42C4 +#define SEG1_SET2_CSI_WGT_VAL_TONE1_C_M 0x38 +#define SEG1_SET2_CSI_WGT_VAL_TONE2_C 0x42C4 +#define SEG1_SET2_CSI_WGT_VAL_TONE2_C_M 0x1C0 +#define SEG1_SET2_CSI_WGT_VAL_TONE3_C 0x42C4 +#define SEG1_SET2_CSI_WGT_VAL_TONE3_C_M 0xE00 +#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C4 +#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x3000 +#define SEG0_SET1_CSI_WGT_LFT_TONES_C 0x42C4 +#define SEG0_SET1_CSI_WGT_LFT_TONES_C_M 0xC000 +#define SEG0_SET1_CSI_WGT_RHT_TONES_C 0x42C4 +#define SEG0_SET1_CSI_WGT_RHT_TONES_C_M 0x30000 +#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC0000 +#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x300000 +#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC00000 +#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x3000000 +#define SEG0_SET2_CSI_WGT_LFT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_LFT_TONES_C_M 0xC000000 +#define SEG0_SET2_CSI_WGT_RHT_TONES_C 0x42C4 +#define SEG0_SET2_CSI_WGT_RHT_TONES_C_M 0x30000000 +#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C 0x42C4 +#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000 +#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C 0x42C8 +#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C_M 0x3 +#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C8 +#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC +#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C8 +#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x30 +#define SEG1_SET1_CSI_WGT_LFT_TONES_C 0x42C8 +#define SEG1_SET1_CSI_WGT_LFT_TONES_C_M 0xC0 +#define SEG1_SET1_CSI_WGT_RHT_TONES_C 0x42C8 +#define SEG1_SET1_CSI_WGT_RHT_TONES_C_M 0x300 +#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC00 +#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x3000 +#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC000 +#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x30000 +#define SEG1_SET2_CSI_WGT_LFT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_LFT_TONES_C_M 0xC0000 +#define SEG1_SET2_CSI_WGT_RHT_TONES_C 0x42C8 +#define SEG1_SET2_CSI_WGT_RHT_TONES_C_M 0x300000 +#define CSI_WGT_RSSI_BYPASS_EN_C 0x42C8 +#define CSI_WGT_RSSI_BYPASS_EN_C_M 0x400000 +#define SEG0_SET1_CSI_WGT_EN_C 0x42C8 +#define SEG0_SET1_CSI_WGT_EN_C_M 0x800000 +#define SEG0_SET2_CSI_WGT_EN_C 0x42C8 +#define SEG0_SET2_CSI_WGT_EN_C_M 0x1000000 +#define SEG1_SET1_CSI_WGT_EN_C 0x42C8 +#define SEG1_SET1_CSI_WGT_EN_C_M 0x2000000 +#define SEG1_SET2_CSI_WGT_EN_C 0x42C8 +#define SEG1_SET2_CSI_WGT_EN_C_M 0x4000000 +#define PROCR_MAX_NSTS_SMO_HW_C 0x42D4 +#define PROCR_MAX_NSTS_SMO_HW_C_M 0x3 +#define PROCR_NOISE_RE_EST_HE_TB_EN_C 0x42D4 +#define PROCR_NOISE_RE_EST_HE_TB_EN_C_M 0x4 +#define PROCR_NOISE_RE_EST_HE_EN_C 0x42D4 +#define PROCR_NOISE_RE_EST_HE_EN_C_M 0x8 +#define PROCR_NOISE_RE_EST_HT_EN_C 0x42D4 +#define PROCR_NOISE_RE_EST_HT_EN_C_M 0x10 +#define PROCR_NOISE_RE_EST_VHT_EN_C 0x42D4 +#define PROCR_NOISE_RE_EST_VHT_EN_C_M 0x20 +#define HE_EXTRA_TONE_CHSMO_EN_C 0x42D8 +#define HE_EXTRA_TONE_CHSMO_EN_C_M 0x1 +#define RPT_TONE_EVM_IDX_C 0x42DC +#define RPT_TONE_EVM_IDX_C_M 0x7FF +#define SFCTR_AWGN_BCC_1SS_MCS0_C 0x42DC +#define SFCTR_AWGN_BCC_1SS_MCS0_C_M 0x1F800 +#define SFCTR_AWGN_BCC_1SS_MCS1_C 0x42DC +#define SFCTR_AWGN_BCC_1SS_MCS1_C_M 0x7E0000 +#define SFCTR_AWGN_BCC_1SS_MCS2_C 0x42DC +#define SFCTR_AWGN_BCC_1SS_MCS2_C_M 0x1F800000 +#define LLR_COEF_C 0x42DC +#define LLR_COEF_C_M 0xE0000000 +#define SFCTR_AWGN_BCC_1SS_MCS3_C 0x42E0 +#define SFCTR_AWGN_BCC_1SS_MCS3_C_M 0x3F +#define SFCTR_AWGN_BCC_1SS_MCS4_C 0x42E0 +#define SFCTR_AWGN_BCC_1SS_MCS4_C_M 0xFC0 +#define SFCTR_AWGN_BCC_1SS_MCS5_C 0x42E0 +#define SFCTR_AWGN_BCC_1SS_MCS5_C_M 0x3F000 +#define SFCTR_AWGN_BCC_1SS_MCS6_C 0x42E0 +#define SFCTR_AWGN_BCC_1SS_MCS6_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_1SS_MCS7_C 0x42E0 +#define SFCTR_AWGN_BCC_1SS_MCS7_C_M 0x3F000000 +#define UPD_SYM_EVM_C 0x42E0 +#define UPD_SYM_EVM_C_M 0xC0000000 +#define SFCTR_AWGN_BCC_1SS_MCS8_C 0x42E4 +#define SFCTR_AWGN_BCC_1SS_MCS8_C_M 0x3F +#define SFCTR_AWGN_BCC_1SS_MCS9_C 0x42E4 +#define SFCTR_AWGN_BCC_1SS_MCS9_C_M 0xFC0 +#define SFCTR_AWGN_BCC_2SS_MCS0_C 0x42E4 +#define SFCTR_AWGN_BCC_2SS_MCS0_C_M 0x3F000 +#define SFCTR_AWGN_BCC_2SS_MCS1_C 0x42E4 +#define SFCTR_AWGN_BCC_2SS_MCS1_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_2SS_MCS2_C 0x42E4 +#define SFCTR_AWGN_BCC_2SS_MCS2_C_M 0x3F000000 +#define DCM_BINARY_CSI_WGT_C 0x42E4 +#define DCM_BINARY_CSI_WGT_C_M 0x40000000 +#define DCM_COMBINE_EN_C 0x42E4 +#define DCM_COMBINE_EN_C_M 0x80000000 +#define SFCTR_AWGN_BCC_2SS_MCS3_C 0x42E8 +#define SFCTR_AWGN_BCC_2SS_MCS3_C_M 0x3F +#define SFCTR_AWGN_BCC_2SS_MCS4_C 0x42E8 +#define SFCTR_AWGN_BCC_2SS_MCS4_C_M 0xFC0 +#define SFCTR_AWGN_BCC_2SS_MCS5_C 0x42E8 +#define SFCTR_AWGN_BCC_2SS_MCS5_C_M 0x3F000 +#define SFCTR_AWGN_BCC_2SS_MCS6_C 0x42E8 +#define SFCTR_AWGN_BCC_2SS_MCS6_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_2SS_MCS7_C 0x42E8 +#define SFCTR_AWGN_BCC_2SS_MCS7_C_M 0x3F000000 +#define EVM_RPT_OFST_EN_C 0x42E8 +#define EVM_RPT_OFST_EN_C_M 0x40000000 +#define LEGACY_2R_ANOTHER_SFCTR_EN_C 0x42E8 +#define LEGACY_2R_ANOTHER_SFCTR_EN_C_M 0x80000000 +#define SFCTR_AWGN_BCC_2SS_MCS8_C 0x42EC +#define SFCTR_AWGN_BCC_2SS_MCS8_C_M 0x3F +#define SFCTR_AWGN_BCC_2SS_MCS9_C 0x42EC +#define SFCTR_AWGN_BCC_2SS_MCS9_C_M 0xFC0 +#define SFCTR_AWGN_BCC_3SS_MCS0_C 0x42EC +#define SFCTR_AWGN_BCC_3SS_MCS0_C_M 0x3F000 +#define SFCTR_AWGN_BCC_3SS_MCS1_C 0x42EC +#define SFCTR_AWGN_BCC_3SS_MCS1_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_3SS_MCS2_C 0x42EC +#define SFCTR_AWGN_BCC_3SS_MCS2_C_M 0x3F000000 +#define DIFF_NLM_FOR_CHANNEL_EN_C 0x42EC +#define DIFF_NLM_FOR_CHANNEL_EN_C_M 0x40000000 +#define SFCTR_AWGN_BCC_3SS_MCS3_C 0x42F0 +#define SFCTR_AWGN_BCC_3SS_MCS3_C_M 0x3F +#define SFCTR_AWGN_BCC_3SS_MCS4_C 0x42F0 +#define SFCTR_AWGN_BCC_3SS_MCS4_C_M 0xFC0 +#define SFCTR_AWGN_BCC_3SS_MCS5_C 0x42F0 +#define SFCTR_AWGN_BCC_3SS_MCS5_C_M 0x3F000 +#define SFCTR_AWGN_BCC_3SS_MCS6_C 0x42F0 +#define SFCTR_AWGN_BCC_3SS_MCS6_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_3SS_MCS7_C 0x42F0 +#define SFCTR_AWGN_BCC_3SS_MCS7_C_M 0x3F000000 +#define SFCTR_AWGN_BCC_3SS_MCS8_C 0x42F4 +#define SFCTR_AWGN_BCC_3SS_MCS8_C_M 0x3F +#define SFCTR_AWGN_BCC_3SS_MCS9_C 0x42F4 +#define SFCTR_AWGN_BCC_3SS_MCS9_C_M 0xFC0 +#define SFCTR_AWGN_BCC_4SS_MCS0_C 0x42F4 +#define SFCTR_AWGN_BCC_4SS_MCS0_C_M 0x3F000 +#define SFCTR_AWGN_BCC_4SS_MCS1_C 0x42F4 +#define SFCTR_AWGN_BCC_4SS_MCS1_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_4SS_MCS2_C 0x42F4 +#define SFCTR_AWGN_BCC_4SS_MCS2_C_M 0x3F000000 +#define SFCTR_AWGN_BCC_4SS_MCS3_C 0x42F8 +#define SFCTR_AWGN_BCC_4SS_MCS3_C_M 0x3F +#define SFCTR_AWGN_BCC_4SS_MCS4_C 0x42F8 +#define SFCTR_AWGN_BCC_4SS_MCS4_C_M 0xFC0 +#define SFCTR_AWGN_BCC_4SS_MCS5_C 0x42F8 +#define SFCTR_AWGN_BCC_4SS_MCS5_C_M 0x3F000 +#define SFCTR_AWGN_BCC_4SS_MCS6_C 0x42F8 +#define SFCTR_AWGN_BCC_4SS_MCS6_C_M 0xFC0000 +#define SFCTR_AWGN_BCC_4SS_MCS7_C 0x42F8 +#define SFCTR_AWGN_BCC_4SS_MCS7_C_M 0x3F000000 +#define SFCTR_AWGN_BCC_4SS_MCS8_C 0x42FC +#define SFCTR_AWGN_BCC_4SS_MCS8_C_M 0x3F +#define SFCTR_AWGN_BCC_4SS_MCS9_C 0x42FC +#define SFCTR_AWGN_BCC_4SS_MCS9_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_1SS_MCS0_C 0x42FC +#define SFCTR_AWGN_LDPC_1SS_MCS0_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_1SS_MCS1_C 0x42FC +#define SFCTR_AWGN_LDPC_1SS_MCS1_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_1SS_MCS10_C 0x42FC +#define SFCTR_AWGN_LDPC_1SS_MCS10_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_1SS_MCS11_C 0x4300 +#define SFCTR_AWGN_LDPC_1SS_MCS11_C_M 0x3F +#define SFCTR_AWGN_LDPC_1SS_MCS2_C 0x4300 +#define SFCTR_AWGN_LDPC_1SS_MCS2_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_1SS_MCS3_C 0x4300 +#define SFCTR_AWGN_LDPC_1SS_MCS3_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_1SS_MCS4_C 0x4300 +#define SFCTR_AWGN_LDPC_1SS_MCS4_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_1SS_MCS5_C 0x4300 +#define SFCTR_AWGN_LDPC_1SS_MCS5_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_1SS_MCS6_C 0x4304 +#define SFCTR_AWGN_LDPC_1SS_MCS6_C_M 0x3F +#define SFCTR_AWGN_LDPC_1SS_MCS7_C 0x4304 +#define SFCTR_AWGN_LDPC_1SS_MCS7_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_1SS_MCS8_C 0x4304 +#define SFCTR_AWGN_LDPC_1SS_MCS8_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_1SS_MCS9_C 0x4304 +#define SFCTR_AWGN_LDPC_1SS_MCS9_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_2SS_MCS0_C 0x4304 +#define SFCTR_AWGN_LDPC_2SS_MCS0_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_2SS_MCS1_C 0x4308 +#define SFCTR_AWGN_LDPC_2SS_MCS1_C_M 0x3F +#define SFCTR_AWGN_LDPC_2SS_MCS10_C 0x4308 +#define SFCTR_AWGN_LDPC_2SS_MCS10_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_2SS_MCS11_C 0x4308 +#define SFCTR_AWGN_LDPC_2SS_MCS11_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_2SS_MCS2_C 0x4308 +#define SFCTR_AWGN_LDPC_2SS_MCS2_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_2SS_MCS3_C 0x4308 +#define SFCTR_AWGN_LDPC_2SS_MCS3_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_2SS_MCS4_C 0x430C +#define SFCTR_AWGN_LDPC_2SS_MCS4_C_M 0x3F +#define SFCTR_AWGN_LDPC_2SS_MCS5_C 0x430C +#define SFCTR_AWGN_LDPC_2SS_MCS5_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_2SS_MCS6_C 0x430C +#define SFCTR_AWGN_LDPC_2SS_MCS6_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_2SS_MCS7_C 0x430C +#define SFCTR_AWGN_LDPC_2SS_MCS7_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_2SS_MCS8_C 0x430C +#define SFCTR_AWGN_LDPC_2SS_MCS8_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_2SS_MCS9_C 0x4310 +#define SFCTR_AWGN_LDPC_2SS_MCS9_C_M 0x3F +#define SFCTR_AWGN_LDPC_3SS_MCS0_C 0x4310 +#define SFCTR_AWGN_LDPC_3SS_MCS0_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_3SS_MCS1_C 0x4310 +#define SFCTR_AWGN_LDPC_3SS_MCS1_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_3SS_MCS10_C 0x4310 +#define SFCTR_AWGN_LDPC_3SS_MCS10_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_3SS_MCS11_C 0x4310 +#define SFCTR_AWGN_LDPC_3SS_MCS11_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_3SS_MCS2_C 0x4314 +#define SFCTR_AWGN_LDPC_3SS_MCS2_C_M 0x3F +#define SFCTR_AWGN_LDPC_3SS_MCS3_C 0x4314 +#define SFCTR_AWGN_LDPC_3SS_MCS3_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_3SS_MCS4_C 0x4314 +#define SFCTR_AWGN_LDPC_3SS_MCS4_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_3SS_MCS5_C 0x4314 +#define SFCTR_AWGN_LDPC_3SS_MCS5_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_3SS_MCS6_C 0x4314 +#define SFCTR_AWGN_LDPC_3SS_MCS6_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_3SS_MCS7_C 0x4318 +#define SFCTR_AWGN_LDPC_3SS_MCS7_C_M 0x3F +#define SFCTR_AWGN_LDPC_3SS_MCS8_C 0x4318 +#define SFCTR_AWGN_LDPC_3SS_MCS8_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_3SS_MCS9_C 0x4318 +#define SFCTR_AWGN_LDPC_3SS_MCS9_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_4SS_MCS0_C 0x4318 +#define SFCTR_AWGN_LDPC_4SS_MCS0_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_4SS_MCS1_C 0x4318 +#define SFCTR_AWGN_LDPC_4SS_MCS1_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_4SS_MCS10_C 0x431C +#define SFCTR_AWGN_LDPC_4SS_MCS10_C_M 0x3F +#define SFCTR_AWGN_LDPC_4SS_MCS11_C 0x431C +#define SFCTR_AWGN_LDPC_4SS_MCS11_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_4SS_MCS2_C 0x431C +#define SFCTR_AWGN_LDPC_4SS_MCS2_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_4SS_MCS3_C 0x431C +#define SFCTR_AWGN_LDPC_4SS_MCS3_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_4SS_MCS4_C 0x431C +#define SFCTR_AWGN_LDPC_4SS_MCS4_C_M 0x3F000000 +#define SFCTR_AWGN_LDPC_4SS_MCS5_C 0x4320 +#define SFCTR_AWGN_LDPC_4SS_MCS5_C_M 0x3F +#define SFCTR_AWGN_LDPC_4SS_MCS6_C 0x4320 +#define SFCTR_AWGN_LDPC_4SS_MCS6_C_M 0xFC0 +#define SFCTR_AWGN_LDPC_4SS_MCS7_C 0x4320 +#define SFCTR_AWGN_LDPC_4SS_MCS7_C_M 0x3F000 +#define SFCTR_AWGN_LDPC_4SS_MCS8_C 0x4320 +#define SFCTR_AWGN_LDPC_4SS_MCS8_C_M 0xFC0000 +#define SFCTR_AWGN_LDPC_4SS_MCS9_C 0x4320 +#define SFCTR_AWGN_LDPC_4SS_MCS9_C_M 0x3F000000 +#define SFCTR_AWGN_LAGCY_12M_C 0x4324 +#define SFCTR_AWGN_LAGCY_12M_C_M 0x3F +#define SFCTR_AWGN_LAGCY_18M_C 0x4324 +#define SFCTR_AWGN_LAGCY_18M_C_M 0xFC0 +#define SFCTR_AWGN_LAGCY_24M_C 0x4324 +#define SFCTR_AWGN_LAGCY_24M_C_M 0x3F000 +#define SFCTR_AWGN_LAGCY_36M_C 0x4324 +#define SFCTR_AWGN_LAGCY_36M_C_M 0xFC0000 +#define SFCTR_AWGN_LAGCY_48M_C 0x4324 +#define SFCTR_AWGN_LAGCY_48M_C_M 0x3F000000 +#define SFCTR_AWGN_LAGCY_54M_C 0x4328 +#define SFCTR_AWGN_LAGCY_54M_C_M 0x3F +#define SFCTR_AWGN_LAGCY_6M_C 0x4328 +#define SFCTR_AWGN_LAGCY_6M_C_M 0xFC0 +#define SFCTR_AWGN_LAGCY_9M_C 0x4328 +#define SFCTR_AWGN_LAGCY_9M_C_M 0x3F000 +#define SFCTR_CH_BCC_1SS_MCS0_C 0x4328 +#define SFCTR_CH_BCC_1SS_MCS0_C_M 0xFC0000 +#define SFCTR_CH_BCC_1SS_MCS1_C 0x4328 +#define SFCTR_CH_BCC_1SS_MCS1_C_M 0x3F000000 +#define SFCTR_CH_BCC_1SS_MCS2_C 0x432C +#define SFCTR_CH_BCC_1SS_MCS2_C_M 0x3F +#define SFCTR_CH_BCC_1SS_MCS3_C 0x432C +#define SFCTR_CH_BCC_1SS_MCS3_C_M 0xFC0 +#define SFCTR_CH_BCC_1SS_MCS4_C 0x432C +#define SFCTR_CH_BCC_1SS_MCS4_C_M 0x3F000 +#define SFCTR_CH_BCC_1SS_MCS5_C 0x432C +#define SFCTR_CH_BCC_1SS_MCS5_C_M 0xFC0000 +#define SFCTR_CH_BCC_1SS_MCS6_C 0x432C +#define SFCTR_CH_BCC_1SS_MCS6_C_M 0x3F000000 +#define SFCTR_CH_BCC_1SS_MCS7_C 0x4330 +#define SFCTR_CH_BCC_1SS_MCS7_C_M 0x3F +#define SFCTR_CH_BCC_1SS_MCS8_C 0x4330 +#define SFCTR_CH_BCC_1SS_MCS8_C_M 0xFC0 +#define SFCTR_CH_BCC_1SS_MCS9_C 0x4330 +#define SFCTR_CH_BCC_1SS_MCS9_C_M 0x3F000 +#define SFCTR_CH_BCC_2SS_MCS0_C 0x4330 +#define SFCTR_CH_BCC_2SS_MCS0_C_M 0xFC0000 +#define SFCTR_CH_BCC_2SS_MCS1_C 0x4330 +#define SFCTR_CH_BCC_2SS_MCS1_C_M 0x3F000000 +#define SFCTR_CH_BCC_2SS_MCS2_C 0x4334 +#define SFCTR_CH_BCC_2SS_MCS2_C_M 0x3F +#define SFCTR_CH_BCC_2SS_MCS3_C 0x4334 +#define SFCTR_CH_BCC_2SS_MCS3_C_M 0xFC0 +#define SFCTR_CH_BCC_2SS_MCS4_C 0x4334 +#define SFCTR_CH_BCC_2SS_MCS4_C_M 0x3F000 +#define SFCTR_CH_BCC_2SS_MCS5_C 0x4334 +#define SFCTR_CH_BCC_2SS_MCS5_C_M 0xFC0000 +#define SFCTR_CH_BCC_2SS_MCS6_C 0x4334 +#define SFCTR_CH_BCC_2SS_MCS6_C_M 0x3F000000 +#define SFCTR_CH_BCC_2SS_MCS7_C 0x4338 +#define SFCTR_CH_BCC_2SS_MCS7_C_M 0x3F +#define SFCTR_CH_BCC_2SS_MCS8_C 0x4338 +#define SFCTR_CH_BCC_2SS_MCS8_C_M 0xFC0 +#define SFCTR_CH_BCC_2SS_MCS9_C 0x4338 +#define SFCTR_CH_BCC_2SS_MCS9_C_M 0x3F000 +#define SFCTR_CH_BCC_3SS_MCS0_C 0x4338 +#define SFCTR_CH_BCC_3SS_MCS0_C_M 0xFC0000 +#define SFCTR_CH_BCC_3SS_MCS1_C 0x4338 +#define SFCTR_CH_BCC_3SS_MCS1_C_M 0x3F000000 +#define SFCTR_CH_BCC_3SS_MCS2_C 0x433C +#define SFCTR_CH_BCC_3SS_MCS2_C_M 0x3F +#define SFCTR_CH_BCC_3SS_MCS3_C 0x433C +#define SFCTR_CH_BCC_3SS_MCS3_C_M 0xFC0 +#define SFCTR_CH_BCC_3SS_MCS4_C 0x433C +#define SFCTR_CH_BCC_3SS_MCS4_C_M 0x3F000 +#define SFCTR_CH_BCC_3SS_MCS5_C 0x433C +#define SFCTR_CH_BCC_3SS_MCS5_C_M 0xFC0000 +#define SFCTR_CH_BCC_3SS_MCS6_C 0x433C +#define SFCTR_CH_BCC_3SS_MCS6_C_M 0x3F000000 +#define SFCTR_CH_BCC_3SS_MCS7_C 0x4340 +#define SFCTR_CH_BCC_3SS_MCS7_C_M 0x3F +#define SFCTR_CH_BCC_3SS_MCS8_C 0x4340 +#define SFCTR_CH_BCC_3SS_MCS8_C_M 0xFC0 +#define SFCTR_CH_BCC_3SS_MCS9_C 0x4340 +#define SFCTR_CH_BCC_3SS_MCS9_C_M 0x3F000 +#define SFCTR_CH_BCC_4SS_MCS0_C 0x4340 +#define SFCTR_CH_BCC_4SS_MCS0_C_M 0xFC0000 +#define SFCTR_CH_BCC_4SS_MCS1_C 0x4340 +#define SFCTR_CH_BCC_4SS_MCS1_C_M 0x3F000000 +#define SFCTR_CH_BCC_4SS_MCS2_C 0x4344 +#define SFCTR_CH_BCC_4SS_MCS2_C_M 0x3F +#define SFCTR_CH_BCC_4SS_MCS3_C 0x4344 +#define SFCTR_CH_BCC_4SS_MCS3_C_M 0xFC0 +#define SFCTR_CH_BCC_4SS_MCS4_C 0x4344 +#define SFCTR_CH_BCC_4SS_MCS4_C_M 0x3F000 +#define SFCTR_CH_BCC_4SS_MCS5_C 0x4344 +#define SFCTR_CH_BCC_4SS_MCS5_C_M 0xFC0000 +#define SFCTR_CH_BCC_4SS_MCS6_C 0x4344 +#define SFCTR_CH_BCC_4SS_MCS6_C_M 0x3F000000 +#define SFCTR_CH_BCC_4SS_MCS7_C 0x4348 +#define SFCTR_CH_BCC_4SS_MCS7_C_M 0x3F +#define SFCTR_CH_BCC_4SS_MCS8_C 0x4348 +#define SFCTR_CH_BCC_4SS_MCS8_C_M 0xFC0 +#define SFCTR_CH_BCC_4SS_MCS9_C 0x4348 +#define SFCTR_CH_BCC_4SS_MCS9_C_M 0x3F000 +#define SFCTR_CH_LDPC_1SS_MCS0_C 0x4348 +#define SFCTR_CH_LDPC_1SS_MCS0_C_M 0xFC0000 +#define SFCTR_CH_LDPC_1SS_MCS1_C 0x4348 +#define SFCTR_CH_LDPC_1SS_MCS1_C_M 0x3F000000 +#define SFCTR_CH_LDPC_1SS_MCS10_C 0x434C +#define SFCTR_CH_LDPC_1SS_MCS10_C_M 0x3F +#define SFCTR_CH_LDPC_1SS_MCS11_C 0x434C +#define SFCTR_CH_LDPC_1SS_MCS11_C_M 0xFC0 +#define SFCTR_CH_LDPC_1SS_MCS2_C 0x434C +#define SFCTR_CH_LDPC_1SS_MCS2_C_M 0x3F000 +#define SFCTR_CH_LDPC_1SS_MCS3_C 0x434C +#define SFCTR_CH_LDPC_1SS_MCS3_C_M 0xFC0000 +#define SFCTR_CH_LDPC_1SS_MCS4_C 0x434C +#define SFCTR_CH_LDPC_1SS_MCS4_C_M 0x3F000000 +#define SFCTR_CH_LDPC_1SS_MCS5_C 0x4350 +#define SFCTR_CH_LDPC_1SS_MCS5_C_M 0x3F +#define SFCTR_CH_LDPC_1SS_MCS6_C 0x4350 +#define SFCTR_CH_LDPC_1SS_MCS6_C_M 0xFC0 +#define SFCTR_CH_LDPC_1SS_MCS7_C 0x4350 +#define SFCTR_CH_LDPC_1SS_MCS7_C_M 0x3F000 +#define SFCTR_CH_LDPC_1SS_MCS8_C 0x4350 +#define SFCTR_CH_LDPC_1SS_MCS8_C_M 0xFC0000 +#define SFCTR_CH_LDPC_1SS_MCS9_C 0x4350 +#define SFCTR_CH_LDPC_1SS_MCS9_C_M 0x3F000000 +#define SFCTR_CH_LDPC_2SS_MCS0_C 0x4354 +#define SFCTR_CH_LDPC_2SS_MCS0_C_M 0x3F +#define SFCTR_CH_LDPC_2SS_MCS1_C 0x4354 +#define SFCTR_CH_LDPC_2SS_MCS1_C_M 0xFC0 +#define SFCTR_CH_LDPC_2SS_MCS10_C 0x4354 +#define SFCTR_CH_LDPC_2SS_MCS10_C_M 0x3F000 +#define SFCTR_CH_LDPC_2SS_MCS11_C 0x4354 +#define SFCTR_CH_LDPC_2SS_MCS11_C_M 0xFC0000 +#define SFCTR_CH_LDPC_2SS_MCS2_C 0x4354 +#define SFCTR_CH_LDPC_2SS_MCS2_C_M 0x3F000000 +#define SFCTR_CH_LDPC_2SS_MCS3_C 0x4358 +#define SFCTR_CH_LDPC_2SS_MCS3_C_M 0x3F +#define SFCTR_CH_LDPC_2SS_MCS4_C 0x4358 +#define SFCTR_CH_LDPC_2SS_MCS4_C_M 0xFC0 +#define SFCTR_CH_LDPC_2SS_MCS5_C 0x4358 +#define SFCTR_CH_LDPC_2SS_MCS5_C_M 0x3F000 +#define SFCTR_CH_LDPC_2SS_MCS6_C 0x4358 +#define SFCTR_CH_LDPC_2SS_MCS6_C_M 0xFC0000 +#define SFCTR_CH_LDPC_2SS_MCS7_C 0x4358 +#define SFCTR_CH_LDPC_2SS_MCS7_C_M 0x3F000000 +#define SFCTR_CH_LDPC_2SS_MCS8_C 0x435C +#define SFCTR_CH_LDPC_2SS_MCS8_C_M 0x3F +#define SFCTR_CH_LDPC_2SS_MCS9_C 0x435C +#define SFCTR_CH_LDPC_2SS_MCS9_C_M 0xFC0 +#define SFCTR_CH_LDPC_3SS_MCS0_C 0x435C +#define SFCTR_CH_LDPC_3SS_MCS0_C_M 0x3F000 +#define SFCTR_CH_LDPC_3SS_MCS1_C 0x435C +#define SFCTR_CH_LDPC_3SS_MCS1_C_M 0xFC0000 +#define SFCTR_CH_LDPC_3SS_MCS10_C 0x435C +#define SFCTR_CH_LDPC_3SS_MCS10_C_M 0x3F000000 +#define SFCTR_CH_LDPC_3SS_MCS11_C 0x4360 +#define SFCTR_CH_LDPC_3SS_MCS11_C_M 0x3F +#define SFCTR_CH_LDPC_3SS_MCS2_C 0x4360 +#define SFCTR_CH_LDPC_3SS_MCS2_C_M 0xFC0 +#define SFCTR_CH_LDPC_3SS_MCS3_C 0x4360 +#define SFCTR_CH_LDPC_3SS_MCS3_C_M 0x3F000 +#define SFCTR_CH_LDPC_3SS_MCS4_C 0x4360 +#define SFCTR_CH_LDPC_3SS_MCS4_C_M 0xFC0000 +#define SFCTR_CH_LDPC_3SS_MCS5_C 0x4360 +#define SFCTR_CH_LDPC_3SS_MCS5_C_M 0x3F000000 +#define SFCTR_CH_LDPC_3SS_MCS6_C 0x4364 +#define SFCTR_CH_LDPC_3SS_MCS6_C_M 0x3F +#define SFCTR_CH_LDPC_3SS_MCS7_C 0x4364 +#define SFCTR_CH_LDPC_3SS_MCS7_C_M 0xFC0 +#define SFCTR_CH_LDPC_3SS_MCS8_C 0x4364 +#define SFCTR_CH_LDPC_3SS_MCS8_C_M 0x3F000 +#define SFCTR_CH_LDPC_3SS_MCS9_C 0x4364 +#define SFCTR_CH_LDPC_3SS_MCS9_C_M 0xFC0000 +#define SFCTR_CH_LDPC_4SS_MCS0_C 0x4364 +#define SFCTR_CH_LDPC_4SS_MCS0_C_M 0x3F000000 +#define SFCTR_CH_LDPC_4SS_MCS1_C 0x4368 +#define SFCTR_CH_LDPC_4SS_MCS1_C_M 0x3F +#define SFCTR_CH_LDPC_4SS_MCS10_C 0x4368 +#define SFCTR_CH_LDPC_4SS_MCS10_C_M 0xFC0 +#define SFCTR_CH_LDPC_4SS_MCS11_C 0x4368 +#define SFCTR_CH_LDPC_4SS_MCS11_C_M 0x3F000 +#define SFCTR_CH_LDPC_4SS_MCS2_C 0x4368 +#define SFCTR_CH_LDPC_4SS_MCS2_C_M 0xFC0000 +#define SFCTR_CH_LDPC_4SS_MCS3_C 0x4368 +#define SFCTR_CH_LDPC_4SS_MCS3_C_M 0x3F000000 +#define SFCTR_CH_LDPC_4SS_MCS4_C 0x436C +#define SFCTR_CH_LDPC_4SS_MCS4_C_M 0x3F +#define SFCTR_CH_LDPC_4SS_MCS5_C 0x436C +#define SFCTR_CH_LDPC_4SS_MCS5_C_M 0xFC0 +#define SFCTR_CH_LDPC_4SS_MCS6_C 0x436C +#define SFCTR_CH_LDPC_4SS_MCS6_C_M 0x3F000 +#define SFCTR_CH_LDPC_4SS_MCS7_C 0x436C +#define SFCTR_CH_LDPC_4SS_MCS7_C_M 0xFC0000 +#define SFCTR_CH_LDPC_4SS_MCS8_C 0x436C +#define SFCTR_CH_LDPC_4SS_MCS8_C_M 0x3F000000 +#define SFCTR_CH_LDPC_4SS_MCS9_C 0x4370 +#define SFCTR_CH_LDPC_4SS_MCS9_C_M 0x3F +#define SFCTR_CH_LAGCY_12M_C 0x4370 +#define SFCTR_CH_LAGCY_12M_C_M 0xFC0 +#define SFCTR_CH_LAGCY_18M_C 0x4370 +#define SFCTR_CH_LAGCY_18M_C_M 0x3F000 +#define SFCTR_CH_LAGCY_24M_C 0x4370 +#define SFCTR_CH_LAGCY_24M_C_M 0xFC0000 +#define SFCTR_CH_LAGCY_36M_C 0x4370 +#define SFCTR_CH_LAGCY_36M_C_M 0x3F000000 +#define SFCTR_CH_LAGCY_48M_C 0x4374 +#define SFCTR_CH_LAGCY_48M_C_M 0x3F +#define SFCTR_CH_LAGCY_54M_C 0x4374 +#define SFCTR_CH_LAGCY_54M_C_M 0xFC0 +#define SFCTR_CH_LAGCY_6M_C 0x4374 +#define SFCTR_CH_LAGCY_6M_C_M 0x3F000 +#define SFCTR_CH_LAGCY_9M_C 0x4374 +#define SFCTR_CH_LAGCY_9M_C_M 0xFC0000 +#define FCTR_AWGN_LAGCY_2R_C 0x4374 +#define FCTR_AWGN_LAGCY_2R_C_M 0xF000000 +#define FCTR_CH_LAGCY_2R_C 0x4374 +#define FCTR_CH_LAGCY_2R_C_M 0xF0000000 +#define FCTR_BCC_STBC_CH_16QAM_C 0x4378 +#define FCTR_BCC_STBC_CH_16QAM_C_M 0xF +#define FCTR_BCC_STBC_CH_256QAM_C 0x4378 +#define FCTR_BCC_STBC_CH_256QAM_C_M 0xF0 +#define FCTR_BCC_STBC_CH_64QAM_C 0x4378 +#define FCTR_BCC_STBC_CH_64QAM_C_M 0xF00 +#define FCTR_BCC_STBC_CH_BPSK_C 0x4378 +#define FCTR_BCC_STBC_CH_BPSK_C_M 0xF000 +#define FCTR_BCC_STBC_CH_QPSK_C 0x4378 +#define FCTR_BCC_STBC_CH_QPSK_C_M 0xF0000 +#define FCTR_BCC_STBC_I_16QAM_C 0x4378 +#define FCTR_BCC_STBC_I_16QAM_C_M 0xF00000 +#define FCTR_BCC_STBC_I_256QAM_C 0x4378 +#define FCTR_BCC_STBC_I_256QAM_C_M 0xF000000 +#define FCTR_BCC_STBC_I_64QAM_C 0x4378 +#define FCTR_BCC_STBC_I_64QAM_C_M 0xF0000000 +#define FCTR_BCC_STBC_I_BPSK_C 0x437C +#define FCTR_BCC_STBC_I_BPSK_C_M 0xF +#define FCTR_BCC_STBC_I_QPSK_C 0x437C +#define FCTR_BCC_STBC_I_QPSK_C_M 0xF0 +#define FCTR_HE_BCC_1SS_CH_16QAM_C 0x437C +#define FCTR_HE_BCC_1SS_CH_16QAM_C_M 0xF00 +#define FCTR_HE_BCC_1SS_CH_256QAM_C 0x437C +#define FCTR_HE_BCC_1SS_CH_256QAM_C_M 0xF000 +#define FCTR_HE_BCC_1SS_CH_64QAM_C 0x437C +#define FCTR_HE_BCC_1SS_CH_64QAM_C_M 0xF0000 +#define FCTR_HE_BCC_1SS_CH_BPSK_C 0x437C +#define FCTR_HE_BCC_1SS_CH_BPSK_C_M 0xF00000 +#define FCTR_HE_BCC_1SS_CH_QPSK_C 0x437C +#define FCTR_HE_BCC_1SS_CH_QPSK_C_M 0xF000000 +#define FCTR_HE_BCC_1SS_I_16QAM_C 0x437C +#define FCTR_HE_BCC_1SS_I_16QAM_C_M 0xF0000000 +#define FCTR_HE_BCC_1SS_I_256QAM_C 0x4380 +#define FCTR_HE_BCC_1SS_I_256QAM_C_M 0xF +#define FCTR_HE_BCC_1SS_I_64QAM_C 0x4380 +#define FCTR_HE_BCC_1SS_I_64QAM_C_M 0xF0 +#define FCTR_HE_BCC_1SS_I_BPSK_C 0x4380 +#define FCTR_HE_BCC_1SS_I_BPSK_C_M 0xF00 +#define FCTR_HE_BCC_1SS_I_QPSK_C 0x4380 +#define FCTR_HE_BCC_1SS_I_QPSK_C_M 0xF000 +#define FCTR_HE_BCC_2SS_CH_16QAM_C 0x4380 +#define FCTR_HE_BCC_2SS_CH_16QAM_C_M 0xF0000 +#define FCTR_HE_BCC_2SS_CH_256QAM_C 0x4380 +#define FCTR_HE_BCC_2SS_CH_256QAM_C_M 0xF00000 +#define FCTR_HE_BCC_2SS_CH_64QAM_C 0x4380 +#define FCTR_HE_BCC_2SS_CH_64QAM_C_M 0xF000000 +#define FCTR_HE_BCC_2SS_CH_BPSK_C 0x4380 +#define FCTR_HE_BCC_2SS_CH_BPSK_C_M 0xF0000000 +#define FCTR_HE_BCC_2SS_CH_QPSK_C 0x4384 +#define FCTR_HE_BCC_2SS_CH_QPSK_C_M 0xF +#define FCTR_HE_BCC_2SS_I_16QAM_C 0x4384 +#define FCTR_HE_BCC_2SS_I_16QAM_C_M 0xF0 +#define FCTR_HE_BCC_2SS_I_256QAM_C 0x4384 +#define FCTR_HE_BCC_2SS_I_256QAM_C_M 0xF00 +#define FCTR_HE_BCC_2SS_I_64QAM_C 0x4384 +#define FCTR_HE_BCC_2SS_I_64QAM_C_M 0xF000 +#define FCTR_HE_BCC_2SS_I_BPSK_C 0x4384 +#define FCTR_HE_BCC_2SS_I_BPSK_C_M 0xF0000 +#define FCTR_HE_BCC_2SS_I_QPSK_C 0x4384 +#define FCTR_HE_BCC_2SS_I_QPSK_C_M 0xF00000 +#define FCTR_HE_BCC_STBC_CH_16QAM_C 0x4384 +#define FCTR_HE_BCC_STBC_CH_16QAM_C_M 0xF000000 +#define FCTR_HE_BCC_STBC_CH_256QAM_C 0x4384 +#define FCTR_HE_BCC_STBC_CH_256QAM_C_M 0xF0000000 +#define FCTR_HE_BCC_STBC_CH_64QAM_C 0x4388 +#define FCTR_HE_BCC_STBC_CH_64QAM_C_M 0xF +#define FCTR_HE_BCC_STBC_CH_BPSK_C 0x4388 +#define FCTR_HE_BCC_STBC_CH_BPSK_C_M 0xF0 +#define FCTR_HE_BCC_STBC_CH_QPSK_C 0x4388 +#define FCTR_HE_BCC_STBC_CH_QPSK_C_M 0xF00 +#define FCTR_HE_BCC_STBC_I_16QAM_C 0x4388 +#define FCTR_HE_BCC_STBC_I_16QAM_C_M 0xF000 +#define FCTR_HE_BCC_STBC_I_256QAM_C 0x4388 +#define FCTR_HE_BCC_STBC_I_256QAM_C_M 0xF0000 +#define FCTR_HE_BCC_STBC_I_64QAM_C 0x4388 +#define FCTR_HE_BCC_STBC_I_64QAM_C_M 0xF00000 +#define FCTR_HE_BCC_STBC_I_BPSK_C 0x4388 +#define FCTR_HE_BCC_STBC_I_BPSK_C_M 0xF000000 +#define FCTR_HE_BCC_STBC_I_QPSK_C 0x4388 +#define FCTR_HE_BCC_STBC_I_QPSK_C_M 0xF0000000 +#define FCTR_HE_LDPC_1SS_CH_C 0x438C +#define FCTR_HE_LDPC_1SS_CH_C_M 0xF +#define FCTR_HE_LDPC_1SS_I_C 0x438C +#define FCTR_HE_LDPC_1SS_I_C_M 0xF0 +#define FCTR_HE_LDPC_2SS_CH_C 0x438C +#define FCTR_HE_LDPC_2SS_CH_C_M 0xF00 +#define FCTR_HE_LDPC_2SS_I_C 0x438C +#define FCTR_HE_LDPC_2SS_I_C_M 0xF000 +#define FCTR_HE_LDPC_STBC_CH_C 0x438C +#define FCTR_HE_LDPC_STBC_CH_C_M 0xF0000 +#define FCTR_HE_LDPC_STBC_I_C 0x438C +#define FCTR_HE_LDPC_STBC_I_C_M 0xF00000 +#define FCTR_HE_MU_BCC_CH_C 0x438C +#define FCTR_HE_MU_BCC_CH_C_M 0xF000000 +#define FCTR_HE_MU_BCC_I_C 0x438C +#define FCTR_HE_MU_BCC_I_C_M 0xF0000000 +#define FCTR_HE_MU_LDPC_CH_C 0x4390 +#define FCTR_HE_MU_LDPC_CH_C_M 0xF +#define FCTR_HE_MU_LDPC_I_C 0x4390 +#define FCTR_HE_MU_LDPC_I_C_M 0xF0 +#define FCTR_HE_MU_NOMUIC_BCC_CH_C 0x4390 +#define FCTR_HE_MU_NOMUIC_BCC_CH_C_M 0xF00 +#define FCTR_HE_MU_NOMUIC_BCC_I_C 0x4390 +#define FCTR_HE_MU_NOMUIC_BCC_I_C_M 0xF000 +#define FCTR_HE_MU_NOMUIC_LDPC_CH_C 0x4390 +#define FCTR_HE_MU_NOMUIC_LDPC_CH_C_M 0xF0000 +#define FCTR_HE_MU_NOMUIC_LDPC_I_C 0x4390 +#define FCTR_HE_MU_NOMUIC_LDPC_I_C_M 0xF00000 +#define FCTR_LDPC_STBC_CH_C 0x4390 +#define FCTR_LDPC_STBC_CH_C_M 0xF000000 +#define FCTR_LDPC_STBC_I_C 0x4390 +#define FCTR_LDPC_STBC_I_C_M 0xF0000000 +#define LLR_COEF_H_DELAY_SPREAD_C 0x4394 +#define LLR_COEF_H_DELAY_SPREAD_C_M 0x7 +#define LLR_COEF_L_DELAY_SPREAD_C 0x4394 +#define LLR_COEF_L_DELAY_SPREAD_C_M 0x38 +#define LLR_COEF_TH_C 0x4394 +#define LLR_COEF_TH_C_M 0x1C0 +#define LLR_SCAL_MODE_C 0x4394 +#define LLR_SCAL_MODE_C_M 0xE00 +#define LDPC_R12_MAX_ITER_C 0x4398 +#define LDPC_R12_MAX_ITER_C_M 0xF +#define LDPC_R23_MAX_ITER_C 0x4398 +#define LDPC_R23_MAX_ITER_C_M 0xF0 +#define LDPC_R34_MAX_ITER_C 0x4398 +#define LDPC_R34_MAX_ITER_C_M 0xF00 +#define LDPC_R56_MAX_ITER_C 0x4398 +#define LDPC_R56_MAX_ITER_C_M 0xF000 +#define LDPC_STBC_MAX_ITER_C 0x4398 +#define LDPC_STBC_MAX_ITER_C_M 0xF0000 +#define SEL_DEFAULT_ITER_C 0x4398 +#define SEL_DEFAULT_ITER_C_M 0x100000 +#define PACKET_FMT_C 0x43A0 +#define PACKET_FMT_C_M 0x7 +#define PFD_EN_C 0x43A0 +#define PFD_EN_C_M 0x8 +#define PFD_HE_ER_BLOCK_C 0x43A0 +#define PFD_HE_ER_BLOCK_C_M 0x10 +#define PFD_HE_MU_BLOCK_C 0x43A0 +#define PFD_HE_MU_BLOCK_C_M 0x20 +#define PFD_HE_SU_BLOCK_C 0x43A0 +#define PFD_HE_SU_BLOCK_C_M 0x40 +#define PFD_HE_TB_BLOCK_C 0x43A0 +#define PFD_HE_TB_BLOCK_C_M 0x80 +#define PFD_HT_BLOCK_C 0x43A0 +#define PFD_HT_BLOCK_C_M 0x100 +#define PFD_LEG_BLOCK_C 0x43A0 +#define PFD_LEG_BLOCK_C_M 0x200 +#define PFD_VHT_BLOCK_C 0x43A0 +#define PFD_VHT_BLOCK_C_M 0x400 +#define MANUAL_SIMI_FLAG_EN_C 0x43A0 +#define MANUAL_SIMI_FLAG_EN_C_M 0x800 +#define SIMI_FLAG_C 0x43A0 +#define SIMI_FLAG_C_M 0x1000 +#define LDPC_SU_SHARE_ITER_EN_C 0x43A8 +#define LDPC_SU_SHARE_ITER_EN_C_M 0x1 +#define BOARDCAST_STA_ID_C 0x43B0 +#define BOARDCAST_STA_ID_C_M 0x7FF +#define TARGET_STA_ID_0_C 0x43B0 +#define TARGET_STA_ID_0_C_M 0x3FF800 +#define TARGET_BSS_COLOR_0_C 0x43B0 +#define TARGET_BSS_COLOR_0_C_M 0xFC00000 +#define BSS_COLOR_MAP_VLD_0_C 0x43B0 +#define BSS_COLOR_MAP_VLD_0_C_M 0x10000000 +#define BSS_COLOR_MAP_VLD_1_C 0x43B0 +#define BSS_COLOR_MAP_VLD_1_C_M 0x20000000 +#define BSS_COLOR_MAP_VLD_2_C 0x43B0 +#define BSS_COLOR_MAP_VLD_2_C_M 0x40000000 +#define BSS_COLOR_MAP_VLD_3_C 0x43B0 +#define BSS_COLOR_MAP_VLD_3_C_M 0x80000000 +#define TARGET_STA_ID_1_C 0x43B4 +#define TARGET_STA_ID_1_C_M 0x7FF +#define TARGET_STA_ID_2_C 0x43B4 +#define TARGET_STA_ID_2_C_M 0x3FF800 +#define TARGET_BSS_COLOR_1_C 0x43B4 +#define TARGET_BSS_COLOR_1_C_M 0xFC00000 +#define VHT_SIGB_NDP_CHK_EN_C 0x43B4 +#define VHT_SIGB_NDP_CHK_EN_C_M 0x10000000 +#define SNIFFER_MODE_EN_C 0x43B4 +#define SNIFFER_MODE_EN_C_M 0x20000000 +#define TARGET_STA_ID_3_C 0x43B8 +#define TARGET_STA_ID_3_C_M 0x7FF +#define TARGET_BSS_COLOR_2_C 0x43B8 +#define TARGET_BSS_COLOR_2_C_M 0x1F800 +#define TARGET_BSS_COLOR_3_C 0x43B8 +#define TARGET_BSS_COLOR_3_C_M 0x7E0000 +#define MIN_SIVAL_TH_C 0x43BC +#define MIN_SIVAL_TH_C_M 0xFF +#define COND_TH_C 0x43BC +#define COND_TH_C_M 0x3F00 +#define COND_NUM_COUNT_NORM_FCTR_C 0x43BC +#define COND_NUM_COUNT_NORM_FCTR_C_M 0x4000 +#define MIN_SIGVAL_COUNT_NORM_FCTR_C 0x43BC +#define MIN_SIGVAL_COUNT_NORM_FCTR_C_M 0x8000 +#define SIG_RPT_GRP_FCTR_C 0x43BC +#define SIG_RPT_GRP_FCTR_C_M 0x10000 +#define TRACKING_RSV_C 0x43C0 +#define TRACKING_RSV_C_M 0xFFFFFFFF +#define NOISE_VAR_TH_0_C 0x43C4 +#define NOISE_VAR_TH_0_C_M 0xFFFFFF +#define USER_EXIST_N1_C 0x43C4 +#define USER_EXIST_N1_C_M 0xFF000000 +#define NOISE_VAR_TH_1_C 0x43C8 +#define NOISE_VAR_TH_1_C_M 0xFFFFFF +#define USER_EXIST_N2_C 0x43C8 +#define USER_EXIST_N2_C_M 0xFF000000 +#define FORCE_RCFO_VAL_C 0x43CC +#define FORCE_RCFO_VAL_C_M 0xFFFF +#define LPBW_KI_E_C 0x43CC +#define LPBW_KI_E_C_M 0xFFFF0000 +#define LPBW_KP_E_C 0x43D0 +#define LPBW_KP_E_C_M 0xFFF +#define CH_TRACKING_NST_C 0x43D0 +#define CH_TRACKING_NST_C_M 0x3FF000 +#define EVM_RPT_SCIDX_C 0x43D0 +#define EVM_RPT_SCIDX_C_M 0xFFC00000 +#define LPBW_OUT_LMT_C 0x43D4 +#define LPBW_OUT_LMT_C_M 0x3FF +#define USER_EXIST_CSI_C 0x43D4 +#define USER_EXIST_CSI_C_M 0xFFC00 +#define USER_EXIST_N3_C 0x43D4 +#define USER_EXIST_N3_C_M 0xFF00000 +#define USER_EXIST_T1_C 0x43D4 +#define USER_EXIST_T1_C_M 0xF0000000 +#define USER_EXIST_N4_C 0x43D8 +#define USER_EXIST_N4_C_M 0xFF +#define USER_EXIST_N9_C 0x43D8 +#define USER_EXIST_N9_C_M 0xFF00 +#define USER_EXIST_NU_C 0x43D8 +#define USER_EXIST_NU_C_M 0xFF0000 +#define ALPHA_FOR_CFO_DATA_00_C 0x43D8 +#define ALPHA_FOR_CFO_DATA_00_C_M 0x3F000000 +#define EVM_RPT_NSC0_C 0x43D8 +#define EVM_RPT_NSC0_C_M 0xC0000000 +#define ALPHA_FOR_CFO_DATA_01_C 0x43DC +#define ALPHA_FOR_CFO_DATA_01_C_M 0x3F +#define ALPHA_FOR_CFO_DATA_02_C 0x43DC +#define ALPHA_FOR_CFO_DATA_02_C_M 0xFC0 +#define ALPHA_FOR_CFO_DATA_03_C 0x43DC +#define ALPHA_FOR_CFO_DATA_03_C_M 0x3F000 +#define ALPHA_FOR_CFO_DATA_10_C 0x43DC +#define ALPHA_FOR_CFO_DATA_10_C_M 0xFC0000 +#define ALPHA_FOR_CFO_DATA_11_C 0x43DC +#define ALPHA_FOR_CFO_DATA_11_C_M 0x3F000000 +#define EVM_RPT_NSC1_C 0x43DC +#define EVM_RPT_NSC1_C_M 0xC0000000 +#define ALPHA_FOR_CFO_DATA_12_C 0x43E0 +#define ALPHA_FOR_CFO_DATA_12_C_M 0x3F +#define ALPHA_FOR_CFO_DATA_13_C 0x43E0 +#define ALPHA_FOR_CFO_DATA_13_C_M 0xFC0 +#define ALPHA_FOR_CFO_DATA_20_C 0x43E0 +#define ALPHA_FOR_CFO_DATA_20_C_M 0x3F000 +#define ALPHA_FOR_CFO_DATA_21_C 0x43E0 +#define ALPHA_FOR_CFO_DATA_21_C_M 0xFC0000 +#define ALPHA_FOR_CFO_DATA_22_C 0x43E0 +#define ALPHA_FOR_CFO_DATA_22_C_M 0x3F000000 +#define EVM_RPT_ALPHA0_C 0x43E0 +#define EVM_RPT_ALPHA0_C_M 0xC0000000 +#define ALPHA_FOR_CFO_DATA_23_C 0x43E4 +#define ALPHA_FOR_CFO_DATA_23_C_M 0x3F +#define ALPHA_FOR_CFO_PILOT_00_C 0x43E4 +#define ALPHA_FOR_CFO_PILOT_00_C_M 0xFC0 +#define ALPHA_FOR_CFO_PILOT_01_C 0x43E4 +#define ALPHA_FOR_CFO_PILOT_01_C_M 0x3F000 +#define ALPHA_FOR_CFO_PILOT_02_C 0x43E4 +#define ALPHA_FOR_CFO_PILOT_02_C_M 0xFC0000 +#define ALPHA_FOR_CFO_PILOT_03_C 0x43E4 +#define ALPHA_FOR_CFO_PILOT_03_C_M 0x3F000000 +#define EVM_RPT_ALPHA1_C 0x43E4 +#define EVM_RPT_ALPHA1_C_M 0xC0000000 +#define ALPHA_FOR_CFO_PILOT_10_C 0x43E8 +#define ALPHA_FOR_CFO_PILOT_10_C_M 0x3F +#define ALPHA_FOR_CFO_PILOT_11_C 0x43E8 +#define ALPHA_FOR_CFO_PILOT_11_C_M 0xFC0 +#define ALPHA_FOR_CFO_PILOT_12_C 0x43E8 +#define ALPHA_FOR_CFO_PILOT_12_C_M 0x3F000 +#define ALPHA_FOR_CFO_PILOT_13_C 0x43E8 +#define ALPHA_FOR_CFO_PILOT_13_C_M 0xFC0000 +#define ALPHA_FOR_CFO_PILOT_20_C 0x43E8 +#define ALPHA_FOR_CFO_PILOT_20_C_M 0x3F000000 +#define N_HESYM_EXT_EN_C 0x43E8 +#define N_HESYM_EXT_EN_C_M 0x40000000 +#define CH_TRACKING_COEF_SEL_C 0x43E8 +#define CH_TRACKING_COEF_SEL_C_M 0x80000000 +#define ALPHA_FOR_CFO_PILOT_21_C 0x43EC +#define ALPHA_FOR_CFO_PILOT_21_C_M 0x3F +#define ALPHA_FOR_CFO_PILOT_22_C 0x43EC +#define ALPHA_FOR_CFO_PILOT_22_C_M 0xFC0 +#define ALPHA_FOR_CFO_PILOT_23_C 0x43EC +#define ALPHA_FOR_CFO_PILOT_23_C_M 0x3F000 +#define ALPHA_FOR_H_00_C 0x43EC +#define ALPHA_FOR_H_00_C_M 0xFC0000 +#define ALPHA_FOR_H_01_C 0x43EC +#define ALPHA_FOR_H_01_C_M 0x3F000000 +#define CH_TRACKING_EN_C 0x43EC +#define CH_TRACKING_EN_C_M 0x40000000 +#define CSI_WGT_BYPASS_CPE_EN_C 0x43EC +#define CSI_WGT_BYPASS_CPE_EN_C_M 0x80000000 +#define ALPHA_FOR_H_02_C 0x43F0 +#define ALPHA_FOR_H_02_C_M 0x3F +#define ALPHA_FOR_H_03_C 0x43F0 +#define ALPHA_FOR_H_03_C_M 0xFC0 +#define ALPHA_FOR_H_10_C 0x43F0 +#define ALPHA_FOR_H_10_C_M 0x3F000 +#define ALPHA_FOR_H_11_C 0x43F0 +#define ALPHA_FOR_H_11_C_M 0xFC0000 +#define ALPHA_FOR_H_12_C 0x43F0 +#define ALPHA_FOR_H_12_C_M 0x3F000000 +#define DATA_TRACKING_EN_C 0x43F0 +#define DATA_TRACKING_EN_C_M 0x40000000 +#define EVM_RPT_MODE_C 0x43F0 +#define EVM_RPT_MODE_C_M 0x80000000 +#define ALPHA_FOR_H_13_C 0x43F4 +#define ALPHA_FOR_H_13_C_M 0x3F +#define ALPHA_FOR_H_20_C 0x43F4 +#define ALPHA_FOR_H_20_C_M 0xFC0 +#define ALPHA_FOR_H_21_C 0x43F4 +#define ALPHA_FOR_H_21_C_M 0x3F000 +#define ALPHA_FOR_H_22_C 0x43F4 +#define ALPHA_FOR_H_22_C_M 0xFC0000 +#define ALPHA_FOR_H_23_C 0x43F4 +#define ALPHA_FOR_H_23_C_M 0x3F000000 +#define FORCE_RCFO_EN_C 0x43F4 +#define FORCE_RCFO_EN_C_M 0x40000000 +#define LGY80_TRACKING_EN_C 0x43F4 +#define LGY80_TRACKING_EN_C_M 0x80000000 +#define ALPHA_FOR_NOISE_VAR_0_C 0x43F8 +#define ALPHA_FOR_NOISE_VAR_0_C_M 0x3F +#define ALPHA_FOR_NOISE_VAR_1_C 0x43F8 +#define ALPHA_FOR_NOISE_VAR_1_C_M 0xFC0 +#define CH_TRACKING_A0_C 0x43F8 +#define CH_TRACKING_A0_C_M 0x3F000 +#define CH_TRACKING_A1_C 0x43F8 +#define CH_TRACKING_A1_C_M 0xFC0000 +#define CH_TRACKING_A1_LGY80_C 0x43F8 +#define CH_TRACKING_A1_LGY80_C_M 0x3F000000 +#define LOOP_DATA_EN_C 0x43F8 +#define LOOP_DATA_EN_C_M 0x40000000 +#define LOOP_FILTER_EN_C 0x43F8 +#define LOOP_FILTER_EN_C_M 0x80000000 +#define CH_TRACKING_A1_STBC_C 0x43FC +#define CH_TRACKING_A1_STBC_C_M 0x3F +#define CH_TRACKING_A2_C 0x43FC +#define CH_TRACKING_A2_C_M 0xFC0 +#define CH_TRACKING_A2_LGY80_C 0x43FC +#define CH_TRACKING_A2_LGY80_C_M 0x3F000 +#define CH_TRACKING_A2_STBC_C 0x43FC +#define CH_TRACKING_A2_STBC_C_M 0xFC0000 +#define USER_EXIST_R1_C 0x43FC +#define USER_EXIST_R1_C_M 0x3F000000 +#define NOISE_TRACKING_EN_C 0x43FC +#define NOISE_TRACKING_EN_C_M 0x40000000 +#define SYMBOL_COUNT_SEL_C 0x43FC +#define SYMBOL_COUNT_SEL_C_M 0x80000000 +#define USER_EXIST_R2_C 0x4400 +#define USER_EXIST_R2_C_M 0x3F +#define USER_EXIST_R3_C 0x4400 +#define USER_EXIST_R3_C_M 0xFC0 +#define USER_EXIST_R4_C 0x4400 +#define USER_EXIST_R4_C_M 0x3F000 +#define USER_EXIST_R9_C 0x4400 +#define USER_EXIST_R9_C_M 0xFC0000 +#define CH_TRACKING_SYMB0_C 0x4400 +#define CH_TRACKING_SYMB0_C_M 0x1F000000 +#define CSI_WGT_BYPASS_CPE_TH_C 0x4400 +#define CSI_WGT_BYPASS_CPE_TH_C_M 0xE0000000 +#define CH_TRACKING_SYMB1_C 0x4404 +#define CH_TRACKING_SYMB1_C_M 0x1F +#define LPBW_SEL_D0_C 0x4404 +#define LPBW_SEL_D0_C_M 0x3E0 +#define LPBW_SEL_D0_TB_C 0x4404 +#define LPBW_SEL_D0_TB_C_M 0x7C00 +#define LPBW_SEL_D1_C 0x4404 +#define LPBW_SEL_D1_C_M 0xF8000 +#define LPBW_SEL_D1_HESU_C 0x4404 +#define LPBW_SEL_D1_HESU_C_M 0x1F00000 +#define LPBW_SEL_D1_TB_C 0x4404 +#define LPBW_SEL_D1_TB_C_M 0x3E000000 +#define LPBW_SEL_D1_LGY_C 0x4408 +#define LPBW_SEL_D1_LGY_C_M 0x1F +#define LPBW_SEL_D1_STBC_C 0x4408 +#define LPBW_SEL_D1_STBC_C_M 0x3E0 +#define LPBW_SEL_D2_C 0x4408 +#define LPBW_SEL_D2_C_M 0x7C00 +#define LPBW_SEL_D2_HESU_C 0x4408 +#define LPBW_SEL_D2_HESU_C_M 0xF8000 +#define LPBW_SEL_D2_TB_C 0x4408 +#define LPBW_SEL_D2_TB_C_M 0x1F00000 +#define LPBW_SEL_D2_LGY_C 0x4408 +#define LPBW_SEL_D2_LGY_C_M 0x3E000000 +#define LPBW_SEL_D2_STBC_C 0x440C +#define LPBW_SEL_D2_STBC_C_M 0x1F +#define LPBW_SEL_P0_C 0x440C +#define LPBW_SEL_P0_C_M 0x3E0 +#define LPBW_SEL_P0_TB_C 0x440C +#define LPBW_SEL_P0_TB_C_M 0x7C00 +#define LPBW_SEL_P1_C 0x440C +#define LPBW_SEL_P1_C_M 0xF8000 +#define LPBW_SEL_P1_HESU_C 0x440C +#define LPBW_SEL_P1_HESU_C_M 0x1F00000 +#define LPBW_SEL_P1_TB_C 0x440C +#define LPBW_SEL_P1_TB_C_M 0x3E000000 +#define LPBW_SEL_P1_LGY_C 0x4410 +#define LPBW_SEL_P1_LGY_C_M 0x1F +#define LPBW_SEL_P1_STBC_C 0x4410 +#define LPBW_SEL_P1_STBC_C_M 0x3E0 +#define LPBW_SEL_P2_C 0x4410 +#define LPBW_SEL_P2_C_M 0x7C00 +#define LPBW_SEL_P2_HESU_C 0x4410 +#define LPBW_SEL_P2_HESU_C_M 0xF8000 +#define LPBW_SEL_P2_TB_C 0x4410 +#define LPBW_SEL_P2_TB_C_M 0x1F00000 +#define LPBW_SEL_P2_LGY_C 0x4410 +#define LPBW_SEL_P2_LGY_C_M 0x3E000000 +#define LPBW_SEL_P2_STBC_C 0x4414 +#define LPBW_SEL_P2_STBC_C_M 0x1F +#define LPBW_SW_SYMB0_C 0x4414 +#define LPBW_SW_SYMB0_C_M 0x3E0 +#define LPBW_SW_SYMB1_C 0x4414 +#define LPBW_SW_SYMB1_C_M 0x7C00 +#define USER_EXIST_T4_C 0x4414 +#define USER_EXIST_T4_C_M 0x78000 +#define EVM_RPT_RUIDX_C 0x4414 +#define EVM_RPT_RUIDX_C_M 0x380000 +#define T2F_R_DC_EST_FORCE_I_C 0x4420 +#define T2F_R_DC_EST_FORCE_I_C_M 0xFFF +#define T2F_R_DC_EST_FORCE_Q_C 0x4420 +#define T2F_R_DC_EST_FORCE_Q_C_M 0xFFF000 +#define T2F_R_GI2_COMB_THR_C 0x4420 +#define T2F_R_GI2_COMB_THR_C_M 0x7F000000 +#define T2F_R_BT_DYN_DC_EST_EN_C 0x4420 +#define T2F_R_BT_DYN_DC_EST_EN_C_M 0x80000000 +#define T2F_R_MANUAL_N_GI2_COMB_C 0x4424 +#define T2F_R_MANUAL_N_GI2_COMB_C_M 0x7F +#define T2F_R_MANUAL_N_GI_COMB_C 0x4424 +#define T2F_R_MANUAL_N_GI_COMB_C_M 0x1F80 +#define T2F_R_MANUAL_N_SGI_COMB_C 0x4424 +#define T2F_R_MANUAL_N_SGI_COMB_C_M 0x3E000 +#define T2F_R_EXTRA_CH_LEN_C 0x4424 +#define T2F_R_EXTRA_CH_LEN_C_M 0x3C0000 +#define T2F_R_MANUAL_N_CDD_OFST_C 0x4424 +#define T2F_R_MANUAL_N_CDD_OFST_C_M 0x3C00000 +#define T2F_R_SBDRDY_WINDOW_LEN_C 0x4424 +#define T2F_R_SBDRDY_WINDOW_LEN_C_M 0x1C000000 +#define T2F_R_DC_EST_VHT_L1_C 0x4424 +#define T2F_R_DC_EST_VHT_L1_C_M 0x20000000 +#define T2F_R_GI2_COMB_LVL_C 0x4424 +#define T2F_R_GI2_COMB_LVL_C_M 0x40000000 +#define T2F_R_LNA_BASED_DC_UPD_EN_C 0x4424 +#define T2F_R_LNA_BASED_DC_UPD_EN_C_M 0x80000000 +#define T2F_R_VHT_LTF_DCCL_MODE_C 0x4428 +#define T2F_R_VHT_LTF_DCCL_MODE_C_M 0x1 +#define T2F_R_DC_EST_FORCE_EN_C 0x4428 +#define T2F_R_DC_EST_FORCE_EN_C_M 0x2 +#define T2F_R_MANUAL_GI_COMB_EN_C 0x4428 +#define T2F_R_MANUAL_GI_COMB_EN_C_M 0x4 +#define T2F_R_MANUAL_CDD_OFST_EN_C 0x4428 +#define T2F_R_MANUAL_CDD_OFST_EN_C_M 0x8 +#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C_M 0x10 +#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C_M 0x20 +#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C_M 0x40 +#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C_M 0x80 +#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C_M 0x100 +#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C_M 0x200 +#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C_M 0x400 +#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C_M 0x800 +#define T2F_R_RXFIR_COMP_EN_C 0x4428 +#define T2F_R_RXFIR_COMP_EN_C_M 0x1000 +#define DUMMY_0_C 0x442C +#define DUMMY_0_C_M 0xFFFFFFFF +#define DUMMY_1_C 0x4430 +#define DUMMY_1_C_M 0xFFFFFFFF +#define DUMMY_2_C 0x4434 +#define DUMMY_2_C_M 0xFFFFFFFF +#define DUMMY_3_C 0x4438 +#define DUMMY_3_C_M 0xFFFFFFFF +#define HE_TB_CCA_END_C 0x443C +#define HE_TB_CCA_END_C_M 0x3FF +#define HE_TB_CCA_ON_C 0x443C +#define HE_TB_CCA_ON_C_M 0xFFC00 +#define HE_TB_PD_COUNT_C 0x443C +#define HE_TB_PD_COUNT_C_M 0x3FF00000 +#define MIMO_PS_OPT_C 0x443C +#define MIMO_PS_OPT_C_M 0xC0000000 +#define HE_TB_RX_ON_C 0x4440 +#define HE_TB_RX_ON_C_M 0x3FF +#define HE_TB_SBD_COUNT_C 0x4440 +#define HE_TB_SBD_COUNT_C_M 0xFFC00 +#define MAXOFST_C 0x4440 +#define MAXOFST_C_M 0x3FF00000 +#define R11RCCA_EN_C 0x4440 +#define R11RCCA_EN_C_M 0x40000000 +#define R55M_DET_EN_C 0x4440 +#define R55M_DET_EN_C_M 0x80000000 +#define MINOFST_C 0x4444 +#define MINOFST_C_M 0xFF +#define FGT_FCTR_C 0x4444 +#define FGT_FCTR_C_M 0x7F00 +#define OFDMA_STF_OFST_C 0x4444 +#define OFDMA_STF_OFST_C_M 0x1F8000 +#define RF2SYNC_DLY_C 0x4444 +#define RF2SYNC_DLY_C_M 0x7E00000 +#define DFEDLY_BW20_C 0x4444 +#define DFEDLY_BW20_C_M 0xF8000000 +#define DFEDLY_BW40_C 0x4448 +#define DFEDLY_BW40_C_M 0x1F +#define DFEDLY_BW80_C 0x4448 +#define DFEDLY_BW80_C_M 0x3E0 +#define OPPDLY_C 0x4448 +#define OPPDLY_C_M 0x7C00 +#define SYNCDLY_BW20_C 0x4448 +#define SYNCDLY_BW20_C_M 0xF8000 +#define SYNCDLY_BW40_C 0x4448 +#define SYNCDLY_BW40_C_M 0x1F00000 +#define SYNCDLY_BW80_C 0x4448 +#define SYNCDLY_BW80_C_M 0x3E000000 +#define PSD_TOP_EN_C 0x4448 +#define PSD_TOP_EN_C_M 0x40000000 +#define ACI_DET_EN_C 0x4448 +#define ACI_DET_EN_C_M 0x80000000 +#define NBIDLY_C 0x444C +#define NBIDLY_C_M 0xF +#define WAIT_SBD_TIME_C 0x444C +#define WAIT_SBD_TIME_C_M 0xF0 +#define WAIT_SEG0_PD_TIME_C 0x444C +#define WAIT_SEG0_PD_TIME_C_M 0xF00 +#define WAIT_SEG1_PD_TIME_C 0x444C +#define WAIT_SEG1_PD_TIME_C_M 0xF000 +#define CCX_SOURCE_SEL_C 0x444C +#define CCX_SOURCE_SEL_C_M 0x70000 +#define DATADLY_BW20_C 0x444C +#define DATADLY_BW20_C_M 0x380000 +#define DATADLY_BW40_C 0x444C +#define DATADLY_BW40_C_M 0x1C00000 +#define DATADLY_BW80_C 0x444C +#define DATADLY_BW80_C_M 0xE000000 +#define SNR_REQ_1SS_MCS0_C 0x444C +#define SNR_REQ_1SS_MCS0_C_M 0x70000000 +#define AGC_LPW_C 0x444C +#define AGC_LPW_C_M 0x80000000 +#define SNR_REQ_1SS_MCS1_C 0x4450 +#define SNR_REQ_1SS_MCS1_C_M 0x7 +#define SNR_REQ_1SS_MCS10_C 0x4450 +#define SNR_REQ_1SS_MCS10_C_M 0x38 +#define SNR_REQ_1SS_MCS11_C 0x4450 +#define SNR_REQ_1SS_MCS11_C_M 0x1C0 +#define SNR_REQ_1SS_MCS2_C 0x4450 +#define SNR_REQ_1SS_MCS2_C_M 0xE00 +#define SNR_REQ_1SS_MCS3_C 0x4450 +#define SNR_REQ_1SS_MCS3_C_M 0x7000 +#define SNR_REQ_1SS_MCS4_C 0x4450 +#define SNR_REQ_1SS_MCS4_C_M 0x38000 +#define SNR_REQ_1SS_MCS5_C 0x4450 +#define SNR_REQ_1SS_MCS5_C_M 0x1C0000 +#define SNR_REQ_1SS_MCS6_C 0x4450 +#define SNR_REQ_1SS_MCS6_C_M 0xE00000 +#define SNR_REQ_1SS_MCS7_C 0x4450 +#define SNR_REQ_1SS_MCS7_C_M 0x7000000 +#define SNR_REQ_1SS_MCS8_C 0x4450 +#define SNR_REQ_1SS_MCS8_C_M 0x38000000 +#define ASSIGN_SBD_OPT_C 0x4450 +#define ASSIGN_SBD_OPT_C_M 0x40000000 +#define DCCL4SYNC_EN_C 0x4450 +#define DCCL4SYNC_EN_C_M 0x80000000 +#define SNR_REQ_1SS_MCS9_C 0x4454 +#define SNR_REQ_1SS_MCS9_C_M 0x7 +#define DFIR_EN_C 0x4454 +#define DFIR_EN_C_M 0x8 +#define HE_TB_CFO_EN_C 0x4454 +#define HE_TB_CFO_EN_C_M 0x10 +#define HE_TB_SYNC_FREE_C 0x4454 +#define HE_TB_SYNC_FREE_C_M 0x20 +#define I_ONLY_C 0x4454 +#define I_ONLY_C_M 0x40 +#define I_ONLY_S_C 0x4454 +#define I_ONLY_S_C_M 0x80 +#define IF_SEG0_PRIM80_C 0x4454 +#define IF_SEG0_PRIM80_C_M 0x100 +#define MIMO_PS_EN_C 0x4454 +#define MIMO_PS_EN_C_M 0x200 +#define NBI_EN_C 0x4454 +#define NBI_EN_C_M 0x400 +#define OFDMA_COMB_EN_C 0x4454 +#define OFDMA_COMB_EN_C_M 0x800 +#define POP_PD_FIRST_EN_C 0x4454 +#define POP_PD_FIRST_EN_C_M 0x1000 +#define SBDSEL_C 0x4454 +#define SBDSEL_C_M 0x2000 +#define SBDSEL_OFDMA_C 0x4454 +#define SBDSEL_OFDMA_C_M 0x4000 +#define SBF_EN_C 0x4454 +#define SBF_EN_C_M 0x8000 +#define SIMI_THD_0_C 0x445C +#define SIMI_THD_0_C_M 0x3FF +#define SIMI_THD_1_C 0x445C +#define SIMI_THD_1_C_M 0xFFC00 +#define SIMI_THD_2_C 0x445C +#define SIMI_THD_2_C_M 0x3FF00000 +#define EXTRATONE_PW_WGT_C 0x445C +#define EXTRATONE_PW_WGT_C_M 0xC0000000 +#define SIMI_THD_3_C 0x4460 +#define SIMI_THD_3_C_M 0x3FF +#define COMBINE_GAIN_GAP_DB_C 0x4460 +#define COMBINE_GAIN_GAP_DB_C_M 0x7C00 +#define EXTRATONE_PW_CHK_SNR_THR_C 0x4460 +#define EXTRATONE_PW_CHK_SNR_THR_C_M 0x38000 +#define SNR_COMB_IDX_C 0x4460 +#define SNR_COMB_IDX_C_M 0xC0000 +#define EXTRATONE_PW_CHK_EN_C 0x4460 +#define EXTRATONE_PW_CHK_EN_C_M 0x100000 +#define MANUL_SNR_COMB_IDX_EN_C 0x4460 +#define MANUL_SNR_COMB_IDX_EN_C_M 0x200000 +#define POSITIVE_SIMI_DET_EN_C 0x4460 +#define POSITIVE_SIMI_DET_EN_C_M 0x400000 +#define REAL_OR_ABS_SIMI_DET_C 0x4460 +#define REAL_OR_ABS_SIMI_DET_C_M 0x800000 +#define PATHA_T2F_R_DCCL_DATA_BKP1_C 0x4464 +#define PATHA_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF +#define PATHA_T2F_R_DCCL_DATA_BKP2_C 0x4468 +#define PATHA_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF +#define PATHA_T2F_R_DC_EST_FILT_EN_C 0x446C +#define PATHA_T2F_R_DC_EST_FILT_EN_C_M 0x1 +#define PATHB_T2F_R_DCCL_DATA_BKP1_C 0x4470 +#define PATHB_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF +#define PATHB_T2F_R_DCCL_DATA_BKP2_C 0x4474 +#define PATHB_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF +#define PATHB_T2F_R_DC_EST_FILT_EN_C 0x4478 +#define PATHB_T2F_R_DC_EST_FILT_EN_C_M 0x1 +#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C 0x447C +#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C_M 0x3F +#define SNR_LOSS_RPT_TYPE_C 0x447C +#define SNR_LOSS_RPT_TYPE_C_M 0xC0 +#define NV_TYPE_C 0x447C +#define NV_TYPE_C_M 0x100 +#define PRECODING_SCHEME_C 0x447C +#define PRECODING_SCHEME_C_M 0x200 +#define TXBF_PL_2NSTS_TH0_STS0_C 0x4480 +#define TXBF_PL_2NSTS_TH0_STS0_C_M 0x7F +#define TXBF_PL_2NSTS_TH0_STS1_C 0x4480 +#define TXBF_PL_2NSTS_TH0_STS1_C_M 0x3F80 +#define TXBF_PL_2NSTS_TH1_STS0_C 0x4480 +#define TXBF_PL_2NSTS_TH1_STS0_C_M 0x1FC000 +#define TXBF_PL_2NSTS_TH1_STS1_C 0x4480 +#define TXBF_PL_2NSTS_TH1_STS1_C_M 0xFE00000 +#define TXBF_PL_TH_SCAL_C 0x4480 +#define TXBF_PL_TH_SCAL_C_M 0x10000000 +#define TXBF_PL_EN_C 0x4480 +#define TXBF_PL_EN_C_M 0x20000000 +#define TXBF_PL_2NSTS_TH2_STS0_C 0x4484 +#define TXBF_PL_2NSTS_TH2_STS0_C_M 0x7F +#define TXBF_PL_2NSTS_TH2_STS1_C 0x4484 +#define TXBF_PL_2NSTS_TH2_STS1_C_M 0x3F80 +#define TXBF_PL_2NSTS_TH3_STS0_C 0x4484 +#define TXBF_PL_2NSTS_TH3_STS0_C_M 0x1FC000 +#define TXBF_PL_2NSTS_TH3_STS1_C 0x4484 +#define TXBF_PL_2NSTS_TH3_STS1_C_M 0xFE00000 +#define STEER_MATRIX_INTERPOLATION_EN_C 0x4488 +#define STEER_MATRIX_INTERPOLATION_EN_C_M 0x4 +#define CFO_COMP_SEG0_312P5KHZ_0_C 0x448C +#define CFO_COMP_SEG0_312P5KHZ_0_C_M 0xFFF +#define CFO_COMP_SEG0_312P5KHZ_1_C 0x448C +#define CFO_COMP_SEG0_312P5KHZ_1_C_M 0xFFF000 +#define TX_TIMING_C 0x448C +#define TX_TIMING_C_M 0xFF000000 +#define CFO_COMP_SEG0_312P5KHZ_2_C 0x4490 +#define CFO_COMP_SEG0_312P5KHZ_2_C_M 0xFFF +#define CFO_COMP_SEG0_312P5KHZ_3_C 0x4490 +#define CFO_COMP_SEG0_312P5KHZ_3_C_M 0xFFF000 +#define CFO_WGTING_C 0x4490 +#define CFO_WGTING_C_M 0xF000000 +#define PRIM_CH_C 0x4490 +#define PRIM_CH_C_M 0x70000000 +#define DAC_CLK_IDX_C 0x4490 +#define DAC_CLK_IDX_C_M 0x80000000 +#define CFO_COMP_SEG1_312P5KHZ_0_C 0x4494 +#define CFO_COMP_SEG1_312P5KHZ_0_C_M 0xFFF +#define CFO_COMP_SEG1_312P5KHZ_1_C 0x4494 +#define CFO_COMP_SEG1_312P5KHZ_1_C_M 0xFFF000 +#define TX_BANDEDGE_CFG_C 0x4494 +#define TX_BANDEDGE_CFG_C_M 0x3000000 +#define SPATIAL_MAP_MODE_IDX_C 0x4494 +#define SPATIAL_MAP_MODE_IDX_C_M 0xC000000 +#define TXBF_BYPASS_EN_C 0x4494 +#define TXBF_BYPASS_EN_C_M 0x10000000 +#define CFO_COMP_SEG0_VLD_0_C 0x4494 +#define CFO_COMP_SEG0_VLD_0_C_M 0x20000000 +#define CFO_COMP_SEG0_VLD_1_C 0x4494 +#define CFO_COMP_SEG0_VLD_1_C_M 0x40000000 +#define CFO_COMP_SEG0_VLD_2_C 0x4494 +#define CFO_COMP_SEG0_VLD_2_C_M 0x80000000 +#define CFO_COMP_SEG1_312P5KHZ_2_C 0x4498 +#define CFO_COMP_SEG1_312P5KHZ_2_C_M 0xFFF +#define CFO_COMP_SEG1_312P5KHZ_3_C 0x4498 +#define CFO_COMP_SEG1_312P5KHZ_3_C_M 0xFFF000 +#define CFO_COMP_SEG0_VLD_3_C 0x4498 +#define CFO_COMP_SEG0_VLD_3_C_M 0x1000000 +#define CFO_COMP_SEG1_VLD_0_C 0x4498 +#define CFO_COMP_SEG1_VLD_0_C_M 0x2000000 +#define CFO_COMP_SEG1_VLD_1_C 0x4498 +#define CFO_COMP_SEG1_VLD_1_C_M 0x4000000 +#define CFO_COMP_SEG1_VLD_2_C 0x4498 +#define CFO_COMP_SEG1_VLD_2_C_M 0x8000000 +#define CFO_COMP_SEG1_VLD_3_C 0x4498 +#define CFO_COMP_SEG1_VLD_3_C_M 0x10000000 +#define IDFT_OVER_SAMPLING_EN_C 0x4498 +#define IDFT_OVER_SAMPLING_EN_C_M 0x20000000 +#define IF_BANDEDGE_C 0x4498 +#define IF_BANDEDGE_C_M 0x40000000 +#define L_STF_TD_MODE_EN_C 0x4498 +#define L_STF_TD_MODE_EN_C_M 0x80000000 +#define TX_DAGC_PW_TOR_DB_C 0x449C +#define TX_DAGC_PW_TOR_DB_C_M 0x7 +#define TX_DAGC_EN_C 0x449C +#define TX_DAGC_EN_C_M 0x8 +#define TX_DAGC_MODE_IDX_C 0x449C +#define TX_DAGC_MODE_IDX_C_M 0x10 +#define TX_SCALE_C 0x44A0 +#define TX_SCALE_C_M 0x7F +#define TX_CCK_BACKOFF_C 0x44A0 +#define TX_CCK_BACKOFF_C_M 0xF80 +#define TX_NORMAL_BACKOFF_C 0x44A0 +#define TX_NORMAL_BACKOFF_C_M 0x1F000 +#define TX_BACKOFF_OFST1_C 0x44A0 +#define TX_BACKOFF_OFST1_C_M 0xE0000 +#define TX_BACKOFF_OFST2_C 0x44A0 +#define TX_BACKOFF_OFST2_C_M 0x700000 +#define TX_BACKOFF_OFST3_C 0x44A0 +#define TX_BACKOFF_OFST3_C_M 0x3800000 +#define TX_BACKOFF_BITMAP0_C 0x44A0 +#define TX_BACKOFF_BITMAP0_C_M 0xC000000 +#define TX_BACKOFF_BITMAP1_C 0x44A0 +#define TX_BACKOFF_BITMAP1_C_M 0x30000000 +#define TX_BACKOFF_BITMAP2_C 0x44A0 +#define TX_BACKOFF_BITMAP2_C_M 0xC0000000 +#define TX_BACKOFF_BITMAP3_C 0x44A4 +#define TX_BACKOFF_BITMAP3_C_M 0x3 +#define TX_BACKOFF_BITMAP4_C 0x44A4 +#define TX_BACKOFF_BITMAP4_C_M 0xC +#define TX_BACKOFF_BITMAP5_C 0x44A4 +#define TX_BACKOFF_BITMAP5_C_M 0x30 +#define TX_BACKOFF_BITMAP6_C 0x44A4 +#define TX_BACKOFF_BITMAP6_C_M 0xC0 +#define TX_BACKOFF_BITMAP7_C 0x44A4 +#define TX_BACKOFF_BITMAP7_C_M 0x300 +#define OV_RPT_RST_C 0x44A4 +#define OV_RPT_RST_C_M 0x400 +#define OBW_TX_EN_C 0x44A8 +#define OBW_TX_EN_C_M 0x1 +#define TX_N_PACKET_C 0x44AC +#define TX_N_PACKET_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_0_C 0x44B0 +#define TXD_HE_SIGB_CH1_0_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_1_C 0x44B4 +#define TXD_HE_SIGB_CH1_1_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_10_C 0x44B8 +#define TXD_HE_SIGB_CH1_10_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_11_C 0x44BC +#define TXD_HE_SIGB_CH1_11_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_12_C 0x44C0 +#define TXD_HE_SIGB_CH1_12_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_13_C 0x44C4 +#define TXD_HE_SIGB_CH1_13_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_14_C 0x44C8 +#define TXD_HE_SIGB_CH1_14_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_15_C 0x44CC +#define TXD_HE_SIGB_CH1_15_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_2_C 0x44D0 +#define TXD_HE_SIGB_CH1_2_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_3_C 0x44D4 +#define TXD_HE_SIGB_CH1_3_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_4_C 0x44D8 +#define TXD_HE_SIGB_CH1_4_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_5_C 0x44DC +#define TXD_HE_SIGB_CH1_5_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_6_C 0x44E0 +#define TXD_HE_SIGB_CH1_6_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_7_C 0x44E4 +#define TXD_HE_SIGB_CH1_7_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_8_C 0x44E8 +#define TXD_HE_SIGB_CH1_8_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH1_9_C 0x44EC +#define TXD_HE_SIGB_CH1_9_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_0_C 0x44F0 +#define TXD_HE_SIGB_CH2_0_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_1_C 0x44F4 +#define TXD_HE_SIGB_CH2_1_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_10_C 0x44F8 +#define TXD_HE_SIGB_CH2_10_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_11_C 0x44FC +#define TXD_HE_SIGB_CH2_11_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_12_C 0x4500 +#define TXD_HE_SIGB_CH2_12_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_13_C 0x4504 +#define TXD_HE_SIGB_CH2_13_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_14_C 0x4508 +#define TXD_HE_SIGB_CH2_14_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_15_C 0x450C +#define TXD_HE_SIGB_CH2_15_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_2_C 0x4510 +#define TXD_HE_SIGB_CH2_2_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_3_C 0x4514 +#define TXD_HE_SIGB_CH2_3_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_4_C 0x4518 +#define TXD_HE_SIGB_CH2_4_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_5_C 0x451C +#define TXD_HE_SIGB_CH2_5_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_6_C 0x4520 +#define TXD_HE_SIGB_CH2_6_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_7_C 0x4524 +#define TXD_HE_SIGB_CH2_7_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_8_C 0x4528 +#define TXD_HE_SIGB_CH2_8_C_M 0xFFFFFFFF +#define TXD_HE_SIGB_CH2_9_C 0x452C +#define TXD_HE_SIGB_CH2_9_C_M 0xFFFFFFFF +#define USER0_DELMTER_C 0x4530 +#define USER0_DELMTER_C_M 0xFFFFFFFF +#define USER0_EOF_PADDING_LEN_C 0x4534 +#define USER0_EOF_PADDING_LEN_C_M 0xFFFFFFFF +#define USER0_INIT_SEED_C 0x4538 +#define USER0_INIT_SEED_C_M 0xFFFFFFFF +#define USER1_DELMTER_C 0x453C +#define USER1_DELMTER_C_M 0xFFFFFFFF +#define USER1_EOF_PADDING_LEN_C 0x4540 +#define USER1_EOF_PADDING_LEN_C_M 0xFFFFFFFF +#define USER1_INIT_SEED_C 0x4544 +#define USER1_INIT_SEED_C_M 0xFFFFFFFF +#define USER2_DELMTER_C 0x4548 +#define USER2_DELMTER_C_M 0xFFFFFFFF +#define USER2_EOF_PADDING_LEN_C 0x454C +#define USER2_EOF_PADDING_LEN_C_M 0xFFFFFFFF +#define USER2_INIT_SEED_C 0x4550 +#define USER2_INIT_SEED_C_M 0xFFFFFFFF +#define USER3_DELMTER_C 0x4554 +#define USER3_DELMTER_C_M 0xFFFFFFFF +#define USER3_EOF_PADDING_LEN_C 0x4558 +#define USER3_EOF_PADDING_LEN_C_M 0xFFFFFFFF +#define USER3_INIT_SEED_C 0x455C +#define USER3_INIT_SEED_C_M 0xFFFFFFFF +#define TXD_VHT_SIGB0_C 0x4560 +#define TXD_VHT_SIGB0_C_M 0x1FFFFFFF +#define MAC_TDRDY_EXT_CNT_I_C 0x4560 +#define MAC_TDRDY_EXT_CNT_I_C_M 0xE0000000 +#define TXD_VHT_SIGB1_C 0x4564 +#define TXD_VHT_SIGB1_C_M 0x1FFFFFFF +#define MAC_TX_INFO_DLY_CNT_I_C 0x4564 +#define MAC_TX_INFO_DLY_CNT_I_C_M 0xE0000000 +#define TXD_VHT_SIGB2_C 0x4568 +#define TXD_VHT_SIGB2_C_M 0x1FFFFFFF +#define TXCOMCT_HE_SIGB_MCS_C 0x4568 +#define TXCOMCT_HE_SIGB_MCS_C_M 0xE0000000 +#define TXD_VHT_SIGB3_C 0x456C +#define TXD_VHT_SIGB3_C_M 0x1FFFFFFF +#define TXCOMCT_N_LTF_C 0x456C +#define TXCOMCT_N_LTF_C_M 0xE0000000 +#define TXD_SIGA1_C 0x4570 +#define TXD_SIGA1_C_M 0x3FFFFFF +#define TAR_TXINFO_TXTP_C 0x4570 +#define TAR_TXINFO_TXTP_C_M 0xFC000000 +#define TXD_SIGA2_C 0x4574 +#define TXD_SIGA2_C_M 0x3FFFFFF +#define TXINFO_RATE_BIAS_C 0x4574 +#define TXINFO_RATE_BIAS_C_M 0xFC000000 +#define TXD_LSIG_C 0x4578 +#define TXD_LSIG_C_M 0xFFFFFF +#define TXINFO_CCA_PW_TH_C 0x4578 +#define TXINFO_CCA_PW_TH_C_M 0xFF000000 +#define TX_PADDING_ZEROS_50NS_C 0x457C +#define TX_PADDING_ZEROS_50NS_C_M 0x1FFFFF +#define TXTIMCT_N_SYM_C 0x457C +#define TXTIMCT_N_SYM_C_M 0xFFE00000 +#define USER0_SERVICE_C 0x4580 +#define USER0_SERVICE_C_M 0xFFFF +#define USER1_SERVICE_C 0x4580 +#define USER1_SERVICE_C_M 0xFFFF0000 +#define USER2_SERVICE_C 0x4584 +#define USER2_SERVICE_C_M 0xFFFF +#define USER3_SERVICE_C 0x4584 +#define USER3_SERVICE_C_M 0xFFFF0000 +#define USER0_MDPU_LEN_BYTE_C 0x4588 +#define USER0_MDPU_LEN_BYTE_C_M 0x3FFF +#define USER1_MDPU_LEN_BYTE_C 0x4588 +#define USER1_MDPU_LEN_BYTE_C_M 0xFFFC000 +#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C 0x4588 +#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C_M 0xF0000000 +#define USER2_MDPU_LEN_BYTE_C 0x458C +#define USER2_MDPU_LEN_BYTE_C_M 0x3FFF +#define USER3_MDPU_LEN_BYTE_C 0x458C +#define USER3_MDPU_LEN_BYTE_C_M 0xFFFC000 +#define TXINFO_PATH_EN_C 0x458C +#define TXINFO_PATH_EN_C_M 0xF0000000 +#define TXUSRCT0_CSI_BUF_ID_C 0x4590 +#define TXUSRCT0_CSI_BUF_ID_C_M 0x7FF +#define TXUSRCT1_CSI_BUF_ID_C 0x4590 +#define TXUSRCT1_CSI_BUF_ID_C_M 0x3FF800 +#define TXINFO_RF_GAIN_IDX_C 0x4590 +#define TXINFO_RF_GAIN_IDX_C_M 0xFFC00000 +#define TXUSRCT2_CSI_BUF_ID_C 0x4594 +#define TXUSRCT2_CSI_BUF_ID_C_M 0x7FF +#define TXUSRCT3_CSI_BUF_ID_C 0x4594 +#define TXUSRCT3_CSI_BUF_ID_C_M 0x3FF800 +#define TXINFO_TX_PW_DBM_C 0x4594 +#define TXINFO_TX_PW_DBM_C_M 0x7FC00000 +#define AMPDU_4BYTES_ALIGN_EN_C 0x4594 +#define AMPDU_4BYTES_ALIGN_EN_C_M 0x80000000 +#define USER0_N_MPDU_C 0x4598 +#define USER0_N_MPDU_C_M 0x1FF +#define USER1_N_MPDU_C 0x4598 +#define USER1_N_MPDU_C_M 0x3FE00 +#define USER2_N_MPDU_C 0x4598 +#define USER2_N_MPDU_C_M 0x7FC0000 +#define TXUSRCT0_PW_BOOST_FCTR_DB_C 0x4598 +#define TXUSRCT0_PW_BOOST_FCTR_DB_C_M 0xF8000000 +#define USER3_N_MPDU_C 0x459C +#define USER3_N_MPDU_C_M 0x1FF +#define TXINFO_CH20_WITH_DATA_C 0x459C +#define TXINFO_CH20_WITH_DATA_C_M 0x1FE00 +#define TXINFO_N_USR_C 0x459C +#define TXINFO_N_USR_C_M 0x1FE0000 +#define TXINFO_TXCMD_TXTP_C 0x459C +#define TXINFO_TXCMD_TXTP_C_M 0x7E000000 +#define BMODE_LOCKED_CLK_EN_C 0x459C +#define BMODE_LOCKED_CLK_EN_C_M 0x80000000 +#define TXUSRCT0_RU_ALLOC_C 0x45A0 +#define TXUSRCT0_RU_ALLOC_C_M 0xFF +#define TXUSRCT0_U_ID_C 0x45A0 +#define TXUSRCT0_U_ID_C_M 0xFF00 +#define TXUSRCT1_RU_ALLOC_C 0x45A0 +#define TXUSRCT1_RU_ALLOC_C_M 0xFF0000 +#define TXUSRCT1_U_ID_C 0x45A0 +#define TXUSRCT1_U_ID_C_M 0xFF000000 +#define TXUSRCT2_RU_ALLOC_C 0x45A4 +#define TXUSRCT2_RU_ALLOC_C_M 0xFF +#define TXUSRCT2_U_ID_C 0x45A4 +#define TXUSRCT2_U_ID_C_M 0xFF00 +#define TXUSRCT3_RU_ALLOC_C 0x45A4 +#define TXUSRCT3_RU_ALLOC_C_M 0xFF0000 +#define TXUSRCT3_U_ID_C 0x45A4 +#define TXUSRCT3_U_ID_C_M 0xFF000000 +#define TXTIMCT_N_SYM_HESIGB_C 0x45A8 +#define TXTIMCT_N_SYM_HESIGB_C_M 0x3F +#define TXUSRCT0_MCS_C 0x45A8 +#define TXUSRCT0_MCS_C_M 0xFC0 +#define TXUSRCT1_MCS_C 0x45A8 +#define TXUSRCT1_MCS_C_M 0x3F000 +#define TXUSRCT2_MCS_C 0x45A8 +#define TXUSRCT2_MCS_C_M 0xFC0000 +#define TXUSRCT3_MCS_C 0x45A8 +#define TXUSRCT3_MCS_C_M 0x3F000000 +#define BMODE_RATE_IDX_C 0x45A8 +#define BMODE_RATE_IDX_C_M 0xC0000000 +#define TXUSRCT1_PW_BOOST_FCTR_DB_C 0x45AC +#define TXUSRCT1_PW_BOOST_FCTR_DB_C_M 0x1F +#define TXUSRCT2_PW_BOOST_FCTR_DB_C 0x45AC +#define TXUSRCT2_PW_BOOST_FCTR_DB_C_M 0x3E0 +#define TXUSRCT3_PW_BOOST_FCTR_DB_C 0x45AC +#define TXUSRCT3_PW_BOOST_FCTR_DB_C_M 0x7C00 +#define TXINFO_PPDU_TYPE_C 0x45AC +#define TXINFO_PPDU_TYPE_C_M 0x78000 +#define TXINFO_TX_SWING_C 0x45AC +#define TXINFO_TX_SWING_C_M 0x780000 +#define TXINFO_TXSC_C 0x45AC +#define TXINFO_TXSC_C_M 0x7800000 +#define TXINFO_CFO_COMP_C 0x45AC +#define TXINFO_CFO_COMP_C_M 0x38000000 +#define MAC_TX_U_ID_PHASE_OPT_T_C 0x45AC +#define MAC_TX_U_ID_PHASE_OPT_T_C_M 0xC0000000 +#define TXTIMCT_PKT_EXT_IDX_C 0x45B0 +#define TXTIMCT_PKT_EXT_IDX_C_M 0x7 +#define TXUSRCT0_N_STS_C 0x45B0 +#define TXUSRCT0_N_STS_C_M 0x38 +#define TXUSRCT0_N_STS_RU_TOT_C 0x45B0 +#define TXUSRCT0_N_STS_RU_TOT_C_M 0x1C0 +#define TXUSRCT0_STRT_STS_C 0x45B0 +#define TXUSRCT0_STRT_STS_C_M 0xE00 +#define TXUSRCT1_N_STS_C 0x45B0 +#define TXUSRCT1_N_STS_C_M 0x7000 +#define TXUSRCT1_N_STS_RU_TOT_C 0x45B0 +#define TXUSRCT1_N_STS_RU_TOT_C_M 0x38000 +#define TXUSRCT1_STRT_STS_C 0x45B0 +#define TXUSRCT1_STRT_STS_C_M 0x1C0000 +#define TXUSRCT2_N_STS_C 0x45B0 +#define TXUSRCT2_N_STS_C_M 0xE00000 +#define TXUSRCT2_N_STS_RU_TOT_C 0x45B0 +#define TXUSRCT2_N_STS_RU_TOT_C_M 0x7000000 +#define TXUSRCT2_STRT_STS_C 0x45B0 +#define TXUSRCT2_STRT_STS_C_M 0x38000000 +#define MAC_TXD_PHASE_OPT_I_C 0x45B0 +#define MAC_TXD_PHASE_OPT_I_C_M 0xC0000000 +#define TXUSRCT3_N_STS_C 0x45B4 +#define TXUSRCT3_N_STS_C_M 0x7 +#define TXUSRCT3_N_STS_RU_TOT_C 0x45B4 +#define TXUSRCT3_N_STS_RU_TOT_C_M 0x38 +#define TXUSRCT3_STRT_STS_C 0x45B4 +#define TXUSRCT3_STRT_STS_C_M 0x1C0 +#define SOURCE_GEN_MODE_IDX_C 0x45B4 +#define SOURCE_GEN_MODE_IDX_C_M 0x600 +#define TXCOMCT_GI_TYPE_C 0x45B4 +#define TXCOMCT_GI_TYPE_C_M 0x1800 +#define TXCOMCT_LTF_TYPE_C 0x45B4 +#define TXCOMCT_LTF_TYPE_C_M 0x6000 +#define TXINFO_DBW_IDX_C 0x45B4 +#define TXINFO_DBW_IDX_C_M 0x18000 +#define TXINFO_PATH_MAP_A_C 0x45B4 +#define TXINFO_PATH_MAP_A_C_M 0x60000 +#define TXINFO_PATH_MAP_B_C 0x45B4 +#define TXINFO_PATH_MAP_B_C_M 0x180000 +#define TXINFO_PATH_MAP_C_C 0x45B4 +#define TXINFO_PATH_MAP_C_C_M 0x600000 +#define TXINFO_PATH_MAP_D_C 0x45B4 +#define TXINFO_PATH_MAP_D_C_M 0x1800000 +#define TXTIMCT_PRE_FEC_FCTR_C 0x45B4 +#define TXTIMCT_PRE_FEC_FCTR_C_M 0x6000000 +#define BMODE_LONG_PREAMBLE_EN_C 0x45B4 +#define BMODE_LONG_PREAMBLE_EN_C_M 0x8000000 +#define MAC_TX_PMAC_EN_I_C 0x45B4 +#define MAC_TX_PMAC_EN_I_C_M 0x10000000 +#define TAR_TXINFO_TXTP_EN_C 0x45B4 +#define TAR_TXINFO_TXTP_EN_C_M 0x20000000 +#define TX_N_PACKET_EN_C 0x45B4 +#define TX_N_PACKET_EN_C_M 0x40000000 +#define TX_CONTINUOUS_C 0x45B4 +#define TX_CONTINUOUS_C_M 0x80000000 +#define TX_EN_C 0x45B8 +#define TX_EN_C_M 0x1 +#define TXCOMCT_BEAM_CHANGE_EN_C 0x45B8 +#define TXCOMCT_BEAM_CHANGE_EN_C_M 0x2 +#define TXCOMCT_DOPPLER_EN_C 0x45B8 +#define TXCOMCT_DOPPLER_EN_C_M 0x4 +#define TXCOMCT_FB_MUMIMO_EN_C 0x45B8 +#define TXCOMCT_FB_MUMIMO_EN_C_M 0x8 +#define TXCOMCT_FEEDBACK_STATUS_C 0x45B8 +#define TXCOMCT_FEEDBACK_STATUS_C_M 0x10 +#define TXCOMCT_HE_SIGB_DCM_EN_C 0x45B8 +#define TXCOMCT_HE_SIGB_DCM_EN_C_M 0x20 +#define TXCOMCT_MIDAMBLE_MODE_C 0x45B8 +#define TXCOMCT_MIDAMBLE_MODE_C_M 0x40 +#define TXCOMCT_MUMIMO_LTF_MODE_EN_C 0x45B8 +#define TXCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x80 +#define TXCOMCT_NDP_C 0x45B8 +#define TXCOMCT_NDP_C_M 0x100 +#define TXCOMCT_STBC_EN_C 0x45B8 +#define TXCOMCT_STBC_EN_C_M 0x200 +#define TXINFO_ANT_SEL_A_C 0x45B8 +#define TXINFO_ANT_SEL_A_C_M 0x400 +#define TXINFO_ANT_SEL_B_C 0x45B8 +#define TXINFO_ANT_SEL_B_C_M 0x800 +#define TXINFO_ANT_SEL_C_C 0x45B8 +#define TXINFO_ANT_SEL_C_C_M 0x1000 +#define TXINFO_ANT_SEL_D_C 0x45B8 +#define TXINFO_ANT_SEL_D_C_M 0x2000 +#define TXINFO_CCA_PW_TH_EN_C 0x45B8 +#define TXINFO_CCA_PW_TH_EN_C_M 0x4000 +#define TXINFO_CFIR_BY_RATE_OFF_C 0x45B8 +#define TXINFO_CFIR_BY_RATE_OFF_C_M 0x8000 +#define TXINFO_DPD_BY_RATE_OFF_C 0x45B8 +#define TXINFO_DPD_BY_RATE_OFF_C_M 0x10000 +#define TXINFO_RF_FIXED_GAIN_EN_C 0x45B8 +#define TXINFO_RF_FIXED_GAIN_EN_C_M 0x20000 +#define TXINFO_UL_CQI_RPT_TRI_C 0x45B8 +#define TXINFO_UL_CQI_RPT_TRI_C_M 0x40000 +#define TXTIMCT_LDPC_EXTR_C 0x45B8 +#define TXTIMCT_LDPC_EXTR_C_M 0x80000 +#define TXUSRCT0_DCM_EN_C 0x45B8 +#define TXUSRCT0_DCM_EN_C_M 0x100000 +#define TXUSRCT0_FEC_TYPE_C 0x45B8 +#define TXUSRCT0_FEC_TYPE_C_M 0x200000 +#define TXUSRCT0_TXBF_EN_C 0x45B8 +#define TXUSRCT0_TXBF_EN_C_M 0x400000 +#define TXUSRCT1_DCM_EN_C 0x45B8 +#define TXUSRCT1_DCM_EN_C_M 0x800000 +#define TXUSRCT1_FEC_TYPE_C 0x45B8 +#define TXUSRCT1_FEC_TYPE_C_M 0x1000000 +#define TXUSRCT1_TXBF_EN_C 0x45B8 +#define TXUSRCT1_TXBF_EN_C_M 0x2000000 +#define TXUSRCT2_DCM_EN_C 0x45B8 +#define TXUSRCT2_DCM_EN_C_M 0x4000000 +#define TXUSRCT2_FEC_TYPE_C 0x45B8 +#define TXUSRCT2_FEC_TYPE_C_M 0x8000000 +#define TXUSRCT2_TXBF_EN_C 0x45B8 +#define TXUSRCT2_TXBF_EN_C_M 0x10000000 +#define TXUSRCT3_DCM_EN_C 0x45B8 +#define TXUSRCT3_DCM_EN_C_M 0x20000000 +#define TXUSRCT3_FEC_TYPE_C 0x45B8 +#define TXUSRCT3_FEC_TYPE_C_M 0x40000000 +#define TXUSRCT3_TXBF_EN_C 0x45B8 +#define TXUSRCT3_TXBF_EN_C_M 0x80000000 +#define PCOEFF0_C 0x45BC +#define PCOEFF0_C_M 0xFFF +#define PCOEFF1_C 0x45BC +#define PCOEFF1_C_M 0xFFF000 +#define NORM_FCTR_C 0x45BC +#define NORM_FCTR_C_M 0x3F000000 +#define DELAY_SAMPLE0_C 0x45BC +#define DELAY_SAMPLE0_C_M 0xC0000000 +#define PCOEFF10_C 0x45C0 +#define PCOEFF10_C_M 0xFFF +#define PCOEFF11_C 0x45C0 +#define PCOEFF11_C_M 0xFFF000 +#define DELAY_SAMPLE1_C 0x45C0 +#define DELAY_SAMPLE1_C_M 0x3000000 +#define DELAY_SAMPLE2_C 0x45C0 +#define DELAY_SAMPLE2_C_M 0xC000000 +#define DELAY_SAMPLE3_C 0x45C0 +#define DELAY_SAMPLE3_C_M 0x30000000 +#define TXPSF_SCALE_OPT_C 0x45C0 +#define TXPSF_SCALE_OPT_C_M 0xC0000000 +#define PCOEFF12_C 0x45C4 +#define PCOEFF12_C_M 0xFFF +#define PCOEFF13_C 0x45C4 +#define PCOEFF13_C_M 0xFFF000 +#define PCOEFF14_C 0x45C8 +#define PCOEFF14_C_M 0xFFF +#define PCOEFF15_C 0x45C8 +#define PCOEFF15_C_M 0xFFF000 +#define PCOEFF2_C 0x45CC +#define PCOEFF2_C_M 0xFFF +#define PCOEFF3_C 0x45CC +#define PCOEFF3_C_M 0xFFF000 +#define PCOEFF4_C 0x45D0 +#define PCOEFF4_C_M 0xFFF +#define PCOEFF5_C 0x45D0 +#define PCOEFF5_C_M 0xFFF000 +#define PCOEFF6_C 0x45D4 +#define PCOEFF6_C_M 0xFFF +#define PCOEFF7_C 0x45D4 +#define PCOEFF7_C_M 0xFFF000 +#define PCOEFF8_C 0x45D8 +#define PCOEFF8_C_M 0xFFF +#define PCOEFF9_C 0x45D8 +#define PCOEFF9_C_M 0xFFF000 +#define PATH0_R_A_G_ELNA0_C 0x45DC +#define PATH0_R_A_G_ELNA0_C_M 0xFF +#define PATH0_R_A_G_ELNA1_C 0x45DC +#define PATH0_R_A_G_ELNA1_C_M 0xFF00 +#define PATH0_R_A_G_LNA0_C 0x45DC +#define PATH0_R_A_G_LNA0_C_M 0xFF0000 +#define PATH0_R_A_G_LNA1_C 0x45DC +#define PATH0_R_A_G_LNA1_C_M 0xFF000000 +#define ANTWGT_HIGH_PIN_TH_C 0x45E0 +#define ANTWGT_HIGH_PIN_TH_C_M 0xFF +#define CCK_RSSI_OFST_C 0x45E0 +#define CCK_RSSI_OFST_C_M 0xFF00 +#define NULL_CONNECT_PIN_TH_C 0x45E0 +#define NULL_CONNECT_PIN_TH_C_M 0xFF0000 +#define GAIN_DIFF_TH_0_C 0x45E0 +#define GAIN_DIFF_TH_0_C_M 0x1F000000 +#define ANTWGT_MAX_TOTAL_THRESH_C 0x45E0 +#define ANTWGT_MAX_TOTAL_THRESH_C_M 0x60000000 +#define ANTWGT_ENABLE_C 0x45E0 +#define ANTWGT_ENABLE_C_M 0x80000000 +#define GAIN_DIFF_TH_1_C 0x45E4 +#define GAIN_DIFF_TH_1_C_M 0x1F +#define GAIN_DIFF_TH_2_C 0x45E4 +#define GAIN_DIFF_TH_2_C_M 0x3E0 +#define GAIN_DIFF_TH_3_C 0x45E4 +#define GAIN_DIFF_TH_3_C_M 0x7C00 +#define GAIN_DIFF_TH_4_C 0x45E4 +#define GAIN_DIFF_TH_4_C_M 0xF8000 +#define GAIN_DIFF_TH_5_C 0x45E4 +#define GAIN_DIFF_TH_5_C_M 0x1F00000 +#define GAIN_DIFF_TH_6_C 0x45E4 +#define GAIN_DIFF_TH_6_C_M 0x3E000000 +#define FORCE_EQUAL_WGT_C 0x45E4 +#define FORCE_EQUAL_WGT_C_M 0x40000000 +#define HW_ANTWGT_EN_C 0x45E4 +#define HW_ANTWGT_EN_C_M 0x80000000 +#define GAIN_DIFF_TH_7_C 0x45E8 +#define GAIN_DIFF_TH_7_C_M 0x1F +#define GAIN_DIFF_TH_8_C 0x45E8 +#define GAIN_DIFF_TH_8_C_M 0x3E0 +#define ANTWGT_PEAK_RATIO_THRESH_OPT_C 0x45E8 +#define ANTWGT_PEAK_RATIO_THRESH_OPT_C_M 0x3C00 +#define NULL_CONNECT_CHK_ENABLE_C 0x45E8 +#define NULL_CONNECT_CHK_ENABLE_C_M 0x4000 +#define ANT_PW_SAVE_RSSI_TH_C 0x45F4 +#define ANT_PW_SAVE_RSSI_TH_C_M 0xFF +#define ANT_PW_SAVE_EN_C 0x45F4 +#define ANT_PW_SAVE_EN_C_M 0x100 +#define EDCCA_ENERGY_TH_C 0x4604 +#define EDCCA_ENERGY_TH_C_M 0xFF +#define EDCCA_OFST_C 0x4604 +#define EDCCA_OFST_C_M 0x1F00 +#define EDCCA_FORCE_PATH_C 0x4604 +#define EDCCA_FORCE_PATH_C_M 0x6000 +#define EDCCA_PERIOD_C 0x4604 +#define EDCCA_PERIOD_C_M 0x18000 +#define EDCCA_VLD_TH_C 0x4604 +#define EDCCA_VLD_TH_C_M 0x60000 +#define EDCCA_EN_C 0x4604 +#define EDCCA_EN_C_M 0x80000 +#define EDCCA_FORCE_PATH_EN_C 0x4604 +#define EDCCA_FORCE_PATH_EN_C_M 0x100000 +#define EDCCA_WGTSEL_EN_C 0x4604 +#define EDCCA_WGTSEL_EN_C_M 0x200000 +#define RAKE_EN_C 0x4628 +#define RAKE_EN_C_M 0x1 +#define DC_WIN_EN_C 0x462C +#define DC_WIN_EN_C_M 0x1 +#define FTM_1ST_SPA_C 0x4638 +#define FTM_1ST_SPA_C_M 0xF +#define FTM_ALPHA_RATIO_C 0x4638 +#define FTM_ALPHA_RATIO_C_M 0xF0 +#define FTM_SEARCH_MP_C 0x4638 +#define FTM_SEARCH_MP_C_M 0xF00 +#define FTM_SIR_C 0x4638 +#define FTM_SIR_C_M 0x7000 +#define FTM_L_C 0x4638 +#define FTM_L_C_M 0xC0000 +#define FTM_N_PRO_C 0x4638 +#define FTM_N_PRO_C_M 0x300000 +#define FTM_1ST_MODE_C 0x4638 +#define FTM_1ST_MODE_C_M 0x800000 +#define FTM_MASK_C 0x4638 +#define FTM_MASK_C_M 0x1000000 +#define FTM_SEARCH_RANGE_20_C 0x4638 +#define FTM_SEARCH_RANGE_20_C_M 0x2000000 +#define FTM_SEARCH_RANGE_40_C 0x4638 +#define FTM_SEARCH_RANGE_40_C_M 0x4000000 +#define FTM_SEARCH_RANGE_80_C 0x4638 +#define FTM_SEARCH_RANGE_80_C_M 0x8000000 +#define PATH0_R_ACI_DET_BKP1_C 0x463C +#define PATH0_R_ACI_DET_BKP1_C_M 0xFFFFFFFF +#define PATH0_R_ACI_DET_BKP2_C 0x4640 +#define PATH0_R_ACI_DET_BKP2_C_M 0xFFFFFFFF +#define PATH0_R_ACI_TH_DB_BW20_C 0x4644 +#define PATH0_R_ACI_TH_DB_BW20_C_M 0xFF +#define PATH0_R_ACI_TH_DB_BW40_C 0x4644 +#define PATH0_R_ACI_TH_DB_BW40_C_M 0xFF00 +#define PATH0_R_ACI_TH_DB_BW80_C 0x4644 +#define PATH0_R_ACI_TH_DB_BW80_C_M 0xFF0000 +#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C 0x4644 +#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000 +#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C 0x4648 +#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF +#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C 0x4648 +#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00 +#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C 0x4648 +#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000 +#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C 0x4648 +#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000 +#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C 0x464C +#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF +#define PATH0_R_LARGE_ACI_DB_C 0x464C +#define PATH0_R_LARGE_ACI_DB_C_M 0x7F00 +#define PATH0_R_ACI_NRBW_OFST_BW20_C 0x464C +#define PATH0_R_ACI_NRBW_OFST_BW20_C_M 0x78000 +#define PATH0_R_ACI_NRBW_OFST_BW40_C 0x464C +#define PATH0_R_ACI_NRBW_OFST_BW40_C_M 0x780000 +#define PATH0_R_ACI_NRBW_OFST_BW80_C 0x464C +#define PATH0_R_ACI_NRBW_OFST_BW80_C_M 0x7800000 +#define PATH0_R_ACI_HIT_CNT_TH_C 0x464C +#define PATH0_R_ACI_HIT_CNT_TH_C_M 0x38000000 +#define PATH0_R_ACI_NRBW_OFST_EN_C 0x464C +#define PATH0_R_ACI_NRBW_OFST_EN_C_M 0x40000000 +#define PATH0_R_BYPASS_RFGC_EN_C 0x464C +#define PATH0_R_BYPASS_RFGC_EN_C_M 0x80000000 +#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C 0x4650 +#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF +#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C 0x4650 +#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000 +#define PATH0_R_DC_COMP_EN_C 0x4650 +#define PATH0_R_DC_COMP_EN_C_M 0x10000000 +#define PATH0_R_ADC_DC_OFST_RXMID_IM_C 0x4654 +#define PATH0_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF +#define PATH0_R_ADC_DC_OFST_RXMID_RE_C 0x4654 +#define PATH0_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000 +#define PATH0_R_DC_OFST_IM_C 0x4658 +#define PATH0_R_DC_OFST_IM_C_M 0x3FFF +#define PATH0_R_DC_OFST_RE_C 0x4658 +#define PATH0_R_DC_OFST_RE_C_M 0xFFFC000 +#define PATH0_R_RXTH1_C 0x465C +#define PATH0_R_RXTH1_C_M 0x1F +#define PATH0_R_RXTH2_C 0x465C +#define PATH0_R_RXTH2_C_M 0x3E0 +#define PATH0_R_A_G_LNA2_C 0x4660 +#define PATH0_R_A_G_LNA2_C_M 0xFF +#define PATH0_R_A_G_LNA3_C 0x4660 +#define PATH0_R_A_G_LNA3_C_M 0xFF00 +#define PATH0_R_A_G_LNA4_C 0x4660 +#define PATH0_R_A_G_LNA4_C_M 0xFF0000 +#define PATH0_R_A_G_LNA5_C 0x4660 +#define PATH0_R_A_G_LNA5_C_M 0xFF000000 +#define PATH0_R_A_G_LNA6_C 0x4664 +#define PATH0_R_A_G_LNA6_C_M 0xFF +#define PATH0_R_A_G_RX0_C 0x4664 +#define PATH0_R_A_G_RX0_C_M 0xFF00 +#define PATH0_R_A_G_TIA0_C 0x4664 +#define PATH0_R_A_G_TIA0_C_M 0xFF0000 +#define PATH0_R_A_G_TIA1_C 0x4664 +#define PATH0_R_A_G_TIA1_C_M 0xFF000000 +#define PATH0_R_A_LNA0_OP1DB_C 0x4668 +#define PATH0_R_A_LNA0_OP1DB_C_M 0xFF +#define PATH0_R_A_LNA1_OP1DB_C 0x4668 +#define PATH0_R_A_LNA1_OP1DB_C_M 0xFF00 +#define PATH0_R_A_LNA2_OP1DB_C 0x4668 +#define PATH0_R_A_LNA2_OP1DB_C_M 0xFF0000 +#define PATH0_R_A_LNA3_OP1DB_C 0x4668 +#define PATH0_R_A_LNA3_OP1DB_C_M 0xFF000000 +#define PATH0_R_A_LNA4_OP1DB_C 0x466C +#define PATH0_R_A_LNA4_OP1DB_C_M 0xFF +#define PATH0_R_A_LNA5_OP1DB_C 0x466C +#define PATH0_R_A_LNA5_OP1DB_C_M 0xFF00 +#define PATH0_R_A_LNA6_OP1DB_C 0x466C +#define PATH0_R_A_LNA6_OP1DB_C_M 0xFF0000 +#define PATH0_R_A_RXOP1DB_C 0x466C +#define PATH0_R_A_RXOP1DB_C_M 0xFF000000 +#define PATH0_R_A_TIA0_LNA0_OP1DB_C 0x4670 +#define PATH0_R_A_TIA0_LNA0_OP1DB_C_M 0xFF +#define PATH0_R_A_TIA0_LNA1_OP1DB_C 0x4670 +#define PATH0_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00 +#define PATH0_R_A_TIA0_LNA2_OP1DB_C 0x4670 +#define PATH0_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000 +#define PATH0_R_A_TIA0_LNA3_OP1DB_C 0x4670 +#define PATH0_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000 +#define PATH0_R_A_TIA0_LNA4_OP1DB_C 0x4674 +#define PATH0_R_A_TIA0_LNA4_OP1DB_C_M 0xFF +#define PATH0_R_A_TIA0_LNA5_OP1DB_C 0x4674 +#define PATH0_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00 +#define PATH0_R_A_TIA0_LNA6_OP1DB_C 0x4674 +#define PATH0_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000 +#define PATH0_R_A_TIA1_LNA6_OP1DB_C 0x4674 +#define PATH0_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000 +#define PATH0_R_G_G_ELNA0_C 0x4678 +#define PATH0_R_G_G_ELNA0_C_M 0xFF +#define PATH0_R_G_G_ELNA1_C 0x4678 +#define PATH0_R_G_G_ELNA1_C_M 0xFF00 +#define PATH0_R_G_G_LNA0_C 0x4678 +#define PATH0_R_G_G_LNA0_C_M 0xFF0000 +#define PATH0_R_G_G_LNA1_C 0x4678 +#define PATH0_R_G_G_LNA1_C_M 0xFF000000 +#define PATH0_R_G_G_LNA2_C 0x467C +#define PATH0_R_G_G_LNA2_C_M 0xFF +#define PATH0_R_G_G_LNA3_C 0x467C +#define PATH0_R_G_G_LNA3_C_M 0xFF00 +#define PATH0_R_G_G_LNA4_C 0x467C +#define PATH0_R_G_G_LNA4_C_M 0xFF0000 +#define PATH0_R_G_G_LNA5_C 0x467C +#define PATH0_R_G_G_LNA5_C_M 0xFF000000 +#define PATH0_R_G_G_LNA6_C 0x4680 +#define PATH0_R_G_G_LNA6_C_M 0xFF +#define PATH0_R_G_G_RX0_C 0x4680 +#define PATH0_R_G_G_RX0_C_M 0xFF00 +#define PATH0_R_G_G_TIA0_C 0x4680 +#define PATH0_R_G_G_TIA0_C_M 0xFF0000 +#define PATH0_R_G_G_TIA1_C 0x4680 +#define PATH0_R_G_G_TIA1_C_M 0xFF000000 +#define PATH0_R_G_LGC_DAGC_C 0x4684 +#define PATH0_R_G_LGC_DAGC_C_M 0xFF +#define PATH0_R_G_LNA0_OP1DB_C 0x4684 +#define PATH0_R_G_LNA0_OP1DB_C_M 0xFF00 +#define PATH0_R_G_LNA1_OP1DB_C 0x4684 +#define PATH0_R_G_LNA1_OP1DB_C_M 0xFF0000 +#define PATH0_R_G_LNA2_OP1DB_C 0x4684 +#define PATH0_R_G_LNA2_OP1DB_C_M 0xFF000000 +#define PATH0_R_G_LNA3_OP1DB_C 0x4688 +#define PATH0_R_G_LNA3_OP1DB_C_M 0xFF +#define PATH0_R_G_LNA4_OP1DB_C 0x4688 +#define PATH0_R_G_LNA4_OP1DB_C_M 0xFF00 +#define PATH0_R_G_LNA5_OP1DB_C 0x4688 +#define PATH0_R_G_LNA5_OP1DB_C_M 0xFF0000 +#define PATH0_R_G_LNA6_OP1DB_C 0x4688 +#define PATH0_R_G_LNA6_OP1DB_C_M 0xFF000000 +#define PATH0_R_G_NLGC_DAGC_C 0x468C +#define PATH0_R_G_NLGC_DAGC_C_M 0xFF +#define PATH0_R_G_RXOP1DB_C 0x468C +#define PATH0_R_G_RXOP1DB_C_M 0xFF00 +#define PATH0_R_G_TIA0_LNA0_OP1DB_C 0x468C +#define PATH0_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000 +#define PATH0_R_G_TIA0_LNA1_OP1DB_C 0x468C +#define PATH0_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000 +#define PATH0_R_G_TIA0_LNA2_OP1DB_C 0x4690 +#define PATH0_R_G_TIA0_LNA2_OP1DB_C_M 0xFF +#define PATH0_R_G_TIA0_LNA3_OP1DB_C 0x4690 +#define PATH0_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00 +#define PATH0_R_G_TIA0_LNA4_OP1DB_C 0x4690 +#define PATH0_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000 +#define PATH0_R_G_TIA0_LNA5_OP1DB_C 0x4690 +#define PATH0_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000 +#define PATH0_R_G_TIA0_LNA6_OP1DB_C 0x4694 +#define PATH0_R_G_TIA0_LNA6_OP1DB_C_M 0xFF +#define PATH0_R_G_TIA1_LNA6_OP1DB_C 0x4694 +#define PATH0_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00 +#define PATH0_R_G_OFST_C 0x4694 +#define PATH0_R_G_OFST_C_M 0xFF0000 +#define PATH0_R_IBADC_SAT_TH_C 0x4694 +#define PATH0_R_IBADC_SAT_TH_C_M 0xFF000000 +#define PATH0_R_IBADC_UNDER_TH_C 0x4698 +#define PATH0_R_IBADC_UNDER_TH_C_M 0xFF +#define PATH0_R_WBADC_SAT_TH_C 0x4698 +#define PATH0_R_WBADC_SAT_TH_C_M 0xFF00 +#define PATH0_R_WBADC_SAT_TH_ANTWGT_C 0x4698 +#define PATH0_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000 +#define PATH0_R_WBADC_UNDER_TH_C 0x4698 +#define PATH0_R_WBADC_UNDER_TH_C_M 0xFF000000 +#define PATH0_R_P_PEAK_IBADC_DBM_C 0x469C +#define PATH0_R_P_PEAK_IBADC_DBM_C_M 0x7F +#define PATH0_R_P_PEAK_WBADC_DBM_C 0x469C +#define PATH0_R_P_PEAK_WBADC_DBM_C_M 0x3F80 +#define PATH0_R_ACI_NRBW_TH_C 0x469C +#define PATH0_R_ACI_NRBW_TH_C_M 0xFC000 +#define PATH0_R_BACKOFF_BMODE_C 0x469C +#define PATH0_R_BACKOFF_BMODE_C_M 0x3F00000 +#define PATH0_R_BACKOFF_IBADC_C 0x469C +#define PATH0_R_BACKOFF_IBADC_C_M 0xFC000000 +#define PATH0_R_BACKOFF_LNA_C 0x46A0 +#define PATH0_R_BACKOFF_LNA_C_M 0x3F +#define PATH0_R_BACKOFF_TIA_C 0x46A0 +#define PATH0_R_BACKOFF_TIA_C_M 0xFC0 +#define PATH0_R_BACKOFF_WBADC_C 0x46A0 +#define PATH0_R_BACKOFF_WBADC_C_M 0x3F000 +#define PATH0_R_G_IBADC_IN_C 0x46A0 +#define PATH0_R_G_IBADC_IN_C_M 0xFC0000 +#define PATH0_R_A_GS_SAT_IDX_RX_C 0x46A0 +#define PATH0_R_A_GS_SAT_IDX_RX_C_M 0x1F000000 +#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C 0x46A0 +#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000 +#define PATH0_R_A_GS_UND_IDX_RX_C 0x46A4 +#define PATH0_R_A_GS_UND_IDX_RX_C_M 0x1F +#define PATH0_R_G_GS_SAT_IDX_RX_C 0x46A4 +#define PATH0_R_G_GS_SAT_IDX_RX_C_M 0x3E0 +#define PATH0_R_G_GS_UND_IDX_RX_C 0x46A4 +#define PATH0_R_G_GS_UND_IDX_RX_C_M 0x7C00 +#define PATH0_R_DLY_DCCL_C 0x46A4 +#define PATH0_R_DLY_DCCL_C_M 0x1F00000 +#define PATH0_R_DLY_DFE_C 0x46A4 +#define PATH0_R_DLY_DFE_C_M 0x3E000000 +#define PATH0_R_G_MIXER_C 0x46A4 +#define PATH0_R_G_MIXER_C_M 0xC0000000 +#define PATH0_R_DLY_PRIM_C 0x46A8 +#define PATH0_R_DLY_PRIM_C_M 0x1F +#define PATH0_R_DLY_SYNC_C 0x46A8 +#define PATH0_R_DLY_SYNC_C_M 0x3E0 +#define PATH0_R_RXIDX_INIT_C 0x46A8 +#define PATH0_R_RXIDX_INIT_C_M 0x7C00 +#define PATH0_R_A_GS_SAT_IDX_H_C 0x46A8 +#define PATH0_R_A_GS_SAT_IDX_H_C_M 0x78000 +#define PATH0_R_A_GS_SAT_IDX_L_C 0x46A8 +#define PATH0_R_A_GS_SAT_IDX_L_C_M 0x780000 +#define PATH0_R_A_GS_SAT_IDX_PP1_C 0x46A8 +#define PATH0_R_A_GS_SAT_IDX_PP1_C_M 0x7800000 +#define PATH0_R_A_GS_SAT_IDX_PP2_C 0x46A8 +#define PATH0_R_A_GS_SAT_IDX_PP2_C_M 0x78000000 +#define PATH0_R_1RCCA_PRE_PD_MODE_C 0x46A8 +#define PATH0_R_1RCCA_PRE_PD_MODE_C_M 0x80000000 +#define PATH0_R_A_GS_SAT_TH_H_C 0x46AC +#define PATH0_R_A_GS_SAT_TH_H_C_M 0xF +#define PATH0_R_A_GS_SAT_TH_L_C 0x46AC +#define PATH0_R_A_GS_SAT_TH_L_C_M 0xF0 +#define PATH0_R_A_GS_UND_IDX_C 0x46AC +#define PATH0_R_A_GS_UND_IDX_C_M 0xF00 +#define PATH0_R_A_GS_UND_IDX_PP1_C 0x46AC +#define PATH0_R_A_GS_UND_IDX_PP1_C_M 0xF000 +#define PATH0_R_A_GS_UND_IDX_PP2_C 0x46AC +#define PATH0_R_A_GS_UND_IDX_PP2_C_M 0xF0000 +#define PATH0_R_A_GS_UND_TH_H_C 0x46AC +#define PATH0_R_A_GS_UND_TH_H_C_M 0xF00000 +#define PATH0_R_A_GS_UND_TH_L_C 0x46AC +#define PATH0_R_A_GS_UND_TH_L_C_M 0xF000000 +#define PATH0_R_GC1_TIME_C 0x46AC +#define PATH0_R_GC1_TIME_C_M 0xF0000000 +#define PATH0_R_GC1_TIME_NLGC_C 0x46B0 +#define PATH0_R_GC1_TIME_NLGC_C_M 0xF +#define PATH0_R_GC2_TIME_C 0x46B0 +#define PATH0_R_GC2_TIME_C_M 0xF0 +#define PATH0_R_GC2_TIME_NLGC_C 0x46B0 +#define PATH0_R_GC2_TIME_NLGC_C_M 0xF00 +#define PATH0_R_GC3_TIME_C 0x46B0 +#define PATH0_R_GC3_TIME_C_M 0xF000 +#define PATH0_R_GC4_TIME_C 0x46B0 +#define PATH0_R_GC4_TIME_C_M 0xF0000 +#define PATH0_R_GC5_TIME_C 0x46B0 +#define PATH0_R_GC5_TIME_C_M 0xF00000 +#define PATH0_R_GC_TIME_LESS_80M_C 0x46B0 +#define PATH0_R_GC_TIME_LESS_80M_C_M 0xF000000 +#define PATH0_R_GC_TIME_LESS_NLINEAR_C 0x46B0 +#define PATH0_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000 +#define PATH0_R_G_GS_SAT_IDX_H_C 0x46B4 +#define PATH0_R_G_GS_SAT_IDX_H_C_M 0xF +#define PATH0_R_G_GS_SAT_IDX_L_C 0x46B4 +#define PATH0_R_G_GS_SAT_IDX_L_C_M 0xF0 +#define PATH0_R_G_GS_SAT_IDX_PP1_C 0x46B4 +#define PATH0_R_G_GS_SAT_IDX_PP1_C_M 0xF00 +#define PATH0_R_G_GS_SAT_IDX_PP2_C 0x46B4 +#define PATH0_R_G_GS_SAT_IDX_PP2_C_M 0xF000 +#define PATH0_R_G_GS_SAT_TH_H_C 0x46B4 +#define PATH0_R_G_GS_SAT_TH_H_C_M 0xF0000 +#define PATH0_R_G_GS_SAT_TH_L_C 0x46B4 +#define PATH0_R_G_GS_SAT_TH_L_C_M 0xF00000 +#define PATH0_R_G_GS_UND_IDX_C 0x46B4 +#define PATH0_R_G_GS_UND_IDX_C_M 0xF000000 +#define PATH0_R_G_GS_UND_IDX_PP1_C 0x46B4 +#define PATH0_R_G_GS_UND_IDX_PP1_C_M 0xF0000000 +#define PATH0_R_G_GS_UND_IDX_PP2_C 0x46B8 +#define PATH0_R_G_GS_UND_IDX_PP2_C_M 0xF +#define PATH0_R_G_GS_UND_TH_H_C 0x46B8 +#define PATH0_R_G_GS_UND_TH_H_C_M 0xF0 +#define PATH0_R_G_GS_UND_TH_L_C 0x46B8 +#define PATH0_R_G_GS_UND_TH_L_C_M 0xF00 +#define PATH0_R_ACI_NRBW_RATIO_C 0x46B8 +#define PATH0_R_ACI_NRBW_RATIO_C_M 0xF000 +#define PATH0_R_AGC_RESTART_TH_IB_C 0x46B8 +#define PATH0_R_AGC_RESTART_TH_IB_C_M 0xF0000 +#define PATH0_R_AGC_RESTART_TH_WB_C 0x46B8 +#define PATH0_R_AGC_RESTART_TH_WB_C_M 0xF00000 +#define PATH0_R_DCCL_ALPHA_80_C 0x46B8 +#define PATH0_R_DCCL_ALPHA_80_C_M 0xF000000 +#define PATH0_R_DCCL_ALPHA_N80_C 0x46B8 +#define PATH0_R_DCCL_ALPHA_N80_C_M 0xF0000000 +#define PATH0_R_LGC_FREEZE_TH_H_C 0x46BC +#define PATH0_R_LGC_FREEZE_TH_H_C_M 0xF +#define PATH0_R_LGC_FREEZE_TH_L_C 0x46BC +#define PATH0_R_LGC_FREEZE_TH_L_C_M 0xF0 +#define PATH0_R_NLGC_FREEZE_TH_H_C 0x46BC +#define PATH0_R_NLGC_FREEZE_TH_H_C_M 0xF00 +#define PATH0_R_NLGC_FREEZE_TH_L_C 0x46BC +#define PATH0_R_NLGC_FREEZE_TH_L_C_M 0xF000 +#define PATH0_R_WB_GAIN_IDX_INIT_C 0x46BC +#define PATH0_R_WB_GAIN_IDX_INIT_C_M 0xF0000 +#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C 0x46BC +#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000 +#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C 0x46BC +#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000 +#define PATH0_R_G_WBADC_IN_C 0x46BC +#define PATH0_R_G_WBADC_IN_C_M 0xC0000000 +#define PATH0_R_DCCL_SYNC_BKP1_C 0x46C0 +#define PATH0_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF +#define PATH0_R_DCCL_SYNC_BKP2_C 0x46C4 +#define PATH0_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF +#define PATH0_R_ALPHA_END_IDX_C 0x46C8 +#define PATH0_R_ALPHA_END_IDX_C_M 0xF +#define PATH0_R_ALPHA_START_IDX_C 0x46C8 +#define PATH0_R_ALPHA_START_IDX_C_M 0xF0 +#define PATH0_R_TIME_CONST_IDX_C 0x46C8 +#define PATH0_R_TIME_CONST_IDX_C_M 0x700 +#define PATH0_R_RXFIR_BKP_C 0x46CC +#define PATH0_R_RXFIR_BKP_C_M 0xFFFFFFFF +#define PATH0_R_FORCE_FIR_TYPE_C 0x46D0 +#define PATH0_R_FORCE_FIR_TYPE_C_M 0x3 +#define PATH0_R_CCK_CCA_SHRINK_EN_C 0x46D0 +#define PATH0_R_CCK_CCA_SHRINK_EN_C_M 0x4 +#define PATH0_P20_R_L1_CFO_CMP_EN_C 0x46D4 +#define PATH0_P20_R_L1_CFO_CMP_EN_C_M 0x1 +#define PATH0_S20_R_L1_CFO_CMP_EN_C 0x46D8 +#define PATH0_S20_R_L1_CFO_CMP_EN_C_M 0x1 +#define PATH0_R_NBI_NOTCH_BKP1_C 0x46DC +#define PATH0_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF +#define PATH0_R_NBI_NOTCH_BKP2_C 0x46E0 +#define PATH0_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF +#define PATH0_R_NBI_IDX_C 0x46E4 +#define PATH0_R_NBI_IDX_C_M 0xFF +#define PATH0_R_CORNER_IDX_C 0x46E4 +#define PATH0_R_CORNER_IDX_C_M 0x300 +#define PATH0_R_NBI_FRAC_IDX_C 0x46E4 +#define PATH0_R_NBI_FRAC_IDX_C_M 0xC00 +#define PATH0_R_NBI_NOTCH_EN_C 0x46E4 +#define PATH0_R_NBI_NOTCH_EN_C_M 0x1000 +#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46E8 +#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7 +#define PATH0_P20_R_DAGC_SETTLING_TIME_C 0x46E8 +#define PATH0_P20_R_DAGC_SETTLING_TIME_C_M 0x18 +#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46E8 +#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20 +#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x46E8 +#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40 +#define PATH0_P20_R_PW_EST_TIME_FAGC_C 0x46E8 +#define PATH0_P20_R_PW_EST_TIME_FAGC_C_M 0x80 +#define PATH0_P20_R_PW_EST_TIME_PAGC_C 0x46E8 +#define PATH0_P20_R_PW_EST_TIME_PAGC_C_M 0x100 +#define PATH0_P20_R_PW_EST_TIME_RFGC_C 0x46E8 +#define PATH0_P20_R_PW_EST_TIME_RFGC_C_M 0x200 +#define PATH0_P20_R_SDAGC_EN_C 0x46E8 +#define PATH0_P20_R_SDAGC_EN_C_M 0x400 +#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46EC +#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7 +#define PATH0_S20_R_DAGC_SETTLING_TIME_C 0x46EC +#define PATH0_S20_R_DAGC_SETTLING_TIME_C_M 0x18 +#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46EC +#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20 +#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x46EC +#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40 +#define PATH0_S20_R_PW_EST_TIME_FAGC_C 0x46EC +#define PATH0_S20_R_PW_EST_TIME_FAGC_C_M 0x80 +#define PATH0_S20_R_PW_EST_TIME_PAGC_C 0x46EC +#define PATH0_S20_R_PW_EST_TIME_PAGC_C_M 0x100 +#define PATH0_S20_R_PW_EST_TIME_RFGC_C 0x46EC +#define PATH0_S20_R_PW_EST_TIME_RFGC_C_M 0x200 +#define PATH0_S20_R_SDAGC_EN_C 0x46EC +#define PATH0_S20_R_SDAGC_EN_C_M 0x400 +#define PATH0_R_5MDET_BKP1_C 0x46F0 +#define PATH0_R_5MDET_BKP1_C_M 0xFFFFFFFF +#define PATH0_R_5MDET_BKP2_C 0x46F4 +#define PATH0_R_5MDET_BKP2_C_M 0xFFFFFFFF +#define PATH0_R_5MDET_TH_DB_C 0x46F8 +#define PATH0_R_5MDET_TH_DB_C_M 0x3F +#define PATH0_R_5MDET_MASK_SB0_C 0x46F8 +#define PATH0_R_5MDET_MASK_SB0_C_M 0x40 +#define PATH0_R_5MDET_MASK_SB1_C 0x46F8 +#define PATH0_R_5MDET_MASK_SB1_C_M 0x80 +#define PATH0_R_5MDET_MASK_SB2_C 0x46F8 +#define PATH0_R_5MDET_MASK_SB2_C_M 0x100 +#define PATH0_R_5MDET_MASK_SB3_C 0x46F8 +#define PATH0_R_5MDET_MASK_SB3_C_M 0x200 +#define PATH0_R_5MDET_MODE_C 0x46F8 +#define PATH0_R_5MDET_MODE_C_M 0x400 +#define PATH0_R_IIR_PW_AVG_EN_C 0x46F8 +#define PATH0_R_IIR_PW_AVG_EN_C_M 0x800 +#define PATH0_R_SBF5M_EN_C 0x46F8 +#define PATH0_R_SBF5M_EN_C_M 0x1000 +#define PATH1_R_ACI_DET_BKP1_C 0x46FC +#define PATH1_R_ACI_DET_BKP1_C_M 0xFFFFFFFF +#define PATH1_R_ACI_DET_BKP2_C 0x4700 +#define PATH1_R_ACI_DET_BKP2_C_M 0xFFFFFFFF +#define PATH1_R_ACI_TH_DB_BW20_C 0x4704 +#define PATH1_R_ACI_TH_DB_BW20_C_M 0xFF +#define PATH1_R_ACI_TH_DB_BW40_C 0x4704 +#define PATH1_R_ACI_TH_DB_BW40_C_M 0xFF00 +#define PATH1_R_ACI_TH_DB_BW80_C 0x4704 +#define PATH1_R_ACI_TH_DB_BW80_C_M 0xFF0000 +#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C 0x4704 +#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000 +#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C 0x4708 +#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF +#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C 0x4708 +#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00 +#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C 0x4708 +#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000 +#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C 0x4708 +#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000 +#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C 0x470C +#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF +#define PATH1_R_LARGE_ACI_DB_C 0x470C +#define PATH1_R_LARGE_ACI_DB_C_M 0x7F00 +#define PATH1_R_ACI_NRBW_OFST_BW20_C 0x470C +#define PATH1_R_ACI_NRBW_OFST_BW20_C_M 0x78000 +#define PATH1_R_ACI_NRBW_OFST_BW40_C 0x470C +#define PATH1_R_ACI_NRBW_OFST_BW40_C_M 0x780000 +#define PATH1_R_ACI_NRBW_OFST_BW80_C 0x470C +#define PATH1_R_ACI_NRBW_OFST_BW80_C_M 0x7800000 +#define PATH1_R_ACI_HIT_CNT_TH_C 0x470C +#define PATH1_R_ACI_HIT_CNT_TH_C_M 0x38000000 +#define PATH1_R_ACI_NRBW_OFST_EN_C 0x470C +#define PATH1_R_ACI_NRBW_OFST_EN_C_M 0x40000000 +#define PATH1_R_BYPASS_RFGC_EN_C 0x470C +#define PATH1_R_BYPASS_RFGC_EN_C_M 0x80000000 +#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C 0x4710 +#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF +#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C 0x4710 +#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000 +#define PATH1_R_DC_COMP_EN_C 0x4710 +#define PATH1_R_DC_COMP_EN_C_M 0x10000000 +#define PATH1_R_ADC_DC_OFST_RXMID_IM_C 0x4714 +#define PATH1_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF +#define PATH1_R_ADC_DC_OFST_RXMID_RE_C 0x4714 +#define PATH1_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000 +#define PATH1_R_DC_OFST_IM_C 0x4718 +#define PATH1_R_DC_OFST_IM_C_M 0x3FFF +#define PATH1_R_DC_OFST_RE_C 0x4718 +#define PATH1_R_DC_OFST_RE_C_M 0xFFFC000 +#define PATH1_R_RXTH1_C 0x471C +#define PATH1_R_RXTH1_C_M 0x1F +#define PATH1_R_RXTH2_C 0x471C +#define PATH1_R_RXTH2_C_M 0x3E0 +#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7 +#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38 +#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0 +#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00 +#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000 +#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000 +#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000 +#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000 +#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000 +#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C 0x4720 +#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000 +#define PATH0_R_IBADC_PW_ALPHA_H_C 0x4720 +#define PATH0_R_IBADC_PW_ALPHA_H_C_M 0xC0000000 +#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C 0x4724 +#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7 +#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C 0x4724 +#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38 +#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C 0x4724 +#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0 +#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00 +#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000 +#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000 +#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000 +#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000 +#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000 +#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C 0x4724 +#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000 +#define PATH0_R_IBADC_PW_ALPHA_L_C 0x4724 +#define PATH0_R_IBADC_PW_ALPHA_L_C_M 0xC0000000 +#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7 +#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38 +#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0 +#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00 +#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000 +#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000 +#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000 +#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000 +#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C 0x4728 +#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000 +#define PATH0_R_BT_LNA_IDX0_C 0x4728 +#define PATH0_R_BT_LNA_IDX0_C_M 0x38000000 +#define PATH0_R_LINEAR_STEP_LIM_C 0x4728 +#define PATH0_R_LINEAR_STEP_LIM_C_M 0xC0000000 +#define PATH0_R_BT_LNA_IDX1_C 0x472C +#define PATH0_R_BT_LNA_IDX1_C_M 0x7 +#define PATH0_R_BT_LNA_IDX2_C 0x472C +#define PATH0_R_BT_LNA_IDX2_C_M 0x38 +#define PATH0_R_BT_LNA_IDX3_C 0x472C +#define PATH0_R_BT_LNA_IDX3_C_M 0x1C0 +#define PATH0_R_ELNA_SEL_MARGIN_LGC_C 0x472C +#define PATH0_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00 +#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C 0x472C +#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000 +#define PATH0_R_IBADC_CLIP_RATIO_C 0x472C +#define PATH0_R_IBADC_CLIP_RATIO_C_M 0x38000 +#define PATH0_R_IBADC_CLIP_TH_C 0x472C +#define PATH0_R_IBADC_CLIP_TH_C_M 0x1C0000 +#define PATH0_R_LGC_STEP_LIM_C 0x472C +#define PATH0_R_LGC_STEP_LIM_C_M 0xE00000 +#define PATH0_R_LNA_IDX_INIT_C 0x472C +#define PATH0_R_LNA_IDX_INIT_C_M 0x7000000 +#define PATH0_R_LNA_SEL_MARGIN_LGC_C 0x472C +#define PATH0_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000 +#define PATH0_R_LINEAR_STEP_MIN_C 0x472C +#define PATH0_R_LINEAR_STEP_MIN_C_M 0xC0000000 +#define PATH0_R_LNA_SEL_MARGIN_NLGC_C 0x4730 +#define PATH0_R_LNA_SEL_MARGIN_NLGC_C_M 0x7 +#define PATH0_R_RXSEL_MARGIN_LGC_C 0x4730 +#define PATH0_R_RXSEL_MARGIN_LGC_C_M 0x38 +#define PATH0_R_RXSEL_MARGIN_NLGC_C 0x4730 +#define PATH0_R_RXSEL_MARGIN_NLGC_C_M 0x1C0 +#define PATH0_R_TIA_SEL_MARGIN_LGC_C 0x4730 +#define PATH0_R_TIA_SEL_MARGIN_LGC_C_M 0xE00 +#define PATH0_R_TIA_SEL_MARGIN_NLGC_C 0x4730 +#define PATH0_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000 +#define PATH0_R_WBADC_CLIP_RATIO_C 0x4730 +#define PATH0_R_WBADC_CLIP_RATIO_C_M 0x38000 +#define PATH0_R_WBADC_CLIP_TH_C 0x4730 +#define PATH0_R_WBADC_CLIP_TH_C_M 0x1C0000 +#define PATH0_R_NLGC_STEP_LIM_C 0x4730 +#define PATH0_R_NLGC_STEP_LIM_C_M 0x600000 +#define PATH0_R_NLGC_STEP_MIN_C 0x4730 +#define PATH0_R_NLGC_STEP_MIN_C_M 0x1800000 +#define PATH0_R_POST_PD_STEP_LIM_C 0x4730 +#define PATH0_R_POST_PD_STEP_LIM_C_M 0x6000000 +#define PATH0_R_POST_PD_STEP_MIN_C 0x4730 +#define PATH0_R_POST_PD_STEP_MIN_C_M 0x18000000 +#define PATH0_R_PRE_PD_STEP_LIM_C 0x4730 +#define PATH0_R_PRE_PD_STEP_LIM_C_M 0x60000000 +#define PATH0_R_AGC_EN_C 0x4730 +#define PATH0_R_AGC_EN_C_M 0x80000000 +#define PATH0_R_PRE_PD_STEP_MIN_C 0x4734 +#define PATH0_R_PRE_PD_STEP_MIN_C_M 0x3 +#define PATH0_R_WBADC_PW_ALPHA_H_C 0x4734 +#define PATH0_R_WBADC_PW_ALPHA_H_C_M 0xC +#define PATH0_R_WBADC_PW_ALPHA_L_C 0x4734 +#define PATH0_R_WBADC_PW_ALPHA_L_C_M 0x30 +#define PATH0_R_A_WB_GIDX_00_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_00_ELNA_C_M 0x40 +#define PATH0_R_A_WB_GIDX_01_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_01_ELNA_C_M 0x80 +#define PATH0_R_A_WB_GIDX_02_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_02_ELNA_C_M 0x100 +#define PATH0_R_A_WB_GIDX_03_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_03_ELNA_C_M 0x200 +#define PATH0_R_A_WB_GIDX_04_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_04_ELNA_C_M 0x400 +#define PATH0_R_A_WB_GIDX_05_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_05_ELNA_C_M 0x800 +#define PATH0_R_A_WB_GIDX_06_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_06_ELNA_C_M 0x1000 +#define PATH0_R_A_WB_GIDX_07_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_07_ELNA_C_M 0x2000 +#define PATH0_R_A_WB_GIDX_08_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_08_ELNA_C_M 0x4000 +#define PATH0_R_A_WB_GIDX_09_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_09_ELNA_C_M 0x8000 +#define PATH0_R_A_WB_GIDX_10_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_10_ELNA_C_M 0x10000 +#define PATH0_R_A_WB_GIDX_11_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_11_ELNA_C_M 0x20000 +#define PATH0_R_A_WB_GIDX_12_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_12_ELNA_C_M 0x40000 +#define PATH0_R_A_WB_GIDX_13_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_13_ELNA_C_M 0x80000 +#define PATH0_R_A_WB_GIDX_14_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_14_ELNA_C_M 0x100000 +#define PATH0_R_A_WB_GIDX_15_ELNA_C 0x4734 +#define PATH0_R_A_WB_GIDX_15_ELNA_C_M 0x200000 +#define PATH0_R_GC_TIME_1T_MORE_C 0x4734 +#define PATH0_R_GC_TIME_1T_MORE_C_M 0x400000 +#define PATH0_R_G_WB_GIDX_00_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_00_ELNA_C_M 0x800000 +#define PATH0_R_G_WB_GIDX_01_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_01_ELNA_C_M 0x1000000 +#define PATH0_R_G_WB_GIDX_02_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_02_ELNA_C_M 0x2000000 +#define PATH0_R_G_WB_GIDX_03_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_03_ELNA_C_M 0x4000000 +#define PATH0_R_G_WB_GIDX_04_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_04_ELNA_C_M 0x8000000 +#define PATH0_R_G_WB_GIDX_05_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_05_ELNA_C_M 0x10000000 +#define PATH0_R_G_WB_GIDX_06_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_06_ELNA_C_M 0x20000000 +#define PATH0_R_G_WB_GIDX_07_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_07_ELNA_C_M 0x40000000 +#define PATH0_R_G_WB_GIDX_08_ELNA_C 0x4734 +#define PATH0_R_G_WB_GIDX_08_ELNA_C_M 0x80000000 +#define PATH0_R_G_WB_GIDX_09_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_09_ELNA_C_M 0x1 +#define PATH0_R_G_WB_GIDX_10_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_10_ELNA_C_M 0x2 +#define PATH0_R_G_WB_GIDX_11_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_11_ELNA_C_M 0x4 +#define PATH0_R_G_WB_GIDX_12_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_12_ELNA_C_M 0x8 +#define PATH0_R_G_WB_GIDX_13_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_13_ELNA_C_M 0x10 +#define PATH0_R_G_WB_GIDX_14_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_14_ELNA_C_M 0x20 +#define PATH0_R_G_WB_GIDX_15_ELNA_C 0x4738 +#define PATH0_R_G_WB_GIDX_15_ELNA_C_M 0x40 +#define PATH0_R_SE1_TIME_C 0x4738 +#define PATH0_R_SE1_TIME_C_M 0x80 +#define PATH0_R_SE1_TIME_NLGC_C 0x4738 +#define PATH0_R_SE1_TIME_NLGC_C_M 0x100 +#define PATH0_R_SE2_TIME_C 0x4738 +#define PATH0_R_SE2_TIME_C_M 0x200 +#define PATH0_R_SE2_TIME_NLGC_C 0x4738 +#define PATH0_R_SE2_TIME_NLGC_C_M 0x400 +#define PATH0_R_SE3_TIME_C 0x4738 +#define PATH0_R_SE3_TIME_C_M 0x800 +#define PATH0_R_SE4_TIME_C 0x4738 +#define PATH0_R_SE4_TIME_C_M 0x1000 +#define PATH0_R_SE5_TIME_C 0x4738 +#define PATH0_R_SE5_TIME_C_M 0x2000 +#define PATH0_R_SE_TIME_DONE_C 0x4738 +#define PATH0_R_SE_TIME_DONE_C_M 0x4000 +#define PATH0_R_SE_TIME_LINEAR_EXT_C 0x4738 +#define PATH0_R_SE_TIME_LINEAR_EXT_C_M 0x8000 +#define PATH0_R_ACI_NRBW_EN_C 0x4738 +#define PATH0_R_ACI_NRBW_EN_C_M 0x10000 +#define PATH0_R_BAND_SEL_C 0x4738 +#define PATH0_R_BAND_SEL_C_M 0x20000 +#define PATH0_R_BT_RX_MODE_EN_C 0x4738 +#define PATH0_R_BT_RX_MODE_EN_C_M 0x40000 +#define PATH0_R_BT_SHARE_C 0x4738 +#define PATH0_R_BT_SHARE_C_M 0x80000 +#define PATH0_R_BT_TX_FORCE_NRBW_C 0x4738 +#define PATH0_R_BT_TX_FORCE_NRBW_C_M 0x100000 +#define PATH0_R_BT_TX_MODE_EN_C 0x4738 +#define PATH0_R_BT_TX_MODE_EN_C_M 0x200000 +#define PATH0_R_BTG_PATH_C 0x4738 +#define PATH0_R_BTG_PATH_C_M 0x400000 +#define PATH0_R_CCK_FORCE_NRBW_C 0x4738 +#define PATH0_R_CCK_FORCE_NRBW_C_M 0x800000 +#define PATH0_R_DCCL_EN_C 0x4738 +#define PATH0_R_DCCL_EN_C_M 0x1000000 +#define PATH0_R_ELNA_BYPASS_EN_C 0x4738 +#define PATH0_R_ELNA_BYPASS_EN_C_M 0x2000000 +#define PATH0_R_ELNA_EN_C 0x4738 +#define PATH0_R_ELNA_EN_C_M 0x4000000 +#define PATH0_R_ELNA_IDX_INIT_C 0x4738 +#define PATH0_R_ELNA_IDX_INIT_C_M 0x8000000 +#define PATH0_R_FORCE_BT_COEX_C 0x4738 +#define PATH0_R_FORCE_BT_COEX_C_M 0x10000000 +#define PATH0_R_FORCE_NRBW_C 0x4738 +#define PATH0_R_FORCE_NRBW_C_M 0x20000000 +#define PATH0_R_I_ONLY_C 0x4738 +#define PATH0_R_I_ONLY_C_M 0x40000000 +#define PATH0_R_LGC_DAGC_EN_C 0x4738 +#define PATH0_R_LGC_DAGC_EN_C_M 0x80000000 +#define PATH0_R_LINEAR_AGC_EN_C 0x473C +#define PATH0_R_LINEAR_AGC_EN_C_M 0x1 +#define PATH0_R_LINEAR_MARGIN_MODE_C 0x473C +#define PATH0_R_LINEAR_MARGIN_MODE_C_M 0x2 +#define PATH0_R_NLGC_AGC_EN_C 0x473C +#define PATH0_R_NLGC_AGC_EN_C_M 0x4 +#define PATH0_R_NLGC_DAGC_EN_C 0x473C +#define PATH0_R_NLGC_DAGC_EN_C_M 0x8 +#define PATH0_R_NRBW_DEF_C 0x473C +#define PATH0_R_NRBW_DEF_C_M 0x10 +#define PATH0_R_POST_PD_AGC_EN_C 0x473C +#define PATH0_R_POST_PD_AGC_EN_C_M 0x20 +#define PATH0_R_PRE_PD_AGC_EN_C 0x473C +#define PATH0_R_PRE_PD_AGC_EN_C_M 0x40 +#define PATH0_R_PURE_POST_PD_MODE_C 0x473C +#define PATH0_R_PURE_POST_PD_MODE_C_M 0x80 +#define PATH0_R_SYNC_PRE_PD_STEP_C 0x473C +#define PATH0_R_SYNC_PRE_PD_STEP_C_M 0x100 +#define PATH0_R_TIA_IDX_INIT_C 0x473C +#define PATH0_R_TIA_IDX_INIT_C_M 0x200 +#define PATH0_R_TIA_SHRINK_DEF_C 0x473C +#define PATH0_R_TIA_SHRINK_DEF_C_M 0x400 +#define PATH0_R_TIA_SHRINK_EN_C 0x473C +#define PATH0_R_TIA_SHRINK_EN_C_M 0x800 +#define PATH0_R_TIA_SHRINK_INIT_C 0x473C +#define PATH0_R_TIA_SHRINK_INIT_C_M 0x1000 +#define PATH1_R_A_G_ELNA0_C 0x4740 +#define PATH1_R_A_G_ELNA0_C_M 0xFF +#define PATH1_R_A_G_ELNA1_C 0x4740 +#define PATH1_R_A_G_ELNA1_C_M 0xFF00 +#define PATH1_R_A_G_LNA0_C 0x4740 +#define PATH1_R_A_G_LNA0_C_M 0xFF0000 +#define PATH1_R_A_G_LNA1_C 0x4740 +#define PATH1_R_A_G_LNA1_C_M 0xFF000000 +#define PATH1_R_A_G_LNA2_C 0x4744 +#define PATH1_R_A_G_LNA2_C_M 0xFF +#define PATH1_R_A_G_LNA3_C 0x4744 +#define PATH1_R_A_G_LNA3_C_M 0xFF00 +#define PATH1_R_A_G_LNA4_C 0x4744 +#define PATH1_R_A_G_LNA4_C_M 0xFF0000 +#define PATH1_R_A_G_LNA5_C 0x4744 +#define PATH1_R_A_G_LNA5_C_M 0xFF000000 +#define PATH1_R_A_G_LNA6_C 0x4748 +#define PATH1_R_A_G_LNA6_C_M 0xFF +#define PATH1_R_A_G_RX0_C 0x4748 +#define PATH1_R_A_G_RX0_C_M 0xFF00 +#define PATH1_R_A_G_TIA0_C 0x4748 +#define PATH1_R_A_G_TIA0_C_M 0xFF0000 +#define PATH1_R_A_G_TIA1_C 0x4748 +#define PATH1_R_A_G_TIA1_C_M 0xFF000000 +#define PATH1_R_A_LNA0_OP1DB_C 0x474C +#define PATH1_R_A_LNA0_OP1DB_C_M 0xFF +#define PATH1_R_A_LNA1_OP1DB_C 0x474C +#define PATH1_R_A_LNA1_OP1DB_C_M 0xFF00 +#define PATH1_R_A_LNA2_OP1DB_C 0x474C +#define PATH1_R_A_LNA2_OP1DB_C_M 0xFF0000 +#define PATH1_R_A_LNA3_OP1DB_C 0x474C +#define PATH1_R_A_LNA3_OP1DB_C_M 0xFF000000 +#define PATH1_R_A_LNA4_OP1DB_C 0x4750 +#define PATH1_R_A_LNA4_OP1DB_C_M 0xFF +#define PATH1_R_A_LNA5_OP1DB_C 0x4750 +#define PATH1_R_A_LNA5_OP1DB_C_M 0xFF00 +#define PATH1_R_A_LNA6_OP1DB_C 0x4750 +#define PATH1_R_A_LNA6_OP1DB_C_M 0xFF0000 +#define PATH1_R_A_RXOP1DB_C 0x4750 +#define PATH1_R_A_RXOP1DB_C_M 0xFF000000 +#define PATH1_R_A_TIA0_LNA0_OP1DB_C 0x4754 +#define PATH1_R_A_TIA0_LNA0_OP1DB_C_M 0xFF +#define PATH1_R_A_TIA0_LNA1_OP1DB_C 0x4754 +#define PATH1_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00 +#define PATH1_R_A_TIA0_LNA2_OP1DB_C 0x4754 +#define PATH1_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000 +#define PATH1_R_A_TIA0_LNA3_OP1DB_C 0x4754 +#define PATH1_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000 +#define PATH1_R_A_TIA0_LNA4_OP1DB_C 0x4758 +#define PATH1_R_A_TIA0_LNA4_OP1DB_C_M 0xFF +#define PATH1_R_A_TIA0_LNA5_OP1DB_C 0x4758 +#define PATH1_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00 +#define PATH1_R_A_TIA0_LNA6_OP1DB_C 0x4758 +#define PATH1_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000 +#define PATH1_R_A_TIA1_LNA6_OP1DB_C 0x4758 +#define PATH1_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000 +#define PATH1_R_G_G_ELNA0_C 0x475C +#define PATH1_R_G_G_ELNA0_C_M 0xFF +#define PATH1_R_G_G_ELNA1_C 0x475C +#define PATH1_R_G_G_ELNA1_C_M 0xFF00 +#define PATH1_R_G_G_LNA0_C 0x475C +#define PATH1_R_G_G_LNA0_C_M 0xFF0000 +#define PATH1_R_G_G_LNA1_C 0x475C +#define PATH1_R_G_G_LNA1_C_M 0xFF000000 +#define PATH1_R_G_G_LNA2_C 0x4760 +#define PATH1_R_G_G_LNA2_C_M 0xFF +#define PATH1_R_G_G_LNA3_C 0x4760 +#define PATH1_R_G_G_LNA3_C_M 0xFF00 +#define PATH1_R_G_G_LNA4_C 0x4760 +#define PATH1_R_G_G_LNA4_C_M 0xFF0000 +#define PATH1_R_G_G_LNA5_C 0x4760 +#define PATH1_R_G_G_LNA5_C_M 0xFF000000 +#define PATH1_R_G_G_LNA6_C 0x4764 +#define PATH1_R_G_G_LNA6_C_M 0xFF +#define PATH1_R_G_G_RX0_C 0x4764 +#define PATH1_R_G_G_RX0_C_M 0xFF00 +#define PATH1_R_G_G_TIA0_C 0x4764 +#define PATH1_R_G_G_TIA0_C_M 0xFF0000 +#define PATH1_R_G_G_TIA1_C 0x4764 +#define PATH1_R_G_G_TIA1_C_M 0xFF000000 +#define PATH1_R_G_LGC_DAGC_C 0x4768 +#define PATH1_R_G_LGC_DAGC_C_M 0xFF +#define PATH1_R_G_LNA0_OP1DB_C 0x4768 +#define PATH1_R_G_LNA0_OP1DB_C_M 0xFF00 +#define PATH1_R_G_LNA1_OP1DB_C 0x4768 +#define PATH1_R_G_LNA1_OP1DB_C_M 0xFF0000 +#define PATH1_R_G_LNA2_OP1DB_C 0x4768 +#define PATH1_R_G_LNA2_OP1DB_C_M 0xFF000000 +#define PATH1_R_G_LNA3_OP1DB_C 0x476C +#define PATH1_R_G_LNA3_OP1DB_C_M 0xFF +#define PATH1_R_G_LNA4_OP1DB_C 0x476C +#define PATH1_R_G_LNA4_OP1DB_C_M 0xFF00 +#define PATH1_R_G_LNA5_OP1DB_C 0x476C +#define PATH1_R_G_LNA5_OP1DB_C_M 0xFF0000 +#define PATH1_R_G_LNA6_OP1DB_C 0x476C +#define PATH1_R_G_LNA6_OP1DB_C_M 0xFF000000 +#define PATH1_R_G_NLGC_DAGC_C 0x4770 +#define PATH1_R_G_NLGC_DAGC_C_M 0xFF +#define PATH1_R_G_RXOP1DB_C 0x4770 +#define PATH1_R_G_RXOP1DB_C_M 0xFF00 +#define PATH1_R_G_TIA0_LNA0_OP1DB_C 0x4770 +#define PATH1_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000 +#define PATH1_R_G_TIA0_LNA1_OP1DB_C 0x4770 +#define PATH1_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000 +#define PATH1_R_G_TIA0_LNA2_OP1DB_C 0x4774 +#define PATH1_R_G_TIA0_LNA2_OP1DB_C_M 0xFF +#define PATH1_R_G_TIA0_LNA3_OP1DB_C 0x4774 +#define PATH1_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00 +#define PATH1_R_G_TIA0_LNA4_OP1DB_C 0x4774 +#define PATH1_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000 +#define PATH1_R_G_TIA0_LNA5_OP1DB_C 0x4774 +#define PATH1_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000 +#define PATH1_R_G_TIA0_LNA6_OP1DB_C 0x4778 +#define PATH1_R_G_TIA0_LNA6_OP1DB_C_M 0xFF +#define PATH1_R_G_TIA1_LNA6_OP1DB_C 0x4778 +#define PATH1_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00 +#define PATH1_R_G_OFST_C 0x4778 +#define PATH1_R_G_OFST_C_M 0xFF0000 +#define PATH1_R_IBADC_SAT_TH_C 0x4778 +#define PATH1_R_IBADC_SAT_TH_C_M 0xFF000000 +#define PATH1_R_IBADC_UNDER_TH_C 0x477C +#define PATH1_R_IBADC_UNDER_TH_C_M 0xFF +#define PATH1_R_WBADC_SAT_TH_C 0x477C +#define PATH1_R_WBADC_SAT_TH_C_M 0xFF00 +#define PATH1_R_WBADC_SAT_TH_ANTWGT_C 0x477C +#define PATH1_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000 +#define PATH1_R_WBADC_UNDER_TH_C 0x477C +#define PATH1_R_WBADC_UNDER_TH_C_M 0xFF000000 +#define PATH1_R_DCCL_SYNC_BKP1_C 0x4780 +#define PATH1_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF +#define PATH1_R_DCCL_SYNC_BKP2_C 0x4784 +#define PATH1_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF +#define PATH1_R_ALPHA_END_IDX_C 0x4788 +#define PATH1_R_ALPHA_END_IDX_C_M 0xF +#define PATH1_R_ALPHA_START_IDX_C 0x4788 +#define PATH1_R_ALPHA_START_IDX_C_M 0xF0 +#define PATH1_R_TIME_CONST_IDX_C 0x4788 +#define PATH1_R_TIME_CONST_IDX_C_M 0x700 +#define PATH1_R_RXFIR_BKP_C 0x478C +#define PATH1_R_RXFIR_BKP_C_M 0xFFFFFFFF +#define PATH1_R_FORCE_FIR_TYPE_C 0x4790 +#define PATH1_R_FORCE_FIR_TYPE_C_M 0x3 +#define PATH1_R_CCK_CCA_SHRINK_EN_C 0x4790 +#define PATH1_R_CCK_CCA_SHRINK_EN_C_M 0x4 +#define PATH1_P20_R_L1_CFO_CMP_EN_C 0x4794 +#define PATH1_P20_R_L1_CFO_CMP_EN_C_M 0x1 +#define PATH1_S20_R_L1_CFO_CMP_EN_C 0x4798 +#define PATH1_S20_R_L1_CFO_CMP_EN_C_M 0x1 +#define PATH1_R_NBI_NOTCH_BKP1_C 0x479C +#define PATH1_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF +#define PATH1_R_NBI_NOTCH_BKP2_C 0x47A0 +#define PATH1_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF +#define PATH1_R_NBI_IDX_C 0x47A4 +#define PATH1_R_NBI_IDX_C_M 0xFF +#define PATH1_R_CORNER_IDX_C 0x47A4 +#define PATH1_R_CORNER_IDX_C_M 0x300 +#define PATH1_R_NBI_FRAC_IDX_C 0x47A4 +#define PATH1_R_NBI_FRAC_IDX_C_M 0xC00 +#define PATH1_R_NBI_NOTCH_EN_C 0x47A4 +#define PATH1_R_NBI_NOTCH_EN_C_M 0x1000 +#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47A8 +#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7 +#define PATH1_P20_R_DAGC_SETTLING_TIME_C 0x47A8 +#define PATH1_P20_R_DAGC_SETTLING_TIME_C_M 0x18 +#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47A8 +#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20 +#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x47A8 +#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40 +#define PATH1_P20_R_PW_EST_TIME_FAGC_C 0x47A8 +#define PATH1_P20_R_PW_EST_TIME_FAGC_C_M 0x80 +#define PATH1_P20_R_PW_EST_TIME_PAGC_C 0x47A8 +#define PATH1_P20_R_PW_EST_TIME_PAGC_C_M 0x100 +#define PATH1_P20_R_PW_EST_TIME_RFGC_C 0x47A8 +#define PATH1_P20_R_PW_EST_TIME_RFGC_C_M 0x200 +#define PATH1_P20_R_SDAGC_EN_C 0x47A8 +#define PATH1_P20_R_SDAGC_EN_C_M 0x400 +#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47AC +#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7 +#define PATH1_S20_R_DAGC_SETTLING_TIME_C 0x47AC +#define PATH1_S20_R_DAGC_SETTLING_TIME_C_M 0x18 +#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47AC +#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20 +#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x47AC +#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40 +#define PATH1_S20_R_PW_EST_TIME_FAGC_C 0x47AC +#define PATH1_S20_R_PW_EST_TIME_FAGC_C_M 0x80 +#define PATH1_S20_R_PW_EST_TIME_PAGC_C 0x47AC +#define PATH1_S20_R_PW_EST_TIME_PAGC_C_M 0x100 +#define PATH1_S20_R_PW_EST_TIME_RFGC_C 0x47AC +#define PATH1_S20_R_PW_EST_TIME_RFGC_C_M 0x200 +#define PATH1_S20_R_SDAGC_EN_C 0x47AC +#define PATH1_S20_R_SDAGC_EN_C_M 0x400 +#define PATH1_R_5MDET_BKP1_C 0x47B0 +#define PATH1_R_5MDET_BKP1_C_M 0xFFFFFFFF +#define PATH1_R_5MDET_BKP2_C 0x47B4 +#define PATH1_R_5MDET_BKP2_C_M 0xFFFFFFFF +#define PATH1_R_5MDET_TH_DB_C 0x47B8 +#define PATH1_R_5MDET_TH_DB_C_M 0x3F +#define PATH1_R_5MDET_MASK_SB0_C 0x47B8 +#define PATH1_R_5MDET_MASK_SB0_C_M 0x40 +#define PATH1_R_5MDET_MASK_SB1_C 0x47B8 +#define PATH1_R_5MDET_MASK_SB1_C_M 0x80 +#define PATH1_R_5MDET_MASK_SB2_C 0x47B8 +#define PATH1_R_5MDET_MASK_SB2_C_M 0x100 +#define PATH1_R_5MDET_MASK_SB3_C 0x47B8 +#define PATH1_R_5MDET_MASK_SB3_C_M 0x200 +#define PATH1_R_5MDET_MODE_C 0x47B8 +#define PATH1_R_5MDET_MODE_C_M 0x400 +#define PATH1_R_IIR_PW_AVG_EN_C 0x47B8 +#define PATH1_R_IIR_PW_AVG_EN_C_M 0x800 +#define PATH1_R_SBF5M_EN_C 0x47B8 +#define PATH1_R_SBF5M_EN_C_M 0x1000 +#define POP_RSV_C 0x47C4 +#define POP_RSV_C_M 0xFFFFFFFF +#define CLIPPING_LVL_C 0x47C8 +#define CLIPPING_LVL_C_M 0x3FF +#define CLIPPING_OBS_C 0x47C8 +#define CLIPPING_OBS_C_M 0x1FC00 +#define CLIPPING_RATIO_C 0x47C8 +#define CLIPPING_RATIO_C_M 0xFE0000 +#define B_THD_C 0x47C8 +#define B_THD_C_M 0x3F000000 +#define BT_GNT_POP_EN_C 0x47C8 +#define BT_GNT_POP_EN_C_M 0x40000000 +#define CCK_EN_C 0x47C8 +#define CCK_EN_C_M 0x80000000 +#define M_THD_C 0x47CC +#define M_THD_C_M 0x3F +#define CCK_DROP_TH_C 0x47CC +#define CCK_DROP_TH_C_M 0x7C0 +#define CCK_POP_H_TH_C 0x47CC +#define CCK_POP_H_TH_C_M 0xF800 +#define CCK_POP_L_TH_C 0x47CC +#define CCK_POP_L_TH_C_M 0x1F0000 +#define D_CNT_C 0x47CC +#define D_CNT_C_M 0x3E00000 +#define D_THD_C 0x47CC +#define D_THD_C_M 0x7C000000 +#define D_EN_C 0x47CC +#define D_EN_C_M 0x80000000 +#define H_THD_C 0x47D0 +#define H_THD_C_M 0x1F +#define L_THD_C 0x47D0 +#define L_THD_C_M 0x3E0 +#define OFDM_DROP_TH_C 0x47D0 +#define OFDM_DROP_TH_C_M 0x7C00 +#define OFDM_POP_H_TH_C 0x47D0 +#define OFDM_POP_H_TH_C_M 0xF8000 +#define OFDM_POP_L_TH_C 0x47D0 +#define OFDM_POP_L_TH_C_M 0x1F00000 +#define P_CNT_C 0x47D0 +#define P_CNT_C_M 0x3E000000 +#define D_LSIG_RDY_C 0x47D0 +#define D_LSIG_RDY_C_M 0x40000000 +#define DL_EN_C 0x47D0 +#define DL_EN_C_M 0x80000000 +#define O_THD_C 0x47D4 +#define O_THD_C_M 0x7 +#define REFPW_LB_C 0x47D4 +#define REFPW_LB_C_M 0x38 +#define M_40_C 0x47D4 +#define M_40_C_M 0x40 +#define OFDM_EN_C 0x47D4 +#define OFDM_EN_C_M 0x80 +#define P_EN_C 0x47D4 +#define P_EN_C_M 0x100 +#define P_LSIG_RDY_C 0x47D4 +#define P_LSIG_RDY_C_M 0x200 +#define REFPW_LB_EN_C 0x47D4 +#define REFPW_LB_EN_C_M 0x400 +#define P20_SEG0R_PINTHD_C 0x47D8 +#define P20_SEG0R_PINTHD_C_M 0xFF +#define P20_SEG0R_PWDIF_C 0x47D8 +#define P20_SEG0R_PWDIF_C_M 0x3F00 +#define P20_SEG0R_P20TAR_C 0x47D8 +#define P20_SEG0R_P20TAR_C_M 0x7C000 +#define P20_SEG0R_BT_WGT_C 0x47D8 +#define P20_SEG0R_BT_WGT_C_M 0x380000 +#define P20_SEG0R_UNIT_WGT_OPT_C 0x47D8 +#define P20_SEG0R_UNIT_WGT_OPT_C_M 0x400000 +#define P20_SEG0R_WGT_EN_C 0x47D8 +#define P20_SEG0R_WGT_EN_C_M 0x800000 +#define P20_SEG0R_ZERO_WGT_EN_C 0x47D8 +#define P20_SEG0R_ZERO_WGT_EN_C_M 0x1000000 +#define S20_SEG0R_PINTHD_C 0x47DC +#define S20_SEG0R_PINTHD_C_M 0xFF +#define S20_SEG0R_PWDIF_C 0x47DC +#define S20_SEG0R_PWDIF_C_M 0x3F00 +#define S20_SEG0R_P20TAR_C 0x47DC +#define S20_SEG0R_P20TAR_C_M 0x7C000 +#define S20_SEG0R_BT_WGT_C 0x47DC +#define S20_SEG0R_BT_WGT_C_M 0x380000 +#define S20_SEG0R_UNIT_WGT_OPT_C 0x47DC +#define S20_SEG0R_UNIT_WGT_OPT_C_M 0x400000 +#define S20_SEG0R_WGT_EN_C 0x47DC +#define S20_SEG0R_WGT_EN_C_M 0x800000 +#define S20_SEG0R_ZERO_WGT_EN_C 0x47DC +#define S20_SEG0R_ZERO_WGT_EN_C_M 0x1000000 +#define BW_INDSEG0R_BW_GAIN_CHK_THD_C 0x47E0 +#define BW_INDSEG0R_BW_GAIN_CHK_THD_C_M 0x3F +#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C 0x47E0 +#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C_M 0x7C0 +#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C 0x47E0 +#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C_M 0xF800 +#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C 0x47E0 +#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C_M 0x1F0000 +#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C 0x47E0 +#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C_M 0x3E00000 +#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C 0x47E0 +#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C_M 0x7C000000 +#define BW_INDSEG0R_BW_GAIN_CHK_EN_C 0x47E0 +#define BW_INDSEG0R_BW_GAIN_CHK_EN_C_M 0x80000000 +#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C 0x47E4 +#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C_M 0x1F +#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C 0x47E4 +#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C_M 0x3E0 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C 0x47E4 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C_M 0x7C00 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C 0x47E4 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C_M 0xF8000 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C 0x47E4 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C_M 0x1F00000 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C 0x47E4 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C_M 0x3E000000 +#define BW_INDSEG0R_BW_START_CHK_EN_C 0x47E4 +#define BW_INDSEG0R_BW_START_CHK_EN_C_M 0x40000000 +#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C 0x47E4 +#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C_M 0x80000000 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C 0x47E8 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C_M 0x1F +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C 0x47E8 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C_M 0x3E0 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C 0x47E8 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C_M 0x7C00 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C 0x47E8 +#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C_M 0xF8000 +#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C 0x47E8 +#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C_M 0xF00000 +#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C 0x47E8 +#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C_M 0xF000000 +#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C 0x47E8 +#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C_M 0xF0000000 +#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C 0x47EC +#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C_M 0xF +#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C 0x47EC +#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C_M 0xF0 +#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C 0x47EC +#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C_M 0xF00 +#define BW_INDSEG0R_INTF_TH_0_C 0x47EC +#define BW_INDSEG0R_INTF_TH_0_C_M 0xF000 +#define BW_INDSEG0R_INTF_TH_1_C 0x47EC +#define BW_INDSEG0R_INTF_TH_1_C_M 0xF0000 +#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C 0x47EC +#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C_M 0xF00000 +#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C 0x47EC +#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C_M 0x7000000 +#define BW_INDSEG0R_SUB20_SEARCH_TH_C 0x47EC +#define BW_INDSEG0R_SUB20_SEARCH_TH_C_M 0x38000000 +#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C 0x47EC +#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x40000000 +#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C 0x47EC +#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C_M 0x80000000 +#define BW_INDSEG0R_EARLY_DROP_BY_L1_C 0x47F0 +#define BW_INDSEG0R_EARLY_DROP_BY_L1_C_M 0x1 +#define BW_INDSEG0R_FORCE_BW_EN_C 0x47F0 +#define BW_INDSEG0R_FORCE_BW_EN_C_M 0x2 +#define BW_INDSEG0R_FORCE_BW_MODE_C 0x47F0 +#define BW_INDSEG0R_FORCE_BW_MODE_C_M 0x4 +#define SEG0R_HIGH_PIN_TH_CFO_C 0x47F4 +#define SEG0R_HIGH_PIN_TH_CFO_C_M 0x1F +#define SEG0R_HIGH_PIN_TH_CFOE_C 0x47F4 +#define SEG0R_HIGH_PIN_TH_CFOE_C_M 0x1E0 +#define SEG0R_CFO_START_OFST_C 0x47F4 +#define SEG0R_CFO_START_OFST_C_M 0xE00 +#define SEG0R_CFO_SIZE_OPT_C 0x47F4 +#define SEG0R_CFO_SIZE_OPT_C_M 0x3000 +#define SEG0R_COUNT_INI_PH_C 0x47F4 +#define SEG0R_COUNT_INI_PH_C_M 0xC000 +#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C 0x47F8 +#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C_M 0x3FF +#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C 0x47F8 +#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C_M 0xFFC00 +#define SEG0R_H2L_TH_C 0x47F8 +#define SEG0R_H2L_TH_C_M 0xFF00000 +#define SEG0R_ZERO_CRO_OBS_INTRVL_C 0x47F8 +#define SEG0R_ZERO_CRO_OBS_INTRVL_C_M 0xF0000000 +#define SEG0R_L2H_TH_C 0x47FC +#define SEG0R_L2H_TH_C_M 0xFF +#define SEG0R_RXI_CHK_TH_C 0x47FC +#define SEG0R_RXI_CHK_TH_C_M 0xFF00 +#define SEG0R_ADCPW_C 0x47FC +#define SEG0R_ADCPW_C_M 0x7F0000 +#define SEG0R_ZERO_CRO_HIGH_TH_C 0x47FC +#define SEG0R_ZERO_CRO_HIGH_TH_C_M 0x3F800000 +#define SEG0R_DCRM_EN_C 0x47FC +#define SEG0R_DCRM_EN_C_M 0x40000000 +#define SEG0R_RFGC_EN_C 0x47FC +#define SEG0R_RFGC_EN_C_M 0x80000000 +#define SEG0R_DC_COUNT_MAX_C 0x4800 +#define SEG0R_DC_COUNT_MAX_C_M 0xF +#define SEG0R_DC_HIGH_TH_20_NRX1_C 0x4800 +#define SEG0R_DC_HIGH_TH_20_NRX1_C_M 0xF0 +#define SEG0R_DC_HIGH_TH_20_NRX2_C 0x4800 +#define SEG0R_DC_HIGH_TH_20_NRX2_C_M 0xF00 +#define SEG0R_DC_HIGH_TH_40_NRX1_C 0x4800 +#define SEG0R_DC_HIGH_TH_40_NRX1_C_M 0xF000 +#define SEG0R_DC_HIGH_TH_40_NRX2_C 0x4800 +#define SEG0R_DC_HIGH_TH_40_NRX2_C_M 0xF0000 +#define SEG0R_DC_HIGH_TH_80_NRX1_C 0x4800 +#define SEG0R_DC_HIGH_TH_80_NRX1_C_M 0xF00000 +#define SEG0R_DC_HIGH_TH_80_NRX2_C 0x4800 +#define SEG0R_DC_HIGH_TH_80_NRX2_C_M 0xF000000 +#define SEG0R_DC_HIGH_TH_80P80_NRX1_C 0x4800 +#define SEG0R_DC_HIGH_TH_80P80_NRX1_C_M 0xF0000000 +#define SEG0R_DC_HIGH_TH_80P80_NRX2_C 0x4804 +#define SEG0R_DC_HIGH_TH_80P80_NRX2_C_M 0xF +#define SEG0R_DC_LOW_TH_20_NRX1_C 0x4804 +#define SEG0R_DC_LOW_TH_20_NRX1_C_M 0xF0 +#define SEG0R_DC_LOW_TH_20_NRX2_C 0x4804 +#define SEG0R_DC_LOW_TH_20_NRX2_C_M 0xF00 +#define SEG0R_DC_LOW_TH_40_NRX1_C 0x4804 +#define SEG0R_DC_LOW_TH_40_NRX1_C_M 0xF000 +#define SEG0R_DC_LOW_TH_40_NRX2_C 0x4804 +#define SEG0R_DC_LOW_TH_40_NRX2_C_M 0xF0000 +#define SEG0R_DC_LOW_TH_80_NRX1_C 0x4804 +#define SEG0R_DC_LOW_TH_80_NRX1_C_M 0xF00000 +#define SEG0R_DC_LOW_TH_80_NRX2_C 0x4804 +#define SEG0R_DC_LOW_TH_80_NRX2_C_M 0xF000000 +#define SEG0R_DC_LOW_TH_80P80_NRX1_C 0x4804 +#define SEG0R_DC_LOW_TH_80P80_NRX1_C_M 0xF0000000 +#define SEG0R_DC_LOW_TH_80P80_NRX2_C 0x4808 +#define SEG0R_DC_LOW_TH_80P80_NRX2_C_M 0xF +#define SEG0R_DC_TH_OFST_C 0x4808 +#define SEG0R_DC_TH_OFST_C_M 0xF0 +#define SEG0R_DCFI_COUNT_MAX_C 0x4808 +#define SEG0R_DCFI_COUNT_MAX_C_M 0xF00 +#define SEG0R_DCFI_HIGH_TH_20_NRX1_C 0x4808 +#define SEG0R_DCFI_HIGH_TH_20_NRX1_C_M 0xF000 +#define SEG0R_DCFI_HIGH_TH_20_NRX2_C 0x4808 +#define SEG0R_DCFI_HIGH_TH_20_NRX2_C_M 0xF0000 +#define SEG0R_DCFI_HIGH_TH_40_NRX1_C 0x4808 +#define SEG0R_DCFI_HIGH_TH_40_NRX1_C_M 0xF00000 +#define SEG0R_DCFI_HIGH_TH_40_NRX2_C 0x4808 +#define SEG0R_DCFI_HIGH_TH_40_NRX2_C_M 0xF000000 +#define SEG0R_DCFI_HIGH_TH_80_NRX1_C 0x4808 +#define SEG0R_DCFI_HIGH_TH_80_NRX1_C_M 0xF0000000 +#define SEG0R_DCFI_HIGH_TH_80_NRX2_C 0x480C +#define SEG0R_DCFI_HIGH_TH_80_NRX2_C_M 0xF +#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C 0x480C +#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C_M 0xF0 +#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C 0x480C +#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C_M 0xF00 +#define SEG0R_DCFI_LOW_TH_20_NRX1_C 0x480C +#define SEG0R_DCFI_LOW_TH_20_NRX1_C_M 0xF000 +#define SEG0R_DCFI_LOW_TH_20_NRX2_C 0x480C +#define SEG0R_DCFI_LOW_TH_20_NRX2_C_M 0xF0000 +#define SEG0R_DCFI_LOW_TH_40_NRX1_C 0x480C +#define SEG0R_DCFI_LOW_TH_40_NRX1_C_M 0xF00000 +#define SEG0R_DCFI_LOW_TH_40_NRX2_C 0x480C +#define SEG0R_DCFI_LOW_TH_40_NRX2_C_M 0xF000000 +#define SEG0R_DCFI_LOW_TH_80_NRX1_C 0x480C +#define SEG0R_DCFI_LOW_TH_80_NRX1_C_M 0xF0000000 +#define SEG0R_DCFI_LOW_TH_80_NRX2_C 0x4810 +#define SEG0R_DCFI_LOW_TH_80_NRX2_C_M 0xF +#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C 0x4810 +#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C_M 0xF0 +#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C 0x4810 +#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C_M 0xF00 +#define SEG0R_DCFI_REF_COUNT_MAX_C 0x4810 +#define SEG0R_DCFI_REF_COUNT_MAX_C_M 0xF000 +#define SEG0R_DCFI_TH_OFST_C 0x4810 +#define SEG0R_DCFI_TH_OFST_C_M 0xF0000 +#define SEG0R_DCPR_HIGH_TH_20_NRX1_C 0x4810 +#define SEG0R_DCPR_HIGH_TH_20_NRX1_C_M 0xF00000 +#define SEG0R_DCPR_HIGH_TH_20_NRX2_C 0x4810 +#define SEG0R_DCPR_HIGH_TH_20_NRX2_C_M 0xF000000 +#define SEG0R_DCPR_HIGH_TH_40_NRX1_C 0x4810 +#define SEG0R_DCPR_HIGH_TH_40_NRX1_C_M 0xF0000000 +#define SEG0R_DCPR_HIGH_TH_40_NRX2_C 0x4814 +#define SEG0R_DCPR_HIGH_TH_40_NRX2_C_M 0xF +#define SEG0R_DCPR_HIGH_TH_80_NRX1_C 0x4814 +#define SEG0R_DCPR_HIGH_TH_80_NRX1_C_M 0xF0 +#define SEG0R_DCPR_HIGH_TH_80_NRX2_C 0x4814 +#define SEG0R_DCPR_HIGH_TH_80_NRX2_C_M 0xF00 +#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C 0x4814 +#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C_M 0xF000 +#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C 0x4814 +#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C_M 0xF0000 +#define SEG0R_DCPR_LOW_TH_20_NRX1_C 0x4814 +#define SEG0R_DCPR_LOW_TH_20_NRX1_C_M 0xF00000 +#define SEG0R_DCPR_LOW_TH_20_NRX2_C 0x4814 +#define SEG0R_DCPR_LOW_TH_20_NRX2_C_M 0xF000000 +#define SEG0R_DCPR_LOW_TH_40_NRX1_C 0x4814 +#define SEG0R_DCPR_LOW_TH_40_NRX1_C_M 0xF0000000 +#define SEG0R_DCPR_LOW_TH_40_NRX2_C 0x4818 +#define SEG0R_DCPR_LOW_TH_40_NRX2_C_M 0xF +#define SEG0R_DCPR_LOW_TH_80_NRX1_C 0x4818 +#define SEG0R_DCPR_LOW_TH_80_NRX1_C_M 0xF0 +#define SEG0R_DCPR_LOW_TH_80_NRX2_C 0x4818 +#define SEG0R_DCPR_LOW_TH_80_NRX2_C_M 0xF00 +#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C 0x4818 +#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C_M 0xF000 +#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C 0x4818 +#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C_M 0xF0000 +#define SEG0R_DCPR_RST_TH_C 0x4818 +#define SEG0R_DCPR_RST_TH_C_M 0xF00000 +#define SEG0R_DCPR_COUNT_MAX_C 0x4818 +#define SEG0R_DCPR_COUNT_MAX_C_M 0x3000000 +#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C 0x4818 +#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C_M 0xC000000 +#define SEG0R_DCPR_RST_COUNT_MAX_C 0x4818 +#define SEG0R_DCPR_RST_COUNT_MAX_C_M 0x30000000 +#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C 0x481C +#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C_M 0x1F +#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C 0x481C +#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C_M 0x3E0 +#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C 0x481C +#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C_M 0x7C00 +#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C 0x481C +#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C_M 0xF8000 +#define SEG0R_FINE_TUNE_STOP_LMT_C 0x481C +#define SEG0R_FINE_TUNE_STOP_LMT_C_M 0x1F00000 +#define SEG0R_CBW20_DC_MAX_RATIO_C 0x481C +#define SEG0R_CBW20_DC_MAX_RATIO_C_M 0x1E000000 +#define SEG0R_FINE_TUNE_DELTA_C 0x481C +#define SEG0R_FINE_TUNE_DELTA_C_M 0xE0000000 +#define SEG0R_CBW40_DC_MAX_RATIO_C 0x4820 +#define SEG0R_CBW40_DC_MAX_RATIO_C_M 0xF +#define SEG0R_CBW80_DC_MAX_RATIO_C 0x4820 +#define SEG0R_CBW80_DC_MAX_RATIO_C_M 0xF0 +#define SEG0R_CBW80P80_DC_MAX_RATIO_C 0x4820 +#define SEG0R_CBW80P80_DC_MAX_RATIO_C_M 0xF00 +#define SEG0R_DC_MAX_RATIO_20_NRX1_C 0x4820 +#define SEG0R_DC_MAX_RATIO_20_NRX1_C_M 0xF000 +#define SEG0R_DC_MAX_RATIO_20_NRX2_C 0x4820 +#define SEG0R_DC_MAX_RATIO_20_NRX2_C_M 0xF0000 +#define SEG0R_DC_MAX_RATIO_40_NRX1_C 0x4820 +#define SEG0R_DC_MAX_RATIO_40_NRX1_C_M 0xF00000 +#define SEG0R_DC_MAX_RATIO_40_NRX2_C 0x4820 +#define SEG0R_DC_MAX_RATIO_40_NRX2_C_M 0xF000000 +#define SEG0R_DC_MAX_RATIO_80_NRX1_C 0x4820 +#define SEG0R_DC_MAX_RATIO_80_NRX1_C_M 0xF0000000 +#define SEG0R_DC_MAX_RATIO_80_NRX2_C 0x4824 +#define SEG0R_DC_MAX_RATIO_80_NRX2_C_M 0xF +#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C 0x4824 +#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C_M 0xF0 +#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C 0x4824 +#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C_M 0xF00 +#define SEG0R_FINE_TUNE_LMT_C 0x4824 +#define SEG0R_FINE_TUNE_LMT_C_M 0xF000 +#define SEG0R_FINE_TUNE_PROCESS_DELAY_C 0x4824 +#define SEG0R_FINE_TUNE_PROCESS_DELAY_C_M 0xF0000 +#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C 0x4824 +#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C_M 0xF00000 +#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C 0x4824 +#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C_M 0xF000000 +#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C 0x4824 +#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C_M 0xF0000000 +#define SEG0R_FINE_TUNE_OPT_C 0x4828 +#define SEG0R_FINE_TUNE_OPT_C_M 0x3 +#define SEG0R_FINE_TUNE_TRUNC_EN_C 0x4828 +#define SEG0R_FINE_TUNE_TRUNC_EN_C_M 0x4 +#define SEG0R_FORCE_CDD_REFINE_OFF_C 0x4828 +#define SEG0R_FORCE_CDD_REFINE_OFF_C_M 0x8 +#define P20_SEG0R_L1_L2_AVG_START_TIME_C 0x482C +#define P20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3 +#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x482C +#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4 +#define P20_SEG0R_L1_L2_AVG_OPT_C 0x482C +#define P20_SEG0R_L1_L2_AVG_OPT_C_M 0x8 +#define S20_SEG0R_L1_L2_AVG_START_TIME_C 0x4830 +#define S20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3 +#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x4830 +#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4 +#define S20_SEG0R_L1_L2_AVG_OPT_C 0x4830 +#define S20_SEG0R_L1_L2_AVG_OPT_C_M 0x8 +#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C 0x4834 +#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C_M 0x7FF +#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C 0x4834 +#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C_M 0x3FF800 +#define PROCSEG0R_ADV_SINR_TH_C 0x4834 +#define PROCSEG0R_ADV_SINR_TH_C_M 0x3FC00000 +#define PROCSEG0R_CH_AVG_SIZE_C 0x4834 +#define PROCSEG0R_CH_AVG_SIZE_C_M 0xC0000000 +#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C 0x4838 +#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C_M 0x7FF +#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C 0x4838 +#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C_M 0x3FF800 +#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C 0x4838 +#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000 +#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C 0x4838 +#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000 +#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C 0x483C +#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C_M 0x7FF +#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C 0x483C +#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C_M 0x3FF800 +#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C 0x483C +#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C_M 0x7C00000 +#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C 0x483C +#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C_M 0xF8000000 +#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C 0x4840 +#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C_M 0x7FF +#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C 0x4840 +#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C_M 0x3FF800 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C 0x4840 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00000 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C 0x4840 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000000 +#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C 0x4844 +#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C_M 0x7FF +#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C 0x4844 +#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C_M 0x3FF800 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C 0x4844 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C_M 0x7C00000 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C 0x4844 +#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C_M 0xF8000000 +#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C 0x4848 +#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C_M 0x7FF +#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C 0x4848 +#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C_M 0x3FF800 +#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C 0x4848 +#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C_M 0x7C00000 +#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C 0x4848 +#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000 +#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C 0x484C +#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C_M 0x7FF +#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C 0x484C +#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C_M 0x3FF800 +#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C 0x484C +#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C_M 0x7C00000 +#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C 0x484C +#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000 +#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C 0x4850 +#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C_M 0x7FF +#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C 0x4850 +#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C_M 0x3FF800 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C 0x4850 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C 0x4850 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C_M 0x1F +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C_M 0x3E0 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C_M 0x1F00000 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C 0x4854 +#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C_M 0x3E000000 +#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C 0x4854 +#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C_M 0x40000000 +#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4854 +#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x80000000 +#define PROCSEG0R_FS_WGT_OFST_0_C 0x4858 +#define PROCSEG0R_FS_WGT_OFST_0_C_M 0xF +#define PROCSEG0R_FS_WGT_OFST_1_C 0x4858 +#define PROCSEG0R_FS_WGT_OFST_1_C_M 0xF0 +#define PROCSEG0R_L1_L2_PROCESS_DELAY_C 0x4858 +#define PROCSEG0R_L1_L2_PROCESS_DELAY_C_M 0xF00 +#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C 0x4858 +#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C_M 0xF000 +#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C 0x4858 +#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C_M 0xF0000 +#define PROCSEG0R_CDD0_WGT_OFST_0_C 0x4858 +#define PROCSEG0R_CDD0_WGT_OFST_0_C_M 0xF00000 +#define PROCSEG0R_CDD0_WGT_OFST_1_C 0x4858 +#define PROCSEG0R_CDD0_WGT_OFST_1_C_M 0xF000000 +#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C 0x4858 +#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C_M 0xF0000000 +#define PROCSEG0R_CH_FALLING_COUNT_MAX_C 0x485C +#define PROCSEG0R_CH_FALLING_COUNT_MAX_C_M 0xF +#define PROCSEG0R_INTF_TH_0_C 0x485C +#define PROCSEG0R_INTF_TH_0_C_M 0xF0 +#define PROCSEG0R_INTF_TH_1_C 0x485C +#define PROCSEG0R_INTF_TH_1_C_M 0xF00 +#define PROCSEG0R_TARGET_COUNT_MAX_C 0x485C +#define PROCSEG0R_TARGET_COUNT_MAX_C_M 0xF000 +#define PROCSEG0R_FS_PEAK_WGT_C 0x485C +#define PROCSEG0R_FS_PEAK_WGT_C_M 0x70000 +#define PROCSEG0R_CDD0_COUNT_LMT_C 0x485C +#define PROCSEG0R_CDD0_COUNT_LMT_C_M 0x380000 +#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C 0x485C +#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C_M 0x1C00000 +#define PROCSEG0R_CH_BEGIN_TH_C 0x485C +#define PROCSEG0R_CH_BEGIN_TH_C_M 0xE000000 +#define PROCSEG0R_CR_SWITCH_BY_PIN_C 0x485C +#define PROCSEG0R_CR_SWITCH_BY_PIN_C_M 0x70000000 +#define SEG0R_PW_TH_C 0x4860 +#define SEG0R_PW_TH_C_M 0x3F +#define SEG0R_PD_LOWER_BOUND_C 0x4860 +#define SEG0R_PD_LOWER_BOUND_C_M 0x7C0 +#define SEG0R_PD_UPPER_BOUND_C 0x4860 +#define SEG0R_PD_UPPER_BOUND_C_M 0xF800 +#define SEG0R_HIGH_PIN_TH_DCFI_C 0x4860 +#define SEG0R_HIGH_PIN_TH_DCFI_C_M 0x1F0000 +#define SEG0R_VERY_HIGH_PIN_TH_C 0x4860 +#define SEG0R_VERY_HIGH_PIN_TH_C_M 0x3E00000 +#define SEG0R_DCFI_FALLING_TH_20_C 0x4860 +#define SEG0R_DCFI_FALLING_TH_20_C_M 0x3C000000 +#define SEG0R_PD_SPATIAL_REUSE_EN_C 0x4860 +#define SEG0R_PD_SPATIAL_REUSE_EN_C_M 0x40000000 +#define SEG0R_DCFI_EN_C 0x4860 +#define SEG0R_DCFI_EN_C_M 0x80000000 +#define SEG0R_DCFI_FALLING_TH_40_C 0x4864 +#define SEG0R_DCFI_FALLING_TH_40_C_M 0xF +#define SEG0R_DCFI_FALLING_TH_80_C 0x4864 +#define SEG0R_DCFI_FALLING_TH_80_C_M 0xF0 +#define SEG0R_DCFI_FALLING_TH_80P80_C 0x4864 +#define SEG0R_DCFI_FALLING_TH_80P80_C_M 0xF00 +#define SEG0R_DCFI_RISING_TH_20_C 0x4864 +#define SEG0R_DCFI_RISING_TH_20_C_M 0xF000 +#define SEG0R_DCFI_RISING_TH_40_C 0x4864 +#define SEG0R_DCFI_RISING_TH_40_C_M 0xF0000 +#define SEG0R_DCFI_RISING_TH_80_C 0x4864 +#define SEG0R_DCFI_RISING_TH_80_C_M 0xF00000 +#define SEG0R_DCFI_RISING_TH_80P80_C 0x4864 +#define SEG0R_DCFI_RISING_TH_80P80_C_M 0xF000000 +#define SEG0R_FALLING_COUNT_MAX_C 0x4864 +#define SEG0R_FALLING_COUNT_MAX_C_M 0xF0000000 +#define SEG0R_FALLING_TH_C 0x4868 +#define SEG0R_FALLING_TH_C_M 0xF +#define SEG0R_RISING_COUNT_MAX_C 0x4868 +#define SEG0R_RISING_COUNT_MAX_C_M 0xF0 +#define SEG0R_WAIT_SETTLE_PERIOD_C 0x4868 +#define SEG0R_WAIT_SETTLE_PERIOD_C_M 0xF00 +#define SEG0R_DCPR_EN_C 0x4868 +#define SEG0R_DCPR_EN_C_M 0x1000 +#define SEG0R_DYN_PW_EN_C 0x4868 +#define SEG0R_DYN_PW_EN_C_M 0x2000 +#define SEG0R_FALLING_EDGE_OPT_C 0x4868 +#define SEG0R_FALLING_EDGE_OPT_C_M 0x4000 +#define SEG0R_FORCE_DCFI_EN_C 0x4868 +#define SEG0R_FORCE_DCFI_EN_C_M 0x8000 +#define SEG0R_SB5M_BLK_EN_C 0x4868 +#define SEG0R_SB5M_BLK_EN_C_M 0x10000 +#define P20_SEG0R_PW_DBM_TH_C 0x486C +#define P20_SEG0R_PW_DBM_TH_C_M 0x7F +#define P20_SEG0R_PW_TH_C 0x486C +#define P20_SEG0R_PW_TH_C_M 0x1F80 +#define P20_SEG0R_DYN_FALLING_TH_C 0x486C +#define P20_SEG0R_DYN_FALLING_TH_C_M 0x7E000 +#define P20_SEG0R_DYN_RISING_TH_C 0x486C +#define P20_SEG0R_DYN_RISING_TH_C_M 0x1F80000 +#define P20_SEG0R_DYN_TH_MAX_C 0x486C +#define P20_SEG0R_DYN_TH_MAX_C_M 0x7E000000 +#define P20_SEG0R_DYN_TH_EN_C 0x486C +#define P20_SEG0R_DYN_TH_EN_C_M 0x80000000 +#define P20_SEG0R_DYN_TH_MIN_C 0x4870 +#define P20_SEG0R_DYN_TH_MIN_C_M 0x3F +#define P20_SEG0R_DYN_COVER_FCTR_C 0x4870 +#define P20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0 +#define P20_SEG0R_DYN_LAMBDA_C 0x4870 +#define P20_SEG0R_DYN_LAMBDA_C_M 0x1C00 +#define P20_SEG0R_DYN_WAIT_PERIOD_C 0x4870 +#define P20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000 +#define P20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4870 +#define P20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000 +#define P20_SEG0R_DYN_OBSER_SIZE_C 0x4870 +#define P20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000 +#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4870 +#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000 +#define P20_SEG0R_PATH_SEL_C 0x4870 +#define P20_SEG0R_PATH_SEL_C_M 0x1800000 +#define P20_SEG0R_PATH_SEL_EN_C 0x4870 +#define P20_SEG0R_PATH_SEL_EN_C_M 0x2000000 +#define S20_SEG0R_PW_DBM_TH_C 0x4874 +#define S20_SEG0R_PW_DBM_TH_C_M 0x7F +#define S20_SEG0R_PW_TH_C 0x4874 +#define S20_SEG0R_PW_TH_C_M 0x1F80 +#define S20_SEG0R_DYN_FALLING_TH_C 0x4874 +#define S20_SEG0R_DYN_FALLING_TH_C_M 0x7E000 +#define S20_SEG0R_DYN_RISING_TH_C 0x4874 +#define S20_SEG0R_DYN_RISING_TH_C_M 0x1F80000 +#define S20_SEG0R_DYN_TH_MAX_C 0x4874 +#define S20_SEG0R_DYN_TH_MAX_C_M 0x7E000000 +#define S20_SEG0R_DYN_TH_EN_C 0x4874 +#define S20_SEG0R_DYN_TH_EN_C_M 0x80000000 +#define S20_SEG0R_DYN_TH_MIN_C 0x4878 +#define S20_SEG0R_DYN_TH_MIN_C_M 0x3F +#define S20_SEG0R_DYN_COVER_FCTR_C 0x4878 +#define S20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0 +#define S20_SEG0R_DYN_LAMBDA_C 0x4878 +#define S20_SEG0R_DYN_LAMBDA_C_M 0x1C00 +#define S20_SEG0R_DYN_WAIT_PERIOD_C 0x4878 +#define S20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000 +#define S20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4878 +#define S20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000 +#define S20_SEG0R_DYN_OBSER_SIZE_C 0x4878 +#define S20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000 +#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4878 +#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000 +#define S20_SEG0R_PATH_SEL_C 0x4878 +#define S20_SEG0R_PATH_SEL_C_M 0x1800000 +#define S20_SEG0R_PATH_SEL_EN_C 0x4878 +#define S20_SEG0R_PATH_SEL_EN_C_M 0x2000000 +#define SMFSEG0R_MF_TH_OFST_0_C 0x487C +#define SMFSEG0R_MF_TH_OFST_0_C_M 0xF +#define SMFSEG0R_MF_TH_OFST_1_C 0x487C +#define SMFSEG0R_MF_TH_OFST_1_C_M 0xF0 +#define SMFSEG0R_MF_TH_20_NRX1_C 0x487C +#define SMFSEG0R_MF_TH_20_NRX1_C_M 0xF00 +#define SMFSEG0R_MF_TH_20_NRX2_C 0x487C +#define SMFSEG0R_MF_TH_20_NRX2_C_M 0xF000 +#define SMFSEG0R_MF_TH_40_NRX1_C 0x487C +#define SMFSEG0R_MF_TH_40_NRX1_C_M 0xF0000 +#define SMFSEG0R_MF_TH_40_NRX2_C 0x487C +#define SMFSEG0R_MF_TH_40_NRX2_C_M 0xF00000 +#define SMFSEG0R_MF_TH_80_NRX1_C 0x487C +#define SMFSEG0R_MF_TH_80_NRX1_C_M 0xF000000 +#define SMFSEG0R_MF_TH_80_NRX2_C 0x487C +#define SMFSEG0R_MF_TH_80_NRX2_C_M 0xF0000000 +#define SMFSEG0R_MF_TH_80P80_NRX1_C 0x4880 +#define SMFSEG0R_MF_TH_80P80_NRX1_C_M 0xF +#define SMFSEG0R_MF_TH_80P80_NRX2_C 0x4880 +#define SMFSEG0R_MF_TH_80P80_NRX2_C_M 0xF0 +#define SMFSEG0R_INTF_TH_0_C 0x4880 +#define SMFSEG0R_INTF_TH_0_C_M 0xF00 +#define SMFSEG0R_INTF_TH_1_C 0x4880 +#define SMFSEG0R_INTF_TH_1_C_M 0xF000 +#define SMFSEG0R_MF_HOLD_C 0x4880 +#define SMFSEG0R_MF_HOLD_C_M 0x70000 +#define SMFSEG0R_MF_WIN_L_C 0x4880 +#define SMFSEG0R_MF_WIN_L_C_M 0x380000 +#define SMFSEG0R_CR_SWITCH_BY_PIN_C 0x4880 +#define SMFSEG0R_CR_SWITCH_BY_PIN_C_M 0x1C00000 +#define SMFSEG0R_MF_PEAK_OPT_C 0x4880 +#define SMFSEG0R_MF_PEAK_OPT_C_M 0x6000000 +#define SMFSEG0R_NULL_POINT_IDX_C 0x4880 +#define SMFSEG0R_NULL_POINT_IDX_C_M 0x18000000 +#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4880 +#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x20000000 +#define SEG0R_EDCCA_LVL_C 0x4884 +#define SEG0R_EDCCA_LVL_C_M 0xFF +#define SEG0R_EDCCA_LVL_P_C 0x4884 +#define SEG0R_EDCCA_LVL_P_C_M 0xFF00 +#define SEG0R_OBSS_LVL_C 0x4884 +#define SEG0R_OBSS_LVL_C_M 0xFF0000 +#define SEG0R_PPDU_LVL_C 0x4884 +#define SEG0R_PPDU_LVL_C_M 0xFF000000 +#define SEG0R_PPDU_LVL_P_C 0x4888 +#define SEG0R_PPDU_LVL_P_C_M 0xFF +#define SEG0R_DCV_C 0x4888 +#define SEG0R_DCV_C_M 0x7F00 +#define SEG0R_PWLMT_C 0x4888 +#define SEG0R_PWLMT_C_M 0x3F8000 +#define SEG0R_WGTHD_C 0x4888 +#define SEG0R_WGTHD_C_M 0x1FC00000 +#define SEG0R_PATHSEL_C 0x4888 +#define SEG0R_PATHSEL_C_M 0x60000000 +#define SEG0R_DROP_EN_C 0x4888 +#define SEG0R_DROP_EN_C_M 0x80000000 +#define SEG0R_ADCPKPW_C 0x488C +#define SEG0R_ADCPKPW_C_M 0x3F +#define SEG0R_LTFTHD_C 0x488C +#define SEG0R_LTFTHD_C_M 0xFC0 +#define SEG0R_DWN_LVL_C 0x488C +#define SEG0R_DWN_LVL_C_M 0x1F000 +#define SEG0R_PWOFST_C 0x488C +#define SEG0R_PWOFST_C_M 0x3E0000 +#define SEG0R_DROP_NC_C 0x488C +#define SEG0R_DROP_NC_C_M 0x3C00000 +#define SEG0R_FORCE_EN_C 0x488C +#define SEG0R_FORCE_EN_C_M 0x4000000 +#define SEG0R_FORGETTING_C 0x488C +#define SEG0R_FORGETTING_C_M 0x8000000 +#define SEG0R_GCRST_C 0x488C +#define SEG0R_GCRST_C_M 0x10000000 +#define SEG0R_PWSLOT_C 0x488C +#define SEG0R_PWSLOT_C_M 0x20000000 +#define SEG0R_SND_EN_C 0x488C +#define SEG0R_SND_EN_C_M 0x40000000 +#define SEG0R_WGTSEL_EN_C 0x488C +#define SEG0R_WGTSEL_EN_C_M 0x80000000 +#define SEG0R_SDAGC_CHK_PIN_THD_C 0x4890 +#define SEG0R_SDAGC_CHK_PIN_THD_C_M 0x3F +#define SEG0R_ALPHA_STEP_C 0x4890 +#define SEG0R_ALPHA_STEP_C_M 0xC0 +#define SEG0R_CBW40_RSSI_SHIFT_C 0x4890 +#define SEG0R_CBW40_RSSI_SHIFT_C_M 0x300 +#define SEG0R_CBW80_RSSI_SHIFT_C 0x4890 +#define SEG0R_CBW80_RSSI_SHIFT_C_M 0xC00 +#define SEG0R_ALPHA_FILTER_EN_C 0x4890 +#define SEG0R_ALPHA_FILTER_EN_C_M 0x1000 +#define SEG0R_LTF_RSSI_CMP_EN_C 0x4890 +#define SEG0R_LTF_RSSI_CMP_EN_C_M 0x2000 +#define SEG0R_PD_RSSI_CMP_EN_C 0x4890 +#define SEG0R_PD_RSSI_CMP_EN_C_M 0x4000 +#define SEG0R_SDAGC_CHK_PIN_EN_C 0x4890 +#define SEG0R_SDAGC_CHK_PIN_EN_C_M 0x8000 +#define SEG0R_COMB_WGT_C 0x4894 +#define SEG0R_COMB_WGT_C_M 0xF +#define L_NOISE_VAR_PER_RX_R0_C 0x4958 +#define L_NOISE_VAR_PER_RX_R0_C_M 0x3FFFF +#define MANUAL_NOISE_RESCAL_FCTR_R0_C 0x4958 +#define MANUAL_NOISE_RESCAL_FCTR_R0_C_M 0x7FFC0000 +#define FD_ANT_WGT_EN_C 0x4958 +#define FD_ANT_WGT_EN_C_M 0x80000000 +#define L_NOISE_VAR_PER_RX_R1_C 0x495C +#define L_NOISE_VAR_PER_RX_R1_C_M 0x3FFFF +#define MANUAL_NOISE_RESCAL_FCTR_R1_C 0x495C +#define MANUAL_NOISE_RESCAL_FCTR_R1_C_M 0x7FFC0000 +#define FD_PW_NORM_EN_C 0x495C +#define FD_PW_NORM_EN_C_M 0x80000000 +#define NOISE_VAR_PER_RX_R0_C 0x4960 +#define NOISE_VAR_PER_RX_R0_C_M 0x3FFFF +#define NOISE_VAR_PER_RX_DB_THD_C 0x4960 +#define NOISE_VAR_PER_RX_DB_THD_C_M 0x3FFC0000 +#define RPL_CAL_EN_C 0x4960 +#define RPL_CAL_EN_C_M 0x40000000 +#define TB_RSSI_M_CAL_EN_C 0x4960 +#define TB_RSSI_M_CAL_EN_C_M 0x80000000 +#define NOISE_VAR_PER_RX_R1_C 0x4964 +#define NOISE_VAR_PER_RX_R1_C_M 0x3FFFF +#define PER_RX_DIFF_MAX_NOISE_PW_THD_C 0x4964 +#define PER_RX_DIFF_MAX_NOISE_PW_THD_C_M 0x3FFC0000 +#define ANT_WGT_MANUAL_EN_C 0x4964 +#define ANT_WGT_MANUAL_EN_C_M 0x40000000 +#define ANT_WGT_NORMALIZE_MODE_EN_C 0x4964 +#define ANT_WGT_NORMALIZE_MODE_EN_C_M 0x80000000 +#define FD_AMP_WGT_LEG_R0_C 0x4968 +#define FD_AMP_WGT_LEG_R0_C_M 0xFFFF +#define FD_AMP_WGT_LEG_R1_C 0x4968 +#define FD_AMP_WGT_LEG_R1_C_M 0xFFFF0000 +#define FD_AMP_WGT_NON_LEG_R0_C 0x496C +#define FD_AMP_WGT_NON_LEG_R0_C_M 0xFFFF +#define FD_AMP_WGT_NON_LEG_R1_C 0x496C +#define FD_AMP_WGT_NON_LEG_R1_C_M 0xFFFF0000 +#define L_SNR_ALL_COMB_C 0x4978 +#define L_SNR_ALL_COMB_C_M 0x3FF +#define L_SNR_PER_RX_R0_C 0x4978 +#define L_SNR_PER_RX_R0_C_M 0xFFC00 +#define L_SNR_PER_RX_R1_C 0x4978 +#define L_SNR_PER_RX_R1_C_M 0x3FF00000 +#define MANUAL_FD_AMP_WGT_EN_C 0x4978 +#define MANUAL_FD_AMP_WGT_EN_C_M 0x40000000 +#define MANUAL_SNR_EN_C 0x4978 +#define MANUAL_SNR_EN_C_M 0x80000000 +#define SNR_ALL_COMB_C 0x497C +#define SNR_ALL_COMB_C_M 0x3FF +#define SNR_PER_RX_STS_R0_S0_C 0x497C +#define SNR_PER_RX_STS_R0_S0_C_M 0xFFC00 +#define SNR_PER_RX_STS_R0_S1_C 0x497C +#define SNR_PER_RX_STS_R0_S1_C_M 0x3FF00000 +#define MANUAL_NOISE_RESCAL_EN_C 0x497C +#define MANUAL_NOISE_RESCAL_EN_C_M 0x40000000 +#define MANUAL_NOISE_VAR_EN_C 0x497C +#define MANUAL_NOISE_VAR_EN_C_M 0x80000000 +#define SNR_PER_RX_STS_R1_S0_C 0x4980 +#define SNR_PER_RX_STS_R1_S0_C_M 0x3FF +#define SNR_PER_RX_STS_R1_S1_C 0x4980 +#define SNR_PER_RX_STS_R1_S1_C_M 0xFFC00 +#define SNR_PER_RX_SUB_R0_S0_C 0x4980 +#define SNR_PER_RX_SUB_R0_S0_C_M 0x3FF00000 +#define NOISE_RESCAL_EN_C 0x4980 +#define NOISE_RESCAL_EN_C_M 0x40000000 +#define SNR_PER_RX_SUB_R0_S1_C 0x4984 +#define SNR_PER_RX_SUB_R0_S1_C_M 0x3FF +#define SNR_PER_RX_SUB_R0_S2_C 0x4984 +#define SNR_PER_RX_SUB_R0_S2_C_M 0xFFC00 +#define SNR_PER_RX_SUB_R0_S3_C 0x4984 +#define SNR_PER_RX_SUB_R0_S3_C_M 0x3FF00000 +#define SNR_PER_RX_SUB_R1_S0_C 0x4988 +#define SNR_PER_RX_SUB_R1_S0_C_M 0x3FF +#define SNR_PER_RX_SUB_R1_S1_C 0x4988 +#define SNR_PER_RX_SUB_R1_S1_C_M 0xFFC00 +#define SNR_PER_RX_SUB_R1_S2_C 0x4988 +#define SNR_PER_RX_SUB_R1_S2_C_M 0x3FF00000 +#define SNR_PER_RX_SUB_R1_S3_C 0x498C +#define SNR_PER_RX_SUB_R1_S3_C_M 0x3FF +#define SNR_PER_STS_S0_C 0x498C +#define SNR_PER_STS_S0_C_M 0xFFC00 +#define SNR_PER_STS_S1_C 0x498C +#define SNR_PER_STS_S1_C_M 0x3FF00000 +#define SNR_PER_SUB_S0_C 0x4990 +#define SNR_PER_SUB_S0_C_M 0x3FF +#define SNR_PER_SUB_S1_C 0x4990 +#define SNR_PER_SUB_S1_C_M 0xFFC00 +#define SNR_PER_SUB_S2_C 0x4990 +#define SNR_PER_SUB_S2_C_M 0x3FF00000 +#define SNR_PER_SUB_S3_C 0x4994 +#define SNR_PER_SUB_S3_C_M 0x3FF +#define RX_DB_SAME_THD_C 0x4994 +#define RX_DB_SAME_THD_C_M 0x7FC00 +#define ANT_WGT_MANUAL_RX0_C 0x4994 +#define ANT_WGT_MANUAL_RX0_C_M 0xFF80000 +#define ANT_WGT_MANUAL_RX1_C 0x4998 +#define ANT_WGT_MANUAL_RX1_C_M 0x1FF +#define FORBT_FD_ANT_WGT_OFF_C 0x4998 +#define FORBT_FD_ANT_WGT_OFF_C_M 0x3FE00 +#define FORBT_FD_ANT_WGT_ON_C 0x4998 +#define FORBT_FD_ANT_WGT_ON_C_M 0x7FC0000 +#define DIFF_SAME_THD_C 0x499C +#define DIFF_SAME_THD_C_M 0x7F +#define RX_DB_DISCONNECT_THD_0_C 0x499C +#define RX_DB_DISCONNECT_THD_0_C_M 0x3F80 +#define RX_DB_DISCONNECT_THD_1_C 0x499C +#define RX_DB_DISCONNECT_THD_1_C_M 0x1FC000 +#define RX_DB_DISCONNECT_THD_2_C 0x499C +#define RX_DB_DISCONNECT_THD_2_C_M 0xFE00000 +#define RX_DB_DISCONNECT_THD_3_C 0x49A0 +#define RX_DB_DISCONNECT_THD_3_C_M 0x7F +#define RX_DB_DISCONNECT_THD_4_C 0x49A0 +#define RX_DB_DISCONNECT_THD_4_C_M 0x3F80 +#define RX_DB_DISCONNECT_THD_5_C 0x49A0 +#define RX_DB_DISCONNECT_THD_5_C_M 0x1FC000 +#define RX_DB_DISCONNECT_THD_6_C 0x49A0 +#define RX_DB_DISCONNECT_THD_6_C_M 0xFE00000 +#define ANT_WGT_NSS2_LOW_BOUND_C 0x49A4 +#define ANT_WGT_NSS2_LOW_BOUND_C_M 0x7F +#define ANT_WGT_NSS2_LOW_BOUND_THD_C 0x49A4 +#define ANT_WGT_NSS2_LOW_BOUND_THD_C_M 0x3F80 +#define DISCONNECT_ANT_WGT_0_C 0x49A4 +#define DISCONNECT_ANT_WGT_0_C_M 0x1FC000 +#define DISCONNECT_ANT_WGT_1_C 0x49A4 +#define DISCONNECT_ANT_WGT_1_C_M 0xFE00000 +#define DISCONNECT_ANT_WGT_2_C 0x49A8 +#define DISCONNECT_ANT_WGT_2_C_M 0x7F +#define DISCONNECT_ANT_WGT_3_C 0x49A8 +#define DISCONNECT_ANT_WGT_3_C_M 0x3F80 +#define DISCONNECT_ANT_WGT_4_C 0x49A8 +#define DISCONNECT_ANT_WGT_4_C_M 0x1FC000 +#define DISCONNECT_ANT_WGT_5_C 0x49A8 +#define DISCONNECT_ANT_WGT_5_C_M 0xFE00000 +#define DISCONNECT_ANT_WGT_6_C 0x49AC +#define DISCONNECT_ANT_WGT_6_C_M 0x7F +#define DISCONNECT_ANT_WGT_7_C 0x49AC +#define DISCONNECT_ANT_WGT_7_C_M 0x3F80 +#define L_RPL_BIAS_COMP_C 0x49B0 +#define L_RPL_BIAS_COMP_C_M 0xFF +#define L_RPL_BIAS_COMP_BW20_C 0x49B0 +#define L_RPL_BIAS_COMP_BW20_C_M 0xFF00 +#define L_RPL_BIAS_COMP_BW40_C 0x49B0 +#define L_RPL_BIAS_COMP_BW40_C_M 0xFF0000 +#define L_RPL_BIAS_COMP_BW40_1_C 0x49B0 +#define L_RPL_BIAS_COMP_BW40_1_C_M 0xFF000000 +#define L_RPL_BIAS_COMP_BW40_2_C 0x49B4 +#define L_RPL_BIAS_COMP_BW40_2_C_M 0xFF +#define L_RPL_BIAS_COMP_BW80_C 0x49B4 +#define L_RPL_BIAS_COMP_BW80_C_M 0xFF00 +#define L_RPL_BIAS_COMP_BW80_1_C 0x49B4 +#define L_RPL_BIAS_COMP_BW80_1_C_M 0xFF0000 +#define L_RPL_BIAS_COMP_BW80_10_C 0x49B4 +#define L_RPL_BIAS_COMP_BW80_10_C_M 0xFF000000 +#define L_RPL_BIAS_COMP_BW80_2_C 0x49B8 +#define L_RPL_BIAS_COMP_BW80_2_C_M 0xFF +#define L_RPL_BIAS_COMP_BW80_3_C 0x49B8 +#define L_RPL_BIAS_COMP_BW80_3_C_M 0xFF00 +#define L_RPL_BIAS_COMP_BW80_4_C 0x49B8 +#define L_RPL_BIAS_COMP_BW80_4_C_M 0xFF0000 +#define L_RPL_BIAS_COMP_BW80_9_C 0x49B8 +#define L_RPL_BIAS_COMP_BW80_9_C_M 0xFF000000 +#define DBCC_C 0x49BC +#define DBCC_C_M 0x1 +#define DBCC_2P4G_BAND_SEL_C 0x49BC +#define DBCC_2P4G_BAND_SEL_C_M 0x2 +#define NONCON160_C 0x49BC +#define NONCON160_C_M 0x4 +#define FC0_INV_C 0x49C0 +#define FC0_INV_C_M 0x7F +#define FC1_INV_C 0x49C0 +#define FC1_INV_C_M 0x3F80 +#define ANT_RX_1RCCA_SEG0_C 0x49C0 +#define ANT_RX_1RCCA_SEG0_C_M 0x3C000 +#define ANT_RX_1RCCA_SEG1_C 0x49C0 +#define ANT_RX_1RCCA_SEG1_C_M 0x3C0000 +#define ANT_RX_BT_SEG0_C 0x49C0 +#define ANT_RX_BT_SEG0_C_M 0x3C00000 +#define ANT_RX_BT_SEG1_C 0x49C0 +#define ANT_RX_BT_SEG1_C_M 0x3C000000 +#define BW_C 0x49C0 +#define BW_C_M 0xC0000000 +#define ANT_RX_SEG0_C 0x49C4 +#define ANT_RX_SEG0_C_M 0xF +#define ANT_RX_SEG1_C 0x49C4 +#define ANT_RX_SEG1_C_M 0xF0 +#define PRICH_C 0x49C4 +#define PRICH_C_M 0xF00 +#define SMALL_BW_MODE_C 0x49C4 +#define SMALL_BW_MODE_C_M 0x3000 +#define BT_SHARE_C 0x49C4 +#define BT_SHARE_C_M 0x4000 +#define PROC0_PROCQ_MATRIX_00_IM_C 0x49C8 +#define PROC0_PROCQ_MATRIX_00_IM_C_M 0xFFFF +#define PROC0_PROCQ_MATRIX_00_RE_C 0x49C8 +#define PROC0_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000 +#define PROC0_PROCQ_MATRIX_01_IM_C 0x49CC +#define PROC0_PROCQ_MATRIX_01_IM_C_M 0xFFFF +#define PROC0_PROCQ_MATRIX_01_RE_C 0x49CC +#define PROC0_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000 +#define PROC0_PROCQ_MATRIX_10_IM_C 0x49D0 +#define PROC0_PROCQ_MATRIX_10_IM_C_M 0xFFFF +#define PROC0_PROCQ_MATRIX_10_RE_C 0x49D0 +#define PROC0_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000 +#define PROC0_PROCQ_MATRIX_11_IM_C 0x49D4 +#define PROC0_PROCQ_MATRIX_11_IM_C_M 0xFFFF +#define PROC0_PROCQ_MATRIX_11_RE_C 0x49D4 +#define PROC0_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000 +#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49D8 +#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1 +#define PRPC1_PROCQ_MATRIX_00_IM_C 0x49DC +#define PRPC1_PROCQ_MATRIX_00_IM_C_M 0xFFFF +#define PRPC1_PROCQ_MATRIX_00_RE_C 0x49DC +#define PRPC1_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000 +#define PRPC1_PROCQ_MATRIX_01_IM_C 0x49E0 +#define PRPC1_PROCQ_MATRIX_01_IM_C_M 0xFFFF +#define PRPC1_PROCQ_MATRIX_01_RE_C 0x49E0 +#define PRPC1_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000 +#define PRPC1_PROCQ_MATRIX_10_IM_C 0x49E4 +#define PRPC1_PROCQ_MATRIX_10_IM_C_M 0xFFFF +#define PRPC1_PROCQ_MATRIX_10_RE_C 0x49E4 +#define PRPC1_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000 +#define PRPC1_PROCQ_MATRIX_11_IM_C 0x49E8 +#define PRPC1_PROCQ_MATRIX_11_IM_C_M 0xFFFF +#define PRPC1_PROCQ_MATRIX_11_RE_C 0x49E8 +#define PRPC1_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000 +#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49EC +#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1 +#define PATH1_R_P_PEAK_IBADC_DBM_C 0x49F0 +#define PATH1_R_P_PEAK_IBADC_DBM_C_M 0x7F +#define PATH1_R_P_PEAK_WBADC_DBM_C 0x49F0 +#define PATH1_R_P_PEAK_WBADC_DBM_C_M 0x3F80 +#define PATH1_R_ACI_NRBW_TH_C 0x49F0 +#define PATH1_R_ACI_NRBW_TH_C_M 0xFC000 +#define PATH1_R_BACKOFF_BMODE_C 0x49F0 +#define PATH1_R_BACKOFF_BMODE_C_M 0x3F00000 +#define PATH1_R_BACKOFF_IBADC_C 0x49F0 +#define PATH1_R_BACKOFF_IBADC_C_M 0xFC000000 +#define PATH1_R_BACKOFF_LNA_C 0x49F4 +#define PATH1_R_BACKOFF_LNA_C_M 0x3F +#define PATH1_R_BACKOFF_TIA_C 0x49F4 +#define PATH1_R_BACKOFF_TIA_C_M 0xFC0 +#define PATH1_R_BACKOFF_WBADC_C 0x49F4 +#define PATH1_R_BACKOFF_WBADC_C_M 0x3F000 +#define PATH1_R_G_IBADC_IN_C 0x49F4 +#define PATH1_R_G_IBADC_IN_C_M 0xFC0000 +#define PATH1_R_A_GS_SAT_IDX_RX_C 0x49F4 +#define PATH1_R_A_GS_SAT_IDX_RX_C_M 0x1F000000 +#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C 0x49F4 +#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000 +#define FTM_EN_C 0x49F8 +#define FTM_EN_C_M 0x1 +#define PATH1_R_A_GS_UND_IDX_RX_C 0x49FC +#define PATH1_R_A_GS_UND_IDX_RX_C_M 0x1F +#define PATH1_R_G_GS_SAT_IDX_RX_C 0x49FC +#define PATH1_R_G_GS_SAT_IDX_RX_C_M 0x3E0 +#define PATH1_R_G_GS_UND_IDX_RX_C 0x49FC +#define PATH1_R_G_GS_UND_IDX_RX_C_M 0x7C00 +#define PATH1_R_DLY_DCCL_C 0x49FC +#define PATH1_R_DLY_DCCL_C_M 0x1F00000 +#define PATH1_R_DLY_DFE_C 0x49FC +#define PATH1_R_DLY_DFE_C_M 0x3E000000 +#define PATH1_R_G_MIXER_C 0x49FC +#define PATH1_R_G_MIXER_C_M 0xC0000000 +#define TB_RSSI_M_BIAS_COMP_C 0x4A00 +#define TB_RSSI_M_BIAS_COMP_C_M 0xFF +#define TB_RSSI_M_BIAS_COMP_BW20_C 0x4A00 +#define TB_RSSI_M_BIAS_COMP_BW20_C_M 0xFF00 +#define TB_RSSI_M_BIAS_COMP_BW40_C 0x4A00 +#define TB_RSSI_M_BIAS_COMP_BW40_C_M 0xFF0000 +#define TB_RSSI_M_BIAS_COMP_BW40_1_C 0x4A00 +#define TB_RSSI_M_BIAS_COMP_BW40_1_C_M 0xFF000000 +#define TB_RSSI_M_BIAS_COMP_BW40_2_C 0x4A04 +#define TB_RSSI_M_BIAS_COMP_BW40_2_C_M 0xFF +#define TB_RSSI_M_BIAS_COMP_BW80_C 0x4A04 +#define TB_RSSI_M_BIAS_COMP_BW80_C_M 0xFF00 +#define TB_RSSI_M_BIAS_COMP_BW80_1_C 0x4A04 +#define TB_RSSI_M_BIAS_COMP_BW80_1_C_M 0xFF0000 +#define TB_RSSI_M_BIAS_COMP_BW80_10_C 0x4A04 +#define TB_RSSI_M_BIAS_COMP_BW80_10_C_M 0xFF000000 +#define TB_RSSI_M_BIAS_COMP_BW80_2_C 0x4A08 +#define TB_RSSI_M_BIAS_COMP_BW80_2_C_M 0xFF +#define TB_RSSI_M_BIAS_COMP_BW80_3_C 0x4A08 +#define TB_RSSI_M_BIAS_COMP_BW80_3_C_M 0xFF00 +#define TB_RSSI_M_BIAS_COMP_BW80_4_C 0x4A08 +#define TB_RSSI_M_BIAS_COMP_BW80_4_C_M 0xFF0000 +#define TB_RSSI_M_BIAS_COMP_BW80_9_C 0x4A08 +#define TB_RSSI_M_BIAS_COMP_BW80_9_C_M 0xFF000000 +#define TIME2EN_INTP_C 0x4A18 +#define TIME2EN_INTP_C_M 0xFF +#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C 0x4A24 +#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C_M 0x3FF +#define LSIGMRLSIG_NOISE_EST_ORG_THR_C 0x4A24 +#define LSIGMRLSIG_NOISE_EST_ORG_THR_C_M 0xFFC00 +#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C 0x4A24 +#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C_M 0x100000 +#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C 0x4A24 +#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C_M 0x200000 +#define PDP_TAU_FIX_FOR_LOWSNR_C 0x4A48 +#define PDP_TAU_FIX_FOR_LOWSNR_C_M 0x7 +#define LPBW_SEL_D1_HEER_C 0x4A4C +#define LPBW_SEL_D1_HEER_C_M 0x1F +#define LPBW_SEL_D2_HEER_C 0x4A4C +#define LPBW_SEL_D2_HEER_C_M 0x3E0 +#define LPBW_SEL_P1_HEER_C 0x4A4C +#define LPBW_SEL_P1_HEER_C_M 0x7C00 +#define LPBW_SEL_P2_HEER_C 0x4A4C +#define LPBW_SEL_P2_HEER_C_M 0xF8000 +#define CCK_ABANDON_TH_11M_1R_DB_C 0x4A50 +#define CCK_ABANDON_TH_11M_1R_DB_C_M 0x1F +#define CCK_ABANDON_TH_11M_2R_DB_C 0x4A50 +#define CCK_ABANDON_TH_11M_2R_DB_C_M 0x3E0 +#define CCK_ABANDON_TH_11M_3R_DB_C 0x4A50 +#define CCK_ABANDON_TH_11M_3R_DB_C_M 0x7C00 +#define CCK_ABANDON_TH_11M_4R_DB_C 0x4A50 +#define CCK_ABANDON_TH_11M_4R_DB_C_M 0xF8000 +#define CCK_ABANDON_TH_5M_1R_DB_C 0x4A50 +#define CCK_ABANDON_TH_5M_1R_DB_C_M 0x1F00000 +#define CCK_ABANDON_TH_5M_2R_DB_C 0x4A50 +#define CCK_ABANDON_TH_5M_2R_DB_C_M 0x3E000000 +#define EVM_DATA_OPT_C 0x4A50 +#define EVM_DATA_OPT_C_M 0xC0000000 +#define CCK_ABANDON_TH_5M_3R_DB_C 0x4A54 +#define CCK_ABANDON_TH_5M_3R_DB_C_M 0x1F +#define CCK_ABANDON_TH_5M_4R_DB_C 0x4A54 +#define CCK_ABANDON_TH_5M_4R_DB_C_M 0x3E0 +#define EVM_SIG_OPT_C 0x4A54 +#define EVM_SIG_OPT_C_M 0xC00 +#define CCK_ABANDON_EN_C 0x4A54 +#define CCK_ABANDON_EN_C_M 0x1000 +#define PATH1_R_DLY_PRIM_C 0x4A5C +#define PATH1_R_DLY_PRIM_C_M 0x1F +#define PATH1_R_DLY_SYNC_C 0x4A5C +#define PATH1_R_DLY_SYNC_C_M 0x3E0 +#define PATH1_R_RXIDX_INIT_C 0x4A5C +#define PATH1_R_RXIDX_INIT_C_M 0x7C00 +#define PATH1_R_A_GS_SAT_IDX_H_C 0x4A5C +#define PATH1_R_A_GS_SAT_IDX_H_C_M 0x78000 +#define PATH1_R_A_GS_SAT_IDX_L_C 0x4A5C +#define PATH1_R_A_GS_SAT_IDX_L_C_M 0x780000 +#define PATH1_R_A_GS_SAT_IDX_PP1_C 0x4A5C +#define PATH1_R_A_GS_SAT_IDX_PP1_C_M 0x7800000 +#define PATH1_R_A_GS_SAT_IDX_PP2_C 0x4A5C +#define PATH1_R_A_GS_SAT_IDX_PP2_C_M 0x78000000 +#define PATH1_R_1RCCA_PRE_PD_MODE_C 0x4A5C +#define PATH1_R_1RCCA_PRE_PD_MODE_C_M 0x80000000 +#define PATH1_R_A_GS_SAT_TH_H_C 0x4A60 +#define PATH1_R_A_GS_SAT_TH_H_C_M 0xF +#define PATH1_R_A_GS_SAT_TH_L_C 0x4A60 +#define PATH1_R_A_GS_SAT_TH_L_C_M 0xF0 +#define PATH1_R_A_GS_UND_IDX_C 0x4A60 +#define PATH1_R_A_GS_UND_IDX_C_M 0xF00 +#define PATH1_R_A_GS_UND_IDX_PP1_C 0x4A60 +#define PATH1_R_A_GS_UND_IDX_PP1_C_M 0xF000 +#define PATH1_R_A_GS_UND_IDX_PP2_C 0x4A60 +#define PATH1_R_A_GS_UND_IDX_PP2_C_M 0xF0000 +#define PATH1_R_A_GS_UND_TH_H_C 0x4A60 +#define PATH1_R_A_GS_UND_TH_H_C_M 0xF00000 +#define PATH1_R_A_GS_UND_TH_L_C 0x4A60 +#define PATH1_R_A_GS_UND_TH_L_C_M 0xF000000 +#define PATH1_R_GC1_TIME_C 0x4A60 +#define PATH1_R_GC1_TIME_C_M 0xF0000000 +#define PATH1_R_GC1_TIME_NLGC_C 0x4A64 +#define PATH1_R_GC1_TIME_NLGC_C_M 0xF +#define PATH1_R_GC2_TIME_C 0x4A64 +#define PATH1_R_GC2_TIME_C_M 0xF0 +#define PATH1_R_GC2_TIME_NLGC_C 0x4A64 +#define PATH1_R_GC2_TIME_NLGC_C_M 0xF00 +#define PATH1_R_GC3_TIME_C 0x4A64 +#define PATH1_R_GC3_TIME_C_M 0xF000 +#define PATH1_R_GC4_TIME_C 0x4A64 +#define PATH1_R_GC4_TIME_C_M 0xF0000 +#define PATH1_R_GC5_TIME_C 0x4A64 +#define PATH1_R_GC5_TIME_C_M 0xF00000 +#define PATH1_R_GC_TIME_LESS_80M_C 0x4A64 +#define PATH1_R_GC_TIME_LESS_80M_C_M 0xF000000 +#define PATH1_R_GC_TIME_LESS_NLINEAR_C 0x4A64 +#define PATH1_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000 +#define PATH1_R_G_GS_SAT_IDX_H_C 0x4A68 +#define PATH1_R_G_GS_SAT_IDX_H_C_M 0xF +#define PATH1_R_G_GS_SAT_IDX_L_C 0x4A68 +#define PATH1_R_G_GS_SAT_IDX_L_C_M 0xF0 +#define PATH1_R_G_GS_SAT_IDX_PP1_C 0x4A68 +#define PATH1_R_G_GS_SAT_IDX_PP1_C_M 0xF00 +#define PATH1_R_G_GS_SAT_IDX_PP2_C 0x4A68 +#define PATH1_R_G_GS_SAT_IDX_PP2_C_M 0xF000 +#define PATH1_R_G_GS_SAT_TH_H_C 0x4A68 +#define PATH1_R_G_GS_SAT_TH_H_C_M 0xF0000 +#define PATH1_R_G_GS_SAT_TH_L_C 0x4A68 +#define PATH1_R_G_GS_SAT_TH_L_C_M 0xF00000 +#define PATH1_R_G_GS_UND_IDX_C 0x4A68 +#define PATH1_R_G_GS_UND_IDX_C_M 0xF000000 +#define PATH1_R_G_GS_UND_IDX_PP1_C 0x4A68 +#define PATH1_R_G_GS_UND_IDX_PP1_C_M 0xF0000000 +#define PATH1_R_G_GS_UND_IDX_PP2_C 0x4A6C +#define PATH1_R_G_GS_UND_IDX_PP2_C_M 0xF +#define PATH1_R_G_GS_UND_TH_H_C 0x4A6C +#define PATH1_R_G_GS_UND_TH_H_C_M 0xF0 +#define PATH1_R_G_GS_UND_TH_L_C 0x4A6C +#define PATH1_R_G_GS_UND_TH_L_C_M 0xF00 +#define PATH1_R_ACI_NRBW_RATIO_C 0x4A6C +#define PATH1_R_ACI_NRBW_RATIO_C_M 0xF000 +#define PATH1_R_AGC_RESTART_TH_IB_C 0x4A6C +#define PATH1_R_AGC_RESTART_TH_IB_C_M 0xF0000 +#define PATH1_R_AGC_RESTART_TH_WB_C 0x4A6C +#define PATH1_R_AGC_RESTART_TH_WB_C_M 0xF00000 +#define PATH1_R_DCCL_ALPHA_80_C 0x4A6C +#define PATH1_R_DCCL_ALPHA_80_C_M 0xF000000 +#define PATH1_R_DCCL_ALPHA_N80_C 0x4A6C +#define PATH1_R_DCCL_ALPHA_N80_C_M 0xF0000000 +#define PATH1_R_LGC_FREEZE_TH_H_C 0x4A70 +#define PATH1_R_LGC_FREEZE_TH_H_C_M 0xF +#define PATH1_R_LGC_FREEZE_TH_L_C 0x4A70 +#define PATH1_R_LGC_FREEZE_TH_L_C_M 0xF0 +#define PATH1_R_NLGC_FREEZE_TH_H_C 0x4A70 +#define PATH1_R_NLGC_FREEZE_TH_H_C_M 0xF00 +#define PATH1_R_NLGC_FREEZE_TH_L_C 0x4A70 +#define PATH1_R_NLGC_FREEZE_TH_L_C_M 0xF000 +#define PATH1_R_WB_GAIN_IDX_INIT_C 0x4A70 +#define PATH1_R_WB_GAIN_IDX_INIT_C_M 0xF0000 +#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C 0x4A70 +#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000 +#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C 0x4A70 +#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000 +#define PATH1_R_G_WBADC_IN_C 0x4A70 +#define PATH1_R_G_WBADC_IN_C_M 0xC0000000 +#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7 +#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38 +#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0 +#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00 +#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000 +#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000 +#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000 +#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000 +#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000 +#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C 0x4A74 +#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000 +#define PATH1_R_IBADC_PW_ALPHA_H_C 0x4A74 +#define PATH1_R_IBADC_PW_ALPHA_H_C_M 0xC0000000 +#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C 0x4A78 +#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7 +#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C 0x4A78 +#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38 +#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C 0x4A78 +#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0 +#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00 +#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000 +#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000 +#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000 +#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000 +#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000 +#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C 0x4A78 +#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000 +#define PATH1_R_IBADC_PW_ALPHA_L_C 0x4A78 +#define PATH1_R_IBADC_PW_ALPHA_L_C_M 0xC0000000 +#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7 +#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38 +#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0 +#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00 +#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000 +#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000 +#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000 +#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000 +#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C 0x4A7C +#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000 +#define PATH1_R_BT_LNA_IDX0_C 0x4A7C +#define PATH1_R_BT_LNA_IDX0_C_M 0x38000000 +#define PATH1_R_LINEAR_STEP_LIM_C 0x4A7C +#define PATH1_R_LINEAR_STEP_LIM_C_M 0xC0000000 +#define PATH1_R_BT_LNA_IDX1_C 0x4A80 +#define PATH1_R_BT_LNA_IDX1_C_M 0x7 +#define PATH1_R_BT_LNA_IDX2_C 0x4A80 +#define PATH1_R_BT_LNA_IDX2_C_M 0x38 +#define PATH1_R_BT_LNA_IDX3_C 0x4A80 +#define PATH1_R_BT_LNA_IDX3_C_M 0x1C0 +#define PATH1_R_ELNA_SEL_MARGIN_LGC_C 0x4A80 +#define PATH1_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00 +#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C 0x4A80 +#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000 +#define PATH1_R_IBADC_CLIP_RATIO_C 0x4A80 +#define PATH1_R_IBADC_CLIP_RATIO_C_M 0x38000 +#define PATH1_R_IBADC_CLIP_TH_C 0x4A80 +#define PATH1_R_IBADC_CLIP_TH_C_M 0x1C0000 +#define PATH1_R_LGC_STEP_LIM_C 0x4A80 +#define PATH1_R_LGC_STEP_LIM_C_M 0xE00000 +#define PATH1_R_LNA_IDX_INIT_C 0x4A80 +#define PATH1_R_LNA_IDX_INIT_C_M 0x7000000 +#define PATH1_R_LNA_SEL_MARGIN_LGC_C 0x4A80 +#define PATH1_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000 +#define PATH1_R_LINEAR_STEP_MIN_C 0x4A80 +#define PATH1_R_LINEAR_STEP_MIN_C_M 0xC0000000 +#define SEG0R_DFS_MSKNPW_TH_C 0x4A84 +#define SEG0R_DFS_MSKNPW_TH_C_M 0x7F +#define SEG0R_DFS_MSKNPW_EN_C 0x4A84 +#define SEG0R_DFS_MSKNPW_EN_C_M 0x80 +#define PATH0_R_IB_PW_DIFF_OFST_BW20_C 0x4A8C +#define PATH0_R_IB_PW_DIFF_OFST_BW20_C_M 0xF +#define PATH0_R_IB_PW_DIFF_OFST_BW40_C 0x4A8C +#define PATH0_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0 +#define PATH0_R_IB_PW_DIFF_OFST_BW80_C 0x4A8C +#define PATH0_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00 +#define PATH1_R_IB_PW_DIFF_OFST_BW20_C 0x4A90 +#define PATH1_R_IB_PW_DIFF_OFST_BW20_C_M 0xF +#define PATH1_R_IB_PW_DIFF_OFST_BW40_C 0x4A90 +#define PATH1_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0 +#define PATH1_R_IB_PW_DIFF_OFST_BW80_C 0x4A90 +#define PATH1_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00 +#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C 0x4A94 +#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C_M 0x1 +#define PATH1_R_LNA_SEL_MARGIN_NLGC_C 0x4A9C +#define PATH1_R_LNA_SEL_MARGIN_NLGC_C_M 0x7 +#define PATH1_R_RXSEL_MARGIN_LGC_C 0x4A9C +#define PATH1_R_RXSEL_MARGIN_LGC_C_M 0x38 +#define PATH1_R_RXSEL_MARGIN_NLGC_C 0x4A9C +#define PATH1_R_RXSEL_MARGIN_NLGC_C_M 0x1C0 +#define PATH1_R_TIA_SEL_MARGIN_LGC_C 0x4A9C +#define PATH1_R_TIA_SEL_MARGIN_LGC_C_M 0xE00 +#define PATH1_R_TIA_SEL_MARGIN_NLGC_C 0x4A9C +#define PATH1_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000 +#define PATH1_R_WBADC_CLIP_RATIO_C 0x4A9C +#define PATH1_R_WBADC_CLIP_RATIO_C_M 0x38000 +#define PATH1_R_WBADC_CLIP_TH_C 0x4A9C +#define PATH1_R_WBADC_CLIP_TH_C_M 0x1C0000 +#define PATH1_R_NLGC_STEP_LIM_C 0x4A9C +#define PATH1_R_NLGC_STEP_LIM_C_M 0x600000 +#define PATH1_R_NLGC_STEP_MIN_C 0x4A9C +#define PATH1_R_NLGC_STEP_MIN_C_M 0x1800000 +#define PATH1_R_POST_PD_STEP_LIM_C 0x4A9C +#define PATH1_R_POST_PD_STEP_LIM_C_M 0x6000000 +#define PATH1_R_POST_PD_STEP_MIN_C 0x4A9C +#define PATH1_R_POST_PD_STEP_MIN_C_M 0x18000000 +#define PATH1_R_PRE_PD_STEP_LIM_C 0x4A9C +#define PATH1_R_PRE_PD_STEP_LIM_C_M 0x60000000 +#define PATH1_R_AGC_EN_C 0x4A9C +#define PATH1_R_AGC_EN_C_M 0x80000000 +#define PATH1_R_PRE_PD_STEP_MIN_C 0x4AA0 +#define PATH1_R_PRE_PD_STEP_MIN_C_M 0x3 +#define PATH1_R_WBADC_PW_ALPHA_H_C 0x4AA0 +#define PATH1_R_WBADC_PW_ALPHA_H_C_M 0xC +#define PATH1_R_WBADC_PW_ALPHA_L_C 0x4AA0 +#define PATH1_R_WBADC_PW_ALPHA_L_C_M 0x30 +#define PATH1_R_A_WB_GIDX_00_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_00_ELNA_C_M 0x40 +#define PATH1_R_A_WB_GIDX_01_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_01_ELNA_C_M 0x80 +#define PATH1_R_A_WB_GIDX_02_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_02_ELNA_C_M 0x100 +#define PATH1_R_A_WB_GIDX_03_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_03_ELNA_C_M 0x200 +#define PATH1_R_A_WB_GIDX_04_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_04_ELNA_C_M 0x400 +#define PATH1_R_A_WB_GIDX_05_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_05_ELNA_C_M 0x800 +#define PATH1_R_A_WB_GIDX_06_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_06_ELNA_C_M 0x1000 +#define PATH1_R_A_WB_GIDX_07_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_07_ELNA_C_M 0x2000 +#define PATH1_R_A_WB_GIDX_08_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_08_ELNA_C_M 0x4000 +#define PATH1_R_A_WB_GIDX_09_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_09_ELNA_C_M 0x8000 +#define PATH1_R_A_WB_GIDX_10_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_10_ELNA_C_M 0x10000 +#define PATH1_R_A_WB_GIDX_11_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_11_ELNA_C_M 0x20000 +#define PATH1_R_A_WB_GIDX_12_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_12_ELNA_C_M 0x40000 +#define PATH1_R_A_WB_GIDX_13_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_13_ELNA_C_M 0x80000 +#define PATH1_R_A_WB_GIDX_14_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_14_ELNA_C_M 0x100000 +#define PATH1_R_A_WB_GIDX_15_ELNA_C 0x4AA0 +#define PATH1_R_A_WB_GIDX_15_ELNA_C_M 0x200000 +#define PATH1_R_GC_TIME_1T_MORE_C 0x4AA0 +#define PATH1_R_GC_TIME_1T_MORE_C_M 0x400000 +#define PATH1_R_G_WB_GIDX_00_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_00_ELNA_C_M 0x800000 +#define PATH1_R_G_WB_GIDX_01_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_01_ELNA_C_M 0x1000000 +#define PATH1_R_G_WB_GIDX_02_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_02_ELNA_C_M 0x2000000 +#define PATH1_R_G_WB_GIDX_03_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_03_ELNA_C_M 0x4000000 +#define PATH1_R_G_WB_GIDX_04_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_04_ELNA_C_M 0x8000000 +#define PATH1_R_G_WB_GIDX_05_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_05_ELNA_C_M 0x10000000 +#define PATH1_R_G_WB_GIDX_06_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_06_ELNA_C_M 0x20000000 +#define PATH1_R_G_WB_GIDX_07_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_07_ELNA_C_M 0x40000000 +#define PATH1_R_G_WB_GIDX_08_ELNA_C 0x4AA0 +#define PATH1_R_G_WB_GIDX_08_ELNA_C_M 0x80000000 +#define PATH1_R_G_WB_GIDX_09_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_09_ELNA_C_M 0x1 +#define PATH1_R_G_WB_GIDX_10_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_10_ELNA_C_M 0x2 +#define PATH1_R_G_WB_GIDX_11_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_11_ELNA_C_M 0x4 +#define PATH1_R_G_WB_GIDX_12_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_12_ELNA_C_M 0x8 +#define PATH1_R_G_WB_GIDX_13_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_13_ELNA_C_M 0x10 +#define PATH1_R_G_WB_GIDX_14_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_14_ELNA_C_M 0x20 +#define PATH1_R_G_WB_GIDX_15_ELNA_C 0x4AA4 +#define PATH1_R_G_WB_GIDX_15_ELNA_C_M 0x40 +#define PATH1_R_SE1_TIME_C 0x4AA4 +#define PATH1_R_SE1_TIME_C_M 0x80 +#define PATH1_R_SE1_TIME_NLGC_C 0x4AA4 +#define PATH1_R_SE1_TIME_NLGC_C_M 0x100 +#define PATH1_R_SE2_TIME_C 0x4AA4 +#define PATH1_R_SE2_TIME_C_M 0x200 +#define PATH1_R_SE2_TIME_NLGC_C 0x4AA4 +#define PATH1_R_SE2_TIME_NLGC_C_M 0x400 +#define PATH1_R_SE3_TIME_C 0x4AA4 +#define PATH1_R_SE3_TIME_C_M 0x800 +#define PATH1_R_SE4_TIME_C 0x4AA4 +#define PATH1_R_SE4_TIME_C_M 0x1000 +#define PATH1_R_SE5_TIME_C 0x4AA4 +#define PATH1_R_SE5_TIME_C_M 0x2000 +#define PATH1_R_SE_TIME_DONE_C 0x4AA4 +#define PATH1_R_SE_TIME_DONE_C_M 0x4000 +#define PATH1_R_SE_TIME_LINEAR_EXT_C 0x4AA4 +#define PATH1_R_SE_TIME_LINEAR_EXT_C_M 0x8000 +#define PATH1_R_ACI_NRBW_EN_C 0x4AA4 +#define PATH1_R_ACI_NRBW_EN_C_M 0x10000 +#define PATH1_R_BAND_SEL_C 0x4AA4 +#define PATH1_R_BAND_SEL_C_M 0x20000 +#define PATH1_R_BT_RX_MODE_EN_C 0x4AA4 +#define PATH1_R_BT_RX_MODE_EN_C_M 0x40000 +#define PATH1_R_BT_SHARE_C 0x4AA4 +#define PATH1_R_BT_SHARE_C_M 0x80000 +#define PATH1_R_BT_TX_FORCE_NRBW_C 0x4AA4 +#define PATH1_R_BT_TX_FORCE_NRBW_C_M 0x100000 +#define PATH1_R_BT_TX_MODE_EN_C 0x4AA4 +#define PATH1_R_BT_TX_MODE_EN_C_M 0x200000 +#define PATH1_R_BTG_PATH_C 0x4AA4 +#define PATH1_R_BTG_PATH_C_M 0x400000 +#define PATH1_R_CCK_FORCE_NRBW_C 0x4AA4 +#define PATH1_R_CCK_FORCE_NRBW_C_M 0x800000 +#define PATH1_R_DCCL_EN_C 0x4AA4 +#define PATH1_R_DCCL_EN_C_M 0x1000000 +#define PATH1_R_ELNA_BYPASS_EN_C 0x4AA4 +#define PATH1_R_ELNA_BYPASS_EN_C_M 0x2000000 +#define PATH1_R_ELNA_EN_C 0x4AA4 +#define PATH1_R_ELNA_EN_C_M 0x4000000 +#define PATH1_R_ELNA_IDX_INIT_C 0x4AA4 +#define PATH1_R_ELNA_IDX_INIT_C_M 0x8000000 +#define PATH1_R_FORCE_BT_COEX_C 0x4AA4 +#define PATH1_R_FORCE_BT_COEX_C_M 0x10000000 +#define PATH1_R_FORCE_NRBW_C 0x4AA4 +#define PATH1_R_FORCE_NRBW_C_M 0x20000000 +#define PATH1_R_I_ONLY_C 0x4AA4 +#define PATH1_R_I_ONLY_C_M 0x40000000 +#define PATH1_R_LGC_DAGC_EN_C 0x4AA4 +#define PATH1_R_LGC_DAGC_EN_C_M 0x80000000 +#define PATH1_R_LINEAR_AGC_EN_C 0x4AA8 +#define PATH1_R_LINEAR_AGC_EN_C_M 0x1 +#define PATH1_R_LINEAR_MARGIN_MODE_C 0x4AA8 +#define PATH1_R_LINEAR_MARGIN_MODE_C_M 0x2 +#define PATH1_R_NLGC_AGC_EN_C 0x4AA8 +#define PATH1_R_NLGC_AGC_EN_C_M 0x4 +#define PATH1_R_NLGC_DAGC_EN_C 0x4AA8 +#define PATH1_R_NLGC_DAGC_EN_C_M 0x8 +#define PATH1_R_NRBW_DEF_C 0x4AA8 +#define PATH1_R_NRBW_DEF_C_M 0x10 +#define PATH1_R_POST_PD_AGC_EN_C 0x4AA8 +#define PATH1_R_POST_PD_AGC_EN_C_M 0x20 +#define PATH1_R_PRE_PD_AGC_EN_C 0x4AA8 +#define PATH1_R_PRE_PD_AGC_EN_C_M 0x40 +#define PATH1_R_PURE_POST_PD_MODE_C 0x4AA8 +#define PATH1_R_PURE_POST_PD_MODE_C_M 0x80 +#define PATH1_R_SYNC_PRE_PD_STEP_C 0x4AA8 +#define PATH1_R_SYNC_PRE_PD_STEP_C_M 0x100 +#define PATH1_R_TIA_IDX_INIT_C 0x4AA8 +#define PATH1_R_TIA_IDX_INIT_C_M 0x200 +#define PATH1_R_TIA_SHRINK_DEF_C 0x4AA8 +#define PATH1_R_TIA_SHRINK_DEF_C_M 0x400 +#define PATH1_R_TIA_SHRINK_EN_C 0x4AA8 +#define PATH1_R_TIA_SHRINK_EN_C_M 0x800 +#define PATH1_R_TIA_SHRINK_INIT_C 0x4AA8 +#define PATH1_R_TIA_SHRINK_INIT_C_M 0x1000 +#define LDPC_MCS0_MAX_ITER_C 0x4AAC +#define LDPC_MCS0_MAX_ITER_C_M 0xF +#define LDPC_MCS10_MAX_ITER_C 0x4AAC +#define LDPC_MCS10_MAX_ITER_C_M 0xF0 +#define LDPC_MCS11_MAX_ITER_C 0x4AAC +#define LDPC_MCS11_MAX_ITER_C_M 0xF00 +#define LDPC_MCS1_MAX_ITER_C 0x4AAC +#define LDPC_MCS1_MAX_ITER_C_M 0xF000 +#define LDPC_MCS2_MAX_ITER_C 0x4AAC +#define LDPC_MCS2_MAX_ITER_C_M 0xF0000 +#define LDPC_MCS3_MAX_ITER_C 0x4AAC +#define LDPC_MCS3_MAX_ITER_C_M 0xF00000 +#define LDPC_MCS4_MAX_ITER_C 0x4AAC +#define LDPC_MCS4_MAX_ITER_C_M 0xF000000 +#define LDPC_MCS5_MAX_ITER_C 0x4AAC +#define LDPC_MCS5_MAX_ITER_C_M 0xF0000000 +#define LDPC_MCS6_MAX_ITER_C 0x4AB0 +#define LDPC_MCS6_MAX_ITER_C_M 0xF +#define LDPC_MCS7_MAX_ITER_C 0x4AB0 +#define LDPC_MCS7_MAX_ITER_C_M 0xF0 +#define LDPC_MCS8_MAX_ITER_C 0x4AB0 +#define LDPC_MCS8_MAX_ITER_C_M 0xF00 +#define LDPC_MCS9_MAX_ITER_C 0x4AB0 +#define LDPC_MCS9_MAX_ITER_C_M 0xF000 +#define CFO_COMP_PHASE_MODE_C 0x4AB4 +#define CFO_COMP_PHASE_MODE_C_M 0x1 +#define PROCR_POST_RX_PROC_DLY_TIME_C 0x4ABC +#define PROCR_POST_RX_PROC_DLY_TIME_C_M 0x7F +#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C 0x4AC8 +#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C_M 0x1 +#define PATH0_R_AGC_RESERVED_1_C 0x4ACC +#define PATH0_R_AGC_RESERVED_1_C_M 0xFFFFFFFF +#define PATH0_R_AGC_RESERVED_2_C 0x4AD0 +#define PATH0_R_AGC_RESERVED_2_C_M 0xFFFFFFFF +#define PATH0_R_RXBY_WBADC_TH_C 0x4AD4 +#define PATH0_R_RXBY_WBADC_TH_C_M 0xF +#define PATH0_R_ALWAYS_RXBY_WBADC_C 0x4AD4 +#define PATH0_R_ALWAYS_RXBY_WBADC_C_M 0x10 +#define PATH0_R_BT_RXBY_WBADC_C 0x4AD4 +#define PATH0_R_BT_RXBY_WBADC_C_M 0x20 +#define PATH0_R_BT_TRACKING_OFF_EN_C 0x4AD4 +#define PATH0_R_BT_TRACKING_OFF_EN_C_M 0x40 +#define PATH1_R_AGC_RESERVED_1_C 0x4AD8 +#define PATH1_R_AGC_RESERVED_1_C_M 0xFFFFFFFF +#define PATH1_R_AGC_RESERVED_2_C 0x4ADC +#define PATH1_R_AGC_RESERVED_2_C_M 0xFFFFFFFF +#define PATH1_R_RXBY_WBADC_TH_C 0x4AE0 +#define PATH1_R_RXBY_WBADC_TH_C_M 0xF +#define PATH1_R_ALWAYS_RXBY_WBADC_C 0x4AE0 +#define PATH1_R_ALWAYS_RXBY_WBADC_C_M 0x10 +#define PATH1_R_BT_RXBY_WBADC_C 0x4AE0 +#define PATH1_R_BT_RXBY_WBADC_C_M 0x20 +#define PATH1_R_BT_TRACKING_OFF_EN_C 0x4AE0 +#define PATH1_R_BT_TRACKING_OFF_EN_C_M 0x40 +#define PATH0_R_BT_BACKOFF_BMODE_C 0x4AE4 +#define PATH0_R_BT_BACKOFF_BMODE_C_M 0x3F +#define PATH0_R_BT_BACKOFF_IBADC_C 0x4AE4 +#define PATH0_R_BT_BACKOFF_IBADC_C_M 0xFC0 +#define PATH0_R_BT_BACKOFF_LNA_C 0x4AE4 +#define PATH0_R_BT_BACKOFF_LNA_C_M 0x3F000 +#define PATH0_R_BT_BACKOFF_TIA_C 0x4AE4 +#define PATH0_R_BT_BACKOFF_TIA_C_M 0xFC0000 +#define PATH0_R_GC_TIME_LESS_160M_C 0x4AE4 +#define PATH0_R_GC_TIME_LESS_160M_C_M 0xF000000 +#define PATH0_R_DCCL_ALPHA_160_C 0x4AE4 +#define PATH0_R_DCCL_ALPHA_160_C_M 0xF0000000 +#define PATH0_R_WBADC_DLY_160M_C 0x4AE8 +#define PATH0_R_WBADC_DLY_160M_C_M 0xF +#define PATH0_R_WBADC_DLY_80M_C 0x4AE8 +#define PATH0_R_WBADC_DLY_80M_C_M 0xF0 +#define PATH0_R_WBADC_DLY_N80M_C 0x4AE8 +#define PATH0_R_WBADC_DLY_N80M_C_M 0xF00 +#define PATH0_R_RSSI_SOURCE_C 0x4AE8 +#define PATH0_R_RSSI_SOURCE_C_M 0x1000 +#define PATH1_R_BT_BACKOFF_BMODE_C 0x4AEC +#define PATH1_R_BT_BACKOFF_BMODE_C_M 0x3F +#define PATH1_R_BT_BACKOFF_IBADC_C 0x4AEC +#define PATH1_R_BT_BACKOFF_IBADC_C_M 0xFC0 +#define PATH1_R_BT_BACKOFF_LNA_C 0x4AEC +#define PATH1_R_BT_BACKOFF_LNA_C_M 0x3F000 +#define PATH1_R_BT_BACKOFF_TIA_C 0x4AEC +#define PATH1_R_BT_BACKOFF_TIA_C_M 0xFC0000 +#define PATH1_R_GC_TIME_LESS_160M_C 0x4AEC +#define PATH1_R_GC_TIME_LESS_160M_C_M 0xF000000 +#define PATH1_R_DCCL_ALPHA_160_C 0x4AEC +#define PATH1_R_DCCL_ALPHA_160_C_M 0xF0000000 +#define PATH1_R_WBADC_DLY_160M_C 0x4AF0 +#define PATH1_R_WBADC_DLY_160M_C_M 0xF +#define PATH1_R_WBADC_DLY_80M_C 0x4AF0 +#define PATH1_R_WBADC_DLY_80M_C_M 0xF0 +#define PATH1_R_WBADC_DLY_N80M_C 0x4AF0 +#define PATH1_R_WBADC_DLY_N80M_C_M 0xF00 +#define PATH1_R_RSSI_SOURCE_C 0x4AF0 +#define PATH1_R_RSSI_SOURCE_C_M 0x1000 +#define SEG0R_SNDCCA_RSV_C 0x4AFC +#define SEG0R_SNDCCA_RSV_C_M 0xFFFFFFFF +#define GD_PHASE_NON_LEG_R0S2_C 0x4B04 +#define GD_PHASE_NON_LEG_R0S2_C_M 0xFF +#define GD_PHASE_NON_LEG_R0S3_C 0x4B04 +#define GD_PHASE_NON_LEG_R0S3_C_M 0xFF00 +#define GD_PHASE_NON_LEG_R1S2_C 0x4B04 +#define GD_PHASE_NON_LEG_R1S2_C_M 0xFF0000 +#define GD_PHASE_NON_LEG_R1S3_C 0x4B04 +#define GD_PHASE_NON_LEG_R1S3_C_M 0xFF000000 +#define MANUAL_GD_PHASE_LEGACY_EN_C 0x4B08 +#define MANUAL_GD_PHASE_LEGACY_EN_C_M 0x1 +#define PATH0_R_TSSI_CURVE_P0_C 0x5600 +#define PATH0_R_TSSI_CURVE_P0_C_M 0x3F +#define PATH0_R_TSSI_CURVE_P1_C 0x5600 +#define PATH0_R_TSSI_CURVE_P1_C_M 0x3F00 +#define PATH0_R_TSSI_CURVE_P2_C 0x5600 +#define PATH0_R_TSSI_CURVE_P2_C_M 0x3F0000 +#define PATH0_R_TSSI_CURVE_P3_C 0x5600 +#define PATH0_R_TSSI_CURVE_P3_C_M 0x3F000000 +#define PATH0_R_TSSI_CURVE_P4_C 0x5604 +#define PATH0_R_TSSI_CURVE_P4_C_M 0x3F +#define PATH0_R_TSSI_CURVE_P5_C 0x5604 +#define PATH0_R_TSSI_CURVE_P5_C_M 0x3F00 +#define PATH0_R_TSSI_CURVE_P6_C 0x5604 +#define PATH0_R_TSSI_CURVE_P6_C_M 0x3F0000 +#define PATH0_R_TSSI_CURVE_EN_C 0x5604 +#define PATH0_R_TSSI_CURVE_EN_C_M 0x80000000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x5608 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x5608 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x5608 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x560C +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x560C +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x560C +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x5610 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x5610 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x5610 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x5614 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x5614 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x5614 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x5618 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x5618 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x5618 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x561C +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x561C +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x561C +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x5620 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x5620 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x5620 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x5620 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x5624 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x5624 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x5624 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x5624 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x5628 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x5628 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x5628 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x5628 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000 +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x562C +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x562C +#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00 +#define PATH0_R_TSSI_J_OFDM_G0_C 0x5630 +#define PATH0_R_TSSI_J_OFDM_G0_C_M 0x3FF +#define PATH0_R_TSSI_J_OFDM_G1_C 0x5630 +#define PATH0_R_TSSI_J_OFDM_G1_C_M 0xFFC00 +#define PATH0_R_TSSI_J_OFDM_G2_C 0x5630 +#define PATH0_R_TSSI_J_OFDM_G2_C_M 0x3FF00000 +#define PATH0_R_TSSI_J_OFDM_G3_C 0x5634 +#define PATH0_R_TSSI_J_OFDM_G3_C_M 0x3FF +#define PATH0_R_TSSI_J_OFDM_G4_C 0x5634 +#define PATH0_R_TSSI_J_OFDM_G4_C_M 0xFFC00 +#define PATH0_R_TSSI_J_OFDM_G5_C 0x5634 +#define PATH0_R_TSSI_J_OFDM_G5_C_M 0x3FF00000 +#define PATH0_R_TSSI_J_OFDM_G6_C 0x5638 +#define PATH0_R_TSSI_J_OFDM_G6_C_M 0x3FF +#define PATH0_R_TSSI_J_OFDM_G7_C 0x5638 +#define PATH0_R_TSSI_J_OFDM_G7_C_M 0xFFC00 +#define PATH0_R_TSSI_J_CCK_G0_C 0x563C +#define PATH0_R_TSSI_J_CCK_G0_C_M 0x3FF +#define PATH0_R_TSSI_J_CCK_G1_C 0x563C +#define PATH0_R_TSSI_J_CCK_G1_C_M 0xFFC00 +#define PATH0_R_TSSI_J_CCK_G2_C 0x563C +#define PATH0_R_TSSI_J_CCK_G2_C_M 0x3FF00000 +#define PATH0_R_TSSI_J_CCK_G3_C 0x5640 +#define PATH0_R_TSSI_J_CCK_G3_C_M 0x3FF +#define PATH0_R_TSSI_J_CCK_G4_C 0x5640 +#define PATH0_R_TSSI_J_CCK_G4_C_M 0xFFC00 +#define PATH0_R_TSSI_J_CCK_G5_C 0x5640 +#define PATH0_R_TSSI_J_CCK_G5_C_M 0x3FF00000 +#define PATH0_R_TSSI_J_CCK_G6_C 0x5644 +#define PATH0_R_TSSI_J_CCK_G6_C_M 0x3FF +#define PATH0_R_TSSI_J_CCK_G7_C 0x5644 +#define PATH0_R_TSSI_J_CCK_G7_C_M 0xFFC00 +#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C 0x5648 +#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF +#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C 0x5648 +#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10 +#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x5648 +#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0 +#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x5648 +#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400 +#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x5648 +#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800 +#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x5648 +#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000 +#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x5648 +#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000 +#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x5648 +#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000 +#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x564C +#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F +#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C 0x564C +#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20 +#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x564C +#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0 +#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x564C +#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100 +#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x564C +#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600 +#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x564C +#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800 +#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x564C +#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000 +#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x564C +#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000 +#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x564C +#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000 +#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x564C +#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x5650 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x5650 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x5650 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x5650 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x5650 +#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000 +#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C 0x5650 +#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000 +#define PATH0_R_TSSI_DCK_BY_CURVE_0_C 0x5654 +#define PATH0_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF +#define PATH0_R_TSSI_DCK_BY_CURVE_1_C 0x5654 +#define PATH0_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000 +#define PATH0_R_TSSI_DCK_BY_CURVE_2_C 0x5658 +#define PATH0_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF +#define PATH0_R_TSSI_DCK_BY_CURVE_3_C 0x5658 +#define PATH0_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000 +#define PATH0_R_TSSI_DCK_BY_CURVE_4_C 0x565C +#define PATH0_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF +#define PATH0_R_TSSI_DCK_BY_CURVE_5_C 0x565C +#define PATH0_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000 +#define PATH0_R_TSSI_DCK_BY_CURVE_6_C 0x5660 +#define PATH0_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF +#define PATH0_R_TSSI_DCK_BY_CURVE_7_C 0x5660 +#define PATH0_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x5664 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x5664 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x5664 +#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0 +#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C 0x5664 +#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000 +#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C 0x5664 +#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000 +#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x5664 +#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000 +#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x5664 +#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000 +#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x5668 +#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1 +#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x5668 +#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2 +#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x5668 +#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4 +#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x5668 +#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8 +#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x5668 +#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0 +#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x5668 +#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800 +#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x5668 +#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000 +#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x5668 +#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000 +#define PATH0_R_TSSI_TIMEOUT_TIME_C 0x566C +#define PATH0_R_TSSI_TIMEOUT_TIME_C_M 0xFFF +#define PATH0_R_TSSI_TIMEOUT_UNIT_C 0x566C +#define PATH0_R_TSSI_TIMEOUT_UNIT_C_M 0x3000 +#define PATH0_R_TXAGC_MAX_C 0x5800 +#define PATH0_R_TXAGC_MAX_C_M 0xFF +#define PATH0_R_TXAGC_MIN_C 0x5800 +#define PATH0_R_TXAGC_MIN_C_M 0xFF00 +#define PATH0_R_TXAGC_RF_MAX_C 0x5800 +#define PATH0_R_TXAGC_RF_MAX_C_M 0x3F0000 +#define PATH0_R_TXAGC_RF_MIN_C 0x5800 +#define PATH0_R_TXAGC_RF_MIN_C_M 0xFC00000 +#define PATH0_R_DPD_OFST_EN_C 0x5800 +#define PATH0_R_DPD_OFST_EN_C_M 0x10000000 +#define PATH0_R_TXAGCSWING_EN_C 0x5800 +#define PATH0_R_TXAGCSWING_EN_C_M 0x20000000 +#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C 0x5800 +#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000 +#define PATH0_R_DIS_CCK_SWING_TXAGC_C 0x5800 +#define PATH0_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000 +#define PATH0_R_TXAGC_OFDM_REF_DBM_C 0x5804 +#define PATH0_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF +#define PATH0_R_TXAGC_OFDM_REF_CW_C 0x5804 +#define PATH0_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00 +#define PATH0_R_TSSI_MAP_OFST_OFDM_C 0x5804 +#define PATH0_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000 +#define PATH0_R_DPD_OFST_C 0x5804 +#define PATH0_R_DPD_OFST_C_M 0xF8000000 +#define PATH0_R_TXAGC_CCK_REF_DBM_C 0x5808 +#define PATH0_R_TXAGC_CCK_REF_DBM_C_M 0x1FF +#define PATH0_R_TXAGC_CCK_REF_CW_C 0x5808 +#define PATH0_R_TXAGC_CCK_REF_CW_C_M 0x3FE00 +#define PATH0_R_TSSI_MAP_OFST_CCK_C 0x5808 +#define PATH0_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000 +#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C 0x580C +#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F +#define PATH0_R_TSSI_MAP_SLOPE_CCK_C 0x580C +#define PATH0_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00 +#define PATH0_R_TXPW_FORCE_RDY_C 0x580C +#define PATH0_R_TXPW_FORCE_RDY_C_M 0x8000 +#define PATH0_R_TSSI_ADC_DC_OFST_RE_C 0x580C +#define PATH0_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000 +#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x580C +#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000 +#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x580C +#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000 +#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C +#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000 +#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C +#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000 +#define PATH0_R_TXAGC_PSEUDO_CW_C 0x5810 +#define PATH0_R_TXAGC_PSEUDO_CW_C_M 0x1FF +#define PATH0_R_TXAGC_PSEUDO_CW_EN_C 0x5810 +#define PATH0_R_TXAGC_PSEUDO_CW_EN_C_M 0x200 +#define PATH0_R_TMETER_T0_C 0x5810 +#define PATH0_R_TMETER_T0_C_M 0xFC00 +#define PATH0_R_DIS_TSSI_F_C 0x5810 +#define PATH0_R_DIS_TSSI_F_C_M 0x10000 +#define PATH0_R_TMETER_TBL_RA_C 0x5810 +#define PATH0_R_TMETER_TBL_RA_C_M 0x7E0000 +#define PATH0_R_TMETER_TBL_RD_C 0x5810 +#define PATH0_R_TMETER_TBL_RD_C_M 0x800000 +#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C 0x5810 +#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000 +#define PATH0_R_TMETER_TBL_FORCE_WEN_C 0x5810 +#define PATH0_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000 +#define PATH0_R_TMETER_TBL_FORCE_REN_C 0x5810 +#define PATH0_R_TMETER_TBL_FORCE_REN_C_M 0x4000000 +#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x5810 +#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000 +#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C 0x5810 +#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000 +#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x5810 +#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000 +#define PATH0_R_TSSI_DBG_PORT_EN_C 0x5810 +#define PATH0_R_TSSI_DBG_PORT_EN_C_M 0x40000000 +#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x5810 +#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000 +#define PATH0_R_TSSI_RF_GAP_TBL_RA_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F +#define PATH0_R_TSSI_RF_GAP_EN_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_EN_C_M 0x40 +#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80 +#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100 +#define PATH0_R_TSSI_RF_GAP_TBL_RD_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_TBL_RD_C_M 0x200 +#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x5814 +#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400 +#define PATH0_R_TSSI_BYPASS_TSSI_C_C 0x5814 +#define PATH0_R_TSSI_BYPASS_TSSI_C_C_M 0x800 +#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x5814 +#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000 +#define PATH0_R_TSSI_DCK_AUTO_EN_C 0x5814 +#define PATH0_R_TSSI_DCK_AUTO_EN_C_M 0x2000 +#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x5814 +#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000 +#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C 0x5814 +#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000 +#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C 0x5814 +#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000 +#define PATH0_R_TSSI_ADC_AMPLIFY_C 0x5814 +#define PATH0_R_TSSI_ADC_AMPLIFY_C_M 0xC00000 +#define PATH0_R_TSSI_PW_TRK_USE_025DB_C 0x5814 +#define PATH0_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000 +#define PATH0_R_TSSI_DCK_SEL_C 0x5814 +#define PATH0_R_TSSI_DCK_SEL_C_M 0x18000000 +#define PATH0_R_TSSI_TXADC_PW_SV_EN_C 0x5814 +#define PATH0_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000 +#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000 +#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C 0x5814 +#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000 +#define PATH0_R_TXAGC_OFST_C 0x5818 +#define PATH0_R_TXAGC_OFST_C_M 0xFF +#define PATH0_R_HE_ER_STF_PW_OFST_C 0x5818 +#define PATH0_R_HE_ER_STF_PW_OFST_C_M 0x1FF00 +#define PATH0_R_HE_STF_PW_OFST_C 0x5818 +#define PATH0_R_HE_STF_PW_OFST_C_M 0x3FE0000 +#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C 0x5818 +#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000 +#define PATH0_R_TSSI_OFST_BY_RFC_C 0x5818 +#define PATH0_R_TSSI_OFST_BY_RFC_C_M 0x8000000 +#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C 0x5818 +#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000 +#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x5818 +#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000 +#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x5818 +#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000 +#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x5818 +#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000 +#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C 0x581C +#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF +#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C 0x581C +#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00 +#define PATH0_R_TSSI_SLOPE_CAL_EN_C 0x581C +#define PATH0_R_TSSI_SLOPE_CAL_EN_C_M 0x100000 +#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x581C +#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000 +#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x581C +#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000 +#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C 0x581C +#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000 +#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x581C +#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000 +#define PATH0_R_TSSI_SLOPE_A_C 0x5820 +#define PATH0_R_TSSI_SLOPE_A_C_M 0xFFF +#define PATH0_R_TSSI_PKT_AVG_NUM_C 0x5820 +#define PATH0_R_TSSI_PKT_AVG_NUM_C_M 0xF000 +#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C 0x5820 +#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000 +#define PATH0_R_TSSI_PW_TRK_SW_OFST_C 0x5820 +#define PATH0_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000 +#define PATH0_R_TSSI_ISEPA_C 0x5820 +#define PATH0_R_TSSI_ISEPA_C_M 0x40000000 +#define PATH0_R_TSSI_EN_C 0x5820 +#define PATH0_R_TSSI_EN_C_M 0x80000000 +#define PATH0_R_TSSI_A_OFDM_5M_C 0x5824 +#define PATH0_R_TSSI_A_OFDM_5M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_5M_C 0x5824 +#define PATH0_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_5M_C 0x5828 +#define PATH0_R_TSSI_K_OFDM_5M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_5M_C 0x5828 +#define PATH0_R_TSSI_DE_OFDM_5M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x5828 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_OFDM_10M_C 0x582C +#define PATH0_R_TSSI_A_OFDM_10M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_10M_C 0x582C +#define PATH0_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_10M_C 0x5830 +#define PATH0_R_TSSI_K_OFDM_10M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_10M_C 0x5830 +#define PATH0_R_TSSI_DE_OFDM_10M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x5830 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_OFDM_20M_C 0x5834 +#define PATH0_R_TSSI_A_OFDM_20M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_20M_C 0x5834 +#define PATH0_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_20M_C 0x5838 +#define PATH0_R_TSSI_K_OFDM_20M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_20M_C 0x5838 +#define PATH0_R_TSSI_DE_OFDM_20M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x5838 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_OFDM_40M_C 0x583C +#define PATH0_R_TSSI_A_OFDM_40M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_40M_C 0x583C +#define PATH0_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_40M_C 0x5840 +#define PATH0_R_TSSI_K_OFDM_40M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_40M_C 0x5840 +#define PATH0_R_TSSI_DE_OFDM_40M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x5840 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_OFDM_80M_C 0x5844 +#define PATH0_R_TSSI_A_OFDM_80M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_80M_C 0x5844 +#define PATH0_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_80M_C 0x5848 +#define PATH0_R_TSSI_K_OFDM_80M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_80M_C 0x5848 +#define PATH0_R_TSSI_DE_OFDM_80M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x5848 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_OFDM_80_80M_C 0x584C +#define PATH0_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF +#define PATH0_R_TSSI_B_OFDM_80_80M_C 0x584C +#define PATH0_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_OFDM_80_80M_C 0x5850 +#define PATH0_R_TSSI_K_OFDM_80_80M_C_M 0xFFF +#define PATH0_R_TSSI_DE_OFDM_80_80M_C 0x5850 +#define PATH0_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x5850 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_CCK_LONG_C 0x5854 +#define PATH0_R_TSSI_A_CCK_LONG_C_M 0x3FFFF +#define PATH0_R_TSSI_B_CCK_LONG_C 0x5854 +#define PATH0_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_CCK_LONG_C 0x5858 +#define PATH0_R_TSSI_K_CCK_LONG_C_M 0xFFF +#define PATH0_R_TSSI_DE_CCK_LONG_C 0x5858 +#define PATH0_R_TSSI_DE_CCK_LONG_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x5858 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000 +#define PATH0_R_TSSI_A_CCK_SHORT_C 0x585C +#define PATH0_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF +#define PATH0_R_TSSI_B_CCK_SHORT_C 0x585C +#define PATH0_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000 +#define PATH0_R_TSSI_K_CCK_SHORT_C 0x5860 +#define PATH0_R_TSSI_K_CCK_SHORT_C_M 0xFFF +#define PATH0_R_TSSI_DE_CCK_SHORT_C 0x5860 +#define PATH0_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x5860 +#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000 +#define PATH0_RSWING_NO_LIM_C 0x5860 +#define PATH0_RSWING_NO_LIM_C_M 0x80000000 +#define PATH0_R_TSSI_DELTA_CODE_MAX_C 0x5864 +#define PATH0_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF +#define PATH0_R_TSSI_DELTA_CODE_MIN_C 0x5864 +#define PATH0_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00 +#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C 0x5864 +#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000 +#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C 0x5864 +#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000 +#define PATH0_R_GOTHROUGH_TX_IQKDPK_C 0x5864 +#define PATH0_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000 +#define PATH0_R_GOTHROUGH_RX_IQKDPK_C 0x5864 +#define PATH0_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000 +#define PATH0_R_IQK_IO_RFC_EN_C 0x5864 +#define PATH0_R_IQK_IO_RFC_EN_C_M 0x20000000 +#define PATH0_R_TX_IMFIR2_FORCE_RDY_C 0x5864 +#define PATH0_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000 +#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x5864 +#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000 +#define PATH0_R_ANT_TRAIN_EN_C 0x5868 +#define PATH0_R_ANT_TRAIN_EN_C_M 0x1 +#define PATH0_R_TX_ANT_SEL_C 0x5868 +#define PATH0_R_TX_ANT_SEL_C_M 0x2 +#define PATH0_R_RFE_BUF_EN_C 0x5868 +#define PATH0_R_RFE_BUF_EN_C_M 0x4 +#define PATH0_R_LNAON_AGC_C 0x5868 +#define PATH0_R_LNAON_AGC_C_M 0x8 +#define PATH0_R_TRSW_BIT_BT_C 0x5868 +#define PATH0_R_TRSW_BIT_BT_C_M 0x10 +#define PATH0_R_TRSW_S_C 0x5868 +#define PATH0_R_TRSW_S_C_M 0x20 +#define PATH0_R_TRSW_O_C 0x5868 +#define PATH0_R_TRSW_O_C_M 0x40 +#define PATH0_R_TRSWB_O_C 0x5868 +#define PATH0_R_TRSWB_O_C_M 0x80 +#define PATH0_R_BT_FORCE_ANTIDX_C 0x5868 +#define PATH0_R_BT_FORCE_ANTIDX_C_M 0xF00 +#define PATH0_R_BT_FORCE_ANTIDX_EN_C 0x5868 +#define PATH0_R_BT_FORCE_ANTIDX_EN_C_M 0x1000 +#define PATH0_R_ANT_MODULE_RFE_OPT_C 0x5868 +#define PATH0_R_ANT_MODULE_RFE_OPT_C_M 0xC000 +#define PATH0_R_RFSW_TR_C 0x5868 +#define PATH0_R_RFSW_TR_C_M 0xFFFF0000 +#define PATH0_R_ANTSEL_C 0x586C +#define PATH0_R_ANTSEL_C_M 0xFFFFFFFF +#define PATH0_R_RFSW_ANT_31_0__C 0x5870 +#define PATH0_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF +#define PATH0_R_RFSW_ANT_63_32__C 0x5874 +#define PATH0_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF +#define PATH0_R_RFSW_ANT_95_64__C 0x5878 +#define PATH0_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF +#define PATH0_R_RFSW_ANT_127_96__C 0x587C +#define PATH0_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF +#define PATH0_R_RFE_SEL_31_0__C 0x5880 +#define PATH0_R_RFE_SEL_31_0__C_M 0xFFFFFFFF +#define PATH0_R_RFE_SEL_63_32__C 0x5884 +#define PATH0_R_RFE_SEL_63_32__C_M 0xFFFFFFFF +#define PATH0_R_RFE_SEL_95_64__C 0x5888 +#define PATH0_R_RFE_SEL_95_64__C_M 0xFFFFFFFF +#define PATH0_R_RFE_SEL_127_96__C 0x588C +#define PATH0_R_RFE_SEL_127_96__C_M 0xFFFFFFFF +#define PATH0_R_RFE_INV_C 0x5890 +#define PATH0_R_RFE_INV_C_M 0xFFFFFFFF +#define PATH0_R_RFE_OPT_C 0x5894 +#define PATH0_R_RFE_OPT_C_M 0xFFFFFFF +#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x5894 +#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000 +#define PATH0_R_PATH_NOTRSW_BT_C 0x5894 +#define PATH0_R_PATH_NOTRSW_BT_C_M 0x20000000 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x5898 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x5898 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x5898 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x5898 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x589C +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x589C +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x589C +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000 +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x589C +#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_C 0x58A0 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF +#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C 0x58A0 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C 0x58A0 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C 0x58A0 +#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000 +#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C 0x58A4 +#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF +#define PATH0_R_TSSI_GAP_S0_C 0x58A4 +#define PATH0_R_TSSI_GAP_S0_C_M 0x1FF00 +#define PATH0_R_TSSI_GAP_S1_C 0x58A4 +#define PATH0_R_TSSI_GAP_S1_C_M 0x3FE0000 +#define PATH0_R_TSSI_GAP_S2_C 0x58A8 +#define PATH0_R_TSSI_GAP_S2_C_M 0x1FF +#define PATH0_R_TSSI_GAP_S3_C 0x58A8 +#define PATH0_R_TSSI_GAP_S3_C_M 0x3FE00 +#define PATH0_R_TSSI_GAP_S4_C 0x58A8 +#define PATH0_R_TSSI_GAP_S4_C_M 0x7FC0000 +#define PATH0_R_TSSI_GAP_S5_C 0x58AC +#define PATH0_R_TSSI_GAP_S5_C_M 0x1FF +#define PATH0_R_TSSI_GAP_S6_C 0x58AC +#define PATH0_R_TSSI_GAP_S6_C_M 0x3FE00 +#define PATH0_R_TSSI_GAP_S7_C 0x58AC +#define PATH0_R_TSSI_GAP_S7_C_M 0x7FC0000 +#define PATH0_R_IQK_DPK_PATH_RST_C 0x58AC +#define PATH0_R_IQK_DPK_PATH_RST_C_M 0x8000000 +#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C 0x58AC +#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000 +#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x58AC +#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000 +#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C 0x58AC +#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000 +#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x58AC +#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000 +#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C 0x58B0 +#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F +#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C 0x58B0 +#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80 +#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x58B0 +#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100 +#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x58B0 +#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200 +#define PATH0_R_DAC_GAIN_COMP_EN_C 0x58B0 +#define PATH0_R_DAC_GAIN_COMP_EN_C_M 0x400 +#define PATH0_R_TSSI_CW_COMP_EN_C 0x58B0 +#define PATH0_R_TSSI_CW_COMP_EN_C_M 0x800 +#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x58B0 +#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000 +#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x58B0 +#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000 +#define PATH0_R_TSSI_DBG_SEL_C 0x58B4 +#define PATH0_R_TSSI_DBG_SEL_C_M 0x1F +#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C 0x58B4 +#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20 +#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C 0x58B4 +#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0 +#define PATH0_R_TXPW_TBL_IOQ_DIS_C 0x58B4 +#define PATH0_R_TXPW_TBL_IOQ_DIS_C_M 0x200 +#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C 0x58B4 +#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000 +#define PATH0_R_TMETER_T0_CW_C 0x58B4 +#define PATH0_R_TMETER_T0_CW_C_M 0xFF0000 +#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C 0x58B4 +#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000 +#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x58B8 +#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F +#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x58B8 +#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00 +#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x58B8 +#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000 +#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x58B8 +#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000 +#define PATH0_R_TXAGC_OFST_MAX_C 0x58BC +#define PATH0_R_TXAGC_OFST_MAX_C_M 0xFF +#define PATH0_R_TXAGC_OFST_MIN_C 0x58BC +#define PATH0_R_TXAGC_OFST_MIN_C_M 0xFF00 +#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000 +#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000 +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000 +#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000 +#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000 +#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x58BC +#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000 +#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C 0x58C0 +#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF +#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C 0x58C0 +#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10 +#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C 0x58C0 +#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0 +#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C 0x58C0 +#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400 +#define PATH0_R_GAIN_TX_FORCE_VAL_C 0x58C0 +#define PATH0_R_GAIN_TX_FORCE_VAL_C_M 0xF800 +#define PATH0_R_GAIN_TX_FORCE_ON_C 0x58C0 +#define PATH0_R_GAIN_TX_FORCE_ON_C_M 0x10000 +#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C 0x58C0 +#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000 +#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C 0x58C0 +#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000 +#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x58C0 +#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000 +#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C 0x58C0 +#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000 +#define PATH0_R_BYPASS_TSSI_CCK_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000 +#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000 +#define PATH0_R_BYPASS_TSSI_HT_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_HT_EN_C_M 0x8000000 +#define PATH0_R_BYPASS_TSSI_VHT_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000 +#define PATH0_R_BYPASS_TSSI_HE_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_HE_EN_C_M 0x20000000 +#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000 +#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C 0x58C0 +#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000 +#define PATH0_R_RF_GAP_CAL_BND0_C 0x58C4 +#define PATH0_R_RF_GAP_CAL_BND0_C_M 0x3F +#define PATH0_R_RF_GAP_CAL_BND1_C 0x58C4 +#define PATH0_R_RF_GAP_CAL_BND1_C_M 0xFC0 +#define PATH0_R_RF_GAP_CAL_BND2_C 0x58C4 +#define PATH0_R_RF_GAP_CAL_BND2_C_M 0x3F000 +#define PATH0_R_TSSI_ADC_OFST_BND01_C 0x58C4 +#define PATH0_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000 +#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x58C4 +#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000 +#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x58C4 +#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000 +#define PATH0_R_TSSI_ADC_OFST_BND12_C 0x58C8 +#define PATH0_R_TSSI_ADC_OFST_BND12_C_M 0xFFF +#define PATH0_R_TSSI_ADC_OFST_BND22_C 0x58C8 +#define PATH0_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000 +#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x58C8 +#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000 +#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C 0x58C8 +#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000 +#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C 0x58C8 +#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000 +#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C 0x58C8 +#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000 +#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C 0x58C8 +#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000 +#define PATH0_R_BYPASS_TSSI_TXBF_EN_C 0x58C8 +#define PATH0_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000 +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x58CC +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7 +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x58CC +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38 +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x58CC +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0 +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x58CC +#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00 +#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x58CC +#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000 +#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C 0x58CC +#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000 +#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C 0x58D0 +#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF +#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C 0x58D0 +#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000 +#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x58D0 +#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000 +#define PATH0_R_TX_LSTF_PW_EST_LEN_C 0x58D0 +#define PATH0_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000 +#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x58D0 +#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000 +#define PATH0_R_TSSI_C_MAP_UNFIX_C 0x58D0 +#define PATH0_R_TSSI_C_MAP_UNFIX_C_M 0x80000000 +#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x58D4 +#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF +#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C 0x58D4 +#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00 +#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C 0x58D4 +#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000 +#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x58D4 +#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000 +#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x58D4 +#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000 +#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x58D4 +#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000 +#define PATH0_R_TXPW_SPLIT_FOR_DPD_C 0x58D4 +#define PATH0_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000 +#define PATH0_R_TXAGC_TP_MASK_EN_C 0x58D4 +#define PATH0_R_TXAGC_TP_MASK_EN_C_M 0x80000000 +#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C 0x58D8 +#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF +#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C 0x58D8 +#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00 +#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C 0x58D8 +#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000 +#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x58D8 +#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000 +#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C 0x58DC +#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF +#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C 0x58DC +#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00 +#define PATH0_R_TXAGC_OFST_FIX_C 0x58DC +#define PATH0_R_TXAGC_OFST_FIX_C_M 0x10000 +#define PATH0_R_TSSI_C_FORCE_VAL_C 0x58DC +#define PATH0_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000 +#define PATH0_R_TSSI_C_FORCE_ON_C 0x58DC +#define PATH0_R_TSSI_C_FORCE_ON_C_M 0x20000000 +#define PATH0_R_TXPW_RSTB_MAN_ON_C 0x58DC +#define PATH0_R_TXPW_RSTB_MAN_ON_C_M 0x40000000 +#define PATH0_R_TXPW_RSTB_MAN_C 0x58DC +#define PATH0_R_TXPW_RSTB_MAN_C_M 0x80000000 +#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C 0x58E0 +#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF +#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C 0x58E0 +#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000 +#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x58E0 +#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000 +#define PATH0_R_TXPW_RDY_NO_DLY_C 0x58E0 +#define PATH0_R_TXPW_RDY_NO_DLY_C_M 0x80000000 +#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x58E4 +#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F +#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x58E4 +#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80 +#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x58E4 +#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x58E4 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x58E4 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x58E4 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x58E4 +#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000 +#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x58E4 +#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000 +#define PATH0_R_TXPW_RSTB_SUB_SEL_C 0x58E4 +#define PATH0_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000 +#define PATH0_R_TXPW_RSTB_SUB_C 0x58E4 +#define PATH0_R_TXPW_RSTB_SUB_C_M 0x10000000 +#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x58E4 +#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000 +#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x58F0 +#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF +#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x58F0 +#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00 +#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x58F0 +#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000 +#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x58F0 +#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000 +#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x58F0 +#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000 +#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x58F4 +#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF +#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x58F4 +#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00 +#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x58F4 +#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000 +#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x58F8 +#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF +#define PATH0_R_LOG_VAL_OFST_CCK_C 0x58F8 +#define PATH0_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00 +#define PATH0_R_TSSI_ADC_PATH_Q_C 0x58F8 +#define PATH0_R_TSSI_ADC_PATH_Q_C_M 0x40000000 +#define PATH0_R_DAC_COMP_POST_DPD_EN_C 0x58F8 +#define PATH0_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000 +#define PATH0_R_LOG_VAL_OFST_OFDM_C 0x58FC +#define PATH0_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF +#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C 0x58FC +#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000 +#define PATH0_R_TSSI_UPD_TMETER_EN_C 0x58FC +#define PATH0_R_TSSI_UPD_TMETER_EN_C_M 0x800000 +#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C 0x58FC +#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000 +#define PATH0_R_TXRFC_BW_TXFORCE_ON_C 0x58FC +#define PATH0_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000 +#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x58FC +#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000 +#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x58FC +#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x5A00 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x5A00 +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x5A04 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x5A04 +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x5A08 +#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x5A08 +#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x5A0C +#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x5A0C +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x5A10 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x5A10 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x5A14 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x5A14 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x5A18 +#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x5A18 +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x5A1C +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x5A1C +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x5A20 +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x5A20 +#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x5A24 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x5A24 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x5A28 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x5A28 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x5A2C +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x5A2C +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x5A30 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x5A30 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x5A34 +#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x5A34 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x5A38 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x5A38 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x5A3C +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x5A3C +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x5A40 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x5A40 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x5A44 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x5A44 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x5A48 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x5A48 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x5A4C +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x5A4C +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x5A50 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x5A50 +#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x5A54 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x5A54 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x5A58 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x5A58 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x5A5C +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x5A5C +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x5A60 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x5A60 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x5A64 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x5A64 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x5A68 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x5A68 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x5A6C +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x5A6C +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x5A70 +#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x5A70 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x5A74 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x5A74 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x5A78 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x5A78 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x5A7C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x5A7C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A80 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A80 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x5A84 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x5A84 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x5A88 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x5A88 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x5A8C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x5A8C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x5A90 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x5A90 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x5A94 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x5A94 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A98 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A98 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x5A9C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x5A9C +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x5AA0 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x5AA0 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x5AA4 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x5AA4 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x5AA8 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x5AA8 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x5AAC +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x5AAC +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x5AB0 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x5AB0 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x5AB4 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x5AB4 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x5AB8 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x5AB8 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x5ABC +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x5ABC +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x5AC0 +#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF +#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C 0x5AC0 +#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x5C00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x5C00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x5C00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x5C00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x5C04 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x5C04 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x5C04 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x5C04 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x5C08 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x5C08 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x5C08 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x5C08 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x5C0C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x5C0C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x5C0C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x5C0C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x5C10 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x5C10 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x5C10 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x5C10 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x5C14 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x5C14 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x5C14 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x5C14 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x5C18 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x5C18 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x5C18 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x5C18 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x5C1C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x5C1C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x5C1C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x5C1C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x5C20 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x5C20 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x5C20 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x5C20 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x5C24 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x5C24 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x5C24 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x5C24 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x5C28 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x5C28 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x5C28 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x5C28 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x5C2C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x5C2C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x5C2C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x5C2C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x5C30 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x5C30 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x5C30 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x5C30 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x5C34 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x5C34 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x5C34 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x5C34 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x5C38 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x5C38 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x5C38 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x5C38 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x5C3C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x5C3C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x5C3C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000 +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x5C3C +#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x5C40 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x5C40 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x5C44 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x5C44 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x5C48 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x5C48 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x5C4C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x5C4C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x5C50 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x5C50 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x5C54 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x5C54 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x5C58 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x5C58 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x5C5C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x5C5C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x5C60 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x5C60 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x5C64 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x5C64 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x5C68 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x5C68 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x5C6C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x5C6C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x5C70 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x5C70 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x5C74 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x5C74 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x5C78 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x5C78 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x5C7C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x5C7C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x5C80 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x5C80 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x5C84 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x5C84 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x5C88 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x5C88 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x5C8C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x5C8C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x5C90 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x5C90 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x5C94 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x5C94 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x5C98 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x5C98 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x5C9C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x5C9C +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x5CA0 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x5CA0 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x5CA4 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x5CA4 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x5CA8 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x5CA8 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x5CAC +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x5CAC +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x5CB0 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x5CB0 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x5CB4 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x5CB4 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x5CB8 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x5CB8 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000 +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x5CBC +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x5CBC +#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000 +#define PATH1_R_TSSI_CURVE_P0_C 0x7600 +#define PATH1_R_TSSI_CURVE_P0_C_M 0x3F +#define PATH1_R_TSSI_CURVE_P1_C 0x7600 +#define PATH1_R_TSSI_CURVE_P1_C_M 0x3F00 +#define PATH1_R_TSSI_CURVE_P2_C 0x7600 +#define PATH1_R_TSSI_CURVE_P2_C_M 0x3F0000 +#define PATH1_R_TSSI_CURVE_P3_C 0x7600 +#define PATH1_R_TSSI_CURVE_P3_C_M 0x3F000000 +#define PATH1_R_TSSI_CURVE_P4_C 0x7604 +#define PATH1_R_TSSI_CURVE_P4_C_M 0x3F +#define PATH1_R_TSSI_CURVE_P5_C 0x7604 +#define PATH1_R_TSSI_CURVE_P5_C_M 0x3F00 +#define PATH1_R_TSSI_CURVE_P6_C 0x7604 +#define PATH1_R_TSSI_CURVE_P6_C_M 0x3F0000 +#define PATH1_R_TSSI_CURVE_EN_C 0x7604 +#define PATH1_R_TSSI_CURVE_EN_C_M 0x80000000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x7608 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x7608 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x7608 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x760C +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x760C +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x760C +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x7610 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x7610 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x7610 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x7614 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x7614 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x7614 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x7618 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x7618 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x7618 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x761C +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x761C +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x761C +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x7620 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x7620 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x7620 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x7620 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x7624 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x7624 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x7624 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x7624 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x7628 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x7628 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x7628 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x7628 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000 +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x762C +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x762C +#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00 +#define PATH1_R_TSSI_J_OFDM_G0_C 0x7630 +#define PATH1_R_TSSI_J_OFDM_G0_C_M 0x3FF +#define PATH1_R_TSSI_J_OFDM_G1_C 0x7630 +#define PATH1_R_TSSI_J_OFDM_G1_C_M 0xFFC00 +#define PATH1_R_TSSI_J_OFDM_G2_C 0x7630 +#define PATH1_R_TSSI_J_OFDM_G2_C_M 0x3FF00000 +#define PATH1_R_TSSI_J_OFDM_G3_C 0x7634 +#define PATH1_R_TSSI_J_OFDM_G3_C_M 0x3FF +#define PATH1_R_TSSI_J_OFDM_G4_C 0x7634 +#define PATH1_R_TSSI_J_OFDM_G4_C_M 0xFFC00 +#define PATH1_R_TSSI_J_OFDM_G5_C 0x7634 +#define PATH1_R_TSSI_J_OFDM_G5_C_M 0x3FF00000 +#define PATH1_R_TSSI_J_OFDM_G6_C 0x7638 +#define PATH1_R_TSSI_J_OFDM_G6_C_M 0x3FF +#define PATH1_R_TSSI_J_OFDM_G7_C 0x7638 +#define PATH1_R_TSSI_J_OFDM_G7_C_M 0xFFC00 +#define PATH1_R_TSSI_J_CCK_G0_C 0x763C +#define PATH1_R_TSSI_J_CCK_G0_C_M 0x3FF +#define PATH1_R_TSSI_J_CCK_G1_C 0x763C +#define PATH1_R_TSSI_J_CCK_G1_C_M 0xFFC00 +#define PATH1_R_TSSI_J_CCK_G2_C 0x763C +#define PATH1_R_TSSI_J_CCK_G2_C_M 0x3FF00000 +#define PATH1_R_TSSI_J_CCK_G3_C 0x7640 +#define PATH1_R_TSSI_J_CCK_G3_C_M 0x3FF +#define PATH1_R_TSSI_J_CCK_G4_C 0x7640 +#define PATH1_R_TSSI_J_CCK_G4_C_M 0xFFC00 +#define PATH1_R_TSSI_J_CCK_G5_C 0x7640 +#define PATH1_R_TSSI_J_CCK_G5_C_M 0x3FF00000 +#define PATH1_R_TSSI_J_CCK_G6_C 0x7644 +#define PATH1_R_TSSI_J_CCK_G6_C_M 0x3FF +#define PATH1_R_TSSI_J_CCK_G7_C 0x7644 +#define PATH1_R_TSSI_J_CCK_G7_C_M 0xFFC00 +#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C 0x7648 +#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF +#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C 0x7648 +#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10 +#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x7648 +#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0 +#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x7648 +#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400 +#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x7648 +#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800 +#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x7648 +#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000 +#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x7648 +#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000 +#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x7648 +#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000 +#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x764C +#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F +#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C 0x764C +#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20 +#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x764C +#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0 +#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x764C +#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100 +#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x764C +#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600 +#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x764C +#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800 +#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x764C +#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000 +#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x764C +#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000 +#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x764C +#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000 +#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x764C +#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x7650 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x7650 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x7650 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x7650 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x7650 +#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000 +#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C 0x7650 +#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000 +#define PATH1_R_TSSI_DCK_BY_CURVE_0_C 0x7654 +#define PATH1_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF +#define PATH1_R_TSSI_DCK_BY_CURVE_1_C 0x7654 +#define PATH1_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000 +#define PATH1_R_TSSI_DCK_BY_CURVE_2_C 0x7658 +#define PATH1_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF +#define PATH1_R_TSSI_DCK_BY_CURVE_3_C 0x7658 +#define PATH1_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000 +#define PATH1_R_TSSI_DCK_BY_CURVE_4_C 0x765C +#define PATH1_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF +#define PATH1_R_TSSI_DCK_BY_CURVE_5_C 0x765C +#define PATH1_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000 +#define PATH1_R_TSSI_DCK_BY_CURVE_6_C 0x7660 +#define PATH1_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF +#define PATH1_R_TSSI_DCK_BY_CURVE_7_C 0x7660 +#define PATH1_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x7664 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x7664 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x7664 +#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0 +#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C 0x7664 +#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000 +#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C 0x7664 +#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000 +#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x7664 +#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000 +#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x7664 +#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000 +#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x7668 +#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1 +#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x7668 +#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2 +#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x7668 +#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4 +#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x7668 +#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8 +#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x7668 +#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0 +#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x7668 +#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800 +#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x7668 +#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000 +#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x7668 +#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000 +#define PATH1_R_TSSI_TIMEOUT_TIME_C 0x766C +#define PATH1_R_TSSI_TIMEOUT_TIME_C_M 0xFFF +#define PATH1_R_TSSI_TIMEOUT_UNIT_C 0x766C +#define PATH1_R_TSSI_TIMEOUT_UNIT_C_M 0x3000 +#define PATH1_R_TXAGC_MAX_C 0x7800 +#define PATH1_R_TXAGC_MAX_C_M 0xFF +#define PATH1_R_TXAGC_MIN_C 0x7800 +#define PATH1_R_TXAGC_MIN_C_M 0xFF00 +#define PATH1_R_TXAGC_RF_MAX_C 0x7800 +#define PATH1_R_TXAGC_RF_MAX_C_M 0x3F0000 +#define PATH1_R_TXAGC_RF_MIN_C 0x7800 +#define PATH1_R_TXAGC_RF_MIN_C_M 0xFC00000 +#define PATH1_R_DPD_OFST_EN_C 0x7800 +#define PATH1_R_DPD_OFST_EN_C_M 0x10000000 +#define PATH1_R_TXAGCSWING_EN_C 0x7800 +#define PATH1_R_TXAGCSWING_EN_C_M 0x20000000 +#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C 0x7800 +#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000 +#define PATH1_R_DIS_CCK_SWING_TXAGC_C 0x7800 +#define PATH1_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000 +#define PATH1_R_TXAGC_OFDM_REF_DBM_C 0x7804 +#define PATH1_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF +#define PATH1_R_TXAGC_OFDM_REF_CW_C 0x7804 +#define PATH1_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00 +#define PATH1_R_TSSI_MAP_OFST_OFDM_C 0x7804 +#define PATH1_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000 +#define PATH1_R_DPD_OFST_C 0x7804 +#define PATH1_R_DPD_OFST_C_M 0xF8000000 +#define PATH1_R_TXAGC_CCK_REF_DBM_C 0x7808 +#define PATH1_R_TXAGC_CCK_REF_DBM_C_M 0x1FF +#define PATH1_R_TXAGC_CCK_REF_CW_C 0x7808 +#define PATH1_R_TXAGC_CCK_REF_CW_C_M 0x3FE00 +#define PATH1_R_TSSI_MAP_OFST_CCK_C 0x7808 +#define PATH1_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000 +#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C 0x780C +#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F +#define PATH1_R_TSSI_MAP_SLOPE_CCK_C 0x780C +#define PATH1_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00 +#define PATH1_R_TXPW_FORCE_RDY_C 0x780C +#define PATH1_R_TXPW_FORCE_RDY_C_M 0x8000 +#define PATH1_R_TSSI_ADC_DC_OFST_RE_C 0x780C +#define PATH1_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000 +#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x780C +#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000 +#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x780C +#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000 +#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C +#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000 +#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C +#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000 +#define PATH1_R_TXAGC_PSEUDO_CW_C 0x7810 +#define PATH1_R_TXAGC_PSEUDO_CW_C_M 0x1FF +#define PATH1_R_TXAGC_PSEUDO_CW_EN_C 0x7810 +#define PATH1_R_TXAGC_PSEUDO_CW_EN_C_M 0x200 +#define PATH1_R_TMETER_T0_C 0x7810 +#define PATH1_R_TMETER_T0_C_M 0xFC00 +#define PATH1_R_DIS_TSSI_F_C 0x7810 +#define PATH1_R_DIS_TSSI_F_C_M 0x10000 +#define PATH1_R_TMETER_TBL_RA_C 0x7810 +#define PATH1_R_TMETER_TBL_RA_C_M 0x7E0000 +#define PATH1_R_TMETER_TBL_RD_C 0x7810 +#define PATH1_R_TMETER_TBL_RD_C_M 0x800000 +#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C 0x7810 +#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000 +#define PATH1_R_TMETER_TBL_FORCE_WEN_C 0x7810 +#define PATH1_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000 +#define PATH1_R_TMETER_TBL_FORCE_REN_C 0x7810 +#define PATH1_R_TMETER_TBL_FORCE_REN_C_M 0x4000000 +#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x7810 +#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000 +#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C 0x7810 +#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000 +#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x7810 +#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000 +#define PATH1_R_TSSI_DBG_PORT_EN_C 0x7810 +#define PATH1_R_TSSI_DBG_PORT_EN_C_M 0x40000000 +#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x7810 +#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000 +#define PATH1_R_TSSI_RF_GAP_TBL_RA_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F +#define PATH1_R_TSSI_RF_GAP_EN_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_EN_C_M 0x40 +#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80 +#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100 +#define PATH1_R_TSSI_RF_GAP_TBL_RD_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_TBL_RD_C_M 0x200 +#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x7814 +#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400 +#define PATH1_R_TSSI_BYPASS_TSSI_C_C 0x7814 +#define PATH1_R_TSSI_BYPASS_TSSI_C_C_M 0x800 +#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x7814 +#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000 +#define PATH1_R_TSSI_DCK_AUTO_EN_C 0x7814 +#define PATH1_R_TSSI_DCK_AUTO_EN_C_M 0x2000 +#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x7814 +#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000 +#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C 0x7814 +#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000 +#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C 0x7814 +#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000 +#define PATH1_R_TSSI_ADC_AMPLIFY_C 0x7814 +#define PATH1_R_TSSI_ADC_AMPLIFY_C_M 0xC00000 +#define PATH1_R_TSSI_PW_TRK_USE_025DB_C 0x7814 +#define PATH1_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000 +#define PATH1_R_TSSI_DCK_SEL_C 0x7814 +#define PATH1_R_TSSI_DCK_SEL_C_M 0x18000000 +#define PATH1_R_TSSI_TXADC_PW_SV_EN_C 0x7814 +#define PATH1_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000 +#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000 +#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C 0x7814 +#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000 +#define PATH1_R_TXAGC_OFST_C 0x7818 +#define PATH1_R_TXAGC_OFST_C_M 0xFF +#define PATH1_R_HE_ER_STF_PW_OFST_C 0x7818 +#define PATH1_R_HE_ER_STF_PW_OFST_C_M 0x1FF00 +#define PATH1_R_HE_STF_PW_OFST_C 0x7818 +#define PATH1_R_HE_STF_PW_OFST_C_M 0x3FE0000 +#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C 0x7818 +#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000 +#define PATH1_R_TSSI_OFST_BY_RFC_C 0x7818 +#define PATH1_R_TSSI_OFST_BY_RFC_C_M 0x8000000 +#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C 0x7818 +#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000 +#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x7818 +#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000 +#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x7818 +#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000 +#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x7818 +#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000 +#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C 0x781C +#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF +#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C 0x781C +#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00 +#define PATH1_R_TSSI_SLOPE_CAL_EN_C 0x781C +#define PATH1_R_TSSI_SLOPE_CAL_EN_C_M 0x100000 +#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x781C +#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000 +#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x781C +#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000 +#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C 0x781C +#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000 +#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x781C +#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000 +#define PATH1_R_TSSI_SLOPE_A_C 0x7820 +#define PATH1_R_TSSI_SLOPE_A_C_M 0xFFF +#define PATH1_R_TSSI_PKT_AVG_NUM_C 0x7820 +#define PATH1_R_TSSI_PKT_AVG_NUM_C_M 0xF000 +#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C 0x7820 +#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000 +#define PATH1_R_TSSI_PW_TRK_SW_OFST_C 0x7820 +#define PATH1_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000 +#define PATH1_R_TSSI_ISEPA_C 0x7820 +#define PATH1_R_TSSI_ISEPA_C_M 0x40000000 +#define PATH1_R_TSSI_EN_C 0x7820 +#define PATH1_R_TSSI_EN_C_M 0x80000000 +#define PATH1_R_TSSI_A_OFDM_5M_C 0x7824 +#define PATH1_R_TSSI_A_OFDM_5M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_5M_C 0x7824 +#define PATH1_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_5M_C 0x7828 +#define PATH1_R_TSSI_K_OFDM_5M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_5M_C 0x7828 +#define PATH1_R_TSSI_DE_OFDM_5M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x7828 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_OFDM_10M_C 0x782C +#define PATH1_R_TSSI_A_OFDM_10M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_10M_C 0x782C +#define PATH1_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_10M_C 0x7830 +#define PATH1_R_TSSI_K_OFDM_10M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_10M_C 0x7830 +#define PATH1_R_TSSI_DE_OFDM_10M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x7830 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_OFDM_20M_C 0x7834 +#define PATH1_R_TSSI_A_OFDM_20M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_20M_C 0x7834 +#define PATH1_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_20M_C 0x7838 +#define PATH1_R_TSSI_K_OFDM_20M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_20M_C 0x7838 +#define PATH1_R_TSSI_DE_OFDM_20M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x7838 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_OFDM_40M_C 0x783C +#define PATH1_R_TSSI_A_OFDM_40M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_40M_C 0x783C +#define PATH1_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_40M_C 0x7840 +#define PATH1_R_TSSI_K_OFDM_40M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_40M_C 0x7840 +#define PATH1_R_TSSI_DE_OFDM_40M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x7840 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_OFDM_80M_C 0x7844 +#define PATH1_R_TSSI_A_OFDM_80M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_80M_C 0x7844 +#define PATH1_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_80M_C 0x7848 +#define PATH1_R_TSSI_K_OFDM_80M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_80M_C 0x7848 +#define PATH1_R_TSSI_DE_OFDM_80M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x7848 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_OFDM_80_80M_C 0x784C +#define PATH1_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF +#define PATH1_R_TSSI_B_OFDM_80_80M_C 0x784C +#define PATH1_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_OFDM_80_80M_C 0x7850 +#define PATH1_R_TSSI_K_OFDM_80_80M_C_M 0xFFF +#define PATH1_R_TSSI_DE_OFDM_80_80M_C 0x7850 +#define PATH1_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x7850 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_CCK_LONG_C 0x7854 +#define PATH1_R_TSSI_A_CCK_LONG_C_M 0x3FFFF +#define PATH1_R_TSSI_B_CCK_LONG_C 0x7854 +#define PATH1_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_CCK_LONG_C 0x7858 +#define PATH1_R_TSSI_K_CCK_LONG_C_M 0xFFF +#define PATH1_R_TSSI_DE_CCK_LONG_C 0x7858 +#define PATH1_R_TSSI_DE_CCK_LONG_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x7858 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000 +#define PATH1_R_TSSI_A_CCK_SHORT_C 0x785C +#define PATH1_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF +#define PATH1_R_TSSI_B_CCK_SHORT_C 0x785C +#define PATH1_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000 +#define PATH1_R_TSSI_K_CCK_SHORT_C 0x7860 +#define PATH1_R_TSSI_K_CCK_SHORT_C_M 0xFFF +#define PATH1_R_TSSI_DE_CCK_SHORT_C 0x7860 +#define PATH1_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x7860 +#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000 +#define PATH1_RSWING_NO_LIM_C 0x7860 +#define PATH1_RSWING_NO_LIM_C_M 0x80000000 +#define PATH1_R_TSSI_DELTA_CODE_MAX_C 0x7864 +#define PATH1_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF +#define PATH1_R_TSSI_DELTA_CODE_MIN_C 0x7864 +#define PATH1_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00 +#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C 0x7864 +#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000 +#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C 0x7864 +#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000 +#define PATH1_R_GOTHROUGH_TX_IQKDPK_C 0x7864 +#define PATH1_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000 +#define PATH1_R_GOTHROUGH_RX_IQKDPK_C 0x7864 +#define PATH1_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000 +#define PATH1_R_IQK_IO_RFC_EN_C 0x7864 +#define PATH1_R_IQK_IO_RFC_EN_C_M 0x20000000 +#define PATH1_R_TX_IMFIR2_FORCE_RDY_C 0x7864 +#define PATH1_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000 +#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x7864 +#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000 +#define PATH1_R_ANT_TRAIN_EN_C 0x7868 +#define PATH1_R_ANT_TRAIN_EN_C_M 0x1 +#define PATH1_R_TX_ANT_SEL_C 0x7868 +#define PATH1_R_TX_ANT_SEL_C_M 0x2 +#define PATH1_R_RFE_BUF_EN_C 0x7868 +#define PATH1_R_RFE_BUF_EN_C_M 0x4 +#define PATH1_R_LNAON_AGC_C 0x7868 +#define PATH1_R_LNAON_AGC_C_M 0x8 +#define PATH1_R_TRSW_BIT_BT_C 0x7868 +#define PATH1_R_TRSW_BIT_BT_C_M 0x10 +#define PATH1_R_TRSW_S_C 0x7868 +#define PATH1_R_TRSW_S_C_M 0x20 +#define PATH1_R_TRSW_O_C 0x7868 +#define PATH1_R_TRSW_O_C_M 0x40 +#define PATH1_R_TRSWB_O_C 0x7868 +#define PATH1_R_TRSWB_O_C_M 0x80 +#define PATH1_R_BT_FORCE_ANTIDX_C 0x7868 +#define PATH1_R_BT_FORCE_ANTIDX_C_M 0xF00 +#define PATH1_R_BT_FORCE_ANTIDX_EN_C 0x7868 +#define PATH1_R_BT_FORCE_ANTIDX_EN_C_M 0x1000 +#define PATH1_R_ANT_MODULE_RFE_OPT_C 0x7868 +#define PATH1_R_ANT_MODULE_RFE_OPT_C_M 0xC000 +#define PATH1_R_RFSW_TR_C 0x7868 +#define PATH1_R_RFSW_TR_C_M 0xFFFF0000 +#define PATH1_R_ANTSEL_C 0x786C +#define PATH1_R_ANTSEL_C_M 0xFFFFFFFF +#define PATH1_R_RFSW_ANT_31_0__C 0x7870 +#define PATH1_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF +#define PATH1_R_RFSW_ANT_63_32__C 0x7874 +#define PATH1_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF +#define PATH1_R_RFSW_ANT_95_64__C 0x7878 +#define PATH1_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF +#define PATH1_R_RFSW_ANT_127_96__C 0x787C +#define PATH1_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF +#define PATH1_R_RFE_SEL_31_0__C 0x7880 +#define PATH1_R_RFE_SEL_31_0__C_M 0xFFFFFFFF +#define PATH1_R_RFE_SEL_63_32__C 0x7884 +#define PATH1_R_RFE_SEL_63_32__C_M 0xFFFFFFFF +#define PATH1_R_RFE_SEL_95_64__C 0x7888 +#define PATH1_R_RFE_SEL_95_64__C_M 0xFFFFFFFF +#define PATH1_R_RFE_SEL_127_96__C 0x788C +#define PATH1_R_RFE_SEL_127_96__C_M 0xFFFFFFFF +#define PATH1_R_RFE_INV_C 0x7890 +#define PATH1_R_RFE_INV_C_M 0xFFFFFFFF +#define PATH1_R_RFE_OPT_C 0x7894 +#define PATH1_R_RFE_OPT_C_M 0xFFFFFFF +#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x7894 +#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000 +#define PATH1_R_PATH_NOTRSW_BT_C 0x7894 +#define PATH1_R_PATH_NOTRSW_BT_C_M 0x20000000 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x7898 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x7898 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x7898 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x7898 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x789C +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x789C +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x789C +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000 +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x789C +#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_C 0x78A0 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF +#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C 0x78A0 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C 0x78A0 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C 0x78A0 +#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000 +#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C 0x78A4 +#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF +#define PATH1_R_TSSI_GAP_S0_C 0x78A4 +#define PATH1_R_TSSI_GAP_S0_C_M 0x1FF00 +#define PATH1_R_TSSI_GAP_S1_C 0x78A4 +#define PATH1_R_TSSI_GAP_S1_C_M 0x3FE0000 +#define PATH1_R_TSSI_GAP_S2_C 0x78A8 +#define PATH1_R_TSSI_GAP_S2_C_M 0x1FF +#define PATH1_R_TSSI_GAP_S3_C 0x78A8 +#define PATH1_R_TSSI_GAP_S3_C_M 0x3FE00 +#define PATH1_R_TSSI_GAP_S4_C 0x78A8 +#define PATH1_R_TSSI_GAP_S4_C_M 0x7FC0000 +#define PATH1_R_TSSI_GAP_S5_C 0x78AC +#define PATH1_R_TSSI_GAP_S5_C_M 0x1FF +#define PATH1_R_TSSI_GAP_S6_C 0x78AC +#define PATH1_R_TSSI_GAP_S6_C_M 0x3FE00 +#define PATH1_R_TSSI_GAP_S7_C 0x78AC +#define PATH1_R_TSSI_GAP_S7_C_M 0x7FC0000 +#define PATH1_R_IQK_DPK_PATH_RST_C 0x78AC +#define PATH1_R_IQK_DPK_PATH_RST_C_M 0x8000000 +#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C 0x78AC +#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000 +#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x78AC +#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000 +#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C 0x78AC +#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000 +#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x78AC +#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000 +#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C 0x78B0 +#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F +#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C 0x78B0 +#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80 +#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x78B0 +#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100 +#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x78B0 +#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200 +#define PATH1_R_DAC_GAIN_COMP_EN_C 0x78B0 +#define PATH1_R_DAC_GAIN_COMP_EN_C_M 0x400 +#define PATH1_R_TSSI_CW_COMP_EN_C 0x78B0 +#define PATH1_R_TSSI_CW_COMP_EN_C_M 0x800 +#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x78B0 +#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000 +#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x78B0 +#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000 +#define PATH1_R_TSSI_DBG_SEL_C 0x78B4 +#define PATH1_R_TSSI_DBG_SEL_C_M 0x1F +#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C 0x78B4 +#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20 +#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C 0x78B4 +#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0 +#define PATH1_R_TXPW_TBL_IOQ_DIS_C 0x78B4 +#define PATH1_R_TXPW_TBL_IOQ_DIS_C_M 0x200 +#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C 0x78B4 +#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000 +#define PATH1_R_TMETER_T0_CW_C 0x78B4 +#define PATH1_R_TMETER_T0_CW_C_M 0xFF0000 +#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C 0x78B4 +#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000 +#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x78B8 +#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F +#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x78B8 +#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00 +#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x78B8 +#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000 +#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x78B8 +#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000 +#define PATH1_R_TXAGC_OFST_MAX_C 0x78BC +#define PATH1_R_TXAGC_OFST_MAX_C_M 0xFF +#define PATH1_R_TXAGC_OFST_MIN_C 0x78BC +#define PATH1_R_TXAGC_OFST_MIN_C_M 0xFF00 +#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000 +#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000 +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000 +#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000 +#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000 +#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x78BC +#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000 +#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C 0x78C0 +#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF +#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C 0x78C0 +#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10 +#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C 0x78C0 +#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0 +#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C 0x78C0 +#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400 +#define PATH1_R_GAIN_TX_FORCE_VAL_C 0x78C0 +#define PATH1_R_GAIN_TX_FORCE_VAL_C_M 0xF800 +#define PATH1_R_GAIN_TX_FORCE_ON_C 0x78C0 +#define PATH1_R_GAIN_TX_FORCE_ON_C_M 0x10000 +#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C 0x78C0 +#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000 +#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C 0x78C0 +#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000 +#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x78C0 +#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000 +#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C 0x78C0 +#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000 +#define PATH1_R_BYPASS_TSSI_CCK_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000 +#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000 +#define PATH1_R_BYPASS_TSSI_HT_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_HT_EN_C_M 0x8000000 +#define PATH1_R_BYPASS_TSSI_VHT_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000 +#define PATH1_R_BYPASS_TSSI_HE_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_HE_EN_C_M 0x20000000 +#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000 +#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C 0x78C0 +#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000 +#define PATH1_R_RF_GAP_CAL_BND0_C 0x78C4 +#define PATH1_R_RF_GAP_CAL_BND0_C_M 0x3F +#define PATH1_R_RF_GAP_CAL_BND1_C 0x78C4 +#define PATH1_R_RF_GAP_CAL_BND1_C_M 0xFC0 +#define PATH1_R_RF_GAP_CAL_BND2_C 0x78C4 +#define PATH1_R_RF_GAP_CAL_BND2_C_M 0x3F000 +#define PATH1_R_TSSI_ADC_OFST_BND01_C 0x78C4 +#define PATH1_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000 +#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x78C4 +#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000 +#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x78C4 +#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000 +#define PATH1_R_TSSI_ADC_OFST_BND12_C 0x78C8 +#define PATH1_R_TSSI_ADC_OFST_BND12_C_M 0xFFF +#define PATH1_R_TSSI_ADC_OFST_BND22_C 0x78C8 +#define PATH1_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000 +#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x78C8 +#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000 +#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C 0x78C8 +#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000 +#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C 0x78C8 +#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000 +#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C 0x78C8 +#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000 +#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C 0x78C8 +#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000 +#define PATH1_R_BYPASS_TSSI_TXBF_EN_C 0x78C8 +#define PATH1_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000 +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x78CC +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7 +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x78CC +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38 +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x78CC +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0 +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x78CC +#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00 +#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x78CC +#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000 +#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C 0x78CC +#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000 +#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C 0x78D0 +#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF +#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C 0x78D0 +#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000 +#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x78D0 +#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000 +#define PATH1_R_TX_LSTF_PW_EST_LEN_C 0x78D0 +#define PATH1_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000 +#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x78D0 +#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000 +#define PATH1_R_TSSI_C_MAP_UNFIX_C 0x78D0 +#define PATH1_R_TSSI_C_MAP_UNFIX_C_M 0x80000000 +#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x78D4 +#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF +#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C 0x78D4 +#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00 +#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C 0x78D4 +#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000 +#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x78D4 +#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000 +#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x78D4 +#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000 +#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x78D4 +#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000 +#define PATH1_R_TXPW_SPLIT_FOR_DPD_C 0x78D4 +#define PATH1_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000 +#define PATH1_R_TXAGC_TP_MASK_EN_C 0x78D4 +#define PATH1_R_TXAGC_TP_MASK_EN_C_M 0x80000000 +#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C 0x78D8 +#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF +#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C 0x78D8 +#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00 +#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C 0x78D8 +#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000 +#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x78D8 +#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000 +#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C 0x78DC +#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF +#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C 0x78DC +#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00 +#define PATH1_R_TXAGC_OFST_FIX_C 0x78DC +#define PATH1_R_TXAGC_OFST_FIX_C_M 0x10000 +#define PATH1_R_TSSI_C_FORCE_VAL_C 0x78DC +#define PATH1_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000 +#define PATH1_R_TSSI_C_FORCE_ON_C 0x78DC +#define PATH1_R_TSSI_C_FORCE_ON_C_M 0x20000000 +#define PATH1_R_TXPW_RSTB_MAN_ON_C 0x78DC +#define PATH1_R_TXPW_RSTB_MAN_ON_C_M 0x40000000 +#define PATH1_R_TXPW_RSTB_MAN_C 0x78DC +#define PATH1_R_TXPW_RSTB_MAN_C_M 0x80000000 +#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C 0x78E0 +#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF +#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C 0x78E0 +#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000 +#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x78E0 +#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000 +#define PATH1_R_TXPW_RDY_NO_DLY_C 0x78E0 +#define PATH1_R_TXPW_RDY_NO_DLY_C_M 0x80000000 +#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x78E4 +#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F +#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x78E4 +#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80 +#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x78E4 +#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x78E4 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x78E4 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x78E4 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x78E4 +#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000 +#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x78E4 +#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000 +#define PATH1_R_TXPW_RSTB_SUB_SEL_C 0x78E4 +#define PATH1_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000 +#define PATH1_R_TXPW_RSTB_SUB_C 0x78E4 +#define PATH1_R_TXPW_RSTB_SUB_C_M 0x10000000 +#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x78E4 +#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000 +#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x78F0 +#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF +#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x78F0 +#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00 +#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x78F0 +#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000 +#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x78F0 +#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000 +#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x78F0 +#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000 +#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x78F4 +#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF +#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x78F4 +#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00 +#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x78F4 +#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000 +#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x78F8 +#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF +#define PATH1_R_LOG_VAL_OFST_CCK_C 0x78F8 +#define PATH1_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00 +#define PATH1_R_TSSI_ADC_PATH_Q_C 0x78F8 +#define PATH1_R_TSSI_ADC_PATH_Q_C_M 0x40000000 +#define PATH1_R_DAC_COMP_POST_DPD_EN_C 0x78F8 +#define PATH1_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000 +#define PATH1_R_LOG_VAL_OFST_OFDM_C 0x78FC +#define PATH1_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF +#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C 0x78FC +#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000 +#define PATH1_R_TSSI_UPD_TMETER_EN_C 0x78FC +#define PATH1_R_TSSI_UPD_TMETER_EN_C_M 0x800000 +#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C 0x78FC +#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000 +#define PATH1_R_TXRFC_BW_TXFORCE_ON_C 0x78FC +#define PATH1_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000 +#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x78FC +#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000 +#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x78FC +#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x7A00 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x7A00 +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x7A04 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x7A04 +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x7A08 +#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x7A08 +#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x7A0C +#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x7A0C +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x7A10 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x7A10 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x7A14 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x7A14 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x7A18 +#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x7A18 +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x7A1C +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x7A1C +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x7A20 +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x7A20 +#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x7A24 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x7A24 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x7A28 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x7A28 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x7A2C +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x7A2C +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x7A30 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x7A30 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x7A34 +#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x7A34 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x7A38 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x7A38 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x7A3C +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x7A3C +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x7A40 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x7A40 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x7A44 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x7A44 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x7A48 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x7A48 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x7A4C +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x7A4C +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x7A50 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x7A50 +#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x7A54 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x7A54 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x7A58 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x7A58 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x7A5C +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x7A5C +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x7A60 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x7A60 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x7A64 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x7A64 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x7A68 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x7A68 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x7A6C +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x7A6C +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x7A70 +#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x7A70 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x7A74 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x7A74 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x7A78 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x7A78 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x7A7C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x7A7C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A80 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A80 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x7A84 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x7A84 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x7A88 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x7A88 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x7A8C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x7A8C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x7A90 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x7A90 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x7A94 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x7A94 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A98 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A98 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x7A9C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x7A9C +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x7AA0 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x7AA0 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x7AA4 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x7AA4 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x7AA8 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x7AA8 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x7AAC +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x7AAC +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x7AB0 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x7AB0 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x7AB4 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x7AB4 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x7AB8 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x7AB8 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x7ABC +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x7ABC +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x7AC0 +#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF +#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C 0x7AC0 +#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x7C00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x7C00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x7C00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x7C00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x7C04 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x7C04 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x7C04 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x7C04 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x7C08 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x7C08 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x7C08 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x7C08 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x7C0C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x7C0C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x7C0C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x7C0C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x7C10 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x7C10 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x7C10 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x7C10 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x7C14 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x7C14 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x7C14 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x7C14 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x7C18 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x7C18 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x7C18 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x7C18 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x7C1C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x7C1C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x7C1C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x7C1C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x7C20 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x7C20 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x7C20 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x7C20 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x7C24 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x7C24 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x7C24 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x7C24 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x7C28 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x7C28 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x7C28 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x7C28 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x7C2C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x7C2C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x7C2C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x7C2C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x7C30 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x7C30 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x7C30 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x7C30 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x7C34 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x7C34 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x7C34 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x7C34 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x7C38 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x7C38 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x7C38 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x7C38 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x7C3C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x7C3C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x7C3C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000 +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x7C3C +#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x7C40 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x7C40 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x7C44 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x7C44 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x7C48 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x7C48 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x7C4C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x7C4C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x7C50 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x7C50 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x7C54 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x7C54 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x7C58 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x7C58 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x7C5C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x7C5C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x7C60 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x7C60 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x7C64 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x7C64 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x7C68 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x7C68 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x7C6C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x7C6C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x7C70 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x7C70 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x7C74 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x7C74 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x7C78 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x7C78 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x7C7C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x7C7C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x7C80 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x7C80 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x7C84 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x7C84 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x7C88 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x7C88 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x7C8C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x7C8C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x7C90 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x7C90 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x7C94 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x7C94 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x7C98 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x7C98 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x7C9C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x7C9C +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x7CA0 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x7CA0 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x7CA4 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x7CA4 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x7CA8 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x7CA8 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x7CAC +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x7CAC +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x7CB0 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x7CB0 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x7CB4 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x7CB4 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x7CB8 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x7CB8 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000 +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x7CBC +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x7CBC +#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000 +#define FPGA_DC_OFST_0_C 0xC000 +#define FPGA_DC_OFST_0_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_1_C 0xC004 +#define FPGA_DC_OFST_1_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_2_C 0xC008 +#define FPGA_DC_OFST_2_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_3_C 0xC00C +#define FPGA_DC_OFST_3_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_4_C 0xC010 +#define FPGA_DC_OFST_4_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_5_C 0xC014 +#define FPGA_DC_OFST_5_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_6_C 0xC018 +#define FPGA_DC_OFST_6_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_7_C 0xC01C +#define FPGA_DC_OFST_7_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_8_C 0xC020 +#define FPGA_DC_OFST_8_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_9_C 0xC024 +#define FPGA_DC_OFST_9_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_10_C 0xC028 +#define FPGA_DC_OFST_10_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_11_C 0xC02C +#define FPGA_DC_OFST_11_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_12_C 0xC030 +#define FPGA_DC_OFST_12_C_M 0xFFFFFFFF +#define FPGA_DC_OFST_13_C 0xC034 +#define FPGA_DC_OFST_13_C_M 0xFFFFFFFF +#define INV_TIASHRINK_C 0xC038 +#define INV_TIASHRINK_C_M 0x1 +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.c b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.c new file mode 100644 index 0000000..52aaee4 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.c @@ -0,0 +1,333 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "../halbb_precomp.h" +#include "halbb_hwimg_raw_data_8852b.h" +#include "halbb_hwimg_raw_data_8852b_gain.h" + +#ifdef BB_8852B_SUPPORT + +bool halbb_sel_headline_8852b(struct bb_info *bb, u32 *array, u32 array_len, + u8 *headline_size, u8 *headline_idx) +{ + bool case_match = false; + u32 cut_drv = (u32)bb->hal_com->cv; + u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type; + u32 cut_para = 0, rfe_para = 0; + u32 compare_target = 0; + u32 cut_max = 0; + u32 i = 0; + + *headline_idx = 0; + *headline_size = 0; + + if (bb->bb_dbg_i.cr_dbg_mode_en) { + rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg; + cut_drv = bb->bb_dbg_i.cut_curr_dbg; + } + + BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n", + rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en); + + while ((i + 1) < array_len) { + if ((array[i] >> 28) != 0xf) { + *headline_size = (u8)i; + break; + } + BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n", + i, array[i], i+1, array[i+1]); + i += 2; + } + + BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i); + + if (i == 0) + return true; + + /*case_idx:1 {RFE:Match, CV:Match}*/ + compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff); + BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CV:Match}\n"); + for (i = 0; i < *headline_size; i += 2) { + if ((array[i] & 0x0fffffff) == compare_target) { + *headline_idx = (u8)(i >> 1); + return true; + } + } + BB_DBG(bb, DBG_INIT, "\t fail\n"); + + /*case_idx:2 {RFE:Match, CV:Dont care}*/ + compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff); + BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CV:Dont_Care}\n"); + for (i = 0; i < *headline_size; i += 2) { + if ((array[i] & 0x0fffffff) == compare_target) { + *headline_idx = (u8)(i >> 1); + return true; + } + } + BB_DBG(bb, DBG_INIT, "\t fail\n"); + + /*case_idx:3 {RFE:Match, CV:Max_in_Table}*/ + BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CV:Max_in_Table}\n"); + for (i = 0; i < *headline_size; i += 2) { + rfe_para = (array[i] & 0x00ff0000) >> 16; + cut_para = array[i] & 0x0ff; + if (rfe_para == rfe_drv) { + if (cut_para > cut_max) { + cut_max = cut_para; + *headline_idx = (u8)(i >> 1); + BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max); + case_match = true; + } + } + } + if (case_match) { + return true; + } + BB_DBG(bb, DBG_INIT, "\t fail\n"); + + /*case_idx:4 {RFE:Dont Care, CV:Max_in_Table}*/ + BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CV:Max_in_Table}\n"); + for (i = 0; i < *headline_size; i += 2) { + rfe_para = (array[i] & 0x00ff0000) >> 16; + cut_para = array[i] & 0x0ff; + if (rfe_para == DONT_CARE_8852B) { + if (cut_para >= cut_max) { + cut_max = cut_para; + *headline_idx = (u8)(i >> 1); + BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max); + case_match = true; + } + } + } + if (case_match) { + return true; + } + BB_DBG(bb, DBG_INIT, "\t fail\n"); + + /*case_idx:5 {RFE:Not_Match, CV:Not_Match}*/ + BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CV:Not_Match}\n"); + BB_DBG(bb, DBG_INIT, "\t all fail\n"); + return false; +} + +void halbb_flag_2_default_8852b(bool *is_matched, bool *find_target) +{ + *is_matched = true; + *find_target = false; +} + +bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder, + u32 folder_len, u32 *folder_array, + enum phl_phy_idx phy_idx) +{ + bool is_matched, find_target; + u32 cfg_target = 0, cfg_para = 0; + u32 i = 0; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u8 h_size = 0; + u8 h_idx = 0; + + BB_DBG(bb, DBG_INIT, "===> %s\n", __func__); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_phy_reg) / sizeof(u32); + array = (u32 *)array_mp_8852b_phy_reg; + } + + BB_DBG(bb, DBG_INIT, "BBCR_form_folder=%d, len=%d, phy_idx=%d\n", + is_form_folder, array_len, phy_idx); + + if (!halbb_sel_headline_8852b(bb, array, array_len, &h_size, &h_idx)) { + BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__); + return false; + } + BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx); + + if (h_size != 0) { + cfg_target = array[h_idx << 1] & 0x0fffffff; + } + + i += h_size; + + BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target); + BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]); + + halbb_flag_2_default_8852b(&is_matched, &find_target); + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + i += 2; + + switch (v1 >> 28) { + case IF_8852B: + case ELSE_IF_8852B: + cfg_para = v1 & 0x0fffffff; + BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n", + (cfg_para & 0xff0000) >> 16, cfg_para & 0xff); + break; + case ELSE_8852B: + BB_DBG(bb, DBG_INIT, "*else\n"); + is_matched = false; + if (!find_target) { + BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]); + return false; + } + break; + case END_8852B: + BB_DBG(bb, DBG_INIT, "*endif\n"); + halbb_flag_2_default_8852b(&is_matched, &find_target); + break; + case CHK_8852B: + /*Check this para meets driver's requirement or not*/ + if (find_target) { + BB_DBG(bb, DBG_INIT, "\t skip\n"); + is_matched = false; + break; + } + + if (cfg_para == cfg_target) { + is_matched = true; + find_target = true; + } else { + is_matched = false; + find_target = false; + } + BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched); + break; + default: + if (is_matched) + halbb_cfg_bb_phy_8852b(bb, v1, v2, phy_idx); + break; + } + } + BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n"); + return true; +} + +bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder, + u32 folder_len, u32 *folder_array) +{ + bool is_matched, find_target; + u32 cfg_target = 0, cfg_para = 0; + u32 i = 0; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u8 h_size = 0; + u8 h_idx = 0; + + BB_DBG(bb, DBG_INIT, "===> %s\n", __func__); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_phy_reg_gain) / sizeof(u32); + array = (u32 *)array_mp_8852b_phy_reg_gain; + } + + BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n", + is_form_folder, array_len); + + if (!halbb_sel_headline_8852b(bb, array, array_len, &h_size, &h_idx)) { + BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__); + return false; + } + BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx); + + if (h_size != 0) { + cfg_target = array[h_idx << 1] & 0x0fffffff; + } + + i += h_size; + + BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target); + BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]); + + halbb_flag_2_default_8852b(&is_matched, &find_target); + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + i += 2; + + switch (v1 >> 28) { + case IF_8852B: + case ELSE_IF_8852B: + cfg_para = v1 & 0x0fffffff; + BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n", + (cfg_para & 0xff0000) >> 16, cfg_para & 0xff); + break; + case ELSE_8852B: + BB_DBG(bb, DBG_INIT, "*else\n"); + is_matched = false; + if (!find_target) { + BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]); + return false; + } + break; + case END_8852B: + BB_DBG(bb, DBG_INIT, "*endif\n"); + halbb_flag_2_default_8852b(&is_matched, &find_target); + break; + case CHK_8852B: + /*Check this para meets driver's requirement or not*/ + if (find_target) { + BB_DBG(bb, DBG_INIT, "\t skip\n"); + is_matched = false; + break; + } + + if (cfg_para == cfg_target) { + is_matched = true; + find_target = true; + } else { + is_matched = false; + find_target = false; + } + BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched); + break; + default: + if (is_matched) + halbb_cfg_bb_gain_8852b(bb, v1, v2); + break; + } + } + BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n"); + return true; +} + +u32 +halbb_get_8852b_phy_reg_ver(void) +{ + return (u32)BB_REG_RELEASE_VERSION_8852B; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.h new file mode 100644 index 0000000..46c01bf --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_HW_IMG_8852B_H_ +#define _HALBB_HW_IMG_8852B_H_ + + + +/****************************************************************************** + * phy_reg.TXT + ******************************************************************************/ +#define DONT_CARE_8852B 0xff + +#define IF_8852B 0x8 +#define ELSE_IF_8852B 0x9 +#define ELSE_8852B 0xa +#define END_8852B 0xb +#define CHK_8852B 0x4 + +bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder, + u32 folder_len, u32 *folder_array, + enum phl_phy_idx phy_idx); +bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder, + u32 folder_len, u32 *folder_array); +u32 halbb_get_8852b_phy_reg_ver(void); + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b.h new file mode 100644 index 0000000..32417e4 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b.h @@ -0,0 +1,1128 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 2.0.1.2*/ +#ifndef _HALBB_HWIMG_RAW_DATA_8852B_H +#define _HALBB_HWIMG_RAW_DATA_8852B_H + + +/****************************************************************************** + * phy_reg.TXT + ******************************************************************************/ + +const u32 array_mp_8852b_phy_reg[] = { + 0x704, 0x601E0100, + 0x4000, 0x00000000, + 0x4004, 0xCA014000, + 0x4008, 0xC751D4F0, + 0x400C, 0x44511475, + 0x4010, 0x00000000, + 0x4014, 0x00000000, + 0x4018, 0x4F4C084B, + 0x401C, 0x084A4E52, + 0x4020, 0x4D504E4B, + 0x4024, 0x4F4C0849, + 0x4028, 0x08484C50, + 0x402C, 0x4C50504C, + 0x4030, 0x5454084A, + 0x4034, 0x084B5654, + 0x4038, 0x6A6C605A, + 0x403C, 0x4C4C084C, + 0x4040, 0x084B4E4D, + 0x4044, 0x4E4C4B4B, + 0x4048, 0x4B4B084A, + 0x404C, 0x084A4E4C, + 0x4050, 0x514F4C4A, + 0x4054, 0x524E084A, + 0x4058, 0x084A5154, + 0x405C, 0x53555554, + 0x4060, 0x45450845, + 0x4064, 0x08454144, + 0x4068, 0x40434445, + 0x406C, 0x44450845, + 0x4070, 0x08444043, + 0x4074, 0x42434444, + 0x4078, 0x46450844, + 0x407C, 0x08444843, + 0x4080, 0x4B4E4A47, + 0x4084, 0x4F4C084B, + 0x4088, 0x084A4E52, + 0x408C, 0x4D504E4B, + 0x4090, 0x4F4C0849, + 0x4094, 0x08484C50, + 0x4098, 0x4C50504C, + 0x409C, 0x5454084A, + 0x40A0, 0x084B5654, + 0x40A4, 0x6A6C605A, + 0x40A8, 0x4C4C084C, + 0x40AC, 0x084B4E4D, + 0x40B0, 0x4E4C4B4B, + 0x40B4, 0x4B4B084A, + 0x40B8, 0x084A4E4C, + 0x40BC, 0x514F4C4A, + 0x40C0, 0x524E084A, + 0x40C4, 0x084A5154, + 0x40C8, 0x53555554, + 0x40CC, 0x45450845, + 0x40D0, 0x08454144, + 0x40D4, 0x40434445, + 0x40D8, 0x44450845, + 0x40DC, 0x08444043, + 0x40E0, 0x42434444, + 0x40E4, 0x46450844, + 0x40E8, 0x08444843, + 0x40EC, 0x4B4E4A47, + 0x40F0, 0x00000000, + 0x40F4, 0x00000006, + 0x40F8, 0x00000000, + 0x40FC, 0x8C30C30C, + 0x4100, 0x4C30C30C, + 0x4104, 0x0C30C30C, + 0x4108, 0x0C30C30C, + 0x410C, 0x0C30C30C, + 0x4110, 0x0C30C30C, + 0x4114, 0x28A28A28, + 0x4118, 0x28A28A28, + 0x411C, 0x28A28A28, + 0x4120, 0x28A28A28, + 0x4124, 0x28A28A28, + 0x4128, 0x28A28A28, + 0x412C, 0x06666666, + 0x4130, 0x33333333, + 0x4134, 0x33333333, + 0x4138, 0x33333333, + 0x413C, 0x00000031, + 0x4140, 0x5100600A, + 0x4144, 0x18363113, + 0x4148, 0x1D976DDC, + 0x414C, 0x1C072DD7, + 0x4150, 0x1127CDF4, + 0x4154, 0x1E37BDF1, + 0x4158, 0x1FB7F1D6, + 0x415C, 0x1EA7DDF9, + 0x4160, 0x1FE445DD, + 0x4164, 0x1F97F1FE, + 0x4168, 0x1FF781ED, + 0x416C, 0x1FA7F5FE, + 0x4170, 0x1E07B913, + 0x4174, 0x1FD7FDFF, + 0x4178, 0x1E17B9FA, + 0x417C, 0x19A66914, + 0x4180, 0x10F65598, + 0x4184, 0x14A5A111, + 0x4188, 0x1D3765DB, + 0x418C, 0x17C685CA, + 0x4190, 0x1107C5F3, + 0x4194, 0x1B5785EB, + 0x4198, 0x1F97ED8F, + 0x419C, 0x1BC7A5F3, + 0x41A0, 0x1FE43595, + 0x41A4, 0x1EB7D9FC, + 0x41A8, 0x1FE65DBE, + 0x41AC, 0x1EC7D9FC, + 0x41B0, 0x1976FCFF, + 0x41B4, 0x1F77F5FF, + 0x41B8, 0x1976FDEC, + 0x41BC, 0x198664EF, + 0x41C0, 0x11062D93, + 0x41C4, 0x10C4E910, + 0x41C8, 0x1CA759DB, + 0x41CC, 0x1335A9B5, + 0x41D0, 0x1097B9F3, + 0x41D4, 0x17B72DE1, + 0x41D8, 0x1F67ED42, + 0x41DC, 0x18074DE9, + 0x41E0, 0x1FD40547, + 0x41E4, 0x1D57ADF9, + 0x41E8, 0x1FE52182, + 0x41EC, 0x1D67B1F9, + 0x41F0, 0x14860CE1, + 0x41F4, 0x1EC7E9FE, + 0x41F8, 0x14860DD6, + 0x41FC, 0x195664C7, + 0x4200, 0x0005E58A, + 0x4204, 0x00000000, + 0x4208, 0x00000000, + 0x420C, 0x7A000000, + 0x4210, 0x0F9F3D7A, + 0x4214, 0x0040817C, + 0x4218, 0x00E10204, + 0x421C, 0x227D94CD, + 0x4220, 0x08028A28, + 0x4224, 0x00000210, + 0x4228, 0x04688000, + 0x4A48, 0x00000002, + 0x422C, 0x0060B002, + 0x4230, 0x9A8249A8, + 0x4234, 0x26A1469E, + 0x4238, 0x2099A824, + 0x423C, 0x2359461C, + 0x4240, 0x1631A675, + 0x4244, 0x2C6B1D63, + 0x4248, 0x0000000E, + 0x424C, 0x00000001, + 0x4250, 0x00000001, + 0x4254, 0x00000000, + 0x4258, 0x00000000, + 0x425C, 0x00000000, + 0x4260, 0x0020000C, + 0x4264, 0x00000000, + 0x4268, 0x00000000, + 0x426C, 0x0418317C, + 0x4270, 0x2B33135C, + 0x4274, 0x00000002, + 0x4278, 0x00000000, + 0x427C, 0x00000000, + 0x4280, 0x00000000, + 0x4284, 0x00000000, + 0x4288, 0x00000000, + 0x428C, 0x00000000, + 0x4290, 0x00000000, + 0x4294, 0x00000000, + 0x4298, 0x00000000, + 0x429C, 0x84026000, + 0x42A0, 0x0051AC20, + 0x4A24, 0x0010C040, + 0x42A4, 0x02024008, + 0x42A8, 0x00000000, + 0x42AC, 0x00000000, + 0x42B0, 0x22CE803C, + 0x42B4, 0x32000000, + 0x42B8, 0x996FD67D, + 0x42BC, 0xBD67D67D, + 0x42C0, 0x7D67D65B, + 0x42C4, 0x28029F59, + 0x42C8, 0x00280280, + 0x42CC, 0x00000000, + 0x42D0, 0x00000000, + 0x42D4, 0x00000003, + 0x42D8, 0x00000001, + 0x42DC, 0x61861800, + 0x42E0, 0x830C30C3, + 0x42E4, 0xC30C30C3, + 0x42E8, 0x830C30C3, + 0x42EC, 0x451450C3, + 0x42F0, 0x05145145, + 0x42F4, 0x05145145, + 0x42F8, 0x05145145, + 0x42FC, 0x0F0C3145, + 0x4300, 0x030C30CF, + 0x4304, 0x030C30C3, + 0x4308, 0x030CF3C3, + 0x430C, 0x030C30C3, + 0x4310, 0x0F3CF3C3, + 0x4314, 0x0F3CF3CF, + 0x4318, 0x0F3CF3CF, + 0x431C, 0x0F3CF3CF, + 0x4320, 0x0F3CF3CF, + 0x4324, 0x030C10C3, + 0x4328, 0x051430C3, + 0x432C, 0x051490CB, + 0x4330, 0x030CD151, + 0x4334, 0x050C50C7, + 0x4338, 0x051492CB, + 0x433C, 0x05145145, + 0x4340, 0x05145145, + 0x4344, 0x05145145, + 0x4348, 0x05145145, + 0x434C, 0x090CD3CF, + 0x4350, 0x071491C5, + 0x4354, 0x073CF143, + 0x4358, 0x071431C3, + 0x435C, 0x0F3CF1C5, + 0x4360, 0x0F3CF3CF, + 0x4364, 0x0F3CF3CF, + 0x4368, 0x0F3CF3CF, + 0x436C, 0x0F3CF3CF, + 0x4370, 0x090C91CF, + 0x4374, 0x11243143, + 0x4378, 0x9777A777, + 0x437C, 0xBB7BAC95, + 0x4380, 0xB667B889, + 0x4384, 0x7B9B8899, + 0x4388, 0x7A5567C8, + 0x438C, 0x2278CCCC, + 0x4390, 0x7C222222, + 0x4394, 0x0000069B, + 0x4398, 0x001CCCCC, + 0x4AAC, 0xCCCCC88C, + 0x4AB0, 0x0000AACC, + 0x439C, 0x00000000, + 0x43A0, 0x00000008, + 0x43A4, 0x00000000, + 0x43A8, 0x00000000, + 0x43AC, 0x00000000, + 0x43B0, 0x10000000, + 0x43B4, 0x00401001, + 0x43B8, 0x00061003, + 0x43BC, 0x000024D8, + 0x43C0, 0x00000000, + 0x43C4, 0x10000020, + 0x43C8, 0x20000200, + 0x43CC, 0x00000000, + 0x43D0, 0x04000000, + 0x43D4, 0x44000100, + 0x43D8, 0x60804060, + 0x43DC, 0x44204210, + 0x43E0, 0x82108082, + 0x43E4, 0x82108402, + 0x43E8, 0xC8082108, + 0x43EC, 0xC8202084, + 0x43F0, 0x44208208, + 0x43F4, 0x84108204, + 0x43F8, 0xD0108104, + 0x43FC, 0xF8210108, + 0x4400, 0x6431E930, + 0x4404, 0x02309468, + 0x4408, 0x10C61C22, + 0x440C, 0x02109469, + 0x4410, 0x10C61C22, + 0x4414, 0x00041049, + 0x4A4C, 0x00060581, + 0x4418, 0x00000000, + 0x441C, 0x00000000, + 0x4420, 0x6C000000, + 0x4424, 0xB0200020, + 0x4428, 0x00001FF0, + 0x442C, 0x00000000, + 0x4430, 0x00000000, + 0x4434, 0x00000000, + 0x4438, 0x00000000, + 0x443C, 0x190642D0, + 0x4440, 0xA80668A0, + 0x4444, 0x60900820, + 0x4448, 0x9F28518C, + 0x444C, 0x32488A62, + 0x4450, 0x9C6E36DC, + 0x4454, 0x0000F52B, + 0x4458, 0x00000000, + 0x445C, 0x4801442E, + 0x4460, 0x0051A0B8, + 0x4464, 0x00000000, + 0x4468, 0x00000000, + 0x446C, 0x00000000, + 0x4470, 0x00000000, + 0x4474, 0x00000000, + 0x4478, 0x00000000, + 0x447C, 0x00000000, + 0x4480, 0x2A0A6040, + 0x4484, 0x0A0A6829, + 0x4488, 0x00000004, + 0x448C, 0x00000000, + 0x4490, 0x80000000, + 0x4494, 0x13000000, + 0x4498, 0xE0000000, + 0x4AB4, 0x00000000, + 0x449C, 0x0000001E, + 0x44A0, 0x02B2C3A6, + 0x44A4, 0x00000400, + 0x44A8, 0x00000001, + 0x44AC, 0x000190C0, + 0x44B0, 0x00000000, + 0x44B4, 0x00000000, + 0x44B8, 0x00000000, + 0x44BC, 0x00000000, + 0x44C0, 0x00000000, + 0x44C4, 0x00000000, + 0x44C8, 0x00000000, + 0x44CC, 0x00000000, + 0x44D0, 0x00000000, + 0x44D4, 0x00000000, + 0x44D8, 0x00000000, + 0x44DC, 0x00000000, + 0x44E0, 0x00000000, + 0x44E4, 0x00000000, + 0x44E8, 0x00000000, + 0x44EC, 0x00000000, + 0x44F0, 0x00000000, + 0x44F4, 0x00000000, + 0x44F8, 0x00000000, + 0x44FC, 0x00000000, + 0x4500, 0x00000000, + 0x4504, 0x00000000, + 0x4508, 0x00000000, + 0x450C, 0x00000000, + 0x4510, 0x00000000, + 0x4514, 0x00000000, + 0x4518, 0x00000000, + 0x451C, 0x00000000, + 0x4520, 0x00000000, + 0x4524, 0x00000000, + 0x4528, 0x00000000, + 0x452C, 0x00000000, + 0x4530, 0x4E830171, + 0x4534, 0x00000870, + 0x4538, 0x000000FF, + 0x453C, 0x00000000, + 0x4540, 0x00000000, + 0x4544, 0x00000000, + 0x4548, 0x00000000, + 0x454C, 0x00000000, + 0x4550, 0x00000000, + 0x4554, 0x00000000, + 0x4558, 0x00000000, + 0x455C, 0x00000000, + 0x4560, 0x40000000, + 0x4564, 0x40000000, + 0x4568, 0x00000000, + 0x456C, 0x20000000, + 0x4570, 0x04F040BB, + 0x4574, 0x000E53FF, + 0x4578, 0x000205CB, + 0x457C, 0x00200000, + 0x4580, 0x00000040, + 0x4584, 0x00000000, + 0x4588, 0x00000017, + 0x458C, 0x30000000, + 0x4590, 0x00000000, + 0x4594, 0x00000000, + 0x4598, 0x00000001, + 0x459C, 0x0003FE00, + 0x45A0, 0x00000086, + 0x45A4, 0x00000000, + 0x45A8, 0xC00001C0, + 0x45AC, 0x78038000, + 0x45B0, 0x8000004A, + 0x45B4, 0x04094800, + 0x45B8, 0x00280002, + 0x45BC, 0x06748790, + 0x45C0, 0x80000000, + 0x45C4, 0x00000000, + 0x45C8, 0x00000000, + 0x45CC, 0x00558670, + 0x45D0, 0x002883F0, + 0x45D4, 0x00090120, + 0x45D8, 0x00000000, + 0x45E0, 0xA3A6D3C4, + 0x45E4, 0xAB27B126, + 0x45E8, 0x00006778, + 0x45F4, 0x000001B5, + 0x45EC, 0x11110F0A, + 0x45F0, 0x00000003, + 0x4A0C, 0x0000000A, + 0x45F8, 0x0058BC3F, + 0x45FC, 0x00000003, + 0x462C, 0x00000020, + 0x4600, 0x000003D9, + 0x45F0, 0x00000004, + 0x4604, 0x002B1CB0, + 0x4A50, 0xC0000000, + 0x4A54, 0x00001000, + 0x4A58, 0x00000000, + 0x4A18, 0x00000024, + 0x4608, 0x00000001, + 0x460C, 0x00000000, + 0x4A10, 0x00000001, + 0x4610, 0x00000001, + 0x4614, 0x16E5298F, + 0x4618, 0x18C6294A, + 0x461C, 0x0E06318A, + 0x4620, 0x0E539CE5, + 0x4624, 0x00019287, + 0x4A14, 0x000000BF, + 0x4628, 0x00000001, + 0x4630, 0x000001AA, + 0x4A18, 0x00001900, + 0x4A1C, 0x000002A6, + 0x4634, 0x000000A3, + 0x4A20, 0x00000086, + 0x4638, 0x01986456, + 0x49F8, 0x00000000, + 0x463C, 0x00000000, + 0x4640, 0x00000000, + 0x4644, 0x00C8CC00, + 0x4648, 0xC400B6B6, + 0x464C, 0xDC400FC0, + 0x4A8C, 0x00000110, + 0x4650, 0x08882550, + 0x4654, 0x08CC2660, + 0x4658, 0x09102660, + 0x465C, 0x00000154, + 0x45DC, 0xC39E38E8, + 0x4660, 0x452607E6, + 0x4664, 0x6750DC65, + 0x4668, 0xF3F0F1ED, + 0x466C, 0x30141506, + 0x4670, 0x2C2B2B2B, + 0x4674, 0x2C2C2C2C, + 0x4678, 0xDDB738E8, + 0x467C, 0x543618FB, + 0x4680, 0x4F31DC6F, + 0x4684, 0xFBEBDA00, + 0x4688, 0x1A10FF04, + 0x468C, 0x282A3000, + 0x4690, 0x2A29292A, + 0x4694, 0x04FA2A2A, + 0x4698, 0xEE0F04D1, + 0x469C, 0x99E91436, + 0x46A0, 0x0701E79E, + 0x46A4, 0x08D77CFF, + 0x46A8, 0x2212FF14, + 0x46AC, 0x60322437, + 0x46B0, 0x63666666, + 0x46B4, 0x35374425, + 0x46B8, 0x35883042, + 0x46BC, 0x5177C252, + 0x4720, 0x7FFFFD63, + 0x4724, 0xB58D11FF, + 0x4728, 0x07FFFFFF, + 0x472C, 0x0E7893B6, + 0x4730, 0xE0391201, + 0x4734, 0x00000020, + 0x4738, 0x8325C500, + 0x473C, 0x00000B7F, + 0x46C0, 0x00000000, + 0x46C4, 0x00000000, + 0x46C8, 0x00000219, + 0x46CC, 0x00000000, + 0x46D0, 0x00000000, + 0x46D4, 0x00000001, + 0x46D8, 0x00000001, + 0x46DC, 0x00000000, + 0x46E0, 0x00000000, + 0x46E4, 0x00000151, + 0x46E8, 0x00000498, + 0x46EC, 0x00000498, + 0x46F0, 0x00000000, + 0x46F4, 0x00000000, + 0x46F8, 0x00001146, + 0x46FC, 0x00000000, + 0x4700, 0x00000000, + 0x4704, 0x00C8CC00, + 0x4708, 0xC400B6B6, + 0x470C, 0xDC400FC0, + 0x4A90, 0x00000110, + 0x4710, 0x08882550, + 0x4714, 0x08CC2660, + 0x4718, 0x09102660, + 0x471C, 0x00000154, + 0x4740, 0xC69F38E8, + 0x4744, 0x462709E9, + 0x4748, 0x6750DC67, + 0x474C, 0xF3F0F1ED, + 0x4750, 0x30141506, + 0x4754, 0x2C2B2B2B, + 0x4758, 0x2C2C2C2C, + 0x475C, 0xE0B738E8, + 0x4760, 0x52381BFE, + 0x4764, 0x5031DC6C, + 0x4768, 0xFBEBDA00, + 0x476C, 0x1A10FF04, + 0x4770, 0x282A3000, + 0x4774, 0x2A29292A, + 0x4778, 0x04FA2A2A, + 0x477C, 0xEE0F04D1, + 0x49F0, 0x99E91436, + 0x49F4, 0x0701E79E, + 0x49FC, 0x08D77CFF, + 0x4A5C, 0x2212FF14, + 0x4A60, 0x60322437, + 0x4A64, 0x63666666, + 0x4A68, 0x35374425, + 0x4A6C, 0x35883042, + 0x4A70, 0x5177C252, + 0x4A74, 0x7FFFFD63, + 0x4A78, 0xB58D11FF, + 0x4A7C, 0x07FFFFFF, + 0x4A80, 0x0E7893B6, + 0x4A9C, 0xE0391201, + 0x4AA0, 0x00000020, + 0x4AA4, 0x8325C500, + 0x4AA8, 0x00000B7F, + 0x4780, 0x00000000, + 0x4784, 0x00000000, + 0x4788, 0x00000219, + 0x478C, 0x00000000, + 0x4790, 0x00000000, + 0x4794, 0x00000001, + 0x4798, 0x00000001, + 0x479C, 0x00000000, + 0x47A0, 0x00000000, + 0x47A4, 0x00000151, + 0x47A8, 0x00000498, + 0x47AC, 0x00000498, + 0x47B0, 0x00000000, + 0x47B4, 0x00000000, + 0x47B8, 0x00001146, + 0x47BC, 0x00000002, + 0x47C0, 0x00000002, + 0x47C4, 0x00000000, + 0x47C8, 0xA32103FE, + 0x47CC, 0xB20A5328, + 0x47D0, 0xC686314F, + 0x47D4, 0x000005D7, + 0x47D8, 0x009B902A, + 0x47DC, 0x009B902A, + 0x47E0, 0x98682C18, + 0x47E4, 0x6308C4C1, + 0x47E8, 0x6248C631, + 0x47EC, 0x922A8253, + 0x47F0, 0x00000005, + 0x47F4, 0x00001759, + 0x47F8, 0x4BB02000, + 0x47FC, 0x831408BE, + 0x4A84, 0x000000E9, + 0x4800, 0x9ABBCACB, + 0x4804, 0x56767578, + 0x4808, 0xBCCBBB13, + 0x480C, 0x7889989B, + 0x4810, 0xBBB0F455, + 0x4814, 0x777BBBBB, + 0x4818, 0x15277777, + 0x481C, 0x27039CE9, + 0x4820, 0x42424432, + 0x4824, 0x36058342, + 0x4828, 0x00000006, + 0x482C, 0x00000005, + 0x4830, 0x00000005, + 0x4834, 0xC7013016, + 0x4838, 0x84413016, + 0x483C, 0x84413016, + 0x4840, 0x8C413016, + 0x4844, 0x8C40B028, + 0x4848, 0x3140B028, + 0x484C, 0x2940B028, + 0x4850, 0x8440B028, + 0x4854, 0x2318C610, + 0x4858, 0x45344753, + 0x485C, 0x236A6A88, + 0x4860, 0xAC8DF814, + 0x4864, 0x08877ACB, + 0x4868, 0x000107AA, + 0x4A94, 0x00000000, + 0x486C, 0xBCEB4A14, + 0x4870, 0x000A3A4A, + 0x4874, 0xBCEB4A14, + 0x4878, 0x000A3A4A, + 0x487C, 0xBCBDBD85, + 0x4880, 0x0CABB99A, + 0x4884, 0x38384242, + 0x4888, 0x0086102E, + 0x488C, 0xCA24C82A, + 0x4890, 0x00008A62, + 0x4894, 0x00000008, + 0x4898, 0x009B902A, + 0x489C, 0x009B902A, + 0x48A0, 0x98682C18, + 0x48A4, 0x6308C4C1, + 0x48A8, 0x6248C631, + 0x48AC, 0x922A8253, + 0x48B0, 0x00000005, + 0x48B4, 0x00001759, + 0x48B8, 0x4BA02000, + 0x48BC, 0x831408BE, + 0x4A88, 0x000000E9, + 0x48C0, 0x9898A8BB, + 0x48C4, 0x54535368, + 0x48C8, 0x99999B13, + 0x48CC, 0x55555899, + 0x48D0, 0xBBB07453, + 0x48D4, 0x777BBBBB, + 0x48D8, 0x15277777, + 0x48DC, 0x27039CE9, + 0x48E0, 0x31413432, + 0x48E4, 0x36058342, + 0x48E8, 0x00000006, + 0x48EC, 0x00000005, + 0x48F0, 0x00000005, + 0x48F4, 0xC7013016, + 0x48F8, 0x84413016, + 0x48FC, 0x84413016, + 0x4900, 0x8C413016, + 0x4904, 0x8C40B028, + 0x4908, 0x3140B028, + 0x490C, 0x2940B028, + 0x4910, 0x8440B028, + 0x4914, 0x2318C610, + 0x4918, 0x45334753, + 0x491C, 0x236A6A88, + 0x4920, 0xAC8DF814, + 0x4924, 0x08877ACB, + 0x4928, 0x000007AA, + 0x4A98, 0x00000000, + 0x492C, 0xBCEB4A14, + 0x4930, 0x000A3A4A, + 0x4934, 0xBCEB4A14, + 0x4938, 0x000A3A4A, + 0x493C, 0x9A8A8A85, + 0x4940, 0x0CA3B99A, + 0x4944, 0x38384242, + 0x4948, 0x8086102E, + 0x494C, 0xCA24C82A, + 0x4950, 0x00008A62, + 0x4954, 0x00000008, + 0x4958, 0x80040000, + 0x495C, 0x80040000, + 0x4960, 0xFE800000, + 0x4964, 0x834C0000, + 0x4968, 0x00000000, + 0x496C, 0x00000000, + 0x4970, 0x00000000, + 0x4974, 0x00000000, + 0x4978, 0x00000000, + 0x497C, 0x00000000, + 0x4980, 0x40000000, + 0x4984, 0x00000000, + 0x4988, 0x00000000, + 0x498C, 0x00000000, + 0x4990, 0x00000000, + 0x4994, 0x04065800, + 0x4998, 0x02004080, + 0x499C, 0x0E1E3E05, + 0x49A0, 0x0A163068, + 0x49A4, 0x00206040, + 0x49A8, 0x02020202, + 0x49AC, 0x00002020, + 0x49B0, 0xF8F8F418, + 0x49B4, 0x28E8F8F8, + 0x49B8, 0x280808E8, + 0x4A00, 0xF8F8FA00, + 0x4A04, 0xFAFAFAF8, + 0x4A08, 0xFAFAFAFA, + 0x4A28, 0xFAFAFAFA, + 0x4A2C, 0xFAFAFAFA, + 0x4A30, 0xFAFAFAFA, + 0x4A34, 0xFAFAFAFA, + 0x4A38, 0xFAFAFAFA, + 0x4A3C, 0xFAFAFAFA, + 0x4A40, 0xFAFAFAFA, + 0x4A44, 0x0000FAFA, + 0x49BC, 0x00000000, + 0x49C0, 0x800CD62D, + 0x49C4, 0x00000103, + 0x49C8, 0x00000000, + 0x49CC, 0x00000000, + 0x49D0, 0x00000000, + 0x49D4, 0x00000000, + 0x49D8, 0x00000000, + 0x49DC, 0x00000000, + 0x49E0, 0x00000000, + 0x49E4, 0x00000000, + 0x49E8, 0x00000000, + 0x49EC, 0x00000000, + 0x994, 0x00000010, + 0x904, 0x00000005, + 0xC3C, 0x2840E1BF, + 0xC40, 0x00000000, + 0xC44, 0x00000007, + 0xC48, 0x410E4000, + 0xC54, 0x1EE14368, + 0xC58, 0x41000000, + 0x730, 0x00000002, + 0xC60, 0x017FFFF2, + 0xC64, 0x0010A130, + 0xC68, 0x10000050, + 0xC6C, 0x10001021, + 0x708, 0x00000000, + 0x884, 0x0043F01D, + 0x704, 0x601E0100, + 0x710, 0xEF810000, + 0x704, 0x601E0100, + 0xD40, 0xF64FA0F7, + 0xD44, 0x0400063F, + 0xD48, 0x0003FF7F, + 0xD4C, 0x00000000, + 0xD50, 0xF64FA0F7, + 0xD54, 0x04100437, + 0xD58, 0x0000FF7F, + 0xD5C, 0x00000000, + 0xD60, 0x00000000, + 0xD64, 0x00000000, + 0xD70, 0x00000015, + 0xD90, 0x000003FF, + 0xD94, 0x00000000, + 0xD98, 0x0000003F, + 0xD9C, 0x00000000, + 0xDA0, 0x000003FE, + 0xDA4, 0x00000000, + 0xDA8, 0x0000003F, + 0xDAC, 0x00000000, + 0xD00, 0x77777777, + 0xD04, 0xBBBBBBBB, + 0xD08, 0xBBBBBBBB, + 0xD0C, 0x00000070, + 0xD10, 0x20110900, + 0xD10, 0x20110FFF, + 0xD78, 0x00000001, + 0xD7C, 0x001D050E, + 0xD84, 0x00004207, + 0xD18, 0x50209900, + 0xD80, 0x00804100, + 0x718, 0x1333233F, + 0x604, 0x041E1E1E, + 0x714, 0x00010000, + 0x586C, 0x000000F0, + 0x586C, 0x000000E0, + 0x586C, 0x000000D0, + 0x586C, 0x000000C0, + 0x586C, 0x000000B0, + 0x586C, 0x000000A0, + 0x586C, 0x00000090, + 0x586C, 0x00000080, + 0x586C, 0x00000070, + 0x586C, 0x00000060, + 0x586C, 0x00000050, + 0x586C, 0x00000040, + 0x586C, 0x00000030, + 0x586C, 0x00000020, + 0x586C, 0x00000010, + 0x586C, 0x00000000, + 0x786C, 0x000000F0, + 0x786C, 0x000000E0, + 0x786C, 0x000000D0, + 0x786C, 0x000000C0, + 0x786C, 0x000000B0, + 0x786C, 0x000000A0, + 0x786C, 0x00000090, + 0x786C, 0x00000080, + 0x786C, 0x00000070, + 0x786C, 0x00000060, + 0x786C, 0x00000050, + 0x786C, 0x00000040, + 0x786C, 0x00000030, + 0x786C, 0x00000020, + 0x786C, 0x00000010, + 0x786C, 0x00000000, + 0xC0D4, 0x4486888C, + 0xC0D8, 0xC6BA10E1, + 0xC0DC, 0x30C52868, + 0xC0E0, 0x05008128, + 0xC0E4, 0x0000A72B, + 0xC1D4, 0x4486888C, + 0xC1D8, 0xC6BA10E1, + 0xC1DC, 0x30C52868, + 0xC1E0, 0x05008128, + 0xC1E4, 0x0000A72B, + 0xC0EC, 0x00000000, + 0xC0E4, 0x0000272B, + 0xC1EC, 0x00000000, + 0xC1E4, 0x0000272B, + 0x334, 0xFFFFFFFF, + 0x33C, 0x55000000, + 0x340, 0x00005555, + 0x724, 0x00111200, + 0x5868, 0xA9550000, + 0x5870, 0x33221100, + 0x5874, 0x77665544, + 0x5878, 0xBBAA9988, + 0x587C, 0xFFEEDDCC, + 0x5880, 0x76543210, + 0x5884, 0xFEDCBA98, + 0x5888, 0x00000000, + 0x588C, 0x00000000, + 0x5894, 0x00000008, + 0x7868, 0xA9550000, + 0x7870, 0x33221100, + 0x7874, 0x77665544, + 0x7878, 0xBBAA9988, + 0x787C, 0xFFEEDDCC, + 0x7880, 0x76543210, + 0x7884, 0xFEDCBA98, + 0x7888, 0x00000000, + 0x788C, 0x00000000, + 0x7894, 0x00000008, + 0x650, 0x00200888, + 0x710, 0xF3810000, + 0x020, 0x0000F381, + 0x024, 0x0000F381, + 0x000, 0xC580801E, + 0xC70, 0x00000400, + 0x980, 0x10002250, + 0x988, 0x3C3C4107, + 0x994, 0x00000010, + 0x2994, 0x00000010, + 0x000, 0x0580801F, + 0x240C, 0x00000000, + 0x640, 0x140A141E, + 0x640, 0x1414141E, + 0x640, 0x1414141E, + 0x644, 0x3414283C, + 0x644, 0x3425283C, + 0x644, 0x3426283C, + 0x2640, 0x140A141E, + 0x2640, 0x1414141E, + 0x2640, 0x1414141E, + 0x2644, 0x3414283C, + 0x2644, 0x3425283C, + 0x2644, 0x3425183C, + 0x2300, 0x02748790, + 0x2304, 0x00558670, + 0x2308, 0x002883F0, + 0x230C, 0x00090120, + 0x2310, 0x00000000, + 0x2314, 0x06000000, + 0x2318, 0x00000000, + 0x231C, 0x00000000, + 0x2320, 0x03020100, + 0x2324, 0x07060504, + 0x2328, 0x0B0A0908, + 0x232C, 0x0F0E0D0C, + 0x2330, 0x13121110, + 0x2334, 0x17161514, + 0x2338, 0x0C700022, + 0x233C, 0x0A0529D0, + 0x2340, 0x000529D0, + 0x2344, 0x0006318A, + 0x2348, 0xB7E6318A, + 0x234C, 0x80039CE7, + 0x2350, 0x80039CE7, + 0x2354, 0x0005298F, + 0x2358, 0x0015296E, + 0x235C, 0x0C07FC31, + 0x2360, 0x0219AAAE, + 0x2364, 0xE4F624C3, + 0x2368, 0x53626F15, + 0x236C, 0x48000000, + 0x2370, 0x48000000, + 0x2374, 0x07540000, + 0x2378, 0x202401B9, + 0x237C, 0x00F7000E, + 0x2380, 0x0F0A1111, + 0x2384, 0x30D9000F, + 0x2388, 0x0200EA02, + 0x238C, 0x003CB061, + 0x2390, 0x69C00000, + 0x2394, 0x00000000, + 0x2398, 0x000000F0, + 0x239C, 0x0001FFFF, + 0x23A0, 0x00C80064, + 0x23A4, 0x0190012C, + 0x23A8, 0x001917BE, + 0x23AC, 0x0B30880C, + 0x23B0, 0xB501CE00, + 0x23B4, 0xDD027C00, + 0x704, 0x601E0102, + 0x704, 0x601E0102, + 0x5864, 0x080801FF, + 0x7864, 0x080801FF, + 0xC60, 0x017FFFF3, + 0x58AC, 0x08000000, + 0x78AC, 0x08000000, + 0x8088, 0x007F0000, + 0x81A4, 0x003F3A00, + 0x81B4, 0x0100007F, + 0x81C0, 0x0060010B, + 0x81A0, 0x00000010, + 0x8138, 0x00000002, + 0x82A4, 0x003F3A00, + 0x82B4, 0x0100007F, + 0x82C0, 0x0060010B, + 0x82A0, 0x00000010, + 0x81A0, 0x00000010, + 0x8238, 0x00000002, + 0x8088, 0x00000000, + 0x8020, 0x00000000, + 0x8120, 0x00000000, + 0x8220, 0x00000000, + 0x8124, 0x00000F0F, + 0x8224, 0x00000F0F, + 0x5864, 0x180801FF, + 0x7864, 0x180801FF, + 0xC60, 0x017FFFF3, + 0xC70, 0x00000600, + 0xC70, 0x00000660, + 0x58AC, 0x08000000, + 0x78AC, 0x08000000, + 0x8120, 0x10000000, + 0x8120, 0x10030000, + 0x8124, 0x00000F0F, + 0x8124, 0x00000F0F, + 0x8224, 0x00000F0F, + 0x8224, 0x00000F0F, + 0x8220, 0x10000000, + 0x8220, 0x10030000, + 0x704, 0x601E0100, + 0x5864, 0x100801FF, + 0x7864, 0x100801FF, + 0x5864, 0x180801FF, + 0x7864, 0x180801FF, + 0x58D4, 0x7401FE00, + 0x78D4, 0x7401FE00, + 0x58F0, 0x400401FF, + 0x78F0, 0x400401FF, + 0x58F0, 0x400401FF, + 0x78F0, 0x400401FF, + 0x704, 0x601E0102, + 0xC7C, 0x0020BFE0, + 0x58C0, 0x00FE0000, + 0x58FC, 0x00000000, + 0x566C, 0x00000005, + 0x566C, 0x00001005, + 0x78C0, 0x00FE0000, + 0x78FC, 0x00000000, + 0x700, 0x00000030, + 0x704, 0x601E0102, + 0x704, 0x601E0100, + 0x704, 0x601E0502, + 0x20FC, 0x00000000, + 0x20F8, 0x00000000, + 0x20F0, 0x00000000, + 0x9C0, 0x00000001, + 0x9C0, 0x00000000, + 0x9C0, 0x00000001, + 0x9C0, 0x00000000, + 0x4AE8, 0x00000744, + 0x4AF0, 0x00000744, + 0x1010, 0x00000010, + 0x3010, 0x00000010, + 0x4AD4, 0x00000060, + 0x4AE0, 0x00000060, + 0x4AE4, 0x0079E99E, + 0x4AEC, 0x0079E99E, + 0x300, 0xF30CE31C, + 0x304, 0x13EF1F19, + 0x308, 0x0C0CF3F3, + 0x30C, 0x0C0C0C0C, + 0x310, 0x80496000, + 0x314, 0x0041E000, + 0x318, 0x20022042, + 0x31C, 0x20448009, + 0x320, 0x00010031, + 0x324, 0xE000E000, + 0x328, 0xE000E000, + 0x32C, 0xE000E000, + 0x12BC, 0x10104041, + 0x12C0, 0x14411111, + 0x32BC, 0x10104041, + 0x32C0, 0x14411111, + 0x010, 0x0005FFFF, + 0x028, 0x0000F381, + 0x02C, 0x0000F381, + 0x620, 0x00141230, + 0x704, 0x601C05FF, + 0x720, 0x20000000, + 0x738, 0x004100CC, + 0x12A0, 0x24903056, + 0x12AC, 0x12333121, + 0x12B8, 0x30020000, + 0x12E4, 0x30D52A68, + 0x2000, 0x18BBBF84, + 0x32A0, 0x24903056, + 0x32AC, 0x12333121, + 0x32B8, 0x30020000, + 0x32E4, 0x30D52A68, + 0x5800, 0x03FF807F, + 0x5804, 0x04237040, + 0x5808, 0x04237040, + 0x7800, 0x03FF807F, + 0x7804, 0x04237040, + 0x7808, 0x04237040, + 0x73C, 0x00000002, + 0x74C, 0x00000001, + 0x748, 0x00000002, + 0x5818, 0x082C1800, + 0x7818, 0x082C1800, + 0x624, 0x0101030A, + 0xC14, 0x85010000, + 0xDD4, 0x00000001, + 0x241C, 0x00000001, + 0x1200, 0x00010142, + 0x3200, 0x00010142, + 0xC0F8, 0x00000001, + 0xC1F8, 0x00000001, + 0x35C, 0x000004C4, + 0x0F0, 0x00000002, + 0x0F4, 0x00000023, + 0x0F8, 0x20210903, + +}; + + +/****************************************************************************** + * phy_reg_gain.TXT + ******************************************************************************/ + +const u32 array_mp_8852b_phy_reg_gain[] = { + 0x000, 0x18FBDDB7, + 0x001, 0x006F5436, + 0x002, 0x00004F31, + 0x100, 0x1BFEE0B7, + 0x101, 0x006C5238, + 0x102, 0x00005031, + 0x10000, 0x07E6C39E, + 0x10001, 0x00654526, + 0x10002, 0x00006750, + 0x10100, 0x09E9C69F, + 0x10101, 0x00674627, + 0x10102, 0x00006750, + 0x20000, 0x06E8C49F, + 0x20001, 0x00654526, + 0x20002, 0x00006750, + 0x20100, 0x07E9C6A0, + 0x20101, 0x00674728, + 0x20102, 0x00006850, + 0x30000, 0x04E5C39D, + 0x30001, 0x00634325, + 0x30002, 0x00006750, + 0x30100, 0x06E9C69F, + 0x30101, 0x00654527, + 0x30102, 0x00006750, + 0x1000000, 0x000000F4, + 0x1000010, 0x000000F8, + 0x1000011, 0x0000F8F8, + 0x1000100, 0x000000F8, + 0x1000110, 0x00000000, + 0x1000111, 0x00000000, + 0x1010000, 0x000000F4, + 0x1010010, 0x000000F8, + 0x1010011, 0x0000F8F8, + 0x1010020, 0x000000F8, + 0x1010021, 0x0808E8E8, + 0x1010029, 0x00002828, + 0x1010100, 0x000000F4, + 0x1010110, 0x000000F8, + 0x1010111, 0x0000F8F8, + 0x1010120, 0x000000F8, + 0x1010121, 0x0808E8E8, + 0x1010129, 0x00002828, + 0x1020000, 0x000000F4, + 0x1020010, 0x000000F8, + 0x1020011, 0x0000F8F8, + 0x1020020, 0x000000F8, + 0x1020021, 0x0808E8E8, + 0x1020029, 0x00002828, + 0x1020100, 0x000000F4, + 0x1020110, 0x000000F8, + 0x1020111, 0x0000F8F8, + 0x1020120, 0x000000F8, + 0x1020121, 0x0808E8E8, + 0x1020129, 0x00002828, + 0x1030000, 0x000000F4, + 0x1030010, 0x000000F8, + 0x1030011, 0x0000F8F8, + 0x1030020, 0x000000F8, + 0x1030021, 0x0808E8E8, + 0x1030029, 0x00002828, + 0x1030100, 0x000000F4, + 0x1030110, 0x000000F8, + 0x1030111, 0x0000F8F8, + 0x1030120, 0x000000F8, + 0x1030121, 0x0808E8E8, + 0x1030129, 0x00002828, + +}; + + +#endif /* _HALBB_HWIMG_RAW_DATA_8852B_H */ \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b_gain.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b_gain.h new file mode 100644 index 0000000..225ffe8 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b_gain.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 2.0.1.2*/ +#ifndef _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H +#define _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H + + +#endif /* _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H */ \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.c b/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.c new file mode 100644 index 0000000..4158099 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.c @@ -0,0 +1,139 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "../halbb_precomp.h" +#ifdef BB_8852B_SUPPORT + +void halbb_cfg_rf_reg_8852b(struct bb_info *bb, u32 addr, u32 data, + enum rf_path rf_path, u32 reg_addr) +{ +} + +void halbb_cfg_rf_radio_a_8852b(struct bb_info *bb, u32 addr, u32 data) +{ +} + +void halbb_cfg_rf_radio_b_8852b(struct bb_info *bb, u32 addr, u32 data) +{ +} + +void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data, + enum phl_phy_idx phy_idx) +{ +#ifdef HALBB_DBCC_SUPPORT + u32 ofst = 0; +#endif + + if (addr == 0xfe) { + halbb_delay_ms(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 ms\n"); + } else if (addr == 0xfd) { + halbb_delay_ms(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 ms\n"); + } else if (addr == 0xfc) { + halbb_delay_ms(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 ms\n"); + } else if (addr == 0xfb) { + halbb_delay_us(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 us\n"); + } else if (addr == 0xfa) { + halbb_delay_us(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 us\n"); + } else if (addr == 0xf9) { + halbb_delay_us(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 us\n"); + } else { + #ifdef HALBB_DBCC_SUPPORT + if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) && + phy_idx == HW_PHY_1) { + ofst = halbb_phy0_to_phy1_ofst(bb, addr); + if (ofst == 0) + return; + addr += ofst; + } else { + phy_idx = HW_PHY_0; + } + BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); + #else + BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data); + #endif + + halbb_set_reg(bb, addr, MASKDWORD, data); + } +} + +void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data) +{ + struct bb_gain_info *gain = &bb->bb_gain_i; + u8 cfg_type = (u8)((addr & 0xff000000) >> 24); + enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16); + u8 path = (u8)((addr & 0xff00) >> 8); + u8 type; + u8 i = 0; + + if (band_idx >= BB_GAIN_BAND_NUM) + return; + + if (path >= HALBB_MAX_PATH) + return; + + if (addr == 0xfe) { + halbb_delay_ms(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 ms\n"); + } else if (addr == 0xfd) { + halbb_delay_ms(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 ms\n"); + } else if (addr == 0xfc) { + halbb_delay_ms(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 ms\n"); + } else if (addr == 0xfb) { + halbb_delay_us(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 us\n"); + } else if (addr == 0xfa) { + halbb_delay_us(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 us\n"); + } else if (addr == 0xf9) { + halbb_delay_us(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 us\n"); + } else if (cfg_type ==0) { /*GAIN ERROR*/ + type = (u8)(addr & 0xff); + if (type == 0) { + for (i = 0; i < 4; i++) + gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff; + } else if (type == 1) { + for (i = 0; i < 3; i++) + gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff; + } else if (type == 2) { + for (i = 0; i < 2; i++) + gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff; + } + } else if (cfg_type == 1) { /*RPL Offset*/ + halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data); + } else { + BB_WARNING("cfg_type=%d\n", cfg_type); + } +} + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.h new file mode 100644 index 0000000..c73ade8 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.h @@ -0,0 +1,34 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALBB_REG_CFG_8852B_H_ +#define _HALBB_REG_CFG_8852B_H_ + +#ifdef BB_8852B_SUPPORT + +void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data, + enum phl_phy_idx phy_idx); +void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data); +#endif +#endif /* RTL8852B_SUPPORT*/ diff --git a/phl/hal_g6/phy/bb/halbb_8852b/halbb_version_rtl8852b.h b/phl/hal_g6/phy/bb/halbb_8852b/halbb_version_rtl8852b.h new file mode 100644 index 0000000..e080bdd --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_8852b/halbb_version_rtl8852b.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +/*RTL8852B BB Parameters*/ +#ifndef _HALBB_VERSION_8852B_H_ +#define _HALBB_VERSION_8852B_H_ +#define BB_REG_RELEASE_DATE_8852B 20210903 +#define BB_REG_RELEASE_VERSION_8852B 23 +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ant_div.c b/phl/hal_g6/phy/bb/halbb_ant_div.c new file mode 100644 index 0000000..e1d01cc --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ant_div.c @@ -0,0 +1,1451 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_ANT_DIV_SUPPORT + +void halbb_antdiv_reset_training_stat(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + struct bb_antdiv_rssi_info *bb_rssi_i = &bb_ant_div->bb_rssi_i; + struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i; + + halbb_mem_set(bb, bb_rate_i, 0, sizeof(struct bb_antdiv_rate_info)); + halbb_mem_set(bb, bb_cn_i, 0, sizeof(struct bb_antdiv_cn_info)); + halbb_mem_set(bb, bb_evm_i, 0, sizeof(struct bb_antdiv_evm_info)); + halbb_mem_set(bb, bb_rssi_i, 0, sizeof(struct bb_antdiv_rssi_info)); + +} + +void halbb_antdiv_reset(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + + /* Reset stat */ + halbb_antdiv_reset_training_stat(bb); +} + +void halbb_antdiv_reg_init(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; + + /* dis r_ant_train_en */ + halbb_set_reg_cmn(bb, cr->path0_r_ant_train_en, cr->path0_r_ant_train_en_m, 0x0, HW_PHY_0); + + /* force r_tx_ant_sel instead of from FW CMAC table */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(1), 0x0, HW_PHY_0); +#ifdef BB_8852A_CAV_SUPPORT + /* r_trsw_tx_extend = 0us */ + halbb_set_reg_cmn(bb, 0x828, 0xf, 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE + + /* dis r_hw_antsw_dis_by_gnt_bt */ + halbb_set_reg_cmn(bb, 0x828, BIT(12), 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE +#endif +#ifdef HALBB_COMPILE_AP_SERIES + /* r_trsw_tx_extend = 0us */ + halbb_set_reg_cmn(bb, 0x2728, 0xf, 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE + /* dis r_hw_antsw_dis_by_gnt_bt */ + halbb_set_reg_cmn(bb, 0x2728, BIT(12), 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE +#endif + /* dis r_bt_force_en */ + halbb_set_reg_cmn(bb, cr->path0_r_bt_force_antidx_en, cr->path0_r_bt_force_antidx_en_m, 0x0, HW_PHY_0); + + /* r_rfsw_ctrl_antenna (Antenna mapping) */ + halbb_set_reg_cmn(bb, cr->path0_r_rfsw_ant_31_0, 0xFFFF, 0x0100, HW_PHY_0); + + /* dis r_BB_SEL_BTG_TRX_S */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(21), 0x1, HW_PHY_0); + + /* "antsel" is controlled by HWs*/ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), 0x0, HW_PHY_0); + /* r_ANT_DIV_SW_2G_S, 2G "CS/CG switching" is controlled by HWs */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(23), 0x0, HW_PHY_0); + /* r_ANT_DIV_SW_5G_S, 5G "CS/CG switching" is controlled by HWs */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(25), 0x0, HW_PHY_0); +} + + +void halbb_antdiv_init(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + + if (dev->rfe_type != 50) + return; + + /* HW reg. init to set mux & ctrler for antdiv */ + halbb_antdiv_reg_init(bb); + + /* Mode setting*/ + bb_ant_div->antdiv_mode = AUTO_ANT; + bb_ant_div->pre_antdiv_mode = AUTO_ANT; + bb_ant_div->antdiv_method = EVM_BASED_ANTDIV; + bb_ant_div->tp_decision_method = TP_HIGHEST_DOMINATION; + bb_ant_div->evm_decision_method = EVM_LINEAR_AVG; + + /* Algorithm parameter setting */ + bb_ant_div->antdiv_period = ANTDIV_PERIOD; + bb_ant_div->antdiv_train_num = ANTDIV_TRAINING_NUM; + bb_ant_div->antdiv_delay = ANTDIV_DELAY; + bb_ant_div->antdiv_intvl = ANTDIV_INTVL; + bb_ant_div->tp_diff_th_high = ANTDIV_DEC_TP_HIGH; + bb_ant_div->tp_diff_th_low = ANTDIV_DEC_TP_LOW; + bb_ant_div->evm_diff_th = ANTDIV_DEC_EVM; + bb_ant_div->tp_lb = TP_LOWER_BOUND; + + /* variable init */ + bb_ant_div->antdiv_wd_cnt = 0; + bb_ant_div->antdiv_training_state_cnt = 0; + bb_ant_div->get_stats = false; + bb_ant_div->antdiv_use_ctrl_frame = true; + + + bb_ant_div->target_ant = ANTDIV_INIT; + bb_ant_div->target_ant_evm = ANTDIV_INIT; + bb_ant_div->target_ant_tp = ANTDIV_INIT; + bb_ant_div->training_ant = ANTDIV_INIT; + bb_ant_div->pre_target_ant = MAIN_ANT; + + halbb_antdiv_reset(bb); + + BB_DBG(bb, DBG_INIT, "Init ant_diversity timer"); +} + +void halbb_antdiv_deinit(struct bb_info *bb) +{ + #if 0 + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + struct bb_antdiv_rssi_info *bb_rssi_i = &bb_ant_div->bb_rssi_i; + struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i; + + if (&bb_rate_i) + halbb_mem_free(bb, bb_rate_i, sizeof(struct bb_antdiv_rate_info)); + if (&bb_cn_i) + halbb_mem_free(bb, bb_cn_i, sizeof(struct bb_antdiv_cn_info)); + if (&bb_evm_i) + halbb_mem_free(bb, bb_evm_i, sizeof(struct bb_antdiv_evm_info)); + if (&bb_rssi_i) + halbb_mem_free(bb, bb_rssi_i, sizeof(struct bb_antdiv_rssi_info)); + #endif +} + + +void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; + u8 band = bb->hal_com->band[0].cur_chandef.band; + u8 default_ant, optional_ant; + struct rtw_hal_com_t *hal = bb->hal_com; + + if ((bb_ant_div->pre_target_ant != ant) || (bb_ant_div->training_ant != ant) ) { + BB_DBG(bb, DBG_ANT_DIV, "Set Antenna =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + if(ant == MAIN_ANT) { + default_ant = ANT1_2G; + optional_ant = ANT2_2G; + } else { + default_ant = ANT2_2G; + optional_ant = ANT1_2G; + } + + /* Original Rx antenna */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0x20000, default_ant, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf0, default_ant, HW_PHY_0); + /* Alternative Rx antenna */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf00, optional_ant, HW_PHY_0); + /* Tx antenna, same as orig. rx ant. */ + halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf000, default_ant, HW_PHY_0); + + rtw_hal_rf_rx_ant(hal, ant); + + } else { + BB_DBG(bb, DBG_ANT_DIV, "Stay in Ori-ant\n"); + } +} + +void halbb_antdiv_get_rssi(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rssi_info *rssi = &bb_ant_div->bb_rssi_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + + rssi->rssi_cck_avg = (u8)HALBB_DIV(rssi->rssi_cck_avg_acc, rssi->pkt_cnt_cck); + rssi->rssi_ofdm_avg = (u8)HALBB_DIV(rssi->rssi_ofdm_avg_acc, rssi->pkt_cnt_ofdm); + rssi->rssi_t_avg = (u8)HALBB_DIV(rssi->rssi_t_avg_acc, rssi->pkt_cnt_t); + + + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) { + rssi->rssi_final = rssi->rssi_cck_avg; + } else { + rssi->rssi_final = rssi->rssi_ofdm_avg; + } + } else { + rssi->rssi_final = rssi->rssi_t_avg; + } +} + +void halbb_antdiv_get_cn_target_ant(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + u32 main_cn, aux_cn; + u8 target_ant_cn; + + /* CN */ + main_cn = (u8)HALBB_DIV(bb_cn_i->main_cn_avg_acc, (bb_rate_i->main_pkt_cnt_t + bb_rate_i->main_pkt_cnt_ofdm)); + aux_cn = (u8)HALBB_DIV(bb_cn_i->aux_cn_avg_acc, (bb_rate_i->aux_pkt_cnt_t+ bb_rate_i->aux_pkt_cnt_ofdm)); + + if (aux_cn == 0) + target_ant_cn = MAIN_ANT; + else if (main_cn == 0) + target_ant_cn = AUX_ANT; + else + target_ant_cn = (main_cn == aux_cn) ? (bb_ant_div->pre_target_ant) : ((main_cn >= aux_cn) ? AUX_ANT : MAIN_ANT); + + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Main-Ant CN_avg]", + (main_cn >> 1), + halbb_show_fraction_num(main_cn & 0x1, 1)); + + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Aux-Ant CN_avg]", + (aux_cn >> 1), + halbb_show_fraction_num(aux_cn & 0x1, 1)); + + bb_ant_div->target_ant_cn = target_ant_cn; + BB_DBG(bb, DBG_ANT_DIV, "CN based TargetAnt= [%s]\n", (bb_ant_div->target_ant_cn == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); +} + + +void halbb_antdiv_get_highest_mcs(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + + u16 main_max_cnt = 0; + u16 aux_max_cnt = 0; + u16 main_max_idx = 0; + u16 aux_max_idx = 0; + u8 ss_ofst = 0; + u8 i; + + BB_DBG(bb, DBG_ANT_DIV, "*Main-Ant CCK cnt:{%d, %d, %d, %d}\n", + bb_rate_i->main_pkt_cnt_legacy[0], bb_rate_i->main_pkt_cnt_legacy[1], + bb_rate_i->main_pkt_cnt_legacy[2], bb_rate_i->main_pkt_cnt_legacy[3]); + + BB_DBG(bb, DBG_ANT_DIV, "*Aux-Ant CCK cnt:{%d, %d, %d, %d}\n", + bb_rate_i->aux_pkt_cnt_legacy[0], bb_rate_i->aux_pkt_cnt_legacy[1], + bb_rate_i->aux_pkt_cnt_legacy[2], bb_rate_i->aux_pkt_cnt_legacy[3]); + + BB_DBG(bb, DBG_ANT_DIV, "*Main-Ant OFDM cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n", + bb_rate_i->main_pkt_cnt_legacy[4], bb_rate_i->main_pkt_cnt_legacy[5], + bb_rate_i->main_pkt_cnt_legacy[6], bb_rate_i->main_pkt_cnt_legacy[7], + bb_rate_i->main_pkt_cnt_legacy[8], bb_rate_i->main_pkt_cnt_legacy[9], + bb_rate_i->main_pkt_cnt_legacy[10], bb_rate_i->main_pkt_cnt_legacy[11]); + + BB_DBG(bb, DBG_ANT_DIV, "*Aux-Ant OFDM cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n", + bb_rate_i->aux_pkt_cnt_legacy[4], bb_rate_i->aux_pkt_cnt_legacy[5], + bb_rate_i->aux_pkt_cnt_legacy[6], bb_rate_i->aux_pkt_cnt_legacy[7], + bb_rate_i->aux_pkt_cnt_legacy[8], bb_rate_i->aux_pkt_cnt_legacy[9], + bb_rate_i->aux_pkt_cnt_legacy[10], bb_rate_i->aux_pkt_cnt_legacy[11]); + + if ((bb_rate_i->main_he_pkt_not_zero == true) || (bb_rate_i->aux_he_pkt_not_zero == true)) { + for (i = 0; i < HE_RATE_NUM; i++) { + + if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_he[i] >= main_max_cnt) { + main_max_cnt = bb_rate_i->main_pkt_cnt_he[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_he[i] >= aux_max_cnt) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_he[i]; + aux_max_idx = i; + } + } else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_he[i] > 0) { + main_max_cnt = bb_rate_i->main_pkt_cnt_he[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_he[i] > 0) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_he[i]; + aux_max_idx = i; + } + } + } + + for (i = 0; i < bb->num_rf_path; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + BB_DBG(bb, DBG_ANT_DIV, + "*Main-Ant HE %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + bb_rate_i->main_pkt_cnt_he[ss_ofst + 0], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 1], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 2], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 3], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 4], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 5], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 6], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 7], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 8], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 9], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 10], + bb_rate_i->main_pkt_cnt_he[ss_ofst + 11]); + + BB_DBG(bb, DBG_ANT_DIV, + "*Aux-Ant HE %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 0], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 1], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 2], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 3], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 4], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 5], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 6], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 7], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 8], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 9], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 10], + bb_rate_i->aux_pkt_cnt_he[ss_ofst + 11]); + + } + + } else if ((bb_rate_i->main_vht_pkt_not_zero == true) || (bb_rate_i->aux_vht_pkt_not_zero == true)) { + + for (i = 0; i < VHT_RATE_NUM; i++) { + + if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_vht[i] >= main_max_cnt) { + main_max_cnt = bb_rate_i->main_pkt_cnt_vht[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_vht[i] >= aux_max_cnt) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_vht[i]; + aux_max_idx = i; + } + } else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_vht[i] > 0) { + main_max_cnt = bb_rate_i->main_pkt_cnt_vht[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_vht[i] > 0) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_vht[i]; + aux_max_idx = i; + } + } + } + + + for (i = 0; i < bb->num_rf_path; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + BB_DBG(bb, DBG_ANT_DIV, + "*Main-Ant VHT %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 0], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 1], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 2], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 3], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 4], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 5], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 6], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 7], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 8], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 9], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 10], + bb_rate_i->main_pkt_cnt_vht[ss_ofst + 11]); + + BB_DBG(bb, DBG_ANT_DIV, + "*Aux-Ant VHT %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 0], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 1], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 2], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 3], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 4], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 5], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 6], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 7], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 8], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 9], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 10], + bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 11]); + } + + } else if ((bb_rate_i->main_ht_pkt_not_zero == true) || (bb_rate_i->aux_ht_pkt_not_zero == true)) { + for (i = 0; i < HT_RATE_NUM; i++) { + + if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_ht[i] >= main_max_cnt) { + main_max_cnt = bb_rate_i->main_pkt_cnt_ht[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_ht[i] >= aux_max_cnt) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_ht[i]; + aux_max_idx = i; + } + } else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) { + if (bb_rate_i->main_pkt_cnt_ht[i] > 0) { + main_max_cnt = bb_rate_i->main_pkt_cnt_ht[i]; + main_max_idx = i; + } + if (bb_rate_i->aux_pkt_cnt_ht[i] > 0) { + aux_max_cnt = bb_rate_i->aux_pkt_cnt_ht[i]; + aux_max_idx = i; + } + } + } + + for (i = 0; i < bb->num_rf_path; i++) { + ss_ofst = (i << 3); + + BB_DBG(bb, DBG_ANT_DIV, + "*HT%02d:%02d cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 0], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 1], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 2], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 3], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 4], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 5], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 6], + bb_rate_i->main_pkt_cnt_ht[ss_ofst + 7]); + + BB_DBG(bb, DBG_ANT_DIV, + "*HT%02d:%02d cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 0], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 1], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 2], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 3], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 4], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 5], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 6], + bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 7]); + } + + } + + /* Compute all throughput*/ + if (bb_ant_div->tp_decision_method == TP_AVG_DOMINATION) { + BB_DBG(bb, DBG_ANT_DIV, "Main_tp = %lld, Aux_tp = %lld\n", + bb_rate_i->main_tp, bb_rate_i->aux_tp); + + if (bb_rate_i->main_tp > bb_rate_i->aux_tp) { + bb_ant_div->target_ant_tp = MAIN_ANT; + bb_rate_i->tp_diff = bb_rate_i->main_tp - bb_rate_i->aux_tp; + } else if (bb_rate_i->main_tp < bb_rate_i->aux_tp) { + bb_ant_div->target_ant_tp = AUX_ANT; + bb_rate_i->tp_diff = bb_rate_i->aux_tp - bb_rate_i->main_tp; + } else { + bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant; + bb_rate_i->no_change_flag = true; + BB_DBG(bb, DBG_ANT_DIV, "TP based TargetAnt= Pre-TargetAnt\n"); + } + + BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= [%s]\n", + (bb_ant_div->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + BB_DBG(bb, DBG_ANT_DIV, "TP Confidence= [%lld]\n", bb_rate_i->tp_diff); + + return; + } + + bb_rate_i->main_max_cnt = main_max_cnt; + bb_rate_i->main_max_idx = main_max_idx; + bb_rate_i->aux_max_cnt = aux_max_cnt; + bb_rate_i->aux_max_idx = aux_max_idx; + + /* Decision Tput based target ant using MCS rate instead of phy data rate */ + if ((main_max_cnt > bb_ant_div->tp_lb) || (aux_max_cnt > bb_ant_div->tp_lb)) { + if (main_max_idx > aux_max_idx) { + bb_ant_div->target_ant_tp = MAIN_ANT; + bb_rate_i->tp_diff = 100; + } else if (main_max_idx < aux_max_idx) { + bb_ant_div->target_ant_tp = AUX_ANT; + bb_rate_i->tp_diff = 100; + } else { + if (main_max_cnt > aux_max_cnt) + bb_ant_div->target_ant_tp = MAIN_ANT; + else if (main_max_cnt < aux_max_cnt) + bb_ant_div->target_ant_tp = AUX_ANT; + else { + bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant; + bb_rate_i->no_change_flag = true; + } + /* Calc. TP confidence*/ + bb_rate_i->tp_diff = DIFF_2(main_max_cnt, aux_max_cnt); + } + } else { + bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant; + bb_rate_i->no_change_flag = true; + BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= Pre-TargetAnt\n"); + } + + if (bb_rate_i->no_change_flag == true) + bb_rate_i->tp_diff = 0; + + if (bb_rate_i->tp_diff > 100) + bb_rate_i->tp_diff = 100; + + BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= [%s]\n", + (bb_ant_div->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + BB_DBG(bb, DBG_ANT_DIV, "TP Confidence= [%lld]\n", bb_rate_i->tp_diff); +} + +void halbb_antdiv_get_evm_target_ant(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + u8 main_2ss_evm_min = 0; + u8 aux_2ss_evm_min = 0; + //u8 main_2ss_evm_avg, aux_2ss_evm_avg; + u8 main_1ss_evm = 0; + u8 aux_1ss_evm = 0; + u8 target_ant_evm_1ss, target_ant_evm_2ss; + u8 decision_evm_ss; + u8 evm_diff_1ss, evm_diff_2ss; + bool no_change_flag_1ss = false; + bool no_change_flag_2ss = false; + + /* 1ss EVM */ + if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) { + /* Modify db to linear (*10)*/ + bb_evm_i->main_evm_1ss = HALBB_DIV(bb_evm_i->main_evm_1ss, 10); + bb_evm_i->aux_evm_1ss = HALBB_DIV(bb_evm_i->aux_evm_1ss, 10); + + main_1ss_evm = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->main_evm_1ss, + (u64)(bb_rate_i->main_pkt_cnt_1ss + bb_rate_i->main_pkt_cnt_ofdm))); + aux_1ss_evm = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->aux_evm_1ss, + (u64)(bb_rate_i->aux_pkt_cnt_1ss + bb_rate_i->aux_pkt_cnt_ofdm))); + + main_1ss_evm = main_1ss_evm << 2; + aux_1ss_evm = aux_1ss_evm << 2; + } else { + main_1ss_evm = (u8)HALBB_DIV(bb_evm_i->main_evm_1ss, + (u64)(bb_rate_i->main_pkt_cnt_1ss + bb_rate_i->main_pkt_cnt_ofdm)); + aux_1ss_evm = (u8)HALBB_DIV(bb_evm_i->aux_evm_1ss, + (u64)(bb_rate_i->aux_pkt_cnt_1ss + bb_rate_i->aux_pkt_cnt_ofdm)); + } + + target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? + (bb_ant_div->pre_target_ant) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + + if (main_1ss_evm == aux_1ss_evm) { + target_ant_evm_1ss = bb_ant_div->pre_target_ant; + no_change_flag_1ss = true; + } else if (main_1ss_evm > aux_1ss_evm) { + target_ant_evm_1ss = MAIN_ANT; + } else { + target_ant_evm_1ss = AUX_ANT; + } + + /* Calc. EVM confindece*/ + evm_diff_1ss = DIFF_2(main_1ss_evm, aux_1ss_evm); + + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Main-Ant 1ss-EVM_avg]", + (main_1ss_evm >> 2), + halbb_show_fraction_num(main_1ss_evm & 0x3, 2)); + + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Aux-Ant 1ss-EVM_avg]", + (aux_1ss_evm >> 2), + halbb_show_fraction_num(aux_1ss_evm & 0x3, 2)); + + /* 2ss EVM */ + if ((bb_rate_i->main_pkt_cnt_2ss + bb_rate_i->aux_pkt_cnt_2ss) != 0) { + if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) { + + bb_evm_i->main_evm_min_acc = HALBB_DIV(bb_evm_i->main_evm_min_acc, 10); + bb_evm_i->aux_evm_min_acc = HALBB_DIV(bb_evm_i->aux_evm_min_acc, 10); + + main_2ss_evm_min = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->main_evm_min_acc, + (u64)bb_rate_i->main_pkt_cnt_2ss)); + aux_2ss_evm_min = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->aux_evm_min_acc, + (u64)bb_rate_i->aux_pkt_cnt_2ss)); + + main_2ss_evm_min = main_2ss_evm_min << 2; + aux_2ss_evm_min = aux_2ss_evm_min << 2; + + } else { + main_2ss_evm_min = (u8)HALBB_DIV(bb_evm_i->main_evm_min_acc, + (u64)bb_rate_i->main_pkt_cnt_2ss); + aux_2ss_evm_min = (u8)HALBB_DIV(bb_evm_i->aux_evm_min_acc, + (u64)bb_rate_i->aux_pkt_cnt_2ss); + } + + if (main_2ss_evm_min == aux_2ss_evm_min) { + target_ant_evm_2ss = bb_ant_div->pre_target_ant; + no_change_flag_2ss = true; + } else if (main_2ss_evm_min > aux_2ss_evm_min) { + target_ant_evm_2ss = MAIN_ANT; + } else { + target_ant_evm_2ss = AUX_ANT; + } + + /* Calc. EVM confindece*/ + evm_diff_2ss = DIFF_2(main_2ss_evm_min, aux_2ss_evm_min); + } + + /*-----For Debug-----*/ + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d) (%d)\n", "[Main-Ant 2ss-EVM_avg]", + (main_2ss_evm_min >> 2), + halbb_show_fraction_num(main_2ss_evm_min & 0x3, 2),main_2ss_evm_min); + + BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d) (%d)\n", "[Aux-Ant 2ss-EVM_avg]", + (aux_2ss_evm_min >> 2), + halbb_show_fraction_num(aux_2ss_evm_min & 0x3, 2), aux_2ss_evm_min); + /*-------------------*/ + + if ((bb_rate_i->main_pkt_cnt_2ss + bb_rate_i->aux_pkt_cnt_2ss) != 0) { + decision_evm_ss = 2; + bb_evm_i->evm_diff = evm_diff_2ss; + bb_ant_div->target_ant_evm = target_ant_evm_2ss; + bb_evm_i->no_change_flag = no_change_flag_2ss; + } else { + decision_evm_ss = 1; + bb_evm_i->evm_diff = evm_diff_1ss; + bb_ant_div->target_ant_evm = target_ant_evm_1ss; + bb_evm_i->no_change_flag = no_change_flag_1ss; + } + + if (bb_evm_i->no_change_flag == true) { + bb_evm_i->evm_diff = 0; + BB_DBG(bb, DBG_ANT_DIV, "EVM based TargetAnt= Pre-TargetAnt\n"); + } + + if (bb_evm_i->evm_diff > 100) + bb_evm_i->evm_diff = 100; + + BB_DBG(bb, DBG_ANT_DIV, "%d-ss EVM based TargetAnt= [%s]\n", + decision_evm_ss, (bb_ant_div->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + BB_DBG(bb, DBG_ANT_DIV, "EVM Confidence= [%d]\n", bb_evm_i->evm_diff); +} + +void halbb_antdiv_training_state(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + u8 next_ant; + + if (bb_ant_div->antdiv_training_state_cnt == 0) { + bb_ant_div->get_stats = false; + + halbb_antdiv_reset_training_stat(bb); + bb_ant_div->training_ant = bb_ant_div->pre_target_ant; + + next_ant = (bb_ant_div->training_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT; + BB_DBG(bb, DBG_ANT_DIV, "Next training ant =%s\n", + (next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + halbb_antdiv_set_ant(bb, next_ant); + + bb_ant_div->training_ant = next_ant; + //bb_ant_div->pre_target_ant = next_ant; + + bb_ant_div->antdiv_training_state_cnt++; + + BB_DBG(bb, DBG_ANT_DIV, "%s Statistics Interval=%d ms\n", + ((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_intvl); + bb_ant_div->get_stats = true; + bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_intvl; + halbb_antdiv_timers(bb, BB_SET_TIMER); + + } else if ((bb_ant_div->antdiv_training_state_cnt % 2) == 0) { + bb_ant_div->antdiv_training_state_cnt++; + + next_ant = bb_ant_div->training_ant; + + BB_DBG(bb, DBG_ANT_DIV, "%s Statistics Interval=%d ms\n", + ((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_intvl); + + bb_ant_div->get_stats = true; + bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_intvl; + halbb_antdiv_timers(bb, BB_SET_TIMER); + + } else if ((bb_ant_div->antdiv_training_state_cnt % 2) != 0) { + bb_ant_div->get_stats = false; + + next_ant = (bb_ant_div->training_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + BB_DBG(bb, DBG_ANT_DIV, "Next training ant =%s\n", + (next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + halbb_antdiv_set_ant(bb, next_ant); + + bb_ant_div->training_ant = next_ant; + + bb_ant_div->antdiv_training_state_cnt++; + + BB_DBG(bb, DBG_ANT_DIV, "%s Delay=%d ms\n", + ((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_delay); + bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_delay; + halbb_antdiv_timers(bb, BB_SET_TIMER); + } +} + +void halbb_antdiv_decision_state(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + + BB_DBG(bb, DBG_ANT_DIV, "[Decisoin state]\n"); + + bb_ant_div->get_stats = false; + bb_ant_div->antdiv_training_state_cnt = 0; + /* Check highest MCS idx of main & aux antenna*/ + halbb_antdiv_get_highest_mcs(bb); + + /* EVM based antenna diversity */ + halbb_antdiv_get_evm_target_ant(bb); + + /* Final Decision */ + if ((bb_rate_i->main_cnt_all + bb_rate_i->aux_cnt_all) == 0) { + BB_DBG(bb, DBG_ANT_DIV, "Not enough count, remain previous antenna\n"); + bb_ant_div->target_ant = bb_ant_div->pre_target_ant; + BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n"); + bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period; + return; + } + + if (bb_rate_i->no_change_flag && bb_evm_i->no_change_flag) { + BB_DBG(bb, DBG_ANT_DIV, "No Decision, remain previous antenna\n"); + bb_ant_div->target_ant = bb_ant_div->pre_target_ant; + BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n"); + bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period; + return; + } + + if ((bb_ant_div->target_ant_evm == bb_ant_div->target_ant_tp) && + (!bb_rate_i->no_change_flag) && (!bb_evm_i->no_change_flag)) { + BB_DBG(bb, DBG_ANT_DIV, "Decision confidence is enough\n"); + bb_ant_div->target_ant = bb_ant_div->target_ant_evm; + } else { + if (bb_rate_i->tp_diff >= bb_ant_div->tp_diff_th_high) { + BB_DBG(bb, DBG_ANT_DIV, "TP confidence is %lld > %d, Decided by MCS based\n" + ,bb_rate_i->tp_diff, bb_ant_div->tp_diff_th_low); + bb_ant_div->target_ant = bb_ant_div->target_ant_tp; + } else if (bb_evm_i->evm_diff >= bb_ant_div->evm_diff_th) { + BB_DBG(bb, DBG_ANT_DIV, "EVM confidence is more than %d, Decided by EVM based\n" + ,bb_ant_div->evm_diff_th); + bb_ant_div->target_ant = bb_ant_div->target_ant_evm; + } else if (bb_rate_i->tp_diff >= bb_ant_div->tp_diff_th_low) { + BB_DBG(bb, DBG_ANT_DIV, "TP confidence is %lld > %d, Decided by MCS based\n" + ,bb_rate_i->tp_diff, bb_ant_div->tp_diff_th_low); + bb_ant_div->target_ant = bb_ant_div->target_ant_tp; + } else { + BB_DBG(bb, DBG_ANT_DIV, "Decision confidence is not enough, remain previous antenna\n"); + bb_ant_div->target_ant = bb_ant_div->pre_target_ant; + + BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n"); + bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period; + } + } + + BB_DBG(bb, DBG_ANT_DIV, "TargetAnt= [%s]\n", (bb_ant_div->target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + +} + +void halbb_evm_based_antdiv(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rssi_su_avg_info *avg = &cmn_rpt->bb_rssi_su_avg_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + + /* Main function */ + if (bb_ant_div->antdiv_training_state_cnt <= ((bb_ant_div->antdiv_train_num << 1) - 2)) { + BB_DBG(bb, DBG_ANT_DIV, "Ant_diversity training state = %d \n", + bb_ant_div->antdiv_training_state_cnt); + halbb_antdiv_training_state(bb); + return; + } else { + halbb_antdiv_decision_state(bb); + halbb_antdiv_reset_training_stat(bb); + } + + /* Set new target antenna */ + + BB_DBG(bb, DBG_ANT_DIV, "Ant_diversity done\n"); + halbb_antdiv_set_ant(bb, bb_ant_div->target_ant); + + /* Re-assign to next step reqired variable */ + bb_ant_div->target_ant_evm = bb_ant_div->target_ant; + bb_ant_div->target_ant_tp = bb_ant_div->target_ant; + bb_ant_div->target_ant_cn = bb_ant_div->target_ant; + bb_ant_div->pre_target_ant = bb_ant_div->target_ant; + +} + +void halbb_antenna_diversity(struct bb_info *bb) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_antdiv_rssi_info *rssi_stat = &bb_ant_div->bb_rssi_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + u8 rssi; + + + halbb_antdiv_get_rssi(bb); + + rssi = rssi_stat->rssi_final; + + + BB_DBG(bb, DBG_ANT_DIV, "%s ======>\n", __func__); + + /* Early return */ + + if(phl_is_mp_mode(bb->phl_com)) { + BB_DBG(bb, DBG_ANT_DIV, "Early return - MP mode\n"); + return; + } + + if (dev->rfe_type != 50) + return; + + if (!(bb->support_ability & BB_ANT_DIV)) { + BB_DBG(bb, DBG_ANT_DIV, "Early return - Not support antenna diversity\n"); + return; + } + + if (!(bb_link->is_linked) && !(bb_link->is_one_entry_only)) { + BB_DBG(bb, DBG_ANT_DIV, "Early return - is_linked=%d, one_entry_only=%d\n", + bb_link->is_linked, bb_link->is_one_entry_only); + return; + } + + if (rssi < ANTDIV_RSSI_TH_HIGH) { + BB_DBG(bb, DBG_ANT_DIV, "RSSI=%d is too low to do Ant_diveristy\n", rssi >> 1); + return; + } + + if (bb_link->one_entry_tp_active_occur) { // if TP > th., do antdiv per watchdog + BB_DBG(bb, DBG_ANT_DIV, "TP occur, do antdv immediately\n"); + bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period; + } + if (bb_ant_div->antdiv_wd_cnt < bb_ant_div->antdiv_period) { // else, do antdiv after specific watchdog + BB_DBG(bb, DBG_ANT_DIV, "Ant-div period = %d, watchdog count = %d\n", + bb_ant_div->antdiv_period, bb_ant_div->antdiv_wd_cnt); + bb_ant_div->antdiv_wd_cnt++; + return; + } else { + bb_ant_div->antdiv_wd_cnt = 0; + } + + /* Fixed-antenna diversity mode */ + if (bb_ant_div->antdiv_mode != AUTO_ANT) { + BB_DBG(bb, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n", + (bb_ant_div->antdiv_mode == FIX_MAIN_ANT) ? "MAIN" : "AUX"); + + if (bb_ant_div->antdiv_mode != bb_ant_div->pre_antdiv_mode) { + + if (bb_ant_div->antdiv_mode == FIX_MAIN_ANT) { + halbb_antdiv_set_ant(bb, MAIN_ANT); + } + else if (bb_ant_div->antdiv_mode == FIX_AUX_ANT) { + halbb_antdiv_set_ant(bb, AUX_ANT); + } + } + bb_ant_div->pre_antdiv_mode = bb_ant_div->antdiv_mode; + return; + } + + /* Main section of EVM/TP based antenna diversity*/ + BB_DBG(bb, DBG_ANT_DIV, "RSSI=%d, Ant_diversity start\n", rssi >> 1); + halbb_evm_based_antdiv(bb); +} + +void halbb_antdiv_get_rssi_stat(struct bb_info *bb) +{ + struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rssi_info *rssi = &bb_ant_div->bb_rssi_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + u8 i = 0; + + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) { + rssi->rssi_cck_avg_acc += psts_h->rssi_avg; + rssi->pkt_cnt_cck++; + + } else { + rssi->rssi_ofdm_avg_acc += psts_h->rssi_avg; + rssi->pkt_cnt_ofdm++; + + } + } else { + rssi->rssi_t_avg_acc+= psts_h->rssi_avg; + rssi->pkt_cnt_t++; + } +} + +void halbb_antdiv_get_evm_stat(struct bb_info *bb) +{ + struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + + /* Only get stats @ training period */ + if (!bb_ant_div->get_stats) + return; + + /* No EVM info. @ cck rate */ + if (cmn_rpt->is_cck_rate) + return; + + if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) { + if(bb_ant_div->training_ant == MAIN_ANT) { + if (rate_i->ss == 1) { + bb_evm_i->main_evm_1ss += halbb_db_2_linear((psts_1->evm_min >> 2)); + } else { + bb_evm_i->main_evm_min_acc += halbb_db_2_linear((psts_1->evm_min>> 2)); + + bb_evm_i->main_evm_max_acc += halbb_db_2_linear((psts_1->evm_max >> 2)); + } + } else if(bb_ant_div->training_ant == AUX_ANT) { + if (rate_i->ss == 1) { + bb_evm_i->aux_evm_1ss += halbb_db_2_linear((psts_1->evm_min >> 2)); + } else { + bb_evm_i->aux_evm_min_acc += halbb_db_2_linear((psts_1->evm_min >> 2)); + + bb_evm_i->aux_evm_max_acc += halbb_db_2_linear((psts_1->evm_max >> 2)); + } + } + } else { + if(bb_ant_div->training_ant == MAIN_ANT) { + if (rate_i->ss == 1) { + bb_evm_i->main_evm_1ss += psts_1->evm_min; + } else { + bb_evm_i->main_evm_min_acc += psts_1->evm_min; + + bb_evm_i->main_evm_max_acc += psts_1->evm_max; + } + } else if(bb_ant_div->training_ant == AUX_ANT) { + if (rate_i->ss == 1) { + bb_evm_i->aux_evm_1ss += psts_1->evm_min; + } else { + bb_evm_i->aux_evm_min_acc += psts_1->evm_min; + + bb_evm_i->aux_evm_max_acc += psts_1->evm_max; + } + } + } +} + +void halbb_antdiv_get_cn_stat(struct bb_info *bb) +{ + struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + + /* Only get stats @ training period */ + if (!bb_ant_div->get_stats) + return; + + /* Data frame only */ + #if 0 + if (bb_ant_div->antdiv_use_ctrl_frame) { + if (!bb_link->is_match_bssid) + return; + } + #endif + + /* No CN info. @ cck rate */ + if (cmn_rpt->is_cck_rate) + return; + + if (rate_i->ss == 0) + return; + + if(bb_ant_div->training_ant == MAIN_ANT) { + bb_cn_i->main_cn_avg_acc += psts_1->cn_avg; + } else if(bb_ant_div->training_ant == AUX_ANT) { + bb_cn_i->aux_cn_avg_acc += psts_1->cn_avg; + } +} + +void halbb_antdiv_get_rate_stat(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + //struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + u8 ofst = rate_i->idx; + + /* Only get stats @ training period */ + if (!bb_ant_div->get_stats) + return; + + /* Data frame only */ + #if 0 + if (bb_ant_div->antdiv_use_ctrl_frame) { + if (!bb_link->is_match_bssid) + return; + } + #endif + + //BB_DBG(bb, DBG_ANT_DIV, "Rate mode= %d\n", rate_i->mode); + //BB_DBG(bb, DBG_ANT_DIV, "Training antenna= %d\n", bb_ant_div->training_ant); + + if(bb_ant_div->training_ant == MAIN_ANT) { + /* pkt_cnt acc */ + //BB_DBG(bb, DBG_ANT_DIV, "MAIN_ANT rate!\n"); + bb_rate_i->main_cnt_all++; + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) + bb_rate_i->main_pkt_cnt_cck++; + else + bb_rate_i->main_pkt_cnt_ofdm++; + } else { + bb_rate_i->main_pkt_cnt_t++; + if (rate_i->ss == 1) + bb_rate_i->main_pkt_cnt_1ss++; + else if (rate_i->ss == 2) + bb_rate_i->main_pkt_cnt_2ss++; + } + + /* rate cnt acc*/ + if (rate_i->mode == BB_LEGACY_MODE) { + bb_rate_i->main_pkt_cnt_legacy[ofst]++; + return; + } + + + if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE) + ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1)); + + if (rate_i->mode == BB_HT_MODE) { + bb_rate_i->main_ht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1); + bb_rate_i->main_pkt_cnt_ht[ofst]++; + /* shift ofst due to mismatch of HT/VHT rate num*/ + ofst += ((ofst << 3) >> 2); + bb_rate_i->main_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } else if (rate_i->mode == BB_VHT_MODE) { + bb_rate_i->main_vht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1); + bb_rate_i->main_pkt_cnt_vht[ofst]++; + bb_rate_i->main_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } else if (rate_i->mode == BB_HE_MODE) { + bb_rate_i->main_he_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1); + bb_rate_i->main_pkt_cnt_he[ofst]++; + bb_rate_i->main_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } + + } else if(bb_ant_div->training_ant == AUX_ANT) { + bb_rate_i->aux_cnt_all++; + //BB_DBG(bb, DBG_ANT_DIV, "Aux_ANT rate!\n"); + /* pkt_cnt acc */ + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) + bb_rate_i->aux_pkt_cnt_cck++; + else + bb_rate_i->aux_pkt_cnt_ofdm++; + } else { + bb_rate_i->aux_pkt_cnt_t++; + if (rate_i->ss == 1) + bb_rate_i->aux_pkt_cnt_1ss++; + else if (rate_i->ss == 2) + bb_rate_i->aux_pkt_cnt_2ss++; + } + + if (rate_i->mode == BB_LEGACY_MODE) { + bb_rate_i->aux_pkt_cnt_legacy[ofst]++; + return; + } + + if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE) + ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1)); + + if (rate_i->mode == BB_HT_MODE) { + bb_rate_i->aux_ht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1); + bb_rate_i->aux_pkt_cnt_ht[ofst]++; + /* shift ofst due to mismatch of HT/VHT rate num*/ + ofst += ((ofst >> 3) << 2); + bb_rate_i->aux_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } else if (rate_i->mode == BB_VHT_MODE) { + bb_rate_i->aux_vht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1); + bb_rate_i->aux_pkt_cnt_vht[ofst]++; + bb_rate_i->aux_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } else if (rate_i->mode == BB_HE_MODE) { + bb_rate_i->aux_he_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1); + bb_rate_i->aux_pkt_cnt_he[ofst]++; + bb_rate_i->aux_tp += + bb_phy_rate_table[ofst + LEGACY_RATE_NUM]; + } + } +} + +void halbb_antdiv_phy_sts(struct bb_info *bb) { + halbb_antdiv_get_rssi_stat(bb); + halbb_antdiv_get_rate_stat(bb); + halbb_antdiv_get_evm_stat(bb); + halbb_antdiv_get_cn_stat(bb); +} + +void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; + + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Antenna Diversity Mode: {1} {0}: Auto-mode {1}: Fix main ant. {2}: Fix aux ant.\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Antenna Diversity Method: {2} {0}: EVM based {1}: CN based\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set training period: {3} {num of watchdog} (How much watchdog to do one ant-div)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set training state number: {4} {num}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set training interval: {5} {ms} (how long for one training state)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set training delay: {6} {ms} (how long to wait RA stable)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set decision threshold: {7} {TP high th.} {TP low th.} {EVM th.}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "TP lower bound: {8} {th.}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "TP decision method: {9} {0}: Max cnt domination {1}: highest rate domination {2}: Avg. TP domination\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EVM decision method: {10} {0}:Linear avg. {1}: dB avg.\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Show all parameter: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[ONLY DEBUG] {101} 0x586c[16]={0,1}\n"); + } else { + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_mode = (u8)var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div Mode=%d\n", bb_ant_div->antdiv_mode); + if (bb_ant_div->antdiv_mode == FIX_MAIN_ANT) { + halbb_antdiv_set_ant(bb, MAIN_ANT); + bb_ant_div->pre_target_ant = MAIN_ANT; + } else if (bb_ant_div->antdiv_mode == FIX_AUX_ANT) { + halbb_antdiv_set_ant(bb, AUX_ANT); + bb_ant_div->pre_target_ant = AUX_ANT; + } else if (bb_ant_div->antdiv_mode == AUTO_ANT) + halbb_antdiv_set_ant(bb, bb_ant_div->pre_target_ant); + } else if (var[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_method = var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training method=%d\n", bb_ant_div->antdiv_method); + } else if (var[0] == 3) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_period = (u8)var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div period=%d watchdog\n", bb_ant_div->antdiv_period); + } else if (var[0] == 4) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_train_num = var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training state num=%d\n", bb_ant_div->antdiv_train_num); + } else if (var[0] == 5) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_intvl = var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training interval=%d\n", bb_ant_div->antdiv_intvl); + } else if (var[0] == 6) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->antdiv_delay = var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training delay=%d\n", bb_ant_div->antdiv_delay); + } else if (var[0] == 7) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]); + bb_ant_div->tp_diff_th_high = (u16)var[1]; + bb_ant_div->tp_diff_th_low = (u16)var[2]; + bb_ant_div->evm_diff_th = (u8)var[3]; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Decision threshold: {TP high = %d} {TP low = %d} {EVM = %d}\n", + bb_ant_div->tp_diff_th_high, + bb_ant_div->tp_diff_th_low, + bb_ant_div->evm_diff_th); + } else if (var[0] == 8) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->tp_lb = (u8)var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "TP lower bound=%d\n", bb_ant_div->tp_lb); + } else if (var[0] == 9) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->tp_decision_method = (u8)var[1]; + BB_DBG(bb, DBG_ANT_DIV, "TP decision method=(( %d ))\n", + bb_ant_div->tp_decision_method); + } else if (var[0] == 10) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_ant_div->evm_decision_method = (u8)var[1]; + BB_DBG(bb, DBG_ANT_DIV, "EVM decision method=(( %d ))\n", + bb_ant_div->evm_decision_method); + } else if (var[0] == 100) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div Mode = {%d}\n", bb_ant_div->antdiv_mode); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training method = {%d}\n", bb_ant_div->antdiv_method); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "TP decision method = {%d}\n", bb_ant_div->tp_decision_method); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EVM decision method = {%d}\n", bb_ant_div->evm_decision_method); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div period = {#%d-watchdog}\n", bb_ant_div->antdiv_period); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training state num = {%d}\n", bb_ant_div->antdiv_train_num); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training interval = {%d}\n", bb_ant_div->antdiv_intvl); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Ant-Div training delay = {%d}\n", bb_ant_div->antdiv_delay); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Decision threshold: {TP high = %d} {TP low = %d} {EVM = %d}\n", + bb_ant_div->tp_diff_th_high, + bb_ant_div->tp_diff_th_low, + bb_ant_div->evm_diff_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "TP lower bound = {%d}\n", bb_ant_div->tp_lb); + } else if (var[0] == 101) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), var[1], HW_PHY_0); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[ONLY DEBUG] 0x1586c[16] = %d\n", var[1]); + + } + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_antdiv_callback(void *context) +{ + struct bb_info *bb = (struct bb_info *)context; + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + + halbb_evm_based_antdiv(bb); +} + +void halbb_antdiv_timers(struct bb_info *bb, enum bb_timer_cfg_t bb_antdiv_timer_state) +{ + struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i; + u8 state = bb_antdiv_timer_state; + + if (state == BB_SET_TIMER) { + halbb_set_timer(bb, &bb->antdiv_timer, bb_ant_div->antdiv_timer_ms); + } else if (state == BB_INIT_TIMER) { + halbb_init_timer(bb, &bb->antdiv_timer, halbb_antdiv_callback, bb, "halbb_antdiv_timers"); + } else if (state == BB_CANCEL_TIMER) { + halbb_cancel_timer(bb, &bb->antdiv_timer); + } else if (state == BB_RELEASE_TIMER) { + halbb_release_timer(bb, &bb->antdiv_timer); + } +} + +void halbb_cr_cfg_antdiv_init(struct bb_info *bb) +{ + struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i; + + switch (bb->cr_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_52AA; + cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_52AA_M; + cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_52AA; + cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_52AA_M; + cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_52AA; + cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_52AA_M; + cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_52AA; + cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_52AA_M; + cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_52AA; + cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_52AA_M; + cr->path0_r_trsw_s = PATH0_R_TRSW_S_52AA; + cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_52AA_M; + cr->path0_r_trsw_o = PATH0_R_TRSW_O_52AA; + cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_52AA_M; + cr->path0_r_trswb_o = PATH0_R_TRSWB_O_52AA; + cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_52AA_M; + cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_52AA; + cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_52AA_M; + cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_52AA; + cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_52AA_M; + cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_52AA; + cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_52AA_M; + cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_52AA; + cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_52AA_M; + cr->path0_r_antsel = PATH0_R_ANTSEL_52AA; + cr->path0_r_antsel_m = PATH0_R_ANTSEL_52AA_M; + cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__52AA; + cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__52AA_M; + cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__52AA; + cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__52AA_M; + cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__52AA; + cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__52AA_M; + cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__52AA; + cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_A; + cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_A_M; + cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_A; + cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_A_M; + cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_A; + cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_A_M; + cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_A; + cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_A_M; + cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_A; + cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_A_M; + cr->path0_r_trsw_s = PATH0_R_TRSW_S_A; + cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_A_M; + cr->path0_r_trsw_o = PATH0_R_TRSW_O_A; + cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_A_M; + cr->path0_r_trswb_o = PATH0_R_TRSWB_O_A; + cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_A_M; + cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_A; + cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_A_M; + cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_A; + cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_A_M; + cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_A; + cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_A_M; + cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_A; + cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_A_M; + cr->path0_r_antsel = PATH0_R_ANTSEL_A; + cr->path0_r_antsel_m = PATH0_R_ANTSEL_A_M; + cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__A; + cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__A_M; + cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__A; + cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__A_M; + cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__A; + cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__A_M; + cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__A; + cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_C; + cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_C_M; + cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_C; + cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_C_M; + cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_C; + cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_C_M; + cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_C; + cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_C_M; + cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_C; + cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_C_M; + cr->path0_r_trsw_s = PATH0_R_TRSW_S_C; + cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_C_M; + cr->path0_r_trsw_o = PATH0_R_TRSW_O_C; + cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_C_M; + cr->path0_r_trswb_o = PATH0_R_TRSWB_O_C; + cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_C_M; + cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_C; + cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_C_M; + cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_C; + cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_C_M; + cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_C; + cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_C_M; + cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_C; + cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_C_M; + cr->path0_r_antsel = PATH0_R_ANTSEL_C; + cr->path0_r_antsel_m = PATH0_R_ANTSEL_C_M; + cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__C; + cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__C_M; + cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__C; + cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__C_M; + cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__C; + cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__C_M; + cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__C; + cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__C_M; + break; + #endif + + default: + break; + } + +} + + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ant_div.h b/phl/hal_g6/phy/bb/halbb_ant_div.h new file mode 100644 index 0000000..577e6f3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ant_div.h @@ -0,0 +1,285 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_ANT_DIV_H__ +#define __HALBB_ANT_DIV_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define EVM_BASED_ANTDIV 0 +#define CN_BASED_ANTDIV 1 + +#define TP_MAX_DOMINATION 0 +#define TP_HIGHEST_DOMINATION 1 +#define TP_AVG_DOMINATION 2 + +#define ANTDIV_INIT 0xff +#define MAIN_ANT 1 /*@ant A or ant Main or S1*/ +#define AUX_ANT 2 /*@AntB or ant Aux or S0*/ +#define MAX_ANT 3 /* @3 for AP using*/ + +#define ANT1_2G 0 +/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 +/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ + +#define ANTDIV_MAX_STA_NUM PHL_MAX_STA_NUM +#define ANTDIV_RSSI_TH_HIGH 25 +#define ANTDIV_RSSI_TH_LOW 20 +#define ANTDIV_PERIOD 1 +#define ANTDIV_TRAINING_NUM 6 + +#define FORCE_RSSI_DIFF 10 + +#define ANTDIV_DELAY 1 +#define ANTDIV_INTVL 10 + +#define ANTDIV_DEC_TP_HIGH 100 +#define ANTDIV_DEC_TP_LOW 5 +#define ANTDIV_DEC_EVM 4 +#define TP_LOWER_BOUND 1 + +/* @Antenna Diversty Control type */ +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define ANT_PATH_A 0 +#define ANT_PATH_B 1 +#define ANT_PATH_AB 2 + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_antdiv_mode_t { + AUTO_ANT = 0, + FIX_MAIN_ANT = 1, + FIX_AUX_ANT = 2, +}; + +enum bb_tp_method_t { + TP_MAX = 0, + TP_HIGHEST = 1, + TP_AVG = 2, +}; + +enum bb_evm_method_t { + EVM_LINEAR_AVG = 0, + EVM_DB_AVG = 1, +}; + +enum bb_antdiv_method_t { + EVM_BASED = 0, + CN_BASED = 1, +}; + + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_antdiv_rssi_info { /*all in U(8,1)*/ + /*acc value*/ + u32 rssi_cck_avg_acc; + u32 rssi_ofdm_avg_acc; + u32 rssi_t_avg_acc; + u8 rssi_cck_avg; + u8 rssi_ofdm_avg; + u8 rssi_t_avg; + u8 rssi_final; + u16 pkt_cnt_t; + u16 pkt_cnt_cck; + u16 pkt_cnt_ofdm; +}; + +struct bb_antdiv_cn_info { + u32 main_cn_avg_acc; /*U(7,1)*/ + u32 aux_cn_avg_acc; /*U(7,1)*/ +}; + +struct bb_antdiv_evm_info { + u64 main_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/ + u64 main_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u64 main_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u64 aux_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/ + u64 aux_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u64 aux_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u8 evm_diff; + bool no_change_flag; +}; + +struct bb_antdiv_rate_info { + /*====[Phy rate counter main ant]=============================================*/ + u16 main_pkt_cnt_cck; + u16 main_pkt_cnt_ofdm; /*L-OFDM*/ + u16 main_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/ + u16 main_pkt_cnt_1ss; /*HT, VHT, HE*/ + u16 main_pkt_cnt_2ss; /*HT, VHT, HE*/ + /*Legacy*/ + u16 main_pkt_cnt_legacy[LEGACY_RATE_NUM]; + /*HT*/ + u16 main_pkt_cnt_ht[HT_RATE_NUM]; + /*VHT*/ + u16 main_pkt_cnt_vht[VHT_RATE_NUM]; + /*HE*/ + u16 main_pkt_cnt_he[HE_RATE_NUM]; + + u16 main_max_cnt; + u16 main_max_idx; + /*====[Phy rate counter] aux ant=============================================*/ + u16 aux_pkt_cnt_cck; + u16 aux_pkt_cnt_ofdm; /*L-OFDM*/ + u16 aux_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/ + u16 aux_pkt_cnt_1ss; /*HT, VHT, HE*/ + u16 aux_pkt_cnt_2ss; /*HT, VHT, HE*/ + /*Legacy*/ + u16 aux_pkt_cnt_legacy[LEGACY_RATE_NUM]; + /*HT*/ + u16 aux_pkt_cnt_ht[HT_RATE_NUM]; + /*VHT*/ + u16 aux_pkt_cnt_vht[VHT_RATE_NUM]; + /*HE*/ + u16 aux_pkt_cnt_he[HE_RATE_NUM]; + + u16 aux_max_cnt; + u16 aux_max_idx; + u16 main_cnt_all; + u16 aux_cnt_all; + + u64 main_tp; + u64 aux_tp; + u64 tp_diff; + + bool no_change_flag; + bool main_ht_pkt_not_zero; + bool main_vht_pkt_not_zero; + bool main_he_pkt_not_zero; + bool aux_ht_pkt_not_zero; + bool aux_vht_pkt_not_zero; + bool aux_he_pkt_not_zero; +}; + +struct bb_antdiv_cr_info { + u32 path0_r_ant_train_en; + u32 path0_r_ant_train_en_m; + u32 path0_r_tx_ant_sel; + u32 path0_r_tx_ant_sel_m; + u32 path0_r_rfe_buf_en; + u32 path0_r_rfe_buf_en_m; + u32 path0_r_lnaon_agc; + u32 path0_r_lnaon_agc_m; + u32 path0_r_trsw_bit_bt; + u32 path0_r_trsw_bit_bt_m; + u32 path0_r_trsw_s; + u32 path0_r_trsw_s_m; + u32 path0_r_trsw_o; + u32 path0_r_trsw_o_m; + u32 path0_r_trswb_o; + u32 path0_r_trswb_o_m; + u32 path0_r_bt_force_antidx; + u32 path0_r_bt_force_antidx_m; + u32 path0_r_bt_force_antidx_en; + u32 path0_r_bt_force_antidx_en_m; + u32 path0_r_ant_module_rfe_opt; + u32 path0_r_ant_module_rfe_opt_m; + u32 path0_r_rfsw_tr; + u32 path0_r_rfsw_tr_m; + u32 path0_r_antsel; + u32 path0_r_antsel_m; + u32 path0_r_rfsw_ant_31_0; + u32 path0_r_rfsw_ant_31_0_m; + u32 path0_r_rfsw_ant_63_32; + u32 path0_r_rfsw_ant_63_32_m; + u32 path0_r_rfsw_ant_95_64; + u32 path0_r_rfsw_ant_95_64_m; + u32 path0_r_rfsw_ant_127_96; + u32 path0_r_rfsw_ant_127_96_m; +}; + +struct bb_antdiv_info { + struct bb_antdiv_cr_info bb_antdiv_cr_i; + /* For CN cacluation */ + struct bb_antdiv_cn_info bb_cn_i; + /* For EVM cacluation */ + struct bb_antdiv_evm_info bb_evm_i; + /* For MCS cacluation */ + struct bb_antdiv_rate_info bb_rate_i; + /* For RSSI */ + struct bb_antdiv_rssi_info bb_rssi_i; + + enum bb_antdiv_mode_t antdiv_mode; + enum bb_antdiv_method_t antdiv_method; + enum bb_antdiv_mode_t pre_antdiv_mode; + enum bb_timer_cfg_t bb_antdiv_timer_state; + enum bb_tp_method_t tp_decision_method; + enum bb_evm_method_t evm_decision_method; + + /* Training state & period related*/ + u8 antdiv_wd_cnt; + u8 antdiv_training_state_cnt; + u32 antdiv_intvl; + u32 antdiv_timer_ms; + u32 antdiv_delay; + u32 antdiv_train_num; + u8 antdiv_period; + u8 tp_lb; + + /* antenna setting */ + u8 pre_target_ant; + u8 training_ant; + u8 target_ant; + u8 target_ant_cn; + u8 target_ant_evm; + u8 target_ant_tp; + + /* Decision*/ + u16 tp_diff_th_high; + u16 tp_diff_th_low; + u8 evm_diff_th; + + /*Phy-sts related */ + bool get_stats; + bool antdiv_use_ctrl_frame; + +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_antdiv_timers(struct bb_info *bb, enum bb_timer_cfg_t bb_antdiv_timer_state); +void halbb_cr_cfg_antdiv_init(struct bb_info *bb); +void halbb_antdiv_reg_init(struct bb_info *bb); +void halbb_antdiv_deinit(struct bb_info *bb); +void halbb_antdiv_init(struct bb_info *bb); +void halbb_antdiv_reset(struct bb_info *bb); +void halbb_antdiv_reset_training_stat(struct bb_info *bb); +void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant); +void halbb_antdiv_get_highest_mcs(struct bb_info *bb); +void halbb_antdiv_get_evm_target_ant(struct bb_info *bb); +void halbb_antdiv_training_state(struct bb_info *bb); +void halbb_antdiv_decision_state(struct bb_info *bb); +void halbb_evm_based_antdiv(struct bb_info *bb); +void halbb_antenna_diversity(struct bb_info *bb); +void halbb_antdiv_phy_sts(struct bb_info *bb); +void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_api.c b/phl/hal_g6/phy/bb/halbb_api.c new file mode 100644 index 0000000..555fe91 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_api.c @@ -0,0 +1,2331 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "halbb_precomp.h" + +void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_dyn_1r_cca_en_8852a_2(bb, en); + break; + #endif + default: + break; + } +} + +u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx) +{ + struct rtw_hw_band *hw_band = &bb->hal_com->band[phy_idx]; + u8 pause_result = 0; + u32 val[5] = {0}; + char val_char = '0'; + + BB_DBG(bb, DBG_DIG, "[%s] event=%d\n", __func__, event); + + if (event == MSG_EVT_SCAN_START || event == MSG_EVT_CONNECT_START) { + val[0] = 90; + if (hw_band->cur_chandef.band == BAND_ON_24G) + val[1] = PAUSE_OFDM_CCK; + else + val[1] = PAUSE_OFDM; + pause_result = halbb_pause_func(bb, F_DIG, HALBB_PAUSE, HALBB_PAUSE_LV_2, 2, val); + halbb_edcca_event_nofity(bb, HALBB_PAUSE); + } else if (event == MSG_EVT_SCAN_END) { + pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2, val); + halbb_edcca_event_nofity(bb, HALBB_RESUME); + } else if (event == MSG_EVT_CONNECT_END) { + pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME_NO_RECOVERY, HALBB_PAUSE_LV_2, 2, val); + halbb_edcca_event_nofity(bb, HALBB_RESUME_NO_RECOVERY); + halbb_dig_new_entry_connect(bb); + } else if (event == MSG_EVT_DBG_RX_DUMP || event == MSG_EVT_DBG_TX_DUMP) { + halbb_dump_bb_reg(bb, &val[0], &val_char, &val[0], false); + halbb_dump_bb_reg(bb, &val[0], &val_char, &val[0], false); + } + + return pause_result; +} + +#ifdef BB_8852B_SUPPORT + +bool halbb_rf_sw_si_test(struct bb_info *bb, enum rf_path rx_path, u8 reg_addr, int ch_idx) +{ + u32 channel_change[3] = {0x1, 0x24, 0x99}; + u32 ofdm_rx = 0x0, reg_value_0 = 0x0, reg_value_1 = 0x0; + ofdm_rx = (u32)rx_path; + + ch_idx = ch_idx % 3; + + if (ofdm_rx == RF_PATH_A) { + halbb_write_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff, channel_change[ch_idx]); + + reg_value_0 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff); + BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_0); + + if (reg_value_0 == channel_change[ch_idx]){ + return true; + } else { + return false; + } + + } else if (ofdm_rx == RF_PATH_B) { + + halbb_write_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff, channel_change[ch_idx]); + + reg_value_1 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff); + BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_1); + + if (reg_value_1 == channel_change[ch_idx]){ + return true; + } else { + return false; + } + + } else { + + halbb_write_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff, channel_change[ch_idx]); + halbb_write_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff, channel_change[ch_idx]); + + reg_value_0 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff); + reg_value_1 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff); + BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_0); + BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_1); + + if ((reg_value_0 == channel_change[ch_idx]) && (reg_value_1 == channel_change[ch_idx])) { + return true; + } else { + return false; + } + + } +} + +#endif +u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx) + +{ + u8 table_size = 0; + u8 i; + u8 txsc_2_buf_idx_160[][2] = {{0, 0}, //BW all + {8, 1}, //20M + {6, 3}, + {4, 2}, + {2, 4}, + {1, 5}, + {3, 7}, + {5, 6}, + {7, 8}, + {12, 9}, //40M + {10, 10}, + {9, 11}, + {11, 12}, + {14, 13}, //80M + {13, 14}}; + u8 txsc_2_buf_idx_080[][2] = {{0, 0}, //BW all + {4, 1}, //20M + {2, 3}, + {1, 2}, + {3, 4}, + {10, 9}, //40M + {9, 10}}; + u8 csi_sub_idx = 0xff; + u16 rpt_val = 0; + + if (bb->ic_type & BB_IC_MAX_BW_160) { + table_size = sizeof(txsc_2_buf_idx_160) / (sizeof(u8) * 2); + for (i = 0; i < table_size; i++) { + if (txsc_2_buf_idx_160[i][0] == txsc_idx) { + csi_sub_idx = txsc_2_buf_idx_160[i][1]; + break; + } + } + } else { + table_size = sizeof(txsc_2_buf_idx_080) / (sizeof(u8) * 2); + for (i = 0; i < table_size; i++) { + if (txsc_2_buf_idx_080[i][0] == txsc_idx) { + csi_sub_idx = txsc_2_buf_idx_080[i][1]; + break; + } + } + } + + BB_DBG(bb, DBG_DBG_API, "%02d -> %02d\n", txsc_idx, csi_sub_idx); + + if (csi_sub_idx == 0xff) { + rpt_val = 0xff; + } else { + rpt_val = (buf_idx << 6) | (csi_sub_idx << 2); + } + + return rpt_val; +} + +u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path) +{ + u16 val = 0; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + val = halbb_cfg_cmac_tx_ant_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + val = halbb_cfg_cmac_tx_ant_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + val = halbb_cfg_cmac_tx_ant_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + val = halbb_cfg_cmac_tx_ant_8852c(bb, tx_path); + break; + #endif + + default: + break; + } + return val; +} + + +void halbb_gpio_ctrl_dump(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_ctrl_dump_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_ctrl_dump_8852a_2(bb); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + //halbb_gpio_ctrl_dump_8852b(bb); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_ctrl_dump_8852c(bb); + break; + #endif + + default: + break; + } +} + +void halbb_gpio_rfm(struct bb_info *bb, enum bb_path path, + enum bb_rfe_src_sel src, bool dis_tx_gnt_wl, + bool active_tx_opt, bool act_bt_en, u8 rfm_output_val) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_rfm_8852a(bb, path, src, dis_tx_gnt_wl, active_tx_opt, + act_bt_en, rfm_output_val); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_rfm_8852a_2(bb, path, src, dis_tx_gnt_wl, active_tx_opt, + act_bt_en, rfm_output_val); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_rfm_8852c(bb, path, src, dis_tx_gnt_wl, active_tx_opt, + act_bt_en, rfm_output_val); + break; + #endif + + default: + break; + } +} + +void halbb_gpio_trsw_table(struct bb_info *bb, enum bb_path path, + bool path_en, bool trsw_tx, bool trsw_rx, + bool trsw, bool trsw_b) +{ + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_trsw_table_8852a(bb, path, path_en, trsw_tx, trsw_rx, + trsw, trsw_b); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_trsw_table_8852a_2(bb, path, path_en, trsw_tx, + trsw_rx, trsw, trsw_b); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_trsw_table_8852c(bb, path, path_en, trsw_tx, + trsw_rx, trsw, trsw_b); + break; + #endif + + default: + break; + } + +} + +void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_setting_init_8852a(bb); + halbb_gpio_setting_all_8852a(bb, rfe_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_setting_init_8852a_2(bb); + halbb_gpio_setting_all_8852a_2(bb, rfe_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_setting_init_8852c(bb); + halbb_gpio_setting_all_8852c(bb, rfe_idx); + break; + #endif + + default: + break; + } +} + +void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path, + bool inv, enum bb_rfe_src_sel src) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_setting_8852a(bb, gpio_idx, path, inv, src); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_setting_8852a_2(bb, gpio_idx, path, inv, src); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_setting_8852c(bb, gpio_idx, path, inv, src); + break; + #endif + + default: + break; + } +} + +void halbb_gpio_setting_init(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_gpio_setting_init_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_gpio_setting_init_8852a_2(bb); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_gpio_setting_init_8852c(bb); + break; + #endif + + default: + break; + } +} + +void halbb_pre_agc_en(struct bb_info *bb, bool enable) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_pre_agc_en_8852a(bb, enable); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_pre_agc_en_8852a_2(bb, enable); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_pre_agc_en_8852b(bb, enable); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_pre_agc_en_8852c(bb, enable); + break; + #endif + + default: + break; + } +} + +void halbb_set_gain_error(struct bb_info *bb, u8 central_ch) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_set_gain_error_8852a_2(bb, central_ch); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_set_gain_error_8852b(bb, central_ch); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_set_gain_error_8852c(bb, central_ch); + break; + #endif + + default: + break; + } +} + +u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type) +{ + struct rtw_hal_com_t *hal_i = bb->hal_com; + u8 i = 0; + bool trx_idle_success = false; + u32 dp = 0; + + if (set_type == HALBB_SET) { + /*[Stop TRX]---------------------------------------------------------*/ + if (bb->ic_type & BB_IC_AX_SERIES) { + /*set debug port to 0x0*/ + if (!halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + return HALBB_SET_FAIL; + } + halbb_set_bb_dbg_port_ip(bb, DBGPORT_IP_TD); + halbb_set_bb_dbg_port(bb, 0x205); + + for (i = 0; i < 100; i++) { + dp = halbb_get_bb_dbg_port_val(bb); + /* CCA_all && mux_state*/ + if ((dp & 0x80000f00) == 0) { + BB_DBG(bb, DBG_DBG_API, "Stop trx wait for (%d) times\n", i); + trx_idle_success = true; + break; + } + halbb_delay_ms(bb, 1); + } + halbb_release_bb_dbg_port(bb); + } + + if (trx_idle_success) { + /*pause all TX queue*/ + rtw_hal_tx_pause(hal_i, 0, true, PAUSE_RSON_PSD); + rtw_hal_tx_pause(hal_i, 1, true, PAUSE_RSON_PSD); + halbb_ctrl_rx_cca(bb, false, HW_PHY_0); + halbb_ctrl_rx_cca(bb, false, HW_PHY_1); + } else { + return HALBB_SET_FAIL; + } + + return HALBB_SET_SUCCESS; + + } else { /*@if (set_type == HALBB_REVERT)*/ + /*Release all TX queue*/ + rtw_hal_tx_pause(hal_i, 0, false, PAUSE_RSON_PSD); + rtw_hal_tx_pause(hal_i, 1, false, PAUSE_RSON_PSD); + halbb_ctrl_rx_cca(bb, true, HW_PHY_0); + halbb_ctrl_rx_cca(bb, true, HW_PHY_1); + + return HALBB_SET_SUCCESS; + } +} + +u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width cbw, enum channel_width dbw) +{ + u8 txsc_idx = 0; + u8 tmp = 0; + u8 ofst = 0; + + if ((cbw == dbw) || (cbw == CHANNEL_WIDTH_20)) { + txsc_idx = 0; + BB_DBG(bb, DBG_PHY_CONFIG, "[TXSC] TxSC_idx = %d\n", txsc_idx); + return txsc_idx; + } + + switch (cbw) { + case CHANNEL_WIDTH_40: + txsc_idx = pri_ch > central_ch ? 1 : 2; + break; + case CHANNEL_WIDTH_80: + if (dbw == CHANNEL_WIDTH_20) { + if (pri_ch > central_ch) + txsc_idx = (pri_ch - central_ch) >> 1; + else + txsc_idx = ((central_ch - pri_ch) >> 1) + 1; + } else { + txsc_idx = pri_ch > central_ch ? 9 : 10; + } + break; + case CHANNEL_WIDTH_160: + if (pri_ch > central_ch) + tmp = (pri_ch - central_ch) >> 1; + else + tmp = ((central_ch - pri_ch) >> 1) + 1; + + if (dbw == CHANNEL_WIDTH_20) { + txsc_idx = tmp; + } else if (dbw == CHANNEL_WIDTH_40) { + if ((tmp == 1) || (tmp == 3)) + txsc_idx = 9; + else if ((tmp == 5) || (tmp == 7)) + txsc_idx = 11; + else if ((tmp == 2) || (tmp == 4)) + txsc_idx = 10; + else if ((tmp == 6) || (tmp == 8)) + txsc_idx = 12; + else + return 0xff; + } else { + txsc_idx = pri_ch > central_ch ? 13 : 14; + } + break; + case CHANNEL_WIDTH_80_80: + if (dbw == CHANNEL_WIDTH_20) { + if (pri_ch > central_ch) + txsc_idx = (10 - (pri_ch - central_ch)) >> 1; + else + txsc_idx = ((central_ch - pri_ch) >> 1) + 5; + } else if (dbw == CHANNEL_WIDTH_40) { + txsc_idx = pri_ch > central_ch ? 10 : 12; + } else { + txsc_idx = 14; + } + default: + break; + } + BB_DBG(bb, DBG_PHY_CONFIG, "[TXSC] TxSC_idx = %d\n", txsc_idx); + return txsc_idx; +} + +void halbb_reset_adc(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_adc_rst_8852a(bb); + break; + #endif + + default: + break; + } +} + +void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_bb_reset_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_bb_reset_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_bb_reset_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_bb_reset_8852c(bb, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_reset_bb(struct bb_info *bb) +{ + halbb_reset_bb_phy(bb, HW_PHY_0); + + if (bb->hal_com->dbcc_en) + halbb_reset_bb_phy(bb, HW_PHY_1); +} + +void halbb_tssi_bb_reset(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_tssi_bb_reset_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_tssi_bb_reset_8852a_2(bb); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_tssi_bb_reset_8852c(bb); + break; + #endif + + default: + break; + } +} + +u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask) +{ + u32 val = 0; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + val = halbb_read_rf_reg_8852a(bb, path, addr, mask); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + val = halbb_read_rf_reg_8852a_2(bb, path, addr, mask); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + val = halbb_read_rf_reg_8852b(bb, path, addr, mask); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + val = halbb_read_rf_reg_8852c(bb, path, addr, mask); + break; + #endif + + + default: + val = 0; + break; + } + + return val; +} + +bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask, + u32 data) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_write_rf_reg_8852a(bb, path, addr, mask, data); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_write_rf_reg_8852a_2(bb, path, addr, mask, data); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_write_rf_reg_8852b(bb, path, addr, mask, data); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_write_rf_reg_8852c(bb, path, addr, mask, data); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 mask, u32 data) +{ + bool rpt = false; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_rf_write_bb_reg_8852a_2(bb, addr, mask, data); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_rf_write_bb_reg_8852b(bb, addr, mask, data); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_rf_write_bb_reg_8852c(bb, addr, mask, data); + break; + #endif + + default: + break; + } + + if (bb->bb_dbg_i.cr_recorder_rf_en) + BB_TRACE("[RF][W] 0x%04x[0x%08x] = 0x%08x\n", addr, mask, data); + + if (!rpt) + BB_WARNING("[%s][IQK]error IO 0x%x\n", __func__, addr); + + return rpt; +} + +u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask) +{ + u32 val = 0; + + val = halbb_get_reg(bb, addr, mask); + + if (bb->bb_dbg_i.cr_recorder_rf_en) + BB_TRACE("[RF][R] 0x%04x[0x%08x] = 0x%08x\n", addr, mask, val); + + return val; +} + +void halbb_dfs_en(struct bb_info *bb, bool en) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_dfs_en_8852a_2(bb, en); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + //halbb_dfs_en_8852b(bb, en); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_dfs_en_8852c(bb, en); + break; + #endif + + default: + break; + } +} + +void halbb_adc_en(struct bb_info *bb, bool en) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_adc_en_8852a_2(bb, en); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_adc_en_8852b(bb, en); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_adc_en_8852c(bb, en); + break; + #endif + + default: + break; + } +} + +void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_tssi_cont_en_8852a_2(bb, en, path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_tssi_cont_en_8852b(bb, en, path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_tssi_cont_en_8852c(bb, en, path); + break; + #endif + + default: + break; + } +} + +void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_bb_reset_en_8852a_2(bb, en, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_bb_reset_en_8852b(bb, en, phy_idx); + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_bb_reset_en_8852a_2(bb, en, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_rf_mode_8852a(bb, mode); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_rf_mode_8852a_2(bb, mode); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_rf_mode_8852b(bb, mode); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_rf_mode_8852c(bb, mode); + break; + #endif + + default: + break; + } +} + +bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_rx_path_8852a(bb, rx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_ctrl_rx_path_8852a_2(bb, rx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_ctrl_rx_path_8852b(bb, rx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_ctrl_rx_path_8852c(bb, rx_path); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_ctrl_tx_path(struct bb_info *bb, enum rf_path tx_path) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_tx_path_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_ctrl_tx_path_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_ctrl_tx_path_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_ctrl_tx_path_8852c(bb, tx_path); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss, + enum rf_path rx_path, u8 rx_nss) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_trx_path_8852a(bb, tx_path, tx_nss, rx_path, rx_nss); + break; + #endif + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_trx_path_8852a_2(bb, tx_path, tx_nss, rx_path, rx_nss); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_trx_path_8852b(bb, tx_path, tx_nss, rx_path, rx_nss); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_trx_path_8852c(bb, tx_path, tx_nss, rx_path, rx_nss); + break; + #endif + + default: + break; + } + +} + +bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx) +{ + bool rpt = true; + struct bb_api_info *bb_api = &bb->bb_api_i; + + bb_api->pri_ch_idx = pri_ch; + bb_api->bw = bw; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_bw_8852a(bb, pri_ch, bw, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_ctrl_bw_8852a_2(bb, pri_ch, bw, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_ctrl_bw_8852b(bb, pri_ch, bw, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_ctrl_bw_8852c(bb, pri_ch, bw, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_ctrl_ch(struct bb_info *bb, u8 central_ch, enum band_type band, + enum phl_phy_idx phy_idx) +{ + bool rpt = true; + struct bb_api_info *bb_api = &bb->bb_api_i; + + bb_api->central_ch = central_ch; + bb_api->band = band; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_ch_8852a(bb, central_ch, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_ctrl_ch_8852a_2(bb, central_ch, band, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_ctrl_ch_8852b(bb, central_ch, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_ctrl_ch_8852c(bb, central_ch, band, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_ctrl_ch2_80p80(struct bb_info *bb, u8 central_ch) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_ch2_80p80_8852a(bb, central_ch); + break; + #endif + #if 0//def BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_ctrl_ch2_80p80_8852a_2(bb, central_ch); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0, + u8 central_ch_seg1, enum band_type band, + enum channel_width bw, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_ctrl_bw_ch_8852a(bb, pri_ch, central_ch_seg0, bw, + phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + #ifdef HALBB_FW_OFLD_SUPPORT + if (halbb_check_fw_ofld(bb)) { + BB_WARNING("Do FW offload at Channel switch\n"); + rpt = halbb_fwofld_bw_ch_8852a_2(bb, pri_ch, central_ch_seg0, + bw, phy_idx); + } + else + rpt = halbb_ctrl_bw_ch_8852a_2(bb, pri_ch, + central_ch_seg0, bw, + band, phy_idx); + #else + rpt = halbb_ctrl_bw_ch_8852a_2(bb, pri_ch, central_ch_seg0, bw, + band, phy_idx); + #endif + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_ctrl_bw_ch_8852b(bb, pri_ch, central_ch_seg0, bw, + band, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_ctrl_bw_ch_8852c(bb, pri_ch, central_ch_seg0, bw, + band, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + + +void halbb_ctrl_dbcc(struct bb_info *bb, bool dbcc_enable) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_dbcc_8852a(bb, dbcc_enable); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_dbcc_8852a_2(bb, dbcc_enable); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_dbcc_8852c(bb, dbcc_enable); + break; + #endif + + default: + break; + } +} + +void halbb_cfg_dbcc(struct bb_info *bb, bool dbcc_enable) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_cfg_dbcc_8852a(bb, dbcc_enable); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_cfg_dbcc_8852a_2(bb, dbcc_enable); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_cfg_dbcc_8852c(bb, dbcc_enable); + break; + #endif + + default: + break; + } +} + +void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_rx_cca_8852a(bb, cca_en, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_rx_cca_8852a_2(bb, cca_en, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_rx_cca_8852b(bb, cca_en, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_rx_cca_8852c(bb, cca_en, phy_idx); + break; + #endif + + default: + break; + } +} +void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_cck_en_8852a(bb, cck_enable, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_cck_en_8852a_2(bb, cck_enable, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_cck_en_8852b(bb, cck_enable, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_cck_en_8852c(bb, cck_enable, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ctrl_ofdm_en_8852a(bb, ofdm_enable, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_ofdm_en_8852a_2(bb, ofdm_enable, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_ofdm_en_8852b(bb, ofdm_enable, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_ofdm_en_8852c(bb, ofdm_enable, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_ctrl_btg(struct bb_info *bb, bool btg) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_btg_8852a_2(bb, btg); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_btg_8852b(bb, btg); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_btg_8852c(bb, btg); + break; + #endif + + default: + break; + } +} + +void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ctrl_btc_preagc_8852a_2(bb, bt_en); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ctrl_btc_preagc_8852b(bb, bt_en); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ctrl_btc_preagc_8852c(bb, bt_en); + break; + #endif + + default: + break; + } +} + +void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_pop_en_8852a_2(bb, en, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_pop_en_8852b(bb, en, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_pop_en_8852c(bb, en, phy_idx); + break; + #endif + + default: + break; + } +} + +bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_querry_pop_en_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_querry_pop_en_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_querry_pop_en_8852c(bb, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound, + enum channel_width bw, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + struct bb_api_info *bb_api = &bb->bb_api_i; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_pd_lower_bound_8852a_2(bb, bound, bw, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_pd_lower_bound_8852b(bb, bound, bw, phy_idx); + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_pd_lower_bound_8852c(bb, bound, bw, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound, + enum channel_width bw, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + struct bb_api_info *bb_api = &bb->bb_api_i; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_pd_lower_bound_cck_8852a_2(bb, bound, bw, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_pd_lower_bound_cck_8852b(bb, bound, bw, phy_idx); + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_pd_lower_bound_cck_8852c(bb, bound, bw, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + + +u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info, + enum phl_phy_idx phy_idx) +{ + u8 rpt = 0; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_querry_pd_lower_bound_8852a_2(bb, get_en_info, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_querry_pd_lower_bound_8852b(bb, get_en_info, phy_idx); + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_querry_pd_lower_bound_8852c(bb, get_en_info, phy_idx); + break; + #endif + default: + rpt = 0; + break; + } + + return rpt; +} + +u8 halbb_get_losel(struct bb_info *bb) +{ + u8 rpt = 0xff; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_losel_8852a_2(bb); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_losel_8852c(bb); + break; + #endif + + default: + rpt = 0xff; + break; + } + + return rpt; +} + + +void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx, + enum rf_path path) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_set_igi_8852a(bb, lna_idx, tia_idx, rxbb_idx, path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_set_igi_8852a_2(bb, lna_idx, tia_idx, rxbb_idx, path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_set_igi_8852b(bb, lna_idx, tia_idx, rxbb_idx, path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_set_igi_8852c(bb, lna_idx, tia_idx, rxbb_idx, path); + break; + #endif + + default: + break; + } +} + +void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch, + bool is_ofdm, enum phl_phy_idx phy_idx) { + + struct rtw_tpu_info *tpu = &bb->hal_com->band[phy_idx].rtw_tpu_i; + u8 shape_idx = tpu->tx_ptrn_shap_idx; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + if (is_ofdm) + halbb_tx_triangular_shap_cfg_8852a_2(bb, shape_idx, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + if (is_ofdm) + halbb_tx_triangular_shap_cfg_8852b(bb, shape_idx, phy_idx); + else + halbb_tx_dfir_shap_cck_8852b(bb, ch, shape_idx, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + if (is_ofdm) + halbb_tx_triangular_shap_cfg_8852c(bb, shape_idx, phy_idx); + //else + // halbb_tx_dfir_shap_cck_8852c(bb, ch, shape_idx, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct rtw_tpu_info *tpu = &bb->hal_com->band[phy_idx].rtw_tpu_i; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + + rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx); + + halbb_set_tx_pow_ref_8852a_2(bb, tpu->ref_pow_ofdm, + tpu->ref_pow_cck, + tpu->ofst_int, + tpu->base_cw_0db, + tpu->tssi_16dBm_cw, + &tpu->ref_pow_ofdm_cw, + &tpu->ref_pow_cck_cw, + phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx); + + halbb_set_tx_pow_ref_8852b(bb, tpu->ref_pow_ofdm, + tpu->ref_pow_cck, + tpu->ofst_int, + tpu->base_cw_0db, + tpu->tssi_16dBm_cw, + &tpu->ref_pow_ofdm_cw, + &tpu->ref_pow_cck_cw, + phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx); + + halbb_set_tx_pow_ref_8852c(bb, tpu->ref_pow_ofdm, + tpu->ref_pow_cck, + tpu->ofst_int, + tpu->base_cw_0db, + tpu->tssi_16dBm_cw, + &tpu->ref_pow_ofdm_cw, + &tpu->ref_pow_cck_cw, + phy_idx); + break; + #endif + + + default: + break; + } +} + +void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_normal_efuse_verify_8852a_2(bb, rx_gain_offset, rx_path, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_normal_efuse_verify_8852b(bb, rx_gain_offset, rx_path, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_normal_efuse_verify_8852c(bb, rx_gain_offset, rx_path, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_normal_efuse_verify_cck_8852a_2(bb, rx_gain_offset, + rx_path, phy_idx); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_normal_efuse_verify_cck_8852b(bb, rx_gain_offset, + rx_path, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_normal_efuse_verify_cck_8852c(bb, rx_gain_offset, + rx_path, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_rx_setting(struct bb_info *bb, u8 patch_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_rx_setting_8852a(bb, patch_idx); + break; + #endif + #if 0//def BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_rx_setting_8852b(bb, patch_idx) + break; + #endif + + #if 0//def BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_rx_setting_8852c(bb, patch_idx) + break; + #endif + default: + break; + } +} + +void halbb_ic_hw_setting_non_io(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + #ifdef BB_DYN_1R_CCA + bb->bb_8852a_2_i.dyn_1r_cca_cfg = RF_PATH_ABCD; + #endif + break; + #endif + + default: + break; + } +} + +void halbb_ic_hw_setting_low_io(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + #ifdef BB_DYN_1R_CCA + bb->bb_8852a_2_i.dyn_1r_cca_cfg = RF_PATH_ABCD; + #endif + break; + #endif + + default: + break; + } +} + +void halbb_ic_hw_setting(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ic_hw_setting_8852a_2(bb); + #ifdef HALBB_DYN_CSI_RSP_SUPPORT + halbb_dyn_csi_rsp_main(bb); + #endif + #ifdef BB_DYN_1R_CCA + halbb_dyn_1r_cca_8852a_2(bb); + #endif + #ifdef BB_DYN_CFO_TRK_LOP + halbb_dyn_cfo_trk_loop(bb); + #endif + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + //halbb_ic_hw_setting_8852b(bb); + #ifdef HALBB_DYN_CSI_RSP_SUPPORT + halbb_dyn_csi_rsp_main(bb); + #endif + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ic_hw_setting_8852c(bb); + break; + #endif + + default: + break; + } +} + +void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len) +{ + u32 val[5] = {0}; + u8 i = 0, j = 0; + enum rf_path cca_path; +#ifdef BB_DYN_CFO_TRK_LOP + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i; +#endif + + if (_os_strcmp(input[1], "-h") == 0) { +#ifdef BB_DYN_1R_CCA + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "1r_cca en {0/1}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "1r_cca force {1:A, 2:B, 3:AB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "1r_cca diff_th {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "1r_cca min_th {val}\n"); +#endif +#ifdef BB_DYN_CFO_TRK_LOP + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_trk en {0/1}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_trk force {0:SNR, 1:link}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_trk para {0:SNR, 1:link} {data_val} {pilot_val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_trk snr_th {th_l} {th_h}\n"); +#endif + return; + } + +#ifdef BB_DYN_CFO_TRK_LOP + if (_os_strcmp(input[1], "cfo_trk") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + + if (_os_strcmp(input[2], "en") == 0) { + halbb_dyn_cfo_trk_loop_en(bb, (bool)val[0]); + } else if (_os_strcmp(input[2], "force") == 0) { + halbb_dyn_cfo_trk_loop_en(bb, false); + + if (val[0] == 0) + halbb_cfo_trk_loop_cr_cfg(bb, DCTL_SNR); + else if (val[0] == 1) + halbb_cfo_trk_loop_cr_cfg(bb, DCTL_LINK); + else + return; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Force state=%d\n", val[0]); + } else if (_os_strcmp(input[2], "para") == 0) { + HALBB_SCAN(input[4], DCMD_HEX, &val[1]); + HALBB_SCAN(input[5], DCMD_HEX, &val[2]); + + if (val[0] >= 2) + return; + + dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_data = (u8)val[1]; + dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_pilot = (u8)val[2]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "state:%d, dctl_data=0x%x, dctl_pilot=0x%x\n", val[0], + dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_data, + dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_pilot); + + } else if (_os_strcmp(input[2], "snr_th") == 0) { + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + + dctl->dctl_snr_th_l = (u16)val[0] << RSSI_MA_H; + dctl->dctl_snr_th_h = (u16)val[1] << RSSI_MA_H; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dctl_snr_th_{l/h}={%d/%d}\n", + val[0], val[1]); + } + } else +#endif +#ifdef BB_DYN_1R_CCA + if (_os_strcmp(input[1], "1r_cca") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + if (_os_strcmp(input[2], "en") == 0) { + halbb_dyn_1r_cca_en_8852a_2(bb, (bool)val[0]); + } else if (_os_strcmp(input[2], "force") == 0) { + halbb_dyn_1r_cca_en_8852a_2(bb, false); + + if (val[0] == 1) + cca_path = RF_PATH_A; + else if (val[0] == 2) + cca_path = RF_PATH_B; + else if (val[0] == 3) + cca_path = RF_PATH_AB; + else + return; + halbb_dyn_1r_cca_cfg_8852a_2(bb, cca_path); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Force cca_path=%d\n", cca_path); + } else if (_os_strcmp(input[2], "diff_th") == 0) { + bb->bb_8852a_2_i.dyn_1r_cca_rssi_diff_th= (u16)(val[0] << 5); + } else if (_os_strcmp(input[2], "min_th") == 0) { + bb->bb_8852a_2_i.dyn_1r_cca_rssi_min_th= (u16)(val[0] << 5); + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Dyn 1R CCA]en=%d, diff_th=%d, min_th=%d\n", + bb->bb_8852a_2_i.dyn_1r_cca_en, + bb->bb_8852a_2_i.dyn_1r_cca_rssi_diff_th >> 5, + bb->bb_8852a_2_i.dyn_1r_cca_rssi_min_th >> 5); + } else +#endif + { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} + +void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 tmp = 0, i = 0; + u32 j = 0; + #ifdef BB_8852B_SUPPORT + bool judge_f; + #endif + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "trx_path {tx_path} {tx_nss} {rx_path} {rx_nss}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "igi ({lna_idx (0~6)} {tia_idx (0~1)} {rxbb_idx (0~31)} {path (0~1)})\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Rx_setting({patch_idx (0:default, 1:patch-1, 2:patch-2)})\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rfe dump\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rfe all {rfe_idx}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rfe cmn {gpio_idx} {path} {inv} {src}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rfe rfm {path} {src} {dis_tx} {ac_tx} {ac_bt} {val}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rfe trsw {path} {path_en} {trsw_tx} {trsw_rx} {trsw} {trsw_b}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rf sw_si rw {run_idx} {rx_path} {reg_addr}\n"); + } else if (_os_strcmp(input[1], "trx_path") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]); + halbb_ctrl_trx_path(bb, (enum rf_path)val[0], (u8)val[1], + (enum rf_path)val[2], (u8)val[3]); + + } else if (_os_strcmp(input[1], "igi") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]); + + if (val[0] > 6) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Invalid LNA index!\n"); + } else if (val[1] > 1) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Invalid TIA index!\n"); + } else if (val[2] > 31) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Invalid RxBB index!\n"); + } else { + halbb_set_igi(bb, (u8)val[0], (bool)val[1], (u8)val[2], + (enum rf_path)val[3]); + } + } else if (_os_strcmp(input[1], "rx_setting") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + if (val[0] > 2) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Invalid Patch index!\n"); + return; + } + halbb_rx_setting(bb, (u8)val[0]); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Rx setting Patch-%d Success!\n", val[0]); + } else if (_os_strcmp(input[1], "rfe") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[6], DCMD_DECIMAL, &val[3]); + HALBB_SCAN(input[7], DCMD_DECIMAL, &val[4]); + HALBB_SCAN(input[8], DCMD_DECIMAL, &val[5]); + if (_os_strcmp(input[2], "dump") == 0) { + halbb_gpio_ctrl_dump(bb); + } else if (_os_strcmp(input[2], "all") == 0) { + //HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + halbb_gpio_setting_all(bb, (u8)val[0]); + } else if (_os_strcmp(input[2], "trsw") == 0) { + halbb_gpio_trsw_table(bb, (enum bb_path)val[0], + (bool)val[1], (bool)val[2], + (bool)val[3], (bool)val[4], + (bool)val[5]); + } else if (_os_strcmp(input[2], "rfm") == 0) { + halbb_gpio_rfm(bb, (enum bb_path)val[0], + (enum bb_rfe_src_sel)val[1], (bool)val[2], + (bool)val[3], (bool)val[4], (u8)val[5]); + } else if (_os_strcmp(input[2], "cmn") == 0) { + halbb_gpio_setting(bb, (u8)val[0], (enum bb_path)val[1], + (bool)val[2], + (enum bb_rfe_src_sel)val[3]); + } + } else if (_os_strcmp(input[1], "dbg") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + #ifdef BB_8852A_2_SUPPORT + if (_os_strcmp(input[2], "pop_en") == 0) { + halbb_pop_en(bb, (bool)val[0], + (enum phl_phy_idx)val[1]); + } else if (_os_strcmp(input[2], "set_pd_low") == 0) { + halbb_set_pd_lower_bound(bb, (u8)val[0], + (enum channel_width)val[1], + (enum phl_phy_idx)val[2]); + } else if (_os_strcmp(input[2], "per") == 0) { + halbb_get_per_8852a_2(bb, (enum phl_phy_idx)val[0]); + } + #endif + } else if (_os_strcmp(input[1], "gain_ofst") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + halbb_normal_efuse_verify(bb, (s8)val[0], (enum rf_path)val[1], (enum phl_phy_idx)val[2]); + #ifdef BB_8852B_SUPPORT + } else if (_os_strcmp(input[1], "rf_sw_si_rw") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[5], DCMD_HEX, &val[3]); + + if (val[0] > 2) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[SW_SI] Do not run test!\n"); + return; + } else if (val[1] > 10000) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[SW_SI] Out-of test range!\n"); + return; + } else if (val[2] > 3) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[SW_SI] Wrong path setting!\n"); + return; + } else if (val[3] > 0xff) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[SW_SI] Wrong addr setting!\n"); + return; + } else { + + while (j < val[1]) { + judge_f = halbb_rf_sw_si_test(bb, (enum rf_path)val[2], (u8)val[3], j); + + if (!judge_f){ + BB_WARNING("[%s] while ocunter = %d\n", __func__, j); + break; + } else { + BB_WARNING("[%s] while ocunter = %d\n", __func__, j); + } + + j++; + } + + } + #endif + } + +#if 0 + else if (_os_strcmp(input[1], "sc_idx") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + for (i = 0; i <= 15; i++) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "rpt(0, %d) = 0x%x\n", i, + halbb_get_csi_buf_idx(bb, (u8)val[0], i)); + } + } +#endif + + *_used = used; + *_out_len = out_len; +} + +#ifdef HALBB_DIG_MCC_SUPPORT +u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + u8 i = 0, role_ch = 0, band_idx = MCC_BAND_NUM; + + BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__); + + role_ch = mi->chandef->center_ch; + + for (i = 0; i < MCC_BAND_NUM; i++) { + if (mcc_dm->mcc_rf_ch[i].center_ch == role_ch) { + band_idx = i; + break; + } + } + + if (band_idx == MCC_BAND_NUM) { + BB_WARNING("%s, band_idx = %d", __func__, band_idx); + return HALBB_SET_FAIL; + } + + if (mi->type == PHL_RTYPE_AP) { + mcc_dm->softap_macid = mi->self_macid; + BB_DBG(bb, DBG_DIG, "SoftAP macid = %d\n", + mcc_dm->softap_macid); + } + + return HALBB_SET_SUCCESS; +} + + +void halbb_mcc_stop(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + u8 i = 0, j = 0; + + BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__); + + if (mcc_dm->mcc_status_en == false) + return; + + mcc_dm->mcc_status_en = false; + + for (i = 0; i < MCC_BAND_NUM; i++) { + mcc_dm->sta_cnt[i] = 0; + mcc_dm->mcc_rf_ch[i].chan = INVALID_INIT_VAL; + mcc_dm->mcc_rf_ch[i].center_ch = INVALID_INIT_VAL; + } +} + +u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1, + struct bb_mcc_i *mi_2) +{ + u8 ret = HALBB_SET_FAIL; + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + + BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__); + + halbb_mem_cpy(bb, &mcc_dm->mcc_rf_ch[MCC_BAND_1], mi_1->chandef, + sizeof(struct rtw_chan_def)); + + halbb_mem_cpy(bb, &mcc_dm->mcc_rf_ch[MCC_BAND_2], mi_2->chandef, + sizeof(struct rtw_chan_def)); + + ret = halbb_upd_mcc_macid(bb, mi_1); + if (ret != HALBB_SET_SUCCESS) + goto exit; + + ret = halbb_upd_mcc_macid(bb, mi_2); + if (ret != HALBB_SET_SUCCESS) + goto exit; + + mcc_dm->mcc_status_en = true; + ret = HALBB_SET_SUCCESS; +exit: + return ret; + +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_api.h b/phl/hal_g6/phy/bb/halbb_api.h new file mode 100644 index 0000000..d2c4433 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_api.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_API_H_ +#define _HALBB_API_H_ + +#include "halbb_ic_hw_info.h" + +/*@--------------------------[Define] ---------------------------------------*/ +#define IGI_2_RSSI(igi) (igi - 10) + +#define FUNC_ENABLE 1 +#define FUNC_DISABLE 2 +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_rfe_src_sel { + PAPE_RFM = 0, + GNT_BT_INV = 1, + LNA0N = 2, + LNAON_RFM = 3, + TRSW_RFM = 4, + TRSW_RFM_B = 5, + GNT_BT = 6, + ZERO = 7, + ANTSEL_0 = 8, + ANTSEL_1 = 9, + ANTSEL_2 = 0xa, + ANTSEL_3 = 0xb, + ANTSEL_4 = 0xc, + ANTSEL_5 = 0xd, + ANTSEL_6 = 0xe, + ANTSEL_7 = 0xf +}; + + +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_api_info { + u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/ + u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/ + u8 tx_queue_bitmap; /*REG0x520[23:16]*/ + u8 ccktx_path; + u8 pri_ch_idx; + u8 central_ch; + u8 bw; + enum band_type band; +}; +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx); +u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx); +void halbb_gpio_setting_init(struct bb_info *bb); +void halbb_pre_agc_en(struct bb_info *bb, bool enable); +void halbb_set_gain_error(struct bb_info *bb, u8 central_ch); +u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type); +void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_reset_adc(struct bb_info *bb); +void halbb_ic_hw_setting_non_io(struct bb_info *bb); +void halbb_ic_hw_setting_low_io(struct bb_info *bb); +void halbb_ic_hw_setting(struct bb_info *bb); +void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_api_ex.h b/phl/hal_g6/phy/bb/halbb_api_ex.h new file mode 100644 index 0000000..1cf8c2c --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_api_ex.h @@ -0,0 +1,129 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_API_EX_H_ +#define _HALBB_API_EX_H_ +#include "halbb_ic_hw_info.h" +#include "halbb_api.h" +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +struct bb_mcc_i { + enum role_type type; + struct rtw_chan_def *chandef; + u32 *macid_bitmap; + u8 macid_map_len; + u8 self_macid; +}; +void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en); +u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx); +u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx); +u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path); +void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx); +void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path, + bool inv, enum bb_rfe_src_sel src); +u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width cbw, enum channel_width dbw); + +void halbb_reset_bb(struct bb_info *bb); + +u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask); + +bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask, + u32 data); +bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 bit_mask, u32 data); +u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask); +void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode); + +bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path); + +bool halbb_ctrl_tx_path(struct bb_info *bb, enum rf_path rx_path); + +void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss, + enum rf_path rx_path, u8 rx_nss); + +void halbb_tssi_bb_reset(struct bb_info *bb); + +void halbb_dfs_en(struct bb_info *bb, bool en); + +void halbb_adc_en(struct bb_info *bb, bool en); + +void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path); + +void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx); + +bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx); + +bool halbb_ctrl_ch(struct bb_info *bb, u8 central_ch, enum band_type band, + enum phl_phy_idx phy_idx); + +bool halbb_ctrl_ch2_80p80(struct bb_info *bb, u8 central_ch); + +bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0, + u8 central_ch_seg1, enum band_type band, + enum channel_width bw, enum phl_phy_idx phy_idx); + +void halbb_ctrl_dbcc(struct bb_info *bb, bool dbcc_enable); + +void halbb_cfg_dbcc(struct bb_info *bb, bool dbcc_enable); + +void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx); + +void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable, + enum phl_phy_idx phy_idx); + +void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable, + enum phl_phy_idx phy_idx); + +void halbb_rx_setting(struct bb_info *bb, u8 patch_idx); + +void halbb_ctrl_btg(struct bb_info *bb, bool btg); + +void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en); + +void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx); + +bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx); + +bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound, + enum channel_width bw, enum phl_phy_idx phy_idx); + +bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound, + enum channel_width bw, enum phl_phy_idx phy_idx); + +u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info, + enum phl_phy_idx phy_idx); + +u8 halbb_get_losel(struct bb_info *bb); + +void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx, + enum rf_path path); +void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch, + bool is_ofdm, enum phl_phy_idx phy_idx); +void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, enum phl_phy_idx phy_idx); + +u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi); + +void halbb_mcc_stop(struct bb_info *bb); + +u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1, + struct bb_mcc_i *mi_2); + +void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset, + enum rf_path rx_path, + enum phl_phy_idx phy_idx); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_auto_dbg.c b/phl/hal_g6/phy/bb/halbb_auto_dbg.c new file mode 100644 index 0000000..dc5b87f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_auto_dbg.c @@ -0,0 +1,122 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_AUTO_DBG_SUPPORT + +#define HALBB_CHK_HANG_APIS + +#ifdef HALBB_CHK_HANG_APIS +void halbb_auto_chk_hang_reset(struct bb_info *bb) +{ + struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i; + struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i; + + halbb_mem_set(bb, chk_hang->dbg_port_val, 0, chk_hang->table_size); +} + +void halbb_auto_chk_hang(struct bb_info *bb) +{ + struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i; + struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i; + u32 dbg_port = 0; + u32 dbg_port_value = 0; + u32 i = 0; + + BB_DBG(bb, DBG_AUTO_DBG, "[%s]\n", __func__); + + /*=== Get check hang Information ===============================*/ + /*Get packet counter Report*/ + + /*Get BB Register*/ + + /*Get RF Register*/ + + /*Get Debug Port*/ + for (i = 0; i < chk_hang->table_size; i++) { + dbg_port = chk_hang->dbg_port_table[i]; + if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + halbb_set_bb_dbg_port_ip(bb, (dbg_port & 0xff0000) >> 16); + halbb_set_bb_dbg_port(bb, dbg_port & 0xffff); + dbg_port_value = halbb_get_bb_dbg_port_val(bb); + halbb_release_bb_dbg_port(bb); + + BB_DBG(bb, DBG_AUTO_DBG, "dbg_port[0x%x]=(0x%x)\n", + dbg_port, dbg_port_value); + } else { + BB_DBG(bb, DBG_AUTO_DBG, "Dbg_port Racing Fail!\n"); + return; + } + } + + /*=== Make check hang decision ===============================*/ + BB_DBG(bb, DBG_AUTO_DBG, "Check Hang Decision\n"); + + + halbb_auto_chk_hang_reset(bb); +} + +void halbb_auto_chk_hang_init(struct bb_info *bb) +{ + struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i; + struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i; + u32 dbg_port_table[] = {0x0, 0x803, 0x208, 0xab0}; + u32 table_size = sizeof(dbg_port_table); + + chk_hang->table_size = table_size; + chk_hang->dbg_port_table = halbb_mem_alloc(bb, table_size); + halbb_mem_cpy(bb, chk_hang->dbg_port_table, dbg_port_table, table_size); + + chk_hang->dbg_port_val= halbb_mem_alloc(bb, table_size); + a_dbg->auto_dbg_type |= AUTO_DBG_CHECK_HANG; +} + +#endif + +void halbb_auto_debug(struct bb_info *bb) +{ + struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i; + + if (!(bb->support_ability & BB_AUTO_DBG)) + return; + + /*check hang*/ + if (a_dbg->auto_dbg_type & AUTO_DBG_CHECK_HANG) + halbb_auto_chk_hang(bb); + + /*check RX Part*/ + /*check TX Part*/ +} + +void halbb_auto_debug_init(struct bb_info *bb) +{ + //struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i; + + /*check hang*/ + halbb_auto_chk_hang_init(bb); + /*check RX Part*/ + /*check TX Part*/ +} +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_auto_dbg.h b/phl/hal_g6/phy/bb/halbb_auto_dbg.h new file mode 100644 index 0000000..84b1e71 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_auto_dbg.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_AUTO_DBG_H__ +#define __HALBB_AUTO_DBG_H__ +#ifdef HALBB_AUTO_DBG_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_auto_dbg_t { + AUTO_DBG_CHECK_HANG = BIT(0), + AUTO_DBG_CHECK_TX = BIT(1) +}; + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_chk_hang_info { + u32 table_size; + u32 *dbg_port_table; + u32 *dbg_port_val; +}; + +struct bb_auto_dbg_info { + enum bb_auto_dbg_t auto_dbg_type; + struct bb_chk_hang_info bb_chk_hang_i; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_auto_debug(struct bb_info *bb); +void halbb_auto_debug_init(struct bb_info *bb); +#endif +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_cfg_ic.h b/phl/hal_g6/phy/bb/halbb_cfg_ic.h new file mode 100644 index 0000000..c67496c --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cfg_ic.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CFG_IC_H__ +#define __HALBB_CFG_IC_H__ + +#ifdef CONFIG_RTL8852A + //#define BB_8852A_CAV_SUPPORT /*CAV*/ + #define BB_8852A_2_SUPPORT /*> CBV*/ +#endif + +#ifdef CONFIG_RTL8852B + #define BB_8852B_SUPPORT +#endif + +#ifdef CONFIG_RTL8852C + #define BB_8852C_SUPPORT +#endif + +#ifdef CONFIG_RTL8192XB + #define BB_8192XB_SUPPORT +#endif + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_cfo_trk.c b/phl/hal_g6/phy/bb/halbb_cfo_trk.c new file mode 100644 index 0000000..ab85e4d --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cfo_trk.c @@ -0,0 +1,1089 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_CFO_TRK_SUPPORT + +#ifdef BB_DYN_CFO_TRK_LOP + +void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en) +{ + bb->bb_cfo_trk_i.bb_dyn_cfo_trk_lop_i.dyn_cfo_trk_loop_en = en; +} + +void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i; + struct bb_cfo_trk_lop_cr_info *cr; + + if (state >= DCTL_NUM) + return; + + if (state == dctl->dyn_cfo_trk_loop_state) { + dctl->dctl_hold_cnt++; + BB_DBG(bb, DBG_IC_API, "hold_cnt = %d", dctl->dctl_hold_cnt); + return; + } + + dctl->dyn_cfo_trk_loop_state = state; + + dctl->dctl_hold_cnt = 0; + cr = &dctl->bb_cfo_trk_lop_cr_i[state]; + + halbb_set_reg(bb, 0x4404, 0x7C00, cr->dctl_data); /*8852a CR*/ + halbb_set_reg(bb, 0x440c, 0x7C00, cr->dctl_pilot); + + BB_DBG(bb, DBG_IC_API, "dctl_data = 0x%x, dctl_pilot = 0x%x", cr->dctl_data, cr->dctl_pilot); +} + +void halbb_dyn_cfo_trk_loop(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i; + struct bb_link_info *link = &bb->bb_link_i; + struct rtw_phl_stainfo_t *sta; + u16 snr_tmp = 0; + + if (!dctl->dyn_cfo_trk_loop_en) { + BB_DBG(bb, DBG_IC_API, "dyn_cfo_trk_loop_en = %d", + dctl->dyn_cfo_trk_loop_en); + return; + } + + if (!link->is_linked) + return; + + if (!link->is_one_entry_only) + return; + + sta = bb->phl_sta_info[bb->bb_link_i.one_entry_macid]; + + if (!sta) + return; + + snr_tmp = sta->hal_sta->rssi_stat.snr_ma; + BB_DBG(bb, DBG_IC_API, "macid=%d, SNR = %s", + bb->bb_link_i.one_entry_macid, + halbb_print_sign_frac_digit2(bb, snr_tmp, 16, 4)); + + BB_DBG(bb, DBG_IC_API, "snr_th{L, H} = {%d, %d}", + dctl->dctl_snr_th_l >> RSSI_MA_H, dctl->dctl_snr_th_h >> RSSI_MA_H); + + if (snr_tmp >= dctl->dctl_snr_th_h) + halbb_cfo_trk_loop_cr_cfg(bb, DCTL_LINK); + else if (snr_tmp <= dctl->dctl_snr_th_l) + halbb_cfo_trk_loop_cr_cfg(bb, DCTL_SNR); +} + +void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i; + + dctl->dyn_cfo_trk_loop_en = false; + dctl->dyn_cfo_trk_loop_state = DCTL_SNR; + dctl->dctl_snr_th_l = (u16)5 << RSSI_MA_H; + dctl->dctl_snr_th_h = (u16)7 << RSSI_MA_H; + + dctl->bb_cfo_trk_lop_cr_i[DCTL_SNR].dctl_data = 0x1f; + dctl->bb_cfo_trk_lop_cr_i[DCTL_SNR].dctl_pilot = 0x7; + + dctl->bb_cfo_trk_lop_cr_i[DCTL_LINK].dctl_data = 0x1f; + dctl->bb_cfo_trk_lop_cr_i[DCTL_LINK].dctl_pilot = 0x9; +} + +#endif + +void halbb_digital_cfo_comp(struct bb_info *bb, s32 curr_cfo) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_hal_com_t *hal = bb->hal_com; + //u32 r_ax_pwr_ul_ctrl2; + s32 cfo_avg_312; /*in unit of sub-carrier spacing*/ + s32 digital_cfo_comp_offset; + bool is_positive = IS_GREATER(curr_cfo, 0); + + if (!bb_link->is_linked) { + BB_DBG(bb, DBG_CFO_TRK, "[%s] is_linked=%d\n", __func__, + bb_link->is_linked); + return; + } + + if (curr_cfo == 0) { + BB_DBG(bb, DBG_CFO_TRK, "curr_cfo=0\n"); + return; + } + + BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__); + + // For manually fine tune digital cfo + digital_cfo_comp_offset = halbb_get_reg(bb, 0x4264, 0x00000003); + + /*CR{S(12,11} = (CFO_avg{S(12,2)} << 9) / 312.5*/ + /*CR = X(KHz) << 9 / 312.5(KHz) = X << 10 / 625 ~= X*(1000/625) = (X*8)/5 = (X << 3)/5 */ + if(is_positive) { + cfo_avg_312 = HALBB_DIV(curr_cfo << 3, 5) + digital_cfo_comp_offset; + } else { + cfo_avg_312 = HALBB_DIV(curr_cfo << 3, 5) - digital_cfo_comp_offset; + } + + halbb_print_sign_frac_digit(bb, curr_cfo, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] [Digital Comp] cfo: %s KHz\n", bb->dbg_buf); + + halbb_print_sign_frac_digit(bb, cfo_avg_312, 32, 11, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] cfo_avg_312: %s * 312.5KHz\n", bb->dbg_buf); + + #ifdef BB_8852A_2_SUPPORT + if (bb->ic_type == BB_RTL8852A && hal->cv == CBV) + cfo_avg_312 = cfo_avg_312 * (-1); /* 8852A bug*/ + #endif + + // 0x448C[11:0] CFO compensation value in unit of sub-carrier spacing + halbb_set_reg(bb, cr->r_cfo_comp_seg0_312p5khz, cr->r_cfo_comp_seg0_312p5khz_m, cfo_avg_312); +} + +void halbb_digital_cfo_comp_init(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i; + + // 0x4494[29] Whether the memory of r_cfo_comp_312p5khz is valid + halbb_set_reg(bb, cr->r_cfo_comp_seg0_vld, cr->r_cfo_comp_seg0_vld_m, 1); + + // 0x4490[27:24] r_cfo_weighting + halbb_set_reg(bb, cr->r_cfo_wgting, cr->r_cfo_wgting_m, 8); + + /* 0xD248 */ + /* All scenario set CFO comp.*/ + rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, 0xd248, 0x7, 0); +} + +void halbb_cfo_trk_reset(struct bb_info *bb) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + + BB_DBG(bb, DBG_CFO_TRK, "%s ======>\n", __func__); + + bb_cfo_trk->is_adjust = false; + + if (bb_cfo_trk->crystal_cap > bb_cfo_trk->def_x_cap) { + halbb_set_crystal_cap(bb, bb_cfo_trk->crystal_cap - 1); + } else if (bb_cfo_trk->crystal_cap < bb_cfo_trk->def_x_cap) { + halbb_set_crystal_cap(bb, bb_cfo_trk->crystal_cap + 1); + } + BB_DBG(bb, DBG_CFO_TRK, "(0x%x) approach to dflt_val=(0x%x)\n", + bb_cfo_trk->crystal_cap, bb_cfo_trk->def_x_cap); +} + +void halbb_cfo_acc_io_en(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]===>\n", __func__); + + if (!cfo_trk->cfo_trig_by_timer_en) + return; + + halbb_cfo_dm(bb); + halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_cfo_trk_i.cfo_timer_i); +} + +void halbb_cfo_acc_callback(void *context) +{ + struct bb_info *bb = (struct bb_info *)context; + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct halbb_timer_info *timer = &cfo_trk->cfo_timer_i; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]===>\n", __func__); + + timer->timer_state = BB_TIMER_IDLE; + + if (bb->phl_com->hci_type == RTW_HCI_PCIE) + halbb_cfo_acc_io_en(bb); + else + rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx); +} + +void halbb_cfo_acc_timer_init(struct bb_info *bb) +{ + struct halbb_timer_info *timer = &bb->bb_cfo_trk_i.cfo_timer_i; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__); + + timer->event_idx = BB_EVENT_TIMER_CFO; + timer->timer_state = BB_TIMER_IDLE; + + halbb_init_timer(bb, &timer->timer_list, halbb_cfo_acc_callback, bb, "halbb_cfo_timer"); +} + +void halbb_cfo_deinit(struct bb_info *bb) +{ + BB_DBG(bb, DBG_CFO_TRK, "halbb_cfo_deinit"); +} + +void halbb_cfo_trk_init(struct bb_info *bb) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]=========>\n", __func__); + + /* Init crystal cap from efuse */ + bb_cfo_trk->def_x_cap = bb->phl_com->dev_cap.xcap & 0x7f; + bb_cfo_trk->crystal_cap = bb_cfo_trk->def_x_cap; + bb_cfo_trk->is_adjust = false; + + bb_cfo_trk->x_cap_ofst = 0; + + bb_cfo_trk->cfo_th[0] = CFO_TRK_TH_1 << 2; + bb_cfo_trk->cfo_th[1] = CFO_TRK_TH_2 << 2; + bb_cfo_trk->cfo_th[2] = CFO_TRK_TH_3 << 2; + bb_cfo_trk->cfo_th[3] = CFO_TRK_TH_4 << 2; + + bb_cfo_trk->cfo_th_en = CFO_TRK_ENABLE_TH << 2; + bb_cfo_trk->cfo_th_stop = CFO_TRK_STOP_TH << 2; + + bb_cfo_trk->sw_comp_fine_tune = CFO_SW_COMP_FINE_TUNE << 2; + + bb_cfo_trk->multi_sta_cfo_mode = TP_BASED_AVG_MODE; + bb_cfo_trk->man_cfo_tol = false; + BB_DBG(bb, DBG_CFO_TRK, "Default xcap=0x%x\n", bb_cfo_trk->def_x_cap); + + // For manually fine tune digital cfo + halbb_set_reg(bb, 0x4264, 0x00000003, 1); + bb_cfo_trk->tb_tx_comp_cfo_th = DIGI_CFO_COMP_LIMIT << 2; + halbb_digital_cfo_comp_init(bb); + + bb_cfo_trk->cfo_timer_i.cb_time = 2000; + bb_cfo_trk->cfo_trig_by_timer_en = false; + + bb_cfo_trk->bb_cfo_trk_state = CFO_STATE_0; + bb_cfo_trk->bb_cfo_trk_cnt = 0; + bb_cfo_trk->cfo_src = CFO_SRC_PREAMBLE; + + // For NIC only, to speed up sw CFO compensation + bb_cfo_trk->cfo_dyn_acc_en = (dev->rfe_type < 50) ? true : false; + bb_cfo_trk->cfo_trk_by_data_en = false; +} + +void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct rtw_hal_com_t *hal = bb->hal_com; + u32 sc_xi_val = 0, sc_xo_val = 0; + + if (bb_cfo_trk->crystal_cap == crystal_cap) + return; + + if (crystal_cap > 0x7F) { + BB_DBG(bb, DBG_CFO_TRK, "crystal_cap(0x%x) > 0x7F\n", crystal_cap); + crystal_cap = 0x7F; + } + + rtw_hal_mac_set_xcap(hal, SC_XO, (u32)crystal_cap & 0x7F); + rtw_hal_mac_set_xcap(hal, SC_XI, (u32)crystal_cap & 0x7F); + + rtw_hal_mac_get_xcap(hal, SC_XO, &sc_xo_val); + rtw_hal_mac_get_xcap(hal, SC_XI, &sc_xi_val); + + BB_DBG(bb, DBG_CFO_TRK, "Set sc_xi/xo= {0x%x, 0x%x}\n", sc_xi_val, sc_xo_val); + + bb_cfo_trk->crystal_cap = (u8)sc_xi_val; + + bb_cfo_trk->x_cap_ofst = (s8)DIFF_2(bb_cfo_trk->crystal_cap, bb_cfo_trk->def_x_cap); + if (bb_cfo_trk->crystal_cap < bb_cfo_trk->def_x_cap) + bb_cfo_trk->x_cap_ofst = bb_cfo_trk->x_cap_ofst * (-1); +} + +void halbb_crystal_cap_adjust(struct bb_info *bb, s32 curr_cfo) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct bb_path_info *bb_path = &bb->bb_path_i; + u8 x_cap = bb_cfo_trk->crystal_cap; + u8 step = 0; + s32 cfo_abs = ABS_32(curr_cfo); + bool is_positive = IS_GREATER(curr_cfo, 0); + + BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] %s ======>\n", __func__); + + if (!bb_cfo_trk->is_adjust) { + /* If cfo_avg > th, enable tracking */ + if (cfo_abs > bb_cfo_trk->cfo_th_en) + bb_cfo_trk->is_adjust = true; + } else { + if (cfo_abs < bb_cfo_trk->cfo_th_stop) + bb_cfo_trk->is_adjust = false; + } + + if (!bb_cfo_trk->is_adjust) { + BB_DBG(bb, DBG_CFO_TRK, "Stop Tracking\n"); + /*halbb_digital_cfo_comp(bb);*/ + return; + } + + /*Adjust Crystal Cap. */ + if (cfo_abs > bb_cfo_trk->cfo_th[3]) + step = 7; + else if (cfo_abs > bb_cfo_trk->cfo_th[2]) + step = 5; + else if (cfo_abs > bb_cfo_trk->cfo_th[1]) + step = 3; + else if (cfo_abs > bb_cfo_trk->cfo_th[0]) + step = 1; + else + return; + + if (is_positive) + x_cap += step; + else if (x_cap > step) + x_cap -= step; + + //x_cap = (is_positive) ? (x_cap + step) : (x_cap - step); + + BB_DBG(bb, DBG_CFO_TRK, "TH[en, stop]={%d, %d}, TH[3:0]={%d, %d, %d, %d}\n", + bb_cfo_trk->cfo_th_en >> 2, bb_cfo_trk->cfo_th_en >> 2, + bb_cfo_trk->cfo_th[3] >> 2, bb_cfo_trk->cfo_th[2] >> 2, + bb_cfo_trk->cfo_th[1] >> 2, bb_cfo_trk->cfo_th[0] >> 2); + + BB_DBG(bb, DBG_CFO_TRK, "step=%s%d\n", + (is_positive) ? "+" : "-", step); + + halbb_set_crystal_cap(bb, x_cap); +} + +s32 halbb_avg_cfo_calc(struct bb_info *bb) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_phl_stainfo_t *sta; + struct rtw_cfo_info *cfo_t = NULL; + s32 cfo_all_avg = 0; + u16 macid; + + sta = bb->phl_sta_info[bb_link->one_entry_macid]; + + if (!sta) + return bb_cfo_trk->cfo_avg_pre; + + macid = sta->macid; + cfo_t = &sta->hal_sta->cfo_stat; + + BB_DBG(bb, DBG_CFO_TRK, "one-entry-only macid=%d\n", macid); + + cfo_all_avg = HALBB_DIV(cfo_t->cfo_tail, (s32)cfo_t->cfo_cnt); + + BB_DBG(bb, DBG_CFO_TRK, "Total cfo=(%d), pkt_cnt=(%d), avg_cfo=(%d)\n", + cfo_t->cfo_tail >> 2, cfo_t->cfo_cnt, cfo_all_avg >> 2); + return cfo_all_avg; +} + +s32 halbb_multi_sta_avg_cfo_calc(struct bb_info *bb) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct rtw_hal_com_t *hal = bb->hal_com; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + u8 band = bb->hal_com->band[0].cur_chandef.band; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_phl_stainfo_t *sta; + struct rtw_cfo_info *cfo_t = NULL; + s32 target_cfo = 0; + s32 cfo_khz_all = 0; + s32 cfo_khz_all_tp_wgt = 0; + s32 cfo_avg = 0; + s32 max_cfo_lb= 0x80000000; + s32 min_cfo_ub = 0x7fffffff; + u16 cfo_cnt_all = 0; + u8 active_entry_cnt = 0, sta_cnt = 0; + u32 tp_all = 0; + u16 active_entry = 0; + u8 i; + u8 cfo_tol = 0; + u16 macid; + + BB_DBG(bb, DBG_CFO_TRK, "Multi entry cfo_trk\n"); + + if (!bb_cfo_trk->man_cfo_tol) { + if (band == BAND_ON_24G) + bb_cfo_trk->sta_cfo_tolerance = STA_CFO_TOLERANCE_2G; + else + bb_cfo_trk->sta_cfo_tolerance = STA_CFO_TOLERANCE_5G; + } + + BB_DBG(bb, DBG_CFO_TRK, "Default multi-sta cfo_trk tolerance=%d\n", + bb_cfo_trk->sta_cfo_tolerance); + + /* There are two extra multi-sta strategies remaining as references*/ +#if 0 + if (bb_cfo_trk->multi_sta_cfo_mode == PKT_BASED_AVG_MODE) { + /* Method-1: Centroid pkt based cfo tracking: Compute average cfo from all sta PPDUs */ + /* Just like one entry only method*/ + BB_DBG(bb, DBG_CFO_TRK, "Pkt based average mode\n"); + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + + if (!bb->sta_exist[i]) + continue; + + if (bb_cfo_trk->cfo_cnt[i] == 0) + continue; + + //BB_DBG(bb, DBG_CFO_TRK, "Macid=%d\n", i); + cfo_khz_all += bb_cfo_trk->cfo_tail[i]; + cfo_cnt_all += bb_cfo_trk->cfo_cnt[i]; + cfo_avg = HALBB_DIV(cfo_khz_all, (s32)cfo_cnt_all); + + BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta total cfo=(%d), pkt_cnt=(%d), avg_cfo=(%d)\n", + cfo_khz_all, cfo_cnt_all, cfo_avg); + + target_cfo = cfo_avg; + } + } else if (bb_cfo_trk->multi_sta_cfo_mode == ENTRY_BASED_AVG_MODE) { + /* Method-2: Entry based cfo tracking: Compute average cfo of ertries */ + BB_DBG(bb, DBG_CFO_TRK, "Entry based average mode\n"); + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + + if (!bb->sta_exist[i]) + continue; + + if (bb_cfo_trk->cfo_cnt[i] == 0) + continue; + + active_entry |= BIT(i); + bb_cfo_trk->cfo_avg[i] = HALBB_DIV(bb_cfo_trk->cfo_tail[i], + (s32)bb_cfo_trk->cfo_cnt[i]); + cfo_khz_all += bb_cfo_trk->cfo_avg[i]; + + BB_DBG(bb, DBG_CFO_TRK, "Macid=%d, cfo_avg=%d\n", + i, bb_cfo_trk->cfo_avg[i]); + } + + /* Average of all entries */ + sta_cnt = (u8) halbb_ones_num_in_bitmap(active_entry, sizeof(active_entry) * 8); + cfo_avg = HALBB_DIV(cfo_khz_all, (s32)sta_cnt); + + BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta cfo_acc=(%d), entry_cnt=(%d), avg_cfo=(%d)\n", + cfo_khz_all, sta_cnt, cfo_avg); + + target_cfo = cfo_avg; + + } +#endif + + /* Method-3: Tp based cfo tracking: With Tp_wgt */ + BB_DBG(bb, DBG_CFO_TRK, "Throughput based average mode\n"); + cfo_tol = bb_cfo_trk->sta_cfo_tolerance; + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + + if (!bb->sta_exist[i]) + continue; + + sta = bb->phl_sta_info[i]; + macid = sta->macid; + + if (!is_sta_active(sta)) + continue; + + if ((dev->rfe_type >= 50) && (sta->macid == 0)) + continue; + + cfo_t = &sta->hal_sta->cfo_stat; + + sta_cnt++; + + if (cfo_t->cfo_cnt != 0) { + cfo_t->cfo_avg = + HALBB_DIV(cfo_t->cfo_tail, (s32)cfo_t->cfo_cnt); + active_entry_cnt++; + } else { /* Linked, but no pkts received*/ + cfo_t->cfo_avg = cfo_t->pre_cfo_avg; + } + + /* Calculate the cfo torlence window */ + if ((cfo_t->cfo_avg - cfo_tol) > max_cfo_lb) + max_cfo_lb = cfo_t->cfo_avg - cfo_tol; + if ((cfo_t->cfo_avg + cfo_tol) < min_cfo_ub) + min_cfo_ub = cfo_t->cfo_avg + cfo_tol; + + cfo_khz_all += cfo_t->cfo_avg; + + /* Acc throuhgput of all entries */ + tp_all += cfo_t->tp; + + /* Multiple tp_wgt first*/ + cfo_khz_all_tp_wgt += cfo_t->cfo_avg * cfo_t->tp; + + BB_DBG(bb, DBG_CFO_TRK, "[%d] Macid=%d, cfo_avg=%d, tp=%d\n", + i, macid, cfo_t->cfo_avg, cfo_t->tp); + + cfo_t->pre_cfo_avg = cfo_t->cfo_avg; + + if (sta_cnt >= bb->hal_com->assoc_sta_cnt) + break; + } + + /* Average of all entries with tp_wgt */ + BB_DBG(bb, DBG_CFO_TRK, "Assoc. sta cnt(%d)\n", sta_cnt); + BB_DBG(bb, DBG_CFO_TRK, "Active sta cnt(%d)\n", active_entry_cnt); + + /* Div. tp_all to normalize wgt*/ + cfo_avg = HALBB_DIV(cfo_khz_all_tp_wgt, (s32)tp_all); + + BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta cfo with tp_wgt=(%d), avg_cfo=(%d)\n", + cfo_khz_all_tp_wgt, cfo_avg); + + /* The target cfo need inside the cfo torlence window*/ + BB_DBG(bb, DBG_CFO_TRK, "max_cfo_lb=%d, min_cfo_ub=%d\n", + max_cfo_lb, min_cfo_ub); + + if (max_cfo_lb <= min_cfo_ub) { + BB_DBG(bb, DBG_CFO_TRK, "cfo torlence win. size = %d\n", + min_cfo_ub - max_cfo_lb); + if (cfo_avg < max_cfo_lb) { + BB_DBG(bb, DBG_CFO_TRK, "cfo_avg < win_lb\n"); + target_cfo = max_cfo_lb; + } else if (cfo_avg > min_cfo_ub) { + BB_DBG(bb, DBG_CFO_TRK, "cfo_avg > win_ub\n"); + target_cfo = min_cfo_ub; + } else { + target_cfo = cfo_avg; + } + } else { /* No intersection of multi-sta cfo torlence, avg. of all cfo of entries */ + BB_DBG(bb, DBG_CFO_TRK, "No intersection of cfo torlence windows\n"); + target_cfo = HALBB_DIV(cfo_khz_all, (s32)sta_cnt); + } + + BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Final target cfo=(%d)\n", target_cfo); + + return target_cfo; +} + +void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len) +{ + if (val_len != 1) { + BB_DBG(bb, DBG_CFO_TRK, "[Error][CFO]Need val_len=1\n"); + return; + } + BB_DBG(bb, DBG_CFO_TRK, "[%s] len=%d, val[0]=0x%x\n", __func__, val_len, val_buf[0]); + + halbb_set_crystal_cap(bb, (u8)(val_buf[0] & 0xff)); +} + +void +halbb_cfo_counter_rst(struct bb_info *bb) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct rtw_phl_stainfo_t *sta; + struct rtw_cfo_info *cfo_t = NULL; + u8 i, sta_cnt = 0; + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + + if (!bb->sta_exist[i]) + continue; + + sta = bb->phl_sta_info[i]; + + if (!is_sta_active(sta)) + continue; + + cfo_t = &sta->hal_sta->cfo_stat; + + cfo_t->cfo_tail = 0; + cfo_t->cfo_cnt = 0; + cfo_t->cfo_avg = 0; + cfo_t->tp = 0; + + sta_cnt++; + if (sta_cnt >= bb->hal_com->assoc_sta_cnt) + break; + } + + bb_cfo_trk->cfo_pkt_cnt = 0; +} + +bool +halbb_cfo_trk_abort(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + s32 cfo_avg = 0; + + /* support_ability */ + if (!(bb->support_ability & BB_CFO_TRK)) { + BB_DBG(bb, DBG_CFO_TRK, "[%s] DISABLED\n", __func__); + halbb_cfo_trk_reset(bb); + return true; + } + + if (bb->pause_ability & BB_CFO_TRK) { + cfo_avg = halbb_avg_cfo_calc(bb); + halbb_print_sign_frac_digit(bb, cfo_avg, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE); + + BB_DBG(bb, DBG_CFO_TRK, "Return: Pause CFO_TRK in LV=%d\n", + bb->pause_lv_table.lv_cfo); + + BB_DBG(bb, DBG_CFO_TRK, "Xcap=0x%x, cfo_avg=%s\n", + cfo_trk->crystal_cap, bb->dbg_buf); + + halbb_cfo_counter_rst(bb); + return true; + } + + return false; +} + +void halbb_cfo_trk(struct bb_info *bb, s32 curr_cfo) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + + if (halbb_cfo_trk_abort(bb)) + return; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__); + + if (!bb_link->is_linked) { + BB_DBG(bb, DBG_CFO_TRK, "is_linked=%d\n",bb_link->is_linked); + + halbb_cfo_trk_reset(bb); /*xcap to default value */ + return; + } + + /* To avoid NIC soft-AP going to multi-sta cfo until AP side is verified for a long time*/ + if ((!bb_link->is_one_entry_only) && (dev->rfe_type < 50)) { + BB_DBG(bb, DBG_CFO_TRK, "rfe_type=%d, is_one_entry_only=%d\n", + dev->rfe_type, bb_link->is_one_entry_only); + + halbb_cfo_trk_reset(bb); /*xcap to default value */ + return; + } + + if (bb_link->first_connect) + return; + + if (curr_cfo == 0) { + BB_DBG(bb, DBG_CFO_TRK, "curr_cfo=0\n"); + return; + } + + halbb_crystal_cap_adjust(bb, curr_cfo); /*Decide xcap need to adjust or not */ +} + +bool halbb_cfo_acc_mode_en(struct bb_info *bb) { + + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_link_info *link = &bb->bb_link_i; + + if (!cfo_trk->cfo_dyn_acc_en) + return false; + + // Check TP, switch compensation period + switch (cfo_trk->bb_cfo_trk_state) { + case CFO_STATE_0: + if (link->total_tp >= CFO_TP_UPPER) { + cfo_trk->bb_cfo_trk_state = CFO_STATE_1; + cfo_trk->cfo_trig_by_timer_en = true; + // cfo_trk speed up + cfo_trk->cfo_timer_i.cb_time = CFO_COMP_PERIOD; + halbb_cfo_acc_io_en(bb); + } + break; + + case CFO_STATE_1: + if (cfo_trk->bb_cfo_trk_cnt >= CFO_PERIOD_CNT) { + cfo_trk->bb_cfo_trk_cnt = 0; + cfo_trk->cfo_trig_by_timer_en = false; + } + if (cfo_trk->cfo_trig_by_timer_en) { + cfo_trk->bb_cfo_trk_cnt++; + } + if (link->total_tp <= CFO_TP_LOWER) { + cfo_trk->bb_cfo_trk_state = CFO_STATE_0; + cfo_trk->bb_cfo_trk_cnt = 0; + cfo_trk->cfo_trig_by_timer_en = false; + } + break; + + default: + cfo_trk->bb_cfo_trk_state = CFO_STATE_0; + cfo_trk->bb_cfo_trk_cnt = 0; + break; + } + BB_DBG(bb, DBG_CFO_TRK, "[CFO_COMP] WD, total_tp = %d, cfo_trk_state = %d, timer_en = %d, trk_cnt = %d\n", + link->total_tp, cfo_trk->bb_cfo_trk_state, cfo_trk->cfo_trig_by_timer_en, cfo_trk->bb_cfo_trk_cnt); + + return cfo_trk->cfo_trig_by_timer_en; +} + +void halbb_cfo_dm(struct bb_info *bb) +{ + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + bool x_cap_update = false; + u8 pre_x_cap = cfo_trk->crystal_cap; + s32 new_cfo = 0; + //s8 xtal_th_ofst; + //u8 thermal; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__); + +#if 0 + rtw_hal_rf_xtal_tracking_offset(bb->hal_com, &xtal_th_ofst); + rtw_hal_rf_get_thermal(bb->hal_com, 0, &thermal); + + BB_DBG(bb, DBG_CFO_TRK, "xtal_th_ofst=%d, thermal=%d\n", xtal_th_ofst, thermal); +#endif + + /* No new packet */ + if (bb_link->is_linked && cfo_trk->cfo_pkt_cnt != 0) { + /* NEED MODIFY*/ + if (bb_link->is_one_entry_only) { + new_cfo = halbb_avg_cfo_calc(bb); + } else { + /* To avoid NIC soft-AP going to multi-sta cfo until AP side is verified for a long time*/ + if (dev->rfe_type >= 50) { + /* Multi-sta cfo tracking -> calc. centroid cfo first*/ + new_cfo = halbb_multi_sta_avg_cfo_calc(bb); + } + } + } + + halbb_cfo_trk(bb, new_cfo); + + cfo_trk->cfo_avg_pre = new_cfo; + + halbb_print_sign_frac_digit(bb, cfo_trk->cfo_avg_pre, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CFO_TRK, "cfo_avg=(%s) Khz\n", bb->dbg_buf); + + BB_DBG(bb, DBG_CFO_TRK, "X_cap {Default:0x%x} {Curr: 0x%x -> 0x%x}, x_cap_ofst=%d step\n", + cfo_trk->def_x_cap, pre_x_cap, cfo_trk->crystal_cap, + cfo_trk->x_cap_ofst); + + x_cap_update = (cfo_trk->crystal_cap == pre_x_cap) ? false : true; + + BB_DBG(bb, DBG_CFO_TRK, "Xcap_up=%d\n", x_cap_update); + + if (x_cap_update) { + if (IS_GREATER(new_cfo, 0)) + new_cfo -= cfo_trk->sw_comp_fine_tune; + else + new_cfo += cfo_trk->sw_comp_fine_tune; + } + halbb_digital_cfo_comp(bb, new_cfo); + + halbb_cfo_counter_rst(bb); +} + +void halbb_cfo_watchdog(struct bb_info *bb) +{ + if (halbb_cfo_acc_mode_en(bb)) + return; + + BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__); + halbb_cfo_dm(bb); + BB_DBG(bb, DBG_CFO_TRK, "\n"); +} + +void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + struct bb_rate_info *rate_info = &bb->bb_cmn_rpt_i.bb_rate_i; + struct dev_cap_t *dev = &bb->phl_com->dev_cap; + struct rtw_phl_stainfo_t *sta; + struct rtw_cfo_info *cfo_t = NULL; + s16 cfo; + u8 fw_rate_idx = rate_info->fw_rate_idx; + u8 bb_macid; + + if (!(physts_bitmap & BIT(IE01_CMN_OFDM) && + physts->bb_physts_rslt_hdr_i.ie_map_type >= LEGACY_OFDM_PKT)) + return; + + if (bb_cfo_trk->cfo_trk_by_data_en) { + if (!desc->user_i[0].is_data) + return; + } + + if (bb_cfo_trk->cfo_src == CFO_SRC_FD) + cfo = physts->bb_physts_rslt_1_i.cfo_avg; + else + cfo = physts->bb_physts_rslt_1_i.cfo_pab_avg; + + if (desc->macid_su > PHL_MAX_STA_NUM) + BB_WARNING("[%s] macid_su=%d\n", __func__, desc->macid_su); + + bb_macid = bb->phl2bb_macid_table[desc->macid_su]; + + if (bb_macid > PHL_MAX_STA_NUM) + BB_WARNING("[%s] bb_macid=%d\n", __func__, bb_macid); + + sta = bb->phl_sta_info[bb_macid]; + + if (!is_sta_active(sta)) + return; + + if (sta->macid > PHL_MAX_STA_NUM) + return; + + if (!sta->hal_sta) + return; + + cfo_t = &sta->hal_sta->cfo_stat; + + if ((dev->rfe_type >= 50) && (bb_macid == 0)) /* No need to cnt AP Rx boardcast pkt*/ + return; + + /* CFO info. of all path from phy-status have been averaged */ + cfo_t->cfo_tail += cfo; + cfo_t->cfo_cnt++; + + bb_cfo_trk->cfo_pkt_cnt++; + + /*BB_DBG(bb, DBG_CFO_TRK, "cfo_cnt[%d]=%d, all_cfo_cnt=%d\n", desc->macid_su, cfo_t->cfo_cnt, bb_cfo_trk->cfo_pkt_cnt);*/ + + /* Calcute throughput from rx rate idx*/ + if (rate_info->mode == BB_HE_MODE) { + /* HE[3.2] = VHT[LGI]x1.25*/ + cfo_t->tp += + ((bb_phy_rate_table[fw_rate_idx - MAX_RATE_VHT - MAX_RATE_HT] << 2) + + bb_phy_rate_table[fw_rate_idx - MAX_RATE_VHT - MAX_RATE_HT]) >> 2; + } else if (rate_info->mode == BB_VHT_MODE) { + cfo_t->tp += bb_phy_rate_table[fw_rate_idx - MAX_RATE_HT]; + } else { + cfo_t->tp += bb_phy_rate_table[fw_rate_idx]; + } +} + + +void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + u32 var[10] = {0}; + bool timer_en_pre; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "src {0:fd, 1:preamble}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "data_only {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dyn_acc {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set Xcap: {1} {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "show Xcap: {100}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "th {en, stop, 0~3} {s(8,2)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tb_comp {s(8,2)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "sw_comp {Xcap_enable_th (kHz)} {sw_comp_fine_tune (kHz)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "period {en} {ms}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set_mode {multi-sta cfo_trk mode - 0:Pkts averaged mode, 1: Entry averaged mode, 2: TP based mode}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_tol {manually adjust hypothetical sta_cfo_tolerance in decimal kHz}\n"); + return; + } + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_HEX, &var[1]); + halbb_set_crystal_cap(bb, (u8)var[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set X_cap=0x%x\n", bb_cfo_trk->crystal_cap); + } else if (var[0] == 100) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "X_cap=0x%x\n", bb_cfo_trk->crystal_cap); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Xcap_enable_th = %d (kHz)\n", bb_cfo_trk->cfo_th_en >> 2); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "sw_comp_fine_tune = %d (kHz)\n", bb_cfo_trk->sw_comp_fine_tune >> 2); + + } else if (_os_strcmp(input[1], "data_only") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + + bb_cfo_trk->cfo_trk_by_data_en = (bool)var[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_trk_by_data_en: %d\n", bb_cfo_trk->cfo_trk_by_data_en); + } else if (_os_strcmp(input[1], "dyn_acc") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + + bb_cfo_trk->cfo_dyn_acc_en = (bool)var[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_dyn_acc_en: %d\n", bb_cfo_trk->cfo_dyn_acc_en); + } else if (_os_strcmp(input[1], "src") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + + bb_cfo_trk->cfo_src = (enum bb_cfo_trk_src_t)var[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfo_src: %s\n", + ((bb_cfo_trk->cfo_src == CFO_SRC_FD) ? "FD" : "PAB")); + } else if (_os_strcmp(input[1], "period") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]); + + timer_en_pre = bb_cfo_trk->cfo_trig_by_timer_en; + bb_cfo_trk->cfo_trig_by_timer_en = (bool)var[0]; + + if (var[1] > 2000) + bb_cfo_trk->cfo_timer_i.cb_time = 2000; + else if (var[1] < 5) + bb_cfo_trk->cfo_timer_i.cb_time = 5; + else + bb_cfo_trk->cfo_timer_i.cb_time = (u16)var[1]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "timer=%d ms, trig_by_timer_en=%d\n", + bb_cfo_trk->cfo_timer_i.cb_time, bb_cfo_trk->cfo_trig_by_timer_en); + + if (!timer_en_pre && bb_cfo_trk->cfo_trig_by_timer_en) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Start callback]\n"); + halbb_cfo_acc_io_en(bb); + } + } else if (_os_strcmp(input[1], "th") == 0) { + + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]); + + if (_os_strcmp(input[2], "en") == 0) { + bb_cfo_trk->cfo_th_en = (u8)var[1]; + } else if (_os_strcmp(input[2], "stop") == 0) { + bb_cfo_trk->cfo_th_stop = (u8)var[1]; + } else { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + if (var[0] < CFO_TRK_TH_SIZE) + bb_cfo_trk->cfo_th[var[0]] = (u8)var[1]; + else + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "TH[en, stop]={%d, %d}, TH[3:0]={%d, %d, %d, %d}\n", + bb_cfo_trk->cfo_th_en, bb_cfo_trk->cfo_th_en, + bb_cfo_trk->cfo_th[3], bb_cfo_trk->cfo_th[2], + bb_cfo_trk->cfo_th[1], bb_cfo_trk->cfo_th[0]); + + } else if (_os_strcmp(input[1], "tb_comp") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + + bb_cfo_trk->tb_tx_comp_cfo_th = (u8)var[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tb_tx_comp_cfo_th = %d\n", + bb_cfo_trk->tb_tx_comp_cfo_th); + } else if (_os_strcmp(input[1], "sw_comp") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]); + + bb_cfo_trk->cfo_th_en = (u8)var[0] << 2; + bb_cfo_trk->sw_comp_fine_tune = (u8)var[1] << 2; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "xcap_enable_th = %d,sw_comp_fine_tune = %d\n", + bb_cfo_trk->cfo_th_en >> 2, bb_cfo_trk->sw_comp_fine_tune >> 2); + } else if (_os_strcmp(input[1], "set_mode") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + + bb_cfo_trk->multi_sta_cfo_mode= (u8)var[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "multi_sta_cfo_mode = %d\n", + bb_cfo_trk->multi_sta_cfo_mode); + } else if (_os_strcmp(input[1], "cfo_tol") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + bb_cfo_trk->man_cfo_tol= true; + bb_cfo_trk->sta_cfo_tolerance = (u8)var[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "manually adjust hypothetical sta_cfo_tolerance = %d\n", + bb_cfo_trk->sta_cfo_tolerance); + } +} + +void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb) +{ + struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_A; + cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_A_M; + cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_A; + cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_A_M; + cr->r_cfo_wgting = CFO_WGTING_A; + cr->r_cfo_wgting_m = CFO_WGTING_A_M; + + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_C; + cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_C_M; + cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_C; + cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_C_M; + cr->r_cfo_wgting = CFO_WGTING_C; + cr->r_cfo_wgting_m = CFO_WGTING_C_M; + + break; + #endif + + #ifdef HALBB_COMPILE_AP2_SERIES + case BB_AP2: + cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_A2; + cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_A2_M; + cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_A2; + cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_A2_M; + cr->r_cfo_wgting = CFO_WGTING_A2; + cr->r_cfo_wgting_m = CFO_WGTING_A2_M; + + break; + + #endif + + default: + break; + } + +} + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_cfo_trk.h b/phl/hal_g6/phy/bb/halbb_cfo_trk.h new file mode 100644 index 0000000..f6631a5 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cfo_trk.h @@ -0,0 +1,158 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CFO_TRK_H__ +#define __HALBB_CFO_TRK_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +#define CFO_TRK_TH_SIZE 4 +#define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/ +#define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/ +#define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/ +#define CFO_TRK_TH_1 0 /* @kHz disable CFO_Track threshold*/ +#define CFO_TRK_ENABLE_TH 2 /* @kHz enable CFO_Track threshold*/ +#define CFO_TRK_STOP_TH 2 /* @kHz disable CFO_Track threshold*/ + +#define CFO_SW_COMP_FINE_TUNE 2 /* @kHz expected CFO Comp. per Xcap ofst*/ +#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/ + +#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/ + +#define SC_XO 1 /* xcap setting output value */ +#define SC_XI 0 /* xcap setting input value */ + +#define STA_CFO_TOLERANCE_2G 30 /* kHz */ +#define STA_CFO_TOLERANCE_5G 80 /* kHz */ + +#define CFO_HW_RPT_2_KHZ(val) (((val) << 1) + ((val) >> 1)) +#define CFO_PERIOD_CNT 15 +#define CFO_TP_UPPER 100 /*MHz*/ +#define CFO_TP_LOWER 50 /*MHz*/ +#define CFO_COMP_PERIOD 250 /*ms*/ +/*@--------------------------[Enum]------------------------------------------*/ + +enum bb_cfo_trk_src_t { + CFO_SRC_FD = 0, + CFO_SRC_PREAMBLE = 1 +}; + +enum bb_cfo_trk_st_t { + CFO_STATE_0 = 0, + CFO_STATE_1 = 1 +}; + +enum multi_sta_cfo_mode_t { + PKT_BASED_AVG_MODE = 0, + ENTRY_BASED_AVG_MODE = 1, + TP_BASED_AVG_MODE = 2, +}; + +#ifdef BB_DYN_CFO_TRK_LOP +enum bb_dctl_state_t { + DCTL_SNR = 0, + DCTL_LINK = 1, + DCTL_NUM +}; +#endif + +/*@--------------------------[Structure]-------------------------------------*/ + +#ifdef BB_DYN_CFO_TRK_LOP +struct bb_cfo_trk_lop_cr_info { + u8 dctl_data; /*data tracking loop filter bandwidth selection for 3rd step*/ + u8 dctl_pilot; /*pilot tracking loop filter bandwidth selection for 3rd step*/ +}; + +struct bb_dyn_cfo_trk_lop_info { + bool dyn_cfo_trk_loop_en; + enum bb_dctl_state_t dyn_cfo_trk_loop_state; + u16 dctl_snr_th_l; + u16 dctl_snr_th_h; + u8 dctl_hold_cnt; + struct bb_cfo_trk_lop_cr_info bb_cfo_trk_lop_cr_i[DCTL_NUM]; +}; +#endif + +struct bb_cfo_trk_cr_info { + u32 r_cfo_comp_seg0_312p5khz; + u32 r_cfo_comp_seg0_312p5khz_m; + u32 r_cfo_comp_seg0_vld; + u32 r_cfo_comp_seg0_vld_m; + u32 r_cfo_wgting; + u32 r_cfo_wgting_m; +}; + +struct bb_cfo_trk_info { + struct bb_cfo_trk_cr_info bb_cfo_trk_cr_i; + bool cfo_trig_by_timer_en; + bool is_adjust; /*@already modify crystal cap*/ + u8 cfo_th[CFO_TRK_TH_SIZE]; /*u(8,2)*/ + u8 cfo_th_en; + u8 cfo_th_stop; /*u(8,2)*/ + s8 x_cap_ofst; + u8 crystal_cap; + u8 def_x_cap; + s32 cfo_avg_pre; /*S(12,2), -512~+511.75 kHz*/ + u32 cfo_pkt_cnt; + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + u8 tb_tx_comp_cfo_th; /*u(8,2)*/ + u8 sw_comp_fine_tune; /*u(8,2)*/ + u8 bb_cfo_trk_cnt; + u8 sta_cfo_tolerance; + bool man_cfo_tol; + bool cfo_dyn_acc_en; + bool cfo_trk_by_data_en; + enum bb_cfo_trk_src_t cfo_src; + enum bb_cfo_trk_st_t bb_cfo_trk_state; + enum multi_sta_cfo_mode_t multi_sta_cfo_mode; + #ifdef BB_DYN_CFO_TRK_LOP + struct bb_dyn_cfo_trk_lop_info bb_dyn_cfo_trk_lop_i; + #endif + struct halbb_timer_info cfo_timer_i; +}; + + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +#ifdef BB_DYN_CFO_TRK_LOP +void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en); +void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state); +void halbb_dyn_cfo_trk_loop(struct bb_info *bb); +void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb); +#endif +void halbb_cfo_deinit(struct bb_info *bb); +void halbb_cfo_trk_init(struct bb_info *bb); +void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap); +void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len); +void halbb_cfo_acc_io_en(struct bb_info *bb); +void halbb_cfo_acc_timer_init(struct bb_info *bb); +void halbb_cfo_dm(struct bb_info *bb); +void halbb_cfo_watchdog(struct bb_info *bb); +void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap, + struct physts_rxd *desc); +void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ch_info.c b/phl/hal_g6/phy/bb/halbb_ch_info.c new file mode 100644 index 0000000..7cce397 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ch_info.c @@ -0,0 +1,819 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_CH_INFO_SUPPORT + +bool halbb_ch_info_wait_from_physts(struct bb_info *bb, u32 dly, u32 dly_max, + enum bb_physts_bitmap_t type) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_physts_info *ch_physts = &ch_rpt->bb_ch_info_physts_i; + struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i; + bool get_ch_rpt_success = false; + u32 wait_time = 0; + + BB_DBG(bb, DBG_IC_API, "dly=%d, dly_max=%d ms\n", dly, dly_max); + + if (type == LEGACY_OFDM_PKT) + cfg->ch_i_type = 0; + else + cfg->ch_i_type = 1; + + halbb_cfg_ch_info_cr(bb, cfg); + + ch_physts->ch_info_state = CH_RPT_START_TO_WAIT; + halbb_cfg_ch_info_en(bb, CH_INFO_FROM_PHY_STS, type, bb->bb_phy_idx); + + while (wait_time <= dly_max) { + //Delay for get physts + BB_DBG(bb, DBG_IC_API, "wait=%d ms\n", wait_time); + halbb_delay_ms(bb, dly); + wait_time += dly; + + if (ch_physts->ch_info_state == CH_RPT_GETTED) { + get_ch_rpt_success = true; + break; + } + } + halbb_cfg_ch_info_en(bb, CH_INFO_DISABLE, type, bb->bb_phy_idx); + + return get_ch_rpt_success; +} + +bool halbb_chk_ch_info_cr_valid(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_rpt_size_info *ch_rpt_size = &ch_rpt->bb_ch_rpt_size_i; + u8 ch_matrix_nr[4]; + u8 i = 0, j = 0; + u8 nc = 1, nr = 1; + u8 msb_bit = 0; + u8 mask_tmp = 0; + u16 per_tone_size; + u16 tone_num_table[] = {64, 128, 256, 512}; + u16 tone_num_table_he[] = {64, 128, 256, 512}; + u8 ofst_table[] = {0, 1, 2, 4}; + + /*{Data_bit}*/ + if (cfg->ch_i_cmprs == 0) + ch_rpt_size->data_byte = 1; + else + ch_rpt_size->data_byte = 2; + + BB_DBG(bb, DBG_IC_API, "ch_i_ele_bitmap = 0x%x\n", cfg->ch_i_ele_bitmap); + + /*{Nc}*/ + for (i = 0; i < 4; i++) { + ch_matrix_nr[i] = (cfg->ch_i_ele_bitmap >> (8 * i)) & 0xff; + if (i == 0 && ch_matrix_nr[i] == 0) { + BB_WARNING("ch_matrix_nr[0] = 0\n"); + return false; + } else if (i >= 1) { + if (ch_matrix_nr[i] != 0) { + nc++; + if (ch_matrix_nr[i] != ch_matrix_nr[i - 1]) { + BB_WARNING("matrix_nr[%d]/[%d]=0x%x/0x%x\n", + i - 1, i, ch_matrix_nr[i-1], ch_matrix_nr[i]); + return false; + } + } + } + } + + /*{Nr}*/ + for (i = 0; i < 8; i++) { + if (ch_matrix_nr[0] & BIT(i)) + msb_bit = i; + } + nr = msb_bit + 1; + + mask_tmp = (u8)halbb_gen_mask_from_0(nr); + if (ch_matrix_nr[0] != mask_tmp) { + BB_WARNING("ch_matrix_nr[0]=0x%x, mask_tmp = 0x%x\n", + ch_matrix_nr[0], mask_tmp); + return false; + } + + ch_rpt_size->n_c = nc; + ch_rpt_size->n_r = nr; + + /* + Length = {Data_bit} * {I,Q} * {Nc * Nr} * {N_tone(BW) / group_num} + = {8 or 16} * 2 * {1'number in ele_bitmap} * {N_tone} / {1/2/4/16} + */ + per_tone_size = ch_rpt_size->data_byte * 2 * nc * nr; + ch_rpt_size->per_tone_ch_rpt_size = per_tone_size; + + ch_rpt_size->ch_info_rpt_len_legcy = per_tone_size >> ofst_table[cfg->ch_i_grp_num_non_he]; + + for (i = 0; i < 4; i++) { + //N_tone; + ch_rpt_size->ch_info_rpt_len[i] = per_tone_size >> ofst_table[cfg->ch_i_grp_num_non_he]; + ch_rpt_size->ch_info_rpt_len_he[i] = per_tone_size >> ofst_table[cfg->ch_i_grp_num_he]; + } + + return true; +} + +void halbb_cfg_ch_info_cr(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg) +{ + struct bb_ch_info_cr_info *cr = &bb->bb_ch_rpt_i.bb_ch_info_cr_i; + u32 val_32; + + BB_DBG(bb, DBG_IC_API, + "en_0/1=%d/%d, src=%d, cmprs=%d, grp_num_nhe/he=%d/%d\n", + cfg->ch_i_phy0_en, cfg->ch_i_phy1_en, + cfg->ch_i_data_src, cfg->ch_i_cmprs, + cfg->ch_i_grp_num_non_he, cfg->ch_i_grp_num_he); + BB_DBG(bb, DBG_IC_API, + "blk_start/end_=%d/%d, bitmap=0x%x, type=%d, seg_len=%d,\n", + cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx, + cfg->ch_i_ele_bitmap, cfg->ch_i_type, cfg->ch_i_seg_len); + + if (!halbb_chk_ch_info_cr_valid(bb, cfg)) { + BB_DBG(bb, DBG_IC_API, "[%s] invalid\n", __func__); + //return; + } + + /*CH-info Common Settings*/ + val_32 = (cfg->ch_i_data_src & 0x1) | + ((cfg->ch_i_cmprs & 0x1) << 1) | + ((cfg->ch_i_grp_num_non_he & 0x3) << 2) | + ((cfg->ch_i_grp_num_he & 0x3) << 4); + + halbb_set_reg(bb, cr->ch_info_en_0, 0xfc, val_32); + halbb_set_reg(bb, cr->ele_bitmap, MASKDWORD, cfg->ch_i_ele_bitmap); + halbb_set_reg(bb, cr->ch_info_type, cr->ch_info_type_m, cfg->ch_i_type); +} + +void halbb_cfg_ch_info_en(struct bb_info *bb, enum bb_ch_info_en_t en, + enum bb_physts_bitmap_t bitmap, enum phl_phy_idx phy_idx) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i; + u32 val_32; + + BB_DBG(bb, DBG_IC_API, "[%s] en=%d, bitmap=0x%x\n", __func__, en, bitmap); + + /*CH Report Enable*/ + val_32 = (en == CH_INFO_DISABLE) ? 0 : 1; + + if (phy_idx == HW_PHY_0) + halbb_set_reg(bb, cr->ch_info_en_0, BIT0, val_32); + else + halbb_set_reg(bb, cr->ch_info_en_0, BIT1, val_32); + + /*Phy-sts IE 8 Enable*/ + if(en == CH_INFO_DISABLE || en == CH_INFO_FROM_CH_STS) + halbb_physts_ie_bitmap_en(bb, bitmap, IE08_FTR_CH, false); + else + halbb_physts_ie_bitmap_en(bb, bitmap, IE08_FTR_CH, true); +} + +void halbb_cfg_ch_info_buff(struct bb_info *bb, struct bb_ch_info_buf_cfg_info *cfg) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i; + u32 val_32; + + BB_DBG(bb, DBG_IC_API, "[%s]\n", __func__); + + val_32 = (cfg->ch_i_blk_start_idx & 0xf) | + ((cfg->ch_i_blk_end_idx & 0xf) << 4); + + halbb_set_reg(bb, cr->ch_info_en_0, 0xff00, val_32); + halbb_set_reg(bb, cr->seg_len, cr->seg_len_m, cfg->ch_i_seg_len); +} + +void halbb_chanifo_self_test(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + + BB_DBG(bb, DBG_IC_API, "[%s]ch_rpt = %d\n", __func__, ch_rpt->seg_idx_pre); +} + +enum bb_ch_info_t halbb_ch_info_parsing(struct bb_info *bb, u8 *addr, u32 len, + u8 *rpt_buf, + struct bb_ch_rpt_hdr_info *hdr, + struct bb_phy_info_rpt *phy_info, + struct bb_ch_info_drv_rpt *drv) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + u32 last_seg_size = 0; + u32 len_tmp = 0; + + drv->raw_data_len = len; /*@TEST_CH_SEG_LEN (12 * 8 = 96)*/ + + if (!addr) + return BB_CH_INFO_FAIL; + + if (len == 0) + return BB_CH_INFO_FAIL; + + halbb_mem_cpy(bb, hdr, addr, ch_rpt->ch_rpt_hdr_len); + + if (hdr->set_valid == 0) + return BB_CH_INFO_FAIL; + + drv->raw_data_len -= ch_rpt->ch_rpt_hdr_len; + + addr += ch_rpt->ch_rpt_hdr_len; + + BB_DBG(bb, DBG_IC_API, "[IN] skip=%d\n", ch_rpt->skip_ch_info); + + BB_DBG(bb, DBG_IC_API, "[Hdr]lenth_curr: %d = %d - %d\n", + drv->raw_data_len, len, ch_rpt->ch_rpt_hdr_len); /*@88 = 96 - 8*/ + + if (hdr->is_pkt_end) { + /*SEG = N-1 (LAST SEG)*/ + drv->seg_idx_curr = hdr->total_seg_num - 1; /*@3*/ + ch_rpt->seg_idx_pre = drv->seg_idx_curr;/*@3*/ + ch_rpt->seg_total_num = hdr->total_seg_num; /*4*/ + ch_rpt->total_len = (hdr->total_len_m << 16 | hdr->total_len_l) + - ch_rpt->ch_rpt_hdr_len - ch_rpt->phy_info_len; /*@320 - 16 = 304*/ + + BB_DBG(bb, DBG_IC_API, + "[SEG_%d Last] seg_total_num=%d, total_len_l=%d, total_len=%d, remnant=%d, skip=%d\n", + drv->seg_idx_curr, ch_rpt->seg_total_num, hdr->total_len_l, + ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info); + + if (ch_rpt->skip_ch_info) { + + ch_rpt->skip_ch_info = false; + ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/ + return BB_CH_INFO_FAIL; + } else if (drv->seg_idx_curr != hdr->seq_num) { + BB_DBG(bb, DBG_IC_API, "[LAST][FAIL]drv_idx=%d != hdr_idx=%d\n", + drv->seg_idx_curr, hdr->seq_num); + + ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/ + ch_rpt->skip_ch_info = false; + return BB_CH_INFO_FAIL; + } else if (drv->raw_data_len < ch_rpt->total_len_remnant) { + BB_DBG(bb, DBG_IC_API, "[LAST][FAIL]raw_data_len=%d < total_len_remnant=%d\n", + drv->raw_data_len, ch_rpt->total_len_remnant); + + ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/ + ch_rpt->skip_ch_info = false; + return BB_CH_INFO_FAIL; + } else { + + BB_DBG(bb, DBG_IC_API, "[LAST] len_remnant=%d\n", ch_rpt->total_len_remnant); + + drv->raw_data_len = ch_rpt->total_len_remnant; /*Last remnant raw data*/ + ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/ + halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len); + return BB_CH_INFO_LAST_SEG; + } + } + + if (ch_rpt->skip_ch_info) { + BB_DBG(bb, DBG_IC_API, "[OUT]skip=%d\n", ch_rpt->skip_ch_info); + return BB_CH_INFO_FAIL; + } + + BB_DBG(bb, DBG_IC_API, "seg_idx_pre=%d\n", ch_rpt->seg_idx_pre); + + if (ch_rpt->seg_idx_pre == (hdr->total_seg_num - 1)) { /*@3 = 4 - 1*/ + /*SEG = 0*/ + drv->seg_idx_curr = 0; + ch_rpt->seg_idx_pre = 0; + + //phy_info = (struct bb_phy_info_rpt *)addr; + halbb_mem_cpy(bb, phy_info, addr, ch_rpt->phy_info_len); + addr += ch_rpt->phy_info_len; + + len_tmp = drv->raw_data_len; + drv->raw_data_len -= ch_rpt->phy_info_len; /*@80 = 88 - 8*/ + + BB_DBG(bb, DBG_IC_API, "[PHY_info]lenth_curr: %d = %d - %d\n", + drv->raw_data_len, len_tmp, ch_rpt->phy_info_len); + + BB_DBG(bb, DBG_IC_API, "[PHY_info]RSSI= {%d, %d, %d}\n", + phy_info->rssi[0], phy_info->rssi[1], phy_info->rssi_avg); + + BB_DBG(bb, DBG_IC_API, + "[SEG_0 Fist] total{num, len}={%d, %d}, remnant=%d, skip=%d\n", + ch_rpt->seg_total_num, ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info); + + if (drv->raw_data_len > ch_rpt->total_len_remnant) { + BB_DBG(bb, DBG_IC_API, "[FAIL]raw_data_len > total_len_remnant\n"); + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } else if (phy_info->rsvd_0 != 0 || phy_info->rsvd_1 != 0 || + phy_info->rsvd_2 != 0) { + BB_DBG(bb, DBG_IC_API, "[FAIL]rsvd_0,1,2: %d, %d, %d\n", + phy_info->rsvd_0, phy_info->rsvd_1, phy_info->rsvd_2); + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } else if (drv->seg_idx_curr != hdr->seq_num) { + BB_DBG(bb, DBG_IC_API, "[FAIL]drv_idx=%d != hdr_idx=%d\n", + drv->seg_idx_curr, hdr->seq_num); + + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } else { + ch_rpt->total_len_remnant -= drv->raw_data_len; + + halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len); + return BB_CH_INFO_SUCCESS; + } + } else { + /*SEG = 1~N-2*/ + drv->seg_idx_curr = ch_rpt->seg_idx_pre + 1; + ch_rpt->seg_idx_pre = drv->seg_idx_curr; + + if (drv->seg_idx_curr >= (hdr->total_seg_num - 1)) { /*@ >= 3*/ + BB_DBG(bb, DBG_IC_API, "[FAIL]Los Last Seg\n"); + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } + + BB_DBG(bb, DBG_IC_API, + "[SEG_%d Mid] total{num, len}={%d, %d}, remnant=%d, skip=%d\n", + drv->seg_idx_curr, ch_rpt->seg_total_num, ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info); + + BB_DBG(bb, DBG_IC_API, "lenth_curr: %d\n", drv->raw_data_len); /*@88 = 96 - 8*/ + + if (drv->raw_data_len > ch_rpt->total_len_remnant) { + BB_DBG(bb, DBG_IC_API, "[FAIL]raw_data_len > total_len_remnant\n"); + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } else if (drv->seg_idx_curr != hdr->seq_num) { + BB_DBG(bb, DBG_IC_API, "[FAIL]drv_idx=%d != hdr_idx=%d\n", + drv->seg_idx_curr, hdr->seq_num); + ch_rpt->skip_ch_info = true; + return BB_CH_INFO_FAIL; + } else { + ch_rpt->total_len_remnant -= drv->raw_data_len; + halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len); + return BB_CH_INFO_SUCCESS; + } + } +} + +void halbb_ch_info_bbcr_init(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i; + + BB_DBG(bb, DBG_IC_API, "[%s]\n", __func__); + + cfg->ch_i_data_src = 0; + cfg->ch_i_cmprs = 1; + cfg->ch_i_grp_num_non_he = 3; + cfg->ch_i_grp_num_he = 3; + cfg->ch_i_blk_start_idx = 9; + cfg->ch_i_blk_end_idx = 10; + cfg->ch_i_ele_bitmap = 0x303; /*Nr X Nc: 2 X 2*/ + cfg->ch_i_type = 1; + cfg->ch_i_seg_len = 0; + halbb_cfg_ch_info_cr(bb, cfg); +} + +void halbb_ch_info_init(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i; + struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i; + + halbb_ch_info_bbcr_init(bb); + ch_rpt->ch_rpt_hdr_len = sizeof(struct bb_ch_rpt_hdr_info); /*8852A: 8Byte*/ + ch_rpt->phy_info_len = sizeof(struct bb_phy_info_rpt); /*8852A: 8Byte*/ + ch_rpt->skip_ch_info = true; + + //Init Parameter + buf->ch_info_buf_len = 1024; + physts->bitmap_type_auto_en = true; + + BB_DBG(bb, DBG_IC_API, "[%s] hdr_len = %d, phy_info_len=%d\n", __func__, ch_rpt->ch_rpt_hdr_len, ch_rpt->phy_info_len); +} + +void halbb_ch_info_print_buf(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + u16 i = 0; + u8 *buf_tmp; + + if (!ch_rpt->test_buf) + return; + + buf_tmp = ch_rpt->test_buf; + BB_DBG(bb, DBG_IC_API, "----------------------------\n"); + for (i = 0; i < ((TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN) >> 3); i++) { + BB_DBG(bb, DBG_IC_API, "[%02d] 0x%016llx\n", i, *(u64 *)buf_tmp); + buf_tmp += 8; + + if (i == 9 || i == 20 || i == 31 || i == 37 || i == 42) + BB_DBG(bb, DBG_IC_API, "----------------------------\n"); + } + BB_DBG(bb, DBG_IC_API, "----------------------------\n"); +} + +void halbb_ch_info_buf_rls(struct bb_info *bb) +{ + struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i; + + if (!buf->octet) + return; + + BB_DBG(bb, DBG_IC_API,"[%s]\n", __func__); + + halbb_mem_free(bb, buf->octet, buf->ch_info_buf_len); + buf->octet = 0; +} + +bool halbb_ch_info_buf_alloc(struct bb_info *bb) +{ + struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i; + + if (buf->octet) + return true; + + BB_DBG(bb, DBG_IC_API,"[%s]\n", __func__); + + buf->octet = (s16 *)halbb_mem_alloc(bb, buf->ch_info_buf_len); + + if (!buf->octet) + return false; + + return true; +} + +void halbb_ch_info_reset(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + + if (ch_rpt->test_buf) + halbb_mem_set(bb, ch_rpt->test_buf, 0, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN)); +} + +void halbb_ch_info_deinit(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + + halbb_ch_info_buf_rls(bb); + if (ch_rpt->test_buf) + halbb_mem_free(bb, ch_rpt->test_buf, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN)); +} +void halbb_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_raw_info *buf = &ch_rpt->bb_ch_info_raw_i; + struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i; + struct bb_ch_rpt_size_info *ch_rpt_size = &ch_rpt->bb_ch_rpt_size_i; + struct bb_ch_info_physts_info *ch_physts = &ch_rpt->bb_ch_info_physts_i; + struct bb_pkt_cnt_su_store_info *store = &bb->bb_cmn_rpt_i.bb_pkt_cnt_su_store_i; + struct bb_ch_rpt_hdr_info ch_rpt_hdr = {0}; + struct bb_phy_info_rpt phy_rpt_in; + struct bb_ch_rpt_hdr_info hdr; /*output*/ + struct bb_phy_info_rpt phy_rpt; /*output*/ + struct bb_ch_info_drv_rpt drv_rpt; /*output*/ + enum bb_ch_info_t rpt; /*output*/ + enum bb_physts_bitmap_t bitmap_type; + u8 grp_num_tab[4] = {1, 2, 4, 16}; + bool val_bool; + u8 seg_idx; + u8 *addr, *addr_tmp, *addr_ori; + u32 len = TEST_CH_SEG_LEN; /*Byte*/ + u32 val[11] = {0}; + u16 i = 0; + u16 tone_num = 0; + + halbb_mem_set(bb, &phy_rpt_in, 0, sizeof(phy_rpt_in)); + halbb_mem_set(bb, &hdr, 0, sizeof(hdr)); + halbb_mem_set(bb, &phy_rpt, 0, sizeof(phy_rpt)); + halbb_mem_set(bb, &drv_rpt, 0, sizeof(drv_rpt)); + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{self_test}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{print}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{rst}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{test} {seg_idx:0~3}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "trig_psts\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg show\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg para0 {0: auto, 6~7: HE/VHT_MU, 12~15: Lgcy/HT/VHT/HE}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg para1 {0/1: 1/2 Byte} {grp: 0~3:1/2/4/16} {H_map(Hex)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg para2 {seg_len}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg para3 {0:LS, 1:CS}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cfg blk {start_idx} {end_idx}\n"); + return; + } + + if (_os_strcmp(input[1], "self_test") == 0) { + halbb_chanifo_self_test(bb); + } else if (_os_strcmp(input[1], "print") == 0) { + halbb_ch_info_print_buf(bb); + } else if (_os_strcmp(input[1], "rst") == 0) { + halbb_ch_info_reset(bb); + } else if (_os_strcmp(input[1], "trig_physts") == 0) { + + if(!halbb_ch_info_buf_alloc(bb)) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Buff alloc fail\n"); + return; + } + + if (ch_physts->bitmap_type_auto_en) { + if (store->he_pkt_not_zero) + bitmap_type = HE_PKT; + else if (store->vht_pkt_not_zero) + bitmap_type = VHT_PKT; + else if (store->ht_pkt_not_zero) + bitmap_type = HT_PKT; + else + bitmap_type = LEGACY_OFDM_PKT; + } else { + bitmap_type = ch_physts->force_bitmap_type; + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Auto Type=%d\n", ch_physts->bitmap_type_auto_en); + + val_bool = halbb_ch_info_wait_from_physts(bb, 100, 500, bitmap_type); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Trigger Type[%s], BW=%d, success=%d\n", + bb_physts_bitmap_type_t[bitmap_type], + 20 << bb->hal_com->band[0].cur_chandef.bw, val_bool); + + if (!val_bool) + return; + + tone_num = HALBB_DIV(ch_physts->ch_info_len, ch_rpt_size->per_tone_ch_rpt_size); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[CH-Info Rpt][%s] len:%d, per_tone_size=%d, tone_num=%d\n", + bb_physts_bitmap_type_t[ch_physts->bitmap_type_rpt], + ch_physts->ch_info_len, ch_rpt_size->per_tone_ch_rpt_size, + tone_num); +#if 0 + if (buf->octet && + buf->ch_info_buf_len > ch_physts->ch_info_len && + ch_physts->ch_info_len != 0) { + halbb_print_buff_64(bb, (u8*)buf->octet, ch_physts->ch_info_len); + } +#endif + } else if (_os_strcmp(input[1], "cfg") == 0) { + + for (i = 0; i <= 4; i++) + HALBB_SCAN(input[3 + i], DCMD_DECIMAL, &val[i]); + + if (_os_strcmp(input[2], "show") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "src=%d, cmprs=%d, grp_num_nhe/he=%d/%d\n", + cfg->ch_i_data_src, cfg->ch_i_cmprs, + cfg->ch_i_grp_num_non_he, cfg->ch_i_grp_num_he); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "blk_start/end_=%d/%d, bitmap=0x%x, type=%d, seg_len=%d\n", + cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx, + cfg->ch_i_ele_bitmap, cfg->ch_i_type, cfg->ch_i_seg_len); + return; + } else if (_os_strcmp(input[2], "para0") == 0) { + if (val[0] == 0) { + ch_physts->bitmap_type_auto_en = true; + return; + } + ch_physts->bitmap_type_auto_en = false; + ch_physts->force_bitmap_type = (enum bb_physts_bitmap_t)val[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "force_bitmap_type=%s\n", + bb_physts_bitmap_type_t[ch_physts->force_bitmap_type]); + } else if (_os_strcmp(input[2], "para1") == 0) { + HALBB_SCAN(input[5], DCMD_HEX, &val[2]); + + cfg->ch_i_cmprs = (bool)val[0]; + if (val[1] < 4) { + cfg->ch_i_grp_num_non_he = (u8)val[1]; + cfg->ch_i_grp_num_he = (u8)val[1]; + } + cfg->ch_i_ele_bitmap = val[2]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "data_wl=%d Byte, grp_num=%d, H_map=0x%x\n", + 1 << cfg->ch_i_cmprs, grp_num_tab[val[1]], + cfg->ch_i_ele_bitmap); + } else if (_os_strcmp(input[2], "para2") == 0) { + cfg->ch_i_seg_len = (u8)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "seg_len=%d\n", + cfg->ch_i_seg_len); + } else if (_os_strcmp(input[2], "para3") == 0) { + cfg->ch_i_data_src = (bool)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "src=%d\n", cfg->ch_i_data_src); + } else if (_os_strcmp(input[2], "blk") == 0) { + cfg->ch_i_blk_start_idx = (u8)val[0]; + cfg->ch_i_blk_end_idx = (u8)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "blk_start/end_=%d/%d\n", + cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + halbb_cfg_ch_info_cr(bb, cfg); + + } else if (_os_strcmp(input[1], "test") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + seg_idx = (u8)val[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[SEG:%d] Input\n", seg_idx); + + /*Rpt Buff*/ + if (!ch_rpt->test_buf) + ch_rpt->test_buf = (u8 *)halbb_mem_alloc(bb, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN)); + + /*Data Buff*/ + addr = (u8 *)halbb_mem_alloc(bb, len); + addr_ori = addr; + + if (!addr) + return; + + /*HDR Info*/ + /*seg_0:[2(hdr) + 10(data)] + seg_1:11(data) + seg_2:11(data) + seg_3:6(data) = 40, 40*8=320*/ + ch_rpt_hdr.total_len_l = 320; + ch_rpt_hdr.total_seg_num = TEST_CH_INFO_MAX_SEG; + ch_rpt_hdr.set_valid = 1; + ch_rpt_hdr.segment_size = TEST_CH_SEG_LEN >> 3; + ch_rpt_hdr.seq_num= seg_idx; + + if (seg_idx == TEST_CH_INFO_MAX_SEG - 1) { + ch_rpt_hdr.is_pkt_end = 1; + } else { + ch_rpt_hdr.is_pkt_end = 0; + } + + halbb_mem_cpy(bb, addr, &ch_rpt_hdr, ch_rpt->ch_rpt_hdr_len); + addr += ch_rpt->ch_rpt_hdr_len; + + if (seg_idx == 0) { + phy_rpt_in.rssi[0] = 50; + phy_rpt_in.rssi[1] = 70; + phy_rpt_in.rssi_avg = 60; + phy_rpt_in.rsvd_0 = 0; + phy_rpt_in.rsvd_1 = 0; + phy_rpt_in.rsvd_2 = 0; + + halbb_mem_cpy(bb, addr, &phy_rpt_in, ch_rpt->phy_info_len); + addr += ch_rpt->phy_info_len; + ch_rpt->test_buf_curr = ch_rpt->test_buf; + } + + if (seg_idx == TEST_CH_INFO_MAX_SEG - 1) { + /*SEG3 (LAST)*/ + for (i = 0; i < (TEST_CH_SEG_LEN - 8 - 40); i++) { + *addr = (u8)i; + addr++; + } + } else if (seg_idx == 0) { + /*SEG 0*/ + for (i = 0; i < (TEST_CH_SEG_LEN - 16); i++) { + *addr = (u8)i; + addr++; + } + } else { + /*SEG 1,2*/ + for (i = 0; i < (TEST_CH_SEG_LEN - 8); i++) { + *addr = (u8)i; + addr++; + } + } + + addr_tmp = addr_ori; + for (i = 0; i < (TEST_CH_SEG_LEN >> 3); i++) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%02d] 0x%016llx\n", i, *(u64 *)addr_tmp); + addr_tmp += 8; + } + + rpt = halbb_ch_info_parsing(bb, addr_ori, len, ch_rpt->test_buf_curr, &hdr, &phy_rpt, &drv_rpt); + + ch_rpt->raw_data_len_acc += drv_rpt.raw_data_len; + ch_rpt->test_buf_curr += drv_rpt.raw_data_len; + + if (rpt == BB_CH_INFO_SUCCESS) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Result] Success\n"); + } else { + if (rpt == BB_CH_INFO_LAST_SEG) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Result] Success, Last Seg\n"); + halbb_ch_info_print_buf(bb); + + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Result] Fail\n"); + } + halbb_ch_info_reset(bb); + ch_rpt->raw_data_len_acc = 0; + ch_rpt->test_buf_curr = ch_rpt->test_buf; + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[ACC] remnant=%d, raw_data_len_acc=%d\n", + ch_rpt->total_len_remnant, ch_rpt->raw_data_len_acc); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[SEG] all_len=%d = Hdr_len + raw_data_len=%d\n", + len, drv_rpt.raw_data_len); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[SEG] total_len=%d, seg_size=%d, end=%d, sts0_evm=%d, seq_num=%d\n", + hdr.total_len_l, hdr.segment_size, hdr.is_pkt_end, hdr.sts0_evm, hdr.seq_num); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[IN] SEG[%d]: rssi{0,1,avg}={%02d,%02d,%02d}, sts1_evm=%d, rsvd{0,1,2}={%d,%d,%d}\n", + ch_rpt_hdr.seq_num, + phy_rpt_in.rssi[0], phy_rpt_in.rssi[1], + phy_rpt_in.rssi_avg, (phy_rpt_in.sts1_evm_m << 4 | phy_rpt_in.sts1_evm_l) , + phy_rpt_in.rsvd_0, phy_rpt_in.rsvd_1, + phy_rpt_in.rsvd_2); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[OUT] SEG[%d]: rssi{0,1,avg}={%02d,%02d,%02d}, sts1_evm=%d, rsvd{0,1,2}={%d,%d,%d}\n\n", + drv_rpt.seg_idx_curr, + phy_rpt.rssi[0], phy_rpt.rssi[1], + phy_rpt.rssi_avg, (phy_rpt.sts1_evm_m << 4 | phy_rpt.sts1_evm_l), + phy_rpt.rsvd_0, phy_rpt.rsvd_1, + phy_rpt.rsvd_2); + + halbb_mem_free(bb, addr_ori, len); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} + +void halbb_cr_cfg_ch_info_init(struct bb_info *bb) +{ + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->ch_info_en_0 = INTF_R_CH_INFO_EN_P0_A; + cr->ele_bitmap = INTF_R_ELE_BITMAP_A; + cr->ch_info_type = CH_INFO_TYPE_A; + cr->ch_info_type_m = CH_INFO_TYPE_A_M; + cr->seg_len = CH_INFO_SEG_LEN_A; + cr->seg_len_m = CH_INFO_SEG_LEN_A_M; + break; + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->ch_info_en_0 = INTF_R_CH_INFO_EN_P0_C; + cr->ele_bitmap = INTF_R_ELE_BITMAP_C; + cr->ch_info_type = CH_INFO_TYPE_C; + cr->ch_info_type_m = CH_INFO_TYPE_C_M; + cr->seg_len = CH_INFO_SEG_LEN_C; + cr->seg_len_m = CH_INFO_SEG_LEN_C_M; + break; + #endif + + default: + break; + } + +} + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ch_info.h b/phl/hal_g6/phy/bb/halbb_ch_info.h new file mode 100644 index 0000000..74a066f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ch_info.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CH_INFO_H__ +#define __HALBB_CH_INFO_H__ + +#ifdef HALBB_CH_INFO_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ +#define TEST_CH_INFO_MAX_SEG 4 +#define TEST_CH_SEG_LEN (12 * 8) /*Byte*/ +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +enum bb_ch_info_state_type { + CH_RPT_START_TO_WAIT = 0, + CH_RPT_GETTED = 1 +}; + +struct bb_ch_info_physts_info { + enum bb_ch_info_state_type ch_info_state; + enum bb_physts_bitmap_t force_bitmap_type; /*force setting*/ + enum bb_physts_bitmap_t bitmap_type_rpt; /*report*/ + bool bitmap_type_auto_en; + u16 ch_info_len; +}; + +struct bb_ch_info_raw_info { + s16 *octet; + u32 ch_info_buf_len; /*Byte*/ +}; + +struct bb_ch_info_cr_info { + u32 ch_info_en_0; + u32 ele_bitmap; + u32 ch_info_type; + u32 ch_info_type_m; + u32 seg_len; + u32 seg_len_m; +}; + +struct bb_ch_rpt_size_info { + u8 data_byte; + u8 n_c; + u8 n_r; + u16 n_tone; + u8 n_group; + u16 ch_info_rpt_len_legcy; /*Lgacy; Byte; ch_info rpt length calculated by BB CR configuration*/ + u16 ch_info_rpt_len[4]; /*HT/VHT 20,40,80; Byte; ch_info rpt length calculated by BB CR configuration*/ + u16 ch_info_rpt_len_he[4]; /*HE 20,40,80; Byte; ch_info rpt length calculated by BB CR configuration*/ + u16 per_tone_ch_rpt_size; +}; + +struct bb_ch_rpt_info { + u8 seg_idx_pre; + u8 seg_total_num; + u32 total_len; /*Raw data length(Unit: byte) = total_len - 16*/ + u32 total_len_remnant; + u16 ch_rpt_hdr_len; + u16 phy_info_len; + bool skip_ch_info; + u32 raw_data_len_acc; + u8 *test_buf; + u8 *test_buf_curr; + struct bb_ch_info_cr_cfg_info bb_ch_info_cr_cfg_i; + struct bb_ch_info_cr_info bb_ch_info_cr_i; /*CR callback table*/ + struct bb_ch_rpt_size_info bb_ch_rpt_size_i; + struct bb_ch_info_raw_info bb_ch_info_raw_i; + struct bb_ch_info_physts_info bb_ch_info_physts_i; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +bool halbb_ch_info_wait_from_physts(struct bb_info *bb, u32 dly, u32 dly_max, + enum bb_physts_bitmap_t type); +void halbb_ch_info_buf_rls(struct bb_info *bb); +bool halbb_ch_info_buf_alloc(struct bb_info *bb); +void halbb_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_ch_info_deinit(struct bb_info *bb); +void halbb_ch_info_init(struct bb_info *bb); +void halbb_cr_cfg_ch_info_init(struct bb_info *bb); +#endif +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_ch_info_ex.h b/phl/hal_g6/phy/bb/halbb_ch_info_ex.h new file mode 100644 index 0000000..038c5c5 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ch_info_ex.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CH_INFO_EX_H__ +#define __HALBB_CH_INFO_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_ch_info_en_t { + CH_INFO_DISABLE = 0, + CH_INFO_FROM_PHY_STS = 1, + CH_INFO_FROM_CH_STS = 2 +}; + +enum bb_ch_info_t { + BB_CH_INFO_SUCCESS = 0, + BB_CH_INFO_LAST_SEG, + BB_CH_INFO_FAIL, +}; +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_ch_info_cr_cfg_info { + bool ch_i_phy0_en; + bool ch_i_phy1_en; + bool ch_i_data_src; /*0~1: CH-estimation, CH-smoothing*/ + bool ch_i_cmprs; /*0~1: 8/16 bit*/ + u8 ch_i_grp_num_non_he; /*0~3: 1/2/4/16*/ + u8 ch_i_grp_num_he; /*0~3: 1/2/4/16*/ + u8 ch_i_blk_start_idx; /*1~10*/ + u8 ch_i_blk_end_idx; /*1~10*/ + u32 ch_i_ele_bitmap; + bool ch_i_type; /*0~1: L-CH, MIMO-CH*/ + u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/ +}; + +struct bb_ch_info_buf_cfg_info { + u8 ch_i_blk_start_idx; /*1~10*/ + u8 ch_i_blk_end_idx; /*1~10*/ + u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/ +}; + +struct bb_ch_rpt_hdr_info { + u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/ + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 total_len_m:1; + u8 total_seg_num:7; + #else + u8 total_seg_num:7; + u8 total_len_m:1; + #endif + + u8 avg_noise_pow; + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 is_pkt_end:1; + u8 set_valid:1; + u8 n_rx:3; + u8 n_sts:3; + #else + u8 n_sts:3; + u8 n_rx:3; + u8 set_valid:1; + u8 is_pkt_end:1; + #endif + u8 segment_size; /*unit (8Byte)*/ + u8 sts0_evm; + u8 seq_num; +}; + +struct bb_phy_info_rpt { + u8 rssi[2]; + u16 rsvd_0; + u8 rssi_avg; + #if (PLATFOM_IS_LITTLE_ENDIAN) + u8 rxsc:4; + u8 sts1_evm_l:4; + u8 sts1_evm_m:4; + u8 rsvd_1:4; + #else + u8 rsvd_1:4; + u8 sts1_evm_m:4; + u8 sts1_evm_l:4; + u8 rxsc:4; + #endif + u8 rsvd_2; +}; + +struct bb_ch_info_drv_rpt { + u32 raw_data_len; + u8 seg_idx_curr; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_cfg_ch_info_cr(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg); +void halbb_cfg_ch_info_en(struct bb_info *bb, enum bb_ch_info_en_t en, + enum bb_physts_bitmap_t bitmap, enum phl_phy_idx phy_idx); +void halbb_cfg_ch_info_buff(struct bb_info *bb, struct bb_ch_info_buf_cfg_info *cfg); +enum bb_ch_info_t halbb_ch_info_parsing(struct bb_info *bb, u8 *addr, u32 len, + u8 *rpt_buf, + struct bb_ch_rpt_hdr_info *hdr, + struct bb_phy_info_rpt *phy_info, + struct bb_ch_info_drv_rpt *drv); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_cmn_rpt.c b/phl/hal_g6/phy/bb/halbb_cmn_rpt.c new file mode 100644 index 0000000..f4d62e0 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cmn_rpt.c @@ -0,0 +1,1226 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#if 1 + +void halbb_print_hist_2_buf_u8(struct bb_info *bb, u8 *val, u16 len, char *buf, + u16 buf_size) +{ + if (len == PHY_HIST_SIZE) { + halbb_snprintf(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10], val[11]); + } else if (len == (PHY_HIST_SIZE - 1)) { + halbb_snprintf(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10]); + } +} + +void halbb_print_hist_2_buf(struct bb_info *bb, u16 *val, u16 len, char *buf, + u16 buf_size) +{ + if (len == PHY_HIST_SIZE) { + halbb_snprintf(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10], val[11]); + } else if (len == (PHY_HIST_SIZE - 1)) { + halbb_snprintf(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10]); + } +} + +void halbb_rx_pop_hist(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + u8 pop_idx = 0; + bool is_cck = cmn_rpt->is_cck_rate; + + if (is_cck) + pop_idx = bb->bb_physts_i.bb_physts_rslt_0_i.pop_idx_cck; + else + pop_idx = bb->bb_physts_i.bb_physts_rslt_1_i.pop_idx; + + if (pop_idx >= POP_HIST_SIZE) + pop_idx = POP_HIST_SIZE - 1; + + if (is_cck) + cmn_rpt->bb_physts_pop_i.pop_hist_cck[pop_idx]++; + else + cmn_rpt->bb_physts_pop_i.pop_hist_ofdm[pop_idx]++; +} + +void halbb_rx_pkt_cnt_rpt_beacon(struct bb_info *bb, struct physts_rxd *desc) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + + if (desc->user_i[0].is_bcn) { + cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon++; + cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate= desc->data_rate; + } +} + +void halbb_rx_pkt_cnt_rpt_reset(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + + //halbb_mem_set(bb, cmn_rpt, 0, sizeof(struct bb_cmn_rpt_info)); + cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon = 0; + halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_all_i, 0, sizeof(struct bb_pkt_cnt_cap_info)); + halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_su_i, 0, sizeof(struct bb_pkt_cnt_su_info)); + halbb_mem_set(bb, &cmn_rpt->bb_rssi_su_acc_i, 0, sizeof(struct bb_rssi_su_acc_info)); + halbb_mem_set(bb, &cmn_rpt->bb_physts_hist_i, 0, sizeof(struct bb_physts_hist_info)); + halbb_mem_set(bb, &cmn_rpt->bb_physts_acc_i, 0, sizeof(struct bb_physts_acc_info)); + + /*[POP cnt reset]*/ + halbb_mem_set(bb, &cmn_rpt->bb_physts_pop_i, 0, sizeof(struct bb_physts_pop_info)); + + /*[MU]*/ + halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_mu_i, 0, sizeof(struct bb_pkt_cnt_mu_info)); + halbb_mem_set(bb, &cmn_rpt->bb_rssi_mu_acc_i, 0, sizeof(struct bb_rssi_mu_acc_info)); +} + +#define CMN_RPT_MU +#ifdef CMN_RPT_MU + +u16 halbb_get_plurality_rx_rate_mu(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i; + u16 max_num_tmp = 0; + u16 rx_rate_plurality = 0; + u16 i = 0; + u16 *pkt_cnt_tmp; + u8 rate_num_tmp; + u16 ofst_mode = 0; + u16 ofst_ss = 0; + u16 idx = 0; + bool plurality_is_legacy_rate = true; + + if (pkt_cnt->pkt_cnt_all == 0) { + return rx_rate_plurality; + } + + //BB_DBG(bb, DBG_CMN, "cnt_t= (%d)\n", pkt_cnt->pkt_cnt_all); + + /*HT, VHT, HE*/ + if (pkt_cnt->he_pkt_not_zero) { + pkt_cnt_tmp = pkt_cnt->pkt_cnt_he; + rate_num_tmp = HE_RATE_NUM; + ofst_mode = BB_HE_1SS_MCS0; + } else if (pkt_cnt->vht_pkt_not_zero) { + pkt_cnt_tmp = pkt_cnt->pkt_cnt_vht; + rate_num_tmp = VHT_RATE_NUM; + ofst_mode = BB_VHT_1SS_MCS0; + } else { + return rx_rate_plurality; + } + + for (i = 0; i < rate_num_tmp; i++) { + if (pkt_cnt_tmp[i] >= max_num_tmp) { + max_num_tmp = pkt_cnt_tmp[i]; + idx = i; + plurality_is_legacy_rate = false; + } + } + + if (plurality_is_legacy_rate) + return rx_rate_plurality; + + //BB_DBG(bb, DBG_CMN, "[T]idx_ori= (%d)\n", idx); + + ofst_ss = idx / HE_VHT_NUM_MCS; + + if (ofst_ss >= 0) /*>=2SS*/ + idx -= (ofst_ss * HE_VHT_NUM_MCS); + + //BB_DBG(bb, DBG_CMN, "ofst_ss= (%d), idx=%d\n", ofst_ss, idx); + + rx_rate_plurality = ofst_mode + (ofst_ss << 4) + idx; + //BB_DBG(bb, DBG_CMN, "[T]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp); + + return rx_rate_plurality; +} + +void halbb_mu_rate_idx_generate(struct bb_info *bb, struct physts_rxd *desc, u8 bw_idx, struct bb_rate_info *ra_i) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i; + u8 user = desc->user_num; + + if (user > MU_USER_MAX) { + BB_WARNING("[%s] user = %d\n", __func__, user); + return; + } + + ra_i->gi_ltf = desc->gi_ltf; + ra_i->bw = bw_idx; + ra_i->ss = psts_13->bb_physts_uer_info[user].n_sts; + ra_i->idx = psts_13->bb_physts_uer_info[user].mcs; + + if (psts_h->ie_map_type == VHT_MU) { + ra_i->mode = BB_VHT_MODE; + ra_i->rate_idx = GEN_VHT_RATE_IDX(ra_i->ss, ra_i->idx); + } else if (psts_h->ie_map_type == HE_MU) { + ra_i->mode = BB_HE_MODE; + ra_i->rate_idx = GEN_HE_RATE_IDX(ra_i->ss, ra_i->idx); + } else { + BB_WARNING("[%s] ie_map_type = %d", __func__, psts_h->ie_map_type); + return; + } + + ra_i->rate_idx_all = ra_i->rate_idx | (((u16)desc->gi_ltf & 0xf) << 12); +} + +void halbb_show_rssi_and_rate_distribution_mu(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i; + struct bb_rssi_mu_acc_info *acc = &cmn_rpt->bb_rssi_mu_acc_i; + struct bb_rssi_mu_avg_info *avg = &cmn_rpt->bb_rssi_mu_avg_i; + u8 rssi_avg_tmp = 0; + u8 rssi_tmp[HALBB_MAX_PATH]; + u16 pkt_cnt_ss = 0; + u8 i = 0, j =0; + u8 rate_num = bb->num_rf_path, ss_ofst = 0; + + avg->rssi_t_avg = (u8)HALBB_DIV(acc->rssi_t_avg_acc, pkt_cnt->pkt_cnt_all); + + for (i = 0; i < HALBB_MAX_PATH; i++) { + if (i >= bb->num_rf_path) + break; + + avg->rssi_t[i] = (u8)HALBB_DIV(acc->rssi_t_acc[i], pkt_cnt->pkt_cnt_all); + } + + /*@======VHT==========================================================*/ + if (pkt_cnt->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + for (j = 0; j < HE_VHT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_vht[ss_ofst + j]; + } + + if (pkt_cnt_ss == 0) { + rssi_avg_tmp = 0; + rssi_tmp[0] = 0; + rssi_tmp[1] = 0; + } else { + rssi_avg_tmp = avg->rssi_t_avg >> 1; + rssi_tmp[0] = avg->rssi_t[0] >> 1; + rssi_tmp[1] = avg->rssi_t[1] >> 1; + } + + BB_DBG(bb, DBG_CMN, + "*[MU] VHT %d-S RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1], + pkt_cnt_ss, + pkt_cnt->pkt_cnt_vht[ss_ofst + 0], + pkt_cnt->pkt_cnt_vht[ss_ofst + 1], + pkt_cnt->pkt_cnt_vht[ss_ofst + 2], + pkt_cnt->pkt_cnt_vht[ss_ofst + 3], + pkt_cnt->pkt_cnt_vht[ss_ofst + 4], + pkt_cnt->pkt_cnt_vht[ss_ofst + 5], + pkt_cnt->pkt_cnt_vht[ss_ofst + 6], + pkt_cnt->pkt_cnt_vht[ss_ofst + 7], + pkt_cnt->pkt_cnt_vht[ss_ofst + 8], + pkt_cnt->pkt_cnt_vht[ss_ofst + 9], + pkt_cnt->pkt_cnt_vht[ss_ofst + 10], + pkt_cnt->pkt_cnt_vht[ss_ofst + 11]); + + pkt_cnt_ss = 0; + } + + } + + /*@======HE==========================================================*/ + if (pkt_cnt->he_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + for (j = 0; j < HE_VHT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j]; + } + + if (pkt_cnt_ss == 0) { + rssi_avg_tmp = 0; + rssi_tmp[0] = 0; + rssi_tmp[1] = 0; + } else { + rssi_avg_tmp = avg->rssi_t_avg >> 1; + rssi_tmp[0] = avg->rssi_t[0] >> 1; + rssi_tmp[1] = avg->rssi_t[1] >> 1; + } + + BB_DBG(bb, DBG_CMN, + "*[MU] HE %d-SS RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1], + pkt_cnt_ss, + pkt_cnt->pkt_cnt_he[ss_ofst + 0], + pkt_cnt->pkt_cnt_he[ss_ofst + 1], + pkt_cnt->pkt_cnt_he[ss_ofst + 2], + pkt_cnt->pkt_cnt_he[ss_ofst + 3], + pkt_cnt->pkt_cnt_he[ss_ofst + 4], + pkt_cnt->pkt_cnt_he[ss_ofst + 5], + pkt_cnt->pkt_cnt_he[ss_ofst + 6], + pkt_cnt->pkt_cnt_he[ss_ofst + 7], + pkt_cnt->pkt_cnt_he[ss_ofst + 8], + pkt_cnt->pkt_cnt_he[ss_ofst + 9], + pkt_cnt->pkt_cnt_he[ss_ofst + 10], + pkt_cnt->pkt_cnt_he[ss_ofst + 11]); + + pkt_cnt_ss = 0; + } + + } + + /*@======SC_BW========================================================*/ + + if (pkt_cnt->sc20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG(bb, DBG_CMN, + "*[MU][Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc20[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]); + } + } + + if (pkt_cnt->sc40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG(bb, DBG_CMN, + "*[MU][Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc40[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]); + } + } +} + +void halbb_rx_pkt_mu_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + enum channel_width bw_curr; + u8 band_idx; + u8 ofst = rate_i->idx; + + if (rate_i->mode <= BB_HT_MODE) { + BB_WARNING("[%s] mode = %d", __func__, rate_i->mode); + return; + } + + pkt_cnt->pkt_cnt_all++; + if (rate_i->ss == 1) + pkt_cnt->pkt_cnt_1ss++; + else if (rate_i->ss == 2) + pkt_cnt->pkt_cnt_2ss++; + + band_idx = (desc->phy_idx == HW_PHY_0) ? 0 : 1; + bw_curr = bb->hal_com->band[band_idx].cur_chandef.bw; + + rx_bw = bw_curr; /*Will be removed, just for tmp debug using*/ + + if (rate_i->ss >= 2) + ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1)); + + if (rate_i->mode == BB_VHT_MODE) { + pkt_cnt->vht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1); + + if (rx_bw == bw_curr) { + pkt_cnt->pkt_cnt_vht[ofst]++; + return; + } + } else if (rate_i->mode == BB_HE_MODE) { + pkt_cnt->he_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1); + + if (rx_bw == bw_curr) { + pkt_cnt->pkt_cnt_he[ofst]++; + return; + } + } + + /*SC BW*/ + if (rx_bw != bw_curr) { + ofst = NOT_GREATER(ofst, LOW_BW_RATE_NUM - 1); + + if (rx_bw == CHANNEL_WIDTH_20) { + pkt_cnt->pkt_cnt_sc20[ofst]++; + pkt_cnt->sc20_occur = true; + } else { + pkt_cnt->pkt_cnt_sc40[ofst]++; + pkt_cnt->sc40_occur = true; + } + } +} + +void halbb_rx_pkt_mu_rssi_statistic(struct bb_info *bb) +{ + struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rssi_mu_acc_info *rssi_mu_acc = &cmn_rpt->bb_rssi_mu_acc_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + u32 *rssi_acc; + u8 i = 0; + + if (rate_i->mode <= BB_HT_MODE) { + BB_WARNING("[%s] mode = %d", __func__, rate_i->mode); + return; + } + + rssi_mu_acc->rssi_t_avg_acc += psts_h->rssi_avg; + rssi_acc = &rssi_mu_acc->rssi_t_acc[0]; + //BB_DBG(bb, DBG_PHY_STS, "Xt = %d\n", rssi_su_acc->rssi_t_avg_acc); + + /*HT/VHT/HE*/ + for (i = 0; i < HALBB_MAX_PATH; i++) { + if (i >= bb->num_rf_path) + break; + + rssi_acc[i] += (u32)psts_h->rssi[i]; + } + //BB_DBG(bb, DBG_PHY_STS, "rssi_acc = %d, %d\n", rssi_acc[0], rssi_acc[1]); +} + +#endif + +#define CMN_RPT_SU +#ifdef CMN_RPT_SU + +void halbb_show_phy_hitogram_su(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_physts_acc_info *acc = &cmn_rpt->bb_physts_acc_i; + struct bb_physts_avg_info *avg = &cmn_rpt->bb_physts_avg_i; + struct bb_physts_hist_info *hist = &cmn_rpt->bb_physts_hist_i; + struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i; + char buf[HALBB_SNPRINT_SIZE] = {0}; + u16 valid_cnt = pkt_cnt->pkt_cnt_t + pkt_cnt->pkt_cnt_ofdm; + + /*=== [EVM, SNR] =====================================================*/ + /*Threshold*/ + + //BB_DBG(bb, DBG_CMN, "[RESULT ACC] cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n", + // acc->cfo_avg_acc, acc->evm_max_acc, acc->evm_min_acc, acc->cn_avg_acc); + + //BB_DBG(bb, DBG_CMN, "valid_cnt=%d\n", valid_cnt); + + halbb_print_hist_2_buf_u8(bb, hist_th->evm_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf); + /*val*/ + avg->evm_1ss = (u8)HALBB_DIV(acc->evm_1ss, (pkt_cnt->pkt_cnt_1ss + pkt_cnt->pkt_cnt_ofdm)); + halbb_print_hist_2_buf(bb, hist->evm_1ss, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_1ss]", + (avg->evm_1ss >> 2), + halbb_show_fraction_num(avg->evm_1ss & 0x3, 2), bb->dbg_buf); + + avg->evm_max = (u8)HALBB_DIV(acc->evm_max_acc, pkt_cnt->pkt_cnt_2ss); + halbb_print_hist_2_buf(bb, hist->evm_max_hist, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_max]", + (avg->evm_max >> 2), + halbb_show_fraction_num(avg->evm_max & 0x3, 2), bb->dbg_buf); + + avg->evm_min = (u8)HALBB_DIV(acc->evm_min_acc, pkt_cnt->pkt_cnt_2ss); + halbb_print_hist_2_buf(bb, hist->evm_min_hist, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_min]", + (avg->evm_min >> 2), + halbb_show_fraction_num(avg->evm_min & 0x3, 2), bb->dbg_buf); + + + avg->snr_avg = (u8)HALBB_DIV(acc->snr_avg_acc, valid_cnt); + halbb_print_hist_2_buf(bb, hist->snr_avg_hist, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%02d.000) %s\n", "[SNR_avg]", + avg->snr_avg, bb->dbg_buf); + + /*=== [CN] ===========================================================*/ + /*Threshold*/ + halbb_print_hist_2_buf_u8(bb, hist_th->cn_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf); + /*val*/ + avg->cn_avg = (u8)HALBB_DIV(acc->cn_avg_acc, valid_cnt); + halbb_print_hist_2_buf(bb, hist->cn_avg_hist, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[CN_avg]", + (avg->cn_avg >> 1), + halbb_show_fraction_num(avg->cn_avg & 0x1, 1), bb->dbg_buf); + + /*=== [CFO] ==========================================================*/ + /*Threshold*/ + halbb_print_hist_2_buf_u8(bb, hist_th->cfo_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf); + /*val*/ + avg->cfo_avg = (s16)HALBB_DIV(acc->cfo_avg_acc, valid_cnt); + + halbb_print_sign_frac_digit(bb, avg->cfo_avg, 16, 2, buf, HALBB_SNPRINT_SIZE); + halbb_print_hist_2_buf(bb, hist->cfo_avg_hist, BB_HIST_SIZE, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "%-9s (%s K) %s\n", "[CFO_avg]", + buf, bb->dbg_buf); + BB_DBG(bb, DBG_CMN, "CFO_src: %s\n", + (bb->bb_cfo_trk_i.cfo_src == CFO_SRC_FD) ? "FD" : "Preamble"); + BB_DBG(bb, DBG_CMN, "valid_cnt = %d\n", valid_cnt); +} + +u16 halbb_get_plurality_rx_rate_su(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + u16 max_num_tmp = 0; + u16 rx_rate_plurality = 0; + u16 i = 0; + u16 *pkt_cnt_tmp; + u8 rate_num_tmp; + u16 ofst_mode = 0; + u16 ofst_ss = 0; + u16 idx = 0; + bool is_ht_mode = false; + bool plurality_is_legacy_rate = true; + + /*Legacy rate*/ + if (pkt_cnt->pkt_cnt_cck || pkt_cnt->pkt_cnt_ofdm) { + for (i = 0; i < LEGACY_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_legacy[i] >= max_num_tmp) { + max_num_tmp = pkt_cnt->pkt_cnt_legacy[i]; + rx_rate_plurality = i; + } + } + } + //BB_DBG(bb, DBG_CMN, "[LEGACY]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp); + + if (pkt_cnt->pkt_cnt_t == 0) { + return rx_rate_plurality; + } + + //BB_DBG(bb, DBG_CMN, "cnt_t= (%d)\n", pkt_cnt->pkt_cnt_t); + + /*HT, VHT, HE*/ + if (pkt_cnt->he_pkt_not_zero) { + pkt_cnt_tmp = pkt_cnt->pkt_cnt_he; + rate_num_tmp = HE_RATE_NUM; + ofst_mode = BB_HE_1SS_MCS0; + } else if (pkt_cnt->vht_pkt_not_zero) { + pkt_cnt_tmp = pkt_cnt->pkt_cnt_vht; + rate_num_tmp = VHT_RATE_NUM; + ofst_mode = BB_VHT_1SS_MCS0; + } else if (pkt_cnt->ht_pkt_not_zero) { + pkt_cnt_tmp = pkt_cnt->pkt_cnt_ht; + rate_num_tmp = HT_RATE_NUM; + ofst_mode = BB_HT_MCS0; + is_ht_mode = true; + } else { + return rx_rate_plurality; + } + + for (i = 0; i < rate_num_tmp; i++) { + if (pkt_cnt_tmp[i] >= max_num_tmp) { + max_num_tmp = pkt_cnt_tmp[i]; + idx = i; + plurality_is_legacy_rate = false; + } + } + + if (plurality_is_legacy_rate) + return rx_rate_plurality; + + //BB_DBG(bb, DBG_CMN, "[T]idx_ori= (%d)\n", idx); + + if (!is_ht_mode) { + ofst_ss = idx / HE_VHT_NUM_MCS; + + if (ofst_ss >= 0) /*>=2SS*/ + idx -= (ofst_ss * HE_VHT_NUM_MCS); + + //BB_DBG(bb, DBG_CMN, "ofst_ss= (%d), idx=%d\n", ofst_ss, idx); + } + + rx_rate_plurality = ofst_mode + (ofst_ss << 4) + idx; + //BB_DBG(bb, DBG_CMN, "[T]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp); + + return rx_rate_plurality; +} + +void halbb_show_rssi_and_rate_distribution_su(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_rssi_su_acc_info *acc = &cmn_rpt->bb_rssi_su_acc_i; + struct bb_rssi_su_avg_info *avg = &cmn_rpt->bb_rssi_su_avg_i; + u8 rssi_avg_tmp = 0; + u8 rssi_tmp[HALBB_MAX_PATH]; + u16 pkt_cnt_ss = 0; + u8 i = 0, j =0; + u8 rate_num = bb->num_rf_path, ss_ofst = 0; + + avg->rssi_cck_avg = (u8)HALBB_DIV(acc->rssi_cck_avg_acc, pkt_cnt->pkt_cnt_cck); + avg->rssi_ofdm_avg = (u8)HALBB_DIV(acc->rssi_ofdm_avg_acc, pkt_cnt->pkt_cnt_ofdm); + avg->rssi_t_avg = (u8)HALBB_DIV(acc->rssi_t_avg_acc, pkt_cnt->pkt_cnt_t); + + for (i = 0; i < HALBB_MAX_PATH; i++) { + if (i >= bb->num_rf_path) + break; + + avg->rssi_cck[i] = (u8)HALBB_DIV(acc->rssi_cck_acc[i], pkt_cnt->pkt_cnt_cck); + avg->rssi_ofdm[i] = (u8)HALBB_DIV(acc->rssi_ofdm_acc[i], pkt_cnt->pkt_cnt_ofdm); + avg->rssi_t[i] = (u8)HALBB_DIV(acc->rssi_t_acc[i], pkt_cnt->pkt_cnt_t); + //BB_DBG(bb, DBG_CMN, "*rssi_ofdm_avg %02d = rssi_ofdm_acc %02d / pkt_cnt_ofdm%02d}\n", + // avg->rssi_ofdm_avg, avg->rssi_ofdm[i], acc->rssi_ofdm_acc[i], pkt_cnt->pkt_cnt_ofdm); + } + + /*@======[Lgcy-non-data]=============================================*/ + BB_DBG(bb, DBG_CMN, "[Lgcy-non-data] {%d, %d, %d, %d | %d, %d, %d, %d, %d, %d, %d, %d} {%d}\n", + pkt_cnt->pkt_cnt_legacy_non_data[0], pkt_cnt->pkt_cnt_legacy_non_data[1], + pkt_cnt->pkt_cnt_legacy_non_data[2], pkt_cnt->pkt_cnt_legacy_non_data[3], + pkt_cnt->pkt_cnt_legacy_non_data[4], pkt_cnt->pkt_cnt_legacy_non_data[5], + pkt_cnt->pkt_cnt_legacy_non_data[6], pkt_cnt->pkt_cnt_legacy_non_data[7], + pkt_cnt->pkt_cnt_legacy_non_data[8], pkt_cnt->pkt_cnt_legacy_non_data[9], + pkt_cnt->pkt_cnt_legacy_non_data[10], pkt_cnt->pkt_cnt_legacy_non_data[11], + pkt_cnt->pkt_cnt_else_non_data); + + /*@======CCK=========================================================*/ + + BB_DBG(bb, DBG_CMN, "*CCK RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d}\n", + avg->rssi_cck_avg >> 1, + avg->rssi_cck[0] >> 1, avg->rssi_cck[1] >> 1, + pkt_cnt->pkt_cnt_cck, + pkt_cnt->pkt_cnt_legacy[0], pkt_cnt->pkt_cnt_legacy[1], + pkt_cnt->pkt_cnt_legacy[2], pkt_cnt->pkt_cnt_legacy[3]); + + /*@======OFDM========================================================*/ + BB_DBG(bb, DBG_CMN, "*OFDM RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d}\n", + avg->rssi_ofdm_avg >> 1, + avg->rssi_ofdm[0] >> 1, avg->rssi_ofdm[1] >> 1, + pkt_cnt->pkt_cnt_ofdm, + pkt_cnt->pkt_cnt_legacy[4], pkt_cnt->pkt_cnt_legacy[5], + pkt_cnt->pkt_cnt_legacy[6], pkt_cnt->pkt_cnt_legacy[7], + pkt_cnt->pkt_cnt_legacy[8], pkt_cnt->pkt_cnt_legacy[9], + pkt_cnt->pkt_cnt_legacy[10], pkt_cnt->pkt_cnt_legacy[11]); + + /*@======HT==========================================================*/ + + if (pkt_cnt->ht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + for (j = 0; j < HT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_ht[ss_ofst + j]; + } + + if (pkt_cnt_ss == 0) { + rssi_avg_tmp = 0; + rssi_tmp[0] = 0; + rssi_tmp[1] = 0; + } else { + rssi_avg_tmp = avg->rssi_t_avg >> 1; + rssi_tmp[0] = avg->rssi_t[0] >> 1; + rssi_tmp[1] = avg->rssi_t[1] >> 1; + } + + BB_DBG(bb, DBG_CMN, + "*HT%02d:%02d RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1], + pkt_cnt_ss, + pkt_cnt->pkt_cnt_ht[ss_ofst + 0], + pkt_cnt->pkt_cnt_ht[ss_ofst + 1], + pkt_cnt->pkt_cnt_ht[ss_ofst + 2], + pkt_cnt->pkt_cnt_ht[ss_ofst + 3], + pkt_cnt->pkt_cnt_ht[ss_ofst + 4], + pkt_cnt->pkt_cnt_ht[ss_ofst + 5], + pkt_cnt->pkt_cnt_ht[ss_ofst + 6], + pkt_cnt->pkt_cnt_ht[ss_ofst + 7]); + + pkt_cnt_ss = 0; + } + } + + /*@======VHT==========================================================*/ + if (pkt_cnt->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + for (j = 0; j < HE_VHT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_vht[ss_ofst + j]; + } + + if (pkt_cnt_ss == 0) { + rssi_avg_tmp = 0; + rssi_tmp[0] = 0; + rssi_tmp[1] = 0; + } else { + rssi_avg_tmp = avg->rssi_t_avg >> 1; + rssi_tmp[0] = avg->rssi_t[0] >> 1; + rssi_tmp[1] = avg->rssi_t[1] >> 1; + } + + BB_DBG(bb, DBG_CMN, + "*VHT %d-S RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1], + pkt_cnt_ss, + pkt_cnt->pkt_cnt_vht[ss_ofst + 0], + pkt_cnt->pkt_cnt_vht[ss_ofst + 1], + pkt_cnt->pkt_cnt_vht[ss_ofst + 2], + pkt_cnt->pkt_cnt_vht[ss_ofst + 3], + pkt_cnt->pkt_cnt_vht[ss_ofst + 4], + pkt_cnt->pkt_cnt_vht[ss_ofst + 5], + pkt_cnt->pkt_cnt_vht[ss_ofst + 6], + pkt_cnt->pkt_cnt_vht[ss_ofst + 7], + pkt_cnt->pkt_cnt_vht[ss_ofst + 8], + pkt_cnt->pkt_cnt_vht[ss_ofst + 9], + pkt_cnt->pkt_cnt_vht[ss_ofst + 10], + pkt_cnt->pkt_cnt_vht[ss_ofst + 11]); + + pkt_cnt_ss = 0; + } + + } + + /*@======HE==========================================================*/ + if (pkt_cnt->he_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + + for (j = 0; j < HE_VHT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j]; + } + + if (pkt_cnt_ss == 0) { + rssi_avg_tmp = 0; + rssi_tmp[0] = 0; + rssi_tmp[1] = 0; + } else { + rssi_avg_tmp = avg->rssi_t_avg >> 1; + rssi_tmp[0] = avg->rssi_t[0] >> 1; + rssi_tmp[1] = avg->rssi_t[1] >> 1; + } + + BB_DBG(bb, DBG_CMN, + "*HE %d-SS RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1], + pkt_cnt_ss, + pkt_cnt->pkt_cnt_he[ss_ofst + 0], + pkt_cnt->pkt_cnt_he[ss_ofst + 1], + pkt_cnt->pkt_cnt_he[ss_ofst + 2], + pkt_cnt->pkt_cnt_he[ss_ofst + 3], + pkt_cnt->pkt_cnt_he[ss_ofst + 4], + pkt_cnt->pkt_cnt_he[ss_ofst + 5], + pkt_cnt->pkt_cnt_he[ss_ofst + 6], + pkt_cnt->pkt_cnt_he[ss_ofst + 7], + pkt_cnt->pkt_cnt_he[ss_ofst + 8], + pkt_cnt->pkt_cnt_he[ss_ofst + 9], + pkt_cnt->pkt_cnt_he[ss_ofst + 10], + pkt_cnt->pkt_cnt_he[ss_ofst + 11]); + + pkt_cnt_ss = 0; + } + + } + + /*@======SC_BW========================================================*/ + + if (pkt_cnt->sc20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG(bb, DBG_CMN, + "*[Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc20[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]); + } + } + + if (pkt_cnt->sc40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG(bb, DBG_CMN, + "*[Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc40[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]); + } + } +} + +void halbb_rx_pkt_su_non_data_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + u8 ofst = rate_i->idx; + + if (rate_i->mode == BB_LEGACY_MODE) { + pkt_cnt->pkt_cnt_legacy_non_data[ofst]++; + } else { + pkt_cnt->pkt_cnt_else_non_data++; + } +} + +void halbb_rx_pkt_su_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + enum channel_width bw_curr; /*max bw in current link mode*/ + u8 band_idx; + u8 ofst = rate_i->idx; + + pkt_cnt->pkt_cnt_all++; + + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) + pkt_cnt->pkt_cnt_cck++; + else + pkt_cnt->pkt_cnt_ofdm++; + } else { + pkt_cnt->pkt_cnt_t++; + if (rate_i->ss == 1) + pkt_cnt->pkt_cnt_1ss++; + else if (rate_i->ss == 2) + pkt_cnt->pkt_cnt_2ss++; + } + + band_idx = (desc->phy_idx == HW_PHY_0) ? 0 : 1; + bw_curr = bb->hal_com->band[band_idx].cur_chandef.bw; + + if (rate_i->mode == BB_LEGACY_MODE) { + pkt_cnt->pkt_cnt_legacy[ofst]++; + return; + } + + + if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE) + ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1)); + + if (rate_i->mode == BB_HT_MODE) { + pkt_cnt->ht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1); + + if (rx_bw == bw_curr) { + pkt_cnt->pkt_cnt_ht[ofst]++; + return; + } + + } else if (rate_i->mode == BB_VHT_MODE) { + pkt_cnt->vht_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1); + + if (rx_bw == bw_curr) { + pkt_cnt->pkt_cnt_vht[ofst]++; + return; + } + + } else if (rate_i->mode == BB_HE_MODE) { + pkt_cnt->he_pkt_not_zero = true; + ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1); + + if (rx_bw == bw_curr) { + pkt_cnt->pkt_cnt_he[ofst]++; + return; + } + } + + /*SC BW*/ + if (rx_bw != bw_curr) { + ofst = NOT_GREATER(ofst, LOW_BW_RATE_NUM - 1); + + if (rx_bw == CHANNEL_WIDTH_20) { + pkt_cnt->pkt_cnt_sc20[ofst]++; + pkt_cnt->sc20_occur = true; + } else if (rx_bw == CHANNEL_WIDTH_40) { + pkt_cnt->pkt_cnt_sc40[ofst]++; + pkt_cnt->sc40_occur = true; + } else { + pkt_cnt->pkt_cnt_sc80[ofst]++; + pkt_cnt->sc80_occur = true; + } + } +} + +void halbb_rx_pkt_su_phy_hist(struct bb_info *bb) +{ + struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_physts_acc_info *acc = &cmn_rpt->bb_physts_acc_i; + struct bb_physts_hist_info *hist = &cmn_rpt->bb_physts_hist_i; + struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i; + u16 tmp_u16; + u8 intvl = 0; + s16 cfo; + + if (cmn_rpt->is_cck_rate) + return; + + //BB_DBG(bb, DBG_CMN, "[2]cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n", + // psts_1->cfo_avg, psts_1->evm_max, psts_1->evm_min, psts_1->cn_avg); + + if (rate_i->ss == 1) { + acc->evm_1ss += psts_1->evm_min; + intvl = halbb_find_intrvl(bb, (psts_1->evm_min >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE); + hist->evm_1ss[intvl]++; + } else { + /*EVM min/max Histogram*/ + acc->evm_min_acc += psts_1->evm_min; + intvl = halbb_find_intrvl(bb, (psts_1->evm_min >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE); + hist->evm_min_hist[intvl]++; + + acc->evm_max_acc += psts_1->evm_max; + intvl = halbb_find_intrvl(bb, (psts_1->evm_max >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE); + hist->evm_max_hist[intvl]++; + //BB_DBG(bb, DBG_CMN, "evm_max_hist[%d]=%d\n", intvl, hist->evm_max_hist[intvl]); + } + + /*SNR_avg Histogram*/ + acc->snr_avg_acc += psts_1->snr_avg; + intvl = halbb_find_intrvl(bb, psts_1->snr_avg, hist_th->evm_hist_th, BB_HIST_TH_SIZE); + hist->snr_avg_hist[intvl]++; + + /*CN_avg Histogram*/ + acc->cn_avg_acc += psts_1->cn_avg; + intvl = halbb_find_intrvl(bb, (psts_1->cn_avg >> 1), hist_th->cn_hist_th, BB_HIST_TH_SIZE); + hist->cn_avg_hist[intvl]++; + + /*CFO_avg Histogram*/ + if (bb_cfo_trk->cfo_src == CFO_SRC_FD) + cfo = psts_1->cfo_avg; + else + cfo = psts_1->cfo_pab_avg; + + tmp_u16 = (u16)ABS_16(cfo); + acc->cfo_avg_acc += cfo; + intvl = halbb_find_intrvl(bb, (tmp_u16 >> 2), hist_th->cfo_hist_th, BB_HIST_TH_SIZE); + hist->cfo_avg_hist[intvl]++; + + //BB_DBG(bb, DBG_CMN, "[ACC] cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n", + // acc->cfo_avg_acc, acc->evm_max_acc, acc->evm_min_acc, acc->cn_avg_acc); +} + +void halbb_rx_pkt_su_rssi_statistic(struct bb_info *bb) +{ + struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_rssi_su_acc_info *rssi_su_acc = &cmn_rpt->bb_rssi_su_acc_i; + struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i; + u32 *rssi_acc; + u8 i = 0; + + if (rate_i->mode == BB_LEGACY_MODE) { + if (cmn_rpt->is_cck_rate) { + rssi_su_acc->rssi_cck_avg_acc += psts_h->rssi_avg; + rssi_acc = &rssi_su_acc->rssi_cck_acc[0]; + //BB_DBG(bb, DBG_PHY_STS, "cck = %d\n", rssi_su_acc->rssi_cck_avg_acc); + } else { + rssi_su_acc->rssi_ofdm_avg_acc += psts_h->rssi_avg; + rssi_acc = &rssi_su_acc->rssi_ofdm_acc[0]; + //BB_DBG(bb, DBG_PHY_STS, "ofdm = %d\n", rssi_su_acc->rssi_ofdm_avg_acc); + } + } else { + rssi_su_acc->rssi_t_avg_acc += psts_h->rssi_avg; + rssi_acc = &rssi_su_acc->rssi_t_acc[0]; + //BB_DBG(bb, DBG_PHY_STS, "Xt = %d\n", rssi_su_acc->rssi_t_avg_acc); + } + + /*HT/VHT/HE*/ + for (i = 0; i < HALBB_MAX_PATH; i++) { + if (i >= bb->num_rf_path) + break; + + rssi_acc[i] += (u32)psts_h->rssi[i]; + } + //BB_DBG(bb, DBG_PHY_STS, "rssi_acc = %d, %d\n", rssi_acc[0], rssi_acc[1]); +} + +//#define ORI_RSSI_FLAG + +void halbb_rx_pkt_su_store_in_sta_info(struct bb_info *bb, struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + struct rtw_phl_stainfo_t *phl_sta; + struct rtw_rssi_info *rssi_t = NULL; + u8 ma_fac = 2; + u8 bb_macid; + u8 i = 0; + + if (desc->macid_su > PHL_MAX_STA_NUM) + BB_WARNING("[%s] macid_su=%d\n", __func__, desc->macid_su); + + bb_macid = bb->phl2bb_macid_table[desc->macid_su]; + + if (bb_macid > PHL_MAX_STA_NUM) + BB_WARNING("[%s] bb_macid=%d\n", __func__, bb_macid); + + phl_sta = bb->phl_sta_info[bb_macid]; + + if (!is_sta_active(phl_sta)) + return; + + if (phl_sta->macid > PHL_MAX_STA_NUM) + return; + + if (!phl_sta->hal_sta) + return; + + rssi_t = &phl_sta->hal_sta->rssi_stat; + + //BB_DBG(bb, DBG_PHY_STS, "desc->macid_su=%d, bb_macid=%d, phl_sta->macid=%d\n", + // desc->macid_su, bb_macid, phl_sta->macid); + + //BB_DBG(bb, DBG_PHY_STS, "[pre] psts_h->rssi_avg = %d, rssi_ma=%d\n", psts_h->rssi_avg, rssi_t->rssi_ma); + + if (desc->user_i[0].is_bcn) { + ma_fac = rssi_t->ma_factor_bcn; + if (rssi_t->rssi_bcn_ma == 0) { + rssi_t->rssi_bcn_ma = (s16)(psts_h->rssi_avg << RSSI_MA_H); + rssi_t->rssi_bcn = (s8)psts_h->rssi_avg; + } else { + rssi_t->rssi_bcn_ma = MA_ACC(rssi_t->rssi_bcn_ma, (u16)psts_h->rssi_avg, ma_fac, RSSI_MA_H); + rssi_t->rssi_bcn = (u8)GET_MA_VAL(rssi_t->rssi_bcn_ma, RSSI_MA_H); + } + rssi_t->pkt_cnt_bcn++; + } else { + ma_fac = rssi_t->ma_factor; + if (rssi_t->rssi_ma == 0) { + rssi_t->rssi_ma = (s16)(psts_h->rssi_avg << RSSI_MA_H); + rssi_t->rssi = (s8)psts_h->rssi_avg; + + if (!bb->bb_cmn_rpt_i.is_cck_rate) + rssi_t->snr_ma = (u16)psts_1->snr_avg << RSSI_MA_H; + //BB_DBG(bb, DBG_BIT21, "[First][macid:%d] snr=%d, rssi_ori=%d, rssi_ma=%d, rssi_ma16=%d\n", bb_macid, rssi_t->snr_ma, psts_h->rssi_avg, rssi_t->rssi, rssi_t->rssi_ma); + } else { + rssi_t->rssi_ma = MA_ACC(rssi_t->rssi_ma, (u16)psts_h->rssi_avg, ma_fac, RSSI_MA_H); + rssi_t->rssi = (u8)GET_MA_VAL(rssi_t->rssi_ma, RSSI_MA_H); + + if (!bb->bb_cmn_rpt_i.is_cck_rate) + rssi_t->snr_ma = MA_ACC(rssi_t->snr_ma, (u16)psts_1->snr_avg, ma_fac, RSSI_MA_H); + //BB_DBG(bb, DBG_BIT21, "[NORML][macid:%d] snr=%d, rssi_ori=%d, rssi_ma=%d, rssi_ma16=%d\n", bb_macid, rssi_t->snr_ma, psts_h->rssi_avg, rssi_t->rssi, rssi_t->rssi_ma); + } + + for (i = 0; i < HALBB_MAX_PATH; i++) { + if (!(physts->rx_path_en & BIT(i))) + continue; + + if (rssi_t->rssi_ma_path[i] == 0) { + rssi_t->rssi_ma_path[i] = (u16)(psts_h->rssi[i] << RSSI_MA_H); + } else { + rssi_t->rssi_ma_path[i] = MA_ACC(rssi_t->rssi_ma_path[i], (u16)psts_h->rssi[i], ma_fac, RSSI_MA_H); + } + } + + rssi_t->pkt_cnt_data++; + } + + //BB_DBG(bb, DBG_PHY_STS, "[%d] rssi = %d, rssi_ma=%d\n", bb_macid, rssi_t->rssi, rssi_t->rssi_ma); + + if (bb->bb_cmn_rpt_i.is_cck_rate) + rssi_t->rssi_cck = psts_h->rssi_avg; + else + rssi_t->rssi_ofdm = psts_h->rssi_avg; + + //BB_DBG(bb, DBG_PHY_STS, "[%d] rssi_cck = %d, rssi_ofdm=%d\n", bb_macid, rssi_t->rssi_cck, rssi_t->rssi_ofdm); +} + +void halbb_get_rx_pkt_cnt_rpt_su(struct bb_info *bb, struct bb_pkt_cnt_su_info *pkt_cnt_rpt) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + + halbb_mem_cpy(bb, pkt_cnt_rpt, pkt_cnt, sizeof(struct bb_pkt_cnt_su_info)); +} +#endif + +void halbb_cmn_info_rpt_store_data(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bb_pkt_cnt_su_store_info *store = &cmn_rpt->bb_pkt_cnt_su_store_i; + + store->ht_pkt_not_zero = pkt_cnt->ht_pkt_not_zero; + store->vht_pkt_not_zero = pkt_cnt->vht_pkt_not_zero; + store->he_pkt_not_zero = pkt_cnt->he_pkt_not_zero; +} + +void halbb_cmn_info_rpt_reset(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + + cmn_rpt->bb_pkt_cnt_bcn_i.beacon_cnt_in_period = cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon; + cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon = 0; + + bb->bb_ch_i.rxsc_l = 0xff; + bb->bb_ch_i.rxsc_20 = 0xff; + bb->bb_ch_i.rxsc_40 = 0xff; + bb->bb_ch_i.rxsc_80 = 0xff; + + halbb_rx_pkt_cnt_rpt_reset(bb); +} + +void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i; + enum channel_width rx_bw = psts_1->bw_idx; + + if (desc->is_su) { + halbb_rate_idx_parsor(bb, desc->data_rate, (enum rtw_gi_ltf)desc->gi_ltf, &cmn_rpt->bb_rate_i); + } else if (physts->physts_bitmap_recv & BIT(IE13_DL_MU_DEF)) { + halbb_mu_rate_idx_generate(bb, desc, psts_1->bw_idx, &cmn_rpt->bb_rate_i); + } else { + BB_DBG(bb, DBG_PHY_STS, "[MU] physts_bitmap_recv=%d\n", physts->physts_bitmap_recv); + return; + } + + cmn_rpt->is_cck_rate = halbb_is_cck_rate(bb, desc->data_rate); + physts->rx_path_en = (cmn_rpt->is_cck_rate) ? psts_0->rx_path_en_cck : psts_1->rx_path_en; + + if (cmn_rpt->bb_rate_i.mode == BB_LEGACY_MODE) + bb->bb_ch_i.rxsc_l = psts_1->rxsc; + else if (psts_1->bw_idx == CHANNEL_WIDTH_20) + bb->bb_ch_i.rxsc_20 = psts_1->rxsc; + else if (psts_1->bw_idx == CHANNEL_WIDTH_40) + bb->bb_ch_i.rxsc_40 = psts_1->rxsc; + else if (psts_1->bw_idx == CHANNEL_WIDTH_80) + bb->bb_ch_i.rxsc_80 = psts_1->rxsc; + else if (psts_1->bw_idx == CHANNEL_WIDTH_160) + bb->bb_ch_i.rxsc_160 = psts_1->rxsc; + + BB_DBG(bb, DBG_PHY_STS, "is_su = %d\n", desc->is_su); + + if (desc->is_su) { + if (desc->user_i[0].is_data || desc->user_i[0].is_bcn) {/*@data frame only*/ + halbb_rx_pkt_su_store_in_sta_info(bb, desc); + halbb_rx_pkt_su_cnt_rpt(bb, desc, rx_bw); + halbb_rx_pkt_su_rssi_statistic(bb); + halbb_rx_pkt_su_phy_hist(bb); + + if (desc->user_i[0].is_bcn) + halbb_rx_pkt_cnt_rpt_beacon(bb, desc); + } else { + halbb_rx_pkt_su_non_data_cnt_rpt(bb, desc, rx_bw); + } + } else { + halbb_rx_pkt_mu_cnt_rpt(bb, desc, rx_bw); + halbb_rx_pkt_mu_rssi_statistic(bb); + } + halbb_rx_pop_hist(bb); + halbb_idle_time_pwr_physts(bb, desc, cmn_rpt->is_cck_rate); +} + +void halbb_physts_hist_init(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i; + u8 evm_hist_th[BB_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35}; + u8 cn_hist_th[BB_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 18}; + u8 cfo_hist_th[BB_HIST_TH_SIZE] = {1, 5, 10, 15, 20, 30, 60, 90, 120, 150, 200}; + + halbb_mem_cpy(bb, hist_th->evm_hist_th, evm_hist_th, BB_HIST_TH_SIZE); + halbb_mem_cpy(bb, hist_th->cn_hist_th, cn_hist_th, BB_HIST_TH_SIZE); + halbb_mem_cpy(bb, hist_th->cfo_hist_th, cfo_hist_th, BB_HIST_TH_SIZE); +} + +void halbb_cmn_rpt_init(struct bb_info *bb) +{ + BB_DBG(bb, DBG_DBG_API, "%s\n", __func__); + + halbb_physts_hist_init(bb); + halbb_rx_pkt_cnt_rpt_reset(bb); +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_cmn_rpt.h b/phl/hal_g6/phy/bb/halbb_cmn_rpt.h new file mode 100644 index 0000000..3134ceb --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cmn_rpt.h @@ -0,0 +1,144 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CMN_RPT_H__ +#define __HALBB_CMN_RPT_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define RSSI_MA_H 4 /*moving average factor for RSSI: 2^4=16 */ +#define RSSI_MA_M 3 +#define RSSI_MA_L 2 +#define RSSI_MA_UL 1 + +#define BB_HIST_SIZE 12 +#define BB_HIST_TH_SIZE (BB_HIST_SIZE - 1) + +#define POP_HIST_SIZE 4 + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_rssi_mu_acc_info { /*all in U(8,1)*/ + /*acc value*/ + u32 rssi_t_avg_acc; + u32 rssi_t_acc[HALBB_MAX_PATH]; /*VHT, HE*/ +}; + +struct bb_pkt_cnt_bcn_info { + u8 pkt_cnt_beacon; + u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ + u16 beacon_phy_rate; +}; + +struct bb_rssi_su_acc_info { /*all in U(8,1)*/ + /*acc value*/ + u32 rssi_cck_avg_acc; + u32 rssi_cck_acc[HALBB_MAX_PATH]; + u32 rssi_ofdm_avg_acc; + u32 rssi_ofdm_acc[HALBB_MAX_PATH]; /*L-OFDM*/ + u32 rssi_t_avg_acc; + u32 rssi_t_acc[HALBB_MAX_PATH]; /*HT, VHT, HE*/ +}; + +struct bb_pkt_cnt_cap_info { + u32 pkt_cnt_ldpc; /*pkt_cnt_ofdm = pkt_cnt_ldpc + pkt_cnt_bcc*/ + u32 pkt_cnt_bcc; + u32 pkt_cnt_stbc; + u32 pkt_cnt_subf; + u32 pkt_cnt_mubf; +}; + +struct bb_physts_hist_info { + u16 evm_1ss[BB_HIST_SIZE]; + u16 evm_min_hist[BB_HIST_SIZE]; + u16 evm_max_hist[BB_HIST_SIZE]; + u16 snr_avg_hist[BB_HIST_SIZE]; + u16 cn_avg_hist[BB_HIST_SIZE]; + u16 cfo_avg_hist[BB_HIST_SIZE]; /*ABS(cfo) 0~256 Khz*/ +}; + +struct bb_physts_hist_th_info { + u8 evm_hist_th[BB_HIST_TH_SIZE]; /*threshold*/ + u8 cn_hist_th[BB_HIST_TH_SIZE]; /*threshold*/ + u8 cfo_hist_th[BB_HIST_TH_SIZE]; /*threshold*/ +}; + +struct bb_physts_acc_info { + u32 evm_1ss; /*U(8,2)*/ /*only for 1SS & L-OFDM*/ + u32 evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u32 evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/ + u32 snr_avg_acc; /*U(6,0)*/ + u32 cn_avg_acc; /*U(7,1)*/ + s32 cfo_avg_acc; /*U(8,2)*/ +}; + +struct bb_physts_avg_info { + u8 evm_1ss; /*U(8,2) 0~63*/ + u8 evm_min; /*U(8,2) 0~63*/ + u8 evm_max; /*U(8,2) 0~63*/ + u8 snr_avg; /*U(6,0) 0~63*/ + u8 cn_avg; /*U(7,1) 0~63*/ + s16 cfo_avg; /*U(16,2) 0~512*/ +}; + +struct bb_physts_pop_info { + u16 pop_hist_cck[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/ + u16 pop_hist_ofdm[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/ +}; + +struct bb_cmn_rpt_info { + bool is_cck_rate; + u8 consec_idle_prd_su; /*consecutive idle period*/ + u8 consec_idle_prd_mu; + struct bb_rate_info bb_rate_i; + struct bb_pkt_cnt_bcn_info bb_pkt_cnt_bcn_i; /*beacon info*/ + struct bb_pkt_cnt_cap_info bb_pkt_cnt_all_i; /*capibility info*/ + struct bb_pkt_cnt_su_info bb_pkt_cnt_su_i; /*Packet count*/ + struct bb_rssi_su_acc_info bb_rssi_su_acc_i; /*acc RSSI*/ + struct bb_rssi_su_avg_info bb_rssi_su_avg_i; /*avg RSSI*/ + struct bb_physts_hist_th_info bb_physts_hist_th_i; + struct bb_physts_hist_info bb_physts_hist_i; /*phy-sts histogram*/ + struct bb_physts_acc_info bb_physts_acc_i; /*acc phy-sts*/ + struct bb_physts_avg_info bb_physts_avg_i; /*avg phy-sts*/ + struct bb_physts_pop_info bb_physts_pop_i; /*pop info*/ + /*[MU]*/ + struct bb_pkt_cnt_mu_info bb_pkt_cnt_mu_i; /*Packet count*/ + struct bb_rssi_mu_acc_info bb_rssi_mu_acc_i; /*acc RSSI*/ + struct bb_rssi_mu_avg_info bb_rssi_mu_avg_i; /*avg RSSI*/ + struct bb_pkt_cnt_su_store_info bb_pkt_cnt_su_store_i; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +u16 halbb_get_plurality_rx_rate_mu(struct bb_info *bb); +u16 halbb_get_plurality_rx_rate_su(struct bb_info *bb); +void halbb_show_phy_hitogram_su(struct bb_info *bb); +void halbb_show_rssi_and_rate_distribution_mu(struct bb_info *bb); +void halbb_show_rssi_and_rate_distribution_su(struct bb_info *bb); +void halbb_rx_pkt_cnt_rpt_reset(struct bb_info *bb); +void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc); +void halbb_cmn_info_rpt_store_data(struct bb_info *bb); +void halbb_cmn_info_rpt_reset(struct bb_info *bb); +void halbb_cmn_rpt_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_cmn_rpt_ex.h b/phl/hal_g6/phy/bb/halbb_cmn_rpt_ex.h new file mode 100644 index 0000000..2993a6f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_cmn_rpt_ex.h @@ -0,0 +1,104 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_CMN_RPT_EX_H__ +#define __HALBB_CMN_RPT_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_rssi_mu_avg_info { /*all in U(8,1)*/ + u8 rssi_t_avg; + u8 rssi_t[HALBB_MAX_PATH]; /*VHT, HE*/ +}; + +struct bb_rssi_su_avg_info { /*all in U(8,1)*/ + u8 rssi_cck_avg; + u8 rssi_cck[HALBB_MAX_PATH]; + u8 rssi_ofdm_avg; + u8 rssi_ofdm[HALBB_MAX_PATH]; /*L-OFDM*/ + u8 rssi_t_avg; + u8 rssi_t[HALBB_MAX_PATH]; /*HT, VHT, HE*/ +}; + +struct bb_pkt_cnt_mu_info { + /*====[Phy rate counter]=============================================*/ + u16 pkt_cnt_all; /*VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/ + u16 pkt_cnt_1ss; /*VHT, HE*/ + u16 pkt_cnt_2ss; /*VHT, HE*/ + u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/ + bool sc20_occur; + /*VHT*/ + u16 pkt_cnt_vht[VHT_RATE_NUM]; + u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/ + bool vht_pkt_not_zero; + bool sc40_occur; + /*HE*/ + u16 pkt_cnt_he[HE_RATE_NUM]; + bool he_pkt_not_zero; +}; + +struct bb_pkt_cnt_su_store_info { + bool ht_pkt_not_zero; + bool vht_pkt_not_zero; + bool he_pkt_not_zero; +}; + +struct bb_pkt_cnt_su_info { + /*====[Phy rate counter]=============================================*/ + u16 pkt_cnt_all; /*CCK + OFDM + HT, VHT, HE*/ + u16 pkt_cnt_cck; + u16 pkt_cnt_ofdm; /*L-OFDM*/ + u16 pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/ + u16 pkt_cnt_1ss; /*HT, VHT, HE*/ + u16 pkt_cnt_2ss; /*HT, VHT, HE*/ + /*Legacy*/ + u16 pkt_cnt_legacy[LEGACY_RATE_NUM]; + /*HT*/ + u16 pkt_cnt_ht[HT_RATE_NUM]; + u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/ + bool ht_pkt_not_zero; + bool sc20_occur; + /*VHT*/ + u16 pkt_cnt_vht[VHT_RATE_NUM]; + u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/ + bool vht_pkt_not_zero; + bool sc40_occur; + /*HE*/ + u16 pkt_cnt_he[HE_RATE_NUM]; + u16 pkt_cnt_sc80[LOW_BW_RATE_NUM]; /*@80M SC*/ + bool he_pkt_not_zero; + bool sc80_occur; + /*non_data packet*/ + u16 pkt_cnt_legacy_non_data[LEGACY_RATE_NUM]; + u16 pkt_cnt_else_non_data; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_get_rx_pkt_cnt_rpt_su(struct bb_info *bb, struct bb_pkt_cnt_su_info *pkt_cnt_rpt); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dbcc.c b/phl/hal_g6/phy/bb/halbb_dbcc.c new file mode 100644 index 0000000..e753cc9 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbcc.c @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" +#ifdef HALBB_DBCC_SUPPORT + +struct bb_info *halbb_get_curr_bb_pointer(struct bb_info *bb, + enum phl_phy_idx phy_idx) +{ + if (phy_idx == bb->bb_phy_idx) { + BB_DBG(bb, DBG_DBCC, "new_phy_idx(%d) = curr_bb_phy_idx(%d)\n", phy_idx, bb->bb_phy_idx); + return bb; + } else { + BB_DBG(bb, DBG_DBCC, "new_phy_idx(%d) != curr_bb_phy_idx(%d)\n", phy_idx, bb->bb_phy_idx); + if (bb->bb_phy_hooker) { + return bb->bb_phy_hooker; + } else { + BB_WARNING("[%s] bb_phy_hooker==NULL", __func__); + return bb; + } + } +} + +void halbb_dbcc_demo_func(struct bb_info *bb) +{ + BB_DBG(bb, DBG_DBCC, "[%s]phy_idx={%d}\n", __func__, bb->bb_phy_idx); + +} + +u32 +halbb_buffer_init_phy1(struct bb_info *bb_0) +{ + struct bb_info *bb_1 = NULL; + + if (!bb_0) { + BB_WARNING("[%s]*bb_phy_0 = NULL\n", __func__); + return RTW_HAL_STATUS_BB_INIT_FAILURE; + } + + bb_1 = halbb_mem_alloc(bb_0, sizeof(struct bb_info)); + + if (!bb_1) { + BB_WARNING("[%s]*bb_phy_1 = NULL\n", __func__); + return RTW_HAL_STATUS_BB_INIT_FAILURE; + } + + bb_1->bb_phy_hooker = bb_0; + bb_1->bb_phy_idx = HW_PHY_1; + bb_0->bb_phy_hooker = bb_1; + bb_1->bb_phy_hooker = bb_0; + bb_1->bb_cmn_hooker = bb_0->bb_cmn_hooker; + + bb_1->phl_com = bb_0->phl_com;/*shared memory for all components*/ + bb_1->hal_com = bb_0->hal_com;/*shared memory for phl and hal*/ + //bb_phy_1->phl_sta_info = bb_phy_0->phl_sta_info; + + halbb_dbg_comp_init(bb_1); + halbb_cmn_info_self_init(bb_1); + //halbb_timer_ctrl(bb_1, BB_INIT_TIMER); + //halbb_dm_init(bb_1, bb->bb_phy_idx); + + BB_DBG(bb_0, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_0->bb_phy_idx, bb_1->bb_phy_idx); + BB_DBG(bb_1, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_0->bb_phy_idx, bb_1->bb_phy_idx); + + BB_DBG(bb_0, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_1->bb_phy_hooker->bb_phy_idx, bb_0->bb_phy_hooker->bb_phy_idx); + BB_DBG(bb_1, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_1->bb_phy_hooker->bb_phy_idx, bb_0->bb_phy_hooker->bb_phy_idx); + + return RTW_HAL_STATUS_SUCCESS; +} + +void halbb_dbcc_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u16 i = 0; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "phy {0/1}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "init\n"); + return; + } + + if (_os_strcmp(input[1], "phy") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + if (val[0] == 1) + bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx = HW_PHY_1; + else + bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx = HW_PHY_0; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "echo cmd convert to phy-%d mode\n", + bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx); + + bb = halbb_get_curr_bb_pointer(bb, bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb_phy_idx=%d\n", bb->bb_phy_idx); + + } else if (_os_strcmp(input[1], "init") == 0) { + //for (i = 0; i < 4; i++) { + // HALBB_SCAN(input[2 + i], DCMD_DECIMAL, &val[i]); + //} + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[DBG]phy_idx={%d}\n", bb->bb_phy_idx); + + BB_DBG(bb, DBG_DBCC, "phy0->phy1\n"); + bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy0->phy1*/ + BB_DBG(bb, DBG_DBCC, "phy1->phy1\n"); + bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy1->phy1*/ + BB_DBG(bb, DBG_DBCC, "phy1->phy0\n"); + bb = halbb_get_curr_bb_pointer(bb, HW_PHY_0); /*phy1->phy0*/ + BB_DBG(bb, DBG_DBCC, "phy0->phy0\n"); + bb = halbb_get_curr_bb_pointer(bb, HW_PHY_0); /*phy0->phy0*/ + BB_DBG(bb, DBG_DBCC, "phy0->phy1\n"); + bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy0->phy1*/ + + //halbb_buffer_init_phy1(bb); + //halbb_dbg_comp_init(bb); + //halbb_dm_init(bb, bb->bb_phy_idx); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[DBG]phy_idx={%d} Init OK\n", bb->bb_phy_idx); + } +} + +#endif + + + diff --git a/phl/hal_g6/phy/bb/halbb_dbcc.h b/phl/hal_g6/phy/bb/halbb_dbcc.h new file mode 100644 index 0000000..ddb376d --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbcc.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DBCC_H__ +#define __HALBB_DBCC_H__ +#ifdef HALBB_DBCC_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_dbcc_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +struct bb_info *halbb_get_curr_bb_pointer(struct bb_info *bb, + enum phl_phy_idx phy_idx); +u32 halbb_buffer_init_phy1(struct bb_info *bb_phy_0); +#endif +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_dbcc_ex.h b/phl/hal_g6/phy/bb/halbb_dbcc_ex.h new file mode 100644 index 0000000..77bcdf9 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbcc_ex.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DBCC_EX_H__ +#define __HALBB_DBCC_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_dbg.c b/phl/hal_g6/phy/bb/halbb_dbg.c new file mode 100644 index 0000000..0c6f94a --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg.c @@ -0,0 +1,1581 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "halbb_precomp.h" + +#define HALBB_DBG_DVLP_FLAG 1 + +void halbb_dbg_comp_init(struct bb_info *bb) +{ + #if 0 + if (bb->phl_com->bb_dbg_comp_manual_cfg != 0xffffffff) { + bb->dbg_component = bb->phl_com->bb_dbg_comp_manual_cfg; + return; + } + #endif + + bb->dbg_component = + /*DBG_RA | */ + /*DBG_FA_CNT | */ + /*DBG_RSSI_MNTR | */ + /*DBG_DFS | */ + /*DBG_EDCCA | */ + /*DBG_ENV_MNTR | */ + /*DBG_CFO_TRK | */ + /*DBG_PHY_STATUS | */ + /*DBG_COMMON_FLOW | */ + /*DBG_IC_API | */ + /*DBG_DBG_API | */ + /*DBG_DBCC | */ + /*DBG_DM_SUMMARY | */ + /*DBG_PHY_CONFIG | */ + /*DBG_INIT | */ + /*DBG_DIG | */ + /*DBG_CMN | */ + 0; + + BB_DBG(bb, DBG_INIT, "dbg_comp = 0x%llx\n", bb->dbg_component); + +} + +void halbb_print_devider(struct bb_info *bb, u8 len, bool with_space) +{ + + if (len == BB_DEVIDER_LEN_32) + BB_TRACE("--------------------------------\n"); + else + BB_TRACE("----------------\n"); + + if (with_space) + BB_TRACE("\n"); +} + +#ifdef HALBB_TDMA_CR_SUPPORT + +void halbb_tdma_cr_sel_io_en(struct bb_info *bb) +{ + BB_DBG(bb, DBG_DBG_API, "[%s]===>\n", __func__); + + halbb_tdma_cr_sel_main(bb); +} + +void halbb_tdma_cr_sel_callback(void *context) +{ + struct bb_info *bb = (struct bb_info *)context; + struct halbb_timer_info *timer = &bb->bb_dbg_i.tdma_cr_timer_i; + + BB_DBG(bb, DBG_DBG_API, "[%s]===>\n", __func__); + timer->timer_state = BB_TIMER_IDLE; + + if (bb->phl_com->hci_type == RTW_HCI_PCIE) + halbb_tdma_cr_sel_io_en(bb); + else + rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx); +} + +void halbb_tdma_cr_timer_init(struct bb_info *bb) +{ + struct halbb_timer_info *timer = &bb->bb_dbg_i.tdma_cr_timer_i; + + BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__); + + timer->event_idx = BB_EVENT_TIMER_TDMA_CR; + timer->timer_state = BB_TIMER_IDLE; + + halbb_init_timer(bb, &timer->timer_list, halbb_tdma_cr_sel_callback, bb, "halbb_tdma_cr"); +} + +void halbb_tdma_cr_sel_main(struct bb_info *bb) +{ + struct bb_dbg_info *dbg = &bb->bb_dbg_i; + u32 period = 0; + u32 val_new = 0, val_old = 0; + + if (!dbg->tdma_cr_en) { + BB_DBG(bb, DBG_DBG_API, "[%s] tdma_cr_en = %d\n", __func__, dbg->tdma_cr_en); + return; + } + + if (dbg->tdma_cr_state == 0) { + val_old = dbg->tdma_cr_val_1; + val_new = dbg->tdma_cr_val_0; + period = dbg->tdma_cr_period_0; + dbg->tdma_cr_state = 1; /*CR0*/ + } else { /*PFD_LEGACY*/ + val_old = dbg->tdma_cr_val_0; + val_new = dbg->tdma_cr_val_1; + period = dbg->tdma_cr_period_1; + dbg->tdma_cr_state= 0; /*CR1*/ + } + + halbb_set_reg(bb, dbg->tdma_cr_idx, dbg->tdma_cr_mask, val_new); + + dbg->tdma_cr_timer_i.cb_time = period; + halbb_cfg_timers(bb, BB_SET_TIMER, &dbg->tdma_cr_timer_i); + + BB_DBG(bb, DBG_DBG_API, "Reg 0x%x[0x%x] = {0x%x -> 0x%x}, period=%d ms\n", + dbg->tdma_cr_idx, dbg->tdma_cr_mask, + val_old , val_new, period); +} + +void halbb_tdma_cr_sel_deinit(struct bb_info *bb) +{ + BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__); +} + +void halbb_tdma_cr_sel_init(struct bb_info *bb) +{ + struct bb_dbg_info *dbg = &bb->bb_dbg_i; + + BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__); + dbg->tdma_cr_en = false; + dbg->tdma_cr_period_0 = 50; + dbg->tdma_cr_period_1 = 50; + dbg->tdma_cr_idx = 0; + dbg->tdma_cr_state = 0; +} +#endif + +#if 1 /*debug port - relative*/ +void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + u32 reg_value = 0; + + reg_value = enable ? 1 : 0; + halbb_set_reg(bb, cr->clk_en, cr->clk_en_m, reg_value); + halbb_set_reg(bb, cr->dbgport_en, cr->dbgport_en_m, reg_value); + +} + +u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + u32 val = 0; + u32 dbg_port, ip; + + ip = halbb_get_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m); + dbg_port = halbb_get_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m); + + val = (ip << 8) | (dbg_port & 0xff); + + return val; +} + +void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + + halbb_set_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m, ip); +} + +void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + + halbb_set_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m, dbg_port); +} + +bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority) +{ + + bool dbg_port_result = false; + + if (curr_dbg_priority > bb->pre_dbg_priority) { + + halbb_bb_dbg_port_clock_en(bb, true); + + BB_DBG(bb, DBG_DBG_API, + "DbgPort racing success, Cur_priority=((%d)), Pre_priority=((%d))\n", + curr_dbg_priority, bb->pre_dbg_priority); + + bb->pre_dbg_priority = curr_dbg_priority; + dbg_port_result = true; + } + + return dbg_port_result; +} + +void halbb_release_bb_dbg_port(struct bb_info *bb) +{ + halbb_bb_dbg_port_clock_en(bb, false); + bb->pre_dbg_priority = DBGPORT_RELEASE; + BB_DBG(bb, DBG_DBG_API, "Release BB dbg_port\n"); +} + +u32 halbb_get_bb_dbg_port_val(struct bb_info *bb) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + u32 dbg_port_value = 0; + + dbg_port_value = halbb_get_reg(bb, cr->dbgport_val, cr->dbgport_val_m); + BB_DBG(bb, DBG_DBG_API, "dbg_port_value = 0x%x\n", dbg_port_value); + + return dbg_port_value; +} + +void halbb_dbgport_dump_all(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len) +{ + switch (bb->ic_type) { + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_dbgport_dump_all_8852a(bb, _used, output, _out_len); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_dbgport_dump_all_8852a_2(bb, _used, output, _out_len); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_dbgport_dump_all_8852b(bb, _used, output, _out_len); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_dbgport_dump_all_8852c(bb, _used, output, _out_len); + break; + #endif + + default: + break; + } +} + +void halbb_dbgport_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dp = 0; /*debug port value*/ + u8 dbg[32]; + u8 tmp = 0; + u8 i; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{dbg_port_ip} {dbg_port_idx}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{dump_all}\n"); + return; + } + + if (!halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{Racing Fail}\n"); + return; + } + + if (_os_strcmp(input[1], "dump_all") == 0) { + halbb_dbgport_dump_all(bb, _used, output, _out_len); + return; + } else { + + HALBB_SCAN(input[1], DCMD_HEX, &val[0]); + HALBB_SCAN(input[2], DCMD_HEX, &val[1]); + + halbb_set_bb_dbg_port_ip(bb, (enum bb_dbg_port_ip_t)val[0]); + halbb_set_bb_dbg_port(bb, val[1]); + dp = halbb_get_bb_dbg_port_val(bb); + halbb_release_bb_dbg_port(bb); + + for (i = 0; i < 32; i++) + dbg[i] = (u8)((dp & BIT(i)) >> i); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Dbg Port[0x%02x, 0x%03x] = 0x08%x\n", val[0], val[1], dp); + + for (i = 4; i != 0; i--) { + tmp = 8 * (i - 1); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "val[%02d:%02d] = 8b'%d %d %d %d %d %d %d %d\n", + tmp + 7, tmp, dbg[tmp + 7], dbg[tmp + 6], + dbg[tmp + 5], dbg[tmp + 4], dbg[tmp + 3], + dbg[tmp + 2], dbg[tmp + 1], dbg[tmp + 0]); + } + } +} +#endif + +#if HALBB_DBG_DVLP_FLAG /*Common debug message - relative*/ +void halbb_rx_rate_distribution_su_cnsl(struct bb_info *bb, u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + u8 i = 0; + u8 rate_num = bb->num_rf_path, ss_ofst = 0; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, "[RxRate Cnt] =============>\n"); + + /*@======CCK=========================================================*/ + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "* CCK = {%d, %d, %d, %d}\n", + pkt_cnt->pkt_cnt_legacy[0], pkt_cnt->pkt_cnt_legacy[1], + pkt_cnt->pkt_cnt_legacy[2], pkt_cnt->pkt_cnt_legacy[3]); + + /*@======OFDM========================================================*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + pkt_cnt->pkt_cnt_legacy[4], pkt_cnt->pkt_cnt_legacy[5], + pkt_cnt->pkt_cnt_legacy[6], pkt_cnt->pkt_cnt_legacy[7], + pkt_cnt->pkt_cnt_legacy[8], pkt_cnt->pkt_cnt_legacy[9], + pkt_cnt->pkt_cnt_legacy[10], pkt_cnt->pkt_cnt_legacy[11]); + + /*@======HT==========================================================*/ + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + pkt_cnt->pkt_cnt_ht[ss_ofst + 0], + pkt_cnt->pkt_cnt_ht[ss_ofst + 1], + pkt_cnt->pkt_cnt_ht[ss_ofst + 2], + pkt_cnt->pkt_cnt_ht[ss_ofst + 3], + pkt_cnt->pkt_cnt_ht[ss_ofst + 4], + pkt_cnt->pkt_cnt_ht[ss_ofst + 5], + pkt_cnt->pkt_cnt_ht[ss_ofst + 6], + pkt_cnt->pkt_cnt_ht[ss_ofst + 7]); + } + + + /*@======VHT==========================================================*/ + + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "* VHT-%d ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_vht[ss_ofst + 0], + pkt_cnt->pkt_cnt_vht[ss_ofst + 1], + pkt_cnt->pkt_cnt_vht[ss_ofst + 2], + pkt_cnt->pkt_cnt_vht[ss_ofst + 3], + pkt_cnt->pkt_cnt_vht[ss_ofst + 4], + pkt_cnt->pkt_cnt_vht[ss_ofst + 5], + pkt_cnt->pkt_cnt_vht[ss_ofst + 6], + pkt_cnt->pkt_cnt_vht[ss_ofst + 7], + pkt_cnt->pkt_cnt_vht[ss_ofst + 8], + pkt_cnt->pkt_cnt_vht[ss_ofst + 9], + pkt_cnt->pkt_cnt_vht[ss_ofst + 10], + pkt_cnt->pkt_cnt_vht[ss_ofst + 11]); + } + + /*@======HE==========================================================*/ + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "* HE-%d ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_he[ss_ofst + 0], + pkt_cnt->pkt_cnt_he[ss_ofst + 1], + pkt_cnt->pkt_cnt_he[ss_ofst + 2], + pkt_cnt->pkt_cnt_he[ss_ofst + 3], + pkt_cnt->pkt_cnt_he[ss_ofst + 4], + pkt_cnt->pkt_cnt_he[ss_ofst + 5], + pkt_cnt->pkt_cnt_he[ss_ofst + 6], + pkt_cnt->pkt_cnt_he[ss_ofst + 7], + pkt_cnt->pkt_cnt_he[ss_ofst + 8], + pkt_cnt->pkt_cnt_he[ss_ofst + 9], + pkt_cnt->pkt_cnt_he[ss_ofst + 10], + pkt_cnt->pkt_cnt_he[ss_ofst + 11]); + } + /*@======SC_BW========================================================*/ + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "*[Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc20[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]); + } + + for (i = 0; i < rate_num; i++) { + ss_ofst = 12 * i; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "*[Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + pkt_cnt->pkt_cnt_sc40[ss_ofst + 0], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 1], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 2], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 3], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 4], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 5], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 6], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 7], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 8], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 9], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 10], + pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]); + } +} + +u16 halbb_rx_utility(struct bb_info *bb, u16 avg_phy_rate, u8 rx_max_ss, + enum channel_width bw) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + u16 utility_primitive = 0, utility = 0; + + if (pkt_cnt->he_pkt_not_zero) { + /*@ HE 1SS MCS11[3.2] 20M: tp = 122, 1000/122 = 8.2, 122*8.25 = 1006.5*/ + utility_primitive = avg_phy_rate * 8 + (avg_phy_rate >> 2); + } else if (pkt_cnt->vht_pkt_not_zero) { + /*@ VHT 1SS MCS9(fake) 20M: tp = 87, 1000/87 = 11.49, 87*11.5 = 1000.5*/ + utility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 1); + } else if (pkt_cnt->ht_pkt_not_zero) { + /*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/ + utility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1); + } else { + /*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/ + utility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1); + } + + utility = (utility_primitive / rx_max_ss) >> bw; + + if (utility > 1000) + utility = 1000; + + return utility; +} + +u16 halbb_rx_avg_phy_rate(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + u16 i = 0; + u8 base = LEGACY_RATE_NUM; + u16 rate = 0; + u32 pkt_cnt_tmp = 0, phy_rate_sum = 0; + enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw; + + //BB_DBG(bb, DBG_CMN, "bw=%d\n", bb->hal_com->band[0].cur_chandef.bw); + + if (pkt_cnt->he_pkt_not_zero) { + /*HE Mode*/ + for (i = 0; i < HE_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_he[i] == 0) + continue; + rate = VHT_2_HE32_RATE(bb_phy_rate_table[i + base] << bw); + phy_rate_sum += pkt_cnt->pkt_cnt_he[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_he[i]; + + //BB_DBG(bb, DBG_CMN, "HE sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_he[i], rate, i + base, pkt_cnt_tmp); + } + } else if (pkt_cnt->vht_pkt_not_zero) { + /*VHT Mode*/ + for (i = 0; i < VHT_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_vht[i] == 0) + continue; + rate = bb_phy_rate_table[i + base] << bw; + phy_rate_sum += pkt_cnt->pkt_cnt_vht[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_vht[i]; + + //BB_DBG(bb, DBG_CMN, "VHT sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_vht[i], rate, i + base, pkt_cnt_tmp); + } + + } else if (pkt_cnt->ht_pkt_not_zero) { + /*HT Mode*/ + for (i = 0; i < HT_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_ht[i] == 0) + continue; + rate = bb_phy_rate_table[i + base] << bw; + phy_rate_sum += pkt_cnt->pkt_cnt_ht[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_ht[i]; + + //BB_DBG(bb, DBG_CMN, "HT sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_ht[i], rate, i + base, pkt_cnt_tmp); + } + + } else { + /*Legacy mode*/ + for (i = BB_01M; i <= BB_54M; i++) { + /*SKIP beacon*/ + if (i == cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate) + continue; + + if (pkt_cnt->pkt_cnt_legacy[i] == 0) + continue; + + rate = bb_phy_rate_table[i]; + phy_rate_sum += pkt_cnt->pkt_cnt_legacy[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_legacy[i]; + + //BB_DBG(bb, DBG_CMN, "LAG sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_legacy[i], rate, i + base, pkt_cnt_tmp); + } + } + + /*SC Data*/ + if (pkt_cnt->sc40_occur) { + for (i = 0; i < LOW_BW_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_sc40[i] == 0) + continue; + rate = bb_phy_rate_table[i + base] << CHANNEL_WIDTH_40; + phy_rate_sum += pkt_cnt->pkt_cnt_sc40[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_sc40[i]; + } + } + + if (pkt_cnt->sc20_occur) { + for (i = 0; i < LOW_BW_RATE_NUM; i++) { + if (pkt_cnt->pkt_cnt_sc20[i] == 0) + continue; + rate = bb_phy_rate_table[i + base]; + phy_rate_sum += pkt_cnt->pkt_cnt_sc20[i] * rate; + pkt_cnt_tmp += pkt_cnt->pkt_cnt_sc20[i]; + } + } + //BB_DBG(bb, DBG_CMN, "sum=%d, cnt=%d\n", phy_rate_sum, pkt_cnt_tmp); + return (u16)HALBB_DIV(phy_rate_sum, pkt_cnt_tmp); /*avg_phy_rate*/ +} + +void halbb_basic_dbg_msg_mac_phy_intf(struct bb_info *bb) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + s32 pw = 0; + //u8 i = 0, usr_ofst = 0; + u32 tmp_32 = 0; + u32 tx_pw = 0, l_sig = 0, sig_a1 = 0, sig_a2 = 0; + u8 txpath_en =0, type = 0, mcs = 0; + char ppdu[][10] = {{"L-CCK"}, {"S-CCK"}, {"Legacy"}, {"HT"}, + {"HT GF"}, {"VHT SU"}, {"VHT MU"}, {"HE SU"}, + {"HE ER SU"}, {"HE MU"}, {"HE TB"}}; + char gi_type[][4] = {{"0.4"}, {"0.8"}, {"1.6"}, {"3.2"}}; + char fec_type[][5] = {{"BCC"}, {"LDPC"}}; + char *txcmd = NULL; + u8 txcmd2 = 0; + bool no_txcmd_hit = false; + + if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) + return; + + txpath_en = (u8)halbb_get_reg(bb, cr->mac_phy_txpath_en, 0xF000); + l_sig = halbb_get_reg(bb, cr->mac_phy_lsig, MASKDWORD); + tx_pw = halbb_get_reg(bb, cr->mac_phy_tx_pw, 0x7FC0000); + + if ((txpath_en == 0) && (l_sig == 0) && (tx_pw == 0)) { + BB_DBG(bb, DBG_CMN, + "[MAC/PHY Intf]Txinfo is empty!BB reset has been probably toggled.\n"); + return; + } + + type = (u8)halbb_get_reg(bb, cr->mac_phy_ppdu_type, 0xf); + mcs = (u8)(halbb_get_reg(bb, cr->mac_phy_mcs_3_0, 0xf0000000) + + (halbb_get_reg(bb, cr->mac_phy_mcs_5_4, 0x3) << 4)); + + halbb_print_sign_frac_digit(bb, tx_pw, 9, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE); + + tmp_32 = halbb_get_reg(bb, cr->mac_phy_txcmd, 0x3f000000); + switch (tmp_32) { + case 0: + txcmd = "data"; + break; + case 1: + txcmd = "beacon"; + break; + case 2: + txcmd = "HT-NDPA"; + break; + case 3: + txcmd = "VHT-NDPA"; + break; + case 4: + txcmd = "HE-NDPA"; + break; + case 8: + txcmd = "RTS"; + break; + case 9: + txcmd = "CTS2self"; + break; + case 10: + txcmd = "CF_end"; + break; + case 11: + txcmd = "compressed-BAR"; + break; + case 12: + txcmd = "BFRP"; + break; + case 13: + txcmd = "NDP"; + break; + case 14: + txcmd = "QoS_Null"; + break; + case 16: + txcmd = "ACK"; + break; + case 17: + txcmd = "CTS"; + break; + case 18: + txcmd = "compressed-BA"; + break; + case 19: + txcmd = "Multi-STA-BA"; + break; + case 20: + txcmd = "HT-CSI"; + break; + case 21: + txcmd = "VHT-CSI"; + break; + case 22: + txcmd = "HE-CSI"; + break; + case 31: + txcmd = "TB_PPDU"; + break; + case 32: + txcmd = "TRIG-BASIC"; + break; + case 33: + txcmd = "TRIG-BFRP"; + break; + case 34: + txcmd = "TRIG-MUBAR"; + break; + case 35: + txcmd = "TRIG-MU-RTS"; + break; + case 36: + txcmd = "TRIG-BSRP"; + break; + case 37: + txcmd = "TRIG-BQRP"; + break; + case 38: + txcmd = "TRIG-NFRP"; + break; + case 48: + txcmd = "TRIG-BASIC-DATA"; + break; + default: + txcmd = "RSVD"; + txcmd2 = (u8)tmp_32; + no_txcmd_hit = true; + break; + } + + if (no_txcmd_hit) + BB_DBG(bb, DBG_CMN, + "[MAC/PHY Intf][%s][RSVD-%d] BW=%dM, TxSC=%d, TxPw=%s dBm, TxPathEn=%d\n", + ppdu[type], txcmd2, + 20 << (halbb_get_reg(bb, cr->mac_phy_bw, 0x30000)), + halbb_get_reg(bb, cr->mac_phy_txsc, 0xf0), + bb->dbg_buf, txpath_en); + else + BB_DBG(bb, DBG_CMN, + "[MAC/PHY Intf][%s][%s] BW=%dM, TxSC=%d, TxPw=%s dBm, TxPathEn=%d\n", + ppdu[type], txcmd, + 20 << (halbb_get_reg(bb, cr->mac_phy_bw, 0x30000)), + halbb_get_reg(bb, cr->mac_phy_txsc, 0xf0), + bb->dbg_buf, txpath_en); + + BB_DBG(bb, DBG_CMN, + "User_num=%d, STBC=%d, FEC=%s, GILTF=%dx%s, NDP_en=%d, N_sts=%d, MCS=%d\n", + halbb_get_reg(bb, cr->mac_phy_n_usr, 0xff0), + halbb_get_reg(bb, cr->mac_phy_stbc, BIT(0)), + fec_type[halbb_get_reg(bb, cr->mac_phy_fec, BIT(27))], + 1 << halbb_get_reg(bb, cr->mac_phy_ltf, 0xC0), + gi_type[halbb_get_reg(bb, cr->mac_phy_gi, 0x30)], + halbb_get_reg(bb, cr->mac_phy_ndp_en, BIT(4)), + halbb_get_reg(bb, cr->mac_phy_n_sts, 0x7000000), mcs); + + /*SIG*/ + tmp_32 = halbb_get_reg(bb, cr->mac_phy_siga_0, MASKDWORD); + if (type > 6) { // === HE === // + sig_a1 = tmp_32 & 0x3ffffff; + sig_a2 = (halbb_get_reg(bb, cr->mac_phy_siga_1, 0xfffff) << 6) | + ((tmp_32 & 0xfc000000) >> 26); + } else if (type > 2) { // === HT / VHT === // + sig_a1 = tmp_32 & 0xffffff; + sig_a2 = (halbb_get_reg(bb, cr->mac_phy_siga_1, 0xffff) << 8) | + ((tmp_32 & 0xff000000) >> 24); + } + BB_DBG(bb, DBG_CMN, "SIG-L/A1/A2= {0x%08x, 0x%08x, 0x%08x}\n", l_sig, sig_a1, + sig_a2); +#if 0 + BB_DBG(bb, DBG_CMN, "============ [User-specified Info] ============\n"); + for (i = 0; i < n_user; i++) { + BB_DBG(bb, DBG_CMN, "------------- [User-%d] -------------\n", i); + usr_ofst = i << 3; + /* FEC */ + txinfo_value = halbb_get_reg(bb, 0x4718 + usr_ofst, BIT(27)); + BB_DBG(bb, DBG_CMN, "FEC: %s\n", fec_type[txinfo_value]); + /* MCS */ + txinfo_value = (halbb_get_reg(bb, 0x471c + usr_ofst, BIT(1) | + BIT(0)) << 4) + halbb_get_reg(bb, 0x4718 + + usr_ofst, + 0xf0000000); + BB_DBG(bb, DBG_CMN, "MCS: %d\n", txinfo_value); + /* DCM */ + txinfo_value = halbb_get_reg(bb, 0x471c + usr_ofst, BIT(2)); + BB_DBG(bb, DBG_CMN, "DCM En: %d\n", txinfo_value); + /* TxBF */ + txinfo_value = halbb_get_reg(bb, 0x471c + usr_ofst, BIT(14)); + BB_DBG(bb, DBG_CMN, "TxBF En: %d\n", txinfo_value); + } +#endif + +} + +void halbb_basic_dbg_msg_pmac(struct bb_info *bb) +{ + +#ifdef HALBB_STATISTICS_SUPPORT + struct bb_stat_info *stat = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat->bb_fa_i; + struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i; + struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i; + struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i; + struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i; + struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i; + struct bb_cca_info *cca = &stat->bb_cca_i; + struct bb_crc_info *crc = &stat->bb_crc_i; + //struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + + if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) + return; + + BB_DBG(bb, DBG_CMN, + "[Tx]{CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON}: {%d, %d, %d, %d}\n", + stat->bb_tx_cnt_i.cck_mac_txen, stat->bb_tx_cnt_i.cck_phy_txon, + stat->bb_tx_cnt_i.ofdm_mac_txen, + stat->bb_tx_cnt_i.ofdm_phy_txon); + BB_DBG(bb, DBG_CMN, + "[CRC]{B/G/N/AC/AX/All/MPDU} OK:{%d, %d, %d, %d, %d, %d, %d} Err:{%d, %d, %d, %d, %d, %d, %d}\n", + crc->cnt_cck_crc32_ok, crc->cnt_ofdm_crc32_ok, + crc->cnt_ht_crc32_ok, crc->cnt_vht_crc32_ok, + crc->cnt_he_crc32_ok, crc->cnt_crc32_ok_all, + crc->cnt_ampdu_crc_ok, crc->cnt_cck_crc32_error, + crc->cnt_ofdm_crc32_error, crc->cnt_ht_crc32_error, + crc->cnt_vht_crc32_error, crc->cnt_he_crc32_error, + crc->cnt_crc32_error_all, crc->cnt_ampdu_crc_error); + BB_DBG(bb, DBG_CMN, + "[CCA]{CCK, OFDM, All}: %d, %d, %d\n", + cca->cnt_cck_cca, cca->cnt_ofdm_cca, cca->cnt_cca_all); + BB_DBG(bb, DBG_CMN, + "[FA]{CCK, OFDM, All}: %d, %d, %d\n", + fa->cnt_cck_fail, fa->cnt_ofdm_fail, fa->cnt_fail_all); + BB_DBG(bb, DBG_CMN, + " *[CCK]sfd/sig_GG=%d/%d, *[OFDM]Prty=%d, Rate=%d, LSIG_brk_s/l=%d/%d, SBD=%d\n", + cck_fa->sfd_gg_cnt, cck_fa->sig_gg_cnt, + legacy_fa->cnt_parity_fail, legacy_fa->cnt_rate_illegal, + legacy_fa->cnt_lsig_brk_s_th, legacy_fa->cnt_lsig_brk_l_th, + legacy_fa->cnt_sb_search_fail); + BB_DBG(bb, DBG_CMN, + " *[HT]CRC8=%d, MCS=%d, *[VHT]SIGA_CRC8=%d, MCS=%d\n", + ht_fa->cnt_crc8_fail, ht_fa->cnt_mcs_fail, + vht_fa->cnt_crc8_fail_vhta, vht_fa->cnt_mcs_fail_vht); + BB_DBG(bb, DBG_CMN, + " *[HE]SIGA_CRC4{SU/ERSU/MU}=%d/%d/%d, SIGB_CRC4{ch1/ch2}=%d/%d, MCS{nrml/bcc/dcm}=%d/%d/%d\n", + he_fa->cnt_crc4_fail_hea_su, he_fa->cnt_crc4_fail_hea_ersu, + he_fa->cnt_crc4_fail_hea_mu, he_fa->cnt_crc4_fail_heb_ch1_mu, + he_fa->cnt_crc4_fail_heb_ch2_mu, he_fa->cnt_mcs_fail_he, + he_fa->cnt_mcs_fail_he_bcc, he_fa->cnt_mcs_fail_he_dcm); +#endif +} + +void halbb_basic_dbg_msg_rx_info(struct bb_info *bb) +{ + struct bb_ch_info *ch = &bb->bb_ch_i; +#ifdef HALBB_CFO_TRK_SUPPORT + struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; +#endif + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_cap_info *pkt_cnt_cap = &cmn_rpt->bb_pkt_cnt_all_i; + struct bb_physts_pop_info *pop_info = &cmn_rpt->bb_physts_pop_i; + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + u8 tmp = 0; + u32 bb_monitor1 = 0; + + if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) + return; + + BB_DBG(bb, DBG_CMN, "rxsc_idx {Lgcy, 20, 40, 80} = {%d, %d, %d, %d}\n", + ch->rxsc_l, ch->rxsc_20, ch->rxsc_40, ch->rxsc_80); + BB_DBG(bb, DBG_CMN, "RX Pkt Cnt: LDPC=(%d), BCC=(%d), STBC=(%d), SU_BF=(%d), MU_BF=(%d), \n", + pkt_cnt_cap->pkt_cnt_ldpc, pkt_cnt_cap->pkt_cnt_bcc, + pkt_cnt_cap->pkt_cnt_stbc, pkt_cnt_cap->pkt_cnt_subf, + pkt_cnt_cap->pkt_cnt_mubf); +#ifdef HALBB_CFO_TRK_SUPPORT + halbb_print_sign_frac_digit(bb, cfo_trk->cfo_avg_pre, 16, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE); + + BB_DBG(bb, DBG_CMN, "CFO[T-1]=(%s kHz), cryst_cap=(%s%d), cfo_ofst=%d\n", + bb->dbg_buf, + ((cfo_trk->crystal_cap > cfo_trk->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_trk->crystal_cap, cfo_trk->def_x_cap), + cfo_trk->x_cap_ofst); +#endif + BB_DBG(bb, DBG_CMN, "Dly_sprd=(%d)\n", tmp); + BB_DBG(bb, DBG_CMN, + "[POP] cnt=%d, hist_cck/ofdm[0:3]={%d | %d, %d, %d}/{%d | %d, %d, %d}\n", + bb->bb_stat_i.bb_cca_i.pop_cnt, + pop_info->pop_hist_cck[0], pop_info->pop_hist_cck[1], + pop_info->pop_hist_cck[2], pop_info->pop_hist_cck[3], + pop_info->pop_hist_ofdm[0], pop_info->pop_hist_ofdm[1], + pop_info->pop_hist_ofdm[2], pop_info->pop_hist_ofdm[3]); + + halbb_set_reg(bb, cr->bb_monitor_sel1, cr->bb_monitor_sel1_m, 1); + bb_monitor1 = halbb_get_reg(bb, cr->bb_monitor1, cr->bb_monitor1_m); + BB_DBG(bb, DBG_CMN, "BB monitor1 = (0x%x)\n", bb_monitor1); +} + +void halbb_basic_dbg_msg_tx_info(struct bb_info *bb) +{ + struct bb_ch_info *ch = &bb->bb_ch_i; + struct rtw_phl_stainfo_t *sta; + struct rtw_ra_sta_info *ra; + //char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + u16 sta_cnt = 0; + u8 i = 0; + u8 tmp = 0; + u16 curr_tx_rt = 0; + enum rtw_gi_ltf curr_gi_ltf = RTW_GILTF_LGI_4XHE32; + enum hal_rate_bw curr_bw = HAL_RATE_BW_20; + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!bb->sta_exist[i]) + continue; + sta = bb->phl_sta_info[i]; + if (!is_sta_active(sta)) + continue; + + ra = &sta->hal_sta->ra_info; + curr_tx_rt = (u16)(ra->rpt_rt_i.mcs_ss_idx) | ((u16)(ra->rpt_rt_i.mode) << 7); + curr_gi_ltf = ra->rpt_rt_i.gi_ltf; + curr_bw = ra->rpt_rt_i.bw; + + halbb_print_rate_2_buff(bb, curr_tx_rt, curr_gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "TxRate[%d]=%s (0x%x-%d), PER=(%d), TXBW=(%d)\n", + i, bb->dbg_buf, curr_tx_rt, curr_gi_ltf, + ra->curr_retry_ratio, (20<= bb->hal_com->assoc_sta_cnt) + break; + } + //BB_DBG(bb, DBG_CMN, "TSSI val=(%d)\n", tmp); + //BB_DBG(bb, DBG_CMN, "EDCA val=(%d)\n", tmp); +} + +void halbb_basic_dbg_msg_physts_mu(struct bb_info *bb) +{ + struct bb_ch_info *ch = &bb->bb_ch_i; + struct bb_link_info *link = &bb->bb_link_i; + + if (bb->bb_cmn_rpt_i.bb_pkt_cnt_mu_i.pkt_cnt_all == 0) { + BB_DBG(bb, DBG_CMN, "NO MU pkt\n"); + return; + } + + /*RX Rate*/ + halbb_print_rate_2_buff(bb, link->rx_rate_plurality_mu, + RTW_GILTF_LGI_4XHE32, bb->dbg_buf, 32); + + BB_DBG(bb, DBG_CMN, "Plurality_RxRate:%s (0x%x)\n", + bb->dbg_buf, link->rx_rate_plurality); + + /*RX Rate Distribution & RSSI*/ + halbb_show_rssi_and_rate_distribution_mu(bb); +} + +void halbb_basic_dbg_msg_physts_su(struct bb_info *bb) +{ + struct bb_ch_info *ch = &bb->bb_ch_i; + struct bb_link_info *link = &bb->bb_link_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + //struct rtw_phl_stainfo_t *sta; + //char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + char dbg_buf2[32] = {0}; + u16 avg_phy_rate = 0, utility = 0; + + /*RX Rate*/ + halbb_print_rate_2_buff(bb, link->rx_rate_plurality, + RTW_GILTF_LGI_4XHE32, dbg_buf2, 32); + + halbb_print_rate_2_buff(bb, cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate, + RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_CMN, "Plurality_RxRate:%s (0x%x), Bcn_Rate=%s (0x%x), Bcn_cnt=%d\n", + dbg_buf2, link->rx_rate_plurality, + bb->dbg_buf ,cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate, + cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon); + + /*RX Rate Distribution & RSSI*/ + halbb_show_rssi_and_rate_distribution_su(bb); + + /*RX Utility*/ + avg_phy_rate = halbb_rx_avg_phy_rate(bb); + utility = halbb_rx_utility(bb, avg_phy_rate, bb->num_rf_path, bb->hal_com->band[0].cur_chandef.bw); + + BB_DBG(bb, DBG_CMN, "Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n", + avg_phy_rate, utility); +} + +void halbb_basic_dbg_message(struct bb_info *bb) +{ + struct bb_link_info *link = &bb->bb_link_i; + struct bb_ch_info *ch = &bb->bb_ch_i; + struct bb_dbg_info *dbg = &bb->bb_dbg_i; + struct bb_physts_info *physts = &bb->bb_physts_i; + enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw; + u8 fc = bb->hal_com->band[0].cur_chandef.center_ch; + u8 sta_cnt = 0; + u8 i; + +#ifdef HALBB_DBG_TRACE_SUPPORT + if (!(bb->dbg_component & DBG_CMN)) + return; + + if (bb->cmn_dbg_msg_cnt >= bb->cmn_dbg_msg_period) { /*unit: Sec*/ + bb->cmn_dbg_msg_cnt = HALBB_WATCHDOG_PERIOD; + } else { + bb->cmn_dbg_msg_cnt += HALBB_WATCHDOG_PERIOD; + return; + } +#endif + + BB_DBG(bb, DBG_CMN, "[%s]%s %s\n", __func__, HLABB_CODE_BASE, HALBB_RELEASE_DATE); + BB_DBG(bb, DBG_CMN, "====[1. System] (%08d sec) (Ability=0x%08llx)\n", + bb->bb_sys_up_time, bb->support_ability); + BB_DBG(bb, DBG_CMN, "[%s mode], TP{T,R,ALL}={%d, %d, %d}, BW:%d, CH_fc:%d\n", + ((bb->bb_watchdog_mode == BB_WATCHDOG_NORMAL) ? "Normal" : + ((bb->bb_watchdog_mode == BB_WATCHDOG_LOW_IO) ? "LowIO" : "NonIO")), + link->tx_tp, link->rx_tp, link->total_tp, 20 << bw, fc); + BB_DBG(bb, DBG_CMN, + "Phy:%d, linked: %d, Num_sta: %d, rssi_max/min= {%02d.%d, %02d.%d}, Noisy:%d\n", + bb->bb_phy_idx, + link->is_linked, bb->hal_com->assoc_sta_cnt, + ch->rssi_max >> 1, (ch->rssi_max & 1) * 5, + ch->rssi_min >> 1, (ch->rssi_min & 1) * 5, + ch->is_noisy); + BB_DBG(bb, DBG_CMN, "physts_cnt{all, 2_self, err_len, ok_ie, err_ie}={%d,%d,%d,%d,%d}\n", + physts->bb_physts_cnt_i.all_cnt, physts->bb_physts_cnt_i.is_2_self_cnt, + physts->bb_physts_cnt_i.ok_ie_cnt, physts->bb_physts_cnt_i.err_ie_cnt, + physts->bb_physts_cnt_i.err_len_cnt); + + for (i = 0; i< PHL_MAX_STA_NUM; i++) { + BB_DBG(bb, DBG_CMN, "[%d] Linked macid=%d\n", + i, bb->sta_exist[i]); + + sta_cnt++; + if (sta_cnt >= bb->hal_com->assoc_sta_cnt) + break; + } + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[2. ENV Mntr]\n"); + halbb_env_mntr_log(bb, DBG_CMN); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[3. PMAC]\n"); + halbb_basic_dbg_msg_pmac(bb); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[4. TX General]\n"); + halbb_basic_dbg_msg_mac_phy_intf(bb); + + if (bb->bb_link_i.is_linked) { + halbb_basic_dbg_msg_tx_info(bb); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[5. RX General]\n"); + halbb_basic_dbg_msg_rx_info(bb); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[6. AVG RSSI/RxRate]\n"); + halbb_basic_dbg_msg_physts_su(bb); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[7. BB Hist]\n"); + halbb_show_phy_hitogram_su(bb); + BB_DBG(bb, DBG_CMN, "\n"); + BB_DBG(bb, DBG_CMN, "====[8. [MU] AVG RSSI/RxRate]\n"); + halbb_basic_dbg_msg_physts_mu(bb); + } + BB_DBG(bb, DBG_CMN, "============================================\n"); + BB_DBG(bb, DBG_CMN, "\n"); +} + +void halbb_dm_summary(struct bb_info *bb, u8 macid) +{ +} + +#endif +void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len) +{ + char *cv = NULL; + char *ic_type = NULL; + char *support = NULL; + u32 used = *_used; + u32 out_len = *_out_len; + u32 date = 0; + u32 release_ver = 0; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n", + "% [Basic Info] %"); + + switch (bb->ic_type) { + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + ic_type = "RTL8852A(Acut)"; + date = BB_REG_RELEASE_DATE_8852A; + release_ver = BB_REG_RELEASE_VERSION_8852A; + break; + #endif + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + ic_type = "RTL8852A(>Bcut)"; + date = BB_REG_RELEASE_DATE_8852A_2; + release_ver = BB_REG_RELEASE_VERSION_8852A_2; + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + ic_type = "RTL8852B"; + date = BB_REG_RELEASE_DATE_8852B; + release_ver = BB_REG_RELEASE_VERSION_8852B; + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + ic_type = "RTL8852C"; + date = BB_REG_RELEASE_DATE_8852C; + release_ver = BB_REG_RELEASE_VERSION_8852C; + break; + #endif + default: + BB_WARNING("[%s]\n", __func__); + break; + } + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "IC", ic_type); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + " %-25s: %s \n", "Normal Mode", + (bb->phl_com->drv_mode == RTW_DRV_MODE_NORMAL)? "Y" : "N"); + + if (bb->hal_com->cv == CAV) + cv = "CAV"; + else if (bb->hal_com->cv == CBV) + cv = "CBV"; + else if (bb->hal_com->cv == CCV) + cv = "CCV"; + else if (bb->hal_com->cv == CDV) + cv = "CDV"; + else if (bb->hal_com->cv == CEV) + cv = "CEV"; + else + cv = "NA"; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %d\n", + "RFE", bb->phl_com->dev_cap.rfe_type); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %d\n", + "PKG", bb->phl_com->dev_cap.pkg_type); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "CV", cv); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + " %-25s: %d.%d\n", "FW Ver", bb->u8_dummy, + bb->u8_dummy); /*TBD*/ + + /*[HALBB Info]*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n", + "% [HALBB Info] %"); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s (%s)\n", + "Branch", HLABB_CODE_BASE, HALBB_RELEASE_DATE); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %02d (%d)\n", + "BB CR Ver", release_ver, date); + /*Feature Compile List*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n", + "% [Support List] %"); + + #ifdef HALBB_DBG_TRACE_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "DBG_TRACE", support); + + #ifdef HALBB_TIMER_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "TIMER", support); + + #ifdef HALBB_PHYSTS_PARSING_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "PHYSTS", support); + #ifdef HALBB_ENV_MNTR_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "ENV_MNTR", support); + #ifdef HALBB_STATISTICS_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "STATISTICS", support); + #ifdef HALBB_RA_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "RA", support); + #ifdef HALBB_EDCCA_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "EDCCA", support); + #ifdef HALBB_CFO_TRK_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "CFO_TRK", support); + #ifdef HALBB_LA_MODE_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "LA_MODE", support); + #ifdef HALBB_PSD_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "PSD", support); + #ifdef HALBB_PWR_CTRL_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "PWR_CTRL", support); + #ifdef HALBB_RUA_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "RUA", support); + #ifdef HALBB_PMAC_TX_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "PMAC_TX", support); + #ifdef HALBB_CH_INFO_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "CH_INFO", support); + #ifdef HALBB_AUTO_DBG_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "AUTO_DBG", support); + #ifdef HALBB_ANT_DIV_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "ANT_DIV", support); + #ifdef HALBB_DBCC_SUPPORT + support = "Y"; + #else + support = "."; + #endif + BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n", + "DBCC", support); + + *_used = used; + *_out_len = out_len; +} + +#if HALBB_DBG_DVLP_FLAG /*Dump register - relative*/ + +void halbb_cr_table_dump(struct bb_info *bb, u32 *cr_table, u32 cr_len) +{ + u8 i = 0; + u32 cr_tmp, val; + + for (i = 0; i < cr_len; i++) { + cr_tmp = cr_table[i]; + if (cr_tmp == 0) + continue; + + val = halbb_get_reg(bb, cr_tmp, MASKDWORD); + BB_TRACE("[%03d]Reg[0x%04x] = 0x%08x\n", i, cr_tmp, val); + } +} + +void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len, bool dump_2_buff) +{ + if (dump_2_buff) { + if (*_out_len < 100) { + BB_WARNING("[%s] out_len=%d", __func__, *_out_len); + return; + } + } + + switch (bb->ic_type) { + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_dump_bb_reg_8852a(bb, _used, output, _out_len); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_dump_bb_reg_8852a_2(bb, _used, output, _out_len, dump_2_buff); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_dump_bb_reg_8852b(bb, _used, output, _out_len, dump_2_buff); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_dump_bb_reg_8852c(bb, _used, output, _out_len, dump_2_buff); + break; + #endif + + default: + break; + } +} + +void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + char help[] = "-h"; + u32 val[10] = {0}; + u32 addr = 0; + + if (input[1]) + HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]); + + if (_os_strcmp(input[1], help) == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dumpreg 0\n"); + } else { + halbb_dump_bb_reg(bb, _used, output, _out_len, true); + } +} + +void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]); + + if (_os_strcmp(input[1], help) == 0) { + BB_DBG_CNSL(out_len, *_used, output + *_used, out_len - *_used, + "{dd_dbg}\n"); + return; + } + /*[Reg]*/ + halbb_dump_bb_reg(bb, &used, output, &out_len, true); + /*[Dbg Port]*/ + halbb_dbgport_dump_all(bb, _used, output, _out_len); + /*[Analog Parameters]*/ + //halbb_get_anapar_table(bb, &used, output, &out_len); + +} +#endif + +void halbb_show_rx_rate(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_HEX, &val[0]); + + if (val[0] == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[SU RX Rate]\n"); + halbb_rx_rate_distribution_su_cnsl(bb, _used, output, _out_len); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[MU RX Rate]\n"); + } +} + +void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 cr = 0; + bool rpt = true; + enum phl_phy_idx phy_idx; + struct rtw_para_info_t *reg = NULL; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{cr_rec, cr_rec_rf} {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "wd {0:Normal/1:LowIo/2:NonIO}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "event {phl_evt_id}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "period {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "init {cr, gain} {phy_idx}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "init dbg_mode {en} {rfe} {cv}\n"); + + } else if (_os_strcmp(input[1], "event") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + halbb_wifi_event_notify(bb, (enum phl_msg_evt_id)val[0], bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "phl_evt_id=%d\n", val[0]); + } else if (_os_strcmp(input[1], "period") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + bb->bb_watchdog_period = (u8)(val[0] & 0xfe); + if (bb->bb_watchdog_period < 2) + bb->bb_watchdog_period = 2; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "wd_period=%d\n", bb->bb_watchdog_period); + } else if (_os_strcmp(input[1], "cr_rec") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + bb->bb_dbg_i.cr_recorder_en = (bool)val[0]; + } else if (_os_strcmp(input[1], "cr_rec_rf") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + bb->bb_dbg_i.cr_recorder_rf_en = (bool)val[0]; + } else if (_os_strcmp(input[1], "wd") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + halbb_watchdog(bb, (enum bb_watchdog_mode_t)val[0], bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Watchdog trigger, mode=%d\n", val[0]); + } else if (_os_strcmp(input[1], "init") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + + if (_os_strcmp(input[2], "cr") == 0) { + phy_idx = (enum phl_phy_idx)val[0]; + reg = &bb->phl_com->phy_sw_cap[phy_idx].bb_phy_reg_info; + rpt = halbb_init_cr_default(bb, false, 0, &val[0], phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "CR init Success=%d\n", rpt); + } else if (_os_strcmp(input[2], "gain") == 0) { + phy_idx = (enum phl_phy_idx)val[0]; + reg = &bb->phl_com->phy_sw_cap[phy_idx].bb_phy_reg_gain_info; + rpt = halbb_init_gain_table(bb, false, 0, &val[0], phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Gain init Success=%d\n", rpt); + } else if (_os_strcmp(input[2], "dbg_mode") == 0) { + bb->bb_dbg_i.cr_dbg_mode_en = (bool)val[0]; + bb->bb_dbg_i.rfe_type_curr_dbg = val[1]; + bb->bb_dbg_i.cut_curr_dbg = val[2]; + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Err\n"); + return; + } + } else if (_os_strcmp(input[1], "1") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + bb->hal_com->assoc_sta_cnt = (u8)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "assoc_sta_cnt=%d\n", bb->hal_com->assoc_sta_cnt); + } else if (_os_strcmp(input[1], "cr_demo") == 0) { + cr = halbb_get_reg(bb, LA_CLK_EN, LA_CLK_EN_M); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Old] cr = %d\n", cr); + + HALBB_SET_CR(bb, LA_CLK_EN, ~cr); + cr = HALBB_GET_CR(bb, LA_CLK_EN); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[New] ~cr = %d\n", cr); + + HALBB_SET_CR(bb, LA_CLK_EN, ~cr); + cr = HALBB_GET_CR(bb, LA_CLK_EN); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[New] cr = %d\n", cr); + } +} + + +void halbb_dbg_setting_init(struct bb_info *bb) +{ + halbb_cmd_parser_init(bb); + bb->fw_dbg_component = 0; + bb->cmn_dbg_msg_cnt = HALBB_WATCHDOG_PERIOD; + bb->cmn_dbg_msg_period = HALBB_WATCHDOG_PERIOD; + halbb_bb_dbg_port_clock_en(bb, true); + + bb->bb_dbg_i.cr_recorder_en = false; + bb->bb_dbg_i.cr_dbg_mode_en = false; +} + +void halbb_cr_cfg_dbg_init(struct bb_info *bb) +{ + struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_52AA_SERIES + case BB_52AA: + cr->dbgport_ip = 0x09F4; + cr->dbgport_ip_m = 0xff; + cr->dbgport_idx = 0x09F0; + cr->dbgport_idx_m = MASKLWORD; + cr->dbgport_val = 0x40B0; + cr->dbgport_val_m = MASKDWORD; + cr->clk_en = 0x09F4; + cr->clk_en_m = BIT(24); + cr->dbgport_en = 0x09F8; + cr->dbgport_en_m = BIT(31); + break; + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->dbgport_ip = DBG_PORT_IP_SEL_A; + cr->dbgport_ip_m = DBG_PORT_IP_SEL_A_M; + cr->dbgport_idx = DBG_PORT_SEL_A; + cr->dbgport_idx_m = DBG_PORT_SEL_A_M; + cr->dbgport_val = DBG32_D_A; + cr->dbgport_val_m = DBG32_D_A_M; + cr->clk_en = DBG_PORT_REF_CLK_EN_A; + cr->clk_en_m = DBG_PORT_REF_CLK_EN_A_M; + cr->dbgport_en = DBG_PORT_EN_A; + cr->dbgport_en_m = DBG_PORT_EN_A_M; + cr->bb_monitor_sel1 = MONITOR_SEL1_A; + cr->bb_monitor_sel1_m = MONITOR_SEL1_A_M; + cr->bb_monitor1 = 0x1b14; + cr->bb_monitor1_m = MASKDWORD; + /*mac_phy_intf*/ + cr->mac_phy_ppdu_type = 0x1800; + cr->mac_phy_txpath_en = 0x1800; + cr->mac_phy_txcmd = 0x1800; + cr->mac_phy_txsc = 0x1804; + cr->mac_phy_bw = 0x1804; + cr->mac_phy_tx_pw = 0x1804; + cr->mac_phy_n_usr = 0x1808; + cr->mac_phy_stbc = 0x1810; + cr->mac_phy_gi = 0x1810; + cr->mac_phy_ltf = 0x1810; + cr->mac_phy_ndp_en = 0x1814; + cr->mac_phy_n_sts = 0x1818; + cr->mac_phy_fec = 0x1818; + cr->mac_phy_mcs_3_0 = 0x1818; + cr->mac_phy_mcs_5_4 = 0x181c; + cr->mac_phy_lsig = 0x1840; + cr->mac_phy_siga_0 = 0x1848; + cr->mac_phy_siga_1 = 0x184c; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->dbgport_ip = DBG_PORT_IP_SEL_C; + cr->dbgport_ip_m = DBG_PORT_IP_SEL_C_M; + cr->dbgport_idx = DBG_PORT_SEL_C; + cr->dbgport_idx_m = DBG_PORT_SEL_C_M; + cr->dbgport_val = DBG32_D_C; + cr->dbgport_val_m = DBG32_D_C_M; + cr->clk_en = DBG_PORT_REF_CLK_EN_C; + cr->clk_en_m = DBG_PORT_REF_CLK_EN_C_M; + cr->dbgport_en = DBG_PORT_EN_C; + cr->dbgport_en_m = DBG_PORT_EN_C_M; + cr->bb_monitor_sel1 = MONITOR_SEL1_C; + cr->bb_monitor_sel1_m = MONITOR_SEL1_C_M; + cr->bb_monitor1 = 0x1b14; + cr->bb_monitor1_m = MASKDWORD; + /*mac_phy_intf*/ + cr->mac_phy_ppdu_type = 0x1800; + cr->mac_phy_txpath_en = 0x1800; + cr->mac_phy_txcmd = 0x1800; + cr->mac_phy_txsc = 0x1804; + cr->mac_phy_bw = 0x1804; + cr->mac_phy_tx_pw = 0x1804; + cr->mac_phy_n_usr = 0x1808; + cr->mac_phy_stbc = 0x1810; + cr->mac_phy_gi = 0x1810; + cr->mac_phy_ltf = 0x1810; + cr->mac_phy_ndp_en = 0x1814; + cr->mac_phy_n_sts = 0x1818; + cr->mac_phy_fec = 0x1818; + cr->mac_phy_mcs_3_0 = 0x1818; + cr->mac_phy_mcs_5_4 = 0x181c; + cr->mac_phy_lsig = 0x1840; + cr->mac_phy_siga_0 = 0x1848; + cr->mac_phy_siga_1 = 0x184c; + + break; + #endif + + default: + break; + } + +} + diff --git a/phl/hal_g6/phy/bb/halbb_dbg.h b/phl/hal_g6/phy/bb/halbb_dbg.h new file mode 100644 index 0000000..08a9bc3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg.h @@ -0,0 +1,219 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DBG_H__ +#define __HALBB_DBG_H__ + +#include "../../hal_headers_le.h" + +/*@--------------------------[Define] ---------------------------------------*/ +#define HALBB_WATCHDOG_PERIOD 2 /*second*/ + +#define PHY_HIST_SIZE 12 +#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) + +#define LA_CLK_EN 0x014 /*Just for dbg, will be removed*/ +#define LA_CLK_EN_M 0x1 /*Just for dbg, will be removed*/ + +#ifdef HALBB_DBG_TRACE_SUPPORT + #ifdef HALBB_DBCC_SUPPORT + #define BB_DBG(bb, comp, fmt, ...) \ + do {\ + if(bb->dbg_component & comp) {\ + _os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\ + } \ + } while (0) + #else + #define BB_DBG(bb, comp, fmt, ...) \ + do {\ + if(bb->dbg_component & comp) {\ + _os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\ + } \ + } while (0) + #endif + + #define BB_TRACE(fmt, ...) \ + do {\ + _os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\ + } while (0) + + #define BB_WARNING(fmt, ...) \ + do {\ + _os_dbgdump("[WARNING][BB]" fmt, ##__VA_ARGS__);\ + } while (0) + + #define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + u32 len_tmp = 0; \ + if (*used_len_tmp < max_buff_len) { \ + len_tmp = _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__); \ + if (in_cnsl) { \ + *used_len_tmp += len_tmp; \ + } else { \ + BB_TRACE("%s\n", buff_addr); \ + } \ + }\ + } while (0) +#else + #define BB_DBG + #define BB_TRACE + #define BB_WARNING + #define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) +#endif + +#define BB_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do {\ + _os_dbgdump("[CNSL]" fmt, ##__VA_ARGS__);\ + } while (0) + +#define BB_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) + +#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/ +#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/ +#define DBGPORT_PRI_1 1 /*Watch dog function*/ +#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_dbg_devider_len_t +{ + BB_DEVIDER_LEN_32 = 0, + BB_DEVIDER_LEN_16 = 1, +}; + +enum bb_dbg_port_ip_t +{ + DBGPORT_IP_TD = 1, + DBGPORT_IP_RX_INNER = 2, + DBGPORT_IP_TX_INNER = 3, + DBGPORT_IP_OUTER = 4, + DBGPORT_IP_INTF = 5, + DBGPORT_IP_CCK = 6, + DBGPORT_IP_BF = 7, + DBGPORT_IP_RX_OUTER = 8, + DBGPORT_IP_RFC0 = 0X1B, + DBGPORT_IP_RFC1 = 0X1C, + DBGPORT_IP_RFC2 = 0X1D, + DBGPORT_IP_RFC3 = 0X1E, + DBGPORT_IP_TST = 0X1F, +}; +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_dbg_cr_info { + u32 dbgport_ip; + u32 dbgport_ip_m; + u32 dbgport_idx; + u32 dbgport_idx_m; + u32 dbgport_val; + u32 dbgport_val_m; + u32 clk_en; + u32 clk_en_m; + u32 dbgport_en; + u32 dbgport_en_m; + u32 bb_monitor_sel1; + u32 bb_monitor_sel1_m; + u32 bb_monitor1; + u32 bb_monitor1_m; + /*mac_phy_intf*/ + u32 mac_phy_ppdu_type; + u32 mac_phy_txpath_en; + u32 mac_phy_txcmd; + u32 mac_phy_txsc; + u32 mac_phy_bw; + u32 mac_phy_tx_pw; + u32 mac_phy_ndp_en; + u32 mac_phy_n_usr; + u32 mac_phy_gi; + u32 mac_phy_ltf; + u32 mac_phy_n_sts; + u32 mac_phy_fec; + u32 mac_phy_mcs_3_0; + u32 mac_phy_mcs_5_4; + u32 mac_phy_stbc; + u32 mac_phy_lsig; + u32 mac_phy_siga_0; + u32 mac_phy_siga_1; +}; + +struct bb_dbg_info { + bool cr_recorder_en; + bool cr_recorder_rf_en; /*HALRF write BB CR*/ + /*CR init debug control*/ + bool cr_dbg_mode_en; + u32 cut_curr_dbg; + u32 rfe_type_curr_dbg; +#ifdef HALBB_TDMA_CR_SUPPORT + struct halbb_timer_info tdma_cr_timer_i; + bool tdma_cr_en; + u8 tdma_cr_state; + u32 tdma_cr_idx; + u32 tdma_cr_mask; + u32 tdma_cr_val_0; + u32 tdma_cr_val_1; + u32 tdma_cr_period_0; + u32 tdma_cr_period_1; +#endif + struct bb_dbg_cr_info bb_dbg_cr_i; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_print_devider(struct bb_info *bb, u8 len, bool with_space); +#ifdef HALBB_TDMA_CR_SUPPORT +void halbb_tdma_cr_sel_io_en(struct bb_info *bb); +void halbb_tdma_cr_timer_init(struct bb_info *bb); +void halbb_tdma_cr_sel_main(struct bb_info *bb); +void halbb_tdma_cr_sel_deinit(struct bb_info *bb); +void halbb_tdma_cr_sel_init(struct bb_info *bb); +#endif +void halbb_dbg_comp_init(struct bb_info *bb); +void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable); +u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb); +void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port); +void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip); +void halbb_release_bb_dbg_port(struct bb_info *bb); +bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority); +u32 halbb_get_bb_dbg_port_val(struct bb_info *bb); +void halbb_basic_dbg_message(struct bb_info *bb); +void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len); +void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halbb_cr_table_dump(struct bb_info *bb, u32 *cr_table, u32 cr_len); +void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len, bool dump_2_buff); +void halbb_show_rx_rate(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halbb_dbg_setting_init(struct bb_info *bb); +void halbb_cr_cfg_dbg_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dbg_cmd.c b/phl/hal_g6/phy/bb/halbb_dbg_cmd.c new file mode 100644 index 0000000..f414559 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg_cmd.c @@ -0,0 +1,865 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halbb_precomp.h" +#include "halbb_dbg_cmd_table.h" + +void halbb_bbcr_rw_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 addr = 0 , mask = MASKDWORD, val_32 = 0; + u32 write_val = 0; + u8 mask_m = 31, mask_l = 0; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]); + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "r dw {reg_DW}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "r {bit_M} {bit_L} {reg_DW}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "w dw {reg_DW} {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "w {bit_M} {bit_L} {reg_DW} {val}\n"); + return; + } + + if (_os_strcmp(input[2], "dw") == 0) { + HALBB_SCAN(input[3], DCMD_HEX, &val[0]); + HALBB_SCAN(input[4], DCMD_HEX, &val[1]); + addr = val[0]; + write_val = val[1]; + } else { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_HEX, &val[2]); + HALBB_SCAN(input[5], DCMD_HEX, &val[3]); + + mask_m = (u8)val[0]; + mask_l = (u8)val[1]; + addr = val[2]; + write_val = val[3]; + + mask = (u32)halbb_gen_mask(mask_m, mask_l); + if (mask == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Error mask = 0x%x\n", mask); + } + } + + if (addr % 4) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Error DW offset = 0x%x\n", addr); + return; + } + + if (_os_strcmp(input[1], "r") == 0) { + val_32 = halbb_get_reg(bb, addr, mask); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[R] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32); + } else if (_os_strcmp(input[1], "w") == 0) { + halbb_set_reg(bb, addr, mask, write_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[W] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, write_val); + + halbb_delay_ms(bb, 1); + + val_32 = halbb_get_reg(bb, addr, mask); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[READ_BACK] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32); + } +#if 0 + else if (_os_strcmp(input[1], "rf_r") == 0) { + val_32 = halbb_rf_get_bb_reg(bb, addr, mask); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[RFR] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32); + } else if (_os_strcmp(input[1], "rf_w") == 0) { + halbb_rf_set_bb_reg(bb, addr, mask, write_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[RFW] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, write_val); + + halbb_delay_ms(bb, 1); + + val_32 = halbb_get_reg(bb, addr, mask); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[READ_BACK] Reg0x%x[%02d:%02d] = 0x%x\n", mask_m, mask_l, addr, val_32); + } +#endif +} + +void halbb_bb_td_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_dbg_info *dbg = &bb->bb_dbg_i; + u32 val[10] = {0}; + u32 tmp = 0; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pop_en {en} {phl_phy_idx}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set_pd_low {val} {bw} {phl_phy_idx}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "per {phl_phy_idx}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pfd set {type}\n"); + #ifdef HALBB_TDMA_CR_SUPPORT + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tdma_cr en\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tdma_cr cr {cr_idx} {cr_mask} {val_0} {val_1}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tdma_cr period {p0_ms} {p1_ms}\n"); + #endif + return; + } + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + + if (_os_strcmp(input[1], "pop_en") == 0) { + halbb_pop_en(bb, (bool)val[0], bb->bb_phy_idx); + } else if (_os_strcmp(input[1], "set_pd_low") == 0) { + halbb_set_pd_lower_bound(bb, (u8)val[0], (enum channel_width)val[1], bb->bb_phy_idx); + #ifdef HALBB_TDMA_CR_SUPPORT + } else if (_os_strcmp(input[1], "tdma_cr") == 0) { + if (_os_strcmp(input[2], "en") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + if (dbg->tdma_cr_idx == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Err tdma_cr_idx = 0\n"); + return; + } + + dbg->tdma_cr_en = (bool)val[0]; + halbb_tdma_cr_sel_main(bb); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tdma_cr_en=%d\n", dbg->tdma_cr_en); + } else if (_os_strcmp(input[2], "period") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + dbg->tdma_cr_period_0 = val[0]; + dbg->tdma_cr_period_1 = val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "period 0/1= {%d, %d} ms\n", + dbg->tdma_cr_period_0, + dbg->tdma_cr_period_1); + } else if (_os_strcmp(input[2], "cr") == 0) { + HALBB_SCAN(input[3], DCMD_HEX, &val[0]); + HALBB_SCAN(input[4], DCMD_HEX, &val[1]); + HALBB_SCAN(input[5], DCMD_HEX, &val[2]); + HALBB_SCAN(input[6], DCMD_HEX, &val[3]); + + dbg->tdma_cr_idx = val[0]; + dbg->tdma_cr_mask = val[1]; + dbg->tdma_cr_val_0 = val[2]; + dbg->tdma_cr_val_1 = val[3]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Reg 0x%x[0x%x] = {0x%x, 0x%x}\n", + dbg->tdma_cr_idx, dbg->tdma_cr_mask, + dbg->tdma_cr_val_0, dbg->tdma_cr_val_1); + } + #endif + #ifdef BB_8852A_2_SUPPORT + } else if (_os_strcmp(input[1], "per") == 0) { + halbb_get_per_8852a_2(bb, bb->bb_phy_idx); + } else if (_os_strcmp(input[1], "pfd") == 0) { + if (bb->ic_type != BB_RTL8852A) + return; + + if (_os_strcmp(input[2], "set") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + halbb_manual_pkt_fmt_sel_8852a_2(bb, (enum bb_pfd_fmt_type)val[0]); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pfd_fmt_type=%d\n", val[0]); + } + #endif + } +} + +void halbb_bb_fd_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{fd dbg}\n"); + return; + } +} + +/*void halbb_fw_trace_en_h2c(struct bb_info *bb, bool enable, + u32 fw_dbg_comp, u32 monitor_mode, u32 macid) +{ + u8 h2c_parameter[7] = {0}; + u8 cmd_length; + + h2c_parameter[0] = enable; + h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0); + h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8); + h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16); + h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24); + h2c_parameter[5] = (u8)monitor_mode; + h2c_parameter[6] = (u8)macid; + cmd_length = 7; + + BB_DBG(bb, DBG_FW_INFO, + "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", + enable, monitor_mode, macid); + + //odm_fill_h2c_cmd(bb, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); +}*/ + +void halbb_cmn_msg_setting(struct bb_info *bb, u32 *val, u32 *_used, + char *output, u32 *_out_len) +{ + u32 used = *_used; + u32 out_len = *_out_len; + + if (val[1] == 1) { + bb->cmn_dbg_msg_period = (u8)val[2]; + + if (bb->cmn_dbg_msg_period < HALBB_WATCHDOG_PERIOD) + bb->cmn_dbg_msg_period = HALBB_WATCHDOG_PERIOD; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "cmn_dbg_msg_period=%d\n", bb->cmn_dbg_msg_period); + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_trace_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u64 pre_debug_components, one = 1; + u64 comp = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + comp = bb->dbg_component; + pre_debug_components = bb->dbg_component; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n================================\n"); + if (val[0] == 100) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[DBG MSG] Component Selection\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "00. (( %s ))RA\n", + ((comp & DBG_RA) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "01. (( %s ))FA_CNT\n", + ((comp & DBG_FA_CNT) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "02. (( %s ))RSSI_MNTR\n", + ((comp & DBG_HALBB_FUN_RSVD_2) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "03. (( %s ))DFS\n", + ((comp & DBG_DFS) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "04. (( %s ))EDCCA\n", + ((comp & DBG_EDCCA) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "05. (( %s ))ENV_MNTR\n", + ((comp & DBG_ENV_MNTR) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "06. (( %s ))CFO_TRK\n", + ((comp & DBG_CFO_TRK) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "07. (( %s ))PWR_CTRL\n", + ((comp & DBG_PWR_CTRL) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "08. (( %s ))RUA_TBL\n", + ((comp & DBG_RUA_TBL) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "09. (( %s ))F_AUTO_DBG\n", + ((comp & DBG_AUTO_DBG) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "10. (( %s ))ANT_DIV\n", + ((comp & DBG_ANT_DIV) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "11. (( %s ))DIG\n", + ((comp & DBG_DIG) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "12. (( %s ))TBD\n", + ((comp & BIT(12)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "13. (( %s ))TBD\n", + ((comp & BIT(13)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "14. (( %s ))TBD\n", + ((comp & BIT(14)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "15. (( %s ))TBD\n", + ((comp & BIT(15)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "16. (( %s ))TBD\n", + ((comp & BIT(16)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "17. (( %s ))TBD\n", + ((comp & BIT(17)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "18. (( %s ))TBD\n", + ((comp & BIT(18)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "19. (( %s ))TBD\n", + ((comp & BIT(19)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "20. (( %s ))PHY_STATUS\n", + ((comp & DBG_PHY_STS) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "21. (( %s ))TBD\n", + ((comp & BIT(21)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "22. (( %s ))FW_INFO\n", + ((comp & DBG_FW_INFO) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "23. (( %s ))COMMON_FLOW\n", + ((comp & DBG_COMMON_FLOW) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "24. (( %s ))IC_API\n", + ((comp & DBG_IC_API) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "25. (( %s ))DBG_API\n", + ((comp & DBG_DBG_API) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "26. (( %s ))DBCC\n", + ((comp & DBG_DBCC) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "27. (( %s ))DM_SUMMARY\n", + ((comp & DBG_DM_SUMMARY) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "28. (( %s ))PHY_CONFIG\n", + ((comp & DBG_PHY_CONFIG) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "29. (( %s ))INIT\n", + ((comp & DBG_INIT) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "30. (( %s ))COMMON\n", + ((comp & DBG_CMN) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "31. (( %s ))TBD\n", + ((comp & BIT(31)) ? ("V") : ("."))); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (val[0] == 101) { + bb->dbg_component = 0; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Disable all debug components\n"); + } else { + if (val[1] == 1) /*@enable*/ + bb->dbg_component |= (one << val[0]); + else if (val[1] == 2) /*@disable*/ + bb->dbg_component &= ~(one << val[0]); + else + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[Warning] 1:on, 2:off\n"); + + if (BIT(val[0]) == DBG_CMN) { + halbb_cmn_msg_setting(bb, val, &used, output, &out_len); + } + } + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "pre-DbgComponents = 0x%llx\n", pre_debug_components); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Curr-DbgComponents = 0x%llx\n", bb->dbg_component); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; +} + +u32 halbb_get_multiple(u8 pow, u8 base) +{ + u8 i; + u32 return_value = 1; + + for (i = 0; i < pow; i++) + return_value *= base; /*base ^ pow*/ + + return return_value; +} + +u32 halbb_str_2_dec(u8 val) +{ + if (val >= 0x30 && val <= 0x39) /*0~9*/ + return (val - 0x30); + else if (val >= 0x41 && val <= 0x46) /*A~F*/ + return (val - 0x41 + 10); + else if (val >= 0x61 && val <= 0x66) /*a~f*/ + return (val - 0x61 + 10); + else + return 1; +} + +void halbb_scanf(char *in, enum bb_scanf_type type, u32 *out) +{ + char buff[DCMD_SCAN_LIMIT]; + u32 multiple = 1; + u8 text_num = 0; + u8 base = 10; + u8 i = 0, j = 0; + + *out = 0; + + for (i = 0; i < DCMD_SCAN_LIMIT; i++) { + /*BB_TRACE("pInput[%d] = %x\n", i, in[i]);*/ + if (in[i] != 0x0) { /* 0x0 = NULL. */ + buff[i] = in[i]; + continue; + } + + if (type == DCMD2_CHAR) { + *out = *in; + break; + } + + base = (type == DCMD2_DECIMAL) ? 10 : 16; + text_num = i; + + for (j = 0; j < text_num; j++) { + /*BB_TRACE("text_num=%d, sbuff[j]=%d, j=%d, value=%d\n",text_num, buff[j], j, base);*/ + multiple = halbb_get_multiple(text_num - 1 - j, base); + *out += halbb_str_2_dec(buff[j]) * multiple; + /*BB_TRACE("[%d]*pOutput = %d\n", j, *out);*/ + } + break; + } +} + +void halbb_cmd_parser(struct bb_info *bb, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + struct bb_echo_cmd_info *echo_cmd = &bb->bb_cmn_hooker->bb_echo_cmd_i; + u32 used = 0; + u8 id = 0; + u32 var1[10] = {0}; + u32 i; + u32 halbb_ary_size = echo_cmd->cmd_size; + u32 directory = 0; + char char_temp = ' '; + //u32 val_tmp; + + if (halbb_ary_size == 0) + return; + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < halbb_ary_size; i++) { + if (_os_strcmp(halbb_cmd_i[i].name, input[0]) == 0) { + id = halbb_cmd_i[i].id; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[%s]===>\n", halbb_cmd_i[i].name); + break; + } + } + if (i == halbb_ary_size) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "HALBB command not found!\n"); + return; + } + } + + #ifdef HALBB_DBCC_SUPPORT + bb = halbb_get_curr_bb_pointer(bb, bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[BB echo cmd] Phy-%d\n", bb->bb_phy_idx); + #endif + + switch (id) { + case HALBB_HELP: { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "BB cmd ==>\n"); + + for (i = 0; i < halbb_ary_size - 2; i++) + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + " %-5d: %s\n", i, halbb_cmd_i[i + 2].name); + } break; + + case HALBB_DEMO: + /*echo bb demo 12 3b abcde -10*/ + + HALBB_SCAN(input[1], DCMD_DECIMAL, &directory); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Decimal value = %d\n", directory); + + HALBB_SCAN(input[2], DCMD_HEX, &directory); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Hex value = 0x%x\n", directory); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "String = %s\n", input[3]); + + HALBB_SCAN(input[4], "%d", &directory); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "value_u32 = %d\n", (u32)directory); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "value_s32 = %d\n", (s32)directory); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "value_hex = 0x%x\n", directory); + break; + + case HALBB_CMN_DBG: + halbb_cmn_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_REG_RW: + halbb_bbcr_rw_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_STASISTICS: + #ifdef HALBB_STATISTICS_SUPPORT + halbb_crc32_cnt_dbg(bb, input, &used, output, &out_len); + #endif + break; + + case HALBB_DBG_PORT: + halbb_dbgport_dbg(bb, input, &used, output, &out_len); + break; + + #ifdef HALBB_RA_SUPPORT + case HALBB_RA: + halbb_ra_dbg(bb, input, &used, output, &out_len); + break; + #endif + + case HALBB_TRACE: + halbb_trace_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_MP_DBG: + halbb_mp_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_SUPPORT_ABILITY: + halbb_supportability_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_IC_API: + halbb_ic_api_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_PROFILE: + halbb_basic_profile_dbg(bb, &used, output, &out_len); + break; + case HALBB_TX_PW: + halbb_pwr_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_LA_MODE: + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_cmd_dbg(bb, input, &used, output, &out_len); + #endif + break; + + case HALBB_PSD: + #ifdef HALBB_PSD_SUPPORT + halbb_psd_dbg(bb, input, &used, output, &out_len); + #endif + break; + + case HALBB_DUMP_REG: + halbb_dump_reg_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_CFO_TRK: + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_trk_dbg(bb, input, &used, output, &out_len); + #endif + break; + +#if 0 + case HALBB_AUTO_DBG: + #ifdef HALBB_AUTO_DEGBUG + halbb_auto_dbg_console(bb, input, &used, output, &out_len); + #endif + break; +#endif + + case HALBB_DD_DBG: + halbb_dd_dump_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_SHOW_RXRATE: + halbb_show_rx_rate(bb, input, &used, output, &out_len); + break; +#if 0 + case HALBB_NBI_EN: + halbb_nbi_debug(bb, input, &used, output, &out_len); + break; + + case HALBB_CSI_MASK_EN: + halbb_csi_debug(bb, input, &used, output, &out_len); + break; +#endif + + case HALBB_DFS_DBG: + #ifdef HALBB_DFS_SUPPORT + halbb_dfs_debug(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_DIG: + #ifdef HALBB_DIG_SUPPORT + halbb_dig_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_NHM: + #ifdef NHM_SUPPORT + halbb_nhm_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_CLM: + #ifdef CLM_SUPPORT + halbb_clm_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_IFS_CLM: + #ifdef IFS_CLM_SUPPORT + halbb_ifs_clm_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_FAHM: + #ifdef FAHM_SUPPORT + halbb_fahm_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_EDCCA_CLM: + #ifdef EDCCA_CLM_SUPPORT + halbb_edcca_clm_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_EDCCA: + #ifdef HALBB_EDCCA_SUPPORT + halbb_edcca_dbg(bb, input, &used, output, &out_len); + #endif + break; + case HALBB_ENV_MNTR: + #ifdef HALBB_ENV_MNTR_SUPPORT + halbb_env_mntr_dbg(bb, input, &used, output, &out_len); + #endif + break; +#if 0 + case HALBB_BB_INFO: + halbb_bb_hw_dbg_info(bb, input, &used, output, &out_len); + break; + + case HALBB_H2C: + halbb_h2C_debug(bb, input, &used, output, &out_len); + break; + + case HALBB_ADAPTIVITY_DBG: + #ifdef HALBB_SUPPORT_ADAPTIVITY + halbb_adaptivity_debug(bb, input, &used, output, &out_len); + #endif + break; +#endif + case HALBB_STA_INFO: + halbb_sta_info_dbg(bb, input, &used, output, &out_len); + break; + + case HALBB_PAUSE_FUNC: + halbb_pause_func_dbg(bb, input, &used, output, &out_len); + break; +#if 0 + case HALBB_PER_TONE_EVM: + halbb_per_tone_evm(bb, input, &used, output, &out_len); + break; + + #ifdef CONFIG_DYNAMIC_TX_TWR + case HALBB_DYN_TXPWR: + halbb_dtp_debug(bb, input, &used, output, &out_len); + break; + #endif +#endif + case HALBB_PHY_STATUS: + halbb_physts_dbg(bb, input, &used, output, &out_len); + break; +#if 0 +#ifdef HALBB_DCC_ENHANCE + case HALBB_DCC: + halbb_dig_cckpd_coex_dbg(bb, input, &used, output, &out_len); + break; +#endif +#endif +#ifdef HALBB_PMAC_TX_SETTING_SUPPORT + case HALBB_PMAC_TX: + halbb_pmac_tx_dbg(bb, input, &used, output, &out_len); + break; +#endif + case HALBB_FW_DBG: + halbb_fw_dbg(bb, input, &used, output, &out_len); + break; +#ifdef HALBB_CH_INFO_SUPPORT + case HALBB_CH_INFO: + halbb_ch_info_dbg(bb, input, &used, output, &out_len); + break; +#endif +#ifdef HALBB_RUA_SUPPORT + case HALBB_RUA_TBL: + halbb_rua_tbl_dbg(bb, input, &used, output, &out_len); + break; +#endif + case HALBB_TD_CFG: + halbb_bb_td_dbg(bb, input, &used, output, &out_len); + break; + case HALBB_FD_CFG: + halbb_bb_fd_dbg(bb, input, &used, output, &out_len); + break; +#ifdef HALBB_DBCC_SUPPORT + case HALBB_DBCC: + halbb_dbcc_dbg(bb, input, &used, output, &out_len); + break; +#endif +#ifdef HALBB_ANT_DIV_SUPPORT + case HALBB_ANT_DIV: + halbb_antdiv_dbg(bb, input, &used, output, &out_len); + break; +#endif +#ifdef HALBB_DYN_CSI_RSP_SUPPORT + case HALBB_DCR_DBG: + halbb_dyn_csi_rsp_dbg(bb, input, &used, output, &out_len); + break; +#endif + case HALBB_RX_GAIN_TABLE: + halbb_rx_gain_table_dbg(bb, input, &used, output, &out_len); + break; + case HALBB_HW_SETTING: + halbb_ic_hw_setting_dbg(bb, input, &used, output, &out_len); + break; + default: + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Do not support this command\n"); + break; + } + + //BB_DBG_CNSL(out_len, used, output + used, out_len - used, + // "[OUT] bb_phy_idx=%d\n", bb->bb_phy_idx); + +} + +void halbb_cmd_parser_init(struct bb_info *bb) +{ + struct bb_echo_cmd_info *echo_cmd = &bb->bb_cmn_hooker->bb_echo_cmd_i; + + echo_cmd->cmd_size = sizeof(halbb_cmd_i) / sizeof(struct halbb_cmd_info); + echo_cmd->echo_phy_idx = HW_PHY_0; +} + +s32 halbb_cmd(struct bb_info *bb, char *input, char *output, u32 out_len) +{ + char *token; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; + + do { + token = _os_strsep(&input, ", "); + if (token) { + if (_os_strlen(token) <= MAX_ARGV) + _os_strcpy(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < MAX_ARGC); + + halbb_cmd_parser(bb, argv, argc, output, out_len); + + return 0; +} + +void halbb_fwdbg_trace(struct bb_info *bb, u32 dbg_comp, u8 fw_trace_en) +{ + struct bb_fw_dbg_cmn_info *bb_fwdbg = &bb->bb_fwdbg_i; + u32 *bb_h2c = (u32 *) bb_fwdbg; + u8 cmdlen = sizeof(struct bb_fw_dbg_cmn_info); + bool ret_val = false; + u8 ret_v0, ret_v1, ret_v2; + + /* Set fwdbg api, mac api need driver package*/ + ret_v0 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_LEVEL, FL_LV_LOUD); + ret_v1 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_OUTPUT, FL_OP_C2H); + ret_v2 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_COMP, FL_COMP_BB); + /* Set fwbb debug component */ + bb_fwdbg->fw_dbg_comp[0] = (u8) (dbg_comp&0x000000ff); + bb_fwdbg->fw_dbg_comp[1] = (u8) (dbg_comp&0x0000ff00); + bb_fwdbg->fw_dbg_comp[2] = (u8) (dbg_comp&0x00ff0000); + bb_fwdbg->fw_dbg_comp[3] = (u8) (dbg_comp&0xff000000); + bb_fwdbg->fw_dbg_trace = fw_trace_en; + BB_DBG(bb, DBG_FW_INFO, "FW TRACE: %x %x\n", bb_h2c[0], bb_h2c[1]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FWTRACE, HALBB_H2C_DM, bb_h2c); +} + +void halbb_fw_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u8 i; + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (_os_strcmp(input[1], help) == 0) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{fw_dbg (dbg_trace=> 1:enable, 2:disable) (dbg_comp)}\n"); + goto out; + } + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + if (val[0] == 1) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[fw_dbg] Enable : dbg_comp = %x\n", val[1]); + halbb_fwdbg_trace(bb, val[1], 1); + } else if (val[0] == 2) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[fw_dbg] Disable : dbg_comp clear\n"); + halbb_fwdbg_trace(bb, 0, 0); + } else if (val[0] == 3) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[fw_dbg] Trigger h2c ==> c2h debug\n"); + halbb_test_h2c_c2h_flow(bb); + } else if (val[0] == 4) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[fw_dbg] Set h2c get tx statistic\n"); + rtw_halbb_query_txsts(bb, (u16)val[1], (u16)val[2]); + } + +out: + *_used = used; + *_out_len = out_len; +} + diff --git a/phl/hal_g6/phy/bb/halbb_dbg_cmd.h b/phl/hal_g6/phy/bb/halbb_dbg_cmd.h new file mode 100644 index 0000000..fcdc3ca --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg_cmd.h @@ -0,0 +1,82 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_DBG_CMD_H_ +#define _HALBB_DBG_CMD_H_ +/*@--------------------------[Define] ---------------------------------------*/ +#define MAX_ARGC 20 +#define MAX_ARGV 16 + +#if 1 +#define HALBB_SCAN _os_sscanf +#define DCMD_DECIMAL "%d" +#define DCMD_HEX "%x" +#define DCMD_HEX64 "%llx" +#define DCMD_CHAR "%s" +#else +#define HALBB_SCAN halbb_scanf +enum bb_scanf_type +{ + DCMD_DECIMAL = 1, + DCMD_HEX = 2, + DCMD_CHAR = 3, +}; +#endif + +#define DCMD_SCAN_LIMIT 10 + +/*@--------------------------[Enum]------------------------------------------*/ + +enum bb_scanf_type +{ + DCMD2_DECIMAL = 1, + DCMD2_HEX = 2, + DCMD2_CHAR = 3, +}; + + enum FWBB_DBG_COMP_SET { + FWBBDBG_H2C = BIT0, + FWBBDBG_RA = BIT8, + FWBBDBG_RUA = BIT16, + FWBBDBG_ULPWR_CTRL = BIT24, + FWBBDBG_ULRA = BIT25, +}; + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_echo_cmd_info { + u8 cmd_size; + enum phl_phy_idx echo_phy_idx; +}; + +struct bb_fw_dbg_cmn_info { + u8 fw_dbg_comp[4]; + u8 fw_dbg_trace; + u8 fw_cmn_info; + u8 fw_rty_rpt_ctrl; + u8 rsvd0; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_dbgport_dump_all(struct bb_info *bb, u32 *_used, char *output, + u32 *_out_len); + +void halbb_dbgport_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_scanf(char *in, enum bb_scanf_type type, u32 *out); +void halbb_cmd_parser_init(struct bb_info *bb); +void halbb_fw_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dbg_cmd_ex.h b/phl/hal_g6/phy/bb/halbb_dbg_cmd_ex.h new file mode 100644 index 0000000..117eee2 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg_cmd_ex.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALBB_DBG_CMD_EX_H__ +#define __HALBB_DBG_CMD_EX_H__ +#define MAX_ARGV 16 + +struct bb_info; + +s32 halbb_cmd(struct bb_info *bb, char *input, char *output, u32 out_len); + + +void halbb_cmd_parser(struct bb_info *bb, char input[][MAX_ARGV], + u32 input_num, char *output, u32 out_len); + + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dbg_cmd_table.h b/phl/hal_g6/phy/bb/halbb_dbg_cmd_table.h new file mode 100644 index 0000000..850bf4f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dbg_cmd_table.h @@ -0,0 +1,134 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_DBG_CMD_TABLE_H_ +#define _HALBB_DBG_CMD_TABLE_H_ +/*@--------------------------[Define] ---------------------------------------*/ + + +/*@--------------------------[Enum]------------------------------------------*/ +enum HALBB_CMD_ID { + HALBB_HELP, + HALBB_DEMO, + HALBB_REG_RW, + HALBB_CMN_DBG, + HALBB_RA, + HALBB_PROFILE, + HALBB_TRACE, + HALBB_MP_DBG, + HALBB_SUPPORT_ABILITY, + HALBB_TX_PW, + HALBB_IC_API, + HALBB_LA_MODE, + HALBB_DUMP_REG, + HALBB_AUTO_DBG, + HALBB_DD_DBG, + HALBB_SHOW_RXRATE, + HALBB_NBI_EN, + HALBB_CSI_MASK_EN, + HALBB_DFS_DBG, + HALBB_DIG, + HALBB_NHM, + HALBB_CLM, + HALBB_IFS_CLM, + HALBB_FAHM, + HALBB_EDCCA_CLM, + HALBB_EDCCA, + HALBB_ENV_MNTR, + HALBB_BB_INFO, + HALBB_H2C, + HALBB_STASISTICS, + HALBB_PSD, + HALBB_DBG_PORT, + HALBB_CFO_TRK, + HALBB_ADAPTIVITY_DBG, + HALBB_STA_INFO, + HALBB_PAUSE_FUNC, + HALBB_PER_TONE_EVM, + HALBB_DYN_TXPWR, + HALBB_PHY_STATUS, + HALBB_DCC, + HALBB_PMAC_TX, + HALBB_FW_DBG, + HALBB_CH_INFO, + HALBB_RUA_TBL, + HALBB_TD_CFG, + HALBB_FD_CFG, + HALBB_DBCC, + HALBB_ANT_DIV, + HALBB_DCR_DBG, + HALBB_RX_GAIN_TABLE, + HALBB_HW_SETTING +}; + +/*@--------------------------[Structure]-------------------------------------*/ + +struct halbb_cmd_info { + char name[16]; + u8 id; +}; + +static const struct halbb_cmd_info halbb_cmd_i[] = { + {"-h", HALBB_HELP}, /*@do not move this element to other position*/ + {"demo", HALBB_DEMO}, /*@do not move this element to other position*/ + {"cr", HALBB_REG_RW}, + {"cmn", HALBB_CMN_DBG}, + {"ra", HALBB_RA}, + {"profile", HALBB_PROFILE}, + {"dbg", HALBB_TRACE}, + {"mp_dbg", HALBB_MP_DBG}, + {"ability", HALBB_SUPPORT_ABILITY}, + {"tx_pw", HALBB_TX_PW}, + {"ic_api", HALBB_IC_API}, + {"lamode", HALBB_LA_MODE}, + {"psd", HALBB_PSD}, + {"dumpreg", HALBB_DUMP_REG}, + //{"auto_dbg", HALBB_AUTO_DBG}, + {"dd_dbg", HALBB_DD_DBG}, + {"cfo_trk", HALBB_CFO_TRK}, + {"rxrate", HALBB_SHOW_RXRATE}, + //{"nbi", HALBB_NBI_EN}, + //{"csi_mask", HALBB_CSI_MASK_EN}, + {"dfs", HALBB_DFS_DBG}, + {"dig", HALBB_DIG}, + {"nhm", HALBB_NHM}, + {"clm", HALBB_CLM}, + {"ifs_clm", HALBB_IFS_CLM}, + {"fahm", HALBB_FAHM}, + {"edcca_clm", HALBB_EDCCA_CLM}, + {"edcca", HALBB_EDCCA}, + {"env_mntr", HALBB_ENV_MNTR}, + //{"bbinfo", HALBB_BB_INFO}, + //{"h2c", HALBB_H2C}, + {"stat", HALBB_STASISTICS}, + {"dbgport", HALBB_DBG_PORT}, + {"sta_info", HALBB_STA_INFO}, + {"pause", HALBB_PAUSE_FUNC}, + {"physts", HALBB_PHY_STATUS}, + {"pmac_tx", HALBB_PMAC_TX}, + {"fw_dbg", HALBB_FW_DBG}, + {"ch_info", HALBB_CH_INFO}, + {"td", HALBB_TD_CFG}, + {"fd", HALBB_FD_CFG}, + {"dbcc", HALBB_DBCC}, + {"rua", HALBB_RUA_TBL}, + {"ant_div", HALBB_ANT_DIV}, + {"dcr", HALBB_DCR_DBG}, + {"gain_table", HALBB_RX_GAIN_TABLE}, + {"hw_set", HALBB_HW_SETTING} + }; + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dfs.c b/phl/hal_g6/phy/bb/halbb_dfs.c new file mode 100644 index 0000000..866f98c --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dfs.c @@ -0,0 +1,745 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_DFS_SUPPORT +void halbb_dfs(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + + BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__); + + if (!(bb->support_ability & BB_DFS)) + return; + if (bb_dfs->dfs_dyn_setting_en) + halbb_dfs_dyn_setting(bb); +} + +void halbb_dfs_init(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + + BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__); + + /*DFS Parameter Initialization*/ + bb_dfs->dfs_rgn_domain = bb->phl_com->dfs_info.region_domain; + halbb_dfs_rgn_dmn_dflt_cnfg(bb); + bb_dfs->chrp_obsrv_flag = false; + bb_dfs->dfs_sw_trgr_mode = false; + bb_dfs->dfs_dbg_mode = false; + bb_dfs->dfs_dyn_setting_en = true; + bb_dfs->dbg_prnt_en = false; + bb_dfs->is_mic_w53 = false; + bb_dfs->is_mic_w56 = false; + bb_dfs->chrp_th = DFS_CHIRP_TH; + bb_dfs->ppb_prcnt = DFS_PPB_IDLE_PRCNT; + bb_dfs->fk_dfs_num_th = 5; + bb_dfs->dfs_tp_th = 2; + bb_dfs->dfs_idle_prd_th = 50; + bb_dfs->dfs_fa_th = 20; + bb_dfs->dfs_nhm_th = 2; + bb_dfs->dfs_n_cnfd_lvl_th = 5; +} + +void halbb_radar_detect_reset(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + + struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i; + + halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 0); + halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 1); +} + +void halbb_radar_detect_disable(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i; + + halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 0); +} + +void halbb_radar_detect_enable(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i; + + halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 1); +} + +bool halbb_is_dfs_band(struct bb_info *bb, u8 ch, u8 bw) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + bool is_w53_band = false, is_w56_band = false; + + if ((ch >= 52) && (ch <= 64)) + is_w53_band = true; + else if ((ch >= 100) && (ch <= 144)) + is_w56_band = true; + +#ifdef CONFIG_PHL_DFS_REGD_JAP + if (bb_dfs->dfs_rgn_domain == DFS_REGD_JAP) + halbb_dfs_rgn_dmn_cnfg_by_ch(bb, is_w53_band, is_w56_band); +#endif + + if ((is_w53_band) || (is_w56_band)) + return true; + else + return false; +} + +void halbb_dfs_rgn_dmn_dflt_cnfg(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + u8 i; + + /* PW unit: 200ns ; PRI unit: 25us */ + +#ifdef CONFIG_PHL_DFS_REGD_FCC + /*Type {0,1,2,3,4,6,L}*/ + u8 pw_min_fcc_tab[DFS_RDR_TYP_NUM] = {5,5,5,30,55,5,250,0}; + u16 pw_max_fcc_tab[DFS_RDR_TYP_NUM] = {5,5,25,50,100,5,500,1000}; + u8 pri_min_fcc_tab[DFS_RDR_TYP_NUM] = {57,20,6,8,8,13,40,0}; + u8 pri_max_fcc_tab[DFS_RDR_TYP_NUM] = {58,123,10,20,20,14,80,0}; + u8 ppb_fcc_tab[DFS_RDR_TYP_NUM] = {18,18,23,16,12,9,8,255}; +#endif +#ifdef CONFIG_PHL_DFS_REGD_ETSI + /*Type {1,2,3,4,5,6,R}*/ + u8 pw_min_etsi_tab[DFS_RDR_TYP_NUM] = {2,2,2,100,2,2,5,0}; + u16 pw_max_etsi_tab[DFS_RDR_TYP_NUM] = {25,75,75,150,10,10,5,1000}; + u8 pri_min_etsi_tab[DFS_RDR_TYP_NUM] = {40,25,10,10,100,33,57,0}; + u8 pri_max_etsi_tab[DFS_RDR_TYP_NUM] = {200,200,18,20,134,100,58,0}; + u8 ppb_etsi_tab[DFS_RDR_TYP_NUM] = {10,15,25,20,10,15,18,255}; + /* + etsi 302 Type {1,2,3,4,5,X,L} + u8 pw_min_etsi2_tab[DFS_RDR_TYP_NUM] = {5,5,50,5,5,0,100,0}; + u16 pw_max_etsi2_tab[DFS_RDR_TYP_NUM] = {5,25,75,75,75,1000,150,1000}; + u8 pri_min_etsi2_tab[DFS_RDR_TYP_NUM] = {53,40,40,25,10,0,10,0}; + u8 pri_max_etsi2_tab[DFS_RDR_TYP_NUM] = {54,200,200,34,18,0,20,0}; + u8 ppb_etsi2_tab[DFS_RDR_TYP_NUM] = {15,10,15,15,25,255,20,255}; + */ +#endif + +#ifdef CONFIG_PHL_DFS_REGD_FCC + if (bb_dfs->dfs_rgn_domain == DFS_REGD_FCC) { + bb_dfs->l_rdr_exst_flag = true; + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + bb_dfs->pw_min_tab[i] = pw_min_fcc_tab[i]; + bb_dfs->pw_max_tab[i] = pw_max_fcc_tab[i]; + bb_dfs->pri_min_tab[i] = pri_min_fcc_tab[i]; + bb_dfs->pri_max_tab[i] = pri_max_fcc_tab[i]; + bb_dfs->ppb_tab[i] = ppb_fcc_tab[i]; + } + } +#endif +#ifdef CONFIG_PHL_DFS_REGD_ETSI + if (bb_dfs->dfs_rgn_domain == DFS_REGD_ETSI) { + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + bb_dfs->pw_min_tab[i] = pw_min_etsi_tab[i]; + bb_dfs->pw_max_tab[i] = pw_max_etsi_tab[i]; + bb_dfs->pri_min_tab[i] = pri_min_etsi_tab[i]; + bb_dfs->pri_max_tab[i] = pri_max_etsi_tab[i]; + bb_dfs->ppb_tab[i] = ppb_etsi_tab[i]; + } + } +#endif +} + +void halbb_dfs_rgn_dmn_cnfg_by_ch(struct bb_info *bb, bool w53_band, + bool w56_band) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + u8 i; + + /* PW unit: 200ns ; PRI unit: 25us */ + + /*Type {1,2,3,4,5,6,7,8}*/ + u8 pw_min_mic_w53_tab[DFS_RDR_TYP_NUM] = {2,2,2,2,2,2,2,2}; + u16 pw_max_mic_w53_tab[DFS_RDR_TYP_NUM] = {25,75,25,75,8,8,8,8}; + u8 pri_min_mic_w53_tab[DFS_RDR_TYP_NUM] = {40,25,40,25,35,42,44,53}; + u8 pri_max_mic_w53_tab[DFS_RDR_TYP_NUM] = {200,200,200,200,36,44,46,55}; + u8 ppb_mic_w53_tab[DFS_RDR_TYP_NUM] = {10,15,22,22,30,25,24,20}; + + /*Type {1,2,3,4,5,6,L,8}, ,ppb of Type3 is set as 15 due to RPT TO*/ + u8 pw_min_mic_w56_tab[DFS_RDR_TYP_NUM] = {2,5,10,5,30,55,250,5}; + u16 pw_max_mic_w56_tab[DFS_RDR_TYP_NUM] = {3,5,10,25,50,100,500,5}; + u8 pri_min_mic_w56_tab[DFS_RDR_TYP_NUM] = {55,57,160,6,8,8,40,13}; + u8 pri_max_mic_w56_tab[DFS_RDR_TYP_NUM] = {56,58,160,10,20,20,80,14}; + u8 ppb_mic_w56_tab[DFS_RDR_TYP_NUM] = {18,18,15,23,16,12,8,9}; + + if (bb_dfs->dfs_rgn_domain == DFS_REGD_JAP) { + if (w53_band) { + bb_dfs->is_mic_w53 = true; + bb_dfs->l_rdr_exst_flag = false; + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + bb_dfs->pw_min_tab[i] = pw_min_mic_w53_tab[i]; + bb_dfs->pw_max_tab[i] = pw_max_mic_w53_tab[i]; + bb_dfs->pri_min_tab[i] = pri_min_mic_w53_tab[i]; + bb_dfs->pri_max_tab[i] = pri_max_mic_w53_tab[i]; + bb_dfs->ppb_tab[i] = ppb_mic_w53_tab[i]; + } + } else if (w56_band) { + bb_dfs->is_mic_w56 = true; + bb_dfs->l_rdr_exst_flag = true; + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + bb_dfs->pw_min_tab[i] = pw_min_mic_w56_tab[i]; + bb_dfs->pw_max_tab[i] = pw_max_mic_w56_tab[i]; + bb_dfs->pri_min_tab[i] = pri_min_mic_w56_tab[i]; + bb_dfs->pri_max_tab[i] = pri_max_mic_w56_tab[i]; + bb_dfs->ppb_tab[i] = ppb_mic_w56_tab[i]; + } + } + } +} + +void halbb_radar_chrp_mntr(struct bb_info *bb, bool chrp_flag) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + u8 i = 0; + + if (bb->bb_sys_up_time - bb_dfs->chrp_srt_t >= DFS_FCC_LP_LNGTH) { + bb_dfs->chrp_obsrv_flag = false; + bb_dfs->chrp_srt_t = 0; + bb_dfs->chrp_cnt = 0; + bb_dfs->lng_rdr_cnt = 0; + } + + if ((chrp_flag) && !(bb_dfs->chrp_obsrv_flag)) { + bb_dfs->chrp_srt_t = bb->bb_sys_up_time; + bb_dfs->chrp_obsrv_flag = true; + } + + if (bb_dfs->dbg_prnt_en) + BB_DBG(bb, DBG_DFS, "[mntr_prd, sys_t, chrp_srt_t]: [%d, %d, %d]\n", + (bb->bb_sys_up_time - bb_dfs->chrp_srt_t), + bb->bb_sys_up_time, bb_dfs->chrp_srt_t); +} + +void halbb_radar_seq_inspctn(struct bb_info *bb, u16 dfs_rpt_idx, + u8 c_num, u8 p_num) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + + if (dfs_rpt_idx != 0) { + if (p_num == DFS_MAX_SEQ_NUM) { + if (c_num != 0) + bb_dfs->n_seq_flag = true; + } else { + if (ABS_8(c_num - p_num) > 1) + bb_dfs->n_seq_flag = true; + } + } + + if (bb_dfs->dbg_prnt_en) { + if (bb_dfs->n_seq_flag) + BB_DBG(bb, DBG_DFS, "[cur_seq_num, pre_seq_num] = [%d, %d]\n", + c_num, p_num); + } + + bb_dfs->lst_seq_num = c_num; +} + +void halbb_radar_ptrn_cmprn(struct bb_info *bb, u16 dfs_rpt_idx, + u8 pri, u16 pw, bool chrp_flag) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + u8 j = 0, pw_lbd = 0, pri_lbd = 0, pri_ubd = 0; + u16 pw_ubd = 0; + u8 pw_factor = 0,pri_factor = 0; + + if (bb_dfs->l_rdr_exst_flag) + halbb_radar_chrp_mntr(bb, chrp_flag); + + if (!bb_dfs->idle_flag ){ + pw_factor = PW_FTR ; + pri_factor = PRI_FTR; + } + else { + pw_factor = PW_FTR_IDLE; + pri_factor = PRI_FTR_IDLE; + + } + + for (j = 0; j < DFS_RDR_TYP_NUM ; j++) { + pw_lbd = (bb_dfs->pw_min_tab[j] * (8 - pw_factor) >> 3); + pw_ubd = (bb_dfs->pw_max_tab[j] * (8 + pw_factor) >> 3); + pri_lbd = (bb_dfs->pri_min_tab[j] * (8 - pri_factor) >> 3); + if ((bb_dfs->pri_max_tab[j] * (8 + pri_factor) >> 3) <= 0xDC) + pri_ubd = (bb_dfs->pri_max_tab[j] * (8 + pri_factor) >> 3); + else + pri_ubd = 0xDC; + + if (bb_dfs->is_mic_w53) { + if (j < 2) { + if ((pw_lbd <= pw) && (pw_ubd >= pw) && + (pri_lbd <= pri) && (pri_ubd >= pri)) + bb_dfs->srt_rdr_cnt[j]++; + } else if (j < 4) { + if ((pw_lbd <= pw) && (pw_ubd >= pw)) { + if (bb_dfs->pw_tmp >= 100 && + bb_dfs->pw_tmp <= 550 && + ABS_16(pw - bb_dfs->pw_tmp) >= 15 && + pri + bb_dfs->pri_tmp >= pri_lbd && + pri + bb_dfs->pri_tmp <= pri_ubd) + bb_dfs->srt_rdr_cnt[j]++; + } + } else { + if ((pw_lbd <= pw) && (pw_ubd >= pw)) { + if (bb_dfs->pw_tmp >= 150 && + bb_dfs->pw_tmp <= 160 && + pri + bb_dfs->pri_tmp >= pri_lbd && + pri + bb_dfs->pri_tmp <= pri_ubd) + bb_dfs->srt_rdr_cnt[j]++; + } + } + } else { + if ((j == DFS_L_RDR_IDX) && (bb_dfs->l_rdr_exst_flag)) { + if ((pw_lbd <= pw) && (pw_ubd >= pw)) + bb_dfs->lng_rdr_cnt++; + } else { + if ((pw_lbd <= pw) && (pw_ubd >= pw) && + (pri_lbd <= pri) && (pri_ubd >= pri)) + bb_dfs->srt_rdr_cnt[j]++; + } + } + + if (dfs_rpt_idx == 0) { + if (bb_dfs->dbg_prnt_en) { + BB_DBG(bb, DBG_DFS, "pw_factor = %d, pri_factor = %d\n", pw_factor,pri_factor); + BB_DBG(bb, DBG_DFS, "Type %d: [pw_lbd-pw_ubd], [pri_lbd-pri_ubd] = [%d-%d], [%d-%d]\n", + (j + 1), pw_lbd, pw_ubd, pri_lbd, pri_ubd); + } + } + bb_dfs->pw_lbd[j] = pw_lbd; + bb_dfs->pw_ubd[j] = pw_ubd; + bb_dfs->pri_lbd[j] = pri_lbd; + bb_dfs->pri_ubd[j] = pri_ubd; + } + + if (chrp_flag) + bb_dfs->chrp_cnt++; + + bb_dfs->pri_tmp = pri; + bb_dfs->pw_tmp = pw; +} + +void halbb_radar_info_processing(struct bb_info *bb, + struct hal_dfs_rpt *rpt, u16 dfs_rpt_idx) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + struct bb_rdr_info *dfs_rdr_info = NULL; + + u8 pri = 0, cur_seq_num = 0, pre_seq_num = 0; + u16 pw = 0; + bool chrp_flag = false; + + dfs_rdr_info = (struct bb_rdr_info *)rpt->dfs_ptr; + cur_seq_num = dfs_rdr_info->rdr_info_seq; + pre_seq_num = bb_dfs->lst_seq_num; + + if (rpt->phy_idx == HW_PHY_0) { + pw = (dfs_rdr_info->rdr_info_sg0_pw_m << 7) | + (dfs_rdr_info->rdr_info_sg0_pw_l); + pri = (dfs_rdr_info->rdr_info_sg0_pri_m << 7) | + (dfs_rdr_info->rdr_info_sg0_pri_l); + chrp_flag = dfs_rdr_info->rdr_info_sg0_chirp_flag; + } else if (rpt->phy_idx == HW_PHY_1) { + pw = (dfs_rdr_info->rdr_info_sg1_pw_m << 4) | + (dfs_rdr_info->rdr_info_sg1_pw_l); + pri = (dfs_rdr_info->rdr_info_sg1_pri_m << 4) | + (dfs_rdr_info->rdr_info_sg1_pri_l); + chrp_flag = dfs_rdr_info->rdr_info_sg1_chirp_flag; + } + + halbb_radar_ptrn_cmprn(bb, dfs_rpt_idx, pri, pw, chrp_flag); + halbb_radar_seq_inspctn(bb, dfs_rpt_idx, cur_seq_num, pre_seq_num); + + if (bb_dfs->dbg_prnt_en) + BB_DBG(bb, DBG_DFS, "DFS_RPT: [pw, pri, c_flag] = [%d, %d, %d]\n", + pw, pri, chrp_flag); + + if (dfs_rpt_idx == (rpt->dfs_num - 1)) { + if (bb_dfs->dbg_prnt_en) { + BB_DBG(bb, DBG_DFS, "\n"); + BB_DBG(bb, DBG_DFS, "lng_rdr_cnt = %d\n", bb_dfs->lng_rdr_cnt); + BB_DBG(bb, DBG_DFS, "srt_rdr_cnt = [%d, %d, %d, %d, %d, %d, %d, %d]\n", + bb_dfs->srt_rdr_cnt[0], bb_dfs->srt_rdr_cnt[1], + bb_dfs->srt_rdr_cnt[2], bb_dfs->srt_rdr_cnt[3], + bb_dfs->srt_rdr_cnt[4], bb_dfs->srt_rdr_cnt[5], + bb_dfs->srt_rdr_cnt[6], bb_dfs->srt_rdr_cnt[7]); + BB_DBG(bb, DBG_DFS, "\n"); + } + } + + if (pri == 0) + bb_dfs->n_cnfd_lvl++; + if (bb_dfs->n_cnfd_lvl > bb_dfs->dfs_n_cnfd_lvl_th) + bb_dfs->n_cnfd_flag = true; + + bb_dfs->pw_rpt[dfs_rpt_idx] = pw; + bb_dfs->pri_rpt[dfs_rpt_idx] = pri; + bb_dfs->chrp_rpt[dfs_rpt_idx] = chrp_flag; + + rpt->dfs_ptr += DFS_RPT_LENGTH; + + /* BB_DBG(bb, DBG_DFS, "dfs_ptr = %p\n", rpt->dfs_ptr); */ +} + +bool halbb_radar_detect(struct bb_info *bb, struct hal_dfs_rpt *dfs_rpt) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + + bool rdr_detected = false; + u8 ppb_typ_th; + u16 i = 0; + + if (bb_dfs->ppb_prcnt == DFS_PPB_ADPTV_PRCNT){ + if (bb_dfs->dbg_prnt_en) + BB_DBG(bb, DBG_DFS, "Enable NHM-aided DFS!\n"); + return rdr_detected; + } + + if (!(bb->support_ability & BB_DFS)) { + BB_DBG(bb, DBG_DFS, "Not support DFS function!\n"); + return false; + } + + if (!(bb_dfs->l_rdr_exst_flag)) { + /* Check Fake DFS rpt */ + if (dfs_rpt->dfs_num < bb_dfs->fk_dfs_num_th) { + if (bb_dfs->dbg_prnt_en) { + BB_DBG(bb, DBG_DFS, "Non-existent form of DFS!\n"); + BB_DBG(bb, DBG_DFS, "\n"); + } + return false; + } + } + + + if (bb_dfs->dbg_prnt_en) { + BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__); + BB_DBG(bb, DBG_DFS, "phy_idx = %d, dfs_num = %d\n", + dfs_rpt->phy_idx, dfs_rpt->dfs_num); + } + + /* DFS Info Parsing/Processing*/ + for (i = 0; i < (dfs_rpt->dfs_num) ; i++) + halbb_radar_info_processing(bb, dfs_rpt, i); + + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + ppb_typ_th = ((bb_dfs->ppb_tab[i] * bb_dfs->ppb_prcnt) >> 3); + if ((i == DFS_L_RDR_IDX) && (bb_dfs->l_rdr_exst_flag)) { + if ((bb_dfs->lng_rdr_cnt >= ppb_typ_th) && + (bb_dfs->chrp_cnt >= bb_dfs->chrp_th)) { + rdr_detected = true; + BB_DBG(bb, DBG_DFS, "Chrp Rdr Appeared!\n"); + BB_DBG(bb, DBG_DFS, "Long Rdr reaches threshold (ppb_th:%d / chirp_th:%d)!\n", + ppb_typ_th,bb_dfs->chrp_th); + } + } else { + if (bb_dfs->srt_rdr_cnt[i] >= ppb_typ_th) { + if (bb_dfs->n_seq_flag) { + rdr_detected = false; + BB_DBG(bb, DBG_DFS, "Non-sequential DFS Dropped!\n"); + } else if (bb_dfs->n_cnfd_flag) { + rdr_detected = false; + BB_DBG(bb, DBG_DFS, "Non-confidential DFS Blocked!\n"); + } else { + rdr_detected = true; + BB_DBG(bb, DBG_DFS, "Rdr Type %d reaches threshold (ppb_th:%d)!\n", + (i+1), ppb_typ_th); + } + } + } + } + + /* Debug Mode */ + if (rdr_detected) { + if (!(bb_dfs->dbg_prnt_en)) { + BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__); + BB_DBG(bb, DBG_DFS, "phy_idx = %d, dfs_num = %d\n", + dfs_rpt->phy_idx, dfs_rpt->dfs_num); + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) { + BB_DBG(bb, DBG_DFS, "Type %d: [pw_lbd-pw_ubd], [pri_lbd-pri_ubd] = [%d-%d], [%d-%d]\n", + (i+1), bb_dfs->pw_lbd[i], + bb_dfs->pw_ubd[i], bb_dfs->pri_lbd[i], + bb_dfs->pri_ubd[i]); + } + for (i = 0; i < dfs_rpt->dfs_num ; i++) { + BB_DBG(bb, DBG_DFS, "DFS_RPT %d: [pw, pri, c_flag] = [%d, %d, %d]\n", + (i + 1), bb_dfs->pw_rpt[i], bb_dfs->pri_rpt[i], + bb_dfs->chrp_rpt[i]); + } + BB_DBG(bb, DBG_DFS, "lng_rdr_cnt = %d, chrp_cnt = %d\n", bb_dfs->lng_rdr_cnt,bb_dfs->chrp_cnt); + BB_DBG(bb, DBG_DFS, "srt_rdr_cnt = [%d, %d, %d, %d, %d, %d, %d, %d]\n", + bb_dfs->srt_rdr_cnt[0], bb_dfs->srt_rdr_cnt[1], + bb_dfs->srt_rdr_cnt[2], bb_dfs->srt_rdr_cnt[3], + bb_dfs->srt_rdr_cnt[4], bb_dfs->srt_rdr_cnt[5], + bb_dfs->srt_rdr_cnt[6], bb_dfs->srt_rdr_cnt[7]); + } + if (bb_dfs->dfs_dbg_mode) { + rdr_detected = false; + BB_DBG(bb, DBG_DFS, "Radar is detected in DFS debug mode!\n"); + } + } + + /* SW Trigger Mode */ + if (bb_dfs->dfs_sw_trgr_mode) { + rdr_detected = true; + BB_DBG(bb, DBG_DFS, "[HALBB] Radar SW-Trigger Mode!\n"); + } + + /* Reset SW Counter/Flag */ + bb_dfs->n_seq_flag = false; + bb_dfs->n_cnfd_flag = false; + bb_dfs->n_cnfd_lvl = 0; + for (i = 0; i < DFS_RDR_TYP_NUM ; i++) + bb_dfs->srt_rdr_cnt[i] = 0; + for (i = 0; i < dfs_rpt->dfs_num ; i++) { + bb_dfs->pw_rpt[i] = 0; + bb_dfs->pri_rpt[i] = 0; + bb_dfs->chrp_rpt[i] = 0; + } + + return rdr_detected; +} + +void halbb_dfs_dyn_setting(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + struct bb_link_info *link = &bb->bb_link_i; + struct bb_env_mntr_info *env_mntr = &bb->bb_env_mntr_i; +#ifdef HALBB_STATISTICS_SUPPORT + struct bb_stat_info *stat = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat->bb_fa_i; +#endif + + if (link->total_tp < bb_dfs->dfs_tp_th) + bb_dfs->idle_flag = true; + else + bb_dfs->idle_flag = false; + + if ((env_mntr->nhm_idle_ratio > bb_dfs->dfs_idle_prd_th) && + (fa->cnt_fail_all < bb_dfs->dfs_fa_th) && + (env_mntr->nhm_ratio < bb_dfs->dfs_nhm_th)) { + if (bb_dfs->idle_flag) + bb_dfs->ppb_prcnt = DFS_PPB_IDLE_PRCNT; + else + bb_dfs->ppb_prcnt = DFS_PPB_PRCNT; + BB_DBG(bb, DBG_DFS, "[DFS Status] Normal DFS Mode\n"); + } else { + bb_dfs->ppb_prcnt = DFS_PPB_ADPTV_PRCNT; + BB_DBG(bb, DBG_DFS, "[DFS Status] Adaptive DFS Mode\n"); + } + + BB_DBG(bb, DBG_DFS, "[T_TP / I_RTO / FA_CNT / N_RTO] = [%d, %d, %d, %d]\n", + link->total_tp, env_mntr->nhm_idle_ratio, + fa->cnt_fail_all, env_mntr->nhm_ratio); +} + +void halbb_dfs_debug(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{1} Set DFS_SW_TRGR_MODE => {0}: Disable, {1}: Enable\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{2} Set DFS_DBG_MODE => {0}: Disable, {1}: Enable\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{3} Set DBG_PRINT => {0}: Disable, {1}: Enable\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{4} Set DYN_SETTING_EN => {0}: Disable, {1}: Enable\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{5} Set Detection Parameter => \n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{1} Set the threshold of fake DFS number => {Num}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{2} Set the threshold of chirp number => {Num}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{3} Set the threshold of ppb percent => {Percent: 1-8}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{4} Set the threshold of DFS_TP Threshold => {Mbps}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{5} Set the threshold of DFS_Idle_Period Threshold => {Percent: 0-100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{6} Set the threshold of DFS_FA Threshold => {Num}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{7} Set the threshold of DFS_NHM Threshold => {Percent: 0-100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---{8} Set the threshold of DFS_N_CNFD_Level Threshold => {Num}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{100} Show all parameter\n"); + } else if (var[0] == 100) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS Region Domain: %s\n", + (bb_dfs->dfs_rgn_domain > 1) ? + (bb_dfs->dfs_rgn_domain > 2) ? + "ETSI": "MIC" : "FCC"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_SW_TRGR_MODE = %d\n", + bb_dfs->dfs_sw_trgr_mode); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_DBG_MODE = %d\n", + bb_dfs->dfs_dbg_mode); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DBG_PRINT = %d\n", + bb_dfs->dbg_prnt_en); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DYN_SETTING_EN = %d\n", + bb_dfs->dfs_dyn_setting_en); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "Fake DFS Num Threshold = %d\n", + bb_dfs->fk_dfs_num_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "Chirp Number = %d\n", + bb_dfs->chrp_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "PPB Percent = %d\n", + bb_dfs->ppb_prcnt); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_TP Threshold = %d\n", + bb_dfs->dfs_tp_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_Idle_Period Threshold = %d\n", + bb_dfs->dfs_idle_prd_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_FA Threshold = %d\n", + bb_dfs->dfs_fa_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_NHM Threshold = %d\n", + bb_dfs->dfs_nhm_th); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_N_CNFD_Level Threshold = %d\n", + bb_dfs->dfs_n_cnfd_lvl_th); + } else { + if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dfs->dfs_sw_trgr_mode = (bool)var[1]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "DFS_SW_TRGR_MODE = %d\n", + bb_dfs->dfs_sw_trgr_mode); + } else if (var[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dfs->dfs_dbg_mode = (bool)var[1]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "DFS_DBG_MODE = %d\n", + bb_dfs->dfs_dbg_mode); + } else if (var[0] == 3) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dfs->dbg_prnt_en = (bool)var[1]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "DBG_PRINT = %d\n", + bb_dfs->dbg_prnt_en); + } else if (var[0] == 4) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dfs->dfs_dyn_setting_en = (bool)var[1]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "DYN_SETTING_EN = %d\n", + bb_dfs->dfs_dyn_setting_en); + } else if (var[0] == 5) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + if (var[1] == 1) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->fk_dfs_num_th = (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "fk_dfs_num_th = %d\n", + bb_dfs->fk_dfs_num_th); + } else if (var[1] == 2) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->chrp_th= (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "chrp_th = %d\n", + bb_dfs->chrp_th); + } else if (var[1] == 3) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->ppb_prcnt = (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ppb_prcnt = %d\n", + bb_dfs->ppb_prcnt); + } else if (var[1] == 4) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->dfs_tp_th = (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "dfs_tp_th = %d\n", + bb_dfs->dfs_tp_th); + } else if (var[1] == 5) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->dfs_idle_prd_th = (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "dfs_idle_prd_th = %d\n", + bb_dfs->dfs_idle_prd_th); + } else if (var[1] == 6) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->dfs_fa_th= (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "dfs_fa_th = %d\n", + bb_dfs->dfs_fa_th); + } else if (var[1] == 7) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->dfs_nhm_th= (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "dfs_nhm_th = %d\n", + bb_dfs->dfs_nhm_th); + } else if (var[1] == 8) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + bb_dfs->dfs_n_cnfd_lvl_th= (u8)var[2]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "dfs_n_cnfd_lvl_th = %d\n", + bb_dfs->dfs_n_cnfd_lvl_th); + } + } + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_cr_cfg_dfs_init(struct bb_info *bb) +{ + struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i; + struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i; + + switch (bb->cr_type) { + +#ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + /*cr->dfs_en = DFS_EN_52AA; + cr->dfs_en_m = DFS_EN_52AA_M; + */ + break; +#endif +#ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->dfs_en = DFS_EN_A; + cr->dfs_en_m = DFS_EN_A_M; + break; +#endif +#ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->dfs_en = DFS_EN_C; + cr->dfs_en_m = DFS_EN_C_M; + break; +#endif + default: + break; + } +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dfs.h b/phl/hal_g6/phy/bb/halbb_dfs.h new file mode 100644 index 0000000..72e5d89 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dfs.h @@ -0,0 +1,173 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DFS_H__ +#define __HALBB_DFS_H__ +/*@--------------------------[Define] ---------------------------------------*/ +#define DFS_RPT_LENGTH 8 +#define DFS_RDR_TYP_NUM 8 +#define DFS_L_RDR_IDX 6 +#define PW_FTR_IDLE 1 +#define PRI_FTR_IDLE 1 +#define PW_FTR 3 +#define PRI_FTR 3 +#define DFS_PPB_PRCNT 4 +#define DFS_PPB_IDLE_PRCNT 5 +#define DFS_PPB_ADPTV_PRCNT 8 +#define DFS_CHIRP_TH 3 +#define DFS_FCC_LP_LNGTH 12 /*Real Waveform length of FCC-LP is 12 secs*/ +#define DFS_MAX_SEQ_NUM 127 +/*@--------------------------[Enum]------------------------------------------*/ +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_dfs_cr_info { + u32 dfs_en; + u32 dfs_en_m; +}; + +struct bb_dfs_info { + struct bb_dfs_cr_info bb_dfs_cr_i; + u8 dfs_rgn_domain; + u8 ppb_prcnt; + u16 pw_rpt[DFS_MAX_SEQ_NUM]; + u8 pri_rpt[DFS_MAX_SEQ_NUM]; + bool chrp_rpt[DFS_MAX_SEQ_NUM]; + u8 chrp_cnt; + u8 chrp_th; + u32 chrp_srt_t; + u8 n_cnfd_lvl; + u8 lng_rdr_cnt; + u8 srt_rdr_cnt[DFS_RDR_TYP_NUM]; + u8 pw_lbd[DFS_RDR_TYP_NUM]; + u16 pw_ubd[DFS_RDR_TYP_NUM]; + u8 pri_lbd[DFS_RDR_TYP_NUM]; + u8 pri_ubd[DFS_RDR_TYP_NUM]; + u8 pw_min_tab[DFS_RDR_TYP_NUM]; + u16 pw_max_tab[DFS_RDR_TYP_NUM]; + u8 pri_min_tab[DFS_RDR_TYP_NUM]; + u8 pri_max_tab[DFS_RDR_TYP_NUM]; + u8 ppb_tab[DFS_RDR_TYP_NUM]; + u8 lst_seq_num; + u8 pri_tmp; + u16 pw_tmp; + bool is_mic_w53; + bool is_mic_w56; + bool l_rdr_exst_flag; + bool chrp_obsrv_flag; + bool n_cnfd_flag; + bool n_seq_flag; + bool idle_flag; + + bool dfs_sw_trgr_mode; + bool dfs_dbg_mode; + bool dbg_prnt_en; + u8 fk_dfs_num_th; + u8 dfs_tp_th; + u8 dfs_idle_prd_th; + u8 dfs_fa_th; + u8 dfs_nhm_th; + u8 dfs_n_cnfd_lvl_th; + + bool dfs_dyn_setting_en; +}; + +struct bb_dfs_rpt { + u8 *dfs_ptr; + u16 dfs_num; + u8 phy_idx; /*phy0,phy1*/ +}; + +#if (PLATFOM_IS_LITTLE_ENDIAN) +struct bb_rdr_info { + u8 rdr_info_sg0_chirp_flag:1; /*[18:9],[8:1],[0]*/ + u8 rdr_info_sg0_pri_l:7; + + u8 rdr_info_sg0_pri_m:1; + u8 rdr_info_sg0_pw_l:7; + + u8 rdr_info_sg0_pw_m:3; + u8 rdr_info_sg1_chirp_flag:1; /*[37:28],[27:20],[19]*/ + u8 rdr_info_sg1_pri_l:4; + + u8 rdr_info_sg1_pri_m:4; + u8 rdr_info_sg1_pw_l:4; + + u8 rdr_info_sg1_pw_m:6; + u8 rdr_info_zw_chirp_flag:1; /*[56:47],[46:39],[38]*/ + u8 rdr_info_zw_pri_l:1; + + u8 rdr_info_zw_pri_m:7; + u8 rdr_info_zw_pw_l:1; + + u8 rdr_info_zw_pw_m; + + u8 rdr_info_zw_pw_h:1; + u8 rdr_info_seq:7; +}; +#else +struct bb_rdr_info { + u8 rdr_info_sg0_pri_l:7; + u8 rdr_info_sg0_chirp_flag:1; + + u8 rdr_info_sg0_pw_l:7; + u8 rdr_info_sg0_pri_m:1; + + u8 rdr_info_sg1_pri_l:4; + u8 rdr_info_sg1_chirp_flag:1; + u8 rdr_info_sg0_pw_m:3; + + u8 rdr_info_sg1_pw_l:4; + u8 rdr_info_sg1_pri_m:4; + + u8 rdr_info_zw_pri_l:1; + u8 rdr_info_zw_chirp_flag:1; + u8 rdr_info_sg1_pw_m:6; + + u8 rdr_info_zw_pw_l:1; + u8 rdr_info_zw_pri_m:7; + + u8 rdr_info_zw_pw_m; + + u8 rdr_info_seq:7; + u8 rdr_info_zw_pw_h:1; +}; +#endif +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +struct hal_dfs_rpt; +void halbb_dfs(struct bb_info *bb); +void halbb_dfs_rgn_dmn_dflt_cnfg(struct bb_info *bb); +void halbb_dfs_rgn_dmn_cnfg_by_ch(struct bb_info *bb, bool w53_band, + bool w56_band); +void halbb_radar_chrp_mntr(struct bb_info *bb, bool chrp_flag); +void halbb_radar_seq_inspctn(struct bb_info *bb, u16 dfs_rpt_idx, + u8 c_num, u8 p_num); +void halbb_radar_ptrn_cmprn(struct bb_info *bb, u16 dfs_rpt_idx, + u8 pri, u16 pw, bool chrp_flag); +void halbb_radar_info_processing(struct bb_info *bb, + struct hal_dfs_rpt *dfs_rpt, u16 dfs_rpt_idx); +void halbb_dfs_dyn_setting(struct bb_info *bb); +void halbb_dfs_debug(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_dfs_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dfs_ex.h b/phl/hal_g6/phy/bb/halbb_dfs_ex.h new file mode 100644 index 0000000..7f7ca47 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dfs_ex.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DFS_EX_H__ +#define __HALBB_DFS_EX_H__ +/*@--------------------------[Define] ---------------------------------------*/ +/*@--------------------------[Enum]------------------------------------------*/ +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_info; +struct hal_dfs_rpt; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_dfs_init(struct bb_info *bb); +void halbb_radar_detect_reset(struct bb_info *bb); +void halbb_radar_detect_disable(struct bb_info *bb); +void halbb_radar_detect_enable(struct bb_info *bb); +bool halbb_is_dfs_band(struct bb_info *bb, u8 ch, u8 pri_ch); +bool halbb_radar_detect(struct bb_info *bb, struct hal_dfs_rpt *rpt); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_dig.c b/phl/hal_g6/phy/bb/halbb_dig.c new file mode 100644 index 0000000..7a14004 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dig.c @@ -0,0 +1,2474 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_DIG_SUPPORT + +#ifdef BB_8852A_2_SUPPORT +u8 halbb_lna_idx_by_rssi(struct bb_info *bb, u8 rssi) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + u8 lna_idx = LNA_IDX_MAX; + + if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[0]) + lna_idx = 6; + else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[1]) + lna_idx = 5; + else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[2]) + lna_idx = 4; + else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[3]) + lna_idx = 3; + else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[4]) + lna_idx = 2; + else + lna_idx = 1; + + return lna_idx; +} + +u8 halbb_tia_idx_by_rssi(struct bb_info *bb, u8 rssi) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + u8 tia_idx = TIA_IDX_MAX; + + if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[0]) + tia_idx = 1; + else + tia_idx = 0; + + return tia_idx; +} + +u8 halbb_rxb_idx_by_rssi(struct bb_info *bb, + struct agc_gaincode_set *set, u8 rssi) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + u8 rxb_idx = RXB_IDX_MAX; + s8 lna_gain = bb_dig->lna_gain[set->lna_idx]; + s8 tia_gain = bb_dig->tia_gain[set->tia_idx]; + s32 rxb_idx_tmp = RXB_IDX_MAX; + s32 wb_rssi = rssi + lna_gain + tia_gain; + + rxb_idx_tmp = (bb_dig->ib_pkpwr - bb_dig->ib_pbk + 110) - wb_rssi + 10; + + if (rxb_idx_tmp > RXB_IDX_MAX) + rxb_idx = RXB_IDX_MAX; + else if (rxb_idx_tmp < RXB_IDX_MIN) + rxb_idx = RXB_IDX_MIN; + else + rxb_idx = (u8)rxb_idx_tmp; + + BB_DIG_DBG(bb, DIG_DBG_LV2, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", + wb_rssi, rxb_idx_tmp); + + return rxb_idx; +} + + +void halbb_dig_set_igi_cr_8852a(struct bb_info *bb, const struct agc_gaincode_set set) +{ + if (bb->ic_type != BB_RTL8852A) + return; + + halbb_set_igi_8852a_2(bb, set.lna_idx, set.tia_idx, set.rxb_idx, RF_PATH_A); + halbb_set_igi_8852a_2(bb, set.lna_idx, set.tia_idx, set.rxb_idx, RF_PATH_B); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", + set.lna_idx, set.tia_idx, set.rxb_idx); +} + +void halbb_dig_agc_update_8852a(struct bb_info *bb, struct bb_dig_op_para_unit *para) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + u8 igi_rssi_th_ifem[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; + u8 igi_rssi_th_efem[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; + u8 *igi_rssi_th; + + + if (bb->ic_type != BB_RTL8852A) + return; + + /* gain para update */ + bb_dig->lna_gain = bb_dig->lna_gain_g; + bb_dig->tia_gain = bb_dig->tia_gain_g; + + /* igi rssi th update */ + switch (bb->phl_com->dev_cap.rfe_type) { + case 51: + case 52: + case 53: + case 54: + igi_rssi_th = igi_rssi_th_efem; + break; + default: + igi_rssi_th = igi_rssi_th_ifem; + } + + halbb_mem_cpy(bb, ¶->igi_rssi_th, igi_rssi_th, sizeof(u8) * IGI_RSSI_TH_NUM); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "Sigi_rssi_th[4:0] = %d,%d,%d,%d,%d\n", + para->igi_rssi_th[4], para->igi_rssi_th[3], + para->igi_rssi_th[2], para->igi_rssi_th[1], + para->igi_rssi_th[0]); +} + +#if 0 +void halbb_dig_write_igi_8852a(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + + halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode); +} +#endif + +void halbb_gaincode_by_rssi_8852a(struct bb_info *bb, + struct agc_gaincode_set *set, u8 rssi) { + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + if (bb->ic_type != BB_RTL8852A) + return; + + set->lna_idx = halbb_lna_idx_by_rssi(bb, rssi); + set->tia_idx = halbb_tia_idx_by_rssi(bb, rssi); + set->rxb_idx = halbb_rxb_idx_by_rssi(bb, set, rssi); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", + rssi, set->lna_idx, set->tia_idx, set->rxb_idx); +} + +bool halbb_dig_gaincode_update_en_8852a(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + struct rtw_hw_band *hw_band = &bb->hal_com->band[bb->bb_phy_idx]; + + if ((bb->ic_type != BB_RTL8852A) || (bb->hal_com->cv >= CCV)) + return false; + + if (hw_band->cur_chandef.band != BAND_ON_24G) + return false; + + halbb_gaincode_by_rssi_8852a(bb, &bb_dig_u->cur_gaincode, bb_dig_u->igi_fa_rssi); + + return true; +} + +#endif + +#ifdef HALBB_DIG_DAMPING_CHK +void halbb_dig_recorder_reset(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i; + + BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__); + + halbb_mem_set(bb, dig_rc, 0, sizeof(struct bb_dig_record_info)); +} + +void halbb_dig_recorder(struct bb_info *bb, u8 igi_curr, u32 fa_metrics) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i; + u8 igi_pre = dig_rc->igi_history[0]; + u8 igi_up = 0; + +// if (!bb->bb_link_i.is_linked) +// return; + + BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__); + +#if 0 + if (bb->bb_link_i.first_connect) { + BB_DBG(bb, DBG_DIG, "first_connect\n"); + halbb_dig_recorder_reset(bb); + dig_rc->igi_history[0] = igi_curr; + dig_rc->fa_history[0] = fa_metrics; + return; + } +#endif + + igi_pre = dig_rc->igi_history[0]; + igi_up = (igi_curr > igi_pre) ? 1 : 0; + dig_rc->igi_bitmap = (dig_rc->igi_bitmap << 1) | igi_up; + + dig_rc->igi_history[5] = dig_rc->igi_history[4]; + dig_rc->igi_history[4] = dig_rc->igi_history[3]; + dig_rc->igi_history[3] = dig_rc->igi_history[2]; + dig_rc->igi_history[2] = dig_rc->igi_history[1]; + dig_rc->igi_history[1] = dig_rc->igi_history[0]; + dig_rc->igi_history[0] = igi_curr; + + dig_rc->fa_history[5] = dig_rc->fa_history[4]; + dig_rc->fa_history[4] = dig_rc->fa_history[3]; + dig_rc->fa_history[3] = dig_rc->fa_history[2]; + dig_rc->fa_history[2] = dig_rc->fa_history[1]; + dig_rc->fa_history[1] = dig_rc->fa_history[0]; + dig_rc->fa_history[0] = fa_metrics; + + BB_DBG(bb, DBG_DIG, "igi_history[5:0] = {%02d, %02d, %02d, %02d, %02d, %02d}\n", + dig_rc->igi_history[5], dig_rc->igi_history[4], dig_rc->igi_history[3], dig_rc->igi_history[2], + dig_rc->igi_history[1], dig_rc->igi_history[0]); + BB_DBG(bb, DBG_DIG, "fa_history[5:0] = {%02d, %02d, %02d, %02d, %02d, %02d}\n", + dig_rc->fa_history[5], dig_rc->fa_history[4], dig_rc->fa_history[3], dig_rc->fa_history[2], + dig_rc->fa_history[1], dig_rc->fa_history[0]); + BB_DBG(bb, DBG_DIG, "igi_bitmap[5:0]=0x%x{ %d, %d, %d, %d, %d, %d}\n", + dig_rc->igi_bitmap, + (dig_rc->igi_bitmap & BIT5) >> 5, + (dig_rc->igi_bitmap & BIT4) >> 4, + (dig_rc->igi_bitmap & BIT3) >> 3, + (dig_rc->igi_bitmap & BIT2) >> 2, + (dig_rc->igi_bitmap & BIT1) >> 1, + dig_rc->igi_bitmap & BIT0); +} + +void halbb_dig_damping_chk(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i; + struct bb_dig_op_unit *bb_dig_u = dig->p_cur_dig_unit; + u8 diff1 = 0, diff2 = 0; + u32 fa_low_th = bb_dig_u->dig_op_para.fa_th[0]; + u32 fa_high_th = bb_dig_u->dig_op_para.fa_th[1]; + u32 fa_high_th2 = bb_dig_u->dig_op_para.fa_th[2]; + u32 fa_high_th3 = bb_dig_u->dig_op_para.fa_th[3]; + bool fa_pattern_match = false; + u32 time_tmp = 0; + + if (!bb->bb_link_i.is_linked) + return; + + BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__); + + /*@== Release Damping ================================================*/ + if (dig_rc->damping_lock_en) { + BB_DBG(bb, DBG_DIG, + "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n", + dig_rc->limit_time, bb->bb_sys_up_time); + + time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD; + + if (DIFF_2(bb->bb_ch_i.rssi_min, dig_rc->limit_rssi) > dig->rls_rssi_diff_th || + time_tmp < bb->bb_sys_up_time) { + dig_rc->damping_lock_en = false; + BB_DBG(bb, DBG_DIG, "[Rls] rssi=%d.%d, limit_rssi=%d.%d, th=%d.%d\n", + bb->bb_ch_i.rssi_min >> 1, + (bb->bb_ch_i.rssi_min & 1) * 5, + dig_rc->limit_rssi >> 1, + (dig_rc->limit_rssi & 1) * 5, + dig->rls_rssi_diff_th >> 1, + (dig->rls_rssi_diff_th & 1) * 5); + } + return; + } + + /*@== Damping Pattern Check===========================================*/ + BB_DBG(bb, DBG_DIG, "fa_th{H2, H2, H1, L}= {%d,%d,%d,%d}\n", + fa_high_th3, fa_high_th2, fa_high_th, fa_low_th); + + if ((dig_rc->igi_bitmap & 0xf) == 0x5) { + BB_DBG(bb, DBG_DIG, "[Type:0] map=0x5\n"); + /*@ 4b'0101 + * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26) + * FA: [3] >high1 ->[2] [1] >high1 ->[0] [new] [2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28) + * FA: [3] >high2 ->[2] [1] >high2 ->[0] [new] igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] > dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] >= fa_high_th && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] >= fa_high_th) { + /*@Check each fa element*/ + fa_pattern_match = true; + } + + } else if ((dig_rc->igi_bitmap & 0x1f) == 0x9) { + BB_DBG(bb, DBG_DIG, "[Type:1] map=0x9\n"); + /*@ 5b'01001 + * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28) + * FA: [3] [2] [1] >high2 ->[0] [new] igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[3] > dig_rc->igi_history[4]) + diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[4]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] >= fa_high_th2 && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] < fa_low_th) { + /*@Check each fa element*/ + fa_pattern_match = true; + } + } else if ((dig_rc->igi_bitmap & 0x3f) == 0x11) { + BB_DBG(bb, DBG_DIG, "[Type:2] map=0x11\n"); + /*@ 6b'010001 + * IGI:[4]up(0x28)->[3]down(0x26)->[2]down(0x24)->[1]down(0x22)->[0]up(0x28)->[new](Lock @ 0x28) + * FA: [4] [3] [2] [1] >high3 ->[0] [new] igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[4] > dig_rc->igi_history[5]) + diff2 = dig_rc->igi_history[4] - dig_rc->igi_history[5]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] >= fa_high_th3 && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] < fa_low_th && + dig_rc->fa_history[4] < fa_low_th) { + /*@Check each fa element*/ + fa_pattern_match = true; + } + } + + if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) { + dig_rc->damping_lock_en = true; + dig_rc->damping_limit_val = dig_rc->igi_history[0]; + dig_rc->limit_time = bb->bb_sys_up_time; + dig_rc->limit_rssi = bb->bb_ch_i.rssi_min; + + BB_DBG(bb, DBG_DIG, + "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n", + dig_rc->damping_limit_val, + dig_rc->limit_time, dig_rc->limit_rssi >> 1); + } + BB_DBG(bb, DBG_DIG, "[lock_en=%d] ptrn_match=%d, diff1=%d, diff2=%d\n", + dig_rc->damping_lock_en, fa_pattern_match, diff1, diff2); +} + +void halbb_dig_damping_chk_init(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i; + + halbb_dig_recorder_reset(bb); + dig->dig_dl_en = true; + dig->rls_rssi_diff_th = 6; /*6 >> 1 = 3dB*/ +} +#endif + +u8 halbb_get_lna_idx(struct bb_info *bb, enum rf_path path) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 lna_idx = LNA_IDX_MAX; + + /*lna initial gain index*/ + switch (path) { + case RF_PATH_A: + lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_lna_init_idx, + cr->path0_lna_init_idx_m, + bb->bb_phy_idx); + break; + case RF_PATH_B: + lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_lna_init_idx, + cr->path1_lna_init_idx_m, + bb->bb_phy_idx); + break; + default: + break; + } + + return lna_idx; +} + +u8 halbb_get_tia_idx(struct bb_info *bb, enum rf_path path) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 tia_idx = TIA_IDX_MAX; + + switch (path) { + case RF_PATH_A: + tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_tia_init_idx, + cr->path0_tia_init_idx_m, + bb->bb_phy_idx); + break; + case RF_PATH_B: + tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_tia_init_idx, + cr->path1_tia_init_idx_m, + bb->bb_phy_idx); + break; + default: + break; + } + + return tia_idx; +} + +u8 halbb_get_rxb_idx(struct bb_info *bb, enum rf_path path) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 rxb_idx = RXB_IDX_MAX; + + switch (path) { + case RF_PATH_A: + rxb_idx = (u8)halbb_get_reg_cmn(bb, + cr->path0_rxb_init_idx, + cr->path0_rxb_init_idx_m, + bb->bb_phy_idx); + break; + case RF_PATH_B: + rxb_idx = (u8)halbb_get_reg_cmn(bb, + cr->path1_rxb_init_idx, + cr->path1_rxb_init_idx_m, + bb->bb_phy_idx); + break; + default: + break; + } + + return rxb_idx; +} + +u8 halbb_igi_by_edcca(struct bb_info *bb, u8 igi) +{ +#ifdef HALBB_EDCCA_SUPPORT + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + const u8 margin = IGI_EDCCA_GAP_LIMIT - 18; /* -128(dBm)+110(RSSI) */ + u8 bound = bb->bb_edcca_i.th_h; + + bound = margin > (EDCCA_MAX - bound) ? EDCCA_MAX : (bound + margin); + if (igi > bound) { + igi = bound; + BB_DIG_DBG(bb, DIG_DBG_LV0, "EDCCA th_h = %d, IGI upper clamp to %d.\n", + bb->bb_edcca_i.th_h, bound); + } +#endif + return igi; +} + +void halbb_dig_noisy_lv_decision(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + struct bb_dig_op_para_unit *para = &bb_dig_u->dig_op_para; + u16 fa_ratio = bb_dig_u->fa_r_avg; + + if (bb_dig_u->fa_valid_state_cnt == 0) { + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV1; + BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_ratio N/A, set noisy_lv=%d\n", DIG_NOISY_LV1); + return; + } + + if (fa_ratio < para->fa_th[0]) + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV0; + else if (fa_ratio < para->fa_th[1]) + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV1; + else if (fa_ratio < para->fa_th[2]) + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV2; + else if (fa_ratio < para->fa_th[3]) + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV3; + else + bb_dig_u->cur_noisy_lv = DIG_NOISY_LV_MAX; + + BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", + para->fa_th[3], para->fa_th[2], para->fa_th[1], para->fa_th[0]); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_avg=%d, noisy_lv=%d\n", + bb_dig_u->fa_r_avg, bb_dig_u->cur_noisy_lv); + + bb_dig_u->fa_valid_state_cnt = 0; +} + +s8 halbb_dig_ofst_by_fa(struct bb_info *bb, u16 fa) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_para_unit *para = &bb_dig->p_cur_dig_unit->dig_op_para; + //enum dig_noisy_level noisy_lv; + s8 ofst = 0; + + if (fa < para->fa_th[0]) { + //noisy_lv = DIG_NOISY_LV0; + ofst = -2; + } else if (fa < para->fa_th[1]) { + //noisy_lv = DIG_NOISY_LV1; + ofst = 0; + } else if (fa < para->fa_th[2]) { + //noisy_lv = DIG_NOISY_LV2; + ofst = 2; + } else if (fa < para->fa_th[3]) { + //noisy_lv = DIG_NOISY_LV3; + ofst = 4; + } else { + //noisy_lv = DIG_NOISY_LV_MAX; + ofst = 6; + } + + BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", + para->fa_th[3], para->fa_th[2], para->fa_th[1], para->fa_th[0]); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "fa=%d, ofst=%d\n", fa, ofst); + + return ofst; +} + +u8 halbb_dig_igi_by_ofst(struct bb_info *bb, u8 igi_pre, s8 ofst) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_op_unit *dig_u = dig->p_cur_dig_unit; + #ifdef HALBB_DIG_DAMPING_CHK + struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i; + #endif + u8 joint_max, joint_min; + u8 dyn_min, dyn_max; + u8 igi_new; + + igi_new = (u8)((s8)igi_pre + ofst); + dyn_min = SUBTRACT_TO_0(dig->igi_rssi, 10); + dyn_max = dyn_min + IGI_OFFSET_MAX; + + #ifdef HALBB_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig->dig_dl_en && + dig_rc->damping_lock_en && + dyn_min < dig_rc->damping_limit_val) { + BB_DBG(bb, DBG_DIG, "[Limit by Damping] Dyn_min=0x%x -> 0x%x\n", + dyn_min, dig_rc->damping_limit_val); + + dyn_min = dig_rc->damping_limit_val; + } + #endif + + joint_max = MIN_2(dyn_max, dig_u->abs_igi_max); + joint_min = MAX_2(dyn_min, dig_u->abs_igi_min); + + if (joint_max >= joint_min) { + /*Check IGI exceed the max/in boundary or not*/ + if (igi_new > joint_max) + igi_new = joint_max; + else if (igi_new < joint_min) + igi_new = joint_min; + } else { + igi_new = joint_max; + } + + BB_DIG_DBG(bb, DIG_DBG_LV0, + "rssi=%02d, dyn(max,min)=(%d,%d), abs(max,min)=(%d,%d), Joint(max,min)=(%d,%d), igi=%d\n", + dig->igi_rssi, + dyn_max, dyn_min, + dig_u->abs_igi_max, dig_u->abs_igi_min, + joint_max, joint_min, + igi_new); + + return igi_new; +} + +void halbb_dig_igi_ofst_by_env(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + u8 fa_rssi_ofst_pre = bb_dig_u->fa_rssi_ofst; + + switch (bb_dig_u->cur_noisy_lv) { + case DIG_NOISY_LV0: + if (bb_dig_u->fa_rssi_ofst < 2) + bb_dig_u->fa_rssi_ofst = 0; + else + bb_dig_u->fa_rssi_ofst -= 2; + break; + case DIG_NOISY_LV2: + bb_dig_u->fa_rssi_ofst += 2; + break; + case DIG_NOISY_LV3: + bb_dig_u->fa_rssi_ofst += 4; + break; + case DIG_NOISY_LV_MAX: + bb_dig_u->fa_rssi_ofst += 6; + break; + default: + break; + } + + if (bb_dig_u->fa_rssi_ofst > IGI_OFFSET_MAX) + bb_dig_u->fa_rssi_ofst = IGI_OFFSET_MAX; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[noisy_lv=%d] ofst: %d -> %d (max: %d)\n", + bb_dig_u->cur_noisy_lv, fa_rssi_ofst_pre, bb_dig_u->fa_rssi_ofst, IGI_OFFSET_MAX); +} + +u8 halbb_dig_igi_bound_decision(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + #ifdef HALBB_DIG_DAMPING_CHK + struct bb_dig_record_info *dig_rc = &bb_dig->bb_dig_record_i; + #endif + u8 tmp_max_bound = bb_dig_u->abs_igi_max; + u8 tmp_min_bound = bb_dig_u->abs_igi_min; + u8 igi_new; + + if (bb_dig->igi_rssi < 10) + bb_dig_u->dyn_igi_min = 0; + else + bb_dig_u->dyn_igi_min = bb_dig->igi_rssi - 10; + + bb_dig_u->dyn_igi_max = bb_dig_u->dyn_igi_min + IGI_OFFSET_MAX; + igi_new = bb_dig_u->dyn_igi_min + bb_dig_u->fa_rssi_ofst; + + #ifdef HALBB_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (bb_dig->dig_dl_en && + dig_rc->damping_lock_en && + bb_dig_u->dyn_igi_min < dig_rc->damping_limit_val) { + BB_DBG(bb, DBG_DIG, + "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n", + bb_dig_u->dyn_igi_min, dig_rc->damping_limit_val); + + bb_dig_u->dyn_igi_min = dig_rc->damping_limit_val; + } + #endif + + tmp_max_bound = MIN_2(bb_dig_u->dyn_igi_max, tmp_max_bound); + tmp_min_bound = MAX_2(bb_dig_u->dyn_igi_min, tmp_min_bound); + + if (igi_new > tmp_max_bound) + igi_new = tmp_max_bound; + else if (igi_new < tmp_min_bound) + igi_new = tmp_min_bound; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi_min=%02d, dyn(max,min)=(%d,%d), abs(max,min)=(%d,%d), igi=%d\n", + bb_dig->igi_rssi, + bb_dig_u->dyn_igi_max, bb_dig_u->dyn_igi_min, + bb_dig_u->abs_igi_max, bb_dig_u->abs_igi_min, + igi_new); + + return igi_new; +} + +bool halbb_dig_ifs_clm_trig(struct bb_info *bb, u16 mntr_time) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + bool is_trig_success = false; +#ifdef HALBB_ENV_MNTR_SUPPORT + struct env_trig_rpt rpt = {0}; + + /* trigger env_mntr_rpt */ + bb_dig->ccx_para_i.mntr_time = mntr_time - 15; + if (halbb_env_mntr_trigger(bb, &bb_dig->ccx_para_i, &rpt) + & IFS_CLM_SUCCESS) { + BB_DIG_DBG(bb, DIG_DBG_LV2, "ifs_clm trigger ok, timestamp %d, mntr_time %d ms.\n", + rpt.ccx_rpt_stamp, bb_dig->ccx_para_i.mntr_time); + bb_dig->ccx_timestamp = rpt.ccx_rpt_stamp; + bb_dig->ccx_is_triggered = true; + is_trig_success = true; + } else { + BB_DIG_DBG(bb, DIG_DBG_LV1, "ifs_clm trigger fail.\n"); + } +#endif + return is_trig_success; +} + +bool halbb_dig_ifs_clm_latch(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_op_unit *dig_u = dig->p_cur_dig_unit; +#ifdef HALBB_ENV_MNTR_SUPPORT + struct env_mntr_rpt rpt = {0}; + u8 ifs_clm_rpt = halbb_env_mntr_result(bb, &rpt) & IFS_CLM_SUCCESS; + + /* get env_mntr_rpt and accumulate */ + if (!dig->ccx_is_triggered) { + BB_DIG_DBG(bb, DIG_DBG_LV1, "[Latch Err] DIG not trigger.\n"); + return false; + } else { + dig->ccx_is_triggered = false; + } + + if (ifs_clm_rpt == 0) { + BB_DIG_DBG(bb, DIG_DBG_LV1, "[Latch Err] FA rpt not valid.\n"); + return false; + } + + if (dig->ccx_timestamp != rpt.ccx_rpt_stamp) { + BB_DIG_DBG(bb, DIG_DBG_LV1, "[Stamp Err] %d, mine: %d.\n", + rpt.ccx_rpt_stamp, dig->ccx_timestamp); + return false; + } + + dig_u->fa_r_acc += (rpt.ifs_clm_ofdm_fa_permil + rpt.ifs_clm_cck_fa_permil); + dig_u->fa_valid_state_cnt++; + + BB_DIG_DBG(bb, DIG_DBG_LV2, "[FA] CCK(%d) + OFDM(%d) = ALL(%d)\n", + rpt.ifs_clm_cck_fa_permil, rpt.ifs_clm_ofdm_fa_permil, + rpt.ifs_clm_cck_fa_permil + rpt.ifs_clm_ofdm_fa_permil); + + BB_DIG_DBG(bb, DIG_DBG_LV2, "[FA] acc: %d, cnt: %d\n", + dig_u->fa_r_acc, dig_u->fa_valid_state_cnt); + +#endif + return true; +} + +void halbb_sdagc_follow_pagc_config(struct bb_info *bb, bool set_en) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u32 val = (set_en) ? 1 : 0; + u8 i = 0; + + if (bb_dig->p_cur_dig_unit->sdagc_follow_pagc_en == set_en) + return; + + bb_dig->p_cur_dig_unit->sdagc_follow_pagc_en = set_en; + + halbb_set_reg_cmn(bb, cr->path0_p20_follow_by_pagcugc_en_a, + cr->path0_p20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx); + halbb_set_reg_cmn(bb, cr->path0_s20_follow_by_pagcugc_en_a, + cr->path0_s20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx); + halbb_set_reg_cmn(bb, cr->path1_p20_follow_by_pagcugc_en_a, + cr->path1_p20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx); + halbb_set_reg_cmn(bb, cr->path1_s20_follow_by_pagcugc_en_a, + cr->path1_s20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "sdagc_follow_pagc=%d\n", val); +} + +void halbb_dyn_pd_th_cck(struct bb_info *bb, u8 rssi, bool set_en) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 pd_dyn_max = bb_dig->igi_rssi + 5; /* PD_low upper bound */ + u8 margin = bb_dig_u->pd_low_th_ofst; /* backoff of CCA ability */ + u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0; + enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw; + + BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__); + + rssi = MIN_2(rssi, pd_dyn_max); + rssi -= MIN_2(rssi, margin); + + if(!set_en) { + halbb_set_pd_lower_bound_cck(bb, RSSI_MIN, cbw, bb->bb_phy_idx); + BB_DIG_DBG(bb, DIG_DBG_LV0, "Dynamic CCK PD th dsiabled\n"); + } else { + if(!halbb_set_pd_lower_bound_cck(bb, RSSI_MAX - rssi, cbw, + bb->bb_phy_idx)) + BB_DIG_DBG(bb, DIG_DBG_LV0, "CCK PD th set warning.\n"); + else + BB_DIG_DBG(bb, DIG_DBG_LV1, "dyn_max=%d, backoff=%d, pd_th=%d(-%ddBm)\n", + pd_dyn_max, margin, rssi, RSSI_MAX - rssi); + } +} + +void halbb_dyn_pd_th_ofdm(struct bb_info *bb, u8 rssi, bool set_en) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 pd_dyn_max = bb_dig->igi_rssi + 5; /* PD_low upper bound */ + u8 margin = bb_dig_u->pd_low_th_ofst; /* backoff of CCA ability */ + u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0; + enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw; + + BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__); + + rssi = MIN_2(rssi, pd_dyn_max); + rssi -= MIN_2(rssi, margin); + + if(!set_en) { + halbb_set_pd_lower_bound(bb, RSSI_MIN, cbw, bb->bb_phy_idx); + BB_DIG_DBG(bb, DIG_DBG_LV0, "Dynamic PD th dsiabled\n"); + } else { + if(!halbb_set_pd_lower_bound(bb, RSSI_MAX - rssi, cbw, + bb->bb_phy_idx)) + BB_DIG_DBG(bb, DIG_DBG_LV0, "PD th set warning.\n"); + else + BB_DIG_DBG(bb, DIG_DBG_LV1, "pd_dyn_max=%d, backoff=%d, pd_th_eq_rssi=%d(-%ddBm)\n", + pd_dyn_max, margin, rssi, RSSI_MAX - rssi); + } +} + +void halbb_dig_mode_update(struct bb_info *bb, enum dig_op_mode mode) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + switch (mode) { + case DIG_ORIGIN: + case DIG_SIMPLE: +#ifdef HALBB_DIG_TDMA_SUPPORT + case DIG_TDMA: + case DIG_TDMA_ADV: +#endif + bb_dig->dig_mode = mode; + break; + default: + bb_dig->dig_mode = DIG_ORIGIN; + } + + BB_DIG_DBG(bb, DIG_DBG_LV0, "Set DIG op mode %d\n", bb_dig->dig_mode); +} + +void halbb_dig_gain_para_init(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + s8 *gain_arr = NULL; + u32 tmp_val, i = 0; + + tmp_val = halbb_get_reg_cmn(bb, cr->path0_ib_pkpwr, + cr->path0_ib_pkpwr_m, bb->bb_phy_idx); + bb_dig->ib_pkpwr = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 8); + + bb_dig->ib_pbk = (u8)halbb_get_reg_cmn(bb, cr->path0_ib_pbk, + cr->path0_ib_pbk_m, + bb->bb_phy_idx); + + /*=== [2G Gain Table] =================*/ + /*LNA*/ + gain_arr = bb_dig->lna_gain_g; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g0_g, + cr->path0_lna_err_g0_g_m, bb->bb_phy_idx); + gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA0_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g1_g, + cr->path0_lna_err_g1_g_m, bb->bb_phy_idx); + gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA1_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g2_g, + cr->path0_lna_err_g2_g_m, bb->bb_phy_idx); + gain_arr[2] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA2_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g3_g, + cr->path0_lna_err_g3_g_m, bb->bb_phy_idx); + gain_arr[3] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA3_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g4_g, + cr->path0_lna_err_g4_g_m, bb->bb_phy_idx); + gain_arr[4] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA4_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g5_g, + cr->path0_lna_err_g5_g_m, bb->bb_phy_idx); + gain_arr[5] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA5_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g6_g, + cr->path0_lna_err_g6_g_m, bb->bb_phy_idx); + gain_arr[6] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA6_GAIN; + + /*TIA*/ + gain_arr = bb_dig->tia_gain_g; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g0_g, + cr->path0_tia_err_g0_g_m, bb->bb_phy_idx); + gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA0_GAIN_G; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g1_g, + cr->path0_tia_err_g1_g_m, bb->bb_phy_idx); + gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA1_GAIN_G; + + /*=== [5G Gain Table] =================*/ + /*LNA*/ + gain_arr = bb_dig->lna_gain_a; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g0_a, + cr->path0_lna_err_g0_a_m, bb->bb_phy_idx); + gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA0_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g1_a, + cr->path0_lna_err_g1_a_m, bb->bb_phy_idx); + gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA1_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g2_a, + cr->path0_lna_err_g2_a_m, bb->bb_phy_idx); + gain_arr[2] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA2_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g3_a, + cr->path0_lna_err_g3_a_m, bb->bb_phy_idx); + gain_arr[3] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA3_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g4_a, + cr->path0_lna_err_g4_a_m, bb->bb_phy_idx); + gain_arr[4] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA4_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g5_a, + cr->path0_lna_err_g5_a_m, bb->bb_phy_idx); + gain_arr[5] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA5_GAIN; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g6_a, + cr->path0_lna_err_g6_a_m, bb->bb_phy_idx); + gain_arr[6] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA6_GAIN; + + /*TIA*/ + gain_arr = bb_dig->tia_gain_a; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g0_a, + cr->path0_tia_err_g0_a_m, bb->bb_phy_idx); + gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA0_GAIN_A; + tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g1_a, + cr->path0_tia_err_g1_a_m, bb->bb_phy_idx); + gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA1_GAIN_A; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "ib_pkpwr=%d, ib_pbk=%d\n", + bb_dig->ib_pkpwr, bb_dig->ib_pbk); + + for (i = 0; i < BB_LNA_SIZE; i++) + BB_DIG_DBG(bb, DIG_DBG_LV0, "lna_gain_g[%d]=%d\n", + i, bb_dig->lna_gain_g[i]); + for (i = 0; i < BB_TIA_SIZE; i++) + BB_DIG_DBG(bb, DIG_DBG_LV0, "tia_gain_g[%d]=%d\n", + i, bb_dig->tia_gain_g[i]); + for (i = 0; i < BB_LNA_SIZE; i++) + BB_DIG_DBG(bb, DIG_DBG_LV0, "lna_gain_a[%d]=%d\n", + i, bb_dig->lna_gain_a[i]); + for (i = 0; i < BB_TIA_SIZE; i++) + BB_DIG_DBG(bb, DIG_DBG_LV0, "tia_gain_a[%d]=%d\n", + i, bb_dig->tia_gain_a[i]); + + /*lna initial gain index*/ + bb_dig->max_gaincode.lna_idx = halbb_get_lna_idx(bb, RF_PATH_A); + bb_dig->max_gaincode.tia_idx = halbb_get_tia_idx(bb, RF_PATH_A); + bb_dig->max_gaincode.rxb_idx = halbb_get_rxb_idx(bb, RF_PATH_A); + + BB_DIG_DBG(bb, DIG_DBG_LV0, "Read max gaincode = (%d,%d,%2d)\n", + bb_dig->max_gaincode.lna_idx, bb_dig->max_gaincode.tia_idx, + bb_dig->max_gaincode.rxb_idx); +} + + +/* fa_cnt 2000/4000/5000/8000 */ +static const u16 fa_th_no_link[FA_TH_NUM] = {196, 352, 440, 528}; +static const u16 fa_th_linked[FA_TH_NUM] = {4, 8, 12, 16}; + +void halbb_dig_para_update(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + struct bb_dig_op_para_unit *para_dst; + + BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__); + + /* IGI and PT_low enable control */ + para_dst = &bb_dig->dig_state_h_i.dig_op_para; + para_dst->dyn_pd_th_en = true; + +#ifdef BB_8852A_2_SUPPORT + if (bb->ic_type == BB_RTL8852A) + halbb_dig_agc_update_8852a(bb, para_dst); +#endif + + /* fa th update */ + if (!bb->bb_link_i.is_linked) + halbb_mem_cpy(bb, ¶_dst->fa_th, fa_th_no_link, + sizeof(u16) * FA_TH_NUM); + else + halbb_mem_cpy(bb, ¶_dst->fa_th, fa_th_linked, + sizeof(u16) * FA_TH_NUM); + + BB_DIG_DBG(bb, DIG_DBG_LV1, "is_linked=%d, fa_th[3:0] = %d,%d,%d,%d\n", + bb->bb_link_i.is_linked, + para_dst->fa_th[3], para_dst->fa_th[2], para_dst->fa_th[1], + para_dst->fa_th[0]); + +#ifdef HALBB_DIG_TDMA_SUPPORT + para_dst = &bb_dig->dig_state_l_i.dig_op_para; + halbb_mem_cpy(bb, para_dst, &bb_dig->dig_state_h_i.dig_op_para, + sizeof(struct bb_dig_op_para_unit)); +#endif +} + +void halbb_dig_fa_info_update(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + + /* average from env_mntr_rpt */ + bb_dig_u->fa_r_avg = HALBB_DIV(bb_dig_u->fa_r_acc, bb_dig_u->fa_valid_state_cnt); + bb_dig_u->fa_r_acc = 0; +} + +void halbb_dig_op_unit_para_reset_h(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *unit_cur = &bb_dig->dig_state_h_i; + u8 i = 0; + + unit_cur->cur_gaincode = bb_dig->max_gaincode; + unit_cur->force_gaincode = bb_dig->max_gaincode; + unit_cur->abs_igi_max = IGI_MAX_PERFORMANCE_MODE; + unit_cur->abs_igi_min = 0xc; + unit_cur->pd_low_th_ofst = 16; +#ifdef HALBB_DIG_TDMA_SUPPORT + unit_cur->state_identifier = DIG_TDMA_HIGH; +#endif +} + +#ifdef HALBB_DIG_TDMA_SUPPORT +void halbb_dig_op_unit_para_reset_l(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *unit_cur = &bb_dig->dig_state_l_i; + u8 i = 0; + + unit_cur->cur_gaincode = bb_dig->max_gaincode; + unit_cur->force_gaincode = bb_dig->max_gaincode; + unit_cur->abs_igi_max = 0x26; + unit_cur->abs_igi_min = 0xc; + unit_cur->pd_low_th_ofst = 16; + unit_cur->state_identifier = DIG_TDMA_LOW; +} +#endif + +void halbb_dig_ifs_clm_para_init(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; +#ifdef HALBB_ENV_MNTR_SUPPORT + struct ccx_para_info *para = &dig->ccx_para_i; + + para->rac_lv = RAC_LV_2; + para->mntr_time = DIG_CCX_WD_TRIGTIME; + + para->clm_app = CLM_DIG; + para->clm_input_opt = CLM_CCA_S80_S40_S20; + + para->nhm_app = NHM_DIG; + para->nhm_incld_cca = NHM_EXCLUDE_CCA; + + para->fahm_app = FAHM_DIG; + para->fahm_numer_opt = FAHM_INCLU_FA; + para->fahm_denom_opt = FAHM_INCLU_CRC_ERR; + + para->ifs_clm_app = IFS_CLM_DIG; + + para->edcca_clm_app = EDCCA_CLM_DIG; + para->ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0; +#endif + dig->ccx_is_triggered = false; +} + +void halbb_dig_para_reset(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + bb_dig->pre_dig_mode = bb_dig->dig_mode; + bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i; + bb_dig->need_update = false; + halbb_dig_op_unit_para_reset_h(bb); /* dig_op_unit para reset */ +#ifdef HALBB_DIG_TDMA_SUPPORT + halbb_dig_op_unit_para_reset_l(bb); /* dig_op_unit para reset */ + bb_dig->gaincode_update_en = false; + bb_dig->tdma_passed_time_acc = 0; + bb_dig->tdma_timestamp_cur = 0; + bb_dig->tdma_timestamp_pre = bb_dig->tdma_timestamp_cur; +#endif +#ifdef HALBB_ENV_MNTR_SUPPORT + bb_dig->ccx_timestamp = 0; + bb_dig->ccx_is_triggered = false; +#endif +} + +void halbb_dig_reset(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]=========>\n", __func__); + + halbb_mem_set(bb, &bb_dig->dig_fa_i, 0, sizeof(struct bb_dig_fa_info)); + halbb_dig_para_reset(bb); +#ifdef BB_8852A_2_SUPPORT + halbb_dig_set_igi_cr_8852a(bb, bb_dig->max_gaincode); +#endif + halbb_dyn_pd_th_ofdm(bb, IGI_NOLINK, false); + halbb_dyn_pd_th_cck(bb, IGI_NOLINK, false); + halbb_sdagc_follow_pagc_config(bb, false); +} + +void halbb_dig_init(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + u8 igi_new; + + if(phl_is_mp_mode(bb->phl_com)) + return; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]=========>\n", __func__); + + /* DIG sub-DM configurations */ + halbb_dig_mode_update(bb, DIG_ORIGIN); + bb_dig->igi_pause_cnt = 0; + bb_dig->le_igi_ofst = 10; + bb_dig->dbg_lv = DIG_DBG_LV2; + bb_dig->dig_state_h_i.state_num_lmt = 3; + bb_dig->dig_state_h_i.sdagc_follow_pagc_en = false; +#ifdef HALBB_DIG_TDMA_SUPPORT + bb_dig->dig_state_l_i.state_num_lmt = 1; + bb_dig->dig_state_l_i.sdagc_follow_pagc_en = false; + bb_dig->dig_timer_i.cb_time = 50; +#endif + halbb_dig_ifs_clm_para_init(bb); + halbb_dig_gain_para_init(bb); + halbb_dig_reset(bb); + bb_dig->dig_state_h_i.igi_fa_rssi = 1; /*init state*/ + halbb_dig_para_update(bb); + +#ifdef HALBB_DIG_DAMPING_CHK + halbb_dig_damping_chk_init(bb); +#endif + igi_new = halbb_dig_igi_by_ofst(bb, IGI_NOLINK, 0); + halbb_dig_cfg_bbcr(bb, igi_new); +} + +void halbb_dig_deinit(struct bb_info *bb) +{ +#ifdef HALBB_DIG_TDMA_SUPPORT + BB_DBG(bb, DBG_INIT, "halbb_dig_deinit"); +#endif +} + +bool halbb_dig_abort(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + + /* support_ability */ + if (!(bb->support_ability & BB_DIG)) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======> DISABLED\n", __func__); + return true; + } + + if (bb->pause_ability & BB_DIG) { + dig->igi_pause_cnt++; + BB_DIG_DBG(bb, DIG_DBG_LV0, "Return: Pause DIG in LV=%d, cnt=%d\n", + bb->pause_lv_table.lv_dig, + dig->igi_pause_cnt); + + return true; + } + + if (dig->igi_pause_cnt) { + dig->igi_pause_cnt = 0; + BB_DIG_DBG(bb, DIG_DBG_LV0, "Skip 1 time after pause DIG\n"); + return true; + } + + return false; +} + +void halbb_dig_lps(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + s16 final_rssi = bb_dig->igi_rssi + bb_dig->le_igi_ofst; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__); + + final_rssi = MIN_2(final_rssi, RSSI_MAX); + final_rssi = MAX_2(final_rssi, RSSI_MIN); + + + BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi=%03d, le_ofst=(%03d), final_rssi=%d\n", + bb_dig->igi_rssi, bb_dig->le_igi_ofst, (s8)final_rssi); + +#ifdef BB_8852A_2_SUPPORT + /* IGI decision */ + if (halbb_dig_gaincode_update_en_8852a(bb)) + halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode); +#endif + + /* Dynamic sync-dagc follow pagc*/ + halbb_sdagc_follow_pagc_config(bb, false); +} + +void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = dig->p_cur_dig_unit; + struct bb_dig_op_unit *dig_u = &dig->dig_state_h_i; + struct bb_dig_op_para_unit *para = &dig_u->dig_op_para; + + if (igi_new == dig_u->igi_fa_rssi) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "[IGI][hold_cnt:%d] %d\n", dig->dig_hold_cnt, igi_new); + dig->dig_hold_cnt++; + return; + } else { + BB_DIG_DBG(bb, DIG_DBG_LV0, "[IGI] %d -> %d\n", dig_u->igi_fa_rssi, igi_new); + dig->dig_hold_cnt = 0; + } + + dig_u->igi_fa_rssi = igi_new; + +#ifdef BB_8852A_2_SUPPORT + /* IGI decision */ + if (halbb_dig_gaincode_update_en_8852a(bb)) + halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode); +#endif + + /* Dynamic PD lower bound */ + halbb_dyn_pd_th_ofdm(bb, igi_new, para->dyn_pd_th_en); + + /* Dynamic CCK PD TH */ + halbb_dyn_pd_th_cck(bb, igi_new, para->dyn_pd_th_en); + + /* Dynamic sync-dagc follow pagc*/ + if (para->dyn_pd_th_en && igi_new > dig->igi_rssi) + halbb_sdagc_follow_pagc_config(bb, true); + else + halbb_sdagc_follow_pagc_config(bb, false); +} + +void halbb_dig_new_entry_connect(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + u8 igi_new; + u8 rssi_min_new = halbb_get_rssi_min(bb); + + BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__); + if (rssi_min_new == 0) + return; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi_min_new=%d\n", rssi_min_new); + /* Update igi_rssi */ + dig->igi_rssi = rssi_min_new >> 1; + igi_new = halbb_dig_igi_by_ofst(bb, dig->igi_rssi, 0); + halbb_dig_cfg_bbcr(bb, igi_new); + /*Update EDCCA threshold*/ + halbb_edcca_thre_calc(bb); +} + +void halbb_dig(struct bb_info *bb) +{ + struct bb_dig_info *dig = &bb->bb_dig_i; + struct bb_dig_op_unit *dig_u = &dig->dig_state_h_i; + struct bb_dig_op_para_unit *para = &dig_u->dig_op_para; + struct bb_link_info *bb_link = &bb->bb_link_i; + u16 fa_avg; + u8 igi_new, igi_pre = dig_u->igi_fa_rssi; + s8 ofst; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__); + + dig->need_update |= (bb_link->first_connect | bb_link->first_disconnect); + + if (halbb_dig_abort(bb)) + return; + + /* Update igi_rssi */ + dig->igi_rssi = (bb_link->is_linked) ? (bb->bb_ch_i.rssi_min >> 1) : IGI_NOLINK; + BB_DIG_DBG(bb, DIG_DBG_LV0, "link=%d, rssi=%d\n", bb_link->is_linked, dig->igi_rssi); + + if (dig->need_update) { + halbb_dig_para_update(bb); + #ifdef HALBB_DIG_DAMPING_CHK + halbb_dig_recorder_reset(bb); + #endif + + BB_DIG_DBG(bb, DIG_DBG_LV0, "Connect/Disconnect\n"); + + igi_new = halbb_dig_igi_by_ofst(bb, dig->igi_rssi, 0); + halbb_dig_cfg_bbcr(bb, igi_new); + dig->need_update = false; + return; + } + +#ifdef HALBB_DIG_TDMA_SUPPORT + if (dig->dig_mode == DIG_TDMA && bb_link->is_linked) { + halbb_dig_timercheck_watchdog(bb); + return; + } + + dig->p_cur_dig_unit = &dig->dig_state_h_i; +#endif + + if (dig->dig_mode == DIG_SIMPLE) { + halbb_dig_lps(bb); + return; + } + + /* FA info handling */ + if (!halbb_dig_ifs_clm_latch(bb)) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "IFS CLM Get Rpt Fail\n"); + goto DIG_END; + } + + fa_avg = HALBB_DIV(dig_u->fa_r_acc, dig_u->fa_valid_state_cnt); + dig_u->fa_r_acc = 0; + dig_u->fa_valid_state_cnt = 0; + +#ifdef HALBB_DIG_DAMPING_CHK + /*Record IGI History*/ + halbb_dig_recorder(bb, igi_pre, fa_avg); + /*DIG Damping Check*/ + halbb_dig_damping_chk(bb); +#endif + ofst = halbb_dig_ofst_by_fa(bb, fa_avg); + igi_new = halbb_dig_igi_by_ofst(bb, igi_pre, ofst); + halbb_dig_cfg_bbcr(bb, igi_new); + +DIG_END: + if (!halbb_dig_ifs_clm_trig(bb, DIG_CCX_WD_TRIGTIME)) + BB_DIG_DBG(bb, DIG_DBG_LV0, "IFS CLM Trig Fail\n"); +} + +#ifdef HALBB_DIG_TDMA_SUPPORT +void halbb_tdma_dig(struct bb_info *bb) { + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + bool ifs_clm_op_status = false; + bool igi_update_en_h = false, igi_update_en_l = false; + + bb_dig->tdma_timestamp_cur++; + bb_dig->tdma_passed_time_acc += (u16)bb_dig->dig_timer_i.cb_time; + + BB_DIG_DBG(bb, DIG_DBG_LV2, "[IN]state_cnt=%d, state_lmt=%d\n", + bb_dig_u->passed_state_cnt, bb_dig_u->state_num_lmt); + + /* FA info handling */ + ifs_clm_op_status = halbb_dig_ifs_clm_latch(bb); + + /* Two seconds periodic procedure */ + if (bb_dig->tdma_passed_time_acc >= WACHDOG_PERIOD_IN_MS) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "Two seconds reached.\n"); + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[TDMA-H]============>\n"); + bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i; + /* FA info handling */ + halbb_dig_fa_info_update(bb); + /* Noisy level decision */ + halbb_dig_noisy_lv_decision(bb); + halbb_dig_igi_ofst_by_env(bb); + /* IGI and boundary decision */ + bb_dig_u->igi_fa_rssi = halbb_dig_igi_bound_decision(bb); +#ifdef BB_8852A_2_SUPPORT + /* IGI decision */ + igi_update_en_h = halbb_dig_gaincode_update_en_8852a(bb); +#endif + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[TDMA-L]============>\n"); + bb_dig->p_cur_dig_unit = &bb_dig->dig_state_l_i; + /* FA info handling */ + halbb_dig_fa_info_update(bb); + /* Noisy level decision */ + halbb_dig_noisy_lv_decision(bb); + halbb_dig_igi_ofst_by_env(bb); + /* IGI and boundary decision */ + bb_dig_u->igi_fa_rssi = halbb_dig_igi_bound_decision(bb); +#ifdef BB_8852A_2_SUPPORT + /* IGI decision */ + igi_update_en_l = halbb_dig_gaincode_update_en_8852a(bb); +#endif + bb_dig->gaincode_update_en = igi_update_en_h | igi_update_en_l; + bb_dig->p_cur_dig_unit = bb_dig_u; + bb_dig->tdma_passed_time_acc = 0; + } + + /* TDMA state transition */ + if (++bb_dig_u->passed_state_cnt >= bb_dig_u->state_num_lmt) { + BB_DIG_DBG(bb, DIG_DBG_LV2, "[OUT]state_cnt=%d, state_lmt=%d\n", + bb_dig_u->passed_state_cnt, + bb_dig_u->state_num_lmt); + bb_dig_u->passed_state_cnt = 0; + switch (bb_dig_u->state_identifier) { + case DIG_TDMA_LOW: + bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i; + BB_DIG_DBG(bb, DIG_DBG_LV1, "[TDMA-L]->[TDMA-H].\n"); + break; + case DIG_TDMA_HIGH: + bb_dig->p_cur_dig_unit = &bb_dig->dig_state_l_i; + BB_DIG_DBG(bb, DIG_DBG_LV1, "[TDMA-H]->[TDMA-L].\n"); + break; + default: + break; + } + bb_dig_u = bb_dig->p_cur_dig_unit; +#ifdef BB_8852A_2_SUPPORT + /* To set lna, tia, rxbb index */ + if (bb_dig->gaincode_update_en) + halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode); +#endif + /* Dynamic PD lower bound */ + halbb_dyn_pd_th_ofdm(bb, bb_dig_u->igi_fa_rssi, + bb_dig_u->dig_op_para.dyn_pd_th_en); + + /* Dynamic CCK PD TH */ + halbb_dyn_pd_th_cck(bb, bb_dig_u->igi_fa_rssi, + bb_dig_u->dig_op_para.dyn_pd_th_en); + + /* Dynamic sync-dagc follow pagc*/ + if (bb_dig_u->dig_op_para.dyn_pd_th_en && + (bb_dig_u->igi_fa_rssi > bb_dig->igi_rssi)) + halbb_sdagc_follow_pagc_config(bb, true); + else + halbb_sdagc_follow_pagc_config(bb, false); + } + + ifs_clm_op_status = halbb_dig_ifs_clm_trig(bb, (u16)bb_dig->dig_timer_i.cb_time); +} + +void halbb_dig_timercheck_watchdog(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + if (bb_dig->tdma_timestamp_cur == bb_dig->tdma_timestamp_pre) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "DIG TDMA timer check FAIL. Restart.\n"); + halbb_dig_reset(bb); + halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_dig_i.dig_timer_i); + } + bb_dig->tdma_timestamp_pre = bb_dig->tdma_timestamp_cur; +} + +void halbb_tdmadig_io_en(struct bb_info *bb) +{ + struct bb_link_info *bb_link = &bb->bb_link_i; + + if (halbb_dig_abort(bb)) { + return; + } + + if (!bb_link->is_linked) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "is_linked=%d, one_entry_only=%d\n", + bb_link->is_linked, bb_link->is_one_entry_only); + return; + } + + if ((bb->bb_dig_i.dig_mode != DIG_TDMA) && + (bb->bb_dig_i.dig_mode != DIG_TDMA_ADV)) + return; + + halbb_tdma_dig(bb); + halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_dig_i.dig_timer_i); +} + +void halbb_tdmadig_callback(void *context) +{ + struct bb_info *bb = (struct bb_info *)context; + struct halbb_timer_info *timer = &bb->bb_dig_i.dig_timer_i; + + BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]===>\n", __func__); + + timer->timer_state = BB_TIMER_IDLE; + + if (bb->phl_com->hci_type == RTW_HCI_PCIE) + halbb_tdmadig_io_en(bb); + else + rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx); +} + +void halbb_dig_timer_init(struct bb_info *bb) +{ + struct halbb_timer_info *timer = &bb->bb_dig_i.dig_timer_i; + + BB_DBG(bb, DBG_DIG, "[%s]\n", __func__); + + timer->event_idx = BB_EVENT_TIMER_DIG; + timer->timer_state = BB_TIMER_IDLE; + + halbb_init_timer(bb, &timer->timer_list, halbb_tdmadig_callback, bb, "halbb_dig_timer"); +} + +#endif /*#ifdef HALBB_DIG_TDMA_SUPPORT*/ + +void halbb_set_dig_pause_val(struct bb_info *bb, u32 *buf, u8 val_len) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *dig_u = bb_dig->p_cur_dig_unit; + struct agc_gaincode_set gaincode = bb_dig->max_gaincode; + u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0; + enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw; + u8 target_pwr, margin = dig_u->pd_low_th_ofst; + + if (val_len != DIG_PAUSE_INFO_SIZE) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "[Error][DIG]Need val_len=%d\n", + DIG_PAUSE_INFO_SIZE); + return; + } + BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s] Pd=-%d dB\n", __func__, buf[0]); + +#ifdef BB_8852A_2_SUPPORT + /* write igi or keep max gaincode */ + if (bb->ic_type == BB_RTL8852A) { + if ((buf[1] == PAUSE_OFDM_CCK) && (bb->hal_com->cv < CCV)) { + BB_DIG_DBG(bb, DIG_DBG_LV0, "[52A] igi_en=1\n"); + halbb_gaincode_by_rssi_8852a(bb, &gaincode, RSSI_MAX - (u8)buf[0]); + } + halbb_dig_set_igi_cr_8852a(bb, gaincode); + } +#endif + + /* write pd lower bound anyway */ + target_pwr = MIN_2((u8)buf[0] + margin, RSSI_MAX); + halbb_set_pd_lower_bound(bb, target_pwr, cbw, bb->bb_phy_idx); + if (buf[1] == PAUSE_OFDM) + target_pwr = 0; + halbb_set_pd_lower_bound_cck(bb, target_pwr, cbw, bb->bb_phy_idx); +} + +void* halbb_get_dig_fa_statistic(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + + return &bb_dig->dig_fa_i; +} + +void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = &bb_dig->dig_state_h_i; + struct agc_gaincode_set set_tmp; + u32 var[10] = {0}; + u8 i = 0; + + if (_os_strcmp(input[1], "-h") == 0) { +#ifdef HALBB_DIG_TDMA_SUPPORT + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "DIG-H state\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{0} {dig op mode = %d(0:DIG,1:TDMA,2:A-TDMA,3:low IO)}\n", + bb_dig->dig_mode); +#else + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{0} {dig op mode = %d(0:DIG,3:low IO)}\n", + bb_dig->dig_mode); +#endif + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{1} {fix_lna = %d} {fix_tia = %d} {fix_rxb = %d}\n", + bb_dig_u->force_gaincode.lna_idx, + bb_dig_u->force_gaincode.tia_idx, + bb_dig_u->force_gaincode.rxb_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{2: get current IGI} {path(0/1)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{3: show rssi threshold of IGI}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{4: modify rssi threshold} {TH idx(0-4)} {value}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{5: show fa ratio vs. noisy level.}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{6: modify fa ratio threshold} {TH idx(0-3)} {value}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{7: dyn PD low bound en = %d} {0:disable, 1:enable}\n", + bb_dig_u->dig_op_para.dyn_pd_th_en); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{8: dyn PD low bound backoff = %d} {value}\n", + bb_dig_u->pd_low_th_ofst); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{9: reset rssi, fa_ratio TH}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{10: show AGC table}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{11: Update gain parameters}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{12: simple mode IGI offset = (%d)} {0:-, 1:+} {val}\n", + bb_dig->le_igi_ofst); +#ifdef HALBB_DIG_TDMA_SUPPORT + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{13: tdma timer = %d ms} {val(ms)}\n", + bb_dig->dig_timer_i.cb_time); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{14: state limit (L,H) = (%d,%d)} {0:L,1:H} {state num}\n", + bb_dig->dig_state_l_i.state_num_lmt, + bb_dig->dig_state_h_i.state_num_lmt); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{15} {0:L,1:H} {fix_lna = %d} {fix_tia = %d} {fix_rxb = %d}\n", + bb_dig_u->force_gaincode.lna_idx, + bb_dig_u->force_gaincode.tia_idx, + bb_dig_u->force_gaincode.rxb_idx); +#endif + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{20: dbg level = %d} {0/1/2}\n", + bb_dig->dbg_lv); +#ifdef HALBB_DIG_DAMPING_CHK + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "damping en {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "damping th {s(8,1)}\n"); +#endif + return; + } + +#ifdef HALBB_DIG_DAMPING_CHK + if (_os_strcmp(input[1], "damping") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[0]); + if (_os_strcmp(input[2], "en") == 0) { + bb_dig->dig_dl_en = (bool)var[0]; + + if (!bb_dig->dig_dl_en) + halbb_dig_recorder_reset(bb); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dig_dl_en = %d\n", bb_dig->dig_dl_en); + } else if (_os_strcmp(input[2], "th") == 0) { + bb_dig->rls_rssi_diff_th = (u8)var[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rls_rssi_diff_th = %d.%d\n", + var[0] >> 1, (var[0] & 1) * 5); + } + return; + } +#endif + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + if (var[0] == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + halbb_dig_mode_update(bb, (enum dig_op_mode)var[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set DIG op mode = %d\n", bb_dig->dig_mode); + } else if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]); + + bb_dig_u->force_gaincode.lna_idx = (u8)var[1]; + bb_dig_u->force_gaincode.tia_idx = (u8)var[2]; + bb_dig_u->force_gaincode.rxb_idx = (u8)var[3]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n", + bb_dig_u->force_gaincode.lna_idx, + bb_dig_u->force_gaincode.tia_idx, + bb_dig_u->force_gaincode.rxb_idx); +#ifdef BB_8852A_2_SUPPORT + halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->force_gaincode); +#endif + } else if (var[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "current(lna,tia,rxb)=((%d,%d,%d))\n", + halbb_get_lna_idx(bb,(enum rf_path)var[1]), + halbb_get_tia_idx(bb,(enum rf_path)var[1]), + halbb_get_rxb_idx(bb,(enum rf_path)var[1])); + } else if (var[0] == 3) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rssi TH: -----%03d-----%03d-----%03d-----%03d-----%03d-----\n", + bb_dig_u->dig_op_para.igi_rssi_th[0], + bb_dig_u->dig_op_para.igi_rssi_th[1], + bb_dig_u->dig_op_para.igi_rssi_th[2], + bb_dig_u->dig_op_para.igi_rssi_th[3], + bb_dig_u->dig_op_para.igi_rssi_th[4]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "lna idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n", + 6,5,4,3,2,1); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tia idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n", + 1,0,0,0,0,0); + } else if (var[0] == 4) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + if (var[1] < 5) { + bb_dig_u->dig_op_para.igi_rssi_th[var[1]] = (u8)var[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set rssi_TH[%d]=%d\n", var[1], + bb_dig_u->dig_op_para.igi_rssi_th[var[1]]); + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rssi TH: -----%03d-----%03d-----%03d-----%03d-----%03d-----\n", + bb_dig_u->dig_op_para.igi_rssi_th[0], + bb_dig_u->dig_op_para.igi_rssi_th[1], + bb_dig_u->dig_op_para.igi_rssi_th[2], + bb_dig_u->dig_op_para.igi_rssi_th[3], + bb_dig_u->dig_op_para.igi_rssi_th[4]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "lna idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n", + 6,5,4,3,2,1); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tia idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n", + 1,0,0,0,0,0); + } else if (var[0] == 5) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "fa ratio TH: -----%03d-----%03d-----%03d-----%03d-----\n", + bb_dig_u->dig_op_para.fa_th[0], + bb_dig_u->dig_op_para.fa_th[1], + bb_dig_u->dig_op_para.fa_th[2], + bb_dig_u->dig_op_para.fa_th[3]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "noisy level: --%1d--|||--%1d--|||--%1d--|||--%1d--|||-%s-\n", + 0,1,2,3,"MAX"); + } else if (var[0] == 6) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + if (var[1] < 4) { + bb_dig_u->dig_op_para.fa_th[var[1]] = (u16)var[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set FA ratio TH[%d]=%d\n", var[1], + bb_dig_u->dig_op_para.fa_th[var[1]]); + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "fa ratio TH: -----%03d-----%03d-----%03d-----%03d-----\n", + bb_dig_u->dig_op_para.fa_th[0], + bb_dig_u->dig_op_para.fa_th[1], + bb_dig_u->dig_op_para.fa_th[2], + bb_dig_u->dig_op_para.fa_th[3]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "noisy level: --%1d--|||--%1d--|||--%1d--|||--%1d--|||-%s-\n", + 0,1,2,3,"MAX"); + } else if (var[0] == 7) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dig_u->dig_op_para.dyn_pd_th_en = (bool)var[1]; + if (bb_dig_u->dig_op_para.dyn_pd_th_en) + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Enabled dyn PD low bound\n"); + else + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Disabled dyn PD low bound\n"); + } else if (var[0] == 8) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dig_u->pd_low_th_ofst = (u8)var[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set dyn PD low bound backoff=%d\n", + bb_dig_u->pd_low_th_ofst); + } else if (var[0] == 9) { + halbb_dig_reset(bb); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Reset state machine parameters\n"); +#ifdef BB_8852A_2_SUPPORT + } else if (var[0] == 10) { + for (i = RSSI_MIN; i <= RSSI_MAX; i++) + halbb_gaincode_by_rssi_8852a(bb, &set_tmp, i); +#endif + } else if (var[0] == 11) { + halbb_dig_gain_para_init(bb); + } else if (var[0] == 12) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + if (var[1] == 0) + bb_dig->le_igi_ofst = -(s8)var[2]; + else if (var[1] == 1) + bb_dig->le_igi_ofst = (s8)var[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "simple mode IGI offset set to (%d)\n", + bb_dig->le_igi_ofst); +#ifdef HALBB_DIG_TDMA_SUPPORT + } else if (var[0] == 13) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + bb_dig->dig_timer_i.cb_time = (u16)var[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tdma timer set to %d ms\n", + bb_dig->dig_timer_i.cb_time); + } else if (var[0] == 14) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + if (var[1] == 0) + bb_dig_u = &bb_dig->dig_state_l_i; + else if (var[1] == 1) + bb_dig_u = &bb_dig->dig_state_h_i; + bb_dig_u->state_num_lmt = (u8)var[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set TDMA-%d state limit to %d\n", + bb_dig_u->state_identifier, + bb_dig_u->state_num_lmt); + } else if (var[0] == 15) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &var[4]); + HALBB_SCAN(input[6], DCMD_DECIMAL, &var[5]); + if (var[1] == 0) + bb_dig_u = &bb_dig->dig_state_l_i; + else if (var[1] == 1) + bb_dig_u = &bb_dig->dig_state_h_i; + + bb_dig_u->force_gaincode.lna_idx = (u8)var[2]; + bb_dig_u->force_gaincode.tia_idx = (u8)var[3]; + bb_dig_u->force_gaincode.rxb_idx = (u8)var[4]; + + bb_dig_u = &bb_dig->dig_state_l_i; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[TDMA-L]IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n", + bb_dig_u->force_gaincode.lna_idx, + bb_dig_u->force_gaincode.tia_idx, + bb_dig_u->force_gaincode.rxb_idx); + bb_dig_u = &bb_dig->dig_state_h_i; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[TDMA-H]IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n", + bb_dig_u->force_gaincode.lna_idx, + bb_dig_u->force_gaincode.tia_idx, + bb_dig_u->force_gaincode.rxb_idx); +#endif + } else if (var[0] == 20) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + if ((enum dig_dbg_level)var[1] <= DIG_DBG_LV2) + bb_dig->dbg_lv = (enum dig_dbg_level)var[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dbg level set to lv%d\n", + bb_dig->dbg_lv); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} + +void halbb_cr_cfg_dig_init(struct bb_info *bb) +{ + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + + switch (bb->cr_type) { +#ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + /*cr->path0_ib_pbk = PATH0_R_IB_PBK_52AA; + *cr->path0_ib_pbk_m = PATH0_R_IB_PBK_52AA_M; + *cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_52AA; + *cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_52AA_M; + *cr->path1_ib_pbk = PATH1_R_IB_PBK_52AA; + *cr->path1_ib_pbk_m = PATH1_R_IB_PBK_52AA_M; + *cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_52AA; + *cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_52AA_M; + */ + cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_52AA; + cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_52AA_M; + cr->path1_lna_init_idx = PATH0_R_LNA_INIT_IDX_52AA; + cr->path1_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_52AA_M; + cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_52AA; + cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_52AA_M; + cr->path1_tia_init_idx = PATH0_R_TIA_INIT_IDX_52AA; + cr->path1_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_52AA_M; + cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_52AA; + cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_52AA_M; + cr->path1_rxb_init_idx = PATH0_R_RXB_INIT_IDX_52AA; + cr->path1_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_52AA_M; + /*cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_52AA; + *cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_52AA_M; + *cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_52AA; + *cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_52AA_M; + *cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA; + *cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M; + *cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA; + *cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M; + *cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA; + *cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M; + *cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA; + *cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M; + *cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_A_52AA; + *cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_A_52AA_M; + *cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_52AA; + *cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_52AA_M; + *cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_A_52AA; + *cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_A_52AA_M; + *cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_52AA; + *cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_52AA_M; + *cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_A_52AA; + *cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_A_52AA_M; + *cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_52AA; + *cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_52AA_M; + *cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_A_52AA; + *cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_A_52AA_M; + *cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_52AA; + *cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_52AA_M; + *cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_A_52AA; + *cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_A_52AA_M; + *cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_52AA; + *cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_52AA_M; + *cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_A_52AA; + *cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_A_52AA_M; + *cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_52AA; + *cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_52AA_M; + *cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_A_52AA; + *cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_A_52AA_M; + *cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_52AA; + *cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_52AA_M; + *cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_A_52AA; + *cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_A_52AA_M; + *cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_52AA; + *cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_52AA_M; + *cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_A_52AA; + *cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_A_52AA_M; + *cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_52AA; + *cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_52AA_M; + *cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_A_52AA; + *cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_A_52AA_M; + *cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_52AA; + *cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_52AA_M; + *cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_A_52AA; + *cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_A_52AA_M; + *cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_52AA; + *cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_52AA_M; + *cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_A_52AA; + *cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_A_52AA_M; + *cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_52AA; + *cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_52AA_M; + *cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_A_52AA; + *cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_A_52AA_M; + *cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_52AA; + *cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_52AA_M; + *cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_A_52AA; + *cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_A_52AA_M; + *cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_52AA; + *cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_52AA_M; + *cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_A_52AA; + *cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_A_52AA_M; + *cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_52AA; + *cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_52AA_M; + *cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_A_52AA; + *cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_A_52AA_M; + *cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_52AA; + *cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_52AA_M; + *cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_A_52AA; + *cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_A_52AA_M; + *cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_52AA; + *cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_52AA_M; + *cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_A_52AA; + *cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_A_52AA_M; + *cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_52AA; + *cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_52AA_M; + */ + break; +#endif +#ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->path0_ib_pbk = PATH0_R_IB_PBK_A; + cr->path0_ib_pbk_m = PATH0_R_IB_PBK_A_M; + cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_A; + cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_A_M; + cr->path1_ib_pbk = PATH1_R_IB_PBK_A; + cr->path1_ib_pbk_m = PATH1_R_IB_PBK_A_M; + cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_A; + cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_A_M; + cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_A; + cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_A_M; + cr->path1_lna_init_idx = PATH1_R_LNA_INIT_IDX_A; + cr->path1_lna_init_idx_m = PATH1_R_LNA_INIT_IDX_A_M; + cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_A; + cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_A_M; + cr->path1_tia_init_idx = PATH1_R_TIA_INIT_IDX_A; + cr->path1_tia_init_idx_m = PATH1_R_TIA_INIT_IDX_A_M; + cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_A; + cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_A_M; + cr->path1_rxb_init_idx = PATH1_R_RXB_INIT_IDX_A; + cr->path1_rxb_init_idx_m = PATH1_R_RXB_INIT_IDX_A_M; + cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_A; + cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_A_M; + cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_A; + cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_A_M; + cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_A; + cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_A_M; + cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_A; + cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_A_M; + cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_A; + cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_A_M; + cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_A; + cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_A_M; + cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_A_A; + cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_A_A_M; + cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_A; + cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_A_M; + cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_A_A; + cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_A_A_M; + cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_A; + cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_A_M; + cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_A_A; + cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_A_A_M; + cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_A; + cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_A_M; + cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_A_A; + cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_A_A_M; + cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_A; + cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_A_M; + cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_A_A; + cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_A_A_M; + cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_A; + cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_A_M; + cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_A_A; + cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_A_A_M; + cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_A; + cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_A_M; + cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_A_A; + cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_A_A_M; + cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_A; + cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_A_M; + cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_A_A; + cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_A_A_M; + cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_A; + cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_A_M; + cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_A_A; + cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_A_A_M; + cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_A; + cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_A_M; + cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_A_A; + cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_A_A_M; + cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_A; + cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_A_M; + cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_A_A; + cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_A_A_M; + cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_A; + cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_A_M; + cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_A_A; + cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_A_A_M; + cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_A; + cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_A_M; + cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_A_A; + cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_A_A_M; + cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_A; + cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_A_M; + cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_A_A; + cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_A_A_M; + cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_A; + cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_A_M; + cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_A_A; + cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_A_A_M; + cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_A; + cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_A_M; + cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_A_A; + cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_A_A_M; + cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_A; + cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_A_M; + cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_A_A; + cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_A_A_M; + cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_A; + cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_A_M; + cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_A_A; + cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_A_A_M; + cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_A; + cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_A_M; + break; +#endif +#ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->path0_lna_init_idx = PATH0_R_LNA_IDX_INIT_C; + cr->path0_lna_init_idx_m = PATH0_R_LNA_IDX_INIT_C_M; + cr->path1_lna_init_idx = PATH1_R_LNA_IDX_INIT_C; + cr->path1_lna_init_idx_m = PATH1_R_LNA_IDX_INIT_C_M; + cr->path0_tia_init_idx = PATH0_R_TIA_IDX_INIT_C; + cr->path0_tia_init_idx_m = PATH0_R_TIA_IDX_INIT_C_M; + cr->path1_tia_init_idx = PATH1_R_TIA_IDX_INIT_C; + cr->path1_tia_init_idx_m = PATH1_R_TIA_IDX_INIT_C_M; + cr->path0_rxb_init_idx = PATH0_R_RXIDX_INIT_C; + cr->path0_rxb_init_idx_m = PATH0_R_RXIDX_INIT_C_M; + cr->path1_rxb_init_idx = PATH1_R_RXIDX_INIT_C; + cr->path1_rxb_init_idx_m = PATH1_R_RXIDX_INIT_C_M; + cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_C; + cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_C_M; + cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_C; + cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_C_M; +#if 0 + cr->path0_ib_pbk = PATH0_R_IB_PBK_C; + cr->path0_ib_pbk_m = PATH0_R_IB_PBK_C_M; + cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_C; + cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_C_M; + cr->path1_ib_pbk = PATH1_R_IB_PBK_C; + cr->path1_ib_pbk_m = PATH1_R_IB_PBK_C_M; + cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_C; + cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_C_M; + cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_C; + cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_C_M; + cr->path1_lna_init_idx = PATH1_R_LNA_INIT_IDX_C; + cr->path1_lna_init_idx_m = PATH1_R_LNA_INIT_IDX_C_M; + cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_C; + cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_C_M; + cr->path1_tia_init_idx = PATH1_R_TIA_INIT_IDX_C; + cr->path1_tia_init_idx_m = PATH1_R_TIA_INIT_IDX_C_M; + cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_C; + cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_C_M; + cr->path1_rxb_init_idx = PATH1_R_RXB_INIT_IDX_C; + cr->path1_rxb_init_idx_m = PATH1_R_RXB_INIT_IDX_C_M; + cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_C; + cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_C_M; + cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_C; + cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_C_M; + cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C; + cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M; + cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C; + cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M; + cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C; + cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M; + cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C; + cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M; + cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_C_C; + cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_C_C_M; + cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_C; + cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_C_M; + cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_C_C; + cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_C_C_M; + cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_C; + cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_C_M; + cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_C_C; + cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_C_C_M; + cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_C; + cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_C_M; + cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_C_C; + cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_C_C_M; + cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_C; + cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_C_M; + cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_C_C; + cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_C_C_M; + cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_C; + cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_C_M; + cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_C_C; + cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_C_C_M; + cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_C; + cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_C_M; + cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_C_C; + cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_C_C_M; + cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_C; + cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_C_M; + cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_C_C; + cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_C_C_M; + cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_C; + cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_C_M; + cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_C_C; + cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_C_C_M; + cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_C; + cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_C_M; + cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_C_C; + cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_C_C_M; + cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_C; + cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_C_M; + cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_C_C; + cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_C_C_M; + cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_C; + cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_C_M; + cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_C_C; + cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_C_C_M; + cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_C; + cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_C_M; + cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_C_C; + cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_C_C_M; + cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_C; + cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_C_M; + cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_C_C; + cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_C_C_M; + cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_C; + cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_C_M; + cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_C_C; + cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_C_C_M; + cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_C; + cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_C_M; + cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_C_C; + cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_C_C_M; + cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_C; + cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_C_M; + cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_C_C; + cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_C_C_M; + cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_C; + cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_C_M; + cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_C_C; + cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_C_C_M; + cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_C; + cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_C_M; +#endif + break; +#endif + default: + break; + } +} +#endif +#ifdef HALBB_DIG_MCC_SUPPORT +void Halbb_init_mccdm(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + u8 i = 0; + + BB_DBG(bb, DBG_DIG, "[%s]=========>\n", __func__); + + mcc_dm->softap_macid = INVALID_INIT_VAL; + + for (i = 0; i < MCC_BAND_NUM; i++) { + mcc_dm->mcc_reg_id[i] = INVALID_INIT_VAL; + mcc_dm->mcc_dm_reg[i] = 0; + mcc_dm->mcc_dm_val[i][0] = 0; + mcc_dm->mcc_dm_val[i][1] = 0; + } +} + +u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h) +{ + bool fw_mccdm_en = false; + + if (!c2h) { + BB_WARNING("Error fw mcc dig c2h failed!!\n"); + return _FAIL; + } + + fw_mccdm_en = (bool)c2h[0]; + BB_DBG(bb, DBG_DIG, "FW MCC DIG : %s\n", fw_mccdm_en ? "true" : "false"); + + return _SUCCESS; +} + +void halbb_mccdm_h2ccmd_rst(struct bb_info *bb) +{ + struct mcc_h2c *mcc_cfg; + bool ret_val = false; + u8 cmdlen = sizeof(struct mcc_h2c); + u32 *bb_h2c; + + mcc_cfg = hal_mem_alloc(bb->hal_com, cmdlen); + + if (!mcc_cfg) { + BB_WARNING(" Error mcc_cfg allocat failed!!\n"); + return; + } + halbb_mem_set(bb, mcc_cfg, 0, cmdlen); + bb_h2c = (u32*) mcc_cfg; + //u8 h2c_mcc[H2C_MAX_LENGTH]; + + /* RST MCC */ + mcc_cfg->mcc_dm_en = 0; + mcc_cfg->reg_cnt = 0; + mcc_cfg->mcc_set = 0; + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC, + HALBB_H2C_DM, bb_h2c); + BB_DBG(bb, DBG_DIG, "MCC H2C RST\n"); + + if (mcc_cfg) + hal_mem_free(bb->hal_com, mcc_cfg, cmdlen); +} + +void Halbb_mccdm_h2c_handler(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + struct mcc_h2c_reg_content *reg_cont; + struct mcc_h2c *mcc_cfg; + bool ret_val = false; + u8 cmdlen = sizeof(struct mcc_h2c); + u8 i; + u8 regid; + u8 ch_idx; + u8 reg_cnt; + u32 *bb_h2c; + + mcc_cfg = hal_mem_alloc(bb->hal_com, cmdlen); + + if (!mcc_cfg) { + BB_WARNING(" Error mcc_cfg allocat failed!!\n"); + return; + } + bb_h2c = (u32*) mcc_cfg; + + if (mcc_dm->mcc_rf_ch[0].center_ch == INVALID_INIT_VAL && + mcc_dm->mcc_rf_ch[1].center_ch == INVALID_INIT_VAL) { + BB_DBG(bb, DBG_DIG, "MCC channel Error\n"); + mcc_cfg->mcc_dm_en = 0; + mcc_cfg->reg_cnt = 0; + mcc_cfg->mcc_set = 0; + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC, + HALBB_H2C_DM, bb_h2c); + if (mcc_cfg) + hal_mem_free(bb->hal_com, mcc_cfg, cmdlen); + return; + } + + /* Set Channel number, reg, and val*/ + for (ch_idx = 0; ch_idx < MCC_BAND_NUM; ch_idx++) { + halbb_mem_set(bb, mcc_cfg, 0, cmdlen); + reg_cnt = 0; + mcc_cfg->mcc_dm_en = 1; + mcc_cfg->mcc_ch_idx = ch_idx; + mcc_cfg->mcc_set = 1; + mcc_cfg->phy0_en = 1; + mcc_cfg->phy1_en = 0; + mcc_cfg->ch_lsb = (u8)mcc_dm->mcc_rf_ch[ch_idx].center_ch; + mcc_cfg->ch_msb = (u8)mcc_dm->mcc_rf_ch[ch_idx].band; + for (i = 0; i < NUM_MAX_IGI_CNT; i++) { + regid = mcc_dm->mcc_reg_id[i]; + if (regid == INVALID_INIT_VAL) + break; + reg_cont = &mcc_cfg->mcc_reg_content[i]; + reg_cont->addr_lsb = (u8)mcc_dm->mcc_dm_reg[i]; + reg_cont->addr_msb = (u8)(mcc_dm->mcc_dm_reg[i] >> 8); + reg_cont->bmask_lsb = (u8)(mcc_dm->mcc_dm_mask[i]); + reg_cont->bmask_msb = (u8)(mcc_dm->mcc_dm_mask[i] >> 8); + reg_cont->val_lsb = (u8)(mcc_dm->mcc_dm_val[i][ch_idx]); + reg_cont->val_msb = (u8)(mcc_dm->mcc_dm_val[i][ch_idx] >> 8); + reg_cnt++; + } + mcc_cfg->reg_cnt = reg_cnt; + BB_DBG(bb, DBG_DIG, "MCC H2C SetCH: 0x%x 0x%x 0x%x\n", + bb_h2c[0], bb_h2c[1], bb_h2c[2]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC, + HALBB_H2C_DM, bb_h2c); + } + + if (mcc_cfg) + hal_mem_free(bb->hal_com, mcc_cfg, cmdlen); +} + +void halbb_mccdm_ctrl(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + u32 val[2] = {0}; + + BB_DBG(bb, DBG_DIG, "MCC status: %x\n", mcc_dm->mcc_status_en); + /*MCC stage no change*/ + if (mcc_dm->mcc_status_en == mcc_dm->mcc_pre_status_en) + return; + + /*Not in MCC stage*/ + if (mcc_dm->mcc_status_en != 0) { + /* Disable normal DIG */ + halbb_pause_func(bb, F_DIG, HALBB_PAUSE_NO_SET, HALBB_PAUSE_LV_2, + 2, val); + } + if (mcc_dm->mcc_status_en == 0 && mcc_dm->mcc_pre_status_en != 0) { + Halbb_init_mccdm(bb); + halbb_mccdm_h2ccmd_rst(bb); + /* Enable normal DIG */ + halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2, + val); + } + + mcc_dm->mcc_pre_status_en = mcc_dm->mcc_status_en; +} + +void halbb_fill_mcccmd(struct bb_info *bb, u8 regid, u16 reg_add, u16 mask, + u8 band, u16 val) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + + mcc_dm->mcc_reg_id[regid] = regid; + mcc_dm->mcc_dm_reg[regid] = reg_add; + mcc_dm->mcc_dm_mask[regid] = mask; + mcc_dm->mcc_dm_val[regid][band] = val; +} + +void halbb_mccdm_igi_rst(struct bb_info *bb, u8 clr_port) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + + mcc_dm->mcc_dm_val[0][clr_port] = PD_IDX_MIN; //-102dBm + //mcc_dm->mcc_dm_val[1][clr_port] = 0xff; +} + +#if 0 +void halbb_mcc_igi_chk(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + + if (mcc_dm->mcc_dm_val[0][0] == 0xffff && + mcc_dm->mcc_dm_val[0][1] == 0xffff) { + mcc_dm->mcc_dm_reg[0] = 0xffff; + mcc_dm->mcc_reg_id[0] = 0xff; + } + + if (mcc_dm->mcc_dm_val[1][0] == 0xffff && + mcc_dm->mcc_dm_val[1][1] == 0xffff) { + mcc_dm->mcc_dm_reg[1] = 0xffff; + mcc_dm->mcc_reg_id[1] = 0xff; + } +} +#endif + +u8 halbb_mccdm_pd_lower_bound_cal(struct bb_info *bb, u8 bound, + enum channel_width bw) +{ + /* + Range of bound value: + BW20: 95~33 + BW40: 92~30 + BW80: 89~27 + */ + u8 bw_attenuation = 0; + u8 subband_filter_atteniation = 7; + u8 bound_idx = 0; + + if (bound == 0) { + BB_DBG(bb, DBG_DIG, + "[PD Bound] Set Boundary to default!\n"); + return 0; + } + + if (bw == CHANNEL_WIDTH_20) { + bw_attenuation = 0; + } else if (bw == CHANNEL_WIDTH_40) { + bw_attenuation = 3; + } else if (bw == CHANNEL_WIDTH_80) { + bw_attenuation = 6; + } else { + BB_DBG(bb, DBG_DIG, + "[PD Bound] Only support BW20/40/80 !\n"); + return 0; + } + + bound += (bw_attenuation + subband_filter_atteniation); + // If Boundary dbm is odd, set it to even number + bound = bound % 2 ? bound + 1 : bound; + + if (bound < 40) { + BB_DBG(bb, DBG_DIG, + "[PD Bound] Threshold too high, set to highest level!\n"); + bound = 40; + } + + if (bound > 102) { + BB_DBG(bb, DBG_DIG, + "[PD Bound] Threshold too low, disable PD lower bound function!\n"); + bound = 102; + } + + bound_idx = (102 - bound) >> 1; + + return bound_idx; +} + +void halbb_mccdm_pd_cal(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + struct bb_dig_info *bb_dig = &bb->bb_dig_i; + struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit; + struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i; + u8 shift = 10; + u8 igi_val; + u8 pd_val; + u8 i; + u16 mask0; + u16 reg0; + enum channel_width cbw = CHANNEL_WIDTH_20; + + for (i = 0; i < MCC_BAND_NUM; i++) { + igi_val = mcc_dm->rssi_min[i] >> 1; + igi_val = SUBTRACT_TO_0(igi_val, shift); + igi_val = MIN_2(igi_val, IGI_MAX_PERFORMANCE_MODE); + igi_val = MAX_2(igi_val, 0xc); + igi_val -= MIN_2(igi_val, bb_dig_u->pd_low_th_ofst); + + cbw = mcc_dm->mcc_rf_ch[i].bw; + + pd_val = halbb_mccdm_pd_lower_bound_cal(bb, RSSI_MAX - igi_val, + cbw); + + reg0 = (u16)cr->seg0r_pd_lower_bound_a; + mask0 = (u16)cr->seg0r_pd_lower_bound_a_m; + + halbb_fill_mcccmd(bb, 0, reg0, mask0, i, (u16)pd_val); + + if (mcc_dm->sta_cnt[i] == 0) + halbb_mccdm_igi_rst(bb, i); + } + + BB_DBG(bb, DBG_DIG, "STA cnt %d %d, RSSI_min: %d %d, BW: %d %d, MCC_pd_idx: %d %d\n", + mcc_dm->sta_cnt[0], mcc_dm->sta_cnt[1], + mcc_dm->rssi_min[0] >> 1, mcc_dm->rssi_min[1] >> 1, + mcc_dm->mcc_rf_ch[0].bw, mcc_dm->mcc_rf_ch[1].bw, + mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]); +} + +void halbb_mccdm_switch(struct bb_info *bb) +{ + struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm; + + if (!(bb->ic_type & HALBB_DIG_MCC_SUPPORT_IC)) { + BB_DBG(bb, DBG_DIG, "IC type is not supported\n"); + return; + } + + halbb_mccdm_ctrl(bb); + + if (mcc_dm->mcc_status_en == 0) + return; + BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__); + + /* Set IGI*/ + halbb_mccdm_pd_cal(bb); + + /* Set H2C Cmd*/ + Halbb_mccdm_h2c_handler(bb); +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dig.h b/phl/hal_g6/phy/bb/halbb_dig.h new file mode 100644 index 0000000..3ee7883 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dig.h @@ -0,0 +1,338 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DIG_H__ +#define __HALBB_DIG_H__ + +#define DIG_VERSION "4.0" + +/*@--------------------------[Define] ---------------------------------------*/ +#define BB_LNA_SIZE 7 +#define BB_TIA_SIZE 2 + +#define IGI_RSSI_TH_NUM 5 +#define FA_TH_NUM 4 +#define RSSI_MAX 110 +#define RSSI_MIN 0 +#define IGI_NOLINK 38 +#define LNA_IDX_MAX 6 +#define LNA_IDX_MIN 0 +#define TIA_IDX_MAX 1 +#define TIA_IDX_MIN 0 +#define RXB_IDX_MAX 31 +#define RXB_IDX_MIN 0 +#define LNA6_GAIN 24 +#define LNA5_GAIN 16 +#define LNA4_GAIN 8 +#define LNA3_GAIN 0 +#define LNA2_GAIN (-8) +#define LNA1_GAIN (-16) +#define LNA0_GAIN (-24) +#define TIA1_GAIN_A 20 +#define TIA0_GAIN_A 12 +#define TIA1_GAIN_G 24 +#define TIA0_GAIN_G 16 +#define IGI_OFFSET_MAX 25 /* IGI window size */ +#define IGI_MAX_PERFORMANCE_MODE 0x5a +#define IGI_MAX_BALANCE_MODE 0x3e +#define PD_TH_MAX_RSSI 70 /* -40dBm */ +#define PD_TH_MIN_RSSI 8 /* -102dBm */ +#define PD_TH_BW80_CMP_VAL 6 +#define PD_TH_BW40_CMP_VAL 3 +#define PD_TH_BW20_CMP_VAL 0 +#define PD_TH_SB_FLTR_CMP_VAL 7 +#define DIG_CCX_WD_TRIGTIME 1900 +#define IGI_EDCCA_GAP_LIMIT 35 +#ifdef HALBB_DIG_TDMA_SUPPORT +#define IGI_MAX_AT_STATE_L 0x26 +#define WACHDOG_PERIOD_IN_MS 2000 +#define H_STATE_NUM_MAX 20 +#define L_STATE_NUM_MAX 10 +#endif +#define DIG_RECORD_NUM 6 +#define DIG_LIMIT_PERIOD 60 /*60 sec*/ + +#ifdef HALBB_DBG_TRACE_SUPPORT +#define BB_DIG_DBG(bb, lv, fmt, ...)\ + do {\ + if(bb->dbg_component & DBG_DIG && bb->bb_dig_i.dbg_lv >= lv) {\ + _os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\ + }\ + } while (0) +#else +#define BB_DIG_DBG(bb, lv, fmt, ...) +#endif + +/*@--------------------------[Enum]------------------------------------------*/ +enum dig_noisy_level { + DIG_NOISY_LV0 = 0, /*FA free*/ + DIG_NOISY_LV1 = 1, + DIG_NOISY_LV2 = 2, + DIG_NOISY_LV3 = 3, + DIG_NOISY_LV_MAX = 4 +}; + +#ifdef HALBB_DIG_TDMA_SUPPORT +enum dig_tdma_state { + DIG_TDMA_LOW = 0, + DIG_TDMA_HIGH = 1 +}; +#endif + +enum dig_dbg_level { + DIG_DBG_LV0 = 0, + DIG_DBG_LV1 = 1, + DIG_DBG_LV2 = 2 +}; +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_dig_cr_info { + u32 path0_ib_pbk; + u32 path0_ib_pbk_m; + u32 path0_ib_pkpwr; + u32 path0_ib_pkpwr_m; + u32 path1_ib_pbk; + u32 path1_ib_pbk_m; + u32 path1_ib_pkpwr; + u32 path1_ib_pkpwr_m; + u32 path0_lna_init_idx; + u32 path0_lna_init_idx_m; + u32 path1_lna_init_idx; + u32 path1_lna_init_idx_m; + u32 path0_tia_init_idx; + u32 path0_tia_init_idx_m; + u32 path1_tia_init_idx; + u32 path1_tia_init_idx_m; + u32 path0_rxb_init_idx; + u32 path0_rxb_init_idx_m; + u32 path1_rxb_init_idx; + u32 path1_rxb_init_idx_m; + u32 seg0r_pd_spatial_reuse_en_a; + u32 seg0r_pd_spatial_reuse_en_a_m; + u32 seg0r_pd_lower_bound_a; + u32 seg0r_pd_lower_bound_a_m; + u32 path0_p20_follow_by_pagcugc_en_a; + u32 path0_s20_follow_by_pagcugc_en_a; + u32 path1_p20_follow_by_pagcugc_en_a; + u32 path1_s20_follow_by_pagcugc_en_a; + u32 path0_p20_follow_by_pagcugc_en_a_m; + u32 path0_s20_follow_by_pagcugc_en_a_m; + u32 path1_p20_follow_by_pagcugc_en_a_m; + u32 path1_s20_follow_by_pagcugc_en_a_m; + u32 path0_lna_err_g0_a; + u32 path0_lna_err_g0_a_m; + u32 path0_lna_err_g0_g; + u32 path0_lna_err_g0_g_m; + u32 path0_lna_err_g1_a; + u32 path0_lna_err_g1_a_m; + u32 path0_lna_err_g1_g; + u32 path0_lna_err_g1_g_m; + u32 path0_lna_err_g2_a; + u32 path0_lna_err_g2_a_m; + u32 path0_lna_err_g2_g; + u32 path0_lna_err_g2_g_m; + u32 path0_lna_err_g3_a; + u32 path0_lna_err_g3_a_m; + u32 path0_lna_err_g3_g; + u32 path0_lna_err_g3_g_m; + u32 path0_lna_err_g4_a; + u32 path0_lna_err_g4_a_m; + u32 path0_lna_err_g4_g; + u32 path0_lna_err_g4_g_m; + u32 path0_lna_err_g5_a; + u32 path0_lna_err_g5_a_m; + u32 path0_lna_err_g5_g; + u32 path0_lna_err_g5_g_m; + u32 path0_lna_err_g6_a; + u32 path0_lna_err_g6_a_m; + u32 path0_lna_err_g6_g; + u32 path0_lna_err_g6_g_m; + u32 path0_tia_err_g0_a; + u32 path0_tia_err_g0_a_m; + u32 path0_tia_err_g0_g; + u32 path0_tia_err_g0_g_m; + u32 path0_tia_err_g1_a; + u32 path0_tia_err_g1_a_m; + u32 path0_tia_err_g1_g; + u32 path0_tia_err_g1_g_m; + u32 path1_lna_err_g0_a; + u32 path1_lna_err_g0_a_m; + u32 path1_lna_err_g0_g; + u32 path1_lna_err_g0_g_m; + u32 path1_lna_err_g1_a; + u32 path1_lna_err_g1_a_m; + u32 path1_lna_err_g1_g; + u32 path1_lna_err_g1_g_m; + u32 path1_lna_err_g2_a; + u32 path1_lna_err_g2_a_m; + u32 path1_lna_err_g2_g; + u32 path1_lna_err_g2_g_m; + u32 path1_lna_err_g3_a; + u32 path1_lna_err_g3_a_m; + u32 path1_lna_err_g3_g; + u32 path1_lna_err_g3_g_m; + u32 path1_lna_err_g4_a; + u32 path1_lna_err_g4_a_m; + u32 path1_lna_err_g4_g; + u32 path1_lna_err_g4_g_m; + u32 path1_lna_err_g5_a; + u32 path1_lna_err_g5_a_m; + u32 path1_lna_err_g5_g; + u32 path1_lna_err_g5_g_m; + u32 path1_lna_err_g6_a; + u32 path1_lna_err_g6_a_m; + u32 path1_lna_err_g6_g; + u32 path1_lna_err_g6_g_m; + u32 path1_tia_err_g0_a; + u32 path1_tia_err_g0_a_m; + u32 path1_tia_err_g0_g; + u32 path1_tia_err_g0_g_m; + u32 path1_tia_err_g1_a; + u32 path1_tia_err_g1_a_m; + u32 path1_tia_err_g1_g; + u32 path1_tia_err_g1_g_m; +}; + +struct agc_gaincode_set { + u8 lna_idx; + u8 tia_idx; + u8 rxb_idx; +}; + +struct bb_dig_fa_info { + u16 fa_r_cck_onesec; + u16 fa_r_ofdm_onesec; + u16 fa_r_onesec; /* overall fa_ratio */ +}; + +struct bb_dig_op_para_unit { + bool dyn_pd_th_en; + u8 igi_rssi_th[IGI_RSSI_TH_NUM]; + u16 fa_th[FA_TH_NUM]; /* permil */ +}; + +#ifdef HALBB_DIG_DAMPING_CHK +struct bb_dig_record_info { + u8 igi_bitmap; /*@Don't add any new parameter before this*/ + u8 igi_history[DIG_RECORD_NUM]; + u32 fa_history[DIG_RECORD_NUM]; + bool damping_lock_en; + u8 damping_limit_val; /*@Limit IGI_dyn_min*/ + u32 limit_time; + u8 limit_rssi; /*s(8,1)*/ +}; +#endif + +/* struct for state unit, i.e., L/H */ +struct bb_dig_op_unit { +#ifdef HALBB_DIG_TDMA_SUPPORT + enum dig_tdma_state state_identifier; /* L/H */ +#endif + struct agc_gaincode_set cur_gaincode; + enum dig_noisy_level cur_noisy_lv; + struct agc_gaincode_set force_gaincode; + struct bb_dig_op_para_unit dig_op_para; + u16 fa_r_acc; /* acced one shot fa_ratio */ + u16 fa_r_avg; /* acced one shot fa_ratio */ + u8 fa_valid_state_cnt; + u8 state_num_lmt; + u8 passed_state_cnt; + u8 igi_fa_rssi; /*final IGI calaulated by FA & RSSI*/ + u8 fa_rssi_ofst; + u8 abs_igi_max; + u8 abs_igi_min; + u8 dyn_igi_max; + u8 dyn_igi_min; + u8 pd_low_th_ofst; /* pd low safe cca region */ + bool sdagc_follow_pagc_en; +}; + +struct bb_dig_info { + enum dig_op_mode dig_mode; + enum dig_op_mode pre_dig_mode; + struct bb_dig_cr_info bb_dig_cr_i; + struct agc_gaincode_set max_gaincode; + u8 igi_rssi; //rssi_min + u8 ib_pbk; + s8 ib_pkpwr; + s8 lna_gain_a[BB_LNA_SIZE]; + s8 lna_gain_g[BB_LNA_SIZE]; + s8 *lna_gain; + s8 tia_gain_a[BB_TIA_SIZE]; + s8 tia_gain_g[BB_TIA_SIZE]; + s8 *tia_gain; + s8 le_igi_ofst; /* low end mode IGI offset */ + struct bb_dig_op_unit *p_cur_dig_unit; + struct bb_dig_op_unit dig_state_h_i; /* high state */ +#ifdef HALBB_DIG_TDMA_SUPPORT + struct bb_dig_op_unit dig_state_l_i; /* low state */ + bool gaincode_update_en; + u16 tdma_passed_time_acc; /* check if 1sec reach */ + u8 tdma_timestamp_pre; + u8 tdma_timestamp_cur; + struct halbb_timer_info dig_timer_i; +#endif +#ifdef HALBB_ENV_MNTR_SUPPORT + u8 ccx_timestamp; + struct ccx_para_info ccx_para_i; + bool ccx_is_triggered; +#endif + struct bb_dig_fa_info dig_fa_i; + enum dig_dbg_level dbg_lv; + u32 rvrt_val[DIG_PAUSE_INFO_SIZE]; /*[Pause fucntion] must set to u32*/ + u16 igi_pause_cnt; /*consective pause counter*/ + bool need_update; + u16 dig_hold_cnt; +#ifdef HALBB_DIG_DAMPING_CHK + struct bb_dig_record_info bb_dig_record_i; + u8 rls_rssi_diff_th; /*s(8,1)*/ + bool dig_dl_en; /*@damping limit function enable*/ +#endif +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +#ifdef HALBB_DIG_TDMA_SUPPORT +void halbb_dig_timercheck_watchdog(struct bb_info*); +void halbb_tdmadig_io_en(struct bb_info *bb); +void halbb_dig_timer_init(struct bb_info *bb); +#endif + +void halbb_dig_lps(struct bb_info *bb); +void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new); +void halbb_dig_new_entry_connect(struct bb_info *bb); +void halbb_dig(struct bb_info *bb); +void halbb_dig_init(struct bb_info *bb); +void halbb_dig_deinit(struct bb_info *bb); +void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_dig_init(struct bb_info *bb); + +void* halbb_get_dig_fa_statistic(struct bb_info *bb); +void halbb_set_dig_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len); +#ifdef HALBB_DIG_MCC_SUPPORT +void Halbb_init_mccdm(struct bb_info *bb); +void halbb_mccdm_switch(struct bb_info *bb); +u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h); +#endif +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dig_ex.h b/phl/hal_g6/phy/bb/halbb_dig_ex.h new file mode 100644 index 0000000..7f32748 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dig_ex.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DIG_EX_H__ +#define __HALBB_DIG_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define DIG_PAUSE_INFO_SIZE 2 +/*@--------------------------[Enum]------------------------------------------*/ +enum dig_op_mode { + DIG_ORIGIN = 0, +#ifdef HALBB_DIG_TDMA_SUPPORT + DIG_TDMA = 1, + DIG_TDMA_ADV = 2, +#endif + DIG_SIMPLE = 3, + DIG_NONE +}; + +enum dig_pause_case { + PAUSE_OFDM = 0, + PAUSE_OFDM_CCK = 1 +}; +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_info; + +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_dig_mode_update(struct bb_info *bb, enum dig_op_mode mode); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.c b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.c new file mode 100644 index 0000000..7ef4a6f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.c @@ -0,0 +1,441 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_DYN_CSI_RSP_SUPPORT + +bool halbb_dyn_csi_rsp_rlt_get(struct bb_info *bb){ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + + BB_DBG(bb, DBG_DCR, "CSI Rsp Rlt = %d.\n", bf->is_csi_rsp_en); + return bf->is_csi_rsp_en; +} + +void halbb_csi_rsp_rlt(struct bb_info *bb, bool en) +{ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + enum dcr_csi_rsp; + + bool ret=false; + + if (en == bf->is_csi_rsp_en) + return; + + bf->is_csi_rsp_en = en; +#if 0 + if (en) { + BB_DBG(bb, DBG_DCR,"[Enable CSI Rsp.]\n"); + //Enable CSI Rsp. + //val = hal_read8(bb->hal_com, 0xcd80); + //val = val | 0x7; + //hal_write8(bb->hal_com, 0xcd80, val); + //ret = rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, bb->bb_phy_idx); + //return dcr_csi_rsp_dis; + } else { + BB_DBG(bb, DBG_DCR,"[Disable CSI Rsp.]\n"); + //Disable CSI Rsp. + //val = hal_read8(bb->hal_com, 0xcd80); + //val = val & ~(0x7); + //hal_write8(bb->hal_com, 0xcd80, val); + //ret = rtw_hal_mac_ax_deinit_bfee(bb->hal_com, bb->bb_phy_idx); + //return dcr_csi_rsp_en; + } +#endif +} + +bool halbb_dcr_is_he_connect(struct bb_info *bb) { + struct rtw_phl_stainfo_t *sta; + struct bb_link_info *link = &bb->bb_link_i; + bool rlt = false; + + if (!link->is_linked) { + return false; + } + + if (!link->is_one_entry_only) + return false; + + sta = bb->phl_sta_info[bb->bb_link_i.one_entry_macid]; + + if (sta && sta->wmode & WLAN_MD_11AX) { + BB_DBG(bb, DBG_DCR, "AX Support!!!!"); + rlt = true; + + } + return rlt; +} + +void halbb_dcr_config_ch_info_he(struct bb_info *bb) { + struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i; + struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i; + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw; + + if (bf->dcr_bw == bw) + return; + + bf->dcr_bw = bw; + BB_DBG(bb, DBG_IC_API, "dcr_bw=%d\n", bf->dcr_bw); + + if (bw == CHANNEL_WIDTH_80) { + cfg->ch_i_grp_num_he = 3; + } else if (bw == CHANNEL_WIDTH_40) { + cfg->ch_i_grp_num_he = 2; + } else { /*if (bw == CHANNEL_WIDTH_20)*/ + if (bb->ic_type == BB_RTL8852B) + cfg->ch_i_grp_num_he = 1; + else + cfg->ch_i_grp_num_he = 2; + } + BB_DBG(bb, DBG_IC_API, "grp_num_he=%d\n", cfg->ch_i_grp_num_he); + + cfg->ch_i_cmprs = 1; + cfg->ch_i_ele_bitmap = 0x303; /*Nr X Nc: 2 X 2*/ + + halbb_cfg_ch_info_cr(bb, cfg); +} + +bool halbb_dcr_get_ch_raw_info(struct bb_info *bb, bool is_csi_en) +{ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + struct bb_ch_info_physts_info *ch_physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i; + bool get_ch_rpt_success = false; + + if (is_csi_en) { + BB_DBG(bb, DBG_DCR, "CSI Rsp enable need to disable for CH Est.\n"); + /* Disable CSI Rsp*/ + rtw_hal_mac_ax_deinit_bfee(bb->hal_com, bb->bb_phy_idx); + halbb_delay_ms(bb, bf->ch_est_dly); + } + + get_ch_rpt_success = halbb_ch_info_wait_from_physts(bb, bf->get_phy_sts_dly, bf->get_phy_sts_dly, HE_PKT); + + if (get_ch_rpt_success && ch_physts->ch_info_len < 200) + get_ch_rpt_success = false; + + if (is_csi_en) { + BB_DBG(bb, DBG_DCR, "Restore CSI Rsp.\n"); + /* enable CSI Rsp*/ + rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, bb->bb_phy_idx); + } + + return get_ch_rpt_success; +} + +bool halbb_dcr_en(struct bb_info *bb, bool en){ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + bool ret = true; + u32 id = bb->phl_com->id.id & 0xFFFF; + + if (id == 0x209 || id == 0x309) { + BB_DBG(bb, DBG_DCR, "DCR_en=%d, cid=0x%x\n", en, id); + } else { + return false; + } + + if (en) { + //Allocate Buffer + ret = halbb_ch_info_buf_alloc(bb); + if (ret) { + bf->dyn_csi_rsp_en = true; + } + } else { + halbb_ch_info_buf_rls(bb); + halbb_dcr_reset(bb); + bf->dyn_csi_rsp_en = false; + } + + return ret; +} + +void halbb_dcr_init(struct bb_info *bb) +{ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + + BB_DBG(bb, DBG_DCR, "%s\n", __func__); + + bf->dyn_csi_rsp_en = false; + bf->is_csi_rsp_en = true; + bf->ch_est_dly= 50; + bf->get_phy_sts_dly = 5; + bf->max_est_tone_num = 54; + bf->ch_chk_cnt = 0; + bf->dyn_csi_rsp_dbg_en = 0; + bf->dcr_bw = CHANNEL_WIDTH_MAX; +} + +void halbb_dcr_reset(struct bb_info *bb) +{ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + + bf->ch_chk_cnt = 0; + bf->is_csi_rsp_en = true; +} + +bool halbb_dcr_abort(struct bb_info *bb) +{ + struct bb_link_info *link = &bb->bb_link_i; + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + + if (!bf->dyn_csi_rsp_en) { + BB_DBG(bb, DBG_DCR,"[Dyn CSI RSP DISABLE]\n"); + halbb_csi_rsp_rlt(bb, true); + return true; + } + + if (!link->is_one_entry_only) { + BB_DBG(bb, DBG_DCR,"[is_one_entry_only = 0]\n"); + halbb_csi_rsp_rlt(bb, true); + return true; + } + + if (!link->is_linked) { + if (link->first_disconnect) + halbb_dcr_reset(bb); + return true; + } + + if(bf->dyn_csi_rsp_dbg_en == 1){ + BB_DBG(bb, DBG_DCR,"[Disable by echo cmd for dbg]\n"); + halbb_csi_rsp_rlt(bb, true); + return true; + } + + if (!halbb_dcr_is_he_connect(bb)) { + //Disable if not HE Mode + BB_DBG(bb, DBG_DCR, "DCR disable cause not in HE mode!\n"); + halbb_csi_rsp_rlt(bb, true); + return true; + } + + return false; +} + +bool halbb_dcr_ch_est(struct bb_info *bb, u16 *addr) +{ + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + u32 ix; + u32 h11h22, h12h21, chdiff; + s32 utility = 0; + bool iscablelink = false; + + for (ix = 0; ix < bf->max_est_tone_num; ix++) { +#if 0 + BB_DBG(bb, DBG_DCR,"Tone Group Idx = %d\n",ix); + BB_DBG(bb, DBG_DCR,"H11 = %s%d.%d + %sj%d.%d", + ((addr[ix*8+0] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+0]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+0]) & 0xfff, 12), + ((addr[ix*8+1] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+1]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+1]) & 0xfff, 12)); + BB_DBG(bb, DBG_DCR,"H22 = %s%d.%d + %sj%d.%d", + ((addr[ix*8+6] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+6]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+6]) & 0xfff, 12), + ((addr[ix*8+7] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+7]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+7]) & 0xfff, 12)); + BB_DBG(bb, DBG_DCR,"H12 = %s%d.%d + %sj%d.%d", + ((addr[ix*8+2] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+2]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+2]) & 0xfff, 12), + ((addr[ix*8+3] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+3]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+3]) & 0xfff, 12)); + BB_DBG(bb, DBG_DCR,"H21 = %s%d.%d + %sj%d.%d", + ((addr[ix*8+4] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+4]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+4]) & 0xfff, 12), + ((addr[ix*8+4] & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(addr[ix*8+5]) >> 12), + halbb_show_fraction_num((u16)ABS_16(addr[ix*8+5]) & 0xfff, 12)); +#endif + h11h22 = ((u16)ABS_16(addr[ix*8+0]))+((u16)ABS_16(addr[ix*8+1])) + +((u16)ABS_16(addr[ix*8+6]))+((u16)ABS_16(addr[ix*8+7])); + h12h21 =((u16)ABS_16(addr[ix*8+2]))+((u16)ABS_16(addr[ix*8+3])) + +((u16)ABS_16(addr[ix*8+4]))+((u16)ABS_16(addr[ix*8+5])); + + if (h11h22 != 0 && h12h21 != 0) { + chdiff = DIFF_2(h11h22, h12h21); + //BB_DBG(bb, DBG_DCR, "H11H22 = %d, H12H22= %d ,Diff= %d\n", h11h22, h12h21, chdiff); + if (chdiff > 10000) + utility += 2; + else if (chdiff > 5000) + utility += 1; + else + utility -= 2; + } + } + + if (utility > 0) + iscablelink = true; + + BB_DBG(bb, DBG_DCR, "utility = %d, isCableLink = %d\n", + utility, iscablelink); + + return iscablelink; +} + +void halbb_dyn_csi_rsp_main(struct bb_info *bb) +{ + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i; + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i; + struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i; + u16 pkt_cnt_ss = 0; + //u8 i = 0, j =0; + //u8 rate_num = bb->num_rf_path, ss_ofst = 0; + u8 ret = dcr_csi_rsp_en; + bool iscablelink = false, is_csi_rsp_en = true; + + if (halbb_dcr_abort(bb)) + return; + +#if 1 + if (pkt_cnt->he_pkt_not_zero) { + halbb_dcr_config_ch_info_he(bb); + pkt_cnt_ss = pkt_cnt->pkt_cnt_t; + } +#else + //Cal HE RX PKT CNT + for (i = 0; i < rate_num; i++) { + ss_ofst = HE_VHT_NUM_MCS * i; + for (j = 0; j < HE_VHT_NUM_MCS ; j++) { + pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j]; + + } + } +#endif + + BB_DBG(bb, DBG_DCR,"[CH Est. dly = %d,Get Physts dly = %d, rpt get = %d, CH chk cnt =%d, HE Pkt=%03d]\n", + bf->ch_est_dly, bf->get_phy_sts_dly, physts->ch_info_state, + bf->ch_chk_cnt, pkt_cnt_ss); + + if ((bf->ch_chk_cnt >= 3) && (pkt_cnt_ss > 400)) { + BB_DBG(bb, DBG_DCR,"[No Need to Chk Ch and Rx Cnt > 400]\n"); + halbb_csi_rsp_rlt(bb, true); + return; + + } + + if (!halbb_dcr_get_ch_raw_info(bb, bf->is_csi_rsp_en)) { /*get report fail*/ + BB_DBG(bb, DBG_DCR,"[Failed To Get Report]\n"); + if (bf->ch_chk_cnt > 0) + bf->ch_chk_cnt--; + //halbb_csi_rsp_rlt(bb, true); + return; + } + + //CSI RAW INFO Get + BB_DBG(bb, DBG_DCR,"[Rpt Get !!!]\n"); + if (bf->ch_chk_cnt >= 3) { + BB_DBG(bb, DBG_DCR,"[No Need to Check Channel]\n"); + halbb_csi_rsp_rlt(bb, true); + return; + } + + //check if cable link + iscablelink = halbb_dcr_ch_est(bb, buf->octet); + halbb_mem_set(bb, buf->octet, 0, buf->ch_info_buf_len); + + if (iscablelink) { + BB_DBG(bb, DBG_DCR,"[CSI Rsp. Disable !!!]\n"); + is_csi_rsp_en = false; + + if (bf->ch_chk_cnt > 0) + bf->ch_chk_cnt--; + ret = dcr_csi_rsp_dis; + } else { + BB_DBG(bb, DBG_DCR,"[CSI Rsp. Enable !!!]\n"); + is_csi_rsp_en = true; + if (bf->ch_chk_cnt < 3) + bf->ch_chk_cnt++; + ret = dcr_csi_rsp_en; + } + halbb_csi_rsp_rlt(bb, is_csi_rsp_en); +} + +void halbb_dyn_csi_rsp_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len) +{ + struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i; + struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i; + u32 val[10] = {0}; + bool dcr_en = false; + bool bool_tmp; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]); + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{0: Config Channel Est Delay Unit:ms\n"); + } else if (val[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + if (val[1] == 1){ + bf->dyn_csi_rsp_dbg_en = 0; + } else { + bf->dyn_csi_rsp_dbg_en = 1; + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Dynamic CSI Rsp Enable = %d\n", + bf->dyn_csi_rsp_dbg_en); + } else if (val[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Config Trainning Delay \n"); + bf->ch_est_dly = (u32)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Trainning Delay = %d ms \n", + bf->ch_est_dly); + } else if (val[0] == 3) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Config Get PHY STS Delay \n"); + + bf->get_phy_sts_dly = (u32)val[1]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "GetPhySTS = %d ms \n", + bf->get_phy_sts_dly); + + } else if (val[0] == 4) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Config Max Tone Cnt \n"); + + bf->max_est_tone_num = (u32)val[1]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "Config Max Tone Cnt = %d \n", + bf->max_est_tone_num); + } else if (val[0] == 5) { + bool_tmp = halbb_dcr_is_he_connect(bb); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, + *_out_len - *_used, "is_he_connect=%d\n", bool_tmp); + } +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.h b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.h new file mode 100644 index 0000000..5fb9caf --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DYN_CSI_RSP_H__ +#define __HALBB_DYN_CSI_RSP_H__ +#ifdef HALBB_DYN_CSI_RSP_SUPPORT + +struct bf_ch_raw_info { + /*result*/ + bool is_csi_rsp_en; + /*state machine*/ + u8 dyn_csi_rsp_dbg_en; + u8 dyn_csi_rsp_en; + u8 ch_chk_cnt; + /*set val*/ + u32 ch_est_dly; + u32 get_phy_sts_dly; + u32 max_est_tone_num; + s32 cablelink_cnt_th; + enum channel_width dcr_bw; +}; + +struct bb_info; + +/*@--------------------------[Enum]------------------------------------------*/ +enum dcr_csi_rsp { + dcr_csi_rsp_dis = 0, /*Disale*/ + dcr_csi_rsp_en = 1, /*Enable*/ +}; +void halbb_dcr_init(struct bb_info *bb); +void halbb_dcr_reset(struct bb_info *bb); +void halbb_dyn_csi_rsp_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len); +void halbb_dyn_csi_rsp_main(struct bb_info *bb); +#endif +#endif diff --git a/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp_ex.h b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp_ex.h new file mode 100644 index 0000000..5f2d9f7 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_dyn_csi_rsp_ex.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_DYN_CSI_RSP_EX_H__ +#define __HALBB_DYN_CSI_RSP_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +bool halbb_dcr_en(struct bb_info *bb, bool en); +bool halbb_dyn_csi_rsp_rlt_get(struct bb_info *bb); + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_edcca.c b/phl/hal_g6/phy/bb/halbb_edcca.c new file mode 100644 index 0000000..f09d981 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_edcca.c @@ -0,0 +1,614 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_EDCCA_SUPPORT +bool halbb_edcca_abort(struct bb_info *bb) +{ + if (!(bb->support_ability & BB_EDCCA)) { + BB_DBG(bb, DBG_EDCCA, "edcca disable\n"); + return true; + } + + if (bb->pause_ability & BB_EDCCA) { + BB_DBG(bb, DBG_EDCCA, "Return edcca pause\n"); + return true; + } + + return false; +} + +void halbb_set_edcca_thre(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; + u32 l2h = bb_edcca->th_h; + + halbb_set_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m, l2h); + halbb_set_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m, l2h); + + halbb_set_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m, (u32)bb_edcca->th_hl_diff); +} + +u8 halbb_edcca_thre_transfer_rssi(struct bb_info *bb) +{ + u8 rssi_min = bb->bb_ch_i.rssi_min >> 1; + u8 edcca_thre = 0; + + /*mapping between rssi and edcca thre */ + edcca_thre = rssi_min -110 + 128; + + if (edcca_thre <= EDCCA_TH_L2H_LB) + edcca_thre = EDCCA_TH_L2H_LB; + + return edcca_thre; +} + +void halbb_edcca_thre_calc(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + u8 band = bb->hal_com->band[0].cur_chandef.band; + u8 th_h = 0; + + BB_DBG(bb, DBG_EDCCA, "[EDCCA] Mode=%d, Band=%d\n", + bb_edcca->edcca_mode, band); + + BB_DBG(bb, DBG_EDCCA, + "[EDCCA] Adapt-5G_th=%d(dBm), Adapt-2.4G_th=%d(dBm),Carrier-sense_th=%d(dBm)\n", + bb_edcca->th_h_5g - 128, bb_edcca->th_h_2p4g - 128, + bb_edcca->th_h_cs - 128); + + if (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) { + BB_DBG(bb, DBG_EDCCA, "Normal Mode without EDCCA\n"); + th_h = halbb_edcca_thre_transfer_rssi(bb); + bb_edcca->th_hl_diff = EDCCA_HL_DIFF_NORMAL; + } else if (bb_edcca->edcca_mode == EDCCA_ADAPT_MODE) { + if (band == BAND_ON_24G) + th_h = bb_edcca->th_h_2p4g; + else + th_h = bb_edcca->th_h_5g; + bb_edcca->th_hl_diff = EDCCA_HL_DIFF_ADPTVTY; + } else if (bb_edcca->edcca_mode == EDCCA_CARRIER_SENSE_MODE) { + th_h = bb_edcca->th_h_cs; + bb_edcca->th_hl_diff = EDCCA_HL_DIFF_ADPTVTY; + } + bb_edcca->th_h = th_h; + bb_edcca->th_l = bb_edcca->th_h - bb_edcca->th_hl_diff; + + halbb_set_edcca_thre(bb); +} + +void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + + if (val_len != 1) { + BB_DBG(bb, DBG_EDCCA, "[Error][EDCCA]Need val_len=1\n"); + return; + } + BB_DBG(bb, DBG_EDCCA, "[%s] len=%d, val[0]=0x%x\n", __func__, val_len, val_buf[0]); + + bb_edcca->th_h = (u8)val_buf[0]; + halbb_set_edcca_thre(bb); +} + +void halbb_edcca_event_nofity(struct bb_info *bb, u8 pause_type) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + u8 pause_result = 0; + u32 val[5] = {0}; + + if (bb_edcca->edcca_mode != EDCCA_NORMAL_MODE) + return; + + val[0] = EDCCA_MAX; + pause_result = halbb_pause_func(bb, F_EDCCA, pause_type, HALBB_PAUSE_LV_2, 1, val); +} + +void halbb_edcca_log(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt; + struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; + enum channel_width bw = 0; + u8 edcca_p_th = 0; + u8 edcca_s_th = 0; + u8 edcca_diff = 0; + bool edcca_en = 0; + + bw = bb->hal_com->band[0].cur_chandef.bw; + + switch (bw) { + case CHANNEL_WIDTH_80_80: + case CHANNEL_WIDTH_160: + BB_DBG(bb, DBG_EDCCA, + "pwdb per20{0,1,2,3,4,5,6,7}={%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, rpt->pwdb_3, + rpt->pwdb_4, rpt->pwdb_5, rpt->pwdb_6, rpt->pwdb_7); + BB_DBG(bb, DBG_EDCCA, + "path=%d, flag {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20, + rpt->flag_s40, rpt->flag_s80); + BB_DBG(bb, DBG_EDCCA, + "pwdb {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20, rpt->pwdb_s40, + rpt->pwdb_s80); + break; + case CHANNEL_WIDTH_80: + BB_DBG(bb, DBG_EDCCA, + "pwdb per20{0,1,2,3}={%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, rpt->pwdb_3); + BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20,s20,s40}={%d,%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20, + rpt->flag_s40); + BB_DBG(bb, DBG_EDCCA, + "pwdb {FB,p20,s20,s40}={%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20, rpt->pwdb_s40); + break; + case CHANNEL_WIDTH_40: + BB_DBG(bb, DBG_EDCCA, "pwdb per20{0,1}={%d,%d}(dBm)\n", rpt->pwdb_0, + rpt->pwdb_1); + BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20,s20}={%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20); + BB_DBG(bb, DBG_EDCCA, "pwdb {FB,p20,s20}={%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20); + break; + case CHANNEL_WIDTH_20: + BB_DBG(bb, DBG_EDCCA, "pwdb per20{0}={%d}(dBm)\n", rpt->pwdb_0); + BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20}={%d,%d}\n", rpt->path, + rpt->flag_fb, rpt->flag_p20); + BB_DBG(bb, DBG_EDCCA, "pwdb {FB,p20}={%d,%d}(dBm)\n", rpt->pwdb_fb, + rpt->pwdb_p20); + break; + default: + break; + } + + edcca_en = (bool)halbb_get_reg(bb, cr->r_snd_en, cr->r_snd_en_m); + edcca_p_th = (u8)halbb_get_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m); + edcca_s_th = (u8)halbb_get_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m); + edcca_diff = (u8)halbb_get_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m); + + BB_DBG(bb, DBG_EDCCA, + "reg val{en, p20_h_th, sec_h_th, diff}:{%d, %d, %d, %d}\n", + edcca_en, edcca_p_th, edcca_s_th, edcca_diff); +} + +void halbb_edcca_get_result(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt; + struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; + u32 tmp = 0; + u64 tmp_linear = 0; + enum channel_width bw = 0; + + bw = bb->hal_com->band[0].cur_chandef.bw; + + halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, 0x0); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m); + rpt->pwdb_1 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_0 = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m); + rpt->path = (u8)((tmp & 0x6) >> 1); + rpt->flag_s80 = (bool)((tmp & BIT(3)) >> 3); + rpt->flag_s40 = (bool)((tmp & BIT(4)) >> 4); + rpt->flag_s20 = (bool)((tmp & BIT(5)) >> 5); + rpt->flag_p20 = (bool)((tmp & BIT(6)) >> 6); + rpt->flag_fb = (bool)((tmp & BIT(7)) >> 7); + rpt->pwdb_s20 = (s8)(((tmp & MASKBYTE1) >> 8) - 256); + rpt->pwdb_p20 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_fb = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + + switch (bw) { + case CHANNEL_WIDTH_80_80: + case CHANNEL_WIDTH_160: + halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, + 0x5); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m); + rpt->pwdb_3 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_2 = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m); + rpt->pwdb_s80 = (s8)(((tmp & MASKBYTE1) >> 8) - 256); + rpt->pwdb_s40 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + + halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, + 0x2); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m); + rpt->pwdb_5 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_4 = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + + halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, + 0x3); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m); + rpt->pwdb_7 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_6 = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + break; + case CHANNEL_WIDTH_80: + halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, + 0x5); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m); + rpt->pwdb_3 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + rpt->pwdb_2 = (s8)(((tmp & MASKBYTE3) >> 24) - 256); + tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m); + rpt->pwdb_s80 = (s8)(((tmp & MASKBYTE1) >> 8) - 256); + rpt->pwdb_s40 = (s8)(((tmp & MASKBYTE2) >> 16) - 256); + break; + case CHANNEL_WIDTH_40: + /*52A/52B/52C has hw bug of pwdb-FB is 0 when bw=40M*/ + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + if ((rpt->pwdb_p20 == (s8)(EDCCA_PWDB_EXCLU_TX)) || + (rpt->pwdb_s20 == (s8)(EDCCA_PWDB_EXCLU_TX))) { + rpt->pwdb_fb = (s8)(EDCCA_PWDB_EXCLU_TX); + } else { + tmp = (u32)EDCCA_PWDB_TO_RSSI(rpt->pwdb_p20); + tmp_linear = halbb_db_2_linear(tmp); + tmp = (u32)EDCCA_PWDB_TO_RSSI(rpt->pwdb_s20); + tmp_linear += halbb_db_2_linear(tmp); + tmp_linear = (tmp_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; + tmp = halbb_convert_to_db(tmp_linear); + rpt->pwdb_fb = (s8)(tmp - 110); + } + } + break; + default: + break; + } +} + +void halbb_edcca(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + + if (halbb_edcca_abort(bb)) + return; + + bb_edcca->edcca_mode = bb->phl_com->edcca_mode; + halbb_edcca_thre_calc(bb); + BB_DBG(bb, DBG_EDCCA, "th_h=%d(dBm), th_l=%d(dBm)\n", + bb_edcca->th_h - 128, bb_edcca->th_l - 128); + halbb_edcca_get_result(bb); + halbb_edcca_log(bb); +} + +void halbb_fw_edcca(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct rtw_phl_com_t *phl = bb->phl_com; + struct rtw_hal_com_t *hal = bb->hal_com; + u8 band = bb->hal_com->band[0].cur_chandef.band; + struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i; + u8 cmdlen; + bool ret_val = false; + u32 *bb_h2c = (u32 *)fw_edcca_i; + cmdlen = sizeof(struct bb_h2c_fw_edcca); + + bb_edcca->edcca_mode = phl->edcca_mode; + //bb_edcca->edcca_mode = EDCCA_ADAPT_MODE; + + if (halbb_edcca_abort(bb)) + return; + + /* FW workaround only for 8852A CAV */ + if (!((hal->cv == CAV) && (hal->chip_id == CHIP_WIFI6_8852A))) + return; + + if (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) { + BB_DBG(bb, DBG_EDCCA, "Normal Mode without FW EDCCA\n"); + return; + } + + BB_DBG(bb, DBG_EDCCA, "FW EDCCA start\n"); + + fw_edcca_i->mode = bb_edcca->edcca_mode; + fw_edcca_i->band = bb->hal_com->band[0].cur_chandef.band; + + BB_DBG(bb, DBG_EDCCA, "[EDCCA] Mode=%d, Band=%d\n", + fw_edcca_i->mode, fw_edcca_i->band); + BB_DBG(bb, DBG_EDCCA, "[EDCCA] Adapt-5G_th=-%d, Adapt-2.4G_th=-%d,Carrier-sense_th=-%d\n", + fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4, + fw_edcca_i->pwr_th_cs); + + BB_DBG(bb, DBG_FW_INFO, "[FW][H2C] h2c conent[0]=%x\n", bb_h2c[0]); + BB_DBG(bb, DBG_FW_INFO, "[FW][H2C] h2c conent[1]=%x\n", bb_h2c[1]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_EDCCA, + HALBB_H2C_DM, bb_h2c); + if (ret_val == false) + BB_WARNING(" H2C cmd: FW Tx error!!\n"); +} + +void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt; + struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i; + enum channel_width bw = 0; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + bw = bb->hal_com->band[0].cur_chandef.bw; + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[EDCCA] Set power threshold(-dBm): {1} {Adapt-5G_th} {Adapt-2.4G_th} {Carrier-sense_th}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[FW EDCCA][8852A CAV] Set power threshold(-dBm): {2} {Adapt-5G_th} {Adapt-2.4G_th} {Carrier-sense_th}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[EDCCA] Set EDCCA mode: {3} {mode 0:normal mode, 1:Adaptivity, 2: Carrier sense}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Show Power threshold: {100}\n"); + } else { + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]); + + bb_edcca->th_h_5g = (u8)var[1]; + bb_edcca->th_h_2p4g = (u8)var[2]; + bb_edcca->th_h_cs = (u8)var[3]; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Adapt-5G_th=-%d(dBm), Adapt-2.4G_th=-%d(dBm), Carrier-sense_th=-%d(dBm)\n", + bb_edcca->th_h_5g, bb_edcca->th_h_2p4g, + bb_edcca->th_h_cs); + + bb_edcca->th_h_5g = 0 - (bb_edcca->th_h_5g) + 128; + bb_edcca->th_h_2p4g = 0 - (bb_edcca->th_h_2p4g) + 128; + bb_edcca->th_h_cs = 0 - (bb_edcca->th_h_cs) + 128; + + + } else if (var[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]); + + fw_edcca_i->pwr_th_5g = (u8)var[1]; + fw_edcca_i->pwr_th_2p4 = (u8)var[2]; + fw_edcca_i->pwr_th_cs = (u8)var[3]; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set FW Adapt-5G_th=-%d, Adapt-2.4G_th=-%d, Carrier-sense_th=-%d\n", + fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4, + fw_edcca_i->pwr_th_cs); + + halbb_fw_edcca(bb); + + } else if (var[0] == 3) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + + bb_edcca->edcca_mode = (u8)var[1]; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set FW EDCCA mode = %s\n", (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) ? "Normal mode" : "Adaptivity/Carrier Sense mode"); + + halbb_fw_edcca(bb); + + } else if (var[0] == 100) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adapt-5G_th=%d(dBm), Adapt-2.4G_th=%d(dBm), Carrier-sense_th=%d(dBm)\n", + bb_edcca->th_h_5g - 128, + bb_edcca->th_h_2p4g -128, + bb_edcca->th_h_cs - 128); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Mode=%d, th_h=%d(dBm), th_l=%d(dBm)\n", + bb_edcca->edcca_mode, bb_edcca->th_h - 128, + bb_edcca->th_l - 128); + + halbb_edcca_get_result(bb); + switch (bw) { + case CHANNEL_WIDTH_80_80: + case CHANNEL_WIDTH_160: + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb per20{0,1,2,3,4,5,6,7}={%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, + rpt->pwdb_3, rpt->pwdb_4, rpt->pwdb_5, + rpt->pwdb_6, rpt->pwdb_7); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "path-%d, flag {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, + rpt->flag_s20, rpt->flag_s40, + rpt->flag_s80); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, + rpt->pwdb_s20, rpt->pwdb_s40, + rpt->pwdb_s80); + break; + case CHANNEL_WIDTH_80: + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb per20{0,1,2,3}={%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, + rpt->pwdb_3); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "path-%d, flag {FB,p20,s20,s40}={%d,%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, + rpt->flag_s20, rpt->flag_s40); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb {FB,p20,s20,s40}={%d,%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, + rpt->pwdb_s20, rpt->pwdb_s40); + break; + case CHANNEL_WIDTH_40: + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb per20{0,1}={%d,%d}(dBm)\n", + rpt->pwdb_0, rpt->pwdb_1); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "path-%d, flag {FB,p20,s20}={%d,%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20, + rpt->flag_s20); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb {FB,p20,s20}={%d,%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20, + rpt->pwdb_s20); + break; + case CHANNEL_WIDTH_20: + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb per20{0}={%d}(dBm)\n", + rpt->pwdb_0); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "path-%d, flag {FB,p20}={%d,%d}\n", + rpt->path, rpt->flag_fb, rpt->flag_p20); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "pwdb {FB,p20}={%d,%d}(dBm)\n", + rpt->pwdb_fb, rpt->pwdb_p20); + break; + default: + break; + } + + #ifdef BB_8852A_52AA_CUT_SUPPORT + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "FW Adapt-5G_th=-%d, Adapt-2.4G_th=-%d, Carrier-sense_th=-%d\n", + fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4, + fw_edcca_i->pwr_th_cs); + #endif + } + } + *_used = used; + *_out_len = out_len; +} + +void halbb_edcca_dev_hw_cap(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal = bb->hal_com; + + hal->dev_hw_cap.edcca_cap.edcca_adap_th_5g = EDCCA_5G; + hal->dev_hw_cap.edcca_cap.edcca_adap_th_2g = EDCCA_2G; + if (bb->ic_type == BB_RTL8852B) /*[HALBB-126] for SingleTone shift 1MHz*/ + hal->dev_hw_cap.edcca_cap.edcca_carrier_sense_th = CARRIER_SENSE - 6; + else + hal->dev_hw_cap.edcca_cap.edcca_carrier_sense_th = CARRIER_SENSE; +} + +void halbb_edcca_init(struct bb_info *bb) +{ + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i; + struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; + struct rtw_phl_com_t *phl = bb->phl_com; + + if(phl_is_mp_mode(bb->phl_com)) + return; + + bb_edcca->edcca_mode = phl->edcca_mode; + + bb_edcca->th_h = EDCCA_MAX; + bb_edcca->th_l = EDCCA_MAX; + bb_edcca->th_h_lb = 46; + + // EDCCA + bb_edcca->th_h_5g = phl->dev_cap.edcca_cap.edcca_adap_th_5g; + bb_edcca->th_h_2p4g = phl->dev_cap.edcca_cap.edcca_adap_th_2g; + bb_edcca->th_h_cs = phl->dev_cap.edcca_cap.edcca_carrier_sense_th; + + // FW EDCCA + fw_edcca_i->pwr_th_5g = EDCCA_5G_TH; + fw_edcca_i->pwr_th_2p4 = EDCCA_2p4G_TH; + fw_edcca_i->pwr_th_cs = CARRIER_SENSE_TH; +} + + +void halbb_cr_cfg_edcca_init(struct bb_info *bb) +{ + struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i; + + switch (bb->cr_type) { + + #ifdef BB_8852A_52AA_CUT_SUPPORT + case BB_52AA: + cr->r_snd_en = SEG0R_SND_EN_52AA; + cr->r_snd_en_m = SEG0R_SND_EN_52AA_M; + cr->r_dwn_level = SEG0R_DWN_LVL_52AA; + cr->r_dwn_level_m = SEG0R_DWN_LVL_52AA_M; + cr->r_edcca_level = SEG0R_EDCCA_LVL_52AA; + cr->r_edcca_level_m = SEG0R_EDCCA_LVL_52AA_M; + cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_52AA; + cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->r_snd_en = SEG0R_SND_EN_A; + cr->r_snd_en_m = SEG0R_SND_EN_A_M; + cr->r_dwn_level = SEG0R_DWN_LVL_A; + cr->r_dwn_level_m = SEG0R_DWN_LVL_A_M; + cr->r_edcca_level = SEG0R_EDCCA_LVL_A; + cr->r_edcca_level_m = SEG0R_EDCCA_LVL_A_M; + cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_A; + cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_A_M; + cr->r_edcca_rpt_a = EDCCA_IOQ_P0_A_A; + cr->r_edcca_rpt_a_m = EDCCA_IOQ_P0_A_A_M; + cr->r_edcca_rpt_b = EDCCA_IOQ_P0_B_A; + cr->r_edcca_rpt_b_m = EDCCA_IOQ_P0_B_A_M; + cr->r_edcca_rpt_sel = EDCCA_RPTREG_SEL_P0_A; + cr->r_edcca_rpt_sel_m = EDCCA_RPTREG_SEL_P0_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->r_snd_en = SEG0R_SND_EN_C; + cr->r_snd_en_m = SEG0R_SND_EN_C_M; + cr->r_dwn_level = SEG0R_DWN_LVL_C; + cr->r_dwn_level_m = SEG0R_DWN_LVL_C_M; + cr->r_edcca_level = SEG0R_EDCCA_LVL_C; + cr->r_edcca_level_m = SEG0R_EDCCA_LVL_C_M; + cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_C; + cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_C_M; + cr->r_edcca_rpt_a = EDCCA_IOQ_P0_A_C; + cr->r_edcca_rpt_a_m = EDCCA_IOQ_P0_A_C_M; + cr->r_edcca_rpt_b = EDCCA_IOQ_P0_B_C; + cr->r_edcca_rpt_b_m = EDCCA_IOQ_P0_B_C_M; + cr->r_edcca_rpt_sel = EDCCA_RPTREG_SEL_P0_C; + cr->r_edcca_rpt_sel_m = EDCCA_RPTREG_SEL_P0_C_M; + break; + #endif + + default: + break; + } + +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_edcca.h b/phl/hal_g6/phy/bb/halbb_edcca.h new file mode 100644 index 0000000..a31f1ac --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_edcca.h @@ -0,0 +1,134 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_EDCCA_H__ +#define __HALBB_EDCCA_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define EDCCA_HL_DIFF_ADPTVTY 7 +#define EDCCA_HL_DIFF_NORMAL 8 + +// EDCCA +#define EDCCA_5G 63 /*@-62 dBm -3 dB margin*/ +#define EDCCA_2G 68 /*@-57 dBm -3 dB margin*/ +#define CARRIER_SENSE 75 /*@-50dBm -3 dB margin*/ +#define EDCCA_MAX 249 /*@ 127dBm for normal mode*/ +#define EDCCA_PWDB_EXCLU_TX 128 /*128 - 256 = -128dBm when Tx*/ +#define EDCCA_PWDB_TO_RSSI(pwdb) ((pwdb + 110) < 0 ? 0 : (pwdb + 110)) +#define EDCCA_TH_L2H_LB 66 /*@ -62 dBm from IEEE*/ + +// FW EDCCA +#define EDCCA_5G_TH 70 // -62 +#define EDCCA_2p4G_TH 65// -57 +#define CARRIER_SENSE_TH 58 // -50 + +/*@--------------------------[Enum]------------------------------------------*/ +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_h2c_fw_edcca { + u8 mode; + u8 band; + u8 pwr_th_5g; + u8 pwr_th_2p4; + u8 pwr_th_cs; + u8 rsvd0; + u8 rsvd1; + u8 rsvd2; +}; + +struct bb_edcca_cr_info { + u32 r_snd_en; + u32 r_snd_en_m; + u32 r_dwn_level; + u32 r_dwn_level_m; + u32 r_edcca_level; + u32 r_edcca_level_m; + u32 r_edcca_level_p; + u32 r_edcca_level_p_m; + u32 r_edcca_rpt_a; + u32 r_edcca_rpt_a_m; + u32 r_edcca_rpt_b; + u32 r_edcca_rpt_b_m; + u32 r_edcca_rpt_sel; + u32 r_edcca_rpt_sel_m; +}; + +struct edcca_hw_rpt { + s8 pwdb_fb; /*52A/52B is 0 when BW=40, 92XB would fix*/ + s8 pwdb_p20; + s8 pwdb_s20; + s8 pwdb_s40; + s8 pwdb_s80; + bool flag_fb; + bool flag_p20; + bool flag_s20; + bool flag_s40; + bool flag_s80; + s8 pwdb_0; + s8 pwdb_1; + s8 pwdb_2; + s8 pwdb_3; + s8 pwdb_4; + s8 pwdb_5; + s8 pwdb_6; + s8 pwdb_7; + s8 pwdb_8; + u8 path; +}; + +struct bb_edcca_info { + struct bb_edcca_cr_info bb_edcca_cr_i; + u8 th_l; + u8 th_h; + u8 th_hl_diff; + u8 edcca_mode; + u8 th_h_lb; + u8 th_h_5g; + u8 th_h_2p4g; + u8 th_h_cs; + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + struct edcca_hw_rpt edcca_rpt; +}; +#ifdef HALBB_DYN_L2H_SUPPORT +struct bb_dyn_l2h_info { + bool en_dyn_l2h; + u32 low_rate_rty_cnt; + u32 drop_cnt; + u8 l2h_th; +}; +#endif + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_edcca(struct bb_info *bb); +void halbb_edcca_thre_calc(struct bb_info * bb); +void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len); +void halbb_edcca_event_nofity(struct bb_info * bb, u8 pause_type); +void halbb_edcca_dev_hw_cap(struct bb_info * bb); +void halbb_edcca_init(struct bb_info *bb); +void halbb_cr_cfg_edcca_init(struct bb_info *bb); +void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_edcca_ex.h b/phl/hal_g6/phy/bb/halbb_edcca_ex.h new file mode 100644 index 0000000..1a18967 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_edcca_ex.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_EDCCA_EX_H__ +#define __HALBB_EDCCA_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_edcca_mode { + EDCCA_NORMAL_MODE = 0, + EDCCA_ADAPT_MODE = 1, + EDCCA_CARRIER_SENSE_MODE = 2, +}; +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_fw_edcca(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_env_mntr.c b/phl/hal_g6/phy/bb/halbb_env_mntr.c new file mode 100644 index 0000000..e452b7f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_env_mntr.c @@ -0,0 +1,3523 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_ENV_MNTR_SUPPORT + +u16 halbb_ccx_get_ratio(struct bb_info *bb, u16 rpt, u16 score) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u32 numer = 0; + u16 ratio = 0; + u16 ret = 0; + + if (rpt == env->ccx_period) { + ret = score; + } else { + numer = rpt * score + (env->ccx_period >> 1); + ratio = (u16)HALBB_DIV(numer, env->ccx_period); + ret = (ratio == score) ? (score - 1) : ratio; + } + + return ret; +} + +void halbb_ccx_ms_2_period_unit(struct bb_info *bb, u16 time_ms, u32 *period, + u32 *unit_idx) +{ + if (time_ms >= 2097) + time_ms = 2097; + + if (time_ms < 263) + *unit_idx = CCX_04_US; + else if (time_ms < 525) + *unit_idx = CCX_08_US; + else if (time_ms < 1049) + *unit_idx = CCX_16_US; + else + *unit_idx = CCX_32_US; + + *period = (u32)((time_ms * MS_TO_4US_RATIO) >> *unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, "[Trigger Time] period:%d, unit_idx:%d\n", + *period, *unit_idx); +} + +u32 halbb_ccx_idx_cnt_2_us(struct bb_info *bb, u16 idx_cnt) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u32 time_us = 0; + + time_us = (u32)(idx_cnt << (2 + env->ccx_unit_idx)); + + return time_us; +} + +u16 halbb_ccx_us_2_idx_cnt(struct bb_info *bb, u32 time_us) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u16 idx_cnt = 0; + + idx_cnt = (u16)(time_us >> (2 + env->ccx_unit_idx)); + + return idx_cnt; +} + +void halbb_ccx_top_setting_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + env->ccx_manual_ctrl = false; + env->ccx_ongoing = false; + env->ccx_rac_lv = RAC_RELEASE; + env->ccx_rpt_stamp = 0; + env->ccx_period = 0; + env->ccx_unit_idx = CCX_32_US; + env->ccx_trigger_time = 0; + env->ccx_edcca_opt_bw_idx = CCX_EDCCA_BW20_0; + + halbb_set_reg_phy0_1(bb, cr->ccx_en, cr->ccx_en_m, 1); + halbb_set_reg_phy0_1(bb, cr->ccx_trig_opt, cr->ccx_trig_opt_m, 1); + halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); + halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m, + CCX_EDCCA_BW20_0); +} + +void halbb_ccx_racing_release(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + BB_DBG(bb, DBG_ENV_MNTR, "lv:(%d)->(0)\n", env->ccx_rac_lv); + + env->ccx_ongoing = false; + env->ccx_rac_lv = RAC_RELEASE; + env->clm_app = CLM_INIT; + env->nhm_app = NHM_INIT; + env->ifs_clm_app = IFS_CLM_INIT; + env->fahm_app = FAHM_INIT; + env->edcca_clm_app = EDCCA_CLM_INIT; +} + +u8 halbb_ccx_racing_ctrl(struct bb_info *bb, enum halbb_racing_lv rac_lv) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 set_result = HALBB_SET_SUCCESS; + + if (rac_lv >= RAC_MAX_NUM) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n", rac_lv); + return HALBB_SET_FAIL; + } + + BB_DBG(bb, DBG_ENV_MNTR, "ccx_ongoing=%d, lv:(%d)->(%d)\n", + env->ccx_ongoing, env->ccx_rac_lv, rac_lv); + + if (env->ccx_ongoing) { + if (rac_lv <= env->ccx_rac_lv) + set_result = HALBB_SET_FAIL; + else + env->ccx_ongoing = false; + } + + if (set_result) + env->ccx_rac_lv = rac_lv; + + BB_DBG(bb, DBG_ENV_MNTR, "ccx racing success=%d\n", set_result); + return set_result; +} + +void halbb_ccx_trigger(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Due to IFS_CLM clock gating : [HALBB-58]*/ + halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 0); + halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 0); + halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 1); + halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1); + + env->ccx_trigger_time = bb->bb_sys_up_time; + env->ccx_rpt_stamp++; + env->ccx_ongoing = true; +} + +void halbb_ccx_edcca_opt_set(struct bb_info *bb, enum ccx_edcca_opt_sc_idx sc) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u8 pri_ch = 0; + u8 central_ch = 0; + enum channel_width bw = 0; + u8 pri_ch_idx = 0; + u8 bw_idx = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + pri_ch = bb->hal_com->band[0].cur_chandef.chan; + central_ch = bb->hal_com->band[0].cur_chandef.center_ch; + bw = bb->hal_com->band[0].cur_chandef.bw; + + /*==== [search pri_ch idx] ====*/ + if (central_ch <= 14) { + // === 2G === // + switch (bw) { + case CHANNEL_WIDTH_20: + break; + case CHANNEL_WIDTH_40: + pri_ch_idx = pri_ch > central_ch ? 1 : 2; + break; + default: + break; + } + } else { + // === 5G === // + switch (bw) { + case CHANNEL_WIDTH_20: + break; + case CHANNEL_WIDTH_40: + case CHANNEL_WIDTH_80: + if (pri_ch > central_ch) + pri_ch_idx = (pri_ch - central_ch) >> 1; + else + pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1; + break; + default: + break; + } + } + + BB_DBG(bb, DBG_ENV_MNTR, + "sc_idx=%d, pri_ch=%d, cen_ch=%d, bw=%d, pri_ch_idx=%d\n", sc, + pri_ch, central_ch, bw, pri_ch_idx); + + /*sc_idx => 4|2|1|3*/ + /*bw_idx => 0|1|2|3*/ + switch (pri_ch_idx) { + case 4: /*p0|s1|s3|s2*/ + if (sc == CCX_EDCCA_SEG0_P0) + bw_idx = CCX_EDCCA_BW20_0; + else if (sc == CCX_EDCCA_SEG0_S1) + bw_idx = CCX_EDCCA_BW20_1; + else if (sc == CCX_EDCCA_SEG0_S2) + bw_idx = CCX_EDCCA_BW20_3; + else if (sc == CCX_EDCCA_SEG0_S3) + bw_idx = CCX_EDCCA_BW20_2; + break; + case 2: /*s1|p0|s2|s3*/ + if (sc == CCX_EDCCA_SEG0_P0) + bw_idx = CCX_EDCCA_BW20_1; + else if (sc == CCX_EDCCA_SEG0_S1) + bw_idx = CCX_EDCCA_BW20_0; + else if (sc == CCX_EDCCA_SEG0_S2) + bw_idx = CCX_EDCCA_BW20_2; + else if (sc == CCX_EDCCA_SEG0_S3) + bw_idx = CCX_EDCCA_BW20_3; + break; + case 1: /*s3|s2|p0|s1*/ + if (sc == CCX_EDCCA_SEG0_P0) + bw_idx = CCX_EDCCA_BW20_2; + else if (sc == CCX_EDCCA_SEG0_S1) + bw_idx = CCX_EDCCA_BW20_3; + else if (sc == CCX_EDCCA_SEG0_S2) + bw_idx = CCX_EDCCA_BW20_1; + else if (sc == CCX_EDCCA_SEG0_S3) + bw_idx = CCX_EDCCA_BW20_0; + break; + case 3: /*s2|s3|s1|p0*/ + if (sc == CCX_EDCCA_SEG0_P0) + bw_idx = CCX_EDCCA_BW20_3; + else if (sc == CCX_EDCCA_SEG0_S1) + bw_idx = CCX_EDCCA_BW20_2; + else if (sc == CCX_EDCCA_SEG0_S2) + bw_idx = CCX_EDCCA_BW20_0; + else if (sc == CCX_EDCCA_SEG0_S3) + bw_idx = CCX_EDCCA_BW20_1; + break; + default: + bw_idx = CCX_EDCCA_BW20_0; + break; + } + + if (env->ccx_edcca_opt_bw_idx != bw_idx) { + halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m, + bw_idx); + BB_DBG(bb, DBG_ENV_MNTR, + "Update EDCCA_OPT_BW_IDX ((%d)) -> ((%d))\n", + env->ccx_edcca_opt_bw_idx, bw_idx); + env->ccx_edcca_opt_bw_idx = bw_idx; + } +} + +#ifdef NHM_SUPPORT + +void halbb_nhm_cal_wgt(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + + for (i = 0; i < NHM_RPT_NUM; i++) { + if (i == 0) + env->nhm_wgt[i] = (u8)(MAX_2(env->nhm_th[i] - 2, 0)); + else if (i == (NHM_RPT_NUM - 1)) + env->nhm_wgt[i] = (u8)(env->nhm_th[i - 1] + 2); + else + env->nhm_wgt[i] = (u8)((env->nhm_th[i - 1] + + env->nhm_th[i]) >> 1); + } +} + +u8 halbb_nhm_cal_wgt_avg(struct bb_info *bb, u8 start_i, u8 end_i, u16 n_sum) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + u32 tmp = 0; + u8 wgt_avg = 0; + u8 nhm_valid = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (n_sum == 0) { + BB_DBG(bb, DBG_ENV_MNTR, + "result_sum = 0, don't need to update\n"); + return 0; + } else if (end_i > NHM_RPT_NUM - 1) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING]nhm_end_idx is larger than 11!!\n"); + return 0; + } + + for (i = start_i; i <= end_i; i++) + tmp += env->nhm_sw_result[i] * env->nhm_wgt[i]; + + wgt_avg = (u8)(NHM_TH_2_RSSI(HALBB_DIV(tmp, n_sum))); + nhm_valid = (u8)halbb_ccx_get_ratio(bb, n_sum, 100); + BB_DBG(bb, DBG_ENV_MNTR, + "valid: ((%d)) percent, wgt_avg(RSSI)=((%d))\n", + nhm_valid, wgt_avg); + + return wgt_avg; +} + +u16 halbb_nhm_exclu_noise_figure(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct rtw_hw_band *hw_band = &bb->hal_com->band[bb->bb_phy_idx]; + u8 first_idx = 255; + u8 second_idx = 255; + u16 non_noise_f = 0; + u8 i = 0; + + non_noise_f = env->nhm_result_sum; + + /*search first & second cluster*/ + for (i = 0; i < NHM_RPT_NUM; i++) { + if (env->nhm_sw_result[i]) { + if (first_idx == 255) { + first_idx = i; + } else if (second_idx == 255) { + second_idx = i; + break; + } + } + } + + /*exclude first cluster under -80dBm, ranging from i ~ i+2 (9dB)*/ + for (i = 0; i < 3; i++) { + if (((first_idx + i) < NHM_RPT_NUM) && + (env->nhm_wgt[first_idx + i] <= NHM_NOISE_F_TH)) + non_noise_f -= env->nhm_sw_result[first_idx + i]; + } + + /*exclude first_idx and second_idx above -80dBm for 52A 2.4G DIG issue*/ + if ((bb->ic_type == BB_RTL8852A) && + (hw_band->cur_chandef.band == BAND_ON_24G)) { + if ((first_idx != 255) && + (env->nhm_wgt[first_idx] > NHM_NOISE_F_TH)) + non_noise_f -= env->nhm_sw_result[first_idx]; + + if ((second_idx != 255) && + (env->nhm_wgt[second_idx] > NHM_NOISE_F_TH)) + non_noise_f -= env->nhm_sw_result[second_idx]; + } + + BB_DBG(bb, DBG_ENV_MNTR, + "cal non_noise_f: 1st_i=%d, 2nd_i=%d, non_noise_f=%d\n", + first_idx, second_idx, non_noise_f); + + return non_noise_f; +} + +void halbb_nhm_get_utility(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i; + struct edcca_hw_rpt *edcca_r = &bb_edcca->edcca_rpt; + u16 non_noise_f = 0; + u8 i = 0; + + halbb_nhm_cal_wgt(bb); + + for (i = 0; i < NHM_RPT_NUM; i++) { + if (((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) && + (i == (NHM_RPT_NUM - 1))) { + env->nhm_sw_result[0] += env->nhm_result[i]; + env->nhm_sw_result[i] = 0; + } else { + env->nhm_sw_result[i] = env->nhm_result[i]; + } + } + + BB_DBG(bb, DBG_ENV_MNTR, + "NHM sw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + env->ccx_rpt_stamp, env->nhm_sw_result[11], + env->nhm_sw_result[10], env->nhm_sw_result[9], + env->nhm_sw_result[8], env->nhm_sw_result[7], + env->nhm_sw_result[6], env->nhm_sw_result[5], + env->nhm_sw_result[4], env->nhm_sw_result[3], + env->nhm_sw_result[2], env->nhm_sw_result[1], + env->nhm_sw_result[0]); + + /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ + non_noise_f = halbb_nhm_exclu_noise_figure(bb); + env->nhm_ratio = (u8)halbb_ccx_get_ratio(bb, non_noise_f, 100); + env->nhm_tx_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_tx_cnt, 100); + env->nhm_cca_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_cca_cnt, 100); + env->nhm_idle_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_idle_cnt, + 100); + env->nhm_pwr = halbb_nhm_cal_wgt_avg(bb, 0, NHM_RPT_NUM - 1, + env->nhm_result_sum); + + if (bb->ic_type == BB_RTL8852A) { + if ((edcca_r->pwdb_fb != (s8)(EDCCA_PWDB_EXCLU_TX)) && + (EDCCA_PWDB_TO_RSSI(edcca_r->pwdb_fb) <= NHM_WA_PWR)) + env->edcca_noise_bg = EDCCA_PWDB_TO_RSSI(edcca_r->pwdb_fb); + + BB_DBG(bb, DBG_ENV_MNTR, "edcca_noise_bg, nhm_pwr = {%d, %d}\n", + env->edcca_noise_bg, env->nhm_pwr); + + if (env->nhm_pwr <= NHM_WA_PWR) + env->nhm_pwr = env->edcca_noise_bg; + } + + for (i = 0; i < NHM_RPT_NUM; i++) + env->nhm_rpt[i] = (u8)halbb_ccx_get_ratio(bb, + env->nhm_sw_result[i], 100); + + BB_DBG(bb, DBG_ENV_MNTR, "cnt ratio{cca, tx, idle} = {%d, %d, %d}\n", + env->nhm_cca_ratio, env->nhm_tx_ratio, env->nhm_idle_ratio); + + BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio=%d, nhm_pwr(RSSI)=%d\n", + env->nhm_ratio, env->nhm_pwr); +} + +bool halbb_nhm_get_result(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u8 i = 0; + u32 result_sum_tmp = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (!(halbb_get_reg(bb, cr->nhm_rdy, cr->nhm_rdy_m))) { + BB_DBG(bb, DBG_ENV_MNTR, "Get NHM report Fail\n"); + return false; + } + + env->nhm_result[0] = (u16)halbb_get_reg(bb, cr->nhm_cnt0, + cr->nhm_cnt0_m); + env->nhm_result[1] = (u16)halbb_get_reg(bb, cr->nhm_cnt1, + cr->nhm_cnt1_m); + env->nhm_result[2] = (u16)halbb_get_reg(bb, cr->nhm_cnt2, + cr->nhm_cnt2_m); + env->nhm_result[3] = (u16)halbb_get_reg(bb, cr->nhm_cnt3, + cr->nhm_cnt3_m); + env->nhm_result[4] = (u16)halbb_get_reg(bb, cr->nhm_cnt4, + cr->nhm_cnt4_m); + env->nhm_result[5] = (u16)halbb_get_reg(bb, cr->nhm_cnt5, + cr->nhm_cnt5_m); + env->nhm_result[6] = (u16)halbb_get_reg(bb, cr->nhm_cnt6, + cr->nhm_cnt6_m); + env->nhm_result[7] = (u16)halbb_get_reg(bb, cr->nhm_cnt7, + cr->nhm_cnt7_m); + env->nhm_result[8] = (u16)halbb_get_reg(bb, cr->nhm_cnt8, + cr->nhm_cnt8_m); + env->nhm_result[9] = (u16)halbb_get_reg(bb, cr->nhm_cnt9, + cr->nhm_cnt9_m); + env->nhm_result[10] = (u16)halbb_get_reg(bb, cr->nhm_cnt10, + cr->nhm_cnt10_m); + env->nhm_result[11] = (u16)halbb_get_reg(bb, cr->nhm_cnt11, + cr->nhm_cnt11_m); + + for (i = 0; i < NHM_RPT_NUM; i++) + result_sum_tmp += (u32)env->nhm_result[i]; + + env->nhm_result_sum = (u16)result_sum_tmp; + BB_DBG(bb, DBG_ENV_MNTR, "nhm_result_sum=%d\n", env->nhm_result_sum); + + /*Get NHM cnt*/ + env->nhm_cca_cnt = (u16)halbb_get_reg(bb, cr->nhm_cca_cnt, + cr->nhm_cca_cnt_m); + env->nhm_tx_cnt = (u16)halbb_get_reg(bb, cr->nhm_tx_cnt, + cr->nhm_tx_cnt_m); + env->nhm_idle_cnt = (u16)halbb_get_reg(bb, cr->nhm_idle_cnt, + cr->nhm_idle_cnt_m); + + BB_DBG(bb, DBG_ENV_MNTR, "cnt{cca, tx, idle} = {%d, %d, %d}\n", + env->nhm_cca_cnt, env->nhm_tx_cnt, env->nhm_idle_cnt); + + BB_DBG(bb, DBG_ENV_MNTR, + "NHM hw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + env->ccx_rpt_stamp, env->nhm_result[11], env->nhm_result[10], + env->nhm_result[9], env->nhm_result[8], env->nhm_result[7], + env->nhm_result[6], env->nhm_result[5], env->nhm_result[4], + env->nhm_result[3], env->nhm_result[2], env->nhm_result[1], + env->nhm_result[0]); + + halbb_nhm_get_utility(bb); + + return true; +} + +void halbb_nhm_set_th_reg(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Set NHM threshold*/ /*Unit: RSSI U(8,1)*/ + halbb_set_reg_phy0_1(bb, cr->nhm_th0, cr->nhm_th0_m, env->nhm_th[0]); + halbb_set_reg_phy0_1(bb, cr->nhm_th1, cr->nhm_th1_m, env->nhm_th[1]); + halbb_set_reg_phy0_1(bb, cr->nhm_th2, cr->nhm_th2_m, env->nhm_th[2]); + halbb_set_reg_phy0_1(bb, cr->nhm_th3, cr->nhm_th3_m, env->nhm_th[3]); + halbb_set_reg_phy0_1(bb, cr->nhm_th4, cr->nhm_th4_m, env->nhm_th[4]); + halbb_set_reg_phy0_1(bb, cr->nhm_th5, cr->nhm_th5_m, env->nhm_th[5]); + halbb_set_reg_phy0_1(bb, cr->nhm_th6, cr->nhm_th6_m, env->nhm_th[6]); + halbb_set_reg_phy0_1(bb, cr->nhm_th7, cr->nhm_th7_m, env->nhm_th[7]); + halbb_set_reg_phy0_1(bb, cr->nhm_th8, cr->nhm_th8_m, env->nhm_th[8]); + halbb_set_reg_phy0_1(bb, cr->nhm_th9, cr->nhm_th9_m, env->nhm_th[9]); + halbb_set_reg_phy0_1(bb, cr->nhm_th10, cr->nhm_th10_m, env->nhm_th[10]); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + env->nhm_th[10], env->nhm_th[9], env->nhm_th[8], env->nhm_th[7], + env->nhm_th[6], env->nhm_th[5], env->nhm_th[4], env->nhm_th[3], + env->nhm_th[2], env->nhm_th[1], env->nhm_th[0]); +} + +bool +halbb_nhm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para, + u8 *nhm_th) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool is_app_change = (env->nhm_app == para->nhm_app) ? false : true; + bool is_update = is_app_change; + u8 nhm_th_11k[NHM_TH_NUM] = {18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60}; /*Unit RSSI*/ + u8 i = 0; + u8 th_ofst = 3; + u8 th0 = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "nhm_App=%d\n", para->nhm_app); + + if (!is_app_change) + goto CHK_NHM_UPDATE_FINISHED; + + switch (para->nhm_app) { + case NHM_INIT: + case NHM_BACKGROUND: /* IEEE 11K*/ + case NHM_DBG_11K: + case NHM_ACS: + case NHM_DIG: + case NHM_TDMA_DIG: + is_update = true; + for (i = 0; i < NHM_TH_NUM; i++) { + if (((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) && + (i == (NHM_TH_NUM - 1))) + nhm_th[i] = RSSI_2_NHM_TH(NHM_WA_TH); + else + nhm_th[i] = RSSI_2_NHM_TH(nhm_th_11k[i]); + } + break; + case NHM_DBG_RSSI: + if (DIFF_2(bb->bb_ch_i.rssi_min, env->ccx_pre_rssi) < 3) + goto CHK_NHM_UPDATE_FINISHED; + + is_update = true; + env->ccx_pre_rssi = bb->bb_ch_i.rssi_min; + th_ofst = 3; + /*nhm th[0] lower bound is 0*/ + th0 = MAX_2(bb->bb_ch_i.rssi_min - NHM_PWR_OFST, 0); + /*nhm_th[0] upper bound is 127 - 10 * th_ofst*/ + th0 = MIN_2(bb->bb_ch_i.rssi_min - NHM_PWR_OFST, + 127 - th_ofst * (NHM_TH_NUM - 1)); + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i)); + break; + case NHM_DBG_MANUAL: + is_update = true; + th_ofst = para->nhm_manual_th_ofst; + if ((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + /*nhm_th[0] upper bound is 109 - 10 * th_ofst*/ + th0 = MIN_2(para->nhm_manual_th0, + NHM_WA_TH - th_ofst * (NHM_TH_NUM - 1)); + for (i = 0; i < NHM_TH_NUM; i++) { + if (i == (NHM_TH_NUM - 1)) + nhm_th[i] = RSSI_2_NHM_TH(NHM_WA_TH); + else + nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i)); + } + } else { + /*nhm_th[0] upper bound is 127 - 10 * th_ofst*/ + th0 = MIN_2(para->nhm_manual_th0, + 127 - th_ofst * (NHM_TH_NUM - 1)); + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i)); + } + break; + default: + break; + } + +CHK_NHM_UPDATE_FINISHED: + if (!is_update) + BB_DBG(bb, DBG_ENV_MNTR, "No need to update NHM_TH\n"); + + return is_update; +} + +bool halbb_nhm_set(struct bb_info *bb, struct ccx_para_info *para) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_link_info *link = &bb->bb_link_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u32 period = 65535; + u32 unit_idx = 0; + u8 nhm_th[NHM_TH_NUM] = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (para->mntr_time == 0) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n"); + return HALBB_SET_FAIL; + } + + if (para->nhm_app == NHM_DBG_RSSI && !(link->is_linked)) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] is_linked = false when nhm_app = rssi\n"); + return HALBB_SET_FAIL; + } + + if (para->nhm_app == NHM_DBG_MANUAL && para->nhm_manual_th_ofst == 0) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] th_ofst is 0 when nhm_app = manual\n"); + return HALBB_SET_FAIL; + } + + if (para->nhm_app == NHM_DBG_MANUAL && para->nhm_manual_th_ofst > 12) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] th_ofst is larger than 12 when nhm_app = manual\n"); + return HALBB_SET_FAIL; + } + + if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL) + return HALBB_SET_FAIL; + + BB_DBG(bb, DBG_ENV_MNTR, "nhm_incld_cca=%d, mntr_time=%d ms\n", + para->nhm_incld_cca, para->mntr_time); + + /*Set unit & period*/ + if (para->mntr_time != env->nhm_mntr_time) { + halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period, + &unit_idx); + halbb_set_reg_phy0_1(bb, cr->nhm_period, cr->nhm_period_m, + period); + halbb_set_reg_phy0_1(bb, cr->nhm_unit_idx, cr->nhm_unit_idx_m, + unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, "Update NHM time ((%d)) -> ((%d))\n", + env->nhm_mntr_time, para->mntr_time); + + env->nhm_mntr_time = para->mntr_time; + env->ccx_period = (u16)period; + env->ccx_unit_idx = (u8)unit_idx; + } + + /*Set include cca*/ + if (para->nhm_incld_cca != env->nhm_include_cca) { + halbb_set_reg_phy0_1(bb, cr->nhm_inclu_cca, cr->nhm_inclu_cca_m, + para->nhm_incld_cca); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update NHM include cca ((%d)) -> ((%d))\n", + env->nhm_include_cca, para->nhm_incld_cca); + + env->nhm_include_cca = para->nhm_incld_cca; + } + + /*Set NHM threshold*/ + if (halbb_nhm_th_update_chk(bb, para, &nhm_th[0])) { + env->nhm_app = para->nhm_app; + halbb_mem_cpy(bb, &env->nhm_th[0], &nhm_th, NHM_TH_NUM); + + /*Set NHM th*/ + halbb_nhm_set_th_reg(bb); + } + + return HALBB_SET_SUCCESS; +} + +void halbb_nhm_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + struct ccx_para_info para = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + env->nhm_app = NHM_INIT; + env->nhm_include_cca = NHM_CCA_INIT; + env->nhm_mntr_time = 0; + env->nhm_pwr = 0; + + /*if r_nhm_en = 0, nhm report will always be 0.*/ + halbb_set_reg_phy0_1(bb, cr->nhm_en, cr->nhm_en_m, true); + + /*r_nhm_pwdb_method_sel[0]=1 : select max path*/ + /*r_nhm_pwdb_method_sel[1] is dummy*/ + halbb_set_reg_phy0_1(bb, cr->nhm_method_sel, cr->nhm_method_sel_m, 0x1); +} + +void halbb_nhm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para = {0}; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u8 end_i = 0; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if ((_os_strcmp(input[1], "-h") == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "NHM Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Basic-Trigger(11k/1900ms): {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(11k): {2} {0~2097ms} {Include CCA}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(RSSI): {3} {0~2097ms} {Include CCA}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(Manual): {4} {0~2097ms} {Include CCA} {th[0]} {th_ofst:1~12}\n"); + } else if (var[0] == 100) { /*Get NHM results*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "ccx_rpt_stamp=%d, ccx_period=%d\n", + env->ccx_rpt_stamp, env->ccx_period); + + if (halbb_nhm_get_result(bb)) { + if ((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) + end_i = NHM_RPT_NUM - 1; + else + end_i = NHM_RPT_NUM; + for (i = 0; i < end_i; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_sw_result[%d] = %d (%d percent)\n", + i, env->nhm_sw_result[i], + env->nhm_rpt[i]); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_cca_cnt = %d (%d percent)\n", + env->nhm_cca_cnt, env->nhm_cca_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_tx_cnt = %d (%d percent)\n", + env->nhm_tx_cnt, env->nhm_tx_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_idle_cnt = %d (%d percent)\n", + env->nhm_idle_cnt, env->nhm_idle_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_ratio=%d, nhm_pwr(RSSI)=%d\n", + env->nhm_ratio, env->nhm_pwr); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "Get NHM result Fail\n"); + } + + halbb_ccx_racing_release(bb); + env->ccx_manual_ctrl = false; + } else { /*NMH trigger*/ + env->ccx_manual_ctrl = true; + + for (i = 1; i < 9; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if (var[0] == 1) { + para.nhm_app = NHM_DBG_11K; + para.mntr_time = 1900; + para.nhm_incld_cca = NHM_EXCLUDE_CCA; + } else if (var[0] == 2) { + para.nhm_app = NHM_DBG_11K; + para.mntr_time = (u16)var[1]; + para.nhm_incld_cca = (enum nhm_option_cca_all)var[2]; + } else if (var[0] == 3) { + para.nhm_app = NHM_DBG_RSSI; + para.mntr_time = (u16)var[1]; + para.nhm_incld_cca = (enum nhm_option_cca_all)var[2]; + } else { + para.nhm_app = NHM_DBG_MANUAL; + para.mntr_time = (u16)var[1]; + para.nhm_incld_cca = (enum nhm_option_cca_all)var[2]; + para.nhm_manual_th0 = (u8)var[3]; + para.nhm_manual_th_ofst = (u8)var[4]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "manual_th_ofst=%d, manaul_th0=%d\n", + para.nhm_manual_th_ofst, + para.nhm_manual_th0); + } + + para.rac_lv = RAC_LV_4; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, inclu_cca=%d\n", + para.nhm_app, para.rac_lv, para.mntr_time, + para.nhm_incld_cca); + + if (halbb_nhm_set(bb, ¶) == HALBB_SET_SUCCESS) { + halbb_ccx_trigger(bb); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ccx_rpt_stamp=%d\n", + env->ccx_rpt_stamp); + + for (i = 0; i < NHM_TH_NUM; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "NHM_th[%d] RSSI = %d\n", i, + NHM_TH_2_RSSI(env->nhm_th[i])); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "NHM mntr set fail!\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*#ifdef NHM_SUPPORT*/ +#ifdef CLM_SUPPORT + +void halbb_clm_get_utility(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + env->clm_ratio = (u8)halbb_ccx_get_ratio(bb, env->clm_result, 100); +} + +bool +halbb_clm_get_result(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + if (!(halbb_get_reg(bb, cr->clm_rdy, cr->clm_rdy_m))) { + BB_DBG(bb, DBG_ENV_MNTR, "Get CLM report Fail\n"); + return false; + } + + env->clm_result = (u16)halbb_get_reg(bb, cr->clm_cnt, cr->clm_cnt_m); + + BB_DBG(bb, DBG_ENV_MNTR, "CLM result = %d\n", env->clm_result); + + halbb_clm_get_utility(bb); + + return true; +} + +bool halbb_clm_set(struct bb_info *bb, struct ccx_para_info *para) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u32 period = 0; + u32 unit_idx = 0; + + if (para->mntr_time == 0) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n"); + return HALBB_SET_FAIL; + } + + if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL) + return HALBB_SET_FAIL; + + /*Set unit & period*/ + if (para->mntr_time != env->clm_mntr_time) { + halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period, + &unit_idx); + halbb_set_reg_phy0_1(bb, cr->clm_period, cr->clm_period_m, + period); + halbb_set_reg_phy0_1(bb, cr->clm_unit_idx, cr->clm_unit_idx_m, + unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, "Update CLM time ((%d)) -> ((%d))\n", + env->clm_mntr_time, para->mntr_time); + + env->clm_mntr_time = para->mntr_time; + env->ccx_period = (u16)period; + env->ccx_unit_idx = (u8)unit_idx; + } + + /*Set input option*/ + if (para->clm_input_opt != env->clm_input_opt) { + halbb_set_reg_phy0_1(bb, cr->clm_opt, cr->clm_opt_m, + para->clm_input_opt); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update CLM input opt ((%d)) -> ((%d))\n", + env->clm_input_opt, para->clm_input_opt); + + env->clm_input_opt = para->clm_input_opt; + } + + env->clm_app = para->clm_app; + + return HALBB_SET_SUCCESS; +} + +void halbb_clm_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + env->clm_input_opt = CLM_CCA_INIT; + env->clm_app = CLM_INIT; + env->clm_mntr_time = 0; +} + +void halbb_clm_set_dbg_sel(struct bb_info *bb, u8 dbg_sel) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + /*r_clm_from_dbg_sel[5](0xa04[25]) is dummy*/ + halbb_set_reg_phy0_1(bb, cr->clm_dbg_sel, cr->clm_dbg_sel_m, dbg_sel); +} + + +void halbb_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para = {0}; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "CLM Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "CLM Basic-Trigger(1900ms): {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "CLM Adv-Trigger: {2} {0~2097ms} {input:0(p20)/1(s20)/2(s40)/3(s80)/4(dbg)/5(txon_cca)/6(s20_s40_s80)/7(s20_s40_s80_p20)}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "CLM set dbg_sel: {3} {bit:0~31}\n"); + } else if (var[0] == 100) { /*Get CLM results */ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "ccx_rpt_stamp=%d, ccx_period=%d\n", + env->ccx_rpt_stamp, env->ccx_period); + + if (halbb_clm_get_result(bb)) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "clm_result = %d (%d percent)\n", + env->clm_result, env->clm_ratio); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "Get CLM_rpt Fail\n"); + } + + halbb_ccx_racing_release(bb); + env->ccx_manual_ctrl = false; + } else if (var[0] == 3) { /* Set dbg_bit_sel */ + halbb_clm_set_dbg_sel(bb, (u8)var[1]); + } else { /* Set & trigger CLM */ + env->ccx_manual_ctrl = true; + + if (var[0] == 1) { + para.mntr_time = 1900; + para.clm_input_opt = CLM_CCA_P20; + } else if (var[0] == 2) { + para.mntr_time = (u16)var[1]; + para.clm_input_opt = (enum clm_opt_input)var[2]; + } + + para.clm_app = CLM_DBG; + para.rac_lv = RAC_LV_4; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, input_opt=%d\n", + para.clm_app, para.rac_lv, para.mntr_time, + para.clm_input_opt); + + if (halbb_clm_set(bb, ¶) == HALBB_SET_SUCCESS) { + halbb_ccx_trigger(bb); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ccx_rpt_stamp=%d\n", + env->ccx_rpt_stamp); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "CLM mntr set fail!\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*#ifdef CLM_SUPPORT*/ + +#ifdef IFS_CLM_SUPPORT + +void halbb_ifs_clm_get_utility(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + u32 numer = 0; + u16 denom = 0; + + env->ifs_clm_tx_ratio = (u8)halbb_ccx_get_ratio(bb, env->ifs_clm_tx, + 100); + env->ifs_clm_edcca_excl_cca_ratio = (u8)halbb_ccx_get_ratio(bb, + env->ifs_clm_edcca_excl_cca, 100); + env->ifs_clm_cck_fa_ratio = (u8)halbb_ccx_get_ratio(bb, + env->ifs_clm_cckfa, 100); + env->ifs_clm_ofdm_fa_ratio = (u8)halbb_ccx_get_ratio(bb, + env->ifs_clm_ofdmfa, 100); + env->ifs_clm_cck_cca_excl_fa_ratio = (u8)halbb_ccx_get_ratio(bb, + env->ifs_clm_cckcca_excl_fa, 100); + env->ifs_clm_ofdm_cca_excl_fa_ratio = (u8)halbb_ccx_get_ratio(bb, + env->ifs_clm_ofdmcca_excl_fa, + 100); + env->ifs_clm_cck_fa_permil = halbb_ccx_get_ratio(bb, env->ifs_clm_cckfa, + 1000); + env->ifs_clm_ofdm_fa_permil = halbb_ccx_get_ratio(bb, + env->ifs_clm_ofdmfa, 1000); + + for (i = 0; i < IFS_CLM_NUM; i++) { + if ((env->ifs_clm_his[i] > 127) && (bb->ic_type == BB_RTL8852A)) + env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; + else + env->ifs_clm_ifs_avg[i] = halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_avg[i]); + + numer = halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_cca[i]) + + (env->ifs_clm_his[i] >> 1); + denom = env->ifs_clm_his[i]; + env->ifs_clm_cca_avg[i] = HALBB_DIV(numer, denom); + } + + BB_DBG(bb, DBG_ENV_MNTR, + "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", + env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); + BB_DBG(bb, DBG_ENV_MNTR, + "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", + env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); + BB_DBG(bb, DBG_ENV_MNTR, + "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", + env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); + BB_DBG(bb, DBG_ENV_MNTR, + "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", + env->ifs_clm_cck_cca_excl_fa_ratio, + env->ifs_clm_ofdm_cca_excl_fa_ratio); + + BB_DBG(bb, DBG_ENV_MNTR, "Time:[his, ifs_avg(us), cca_avg(us)]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG(bb, DBG_ENV_MNTR, "T%d:[%d, %d, %d]\n", i + 1, + env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], + env->ifs_clm_cca_avg[i]); +} + +bool +halbb_ifs_clm_get_result(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u8 i = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (!(halbb_get_reg(bb, cr->ifs_clm_rdy, cr->ifs_clm_rdy_m))) { + BB_DBG(bb, DBG_ENV_MNTR, "Get IFS_CLM report Fail\n"); + return false; + } + + /*CLM result*/ + env->ifs_clm_tx = (u16)halbb_get_reg(bb, cr->ifs_clm_tx_cnt, + cr->ifs_clm_tx_cnt_m); + env->ifs_clm_edcca_excl_cca = (u16)halbb_get_reg(bb, + cr->ifs_clm_edcca_exclu_cca, + cr->ifs_clm_edcca_exclu_cca_m); + env->ifs_clm_cckcca_excl_fa = (u16)halbb_get_reg(bb, + cr->ifs_clm_cckcca_exclu_fa, + cr->ifs_clm_cckcca_exclu_fa_m); + env->ifs_clm_ofdmcca_excl_fa = (u16)halbb_get_reg(bb, + cr->ifs_clm_ofdmcca_exclu_fa, + cr->ifs_clm_ofdmcca_exclu_fa_m); + env->ifs_clm_cckfa = (u16)halbb_get_reg(bb, cr->ifs_clm_cck_fa, + cr->ifs_clm_cck_fa_m); + env->ifs_clm_ofdmfa = (u16)halbb_get_reg(bb, cr->ifs_clm_ofdm_fa, + cr->ifs_clm_ofdm_fa_m); + + /* IFS result */ + env->ifs_clm_his[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_his, + cr->ifs_clm_t1_his_m); + env->ifs_clm_his[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_his, + cr->ifs_clm_t2_his_m); + env->ifs_clm_his[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_his, + cr->ifs_clm_t3_his_m); + env->ifs_clm_his[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_his, + cr->ifs_clm_t4_his_m); + + env->ifs_clm_avg[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_avg, + cr->ifs_clm_t1_avg_m); + env->ifs_clm_avg[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_avg, + cr->ifs_clm_t2_avg_m); + env->ifs_clm_avg[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_avg, + cr->ifs_clm_t3_avg_m); + env->ifs_clm_avg[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_avg, + cr->ifs_clm_t4_avg_m); + + env->ifs_clm_cca[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_cca, + cr->ifs_clm_t1_cca_m); + env->ifs_clm_cca[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_cca, + cr->ifs_clm_t2_cca_m); + env->ifs_clm_cca[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_cca, + cr->ifs_clm_t3_cca_m); + env->ifs_clm_cca[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_cca, + cr->ifs_clm_t4_cca_m); + env->ifs_clm_total_ifs = (u16)halbb_get_reg(bb, cr->ifs_total_cnt, + cr->ifs_total_cnt_m); + + /*Print Result*/ + BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM total_ifs = %d\n", + env->ifs_clm_total_ifs); + BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM {Tx, EDCCA_exclu_cca} = {%d, %d}\n", + env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); + BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM FA {CCK, OFDM} = {%d, %d}\n", + env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); + BB_DBG(bb, DBG_ENV_MNTR, + "IFS-CLM CCA_exclu_FA {CCK, OFDM} = {%d, %d}\n", + env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); + + BB_DBG(bb, DBG_ENV_MNTR, "Time:[his, avg, cca]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG(bb, DBG_ENV_MNTR, "T%d:[%d, %d, %d]\n", i + 1, + env->ifs_clm_his[i], env->ifs_clm_avg[i], + env->ifs_clm_cca[i]); + + halbb_ifs_clm_get_utility(bb); + + return true; +} + +void halbb_ifs_clm_set_th_reg(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u8 i = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + /*Set IFS for en/th_low/th_high T1~T4*/ + halbb_set_reg_phy0_1(bb, cr->ifs_t1_th_l, cr->ifs_t1_th_l_m, + env->ifs_clm_th_l[0]); + halbb_set_reg_phy0_1(bb, cr->ifs_t2_th_l, cr->ifs_t2_th_l_m, + env->ifs_clm_th_l[1]); + halbb_set_reg_phy0_1(bb, cr->ifs_t3_th_l, cr->ifs_t3_th_l_m, + env->ifs_clm_th_l[2]); + halbb_set_reg_phy0_1(bb, cr->ifs_t4_th_l, cr->ifs_t4_th_l_m, + env->ifs_clm_th_l[3]); + + halbb_set_reg_phy0_1(bb, cr->ifs_t1_th_h, cr->ifs_t1_th_h_m, + env->ifs_clm_th_h[0]); + halbb_set_reg_phy0_1(bb, cr->ifs_t2_th_h, cr->ifs_t2_th_h_m, + env->ifs_clm_th_h[1]); + halbb_set_reg_phy0_1(bb, cr->ifs_t3_th_h, cr->ifs_t3_th_h_m, + env->ifs_clm_th_h[2]); + halbb_set_reg_phy0_1(bb, cr->ifs_t4_th_h, cr->ifs_t4_th_h_m, + env->ifs_clm_th_h[3]); + + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG(bb, DBG_ENV_MNTR, + "Update IFS_T%d_th{low, high} : {%d, %d}\n", + i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); +} + +bool halbb_ifs_clm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para, + u16 *ifs_th_l, u16 *ifs_th_h) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool is_app_change = (env->ifs_clm_app == para->ifs_clm_app) ? false : true; + bool is_update = false; + u8 i = 0; + u32 ifs_th0_us = 0; + u32 ifs_th_times = 0; + u32 ifs_th_h_us[IFS_CLM_NUM] = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "ifs_clm_App=%d\n", para->ifs_clm_app); + + if (!is_app_change) + goto CHK_IFS_UPDATE_FINISHED; + + is_update = true; + + switch (para->ifs_clm_app) { + case IFS_CLM_INIT: + case IFS_CLM_BACKGROUND: + case IFS_CLM_ACS: + case IFS_CLM_DBG: + case IFS_CLM_DIG: + case IFS_CLM_TDMA_DIG: + /*ifs_th_h_us = {4096 , 1024 , 256 , 64}*/ + /*ifs_th_l_us = {1024+unit, 256+unit, 64+unit, 0}*/ + ifs_th0_us = 64; + ifs_th_times = 4; + + break; + case IFS_CLM_DBG_MANUAL: + /*ifs_th_h_us[0] = ifs_th0_us*/ + /*ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times, i = 1 ~ 3*/ + /*ifs_th_l_us[0] = 0*/ + /*ifs_th_l_us[i] = ifs_th_h_us[i - 1] + unit, i = 1 ~ 3*/ + ifs_th0_us = para->ifs_clm_manual_th0; + ifs_th_times = para->ifs_clm_manual_th_times; + + break; + default: + break; + } + + for (i = 0; i < IFS_CLM_NUM; i++) { + ifs_th_l[i] = (i == 0) ? 0 : ifs_th_h[i - 1] + 1; + ifs_th_h_us[i] = (i == 0) ? ifs_th0_us : ifs_th_h_us[i - 1] * + ifs_th_times; + ifs_th_h[i] = halbb_ccx_us_2_idx_cnt(bb, ifs_th_h_us[i]); + } + +CHK_IFS_UPDATE_FINISHED: + if (!is_update) + BB_DBG(bb, DBG_ENV_MNTR, "No need to update IFS_TH\n"); + + return is_update; +} + +bool halbb_ifs_clm_set(struct bb_info *bb, struct ccx_para_info *para) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u32 period = 0; + u32 unit_idx = 0; + u16 ccx_mntr_time = 0; + u16 ifs_th_l[IFS_CLM_NUM] = {0}; + u16 ifs_th_h[IFS_CLM_NUM] = {0}; + u8 i = 0; + + if (para->mntr_time == 0) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n"); + return HALBB_SET_FAIL; + } + + if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL) + return HALBB_SET_FAIL; + + /*Set unit & period*/ + if (para->mntr_time != env->ifs_clm_mntr_time) { + halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period, + &unit_idx); + halbb_set_reg_phy0_1(bb, cr->ifs_clm_period, + cr->ifs_clm_period_m, period); + halbb_set_reg_phy0_1(bb, cr->ifs_clm_unit_idx, + cr->ifs_clm_unit_idx_m, unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update IFS-CLM time ((%d)) -> ((%d))\n", + env->ifs_clm_mntr_time, para->mntr_time); + + env->ifs_clm_mntr_time = para->mntr_time; + env->ccx_period = (u16)period; + env->ccx_unit_idx = (u8)unit_idx; + } + + /*Set IFS CLM threshold*/ + if (halbb_ifs_clm_th_update_chk(bb, para, &ifs_th_l[0], &ifs_th_h[0])) { + env->ifs_clm_app = para->ifs_clm_app; + for (i = 0; i < IFS_CLM_NUM; i++) { + env->ifs_clm_th_l[i] = ifs_th_l[i]; + env->ifs_clm_th_h[i] = ifs_th_h[i]; + } + + halbb_ifs_clm_set_th_reg(bb); + } + + return HALBB_SET_SUCCESS; +} + +void halbb_ifs_clm_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + struct ccx_para_info para = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + env->ifs_clm_app = IFS_CLM_INIT; + env->ifs_clm_mntr_time = 0; + + /*if r_IFS_collect_en = 0, ifs_clm ready bit will always be 0.*/ + halbb_set_reg_phy0_1(bb, cr->ifs_clm_en, cr->ifs_clm_en_m, true); + + /*Enable IFS cnt*/ + halbb_set_reg_phy0_1(bb, cr->ifs_t1_en, cr->ifs_t1_en_m, true); + halbb_set_reg_phy0_1(bb, cr->ifs_t2_en, cr->ifs_t2_en_m, true); + halbb_set_reg_phy0_1(bb, cr->ifs_t3_en, cr->ifs_t3_en_m, true); + halbb_set_reg_phy0_1(bb, cr->ifs_t4_en, cr->ifs_t4_en_m, true); +} + +void halbb_ifs_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para = {0}; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "IFS-CLM Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "IFS-CLM Basic-Trigger 1900ms: {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "IFS-CLM Adv-Trigger: {2} {0~2097ms}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "IFS-CLM Adv-Trigger(manual): {3} {0~2097ms} {ifs_th0(us)} {ifs_th_times}\n"); + } else if (var[0] == 100) { /*Get IFS_CLM results*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "ccx_rpt_stamp=%d, ccx_period=%d\n", + env->ccx_rpt_stamp, env->ccx_period); + + if (halbb_ifs_clm_get_result(bb)) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM Tx cnt = %d (%d percent)\n", + env->ifs_clm_tx, env->ifs_clm_tx_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM EDCCA_excl_cca cnt = %d (%d percent)\n", + env->ifs_clm_edcca_excl_cca, + env->ifs_clm_edcca_excl_cca_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM CCK FA cnt = %d (%d percent/%d permil)\n", + env->ifs_clm_cckfa, + env->ifs_clm_cck_fa_ratio, + env->ifs_clm_cck_fa_permil); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM OFDM FA cnt = %d (%d percent/%d permil)\n", + env->ifs_clm_ofdmfa, + env->ifs_clm_ofdm_fa_ratio, + env->ifs_clm_ofdm_fa_permil); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM CCK CCA_excl_fa cnt = %d (%d percent)\n", + env->ifs_clm_cckcca_excl_fa, + env->ifs_clm_cck_cca_excl_fa_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_CLM OFDM CCA_excl_fa cnt = %d (%d percent)\n", + env->ifs_clm_ofdmcca_excl_fa, + env->ifs_clm_ofdm_cca_excl_fa_ratio); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "IFS_total cnt = %d\n", + env->ifs_clm_total_ifs); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Time(us):[his, ifs_avg(us), cca_avg(us)]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "T%d(%d ~ %d):[%d, %d, %d]\n", + i + 1, halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_l[i]), + halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_h[i]), + env->ifs_clm_his[i], + env->ifs_clm_ifs_avg[i], + env->ifs_clm_cca_avg[i]); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "Get ICS-CLM_rpt Fail\n"); + } + + halbb_ccx_racing_release(bb); + env->ccx_manual_ctrl = false; + } else { /*IFS_CLM trigger*/ + env->ccx_manual_ctrl = true; + + if (var[0] == 1) { + para.ifs_clm_app = IFS_CLM_DBG; + para.mntr_time = 1900; + para.ifs_clm_manual_th0 = 0; + para.ifs_clm_manual_th_times = 0; + } else if (var[0] == 2) { + para.ifs_clm_app = IFS_CLM_DBG; + para.mntr_time = (u16)var[1]; + para.ifs_clm_manual_th0 = 0; + para.ifs_clm_manual_th_times = 0; + } else { + para.ifs_clm_app = IFS_CLM_DBG_MANUAL; + para.mntr_time = (u16)var[1]; + para.ifs_clm_manual_th0 = (u32)var[2]; + para.ifs_clm_manual_th_times = (u32)var[3]; + } + + para.rac_lv = RAC_LV_4; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, manual_th0=%d(us), manual_th_times=%d\n", + para.ifs_clm_app, para.rac_lv, para.mntr_time, + para.ifs_clm_manual_th0, + para.ifs_clm_manual_th_times); + + if (halbb_ifs_clm_set(bb, ¶) == HALBB_SET_SUCCESS) { + halbb_ccx_trigger(bb); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ccx_rpt_stamp=%d\n", + env->ccx_rpt_stamp); + + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "IFS_T%d_th(us){low, high} : {%d, %d}\n", + i + 1,halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_l[i]), + halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_h[i])); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "IFS_CLM mntr set fail!\n"); + } + } + + *_used = used; + *_out_len = out_len; +} +#endif + +#ifdef FAHM_SUPPORT + +void halbb_fahm_cal_wgt(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + + for (i = 0; i < FAHM_RPT_NUM; i++) { + if (i == 0) + env->fahm_wgt[i] = (u8)(MAX_2(env->fahm_th[i] - 2, 0)); + else if (i == (FAHM_RPT_NUM - 1)) + env->fahm_wgt[i] = (u8)(env->fahm_th[i - 1] + 2); + else + env->fahm_wgt[i] = (u8)((env->fahm_th[i - 1] + + env->fahm_th[i]) >> 1); + } +} + +u8 halbb_fahm_cal_wgt_avg(struct bb_info *bb, u8 start_i, u8 end_i, u16 n_sum) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + u32 tmp = 0; + u8 wgt_avg = 0; + u8 fahm_valid = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (n_sum == 0) { + BB_DBG(bb, DBG_ENV_MNTR, + "fahm_rpt_sum = 0, don't need to update noise\n"); + return 0; + } else if (end_i > FAHM_RPT_NUM - 1) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING]fahm_rpt_end_idx is larger than 11!!\n"); + return 0; + } + + for (i = start_i; i <= end_i; i++) + tmp += env->fahm_sw_result[i] * env->fahm_wgt[i]; + + wgt_avg = (u8)(FAHM_TH_2_RSSI(HALBB_DIV(tmp, n_sum))); + fahm_valid = (u8)halbb_ccx_get_ratio(bb, n_sum, 100); + BB_DBG(bb, DBG_ENV_MNTR, + "valid: ((%d)) percent, wgt_avg(RSSI)=((%d))\n", + fahm_valid, wgt_avg); + + return wgt_avg; +} + + +void halbb_fahm_get_utility(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + + halbb_fahm_cal_wgt(bb); + + for (i = 0; i < FAHM_RPT_NUM; i++) { + if (((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) && + (i == (FAHM_RPT_NUM - 1))) { + env->fahm_sw_result[0] += env->fahm_result[i]; + env->fahm_sw_result[i] = 0; + } else { + env->fahm_sw_result[i] = env->fahm_result[i]; + } + } + + BB_DBG(bb, DBG_ENV_MNTR, + "FAHM sw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + env->ccx_rpt_stamp, env->fahm_sw_result[11], + env->fahm_sw_result[10], env->fahm_sw_result[9], + env->fahm_sw_result[8], env->fahm_sw_result[7], + env->fahm_sw_result[6], env->fahm_sw_result[5], + env->fahm_sw_result[4], env->fahm_sw_result[3], + env->fahm_sw_result[2], env->fahm_sw_result[1], + env->fahm_sw_result[0]); + + env->fahm_ratio = (u8)halbb_ccx_get_ratio(bb, env->fahm_result_sum, + 100); + env->fahm_denom_ratio = (u8)halbb_ccx_get_ratio(bb, + env->fahm_denom_result, 100); + env->fahm_pwr = halbb_fahm_cal_wgt_avg(bb, 0, FAHM_RPT_NUM - 1, + env->fahm_result_sum); + + for (i = 0; i < FAHM_RPT_NUM; i++) + env->fahm_rpt[i] = (u8)halbb_ccx_get_ratio(bb, + env->fahm_sw_result[i], 100); + + BB_DBG(bb, DBG_ENV_MNTR, "fahm_ratio=%d, fahm_pwr(RSSI)=%d\n", + env->fahm_ratio, env->fahm_pwr); +} + +bool halbb_fahm_get_result(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u8 i = 0; + u32 result_sum_tmp = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (!(halbb_get_reg(bb, cr->fahm_rdy, cr->fahm_rdy_m))) { + BB_DBG(bb, DBG_ENV_MNTR, "Get FAHM report Fail\n"); + return false; + } + + env->fahm_result[0] = (u16)halbb_get_reg(bb, cr->fahm_cnt0, + cr->fahm_cnt0_m); + env->fahm_result[1] = (u16)halbb_get_reg(bb, cr->fahm_cnt1, + cr->fahm_cnt1_m); + env->fahm_result[2] = (u16)halbb_get_reg(bb, cr->fahm_cnt2, + cr->fahm_cnt2_m); + env->fahm_result[3] = (u16)halbb_get_reg(bb, cr->fahm_cnt3, + cr->fahm_cnt3_m); + env->fahm_result[4] = (u16)halbb_get_reg(bb, cr->fahm_cnt4, + cr->fahm_cnt4_m); + env->fahm_result[5] = (u16)halbb_get_reg(bb, cr->fahm_cnt5, + cr->fahm_cnt5_m); + env->fahm_result[6] = (u16)halbb_get_reg(bb, cr->fahm_cnt6, + cr->fahm_cnt6_m); + env->fahm_result[7] = (u16)halbb_get_reg(bb, cr->fahm_cnt7, + cr->fahm_cnt7_m); + env->fahm_result[8] = (u16)halbb_get_reg(bb, cr->fahm_cnt8, + cr->fahm_cnt8_m); + env->fahm_result[9] = (u16)halbb_get_reg(bb, cr->fahm_cnt9, + cr->fahm_cnt9_m); + env->fahm_result[10] = (u16)halbb_get_reg(bb, cr->fahm_cnt10, + cr->fahm_cnt10_m); + env->fahm_result[11] = (u16)halbb_get_reg(bb, cr->fahm_cnt11, + cr->fahm_cnt11_m); + + for (i = 0; i < FAHM_RPT_NUM; i++) + result_sum_tmp += (u32)env->fahm_result[i]; + + env->fahm_result_sum = (u16)result_sum_tmp; + BB_DBG(bb, DBG_ENV_MNTR, "fahm_result_sum=%d\n", env->fahm_result_sum); + + /*Get FAHM denominator*/ + env->fahm_denom_result = (u16)halbb_get_reg(bb, cr->fahm_denom_cnt, + cr->fahm_denom_cnt_m); + BB_DBG(bb, DBG_ENV_MNTR, "fahm_denominator result = %d\n", + env->fahm_denom_result); + + BB_DBG(bb, DBG_ENV_MNTR, + "FAHM hw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + env->ccx_rpt_stamp, env->fahm_result[11], env->fahm_result[10], + env->fahm_result[9], env->fahm_result[8], env->fahm_result[7], + env->fahm_result[6], env->fahm_result[5], env->fahm_result[4], + env->fahm_result[3], env->fahm_result[2], env->fahm_result[1], + env->fahm_result[0]); + + halbb_fahm_get_utility(bb); + + return true; +} + +void halbb_fahm_set_th_reg(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Set FAHM threshold*/ /*Unit: RSSI U(8,1)*/ + halbb_set_reg_phy0_1(bb, cr->fahm_th0, cr->fahm_th0_m, env->fahm_th[0]); + halbb_set_reg_phy0_1(bb, cr->fahm_th1, cr->fahm_th1_m, env->fahm_th[1]); + halbb_set_reg_phy0_1(bb, cr->fahm_th2, cr->fahm_th2_m, env->fahm_th[2]); + halbb_set_reg_phy0_1(bb, cr->fahm_th3, cr->fahm_th3_m, env->fahm_th[3]); + halbb_set_reg_phy0_1(bb, cr->fahm_th4, cr->fahm_th4_m, env->fahm_th[4]); + halbb_set_reg_phy0_1(bb, cr->fahm_th5, cr->fahm_th5_m, env->fahm_th[5]); + halbb_set_reg_phy0_1(bb, cr->fahm_th6, cr->fahm_th6_m, env->fahm_th[6]); + halbb_set_reg_phy0_1(bb, cr->fahm_th7, cr->fahm_th7_m, env->fahm_th[7]); + halbb_set_reg_phy0_1(bb, cr->fahm_th8, cr->fahm_th8_m, env->fahm_th[8]); + halbb_set_reg_phy0_1(bb, cr->fahm_th9, cr->fahm_th9_m, env->fahm_th[9]); + halbb_set_reg_phy0_1(bb, cr->fahm_th10, cr->fahm_th10_m, + env->fahm_th[10]); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update FAHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + env->fahm_th[10], env->fahm_th[9], env->fahm_th[8], + env->fahm_th[7], env->fahm_th[6], env->fahm_th[5], + env->fahm_th[4], env->fahm_th[3], env->fahm_th[2], + env->fahm_th[1], env->fahm_th[0]); +} + +bool +halbb_fahm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para, + u8 *fahm_th) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool is_app_change = (env->fahm_app == para->fahm_app) ? false : true; + bool is_update = is_app_change; + u8 fahm_th_11k[FAHM_TH_NUM] = {18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60}; /*Unit RSSI*/ + u8 i = 0; + u8 th_ofst = 3; + u8 th0 = 0; + + BB_DBG(bb, DBG_ENV_MNTR, "fahm_App=%d\n", para->fahm_app); + + if (!is_app_change) + goto CHK_FAHM_UPDATE_FINISHED; + + switch (para->fahm_app) { + case FAHM_INIT: + case FAHM_BACKGROUND: /* IEEE 11K*/ + case FAHM_DBG_11K: + case FAHM_ACS: + case FAHM_DIG: + case FAHM_TDMA_DIG: + is_update = true; + for (i = 0; i < FAHM_TH_NUM; i++) { + if (((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) && + (i == (FAHM_TH_NUM - 1))) + fahm_th[i] = RSSI_2_FAHM_TH(FAHM_WA_TH); + else + fahm_th[i] = RSSI_2_FAHM_TH(fahm_th_11k[i]); + } + break; + case FAHM_DBG_RSSI: + if (DIFF_2(bb->bb_ch_i.rssi_min, env->ccx_pre_rssi) < 3) + goto CHK_FAHM_UPDATE_FINISHED; + + is_update = true; + env->ccx_pre_rssi = bb->bb_ch_i.rssi_min; + th_ofst = 3; + /*fahm th[0] lower bound is 0*/ + th0 = MAX_2(bb->bb_ch_i.rssi_min - FAHM_PWR_OFST, 0); + /*fahm_th[0] upper bound is 127 - 10 * th_ofst*/ + th0 = MIN_2(bb->bb_ch_i.rssi_min - FAHM_PWR_OFST, + 127 - th_ofst * (FAHM_TH_NUM - 1)); + for (i = 0; i < FAHM_TH_NUM; i++) + fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i)); + break; + case FAHM_DBG_MANUAL: + is_update = true; + th_ofst = para->fahm_manual_th_ofst; + if ((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + /*fahm_th[0] upper bound is 109 - 10 * th_ofst*/ + th0 = MIN_2(para->fahm_manual_th0, + FAHM_WA_TH - th_ofst * (FAHM_TH_NUM - 1)); + for (i = 0; i < FAHM_TH_NUM; i++) { + if (i == (FAHM_TH_NUM - 1)) + fahm_th[i] = RSSI_2_FAHM_TH(FAHM_WA_TH); + else + fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i)); + } + } else { + /*fahm_th[0] upper bound is 127 - 10 * th_ofst*/ + th0 = MIN_2(para->fahm_manual_th0, + 127 - th_ofst * (FAHM_TH_NUM - 1)); + for (i = 0; i < FAHM_TH_NUM; i++) + fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i)); + } + break; + default: + break; + } + +CHK_FAHM_UPDATE_FINISHED: + if (!is_update) + BB_DBG(bb, DBG_ENV_MNTR, "No need to update FAHM_TH\n"); + + return is_update; +} + +bool halbb_fahm_set(struct bb_info *bb, struct ccx_para_info *para) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_link_info *link = &bb->bb_link_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u32 period = 65535; + u32 unit_idx = 0; + u8 fahm_th[FAHM_TH_NUM] = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (para->mntr_time == 0) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n"); + return HALBB_SET_FAIL; + } + + if (para->fahm_app == FAHM_DBG_RSSI && !(link->is_linked)) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] is_linked = false when fahm_app = rssi\n"); + return HALBB_SET_FAIL; + } + + if (para->fahm_app == FAHM_DBG_MANUAL && + para->fahm_manual_th_ofst == 0) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] th_ofst is 0 when fahm_app = manual\n"); + return HALBB_SET_FAIL; + } + + if (para->fahm_app == FAHM_DBG_MANUAL && + para->fahm_manual_th_ofst > 12) { + BB_DBG(bb, DBG_ENV_MNTR, + "[WARNING] th_ofst is larger than 12 when fahm_app = manual\n"); + return HALBB_SET_FAIL; + } + + if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL) + return HALBB_SET_FAIL; + + BB_DBG(bb, DBG_ENV_MNTR, "mntr_time=%d ms\n", para->mntr_time); + + /*Set unit & period*/ + if (para->mntr_time != env->fahm_mntr_time) { + halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period, + &unit_idx); + halbb_set_reg_phy0_1(bb, cr->fahm_period, cr->fahm_period_m, + period); + halbb_set_reg_phy0_1(bb, cr->fahm_unit_idx, cr->fahm_unit_idx_m, + unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, "Update FAHM time ((%d)) -> ((%d))\n", + env->fahm_mntr_time, para->mntr_time); + + env->fahm_mntr_time = para->mntr_time; + env->ccx_period = (u16)period; + env->ccx_unit_idx = (u8)unit_idx; + } + + /*Set numerator_opt*/ + if (para->fahm_numer_opt != env->fahm_numer_opt) { + halbb_set_reg_phy0_1(bb, cr->fahm_numer_opt, + cr->fahm_numer_opt_m, + para->fahm_numer_opt); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update FAHM numer_opt ((%d)) -> ((%d))\n", + env->fahm_numer_opt, para->fahm_numer_opt); + + env->fahm_numer_opt = para->fahm_numer_opt; + } + + /*Set denominator_opt*/ + if (para->fahm_denom_opt != env->fahm_denom_opt) { + halbb_set_reg_phy0_1(bb, cr->fahm_denom_opt, + cr->fahm_denom_opt_m, + para->fahm_denom_opt); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update FAHM denom_opt ((%d)) -> ((%d))\n", + env->fahm_denom_opt, para->fahm_denom_opt); + + env->fahm_denom_opt = para->fahm_denom_opt; + } + + /*Set FAHM threshold*/ + if (halbb_fahm_th_update_chk(bb, para, &fahm_th[0])) { + env->fahm_app = para->fahm_app; + halbb_mem_cpy(bb, &env->fahm_th[0], &fahm_th, FAHM_TH_NUM); + + /*Set FAHM th*/ + halbb_fahm_set_th_reg(bb); + } + + return HALBB_SET_SUCCESS; +} + +void halbb_fahm_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + struct ccx_para_info para = {0}; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + env->fahm_app = FAHM_INIT; + env->fahm_numer_opt = 0; + env->fahm_denom_opt = 0; + env->fahm_mntr_time = 0; + + /*r_fahm_en_ofdm = r_fahm_en_cck = 1, or fahm report will be 0.*/ + halbb_set_reg_phy0_1(bb, cr->fahm_ofdm_en, cr->fahm_ofdm_en_m, true); + halbb_set_reg_phy0_1(bb, cr->fahm_cck_en, cr->fahm_cck_en_m, true); + + /*r_fahm_pwdb_sel = 1:select max path*/ + halbb_set_reg_phy0_1(bb, cr->fahm_method_sel, cr->fahm_method_sel_m, + 0x1); + + /*r_fahm_dis_count_each_mpdu = 1, or fa report will abnormal*/ + halbb_set_reg_phy0_1(bb, cr->fahm_dis_count_each_mpdu, + cr->fahm_dis_count_each_mpdu_m, true); +} + +void halbb_fahm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u8 end_i = 0; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if ((_os_strcmp(input[1], "-h") == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "FAHM Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Basic-Trigger(11k/1900ms): {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(11k): {2} {0~2097ms} {numer_opt} {denom_opt}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(RSSI): {3} {0~2097ms} {numer_opt} {denom_opt}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger(Manual): {4} {0~2097ms} {numer_opt} {denom_opt} {th[0]} {th_ofst:1~12}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "numer_opt/denom_opt: {BIT 0/1/2} = {FA/CRC32_OK/CRC32_ERR}\n"); + } else if (var[0] == 100) { /*Get FAHM results*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "ccx_rpt_stamp=%d, ccx_period=%d\n", + env->ccx_rpt_stamp, env->ccx_period); + + if (halbb_fahm_get_result(bb)) { + if ((bb->ic_type == BB_RTL8852A) || + (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) + end_i = FAHM_RPT_NUM - 1; + else + end_i = FAHM_RPT_NUM; + for (i = 0; i < end_i; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "fahm_sw_result[%d] = %d (%d percent)\n", + i, env->fahm_sw_result[i], + env->fahm_rpt[i]); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "fahm_ratio=%d, fahm_pwr(RSSI)=%d\n", + env->fahm_ratio, env->fahm_pwr); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "fahm_denominator result = %d (%d percent)\n", + env->fahm_denom_result, + env->fahm_denom_ratio); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "Get FAHM_rpt Fail\n"); + } + + halbb_ccx_racing_release(bb); + env->ccx_manual_ctrl = false; + } else { /*FAMH trigger*/ + env->ccx_manual_ctrl = true; + + for (i = 1; i < 9; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if (var[0] == 1) { + para.fahm_app = FAHM_DBG_11K; + para.mntr_time = 1900; + para.fahm_numer_opt = FAHM_INCLU_FA; + para.fahm_denom_opt = FAHM_INCLU_CRC_ERR; + } else if (var[0] == 2) { + para.fahm_app = FAHM_DBG_11K; + para.mntr_time = (u16)var[1]; + para.fahm_numer_opt = (u8)var[2]; + para.fahm_denom_opt = (u8)var[3]; + } else if (var[0] == 3) { + para.fahm_app = FAHM_DBG_RSSI; + para.mntr_time = (u16)var[1]; + para.fahm_numer_opt = (u8)var[2]; + para.fahm_denom_opt = (u8)var[3]; + } else { + para.fahm_app = FAHM_DBG_MANUAL; + para.mntr_time = (u16)var[1]; + para.fahm_numer_opt = (u8)var[2]; + para.fahm_denom_opt = (u8)var[3]; + para.fahm_manual_th0 = (u8)var[4]; + para.fahm_manual_th_ofst = (u8)var[5]; + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "manual_th_ofst=%d, manaul_th_0=%d\n", + para.fahm_manual_th_ofst, + para.fahm_manual_th0); + } + + para.rac_lv = RAC_LV_4; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, numer_opt=%d, denom_opt=%d\n", + para.fahm_app, para.rac_lv, para.mntr_time, + para.fahm_numer_opt, para.fahm_denom_opt); + + if (halbb_fahm_set(bb, ¶) == HALBB_SET_SUCCESS) { + halbb_ccx_trigger(bb); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ccx_rpt_stamp=%d\n", + env->ccx_rpt_stamp); + + for (i = 0; i < FAHM_TH_NUM; i++) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "FAHM_th[%d] RSSI = %d\n", i, + FAHM_TH_2_RSSI(env->fahm_th[i])); + } + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "FAHM mntr set fail!\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif +#ifdef EDCCA_CLM_SUPPORT + +void halbb_edcca_clm_get_utility(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + env->edcca_clm_ratio = (u8)halbb_ccx_get_ratio(bb, + env->edcca_clm_result, 100); +} + +bool +halbb_edcca_clm_get_result(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + if (!(halbb_get_reg(bb, cr->edcca_clm_rdy, cr->edcca_clm_rdy_m))) { + BB_DBG(bb, DBG_ENV_MNTR, "Get EDCCA_CLM report Fail\n"); + return false; + } + + env->edcca_clm_result = (u16)halbb_get_reg(bb, cr->edcca_clm_cnt, + cr->edcca_clm_cnt_m); + + BB_DBG(bb, DBG_ENV_MNTR, "EDCCA_CLM result = %d\n", + env->edcca_clm_result); + + halbb_edcca_clm_get_utility(bb); + + return true; +} + +bool halbb_edcca_clm_set(struct bb_info *bb, struct ccx_para_info *para) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + u32 period = 0; + u32 unit_idx = 0; + + if (para->mntr_time == 0) { + BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n"); + return HALBB_SET_FAIL; + } + + if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL) + return HALBB_SET_FAIL; + + /*Set unit & period*/ + if (para->mntr_time != env->edcca_clm_mntr_time) { + halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period, + &unit_idx); + halbb_set_reg_phy0_1(bb, cr->edcca_clm_period, + cr->edcca_clm_period_m, period); + halbb_set_reg_phy0_1(bb, cr->edcca_clm_unit_idx, + cr->edcca_clm_unit_idx_m, unit_idx); + + BB_DBG(bb, DBG_ENV_MNTR, + "Update EDCCA-CLM time ((%d)) -> ((%d))\n", + env->edcca_clm_mntr_time, para->mntr_time); + + env->edcca_clm_mntr_time = para->mntr_time; + env->ccx_period = (u16)period; + env->ccx_unit_idx = (u8)unit_idx; + } + + halbb_ccx_edcca_opt_set(bb, para->ccx_edcca_opt_sc_idx); + + env->edcca_clm_app = para->edcca_clm_app; + + return HALBB_SET_SUCCESS; +} + +void halbb_edcca_clm_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + env->edcca_clm_app = EDCCA_CLM_INIT; + env->edcca_clm_mntr_time = 0; +} + +void halbb_edcca_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct ccx_para_info para = {0}; + u8 i = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EDCCA-CLM Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EDCCA-CLM Basic-Trigger(1900ms): {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EDCCA-CLM Adv-Trigger: {2} {0~2097ms} {edcca_opt:0(seg0_p0), 1~7(others)}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "edcca_opt: 0~3:seg0(p0/s1/s2/s3), 4~7:seg1(p0/s1/s2/s3)\n"); + } else if (var[0] == 100) { /*Get EDCCA-CLM results */ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "ccx_rpt_stamp=%d, ccx_period=%d\n", + env->ccx_rpt_stamp, env->ccx_period); + + if (halbb_edcca_clm_get_result(bb)) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "edcca_clm_result = %d (%d percent)\n", + env->edcca_clm_result, + env->edcca_clm_ratio); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "Get EDCCA_CLM_rpt Fail\n"); + } + + halbb_ccx_racing_release(bb); + env->ccx_manual_ctrl = false; + } else { /* Set & trigger CLM */ + env->ccx_manual_ctrl = true; + + if (var[0] == 1) { + para.mntr_time = 1900; + para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0; + } else if (var[0] == 2) { + para.mntr_time = (u16)var[1]; + para.ccx_edcca_opt_sc_idx = (enum ccx_edcca_opt_sc_idx)var[2]; + } + + para.edcca_clm_app = EDCCA_CLM_DBG; + para.rac_lv = RAC_LV_4; + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, edcca_opt=%d\n", + para.edcca_clm_app, para.rac_lv, para.mntr_time, + para.ccx_edcca_opt_sc_idx); + + if (halbb_edcca_clm_set(bb, ¶) == HALBB_SET_SUCCESS) { + halbb_ccx_trigger(bb); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "ccx_rpt_stamp=%d\n", + env->ccx_rpt_stamp); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "EDCCA_CLM mntr set fail!\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif + +bool +halbb_env_mntr_init_app_chk(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool chk_result = HALBB_SET_FAIL; + + if ((env->clm_app == CLM_INIT) && (env->nhm_app == NHM_INIT) && + (env->fahm_app == FAHM_INIT) && + (env->ifs_clm_app == IFS_CLM_INIT) && + (env->edcca_clm_app == EDCCA_CLM_INIT)) + chk_result = HALBB_SET_SUCCESS; + + return chk_result; +} + +bool +halbb_env_mntr_dig_app_chk(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool is_dig = false; + bool is_tdma_dig = false; + bool chk_result = HALBB_SET_FAIL; + + if ((env->clm_app == CLM_DIG) && (env->nhm_app == NHM_DIG) && + (env->fahm_app == FAHM_DIG) && (env->ifs_clm_app == IFS_CLM_DIG) && + (env->edcca_clm_app == EDCCA_CLM_DIG)) + is_dig = true; + + if ((env->clm_app == CLM_TDMA_DIG) && (env->nhm_app == NHM_TDMA_DIG) && + (env->fahm_app == FAHM_TDMA_DIG) && + (env->ifs_clm_app == IFS_CLM_TDMA_DIG) && + (env->edcca_clm_app == EDCCA_CLM_TDMA_DIG)) + is_tdma_dig = true; + + if (is_dig || is_tdma_dig) + chk_result = HALBB_SET_SUCCESS; + + return chk_result; +} + +bool +halbb_env_mntr_bg_app_chk(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + bool chk_result = HALBB_SET_FAIL; + + if ((env->clm_app == CLM_BACKGROUND) && + (env->nhm_app == NHM_BACKGROUND) && + (env->fahm_app == FAHM_BACKGROUND) && + (env->ifs_clm_app == IFS_CLM_BACKGROUND) && + (env->edcca_clm_app == EDCCA_CLM_BACKGROUND)) + chk_result = HALBB_SET_SUCCESS; + + return chk_result; +} + +void halbb_env_mntr_cmn_log(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + + if ((env->ccx_watchdog_result == CCX_FAIL) && + (!halbb_env_mntr_dig_app_chk(bb))) { + BB_DBG(bb, DBG_CMN, + "Env_mntr get CCX result failed and app is not DIG!\n"); + return; + } + + BB_DBG(bb, DBG_CMN, + "{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n", + env->nhm_tx_ratio, env->nhm_idle_ratio, env->nhm_cca_ratio, + env->clm_ratio, env->edcca_clm_ratio); + BB_DBG(bb, DBG_CMN, "{FA, CRC_err} = {%d, %d} %%\n", env->fahm_ratio, + env->fahm_denom_ratio); + BB_DBG(bb, DBG_CMN, "FA{CCK, OFDM} = {%d, %d} %%\n",env->ifs_clm_cck_fa_ratio, + env->ifs_clm_ofdm_fa_ratio); + BB_DBG(bb, DBG_CMN, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n", + env->ifs_clm_cck_cca_excl_fa_ratio, + env->ifs_clm_ofdm_cca_excl_fa_ratio); + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + BB_DBG(bb, DBG_CMN, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_CMN, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->nhm_pwr, env->nhm_rpt[10],env->nhm_rpt[9], + env->nhm_rpt[8], env->nhm_rpt[7],env->nhm_rpt[6], + env->nhm_rpt[5], env->nhm_rpt[4], env->nhm_rpt[3], + env->nhm_rpt[2], env->nhm_rpt[1], env->nhm_rpt[0]); + BB_DBG(bb, DBG_CMN, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->fahm_pwr, env->fahm_rpt[10], env->fahm_rpt[9], + env->fahm_rpt[8], env->fahm_rpt[7], env->fahm_rpt[6], + env->fahm_rpt[5], env->fahm_rpt[4], env->fahm_rpt[3], + env->fahm_rpt[2], env->fahm_rpt[1], env->fahm_rpt[0]); + } else { + BB_DBG(bb, DBG_CMN, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[10]), + NHM_TH_2_RSSI(env->nhm_th[9]), NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_CMN, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->nhm_pwr, env->nhm_rpt[11], env->nhm_rpt[10], + env->nhm_rpt[9], env->nhm_rpt[8], env->nhm_rpt[7], + env->nhm_rpt[6], env->nhm_rpt[5], env->nhm_rpt[4], + env->nhm_rpt[3], env->nhm_rpt[2], env->nhm_rpt[1], + env->nhm_rpt[0]); + BB_DBG(bb, DBG_CMN, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->fahm_pwr, env->fahm_rpt[11], env->fahm_rpt[10], + env->fahm_rpt[9], env->fahm_rpt[8], env->fahm_rpt[7], + env->fahm_rpt[6], env->fahm_rpt[5], env->fahm_rpt[4], + env->fahm_rpt[3], env->fahm_rpt[2], env->fahm_rpt[1], + env->fahm_rpt[0]); + } + BB_DBG(bb, DBG_CMN, "nhm_ratio = %d %%\n", env->nhm_ratio); +} + +void halbb_env_mntr_log(struct bb_info *bb, u32 dbg_comp) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 i = 0; + + if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) + return; + + if (dbg_comp == DBG_CMN) { + halbb_env_mntr_cmn_log(bb); + return; + } + + if ((env->ccx_watchdog_result == CCX_FAIL) && + (!halbb_env_mntr_dig_app_chk(bb))) { + BB_DBG(bb, DBG_ENV_MNTR, + "Env_mntr get CCX result failed and app is not DIG!\n"); + return; + } + + BB_DBG(bb, DBG_ENV_MNTR, + "{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n", + env->nhm_tx_ratio, env->nhm_idle_ratio, env->nhm_cca_ratio, + env->clm_ratio, env->edcca_clm_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "{FA, CRC_err} = {%d, %d} %%\n", env->fahm_ratio, + env->fahm_denom_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "FA{CCK, OFDM} = {%d, %d} %%\n", + env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n", + env->ifs_clm_cck_cca_excl_fa_ratio, + env->ifs_clm_ofdm_cca_excl_fa_ratio); + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + BB_DBG(bb, DBG_ENV_MNTR, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_ENV_MNTR, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->nhm_pwr, env->nhm_rpt[10],env->nhm_rpt[9], + env->nhm_rpt[8], env->nhm_rpt[7],env->nhm_rpt[6], + env->nhm_rpt[5], env->nhm_rpt[4], env->nhm_rpt[3], + env->nhm_rpt[2], env->nhm_rpt[1], env->nhm_rpt[0]); + BB_DBG(bb, DBG_ENV_MNTR, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->fahm_pwr, env->fahm_rpt[10], env->fahm_rpt[9], + env->fahm_rpt[8], env->fahm_rpt[7], env->fahm_rpt[6], + env->fahm_rpt[5], env->fahm_rpt[4], env->fahm_rpt[3], + env->fahm_rpt[2], env->fahm_rpt[1], env->fahm_rpt[0]); + } else { + BB_DBG(bb, DBG_ENV_MNTR, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[10]), + NHM_TH_2_RSSI(env->nhm_th[9]), NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_ENV_MNTR, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->nhm_pwr, env->nhm_rpt[11], env->nhm_rpt[10], + env->nhm_rpt[9], env->nhm_rpt[8], env->nhm_rpt[7], + env->nhm_rpt[6], env->nhm_rpt[5], env->nhm_rpt[4], + env->nhm_rpt[3], env->nhm_rpt[2], env->nhm_rpt[1], + env->nhm_rpt[0]); + BB_DBG(bb, DBG_ENV_MNTR, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + env->fahm_pwr, env->fahm_rpt[11], env->fahm_rpt[10], + env->fahm_rpt[9], env->fahm_rpt[8], env->fahm_rpt[7], + env->fahm_rpt[6], env->fahm_rpt[5], env->fahm_rpt[4], + env->fahm_rpt[3], env->fahm_rpt[2], env->fahm_rpt[1], + env->fahm_rpt[0]); + } + BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio = %d %%\n", env->nhm_ratio); + BB_DBG(bb, DBG_ENV_MNTR, + "[IFS] Time(us):[his, ifs_avg(us), cca_avg(us)], total cnt=%d\n", + env->ifs_clm_total_ifs); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG(bb, DBG_ENV_MNTR, + " *[%d](%04d~%04d):[%03d, %04d, %04d]\n", + i + 1, halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_l[i]), + halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_h[i]), + env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], + env->ifs_clm_cca_avg[i]); +} + +void halbb_env_mntr_get_bg_result(struct bb_info *bb, + struct env_mntr_rpt *bg_rpt, + enum phl_phy_idx phy_idx) +{ + struct bb_env_mntr_info *env = NULL; + +#ifdef HALBB_DBCC_SUPPORT + bb = halbb_get_curr_bb_pointer(bb, phy_idx); + BB_DBG(bb, DBG_ENV_MNTR, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); +#endif + env = &bb->bb_env_mntr_i; + + halbb_mem_cpy(bb, bg_rpt, &env->env_mntr_rpt_bg, + sizeof(struct env_mntr_rpt)); +} + +void halbb_env_mntr_get_bg_setting(struct bb_info *bb, + struct ccx_para_info *bg_para, + enum phl_phy_idx phy_idx) +{ + struct bb_env_mntr_info *env = NULL; + +#ifdef HALBB_DBCC_SUPPORT + bb = halbb_get_curr_bb_pointer(bb, phy_idx); + BB_DBG(bb, DBG_ENV_MNTR, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); +#endif + env = &bb->bb_env_mntr_i; + + halbb_mem_cpy(bb, bg_para, &env->ccx_para_info_bg, + sizeof(struct ccx_para_info)); +} + +u8 halbb_env_mntr_trigger(struct bb_info *bb, struct ccx_para_info *para, + struct env_trig_rpt *trig_rpt) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u8 trigger_result = CCX_FAIL; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + if (halbb_clm_set(bb, para)) + trigger_result |= CLM_SUCCESS; + + if (halbb_nhm_set(bb, para)) + trigger_result |= NHM_SUCCESS; + + if (halbb_fahm_set(bb, para)) + trigger_result |= FAHM_SUCCESS; + + if (halbb_ifs_clm_set(bb, para)) + trigger_result |= IFS_CLM_SUCCESS; + + if (halbb_edcca_clm_set(bb, para)) + trigger_result |= EDCCA_CLM_SUCCESS; + + if (trigger_result) + halbb_ccx_trigger(bb); + + /*monitor for the test duration*/ + env->start_time = halbb_get_sys_time(bb); + + trig_rpt->ccx_rpt_stamp = env->ccx_rpt_stamp; + + /*update bg structure*/ + if (halbb_env_mntr_bg_app_chk(bb) || halbb_env_mntr_dig_app_chk(bb)) + halbb_mem_cpy(bb, &env->ccx_para_info_bg, para, + sizeof(struct ccx_para_info)); + + BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp=%d, trigger_result=0x%x\n", + trig_rpt->ccx_rpt_stamp, trigger_result); + + return trigger_result; +} + +u8 halbb_env_mntr_result(struct bb_info *bb, struct env_mntr_rpt *rpt) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u64 progressing_time = 0; + u8 i = 0; + + /*monitor for the test duration*/ + progressing_time = halbb_get_sys_time(bb); + BB_DBG(bb, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + BB_DBG(bb, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time); + + rpt->ccx_rpt_result = CCX_FAIL; + + /*Get CLM result*/ + if (halbb_clm_get_result(bb)) { + rpt->clm_ratio = env->clm_ratio; + rpt->clm_result = env->clm_result; + rpt->ccx_rpt_result |= CLM_SUCCESS; + } else { + rpt->clm_ratio = ENV_MNTR_FAIL_BYTE; + rpt->clm_result = ENV_MNTR_FAIL_WORD; + } + + /*Get NHM result*/ + if (halbb_nhm_get_result(bb)) { + rpt->nhm_ratio = env->nhm_ratio; + rpt->nhm_tx_ratio = env->nhm_tx_ratio; + rpt->nhm_cca_ratio = env->nhm_cca_ratio; + rpt->nhm_idle_ratio = env->nhm_idle_ratio; + rpt->nhm_tx_cnt = env->nhm_tx_cnt; + rpt->nhm_cca_cnt = env->nhm_cca_cnt; + rpt->nhm_idle_cnt = env->nhm_idle_cnt; + rpt->nhm_pwr = env->nhm_pwr; + rpt->ccx_rpt_result |= NHM_SUCCESS; + halbb_mem_cpy(bb, &rpt->nhm_rpt[0], &env->nhm_rpt[0], + NHM_RPT_NUM); + } else { + rpt->nhm_ratio = ENV_MNTR_FAIL_BYTE; + rpt->nhm_tx_ratio = ENV_MNTR_FAIL_BYTE; + rpt->nhm_cca_ratio = ENV_MNTR_FAIL_BYTE; + rpt->nhm_idle_ratio = ENV_MNTR_FAIL_BYTE; + rpt->nhm_pwr = ENV_MNTR_FAIL_BYTE; + for (i = 0; i < NHM_RPT_NUM; i++) + rpt->nhm_rpt[i] = ENV_MNTR_FAIL_BYTE; + } + + /*Get FAHM result*/ + if (halbb_fahm_get_result(bb)) { + rpt->fahm_ratio = env->fahm_ratio; + rpt->fahm_denom_ratio = env->fahm_denom_ratio; + rpt->fahm_pwr = env->fahm_pwr; + rpt->ccx_rpt_result |= FAHM_SUCCESS; + halbb_mem_cpy(bb, &rpt->fahm_rpt[0], &env->fahm_rpt[0], + FAHM_RPT_NUM); + } else { + rpt->fahm_ratio = ENV_MNTR_FAIL_BYTE; + rpt->fahm_denom_ratio = ENV_MNTR_FAIL_BYTE; + rpt->fahm_pwr = ENV_MNTR_FAIL_BYTE; + for (i = 0; i < FAHM_RPT_NUM; i++) + rpt->fahm_rpt[i] = ENV_MNTR_FAIL_BYTE; + } + + /*Get IFS_CLM result*/ + if (halbb_ifs_clm_get_result(bb)) { + rpt->ifs_clm_tx_ratio = env->ifs_clm_tx_ratio; + rpt->ifs_clm_edcca_excl_cca_ratio = env->ifs_clm_edcca_excl_cca_ratio; + rpt->ifs_clm_cck_fa_ratio = env->ifs_clm_cck_fa_ratio; + rpt->ifs_clm_ofdm_fa_ratio = env->ifs_clm_ofdm_fa_ratio; + rpt->ifs_clm_cck_cca_excl_fa_ratio = env->ifs_clm_cck_cca_excl_fa_ratio; + rpt->ifs_clm_ofdm_cca_excl_fa_ratio = env->ifs_clm_ofdm_cca_excl_fa_ratio; + rpt->ifs_clm_cck_fa_permil = env->ifs_clm_cck_fa_permil; + rpt->ifs_clm_ofdm_fa_permil = env->ifs_clm_ofdm_fa_permil; + rpt->ifs_clm_total_ifs = env->ifs_clm_total_ifs; + for (i = 0; i < IFS_CLM_NUM; i++) { + rpt->ifs_clm_his[i] = env->ifs_clm_his[i]; + rpt->ifs_clm_ifs_avg[i] = env->ifs_clm_ifs_avg[i]; + rpt->ifs_clm_cca_avg[i] = env->ifs_clm_cca_avg[i]; + } + rpt->ccx_rpt_result |= IFS_CLM_SUCCESS; + } else { + rpt->ifs_clm_tx_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_edcca_excl_cca_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_cck_fa_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_ofdm_fa_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_cck_cca_excl_fa_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_ofdm_cca_excl_fa_ratio = ENV_MNTR_FAIL_BYTE; + rpt->ifs_clm_cck_fa_permil = ENV_MNTR_FAIL_WORD; + rpt->ifs_clm_ofdm_fa_permil = ENV_MNTR_FAIL_WORD; + rpt->ifs_clm_total_ifs = ENV_MNTR_FAIL_WORD; + for (i = 0; i < IFS_CLM_NUM; i++) { + rpt->ifs_clm_his[i] = ENV_MNTR_FAIL_WORD; + rpt->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; + rpt->ifs_clm_cca_avg[i] = ENV_MNTR_FAIL_DWORD; + } + } + + /*Get EDCCA_CLM result*/ + if (halbb_edcca_clm_get_result(bb)) { + rpt->edcca_clm_ratio = env->edcca_clm_ratio; + rpt->ccx_rpt_result |= EDCCA_CLM_SUCCESS; + } else { + rpt->edcca_clm_ratio = ENV_MNTR_FAIL_BYTE; + } + + rpt->ccx_rpt_stamp = env->ccx_rpt_stamp; + + BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp=%d, ccx_rpt_result=0x%x\n", + rpt->ccx_rpt_stamp, rpt->ccx_rpt_result); + + /*update bg structure*/ + if (halbb_env_mntr_bg_app_chk(bb) || halbb_env_mntr_dig_app_chk(bb)) + halbb_mem_cpy(bb, &env->env_mntr_rpt_bg, rpt, + sizeof(struct env_mntr_rpt)); + + halbb_ccx_racing_release(bb); + + return rpt->ccx_rpt_result; +} + +/*Environment Monitor*/ +bool +halbb_env_mntr_watchdog_chk(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + u32 sys_return_time = 0; + bool chk_result = HALBB_SET_FAIL; + + sys_return_time = env->ccx_trigger_time + MAX_ENV_MNTR_TIME; + + if ((!halbb_env_mntr_bg_app_chk(bb)) && + (!halbb_env_mntr_init_app_chk(bb)) && + (sys_return_time > bb->bb_sys_up_time)) { + BB_DBG(bb, DBG_ENV_MNTR, + "APP:{CLM, NHM, FAHM, IFS_CLM, EDCCA} = {%d, %d, %d, %d, %d}\n", + env->clm_app, env->nhm_app, env->fahm_app, + env->ifs_clm_app, env->edcca_clm_app); + BB_DBG(bb, DBG_ENV_MNTR, "trigger_time=%d, sys_time=%d\n", + env->ccx_trigger_time, bb->bb_sys_up_time); + } else { + chk_result = HALBB_SET_SUCCESS; + } + + return chk_result; +} + +void halbb_idle_time_pwr_physts(struct bb_info *bb, struct physts_rxd *desc, bool is_cck_rate) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_physts_info *physts = &bb->bb_physts_i; + u16 idle_pwr = 0; /*u(8,1)*/ + + if (is_cck_rate) + idle_pwr = physts->bb_physts_rslt_0_i.avg_idle_noise_pwr_cck; + else + idle_pwr = physts->bb_physts_rslt_1_i.avg_idle_noise_pwr; + + BB_DBG(bb, DBG_PHY_STS, "cck=%d, idle_pwr=%d.%d, nhm_pwr=%d\n", + is_cck_rate, idle_pwr >> 1, (idle_pwr & 1) * 5, env->nhm_pwr); + + if (idle_pwr > (env->nhm_pwr + 10) && env->nhm_pwr != 0) + return; + + if (env->idle_pwr_physts != 0) + env->idle_pwr_physts = MA_ACC(env->idle_pwr_physts, idle_pwr, 2, RSSI_MA_L); + else + env->idle_pwr_physts = idle_pwr << RSSI_MA_L; + + BB_DBG(bb, DBG_PHY_STS, "idle_pwr_physts=%d (%d.%03d)\n", + env->idle_pwr_physts, env->idle_pwr_physts >> 3, (env->idle_pwr_physts & 0x7) * 125); +} + +void halbb_env_mntr(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para = {0}; + struct env_mntr_rpt rpt = {0}; + struct env_trig_rpt trig_rpt = {0}; + u8 chk_result = CCX_FAIL; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + env->ccx_watchdog_result = CCX_FAIL; + + if (!(bb->support_ability & BB_ENVMNTR)) + return; + + if (env->ccx_manual_ctrl) { + BB_DBG(bb, DBG_ENV_MNTR, "CCX in manual ctrl\n"); + return; + } + + if (halbb_env_mntr_watchdog_chk(bb)) { + /*get result*/ + env->ccx_watchdog_result = halbb_env_mntr_result(bb, &rpt); + + /*set parameter*/ + para.mntr_time = 1900; + para.rac_lv = RAC_LV_1; + para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0; + + para.clm_app = CLM_BACKGROUND; + para.clm_input_opt = CLM_CCA_S80_S40_S20; + + para.nhm_app = NHM_BACKGROUND; + para.nhm_incld_cca = NHM_EXCLUDE_CCA; + + para.fahm_app = FAHM_BACKGROUND; + para.fahm_numer_opt = FAHM_INCLU_FA; + para.fahm_denom_opt = FAHM_INCLU_CRC_ERR; + + para.ifs_clm_app = IFS_CLM_BACKGROUND; + + para.edcca_clm_app = EDCCA_CLM_BACKGROUND; + + chk_result = halbb_env_mntr_trigger(bb, ¶, &trig_rpt); + } + + BB_DBG(bb, DBG_ENV_MNTR, "get_result=0x%x, chk_result:0x%x\n", + env->ccx_watchdog_result, chk_result); + + BB_DBG(bb, DBG_ENV_MNTR, "CCX Summary:\n"); + halbb_env_mntr_log(bb, DBG_ENV_MNTR); +} + +void halbb_env_mntr_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + + BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + halbb_ccx_top_setting_init(bb); + halbb_clm_init(bb); + halbb_nhm_init(bb); + halbb_ifs_clm_init(bb); + halbb_fahm_init(bb); + halbb_edcca_clm_init(bb); + env->idle_pwr_physts= 0; +} + +void halbb_env_mntr_bg_log(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct ccx_para_info para = {0}; + struct env_mntr_rpt rpt = {0}; + u8 i = 0; + + halbb_env_mntr_get_bg_setting(bb, ¶, phy_idx); + halbb_env_mntr_get_bg_result(bb, &rpt, phy_idx); + + /*bg_para*/ + BB_DBG(bb, DBG_ENV_MNTR, + "rac_lv = %d, mntr_time = %d, edcca_opt_sc_idx = %d\n", + para.rac_lv, para.mntr_time, para.ccx_edcca_opt_sc_idx); + BB_DBG(bb, DBG_ENV_MNTR, + "APP:{CLM, NHM, FAHM, IFS_CLM, EDCCA} = {%d, %d, %d, %d, %d}\n", + para.clm_app, para.nhm_app, para.fahm_app, para.ifs_clm_app, + para.edcca_clm_app); + BB_DBG(bb, DBG_ENV_MNTR, "clm_input_opt = %d, nhm_inclu_cca = %d\n", + para.clm_input_opt, para.nhm_incld_cca); + BB_DBG(bb, DBG_ENV_MNTR, "fahm_numer_opt = %d, fahm_denom_opt = %d\n", + para.fahm_numer_opt, para.fahm_denom_opt); + + /*bg_rpt*/ + BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp = %d\n", rpt.ccx_rpt_stamp); + BB_DBG(bb, DBG_ENV_MNTR, + "{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n", + rpt.nhm_tx_ratio, rpt.nhm_idle_ratio, rpt.nhm_cca_ratio, + rpt.clm_ratio, rpt.edcca_clm_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "{FA, CRC_err} = {%d, %d} %%\n", + rpt.fahm_ratio, rpt.fahm_denom_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "FA{CCK, OFDM} = {%d, %d} %%\n", + rpt.ifs_clm_cck_fa_ratio, rpt.ifs_clm_ofdm_fa_ratio); + BB_DBG(bb, DBG_ENV_MNTR, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n", + rpt.ifs_clm_cck_cca_excl_fa_ratio, + rpt.ifs_clm_ofdm_cca_excl_fa_ratio); + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + BB_DBG(bb, DBG_ENV_MNTR, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_ENV_MNTR, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.nhm_pwr, rpt.nhm_rpt[10], rpt.nhm_rpt[9], + rpt.nhm_rpt[8], rpt.nhm_rpt[7], rpt.nhm_rpt[6], + rpt.nhm_rpt[5], rpt.nhm_rpt[4], rpt.nhm_rpt[3], + rpt.nhm_rpt[2], rpt.nhm_rpt[1], rpt.nhm_rpt[0]); + BB_DBG(bb, DBG_ENV_MNTR, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.fahm_pwr, rpt.fahm_rpt[10], rpt.fahm_rpt[9], + rpt.fahm_rpt[8], rpt.fahm_rpt[7], rpt.fahm_rpt[6], + rpt.fahm_rpt[5], rpt.fahm_rpt[4], rpt.fahm_rpt[3], + rpt.fahm_rpt[2], rpt.fahm_rpt[1], rpt.fahm_rpt[0]); + } else { + BB_DBG(bb, DBG_ENV_MNTR, + "%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + " Th", NHM_TH_2_RSSI(env->nhm_th[10]), + NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG(bb, DBG_ENV_MNTR, + "[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.nhm_pwr, rpt.nhm_rpt[11], rpt.nhm_rpt[10], + rpt.nhm_rpt[9], rpt.nhm_rpt[8], rpt.nhm_rpt[7], + rpt.nhm_rpt[6], rpt.nhm_rpt[5], rpt.nhm_rpt[4], + rpt.nhm_rpt[3], rpt.nhm_rpt[2], rpt.nhm_rpt[1], + rpt.nhm_rpt[0]); + BB_DBG(bb, DBG_ENV_MNTR, + "[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.fahm_pwr, rpt.fahm_rpt[11], rpt.fahm_rpt[10], + rpt.fahm_rpt[9], rpt.fahm_rpt[8], rpt.fahm_rpt[7], + rpt.fahm_rpt[6], rpt.fahm_rpt[5], rpt.fahm_rpt[4], + rpt.fahm_rpt[3], rpt.fahm_rpt[2], rpt.fahm_rpt[1], + rpt.fahm_rpt[0]); + } + BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio = %d %%\n", rpt.nhm_ratio); + BB_DBG(bb, DBG_ENV_MNTR, + "[IFS] Time(us):[his, ifs_avg(us), cca_avg(us)], total cnt=%d\n", + rpt.ifs_clm_total_ifs); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG(bb, DBG_ENV_MNTR, + " *[%d](%04d~%04d):[%03d, %04d, %04d]\n", i + 1, + halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_l[i]), + halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_h[i]), + rpt.ifs_clm_his[i], rpt.ifs_clm_ifs_avg[i], + rpt.ifs_clm_cca_avg[i]); +} + +void halbb_env_mntr_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct ccx_para_info para = {0}; + struct env_mntr_rpt rpt = {0}; + struct env_trig_rpt trig_rpt = {0}; + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + enum phl_phy_idx phy_idx = HW_PHY_0; + u8 set_result = CCX_FAIL; + u8 i = 0; + + for (i = 0; i < 2; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Basic-Trigger(1900ms): {1}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Adv-Trigger: {2} {0~2097ms}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Get Result: {100}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Get Background Result: {101} {phy_idx}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Show noise {noise}\n"); + } else if (var[0] == 100) { /* Get results */ + set_result = halbb_env_mntr_result(bb, &rpt); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Result=0x%x, ccx_rpt_stamp=%d\n", + set_result, rpt.ccx_rpt_stamp); + + if (set_result) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "{tx, idle, cca_p20, cca_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n", + rpt.nhm_tx_ratio, rpt.nhm_idle_ratio, + rpt.nhm_cca_ratio, rpt.clm_ratio, + rpt.edcca_clm_ratio); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "{FA, CRC32 error} = {%d, %d} %%\n", + rpt.fahm_ratio, rpt.fahm_denom_ratio); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "FA{CCK, OFDM} = {%d, %d} %%\n", + rpt.ifs_clm_cck_fa_ratio, + rpt.ifs_clm_ofdm_fa_ratio); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n", + rpt.ifs_clm_cck_cca_excl_fa_ratio, + rpt.ifs_clm_ofdm_cca_excl_fa_ratio); + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) || + (bb->ic_type == BB_RTL8852C)) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "NHM/FAHM_th(RSSI)[H->L] = [%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "NHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.nhm_rpt[10], rpt.nhm_rpt[9], + rpt.nhm_rpt[8], rpt.nhm_rpt[7], + rpt.nhm_rpt[6], rpt.nhm_rpt[5], + rpt.nhm_rpt[4], rpt.nhm_rpt[3], + rpt.nhm_rpt[2], rpt.nhm_rpt[1], + rpt.nhm_rpt[0]); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "FAHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.fahm_rpt[10], rpt.fahm_rpt[9], + rpt.fahm_rpt[8], rpt.fahm_rpt[7], + rpt.fahm_rpt[6], rpt.fahm_rpt[5], + rpt.fahm_rpt[4], rpt.fahm_rpt[3], + rpt.fahm_rpt[2], rpt.fahm_rpt[1], + rpt.fahm_rpt[0]); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "NHM/FAHM_th(RSSI)[H->L] = [%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + NHM_TH_2_RSSI(env->nhm_th[10]), + NHM_TH_2_RSSI(env->nhm_th[9]), + NHM_TH_2_RSSI(env->nhm_th[8]), + NHM_TH_2_RSSI(env->nhm_th[7]), + NHM_TH_2_RSSI(env->nhm_th[6]), + NHM_TH_2_RSSI(env->nhm_th[5]), + NHM_TH_2_RSSI(env->nhm_th[4]), + NHM_TH_2_RSSI(env->nhm_th[3]), + NHM_TH_2_RSSI(env->nhm_th[2]), + NHM_TH_2_RSSI(env->nhm_th[1]), + NHM_TH_2_RSSI(env->nhm_th[0])); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "NHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.nhm_rpt[11], rpt.nhm_rpt[10], + rpt.nhm_rpt[9], rpt.nhm_rpt[8], + rpt.nhm_rpt[7], rpt.nhm_rpt[6], + rpt.nhm_rpt[5], rpt.nhm_rpt[4], + rpt.nhm_rpt[3], rpt.nhm_rpt[2], + rpt.nhm_rpt[1], rpt.nhm_rpt[0]); + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "FAHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n", + rpt.fahm_rpt[11], rpt.fahm_rpt[10], + rpt.fahm_rpt[9], rpt.fahm_rpt[8], + rpt.fahm_rpt[7], rpt.fahm_rpt[6], + rpt.fahm_rpt[5], rpt.fahm_rpt[4], + rpt.fahm_rpt[3], rpt.fahm_rpt[2], + rpt.fahm_rpt[1], rpt.fahm_rpt[0]); + } + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "nhm_ratio = %d %%, nhm_pwr(RSSI) = %d, fahm_pwr(RSSI)=%d\n", + rpt.nhm_ratio, rpt.nhm_pwr, rpt.fahm_pwr); + + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "IFS_total cnt = %d\n", + rpt.ifs_clm_total_ifs); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Time(us):[his, ifs_avg(us), cca_avg(us)]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, + "T%d(%d ~ %d):[%d, %d, %d]\n", + i + 1, halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_l[i]), + halbb_ccx_idx_cnt_2_us(bb, + env->ifs_clm_th_h[i]), + rpt.ifs_clm_his[i], + rpt.ifs_clm_ifs_avg[i], + rpt.ifs_clm_cca_avg[i]); + } else { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "Get CCX_rpt all Fail\n"); + } + env->ccx_manual_ctrl = false; + } else if (var[0] == 101) { /* Get bg results */ + phy_idx = (enum phl_phy_idx)var[1]; + halbb_env_mntr_bg_log(bb, phy_idx); + } else if (_os_strcmp(input[1], "noise") == 0) { + /*This command is used for customers, do not modify it arbitrarily*/ + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "noise=%d(dBm)\n", env->nhm_pwr - 110); + } else { /* Set & trigger*/ + env->ccx_manual_ctrl = true; + + if (var[0] == 1) + para.mntr_time = 1900; + else if (var[0] == 2) + para.mntr_time = (u16)var[1]; + + para.rac_lv = RAC_LV_4; + + /*clm para*/ + para.clm_app = CLM_DBG; + para.clm_input_opt = CLM_CCA_S80_S40_S20; + + /*nhm para*/ + para.nhm_app = NHM_DBG_11K; + para.nhm_incld_cca = NHM_EXCLUDE_CCA; + + /*fahm para*/ + para.fahm_app = FAHM_DBG_11K; + para.fahm_numer_opt = FAHM_INCLU_FA; + para.fahm_denom_opt = FAHM_INCLU_CRC_ERR; + + /*ifs_clm para*/ + para.ifs_clm_app = IFS_CLM_DBG; + + /*edcca_clm para*/ + para.edcca_clm_app = EDCCA_CLM_DBG; + para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0; + + set_result = halbb_env_mntr_trigger(bb, ¶, &trig_rpt); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Result=0x%x, ccx_rpt_stamp=%d\n", + set_result, trig_rpt.ccx_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} + +u8 halbb_env_mntr_get_802_11_k_rsni(struct bb_info *bb, s8 rcpi, s8 anpi) +{ + u8 rsni = 0; + u8 signal = 0; + u8 sig_to_rsni[13] = {0, 8, 15, 20, 24, 27, 30, 32, 35, 37, 39, 41, 43}; + + /*rcpi = signal + noise + interference = rssi*/ + /*anpi = noise + interferecne = nhm*/ + /*signal = rcpi - anpi*/ + + /*rsni = 2*(10*log10((rcpi_lin/anpi_lin)-1)+10), unit = 0.5dB*/ + /*rcpi_lin/anpi_lin=10^((rcpi_dB-anpi_db)/10)*/ + /*rsni is approximated as 2*((rcpi_db-anpi_db)+10) when signal >= 13*/ + + if (rcpi <= anpi) + signal = 0; + else if (rcpi - anpi >= 117) + signal = 117; + else + signal = rcpi - anpi; + + if (signal < 13) + rsni = sig_to_rsni[signal]; + else + rsni = 2 * (signal + 10); + + return rsni; +} + +void halbb_cr_cfg_env_mntr_init(struct bb_info *bb) +{ + struct bb_env_mntr_info *env = &bb->bb_env_mntr_i; + struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->ccx_en = CCX_EN_A; + cr->ccx_en_m = CCX_EN_A_M; + cr->ccx_trig_opt = CCX_TRIG_OPT_A; + cr->ccx_trig_opt_m = CCX_TRIG_OPT_A_M; + cr->ccx_trig = MEASUREMENT_TRIG_A; + cr->ccx_trig_m = MEASUREMENT_TRIG_A_M; + cr->ccx_edcca_opt = CCX_EDCCA_OPT_A; + cr->ccx_edcca_opt_m = CCX_EDCCA_OPT_A_M; + cr->clm_unit_idx = CLM_COUNTER_UNIT_A; + cr->clm_unit_idx_m = CLM_COUNTER_UNIT_A_M; + cr->clm_opt = CLM_CCA_OPT_A; + cr->clm_opt_m = CLM_CCA_OPT_A_M; + cr->clm_period = CLM_PERIOD_A; + cr->clm_period_m = CLM_PERIOD_A_M; + cr->clm_dbg_sel = CLM_FROM_DBG_SEL_A; + cr->clm_dbg_sel_m = CLM_FROM_DBG_SEL_A_M; + cr->clm_cnt = RO_CLM_RESULT_A; + cr->clm_cnt_m = RO_CLM_RESULT_A_M; + cr->clm_rdy = RO_CLM_RDY_A; + cr->clm_rdy_m = RO_CLM_RDY_A_M; + cr->edcca_clm_period = CLM_EDCCA_PERIOD_A; + cr->edcca_clm_period_m = CLM_EDCCA_PERIOD_A_M; + cr->edcca_clm_unit_idx = CLM_EDCCA_COUNTER_UNIT_A; + cr->edcca_clm_unit_idx_m = CLM_EDCCA_COUNTER_UNIT_A_M; + cr->edcca_clm_cnt = RO_CLM_EDCCA_RESULT_A; + cr->edcca_clm_cnt_m = RO_CLM_EDCCA_RESULT_A_M; + cr->edcca_clm_rdy = RO_CLM_EDCCA_RDY_A; + cr->edcca_clm_rdy_m = RO_CLM_EDCCA_RDY_A_M; + cr->nhm_en = NHM_EN_A; + cr->nhm_en_m = NHM_EN_A_M; + cr->nhm_method_sel = NHM_PWDB_METHOD_SEL_A; + cr->nhm_method_sel_m = NHM_PWDB_METHOD_SEL_A_M; + cr->nhm_period = NHM_PERIOD_A; + cr->nhm_period_m = NHM_PERIOD_A_M; + cr->nhm_unit_idx = NHM_COUNTER_UNIT_A; + cr->nhm_unit_idx_m = NHM_COUNTER_UNIT_A_M; + cr->nhm_inclu_cca = NHM_IGNORE_CCA_A; + cr->nhm_inclu_cca_m = NHM_IGNORE_CCA_A_M; + cr->nhm_th0 = NHM_TH0_A; + cr->nhm_th0_m = NHM_TH0_A_M; + cr->nhm_th1 = NHM_TH1_A; + cr->nhm_th1_m = NHM_TH1_A_M; + cr->nhm_th2 = NHM_TH2_A; + cr->nhm_th2_m = NHM_TH2_A_M; + cr->nhm_th3 = NHM_TH3_A; + cr->nhm_th3_m = NHM_TH3_A_M; + cr->nhm_th4 = NHM_TH4_A; + cr->nhm_th4_m = NHM_TH4_A_M; + cr->nhm_th5 = NHM_TH5_A; + cr->nhm_th5_m = NHM_TH5_A_M; + cr->nhm_th6 = NHM_TH6_A; + cr->nhm_th6_m = NHM_TH6_A_M; + cr->nhm_th7 = NHM_TH7_A; + cr->nhm_th7_m = NHM_TH7_A_M; + cr->nhm_th8 = NHM_TH8_A; + cr->nhm_th8_m = NHM_TH8_A_M; + cr->nhm_th9 = NHM_TH9_A; + cr->nhm_th9_m = NHM_TH9_A_M; + cr->nhm_th10 = NHM_TH10_A; + cr->nhm_th10_m = NHM_TH10_A_M; + cr->nhm_cnt0 = NHM_CNT0_A; + cr->nhm_cnt0_m = NHM_CNT0_A_M; + cr->nhm_cnt1 = NHM_CNT1_A; + cr->nhm_cnt1_m = NHM_CNT1_A_M; + cr->nhm_cnt2 = NHM_CNT2_A; + cr->nhm_cnt2_m = NHM_CNT2_A_M; + cr->nhm_cnt3 = NHM_CNT3_A; + cr->nhm_cnt3_m = NHM_CNT3_A_M; + cr->nhm_cnt4 = NHM_CNT4_A; + cr->nhm_cnt4_m = NHM_CNT4_A_M; + cr->nhm_cnt5 = NHM_CNT5_A; + cr->nhm_cnt5_m = NHM_CNT5_A_M; + cr->nhm_cnt6 = NHM_CNT6_A; + cr->nhm_cnt6_m = NHM_CNT6_A_M; + cr->nhm_cnt7 = NHM_CNT7_A; + cr->nhm_cnt7_m = NHM_CNT7_A_M; + cr->nhm_cnt8 = NHM_CNT8_A; + cr->nhm_cnt8_m = NHM_CNT8_A_M; + cr->nhm_cnt9 = NHM_CNT9_A; + cr->nhm_cnt9_m = NHM_CNT9_A_M; + cr->nhm_cnt10 = NHM_CNT10_A; + cr->nhm_cnt10_m = NHM_CNT10_A_M; + cr->nhm_cnt11 = NHM_CNT11_A; + cr->nhm_cnt11_m = NHM_CNT11_A_M; + cr->nhm_cca_cnt = NHM_CCA_CNT_A; + cr->nhm_cca_cnt_m = NHM_CCA_CNT_A_M; + cr->nhm_tx_cnt = NHM_TXON_CNT_A; + cr->nhm_tx_cnt_m = NHM_TXON_CNT_A_M; + cr->nhm_idle_cnt = NHM_IDLE_CNT_A; + cr->nhm_idle_cnt_m = NHM_IDLE_CNT_A_M; + cr->nhm_rdy = NHM_RDY_A; + cr->nhm_rdy_m = NHM_RDY_A_M; + cr->fahm_ofdm_en = FAHM_EN_OFDM_A; + cr->fahm_ofdm_en_m = FAHM_EN_OFDM_A_M; + cr->fahm_cck_en = FAHM_EN_CCK_A; + cr->fahm_cck_en_m = FAHM_EN_CCK_A_M; + cr->fahm_numer_opt = FAHM_NUM_CANDIDATE_A; + cr->fahm_numer_opt_m = FAHM_NUM_CANDIDATE_A_M; + cr->fahm_denom_opt = FAHM_DEN_CANDIDATE_A; + cr->fahm_denom_opt_m = FAHM_DEN_CANDIDATE_A_M; + cr->fahm_period = FAHM_PERIOD_A; + cr->fahm_period_m = FAHM_PERIOD_A_M; + cr->fahm_unit_idx = FAHM_COUNTER_UNIT_A; + cr->fahm_unit_idx_m = FAHM_COUNTER_UNIT_A_M; + cr->fahm_method_sel = FAHM_PWDB_SEL_A; + cr->fahm_method_sel_m = FAHM_PWDB_SEL_A_M; + cr->fahm_th0 = FAHM_TH0_A; + cr->fahm_th0_m = FAHM_TH0_A_M; + cr->fahm_th1 = FAHM_TH1_A; + cr->fahm_th1_m = FAHM_TH1_A_M; + cr->fahm_th2 = FAHM_TH2_A; + cr->fahm_th2_m = FAHM_TH2_A_M; + cr->fahm_th3 = FAHM_TH3_A; + cr->fahm_th3_m = FAHM_TH3_A_M; + cr->fahm_th4 = FAHM_TH4_A; + cr->fahm_th4_m = FAHM_TH4_A_M; + cr->fahm_th5 = FAHM_TH5_A; + cr->fahm_th5_m = FAHM_TH5_A_M; + cr->fahm_th6 = FAHM_TH6_A; + cr->fahm_th6_m = FAHM_TH6_A_M; + cr->fahm_th7 = FAHM_TH7_A; + cr->fahm_th7_m = FAHM_TH7_A_M; + cr->fahm_th8 = FAHM_TH8_A; + cr->fahm_th8_m = FAHM_TH8_A_M; + cr->fahm_th9 = FAHM_TH9_A; + cr->fahm_th9_m = FAHM_TH9_A_M; + cr->fahm_th10 = FAHM_TH10_A; + cr->fahm_th10_m = FAHM_TH10_A_M; + cr->fahm_dis_count_each_mpdu = FAHM_DIS_COUNT_EACH_MPDU_A; + cr->fahm_dis_count_each_mpdu_m = FAHM_DIS_COUNT_EACH_MPDU_A_M; + cr->fahm_cnt0 = RO_FAHM_NUM0_A; + cr->fahm_cnt0_m = RO_FAHM_NUM0_A_M; + cr->fahm_cnt1 = RO_FAHM_NUM1_A; + cr->fahm_cnt1_m = RO_FAHM_NUM1_A_M; + cr->fahm_cnt2 = RO_FAHM_NUM2_A; + cr->fahm_cnt2_m = RO_FAHM_NUM2_A_M; + cr->fahm_cnt3 = RO_FAHM_NUM3_A; + cr->fahm_cnt3_m = RO_FAHM_NUM3_A_M; + cr->fahm_cnt4 = RO_FAHM_NUM4_A; + cr->fahm_cnt4_m = RO_FAHM_NUM4_A_M; + cr->fahm_cnt5 = RO_FAHM_NUM5_A; + cr->fahm_cnt5_m = RO_FAHM_NUM5_A_M; + cr->fahm_cnt6 = RO_FAHM_NUM6_A; + cr->fahm_cnt6_m = RO_FAHM_NUM6_A_M; + cr->fahm_cnt7 = RO_FAHM_NUM7_A; + cr->fahm_cnt7_m = RO_FAHM_NUM7_A_M; + cr->fahm_cnt8 = RO_FAHM_NUM8_A; + cr->fahm_cnt8_m = RO_FAHM_NUM8_A_M; + cr->fahm_cnt9 = RO_FAHM_NUM9_A; + cr->fahm_cnt9_m = RO_FAHM_NUM9_A_M; + cr->fahm_cnt10 = RO_FAHM_NUM10_A; + cr->fahm_cnt10_m = RO_FAHM_NUM10_A_M; + cr->fahm_cnt11 = RO_FAHM_NUM11_A; + cr->fahm_cnt11_m = RO_FAHM_NUM11_A_M; + cr->fahm_denom_cnt = RO_FAHM_DEN_A; + cr->fahm_denom_cnt_m = RO_FAHM_DEN_A_M; + cr->fahm_rdy = RO_FAHM_RDY_A; + cr->fahm_rdy_m = RO_FAHM_RDY_A_M; + cr->ifs_clm_en = IFS_COLLECT_EN_A; + cr->ifs_clm_en_m = IFS_COLLECT_EN_A_M; + cr->ifs_clm_clr = IFS_COUNTER_CLR_A; + cr->ifs_clm_clr_m = IFS_COUNTER_CLR_A_M; + cr->ifs_clm_period = IFS_COLLECT_TOTAL_TIME_A; + cr->ifs_clm_period_m = IFS_COLLECT_TOTAL_TIME_A_M; + cr->ifs_clm_unit_idx = IFS_COUNTER_UNIT_A; + cr->ifs_clm_unit_idx_m = IFS_COUNTER_UNIT_A_M; + cr->ifs_t1_en = IFS_T1_EN_A; + cr->ifs_t1_en_m = IFS_T1_EN_A_M; + cr->ifs_t2_en = IFS_T2_EN_A; + cr->ifs_t2_en_m = IFS_T2_EN_A_M; + cr->ifs_t3_en = IFS_T3_EN_A; + cr->ifs_t3_en_m = IFS_T3_EN_A_M; + cr->ifs_t4_en = IFS_T4_EN_A; + cr->ifs_t4_en_m = IFS_T4_EN_A_M; + cr->ifs_t1_th_l = IFS_T1_TH_LOW_A; + cr->ifs_t1_th_l_m = IFS_T1_TH_LOW_A_M; + cr->ifs_t2_th_l = IFS_T2_TH_LOW_A; + cr->ifs_t2_th_l_m = IFS_T2_TH_LOW_A_M; + cr->ifs_t3_th_l = IFS_T3_TH_LOW_A; + cr->ifs_t3_th_l_m = IFS_T3_TH_LOW_A_M; + cr->ifs_t4_th_l = IFS_T4_TH_LOW_A; + cr->ifs_t4_th_l_m = IFS_T4_TH_LOW_A_M; + cr->ifs_t1_th_h = IFS_T1_TH_HIGH_A; + cr->ifs_t1_th_h_m = IFS_T1_TH_HIGH_A_M; + cr->ifs_t2_th_h = IFS_T2_TH_HIGH_A; + cr->ifs_t2_th_h_m = IFS_T2_TH_HIGH_A_M; + cr->ifs_t3_th_h = IFS_T3_TH_HIGH_A; + cr->ifs_t3_th_h_m = IFS_T3_TH_HIGH_A_M; + cr->ifs_t4_th_h = IFS_T4_TH_HIGH_A; + cr->ifs_t4_th_h_m = IFS_T4_TH_HIGH_A_M; + cr->ifs_clm_tx_cnt = IFSCNT_CNT_TX_A; + cr->ifs_clm_tx_cnt_m = IFSCNT_CNT_TX_A_M; + cr->ifs_clm_edcca_exclu_cca = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_A; + cr->ifs_clm_edcca_exclu_cca_m = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_A_M; + cr->ifs_clm_cckcca_exclu_fa = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_A; + cr->ifs_clm_cckcca_exclu_fa_m = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_A_M; + cr->ifs_clm_ofdmcca_exclu_fa = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_A; + cr->ifs_clm_ofdmcca_exclu_fa_m = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_A_M; + cr->ifs_clm_cck_fa = IFSCNT_CNT_CCKFA_A; + cr->ifs_clm_cck_fa_m = IFSCNT_CNT_CCKFA_A_M; + cr->ifs_clm_ofdm_fa = IFSCNT_CNT_OFDMFA_A; + cr->ifs_clm_ofdm_fa_m = IFSCNT_CNT_OFDMFA_A_M; + cr->ifs_clm_t1_his = IFS_T1_HIS_A; + cr->ifs_clm_t1_his_m = IFS_T1_HIS_A_M; + cr->ifs_clm_t2_his = IFS_T2_HIS_A; + cr->ifs_clm_t2_his_m = IFS_T2_HIS_A_M; + cr->ifs_clm_t3_his = IFS_T3_HIS_A; + cr->ifs_clm_t3_his_m = IFS_T3_HIS_A_M; + cr->ifs_clm_t4_his = IFS_T4_HIS_A; + cr->ifs_clm_t4_his_m = IFS_T4_HIS_A_M; + cr->ifs_clm_t1_avg = IFS_T1_AVG_A; + cr->ifs_clm_t1_avg_m = IFS_T1_AVG_A_M; + cr->ifs_clm_t2_avg = IFS_T2_AVG_A; + cr->ifs_clm_t2_avg_m = IFS_T2_AVG_A_M; + cr->ifs_clm_t3_avg = IFS_T3_AVG_A; + cr->ifs_clm_t3_avg_m = IFS_T3_AVG_A_M; + cr->ifs_clm_t4_avg = IFS_T4_AVG_A; + cr->ifs_clm_t4_avg_m = IFS_T4_AVG_A_M; + cr->ifs_clm_t1_cca = IFS_T1_CLM_A; + cr->ifs_clm_t1_cca_m = IFS_T1_CLM_A_M; + cr->ifs_clm_t2_cca = IFS_T2_CLM_A; + cr->ifs_clm_t2_cca_m = IFS_T2_CLM_A_M; + cr->ifs_clm_t3_cca = IFS_T3_CLM_A; + cr->ifs_clm_t3_cca_m = IFS_T3_CLM_A_M; + cr->ifs_clm_t4_cca = IFS_T4_CLM_A; + cr->ifs_clm_t4_cca_m = IFS_T4_CLM_A_M; + cr->ifs_total_cnt = IFS_TOTAL_A; + cr->ifs_total_cnt_m = IFS_TOTAL_A_M; + cr->ifs_clm_rdy = IFSCNT_DONE_A; + cr->ifs_clm_rdy_m = IFSCNT_DONE_A_M; + + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->ccx_en = CCX_EN_C; + cr->ccx_en_m = CCX_EN_C_M; + cr->ccx_trig_opt = CCX_TRIG_OPT_C; + cr->ccx_trig_opt_m = CCX_TRIG_OPT_C_M; + cr->ccx_trig = MEASUREMENT_TRIG_C; + cr->ccx_trig_m = MEASUREMENT_TRIG_C_M; + cr->ccx_edcca_opt = CCX_EDCCA_OPT_C; + cr->ccx_edcca_opt_m = CCX_EDCCA_OPT_C_M; + cr->clm_unit_idx = CLM_COUNTER_UNIT_C; + cr->clm_unit_idx_m = CLM_COUNTER_UNIT_C_M; + cr->clm_opt = CLM_CCA_OPT_C; + cr->clm_opt_m = CLM_CCA_OPT_C_M; + cr->clm_period = CLM_PERIOD_C; + cr->clm_period_m = CLM_PERIOD_C_M; + cr->clm_dbg_sel = CLM_FROM_DBG_SEL_C; + cr->clm_dbg_sel_m = CLM_FROM_DBG_SEL_C_M; + cr->clm_cnt = RO_CLM_RESULT_C; + cr->clm_cnt_m = RO_CLM_RESULT_C_M; + cr->clm_rdy = RO_CLM_RDY_C; + cr->clm_rdy_m = RO_CLM_RDY_C_M; + cr->edcca_clm_period = CLM_EDCCA_PERIOD_C; + cr->edcca_clm_period_m = CLM_EDCCA_PERIOD_C_M; + cr->edcca_clm_unit_idx = CLM_EDCCA_COUNTER_UNIT_C; + cr->edcca_clm_unit_idx_m = CLM_EDCCA_COUNTER_UNIT_C_M; + cr->edcca_clm_cnt = RO_CLM_EDCCA_RESULT_C; + cr->edcca_clm_cnt_m = RO_CLM_EDCCA_RESULT_C_M; + cr->edcca_clm_rdy = RO_CLM_EDCCA_RDY_C; + cr->edcca_clm_rdy_m = RO_CLM_EDCCA_RDY_C_M; + cr->nhm_en = NHM_EN_C; + cr->nhm_en_m = NHM_EN_C_M; + cr->nhm_method_sel = NHM_PWDB_METHOD_SEL_C; + cr->nhm_method_sel_m = NHM_PWDB_METHOD_SEL_C_M; + cr->nhm_period = NHM_PERIOD_C; + cr->nhm_period_m = NHM_PERIOD_C_M; + cr->nhm_unit_idx = NHM_COUNTER_UNIT_C; + cr->nhm_unit_idx_m = NHM_COUNTER_UNIT_C_M; + cr->nhm_inclu_cca = NHM_IGNORE_CCA_C; + cr->nhm_inclu_cca_m = NHM_IGNORE_CCA_C_M; + cr->nhm_th0 = NHM_TH0_C; + cr->nhm_th0_m = NHM_TH0_C_M; + cr->nhm_th1 = NHM_TH1_C; + cr->nhm_th1_m = NHM_TH1_C_M; + cr->nhm_th2 = NHM_TH2_C; + cr->nhm_th2_m = NHM_TH2_C_M; + cr->nhm_th3 = NHM_TH3_C; + cr->nhm_th3_m = NHM_TH3_C_M; + cr->nhm_th4 = NHM_TH4_C; + cr->nhm_th4_m = NHM_TH4_C_M; + cr->nhm_th5 = NHM_TH5_C; + cr->nhm_th5_m = NHM_TH5_C_M; + cr->nhm_th6 = NHM_TH6_C; + cr->nhm_th6_m = NHM_TH6_C_M; + cr->nhm_th7 = NHM_TH7_C; + cr->nhm_th7_m = NHM_TH7_C_M; + cr->nhm_th8 = NHM_TH8_C; + cr->nhm_th8_m = NHM_TH8_C_M; + cr->nhm_th9 = NHM_TH9_C; + cr->nhm_th9_m = NHM_TH9_C_M; + cr->nhm_th10 = NHM_TH10_C; + cr->nhm_th10_m = NHM_TH10_C_M; + cr->fahm_dis_count_each_mpdu = FAHM_DIS_COUNT_EACH_MPDU_C; + cr->fahm_dis_count_each_mpdu_m = FAHM_DIS_COUNT_EACH_MPDU_C_M; + cr->nhm_cnt0 = NHM_CNT0_C; + cr->nhm_cnt0_m = NHM_CNT0_C_M; + cr->nhm_cnt1 = NHM_CNT1_C; + cr->nhm_cnt1_m = NHM_CNT1_C_M; + cr->nhm_cnt2 = NHM_CNT2_C; + cr->nhm_cnt2_m = NHM_CNT2_C_M; + cr->nhm_cnt3 = NHM_CNT3_C; + cr->nhm_cnt3_m = NHM_CNT3_C_M; + cr->nhm_cnt4 = NHM_CNT4_C; + cr->nhm_cnt4_m = NHM_CNT4_C_M; + cr->nhm_cnt5 = NHM_CNT5_C; + cr->nhm_cnt5_m = NHM_CNT5_C_M; + cr->nhm_cnt6 = NHM_CNT6_C; + cr->nhm_cnt6_m = NHM_CNT6_C_M; + cr->nhm_cnt7 = NHM_CNT7_C; + cr->nhm_cnt7_m = NHM_CNT7_C_M; + cr->nhm_cnt8 = NHM_CNT8_C; + cr->nhm_cnt8_m = NHM_CNT8_C_M; + cr->nhm_cnt9 = NHM_CNT9_C; + cr->nhm_cnt9_m = NHM_CNT9_C_M; + cr->nhm_cnt10 = NHM_CNT10_C; + cr->nhm_cnt10_m = NHM_CNT10_C_M; + cr->nhm_cnt11 = NHM_CNT11_C; + cr->nhm_cnt11_m = NHM_CNT11_C_M; + cr->nhm_cca_cnt = NHM_CCA_CNT_C; + cr->nhm_cca_cnt_m = NHM_CCA_CNT_C_M; + cr->nhm_tx_cnt = NHM_TXON_CNT_C; + cr->nhm_tx_cnt_m = NHM_TXON_CNT_C_M; + cr->nhm_idle_cnt = NHM_IDLE_CNT_C; + cr->nhm_idle_cnt_m = NHM_IDLE_CNT_C_M; + cr->nhm_rdy = NHM_RDY_C; + cr->nhm_rdy_m = NHM_RDY_C_M; + cr->fahm_ofdm_en = FAHM_EN_OFDM_C; + cr->fahm_ofdm_en_m = FAHM_EN_OFDM_C_M; + cr->fahm_cck_en = FAHM_EN_CCK_C; + cr->fahm_cck_en_m = FAHM_EN_CCK_C_M; + cr->fahm_numer_opt = FAHM_NUM_CANDIDATE_C; + cr->fahm_numer_opt_m = FAHM_NUM_CANDIDATE_C_M; + cr->fahm_denom_opt = FAHM_DEN_CANDIDATE_C; + cr->fahm_denom_opt_m = FAHM_DEN_CANDIDATE_C_M; + cr->fahm_period = FAHM_PERIOD_C; + cr->fahm_period_m = FAHM_PERIOD_C_M; + cr->fahm_unit_idx = FAHM_COUNTER_UNIT_C; + cr->fahm_unit_idx_m = FAHM_COUNTER_UNIT_C_M; + cr->fahm_method_sel = FAHM_PWDB_SEL_C; + cr->fahm_method_sel_m = FAHM_PWDB_SEL_C_M; + cr->fahm_th0 = FAHM_TH0_C; + cr->fahm_th0_m = FAHM_TH0_C_M; + cr->fahm_th1 = FAHM_TH1_C; + cr->fahm_th1_m = FAHM_TH1_C_M; + cr->fahm_th2 = FAHM_TH2_C; + cr->fahm_th2_m = FAHM_TH2_C_M; + cr->fahm_th3 = FAHM_TH3_C; + cr->fahm_th3_m = FAHM_TH3_C_M; + cr->fahm_th4 = FAHM_TH4_C; + cr->fahm_th4_m = FAHM_TH4_C_M; + cr->fahm_th5 = FAHM_TH5_C; + cr->fahm_th5_m = FAHM_TH5_C_M; + cr->fahm_th6 = FAHM_TH6_C; + cr->fahm_th6_m = FAHM_TH6_C_M; + cr->fahm_th7 = FAHM_TH7_C; + cr->fahm_th7_m = FAHM_TH7_C_M; + cr->fahm_th8 = FAHM_TH8_C; + cr->fahm_th8_m = FAHM_TH8_C_M; + cr->fahm_th9 = FAHM_TH9_C; + cr->fahm_th9_m = FAHM_TH9_C_M; + cr->fahm_th10 = FAHM_TH10_C; + cr->fahm_th10_m = FAHM_TH10_C_M; + cr->fahm_cnt0 = RO_FAHM_NUM0_C; + cr->fahm_cnt0_m = RO_FAHM_NUM0_C_M; + cr->fahm_cnt1 = RO_FAHM_NUM1_C; + cr->fahm_cnt1_m = RO_FAHM_NUM1_C_M; + cr->fahm_cnt2 = RO_FAHM_NUM2_C; + cr->fahm_cnt2_m = RO_FAHM_NUM2_C_M; + cr->fahm_cnt3 = RO_FAHM_NUM3_C; + cr->fahm_cnt3_m = RO_FAHM_NUM3_C_M; + cr->fahm_cnt4 = RO_FAHM_NUM4_C; + cr->fahm_cnt4_m = RO_FAHM_NUM4_C_M; + cr->fahm_cnt5 = RO_FAHM_NUM5_C; + cr->fahm_cnt5_m = RO_FAHM_NUM5_C_M; + cr->fahm_cnt6 = RO_FAHM_NUM6_C; + cr->fahm_cnt6_m = RO_FAHM_NUM6_C_M; + cr->fahm_cnt7 = RO_FAHM_NUM7_C; + cr->fahm_cnt7_m = RO_FAHM_NUM7_C_M; + cr->fahm_cnt8 = RO_FAHM_NUM8_C; + cr->fahm_cnt8_m = RO_FAHM_NUM8_C_M; + cr->fahm_cnt9 = RO_FAHM_NUM9_C; + cr->fahm_cnt9_m = RO_FAHM_NUM9_C_M; + cr->fahm_cnt10 = RO_FAHM_NUM10_C; + cr->fahm_cnt10_m = RO_FAHM_NUM10_C_M; + cr->fahm_cnt11 = RO_FAHM_NUM11_C; + cr->fahm_cnt11_m = RO_FAHM_NUM11_C_M; + cr->fahm_denom_cnt = RO_FAHM_DEN_C; + cr->fahm_denom_cnt_m = RO_FAHM_DEN_C_M; + cr->fahm_rdy = RO_FAHM_RDY_C; + cr->fahm_rdy_m = RO_FAHM_RDY_C_M; + cr->ifs_clm_en = IFS_COLLECT_EN_C; + cr->ifs_clm_en_m = IFS_COLLECT_EN_C_M; + cr->ifs_clm_clr = IFS_COUNTER_CLR_C; + cr->ifs_clm_clr_m = IFS_COUNTER_CLR_C_M; + cr->ifs_clm_period = IFS_COLLECT_TOTAL_TIME_C; + cr->ifs_clm_period_m = IFS_COLLECT_TOTAL_TIME_C_M; + cr->ifs_clm_unit_idx = IFS_COUNTER_UNIT_C; + cr->ifs_clm_unit_idx_m = IFS_COUNTER_UNIT_C_M; + cr->ifs_t1_en = IFS_T1_EN_C; + cr->ifs_t1_en_m = IFS_T1_EN_C_M; + cr->ifs_t2_en = IFS_T2_EN_C; + cr->ifs_t2_en_m = IFS_T2_EN_C_M; + cr->ifs_t3_en = IFS_T3_EN_C; + cr->ifs_t3_en_m = IFS_T3_EN_C_M; + cr->ifs_t4_en = IFS_T4_EN_C; + cr->ifs_t4_en_m = IFS_T4_EN_C_M; + cr->ifs_t1_th_l = IFS_T1_TH_LOW_C; + cr->ifs_t1_th_l_m = IFS_T1_TH_LOW_C_M; + cr->ifs_t2_th_l = IFS_T2_TH_LOW_C; + cr->ifs_t2_th_l_m = IFS_T2_TH_LOW_C_M; + cr->ifs_t3_th_l = IFS_T3_TH_LOW_C; + cr->ifs_t3_th_l_m = IFS_T3_TH_LOW_C_M; + cr->ifs_t4_th_l = IFS_T4_TH_LOW_C; + cr->ifs_t4_th_l_m = IFS_T4_TH_LOW_C_M; + cr->ifs_t1_th_h = IFS_T1_TH_HIGH_C; + cr->ifs_t1_th_h_m = IFS_T1_TH_HIGH_C_M; + cr->ifs_t2_th_h = IFS_T2_TH_HIGH_C; + cr->ifs_t2_th_h_m = IFS_T2_TH_HIGH_C_M; + cr->ifs_t3_th_h = IFS_T3_TH_HIGH_C; + cr->ifs_t3_th_h_m = IFS_T3_TH_HIGH_C_M; + cr->ifs_t4_th_h = IFS_T4_TH_HIGH_C; + cr->ifs_t4_th_h_m = IFS_T4_TH_HIGH_C_M; + cr->ifs_clm_tx_cnt = IFSCNT_CNT_TX_C; + cr->ifs_clm_tx_cnt_m = IFSCNT_CNT_TX_C_M; + cr->ifs_clm_edcca_exclu_cca = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C; + cr->ifs_clm_edcca_exclu_cca_m = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C_M; + cr->ifs_clm_cckcca_exclu_fa = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C; + cr->ifs_clm_cckcca_exclu_fa_m = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C_M; + cr->ifs_clm_ofdmcca_exclu_fa = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C; + cr->ifs_clm_ofdmcca_exclu_fa_m = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C_M; + cr->ifs_clm_cck_fa = IFSCNT_CNT_CCKFA_C; + cr->ifs_clm_cck_fa_m = IFSCNT_CNT_CCKFA_C_M; + cr->ifs_clm_ofdm_fa = IFSCNT_CNT_OFDMFA_C; + cr->ifs_clm_ofdm_fa_m = IFSCNT_CNT_OFDMFA_C_M; + cr->ifs_clm_t1_his = IFS_T1_HIS_C; + cr->ifs_clm_t1_his_m = IFS_T1_HIS_C_M; + cr->ifs_clm_t2_his = IFS_T2_HIS_C; + cr->ifs_clm_t2_his_m = IFS_T2_HIS_C_M; + cr->ifs_clm_t3_his = IFS_T3_HIS_C; + cr->ifs_clm_t3_his_m = IFS_T3_HIS_C_M; + cr->ifs_clm_t4_his = IFS_T4_HIS_C; + cr->ifs_clm_t4_his_m = IFS_T4_HIS_C_M; + cr->ifs_clm_t1_avg = IFS_T1_AVG_C; + cr->ifs_clm_t1_avg_m = IFS_T1_AVG_C_M; + cr->ifs_clm_t2_avg = IFS_T2_AVG_C; + cr->ifs_clm_t2_avg_m = IFS_T2_AVG_C_M; + cr->ifs_clm_t3_avg = IFS_T3_AVG_C; + cr->ifs_clm_t3_avg_m = IFS_T3_AVG_C_M; + cr->ifs_clm_t4_avg = IFS_T4_AVG_C; + cr->ifs_clm_t4_avg_m = IFS_T4_AVG_C_M; + cr->ifs_clm_t1_cca = IFS_T1_CLM_C; + cr->ifs_clm_t1_cca_m = IFS_T1_CLM_C_M; + cr->ifs_clm_t2_cca = IFS_T2_CLM_C; + cr->ifs_clm_t2_cca_m = IFS_T2_CLM_C_M; + cr->ifs_clm_t3_cca = IFS_T3_CLM_C; + cr->ifs_clm_t3_cca_m = IFS_T3_CLM_C_M; + cr->ifs_clm_t4_cca = IFS_T4_CLM_C; + cr->ifs_clm_t4_cca_m = IFS_T4_CLM_C_M; + cr->ifs_total_cnt = IFS_TOTAL_C; + cr->ifs_total_cnt_m = IFS_TOTAL_C_M; + cr->ifs_clm_rdy = IFSCNT_DONE_C; + cr->ifs_clm_rdy_m = IFSCNT_DONE_C_M; + break; + #endif + + default: + break; + } + +} + + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_env_mntr.h b/phl/hal_g6/phy/bb/halbb_env_mntr.h new file mode 100644 index 0000000..8f7dcd2 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_env_mntr.h @@ -0,0 +1,428 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_ENV_MNTR_H__ +#define __HALBB_ENV_MNTR_H__ + +/*--------------------------[Define] ---------------------------------------*/ +#define ENV_MNTR_FAIL_BYTE 0xff +#define ENV_MNTR_FAIL_WORD 0xffff +#define ENV_MNTR_FAIL_DWORD 0xffffffff +#define MAX_ENV_MNTR_TIME 8 /*second*/ +#define MS_TO_4US_RATIO 250 +/*NHM*/ +#define RSSI_2_NHM_TH(rssi) ((rssi) << 1) /*NHM_threshold = u(8,1)*/ +#define NHM_TH_2_RSSI(th) (th >> 1) +#define NHM_PWR_OFST 20 +#define NHM_NOISE_F_TH 60 /*60/2 = 30 = -80 dBm*/ +#define NHM_WA_TH 109 /*109 = -1 dBm*/ +#define NHM_WA_PWR 26 /*26 - 110 = -84dBm, only for 52A*/ +/*FAHM*/ +#define RSSI_2_FAHM_TH(rssi) ((rssi) << 1) /*FAHM_threshold = u(8,1)*/ +#define FAHM_TH_2_RSSI(th) (th >> 1) +#define FAHM_PWR_OFST 20 +#define FAHM_WA_TH 109 /*109 = -1 dBm*/ + +/*--------------------------[Enum]------------------------------------------*/ +enum ccx_unit { + CCX_04_US = 0, /*4us*/ + CCX_08_US = 1, /*8us*/ + CCX_16_US = 2, /*16us*/ + CCX_32_US = 3 /*32us*/ +}; + +enum ccx_func_sel { + NHM_SEL = BIT(0), + CLM_SEL = BIT(1), + FAHM_SEL = BIT(2), + IFS_CLM_SEL = BIT(3), + EDCCA_CLM_SEL = BIT(4), +}; + +enum ccx_edcca_opt_bw_idx { + CCX_EDCCA_BW20_0 = 0, /*seg0:SC=4*/ + CCX_EDCCA_BW20_1 = 1, /*seg0:SC=2*/ + CCX_EDCCA_BW20_2 = 2, /*seg0:SC=1*/ + CCX_EDCCA_BW20_3 = 3, /*seg0:SC=3*/ + CCX_EDCCA_BW20_4 = 4, /*seg1:SC=4*/ + CCX_EDCCA_BW20_5 = 5, /*seg1:SC=2*/ + CCX_EDCCA_BW20_6 = 6, /*seg1:SC=1*/ + CCX_EDCCA_BW20_7 = 7 /*seg2:SC=3*/ +}; + +/*--------------------------[Structure]-------------------------------------*/ + +struct bb_env_mntr_cr_info { + u32 ccx_en; + u32 ccx_en_m; + u32 ccx_trig_opt; + u32 ccx_trig_opt_m; + u32 ccx_trig; + u32 ccx_trig_m; + u32 ccx_edcca_opt; + u32 ccx_edcca_opt_m; + u32 clm_unit_idx; + u32 clm_unit_idx_m; + u32 clm_opt; + u32 clm_opt_m; + u32 clm_period; + u32 clm_period_m; + u32 clm_dbg_sel; + u32 clm_dbg_sel_m; + u32 clm_cnt; + u32 clm_cnt_m; + u32 clm_rdy; + u32 clm_rdy_m; + u32 edcca_clm_period; + u32 edcca_clm_period_m; + u32 edcca_clm_unit_idx; + u32 edcca_clm_unit_idx_m; + u32 edcca_clm_cnt; + u32 edcca_clm_cnt_m; + u32 edcca_clm_rdy; + u32 edcca_clm_rdy_m; + u32 nhm_en; + u32 nhm_en_m; + u32 nhm_method_sel; + u32 nhm_method_sel_m; + u32 nhm_period; + u32 nhm_period_m; + u32 nhm_unit_idx; + u32 nhm_unit_idx_m; + u32 nhm_inclu_cca; + u32 nhm_inclu_cca_m; + u32 nhm_th0; + u32 nhm_th0_m; + u32 nhm_th1; + u32 nhm_th1_m; + u32 nhm_th2; + u32 nhm_th2_m; + u32 nhm_th3; + u32 nhm_th3_m; + u32 nhm_th4; + u32 nhm_th4_m; + u32 nhm_th5; + u32 nhm_th5_m; + u32 nhm_th6; + u32 nhm_th6_m; + u32 nhm_th7; + u32 nhm_th7_m; + u32 nhm_th8; + u32 nhm_th8_m; + u32 nhm_th9; + u32 nhm_th9_m; + u32 nhm_th10; + u32 nhm_th10_m; + u32 nhm_cnt0; + u32 nhm_cnt0_m; + u32 nhm_cnt1; + u32 nhm_cnt1_m; + u32 nhm_cnt2; + u32 nhm_cnt2_m; + u32 nhm_cnt3; + u32 nhm_cnt3_m; + u32 nhm_cnt4; + u32 nhm_cnt4_m; + u32 nhm_cnt5; + u32 nhm_cnt5_m; + u32 nhm_cnt6; + u32 nhm_cnt6_m; + u32 nhm_cnt7; + u32 nhm_cnt7_m; + u32 nhm_cnt8; + u32 nhm_cnt8_m; + u32 nhm_cnt9; + u32 nhm_cnt9_m; + u32 nhm_cnt10; + u32 nhm_cnt10_m; + u32 nhm_cnt11; + u32 nhm_cnt11_m; + u32 nhm_cca_cnt; + u32 nhm_cca_cnt_m; + u32 nhm_tx_cnt; + u32 nhm_tx_cnt_m; + u32 nhm_idle_cnt; + u32 nhm_idle_cnt_m; + u32 nhm_rdy; + u32 nhm_rdy_m; + u32 fahm_ofdm_en; + u32 fahm_ofdm_en_m; + u32 fahm_cck_en; + u32 fahm_cck_en_m; + u32 fahm_numer_opt; + u32 fahm_numer_opt_m; + u32 fahm_denom_opt; + u32 fahm_denom_opt_m; + u32 fahm_dis_count_each_mpdu; + u32 fahm_dis_count_each_mpdu_m; + u32 fahm_period; + u32 fahm_period_m; + u32 fahm_unit_idx; + u32 fahm_unit_idx_m; + u32 fahm_method_sel; + u32 fahm_method_sel_m; + u32 fahm_th0; + u32 fahm_th0_m; + u32 fahm_th1; + u32 fahm_th1_m; + u32 fahm_th2; + u32 fahm_th2_m; + u32 fahm_th3; + u32 fahm_th3_m; + u32 fahm_th4; + u32 fahm_th4_m; + u32 fahm_th5; + u32 fahm_th5_m; + u32 fahm_th6; + u32 fahm_th6_m; + u32 fahm_th7; + u32 fahm_th7_m; + u32 fahm_th8; + u32 fahm_th8_m; + u32 fahm_th9; + u32 fahm_th9_m; + u32 fahm_th10; + u32 fahm_th10_m; + u32 fahm_cnt0; + u32 fahm_cnt0_m; + u32 fahm_cnt1; + u32 fahm_cnt1_m; + u32 fahm_cnt2; + u32 fahm_cnt2_m; + u32 fahm_cnt3; + u32 fahm_cnt3_m; + u32 fahm_cnt4; + u32 fahm_cnt4_m; + u32 fahm_cnt5; + u32 fahm_cnt5_m; + u32 fahm_cnt6; + u32 fahm_cnt6_m; + u32 fahm_cnt7; + u32 fahm_cnt7_m; + u32 fahm_cnt8; + u32 fahm_cnt8_m; + u32 fahm_cnt9; + u32 fahm_cnt9_m; + u32 fahm_cnt10; + u32 fahm_cnt10_m; + u32 fahm_cnt11; + u32 fahm_cnt11_m; + u32 fahm_denom_cnt; + u32 fahm_denom_cnt_m; + u32 fahm_rdy; + u32 fahm_rdy_m; + u32 ifs_clm_en; + u32 ifs_clm_en_m; + u32 ifs_clm_clr; + u32 ifs_clm_clr_m; + u32 ifs_clm_period; + u32 ifs_clm_period_m; + u32 ifs_clm_unit_idx; + u32 ifs_clm_unit_idx_m; + u32 ifs_t1_en; + u32 ifs_t1_en_m; + u32 ifs_t2_en; + u32 ifs_t2_en_m; + u32 ifs_t3_en; + u32 ifs_t3_en_m; + u32 ifs_t4_en; + u32 ifs_t4_en_m; + u32 ifs_t1_th_l; + u32 ifs_t1_th_l_m; + u32 ifs_t2_th_l; + u32 ifs_t2_th_l_m; + u32 ifs_t3_th_l; + u32 ifs_t3_th_l_m; + u32 ifs_t4_th_l; + u32 ifs_t4_th_l_m; + u32 ifs_t1_th_h; + u32 ifs_t1_th_h_m; + u32 ifs_t2_th_h; + u32 ifs_t2_th_h_m; + u32 ifs_t3_th_h; + u32 ifs_t3_th_h_m; + u32 ifs_t4_th_h; + u32 ifs_t4_th_h_m; + u32 ifs_clm_tx_cnt; + u32 ifs_clm_tx_cnt_m; + u32 ifs_clm_edcca_exclu_cca; + u32 ifs_clm_edcca_exclu_cca_m; + u32 ifs_clm_cckcca_exclu_fa; + u32 ifs_clm_cckcca_exclu_fa_m; + u32 ifs_clm_ofdmcca_exclu_fa; + u32 ifs_clm_ofdmcca_exclu_fa_m; + u32 ifs_clm_cck_fa; + u32 ifs_clm_cck_fa_m; + u32 ifs_clm_ofdm_fa; + u32 ifs_clm_ofdm_fa_m; + u32 ifs_clm_t1_his; + u32 ifs_clm_t1_his_m; + u32 ifs_clm_t2_his; + u32 ifs_clm_t2_his_m; + u32 ifs_clm_t3_his; + u32 ifs_clm_t3_his_m; + u32 ifs_clm_t4_his; + u32 ifs_clm_t4_his_m; + u32 ifs_clm_t1_avg; + u32 ifs_clm_t1_avg_m; + u32 ifs_clm_t2_avg; + u32 ifs_clm_t2_avg_m; + u32 ifs_clm_t3_avg; + u32 ifs_clm_t3_avg_m; + u32 ifs_clm_t4_avg; + u32 ifs_clm_t4_avg_m; + u32 ifs_clm_t1_cca; + u32 ifs_clm_t1_cca_m; + u32 ifs_clm_t2_cca; + u32 ifs_clm_t2_cca_m; + u32 ifs_clm_t3_cca; + u32 ifs_clm_t3_cca_m; + u32 ifs_clm_t4_cca; + u32 ifs_clm_t4_cca_m; + u32 ifs_total_cnt; + u32 ifs_total_cnt_m; + u32 ifs_clm_rdy; + u32 ifs_clm_rdy_m; +}; + +struct bb_env_mntr_info { + struct bb_env_mntr_cr_info bb_env_mntr_cr_i; + /*sw ctrl*/ + u32 ccx_trigger_time; + u64 start_time; + u8 ccx_rpt_stamp; + u8 ccx_watchdog_result; + bool ccx_ongoing; + u8 ccx_rac_lv; + bool ccx_manual_ctrl; + u8 ccx_pre_rssi; + u16 clm_mntr_time; /*0~2097 ms*/ + enum clm_application clm_app; + u16 nhm_mntr_time; /*0~2097 ms*/ + enum nhm_application nhm_app; + u16 ifs_clm_mntr_time; /*0~2097 ms*/ + enum ifs_clm_application ifs_clm_app; + u16 fahm_mntr_time; /*0~2097 ms*/ + enum fahm_application fahm_app; + u16 edcca_clm_mntr_time; /*0~2097 ms*/ + enum edcca_clm_application edcca_clm_app; + /*hw ctrl*/ + u16 ccx_period; + u8 ccx_unit_idx; /*0/1/2/3 : 4/8/16/32 us*/ + enum ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; + enum clm_opt_input clm_input_opt; + enum nhm_option_cca_all nhm_include_cca; + u8 nhm_th[NHM_TH_NUM]; + u16 ifs_clm_th_l[IFS_CLM_NUM]; + u16 ifs_clm_th_h[IFS_CLM_NUM]; + u8 fahm_numer_opt; + u8 fahm_denom_opt; + u8 fahm_th[FAHM_TH_NUM]; + /*hw report*/ + u16 clm_result; /*sample cnt*/ + u16 nhm_result[NHM_RPT_NUM]; /*sample cnt*/ + u16 nhm_tx_cnt; /*sample cnt*/ + u16 nhm_cca_cnt; /*sample cnt*/ + u16 nhm_idle_cnt; /*sample cnt*/ + u16 ifs_clm_tx; /*sample cnt*/ + u16 ifs_clm_edcca_excl_cca; /*sample cnt*/ + u16 ifs_clm_ofdmfa; /*sample cnt*/ + u16 ifs_clm_ofdmcca_excl_fa; /*sample cnt*/ + u16 ifs_clm_cckfa; /*sample cnt*/ + u16 ifs_clm_cckcca_excl_fa; /*sample cnt*/ + u16 ifs_clm_total_ifs; /*cnt*/ + u16 ifs_clm_his[IFS_CLM_NUM]; /*cnt*/ + u16 ifs_clm_avg[IFS_CLM_NUM]; /*sample cnt*/ + u16 ifs_clm_cca[IFS_CLM_NUM]; /*sample cnt*/ + u16 fahm_result[FAHM_RPT_NUM]; /*sample cnt*/ + u16 fahm_denom_result; /*sample cnt*/ + u16 edcca_clm_result; /*sample cnt*/ + /*sw report*/ + u8 clm_ratio; /*percent*/ + u16 nhm_sw_result[NHM_RPT_NUM]; /*sample cnt*/ + u8 nhm_wgt[NHM_RPT_NUM]; /*dBm+110*/ + u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/ + u8 nhm_tx_ratio; /*percent*/ + u8 nhm_cca_ratio; /*percent*/ + u8 nhm_idle_ratio; /*percent*/ + u8 nhm_ratio; /*percent*/ + u16 nhm_result_sum; /*sample cnt*/ + u8 nhm_pwr; /*dBm+110*/ + u8 ifs_clm_tx_ratio; /*percent*/ + u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/ + u8 ifs_clm_cck_fa_ratio; /*percent*/ + u8 ifs_clm_ofdm_fa_ratio; /*percent*/ + u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/ + u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/ + u16 ifs_clm_cck_fa_permil; /*permil*/ + u16 ifs_clm_ofdm_fa_permil; /*permil*/ + u32 ifs_clm_ifs_avg[IFS_CLM_NUM]; /*us*/ + u32 ifs_clm_cca_avg[IFS_CLM_NUM]; /*us*/ + u16 fahm_sw_result[FAHM_RPT_NUM]; /*sample cnt*/ + u8 fahm_wgt[FAHM_RPT_NUM]; /*dBm+110*/ + u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/ + u16 fahm_result_sum; /*sample cnt*/ + u8 fahm_ratio; /*percent*/ + u8 fahm_denom_ratio; /*percent*/ + u8 fahm_pwr; /*dBm+110*/ + u8 edcca_clm_ratio; /*percent*/ + u8 edcca_noise_bg; /*dBm+110, only for 52A*/ + struct env_mntr_rpt env_mntr_rpt_bg; + struct ccx_para_info ccx_para_info_bg; + u16 idle_pwr_physts; /*RSSI u(16,3) Idle time pwr from physts*/ +}; + +/*--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; + +u32 halbb_ccx_idx_cnt_2_us(struct bb_info *bb, u16 idx_cnt); + +#ifdef CLM_SUPPORT +void halbb_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#ifdef NHM_SUPPORT +void halbb_nhm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#ifdef IFS_CLM_SUPPORT +void halbb_ifs_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#ifdef FAHM_SUPPORT +void halbb_fahm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#ifdef EDCCA_CLM_SUPPORT +void halbb_edcca_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +void halbb_env_mntr_log(struct bb_info *bb, u32 dbg_comp); +void halbb_idle_time_pwr_physts(struct bb_info *bb, struct physts_rxd *desc, bool is_cck_rate); +void halbb_env_mntr(struct bb_info *bb); +void halbb_env_mntr_init(struct bb_info *bb); +void halbb_env_mntr_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_env_mntr_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_env_mntr_ex.h b/phl/hal_g6/phy/bb/halbb_env_mntr_ex.h new file mode 100644 index 0000000..777fdba --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_env_mntr_ex.h @@ -0,0 +1,216 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_ENV_MNTR_EX_H__ +#define __HALBB_ENV_MNTR_EX_H__ + +/*--------------------------[Define] ---------------------------------------*/ + +/*NHM*/ +#define NHM_TH_NUM 11 /*threshold number of NHM*/ +#define NHM_RPT_NUM 12 +/*FAHM*/ +#define FAHM_INCLU_FA BIT(0) +#define FAHM_INCLU_CRC_OK BIT(1) +#define FAHM_INCLU_CRC_ERR BIT(2) +#define FAHM_TH_NUM 11 /*threshold number of FAHM*/ +#define FAHM_RPT_NUM 12 +/*IFS-CLM*/ +#define IFS_CLM_NUM 4 + +/*--------------------------[Enum]------------------------------------------*/ +enum mntr_result_lv { + CCX_FAIL = 0, + NHM_SUCCESS = BIT(0), + CLM_SUCCESS = BIT(1), + FAHM_SUCCESS = BIT(2), + IFS_CLM_SUCCESS = BIT(3), + EDCCA_CLM_SUCCESS = BIT(4), + CCX_SUCCESS = 0x1f, +}; + +enum halbb_racing_lv { + RAC_RELEASE = 0, + RAC_LV_1 = 1, /* Low Priority function */ + RAC_LV_2 = 2, /* Middle Priority function */ + RAC_LV_3 = 3, /* High priority function (ex: Check hang function) */ + RAC_LV_4 = 4, /* Debug function (the highest priority) */ + RAC_MAX_NUM = 5 +}; + +enum ccx_edcca_opt_sc_idx { + CCX_EDCCA_SEG0_P0 = 0, /*seg0:p20*/ + CCX_EDCCA_SEG0_S1 = 1, /*seg0:s20*/ + CCX_EDCCA_SEG0_S2 = 2, /*seg0:s40, opposite of p20*/ + CCX_EDCCA_SEG0_S3 = 3, /*seg0:s40, opposite of s20*/ + CCX_EDCCA_SEG1_P0 = 4, /*seg1:p20*/ + CCX_EDCCA_SEG1_S1 = 5, /*seg1:s20*/ + CCX_EDCCA_SEG1_S2 = 6, /*seg1:s40, opposite of p20*/ + CCX_EDCCA_SEG1_S3 = 7 /*seg1:s40, opposite of s20*/ +}; + +enum nhm_option_cca_all { + NHM_EXCLUDE_CCA = 0, + NHM_INCLUDE_CCA = 1, + NHM_CCA_INIT +}; + +enum clm_opt_input { + CLM_CCA_P20 = 0, + CLM_CCA_S20 = 1, + CLM_CCA_S40 = 2, + CLM_CCA_S80 = 3, + CLM_FROM_DBG = 4, + CLM_TXON_CCA = 5, + CLM_CCA_S80_S40_S20 = 6, + CLM_CCA_S80_S40_S20_P20 = 7, + CLM_CCA_INIT +}; + +enum nhm_application { + NHM_INIT = 0, + NHM_BACKGROUND = 1, /*IEEE 11K for background*/ + NHM_ACS = 2, + NHM_DIG = 3, + NHM_TDMA_DIG = 4, + NHM_DBG_11K = 5, /*IEEE 11K for dbg cmd*/ + NHM_DBG_RSSI = 6, /*nhm_th[0]=rssi-20, th_ofst=3dB*/ + NHM_DBG_MANUAL = 7 /*nhm_th[0] & th_ofst is manual*/ +}; + +enum clm_application { + CLM_INIT = 0, + CLM_BACKGROUND = 1,/*default*/ + CLM_ACS = 2, + CLM_DIG = 3, + CLM_TDMA_DIG = 4, + CLM_DBG = 5 +}; + +enum ifs_clm_application { + IFS_CLM_INIT = 0, + IFS_CLM_BACKGROUND = 1,/*default*/ + IFS_CLM_ACS = 2, + IFS_CLM_DIG = 3, + IFS_CLM_TDMA_DIG = 4, + IFS_CLM_DBG = 5, + IFS_CLM_DBG_MANUAL = 6 +}; + +enum fahm_application { + FAHM_INIT = 0, + FAHM_BACKGROUND = 1, /*IEEE 11K for background*/ + FAHM_ACS = 2, + FAHM_DIG = 3, + FAHM_TDMA_DIG = 4, + FAHM_DBG_11K = 5, /*IEEE 11K for dbg cmd*/ + FAHM_DBG_RSSI = 6, /*fahm_th[0]=rssi-20, th_ofst=3dB*/ + FAHM_DBG_MANUAL = 7 /*fahm_th[0] & th_ofst is manual*/ +}; + +enum edcca_clm_application { + EDCCA_CLM_INIT = 0, + EDCCA_CLM_BACKGROUND = 1,/*default*/ + EDCCA_CLM_ACS = 2, + EDCCA_CLM_DIG = 3, + EDCCA_CLM_TDMA_DIG = 4, + EDCCA_CLM_DBG = 5 +}; + +/*--------------------------[Structure]-------------------------------------*/ +struct bb_info; + +struct env_trig_rpt { + u8 ccx_rpt_stamp; +}; + +struct env_mntr_rpt { + u8 ccx_rpt_stamp; + u8 ccx_rpt_result; + u8 clm_ratio; /*percent*/ + u16 clm_result; /*sample cnt*/ + u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/ + u8 nhm_ratio; /*percent*/ + u8 nhm_tx_ratio; /*percent*/ + u8 nhm_cca_ratio; /*percent*/ + u8 nhm_idle_ratio; /*percent*/ + u16 nhm_tx_cnt; /*sample cnt*/ + u16 nhm_cca_cnt; /*sample cnt*/ + u16 nhm_idle_cnt; /*sample cnt*/ + u8 nhm_pwr; /*dBm+110*/ + u8 ifs_clm_tx_ratio; /*percent*/ + u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/ + u8 ifs_clm_cck_fa_ratio; /*percent*/ + u8 ifs_clm_ofdm_fa_ratio; /*percent*/ + u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/ + u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/ + u16 ifs_clm_cck_fa_permil; /*permil*/ + u16 ifs_clm_ofdm_fa_permil; /*permil*/ + u16 ifs_clm_total_ifs; /*cnt*/ + u16 ifs_clm_his[IFS_CLM_NUM]; /*cnt*/ + u32 ifs_clm_ifs_avg[IFS_CLM_NUM]; /*us*/ + u32 ifs_clm_cca_avg[IFS_CLM_NUM]; /*us*/ + u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/ + u8 fahm_ratio; /*percent*/ + u8 fahm_denom_ratio; /*percent*/ + u8 fahm_pwr; /*dBm+110*/ + u8 edcca_clm_ratio; /*percent*/ +}; + +struct ccx_para_info { + enum halbb_racing_lv rac_lv; + u16 mntr_time; /*0~2097ms*/ + enum ccx_edcca_opt_sc_idx ccx_edcca_opt_sc_idx; + enum clm_application clm_app; + enum clm_opt_input clm_input_opt; + enum nhm_application nhm_app; + u8 nhm_manual_th_ofst; + u8 nhm_manual_th0; /*dbg manual mode*/ + enum nhm_option_cca_all nhm_incld_cca; /*Include CCA*/ + enum ifs_clm_application ifs_clm_app; + u32 ifs_clm_manual_th_times; + u32 ifs_clm_manual_th0;/*us*/ + enum fahm_application fahm_app; + u8 fahm_manual_th_ofst; + u8 fahm_manual_th0; /*dbg manual mode*/ + u8 fahm_numer_opt; + u8 fahm_denom_opt; + enum edcca_clm_application edcca_clm_app; +}; + +/*--------------------------[Prptotype]-------------------------------------*/ +void halbb_env_mntr_get_bg_result(struct bb_info *bb, + struct env_mntr_rpt *bg_rpt, + enum phl_phy_idx phy_idx); +void halbb_env_mntr_get_bg_setting(struct bb_info *bb, + struct ccx_para_info *bg_para, + enum phl_phy_idx phy_idx); +u8 halbb_env_mntr_trigger(struct bb_info *bb, struct ccx_para_info *para, + struct env_trig_rpt *trig_rpt); +u8 halbb_env_mntr_result(struct bb_info *bb, struct env_mntr_rpt *rpt); + +u8 halbb_env_mntr_get_802_11_k_rsni(struct bb_info *bb, s8 rcpi, s8 anpi); + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_ex.h b/phl/hal_g6/phy/bb/halbb_ex.h new file mode 100644 index 0000000..46dc4f4 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ex.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALBB_EX_H__ +#define __HALBB_EX_H__ +#include "halbb_ic_hw_info.h" + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +enum halbb_pause_type { + HALBB_PAUSE = 1, /*Pause & Set new value*/ + HALBB_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ + HALBB_RESUME = 3, + HALBB_RESUME_NO_RECOVERY = 4, +}; + +enum halbb_pause_lv_type { + HALBB_PAUSE_RELEASE = -1, + HALBB_PAUSE_LV_0 = 0, /* @Low Priority function */ + HALBB_PAUSE_LV_1 = 1, /* @Middle Priority function */ + HALBB_PAUSE_LV_2 = 2, /* @High priority function (ex: Check hang function) */ + HALBB_PAUSE_LV_3 = 3, /* @Debug function (the highest priority) */ + HALBB_PAUSE_MAX_NUM = 4 +}; + +enum halbb_pause_rpt { + PAUSE_FAIL = 0, + PAUSE_SUCCESS = 1 +}; + +/*---[BB Components]---*/ +enum habb_fun_t { + F_RA = 0, + F_FA_CNT = 1, + HALBB_FUN_RSVD_2 = 2, + F_DFS = 3, + F_EDCCA = 4, + F_ENV_MNTR = 5, + F_CFO_TRK = 6, + F_PWR_CTRL = 7, + F_RUA_TBL = 8, + F_AUTO_DBG = 9, + F_ANT_DIV = 10, + F_DIG = 11, + F_DCR = 31, + F_DEFAULT = 0xff +}; + +enum bb_watchdog_mode_t { + BB_WATCHDOG_NORMAL = 0, + BB_WATCHDOG_LOW_IO = 1, + BB_WATCHDOG_NON_IO = 2, +}; + +struct halbb_func_info { + char name[16]; + u8 id; +}; + +static const struct halbb_func_info halbb_func_i[] = { + {"ra", F_RA}, /*@do not move this element to other position*/ + {"fa_cnt", F_FA_CNT}, /*@do not move this element to other position*/ + {"rsvd2", HALBB_FUN_RSVD_2}, + {"dfs", F_DFS}, + {"edcca", F_EDCCA}, + {"env_mntr", F_ENV_MNTR}, + {"cfo_trk", F_CFO_TRK}, + {"pwr_ctrl", F_PWR_CTRL}, + {"rua_tbl", F_RUA_TBL}, + {"auto_dbg", F_AUTO_DBG}, + {"ant_div", F_ANT_DIV}, + {"dig", F_DIG}, +}; + +/*@=[HALBB supportability]=======================================*/ +enum habb_supportability_t { + BB_RA = BIT(F_RA), + BB_FA_CNT = BIT(F_FA_CNT), + BB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2), + BB_DFS = BIT(F_DFS), + BB_EDCCA = BIT(F_EDCCA), + BB_ENVMNTR = BIT(F_ENV_MNTR), + BB_CFO_TRK = BIT(F_CFO_TRK), + BB_PWR_CTRL = BIT(F_PWR_CTRL), + BB_RUA_TBL = BIT(F_RUA_TBL), + BB_AUTO_DBG = BIT(F_AUTO_DBG), + BB_ANT_DIV = BIT(F_ANT_DIV), + BB_DIG = BIT(F_DIG), + BB_DCR = BIT(F_DCR) +}; + +/*@=[HALBB Debug Component]=====================================*/ +enum halbb_dbg_comp_t { + /*=== [DM Part] ==========================*/ + DBG_RA = BIT(F_RA), + DBG_FA_CNT = BIT(F_FA_CNT), + DBG_HALBB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2), + DBG_DFS = BIT(F_DFS), + DBG_EDCCA = BIT(F_EDCCA), + DBG_ENV_MNTR = BIT(F_ENV_MNTR), + DBG_CFO_TRK = BIT(F_CFO_TRK), + DBG_PWR_CTRL = BIT(F_PWR_CTRL), + DBG_RUA_TBL = BIT(F_RUA_TBL), + DBG_AUTO_DBG = BIT(F_AUTO_DBG), + DBG_ANT_DIV = BIT(F_ANT_DIV), + DBG_DIG = BIT(F_DIG), + /*=== [Non-DM Part] ======================*/ + DBG_BIT12 = BIT(12), + DBG_BIT13 = BIT(13), + DBG_BIT14 = BIT(14), + DBG_BIT15 = BIT(15), + DBG_BIT16 = BIT(16), + DBG_BIT17 = BIT(17), + DBG_BIT18 = BIT(18), + DBG_BIT19 = BIT(19), + DBG_PHY_STS = BIT(20), + DBG_BIT21 = BIT(21), + DBG_FW_INFO = BIT(22), + DBG_COMMON_FLOW = BIT(23), + DBG_IC_API = BIT(24), + DBG_DBG_API = BIT(25), + DBG_DBCC = BIT(26), + DBG_DM_SUMMARY = BIT(27), + DBG_PHY_CONFIG = BIT(28), + DBG_INIT = BIT(29), + DBG_CMN = BIT(30), + DBG_DCR = BIT(F_DCR) +}; +/*@--------------------------[Structure]-------------------------------------*/ + +#if 0 +/*For development use only, and will move to "struct rtw_rssi_info" in near furture*/ +struct bb_rssi_info{ + u8 rssi; /*avg RSSI among all RF path, dbm = RSSI - 110*/ + u16 rssi_acc; /*U(16,4) version of rssi*/ + u8 rssi_cck; /*instance value of CCK RSSI*/ + u8 rssi_ofdm; /*instance value of OFDM RSSI*/ +}; +#endif + +struct bb_sta_info { + u8 sta_status_tmp; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ + +struct bb_info; +bool halbb_sta_info_init(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info); +bool halbb_sta_info_deinit(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info); +bool halbb_sta_info_add_entry(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_info); +bool halbb_sta_info_delete_entry(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info); +void halbb_media_status_update(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_info, + bool is_connected); +void halbb_watchdog_reset(struct bb_info *bb); +void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode, + enum phl_phy_idx phy_idx); +void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx); +u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func, + enum halbb_pause_type pause_type, + enum halbb_pause_lv_type lv, + u8 val_lehgth, + u32 *val_buf); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_export_fun.h b/phl/hal_g6/phy/bb/halbb_export_fun.h new file mode 100644 index 0000000..02476d1 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_export_fun.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_EXPORT_FUN_H__ +#define __HALBB_EXPORT_FUN_H__ +#include "halbb_cfg_ic.h" +#include "halbb_hw_cfg_ex.h" +#include "halbb_init_ex.h" +#include "halbb_ex.h" +#include "halbb_dbg_cmd_ex.h" +#include "halbb_physts_ex.h" +#include "halbb_api_ex.h" +#include "halbb_interface_ex.h" +#include "halbb_dfs_ex.h" +#include "halbb_dig_ex.h" +#include "halbb_mp_ex.h" +#include "halbb_plcp_tx_ex.h" +#include "halbb_pmac_setting_ex.h" +#include "halbb_la_mode_ex.h" +#include "halbb_ra_ex.h" +#include "halbb_cmn_rpt_ex.h" +#include "halbb_ch_info_ex.h" +#include "halbb_math_lib_ex.h" +#include "halbb_edcca_ex.h" +#include "halbb_dbcc_ex.h" +#include "halbb_rua_tbl_ex.h" +#include "halbb_env_mntr_ex.h" +#include "halbb_pwr_ctrl_ex.h" +#include "halbb_dyn_csi_rsp_ex.h" +#ifdef BB_8852A_CAV_SUPPORT + #include "halbb_8852a/halbb_8852a_api_ex.h" +#endif +#ifdef BB_8852A_2_SUPPORT + #include "halbb_8852a_2/halbb_8852a_2_api_ex.h" +#endif +#ifdef BB_8852B_SUPPORT + #include "halbb_8852b/halbb_8852b_api_ex.h" +#endif +#ifdef BB_8852C_SUPPORT + #include "halbb_8852c/halbb_8852c_api_ex.h" +#endif +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_features.h b/phl/hal_g6/phy/bb/halbb_features.h new file mode 100644 index 0000000..a3dd4d3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_features.h @@ -0,0 +1,122 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALBB_FEATURES_H__ +#define __HALBB_FEATURES_H__ + +#include "../../hal_headers_le.h" +#include "halbb_cfg_ic.h" +#include "halbb_ic_hw_info.h" + +/*[Control by Outer Driver]--------------------------------------------------*/ +#ifndef DRV_BB_TIMER_SUPPORT_DISABLE + #define HALBB_TIMER_SUPPORT +#endif + +#ifndef DRV_BB_DBG_TRACE_DISABLE + #define HALBB_DBG_TRACE_SUPPORT +#endif + +#ifndef DRV_BB_PHYSTS_PARSING_DISABLE + #define HALBB_PHYSTS_PARSING_SUPPORT +#endif +#ifndef DRV_BB_ENV_MNTR_DISABLE + #define HALBB_ENV_MNTR_SUPPORT + #define CLM_SUPPORT + #define NHM_SUPPORT + #define IFS_CLM_SUPPORT + #define FAHM_SUPPORT + #define EDCCA_CLM_SUPPORT +#endif +#ifndef DRV_BB_STATISTICS_DISABLE + #define HALBB_STATISTICS_SUPPORT +#endif +#ifndef DRV_BB_RA_DISABLE + #define HALBB_RA_SUPPORT +#endif +#ifndef DRV_BB_ADPTVTY_DISABLE + #define HALBB_EDCCA_SUPPORT +#endif +#ifndef DRV_BB_DFS_DISABLE + #define HALBB_DFS_SUPPORT +#endif +#ifndef DRV_BB_CFO_TRK_DISABLE + #define HALBB_CFO_TRK_SUPPORT + //#define BB_DYN_CFO_TRK_LOP +#endif +#ifndef DRV_BB_DIG_DISABLE + #define HALBB_DIG_SUPPORT + #ifndef DRV_BB_TDMADIG_DISABLE + #define HALBB_DIG_TDMA_SUPPORT + #endif + #ifndef DRV_BB_DIG_MCC_DISABLE + #define HALBB_DIG_MCC_SUPPORT + #define HALBB_DIG_MCC_SUPPORT_IC (BB_RTL8852A | BB_RTL8852B) + #endif + #define HALBB_DIG_DAMPING_CHK +#endif +#ifndef DRV_BB_LA_MODE_DISABLE + #define HALBB_LA_MODE_SUPPORT +#endif +#ifndef DRV_BB_PSD_DISABLE + #define HALBB_PSD_SUPPORT +#endif +#ifndef DRV_BB_PWR_CTRL_DISABLE + #define HALBB_PWR_CTRL_SUPPORT +#endif +#ifndef DRV_BB_RUA_DISABLE + #define HALBB_RUA_SUPPORT +#endif +#ifndef DRV_BB_PMAC_TX_DISABLE + #define HALBB_PMAC_TX_SUPPORT +#endif +#ifndef DRV_BB_CH_INFO_DISABLE + #define HALBB_CH_INFO_SUPPORT + #ifndef DRV_BB_DYN_CSI_RSP_DISABLE + #define HALBB_DYN_CSI_RSP_SUPPORT + #endif +#endif +#ifndef DRV_BB_AUTO_DBG_DISABLE + #define HALBB_AUTO_DBG_SUPPORT +#endif +#if 0 + #define HALBB_ANT_DIV_SUPPORT +#endif +#ifndef DRV_BB_DYN_L2H_DISABLE + #define HALBB_DYN_L2H_SUPPORT +#endif +/*[DBCC]*/ +#if (defined(CONFIG_DBCC_SUPPORT) && defined(HALBB_COMPILE_IC_DBCC)) + #define HALBB_DBCC_SUPPORT + #define HALBB_DBCC_DVLP_FLAG +#endif +/*[FW OFFLOAD]*/ +#if (defined(CONFIG_FW_IO_OFLD_SUPPORT) && defined(HALBB_COMPILE_IC_FWOFLD)) +#define HALBB_FW_OFLD_SUPPORT +#endif + +#define HALBB_TDMA_CR_SUPPORT + +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_fwofld.c b/phl/hal_g6/phy/bb/halbb_fwofld.c new file mode 100644 index 0000000..86bf9f3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_fwofld.c @@ -0,0 +1,926 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_FW_OFLD_SUPPORT +bool halbb_check_fw_ofld(struct bb_info *bb) +{ + bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0; + + BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret); + return ret; +} + +bool halbb_fw_delay(struct bb_info *bb, u32 val) +{ +/* halbb_set_reg */ + struct rtw_mac_cmd cmd; + u32 ret; + + cmd.type = RTW_MAC_DELAY_OFLD; + cmd.lc = 0; + cmd.value = val; /*delay us*/ + ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); + BB_DBG(bb, DBG_FW_INFO, "FW ofld delay:%x\n", val); + if (ret) { + BB_WARNING("IO offload fail: %d\n", ret); + return false; + } + else { + return true; + } +} + +bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) +{ +/* halbb_set_reg */ + struct rtw_mac_cmd cmd; + u32 ret; + + cmd.src = RTW_MAC_BB_CMD_OFLD; + cmd.type = RTW_MAC_WRITE_OFLD; + cmd.lc = lc; + cmd.offset = (u16)addr; + cmd.value = val; + cmd.mask = mask; + ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); + BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask); + if (ret) { + BB_WARNING("IO offload fail: %d\n", ret); + return false; + } + else { + return true; + } + +} + +bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, + u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc) +{ + bool ret = true; + u32 val_mod = val; + + #ifdef HALBB_DBCC_SUPPORT + if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) + addr += halbb_phy0_to_phy1_ofst(bb, addr); + #endif + + ret = halbb_fw_set_reg(bb, addr, mask, val_mod, lc); + return ret; +} + +bool halbb_fwcfg_bb_phy_8852a_2(struct bb_info *bb, u32 addr, u32 data, + enum phl_phy_idx phy_idx) +{ +#ifdef HALBB_DBCC_SUPPORT + u32 ofst = 0; +#endif + bool ret = true; + + if (addr == 0xfe) { + halbb_delay_ms(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 ms\n"); + } else if (addr == 0xfd) { + halbb_delay_ms(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 ms\n"); + } else if (addr == 0xfc) { + halbb_delay_ms(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 ms\n"); + } else if (addr == 0xfb) { + halbb_delay_us(bb, 50); + BB_DBG(bb, DBG_INIT, "Delay 50 us\n"); + } else if (addr == 0xfa) { + halbb_delay_us(bb, 5); + BB_DBG(bb, DBG_INIT, "Delay 5 us\n"); + } else if (addr == 0xf9) { + halbb_delay_us(bb, 1); + BB_DBG(bb, DBG_INIT, "Delay 1 us\n"); + } else { + #ifdef HALBB_DBCC_SUPPORT + if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) && + phy_idx == HW_PHY_1) { + ofst = halbb_phy0_to_phy1_ofst(bb, addr); + if (ofst == 0) + return true; + addr += ofst; + } else { + phy_idx = HW_PHY_0; + } + #endif + + /*FWOFLD in init BB reg flow */ + if (halbb_check_fw_ofld(bb)) { + ret &= halbb_fw_set_reg(bb, addr, MASKDWORD, data, 0); + BB_DBG(bb, DBG_INIT, "[REG FWOFLD]0x%04X = 0x%08X, ret = %d\n", addr, data, (u8)ret); + } + else { + halbb_set_reg(bb, addr, MASKDWORD, data); + #ifdef HALBB_DBCC_SUPPORT + BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); + #else + BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data); + #endif + } + + } + return ret; +} + +bool halbb_fwofld_cck_en_8852a_2(struct bb_info *bb, bool cck_en, + enum phl_phy_idx phy_idx) +{ + bool ret = true; + + if (cck_en) { + ret &= halbb_fw_set_reg(bb, 0x2344, BIT(31), 0, 0); + } else { + ret &= halbb_fw_set_reg(bb, 0x2344, BIT(31), 1, 0); + } + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx); + return ret; +} + +bool halbb_fwofld_btg_8852a_2(struct bb_info *bb, bool btg) +{ + struct rtw_phl_com_t *phl = bb->phl_com; + struct dev_cap_t *dev = &phl->dev_cap; + bool ret = true; + + if (dev->rfe_type >= 50) + return true; + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + if (btg) { + // Path A + ret &= halbb_fw_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x1, 0); + // Path B + ret &= halbb_fw_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x3, 0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n"); + // Apply Grant BT by TMAC Setting + ret &= halbb_fw_set_reg(bb, 0x980, 0x1e0000, 0x0, 0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n"); + // Add BT share + ret &= halbb_fw_set_reg(bb, 0x4978, BIT(14), 0x1, 0); + ret &= halbb_fw_set_reg(bb, 0x4974, 0x3c00000, 0x2, 0); + ret &= halbb_fw_set_reg(bb, 0x441c, BIT(31), 0x1, 0); + } else { + // Path A + ret &= halbb_fw_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x0, 0); + // Path B + ret &= halbb_fw_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x0, 0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n"); + // Ignore Grant BT by PMAC Setting + ret &= halbb_fw_set_reg(bb, 0x980, 0x1e0000, 0xf, 0); + ret &= halbb_fw_set_reg(bb, 0x980, 0x3c000000, 0x4, 0); + BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n"); + // Reset BT share + ret &= halbb_fw_set_reg(bb, 0x4978, BIT(14), 0x0, 0); + ret &= halbb_fw_set_reg(bb, 0x4974, 0x3c00000, 0x0, 0); + ret &= halbb_fw_set_reg(bb, 0x441c, BIT(31), 0x0, 0); + } + return ret; +} + +bool halbb_fw_5m_mask_8852a_2(struct bb_info *bb, u8 pri_ch, enum channel_width bw) +{ + bool mask_5m_low = false; + bool mask_5m_en = false; + bool ret = true; + + switch (bw) { + case CHANNEL_WIDTH_40: + /* Prich=1 : Mask 5M High + Prich=2 : Mask 5M Low */ + mask_5m_en = true; + mask_5m_low = pri_ch == 2 ? true : false; + break; + case CHANNEL_WIDTH_80: + /* Prich=3 : Mask 5M High + Prich=4 : Mask 5M Low + Else : Mask 5M Disable */ + mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)) ? true : false; + mask_5m_low = pri_ch == 4 ? true : false; + break; + default: + mask_5m_en = false; + break; + } + + BB_DBG(bb, DBG_PHY_CONFIG, "[5M Mask] pri_ch = %d, bw = %d", pri_ch, bw); + + if (!mask_5m_en) { + ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12), 0x0, 0); + ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12), 0x0, 0); + } else { + if (mask_5m_low) { + ret &= halbb_fw_set_reg(bb, 0x46b0, 0x3f, 0x4, 0); + ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12) | BIT(8) | BIT(6), 0x5, 0); + ret &= halbb_fw_set_reg(bb, 0x4784, 0x3f, 0x4, 0); + ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12) | BIT(8) | BIT(6), 0x5, 0); + } else { + ret &= halbb_fw_set_reg(bb, 0x46b0, 0x3f, 0x4, 0); + ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12) | BIT(8) | BIT(6), 0x6, 0); + ret &= halbb_fw_set_reg(bb, 0x4784, 0x3f, 0x4, 0); + ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12) | BIT(8) | BIT(6), 0x6, 0); + } + } + return ret; +} + +bool halbb_fw_set_rf_reg_8852a_2(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data, u8 lc) +{ +/* halbb_write_rf_reg_8852a_2 */ + bool ret = true; + u32 direct_addr = 0; + u32 offset_write_rf[2] = {0xc000, 0xd000}; + + /*==== Error handling ====*/ + if (path > RF_PATH_B) { + BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path); + return false; + } + + /*==== Calculate offset ====*/ + reg_addr &= 0xff; + direct_addr = offset_write_rf[path] + (reg_addr << 2); + + /*==== RF register only has 20bits ====*/ + bit_mask &= RFREGOFFSETMASK; + halbb_fw_delay(bb, 1); + /*==== Write RF register directly ====*/ + ret = halbb_fw_set_reg(bb, direct_addr, bit_mask, data, lc); + + /*halbb_delay_us(bb, 1);*/ + halbb_fw_delay(bb, 1); + + BB_DBG(bb, DBG_FW_INFO, "FW OFLD RF-%d 0x%x = 0x%x , bit mask = 0x%x, ret = %d\n", + path, reg_addr, data, bit_mask, (u8)ret); + + return ret; +} +bool halbb_fw_set_efuse_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path, enum phl_phy_idx phy_idx) +{ + u8 band; + bool ret = true; + u8 upper_bound = 60; // S(7,4): 3.75 + u8 lower_bound = 64; // S(7,4): -4 + s32 hidden_efuse = 0, normal_efuse = 0, normal_efuse_cck = 0; + s32 tmp = 0; + u32 efuse_5g[BB_PATH_MAX_8852A] = {0x4624, 0x46f8}; + u32 efuse_5g_mask = 0x07e00000; + u32 efuse_2g[BB_PATH_MAX_8852A] = {0x4628, 0x46fc}; + u32 efuse_2g_mask = 0x0000003f; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // 2G Band: (0) + // 5G Band: (1):Low, (2): Mid, (3):High + if (central_ch >= 0 && central_ch <= 14) + band = 0; + else if (central_ch >= 36 && central_ch <= 64) + band = 1; + else if (central_ch >= 100 && central_ch <= 144) + band = 2; + else if (central_ch >= 149 && central_ch <= 177) + band = 3; + else + band = 0; + + // === [Set hidden efuse] === // + if (bb->bb_efuse_i.hidden_efuse_check) { + for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) { + if (central_ch >= 0 && central_ch <= 14) { + hidden_efuse = (bb->bb_efuse_i.gain_cg[path][band] << 2); + ret &= halbb_fw_set_reg(bb, efuse_2g[path], efuse_2g_mask, (hidden_efuse & 0x3f), 0); + } else { + hidden_efuse = (bb->bb_efuse_i.gain_cg[path][band] << 2); + ret &= halbb_fw_set_reg(bb, efuse_5g[path], efuse_5g_mask, (hidden_efuse & 0x3f), 0); + } + } + BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Hidden efuse dynamic setting!!\n"); + } else { + BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Values of hidden efuse are all 0xff, bypass dynamic setting!!\n"); + } + + // === [Set normal efuse] === // + if (bb->bb_efuse_i.normal_efuse_check) { + if ((bb->rx_path == RF_PATH_A) || (bb->rx_path == RF_PATH_AB)) { + normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_A][band + 1]; + normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_A][0]; + } else if (bb->rx_path == RF_PATH_B) { + normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_B][band + 1]; + normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_B][0]; + } + normal_efuse *= (-1); + normal_efuse_cck *= (-1); + + // OFDM normal efuse + if (normal_efuse > 3) { + tmp = (normal_efuse << 4) + (bb->bb_efuse_i.efuse_ofst << 2) - upper_bound; + ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (tmp & 0x7f), phy_idx, 0); + // Set efuse + ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, (upper_bound & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, (upper_bound & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, (upper_bound & 0x7f), phy_idx, 0); + } else if (normal_efuse < -4) { + tmp = (normal_efuse << 4) + (bb->bb_efuse_i.efuse_ofst << 2) + lower_bound; + // r_1_rpl_bias_comp + ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0); + // r_tb_rssi_bias_comp + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (tmp & 0x7f), phy_idx, 0); + // Set efuse + ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, (lower_bound & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, (lower_bound & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, (lower_bound & 0x7f), phy_idx, 0); + } else { + ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, (bb->bb_efuse_i.efuse_ofst & 0x1f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (bb->bb_efuse_i.efuse_ofst_tb & 0x7f), phy_idx, 0); + // Set efuse + ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, ((normal_efuse << 4) & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, ((normal_efuse << 4) & 0x7f), phy_idx, 0); + ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, ((normal_efuse << 4) & 0x7f), phy_idx, 0); + } + + // CCK normal efuse + if (band == 0) { + tmp = normal_efuse_cck << 3; + ret &= halbb_fw_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f), 0); + } + + BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Normal efuse dynamic setting!!\n"); + } else { + BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Values of normal efuse are all 0xff, bypass dynamic setting!!\n"); + } + return ret; +} +bool halbb_fw_set_gain_error_8852a_2(struct bb_info *bb, u8 central_ch) +{ + bool ret = true; + u8 band; + u8 path = 0, lna_idx = 0, tia_idx = 0; + s32 tmp = 0; + u32 lna_err_a_5g[BB_PATH_MAX_8852A][7] = {{0x462c, 0x462c, 0x4630, + 0x4634, 0x4634, 0x4638, + 0x4638}, {0x4700, 0x4700, + 0x4704, 0x4708, 0x4708, + 0x470c, 0x470c}}; + u32 lna_err_a_5g_mask[7] = {0x00000fc0, 0x3f000000, 0x0003f000, + 0x0000003f, 0x00fc0000, 0x00000fc0, + 0x3f000000}; + u32 lna_err_a_2g[BB_PATH_MAX_8852A][7] = {{0x462c, 0x4630, 0x4630, + 0x4634, 0x4634, 0x4638, + 0x463c}, {0x4700, 0x4704, + 0x4704, 0x4708, 0x4708, + 0x470c, 0x4710}}; + u32 lna_err_a_2g_mask[7] = {0x0003f000, 0x0000003f, 0x00fc0000, + 0x00000fc0, 0x3f000000, 0x0003f000, + 0x0000003f}; + u32 tia_err_a_5g[BB_PATH_MAX_8852A][2] = {{0x4640, 0x4644}, {0x4714, + 0x4718}}; + u32 tia_err_a_5g_mask[2] = {0x0003f000, 0x0000003f}; + u32 tia_err_a_2g[BB_PATH_MAX_8852A][2] = {{0x4640, 0x4644}, {0x4714, + 0x4718}}; + u32 tia_err_a_2g_mask[2] = {0x00fc0000, 0x00000fc0}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // 2G Band: (0) + // 5G Band: (1):Low, (2): Mid, (3):High + if (central_ch >= 0 && central_ch <= 14) + band = 0; + else if (central_ch >= 36 && central_ch <= 64) + band = 1; + else if (central_ch >= 100 && central_ch <= 144) + band = 2; + else if (central_ch >= 149 && central_ch <= 177) + band = 3; + else + band = 0; + + if (central_ch >= 0 && central_ch <= 14) { + for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) { + // Set 2G LNA Gain Err + for (lna_idx = 0; lna_idx < 7; lna_idx++) { + tmp = bb->bb_gain_i.lna_gain[band][path][lna_idx]; + + ret &= halbb_fw_set_reg(bb, lna_err_a_2g[path][lna_idx], + lna_err_a_2g_mask[lna_idx], (tmp & 0x3f), 0); + + } + // Set 2G TIA Gain Err + for (tia_idx = 0; tia_idx < 2; tia_idx++) { + tmp = bb->bb_gain_i.tia_gain[band][path][tia_idx]; + ret &= halbb_fw_set_reg(bb, tia_err_a_2g[path][tia_idx], + tia_err_a_2g_mask[tia_idx], (tmp & 0x3f), 0); + } + } + } else { + for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) { + // Set 5G LNA Gain Err + for (lna_idx = 0; lna_idx < 7; lna_idx++) { + tmp = bb->bb_gain_i.lna_gain[band][path][lna_idx]; + + ret &= halbb_fw_set_reg(bb, lna_err_a_5g[path][lna_idx], + lna_err_a_5g_mask[lna_idx], (tmp & 0x3f), 0); + } + // Set 5G TIA Gain Err + for (tia_idx = 0; tia_idx < 2; tia_idx++) { + tmp = bb->bb_gain_i.tia_gain[band][path][tia_idx]; + ret &= halbb_fw_set_reg(bb, tia_err_a_5g[path][tia_idx], + tia_err_a_5g_mask[tia_idx], (tmp & 0x3f), 0); + } + } + } + return ret; +} +bool halbb_fwofld_sco_cck_8852a_2(struct bb_info *bb, u8 pri_ch) +{ + u32 sco_barker_threshold[14] = {0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, + 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, + 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, + 0x1db75, 0x1ddc4}; + u32 sco_cck_threshold[14] = {0x27de3, 0x27f35, 0x28088, 0x281da, + 0x2832d, 0x2847f, 0x285d2, 0x28724, + 0x28877, 0x289c9, 0x28b1c, 0x28c6e, + 0x28dc1, 0x290ed}; + bool rpt = true; + + if (pri_ch > 14) { + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Fail]"); + /*Return true because its not FW offload fail*/ + return true; + } + + rpt &= halbb_fw_set_reg(bb, 0x23b0, 0x7ffff, sco_barker_threshold[pri_ch - 1], 0); + rpt &= halbb_fw_set_reg(bb, 0x23b4, 0x7ffff, sco_cck_threshold[pri_ch - 1], 0); + BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Success]"); + return rpt; +} + +bool halbb_fwofld_rf_ch_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path, + bool *is_2g_ch, u32 *rf_reg18) +{ + //u32 rf_reg18 = 0; + bool ret = true; + + /*rf_reg18 = halbb_read_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK);*/ + /*==== [Error handling] ====*/ + if (*rf_reg18 == INVALID_RF_DATA) { + BB_WARNING("Invalid RF_0x18 for Path-%d\n", path); + return false; + } + *is_2g_ch = (central_ch <= 14) ? true : false; + /*==== [Set RF Reg 0x18] ====*/ + *rf_reg18 &= ~0x303ff; /*[17:16],[9:8],[7:0]*/ + *rf_reg18 |= central_ch; /* Channel*/ + /*==== [5G Setting] ====*/ + if (!*is_2g_ch) + *rf_reg18 |= (BIT(16) | BIT(8)); + /*ret &= halbb_fw_set_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK, *rf_reg18);*/ + + BB_DBG(bb, DBG_PHY_CONFIG, "[Success][ch_setting] CH: %d for Path-%d\n", + central_ch, path); + return ret; +} + +bool halbb_fwofld_ch_8852a_2(struct bb_info *bb, u8 central_ch, + enum phl_phy_idx phy_idx, u32 *path0_rf18, u32 *path1_rf18) +{ + u8 sco_comp; + bool is_2g_ch = false; + bool ret = true; + + if (bb->is_disable_phy_api) { + BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__); + return true; + } + /*==== Error handling ====*/ + if ((central_ch > 14 && central_ch < 36) || + (central_ch > 64 && central_ch < 100) || + (central_ch > 144 && central_ch < 149) || + central_ch > 177 ) { + BB_WARNING("Invalid CH:%d for PHY%d\n", central_ch, + phy_idx); + return false; + } + + if (phy_idx == HW_PHY_0) { + /*============== [Path A] ==============*/ + ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_A, &is_2g_ch, path0_rf18); + //------------- [Mode Sel - Path A] ------------// + if (is_2g_ch) + ret &= halbb_fw_set_reg_cmn(bb, 0x4644, BIT(31) | BIT(30), 1, + phy_idx, 0); + else + ret &= halbb_fw_set_reg_cmn(bb, 0x4644, BIT(31) | BIT(30), 0, + phy_idx, 0); + + /*============== [Path B] ==============*/ + if (!bb->hal_com->dbcc_en) { + ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_B, + &is_2g_ch, path1_rf18); + //------------- [Mode Sel - Path B] ------------// + if (is_2g_ch) + ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), + 1, phy_idx, 0); + else + ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), + 0, phy_idx, 0); + } else { /*==== [Phy0 config at 2/5G] ====*/ + if (is_2g_ch) + ret &= halbb_fw_set_reg(bb, 0x4970, BIT(1), 0, 0); + else + ret &= halbb_fw_set_reg(bb, 0x4970, BIT(1), 1, 0); + } + /*==== [SCO compensate fc setting] ====*/ + sco_comp = halbb_sco_mapping_8852a_2(bb, central_ch); + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0x7f, sco_comp, phy_idx, 0); + } else { + /*============== [Path B] ==============*/ + ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_B, &is_2g_ch, path0_rf18); + + //------------- [Mode Sel - Path B] ------------// + if (is_2g_ch) + ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), 1, + phy_idx, 0); + else + ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), 0, + phy_idx, 0); + + /*==== [SCO compensate fc setting] ====*/ + sco_comp = halbb_sco_mapping_8852a_2(bb, central_ch); + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0x7f, sco_comp, phy_idx, 0); + } + + /* === Bandedge ===*/ + if (is_2g_ch) + ret &= halbb_fw_set_reg_cmn(bb, 0x4498, BIT(30), 1, phy_idx, 0); + else + ret &= halbb_fw_set_reg_cmn(bb, 0x4498, BIT(30), 0, phy_idx, 0); + /* === CCK Parameters === */ + if (central_ch == 14) { + ret &= halbb_fw_set_reg(bb, 0x2300, 0xffffff, 0x3b13ff, 0); + ret &= halbb_fw_set_reg(bb, 0x2304, 0xffffff, 0x1c42de, 0); + ret &= halbb_fw_set_reg(bb, 0x2308, 0xffffff, 0xfdb0ad, 0); + ret &= halbb_fw_set_reg(bb, 0x230c, 0xffffff, 0xf60f6e, 0); + ret &= halbb_fw_set_reg(bb, 0x2310, 0xffffff, 0xfd8f92, 0); + ret &= halbb_fw_set_reg(bb, 0x2314, 0xffffff, 0x2d011, 0); + ret &= halbb_fw_set_reg(bb, 0x2318, 0xffffff, 0x1c02c, 0); + ret &= halbb_fw_set_reg(bb, 0x231c, 0xffffff, 0xfff00a, 0); + } else { + ret &= halbb_fw_set_reg(bb, 0x2300, 0xffffff, 0x3d23ff, 0); + ret &= halbb_fw_set_reg(bb, 0x2304, 0xffffff, 0x29b354, 0); + ret &= halbb_fw_set_reg(bb, 0x2308, 0xffffff, 0xfc1c8, 0); + ret &= halbb_fw_set_reg(bb, 0x230c, 0xffffff, 0xfdb053, 0); + ret &= halbb_fw_set_reg(bb, 0x2310, 0xffffff, 0xf86f9a, 0); + ret &= halbb_fw_set_reg(bb, 0x2314, 0xffffff, 0xfaef92, 0); + ret &= halbb_fw_set_reg(bb, 0x2318, 0xffffff, 0xfe5fcc, 0); + ret &= halbb_fw_set_reg(bb, 0x231c, 0xffffff, 0xffdff5, 0); + } + /* === Set Gain Error === */ + ret &= halbb_fw_set_gain_error_8852a_2(bb, central_ch); + /* === Set Efuse === */ + ret &= halbb_fw_set_efuse_8852a_2(bb, central_ch, bb->rx_path, phy_idx); + + /* === Set Ch idx report in phy-sts === */ + /* write for last cmd*/ + ret &= halbb_fw_set_reg_cmn(bb, 0x0734, 0x0ff0000, central_ch, phy_idx, 0); + + BB_DBG(bb, DBG_PHY_CONFIG, "[Switch CH] CH: %d for PHY%d, ret = %d\n", + central_ch, phy_idx, (u8)ret); + return ret; +} + +bool halbb_fw_bw_setting_8852a_2(struct bb_info *bb, enum channel_width bw, + enum rf_path path, u32 *rf_reg18) +{ + bool ret = true; + /*u32 rf_reg18 = 0;*/ + u32 adc_sel[2] = {0x12d0, 0x32d0}; + u32 wbadc_sel[2] = {0x12ec, 0x32ec}; + + /*rf_reg18 = halbb_read_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK);*/ + /*==== [Error handling] ====*/ + if (*rf_reg18 == INVALID_RF_DATA) { + BB_WARNING("Invalid RF_0x18 for Path-%d\n", path); + return false; + } + *rf_reg18 &= ~(BIT(11) | BIT(10)); + /*==== [Switch bandwidth] ====*/ + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + if (bw == CHANNEL_WIDTH_5) { + /*ADC clock = 20M & WB ADC clock = 40M for BW5 */ + ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x1, 0); + ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x0, 0); + } else if (bw == CHANNEL_WIDTH_10) { + /*ADC clock = 40M & WB ADC clock = 80M for BW10 */ + ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x2, 0); + ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x1, 0); + } else if (bw == CHANNEL_WIDTH_20) { + /*ADC clock = 80M & WB ADC clock = 160M for BW20 */ + ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0); + ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0); + } + + /*RF bandwidth */ + *rf_reg18 |= (BIT(11) | BIT(10)); + + break; + case CHANNEL_WIDTH_40: + /*ADC clock = 80M & WB ADC clock = 160M for BW40 */ + ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0); + ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0); + + /*RF bandwidth */ + *rf_reg18 |= BIT(11); + + break; + case CHANNEL_WIDTH_80: + /*ADC clock = 160M & WB ADC clock = 160M for BW40 */ + ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0); + ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0); + + /*RF bandwidth */ + *rf_reg18 |= BIT(10); + + break; + default: + BB_WARNING("Fail to set ADC\n"); + } + + /*==== [Write RF register] ====*/ + /*ret &= halbb_fw_set_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK, rf_reg18);*/ + BB_DBG(bb, DBG_PHY_CONFIG, + "[bw_setting] ADC setting for Path-%d\n, ret = %d", path, (u8)ret); + return ret; +} + +bool halbb_fwofld_bw_8852a_2(struct bb_info *bb, u8 pri_ch, enum channel_width bw, + enum phl_phy_idx phy_idx, u32 *path0_rf18, u32 *path1_rf18) +{ + bool ret = true; + + if (bb->is_disable_phy_api) { + BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__); + return true; + } + + /*==== Error handling ====*/ + if (bw >= CHANNEL_WIDTH_MAX || (bw == CHANNEL_WIDTH_40 && pri_ch > 2) || + (bw == CHANNEL_WIDTH_80 && pri_ch > 4)) { + BB_WARNING("Fail to switch bw(bw:%d, pri ch:%d)\n", bw, + pri_ch); + return true; + } + + /*==== Switch bandwidth ====*/ + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + if (bw == CHANNEL_WIDTH_5) { + /*RF_BW:[31:30]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0, + phy_idx, 0); + /*small BW:[13:12]=0x1 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x1, phy_idx, 0); + /*Pri ch:[11:8]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0); + } else if (bw == CHANNEL_WIDTH_10) { + /*RF_BW:[31:30]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0, + phy_idx, 0); + /*small BW:[13:12]=0x2 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x2, phy_idx, 0); + /*Pri ch:[11:8]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0); + } else if (bw == CHANNEL_WIDTH_20) { + /*RF_BW:[31:30]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0, + phy_idx, 0); + /*small BW:[13:12]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0); + /*Pri ch:[11:8]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0); + } + + break; + case CHANNEL_WIDTH_40: + /*RF_BW:[31:30]=0x1 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x1, phy_idx, 0); + /*small BW:[13:12]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0); + /*Pri ch:[11:8] */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, pri_ch, phy_idx, 0); + /*CCK primary channel */ + if (pri_ch == 1) + ret &= halbb_fw_set_reg(bb, 0x237c, BIT(0), 1, 0); + else + ret &= halbb_fw_set_reg(bb, 0x237c, BIT(0), 0, 0); + + break; + case CHANNEL_WIDTH_80: + /*RF_BW:[31:30]=0x2 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x2, phy_idx, 0); + /*small BW:[13:12]=0x0 */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0); + /*Pri ch:[11:8] */ + ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, pri_ch, phy_idx, 0); + + break; + default: + BB_WARNING("Fail to switch bw (bw:%d, pri ch:%d)\n", bw, + pri_ch); + } + + if (phy_idx == HW_PHY_0) { + /*============== [Path A] ==============*/ + ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_A, path0_rf18); + /*============== [Path B] ==============*/ + if (!bb->hal_com->dbcc_en) + ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_B, path1_rf18); + } else { + /*============== [Path B] ==============*/ + ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_B, path1_rf18); + } + + BB_DBG(bb, DBG_PHY_CONFIG, + "[Switch BW] BW: %d for PHY%d\n, ret = %d", bw, phy_idx, (u8)ret); + + return ret; +} + +bool halbb_fwofld_bw_ch_8852a_2(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width bw, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + bool cck_en = false; + bool is_2g_ch = false; + u8 pri_ch_idx = 0; + u32 path0_rf18 = 0; + u32 path1_rf18 = 0; + + /*==== [Set pri_ch idx] ====*/ + if (central_ch <= 14) { + // === 2G === // + switch (bw) { + case CHANNEL_WIDTH_20: + break; + + case CHANNEL_WIDTH_40: + pri_ch_idx = pri_ch > central_ch ? 1 : 2; + break; + + default: + break; + } + + /*==== [CCK SCO Compesate] ====*/ + rpt &= halbb_fwofld_sco_cck_8852a_2(bb, pri_ch); + + cck_en = true; + is_2g_ch = true; + } else { + // === 5G === // + switch (bw) { + case CHANNEL_WIDTH_20: + break; + + case CHANNEL_WIDTH_40: + case CHANNEL_WIDTH_80: + if (pri_ch > central_ch) + pri_ch_idx = (pri_ch - central_ch) >> 1; + else + pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1; + break; + + default: + break; + } + cck_en = false; + is_2g_ch = false; + } + if (!bb->hal_com->dbcc_en) { + /*============== [Path A] ==============*/ + path0_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK); + /*============== [Path B] ==============*/ + path1_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK); + } else { + if (phy_idx == HW_PHY_0) { + /*============== [Path A] ==============*/ + path0_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK); + } + else { + /*============== [Path B] ==============*/ + path1_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK); + } + } + /*BB_WARNING("RF a/b = %x , %x", path0_rf18, path1_rf18);*/ + /*==== [Switch BW] ====*/ + rpt &= halbb_fwofld_bw_8852a_2(bb, pri_ch_idx, bw, phy_idx, &path0_rf18, &path1_rf18); + /*BB_WARNING("SwBW : RF a/b = %x , %x", path0_rf18, path1_rf18);*/ + /*==== [Switch CH] ====*/ + rpt &= halbb_fwofld_ch_8852a_2(bb, central_ch, phy_idx, &path0_rf18, &path1_rf18); + /*BB_WARNING("SwCH : RF a/b = %x , %x", path0_rf18, path1_rf18);*/ + if (!bb->hal_com->dbcc_en) { + /*============== [Path A] ==============*/ + rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK, path0_rf18, 0); + /*============== [Path B] ==============*/ + rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK, path1_rf18, 0); + } else { + if (phy_idx == HW_PHY_0) { + /*============== [Path A] ==============*/ + rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK, path0_rf18, 0); + } else { + /*============== [Path B] ==============*/ + rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK, path1_rf18, 0); + } + } + /*==== [CCK Enable / Disable] ====*/ + rpt &= halbb_fwofld_cck_en_8852a_2(bb, cck_en, phy_idx); + /*==== [Spur elimination] ====*/ + if (central_ch == 153) { + rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x210, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x210, 0); + rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x7c0, 0); + rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0); + } else if (central_ch == 151) { + rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x210, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x210, 0); + rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x40, 0); + rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0); + } else if (central_ch == 155) { + rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x2d0, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x2d0, 0); + rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x740, 0); + rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0); + } else { + rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x0, 0); + rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x0, 0); + rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x0, 0); + } + + if (is_2g_ch && ((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB))) + rpt &=halbb_fwofld_btg_8852a_2(bb, true); + else + rpt &=halbb_fwofld_btg_8852a_2(bb, false); + + /* Dynamic 5M Mask Setting */ + rpt &=halbb_fw_5m_mask_8852a_2(bb, pri_ch, bw); + + /*==== [TSSI reset] ====*/ + if (!bb->hal_com->dbcc_en) { + // Path A + rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3, 0); + // Path B + rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3, 1); + } else { + if (phy_idx == HW_PHY_0) { + // Path A + rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3, 1); + } else { + // Path B + rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1, 0); + rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3, 1); + } + } + + return rpt; +} +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_fwofld.h b/phl/hal_g6/phy/bb/halbb_fwofld.h new file mode 100644 index 0000000..b8e62f3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_fwofld.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_FWOFLD_H__ +#define __HALBB_FWOFLD_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +#ifdef HALBB_FW_OFLD_SUPPORT +bool halbb_fwcfg_bb_phy_8852a_2(struct bb_info *bb, u32 addr, u32 data, + enum phl_phy_idx phy_idx); +bool halbb_fwofld_bw_ch_8852a_2(struct bb_info *bb, u8 pri_ch, u8 central_ch, + enum channel_width bw, enum phl_phy_idx phy_idx); +#endif +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_hw_cfg.c b/phl/hal_g6/phy/bb/halbb_hw_cfg.c new file mode 100644 index 0000000..8e5a60b --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_hw_cfg.c @@ -0,0 +1,327 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +void halbb_cfg_bb_rpl_ofst(struct bb_info *bb, enum bb_band_t band, u8 path, u32 addr, u32 data) +{ + struct bb_gain_info *gain = &bb->bb_gain_i; + u8 i = 0; + u8 bw = (u8)(addr & 0xf0) >> 4; + u8 rxsc_start = (u8)(addr & 0xf); + u8 rxsc = 0; + s8 ofst = 0; + + if (bw == (u8)CHANNEL_WIDTH_20) { + gain->rpl_ofst_20[band][path] = (s8)data; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, gain->rpl_ofst_20[band][path]); + } else if (bw == (u8)CHANNEL_WIDTH_40){ + if (rxsc_start == BB_RXSC_START_IDX_FULL) { + gain->rpl_ofst_40[band][path][0] = (s8)data; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, + gain->rpl_ofst_40[band][path][0]); + } else if (rxsc_start == BB_RXSC_START_IDX_20) { + for (i = 0; i < 2; i++) { + rxsc = BB_RXSC_START_IDX_20 + i; + ofst = (s8)((data >> (8 * i)) & 0xff); + gain->rpl_ofst_40[band][path][rxsc] = ofst; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, + gain->rpl_ofst_40[band][path][rxsc]); + } + } + + } else if (bw == (u8)CHANNEL_WIDTH_80){ + if (rxsc_start == BB_RXSC_START_IDX_FULL) { + gain->rpl_ofst_80[band][path][0] = (s8)data; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, + gain->rpl_ofst_80[band][path][0]); + } else if (rxsc_start == BB_RXSC_START_IDX_20) { + for (i = 0; i < 4; i++) { + rxsc = BB_RXSC_START_IDX_20 + i; + ofst = (s8)((data >> (8 * i)) & 0xff); + gain->rpl_ofst_80[band][path][rxsc] = ofst; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, + gain->rpl_ofst_80[band][path][rxsc]); + } + } else if (rxsc_start == BB_RXSC_START_IDX_40) { + for (i = 0; i < 2; i++) { + rxsc = BB_RXSC_START_IDX_40 + i; + ofst = (s8)((data >> (8 * i)) & 0xff); + gain->rpl_ofst_80[band][path][rxsc] = ofst; + BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n", + band, path, (20 << bw), rxsc, + gain->rpl_ofst_80[band][path][rxsc]); + } + } + } +} + +bool halbb_init_cr_default(struct bb_info *bb, bool is_form_folder, u32 folder_len, + u32 *folder_array, enum phl_phy_idx phy_idx) +{ + bool result = true; + + if (!bb->bb_cmn_info_init_ready) { + BB_WARNING("bb_cmn_info_init_ready = false"); + return false; + } + + if (is_form_folder) { + if (!folder_array) { + BB_WARNING("[%s] folder_array=NULL\n", __func__); + return false; + } + + if (folder_len == 0) { + BB_WARNING("[%s] folder_len=0\n", __func__); + return false; + } + } + +#ifdef HALBB_DBCC_SUPPORT + if (phy_idx == HW_PHY_1 && !bb->hal_com->dbcc_en) { + BB_WARNING("[%s]\n",__func__); + if (!bb->bb_dbg_i.cr_dbg_mode_en) + return false; + } +#endif + + BB_DBG(bb, DBG_INIT, "[%s] ic=%d\n", __func__, bb->hal_com->chip_id); + + switch (bb->ic_type) { + + case BB_RTL8852AA: + #ifdef BB_8852A_CAV_SUPPORT + result = halbb_cfg_bbcr_ax_8852a(bb, is_form_folder, folder_len, + folder_array, phy_idx); + #else + BB_WARNING("[%s] NOT Support 8852AA\n", __func__); + result = false; + #endif + break; + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + result = halbb_cfg_bbcr_ax_8852a_2(bb, is_form_folder, folder_len, + folder_array, phy_idx); + halbb_tpu_mac_cr_init(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + result = halbb_cfg_bbcr_ax_8852b(bb, is_form_folder, folder_len, + folder_array, phy_idx); + halbb_tpu_mac_cr_init(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + result = halbb_cfg_bbcr_ax_8852c(bb, is_form_folder, folder_len, + folder_array, phy_idx); + halbb_tpu_mac_cr_init(bb, phy_idx); + break; + #endif + + default: + BB_WARNING("[%s] ic=%d\n", __func__, bb->hal_com->chip_id); + break; + } + + BB_DBG(bb, DBG_INIT, "BB_CR_init_success = %d\n", result); + return result; +} + +bool halbb_init_gain_table(struct bb_info *bb, bool is_form_folder, u32 folder_len, + u32 *folder_array, enum phl_phy_idx phy_idx) +{ + bool result = true; + + if (!bb->bb_cmn_info_init_ready) { + BB_WARNING("bb_cmn_info_init_ready = false"); + return false; + } + + if (is_form_folder) { + if (!folder_array) { + BB_WARNING("[%s] folder_array=NULL\n", __func__); + return false; + } + + if (folder_len == 0) { + BB_WARNING("[%s] folder_len=0\n", __func__); + return false; + } + } + +#ifdef HALBB_DBCC_SUPPORT + if (phy_idx == HW_PHY_1 && !bb->hal_com->dbcc_en) { + BB_WARNING("[%s]\n",__func__); + if (!bb->bb_dbg_i.cr_dbg_mode_en) + return false; + } +#endif + + BB_DBG(bb, DBG_INIT, "[%s] ic=%d\n", __func__, bb->hal_com->chip_id); + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + result &= halbb_cfg_bb_gain_ax_8852a_2(bb, is_form_folder, + folder_len, folder_array); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + result &= halbb_cfg_bb_gain_ax_8852b(bb, is_form_folder, + folder_len, folder_array); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + result &= halbb_cfg_bb_gain_ax_8852c(bb, is_form_folder, + folder_len, folder_array); + break; + #endif + + default: + BB_WARNING("[%s] ic=%d\n", __func__, bb->hal_com->chip_id); + break; + } + + BB_DBG(bb, DBG_INIT, "BB_Gain_table_init_success = %d\n", result); + return result; +} + +bool halbb_init_reg(struct bb_info *bb) +{ + struct rtw_para_info_t *reg = NULL; + bool rpt_0 = true, rpt_1 = true, rpt_gain = true; + + reg = &bb->phl_com->phy_sw_cap[HW_PHY_0].bb_phy_reg_info; + rpt_0 = halbb_init_cr_default(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_0); + + if (bb->hal_com->dbcc_en) { + reg = &bb->phl_com->phy_sw_cap[HW_PHY_1].bb_phy_reg_info; + rpt_1 = halbb_init_cr_default(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_1); + } + + reg = &bb->phl_com->phy_sw_cap[HW_PHY_0].bb_phy_reg_gain_info; + rpt_gain = halbb_init_gain_table(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_0); + + if (rpt_0 && rpt_1 && rpt_gain) + return true; + else + return false; +} + +void halbb_rx_gain_table_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len) +{ + struct bb_gain_info *gain = &bb->bb_gain_i; + u32 val[10] = {0}; + u8 i = 0, j = 0; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{show}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set {lna, tia} band path idx val\n"); + return; + } + + if (_os_strcmp(input[1], "show") == 0) { + for (i = 0; i < BB_GAIN_BAND_NUM; i++) { + if (i == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "===[2G]===\n"); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "===[5G-%s]===\n", (i == 1) ? ("Low") : ((i == 2) ? "Mid" : "High")); + } + for (j = 0; j < HALBB_MAX_PATH; j++) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "LNA_gain[Path=%d] = {%d, %d, %d, %d, %d, %d, %d}\n", + j, + gain->lna_gain[i][j][0], + gain->lna_gain[i][j][1], + gain->lna_gain[i][j][2], + gain->lna_gain[i][j][3], + gain->lna_gain[i][j][4], + gain->lna_gain[i][j][5], + gain->lna_gain[i][j][6]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "TIA_gain[Path=%d] = {%d, %d}\n", + j, + gain->tia_gain[i][j][0], + gain->tia_gain[i][j][1]); + } + } + } else if (_os_strcmp(input[1], "set") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[6], DCMD_DECIMAL, &val[3]); + + if (_os_strcmp(input[2], "lna") == 0) { + if (val[0] >= BB_GAIN_BAND_NUM || + val[1] >= HALBB_MAX_PATH || + val[2] >= IC_LNA_NUM) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + gain->lna_gain[val[0]][val[1]][val[2]] = (s8)val[3]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set lna_gain[%d][%d][%d] = %d\n", + val[0], val[1], val[2], val[3]); + + } else if (_os_strcmp(input[2], "tia") == 0) { + if (val[0] >= BB_GAIN_BAND_NUM || + val[1] >= HALBB_MAX_PATH || + val[2] >= IC_TIA_NUM) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + gain->tia_gain[val[0]][val[1]][val[2]] = (s8)val[3]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set tia_gain[%d][%d][%d] = %d\n", + val[0], val[1], val[2], val[3]); + } + halbb_set_gain_error(bb, bb->hal_com->band[bb->bb_phy_idx].cur_chandef.center_ch); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} diff --git a/phl/hal_g6/phy/bb/halbb_hw_cfg.h b/phl/hal_g6/phy/bb/halbb_hw_cfg.h new file mode 100644 index 0000000..628e44e --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_hw_cfg.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_HW_CFG_H__ +#define __HALBB_HW_CFG_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +#define BB_RXSC_NUM_40 9 /*SC:0,1~8*/ +#define BB_RXSC_NUM_80 13 /*SC:0,1~8,9~12*/ +#define BB_RXSC_NUM_160 15 /*SC:0,1~8,9~12,13~14*/ +#define BB_RXSC_START_IDX_FULL 0 +#define BB_RXSC_START_IDX_20 1 +#define BB_RXSC_START_IDX_40 9 +#define BB_RXSC_START_IDX_80 13 + +//#define BB_GAIN_BAND_NUM 4 +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_band_t { + BB_BAND_2G = 0, + BB_BAND_5G_L = 1, + BB_BAND_5G_M = 2, + BB_BAND_5G_H = 3, + BB_GAIN_BAND_NUM = 4 +}; +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_cfg_bb_rpl_ofst(struct bb_info *bb, enum bb_band_t band, u8 path, u32 addr, u32 data); +bool halbb_init_cr_default(struct bb_info *bb, bool is_form_folder, u32 folder_len, + u32 *folder_array, enum phl_phy_idx phy_idx); +bool halbb_init_gain_table(struct bb_info *bb, bool is_form_folder, u32 folder_len, + u32 *folder_array, enum phl_phy_idx phy_idx); +void halbb_rx_gain_table_dbg(struct bb_info *bb, char input[][16], + u32 *_used, char *output, u32 *_out_len); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_hw_cfg_ex.h b/phl/hal_g6/phy/bb/halbb_hw_cfg_ex.h new file mode 100644 index 0000000..61cc3f4 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_hw_cfg_ex.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALBB_HW_CFG_EX_H_ +#define _HALBB_HW_CFG_EX_H_ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_para_init_t { + BB_DEFAULT_CR = 0, + BB_GAIN_TABLE = 1, +}; + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +bool halbb_init_reg(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ic_hw_info.h b/phl/hal_g6/phy/bb/halbb_ic_hw_info.h new file mode 100644 index 0000000..b72d325 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ic_hw_info.h @@ -0,0 +1,350 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_IC_HW_INFO_H__ +#define __HALBB_IC_HW_INFO_H__ + +enum bb_ic_t { + BB_RTL8852AA = BIT(0), /*8852A Acut*/ + BB_RTL8852A = BIT(1), /*8852A > Bcut*/ + BB_RTL8852B = BIT(2), + BB_RTL8852C = BIT(3), + BB_RTL8834A = BIT(4), + BB_RTL8192XB = BIT(5) +}; + +enum bb_cr_t { + BB_52AA = 0, + BB_AP = 1, + BB_AP2 = 2, + BB_CLIENT = 3 +}; + +#define BB_IC_N_1SS 0 +#define BB_IC_N_2SS 0 +#define BB_IC_N_3SS 0 +#define BB_IC_N_4SS 0 + +#define BB_IC_AC_1SS 0 +#define BB_IC_AC_2SS 0 +#define BB_IC_AC_3SS 0 +#define BB_IC_AC_4SS 0 + +#define BB_IC_AX_1SS 0 +#define BB_IC_AX_2SS (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B | BB_RTL8852C) +#define BB_IC_AX_3SS 0 +#define BB_IC_AX_4SS (BB_RTL8834A) + +/*@====the following macro DO NOT need to update when adding a new IC======= */ +#define BB_IC_1SS (BB_IC_N_1SS | BB_IC_AC_1SS | BB_IC_AX_1SS) +#define BB_IC_2SS (BB_IC_N_2SS | BB_IC_AC_2SS | BB_IC_AX_2SS) +#define BB_IC_3SS (BB_IC_N_3SS | BB_IC_AC_3SS | BB_IC_AX_3SS) +#define BB_IC_4SS (BB_IC_N_4SS | BB_IC_AC_4SS | BB_IC_AX_4SS) + +#define BB_IC_ABOVE_1SS (BB_IC_1SS | BB_IC_2SS | BB_IC_3SS |\ + BB_IC_4SS) +#define BB_IC_ABOVE_2SS (BB_IC_2SS | BB_IC_3SS | BB_IC_4SS) +#define BB_IC_ABOVE_3SS (BB_IC_3SS | BB_IC_4SS) +#define BB_IC_ABOVE_4SS BB_IC_4SS + +#define BB_IC_N_SERIES (BB_IC_N_1SS | BB_IC_N_2SS | BB_IC_N_3SS |\ + BB_IC_N_4SS) +#define BB_IC_AC_SERIES (BB_IC_AC_1SS | BB_IC_AC_2SS |\ + BB_IC_AC_3SS | BB_IC_AC_4SS) +#define BB_IC_AX_SERIES (BB_IC_AX_1SS | BB_IC_AX_2SS |\ + BB_IC_AX_3SS | BB_IC_AX_4SS) +/*@==========================================================================*/ + +#define BB_IC_AX_AP (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852C | BB_RTL8834A) +#define BB_IC_AX_AP2 (BB_RTL8852C | BB_RTL8192XB) +#define BB_IC_AX_CLIENT (BB_RTL8852B) + +/*@==========================================================================*/ + +#define BB_IC_MAX_BW_80 (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B) +#define BB_IC_MAX_BW_160 (BB_RTL8852C | BB_RTL8834A) + +/*@==========================================================================*/ +#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) + #define HALBB_COMPILE_IC_DBCC +#endif + +#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) + /* FW OFFLOAD will be used in non-AP-only ICs*/ + #define HALBB_COMPILE_IC_FWOFLD +#endif + +#if defined(RTL8851A_SUPPORT) + #define HALBB_COMPILE_IC_1SS +#endif + +#if (defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) || defined(BB_8852C_SUPPORT)) + #define HALBB_COMPILE_IC_2SS +#endif + +#if defined(RTL8853A_SUPPORT) + #define HALBB_COMPILE_IC_3SS +#endif + +#if defined(RTL8834A_SUPPORT) + #define HALBB_COMPILE_IC_4SS +#endif + +/*@==========================================================================*/ +#if (defined(HALBB_COMPILE_IC_4SS)) + #define HALBB_COMPILE_ABOVE_4SS +#endif + +#if (defined(HALBB_COMPILE_IC_3SS) || defined(HALBB_COMPILE_ABOVE_4SS)) + #define HALBB_COMPILE_ABOVE_3SS +#endif + +#if (defined(HALBB_COMPILE_IC_2SS) || defined(HALBB_COMPILE_ABOVE_3SS)) + #define HALBB_COMPILE_ABOVE_2SS +#endif + +#if (defined(HALBB_COMPILE_IC_1SS) || defined(HALBB_COMPILE_ABOVE_2SS)) + #define HALBB_COMPILE_ABOVE_1SS +#endif + +#if (defined(HALBB_COMPILE_ABOVE_4SS)) + #define HALBB_MAX_PATH 4 +#elif (defined(HALBB_COMPILE_ABOVE_3SS)) + #define HALBB_MAX_PATH 3 +#elif (defined(HALBB_COMPILE_ABOVE_2SS)) + #define HALBB_MAX_PATH 2 +#else + #define HALBB_MAX_PATH 1 +#endif +/*@==========================================================================*/ +#if (defined(BB_8852A_CAV_SUPPORT)) + #define HALBB_52AA_SERIES +#endif + +#if (defined(BB_8852A_2_SUPPORT) || defined(BB_8852C_SUPPORT) || defined(BB_8834A_SUPPORT)) + #define HALBB_COMPILE_AP_SERIES +#endif + +#if (defined(BB_8852C_SUPPORT) || defined(BB_8192XB_SUPPORT)) + #define HALBB_COMPILE_AP2_SERIES +#endif + +#if (defined(BB_8852B_SUPPORT)) + #define HALBB_COMPILE_CLIENT_SERIES +#endif + +/*@==========================================================================*/ +enum halbb_rate_type { + BB_1SS = 1, /*HE/VHT/HT 1SS*/ + BB_2SS = 2, /*HE/VHT/HT 2SS*/ + BB_3SS = 3, /*HE/VHT/HT 3SS*/ + BB_4SS = 4, /*HE/VHT/HT 4SS*/ + BB_CCK = 11, /*B mode*/ + BB_OFDM = 12 /*G mode*/ +}; + +enum halbb_rate_table { + BB_01M = 0, + BB_02M = 1, + BB_05M = 2, + BB_11M = 3, + BB_06M = 4, + BB_09M = 5, + BB_12M = 6, + BB_18M = 7, + BB_24M = 8, + BB_36M = 9, + BB_48M = 10, + BB_54M = 11, + BB_HT_MCS0 = 128, /*0x1000000*/ + BB_VHT_1SS_MCS0 = 256, /*0x2000000*/ + BB_VHT_2SS_MCS0 = 272, + BB_VHT_3SS_MCS0 = 288, + BB_VHT_4SS_MCS0 = 304, + BB_VHT_5SS_MCS0 = 320, + BB_VHT_6SS_MCS0 = 336, + BB_VHT_7SS_MCS0 = 352, + BB_VHT_8SS_MCS0 = 368, + BB_HE_1SS_MCS0 = 384, /*0x3000000*/ + BB_HE_2SS_MCS0 = 400, + BB_HE_3SS_MCS0 = 416, + BB_HE_4SS_MCS0 = 432, + BB_HE_5SS_MCS0 = 448, + BB_HE_6SS_MCS0 = 464, + BB_HE_7SS_MCS0 = 480, + BB_HE_8SS_MCS0 = 496 +}; + +enum halbb_legacy_spec_rate { + BB_SPEC_RATE_6M = 0xb, + BB_SPEC_RATE_9M = 0xf, + BB_SPEC_RATE_12M = 0xa, + BB_SPEC_RATE_18M = 0xe, + BB_SPEC_RATE_24M = 0x9, + BB_SPEC_RATE_36M = 0xd, + BB_SPEC_RATE_48M = 0x8, + BB_SPEC_RATE_54M = 0xc +}; + +#define GEN_HT_RATE_IDX(MCS) (0x80 | ((MCS) & 0x1f)) +#define GEN_VHT_RATE_IDX(SS, MCS) (0x100 | (((SS) & 0x3) << 4) | ((MCS) & 0xf)) +#define GEN_HE_RATE_IDX(SS, MCS) (0x180 | (((SS) & 0x3) << 4) | ((MCS) & 0xf)) + +#define BB_HT_MCS(x) (BB_HT_MCS0 + x) +#define BB_VHT_1SS_MCS(x) (BB_VHT_1SS_MCS0 + x) +#define BB_VHT_2SS_MCS(x) (BB_VHT_2SS_MCS0 + x) +#define BB_VHT_3SS_MCS(x) (BB_VHT_3SS_MCS0 + x) +#define BB_VHT_4SS_MCS(x) (BB_VHT_4SS_MCS0 + x) +#define BB_VHT_5SS_MCS(x) (BB_VHT_5SS_MCS0 + x) +#define BB_VHT_6SS_MCS(x) (BB_VHT_6SS_MCS0 + x) +#define BB_VHT_7SS_MCS(x) (BB_VHT_7SS_MCS0 + x) +#define BB_VHT_8SS_MCS(x) (BB_VHT_8SS_MCS0 + x) +#define BB_HE_1SS_MCS(x) (BB_HE_1SS_MCS0 + x) +#define BB_HE_2SS_MCS(x) (BB_HE_2SS_MCS0 + x) +#define BB_HE_3SS_MCS(x) (BB_HE_3SS_MCS0 + x) +#define BB_HE_4SS_MCS(x) (BB_HE_4SS_MCS0 + x) +#define BB_HE_5SS_MCS(x) (BB_HE_5SS_MCS0 + x) +#define BB_HE_6SS_MCS(x) (BB_HE_6SS_MCS0 + x) +#define BB_HE_7SS_MCS(x) (BB_HE_7SS_MCS0 + x) +#define BB_HE_8SS_MCS(x) (BB_HE_8SS_MCS0 + x) + +#define BB_VHT_MCS(SS, x) (BB_VHT_1SS_MCS0 + ((SS - 1) * 16 ) + x) +#define BB_HE_MCS(SS, x) (BB_HE_1SS_MCS0 + ((SS - 1) * 16 ) + x) + +/*[Rate Number]*/ +#define HT_NUM_MCS 8 +#define HE_VHT_NUM_MCS 12 +#define LEGACY_RATE_NUM 12 + +#define HT_RATE_NUM_4SS (HT_NUM_MCS * 4) +#define VHT_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4) +#define HE_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4) + +#define HT_RATE_NUM_3SS (HT_NUM_MCS * 3) +#define VHT_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3) +#define HE_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3) + +#define HT_RATE_NUM_2SS (HT_NUM_MCS * 2) +#define VHT_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2) +#define HE_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2) + +#define HT_RATE_NUM_1SS HT_NUM_MCS +#define VHT_RATE_NUM_1SS HE_VHT_NUM_MCS +#define HE_RATE_NUM_1SS HE_VHT_NUM_MCS + +#if (defined(HALBB_COMPILE_ABOVE_4SS)) + #define HT_RATE_NUM HT_RATE_NUM_4SS + #define VHT_RATE_NUM VHT_RATE_NUM_4SS + #define HE_RATE_NUM HE_RATE_NUM_4SS +#elif (defined(HALBB_COMPILE_ABOVE_3SS)) + #define HT_RATE_NUM HT_RATE_NUM_3SS + #define VHT_RATE_NUM VHT_RATE_NUM_3SS + #define HE_RATE_NUM HE_RATE_NUM_3SS +#elif (defined(HALBB_COMPILE_ABOVE_2SS)) + #define HT_RATE_NUM HT_RATE_NUM_2SS + #define VHT_RATE_NUM VHT_RATE_NUM_2SS + #define HE_RATE_NUM HE_RATE_NUM_2SS +#else + #define HT_RATE_NUM HT_RATE_NUM_1SS + #define VHT_RATE_NUM VHT_RATE_NUM_1SS + #define HE_RATE_NUM HE_RATE_NUM_1SS +#endif + +#define LOW_BW_RATE_NUM HE_RATE_NUM + +/*@==========================================================================*/ + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum bb_qam_type { + BB_QAM_CCK = 0, + BB_QAM_BPSK = 1, + BB_QAM_QPSK = 2, + BB_QAM_16QAM = 3, + BB_QAM_64QAM = 4, + BB_QAM_256QAM = 5, + BB_QAM_1024QAM = 6 +}; + +enum bb_mode_type { /*@Fast antenna training*/ + BB_LEGACY_MODE = 0, + BB_HT_MODE = 1, + BB_VHT_MODE = 2, + BB_HE_MODE = 3 +}; + + +/* BB_CMNINFO_CART_VER */ +enum halbb_cart_ver { + BB_CART_A = 0, + BB_CART_B = 1, + BB_CART_C = 2, + BB_CART_D = 3, + BB_CART_E = 4, + BB_CART_F = 5, + BB_CART_G = 6, + BB_CART_H = 7, + BB_CART_I = 8, + BB_CART_J = 9, + BB_CART_K = 10, + BB_CART_L = 11, + BB_CART_M = 12, + BB_CART_N = 13, + BB_CART_O = 14, + BB_CART_TEST = 15, +}; + +enum bb_path { + BB_PATH_NON = 0, + BB_PATH_A = 0x00000001, + BB_PATH_B = 0x00000002, + BB_PATH_C = 0x00000004, + BB_PATH_D = 0x00000008, + + BB_PATH_AB = (BB_PATH_A | BB_PATH_B), + BB_PATH_AC = (BB_PATH_A | BB_PATH_C), + BB_PATH_AD = (BB_PATH_A | BB_PATH_D), + BB_PATH_BC = (BB_PATH_B | BB_PATH_C), + BB_PATH_BD = (BB_PATH_B | BB_PATH_D), + BB_PATH_CD = (BB_PATH_C | BB_PATH_D), + + BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), + BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), + BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), + BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), + + BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), + BB_PATH_AUTO = 0xff /*for auto path selection*/ +}; + +enum rf_syn { + RF_SYN0 = 0, + RF_SYN1 = 1, +}; + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ic_sw_info.h b/phl/hal_g6/phy/bb/halbb_ic_sw_info.h new file mode 100644 index 0000000..622c0fa --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ic_sw_info.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_IC_SW_INFO_H__ +#define __HALBB_IC_SW_INFO_H__ + +#define HLABB_CODE_BASE "HALBB_025" +#define HALBB_RELEASE_DATE "20210930" + +/*HALBB API status*/ +#define HALBB_SET_FAIL 0 +#define HALBB_SET_SUCCESS 1 +#define HALBB_SET_NO_NEED 3 + +/*HALBB Set/Revert*/ +#define HALBB_SET 1 +#define HALBB_REVERT 2 + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum halbb_api_host { + RUN_IN_FW = 0, + RUN_IN_DRIVER = 1 +}; + +enum halbb_backup_type { + HALBB_BACKUP = 1, + HALBB_RESTORE = 2 +}; + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_init.c b/phl/hal_g6/phy/bb/halbb_init.c new file mode 100644 index 0000000..e20dfc2 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_init.c @@ -0,0 +1,616 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halbb_precomp.h" + +bool halbb_chk_bb_rf_pkg_set_valid(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal_i = bb->hal_com; + u8 bb_ver = 0; /*hal_i->bb_para_pkg_ver;*/ /*TBD*/ + u8 rf_ver = 0; /*hal_i->rf_para_pkg_ver;*/ /*TBD*/ + bool valid = true; + + switch (bb->ic_type) { + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + valid = halbb_chk_pkg_valid_8852a(bb, bb_ver, rf_ver); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + valid = halbb_chk_pkg_valid_8852a_2(bb, bb_ver, rf_ver); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + valid = halbb_chk_pkg_valid_8852b(bb, bb_ver, rf_ver); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + valid = halbb_chk_pkg_valid_8852c(bb, bb_ver, rf_ver); + break; + #endif + + #ifdef BB_8834A_SUPPORT + case BB_RTL8834A: + valid = halbb_chk_pkg_valid_8834a(bb, bb_ver, rf_ver); + break; + #endif + + default: + break; + + } + + return valid; +} + +void halbb_ic_hw_setting_init(struct bb_info *bb) +{ + #ifdef HALBB_TDMA_CR_SUPPORT + halbb_tdma_cr_sel_init(bb); + #endif + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_ic_hw_setting_init_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_ic_hw_setting_init_8852a_2(bb); + #ifdef HALBB_DYN_CSI_RSP_SUPPORT + halbb_dcr_init(bb); + #endif + #ifdef BB_DYN_CFO_TRK_LOP + halbb_dyn_cfo_trk_loop_init(bb); + #endif + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_ic_hw_setting_init_8852b(bb); + #ifdef HALBB_DYN_CSI_RSP_SUPPORT + halbb_dcr_init(bb); + #endif + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_ic_hw_setting_init_8852c(bb); + #ifdef HALBB_DYN_CSI_RSP_SUPPORT + halbb_dcr_init(bb); + #endif + break; + #endif + + default: + break; + } +} + +void halbb_get_efuse_init(struct bb_info *bb) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_get_normal_efuse_init_8852a_2(bb); + halbb_get_hidden_efuse_init_8852a_2(bb); + break; + #endif + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_get_normal_efuse_init_8852b(bb); + halbb_get_hide_efuse_init_8852b(bb); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_get_normal_efuse_init_8852c(bb); + halbb_get_hidden_efuse_init_8852c(bb); + break; + #endif + + default: + break; + } +} + +void halbb_cmn_info_self_init(struct bb_info *bb) +{ + struct rtw_hal_com_t *hal_i = bb->hal_com; + + /*[IC type]*/ + if (hal_i->chip_id == CHIP_WIFI6_8852A) { + if (hal_i->cv == CAV) + bb->ic_type = BB_RTL8852AA; + else + bb->ic_type = BB_RTL8852A; + } else if (hal_i->chip_id == CHIP_WIFI6_8852B) { + bb->ic_type = BB_RTL8852B; + #ifdef BB_8852C_SUPPORT + } else if (hal_i->chip_id == CHIP_WIFI6_8852C) { + bb->ic_type = BB_RTL8852C; + #endif + } else if (hal_i->chip_id == CHIP_WIFI6_8834A) { + bb->ic_type = BB_RTL8834A; + #ifdef BB_8192XB_SUPPORT + } else if (hal_i->chip_id == CHIP_WIFI6_8192XB) { + bb->ic_type = BB_RTL8192XB; + #endif + } + + /*[CR type]*/ + if (bb->ic_type == BB_RTL8852AA) + bb->cr_type = BB_52AA; + else if (bb->ic_type & BB_IC_AX_AP) + bb->cr_type = BB_AP; + else if (bb->ic_type & BB_IC_AX_AP2) + bb->cr_type = BB_AP2; + else if (bb->ic_type & BB_IC_AX_CLIENT) + bb->cr_type = BB_CLIENT; + + /*[RF path number]*/ + if (bb->ic_type & BB_IC_1SS) + bb->num_rf_path = 1; + else if (bb->ic_type & BB_IC_2SS) + bb->num_rf_path = 2; + else if (bb->ic_type & BB_IC_3SS) + bb->num_rf_path = 3; + else if (bb->ic_type & BB_IC_4SS) + bb->num_rf_path = 4; + else + bb->num_rf_path = 1; + + BB_DBG(bb, DBG_INIT, "cr_type=%d, num_rf_path=%d\n", + bb->cr_type, bb->num_rf_path); + + BB_DBG(bb, DBG_INIT, + "num_rf_path=%d, rate_num{Legcy, HT, VHT, HE}={%d,%d,%d,%d}\n", + bb->num_rf_path, + LEGACY_RATE_NUM, HT_RATE_NUM, VHT_RATE_NUM, HE_RATE_NUM); + + bb->manual_support_ability = 0xffffffff; + bb->bb_dm_init_ready = false; + bb->bb_sys_up_time = 0; + bb->bb_watchdog_en = true; + bb->bb_ic_api_en = true; + /*[Drv Dbg Info]*/ + bb->cmn_dbg_msg_period = 2; + bb->cmn_dbg_msg_cnt = 0; + /*[Dummy]*/ + bb->bool_dummy = false; + bb->u8_dummy = 0xff; + bb->u16_dummy = 0xffff; + bb->u32_dummy = 0xffffffff; + /*@=== [HALBB Structure] ============================================*/ + bb->bb_link_i.is_linked = false; + bb->bb_link_i.is_linked_pre = false; + bb->bb_link_i.tp_active_th = 5; + bb->bb_path_i.rx_path_en = bb->num_rf_path; + bb->bb_path_i.tx_path_en = bb->num_rf_path; + bb->adv_bb_dm_en = true; + + bb->bb_cmn_info_init_ready = true; + bb->bb_watchdog_period = 2; /*sec*/ + + bb->bb_cmn_hooker->bb_dm_number = sizeof(halbb_func_i) / sizeof(struct halbb_func_info); + halbb_edcca_dev_hw_cap(bb); + halbb_cmn_info_self_reset(bb); +} + +u64 halbb_supportability_default(struct bb_info *bb) +{ + u64 support_ability = 0; + + switch (bb->ic_type) { +#ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + support_ability |= + /*BB_RA |*/ + BB_FA_CNT | + /*BB_DFS |*/ + BB_EDCCA | + /*BB_ENVMNTR |*/ + BB_CFO_TRK | + /*BB_DIG |*/ + 0; + break; +#endif +#ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + support_ability |= + /*BB_RA |*/ + BB_FA_CNT | + BB_DFS | + BB_EDCCA | + BB_ENVMNTR | + BB_CFO_TRK | + BB_DIG | + /*BB_ANT_DIV |*/ + 0; + break; +#endif +#ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + support_ability |= + BB_RA | + BB_FA_CNT | + BB_DFS | + BB_EDCCA | + BB_CFO_TRK | + BB_ENVMNTR | + BB_DIG | + 0; + + break; +#endif +#ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + support_ability |= + /*BB_RA |*/ + BB_FA_CNT | + BB_DFS | + BB_EDCCA | + BB_ENVMNTR | + BB_CFO_TRK | + BB_DIG | + /*BB_ANT_DIV |*/ + 0; + break; +#endif + + default: + BB_WARNING("[%s]\n", __func__); + break; + } + return support_ability; +} + +void halbb_supportability_init(struct bb_info *bb) +{ + u64 support_ability; + +#if 0 + if (bb->phl_com->bb_ability_manual != 0xffffffff) { + support_ability = bb->phl_com->bb_ability_manual; + } else +#endif + if(phl_is_mp_mode(bb->phl_com)) { + support_ability = 0; + } else { + support_ability = halbb_supportability_default(bb); + } + + bb->support_ability = support_ability; + + BB_DBG(bb, DBG_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n", + bb->ic_type, bb->phl_com->drv_mode, bb->support_ability); +} + +void halbb_hw_init(struct bb_info *bb) +{ + BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); + + halbb_cmn_info_self_init(bb); + + if (!halbb_chk_bb_rf_pkg_set_valid(bb)) { + BB_WARNING("[%s] Init fail\n", __func__); + return; + } +} + +void halbb_dm_deinit(struct rtw_phl_com_t *phl_com, void *bb_phy_0) +{ + struct bb_info *bb = (struct bb_info *)bb_phy_0; + + if (!bb->bb_dm_init_ready) + return; + + halbb_timer_ctrl(bb, BB_CANCEL_TIMER); + + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_deinit(bb); + #endif + #ifdef HALBB_PSD_SUPPORT + halbb_psd_deinit(bb); + #endif + #ifdef HALBB_CH_INFO_SUPPORT + halbb_ch_info_deinit(bb); + #endif + #ifdef HALBB_DIG_SUPPORT + halbb_dig_deinit(bb); + #endif + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antdiv_deinit(bb); + #endif + #ifdef BB_8852A_2_SUPPORT + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_deinit(bb); + #endif + + bb->bb_dm_init_ready = false; +} + +enum rtw_hal_status halbb_dm_init(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + if (!bb) { + BB_WARNING("[%s] *bb = NULL", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + if (!bb->bb_cmn_info_init_ready) { + BB_WARNING("bb_cmn_info_init_ready = false"); + return RTW_HAL_STATUS_FAILURE; + } + +#ifdef HALBB_DBCC_SUPPORT + #ifdef HALBB_DBCC_DVLP_FLAG + if (phy_idx == HW_PHY_1) + return hal_status; + #endif + bb = halbb_get_curr_bb_pointer(bb, phy_idx); + BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); +#endif + halbb_ic_hw_setting_init(bb); + halbb_gpio_setting_init(bb); + halbb_get_efuse_init(bb); + + halbb_supportability_init(bb); + halbb_physts_parsing_init(bb); + halbb_cmn_rpt_init(bb); + halbb_dbg_setting_init(bb); + + #ifdef HALBB_PWR_CTRL_SUPPORT + halbb_macid_ctrl_init(bb); + #endif + #ifdef HALBB_STATISTICS_SUPPORT + halbb_statistics_init(bb); + #endif + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_init(bb); + #endif + #ifdef HALBB_PSD_SUPPORT + halbb_psd_init(bb); + #endif + #ifdef HALBB_EDCCA_SUPPORT + halbb_edcca_init(bb); + #endif + #ifdef HALBB_DFS_SUPPORT + halbb_dfs_init(bb); + #endif + #ifdef HALBB_DIG_SUPPORT + halbb_dig_init(bb); + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_trk_init(bb); + #endif + #ifdef HALBB_RA_SUPPORT + halbb_ra_init(bb); + #endif + #ifdef HALBB_ENV_MNTR_SUPPORT + halbb_env_mntr_init(bb); + #endif + #ifdef HALBB_PWR_CTRL_SUPPORT + halbb_pwr_ctrl_init(bb); + #endif + #ifdef HALBB_RUA_SUPPORT + halbb_rua_tbl_init(bb); + #endif + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antdiv_init(bb); + #endif + #ifdef HALBB_CH_INFO_SUPPORT + halbb_ch_info_init(bb); + #endif + halbb_reset_adc(bb); + + #ifdef HALBB_DIG_MCC_SUPPORT + Halbb_init_mccdm(bb); + #endif + bb->bb_dm_init_ready = true; + BB_DBG(bb, DBG_INIT, "bb_init_ready = %d\n", bb->bb_dm_init_ready); + + return hal_status; +} + +void halbb_timer_ctrl(struct bb_info *bb, enum bb_timer_cfg_t timer_state) +{ + BB_DBG(bb, DBG_INIT, "[%s] timer_state = %d\n", __func__, timer_state); + + /*BB-0 & BB-1 timer*/ + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_cfg_timers(bb, timer_state, &bb->bb_ant_div_i.antdiv_timer_i); + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfg_timers(bb, timer_state, &bb->bb_cfo_trk_i.cfo_timer_i); + #endif + #ifdef HALBB_TDMA_CR_SUPPORT + halbb_cfg_timers(bb, timer_state, &bb->bb_dbg_i.tdma_cr_timer_i); + #endif + #ifdef HALBB_DIG_TDMA_SUPPORT + halbb_cfg_timers(bb, timer_state, &bb->bb_dig_i.dig_timer_i); + #endif + + if (!bb->bb_cmn_hooker) + return; + + /*BB Common Timer*/ + #ifdef HALBB_LA_MODE_SUPPORT + halbb_cfg_timers(bb, timer_state, &bb->bb_cmn_hooker->bb_la_mode_i.la_timer_i); + #endif +} + +void halbb_timer_init(struct bb_info *bb) +{ + BB_DBG(bb, DBG_INIT, "[%s]\n", __func__); + + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antdiv_timer_init(bb); + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cfo_acc_timer_init(bb); + #endif + #ifdef HALBB_TDMA_CR_SUPPORT + halbb_tdma_cr_timer_init(bb); + #endif + #ifdef HALBB_DIG_TDMA_SUPPORT + halbb_dig_timer_init(bb); + #endif + #ifdef HALBB_LA_MODE_SUPPORT + halbb_la_timer_init(bb); + #endif +} + +void halbb_cr_cfg_init(struct bb_info *bb) +{ + halbb_cr_cfg_dbg_init(bb); + halbb_cr_cfg_physts_init(bb); + #ifdef HALBB_STATISTICS_SUPPORT + halbb_cr_cfg_stat_init(bb); + #endif + #ifdef HALBB_PSD_SUPPORT + halbb_cr_cfg_psd_init(bb); + #endif + #ifdef HALBB_DIG_SUPPORT + halbb_cr_cfg_dig_init(bb); + #endif + #ifdef HALBB_ENV_MNTR_SUPPORT + halbb_cr_cfg_env_mntr_init(bb); + #endif + #ifdef HALBB_EDCCA_SUPPORT + halbb_cr_cfg_edcca_init(bb); + #endif + #ifdef HALBB_DFS_SUPPORT + halbb_cr_cfg_dfs_init(bb); + #endif + #ifdef HALBB_LA_MODE_SUPPORT + halbb_cr_cfg_la_init(bb); + #endif + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_cr_cfg_antdiv_init(bb); + #endif + #ifdef HALBB_PMAC_TX_SUPPORT + halbb_cr_cfg_plcp_init(bb); + #endif + halbb_cr_cfg_mp_init(bb); + #ifdef HALBB_CH_INFO_SUPPORT + halbb_cr_cfg_ch_info_init(bb); + #endif + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_cr_cfg_cfo_trk_init(bb); + #endif +} + +void halbb_buffer_deinit(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void *bb_phy_0) +{ + struct bb_info *bb = (struct bb_info *)bb_phy_0; + + BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_idx); + halbb_timer_ctrl(bb, BB_CANCEL_TIMER); + halbb_timer_ctrl(bb, BB_RELEASE_TIMER); + + /*Deinit phy-cmn*/ + if (bb->bb_cmn_hooker) { + BB_DBG(bb, DBG_INIT, "deinit bb_cmn_hooker"); + hal_mem_free(hal_com, bb->bb_cmn_hooker, sizeof(struct bb_cmn_info)); + } + #ifdef HALBB_DBCC_SUPPORT + /*Deinit phy-1*/ + if (bb->bb_phy_hooker) { + BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_hooker->bb_phy_idx); + //halbb_timer_ctrl(bb->bb_phy_hooker, BB_CANCEL_TIMER); + //halbb_timer_ctrl(bb->bb_phy_hooker, BB_RELEASE_TIMER); + hal_mem_free(hal_com, bb->bb_phy_hooker, sizeof(struct bb_info)); + } + #endif + /*Deinit phy-0*/ + if (bb) { + hal_mem_free(hal_com, bb, sizeof(struct bb_info)); + } +} + +u32 +halbb_buffer_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **bb_out_addr) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct bb_info *bb_0 = NULL; + struct bb_cmn_info *bb_cmn = NULL; + + bb_0 = hal_mem_alloc(hal_com, sizeof(struct bb_info)); + + if (!bb_0) { + BB_WARNING("*bb = NULL\n"); + return RTW_HAL_STATUS_BB_INIT_FAILURE; + } + + *bb_out_addr = bb_0; + + bb_0->phl_com = phl_com;/*shared memory for all components*/ + bb_0->hal_com = hal_com;/*shared memory for phl and hal*/ + bb_0->bb_phy_idx = HW_PHY_0; + + bb_cmn = hal_mem_alloc(hal_com, sizeof(struct bb_cmn_info)); + if (!bb_cmn) { + BB_WARNING("*bb_cmn = NULL\n"); + return RTW_HAL_STATUS_BB_INIT_FAILURE; + } + + bb_0->bb_cmn_hooker = bb_cmn; + + halbb_dbg_comp_init(bb_0); + halbb_hw_init(bb_0); + halbb_timer_init(bb_0); + halbb_cr_cfg_init(bb_0); + + #ifdef HALBB_DBCC_SUPPORT + BB_DBG(bb_0, DBG_INIT, "dbcc_support = %d\n", phl_com->dev_cap.dbcc_sup); + hal_status = halbb_buffer_init_phy1(bb_0); + #else + BB_DBG(bb_0, DBG_INIT, "DBCC macro not enabled\n"); + #endif + + BB_DBG(bb_0, DBG_INIT, "[%s]\n", __func__); + BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Base:", HLABB_CODE_BASE); + BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Release Date", HALBB_RELEASE_DATE); + + #ifdef BB_8852A_CAV_SUPPORT + BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A); + BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A); + #endif + + #ifdef BB_8852A_2_SUPPORT + BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A_2); + BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A_2); + #endif + + return (u32)hal_status; +} + diff --git a/phl/hal_g6/phy/bb/halbb_init.h b/phl/hal_g6/phy/bb/halbb_init.h new file mode 100644 index 0000000..6ebf49e --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_init.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_INIT_H_ +#define _HALBB_INIT_H_ +#include "../../hal_headers_le.h" + + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + + /*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_cmn_info_self_init(struct bb_info *bb); +void halbb_timer_ctrl(struct bb_info *bb, enum bb_timer_cfg_t timer_state); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_init_ex.h b/phl/hal_g6/phy/bb/halbb_init_ex.h new file mode 100644 index 0000000..b1bacb1 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_init_ex.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_INIT_EX_H_ +#define _HALBB_INIT_EX_H_ + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + + /*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_dm_deinit(struct rtw_phl_com_t *phl_com, void *bb_phy_0); +enum rtw_hal_status halbb_dm_init(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_buffer_deinit(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void *bb_phy_0); +u32 halbb_buffer_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **bb_out_addr); + +void halbb_get_efuse_init(struct bb_info *bb); + +void halbb_ic_hw_setting_init(struct bb_info *bb); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_interface.c b/phl/hal_g6/phy/bb/halbb_interface.c new file mode 100644 index 0000000..7f3e1d1 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_interface.c @@ -0,0 +1,582 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg, + struct halbb_timer_info *timer) +{ + BB_DBG(bb, DBG_DBG_API, "[%s] %s timer\n", __func__, + ((cfg == BB_SET_TIMER) ? "SET" : ((cfg == BB_CANCEL_TIMER) ? "CANCEL" : ("RLS")))); + + if (cfg == BB_INIT_TIMER) { + BB_WARNING("[%s]\n", __func__); + return; + } + + if (cfg == BB_SET_TIMER) { + if (timer->timer_state != BB_TIMER_IDLE) { + BB_WARNING("[%s] state=%d\n", __func__, timer->timer_state); + return; + } + + timer->timer_state = BB_TIMER_RUN; + halbb_set_timer(bb, &timer->timer_list, timer->cb_time); + } else if (cfg == BB_CANCEL_TIMER) { + halbb_cancel_timer(bb, &timer->timer_list); + timer->timer_state = BB_TIMER_IDLE; + } else if (cfg == BB_RELEASE_TIMER) { + halbb_release_timer(bb, &timer->timer_list); + timer->timer_state = BB_TIMER_RELEASE; + } +} + +u32 halbb_get_sys_time(struct bb_info *bb) +{ + return 0; +} + +u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr) +{ + u32 ofst = 0; + +#ifdef HALBB_DBCC_SUPPORT + switch (bb->ic_type) { + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + ofst = halbb_phy0_to_phy1_ofst_8852a(bb, addr); + break; + #endif + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + ofst = halbb_phy0_to_phy1_ofst_8852a_2(bb, addr); + break; + #endif + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + ofst = halbb_phy0_to_phy1_ofst_8852c(bb, addr); + break; + #endif + + default: + break; + } +#endif + return ofst; +} + +#ifdef BB_FW_OFLD_SUPPORT +bool halbb_check_fw_ofld(struct bb_info *bb) +{ + bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0; + BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret); + return ret; +} + +bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) +{ +/* halbb_set_reg */ + struct rtw_mac_cmd cmd; + u32 ret; + + cmd.src = RTW_MAC_BB_CMD_OFLD; + cmd.type = RTW_MAC_WRITE_OFLD; + cmd.lc = lc; + cmd.offset = (u16)addr; + cmd.value = val; + cmd.mask = mask; + ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); + BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask); + if (ret) { + BB_WARNING("IO offload fail: %d\n", ret); + return false; + } + else { + return true; + } + +} + +bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, + u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc) +{ + bool ret = true; + u32 val_mod = val; + + #ifdef HALBB_DBCC_SUPPORT + if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) + addr += halbb_phy0_to_phy1_ofst(bb, addr); + #endif + + ret = halbb_fw_set_reg(bb, addr, mask, val_mod, lc); + return ret; +} + +#endif + +void halbb_set_cr(struct bb_info *bb, u32 addr, u32 val) +{ + if (bb->bb_dbg_i.cr_recorder_en) + BB_TRACE("[W] 0x%04x = 0x%08x\n", addr, val); + + halbb_set_32(bb, addr, val); +} + +u32 halbb_get_cr(struct bb_info *bb, u32 addr) +{ + u32 val = halbb_get_32(bb, addr); + + if (bb->bb_dbg_i.cr_recorder_en) + BB_TRACE("[R] 0x%04x = 0x%08x\n", addr, val); + + return val; +} + +void halbb_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val) +{ + u32 ori_val = 0; + u32 shift; + + if (mask != MASKDWORD) { + ori_val = halbb_get_32(bb, addr); + shift = halbb_cal_bit_shift(mask); + val = ((ori_val) & (~mask)) | (((val << shift)) & mask); + } + + halbb_set_cr(bb, addr, val); +} + +void halbb_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val, enum phl_phy_idx phy_idx) +{ + u32 ori_val, shift; + u32 val_mod = val; + + #ifdef HALBB_DBCC_SUPPORT + if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) + addr += halbb_phy0_to_phy1_ofst(bb, addr); + #endif + + if (mask != MASKDWORD) { + shift = halbb_cal_bit_shift(mask); + + ori_val = halbb_get_32(bb, addr); + val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask); + } + + halbb_set_cr(bb, addr, val_mod); +} + +void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val) +{ + u32 ori_val = 0, shift = 0; + u32 val_mod = val; + + if (mask != MASKDWORD) { + shift = halbb_cal_bit_shift(mask); + + ori_val = halbb_get_32(bb, addr); + val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask); + } + + halbb_set_cr(bb, addr, val_mod); + + #ifdef HALBB_DBCC_SUPPORT + if (!bb->hal_com->dbcc_en) + return; + + addr += halbb_phy0_to_phy1_ofst(bb, addr); + if (mask != MASKDWORD) { + ori_val = halbb_get_32(bb, addr); + val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask); + } + halbb_set_cr(bb, addr, val_mod); + #endif +} + +u32 halbb_get_reg(struct bb_info *bb, u32 addr, u32 mask) +{ + u32 val_0 = 0; + + val_0 = (halbb_get_cr(bb, addr) & mask) >> halbb_cal_bit_shift(mask); + + return val_0; +} + +u32 halbb_get_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, enum phl_phy_idx phy_idx) +{ + u32 val_0 = 0; + + #ifdef HALBB_DBCC_SUPPORT + if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) + addr += halbb_phy0_to_phy1_ofst(bb, addr); + #endif + + val_0 = (halbb_get_cr(bb, addr) & mask) >> halbb_cal_bit_shift(mask); + + return val_0; +} + +u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1) +{ + u32 val_0 = 0; + u32 shift = halbb_cal_bit_shift(mask); + + val_0 = (halbb_get_cr(bb, addr) & mask) >> shift; + + #ifdef HALBB_DBCC_SUPPORT + if (!bb->hal_com->dbcc_en) + return val_0; + + addr += halbb_phy0_to_phy1_ofst(bb, addr); + *val_1 = (halbb_get_cr(bb, addr) & mask) >> shift; + #endif + + return val_0; +} + +bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid, + u8 classid, u32 *pval) +{ + u32 rt_val = 0; + struct rtw_g6_h2c_hdr hdr = {0}; + struct rtw_hal_com_t *hal_com = NULL; + + hdr.h2c_class = classid; + hdr.h2c_func = cmdid; + hdr.content_len = cmdlen; + hdr.type = H2CB_TYPE_LONG_DATA; + hdr.rec_ack = 0; + hdr.done_ack = 0; + hal_com = bb->hal_com; + BB_DBG(bb, DBG_FW_INFO, "H2C: %x %x %x\n", classid, cmdid, cmdlen); + rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval); + if (rt_val != 0) { + BB_WARNING("Error H2C CLASS=%d, ID=%d, Rt_v = %d\n", classid, cmdid, rt_val); + return false; + } else { + return true; + } +} + +bool halbb_test_h2c_c2h_flow(struct bb_info *bb) +{ + u32 rt_val = 0; + u32 *bb_h2c; + u8 h2ctest[4] = {1, 0, 0, 0}; + + bb_h2c = (u32 *) &h2ctest; + rt_val = halbb_fill_h2c_cmd(bb, 1, DM_H2C_FW_H2C_TEST, HALBB_H2C_DM, bb_h2c); + if (rt_val != 0) { + BB_WARNING("Error H2C TEST\n"); + return false; + } else { + return true; + } +} + +u32 halbb_c2h_rua_parsing(struct bb_info *bb, u8 cmdid, u8 len, u8 *c2h) +{ + u32 val = 0; + return val; +} + +u32 halbb_c2h_mu_gptbl_rpt(struct bb_info *bb, u16 len, u8 *c2h) +{ + /* Set MU grouping table and return value */ + u32 val = 0; + u8 i = 0; + u8 j = 0; + u8 k = 0; + u8 mask = 0x03; + struct hal_mu_score_tbl *mu_sc_tbl = &bb->hal_com->bb_mu_score_tbl; + + /* + Need to do MU protect to prevent error c2h sending + this function will be return to prevent error c2h + */ + return val; + for (i = 0; i < HAL_MAX_MU_STA_NUM; i++) + for (j = 0; j < HAL_MAX_MU_SCORE_SIZE; j++) { + if (mask == 0x03) { + mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask); + mask = mask <<2; + } else if (mask == 0x0c) { + mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>2; + mask = mask <<2; + } else if (mask == 0x30) { + mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>4; + mask = mask <<2; + } else { /*(mask == 0xc0) */ + mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>6; + mask = 0x03; + k++; + } + } + return val; +} + +#ifdef HALBB_DYN_L2H_SUPPORT +u32 halbb_c2h_lowrt_rty(struct bb_info *bb, u16 len, u8 *c2h) +{ + u32 c2h_rty_cnt = 0; + struct bb_dyn_l2h_info *dyn_l2h_i = &bb->bb_dyn_l2h_i; + + c2h_rty_cnt = (*c2h) + ((*(c2h+1))<<8); + dyn_l2h_i->low_rate_rty_cnt += c2h_rty_cnt; + return 0; +} + +void halbb_fw_ctrl_rtyrpt(struct bb_info *bb, u8 rpt_rtycnt, u8 en_fw_rpt) +{ + struct bb_fw_dbg_cmn_info *fwmn_i = &bb->bb_fwdbg_i; + u32 *bb_h2c = (u32 *) fwmn_i; + u8 cmdlen = sizeof(struct bb_fw_dbg_cmn_info); + bool ret_val = false; + + fwmn_i->fw_cmn_info |= (en_fw_rpt & 0x01); + fwmn_i->fw_rty_rpt_ctrl = rpt_rtycnt; + BB_DBG(bb, DBG_FW_INFO, "FW CTRL RTYRPT: %d %d\n", fwmn_i->fw_cmn_info, fwmn_i->fw_rty_rpt_ctrl); + BB_DBG(bb, DBG_FW_INFO, "FW CMN CTRL: %x %x\n", bb_h2c[0], bb_h2c[1]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FWTRACE, HALBB_H2C_DM, bb_h2c); +} + +#endif + +/* Remove after 8852A B cut */ +/* +u32 halbb_c2h_fw_trig_tx_rpt(struct bb_info *bb, u16 len, u8 *c2h) +{ + struct bb_c2h_fw_tx_rpt *fw_tx_i = &bb->bb_fwtx_c2h_i; + bool tx_stat = c2h[0] & BIT(0); + u32 val = (u32)false; + + if (tx_stat) { + BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx done\n"); + } else { + BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx fail\n"); + } + + // PD hit enable + halbb_set_reg(bb, 0xa3c, BIT(9), 0); + halbb_set_reg(bb, 0xabc, BIT(9), 0); + + fw_tx_i->tx_done = tx_stat; + + val = (u32)true; + return val; +}*/ + +u32 halbb_c2h_fw_h2c_test(struct bb_info *bb, u16 len, u8 *c2h) +{ + u16 i; + u32 val = (u32)false; + + for (i = 0; i < len; i++) { + BB_DBG(bb, DBG_FW_INFO, "FW H2C and C2H test: %d\n", c2h[i]); + } + return val; +} + +u32 halbb_c2h_ra_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h) +{ + u32 val = 0; + u16 i; + + BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: cmdid:%d len:%d\n", cmdid, len); + BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: content ==>"); + + for (i = 0; i < len; i++) + BB_DBG(bb, DBG_FW_INFO, "%x", *(c2h+i)); + BB_DBG(bb, DBG_FW_INFO, "<== \n "); + switch(cmdid) { + case HALBB_C2HRA_STS_RPT: + val = halbb_get_fw_ra_rpt(bb, len, c2h); + break; + case HALBB_C2HRA_MU_GPTBL_RPT: + val = halbb_c2h_mu_gptbl_rpt(bb, len, c2h); + break; + case HALBB_C2HRA_TXSTS: + val = halbb_get_txsts_rpt(bb, len, c2h); + break; + default: + break; + } + return val; +} + +u32 halbb_c2h_dm_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h) +{ + u32 val = 0; + u16 i; + + BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: cmdid:%d len:%d\n", cmdid, len); + BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: content ==>"); + for (i = 0; i < len; i++) + BB_DBG(bb, DBG_FW_INFO, "%x", *(c2h+i)); + BB_DBG(bb, DBG_FW_INFO, "<== \n "); + switch(cmdid) { + case DM_C2H_FW_TEST: + val = halbb_c2h_fw_h2c_test(bb, len, c2h); + break; + case DM_C2H_FW_TRIG_TX_RPT: /* Remove after 8852A B cut */ + break; + #ifdef HALBB_DYN_L2H_SUPPORT + case DM_C2H_LOWRT_RTY: + val = halbb_c2h_lowrt_rty(bb, len, c2h); + break; + #endif + #ifdef HALBB_DIG_MCC_SUPPORT + case DM_C2H_MCC_DIG: + val = halbb_c2h_mccdm_check(bb, len, c2h); + break; + #endif + default: + break; + } + return val; +} + +u32 rtw_halbb_c2h_parsing(struct bb_info *bb, u8 classid, u8 cmdid, u16 len, u8 *c2h) +{ + u32 val = 0; + switch(classid) { + case HALBB_C2H_RUA: + break; + case HALBB_C2H_RA: + val = halbb_c2h_ra_parsing(bb, cmdid, len, c2h); + break; + case HALBB_C2H_DM: + val = halbb_c2h_dm_parsing(bb, cmdid, len, c2h); + break; + default: + break; + } + return val; +} + +u8 halbb_set_cmac_txpwr_mode(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + /* power by macid */ + return 0; +} + +u8 halbb_set_cmac_ntx_en(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 1; +} + +u8 halbb_set_cmac_path_map_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 0; +} + +u8 halbb_set_cmac_path_map_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 1; +} + +u8 halbb_set_cmac_path_map_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 2; +} + +u8 halbb_set_cmac_path_map_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 3; +} + +u8 halbb_set_cmac_antsel_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + /* antenna selection*/ + return 0; +} + +u8 halbb_set_cmac_antsel_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 0; +} + +u8 halbb_set_cmac_antsel_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 0; +} + +u8 halbb_set_cmac_antsel_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 0; +} + +u8 halbb_set_cmac_pwr_tol(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + return 0; +} + +u8 halbb_set_cmac_databw_er(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + /* 0: RU242, 1:RU106*/ + return 0; +} + +bool halbb_set_pwr_by_rate_tbl(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + struct halbb_pwr_by_rate_tbl pwr_t = {{0}}; + u8 i = 0; + enum rtw_data_rate ru_pwr_rate[PWR_TBL_NUM] = {RTW_DATA_RATE_HE_NSS1_MCS0, + RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS2, + RTW_DATA_RATE_HE_NSS1_MCS3, RTW_DATA_RATE_HE_NSS1_MCS4, + RTW_DATA_RATE_HE_NSS1_MCS5, RTW_DATA_RATE_HE_NSS1_MCS6, + RTW_DATA_RATE_HE_NSS1_MCS7, RTW_DATA_RATE_HE_NSS1_MCS8, + RTW_DATA_RATE_HE_NSS1_MCS9, RTW_DATA_RATE_HE_NSS1_MCS10, + RTW_DATA_RATE_HE_NSS1_MCS11, RTW_DATA_RATE_HE_NSS2_MCS0, + RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS2, + RTW_DATA_RATE_HE_NSS2_MCS3, RTW_DATA_RATE_HE_NSS2_MCS4, + RTW_DATA_RATE_HE_NSS2_MCS5, RTW_DATA_RATE_HE_NSS2_MCS6, + RTW_DATA_RATE_HE_NSS2_MCS7, RTW_DATA_RATE_HE_NSS2_MCS8, + RTW_DATA_RATE_HE_NSS2_MCS9, RTW_DATA_RATE_HE_NSS2_MCS10, + RTW_DATA_RATE_HE_NSS2_MCS11, RTW_DATA_RATE_HE_NSS1_MCS0, + RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS3, + RTW_DATA_RATE_HE_NSS1_MCS4, RTW_DATA_RATE_HE_NSS2_MCS0, + RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS3, + RTW_DATA_RATE_HE_NSS2_MCS4}; + u32 *pval = (u32 *)&pwr_t; + u8 cmdlen = sizeof(pwr_t); + u8 dcm = 0; + enum rtw_data_rate rate; + enum channel_width bw = phl_sta_i->chandef.bw; + u8 channel = phl_sta_i->chandef.center_ch; + s16 pwr_db = 0; + + + for (i = 0; i < PWR_TBL_NUM; i++) { + rate = ru_pwr_rate[i]; + if (i >=24) + dcm = 1; + /*rtw_hal_rf_read_pwr_table(bb->hal_com, 0, rate, bw, channel, 0, dcm, 0, &pwr_db);*/ + pwr_t.pwr_by_rate[i*2] = (u8)(pwr_db&0xff); + pwr_t.pwr_by_rate[i*2+1] = (u8)((pwr_db>>8)&0xff); + } + /* Get pwr by rate tbl from halrf */ + halbb_fill_h2c_cmd(bb, cmdlen, RUA_H2C_PWR_TBL, HALBB_H2C_RUA, pval); + return false; +} diff --git a/phl/hal_g6/phy/bb/halbb_interface.h b/phl/hal_g6/phy/bb/halbb_interface.h new file mode 100644 index 0000000..b1a2461 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_interface.h @@ -0,0 +1,216 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_INTERFACE_H__ +#define __HALBB_INTERFACE_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +/*[IO Reg]*/ + +#define BB_OFST 0x10000 + +#define HALBB_SET_CR_CMN(bb, cr, val, phy_idx) halbb_set_reg_cmn(bb, cr, cr##_M, val, phy_idx); +#define HALBB_SET_CR(bb, cr, val) halbb_set_reg(bb, cr, cr##_M, val); + +#define HALBB_GET_CR_CMN(bb, cr, val, phy_idx) halbb_get_reg_cmn(bb, cr, cr##_M, phy_idx); +#define HALBB_GET_CR(bb, cr) halbb_get_reg(bb, cr, cr##_M); + +#define halbb_get_32(bb, addr) hal_read32((bb)->hal_com, (addr | BB_OFST)) +#define halbb_get_16(bb, addr) hal_read16((bb)->hal_com, (addr | BB_OFST)) +#define halbb_get_8(bb, addr) hal_read8((bb)->hal_com, (addr | BB_OFST)) +#define halbb_set_32(bb, addr, val) hal_write32((bb)->hal_com, (addr | BB_OFST), val) +#define halbb_set_16(bb, addr, val) hal_write16((bb)->hal_com, (addr | BB_OFST), val) +#define halbb_set_8(bb, addr, val) hal_write8((bb)->hal_com, (addr | BB_OFST), val) + +#define halbb_read_mem(bb, addr, cnt, pmem) hal_read_mem((bb)->hal_com, addr, cnt, pmem) + +/*[Delay]*/ +#define halbb_delay_ms(bb, ms) _os_delay_ms(bb->hal_com->drv_priv, ms) +#define halbb_delay_us(bb, us) _os_delay_us(bb->hal_com->drv_priv, us) + +/*[Memory Access]*/ +#define halbb_mem_alloc(bb, buf_sz) _os_mem_alloc(bb->hal_com->drv_priv, buf_sz) +#define halbb_mem_free(bb, buf, buf_sz) _os_mem_free(bb->hal_com->drv_priv, (void *)buf, buf_sz) +#define halbb_mem_set(bb, buf, value, size) _os_mem_set(bb->hal_com->drv_priv, (void *)buf, value, size) +#define halbb_mem_cpy(bb, dest, src, size) _os_mem_cpy(bb->hal_com->drv_priv, (void *)dest, (void *)src, size) +#define halbb_mem_cmp(bb, dest, src, size) _os_mem_cmp(bb->hal_com->drv_priv, (void *)dest, (void *)src, size) + +/*[Timer]*/ +#ifdef HALBB_TIMER_SUPPORT +#define halbb_timer_list _os_timer +#define halbb_init_timer(bb, timer, call_back_func, context, sz_id) _os_init_timer(bb->hal_com->drv_priv, timer, call_back_func, context, sz_id) +#define halbb_set_timer(bb, timer, ms_delay) _os_set_timer(bb->hal_com->drv_priv, timer, ms_delay) +#define halbb_cancel_timer(bb, timer) _os_cancel_timer(bb->hal_com->drv_priv, timer) +#define halbb_release_timer(bb, timer) _os_release_timer(bb->hal_com->drv_priv, timer) +#else +#define halbb_timer_list u8 +#define halbb_init_timer(bb, timer, call_back_func, context, sz_id) +#define halbb_set_timer(bb, timer, ms_delay) +#define halbb_cancel_timer(bb, timer) +#define halbb_release_timer(bb, timer) +#endif + +/*[Efuse]*/ +#ifndef RTW_FLASH_98D +#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_efuse_get_info(bb->hal_com, info_type, (void *)value, size) +#else +#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_flash_get_info(bb->hal_com, info_type, (void *)value, size) +#endif +#define halbb_phy_efuse_get_info(bb, addr, size, value) rtw_hal_mac_read_phy_efuse(bb->hal_com, addr, size, value) + +/*[String]*/ +#define halbb_snprintf _os_snprintf + +/*[PwrTable]*/ +#define PWR_TBL_NUM 32 +#define NUM_HE_MCS 12 +#define NUM_DCM_MCS 4 + + +/*@--------------------------[Enum]------------------------------------------*/ +enum bb_timer_cfg_t { + BB_INIT_TIMER = 0, + BB_CANCEL_TIMER = 1, + BB_RELEASE_TIMER = 2, + BB_SET_TIMER = 3 +}; + +enum halbb_h2c_ra_cmdid { + RA_H2C_MACIDCFG = 0x0, + RA_H2C_RSSISETTING = 0x1, + RA_H2C_GET_TXSTS = 0x2, + RA_H2C_RA_ADJUST = 0x3, + RA_H2C_ADJUST_RA_MASK = 0x4, + RA_H2C_RA_D_O_TIMER = 0x5, + RA_H2C_MUCFG = 0x10, + RA_MAX_H2CCMD +}; + +enum halbb_h2c_rua_cmdid { + RUA_H2C_TABLE = 0x0, + RUA_H2C_SWGRP = 0x1, + RUA_H2C_DL_MACID = 0x2, + RUA_H2C_UL_MACID = 0x3, + RUA_H2C_CSIINFO = 0x4, + RUA_H2C_CQI = 0x5, + RUA_H2C_BBINFO = 0x6, + RUA_H2C_SEN_TBL = 0x7, + RUA_H2C_PWR_TBL = 0x8, + RUA_MAX_H2CCMD +}; + +enum halbb_h2c_classid { + HALBB_H2C_RUA = 0x0, + HALBB_H2C_RA = 0x1, + HALBB_H2C_DM = 0x2, + HALBB_MAX_H2CCMD +}; + +enum halbb_h2c_dm_cmdid { + DM_H2C_FWTRACE = 0x0, + DM_H2C_FW_TRIG_TX = 0x1, + DM_H2C_FW_HE_SIGB = 0x2, + DM_H2C_FW_H2C_TEST = 0x3, + DM_H2C_FW_EDCCA = 0x4, + DM_H2C_FW_CMW = 0x5, + DM_H2C_FW_MCC = 0x6, + DM_MAX_H2CCMD +}; + +enum halbb_c2h_classid { + HALBB_C2H_RUA = 0x0, + HALBB_C2H_RA = 0x1, + HALBB_C2H_DM = 0x2, + HALBB_MAX_C2HCMD +}; + +enum halbb_c2h_ra_cmdid { + HALBB_C2HRA_STS_RPT = 0x0, + HALBB_C2HRA_MU_GPTBL_RPT = 0x1, + HALBB_C2HRA_TXSTS = 0x2, + HALBB_MAX_C2HRACMD +}; + +enum halbb_c2h_dm_cmdid { + DM_C2H_FW_TEST = 0x0, + DM_C2H_FW_TRIG_TX_RPT = 0x1, + DM_C2H_SIGB = 0x2, + DM_C2H_LOWRT_RTY = 0x3, + DM_C2H_MCC_DIG = 0x4, + HALBB_MAX_C2HDMCMD +}; + +enum halbb_event_idx_t { + /*timer*/ + BB_EVENT_TIMER_DIG = 0, + BB_EVENT_TIMER_CFO = 1, + BB_EVENT_TIMER_ANTDIV = 2, + BB_EVENT_TIMER_TDMA_CR = 3, + BB_EVENT_TIMER_LA = 4 +}; + +enum halbb_timer_state_t { + /*timer*/ + BB_TIMER_IDLE = 0, + BB_TIMER_RUN = 1, + BB_TIMER_RELEASE = 0xff, +}; + +/*@--------------------------[Structure]-------------------------------------*/ +struct halbb_timer_info { + halbb_timer_list timer_list; + u32 cb_time; /*callback time (ms)*/ + enum halbb_event_idx_t event_idx; + enum halbb_timer_state_t timer_state; +}; + + +struct halbb_pwr_by_rate_tbl { + u8 pwr_by_rate[PWR_TBL_NUM*2]; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg, + struct halbb_timer_info *timer); +u32 halbb_get_sys_time(struct bb_info *bb); +u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr); +void halbb_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val, + enum phl_phy_idx phy_idx); +void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val); +u32 halbb_get_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, + enum phl_phy_idx phy_idx); +u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1); +bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid, + u8 classid, u32 *pval); +bool halbb_test_h2c_c2h_flow(struct bb_info *bb); + +bool halbb_check_fw_ofld(struct bb_info *bb); +bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lst_cmd); +bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val, + enum phl_phy_idx phy_idx, u8 lst_cmd); +bool halbb_fw_set_rf_reg(struct bb_info *bb, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_interface_ex.h b/phl/hal_g6/phy/bb/halbb_interface_ex.h new file mode 100644 index 0000000..d241e68 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_interface_ex.h @@ -0,0 +1,53 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_INTERFACE_EX_H__ +#define __HALBB_INTERFACE_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val); +u32 halbb_get_reg(struct bb_info *bb, u32 addr, u32 bit_mask); +u32 rtw_halbb_c2h_parsing(struct bb_info *bb, u8 classid, u8 cmdid, u16 len, u8 *c2h); +u8 halbb_set_cmac_txpwr_mode(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_ntx_en(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_path_map_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_path_map_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_path_map_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_path_map_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_antsel_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_antsel_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_antsel_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_antsel_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_pwr_tol(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +u8 halbb_set_cmac_databw_er(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); + + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_la_mode.c b/phl/hal_g6/phy/bb/halbb_la_mode.c new file mode 100644 index 0000000..0182f4d --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_la_mode.c @@ -0,0 +1,2254 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_LA_MODE_SUPPORT +#define LAMODE_ECHO_CMD 1 +#define LAMODE_MAIN 1 +#define SET_BB_TRIG_RULE 1 +#define SET_BB_DMA_FMT 1 +#define SET_MAC_CFG 1 +#define SET_MAC_TRIG 1 +#define SET_MAC_GET_BUF_RPT 1 + +#if (SET_MAC_GET_BUF_RPT) +u8 halbb_la_ptrn_chk(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + u32 i = 0, idx = 0; + u8 ptrn_match = 1; + u8 ptrn_match_num = 0; + u32 shift = 0; + u32 point_tmp = 0; + u32 mask_tmp = 0; + u32 val_tmp = 0; + u32 data_msb_tmp = 0; + + if (!la->la_ptrn_chk_en) { + BB_TRACE("la_ptrn_chk_en=%d\n", la->la_ptrn_chk_en); + return 0; + } + + for (i = 0; i < LA_CHK_PTRN_NUM; i++) { + BB_TRACE("[%d] point=%05d, chk_mask=0x%08x, chk_val=0x%x\n", + i, la->la_ptrn_chk_i[i].smp_point, + la->la_ptrn_chk_i[i].la_ptrn_chk_mask, + la->la_ptrn_chk_i[i].la_ptrn_chk_val); + } + BB_TRACE("==========================>\n"); + + for (i = 0; i < LA_CHK_PTRN_NUM; i++) { + if (la->la_ptrn_chk_i[i].la_ptrn_chk_mask == 0) + continue; + + point_tmp = la->la_ptrn_chk_i[i].smp_point; + mask_tmp = la->la_ptrn_chk_i[i].la_ptrn_chk_mask; + val_tmp = la->la_ptrn_chk_i[i].la_ptrn_chk_val; + + idx = point_tmp << 1; + data_msb_tmp = SWAP4BYTE(buf->octet[idx + 1]); + BB_TRACE("[%d] [Point:%d] %08x | %08x\n", + i, point_tmp, SWAP4BYTE(buf->octet[idx + 1]), + SWAP4BYTE(buf->octet[idx])); + + if (mask_tmp != MASKDWORD) + shift = halbb_cal_bit_shift(mask_tmp); + + if ((data_msb_tmp & mask_tmp) == (val_tmp << shift)) { + ptrn_match_num++; + BB_TRACE("pattern[%d] match\n", i); + } else { + ptrn_match &= 0; + BB_TRACE("pattern[%d] NOT match\n", i); + } + } + + if (ptrn_match_num == 0) + ptrn_match = 0; + + BB_TRACE("pattern_match=%d, ptrn_match_num=%d\n", ptrn_match, ptrn_match_num); + + if (ptrn_match) + la->la_count = 0; + + return ptrn_match; +} + +void halbb_la_rpt_buf_get(struct bb_info *bb, u16 finish_ofst, bool is_round_up) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + u8 la_ptrn_match; + u32 i = 0; + u32 addr = 0, start_addr = 0, finish_addr = 0; /* @(unit: Byte)*/ + u32 round_up_size = 0; + u32 finish_ofst_byte = 0; + u8 *la_data; + + if (la->la_mode_state != LA_STATE_GET_DLE_BUF) { + BB_WARNING("[%s]\n", __func__); + return; + } + + BB_TRACE("[%s]\n", __func__); + + /*@==== [Get LA Report] ==============================================*/ + finish_ofst_byte = ((u32)finish_ofst) << 3; + finish_addr = buf->start_pos + finish_ofst_byte; + + BB_TRACE("start_addr = ((0x%x)), end_addr = ((0x%x)), buf_size = ((0x%x))\n", + buf->start_pos, buf->end_pos, buf->buffer_size); + + if (is_round_up) { + start_addr = finish_addr; + round_up_size = buf->end_pos - start_addr; + + BB_TRACE("[Round_up:1] round_up_point=(%d)\n", finish_ofst); /*@Byte to 8Byte*/ + BB_TRACE("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n", + buf->start_pos, finish_addr, buf->end_pos); + + la->smp_number = buf->smp_number_max; + } else { + start_addr = buf->start_pos; + + BB_TRACE("[Round_up:0]\n"); + BB_TRACE("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n", + buf->start_pos, finish_addr, buf->end_pos); + + la->smp_number = DIFF_2(start_addr, finish_addr) >> 3; + } + BB_TRACE("smp_num=(%d)\n", la->smp_number); + + /*@==== [Get LA Patterns in TXFF] ====================================*/ + BB_TRACE("Dump_Start\n"); + + if (!buf->octet) + return; + + la_data = (u8 *)buf->octet; + + if (is_round_up) { + /*BB_TRACE("0x%x + 0x%x = 0x%x, 0x%x\n", round_up_size, finish_ofst_byte + 8, (round_up_size + finish_ofst_byte + 8), buf->buffer_size);*/ + rtw_hal_mac_get_buffer_data(bb->hal_com, start_addr, la_data, round_up_size, 1); + la_data += round_up_size; + } + rtw_hal_mac_get_buffer_data(bb->hal_com, buf->start_pos, la_data, finish_ofst_byte, 1); + + la_ptrn_match = halbb_la_ptrn_chk(bb); + + BB_TRACE("[Dump_End], la_ptrn_match=%d, la_count=%d\n", + la_ptrn_match, la->la_count); +} +#endif + +#if (SET_MAC_CFG) +void halbb_la_set_mac_trig_time(struct bb_info *bb, u32 trig_time, u8 *unit, u8 *unit_num) +{ + u32 ref_time = 128; + u8 time_unit_num = 0; + u8 i; + + /*mac_la_tgr_tu_sel: 0 ~ 2^[0~15] */ + /*mac_la_tgr_time_val: 0 ~ 2^7 */ + + if (trig_time > 0x400000) + trig_time = 0x400000; + + for (i = 0; i < 16; i++) { + if (trig_time <= (ref_time << i)) { + *unit = i; + break; + } + } + + *unit_num = (u8)(trig_time >> *unit); + + BB_DBG(bb, DBG_DBG_API, "2. [Set Trig-Time] Time=%d * unit=2^%d us\n", + *unit_num, *unit); +} + +bool halbb_la_mac_cfg_buf(struct bb_info *bb, enum la_buff_mode_t mode) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + struct la_string_info *buf = &la->la_string_i; + u32 addr_start = 0; + u32 addr_end = 0; + u32 buf_size_tmp = 0; + + switch (bb->ic_type) { + case BB_RTL8852A: + if (mode == LA_BUFF_256K) + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + else if(mode == LA_BUFF_192K) + buf->buffer_size = 0x30000; + else + buf->buffer_size = 0; + break; + case BB_RTL8852B: + if (mode == LA_BUFF_128K && bb->hal_com->cv == CAV) + buf->buffer_size = 0x20000; /*2^17=(2^7)*(2^10)=128K Byte*/ + else if (mode == LA_BUFF_64K && bb->hal_com->cv >= CBV) + buf->buffer_size = 0x10000; /*2^16=(2^6)*(2^10)=64K Byte*/ + else + buf->buffer_size = 0; + break; + case BB_RTL8852C: + if (mode == LA_BUFF_256K) + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + else if (mode == LA_BUFF_128K) + buf->buffer_size = 0x20000; /*2^17=(2^7)*(2^10)=128K Byte*/ + else + buf->buffer_size = 0; + break; + case BB_RTL8192XB: + if (mode == LA_BUFF_256K) + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + else + buf->buffer_size = 0; + break; + default: + BB_WARNING("[%s] IC\n", __func__); + buf->buffer_size = 0; + break; + } + + if (buf->buffer_size == 0) { + BB_WARNING("[%s] Buf=0\n", __func__); + return false; + } + + rtw_hal_mac_lamode_cfg_buf(bb->hal_com, cfg->mac_la_buf_sel, &addr_start, &addr_end); + + buf->start_pos = addr_start; + buf->end_pos = addr_end; + buf_size_tmp = buf->end_pos - buf->start_pos; + + if (buf_size_tmp != buf->buffer_size) { + BB_WARNING("buf_size_tmp=0x%x, buffer_size=0x%x\n", + buf_size_tmp, buf->buffer_size); + return false; + } + buf->smp_number_max = buf->buffer_size >> 3; + + BB_TRACE("addr=[0x%x ~ 0x%x], buf_size=(%d K), smp_num_max=(%d)\n", + buf->start_pos, buf->end_pos, (buf->buffer_size >> 10), + buf->smp_number_max); + return true; +} + +void halbb_la_mac_cfg_buf_default(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + enum la_buff_mode_t mode; + + switch (bb->ic_type) { + case BB_RTL8852A: + mode = LA_BUFF_256K; + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + break; + case BB_RTL8852B: + if (bb->hal_com->cv == CAV) { + mode = LA_BUFF_128K; + buf->buffer_size = 0x20000; /*2^17=(2^7)*(2^10)=128K Byte*/ + } else { + mode = LA_BUFF_64K; + buf->buffer_size = 0x10000; /*2^16=(2^6)*(2^10)=64K Byte*/ + } + break; + case BB_RTL8852C: + mode = LA_BUFF_256K; + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + break; + case BB_RTL8192XB: + mode = LA_BUFF_256K; + buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/ + break; + default: + BB_WARNING("[%s]\n", __func__); + } + la->la_mac_cfg_i.mac_la_buf_sel = mode; + //BB_TRACE("Auto Init MAC BUF CR, mode=(%d)K\n", 64 * (mode + 1)); + + buf->smp_number_max = buf->buffer_size >> 3; +} + +void halbb_la_mac_cfg_cmn(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + u8 t_unit = 0, t_unit_num = 0; + + cfg->mac_la_en = (cfg->mac_la_buf_sel == LA_BUF_DISABLE) ? 0 : 1; + + halbb_la_set_mac_trig_time(bb, cfg->la_trigger_time, &t_unit, &t_unit_num); + + rtw_hal_mac_lamode_cfg(bb->hal_com, cfg->mac_la_en, cfg->mac_la_restart_en, + cfg->mac_la_timeout_en, cfg->mac_la_timeout_val, + cfg->mac_la_data_loss_imr, t_unit, t_unit_num); + +} + +void halbb_la_mac_init(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + + /*[MAC Buf]*/ + //cfg->mac_la_buf_sel = LA_BUFF_256K; + //halbb_la_mac_cfg_buf(bb, cfg->mac_la_buf_sel); + + /*[MAC Common]*/ + halbb_la_mac_cfg_cmn(bb); +} + +#endif + +#if SET_MAC_TRIG +void halbb_la_mac_set_adv_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i; + + halbb_mem_set(bb, trig_mac, 0, sizeof(struct la_trig_mac_info)); +} + +void halbb_la_mac_set_trig(struct bb_info *bb, bool mac_trig_en) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i; + struct bb_la_cr_info *cr = &la->bb_la_cr_i; + + BB_TRACE(" *[%s]\n", __func__); + + if (!mac_trig_en) { + /*MAC_AND0*/ + halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, 0); + /*MAC_AND1*/ + halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, 0); + /*MAC_AND2*/ + halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m, 0); + return; + } + + halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, + trig_mac->la_mac_and0_en); + halbb_set_reg(bb, cr->la_mac_and0_sel, cr->la_mac_and0_sel_m, + trig_mac->la_mac_and0_sel); + halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(16), 0); + if (trig_mac->la_mac_and0_sel == 1) + halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(22), + trig_mac->la_mac_and0_mac_sel); + else if (trig_mac->la_mac_and0_sel == 2) + halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(23), + trig_mac->la_mac_and0_mac_sel); + halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, + trig_mac->la_mac_and1_en); + halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m, + trig_mac->la_mac_and2_en); + halbb_set_reg(bb, cr->la_mac_and2_frame_sel, + cr->la_mac_and2_frame_sel_m, + trig_mac->la_mac_and2_frame_sel); +} +#endif + +#if SET_BB_DMA_FMT +void halbb_la_bb_set_dma_type(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + struct bb_la_cr_info *cr = &la->bb_la_cr_i; + u32 la_en = 1; + u32 r_dma_rdrdy = 0; + + if (la->la_smp_rate == LA_SMP_CLK_160) { + dma->dma_a_ck160_dly_en = 1; + dma->dma_b_ck160_dly_en = 1; + dma->dma_c_ck160_dly_en = 1; + dma->dma_d_ck160_dly_en = 1; + } else { + dma->dma_a_ck160_dly_en = 0; + dma->dma_b_ck160_dly_en = 0; + dma->dma_c_ck160_dly_en = 0; + dma->dma_d_ck160_dly_en = 0; + } + + halbb_set_reg(bb, cr->la_en, cr->la_en_m, la_en); + halbb_set_reg(bb, cr->dma_dbgport_base_n, cr->dma_dbgport_base_n_m, + dma->dma_dbgport_base_n); + halbb_set_reg(bb, cr->dma_a_path_sel, cr->dma_a_path_sel_m, + dma->dma_a_path_sel); + halbb_set_reg(bb, cr->dma_b_path_sel, cr->dma_b_path_sel_m, + dma->dma_b_path_sel); + halbb_set_reg(bb, cr->dma_c_path_sel, cr->dma_c_path_sel_m, + dma->dma_c_path_sel); + halbb_set_reg(bb, cr->dma_d_path_sel, cr->dma_d_path_sel_m, + dma->dma_d_path_sel); + halbb_set_reg(bb, cr->dma_a_src_sel, cr->dma_a_src_sel_m, + dma->dma_a_src_sel); + halbb_set_reg(bb, cr->dma_b_src_sel, cr->dma_b_src_sel_m, + dma->dma_b_src_sel); + halbb_set_reg(bb, cr->dma_c_src_sel, cr->dma_c_src_sel_m, + dma->dma_c_src_sel); + halbb_set_reg(bb, cr->dma_d_src_sel, cr->dma_d_src_sel_m, + dma->dma_d_src_sel); + + BB_TRACE("DMA_hdr[63:60]=[%d, %d, %d, %d]\n", + dma->dma_hdr_sel_63, dma->dma_hdr_sel_62, + dma->dma_hdr_sel_61, dma->dma_hdr_sel_60); + + halbb_set_reg(bb, cr->dma_hdr_sel_63, cr->dma_hdr_sel_63_m, + dma->dma_hdr_sel_63); + halbb_set_reg(bb, cr->dma_hdr_sel_62, cr->dma_hdr_sel_62_m, + dma->dma_hdr_sel_62); + halbb_set_reg(bb, cr->dma_hdr_sel_61, cr->dma_hdr_sel_61_m, + dma->dma_hdr_sel_61); + halbb_set_reg(bb, cr->dma_hdr_sel_60, cr->dma_hdr_sel_60_m, + dma->dma_hdr_sel_60); + halbb_set_reg(bb, cr->dma_a_ck160_dly_en, cr->dma_a_ck160_dly_en_m, + dma->dma_a_ck160_dly_en); + halbb_set_reg(bb, cr->dma_b_ck160_dly_en, cr->dma_b_ck160_dly_en_m, + dma->dma_b_ck160_dly_en); + halbb_set_reg(bb, cr->dma_dbgport_phy_sel, cr->dma_dbgport_phy_sel_m, + dma->dma_dbgport_phy_sel); + halbb_set_reg(bb, cr->dma_data_type, cr->dma_data_type_m, + dma->dma_data_type); + halbb_set_reg(bb, cr->r_dma_rdrdy, cr->r_dma_rdrdy_m, r_dma_rdrdy); +} + +void halbb_la_bb_set_dma_type_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + + dma->dma_dbgport_base_n = 31; + dma->dma_a_path_sel = 0; + dma->dma_b_path_sel = 1; + dma->dma_c_path_sel = 2; + dma->dma_d_path_sel = 3; + dma->dma_a_src_sel = 3; + dma->dma_b_src_sel = 3; + dma->dma_c_src_sel = 3; + dma->dma_d_src_sel = 3; + dma->dma_dbgport_phy_sel = 0; + dma->dma_hdr_sel_63 = LA_HDR_CCA; + dma->dma_hdr_sel_62 = LA_HDR_AGC_RDY; + dma->dma_hdr_sel_61 = LA_HDR_RXHE_FULLBAND; + dma->dma_hdr_sel_60 = LA_HDR_CRC_OK; + dma->dma_data_type = DMA01_NRML_2s_12b; +} + +#endif + +#if SET_BB_TRIG_RULE +void halbb_la_bb_set_adv_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + + halbb_mem_set(bb, adv, 0, sizeof(struct la_adv_trig_info)); +} + +void halbb_la_bb_set_cmn_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + + la->la_trigger_cnt = 0; + la->la_dbg_port = 0x10205; + la->la_trigger_edge = LA_P_EDGE; + la->la_smp_rate = LA_SMP_CLK_80; + la->la_mac_cfg_i.la_trigger_time = 404; + la->la_polling_cnt = 20; + la->la_and0_disable = true; +} + +void halbb_la_bb_set_re_trig_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_re_trig_info *re_trig = &la->la_re_trig_i; + + halbb_mem_set(bb, re_trig, 0, sizeof(struct la_re_trig_info)); +} + +void halbb_la_bb_set_re_trig(struct bb_info *bb, bool re_trig_en) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_re_trig_info *re_trig = &la->la_re_trig_i; + struct rtw_hal_com_t *hal_i = bb->hal_com; + struct bb_la_cr_info *cr = &la->bb_la_cr_i; + + if (!re_trig_en) { + halbb_set_reg(bb, cr->la_re_and1_sel, + cr->la_re_and1_sel_m, 0);/*1b'1*/ + halbb_set_reg(bb, cr->la_re_and1_inv, + cr->la_re_and1_inv_m, 1); + return; + } + + halbb_set_reg(bb, cr->la_re_trig_edge, cr->la_re_trig_edge_m, + re_trig->la_re_trig_edge); + halbb_set_reg(bb, cr->la_re_and1_sel, cr->la_re_and1_sel_m, + re_trig->la_re_and0_sel); + if (re_trig->la_re_and0_sel == 0xf) + halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m, + re_trig->la_re_and0_val); + else + halbb_set_reg(bb, cr->la_re_and1_val, cr->la_re_and1_val_m, + re_trig->la_re_and0_val); + halbb_set_reg(bb, cr->la_re_and1_inv, cr->la_re_and1_inv_m, + re_trig->la_re_and0_inv); +} +void halbb_la_bb_set_trig(struct bb_info *bb, bool and0_trig_disable, bool adv_trig_en, bool not_stop_trig_en) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + struct bb_la_cr_info *cr = &la->bb_la_cr_i; + u32 trig_sel = 0; + + BB_TRACE(" {and0_trig_disable, adv_trig, not_stop_trig} = {%d, %d, %d}\n", + and0_trig_disable, adv_trig_en, not_stop_trig_en); + + /*===== [And-0 Trigger] ==============================================*/ + if (and0_trig_disable) { + halbb_set_reg(bb, cr->and0_trig_disable, + cr->and0_trig_disable_m, 1);/*disable=1*/ + } else { + if (not_stop_trig_en) + trig_sel = 0; /*set to unchanged BB debug port bit*/ + else + trig_sel = la->la_and0_bit_sel; + + halbb_set_reg(bb, cr->and0_trig_disable, + cr->and0_trig_disable_m, 0); /*disable=0*/ + halbb_set_reg(bb, cr->la_and0_bit_sel, cr->la_and0_bit_sel_m, + trig_sel); /*debug port bit*/ + } + + BB_TRACE(" *Set dbg_port[BIT] = %d\n", trig_sel); + + /*===== [And-1~7 Trigger] ============================================*/ + if (!adv_trig_en) { /*normal LA mode & back to default*/ + /*AND1*/ + halbb_set_reg(bb, cr->la_and1_mask, cr->la_and1_mask_m, 0); + /*AND2*/ + halbb_set_reg(bb, cr->la_and2_en, cr->la_and2_en_m, 0); + /*AND3*/ + halbb_set_reg(bb, cr->la_and3_en, cr->la_and3_en_m, 0); + /*AND4*/ + halbb_set_reg(bb, cr->la_and4_en, cr->la_and4_en_m, 0); + /*AND5*/ + halbb_set_reg(bb, cr->la_and5_sel, cr->la_and5_sel_m, 0); + /*AND6*/ + halbb_set_reg(bb, cr->la_and6_sel, cr->la_and6_sel_m, 0); + /*AND7*/ + halbb_set_reg(bb, cr->la_and7_sel, cr->la_and7_sel_m, 0); + return; + } + /*AND1*/ + halbb_set_reg(bb, cr->la_and1_mask, cr->la_and1_mask_m, + adv->la_and1_mask); + halbb_set_reg(bb, cr->la_and1_inv, cr->la_and1_inv_m, adv->la_and1_inv); + halbb_set_reg(bb, cr->la_and1_val, cr->la_and1_val_m, adv->la_and1_val); + /*AND2*/ + halbb_set_reg(bb, cr->la_and2_en, cr->la_and2_en_m, adv->la_and2_en); + halbb_set_reg(bb, cr->la_and2_inv, cr->la_and2_inv_m, adv->la_and2_inv); + halbb_set_reg(bb, cr->la_and2_val, cr->la_and2_val_m, adv->la_and2_val); + halbb_set_reg(bb, cr->la_and2_mask, cr->la_and2_mask_m, + adv->la_and2_mask); + halbb_set_reg(bb, cr->la_and2_sign, cr->la_and2_sign_m, + adv->la_and2_sign); + /*AND3*/ + halbb_set_reg(bb, cr->la_and3_en, cr->la_and3_en_m, adv->la_and3_en); + halbb_set_reg(bb, cr->la_and3_inv, cr->la_and3_inv_m, adv->la_and3_inv); + halbb_set_reg(bb, cr->la_and3_val, cr->la_and3_val_m, adv->la_and3_val); + halbb_set_reg(bb, cr->la_and3_mask, cr->la_and3_mask_m, + adv->la_and3_mask); + halbb_set_reg(bb, cr->la_and3_sign, cr->la_and3_sign_m, + adv->la_and3_sign); + /*AND4*/ + halbb_set_reg(bb, cr->la_and4_en, cr->la_and4_en_m, adv->la_and4_en); + halbb_set_reg(bb, cr->la_and4_inv, cr->la_and4_inv_m, adv->la_and4_inv); + halbb_set_reg(bb, cr->la_and4_rate, cr->la_and4_rate_m, + adv->la_and4_rate); + /*AND5*/ + halbb_set_reg(bb, cr->la_and5_sel, cr->la_and5_sel_m, adv->la_and5_sel); + halbb_set_reg(bb, cr->la_and5_inv, cr->la_and5_inv_m, adv->la_and5_inv); + if (adv->la_and5_sel == 0xf) + halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m, + adv->la_and5_val); + else + halbb_set_reg(bb, cr->la_and5_val, cr->la_and5_val_m, + adv->la_and5_val); + + /*AND6*/ + halbb_set_reg(bb, cr->la_and6_sel, cr->la_and6_sel_m, adv->la_and6_sel); + halbb_set_reg(bb, cr->la_and6_inv, cr->la_and6_inv_m, adv->la_and6_inv); + if (adv->la_and6_sel == 0xf) + halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m, + adv->la_and6_val); + else + halbb_set_reg(bb, cr->la_and6_val, cr->la_and6_val_m, + adv->la_and6_val); + + /*AND7*/ + halbb_set_reg(bb, cr->la_and7_sel, cr->la_and7_sel_m, adv->la_and7_sel); + halbb_set_reg(bb, cr->la_and7_inv, cr->la_and7_inv_m, adv->la_and7_inv); + if (adv->la_and7_sel == 0xf) + halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m, + adv->la_and7_val); + else + halbb_set_reg(bb, cr->la_and7_val, cr->la_and7_val_m, + adv->la_and7_val); +} + +void halbb_la_bb_set_dbg_port(struct bb_info *bb, bool not_stop_trig_en) +{ + + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + u32 trig_sel = la->la_and0_bit_sel; + u32 dbg_port = la->la_dbg_port; + + /*===== [And-0 Trigger] ====================*/ + /*set to unchanged BB debug port*/ + if (not_stop_trig_en) { + dbg_port = 0xf; + trig_sel = 0; + BB_TRACE("[BB Setting] not stop trigger!\n"); + } + + if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + halbb_set_bb_dbg_port_ip(bb, (dbg_port & 0xff0000) >> 16); + halbb_set_bb_dbg_port(bb, dbg_port & 0xffff); + BB_TRACE(" *Set dbg_port=(0x%x)\n", dbg_port); + } else { + dbg_port = halbb_get_bb_dbg_port_idx(bb); + BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port); + } +} + +void halbb_la_bb_set_general(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + struct bb_la_cr_info *cr = &la->bb_la_cr_i; + u32 rdrdy_3_phase_en = 0; + u32 la_top_trig = 1; + + BB_TRACE("3. [BB Setting] Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n", + (la->la_trigger_edge == LA_P_EDGE) ? "P" : "N", + 80 >> la->la_smp_rate, dma->dma_data_type); + + rdrdy_3_phase_en = (dma->dma_data_type == DMA13_MPHS_1s_3p_10b) ? 1 : 0; + + halbb_set_reg(bb, cr->la_trigger_edge, cr->la_trigger_edge_m, + la->la_trigger_edge); + halbb_set_reg(bb, cr->rdrdy_3_phase_en, cr->rdrdy_3_phase_en_m, + rdrdy_3_phase_en); + halbb_set_reg(bb, cr->la_smp_rate, cr->la_smp_rate_m, la->la_smp_rate); + halbb_set_reg(bb, cr->la_trigger_cnt, cr->la_trigger_cnt_m, + la->la_trigger_cnt); + halbb_set_reg(bb, cr->la_clk_en, cr->la_clk_en_m, la_top_trig); +} + +#endif + +#if LAMODE_MAIN +void +halbb_la_drv_buf_release(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + + if (buf->length != 0 && buf->octet) { + halbb_mem_free(bb, buf->octet, buf->buffer_size); + buf->length = 0; + } +} + +bool +halbb_la_drv_buf_allocate(struct bb_info *bb) +{ + + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + bool ret = true; + + BB_TRACE("[LA mode BufferAllocate]\n"); + + if (buf->length == 0) { + buf->octet = (u32 *)halbb_mem_alloc(bb, buf->buffer_size); + + if (!buf->octet) + ret = false; + + if (ret) + buf->length = buf->buffer_size; + } + + return ret; +} + +void halbb_la_stop(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + + la->la_mode_state = LA_STATE_IDLE; +} + +void halbb_la_main(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + u8 mac_rpt_state = LA_HW_IDLE; + u32 mac_trig_fail; + u8 tmp_u1b = 0; + u8 i = 0; + u16 finish_ofst = 0; + bool round_up = 0; + bool loss_data; + + if (la->la_mode_state != LA_STATE_MAIN) { + halbb_la_stop(bb); + BB_WARNING("[%s]\n", __func__); + } + + BB_TRACE("1. [BB Setting] dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Bit_Sel = ((0x%x)), Dma_type = ((%d))\n", + la->la_dbg_port, la->la_trigger_edge, + la->la_smp_rate, la->la_and0_bit_sel, dma->dma_data_type); + + halbb_la_bb_set_general(bb); + halbb_la_bb_set_dma_type(bb); + halbb_la_bb_set_dbg_port(bb, la->not_stop_trig); + halbb_la_bb_set_trig(bb, la->la_and0_disable, + la->adv_trig_i.adv_trig_en, la->not_stop_trig); + halbb_la_bb_set_re_trig(bb, la->la_re_trig_i.re_trig_en); + halbb_la_mac_set_trig(bb, la->la_trig_mac_i.la_mac_trig_en); + + halbb_la_mac_cfg_cmn(bb); + + if (la->not_stop_trig) { + halbb_delay_ms(bb, 100); + halbb_la_bb_set_dbg_port(bb, false); + } + + mac_trig_fail = rtw_hal_mac_lamode_trig(bb->hal_com, 1); + + if (!mac_trig_fail) { + do { /*Polling time always use 100ms, when it exceed 2s, break loop*/ + rtw_hal_mac_get_lamode_st(bb->hal_com, (u8 *)&mac_rpt_state, + &finish_ofst, &round_up, + &loss_data); + + BB_TRACE("[%d] rpt=((0x%x)), finish_ofst =((%d)), round_up =((%d)) \n", i, mac_rpt_state, finish_ofst, round_up); + + if (mac_rpt_state == LA_HW_RE_START) { + BB_TRACE("[Restart]\n"); + break; + } else if (mac_rpt_state == LA_HW_FINISH_STOP) { + BB_TRACE("[LA Query OK]\n"); + break; + } else if (mac_rpt_state == LA_HW_START) { + halbb_delay_ms(bb, 100); + i++; + continue; + } else if (mac_rpt_state == LA_HW_FINISH_TIMEOUT) { + BB_TRACE("[LA HW timeout]\n"); + break; + } else { /*LA_HW_IDLE)*/ + break; + } + } while (i < la->la_polling_cnt); + + if (mac_rpt_state == LA_HW_FINISH_STOP) { + la->la_mode_state = LA_STATE_GET_DLE_BUF; + halbb_la_rpt_buf_get(bb, finish_ofst, round_up); + } else if (mac_rpt_state == LA_HW_RE_START) { + la->la_mode_state = LA_STATE_WAIT_RESTART; + la->la_count = 0; + return; + } else { + BB_TRACE("[Polling Fail]\n"); + } + } + + halbb_la_stop(bb); + + BB_TRACE("[LA mode] la_count = ((%d))\n", la->la_count); + if (la->la_count <= 1) { + BB_TRACE("LA Dump finished ---------->\n\n\n"); + halbb_release_bb_dbg_port(bb); + } else { + la->la_count--; + BB_TRACE("LA Dump more ---------->\n\n\n"); + + la->la_timer_i.cb_time = 500; + halbb_cfg_timers(bb, BB_SET_TIMER, &la->la_timer_i); + } +} + +void halbb_la_re_trig_watchdog(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + + if (la->la_mode_state != LA_STATE_WAIT_RESTART) { + return; + } + la->la_re_trig_i.re_trig_wait_cnt++; + BB_TRACE("re_trig_wait_cnt=(%d)\n", la->la_re_trig_i.re_trig_wait_cnt); + + la->la_mode_state = LA_STATE_MAIN; + halbb_la_main(bb); +} + +void halbb_la_run(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + bool is_set_success = true; + + BB_TRACE("[%s] LA_State=(%d), mode=%d\n", __func__, la->la_mode_state, la->la_run_mode); + + if (!la->la_mac_cfg_i.mac_alloc_success) { + la->la_mac_cfg_i.mac_alloc_success = halbb_la_mac_cfg_buf(bb, la->la_mac_cfg_i.mac_la_buf_sel); + if (!la->la_mac_cfg_i.mac_alloc_success) { + BB_WARNING("MAC BUF CR set fail)\n"); + return; + } + } + + if (la->la_mode_state != LA_STATE_IDLE) { + halbb_la_stop(bb); + return; + } + + if (buf->length == 0) + is_set_success = halbb_la_drv_buf_allocate(bb); + + if (!is_set_success) { + BB_WARNING("LA_BUf_alloc fail)\n"); + return; + } + + halbb_mem_set(bb, buf->octet, 0, buf->buffer_size); + + la->la_re_trig_i.re_trig_wait_cnt = 0; + la->la_mode_state = LA_STATE_MAIN; + halbb_la_main(bb); +} + +void halbb_la_deinit(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + + halbb_la_stop(bb); + halbb_la_drv_buf_release(bb); +} + +void halbb_la_reset(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *la_string = &la->la_string_i; + + la->la_mode_state = LA_STATE_IDLE; + la->la_print_i.is_la_print = false; + la->not_stop_trig = false; + la->la_and0_bit_sel = 0; + + halbb_la_bb_set_cmn_reset(bb); + halbb_la_bb_set_dma_type_reset(bb); + halbb_la_bb_set_adv_reset(bb); + halbb_la_mac_set_adv_reset(bb); + halbb_la_bb_set_re_trig_reset(bb); + + halbb_la_mac_init(bb); +} + +void halbb_la_init(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_string_info *buf = &la->la_string_i; + + la->la_ptrn_chk_en = false; + la->la_mac_cfg_i.mac_alloc_success = false; + la->la_count_max = 1; + buf->length = 0; + halbb_la_reset(bb); + halbb_mem_set(bb, la->la_ptrn_chk_i, 0, sizeof(struct la_ptrn_chk_info) * LA_CHK_PTRN_NUM); + halbb_la_mac_cfg_buf_default(bb); +} + +void halbb_cr_cfg_la_init(struct bb_info *bb) +{ + struct bb_la_cr_info *cr = &bb->bb_cmn_hooker->bb_la_mode_i.bb_la_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->la_clk_en = LA_CKEN_A; + cr->la_clk_en_m = LA_CKEN_A_M; + cr->la_en = LA_EN_A; + cr->la_en_m = LA_EN_A_M; + cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_A; + cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_A_M; + cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_A; + cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_A_M; + cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_A; + cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_A_M; + cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_A; + cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_A_M; + cr->dma_d_path_sel = LA_TYPED_PATH_SEL_A; + cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_A_M; + cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_A; + cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_A_M; + cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_A; + cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_A_M; + cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_A; + cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_A_M; + cr->dma_d_src_sel = LA_TYPED_SRC_SEL_A; + cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_A_M; + cr->la_smp_rate = LA_SMP_RT_SEL_A; + cr->la_smp_rate_m = LA_SMP_RT_SEL_A_M; + cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_A; + cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_A_M; + cr->la_trigger_edge = LA_EDGE_SEL_A; + cr->la_trigger_edge_m = LA_EDGE_SEL_A_M; + cr->dma_hdr_sel_63 = LA_HDR_SEL_63_A; + cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_A_M; + cr->dma_hdr_sel_62 = LA_HDR_SEL_62_A; + cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_A_M; + cr->dma_hdr_sel_61 = LA_HDR_SEL_61_A; + cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_A_M; + cr->dma_hdr_sel_60 = LA_HDR_SEL_60_A; + cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_A_M; + cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_A; + cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_A_M; + cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_A; + cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_A_M; + cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_A; + cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_A_M; + cr->dma_data_type = LA_DATA_A; + cr->dma_data_type_m = LA_DATA_A_M; + cr->r_dma_rdrdy = LA_RDRDY_A; + cr->r_dma_rdrdy_m= LA_RDRDY_A_M; + cr->la_and0_bit_sel = LA_TRIG_A; + cr->la_and0_bit_sel_m = LA_TRIG_A_M; + cr->la_trigger_cnt = LA_TRIG_CNT_A; + cr->la_trigger_cnt_m = LA_TRIG_CNT_A_M; + cr->and0_trig_disable = LA_TRIG_NEW_ONLY_A; + cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_A_M; + cr->la_and1_inv = LA_TRIG_AND1_INV_A; + cr->la_and1_inv_m = LA_TRIG_AND1_INV_A_M; + cr->la_and2_en = LA_TRIG_AND2_EN_A; + cr->la_and2_en_m = LA_TRIG_AND2_EN_A_M; + cr->la_and2_inv = LA_TRIG_AND2_INV_A; + cr->la_and2_inv_m = LA_TRIG_AND2_INV_A_M; + cr->la_and3_en = LA_TRIG_AND3_EN_A; + cr->la_and3_en_m = LA_TRIG_AND3_EN_A_M; + cr->la_and3_inv = LA_TRIG_AND3_INV_A; + cr->la_and3_inv_m = LA_TRIG_AND3_INV_A_M; + cr->la_and4_en = LA_TRIG_AND4_EN_A; + cr->la_and4_en_m = LA_TRIG_AND4_EN_A_M; + cr->la_and4_rate = LA_TRIG_AND4_VAL_A; + cr->la_and4_rate_m = LA_TRIG_AND4_VAL_A_M; + cr->la_and4_inv = LA_TRIG_AND4_INV_A; + cr->la_and4_inv_m = LA_TRIG_AND4_INV_A_M; + cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_A; + cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_A_M; + cr->la_and1_val = LA_TRIG_AND1_VAL_A; + cr->la_and1_val_m = LA_TRIG_AND1_VAL_A_M; + cr->la_and2_mask = LA_TRIG_AND2_MASK_A; + cr->la_and2_mask_m = LA_TRIG_AND2_MASK_A_M; + cr->la_and2_val = LA_TRIG_AND2_VAL_A; + cr->la_and2_val_m = LA_TRIG_AND2_VAL_A_M; + cr->la_and3_mask = LA_TRIG_AND3_MASK_A; + cr->la_and3_mask_m = LA_TRIG_AND3_MASK_A_M; + cr->la_and3_val = LA_TRIG_AND3_VAL_A; + cr->la_and3_val_m = LA_TRIG_AND3_VAL_A_M; + cr->la_and5_sel = LA_TRIG_AND5_A; + cr->la_and5_sel_m = LA_TRIG_AND5_A_M; + cr->la_and5_val = LA_TRIG_AND5_VAL_A; + cr->la_and5_val_m = LA_TRIG_AND5_VAL_A_M; + cr->la_and5_inv = LA_TRIG_AND5_INV_A; + cr->la_and5_inv_m = LA_TRIG_AND5_INV_A_M; + cr->la_and6_sel = LA_TRIG_AND6_A; + cr->la_and6_sel_m = LA_TRIG_AND6_A_M; + cr->la_and6_val = LA_TRIG_AND6_VAL_A; + cr->la_and6_val_m = LA_TRIG_AND6_VAL_A_M; + cr->la_and6_inv = LA_TRIG_AND6_INV_A; + cr->la_and6_inv_m = LA_TRIG_AND6_INV_A_M; + cr->la_and7_sel = LA_TRIG_AND7_A; + cr->la_and7_sel_m = LA_TRIG_AND7_A_M; + cr->la_and7_val = LA_TRIG_AND7_VAL_A; + cr->la_and7_val_m = LA_TRIG_AND7_VAL_A_M; + cr->la_and7_inv = LA_TRIG_AND7_INV_A; + cr->la_and7_inv_m = LA_TRIG_AND7_INV_A_M; + cr->la_brk_sel = BRK_R_BRK_SEL_FOR_CNT_A; + cr->la_brk_sel_m =BRK_R_BRK_SEL_FOR_CNT_A_M; + cr->la_mac_and1_en = LA_M_AND1_EN_A; + cr->la_mac_and1_en_m = LA_M_AND1_EN_A_M; + cr->la_mac_and2_en = LA_M_AND2_EN_A; + cr->la_mac_and2_en_m = LA_M_AND2_EN_A_M; + cr->la_mac_and2_frame_sel = TARGET_FRAME_TYPE_A; + cr->la_mac_and2_frame_sel_m =TARGET_FRAME_TYPE_A_M; + cr->la_mac_and0_sel = LA_M_AND0_SEL_A; + cr->la_mac_and0_sel_m = LA_M_AND0_SEL_A_M; + cr->la_mac_and0_en = LA_M_AND0_EN_A; + cr->la_mac_and0_en_m = LA_M_AND0_EN_A_M; + cr->la_mac_and0_mac_sel = INTF_R_MAC_SEL_A; + cr->la_mac_and0_mac_sel_m = INTF_R_MAC_SEL_A_M; + cr->la_and2_sign = LA_SIGN2_A; + cr->la_and2_sign_m = LA_SIGN2_A_M; + cr->la_and3_sign = LA_SIGN3_A; + cr->la_and3_sign_m = LA_SIGN3_A_M; + cr->la_re_trig_edge = LA_RE_INIT_POLARITY_A; + cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_A_M; + cr->la_re_and1_sel = LA_RE_INIT_AND1_A; + cr->la_re_and1_sel_m = LA_RE_INIT_AND1_A_M; + cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_A; + cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_A_M; + cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_A; + cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->la_clk_en = LA_CKEN_C; + cr->la_clk_en_m = LA_CKEN_C_M; + cr->la_en = LA_EN_C; + cr->la_en_m = LA_EN_C_M; + cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_C; + cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_C_M; + cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_C; + cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_C_M; + cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_C; + cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_C_M; + cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_C; + cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_C_M; + cr->dma_d_path_sel = LA_TYPED_PATH_SEL_C; + cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_C_M; + cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_C; + cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_C_M; + cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_C; + cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_C_M; + cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_C; + cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_C_M; + cr->dma_d_src_sel = LA_TYPED_SRC_SEL_C; + cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_C_M; + cr->la_smp_rate = LA_SMP_RT_SEL_C; + cr->la_smp_rate_m = LA_SMP_RT_SEL_C_M; + cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_C; + cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_C_M; + cr->la_trigger_edge = LA_EDGE_SEL_C; + cr->la_trigger_edge_m = LA_EDGE_SEL_C_M; + cr->dma_hdr_sel_63 = LA_HDR_SEL_63_C; + cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_C_M; + cr->dma_hdr_sel_62 = LA_HDR_SEL_62_C; + cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_C_M; + cr->dma_hdr_sel_61 = LA_HDR_SEL_61_C; + cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_C_M; + cr->dma_hdr_sel_60 = LA_HDR_SEL_60_C; + cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_C_M; + cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_C; + cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_C_M; + cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_C; + cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_C_M; + cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_C; + cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_C_M; + cr->dma_data_type = LA_DATA_C; + cr->dma_data_type_m = LA_DATA_C_M; + cr->r_dma_rdrdy = LA_RDRDY_C; + cr->r_dma_rdrdy_m= LA_RDRDY_C_M; + cr->la_and0_bit_sel = LA_TRIG_C; + cr->la_and0_bit_sel_m = LA_TRIG_C_M; + cr->la_trigger_cnt = LA_TRIG_CNT_C; + cr->la_trigger_cnt_m = LA_TRIG_CNT_C_M; + cr->and0_trig_disable = LA_TRIG_NEW_ONLY_C; + cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_C_M; + cr->la_and1_inv = LA_TRIG_AND1_INV_C; + cr->la_and1_inv_m = LA_TRIG_AND1_INV_C_M; + cr->la_and2_en = LA_TRIG_AND2_EN_C; + cr->la_and2_en_m = LA_TRIG_AND2_EN_C_M; + cr->la_and2_inv = LA_TRIG_AND2_INV_C; + cr->la_and2_inv_m = LA_TRIG_AND2_INV_C_M; + cr->la_and3_en = LA_TRIG_AND3_EN_C; + cr->la_and3_en_m = LA_TRIG_AND3_EN_C_M; + cr->la_and3_inv = LA_TRIG_AND3_INV_C; + cr->la_and3_inv_m = LA_TRIG_AND3_INV_C_M; + cr->la_and4_en = LA_TRIG_AND4_EN_C; + cr->la_and4_en_m = LA_TRIG_AND4_EN_C_M; + cr->la_and4_rate = LA_TRIG_AND4_VAL_C; + cr->la_and4_rate_m = LA_TRIG_AND4_VAL_C_M; + cr->la_and4_inv = LA_TRIG_AND4_INV_C; + cr->la_and4_inv_m = LA_TRIG_AND4_INV_C_M; + cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_C; + cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_C_M; + cr->la_and1_val = LA_TRIG_AND1_VAL_C; + cr->la_and1_val_m = LA_TRIG_AND1_VAL_C_M; + cr->la_and2_mask = LA_TRIG_AND2_MASK_C; + cr->la_and2_mask_m = LA_TRIG_AND2_MASK_C_M; + cr->la_and2_val = LA_TRIG_AND2_VAL_C; + cr->la_and2_val_m = LA_TRIG_AND2_VAL_C_M; + cr->la_and3_mask = LA_TRIG_AND3_MASK_C; + cr->la_and3_mask_m = LA_TRIG_AND3_MASK_C_M; + cr->la_and3_val = LA_TRIG_AND3_VAL_C; + cr->la_and3_val_m = LA_TRIG_AND3_VAL_C_M; + cr->la_and5_sel = LA_TRIG_AND5_C; + cr->la_and5_sel_m = LA_TRIG_AND5_C_M; + cr->la_and5_val = LA_TRIG_AND5_VAL_C; + cr->la_and5_val_m = LA_TRIG_AND5_VAL_C_M; + cr->la_and5_inv = LA_TRIG_AND5_INV_C; + cr->la_and5_inv_m = LA_TRIG_AND5_INV_C_M; + cr->la_and6_sel = LA_TRIG_AND6_C; + cr->la_and6_sel_m = LA_TRIG_AND6_C_M; + cr->la_and6_val = LA_TRIG_AND6_VAL_C; + cr->la_and6_val_m = LA_TRIG_AND6_VAL_C_M; + cr->la_and6_inv = LA_TRIG_AND6_INV_C; + cr->la_and6_inv_m = LA_TRIG_AND6_INV_C_M; + cr->la_and7_sel = LA_TRIG_AND7_C; + cr->la_and7_sel_m = LA_TRIG_AND7_C_M; + cr->la_and7_val = LA_TRIG_AND7_VAL_C; + cr->la_and7_val_m = LA_TRIG_AND7_VAL_C_M; + cr->la_and7_inv = LA_TRIG_AND7_INV_C; + cr->la_and7_inv_m = LA_TRIG_AND7_INV_C_M; + cr->la_brk_sel = BRK_R_BRK_SEL_FOR_CNT_C; + cr->la_brk_sel_m =BRK_R_BRK_SEL_FOR_CNT_C_M; + cr->la_mac_and1_en = LA_M_AND1_EN_C; + cr->la_mac_and1_en_m = LA_M_AND1_EN_C_M; + cr->la_mac_and2_en = LA_M_AND2_EN_C; + cr->la_mac_and2_en_m = LA_M_AND2_EN_C_M; + cr->la_mac_and2_frame_sel = TARGET_FRAME_TYPE_C; + cr->la_mac_and2_frame_sel_m =TARGET_FRAME_TYPE_C_M; + cr->la_mac_and0_sel = LA_M_AND0_SEL_C; + cr->la_mac_and0_sel_m = LA_M_AND0_SEL_C_M; + cr->la_mac_and0_en = LA_M_AND0_EN_C; + cr->la_mac_and0_en_m = LA_M_AND0_EN_C_M; + cr->la_mac_and0_mac_sel = INTF_R_MAC_SEL_C; + cr->la_mac_and0_mac_sel_m = INTF_R_MAC_SEL_C_M; + cr->la_and2_sign = LA_SIGN2_C; + cr->la_and2_sign_m = LA_SIGN2_C_M; + cr->la_and3_sign = LA_SIGN3_C; + cr->la_and3_sign_m = LA_SIGN3_C_M; + cr->la_re_trig_edge = LA_RE_INIT_POLARITY_C; + cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_C_M; + cr->la_re_and1_sel = LA_RE_INIT_AND1_C; + cr->la_re_and1_sel_m = LA_RE_INIT_AND1_C_M; + cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_C; + cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_C_M; + cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_C; + cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_C_M; + break; + #endif + #ifdef HALBB_COMPILE_AP2_SERIES + case BB_AP2: + cr->la_clk_en = LA_CKEN_A2; + cr->la_clk_en_m = LA_CKEN_A2_M; + cr->la_en = LA_EN_A2; + cr->la_en_m = LA_EN_A2_M; + cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_A2; + cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_A2_M; + cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_A2; + cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_A2_M; + cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_A2; + cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_A2_M; + cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_A2; + cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_A2_M; + cr->dma_d_path_sel = LA_TYPED_PATH_SEL_A2; + cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_A2_M; + cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_A2; + cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_A2_M; + cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_A2; + cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_A2_M; + cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_A2; + cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_A2_M; + cr->dma_d_src_sel = LA_TYPED_SRC_SEL_A2; + cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_A2_M; + cr->la_smp_rate = LA_SMP_RT_SEL_A2; + cr->la_smp_rate_m = LA_SMP_RT_SEL_A2_M; + cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_A2; + cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_A2_M; + cr->la_trigger_edge = LA_EDGE_SEL_A2; + cr->la_trigger_edge_m = LA_EDGE_SEL_A2_M; + cr->dma_hdr_sel_63 = LA_HDR_SEL_63_A2; + cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_A2_M; + cr->dma_hdr_sel_62 = LA_HDR_SEL_62_A2; + cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_A2_M; + cr->dma_hdr_sel_61 = LA_HDR_SEL_61_A2; + cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_A2_M; + cr->dma_hdr_sel_60 = LA_HDR_SEL_60_A2; + cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_A2_M; + cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_A2; + cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_A2_M; + cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_A2; + cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_A2_M; + cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_A2; + cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_A2_M; + cr->dma_data_type = LA_DATA_A2; + cr->dma_data_type_m = LA_DATA_A2_M; + cr->r_dma_rdrdy = LA_RDRDY_A2; + cr->r_dma_rdrdy_m= LA_RDRDY_A2_M; + cr->la_and0_bit_sel = LA_TRIG_A2; + cr->la_and0_bit_sel_m = LA_TRIG_A2_M; + cr->la_trigger_cnt = LA_TRIG_CNT_A2; + cr->la_trigger_cnt_m = LA_TRIG_CNT_A2_M; + cr->and0_trig_disable = LA_TRIG_NEW_ONLY_A2; + cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_A2_M; + cr->la_and1_inv = LA_TRIG_AND1_INV_A2; + cr->la_and1_inv_m = LA_TRIG_AND1_INV_A2_M; + cr->la_and2_en = LA_TRIG_AND2_EN_A2; + cr->la_and2_en_m = LA_TRIG_AND2_EN_A2_M; + cr->la_and2_inv = LA_TRIG_AND2_INV_A2; + cr->la_and2_inv_m = LA_TRIG_AND2_INV_A2_M; + cr->la_and3_en = LA_TRIG_AND3_EN_A2; + cr->la_and3_en_m = LA_TRIG_AND3_EN_A2_M; + cr->la_and3_inv = LA_TRIG_AND3_INV_A2; + cr->la_and3_inv_m = LA_TRIG_AND3_INV_A2_M; + cr->la_and4_en = LA_TRIG_AND4_EN_A2; + cr->la_and4_en_m = LA_TRIG_AND4_EN_A2_M; + cr->la_and4_rate = LA_TRIG_AND4_VAL_A2; + cr->la_and4_rate_m = LA_TRIG_AND4_VAL_A2_M; + cr->la_and4_inv = LA_TRIG_AND4_INV_A2; + cr->la_and4_inv_m = LA_TRIG_AND4_INV_A2_M; + cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_A2; + cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_A2_M; + cr->la_and1_val = LA_TRIG_AND1_VAL_A2; + cr->la_and1_val_m = LA_TRIG_AND1_VAL_A2_M; + cr->la_and2_mask = LA_TRIG_AND2_MASK_A2; + cr->la_and2_mask_m = LA_TRIG_AND2_MASK_A2_M; + cr->la_and2_val = LA_TRIG_AND2_VAL_A2; + cr->la_and2_val_m = LA_TRIG_AND2_VAL_A2_M; + cr->la_and3_mask = LA_TRIG_AND3_MASK_A2; + cr->la_and3_mask_m = LA_TRIG_AND3_MASK_A2_M; + cr->la_and3_val = LA_TRIG_AND3_VAL_A2; + cr->la_and3_val_m = LA_TRIG_AND3_VAL_A2_M; + cr->la_and5_sel = LA_TRIG_AND5_A2; + cr->la_and5_sel_m = LA_TRIG_AND5_A2_M; + cr->la_and5_val = LA_TRIG_AND5_VAL_A2; + cr->la_and5_val_m = LA_TRIG_AND5_VAL_A2_M; + cr->la_and5_inv = LA_TRIG_AND5_INV_A2; + cr->la_and5_inv_m = LA_TRIG_AND5_INV_A2_M; + cr->la_and6_sel = LA_TRIG_AND6_A2; + cr->la_and6_sel_m = LA_TRIG_AND6_A2_M; + cr->la_and6_val = LA_TRIG_AND6_VAL_A2; + cr->la_and6_val_m = LA_TRIG_AND6_VAL_A2_M; + cr->la_and6_inv = LA_TRIG_AND6_INV_A2; + cr->la_and6_inv_m = LA_TRIG_AND6_INV_A2_M; + cr->la_and7_sel = LA_TRIG_AND7_A2; + cr->la_and7_sel_m = LA_TRIG_AND7_A2_M; + cr->la_and7_val = LA_TRIG_AND7_VAL_A2; + cr->la_and7_val_m = LA_TRIG_AND7_VAL_A2_M; + cr->la_and7_inv = LA_TRIG_AND7_INV_A2; + cr->la_and7_inv_m = LA_TRIG_AND7_INV_A2_M; + cr->la_brk_sel = BRK_R_BRK_SEL_FOR_CNT_A2; + cr->la_brk_sel_m =BRK_R_BRK_SEL_FOR_CNT_A2_M; + cr->la_mac_and1_en = LA_M_AND1_EN_A2; + cr->la_mac_and1_en_m = LA_M_AND1_EN_A2_M; + cr->la_mac_and2_en = LA_M_AND2_EN_A2; + cr->la_mac_and2_en_m = LA_M_AND2_EN_A2_M; + cr->la_mac_and2_frame_sel = TARGET_FRAME_TYPE_A2; + cr->la_mac_and2_frame_sel_m =TARGET_FRAME_TYPE_A2_M; + cr->la_mac_and0_sel = LA_M_AND0_SEL_A2; + cr->la_mac_and0_sel_m = LA_M_AND0_SEL_A2_M; + cr->la_mac_and0_en = LA_M_AND0_EN_A2; + cr->la_mac_and0_en_m = LA_M_AND0_EN_A2_M; + cr->la_mac_and0_mac_sel = INTF_R_MAC_SEL_A2; + cr->la_mac_and0_mac_sel_m = INTF_R_MAC_SEL_A2_M; + cr->la_and2_sign = LA_SIGN2_A2; + cr->la_and2_sign_m = LA_SIGN2_A2_M; + cr->la_and3_sign = LA_SIGN3_A2; + cr->la_and3_sign_m = LA_SIGN3_A2_M; + cr->la_re_trig_edge = LA_RE_INIT_POLARITY_A2; + cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_A2_M; + cr->la_re_and1_sel = LA_RE_INIT_AND1_A2; + cr->la_re_and1_sel_m = LA_RE_INIT_AND1_A2_M; + cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_A2; + cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_A2_M; + cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_A2; + cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_A2_M; + break; + #endif + + + default: + break; + } + +} +#endif + +#if LAMODE_ECHO_CMD +void halbb_la_cr_dump(struct bb_info *bb) +{ + struct bb_la_cr_info *cr = &bb->bb_cmn_hooker->bb_la_mode_i.bb_la_cr_i; + u32 cr_table[16]; + u8 cr_len = sizeof(cr_table) / sizeof(u32); + + BB_TRACE("[%s]\n", __func__); + + cr_table[0] = cr->la_clk_en; + cr_table[1] = cr->la_en; + cr_table[2] = cr->dma_hdr_sel_63; + cr_table[3] = cr->la_and0_bit_sel; + cr_table[4] = cr->la_and1_mask; + cr_table[5] = cr->la_and1_val; + cr_table[6] = cr->la_and2_mask; + cr_table[7] = cr->la_and2_val; + cr_table[8] = cr->la_and3_mask; + cr_table[9] = cr->la_and3_val; + cr_table[10] = cr->la_and5_sel; + cr_table[11] = cr->la_brk_sel; + cr_table[12] = cr->la_mac_and2_frame_sel; + cr_table[13] = cr->la_mac_and0_sel; + cr_table[14] = cr->la_mac_and0_mac_sel; + cr_table[15] = cr->la_re_trig_edge; + + halbb_cr_table_dump(bb, cr_table, cr_len); +} + +void halbb_la_buffer_print(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + struct la_string_info *buf = &la->la_string_i; + struct la_print_info *print = &la->la_print_i; + u64 la_pattern_msb, la_pattern_lsb; + u64 la_pattern, la_pattern_part; + s64 tmp_s64; + u64 mask = 0xffffffff; + u8 mask_length = 0; + u32 i; + u32 idx; + u32 var[10] = {0}; + + if (!buf->octet || buf->length == 0 || buf->length < la->smp_number) + return; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &var[3]); + + BB_TRACE("echo lamode 1 %d %d %d 0 %x %d %d %d\n\n", + la->la_and0_bit_sel, dma->dma_data_type, + la->la_mac_cfg_i.la_trigger_time, + la->la_dbg_port, la->la_trigger_edge, la->la_smp_rate, + la->la_count); + BB_TRACE("[LA Data Dump] smp_number = %d\n", la->smp_number); + BB_TRACE("Dump_Start\n"); + + print->print_len = (u8)var[0]; + + if (var[0] == 0) { + for (i = 0; i < la->smp_number; i++) { + idx = i << 1; + BB_TRACE("%08x%08x\n", SWAP4BYTE(buf->octet[idx + 1]), + SWAP4BYTE(buf->octet[idx])); + } + } else if (var[0] == 1) { + + print->print_mode = (u8)var[1]; + print->print_lsb = (u8)var[2]; + print->print_msb = (u8)var[3]; + + /*------------------------*/ + if (var[1] == 0) + BB_TRACE("[Hex]\n"); + else if (var[1] == 1) + BB_TRACE("[Dec unsigned]\n"); + else if (var[1] == 2) + BB_TRACE("[Dec signed]\n"); + + BB_TRACE("BIT[%d:%d]\n", var[3], var[2]); + + if (var[2] > var[3]) { + BB_TRACE("[Warning] BIT_L > BIT_H\n"); + return; + } + + mask_length = (u8)(var[3] - var[2] + 1); + mask = halbb_gen_mask_from_0(mask_length) << var[2]; + /*------------------------*/ + for (i = 0; i < la->smp_number; i++) { + idx = i << 1; + la_pattern_msb = (u64)SWAP4BYTE(buf->octet[idx + 1]); + la_pattern_lsb = (u64)SWAP4BYTE(buf->octet[idx + 1]); + la_pattern = (la_pattern_msb << 32) | la_pattern_lsb; + la_pattern_part = (la_pattern & mask) >> var[2]; + + if (var[1] == 0) { + BB_TRACE("0x%llx\n", la_pattern_part); + } else if (var[1] == 1) { + BB_TRACE("%llu\n", la_pattern_part); + } else if (var[1] == 2) { + tmp_s64 = halbb_cnvrt_2_sign_64(la_pattern_part, + mask_length); + BB_TRACE("%lld\n", tmp_s64); + } + } + } + BB_TRACE("Dump_End\n\n"); +} + +void halbb_la_cmd_bb_show_cfg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + struct la_dma_info *dma = &la->la_dma_i; + struct la_re_trig_info *re = &la->la_re_trig_i; + struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i; + struct la_print_info *print = &la->la_print_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cmn {TrigTime:%d} {TrigCnt:%d} {DbgPort:0x%x} {Edge:P/N:%d} {f_smp:%d M(%d)}\n", + cfg->la_trigger_time, la->la_trigger_cnt, + la->la_dbg_port, la->la_trigger_edge, 80 >> la->la_smp_rate, la->la_smp_rate); + /*BB DMA*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {0:dbgPort_base_N} {N:%d}\n", + dma->dma_dbgport_base_n); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {1:path_sel} {A:%d} {B:%d} {C:%d} {D:%d}\n", + dma->dma_a_path_sel, dma->dma_b_path_sel, + dma->dma_c_path_sel, dma->dma_d_path_sel); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {2:src_sel} {A:%d} {B:%d} {C:%d} {D:%d}\n", + dma->dma_a_src_sel, dma->dma_b_src_sel, + dma->dma_c_src_sel, dma->dma_d_src_sel); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {3:hdr_sel} {B63:%d} {B62:%d} {B61:%d} {B60:%d}\n", + dma->dma_hdr_sel_63, dma->dma_hdr_sel_62, + dma->dma_hdr_sel_61, dma->dma_hdr_sel_60); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {4:phy_sel} {phy:%d}\n", dma->dma_dbgport_phy_sel); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dma {5:dma_sel} {type:%d}\n", dma->dma_data_type); + + /*BB -Trig*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {0:And0} {disable:%d} {bit_num:%d}\n", + la->la_and0_disable, la->la_and0_bit_sel); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {1:And1} {mask:0x%x} {inv:%d} {bitmap_val:0x%x}\n", + adv->la_and1_mask, adv->la_and1_inv, adv->la_and1_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {2:And2} {en:%d} {inv:%d} {val:%d} {mask(0x%x)} {sign:%d}\n", + adv->la_and2_en, adv->la_and2_inv, adv->la_and2_val, + adv->la_and2_mask, adv->la_and2_sign); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {3:And3} {en:%d} {inv:%d} {val:%d} {mask(0x%x)} {sign:%d}\n", + adv->la_and3_en, adv->la_and3_inv, adv->la_and3_val, + adv->la_and3_mask, adv->la_and3_sign); + + halbb_print_rate_2_buff(bb, adv->la_and4_rate, RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {4:And4} {en:%d} {inv:%d} {rate_idx: %s (0x%x)}\n", + adv->la_and4_en, adv->la_and4_inv, bb->dbg_buf, adv->la_and4_rate); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {5:And5} {sel:%d} {inv:%d} {val:%d}\n", + adv->la_and5_sel, adv->la_and5_inv, adv->la_and5_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {6:And6} {sel:%d} {inv:%d} {val:%d}\n", + adv->la_and6_sel, adv->la_and6_inv, adv->la_and6_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bb {7:And7} {sel:%d} {inv:%d} {val:%d}\n", + adv->la_and7_sel, adv->la_and7_inv, adv->la_and7_val); + /*MAC Adv-Trig*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "mac {0:And0} {en:%d} {0:cca,1:er,2:ok:%d} {0:tmac,1:pmac:%d}\n", + trig_mac->la_mac_and0_en, trig_mac->la_mac_and0_sel, + trig_mac->la_mac_and0_mac_sel); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "mac {1:And1} {en:%d}\n", trig_mac->la_mac_and1_en); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "mac {2:And2} {en:%d} {frame_type(%x)}\n", + trig_mac->la_mac_and2_en, trig_mac->la_mac_and2_frame_sel); + /*BB Re-Trig*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "re {mac_en:%d} {en/sel:%d} {inv:%d} {val:%d} {edge:%d}\n", + cfg->mac_la_restart_en, re->la_re_and0_sel, + re->la_re_and0_inv, re->la_re_and0_val, + re->la_re_trig_edge); + /*Buffer*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "buf {0:64K, 1:128K, 2:192K, 3:256K, 4:320K:%d}\n", + cfg->mac_la_buf_sel); + + /*control*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "poll {la_polling_cnt:%d} (polling time = %d * 100ms)\n", + la->la_polling_cnt, la->la_polling_cnt); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tmac {timeout_en:%d} {timeout_val:%d} (timeout= 1s << %d )\n", + cfg->mac_la_timeout_en, cfg->mac_la_timeout_val, + cfg->mac_la_timeout_val); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "get {finish_ofst} {is_round_up} (get buffer data for timeout)\n"); + + /*Print*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "print {0:all(Hex):%d}\n", print->print_len); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "print {1:partial:%d} {0:hex,1:dec,2:s-dec:%d} {bit_L:%d} {bit_H:%d}\n", + print->print_len, print->print_mode, print->print_lsb, + print->print_msb); + + /*Setting*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set {1:Fake Trig} {en:%d}\n", la->not_stop_trig); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set {2:Auto Print} {en:%d}\n", + print->is_la_print); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "max_num {val:%d}: consective capture LA pattern number\n", la->la_count); +} + +void halbb_la_cmd_bb_cmn(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_HEX, &val[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]); + HALBB_SCAN(input[6], DCMD_DECIMAL, &val[4]); + + la->la_mac_cfg_i.la_trigger_time = val[0]; + la->la_trigger_cnt = (u8)val[1]; + la->la_dbg_port = val[2]; + la->la_trigger_edge = (enum la_bb_trig_edge)val[3]; + la->la_smp_rate = (enum la_bb_smp_clk)val[4]; +} + +void halbb_la_cmd_bb_dma(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]); + HALBB_SCAN(input[6], DCMD_DECIMAL, &val[4]); + + if (val[0] == 0) { + dma->dma_dbgport_base_n = (u8)val[1]; + } else if (val[0] == 1) { + dma->dma_a_path_sel = (u8)val[1]; + dma->dma_b_path_sel = (u8)val[2]; + dma->dma_c_path_sel = (u8)val[3]; + dma->dma_d_path_sel = (u8)val[4]; + } else if (val[0] == 2) { + dma->dma_a_src_sel = (u8)val[1]; + dma->dma_b_src_sel = (u8)val[2]; + dma->dma_c_src_sel = (u8)val[3]; + dma->dma_d_src_sel = (u8)val[4]; + } else if (val[0] == 3) { + dma->dma_hdr_sel_63 = (enum la_hdr_sel_t)val[1]; + dma->dma_hdr_sel_62 = (enum la_hdr_sel_t)val[2]; + dma->dma_hdr_sel_61 = (enum la_hdr_sel_t)val[3]; + dma->dma_hdr_sel_60 = (enum la_hdr_sel_t)val[4]; + } else if (val[0] == 4) { + dma->dma_dbgport_phy_sel = (bool)val[1]; + } else if (val[0] == 5) { + dma->dma_data_type = (enum la_dma_data_type_t)val[1]; + } +} + +void halbb_la_cmd_bb_trig(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_HEX, &val[0]); + HALBB_SCAN(input[3], DCMD_HEX, &val[1]); + HALBB_SCAN(input[4], DCMD_HEX, &val[2]); + HALBB_SCAN(input[5], DCMD_HEX, &val[3]); + HALBB_SCAN(input[6], DCMD_HEX, &val[4]); + HALBB_SCAN(input[7], DCMD_HEX, &val[5]); + HALBB_SCAN(input[8], DCMD_HEX, &val[6]); + + if (val[0] == 0) { + la->la_and0_disable = (bool)val[1]; + la->la_and0_bit_sel = val[2]; + } else if (val[0] == 1) { + adv->la_and1_mask = val[1]; + adv->la_and1_inv = (bool)val[2]; + adv->la_and1_val = val[3]; + } else if (val[0] == 2) { + adv->la_and2_en = (bool)val[1]; + adv->la_and2_inv = (bool)val[2]; + adv->la_and2_val = val[3]; + adv->la_and2_mask = val[4]; + adv->la_and2_sign = (u8)val[5]; + } else if (val[0] == 3) { + adv->la_and3_en = (bool)val[1]; + adv->la_and3_inv = (bool)val[2]; + adv->la_and3_val = val[3]; + adv->la_and3_mask = val[4]; + adv->la_and3_sign = (u8)val[5]; + } else if (val[0] == 4) { + adv->la_and4_en = (bool)val[1]; + adv->la_and4_inv = (bool)val[2]; + adv->la_and4_rate = (u16)val[3]; + } else if (val[0] == 5) { + adv->la_and5_sel = (u8)val[1]; + adv->la_and5_inv = (bool)val[2]; + adv->la_and5_val = (u8)val[3]; + } else if (val[0] == 6) { + adv->la_and6_sel = (u8)val[1]; + adv->la_and6_inv = (bool)val[2]; + adv->la_and6_val = (u8)val[3]; + } else if (val[0] == 7) { + adv->la_and7_sel = (u8)val[1]; + adv->la_and7_inv = (bool)val[2]; + adv->la_and7_val = (u8)val[3]; + } + + if (adv->la_and1_mask == 0 && + !adv->la_and2_en && !adv->la_and3_en && !adv->la_and4_en && + adv->la_and5_sel == 0 && + adv->la_and6_sel == 0 && + adv->la_and7_sel == 0) { + adv->adv_trig_en = false; + } else { + adv->adv_trig_en = true; + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Adv_trig_en=%d]\n\n", adv->adv_trig_en); +} + +void halbb_la_cmd_bb_re_trig(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_re_trig_info *re = &la->la_re_trig_i; + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]); + + la->la_mac_cfg_i.mac_la_restart_en = (u8)val[0]; + re->re_trig_en = (bool)val[0]; + + re->la_re_and0_sel = (u8)val[1]; + re->la_re_and0_inv = (bool)val[2]; + re->la_re_and0_val = (u8)val[3]; + re->la_re_trig_edge = (bool)val[4]; +} + +void halbb_la_io_en(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + + BB_TRACE("[%s]", __func__); + la->la_run_mode = LA_RUN_GET_MORE; + halbb_la_run(bb); +} + +void halbb_la_callback(void *context) +{ + struct bb_info *bb = (struct bb_info *)context; + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct halbb_timer_info *timer = &la->la_timer_i; + + BB_TRACE("[%s]===>\n", __func__); + + timer->timer_state = BB_TIMER_IDLE; + + if (bb->phl_com->hci_type == RTW_HCI_PCIE) + halbb_la_io_en(bb); + else + rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx); +} + +void halbb_la_timer_init(struct bb_info *bb) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct halbb_timer_info *timer = &la->la_timer_i; + + timer->event_idx = BB_EVENT_TIMER_LA; + timer->timer_state = BB_TIMER_IDLE; + + halbb_init_timer(bb, &timer->timer_list, halbb_la_callback, bb, "halbb_la_timer"); +} + +void halbb_la_cmd_rtl_test(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + struct la_re_trig_info *re_trig = &la->la_re_trig_i; + struct la_dma_info *dma = &la->la_dma_i; + enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw; + u32 trig_time_cca = 0; + s32 val_sign32_tmp = 0; + u32 var[10] = {0}; + u32 test_case = 0; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]); + test_case = var[0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "RTL_test_case=%d\n", test_case); + + if (bw > CHANNEL_WIDTH_80) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support for BW > %dM\n", 20 << bw); + return; + } + + halbb_la_reset(bb); + + /*Trig Time*/ + trig_time_cca = ((la->la_string_i.smp_number_max >> (bw + 1)) / 10) + - (2 << (2 - bw)) - (2 - bw); + + /*--- Basic Trigger Setting --------------------------------*/ + la->la_mac_cfg_i.la_trigger_time = trig_time_cca; + la->la_trigger_edge = LA_P_EDGE; + la->la_smp_rate = LA_SMP_CLK_20 - bw; + la->la_trigger_cnt = 0; + + if (test_case == 0) { + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_CCA; + dma->dma_hdr_sel_62 = LA_HDR_AGC_RDY; + dma->dma_hdr_sel_61 = LA_HDR_RXHE_FULLBAND; + dma->dma_hdr_sel_60 = LA_HDR_CRC_OK; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 31; + /*DBG_PORT*/ + la->la_dbg_port = 0x20002; /*dbg_rx_inner_state_2*/ + la->la_and0_bit_sel = 31; + /*AND_0*/ + la->la_and0_disable = false; + /*AND_1~AND_7*/ + adv->adv_trig_en = false; + + } else if (test_case == 1) { + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_CCA; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 31; + /*DBG_PORT*/ + la->la_dbg_port = 0x20002; /*dbg_rx_inner_state_2*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_1*/ + adv->la_and1_mask = 0x7C000000; + adv->la_and1_val = 20; + adv->la_and1_inv = false; + } else if (test_case == 2) { /*EVM > 35*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + /*DBG_PORT*/ + la->la_dbg_port = 0x20011; /*dbg_rx_inner_state_2*/ + dma->dma_dbgport_base_n = 31; + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_2*/ + adv->la_and2_en = true; + adv->la_and2_inv = false; + adv->la_and2_val = 35 << 2; /*u(8,2)*/ + adv->la_and2_mask = 0xff0000; /*2-nd stream*/ + adv->la_and2_sign = LA_UNSIGNED; + } else if (test_case == 3) { /*CFO < 1/32 carrier spacing*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 23; + /*DBG_PORT*/ + la->la_dbg_port = 0x20003; /*dbg_rx_inner_state_2*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_3*/ + adv->la_and3_en = true; + adv->la_and3_inv = false; + adv->la_and3_val = 0x4; /*+1/32 carrier spacing, S(16,16)*/ + adv->la_and3_mask = 0xffff00; /*phy0_rCFO_for_STO_update*/ + adv->la_and3_sign = LA_SIGNED; + } else if (test_case == 4) { /*rx_rate = HE 2SS MCS7*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 31; + /*DBG_PORT*/ + la->la_dbg_port = 0x20002; /*dbg_rx_inner_state_2*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_4*/ + adv->la_and4_en = true; + adv->la_and4_inv = false; + adv->la_and4_rate = 0x197; /*HE 2SS MCS7*/ + } else if (test_case == 5) { /*state = CCK CCA*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 31; + /*DBG_PORT*/ + la->la_dbg_port = 0x1029f; /*AGC(dbg_ctrl_3)*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_5*/ + adv->la_and5_sel = LA_CCK_CCA; + adv->la_and5_inv = false; + } else if (test_case == 6) { /*state = bfmx_csi_standby*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 19; + /*DBG_PORT*/ + la->la_dbg_port = 0x70035; /*BFeeTop_phy0*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_6*/ + adv->la_and6_sel = LA_BFMX_CSI_STANDBY; + adv->la_and6_inv = false; + } else if (test_case == 7) { /*TD_STATE = HE_TB_STANDBY*/ + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_ORI; + dma->dma_hdr_sel_62 = LA_HDR_ORI; + dma->dma_hdr_sel_61 = LA_HDR_ORI; + dma->dma_hdr_sel_60 = LA_HDR_ORI; + dma->dma_data_type = DMA01_NRML_2s_12b; + dma->dma_dbgport_base_n = 31; + /*DBG_PORT*/ + la->la_dbg_port = 0x10202; /*HE_TB*/ + /*AND_0*/ + la->la_and0_disable = true; + /*AND_1~AND_7*/ + adv->adv_trig_en = true; + /*AND_7*/ + adv->la_and7_sel = LA_RX_TD_STATE; + adv->la_and7_inv = false; + adv->la_and7_val = 40; /*HE TB standby*/ + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support\n"); + return; + } + BB_TRACE("RTL Test Case Trigger: %d\n", test_case); + halbb_la_cr_dump(bb); + la->la_run_mode = LA_RUN_RTL_TEST; + la->la_count = la->la_count_max; + halbb_la_run(bb); + halbb_print_devider(bb, BB_DEVIDER_LEN_32, true); +} + +void halbb_la_cmd_mac_trig(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i; + u32 val[10] = {0}; + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_HEX, &val[2]); + HALBB_SCAN(input[5], DCMD_HEX, &val[3]); + + if (val[0] == 0) { + trig_mac->la_mac_and0_en = (bool)val[1]; + trig_mac->la_mac_and0_sel = (u8)val[2]; + trig_mac->la_mac_and0_mac_sel = (u8)val[3]; + } else if (val[0] == 1) { + trig_mac->la_mac_and1_en = (bool)val[1]; + } else if (val[0] == 2) { + trig_mac->la_mac_and2_en = (bool)val[1]; + trig_mac->la_mac_and2_frame_sel = (u8)val[2]; + } + + if (!trig_mac->la_mac_and0_en && + !trig_mac->la_mac_and1_en && + !trig_mac->la_mac_and2_en) + trig_mac->la_mac_trig_en = false; + else + trig_mac->la_mac_trig_en = true; + +} + +void halbb_la_cmd_fast(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_adv_trig_info *adv = &la->adv_trig_i; + struct la_re_trig_info *re_trig = &la->la_re_trig_i; + struct la_dma_info *dma = &la->la_dma_i; + u32 trig_time_cca = 0; + s32 val_sign32_tmp = 0; + u32 var[10] = {0}; + enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw; + u8 i = 0; + + if (bw > CHANNEL_WIDTH_80) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support for BW > %dM\n", 20 << bw); + return; + } + + for (i = 0; i < 5; i++) { + HALBB_SCAN(input[2 + i], DCMD_DECIMAL, &var[i]); + } + + trig_time_cca = ((la->la_string_i.smp_number_max >> (bw + 1)) / 10) + - (2 << (2 - bw)) - (2 - bw); + + /*DMA SEL*/ + dma->dma_hdr_sel_63 = LA_HDR_CCA; + dma->dma_hdr_sel_62 = LA_HDR_AGC_RDY; + dma->dma_hdr_sel_61 = LA_HDR_RXHE_FULLBAND; + dma->dma_hdr_sel_60 = LA_HDR_CRC_OK; + + dma->dma_data_type = DMA03_NRML_2s_14b; + + if (var[0] < 10) { + /*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/ + /*--- Basic Trigger Setting --------------------------------*/ + la->la_mac_cfg_i.la_trigger_time = trig_time_cca; + la->la_trigger_edge = LA_P_EDGE; + la->la_smp_rate = LA_SMP_CLK_20 - bw; + la->la_trigger_cnt = 0; + if (var[0] == 0) { /*CCA*/ + la->la_and0_disable = true; + la->la_dbg_port = 0x2002; /*dbg_rx_inner_state_2*/ + halbb_la_bb_set_dma_type_reset(bb); + halbb_la_bb_set_adv_reset(bb); + halbb_la_mac_set_adv_reset(bb); + halbb_la_bb_set_re_trig_reset(bb); + adv->adv_trig_en = true; + adv->la_and5_sel = 2; + adv->la_and5_inv = false; + adv->la_and5_val = 0; + BB_TRACE("[Fast trigger 0: OFDM CCA]\n"); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support\n"); + return; + } + + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support\n"); + return; + } + la->la_run_mode = LA_RUN_FAST; + la->la_count = la->la_count_max; + halbb_la_run(bb); +} + +void halbb_la_cmd_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i; + struct la_dma_info *dma = &la->la_dma_i; + struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i; + struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i; + struct la_string_info *buf = &la->la_string_i; + u32 val[10] = {0}; + u8 i = 0; + + if (_os_strcmp(input[1], "-h") == 0) { + /*BB Basic Trigger*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "adv_help\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {TrigCnt}\n\t {DbgPort} {Edge:P/N} {f_smp} {Cap_num}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "MAC_trig: 1 1 {0:cca,1:ok_pmac,2:er_pmac,3:ok,4:er} {DMA#} {TrigTime} {trig_cnt}\n\t {DbgPort} {Edge:0(P),1(N)} {f_smp} {Cpture num}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "fast\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rtl_test {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cr_dump\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "buf {0~4: 64K/128K/192K/256K/320K}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "reset: reset all setting\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "trig\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ptrn_chk {show(END), rst(END), {ptrn_idx:0~3} {smp_point} {msb32_mask(hex)} {val(hex)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ptrn_chk max_num {val)}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "max_num {val}\n"); + #if 0 + /*Fast Trigger*/ + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "fast {0: CCA trig & AGC Dbg Port}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "fast {1: CCA trig & EVM Dbg Port}\n"); + #endif + + return; + } + + if (_os_strcmp(input[1], "adv_help") == 0 || + _os_strcmp(input[1], "show") == 0) { + halbb_la_cmd_bb_show_cfg(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "ptrn_chk") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + if (_os_strcmp(input[2], "show") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[LA CHK Pattern] ===>\n"); + } else if (_os_strcmp(input[2], "max_num") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + la->la_count_max = val[0]; + } else if (_os_strcmp(input[2], "rst") == 0) { + halbb_mem_set(bb, la->la_ptrn_chk_i, 0, sizeof(struct la_ptrn_chk_info) * LA_CHK_PTRN_NUM); + la->la_ptrn_chk_en = false; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ptrn_chk reset(Disable)\n"); + } else if (val[0] < LA_CHK_PTRN_NUM) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_HEX, &val[2]); + HALBB_SCAN(input[5], DCMD_HEX, &val[3]); + + if (val[1] < la->la_string_i.smp_number_max) { + la->la_ptrn_chk_i[val[0]].smp_point = val[1]; + la->la_ptrn_chk_i[val[0]].la_ptrn_chk_mask = val[2]; + la->la_ptrn_chk_i[val[0]].la_ptrn_chk_val = val[3]; + la->la_ptrn_chk_en = true; + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Err] smp_number_max=%d\n", la->la_string_i.smp_number_max); + } + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err, idx=%d\n", val[0]); + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ptrn_chk_en=%d, max_num = %d\n", la->la_ptrn_chk_en, la->la_count_max); + + for (i = 0; i < LA_CHK_PTRN_NUM; i++) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%d] point=%05d, chk_mask=0x%08x, chk_val=0x%x\n", + i, la->la_ptrn_chk_i[i].smp_point, + la->la_ptrn_chk_i[i].la_ptrn_chk_mask, + la->la_ptrn_chk_i[i].la_ptrn_chk_val); + } + } else if (_os_strcmp(input[1], "fast") == 0) { + halbb_la_cmd_fast(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "rtl_test") == 0) { + halbb_la_cmd_rtl_test(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "max_num") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + la->la_count_max = val[0]; + //la->la_count = la->la_count_max; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "max_num = %d\n", la->la_count_max); + } else if (_os_strcmp(input[1], "cr_dump") == 0) { + halbb_la_cr_dump(bb); + } else if (_os_strcmp(input[1], "reset") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Reset\n"); + halbb_la_reset(bb); + } else if (_os_strcmp(input[1], "trig") == 0) { + la->la_run_mode = LA_RUN_MANUAL; + la->la_count = la->la_count_max; + halbb_la_run(bb); + } else if (_os_strcmp(input[1], "cmn") == 0) { + halbb_la_cmd_bb_cmn(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "dma") == 0) { + halbb_la_cmd_bb_dma(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "bb") == 0) { + halbb_la_cmd_bb_trig(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "mac") == 0) { + halbb_la_cmd_mac_trig(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "tmac") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]); + cfg->mac_la_timeout_en = (u8)val[1]; + cfg->mac_la_timeout_val = (u8)val[2]; + } else if (_os_strcmp(input[1], "poll") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + la->la_polling_cnt = (u8)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "la_polling_cnt = %d, polling time = %d * 100ms\n", + la->la_polling_cnt, la->la_polling_cnt); + } else if (_os_strcmp(input[1], "get") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]); + la->la_mode_state = LA_STATE_GET_DLE_BUF; + halbb_mem_set(bb, buf->octet, 0, buf->length); + halbb_la_rpt_buf_get(bb, (u16)val[1], (bool)val[2]); + halbb_la_stop(bb); + } else if (_os_strcmp(input[1], "re") == 0) { + halbb_la_cmd_bb_re_trig(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "buf") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + la->la_mac_cfg_i.mac_la_buf_sel = (enum la_buff_mode_t)val[1]; + la->la_mac_cfg_i.mac_alloc_success = halbb_la_mac_cfg_buf(bb, la->la_mac_cfg_i.mac_la_buf_sel); + + if (!la->la_mac_cfg_i.mac_alloc_success) + halbb_la_stop(bb); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "MAC_BUF_alloc_success=%d, Buff_mode=(%d)K\n", + la->la_mac_cfg_i.mac_alloc_success, + 64 * (la->la_mac_cfg_i.mac_la_buf_sel + 1)); + } else if (_os_strcmp(input[1], "set") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + + if (val[1] == 1) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]); + la->not_stop_trig = (bool)val[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "not_stop_trig=(%d)\n", la->not_stop_trig); + } else if (val[1] == 2) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]); + la->la_print_i.is_la_print = (bool)val[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Auto print=(%d)\n", la->la_print_i.is_la_print); + } + } else if (_os_strcmp(input[1], "print") == 0) { + halbb_la_buffer_print(bb, input, _used, output, _out_len); + } else if (_os_strcmp(input[1], "1") == 0) { + if (!la->la_mac_cfg_i.mac_alloc_success) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Need to set MAC CR(buf) first: echo bb lamode buf {val}\n"); + } + + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[3]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[4]); + HALBB_SCAN(input[6], DCMD_HEX, &val[5]); + HALBB_SCAN(input[7], DCMD_HEX, &val[6]); + HALBB_SCAN(input[8], DCMD_DECIMAL, &val[7]); + HALBB_SCAN(input[9], DCMD_DECIMAL, &val[8]); + HALBB_SCAN(input[10], DCMD_DECIMAL, &val[9]); + + halbb_la_bb_set_adv_reset(bb); + halbb_la_mac_set_adv_reset(bb); + halbb_la_bb_set_re_trig_reset(bb); + + la->la_basic_mode_sel = (u8)val[1]; + la->la_and0_bit_sel = val[2]; + la->la_mac_cfg_i.la_trigger_time = val[4]; /*unit: us*/ + la->la_trigger_cnt= (u8)val[5]; + la->la_dbg_port = val[6]; + la->la_trigger_edge = (enum la_bb_trig_edge)val[7]; + la->la_smp_rate = (enum la_bb_smp_clk)(val[8]); + la->la_count_max = val[9]; + + if (la->la_basic_mode_sel == 0) { + dma->dma_data_type = (u8)val[3]; + la->la_and0_disable = false; + la->adv_trig_i.adv_trig_en = false; + la->la_re_trig_i.re_trig_en = false; + trig_mac->la_mac_trig_en = false; + } else { + la->la_and0_disable = true; + la->adv_trig_i.adv_trig_en = false; + la->la_re_trig_i.re_trig_en = false; + trig_mac->la_mac_trig_en = true; + trig_mac->la_mac_and0_en = true; + trig_mac->la_mac_and0_sel = (u8)val[3]; + } + + BB_TRACE("echo bb lamode 1 %d %d %d %d %d %x %d %d %d\n\n", + val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9]); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "a.En= ((1)), b.Mode = ((%d)), c.Trig_sel = ((0x%x)), d.Dma_type = ((%d))\n", + la->la_and0_bit_sel, la->la_basic_mode_sel, + dma->dma_data_type); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "e.Trig_time = ((%dus)), f.Trig_cnt = ((%d)), g.Dbg_port = ((0x%x))\n", + la->la_mac_cfg_i.la_trigger_time, la->la_trigger_cnt, + la->la_dbg_port); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "h.Trig_edge = ((%d)), i.La rate = ((%d MHz)), j.Cap_num = ((%d))\n\n", + la->la_trigger_edge, (80 >> la->la_smp_rate), + la->la_count_max); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{And0_disable, adv_trig, re_trig, mac_trig}= {%d, %d, %d, %d}\n", + la->la_and0_disable, la->adv_trig_i.adv_trig_en, + la->la_re_trig_i.re_trig_en, + trig_mac->la_mac_trig_en); + la->la_run_mode = LA_RUN_HERITAGE; + la->la_count = la->la_count_max; + halbb_la_run(bb); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} +#endif + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_la_mode.h b/phl/hal_g6/phy/bb/halbb_la_mode.h new file mode 100644 index 0000000..d00de9f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_la_mode.h @@ -0,0 +1,433 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_LA_MODE_H__ +#define __HALBB_LA_MODE_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define LA_CHK_PTRN_NUM 4 +/*@--------------------------[Enum]------------------------------------------*/ + +enum la_run_mode_t { + LA_RUN_HERITAGE = 0, + LA_RUN_FAST = 1, + LA_RUN_MANUAL = 2, + LA_RUN_RTL_TEST = 3, + LA_RUN_GET_MORE = 4, +}; + +enum la_state_trig_t { + LA_AND_DISABLE = 0, + LA_CCK_CCA = 1, + LA_OFDM_CCA = 2, + LA_OFDM_VBON = 3, + LA_RX_STATE = 4, + LA_RX_STATE_FEQ = 5, + LA_RX_TD_STATE = 6, + LA_MUX_STATE = 7, + LA_PHYTXON = 8, + LA_BFMX_NDP_STANDBY = 9, + LA_BFMX_CSI_STANDBY = 10, + LA_CCA_SPOOF = 11, + LA_RXPKT_OK_MX = 12, + LA_RXPKT_FAIL_MX = 13, + LA_BRK = 14, + LA_BRK_SEL = 15, + LA_HE_TB_STANDBY = 16, +}; + +enum la_hdr_sel_t { + LA_HDR_ORI = 0, + LA_HDR_CCA = 1, + LA_HDR_CCA_OFDM = 2, + LA_HDR_CCA_CCK = 3, + LA_HDR_AGC_RDY = 4, + LA_HDR_AGC_RDY_HT = 5, + LA_HDR_RXHT = 6, + LA_HDR_RXVHT = 7, + LA_HDR_RXHE_FULLBAND = 8, + LA_HDR_RXHE_OFDMA = 9, + LA_HDR_OFDM_VBON = 10, + LA_HDR_RXPKT_OK_SYNC = 11, + LA_HDR_RDRDY = 12, + LA_HDR_CRC_OK = 13, + LA_HDR_CRC_ERR = 14 +}; + +enum la_bb_trig_edge { + LA_P_EDGE = 0, + LA_N_EDGE = 1, +}; + +enum la_mac_polling_state { + LA_HW_IDLE = 0, + LA_HW_START = 1, + LA_HW_FINISH_STOP = 2, + LA_HW_FINISH_TIMEOUT = 3, + LA_HW_RE_START = 4 +}; + +enum la_mode_state_t { + LA_STATE_IDLE = 0, + LA_STATE_MAIN = 1, + LA_STATE_GET_DLE_BUF = 2, + LA_STATE_WAIT_RESTART = 3 +}; + +enum la_buff_mode_t { + LA_BUFF_64K = 0, + LA_BUFF_128K = 1, + LA_BUFF_192K = 2, + LA_BUFF_256K = 3, + LA_BUFF_320K = 4, + LA_BUF_DISABLE = 0xff +}; + +enum la_bb_smp_clk { + LA_SMP_CLK_80 = 0, + LA_SMP_CLK_40 = 1, + LA_SMP_CLK_20 = 2, + LA_SMP_CLK_10 = 3, + LA_SMP_CLK_5 = 4, + LA_SMP_CLK_2_5 = 5, + LA_SMP_CLK_1_25 = 6, + LA_SMP_CLK_160 = 7 +}; + +enum la_dma_data_type_t { + DMA00_NRML_1s_14b = 0, + DMA01_NRML_2s_12b = 1, /*Dbgport 16-bit: dbg[N, N-15]*/ + DMA02_NRML_2s_13b = 2, /*Dbgport 12-bit: dbg[N, N-11]*/ + DMA03_NRML_2s_14b = 3, /*Dbgport 08-bit: dbg[N, N-07]*/ + DMA04_NRML_3s_08b = 4, + DMA05_NRML_3s_09b = 5, + DMA06_NRML_3s_10b = 6, + DMA07_NRML_4s_07b = 7, + DMA08_NRML_4s_08b = 8, + DMA09_DUAL_4s_12b = 9, + DMA10_DUAL_4s_13b = 10, + DMA11_DUAL_4s_14b = 11, + DMA12_MPHS_1s_2p_12b = 12, + DMA13_MPHS_1s_3p_10b = 13, + DMA14_MPHS_1s_4p_08b = 14, + DMA15_MPHS_2s_2p_08b = 15, + DMA16_DBG_BB_MNTR = 16, + DMA17_DUAL_WB_1s_14b = 17, + DMA18_DUAL_WB_2s_14b = 18, + DMA19_DUAL_WB_3s_14b = 19, + DMA20_DUAL_WB_4s_14b = 20, + DMA30_DBG_LA_SEL = 30 +}; + +enum la_trig_sign_t { + LA_UNSIGNED = 0, + LA_SIGNED = 1, + LA_NORM = 2, +}; + +/*@--------------------------[Structure]-------------------------------------*/ + +struct la_ptrn_chk_info { + u32 smp_point; + u32 la_ptrn_chk_mask; /*if mask=0: disable pattern chk, for MSB 32bit only*/ + u32 la_ptrn_chk_val; +}; + +struct la_print_info { + bool is_la_print; + u8 print_len; /*0: all, 1:partial*/ + u8 print_mode; /*0: hex, 1:unsign, 2:sign*/ + u8 print_lsb; + u8 print_msb; +}; + +struct la_dma_info { + u8 dma_dbgport_base_n; + u8 dma_a_path_sel; + u8 dma_b_path_sel; + u8 dma_c_path_sel; + u8 dma_d_path_sel; + u8 dma_a_src_sel; + u8 dma_b_src_sel; + u8 dma_c_src_sel; + u8 dma_d_src_sel; + enum la_hdr_sel_t dma_hdr_sel_63; + enum la_hdr_sel_t dma_hdr_sel_62; + enum la_hdr_sel_t dma_hdr_sel_61; + enum la_hdr_sel_t dma_hdr_sel_60; + bool dma_a_ck160_dly_en; + bool dma_b_ck160_dly_en; + bool dma_c_ck160_dly_en; + bool dma_d_ck160_dly_en; + bool dma_dbgport_phy_sel; + enum la_dma_data_type_t dma_data_type; +}; + +struct la_string_info { + u32 *octet; + u32 length; + u32 buffer_size; /*Byte*/ + u32 start_pos; + u32 end_pos; /*buf addr*/ + u32 smp_number_max; /*number of LA sample*/ +}; + +struct la_re_trig_info { + bool re_trig_en; + u16 re_trig_wait_cnt; + /*Re-trig*/ + bool la_re_trig_edge; + u8 la_re_and0_sel; + u8 la_re_and0_val; + bool la_re_and0_inv; +}; + +struct la_adv_trig_info { /*AND0~AND7*/ + bool adv_trig_en; /*SW ctrl value*/ + /*AND1*/ + u32 la_and1_mask; /*sel all 0 = disable*/ + u32 la_and1_val; + bool la_and1_inv; + /*AND2*/ + bool la_and2_en; + bool la_and2_inv; + u32 la_and2_val; + u32 la_and2_mask; + enum la_trig_sign_t la_and2_sign; /*0: unsigned, 1:signed, 2:norm*/ + /*AND3*/ + bool la_and3_en; + bool la_and3_inv; + u32 la_and3_val; + u32 la_and3_mask; + enum la_trig_sign_t la_and3_sign; /*0: unsigned, 1:signed, 2:norm*/ + /*AND4*/ + bool la_and4_en; + u16 la_and4_rate; /*rate_idx*/ + bool la_and4_inv; + /*AND5*/ + enum la_state_trig_t la_and5_sel; + bool la_and5_inv; + u8 la_and5_val; + /*AND6*/ + enum la_state_trig_t la_and6_sel; + bool la_and6_inv; + u8 la_and6_val; + /*AND7*/ + enum la_state_trig_t la_and7_sel; + bool la_and7_inv; + u8 la_and7_val; +}; + +struct la_trig_mac_info { + bool la_mac_trig_en; /*sw tag*/ + bool la_mac_and0_en; + u8 la_mac_and0_sel; /*0~2: cca, crc_er, crc_ok*/ + u8 la_mac_and0_mac_sel; /*0: true mac, 1: pmac*/ + bool la_mac_and1_en; + bool la_mac_and2_en; + u8 la_mac_and2_frame_sel; /*6-bit mac hdr*/ +}; + +struct la_mac_cfg_info { + enum la_buff_mode_t mac_la_buf_sel; + bool mac_alloc_success; + u32 la_trigger_time; /*mu sec*/ + u8 mac_la_en; + u8 mac_la_restart_en; + u8 mac_la_timeout_en; + u8 mac_la_data_loss_imr;/*Error flag mask bit for LA data loss due to pktbuffer busy */ + u8 mac_la_timeout_val; /*0:1s, 1:2s, 2:4s, 3:8s*/ +}; + +struct bb_la_cr_info { + u32 la_clk_en; + u32 la_clk_en_m; + u32 la_en; + u32 la_en_m; + u32 dma_dbgport_base_n; + u32 dma_dbgport_base_n_m; + u32 dma_a_path_sel; + u32 dma_a_path_sel_m; + u32 dma_b_path_sel; + u32 dma_b_path_sel_m; + u32 dma_c_path_sel; + u32 dma_c_path_sel_m; + u32 dma_d_path_sel; + u32 dma_d_path_sel_m; + u32 dma_a_src_sel; + u32 dma_a_src_sel_m; + u32 dma_b_src_sel; + u32 dma_b_src_sel_m; + u32 dma_c_src_sel; + u32 dma_c_src_sel_m; + u32 dma_d_src_sel; + u32 dma_d_src_sel_m; + u32 la_smp_rate; + u32 la_smp_rate_m; + u32 rdrdy_3_phase_en; + u32 rdrdy_3_phase_en_m; + u32 la_trigger_edge; + u32 la_trigger_edge_m; + u32 dma_hdr_sel_63; + u32 dma_hdr_sel_63_m; + u32 dma_hdr_sel_62; + u32 dma_hdr_sel_62_m; + u32 dma_hdr_sel_61; + u32 dma_hdr_sel_61_m; + u32 dma_hdr_sel_60; + u32 dma_hdr_sel_60_m; + u32 dma_a_ck160_dly_en; + u32 dma_a_ck160_dly_en_m; + u32 dma_b_ck160_dly_en; + u32 dma_b_ck160_dly_en_m; + u32 dma_dbgport_phy_sel; + u32 dma_dbgport_phy_sel_m; + u32 dma_data_type; + u32 dma_data_type_m; + u32 r_dma_rdrdy; + u32 r_dma_rdrdy_m; + u32 la_and0_bit_sel; + u32 la_and0_bit_sel_m; + u32 la_trigger_cnt; + u32 la_trigger_cnt_m; + u32 and0_trig_disable; + u32 and0_trig_disable_m; + u32 la_and1_inv; + u32 la_and1_inv_m; + u32 la_and2_en; + u32 la_and2_en_m; + u32 la_and2_inv; + u32 la_and2_inv_m; + u32 la_and3_en; + u32 la_and3_en_m; + u32 la_and3_inv; + u32 la_and3_inv_m; + u32 la_and4_en; + u32 la_and4_en_m; + u32 la_and4_rate; + u32 la_and4_rate_m; + u32 la_and4_inv; + u32 la_and4_inv_m; + u32 la_and1_mask; + u32 la_and1_mask_m; + u32 la_and1_val; + u32 la_and1_val_m; + u32 la_and2_mask; + u32 la_and2_mask_m; + u32 la_and2_val; + u32 la_and2_val_m; + u32 la_and3_mask; + u32 la_and3_mask_m; + u32 la_and3_val; + u32 la_and3_val_m; + u32 la_and5_sel; + u32 la_and5_sel_m; + u32 la_and5_val; + u32 la_and5_val_m; + u32 la_and5_inv; + u32 la_and5_inv_m; + u32 la_and6_sel; + u32 la_and6_sel_m; + u32 la_and6_val; + u32 la_and6_val_m; + u32 la_and6_inv; + u32 la_and6_inv_m; + u32 la_and7_sel; + u32 la_and7_sel_m; + u32 la_and7_val; + u32 la_and7_val_m; + u32 la_and7_inv; + u32 la_and7_inv_m; + u32 la_brk_sel; + u32 la_brk_sel_m; + u32 la_mac_and1_en; + u32 la_mac_and1_en_m; + u32 la_mac_and2_en; + u32 la_mac_and2_en_m; + u32 la_mac_and2_frame_sel; + u32 la_mac_and2_frame_sel_m; + u32 la_mac_and0_sel; + u32 la_mac_and0_sel_m; + u32 la_mac_and0_en; + u32 la_mac_and0_en_m; + u32 la_mac_and0_mac_sel; + u32 la_mac_and0_mac_sel_m; + u32 la_and2_sign; + u32 la_and2_sign_m; + u32 la_and3_sign; + u32 la_and3_sign_m; + u32 la_re_trig_edge; + u32 la_re_trig_edge_m; + u32 la_re_and1_sel; + u32 la_re_and1_sel_m; + u32 la_re_and1_val; + u32 la_re_and1_val_m; + u32 la_re_and1_inv; + u32 la_re_and1_inv_m; +}; + +struct bb_la_mode_info { + struct bb_la_cr_info bb_la_cr_i; + struct la_string_info la_string_i; + enum la_mode_state_t la_mode_state; + u32 la_dbg_port; /*[31:16]:DBG_IP, [15:0]:DBG_PORT*/ + u32 la_count; /*curr value*/ + u32 la_count_max; + u32 smp_number; + u32 txff_page; + bool not_stop_trig; /*set impossible trigger condition*/ + u8 la_basic_mode_sel; /*0:bb_mode, mac mode*/ + /*[General setting]*/ + u8 la_polling_cnt; + u8 la_trigger_cnt; + enum la_bb_trig_edge la_trigger_edge; + enum la_bb_smp_clk la_smp_rate; + /*[AND-0 sel]*/ + bool la_and0_disable; + u32 la_and0_bit_sel; /*And0 trigger bit sel*/ + struct la_dma_info la_dma_i; + struct la_re_trig_info la_re_trig_i; + struct la_adv_trig_info adv_trig_i; + struct la_trig_mac_info la_trig_mac_i; + struct la_mac_cfg_info la_mac_cfg_i; /*MAC CR Control*/ + struct la_print_info la_print_i; + bool la_ptrn_chk_en; + struct la_ptrn_chk_info la_ptrn_chk_i[LA_CHK_PTRN_NUM]; + enum la_run_mode_t la_run_mode; + struct halbb_timer_info la_timer_i; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_la_re_trig_watchdog(struct bb_info *bb); +void halbb_la_run(struct bb_info *bb); +void halbb_la_deinit(struct bb_info *bb); +void halbb_la_init(struct bb_info *bb); +void halbb_cr_cfg_la_init(struct bb_info *bb); +void halbb_la_io_en(struct bb_info *bb); +void halbb_la_timer_init(struct bb_info *bb); +void halbb_la_callback(void *context); +void halbb_la_cmd_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, + u32 *_out_len); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_la_mode_ex.h b/phl/hal_g6/phy/bb/halbb_la_mode_ex.h new file mode 100644 index 0000000..c087549 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_la_mode_ex.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_LA_MODE_EX_H__ +#define __HALBB_LA_MODE_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_math_lib.c b/phl/hal_g6/phy/bb/halbb_math_lib.c new file mode 100644 index 0000000..bb1dc13 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_math_lib.c @@ -0,0 +1,426 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +const u32 db_invert_table[12][8] = { + {10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */ + {64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */ + {401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */ + {316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */ + {1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */ + {12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */ + {79433, 100000, 125893, 158489, 199526, 251189, 316228, + 398107}, /* @U(32,0) */ + {501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262, + 2511886}, /* @U(32,0) */ + {3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254, + 15848932}, /* @U(32,0) */ + {19952623, 25118864, 31622777, 39810717, 50118723, 63095734, + 79432823, 100000000}, /* @U(32,0) */ + {125892541, 158489319, 199526232, 251188643, 316227766, 398107171, + 501187234, 630957345}, /* @U(32,0) */ + {794328235, 1000000000, 1258925412, 1584893192, 1995262315, + 2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */ + +/*Y = 10*log(X)*/ +s32 halbb_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit) +{ + s32 Y, integer = 0, decimal = 0; + u32 i; + + if (X == 0) + X = 1; /* @log2(x), x can't be 0 */ + + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { + integer = i; + if (i > 0) { + /*decimal is 0.5dB*3=1.5dB~=2dB */ + decimal = (X & BIT(i - 1)) ? 2 : 0; + } + break; + } + } + + Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */ + + return Y; +} + +s32 halbb_sign_conversion(s32 val, u32 total_bit) +{ + if (val & BIT(total_bit - 1)) + val -= BIT(total_bit); + + return val; +} + +/*threshold must form low to high*/ +u8 halbb_find_intrvl(struct bb_info *bb, u16 val, u8 *threshold, u8 len) +{ + u8 i = 0; + u8 ret_val = 0; + u8 max_th = threshold[len - 1]; + + for (i = 0; i < len; i++) { + if (val < threshold[i]) { + ret_val = i; + break; + } else if (val >= max_th) { + ret_val = len; + break; + } + } + + return ret_val; +} + +void halbb_seq_sorting(struct bb_info *bb, u32 *val, u32 *idx, u32 *idx_out, + u8 seq_length) +{ + u8 i = 0, j = 0, tmp = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) + idx[i] = i; + + for (i = 0; i < (seq_length - 1); i++) { + tmp = seq_length - 1 - i; /*to prevent WIN WHQL warning*/ + for (j = 0; j < tmp; j++) { + + tmp_a = val[j]; + tmp_b = val[j + 1]; + + tmp_idx_a = idx[j]; + tmp_idx_b = idx[j + 1]; + + if (tmp_a < tmp_b) { + val[j] = tmp_b; + val[j + 1] = tmp_a; + + idx[j] = tmp_idx_b; + idx[j + 1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) + idx_out[idx[i]] = i + 1; +} + +u32 halbb_convert_to_db(u64 val) +{ + u8 i; + u8 j; + u32 dB; + + if (val >= db_invert_table[11][7]) + return 96; /* @maximum 96 dB */ + + for (i = 0; i < 12; i++) { + if (i <= 2 && (val << FRAC_BITS) <= db_invert_table[i][7]) + break; + else if (i > 2 && val <= db_invert_table[i][7]) + break; + } + + for (j = 0; j < 8; j++) { + if (i <= 2 && (val << FRAC_BITS) <= db_invert_table[i][j]) + break; + else if (i > 2 && i < 12 && val <= db_invert_table[i][j]) + break; + } + + /*special cases*/ + if (j == 0 && i == 0) + goto end; + + if (i == 3 && j == 0) { + if (db_invert_table[3][0] - val > + val - (db_invert_table[2][7] >> FRAC_BITS)) { + i = 2; + j = 7; + } + goto end; + } + + if (i < 3) + val = val << FRAC_BITS; /*@elements of row 0~2 shift left*/ + + /*compare difference to get precise dB*/ + if (j == 0) { + if (db_invert_table[i][j] - val > + val - db_invert_table[i - 1][7]) { + i = i - 1; + j = 7; + } + } else { + if (db_invert_table[i][j] - val > + val - db_invert_table[i][j - 1]) { + j = j - 1; + } + } +end: + dB = (i << 3) + j + 1; + + return dB; +} + +u64 halbb_db_2_linear(u32 val) +{ + u8 i = 0; + u8 j = 0; + u64 linear = 0; + + val = val & 0xFF; + + /* @1dB~96dB */ + if (val > 96) { + val = 96; + } else if (val < 1) { + linear = 1; + return linear; + } + + i = (u8)((val - 1) >> 3); + j = (u8)(val - 1) - (i << 3); + + linear = db_invert_table[i][j]; + + if (i > 2) + linear = linear << FRAC_BITS; + + return linear; +} + +u16 halbb_show_fraction_num(u32 frac_val, u8 bit_num) +{ + u8 i = 0; + u16 val = 0; + u16 base = 500; /* Fix to 3 digit after the decimal point*/ + + for (i = bit_num; i > 0; i--) { + if (frac_val & BIT(i - 1)) + val += (base >> (bit_num - i)); + } + return val; +} + +u32 halbb_show_fraction_num_opt(u32 frac_val, u8 bit_num, u8 decimal_place) +{ + u8 i = 0; + u32 val = 0; + u32 base = 5; + + if (decimal_place == 0) + return 0; + + if (decimal_place > 9) + decimal_place = 9; + + for (i = 1; i < decimal_place; i++) + base *= 10; + + for (i = bit_num; i > 0; i--) { + if (frac_val & BIT(i - 1)) + val += (base >> (bit_num - i)); + } + return val; +} + +u16 halbb_ones_num_in_bitmap(u64 val, u8 size) +{ + u8 i = 0; + u8 ones_num = 0; + + for (i = 0; i < size; i++) { + if (val & BIT(0)) + ones_num++; + + val = val >> 1; + } + + return ones_num; +} + +u64 halbb_gen_mask_from_0(u8 mask_num) +{ + u8 i = 0; + u64 bitmask = 0; + + if (mask_num > 64 || mask_num == 0) + return 0; + + for (i = 0; i < mask_num; i++) + bitmask = (bitmask << 1) | BIT(0); + + return bitmask; +} + +u64 halbb_gen_mask(u8 up_num, u8 low_num) +{ + if (up_num < low_num) + return 0; + + return (halbb_gen_mask_from_0(up_num - low_num + 1) << low_num); +} + +u32 halbb_cal_bit_shift(u32 bit_mask) +{ + u32 i; + + for (i = 0; i <= 31; i++) { + if ((bit_mask >> i) & BIT0) + break; + } + return i; +} + +s32 halbb_cnvrt_2_sign(u32 val, u8 bit_num) +{ + if (bit_num > 32) + return (s32)val; + + if (val & BIT(bit_num - 1)) /*Sign BIT*/ + val -= (1 << bit_num); /*@2's*/ + + return val; +} + +s64 halbb_cnvrt_2_sign_64(u64 val, u8 bit_num) +{ + u64 one = 1; + s64 val_sign = (s64)val; + + if (bit_num >= 64) + return (s64)val; + + if (val & (one << (bit_num - 1))) /*Sign BIT*/ + val_sign = val - (one << bit_num); /*@2's*/ + + return val_sign; +} + +void halbb_print_sign_frac_digit(struct bb_info *bb, u32 val, u8 total_bit_num, + u8 frac_bit_num, char *buf, u16 buf_size) +{ + s32 val_s32 = (s32)val; + u32 val_abs = 0; + u32 mask_frac = 0; + u32 frac_digit = 0; + + val_abs = ABS_32(val_s32); + mask_frac = (u32)halbb_gen_mask_from_0(frac_bit_num); + frac_digit = halbb_show_fraction_num(val_abs & mask_frac, frac_bit_num); + + if (frac_bit_num == 1) { + frac_digit = (val & 0x1) * 5; + _os_snprintf(buf, buf_size, "%s%d.%d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else if (frac_bit_num == 2) { + frac_digit = (val & 0x3) * 25; + _os_snprintf(buf, buf_size, "%s%d.%02d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else if (frac_bit_num == 3) { + frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 3); + _os_snprintf(buf, buf_size, "%s%d.%03d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else if (frac_bit_num == 4) { + frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 4); + _os_snprintf(buf, buf_size, "%s%d.%04d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else if (frac_bit_num == 5) { + frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 5); + _os_snprintf(buf, buf_size, "%s%d.%05d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else { + frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 8); + _os_snprintf(buf, buf_size, "%s%d.%08d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } +} + +char *halbb_print_sign_frac_digit2(struct bb_info *bb, u32 val, u8 total_bit_num, + u8 frac_bit_num) +{ + char *buf = bb->dbg_buf; + u16 buf_size = HALBB_SNPRINT_SIZE; + s32 val_s32 = (s32)val; + u32 val_abs = 0; + u32 mask_frac = 0; + u16 frac_digit = 0; + + val_abs = ABS_32(val_s32); + mask_frac = (u32)halbb_gen_mask_from_0(frac_bit_num); + if (frac_bit_num == 1) { + frac_digit = (val & 0x1) * 5; + _os_snprintf(buf, buf_size, "%s%d.%d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else if (frac_bit_num == 2) { + frac_digit = (val & 0x3) * 25; + _os_snprintf(buf, buf_size, "%s%d.%02d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } else { + frac_digit = halbb_show_fraction_num(val_abs & mask_frac, frac_bit_num); + _os_snprintf(buf, buf_size, "%s%d.%03d", (val_s32 >= 0) ? "" : "-", + val_abs >> frac_bit_num, frac_digit); + } + + return buf; +} + +void halbb_print_buff_64(struct bb_info *bb, u8 *addr, u16 length) /*unit: Byte*/ +{ + u64 *buff_tmp = NULL; + u8 print_len = length >> 3; + u8 i; + + if (length % 8) + print_len++; + + buff_tmp = (u64 *)addr; + + for (i = 0; i < print_len; i++) { + BB_TRACE("[%02d]0x%016llx\n", i, buff_tmp[i]); + } +} + +void halbb_print_buff_32(struct bb_info *bb, u8 *addr, u16 length) /*unit: Byte*/ +{ + u32 *buff_tmp = NULL; + u8 print_len = length >> 2; + u8 i; + + if (length % 4) + print_len++; + + buff_tmp = (u32 *)addr; + + for (i = 0; i < print_len; i++) { + BB_TRACE("0x%08x\n", buff_tmp[i]); + } +} + diff --git a/phl/hal_g6/phy/bb/halbb_math_lib.h b/phl/hal_g6/phy/bb/halbb_math_lib.h new file mode 100644 index 0000000..1351b38 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_math_lib.h @@ -0,0 +1,121 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_MATH_LIB_H__ +#define __HALBB_MATH_LIB_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define RFREGOFFSETMASK 0xfffff + +#define KB_2_MB(val) ((val) >> 10) + +#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) +#define DIFF_2(_x_, _y_) (((_x_) >= (_y_)) ? ((_x_) - (_y_)) : ((_y_) - (_x_))) +#define SUBTRACT_TO_0(_x_, _y_) (((_x_) >= (_y_)) ? ((_x_) - (_y_)) : 0) + +#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) +#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) +#define NOT_GREATER(_x_, _y_) (((_x_) > (_y_)) ? (_y_) : (_x_)) + + +#define BYTE_DUPLICATE_2_DWORD(B0) \ + (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) + +#define BYTE_2_DWORD(B3, B2, B1, B0) \ + (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) +#define BYTE_2_WORD(B1, B0) \ + (((B1) << 8) | (B0)) +#define BIT_2_BYTE(B3, B2, B1, B0) \ + (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) + +#define NIBBLE_2_WORD(B3, B2, B1, B0) \ + ((((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) |\ + (((B1) & 0xf) << 4) | ((B0) & 0xf)) + +#define NIBBLE_2_DWORD(B7, B6, B5, B4, B3, B2, B1, B0) \ + ((((B7) & 0xf) << 28) | (((B6) & 0xf) << 24) | \ + (((B5) & 0xf) << 20) | (((B4) & 0xf) << 16) | \ + (((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) | \ + (((B1) & 0xf) << 4) | ((B0) & 0xf)) + +#if PLATFOM_IS_LITTLE_ENDIAN +#define SWAP4BYTE(x) ((u32)(x)) +#else +#define SWAP4BYTE(x) \ + ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) +#endif + +#define HALBB_DIV(a, b) ((b) ? ((a) / (b)) : 0) +#define ABS_32(X) (((X) & BIT(31)) ? (0 - (X)) : (X)) +#define ABS_16(X) (((X) & BIT(15)) ? (0 - (X)) : (X)) +#define ABS_8(X) (((X) & BIT(7)) ? (0 - (X)) : (X)) +#define DIVIDED_2(X) ((X) >> 1) +#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5) +#define DIVIDED_4(X) ((X) >> 2) + + +#define WEIGHTING_AVG_2(v1, w1, v2, w2) \ + (((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1))) +#define MA_ACC(old, new_val, ma, ma_max) ((old) - ((old << (ma_max - ma)) >> (ma_max)) + (new_val << (ma_max - ma))) +#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma)) + +#define FRAC_BITS 3 + + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +s32 halbb_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit); +s32 halbb_sign_conversion(s32 val, u32 total_bit); +u8 halbb_find_intrvl(struct bb_info *bb, u16 val, u8 *threshold, u8 len); +void halbb_seq_sorting(struct bb_info *bb, u32 *val, u32 *idx, u32 *idx_out, + u8 seq_length); +u16 halbb_show_fraction_num(u32 frac_val, u8 bit_num); +u16 halbb_ones_num_in_bitmap(u64 val, u8 size); +u64 halbb_gen_mask_from_0(u8 mask_num); +u64 halbb_gen_mask(u8 up_num, u8 low_num); +u32 halbb_cal_bit_shift(u32 bit_mask); +s32 halbb_cnvrt_2_sign(u32 val, u8 bit_num); +s64 halbb_cnvrt_2_sign_64(u64 val, u8 bit_num); +void halbb_print_sign_frac_digit(struct bb_info *bb, u32 val, u8 total_bit_num, + u8 frac_bit_num, char *buf, u16 buf_size); +char *halbb_print_sign_frac_digit2(struct bb_info *bb, u32 val, u8 total_bit_num, + u8 frac_bit_num); +void halbb_print_buff_64(struct bb_info *bb, u8 *addr, u16 length); +void halbb_print_buff_32(struct bb_info *bb, u8 *addr, u16 length); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_math_lib_ex.h b/phl/hal_g6/phy/bb/halbb_math_lib_ex.h new file mode 100644 index 0000000..e31c226 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_math_lib_ex.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_MATH_LIB_EX_H__ +#define __HALBB_MATH_LIB_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +u32 halbb_convert_to_db(u64 val); +u64 halbb_db_2_linear(u32 val); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_mp.c b/phl/hal_g6/phy/bb/halbb_mp.c new file mode 100644 index 0000000..403cf6c --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_mp.c @@ -0,0 +1,853 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index, + enum phl_phy_idx phy_idx) +{ + u32 tx_ok; + + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + if (halbb_is_cck_rate(bb, (u16)rate_index)) + tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m); + else + tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); + return (u16)tx_ok; +} + +u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0, he_ok = 0; + u32 crc_ok; + + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + if (phy_idx == HW_PHY_0) + cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m); + else + cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m); + + ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); + ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx); + vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx); + he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx); + + crc_ok = cck_ok + ofdm_ok + ht_ok + vht_ok + he_ok; + + // === [Reset cnt] === // + if (crc_ok == 65535) { + halbb_mp_reset_cnt(bb); + crc_ok = 0; + } + + return crc_ok; +} + +u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0, he_err = 0; + u32 crc_err; + + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + if (phy_idx == HW_PHY_0) + cck_err = halbb_get_reg(bb, cr->cnt_cck_crc32fail_p0, cr->cnt_cck_crc32fail_p0_m); + else + cck_err = halbb_get_reg(bb, cr->cnt_cck_crc32fail_p1, cr->cnt_cck_crc32fail_p1_m); + + ofdm_err = halbb_get_reg_cmn(bb, cr->cnt_l_crc_err, cr->cnt_l_crc_err_m, phy_idx); + ht_err = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_err, cr->cnt_ht_crc_err_m, phy_idx); + vht_err = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_err, cr->cnt_vht_crc_err_m, phy_idx); + he_err = halbb_get_reg_cmn(bb, cr->cnt_he_crc_err, cr->cnt_he_crc_err_m, phy_idx); + + crc_err = cck_err + ofdm_err + ht_err + vht_err + he_err; + + // === [Reset cnt] === // + if (crc_err == 65535) { + halbb_mp_reset_cnt(bb); + crc_err = 0; + } + + return crc_err; +} + +void halbb_mp_reset_cnt(struct bb_info *bb) +{ + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + // PHY0 cnt reset + halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 1, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 0, HW_PHY_0); + // PHY1 cnt reset + halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 1, HW_PHY_1); + halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 0, HW_PHY_1); +} + +void halbb_mp_psts_setting(struct bb_info *bb, u32 ie_bitmap_setting) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (ie_bitmap_setting & BIT(IE00_CMN_CCK)) { + halbb_set_reg(bb, cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_he_mu_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_vht_mu, cr->phy_sts_bitmap_vht_mu_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_cck, cr->phy_sts_bitmap_cck_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_legacy, cr->phy_sts_bitmap_legacy_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_ht_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_vht, cr->phy_sts_bitmap_vht_m, BIT(IE00_CMN_CCK)); + halbb_set_reg(bb, cr->phy_sts_bitmap_he, cr->phy_sts_bitmap_he_m, BIT(IE00_CMN_CCK)); + } + if (ie_bitmap_setting & BIT(IE01_CMN_OFDM)) { + halbb_set_reg(bb, cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_he_mu_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_vht_mu, cr->phy_sts_bitmap_vht_mu_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_cck, cr->phy_sts_bitmap_cck_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_legacy, cr->phy_sts_bitmap_legacy_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_ht_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_vht, cr->phy_sts_bitmap_vht_m, BIT(IE01_CMN_OFDM)); + halbb_set_reg(bb, cr->phy_sts_bitmap_he, cr->phy_sts_bitmap_he_m, BIT(IE01_CMN_OFDM)); + } + + BB_DBG(bb, DBG_PHY_CONFIG, "[MP] physts ie bitmap setting : 0x%08x\n", ie_bitmap_setting); + + +} + +void +halbb_mp_get_psts_ie_bitmap(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + u32 *bitmap_ptr = &physts->physts_bitmap_recv; + u32 *mp_bitmap_ptr = &bb_mp_physts->ie_bitmap; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + mp_bitmap_ptr = bitmap_ptr; + +} + + +void +halbb_mp_get_psts_ie_00(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i; + struct mp_physts_rslt_0 *mp_psts_0 = &bb_mp_physts->mp_physts_rslt_0_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + mp_psts_0 = (struct mp_physts_rslt_0 *)psts_0; + +} + +void +halbb_mp_get_psts_ie_01(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + //struct bb_mp_psts *mp_physts = &bb->bb_mp_psts_i; + struct mp_physts_rslt_1 *mp_psts_1 = &bb_mp_physts->mp_physts_rslt_1_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + mp_psts_1 = (struct mp_physts_rslt_1 *)psts_1; + +} + +void +halbb_mp_get_psts(struct bb_info *bb , struct bb_mp_psts *bb_mp_physts) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // IE bitmap info // + halbb_mp_get_psts_ie_bitmap(bb , bb_mp_physts); + + // detail info of per IE // + if (bb_mp_physts->ie_bitmap & BIT(IE00_CMN_CCK)) { + halbb_mp_get_psts_ie_00(bb , bb_mp_physts); + } + if (bb_mp_physts->ie_bitmap & BIT(IE01_CMN_OFDM)) { + halbb_mp_get_psts_ie_01(bb , bb_mp_physts); + } +} + +void halbb_keeper_cond(struct bb_info *bb, bool keeper_en, u8 keeper_trig_cond, + u8 dbg_sel, enum phl_phy_idx phy_idx) +{ + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, keeper_en, + phy_idx); //0x0738[4] + halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond, + cr->sts_keeper_trig_cond_m, keeper_trig_cond, phy_idx); //0x0738[7:6] + halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, dbg_sel, + phy_idx); //0x0738[30:28] +} + +void halbb_dbg_port_sel(struct bb_info *bb, u16 dbg_port_sel, u8 dbg_port_ip_sel, + bool dbg_port_ref_clk_en, bool dbg_port_en) +{ + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + halbb_set_reg(bb, cr->dbg_port_sel, 0xfff, dbg_port_sel); // 0x20f0[11:0] + halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m, + dbg_port_ip_sel); // 0x20f0[23:16] + halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, + dbg_port_ref_clk_en); // 0x20f4[24] + halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, dbg_port_en); // 0x20f8[31] + +} + +u8 halbb_mp_get_rxevm(struct bb_info *bb, u8 user, u8 strm, bool rxevm_table) +{ + u8 rx_evm; + u8 mode; + u32 user_mask[4] = {0xff000000, 0xff0000, 0xff00, 0xff}; + + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + /*==== Error handling ====*/ + if ((user >= 4) || (strm >= 4)) { + BB_WARNING("Invalid User or Stream\n"); + return false; + } + /*=== [All tone] ===*/ + halbb_set_reg(bb, cr->rpt_tone_evm_idx, 0x3ff, 0); // Only use [9:0], Total [10:0] + halbb_set_reg_cmn(bb, cr->rpt_tone_evm_idx, 0x3ff, 0, HW_PHY_1); + /*=== [Switch MUX] ===*/ + halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0); + halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1); + halbb_set_reg(bb, cr->dbg_port_ip_sel, 0x1f, 2); // Only use [4:0], Total [7:0] + halbb_set_reg(bb, cr->dbg_port_sel, 0xf0, 1); // Only use [7:4], Total [15:0] + + mode = user + 1 + rxevm_table * 8; + + halbb_set_reg(bb, cr->dbg_port_sel, 0xf, mode); // Only use [3:0], Total [15:0] + + rx_evm = (u8)halbb_get_reg(bb, cr->dbg32_d, user_mask[strm]); + return rx_evm; +} + +struct rxevm_physts halbb_mp_get_rxevm_physts(struct bb_info *bb, + enum phl_phy_idx phy_idx) +{ + // Note: Only supports 2SS ! // + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + bool is_cck; + u8 i = 0; + u32 rxevm_tmp = 0; + u8 addr_ofst[2] = {0, 20}; + u32 dbg_port = 0; + u16 tmp = 0; + u32 bitmap[7] = {cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_vht_mu, + cr->phy_sts_bitmap_trigbase, cr->phy_sts_bitmap_legacy, + cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_vht, + cr->phy_sts_bitmap_he}; + u32 bitmap_m[7] = {cr->phy_sts_bitmap_he_mu_m, + cr->phy_sts_bitmap_vht_mu_m, + cr->phy_sts_bitmap_trigbase_m, + cr->phy_sts_bitmap_legacy_m, cr->phy_sts_bitmap_ht_m, + cr->phy_sts_bitmap_vht_m, cr->phy_sts_bitmap_he_m}; + u32 bitmap_restore[7] = {0}; + + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] halbb_mp_get_rxevm_physts==========================>\n"); + + //=== Backup Bitmap value ===// + for (i = 0; i < 7; i++) + bitmap_restore[i] = halbb_get_reg_cmn(bb, bitmap[i], bitmap_m[i], phy_idx); + //=== Set Bitmap ===// + for (i = 0; i < 7; i++) + halbb_set_reg_cmn(bb, bitmap[i], bitmap_m[i], 0x300002, phy_idx); + + // Set keeper condition // + halbb_keeper_cond(bb, true, 0x1, 0x2, phy_idx); + + // DBG port polling // + if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + tmp = (phy_idx == HW_PHY_0 ? 0x700 : 0x701); + halbb_dbg_port_sel(bb, tmp, 0x1, 0x0, 0x1); + } else { + dbg_port = halbb_get_bb_dbg_port_idx(bb); + BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port); + return bb->rxevm; + } + + // Config user0 + halbb_set_reg_cmn(bb, cr->sts_user_sel, cr->sts_user_sel_m, 0, phy_idx); + + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, phy_idx); + + halbb_delay_us(bb, 2); + + if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) { + // Determine CCK pkt + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 1, phy_idx); + is_cck = (halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xf, phy_idx) == 11) ? true : false; + + // CCK + if (is_cck) { + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 5, phy_idx); + rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, phy_idx); // Only use [15:8], Total [31:0] + bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 = (u8)rxevm_tmp; + bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 = 0; + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm][CCK][Phy-%d] rxevm_ss_0=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0); + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm][CCK][Phy-%d] rxevm_ss_1=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1); + } else { + if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B)) { + for (i = 0; i < 2; i++) { + // Usr0 + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 15 + addr_ofst[i], phy_idx); + rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xffff00, phy_idx); // Only use [23:8], Total [31:0] + bb->rxevm.rxevm_seg[i].rxevm_user[0].rxevm_ss_0 = (rxevm_tmp & 0xff); + bb->rxevm.rxevm_seg[i].rxevm_user[0].rxevm_ss_1 = ((rxevm_tmp & 0xff00) >> 8); + + // Usr1 + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 19 + addr_ofst[i], phy_idx); + bb->rxevm.rxevm_seg[i].rxevm_user[1].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); // Only use [31:24], Total [31:0] + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 18 + addr_ofst[i], phy_idx); + bb->rxevm.rxevm_seg[i].rxevm_user[1].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff, phy_idx); // Only use [7:0], Total [31:0] + // Usr2 + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 22 + addr_ofst[i], phy_idx); + rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xffff00, phy_idx); // Only use [23:8], Total [31:0] + bb->rxevm.rxevm_seg[i].rxevm_user[2].rxevm_ss_0 = (rxevm_tmp & 0xff); + bb->rxevm.rxevm_seg[i].rxevm_user[2].rxevm_ss_1 = ((rxevm_tmp & 0xff00) >> 8); + // Usr3 + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 26 + addr_ofst[i], phy_idx); + bb->rxevm.rxevm_seg[i].rxevm_user[3].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); // Only use [31:24], Total [31:0] + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 29 + addr_ofst[i], phy_idx); + bb->rxevm.rxevm_seg[i].rxevm_user[3].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff, phy_idx); // Only use [7:0], Total [31:0] + } + } else { + // Usr0 + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 15, phy_idx); + bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 19, phy_idx); + bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] [Phy-%d] rxevm_ss_0=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0); + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] [Phy-%d] rxevm_ss_1=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1); + } + } + bb->bb_cmn_backup_i.last_rxevm_rpt = bb->rxevm; + } else { + BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] No crc_ok\n"); + bb->rxevm = bb->bb_cmn_backup_i.last_rxevm_rpt; + } + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, phy_idx); + + halbb_release_bb_dbg_port(bb); + + //=== Restore Bitmap value ===// + //for (i = 0; i < 7; i++) + // halbb_set_reg_cmn(bb, bitmap[i], bitmap_m[i], bitmap_restore[i], phy_idx); + + return bb->rxevm; +} +/* +u16 halbb_mp_get_pwdb_diff(struct bb_info *bb, enum rf_path path) +{ + u16 pwdb_diff; + u32 rpt_addr[4] = {0x4048, 0x4060, 0x4078, 0x4090}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (path > RF_PATH_D) { + BB_WARNING("Invalid Path\n"); + return false; + } + + pwdb_diff = (u16)halbb_get_reg(bb, rpt_addr[path], 0xff800); + return pwdb_diff; + +} +*/ +u8 halbb_mp_get_rssi(struct bb_info *bb, enum rf_path path) +{ + u8 rssi; + u32 dbg_port = 0; +#if 0 + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + /*==== Error handling ====*/ + if (path > RF_PATH_D) { + BB_WARNING("Invalid Path\n"); + return false; + } + + rssi = psts_h->rssi[path]; + + BB_DBG(bb, DBG_PHY_CONFIG, "[MP] rssi for Path-%d : %d\n", path, rssi); +#else + // RSSI_FD + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + + // Phy0 / 1 + halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, 1, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond, cr->sts_keeper_trig_cond_m, 1, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, 2, HW_PHY_0); + + if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0); + halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1); + halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m, 1); + halbb_set_reg(bb, cr->dbg_port_sel, 0xf00, 7); // Only use [11:8], Total [15:0] + + halbb_set_reg(bb, cr->dbg_port_sel, 0xff, 0); // Only use [7:0], Total [15:0] + } else { + dbg_port = halbb_get_bb_dbg_port_idx(bb); + BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port); + return bb->bb_cmn_backup_i.last_rssi; + } + + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, HW_PHY_0); + + halbb_delay_us(bb, 2); + + if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) { + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 3, HW_PHY_0); + rssi = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, HW_PHY_0); // Only use [23:8], Total [31:0] + bb->bb_cmn_backup_i.last_rssi = rssi; + } else { + rssi = bb->bb_cmn_backup_i.last_rssi; + } + + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, HW_PHY_0); + + halbb_release_bb_dbg_port(bb); +#endif + return rssi; +} + +s32 halbb_rssi_cal(struct bb_info *bb, u8 rssi_0, u8 rssi_1, bool is_higher_rssi_path, enum phl_phy_idx phy_idx) +{ + u8 rssi_diff = rssi_0 - rssi_1; + s32 rssi_cal; + u64 alpha_tmp; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (rssi_diff == 0) + return 0; + + rssi_diff = rssi_diff % 2 ? (rssi_diff + 1) >> 1 : rssi_diff >> 1; + + alpha_tmp = halbb_db_2_linear((u32) rssi_diff); + + alpha_tmp = (alpha_tmp >> 2) % 2 ? (alpha_tmp >> FRAC_BITS) + 1 : alpha_tmp >> FRAC_BITS; + + if (is_higher_rssi_path) + rssi_cal = halbb_convert_to_db(alpha_tmp) - + halbb_convert_to_db(alpha_tmp + 1) + 3; + else + rssi_cal = 3 - halbb_convert_to_db(alpha_tmp + 1); + + return rssi_cal; +} + +struct rssi_physts halbb_get_mp_rssi_physts(struct bb_info *bb, enum rf_path path, enum phl_phy_idx phy_idx) +{ + // RSSI_FD + struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; + struct bb_physts_info physts = bb->bb_physts_i; + struct bb_physts_rslt_hdr_info psts_h = physts.bb_physts_rslt_hdr_i; + struct bb_efuse_info efuse = bb->bb_efuse_i; + struct rssi_physts rssi_rpt; + bool rssi_0_high = psts_h.rssi[0] > psts_h.rssi[1] ? true : false; + s32 efuse_tmp = 0; + u8 band = 0; + u8 central_ch = bb->hal_com->band[phy_idx].cur_chandef.center_ch; + u8 RPL = 0; + u32 dbg_port = 0; + s32 cal_tmp[2] = {0}; + + halbb_mem_set(bb, &rssi_rpt,0,sizeof(rssi_rpt)); + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // 2G Band: (0) + // 5G Band: (1):Low, (2): Mid, (3):High + if (central_ch >= 0 && central_ch <= 14) + band = 0; + else if (central_ch >= 36 && central_ch <= 64) + band = 1; + else if (central_ch >= 100 && central_ch <= 144) + band = 2; + else if (central_ch >= 149 && central_ch <= 177) + band = 3; + else + band = 0; + + efuse_tmp = efuse.gain_offset[RF_PATH_A][band] - efuse.gain_offset[RF_PATH_B][band]; + + // Phy0 / 1 + halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, 1, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond, cr->sts_keeper_trig_cond_m, 1, HW_PHY_0); + halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, 2, HW_PHY_0); + + if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) { + halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0); + halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1); + halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m, 1); + halbb_set_reg(bb, cr->dbg_port_sel, 0xf00, 7); // Only use [11:8], Total [15:0] + + halbb_set_reg(bb, cr->dbg_port_sel, 0xff, 0); // Only use [7:0], Total [15:0] + } else { + dbg_port = halbb_get_bb_dbg_port_idx(bb); + BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port); + return bb->bb_cmn_backup_i.last_rssi_rpt; + } + + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, HW_PHY_0); + + halbb_delay_us(bb, 2); + + if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) { + halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 3, HW_PHY_0); + RPL = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, HW_PHY_0); // Only use [23:8], Total [31:0] + bb->bb_cmn_backup_i.last_rssi = RPL; + } else { + RPL = bb->bb_cmn_backup_i.last_rssi; + } + + halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, HW_PHY_0); + + halbb_release_bb_dbg_port(bb); + + if (path == RF_PATH_A) { + rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(RPL - 220); + rssi_rpt.rssi_seg[phy_idx].rssi[1] = 0; + } else if (path == RF_PATH_B) { + rssi_rpt.rssi_seg[phy_idx].rssi[0] = 0; + rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(RPL - 220); + } else { + if (rssi_0_high) { + if (psts_h.rssi[0] - psts_h.rssi[1] > 12) { + rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(RPL - 220 + 6); + rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(psts_h.rssi[1] - 220); + } else { + cal_tmp[0] = halbb_rssi_cal(bb, psts_h.rssi[0], psts_h.rssi[1], true, phy_idx); + cal_tmp[1] = halbb_rssi_cal(bb, psts_h.rssi[0], psts_h.rssi[1], false, phy_idx); + rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)((RPL - 220) + (cal_tmp[0] << 1)); + rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)((RPL - 220) + (efuse_tmp << 1) + (cal_tmp[1] << 1)); + } + } else { + if (psts_h.rssi[1] - psts_h.rssi[0] > 12) { + rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(psts_h.rssi[0] - 220); + rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(RPL - 220 + 6); + } else { + cal_tmp[0] = halbb_rssi_cal(bb, psts_h.rssi[1], psts_h.rssi[0], false, phy_idx); + cal_tmp[1] = halbb_rssi_cal(bb, psts_h.rssi[1], psts_h.rssi[0], true, phy_idx); + rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)((RPL - 220) + (cal_tmp[0] << 1)); + rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)((RPL - 220) + (efuse_tmp << 1) + (cal_tmp[1] << 1)); + } + } + } + return rssi_rpt; +} + +void halbb_mp_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct rxevm_physts rxevm; + + halbb_mem_set(bb, &rxevm,0,sizeof(rxevm)); + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "EVM({phy_idx (0~1)})\n"); + + } else if (_os_strcmp(input[1], "evm") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + + rxevm = halbb_mp_get_rxevm_physts(bb, (enum phl_phy_idx)val[0]); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[MP] [User 0] [SS0] RXEVM = -%d\n", + rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 >> 2); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[MP] [User 0] [SS1] RXEVM = -%d\n", + rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 >> 2); + + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_cr_cfg_mp_init(struct bb_info *bb) +{ + struct bb_rpt_info *rpt_info = &bb->bb_rpt_i; + struct bb_rpt_cr_info *cr = &rpt_info->bb_rpt_cr_i; + + switch (bb->cr_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + cr->cnt_ccktxon = CNT_CCKTXON_52AA; + cr->cnt_ccktxon_m = CNT_CCKTXON_52AA_M; + cr->cnt_ofdmtxon = CNT_OFDMTXON_52AA; + cr->cnt_ofdmtxon_m = CNT_OFDMTXON_52AA_M; + cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_52AA; + cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_52AA_M; + cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_52AA; + cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_52AA_M; + cr->cnt_l_crc_ok = CNT_L_CRC_OK_52AA; + cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_52AA_M; + cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_52AA; + cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_52AA_M; + cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_52AA; + cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_52AA_M; + cr->cnt_he_crc_ok = CNT_HE_CRC_OK_52AA; + cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_52AA_M; + cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_52AA; + cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_52AA_M; + cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_52AA; + cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_52AA_M; + cr->cnt_l_crc_err = CNT_L_CRC_ERR_52AA; + cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_52AA_M; + cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_52AA; + cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_52AA_M; + cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_52AA; + cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_52AA_M; + cr->cnt_he_crc_err = CNT_HE_CRC_ERR_52AA; + cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_52AA_M; + cr->rst_all_cnt = RST_ALL_CNT_52AA; + cr->rst_all_cnt_m = RST_ALL_CNT_52AA_M; + cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_52AA; + cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_52AA_M; + cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_52AA; + cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_52AA_M; + cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_52AA; + cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_52AA_M; + cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_52AA; + cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_52AA_M; + cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_52AA; + cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_52AA_M; + cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_52AA; + cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_52AA_M; + cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_52AA; + cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_52AA_M; + cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_52AA; + cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_52AA_M; + cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_52AA; + cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_52AA_M; + cr->dbg_port_en = DBG_PORT_EN_52AA; + cr->dbg_port_en_m = DBG_PORT_EN_52AA_M; + cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_52AA; + cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_52AA_M; + cr->dbg_port_sel = DBG_PORT_SEL_52AA; + cr->dbg_port_sel_m = DBG_PORT_SEL_52AA_M; + cr->dbg32_d = DBG32_D_52AA; + cr->dbg32_d_m = DBG32_D_52AA_M; + cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_52AA; + cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_52AA_M; + cr->sts_keeper_en = STS_KEEPER_EN_52AA; + cr->sts_keeper_en_m = STS_KEEPER_EN_52AA_M; + cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_52AA; + cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_52AA_M; + cr->sts_dbg_sel = STS_DBG_SEL_52AA; + cr->sts_dbg_sel_m = STS_DBG_SEL_52AA_M; + cr->sts_keeper_read = STS_KEEPER_READ_52AA; + cr->sts_keeper_read_m = STS_KEEPER_READ_52AA_M; + cr->sts_keeper_addr = STS_KEEPER_ADDR_52AA; + cr->sts_keeper_addr_m = STS_KEEPER_ADDR_52AA_M; + cr->sts_keeper_data = STS_KEEPER_DATA_52AA; + cr->sts_keeper_data_m = STS_KEEPER_DATA_52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->cnt_ccktxon = CNT_CCKTXON_A; + cr->cnt_ccktxon_m = CNT_CCKTXON_A_M; + cr->cnt_ofdmtxon = CNT_OFDMTXON_A; + cr->cnt_ofdmtxon_m = CNT_OFDMTXON_A_M; + cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_A; + cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_A_M; + cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_A; + cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_A_M; + cr->cnt_l_crc_ok = CNT_L_CRC_OK_A; + cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_A_M; + cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_A; + cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_A_M; + cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_A; + cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_A_M; + cr->cnt_he_crc_ok = CNT_HE_CRC_OK_A; + cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_A_M; + cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_A; + cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_A_M; + cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_A; + cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_A_M; + cr->cnt_l_crc_err = CNT_L_CRC_ERR_A; + cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_A_M; + cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_A; + cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_A_M; + cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_A; + cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_A_M; + cr->cnt_he_crc_err = CNT_HE_CRC_ERR_A; + cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_A_M; + cr->rst_all_cnt = RST_ALL_CNT_A; + cr->rst_all_cnt_m = RST_ALL_CNT_A_M; + cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_A; + cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_A_M; + cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_A; + cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_A_M; + cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_A; + cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_A_M; + cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_A; + cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_A_M; + cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_A; + cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_A_M; + cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_A; + cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_A_M; + cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_A; + cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_A_M; + cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_A; + cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_A_M; + cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_A; + cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_A_M; + cr->dbg_port_en = DBG_PORT_EN_A; + cr->dbg_port_en_m = DBG_PORT_EN_A_M; + cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_A; + cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_A_M; + cr->dbg_port_sel = DBG_PORT_SEL_A; + cr->dbg_port_sel_m = DBG_PORT_SEL_A_M; + cr->dbg32_d = DBG32_D_A; + cr->dbg32_d_m = DBG32_D_A_M; + cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_A; + cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_A_M; + cr->sts_keeper_en = STS_KEEPER_EN_A; + cr->sts_keeper_en_m = STS_KEEPER_EN_A_M; + cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_A; + cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_A_M; + cr->sts_dbg_sel = STS_DBG_SEL_A; + cr->sts_dbg_sel_m = STS_DBG_SEL_A_M; + cr->sts_keeper_read = STS_KEEPER_READ_A; + cr->sts_keeper_read_m = STS_KEEPER_READ_A_M; + cr->sts_keeper_addr = STS_KEEPER_ADDR_A; + cr->sts_keeper_addr_m = STS_KEEPER_ADDR_A_M; + cr->sts_keeper_data = STS_KEEPER_DATA_A; + cr->sts_keeper_data_m = STS_KEEPER_DATA_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->cnt_ccktxon = CNT_CCKTXON_C; + cr->cnt_ccktxon_m = CNT_CCKTXON_C_M; + cr->cnt_ofdmtxon = CNT_OFDMTXON_C; + cr->cnt_ofdmtxon_m = CNT_OFDMTXON_C_M; + cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_C; + cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_C_M; + cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_C; + cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_C_M; + cr->cnt_l_crc_ok = CNT_L_CRC_OK_C; + cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_C_M; + cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_C; + cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_C_M; + cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_C; + cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_C_M; + cr->cnt_he_crc_ok = CNT_HE_CRC_OK_C; + cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_C_M; + cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_C; + cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_C_M; + cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_C; + cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_C_M; + cr->cnt_l_crc_err = CNT_L_CRC_ERR_C; + cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_C_M; + cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_C; + cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_C_M; + cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_C; + cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_C_M; + cr->cnt_he_crc_err = CNT_HE_CRC_ERR_C; + cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_C_M; + cr->rst_all_cnt = RST_ALL_CNT_C; + cr->rst_all_cnt_m = RST_ALL_CNT_C_M; + cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_C; + cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_C_M; + cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_C; + cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_C_M; + cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_C; + cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_C_M; + cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_C; + cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_C_M; + cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_C; + cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_C_M; + cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_C; + cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_C_M; + cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_C; + cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_C_M; + cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_C; + cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_C_M; + cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_C; + cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_C_M; + cr->dbg_port_en = DBG_PORT_EN_C; + cr->dbg_port_en_m = DBG_PORT_EN_C_M; + cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_C; + cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_C_M; + cr->dbg_port_sel = DBG_PORT_SEL_C; + cr->dbg_port_sel_m = DBG_PORT_SEL_C_M; + cr->dbg32_d = DBG32_D_C; + cr->dbg32_d_m = DBG32_D_C_M; + cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_C; + cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_C_M; + cr->sts_keeper_en = STS_KEEPER_EN_C; + cr->sts_keeper_en_m = STS_KEEPER_EN_C_M; + cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_C; + cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_C_M; + cr->sts_dbg_sel = STS_DBG_SEL_C; + cr->sts_dbg_sel_m = STS_DBG_SEL_C_M; + cr->sts_keeper_read = STS_KEEPER_READ_C; + cr->sts_keeper_read_m = STS_KEEPER_READ_C_M; + cr->sts_keeper_addr = STS_KEEPER_ADDR_C; + cr->sts_keeper_addr_m = STS_KEEPER_ADDR_C_M; + cr->sts_keeper_data = STS_KEEPER_DATA_C; + cr->sts_keeper_data_m = STS_KEEPER_DATA_C_M; + cr->pw_dbm_rx0 = P0_L_TOT_PW_DBM_RX0_C; + cr->pw_dbm_rx0_m = P0_L_TOT_PW_DBM_RX0_C_M; + cr->sts_user_sel = STS_USER_SEL_C; + cr->sts_user_sel_m = STS_USER_SEL_C_M; + break; + #endif + + default: + break; + } +} + + diff --git a/phl/hal_g6/phy/bb/halbb_mp_ex.h b/phl/hal_g6/phy/bb/halbb_mp_ex.h new file mode 100644 index 0000000..cd3c510 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_mp_ex.h @@ -0,0 +1,217 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_MP_EX_H__ +#define __HALBB_MP_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define MAX_USER_NUM 4 + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_rpt_cr_info { + u32 cnt_ccktxon; + u32 cnt_ccktxon_m; + u32 cnt_ofdmtxon; + u32 cnt_ofdmtxon_m; + u32 cnt_cck_crc32ok_p0; + u32 cnt_cck_crc32ok_p0_m; + u32 cnt_cck_crc32ok_p1; + u32 cnt_cck_crc32ok_p1_m; + u32 cnt_l_crc_ok; + u32 cnt_l_crc_ok_m; + u32 cnt_ht_crc_ok; + u32 cnt_ht_crc_ok_m; + u32 cnt_vht_crc_ok; + u32 cnt_vht_crc_ok_m; + u32 cnt_he_crc_ok; + u32 cnt_he_crc_ok_m; + u32 cnt_cck_crc32fail_p0; + u32 cnt_cck_crc32fail_p0_m; + u32 cnt_cck_crc32fail_p1; + u32 cnt_cck_crc32fail_p1_m; + u32 cnt_l_crc_err; + u32 cnt_l_crc_err_m; + u32 cnt_ht_crc_err; + u32 cnt_ht_crc_err_m; + u32 cnt_vht_crc_err; + u32 cnt_vht_crc_err_m; + u32 cnt_he_crc_err; + u32 cnt_he_crc_err_m; + u32 rst_all_cnt; + u32 rst_all_cnt_m; + u32 phy_sts_bitmap_he_mu; + u32 phy_sts_bitmap_he_mu_m; + u32 phy_sts_bitmap_vht_mu; + u32 phy_sts_bitmap_vht_mu_m; + u32 phy_sts_bitmap_cck; + u32 phy_sts_bitmap_cck_m; + u32 phy_sts_bitmap_legacy; + u32 phy_sts_bitmap_legacy_m; + u32 phy_sts_bitmap_ht; + u32 phy_sts_bitmap_ht_m; + u32 phy_sts_bitmap_vht; + u32 phy_sts_bitmap_vht_m; + u32 phy_sts_bitmap_he; + u32 phy_sts_bitmap_he_m; + u32 rpt_tone_evm_idx; + u32 rpt_tone_evm_idx_m; + u32 dbg_port_ref_clk_en; + u32 dbg_port_ref_clk_en_m; + u32 dbg_port_en; + u32 dbg_port_en_m; + u32 dbg_port_ip_sel; + u32 dbg_port_ip_sel_m; + u32 dbg_port_sel; + u32 dbg_port_sel_m; + u32 dbg32_d; + u32 dbg32_d_m; + u32 phy_sts_bitmap_trigbase; + u32 phy_sts_bitmap_trigbase_m; + u32 sts_keeper_en; + u32 sts_keeper_en_m; + u32 sts_keeper_trig_cond; + u32 sts_keeper_trig_cond_m; + u32 sts_dbg_sel; + u32 sts_dbg_sel_m; + u32 sts_keeper_read; + u32 sts_keeper_read_m; + u32 sts_keeper_addr; + u32 sts_keeper_addr_m; + u32 sts_keeper_data; + u32 sts_keeper_data_m; + u32 pw_dbm_rx0; + u32 pw_dbm_rx0_m; + u32 path0_rssi_at_agc_rdy; + u32 path0_rssi_at_agc_rdy_m; + u32 path1_rssi_at_agc_rdy; + u32 path1_rssi_at_agc_rdy_m; + u32 sts_user_sel; + u32 sts_user_sel_m; +}; + +struct bb_rpt_info { + struct bb_rpt_cr_info bb_rpt_cr_i; +}; + +struct rxevm_usr { + u8 rxevm_ss_0; + u8 rxevm_ss_1; + u8 rxevm_ss_2; + u8 rxevm_ss_3; +}; + +struct rxevm_info { + struct rxevm_usr rxevm_user[MAX_USER_NUM]; + bool rxevm_valid; +}; + +struct rxevm_physts { + // Seg0/1 + struct rxevm_info rxevm_seg[2]; +}; + +struct rssi_i { + s32 rssi[4]; +}; + +struct rssi_physts { + // Seg0/1 + struct rssi_i rssi_seg[2]; +}; + +struct mp_physts_rslt_0 { + u8 rx_path_en_cck; + u8 cfo_avg_cck; + u8 evm_avg_cck; + u8 avg_idle_noise_pwr_cck; + u8 pop_idx_cck; +}; + +struct mp_physts_rslt_1 { + u8 rx_path_en; + s16 cfo_avg; /*S(12,2), -512~+511.75 kHz*/ + u8 evm_max; + u8 evm_min; + u8 snr_avg; + u8 cn_avg; + u8 avg_idle_noise_pwr; + u8 pop_idx; + u8 rxsc; + u8 ch_idx; + enum channel_width bw_idx; + bool is_su; /*if (not MU && not OFDMA), is_su = 1*/ + bool is_ldpc; + bool is_ndp; + bool is_stbc; + bool grant_bt; + bool is_awgn; + bool is_bf; +}; + +struct mp_physts_rslt_basic { + struct mp_physts_rslt_0 mp_physts_rslt_basic_0_i; + struct mp_physts_rslt_1 mp_physts_rslt_basic_1_i; + +}; + + +struct bb_mp_psts { + u32 ie_bitmap; + struct mp_physts_rslt_basic mp_physts_rslt_basic_i; + struct mp_physts_rslt_0 mp_physts_rslt_0_i; + struct mp_physts_rslt_1 mp_physts_rslt_1_i; +}; + + + +struct halbb_mp { + /*Tx ok count, statistics used in Mass Production Test.*/ + u64 tx_phy_ok_cnt; + /*Rx CRC32 ok/error count, statistics used in Mass Production Test.*/ + u64 rx_phy_crc_ok_cnt; + u64 rx_phy_crc_err_cnt; + /*The Value of IO operation is depend of MptActType.*/ + u32 io_ok_value; + u32 io_err_value; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index, + enum phl_phy_idx phy_idx); +u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx); +u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_mp_reset_cnt(struct bb_info *bb); +u8 halbb_mp_get_rxevm(struct bb_info *bb, u8 user, u8 strm, bool rxevm_table); +struct rxevm_physts halbb_mp_get_rxevm_physts(struct bb_info *bb, + enum phl_phy_idx phy_idx); +//u16 halbb_mp_get_pwdb_diff(struct bb_info *bb, enum rf_path path); +u8 halbb_mp_get_rssi(struct bb_info *bb, enum rf_path path); +struct rssi_physts halbb_get_mp_rssi_physts(struct bb_info *bb, enum rf_path path, enum phl_phy_idx phy_idx); +void halbb_mp_get_psts(struct bb_info *bb , struct bb_mp_psts *bb_mp_physts); +void halbb_mp_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_mp_init(struct bb_info *bb); +#endif diff --git a/phl/hal_g6/phy/bb/halbb_physts.c b/phl/hal_g6/phy/bb/halbb_physts.c new file mode 100644 index 0000000..bf4395e --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_physts.c @@ -0,0 +1,2702 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_PHYSTS_PARSING_SUPPORT + +static const u32 phy_sts_dbg[] = { + 0x34006A8A,//HDR + 0x00003632, + 0x03020101,//IE-1 +#if 0 //to save memory + 0x8DF0CA04, + 0x0b797f1e, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020102,//IE-2 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x00000000, + 0x00000000, + 0x03020103,//IE-3 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x78787878, + 0x78787878, + 0x03020104,//IE-4 + 0x0706050f, + 0x30201005,//IE-5 + 0x70605040, + 0x03020106,//IE-6 + 0x07060504, + 0x30201007,//IE-7 + 0x70605040, + 0x02000088,//IE-8 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03002089,//IE-9 + 0x07060504, + 0x0302008A,//IE-10 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x0302010B,//IE-11 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020100, + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020100, + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020100, + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020100, + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x13121110, + 0x17161514, + 0x1b1a1918, + 0x1f1e1d1c, + 0x03020100, + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x0002004c, //IE-12 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002008D, //IE-13 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x030200ae, //IE-14 + 0x00000000, + 0x71c50701, + 0x1c71c71c, + 0x010e0105, + 0x05040302, + 0x09080706, + 0x0d0c0b0a, + 0x0000000e, + 0x00000000, + 0x0002008F, //IE-15 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x00002071, //IE-17 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03020112, //IE-18 + 0x07060504, + 0x0b0a0908, + 0x0f0e0d0c, + 0x03002013, //IE-19 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03012074, //IE-20 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03012075, //IE-21 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03010076, //IE-22 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03020118, //IE-24 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x03020119, //IE-25 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x0302011a, //IE-26 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x0302011b, //IE-27 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x0302011c, //IE-28 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x87654321, + 0x87654321, + 0x0302011d, //IE-29 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x87654321, + 0x87654321, + 0x0302011e, //IE-30 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x87654321, + 0x87654321, + 0x0302011f, //IE-31 + 0x87654321, + 0x654321a9, + 0x0000a987, + 0x0002004c, + 0x87654321, + 0x87654321, + 0x87654321, +#endif +}; + +void halbb_physts_detail_dump_ie_11(struct bb_info *bb) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_11_info *psts_11 = &physts->bb_physts_rslt_11_i; + struct physts_ie_11_info *ie_11 = NULL; + struct physts_ie_11_pkt_info *pkt_info; + char *mode = NULL; + char *state = NULL; + u64 type = 0; + u32 type1 = 0, type2 = 0; + u8 i = 0, j = 0; + + ie_11 = (struct physts_ie_11_info *)psts_11->ie_11_addr; + + BB_TRACE("[11][PLCP_Hist][T=%04d] LSIG=0x%05X, SIGA1=0x%07X, SIGA2=0x%04X\n", + (ie_11->time_stamp_m << 8) | ie_11->time_stamp_l, + (ie_11->l_sig_m << 11) | (ie_11->l_sig_lm << 3) | ie_11->l_sig_l, + (ie_11->sig_a1_m1 << 18) | (ie_11->sig_a1_m2 << 10) | (ie_11->sig_a1_m3 << 2) | ie_11->sig_a1_l, + (ie_11->sig_a2_m << 8) | ie_11->sig_a2_l); +#if 0 + BB_TRACE("*stamp=%d, r/tx_pkt_idx={%d, %d}\n", + (ie_11->time_stamp_m << 8) | (ie_11->time_stamp_l), + ie_11->rx_pkt_info_idx, + (ie_11->tx_pkt_info_idx_m << 1) | ie_11->tx_pkt_info_idx_l); +#endif + for (i = 0; i < IE11_PKT_INFO_LEN; i++) { + j = (ie_11->rx_pkt_info_idx + i) % IE11_PKT_INFO_LEN; + + pkt_info = &ie_11->pkt_info_rx_i[j]; + type = (pkt_info->info_type_4 << 31) | (pkt_info->info_type_3 << 23) | + (pkt_info->info_type_2 << 15) |(pkt_info->info_type_1 << 7) | + pkt_info->info_type_0; + + if (pkt_info->pkt_format == 1) { + type1 = (u32)(type & 0xFFFFFF); + type2 = (u32)(type >> 23); + mode = " HT "; + } else if (pkt_info->pkt_format == 2) { + type1 = (u32)(type & 0xFFFFFF); + type2 = (u32)(type >> 23); + mode = "VHT "; + } else if (pkt_info->pkt_format == 3) { + type1 = (u32)(type & 0x3FFFFFF); + type2 = (u32)(type >> 25); + mode = " HE "; + } else { + type1 = (u32)type; + type2 = 0; + mode = "Lgcy"; + } + + if (pkt_info->state == 1) { + state = "CRC-ER"; + } else if (pkt_info->state == 2) { + state = "Break "; + } else if (pkt_info->state == 3) { + state = "SS FAL"; + } else { + state = "CRC-OK"; + } + + BB_TRACE(" *[R][%d][%s][%s][T=%04d] l_rate=%d, SIG1/2={0x%08x, 0x%08x}\n", + i, mode, state, + (pkt_info->time_stamp_m << 5) | pkt_info->time_stamp_l, + pkt_info->l_rate, + type1, type2); + } + BB_TRACE(" *\n"); + + for (i = 0; i < IE11_PKT_INFO_LEN; i++) { + j = (ie_11->rx_pkt_info_idx + i) % IE11_PKT_INFO_LEN; + pkt_info = &ie_11->pkt_info_tx_i[i]; + type = (pkt_info->info_type_4 << 31) | (pkt_info->info_type_3 << 23) | + (pkt_info->info_type_2 << 15) |(pkt_info->info_type_1 << 7) | + pkt_info->info_type_0; + + if (pkt_info->pkt_format == 1) { + type1 = (u32)(type & 0xFFFFFF); + type2 = (u32)(type >> 23); + mode = " HT "; + } else if (pkt_info->pkt_format == 2) { + type1 = (u32)(type & 0xFFFFFF); + type2 = (u32)(type >> 23); + mode = "VHT "; + } else if (pkt_info->pkt_format == 3) { + type1 = (u32)(type & 0x3FFFFFF); + type2 = (u32)(type >> 25); + mode = " HE "; + } else { + type1 = (u32)type; + type2 = 0; + mode = "Lgcy"; + } + + if (pkt_info->state == 1) { + state = "CRC-ER"; + } else if (pkt_info->state == 2) { + state = "Break "; + } else if (pkt_info->state == 3) { + state = "SS FAL"; + } else { + state = "CRC-OK"; + } + + BB_TRACE(" *[T][%d][%s][%s][T=%04d] l_rate=%d, SIG1/2={0x%08x, 0x%08x}\n", + i, mode, state, + (pkt_info->time_stamp_m << 5) | pkt_info->time_stamp_l, + pkt_info->l_rate, + type1, type2); + } +} + +void halbb_physts_detail_dump_ie_4_7(struct bb_info *bb, enum bb_physts_ie_t ie) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_4_to_7_info *psts_r = NULL; + struct physts_ie_4_to_7_info *ie_4_7 = NULL; + char dbg_buf_1[HALBB_SNPRINT_SIZE_S], dbg_buf_2[HALBB_SNPRINT_SIZE_S], dbg_buf_3[HALBB_SNPRINT_SIZE_S]; + + if (ie < IE04_CMN_EXT_PATH_A) + return; + + BB_TRACE("[%02d][Extend path-%c]\n", ie, ('A' + (u8)(ie - IE04_CMN_EXT_PATH_A))); + + if (ie == IE04_CMN_EXT_PATH_A) + psts_r = &physts->bb_physts_rslt_4_i; + else if (ie == IE05_CMN_EXT_PATH_B) + psts_r = &physts->bb_physts_rslt_5_i; + else if (ie == IE06_CMN_EXT_PATH_C) + psts_r = &physts->bb_physts_rslt_6_i; + else if (ie == IE07_CMN_EXT_PATH_D) + psts_r = &physts->bb_physts_rslt_7_i; + else + return; + + ie_4_7 = (struct physts_ie_4_to_7_info *)psts_r->ie_04_07_addr; + + BB_TRACE(" *ie_hdr=%d\n", ie_4_7->ie_hdr); + + halbb_print_sign_frac_digit(bb, (s8)ie_4_7->sig_val_y, 8, 2, dbg_buf_1, HALBB_SNPRINT_SIZE_S); + halbb_print_sign_frac_digit(bb, (s8)ie_4_7->td_ant_weight, 8, 6, dbg_buf_3, HALBB_SNPRINT_SIZE_S); + + BB_TRACE(" *ant=%d, sig_val=%s, rf_gain_idx=%d, snr_lgy=%d, evm_ss_y=%d.%02d, ant_weight=%s\n", + ie_4_7->ant_idx, dbg_buf_1, ie_4_7->rf_gain_idx, + ie_4_7->snr_lgy, ie_4_7->evm_ss_y >> 2, + halbb_show_fraction_num(ie_4_7->evm_ss_y & 0x3, 2), dbg_buf_3); + + halbb_print_sign_frac_digit(bb, (s8)ie_4_7->dc_est_re, 8, 7, dbg_buf_1, HALBB_SNPRINT_SIZE_S); + halbb_print_sign_frac_digit(bb, (s8)ie_4_7->dc_est_im, 8, 7, dbg_buf_2, HALBB_SNPRINT_SIZE_S); + + BB_TRACE(" *dc_est_re/im={%s, %s}, tia_gain=%d, tia_shrink=%d\n", + dbg_buf_1, dbg_buf_2, + ie_4_7->rf_tia_gain_idx, ie_4_7->tia_shrink_indicator); +} + +void halbb_physts_detail_dump(struct bb_info *bb, u32 bitmap, u32 bitmap_mask) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + struct physts_ie_1_info *ie_1 = NULL; + struct bb_physts_rslt_2_info *psts_2 = &physts->bb_physts_rslt_2_i; + struct bb_physts_rslt_8_info *psts_8 = &physts->bb_physts_rslt_8_i; + struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i; + struct bb_physts_rslt_12_info *psts_12 = &physts->bb_physts_rslt_12_i; + struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i; + struct bb_physts_rslt_14_info *psts_14 = &physts->bb_physts_rslt_14_i; + struct bb_physts_rslt_15_info *psts_15 = &physts->bb_physts_rslt_15_i; + struct bb_physts_rslt_17_info *psts_17 = &physts->bb_physts_rslt_17_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + char *tmp_char = NULL; + u8 i; + + if (!physts->is_valid) { + BB_TRACE("physts invalid\n"); + return; + } + + if (psts_h->ie_map_type > 16) + return; + + if (bitmap_mask != 0xffffffff) { + BB_TRACE("user_def_mask=0x%08x\n", bitmap_mask); + } + + BB_TRACE("[Hdr] rssi={%d}{%d,%d,%d,%d}\n", + TRANS_2_RSSI(psts_h->rssi_avg), + TRANS_2_RSSI(psts_h->rssi[0]), + TRANS_2_RSSI(psts_h->rssi[1]), + TRANS_2_RSSI(psts_h->rssi[2]), + TRANS_2_RSSI(psts_h->rssi[3])); + + if (bitmap == 0) { + BB_TRACE("Hdr only, empty IE\n"); + return; + } + + if (bitmap & BIT(IE00_CMN_CCK)) { + BB_TRACE("[00][CCK] path_en=0x%x, rpl=%d.%01d, cfo=%s%d.%02d kHz, evm=%d.%02d\n", + psts_0->rx_path_en_cck, + psts_0->rpl >> 2, + halbb_show_fraction_num(psts_0->rpl & 0x3, 2), + ((psts_0->cfo_avg_cck & BIT15)!= 0) ? "-": " ", + ABS_16(psts_0->cfo_avg_cck) >> 2, + halbb_show_fraction_num((u16)ABS_16(psts_0->cfo_avg_cck) & 0x3, 2), + psts_0->evm_avg_cck >> 2, + halbb_show_fraction_num(psts_0->evm_avg_cck & 0x3, 2)); + BB_TRACE("[00][CCK] idle_noise=%d.%01d, pop idx=%d\n", + psts_0->avg_idle_noise_pwr_cck >> 1, + halbb_show_fraction_num(psts_0->avg_idle_noise_pwr_cck & 0x1, 1), + psts_0->pop_idx_cck); + } + + if (bitmap & BIT(IE01_CMN_OFDM)) { + ie_1 = (struct physts_ie_1_info *)physts->bb_physts_rslt_1_i.ie_01_addr; + + BB_TRACE("[01][OFDM] path_en=0x%x, rpl=%d.%01d, cfo_fd=%s%d.%02d kHz, cfo_pab=%s%d.%02d kHz, Max&Min evm={%d.%02d,%d.%02d}, avg SNR=%d , CN=%d.%01d\n", + psts_1->rx_path_en, + psts_1->rpl_fd >> 1, + halbb_show_fraction_num(psts_1->rpl_fd & 0x1, 1), + ((psts_1->cfo_avg & BIT15) != 0) ? "-": " ", + ABS_16(psts_1->cfo_avg) >> 2, + halbb_show_fraction_num((u16)ABS_16(psts_1->cfo_avg) & 0x3, 2), + ((psts_1->cfo_pab_avg & BIT15) != 0) ? "-": " ", + ABS_16(psts_1->cfo_pab_avg) >> 2, + halbb_show_fraction_num((u16)ABS_16(psts_1->cfo_pab_avg) & 0x3, 2), + psts_1->evm_max >> 2, + halbb_show_fraction_num(psts_1->evm_max & 0x3, 2), + psts_1->evm_min >> 2, + halbb_show_fraction_num(psts_1->evm_min & 0x3, 2), + psts_1->snr_avg, + psts_1->cn_avg >> 1, + halbb_show_fraction_num(psts_1->cn_avg & 0x1, 1)); + BB_TRACE("[01][OFDM] idle_noise=%d, pop idx=%d, ch=%d, bw=%d, rxsc=%d, su=%d, ldpc=%d, stbc=%d, gnt_bt=%d, awgn=%d, bf=%d\n", + psts_1->avg_idle_noise_pwr >> 1, psts_1->pop_idx, + psts_1->ch_idx, psts_1->bw_idx, psts_1->rxsc, + psts_1->is_su, psts_1->is_ldpc, psts_1->is_stbc, + psts_1->grant_bt, psts_1->is_awgn, psts_1->is_bf); + BB_TRACE("[01][OFDM] pwr_to_cca=%d ns, cca_to_agc=%d ns, cca_to_sbd=%dns", + (BYTE_2_WORD((u32)ie_1->pwr_to_cca_m, (u32)ie_1->pwr_to_cca_l) * 25), + ie_1->cca_to_agc * 25, ie_1->cca_to_sbd * 25); + } + + if (bitmap & BIT(IE02_CMN_EXT_AX)) { + BB_TRACE("[02][HE] max_nsts=%d, ltf_type=%d, gi=%d, c_cfo_i/q={%s%d.%07d, %s%d.%07d}, f_cfo_i/q={%s%d.%07d, %s%d.%07d}\n", + psts_2->max_nsts, psts_2->ltf_type, psts_2->gi, + ((psts_2->c_cfo_i & BIT31)!= 0) ? "-": " ", + ((u32)ABS_32(psts_2->c_cfo_i) >> 7), + halbb_show_fraction_num((u32)ABS_32(psts_2->c_cfo_i) & 0x7f, 7), + ((psts_2->c_cfo_q & BIT31)!= 0) ? "-": " ", + ((u32)ABS_32(psts_2->c_cfo_q) >> 7), + halbb_show_fraction_num((u32)ABS_32(psts_2->c_cfo_q) & 0x7f, 7), + ((psts_2->f_cfo_i & BIT31)!= 0) ? "-": " ", + ((u32)ABS_32(psts_2->f_cfo_i) >> 7), + halbb_show_fraction_num((u32)ABS_32(psts_2->f_cfo_i) & 0x7f, 7), + ((psts_2->f_cfo_q & BIT31)!= 0) ? "-": " ", + ((u32)ABS_32(psts_2->f_cfo_q) >> 7), + halbb_show_fraction_num((u32)ABS_32(psts_2->f_cfo_q) & 0x7f, 7)); + + BB_TRACE("[02][HE] rx_info_1=%d, rx_state_feq=%d, est_cmped_phase=0.%08d, pkt_ext=%d, n_ltf=%d, n_sym=%d\n", + psts_2->rx_info_1, psts_2->rx_state_feq, + halbb_show_fraction_num(psts_2->est_cmped_phase & 0xff, 8), + psts_2->pkt_extension, psts_2->n_ltf, psts_2->n_sym); + } + + if (bitmap & BIT(IE03_CMN_EXT_SEG_1)) { + /* suspended due to low priority */ + + } + + if (bitmap & BIT(IE04_CMN_EXT_PATH_A)) + halbb_physts_detail_dump_ie_4_7(bb, IE04_CMN_EXT_PATH_A); + + if (bitmap & BIT(IE05_CMN_EXT_PATH_B)) + halbb_physts_detail_dump_ie_4_7(bb, IE05_CMN_EXT_PATH_B); + + if (bitmap & BIT(IE06_CMN_EXT_PATH_C)) + halbb_physts_detail_dump_ie_4_7(bb, IE06_CMN_EXT_PATH_C); + + if (bitmap & BIT(IE07_CMN_EXT_PATH_D)) + halbb_physts_detail_dump_ie_4_7(bb, IE07_CMN_EXT_PATH_D); + + if (bitmap & BIT(IE08_FTR_CH)) { + BB_TRACE("[08][ch_info] rxsc=%d, n_rx=%d, sts=%d, EVM{1,2}={%d.%02d, %d.%02d}, avg_noise_pw=%d.%01d\n", + psts_8->rxsc, psts_8->n_rx, psts_8->n_sts, + psts_8->evm_1_sts >> 2, + halbb_show_fraction_num(psts_8->evm_1_sts & 0x3, 2), + psts_8->evm_2_sts >> 2, + halbb_show_fraction_num(psts_8->evm_2_sts & 0x3, 2), + (psts_8->avg_idle_noise_pwr >> 1), + halbb_show_fraction_num(psts_8->avg_idle_noise_pwr & 0x1, 1)); + } + + if (bitmap & BIT(IE09_FTR_PLCP_0)) { + if (cmn_rpt->bb_rate_i.mode == BB_HE_MODE) + tmp_char = "HE"; + else if (cmn_rpt->bb_rate_i.mode == BB_VHT_MODE) + tmp_char = "VHT"; + else if (cmn_rpt->bb_rate_i.mode == BB_HT_MODE) + tmp_char = "HT"; + else + tmp_char = "Lgcy"; + + BB_TRACE("[09][PLCP] mode=%s LSIG=0x%06x, SIGA1=0x%08x, SIGA2=0x%08x\n", + tmp_char, psts_9->l_sig, psts_9->sig_a1, psts_9->sig_a2); + } + + if (bitmap & BIT(IE11_FTR_PLCP_HISTOGRAM)) + halbb_physts_detail_dump_ie_11(bb); + + if (bitmap & BIT(IE12_MU_EIGEN_INFO)) { + for (i = 0; i < psts_12->n_user; i++) { + if (i >= MU_USER_MAX) + break; + + BB_TRACE("[12][MU_eigen][U:%d] sig_val_ss[3:0]={%d,%d,%d,%d}, cn bad tone=%d, sig bad tone=%d\n", + i, + psts_12->bb_physts_uer_info[i].sig_val_ss3_seg_cr_user_i, + psts_12->bb_physts_uer_info[i].sig_val_ss2_seg_cr_user_i, + psts_12->bb_physts_uer_info[i].sig_val_ss1_seg_cr_user_i, + psts_12->bb_physts_uer_info[i].sig_val_ss0_seg_cr_user_i, + psts_12->bb_physts_uer_info[i].cn_bad_tone_cnt_seg_cr_user_i, + psts_12->bb_physts_uer_info[i].sig_bad_tone_cnt_seg_cr_user_i); + } + } + + if (bitmap & BIT(IE13_DL_MU_DEF)) { + for (i = 0; i < psts_13->n_user; i++) { + if (i >= MU_USER_MAX) + break; + + BB_TRACE("[13][HEMU][U:%d] avg_cn=%d.%01d, fec_type=%d, awgn=%d, bf=%d, dcm=%d, mu=%d\n", + i, + (psts_13->bb_physts_uer_info[i].avg_cn_seg_cr >> 1), + halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].avg_cn_seg_cr & 0x1, 1), + psts_13->bb_physts_uer_info[i].fec_type, + psts_13->bb_physts_uer_info[i].is_awgn, + psts_13->bb_physts_uer_info[i].is_bf, + psts_13->bb_physts_uer_info[i].is_dcm, + psts_13->bb_physts_uer_info[i].is_mu_mimo); + + BB_TRACE("[13][HEMU][U:%d] mcs=%d, sts=%d, sts_ru_total=%d, gi_ltf=%d, pilot_exist=%d, mu=%d\n", + i, + psts_13->bb_physts_uer_info[i].mcs, + psts_13->bb_physts_uer_info[i].n_sts, + psts_13->bb_physts_uer_info[i].n_sts_ru_total, + psts_13->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type, + psts_13->bb_physts_uer_info[i].pilot_exist, + psts_13->bb_physts_uer_info[i].is_mu_mimo); + + BB_TRACE("[13][HEMU][U:%d] ru_aloc=%d, evm_segN_max/min={%d.%02d, %d.%02d}, snr=%s%d.%01d, start_sts=%d\n", + i, + psts_13->bb_physts_uer_info[i].ru_alloc, + psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr >> 2, + halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr & 0x3, 2), + psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr >> 2, + halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr & 0x3, 2), + ((psts_13->bb_physts_uer_info[i].snr & BIT7)!= 0) ? "-": " ", + ABS_8(psts_13->bb_physts_uer_info[i].snr ) >> 1, + halbb_show_fraction_num((u8)ABS_8(psts_13->bb_physts_uer_info[i].snr ) & 0x1, 1), + psts_13->bb_physts_uer_info[i].start_sts); + } + + BB_TRACE("[13][HEMU] n_not_sup_sta=%d\n", psts_13->n_not_sup_sta); + } + + if (bitmap & BIT(IE14_TB_UL_CQI)) { + BB_TRACE("[14][TB_CQI] ndp_en=%d, n_user=%d\n", + psts_14->rxinfo_ndp_en, psts_14->n_user); + + for (i = 0; i < psts_14->n_user; i++) { + if (i >= TB_USER_MAX) + break; + BB_TRACE("[14][TB_CQI][U:%d] cqi_bitmap_ul_tb=%d\n", + i, + psts_14->bb_physts_uer_info[i].cqi_bitmap_ul_tb); + } + } + + if (bitmap & BIT(IE15_TB_UL_DEF)) { + BB_TRACE("[15][TB_AC_MU] n_user=%d\n", psts_15->n_user); + for (i = 0; i < psts_15->n_user; i++) { + if (i >= TB_USER_MAX) + break; + + BB_TRACE("[15][TB_AC_MU][U:%d] avg_cn=%d.%01d, fec_type=%d, awgn=%d, bf=%d, dcm=%d, mu=%d\n", + i, + (psts_15->bb_physts_uer_info[i].avg_cn_seg_cr >> 1), + halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].avg_cn_seg_cr & 0x1, 1), + psts_15->bb_physts_uer_info[i].fec_type, + psts_15->bb_physts_uer_info[i].is_awgn, + psts_15->bb_physts_uer_info[i].is_bf, + psts_15->bb_physts_uer_info[i].is_dcm, + psts_15->bb_physts_uer_info[i].is_mu_mimo); + + BB_TRACE("[15][TB_AC_MU][U:%d] mcs=%d, sts=%d, sts_ru_total=%d, gi_ltf=%d, pilot_exist=%d, mu=%d\n", + i, + psts_15->bb_physts_uer_info[i].mcs, + psts_15->bb_physts_uer_info[i].n_sts, + psts_15->bb_physts_uer_info[i].n_sts_ru_total, + psts_15->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type, + psts_15->bb_physts_uer_info[i].pilot_exist, + psts_15->bb_physts_uer_info[i].is_mu_mimo); + + BB_TRACE("[15][TB_AC_MU][U:%d] ru_aloc=%d, evm_segN_max/min={%d.%02d, %d.%02d}, snr=%s%d.%02d, start_sts=%d\n", + i, + psts_15->bb_physts_uer_info[i].ru_alloc, + psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr >> 2, + halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr & 0x3, 2), + (psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr >> 2), + halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr & 0x3, 2), + ((psts_15->bb_physts_uer_info[i].snr & BIT7)!= 0) ? "-": " ", + ((u8)ABS_8(psts_15->bb_physts_uer_info[i].snr ) >> 1), + halbb_show_fraction_num((u8)ABS_8(psts_15->bb_physts_uer_info[i].snr ) & 0x1, 1), + (psts_15->bb_physts_uer_info[i].start_sts )); + + BB_TRACE("[15][TB_AC_MU][U:%d] uid=%d, avg_cfo_seg0=%s%d.%02d, rssi_m_ul_tb=%d.%02d\n", + i, psts_15->bb_physts_uer_info[i].uid, + ((psts_15->bb_physts_uer_info[i].avg_cfo_seg0 & BIT15)!= 0) ? "-": " ", + ((u16)ABS_16(psts_15->bb_physts_uer_info[i].avg_cfo_seg0) >> 2), + halbb_show_fraction_num((u16)ABS_16(psts_15->bb_physts_uer_info[i].avg_cfo_seg0) & 0x3, 2), + (psts_15->bb_physts_uer_info[i].rssi_m_ul_tb >> 2), + halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rssi_m_ul_tb & 0x3, 2)); + + } + } + if (bitmap & BIT(IE17_TB_UL_CTRL)) { + BB_TRACE("[17][TB_UL_CTRL] n_user=%d\n", psts_17->n_user); + + BB_TRACE("[17][TB_UL_CTRL][CMN] stbc_en=%d, ldpc_extra=%d, doppler_en=%d, midamle_mode=%d, gi_type=%d, ltf_type=%d\n", + psts_17->bb_physts_cmn_info.stbc_en , + psts_17->bb_physts_cmn_info.ldpc_extra, + psts_17->bb_physts_cmn_info.doppler_en, + psts_17->bb_physts_cmn_info.midamle_mode, + psts_17->bb_physts_cmn_info.gi_type, + psts_17->bb_physts_cmn_info.ltf_type); + BB_TRACE("[17][TB_UL_CTRL][CMN] n_ltf=%d, n_sym=%d, pe_idx=%d, pre_fec_factor=%d, n_usr=%d, mumimo_ltf_mode_en=%d\n", + psts_17->bb_physts_cmn_info.n_ltf, + psts_17->bb_physts_cmn_info.n_sym, + psts_17->bb_physts_cmn_info.pe_idx, + psts_17->bb_physts_cmn_info.pre_fec_factor, + psts_17->bb_physts_cmn_info.n_usr, + psts_17->bb_physts_cmn_info.mumimo_ltf_mode_en); + BB_TRACE("[17][TB_UL_CTRL][CMN] ndp=%d, pri_exp_rssi_dbm=%d, dbw_idx=%d, rxtime=%d\n", + psts_17->bb_physts_cmn_info.ndp, + psts_17->bb_physts_cmn_info.pri_exp_rssi_dbm, + psts_17->bb_physts_cmn_info.dbw_idx, + psts_17->bb_physts_cmn_info.rxtime); + for (i = 0; i < psts_15->n_user; i++) { + if (i >= TB_USER_MAX) + break; + + BB_TRACE("[17][TB_UL_CTRL][U:%d] u_id=%d, ru_alloc=%d, n_sts_ru_tot=%d, strt_sts=%d, n_sts=%d, fec_type=%d, mcs=%d, dcm_en=%d\n", + i, + psts_17->bb_physts_uer_info[i].u_id, + psts_17->bb_physts_uer_info[i].ru_alloc, + psts_17->bb_physts_uer_info[i].n_sts_ru_tot, + psts_17->bb_physts_uer_info[i].strt_sts, + psts_17->bb_physts_uer_info[i].n_sts, + psts_17->bb_physts_uer_info[i].fec_type, + psts_17->bb_physts_uer_info[i].mcs, + psts_17->bb_physts_uer_info[i].dcm_en); + + } + } +} + +void halbb_physts_ie_bitmap_set(struct bb_info *bb, u32 ie_page, u32 bitmap) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_cr_info *cr = &bb->bb_physts_i.bb_physts_cr_i; + + if (ie_page >= PHYSTS_BITMAP_NUM) + return; + + if (ie_page == 9) /* Bitmap 9 is rsvd */ + return; + + physts->bitmap_type[ie_page] = bitmap; + BB_DBG(bb, DBG_PHY_CONFIG, "Bitmap[%d] = 0x%x\n", + ie_page, physts->bitmap_type[ie_page]); + + if (ie_page >= 10) + ie_page--; + + if (bb->ic_type == BB_RTL8852A) + bitmap &= 0x337cff3f; + + //halbb_set_reg(bb, cr->plcp_hist, cr->plcp_hist_m, (bitmap & BIT(11)) ? 1 : 0); + halbb_set_reg(bb, cr->bitmap_search_fail + (ie_page << 2), MASKDWORD, bitmap); +} + +u32 halbb_physts_ie_bitmap_get(struct bb_info *bb, u32 ie_page) +{ + struct bb_physts_cr_info *cr = &bb->bb_physts_i.bb_physts_cr_i; + + if (ie_page >= PHYSTS_BITMAP_NUM) + return 0; + + if (ie_page == 9) /* Bitmap 9 is rsvd */ + return 0; + + else if (ie_page >= 10) + ie_page--; + + return halbb_get_reg(bb, cr->bitmap_search_fail + (ie_page << 2), MASKDWORD); +} + +void halbb_physts_ie_bitmap_en(struct bb_info *bb, enum bb_physts_bitmap_t type, + enum bb_physts_ie_t ie, bool en) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + u32 bitmap_ori = physts->bitmap_type[type]; + u32 bitmap = bitmap_ori & ~((u32)BIT(ie)); + +#if 0 + BB_DBG(bb, DBG_IC_API, "Bitmap_ori[%d] = 0x%x\n", + type, bitmap_ori); + + BB_DBG(bb, DBG_IC_API, "Bitmap_en[%d][Bit:%d]=%d\n", + type, ie, en); +#endif + if (en) { + if (bitmap_ori & (u32)BIT(ie)) + return; + + bitmap |= (u32)BIT(ie); + } else { + if (!(bitmap_ori & (u32)BIT(ie))) + return; + } + + halbb_physts_ie_bitmap_set(bb, type, bitmap); +} + +void halbb_physts_brk_fail_rpt_en(struct bb_info *bb, bool enable, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_physts_brk_fail_pkt_rpt_8852a_2(bb, enable, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_physts_td_time_rpt_en(struct bb_info *bb, bool en, + enum phl_phy_idx phy_idx) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i; + + halbb_set_reg_cmn(bb, cr->period_cnt_en, BIT0, en, phy_idx); /*enable pwr_2_cca time report*/ +} + +void halbb_mod_rssi_by_path_en(struct bb_info *bb, u8 rx_path_en) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + u8 num_path_en = 0; + u8 valid_rssi_max = 0; + u8 i = 0; + + for (i = 0; i < bb->num_rf_path; i++) { + if (!(rx_path_en & BIT(i))) { + psts_h->rssi[i] = 0; + continue; + } + + num_path_en++; + + if (psts_h->rssi[i] > valid_rssi_max) + valid_rssi_max = psts_h->rssi[i]; + } + + if (num_path_en < bb->num_rf_path) + psts_h->rssi_avg = valid_rssi_max; +} + +u8 halbb_physts_ie_hdr(struct bb_info *bb, + u8 *addr, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + struct physts_hdr_info *physts_hdr = NULL; + + /*---[Physts header parsing]------------------------------------------*/ + physts_hdr = (struct physts_hdr_info *)addr; + + #if 0 + if (desc->is_to_self) { + BB_DBG(bb, DBG_PHY_STS, "ie_map=%02d, null_tb_ppdu=%d, valid=%d, length=%d, rssi= {%d}{%d, %d, %d, %d}\n\n", + physts_hdr->ie_bitmap_select, + physts_hdr->null_tb_ppdu, + physts_hdr->is_valid, + physts_hdr->physts_total_length, + TRANS_2_RSSI(physts_hdr->rssi_avg_td), + TRANS_2_RSSI(physts_hdr->rssi_td[0]), + TRANS_2_RSSI(physts_hdr->rssi_td[1]), + TRANS_2_RSSI(physts_hdr->rssi_td[2]), + TRANS_2_RSSI(physts_hdr->rssi_td[3])); + } + #endif + + psts_h->rssi_avg = physts_hdr->rssi_avg_td; + psts_h->rssi[0] = physts_hdr->rssi_td[0]; + psts_h->rssi[1] = physts_hdr->rssi_td[1]; + psts_h->rssi[2] = physts_hdr->rssi_td[2]; + psts_h->rssi[3] = physts_hdr->rssi_td[3]; + psts_h->ie_map_type = (enum bb_physts_bitmap_t)physts_hdr->ie_bitmap_select; + + + return physts_hdr->physts_total_length; +} + +bool halbb_physts_ie_00(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i; + struct physts_ie_0_info *physts_ie_0 = NULL; + u32 cfo_tmp; + + physts_ie_0 = (struct physts_ie_0_info *)addr; + psts_0->ie_00_addr = addr; + + psts_0->rx_path_en_cck = physts_ie_0->rx_path_en_bitmap; + cfo_tmp = (physts_ie_0->avg_cfo_m << 8) | physts_ie_0->avg_cfo_l; + psts_0->cfo_avg_cck = (s16) halbb_cnvrt_2_sign(cfo_tmp, 12); + psts_0->evm_avg_cck = physts_ie_0->rxevm_pld; + psts_0->avg_idle_noise_pwr_cck = physts_ie_0->avg_idle_noise_pwr; + psts_0->rpl = (physts_ie_0->rpl_m << 1) | physts_ie_0->rpl_l; + psts_0->pop_idx_cck = physts_ie_0->pop_idx; + + halbb_mod_rssi_by_path_en(bb, psts_0->rx_path_en_cck); + + return true; +} + +bool halbb_physts_ie_01(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + struct physts_ie_1_info *ie_1 = NULL; + u32 cfo_tmp; + + ie_1 = (struct physts_ie_1_info *)addr; + psts_1->ie_01_addr = addr; + + /*0~6: 5, 10, 20, 40, 80, 160, 80_80*/ + + if (ie_1->bw_idx == 0) + psts_1->bw_idx = CHANNEL_WIDTH_5; + else if (ie_1->bw_idx == 1) + psts_1->bw_idx = CHANNEL_WIDTH_10; + else if (ie_1->bw_idx == 2) + psts_1->bw_idx = CHANNEL_WIDTH_20; + else if (ie_1->bw_idx == 3) + psts_1->bw_idx = CHANNEL_WIDTH_40; + else if (ie_1->bw_idx == 4) + psts_1->bw_idx = CHANNEL_WIDTH_80; + else if (ie_1->bw_idx == 5) + psts_1->bw_idx = CHANNEL_WIDTH_160; + else if (ie_1->bw_idx == 6) + psts_1->bw_idx = CHANNEL_WIDTH_80_80; + else + psts_1->bw_idx = CHANNEL_WIDTH_20; + + psts_1->rx_path_en = ie_1->rx_path_en_bitmap; +#if 0 + cfo_tmp = (ie_1->avg_cfo_premb_seg0_m << 4) | ie_1->avg_cfo_premb_seg0_l; + psts_1->cfo_pab_avg = (s16) halbb_cnvrt_2_sign(cfo_tmp, 12); +#else + cfo_tmp = (((u32)ie_1->avg_cfo_seg0_m) << 8) | (u32)ie_1->avg_cfo_seg0_l; + psts_1->cfo_avg = (s16)halbb_cnvrt_2_sign(cfo_tmp, 12); + cfo_tmp = (((u32)ie_1->avg_cfo_premb_seg0_m) << 4) | (u32)ie_1->avg_cfo_premb_seg0_l; + psts_1->cfo_pab_avg = (s16)halbb_cnvrt_2_sign(cfo_tmp, 12); +#endif + psts_1->evm_max = ie_1->evm_max; + psts_1->evm_min = ie_1->evm_min; + psts_1->snr_avg = ie_1->avg_snr; + psts_1->cn_avg = ie_1->avg_cn_seg0; + psts_1->avg_idle_noise_pwr = ie_1->avg_idle_noise_pwr; + psts_1->pop_idx = ie_1->pop_idx; + psts_1->ch_idx = ie_1->ch_idx_seg0; + psts_1->rpl_fd = ie_1->rssi_avg_fd; + //psts_1->bw_idx = ie_1->bw_idx; + psts_1->rxsc = ie_1->rxsc; + psts_1->is_su = ie_1->is_su; + psts_1->is_ldpc = ie_1->is_ldpc; + psts_1->is_ndp = ie_1->is_ndp; + psts_1->is_stbc = ie_1->is_stbc; + psts_1->grant_bt = ie_1->grant_bt; + psts_1->is_awgn = ie_1->is_awgn; + psts_1->is_bf = ie_1->is_bf; + + //BB_DBG(bb, DBG_CMN, "[1]cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n", + // psts_1->cfo_avg, psts_1->evm_max, psts_1->evm_min, psts_1->cn_avg); + halbb_mod_rssi_by_path_en(bb, psts_1->rx_path_en); + + return true; +} + +bool halbb_physts_ie_02(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_2_info *psts_2 = &physts->bb_physts_rslt_2_i; + struct physts_ie_2_info *ie_2 = NULL; + u32 cfo_tmp; + u32 lt_cfo_buffer_th = (1<<24); + u32 lt_cfo_abs_tmp_i,lt_cfo_abs_tmp_q; + + ie_2 = (struct physts_ie_2_info *)addr; + psts_2->ie_02_addr = addr; + + psts_2->max_nsts = ie_2->max_nsts; + psts_2->ltf_type = ie_2->ltf_type; + psts_2->gi = ie_2->gi; + cfo_tmp = (ie_2->c_cfo_i_m1<<10) | (ie_2->c_cfo_i_m2<<2) | ie_2->c_cfo_i_l; + psts_2->c_cfo_i = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18); + psts_2->rx_info_1 = ie_2->rx_info_1; + psts_2->rx_state_feq = ie_2->rx_state_feq; + cfo_tmp = (ie_2->c_cfo_q_m1<<10) | (ie_2->c_cfo_q_m2<<2) | ie_2->c_cfo_q_l; + psts_2->c_cfo_q = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18); + psts_2->est_cmped_phase = ie_2->est_cmped_phase; + psts_2->pkt_extension = ie_2->pkt_extension; + cfo_tmp = (ie_2->f_cfo_i_m1<<10) | (ie_2->f_cfo_i_m2<<2) | ie_2->f_cfo_i_l; + psts_2->f_cfo_i = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18); + psts_2->n_ltf = ie_2->n_ltf; + psts_2->n_sym = (ie_2->n_sym_m<<5) | ie_2->n_sym_l; + cfo_tmp = (ie_2->f_cfo_q_m1<<10) | (ie_2->f_cfo_q_m2<<2) | ie_2->f_cfo_q_l; + psts_2->f_cfo_q = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18); + psts_2->midamble = ie_2->midamble; + psts_2->is_mu_mimo = ie_2->is_mu_mimo; + psts_2->is_dl_ofdma = ie_2->is_dl_ofdma; + psts_2->is_dcm = ie_2->is_dcm; + psts_2->is_doppler = ie_2->is_doppler; + + physts->l_ltf_cfo_i += psts_2->f_cfo_i; + physts->l_ltf_cfo_q += psts_2->f_cfo_q; + lt_cfo_abs_tmp_i = ABS_32(physts->l_ltf_cfo_i); + lt_cfo_abs_tmp_q = ABS_32(physts->l_ltf_cfo_q); + if ( lt_cfo_abs_tmp_i > lt_cfo_buffer_th || lt_cfo_abs_tmp_q > lt_cfo_buffer_th ){ + physts->l_ltf_cfo_i = physts->l_ltf_cfo_i >> 16; + physts->l_ltf_cfo_q = physts->l_ltf_cfo_q >> 16; + } + + return true; +} +bool halbb_physts_ie_03(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_3_info *psts_3 = &physts->bb_physts_rslt_3_i; + struct physts_ie_3_info *ie_3 = NULL; + + ie_3 = (struct physts_ie_3_info *)addr; + psts_3->ie_03_addr = addr; + + psts_3->avg_cn_seg1 = ie_3->avg_cn_seg1; + psts_3->sigval_below_th_tone_cnt_seg1 = ie_3->sigval_below_th_tone_cnt_seg1; + psts_3->cn_excess_th_tone_cnt_seg1 = ie_3->cn_excess_th_tone_cnt_seg1; + psts_3->avg_cfo_seg1 = (ie_3->avg_cfo_seg1_m<<8) | ie_3->avg_cfo_seg1_l; + psts_3->avg_cfo_premb_seg1 = (ie_3->avg_cfo_premb_seg1_m<<8) | ie_3->avg_cfo_premb_seg1_l; + psts_3->est_cmped_phase_seg1 = ie_3->est_cmped_phase_seg1; + psts_3->avg_snr_seg1 = ie_3->avg_snr_seg1; + psts_3->c_cfo_i_seg1 = (ie_3->c_cfo_i_seg1_m1<<10) | (ie_3->c_cfo_i_seg1_m2<<2) | ie_3->c_cfo_i_seg1_l; + psts_3->c_cfo_q_seg1 = (ie_3->c_cfo_q_seg1_m<<16) | (ie_3->c_cfo_q_seg1_l1<<8) | ie_3->c_cfo_q_seg1_l2; + psts_3->f_cfo_i_seg1 = (ie_3->f_cfo_i_seg1_m<<14) | (ie_3->f_cfo_i_seg1_lm<<6) | ie_3->f_cfo_i_seg1_l; + psts_3->f_cfo_q_seg1 = (ie_3->f_cfo_q_seg1_m<<12) | (ie_3->f_cfo_q_seg1_lm<<4) | ie_3->f_cfo_q_seg1_l; + psts_3->ch_idx_seg1 = ie_3->ch_idx_seg1; + psts_3->evm_max_seg1 = ie_3->evm_max_seg1; + psts_3->evm_min_seg1 = ie_3->evm_min_seg1; + + return true; +} + +bool halbb_physts_ie_04_07(struct bb_info *bb, + enum bb_physts_ie_t ie, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_4_to_7_info *psts_r = NULL; + struct physts_ie_4_to_7_info *ie_4_7 = NULL; + u8 ant_idx_tmp; + + if (ie == IE04_CMN_EXT_PATH_A) + psts_r = &physts->bb_physts_rslt_4_i; + else if (ie == IE05_CMN_EXT_PATH_B) + psts_r = &physts->bb_physts_rslt_5_i; + else if (ie == IE06_CMN_EXT_PATH_C) + psts_r = &physts->bb_physts_rslt_6_i; + else if (ie == IE07_CMN_EXT_PATH_D) + psts_r = &physts->bb_physts_rslt_7_i; + else + return false; + + ie_4_7 = (struct physts_ie_4_to_7_info *)addr; + psts_r->ie_04_07_addr = addr; + + ant_idx_tmp = (ie_4_7->ant_idx_msb << 3) | ie_4_7->ant_idx; + + psts_r->ant_idx = ant_idx_tmp; + psts_r->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_4_7->sig_val_y, 8); + psts_r->rf_gain_idx = ie_4_7->rf_gain_idx; + psts_r->snr_lgy = ie_4_7->snr_lgy; + psts_r->evm_ss_y = ie_4_7->evm_ss_y; + psts_r->td_ant_weight = ie_4_7->td_ant_weight; + psts_r->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_4_7->dc_est_re, 8); + psts_r->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_4_7->dc_est_im, 8); + psts_r->rf_tia_gain_idx = ie_4_7->rf_tia_gain_idx; + psts_r->tia_shrink_indicator = ie_4_7->tia_shrink_indicator; + + return true; +} + +#if 1 +bool halbb_physts_ie_05(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_4_to_7_info *psts_5 = &physts->bb_physts_rslt_5_i; + struct physts_ie_4_to_7_info *ie_5 = NULL; + u8 ant_idx_tmp; + + ie_5 = (struct physts_ie_4_to_7_info *)addr; + + ant_idx_tmp = (ie_5->ant_idx_msb << 3) | ie_5->ant_idx; + + psts_5->ant_idx = ant_idx_tmp; + psts_5->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_5->sig_val_y,8); + psts_5->rf_gain_idx = ie_5->rf_gain_idx; + psts_5->snr_lgy = ie_5->snr_lgy; + psts_5->evm_ss_y = ie_5->evm_ss_y; + psts_5->td_ant_weight = ie_5->td_ant_weight; + psts_5->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_5->dc_est_re,8); + psts_5->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_5->dc_est_im,8); + psts_5->rf_tia_gain_idx = ie_5->rf_tia_gain_idx; + psts_5->tia_shrink_indicator = ie_5->tia_shrink_indicator; + + return true; +} + +bool halbb_physts_ie_06(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_4_to_7_info *psts_6 = &physts->bb_physts_rslt_6_i; + struct physts_ie_4_to_7_info *ie_6 = NULL; + u8 ant_idx_tmp; + + ie_6 = (struct physts_ie_4_to_7_info *)addr; + + ant_idx_tmp = (ie_6->ant_idx_msb << 3) | ie_6->ant_idx; + + psts_6->ant_idx = ant_idx_tmp; + psts_6->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_6->sig_val_y,8); + psts_6->rf_gain_idx = ie_6->rf_gain_idx; + psts_6->snr_lgy = ie_6->snr_lgy; + psts_6->evm_ss_y = ie_6->evm_ss_y; + psts_6->td_ant_weight = ie_6->td_ant_weight; + psts_6->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_6->dc_est_re,8); + psts_6->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_6->dc_est_im,8); + psts_6->rf_tia_gain_idx = ie_6->rf_tia_gain_idx; + psts_6->tia_shrink_indicator = ie_6->tia_shrink_indicator; + + return true; +} + +bool halbb_physts_ie_07(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_4_to_7_info *psts_7 = &physts->bb_physts_rslt_7_i; + struct physts_ie_4_to_7_info *ie_7 = NULL; + u8 ant_idx_tmp; + + ie_7 = (struct physts_ie_4_to_7_info *)addr; + + ant_idx_tmp = (ie_7->ant_idx_msb << 3) | ie_7->ant_idx; + + psts_7->ant_idx = ant_idx_tmp; + psts_7->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_7->sig_val_y,8); + psts_7->rf_gain_idx = ie_7->rf_gain_idx; + psts_7->snr_lgy = ie_7->snr_lgy; + psts_7->evm_ss_y = ie_7->evm_ss_y; + psts_7->td_ant_weight = ie_7->td_ant_weight; + psts_7->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_7->dc_est_re,8); + psts_7->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_7->dc_est_im,8); + psts_7->rf_tia_gain_idx = ie_7->rf_tia_gain_idx; + psts_7->tia_shrink_indicator = ie_7->tia_shrink_indicator; + + return true; +} +#endif + +bool halbb_physts_ie_08(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_8_info *psts_8 = &physts->bb_physts_rslt_8_i; + struct physts_ie_8_ch_info *ie_8 = NULL; + #ifdef HALBB_CH_INFO_SUPPORT + struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i; + struct bb_ch_info_physts_info *ch_physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i; + #endif + u64 *phy_sts_tmp = NULL; + + ie_8 = (struct physts_ie_8_ch_info *)addr; + psts_8->ie_08_addr = addr; + addr += sizeof(struct physts_ie_8_ch_info); + + psts_8->rxsc = ie_8->rxsc; + psts_8->n_rx = ie_8->n_rx; + psts_8->n_sts = ie_8->n_sts; + psts_8->ch_info_len = (ie_8->ch_info_len_m << 2) | ie_8->ch_info_len_l; + psts_8->evm_1_sts= ie_8->evm_1_sts; + psts_8->evm_2_sts = ie_8->evm_2_sts; + psts_8->avg_idle_noise_pwr= ie_8->avg_idle_noise_pwr; + psts_8->is_ch_info_len_valid= ie_8->is_ch_info_len_valid; + + #ifdef HALBB_CH_INFO_SUPPORT + if (ch_physts->ch_info_state == CH_RPT_START_TO_WAIT) { + halbb_mem_cpy(bb, buf->octet, (s16*)addr, buf->ch_info_buf_len); + ch_physts->ch_info_state = CH_RPT_GETTED; + ch_physts->ch_info_len = psts_8->ch_info_len; + ch_physts->bitmap_type_rpt = physts->bb_physts_rslt_hdr_i.ie_map_type; + } + #endif + + if (bb->bb_physts_i.print_more_info) { + BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-8] ch-raw info. len=%d\n", psts_8->ch_info_len); + halbb_print_buff_64(bb, addr, psts_8->ch_info_len); + } + + return true; +} + +void halbb_physts_ie_09_lgcy(struct bb_info *bb, + u8 *addr, + u8 rate_mode, + struct physts_rxd *desc) +{ + struct physts_ie_9_lgcy_info *ie_9 = NULL; + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i; + + ie_9 = (struct physts_ie_9_lgcy_info *)addr; + psts_9->ie_09_addr = addr; + psts_9->l_sig = (ie_9->l_sig_m << 11) | (ie_9->l_sig_lm << 3) | (ie_9->l_sig_l); +} + +void halbb_physts_ie_09_vht(struct bb_info *bb, + u8 *addr, + u8 rate_mode, + struct physts_rxd *desc) +{ + struct physts_ie_9_vht_info *ie_9 = NULL; + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i; + + ie_9 = (struct physts_ie_9_vht_info *)addr; + psts_9->ie_09_addr = addr; + psts_9->l_sig = (ie_9->l_sig_m << 11) | (ie_9->l_sig_lm << 3) | (ie_9->l_sig_l); + psts_9->sig_a1 = (ie_9->sig_a1_m << 18)| (ie_9->sig_a1_lm1 << 10) | (ie_9->sig_a1_lm2 << 2) | (ie_9->sig_a1_l); + psts_9->sig_a2 = (ie_9->sig_a2_m << 2) | (ie_9->sig_a2_l); +} + +void halbb_physts_ie_09_he(struct bb_info *bb, + u8 *addr, + u8 rate_mode, + struct physts_rxd *desc) +{ + struct physts_ie_9_he_info *ie_9 = NULL; + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i; + + ie_9 = (struct physts_ie_9_he_info *)addr; + psts_9->ie_09_addr = addr; + psts_9->l_sig = (ie_9->l_sig_m<<11) | (ie_9->l_sig_lm<<3) | (ie_9->l_sig_l); + psts_9->sig_a1 = (ie_9->sig_a1_m1<<18) | (ie_9->sig_a1_m2<<10) | (ie_9->sig_a1_m3<<2) | (ie_9->sig_a1_l); + psts_9->sig_a2 = (ie_9->sig_a2_m << 8) | (ie_9->sig_a2_l); + +#ifdef BB_8852A_2_SUPPORT + if (bb->ic_type == BB_RTL8852A && + bb->hal_com->cv <= CBV) { + if (psts_9->sig_a1 & BIT7 && /*DCM == 1*/ + ((psts_9->sig_a1 & 0x3800000) >> 23) == 1 && /*NSTS == 2*/ + psts_9->sig_a2 & BIT9) { /*STBC == 1*/ + desc->data_rate &= ~0x70; + desc->data_rate |= 0x10; /*HW issue*/ + } + } +#endif +} + +bool halbb_physts_ie_09(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + u8 mode = physts->bb_rate_i.mode; + + /* To get rate mode for plcp ie parsing */ + + /* allocate different plcp type structure */ + if (mode == BB_LEGACY_MODE) { + halbb_physts_ie_09_lgcy(bb, addr, mode, desc); + } else if ((mode == BB_HT_MODE) || (mode == BB_VHT_MODE)) { + halbb_physts_ie_09_vht(bb, addr, mode, desc); + } else if (mode == BB_HE_MODE) { + halbb_physts_ie_09_he(bb, addr, mode, desc); + } + + return true; +} + +bool halbb_physts_ie_10(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct physts_ie_10_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_10_sigb_info physts_sigb; + u16 sigb_len; /* bytes */ + + physts_c = (struct physts_ie_10_cmn_info *)addr; + addr += sizeof(struct physts_ie_10_cmn_info); + + physts_sigb.sigb_raw_data_bits_addr = addr; + + /* SIG-B len(with zero padding)= IE length - remaining cotent len (64bits)*/ + sigb_len = ie_length - 8; + + if (bb->bb_physts_i.print_more_info) { + BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-10] SIG-B len(with zero-pad)=%d\n", sigb_len); + halbb_print_buff_64(bb, physts_sigb.sigb_raw_data_bits_addr, sigb_len); + } + + return true; +} + +bool halbb_physts_ie_11(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_11_info *psts_11 = &physts->bb_physts_rslt_11_i; + struct physts_ie_11_info *ie_11 = NULL; + + ie_11 = (struct physts_ie_11_info *)addr; + psts_11->ie_11_addr = addr; + + psts_11->l_sig = (ie_11->l_sig_m << 11) | (ie_11->l_sig_lm << 3) | (ie_11->l_sig_l); + psts_11->sig_a1 = (ie_11->sig_a1_m1 << 18) | (ie_11->sig_a1_m2 << 10) | (ie_11->sig_a1_m3 << 2) | (ie_11->sig_a1_l); + psts_11->sig_a2 = (ie_11->sig_a2_m<<8) | ie_11->sig_a2_l; + psts_11->time_stamp = (ie_11->time_stamp_m << 8) | (ie_11->time_stamp_l); + psts_11->rx_pkt_info_idx = ie_11->rx_pkt_info_idx; + psts_11->tx_pkt_info_idx = (ie_11->tx_pkt_info_idx_m << 1) | (ie_11->tx_pkt_info_idx_l); + + return true; +} + +bool halbb_physts_ie_12(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_12_info *psts_12 = &physts->bb_physts_rslt_12_i; + + struct physts_ie_12_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_12_user_info *physts_u[MU_USER_MAX] = {NULL}; /*per user*/ + u8 i; + + physts_c = (struct physts_ie_12_cmn_info *)addr; + psts_12->ie_12_addr = addr; + addr += sizeof(struct physts_ie_12_cmn_info); + + //BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-12]n_user=%d\n",physts_c->n_user); + psts_12->n_user = physts_c->n_user; + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= MU_USER_MAX) + break; + physts_u[i] = (struct physts_ie_12_user_info *)addr; + + /* + physts_u[i].sig_val_ss0_seg_cr_user_i = *addr; + physts_u[i].sig_val_ss1_seg_cr_user_i = *(++addr); + physts_u[i].sig_val_ss2_seg_cr_user_i = *(++addr); + physts_u[i].sig_val_ss3_seg_cr_user_i = *(++addr); + physts_u[i].sig_bad_tone_cnt_seg_cr_user_i = *(++addr); + physts_u[i].cn_bad_tone_cnt_seg_cr_user_i = *(++addr); + */ + + psts_12->bb_physts_uer_info[i].cn_bad_tone_cnt_seg_cr_user_i = + physts_u[i]->cn_bad_tone_cnt_seg_cr_user_i; + psts_12->bb_physts_uer_info[i].sig_bad_tone_cnt_seg_cr_user_i = + physts_u[i]->sig_bad_tone_cnt_seg_cr_user_i; + psts_12->bb_physts_uer_info[i].sig_val_ss0_seg_cr_user_i = + physts_u[i]->sig_val_ss0_seg_cr_user_i; + psts_12->bb_physts_uer_info[i].sig_val_ss1_seg_cr_user_i = + physts_u[i]->sig_val_ss1_seg_cr_user_i; + psts_12->bb_physts_uer_info[i].sig_val_ss2_seg_cr_user_i = + physts_u[i]->sig_val_ss2_seg_cr_user_i; + psts_12->bb_physts_uer_info[i].sig_val_ss3_seg_cr_user_i = + physts_u[i]->sig_val_ss3_seg_cr_user_i; + + addr += sizeof(struct physts_ie_12_user_info); + } + + return true; +} + +bool halbb_physts_ie_13(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i; + + struct physts_ie_13_cmn_info_p1 *physts_c = NULL; /*common*/ + struct physts_ie_13_cmn_info_p2 *physts_c2 = NULL; /*common*/ + struct physts_ie_13_user_info *physts_u[MU_USER_MAX] = {NULL}; /*per user*/ + u8 i; + u16 sta_id_tmp; + + physts_c = (struct physts_ie_13_cmn_info_p1 *)addr; + psts_13->ie_13_addr = addr; + addr += sizeof(struct physts_ie_13_cmn_info_p1); + + //BB_DBG(bb, DBG_PHY_STS, "n_user=%d\n", physts_c->n_user); + psts_13->n_user = physts_c->n_user; + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= MU_USER_MAX) + break; + + physts_u[i] = (struct physts_ie_13_user_info *)addr; + + + psts_13->bb_physts_uer_info[i].avg_cn_seg_cr = physts_u[i]->avg_cn_seg_cr; + psts_13->bb_physts_uer_info[i].fec_type = physts_u[i]->fec_type; + psts_13->bb_physts_uer_info[i].is_awgn = physts_u[i]->is_awgn; + psts_13->bb_physts_uer_info[i].is_bf= physts_u[i]->is_bf; + psts_13->bb_physts_uer_info[i].is_dcm = physts_u[i]->is_dcm; + psts_13->bb_physts_uer_info[i].is_mu_mimo = physts_u[i]->is_mu_mimo; + psts_13->bb_physts_uer_info[i].mcs = physts_u[i]->mcs; + psts_13->bb_physts_uer_info[i].n_sts = physts_u[i]->n_sts; + psts_13->bb_physts_uer_info[i].n_sts_ru_total = physts_u[i]->n_sts_ru_total; + psts_13->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type = physts_u[i]->pdp_he_ltf_and_gi_type; + psts_13->bb_physts_uer_info[i].pilot_exist = physts_u[i]->pilot_exist; + psts_13->bb_physts_uer_info[i].ru_alloc = physts_u[i]->ru_alloc; + psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr = physts_u[i]->rx_evm_max_seg_cr; + psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr = physts_u[i]->rx_evm_min_seg_cr; + psts_13->bb_physts_uer_info[i].snr = (s8)halbb_cnvrt_2_sign(physts_u[i]->snr,8); + psts_13->bb_physts_uer_info[i].start_sts = physts_u[i]->start_sts; + sta_id_tmp = (physts_u[i]->sta_id_m << 8) | physts_u[i]->sta_id_l; + psts_13->bb_physts_uer_info[i].sta_id = sta_id_tmp; + + addr += sizeof(struct physts_ie_13_user_info); + } + + physts_c2 = (struct physts_ie_13_cmn_info_p2 *)addr; + + psts_13->n_not_sup_sta = physts_c2->n_not_sup_sta; + + return true; +} + +bool halbb_physts_ie_14(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_14_info *psts_14 = &physts->bb_physts_rslt_14_i; + + struct physts_ie_14_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_14_user_info physts_u[TB_USER_MAX]; /*per user*/ + u8 cqi_user_len = 0; + u8 *cqi_user_addr; + u8 i; + + physts_c = (struct physts_ie_14_cmn_info *)addr; + psts_14->ie_14_addr = addr; + addr += sizeof(struct physts_ie_14_cmn_info); + + psts_14->n_user = physts_c->n_user; + psts_14->rxinfo_ndp_en= physts_c->rxinfo_ndp_en; + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + + physts_u[i].cqi_bitmap_ul_tb = *addr; + physts_u[i].cqi_raw_len_ul_tb = *(++addr); + physts_u[i].cqi_raw_ul_tb_addr = (++addr); + + psts_14->bb_physts_uer_info[i].cqi_bitmap_ul_tb = physts_u[i].cqi_bitmap_ul_tb; + psts_14->bb_physts_uer_info[i].cqi_raw_len_ul_tb = physts_u[i].cqi_raw_len_ul_tb; + psts_14->bb_physts_uer_info[i].cqi_raw_ul_tb_addr= physts_u[i].cqi_raw_ul_tb_addr; + + + addr += physts_u[i].cqi_raw_len_ul_tb; + } + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + cqi_user_len = physts_u[i].cqi_raw_len_ul_tb; + cqi_user_addr = physts_u[i].cqi_raw_ul_tb_addr; + if (bb->bb_physts_i.print_more_info) { + BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-14][User:%d] len=%d\n", i, cqi_user_len); + halbb_print_buff_64(bb, cqi_user_addr, cqi_user_len); + } + } + + return true; +} + +bool halbb_physts_ie_15(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_15_info *psts_15 = &physts->bb_physts_rslt_15_i; + + struct physts_ie_15_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_15_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/ + u8 i; + u16 rssi_tmp; + s16 cfo_tmp; + + physts_c = (struct physts_ie_15_cmn_info *)addr; + psts_15->ie_15_addr = addr; + addr += sizeof(struct physts_ie_15_cmn_info); + + psts_15->n_user = physts_c->n_user; + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + physts_u[i] = (struct physts_ie_15_user_info *)addr; + + cfo_tmp = (s16) halbb_cnvrt_2_sign(((physts_u[i]->avg_cfo_seg0_m << 8) | physts_u[i]->avg_cfo_seg0_l), 12); + rssi_tmp = (physts_u[i]->rssi_m_ul_tb_m << 8) | physts_u[i]->rssi_m_ul_tb_l; + + psts_15->bb_physts_uer_info[i].avg_cn_seg_cr = physts_u[i]->avg_cn_seg_cr; + psts_15->bb_physts_uer_info[i].fec_type = physts_u[i]->fec_type; + psts_15->bb_physts_uer_info[i].is_awgn = physts_u[i]->is_awgn; + psts_15->bb_physts_uer_info[i].is_bf= physts_u[i]->is_bf; + psts_15->bb_physts_uer_info[i].is_dcm = physts_u[i]->is_dcm; + psts_15->bb_physts_uer_info[i].is_mu_mimo = physts_u[i]->is_mu_mimo; + psts_15->bb_physts_uer_info[i].mcs = physts_u[i]->mcs; + psts_15->bb_physts_uer_info[i].n_sts = physts_u[i]->n_sts; + psts_15->bb_physts_uer_info[i].n_sts_ru_total = physts_u[i]->n_sts_ru_total; + psts_15->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type = physts_u[i]->pdp_he_ltf_and_gi_type; + psts_15->bb_physts_uer_info[i].pilot_exist = physts_u[i]->pilot_exist; + psts_15->bb_physts_uer_info[i].ru_alloc = physts_u[i]->ru_alloc; + psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr = physts_u[i]->rx_evm_max_seg_cr; + psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr = physts_u[i]->rx_evm_min_seg_cr; + psts_15->bb_physts_uer_info[i].snr = physts_u[i]->snr; + psts_15->bb_physts_uer_info[i].start_sts = physts_u[i]->start_sts; + + psts_15->bb_physts_uer_info[i].uid = physts_u[i]->uid; + psts_15->bb_physts_uer_info[i].avg_cfo_seg0 = cfo_tmp; + psts_15->bb_physts_uer_info[i].rssi_m_ul_tb = rssi_tmp; + + + addr += sizeof(struct physts_ie_15_user_info); + } + + return true; +} + +bool halbb_physts_ie_17(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct physts_ie_17_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_17_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_17_info *psts_17 = &physts->bb_physts_rslt_17_i; + u8 i; + u8 n_user; + + physts_c = (struct physts_ie_17_cmn_info *)addr; + psts_17->ie_17_addr = addr; + addr += sizeof(struct physts_ie_17_cmn_info); + + psts_17->bb_physts_cmn_info.stbc_en = physts_c->stbc_en; + psts_17->bb_physts_cmn_info.ldpc_extra = physts_c->ldpc_extra; + psts_17->bb_physts_cmn_info.doppler_en = physts_c->doppler_en; + psts_17->bb_physts_cmn_info.midamle_mode = physts_c->midamle_mode; + psts_17->bb_physts_cmn_info.gi_type = physts_c->gi_type; + psts_17->bb_physts_cmn_info.ltf_type = physts_c->ltf_type; + psts_17->bb_physts_cmn_info.n_ltf = physts_c->n_ltf; + psts_17->bb_physts_cmn_info.n_sym = (physts_c->n_sym_m<<5)|physts_c->n_sym_l; + psts_17->bb_physts_cmn_info.pe_idx = ((physts_c->pe_idx_m<<2)|physts_c->pe_idx_l); + psts_17->bb_physts_cmn_info.pre_fec_factor = physts_c->pre_fec_factor; + psts_17->bb_physts_cmn_info.n_usr = ((physts_c->n_user_m<<5)|physts_c->n_user_l); + psts_17->bb_physts_cmn_info.mumimo_ltf_mode_en = physts_c->mumimo_ltf_mode_en; + psts_17->bb_physts_cmn_info.ndp = physts_c->ndp; + psts_17->bb_physts_cmn_info.pri_exp_rssi_dbm = ((physts_c->pri_exp_rssi_dbm_m<<3)|physts_c->pri_exp_rssi_dbm_l); + psts_17->bb_physts_cmn_info.dbw_idx = physts_c->dbw_idx; + psts_17->bb_physts_cmn_info.rxtime = (physts_c->rxtime_m<<8)|physts_c->rxtime_l; + + + n_user = (physts_c->n_user_m<<4) | physts_c->n_user_l; + psts_17->n_user = n_user; + + //BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-17]n_user=%d\n", n_user); + + for (i = 0; i < n_user; i++) { + if (i >= TB_USER_MAX) + break; + physts_u[i] = (struct physts_ie_17_user_info *)addr; + + psts_17->bb_physts_uer_info[i].u_id= physts_u[i]->u_id; + psts_17->bb_physts_uer_info[i].ru_alloc= physts_u[i]->ru_alloc; + psts_17->bb_physts_uer_info[i].n_sts_ru_tot= physts_u[i]->n_sts_ru_tot; + psts_17->bb_physts_uer_info[i].strt_sts= physts_u[i]->strt_sts; + psts_17->bb_physts_uer_info[i].n_sts= physts_u[i]->n_sts; + psts_17->bb_physts_uer_info[i].fec_type= physts_u[i]->fec_type; + psts_17->bb_physts_uer_info[i].mcs= physts_u[i]->mcs; + psts_17->bb_physts_uer_info[i].dcm_en= (bool)physts_u[i]->dcm_en; + + addr += sizeof(struct physts_ie_17_user_info); + } + + return true; +} + +bool halbb_physts_ie_18(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_18_info *psts_18 = &physts->bb_physts_rslt_18_i; + struct physts_ie_18_info *ie_18 = NULL; + + ie_18 = (struct physts_ie_18_info *)addr; + psts_18->ie_18_addr = addr; + + psts_18->rx_time = (ie_18->rx_time_m<<8) | ie_18->rx_time_l; + psts_18->ch_len_lgcy_seg0 = ie_18->ch_len_lgcy_seg0; + psts_18->bw_det_seg0 = ie_18->bw_det_seg0; + psts_18->snr_idx_lgcy_seg0 = ie_18->snr_idx_lgcy_seg0; + psts_18->pdp_idx_lgcy_seg0 = ie_18->pdp_idx_lgcy_seg0; + psts_18->pfd_flow = (ie_18->pfd_flow_m<<8) | ie_18->pfd_flow_l; + psts_18->ch_len_lgcy_seg1 = ie_18->ch_len_lgcy_seg1; + psts_18->bw_det_seg1 = ie_18->bw_det_seg1; + psts_18->snr_idx_lgcy_seg1 = ie_18->snr_idx_lgcy_seg1; + psts_18->pdp_idx_lgcy_seg1 = ie_18->pdp_idx_lgcy_seg1; + psts_18->is_seg1_exist = ie_18->is_seg1_exist; + + return true; +} + +bool halbb_physts_ie_19(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_19_info *psts_19 = &physts->bb_physts_rslt_19_i; + struct physts_ie_19_info *ie_19 = NULL; + + ie_19 = (struct physts_ie_19_info *)addr; + psts_19->ie_19_addr = addr; + + psts_19->ppdu_inpwrdbm_p20 = ie_19->ppdu_inpwrdbm_p20; + psts_19->ppdu_inpwrdbm_s20 = ie_19->ppdu_inpwrdbm_s20; + psts_19->ppdu_inpwrdbm_s40 = ie_19->ppdu_inpwrdbm_s40; + psts_19->ppdu_inpwrdbm_s80 = ie_19->ppdu_inpwrdbm_s80; + psts_19->ppdu_inpwrdbm_per20_1 = ie_19->ppdu_inpwrdbm_per20_1; + psts_19->ppdu_inpwrdbm_per20_2 = ie_19->ppdu_inpwrdbm_per20_2; + psts_19->ppdu_inpwrdbm_per20_3 = ie_19->ppdu_inpwrdbm_per20_3; + psts_19->ppdu_inpwrdbm_per20_4 = ie_19->ppdu_inpwrdbm_per20_4; + psts_19->edcca_rpt_cnt_p20 = ie_19->edcca_rpt_cnt_p20; + psts_19->edcca_rpt_p20_max = ie_19->edcca_rpt_p20_max; + psts_19->edcca_rpt_p20_min = ie_19->edcca_rpt_p20_min; + psts_19->edcca_total_smp_cnt = ie_19->edcca_total_smp_cnt; + psts_19->edcca_rpt_cnt_s80 = ie_19->edcca_rpt_cnt_s80; + psts_19->edcca_rpt_cnt_s80_max = ie_19->edcca_rpt_cnt_s80_max; + psts_19->edcca_rpt_cnt_s80_min = ie_19->edcca_rpt_cnt_s80_min; + psts_19->pop_reg_pwr = ie_19->pop_reg_pwr; + psts_19->pop_trig_pwr = ie_19->pop_trig_pwr; + psts_19->early_drop_pwr = ie_19->early_drop_pwr; + psts_19->tx_over_flow = ie_19->tx_over_flow; + + return true; +} + +bool halbb_physts_ie_20(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_20_info *psts_20 = &physts->bb_physts_rslt_20_i; + + struct physts_ie_20_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_20_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/ + u8 i; + + physts_c = (struct physts_ie_20_cmn_info *)addr; + psts_20->ie_20_addr = addr; + addr += sizeof(struct physts_ie_20_cmn_info); + + //BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-20]n_user=%d\n", physts_c->n_user); + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + physts_u[i] = (struct physts_ie_20_user_info *)addr; + addr += sizeof(struct physts_ie_20_user_info); + + /* mapping to the bb struct */ + psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_0_seg_0 = + physts_u[i]->ch_smo_n_block_lgcy_sub_0_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_1_seg_0 = + physts_u[i]->ch_smo_n_block_lgcy_sub_1_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_2_seg_0 = + physts_u[i]->ch_smo_n_block_lgcy_sub_2_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_3_seg_0 = + physts_u[i]->ch_smo_n_block_lgcy_sub_3_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_en_lgcy_seg_0 = + physts_u[i]->ch_smo_en_lgcy_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_en_non_lgcy_seg_0 = + physts_u[i]->ch_smo_en_non_lgcy_seg_0; + psts_20->bb_physts_usr_info[i].ch_smo_n_block_non_lgcy_seg_0 = + physts_u[i]->ch_smo_n_block_non_lgcy_seg_0; + psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_0_seg_0 = + physts_u[i]->ch_len_non_lgcy_sts_0_seg_0; + psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_1_seg_0 = + physts_u[i]->ch_len_non_lgcy_sts_1_seg_0; + psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_2_seg_0 = + physts_u[i]->ch_len_non_lgcy_sts_2_seg_0; + psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_3_seg_0 = + physts_u[i]->ch_len_non_lgcy_sts_3_seg_0; + + psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_0_seg_0 = + physts_u[i]->snr_idx_non_lgy_sts_0_seg_0; + psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_1_seg_0 = + physts_u[i]->snr_idx_non_lgy_sts_1_seg_0; + psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_2_seg_0 = + (physts_u[i]->snr_idx_non_lgy_sts_2_seg_0_m<<2) | + physts_u[i]->snr_idx_non_lgy_sts_2_seg_0_l; + psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_3_seg_0 = + physts_u[i]->snr_idx_non_lgy_sts_3_seg_0; + + psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_0_seg_0 = + physts_u[i]->pdp_idx_non_lgcy_sts_0_seg_0; + psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_1_seg_0 = + (physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_0_m<<1) | + physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_0_l; + psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_2_seg_0 = + physts_u[i]->pdp_idx_non_lgcy_sts_2_seg_0; + psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_3_seg_0 = + physts_u[i]->pdp_idx_non_lgcy_sts_3_seg_0; + + psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_0_seg_0 = + physts_u[i]->snr_non_lgy_sts_0_seg_0; + psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_1_seg_0 = + physts_u[i]->snr_non_lgy_sts_1_seg_0; + psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_2_seg_0 = + physts_u[i]->snr_non_lgy_sts_2_seg_0; + psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_3_seg_0 = + physts_u[i]->snr_non_lgy_sts_3_seg_0; + + psts_20->bb_physts_usr_info[i].evm_ss_0_seg_0 = + physts_u[i]->evm_ss_0_seg_0; + psts_20->bb_physts_usr_info[i].evm_ss_1_seg_0 = + physts_u[i]->evm_ss_1_seg_0; + psts_20->bb_physts_usr_info[i].evm_ss_2_seg_0 = + physts_u[i]->evm_ss_2_seg_0; + psts_20->bb_physts_usr_info[i].evm_ss_3_seg_0 = + physts_u[i]->evm_ss_3_seg_0; + } + + return true; +} + +bool halbb_physts_ie_21(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_21_info *psts_21 = &physts->bb_physts_rslt_21_i; + + struct physts_ie_21_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_21_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/ + u8 i; + + physts_c = (struct physts_ie_21_cmn_info *)addr; + psts_21->ie_21_addr = addr; + addr += sizeof(struct physts_ie_21_cmn_info); + + //BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-21]n_user=%d\n", physts_c->n_user); + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + physts_u[i] = (struct physts_ie_21_user_info *)addr; + addr += sizeof(struct physts_ie_21_user_info); + + /* mapping to the bb struct */ + psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_0_seg_1 = + physts_u[i]->ch_smo_n_block_lgcy_sub_0_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_1_seg_1 = + physts_u[i]->ch_smo_n_block_lgcy_sub_1_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_2_seg_1 = + physts_u[i]->ch_smo_n_block_lgcy_sub_2_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_3_seg_1 = + physts_u[i]->ch_smo_n_block_lgcy_sub_3_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_en_lgcy_seg_1 = + physts_u[i]->ch_smo_en_lgcy_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_en_non_lgcy_seg_1 = + physts_u[i]->ch_smo_en_non_lgcy_seg_1; + psts_21->bb_physts_usr_info[i].ch_smo_n_block_non_lgcy_seg_1 = + physts_u[i]->ch_smo_n_block_non_lgcy_seg_1; + psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_0_seg_1 = + physts_u[i]->ch_len_non_lgcy_sts_0_seg_1; + psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_1_seg_1 = + physts_u[i]->ch_len_non_lgcy_sts_1_seg_1; + psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_2_seg_1 = + physts_u[i]->ch_len_non_lgcy_sts_2_seg_1; + psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_3_seg_1 = + physts_u[i]->ch_len_non_lgcy_sts_3_seg_1; + + psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_0_seg_1 = + physts_u[i]->snr_idx_non_lgy_sts_0_seg_1; + psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_1_seg_1 = + physts_u[i]->snr_idx_non_lgy_sts_1_seg_1; + psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_2_seg_1 = + (physts_u[i]->snr_idx_non_lgy_sts_2_seg_1_m<<2) | + physts_u[i]->snr_idx_non_lgy_sts_2_seg_1_l; + psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_3_seg_1 = + physts_u[i]->snr_idx_non_lgy_sts_3_seg_1; + + psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_0_seg_1 = + physts_u[i]->pdp_idx_non_lgcy_sts_0_seg_1; + psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_1_seg_1 = + (physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_1_m<<1) | + physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_1_l; + psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_2_seg_1 = + physts_u[i]->pdp_idx_non_lgcy_sts_2_seg_1; + psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_3_seg_1 = + physts_u[i]->pdp_idx_non_lgcy_sts_3_seg_1; + + psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_0_seg_1 = + physts_u[i]->snr_non_lgy_sts_0_seg_1; + psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_1_seg_1 = + physts_u[i]->snr_non_lgy_sts_1_seg_1; + psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_2_seg_1 = + physts_u[i]->snr_non_lgy_sts_2_seg_1; + psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_3_seg_1 = + physts_u[i]->snr_non_lgy_sts_3_seg_1; + + psts_21->bb_physts_usr_info[i].evm_ss_0_seg_1 = + physts_u[i]->evm_ss_0_seg_1; + psts_21->bb_physts_usr_info[i].evm_ss_1_seg_1 = + physts_u[i]->evm_ss_1_seg_1; + psts_21->bb_physts_usr_info[i].evm_ss_2_seg_1 = + physts_u[i]->evm_ss_2_seg_1; + psts_21->bb_physts_usr_info[i].evm_ss_3_seg_1 = + physts_u[i]->evm_ss_3_seg_1; + } + + return true; +} + +bool halbb_physts_ie_22(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct physts_ie_22_cmn_info *physts_c = NULL; /*common*/ + struct physts_ie_22_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/ + u8 i; + + physts_c = (struct physts_ie_22_cmn_info *)addr; + addr += sizeof(struct physts_ie_22_cmn_info); + + //BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-22] n_user=%d\n", physts_c->n_user); + + for (i = 0; i < physts_c->n_user; i++) { + if (i >= TB_USER_MAX) + break; + physts_u[i] = (struct physts_ie_22_user_info *)addr; + addr += sizeof(struct physts_ie_22_user_info); + } + + return true; +} + +bool halbb_physts_ie_24(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_24_info *psts_24 = &physts->bb_physts_rslt_24_i; + struct physts_ie_24_info *ie_24 = NULL; + + ie_24 = (struct physts_ie_24_info *)addr; + psts_24->ie_24_addr = addr; + + psts_24->pre_agc_step_a = ie_24->pre_agc_step_a; + psts_24->l_fine_agc_step_a = ie_24->l_fine_agc_step_a; + psts_24->ht_fine_agc_step_a = ie_24->ht_fine_agc_step_a; + psts_24->pre_gain_code_a = ie_24->pre_gain_code_a; + psts_24->l_fine_gain_code_a = ie_24->l_fine_gain_code_a; + psts_24->ht_fine_gain_code_a = ie_24->ht_fine_gain_code_a; + psts_24->l_dagc_a = ie_24->l_dagc_a; + psts_24->ht_dagc_a = ie_24->ht_dagc_a; + psts_24->pre_ibpwrdbm_a = ie_24->pre_ibpwrdbm_a; + psts_24->pre_wbpwrdbm_a = ie_24->pre_wbpwrdbm_a; + psts_24->l_ibpwrdbm_a = ie_24->l_ibpwrdbm_a; + psts_24->l_wbpwrdbm_a = ie_24->l_wbpwrdbm_a; + psts_24->ht_ibpwrdbm_a = ie_24->ht_ibpwrdbm_a; + psts_24->ht_wbpwrdbm_a = ie_24->ht_wbpwrdbm_a; + psts_24->l_dig_ibpwrdbm_a = ie_24->l_dig_ibpwrdbm_a; + psts_24->ht_dig_ibpwrdbm_a = ie_24->ht_dig_ibpwrdbm_a; + psts_24->lna_inpwrdbm_a = ie_24->lna_inpwrdbm_a; + psts_24->aci2sig_db = ie_24->aci2sig_db; + psts_24->sb5m_ratio_0 = ie_24->sb5m_ratio_0; + psts_24->sb5m_ratio_1 = ie_24->sb5m_ratio_1; + psts_24->sb5m_ratio_2 = ie_24->sb5m_ratio_2; + psts_24->sb5m_ratio_3 = ie_24->sb5m_ratio_3; + psts_24->aci_indicator_a = ie_24->aci_indicator_a; + psts_24->tia_shrink_indicator_a = ie_24->tia_shrink_indicator_a; + psts_24->pre_gain_code_tia_a = ie_24->pre_gain_code_tia_a; + psts_24->l_fine_gain_code_tia_a = ie_24->l_fine_gain_code_tia_a; + psts_24->ht_fine_gain_code_tia_a = ie_24->ht_fine_gain_code_tia_a; + psts_24->aci_det = ie_24->aci_det; + + return true; +} + +bool halbb_physts_ie_25(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_25_info *psts_25 = &physts->bb_physts_rslt_25_i; + struct physts_ie_25_info *ie_25 = NULL; + + ie_25 = (struct physts_ie_25_info *)addr; + psts_25->ie_25_addr = addr; + + psts_25->pre_agc_step_b = ie_25->pre_agc_step_b; + psts_25->l_fine_agc_step_b = ie_25->l_fine_agc_step_b; + psts_25->ht_fine_agc_step_b = ie_25->ht_fine_agc_step_b; + psts_25->pre_gain_code_b = ie_25->pre_gain_code_b; + psts_25->l_fine_gain_code_b = ie_25->l_fine_gain_code_b; + psts_25->ht_fine_gain_code_b = ie_25->ht_fine_gain_code_b; + psts_25->l_dagc_b = ie_25->l_dagc_b; + psts_25->ht_dagc_b = ie_25->ht_dagc_b; + psts_25->pre_ibpwrdbm_b = ie_25->pre_ibpwrdbm_b; + psts_25->pre_wbpwrdbm_b = ie_25->pre_wbpwrdbm_b; + psts_25->l_ibpwrdbm_b = ie_25->l_ibpwrdbm_b; + psts_25->l_wbpwrdbm_b = ie_25->l_wbpwrdbm_b; + psts_25->ht_ibpwrdbm_b = ie_25->ht_ibpwrdbm_b; + psts_25->ht_wbpwrdbm_b = ie_25->ht_wbpwrdbm_b; + psts_25->l_dig_ibpwrdbm_b = ie_25->l_dig_ibpwrdbm_b; + psts_25->ht_dig_ibpwrdbm_b = ie_25->ht_dig_ibpwrdbm_b; + psts_25->lna_inpwrdbm_b = ie_25->lna_inpwrdbm_b; + psts_25->aci2sig_db = ie_25->aci2sig_db; + psts_25->sb5m_ratio_0 = ie_25->sb5m_ratio_0; + psts_25->sb5m_ratio_1 = ie_25->sb5m_ratio_1; + psts_25->sb5m_ratio_2 = ie_25->sb5m_ratio_2; + psts_25->sb5m_ratio_3 = ie_25->sb5m_ratio_3; + psts_25->aci_indicator_b = ie_25->aci_indicator_b; + psts_25->tia_shrink_indicator_b = ie_25->tia_shrink_indicator_b; + psts_25->pre_gain_code_tia_b = ie_25->pre_gain_code_tia_b; + psts_25->l_fine_gain_code_tia_b = ie_25->l_fine_gain_code_tia_b; + psts_25->ht_fine_gain_code_tia_b = ie_25->ht_fine_gain_code_tia_b; + psts_25->aci_det = ie_25->aci_det; + + return true; +} + +bool halbb_physts_ie_26(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct physts_ie_26_info *ie_26 = NULL; + + ie_26 = (struct physts_ie_26_info *)addr; + + return true; +} + +bool halbb_physts_ie_27(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct physts_ie_27_info *ie_27 = NULL; + + ie_27 = (struct physts_ie_27_info *)addr; + + return true; +} + +bool halbb_physts_ie_28(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_28_info *psts_28 = &physts->bb_physts_rslt_28_i; + struct physts_ie_28_info *ie_28 = NULL; + + ie_28 = (struct physts_ie_28_info *)addr; + psts_28->ie_28_addr = addr; + + psts_28->ant_weight_a = (ie_28->ant_weight_a_m<<1) | ie_28->ant_weight_a_l; + psts_28->h3_real_a = ie_28->h3_real_a; + psts_28->h3_imag_a = ie_28->h3_imag_a; + psts_28->h4_real_a = ie_28->h4_real_a; + psts_28->h4_imag_a = ie_28->h4_imag_a; + psts_28->h5_real_a = ie_28->h5_real_a; + psts_28->h5_imag_a = ie_28->h5_imag_a; + psts_28->h6_real_a = ie_28->h6_real_a; + psts_28->h6_imag_a = ie_28->h6_imag_a; + psts_28->h7_real_a = ie_28->h7_real_a; + psts_28->h7_imag_a = ie_28->h7_imag_a; + psts_28->h8_real_a = ie_28->h8_real_a; + psts_28->h8_imag_a = ie_28->h8_imag_a; + psts_28->h9_real_a = ie_28->h9_real_a; + psts_28->h9_imag_a = ie_28->h9_imag_a; + psts_28->h10_real_a = ie_28->h10_real_a; + psts_28->h10_imag_a = ie_28->h10_imag_a; + psts_28->h11_real_a = ie_28->h11_real_a; + psts_28->h11_imag_a = ie_28->h11_imag_a; + psts_28->h12_real_a = ie_28->h12_real_a; + psts_28->h12_imag_a = ie_28->h12_imag_a; + psts_28->h13_real_a = ie_28->h13_real_a; + psts_28->h13_imag_a = ie_28->h13_imag_a; + psts_28->h14_real_a = ie_28->h14_real_a; + psts_28->h14_imag_a = ie_28->h14_imag_a; + psts_28->h15_real_a = ie_28->h15_real_a; + psts_28->h15_imag_a = ie_28->h15_imag_a; + psts_28->h16_real_a = ie_28->h16_real_a; + psts_28->h16_imag_a = ie_28->h16_imag_a; + psts_28->h17_real_a = ie_28->h17_real_a; + psts_28->h17_imag_a = ie_28->h17_imag_a; + + return true; +} + +bool halbb_physts_ie_29(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_29_info *psts_29 = &physts->bb_physts_rslt_29_i; + struct physts_ie_29_info *ie_29 = NULL; + + ie_29 = (struct physts_ie_29_info *)addr; + psts_29->ie_29_addr = addr; + + psts_29->ant_weight_b = (ie_29->ant_weight_b_m<<1) | ie_29->ant_weight_b_l; + psts_29->h3_real_b = ie_29->h3_real_b; + psts_29->h3_imag_b = ie_29->h3_imag_b; + psts_29->h4_real_b = ie_29->h4_real_b; + psts_29->h4_imag_b = ie_29->h4_imag_b; + psts_29->h5_real_b = ie_29->h5_real_b; + psts_29->h5_imag_b = ie_29->h5_imag_b; + psts_29->h6_real_b = ie_29->h6_real_b; + psts_29->h6_imag_b = ie_29->h6_imag_b; + psts_29->h7_real_b = ie_29->h7_real_b; + psts_29->h7_imag_b = ie_29->h7_imag_b; + psts_29->h8_real_b = ie_29->h8_real_b; + psts_29->h8_imag_b = ie_29->h8_imag_b; + psts_29->h9_real_b = ie_29->h9_real_b; + psts_29->h9_imag_b = ie_29->h9_imag_b; + psts_29->h10_real_b = ie_29->h10_real_b; + psts_29->h10_imag_b = ie_29->h10_imag_b; + psts_29->h11_real_b = ie_29->h11_real_b; + psts_29->h11_imag_b = ie_29->h11_imag_b; + psts_29->h12_real_b = ie_29->h12_real_b; + psts_29->h12_imag_b = ie_29->h12_imag_b; + psts_29->h13_real_b = ie_29->h13_real_b; + psts_29->h13_imag_b = ie_29->h13_imag_b; + psts_29->h14_real_b = ie_29->h14_real_b; + psts_29->h14_imag_b = ie_29->h14_imag_b; + psts_29->h15_real_b = ie_29->h15_real_b; + psts_29->h15_imag_b = ie_29->h15_imag_b; + psts_29->h16_real_b = ie_29->h16_real_b; + psts_29->h16_imag_b = ie_29->h16_imag_b; + psts_29->h17_real_b = ie_29->h17_real_b; + psts_29->h17_imag_b = ie_29->h17_imag_b; + + return true; +} + +bool halbb_physts_ie_30(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct physts_ie_30_info *ie_30 = NULL; + + ie_30 = (struct physts_ie_30_info *)addr; + + return true; +} + +bool halbb_physts_ie_31(struct bb_info *bb, + u8 *addr, + u16 ie_length, + struct physts_rxd *desc) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct physts_ie_31_info *ie_31 = NULL; + + ie_31 = (struct physts_ie_31_info *)addr; + + return true; +} + +void halbb_physts_rpt_gen(struct bb_info *bb, struct physts_result *rpt, + bool physts_rpt_valid, struct physts_rxd *desc, + bool is_cck_rate) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i; + struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i; + u16 tmp_val16 = 0; + u8 i = 0; + + rpt->physts_rpt_valid = physts_rpt_valid; + rpt->rssi_avg = psts_h->rssi_avg; + rpt->rssi[0] = psts_h->rssi[0]; + rpt->rssi[1] = psts_h->rssi[1]; + rpt->rssi[2] = psts_h->rssi[2]; + rpt->rssi[3] = psts_h->rssi[3]; + rpt->ie_map_type = psts_h->ie_map_type; + + for (i = 0; i < 4; i++) { + if (psts_h->rssi[i] == 0) + continue; + + tmp_val16 = SUBTRACT_TO_0((((u16)psts_h->rssi[i]) << 2), bb->bb_env_mntr_i.idle_pwr_physts); + rpt->snr_td[i] = GET_MA_VAL(tmp_val16, 3); + } + + rpt->is_mu_pkt = (desc->is_su) ? 0 : 1; /*TBD*/ + + if (!physts_rpt_valid) + return; + + if (!desc->is_to_self) + return; + + if (is_cck_rate) { + rpt->ch_idx = bb->bb_ch_i.rf_central_ch_cfg; + rpt->rx_bw = CHANNEL_WIDTH_20; + rpt->rxsc = 0; + rpt->is_bf = 0; + rpt->snr_td_avg = SUBTRACT_TO_0((u16)psts_h->rssi_avg, psts_0->avg_idle_noise_pwr_cck); + rpt->snr_fd_avg = 0; /*HW not support*/ + rpt->is_su = 1; + rpt->is_ldpc = 0; + rpt->is_stbc = 0; + } else { + rpt->ch_idx = psts_1->ch_idx; + rpt->rx_bw = psts_1->bw_idx; + rpt->rxsc = psts_1->rxsc; + rpt->is_bf = psts_1->is_bf; + rpt->snr_fd_avg = psts_1->snr_avg; + rpt->snr_td_avg = SUBTRACT_TO_0((u16)psts_h->rssi_avg, psts_1->avg_idle_noise_pwr); + rpt->is_su = psts_1->is_su; + rpt->is_ldpc = psts_1->is_ldpc; + rpt->is_stbc = psts_1->is_stbc; + + for (i = 0; i < 4; i++) { + if (psts_h->rssi[i] == 0) + continue; + + rpt->snr_fd[i] = (((rpt->snr_fd_avg << 1) + rpt->rssi_avg - rpt->rssi[i]) >> 1); + } + } + + BB_DBG(bb, DBG_PHY_STS, "[RPT] rssi_u81=(%d){%d,%d,%d,%d} idle_pwr_physts_u83=%d\n", + rpt->rssi_avg, rpt->rssi[0], rpt->rssi[1], rpt->rssi[2], rpt->rssi[3], + bb->bb_env_mntr_i.idle_pwr_physts); + BB_DBG(bb, DBG_PHY_STS, "[RPT] snr_td=(%d){%d,%d,%d,%d}\n", + rpt->snr_td_avg, rpt->snr_td[0], rpt->snr_td[1], rpt->snr_td[2], rpt->snr_td[3]); + BB_DBG(bb, DBG_PHY_STS, "[RPT] snr_fd =(%d){%d,%d,%d,%d}\n", + rpt->snr_fd_avg, rpt->snr_fd[0], rpt->snr_fd[1], rpt->snr_fd[2], rpt->snr_fd[3]); +} + +void halbb_physts_print(struct bb_info *bb, struct physts_rxd *desc, + u16 total_len, u8 *addr, u32 physts_bitmap) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i; + u8 i = 0, curr_ie = 0; + + if (physts->physts_dump_mode == 0) + return; + + if (!physts->show_phy_sts_all_pkt) { + if (!desc->is_to_self) + return; + } + + if (physts->show_phy_sts_cnt >= physts->show_phy_sts_max_cnt) + return; + + physts->show_phy_sts_cnt++; + + BB_TRACE("[Dump_idx:%04d][%d: %s] len=%04d bitmap=0x%08x\n", + bb->bb_physts_i.physts_dump_idx, + psts_h->ie_map_type, + bb_physts_bitmap_type_t[psts_h->ie_map_type], + total_len, physts_bitmap); + + bb->bb_physts_i.physts_dump_idx++; + + if (bb->bb_physts_i.physts_dump_mode & BIT(0)) { + BB_TRACE("[HDR]\n"); + halbb_print_buff_64(bb, addr, PHYSTS_HDR_LEN); + addr += PHYSTS_HDR_LEN; + total_len -= PHYSTS_HDR_LEN; + + for (i = 0; i < IE_PHYSTS_LEN_ALL; i++) { + if (total_len < 8) + break; + + curr_ie = *addr & 0x1f; + BB_TRACE("===[IE_%02d]===\n", curr_ie); + halbb_print_buff_64(bb, addr, physts->ie_len_curr[i]); + addr += physts->ie_len_curr[i]; + if (total_len >= physts->ie_len_curr[i]) + total_len -= physts->ie_len_curr[i]; + } + BB_TRACE("----------------------------\n"); + } + + if (bb->bb_physts_i.physts_dump_mode & BIT(1)) { + halbb_print_rate_2_buff(bb, desc->data_rate, desc->gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE); + + BB_TRACE("is_to_self=%d, su=%d, user_num=%d, phy_idx=%d, total_len=%d\n", + desc->is_to_self, desc->is_su, desc->user_num, desc->phy_idx, total_len); + BB_TRACE("Rate= %s (0x%x-%x), macid_su=%d\n", + bb->dbg_buf, desc->data_rate, desc->gi_ltf, desc->macid_su); + + if (desc->user_num >= 4) + return; + + for (i = 0; i < desc->user_num; i++) { + BB_TRACE("[%d]bcn=%d, ctrl=%d, data=%d, mgnt=%d\n", i, + desc->user_i[i].is_bcn, desc->user_i[i].is_ctrl, + desc->user_i[i].is_data, desc->user_i[i].is_mgnt); + } + BB_TRACE("----------------------------\n"); + halbb_physts_detail_dump(bb, physts_bitmap, 0xffffffff); + } + BB_TRACE("==============================================\n"); +} + +bool halbb_physts_parsing(struct bb_info *bb, + u8 *addr, + u16 physts_total_length, + struct physts_rxd *desc, + struct physts_result *bb_rpt) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + u8 physts_ie_len_tab[IE_PHYSTS_LEN_ALL] = {2, 4, 3, 3, 1, 1, 1, 1, + VAR_LENGTH, 1, VAR_LENGTH, 22, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH, + VAR_LENGTH, VAR_LENGTH, 2, 3, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH, 0, + 3, 3, 3, 3, 4, 4, 4, 4}; /*Unit: 8Byte*/ + enum bb_physts_hdr_t physts_hdr_t; + u32 physts_bitmap = 0; + u16 ie_len; + u16 acc_ie_len = 0; + u16 total_ie_len = physts_total_length - PHYSTS_HDR_LEN; /*Unit: Byte*/ + u16 ie_length_hdr = 0; + u8 i = 0; + u8 curr_ie = 0xff; + u8 *addr_in_bkp = addr; + bool is_cck_rate = false; + bool is_valid = true; + +#ifdef HALBB_DBCC_SUPPORT + #ifdef HALBB_DBCC_DVLP_FLAG + if (desc->phy_idx == HW_PHY_1) + return false; + #endif + bb = halbb_get_curr_bb_pointer(bb, desc->phy_idx); + //BB_DBG(bb, DBG_PHY_STS, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx); +#endif + + if (desc->is_su) + desc->macid_su = desc->user_i[0].macid; + + physts->bb_physts_cnt_i.all_cnt++; + if (desc->is_to_self) { + physts->bb_physts_cnt_i.is_2_self_cnt++; + } + + /*---[Physts header parsing]------------------------------------------*/ + ie_length_hdr = halbb_physts_ie_hdr(bb, addr, desc); + addr += PHYSTS_HDR_LEN; + + if ((ie_length_hdr << 3) != physts_total_length) { + physts->bb_physts_cnt_i.err_len_cnt++; + //BB_DBG(bb, DBG_PHY_STS, "len_hdr error\n"); + is_valid = false; + //return false; + goto PARSING_END; + } + + if (!desc->is_to_self && !physts->show_phy_sts_all_pkt) { + /*Only parsing Hdr if the packet is not "to_self"*/ + is_valid = true; + goto PARSING_END; + } + + if (total_ie_len == 0) { + is_valid = true; + goto PARSING_END; + } + + halbb_rate_idx_parsor(bb, desc->data_rate, (enum rtw_gi_ltf)desc->gi_ltf, &physts->bb_rate_i); + is_cck_rate = halbb_is_cck_rate(bb, desc->data_rate); + + /*---[Physts per IE parsing]------------------------------------------*/ + for (i = 0; i < IE_PHYSTS_LEN_ALL; i++) { + curr_ie = *addr & 0x1f; + + if (physts_bitmap & BIT(curr_ie)) { + is_valid = false; + break; + } + + if (physts_ie_len_tab[curr_ie] != VAR_LENGTH) { + physts_hdr_t = HDR_TYPE1; + ie_len = (u16)(physts_ie_len_tab[curr_ie] << 3); /*8-byte to byte*/ + } else { + physts_hdr_t = HDR_TYPE2; + ie_len = (u16)((((*(addr + 1) & 0xf) << 3) | ((*addr & 0xe0) >> 5)) << 3); + } + + if (curr_ie == IE00_CMN_CCK) { + halbb_physts_ie_00(bb, addr, ie_len, desc); + } else if (curr_ie == IE01_CMN_OFDM) { + halbb_physts_ie_01(bb, addr, ie_len, desc); + } else if (curr_ie == IE02_CMN_EXT_AX) { + halbb_physts_ie_02(bb, addr, ie_len, desc); + } else if (curr_ie == IE03_CMN_EXT_SEG_1) { + halbb_physts_ie_03(bb, addr, ie_len, desc); + } else if (curr_ie >= IE04_CMN_EXT_PATH_A && + curr_ie <= IE07_CMN_EXT_PATH_D) { + halbb_physts_ie_04_07(bb, curr_ie, addr, ie_len, desc); + } else if (curr_ie == IE08_FTR_CH) { + halbb_physts_ie_08(bb, addr, ie_len, desc); + } else if (curr_ie == IE09_FTR_PLCP_0) { + halbb_physts_ie_09(bb, addr, ie_len, desc); + } else if (curr_ie == IE10_FTR_PLCP_EXT) { + halbb_physts_ie_10(bb, addr, ie_len, desc); + } else if (curr_ie == IE11_FTR_PLCP_HISTOGRAM) { + halbb_physts_ie_11(bb, addr, ie_len, desc); + } else if (curr_ie == IE12_MU_EIGEN_INFO) { + halbb_physts_ie_12(bb, addr, ie_len, desc); + } else if (curr_ie == IE13_DL_MU_DEF) { + halbb_physts_ie_13(bb, addr, ie_len, desc); + } else if (curr_ie == IE14_TB_UL_CQI) { + halbb_physts_ie_14(bb, addr, ie_len, desc); + } else if (curr_ie == IE15_TB_UL_DEF) { + halbb_physts_ie_15(bb, addr, ie_len, desc); + } else if (curr_ie == IE17_TB_UL_CTRL) { + halbb_physts_ie_17(bb, addr, ie_len, desc); + } else if (curr_ie == IE18_DBG_OFDM_FD_CMN) { + halbb_physts_ie_18(bb, addr, ie_len, desc); + } else if (curr_ie == IE19_DBG_OFDM_TD_CMN) { + halbb_physts_ie_19(bb, addr, ie_len, desc); + } else if (curr_ie == IE20_DBG_OFDM_FD_USER_SEG_0) { + halbb_physts_ie_20(bb, addr, ie_len, desc); + } else if (curr_ie == IE21_DBG_OFDM_FD_USER_SEG_1) { + halbb_physts_ie_21(bb, addr, ie_len, desc); + } else if (curr_ie == IE22_DBG_OFDM_FD_USER_AGC) { + halbb_physts_ie_22(bb, addr, ie_len, desc); + } else if (curr_ie == IE24_DBG_OFDM_TD_PATH_A) { + halbb_physts_ie_24(bb, addr, ie_len, desc); + } else if (curr_ie == IE25_DBG_OFDM_TD_PATH_B) { + halbb_physts_ie_25(bb, addr, ie_len, desc); + } else if (curr_ie == IE26_DBG_OFDM_TD_PATH_C) { + halbb_physts_ie_26(bb, addr, ie_len, desc); + } else if (curr_ie == IE27_DBG_OFDM_TD_PATH_D) { + halbb_physts_ie_27(bb, addr, ie_len, desc); + } else if (curr_ie == IE28_DBG_CCK_PATH_A) { + halbb_physts_ie_28(bb, addr, ie_len, desc); + } else if (curr_ie == IE29_DBG_CCK_PATH_B) { + halbb_physts_ie_29(bb, addr, ie_len, desc); + } else if (curr_ie == IE30_DBG_CCK_PATH_C) { + halbb_physts_ie_30(bb, addr, ie_len, desc); + } else if (curr_ie == IE31_DBG_CCK_PATH_D) { + halbb_physts_ie_31(bb, addr, ie_len, desc); + } else { + break; + } + + physts->ie_len_curr[i] = ie_len; + + addr += ie_len; + acc_ie_len += ie_len; + physts_bitmap |= BIT(curr_ie); + + BB_DBG(bb, DBG_PHY_STS, "IE=%d, Hdr_type=%d, len=%d, acc_ie_len=%d\n", + curr_ie, physts_hdr_t, ie_len, acc_ie_len); + + if (acc_ie_len == total_ie_len) { + is_valid = true; + physts->bb_physts_cnt_i.ok_ie_cnt++; + break; + } else if (acc_ie_len > total_ie_len) { + is_valid = false; + physts->bb_physts_cnt_i.err_ie_cnt++; + break; + } + } + + BB_DBG(bb, DBG_PHY_STS, "[%d]Parsing_OK = %d, bitmap=0x%x\n", + physts->bb_physts_cnt_i.all_cnt, is_valid, physts_bitmap); + + /*===================================================================*/ +PARSING_END: + halbb_physts_rpt_gen(bb, bb_rpt, is_valid, desc, is_cck_rate); + physts->is_valid = is_valid; + + if (!is_valid) + return false; + + if (desc->is_to_self) { + physts->physts_bitmap_recv = physts_bitmap; + + halbb_cmn_rpt(bb, desc); + #ifdef HALBB_CFO_TRK_SUPPORT + halbb_parsing_cfo(bb, physts_bitmap, desc); + #endif + + #ifdef HALBB_ANT_DIV_SUPPORT + halbb_antdiv_phy_sts(bb); + #endif + } + + halbb_physts_print(bb, desc, physts_total_length, addr_in_bkp, physts_bitmap); + + return true; +} + +void +halbb_phy_sts_manual_trig(struct bb_info *bb, enum bb_mode_type mode, u8 ss) +{ + struct physts_rxd rxdesc = {0}; + struct physts_result bb_rpt = {0}; + u8 i = 0; + u8 rate_tmp = 0; + + bb->u8_dummy++; + + BB_DBG(bb, DBG_PHY_STS, "[%s]\n", __func__); + + if (ss == 0) + ss = 1; + else if (ss >= 2) + ss= 2; + + if (mode == BB_LEGACY_MODE) { + rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS; + rxdesc.data_rate = rate_tmp; + } else if (mode == BB_HT_MODE) { + rate_tmp = bb->u8_dummy % HT_NUM_MCS; + rate_tmp += (ss - 1) * 8; + rxdesc.data_rate = BB_HT_MCS(rate_tmp); + } else if (mode == BB_VHT_MODE) { + rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS; + rxdesc.data_rate = BB_VHT_MCS(ss, rate_tmp); + } else if (mode == BB_HE_MODE) { + rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS; + rxdesc.data_rate = BB_HE_MCS(ss, rate_tmp); + } + + BB_DBG(bb, DBG_PHY_STS, "rate = %d\n", rxdesc.data_rate); + + rxdesc.gi_ltf = 0; + rxdesc.is_su = 1; + rxdesc.macid_su = 0; + rxdesc.user_num = 0; + rxdesc.is_to_self = 1; + + for (i = 0; i < rxdesc.user_num; i++) { + rxdesc.user_i[i].macid = 0; + rxdesc.user_i[i].is_data = 1; + rxdesc.user_i[i].is_ctrl = 0; + rxdesc.user_i[i].is_mgnt = 0; + rxdesc.user_i[i].is_bcn = 0; + } + + halbb_physts_parsing(bb, (u8 *)phy_sts_dbg, sizeof(phy_sts_dbg), &rxdesc, &bb_rpt); +} + +void halbb_physts_watchdog(struct bb_info *bb) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i; + + if (cmn_rpt->bb_pkt_cnt_mu_i.pkt_cnt_all != 0) + cmn_rpt->consec_idle_prd_mu = 0; + else + cmn_rpt->consec_idle_prd_mu++; + + BB_DBG(bb, DBG_COMMON_FLOW, "su_cnt=%d, mu_cnt=%d\n", + cmn_rpt->bb_pkt_cnt_su_i.pkt_cnt_all, + cmn_rpt->bb_pkt_cnt_mu_i.pkt_cnt_all); + + /*[Phy-sts control]*/ + physts->show_phy_sts_cnt = 0; + + physts->bb_physts_cnt_i.all_cnt = 0; + physts->bb_physts_cnt_i.is_2_self_cnt = 0; + physts->bb_physts_cnt_i.ok_ie_cnt = 0; + physts->bb_physts_cnt_i.err_ie_cnt = 0; + physts->bb_physts_cnt_i.err_len_cnt = 0; +} + +void halbb_physts_parsing_init(struct bb_info *bb) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i; + u32 u32_tmp = 0; + u32 mask_tmp = 0; + u8 i = 0; + + if(phl_is_mp_mode(bb->phl_com)) + halbb_physts_brk_fail_rpt_en(bb, true, bb->bb_phy_idx); + else + halbb_physts_brk_fail_rpt_en(bb, false, bb->bb_phy_idx); + + /*Enable IE Pages 9*/ + for (i = 0; i < PHYSTS_BITMAP_NUM; i++) { + u32_tmp = halbb_physts_ie_bitmap_get(bb, i); + + if (i >= CCK_PKT) { + u32_tmp |= BIT(IE09_FTR_PLCP_0); + halbb_physts_ie_bitmap_set(bb, i, u32_tmp); + u32_tmp = halbb_physts_ie_bitmap_get(bb, i); + } + physts->bitmap_type[i] = u32_tmp; + } + /*[MP Mode] Enable extend path info A~D*/ + if(phl_is_mp_mode(bb->phl_com)) { + mask_tmp = (u32)halbb_gen_mask(IE04_CMN_EXT_PATH_A + bb->num_rf_path - 1, IE04_CMN_EXT_PATH_A); + //BB_DBG(bb, DBG_DBG_API, "mask_tmp = 0x%x\n", mask_tmp); + for (i = 0; i < PHYSTS_BITMAP_NUM; i++) { + u32_tmp = halbb_physts_ie_bitmap_get(bb, i); + + if (i >= LEGACY_OFDM_PKT) { + u32_tmp |= mask_tmp; + bb->num_rf_path; + + halbb_physts_ie_bitmap_set(bb, i, u32_tmp); + u32_tmp = halbb_physts_ie_bitmap_get(bb, i); + } + physts->bitmap_type[i] = u32_tmp; + } + } + + halbb_physts_ie_bitmap_en(bb, HE_MU, IE13_DL_MU_DEF, true); + halbb_physts_ie_bitmap_en(bb, VHT_MU, IE13_DL_MU_DEF, true); + + physts->show_phy_sts_all_pkt = false; + physts->show_phy_sts_max_cnt = 5; + physts->show_phy_sts_cnt = 0; +} + +void halbb_physts_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i; + u32 val[10] = {0}; + u32 u32_tmp = 0; + u8 ie11_ever_used = 0; + u8 i; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dump {0:dis, 1: raw data, 2: msg, 3: raw + msg}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "filter {max_num_per_2s} {not_2_self_pkt_en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "brk_rpt_en {en} :[enable physts of brk&fail pkt]\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bitmap show\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "bitmap set {idx, all, or} {hex_val}\n"); + return; + } + + if (_os_strcmp(input[1], "bitmap") == 0) { + if (_os_strcmp(input[2], "show") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Show all IE BITMAP\n"); + } else if (_os_strcmp(input[2], "set") == 0) { + HALBB_SCAN(input[4], DCMD_HEX, &val[1]); + if (_os_strcmp(input[3], "all") == 0) { + for (i = 0; i < PHYSTS_BITMAP_NUM; i++) + halbb_physts_ie_bitmap_set(bb, i, val[1]); + } else if (_os_strcmp(input[3], "or") == 0) { + for (i = 0; i < PHYSTS_BITMAP_NUM; i++) { + u32_tmp = val[1] | halbb_physts_ie_bitmap_get(bb, i); + halbb_physts_ie_bitmap_set(bb, i, u32_tmp); + } + } else { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + halbb_physts_ie_bitmap_set(bb, val[0], val[1]); + } + } + + for (i = 0; i < PHYSTS_BITMAP_NUM; i++) { + u32_tmp = halbb_physts_ie_bitmap_get(bb, i); + + if (physts->bitmap_type[i] != u32_tmp) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Warning] Mismatch drv_para=0x%08x\n", + physts->bitmap_type[i]); + } + + if (ie11_ever_used == 0) + ie11_ever_used = (u32_tmp & BIT(11)) ? 1 : 0; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "IE_BITMAP[%02d]=0x%08x : %s\n", + i, u32_tmp, bb_physts_bitmap_type_t[i]); + } + /*IE-11 HW enable*/ + halbb_set_reg(bb, cr->plcp_hist, cr->plcp_hist_m, ie11_ever_used); + } else if (_os_strcmp(input[1], "filter") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + bb->bb_physts_i.show_phy_sts_max_cnt = (u16)val[0]; + bb->bb_physts_i.show_phy_sts_all_pkt = (bool)val[1]; + + physts->show_phy_sts_cnt = 0; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "show_max_num=%d, show_not2self_pkt_en=%d\n\n", + bb->bb_physts_i.show_phy_sts_max_cnt, + bb->bb_physts_i.show_phy_sts_all_pkt); + } else if (_os_strcmp(input[1], "dump") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + bb->bb_physts_i.physts_dump_idx = 0; + bb->bb_physts_i.physts_dump_mode = (u8)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "physts_dump_mode=%d\n", bb->bb_physts_i.physts_dump_mode); + + if (bb->bb_physts_i.physts_dump_mode != 0) + halbb_physts_td_time_rpt_en(bb, true, bb->bb_phy_idx); + + } else if (_os_strcmp(input[1], "trig") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + halbb_phy_sts_manual_trig(bb, (enum bb_mode_type)val[0], (u8)val[1]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Physts manual trigger\n"); + } else if (_os_strcmp(input[1], "brk_rpt_en") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + halbb_physts_brk_fail_rpt_en(bb, (bool)val[0], bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "brk_rpt_en = %d\n",val[0]); + } +} + +void halbb_cr_cfg_physts_init(struct bb_info *bb) +{ + struct bb_physts_info *physts = &bb->bb_physts_i; + struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->plcp_hist = PLCP_HISTOGRAM_EN_A; + cr->plcp_hist_m = PLCP_HISTOGRAM_EN_A_M; + cr->bitmap_search_fail = PHY_STS_BITMAP_SEARCH_FAIL_A; + cr->period_cnt_en = PERIOD_CNT_EN_A; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->plcp_hist = PLCP_HISTOGRAM_EN_C; + cr->plcp_hist_m = PLCP_HISTOGRAM_EN_C_M; + cr->bitmap_search_fail = PHY_STS_BITMAP_SEARCH_FAIL_C; + cr->period_cnt_en = PERIOD_CNT_EN_C; + break; + #endif + + default: + break; + } + +} + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_physts.h b/phl/hal_g6/phy/bb/halbb_physts.h new file mode 100644 index 0000000..978c1a2 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_physts.h @@ -0,0 +1,746 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PHYSTS_H__ +#define __HALBB_PHYSTS_H__ + +#define VAR_LENGTH 0xff +#define TRANS_2_RSSI(X) (X >> 1) +#define PHYSTS_HDR_LEN 8 +#define TB_USER_MAX 4 +#define MU_USER_MAX 4 +#define PSTS_USR(x,y) psts_##x_usr_##y + +#define IE11_PKT_INFO_LEN 10 + +enum bb_physts_bw_info{ + PSTS_BW5 = 0, + PSTS_BW10 = 1, + PSTS_BW20 = 2, + PSTS_BW40 = 3, + PSTS_BW80 = 4, + PSTS_BW160 = 5, + PSTS_BW80_80 = 6, + PSTS_BW_MAX +}; + +enum bb_physts_ie_t { + IE00_CMN_CCK = 0, + IE01_CMN_OFDM = 1, + IE02_CMN_EXT_AX = 2, + IE03_CMN_EXT_SEG_1 = 3, + IE04_CMN_EXT_PATH_A = 4, + IE05_CMN_EXT_PATH_B = 5, + IE06_CMN_EXT_PATH_C = 6, + IE07_CMN_EXT_PATH_D = 7, + IE08_FTR_CH = 8, + IE09_FTR_PLCP_0 = 9, + IE10_FTR_PLCP_EXT = 10, + IE11_FTR_PLCP_HISTOGRAM = 11, + IE12_MU_EIGEN_INFO = 12, + IE13_DL_MU_DEF = 13, + IE14_TB_UL_CQI = 14, + IE15_TB_UL_DEF = 15, + IE16_RSVD16 = 16, + IE17_TB_UL_CTRL = 17, + IE18_DBG_OFDM_FD_CMN = 18, + IE19_DBG_OFDM_TD_CMN = 19, + IE20_DBG_OFDM_FD_USER_SEG_0 = 20, + IE21_DBG_OFDM_FD_USER_SEG_1 = 21, + IE22_DBG_OFDM_FD_USER_AGC = 22, + IE23_RSVD23 = 23, + IE24_DBG_OFDM_TD_PATH_A = 24, + IE25_DBG_OFDM_TD_PATH_B = 25, + IE26_DBG_OFDM_TD_PATH_C = 26, + IE27_DBG_OFDM_TD_PATH_D = 27, + IE28_DBG_CCK_PATH_A = 28, + IE29_DBG_CCK_PATH_B = 29, + IE30_DBG_CCK_PATH_C = 30, + IE31_DBG_CCK_PATH_D = 31, + IE_PHYSTS_LEN_ALL = 32 +}; + +struct bb_info; + +static const char bb_physts_bitmap_type_t[][9] = { + "SRH_FAIL", + "BRK_BY_TX", + "CCA_SPF", + "OFDM_BRK", + "CCK_BRK", + "DLMU_SPF", + "HE_MU", + "VHT_MU", + "TB_SPF", + "N/A", + "TB", + "CCK", + "LEGACY", + "HT", + "VHT", + "HE", +}; + +struct bb_physts_rslt_hdr_info { + u8 rssi[4]; + u8 rssi_avg; + enum bb_physts_bitmap_t ie_map_type; +}; + +struct bb_physts_rslt_0_info { + u8 *ie_00_addr; + u8 rx_path_en_cck; + s16 cfo_avg_cck; /*S(12,2), -512~+511.75 kHz*/ + u8 evm_avg_cck; + u8 avg_idle_noise_pwr_cck; /*u(8,1)*/ + u8 pop_idx_cck; + u16 rpl; /*U(9,2)*/ +}; + +struct bb_physts_rslt_1_info { + u8 *ie_01_addr; + u8 rx_path_en; + s16 cfo_avg; /*S(12,2), -512~+511.75 kHz, FD tracking CFO*/ + s16 cfo_pab_avg; /*S(12,2), -512~+511.75 kHz, preamble CFO*/ + u8 evm_max; + u8 evm_min; + u8 snr_avg; + u8 cn_avg; + u8 avg_idle_noise_pwr; /*u(8,1)*/ + u8 pop_idx; + u8 rxsc; + u8 ch_idx; + u8 rpl_fd; + enum channel_width bw_idx; + bool is_su; /*if (not MU && not OFDMA), is_su = 1*/ + bool is_ldpc; + bool is_ndp; + bool is_stbc; + bool grant_bt; + bool is_awgn; + bool is_bf; +}; + +struct bb_physts_rslt_2_info { + u8 *ie_02_addr; + u8 max_nsts; + u8 ltf_type; + u8 gi; + s32 c_cfo_i; + u8 rx_info_1; + u8 rx_state_feq; + s32 c_cfo_q; + u8 est_cmped_phase; + u8 pkt_extension; + s32 f_cfo_i; + u8 n_ltf; + u16 n_sym; + s32 f_cfo_q; + bool midamble; + bool is_mu_mimo; + bool is_dl_ofdma; + bool is_dcm; + bool is_doppler; +}; + +struct bb_physts_rslt_3_info { + u8 *ie_03_addr; + u8 avg_cn_seg1; + u8 sigval_below_th_tone_cnt_seg1; + u8 cn_excess_th_tone_cnt_seg1; + u16 avg_cfo_seg1; + u16 avg_cfo_premb_seg1; + u8 est_cmped_phase_seg1; + u8 avg_snr_seg1; + u32 c_cfo_i_seg1; + u32 c_cfo_q_seg1; + u32 f_cfo_i_seg1; + u32 f_cfo_q_seg1; + u8 ch_idx_seg1; + u8 evm_max_seg1; + u8 evm_min_seg1; +}; + +struct bb_physts_rslt_4_to_7_info { + u8 *ie_04_07_addr; + u8 ant_idx; + s8 sig_val_y; + u8 rf_gain_idx; + u8 snr_lgy; + u8 evm_ss_y; + u8 td_ant_weight; + s8 dc_est_re; + s8 dc_est_im; + bool rf_tia_gain_idx; + bool tia_shrink_indicator; + //bool ant_idx_0_msb; +}; + +struct bb_physts_rslt_8_info { + u8 *ie_08_addr; + u8 rxsc; + u8 n_rx; + u8 n_sts; + u16 ch_info_len; + u8 evm_1_sts; + u8 evm_2_sts; + u8 avg_idle_noise_pwr; + bool is_ch_info_len_valid; +}; + +struct bb_physts_rslt_9_info { + u8 *ie_09_addr; + u32 l_sig; + u32 sig_a1; + u16 sig_a2; +}; + +struct bb_physts_rslt_10_info { + u8 *ie_10_addr; + u8 tmp; +}; + +struct bb_physts_rslt_11_info { + u8 *ie_11_addr; + u32 l_sig; + u32 sig_a1; + u16 sig_a2; + u16 time_stamp; + u8 rx_pkt_info_idx; + u8 tx_pkt_info_idx; +}; + +struct bb_physts_user_info_ie_12{ + u8 sig_val_ss0_seg_cr_user_i; + u8 sig_val_ss1_seg_cr_user_i; + u8 sig_val_ss2_seg_cr_user_i; + u8 sig_val_ss3_seg_cr_user_i; + u8 sig_bad_tone_cnt_seg_cr_user_i; + u8 cn_bad_tone_cnt_seg_cr_user_i; +}; + +struct bb_physts_rslt_12_info { + u8 *ie_12_addr; + u8 n_user; + struct bb_physts_user_info_ie_12 bb_physts_uer_info[MU_USER_MAX]; +}; + +struct bb_physts_user_info_ie_13{ + u8 is_bf; + u8 fec_type; + u8 mcs; + u8 pilot_exist; + u8 n_sts; + u8 n_sts_ru_total; + u8 is_awgn; + u8 is_mu_mimo; + u8 pdp_he_ltf_and_gi_type; + u8 start_sts; + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + s8 snr; + u8 ru_alloc; + u8 is_dcm; + u8 avg_cn_seg_cr; + u16 sta_id; +}; + +struct bb_physts_rslt_13_info { + u8 *ie_13_addr; + u8 n_user; + struct bb_physts_user_info_ie_13 bb_physts_uer_info[MU_USER_MAX]; + u8 n_not_sup_sta; +}; + +struct bb_physts_user_info_ie_14{ + u8 cqi_bitmap_ul_tb; + u8 cqi_raw_len_ul_tb; + u8 *cqi_raw_ul_tb_addr; +}; + +struct bb_physts_rslt_14_info { + u8 *ie_14_addr; + u8 rxinfo_ndp_en; + u8 n_user; + struct bb_physts_user_info_ie_14 bb_physts_uer_info[MU_USER_MAX]; + +}; + +struct bb_physts_user_info_ie_15{ + /* 64bit cmn_info */ + u8 mcs; + u8 fec_type; + u8 is_bf; + + u8 n_sts_ru_total; + u8 n_sts; + u8 pilot_exist; + + u8 start_sts; + u8 pdp_he_ltf_and_gi_type; + u8 is_mu_mimo; + u8 is_awgn; + + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + s8 snr; + u8 ru_alloc; + + u8 avg_cn_seg_cr; + u8 is_dcm; + + /* others */ + u8 uid; + s16 avg_cfo_seg0; + u16 rssi_m_ul_tb; +}; + +struct bb_physts_rslt_15_info { + u8 *ie_15_addr; + u8 n_user; + struct bb_physts_user_info_ie_15 bb_physts_uer_info[MU_USER_MAX]; + +}; + +struct bb_physts_rslt_16_info { + u8 *ie_16_addr; + u8 tmp; +}; + +struct bb_physts_cmn_info_ie_17 { + bool stbc_en; + bool ldpc_extra; + bool doppler_en; + bool midamle_mode; + u8 gi_type; + u8 ltf_type; + u8 n_ltf; + u8 n_sym; + u8 pe_idx; + u8 pre_fec_factor; + u8 n_usr; + bool mumimo_ltf_mode_en; + bool ndp; + u8 pri_exp_rssi_dbm; + u8 dbw_idx; + + u8 rsvd; + + u16 rxtime; +}; + +struct bb_physts_user_info_ie_17 { + u8 u_id; + u8 ru_alloc; + u8 n_sts_ru_tot; + + u8 rsvd1; + + u8 strt_sts; + u8 n_sts; + bool fec_type; + u8 mcs; + + u8 rsvd2; + + bool dcm_en; + + u8 rsvd3; +}; + +struct bb_physts_rslt_17_info { + u8 *ie_17_addr; + u8 n_user; + struct bb_physts_cmn_info_ie_17 bb_physts_cmn_info; + struct bb_physts_user_info_ie_17 bb_physts_uer_info[MU_USER_MAX]; +}; + +struct bb_physts_rslt_18_info { + u8 *ie_18_addr; + u16 rx_time; + u8 ch_len_lgcy_seg0; + u8 bw_det_seg0; + u8 snr_idx_lgcy_seg0; + u8 pdp_idx_lgcy_seg0; + u16 pfd_flow; + u8 ch_len_lgcy_seg1; + u8 bw_det_seg1; + u8 snr_idx_lgcy_seg1; + u8 pdp_idx_lgcy_seg1; + bool is_seg1_exist; +}; + +struct bb_physts_rslt_19_info { + u8 *ie_19_addr; + u8 ppdu_inpwrdbm_p20; + u8 ppdu_inpwrdbm_s20; + u8 ppdu_inpwrdbm_s40; + u8 ppdu_inpwrdbm_s80; + u8 ppdu_inpwrdbm_per20_1; + u8 ppdu_inpwrdbm_per20_2; + u8 ppdu_inpwrdbm_per20_3; + u8 ppdu_inpwrdbm_per20_4; + u8 edcca_rpt_cnt_p20; + u8 edcca_rpt_p20_max; + u8 edcca_rpt_p20_min; + u8 edcca_total_smp_cnt; + u8 edcca_rpt_cnt_s80; + u8 edcca_rpt_cnt_s80_max; + u8 edcca_rpt_cnt_s80_min; + u8 pop_reg_pwr; + u8 pop_trig_pwr; + u8 early_drop_pwr; + bool tx_over_flow; +}; + +struct bb_physts_user_info_20 { + u8 ch_smo_n_block_lgcy_sub_0_seg_0; + u8 ch_smo_n_block_lgcy_sub_1_seg_0; + u8 ch_smo_n_block_lgcy_sub_2_seg_0; + u8 ch_smo_n_block_lgcy_sub_3_seg_0; + + u8 ch_smo_en_lgcy_seg_0; + u8 ch_smo_en_non_lgcy_seg_0; + + u8 ch_smo_n_block_non_lgcy_seg_0; + + u8 ch_len_non_lgcy_sts_0_seg_0; + u8 ch_len_non_lgcy_sts_1_seg_0; + u8 ch_len_non_lgcy_sts_2_seg_0; + u8 ch_len_non_lgcy_sts_3_seg_0; + + u8 snr_idx_non_lgy_sts_0_seg_0; + u8 snr_idx_non_lgy_sts_1_seg_0; + u8 snr_idx_non_lgy_sts_2_seg_0; + u8 snr_idx_non_lgy_sts_3_seg_0; + u8 pdp_idx_non_lgcy_sts_0_seg_0; + u8 pdp_idx_non_lgcy_sts_1_seg_0; + u8 pdp_idx_non_lgcy_sts_2_seg_0; + u8 pdp_idx_non_lgcy_sts_3_seg_0; + + u8 snr_non_lgy_sts_0_seg_0; + u8 snr_non_lgy_sts_1_seg_0; + u8 snr_non_lgy_sts_2_seg_0; + u8 snr_non_lgy_sts_3_seg_0; + u8 evm_ss_0_seg_0; + u8 evm_ss_1_seg_0; + u8 evm_ss_2_seg_0; + u8 evm_ss_3_seg_0; +}; + + +struct bb_physts_rslt_20_info { + u8 *ie_20_addr; + u8 n_user; + struct bb_physts_user_info_20 bb_physts_usr_info[MU_USER_MAX]; +}; + +struct bb_physts_user_info_21 { + u8 ch_smo_n_block_lgcy_sub_0_seg_1; + u8 ch_smo_n_block_lgcy_sub_1_seg_1; + u8 ch_smo_n_block_lgcy_sub_2_seg_1; + u8 ch_smo_n_block_lgcy_sub_3_seg_1; + + u8 ch_smo_en_lgcy_seg_1; + u8 ch_smo_en_non_lgcy_seg_1; + + u8 ch_smo_n_block_non_lgcy_seg_1; + + u8 ch_len_non_lgcy_sts_0_seg_1; + u8 ch_len_non_lgcy_sts_1_seg_1; + u8 ch_len_non_lgcy_sts_2_seg_1; + u8 ch_len_non_lgcy_sts_3_seg_1; + + u8 snr_idx_non_lgy_sts_0_seg_1; + u8 snr_idx_non_lgy_sts_1_seg_1; + u8 snr_idx_non_lgy_sts_2_seg_1; + u8 snr_idx_non_lgy_sts_3_seg_1; + u8 pdp_idx_non_lgcy_sts_0_seg_1; + u8 pdp_idx_non_lgcy_sts_1_seg_1; + u8 pdp_idx_non_lgcy_sts_2_seg_1; + u8 pdp_idx_non_lgcy_sts_3_seg_1; + + u8 snr_non_lgy_sts_0_seg_1; + u8 snr_non_lgy_sts_1_seg_1; + u8 snr_non_lgy_sts_2_seg_1; + u8 snr_non_lgy_sts_3_seg_1; + u8 evm_ss_0_seg_1; + u8 evm_ss_1_seg_1; + u8 evm_ss_2_seg_1; + u8 evm_ss_3_seg_1; +}; + +struct bb_physts_rslt_21_info { + u8 *ie_21_addr; + u8 n_user; + struct bb_physts_user_info_21 bb_physts_usr_info[MU_USER_MAX]; +}; + +struct bb_physts_rslt_22_info { + u8 *ie_22_addr; + u8 tmp; +}; + +struct bb_physts_rslt_23_info { + u8 *ie_23_addr; + u8 tmp; +}; + +struct bb_physts_rslt_24_info { + u8 *ie_24_addr; + u8 pre_agc_step_a; + u8 l_fine_agc_step_a; + u8 ht_fine_agc_step_a; + u8 pre_gain_code_a; + u8 l_fine_gain_code_a; + u8 ht_fine_gain_code_a; + u8 l_dagc_a; + u8 ht_dagc_a; + u8 pre_ibpwrdbm_a; + u8 pre_wbpwrdbm_a; + u8 l_ibpwrdbm_a; + u8 l_wbpwrdbm_a; + u8 ht_ibpwrdbm_a; + u8 ht_wbpwrdbm_a; + u8 l_dig_ibpwrdbm_a; + u8 ht_dig_ibpwrdbm_a; + u8 lna_inpwrdbm_a; + u8 aci2sig_db; + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + bool aci_indicator_a; + bool tia_shrink_indicator_a; + bool pre_gain_code_tia_a; + bool l_fine_gain_code_tia_a; + bool ht_fine_gain_code_tia_a; + bool aci_det; +}; + +struct bb_physts_rslt_25_info { + u8 *ie_25_addr; + u8 pre_agc_step_b; + u8 l_fine_agc_step_b; + u8 ht_fine_agc_step_b; + u8 pre_gain_code_b; + u8 l_fine_gain_code_b; + u8 ht_fine_gain_code_b; + u8 l_dagc_b; + u8 ht_dagc_b; + u8 pre_ibpwrdbm_b; + u8 pre_wbpwrdbm_b; + u8 l_ibpwrdbm_b; + u8 l_wbpwrdbm_b; + u8 ht_ibpwrdbm_b; + u8 ht_wbpwrdbm_b; + u8 l_dig_ibpwrdbm_b; + u8 ht_dig_ibpwrdbm_b; + u8 lna_inpwrdbm_b; + u8 aci2sig_db; + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + bool aci_indicator_b; + bool tia_shrink_indicator_b; + bool pre_gain_code_tia_b; + bool l_fine_gain_code_tia_b; + bool ht_fine_gain_code_tia_b; + bool aci_det; +}; + +struct bb_physts_rslt_26_info { + u8 *ie_26_addr; + u8 tmp; +}; + +struct bb_physts_rslt_27_info { + u8 *ie_27_addr; + u8 tmp; +}; + +struct bb_physts_rslt_28_info { + u8 *ie_28_addr; + u16 ant_weight_a; + u8 h3_real_a; + u8 h3_imag_a; + u8 h4_real_a; + u8 h4_imag_a; + u8 h5_real_a; + u8 h5_imag_a; + u8 h6_real_a; + u8 h6_imag_a; + u8 h7_real_a; + u8 h7_imag_a; + u8 h8_real_a; + u8 h8_imag_a; + u8 h9_real_a; + u8 h9_imag_a; + u8 h10_real_a; + u8 h10_imag_a; + u8 h11_real_a; + u8 h11_imag_a; + u8 h12_real_a; + u8 h12_imag_a; + u8 h13_real_a; + u8 h13_imag_a; + u8 h14_real_a; + u8 h14_imag_a; + u8 h15_real_a; + u8 h15_imag_a; + u8 h16_real_a; + u8 h16_imag_a; + u8 h17_real_a; + u8 h17_imag_a; +}; + +struct bb_physts_rslt_29_info { + u8 *ie_29_addr; + u16 ant_weight_b; + u8 h3_real_b; + u8 h3_imag_b; + u8 h4_real_b; + u8 h4_imag_b; + u8 h5_real_b; + u8 h5_imag_b; + u8 h6_real_b; + u8 h6_imag_b; + u8 h7_real_b; + u8 h7_imag_b; + u8 h8_real_b; + u8 h8_imag_b; + u8 h9_real_b; + u8 h9_imag_b; + u8 h10_real_b; + u8 h10_imag_b; + u8 h11_real_b; + u8 h11_imag_b; + u8 h12_real_b; + u8 h12_imag_b; + u8 h13_real_b; + u8 h13_imag_b; + u8 h14_real_b; + u8 h14_imag_b; + u8 h15_real_b; + u8 h15_imag_b; + u8 h16_real_b; + u8 h16_imag_b; + u8 h17_real_b; + u8 h17_imag_b; +}; + +struct bb_physts_rslt_30_info { + u8 *ie_30_addr; + u8 tmp; +}; + +struct bb_physts_rslt_31_info { + u8 *ie_31_addr; + u8 tmp; +}; + +struct bb_physts_cnt_info { + u16 all_cnt; + u16 is_2_self_cnt; + u16 err_ie_cnt; + u16 ok_ie_cnt; + u16 err_len_cnt; +}; + +struct bb_physts_cr_info { + u32 bitmap_search_fail; + //u32 bitmap_search_fail_m; + u32 plcp_hist; + u32 plcp_hist_m; + u32 period_cnt_en; +}; + +struct bb_physts_info { + u32 physts_bitmap_recv; + u32 bitmap_type[PHYSTS_BITMAP_NUM]; + u8 rx_path_en; + bool print_more_info; + u8 physts_dump_mode; /*0: disable, 1:raw data, 2: msg mode, 3:raw data + msg mode*/ + u16 physts_dump_idx; + bool is_valid; // used for UI parsing + bool show_phy_sts_all_pkt; + u16 show_phy_sts_cnt; + u16 show_phy_sts_max_cnt; + // long term cfo rslt + s32 l_ltf_cfo_i; + s32 l_ltf_cfo_q; + u16 ie_len_curr[IE_PHYSTS_LEN_ALL]; + struct bb_rate_info bb_rate_i; + struct bb_rate_info bb_rate_mu_i; + struct bb_physts_cr_info bb_physts_cr_i; + struct bb_physts_cnt_info bb_physts_cnt_i; + struct bb_physts_rslt_hdr_info bb_physts_rslt_hdr_i; + struct bb_physts_rslt_0_info bb_physts_rslt_0_i; + struct bb_physts_rslt_1_info bb_physts_rslt_1_i; + struct bb_physts_rslt_2_info bb_physts_rslt_2_i; + struct bb_physts_rslt_3_info bb_physts_rslt_3_i; + struct bb_physts_rslt_4_to_7_info bb_physts_rslt_4_i; + struct bb_physts_rslt_4_to_7_info bb_physts_rslt_5_i; + struct bb_physts_rslt_4_to_7_info bb_physts_rslt_6_i; + struct bb_physts_rslt_4_to_7_info bb_physts_rslt_7_i; + struct bb_physts_rslt_8_info bb_physts_rslt_8_i; + struct bb_physts_rslt_9_info bb_physts_rslt_9_i; + struct bb_physts_rslt_10_info bb_physts_rslt_10_i; + struct bb_physts_rslt_11_info bb_physts_rslt_11_i; + struct bb_physts_rslt_12_info bb_physts_rslt_12_i; + struct bb_physts_rslt_13_info bb_physts_rslt_13_i; + struct bb_physts_rslt_14_info bb_physts_rslt_14_i; + struct bb_physts_rslt_15_info bb_physts_rslt_15_i; + struct bb_physts_rslt_16_info bb_physts_rslt_16_i; + struct bb_physts_rslt_17_info bb_physts_rslt_17_i; + struct bb_physts_rslt_18_info bb_physts_rslt_18_i; + struct bb_physts_rslt_19_info bb_physts_rslt_19_i; + struct bb_physts_rslt_20_info bb_physts_rslt_20_i; + struct bb_physts_rslt_21_info bb_physts_rslt_21_i; + struct bb_physts_rslt_22_info bb_physts_rslt_22_i; + struct bb_physts_rslt_23_info bb_physts_rslt_23_i; + struct bb_physts_rslt_24_info bb_physts_rslt_24_i; + struct bb_physts_rslt_25_info bb_physts_rslt_25_i; + struct bb_physts_rslt_26_info bb_physts_rslt_26_i; + struct bb_physts_rslt_27_info bb_physts_rslt_27_i; + struct bb_physts_rslt_28_info bb_physts_rslt_28_i; + struct bb_physts_rslt_29_info bb_physts_rslt_29_i; + struct bb_physts_rslt_30_info bb_physts_rslt_30_i; + struct bb_physts_rslt_31_info bb_physts_rslt_31_i; +}; + +void halbb_physts_ie_bitmap_set(struct bb_info *bb, u32 ie_page, u32 bitmap); +u32 halbb_physts_ie_bitmap_get(struct bb_info *bb, u32 ie_page); +void halbb_physts_ie_bitmap_en(struct bb_info *bb, enum bb_physts_bitmap_t type, + enum bb_physts_ie_t ie, bool en); +void halbb_phy_sts_manual_trig(struct bb_info *bb, enum bb_mode_type mode, u8 ss); +void halbb_physts_watchdog(struct bb_info *bb); +void halbb_physts_parsing_init(struct bb_info *bb); + +void halbb_physts_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cr_cfg_physts_init(struct bb_info *bb); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_physts_ex.h b/phl/hal_g6/phy/bb/halbb_physts_ex.h new file mode 100644 index 0000000..d197842 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_physts_ex.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALBB_PHYSTS_EX_H__ +#define __HALBB_PHYSTS_EX_H__ + +enum bb_physts_bitmap_t { + TD_SEARCH_FAIL = 0, + BRK_BY_TX_PKT = 1, + CCA_SPOOF = 2, + OFDM_BRK = 3, + CCK_BRK = 4, + DL_MU_SPOOFING = 5, + HE_MU = 6, + VHT_MU = 7, + UL_TB_SPOOFING = 8, + RSVD_9 = 9, + TRIG_BASE_PPDU = 10, + CCK_PKT = 11, + LEGACY_OFDM_PKT = 12, + HT_PKT = 13, + VHT_PKT = 14, + HE_PKT = 15, + PHYSTS_BITMAP_NUM +}; + +struct physts_rxd_user { + u8 macid; + u8 is_data: 1; + u8 is_ctrl:1; + u8 is_mgnt:1; + u8 is_bcn:1; + u8 rsvd_0:4; +}; + +struct physts_rxd { + u8 is_su:1; + u8 user_num:2; + u8 is_to_self:1; + u8 gi_ltf:4; + u16 data_rate; + u8 macid_su; + //u8 ppdu_cnt; + enum phl_phy_idx phy_idx; + struct physts_rxd_user user_i[4]; +}; + +struct physts_result { + bool physts_rpt_valid; /* @if physts_rpt_valid is false, please ignore the parsing result in this structure*/ + u8 rssi_avg; + u8 rssi[4]; /* u(8,1) RSSI in 0~100 index */ + enum bb_physts_bitmap_t ie_map_type; + u8 ch_idx; /* channel number---*/ + enum channel_width rx_bw; + u8 rxsc; /* sub-channel---*/ + u8 is_mu_pkt; /* is MU packet or not---bool*/ + u8 is_bf; /* BF packet---bool*/ + u8 snr_fd_avg; /* fd, u(8,0), OFDM, fd_snr_avg(phy-sts), limited by FD DFIR output wordlength*/ + u8 snr_fd[4]; /* fd, u(8,0), OFDM, fd_snr_avg(phy-sts) + td_rssi_diff[i]*/ + u8 snr_td_avg; /* td, u(8,0), OFDM + CCK, td_rssi_avg(phy-sts) - MA(rx_idle_pwer)*/ + u8 snr_td[4]; /* td, u(8,0), OFDM + CCK, td_rssi[i](phy-sts) - MA(rx_idle_pwer), limited by DIG in 52A B-cut*/ + u8 is_su ; + u8 is_ldpc; + u8 is_stbc; +}; + +struct bb_info; + +bool halbb_physts_parsing(struct bb_info *bb, + u8 *addr, + u16 physts_total_length, + struct physts_rxd *desc, + struct physts_result *bb_rpt); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_physts_ie_b_endian.h b/phl/hal_g6/phy/bb/halbb_physts_ie_b_endian.h new file mode 100644 index 0000000..b09ad1b --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_physts_ie_b_endian.h @@ -0,0 +1,1191 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PHYSTS_IE_B_ENDIAN_H__ +#define __HALBB_PHYSTS_IE_B_ENDIAN_H__ + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + +struct physts_hdr_info { + u8 is_valid:1; /*valid: total content length <= 1024 bytes*/ + u8 null_tb_ppdu:1; + u8 rsvd_0:1; + u8 ie_bitmap_select: 5; + u8 physts_total_length; /*total length(unit: 8byte)*/ + u8 rsvd_1; + u8 rssi_avg_td; /*U(8,1) RSSI=dBm+110¡Aex:-30dBm->RSSI:80%*/ + u8 rssi_td[4]; +}; + +enum bb_physts_hdr_t { + HDR_TYPE1 = 1, /*5bit fix length*/ + HDR_TYPE2 = 2 /*12bit variable length*/ +}; + +struct physts_ie_0_info { + /*[DW0]*/ + u8 rpl_l:1; + u8 pop_idx:2; + u8 ie_hdr:5; + + u8 rpl_m; + u8 cca_time; + u8 cck_hw_antsw_occur_c:1; + u8 cck_hw_antsw_occur_b:1; + u8 cck_hw_antsw_occur_a:1; + u8 antwgt_gain_diff:5; + /*[DW1]*/ + u8 avg_idle_noise_pwr; + u8 avg_cfo_l; + u8 coarse_cfo_l:4; + u8 avg_cfo_m:4; + u8 coarse_cfo_m; + /*[DW2]*/ + u8 rxevm_hdr; + u8 rxevm_pld; + u8 sig_len_l; + u8 sig_len_m; + /*[DW3]*/ + u8 cck_hw_antsw_occur_d:1; + u8 rsvd_1_dummy_1bit:1; + u8 sync_mode:1; + u8 preamble_type:1; + u8 antdiv_rslt_d:1; + u8 antdiv_rslt_c:1; + u8 antdiv_rslt_b:1 ; + u8 antdiv_rslt_a:1; + + u8 dagc_b_l:3; + u8 dagc_a:5; + + u8 dagc_d_l:1; + u8 dagc_c:5; + u8 dagc_b_m:2; + + u8 rx_path_en_bitmap:4; + u8 dagc_d_m:4; +}; + +struct physts_ie_1_info { + /*[DW0]*/ + u8 rsvd_0_dummy_1bit:1; + u8 pop_idx:2; + u8 ie_hdr:5; + u8 rssi_avg_fd; + u8 ch_idx_seg0; + u8 rx_path_en_bitmap:4; + u8 rxsc:4; + /*[DW1]*/ + u8 avg_idle_noise_pwr; + u8 avg_cfo_seg0_l; + + u8 avg_cfo_premb_seg0_l:4; + u8 avg_cfo_seg0_m:4; + + u8 avg_cfo_premb_seg0_m; + /*[DW2]*/ + u8 ant_idx_b:1; + u8 ant_idx_a:1; + u8 avg_snr:6; + u8 evm_max; + u8 evm_min; + u8 grant_bt:1; + u8 is_stbc:1; + u8 is_ndp:1; + u8 is_ldpc:1; + u8 is_su:1; + u8 pdp_he_ltf_and_gi_type:3; + /*[DW3]*/ + u8 is_awgn:1; + u8 bf_gain_max:7; + u8 avg_cn_seg0:7; + u8 is_bf:1; + u8 sigval_below_th_tone_cnt_seg0; + u8 cn_excess_th_tone_cnt_seg0; + /*[DW4]*/ + u8 pwr_to_cca_l; + u8 pwr_to_cca_m; + u8 cca_to_agc; + u8 cca_to_sbd; + /*[DW5]*/ + u8 edcca_rpt_cnt:7; + u8 rsvd_1_dummy_1bit:1; + u8 edcca_rpt_curr_bw_max_l:1; + u8 edcca_total_smp_cnt:7; + u8 edcca_rpt_curr_bw_min_l:2; + u8 edcca_rpt_curr_bw_max_m:6; + u8 bw_idx:3; /*0~6: 5, 10, 20, 40, 80, 160, 80_80*/ + u8 edcca_rpt_curr_bw_min_m:5; +}; + +struct physts_ie_2_info { + /*[DW0]*/ + u8 max_nsts:3; + u8 ie_hdr:5; + + u8 c_cfo_i_l:2; + u8 is_mu_mimo:1; + u8 gi:2; + u8 ltf_type:2 ; + u8 midamble:1; + + u8 c_cfo_i_m2; + u8 c_cfo_i_m1; + /*[DW1]*/ + u8 rx_info_1; + + u8 c_cfo_q_l:2; + u8 is_dl_ofdma:1; + u8 rx_state_feq:5; + + u8 c_cfo_q_m2; + u8 c_cfo_q_m1; + /*[DW2]*/ + u8 est_cmped_phase; + + u8 f_cfo_i_l:2; + u8 rsvd_0_dummy_1bit:1; + u8 pkt_extension:3; + u8 is_doppler:1; + u8 is_dcm:1; + + u8 f_cfo_i_m2; + u8 f_cfo_i_m1; + /*[DW3]*/ + u8 n_sym_l:5; + u8 n_ltf:3; + + u8 f_cfo_q_l:2; + u8 n_sym_m:6; + + u8 f_cfo_q_m2; + u8 f_cfo_q_m1; +}; + +struct physts_ie_3_info { + /*[DW0]*/ + u8 rsvd_0_dummy_3bit:3; + u8 ie_hdr:5; + + u8 rsvd_1_dummy_1bit:1; + u8 avg_cn_seg1:7; + + u8 sigval_below_th_tone_cnt_seg1; + u8 cn_excess_th_tone_cnt_seg1; + + /*[DW1]*/ + u8 avg_cfo_seg1_l; + + u8 rsvd_2_dummy_4bit:4; + u8 avg_cfo_seg1_m:4; + + u8 avg_cfo_premb_seg1_l; + + u8 rsvd_3_dummy_4bit:4; + u8 avg_cfo_premb_seg1_m:4; + + /*[DW2]*/ + u8 est_cmped_phase_seg1; + + u8 c_cfo_i_seg1_l:2; + u8 avg_snr_seg1:6; + + u8 c_cfo_i_seg1_m2; + u8 c_cfo_i_seg1_m1; + + u8 c_cfo_q_seg1_l2; + u8 c_cfo_q_seg1_l1; + + u8 f_cfo_i_seg1_l:6; + u8 c_cfo_q_seg1_m:2; + + u8 f_cfo_i_seg1_lm; + + u8 f_cfo_q_seg1_l:4; + u8 f_cfo_i_seg1_m:4; + + u8 f_cfo_q_seg1_lm; + + u8 rsvd_5_dummy_10bit_l:2; + u8 f_cfo_q_seg1_m:6; + + u8 rsvd_5_dummy_10bit_m; + u8 ch_idx_seg1; + u8 evm_max_seg1; + u8 evm_min_seg1; + u8 rsvd_6_dummy_8bit; +}; + +struct physts_ie_4_to_7_info { + /*[DW0]*/ + u8 ant_idx:3; + u8 ie_hdr:5; + + u8 sig_val_y; + u8 rf_gain_idx; + + u8 snr_lgy:6; + u8 tia_shrink_indicator:1; + u8 rf_tia_gain_idx:1; + + /*[DW0]*/ + u8 evm_ss_y; + + u8 ant_idx_msb:1; + u8 td_ant_weight:7; + + u8 dc_est_re; + u8 dc_est_im; +}; + +struct physts_ie_type2_len_info { + u8 ie_length_l:3; + u8 ie_bitmap_select: 5; + + u8 rsvd_0:4; + u8 ie_length_m:4; +}; + +struct physts_ie_8_ch_info { + /*[DW0]*/ + u8 ie_hdr_l; + + u8 rxsc:4; + u8 ie_hdr_m:4; + + u8 ch_info_len_l:2; + u8 n_sts:3; + u8 n_rx:3; + + u8 ch_info_len_m; + /*[DW1]*/ + u8 evm_1_sts; + u8 evm_2_sts; + u8 avg_idle_noise_pwr; + + u8 rsvd_0_dummy_7bit:7; + u8 is_ch_info_len_valid:1; + + u8 rsvd1_0_dummy_8bit; + u8 rsvd1_1_dummy_8bit; + u8 rsvd1_2_dummy_8bit; + u8 rsvd1_3_dummy_8bit; + u8 rsvd1_4_dummy_8bit; + u8 rsvd1_5_dummy_8bit; + u8 rsvd1_6_dummy_8bit; + u8 rsvd1_7_dummy_8bit; + + u8 rsvd2_0_dummy_8bit; + u8 rsvd2_1_dummy_8bit; + u8 rsvd2_2_dummy_8bit; + u8 rsvd2_3_dummy_8bit; + u8 rsvd2_4_dummy_8bit; + u8 rsvd2_5_dummy_8bit; + u8 rsvd2_6_dummy_8bit; + u8 rsvd2_7_dummy_8bit; +}; + +struct physts_ie_8_ch_raw_info { + u8 *channel_info_raw; +}; + +struct physts_ie_9_lgcy_info { + /*[DW0]*/ + u8 l_sig_l:3; + u8 ie_hdr:5; + + u8 l_sig_lm; + + u8 rsvd_0_dummy_2bit:2; + u8 l_sig_m:6; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + +}; + +struct physts_ie_9_vht_info { + /*[DW0]*/ + u8 l_sig_l:3; + u8 ie_hdr:5; + + u8 l_sig_lm; + + u8 sig_a1_l:2; + u8 l_sig_m:6; + + u8 sig_a1_lm2; + u8 sig_a1_lm1; + + u8 sig_a2_l:2; + u8 sig_a1_m:6; + + u8 sig_a2_m; + + u8 rsvd_0_dummy_8bit; +}; + +struct physts_ie_9_he_info { + /*[DW0]*/ + u8 l_sig_l:3; + u8 ie_hdr:5; + + u8 l_sig_lm; + + u8 sig_a1_l:2; + u8 l_sig_m:6; + + u8 sig_a1_m3; + u8 sig_a1_m2; + u8 sig_a1_m1; + + u8 sig_a2_l; + u8 sig_a2_m; +}; + +struct physts_ie_10_sigb_info { + u8 *sigb_raw_data_bits_addr; +}; + +struct physts_ie_10_cmn_info { + /*[DW0]*/ + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + u8 rsvd_5_dummy_8bit; + +}; + +struct physts_ie_11_pkt_info { + /*[DW0]*/ + u8 l_length_l:3; + u8 l_rate:3; + u8 pkt_format:2; + + u8 l_length_lm; + + u8 info_type_0:7; + u8 l_length_m:1; + + u8 info_type_1; + u8 info_type_2; + u8 info_type_3; + + u8 time_stamp_l:5; + u8 info_type_4:3; + + u8 state:2; + u8 time_stamp_m:6; +}; + +struct physts_ie_11_info { + /*[DW0]*/ + u8 l_sig_l:3; + u8 ie_hdr:5; + + u8 l_sig_lm; + + u8 sig_a1_l:2; + u8 l_sig_m:6; + + u8 sig_a1_m3; + u8 sig_a1_m2; + u8 sig_a1_m1; + + u8 sig_a2_l; + u8 sig_a2_m; + + u8 time_stamp_l; + + u8 tx_pkt_info_idx_l:1; + u8 rx_pkt_info_idx:4; + u8 time_stamp_m:3; + + u8 rsvd_0_dummy_5bit:5; + u8 tx_pkt_info_idx_m:3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + + struct physts_ie_11_pkt_info pkt_info_rx_i[10]; + struct physts_ie_11_pkt_info pkt_info_tx_i[10]; +}; + +struct physts_ie_12_user_info { + u8 sig_val_ss0_seg_cr_user_i; + u8 sig_val_ss1_seg_cr_user_i; + u8 sig_val_ss2_seg_cr_user_i; + u8 sig_val_ss3_seg_cr_user_i; + u8 sig_bad_tone_cnt_seg_cr_user_i; + u8 cn_bad_tone_cnt_seg_cr_user_i; +}; + +struct physts_ie_12_cmn_info { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; +}; + +struct physts_ie_13_user_info { + u8 is_bf:1; + u8 fec_type:1; + u8 mcs:6; + + u8 pilot_exist:2; + u8 n_sts:3; + u8 n_sts_ru_total:3; + + u8 is_awgn:1; + u8 is_mu_mimo:1; + u8 pdp_he_ltf_and_gi_type:3; + u8 start_sts:3; + + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + u8 snr; + u8 ru_alloc; + + u8 is_dcm:1; + u8 avg_cn_seg_cr:7; + + u8 sta_id_l; + + u8 rsvd_0_dummy_5bit:5; + u8 sta_id_m:3; +}; + +struct physts_ie_13_cmn_info_p1 { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; + u8 rsvd_1_dummy_8bit; +}; + +struct physts_ie_13_cmn_info_p2 { + u8 n_not_sup_sta; + + u8 not_support_sta_id0_l; + + u8 rsvd_0_dummy_5bit:5; + u8 not_support_sta_id0_m:3; + + u8 not_support_sta_id1_l; + + u8 rsvd_1_dummy_5bit:5; + u8 not_support_sta_id1_m:3; + + u8 not_support_sta_id2_l; + + u8 not_support_sta_id3_l:5; + u8 not_support_sta_id2_m:3; + + u8 rsvd_2_dummy_2bit:2; + u8 not_support_sta_id3_m:6; +}; + +struct physts_ie_14_user_info { + u8 cqi_bitmap_ul_tb; + u8 cqi_raw_len_ul_tb; + u8 *cqi_raw_ul_tb_addr; +}; + +struct physts_ie_14_cmn_info { + u8 ie_hdr_l; + u8 rsvd_0_dummy_3bit:3; + u8 rxinfo_ndp_en:1; + u8 ie_hdr_m:4; + u8 n_user; + u8 rxinfo_ndp_1; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; +}; + +struct physts_ie_15_cmn_info { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; +}; + +struct physts_ie_15_user_info { + /* 64bit cmn_info */ + u8 is_bf:1; + u8 fec_type:1; + u8 mcs:6; + + u8 pilot_exist:2; + u8 n_sts:3; + u8 n_sts_ru_total:3; + + u8 is_awgn:1; + u8 is_mu_mimo:1; + u8 pdp_he_ltf_and_gi_type:3; + u8 start_sts:3; + + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + u8 snr; + u8 ru_alloc; + + u8 is_dcm:1; + u8 avg_cn_seg_cr:7; + + /* others */ + u8 uid; + u8 avg_cfo_seg0_l; + + u8 rsvd_0_dummy_4bit:4; + u8 avg_cfo_seg0_m:4; + + u8 rssi_m_ul_tb_l; + + u8 rsvd_1_dummy_7bit:7; + u8 rssi_m_ul_tb_m:1; +}; + +struct physts_ie_17_cmn_info { + u8 ie_hdr_l; + + u8 n_user_l:4; + u8 ie_hdr_m:4; + + u8 rsvd_0_dummy_4bit:4; + u8 n_user_m:4; + + u8 rsvd_0_dummy_8it; + u8 rsvd_1_dummy_8it; + u8 rsvd_2_dummy_8it; + u8 rsvd_3_dummy_8it; + u8 rsvd_4_dummy_8it; + + /*64bit rx_tb_cmn_ctrl*/ + + u8 ltf_type:2; + u8 gi_type:2; + u8 midamle_mode:1; + u8 doppler_en:1; + u8 ldpc_extra:1; + u8 stbc_en:1; + + u8 n_sym_l:5; + u8 n_ltf:3; + + u8 pe_idx_l:2; + u8 n_sym_m:6; + + u8 n_usr_l:5; + u8 pre_fec_factor:2; + u8 pe_idx_m:1; + + u8 pri_exp_rssi_dbm_l:3; + u8 ndp:1; + u8 mumimo_ltf_mode_en:1; + u8 n_usr_m:3; + + u8 rsvd1:2; + u8 dbw_idx:2; + u8 pri_exp_rssi_dbm_m:4; + + u8 rxtime_l:8; + + u8 rsvd2:2; + u8 rxtime_m:6; +}; + +struct physts_ie_17_user_info { + /*64bit rx_tb_user_ctrl*/ + u8 u_id; + + u8 ru_alloc; + + u8 strt_sts:3; + u8 rsvd1:2; + u8 n_sts_ru_tot:3; + + u8 mcs:4; + u8 fec_type:1; + u8 n_sts:3; + + u8 rsvd3:5; + u8 dcm_en:1; + u8 rsvd2:2; + + u8 rsvd4; + u8 rsvd5; + u8 rsvd6; +}; + +struct physts_ie_18_info { + /*[DW0]*/ + u8 rsvd_0_dummy_2bit:2; + u8 is_seg1_exist:1; + u8 ie_hdr:5; + + u8 rx_time_l; + + u8 rsvd_1_dummy_2bit:2; + u8 rx_time_m:6; + + u8 ch_len_lgcy_seg0; + u8 bw_det_seg0; + + u8 rsvd_2_dummy_2bit:2; + u8 pdp_idx_lgcy_seg0:3; + u8 snr_idx_lgcy_seg0:3; + + u8 pfd_flow_l; + + u8 rsvd_3_dummy_4bit:4; + u8 pfd_flow_m:4; + + u8 ch_len_lgcy_seg1; + u8 bw_det_seg1; + + u8 rsvd_3_dummy_2bit:2; + u8 pdp_idx_lgcy_seg1:3; + u8 snr_idx_lgcy_seg1:3; + + u8 rsvd_3_dummy_8bit; + + u8 zero_padding_l2; + u8 zero_padding_l1; + u8 zero_padding_m2; + u8 zero_padding_m1; +}; + +struct physts_ie_19_info { + /*[DW0]*/ + u8 tx_over_flow:1; + u8 rsvd_0_dummy_2bit:2; + u8 ie_hdr:5; + + u8 ppdu_inpwrdbm_p20; + u8 ppdu_inpwrdbm_s20; + u8 ppdu_inpwrdbm_s40; + u8 ppdu_inpwrdbm_s80; + u8 ppdu_inpwrdbm_per20_1; + u8 ppdu_inpwrdbm_per20_2; + u8 ppdu_inpwrdbm_per20_3; + u8 ppdu_inpwrdbm_per20_4; + u8 edcca_rpt_cnt_p20; + u8 edcca_rpt_p20_max; + u8 edcca_rpt_p20_min; + u8 edcca_total_smp_cnt; + u8 edcca_rpt_cnt_s80; + u8 edcca_rpt_cnt_s80_max; + u8 edcca_rpt_cnt_s80_min; + u8 rsvd_1_dummy_8bit; + u8 pop_reg_pwr; + u8 pop_trig_pwr; + u8 early_drop_pwr; + + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + u8 rsvd_5_dummy_8bit; +}; + +struct physts_ie_20_user_info { + u8 ch_smo_n_block_lgcy_sub_3_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_2_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_1_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_0_seg_0:2; + + u8 ch_smo_en_non_lgcy_seg_0:4; + u8 ch_smo_en_lgcy_seg_0:4; + + u8 rsvd_0_dummy_5bit:5; + u8 ch_smo_n_block_non_lgcy_seg_0:3; + + u8 ch_len_non_lgcy_sts_0_seg_0; + u8 ch_len_non_lgcy_sts_1_seg_0; + u8 ch_len_non_lgcy_sts_2_seg_0; + u8 ch_len_non_lgcy_sts_3_seg_0; + + u8 snr_idx_non_lgy_sts_2_seg_0_l:2; + u8 snr_idx_non_lgy_sts_1_seg_0:3; + u8 snr_idx_non_lgy_sts_0_seg_0:3; + + u8 pdp_idx_non_lgcy_sts_1_seg_0_l:1; + u8 pdp_idx_non_lgcy_sts_0_seg_0:3; + u8 snr_idx_non_lgy_sts_3_seg_0:3; + u8 snr_idx_non_lgy_sts_2_seg_0_m:1; + + u8 pdp_idx_non_lgcy_sts_3_seg_0:3; + u8 pdp_idx_non_lgcy_sts_2_seg_0:3; + u8 pdp_idx_non_lgcy_sts_1_seg_0_m:2; + + u8 snr_non_lgy_sts_0_seg_0; + u8 snr_non_lgy_sts_1_seg_0; + u8 snr_non_lgy_sts_2_seg_0; + u8 snr_non_lgy_sts_3_seg_0; + u8 evm_ss_0_seg_0; + u8 evm_ss_1_seg_0; + u8 evm_ss_2_seg_0; + u8 evm_ss_3_seg_0; +}; + +struct physts_ie_20_cmn_info { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; +}; + +struct physts_ie_21_user_info { + u8 ch_smo_n_block_lgcy_sub_3_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_2_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_1_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_0_seg_1:2; + + u8 ch_smo_en_non_lgcy_seg_1:4; + u8 ch_smo_en_lgcy_seg_1:4; + + u8 rsvd_0_dummy_5bit:5; + u8 ch_smo_n_block_non_lgcy_seg_1:3; + + u8 ch_len_non_lgcy_sts_0_seg_1; + u8 ch_len_non_lgcy_sts_1_seg_1; + u8 ch_len_non_lgcy_sts_2_seg_1; + u8 ch_len_non_lgcy_sts_3_seg_1; + + u8 snr_idx_non_lgy_sts_2_seg_1_l:2; + u8 snr_idx_non_lgy_sts_1_seg_1:3; + u8 snr_idx_non_lgy_sts_0_seg_1:3; + + u8 pdp_idx_non_lgcy_sts_1_seg_1_l:1; + u8 pdp_idx_non_lgcy_sts_0_seg_1:3; + u8 snr_idx_non_lgy_sts_3_seg_1:3; + u8 snr_idx_non_lgy_sts_2_seg_1_m:1; + + u8 pdp_idx_non_lgcy_sts_3_seg_1:3; + u8 pdp_idx_non_lgcy_sts_2_seg_1:3; + u8 pdp_idx_non_lgcy_sts_1_seg_1_m:2; + + u8 snr_non_lgy_sts_0_seg_1; + u8 snr_non_lgy_sts_1_seg_1; + u8 snr_non_lgy_sts_2_seg_1; + u8 snr_non_lgy_sts_3_seg_1; + u8 evm_ss_0_seg_1; + u8 evm_ss_1_seg_1; + u8 evm_ss_2_seg_1; + u8 evm_ss_3_seg_1; +}; + +struct physts_ie_21_cmn_info { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; +}; + +struct physts_ie_22_user_info { + u8 pw_norm_lgcy_path0; + u8 pw_norm_lgcy_path1; + u8 pw_norm_lgcy_path2; + u8 pw_norm_lgcy_path3; + u8 ant_wgt_lgcy_path0; + u8 ant_wgt_lgcy_path1; + u8 ant_wgt_lgcy_path2; + u8 ant_wgt_lgcy_path3; +}; + +struct physts_ie_22_cmn_info { + u8 ie_hdr_l; + + u8 rsvd_0_dummy_4bit:4; + u8 ie_hdr_m:4; + + u8 n_user; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + + u8 pw_norm_lgcy_path0; + u8 pw_norm_lgcy_path1; + u8 pw_norm_lgcy_path2; + u8 pw_norm_lgcy_path3; + u8 ant_wgt_lgcy_path0; + u8 ant_wgt_lgcy_path1; + u8 ant_wgt_lgcy_path2; + u8 ant_wgt_lgcy_path3; +}; + +struct physts_ie_24_info { + /*[DW0]*/ + u8 aci_indicator_a:1; + u8 pre_agc_step_a:2; + u8 ie_hdr:5; + + u8 ht_fine_gain_code_tia_a:1; + u8 l_fine_gain_code_tia_a:1; + u8 pre_gain_code_tia_a:1; + u8 tia_shrink_indicator_a:1; + u8 ht_fine_agc_step_a:2; + u8 l_fine_agc_step_a:2; + + u8 pre_gain_code_a; + u8 l_fine_gain_code_a; + u8 ht_fine_gain_code_a; + u8 l_dagc_a; + u8 ht_dagc_a; + u8 pre_ibpwrdbm_a; + u8 pre_wbpwrdbm_a; + u8 l_ibpwrdbm_a; + u8 l_wbpwrdbm_a; + u8 ht_ibpwrdbm_a; + u8 ht_wbpwrdbm_a; + u8 l_dig_ibpwrdbm_a; + u8 ht_dig_ibpwrdbm_a; + u8 lna_inpwrdbm_a; + + u8 aci_det:1; + u8 aci2sig_db:7; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_25_info { + /*[DW0]*/ + u8 aci_indicator_b:1; + u8 pre_agc_step_b:2; + u8 ie_hdr:5; + + u8 ht_fine_gain_code_tia_b:1; + u8 l_fine_gain_code_tia_b:1; + u8 pre_gain_code_tia_b:1; + u8 tia_shrink_indicator_b:1; + u8 ht_fine_agc_step_b:2; + u8 l_fine_agc_step_b:2; + + u8 pre_gain_code_b; + u8 l_fine_gain_code_b; + u8 ht_fine_gain_code_b; + u8 l_dagc_b; + u8 ht_dagc_b; + u8 pre_ibpwrdbm_b; + u8 pre_wbpwrdbm_b; + u8 l_ibpwrdbm_b; + u8 l_wbpwrdbm_b; + u8 ht_ibpwrdbm_b; + u8 ht_wbpwrdbm_b; + u8 l_dig_ibpwrdbm_b; + u8 ht_dig_ibpwrdbm_b; + u8 lna_inpwrdbm_b; + + u8 aci_det:1; + u8 aci2sig_db:7; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_26_info { + /*[DW0]*/ + u8 aci_indicator_c:1; + u8 pre_agc_step_c:2; + u8 ie_hdr:5; + + u8 ht_fine_gain_code_tia_c:1; + u8 l_fine_gain_code_tia_c:1; + u8 pre_gain_code_tia_c:1; + u8 tia_shrink_indicator_c:1; + u8 ht_fine_agc_step_c:2; + u8 l_fine_agc_step_c:2; + + u8 pre_gain_code_c; + u8 l_fine_gain_code_c; + u8 ht_fine_gain_code_c; + u8 l_dagc_c; + u8 ht_dagc_c; + u8 pre_ibpwrdbm_c; + u8 pre_wbpwrdbm_c; + u8 l_ibpwrdbm_c; + u8 l_wbpwrdbm_c; + u8 ht_ibpwrdbm_c; + u8 ht_wbpwrdbm_c; + u8 l_dig_ibpwrdbm_c; + u8 ht_dig_ibpwrdbm_c; + u8 lna_inpwrdbm_c; + + u8 aci_det:1; + u8 aci2sig_db:7; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_27_info { + /*[DW0]*/ + u8 aci_indicator_d:1; + u8 pre_agc_step_d:2; + u8 ie_hdr:5; + + u8 ht_fine_gain_code_tia_d:1; + u8 l_fine_gain_code_tia_d:1; + u8 pre_gain_code_tia_d:1; + u8 tia_shrink_indicator_d:1; + u8 ht_fine_agc_step_d:2; + u8 l_fine_agc_step_d:2; + + u8 pre_gain_code_d; + u8 l_fine_gain_code_d; + u8 ht_fine_gain_code_d; + u8 l_dagc_d; + u8 ht_dagc_d; + u8 pre_ibpwrdbm_d; + u8 pre_wbpwrdbm_d; + u8 l_ibpwrdbm_d; + u8 l_wbpwrdbm_d; + u8 ht_ibpwrdbm_d; + u8 ht_wbpwrdbm_d; + u8 l_dig_ibpwrdbm_d; + u8 ht_dig_ibpwrdbm_d; + u8 lna_inpwrdbm_d; + + u8 aci_det:1; + u8 aci2sig_db:7; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_28_info { + /*[DW0]*/ + u8 ant_weight_a_l:1; + u8 rsvd_0_dummy_2bit:2; + u8 ie_hdr:5; + + u8 ant_weight_a_m; + u8 h3_real_a; + u8 h3_imag_a; + u8 h4_real_a; + u8 h4_imag_a; + u8 h5_real_a; + u8 h5_imag_a; + u8 h6_real_a; + u8 h6_imag_a; + u8 h7_real_a; + u8 h7_imag_a; + u8 h8_real_a; + u8 h8_imag_a; + u8 h9_real_a; + u8 h9_imag_a; + u8 h10_real_a; + u8 h10_imag_a; + u8 h11_real_a; + u8 h11_imag_a; + u8 h12_real_a; + u8 h12_imag_a; + u8 h13_real_a; + u8 h13_imag_a; + u8 h14_real_a; + u8 h14_imag_a; + u8 h15_real_a; + u8 h15_imag_a; + u8 h16_real_a; + u8 h16_imag_a; + u8 h17_real_a; + u8 h17_imag_a; +}; + +struct physts_ie_29_info { + /*[DW0]*/ + u8 ant_weight_b_l:1; + u8 rsvd_0_dummy_2bit:2; + u8 ie_hdr:5; + + u8 ant_weight_b_m; + u8 h3_real_b; + u8 h3_imag_b; + u8 h4_real_b; + u8 h4_imag_b; + u8 h5_real_b; + u8 h5_imag_b; + u8 h6_real_b; + u8 h6_imag_b; + u8 h7_real_b; + u8 h7_imag_b; + u8 h8_real_b; + u8 h8_imag_b; + u8 h9_real_b; + u8 h9_imag_b; + u8 h10_real_b; + u8 h10_imag_b; + u8 h11_real_b; + u8 h11_imag_b; + u8 h12_real_b; + u8 h12_imag_b; + u8 h13_real_b; + u8 h13_imag_b; + u8 h14_real_b; + u8 h14_imag_b; + u8 h15_real_b; + u8 h15_imag_b; + u8 h16_real_b; + u8 h16_imag_b; + u8 h17_real_b; + u8 h17_imag_b; +}; + +struct physts_ie_30_info { + /*[DW0]*/ + u8 ant_weight_c_l:1; + u8 rsvd_0_dummy_2bit:2; + u8 ie_hdr:5; + + u8 ant_weight_c_m; + u8 h3_real_c; + u8 h3_imag_c; + u8 h4_real_c; + u8 h4_imag_c; + u8 h5_real_c; + u8 h5_imag_c; + u8 h6_real_c; + u8 h6_imag_c; + u8 h7_real_c; + u8 h7_imag_c; + u8 h8_real_c; + u8 h8_imag_c; + u8 h9_real_c; + u8 h9_imag_c; + u8 h10_real_c; + u8 h10_imag_c; + u8 h11_real_c; + u8 h11_imag_c; + u8 h12_real_c; + u8 h12_imag_c; + u8 h13_real_c; + u8 h13_imag_c; + u8 h14_real_c; + u8 h14_imag_c; + u8 h15_real_c; + u8 h15_imag_c; + u8 h16_real_c; + u8 h16_imag_c; + u8 h17_real_c; + u8 h17_imag_c; +}; + +struct physts_ie_31_info { + /*[DW0]*/ + u8 ant_weight_d_l:1; + u8 rsvd_0_dummy_2bit:2; + u8 ie_hdr:5; + + u8 ant_weight_d_m; + u8 h3_real_d; + u8 h3_imag_d; + u8 h4_real_d; + u8 h4_imag_d; + u8 h5_real_d; + u8 h5_imag_d; + u8 h6_real_d; + u8 h6_imag_d; + u8 h7_real_d; + u8 h7_imag_d; + u8 h8_real_d; + u8 h8_imag_d; + u8 h9_real_d; + u8 h9_imag_d; + u8 h10_real_d; + u8 h10_imag_d; + u8 h11_real_d; + u8 h11_imag_d; + u8 h12_real_d; + u8 h12_imag_d; + u8 h13_real_d; + u8 h13_imag_d; + u8 h14_real_d; + u8 h14_imag_d; + u8 h15_real_d; + u8 h15_imag_d; + u8 h16_real_d; + u8 h16_imag_d; + u8 h17_real_d; + u8 h17_imag_d; +}; + + /*@--------------------------[Prptotype]-------------------------------------*/ +#endif diff --git a/phl/hal_g6/phy/bb/halbb_physts_ie_l_endian.h b/phl/hal_g6/phy/bb/halbb_physts_ie_l_endian.h new file mode 100644 index 0000000..0f2a050 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_physts_ie_l_endian.h @@ -0,0 +1,1168 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PHYSTS_IE_L_ENDIAN_H__ +#define __HALBB_PHYSTS_IE_L_ENDIAN_H__ + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + +struct physts_hdr_info { + u8 ie_bitmap_select: 5; + u8 rsvd_0:1; + u8 null_tb_ppdu:1; + u8 is_valid:1; /*valid: total content length <= 1024 bytes*/ + u8 physts_total_length; /*total length(unit: 8byte)*/ + u8 rsvd_1; + u8 rssi_avg_td; /*U(8,1) RSSI=dBm+110¡Aex:-30dBm->RSSI:80%*/ + u8 rssi_td[4]; +}; + +enum bb_physts_hdr_t { + HDR_TYPE1 = 1, /*5bit fix length*/ + HDR_TYPE2 = 2 /*12bit variable length*/ +}; + +struct physts_ie_0_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pop_idx:2; + u8 rpl_l:1; + + u8 rpl_m; + u8 cca_time; + u8 antwgt_gain_diff:5; + u8 cck_hw_antsw_occur_a:1; + u8 cck_hw_antsw_occur_b:1; + u8 cck_hw_antsw_occur_c:1; + /*[DW1]*/ + u8 avg_idle_noise_pwr; + u8 avg_cfo_l; + u8 avg_cfo_m:4; + u8 coarse_cfo_l:4; + u8 coarse_cfo_m; + /*[DW2]*/ + u8 rxevm_hdr; + u8 rxevm_pld; + u8 sig_len_l; + u8 sig_len_m; + /*[DW3]*/ + u8 antdiv_rslt_a:1; + u8 antdiv_rslt_b:1 ; + u8 antdiv_rslt_c:1; + u8 antdiv_rslt_d:1; + u8 preamble_type:1; + u8 sync_mode:1; + u8 rsvd_1_dummy_1bit:1; + u8 cck_hw_antsw_occur_d:1; + + u8 dagc_a:5; + u8 dagc_b_l:3; + + u8 dagc_b_m:2; + u8 dagc_c:5; + u8 dagc_d_l:1; + + u8 dagc_d_m:4; + u8 rx_path_en_bitmap:4; +}; + +struct physts_ie_1_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pop_idx:2; + u8 rsvd_0_dummy_1bit:1; + u8 rssi_avg_fd; + u8 ch_idx_seg0; + u8 rxsc:4; + u8 rx_path_en_bitmap:4; + /*[DW1]*/ + u8 avg_idle_noise_pwr; + u8 avg_cfo_seg0_l; + + u8 avg_cfo_seg0_m:4; + u8 avg_cfo_premb_seg0_l:4; + + u8 avg_cfo_premb_seg0_m; + /*[DW2]*/ + u8 avg_snr:6; + u8 ant_idx_a:1; + u8 ant_idx_b:1; + u8 evm_max; + u8 evm_min; + u8 pdp_he_ltf_and_gi_type:3; + u8 is_su:1; + u8 is_ldpc:1; + u8 is_ndp:1; + u8 is_stbc:1; + u8 grant_bt:1; + /*[DW3]*/ + u8 bf_gain_max:7; + u8 is_awgn:1; + u8 is_bf:1; + u8 avg_cn_seg0:7; + u8 sigval_below_th_tone_cnt_seg0; + u8 cn_excess_th_tone_cnt_seg0; + /*[DW4]*/ + u8 pwr_to_cca_l; + u8 pwr_to_cca_m; + u8 cca_to_agc; + u8 cca_to_sbd; + /*[DW5]*/ + u8 rsvd_1_dummy_1bit:1; + u8 edcca_rpt_cnt:7; + u8 edcca_total_smp_cnt:7; + u8 edcca_rpt_curr_bw_max_l:1; + u8 edcca_rpt_curr_bw_max_m:6; + u8 edcca_rpt_curr_bw_min_l:2; + u8 edcca_rpt_curr_bw_min_m:5; + u8 bw_idx:3; /*0~6: 5, 10, 20, 40, 80, 160, 80_80*/ +}; + +struct physts_ie_2_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 max_nsts:3; + + u8 midamble:1; + u8 ltf_type:2 ; + u8 gi:2; + u8 is_mu_mimo:1; + u8 c_cfo_i_l:2; + + u8 c_cfo_i_m2; + u8 c_cfo_i_m1; + /*[DW1]*/ + u8 rx_info_1; + + u8 rx_state_feq:5; + u8 is_dl_ofdma:1; + u8 c_cfo_q_l:2; + + u8 c_cfo_q_m2; + u8 c_cfo_q_m1; + /*[DW2]*/ + u8 est_cmped_phase; + + u8 is_dcm:1; + u8 is_doppler:1; + u8 pkt_extension:3; + u8 rsvd_0_dummy_1bit:1; + u8 f_cfo_i_l:2; + + u8 f_cfo_i_m2; + u8 f_cfo_i_m1; + /*[DW3]*/ + u8 n_ltf:3; + u8 n_sym_l:5; + + u8 n_sym_m:6; + u8 f_cfo_q_l:2; + + u8 f_cfo_q_m2; + u8 f_cfo_q_m1; +}; + +struct physts_ie_3_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_3bit:3; + + u8 avg_cn_seg1:7; + u8 rsvd_1_dummy_1bit:1; + + u8 sigval_below_th_tone_cnt_seg1; + u8 cn_excess_th_tone_cnt_seg1; + + /*[DW1]*/ + u8 avg_cfo_seg1_l; + + u8 avg_cfo_seg1_m:4; + u8 rsvd_2_dummy_4bit:4; + + u8 avg_cfo_premb_seg1_l; + + u8 avg_cfo_premb_seg1_m:4; + u8 rsvd_3_dummy_4bit:4; + + /*[DW2]*/ + u8 est_cmped_phase_seg1; + + u8 avg_snr_seg1:6; + u8 c_cfo_i_seg1_l:2; + + u8 c_cfo_i_seg1_m2; + u8 c_cfo_i_seg1_m1; + + u8 c_cfo_q_seg1_l2; + u8 c_cfo_q_seg1_l1; + + u8 c_cfo_q_seg1_m:2; + u8 f_cfo_i_seg1_l:6; + + u8 f_cfo_i_seg1_lm; + + u8 f_cfo_i_seg1_m:4; + u8 f_cfo_q_seg1_l:4; + + u8 f_cfo_q_seg1_lm; + + u8 f_cfo_q_seg1_m:6; + u8 rsvd_5_dummy_10bit_l:2; + + u8 rsvd_5_dummy_10bit_m; + u8 ch_idx_seg1; + u8 evm_max_seg1; + u8 evm_min_seg1; + u8 rsvd_6_dummy_8bit; +}; + +/*physts_ie_4_to_7_info*/ +struct physts_ie_4_to_7_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 ant_idx:3; + + u8 sig_val_y; + u8 rf_gain_idx; + + u8 rf_tia_gain_idx:1; + u8 tia_shrink_indicator:1; + u8 snr_lgy:6; + + /*[DW0]*/ + u8 evm_ss_y; + + u8 td_ant_weight:7; + u8 ant_idx_msb:1; + + u8 dc_est_re; + u8 dc_est_im; +}; + +struct physts_ie_8_ch_info { + /*[DW0]*/ + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rxsc:4; + + u8 n_rx:3; + u8 n_sts:3; + u8 ch_info_len_l:2; + + u8 ch_info_len_m; + /*[DW1]*/ + u8 evm_1_sts; + u8 evm_2_sts; + u8 avg_idle_noise_pwr; + + u8 is_ch_info_len_valid:1; + u8 rsvd_0_dummy_7bit:7; + u8 rsvd_1[8]; + u8 rsvd_2[8]; +}; + +struct physts_ie_8_ch_raw_info { + u8 *channel_info_raw; +}; + +struct physts_ie_9_lgcy_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 l_sig_l:3; + + u8 l_sig_lm; + + u8 l_sig_m:6; + u8 rsvd_0_dummy_2bit:2; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + +}; + +struct physts_ie_9_vht_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 l_sig_l:3; + + u8 l_sig_lm; + + u8 l_sig_m:6; + u8 sig_a1_l:2; + + u8 sig_a1_lm2; + u8 sig_a1_lm1; + + u8 sig_a1_m:6; + u8 sig_a2_l:2; + + u8 sig_a2_m; + + u8 rsvd_0_dummy_8bit; +}; + +struct physts_ie_9_he_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 l_sig_l:3; + + u8 l_sig_lm; + + u8 l_sig_m:6; + u8 sig_a1_l:2; + + u8 sig_a1_m3; + u8 sig_a1_m2; + u8 sig_a1_m1; + + u8 sig_a2_l; + u8 sig_a2_m; +}; + +struct physts_ie_10_sigb_info { + u8 *sigb_raw_data_bits_addr; +}; + +struct physts_ie_10_cmn_info { + /*[DW0]*/ + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + u8 rsvd_5_dummy_8bit; + +}; + +struct physts_ie_11_pkt_info { + /*[DW0]*/ + u8 pkt_format:2; + u8 l_rate:3; + u8 l_length_l:3; + + u8 l_length_lm; + + u8 l_length_m:1; + u8 info_type_0:7; + + u8 info_type_1; + u8 info_type_2; + u8 info_type_3; + + u8 info_type_4:3; + u8 time_stamp_l:5; + + u8 time_stamp_m:6; + u8 state:2; +}; + +struct physts_ie_11_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 l_sig_l:3; + + u8 l_sig_lm; + + u8 l_sig_m:6; + u8 sig_a1_l:2; + + u8 sig_a1_m3; + u8 sig_a1_m2; + u8 sig_a1_m1; + + u8 sig_a2_l; + u8 sig_a2_m; + + u8 time_stamp_l; + + u8 time_stamp_m:3; + u8 rx_pkt_info_idx:4; + u8 tx_pkt_info_idx_l:1; + + u8 tx_pkt_info_idx_m:3; + u8 rsvd_0_dummy_5bit:5; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + + struct physts_ie_11_pkt_info pkt_info_rx_i[10]; + struct physts_ie_11_pkt_info pkt_info_tx_i[10]; +}; + +struct physts_ie_12_user_info { + u8 sig_val_ss0_seg_cr_user_i; + u8 sig_val_ss1_seg_cr_user_i; + u8 sig_val_ss2_seg_cr_user_i; + u8 sig_val_ss3_seg_cr_user_i; + u8 sig_bad_tone_cnt_seg_cr_user_i; + u8 cn_bad_tone_cnt_seg_cr_user_i; +}; + +struct physts_ie_12_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; +}; + +struct physts_ie_13_user_info { + u8 mcs:6; + u8 fec_type:1; + u8 is_bf:1; + + u8 n_sts_ru_total:3; + u8 n_sts:3; + u8 pilot_exist:2; + + u8 start_sts:3; + u8 pdp_he_ltf_and_gi_type:3; + u8 is_mu_mimo:1; + u8 is_awgn:1; + + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + u8 snr; + u8 ru_alloc; + + u8 avg_cn_seg_cr:7; + u8 is_dcm:1; + + u8 sta_id_l; + + u8 sta_id_m:3; + u8 rsvd_0_dummy_5bit:5; +}; + +struct physts_ie_13_cmn_info_p1 { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; + u8 rsvd_1_dummy_8bit; +}; + +struct physts_ie_13_cmn_info_p2 { + u8 n_not_sup_sta; + + u8 not_support_sta_id0_l; + + u8 not_support_sta_id0_m:3; + u8 rsvd_0_dummy_5bit:5; + + u8 not_support_sta_id1_l; + + u8 not_support_sta_id1_m:3; + u8 rsvd_1_dummy_5bit:5; + + u8 not_support_sta_id2_l; + + u8 not_support_sta_id2_m:3; + u8 not_support_sta_id3_l:5; + + u8 not_support_sta_id3_m:6; + u8 rsvd_2_dummy_2bit:2; +}; + +struct physts_ie_14_user_info { + u8 cqi_bitmap_ul_tb; + u8 cqi_raw_len_ul_tb; + u8 *cqi_raw_ul_tb_addr; +}; + +struct physts_ie_14_cmn_info { + u8 ie_hdr_l; + u8 ie_hdr_m:4; + u8 rxinfo_ndp_en:1; + u8 rsvd_0_dummy_3bit:3; + u8 n_user; + u8 rxinfo_ndp_1; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; +}; + +struct physts_ie_15_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; +}; + +struct physts_ie_15_user_info { + /* 64bit cmn_info */ + u8 mcs:6; + u8 fec_type:1; + u8 is_bf:1; + + u8 n_sts_ru_total:3; + u8 n_sts:3; + u8 pilot_exist:2; + + u8 start_sts:3; + u8 pdp_he_ltf_and_gi_type:3; + u8 is_mu_mimo:1; + u8 is_awgn:1; + + u8 rx_evm_max_seg_cr; + u8 rx_evm_min_seg_cr; + u8 snr; + u8 ru_alloc; + + u8 avg_cn_seg_cr:7; + u8 is_dcm:1; + + /* others */ + u8 uid; + u8 avg_cfo_seg0_l; + + u8 avg_cfo_seg0_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 rssi_m_ul_tb_l; + + u8 rssi_m_ul_tb_m:1; + u8 rsvd_1_dummy_7bit:7; +}; + +struct physts_ie_17_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 n_user_l:4; + + u8 n_user_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 rsvd_0_dummy_8it; + u8 rsvd_1_dummy_8it; + u8 rsvd_2_dummy_8it; + u8 rsvd_3_dummy_8it; + u8 rsvd_4_dummy_8it; + + /*64bit rx_tb_cmn_ctrl*/ + + u8 stbc_en:1; + u8 ldpc_extra:1; + u8 doppler_en:1; + u8 midamle_mode:1; + u8 gi_type:2; + u8 ltf_type:2; + + u8 n_ltf:3; + u8 n_sym_l:5; + + u8 n_sym_m:6; + u8 pe_idx_l:2; + + u8 pe_idx_m:1; + u8 pre_fec_factor:2; + u8 n_usr_l:5; + + u8 n_usr_m:3; + u8 mumimo_ltf_mode_en:1; + u8 ndp:1; + u8 pri_exp_rssi_dbm_l:3; + + u8 pri_exp_rssi_dbm_m:4; + u8 dbw_idx:2; + u8 rsvd1:2; + + u8 rxtime_l:8; + + u8 rxtime_m:6; + u8 rsvd2:2; +}; + +struct physts_ie_17_user_info { + /*64bit rx_tb_user_ctrl*/ + u8 u_id; + + u8 ru_alloc; + + u8 n_sts_ru_tot:3; + u8 rsvd1:2; + u8 strt_sts:3; + + u8 n_sts:3; + u8 fec_type:1; + u8 mcs:4; + + u8 rsvd2:2; + u8 dcm_en:1; + u8 rsvd3:5; + + u8 rsvd4; + u8 rsvd5; + u8 rsvd6; +}; + +struct physts_ie_18_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 is_seg1_exist:1; + u8 rsvd_0_dummy_2bit:2; + + u8 rx_time_l; + + u8 rx_time_m:6; + u8 rsvd_1_dummy_2bit:2; + + u8 ch_len_lgcy_seg0; + u8 bw_det_seg0; + + u8 snr_idx_lgcy_seg0:3; + u8 pdp_idx_lgcy_seg0:3; + u8 rsvd_2_dummy_2bit:2; + + u8 pfd_flow_l; + + u8 pfd_flow_m:4; + u8 rsvd_3_dummy_4bit:4; + + u8 ch_len_lgcy_seg1; + u8 bw_det_seg1; + + u8 snr_idx_lgcy_seg1:3; + u8 pdp_idx_lgcy_seg1:3; + u8 rsvd_3_dummy_2bit:2; + + u8 rsvd_3_dummy_8bit; + + u8 zero_padding_l2; + u8 zero_padding_l1; + u8 zero_padding_m2; + u8 zero_padding_m1; +}; + +struct physts_ie_19_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_2bit:2; + u8 tx_over_flow:1; + + u8 ppdu_inpwrdbm_p20; + u8 ppdu_inpwrdbm_s20; + u8 ppdu_inpwrdbm_s40; + u8 ppdu_inpwrdbm_s80; + u8 ppdu_inpwrdbm_per20_1; + u8 ppdu_inpwrdbm_per20_2; + u8 ppdu_inpwrdbm_per20_3; + u8 ppdu_inpwrdbm_per20_4; + u8 edcca_rpt_cnt_p20; + u8 edcca_rpt_p20_max; + u8 edcca_rpt_p20_min; + u8 edcca_total_smp_cnt; + u8 edcca_rpt_cnt_s80; + u8 edcca_rpt_cnt_s80_max; + u8 edcca_rpt_cnt_s80_min; + u8 rsvd_1_dummy_8bit; + u8 pop_reg_pwr; + u8 pop_trig_pwr; + u8 early_drop_pwr; + + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + u8 rsvd_5_dummy_8bit; +}; + +struct physts_ie_20_user_info { + u8 ch_smo_n_block_lgcy_sub_0_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_1_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_2_seg_0:2; + u8 ch_smo_n_block_lgcy_sub_3_seg_0:2; + + u8 ch_smo_en_lgcy_seg_0:4; + u8 ch_smo_en_non_lgcy_seg_0:4; + + u8 ch_smo_n_block_non_lgcy_seg_0:3; + u8 rsvd_0_dummy_5bit:5; + + u8 ch_len_non_lgcy_sts_0_seg_0; + u8 ch_len_non_lgcy_sts_1_seg_0; + u8 ch_len_non_lgcy_sts_2_seg_0; + u8 ch_len_non_lgcy_sts_3_seg_0; + + u8 snr_idx_non_lgy_sts_0_seg_0:3; + u8 snr_idx_non_lgy_sts_1_seg_0:3; + u8 snr_idx_non_lgy_sts_2_seg_0_l:2; + + u8 snr_idx_non_lgy_sts_2_seg_0_m:1; + u8 snr_idx_non_lgy_sts_3_seg_0:3; + u8 pdp_idx_non_lgcy_sts_0_seg_0:3; + u8 pdp_idx_non_lgcy_sts_1_seg_0_l:1; + + u8 pdp_idx_non_lgcy_sts_1_seg_0_m:2; + u8 pdp_idx_non_lgcy_sts_2_seg_0:3; + u8 pdp_idx_non_lgcy_sts_3_seg_0:3; + + u8 snr_non_lgy_sts_0_seg_0; + u8 snr_non_lgy_sts_1_seg_0; + u8 snr_non_lgy_sts_2_seg_0; + u8 snr_non_lgy_sts_3_seg_0; + u8 evm_ss_0_seg_0; + u8 evm_ss_1_seg_0; + u8 evm_ss_2_seg_0; + u8 evm_ss_3_seg_0; +}; + +struct physts_ie_20_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; +}; + +struct physts_ie_21_user_info { + u8 ch_smo_n_block_lgcy_sub_0_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_1_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_2_seg_1:2; + u8 ch_smo_n_block_lgcy_sub_3_seg_1:2; + + u8 ch_smo_en_lgcy_seg_1:4; + u8 ch_smo_en_non_lgcy_seg_1:4; + + u8 ch_smo_n_block_non_lgcy_seg_1:3; + u8 rsvd_0_dummy_5bit:5; + + u8 ch_len_non_lgcy_sts_0_seg_1; + u8 ch_len_non_lgcy_sts_1_seg_1; + u8 ch_len_non_lgcy_sts_2_seg_1; + u8 ch_len_non_lgcy_sts_3_seg_1; + + u8 snr_idx_non_lgy_sts_0_seg_1:3; + u8 snr_idx_non_lgy_sts_1_seg_1:3; + u8 snr_idx_non_lgy_sts_2_seg_1_l:2; + + u8 snr_idx_non_lgy_sts_2_seg_1_m:1; + u8 snr_idx_non_lgy_sts_3_seg_1:3; + u8 pdp_idx_non_lgcy_sts_0_seg_1:3; + u8 pdp_idx_non_lgcy_sts_1_seg_1_l:1; + + u8 pdp_idx_non_lgcy_sts_1_seg_1_m:2; + u8 pdp_idx_non_lgcy_sts_2_seg_1:3; + u8 pdp_idx_non_lgcy_sts_3_seg_1:3; + + u8 snr_non_lgy_sts_0_seg_1; + u8 snr_non_lgy_sts_1_seg_1; + u8 snr_non_lgy_sts_2_seg_1; + u8 snr_non_lgy_sts_3_seg_1; + u8 evm_ss_0_seg_1; + u8 evm_ss_1_seg_1; + u8 evm_ss_2_seg_1; + u8 evm_ss_3_seg_1; +}; + +struct physts_ie_21_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; +}; + +struct physts_ie_22_user_info { + u8 pw_norm_lgcy_path0; + u8 pw_norm_lgcy_path1; + u8 pw_norm_lgcy_path2; + u8 pw_norm_lgcy_path3; + u8 ant_wgt_lgcy_path0; + u8 ant_wgt_lgcy_path1; + u8 ant_wgt_lgcy_path2; + u8 ant_wgt_lgcy_path3; +}; + +struct physts_ie_22_cmn_info { + u8 ie_hdr_l; + + u8 ie_hdr_m:4; + u8 rsvd_0_dummy_4bit:4; + + u8 n_user; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; + u8 rsvd_3_dummy_8bit; + u8 rsvd_4_dummy_8bit; + + u8 pw_norm_lgcy_path0; + u8 pw_norm_lgcy_path1; + u8 pw_norm_lgcy_path2; + u8 pw_norm_lgcy_path3; + u8 ant_wgt_lgcy_path0; + u8 ant_wgt_lgcy_path1; + u8 ant_wgt_lgcy_path2; + u8 ant_wgt_lgcy_path3; +}; + +struct physts_ie_24_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pre_agc_step_a:2; + u8 aci_indicator_a:1; + + u8 l_fine_agc_step_a:2; + u8 ht_fine_agc_step_a:2; + u8 tia_shrink_indicator_a:1; + u8 pre_gain_code_tia_a:1; + u8 l_fine_gain_code_tia_a:1; + u8 ht_fine_gain_code_tia_a:1; + + u8 pre_gain_code_a; + u8 l_fine_gain_code_a; + u8 ht_fine_gain_code_a; + u8 l_dagc_a; + u8 ht_dagc_a; + u8 pre_ibpwrdbm_a; + u8 pre_wbpwrdbm_a; + u8 l_ibpwrdbm_a; + u8 l_wbpwrdbm_a; + u8 ht_ibpwrdbm_a; + u8 ht_wbpwrdbm_a; + u8 l_dig_ibpwrdbm_a; + u8 ht_dig_ibpwrdbm_a; + u8 lna_inpwrdbm_a; + + u8 aci2sig_db:7; + u8 aci_det:1; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_25_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pre_agc_step_b:2; + u8 aci_indicator_b:1; + + u8 l_fine_agc_step_b:2; + u8 ht_fine_agc_step_b:2; + u8 tia_shrink_indicator_b:1; + u8 pre_gain_code_tia_b:1; + u8 l_fine_gain_code_tia_b:1; + u8 ht_fine_gain_code_tia_b:1; + + u8 pre_gain_code_b; + u8 l_fine_gain_code_b; + u8 ht_fine_gain_code_b; + u8 l_dagc_b; + u8 ht_dagc_b; + u8 pre_ibpwrdbm_b; + u8 pre_wbpwrdbm_b; + u8 l_ibpwrdbm_b; + u8 l_wbpwrdbm_b; + u8 ht_ibpwrdbm_b; + u8 ht_wbpwrdbm_b; + u8 l_dig_ibpwrdbm_b; + u8 ht_dig_ibpwrdbm_b; + u8 lna_inpwrdbm_b; + + u8 aci2sig_db:7; + u8 aci_det:1; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_26_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pre_agc_step_c:2; + u8 aci_indicator_c:1; + + u8 l_fine_agc_step_c:2; + u8 ht_fine_agc_step_c:2; + u8 tia_shrink_indicator_c:1; + u8 pre_gain_code_tia_c:1; + u8 l_fine_gain_code_tia_c:1; + u8 ht_fine_gain_code_tia_c:1; + + u8 pre_gain_code_c; + u8 l_fine_gain_code_c; + u8 ht_fine_gain_code_c; + u8 l_dagc_c; + u8 ht_dagc_c; + u8 pre_ibpwrdbm_c; + u8 pre_wbpwrdbm_c; + u8 l_ibpwrdbm_c; + u8 l_wbpwrdbm_c; + u8 ht_ibpwrdbm_c; + u8 ht_wbpwrdbm_c; + u8 l_dig_ibpwrdbm_c; + u8 ht_dig_ibpwrdbm_c; + u8 lna_inpwrdbm_c; + + u8 aci2sig_db:7; + u8 aci_det:1; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_27_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 pre_agc_step_d:2; + u8 aci_indicator_d:1; + + u8 l_fine_agc_step_d:2; + u8 ht_fine_agc_step_d:2; + u8 tia_shrink_indicator_d:1; + u8 pre_gain_code_tia_d:1; + u8 l_fine_gain_code_tia_d:1; + u8 ht_fine_gain_code_tia_d:1; + + u8 pre_gain_code_d; + u8 l_fine_gain_code_d; + u8 ht_fine_gain_code_d; + u8 l_dagc_d; + u8 ht_dagc_d; + u8 pre_ibpwrdbm_d; + u8 pre_wbpwrdbm_d; + u8 l_ibpwrdbm_d; + u8 l_wbpwrdbm_d; + u8 ht_ibpwrdbm_d; + u8 ht_wbpwrdbm_d; + u8 l_dig_ibpwrdbm_d; + u8 ht_dig_ibpwrdbm_d; + u8 lna_inpwrdbm_d; + + u8 aci2sig_db:7; + u8 aci_det:1; + + u8 sb5m_ratio_0; + u8 sb5m_ratio_1; + u8 sb5m_ratio_2; + u8 sb5m_ratio_3; + + u8 rsvd_0_dummy_8bit; + u8 rsvd_1_dummy_8bit; + u8 rsvd_2_dummy_8bit; +}; + +struct physts_ie_28_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_2bit:2; + u8 ant_weight_a_l:1; + + u8 ant_weight_a_m; + u8 h3_real_a; + u8 h3_imag_a; + u8 h4_real_a; + u8 h4_imag_a; + u8 h5_real_a; + u8 h5_imag_a; + u8 h6_real_a; + u8 h6_imag_a; + u8 h7_real_a; + u8 h7_imag_a; + u8 h8_real_a; + u8 h8_imag_a; + u8 h9_real_a; + u8 h9_imag_a; + u8 h10_real_a; + u8 h10_imag_a; + u8 h11_real_a; + u8 h11_imag_a; + u8 h12_real_a; + u8 h12_imag_a; + u8 h13_real_a; + u8 h13_imag_a; + u8 h14_real_a; + u8 h14_imag_a; + u8 h15_real_a; + u8 h15_imag_a; + u8 h16_real_a; + u8 h16_imag_a; + u8 h17_real_a; + u8 h17_imag_a; +}; + +struct physts_ie_29_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_2bit:2; + u8 ant_weight_b_l:1; + + u8 ant_weight_b_m; + u8 h3_real_b; + u8 h3_imag_b; + u8 h4_real_b; + u8 h4_imag_b; + u8 h5_real_b; + u8 h5_imag_b; + u8 h6_real_b; + u8 h6_imag_b; + u8 h7_real_b; + u8 h7_imag_b; + u8 h8_real_b; + u8 h8_imag_b; + u8 h9_real_b; + u8 h9_imag_b; + u8 h10_real_b; + u8 h10_imag_b; + u8 h11_real_b; + u8 h11_imag_b; + u8 h12_real_b; + u8 h12_imag_b; + u8 h13_real_b; + u8 h13_imag_b; + u8 h14_real_b; + u8 h14_imag_b; + u8 h15_real_b; + u8 h15_imag_b; + u8 h16_real_b; + u8 h16_imag_b; + u8 h17_real_b; + u8 h17_imag_b; +}; + +struct physts_ie_30_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_2bit:2; + u8 ant_weight_c_l:1; + + u8 ant_weight_c_m; + u8 h3_real_c; + u8 h3_imag_c; + u8 h4_real_c; + u8 h4_imag_c; + u8 h5_real_c; + u8 h5_imag_c; + u8 h6_real_c; + u8 h6_imag_c; + u8 h7_real_c; + u8 h7_imag_c; + u8 h8_real_c; + u8 h8_imag_c; + u8 h9_real_c; + u8 h9_imag_c; + u8 h10_real_c; + u8 h10_imag_c; + u8 h11_real_c; + u8 h11_imag_c; + u8 h12_real_c; + u8 h12_imag_c; + u8 h13_real_c; + u8 h13_imag_c; + u8 h14_real_c; + u8 h14_imag_c; + u8 h15_real_c; + u8 h15_imag_c; + u8 h16_real_c; + u8 h16_imag_c; + u8 h17_real_c; + u8 h17_imag_c; +}; + +struct physts_ie_31_info { + /*[DW0]*/ + u8 ie_hdr:5; + u8 rsvd_0_dummy_2bit:2; + u8 ant_weight_d_l:1; + + u8 ant_weight_d_m; + u8 h3_real_d; + u8 h3_imag_d; + u8 h4_real_d; + u8 h4_imag_d; + u8 h5_real_d; + u8 h5_imag_d; + u8 h6_real_d; + u8 h6_imag_d; + u8 h7_real_d; + u8 h7_imag_d; + u8 h8_real_d; + u8 h8_imag_d; + u8 h9_real_d; + u8 h9_imag_d; + u8 h10_real_d; + u8 h10_imag_d; + u8 h11_real_d; + u8 h11_imag_d; + u8 h12_real_d; + u8 h12_imag_d; + u8 h13_real_d; + u8 h13_imag_d; + u8 h14_real_d; + u8 h14_imag_d; + u8 h15_real_d; + u8 h15_imag_d; + u8 h16_real_d; + u8 h16_imag_d; + u8 h17_real_d; + u8 h17_imag_d; +}; + + /*@--------------------------[Prptotype]-------------------------------------*/ +#endif diff --git a/phl/hal_g6/phy/bb/halbb_plcp_gen.c b/phl/hal_g6/phy/bb/halbb_plcp_gen.c new file mode 100644 index 0000000..2a4664f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_plcp_gen.c @@ -0,0 +1,871 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" +#include "halbb_plcp_gen.h" +//search tb_ru_tot_sts_max + +void halbb_set_bit(u8 strt, u8 len, u32 in, u32 *out) +{ + u32 bit_mask = 0; + u8 i = 0; + + for (i = 0; i < len; i++) + bit_mask += 1 << i; + in &= bit_mask; + *out |= (in << strt); +} + +void halbb_write_cr(struct bb_info *bb, struct cr_address_t cr_address, u32 val, enum phl_phy_idx phy_idx) +{ + halbb_set_reg_cmn(bb, cr_address.address, cr_address.bitmask, val, phy_idx); +} + +u32 halbb_ceil(u32 numerator, u32 denominator) +{ + u32 out = 0; + /*========[ return BSOD ]========*/ +// if (denominator == 0) +// return 0; + out = (numerator / denominator) + (numerator > (numerator / denominator)*denominator); + return out; +} + +u32 halbb_mod(u32 numerator, u32 denominator) +{ + u32 out; + /*========[ return BSOD ]========*/ +// if (denominator == 0) +// return 0; + out = numerator - (numerator / denominator) * denominator; + return out; +} + +u32 halbb_min(u32 val_1, u32 val_2) +{ + u32 out = val_1 > val_2 ? val_2 : val_1; + return out; +} + +u32 halbb_max(u32 val_1, u32 val_2) +{ + u32 out = val_1 < val_2 ? val_2 : val_1; + return out; +} +enum spec_list halbb_format2spec(enum packet_format_t in, bool *valid) +{ + enum spec_list spec = SPEC_B_MODE; + + *valid = true; + + switch (in){ + case B_MODE_FMT: + spec = SPEC_B_MODE; + break; + case LEGACY_FMT: + spec = SPEC_LEGACY; + break; + case HT_MF_FMT: + case HT_GF_FMT: + spec = SPEC_HT; + break; + case VHT_FMT: + spec = SPEC_VHT; + break; + case HE_SU_FMT: + case HE_ER_SU_FMT: + case HE_MU_FMT: + case HE_TB_FMT: + spec = SPEC_HE; + break; + default: + (*valid) = false; + break; + } + + return spec; +} + +void halbb_find_apep(u32 *apep, bool *can_find, u32 *n_mpdu, u32 *mpdu_length, u8 spec_idx) +{ + u32 apep_tmp; + bool is_match; + + if (spec_idx == SPEC_HT) + *n_mpdu = halbb_max(halbb_ceil(*apep, (1 << 12) - 1 + 4), 2); + else + *n_mpdu = halbb_ceil(*apep, (1 << 14) - 1 + 4); + + /*========[ return BSOD ]========*/ +// if (*n_mpdu == 0) +// return; + + + *mpdu_length = *apep / *n_mpdu - 4; //????????????? + *mpdu_length = *apep - (4 + 4 * halbb_ceil(*mpdu_length, 4)) * (*n_mpdu - 1) - 4; + apep_tmp = (*n_mpdu - 1)*(4 + 4 * halbb_ceil(*mpdu_length, 4)) + (4 + *mpdu_length); + is_match = (apep_tmp == *apep); + *can_find = true; + while (!is_match) + { + *n_mpdu = *n_mpdu + 1; + + /*========[ return BSOD ]========*/ +// if (*n_mpdu == 0) +// return; + + *mpdu_length = *apep / *n_mpdu - 4; + *mpdu_length = *apep - (4 + 4 * halbb_ceil(*mpdu_length , 4)) * (*n_mpdu - 1) - 4; + apep_tmp = (*n_mpdu - 1)*(4 + 4 * halbb_ceil(*mpdu_length , 4)) + (4 + *mpdu_length); + is_match = apep_tmp == *apep; + if (*n_mpdu > (1 << 8)){ + *can_find = false; + break; + } + } +} + + +void halbb_com_par_cal(struct bb_info *bb, u16 n_sd, enum coding_rate_t code_rate, u8 n_bpscs, u8 nss, bool dcm, struct plcp_mcs_table_out_t *out) +{ + if (dcm) + out->n_cbps = (n_sd * nss * n_bpscs) >> 1; + else + out->n_cbps = n_sd * nss * n_bpscs; + + switch (code_rate) { + case R12: + out->n_dbps = out->n_cbps >> 1; + break; + case R23: + out->n_dbps = (out->n_cbps * 2) / 3; + break; + case R34: + out->n_dbps = (out->n_cbps * 3) / 4; + break; + case R56: + out->n_dbps = (out->n_cbps * 5) / 6; + break; + default: + break; + } +} + +bool ldpc_extra_check(u32 n_avbits, u32 n_pld, u8 code_rate) +{ + bool cnd0, cnd1, cnd2; + u32 n_cw = 0, l_ldpc = 0, l_ldpc_idx = 0; + u32 n_shrt = 0, n_punc = 0; + u32 table0[4][4] = {{456, 304, 228, 152}, {732, 488, 366, 244}, + {1458, 972, 729, 486}, {972, 1296, 1458, 1620}};//912 * (1-R), 1464 * (1-R), 2916 * (1-R), 1944 * R + u32 table1[3][4] = {{324, 432, 486, 540}, {648, 864, 972, 1080}, + {972, 1296, 1458, 1620}};//648 * R, 1296 * R, 1944 * R + u32 table2[4] = {1, 2, 3, 5} ; + + if (n_avbits <= 648) { + n_cw = 1; + if (n_avbits >= n_pld + table0[0][code_rate]) + l_ldpc = 1296; + else + l_ldpc = 648; + } else if (n_avbits <= 1296) { + n_cw = 1; + if (n_avbits >= n_pld + table0[1][code_rate]) + l_ldpc = 1944; + else + l_ldpc = 1296; + } else if (n_avbits <= 1944) { + n_cw = 1; + l_ldpc = 1944; + } else if (n_avbits <= 2592) { + n_cw = 2; + if (n_avbits >= n_pld + table0[2][code_rate]) + l_ldpc = 1944; + else + l_ldpc = 1296; + } else { + l_ldpc = 1944; + n_cw = halbb_ceil(n_pld, table0[3][code_rate]); + } + + if (l_ldpc == 648) + l_ldpc_idx = 0; + else if (l_ldpc == 1296) + l_ldpc_idx = 1; + else if (l_ldpc == 1944) + l_ldpc_idx = 2; + + n_shrt = n_cw * table1[l_ldpc_idx][code_rate] > n_pld ? n_cw * table1[l_ldpc_idx][code_rate] - n_pld : 0; + n_punc = n_cw * l_ldpc > n_avbits + n_shrt ? n_cw * l_ldpc - n_avbits - n_shrt : 0; + + cnd0 = 10 * n_punc > n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]); + + cnd1 = 10 * n_shrt < 12 * n_punc * table2[code_rate]; + cnd2 = n_punc * 10 > 3 * n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]); //n_punc * 10 > 3 * n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]); ? + + return (cnd0 && cnd1) || cnd2; +} + +bool halbb_legacy_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out) +{ + u16 n_dbps_table[8] = {24, 36, 48, 72, 96, 144, 192, 216}; // int size + u16 n_cbps_table[8] = {48, 48, 96, 96, 192, 192, 288, 288}; + enum coding_rate_t code_rate_table[8] = {R12, R34, R12, R34, R12, R34, + R23,R34}; + /*if (in->mcs < 8) + out->valid = true; + else + out->valid = false; + */ + if (in->mcs >= 8) { + //rtw_error("invalid mcs input"); + out->valid = false; + return false; + } else { + out->valid = true; + } + + out->code_rate = code_rate_table[in->mcs]; + out->n_cbps = n_cbps_table[in->mcs]; + out->n_dbps = n_dbps_table[in->mcs]; + out->n_es = 1; + out->fec = 0; + out->dcm = 0; + out->nss = 1; + + return true; +} + +bool halbb_ht_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out) +{ + + u8 nss, mcs; + u16 n_sd_table[2] = {52, 108}; + u8 n_bpscs_table[8] = {1, 2, 2, 4, 4, 6, 6, 6}; + enum coding_rate_t code_rate_table[8] = {R12, R12, R34, R12, R34, R23, + R34, R56}; + + out->valid = ((in->bw < 2) && (in->mcs <= 32)); + if ((in->mcs == 32) && (in->bw == 1)) {//????????????????????????????????????????????????????????????? + out->code_rate = R12; + out->n_cbps = 48; + out->n_dbps = 24; + out->n_es = 1; + out->valid = in->fec == BCC; + out->fec = 0; + out->nss = 1; + out->dcm = 0; + } else if (out->valid) { + nss = (in->mcs >> 3) + 1; + mcs = in->mcs - ((nss - 1) << 3); + out->code_rate = code_rate_table[mcs]; + halbb_com_par_cal(bb, n_sd_table[in->bw], code_rate_table[mcs], + n_bpscs_table[mcs], nss, false, out); + out->n_es = in->fec == BCC ? ((in->mcs == 21 || in->mcs == 22 || + in->mcs == 23 || in->mcs == 28 || + in->mcs == 29 || in->mcs == 30 || + in->mcs == 31) && in->bw == 1) + 1 + : 0; + out->fec = in->fec; + out->nss = nss; + out->dcm = 0; + } else { + return false; + //rtw_error("invalid mcs input"); + } + return true; +} + +bool halbb_vht_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out){ + u16 n_sd_table[4] = {52, 108, 234, 468}; + enum coding_rate_t code_rate_table[12] = {R12, R12, R34, R12, R34, R23, + R34, R56, R34, R56, R34, R56}; + u8 n_bpscs_table[12] = { 1, 2, 2, 4, 4, 6, 6, 6, 8, 8, 10, 10}; + s8 n_es_table[4][8][12] = { + { + { 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 2, -1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 2, -1, 0, 0 } + }, + { + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 }, + { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0} + }, + { + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 }, + { 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 } + }, + { + { 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 0, 0 }, + { 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 0, 0 }, + { 1, 1, 1, 2, 2, 3, 3, 4, 4, -1, 0, 0 }, + { 1, 1, 2, 2, 3, 4, 4, 6, 6, 6, 0, 0 }, + { 1, 2, 2, 3, 4, 5, 5, 6, 8, 8, 0, 0 }, + { 1, 2, 2, 3, 4, 6, 6, 8, 8, 9, 0, 0 }, + { 1, 2, 3, 4, 6, 7, 7, 9, 12, 12, 0, 0 }, + { 1, 2, 3, 4, 6, 8, 8, 9, 12, 12, 0, 0 } + } + }; + u16 n_sd = n_sd_table[in->bw]; + u8 n_bpscs = n_bpscs_table[in->mcs]; + //enum coding_rate_t code_rate = code_rate_table[in->mcs]; + u8 nss = in->nss; + + out->valid = ((((in->fec == LDPC) && (in->mcs <= 11)) || + ((in->fec == BCC) && (in->mcs <= 9))) && + ((in->nss > 0) && (in->nss <= 8))); + out->code_rate = code_rate_table[in->mcs]; + halbb_com_par_cal(bb, n_sd, code_rate_table[in->mcs], n_bpscs, nss, false, out); + if ((in->fec == BCC) && (out->valid)) { + s8 n_es = n_es_table[in->bw][in->nss - 1][in->mcs]; + out->n_es = n_es; + out->valid = (n_es != -1); + out->fec = in->fec; + out->dcm = 0; + out->nss = in->nss; + } else if (out->valid) { + out->n_es = 0; + out->fec = in->fec; + out->dcm = 0; + out->nss = in->nss; + } else { + //rtw_error("invalid mcs input"); + return false; + } + return true; +} + +bool halbb_he_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out) +{ + struct plcp_mcs_table_out_t out_temp; + u16 n_sd_table[8] = {24, 48, 102, 234, 468, 980, 1960, 52}; + enum coding_rate_t code_rate_table[12] = {R12, R12, R34, R12, R34, R23, + R34, R56, R34, R56, R34, R56}; + u8 n_bpscs_table[12] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8, 10, 10}; + u16 n_sd_short_table[2][8] = {{6,12,24,60,120,240,492,0}, + {2,6,12,30,60,120,246,0} }; + out->valid = ((in->nss > 0 && in->nss <= 8) && (!in->dcm || in->mcs == 0 || in->mcs == 1 || in->mcs == 3 || in->mcs == 4) && (!in->dcm || in->nss == 1 || in->nss == 2) && (in->fec == LDPC || ( in->mcs <= 9 && in->ru_size <= RU242))); + if (!out->valid) { + //rtw_error("invalid mcs input"); + return false; + } + out->code_rate = code_rate_table[in->mcs]; + halbb_com_par_cal(bb, n_sd_table[in->ru_size], code_rate_table[in->mcs], + n_bpscs_table[in->mcs], in->ru_size==HESIGB ? 1 : in->nss, + in->dcm, out); + out->n_es = in->fec == BCC || in->ru_size == HESIGB; + halbb_com_par_cal(bb, n_sd_short_table[in->dcm][in->ru_size], code_rate_table[in->mcs], n_bpscs_table[in->mcs],in->nss,false,&out_temp); + out->he_n_cbps_short = out_temp.n_cbps; + out->he_n_dbps_short = out_temp.n_dbps; + out->fec = in->fec || in->ru_size == HESIGB; + out->dcm = in->dcm; + out->nss = in->ru_size == HESIGB ? 1 : in->nss; + + return true; +} + +enum plcp_sts halbb_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out) +{ + switch ((enum spec_list)(in->spec_idx)) { + case SPEC_LEGACY: + if (!halbb_legacy_mcs_table(bb, in, out)) + return OFDM_INVALID; + break; + case SPEC_HT: + if (!halbb_ht_mcs_table(bb, in, out)) + return HT_INVALID; + break; + case SPEC_VHT: + if (!halbb_vht_mcs_table(bb, in, out)) + return VHT_INVALID; + break; + case SPEC_HE: + if (!halbb_he_mcs_table(bb, in, out)) + return HE_INVALID; + break; + default: + out->valid = false; + return SPEC_INVALID; + //break; + } + //rtw_assert(out->valid, "invalid spec"); + return PLCP_SUCCESS; +} + + +void halbb_get_mcs_out(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out, bool *valid){ + + bool mu_usr_en[9] = { false,false,false,false,false,false,false,true,true }; + struct plcp_mcs_table_in_t mcs_in; + enum spec_list spec; + u32 u = 0; + + if (mu_usr_en[in->format_idx]) + par->com.n_usr_refine = in->n_user; + else + par->com.n_usr_refine = 1; + + spec = halbb_format2spec((enum packet_format_t)(in->format_idx), valid); + if (!(*valid)){ + //rtw_error("invalid spec"); + return; + } + + par->com.spec_idx = spec; + mcs_in.spec_idx = (u8)spec;//????????????????????????????????????????????????????????????????????????????????? + for (u = 0; u < par->com.n_usr_refine; u++){ + mcs_in.bw = in->dbw; + mcs_in.dcm = in->usr[u].dcm; + mcs_in.fec = in->usr[u].fec; + mcs_in.mcs = in->usr[u].mcs; + mcs_in.nss = in->usr[u].nss; + if (par->com.spec_idx == SPEC_HE) { + if (in->format_idx == HE_TB_FMT || in->format_idx == HE_MU_FMT) + mcs_in.ru_size = in->usr[u].ru_size_idx; + else if (in->format_idx == HE_ER_SU_FMT) + mcs_in.ru_size = (u8)(3 - in->he_er_u106ru_en);//????????????????????????????????????????????????????????????????????????????????? + else + mcs_in.ru_size = in->dbw + 3; + } else { + mcs_in.ru_size = 0; + } + par->usr[u].ru_size_refine = mcs_in.ru_size; + out->plcp_valid = halbb_mcs_table(bb, &mcs_in, &par->usr_mcs_out[u]); + out->usr[u].mcs_valid = par->usr_mcs_out[u].valid; + if (!par->usr_mcs_out[u].valid){ + *valid = false; + return; + } + out->usr[u].ru_size = mcs_in.ru_size; + out->usr[u].dcm = par->usr_mcs_out[u].dcm; + out->usr[u].fec = par->usr_mcs_out[u].fec; + out->usr[u].nss = par->usr_mcs_out[u].nss; + } +} + +void halbb_get_nsym_init(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par) +{ + u8 n_tail = 6; + u8 n_service = 16; + u32 u_max = 0; + u32 val_max = 0; + u32 comp_val; + u32 u = 0; + + for (u = 0; u < par->com.n_usr_refine; u++){ + par->usr[u].n_excess = halbb_mod((par->usr[u].apep_refine << 3) + par->usr_mcs_out[u].n_es * n_tail + n_service, par->usr_mcs_out[u].n_dbps << par->com.stbc); + if (par->usr[u].n_excess == 0 || par->com.spec_idx != SPEC_HE) + par->usr[u].pre_fec_padding_factor_init = 4; + else + par->usr[u].pre_fec_padding_factor_init = halbb_min(halbb_ceil(par->usr[u].n_excess, par->usr_mcs_out[u].he_n_dbps_short << par->com.stbc), 4); + + par->usr[u].n_sym_init = halbb_ceil((par->usr[u].apep_refine << 3) + n_service + n_tail * par->usr_mcs_out[u].n_es, par->usr_mcs_out[u].n_dbps << par->com.stbc) << par->com.stbc; + + comp_val = ((par->usr[u].n_sym_init - par->com.m_stbc) << 2) + (par->usr[u].pre_fec_padding_factor_init << par->com.stbc); + if (comp_val >= val_max) { + val_max = comp_val; + u_max = u; + } + } + + par->com.n_sym_init = (u16)par->usr[u_max].n_sym_init;//????????????????????????????????????????????????????????????????????????????????? + par->com.pre_fec_padding_factor_init = (u16)par->usr[u_max].pre_fec_padding_factor_init;//????????????????????????????????????????????????????????????????????????????????? + + if (par->com.pre_fec_padding_factor_init < 4) { + for (u = 0; u < par->com.n_usr_refine; u++){ + par->usr[u].n_dbps_last_init = par->com.pre_fec_padding_factor_init * par->usr_mcs_out[u].he_n_dbps_short; + par->usr[u].n_cbps_last_init = par->com.pre_fec_padding_factor_init * par->usr_mcs_out[u].he_n_cbps_short; + } + } else { + for (u = 0; u < in->n_user; u++) { + par->usr[u].n_dbps_last_init = par->usr_mcs_out[u].n_dbps; + par->usr[u].n_cbps_last_init = par->usr_mcs_out[u].n_cbps; + } + } + +} + +void halbb_get_nsym(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, const struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out) +{ + u8 n_service, n_tail; + u8 t_pe_table[4][3] = {{0, 2, 4}, {0, 0, 1}, {0, 0, 2}, {0, 1, 3}}; + u32 n_pld, n_avbits, n_dpbs_last; + u32 psdu = 0; + u32 u = 0; + + if (!par->com.ndp_en) { + n_service = 16; + n_tail = 6; + out->ldpc_extra = false; + + out->stbc = par->com.stbc; + for (u = 0; u < par->com.n_usr_refine; u++) { + out->usr[u].nsts = out->usr[u].nss << par->com.stbc; + if (par->usr_mcs_out[u].fec == LDPC) { + if (par->com.spec_idx == SPEC_HT) + n_pld = (par->usr[u].apep_refine << 3) + n_service; + else + n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (par->usr[u].n_dbps_last_init << par->com.stbc); + + n_avbits = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_cbps + (par->usr[u].n_cbps_last_init << par->com.stbc); + out->ldpc_extra = ldpc_extra_check(n_avbits, n_pld, (u8)par->usr_mcs_out[u].code_rate);//????????????????????????????????????????????????????????????????????????????????? + if (out->ldpc_extra > 0) + break; + } + } + + out->doppler_en = par->com.doppler_mode > 0; + out->midamble = out->doppler_en ? par->com.doppler_mode - 1 : 0; + + if (out->ldpc_extra > 0 || (par->com.tb_trig && par->com.tb_ldpc_extra)) { + if (par->com.pre_fec_padding_factor_init == 4) { + out->n_sym = par->com.n_sym_init + par->com.m_stbc; + out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? 1 : 0; + } else { + out->n_sym = par->com.n_sym_init; + out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? halbb_mod(par->com.pre_fec_padding_factor_init + 1, 4) : 0; + } + } else { + out->n_sym = par->com.n_sym_init; + out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? halbb_mod(par->com.pre_fec_padding_factor_init, 4) : 0; + } + + for (u = 0; u < par->com.n_usr_refine; u++) { + //u32 n_pld(0), psdu(0); + if (par->com.spec_idx == SPEC_HT && par->usr_mcs_out[u].fec == LDPC) { + n_pld = (in->usr[u].apep << 3) + n_service; + } else if (par->usr_mcs_out[u].fec == LDPC) { + n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (par->usr[u].n_dbps_last_init << par->com.stbc); + } else { + n_dpbs_last = out->pre_fec_padding_factor == 0 ? par->usr_mcs_out[u].n_dbps : par->usr_mcs_out[u].he_n_dbps_short * out->pre_fec_padding_factor; + n_pld = (out->n_sym - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (n_dpbs_last << par->com.stbc); + } + + psdu = (n_pld - n_service - n_tail * par->usr_mcs_out[u].n_es) >> 3; + //out->usr[u]->eof_padding_length = max(0,psdu - ceil(par->usr[u]->apep_refine, 4) << 2); + if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && par->usr[u].n_mpdu_refine == 1)) { + out->usr[u].eof_padding_length = 0; + } else { + out->usr[u].eof_padding_length = (psdu > (halbb_ceil(par->usr[u].apep_refine, 4) << 2)) ? (psdu - (halbb_ceil(par->usr[u].apep_refine, 4) << 2)) : 0; + } + out->usr[u].nsts = par->usr_mcs_out[u].nss << par->com.stbc; + out->usr[u].apep_len = par->usr[u].apep_refine; + out->usr[u].mpdu_length_byte = par->usr[u].mpdu_length_byte_refine; + out->usr[u].n_mpdu = par->usr[u].n_mpdu_refine; + } + + if (par->com.tb_trig) + out->t_pe = par->com.tb_trig_t_pe; + else + out->t_pe = par->com.spec_idx == SPEC_HE ? t_pe_table[out->pre_fec_padding_factor][in->nominal_t_pe] : 0; + + } else { + out->ldpc_extra = false; + out->t_pe = par->com.spec_idx == SPEC_HE ? 2 : 0; + out->stbc = par->com.stbc; + for (u = 0; u < par->com.n_usr_refine; u++) { + out->usr[u].eof_padding_length = 0; + out->usr[u].nsts = par->usr_mcs_out[u].nss << par->com.stbc; + out->usr[u].apep_len = par->usr[u].apep_refine; + out->usr[u].mpdu_length_byte = par->usr[u].mpdu_length_byte_refine; + out->usr[u].n_mpdu = par->usr[u].n_mpdu_refine; + } + out->n_sym = 0; + out->pre_fec_padding_factor = 0; + } + out->n_sym_hesigb = par->com.n_hesigb_sym; +} + +void halbb_get_txtime(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out) +{ + struct bb_h2c_fw_tx_setting *fw_tx_i = &bb->bb_fwtx_h2c_i; + //n_ma, m_ma + u8 m_table[9] = {0,0,0,0,0,2,1,1,2}; + u32 l_len_temp; + + if (par->com.doppler_mode > 0) + par->com.n_ma = halbb_ceil(out->n_sym - 1, par->com.m_ma) > 1 ? halbb_ceil(out->n_sym - 1, par->com.m_ma) - 1 : 0; + else + par->com.n_ma = 0; + + out->tx_time_0p4us = par->com.preamble_0p4us + par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + out->n_sym * par->com.t_sym_0p4us + out->t_pe * 10; + + if (par->com.spec_idx == SPEC_LEGACY) { + out->l_len = (u16)par->usr[0].apep_refine; //????????????????????????????????????????????????????????????????????????????????? + } else { + l_len_temp = halbb_ceil(out->tx_time_0p4us - 50, 10) * 3 - 3 - m_table[in->format_idx]; + if (par->com.spec_idx == SPEC_HT) + out->l_len = (u16)halbb_max(l_len_temp,in->ht_l_len);//????????????????????????????????????????????????????????????????????????????????? + else + out->l_len = (u16)l_len_temp;//????????????????????????????????????????????????????????????????????????????????? + } + + if (par->com.spec_idx == SPEC_VHT) + out->disamb = par->com.gi == 0 ? halbb_mod(out->n_sym, 10) == 9 : 0; + else if (par->com.spec_idx == SPEC_HE) + out->disamb = (out->t_pe * 10 + halbb_mod(10 - halbb_mod(out->tx_time_0p4us, 10), 10)) >= par->com.t_sym_0p4us; + else + out->disamb = 0; + out->ndp = par->com.ndp_en; + out->n_ltf = par->com.n_ltf_sym > 0 ? (u16)(par->com.n_ltf_sym - 1) : 0;//????????????????????????????????????????????????????????????????????????????????? + out->valid = out->tx_time_0p4us <= 13710 || in->format_idx == HT_GF_FMT; + fw_tx_i->tx_time[0]= (u8) (out->tx_time_0p4us & 0x000000ff); // for FW trigger specific duty cycle used + fw_tx_i->tx_time[1]= (u8) ((out->tx_time_0p4us & 0x0000ff00) >> 8); + fw_tx_i->tx_time[2]= (u8) ((out->tx_time_0p4us & 0x00ff0000) >> 16); + fw_tx_i->tx_time[3]= (u8) ((out->tx_time_0p4us & 0xff000000) >> 24); + //rtw_assert(out->valid,"txtime exceeds"); + if (!out->valid) + out->plcp_valid = LENGTH_EXCEED; + out->n_usr = par->com.n_usr_refine; + out->gi = par->com.gi; +} + +void halbb_refine_input(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par) +{ + bool can_find = false , disam; + u8 n_tail = 6; + u8 n_service = 24; + u8 remain_time_0p4us; + u32 n_mpdu = 0, mpdu_length = 0, apep, tmp, max_tx_time_0p4us, n_dbps_last, n_pld, n_psdu; + bool ndp_en_table[9] = {false,false,true,true,true,true,false,false,false}; + u8 n_ltf_table[9] = { 0, 1, 2, 4, 4, 6, 6, 8, 8 }; + u8 t_fft_0p4us[2] = { 8, 32 }; + u8 must_preamble_0p4us_table[9] = { 0, 50, 80, 50, 90, 90, 110, 90, 100 }; + u8 m_ma_table[3] = { 0, 10, 20 }; + u32 u = 0; + u8 spec_idx = 0; + + spec_idx = (u8)par->com.spec_idx; + + if (par->com.spec_idx > SPEC_LEGACY) + par->com.stbc = in->stbc; + else + par->com.stbc = false; + + par->com.m_stbc = par->com.stbc + 1; + if (par->com.spec_idx == SPEC_HE) + par->com.doppler_mode = in->doppler_mode; + else + par->com.doppler_mode = 0; + + par->com.n_sts_max = 0; + for (u = 0; u < par->com.n_usr_refine; u++) + par->com.n_sts_max = halbb_max(par->com.n_sts_max, par->usr_mcs_out[u].nss << par->com.stbc); + + if (in->format_idx == HE_TB_FMT && in->mode_idx == 3) + par->com.n_ltf_sym = n_ltf_table[in->tb_ru_tot_sts_max+1]; + else + par->com.n_ltf_sym = (par->com.spec_idx == SPEC_LEGACY ? 0 : n_ltf_table[par->com.n_sts_max]) + n_ltf_table[par->com.spec_idx == SPEC_HT ? in->ness : 0]; + + if (in->format_idx == HE_MU_FMT) + par->com.n_hesigb_sym = in->n_hesigb_sym; + else + par->com.n_hesigb_sym = 0; + //t_sym + if (par->com.spec_idx == SPEC_LEGACY) + par->com.gi = 1; + else if (par->com.spec_idx == SPEC_HT || par->com.spec_idx == SPEC_VHT) + par->com.gi = in->gi > 0; + else + par->com.gi = (u8)halbb_max(1,in->gi); //??????????????????????????????????? + + + par->com.t_sym_0p4us = t_fft_0p4us[par->com.spec_idx == SPEC_HE] + (1 << par->com.gi); + if (par->com.spec_idx == SPEC_HE) + par->com.t_ltf_sym_0p4us = (8 << halbb_min(in->ltf_type, 2)) + (1 << par->com.gi); + else + par->com.t_ltf_sym_0p4us = 10; + + + par->com.preamble_0p4us = must_preamble_0p4us_table[in->format_idx] + (u16)par->com.n_ltf_sym * (u16)par->com.t_ltf_sym_0p4us + (u16)par->com.n_hesigb_sym * 10;//????????????????????????? + + + par->com.m_ma = m_ma_table[par->com.doppler_mode]; + + + par->com.ndp_en = ndp_en_table[in->format_idx] && in->ndp; + par->com.tb_trig = (in->mode_idx == 3 && in->format_idx == HE_TB_FMT); + if (par->com.ndp_en) { + apep = 0; + for (u = 0; u < par->com.n_usr_refine; u++) { + par->usr[u].n_mpdu_refine = 1; + par->usr[u].mpdu_length_byte_refine = apep; + par->usr[u].apep_refine = apep; + } + } else if (in->mode_idx == 0){//apep + for (u = 0; u < par->com.n_usr_refine; u++) { + apep = in->usr[u].apep; + if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && apep < (1 << 14))) { + par->usr[u].n_mpdu_refine = 1; + par->usr[u].mpdu_length_byte_refine = apep; + par->usr[u].apep_refine = apep; + } else{ + halbb_find_apep(&apep,&can_find,&n_mpdu,&mpdu_length,spec_idx); + while (!can_find){ + apep = apep - 1; + halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx); + } + par->usr[u].n_mpdu_refine = n_mpdu; + par->usr[u].mpdu_length_byte_refine = mpdu_length; + par->usr[u].apep_refine = apep; + } + } + } else if(in->mode_idx == 1 || par->com.tb_trig) { // max_tx_time + disam = par->com.spec_idx == SPEC_HE ? in->nominal_t_pe == 2 : false; + disam = par->com.tb_trig ? (bool)in->tb_disam : disam; //?????????????????????????????????????????????? +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + /*========[ return BSOD ]========*/ +// if ((par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + par->com.m_ma * par->com.t_sym_0p4us) == 0) +// return; + + + max_tx_time_0p4us = par->com.tb_trig ? halbb_ceil(in->tb_l_len + 3 + 2,3)*10 : in->max_tx_time_0p4us; + tmp = (max_tx_time_0p4us > par->com.preamble_0p4us + (disam + 2) * par->com.t_sym_0p4us ) && par->com.doppler_mode > 0 ? (in->max_tx_time_0p4us - par->com.preamble_0p4us - (disam + 2) * par->com.t_sym_0p4us) / (par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + par->com.m_ma * par->com.t_sym_0p4us) : 0; + par->com.n_ma = par->com.doppler_mode > 0 ? tmp : 0; + par->com.n_sym_init = ((u16)max_tx_time_0p4us - par->com.preamble_0p4us - ((u16)par->com.n_ma * (u16)par->com.n_ltf_sym * (u16)par->com.t_ltf_sym_0p4us)) / (u16)par->com.t_sym_0p4us - disam; // Look + + if (par->com.stbc) + par->com.n_sym_init = (u16)halbb_ceil(par->com.n_sym_init, 2) << 1; //??????????????????????????????? + + remain_time_0p4us = (u8)(max_tx_time_0p4us - par->com.preamble_0p4us - par->com.n_sym_init * par->com.t_sym_0p4us - par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us);//????????????????????????????????? false? + + if (par->com.spec_idx == SPEC_HE && !par->com.tb_trig) { + if (remain_time_0p4us >= 40) { + par->com.pre_fec_padding_factor_init = 4; + } else if (remain_time_0p4us >= 30) { + if (in->nominal_t_pe == 2) + par->com.pre_fec_padding_factor_init = 3; + else + par->com.pre_fec_padding_factor_init = 4; + } else if (remain_time_0p4us >= 20) { + if (in->nominal_t_pe == 2) + par->com.pre_fec_padding_factor_init = 2; + else + par->com.pre_fec_padding_factor_init = 4; + } else if (remain_time_0p4us >= 10) { + if (in->nominal_t_pe == 2) + par->com.pre_fec_padding_factor_init = 1; + else if (in->nominal_t_pe == 1) + par->com.pre_fec_padding_factor_init = 3; + else + par->com.pre_fec_padding_factor_init = 4; + } else if (remain_time_0p4us >= 0) { + if (in->nominal_t_pe == 2) + par->com.pre_fec_padding_factor_init = 1; + else if (in->nominal_t_pe == 1) + par->com.pre_fec_padding_factor_init = 1; + else + par->com.pre_fec_padding_factor_init = 1; + } + } else if(!par->com.tb_trig) { + par->com.pre_fec_padding_factor_init = 4; + } else { + //tb_tri_en + par->com.tb_trig_t_pe = (max_tx_time_0p4us - par->com.preamble_0p4us - par->com.n_sym_init * par->com.t_sym_0p4us - par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us)/10; + par->com.tb_ldpc_extra = in->tb_ldpc_extra; + if (par->com.tb_ldpc_extra) { + if (in->tb_pre_fec_padding_factor == 1) { + par->com.n_sym_init = par->com.n_sym_init - 1; + par->com.pre_fec_padding_factor_init = 4; + } else { + par->com.n_sym_init = par->com.n_sym_init; + par->com.pre_fec_padding_factor_init = (u16)in->tb_pre_fec_padding_factor - 1; //?????????????????????????????? + } + } else { + par->com.n_sym_init = par->com.n_sym_init; + par->com.pre_fec_padding_factor_init = in->tb_pre_fec_padding_factor == 0 ? 4 : (u16)in->tb_pre_fec_padding_factor; + } + } + + for (u = 0; u < par->com.n_usr_refine; u++) { + n_dbps_last = par->com.pre_fec_padding_factor_init == 4 ? par->usr_mcs_out[u].n_dbps : par->usr_mcs_out[u].he_n_dbps_short * par->com.pre_fec_padding_factor_init; + n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (n_dbps_last << par->com.stbc); + n_psdu = (n_pld - n_tail * par->usr_mcs_out[u].n_es - n_service) >> 3; + apep = n_psdu; + if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && apep < (1 << 14))) { + par->usr[u].n_mpdu_refine = 1; + par->usr[u].mpdu_length_byte_refine = apep; + par->usr[u].apep_refine = apep; + } else { + //can_find; + //u32 n_mpdu, mpdu_length; + halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx); + while (!can_find) { + apep = apep - 1; + halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx); + } + par->usr[u].n_mpdu_refine = n_mpdu; + par->usr[u].mpdu_length_byte_refine = mpdu_length; + par->usr[u].apep_refine = apep; + } + } + } else { //n_mpdu,mpdu_len + for (u = 0; u < par->com.n_usr_refine; u++) { + par->usr[u].n_mpdu_refine = par->com.spec_idx > SPEC_LEGACY ? in->usr[u].n_mpdu : 1; + par->usr[u].mpdu_length_byte_refine = in->usr[u].mpdu_length_byte; + + if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && par->usr[u].n_mpdu_refine == 1)) + par->usr[u].apep_refine = par->usr[u].mpdu_length_byte_refine; + else + par->usr[u].apep_refine = (par->usr[u].n_mpdu_refine - 1)*(4 + 4 * halbb_ceil(par->usr[u].mpdu_length_byte_refine, 4)) + (4 + par->usr[u].mpdu_length_byte_refine); + } + } +} + +enum plcp_sts halbb_tx_plcp_cal(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_out_t *out) +{ + + bool mcs_out_valid = false; + struct plcp_tx_pre_fec_padding_setting_par_t par; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + halbb_get_mcs_out(bb, in, &par, out, &mcs_out_valid); + if (!mcs_out_valid) { + out->valid = false; + return out->plcp_valid; + } + halbb_refine_input(bb, in, &par); + halbb_get_nsym_init(bb, in, &par); + halbb_get_nsym(bb, in, &par, out); + halbb_get_txtime(bb, in, &par, out); + return out->plcp_valid; +} \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_plcp_gen.h b/phl/hal_g6/phy/bb/halbb_plcp_gen.h new file mode 100644 index 0000000..583fa4b --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_plcp_gen.h @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_PLCP_GEN_H_ +#define _HALBB_PLCP_GEN_H_ + +/* ============================================================ + define + ============================================================ +*/ +#define N_USER 4 + +/* ============================================================ + structure + ============================================================ +*/ + + +struct plcp_mcs_table_in_t { + u8 spec_idx : 3; + u8 mcs : 5; + u8 nss : 4; + u8 bw : 2;//0:BW20, 1:BW40, 2:BW80, 3:BW160 /*enum channel_width*/ + u8 rsvd0 : 2; + u8 ru_size : 3; //0:RU26, 1:RU52, 2:RU106, 3:RU242, 4:RU484, 5:RU996, 6:RU996x2, 7:hesigb + u8 rsvd1 : 5; + bool dcm; + bool fec; +}; + +struct plcp_mcs_table_out_t { + u32 n_dbps : 17; + u32 he_n_dbps_short : 15; + u32 n_cbps : 18; + u32 n_es : 4; + u32 valid : 1; + u32 code_rate : 2; + u32 nss : 3; + u32 rsvd0 : 4; + u32 he_n_cbps_short : 15; + u32 rsvd1 : 17; + bool dcm; + bool fec; +}; +//========== [Par] ==========// +struct com_pre_fec_par { + u16 n_sym_init : 11; + u16 spec_idx : 3; + u16 pre_fec_padding_factor_init : 3; + u16 ndp_en : 1; + u16 preamble_0p4us : 16; + u8 m_stbc : 2; + u8 stbc : 1; + u8 doppler_mode : 2; + u8 gi : 2; + u32 t_sym_0p4us : 6; + u32 t_ltf_sym_0p4us : 6; + u32 n_ltf_sym : 4; + u32 n_sts_max : 4; + u32 n_ma : 6; + u32 m_ma : 5; + u32 tb_trig : 1; + u32 n_hesigb_sym : 8; + u32 n_usr_refine : 8; + u32 tb_trig_t_pe : 3; + u32 tb_ldpc_extra : 1; + u32 rsvd1 : 12; +}; + +struct usr_pre_fec_par { + u32 n_excess : 15; + u32 pre_fec_padding_factor_init : 3; + u32 n_sym_init : 11; + u32 rsvd0 : 3; + u32 n_dbps_last_init : 17; + u32 n_mpdu_refine : 9; + u32 rsvd1 : 6; + u32 n_cbps_last_init : 18; + u32 mpdu_length_byte_refine : 14; + u32 apep_refine : 22; + u32 ru_size_refine : 3; + u32 rsvd3 : 7; +}; + +struct plcp_tx_pre_fec_padding_setting_par_t { + struct com_pre_fec_par com; + struct plcp_mcs_table_out_t usr_mcs_out[4]; + struct usr_pre_fec_par usr[N_USER]; +}; +//========== [Input] ==========// +struct usr_pre_fec_in { + u8 ru_size_idx : 3; + u8 nss : 4; + u8 rsvd0 : 1; + u8 mcs : 6; + u8 rsvd1 : 2; + u32 apep : 22; + u32 n_mpdu : 9; + u32 rsvd2 : 1; + u16 mpdu_length_byte : 14; + u16 rsvd3 : 2; + bool dcm; + bool fec; +}; + +struct plcp_tx_pre_fec_padding_setting_in_t { + u8 format_idx : 4; + u8 stbc : 1; + u8 he_dcm_sigb : 1; + u8 doppler_mode : 2; //0: diable ,1:MA10, 2:MA20 + u16 n_hesigb_sym : 11; //per ch + u16 he_mcs_sigb : 3; + u16 nominal_t_pe : 2; + u8 dbw : 2; + u8 gi : 2; //0.4,0.8,1.6,3.2 + u8 ltf_type : 2; //1x, 2x, 4x + u8 ness : 2; + + u32 mode_idx : 2; //0:apep, 1:max_tx_time, 2:n_mpdu,mpdu_len, 3:tb_trigger_mode + u32 max_tx_time_0p4us : 14; + u32 n_user : 8; + + u32 ndp : 1; + u32 he_er_u106ru_en : 1; //done + u32 rsvd1 : 6; + u32 tb_l_len : 12; + u32 tb_ru_tot_sts_max : 3; + u32 tb_disam : 1; + u32 tb_ldpc_extra : 1; + u32 tb_pre_fec_padding_factor : 2; + u32 ht_l_len : 12; + u32 rsvd2 : 10; + struct usr_pre_fec_in usr[N_USER]; +}; + + +//========== [Output] ==========// +struct usr_pre_fec_out { + u32 nss : 4; + u32 nsts : 4; + u32 mpdu_length_byte : 14; + u32 n_mpdu : 9; + u32 rsvd0 : 1; + u32 eof_padding_length : 32; + u32 apep_len : 22; + u32 ru_size : 3; + u32 mcs_valid : 1; + u32 rsvd1 : 6; + bool fec; + bool dcm; +}; +struct plcp_tx_pre_fec_padding_setting_out_t { + u32 pre_fec_padding_factor : 2; // 0:4, 1:1, 2:2, 3:3 + u32 n_sym : 11; + u32 ldpc_extra : 1; + u32 rsvd : 14; + u32 t_pe : 3; //0: 0us, 1:4us, 2:8us, 3:12us, 4:16us + u32 valid : 1; + u16 l_len : 12; + u16 disamb : 1; + u16 n_ltf : 3; + u32 tx_time_0p4us; + u32 stbc : 1; + u32 doppler_en : 1; + u32 midamble : 2; + u32 n_usr : 8; + u32 ndp : 1; + u32 gi : 2; + u32 n_sym_hesigb : 6; + u32 plcp_valid : 8; + u32 rvsd0 : 3; + struct usr_pre_fec_out usr[N_USER]; +}; + +/* ============================================================ + Enumeration + ============================================================ +*/ +enum spec_list { + SPEC_B_MODE = 0, + SPEC_LEGACY = 1, + SPEC_HT = 2, + SPEC_VHT = 3, + SPEC_HE = 4 +}; + +enum fec_t { + BCC = 0, + LDPC +}; + +enum ru_sizes_list{ + RU26 = 0, + RU52, + RU106, + RU242, + RU484, + RU996, + RU996X2, + HESIGB +}; + +enum packet_format_t{ + B_MODE_FMT = 0, + LEGACY_FMT, + HT_MF_FMT, + HT_GF_FMT, + VHT_FMT, + HE_SU_FMT, + HE_ER_SU_FMT, + HE_MU_FMT, + HE_TB_FMT +}; + +enum coding_rate_t{ + R12 = 0, + R23, + R34, + R56 +}; + +/* ============================================================ + Function Prototype + ============================================================ +*/ + +struct bb_info; + +u32 halbb_ceil(u32 numerator, u32 denominator); +u32 halbb_mod(u32 numerator, u32 denominator); +u32 halbb_min(u32 val_1, u32 val_2); +u32 halbb_max(u32 val_1, u32 val_2); +void halbb_set_bit(u8 strt, u8 len, u32 in, u32* out); +void halbb_write_cr(struct bb_info *bb, struct cr_address_t cr_address, u32 val, + enum phl_phy_idx phy_idx); +enum plcp_sts halbb_tx_plcp_cal(struct bb_info *bb, + const struct plcp_tx_pre_fec_padding_setting_in_t *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out); + + +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_plcp_tx.c b/phl/hal_g6/phy/bb/halbb_plcp_tx.c new file mode 100644 index 0000000..32746be --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_plcp_tx.c @@ -0,0 +1,2406 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" +#include "halbb_plcp_gen.h" +//#include "halbb_plcp_tx.h" +//#include "halbb_he_sigb_gen.h" +#ifdef HALBB_PMAC_TX_SUPPORT + +u8 halbb_set_crc8(struct bb_info *bb, unsigned char in[], u8 len) +{ + u16 i = 0; + u8 reg0 = 1; + u8 reg1 = 1; + u8 reg2 = 1; + u8 reg3 = 1; + u8 reg4 = 1; + u8 reg5 = 1; + u8 reg6 = 1; + u8 reg7 = 1; + u8 bit_in = 0; + u8 out = 0; + + for (i = 0; i < len; i++) { + bit_in = in[i] ^ reg7; + reg7 = reg6; + reg6 = reg5; + reg5 = reg4; + reg4 = reg3; + reg3 = reg2; + reg2 = bit_in ^ reg1; + reg1 = bit_in ^ reg0; + reg0 = bit_in; + } + out = (reg0 << 7) | (reg1 << 6) | (reg2 << 5) | (reg3 << 4) | + (reg4 << 3) | (reg5 << 2) | (reg6 << 1) | reg7; + return ~out; +} + + +void rtw_halbb_plcp_gen_init(struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_in_t *in_plcp) +{ + u32 i = 0; + + //Outer Input + in->source_gen_mode = 2; + in->locked_clk = 1; + in->dyn_bw = 0; + in->ndp_en = 0; + in->doppler = 0; + in->ht_l_len = 0; + in->preamble_puncture = 0; + in->he_sigb_compress_en = 1; + in->ul_flag = 0; + in->bss_color= 10; + in->sr = 0; + in->beamchange_en = 1; + in->ul_srp1 = 0; + in->ul_srp2 = 0; + in->ul_srp3 = 0; + in->ul_srp4 = 0; + in->group_id = 0; + in->txop = 127; + in->nominal_t_pe = 2; + in->ness = 0; + in->tb_rsvd = 0; + in->vht_txop_not_allowed = 0; + + for (i = 0; i < in->n_user; i++) { + in->usr[i].mpdu_len = 0; + in->usr[i].n_mpdu = 0; + in->usr[i].txbf = 0; + in->usr[i].scrambler_seed = 0x81; + in->usr[i].random_init_seed = 0x4b; + } + + //PLCP Input + in_plcp->format_idx = (u8)in->ppdu_type; + in_plcp->stbc = (u8)in->stbc; + in_plcp->he_dcm_sigb = (u8)in->he_dcm_sigb; + in_plcp->doppler_mode = (u8)in->doppler; + in_plcp->he_mcs_sigb = (u16)in->he_mcs_sigb; + in_plcp->nominal_t_pe = in->nominal_t_pe; + in_plcp->dbw = (u8)in->dbw; + in_plcp->gi = (u8)in->gi; + in_plcp->ltf_type = (u8)in->he_ltf_type; + in_plcp->ness = in->ness; + in_plcp->mode_idx = (u8)in->mode; + in_plcp->max_tx_time_0p4us = in->max_tx_time_0p4us; + in_plcp->n_user = in->n_user; + in_plcp->ndp = in->ndp_en; + in_plcp->he_er_u106ru_en = in->he_er_u106ru_en; + in_plcp->tb_l_len = in->tb_l_len; + in_plcp->tb_ru_tot_sts_max = in->tb_ru_tot_sts_max; + in_plcp->tb_disam = in->tb_disam; + in_plcp->tb_ldpc_extra = in->tb_ldpc_extra; + in_plcp->tb_pre_fec_padding_factor = in->tb_pre_fec_padding_factor; + in_plcp->ht_l_len = in->ht_l_len; + for (i = 0; i < in_plcp->n_user; i++) { + in_plcp->usr[i].nss = (u8)in->usr[i].nss; + in_plcp->usr[i].fec = (u8)in->usr[i].fec; + in_plcp->usr[i].apep = in->usr[i].apep; + in_plcp->usr[i].dcm = (bool)in->usr[i].dcm; + in_plcp->usr[i].mcs = (u8)in->usr[i].mcs; + in_plcp->usr[i].mpdu_length_byte = (u16)in->usr[i].mpdu_len; + in_plcp->usr[i].n_mpdu = in->usr[i].n_mpdu; + } + + if (in->ppdu_type == HE_SU_FMT) { //HE_SU + if (in->dbw == 0) + in->usr[0].ru_alloc = 122; + else if (in->dbw == 1) + in->usr[0].ru_alloc = 130; + else if (in->dbw == 2) + in->usr[0].ru_alloc = 134; + else + in->usr[0].ru_alloc = 137; + } else if (in->ppdu_type == HE_ER_SU_FMT) { //HE_ER_SU + if (in->he_er_u106ru_en) + in->usr[0].ru_alloc = 108; + else + in->usr[0].ru_alloc = 122; + } +} + +void halbb_plcp_lsig(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx) +{ + bool parity = 0; + u8 lsig_rate = 0; + u32 lsig_bits = 0; + u32 lsig = 0; + u8 i = 0; + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if (in->ppdu_type == LEGACY_FMT) { + switch (in->usr[0].mcs) { + case 0: + lsig_rate = 11; + break; + case 1: + lsig_rate = 15; + break; + case 2: + lsig_rate = 10; + break; + case 3: + lsig_rate = 14; + break; + case 4: + lsig_rate = 9; + break; + case 5: + lsig_rate = 13; + break; + case 6: + lsig_rate = 8; + break; + case 7: + lsig_rate = 12; + break; + default: + break; + } + } else { + lsig_rate = 11; + } + lsig_bits = ((out_plcp->l_len) << 5) + lsig_rate; + for (i = 0; i < 17; i++) + parity ^= (lsig_bits >> i) % 2; + + halbb_set_bit(0, 4, lsig_rate, &lsig); + halbb_set_bit(4, 1, 0, &lsig);// rsvd // + halbb_set_bit(5, 12, out_plcp->l_len, &lsig); + halbb_set_bit(17, 1, parity, &lsig); + halbb_set_bit(18, 6, 0, &lsig); + /*=== Write CR ===*/ + halbb_set_reg_cmn(bb, cr->lsig, cr->lsig_m, lsig, phy_idx); +} + +void halbb_plcp_siga(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx) +{ + u32 siga1 = 0; + u32 siga2 = 0; + unsigned char siga_bits[64] = {0}; + u8 crc8_out; + u8 crc4_out = 0; + u8 i = 0; + u8 n_he_ltf[8] = { 0, 1, 1, 2, 2, 3, 3, 4 }; + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + if ((in->ppdu_type == HE_SU_FMT) || (in->ppdu_type == HE_ER_SU_FMT)) { // HE_SU SIG-A // + /*=== SIG-A1 ===*/ + halbb_set_bit(0, 1, 1, &siga1); + halbb_set_bit(1, 1, in->beamchange_en, &siga1); + halbb_set_bit(2, 1, in->ul_flag, &siga1); + halbb_set_bit(3, 4, in->usr[0].mcs, &siga1); + if ((in->gi == 1) && (in->he_ltf_type == 2)) + halbb_set_bit(7, 1, 1, &siga1); + else + halbb_set_bit(7, 1, out_plcp->usr[0].dcm, &siga1); + halbb_set_bit(8, 6, in->bss_color, &siga1); + halbb_set_bit(14, 1, 1, &siga1); // rsvd // + halbb_set_bit(15, 4, in->sr, &siga1); + if (in->ppdu_type == HE_ER_SU_FMT) { + if (in->he_er_u106ru_en) + halbb_set_bit(19, 2, 1, &siga1); + else + halbb_set_bit(19, 2, 0, &siga1); + } else { + halbb_set_bit(19, 2, in->dbw, &siga1); + } + if (out_plcp->gi == 1 && in->he_ltf_type == 0) + halbb_set_bit(21, 2, 0, &siga1);// he_ltf_type & GI + else if (out_plcp->gi == 1 && in->he_ltf_type == 1) + halbb_set_bit(21, 2, 1, &siga1); + else if (out_plcp->gi == 2 && in->he_ltf_type == 1) + halbb_set_bit(21, 2, 2, &siga1); + else if ((out_plcp->gi == 1 && in->he_ltf_type == 2) || (out_plcp->gi == 3 && in->he_ltf_type == 2)) + halbb_set_bit(21, 2, 3, &siga1); + halbb_set_bit(23, 3, out_plcp->usr[0].nsts-1, &siga1);//NSTS & Midamble// doppler //??????????????? + /*=== SIG-A2 ===*/ + halbb_set_bit(0, 7, in->txop, &siga2); + halbb_set_bit(7, 1, out_plcp->usr[0].fec, &siga2); + if (out_plcp->usr[0].fec == 0) + halbb_set_bit(8, 1, 1, &siga2); + else + halbb_set_bit(8, 1, out_plcp->ldpc_extra, &siga2); + if ((in->gi == 1) && (in->he_ltf_type == 2)) + halbb_set_bit(9, 1, 1, &siga2); + else + halbb_set_bit(9, 1, out_plcp->stbc, &siga2); + halbb_set_bit(10, 1, 0, &siga2);//Beamformed? // + halbb_set_bit(11, 2, out_plcp->pre_fec_padding_factor, &siga2); + halbb_set_bit(13, 1, out_plcp->disamb, &siga2); + halbb_set_bit(14, 1, 1, &siga2); // rsvd // + halbb_set_bit(15, 1, out_plcp->doppler_en, &siga2); + //CRC4// + //--- Set HESIG1 --- + for(i = 0; i < 26; i++) + siga_bits[i] = ( siga1 >> i ) & 0x1 ; + //--- Set HESIG2 --- + for(i = 0; i < 16; i++) + siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, siga_bits, 42); + crc4_out = crc8_out & 0xf; + halbb_set_bit(16, 4, crc4_out, &siga2); + halbb_set_bit(20, 6, 0, &siga2); + } + else if (in->ppdu_type == HE_MU_FMT) { // HE MU SIG-A // + /*=== SIG-A1 ===*/ + halbb_set_bit(0, 1, in->ul_flag, &siga1); + halbb_set_bit(1, 3, in->he_mcs_sigb, &siga1); + halbb_set_bit(4, 1, in->he_dcm_sigb, &siga1); + halbb_set_bit(5, 6, in->bss_color, &siga1); + halbb_set_bit(11, 4, in->sr, &siga1); + halbb_set_bit(15, 3, in->dbw, &siga1); // Bandwidth = DBW + halbb_set_bit(18, 4, out_plcp->n_sym_hesigb, &siga1); + halbb_set_bit(22, 1, 0, &siga1); + if (in->he_ltf_type == 2 && out_plcp->gi == 1) + halbb_set_bit(23, 2, 0, &siga1);// he_ltf_type & GI + else if (in->he_ltf_type == 1 && out_plcp->gi == 1) + halbb_set_bit(23, 2, 1, &siga1); + else if (in->he_ltf_type == 1 && out_plcp->gi == 2) + halbb_set_bit(23, 2, 2, &siga1); + else if (in->he_ltf_type == 2 && out_plcp->gi == 3) + halbb_set_bit(23, 2, 3, &siga1); + halbb_set_bit(25, 1, out_plcp->doppler_en, &siga1); + /*=== SIG-A2 ===*/ + halbb_set_bit(0, 7, in->txop, &siga2); + halbb_set_bit(7, 1, 1, &siga2); //rsvd + halbb_set_bit(8, 3, n_he_ltf[out_plcp->n_ltf], &siga2);//N_LTF & Midamble// doppler + halbb_set_bit(11, 1, out_plcp->ldpc_extra, &siga2);// LDPC extra symbpl seg ldpc_extra + halbb_set_bit(12, 1, out_plcp->stbc, &siga2); + halbb_set_bit(13, 2, out_plcp->pre_fec_padding_factor, &siga2); + halbb_set_bit(15, 1, out_plcp->disamb, &siga2); + //CRC4// + //--- Set HESIG1 --- + for(i = 0; i < 26; i++) + siga_bits[i] = ( siga1 >> i ) & 0x1 ; + //--- Set HESIG2 --- + for(i = 0; i < 16; i++) + siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, siga_bits, 42); + crc4_out = crc8_out & 0xf; + halbb_set_bit(16, 4, crc4_out, &siga2); + halbb_set_bit(20, 6, 0, &siga2); + halbb_set_bit(20, 6, 0, &siga2); + } + else if (in->ppdu_type == HE_TB_FMT) { // HE_TB SIG-A // + /*=== SIG-A1 ===*/ + halbb_set_bit(0, 1, 0, &siga1); + halbb_set_bit(1, 6, in->bss_color, &siga1); + halbb_set_bit(7, 4, in->ul_srp1, &siga1); + halbb_set_bit(11, 4, in->ul_srp2, &siga1); + halbb_set_bit(15, 4, in->ul_srp3, &siga1); + halbb_set_bit(19, 4, in->ul_srp4, &siga1); + halbb_set_bit(23, 1, 1, &siga1); // rsvd // + halbb_set_bit(24, 2, in->dbw, &siga1); + /*=== SIG-A2 ===*/ + halbb_set_bit(0, 7, in->txop, &siga2); + halbb_set_bit(7, 9, in->tb_rsvd, &siga2); + //CRC4// + //--- Set HESIG1 --- + for(i = 0; i < 26; i++) + siga_bits[i] = ( siga1 >> i ) & 0x1 ; + //--- Set HESIG2 --- + for(i = 0; i < 16; i++) + siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, siga_bits, 42); + crc4_out = crc8_out & 0xf; + halbb_set_bit(16, 4, crc4_out, &siga2); + halbb_set_bit(20, 6, 0, &siga2); + } + else if (in->ppdu_type == VHT_FMT) {// VHT SIG-A // + /*=== SIG-A1 ===*/ + halbb_set_bit(0, 2, in->dbw, &siga1); + halbb_set_bit(2, 1, 1, &siga1); // rsvd // + halbb_set_bit(3, 1, out_plcp->stbc, &siga1); + halbb_set_bit(4, 6, in->group_id, &siga1); + halbb_set_bit(10, 3, out_plcp->usr[0].nsts-1, &siga1); // NSS // + halbb_set_bit(13, 9, in->usr[0].aid, &siga1); // AID // + halbb_set_bit(22, 1, in->vht_txop_not_allowed, &siga1); + halbb_set_bit(23, 1, 1, &siga1); + /*=== SIG-A2 ===*/ + if (out_plcp->gi == 0) + halbb_set_bit(0, 1, 1, &siga2); // Short GI // + else + halbb_set_bit(0, 1, 0, &siga2); + halbb_set_bit(1, 1, out_plcp->disamb, &siga2); + halbb_set_bit(2, 1, out_plcp->usr[0].fec, &siga2); + halbb_set_bit(3, 1, out_plcp->ldpc_extra, &siga2); + halbb_set_bit(4, 4, in->usr[0].mcs, &siga2); + halbb_set_bit(8, 1, 0, &siga2);//Beamformed? // + halbb_set_bit(9, 1, 1, &siga2);// rsvd // + //CRC8// + //--- Set HTSIG1 --- + for(i = 0; i < 24; i++) + siga_bits[i] = ( siga1 >> i ) & 0x1 ; + + for(i = 0; i < 10; i++) + siga_bits[i+24] = ( siga2 >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, siga_bits, 34); + halbb_set_bit(10, 8, crc8_out, &siga2); + halbb_set_bit(18, 6, 0, &siga2); + } + else if (in->ppdu_type == HT_MF_FMT) {// HT_MF SIG-A // + /*=== SIG-A1 ===*/ + halbb_set_bit(0, 7, in->usr[0].mcs, &siga1); + halbb_set_bit(7, 1, in->dbw, &siga1); + halbb_set_bit(8, 16, out_plcp->usr[0].apep_len, &siga1); + /*=== SIG-A2 ===*/ + halbb_set_bit(0, 1, 1, &siga2); + halbb_set_bit(1, 1, ~in->ndp_en, &siga2); + halbb_set_bit(2, 1, 1, &siga2); + halbb_set_bit(3, 1, out_plcp->usr[0].n_mpdu > 1 ? 1 : 0, &siga2); + halbb_set_bit(4, 2, out_plcp->usr[0].nsts - out_plcp->usr[0].nss, &siga2); + halbb_set_bit(6, 1, out_plcp->usr[0].fec, &siga2); + if (out_plcp->gi == 0) + halbb_set_bit(7, 1, 1, &siga2); + else + halbb_set_bit(7, 1, 0, &siga2); + halbb_set_bit(8, 2, in->ness, &siga2); + //CRC8// + //--- Set HTSIG1 --- + for(i = 0; i < 24; i++) + siga_bits[i] = ( siga1 >> i ) & 0x1 ; + //--- Set HTSIG2 --- + for(i = 0; i < 10; i++) + siga_bits[i+24] = ( siga2 >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, siga_bits, 34); + halbb_set_bit(10, 8, crc8_out, &siga2); + halbb_set_bit(18, 6, 0, &siga2); + } + /*=== Write CR ===*/ + halbb_set_reg_cmn(bb, cr->siga1, cr->siga1_m, siga1, phy_idx); + halbb_set_reg_cmn(bb, cr->siga2, cr->siga2_m, siga2, phy_idx); +} + + +void halbb_cfg_txinfo(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx) +{ + u8 txinfo_ppdu = 0; + u8 ch20_with_data = 0; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + halbb_set_reg_cmn(bb, cr->cfo_comp, cr->cfo_comp_m, 7, phy_idx); + halbb_set_reg_cmn(bb, cr->obw_cts2self_dup_type, cr->obw_cts2self_dup_type_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->txcmd_txtp, cr->txcmd_txtp_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->ul_cqi_rpt_tri, cr->ul_cqi_rpt_tri_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->rf_fixed_gain_en, cr->rf_fixed_gain_en_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->rf_gain_idx, cr->rf_gain_idx_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->cca_pw_th_en, cr->cca_pw_th_en_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->cca_pw_th, cr->cca_pw_th_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->ant_sel_a, cr->ant_sel_a_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->ant_sel_b, cr->ant_sel_b_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->ant_sel_c, cr->ant_sel_c_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->ant_sel_d, cr->ant_sel_d_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->dbw_idx, cr->dbw_idx_m, in->dbw, phy_idx); + halbb_set_reg_cmn(bb, cr->txsc, cr->txsc_m, in->txsc, phy_idx); + halbb_set_reg_cmn(bb, cr->source_gen_mode_idx, cr->source_gen_mode_idx_m, in->source_gen_mode, phy_idx); + // 'b"[7:0] means whether the corresponding channel20 contains legacy portion data in DBW + if (in->ppdu_type == HE_TB_FMT) { + switch (in->dbw) { + case 0: + if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40) + || (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61) + ch20_with_data = 0x80; + break; + + case 1: + if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40) + || (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61) + ch20_with_data = 0x80; + + else if (((in->usr[0].ru_alloc >> 1) >= 9 && (in->usr[0].ru_alloc >> 1) <= 17) || ((in->usr[0].ru_alloc >> 1) >= 41 && (in->usr[0].ru_alloc >> 1) <= 44) + || (in->usr[0].ru_alloc >> 1) == 55 || (in->usr[0].ru_alloc >> 1) == 56 || (in->usr[0].ru_alloc >> 1) == 62) + ch20_with_data = 0x40; + + else if ((in->usr[0].ru_alloc >> 1) == 65) + ch20_with_data = 0xc0; + + break; + + case 2: + if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40) + || (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61) + ch20_with_data = 0x80; + + else if (((in->usr[0].ru_alloc >> 1) >= 10 && (in->usr[0].ru_alloc >> 1) <= 17) || ((in->usr[0].ru_alloc >> 1) >= 42 && (in->usr[0].ru_alloc >> 1) <= 44) + || (in->usr[0].ru_alloc >> 1) == 56) + ch20_with_data = 0x40; + + else if ((in->usr[0].ru_alloc >> 1) == 9 || (in->usr[0].ru_alloc >> 1) == 41 || (in->usr[0].ru_alloc >> 1) == 55 || (in->usr[0].ru_alloc >> 1) == 62 || (in->usr[0].ru_alloc >> 1) == 65) + ch20_with_data = 0xc0; + + else if (((in->usr[0].ru_alloc >> 1) >= 19 && (in->usr[0].ru_alloc >> 1) <= 26) || ((in->usr[0].ru_alloc >> 1) >= 45 && (in->usr[0].ru_alloc >> 1) <= 47) + || (in->usr[0].ru_alloc >> 1) == 57) + ch20_with_data = 0x20; + + else if (((in->usr[0].ru_alloc >> 1) >= 28 && (in->usr[0].ru_alloc >> 1) <= 36) || ((in->usr[0].ru_alloc >> 1) >= 49 && (in->usr[0].ru_alloc >> 1) <= 52) + || (in->usr[0].ru_alloc >> 1) == 59 || (in->usr[0].ru_alloc >> 1) == 60 || (in->usr[0].ru_alloc >> 1) == 64) + ch20_with_data = 0x10; + + else if ((in->usr[0].ru_alloc >> 1) == 27 || (in->usr[0].ru_alloc >> 1) == 48 || (in->usr[0].ru_alloc >> 1) == 58 || (in->usr[0].ru_alloc >> 1) == 63 || (in->usr[0].ru_alloc >> 1) == 66) + ch20_with_data = 0x30; + + else if ((in->usr[0].ru_alloc >> 1) == 18) + ch20_with_data = 0x60; + + else if ((in->usr[0].ru_alloc >> 1) == 67) + ch20_with_data = 0xf0; + + break; + default: + break; + } + } else { + switch (in->dbw) { + case 0: + ch20_with_data = 0x80; + break; + case 1: + ch20_with_data = 0xc0; + break; + case 2: + ch20_with_data = 0xf0; + break; + case 3: + ch20_with_data = 0xff; + break; + default: + break; + } + } + halbb_set_reg_cmn(bb, cr->ch20_with_data, cr->ch20_with_data_m, ch20_with_data, phy_idx); + + switch(in->ppdu_type) { + case B_MODE_FMT: //CCK + if (in->long_preamble_en) + txinfo_ppdu = 0; + else + txinfo_ppdu = 1; + break; + case LEGACY_FMT: //Legacy + txinfo_ppdu = 2; + break; + case HT_MF_FMT: //HT_MF + txinfo_ppdu = 3; + break; + case HT_GF_FMT: //HT_GF + txinfo_ppdu = 4; + break; + case VHT_FMT: //VHT + txinfo_ppdu = 5; + break; + case HE_SU_FMT: //HE_SU + txinfo_ppdu = 7; + break; + case HE_ER_SU_FMT: //HE_ER_SU + txinfo_ppdu = 8; + break; + case HE_MU_FMT: //HE_MU + txinfo_ppdu = 9; + break; + case HE_TB_FMT: //HE_TB + txinfo_ppdu = 10; + break; + default: + break; + } + halbb_set_reg_cmn(bb, cr->ppdu_type, cr->ppdu_type_m, txinfo_ppdu, phy_idx); + if (in->ppdu_type == B_MODE_FMT) + halbb_set_reg_cmn(bb, cr->n_usr, cr->n_usr_m, in->n_user, phy_idx); + else + halbb_set_reg_cmn(bb, cr->n_usr, cr->n_usr_m, out_plcp->n_usr, phy_idx); +} + +void halbb_cfg_txctrl(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx)//Add random value +{ + u8 i = 0; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + u32 pw_boost_fac[4] = {cr->usr0_pw_boost_fctr_db, cr->usr1_pw_boost_fctr_db, + cr->usr2_pw_boost_fctr_db, cr->usr3_pw_boost_fctr_db}; + u32 pw_boost_fac_m[4] = {cr->usr0_pw_boost_fctr_db_m ,cr->usr1_pw_boost_fctr_db_m, + cr->usr2_pw_boost_fctr_db_m, cr->usr3_pw_boost_fctr_db_m}; + u32 dcm_en[4] = {cr->usr0_dcm_en, cr->usr1_dcm_en, cr->usr2_dcm_en, + cr->usr3_dcm_en}; + u32 dcm_en_m[4] = {cr->usr0_dcm_en_m, cr->usr1_dcm_en_m, cr->usr2_dcm_en_m, + cr->usr3_dcm_en_m}; + u32 mcs[4] = {cr->usr0_mcs, cr->usr1_mcs, cr->usr2_mcs, cr->usr3_mcs}; + u32 mcs_m[4] = {cr->usr0_mcs_m, cr->usr1_mcs_m, cr->usr2_mcs_m, cr->usr3_mcs_m}; + u32 fec[4] = {cr->usr0_fec_type, cr->usr1_fec_type, cr->usr2_fec_type, cr->usr3_fec_type}; + u32 fec_m[4] = {cr->usr0_fec_type_m, cr->usr1_fec_type_m, cr->usr2_fec_type_m, cr->usr3_fec_type_m}; + u32 n_sts[4] = {cr->usr0_n_sts, cr->usr1_n_sts, cr->usr2_n_sts, cr->usr3_n_sts}; + u32 n_sts_m[4] = {cr->usr0_n_sts_m, cr->usr1_n_sts_m, cr->usr2_n_sts_m, cr->usr3_n_sts_m}; + u32 n_sts_ru_tot[4] = {cr->usr0_n_sts_ru_tot, cr->usr1_n_sts_ru_tot, + cr->usr2_n_sts_ru_tot, cr->usr3_n_sts_ru_tot}; + u32 n_sts_ru_tot_m[4] = {cr->usr0_n_sts_ru_tot_m, cr->usr1_n_sts_ru_tot_m, + cr->usr2_n_sts_ru_tot_m, cr->usr3_n_sts_ru_tot_m}; + u32 ru_alloc[4] = {cr->usr0_ru_alloc, cr->usr1_ru_alloc, cr->usr2_ru_alloc, + cr->usr3_ru_alloc}; + u32 ru_alloc_m[4] = {cr->usr0_ru_alloc_m, cr->usr1_ru_alloc_m, cr->usr2_ru_alloc_m, + cr->usr3_ru_alloc_m}; + u32 txbf_en[4] = {cr->usr0_txbf_en, cr->usr1_txbf_en, cr->usr2_txbf_en, + cr->usr3_txbf_en}; + u32 txbf_en_m[4] = {cr->usr0_txbf_en_m, cr->usr1_txbf_en_m, cr->usr2_txbf_en_m, + cr->usr3_txbf_en_m}; + u32 precoding_mode_idx[4] = {cr->usr0_precoding_mode_idx, cr->usr1_precoding_mode_idx, + cr->usr2_precoding_mode_idx, cr->usr3_precoding_mode_idx}; + u32 precoding_mode_idx_m[4] = {cr->usr0_precoding_mode_idx_m, cr->usr1_precoding_mode_idx_m, + cr->usr2_precoding_mode_idx_m, cr->usr3_precoding_mode_idx_m}; + u32 csi_buf_id[4] = {cr->usr0_csi_buf_id, cr->usr1_csi_buf_id, cr->usr2_csi_buf_id, + cr->usr3_csi_buf_id}; + u32 csi_buf_id_m[4] = {cr->usr0_csi_buf_id_m, cr->usr1_csi_buf_id_m, + cr->usr2_csi_buf_id_m, cr->usr3_csi_buf_id_m}; + u32 strt_sts[4] = {cr->usr0_strt_sts, cr->usr1_strt_sts, cr->usr2_strt_sts, + cr->usr3_strt_sts}; + u32 strt_sts_m[4] = {cr->usr0_strt_sts_m, cr->usr1_strt_sts_m, cr->usr2_strt_sts_m, + cr->usr3_strt_sts_m}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // Default value // + // When HE_TB NDP, it's valid; o.w., it's RSVD and set to 1'b0 + halbb_set_reg_cmn(bb, cr->feedback_status, cr->feedback_status_m, 0, phy_idx); + // Whether this PPDU contains data field or not. 0: with data field, 1:without data field + halbb_set_reg_cmn(bb, cr->ndp, cr->ndp_m, 0, phy_idx); + // it's RSVD except HE PPDU and set to 1'b0 when it's RSVD 0: disable MU-MIMO-LTF-Mode, 1: enable MU-MIMO-LTF-Mode + halbb_set_reg_cmn(bb, cr->mumimo_ltf_mode_en, cr->mumimo_ltf_mode_en_m, 0, phy_idx); + // it's RSVD except VHT_MU and HE_MU. When it's RSVD, it shall be set to 1'b0 0: non-full-bandwidth-MU-MIMO, 1: full-bandwidth-MU-MIMO + halbb_set_reg_cmn(bb, cr->fb_mumimo_en, cr->fb_mumimo_en_m, 0, phy_idx); + + // usr value // + // U_ID + halbb_set_reg_cmn(bb, cr->usr0_u_id, cr->usr0_u_id_m, 0, phy_idx); + halbb_set_reg_cmn(bb, cr->usr1_u_id, cr->usr1_u_id_m, 1, phy_idx); + halbb_set_reg_cmn(bb, cr->usr2_u_id, cr->usr2_u_id_m, 2, phy_idx); + halbb_set_reg_cmn(bb, cr->usr3_u_id, cr->usr3_u_id_m, 3, phy_idx); + + // Input Interface // + // When HE_MU, whether to apply DCM is HE-SIGB or not; o.w., it's RSVD and set to 1'b0 + if (in->ppdu_type != HE_MU_FMT) + halbb_set_reg_cmn(bb, cr->he_sigb_dcm_en, cr->he_sigb_dcm_en_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->he_sigb_dcm_en, cr->he_sigb_dcm_en_m, in->he_dcm_sigb, phy_idx);//0: disable, 1:enable + + // When HE_MU, the MCS for HE-SIGB or not; o.w., it's RSVD and set to 3'b0 + if (in->ppdu_type != HE_MU_FMT) + halbb_set_reg_cmn(bb, cr->he_sigb_mcs, cr->he_sigb_mcs_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->he_sigb_mcs, cr->he_sigb_mcs_m, in->he_mcs_sigb, phy_idx); + + // When HE_SU or HE_ER_SU, it means whether to apply beam_change or not; o.w. it's RSVD and set to 1'b1 for OFDM and set to 1'b0 for b_mode. + if (in->ppdu_type == B_MODE_FMT) + halbb_set_reg_cmn(bb, cr->beam_change_en, cr->beam_change_en_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->beam_change_en, cr->beam_change_en_m, in->beamchange_en, phy_idx); + + // The number of LTF. The definition is on the right-hand side. it's RSVD when b_mode and Legacy. When it's RSVD, it shall be set to 3'b0. + if (in->ppdu_type == B_MODE_FMT || in->ppdu_type == LEGACY_FMT) + halbb_set_reg_cmn(bb, cr->n_ltf, cr->n_ltf_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->n_ltf, cr->n_ltf_m, out_plcp->n_ltf, phy_idx); + + // 0: LTF_type1x, 1: LTF_type2x, 2: LTF_type4x, 3:RSVD + if (in->ppdu_type < HE_SU_FMT) + halbb_set_reg_cmn(bb, cr->ltf_type, cr->ltf_type_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->ltf_type, cr->ltf_type_m, in->he_ltf_type, phy_idx); + + // 0: GI_0p4us, 1: GI_0p8us, 2:GI_1p6us, 3:GI_3p2us + if (in->ppdu_type == B_MODE_FMT) + halbb_set_reg_cmn(bb, cr->gi_type, cr->gi_type_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->gi_type, cr->gi_type_m, out_plcp->gi, phy_idx); + + // it's RSVD except HE PPDU when Doppler=enable. When it's RSVD, it shall be set to 1'b0 + if (!((in->ppdu_type > VHT_FMT) && out_plcp->doppler_en)) + halbb_set_reg_cmn(bb, cr->midamble_mode, cr->midamble_mode_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->midamble_mode, cr->midamble_mode_m, out_plcp->midamble, phy_idx); + + // it's RSVD expect HE PPDU. It shall be set to 1'b0 + if (in->ppdu_type < HE_SU_FMT) + halbb_set_reg_cmn(bb, cr->doppler_en, cr->doppler_en_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->doppler_en, cr->doppler_en_m, out_plcp->doppler_en, phy_idx); + + // It's RSVD when b_mode and Legacy, and shall be set to 1'b0. For 8852A, STBC only support NSS * 2 = NSTS + if (in->ppdu_type == B_MODE_FMT || in->ppdu_type == LEGACY_FMT) + halbb_set_reg_cmn(bb, cr->stbc_en, cr->stbc_en_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->stbc_en, cr->stbc_en_m, out_plcp->stbc, phy_idx); + + // usr0 value // + // The power boost factor applied in corresponding RU in pwr. S(5,2) + // Initialize + for (i = 0; i < 4; i++) { + halbb_set_reg_cmn(bb, pw_boost_fac[i], pw_boost_fac_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, dcm_en[i], dcm_en_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, mcs[i], mcs_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, fec[i], fec_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, n_sts[i], n_sts_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, n_sts_ru_tot[i], n_sts_ru_tot_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], 0, phy_idx); + // Txbf + if (bb->ic_type == BB_RTL8852A || bb->ic_type == BB_RTL8852B) + halbb_set_reg_cmn(bb, txbf_en[i], txbf_en_m[i], 0, phy_idx); + else + halbb_set_reg_cmn(bb, precoding_mode_idx[i], precoding_mode_idx_m[i], 0, phy_idx); + // CSI buf_id + halbb_set_reg_cmn(bb, csi_buf_id[i], csi_buf_id_m[i], 0, phy_idx); + // Strt sts + halbb_set_reg_cmn(bb, strt_sts[i], strt_sts_m[i], 0, phy_idx); + } + + for (i = 0; i < in->n_user; i++) { + halbb_set_reg_cmn(bb, pw_boost_fac[i], pw_boost_fac_m[i], in->usr[i].pwr_boost_db, phy_idx); + + // Whether the user applies DCM; it's RSVD when STBC or MU-MIMO + if (!out_plcp->stbc) // if (!STBC) + halbb_set_reg_cmn(bb, dcm_en[i], dcm_en_m[i], out_plcp->usr[i].dcm, phy_idx); + + // The modulation and coding scheme applied to the user.For 8852A, HT(0~31), VHT/HE(0~11), OFDM(0~8), bmode(0~3); otherwise, it's RSVD + halbb_set_reg_cmn(bb, mcs[i], mcs_m[i], in->usr[i].mcs, phy_idx); + + // 0: BCC, 1:LDPC + if (in->ppdu_type == B_MODE_FMT) + halbb_set_reg_cmn(bb, fec[i], fec_m[i], 0, phy_idx); + else + halbb_set_reg_cmn(bb, fec[i], fec_m[i], out_plcp->usr[i].fec, phy_idx); + + // The number of space-time-stream + halbb_set_reg_cmn(bb, n_sts[i], n_sts_m[i], out_plcp->usr[i].nsts - 1, phy_idx); + + // N_STS_RU_total - 1 + halbb_set_reg_cmn(bb, n_sts_ru_tot[i], n_sts_ru_tot_m[i], out_plcp->usr[i].nsts - 1, phy_idx); + + // For all PPDU excepts HE_SU, HE_ER_SU, HE_MU, HE_TB, are RSVD and shall be set to 8'b0 + if (in->ppdu_type < HE_SU_FMT) + halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], 0, phy_idx); + else + halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], in->usr[i].ru_alloc, phy_idx); + } + + // it's RSVD except HE PPDU and shall be set to 2'b0 + if (in->ppdu_type < HE_SU_FMT) + halbb_set_reg_cmn(bb, cr->pre_fec_fctr, cr->pre_fec_fctr_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->pre_fec_fctr, cr->pre_fec_fctr_m, out_plcp->pre_fec_padding_factor, phy_idx); + + // it's RSVD except HE-PPDU and shall be set to 2'b0. it means the duration for packet extension field + if (in->ppdu_type < HE_SU_FMT) + halbb_set_reg_cmn(bb, cr->pkt_ext_idx, cr->pkt_ext_idx_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->pkt_ext_idx, cr->pkt_ext_idx_m, out_plcp->t_pe, phy_idx); + + // 0: without LDPC extra, 1: with LDPC extra + halbb_set_reg_cmn(bb, cr->ldpc_extr, cr->ldpc_extr_m, out_plcp->ldpc_extra, phy_idx); + + // The number of data symbols in HE-SIGB. It is RSVD except HE_MU and shall be set to 6'b0 + if (in->ppdu_type != HE_MU_FMT) + halbb_set_reg_cmn(bb, cr->n_sym_hesigb, cr->n_sym_hesigb_m, 0, phy_idx); + else + halbb_set_reg_cmn(bb, cr->n_sym_hesigb, cr->n_sym_hesigb_m, out_plcp->n_sym_hesigb, phy_idx); + + // It means the number of data symbols in data_field, which the number of midamble symbols are excluded + halbb_set_reg_cmn(bb, cr->n_sym, cr->n_sym_m, out_plcp->n_sym, phy_idx); +} + +void halbb_plcp_delimiter(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx) //Add random value +{ + u8 crc8_out = 0; + u16 tmp = 0; + u32 delimiter = 0; + unsigned char delimiter_crc[32] = {0}; + u8 i = 0; + u8 j = 0; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + u32 delmter[4] = {cr->usr0_delmter, cr->usr1_delmter, cr->usr2_delmter, + cr->usr3_delmter}; + u32 delmter_m[4] = {cr->usr0_delmter_m, cr->usr1_delmter_m, + cr->usr2_delmter_m, cr->usr3_delmter_m}; + u32 mpdu_len[4] = {cr->usr0_mdpu_len_byte, cr->usr1_mdpu_len_byte, + cr->usr2_mdpu_len_byte, cr->usr3_mdpu_len_byte}; + u32 mpdu_len_m[4] = {cr->usr0_mdpu_len_byte_m, cr->usr1_mdpu_len_byte_m, + cr->usr2_mdpu_len_byte_m, cr->usr3_mdpu_len_byte_m}; + u32 n_mpdu[4] = {cr->usr0_n_mpdu, cr->usr1_n_mpdu, cr->usr2_n_mpdu, + cr->usr3_n_mpdu}; + u32 n_mpdu_m[4] = {cr->usr0_n_mpdu_m, cr->usr1_n_mpdu_m, cr->usr2_n_mpdu_m, + cr->usr3_n_mpdu_m}; + u32 eof_padding_len[4] = {cr->usr0_eof_padding_len, cr->usr1_eof_padding_len, + cr->usr2_eof_padding_len, cr->usr3_eof_padding_len}; + u32 eof_padding_len_m[4] = {cr->usr0_eof_padding_len_m, cr->usr1_eof_padding_len_m, + cr->usr2_eof_padding_len_m, cr->usr3_eof_padding_len_m}; + u32 init_seed[4] = {cr->usr0_init_seed, cr->usr1_init_seed, + cr->usr2_init_seed, cr->usr3_init_seed}; + u32 init_seed_m[4] = {cr->usr0_init_seed_m, cr->usr1_init_seed_m, + cr->usr2_init_seed_m, cr->usr3_init_seed_m}; + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + // Initialize + for (i = 0; i < 4; i++) { + halbb_set_reg_cmn(bb, delmter[i], delmter_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, mpdu_len[i], mpdu_len_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, n_mpdu[i], n_mpdu_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, eof_padding_len[i], eof_padding_len_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, init_seed[i], init_seed_m[i], 0, phy_idx); + } + + for (i = 0; i < in->n_user; i++) { + //=== [Delimiter] ===// + if (out_plcp->usr[i].n_mpdu == 1) + halbb_set_bit(0, 1, 1, &delimiter); + else + halbb_set_bit(0, 1, 0, &delimiter); + halbb_set_bit(1, 1, 0, &delimiter); //rsvd + halbb_set_bit(2, 2, out_plcp->usr[i].mpdu_length_byte >> 12, &delimiter); + tmp = out_plcp->usr[i].mpdu_length_byte & 0xfff; + halbb_set_bit(4, 12, tmp, &delimiter); + //CRC8// + //--- Set Delimiter --- + for(j = 0; j < 16; j++) + delimiter_crc[j] = ( delimiter >> j ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, delimiter_crc, 16); + halbb_set_bit(16, 8, crc8_out, &delimiter); + halbb_set_bit(24, 8, 0x4e, &delimiter); // MSB [01001110] LSB + /*=== Write CR ===*/ + halbb_set_reg_cmn(bb, delmter[i], delmter_m[i], delimiter, phy_idx); + //=== [MPDU Length] ===// + halbb_set_reg_cmn(bb, mpdu_len[i], mpdu_len_m[i], out_plcp->usr[i].mpdu_length_byte, phy_idx); + //=== [N_MPDU] ===// + halbb_set_reg_cmn(bb, n_mpdu[i], n_mpdu_m[i], out_plcp->usr[i].n_mpdu, phy_idx); + //=== [EOF Padding Length] ===// + halbb_set_reg_cmn(bb, eof_padding_len[i], eof_padding_len_m[i], out_plcp->usr[i].eof_padding_length * 8, phy_idx); + //=== [Init seed] ===// + halbb_set_reg_cmn(bb, init_seed[i], init_seed_m[i], in->usr[i].random_init_seed, phy_idx); + } +} + +void halbb_cfg_cck(struct bb_info *bb, struct halbb_plcp_info *in, enum phl_phy_idx phy_idx) +{ + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + if (bb->ic_type == BB_RTL8852A || bb->ic_type == BB_RTL8852B) { + // === 11b_tx_pmac_psdu_byte === // + halbb_set_reg(bb, cr->b_psdu_byte, cr->b_psdu_byte_m, in->usr[0].apep); + // === 11b_tx_pmac_psdu_type === // + halbb_set_reg(bb, cr->b_ppdu_type, cr->b_ppdu_type_m, ~in->long_preamble_en); + // === 11b_tx_pmac_psdu_rate === // + halbb_set_reg(bb, cr->b_psdu_rate, cr->b_psdu_rate_m, in->usr[0].mcs); + // === 11b_tx_pmac_service_bit2 === // + halbb_set_reg(bb, cr->b_service_bit2, cr->b_service_bit2_m, 1); + } else { + // === 11b_tx_pmac_psdu_byte === // + halbb_set_reg_cmn(bb, cr->usr0_mdpu_len_byte, cr->usr0_mdpu_len_byte_m, in->usr[0].apep, phy_idx); + // === 11b_tx_pmac_psdu_type === // + halbb_set_reg_cmn(bb, cr->ppdu_type, cr->ppdu_type_m, ~in->long_preamble_en, phy_idx); + // === 11b_tx_pmac_psdu_rate === // + halbb_set_reg(bb, cr->b_rate_idx, cr->b_rate_idx_m, in->usr[0].mcs); + // === 11b_tx_pmac_service_bit2 === // + halbb_set_reg(bb, cr->b_locked_clk_en, cr->b_locked_clk_en_m, 1); + } + // === 11b_tx_pmac_carrier_suppress_tx === // + halbb_set_reg(bb, cr->b_carrier_suppress_tx, cr->b_carrier_suppress_tx_m, 0); + // === 11b_tx_pmac_psdu_header === // + halbb_set_reg(bb, cr->b_header_0, cr->b_header_0_m, 0x3020100); + halbb_set_reg(bb, cr->b_header_1, cr->b_header_1_m, 0x7060504); + halbb_set_reg(bb, cr->b_header_2, cr->b_header_2_m, 0xb0a0908); + halbb_set_reg(bb, cr->b_header_3, cr->b_header_3_m, 0xf0e0d0c); + halbb_set_reg(bb, cr->b_header_4, cr->b_header_4_m, 0x13121110); + halbb_set_reg(bb, cr->b_header_5, cr->b_header_5_m, 0x17161514); +} + +void halbb_vht_sigb(struct bb_info *bb, struct halbb_plcp_info *in, + struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp, + enum phl_phy_idx phy_idx) +{ + // VHT SU + u8 crc8_out = 0; + u8 scrambler_seed = 0; + u32 vht_sigb = 0; + unsigned char sigb[32] = {0}; + u8 i = 0; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + u32 vht_sigb_cr[4] = {cr->vht_sigb0, cr->vht_sigb1, cr->vht_sigb2, + cr->vht_sigb3}; + u32 vht_sigb_cr_m[4] = {cr->vht_sigb0_m, cr->vht_sigb1_m, cr->vht_sigb2_m, + cr->vht_sigb3_m}; + u32 service[4] = {cr->usr0_service, cr->usr1_service, cr->usr2_service, + cr->usr3_service}; + u32 service_m[4] = {cr->usr0_service_m, cr->usr1_service_m, + cr->usr2_service_m, cr->usr3_service_m}; + + // Initialize + for (i = 0; i < 4; i++) { + halbb_set_reg_cmn(bb, vht_sigb_cr[i], vht_sigb_cr_m[i], 0, phy_idx); + halbb_set_reg_cmn(bb, service[i], service_m[i], 0, phy_idx); + } + switch (in->dbw) {//0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 + case 0: + halbb_set_bit(0, 17, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb); + halbb_set_bit(17, 3, 0x7, &vht_sigb); + //--- Set VHT SigB --- + for(i = 0; i < 20; i++) + sigb[i] = ( vht_sigb >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, sigb, 20); + halbb_set_bit(20, 6, 0x0, &vht_sigb); + break; + case 1: + halbb_set_bit(0, 19, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb); + halbb_set_bit(19, 2, 0x3, &vht_sigb); + //--- Set VHT SigB --- + for(i = 0; i < 21; i++) + sigb[i] = ( vht_sigb >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, sigb, 21); + halbb_set_bit(21, 6, 0x0, &vht_sigb); + break; + case 2: + case 3: + halbb_set_bit(0, 21, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb); + halbb_set_bit(21, 2, 0x3, &vht_sigb); + //--- Set VHT SigB --- + for(i = 0; i < 23; i++) + sigb[i] = ( vht_sigb >> i ) & 0x1 ; + crc8_out = halbb_set_crc8(bb, sigb, 23); + halbb_set_bit(23, 6, 0x0, &vht_sigb); + break; + default: + break; + } + //=== [Service] ===// + scrambler_seed = in->usr[0].scrambler_seed & 0x7f; + + halbb_set_reg_cmn(bb, service[0], service_m[0], (crc8_out << 8) + scrambler_seed, phy_idx); + halbb_set_reg_cmn(bb, vht_sigb_cr[0], vht_sigb_cr_m[0], vht_sigb, phy_idx); +} + +void halbb_service(struct bb_info *bb, struct halbb_plcp_info *in, + enum phl_phy_idx phy_idx) +{ + u8 i = 0; + u32 scrambler_seed[4] = {0}; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + u32 service[4] = {cr->usr0_service, cr->usr1_service, cr->usr2_service, + cr->usr3_service}; + u32 service_m[4] = {cr->usr0_service_m, cr->usr1_service_m, + cr->usr2_service_m, cr->usr3_service_m}; + + for (i = 0; i < 4; i++) + halbb_set_reg_cmn(bb, service[i], service_m[i], 0, phy_idx); + for(i = 0; i < in->n_user; i++) { + //=== [Service] ===// + scrambler_seed[i] = in->usr[i].scrambler_seed & 0x7f; + halbb_set_reg_cmn(bb, service[i], service_m[i], scrambler_seed[i], phy_idx); + } +} + +void halbb_he_sigb(struct bb_info *bb, struct halbb_plcp_info *in, + enum phl_phy_idx phy_idx) +{ + struct bb_h2c_he_sigb *he_sigb = &bb->bb_h2c_he_sigb_i; + u8 i = 0; + u16 cmdlen; + bool ret_val = false; + u32 *bb_h2c = (u32 *)he_sigb; + + struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i; + + u32 n_sym_sigb_ch1_phy0[16] = {cr->he_sigb_ch1_0, cr->he_sigb_ch1_1, + cr->he_sigb_ch1_2, cr->he_sigb_ch1_3, + cr->he_sigb_ch1_4, cr->he_sigb_ch1_5, + cr->he_sigb_ch1_6, cr->he_sigb_ch1_7, + cr->he_sigb_ch1_8, cr->he_sigb_ch1_9, + cr->he_sigb_ch1_10, cr->he_sigb_ch1_11, + cr->he_sigb_ch1_12, cr->he_sigb_ch1_13, + cr->he_sigb_ch1_14, cr->he_sigb_ch1_15}; + u32 n_sym_sigb_ch2_phy0[16] = {cr->he_sigb_ch2_0, cr->he_sigb_ch2_1, + cr->he_sigb_ch2_2, cr->he_sigb_ch2_3, + cr->he_sigb_ch2_4, cr->he_sigb_ch2_5, + cr->he_sigb_ch2_6, cr->he_sigb_ch2_7, + cr->he_sigb_ch2_8, cr->he_sigb_ch2_9, + cr->he_sigb_ch2_10, cr->he_sigb_ch2_11, + cr->he_sigb_ch2_12, cr->he_sigb_ch2_13, + cr->he_sigb_ch2_14, cr->he_sigb_ch2_15}; + + for (i = 0; i < 16; i++) { + halbb_set_reg(bb, n_sym_sigb_ch1_phy0[i], MASKDWORD, 0); + halbb_set_reg(bb, n_sym_sigb_ch2_phy0[i], MASKDWORD, 0); + } + + if (phy_idx == HW_PHY_0) { + for (i = 0; i < 16; i++) { + he_sigb->n_sym_sigb_ch1[i].address= n_sym_sigb_ch1_phy0[i]; + he_sigb->n_sym_sigb_ch2[i].address = n_sym_sigb_ch2_phy0[i]; + } + } /*else { + for (i = 0; i < 16; i++) { + he_sigb->n_sym_sigb_ch1[i] = n_sym_sigb_ch1_phy1[i]; + he_sigb->n_sym_sigb_ch2[i] = n_sym_sigb_ch2_phy1[i]; + } + }*/ + + cmdlen = sizeof(struct bb_h2c_he_sigb); + + he_sigb->dl_rua_out.ppdu_bw = (u16)in->dbw; + he_sigb->dl_rua_out.sta_list_num = (u8)in->n_user; + he_sigb->dl_rua_out.fixed_mode = 1; + he_sigb->force_sigb_rate = 1; // Force SIGB MCS & DCM setting + he_sigb->force_sigb_mcs = (u8)in->he_mcs_sigb; + he_sigb->force_sigb_dcm = (u8)in->he_dcm_sigb; + + for (i = 0; i < in->n_user; i++) { + he_sigb->dl_rua_out.dl_output_sta_list[i].dropping_flag = 0; + he_sigb->dl_rua_out.dl_output_sta_list[i].txbf = (u8)in->usr[i].txbf; + he_sigb->dl_rua_out.dl_output_sta_list[i].coding = (u8)in->usr[i].fec; + he_sigb->dl_rua_out.dl_output_sta_list[i].nsts = (u8)(in->usr[i].nss << in->stbc) - 1; + he_sigb->dl_rua_out.dl_output_sta_list[i].mac_id = i; + he_sigb->dl_rua_out.dl_output_sta_list[i].ru_position = (u8)in->usr[i].ru_alloc << 1; + //he_sigb->dl_rua_out.dl_output_sta_list[i].aid = (u16)in->usr[i].aid; + he_sigb->aid12[i] = (u16)in->usr[i].aid; + he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.dcm = (u8)in->usr[i].dcm; + he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.mcs = (u8)in->usr[i].mcs; + he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.ss = (u8)in->usr[i].nss; + } + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_HE_SIGB, + HALBB_H2C_DM, bb_h2c); + /* + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 NSS = %d\n", in->usr[0].nss); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 MCS = %d\n", in->usr[0].mcs); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 AID = %d\n", in->usr[0].aid); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 ru position = %d\n", he_sigb->dl_rua_out.dl_output_sta_list[0].ru_position); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 dropping flag = %d\n", he_sigb->dl_rua_out.dl_output_sta_list[0].dropping_flag); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] SIGB Addr = 0x%x, Mask = 0x%x\n", + he_sigb->n_sym_sigb_ch1[0].address, he_sigb->n_sym_sigb_ch1[0].bitmask); + */ +} + +enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in, + struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx) +{ + u16 i = 0; + u8 he_sigb_c2h[2] = {0}; + bool he_sigb_valid = false; + bool he_sigb_pol = false; + u16 he_n_sigb_sym = 0; + u32 he_sigb_tmp = 0; + + enum plcp_sts tmp = PLCP_SUCCESS; + struct plcp_tx_pre_fec_padding_setting_in_t in_plcp; + struct plcp_tx_pre_fec_padding_setting_out_t out; + //struct _bb_result he_result; + + halbb_mem_cpy(bb, in->usr, user, 4*sizeof(struct usr_plcp_gen_in)); + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + rtw_halbb_plcp_gen_init(in, &in_plcp); + + // HE SIG-B + if (in->ppdu_type == HE_MU_FMT) { + halbb_he_sigb(bb, in, phy_idx); + + for (i = 0; i < 500; i++) { + halbb_delay_us(bb, 10); + he_sigb_pol = (bool)halbb_get_reg(bb, 0xfc, BIT(16)); + if (he_sigb_pol) { + he_sigb_valid = (bool)halbb_get_reg(bb, 0xfc, BIT(8)); + he_n_sigb_sym = (u16)halbb_get_reg(bb, 0xfc, 0x3f); + in_plcp.n_hesigb_sym = he_n_sigb_sym; + break; + } + } + + for (i = 0; i < in->n_user; i++) { + // === Set ru_size_idx === // + if(in->usr[i].ru_alloc < 37) + in_plcp.usr[i].ru_size_idx = 0; + else if(in->usr[i].ru_alloc < 53) + in_plcp.usr[i].ru_size_idx = 1; + else if(in->usr[i].ru_alloc < 61) + in_plcp.usr[i].ru_size_idx = 2; + else if(in->usr[i].ru_alloc < 65) + in_plcp.usr[i].ru_size_idx = 3; + else if(in->usr[i].ru_alloc < 67) + in_plcp.usr[i].ru_size_idx = 4; + else + in_plcp.usr[i].ru_size_idx = 5; + + in->usr[i].ru_alloc = (in->usr[i].ru_alloc << 1); + BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User%d RU_alloc = %d\n", i, in->usr[i].ru_alloc); + } + } + + if (in->ppdu_type == HE_TB_FMT) { + in->n_user = 1; + // === Set ru_size_idx === // + if(in->usr[0].ru_alloc < 37) + in_plcp.usr[0].ru_size_idx = 0; + else if(in->usr[0].ru_alloc < 53) + in_plcp.usr[0].ru_size_idx = 1; + else if(in->usr[0].ru_alloc < 61) + in_plcp.usr[0].ru_size_idx = 2; + else if(in->usr[0].ru_alloc < 65) + in_plcp.usr[0].ru_size_idx = 3; + else if(in->usr[0].ru_alloc < 67) + in_plcp.usr[0].ru_size_idx = 4; + else + in_plcp.usr[0].ru_size_idx = 5; + + in->usr[0].ru_alloc = (in->usr[0].ru_alloc << 1); + } + + // CCK + if (in->ppdu_type == B_MODE_FMT) { + halbb_cfg_cck(bb, in, phy_idx); + if ((in->usr[0].mcs == 0) && (in->long_preamble_en == 0)) + tmp = CCK_INVALID; + } else { + tmp = halbb_tx_plcp_cal(bb, &in_plcp, &out); + // VHT SIG-B + if (in->ppdu_type == VHT_FMT) + halbb_vht_sigb(bb, in, &out, phy_idx); + else + halbb_service(bb, in, phy_idx); + // L-SIG + halbb_plcp_lsig(bb, in, &out, phy_idx); + // SIG-A + if (in->ppdu_type > LEGACY_FMT) + halbb_plcp_siga(bb, in, &out, phy_idx); + // Tx Ctrl Info + halbb_cfg_txctrl(bb, in, &out, phy_idx); + // Delimiter + halbb_plcp_delimiter(bb, in, &out, phy_idx); + } + // Tx Info + halbb_cfg_txinfo(bb, in, &out, phy_idx); + +// === [Global Verification Setting] === // +#ifdef BB_8852A_CAV_SUPPORT + if (bb->ic_type == BB_RTL8852AA) + halbb_plcp_gen_homologation_8852a (bb, in); +#endif +// ===================================== // + return tmp; +} + + +void halbb_cr_cfg_plcp_init(struct bb_info *bb) +{ + struct bb_plcp_info *plcp_info = &bb->bb_plcp_i; + struct bb_plcp_cr_info *cr = &plcp_info->bb_plcp_cr_i; + + switch (bb->cr_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + cr->b_header_0 = R1B_TX_PMAC_HEADER_0_52AA; + cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_52AA_M; + cr->b_header_1 = R1B_TX_PMAC_HEADER_1_52AA; + cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_52AA_M; + cr->b_header_2 = R1B_TX_PMAC_HEADER_2_52AA; + cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_52AA_M; + cr->b_header_3 = R1B_TX_PMAC_HEADER_3_52AA; + cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_52AA_M; + cr->b_header_4 = R1B_TX_PMAC_HEADER_4_52AA; + cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_52AA_M; + cr->b_header_5 = R1B_TX_PMAC_HEADER_5_52AA; + cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_52AA_M; + cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_52AA; + cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_52AA_M; + cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_52AA; + cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_52AA_M; + cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_52AA; + cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_52AA_M; + cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_52AA; + cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_52AA_M; + cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_52AA; + cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_52AA_M; + cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_52AA; + cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_52AA_M; + cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_52AA; + cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_52AA_M; + cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_52AA; + cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_52AA_M; + cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_52AA; + cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_52AA_M; + cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_52AA; + cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_52AA_M; + cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_52AA; + cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_52AA_M; + cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_52AA; + cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_52AA_M; + cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_52AA; + cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_52AA_M; + cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_52AA; + cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_52AA_M; + cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_52AA; + cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_52AA_M; + cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_52AA; + cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_52AA_M; + cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_52AA; + cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_52AA_M; + cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_52AA; + cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_52AA_M; + cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_52AA; + cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_52AA_M; + cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_52AA; + cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_52AA_M; + cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_52AA; + cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_52AA_M; + cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_52AA; + cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_52AA_M; + cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_52AA; + cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_52AA_M; + cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_52AA; + cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_52AA_M; + cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_52AA; + cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_52AA_M; + cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_52AA; + cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_52AA_M; + cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_52AA; + cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_52AA_M; + cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_52AA; + cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_52AA_M; + cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_52AA; + cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_52AA_M; + cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_52AA; + cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_52AA_M; + cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_52AA; + cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_52AA_M; + cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_52AA; + cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_52AA_M; + cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_52AA; + cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_52AA_M; + cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_52AA; + cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_52AA_M; + cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_52AA; + cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_52AA_M; + cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_52AA; + cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_52AA_M; + cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_52AA; + cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_52AA_M; + cr->usr0_delmter = USER0_DELMTER_52AA; + cr->usr0_delmter_m = USER0_DELMTER_52AA_M; + cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_52AA; + cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_52AA_M; + cr->usr0_init_seed = USER0_INIT_SEED_52AA; + cr->usr0_init_seed_m = USER0_INIT_SEED_52AA_M; + cr->usr1_delmter = USER1_DELMTER_52AA; + cr->usr1_delmter_m = USER1_DELMTER_52AA_M; + cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_52AA; + cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_52AA_M; + cr->usr1_init_seed = USER1_INIT_SEED_52AA; + cr->usr1_init_seed_m = USER1_INIT_SEED_52AA_M; + cr->usr2_delmter = USER2_DELMTER_52AA; + cr->usr2_delmter_m = USER2_DELMTER_52AA_M; + cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_52AA; + cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_52AA_M; + cr->usr2_init_seed = USER2_INIT_SEED_52AA; + cr->usr2_init_seed_m = USER2_INIT_SEED_52AA_M; + cr->usr3_delmter = USER3_DELMTER_52AA; + cr->usr3_delmter_m = USER3_DELMTER_52AA_M; + cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_52AA; + cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_52AA_M; + cr->usr3_init_seed = USER3_INIT_SEED_52AA; + cr->usr3_init_seed_m = USER3_INIT_SEED_52AA_M; + cr->vht_sigb0 = TXD_VHT_SIGB0_52AA; + cr->vht_sigb0_m = TXD_VHT_SIGB0_52AA_M; + cr->vht_sigb1 = TXD_VHT_SIGB1_52AA; + cr->vht_sigb1_m = TXD_VHT_SIGB1_52AA_M; + cr->vht_sigb2 = TXD_VHT_SIGB2_52AA; + cr->vht_sigb2_m = TXD_VHT_SIGB2_52AA_M; + cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_52AA; + cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_52AA_M; + cr->vht_sigb3 = TXD_VHT_SIGB3_52AA; + cr->vht_sigb3_m = TXD_VHT_SIGB3_52AA_M; + cr->n_ltf = TXCOMCT_N_LTF_52AA; + cr->n_ltf_m = TXCOMCT_N_LTF_52AA_M; + cr->siga1 = TXD_SIGA1_52AA; + cr->siga1_m = TXD_SIGA1_52AA_M; + cr->siga2 = TXD_SIGA2_52AA; + cr->siga2_m = TXD_SIGA2_52AA_M; + cr->lsig = TXD_LSIG_52AA; + cr->lsig_m = TXD_LSIG_52AA_M; + cr->cca_pw_th = TXINFO_CCA_PW_TH_52AA; + cr->cca_pw_th_m = TXINFO_CCA_PW_TH_52AA_M; + cr->n_sym = TXTIMCT_N_SYM_52AA; + cr->n_sym_m = TXTIMCT_N_SYM_52AA_M; + cr->usr0_service = USER0_SERVICE_52AA; + cr->usr0_service_m = USER0_SERVICE_52AA_M; + cr->usr1_service = USER1_SERVICE_52AA; + cr->usr1_service_m = USER1_SERVICE_52AA_M; + cr->usr2_service = USER2_SERVICE_52AA; + cr->usr2_service_m = USER2_SERVICE_52AA_M; + cr->usr3_service = USER3_SERVICE_52AA; + cr->usr3_service_m = USER3_SERVICE_52AA_M; + cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_52AA; + cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_52AA_M; + cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_52AA; + cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_52AA_M; + cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_52AA; + cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_52AA_M; + cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_52AA; + cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_52AA_M; + cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_52AA; + cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_52AA_M; + cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_52AA; + cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_52AA_M; + cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_52AA; + cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_52AA_M; + cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_52AA; + cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_52AA_M; + cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_52AA; + cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_52AA_M; + cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_52AA; + cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_52AA_M; + cr->usr0_n_mpdu = USER0_N_MPDU_52AA; + cr->usr0_n_mpdu_m = USER0_N_MPDU_52AA_M; + cr->usr1_n_mpdu = USER1_N_MPDU_52AA; + cr->usr1_n_mpdu_m = USER1_N_MPDU_52AA_M; + cr->usr2_n_mpdu = USER2_N_MPDU_52AA; + cr->usr2_n_mpdu_m = USER2_N_MPDU_52AA_M; + cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_52AA; + cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_52AA_M; + cr->usr3_n_mpdu = USER3_N_MPDU_52AA; + cr->usr3_n_mpdu_m = USER3_N_MPDU_52AA_M; + cr->ch20_with_data = TXINFO_CH20_WITH_DATA_52AA; + cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_52AA_M; + cr->n_usr = TXINFO_N_USR_52AA; + cr->n_usr_m = TXINFO_N_USR_52AA_M; + cr->txcmd_txtp = TXINFO_TXCMD_TXTP_52AA; + cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_52AA_M; + cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_52AA; + cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_52AA_M; + cr->usr0_u_id = TXUSRCT0_U_ID_52AA; + cr->usr0_u_id_m = TXUSRCT0_U_ID_52AA_M; + cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_52AA; + cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_52AA_M; + cr->usr1_u_id = TXUSRCT1_U_ID_52AA; + cr->usr1_u_id_m = TXUSRCT1_U_ID_52AA_M; + cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_52AA; + cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_52AA_M; + cr->usr2_u_id = TXUSRCT2_U_ID_52AA; + cr->usr2_u_id_m = TXUSRCT2_U_ID_52AA_M; + cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_52AA; + cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_52AA_M; + cr->usr3_u_id = TXUSRCT3_U_ID_52AA; + cr->usr3_u_id_m = TXUSRCT3_U_ID_52AA_M; + cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_52AA; + cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_52AA_M; + cr->usr0_mcs = TXUSRCT0_MCS_52AA; + cr->usr0_mcs_m = TXUSRCT0_MCS_52AA_M; + cr->usr1_mcs = TXUSRCT1_MCS_52AA; + cr->usr1_mcs_m = TXUSRCT1_MCS_52AA_M; + cr->usr2_mcs = TXUSRCT2_MCS_52AA; + cr->usr2_mcs_m = TXUSRCT2_MCS_52AA_M; + cr->usr3_mcs = TXUSRCT3_MCS_52AA; + cr->usr3_mcs_m = TXUSRCT3_MCS_52AA_M; + cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_52AA; + cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_52AA_M; + cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_52AA; + cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_52AA_M; + cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_52AA; + cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_52AA_M; + cr->ppdu_type = TXINFO_PPDU_TYPE_52AA; + cr->ppdu_type_m = TXINFO_PPDU_TYPE_52AA_M; + cr->txsc = TXINFO_TXSC_52AA; + cr->txsc_m = TXINFO_TXSC_52AA_M; + cr->cfo_comp = TXINFO_CFO_COMP_52AA; + cr->cfo_comp_m = TXINFO_CFO_COMP_52AA_M; + cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_52AA; + cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_52AA_M; + cr->usr0_n_sts = TXUSRCT0_N_STS_52AA; + cr->usr0_n_sts_m = TXUSRCT0_N_STS_52AA_M; + cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_52AA; + cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_52AA_M; + cr->usr0_strt_sts = TXUSRCT0_STRT_STS_52AA; + cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_52AA_M; + cr->usr1_n_sts = TXUSRCT1_N_STS_52AA; + cr->usr1_n_sts_m = TXUSRCT1_N_STS_52AA_M; + cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_52AA; + cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_52AA_M; + cr->usr1_strt_sts = TXUSRCT1_STRT_STS_52AA; + cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_52AA_M; + cr->usr2_n_sts = TXUSRCT2_N_STS_52AA; + cr->usr2_n_sts_m = TXUSRCT2_N_STS_52AA_M; + cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_52AA; + cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_52AA_M; + cr->usr2_strt_sts = TXUSRCT2_STRT_STS_52AA; + cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_52AA_M; + cr->usr3_n_sts = TXUSRCT3_N_STS_52AA; + cr->usr3_n_sts_m = TXUSRCT3_N_STS_52AA_M; + cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_52AA; + cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_52AA_M; + cr->usr3_strt_sts = TXUSRCT3_STRT_STS_52AA; + cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_52AA_M; + cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_52AA; + cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_52AA_M; + cr->gi_type = TXCOMCT_GI_TYPE_52AA; + cr->gi_type_m = TXCOMCT_GI_TYPE_52AA_M; + cr->ltf_type = TXCOMCT_LTF_TYPE_52AA; + cr->ltf_type_m = TXCOMCT_LTF_TYPE_52AA_M; + cr->dbw_idx = TXINFO_DBW_IDX_52AA; + cr->dbw_idx_m = TXINFO_DBW_IDX_52AA_M; + cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_52AA; + cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_52AA_M; + cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_52AA; + cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_52AA_M; + cr->doppler_en = TXCOMCT_DOPPLER_EN_52AA; + cr->doppler_en_m = TXCOMCT_DOPPLER_EN_52AA_M; + cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_52AA; + cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_52AA_M; + cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_52AA; + cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_52AA_M; + cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_52AA; + cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_52AA_M; + cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_52AA; + cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_52AA_M; + cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_52AA; + cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_52AA_M; + cr->ndp = TXCOMCT_NDP_52AA; + cr->ndp_m = TXCOMCT_NDP_52AA_M; + cr->stbc_en = TXCOMCT_STBC_EN_52AA; + cr->stbc_en_m = TXCOMCT_STBC_EN_52AA_M; + cr->ant_sel_a = TXINFO_ANT_SEL_A_52AA; + cr->ant_sel_a_m = TXINFO_ANT_SEL_A_52AA_M; + cr->ant_sel_b = TXINFO_ANT_SEL_B_52AA; + cr->ant_sel_b_m = TXINFO_ANT_SEL_B_52AA_M; + cr->ant_sel_c = TXINFO_ANT_SEL_C_52AA; + cr->ant_sel_c_m = TXINFO_ANT_SEL_C_52AA_M; + cr->ant_sel_d = TXINFO_ANT_SEL_D_52AA; + cr->ant_sel_d_m = TXINFO_ANT_SEL_D_52AA_M; + cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_52AA; + cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_52AA_M; + cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_52AA; + cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_52AA_M; + cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_52AA; + cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_52AA_M; + cr->ldpc_extr = TXTIMCT_LDPC_EXTR_52AA; + cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_52AA_M; + cr->usr0_dcm_en = TXUSRCT0_DCM_EN_52AA; + cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_52AA_M; + cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_52AA; + cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_52AA_M; + cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_52AA; + cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_52AA_M; + cr->usr1_dcm_en = TXUSRCT1_DCM_EN_52AA; + cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_52AA_M; + cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_52AA; + cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_52AA_M; + cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_52AA; + cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_52AA_M; + cr->usr2_dcm_en = TXUSRCT2_DCM_EN_52AA; + cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_52AA_M; + cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_52AA; + cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_52AA_M; + cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_52AA; + cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_52AA_M; + cr->usr3_dcm_en = TXUSRCT3_DCM_EN_52AA; + cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_52AA_M; + cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_52AA; + cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_52AA_M; + cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_52AA; + cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->b_header_0 = R1B_TX_PMAC_HEADER_0_A; + cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_A_M; + cr->b_header_1 = R1B_TX_PMAC_HEADER_1_A; + cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_A_M; + cr->b_header_2 = R1B_TX_PMAC_HEADER_2_A; + cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_A_M; + cr->b_header_3 = R1B_TX_PMAC_HEADER_3_A; + cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_A_M; + cr->b_header_4 = R1B_TX_PMAC_HEADER_4_A; + cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_A_M; + cr->b_header_5 = R1B_TX_PMAC_HEADER_5_A; + cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_A_M; + cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_A; + cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_A_M; + cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A; + cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A_M; + cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_A; + cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_A_M; + cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_A; + cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_A_M; + cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_A; + cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_A_M; + cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_A; + cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_A_M; + cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_A; + cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_A_M; + cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_A; + cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_A_M; + cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_A; + cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_A_M; + cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_A; + cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_A_M; + cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_A; + cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_A_M; + cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_A; + cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_A_M; + cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_A; + cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_A_M; + cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_A; + cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_A_M; + cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_A; + cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_A_M; + cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_A; + cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_A_M; + cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_A; + cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_A_M; + cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_A; + cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_A_M; + cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_A; + cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_A_M; + cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_A; + cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_A_M; + cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_A; + cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_A_M; + cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_A; + cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_A_M; + cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_A; + cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_A_M; + cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_A; + cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_A_M; + cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_A; + cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_A_M; + cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_A; + cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_A_M; + cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_A; + cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_A_M; + cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_A; + cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_A_M; + cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_A; + cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_A_M; + cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_A; + cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_A_M; + cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_A; + cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_A_M; + cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_A; + cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_A_M; + cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_A; + cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_A_M; + cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_A; + cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_A_M; + cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_A; + cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_A_M; + cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_A; + cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_A_M; + cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_A; + cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_A_M; + cr->usr0_delmter = USER0_DELMTER_A; + cr->usr0_delmter_m = USER0_DELMTER_A_M; + cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_A; + cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_A_M; + cr->usr0_init_seed = USER0_INIT_SEED_A; + cr->usr0_init_seed_m = USER0_INIT_SEED_A_M; + cr->usr1_delmter = USER1_DELMTER_A; + cr->usr1_delmter_m = USER1_DELMTER_A_M; + cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_A; + cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_A_M; + cr->usr1_init_seed = USER1_INIT_SEED_A; + cr->usr1_init_seed_m = USER1_INIT_SEED_A_M; + cr->usr2_delmter = USER2_DELMTER_A; + cr->usr2_delmter_m = USER2_DELMTER_A_M; + cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_A; + cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_A_M; + cr->usr2_init_seed = USER2_INIT_SEED_A; + cr->usr2_init_seed_m = USER2_INIT_SEED_A_M; + cr->usr3_delmter = USER3_DELMTER_A; + cr->usr3_delmter_m = USER3_DELMTER_A_M; + cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_A; + cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_A_M; + cr->usr3_init_seed = USER3_INIT_SEED_A; + cr->usr3_init_seed_m = USER3_INIT_SEED_A_M; + cr->vht_sigb0 = TXD_VHT_SIGB0_A; + cr->vht_sigb0_m = TXD_VHT_SIGB0_A_M; + cr->vht_sigb1 = TXD_VHT_SIGB1_A; + cr->vht_sigb1_m = TXD_VHT_SIGB1_A_M; + cr->vht_sigb2 = TXD_VHT_SIGB2_A; + cr->vht_sigb2_m = TXD_VHT_SIGB2_A_M; + cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_A; + cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_A_M; + cr->vht_sigb3 = TXD_VHT_SIGB3_A; + cr->vht_sigb3_m = TXD_VHT_SIGB3_A_M; + cr->n_ltf = TXCOMCT_N_LTF_A; + cr->n_ltf_m = TXCOMCT_N_LTF_A_M; + cr->siga1 = TXD_SIGA1_A; + cr->siga1_m = TXD_SIGA1_A_M; + cr->siga2 = TXD_SIGA2_A; + cr->siga2_m = TXD_SIGA2_A_M; + cr->lsig = TXD_LSIG_A; + cr->lsig_m = TXD_LSIG_A_M; + cr->cca_pw_th = TXINFO_CCA_PW_TH_A; + cr->cca_pw_th_m = TXINFO_CCA_PW_TH_A_M; + cr->n_sym = TXTIMCT_N_SYM_A; + cr->n_sym_m = TXTIMCT_N_SYM_A_M; + cr->usr0_service = USER0_SERVICE_A; + cr->usr0_service_m = USER0_SERVICE_A_M; + cr->usr1_service = USER1_SERVICE_A; + cr->usr1_service_m = USER1_SERVICE_A_M; + cr->usr2_service = USER2_SERVICE_A; + cr->usr2_service_m = USER2_SERVICE_A_M; + cr->usr3_service = USER3_SERVICE_A; + cr->usr3_service_m = USER3_SERVICE_A_M; + cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_A; + cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_A_M; + cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_A; + cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_A_M; + cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_A; + cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_A_M; + cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_A; + cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_A_M; + cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_A; + cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_A_M; + cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_A; + cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_A_M; + cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_A; + cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_A_M; + cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_A; + cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_A_M; + cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_A; + cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_A_M; + cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_A; + cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_A_M; + cr->usr0_n_mpdu = USER0_N_MPDU_A; + cr->usr0_n_mpdu_m = USER0_N_MPDU_A_M; + cr->usr1_n_mpdu = USER1_N_MPDU_A; + cr->usr1_n_mpdu_m = USER1_N_MPDU_A_M; + cr->usr2_n_mpdu = USER2_N_MPDU_A; + cr->usr2_n_mpdu_m = USER2_N_MPDU_A_M; + cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_A; + cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_A_M; + cr->usr3_n_mpdu = USER3_N_MPDU_A; + cr->usr3_n_mpdu_m = USER3_N_MPDU_A_M; + cr->ch20_with_data = TXINFO_CH20_WITH_DATA_A; + cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_A_M; + cr->n_usr = TXINFO_N_USR_A; + cr->n_usr_m = TXINFO_N_USR_A_M; + cr->txcmd_txtp = TXINFO_TXCMD_TXTP_A; + cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_A_M; + cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_A; + cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_A_M; + cr->usr0_u_id = TXUSRCT0_U_ID_A; + cr->usr0_u_id_m = TXUSRCT0_U_ID_A_M; + cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_A; + cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_A_M; + cr->usr1_u_id = TXUSRCT1_U_ID_A; + cr->usr1_u_id_m = TXUSRCT1_U_ID_A_M; + cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_A; + cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_A_M; + cr->usr2_u_id = TXUSRCT2_U_ID_A; + cr->usr2_u_id_m = TXUSRCT2_U_ID_A_M; + cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_A; + cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_A_M; + cr->usr3_u_id = TXUSRCT3_U_ID_A; + cr->usr3_u_id_m = TXUSRCT3_U_ID_A_M; + cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_A; + cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_A_M; + cr->usr0_mcs = TXUSRCT0_MCS_A; + cr->usr0_mcs_m = TXUSRCT0_MCS_A_M; + cr->usr1_mcs = TXUSRCT1_MCS_A; + cr->usr1_mcs_m = TXUSRCT1_MCS_A_M; + cr->usr2_mcs = TXUSRCT2_MCS_A; + cr->usr2_mcs_m = TXUSRCT2_MCS_A_M; + cr->usr3_mcs = TXUSRCT3_MCS_A; + cr->usr3_mcs_m = TXUSRCT3_MCS_A_M; + cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_A; + cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_A_M; + cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_A; + cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_A_M; + cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_A; + cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_A_M; + cr->ppdu_type = TXINFO_PPDU_TYPE_A; + cr->ppdu_type_m = TXINFO_PPDU_TYPE_A_M; + cr->txsc = TXINFO_TXSC_A; + cr->txsc_m = TXINFO_TXSC_A_M; + cr->cfo_comp = TXINFO_CFO_COMP_A; + cr->cfo_comp_m = TXINFO_CFO_COMP_A_M; + cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_A; + cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_A_M; + cr->usr0_n_sts = TXUSRCT0_N_STS_A; + cr->usr0_n_sts_m = TXUSRCT0_N_STS_A_M; + cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_A; + cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_A_M; + cr->usr0_strt_sts = TXUSRCT0_STRT_STS_A; + cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_A_M; + cr->usr1_n_sts = TXUSRCT1_N_STS_A; + cr->usr1_n_sts_m = TXUSRCT1_N_STS_A_M; + cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_A; + cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_A_M; + cr->usr1_strt_sts = TXUSRCT1_STRT_STS_A; + cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_A_M; + cr->usr2_n_sts = TXUSRCT2_N_STS_A; + cr->usr2_n_sts_m = TXUSRCT2_N_STS_A_M; + cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_A; + cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_A_M; + cr->usr2_strt_sts = TXUSRCT2_STRT_STS_A; + cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_A_M; + cr->usr3_n_sts = TXUSRCT3_N_STS_A; + cr->usr3_n_sts_m = TXUSRCT3_N_STS_A_M; + cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_A; + cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_A_M; + cr->usr3_strt_sts = TXUSRCT3_STRT_STS_A; + cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_A_M; + cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_A; + cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_A_M; + cr->gi_type = TXCOMCT_GI_TYPE_A; + cr->gi_type_m = TXCOMCT_GI_TYPE_A_M; + cr->ltf_type = TXCOMCT_LTF_TYPE_A; + cr->ltf_type_m = TXCOMCT_LTF_TYPE_A_M; + cr->dbw_idx = TXINFO_DBW_IDX_A; + cr->dbw_idx_m = TXINFO_DBW_IDX_A_M; + cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_A; + cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_A_M; + cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_A; + cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_A_M; + cr->doppler_en = TXCOMCT_DOPPLER_EN_A; + cr->doppler_en_m = TXCOMCT_DOPPLER_EN_A_M; + cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_A; + cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_A_M; + cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_A; + cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_A_M; + cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_A; + cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_A_M; + cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_A; + cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_A_M; + cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_A; + cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_A_M; + cr->ndp = TXCOMCT_NDP_A; + cr->ndp_m = TXCOMCT_NDP_A_M; + cr->stbc_en = TXCOMCT_STBC_EN_A; + cr->stbc_en_m = TXCOMCT_STBC_EN_A_M; + cr->ant_sel_a = TXINFO_ANT_SEL_A_A; + cr->ant_sel_a_m = TXINFO_ANT_SEL_A_A_M; + cr->ant_sel_b = TXINFO_ANT_SEL_B_A; + cr->ant_sel_b_m = TXINFO_ANT_SEL_B_A_M; + cr->ant_sel_c = TXINFO_ANT_SEL_C_A; + cr->ant_sel_c_m = TXINFO_ANT_SEL_C_A_M; + cr->ant_sel_d = TXINFO_ANT_SEL_D_A; + cr->ant_sel_d_m = TXINFO_ANT_SEL_D_A_M; + cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_A; + cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_A_M; + cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_A; + cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_A_M; + cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_A; + cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_A_M; + cr->ldpc_extr = TXTIMCT_LDPC_EXTR_A; + cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_A_M; + cr->usr0_dcm_en = TXUSRCT0_DCM_EN_A; + cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_A_M; + cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_A; + cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_A_M; + cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_A; + cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_A_M; + cr->usr1_dcm_en = TXUSRCT1_DCM_EN_A; + cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_A_M; + cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_A; + cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_A_M; + cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_A; + cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_A_M; + cr->usr2_dcm_en = TXUSRCT2_DCM_EN_A; + cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_A_M; + cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_A; + cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_A_M; + cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_A; + cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_A_M; + cr->usr3_dcm_en = TXUSRCT3_DCM_EN_A; + cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_A_M; + cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_A; + cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_A_M; + cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_A; + cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP2_SERIES + case BB_AP2: + cr->b_header_0 = R1B_TX_PMAC_HEADER_0_A2; + cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_A2_M; + cr->b_header_1 = R1B_TX_PMAC_HEADER_1_A2; + cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_A2_M; + cr->b_header_2 = R1B_TX_PMAC_HEADER_2_A2; + cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_A2_M; + cr->b_header_3 = R1B_TX_PMAC_HEADER_3_A2; + cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_A2_M; + cr->b_header_4 = R1B_TX_PMAC_HEADER_4_A2; + cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_A2_M; + cr->b_header_5 = R1B_TX_PMAC_HEADER_5_A2; + cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_A2_M; + cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A2; + cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A2_M; + cr->b_rate_idx = BMODE_RATE_IDX_A2; + cr->b_rate_idx_m = BMODE_RATE_IDX_A2_M; + cr->b_locked_clk_en = BMODE_LOCKED_CLK_EN_A2; + cr->b_locked_clk_en_m = BMODE_LOCKED_CLK_EN_A2_M; + cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_A2; + cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_A2_M; + cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_A2; + cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_A2_M; + cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_A2; + cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_A2_M; + cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_A2; + cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_A2_M; + cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_A2; + cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_A2_M; + cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_A2; + cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_A2_M; + cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_A2; + cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_A2_M; + cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_A2; + cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_A2_M; + cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_A2; + cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_A2_M; + cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_A2; + cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_A2_M; + cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_A2; + cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_A2_M; + cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_A2; + cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_A2_M; + cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_A2; + cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_A2_M; + cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_A2; + cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_A2_M; + cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_A2; + cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_A2_M; + cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_A2; + cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_A2_M; + cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_A2; + cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_A2_M; + cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_A2; + cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_A2_M; + cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_A2; + cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_A2_M; + cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_A2; + cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_A2_M; + cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_A2; + cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_A2_M; + cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_A2; + cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_A2_M; + cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_A2; + cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_A2_M; + cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_A2; + cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_A2_M; + cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_A2; + cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_A2_M; + cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_A2; + cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_A2_M; + cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_A2; + cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_A2_M; + cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_A2; + cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_A2_M; + cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_A2; + cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_A2_M; + cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_A2; + cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_A2_M; + cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_A2; + cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_A2_M; + cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_A2; + cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_A2_M; + cr->usr0_delmter = USER0_DELMTER_A2; + cr->usr0_delmter_m = USER0_DELMTER_A2_M; + cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_A2; + cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_A2_M; + cr->usr0_init_seed = USER0_INIT_SEED_A2; + cr->usr0_init_seed_m = USER0_INIT_SEED_A2_M; + cr->usr1_delmter = USER1_DELMTER_A2; + cr->usr1_delmter_m = USER1_DELMTER_A2_M; + cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_A2; + cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_A2_M; + cr->usr1_init_seed = USER1_INIT_SEED_A2; + cr->usr1_init_seed_m = USER1_INIT_SEED_A2_M; + cr->usr2_delmter = USER2_DELMTER_A2; + cr->usr2_delmter_m = USER2_DELMTER_A2_M; + cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_A2; + cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_A2_M; + cr->usr2_init_seed = USER2_INIT_SEED_A2; + cr->usr2_init_seed_m = USER2_INIT_SEED_A2_M; + cr->usr3_delmter = USER3_DELMTER_A2; + cr->usr3_delmter_m = USER3_DELMTER_A2_M; + cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_A2; + cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_A2_M; + cr->usr3_init_seed = USER3_INIT_SEED_A2; + cr->usr3_init_seed_m = USER3_INIT_SEED_A2_M; + cr->vht_sigb0 = TXD_VHT_SIGB0_A2; + cr->vht_sigb0_m = TXD_VHT_SIGB0_A2_M; + cr->vht_sigb1 = TXD_VHT_SIGB1_A2; + cr->vht_sigb1_m = TXD_VHT_SIGB1_A2_M; + cr->vht_sigb2 = TXD_VHT_SIGB2_A2; + cr->vht_sigb2_m = TXD_VHT_SIGB2_A2_M; + cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_A2; + cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_A2_M; + cr->vht_sigb3 = TXD_VHT_SIGB3_A2; + cr->vht_sigb3_m = TXD_VHT_SIGB3_A2_M; + cr->n_ltf = TXCOMCT_N_LTF_A2; + cr->n_ltf_m = TXCOMCT_N_LTF_A2_M; + cr->siga1 = TXD_SIGA1_A2; + cr->siga1_m = TXD_SIGA1_A2_M; + cr->siga2 = TXD_SIGA2_A2; + cr->siga2_m = TXD_SIGA2_A2_M; + cr->lsig = TXD_LSIG_A2; + cr->lsig_m = TXD_LSIG_A2_M; + cr->cca_pw_th = TXINFO_CCA_PW_TH_A2; + cr->cca_pw_th_m = TXINFO_CCA_PW_TH_A2_M; + cr->n_sym = TXTIMCT_N_SYM_A2; + cr->n_sym_m = TXTIMCT_N_SYM_A2_M; + cr->usr0_service = USER0_SERVICE_A2; + cr->usr0_service_m = USER0_SERVICE_A2_M; + cr->usr1_service = USER1_SERVICE_A2; + cr->usr1_service_m = USER1_SERVICE_A2_M; + cr->usr2_service = USER2_SERVICE_A2; + cr->usr2_service_m = USER2_SERVICE_A2_M; + cr->usr3_service = USER3_SERVICE_A2; + cr->usr3_service_m = USER3_SERVICE_A2_M; + cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_A2; + cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_A2_M; + cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_A2; + cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_A2_M; + cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_A2; + cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_A2_M; + cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_A2; + cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_A2_M; + cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_A2; + cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_A2_M; + cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_A2; + cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_A2_M; + cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_A2; + cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_A2_M; + cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_A2; + cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_A2_M; + cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_A2; + cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_A2_M; + cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_A2; + cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_A2_M; + cr->usr0_n_mpdu = USER0_N_MPDU_A2; + cr->usr0_n_mpdu_m = USER0_N_MPDU_A2_M; + cr->usr1_n_mpdu = USER1_N_MPDU_A2; + cr->usr1_n_mpdu_m = USER1_N_MPDU_A2_M; + cr->usr2_n_mpdu = USER2_N_MPDU_A2; + cr->usr2_n_mpdu_m = USER2_N_MPDU_A2_M; + cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_A2; + cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_A2_M; + cr->usr3_n_mpdu = USER3_N_MPDU_A2; + cr->usr3_n_mpdu_m = USER3_N_MPDU_A2_M; + cr->ch20_with_data = TXINFO_CH20_WITH_DATA_A2; + cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_A2_M; + cr->n_usr = TXINFO_N_USR_A2; + cr->n_usr_m = TXINFO_N_USR_A2_M; + cr->txcmd_txtp = TXINFO_TXCMD_TXTP_A2; + cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_A2_M; + cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_A2; + cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_A2_M; + cr->usr0_u_id = TXUSRCT0_U_ID_A2; + cr->usr0_u_id_m = TXUSRCT0_U_ID_A2_M; + cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_A2; + cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_A2_M; + cr->usr1_u_id = TXUSRCT1_U_ID_A2; + cr->usr1_u_id_m = TXUSRCT1_U_ID_A2_M; + cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_A2; + cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_A2_M; + cr->usr2_u_id = TXUSRCT2_U_ID_A2; + cr->usr2_u_id_m = TXUSRCT2_U_ID_A2_M; + cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_A2; + cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_A2_M; + cr->usr3_u_id = TXUSRCT3_U_ID_A2; + cr->usr3_u_id_m = TXUSRCT3_U_ID_A2_M; + cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_A2; + cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_A2_M; + cr->usr0_mcs = TXUSRCT0_MCS_A2; + cr->usr0_mcs_m = TXUSRCT0_MCS_A2_M; + cr->usr1_mcs = TXUSRCT1_MCS_A2; + cr->usr1_mcs_m = TXUSRCT1_MCS_A2_M; + cr->usr2_mcs = TXUSRCT2_MCS_A2; + cr->usr2_mcs_m = TXUSRCT2_MCS_A2_M; + cr->usr3_mcs = TXUSRCT3_MCS_A2; + cr->usr3_mcs_m = TXUSRCT3_MCS_A2_M; + cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_A2; + cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_A2_M; + cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_A2; + cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_A2_M; + cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_A2; + cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_A2_M; + cr->ppdu_type = TXINFO_PPDU_TYPE_A2; + cr->ppdu_type_m = TXINFO_PPDU_TYPE_A2_M; + cr->txsc = TXINFO_TXSC_A2; + cr->txsc_m = TXINFO_TXSC_A2_M; + cr->cfo_comp = TXINFO_CFO_COMP_A2; + cr->cfo_comp_m = TXINFO_CFO_COMP_A2_M; + cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_A2; + cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_A2_M; + cr->usr0_n_sts = TXUSRCT0_N_STS_A2; + cr->usr0_n_sts_m = TXUSRCT0_N_STS_A2_M; + cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_A2; + cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_A2_M; + cr->usr0_strt_sts = TXUSRCT0_STRT_STS_A2; + cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_A2_M; + cr->usr1_n_sts = TXUSRCT1_N_STS_A2; + cr->usr1_n_sts_m = TXUSRCT1_N_STS_A2_M; + cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_A2; + cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_A2_M; + cr->usr1_strt_sts = TXUSRCT1_STRT_STS_A2; + cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_A2_M; + cr->usr2_n_sts = TXUSRCT2_N_STS_A2; + cr->usr2_n_sts_m = TXUSRCT2_N_STS_A2_M; + cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_A2; + cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_A2_M; + cr->usr2_strt_sts = TXUSRCT2_STRT_STS_A2; + cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_A2_M; + cr->usr3_n_sts = TXUSRCT3_N_STS_A2; + cr->usr3_n_sts_m = TXUSRCT3_N_STS_A2_M; + cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_A2; + cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_A2_M; + cr->usr3_strt_sts = TXUSRCT3_STRT_STS_A2; + cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_A2_M; + cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_A2; + cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_A2_M; + cr->gi_type = TXCOMCT_GI_TYPE_A2; + cr->gi_type_m = TXCOMCT_GI_TYPE_A2_M; + cr->ltf_type = TXCOMCT_LTF_TYPE_A2; + cr->ltf_type_m = TXCOMCT_LTF_TYPE_A2_M; + cr->dbw_idx = TXINFO_DBW_IDX_A2; + cr->dbw_idx_m = TXINFO_DBW_IDX_A2_M; + cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_A2; + cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_A2_M; + cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_A2; + cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_A2_M; + cr->doppler_en = TXCOMCT_DOPPLER_EN_A2; + cr->doppler_en_m = TXCOMCT_DOPPLER_EN_A2_M; + cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_A2; + cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_A2_M; + cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_A2; + cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_A2_M; + cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_A2; + cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_A2_M; + cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_A2; + cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_A2_M; + cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_A2; + cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_A2_M; + cr->ndp = TXCOMCT_NDP_A2; + cr->ndp_m = TXCOMCT_NDP_A2_M; + cr->stbc_en = TXCOMCT_STBC_EN_A2; + cr->stbc_en_m = TXCOMCT_STBC_EN_A2_M; + cr->ant_sel_a = TXINFO_ANT_SEL_A_A2; + cr->ant_sel_a_m = TXINFO_ANT_SEL_A_A2_M; + cr->ant_sel_b = TXINFO_ANT_SEL_B_A2; + cr->ant_sel_b_m = TXINFO_ANT_SEL_B_A2_M; + cr->ant_sel_c = TXINFO_ANT_SEL_C_A2; + cr->ant_sel_c_m = TXINFO_ANT_SEL_C_A2_M; + cr->ant_sel_d = TXINFO_ANT_SEL_D_A2; + cr->ant_sel_d_m = TXINFO_ANT_SEL_D_A2_M; + cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_A2; + cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_A2_M; + cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_A2; + cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_A2_M; + cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_A2; + cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_A2_M; + cr->ldpc_extr = TXTIMCT_LDPC_EXTR_A2; + cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_A2_M; + cr->usr0_dcm_en = TXUSRCT0_DCM_EN_A2; + cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_A2_M; + cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_A2; + cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_A2_M; + cr->usr0_precoding_mode_idx = TXUSRCT0_PRECODING_MODE_IDX_A2; + cr->usr0_precoding_mode_idx_m = TXUSRCT0_PRECODING_MODE_IDX_A2; + cr->usr1_dcm_en = TXUSRCT1_DCM_EN_A2; + cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_A2_M; + cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_A2; + cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_A2_M; + cr->usr1_precoding_mode_idx = TXUSRCT1_PRECODING_MODE_IDX_A2; + cr->usr1_precoding_mode_idx_m = TXUSRCT1_PRECODING_MODE_IDX_A2; + cr->usr2_dcm_en = TXUSRCT2_DCM_EN_A2; + cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_A2_M; + cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_A2; + cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_A2_M; + cr->usr2_precoding_mode_idx = TXUSRCT2_PRECODING_MODE_IDX_A2; + cr->usr2_precoding_mode_idx_m = TXUSRCT2_PRECODING_MODE_IDX_A2; + cr->usr3_dcm_en = TXUSRCT3_DCM_EN_A2; + cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_A2_M; + cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_A2; + cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_A2_M; + cr->usr3_precoding_mode_idx = TXUSRCT3_PRECODING_MODE_IDX_A2; + cr->usr3_precoding_mode_idx_m = TXUSRCT3_PRECODING_MODE_IDX_A2; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->b_header_0 = R1B_TX_PMAC_HEADER_0_C; + cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_C_M; + cr->b_header_1 = R1B_TX_PMAC_HEADER_1_C; + cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_C_M; + cr->b_header_2 = R1B_TX_PMAC_HEADER_2_C; + cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_C_M; + cr->b_header_3 = R1B_TX_PMAC_HEADER_3_C; + cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_C_M; + cr->b_header_4 = R1B_TX_PMAC_HEADER_4_C; + cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_C_M; + cr->b_header_5 = R1B_TX_PMAC_HEADER_5_C; + cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_C_M; + cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_C; + cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_C_M; + cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C; + cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C_M; + cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_C; + cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_C_M; + cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_C; + cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_C_M; + cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_C; + cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_C_M; + cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_C; + cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_C_M; + cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_C; + cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_C_M; + cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_C; + cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_C_M; + cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_C; + cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_C_M; + cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_C; + cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_C_M; + cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_C; + cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_C_M; + cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_C; + cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_C_M; + cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_C; + cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_C_M; + cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_C; + cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_C_M; + cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_C; + cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_C_M; + cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_C; + cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_C_M; + cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_C; + cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_C_M; + cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_C; + cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_C_M; + cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_C; + cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_C_M; + cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_C; + cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_C_M; + cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_C; + cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_C_M; + cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_C; + cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_C_M; + cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_C; + cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_C_M; + cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_C; + cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_C_M; + cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_C; + cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_C_M; + cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_C; + cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_C_M; + cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_C; + cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_C_M; + cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_C; + cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_C_M; + cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_C; + cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_C_M; + cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_C; + cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_C_M; + cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_C; + cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_C_M; + cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_C; + cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_C_M; + cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_C; + cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_C_M; + cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_C; + cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_C_M; + cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_C; + cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_C_M; + cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_C; + cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_C_M; + cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_C; + cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_C_M; + cr->usr0_delmter = USER0_DELMTER_C; + cr->usr0_delmter_m = USER0_DELMTER_C_M; + cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_C; + cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_C_M; + cr->usr0_init_seed = USER0_INIT_SEED_C; + cr->usr0_init_seed_m = USER0_INIT_SEED_C_M; + cr->usr1_delmter = USER1_DELMTER_C; + cr->usr1_delmter_m = USER1_DELMTER_C_M; + cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_C; + cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_C_M; + cr->usr1_init_seed = USER1_INIT_SEED_C; + cr->usr1_init_seed_m = USER1_INIT_SEED_C_M; + cr->usr2_delmter = USER2_DELMTER_C; + cr->usr2_delmter_m = USER2_DELMTER_C_M; + cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_C; + cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_C_M; + cr->usr2_init_seed = USER2_INIT_SEED_C; + cr->usr2_init_seed_m = USER2_INIT_SEED_C_M; + cr->usr3_delmter = USER3_DELMTER_C; + cr->usr3_delmter_m = USER3_DELMTER_C_M; + cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_C; + cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_C_M; + cr->usr3_init_seed = USER3_INIT_SEED_C; + cr->usr3_init_seed_m = USER3_INIT_SEED_C_M; + cr->vht_sigb0 = TXD_VHT_SIGB0_C; + cr->vht_sigb0_m = TXD_VHT_SIGB0_C_M; + cr->vht_sigb1 = TXD_VHT_SIGB1_C; + cr->vht_sigb1_m = TXD_VHT_SIGB1_C_M; + cr->vht_sigb2 = TXD_VHT_SIGB2_C; + cr->vht_sigb2_m = TXD_VHT_SIGB2_C_M; + cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_C; + cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_C_M; + cr->vht_sigb3 = TXD_VHT_SIGB3_C; + cr->vht_sigb3_m = TXD_VHT_SIGB3_C_M; + cr->n_ltf = TXCOMCT_N_LTF_C; + cr->n_ltf_m = TXCOMCT_N_LTF_C_M; + cr->siga1 = TXD_SIGA1_C; + cr->siga1_m = TXD_SIGA1_C_M; + cr->siga2 = TXD_SIGA2_C; + cr->siga2_m = TXD_SIGA2_C_M; + cr->lsig = TXD_LSIG_C; + cr->lsig_m = TXD_LSIG_C_M; + cr->cca_pw_th = TXINFO_CCA_PW_TH_C; + cr->cca_pw_th_m = TXINFO_CCA_PW_TH_C_M; + cr->n_sym = TXTIMCT_N_SYM_C; + cr->n_sym_m = TXTIMCT_N_SYM_C_M; + cr->usr0_service = USER0_SERVICE_C; + cr->usr0_service_m = USER0_SERVICE_C_M; + cr->usr1_service = USER1_SERVICE_C; + cr->usr1_service_m = USER1_SERVICE_C_M; + cr->usr2_service = USER2_SERVICE_C; + cr->usr2_service_m = USER2_SERVICE_C_M; + cr->usr3_service = USER3_SERVICE_C; + cr->usr3_service_m = USER3_SERVICE_C_M; + cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_C; + cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_C_M; + cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_C; + cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_C_M; + cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_C; + cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_C_M; + cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_C; + cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_C_M; + cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_C; + cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_C_M; + cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_C; + cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_C_M; + cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_C; + cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_C_M; + cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_C; + cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_C_M; + cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_C; + cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_C_M; + cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_C; + cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_C_M; + cr->usr0_n_mpdu = USER0_N_MPDU_C; + cr->usr0_n_mpdu_m = USER0_N_MPDU_C_M; + cr->usr1_n_mpdu = USER1_N_MPDU_C; + cr->usr1_n_mpdu_m = USER1_N_MPDU_C_M; + cr->usr2_n_mpdu = USER2_N_MPDU_C; + cr->usr2_n_mpdu_m = USER2_N_MPDU_C_M; + cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_C; + cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_C_M; + cr->usr3_n_mpdu = USER3_N_MPDU_C; + cr->usr3_n_mpdu_m = USER3_N_MPDU_C_M; + cr->ch20_with_data = TXINFO_CH20_WITH_DATA_C; + cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_C_M; + cr->n_usr = TXINFO_N_USR_C; + cr->n_usr_m = TXINFO_N_USR_C_M; + cr->txcmd_txtp = TXINFO_TXCMD_TXTP_C; + cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_C_M; + cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_C; + cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_C_M; + cr->usr0_u_id = TXUSRCT0_U_ID_C; + cr->usr0_u_id_m = TXUSRCT0_U_ID_C_M; + cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_C; + cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_C_M; + cr->usr1_u_id = TXUSRCT1_U_ID_C; + cr->usr1_u_id_m = TXUSRCT1_U_ID_C_M; + cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_C; + cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_C_M; + cr->usr2_u_id = TXUSRCT2_U_ID_C; + cr->usr2_u_id_m = TXUSRCT2_U_ID_C_M; + cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_C; + cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_C_M; + cr->usr3_u_id = TXUSRCT3_U_ID_C; + cr->usr3_u_id_m = TXUSRCT3_U_ID_C_M; + cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_C; + cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_C_M; + cr->usr0_mcs = TXUSRCT0_MCS_C; + cr->usr0_mcs_m = TXUSRCT0_MCS_C_M; + cr->usr1_mcs = TXUSRCT1_MCS_C; + cr->usr1_mcs_m = TXUSRCT1_MCS_C_M; + cr->usr2_mcs = TXUSRCT2_MCS_C; + cr->usr2_mcs_m = TXUSRCT2_MCS_C_M; + cr->usr3_mcs = TXUSRCT3_MCS_C; + cr->usr3_mcs_m = TXUSRCT3_MCS_C_M; + cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_C; + cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_C_M; + cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_C; + cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_C_M; + cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_C; + cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_C_M; + cr->ppdu_type = TXINFO_PPDU_TYPE_C; + cr->ppdu_type_m = TXINFO_PPDU_TYPE_C_M; + cr->txsc = TXINFO_TXSC_C; + cr->txsc_m = TXINFO_TXSC_C_M; + cr->cfo_comp = TXINFO_CFO_COMP_C; + cr->cfo_comp_m = TXINFO_CFO_COMP_C_M; + cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_C; + cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_C_M; + cr->usr0_n_sts = TXUSRCT0_N_STS_C; + cr->usr0_n_sts_m = TXUSRCT0_N_STS_C_M; + cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_C; + cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_C_M; + cr->usr0_strt_sts = TXUSRCT0_STRT_STS_C; + cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_C_M; + cr->usr1_n_sts = TXUSRCT1_N_STS_C; + cr->usr1_n_sts_m = TXUSRCT1_N_STS_C_M; + cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_C; + cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_C_M; + cr->usr1_strt_sts = TXUSRCT1_STRT_STS_C; + cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_C_M; + cr->usr2_n_sts = TXUSRCT2_N_STS_C; + cr->usr2_n_sts_m = TXUSRCT2_N_STS_C_M; + cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_C; + cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_C_M; + cr->usr2_strt_sts = TXUSRCT2_STRT_STS_C; + cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_C_M; + cr->usr3_n_sts = TXUSRCT3_N_STS_C; + cr->usr3_n_sts_m = TXUSRCT3_N_STS_C_M; + cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_C; + cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_C_M; + cr->usr3_strt_sts = TXUSRCT3_STRT_STS_C; + cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_C_M; + cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_C; + cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_C_M; + cr->gi_type = TXCOMCT_GI_TYPE_C; + cr->gi_type_m = TXCOMCT_GI_TYPE_C_M; + cr->ltf_type = TXCOMCT_LTF_TYPE_C; + cr->ltf_type_m = TXCOMCT_LTF_TYPE_C_M; + cr->dbw_idx = TXINFO_DBW_IDX_C; + cr->dbw_idx_m = TXINFO_DBW_IDX_C_M; + cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_C; + cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_C_M; + cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_C; + cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_C_M; + cr->doppler_en = TXCOMCT_DOPPLER_EN_C; + cr->doppler_en_m = TXCOMCT_DOPPLER_EN_C_M; + cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_C; + cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_C_M; + cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_C; + cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_C_M; + cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_C; + cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_C_M; + cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_C; + cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_C_M; + cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_C; + cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_C_M; + cr->ndp = TXCOMCT_NDP_C; + cr->ndp_m = TXCOMCT_NDP_C_M; + cr->stbc_en = TXCOMCT_STBC_EN_C; + cr->stbc_en_m = TXCOMCT_STBC_EN_C_M; + cr->ant_sel_a = TXINFO_ANT_SEL_A_C; + cr->ant_sel_a_m = TXINFO_ANT_SEL_A_C_M; + cr->ant_sel_b = TXINFO_ANT_SEL_B_C; + cr->ant_sel_b_m = TXINFO_ANT_SEL_B_C_M; + cr->ant_sel_c = TXINFO_ANT_SEL_C_C; + cr->ant_sel_c_m = TXINFO_ANT_SEL_C_C_M; + cr->ant_sel_d = TXINFO_ANT_SEL_D_C; + cr->ant_sel_d_m = TXINFO_ANT_SEL_D_C_M; + cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_C; + cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_C_M; + cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_C; + cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_C_M; + cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_C; + cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_C_M; + cr->ldpc_extr = TXTIMCT_LDPC_EXTR_C; + cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_C_M; + cr->usr0_dcm_en = TXUSRCT0_DCM_EN_C; + cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_C_M; + cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_C; + cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_C_M; + cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_C; + cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_C_M; + cr->usr1_dcm_en = TXUSRCT1_DCM_EN_C; + cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_C_M; + cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_C; + cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_C_M; + cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_C; + cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_C_M; + cr->usr2_dcm_en = TXUSRCT2_DCM_EN_C; + cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_C_M; + cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_C; + cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_C_M; + cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_C; + cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_C_M; + cr->usr3_dcm_en = TXUSRCT3_DCM_EN_C; + cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_C_M; + cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_C; + cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_C_M; + cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_C; + cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_C_M; + break; + #endif + + default: + break; + } + +} +#else + +enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in, + struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx) +{ + return SPEC_INVALID; +} + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_plcp_tx.h b/phl/hal_g6/phy/bb/halbb_plcp_tx.h new file mode 100644 index 0000000..43fb461 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_plcp_tx.h @@ -0,0 +1,370 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_PLCP_TX_H_ +#define _HALBB_PLCP_TX_H_ + +/* ============================================================ + structure + ============================================================ +*/ +struct bb_plcp_cr_info { + u32 b_header_0; + u32 b_header_0_m; + u32 b_header_1; + u32 b_header_1_m; + u32 b_header_2; + u32 b_header_2_m; + u32 b_header_3; + u32 b_header_3_m; + u32 b_header_4; + u32 b_header_4_m; + u32 b_header_5; + u32 b_header_5_m; + u32 b_psdu_byte; + u32 b_psdu_byte_m; + u32 b_carrier_suppress_tx; + u32 b_carrier_suppress_tx_m; + u32 b_ppdu_type; + u32 b_ppdu_type_m; + u32 b_psdu_rate; + u32 b_psdu_rate_m; + u32 b_service_bit2; + u32 b_service_bit2_m; + u32 he_sigb_ch1_0; + u32 he_sigb_ch1_0_m; + u32 he_sigb_ch1_1; + u32 he_sigb_ch1_1_m; + u32 he_sigb_ch1_10; + u32 he_sigb_ch1_10_m; + u32 he_sigb_ch1_11; + u32 he_sigb_ch1_11_m; + u32 he_sigb_ch1_12; + u32 he_sigb_ch1_12_m; + u32 he_sigb_ch1_13; + u32 he_sigb_ch1_13_m; + u32 he_sigb_ch1_14; + u32 he_sigb_ch1_14_m; + u32 he_sigb_ch1_15; + u32 he_sigb_ch1_15_m; + u32 he_sigb_ch1_2; + u32 he_sigb_ch1_2_m; + u32 he_sigb_ch1_3; + u32 he_sigb_ch1_3_m; + u32 he_sigb_ch1_4; + u32 he_sigb_ch1_4_m; + u32 he_sigb_ch1_5; + u32 he_sigb_ch1_5_m; + u32 he_sigb_ch1_6; + u32 he_sigb_ch1_6_m; + u32 he_sigb_ch1_7; + u32 he_sigb_ch1_7_m; + u32 he_sigb_ch1_8; + u32 he_sigb_ch1_8_m; + u32 he_sigb_ch1_9; + u32 he_sigb_ch1_9_m; + u32 he_sigb_ch2_0; + u32 he_sigb_ch2_0_m; + u32 he_sigb_ch2_1; + u32 he_sigb_ch2_1_m; + u32 he_sigb_ch2_10; + u32 he_sigb_ch2_10_m; + u32 he_sigb_ch2_11; + u32 he_sigb_ch2_11_m; + u32 he_sigb_ch2_12; + u32 he_sigb_ch2_12_m; + u32 he_sigb_ch2_13; + u32 he_sigb_ch2_13_m; + u32 he_sigb_ch2_14; + u32 he_sigb_ch2_14_m; + u32 he_sigb_ch2_15; + u32 he_sigb_ch2_15_m; + u32 he_sigb_ch2_2; + u32 he_sigb_ch2_2_m; + u32 he_sigb_ch2_3; + u32 he_sigb_ch2_3_m; + u32 he_sigb_ch2_4; + u32 he_sigb_ch2_4_m; + u32 he_sigb_ch2_5; + u32 he_sigb_ch2_5_m; + u32 he_sigb_ch2_6; + u32 he_sigb_ch2_6_m; + u32 he_sigb_ch2_7; + u32 he_sigb_ch2_7_m; + u32 he_sigb_ch2_8; + u32 he_sigb_ch2_8_m; + u32 he_sigb_ch2_9; + u32 he_sigb_ch2_9_m; + u32 usr0_delmter; + u32 usr0_delmter_m; + u32 usr0_eof_padding_len; + u32 usr0_eof_padding_len_m; + u32 usr0_init_seed; + u32 usr0_init_seed_m; + u32 usr1_delmter; + u32 usr1_delmter_m; + u32 usr1_eof_padding_len; + u32 usr1_eof_padding_len_m; + u32 usr1_init_seed; + u32 usr1_init_seed_m; + u32 usr2_delmter; + u32 usr2_delmter_m; + u32 usr2_eof_padding_len; + u32 usr2_eof_padding_len_m; + u32 usr2_init_seed; + u32 usr2_init_seed_m; + u32 usr3_delmter; + u32 usr3_delmter_m; + u32 usr3_eof_padding_len; + u32 usr3_eof_padding_len_m; + u32 usr3_init_seed; + u32 usr3_init_seed_m; + u32 vht_sigb0; + u32 vht_sigb0_m; + u32 vht_sigb1; + u32 vht_sigb1_m; + u32 vht_sigb2; + u32 vht_sigb2_m; + u32 he_sigb_mcs; + u32 he_sigb_mcs_m; + u32 vht_sigb3; + u32 vht_sigb3_m; + u32 n_ltf; + u32 n_ltf_m; + u32 siga1; + u32 siga1_m; + u32 siga2; + u32 siga2_m; + u32 lsig; + u32 lsig_m; + u32 cca_pw_th; + u32 cca_pw_th_m; + u32 n_sym; + u32 n_sym_m; + u32 usr0_service; + u32 usr0_service_m; + u32 usr1_service; + u32 usr1_service_m; + u32 usr2_service; + u32 usr2_service_m; + u32 usr3_service; + u32 usr3_service_m; + u32 usr0_mdpu_len_byte; + u32 usr0_mdpu_len_byte_m; + u32 usr1_mdpu_len_byte; + u32 usr1_mdpu_len_byte_m; + u32 obw_cts2self_dup_type; + u32 obw_cts2self_dup_type_m; + u32 usr2_mdpu_len_byte; + u32 usr2_mdpu_len_byte_m; + u32 usr3_mdpu_len_byte; + u32 usr3_mdpu_len_byte_m; + u32 usr0_csi_buf_id; + u32 usr0_csi_buf_id_m; + u32 usr1_csi_buf_id; + u32 usr1_csi_buf_id_m; + u32 rf_gain_idx; + u32 rf_gain_idx_m; + u32 usr2_csi_buf_id; + u32 usr2_csi_buf_id_m; + u32 usr3_csi_buf_id; + u32 usr3_csi_buf_id_m; + u32 usr0_n_mpdu; + u32 usr0_n_mpdu_m; + u32 usr1_n_mpdu; + u32 usr1_n_mpdu_m; + u32 usr2_n_mpdu; + u32 usr2_n_mpdu_m; + u32 usr0_pw_boost_fctr_db; + u32 usr0_pw_boost_fctr_db_m; + u32 usr3_n_mpdu; + u32 usr3_n_mpdu_m; + u32 ch20_with_data; + u32 ch20_with_data_m; + u32 n_usr; + u32 n_usr_m; + u32 txcmd_txtp; + u32 txcmd_txtp_m; + u32 usr0_ru_alloc; + u32 usr0_ru_alloc_m; + u32 usr0_u_id; + u32 usr0_u_id_m; + u32 usr1_ru_alloc; + u32 usr1_ru_alloc_m; + u32 usr1_u_id; + u32 usr1_u_id_m; + u32 usr2_ru_alloc; + u32 usr2_ru_alloc_m; + u32 usr2_u_id; + u32 usr2_u_id_m; + u32 usr3_ru_alloc; + u32 usr3_ru_alloc_m; + u32 usr3_u_id; + u32 usr3_u_id_m; + u32 n_sym_hesigb; + u32 n_sym_hesigb_m; + u32 usr0_mcs; + u32 usr0_mcs_m; + u32 usr1_mcs; + u32 usr1_mcs_m; + u32 usr2_mcs; + u32 usr2_mcs_m; + u32 usr3_mcs; + u32 usr3_mcs_m; + u32 usr1_pw_boost_fctr_db; + u32 usr1_pw_boost_fctr_db_m; + u32 usr2_pw_boost_fctr_db; + u32 usr2_pw_boost_fctr_db_m; + u32 usr3_pw_boost_fctr_db; + u32 usr3_pw_boost_fctr_db_m; + u32 ppdu_type; + u32 ppdu_type_m; + u32 txsc; + u32 txsc_m; + u32 cfo_comp; + u32 cfo_comp_m; + u32 pkt_ext_idx; + u32 pkt_ext_idx_m; + u32 usr0_n_sts; + u32 usr0_n_sts_m; + u32 usr0_n_sts_ru_tot; + u32 usr0_n_sts_ru_tot_m; + u32 usr0_strt_sts; + u32 usr0_strt_sts_m; + u32 usr1_n_sts; + u32 usr1_n_sts_m; + u32 usr1_n_sts_ru_tot; + u32 usr1_n_sts_ru_tot_m; + u32 usr1_strt_sts; + u32 usr1_strt_sts_m; + u32 usr2_n_sts; + u32 usr2_n_sts_m; + u32 usr2_n_sts_ru_tot; + u32 usr2_n_sts_ru_tot_m; + u32 usr2_strt_sts; + u32 usr2_strt_sts_m; + u32 usr3_n_sts; + u32 usr3_n_sts_m; + u32 usr3_n_sts_ru_tot; + u32 usr3_n_sts_ru_tot_m; + u32 usr3_strt_sts; + u32 usr3_strt_sts_m; + u32 source_gen_mode_idx; + u32 source_gen_mode_idx_m; + u32 gi_type; + u32 gi_type_m; + u32 ltf_type; + u32 ltf_type_m; + u32 dbw_idx; + u32 dbw_idx_m; + u32 pre_fec_fctr; + u32 pre_fec_fctr_m; + u32 beam_change_en; + u32 beam_change_en_m; + u32 doppler_en; + u32 doppler_en_m; + u32 fb_mumimo_en; + u32 fb_mumimo_en_m; + u32 feedback_status; + u32 feedback_status_m; + u32 he_sigb_dcm_en; + u32 he_sigb_dcm_en_m; + u32 midamble_mode; + u32 midamble_mode_m; + u32 mumimo_ltf_mode_en; + u32 mumimo_ltf_mode_en_m; + u32 ndp; + u32 ndp_m; + u32 stbc_en; + u32 stbc_en_m; + u32 ant_sel_a; + u32 ant_sel_a_m; + u32 ant_sel_b; + u32 ant_sel_b_m; + u32 ant_sel_c; + u32 ant_sel_c_m; + u32 ant_sel_d; + u32 ant_sel_d_m; + u32 cca_pw_th_en; + u32 cca_pw_th_en_m; + u32 rf_fixed_gain_en; + u32 rf_fixed_gain_en_m; + u32 ul_cqi_rpt_tri; + u32 ul_cqi_rpt_tri_m; + u32 ldpc_extr; + u32 ldpc_extr_m; + u32 usr0_dcm_en; + u32 usr0_dcm_en_m; + u32 usr0_fec_type; + u32 usr0_fec_type_m; + u32 usr0_txbf_en; + u32 usr0_txbf_en_m; + u32 usr1_dcm_en; + u32 usr1_dcm_en_m; + u32 usr1_fec_type; + u32 usr1_fec_type_m; + u32 usr1_txbf_en; + u32 usr1_txbf_en_m; + u32 usr2_dcm_en; + u32 usr2_dcm_en_m; + u32 usr2_fec_type; + u32 usr2_fec_type_m; + u32 usr2_txbf_en; + u32 usr2_txbf_en_m; + u32 usr3_dcm_en; + u32 usr3_dcm_en_m; + u32 usr3_fec_type; + u32 usr3_fec_type_m; + u32 usr3_txbf_en; + u32 usr3_txbf_en_m; + u32 usr0_precoding_mode_idx; + u32 usr0_precoding_mode_idx_m; + u32 usr1_precoding_mode_idx; + u32 usr1_precoding_mode_idx_m; + u32 usr2_precoding_mode_idx; + u32 usr2_precoding_mode_idx_m; + u32 usr3_precoding_mode_idx; + u32 usr3_precoding_mode_idx_m; + u32 b_rate_idx; + u32 b_rate_idx_m; + u32 b_locked_clk_en; + u32 b_locked_clk_en_m; +}; + +struct bb_plcp_info { + struct bb_plcp_cr_info bb_plcp_cr_i; +}; + + +/* ============================================================ + Function Prototype + ============================================================ +*/ + +struct bb_info; + +void halbb_cr_cfg_plcp_init(struct bb_info *bb); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_plcp_tx_ex.h b/phl/hal_g6/phy/bb/halbb_plcp_tx_ex.h new file mode 100644 index 0000000..0eb8a31 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_plcp_tx_ex.h @@ -0,0 +1,224 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_PLCP_TX_EX_H_ +#define _HALBB_PLCP_TX_EX_H_ +/* ============================================================ + define + ============================================================ +*/ +#define N_USER 4 +#define DL_STA_LIST_MAX_NUM 8 +/* ============================================================ + Enumeration + ============================================================ + */ + +enum plcp_sts { + PLCP_SUCCESS = 0, + LENGTH_EXCEED, + CCK_INVALID, + OFDM_INVALID, + HT_INVALID, + VHT_INVALID, + HE_INVALID, + SPEC_INVALID +}; +/* ============================================================ + structure + ============================================================ +*/ +struct cr_address_t { + u32 address; + u32 bitmask; +}; + +struct ru_rate_entry { + u8 dcm: 1; + u8 ss: 3; + u8 mcs: 4; +}; + +struct rura_report { + u8 rate_table_col_idx: 6; + u8 partial_allocation_flag: 1; + u8 rate_change_flag: 1; +}; + +struct dl_ru_output_sta_entry { + u8 dropping_flag: 1; //0 + u8 txbf: 1; + u8 coding: 1; + u8 nsts: 3; + u8 rsvd0: 2; + + u8 mac_id: 8; + u8 ru_position: 8; + + u8 vip_flag: 1; //dont care + u8 pwr_boost_factor: 5; //dont care + u8 rsvd1: 2; + + u32 tx_length; + + struct ru_rate_entry ru_rate; + //for dl rura + struct rura_report ru_ra_report; +}; + +struct dl_rua_output { + u16 ru2su_flag: 1; + u16 ppdu_bw: 2; //set + u16 group_tx_pwr: 9; + u16 stbc: 1; + u16 gi_ltf: 3; + + u8 doppler: 1; + u8 n_ltf_and_ma: 3; + u8 sta_list_num: 4; //set + + u8 grp_mode: 1; + u8 group_id: 6; + u8 fixed_mode: 1; //set 1 + + struct dl_ru_output_sta_entry dl_output_sta_list[DL_STA_LIST_MAX_NUM]; +}; + +//sig-b output +struct sigb_compute_output { + u8 sta_0_idx: 2; + u8 sta_1_idx: 2; + u8 sta_2_idx: 2; + u8 sta_3_idx: 2; + u32 hw_sigb_content_channelone_len: 8; + u32 hw_sigb_content_channeltwo_len: 8; + u32 hw_sigb_symbolnum: 6; + u32 hw_sigb_content_channeltwo_offset: 5; //have to +1 + u32 ru2su_flag: 1; + u32 sigb_dcm: 1; + u32 sigb_mcs: 3; +}; + +struct bb_h2c_he_sigb { + u16 aid12[4]; + u8 force_sigb_rate; + u8 force_sigb_mcs; + u8 force_sigb_dcm; + u8 rsvd; + struct dl_rua_output dl_rua_out; + struct sigb_compute_output sigb_output; + struct cr_address_t n_sym_sigb_ch1[16]; + struct cr_address_t n_sym_sigb_ch2[16]; +}; + +//========== [Outer-Input] ==========// +struct usr_plcp_gen_in { + u32 mcs : 6; + u32 mpdu_len : 14; + u32 n_mpdu : 9; + u32 fec : 1; + u32 dcm : 1; + u32 rsvd0 : 1; + u32 aid : 12; + u32 scrambler_seed : 8; // rand (1~255) + u32 random_init_seed : 8; // rand (1~255) + u32 rsvd1 : 4; + u32 apep : 22; + u32 ru_alloc : 8; + u32 rsvd2 : 2; + u32 nss : 4; + u32 txbf : 1; + u32 pwr_boost_db : 5; + u32 rsvd3 : 22; +}; + +struct halbb_plcp_info { + u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 + u32 source_gen_mode : 2; + u32 locked_clk : 1; + u32 dyn_bw : 1; + u32 ndp_en : 1; + u32 long_preamble_en : 1; //bmode + u32 stbc : 1; + u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 + u32 tb_l_len : 12; + u32 tb_ru_tot_sts_max : 3; + u32 vht_txop_not_allowed : 1; + u32 tb_disam : 1; + u32 doppler : 2; + u32 he_ltf_type : 2;//0:1x,1:2x,2:4x + + u32 ht_l_len : 12; + u32 preamble_puncture : 1; + u32 he_mcs_sigb : 3;//0~5 + u32 he_dcm_sigb : 1; + u32 he_sigb_compress_en : 1; + u32 max_tx_time_0p4us : 14; + + + u32 ul_flag : 1; + u32 tb_ldpc_extra : 1; + u32 bss_color : 6; + u32 sr : 4; + u32 beamchange_en : 1; + u32 he_er_u106ru_en : 1; + u32 ul_srp1 : 4; + u32 ul_srp2 : 4; + u32 ul_srp3 : 4; + u32 ul_srp4 : 4; + u32 mode : 2; + + u32 group_id : 6; + u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB + u32 txop : 7; + u32 tb_strt_sts : 3; + u32 tb_pre_fec_padding_factor : 2; + u32 cbw : 2; + u32 txsc : 4; + u32 tb_mumimo_mode_en : 1; + u32 rsvd1 : 3; + + u8 nominal_t_pe : 2; // def = 2 + u8 ness : 2; // def = 0 + u8 rsvd2 : 4; + + u8 n_user; + u16 tb_rsvd : 9;//def = 0 + u16 rsvd3 : 7; + + struct usr_plcp_gen_in usr[N_USER]; +}; + +/* ============================================================ + Function Prototype + ============================================================ +*/ + +struct bb_info; + +enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in, + struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_pmac_setting.c b/phl/hal_g6/phy/bb/halbb_pmac_setting.c new file mode 100644 index 0000000..b95a75b --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pmac_setting.c @@ -0,0 +1,733 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +/*============================ [Tx Settings] =============================*/ +void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info, + enum phl_phy_idx phy_idx) +{ + + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx); + break; + #endif + default: + break; + } +} + +void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + halbb_set_tmac_tx_8852a(bb, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_set_tmac_tx_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_set_tmac_tx_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_set_tmac_tx_8852c(bb, phy_idx); + break; + #endif + default: + break; + } +} +/*============================ [Power Module] =============================*/ +bool halbb_cfg_lbk(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk, + enum rf_path tx_path, enum rf_path rx_path, + enum channel_width bw, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_A_CUT_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_cfg_lbk_8852c(bb, lbk_en, is_dgt_lbk, tx_path, + rx_path, bw, phy_idx); + break; + #endif + default: + break; + } + + return rpt; +} + +/*============================ [Power Module] =============================*/ +bool halbb_set_txpwr_dbm(struct bb_info *bb, s16 pwr_dbm, + enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_txpwr_dbm_8852a(bb, pwr_dbm, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_txpwr_dbm_8852a_2(bb, pwr_dbm, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_txpwr_dbm_8852b(bb, pwr_dbm, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_txpwr_dbm_8852c(bb, pwr_dbm, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +s16 halbb_get_txpwr_dbm(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + s16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_txpwr_dbm_8852a(bb, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_txpwr_dbm_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_txpwr_dbm_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_txpwr_dbm_8852c(bb, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +s16 halbb_get_txinfo_txpwr_dbm(struct bb_info *bb) +{ + s16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_txinfo_txpwr_dbm_8852a(bb); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_txinfo_txpwr_dbm_8852a_2(bb); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_txinfo_txpwr_dbm_8852b(bb); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_txinfo_txpwr_dbm_8852c(bb); + break; + #endif + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_set_cck_txpwr_idx(struct bb_info *bb, u16 pwr_idx, + enum rf_path tx_path) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_cck_txpwr_idx_8852a(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_cck_txpwr_idx_8852a_2(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_cck_txpwr_idx_8852b(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_cck_txpwr_idx_8852c(bb, pwr_idx, tx_path); + break; + #endif + default: + rpt = false; + break; + } + + return rpt; +} + +u16 halbb_get_cck_txpwr_idx(struct bb_info *bb, enum rf_path tx_path) +{ + u16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_cck_txpwr_idx_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_cck_txpwr_idx_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_cck_txpwr_idx_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_cck_txpwr_idx_8852c(bb, tx_path); + break; + #endif + + default: + rpt= false; + break; + } + return rpt; +} + +s16 halbb_get_cck_ref_dbm(struct bb_info *bb, enum rf_path tx_path) +{ + s16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_cck_ref_dbm_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_cck_ref_dbm_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_cck_ref_dbm_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_cck_ref_dbm_8852c(bb, tx_path); + break; + #endif + + default: + rpt= false; + break; + } + return rpt; +} + +bool halbb_set_ofdm_txpwr_idx(struct bb_info *bb, u16 pwr_idx, + enum rf_path tx_path) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_ofdm_txpwr_idx_8852a(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_ofdm_txpwr_idx_8852a_2(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_ofdm_txpwr_idx_8852b(bb, pwr_idx, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_ofdm_txpwr_idx_8852c(bb, pwr_idx, tx_path); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +u16 halbb_get_ofdm_txpwr_idx(struct bb_info *bb, enum rf_path tx_path) +{ + u16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_ofdm_txpwr_idx_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_ofdm_txpwr_idx_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_ofdm_txpwr_idx_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_ofdm_txpwr_idx_8852c(bb, tx_path); + break; + #endif + + default: + rpt= false; + break; + } + return rpt; +} + +s16 halbb_get_ofdm_ref_dbm(struct bb_info *bb, enum rf_path tx_path) +{ + s16 rpt; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_get_ofdm_ref_dbm_8852a(bb, tx_path); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_get_ofdm_ref_dbm_8852a_2(bb, tx_path); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_get_ofdm_ref_dbm_8852b(bb, tx_path); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_get_ofdm_ref_dbm_8852c(bb, tx_path); + break; + #endif + + default: + rpt= false; + break; + } + return rpt; +} + + +/*============================ [Others] =============================*/ +bool halbb_chk_tx_idle(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_chk_tx_idle_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_chk_tx_idle_8852c(bb, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +void halbb_dpd_bypass(struct bb_info *bb, bool pdp_bypass, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_dpd_bypass_8852a_2(bb, pdp_bypass, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + //halbb_dpd_bypass_8852b(bb, pdp_bypass, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_dpd_bypass_8852c(bb, pdp_bypass, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_backup_info(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_backup_info_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_backup_info_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_backup_info_8852c(bb, phy_idx); + break; + #endif + + default: + break; + } +} + +void halbb_restore_info(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); + + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_restore_info_8852a_2(bb, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_restore_info_8852b(bb, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_restore_info_8852c(bb, phy_idx); + break; + #endif + + default: + break; + } +} + +bool halbb_set_txsc(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_txsc_8852a(bb, txsc, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_txsc_8852a_2(bb, txsc, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_txsc_8852b(bb, txsc, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_txsc_8852c(bb, txsc, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_set_bss_color(struct bb_info *bb, u8 bss_color, + enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_bss_color_8852a(bb, bss_color, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_bss_color_8852a_2(bb, bss_color, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_bss_color_8852b(bb, bss_color, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_bss_color_8852c(bb, bss_color, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +bool halbb_set_sta_id(struct bb_info *bb, u16 sta_id, enum phl_phy_idx phy_idx) +{ + bool rpt = true; + + switch (bb->ic_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_RTL8852AA: + rpt = halbb_set_sta_id_8852a(bb, sta_id, phy_idx); + break; + #endif + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + rpt = halbb_set_sta_id_8852a_2(bb, sta_id, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + rpt = halbb_set_sta_id_8852b(bb, sta_id, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + rpt = halbb_set_sta_id_8852c(bb, sta_id, phy_idx); + break; + #endif + + default: + rpt = false; + break; + } + + return rpt; +} + +void halbb_pmac_tx_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{bw} {pri_ch bw} {phy_idx}\n"); + + } else if (_os_strcmp(input[1], "tx_path") == 0) { + HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]); + + //halbb_set_pmac_tx_path(bb, (enum bb_path)val[0]); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Cfg Tx Path API \n"); + } + *_used = used; + *_out_len = out_len; +} + diff --git a/phl/hal_g6/phy/bb/halbb_pmac_setting.h b/phl/hal_g6/phy/bb/halbb_pmac_setting.h new file mode 100644 index 0000000..8cd350f --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pmac_setting.h @@ -0,0 +1,53 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_PMAC_SETTING_H_ +#define _HALBB_PMAC_SETTING_H_ + +/* ============================================================ + Enumeration + ============================================================ + */ + +enum halbb_pmac_mode { + NONE_TEST, + PKTS_TX, + PKTS_RX, + CONT_TX, + FW_TRIG_TX, + OFDM_SINGLE_TONE_TX, + CCK_CARRIER_SIPPRESSION_TX +}; +/* ============================================================ + Function Prototype + ============================================================ +*/ + +struct bb_info; + +void halbb_pmac_tx_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_pmac_setting_ex.h b/phl/hal_g6/phy/bb/halbb_pmac_setting_ex.h new file mode 100644 index 0000000..4f6c7fd --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pmac_setting_ex.h @@ -0,0 +1,113 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef _HALBB_PMAC_SETTING_EX_H_ +#define _HALBB_PMAC_SETTING_EX_H_ +#include "halbb_ic_hw_info.h" +#include "halbb_pmac_setting.h" + +/* ============================================================ + structure + ============================================================ +*/ +struct halbb_pmac_info { + u8 en_pmac_tx:1; /*0: PMAC Tx Off 1: PMAC Tx On */ + u8 is_cck:1; + u8 mode:3; /*1: Packet TX 3:Continuous TX */ + u8 rsvd:3; + u16 tx_cnt; + u16 period; // us + u16 tx_time; // us + u8 duty_cycle; // for fw trig. tx used +}; + +struct bb_h2c_fw_tx_setting { + u8 pkt_cnt[2]; + bool tx_en; + u8 tx_type; + u8 tx_period[4]; + u8 tx_time[4]; + u8 duty_cycle[4]; +}; + +struct bb_c2h_fw_tx_rpt { + bool tx_done; +}; + + +/* ============================================================ + Function Prototype + ============================================================ +*/ + +struct bb_info; + +void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info, + enum phl_phy_idx phy_idx); + +void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx); + +bool halbb_cfg_lbk(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk, + enum rf_path tx_path, enum rf_path rx_path, + enum channel_width bw, enum phl_phy_idx phy_idx); + +bool halbb_set_txpwr_dbm(struct bb_info *bb, s16 pwr_dbm, + enum phl_phy_idx phy_idx); + +s16 halbb_get_txpwr_dbm(struct bb_info *bb, enum phl_phy_idx phy_idx); + +s16 halbb_get_txinfo_txpwr_dbm(struct bb_info *bb); + +bool halbb_set_cck_txpwr_idx(struct bb_info *bb, u16 pwr_idx, + enum rf_path tx_path); + +u16 halbb_get_cck_txpwr_idx(struct bb_info *bb, enum rf_path tx_path); + +s16 halbb_get_cck_ref_dbm(struct bb_info *bb, enum rf_path tx_path); + +bool halbb_set_ofdm_txpwr_idx(struct bb_info *bb, u16 pwr_idx, + enum rf_path tx_path); + +u16 halbb_get_ofdm_txpwr_idx(struct bb_info *bb, enum rf_path tx_path); + +s16 halbb_get_ofdm_ref_dbm(struct bb_info *bb, enum rf_path tx_path); + +bool halbb_chk_tx_idle(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_dpd_bypass(struct bb_info *bb, bool pdp_bypass, + enum phl_phy_idx phy_idx); + +void halbb_backup_info(struct bb_info *bb, enum phl_phy_idx phy_idx); + +void halbb_restore_info(struct bb_info *bb, enum phl_phy_idx phy_idx); + +bool halbb_set_txsc(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx); + +bool halbb_set_bss_color(struct bb_info *bb, u8 bss_color, + enum phl_phy_idx phy_idx); + +bool halbb_set_sta_id(struct bb_info *bb, u16 sta_id, enum phl_phy_idx phy_idx); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_precomp.h b/phl/hal_g6/phy/bb/halbb_precomp.h new file mode 100644 index 0000000..a056d84 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_precomp.h @@ -0,0 +1,144 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PRECOMP_H__ +#define __HALBB_PRECOMP_H__ + +#include "halbb_cfg_ic.h" + +/*---[Define Only] ----------------------------------------------------------*/ +#include "../../hal_headers_le.h" +#include "halbb_types.h" +#include "halbb_features.h" +#include "halbb_ic_hw_info.h" +#include "halbb_ic_sw_info.h" +#include "halbb_interface.h" + +#include "halbb_rua_tbl_ex.h" + +#if (PLATFOM_IS_LITTLE_ENDIAN) + #include "halbb_physts_ie_l_endian.h" + #include "halbb_ra_l_endian.h" + #include "halbb_rua_tbl_l_endian.h" +#else + #include "halbb_physts_ie_b_endian.h" + #include "halbb_ra_b_endian.h" + #include "halbb_rua_tbl_b_endian.h" +#endif + +/*---[Include structure & prototype] ----------------------------------------*/ +#ifdef BB_8852A_CAV_SUPPORT + + #include "halbb_8852a/halbb_cr_info_8852a_a_cut.h" + #include "halbb_8852a/halbb_8852a.h" + #include "halbb_8852a/halbb_8852a_api.h" + #include "halbb_8852a/halbb_8852a_api_ex.h" + #include "halbb_8852a/halbb_hwimg_8852a.h" + #include "halbb_8852a/halbb_reg_cfg_8852a.h" + #include "halbb_8852a/halbb_version_rtl8852a.h" +#endif + +#ifdef BB_8852A_2_SUPPORT + #include "halbb_8852a_2/halbb_cr_info_8852a_2.h" + #include "halbb_8852a_2/halbb_8852a_2.h" + #include "halbb_8852a_2/halbb_8852a_2_api.h" + #include "halbb_8852a_2/halbb_8852a_2_api_ex.h" + #include "halbb_8852a_2/halbb_hwimg_8852a_2.h" + #include "halbb_8852a_2/halbb_reg_cfg_8852a_2.h" + #include "halbb_8852a_2/halbb_version_rtl8852a_2.h" +#endif + +#ifdef BB_8852B_SUPPORT + #include "halbb_8852b/halbb_cr_info_8852b.h" + #include "halbb_8852b/halbb_8852b.h" + #include "halbb_8852b/halbb_8852b_api.h" + #include "halbb_8852b/halbb_8852b_api_ex.h" + #include "halbb_8852b/halbb_hwimg_8852b.h" + #include "halbb_8852b/halbb_reg_cfg_8852b.h" + #include "halbb_8852b/halbb_version_rtl8852b.h" +#endif + +#ifdef BB_8852C_SUPPORT + #include "halbb_8852c/halbb_cr_info_8852c.h" + #include "halbb_8852c/halbb_8852c.h" + #include "halbb_8852c/halbb_8852c_api.h" + #include "halbb_8852c/halbb_8852c_api_ex.h" + #include "halbb_8852c/halbb_hwimg_8852c.h" + #include "halbb_8852c/halbb_reg_cfg_8852c.h" + #include "halbb_8852c/halbb_version_rtl8852c.h" +#endif + +#include "halbb_ra.h" +#include "halbb_ra_ex.h" +#include "halbb_hw_cfg.h" +#include "halbb_hw_cfg_ex.h" +#include "halbb_api.h" +#include "halbb_api_ex.h" +#include "halbb_interface_ex.h" +#include "halbb_math_lib_ex.h" +#include "halbb_math_lib.h" +#include "halbb_dbg.h" +#include "halbb_dbg_cmd.h" +#include "halbb_dbg_cmd_ex.h" +#include "halbb_physts_ex.h" +#include "halbb_physts.h" +#include "halbb_cmn_rpt_ex.h" +#include "halbb_cmn_rpt.h" +#include "halbb_init.h" +#include "halbb_init_ex.h" +#include "halbb_pmac_setting.h" +#include "halbb_pmac_setting_ex.h" +#include "halbb_plcp_tx_ex.h" +#include "halbb_plcp_tx.h" +#include "halbb_plcp_gen.h" +#include "halbb_la_mode_ex.h" +#include "halbb_la_mode.h" +#include "halbb_psd.h" +#include "halbb_pwr_ctrl_ex.h" +#include "halbb_pwr_ctrl.h" +#include "halbb_mp_ex.h" +#include "halbb_dfs.h" +#include "halbb_dfs_ex.h" +#include "halbb_cfo_trk.h" +#include "halbb_edcca.h" +#include "halbb_edcca_ex.h" +#include "halbb_env_mntr_ex.h" +#include "halbb_env_mntr.h" +#include "halbb_dig_ex.h" +#include "halbb_dig.h" +#include "halbb_dyn_csi_rsp.h" +#include "halbb_dyn_csi_rsp_ex.h" +#include "halbb_ant_div.h" +#include "halbb_statistics.h" +#include "halbb_ch_info_ex.h" +#include "halbb_ch_info.h" +#include "halbb_auto_dbg.h" +#include "halbb_dbcc_ex.h" +#include "halbb_dbcc.h" +#include "halbb_rua_tbl.h" +#include "halbb_fwofld.h" +#include "halbb_ex.h" +#include "halbb.h" + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_psd.c b/phl/hal_g6/phy/bb/halbb_psd.c new file mode 100644 index 0000000..3c07fa3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_psd.c @@ -0,0 +1,504 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_PSD_SUPPORT +static const u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127}; +static const u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67}; + +void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + if (igi_lv == IGI_DEFAULT) { + psd->igi_pin = 28; + halbb_set_reg(bb, 0x1590, 0x7000, psd->lna_bkp); + halbb_set_reg(bb, 0x1650, 0x7000, psd->lna_bkp_b); + halbb_set_reg(bb, 0x1598, BIT(20), psd->tia_bkp); + halbb_set_reg(bb, 0x1658, BIT(20), psd->tia_bkp_b); + halbb_set_reg(bb, 0x1580, 0x3e0, psd->rxbb_bkp); + halbb_set_reg(bb, 0x1640, 0x3e0, psd->rxbb_bkp_b); + } else if (igi_lv == IGI_LEVEL1) {/*@ target Pin=-72dBm*/ + psd->igi_pin = 28; + halbb_set_reg(bb, 0x1590, 0x7000, 0x6); + halbb_set_reg(bb, 0x1650, 0x7000, 0x6); + halbb_set_reg(bb, 0x1598, BIT(20), 0x1); + halbb_set_reg(bb, 0x1658, BIT(20), 0x1); + halbb_set_reg(bb, 0x1580, 0x3e0, 0x1f); + halbb_set_reg(bb, 0x1640, 0x3e0, 0x1f); + } else if (igi_lv == IGI_LEVEL2) {/*@ target Pin=-50dBm*/ + psd->igi_pin = 50; + halbb_set_reg(bb, 0x1590, 0x7000, 0x6); + halbb_set_reg(bb, 0x1650, 0x7000, 0x6); + halbb_set_reg(bb, 0x1598, BIT(20), 0x1); + halbb_set_reg(bb, 0x1658, BIT(20), 0x1); + halbb_set_reg(bb, 0x1580, 0x3e0, 0x9); + halbb_set_reg(bb, 0x1640, 0x3e0, 0x9); + } else if (igi_lv == IGI_LEVEL3) {/*@ target Pin=-35dBm*/ + psd->igi_pin = 65; + halbb_set_reg(bb, 0x1590, 0x7000, 0x6); + halbb_set_reg(bb, 0x1650, 0x7000, 0x6); + halbb_set_reg(bb, 0x1598, BIT(20), 0x0); + halbb_set_reg(bb, 0x1658, BIT(20), 0x0); + halbb_set_reg(bb, 0x1580, 0x3e0, 0x0); + halbb_set_reg(bb, 0x1640, 0x3e0, 0x0); + } else if (igi_lv == IGI_LEVEL4) {/*@ target Pin=0dBm*/ + psd->igi_pin = 100; + halbb_set_reg(bb, 0x1590, 0x7000, 0x0); + halbb_set_reg(bb, 0x1650, 0x7000, 0x0); + halbb_set_reg(bb, 0x1598, BIT(20), 0x0); + halbb_set_reg(bb, 0x1658, BIT(20), 0x0); + halbb_set_reg(bb, 0x1580, 0x3e0, 0x8); + halbb_set_reg(bb, 0x1640, 0x3e0, 0x8); + } +} + +u32 halbb_get_psd_data(struct bb_info *bb, u32 psd_tone_idx, u32 igi_pin) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + struct bb_psd_cr_info *cr = &psd->bb_psd_cr_i; + u8 i = 0; + u8 j = 0; + u32 psd_report = 0; + bool psd_rdy = false; + + halbb_set_reg(bb, cr->fft_idx, cr->fft_idx_m, psd_tone_idx & 0x3ff); + /*PSD trigger start*/ + halbb_set_reg(bb, cr->psd_en, cr->psd_en_m, 1); + halbb_delay_us(bb, 10 << (psd->fft_point >> 7)); + + /*Get PSD Report*/ + do { /*Polling time always use 100ms, when it exceed 2s, break loop*/ + psd_rdy = (u8)halbb_get_reg(bb, psd->psd_report_reg, BIT(25)); + + if (!psd_rdy) { + halbb_delay_us(bb, 100); + i++; + continue; + } else { + /*BB_DBG(bb, DBG_DBG_API, "psd_rdy = %d\n", psd_rdy);*/ + psd_report = halbb_get_reg(bb, psd->psd_report_reg, + 0x1ffffff); + /*psd_report = psd_report >> 22;*/ + psd_report = halbb_convert_to_db((u64)psd_report) + + igi_pin; + break; + } + psd_report = 0; + } while (i < 20); + + /*PSD trigger stop*/ + halbb_set_reg(bb, psd->psd_reg, BIT(22), 0); + + do { /*Polling time always use 100ms, when it exceed 2s, break loop*/ + psd_rdy = (u8)halbb_get_reg(bb, psd->psd_report_reg, BIT(25)); + + if (psd_rdy) { + /*BB_TRACE("psd_rdy2 = %d, wait %d * 100us for release \n", psd_rdy, (j + 1));*/ + halbb_delay_us(bb, 100); + j++; + continue; + } else { + + break; + } + } while (j < 20); + + return psd_report; +} + +void halbb_psd_para_setting(struct bb_info *bb, u8 sw_avg_time, u8 hw_avg_time, + u8 i_q_setting, u16 fft_point, u8 path, + u8 psd_input, u8 channel, u8 bw) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + u8 fft_idx = 0; + + psd->fft_point_pre = psd->fft_point; + psd->fft_point = fft_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + psd->sw_avg_time = sw_avg_time; + psd->hw_avg_time = hw_avg_time; + psd->i_q_setting = i_q_setting; + psd->path = path; + psd->input = psd_input; + psd->psd_fc_ch = channel; + psd->bw = bw; + + if (fft_point == 128) + fft_idx = 3; + else if (fft_point == 256) + fft_idx = 2; + else if (fft_point == 512) + fft_idx = 1; + else if (fft_point == 1024) + fft_idx = 0; + + halbb_set_reg(bb, psd->psd_reg, BIT(16) | BIT(15), fft_idx); + halbb_set_reg(bb, psd->psd_reg, BIT(12) | BIT(11), i_q_setting); + halbb_set_reg(bb, psd->psd_reg, BIT(14) | BIT(13), hw_avg_time); + halbb_set_reg(bb, psd->psd_reg, BIT(18) | BIT(17), path); + halbb_set_reg(bb, psd->psd_reg, BIT(20) | BIT(19), psd_input); +} + +bool halbb_psd_alloc_buff(struct bb_info *bb) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + if (!psd->rpt) { + psd->rpt = (u8 *)halbb_mem_alloc(bb, psd->fft_point); + } else if (psd->rpt && psd->fft_point != psd->fft_point_pre) { + halbb_mem_free(bb, psd->rpt, sizeof(psd->rpt)); + psd->rpt = (u8 *)halbb_mem_alloc(bb, psd->fft_point); + } + + if (!psd->rpt) + return false; + else + return true; +} + +void halbb_get_gain_index(struct bb_info *bb) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + psd->lna_bkp = (u8)halbb_get_reg(bb, 0x1590, 0x7000); + psd->lna_bkp_b = (u8)halbb_get_reg(bb, 0x1650, 0x7000); + psd->tia_bkp = (u8)halbb_get_reg(bb, 0x1598, BIT(20)); + psd->tia_bkp_b = (u8)halbb_get_reg(bb, 0x1658, BIT(20)); + psd->rxbb_bkp = (u8)halbb_get_reg(bb, 0x1580, 0x3e0); + psd->rxbb_bkp_b = (u8)halbb_get_reg(bb, 0x1640, 0x3e0); +} + +u8 halbb_psd(struct bb_info *bb, enum igi_lv_sel igi_lv, u16 start_point, + u16 stop_point) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + struct bb_api_info *api = &bb->bb_api_i; + u32 i = 0, mod_tone_idx = 0; + u32 t = 0; + u16 fft_max_half_bw = 0; + u16 fail_cnt = 0; + u16 valid_cnt = 0; + u8 psd_fc_ch = psd->psd_fc_ch; + enum band_type psd_band = psd->psd_band; + u8 bw = psd->bw; + u32 psd_result_tmp = 0; + u32 psd_result_total = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_idx = 0; + u8 set_result = 0; + u8 psd_pri_ch = 1; + + if (bb->hal_com->chip_id == CHIP_WIFI6_8852A) { + halbb_mem_cpy(bb, psd_result_cali_tone, + psd_result_cali_tone_8821, 7); + halbb_mem_cpy(bb, psd_result_cali_val, + psd_result_cali_val_8821, 7); + } + + psd->psd_in_progress = 1; + halbb_set_reg(bb, 0x014, BIT(1), 1); + + BB_TRACE(" PSD_Start =>\n"); + /* @[Get default gain value]*/ + halbb_get_gain_index(bb); + /* @[Stop pre-AGC]*/ + /* @[Set High IGI level & make it can't CCA]*/ + halbb_pre_agc_en(bb, false); + halbb_psd_igi_lv(bb, IGI_LEVEL4); + + halbb_delay_us(bb, 10); + BB_TRACE(" sw_avg_time = %d , hw_avg_time = %d , IQ = %d , fft_point = %d , path = %d , input = %d , ch = %d , BW = %d\n", + psd->sw_avg_time, psd->hw_avg_time, psd->i_q_setting, + psd->fft_point, psd->path, psd->input, psd_fc_ch, bw); + + if (halbb_stop_ic_trx(bb, HALBB_SET) == HALBB_SET_FAIL) { + /*@[resume pre-AGC and resume IGI level]*/ + halbb_pre_agc_en(bb, true); + halbb_psd_igi_lv(bb, IGI_DEFAULT); + return HALBB_SET_FAIL; + } + + /* @[Set IGI level]*/ + halbb_psd_igi_lv(bb, igi_lv); + + /* @[Backup RF Reg]*/ + psd->rf_0x18_bkp = halbb_read_rf_reg(bb, RF_PATH_A, 0x18, + RFREGOFFSETMASK); + psd->rf_0x18_bkp_b = halbb_read_rf_reg(bb, RF_PATH_B, 0x18, + RFREGOFFSETMASK); + + if ((psd->input == 0) || (psd->input == 1)) { + if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) + psd->psd_bw = 80; + else + psd->psd_bw = 160; + } else if ((psd->input == 2) || (psd->input == 3)) { + if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) + psd->psd_bw = 40; + else + psd->psd_bw = 80; + } + if (psd->psd_bw == 80) + halbb_set_reg(bb, 0x9c8, BIT(23), 1); + else + halbb_set_reg(bb, 0x9c8, BIT(23), 0); + + BB_DBG(bb, DBG_DBG_API, " PSD_BW = %d\n", psd->psd_bw); + + /* Set RF fc*/ + if(halbb_ctrl_ch(bb, psd_fc_ch, psd_band, HW_PHY_0) == false) + return HALBB_SET_FAIL; + if(halbb_ctrl_ch(bb, psd_fc_ch, psd_band, HW_PHY_1) == false) + return HALBB_SET_FAIL; + if(halbb_ctrl_bw(bb, psd_pri_ch, bw, HW_PHY_0) == false) + return HALBB_SET_FAIL; + if(halbb_ctrl_bw(bb, psd_pri_ch, bw, HW_PHY_1) == false) + return HALBB_SET_FAIL; + + BB_DBG(bb, DBG_DBG_API, "RF0x18=((0x%x))\n", + halbb_read_rf_reg(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK)); + + halbb_delay_us(bb, 10); + + if (stop_point > (psd->fft_point - 1)) + stop_point = (psd->fft_point - 1); + + if (start_point > (psd->fft_point - 1)) + start_point = (psd->fft_point - 1); + + if (start_point > stop_point) + stop_point = start_point; + + for (i = start_point; i <= stop_point; i++) { + + fft_max_half_bw = (psd->fft_point) >> 1; + + if (i < fft_max_half_bw) + mod_tone_idx = i + fft_max_half_bw; + else + mod_tone_idx = i - fft_max_half_bw; + + psd_result_tmp = 0; + psd_result_total = 0; + fail_cnt = 0; + for (t = 0; t < psd->sw_avg_time; t++) { + psd_result_tmp = halbb_get_psd_data(bb, mod_tone_idx, + psd->igi_pin); + if (psd_result_tmp == 0) + fail_cnt ++; + psd_result_total += psd_result_tmp; + } + if (psd->sw_avg_time > fail_cnt) + valid_cnt = psd->sw_avg_time - fail_cnt; + else + valid_cnt = psd->sw_avg_time; + psd_result = (u8)((psd_result_total / valid_cnt)) - + psd->psd_pwr_common_offset; + psd->rpt[i] = psd_result; + + if (psd->fft_point == 128 && psd->noise_k_en) { + if (i > psd_result_cali_tone[noise_idx]) + noise_idx++; + + if (noise_idx > 6) + noise_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_idx]) + psd_result = psd_result - + psd_result_cali_val[noise_idx]; + else + psd_result = 0; + + psd->psd_result[i] = psd_result; + } + + BB_DBG(bb, DBG_DBG_API, "[%-4d] N_cali = %d, PSD = %d\n", + mod_tone_idx, psd_result_cali_val[noise_idx], + psd_result); + } + + /*@[Revert Reg]*/ + set_result = halbb_stop_ic_trx(bb, HALBB_REVERT); + + halbb_ctrl_ch(bb, api->central_ch, api->band, HW_PHY_0); + halbb_ctrl_ch(bb, api->central_ch, api->band, HW_PHY_1); + halbb_ctrl_bw(bb, api->pri_ch_idx, (enum channel_width)api->bw, + HW_PHY_0); + halbb_ctrl_bw(bb, api->pri_ch_idx, (enum channel_width)api->bw, + HW_PHY_1); + + BB_DBG(bb, DBG_DBG_API, " PSD_finish\n\n"); + + /*@[Resume pre-AGC and IGI level]*/ + halbb_pre_agc_en(bb, true); + halbb_psd_igi_lv(bb, IGI_DEFAULT); + + psd->psd_in_progress = 0; + + return HALBB_SET_SUCCESS; +} + +void halbb_psd_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + HALBB_SCAN(input[1], DCMD_DECIMAL, &var1[0]); + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {0:I,1:Q,2:IQ} {fft_point: 128/256/512/1024}\n{path_sel 0~3} {00: dout_sub20_0_40M, 01: ccx_in, 10: dout_cfir, 11: rxdib_in} {CH} {BW 20/40/80: 0/1/2}\n\n"); + + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{1} {IGI_lv(0:4)} {start_point} {stop_point}\n"); + + } else if (var1[0] == 0) { + + for (i = 1; i < 10; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), bw=((%d))\n", + var1[1], var1[2], var1[3], var1[4], var1[5], + var1[6], (u8)var1[7], (u8)var1[8]); + + halbb_psd_para_setting(bb, (u8)var1[1], (u8)var1[2], + (u8)var1[3], (u16)var1[4], (u8)var1[5], + (u8)var1[6], (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var1[1]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &var1[2]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &var1[3]); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "IGI_lv=((0x%x)), start_point=((%d)), stop_point=((%d))\n", + var1[1], var1[2], var1[3]); + + bb->dbg_component |= DBG_DBG_API; + + if (!halbb_psd_alloc_buff(bb)) { + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "memory alloc FAIL\n"); + return; + } + + if (halbb_psd(bb, (enum igi_lv_sel)var1[1], (u16)var1[2], + (u16)var1[3]) == HALBB_SET_FAIL) + BB_DBG_CNSL(out_len, used, output + used, + out_len - used, "PSD_SET_FAIL\n"); + + bb->dbg_component &= ~(DBG_DBG_API); + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_psd_init(struct bb_info *bb) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__); + psd->psd_in_progress = false; + psd->psd_reg = 0x1150; + psd->psd_report_reg = 0x40b4; + psd->psd_pwr_common_offset = 0; + psd->fft_point_pre = 0; + halbb_psd_para_setting(bb, 1, 3, 2, 512, 0, 0, 36, 0); +} + +void halbb_psd_deinit(struct bb_info *bb) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + if (psd->rpt) + halbb_mem_free(bb, psd->rpt, sizeof(psd->rpt)); +} + +bool halbb_get_psd_result(struct bb_info *bb, u8 *psd_data, u16 *psd_len) +{ + struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; + + if (!psd->rpt) + return false; + + psd_data = psd->rpt; + *psd_len = psd->fft_point; + return true; +} + +void halbb_cr_cfg_psd_init(struct bb_info *bb) +{ + struct bb_psd_cr_info *cr = &bb->bb_cmn_hooker->bb_psd_i.bb_psd_cr_i; + + switch (bb->cr_type) { + + #ifdef HALBB_52AA_SERIES + case BB_52AA: + cr->fft_idx = PSD_FFT_IDX_52AA; + cr->fft_idx_m = PSD_FFT_IDX_52AA_M; + cr->psd_en = PSD_ENABLE_52AA; + cr->psd_en_m = PSD_ENABLE_52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->fft_idx = PSD_FFT_IDX_A; + cr->fft_idx_m = PSD_FFT_IDX_A_M; + cr->psd_en = PSD_ENABLE_A; + cr->psd_en_m = PSD_ENABLE_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->fft_idx = PSD_FFT_IDX_C; + cr->fft_idx_m = PSD_FFT_IDX_C_M; + cr->psd_en = PSD_ENABLE_C; + cr->psd_en_m = PSD_ENABLE_C_M; + break; + #endif + + default: + break; + } + +} +#endif diff --git a/phl/hal_g6/phy/bb/halbb_psd.h b/phl/hal_g6/phy/bb/halbb_psd.h new file mode 100644 index 0000000..3415691 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_psd.h @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PSD_H__ +#define __HALBB_PSD_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum igi_lv_sel { + IGI_DEFAULT = 0,/*@default value*/ + IGI_LEVEL1 = 1, + IGI_LEVEL2 = 2, + IGI_LEVEL3 = 3, + IGI_LEVEL4 = 4 +}; +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_psd_cr_info { + u32 psd_en; + u32 psd_en_m; + u32 fft_idx; + u32 fft_idx_m; +}; + +struct bb_psd_info { + struct bb_psd_cr_info bb_psd_cr_i; + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u8 hw_avg_time; + u16 sw_avg_time; + u16 fft_point; + u16 fft_point_pre; + u32 rf_0x18_bkp; + u32 rf_0x18_bkp_b; + u8 psd_fc_ch; + u32 psd_bw; + u8 psd_result[128]; + u8 i_q_setting; + u8 path; + u8 bw; + u8 input; + u8 noise_k_en; + u8 lna_bkp; + u8 lna_bkp_b; + u8 tia_bkp; + u8 tia_bkp_b; + u8 rxbb_bkp; + u8 rxbb_bkp_b; + u32 igi_pin; + u8 *rpt; + enum band_type psd_band; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv); +u32 halbb_get_psd_data(struct bb_info *bb, u32 psd_tone_idx, u32 igi_pin); +void halbb_psd_para_setting(struct bb_info *bb, u8 sw_avg_time, u8 hw_avg_time, + u8 i_q_setting, u16 fft_point, u8 path, + u8 psd_input, u8 channel, u8 bw); +bool halbb_psd_alloc_buff(struct bb_info *bb); +void halbb_get_gain_index(struct bb_info *bb); +u8 halbb_psd(struct bb_info *bb, enum igi_lv_sel igi, u16 start_point, + u16 stop_point); +void halbb_psd_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_psd_init(struct bb_info *bb); +void halbb_psd_deinit(struct bb_info *bb); +bool halbb_get_psd_result(struct bb_info *bb, u8 *psd_data, u16 *psd_len); +void halbb_cr_cfg_psd_init(struct bb_info *bb); +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_pwr_ctrl.c b/phl/hal_g6/phy/bb/halbb_pwr_ctrl.c new file mode 100644 index 0000000..d472a6d --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pwr_ctrl.c @@ -0,0 +1,955 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_PWR_CTRL_SUPPORT +/* @ Dynamic CCA TH part */ + +void halbb_set_ccath_macid(struct bb_info *bb, u16 macid, s8 cca_th, bool cca_th_en) +{ + u32 ret_v = 0; + u32 mask_ccath = 0xff0000; + u32 mask_en = BIT(26); + struct rtw_phl_stainfo_t *phl_sta_i = NULL; + enum phl_band_idx hw_band; + u32 reg_ofst = REG_PWRMACID_OFST + (macid << 2) + 0xd200; + + if (!bb->sta_exist[macid]) { + BB_WARNING("Error Set Pwr Macid for STA not exist!!\n"); + return; + } + + phl_sta_i = bb->phl_sta_info[macid]; + + if (!phl_sta_i) + return; + + //phl_sta_i = bb->phl_sta_info[macid]; + hw_band = phl_sta_i->wrole->hw_band; + /* pwr : S(8,1)*/ + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_ccath, cca_th); + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_en, cca_th_en); + BB_DBG(bb, DBG_PWR_CTRL, "halbb_set_ccath_macid = %x %x\n", cca_th, cca_th_en); + if (ret_v != 0) + BB_WARNING("Error Set Pwr Macid for API return fail!!\n"); +} + +void halbb_ccath_init(struct bb_info *bb) +{ + u8 i; + struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i; + + BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__); + dyncca_i->dyncca_offset = 10; /* clean */ + dyncca_i->dyncca_offset_n = 6; /* noisy */ + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + dyncca_i->macidcca_i[i].cca_th = 0; + dyncca_i->macidcca_i[i].cca_th_en= 0; + } +} + +void halbb_cca_th_per_sta(struct bb_info *bb, u16 macid) +{ + bool noisy_state = bb->is_noisy; + struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i; + s8 dyn_ccath = 0; + s8 offset = dyncca_i->dyncca_offset; + struct rtw_phl_stainfo_t *sta; + u8 rssi = 0; + + #if 0 + if (!dyncca_i) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n"); + return; + } + #endif + + sta = bb->phl_sta_info[macid]; + if (!sta) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n"); + return; + } + if (!is_sta_active(sta)) + return; + + rssi = sta->hal_sta->rssi_stat.rssi; + + if (noisy_state) + offset = dyncca_i->dyncca_offset_n; + + dyn_ccath = (s8)rssi - 110 - offset; +} + +void halbb_dyncca_th(struct bb_info *bb) +{ + struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i; + u8 i; + + if (!dyncca_i) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n"); + return; + } + if (!dyncca_i->dyncca_en) + return; + /* Need to add support ability here */ + /*if (!(bb->support_ability & BB_PWR_CTRL)) + return; + */ + BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__); + + for (i = 0; i < PHL_MAX_STA_NUM; i++) + halbb_cca_th_per_sta( bb, i); +} + +/* @ Power Ctrl part */ +s8 halbb_get_pwr_macid_idx(struct bb_info *bb, u16 macid, u8 idx) +{ + s8 tx_pwr = 0; + struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid]; + + if (!dtp) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer macid = %d\n", macid); + return 0; + } + + tx_pwr = dtp->pwr_val[idx]; + return tx_pwr; /* S(8,1)*/ +} + +bool halbb_get_pwr_macid_en_idx(struct bb_info *bb, u16 macid, u8 idx) +{ + bool pwr_en = false; + struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid]; + + if (!dtp) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer macid = %d\n", macid); + return 0; + } + pwr_en = dtp->en_pwr[idx]; + return pwr_en; /* bool*/ +} + +void halbb_set_pwr_macid_idx(struct bb_info *bb, u16 macid, s8 pwr, bool pwr_en, u8 idx) +{ + u32 ret_v = 0; + u32 mask_pwr = 0xff; + u32 mask_en = BIT(24); + struct rtw_phl_stainfo_t *phl_sta_i = NULL; + enum phl_band_idx hw_band; + u32 reg_ofst = REG_PWRMACID_OFST + (macid << 2) + 0xd200; + + if (!bb->sta_exist[macid]) { + BB_WARNING("Error Set Pwr Macid for STA not exist!!\n"); + return; + } + phl_sta_i = bb->phl_sta_info[macid]; + if (!phl_sta_i) + return; + //phl_sta_i = bb->phl_sta_info[macid]; + + if (idx == 1) { + mask_pwr = 0x0000ff00; + mask_en = BIT(25); + } + + hw_band = phl_sta_i->wrole->hw_band; + /* pwr : S(8,1)*/ + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_pwr, pwr); + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_en, pwr_en); + BB_DBG(bb, DBG_PWR_CTRL, "halbb_set_pwr_macid(%d) = %x %x\n", idx, pwr, pwr_en); + if (ret_v != 0) + BB_WARNING("Error Set Pwr Macid for API return fail!!\n"); +} + +void halbb_pwr_ctrl_en(struct bb_info *bb, bool pwr_ctrl_en) +{ + u32 ret_v = 0; + u32 mask_en = BIT(29); + u32 reg_ofst = 0xd20c; + + BB_DBG(bb, DBG_PWR_CTRL, "halbb_pwr_ctrl_en() = %x\n", (u32)pwr_ctrl_en); + + if(pwr_ctrl_en) { + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, reg_ofst, mask_en, 0x1); + if (bb->hal_com->dbcc_en) + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 1, reg_ofst, mask_en, 0x1); + } else { + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, reg_ofst, mask_en, 0x0); + if (bb->hal_com->dbcc_en) + ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 1, reg_ofst, mask_en, 0x0); + } + + if (ret_v != 0) + BB_WARNING("Error Enable Power Control for API return fail!!\n"); +} +void halbb_pwr_ctrl_th(struct bb_info *bb) +{ + bool noisy_state = bb->is_noisy; + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + if (!pwr_ctrl_i) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n"); + return; + } + + if (noisy_state == 0) { + pwr_ctrl_i->enhance_pwr_th[0] = pwr_ctrl_i->set_pwr_th[0]; + pwr_ctrl_i->enhance_pwr_th[1] = pwr_ctrl_i->set_pwr_th[1]; + pwr_ctrl_i->enhance_pwr_th[2] = pwr_ctrl_i->set_pwr_th[2]; + } else { + pwr_ctrl_i->enhance_pwr_th[0] = pwr_ctrl_i->set_pwr_th[0] + 8; + pwr_ctrl_i->enhance_pwr_th[1] = pwr_ctrl_i->set_pwr_th[1] + 5; + pwr_ctrl_i->enhance_pwr_th[2] = pwr_ctrl_i->set_pwr_th[2]; + } + + BB_DBG(bb, DBG_PWR_CTRL, + "halbb pwr ctrl pwr_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n", + pwr_ctrl_i->enhance_pwr_th[0], pwr_ctrl_i->enhance_pwr_th[1], + pwr_ctrl_i->enhance_pwr_th[2]); +} + +u8 halbb_pwr_lvl_check(struct bb_info *bb, u8 rssi_in, u8 last_pwr_lvl) +{ + u8 i; + u8 th[HALBB_PWR_STATE_NUM]; + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + if (!pwr_ctrl_i) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n"); + return 0; + } + + for (i = 0; i < HALBB_PWR_STATE_NUM; i++) + th[i] = pwr_ctrl_i->set_pwr_th[i]; + + BB_DBG(bb, DBG_PWR_CTRL, + "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n", + th[0], th[1], th[2]); + + for (i = 0; i < HALBB_PWR_STATE_NUM; i++) { + if (i >= last_pwr_lvl) + th[i] += DTP_FLOOR_UP_GAP; + } + BB_DBG(bb, DBG_PWR_CTRL, + "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n", + th[0], th[1], th[2]); + + if (rssi_in >= th[2]) + return TX_HP_LV_3; + else if (rssi_in < (th[2] - 3) && rssi_in >= th[1]) + return TX_HP_LV_2; + else if (rssi_in < (th[1] - 3) && rssi_in >= th[0]) + return TX_HP_LV_1; + else if (rssi_in < (th[0] - 3)) + return TX_HP_LV_0; + else + return TX_HP_LV_UNCHANGE; +} + +void halbb_set_pwr_ctrl(struct bb_info *bb, u16 macid, u8 pwr_lv) +{ + struct rtw_phl_stainfo_t *sta; + s8 pwr = 0; + bool pwr_ctrl_en = false; + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + if (!(bb->support_ability & BB_PWR_CTRL)) + return; + + sta = bb->phl_sta_info[macid]; + if (!sta) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n"); + return; + } + + if (pwr_lv == TX_HP_LV_3) { + pwr_ctrl_en = true; + pwr = pwr_ctrl_i->pwr_lv_dbm[2]; + } else if (pwr_lv == TX_HP_LV_2) { + pwr_ctrl_en = true; + pwr = pwr_ctrl_i->pwr_lv_dbm[1]; + } else if (pwr_lv == TX_HP_LV_1) { + pwr_ctrl_en = true; + pwr = pwr_ctrl_i->pwr_lv_dbm[0]; + } else { + pwr_ctrl_en = false; + pwr = 0; + } + halbb_set_pwr_macid_idx(bb, macid, pwr, pwr_ctrl_en, 0); + /* only use pwr_tbl_0 */ +} + +void halbb_pwr_ctrl_per_sta(struct bb_info *bb, u16 macid) +{ + struct rtw_phl_stainfo_t *sta; + struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid]; + u8 lst_pwr_lv = 0; + u8 rssi = 0; + + sta = bb->phl_sta_info[macid]; + if (!sta) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n"); + return; + } + if (is_sta_active(sta)) { + rssi = (sta->hal_sta->rssi_stat.rssi) >> 1; + lst_pwr_lv = dtp->last_pwr_lvl; + dtp->dyn_tx_pwr_lvl = halbb_pwr_lvl_check(bb, rssi, lst_pwr_lv); + BB_DBG(bb, DBG_PWR_CTRL, + "STA=%d , RSSI: %d , GetPwrLv: %d\n", macid, + rssi, dtp->dyn_tx_pwr_lvl); + + if (dtp->dyn_tx_pwr_lvl == TX_HP_LV_UNCHANGE || + dtp->dyn_tx_pwr_lvl == lst_pwr_lv) { + dtp->dyn_tx_pwr_lvl = lst_pwr_lv; + BB_DBG(bb, DBG_PWR_CTRL, + "DTP_lv not change: ((%d))\n", + dtp->dyn_tx_pwr_lvl); + return; + } + + BB_DBG(bb, DBG_PWR_CTRL, + "DTP_lv update: ((%d)) -> ((%d))\n", lst_pwr_lv, + dtp->dyn_tx_pwr_lvl); + + dtp->last_pwr_lvl = dtp->dyn_tx_pwr_lvl; + halbb_set_pwr_ctrl(bb, macid, dtp->dyn_tx_pwr_lvl); + } +} + +void halbb_pwr_ctrl(struct bb_info *bb) +{ + struct bb_pwr_ctrl_info *pwr_ctrl = &bb->bb_pwr_ctrl_i; + u16 i; + + if (!(bb->support_ability & BB_PWR_CTRL)) { + /* Disable*/ + halbb_pwr_ctrl_en(bb, false); + return; + } + + BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__); + /*Enable*/ + halbb_pwr_ctrl_en(bb, true); + for (i = 0; i < PHL_MAX_STA_NUM; i++) + halbb_pwr_ctrl_per_sta( bb, i); + + BB_DBG(bb, DBG_PWR_CTRL, "pwr = %d\n", pwr_ctrl->pwr); +} +void halbb_pwr_ctrl_para_init(struct bb_info *bb) +{ + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + pwr_ctrl_i->set_pwr_th[0] = TX_PWR_TH_LVL1; + pwr_ctrl_i->set_pwr_th[1] = TX_PWR_TH_LVL2; + pwr_ctrl_i->set_pwr_th[2] = TX_PWR_TH_LVL3; + + pwr_ctrl_i->pwr_lv_dbm[0] = TX_PWR_LVL1; + pwr_ctrl_i->pwr_lv_dbm[1] = TX_PWR_LVL2; + pwr_ctrl_i->pwr_lv_dbm[2] = TX_PWR_LVL3; +} + +void halbb_pwr_ctrl_txpwr_cfg(struct bb_info *bb, u8 pwr_lv1, u8 pwr_lv2, u8 pwr_lv3) +{ + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + pwr_ctrl_i->pwr_lv_dbm[0] = pwr_lv1; + pwr_ctrl_i->pwr_lv_dbm[1] = pwr_lv2; + pwr_ctrl_i->pwr_lv_dbm[2] = pwr_lv3; +} + +void halbb_pwr_ctrl_th_cfg(struct bb_info *bb, u8 th_lv1, u8 th_lv2, u8 th_lv3) +{ + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + pwr_ctrl_i->set_pwr_th[0] = th_lv1; + pwr_ctrl_i->set_pwr_th[1] = th_lv2; + pwr_ctrl_i->set_pwr_th[2] = th_lv3; +} + +void halbb_pwr_ctrl_init(struct bb_info *bb) +{ + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + u8 i = 0; + + if (!pwr_ctrl_i) { + BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n"); + return; + } + + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + pwr_ctrl_i->dtp_i[i].last_pwr_lvl= TX_HP_LV_0; + pwr_ctrl_i->dtp_i[i].dyn_tx_pwr_lvl= TX_HP_LV_0; + } + + halbb_pwr_ctrl_para_init(bb); + + for (i = 0; i < HALBB_PWR_STATE_NUM; i++) + pwr_ctrl_i->enhance_pwr_th[i] = 0xff; + + BB_DBG(bb, DBG_PWR_CTRL, "pwr = %d\n", pwr_ctrl_i->pwr); +} + +void halbb_pwr_ctrl_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u32 val[10] = {0}; + u8 i = 0; + struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i; + + if (_os_strcmp(input[1], help) == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{Use Org TH and PWR} [pwr_ctrl] [0]\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{Modify LV1(H)~LV3(L) Power} [pwr_ctrl] [1] [LV1] [LV2] [LV3]\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{Modify LV1(H)~LV3(L) TH} [pwr_ctrl] [2] [LV1] [LV2] [LV3]\n"); + return; + } + for (i = 0; i < 8; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + switch (val[0]) { + case 0: + halbb_pwr_ctrl_para_init(bb); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Reset Parameters\n"); + break; + case 1: + halbb_pwr_ctrl_txpwr_cfg(bb, (u8)val[1], (u8)val[2], (u8)val[3]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "PWRCTRL TxPWR for each LV = {%d, %d, %d}\n", + pwr_ctrl_i->pwr_lv_dbm[0], pwr_ctrl_i->pwr_lv_dbm[1], + pwr_ctrl_i->pwr_lv_dbm[2]); + break; + case 2: + halbb_pwr_ctrl_th_cfg(bb, (u8)val[1], (u8)val[2], (u8)val[3]); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "PWRCTRL TH for each LV = {%d, %d, %d}\n", + pwr_ctrl_i->set_pwr_th[0], pwr_ctrl_i->set_pwr_th[1], + pwr_ctrl_i->set_pwr_th[2]); + break; + default: + break; + } +} + +#endif + + +bool halbb_set_pwr_ul_tb_ofst(struct bb_info *bb, s16 pw_ofst, + enum phl_phy_idx phy_idx) +{ + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + halbb_set_pwr_ul_tb_ofst_8852a_2(bb, pw_ofst, phy_idx); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + halbb_set_pwr_ul_tb_ofst_8852b(bb, pw_ofst, phy_idx); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + halbb_set_pwr_ul_tb_ofst_8852c(bb, (s8)pw_ofst, phy_idx); + break; + #endif + + default: + break; + } + + return true; +} + +void halbb_macid_ctrl_init(struct bb_info *bb) +{ + u8 i = 0; + u32 reg_ofst = 0; + u32 ret_v = 0; + + BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__); + if (bb->hal_com == NULL) { + BB_WARNING("hal_com is not allocated in halbb_macid_ctrl_init!!\n"); + return; + } + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + reg_ofst = REG_PWRMACID_OFST + (i<<2) + 0xd200; + ret_v = rtw_hal_mac_set_pwr_reg( bb->hal_com, 0, reg_ofst, 0); + if (bb->hal_com->dbcc_en) + ret_v = rtw_hal_mac_set_pwr_reg( bb->hal_com, 1, reg_ofst, 0); + } +} + +void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx) + { + u32 tpu_array_type1[] = {0xD248, 0x07763333, + 0xD220, 0x01ebf004, + 0xD240, 0x0002f8ff}; + u32 *tpu_array = NULL; + u8 cr_size = 0; + u8 i = 0; + enum phl_band_idx band; + + band = (phy_idx == HW_PHY_0) ? HW_BAND_0 : HW_BAND_1; + + switch (bb->ic_type) { + + #if defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) + case BB_RTL8852A: + case BB_RTL8852B: + tpu_array = (u32 *)tpu_array_type1; + cr_size = sizeof(tpu_array_type1)/sizeof(u32); + break; + #endif + default: + break; + } + + BB_DBG(bb, DBG_INIT, "[%s] size=%d\n", __func__, cr_size >> 1); + + if (!tpu_array) { + BB_WARNING("[%s]\n", __func__); + return; + } + + for (i = 0; i < cr_size; i+=2) { + BB_DBG(bb, DBG_INIT, "0x%x = 0x%x\n", tpu_array[i], tpu_array[i+1]); + rtw_hal_mac_set_pwr_reg(bb->hal_com, band, tpu_array[i], tpu_array[i+1]); + } +} + +void halbb_pwr_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_tpu_info *tpu = &bb->hal_com->band[bb->bb_phy_idx].rtw_tpu_i; + struct rtw_tpu_pwr_by_rate_info *by_rate = &tpu->rtw_tpu_pwr_by_rate_i; + struct rtw_tpu_pwr_imt_info *lmt = &tpu->rtw_tpu_pwr_imt_i; + bool rpt_tmp; + u16 size_tmp = 0; + u32 val[10] = {0}; + u16 i = 0, j = 0; + u8 rate_idx = 0, path = 0; + s8 *tmp_s8, val_s8; + + if (_os_strcmp(input[1], "-h") == 0) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dbg_en {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "show\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set all {s(7,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set lgcy {idx} {s(7,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "set mcs {path:0~3} {idx} {s(7,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ofst bw {all:255, 0~4: 80_80/160/80/40/20} {0:+, 1:-} {u(3,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ofst mode {all:255 0~4: HE/VHT/HT/Legacy/CCK} {0:+, 1:-} {u(3,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ref {cck, ofdm} {s(9,2) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ref ofst {s(8,3) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "cw {0:rf_0db_cw(39), 1:tssi_16dBm_cw(300)} {val}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "lmt en {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "lmt {all, ru_all} {s(7,1) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tb_ofst {s(5,0) dB}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tx_shap {ch} {shap_idx} {is_ofdm}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tpu 0\n"); + + return; + } + if (_os_strcmp(input[1], "tpu") == 0) { + halbb_set_tx_pow_ref(bb, bb->bb_phy_idx); + rtw_hal_mac_write_pwr_by_rate_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + rtw_hal_mac_write_pwr_limit_rua_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + rtw_hal_mac_write_pwr_limit_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + rtw_hal_mac_write_pwr_ofst_mode(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + rtw_hal_mac_write_pwr_ofst_bw(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set all TPU component\n"); + } else if (_os_strcmp(input[1], "dbg_en") == 0) { + HALBB_SCAN(input[2], DCMD_HEX, &val[0]); + rtw_hal_mac_set_tpu_mode(bb->hal_com, (enum rtw_tpu_op_mode)val[0], bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "dbg_en=%d, Locking driver set TPU = %d\n", val[0], tpu->normal_mode_lock_en); + } else if (_os_strcmp(input[1], "show") == 0) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[PW Ref]\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%d}\n", "[base_cw_0db]", tpu->base_cw_0db); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%s dB}\n", "[ref_ofst]", + halbb_print_sign_frac_digit2(bb, tpu->ofst_int, 8, 3)); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%s dBm} pw_cw=0x%03x\n", "[CCK]", + halbb_print_sign_frac_digit2(bb, tpu->ref_pow_cck, 16, 2), + tpu->ref_pow_cck_cw); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%s dBm} pw_cw=0x%03x\n", "[OFDM]", + halbb_print_sign_frac_digit2(bb, tpu->ref_pow_ofdm, 16, 2), + tpu->ref_pow_ofdm_cw); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[PW Offset] (s41)\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-20s {%02d, %02d, %02d, %02d, %02d}\n", "[AX/AC/N/G/B]", + tpu->pwr_ofst_mode[0], tpu->pwr_ofst_mode[1], + tpu->pwr_ofst_mode[2], tpu->pwr_ofst_mode[3], + tpu->pwr_ofst_mode[4]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-20s {%02d, %02d, %02d, %02d, %02d}\n", "[80_80/160/80/40/20]", + tpu->pwr_ofst_bw[0], tpu->pwr_ofst_bw[1], + tpu->pwr_ofst_bw[2], tpu->pwr_ofst_bw[3], + tpu->pwr_ofst_bw[4]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Pwr By Rate] (s71)\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%02d, %02d, %02d, %02d}\n", "[CCK]", + by_rate->pwr_by_rate_lgcy[0], by_rate->pwr_by_rate_lgcy[1], + by_rate->pwr_by_rate_lgcy[2], by_rate->pwr_by_rate_lgcy[3]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s {%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n","[Lgcy]", + by_rate->pwr_by_rate_lgcy[4], by_rate->pwr_by_rate_lgcy[5], + by_rate->pwr_by_rate_lgcy[6], by_rate->pwr_by_rate_lgcy[7], + by_rate->pwr_by_rate_lgcy[8], by_rate->pwr_by_rate_lgcy[9], + by_rate->pwr_by_rate_lgcy[10], by_rate->pwr_by_rate_lgcy[11]); + for (i = 0; i < HAL_MAX_PATH; i++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%d]%-7s {%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n", + i, "[OFDM]", + by_rate->pwr_by_rate[i][0], by_rate->pwr_by_rate[i][1], + by_rate->pwr_by_rate[i][2], by_rate->pwr_by_rate[i][3], + by_rate->pwr_by_rate[i][4], by_rate->pwr_by_rate[i][5], + by_rate->pwr_by_rate[i][6], by_rate->pwr_by_rate[i][7], + by_rate->pwr_by_rate[i][8], by_rate->pwr_by_rate[i][9], + by_rate->pwr_by_rate[i][10], by_rate->pwr_by_rate[i][11]); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%d]%-7s {%02d, %02d, %02d, %02d}\n", + i,"[DCM]", + by_rate->pwr_by_rate[i][12], by_rate->pwr_by_rate[i][13], + by_rate->pwr_by_rate[i][14], by_rate->pwr_by_rate[i][15]); + } + + for (j = 0; j < TPU_SIZE_BF; j++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Pwr Lmt][%sBF]\n", (j == 0) ? "non-" : ""); + + for (i = 0; i < HAL_MAX_PATH; i++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d}\n", "[CCK-20M]", + i, lmt->pwr_lmt_cck_20m[i][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d}\n", "[CCK-40M]", + i, lmt->pwr_lmt_cck_40m[i][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d}\n", "[Lgcy-20M]", + i, lmt->pwr_lmt_lgcy_20m[i][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n", "[OFDM-20M]", + i, lmt->pwr_lmt_20m[i][0][j], lmt->pwr_lmt_20m[i][1][j], + lmt->pwr_lmt_20m[i][2][j], lmt->pwr_lmt_20m[i][3][j], + lmt->pwr_lmt_20m[i][4][j], lmt->pwr_lmt_20m[i][5][j], + lmt->pwr_lmt_20m[i][6][j], lmt->pwr_lmt_20m[i][7][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d, %02d, %02d, %02d}\n", "[OFDM-40M]", + i, lmt->pwr_lmt_40m[i][0][j], lmt->pwr_lmt_40m[i][1][j], + lmt->pwr_lmt_40m[i][2][j], lmt->pwr_lmt_40m[i][3][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d, %02d}\n", "[OFDM-80M]", + i, lmt->pwr_lmt_80m[i][0][j], lmt->pwr_lmt_80m[i][1][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s[%d]{%02d}\n", "[OFDM-160M]", + i, lmt->pwr_lmt_160m[i][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d}\n", "[40m_0p5]", + i, lmt->pwr_lmt_40m_0p5[i][j]); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d}\n", "[40m_2p5]", + i, lmt->pwr_lmt_40m_2p5[i][j]); + + } + } + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Pwr Lmt RUA]\n"); + + for (j = 0; j < TPU_SIZE_RUA; j++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[RU-%3d]\n", (j == 0) ? 26 : ((j == 1) ? 52 : 106)); + for (i = 0; i < HAL_MAX_PATH; i++) { + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s [%d]{%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n", "[OFDM-20M]", + i, tpu->pwr_lmt_ru[i][j][0], tpu->pwr_lmt_ru[i][j][1], + tpu->pwr_lmt_ru[i][j][2], tpu->pwr_lmt_ru[i][j][3], + tpu->pwr_lmt_ru[i][j][4], tpu->pwr_lmt_ru[i][j][5], + tpu->pwr_lmt_ru[i][j][6], tpu->pwr_lmt_ru[i][j][7]); + } + } + BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used, + "================\n\n"); + } else if (_os_strcmp(input[1], "cw") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + if (val[0] == 0) { + tpu->base_cw_0db = (u8)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "rf_cw_0dbm=%d\n", tpu->base_cw_0db); + } else if (val[0] == 1) { + tpu->tssi_16dBm_cw = (u16)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "tssi_16dBm_cw=%d\n", tpu->tssi_16dBm_cw); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + halbb_set_tx_pow_ref(bb, bb->bb_phy_idx); + } else if (_os_strcmp(input[1], "ofst") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + + if (val[1] == 0) { + if (val[2] > 7) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Set Err] max = +3.5 dB\n"); + return; + } + + val_s8 = (s8)val[2]; + } else { + if (val[2] > 8) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Set Err] max = -4 dB\n"); + return; + } + val_s8 = (s8)val[2] * -1; + } + + if (_os_strcmp(input[2], "bw") == 0) { + if (val[0] == 255) { + for (i = 0; i < TPU_SIZE_BW; i++) + tpu->pwr_ofst_bw[i] = val_s8; + + } else if (val[0] >= TPU_SIZE_BW) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } else { + tpu->pwr_ofst_bw[val[0]] = val_s8; + } + rtw_hal_mac_write_pwr_ofst_bw(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + } else if (_os_strcmp(input[2], "mode") == 0) { + if (val[0] == 255) { + for (i = 0; i < TPU_SIZE_MODE; i++) + tpu->pwr_ofst_mode[i] = val_s8; + + } else if (val[0] >= TPU_SIZE_MODE) { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } else { + tpu->pwr_ofst_mode[val[0]] = val_s8; + } + rtw_hal_mac_write_pwr_ofst_mode(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[%s]pw ofst[%d]=(%s%d.%d)dB\n", + (_os_strcmp(input[2], "bw") == 0) ? "BW" : "MODE", + val[0], (val[1] == 0) ? "+" : "-", + val[2] >> 1, (val[2] & 0x1) * 5); + } else if (_os_strcmp(input[1], "ref") == 0) { + if (_os_strcmp(input[2], "ofst") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "ref_ofst=(%s)dB\n", + halbb_print_sign_frac_digit2(bb, tpu->ofst_int, 8, 3)); + } else { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + if (_os_strcmp(input[2], "ofdm") == 0) { + tpu->ref_pow_ofdm = (s16)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s ref_pw={%s dBm} cw=0x%09x\n", "[OFDM]", + halbb_print_sign_frac_digit2(bb, tpu->ref_pow_ofdm, 16, 2), + tpu->ref_pow_ofdm_cw); + } else if (_os_strcmp(input[2], "cck") == 0) { + tpu->ref_pow_cck = (s16)val[0]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "%-10s ref_pw={%s dBm} cw=0x%09x\n", "[CCK]", + halbb_print_sign_frac_digit2(bb, tpu->ref_pow_cck, 16, 2), + tpu->ref_pow_cck_cw); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + //halbb_print_sign_frac_digit2(bb, val[0], 32, 2); + //BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, "ref_pw = (%s)dBm\n", bb->dbg_buf); + } + halbb_set_tx_pow_ref(bb, bb->bb_phy_idx); + } else if (_os_strcmp(input[1], "set") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]); + if (_os_strcmp(input[2], "lgcy") == 0) { + rate_idx = (u8)val[0]; + if (rate_idx > TPU_SIZE_PWR_TAB_lGCY) + return; + + tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate_lgcy[rate_idx] = (s8)val[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[TX Pw] lgcy[%d] = (%d.%d)dBm\n", rate_idx, val[1]>>1, (val[1] & 1)*5); + } else if (_os_strcmp(input[2], "mcs") == 0) { + path = (u8)val[0]; + if (path > HAL_MAX_PATH) + return; + rate_idx = (u8)val[1]; + if (rate_idx > TPU_SIZE_PWR_TAB) + return; + + tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate[path][rate_idx] = (s8)val[2]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[TX Pw] Path[%d] MCS[%d] = (%d.%d)dBm\n", path, rate_idx, val[2]>>1, (val[2] & 1)*5); + } else if (_os_strcmp(input[2], "all") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + for (i = 0; i < TPU_SIZE_PWR_TAB_lGCY; i++) + tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate_lgcy[i] = (s8)val[0]; + + for (i = 0; i < HAL_MAX_PATH; i++) { + for (j = 0; j < TPU_SIZE_PWR_TAB; j++) + tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate[i][j] = (s8)val[0]; + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[TX Pw] All rate = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5); + + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + rtw_hal_mac_write_pwr_by_rate_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + } else if (_os_strcmp(input[1], "lmt") == 0) { + if (_os_strcmp(input[2], "en") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + + tpu->pwr_lmt_en = (bool)val[0]; + rtw_hal_mac_write_pwr_limit_en(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pwr_lmt_en = %d\n", tpu->pwr_lmt_en); + } else if (_os_strcmp(input[2], "all") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + + size_tmp = sizeof(struct rtw_tpu_pwr_imt_info) / sizeof(s8); + tmp_s8 = &lmt->pwr_lmt_cck_20m[0][0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pwr_lmt_size = %d\n", size_tmp); + + for (i = 0; i < size_tmp; i++) { + *tmp_s8 = (u8)val[0]; + tmp_s8++; + } + rtw_hal_mac_write_pwr_limit_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set all Pwr Lmt = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5); + + } else if (_os_strcmp(input[2], "ru_all") == 0) { + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]); + + size_tmp = HAL_MAX_PATH * TPU_SIZE_RUA * TPU_SIZE_BW20_SC; + tmp_s8 = &tpu->pwr_lmt_ru[0][0][0]; + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "pwr_lmt_size_ru = %d\n", size_tmp); + + for (i = 0; i < size_tmp; i++) { + *tmp_s8 = (s8)val[0]; + tmp_s8++; + } + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set all RUA Pwr Lmt = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5); + rtw_hal_mac_write_pwr_limit_rua_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + return; + } + } else if (_os_strcmp(input[1], "tb_ofst") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + + rpt_tmp = halbb_set_pwr_ul_tb_ofst(bb, (s16)val[0], bb->bb_phy_idx); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[ULTB Ofst]Set succcess=%d, en = %d, pw_ofst=%d\n", + rpt_tmp, val[0], (s16)val[1]); + } else if (_os_strcmp(input[1], "tx_shap") == 0) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]); + HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]); + HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]); + + tpu->tx_ptrn_shap_idx = (u8)val[1]; + halbb_set_tx_pow_pattern_shap(bb, (u8)val[0], (bool)val[2], bb->bb_phy_idx); + + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Tx Shap] ch=%d, shap_idx=%d\n", val[0], tpu->tx_ptrn_shap_idx); + } else { + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Set Err\n"); + } +} diff --git a/phl/hal_g6/phy/bb/halbb_pwr_ctrl.h b/phl/hal_g6/phy/bb/halbb_pwr_ctrl.h new file mode 100644 index 0000000..0a6f0cf --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pwr_ctrl.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PWR_CTRL_H__ +#define __HALBB_PWR_CTRL_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define REG_PWRMACID_OFST 0x0016c +#define HALBB_PWR_STATE_NUM 3 +#define DTP_FLOOR_UP_GAP 3 +#define TX_HP_LV_0 0 +#define TX_HP_LV_1 1 +#define TX_HP_LV_2 2 +#define TX_HP_LV_3 3 +#define TX_HP_LV_UNCHANGE 4 +/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ +#define TX_PWR_TH_LVL3 87 +#define TX_PWR_TH_LVL2 73 +#define TX_PWR_TH_LVL1 62 +/*#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define TX_PWR_TH_LVL3 90 +#define TX_PWR_TH_LVL2 85 +#define TX_PWR_TH_LVL1 80 +#endif*/ +#define TX_PWR_LVL3 6 /*3dBm*/ +#define TX_PWR_LVL2 12 /*6dBm*/ +#define TX_PWR_LVL1 20 /*10dBm*/ +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ +/* @ Dynamic CCA TH part */ +struct bb_macidcca_info { + bool cca_th_en; + s8 cca_th; +}; + +struct bb_dyncca_info { + /* [] */ + bool dyncca_en; + u8 dyncca_offset; + u8 dyncca_offset_n; + /**/ + struct bb_macidcca_info macidcca_i[PHL_MAX_STA_NUM]; +}; + +/* @ Power Ctrl part */ +struct bb_dtp_info { + /*u8 dyn_tx_power; + u8 last_tx_power;*/ + u8 dyn_tx_pwr_lvl:4; + u8 last_pwr_lvl:4; + + s8 pwr_val[2]; /* S(8,1) */ + bool en_pwr[2]; +}; + +struct bb_pwr_ctrl_info { + u8 pwr; + + /* [] */ + u8 enhance_pwr_th[HALBB_PWR_STATE_NUM]; + u8 set_pwr_th[HALBB_PWR_STATE_NUM]; + u8 pwr_lv_dbm[HALBB_PWR_STATE_NUM]; + /**/ + struct bb_dtp_info dtp_i[PHL_MAX_STA_NUM]; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ +#ifdef HALBB_PWR_CTRL_SUPPORT +void halbb_pwr_ctrl(struct bb_info *bb); +void halbb_pwr_ctrl_init(struct bb_info *bb); +void halbb_set_pwr_macid_idx(struct bb_info *bb, u16 macid, s8 pwr, bool pwr_en, u8 idx); +#endif +void halbb_macid_ctrl_init(struct bb_info *bb); +void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_pwr_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_pwr_ctrl_ex.h b/phl/hal_g6/phy/bb/halbb_pwr_ctrl_ex.h new file mode 100644 index 0000000..ef03b37 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_pwr_ctrl_ex.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_PWR_CTRL_EX_H__ +#define __HALBB_PWR_CTRL_EX_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +bool halbb_set_pwr_ul_tb_ofst(struct bb_info *bb, s16 pw_ofst, + enum phl_phy_idx phy_idx); +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/bb/halbb_ra.c b/phl/hal_g6/phy/bb/halbb_ra.c new file mode 100644 index 0000000..79831c3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ra.c @@ -0,0 +1,2121 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halbb_precomp.h" +#ifdef HALBB_RA_SUPPORT + +const u16 bb_phy_rate_table[] = { + /*CCK*/ + 1, 2, 5, 11, + /*OFDM*/ + 6, 9, 12, 18, 24, 36, 48, 54, + /*HT/VHT-1ss LGI*/ + 6, 13, 19, 26, 39, 52, 58, 65, 78, 87, 98, 108, + /*HT/VHT-2ss LGI*/ + 13, 26, 39, 52, 78, 104, 117, 130, 156, 173, 195, 217, + /*HT/VHT-3ss LGI*/ + 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, 293, 325, + /*HT/VHT-4ss LGI*/ + 26, 52, 78, 104, 156, 208, 234, 260, 312, 347, 390, 433, +}; /*HE[3.2] = VHT[LGI] * 1.125*/ + +bool halbb_is_he_rate(struct bb_info *bb, u16 rate) +{ + return ((((rate & 0x1ff) >= BB_HE_1SS_MCS0) && + ((rate & 0x1ff) <= BB_HE_1SS_MCS(11))) || + (((rate & 0x1ff) >= BB_HE_2SS_MCS0) && + ((rate & 0x1ff) <= BB_HE_2SS_MCS(11))) || + (((rate & 0x1ff) >= BB_HE_3SS_MCS0) && + ((rate & 0x1ff) <= BB_HE_3SS_MCS(11))) || + (((rate & 0x1ff) >= BB_HE_4SS_MCS0) && + ((rate & 0x1ff) <= BB_HE_4SS_MCS(11)))) ? true : false; +} + +bool halbb_is_vht_rate(struct bb_info *bb, u16 rate) +{ + return ((((rate & 0x1ff) >= BB_VHT_1SS_MCS0) && + ((rate & 0x1ff) <= BB_VHT_1SS_MCS(9))) || + (((rate & 0x1ff) >= BB_VHT_2SS_MCS0) && + ((rate & 0x1ff) <= BB_VHT_2SS_MCS(9))) || + (((rate & 0x1ff) >= BB_VHT_3SS_MCS0) && + ((rate & 0x1ff) <= BB_VHT_3SS_MCS(9))) || + (((rate & 0x1ff) >= BB_VHT_4SS_MCS0) && + ((rate & 0x1ff) <= BB_VHT_4SS_MCS(9)))) ? true : false; +} + +bool halbb_is_ht_rate(struct bb_info *bb, u16 rate) +{ + return (((rate & 0x1ff) >= BB_HT_MCS0) && + ((rate & 0x1ff) <= BB_HT_MCS(31))) ? true : false; +} + +bool halbb_is_ofdm_rate(struct bb_info *bb, u16 rate) +{ + return (((rate & 0x1ff) >= BB_06M) && + ((rate & 0x1ff) <= BB_54M)) ? true : false; +} + +bool halbb_is_cck_rate(struct bb_info *bb, u16 rate) +{ + return ((rate & 0x1ff) <= BB_11M) ? true : false; +} + +u8 halbb_legacy_rate_2_spec_rate(struct bb_info *bb, u16 rate) +{ + u8 rate_idx = 0x0; + u8 legacy_spec_rate_t[8] = {BB_SPEC_RATE_6M, BB_SPEC_RATE_9M, + BB_SPEC_RATE_12M, BB_SPEC_RATE_18M, + BB_SPEC_RATE_24M, BB_SPEC_RATE_36M, + BB_SPEC_RATE_48M, BB_SPEC_RATE_54M}; + + rate_idx = rate - BB_06M; + return legacy_spec_rate_t[rate_idx]; +} + +u8 halbb_mgnt_2_hw_rate(u8 rate) +{ + u8 ret = 0; + + /*exclude BSS basic bit*/ + rate &= 0x7f; + + /*a/b/g mode only, there is no requirement for n/ac/ax mode*/ + if (rate > 108) + return ret; + + /*unit:0.5Mbps*/ + switch (rate) { + case 2: + ret = BB_01M; + break; + case 4: + ret = BB_02M; + break; + case 11: + ret = BB_05M; + break; + case 22: + ret = BB_11M; + break; + case 12: + ret = BB_06M; + break; + case 18: + ret = BB_09M; + break; + case 24: + ret = BB_12M; + break; + case 36: + ret = BB_18M; + break; + case 48: + ret = BB_24M; + break; + case 72: + ret = BB_36M; + break; + case 96: + ret = BB_48M; + break; + case 108: + ret = BB_54M; + break; + default: + break; + } + + return ret; +} + +u8 halbb_mcs_ss_to_fw_rate_idx(u8 mode, u8 mcs, u8 ss) +{ + u8 fw_rate_idx = 0; + + if (mode == 3) { + fw_rate_idx = RATE_HE1SS_MCS0 + (ss - 1) * 12; // MAX HE MCS is MCS11 (Totally, 12 MCS index) + } else if (mode == 2) { + fw_rate_idx = RATE_VHT1SS_MCS0 + (ss - 1) * 10; // MAX VHT MCS is MCS9 (Totally, 10 MCS index) + } else if (mode == 1) { // HT + fw_rate_idx = RATE_HT_MCS0 + (ss - 1) * 8; + } else { + fw_rate_idx = 0; + } + + return fw_rate_idx; +} + +void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i) +{ + ra_i->rate_idx_all = rate_idx | (((u16)gi_ltf & 0xf) << 12); + ra_i->rate_idx = rate_idx; + ra_i->gi_ltf = gi_ltf; + ra_i->mode = (enum bb_mode_type)((rate_idx & 0x180) >> 7); + + if (ra_i->mode == BB_LEGACY_MODE) { + ra_i->ss = 1; + ra_i->idx = rate_idx & 0x1f; + } else if (ra_i->mode == BB_HT_MODE) { + ra_i->ss = (ra_i->idx >> 3) + 1; + ra_i->idx = rate_idx & 0x1f; + } else { + ra_i->ss = ((rate_idx & 0x70) >> 4) + 1; + ra_i->idx = rate_idx & 0xf; + } + + /* Transfer to fw used rate_idx*/ + if (ra_i->mode == BB_LEGACY_MODE) { + ra_i->fw_rate_idx = ra_i->idx; + return; + } + + ra_i->fw_rate_idx = halbb_mcs_ss_to_fw_rate_idx(ra_i->mode, ra_i->idx, ra_i->ss); + + return; +} + +u8 halbb_rate_2_rate_digit(struct bb_info *bb, u16 rate) +{ + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_digit = 0; + + if (rate >= BB_HE_8SS_MCS0) + rate_digit = (rate - BB_HE_8SS_MCS0); + else if (rate >= BB_HE_7SS_MCS0) + rate_digit = (rate - BB_HE_7SS_MCS0); + else if (rate >= BB_HE_6SS_MCS0) + rate_digit = (rate - BB_HE_6SS_MCS0); + else if (rate >= BB_HE_5SS_MCS0) + rate_digit = (rate - BB_HE_5SS_MCS0); + else if (rate >= BB_HE_4SS_MCS0) + rate_digit = (rate - BB_HE_4SS_MCS0); + else if (rate >= BB_HE_3SS_MCS0) + rate_digit = (rate - BB_HE_3SS_MCS0); + else if (rate >= BB_HE_2SS_MCS0) + rate_digit = (rate - BB_HE_2SS_MCS0); + else if (rate >= BB_HE_1SS_MCS0) + rate_digit = (rate - BB_HE_1SS_MCS0); + else if (rate >= BB_VHT_8SS_MCS0) + rate_digit = (rate - BB_VHT_8SS_MCS0); + else if (rate >= BB_VHT_7SS_MCS0) + rate_digit = (rate - BB_VHT_7SS_MCS0); + else if (rate >= BB_VHT_6SS_MCS0) + rate_digit = (rate - BB_VHT_6SS_MCS0); + else if (rate >= BB_VHT_5SS_MCS0) + rate_digit = (rate - BB_VHT_5SS_MCS0); + else if (rate >= BB_VHT_4SS_MCS0) + rate_digit = (rate - BB_VHT_4SS_MCS0); + else if (rate >= BB_VHT_3SS_MCS0) + rate_digit = (rate - BB_VHT_3SS_MCS0); + else if (rate >= BB_VHT_2SS_MCS0) + rate_digit = (rate - BB_VHT_2SS_MCS0); + else if (rate >= BB_VHT_1SS_MCS0) + rate_digit = (rate - BB_VHT_1SS_MCS0); + else if (rate >= BB_HT_MCS0) + rate_digit = (rate - BB_HT_MCS0); + else if (rate <= BB_54M) + rate_digit = legacy_table[rate]; + + return rate_digit; +} + +/*u8 halbb_get_rx_stream_num(struct bb_info *bb, enum rf_type type) +{ + u8 rx_num = 1; + + if (type == RF_1T1R) + rx_num = 1; + else if (type == RF_2T2R || type == RF_1T2R) + rx_num = 2; + else if (type == RF_3T3R || type == RF_2T3R) + rx_num = 3; + else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R) + rx_num = 4; + else + BB_WARNING("%s\n", __func__); + + return rx_num; +}*/ + +u8 halbb_rate_type_2_num_ss(struct bb_info *bb, enum halbb_rate_type type) +{ + u8 num_ss = 1; + + switch (type) { + case BB_CCK: + case BB_OFDM: + case BB_1SS: + num_ss = 1; + break; + case BB_2SS: + num_ss = 2; + break; + case BB_3SS: + num_ss = 3; + break; + case BB_4SS: + num_ss = 4; + break; + default: + break; + } + + return num_ss; +} + +u8 halbb_rate_to_num_ss(struct bb_info *bb, u16 rate) +{ + u8 num_ss = 1; + + if (rate <= BB_54M) + num_ss = 1; + else if (rate <= BB_HT_MCS(31)) + num_ss = ((rate - BB_HT_MCS0) >> 3) + 1; + else if (rate <= BB_VHT_1SS_MCS(9)) + num_ss = 1; + else if (rate <= BB_VHT_2SS_MCS(9)) + num_ss = 2; + else if (rate <= BB_VHT_3SS_MCS(9)) + num_ss = 3; + else if (rate <= BB_VHT_4SS_MCS(9)) + num_ss = 4; + else if (rate <= BB_VHT_5SS_MCS(9)) + num_ss = 5; + else if (rate <= BB_VHT_6SS_MCS(9)) + num_ss = 6; + else if (rate <= BB_VHT_7SS_MCS(9)) + num_ss = 7; + else if (rate <= BB_VHT_8SS_MCS(9)) + num_ss = 8; + else if (rate <= BB_HE_1SS_MCS(11)) + num_ss = 1; + else if (rate <= BB_HE_2SS_MCS(11)) + num_ss = 2; + else if (rate <= BB_HE_3SS_MCS(11)) + num_ss = 3; + else if (rate <= BB_HE_4SS_MCS(11)) + num_ss = 4; + else if (rate <= BB_HE_5SS_MCS(11)) + num_ss = 5; + else if (rate <= BB_HE_6SS_MCS(11)) + num_ss = 6; + else if (rate <= BB_HE_7SS_MCS(11)) + num_ss = 7; + else if (rate <= BB_HE_8SS_MCS(11)) + num_ss = 8; + + return num_ss; +} + +void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size) +{ + struct bb_rate_info rate; + char *ss = NULL; + char *mode = NULL; + char *gi = NULL; + + halbb_rate_idx_parsor(bb, rate_idx, gi_ltf, &rate); + + if (rate.mode == BB_HE_MODE) + mode = "HE "; + else if (rate.mode == BB_VHT_MODE) + mode = "VHT "; + else if (rate.mode == BB_HT_MODE) + mode = "HT"; + else + mode = ""; + + if (rate.ss == 4) + ss = "4"; + else if (rate.ss == 3) + ss = "3"; + else if (rate.ss == 2) + ss = "2"; + else + ss = "1"; + + if (rate.mode == BB_HE_MODE) { + if (rate.gi_ltf == RTW_GILTF_LGI_4XHE32) + gi = "[4X32]"; + else if (rate.gi_ltf == RTW_GILTF_SGI_4XHE08) + gi = "[4X08]"; + else if (rate.gi_ltf == RTW_GILTF_2XHE16) + gi = "[2X16]"; + else if (rate.gi_ltf == RTW_GILTF_2XHE08) + gi = "[2X08]"; + else if (rate.gi_ltf == RTW_GILTF_1XHE16) + gi = "[1X16]"; + else + gi = "[1X08]"; + } else if (rate.mode >= BB_HT_MODE) { + if (rate.gi_ltf == RTW_GILTF_SGI_4XHE08) + gi = "[sgi]"; + else + gi = ""; + } else { + gi = ""; + } + + /* BB_SNPRINTF wait driver porting */ + _os_snprintf(buf, buf_size, "(%s%s%s%s%d%s%s)", + mode, + (rate.mode >= BB_VHT_MODE) ? ss : "", + (rate.mode >= BB_VHT_MODE) ? "-ss " : "", + (rate.rate_idx >= BB_HT_MCS0) ? "MCS" : "", + (rate.rate_idx >= BB_HT_MCS0) ? rate.idx : bb_phy_rate_table[rate.idx], + gi, + (rate.rate_idx < BB_HT_MCS0) ? "M" : ""); +} + +enum bb_qam_type halbb_get_qam_order(struct bb_info *bb, u16 rate_idx) +{ + u16 tmp_idx = rate_idx; + enum bb_qam_type qam_order = BB_QAM_BPSK; + enum bb_qam_type qam[10] = {BB_QAM_BPSK, BB_QAM_QPSK, + BB_QAM_QPSK, BB_QAM_16QAM, + BB_QAM_16QAM, BB_QAM_64QAM, + BB_QAM_64QAM, BB_QAM_64QAM, + BB_QAM_256QAM, BB_QAM_256QAM}; + + if (rate_idx <= BB_11M) + return BB_QAM_CCK; + + if ((rate_idx >= BB_VHT_MCS(1, 0)) && (rate_idx <= BB_VHT_MCS(4, 9))) { + if (rate_idx >= BB_VHT_MCS(4, 0)) + tmp_idx -= BB_VHT_MCS(4, 0); + else if (rate_idx >= BB_VHT_MCS(3, 0)) + tmp_idx -= BB_VHT_MCS(3, 0); + else if (rate_idx >= BB_VHT_MCS(2, 0)) + tmp_idx -= BB_VHT_MCS(2, 0); + else + tmp_idx -= BB_VHT_MCS(1, 0); + + qam_order = qam[tmp_idx]; + } else if ((rate_idx >= BB_HT_MCS(0)) && (rate_idx <= BB_HT_MCS(31))) { + if (rate_idx >= BB_HT_MCS(24)) + tmp_idx -= BB_HT_MCS(24); + else if (rate_idx >= BB_HT_MCS(16)) + tmp_idx -= BB_HT_MCS(16); + else if (rate_idx >= BB_HT_MCS(8)) + tmp_idx -= BB_HT_MCS(8); + else + tmp_idx -= BB_HT_MCS(0); + + qam_order = qam[tmp_idx]; + } else { + if ((rate_idx > BB_06M) && (rate_idx <= BB_54M)) { + tmp_idx -= BB_06M; + qam_order = qam[tmp_idx - 1]; + } else { /* OFDM 6M & all other undefine rate*/ + qam_order = BB_QAM_BPSK; + } + } + return qam_order; +} + +u8 halbb_rate_order_compute(struct bb_info *bb, u16 rate_idx) +{ + u16 rate_order = rate_idx & 0x7f; + + rate_idx &= 0x7f; + + if (rate_idx >= BB_VHT_MCS(4, 0)) + rate_order -= BB_VHT_MCS(4, 0); + else if (rate_idx >= BB_VHT_MCS(3, 0)) + rate_order -= BB_VHT_MCS(3, 0); + else if (rate_idx >= BB_VHT_MCS(2, 0)) + rate_order -= BB_VHT_MCS(2, 0); + else if (rate_idx >= BB_VHT_MCS(1, 0)) + rate_order -= BB_VHT_MCS(1, 0); + else if (rate_idx >= BB_HT_MCS(24)) + rate_order -= BB_HT_MCS(24); + else if (rate_idx >= BB_HT_MCS(16)) + rate_order -= BB_HT_MCS(16); + else if (rate_idx >= BB_HT_MCS(8)) + rate_order -= BB_HT_MCS(8); + else if (rate_idx >= BB_HT_MCS(0)) + rate_order -= BB_HT_MCS(0); + else if (rate_idx >= BB_06M) + rate_order -= BB_06M; + else + rate_order -= BB_01M; + + if (rate_idx >= BB_HT_MCS(0)) + rate_order++; + + return (u8)rate_order; +} + +u8 halbb_init_ra_by_rssi(struct bb_info *bb, u8 rssi_assoc) +{ + u8 init_ra_lv = 0; + BB_DBG(bb, DBG_RA, "====>%s\n", __func__); + if (rssi_assoc > 50) + init_ra_lv = 1; + else if (rssi_assoc > 30) + init_ra_lv = 2; + else if (rssi_assoc > 1) + init_ra_lv = 3; + else + init_ra_lv = 0; + return init_ra_lv; +} + +bool halbb_set_csi_rate(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + u8 macid; + struct bb_h2c_ra_cfg_info *ra_cfg; + struct rtw_hal_stainfo_t *hal_sta_i; + struct rtw_ra_sta_info * ra_sta_i; + + if (!phl_sta_i || !bb) + return false; + macid = (u8)(phl_sta_i->macid); + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) + return false; + ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + ra_sta_i = &(hal_sta_i->ra_info); + if (!ra_sta_i) + return false; + /*if ((!ra_sta_i->ra_csi_rate_en) && (!ra_sta_i->fixed_csi_rate_en)) + return false;*/ + /* Set csi rate ctrl enable */ + ra_cfg->ramask[7] |= BIT(7); + ra_cfg->ra_csi_rate_en = ra_sta_i->ra_csi_rate_en; + ra_cfg->fixed_csi_rate_en = ra_sta_i->fixed_csi_rate_en; + ra_cfg->cr_tbl_sel = bb->hal_com->csi_para_ctrl_sel; + ra_cfg->band_num = ra_sta_i->band_num; + ra_cfg->fixed_csi_rate_l = ra_sta_i->csi_rate.mcs_ss_idx; + ra_cfg->fixed_csi_rate_m = ra_sta_i->csi_rate.mode | + ra_sta_i->csi_rate.gi_ltf << 2 | + ra_sta_i->csi_rate.bw << 5; + return true; +} + +u8 halbb_rssi_lv_dec(struct bb_info *bb, u8 rssi, u8 ratr_state) +{ + /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + /*u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};*/ + u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; + /*@ RSSI definition changed in AX*/ + u8 new_rssi_lv = 0; + u8 i; + + BB_DBG(bb, DBG_RA, + "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n", + ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], + rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]); + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (i >= (ratr_state)) + rssi_lv_t[i] += RA_FLOOR_UP_GAP; + } + BB_DBG(bb, DBG_RA, + "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi, + rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3], + rssi_lv_t[4], rssi_lv_t[5]); + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (rssi < rssi_lv_t[i]) { + new_rssi_lv = i; + break; + } + } + return new_rssi_lv; +} + +u64 halbb_ramask_by_rssi(struct bb_info *bb, u8 rssi_lv, u64 ramask) +{ + u64 ra_mask_bitmap = ramask; + + if (rssi_lv == 0) + ra_mask_bitmap &= 0xffffffffffffffff; + else if (rssi_lv == 1) + ra_mask_bitmap &= 0xfffffffffffffff0; + else if (rssi_lv == 2) + ra_mask_bitmap &= 0xffffffffffffefe0; + else if (rssi_lv == 3) + ra_mask_bitmap &= 0xffffffffffffcfc0; + else if (rssi_lv == 4) + ra_mask_bitmap &= 0xffffffffffff8f80; + else if (rssi_lv >= 5) + ra_mask_bitmap &= 0xffffffffffff0f00; + + /*Avoid empty HT/VHT/HE ramask when HT/VHT/HE mode is enabled*/ + if ((ra_mask_bitmap >> 12) == 0x0) { + ra_mask_bitmap |= (ramask & 0xfffffffffffff000); + BB_DBG(bb, DBG_RA, + "Empty HT/VHT/HE ramask! Bypass HT/VHT/HE ramask_by_rssi\n"); + } + + /*Avoid empty legacy ramask after foolproof of HT/VHT/HE mode*/ + if (ra_mask_bitmap == 0x0) { + ra_mask_bitmap |= (ramask & 0xfff); + BB_DBG(bb, DBG_RA, + "Empty ramask! Bypass a/b/g ramask_by_rssi\n"); + } + + return ra_mask_bitmap; +} + +u64 halbb_ramask_mod(struct bb_info *bb, u8 macid, u64 ramask, u8 rssi, u8 mode, + u8 nss) +{ + struct bb_ra_info *bb_ra = &bb->bb_ra_i[macid]; + u64 mod_mask = ramask; + u64 mod_mask_rssi = ramask; + u8 new_rssi_lv = 0; + u8 wifi_mode = RA_non_ht; + + if (mode == CCK_SUPPORT) { /* B mode */ + mod_mask &= RAMASK_B; + wifi_mode = RA_CCK; + BB_DBG(bb, DBG_RA, "RA mask B mode\n"); + } else if (mode == OFDM_SUPPORT) { /* AG mode */ + mod_mask &= RAMASK_AG; + wifi_mode = RA_non_ht; + BB_DBG(bb, DBG_RA, "RA mask A mode\n"); + } else if (mode == (CCK_SUPPORT|OFDM_SUPPORT)) { + /* BG mode */ + mod_mask &= RAMASK_BG; + wifi_mode = RA_non_ht; + BB_DBG(bb, DBG_RA, "RA mask 2.4G BG mode\n"); + } else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|HT_SUPPORT)) { + /* 2G N mode */ + mod_mask &= RAMASK_HT_2G; + wifi_mode = RA_HT; + BB_DBG(bb, DBG_RA, "RA mask 2.4G HT mode\n"); + } else if (mode == (OFDM_SUPPORT|HT_SUPPORT)) { + /* 5G N mode */ + mod_mask &= RAMASK_HT_5G; + wifi_mode = RA_HT; + BB_DBG(bb, DBG_RA, "RA mask 5G HT mode\n"); + } else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|VHT_SUPPORT_TX)) { + /* 2G AC mode */ + mod_mask &= RAMASK_VHT_2G; + wifi_mode = RA_VHT; + BB_DBG(bb, DBG_RA, "RA mask 2.4G VHT mode\n"); + } else if (mode == (OFDM_SUPPORT|VHT_SUPPORT_TX)) { + /* 5G AC mode */ + mod_mask &= RAMASK_VHT_5G; + wifi_mode = RA_VHT; + BB_DBG(bb, DBG_RA, "RA mask 5G VHT mode\n"); + } else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|HE_SUPPORT)) { + /* 2G AX mode */ + mod_mask &= RAMASK_HE_2G; + wifi_mode = RA_HE; + BB_DBG(bb, DBG_RA, "RA mask 2.4G HE mode\n"); + } else if (mode == (OFDM_SUPPORT|HE_SUPPORT)) { + /* 5G AX mode */ + mod_mask &= RAMASK_HE_5G; + wifi_mode = RA_HE; + BB_DBG(bb, DBG_RA, "RA mask 5G HE mode\n"); + } else { + BB_WARNING("MD id %x, RA mask not found\n", mode); + } + BB_DBG(bb, DBG_RA, "RA mask SS NUM : %d\n", nss); + if (wifi_mode == RA_HT) { + switch (nss) { + case RA_1SS_MODE: + mod_mask &= RAMASK_1SS_HT; + break; + case RA_2SS_MODE: + mod_mask &= RAMASK_2SS_HT; + break; + case RA_3SS_MODE: + mod_mask &= RAMASK_3SS_HT; + break; + case RA_4SS_MODE: + mod_mask &= RAMASK_4SS_HT; + break; + default: + mod_mask &= RAMASK_1SS_HT; + break; + } + } else if (wifi_mode == RA_VHT) { + switch (nss) { + case RA_1SS_MODE: + mod_mask &= RAMASK_1SS_VHT; + break; + case RA_2SS_MODE: + mod_mask &= RAMASK_2SS_VHT; + break; + case RA_3SS_MODE: + mod_mask &= RAMASK_3SS_VHT; + break; + case RA_4SS_MODE: + mod_mask &= RAMASK_4SS_VHT; + break; + default: + mod_mask &= RAMASK_1SS_VHT; + break; + } + } else if (wifi_mode == RA_HE) { + switch (nss) { + case RA_1SS_MODE: + mod_mask &= RAMASK_1SS_HE; + break; + case RA_2SS_MODE: + mod_mask &= RAMASK_2SS_HE; + break; + case RA_3SS_MODE: + mod_mask &= RAMASK_3SS_HE; + break; + case RA_4SS_MODE: + mod_mask &= RAMASK_4SS_HE; + break; + default: + mod_mask &= RAMASK_1SS_HE; + break; + } + } else { + BB_DBG(bb, DBG_RA, "RA mask non-ht mode\n"); + } + BB_DBG(bb, DBG_RA, "RA mask modify : %llx\n", mod_mask); + new_rssi_lv = halbb_rssi_lv_dec(bb, rssi, bb_ra->rssi_lv); + if (wifi_mode != RA_CCK) { + mod_mask_rssi = halbb_ramask_by_rssi(bb, new_rssi_lv, mod_mask); + //BB_DBG(bb, DBG_RA, "RA mask modify by rssi : 0x%016llx\n", mod_mask_rssi); + } else { + mod_mask_rssi = mod_mask; + } + return mod_mask_rssi; +} + +void rtw_halbb_mudbg(struct bb_info *bb, u8 type, u8 mu_entry, u8 macid, + bool en_256q, bool en_1024q) +{ + struct bb_h2c_mu_cfg mucfg = {0}; + u32 *bb_h2c = (u32 *)&mucfg; + u8 cmdlen = sizeof(mucfg); + + mucfg.cmd_type = type; + mucfg.entry = mu_entry; + mucfg.macid = macid; + halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MUCFG, HALBB_H2C_RA, bb_h2c); +} + +u64 halbb_gen_abg_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + u64 tmp_mask = 0; + u64 abg_mask = 0; + u8 i; + struct protocol_cap_t *asoc_cap_i; + + if (!phl_sta_i) + return 0; + + asoc_cap_i = &phl_sta_i->asoc_cap; + + BB_DBG(bb, DBG_RA, + "supported rates(L->H) = [%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x]\n", + asoc_cap_i->supported_rates[0], asoc_cap_i->supported_rates[1], + asoc_cap_i->supported_rates[2], asoc_cap_i->supported_rates[3], + asoc_cap_i->supported_rates[4], asoc_cap_i->supported_rates[5], + asoc_cap_i->supported_rates[6], asoc_cap_i->supported_rates[7], + asoc_cap_i->supported_rates[8], asoc_cap_i->supported_rates[9], + asoc_cap_i->supported_rates[10], asoc_cap_i->supported_rates[11]); + for (i = 0; i < MAX_ABG_RATE_NUM; i++) { + if (asoc_cap_i->supported_rates[i] == 0x0) + continue; + + tmp_mask = (u64)halbb_mgnt_2_hw_rate(asoc_cap_i->supported_rates[i]); + abg_mask |= (u64)BIT(tmp_mask); + } + BB_DBG(bb, DBG_RA, "gen_abgmask: 0x%llx\n", abg_mask); + + return abg_mask; +} + +u64 halbb_gen_vht_mask(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + u8 vht_cap[2] = {0}; + u8 tmp_cap = 0; + u8 cap_ss; + u64 tmp_mask_nss = 0; + u8 i; + struct protocol_cap_t *asoc_cap_i; + + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + if (!phl_sta_i) + return 0; + asoc_cap_i = &phl_sta_i->asoc_cap; + vht_cap[0] = asoc_cap_i->vht_rx_mcs[0]; + vht_cap[1] = asoc_cap_i->vht_rx_mcs[1]; + BB_DBG(bb, DBG_RA, "%s : vhtcap:%x %x\n", __func__, vht_cap[0], vht_cap[1]); + for (i = 0; i < MAX_NSS_VHT; i++) { + if (i == 0) + tmp_cap = vht_cap[0]; + else if (i == 4) + tmp_cap = vht_cap[1]; + + cap_ss = tmp_cap & 0x03; + tmp_cap = tmp_cap >> 2; + if (cap_ss == 0) + tmp_mask_nss |= ((u64)0xff << (i * 12)); + else if (cap_ss == 1) + tmp_mask_nss |= ((u64)0x1ff << (i * 12)); + else if (cap_ss == 2) + tmp_mask_nss |= ((u64)0x3ff << (i * 12)); + + BB_DBG(bb, DBG_RA, "gen_vhtmask:cap%x, ss%x, hemask: 0x%llx\n", + cap_ss, i, tmp_mask_nss); + } + return tmp_mask_nss; +} + +u64 halbb_gen_ht_mask(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + u8 ht_cap[4] = {0}; + u64 cap_ss; + u64 tmp_mask_nss = 0; + u8 i; + struct protocol_cap_t *asoc_cap_i; + + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + if (!phl_sta_i) + return 0; + asoc_cap_i = &phl_sta_i->asoc_cap; + for (i = 0; i < MAX_NSS_HT; i++)/* can use pointer after merge code*/ + ht_cap[i] = asoc_cap_i->ht_rx_mcs[i]; + BB_DBG(bb, DBG_RA, "%s : htcap: %x %x\n", __func__, ht_cap[0], ht_cap[1]); + for (i = 0; i < MAX_NSS_HT; i++) { + cap_ss = (u64)ht_cap[i]; + tmp_mask_nss = tmp_mask_nss | (cap_ss << (i * 12)); + BB_DBG(bb, DBG_RA, "gen_htmask:cap%llx, ss%x, htmask: 0x%llx\n", cap_ss, i, tmp_mask_nss); + } + + return tmp_mask_nss; +} + +u64 halbb_gen_he_mask(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i, enum channel_width bw) +{ + u8 he_cap[2] = {0}; + u8 tmp_cap = 0; + u8 cap_ss; + u64 tmp_mask_nss = 0; + u8 i; + struct protocol_cap_t *asoc_cap_i; + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + /*@In HE cap, mcs is correspond to channel bw"*/ + + if (!phl_sta_i) + return 0; + asoc_cap_i = &phl_sta_i->asoc_cap; + if (bw == CHANNEL_WIDTH_80_80) { + he_cap[0] = asoc_cap_i->he_rx_mcs[4]; + he_cap[1] = asoc_cap_i->he_rx_mcs[5]; + } else if (bw == CHANNEL_WIDTH_160) { + he_cap[0] = asoc_cap_i->he_rx_mcs[2]; + he_cap[1] = asoc_cap_i->he_rx_mcs[3]; + } else { + he_cap[0] = asoc_cap_i->he_rx_mcs[0]; + he_cap[1] = asoc_cap_i->he_rx_mcs[1]; + } + BB_DBG(bb, DBG_RA, "%s: hecap:%x %x\n", __func__, he_cap[0], he_cap[1]); + for (i = 0; i < MAX_NSS_HE; i++) { + if (i == 0) + tmp_cap = he_cap[0]; + else if (i == 4) + tmp_cap = he_cap[1]; + cap_ss = tmp_cap & 0x03; + tmp_cap = tmp_cap >> 2; + if (cap_ss == 0) + tmp_mask_nss |= ((u64)0xff << (i * 12)); + else if (cap_ss == 1) + tmp_mask_nss |= ((u64)0x3ff << (i * 12)); + else if (cap_ss == 2) + tmp_mask_nss |= ((u64)0xfff << (i * 12)); + + BB_DBG(bb, DBG_RA, "gen_hemask:cap%x, ss%x, hemask: 0x%llx\n", + cap_ss, i, tmp_mask_nss); + } + return tmp_mask_nss; +} + +bool halbb_chk_bw_under_20(struct bb_info *bb, u8 bw) +{ + bool ret_val = true; + + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + ret_val = true; + break; + case CHANNEL_WIDTH_40: + case CHANNEL_WIDTH_80: + case CHANNEL_WIDTH_80_80: + case CHANNEL_WIDTH_160: + ret_val = false; + break; + default: + ret_val = false; + break; + } + return ret_val; +} + +bool halbb_chk_bw_under_40(struct bb_info *bb, u8 bw) +{ + bool ret_val = true; + + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + case CHANNEL_WIDTH_40: + ret_val = true; + break; + case CHANNEL_WIDTH_80: + case CHANNEL_WIDTH_80_80: + case CHANNEL_WIDTH_160: + ret_val = false; + break; + default: + ret_val = false; + break; + } + return ret_val; +} + +bool halbb_hw_bw_mode_chk(struct bb_info *bb, u8 bw, u8 hw_mode) +{ + bool ret_val = true; + + switch (hw_mode) { + case CCK_SUPPORT: + case OFDM_SUPPORT: + case (CCK_SUPPORT | OFDM_SUPPORT): + ret_val = halbb_chk_bw_under_20(bb, bw); + break; + case HT_SUPPORT: + case (HT_SUPPORT | CCK_SUPPORT): + case (HT_SUPPORT | OFDM_SUPPORT): + case (HT_SUPPORT | OFDM_SUPPORT | CCK_SUPPORT): + ret_val = halbb_chk_bw_under_40(bb, bw); + break; + case VHT_SUPPORT_TX: + case (VHT_SUPPORT_TX | CCK_SUPPORT): + case (VHT_SUPPORT_TX | OFDM_SUPPORT): + case (VHT_SUPPORT_TX | OFDM_SUPPORT | CCK_SUPPORT): + case HE_SUPPORT: + case (HE_SUPPORT | CCK_SUPPORT): + case (HE_SUPPORT | OFDM_SUPPORT): + case (HE_SUPPORT | OFDM_SUPPORT | CCK_SUPPORT): + ret_val = true; + break; + default: + ret_val = true; + break; + } + if (!ret_val) + BB_WARNING("WRONG BW setting !!!!\n"); + return ret_val; +} + +u8 halbb_hw_bw_mapping(struct bb_info *bb, u8 bw, u8 hw_mode) +{ + u8 hw_bw_map = CHANNEL_WIDTH_20; + bool ret_val; + + if (bw <= CHANNEL_WIDTH_80) + hw_bw_map = bw; + else if (bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) + hw_bw_map = CHANNEL_WIDTH_160; + else + hw_bw_map = CHANNEL_WIDTH_20; + ret_val = halbb_hw_bw_mode_chk(bb, bw, hw_mode); + return hw_bw_map; +} + +u8 halbb_hw_mode_mapping(struct bb_info *bb, u8 wifi_mode) +{ + u8 hw_mode_map = 0; + /* Driver wifi mode mapping */ + + if (wifi_mode & WLAN_MD_11B) /*11B*/ + hw_mode_map |= CCK_SUPPORT; + if ((wifi_mode & WLAN_MD_11A) || (wifi_mode & WLAN_MD_11G)) /*11G, 11A*/ + hw_mode_map |= OFDM_SUPPORT; + + /* To prevent unnecessary mode from driver, causing confusing ra mask selection after then*/ + if (wifi_mode & WLAN_MD_11AX) /*11AX*/ + hw_mode_map |= HE_SUPPORT; + else if (wifi_mode & WLAN_MD_11AC) /*11AC*/ + hw_mode_map |= VHT_SUPPORT_TX; + else if (wifi_mode & WLAN_MD_11N) /* 11_N*/ + hw_mode_map |= HT_SUPPORT; + + if (hw_mode_map == 0) + BB_WARNING("WRONG Wireless mode !!!!\n"); + return hw_mode_map; +} + +bool halbb_ac_n_sgi_chk(struct bb_info *bb, u8 hw_mode, bool en_sgi) +{ + bool sgi_chk = en_sgi; + + /* Driver wifi mode mapping */ + if (hw_mode & HE_SUPPORT) { + sgi_chk = false; + BB_DBG(bb, DBG_RA, "HE mode sgi is not used!\n"); + } + return sgi_chk; +} + +u8 halbb_ax_giltf_chk(struct bb_info *bb, u8 hw_mode, u8 giltf_cap) +{ + u8 giltf_chk = giltf_cap; + + /* Driver wifi mode mapping */ + if (!(hw_mode & HE_SUPPORT)) { + giltf_chk = 0; + BB_DBG(bb, DBG_RA, "In non-HE mode gi_ltf is not used!\n"); + } + return giltf_chk; +} + +bool halbb_ldpc_chk(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_mode) +{ + struct protocol_cap_t *asoc_cap_i; + bool ldpc_en = false; + + /* Driver wifi mode mapping */ + if (!phl_sta_i) + return false; + asoc_cap_i = &phl_sta_i->asoc_cap; + if (hw_mode & HE_SUPPORT) { + ldpc_en |= asoc_cap_i->he_ldpc; + BB_DBG(bb, DBG_RA, "Enable HE LDPC\n"); + } else if (hw_mode&VHT_SUPPORT_TX) { + ldpc_en |= asoc_cap_i->vht_ldpc; + BB_DBG(bb, DBG_RA, "Enable VHT LDPC\n"); + } else if (hw_mode&HT_SUPPORT) { + ldpc_en |= asoc_cap_i->ht_ldpc; + BB_DBG(bb, DBG_RA, "Enable HT LDPC\n"); + } + return ldpc_en; +} + +u8 halbb_nss_mapping(struct bb_info *bb, u8 nss) +{ + u8 mapping_nss = 0; + + if (nss != 0) + mapping_nss = nss - 1; + /* Driver tx_nss mapping */ + if (mapping_nss > (bb->hal_com->rfpath_tx_num - 1)) + mapping_nss = bb->hal_com->rfpath_tx_num - 1; + return mapping_nss; +} + +bool halbb_stbc_mapping(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_mode) +{ + struct protocol_cap_t *asoc_cap_i; + bool stbc_en = false; + + /* Driver wifi mode mapping */ + if (!phl_sta_i) + return false; + asoc_cap_i = &phl_sta_i->asoc_cap; + if (hw_mode & HE_SUPPORT) { + if (asoc_cap_i->stbc_he_rx != 0) + stbc_en = true; + BB_DBG(bb, DBG_RA, "HE STBC %d\n", stbc_en); + } else if (hw_mode & VHT_SUPPORT_TX) { + if (asoc_cap_i->stbc_vht_rx != 0) + stbc_en = true; + BB_DBG(bb, DBG_RA, "VHT STBC %d\n", stbc_en); + } else if (hw_mode & HT_SUPPORT) { + if (asoc_cap_i->stbc_ht_rx != 0) + stbc_en = true; + BB_DBG(bb, DBG_RA, "HT STBC %d\n", stbc_en); + } + return stbc_en; +} + +bool halbb_sgi_chk(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_bw) +{ + struct protocol_cap_t *asoc_cap_i; + bool sgi_en = false; + + /* Driver wifi mode mapping */ + if (!phl_sta_i) + return false; + asoc_cap_i = &phl_sta_i->asoc_cap; + if (hw_bw == CHANNEL_WIDTH_20) { + sgi_en = asoc_cap_i->sgi_20; + BB_DBG(bb, DBG_RA, "Enable 20M SGI\n"); + } else if (hw_bw == CHANNEL_WIDTH_40) { + sgi_en = asoc_cap_i->sgi_40; + BB_DBG(bb, DBG_RA, "Enable 40M SGI\n"); + } else if (hw_bw == CHANNEL_WIDTH_80) { + sgi_en = asoc_cap_i->sgi_80; + BB_DBG(bb, DBG_RA, "Enable 80M SGI\n"); + } else if (hw_bw == CHANNEL_WIDTH_160) { + sgi_en = asoc_cap_i->sgi_160; + BB_DBG(bb, DBG_RA, "Enable 160M SGI\n"); + } + return sgi_en; +} + +void halbb_ramask_trans(struct bb_info *bb, u8 macid, u64 mask) +{ + struct bb_h2c_ra_cfg_info *ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + + ra_cfg->ramask[0] = (u8)(mask & 0x00000000000000ff); + ra_cfg->ramask[1] = (u8)((mask & 0x000000000000ff00)>>8); + ra_cfg->ramask[2] = (u8)((mask & 0x0000000000ff0000)>>16); + ra_cfg->ramask[3] = (u8)((mask & 0x00000000ff000000)>>24); + ra_cfg->ramask[4] = (u8)((mask & 0x000000ff00000000)>>32); + ra_cfg->ramask[5] = (u8)((mask & 0x0000ff0000000000)>>40); + ra_cfg->ramask[6] = (u8)((mask & 0x00ff000000000000)>>48); + ra_cfg->ramask[7] = (u8)((mask & 0xff00000000000000)>>56); +} + +u8 halbb_get_opt_giltf(struct bb_info *bb, u8 assoc_giltf) +{ + u8 i =0; + u8 opt_gi_ltf = 0; + + if (assoc_giltf & BIT(1)) /* cap. for 4x0.8*/ + opt_gi_ltf |= BIT(BB_OPT_GILTF_4XHE08); + else if (assoc_giltf & BIT(5)) /* cap. for 1x0.8*/ + opt_gi_ltf |= BIT(BB_OPT_GILTF_1XHE08); + + BB_DBG(bb, DBG_RA, "Ass GILTF=%x,opt GILTF=%x\n", assoc_giltf, opt_gi_ltf); + return opt_gi_ltf; +} + +u8 halbb_giltf_trans(struct bb_info *bb, u8 assoc_giltf, u8 cal_giltf) +{ + u8 i =0; + + BB_DBG(bb, DBG_RA, "Ass GILTF=%x,Cal GILTF=%x\n", assoc_giltf, cal_giltf); + if (cal_giltf == RTW_GILTF_LGI_4XHE32 && (assoc_giltf & BIT(0))) + return cal_giltf; + else if (cal_giltf == RTW_GILTF_SGI_4XHE08 && (assoc_giltf & BIT(1))) + return cal_giltf; + else if (cal_giltf == RTW_GILTF_2XHE16 && (assoc_giltf & BIT(2))) + return cal_giltf; + else if (cal_giltf == RTW_GILTF_2XHE08 && (assoc_giltf & BIT(3))) + return cal_giltf; + else if (cal_giltf == RTW_GILTF_1XHE16 && (assoc_giltf & BIT(4))) + return cal_giltf; + else if (cal_giltf == RTW_GILTF_1XHE08 && (assoc_giltf & BIT(5))) + return cal_giltf; + if (assoc_giltf & BIT(3)) + return RTW_GILTF_2XHE08; + else if (assoc_giltf & BIT(2)) + return RTW_GILTF_2XHE16; + else if (assoc_giltf & BIT(1)) + return RTW_GILTF_SGI_4XHE08; + else if (assoc_giltf & BIT(5)) + return RTW_GILTF_1XHE08; + else if (assoc_giltf & BIT(4)) + return RTW_GILTF_1XHE16; + else + return RTW_GILTF_LGI_4XHE32; +} + +bool rtw_halbb_dft_mask(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + u8 mode = 0; /* connect to phl->assoc*/ + u8 hw_md; + u64 init_mask = 0; + u64 get_mask = 0; + u32 mask0, mask1; + enum channel_width bw; + struct rtw_hal_stainfo_t *hal_sta_i; + struct protocol_cap_t *asoc_cap_i; + + if (!phl_sta_i || !bb) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return false; + } + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return false; + } + asoc_cap_i = &phl_sta_i->asoc_cap; + mode = phl_sta_i->wmode; + bw = phl_sta_i->chandef.bw; + hw_md = halbb_hw_mode_mapping(bb, mode); + BB_DBG(bb, DBG_RA, "Gen Dftmask: mode = %x, hw_md = %x\n", mode, hw_md); + + if (hw_md & (CCK_SUPPORT | OFDM_SUPPORT)) + init_mask = halbb_gen_abg_mask(bb, phl_sta_i); + + if (init_mask == 0) { + if (hw_md & CCK_SUPPORT) { + init_mask |= 0x0000000f; + BB_DBG(bb, DBG_RA, + "[%s]abg mask is null!, set b mask=0xf\n", __func__); + } + + if (hw_md & OFDM_SUPPORT) { + init_mask |= 0x00000ff0; + BB_DBG(bb, DBG_RA, + "[%s]abg mask is null!, set ag mask=0xff\n", __func__); + } + } + + if (hw_md & HE_SUPPORT) + get_mask = halbb_gen_he_mask(bb, phl_sta_i, bw); + else if (hw_md & VHT_SUPPORT_TX) + get_mask = halbb_gen_vht_mask(bb, phl_sta_i); + else if (hw_md & HT_SUPPORT) + get_mask = halbb_gen_ht_mask(bb, phl_sta_i); + else + get_mask = 0; + init_mask |= (get_mask << 12); + mask0 = (u32)(init_mask & 0xffffffff); + mask1 = (u32)((init_mask >> 32) & 0xffffffff); + if (init_mask != 0) { + hal_sta_i->ra_info.cur_ra_mask = init_mask; + BB_DBG(bb, DBG_RA, "Default mask = %x %x\n", mask0, mask1); + return true; + } else { + BB_WARNING("Error default mask, it should not zero\n"); + return false; + } +} + +u8 rtw_halbb_arfr_trans(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + struct rtw_hal_stainfo_t *hal_sta_i; + u8 mode; + u8 arfr_ret = 0x0; + + if (!phl_sta_i) + return false; + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) + return false; + mode = phl_sta_i->wmode; + if (mode & WLAN_MD_11B) /*11B*/ + arfr_ret |= CCK_SUPPORT; + if ((mode & WLAN_MD_11A)||(mode & WLAN_MD_11G)) /*11G, 11A*/ + arfr_ret |= OFDM_SUPPORT; + if (mode & WLAN_MD_11N) /* 11_N*/ + arfr_ret |= HT_SUPPORT; + if (mode & WLAN_MD_11AC) /*11AC*/ + arfr_ret |= VHT_SUPPORT_TX; + return arfr_ret; + /*if (mode|WLAN_MD_11AX ) // 11AX usually can use arfr + hw_mode_map |= HE_SUPPORT;*/ +} + +bool rtw_halbb_raregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + /*struct rtw_phl_stainfo_t *phl_sta_i = bb->phl_sta_info[macid];*/ + u8 macid; + struct bb_h2c_ra_cfg_info *ra_cfg; + struct rtw_hal_stainfo_t *hal_sta_i; + bool tx_ldpc; + bool tx_stbc; + bool ret_val = false; + u8 tx_nss; + u8 rssi; + struct protocol_cap_t *asoc_cap_i; + u8 rssi_assoc ; + u8 mode; + bool en_sgi = false; + u8 giltf_cap = 0; + u8 init_lv; + /* Need to mapping with driver wifi mode*/ + u32 *bb_h2c; + u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info); + u64 mod_mask; + + BB_DBG(bb, DBG_RA, "====>%s\n", __func__); + if (!phl_sta_i || !bb) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return ret_val; + } + macid = (u8)(phl_sta_i->macid); + ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + bb_h2c = (u32 *) ra_cfg; + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return ret_val; + } + asoc_cap_i = &phl_sta_i->asoc_cap; + /*@ use assoc rssi to init ra, only use in ra register, it is an integer using U(8,0)*/ + rssi_assoc = (u8)(hal_sta_i->rssi_stat.assoc_rssi); + BB_DBG(bb, DBG_RA, "Assoc rssi = %d\n", rssi_assoc); + rssi = (u8)(hal_sta_i->rssi_stat.rssi) >> 1; + mode = phl_sta_i->wmode; + init_lv = halbb_init_ra_by_rssi(bb, rssi_assoc); + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx); + if (asoc_cap_i->dcm_max_const_rx) + ra_cfg->dcm_cap = 1; + else + ra_cfg->dcm_cap = 0; + mode = halbb_hw_mode_mapping(bb, mode); + + /* ONLY need to get the optional gi-ltf combination for H2C FW*/ + /* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/ + giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi); + ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap); + + /* giltf assigned by phl/halbb or trained by FW*/ + if (hal_sta_i->ra_info.fix_giltf_en == false) { /*giltf from halbb*/ + if (bb->ic_type & (BB_RTL8852A | BB_RTL8852B | BB_RTL8852C)) { /*Disable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = true; + ra_cfg->fix_giltf = RTW_GILTF_2XHE08; + /* gi_ltf is decided by delay spread. This is not ready. + if (is_giltf_decided_by_delay_sp) + ra_cfg->fix_giltf = halbb_ra_giltf_ctrl(bb, macid, delay_sp, asoc_cap_i->ltf_gi); + */ + } else { /*Enable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = false; + } + } else { /*giltf from phl*/ + ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf); + } + BB_DBG(bb, DBG_RA, "fix_giltf_en(phl)=%d, fix_giltf_en(Final)=%d, fix_giltf=%d\n", + hal_sta_i->ra_info.fix_giltf_en, ra_cfg->fix_giltf_en, ra_cfg->fix_giltf); + + ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra; + mod_mask = hal_sta_i->ra_info.cur_ra_mask; + ra_cfg->er_cap = asoc_cap_i->er_su; + tx_stbc = halbb_stbc_mapping(bb, phl_sta_i, mode); + ra_cfg->upd_all= true; + ra_cfg->upd_bw_nss_mask= false; + ra_cfg->upd_mask= false; + if (mode == 0) + return ret_val; + tx_ldpc = halbb_ldpc_chk(bb, phl_sta_i, mode); + ra_cfg->mode_ctrl = mode; + ra_cfg->bw_cap = halbb_hw_bw_mapping(bb, phl_sta_i->chandef.bw, mode); + en_sgi = halbb_sgi_chk(bb, phl_sta_i, ra_cfg->bw_cap); + ra_cfg->macid = macid; + ra_cfg->init_rate_lv = init_lv; + ra_cfg->en_sgi = halbb_ac_n_sgi_chk(bb, mode, en_sgi); + ra_cfg->ldpc_cap = tx_ldpc; + ra_cfg->stbc_cap = tx_stbc; + ra_cfg->ss_num = tx_nss; + /*@ modify ra mask by assoc rssi*/ + mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi_assoc, mode, tx_nss); + halbb_ramask_trans(bb, macid, mod_mask); + ret_val = halbb_set_csi_rate(bb, phl_sta_i); + if (!ret_val) + return ret_val; + BB_DBG(bb, DBG_RA, "RA Register=>In: Dis_ra=%x, MD=%x, BW=%x, macid=%x\n", + hal_sta_i->ra_info.dis_ra, mode, phl_sta_i->chandef.bw, macid); + BB_DBG(bb, DBG_RA, "RA Register=>In: DCM =%x, ER=%x, in_rt=%x, upd_a=%x, sgi=%x, ldpc=%x, stbc=%x\n", + ra_cfg->dcm_cap, ra_cfg->er_cap, init_lv, ra_cfg->upd_all, + en_sgi, tx_ldpc, tx_stbc); + BB_DBG(bb, DBG_RA, "RA Register=>In: SS=%x, GILTF_cap=%x, upd_bnm=%x, upd_m=%x, mask=%llx\n", + tx_nss, giltf_cap, ra_cfg->upd_bw_nss_mask, ra_cfg->upd_mask, mod_mask); + BB_DBG(bb, DBG_RA, "RA Register=>Out racfg: dis%x bw%x md%x mid%x\n", ra_cfg->is_dis_ra, + ra_cfg->bw_cap, ra_cfg->mode_ctrl, ra_cfg->macid); + BB_DBG(bb, DBG_RA, "RA Register=>Out h2cp: %x %x %x %x\n", bb_h2c[0], bb_h2c[1], + bb_h2c[2], bb_h2c[3]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c); + return ret_val; +} + +bool rtw_halbb_ra_deregistered(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + return true; +} + +bool rtw_halbb_raupdate(struct bb_info *bb, + struct rtw_phl_stainfo_t *phl_sta_i) +{ + /* Update only change bw, nss, ramask */ + u8 macid; + struct bb_h2c_ra_cfg_info *ra_cfg; + struct rtw_hal_stainfo_t *hal_sta_i; + struct protocol_cap_t *asoc_cap_i; + u8 tx_nss; + u8 rssi; + u8 init_lv = 0; + u8 mode = 0; + u8 giltf_cap = 0; + bool ret_val = false; + /* Need to mapping with driver wifi mode*/ + u32 *bb_h2c; + u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info); + u64 mod_mask; + + BB_DBG(bb, DBG_RA, "====>%s\n", __func__); + if (!phl_sta_i || !bb) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return ret_val; + } + macid = (u8) (phl_sta_i->macid); + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + return ret_val; + } + ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + mode = ra_cfg->mode_ctrl; + bb_h2c = (u32 *) ra_cfg; + asoc_cap_i = &phl_sta_i->asoc_cap; + rssi = hal_sta_i->rssi_stat.rssi >> 1; + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx); + ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra; + mod_mask = hal_sta_i->ra_info.cur_ra_mask; + ra_cfg->upd_all= false; + ra_cfg->upd_bw_nss_mask= true; + ra_cfg->upd_mask= false; + mode = ra_cfg->mode_ctrl; + if (mode == 0) + return ret_val; + ra_cfg->mode_ctrl = mode; + + /* ONLY need to get the optional gi-ltf combination for H2C FW*/ + /* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/ + giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi); + ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap); + + /* giltf assigned by phl/halbb or trained by FW*/ + if (hal_sta_i->ra_info.fix_giltf_en == false) { /*giltf from halbb*/ + if (bb->ic_type & (BB_RTL8852A | BB_RTL8852B | BB_RTL8852C)) { /*Disable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = true; + ra_cfg->fix_giltf = RTW_GILTF_2XHE08; + /* gi_ltf is decided by delay spread. This is not ready. + if (is_giltf_decided_by_delay_sp) + ra_cfg->fix_giltf = halbb_ra_giltf_ctrl(bb, macid, delay_sp, asoc_cap_i->ltf_gi); + */ + } else { /*Enable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = false; + } + } else { /*giltf from phl*/ + ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf); + } + BB_DBG(bb, DBG_RA, "fix_giltf_en(phl)=%d, fix_giltf_en(Final)=%d, fix_giltf=%d\n", + hal_sta_i->ra_info.fix_giltf_en, ra_cfg->fix_giltf_en, ra_cfg->fix_giltf); + + ra_cfg->bw_cap = halbb_hw_bw_mapping(bb, phl_sta_i->chandef.bw, mode); + ra_cfg->init_rate_lv = 0; + ra_cfg->ss_num = tx_nss; + mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi, mode, tx_nss); + halbb_ramask_trans(bb, macid, mod_mask); + BB_DBG(bb, DBG_RA, "RA update: %x %x %x\n", bb_h2c[0], bb_h2c[1], + bb_h2c[2]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c); + return ret_val; +} + +bool halbb_raupdate_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i) +{ + u8 macid; + struct bb_h2c_ra_cfg_info *ra_cfg; + struct rtw_hal_stainfo_t *hal_sta_i; + struct protocol_cap_t *asoc_cap_i; + u8 tx_nss; + u8 rssi; + u8 init_lv = 0; + u8 mode = 0; + u8 giltf_cap = 0; + bool ret_val = false; + /* Need to mapping with driver wifi mode*/ + u32 *bb_h2c; + u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info); + u64 mod_mask; + + macid = (u8)(phl_sta_i->macid); + hal_sta_i = phl_sta_i->hal_sta; + + ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + mode = ra_cfg->mode_ctrl; + bb_h2c = (u32 *) ra_cfg; + asoc_cap_i = &phl_sta_i->asoc_cap; + rssi = hal_sta_i->rssi_stat.rssi >> 1; + /*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/ + tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx); + ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra; + mod_mask = hal_sta_i->ra_info.cur_ra_mask; + ra_cfg->upd_all= false; + ra_cfg->upd_bw_nss_mask= false; + ra_cfg->upd_mask= true; + /* while ra mask is updated, gi_ltf can also be update */ + mode = ra_cfg->mode_ctrl; + if (mode == 0) + return ret_val; + ra_cfg->mode_ctrl = mode; + ra_cfg->init_rate_lv = 0; + /* ONLY need to get the optional gi-ltf combination for H2C FW*/ + /* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/ + giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi); + ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap); + + /* giltf assigned by phl/halbb or trained by FW*/ + if (hal_sta_i->ra_info.fix_giltf_en == false) { /*giltf from halbb*/ + if (bb->ic_type & (BB_RTL8852A | BB_RTL8852B | BB_RTL8852C)) { /*Disable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = true; + ra_cfg->fix_giltf = RTW_GILTF_2XHE08; + /* gi_ltf is decided by delay spread. This is not ready. + if (is_giltf_decided_by_delay_sp) + ra_cfg->fix_giltf = halbb_ra_giltf_ctrl(bb, macid, delay_sp, asoc_cap_i->ltf_gi); + */ + } else { /*Enable FW train GI_LTF*/ + ra_cfg->fix_giltf_en = false; + } + } else { /*giltf from phl*/ + ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf); + } + BB_DBG(bb, DBG_RA, "fix_giltf_en(phl)=%d, fix_giltf_en(Final)=%d, fix_giltf=%d\n", + hal_sta_i->ra_info.fix_giltf_en, ra_cfg->fix_giltf_en, ra_cfg->fix_giltf); + + mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi, mode, tx_nss); + halbb_ramask_trans(bb, macid, mod_mask); + BB_DBG(bb, DBG_RA, "RA update mask: %x %x %x\n", bb_h2c[0], bb_h2c[1], + bb_h2c[2]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c); + return ret_val; +} + +u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h) +{ + u16 macid_rpt; + struct rtw_hal_stainfo_t *hal_sta_i; + struct rtw_phl_stainfo_t *phl_sta_i; + struct rtw_rate_info *rt_i; + struct halbb_ra_rpt_info *ra_rpt_i; + + if (!c2h) + return 0; + ra_rpt_i = (struct halbb_ra_rpt_info *)c2h; + macid_rpt = ra_rpt_i->rpt_macid_l + (ra_rpt_i->rpt_macid_m << 8); + if (macid_rpt >= PHL_MAX_STA_NUM) { + BB_WARNING("[%s]Error macid = %d!!\n", __func__, macid_rpt); + return 0; + } + if (!bb->sta_exist[macid_rpt]) { + BB_WARNING("[%s]Error macid = %d!!\n", __func__, macid_rpt); + return 0; + } + phl_sta_i = bb->phl_sta_info[(u8)macid_rpt]; + if (!phl_sta_i) { + BB_WARNING("[%s]phl_sta==NULL, Wrong C2H RA macid !!\n", __func__); + return 0; + } + hal_sta_i = phl_sta_i->hal_sta; + if (!hal_sta_i) { + BB_WARNING("[%s]hal_sta==NULL, Wrong C2H RA macid !!\n", __func__); + return 0; + } + hal_sta_i->ra_info.curr_retry_ratio = ra_rpt_i->retry_ratio; + rt_i = &hal_sta_i->ra_info.rpt_rt_i; + rt_i->mcs_ss_idx = ra_rpt_i->rpt_mcs_nss; + rt_i->gi_ltf = ra_rpt_i->rpt_gi_ltf; + rt_i->bw = ra_rpt_i->rpt_bw; + rt_i->mode = ra_rpt_i->rpt_md_sel; + BB_DBG(bb, DBG_RA, "RA RPT: macid = %d, mode = %d, giltf = %x, mcs_nss = %x\n", + macid_rpt, rt_i->mode, rt_i->gi_ltf, rt_i->mcs_ss_idx); + return 0; +} + +bool rtw_halbb_query_txsts(struct bb_info *bb, u16 macid0, u16 macid1) +{ + u8 content[4]; + u32 *bb_h2c = (u32 *)content; + bool ret_val; + u16 cmdlen = 4; + + BB_DBG(bb, DBG_RA, "====> QuerryTxSts : macid = %d %d\n", macid0, macid1); + content[0] = (u8)(macid0& 0xff); + content[1] = (u8)((macid0>>8)& 0xff); + content[2] = (u8)(macid1& 0xff); + content[3] = (u8)((macid1>>8)& 0xff); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_GET_TXSTS, HALBB_H2C_RA, bb_h2c); + if (!ret_val) + BB_WARNING("Error H2C cmd in querry txsts !!\n"); + return ret_val; +} + +void halbb_drv_cmac_rpt_parsing(struct bb_info *bb, u8 *rpt) +{ + struct bb_fw_cmac_rpt_info *c_rpt; + u16 rpt_len, i; + u8 *rpt_tmp = rpt; + + if (!rpt) + return; + c_rpt = (struct bb_fw_cmac_rpt_info *)rpt; + rpt_len = sizeof(struct bb_fw_cmac_rpt_info); + if (rpt_len % 4) { + return; + } + BB_DBG(bb, DBG_RA, + "[%d] try_rate=%d, fix_rate=0x%x, final{rate, giltf}={0x%x,0x%x}, data_bw = 0x%x\n", + c_rpt->macid, c_rpt->try_rate, c_rpt->fix_rate, + c_rpt->final_rate, c_rpt->final_gi_ltf, c_rpt->data_bw); + for (i = 0; i < rpt_len; i++) { + BB_DBG(bb, DBG_RA, "[%d] 0x%x\n", i, *(u32*)rpt); + rpt_tmp += 4; + } +} + +u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h) +{ + u16 macid_rpt; + u8 i = 0; + struct rtw_hal_stainfo_t *hal_sta_i; + struct rtw_phl_stainfo_t *phl_sta_i; + struct rtw_ra_sta_info *ra_sta_i; + struct halbb_txsts_info *txsts_i; + u16 tx_total; + u16 tx_ok[4]; + u16 tx_retry[4]; + + if (!c2h) + return 0; + txsts_i = (struct halbb_txsts_info *)c2h; + macid_rpt = txsts_i->rpt_macid_l + (txsts_i->rpt_macid_m << 8); + if (macid_rpt >= PHL_MAX_STA_NUM) { + BB_WARNING("report macid = %d, Error macid !!\n", macid_rpt); + return 0; + } + if (!bb->sta_exist[macid_rpt]) { + BB_WARNING("report macid = %d, Error macid !!\n", macid_rpt); + return 0; + } + phl_sta_i = bb->phl_sta_info[(u8)macid_rpt]; + if (phl_sta_i == NULL) { + BB_WARNING("phl_sta == NULL, Wrong C2H RA macid !!\n"); + return 0; + } + hal_sta_i = phl_sta_i->hal_sta; + if (hal_sta_i == NULL) { + BB_WARNING("hal_sta == NULL, Wrong C2H RA macid !!\n"); + return 0; + } + ra_sta_i = &hal_sta_i->ra_info; + tx_ok[0] = txsts_i->tx_ok_be_l + (txsts_i->tx_ok_be_m << 8); + tx_ok[1] = txsts_i->tx_ok_bk_l + (txsts_i->tx_ok_bk_m << 8); + tx_ok[2] = txsts_i->tx_ok_vi_l + (txsts_i->tx_ok_vi_m << 8); + tx_ok[3] = txsts_i->tx_ok_vo_l + (txsts_i->tx_ok_vo_m << 8); + tx_retry[0] = txsts_i->tx_retry_be_l + (txsts_i->tx_retry_be_m << 8); + tx_retry[1] = txsts_i->tx_retry_bk_l + (txsts_i->tx_retry_bk_m << 8); + tx_retry[2] = txsts_i->tx_retry_vi_l + (txsts_i->tx_retry_vi_m << 8); + tx_retry[3] = txsts_i->tx_retry_vo_l + (txsts_i->tx_retry_vo_m << 8); + for ( i = 0; i <= 3; i++) { + if ((0xffffffff - ra_sta_i->tx_ok_cnt[i]) > (tx_ok[i])) + ra_sta_i->tx_ok_cnt[i] += tx_ok[i]; + if ((0xffffffff - ra_sta_i->tx_retry_cnt[i]) > (tx_retry[i])) + ra_sta_i->tx_retry_cnt[i] += tx_retry[i]; + BB_DBG(bb, DBG_RA, "TxOk[%d] = %d, TxRty[%d] = %d\n", i, tx_ok[i], i, tx_retry[i]); + } + tx_total = txsts_i->tx_total_l + (txsts_i->tx_total_m << 8); + if ((0xffffffff - ra_sta_i->tx_total_cnt) > tx_total) + ra_sta_i->tx_total_cnt += tx_total; + BB_DBG(bb, DBG_RA, "====> GetTxSts : TxTotal = %d\n", tx_total); + return 0; +} + +void halbb_ra_rssisetting(struct bb_info *bb) +{ + u8 macid = 0; + u8 i = 0, sta_cnt = 0; + u16 cmdlen; + bool ret_val = true; + struct rtw_ra_sta_info *bb_ra; + struct rtw_hal_stainfo_t *hal_sta_i; + struct bb_h2c_rssi_setting *rssi_i; + struct bb_link_info *bb_link = &bb->bb_link_i; + u16 rssi_len = 0; + u32 *bb_h2c; + u8 rssi_a = 0; + u8 rssi_b = 0; + + rssi_len = sizeof(struct bb_h2c_rssi_setting) * PHL_MAX_STA_NUM; + rssi_i = hal_mem_alloc(bb->hal_com, rssi_len); + if (!rssi_i) { + BB_WARNING(" Error RSSI allocat failed!!\n"); + return; + } + bb_h2c = (u32 *)rssi_i; + cmdlen = rssi_len; + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!bb->sta_exist[i] || !bb->phl_sta_info[i]) + continue; + + hal_sta_i = bb->phl_sta_info[i]->hal_sta; + if (!hal_sta_i) + continue; + + bb_ra = &hal_sta_i->ra_info; + if (!(bb_ra->ra_registered)) + continue; + + macid = (u8)(bb->phl_sta_info[i]->macid); + BB_DBG(bb, DBG_RA, "Add BB rssi info[%d], macid=%d\n", i, macid); + /* Need modify for Nss > 2 */ + rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f; + if (!bb->hal_com->dbcc_en) + rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f; + rssi_i[sta_cnt].macid = macid; + rssi_i[sta_cnt].rssi = rssi_a | BIT(7); + rssi_i[sta_cnt].rainfo1 = 0; + rssi_i[sta_cnt].rainfo2 = 0; /* RSVD */ + rssi_i[sta_cnt].drv_ractrl = 0; /* RSVD */ + rssi_i[sta_cnt].is_fixed_rate = bb_ra->fixed_rt_en; + rssi_i[sta_cnt].fixed_rate = bb_ra->fixed_rt_i.mcs_ss_idx; + rssi_i[sta_cnt].fixed_rate_md = bb_ra->fixed_rt_i.mode; + rssi_i[sta_cnt].fixed_giltf = bb_ra->fixed_rt_i.gi_ltf; + rssi_i[sta_cnt].fixed_bw = bb_ra->fixed_rt_i.bw; + rssi_i[sta_cnt].rsvd2_rssi_b = rssi_b; + sta_cnt++; + + if (sta_cnt == bb_link->num_linked_client) + break; + } + + if (sta_cnt == STA_NUM_RSSI_CMD) { + /* Fill endcmd = 1 for last sta */ + rssi_i[sta_cnt - 1].endcmd = 1; + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, + HALBB_H2C_RA, bb_h2c); + BB_DBG(bb, DBG_RA, "sta_cnt=%d, RSSI cmd end 1\n", sta_cnt); + } else if ((sta_cnt > 0) && (sta_cnt < STA_NUM_RSSI_CMD)) { + /* Fill endcmd = 1 for last sta */ + rssi_i[sta_cnt - 1].endcmd = 1; + rssi_i[sta_cnt].macid = 0xff; + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, + HALBB_H2C_RA, bb_h2c); + BB_DBG(bb, DBG_RA, "sta_cnt=%d, RSSI cmd end 2\n", sta_cnt); + } + + BB_DBG(bb, DBG_RA, "RSSI=>h2c[0~3]: %x %x %x %x\n", bb_h2c[0], bb_h2c[1], + bb_h2c[2], bb_h2c[3]); + + if (ret_val == false) + BB_WARNING(" H2C cmd error!!\n"); + + if (rssi_i) + hal_mem_free(bb->hal_com, rssi_i, rssi_len); + +} + +void halbb_ra_giltf_ctrl(struct bb_info *bb, u8 macid, u8 delay_sp, u8 assoc_giltf) +{ + struct bb_ra_info *bb_ra = &bb->bb_ra_i[macid]; + struct bb_h2c_ra_cfg_info *ra_cfg = &bb->bb_ra_i[macid].ra_cfg; + enum rtw_gi_ltf giltf = RTW_GILTF_LGI_4XHE32; + + if (!bb) + return; + /*This dhould be decision before ra mask h2c*/ + /* GI LTF decision algorithm is needed*/ + /*if (delay_sp) + giltf = RTW_GILTF_LGI_4XHE32; + else + giltf = RTW_GILTF_LGI_4XHE32; + ra_cfg->giltf = giltf;*/ +} + +void halbb_ra_watchdog(struct bb_info *bb) +{ + struct bb_link_info *bb_link = &bb->bb_link_i; + u8 i = 0, sta_cnt = 0, macid = 0; +#if 0 + if (!(bb->support_ability & BB_RA)) + return; +#endif + + halbb_ra_rssisetting(bb); + for (i = 0; i < PHL_MAX_STA_NUM; i++) { + if (!(bb->sta_exist[i])) + continue; + + if (!(bb->phl_sta_info[i]) || !bb) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + continue; + } + + if (!(bb->phl_sta_info[i]->hal_sta)) { + BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n"); + continue; + } + + if (!(bb->phl_sta_info[i]->hal_sta->ra_info.ra_registered)) + continue; + + macid = (u8)(bb->phl_sta_info[i]->macid); + BB_DBG(bb, DBG_RA, "====>ra update mask[%d], macid=%d\n", i, macid); + halbb_raupdate_mask(bb, bb->phl_sta_info[i]); + + sta_cnt++; + + if (sta_cnt == bb_link->num_linked_client) + break; + } +} + +void halbb_ra_init(struct bb_info *bb) +{ + struct bb_ra_info *bb_ra = NULL; + u8 macid = 0; + + for (macid = 0; macid < PHL_MAX_STA_NUM; macid ++) { + bb_ra = &bb->bb_ra_i[macid]; + if (!bb_ra) + halbb_mem_set(bb, bb_ra, 0, sizeof (struct bb_ra_info)); + } +} + +u8 rtw_halbb_rts_rate(struct bb_info *bb, u16 tx_rate, bool is_erp_prot) +{ + + u8 rts_ini_rate = RTW_DATA_RATE_OFDM6; + + if (is_erp_prot) { /* use CCK rate as RTS */ + rts_ini_rate = RTW_DATA_RATE_CCK1; + } else { + switch (tx_rate) { + case RTW_DATA_RATE_VHT_NSS4_MCS9: + case RTW_DATA_RATE_VHT_NSS4_MCS8: + case RTW_DATA_RATE_VHT_NSS4_MCS7: + case RTW_DATA_RATE_VHT_NSS4_MCS6: + case RTW_DATA_RATE_VHT_NSS4_MCS5: + case RTW_DATA_RATE_VHT_NSS4_MCS4: + case RTW_DATA_RATE_VHT_NSS4_MCS3: + case RTW_DATA_RATE_VHT_NSS3_MCS9: + case RTW_DATA_RATE_VHT_NSS3_MCS8: + case RTW_DATA_RATE_VHT_NSS3_MCS7: + case RTW_DATA_RATE_VHT_NSS3_MCS6: + case RTW_DATA_RATE_VHT_NSS3_MCS5: + case RTW_DATA_RATE_VHT_NSS3_MCS4: + case RTW_DATA_RATE_VHT_NSS3_MCS3: + case RTW_DATA_RATE_VHT_NSS2_MCS9: + case RTW_DATA_RATE_VHT_NSS2_MCS8: + case RTW_DATA_RATE_VHT_NSS2_MCS7: + case RTW_DATA_RATE_VHT_NSS2_MCS6: + case RTW_DATA_RATE_VHT_NSS2_MCS5: + case RTW_DATA_RATE_VHT_NSS2_MCS4: + case RTW_DATA_RATE_VHT_NSS2_MCS3: + case RTW_DATA_RATE_VHT_NSS1_MCS9: + case RTW_DATA_RATE_VHT_NSS1_MCS8: + case RTW_DATA_RATE_VHT_NSS1_MCS7: + case RTW_DATA_RATE_VHT_NSS1_MCS6: + case RTW_DATA_RATE_VHT_NSS1_MCS5: + case RTW_DATA_RATE_VHT_NSS1_MCS4: + case RTW_DATA_RATE_VHT_NSS1_MCS3: + case RTW_DATA_RATE_MCS31: + case RTW_DATA_RATE_MCS30: + case RTW_DATA_RATE_MCS29: + case RTW_DATA_RATE_MCS28: + case RTW_DATA_RATE_MCS27: + case RTW_DATA_RATE_MCS23: + case RTW_DATA_RATE_MCS22: + case RTW_DATA_RATE_MCS21: + case RTW_DATA_RATE_MCS20: + case RTW_DATA_RATE_MCS19: + case RTW_DATA_RATE_MCS15: + case RTW_DATA_RATE_MCS14: + case RTW_DATA_RATE_MCS13: + case RTW_DATA_RATE_MCS12: + case RTW_DATA_RATE_MCS11: + case RTW_DATA_RATE_MCS7: + case RTW_DATA_RATE_MCS6: + case RTW_DATA_RATE_MCS5: + case RTW_DATA_RATE_MCS4: + case RTW_DATA_RATE_MCS3: + case RTW_DATA_RATE_OFDM54: + case RTW_DATA_RATE_OFDM48: + case RTW_DATA_RATE_OFDM36: + case RTW_DATA_RATE_OFDM24: + rts_ini_rate = RTW_DATA_RATE_OFDM24; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS2: + case RTW_DATA_RATE_VHT_NSS4_MCS1: + case RTW_DATA_RATE_VHT_NSS3_MCS2: + case RTW_DATA_RATE_VHT_NSS3_MCS1: + case RTW_DATA_RATE_VHT_NSS2_MCS2: + case RTW_DATA_RATE_VHT_NSS2_MCS1: + case RTW_DATA_RATE_VHT_NSS1_MCS2: + case RTW_DATA_RATE_VHT_NSS1_MCS1: + case RTW_DATA_RATE_MCS26: + case RTW_DATA_RATE_MCS25: + case RTW_DATA_RATE_MCS18: + case RTW_DATA_RATE_MCS17: + case RTW_DATA_RATE_MCS10: + case RTW_DATA_RATE_MCS9: + case RTW_DATA_RATE_MCS2: + case RTW_DATA_RATE_MCS1: + case RTW_DATA_RATE_OFDM18: + case RTW_DATA_RATE_OFDM12: + rts_ini_rate = RTW_DATA_RATE_OFDM12; + break; + case RTW_DATA_RATE_VHT_NSS4_MCS0: + case RTW_DATA_RATE_VHT_NSS3_MCS0: + case RTW_DATA_RATE_VHT_NSS2_MCS0: + case RTW_DATA_RATE_VHT_NSS1_MCS0: + case RTW_DATA_RATE_MCS24: + case RTW_DATA_RATE_MCS16: + case RTW_DATA_RATE_MCS8: + case RTW_DATA_RATE_MCS0: + case RTW_DATA_RATE_OFDM9: + case RTW_DATA_RATE_OFDM6: + rts_ini_rate = RTW_DATA_RATE_OFDM6; + break; + case RTW_DATA_RATE_CCK11: + case RTW_DATA_RATE_CCK5_5: + case RTW_DATA_RATE_CCK2: + case RTW_DATA_RATE_CCK1: + rts_ini_rate = RTW_DATA_RATE_CCK1; + break; + default: + rts_ini_rate = RTW_DATA_RATE_OFDM6; + break; + } + } + + if (bb->hal_com->band[0].cur_chandef.band == BAND_ON_5G) { + if (rts_ini_rate < RTW_DATA_RATE_OFDM6) + rts_ini_rate = RTW_DATA_RATE_OFDM6; + } + return rts_ini_rate; +} + +void halbb_ra_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + u8 rssi_assoc = 60; + bool ret_val = false; + struct rtw_ra_sta_info *bb_ra; + struct rtw_hal_stainfo_t *hal_sta_i; + //struct bb_h2c_rssi_setting *rssi_i; + u16 rssi_len = 0; + u8 rssi_a = 0; + u8 rssi_b = 0; + + if (_os_strcmp(input[1], help) == 0) { + //BB_DBG_CNSL(out_len, used, output + used, out_len - used, + // "{Test ra mode}: [ra] [100] [macid] [mode 0: fixed rate, 1:fixed macidcfg]\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{Fix rate} [ra] [1] [macid] [mode] [giltf] [ss_mcs] [bw])\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{Auto rate}: [ra] [2] [macid]\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "=============Notes=============>\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[mode]: 0:(legacy), 1:(HT), 2:(VHT), 3:(HE)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[giltf]: 0: (4xHE-LTF 3.2usGI), 1: (4xHE-LTF 0.8usGI), 2: (2xHE-LTF 1.6usGI)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[giltf]: 3: (2xHE-LTF 0.8usGI), 4: (1xHE-LTF 1.6usGI), 5: (1xHE-LTF 0.8usGI)\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "[ss_mcs]: (Bitmap format) [6:4]: Nsts [3:0]: MCS\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "==============================>\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{Drvier shift rate up/down threshold}: [ra] [3] [macid] [0: Increase th. (Tend to RU) 1: Decrease th (Tend to RD)] [percent]\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{Manually adjust RA mask}: [ra] [4] [macid] [0: dis. manual adj. RA mask; 1: en. manual adj. RA mask] [0: mask; 1: reveal] [rate_mode] [ss_mcs]\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{d_o_timer}: [ra] [5] [macid] [en] [timer (FW default 20)]\n"); + + //BB_DBG_CNSL(out_len, used, output + used, out_len - used, + // "{Fix rate & ra mask}: ra (3 [macid] [mode] [giltf] [ss_mcs] [mask1] [mask0])}\n"); + goto out; + } + for (i = 0; i < 8; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + //rssi_len = sizeof(struct bb_h2c_rssi_setting); + //rssi_i = hal_mem_alloc(bb->hal_com, rssi_len); + + if (0) { /* Test RA mode */ + /* + bb_h2c = (u32 *) &ra_cfg; + ra_cfg.bw_cap = 0; + ra_cfg.mode_ctrl = (u8)val[2]; + ra_cfg.is_dis_ra= false; + ra_cfg.macid = (u8)val[1]; + ra_cfg.stbc_cap = false; + ra_cfg.ldpc_cap = false; + ra_cfg.en_sgi = false; + ra_cfg.upd_all = true; + ra_cfg.init_rate_lv = 1; + ra_cfg.er_cap = false; + ra_cfg.dcm_cap = false; + ra_cfg.upd_mask = false; + ra_cfg.upd_bw_nss_mask = false; + ra_cfg.giltf = 0; + ra_cfg.ss_num = 1; + for (i = 0; i < 8; i++) + ra_cfg.ramask[i] = 0xff; + BB_DBG(bb, DBG_RA, "RA Register: %x %x %x\n", bb_h2c[0], bb_h2c[1], + bb_h2c[2]); + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c); + */ + } else if (val[0] == 1) { + struct bb_h2c_rssi_setting rssi_i; + u32 *bb_h2c = (u32 *) &rssi_i; + u8 cmdlen = sizeof(struct bb_h2c_rssi_setting); + + hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta; + bb_ra = &hal_sta_i->ra_info; + if (bb_ra->ra_registered) { + BB_DBG(bb, DBG_RA, "RA fix rate macid=[%d]\n", (u8)val[1]); + /* Need modify for Nss > 2 */ + rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f; + if (!bb->hal_com->dbcc_en) + rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f; + rssi_i.macid = (u8)val[1]; + rssi_i.rssi = rssi_a | BIT(7); + rssi_i.is_fixed_rate = true; + rssi_i.fixed_rate = (u8)val[4]; + rssi_i.fixed_giltf = (u8)val[3]; + rssi_i.fixed_bw = (u8)val[5]; + rssi_i.fixed_rate_md = (u8)val[2]; + rssi_i.rsvd2_rssi_b = rssi_b; + rssi_i.endcmd = 1; + + bb_ra->fixed_rt_en = rssi_i.is_fixed_rate; + bb_ra->fixed_rt_i.mcs_ss_idx = rssi_i.fixed_rate; + bb_ra->fixed_rt_i.mode = rssi_i.fixed_rate_md; + bb_ra->fixed_rt_i.gi_ltf = rssi_i.fixed_giltf; + bb_ra->fixed_rt_i.bw = rssi_i.fixed_bw; + BB_DBG(bb, DBG_RA, "RA fix rate H2C: %x %x\n", bb_h2c[0], bb_h2c[1]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, HALBB_H2C_RA, bb_h2c); + } else { + BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n"); + } + } else if (val[0] == 2) { + struct bb_h2c_rssi_setting rssi_i; + u32 *bb_h2c = (u32 *) &rssi_i; + u8 cmdlen = sizeof(struct bb_h2c_rssi_setting); + + hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta; + bb_ra = &hal_sta_i->ra_info; + if (bb_ra->ra_registered) { + BB_DBG(bb, DBG_RA, "RA auto rate macid=[%d]\n", (u8)val[1]); + /* Need modify for Nss > 2 */ + rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f; + if (!bb->hal_com->dbcc_en) + rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f; + rssi_i.macid = (u8)val[1]; + rssi_i.rssi = rssi_a | BIT(7); + rssi_i.is_fixed_rate = false; + rssi_i.rsvd2_rssi_b = rssi_b; + rssi_i.endcmd = 1; + + bb_ra->fixed_rt_en = rssi_i.is_fixed_rate; + BB_DBG(bb, DBG_RA, "RA auto rate H2C: %x %x\n", bb_h2c[0], bb_h2c[1]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, HALBB_H2C_RA, bb_h2c); + } else { + BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n"); + } + } else if (val[0] == 3) { + struct bb_h2c_ra_adjust ra_th_i; + u32 *bb_h2c = (u32 *) &ra_th_i; + u8 cmdlen = sizeof(struct bb_h2c_ra_adjust); + + hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta; + bb_ra = &hal_sta_i->ra_info; + if (bb_ra->ra_registered) { + BB_DBG(bb, DBG_RA, "RA adjust th. macid=[%d]\n", (u8)val[1]); + ra_th_i.macid = (u8)val[1]; + ra_th_i.drv_shift_en = (u8)val[2] & 0x01; + ra_th_i.drv_shift_value= (u8)val[3] & 0x7f; + + BB_DBG(bb, DBG_RA, "RA adjust %s th =[%d]\n", + ra_th_i.drv_shift_en == 0x1 ? "RD": "RU", ra_th_i.drv_shift_value); + + BB_DBG(bb, DBG_RA, "RA adjust th H2C: %x %x\n", bb_h2c[0], bb_h2c[1]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RA_ADJUST, HALBB_H2C_RA, bb_h2c); + } else { + BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n"); + } + } else if (val[0] == 4) { + struct bb_h2c_ra_mask ra_mask_i; + u32 *bb_h2c = (u32 *) &ra_mask_i; + u8 cmdlen = sizeof(struct bb_h2c_ra_mask); + + hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta; + bb_ra = &hal_sta_i->ra_info; + + if (bb_ra->ra_registered) { + BB_DBG(bb, DBG_RA, "macid=[%d]\n", (u8)val[1]); + + ra_mask_i.macid = (u8)val[1]; + ra_mask_i.is_manual_adjust_ra_mask = (u8)val[2] & 0x01; + ra_mask_i.mask_or_reveal = (u8)val[3] & 0x01; + ra_mask_i.mask_rate_md= (u8)val[4]; + ra_mask_i.mask_rate= (u8)val[5]; + + BB_DBG(bb, DBG_RA, "Manual adjust RA mask = %d\n", + ra_mask_i.is_manual_adjust_ra_mask); + BB_DBG(bb, DBG_RA, "Adjust mode=%d, rate(d')=%d\n", + ra_mask_i.mask_rate_md, ra_mask_i.mask_rate); + BB_DBG(bb, DBG_RA, "[%s] this rate in RA mask\n", + ra_mask_i.mask_or_reveal ? "Reveal": "Mask"); + BB_DBG(bb, DBG_RA, "RA adjust th H2C: %x %x\n", + bb_h2c[0], bb_h2c[1]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_ADJUST_RA_MASK, HALBB_H2C_RA, bb_h2c); + } else { + BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n"); + } + } else if (val[0] == 5) { + struct bb_h2c_ra_d_o_timer ra_d_o_timer_i; + u32 *bb_h2c = (u32 *) &ra_d_o_timer_i; + u8 cmdlen = sizeof(struct bb_h2c_ra_d_o_timer); + + hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta; + bb_ra = &hal_sta_i->ra_info; + if (bb_ra->ra_registered) { + BB_DBG(bb, DBG_RA, "RA d_o_timer macid=[%d]\n", (u8)val[1]); + ra_d_o_timer_i.macid = (u8)val[1]; + ra_d_o_timer_i.d_o_timer_en = (u8)val[2] & 0x01; + ra_d_o_timer_i.d_o_timer_value= (u8)val[3] & 0x7f; + + BB_DBG(bb, DBG_RA, "RA d_o_timer {en,value} = {%d,%d}\n", + ra_d_o_timer_i.d_o_timer_en , ra_d_o_timer_i.d_o_timer_value); + + BB_DBG(bb, DBG_RA, "RA d_o_timer H2C: %x\n", bb_h2c[0]); + + ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RA_D_O_TIMER, HALBB_H2C_RA, bb_h2c); + } else { + BB_DBG(bb, DBG_RA, "No Link ! RA d_o_timer cmd fail!\n"); + } + } + //if (rssi_i) + // hal_mem_free(bb->hal_com, rssi_i, rssi_len); +out: + *_used = used; + *_out_len = out_len; +} + +#endif + + diff --git a/phl/hal_g6/phy/bb/halbb_ra.h b/phl/hal_g6/phy/bb/halbb_ra.h new file mode 100644 index 0000000..d1cb186 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ra.h @@ -0,0 +1,282 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_RA_H_ +#define _HALBB_RA_H_ + +/*@--------------------------[extern] ---------------------------------------*/ +extern const u16 bb_phy_rate_table[LEGACY_RATE_NUM + HE_RATE_NUM_4SS]; +/*@--------------------------[Define] ---------------------------------------*/ +#define VHT_2_HE32_RATE(X) ((((X) << 3) + (X) + 4) >> 3) /*= Round(X * 1.125)*/ +#define HE32_2_HE16_RATE(X) ((((X) << 3) + (X) + 4) >> 3) /*= Round(X * 1.125)*/ +#define HE32_2_HE08_RATE(X) ((((X) << 4) + ((X) << 1) + (X) + 8) >> 4) /*= Round(X * 1.1875)*/ + +#define RAMASK_B 0x000000000000000f +#define RAMASK_AG 0x0000000000000ff0 +#define RAMASK_BG 0x0000000000000ff5 +#define RAMASK_HT_2G 0x00000ffffffff015 +#define RAMASK_HT_5G 0x00000ffffffff010 +#define RAMASK_VHT_2G 0x000ffffffffff015 +#define RAMASK_VHT_5G 0x000ffffffffff010 +#define RAMASK_HE_2G 0x0ffffffffffff015 +#define RAMASK_HE_5G 0x0ffffffffffff010 + +#define RAMASK_1SS_HT 0x00000000000fffff +#define RAMASK_2SS_HT 0x00000000ff0fffff +#define RAMASK_3SS_HT 0x00000ff0ff0fffff +#define RAMASK_4SS_HT 0x00ff0ff0ff0fffff + +#define RAMASK_1SS_VHT 0x00000000003fffff +#define RAMASK_2SS_VHT 0x00000003ff3fffff +#define RAMASK_3SS_VHT 0x00003ff3ff3fffff +#define RAMASK_4SS_VHT 0x03ff3ff3ff3fffff + +#define RAMASK_1SS_HE 0x0000000000ffffff +#define RAMASK_2SS_HE 0x0000000fffffffff +#define RAMASK_3SS_HE 0x0000ffffffffffff +#define RAMASK_4SS_HE 0x0fffffffffffffff + +#define MAX_ABG_RATE_NUM 12 +#define MAX_NSS_VHT 4 +#define MAX_NSS_HT 4 +#define MAX_NSS_HE 4 + +#define STA_NUM_RSSI_CMD PHL_MAX_STA_NUM + +#define MASKRATE_AX 0x01ff +#define MASKGILTF_AX 0x0e00 + +/* WiFi Support Mode */ +#define CCK_SUPPORT BIT(0) +#define OFDM_SUPPORT BIT(1) +#define HT_SUPPORT BIT(2) +#define VHT_SUPPORT_TX BIT(3) +#define HE_SUPPORT BIT(4) + +#define RA_FLOOR_TABLE_SIZE 7 +#define RA_FLOOR_UP_GAP 3 + +#define MAX_RATE_HE 24 +#define MAX_RATE_VHT 40 // 8198F is 4SS +#define MAX_RATE_HT 32 + +/*@--------------------------[Enum]------------------------------------------*/ + +/* rate_idx table used in FW*/ +enum rate_table { + RATE_CCK_1M = 0x00, + RATE_CCK_2M = 0x01, + RATE_CCK_5M = 0x02, + RATE_CCK_11M = 0x03, + RATE_OFDM_6M = 0x04, + RATE_OFDM_9M = 0x05, + RATE_OFDM_12M = 0x06, + RATE_OFDM_18M = 0x07, + RATE_OFDM_24M = 0x08, + RATE_OFDM_36M = 0x09, + RATE_OFDM_48M = 0x0A, + RATE_OFDM_54M = 0x0B, + RATE_HT_MCS0 = 0x0C, + RATE_HT_MCS1 = 0x0D, + RATE_HT_MCS2 = 0x0E, + RATE_HT_MCS3 = 0x0F, + RATE_HT_MCS4 = 0x10, + RATE_HT_MCS5 = 0x11, + RATE_HT_MCS6 = 0x12, + RATE_HT_MCS7 = 0x13, + RATE_HT_MCS8 = 0x14, + RATE_HT_MCS9 = 0x15, + RATE_HT_MCS10 = 0x16, + RATE_HT_MCS11 = 0x17, + RATE_HT_MCS12 = 0x18, + RATE_HT_MCS13 = 0x19, + RATE_HT_MCS14 = 0x1A, + RATE_HT_MCS15 = 0x1B, + RATE_HT_MCS16 = 0x1C, + RATE_HT_MCS17 = 0x1D, + RATE_HT_MCS18 = 0x1E, + RATE_HT_MCS19 = 0x1F, + RATE_HT_MCS20 = 0x20, + RATE_HT_MCS21 = 0x21, + RATE_HT_MCS22 = 0x22, + RATE_HT_MCS23 = 0x23, + RATE_HT_MCS24 = 0x24, + RATE_HT_MCS25 = 0x25, + RATE_HT_MCS26 = 0x26, + RATE_HT_MCS27 = 0x27, + RATE_HT_MCS28 = 0x28, + RATE_HT_MCS29 = 0x29, + RATE_HT_MCS30 = 0x2A, + RATE_HT_MCS31 = 0x2B, + RATE_VHT1SS_MCS0 = 0x2C, + RATE_VHT1SS_MCS1 = 0x2D, + RATE_VHT1SS_MCS2 = 0x2E, + RATE_VHT1SS_MCS3 = 0x2F, + RATE_VHT1SS_MCS4 = 0x30, + RATE_VHT1SS_MCS5 = 0x31, + RATE_VHT1SS_MCS6 = 0x32, + RATE_VHT1SS_MCS7 = 0x33, + RATE_VHT1SS_MCS8 = 0x34, + RATE_VHT1SS_MCS9 = 0x35, + RATE_VHT2SS_MCS0 = 0x36, + RATE_VHT2SS_MCS1 = 0x37, + RATE_VHT2SS_MCS2 = 0x38, + RATE_VHT2SS_MCS3 = 0x39, + RATE_VHT2SS_MCS4 = 0x3A, + RATE_VHT2SS_MCS5 = 0x3B, + RATE_VHT2SS_MCS6 = 0x3C, + RATE_VHT2SS_MCS7 = 0x3D, + RATE_VHT2SS_MCS8 = 0x3E, + RATE_VHT2SS_MCS9 = 0x3F, + RATE_VHT3SS_MCS0 = 0x40, + RATE_VHT3SS_MCS1 = 0x41, + RATE_VHT3SS_MCS2 = 0x42, + RATE_VHT3SS_MCS3 = 0x43, + RATE_VHT3SS_MCS4 = 0x44, + RATE_VHT3SS_MCS5 = 0x45, + RATE_VHT3SS_MCS6 = 0x46, + RATE_VHT3SS_MCS7 = 0x47, + RATE_VHT3SS_MCS8 = 0x48, + RATE_VHT3SS_MCS9 = 0x49, + RATE_VHT4SS_MCS0 = 0x4A, + RATE_VHT4SS_MCS1 = 0x4B, + RATE_VHT4SS_MCS2 = 0x4C, + RATE_VHT4SS_MCS3 = 0x4D, + RATE_VHT4SS_MCS4 = 0x4E, + RATE_VHT4SS_MCS5 = 0x4F, + RATE_VHT4SS_MCS6 = 0x50, + RATE_VHT4SS_MCS7 = 0x51, + RATE_VHT4SS_MCS8 = 0x52, + RATE_VHT4SS_MCS9 = 0x53, + // HE + RATE_HE1SS_MCS0 = 0x54, + RATE_HE1SS_MCS1 = 0x55, + RATE_HE1SS_MCS2 = 0x56, + RATE_HE1SS_MCS3 = 0x57, + RATE_HE1SS_MCS4 = 0x58, + RATE_HE1SS_MCS5 = 0x59, + RATE_HE1SS_MCS6 = 0x5A, + RATE_HE1SS_MCS7 = 0x5B, + RATE_HE1SS_MCS8 = 0x5C, + RATE_HE1SS_MCS9 = 0x5D, + RATE_HE1SS_MCS10 = 0x5E, + RATE_HE1SS_MCS11 = 0x5F, + RATE_HE2SS_MCS0 = 0x60, + RATE_HE2SS_MCS1 = 0x61, + RATE_HE2SS_MCS2 = 0x62, + RATE_HE2SS_MCS3 = 0x63, + RATE_HE2SS_MCS4 = 0x64, + RATE_HE2SS_MCS5 = 0x65, + RATE_HE2SS_MCS6 = 0x66, + RATE_HE2SS_MCS7 = 0x67, + RATE_HE2SS_MCS8 = 0x68, + RATE_HE2SS_MCS9 = 0x69, + RATE_HE2SS_MCS10 = 0x6A, + RATE_HE2SS_MCS11 = 0x6B, +}; + +enum spatial_stream_num { + RA_1SS_MODE = 0, + RA_2SS_MODE = 1, + RA_3SS_MODE = 2, + RA_4SS_MODE = 3 +}; + +enum wifi_mode { + RA_CCK = 0, + RA_non_ht = 1, + RA_HT = 2, + RA_VHT = 3, + RA_HE = 4 +}; + +enum mu_cmd_type { + MU_ADD_ENTRY = 0, + MU_DEL_ENTRY = 1, + MU_DBG_CTRL =2, +}; + +enum bb_opt_gi_ltf { + BB_OPT_GILTF_4XHE08 = 0, + BB_OPT_GILTF_1XHE08 = 1 +}; + + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_rate_info { + u16 rate_idx_all; + u16 rate_idx; + enum rtw_gi_ltf gi_ltf; + enum bb_mode_type mode; /*0:legacy, 1:HT, 2*/ + enum channel_width bw; + u8 ss; + u8 idx; + u8 fw_rate_idx; +}; + +struct bb_ra_info { + /* Config move to phl_sta_info*/ + struct bb_h2c_ra_cfg_info ra_cfg; + u8 cal_giltf; + /* Ctrl */ + u8 drv_ractrl; + bool fixed_rate_en; + u8 fixed_rate; /* 7bit rate */ + u8 fixed_rat_md; /* 2bit rate_mode */ + u8 fixed_giltf; /* 3bit giltf */ + u8 fixed_bw; /* 2bit bw */ + u8 rssi; /* should not put here */ + u8 rainfo_cfg1; /* prepare for other control*/ + u8 rainfo_cfg2; /* prepare for other control*/ + + u8 rssi_lv; + + /* Report */ + u8 rpt_rate; /* 7bit rate + 2bit rat_md + 3bit giltf + 2bit bw */ + u8 rpt_rat_md; + u8 rpt_giltf; + u8 rpt_bw; + u8 rpt_ratio; + + u8 tmp; + +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ + +struct bb_info; +bool halbb_is_cck_rate(struct bb_info *bb, u16 rate); +bool halbb_is_ofdm_rate(struct bb_info *bb, u16 rate); +bool halbb_is_ht_rate(struct bb_info *bb, u16 rate); +bool halbb_is_vht_rate(struct bb_info *bb, u16 rate); +bool halbb_is_he_rate(struct bb_info *bb, u16 rate); +u8 halbb_legacy_rate_2_spec_rate(struct bb_info *bb, u16 rate); +u8 halbb_rate_2_rate_digit(struct bb_info *bb, u16 rate); +u8 halbb_get_rx_stream_num(struct bb_info *bb, enum rf_type type); +u8 halbb_rate_type_2_num_ss(struct bb_info *bb, enum halbb_rate_type type); +u8 halbb_rate_to_num_ss(struct bb_info *bb, u16 rate); +void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size); +enum bb_qam_type halbb_get_qam_order(struct bb_info *bb, u16 rate_idx); +u8 halbb_rate_order_compute(struct bb_info *bb, u16 rate_idx); +void halbb_ra_watchdog(struct bb_info *bb); + +void halbb_ra_init(struct bb_info *bb); +void halbb_ra_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i); +u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h); +u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ra_b_endian.h b/phl/hal_g6/phy/bb/halbb_ra_b_endian.h new file mode 100644 index 0000000..b5be031 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ra_b_endian.h @@ -0,0 +1,252 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_RA_B_ENDIAN_H_ +#define _HALBB_RA_B_ENDIAN_H_ +/*@--------------------------[Define] ---------------------------------------*/ + + +/*@--------------------------[Enum]------------------------------------------*/ + + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_fw_cmac_rpt_info { /*need to translate to big endian*/ + /* dword 0 */ + u32 rpt_sel: 5; + u32 polluted: 1; + u32 tx_state: 2; + u32 sw_define: 4; + u32 rsvd0: 2; + u32 try_rate: 1; + u32 fix_rate: 1; + u32 macid: 7; + u32 rsvd1: 1; + u32 qsel: 6; + u32 rsvd2: 1; + u32 txop_start: 1; + /* dword 1 */ + u32 queue_time: 16; + u32 acc_tx_time: 8; + u32 rsvd3: 5; + u32 bmc: 1; + u32 bitmap_short: 2; + /* dword 2 */ + u32 final_rate: 9; + u32 final_gi_ltf: 3; + u32 data_bw: 2; + u32 mu2su: 1; + u32 mu_lmt: 1; + u32 final_rts_rate: 9; + u32 final_rts_gi_ltf: 3; + u32 rts_tx_state: 2; + u32 collision_head: 1; + u32 collision_tail: 1; + /* dword 3 */ + u32 total_pkt_num: 8; + u32 data_tx_cnt: 6; + u32 bpri: 1; + u32 bbar: 1; + u32 pkt_ok_num: 8; + u32 rts_tx_count: 6; + u32 rsvd4: 2; + /* dword 4 */ + u32 init_rate: 9; + u32 init_gi_ltf: 3; + u32 ppdu_type: 2; + u32 he_tb_ppdu_flag: 1; + u32 ppdu_fst_rpt: 1; + u32 su_txpwr: 6; + u32 rsvd5: 2; + u32 diff_pkt_num: 4; + u32 user_define_ext_l: 4; + /* dword 5 */ + u32 user_define: 8; + u32 fw_define: 8; + u32 txpwr_pd: 5; + u32 bsr: 1; + u32 rsvd6: 2; + u32 sr_rx_count: 4; + u32 user_define_ext_h: 4; +}; + +struct bb_h2c_ra_cfg_info { + + u8 bw_cap:2; + u8 mode_ctrl:5; + /* + @ Bit0 : CCK + @ Bit1 : OFDM + @ Bit2 : HT + @ Bit3 : VHT + @ Bit4 : HE + */ + u8 is_dis_ra:1; + + u8 macid; + + u8 stbc_cap:1; + u8 ldpc_cap:1; + u8 en_sgi:1; + u8 upd_all:1; + u8 init_rate_lv:2; + u8 er_cap:1; + u8 dcm_cap:1; + + u8 upd_mask:1; + u8 upd_bw_nss_mask:1; + u8 giltf_cap:3; + u8 ss_num:3; + + + u8 ramask[8]; /* ramask[7] bit 7 is for indicate bfee csi rate ctrl */ + + /* BFee CSI rate ctrl */ + u8 band_num; + + u8 rsvd2:1; + u8 fix_giltf:3; + u8 fix_giltf_en:1; + u8 cr_tbl_sel:1; + u8 fixed_csi_rate_en:1; + u8 ra_csi_rate_en:1; + + u8 fixed_csi_rate_l; + + u8 fixed_csi_rate_m; +}; + +struct bb_h2c_rssi_setting { + u8 macid; + u8 rssi; + u8 rainfo1; + u8 rainfo2; + + u8 drv_ractrl; + /* RSVD */ + + u8 fixed_rate:7; + u8 is_fixed_rate:1; + + u8 rsvd2_M:1; + u8 fixed_bw:2; + u8 fixed_giltf:3; + u8 fixed_rate_md:2; + + u8 endcmd:1; + u8 rsvd2_rssi_b:7; +}; + +struct bb_h2c_ra_mask { + u8 macid; + + u8 mask_rate:7; + u8 mask_or_reveal:1; + + u8 rsvd1:5; + u8 is_manual_adjust_ra_mask:1; + u8 mask_rate_md:2; + + u8 rsvd2; +}; + +struct bb_h2c_ra_adjust { + u8 macid; + + u8 drv_shift_en:1; + u8 drv_shift_value:7; +}; + +struct bb_h2c_ra_d_o_timer { + u8 macid; + + u8 d_o_timer_en:1; + u8 d_o_timer_value:7; +}; + +struct bb_h2c_mu_cfg { + u8 cmd_type; + u8 entry; + u8 macid; + + u8 rsvd3:6; + u8 en_1024q:1; + u8 en_256q:1; +}; + +struct halbb_ra_rpt_info { + u8 rpt_macid_l; + u8 rpt_macid_m; + + u8 retry_ratio; + u8 rsvd0; + + u8 rsvd1: 1; + u8 rpt_mcs_nss: 7; + + u8 rsvd2: 1; + u8 rpt_bw: 2; + u8 rpt_gi_ltf: 3; + u8 rpt_md_sel: 2; + + u8 rsvd3; + u8 rsvd4; +}; + +struct halbb_txsts_info { + u8 rpt_macid_l; + u8 rpt_macid_m; + + u8 avg_agg; + u8 rsvd0; + + u8 tx_ok_be_l; + u8 tx_ok_be_m; + u8 tx_ok_bk_l; + u8 tx_ok_bk_m; + u8 tx_ok_vi_l; + u8 tx_ok_vi_m; + u8 tx_ok_vo_l; + u8 tx_ok_vo_m; + + u8 tx_retry_be_l; + u8 tx_retry_be_m; + u8 tx_retry_bk_l; + u8 tx_retry_bk_m; + u8 tx_retry_vi_l; + u8 tx_retry_vi_m; + u8 tx_retry_vo_l; + u8 tx_retry_vo_m; + + + u8 tx_rate_l; + u8 tx_rate_m; + u8 retry_ratio; + u8 rsvd1; + + u8 tx_total_l; + u8 tx_total_m; + u8 rsvd2; + u8 rsvd3; + + u8 rsvd4; + u8 rsvd5; + u8 rsvd6; + u8 rsvd7; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ + + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ra_ex.h b/phl/hal_g6/phy/bb/halbb_ra_ex.h new file mode 100644 index 0000000..d202bae --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ra_ex.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_RA_EX_H_ +#define _HALBB_RA_EX_H_ +/*@--------------------------[Define] ---------------------------------------*/ + + + +/*@--------------------------[Enum]------------------------------------------*/ + + + +/*@--------------------------[Structure]-------------------------------------*/ + + +/*@--------------------------[Prptotype]-------------------------------------*/ + + +extern bool rtw_halbb_raregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +extern bool rtw_halbb_raupdate(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +extern bool rtw_halbb_dft_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +extern bool rtw_halbb_ra_deregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i); +extern bool rtw_halbb_query_txsts(struct bb_info *bb, u16 macid0, u16 macid1); +void halbb_drv_cmac_rpt_parsing(struct bb_info *bb, u8 *rpt); + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_ra_l_endian.h b/phl/hal_g6/phy/bb/halbb_ra_l_endian.h new file mode 100644 index 0000000..3cbbc94 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_ra_l_endian.h @@ -0,0 +1,250 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALBB_RA_L_ENDIAN_H_ +#define _HALBB_RA_L_ENDIAN_H_ +/*@--------------------------[Define] ---------------------------------------*/ + + + +/*@--------------------------[Enum]------------------------------------------*/ + + + +/*@--------------------------[Structure]-------------------------------------*/ + +struct bb_fw_cmac_rpt_info { + /* dword 0 */ + u32 rpt_sel: 5; + u32 polluted: 1; + u32 tx_state: 2; + u32 sw_define: 4; + u32 rsvd0: 2; + u32 try_rate: 1; + u32 fix_rate: 1; + u32 macid: 7; + u32 rsvd1: 1; + u32 qsel: 6; + u32 rsvd2: 1; + u32 txop_start: 1; + /* dword 1 */ + u32 queue_time: 16; + u32 acc_tx_time: 8; + u32 rsvd3: 5; + u32 bmc: 1; + u32 bitmap_short: 2; + /* dword 2 */ + u32 final_rate: 9; + u32 final_gi_ltf: 3; + u32 data_bw: 2; + u32 mu2su: 1; + u32 mu_lmt: 1; + u32 final_rts_rate: 9; + u32 final_rts_gi_ltf: 3; + u32 rts_tx_state: 2; + u32 collision_head: 1; + u32 collision_tail: 1; + /* dword 3 */ + u32 total_pkt_num: 8; + u32 data_tx_cnt: 6; + u32 bpri: 1; + u32 bbar: 1; + u32 pkt_ok_num: 8; + u32 rts_tx_count: 6; + u32 rsvd4: 2; + /* dword 4 */ + u32 init_rate: 9; + u32 init_gi_ltf: 3; + u32 ppdu_type: 2; + u32 he_tb_ppdu_flag: 1; + u32 ppdu_fst_rpt: 1; + u32 su_txpwr: 6; + u32 rsvd5: 2; + u32 diff_pkt_num: 4; + u32 user_define_ext_l: 4; + /* dword 5 */ + u32 user_define: 8; + u32 fw_define: 8; + u32 txpwr_pd: 5; + u32 bsr: 1; + u32 rsvd6: 2; + u32 sr_rx_count: 4; + u32 user_define_ext_h: 4; +}; + +struct bb_h2c_ra_cfg_info { + u8 is_dis_ra:1; + u8 mode_ctrl:5; + /* + @ Bit0 : CCK + @ Bit1 : OFDM + @ Bit2 : HT + @ Bit3 : VHT + @ Bit4 : HE + */ + u8 bw_cap:2; + + u8 macid; + + u8 dcm_cap:1; + u8 er_cap:1; + u8 init_rate_lv:2; + u8 upd_all:1; + u8 en_sgi:1; + u8 ldpc_cap:1; + u8 stbc_cap:1; + + u8 ss_num:3; + u8 giltf_cap:3; + u8 upd_bw_nss_mask:1; + u8 upd_mask:1; + + u8 ramask[8]; /* ramask[7] bit 7 is for indicate bfee csi rate ctrl */ + + /* BFee CSI rate ctrl */ + u8 band_num; + + u8 ra_csi_rate_en:1; + u8 fixed_csi_rate_en:1; + u8 cr_tbl_sel:1; + u8 fix_giltf_en:1; + u8 fix_giltf:3; + u8 rsvd2:1; + + u8 fixed_csi_rate_l; + + u8 fixed_csi_rate_m; +}; + +struct bb_h2c_rssi_setting { + u8 macid; + u8 rssi; + u8 rainfo1; + u8 rainfo2; + + u8 drv_ractrl; + /* RSVD */ + + u8 is_fixed_rate:1; + u8 fixed_rate:7; + + u8 fixed_rate_md:2; + u8 fixed_giltf:3; + u8 fixed_bw:2; + u8 rsvd2_M:1; + + u8 rsvd2_rssi_b:7; + u8 endcmd:1; +}; + +struct bb_h2c_ra_mask { + u8 macid; + + u8 mask_or_reveal:1; + u8 mask_rate:7; + + u8 mask_rate_md:2; + u8 is_manual_adjust_ra_mask:1; + u8 rsvd1:5; + + u8 rsvd2; +}; + +struct bb_h2c_ra_adjust { + u8 macid; + + u8 drv_shift_value:7; + u8 drv_shift_en:1; +}; + +struct bb_h2c_ra_d_o_timer { + u8 macid; + + u8 d_o_timer_value:7; + u8 d_o_timer_en:1; +}; + +struct bb_h2c_mu_cfg { + u8 cmd_type; + u8 entry; + u8 macid; + u8 en_256q:1; + u8 en_1024q:1; + u8 rsvd3:6; +}; + +struct halbb_ra_rpt_info { + u8 rpt_macid_l; + u8 rpt_macid_m; + + u8 retry_ratio; + u8 rsvd0; + + u8 rpt_mcs_nss: 7; + u8 rsvd1: 1; + + u8 rpt_md_sel: 2; + u8 rpt_gi_ltf: 3; + u8 rpt_bw: 2; + u8 rsvd2: 1; + + u8 rsvd3; + u8 rsvd4; +}; + +struct halbb_txsts_info { + u8 rpt_macid_l; + u8 rpt_macid_m; + + u8 avg_agg; + u8 rsvd0; + + u8 tx_ok_be_l; + u8 tx_ok_be_m; + u8 tx_ok_bk_l; + u8 tx_ok_bk_m; + u8 tx_ok_vi_l; + u8 tx_ok_vi_m; + u8 tx_ok_vo_l; + u8 tx_ok_vo_m; + + u8 tx_retry_be_l; + u8 tx_retry_be_m; + u8 tx_retry_bk_l; + u8 tx_retry_bk_m; + u8 tx_retry_vi_l; + u8 tx_retry_vi_m; + u8 tx_retry_vo_l; + u8 tx_retry_vo_m; + + + u8 tx_rate_l; + u8 tx_rate_m; + u8 retry_ratio; + u8 rsvd1; + + u8 tx_total_l; + u8 tx_total_m; + u8 rsvd2; + u8 rsvd3; + + u8 rsvd4; + u8 rsvd5; + u8 rsvd6; + u8 rsvd7; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_rua_tbl.c b/phl/hal_g6/phy/bb/halbb_rua_tbl.c new file mode 100644 index 0000000..00d9660 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_rua_tbl.c @@ -0,0 +1,1566 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_RUA_SUPPORT + +u32 halbb_rua_tbl_hdr_cfg(struct bb_info *bb, + struct rtw_rua_tbl_hdr *rtw_tbl_hdr, + struct halbb_rua_tbl_hdr_info *rua_tbl_hdr) +{ + u32 ret = RTW_HAL_STATUS_SUCCESS; + + /*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/ + BB_DBG(bb, DBG_RUA_TBL, "halbb_rau_tbl_hdr_cfg\n"); + rua_tbl_hdr->idx = rtw_tbl_hdr->idx; + rua_tbl_hdr->rw = rtw_tbl_hdr->rw; + rua_tbl_hdr->len_l= (u8)(rtw_tbl_hdr->len&0x0007); + rua_tbl_hdr->len_m= (u8)((rtw_tbl_hdr->len&0x03f8)>>3); + rua_tbl_hdr->offset= (u8)rtw_tbl_hdr->offset; + rua_tbl_hdr->type = (u8)rtw_tbl_hdr->type; + rua_tbl_hdr->tbl_class = rtw_tbl_hdr->tbl_class; + + return ret; +} + +void halbb_ru_rate_cfg(struct bb_info *bb, + struct rtw_ru_rate_ent *rate_ent, + struct halbb_ru_rate_info *rate_i) +{ + BB_DBG(bb, DBG_RUA_TBL, "halbb_ru_rate_cfg\n"); + rate_i->dcm = rate_ent->dcm; + rate_i->mcs = rate_ent->mcs; + rate_i->ss = rate_ent->ss; +} + +u32 halbb_dlfix_sta_i_ax4ru_cfg(struct bb_info *bb, + struct rtw_dlfix_sta_i_ax4ru *sta_ent, + struct halbb_dl_fix_sta_info *fix_sta_i) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 i; + + /*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/ + BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n"); + + if ((!fix_sta_i) || (!sta_ent)) { + BB_WARNING("halbb_rua_sta_info_cfg: NULL pointer!!\n"); + return ret; + } + + fix_sta_i->mac_id = sta_ent->mac_id; + for (i = 0; i < 3; i++) + fix_sta_i->ru_pos[i] = sta_ent->ru_pos[i]; + fix_sta_i->fix_rate = sta_ent->fix_rate; + fix_sta_i->fix_coding = sta_ent->fix_coding; + fix_sta_i->fix_txbf = sta_ent->fix_txbf; + fix_sta_i->fix_pwr_fac = sta_ent->fix_pwr_fac; + halbb_ru_rate_cfg(bb, &(sta_ent->rate), &(fix_sta_i->rate_i)); + fix_sta_i->txbf = sta_ent->txbf; + fix_sta_i->coding = sta_ent->coding; + fix_sta_i->pwr_boost_fac = sta_ent->pwr_boost_fac; + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_ulfix_sta_i_ax4ru_cfg(struct bb_info *bb, + struct rtw_ulfix_sta_i_ax4ru *sta_ent, + struct halbb_ul_fix_sta_info *fix_sta_i) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 i; + + /*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/ + BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n"); + + if ((!fix_sta_i) || (!sta_ent)) { + BB_WARNING("halbb_rua_sta_info_cfg: NULL pointer!!\n"); + return ret; + } + + fix_sta_i->mac_id = sta_ent->mac_id; + for (i = 0; i < 3; i++) { + fix_sta_i->ru_pos[i] = sta_ent->ru_pos[i]; + fix_sta_i->tgt_rssi[i] = sta_ent->tgt_rssi[i]; + } + fix_sta_i->fix_tgt_rssi = sta_ent->fix_tgt_rssi; + fix_sta_i->fix_rate = sta_ent->fix_rate; + fix_sta_i->fix_coding = sta_ent->fix_coding; + fix_sta_i->coding = sta_ent->coding; + halbb_ru_rate_cfg(bb, &(sta_ent->rate), &(fix_sta_i->rate_i)); + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_tf_ba_tbl_info_cfg(struct bb_info *bb, + struct rtw_tf_ba_tbl *tf_tbl, + struct halbb_tf_ba_tbl_info *tf_i) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + + /*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/ + BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n"); + + if ((!tf_i) || (!tf_tbl)) { + BB_WARNING("halbb_tf_ba_tbl_info_cfg: NULL pointer!!\n"); + return ret; + } + tf_i->fix_ba = (u8)tf_tbl->fix_ba; + tf_i->ru_psd_l = (u8)(tf_tbl->ru_psd&0x007f); + tf_i->ru_psd_m = (u8)((tf_tbl->ru_psd&0x0180)>>7); + tf_i->tf_rate_l = (u8)(tf_tbl->tf_rate&0x003f); + tf_i->tf_rate_m = (u8)((tf_tbl->tf_rate&0x01c0)>>6); + tf_i->rf_gain_fix = (u8)tf_tbl->rf_gain_fix; + tf_i->rf_gain_idx_l = (u8)(tf_tbl->rf_gain_idx&0x0000000f); + tf_i->rf_gain_idx_m = (u8)((tf_tbl->rf_gain_idx&0x000003f0)>>4); + tf_i->tb_ppdu_bw = (u8)tf_tbl->tb_ppdu_bw; + halbb_ru_rate_cfg(bb, &(tf_tbl->rate), &(tf_i->rate_i)); + + tf_i->gi_ltf = tf_tbl->gi_ltf; + tf_i->doppler = tf_tbl->doppler; + tf_i->stbc = tf_tbl->stbc; + tf_i->sta_coding = tf_tbl->sta_coding; + tf_i->tb_t_pe_nom = tf_tbl->tb_t_pe_nom; + tf_i->pr20_bw_en = tf_tbl->pr20_bw_en; + tf_i->ma_type = tf_tbl->ma_type; + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +void halbb_rua_tbl_init(struct bb_info *bb) +{ + + BB_DBG(bb, DBG_RUA_TBL, "RUA TBL Init\n"); + +} + +u32 halbb_upd_dlru_fixtbl_ax4ru(struct bb_info *bb, + struct rtw_dlru_fixtbl_ax4ru *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 i; + bool ret_v= false; + u8 len = sizeof(struct rtw_dlru_fixtbl_ax4ru); + struct halbb_dl_ru_fix_tbl_info *fix_tbl_i; + u8 pkt_len = sizeof(struct halbb_dl_ru_fix_tbl_info); + u32 *bb_h2c = NULL; + /*u8 *buf;*/ + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_dlru_fixtbl: in_len = %d, out_len = %d\n", len, pkt_len); + //if (len != pkt_len) + // BB_WARNING("halbb_upd_dlru_fixtbl: tble length mismatch!!\n"); + + fix_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) fix_tbl_i; + info->tbl_hdr.len= sizeof(struct halbb_dl_ru_fix_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = DL_RU_FIX_TBL; + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(fix_tbl_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + fix_tbl_i->max_sta_num = info->max_sta_num; + fix_tbl_i->min_sta_num = info->min_sta_num; + fix_tbl_i->doppler = info->doppler; + fix_tbl_i->stbc = info->stbc; + fix_tbl_i->gi_ltf = info->gi_ltf; + fix_tbl_i->ma_type = info->ma_type; + fix_tbl_i->fixru_flag = info->fixru_flag; + fix_tbl_i->rupos_csht_flag = info->rupos_csht_flag; + fix_tbl_i->ru_swp_flg = info->ru_swp_flg; + for (i = 0; i < HALBB_AX4RU_STA_NUM; i++) + halbb_dlfix_sta_i_ax4ru_cfg(bb, &(info->sta[i]), &(fix_tbl_i->sta_i[i])); + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); +out: + if (fix_tbl_i) + hal_mem_free(bb->hal_com, fix_tbl_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_upd_dlru_fixtbl(struct bb_info *bb, + union rtw_dlru_fixtbl *union_info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + default: + ret = RTW_HAL_STATUS_FAILURE; + break; + } + + return ret; +} + +u32 halbb_upd_ulru_fixtbl_ax4ru(struct bb_info *bb, + struct rtw_ulru_fixtbl_ax4ru *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 i; + bool ret_v= false; + u8 len = sizeof(struct rtw_ulru_fixtbl_ax4ru); + struct halbb_ul_ru_fix_tbl_info *fix_tbl_i; + u8 pkt_len = sizeof(struct halbb_ul_ru_fix_tbl_info); + u32 *bb_h2c = NULL; + /*u8 *buf;*/ + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ulru_fixtbl: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_upd_ulru_fixtbl: tble length mismatch!!\n"); + + fix_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) fix_tbl_i; + info->tbl_hdr.len= sizeof(struct halbb_ul_ru_fix_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = UL_RU_FIX_TBL; + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(fix_tbl_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + + fix_tbl_i->max_sta_num = info->max_sta_num; + fix_tbl_i->min_sta_num = info->min_sta_num; + fix_tbl_i->doppler = info->doppler; + fix_tbl_i->ma_type = info->ma_type; + fix_tbl_i->gi_ltf = info->gi_ltf; + fix_tbl_i->stbc = info->stbc; + fix_tbl_i->fix_tb_t_pe_nom = info->fix_tb_t_pe_nom; + fix_tbl_i->tb_t_pe_nom = info->tb_t_pe_nom; + fix_tbl_i->fixru_flag = info->fixru_flag; + for (i = 0; i < HALBB_AX4RU_STA_NUM; i++) + halbb_ulfix_sta_i_ax4ru_cfg(bb, &(info->sta[i]), &(fix_tbl_i->sta_i[i])); + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); +out: + if (fix_tbl_i) + hal_mem_free(bb->hal_com, fix_tbl_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + + +u32 halbb_upd_ulru_fixtbl(struct bb_info *bb, + union rtw_ulru_fixtbl *union_info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + switch (bb->ic_type) { + + #ifdef BB_8852A_2_SUPPORT + case BB_RTL8852A: + ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + #ifdef BB_8852B_SUPPORT + case BB_RTL8852B: + ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + #ifdef BB_8852C_SUPPORT + case BB_RTL8852C: + ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru)); + break; + #endif + + default: + ret = RTW_HAL_STATUS_FAILURE; + break; + } + + return ret; +} + +u32 halbb_upd_dlru_grptbl(struct bb_info *bb, + struct rtw_dl_ru_gp_tbl *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + bool ret_v= false; + u8 len = sizeof(struct rtw_dl_ru_gp_tbl); + struct halbb_dl_ru_gp_tbl_info *gp_tbl_i; + u8 pkt_len = sizeof(struct halbb_dl_ru_gp_tbl_info); + u32 *bb_h2c = NULL; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_dlru_grptbl: in_len = %d, out_len = %d\n", len, pkt_len); + //if (len != pkt_len) + // BB_WARNING("halbb_upd_dlru_grptbl: tble length mismatch!!\n"); + gp_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len); + bb_h2c=(u32 *) gp_tbl_i; + info->tbl_hdr.len= sizeof(struct halbb_dl_ru_gp_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = DL_RU_GP_TBL; + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(gp_tbl_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + gp_tbl_i->ppdu_bw = (u8)info->ppdu_bw; + gp_tbl_i->tx_pwr_l = (u8)(info->tx_pwr&0x003f); + gp_tbl_i->tx_pwr_m = (u8)((info->tx_pwr&0x01c0)>>6); + gp_tbl_i->pwr_boost_fac = (u8)info->pwr_boost_fac; + gp_tbl_i->fix_mode_flag = info->fix_mode_flag; + ret = halbb_tf_ba_tbl_info_cfg(bb, &(info->tf), &(gp_tbl_i->tf)); + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); +out: + if (gp_tbl_i) + hal_mem_free(bb->hal_com, gp_tbl_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_upd_ulru_grptbl(struct bb_info *bb, + struct rtw_ul_ru_gp_tbl *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + bool ret_v= false; + u8 len = sizeof(struct rtw_ul_ru_gp_tbl); + struct halbb_ul_ru_gp_tbl_info *gp_tbl_i; + u8 pkt_len = sizeof(struct halbb_ul_ru_gp_tbl_info); + u32 *bb_h2c = NULL; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ulru_grptbl: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_upd_ulru_grptbl: tble length mismatch!!\n"); + gp_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len); + bb_h2c = (u32 *) gp_tbl_i; + + info->tbl_hdr.len= sizeof(struct halbb_ul_ru_gp_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = UL_RU_GP_TBL; + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(gp_tbl_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + + gp_tbl_i->grp_psd_max_l = (u8)(info->grp_psd_max&0x00ff); + gp_tbl_i->grp_psd_max_m = (u8)((info->grp_psd_max>>8)&0x0001); + gp_tbl_i->grp_psd_min_l = (u8)(info->grp_psd_min&0x007f); + gp_tbl_i->grp_psd_min_m = (u8)((info->grp_psd_min>>7)&0x0003); + gp_tbl_i->tf_rate_l = (u8)(info->tf_rate&0x003f); + gp_tbl_i->tf_rate_m = (u8)((info->tf_rate>>6)&0x0007); + gp_tbl_i->fix_tf_rate = (u8)info->fix_tf_rate; + gp_tbl_i->ppdu_bw = (u8)info->ppdu_bw; + gp_tbl_i->rf_gain_fix = (u8)info->rf_gain_fix; + gp_tbl_i->rf_gain_idx_l = (u8)(info->rf_gain_idx&0x001f); + gp_tbl_i->rf_gain_idx_m = (u8)((info->rf_gain_idx>>5)&0x001f); + gp_tbl_i->fix_mode_flag = (u8)info->fix_mode_flag; + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); +out: + if (gp_tbl_i) + hal_mem_free(bb->hal_com, gp_tbl_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_upd_rusta_info(struct bb_info *bb, + struct rtw_ru_sta_info *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_ru_sta_info); + struct halbb_ru_sta_info *ru_sta_i; + u8 pkt_len = sizeof(struct halbb_ru_sta_info); + u32 *bb_h2c = NULL; + u8 i = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_rusta_info: in_len = %d, out_len = %d\n", len, pkt_len); + //if (len != pkt_len) + // BB_WARNING("halbb_upd_rusta_info: tble length mismatch!!\n"); + ru_sta_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c=(u32 *) ru_sta_i; + + info->tbl_hdr.len = sizeof(struct halbb_ru_sta_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = RU_STA_INFO; + + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ru_sta_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + ru_sta_i->gi_ltf_48spt = info->gi_ltf_48spt; + ru_sta_i->gi_ltf_18spt = info->gi_ltf_18spt; + ru_sta_i->dlsu_info_en = info->dlsu_info_en; + ru_sta_i->dlsu_bw = info->dlsu_bw; + ru_sta_i->dlsu_gi_ltf = info->dlsu_gi_ltf; + ru_sta_i->dlsu_doppler_ctrl = info->dlsu_doppler_ctrl; + ru_sta_i->dlsu_coding = info->dlsu_coding; + ru_sta_i->dlsu_txbf = info->dlsu_txbf; + ru_sta_i->dlsu_stbc = info->dlsu_stbc; + ru_sta_i->dl_fwcqi_flag = info->dl_fwcqi_flag; + ru_sta_i->dlru_ratetbl_ridx = info->dlru_ratetbl_ridx; + ru_sta_i->csi_info_bitmap = info->csi_info_bitmap; + for (i = 0; i < 4; i++) + ru_sta_i->dl_swgrp_bitmap[i] = (u8)((info->dl_swgrp_bitmap) >> (i<<3))&0xff; + ru_sta_i->dlsu_dcm = (u8)info->dlsu_dcm; + ru_sta_i->dlsu_rate_l = (u8)(info->dlsu_rate&0x0001); + ru_sta_i->dlsu_rate_m = (u8)((info->dlsu_rate>>1)&0x00ff); + ru_sta_i->dlsu_pwr = info->dlsu_pwr; + ru_sta_i->ulsu_info_en = info->ulsu_info_en; + ru_sta_i->ulsu_bw = info->ulsu_bw; + ru_sta_i->ulsu_gi_ltf = info->ulsu_gi_ltf; + ru_sta_i->ulsu_doppler_ctrl = info->ulsu_doppler_ctrl; + ru_sta_i->ulsu_dcm = info->ulsu_dcm; + ru_sta_i->ulsu_ss = info->ulsu_ss; + ru_sta_i->ulsu_mcs = info->ulsu_mcs; + ru_sta_i->ul_fwcqi_flag = (u8)info->ul_fwcqi_flag; + ru_sta_i->ulru_ratetbl_ridx = (u8)info->ulru_ratetbl_ridx; + ru_sta_i->ulsu_stbc = (u8)info->ulsu_stbc; + ru_sta_i->ulsu_coding = (u8)info->ulsu_coding; + ru_sta_i->ulsu_rssi_m_l = (u8)(info->ulsu_rssi_m&0x0001); + ru_sta_i->ulsu_rssi_m_m = (u8)((info->ulsu_rssi_m>>1)&0x00ff); + for (i = 0; i < 4; i++) + ru_sta_i->ul_swgrp_bitmap[i] = (u8)((info->ul_swgrp_bitmap) >> (i<<3))&0xff; + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); + +out: + if (ru_sta_i) + hal_mem_free(bb->hal_com, ru_sta_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_upd_ba_infotbl(struct bb_info *bb, + struct rtw_ba_tbl_info *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_ba_tbl_info); + struct halbb_ba_tbl_info *ba_i; + u8 pkt_len = sizeof(struct halbb_ba_tbl_info); + u32 *bb_h2c = NULL; + u8 i = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ba_infotbl: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_upd_ba_infotbl: tble length mismatch!!\n"); + ba_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) ba_i; + + info->tbl_hdr.len = sizeof(struct halbb_ba_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = BA_INFO_TBL; + + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ba_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + ret = halbb_tf_ba_tbl_info_cfg( bb, &(info->tf_ba_t), &(ba_i->tf_i)); + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c); + +out: + if (ba_i) + hal_mem_free(bb->hal_com, ba_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; +} + +u32 halbb_swgrp_hdl(struct bb_info *bb, struct rtw_sw_grp_set *info) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_sw_grp_set); + struct halbb_sw_grp_set *swgrp_i; + u8 pkt_len = sizeof(struct halbb_sw_grp_set); + u32 *bb_h2c = NULL; + u8 i,j = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_swgrp_hdl: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_swgrp_hdl: tble length mismatch!!\n"); + swgrp_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) swgrp_i; + + /* + info->tbl_hdr.len = sizeof(struct halbb_tf_ba_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info); + info->tbl_hdr.tbl_class = BA_INFO_TBL; + + ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ba_i->tbl_hdr_i)); + if (ret == RTW_HAL_STATUS_FAILURE) + goto out; + */ + for (i = 0; i < 8; i++) { + swgrp_i->swgrp_bitmap[i].macid= info->swgrp_bitmap[i].macid; + swgrp_i->swgrp_bitmap[i].en_upd_dl_swgrp = info->swgrp_bitmap[i].en_upd_dl_swgrp; + swgrp_i->swgrp_bitmap[i].en_upd_ul_swgrp = info->swgrp_bitmap[i].en_upd_ul_swgrp; + for (j = 0; j < 4; j++) { + swgrp_i->swgrp_bitmap[i].dl_sw_grp_bitmap[j] = (u8)((info->swgrp_bitmap[i].dl_sw_grp_bitmap) >> (j<<3))&0xff; + swgrp_i->swgrp_bitmap[i].ul_sw_grp_bitmap[j] = (u8)((info->swgrp_bitmap[i].ul_sw_grp_bitmap) >> (j<<3))&0xff; + } + swgrp_i->swgrp_bitmap[i].cmdend= info->swgrp_bitmap[i].cmdend; + if (swgrp_i->swgrp_bitmap[i].cmdend) + break; + } + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_SWGRP, HALBB_H2C_RUA, bb_h2c); + +//out: + if (swgrp_i) + hal_mem_free(bb->hal_com, swgrp_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + +u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_dl_macid_cfg); + struct dl_macid_cfg *dlmac_i; + u8 pkt_len = sizeof(struct dl_macid_cfg); + u32 *bb_h2c = NULL; + //u8 i,j = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_dlmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_dlmacid_cfg: tble length mismatch!!\n"); + dlmac_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) dlmac_i; + + dlmac_i->macid = (u8)cfg->macid; + + dlmac_i->dl_su_rate_cfg = (u8)cfg->dl_su_rate_cfg; + dlmac_i->dl_su_rate_l = (u8)(cfg->dl_su_rate & 0x7f); + dlmac_i->dl_su_rate_m= (u8)(cfg->dl_su_rate & 0x180)>>7; + dlmac_i->dl_su_bw = (u8)cfg->dl_su_bw; + + dlmac_i->dl_su_pwr_cfg = (u8)cfg->dl_su_pwr_cfg; + dlmac_i->dl_su_pwr_l= (u8)(cfg->dl_su_pwr & 0x7); + dlmac_i->dl_su_pwr_m= (u8)(cfg->dl_su_pwr & 0x38)>>3; + + dlmac_i->gi_ltf_4x8_support = (u8)cfg->gi_ltf_4x8_support; + dlmac_i->gi_ltf_1x8_support = (u8)cfg->gi_ltf_1x8_support; + + dlmac_i->dl_su_info_en = (u8)cfg->dl_su_info_en; + + dlmac_i->dl_su_gi_ltf = (u8)cfg->dl_su_gi_ltf; + dlmac_i->dl_su_doppler_ctrl = (u8)cfg->dl_su_doppler_ctrl; + dlmac_i->dl_su_coding = (u8)cfg->dl_su_coding; + dlmac_i->dl_su_txbf = (u8)cfg->dl_su_txbf; + dlmac_i->dl_su_stbc = (u8)cfg->dl_su_stbc; + dlmac_i->dl_su_dcm = (u8)cfg->dl_su_dcm; + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_DL_MACID, HALBB_H2C_RUA, bb_h2c); +//out: + if (dlmac_i) + hal_mem_free(bb->hal_com, dlmac_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + + +u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_ul_macid_set); + struct halbb_ul_macid_set *ulmac_i; + u8 pkt_len = sizeof(struct halbb_ul_macid_set); + u32 *bb_h2c = NULL; + u8 i = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_ulmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_ulmacid_cfg: tble length mismatch!!\n"); + ulmac_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) ulmac_i; + + for (i = 0; i < 8; i++) { + ulmac_i->ul_macid_cfg[i].macid= (u8)cfg->ul_macid_cfg[i].macid; + ulmac_i->ul_macid_cfg[i].endcmd = (u8)cfg->ul_macid_cfg[i].endcmd; + + ulmac_i->ul_macid_cfg[i].ul_su_info_en = (u8)cfg->ul_macid_cfg[i].ul_su_info_en; + + ulmac_i->ul_macid_cfg[i].ul_su_bw = (u8)cfg->ul_macid_cfg[i].ul_su_bw; + ulmac_i->ul_macid_cfg[i].ul_su_gi_ltf= (u8)cfg->ul_macid_cfg[i].ul_su_gi_ltf; + ulmac_i->ul_macid_cfg[i].ul_su_doppler_ctrl = (u8)cfg->ul_macid_cfg[i].ul_su_doppler_ctrl; + ulmac_i->ul_macid_cfg[i].ul_su_dcm= (u8)cfg->ul_macid_cfg[i].ul_su_dcm; + + ulmac_i->ul_macid_cfg[i].ul_su_ss = (u8)cfg->ul_macid_cfg[i].ul_su_ss; + ulmac_i->ul_macid_cfg[i].ul_su_mcs= (u8)cfg->ul_macid_cfg[i].ul_su_mcs; + ulmac_i->ul_macid_cfg[i].ul_su_coding = (u8)cfg->ul_macid_cfg[i].ul_su_coding; + ulmac_i->ul_macid_cfg[i].ul_su_rssi_m_l= (u8)(cfg->ul_macid_cfg[i].ul_su_rssi_m & 0x1); + ulmac_i->ul_macid_cfg[i].ul_su_rssi_m_m= (u8)(cfg->ul_macid_cfg[i].ul_su_rssi_m & 0x1fe)>>1; + + if (ulmac_i->ul_macid_cfg[i].endcmd) + break; + } + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_UL_MACID, HALBB_H2C_RUA, bb_h2c); +//out: + if (ulmac_i) + hal_mem_free(bb->hal_com, ulmac_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + +u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_csiinfo_cfg); + struct csiinfo_cfg *csiinfo_i; + u8 pkt_len = sizeof(struct csiinfo_cfg); + u32 *bb_h2c = NULL; + //u8 i,j = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_csiinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_csiinfo_cfg: tble length mismatch!!\n"); + csiinfo_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) csiinfo_i; + + csiinfo_i->macid = (u8)cfg->macid; + csiinfo_i->csi_info_bitmap = (u8)cfg->csi_info_bitmap; + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_CSIINFO, HALBB_H2C_RUA, bb_h2c); +//out: + if (csiinfo_i) + hal_mem_free(bb->hal_com, csiinfo_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + + +u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_cqi_set); + struct halbb_cqi_set *cqi_i; + u8 pkt_len = sizeof(struct halbb_cqi_set); + u32 *bb_h2c = NULL; + u8 i,j = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_ulmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_ulmacid_cfg: tble length mismatch!!\n"); + cqi_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) cqi_i; + + for (i = 0; i < 8; i++) { + cqi_i->cqi_info[i].macid= (u8)cfg->cqi_info[i].macid; + cqi_i->cqi_info[i].fw_cqi_flag= (u8)cfg->cqi_info[i].fw_cqi_flag; + cqi_i->cqi_info[i].ru_rate_table_row_idx= (u8)cfg->cqi_info[i].ru_rate_table_row_idx; + cqi_i->cqi_info[i].ul_dl= (u8)cfg->cqi_info[i].ul_dl; + cqi_i->cqi_info[i].endcmd = (u8)cfg->cqi_info[i].endcmd; + + for (j=0;j<19;j++) + cqi_i->cqi_info[i].cqi_diff_table[j]= (u8)cfg->cqi_info[i].cqi_diff_table[j]; + + if (cqi_i->cqi_info[i].endcmd) + break; + } + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_CQI, HALBB_H2C_RUA, bb_h2c); +//out: + if (cqi_i) + hal_mem_free(bb->hal_com, cqi_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + +u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_bbinfo_cfg); + struct halbb_bb_info_cfg *bbinfo_i; + u8 pkt_len = sizeof(struct halbb_bb_info_cfg); + u32 *bb_h2c = NULL; + //u8 i,j = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_bbinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_bbinfo_cfg: tble length mismatch!!\n"); + bbinfo_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) bbinfo_i; + + bbinfo_i->p20_ch_bitmap = (u8)cfg->p20_ch_bitmap; + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_BBINFO, HALBB_H2C_RUA, bb_h2c); +//out: + if (bbinfo_i) + hal_mem_free(bb->hal_com, bbinfo_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + + +u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg) +{ + u32 ret = RTW_HAL_STATUS_FAILURE; + u8 len = sizeof(struct rtw_pwr_by_rt_tbl); + struct halbb_pwr_by_rt_tbl *pbr_i; + u8 pkt_len = sizeof(struct halbb_pwr_by_rt_tbl); + u32 *bb_h2c = NULL; + u8 i = 0; + bool ret_v = false; + + BB_DBG(bb, DBG_RUA_TBL, "halbb_bbinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len); + // if (len != pkt_len) + // BB_WARNING("halbb_bbinfo_cfg: tble length mismatch!!\n"); + pbr_i = hal_mem_alloc(bb->hal_com, pkt_len); + + bb_h2c = (u32 *) pbr_i; + + for (i=0;i<32;i++){ + pbr_i->pwr_by_rt[2*i] = (u8)(cfg->pwr_by_rt[i] & 0xff); + pbr_i->pwr_by_rt[2*i+1] = (u8)((cfg->pwr_by_rt[i] & 0xff00)>>8); + } + + BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2)); + ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_PWR_TBL, HALBB_H2C_RUA, bb_h2c); +//out: + if (pbr_i) + hal_mem_free(bb->hal_com, pbr_i, pkt_len); + if (ret_v) + ret = RTW_HAL_STATUS_SUCCESS; + return ret; + +} + +/* For Test mode */ +void halbb_test_dlru_gp_tbl(struct bb_info *bb, struct rtw_dl_ru_gp_tbl *tbl) +{ + tbl->tbl_hdr.rw = 1; /* write */ + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.len = sizeof(struct rtw_dl_ru_gp_tbl); + tbl->tbl_hdr.type = 0; + tbl->ppdu_bw = 2; + tbl->tx_pwr = 0x3c; + tbl->pwr_boost_fac = 0; + tbl->fix_mode_flag = 1; + tbl->tf.fix_ba = 1; + tbl->tf.ru_psd = 20; + tbl->tf.tf_rate = 388; + tbl->tf.rf_gain_fix = 0; + tbl->tf.rf_gain_idx = 0; + tbl->tf.tb_ppdu_bw = 2; + tbl->tf.rate.dcm = 0; + tbl->tf.rate.mcs = 7; + tbl->tf.rate.ss = 0; + tbl->tf.gi_ltf = 2; + tbl->tf.doppler = 0; + tbl->tf.stbc = 0; + tbl->tf.sta_coding = 1; + tbl->tf.tb_t_pe_nom = 2; + tbl->tf.pr20_bw_en = 0; + tbl->tf.ma_type = 0; +} + +void halbb_test_dl_sta_ent0(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 0; + sta_ent->ru_pos[0] = 122; + sta_ent->ru_pos[1] = 122; + sta_ent->ru_pos[2] = 122; + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->fix_txbf = 1; + sta_ent->fix_pwr_fac = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 1; + sta_ent->txbf = 0; + sta_ent->coding = 1; + sta_ent->pwr_boost_fac = 0; +} + +void halbb_test_dl_sta_ent1(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 1; + sta_ent->ru_pos[0] = 124; + sta_ent->ru_pos[1] = 124; + sta_ent->ru_pos[2] = 124; + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->fix_txbf = 1; + sta_ent->fix_pwr_fac = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 10; + sta_ent->rate.ss = 1; + sta_ent->txbf = 0; + sta_ent->coding = 1; + sta_ent->pwr_boost_fac = 0; +} + +void halbb_test_dl_sta_ent2(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 2; + sta_ent->ru_pos[0] = 0; + sta_ent->ru_pos[1] = 126; + sta_ent->ru_pos[2] = 126; + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->fix_txbf = 1; + sta_ent->fix_pwr_fac = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 9; + sta_ent->rate.ss = 1; + sta_ent->txbf = 0; + sta_ent->coding = 1; + sta_ent->pwr_boost_fac = 0; +} + +void halbb_test_dl_sta_ent3(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 255; + sta_ent->ru_pos[0] = 0; + sta_ent->ru_pos[1] = 0; + sta_ent->ru_pos[2] = 128; + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->fix_txbf = 1; + sta_ent->fix_pwr_fac = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 0; + sta_ent->txbf = 0; + sta_ent->coding = 1; + sta_ent->pwr_boost_fac = 0; +} + +void halbb_test_dl_fix_tbl(struct bb_info *bb, struct rtw_dlru_fixtbl_ax4ru *tbl) +{ + tbl->tbl_hdr.rw = 1; /* write */ + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.len = sizeof(struct rtw_dlru_fixtbl_ax4ru); + tbl->tbl_hdr.type = 0; + /* Need finish */ + tbl->max_sta_num = 4; + tbl->min_sta_num = 2; + tbl->doppler = 0; + tbl->stbc = 0; + tbl->gi_ltf = 3; + tbl->ma_type = 0; + tbl->fixru_flag = 1; + halbb_test_dl_sta_ent0(bb, &(tbl->sta[0])); + halbb_test_dl_sta_ent1(bb, &(tbl->sta[1])); + halbb_test_dl_sta_ent2(bb, &(tbl->sta[2])); + halbb_test_dl_sta_ent3(bb, &(tbl->sta[3])); +} + +void halbb_test_ru_sta_info(struct bb_info *bb, struct rtw_ru_sta_info *tbl) +{ + tbl->tbl_hdr.rw = 1; /* write */ + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.len = sizeof(struct rtw_ru_sta_info); + tbl->tbl_hdr.type = 0; + + tbl->gi_ltf_18spt = 0; + tbl->gi_ltf_48spt = 0; + tbl->dlsu_info_en = 1; + tbl->dlsu_bw = 2; + tbl->dlsu_gi_ltf = 2; + tbl->dlsu_doppler_ctrl = 0; + tbl->dlsu_coding = 1; + tbl->dlsu_txbf = 0; + tbl->dlsu_stbc = 0; + tbl->dl_fwcqi_flag = 0; + tbl->dlru_ratetbl_ridx = 12; + tbl->csi_info_bitmap = 0; + tbl->dl_swgrp_bitmap = 1; + tbl->dlsu_dcm = 0; + tbl->dlsu_rate = 390; + tbl->dlsu_pwr = 25; + + tbl->ulsu_info_en = 1; + tbl->ulsu_bw = 2; + tbl->ulsu_gi_ltf = 3; + tbl->ulsu_doppler_ctrl = 0; + tbl->ulsu_dcm = 0; + tbl->ulsu_ss = 0; + tbl->ulsu_mcs = 7; + tbl->ul_fwcqi_flag = 1; + tbl->ulru_ratetbl_ridx = 13; + tbl->ulsu_stbc = 0; + tbl->ulsu_coding = 1; + tbl->ulsu_rssi_m = 200; + tbl->ul_swgrp_bitmap = 2; +} + +void halbb_test_ul_sta_ent0(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 0; + sta_ent->ru_pos[0] = 122; + sta_ent->ru_pos[1] = 122; + sta_ent->ru_pos[2] = 122; + + sta_ent->fix_tgt_rssi=1; + sta_ent->tgt_rssi[0] = 115; + sta_ent->tgt_rssi[1] = 110; + sta_ent->tgt_rssi[2] = 105; + + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 1; + sta_ent->coding = 1; + +} + +void halbb_test_ul_sta_ent1(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent) +{ + + sta_ent->mac_id = 1; + sta_ent->ru_pos[0] = 124; + sta_ent->ru_pos[1] = 124; + sta_ent->ru_pos[2] = 124; + + sta_ent->fix_tgt_rssi=1; + sta_ent->tgt_rssi[0] = 115; + sta_ent->tgt_rssi[1] = 110; + sta_ent->tgt_rssi[2] = 105; + + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 1; + sta_ent->coding = 1; + +} + +void halbb_test_ul_sta_ent2(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent) +{ + sta_ent->mac_id = 255; + sta_ent->ru_pos[0] = 0; + sta_ent->ru_pos[1] = 126; + sta_ent->ru_pos[2] = 126; + + sta_ent->fix_tgt_rssi=1; + sta_ent->tgt_rssi[0] = 0; + sta_ent->tgt_rssi[1] = 110; + sta_ent->tgt_rssi[2] = 105; + + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 1; + sta_ent->coding = 1; +} + +void halbb_test_ul_sta_ent3(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent) +{ + + sta_ent->mac_id = 255; + sta_ent->ru_pos[0] = 0; + sta_ent->ru_pos[1] = 0; + sta_ent->ru_pos[2] = 128; + + sta_ent->fix_tgt_rssi=1; + sta_ent->tgt_rssi[0] = 0; + sta_ent->tgt_rssi[1] = 0; + sta_ent->tgt_rssi[2] = 105; + + sta_ent->fix_rate = 1; + sta_ent->fix_coding = 1; + sta_ent->rate.dcm = 0; + sta_ent->rate.mcs = 11; + sta_ent->rate.ss = 1; + sta_ent->coding = 1; +} + + +void halbb_test_ul_fix_tbl(struct bb_info *bb, struct rtw_ulru_fixtbl_ax4ru *tbl) +{ + tbl->tbl_hdr.rw = 1; /* write */ + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.type = 0; + /* Need finish */ + + tbl->max_sta_num = 4; + tbl->min_sta_num = 2; + tbl->doppler = 0; + tbl->stbc = 0; + tbl->gi_ltf = 2; + tbl->ma_type = 0; + tbl->fix_tb_t_pe_nom=1; + tbl->tb_t_pe_nom=2; + tbl->fixru_flag = 1; + halbb_test_ul_sta_ent0(bb, &(tbl->sta[0])); + halbb_test_ul_sta_ent1(bb, &(tbl->sta[1])); + halbb_test_ul_sta_ent2(bb, &(tbl->sta[2])); + halbb_test_ul_sta_ent3(bb, &(tbl->sta[3])); +} + +void halbb_test_ulru_gp_tbl(struct bb_info *bb, struct rtw_ul_ru_gp_tbl *tbl) +{ + tbl->tbl_hdr.rw = 1; /* write */ + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.type = 0; + + tbl->grp_psd_max = 100; + tbl->grp_psd_min = 80; + tbl->ppdu_bw = 2; + tbl->tf_rate = 390; + tbl->fix_tf_rate = 1; + tbl->rf_gain_fix = 0; + tbl->rf_gain_idx = 0; + tbl->fix_mode_flag= 1; +} + +void halbb_test_ba_tbl(struct bb_info *bb, struct rtw_ba_tbl_info *tbl) +{ + + tbl->tbl_hdr.rw = 1; + tbl->tbl_hdr.idx = 0; + tbl->tbl_hdr.offset = 0; + tbl->tbl_hdr.len = sizeof(struct rtw_ba_tbl_info); + tbl->tbl_hdr.type = 0; + tbl->tf_ba_t.fix_ba = 1; + tbl->tf_ba_t.ru_psd = 20; + tbl->tf_ba_t.tf_rate = 388; + tbl->tf_ba_t.rf_gain_fix = 0; + tbl->tf_ba_t.rf_gain_idx = 0; + tbl->tf_ba_t.tb_ppdu_bw = 2; + tbl->tf_ba_t.rate.dcm = 0; + tbl->tf_ba_t.rate.mcs = 7; + tbl->tf_ba_t.rate.ss = 0; + tbl->tf_ba_t.gi_ltf = 2; + tbl->tf_ba_t.doppler = 0; + tbl->tf_ba_t.stbc = 0; + tbl->tf_ba_t.sta_coding = 1; + tbl->tf_ba_t.tb_t_pe_nom = 2; + tbl->tf_ba_t.pr20_bw_en = 0; + tbl->tf_ba_t.ma_type = 0; + +} + +void halbb_test_swgrp_hdl(struct bb_info *bb, struct rtw_sw_grp_set *hdl) +{ + hdl->swgrp_bitmap[0].macid = 3; + hdl->swgrp_bitmap[0].en_upd_dl_swgrp = 1; + hdl->swgrp_bitmap[0].en_upd_ul_swgrp = 0; + hdl->swgrp_bitmap[0].dl_sw_grp_bitmap = 92; + hdl->swgrp_bitmap[0].ul_sw_grp_bitmap = 5; + hdl->swgrp_bitmap[0].cmdend = 0; + + hdl->swgrp_bitmap[1].macid = 7; + hdl->swgrp_bitmap[1].en_upd_dl_swgrp = 0; + hdl->swgrp_bitmap[1].en_upd_ul_swgrp = 1; + hdl->swgrp_bitmap[1].dl_sw_grp_bitmap = 99; + hdl->swgrp_bitmap[1].ul_sw_grp_bitmap = 58; + hdl->swgrp_bitmap[1].cmdend = 1; +} + +void halbb_test_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg) +{ + cfg->macid = 5; + cfg->dl_su_rate_cfg = 1; + cfg->dl_su_rate = 3; + cfg->dl_su_bw = 2; + cfg->dl_su_pwr_cfg = 1; + cfg->dl_su_pwr = 15; + cfg->gi_ltf_4x8_support = 1; + cfg->gi_ltf_1x8_support = 0; + cfg->dl_su_info_en = 1; + cfg->dl_su_gi_ltf = 3; + cfg->dl_su_doppler_ctrl = 2; + cfg->dl_su_coding = 1; + cfg->dl_su_txbf = 0; + cfg->dl_su_stbc = 0; + cfg->dl_su_dcm = 0; +} + +void halbb_test_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg) +{ + cfg->ul_macid_cfg[0].macid = 5; + cfg->ul_macid_cfg[0].endcmd = 0; + + cfg->ul_macid_cfg[0].ul_su_info_en = 1; + cfg->ul_macid_cfg[0].ul_su_bw = 0; + cfg->ul_macid_cfg[0].ul_su_gi_ltf = 1; + cfg->ul_macid_cfg[0].ul_su_doppler_ctrl = 0; + cfg->ul_macid_cfg[0].ul_su_dcm = 1; + cfg->ul_macid_cfg[0].ul_su_ss = 2; + cfg->ul_macid_cfg[0].ul_su_mcs = 7; + + cfg->ul_macid_cfg[0].ul_su_stbc = 0; + cfg->ul_macid_cfg[0].ul_su_coding = 1; + cfg->ul_macid_cfg[0].ul_su_rssi_m = 100; + + cfg->ul_macid_cfg[1].macid = 3; + cfg->ul_macid_cfg[1].endcmd = 0; + + cfg->ul_macid_cfg[1].ul_su_info_en = 1; + cfg->ul_macid_cfg[1].ul_su_bw = 0; + cfg->ul_macid_cfg[1].ul_su_gi_ltf = 2; + cfg->ul_macid_cfg[1].ul_su_doppler_ctrl = 0; + cfg->ul_macid_cfg[1].ul_su_dcm = 1; + cfg->ul_macid_cfg[1].ul_su_ss = 2; + cfg->ul_macid_cfg[1].ul_su_mcs = 8; + + cfg->ul_macid_cfg[1].ul_su_stbc = 0; + cfg->ul_macid_cfg[1].ul_su_coding = 1; + cfg->ul_macid_cfg[1].ul_su_rssi_m = 101; + + cfg->ul_macid_cfg[2].macid = 6; + cfg->ul_macid_cfg[2].endcmd = 1; + + cfg->ul_macid_cfg[2].ul_su_info_en = 1; + cfg->ul_macid_cfg[2].ul_su_bw = 0; + cfg->ul_macid_cfg[2].ul_su_gi_ltf = 3; + cfg->ul_macid_cfg[2].ul_su_doppler_ctrl = 0; + cfg->ul_macid_cfg[2].ul_su_dcm = 1; + cfg->ul_macid_cfg[2].ul_su_ss = 2; + cfg->ul_macid_cfg[2].ul_su_mcs = 9; + + cfg->ul_macid_cfg[2].ul_su_stbc = 0; + cfg->ul_macid_cfg[2].ul_su_coding = 1; + cfg->ul_macid_cfg[2].ul_su_rssi_m = 102; + + +} + + +void halbb_test_sta_modify(struct bb_info *bb, struct rtw_dlru_fixtbl_ax4ru *fix_tbl, u8 mcs, u8 ss) +{ + fix_tbl->max_sta_num = 2; + fix_tbl->min_sta_num = 2; + fix_tbl->doppler=0; + fix_tbl->stbc=0; + fix_tbl->gi_ltf=0; + fix_tbl->ma_type=0; + fix_tbl->fixru_flag = true; + fix_tbl->sta[0].mac_id=2; + fix_tbl->sta[0].ru_pos[0]=130; + fix_tbl->sta[0].ru_pos[1]=122; + fix_tbl->sta[0].ru_pos[2]=122; + fix_tbl->sta[0].fix_rate=1; + fix_tbl->sta[0].rate.mcs=mcs; + fix_tbl->sta[0].rate.ss=ss; + fix_tbl->sta[0].rate.dcm=0; + fix_tbl->sta[0].fix_coding=1; + fix_tbl->sta[0].coding=1; + fix_tbl->sta[0].fix_txbf=1; + fix_tbl->sta[0].txbf=0; + fix_tbl->sta[0].fix_pwr_fac=1; + fix_tbl->sta[0].pwr_boost_fac=0; + + fix_tbl->sta[1].mac_id=3; + fix_tbl->sta[1].ru_pos[0]=132; + fix_tbl->sta[1].ru_pos[1]=124; + fix_tbl->sta[1].ru_pos[2]=124; + fix_tbl->sta[1].fix_rate=1; + fix_tbl->sta[1].rate.mcs=mcs; + fix_tbl->sta[1].rate.ss=ss; + fix_tbl->sta[1].rate.dcm=0; + fix_tbl->sta[1].fix_coding=1; + fix_tbl->sta[1].coding=1; + fix_tbl->sta[1].fix_txbf=1; + fix_tbl->sta[1].txbf=0; + fix_tbl->sta[1].fix_pwr_fac=1; + fix_tbl->sta[1].pwr_boost_fac=0; + + fix_tbl->sta[2].mac_id=4; + fix_tbl->sta[2].ru_pos[0]=0; + fix_tbl->sta[2].ru_pos[1]=126; + fix_tbl->sta[2].ru_pos[2]=126; + fix_tbl->sta[2].fix_rate=1; + fix_tbl->sta[2].rate.mcs=mcs; + fix_tbl->sta[2].rate.ss=ss; + fix_tbl->sta[2].rate.dcm=0; + fix_tbl->sta[2].fix_coding=1; + fix_tbl->sta[2].coding=1; + fix_tbl->sta[2].fix_txbf=1; + fix_tbl->sta[2].txbf=0; + fix_tbl->sta[2].fix_pwr_fac=1; + fix_tbl->sta[2].pwr_boost_fac=0; + + fix_tbl->sta[3].mac_id=5; + fix_tbl->sta[3].ru_pos[0]=0; + fix_tbl->sta[3].ru_pos[1]=0; + fix_tbl->sta[3].ru_pos[2]=128; + fix_tbl->sta[3].fix_rate=1; + fix_tbl->sta[3].rate.mcs=mcs; + fix_tbl->sta[3].rate.ss=ss; + fix_tbl->sta[3].rate.dcm=0; + fix_tbl->sta[3].fix_coding=1; + fix_tbl->sta[3].coding=1; + fix_tbl->sta[3].fix_txbf=1; + fix_tbl->sta[3].txbf=0; + fix_tbl->sta[3].fix_pwr_fac=1; + fix_tbl->sta[3].pwr_boost_fac=0; +} + +void halbb_test_grppwr_modify(struct bb_info *bb, struct rtw_dl_ru_gp_tbl *tbl, u8 grp_pwr) +{ + tbl->ppdu_bw = CHANNEL_WIDTH_80; + tbl->tx_pwr = grp_pwr; /*TODO:get from bb api*/ + tbl->pwr_boost_fac = 0;/*TODO:get from bb api*/ + tbl->fix_mode_flag = 1; + + /* Trigger BA settings */ + tbl->tf.tf_rate = RTW_DATA_RATE_OFDM24; + tbl->tf.tb_ppdu_bw = CHANNEL_WIDTH_80; + tbl->tf.rate.dcm = 0; + tbl->tf.rate.mcs = 3; + tbl->tf.rate.ss = 0; + tbl->tf.fix_ba = 0; + tbl->tf.ru_psd = 20;/*TODO:get from bb api*/ + tbl->tf.rf_gain_fix = 0;/*TODO:get from bb api*/ + tbl->tf.rf_gain_idx = 0;/*TODO:get from bb api*/ + tbl->tf.gi_ltf = RTW_GILTF_2XHE16; + tbl->tf.doppler = 0; + tbl->tf.stbc = 0; + tbl->tf.sta_coding = 0; + tbl->tf.tb_t_pe_nom = 2; + tbl->tf.pr20_bw_en = 0; + tbl->tf.ma_type = 0; +} + +void halbb_test_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg) +{ + cfg->macid = 5; + cfg->csi_info_bitmap= 99; +} + + +void halbb_test_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg) +{ + u8 i; + + cfg->cqi_info[0].macid = 5; + cfg->cqi_info[0].fw_cqi_flag= 1; + cfg->cqi_info[0].ru_rate_table_row_idx= 4; + cfg->cqi_info[0].ul_dl= 0; + cfg->cqi_info[0].endcmd= 0; + + for (i=10;i<29;i++) + cfg->cqi_info[0].cqi_diff_table[i-10]= i; + + + + cfg->cqi_info[1].macid = 3; + cfg->cqi_info[1].fw_cqi_flag= 1; + cfg->cqi_info[1].ru_rate_table_row_idx= 2; + cfg->cqi_info[1].ul_dl= 1; + cfg->cqi_info[1].endcmd= 0; + + for (i=20;i<39;i++) + cfg->cqi_info[1].cqi_diff_table[i-20]= i; + + + + cfg->cqi_info[2].macid = 1; + cfg->cqi_info[2].fw_cqi_flag= 1; + cfg->cqi_info[2].ru_rate_table_row_idx= 0; + cfg->cqi_info[2].ul_dl= 0; + cfg->cqi_info[2].endcmd= 0; + + for (i=30;i<49;i++) + cfg->cqi_info[2].cqi_diff_table[i-30]= i-40; + + + + cfg->cqi_info[3].macid = 7; + cfg->cqi_info[3].fw_cqi_flag= 1; + cfg->cqi_info[3].ru_rate_table_row_idx= 6; + cfg->cqi_info[3].ul_dl= 0; + cfg->cqi_info[3].endcmd= 1; + + for (i=40;i<59;i++) + cfg->cqi_info[3].cqi_diff_table[i-40]= i-60; + + + +} + +void halbb_test_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg) +{ + cfg->p20_ch_bitmap= 168; +} + +void halbb_test_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg) +{ u8 i; + + for (i=0;i<32;i++) + cfg->pwr_by_rt[i]= -200 + i*10; +} + + +u32 halbb_set_rua_tbl(struct bb_info *bb, u8 rua_tbl_idx) +{ + + u32 ret = 0; + struct rtw_dl_ru_gp_tbl dl_ru_gp_t = {{0}}; + struct rtw_ul_ru_gp_tbl ul_ru_gp_t = {{0}}; + struct rtw_ru_sta_info ru_sta_i = {{0}}; + struct rtw_dlru_fixtbl_ax4ru dl_ru_fix_t = {{0}}; + struct rtw_ulru_fixtbl_ax4ru ul_ru_fix_t = {{0}}; + struct rtw_ba_tbl_info ba_tbl_i = {{0}}; + + BB_DBG(bb, DBG_RUA_TBL, "SET RUA TBL (%d)\n", rua_tbl_idx); + switch(rua_tbl_idx) { + case DL_RU_GP_TBL: + halbb_test_dlru_gp_tbl(bb, &dl_ru_gp_t); + halbb_upd_dlru_grptbl(bb, &dl_ru_gp_t); + break; + case UL_RU_GP_TBL: + halbb_test_ulru_gp_tbl(bb, &ul_ru_gp_t); + halbb_upd_ulru_grptbl(bb, &ul_ru_gp_t); + break; + case RU_STA_INFO: + halbb_test_ru_sta_info(bb, &ru_sta_i); + halbb_upd_rusta_info(bb, &ru_sta_i); + break; + case DL_RU_FIX_TBL: + halbb_test_dl_fix_tbl(bb, &dl_ru_fix_t); + halbb_upd_dlru_fixtbl_ax4ru(bb, &dl_ru_fix_t);//shall be revised + break; + case UL_RU_FIX_TBL: + halbb_test_ul_fix_tbl(bb, &ul_ru_fix_t); + halbb_upd_ulru_fixtbl_ax4ru(bb, &ul_ru_fix_t);//shall be revised + break; + case BA_INFO_TBL: + halbb_test_ba_tbl(bb, &ba_tbl_i); + halbb_upd_ba_infotbl(bb, &ba_tbl_i); + break; + default: + break; + } + return ret; +} + +u32 halbb_set_rua_cfg(struct bb_info *bb, u8 rua_cfg_idx) +{ + + u32 ret = 0; + struct rtw_sw_grp_set swgrp_hdl; + struct rtw_dl_macid_cfg dlmacid_cfg; + struct rtw_ul_macid_set ulmacid_cfg; + struct rtw_csiinfo_cfg csiinfo_cfg; + struct rtw_cqi_set cqi_info; + struct rtw_bbinfo_cfg bbinfo_cfg; + struct rtw_pwr_by_rt_tbl pbr_tbl; + + halbb_mem_set(bb, &swgrp_hdl, 0, sizeof(swgrp_hdl)); + halbb_mem_set(bb, &dlmacid_cfg, 0, sizeof(dlmacid_cfg)); + halbb_mem_set(bb, &ulmacid_cfg, 0, sizeof(ulmacid_cfg)); + halbb_mem_set(bb, &csiinfo_cfg, 0, sizeof(csiinfo_cfg)); + halbb_mem_set(bb, &cqi_info, 0, sizeof(cqi_info)); + halbb_mem_set(bb, &bbinfo_cfg, 0, sizeof(bbinfo_cfg)); + halbb_mem_set(bb, &pbr_tbl, 0, sizeof(pbr_tbl)); + + BB_DBG(bb, DBG_RUA_TBL, "SET RUA TBL (%d)\n", rua_cfg_idx); + switch(rua_cfg_idx) { + case SW_GRP_HDL: + halbb_test_swgrp_hdl(bb, &swgrp_hdl); + halbb_swgrp_hdl(bb, &swgrp_hdl); + break; + case DL_MACID_CFG: + halbb_test_dlmacid_cfg(bb, &dlmacid_cfg); + halbb_dlmacid_cfg(bb, &dlmacid_cfg); + break; + + case UL_MACID_CFG: + halbb_test_ulmacid_cfg(bb, &ulmacid_cfg); + halbb_ulmacid_cfg(bb, &ulmacid_cfg); + + break; + case CSI_INFO_CFG: + halbb_test_csiinfo_cfg(bb, &csiinfo_cfg); + halbb_csiinfo_cfg(bb, &csiinfo_cfg); + break; + case CQI_CFG: + halbb_test_cqi_cfg(bb, &cqi_info); + halbb_cqi_cfg(bb, &cqi_info); + break; + case BB_INFO_CFG: + halbb_test_bbinfo_cfg(bb, &bbinfo_cfg); + halbb_bbinfo_cfg(bb, &bbinfo_cfg); + break; + case PWR_TBL_init: + halbb_test_pbr_tbl_cfg(bb, &pbr_tbl); + halbb_pbr_tbl_cfg(bb, &pbr_tbl); + break; + default: + break; + } + return ret; +} + +u32 halbb_set_rua_sta_rate_ss(struct bb_info *bb, u8 hdr_type, u8 ent, u8 mcs, u8 ss) +{ + + u32 ret = 0; + //struct rtw_dlru_fixtbl_ax4ru dl_ru_fix_t; + union rtw_dlru_fixtbl dl_ru_fix_t; + halbb_mem_set(bb, &dl_ru_fix_t,0,sizeof(dl_ru_fix_t)); + + BB_DBG(bb, DBG_RUA_TBL, "SET DL FIX RUA TBL with sta_info change\n"); + BB_DBG(bb, DBG_RUA_TBL, "hdr_type: %d, ent: %d, mcs: %d ,ss: %d\n", hdr_type, ent, mcs, ss); + + dl_ru_fix_t.ax4ru.tbl_hdr.rw = 1; /* write */ + dl_ru_fix_t.ax4ru.tbl_hdr.idx = ent; + dl_ru_fix_t.ax4ru.tbl_hdr.offset = 0; + dl_ru_fix_t.ax4ru.tbl_hdr.len = sizeof(struct rtw_dlru_fixtbl_ax4ru); + dl_ru_fix_t.ax4ru.tbl_hdr.type = hdr_type; + + halbb_test_sta_modify(bb, &dl_ru_fix_t.ax4ru, mcs, ss); + + ret = halbb_upd_dlru_fixtbl(bb, &dl_ru_fix_t); + + + return ret; +} + + +u32 halbb_set_rua_grp_pwr(struct bb_info *bb, u8 hdr_type, u8 ent, u8 grp_pwr) +{ + + u32 ret = 0; + struct rtw_dl_ru_gp_tbl dl_ru_gp_t = {0}; + + BB_DBG(bb, DBG_RUA_TBL, "SET DL GRP RUA TBL with grp_pwr change\n"); + BB_DBG(bb, DBG_RUA_TBL, "hdr_type: %d, ent: %d, grp_pwr: %d\n", hdr_type, ent, grp_pwr); + + dl_ru_gp_t.tbl_hdr.rw = 1; /* write */ + dl_ru_gp_t.tbl_hdr.idx = ent; + dl_ru_gp_t.tbl_hdr.offset = 0; + dl_ru_gp_t.tbl_hdr.len = sizeof(struct rtw_dl_ru_gp_tbl); + dl_ru_gp_t.tbl_hdr.type = hdr_type; + + halbb_test_grppwr_modify(bb, &dl_ru_gp_t, grp_pwr); + + ret = halbb_upd_dlru_grptbl(bb, &dl_ru_gp_t); + + return ret; +} + + +void halbb_rua_tbl_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char help[] = "-h"; + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if (_os_strcmp(input[1], help) == 0) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (0 [dlru_grptbl])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (1 [ulru_grptbl])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (2 [rusta_info])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (3 [dlru_fixtbl])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (4 [ulru_fixtbl])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (5 [ba_infotbl])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 0 [SW_GRP_HDL])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 1 [DL_MACID_CFG])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 2 [UL_MACID_CFG])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 3 [CSI_INFO_CFG])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 4 [CQI_CFG])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 5 [BB_INFO_CFG])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (6 6 [PWR_TBL_init])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (7 1:hw,0:sw ent mcs ss [dlru_fixtbl with sta_info change])}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rua (8 1:hw,0:sw ent grp_pwr [dlru_fixtbl with grp_pwr change])}\n"); + goto out; + } + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + if (val[0] < 6) + halbb_set_rua_tbl(bb, (u8)val[0]); + else if(val[0] == 6 ) + halbb_set_rua_cfg(bb, (u8)val[1]); + else if(val[0] == 7 ) + halbb_set_rua_sta_rate_ss(bb, (u8)val[1],(u8)val[2],(u8)val[3],(u8)val[4]); + else + halbb_set_rua_grp_pwr(bb, (u8)val[1],(u8)val[2],(u8)val[3]); + +out: + *_used = used; + *_out_len = out_len; +} +#endif /* HALBB_RUA_SUPPORT */ diff --git a/phl/hal_g6/phy/bb/halbb_rua_tbl.h b/phl/hal_g6/phy/bb/halbb_rua_tbl.h new file mode 100644 index 0000000..63f45d3 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_rua_tbl.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_RUA_TBL_H__ +#define __HALBB_RUA_TBL_H__ + +#ifdef HALBB_RUA_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ +/*[IO Reg]*/ + + +/*@--------------------------[Enum]------------------------------------------*/ + +enum rua_tbl_sel { + DL_RU_GP_TBL = 0x0, + UL_RU_GP_TBL = 0x1, + RU_STA_INFO = 0x2, + DL_RU_FIX_TBL = 0x3, + UL_RU_FIX_TBL = 0x4, + BA_INFO_TBL = 0x5 +}; + +enum rua_cfg_sel { + SW_GRP_HDL = 0x0, + DL_MACID_CFG = 0x1, + UL_MACID_CFG = 0x2, + CSI_INFO_CFG = 0x3, + CQI_CFG = 0x4, + BB_INFO_CFG = 0x5, + PWR_TBL_init = 0x6 +}; + + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +void halbb_rua_tbl_init(struct bb_info *bb); +void halbb_rua_tbl_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif /* HALBB_RUA_SUPPORT */ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_rua_tbl_b_endian.h b/phl/hal_g6/phy/bb/halbb_rua_tbl_b_endian.h new file mode 100644 index 0000000..d422c90 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_rua_tbl_b_endian.h @@ -0,0 +1,408 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_RUA_TBL_B_ENDIAN_H__ +#define __HALBB_RUA_TBL_B_ENDIAN_H__ + +#ifdef HALBB_RUA_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ +/*[IO Reg]*/ + +/*@--------------------------[Enum]------------------------------------------*/ + + + +/*@--------------------------[Structure]-------------------------------------*/ + + +struct halbb_rua_tbl_hdr_info { + u8 idx:7; + u8 rw:1; + + u8 len_l:3; + u8 offset:5; + + u8 type:1; + u8 len_m:7; + + u8 tbl_class; +}; + +struct halbb_ru_rate_info { + u8 mcs:4; + u8 ss:3; + u8 dcm:1; +}; + + + +struct halbb_tf_ba_tbl_info { + u8 ru_psd_l:7; + u8 fix_ba:1; + + u8 tf_rate_l:6; + u8 ru_psd_m:2; + + u8 rf_gain_idx_l:4; + u8 rf_gain_fix:1; + u8 tf_rate_m:3; + + u8 tb_ppdu_bw:2; + u8 rf_gain_idx_m:6; + + struct halbb_ru_rate_info rate_i; + + u8 tb_t_pe_nom:2; + u8 sta_coding:1; + u8 stbc:1; + u8 doppler:1; + u8 gi_ltf:3; + + u8 rsvd1: 6; + u8 ma_type: 1; + u8 pr20_bw_en:1; + +}; + +struct halbb_dl_ru_gp_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + + u8 tx_pwr_l:6; + u8 ppdu_bw:2; + + u8 pwr_boost_fac:5; + u8 tx_pwr_m:3; + + u8 rsvd1:7; + u8 fix_mode_flag:1; + + u8 rsvd2; + + struct halbb_tf_ba_tbl_info tf; +}; + + + +struct halbb_ul_ru_gp_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 grp_psd_max_l; + + u8 grp_psd_min_l:7; + u8 grp_psd_max_m:1; + + u8 tf_rate_l:6; + u8 grp_psd_min_m:2; + + u8 rsvd2:4; + u8 fix_tf_rate:1; + u8 tf_rate_m:3; + + u8 rf_gain_idx_l:5; + u8 rf_gain_fix:1; + u8 ppdu_bw:2; + + u8 rsvd1: 2; + u8 fix_mode_flag: 1; + u8 rf_gain_idx_m:5; + +}; + +struct halbb_ru_sta_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; +/* sta capability */ + u8 rsvd0:6; + u8 gi_ltf_18spt:1; + u8 gi_ltf_48spt:1; + +/* dl su */ + u8 dlsu_doppler_ctrl:2; + u8 dlsu_gi_ltf:3; + u8 dlsu_bw:2; + u8 dlsu_info_en:1; + + u8 dlru_ratetbl_ridx:4; + u8 dl_fwcqi_flag:1; + u8 dlsu_stbc:1; + u8 dlsu_txbf:1; + u8 dlsu_coding:1; + + u8 csi_info_bitmap; + + u8 dl_swgrp_bitmap[4]; + + u8 dlsu_rate_l:1; + u8 rsvd1:6; + u8 dlsu_dcm:1; + + u8 dlsu_rate_m; + + u8 rsvd2:2; + u8 dlsu_pwr:6; + + u8 rsvd4; +/* ul su */ + u8 ulsu_doppler_ctrl:2; + u8 ulsu_gi_ltf:3; + u8 ulsu_bw:2; + u8 ulsu_info_en:1; + + u8 ulsu_mcs:4; + u8 ulsu_ss:3; + u8 ulsu_dcm:1; + + u8 ulsu_rssi_m_l:1; + u8 ulsu_coding:1; + u8 ulsu_stbc:1; + u8 ulru_ratetbl_ridx:4; + u8 ul_fwcqi_flag:1; + + u8 ulsu_rssi_m_m; + + u8 ul_swgrp_bitmap[4]; +/* tb info */ +}; + +struct halbb_dl_fix_sta_info { + u8 mac_id; + u8 ru_pos[3]; + + u8 rsvd0: 4; + u8 fix_pwr_fac:1; + u8 fix_txbf:1; + u8 fix_coding:1; + u8 fix_rate:1; + + struct halbb_ru_rate_info rate_i; + + u8 rsvd1: 1; + u8 pwr_boost_fac:5; + u8 coding:1; + u8 txbf:1; + u8 rsvd2; +}; + +struct halbb_dl_ru_fix_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 rsvd0:1; + u8 ru_swp_flg:1; + u8 min_sta_num:3; + u8 max_sta_num:3; + + u8 rupos_csht_flag:1; + u8 fixru_flag:1; + u8 ma_type:1; + u8 gi_ltf:3; + u8 stbc:1; + u8 doppler:1; + + u8 rsvd2; + u8 rsvd3; + struct halbb_dl_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM]; + +}; + +struct halbb_ul_fix_sta_info { + u8 mac_id; + u8 ru_pos[3]; + u8 tgt_rssi[3]; + u8 rsvd1: 4; + u8 coding: 1; + u8 fix_coding: 1; + u8 fix_rate: 1; + u8 fix_tgt_rssi: 1; + struct halbb_ru_rate_info rate_i; +}; + + +struct halbb_ul_ru_fix_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 ma_type:1; + u8 doppler:1; + u8 min_sta_num:3; + u8 max_sta_num:3; + u8 fixru_flag: 1; + u8 tb_t_pe_nom: 2; + u8 fix_tb_t_pe_nom: 1; + u8 stbc:1; + u8 gi_ltf:3; + + struct halbb_ul_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM]; + +}; + +struct halbb_rua_tbl { + struct halbb_dl_ru_gp_tbl_info dl_ru_gp_tbl_i; + struct halbb_ul_ru_gp_tbl_info ul_ru_gp_tbl_i; + struct halbb_ru_sta_info ru_sta_i; + struct halbb_dl_ru_fix_tbl_info dl_ru_fix_tbl_i; + struct halbb_ul_ru_fix_tbl_info ul_ru_fix_tbl_i; + struct halbb_tf_ba_tbl_info tf_ba_tbl_i; +}; + +struct halbb_sw_grp_bitmap { + u8 macid; + + u8 rsvd1:5; + u8 cmdend:1; // add for determine whether last user or not + u8 en_upd_ul_swgrp:1; + u8 en_upd_dl_swgrp:1; + + u8 rsvd2; + u8 rsvd3; + + u8 dl_sw_grp_bitmap[4]; + u8 ul_sw_grp_bitmap[4]; +}; + +struct halbb_sw_grp_set { + + struct halbb_sw_grp_bitmap swgrp_bitmap[8]; + +}; + +struct dl_macid_cfg { + u8 macid; + + u8 dl_su_rate_l:7; + u8 dl_su_rate_cfg:1; + + u8 dl_su_pwr_l:3; + u8 dl_su_pwr_cfg:1; + u8 dl_su_bw:2; + u8 dl_su_rate_m:2; + + u8 rsvd0:5; + u8 dl_su_pwr_m:3; + + u8 rsvd1:6; + u8 gi_ltf_1x8_support:1; + u8 gi_ltf_4x8_support:1; + + u8 dl_su_doppler_ctrl:2; + u8 dl_su_gi_ltf:3; + u8 rsvd2:2; + u8 dl_su_info_en:1; + + u8 rsvd3:4; + u8 dl_su_dcm:1; + u8 dl_su_stbc:1; + u8 dl_su_txbf:1; + u8 dl_su_coding:1; + + u8 rsvd4; +}; + +struct halbb_ul_macid_cfg { + + u8 macid; + + u8 rsvd0: 7; + u8 endcmd: 1; + + u8 rsvd1; + u8 rsvd2; + + u8 ul_su_doppler_ctrl: 2; + u8 ul_su_gi_ltf: 3; + u8 ul_su_bw: 2; + u8 ul_su_info_en: 1; + + u8 ul_su_mcs: 4; + u8 ul_su_ss: 3; + u8 ul_su_dcm: 1; + + u8 ul_su_rssi_m_l: 1; + u8 ul_su_coding: 1; + u8 ul_su_stbc: 1; + u8 rsvd3: 5; + + u8 ul_su_rssi_m_m; + +}; + +struct halbb_ul_macid_set { + + struct halbb_ul_macid_cfg ul_macid_cfg[8]; + +}; + + + +struct halbb_ba_tbl_info { + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + + struct halbb_tf_ba_tbl_info tf_i; +}; + +struct csiinfo_cfg{ + u8 macid; + u8 csi_info_bitmap; + + u8 rsvd0; + u8 rsvd1; +}; + +struct halbb_cqi_info { + u8 macid; + + u8 rsvd0: 1; + u8 endcmd: 1; + u8 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */ + u8 ru_rate_table_row_idx: 4; /* UL or DL*/ + u8 fw_cqi_flag: 1; /* UL or DL*/ + + u8 rsvd1; + u8 rsvd2; + + s8 cqi_diff_table[19]; /* UL or DL*/ + u8 rsvd3; +}; + +struct halbb_cqi_set{ + struct halbb_cqi_info cqi_info[8]; +}; + +struct halbb_bb_info_cfg { + u8 p20_ch_bitmap; + + u8 rsvd0; + u8 rsvd1; + u8 rsvd2; +}; + +struct halbb_pwr_by_rt_tbl{ + u8 pwr_by_rt[64]; +}; + + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif /* HALBB_RUA_SUPPORT */ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_rua_tbl_ex.h b/phl/hal_g6/phy/bb/halbb_rua_tbl_ex.h new file mode 100644 index 0000000..73ab7c5 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_rua_tbl_ex.h @@ -0,0 +1,459 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_RUA_TBL_EX_H__ +#define __HALBB_RUA_TBL_EX_H__ +#ifdef HALBB_RUA_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ +#define HALBB_AX4RU_STA_NUM 4 +#define HALBB_AX8RU_STA_NUM 8 +/*@--------------------------[Enum]------------------------------------------*/ +enum rtw_rua_tbl_hdr_rw { + RUA_TBL_RW_READ = 0, + RUA_TBL_RW_WRITE = 1 +}; +enum rtw_rua_tbl_hdr_type { + RUA_TBL_TYPE_SW = 0, + RUA_TBL_TYPE_HW = 1 +}; +enum rtw_rua_tbl_hdr_class { + RUA_TBL_CL_DLRU_SW = 0x0, + RUA_TBL_CL_ULRU_SW = 0x1, + RUA_TBL_CL_RU_STA = 0x2, + RUA_TBL_CL_DLRU_SW_FIX = 0x3, + RUA_TBL_CL_ULRU_SW_FIX = 0x4, + RUA_TBL_CL_BA_INFO = 0x5 +}; +/*@--------------------------[Structure]-------------------------------------*/ + struct rtw_rua_tbl_hdr { + u8 rw:1; + u8 idx:7; + + u16 offset:5; + u16 len:10; + u16 type:1; + + u8 tbl_class; +}; + +struct rtw_ru_rate_ent { + u8 dcm:1; + u8 ss:3; + u8 mcs:4; +}; + +struct rtw_tf_ba_tbl { + u32 fix_ba:1; + u32 ru_psd:9; + u32 tf_rate:9; + u32 rf_gain_fix:1; + u32 rf_gain_idx:10; + u32 tb_ppdu_bw:2; + + struct rtw_ru_rate_ent rate; + + u8 gi_ltf:3; + u8 doppler:1; + u8 stbc:1; + u8 sta_coding:1; + u8 tb_t_pe_nom:2; + + u8 pr20_bw_en:1; + u8 ma_type:1; + u8 rsvd1:6; + + u8 rsvd2; +}; + +struct rtw_dl_ru_gp_tbl { + + struct rtw_rua_tbl_hdr tbl_hdr; + + u16 ppdu_bw:2; + u16 tx_pwr:9; + u16 pwr_boost_fac:5; + + u8 fix_mode_flag:1; + u8 rsvd1:7; + + u8 rsvd2; + + struct rtw_tf_ba_tbl tf; +}; + +struct rtw_ul_ru_gp_tbl { + + struct rtw_rua_tbl_hdr tbl_hdr; + u32 grp_psd_max:9; + u32 grp_psd_min:9; + u32 tf_rate:9; + u32 fix_tf_rate:1; + u32 rsvd2:4; + + u16 ppdu_bw:2; + u16 rf_gain_fix:1; + u16 rf_gain_idx:10; + u16 fix_mode_flag:1; + u16 rsvd1:2; +}; + +struct rtw_ru_sta_info { + + struct rtw_rua_tbl_hdr tbl_hdr; +/* sta capability */ + u8 gi_ltf_48spt:1; + u8 gi_ltf_18spt:1; + u8 rsvd0:6; +/* dl su */ + u8 dlsu_info_en:1; + u8 dlsu_bw:2; + u8 dlsu_gi_ltf:3; + u8 dlsu_doppler_ctrl:2; + + u8 dlsu_coding:1; + u8 dlsu_txbf:1; + u8 dlsu_stbc:1; + u8 dl_fwcqi_flag:1; + u8 dlru_ratetbl_ridx:4; + u8 csi_info_bitmap; + u32 dl_swgrp_bitmap; + + u16 dlsu_dcm:1; + u16 rsvd1:6; + u16 dlsu_rate:9; + u8 dlsu_pwr:6; + u8 rsvd2:2; + u8 rsvd4; +/* ul su */ + u8 ulsu_info_en:1; + u8 ulsu_bw:2; + u8 ulsu_gi_ltf:3; + u8 ulsu_doppler_ctrl:2; + u8 ulsu_dcm:1; + u8 ulsu_ss:3; + u8 ulsu_mcs:4; + u16 ul_fwcqi_flag:1; + u16 ulru_ratetbl_ridx:4; + u16 ulsu_stbc:1; + u16 ulsu_coding:1; + u16 ulsu_rssi_m:9; + u32 ul_swgrp_bitmap; +/* tb info */ +}; + +/* +struct rtw_dl_fix_sta_ent { + u8 mac_id; + u8 ru_pos[3]; + + u8 fix_rate:1; + u8 fix_coding:1; + u8 fix_txbf:1; + u8 fix_pwr_fac:1; + u8 rsvd0:4; + + struct rtw_ru_rate_ent rate; + + u8 txbf:1; + u8 coding:1; + u8 pwr_boost_fac:5; + u8 rsvd1: 1; + u8 rsvd2; + +}; + +struct rtw_dl_ru_fix_tbl { + + struct rtw_rua_tbl_hdr tbl_hdr; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 ru_swp_flg:1; + u8 rsvd0:1; + + u8 doppler:1; + u8 stbc:1; + u8 gi_ltf:3; + u8 ma_type:1; + u8 fixru_flag:1; + u8 rupos_csht_flag:1; + + u8 rsvd2; + + struct rtw_dl_fix_sta_ent sta[HALBB_AX4RU_STA_NUM]; + +}; +*/ + +struct rtw_dlfix_sta_i_ax4ru { + u8 mac_id; + u8 ru_pos[3]; + + u8 fix_rate:1; + u8 fix_coding:1; + u8 fix_txbf:1; + u8 fix_pwr_fac:1; + u8 rsvd0:4; + + struct rtw_ru_rate_ent rate; + + u8 txbf:1; + u8 coding:1; + u8 pwr_boost_fac:5; + u8 rsvd1: 1; + u8 rsvd2; + +}; + +struct rtw_dlru_fixtbl_ax4ru { + + struct rtw_rua_tbl_hdr tbl_hdr; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 ru_swp_flg:1; + u8 rsvd0:1; + + u8 doppler:1; + u8 stbc:1; + u8 gi_ltf:3; + u8 ma_type:1; + u8 fixru_flag:1; + u8 rupos_csht_flag:1; + + u8 rsvd2; + + struct rtw_dlfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM]; +}; + +union rtw_dlru_fixtbl{ + struct rtw_dlru_fixtbl_ax4ru ax4ru; +}; + +/* +struct rtw_ul_fix_sta_ent { + u8 mac_id; + u8 ru_pos[3]; + u8 tgt_rssi[3]; + u8 fix_tgt_rssi:1; + u8 fix_rate:1; + u8 fix_coding:1; + u8 coding:1; + u8 rsvd1:4; + struct rtw_ru_rate_ent rate; +}; + +struct rtw_ul_ru_fix_tbl { + + struct rtw_rua_tbl_hdr tbl_hdr; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 doppler:1; + u8 ma_type:1; + u8 gi_ltf:3; + u8 stbc:1; + u8 fix_tb_t_pe_nom: 1; + u8 tb_t_pe_nom: 2; + u8 fixru_flag: 1; + struct rtw_ul_fix_sta_ent sta[HALBB_AX4RU_STA_NUM]; + +}; +*/ + +struct rtw_ulfix_sta_i_ax4ru { + u8 mac_id; + u8 ru_pos[3]; + u8 tgt_rssi[3]; + u8 fix_tgt_rssi:1; + u8 fix_rate:1; + u8 fix_coding:1; + u8 coding:1; + u8 rsvd1:4; + struct rtw_ru_rate_ent rate; +}; + +struct rtw_ulru_fixtbl_ax4ru { + + struct rtw_rua_tbl_hdr tbl_hdr; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 doppler:1; + u8 ma_type:1; + u8 gi_ltf:3; + u8 stbc:1; + u8 fix_tb_t_pe_nom: 1; + u8 tb_t_pe_nom: 2; + u8 fixru_flag: 1; + struct rtw_ulfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM]; + +}; + +union rtw_ulru_fixtbl{ + struct rtw_ulru_fixtbl_ax4ru ax4ru; +}; + +struct rtw_ba_tbl_info { + struct rtw_rua_tbl_hdr tbl_hdr; + + struct rtw_tf_ba_tbl tf_ba_t; +}; + +struct rtw_sw_grp_bitmap { + u8 macid; + + u8 en_upd_dl_swgrp:1; + u8 en_upd_ul_swgrp:1; + u8 cmdend:1; // add for determine whether last user or not + u8 rsvd1:5; + + u32 dl_sw_grp_bitmap; + u32 ul_sw_grp_bitmap; +}; + +struct rtw_sw_grp_set { + + struct rtw_sw_grp_bitmap swgrp_bitmap[8]; + +}; + +struct rtw_dl_macid_cfg { + + u32 macid: 8; + u32 dl_su_rate_cfg: 1; + u32 dl_su_rate: 9; + u32 dl_su_bw: 2; + u32 dl_su_pwr_cfg: 1; + u32 dl_su_pwr: 6; + u32 rsvd0: 5; + + u32 gi_ltf_4x8_support: 1; + u32 gi_ltf_1x8_support: 1; + u32 rsvd1: 6; + u32 dl_su_info_en: 1; + u32 rsvd2: 2; + u32 dl_su_gi_ltf: 3; + u32 dl_su_doppler_ctrl: 2; + u32 dl_su_coding: 1; + u32 dl_su_txbf: 1; + u32 dl_su_stbc: 1; + u32 dl_su_dcm: 1; + u32 rsvd3: 12; + +}; + + +struct rtw_ul_macid_cfg { + + u32 macid: 8; + u32 endcmd: 1; + u32 rsvd0: 23; + + u32 ul_su_info_en: 1; + u32 ul_su_bw: 2; + u32 ul_su_gi_ltf: 3; + u32 ul_su_doppler_ctrl: 2; + u32 ul_su_dcm: 1; + u32 ul_su_ss: 3; + u32 ul_su_mcs: 4; + u32 rsvd2: 5; + u32 ul_su_stbc: 1; + u32 ul_su_coding: 1; + u32 ul_su_rssi_m: 9; + +}; + +struct rtw_ul_macid_set { + + struct rtw_ul_macid_cfg ul_macid_cfg[8]; + +}; + +struct rtw_csiinfo_cfg { + u32 macid: 8; + u32 csi_info_bitmap: 8; + u32 rsvd0: 16; +}; + + +struct rtw_cqi_info { + u32 macid: 8; + u32 fw_cqi_flag: 1; /* UL or DL*/ + u32 ru_rate_table_row_idx: 4; /* UL or DL*/ + u32 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */ + u32 endcmd: 1; + u32 rsvd0: 1; + u32 rsvd1: 16; + + s8 cqi_diff_table[19]; /* UL or DL*/ + u8 rsvd2; +}; + +struct rtw_cqi_set{ + struct rtw_cqi_info cqi_info[8]; +}; + +struct rtw_bbinfo_cfg { + u32 p20_ch_bitmap: 8; + u32 rsvd0: 24; +}; + +struct rtw_pwr_by_rt_tbl{ + s16 pwr_by_rt[32]; +}; + + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; +// u32 halbb_upd_dlru_fixtbl(struct bb_info *bb, +// struct rtw_dl_ru_fix_tbl *info); +u32 halbb_upd_dlru_fixtbl(struct bb_info *bb, + union rtw_dlru_fixtbl *union_info); +u32 halbb_upd_dlru_grptbl(struct bb_info *bb, + struct rtw_dl_ru_gp_tbl *info); +// u32 halbb_upd_ulru_fixtbl(struct bb_info *bb, +// struct rtw_ul_ru_fix_tbl *info); +u32 halbb_upd_ulru_fixtbl(struct bb_info *bb, + union rtw_ulru_fixtbl *union_info); +u32 halbb_upd_ulru_grptbl(struct bb_info *bb, + struct rtw_ul_ru_gp_tbl *info); +u32 halbb_upd_rusta_info(struct bb_info *bb, + struct rtw_ru_sta_info *info); +u32 halbb_upd_ba_infotbl(struct bb_info *bb, + struct rtw_ba_tbl_info *info); +u32 halbb_swgrp_hdl(struct bb_info *bb, + struct rtw_sw_grp_set *info); + +u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg); + +u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg); + +u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg); + +u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg); + +u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg); + +u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg); + +/*u32 halbb_rua_tbl_init(struct bb_info *bb);*/ +#endif +#endif diff --git a/phl/hal_g6/phy/bb/halbb_rua_tbl_l_endian.h b/phl/hal_g6/phy/bb/halbb_rua_tbl_l_endian.h new file mode 100644 index 0000000..04db39b --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_rua_tbl_l_endian.h @@ -0,0 +1,408 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_RUA_TBL_L_ENDIAN_H__ +#define __HALBB_RUA_TBL_L_ENDIAN_H__ + +#ifdef HALBB_RUA_SUPPORT +/*@--------------------------[Define] ---------------------------------------*/ +/*[IO Reg]*/ + +/*@--------------------------[Enum]------------------------------------------*/ + + + +/*@--------------------------[Structure]-------------------------------------*/ + + +struct halbb_rua_tbl_hdr_info { + u8 rw:1; + u8 idx:7; + + u8 offset:5; + u8 len_l:3; + + u8 len_m:7; + u8 type:1; + + u8 tbl_class; +}; + +struct halbb_ru_rate_info { + u8 dcm:1; + u8 ss:3; + u8 mcs:4; +}; + + + +struct halbb_tf_ba_tbl_info { + u8 fix_ba:1; + u8 ru_psd_l:7; + + u8 ru_psd_m:2; + u8 tf_rate_l:6; + + u8 tf_rate_m:3; + u8 rf_gain_fix:1; + u8 rf_gain_idx_l:4; + + u8 rf_gain_idx_m:6; + u8 tb_ppdu_bw:2; + + struct halbb_ru_rate_info rate_i; + + u8 gi_ltf:3; + u8 doppler:1; + u8 stbc:1; + u8 sta_coding:1; + u8 tb_t_pe_nom:2; + + u8 pr20_bw_en:1; + u8 ma_type: 1; + u8 rsvd1: 6; + +}; + +struct halbb_dl_ru_gp_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + + u8 ppdu_bw:2; + u8 tx_pwr_l:6; + + u8 tx_pwr_m:3; + u8 pwr_boost_fac:5; + + u8 fix_mode_flag:1; + u8 rsvd1:7; + + u8 rsvd2; + + struct halbb_tf_ba_tbl_info tf; +}; + + + +struct halbb_ul_ru_gp_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 grp_psd_max_l; + + u8 grp_psd_max_m:1; + u8 grp_psd_min_l:7; + + u8 grp_psd_min_m:2; + u8 tf_rate_l:6; + + u8 tf_rate_m:3; + u8 fix_tf_rate:1; + u8 rsvd2:4; + + u8 ppdu_bw:2; + u8 rf_gain_fix:1; + u8 rf_gain_idx_l:5; + + u8 rf_gain_idx_m:5; + u8 fix_mode_flag: 1; + u8 rsvd1: 2; + +}; + +struct halbb_ru_sta_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; +/* sta capability */ + u8 gi_ltf_48spt:1; + u8 gi_ltf_18spt:1; + u8 rsvd0:6; + +/* dl su */ + u8 dlsu_info_en:1; + u8 dlsu_bw:2; + u8 dlsu_gi_ltf:3; + u8 dlsu_doppler_ctrl:2; + + u8 dlsu_coding:1; + u8 dlsu_txbf:1; + u8 dlsu_stbc:1; + u8 dl_fwcqi_flag:1; + u8 dlru_ratetbl_ridx:4; + + u8 csi_info_bitmap; + + u8 dl_swgrp_bitmap[4]; + + u8 dlsu_dcm:1; + u8 rsvd1:6; + u8 dlsu_rate_l:1; + + u8 dlsu_rate_m; + + u8 dlsu_pwr:6; + u8 rsvd2:2; + + u8 rsvd4; +/* ul su */ + u8 ulsu_info_en:1; + u8 ulsu_bw:2; + u8 ulsu_gi_ltf:3; + u8 ulsu_doppler_ctrl:2; + + u8 ulsu_dcm:1; + u8 ulsu_ss:3; + u8 ulsu_mcs:4; + + u8 ul_fwcqi_flag:1; + u8 ulru_ratetbl_ridx:4; + u8 ulsu_stbc:1; + u8 ulsu_coding:1; + u8 ulsu_rssi_m_l:1; + + u8 ulsu_rssi_m_m; + + u8 ul_swgrp_bitmap[4]; +/* tb info */ +}; + +struct halbb_dl_fix_sta_info { + u8 mac_id; + u8 ru_pos[3]; + + u8 fix_rate:1; + u8 fix_coding:1; + u8 fix_txbf:1; + u8 fix_pwr_fac:1; + u8 rsvd0: 4; + + struct halbb_ru_rate_info rate_i; + + u8 txbf:1; + u8 coding:1; + u8 pwr_boost_fac:5; + u8 rsvd1: 1; + u8 rsvd2; +}; + +struct halbb_dl_ru_fix_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 ru_swp_flg:1; + u8 rsvd0:1; + + u8 doppler:1; + u8 stbc:1; + u8 gi_ltf:3; + u8 ma_type:1; + u8 fixru_flag:1; + u8 rupos_csht_flag:1; + + u8 rsvd2; + u8 rsvd3; + struct halbb_dl_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM]; + +}; + +struct halbb_ul_fix_sta_info { + u8 mac_id; + u8 ru_pos[3]; + u8 tgt_rssi[3]; + u8 fix_tgt_rssi: 1; + u8 fix_rate: 1; + u8 fix_coding: 1; + u8 coding: 1; + u8 rsvd1: 4; + struct halbb_ru_rate_info rate_i; +}; + + +struct halbb_ul_ru_fix_tbl_info { + + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + u8 max_sta_num:3; + u8 min_sta_num:3; + u8 doppler:1; + u8 ma_type:1; + u8 gi_ltf:3; + u8 stbc:1; + u8 fix_tb_t_pe_nom: 1; + u8 tb_t_pe_nom: 2; + u8 fixru_flag: 1; + + struct halbb_ul_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM]; + +}; + +struct halbb_rua_tbl { + struct halbb_dl_ru_gp_tbl_info dl_ru_gp_tbl_i; + struct halbb_ul_ru_gp_tbl_info ul_ru_gp_tbl_i; + struct halbb_ru_sta_info ru_sta_i; + struct halbb_dl_ru_fix_tbl_info dl_ru_fix_tbl_i; + struct halbb_ul_ru_fix_tbl_info ul_ru_fix_tbl_i; + struct halbb_tf_ba_tbl_info tf_ba_tbl_i; +}; + +struct halbb_sw_grp_bitmap { + u8 macid; + + u8 en_upd_dl_swgrp:1; + u8 en_upd_ul_swgrp:1; + u8 cmdend:1; // add for determine whether last user or not + u8 rsvd1:5; + + u8 rsvd2; + u8 rsvd3; + + u8 dl_sw_grp_bitmap[4]; + u8 ul_sw_grp_bitmap[4]; +}; + +struct halbb_sw_grp_set { + + struct halbb_sw_grp_bitmap swgrp_bitmap[8]; + +}; + +struct dl_macid_cfg { + u8 macid; + + u8 dl_su_rate_cfg:1; + u8 dl_su_rate_l:7; + + u8 dl_su_rate_m:2; + u8 dl_su_bw:2; + u8 dl_su_pwr_cfg:1; + u8 dl_su_pwr_l:3; + + u8 dl_su_pwr_m:3; + u8 rsvd0:5; + + u8 gi_ltf_4x8_support:1; + u8 gi_ltf_1x8_support:1; + u8 rsvd1:6; + + u8 dl_su_info_en:1; + u8 rsvd2:2; + u8 dl_su_gi_ltf:3; + u8 dl_su_doppler_ctrl:2; + + u8 dl_su_coding:1; + u8 dl_su_txbf:1; + u8 dl_su_stbc:1; + u8 dl_su_dcm:1; + u8 rsvd3:4; + + u8 rsvd4; +}; + +struct halbb_ul_macid_cfg { + + u8 macid; + + u8 endcmd: 1; + u8 rsvd0: 7; + + u8 rsvd1; + u8 rsvd2; + + u8 ul_su_info_en: 1; + u8 ul_su_bw: 2; + u8 ul_su_gi_ltf: 3; + u8 ul_su_doppler_ctrl: 2; + + u8 ul_su_dcm: 1; + u8 ul_su_ss: 3; + u8 ul_su_mcs: 4; + + u8 rsvd3: 5; + u8 ul_su_stbc: 1; + u8 ul_su_coding: 1; + u8 ul_su_rssi_m_l: 1; + + u8 ul_su_rssi_m_m; + +}; + +struct halbb_ul_macid_set { + + struct halbb_ul_macid_cfg ul_macid_cfg[8]; + +}; + + + +struct halbb_ba_tbl_info { + struct halbb_rua_tbl_hdr_info tbl_hdr_i; + + struct halbb_tf_ba_tbl_info tf_i; +}; + +struct csiinfo_cfg{ + u8 macid; + u8 csi_info_bitmap; + + u8 rsvd0; + u8 rsvd1; +}; + +struct halbb_cqi_info { + u8 macid; + + u8 fw_cqi_flag: 1; /* UL or DL*/ + u8 ru_rate_table_row_idx: 4; /* UL or DL*/ + u8 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */ + u8 endcmd: 1; + u8 rsvd0: 1; + + u8 rsvd1; + u8 rsvd2; + + s8 cqi_diff_table[19]; /* UL or DL*/ + u8 rsvd3; +}; + +struct halbb_cqi_set{ + struct halbb_cqi_info cqi_info[8]; +}; + +struct halbb_bb_info_cfg { + u8 p20_ch_bitmap; + + u8 rsvd0; + u8 rsvd1; + u8 rsvd2; +}; + +struct halbb_pwr_by_rt_tbl{ + u8 pwr_by_rt[64]; +}; + + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif /* HALBB_RUA_SUPPORT */ + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_statistics.c b/phl/hal_g6/phy/bb/halbb_statistics.c new file mode 100644 index 0000000..419c869 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_statistics.c @@ -0,0 +1,1497 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halbb_precomp.h" + +#ifdef HALBB_STATISTICS_SUPPORT + +void halbb_set_crc32_cnt2_rate(struct bb_info *bb, u16 rate_idx) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + bool is_ofdm_rate = halbb_is_ofdm_rate(bb, rate_idx); + bool is_ht_rate = halbb_is_ht_rate(bb, rate_idx); + bool is_vht_rate = halbb_is_vht_rate(bb, rate_idx); + bool is_he_rate = halbb_is_he_rate(bb, rate_idx); + u32 reg_addr = cr->intf_r_rate; + u32 ofdm_rate_bitmask = cr->intf_r_rate_m; + u32 ht_mcs_bitmask = cr->intf_r_mcs_m; + u32 vht_mcs_bitmask = cr->intf_r_vht_mcs_m; + u32 vht_ss_bitmask = cr->intf_r_vht_nss_m; + u32 he_mcs_bitmask =cr->intf_r_he_mcs_m; + u32 he_ss_bitmask = cr->intf_r_he_nss_m; + u8 rate_digi = 0x0; + u8 ss = 0x0; + + if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate && !is_he_rate) + BB_DBG(bb, DBG_FA_CNT, + "[STAT] rate_idx = (0x%x) Not support !!\n", + rate_idx); + + if (is_ofdm_rate) { + rate_digi = halbb_legacy_rate_2_spec_rate(bb, rate_idx); + halbb_set_reg(bb, reg_addr, ofdm_rate_bitmask, rate_digi); + usr_set->ofdm2_rate_idx = rate_idx; + usr_set->ht2_rate_idx = 0; + usr_set->vht2_rate_idx = 0; + usr_set->he2_rate_idx = 0; + } else if (is_ht_rate) { + rate_digi = halbb_rate_2_rate_digit(bb, rate_idx); + halbb_set_reg(bb, reg_addr, ht_mcs_bitmask, rate_digi); + usr_set->ht2_rate_idx = rate_idx; + usr_set->ofdm2_rate_idx = 0; + usr_set->vht2_rate_idx = 0; + usr_set->he2_rate_idx = 0; + } else if (is_vht_rate) { + rate_digi = halbb_rate_2_rate_digit(bb, rate_idx); + ss = halbb_rate_to_num_ss(bb, rate_idx); + halbb_set_reg(bb, reg_addr, vht_mcs_bitmask, rate_digi); + halbb_set_reg(bb, reg_addr, vht_ss_bitmask, ss - 1); + usr_set->vht2_rate_idx = rate_idx; + usr_set->ofdm2_rate_idx = 0; + usr_set->ht2_rate_idx = 0; + usr_set->he2_rate_idx = 0; + } else if (is_he_rate) { + rate_digi = halbb_rate_2_rate_digit(bb, rate_idx); + ss = halbb_rate_to_num_ss(bb, rate_idx); + halbb_set_reg(bb, reg_addr, he_mcs_bitmask, rate_digi); + halbb_set_reg(bb, reg_addr, he_ss_bitmask, ss - 1); + usr_set->he2_rate_idx = rate_idx; + usr_set->ofdm2_rate_idx = 0; + usr_set->ht2_rate_idx = 0; + usr_set->vht2_rate_idx = 0; + } +} + +void halbb_set_crc32_cnt3_format(struct bb_info *bb, u8 usr_type_sel) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + u32 reg_addr = cr->intf_r_mac_hdr_type; + u32 type_bitmask = cr->intf_r_mac_hdr_type_m; + + usr_set->stat_type_sel_i = usr_type_sel; + usr_set->stat_mac_type_i = TYPE_DATA; + + switch(usr_set->stat_type_sel_i) { + case STATE_PROBE_RESP: + usr_set->stat_mac_type_i = TYPE_PROBE_RESP; + break; + case STATE_BEACON: + usr_set->stat_mac_type_i = TYPE_BEACON; + break; + case STATE_ACTION: + usr_set->stat_mac_type_i = TYPE_ACTION; + break; + case STATE_BFRP: + usr_set->stat_mac_type_i = TYPE_BFRP; + break; + case STATE_NDPA: + usr_set->stat_mac_type_i = TYPE_NDPA; + break; + case STATE_BA: + usr_set->stat_mac_type_i = TYPE_BA; + break; + case STATE_RTS: + usr_set->stat_mac_type_i = TYPE_RTS; + break; + case STATE_CTS: + usr_set->stat_mac_type_i = TYPE_CTS; + break; + case STATE_ACK: + usr_set->stat_mac_type_i = TYPE_ACK; + break; + case STATE_DATA: + usr_set->stat_mac_type_i = TYPE_DATA; + break; + case STATE_NULL: + usr_set->stat_mac_type_i = TYPE_NULL; + break; + case STATE_QOS: + usr_set->stat_mac_type_i = TYPE_QOS; + break; + default: + BB_DBG(bb, DBG_FA_CNT, + "[STAT] MAC frame type cnt: Not support !!!\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] Please choose one of the following options\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {1: Probe Request}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {2: Beacon}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {3: Action}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {4: Beamforming Report Poll}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {5: NDPA}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {6: BA}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {7: RTS}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {8: CTS}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {9: ACK}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {10: Data}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {11: Null}\n"); + BB_DBG(bb, DBG_FA_CNT, + "[STAT] {12: QoS Data}\n"); + break; + } + halbb_set_reg(bb, reg_addr, type_bitmask, usr_set->stat_mac_type_i); +} + +void halbb_crc32_cnt_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u16 rate = 0x0; + u8 usr_type_sel = 0; + + if ((_os_strcmp(input[1], help) == 0)) { + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "Get CRC_OK/error for specific rate_idx or mac hdr type\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "============== Specific rate cnt ==============\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {1} {rate_idx in decimal}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "---------- Specific MAC header type ----------\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {1: Probe Request}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {2: Beacon}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {3: Action}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {4: Beamforming Report Poll}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {5: NDPA}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {6: BA}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {7: RTS}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {8: CTS}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {9: ACK}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {10: Data}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {11: Null}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "stat {2} {12: QoS Data}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Chk hang Auto recovery enable: {3} {en}\n"); + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Chk hang limit: {4} {#limit}\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "============== Notes ==============\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "------------ Rate_idx ------------\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "CCK_idx: 0~3\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "OFDM_idx: 4~11\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "HT_idx: 128~\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "VHT_1ss_idx: 256~265\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "VHT_2ss_idx: 272~281\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "HE_1ss_idx: 384~395\n"); + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "HE_2ss_idx: 400~411\n"); + } else { + HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]); + + if (var[0] == 1) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + rate = (u16)var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{rate}={0x%x}", rate); + halbb_set_crc32_cnt2_rate(bb, rate); + } else if (var[0] == 2) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + usr_type_sel = (u8)var[1]; + BB_DBG_CNSL(out_len, used, output + used, out_len - used, + "{MAC header type}={%d}", usr_type_sel); + halbb_set_crc32_cnt3_format(bb, usr_type_sel); + } else if (var[0] == 3) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + stat_t->hang_recovery_en = (u8)var[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Chk hang Auto recovery enable=%d\n", stat_t->hang_recovery_en); + } else if (var[0] == 4) { + HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]); + stat_t->chk_hang_limit = (u8)var[1]; + BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Chk hang limit=%d\n", stat_t->chk_hang_limit); + } + } + + *_used = used; + *_out_len = out_len; +} + +void halbb_print_cnt3(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + //char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + u32 tmp = 0; + u8 pcr = 0; + tmp = crc2->cnt_ofdm3_crc32_ok + crc2->cnt_ofdm3_crc32_error; + + if (bb->hal_com->dbcc_en) { + BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n"); + BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1"); + } + + switch(usr_set->stat_type_sel_i) { + case STATE_PROBE_RESP: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[Probe Response Data CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_BEACON: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[Beacon CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_ACTION: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[Action CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_BFRP: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[BFRP CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_NDPA: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[NDPA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_BA: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[BA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_RTS: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[RTS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_CTS: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[CTS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_ACK: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[ACK CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_DATA: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[DATA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_NULL: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[Null CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + case STATE_QOS: + pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp); + BB_DBG(bb, DBG_FA_CNT, + "[QoS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + crc2->cnt_ofdm3_crc32_error, + crc2->cnt_ofdm3_crc32_ok, pcr); + break; + default: + break; + } + +} + +void halbb_print_cnt2(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i; + u32 tmp = 0; + //char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + + if (bb->hal_com->dbcc_en) { + BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n"); + BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1"); + } + + if (usr_set->ofdm2_rate_idx) { + tmp = crc2->cnt_ofdm2_crc32_error + crc2->cnt_ofdm2_crc32_ok; + crc2->ofdm2_pcr = (u8)HALBB_DIV(crc2->cnt_ofdm2_crc32_ok * 100, + tmp); + halbb_print_rate_2_buff(bb, usr_set->ofdm2_rate_idx, RTW_GILTF_LGI_4XHE32, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_FA_CNT, + "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + bb->dbg_buf, crc2->cnt_ofdm2_crc32_error, + crc2->cnt_ofdm2_crc32_ok, crc2->ofdm2_pcr); + } else if (usr_set->ht2_rate_idx) { + tmp = crc2->cnt_ht2_crc32_error + crc2->cnt_ht2_crc32_ok; + crc2->ht2_pcr = (u8)HALBB_DIV(crc2->cnt_ht2_crc32_ok * 100, + tmp); + halbb_print_rate_2_buff(bb, usr_set->ht2_rate_idx, RTW_GILTF_LGI_4XHE32, bb->dbg_buf, + HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_FA_CNT, + "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + bb->dbg_buf, crc2->cnt_ht2_crc32_error, + crc2->cnt_ht2_crc32_ok, crc2->ht2_pcr); + } else if(usr_set->vht2_rate_idx) { + tmp = crc2->cnt_vht2_crc32_error + + crc2->cnt_vht2_crc32_ok; + crc2->vht2_pcr = (u8)HALBB_DIV(crc2->cnt_vht2_crc32_ok * + 100, tmp); + halbb_print_rate_2_buff(bb, usr_set->vht2_rate_idx, + RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_FA_CNT, + "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + bb->dbg_buf, crc2->cnt_vht2_crc32_error, + crc2->cnt_vht2_crc32_ok, crc2->vht2_pcr); + } else if (usr_set->he2_rate_idx) { + tmp = crc2->cnt_he2_crc32_error + + crc2->cnt_he2_crc32_ok; + crc2->he2_pcr = (u8)HALBB_DIV(crc2->cnt_he2_crc32_ok * + 100, tmp); + halbb_print_rate_2_buff(bb, usr_set->he2_rate_idx, + RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE); + BB_DBG(bb, DBG_FA_CNT, + "[HE:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n", + bb->dbg_buf, crc2->cnt_he2_crc32_error, + crc2->cnt_he2_crc32_ok, crc2->he2_pcr); + } +} + +void halbb_chk_hang(struct bb_info *bb) +{ + struct bb_stat_info *stat = &bb->bb_stat_i; + struct bb_cca_info *cca = &stat->bb_cca_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + bool chk_hang_en = false; + + /* According to sd4 info., when rx hang --> all cca brk, half of brk is l-sig brk */ + chk_hang_en = (cca->cnt_cca_all == 0); + + if (chk_hang_en) { + BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] ReasonCode:RHAX-2 (POP HANG)\n\n"); + stat->chk_hang_cnt = stat->chk_hang_cnt + 1; + + BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] hang_cnt=%d, hang_limit=%d, recovery_en=%d\n", + stat->chk_hang_cnt, stat->chk_hang_limit, stat->hang_recovery_en); + + if (stat->hang_recovery_en && (stat->chk_hang_cnt >= stat->chk_hang_limit)) { + + BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] Change PoP counter limit\n"); + halbb_set_reg(bb, cr->max_cnt_pop, cr->max_cnt_pop_m, 0x0); + halbb_delay_us(bb, 1); + halbb_set_reg(bb, cr->max_cnt_pop, cr->max_cnt_pop_m, 0x50); + + stat->chk_hang_cnt = 0; + } + } +} + +void halbb_print_cnt(struct bb_info *bb, bool cck_en, enum phl_phy_idx phy_idx, enum phl_phy_idx phy_idx_2) +{ + + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i; + struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i; + struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i; + struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i; + struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i; + struct rtw_hal_com_t *hal = bb->hal_com; + struct rtw_hal_stat_info *stat_info = &hal->band[bb->bb_phy_idx].stat_info; + + if (bb->hal_com->dbcc_en) { + if (!cck_en) { + fa->cnt_fail_all = fa->cnt_ofdm_fail; + cca->cnt_cca_all = cca->cnt_ofdm_cca; + } else { + fa->cnt_fail_all = fa->cnt_ofdm_fail + + fa->cnt_cck_fail; + cca->cnt_cca_all = cca->cnt_cck_cca + + cca->cnt_ofdm_cca; + } + } else { + if (!cck_en) { + fa->cnt_fail_all = fa->cnt_ofdm_fail; + cca->cnt_cca_all = cca->cnt_ofdm_cca; + } else { + fa->cnt_fail_all = fa->cnt_ofdm_fail + + fa->cnt_cck_fail; + cca->cnt_cca_all = cca->cnt_cck_cca + + cca->cnt_ofdm_cca; + } + + } + + crc->cnt_crc32_error_all = crc->cnt_he_crc32_error + + crc->cnt_vht_crc32_error + + crc->cnt_ht_crc32_error + + crc->cnt_ofdm_crc32_error + + crc->cnt_cck_crc32_error; + + crc->cnt_crc32_ok_all = crc->cnt_he_crc32_ok + + crc->cnt_vht_crc32_ok + + crc->cnt_ht_crc32_ok + + crc->cnt_ofdm_crc32_ok + + crc->cnt_cck_crc32_ok; + + stat_info->cnt_fail_all = fa->cnt_fail_all; + stat_info->cnt_cck_fail = fa->cnt_cck_fail; + stat_info->cnt_ofdm_fail = fa->cnt_ofdm_fail; + stat_info->cnt_cca_all = cca->cnt_cca_all; + stat_info->cnt_ofdm_cca = cca->cnt_ofdm_cca; + stat_info->cnt_cck_cca = cca->cnt_cck_cca; + stat_info->cnt_crc32_error_all = crc->cnt_crc32_error_all; + stat_info->cnt_he_crc32_error = crc->cnt_he_crc32_error; + stat_info->cnt_vht_crc32_error = crc->cnt_vht_crc32_error; + stat_info->cnt_ht_crc32_error = crc->cnt_ht_crc32_error; + stat_info->cnt_ofdm_crc32_error = crc->cnt_ofdm_crc32_error; + stat_info->cnt_cck_crc32_error = crc->cnt_cck_crc32_error; + stat_info->cnt_crc32_ok_all = crc->cnt_crc32_ok_all; + stat_info->cnt_he_crc32_ok = crc->cnt_he_crc32_ok; + stat_info->cnt_vht_crc32_ok = crc->cnt_vht_crc32_ok; + stat_info->cnt_ht_crc32_ok = crc->cnt_ht_crc32_ok; + stat_info->cnt_ofdm_crc32_ok = crc->cnt_ofdm_crc32_ok; + stat_info->cnt_cck_crc32_ok = crc->cnt_cck_crc32_ok; + stat_info->igi_fa_rssi = bb->bb_dig_i.p_cur_dig_unit->igi_fa_rssi; + + if (bb->hal_com->dbcc_en) { + BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n"); + BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1"); +#if 1 + if (cck_en) { + if (phy_idx_2 != HW_PHY_MAX) + BB_DBG(bb, DBG_FA_CNT, "[The following CCK statistics is at %s]===>\n", + phy_idx_2 == HW_PHY_0 ? "PHY-0" : "PHY-1"); + } +#endif + } + + BB_DBG(bb, DBG_FA_CNT, "[Tx counter]===>\n"); + BB_DBG(bb, DBG_FA_CNT, + "[Tx Cnt]{CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON}: {%d, %d, %d, %d}\n", + tx->cck_mac_txen, tx->cck_phy_txon, tx->ofdm_mac_txen, + tx->ofdm_phy_txon); + + BB_DBG(bb, DBG_FA_CNT, "[Rx counter]===>\n"); + BB_DBG(bb, DBG_FA_CNT, + "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + cca->cnt_cck_cca, cca->cnt_ofdm_cca, cca->cnt_cca_all); + BB_DBG(bb, DBG_FA_CNT, + "[CCA Spoofing Cnt] {CCK, OFDM} = {%d, %d}\n", + cca->cnt_cck_spoofing, cca->cnt_ofdm_spoofing); + BB_DBG(bb, DBG_FA_CNT, + "[MPDU] {miss, CRC ok, CRC err} = {%d, %d, %d}\n", + crc->cnt_ampdu_miss, crc->cnt_ampdu_crc_ok, + crc->cnt_ampdu_crc_error); + BB_DBG(bb, DBG_FA_CNT, + "[Total HW Break counter] = {%d}\n", fa->cnt_total_brk); + BB_DBG(bb, DBG_FA_CNT, + "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa->cnt_cck_fail, fa->cnt_ofdm_fail, fa->cnt_fail_all); + BB_DBG(bb, DBG_FA_CNT, + "[CCK FA] SFD_err=%d, SIG_err=%d CRC16=%d\n", + cck_fa->sfd_gg_cnt, cck_fa->sig_gg_cnt, cck_fa->cnt_cck_crc_16); + BB_DBG(bb, DBG_FA_CNT, + "[OFDM FA] Parity_err=%d, Rate=%d, LSIG_brk_s=%d, LSIG_brk_l=%d, SBD=%d\n", + legacy_fa->cnt_parity_fail, legacy_fa->cnt_rate_illegal, + legacy_fa->cnt_lsig_brk_s_th, legacy_fa->cnt_lsig_brk_l_th, + legacy_fa->cnt_sb_search_fail); + BB_DBG(bb, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n", + ht_fa->cnt_crc8_fail, ht_fa->cnt_mcs_fail); + BB_DBG(bb, DBG_FA_CNT, + "[VHT FA] SIGA_CRC8=%d, MCS=%d\n", + vht_fa->cnt_crc8_fail_vhta, vht_fa->cnt_mcs_fail_vht); +#if 0 + BB_DBG(bb, DBG_FA_CNT, + "[HE FA] SIGA_CRC4_SU=%d, SIGA_CRC4_ERSU=%d, SIGA_CRC4_MU=%d, SIGB_CRC4_ch1=%d, SIGB_CRC4_ch2=%d, MCS=%d, MCS_bcc=%d, MCS_DCM=%d\n", + he_fa->cnt_crc4_fail_hea_su, he_fa->cnt_crc4_fail_hea_ersu, + he_fa->cnt_crc4_fail_hea_mu, he_fa->cnt_crc4_fail_heb_ch1_mu, + he_fa->cnt_crc4_fail_heb_ch2_mu, he_fa->cnt_mcs_fail_he, + he_fa->cnt_mcs_fail_he_bcc, he_fa->cnt_mcs_fail_he_dcm); +#endif + + BB_DBG(bb, DBG_FA_CNT, + "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, HE, Total} = {%d, %d, %d, %d, %d, %d}\n", + crc->cnt_cck_crc32_ok, crc->cnt_ofdm_crc32_ok, + crc->cnt_ht_crc32_ok, crc->cnt_vht_crc32_ok, + crc->cnt_he_crc32_ok, crc->cnt_crc32_ok_all); + BB_DBG(bb, DBG_FA_CNT, + "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, HE, Total} = {%d, %d, %d, %d, %d, %d}\n", + crc->cnt_cck_crc32_error, crc->cnt_ofdm_crc32_error, + crc->cnt_ht_crc32_error, crc->cnt_vht_crc32_error, + crc->cnt_he_crc32_error, crc->cnt_crc32_error_all); + BB_DBG(bb, DBG_FA_CNT, "[Halbb DM status]===>\n"); + BB_DBG(bb, DBG_FA_CNT, "[DIG] IGI=%d\n", stat_info->igi_fa_rssi); +} + +void halbb_cnt_reg_reset(struct bb_info *bb) +{ + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + /* @reset CCK FA counter */ + halbb_set_reg(bb, cr->r1b_rx_rpt_rst, cr->r1b_rx_rpt_rst_m, 0); + halbb_set_reg(bb, cr->r1b_rx_rpt_rst, cr->r1b_rx_rpt_rst_m, 1); + + /* @make sure cnt is enable */ + halbb_set_reg_phy0_1(bb, cr->enable_all_cnt, cr->enable_all_cnt_m, 1); + + /* @reset all bb hw cnt */ + halbb_mp_reset_cnt(bb); +} + +void halbb_cck_cnt_statistics(struct bb_info *bb) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + + u32 ret_value = 0; + +#if (defined(HALBB_COMPILE_AP_SERIES) || defined(HALBB_COMPILE_CLIENT_SERIES)) + /* select cck dbg port */ + halbb_set_reg(bb, cr->r1b_rr_sel, cr->r1b_rr_sel_m, 2); + + /* read CCK CCA counter */ + ret_value = halbb_get_reg(bb, cr->cck_cca, cr->cck_cca_m); + cca->cnt_cck_cca = ret_value; + + /* select cck dbg port */ + halbb_set_reg(bb, cr->r1b_rr_sel, cr->r1b_rr_sel_m, 1); + + /* read CCK CRC32 counter */ + ret_value = halbb_get_reg(bb, cr->cck_crc32ok, MASKDWORD); + crc->cnt_cck_crc32_ok = ret_value & cr->cck_crc32ok_m; + crc->cnt_cck_crc32_error = (ret_value & cr->cck_crc32fail_m) >> 16; + + /* Read CCK FA counter */ + ret_value = halbb_get_reg(bb, 0x23e0, MASKLWORD); // Reg. doc. doesn't have CCK report reg. 0x78(0x23), need change these addr. one by one + cck_fa->sfd_gg_cnt = ret_value; + + ret_value = halbb_get_reg(bb, 0x23e0, MASKHWORD); + cck_fa->cnt_cck_crc_16 = ret_value; + + ret_value = halbb_get_reg(bb, 0x23e8, MASKLWORD); + cck_fa->sig_gg_cnt = ret_value; + + /* Number of spoofing*/ + ret_value = halbb_get_reg(bb, 0x23ec, MASKBYTE0); + cca->cnt_cck_spoofing = ret_value; + + //fa->cnt_cck_fail = cck_fa->sfd_gg_cnt + cck_fa->sig_gg_cnt; + + /* Adjust FA computation due to repeated caculatation of brk_cnt when pop starting*/ + fa->cnt_cck_fail = cca->cnt_cck_cca - crc->cnt_cck_crc32_ok - + crc->cnt_cck_crc32_error - cca->cnt_cck_spoofing; +#elif (defined(HALBB_COMPILE_AP2_SERIES)) + /*Wait for b mode report CR docs. preparation*/ +#endif +} + +void halbb_ofdm_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i; + struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i; + struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i; + struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + u32 ret_value = 0; + + /* read OFDM CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok, MASKDWORD, phy_idx); + crc->cnt_ofdm_crc32_ok = ret_value & cr->l_crc_ok_m; + crc->cnt_ofdm_crc32_error = (ret_value & cr->l_crc_err_m) >> 16; + + /* read OFDM2 CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok2, MASKDWORD, phy_idx); + crc2->cnt_ofdm2_crc32_ok = ret_value & cr->l_crc_ok2_m; + crc2->cnt_ofdm2_crc32_error = (ret_value & cr->l_crc_err2_m) >> 16; + + /* read OFDM3 CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok3, MASKDWORD, phy_idx); + crc2->cnt_ofdm3_crc32_ok = ret_value & cr->l_crc_ok3_m; + crc2->cnt_ofdm3_crc32_error = (ret_value & cr->l_crc_err3_m) >> 16; + + /* read HT CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->ht_crc_ok, MASKDWORD, phy_idx); + crc->cnt_ht_crc32_ok = ret_value & cr->ht_crc_ok_m; + crc->cnt_ht_crc32_error = (ret_value & cr->ht_crc_err_m) >> 16; + + /* read HT2 CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->ht_crc_ok2, MASKDWORD, phy_idx); + crc2->cnt_ht2_crc32_ok = ret_value & cr->ht_crc_ok2_m; + crc2->cnt_ht2_crc32_error = (ret_value & cr->ht_crc_err2_m) >> 16; + + /*read VHT CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->vht_crc_ok, MASKDWORD, phy_idx); + crc->cnt_vht_crc32_ok = ret_value & cr->vht_crc_ok_m; + crc->cnt_vht_crc32_error = (ret_value & cr->vht_crc_err_m) >> 16; + + /*read VHT2 CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->vht_crc_ok2, MASKDWORD, phy_idx); + crc2->cnt_vht2_crc32_ok = ret_value & cr->vht_crc_ok2_m; + crc2->cnt_vht2_crc32_error = (ret_value & cr->vht_crc_err2_m) >> 16; + + /*read HE CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->he_crc_ok, MASKDWORD, phy_idx); + crc->cnt_he_crc32_ok = ret_value & cr->he_crc_ok_m; + crc->cnt_he_crc32_error = (ret_value & cr->he_crc_err_m) >> 16; + + /*read HE2 CRC32 counter */ + ret_value = halbb_get_reg_cmn(bb, cr->he_crc_ok2, MASKDWORD, phy_idx); + crc2->cnt_he2_crc32_ok = ret_value & cr->he_crc_ok2_m; + crc2->cnt_he2_crc32_error = (ret_value & cr->he_crc_err2_m) >> 16; + + ret_value = halbb_get_reg_cmn(bb, cr->brk, cr->brk_m, phy_idx); + fa->cnt_total_brk = ret_value; + + /* Acut workaround because of no HE cnt */ + fa->cnt_ofdm_fail= ret_value; + + /* @calculate OFDM FA counter instead of reading brk_cnt*/ + ret_value = halbb_get_reg_cmn(bb, cr->search_fail, cr->search_fail_m, phy_idx); + legacy_fa->cnt_sb_search_fail = ret_value; + + /* Legacy portion */ + ret_value = halbb_get_reg_cmn(bb, cr->lsig_brk_s_th, cr->lsig_brk_s_th_m, phy_idx); + legacy_fa->cnt_lsig_brk_s_th = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->lsig_brk_l_th, cr->lsig_brk_l_th_m, phy_idx); + legacy_fa->cnt_lsig_brk_l_th = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->rxl_err_parity, cr->rxl_err_parity_m, phy_idx); + legacy_fa->cnt_parity_fail = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->rxl_err_rate, cr->rxl_err_rate_m, phy_idx); + legacy_fa->cnt_rate_illegal = ret_value; + + /* HT portion */ + ret_value = halbb_get_reg_cmn(bb, cr->ht_not_support_mcs, cr->ht_not_support_mcs_m, phy_idx); + ht_fa->cnt_mcs_fail = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->htsig_crc8_err_s_th, cr->htsig_crc8_err_s_th_m, phy_idx); + ht_fa->cnt_crc8_fail_s_th = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->htsig_crc8_err_l_th, cr->htsig_crc8_err_l_th_m, phy_idx); + ht_fa->cnt_crc8_fail_l_th = ret_value; + + ht_fa->cnt_crc8_fail = ht_fa->cnt_crc8_fail_s_th + ht_fa->cnt_crc8_fail_l_th; + + /* VHT portion */ + ret_value = halbb_get_reg_cmn(bb, cr->vht_not_support_mcs, cr->vht_not_support_mcs_m, phy_idx); + vht_fa->cnt_mcs_fail_vht = ret_value; + + ret_value = halbb_get_reg_cmn(bb, cr->vht_err_siga_crc8, cr->vht_err_siga_crc8_m, phy_idx); + vht_fa->cnt_crc8_fail_vhta = ret_value; + +#if 0 + /* HE portion need to ECO for CBV */ + ret_value = halbb_get_reg_cmn(bb, cr->hesu_err_sig_a_crc4, MASKDWORD, phy_idx); + he_fa->cnt_crc4_fail_hea_su = ret_value & cr->hesu_err_sig_a_crc4_m; + he_fa->cnt_crc4_fail_hea_ersu = ret_value & cr->heersu_err_sig_a_crc4_m; + + ret_value = halbb_get_reg_cmn(bb, cr->hemu_err_sig_a_crc4, MASKDWORD, phy_idx); + he_fa->cnt_crc4_fail_hea_mu = ret_value & cr->hemu_err_sig_a_crc4_m; + he_fa->cnt_crc4_fail_heb_ch1_mu = (ret_value & cr->hemu_err_sigb_ch1_comm_crc4_m) >> 16; + + ret_value = halbb_get_reg_cmn(bb, 0x4a08, cr->hemu_err_sigb_ch1_comm_crc4, phy_idx); + he_fa->cnt_crc4_fail_heb_ch2_mu = ret_value & cr->hemu_err_sigb_ch1_comm_crc4_m; + he_fa->cnt_mcs_fail_he_bcc = ret_value & cr->he_u0_err_bcc_mcs_m; + + ret_value = halbb_get_reg_cmn(bb, 0x4a0c, cr->he_u0_err_mcs, phy_idx); + he_fa->cnt_mcs_fail_he = ret_value & cr->he_u0_err_m; + he_fa->cnt_mcs_fail_he_dcm = ret_value & cr->he_u0_err_mcs_m; + + + fa->cnt_ofdm_fail = legacy_fa->cnt_lsig_brk_s_th + + legacy_fa->cnt_sb_search_fail + + legacy_fa->cnt_lsig_brk_l_th + + legacy_fa->cnt_rate_illegal + + legacy_fa->cnt_parity_fail + + ht_fa->cnt_mcs_fail + ht_fa->cnt_crc8_fail + + vht_fa->cnt_mcs_fail_vht + + vht_fa->cnt_crc8_fail_vhta + + he_fa->cnt_crc4_fail_hea_su + + he_fa->cnt_crc4_fail_hea_ersu + + he_fa->cnt_crc4_fail_hea_mu + + he_fa->cnt_crc4_fail_heb_ch1_mu + + he_fa->cnt_crc4_fail_heb_ch2_mu + + he_fa->cnt_mcs_fail_he_bcc + + he_fa->cnt_mcs_fail_he + + he_fa->cnt_mcs_fail_he_dcm +#endif + + /* read OFDM CCA counter */ + ret_value = halbb_get_reg_cmn(bb, cr->ofdm_cca, cr->ofdm_cca_m, phy_idx); + cca->cnt_ofdm_cca = ret_value; + ret_value = halbb_get_reg_cmn(bb, cr->cca_spoofing, cr->cca_spoofing_m, phy_idx); + cca->cnt_ofdm_spoofing = ret_value; + ret_value = halbb_get_reg_cmn(bb, cr->ampdu_miss, cr->ampdu_miss_m, phy_idx); + crc->cnt_ampdu_miss = ret_value; + ret_value = halbb_get_reg_cmn(bb, cr->ampdu_crc_ok, cr->ampdu_crc_ok_m, phy_idx); + crc->cnt_ampdu_crc_ok = ret_value; + ret_value = halbb_get_reg_cmn(bb, cr->ampdu_crc_err, cr->ampdu_crc_err_m, phy_idx); + crc->cnt_ampdu_crc_error = ret_value; + /* POP counter */ + ret_value = halbb_get_reg_cmn(bb, cr->cnt_pop_trig, cr->cnt_pop_trig_m, phy_idx); + cca->pop_cnt = ret_value; + +} + +void halbb_cck_tx_cnt_statistics(struct bb_info *bb) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + u32 ret_value = 0; + + /* read Tx counter */ + ret_value = halbb_get_reg(bb, cr->ccktxon, cr->ccktxon_m); + tx->cck_phy_txon = ret_value; + ret_value = halbb_get_reg(bb, cr->ccktxen, cr->ccktxen_m); + tx->cck_mac_txen = ret_value; +} + +void halbb_ofdm_tx_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + u32 ret_value = 0; + + /* read Tx counter */ + ret_value = halbb_get_reg_cmn(bb, cr->ofdmtxon, MASKDWORD, phy_idx); + tx->ofdm_phy_txon = ret_value & cr->ofdmtxon_m; + tx->ofdm_mac_txen = (ret_value & cr->ofdmtxen_m) >> 16; +} + +void halbb_statistics_reset(struct bb_info *bb) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_fa_info *fa = &stat_t->bb_fa_i; + struct bb_cca_info *cca = &stat_t->bb_cca_i; + struct bb_crc_info *crc = &stat_t->bb_crc_i; + struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i; + struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i; + + /* @reset sw mem */ + halbb_mem_set(bb, tx, 0, sizeof(struct bb_tx_cnt_info)); + halbb_mem_set(bb, fa, 0, sizeof(struct bb_fa_info)); + halbb_mem_set(bb, cca, 0, sizeof(struct bb_cca_info)); + halbb_mem_set(bb, crc, 0, sizeof(struct bb_crc_info)); + halbb_mem_set(bb, crc2, 0, sizeof(struct bb_crc2_info)); +} + +void halbb_statistics(struct bb_info *bb) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + //char dbg_buf[HALBB_SNPRINT_SIZE] = {0}; + u32 tmp = 0; + u8 path_a_ch = 0; + u8 path_b_ch = 0; + bool cck_en = 0; + u8 cck_band_sel = 0; + + /* Always turn on*/ + if (!(bb->support_ability & BB_FA_CNT)) + return; + + BB_DBG(bb, DBG_FA_CNT, "[%s]===>\n", __func__); + + /*Need to provide API by HALRF . Dino 2020.02.21*/ + path_a_ch = (u8)halbb_read_rf_reg(bb, RF_PATH_A, 0x18, 0x3ff); + path_b_ch = (u8)halbb_read_rf_reg(bb, RF_PATH_B, 0x18, 0x3ff); + + cck_en = (path_a_ch <= 14) || (path_b_ch <= 14); + cck_band_sel = (u8)halbb_get_reg(bb, cr->dbcc, cr->dbcc_m); + + if (bb->hal_com->dbcc_en) { + if (!cck_en) { + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0); + halbb_ofdm_cnt_statistics(bb, HW_PHY_0); + + halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_MAX); + halbb_print_cnt2(bb, HW_PHY_0); + halbb_print_cnt3(bb, HW_PHY_0); + + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_1); + halbb_ofdm_cnt_statistics(bb, HW_PHY_1); + + halbb_print_cnt(bb, cck_en, HW_PHY_1, HW_PHY_MAX); + halbb_print_cnt2(bb, HW_PHY_1); + halbb_print_cnt3(bb, HW_PHY_1); + } else { + halbb_cck_tx_cnt_statistics(bb); + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0); + halbb_cck_cnt_statistics(bb); + halbb_ofdm_cnt_statistics(bb, HW_PHY_0); + + halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_0); + halbb_print_cnt2(bb, HW_PHY_0); + halbb_print_cnt3(bb, HW_PHY_0); + + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_1); + halbb_ofdm_cnt_statistics(bb, HW_PHY_1); + + halbb_print_cnt(bb, cck_en, HW_PHY_1, HW_PHY_MAX); + halbb_print_cnt2(bb, HW_PHY_1); + halbb_print_cnt3(bb, HW_PHY_1); + }/*else if (cck_en && (cck_band_sel == 1)) { + halbb_cck_cnt_statistics(bb, HW_PHY_1); + halbb_ofdm_cnt_statistics(bb, HW_PHY_0); + + halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_1); + halbb_print_cnt2(bb, HW_PHY_0); + halbb_print_cnt3(bb, HW_PHY_0); + }*/ + } else { + if (!cck_en) { + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0); + halbb_ofdm_cnt_statistics(bb, HW_PHY_0); + + halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_MAX); + halbb_print_cnt2(bb, HW_PHY_0); + halbb_print_cnt3(bb, HW_PHY_0); + } else { + halbb_cck_tx_cnt_statistics(bb); + halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0); + halbb_cck_cnt_statistics(bb); + halbb_ofdm_cnt_statistics(bb, HW_PHY_0); + + halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_0); + halbb_print_cnt2(bb, HW_PHY_0); + halbb_print_cnt3(bb, HW_PHY_0); + } + } + +/*==52A CBV CCV/52B/52C Rx hang workaround==*/ + halbb_chk_hang(bb); +/*================================*/ + + halbb_cnt_reg_reset(bb); +} + +void halbb_statistics_init(struct bb_info *bb) +{ + struct bb_stat_info *stat_t = &bb->bb_stat_i; + stat_t->chk_hang_cnt = 0; + stat_t->hang_recovery_en = HANG_RECOVERY; + stat_t->chk_hang_limit = HANG_LIMIT; + halbb_statistics_reset(bb); + halbb_set_crc32_cnt2_rate(bb, BB_06M); + halbb_set_crc32_cnt3_format(bb, STATE_BEACON); +} + +void halbb_cr_cfg_stat_init(struct bb_info *bb) +{ + struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i; + + switch (bb->cr_type) { + + #ifdef BB_8852A_CAV_SUPPORT + case BB_52AA: + cr->cck_cca = CNT_CCK_CCA_P0_52AA; + cr->cck_cca_m = CNT_CCK_CCA_P0_52AA_M; + cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_52AA; + cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_52AA_M; + cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_52AA; + cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_52AA_M; + cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_52AA; + cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_52AA_M; + cr->cca_spoofing = CNT_CCA_SPOOFING_52AA; + cr->cca_spoofing_m = CNT_CCA_SPOOFING_52AA_M; + cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_52AA; + cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_52AA_M; + cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_52AA; + cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_52AA_M; + cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_52AA; + cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_52AA_M; + cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_52AA; + cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_52AA_M; + cr->brk = CNT_BRK_52AA; + cr->brk_m = CNT_BRK_52AA_M; + cr->brk_sel = CNT_BRK_SEL_52AA; + cr->brk_sel_m = CNT_BRK_SEL_52AA_M; + cr->rxl_err_parity = CNT_RXL_ERR_PARITY_52AA; + cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_52AA_M; + cr->rxl_err_rate = CNT_RXL_ERR_RATE_52AA; + cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_52AA_M; + cr->ht_err_crc8 = CNT_HT_ERR_CRC8_52AA; + cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_52AA_M; + cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_52AA; + cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_52AA_M; + cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_52AA; + cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_52AA_M; + cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_52AA; + cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_52AA_M; + cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_52AA; + cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_52AA_M; + cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_52AA; + cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_52AA_M; + cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_52AA; + cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_52AA_M; + cr->search_fail = CNT_SEARCH_FAIL_52AA; + cr->search_fail_m = CNT_SEARCH_FAIL_52AA_M; + cr->ofdm_cca = CNT_OFDM_CCA_52AA; + cr->ofdm_cca_m = CNT_OFDM_CCA_52AA_M; + cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_52AA; + cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_52AA_M; + cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_52AA; + cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_52AA_M; + cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_52AA; + cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_52AA_M; + cr->ofdmtxon = CNT_OFDMTXON_52AA; + cr->ofdmtxon_m = CNT_OFDMTXON_52AA_M; + cr->ofdmtxen = CNT_OFDMTXEN_52AA; + cr->ofdmtxen_m = CNT_OFDMTXEN_52AA_M; + cr->drop_trig = CNT_DROP_TRIG_52AA; + cr->drop_trig_m = CNT_DROP_TRIG_52AA_M; + cr->pop_trig = CNT_POP_TRIG_52AA; + cr->pop_trig_m = CNT_POP_TRIG_52AA_M; + cr->tx_conflict = CNT_TX_CONFLICT_52AA; + cr->tx_conflict_m = CNT_TX_CONFLICT_52AA_M; + cr->wmac_rstb = CNT_WMAC_RSTB_52AA; + cr->wmac_rstb_m = CNT_WMAC_RSTB_52AA_M; + cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_52AA; + cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_52AA_M; + cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_52AA; + cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_52AA_M; + cr->he_crc_ok = CNT_HE_CRC_OK_52AA; + cr->he_crc_ok_m = CNT_HE_CRC_OK_52AA_M; + cr->he_crc_err = CNT_HE_CRC_ERR_52AA; + cr->he_crc_err_m = CNT_HE_CRC_ERR_52AA_M; + cr->vht_crc_ok = CNT_VHT_CRC_OK_52AA; + cr->vht_crc_ok_m = CNT_VHT_CRC_OK_52AA_M; + cr->vht_crc_err = CNT_VHT_CRC_ERR_52AA; + cr->vht_crc_err_m = CNT_VHT_CRC_ERR_52AA_M; + cr->ht_crc_ok = CNT_HT_CRC_OK_52AA; + cr->ht_crc_ok_m = CNT_HT_CRC_OK_52AA_M; + cr->ht_crc_err = CNT_HT_CRC_ERR_52AA; + cr->ht_crc_err_m = CNT_HT_CRC_ERR_52AA_M; + cr->l_crc_ok = CNT_L_CRC_OK_52AA; + cr->l_crc_ok_m = CNT_L_CRC_OK_52AA_M; + cr->l_crc_err = CNT_L_CRC_ERR_52AA; + cr->l_crc_err_m = CNT_L_CRC_ERR_52AA_M; + cr->he_crc_ok2 = CNT_HE_CRC_OK2_52AA; + cr->he_crc_ok2_m = CNT_HE_CRC_OK2_52AA_M; + cr->he_crc_err2 = CNT_HE_CRC_ERR2_52AA; + cr->he_crc_err2_m = CNT_HE_CRC_ERR2_52AA_M; + cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_52AA; + cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_52AA_M; + cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_52AA; + cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_52AA_M; + cr->ht_crc_ok2 = CNT_HT_CRC_OK2_52AA; + cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_52AA_M; + cr->ht_crc_err2 = CNT_HT_CRC_ERR2_52AA; + cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_52AA_M; + cr->l_crc_ok2 = CNT_L_CRC_OK2_52AA; + cr->l_crc_ok2_m = CNT_L_CRC_OK2_52AA_M; + cr->l_crc_err2 = CNT_L_CRC_ERR2_52AA; + cr->l_crc_err2_m = CNT_L_CRC_ERR2_52AA_M; + cr->l_crc_ok3 = CNT_L_CRC_OK3_52AA; + cr->l_crc_ok3_m = CNT_L_CRC_OK3_52AA_M; + cr->l_crc_err3 = CNT_L_CRC_ERR3_52AA; + cr->l_crc_err3_m = CNT_L_CRC_ERR3_52AA_M; + cr->ampdu_rxon = CNT_AMPDU_RXON_52AA; + cr->ampdu_rxon_m = CNT_AMPDU_RXON_52AA_M; + cr->ampdu_miss = CNT_AMPDU_MISS_52AA; + cr->ampdu_miss_m = CNT_AMPDU_MISS_52AA_M; + cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_52AA; + cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_52AA_M; + cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_52AA; + cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_52AA_M; + cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_52AA; + cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_52AA_M; + cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_52AA; + cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_52AA_M; + cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_52AA; + cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_52AA_M; + cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_52AA; + cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_52AA_M; + cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_52AA; + cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_52AA_M; + cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_52AA; + cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_52AA_M; + cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_52AA; + cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_52AA_M; + cr->r1b_rr_sel = R1B_RR_SEL_52AA; + cr->r1b_rr_sel_m = R1B_RR_SEL_52AA_M; + cr->rst_all_cnt = RST_ALL_CNT_52AA; + cr->rst_all_cnt_m = RST_ALL_CNT_52AA_M; + cr->enable_all_cnt = ENABLE_ALL_CNT_52AA; + cr->enable_all_cnt_m = ENABLE_ALL_CNT_52AA_M; + cr->enable_ofdm = ENABLE_OFDM_52AA; + cr->enable_ofdm_m = ENABLE_OFDM_52AA_M; + cr->enable_cck = ENABLE_CCK_52AA; + cr->enable_cck_m = ENABLE_CCK_52AA_M; + cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_52AA; + cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_52AA_M; + cr->intf_r_rate = INTF_R_CNT_RATE_52AA; + cr->intf_r_rate_m = INTF_R_CNT_RATE_52AA_M; + cr->intf_r_mcs = INTF_R_CNT_MCS_52AA; + cr->intf_r_mcs_m = INTF_R_CNT_MCS_52AA_M; + cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_52AA; + cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_52AA_M; + cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_52AA; + cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_52AA_M; + cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_52AA; + cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_52AA_M; + cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_52AA; + cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_52AA_M; + cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_52AA; + cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_52AA_M; + cr->intf_r_pkt_type = INTF_R_PKT_TYPE_52AA; + cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_52AA_M; + cr->dbcc = DBCC_52AA; + cr->dbcc_m = DBCC_52AA_M; + cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_52AA; + cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_52AA_M; + cr->max_cnt_pop = MAX_CNT_POP_52AA; + cr->max_cnt_pop_m = MAX_CNT_POP_52AA_M; + break; + + #endif + #ifdef HALBB_COMPILE_AP_SERIES + case BB_AP: + cr->cck_cca = CNT_CCK_CCA_P0_A; + cr->cck_cca_m = CNT_CCK_CCA_P0_A_M; + cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_A; + cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_A_M; + cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_A; + cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_A_M; + cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_A; + cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_A_M; + cr->cca_spoofing = CNT_CCA_SPOOFING_A; + cr->cca_spoofing_m = CNT_CCA_SPOOFING_A_M; + cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_A; + cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_A_M; + cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_A; + cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_A_M; + cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_A; + cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_A_M; + cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_A; + cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_A_M; + cr->brk = CNT_BRK_A; + cr->brk_m = CNT_BRK_A_M; + cr->brk_sel = CNT_BRK_SEL_A; + cr->brk_sel_m = CNT_BRK_SEL_A_M; + cr->rxl_err_parity = CNT_RXL_ERR_PARITY_A; + cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_A_M; + cr->rxl_err_rate = CNT_RXL_ERR_RATE_A; + cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_A_M; + cr->ht_err_crc8 = CNT_HT_ERR_CRC8_A; + cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_A_M; + cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_A; + cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_A_M; + cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_A; + cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_A_M; + cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_A; + cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_A_M; + cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_A; + cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_A_M; + cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_A; + cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_A_M; + cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_A; + cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_A_M; + cr->search_fail = CNT_SEARCH_FAIL_A; + cr->search_fail_m = CNT_SEARCH_FAIL_A_M; + cr->ofdm_cca = CNT_OFDM_CCA_A; + cr->ofdm_cca_m = CNT_OFDM_CCA_A_M; + cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_A; + cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_A_M; + cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_A; + cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_A_M; + cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_A; + cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_A_M; + cr->ccktxon = CNT_CCKTXON_A; + cr->ccktxon_m = CNT_CCKTXON_A_M; + cr->ccktxen = CNT_CCKTXEN_A; + cr->ccktxen_m = CNT_CCKTXEN_A_M; + cr->ofdmtxon = CNT_OFDMTXON_A; + cr->ofdmtxon_m = CNT_OFDMTXON_A_M; + cr->ofdmtxen = CNT_OFDMTXEN_A; + cr->ofdmtxen_m = CNT_OFDMTXEN_A_M; + cr->drop_trig = CNT_DROP_TRIG_A; + cr->drop_trig_m = CNT_DROP_TRIG_A_M; + cr->pop_trig = CNT_POP_TRIG_A; + cr->pop_trig_m = CNT_POP_TRIG_A_M; + cr->tx_conflict = CNT_TX_CONFLICT_A; + cr->tx_conflict_m = CNT_TX_CONFLICT_A_M; + cr->wmac_rstb = CNT_WMAC_RSTB_A; + cr->wmac_rstb_m = CNT_WMAC_RSTB_A_M; + cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_A; + cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_A_M; + cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_A; + cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_A_M; + cr->he_crc_ok = CNT_HE_CRC_OK_A; + cr->he_crc_ok_m = CNT_HE_CRC_OK_A_M; + cr->he_crc_err = CNT_HE_CRC_ERR_A; + cr->he_crc_err_m = CNT_HE_CRC_ERR_A_M; + cr->vht_crc_ok = CNT_VHT_CRC_OK_A; + cr->vht_crc_ok_m = CNT_VHT_CRC_OK_A_M; + cr->vht_crc_err = CNT_VHT_CRC_ERR_A; + cr->vht_crc_err_m = CNT_VHT_CRC_ERR_A_M; + cr->ht_crc_ok = CNT_HT_CRC_OK_A; + cr->ht_crc_ok_m = CNT_HT_CRC_OK_A_M; + cr->ht_crc_err = CNT_HT_CRC_ERR_A; + cr->ht_crc_err_m = CNT_HT_CRC_ERR_A_M; + cr->l_crc_ok = CNT_L_CRC_OK_A; + cr->l_crc_ok_m = CNT_L_CRC_OK_A_M; + cr->l_crc_err = CNT_L_CRC_ERR_A; + cr->l_crc_err_m = CNT_L_CRC_ERR_A_M; + cr->he_crc_ok2 = CNT_HE_CRC_OK2_A; + cr->he_crc_ok2_m = CNT_HE_CRC_OK2_A_M; + cr->he_crc_err2 = CNT_HE_CRC_ERR2_A; + cr->he_crc_err2_m = CNT_HE_CRC_ERR2_A_M; + cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_A; + cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_A_M; + cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_A; + cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_A_M; + cr->ht_crc_ok2 = CNT_HT_CRC_OK2_A; + cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_A_M; + cr->ht_crc_err2 = CNT_HT_CRC_ERR2_A; + cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_A_M; + cr->l_crc_ok2 = CNT_L_CRC_OK2_A; + cr->l_crc_ok2_m = CNT_L_CRC_OK2_A_M; + cr->l_crc_err2 = CNT_L_CRC_ERR2_A; + cr->l_crc_err2_m = CNT_L_CRC_ERR2_A_M; + cr->l_crc_ok3 = CNT_L_CRC_OK3_A; + cr->l_crc_ok3_m = CNT_L_CRC_OK3_A_M; + cr->l_crc_err3 = CNT_L_CRC_ERR3_A; + cr->l_crc_err3_m = CNT_L_CRC_ERR3_A_M; + cr->ampdu_rxon = CNT_AMPDU_RXON_A; + cr->ampdu_rxon_m = CNT_AMPDU_RXON_A_M; + cr->ampdu_miss = CNT_AMPDU_MISS_A; + cr->ampdu_miss_m = CNT_AMPDU_MISS_A_M; + cr->ampdu_crc_ok = CNT_AMPDU_RX_CRC32_OK_A; + cr->ampdu_crc_ok_m = CNT_AMPDU_RX_CRC32_OK_A_M; + cr->ampdu_crc_err = CNT_AMPDU_RX_CRC32_ERR_A; + cr->ampdu_crc_err_m = CNT_AMPDU_RX_CRC32_ERR_A_M; + cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_A; + cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_A_M; + cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_A; + cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_A_M; + cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_A; + cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_A_M; + cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_A; + cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_A_M; + cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_A; + cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_A_M; + cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_A; + cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_A_M; + cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_A; + cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_A_M; + cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_A; + cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_A_M; + cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_A; + cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_A_M; + cr->r1b_rr_sel = R1B_RR_SEL_A; + cr->r1b_rr_sel_m = R1B_RR_SEL_A_M; + cr->rst_all_cnt = RST_ALL_CNT_A; + cr->rst_all_cnt_m = RST_ALL_CNT_A_M; + cr->enable_all_cnt = ENABLE_ALL_CNT_A; + cr->enable_all_cnt_m = ENABLE_ALL_CNT_A_M; + cr->enable_ofdm = ENABLE_OFDM_A; + cr->enable_ofdm_m = ENABLE_OFDM_A_M; + cr->enable_cck = ENABLE_CCK_A; + cr->enable_cck_m = ENABLE_CCK_A_M; + cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_A; + cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_A_M; + cr->intf_r_rate = INTF_R_CNT_RATE_A; + cr->intf_r_rate_m = INTF_R_CNT_RATE_A_M; + cr->intf_r_mcs = INTF_R_CNT_MCS_A; + cr->intf_r_mcs_m = INTF_R_CNT_MCS_A_M; + cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_A; + cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_A_M; + cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_A; + cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_A_M; + cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_A; + cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_A_M; + cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_A; + cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_A_M; + cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_A; + cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_A_M; + cr->intf_r_pkt_type = INTF_R_PKT_TYPE_A; + cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_A_M; + cr->dbcc = DBCC_A; + cr->dbcc_m = DBCC_A_M; + cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_A; + cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_A_M; + cr->cnt_pop_trig = CNT_POP_TRIG_A; + cr->cnt_pop_trig_m = CNT_POP_TRIG_A_M; + cr->max_cnt_pop = MAX_CNT_POP_A; + cr->max_cnt_pop_m = MAX_CNT_POP_A_M; + break; + + #endif + #ifdef HALBB_COMPILE_CLIENT_SERIES + case BB_CLIENT: + cr->cck_cca = CNT_CCK_CCA_P0_C; + cr->cck_cca_m = CNT_CCK_CCA_P0_C_M; + cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_C; + cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_C_M; + cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_C; + cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_C_M; + cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_C; + cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_C_M; + cr->cca_spoofing = CNT_CCA_SPOOFING_C; + cr->cca_spoofing_m = CNT_CCA_SPOOFING_C_M; + cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_C; + cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_C_M; + cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_C; + cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_C_M; + cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_C; + cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_C_M; + cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_C; + cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_C_M; + cr->brk = CNT_BRK_C; + cr->brk_m = CNT_BRK_C_M; + cr->brk_sel = CNT_BRK_SEL_C; + cr->brk_sel_m = CNT_BRK_SEL_C_M; + cr->rxl_err_parity = CNT_RXL_ERR_PARITY_C; + cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_C_M; + cr->rxl_err_rate = CNT_RXL_ERR_RATE_C; + cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_C_M; + cr->ht_err_crc8 = CNT_HT_ERR_CRC8_C; + cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_C_M; + cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_C; + cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_C_M; + cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_C; + cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_C_M; + cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_C; + cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_C_M; + cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_C; + cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_C_M; + cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_C; + cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_C_M; + cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_C; + cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_C_M; + cr->search_fail = CNT_SEARCH_FAIL_C; + cr->search_fail_m = CNT_SEARCH_FAIL_C_M; + cr->ofdm_cca = CNT_OFDM_CCA_C; + cr->ofdm_cca_m = CNT_OFDM_CCA_C_M; + cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_C; + cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_C_M; + cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_C; + cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_C_M; + cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_C; + cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_C_M; + cr->ccktxon = CNT_CCKTXON_C; + cr->ccktxon_m = CNT_CCKTXON_C_M; + cr->ccktxen = CNT_CCKTXEN_C; + cr->ccktxen_m = CNT_CCKTXEN_C_M; + cr->ofdmtxon = CNT_OFDMTXON_C; + cr->ofdmtxon_m = CNT_OFDMTXON_C_M; + cr->ofdmtxen = CNT_OFDMTXEN_C; + cr->ofdmtxen_m = CNT_OFDMTXEN_C_M; + cr->drop_trig = CNT_DROP_TRIG_C; + cr->drop_trig_m = CNT_DROP_TRIG_C_M; + cr->pop_trig = CNT_POP_TRIG_C; + cr->pop_trig_m = CNT_POP_TRIG_C_M; + cr->tx_conflict = CNT_TX_CONFLICT_C; + cr->tx_conflict_m = CNT_TX_CONFLICT_C_M; + cr->wmac_rstb = CNT_WMAC_RSTB_C; + cr->wmac_rstb_m = CNT_WMAC_RSTB_C_M; + cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_C; + cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_C_M; + cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_C; + cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_C_M; + cr->he_crc_ok = CNT_HE_CRC_OK_C; + cr->he_crc_ok_m = CNT_HE_CRC_OK_C_M; + cr->he_crc_err = CNT_HE_CRC_ERR_C; + cr->he_crc_err_m = CNT_HE_CRC_ERR_C_M; + cr->vht_crc_ok = CNT_VHT_CRC_OK_C; + cr->vht_crc_ok_m = CNT_VHT_CRC_OK_C_M; + cr->vht_crc_err = CNT_VHT_CRC_ERR_C; + cr->vht_crc_err_m = CNT_VHT_CRC_ERR_C_M; + cr->ht_crc_ok = CNT_HT_CRC_OK_C; + cr->ht_crc_ok_m = CNT_HT_CRC_OK_C_M; + cr->ht_crc_err = CNT_HT_CRC_ERR_C; + cr->ht_crc_err_m = CNT_HT_CRC_ERR_C_M; + cr->l_crc_ok = CNT_L_CRC_OK_C; + cr->l_crc_ok_m = CNT_L_CRC_OK_C_M; + cr->l_crc_err = CNT_L_CRC_ERR_C; + cr->l_crc_err_m = CNT_L_CRC_ERR_C_M; + cr->he_crc_ok2 = CNT_HE_CRC_OK2_C; + cr->he_crc_ok2_m = CNT_HE_CRC_OK2_C_M; + cr->he_crc_err2 = CNT_HE_CRC_ERR2_C; + cr->he_crc_err2_m = CNT_HE_CRC_ERR2_C_M; + cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_C; + cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_C_M; + cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_C; + cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_C_M; + cr->ht_crc_ok2 = CNT_HT_CRC_OK2_C; + cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_C_M; + cr->ht_crc_err2 = CNT_HT_CRC_ERR2_C; + cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_C_M; + cr->l_crc_ok2 = CNT_L_CRC_OK2_C; + cr->l_crc_ok2_m = CNT_L_CRC_OK2_C_M; + cr->l_crc_err2 = CNT_L_CRC_ERR2_C; + cr->l_crc_err2_m = CNT_L_CRC_ERR2_C_M; + cr->l_crc_ok3 = CNT_L_CRC_OK3_C; + cr->l_crc_ok3_m = CNT_L_CRC_OK3_C_M; + cr->l_crc_err3 = CNT_L_CRC_ERR3_C; + cr->l_crc_err3_m = CNT_L_CRC_ERR3_C_M; + cr->ampdu_rxon = CNT_AMPDU_RXON_C; + cr->ampdu_rxon_m = CNT_AMPDU_RXON_C_M; + cr->ampdu_miss = CNT_AMPDU_MISS_C; + cr->ampdu_miss_m = CNT_AMPDU_MISS_C_M; + cr->ampdu_crc_ok = CNT_AMPDU_RX_CRC32_OK_C; + cr->ampdu_crc_ok_m = CNT_AMPDU_RX_CRC32_OK_C_M; + cr->ampdu_crc_err = CNT_AMPDU_RX_CRC32_ERR_C; + cr->ampdu_crc_err_m = CNT_AMPDU_RX_CRC32_ERR_C_M; + cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_C; + cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_C_M; + cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_C; + cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_C_M; + cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_C; + cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_C_M; + cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C; + cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C_M; + cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C; + cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C_M; + cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_C; + cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_C_M; + cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_C; + cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_C_M; + cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_C; + cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_C_M; + cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_C; + cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_C_M; + cr->r1b_rr_sel = R1B_RR_SEL_C; + cr->r1b_rr_sel_m = R1B_RR_SEL_C_M; + cr->rst_all_cnt = RST_ALL_CNT_C; + cr->rst_all_cnt_m = RST_ALL_CNT_C_M; + cr->enable_all_cnt = ENABLE_ALL_CNT_C; + cr->enable_all_cnt_m = ENABLE_ALL_CNT_C_M; + cr->enable_ofdm = ENABLE_OFDM_C; + cr->enable_ofdm_m = ENABLE_OFDM_C_M; + cr->enable_cck = ENABLE_CCK_C; + cr->enable_cck_m = ENABLE_CCK_C_M; + cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_C; + cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_C_M; + cr->intf_r_rate = INTF_R_CNT_RATE_C; + cr->intf_r_rate_m = INTF_R_CNT_RATE_C_M; + cr->intf_r_mcs = INTF_R_CNT_MCS_C; + cr->intf_r_mcs_m = INTF_R_CNT_MCS_C_M; + cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_C; + cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_C_M; + cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_C; + cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_C_M; + cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_C; + cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_C_M; + cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_C; + cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_C_M; + cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_C; + cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_C_M; + cr->intf_r_pkt_type = INTF_R_PKT_TYPE_C; + cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_C_M; + cr->dbcc = DBCC_C; + cr->dbcc_m = DBCC_C_M; + cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_C; + cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_C_M; + cr->cnt_pop_trig = CNT_POP_TRIG_C; + cr->cnt_pop_trig_m = CNT_POP_TRIG_C_M; + cr->max_cnt_pop = MAX_CNT_POP_C; + cr->max_cnt_pop_m = MAX_CNT_POP_C_M; + break; + #endif + default: + break; + } + +} + +#endif diff --git a/phl/hal_g6/phy/bb/halbb_statistics.h b/phl/hal_g6/phy/bb/halbb_statistics.h new file mode 100644 index 0000000..3439457 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_statistics.h @@ -0,0 +1,385 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_STATISTICS_H__ +#define __HALBB_STATISTICS_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define CHK_HANG_L_SIG_TH 3 +#define HANG_RECOVERY true // Disable auto-recovery mechanism for 52A CBV +#define HANG_LIMIT 1 + +/*@--------------------------[Enum]------------------------------------------*/ +enum stat_type_sel { + STATE_PROBE_RESP = 1, + STATE_BEACON = 2, + STATE_ACTION = 3, + STATE_BFRP = 4, + STATE_NDPA = 5, + STATE_BA = 6, + STATE_RTS = 7, + STATE_CTS = 8, + STATE_ACK = 9, + STATE_DATA = 10, + STATE_NULL = 11, + STATE_QOS = 12, +}; + +enum stat_mac_type { + TYPE_PROBE_RESP = 0x05, + TYPE_BEACON = 0x08, + TYPE_ACTION = 0x0d, + TYPE_BFRP = 0x14, + TYPE_NDPA = 0x15, + TYPE_BA = 0x19, + TYPE_RTS = 0x1b, + TYPE_CTS = 0x1c, + TYPE_ACK = 0x1d, + TYPE_DATA = 0x20, + TYPE_NULL = 0x24, + TYPE_QOS = 0x28, +}; + +/*@--------------------------[Structure]-------------------------------------*/ +struct bb_usr_set_info { + u16 ofdm2_rate_idx; + u16 ht2_rate_idx; + u16 vht2_rate_idx; + u16 he2_rate_idx; + enum stat_mac_type stat_mac_type_i; + enum stat_type_sel stat_type_sel_i; +}; + +struct bb_cca_info { + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_cck_spoofing; + u32 cnt_ofdm_spoofing; + u32 cnt_cca_spoofing_all; + u32 pop_cnt; +}; + +struct bb_crc_info { + u32 cnt_ampdu_miss; + u32 cnt_ampdu_crc_error; + u32 cnt_ampdu_crc_ok; + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_he_crc32_ok; + u32 cnt_he_crc32_error; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; +}; + +struct bb_crc2_info { + u32 cnt_ofdm2_crc32_error; + u32 cnt_ofdm2_crc32_ok; + u8 ofdm2_pcr; + u32 cnt_ht2_crc32_error; + u32 cnt_ht2_crc32_ok; + u8 ht2_pcr; + u32 cnt_vht2_crc32_error; + u32 cnt_vht2_crc32_ok; + u8 vht2_pcr; + u32 cnt_he2_crc32_error; + u32 cnt_he2_crc32_ok; + u8 he2_pcr; + u32 cnt_ofdm3_crc32_error; + u32 cnt_ofdm3_crc32_ok; +}; + +struct bb_cck_fa_info { + u32 sfd_gg_cnt; + u32 sig_gg_cnt; + u32 cnt_cck_crc_16; +}; + +struct bb_legacy_fa_info { + u32 cnt_lsig_brk_s_th; + u32 cnt_lsig_brk_l_th; + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_sb_search_fail; +}; + +struct bb_ht_fa_info { + u32 cnt_crc8_fail; + u32 cnt_crc8_fail_s_th; + u32 cnt_crc8_fail_l_th; + u32 cnt_mcs_fail; +}; + +struct bb_vht_fa_info { + u32 cnt_crc8_fail_vhta; + /*u32 cnt_crc8_fail_vhtb; removed at RXD*/ + u32 cnt_mcs_fail_vht; +}; + +struct bb_he_fa_info { + u32 cnt_crc4_fail_hea_su; + u32 cnt_crc4_fail_hea_ersu; + u32 cnt_crc4_fail_hea_mu; + u32 cnt_crc4_fail_heb_ch1_mu; + u32 cnt_crc4_fail_heb_ch2_mu; + u32 cnt_mcs_fail_he_bcc; + u32 cnt_mcs_fail_he; + u32 cnt_mcs_fail_he_dcm; +}; + +struct bb_fa_info { + u32 cnt_total_brk; + u32 cnt_cck_fail; + u32 cnt_ofdm_fail; + u32 cnt_fail_all; + struct bb_cck_fa_info bb_cck_fa_i; + struct bb_legacy_fa_info bb_legacy_fa_i; + struct bb_ht_fa_info bb_ht_fa_i; + struct bb_vht_fa_info bb_vht_fa_i; + struct bb_he_fa_info bb_he_fa_i; +}; + +struct bb_tx_cnt_info { + u32 cck_mac_txen; + u32 cck_phy_txon; + u32 ofdm_mac_txen; + u32 ofdm_phy_txon; +}; + +struct bb_stat_cr_info { + u32 cck_cca; + u32 cck_cca_m; + u32 cck_crc16fail; + u32 cck_crc16fail_m; + u32 cck_crc32ok; + u32 cck_crc32ok_m; + u32 cck_crc32fail; + u32 cck_crc32fail_m; + u32 cca_spoofing; + u32 cca_spoofing_m; + u32 lsig_brk_s_th; + u32 lsig_brk_s_th_m; + u32 lsig_brk_l_th; + u32 lsig_brk_l_th_m; + u32 htsig_crc8_err_s_th; + u32 htsig_crc8_err_s_th_m; + u32 htsig_crc8_err_l_th; + u32 htsig_crc8_err_l_th_m; + u32 brk; + u32 brk_m; + u32 brk_sel; + u32 brk_sel_m; + u32 rxl_err_parity; + u32 rxl_err_parity_m; + u32 rxl_err_rate; + u32 rxl_err_rate_m; + u32 ht_err_crc8; + u32 ht_err_crc8_m; + u32 vht_err_siga_crc8; + u32 vht_err_siga_crc8_m; + u32 ht_not_support_mcs; + u32 ht_not_support_mcs_m; + u32 vht_not_support_mcs; + u32 vht_not_support_mcs_m; + u32 err_during_bt_tx; + u32 err_during_bt_tx_m; + u32 err_during_bt_rx; + u32 err_during_bt_rx_m; + u32 edge_murx_nsts0; + u32 edge_murx_nsts0_m; + u32 search_fail; + u32 search_fail_m; + u32 ofdm_cca; + u32 ofdm_cca_m; + u32 ofdm_cca_s20; + u32 ofdm_cca_s20_m; + u32 ofdm_cca_s40; + u32 ofdm_cca_s40_m; + u32 ofdm_cca_s80; + u32 ofdm_cca_s80_m; + u32 ccktxen; + u32 ccktxen_m; + u32 ccktxon; + u32 ccktxon_m; + u32 ofdmtxon; + u32 ofdmtxon_m; + u32 ofdmtxen; + u32 ofdmtxen_m; + u32 drop_trig; + u32 drop_trig_m; + u32 pop_trig; + u32 pop_trig_m; + u32 tx_conflict; + u32 tx_conflict_m; + u32 wmac_rstb; + u32 wmac_rstb_m; + u32 en_tb_ppdu_fix_gain; + u32 en_tb_ppdu_fix_gain_m; + u32 en_tb_cca_pw_th; + u32 en_tb_cca_pw_th_m; + u32 he_crc_ok; + u32 he_crc_ok_m; + u32 he_crc_err; + u32 he_crc_err_m; + u32 vht_crc_ok; + u32 vht_crc_ok_m; + u32 vht_crc_err; + u32 vht_crc_err_m; + u32 ht_crc_ok; + u32 ht_crc_ok_m; + u32 ht_crc_err; + u32 ht_crc_err_m; + u32 l_crc_ok; + u32 l_crc_ok_m; + u32 l_crc_err; + u32 l_crc_err_m; + u32 he_crc_ok2; + u32 he_crc_ok2_m; + u32 he_crc_err2; + u32 he_crc_err2_m; + u32 vht_crc_ok2; + u32 vht_crc_ok2_m; + u32 vht_crc_err2; + u32 vht_crc_err2_m; + u32 ht_crc_ok2; + u32 ht_crc_ok2_m; + u32 ht_crc_err2; + u32 ht_crc_err2_m; + u32 l_crc_ok2; + u32 l_crc_ok2_m; + u32 l_crc_err2; + u32 l_crc_err2_m; + u32 l_crc_ok3; + u32 l_crc_ok3_m; + u32 l_crc_err3; + u32 l_crc_err3_m; + u32 ampdu_rxon; + u32 ampdu_rxon_m; + u32 ampdu_miss; + u32 ampdu_miss_m; + u32 ampdu_crc_ok; + u32 ampdu_crc_ok_m; + u32 ampdu_crc_err; + u32 ampdu_crc_err_m; + u32 hesu_err_sig_a_crc4; + u32 hesu_err_sig_a_crc4_m; + u32 heersu_err_sig_a_crc4; + u32 heersu_err_sig_a_crc4_m; + u32 hemu_err_sig_a_crc4; + u32 hemu_err_sig_a_crc4_m; + u32 hemu_err_sigb_ch1_comm_crc4; + u32 hemu_err_sigb_ch1_comm_crc4_m; + u32 hemu_err_sigb_ch2_comm_crc4; + u32 hemu_err_sigb_ch2_comm_crc4_m; + u32 he_u0_err_bcc_mcs; + u32 he_u0_err_bcc_mcs_m; + u32 he_u0_err_mcs; + u32 he_u0_err_mcs_m; + u32 he_u0_err_dcm_mcs; + u32 he_u0_err_dcm_mcs_m; + u32 r1b_rx_rpt_rst; + u32 r1b_rx_rpt_rst_m; + u32 r1b_rr_sel; + u32 r1b_rr_sel_m; + u32 rst_all_cnt; + u32 rst_all_cnt_m; + u32 enable_all_cnt; + u32 enable_all_cnt_m; + u32 enable_ofdm; + u32 enable_ofdm_m; + u32 enable_cck; + u32 enable_cck_m; + u32 r1b_rx_dis_cca; + u32 r1b_rx_dis_cca_m; + u32 intf_r_rate; + u32 intf_r_rate_m; + u32 intf_r_mcs; + u32 intf_r_mcs_m; + u32 intf_r_vht_mcs; + u32 intf_r_vht_mcs_m; + u32 intf_r_he_mcs; + u32 intf_r_he_mcs_m; + u32 intf_r_vht_nss; + u32 intf_r_vht_nss_m; + u32 intf_r_he_nss; + u32 intf_r_he_nss_m; + u32 intf_r_mac_hdr_type; + u32 intf_r_mac_hdr_type_m; + u32 intf_r_pkt_type; + u32 intf_r_pkt_type_m; + u32 dbcc; + u32 dbcc_m; + u32 dbcc_2p4g_band_sel; + u32 dbcc_2p4g_band_sel_m; + u32 cnt_pop_trig; + u32 cnt_pop_trig_m; + u32 max_cnt_pop; + u32 max_cnt_pop_m; +}; + +struct bb_stat_info { + struct bb_stat_cr_info bb_stat_cr_i; + u32 cnt_bw_usc; + u32 cnt_bw_lsc; + u32 time_fa_all; + u32 dbg_port0; + u32 chk_hang_cnt; + u8 chk_hang_limit; + bool hang_recovery_en; + bool cck_block_enable; + bool ofdm_block_enable; + struct bb_tx_cnt_info bb_tx_cnt_i; + struct bb_cca_info bb_cca_i; + struct bb_crc_info bb_crc_i; + struct bb_crc2_info bb_crc2_i; + struct bb_fa_info bb_fa_i; + struct bb_usr_set_info bb_usr_set_i; +}; + +struct bb_info; +/*@--------------------------[Prptotype]-------------------------------------*/ + +void halbb_chk_hang(struct bb_info *bb); +void halbb_print_cnt3(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_print_cnt2(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_print_cnt(struct bb_info *bb, bool cck_enable, enum phl_phy_idx phy_idx, enum phl_phy_idx phy_idx_2); +void halbb_cnt_reg_reset(struct bb_info *bb); +void halbb_set_crc32_cnt2_rate(struct bb_info *bb, u16 rate_idx); +void halbb_set_crc32_cnt3_format(struct bb_info *bb, u8 usr_type_sel); +void halbb_crc32_cnt_dbg(struct bb_info *bb, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halbb_cck_cnt_statistics(struct bb_info *bb); +void halbb_ofdm_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx); +void halbb_statistics_reset(struct bb_info *bb); +void halbb_statistics(struct bb_info *bb); +void halbb_statistics_init(struct bb_info *bb); +void halbb_cr_cfg_stat_init(struct bb_info *bb); +#endif + diff --git a/phl/hal_g6/phy/bb/halbb_types.h b/phl/hal_g6/phy/bb/halbb_types.h new file mode 100644 index 0000000..f777b19 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_types.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_TYPES_H__ +#define __HALBB_TYPES_H__ + /*@--------------------------[Define] ---------------------------------------*/ +#define HALBB_CONFIG_RUN_IN_DRV + +/*For FW API*/ +#define __iram_func__ + +#endif /* __HALBB_TYPES_H__ */ diff --git a/phl/hal_g6/phy/bb/halbb_wpp.h b/phl/hal_g6/phy/bb/halbb_wpp.h new file mode 100644 index 0000000..e995799 --- /dev/null +++ b/phl/hal_g6/phy/bb/halbb_wpp.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALBB_WPP_H__ +#define __HALBB_WPP_H__ + +#define HALBB_WPP_CONTROL_GUIDS \ + WPP_DEFINE_CONTROL_GUID( \ + HalbbGuid, (111AA0F8,4BB9,4C05,BE3E,03383B8CD916), \ + WPP_DEFINE_BIT(DBG_RA) \ + WPP_DEFINE_BIT(DBG_FA_CNT) \ + WPP_DEFINE_BIT(HALBB_FUN_RSVD_2) \ + WPP_DEFINE_BIT(DBG_DFS) \ + WPP_DEFINE_BIT(DBG_EDCCA)\ + WPP_DEFINE_BIT(DBG_ENV_MNTR)\ + WPP_DEFINE_BIT(DBG_CFO_TRK)\ + WPP_DEFINE_BIT(DBG_PWR_CTRL)\ + WPP_DEFINE_BIT(DBG_RUA_TBL)\ + WPP_DEFINE_BIT(DBG_AUTO_DBG)\ + WPP_DEFINE_BIT(DBG_ANT_DIV)\ + WPP_DEFINE_BIT(DBG_DIG)\ + WPP_DEFINE_BIT(DBG_BIT12)\ + WPP_DEFINE_BIT(DBG_BIT13)\ + WPP_DEFINE_BIT(DBG_BIT14)\ + WPP_DEFINE_BIT(DBG_BIT15)\ + WPP_DEFINE_BIT(DBG_BIT16)\ + WPP_DEFINE_BIT(DBG_BIT17)\ + WPP_DEFINE_BIT(DBG_BIT18)\ + WPP_DEFINE_BIT(DBG_BIT19)\ + WPP_DEFINE_BIT(DBG_PHY_STS)\ + WPP_DEFINE_BIT(DBG_BIT21)\ + WPP_DEFINE_BIT(DBG_FW_INFO)\ + WPP_DEFINE_BIT(DBG_COMMON_FLOW)\ + WPP_DEFINE_BIT(DBG_IC_API)\ + WPP_DEFINE_BIT(DBG_DBG_API)\ + WPP_DEFINE_BIT(DBG_DBCC)\ + WPP_DEFINE_BIT(DBG_DM_SUMMARY)\ + WPP_DEFINE_BIT(DBG_PHY_CONFIG)\ + WPP_DEFINE_BIT(DBG_INIT)\ + WPP_DEFINE_BIT(DBG_CMN)\ + WPP_DEFINE_BIT(DBG_DCR)\ + ) +#endif /* __HALBB_TYPES_H__ */ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf.c b/phl/hal_g6/phy/rf/halrf.c new file mode 100644 index 0000000..698e2fd --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf.c @@ -0,0 +1,2398 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halrf_precomp.h" + +#if 1 + +enum rtw_hal_status halrf_chl_rfk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + u32 start_time, finish_time; + + #if 0 + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + start_time = _os_get_cur_time_us(); + + /*[RX Gain K]*/ + halrf_do_rx_gain_k(rf, phy_idx); + + /*[TX GAP K]*/ + halrf_gapk_trigger(rf, phy_idx, true); + + /*[RX dck]*/ + halrf_rx_dck_trigger(rf, phy_idx, true); + + /*[LOK, IQK]*/ + halrf_iqk_trigger(rf, phy_idx, force); + + /*[TSSI Trk]*/ + halrf_tssi_trigger(rf, phy_idx); + + /*[DPK]*/ + halrf_dpk_trigger(rf, phy_idx, force); + halrf_fw_ntfy(rf, phy_idx); + RF_WARNING("===>%s\n", __func__); + halrf_lck_check_8852b(rf); + finish_time = _os_get_cur_time_us(); + RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] halrf_chl_rfk_trigger processing time = %d.%dms\n", + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + return RTW_HAL_STATUS_SUCCESS; +} + +void halrf_dack_recover(void *rf_void, + u8 offset, + enum rf_path path, + u32 val, + bool reload) +{ + + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + #if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + if (hal_i->cv == CAV) + halrf_dack_recover_8852a(rf, offset, path, val, reload); + break; +#endif + default: + break; + } +} + +enum rtw_hal_status halrf_dack_trigger(void *rf_void, bool force) +{ + + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dack_info *dack = &rf->dack; + u32 start_time, finish_time; + + #if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + if (!(rf->support_ability & HAL_RF_DACK)) + return RTW_HAL_STATUS_SUCCESS; + + halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_DACK, RFK_START); + start_time = _os_get_cur_time_us(); + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + if (hal_i->cv == CAV) + halrf_dac_cal_8852a(rf, force); + else + halrf_dac_cal_8852a_b(rf, force); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_dac_cal_8852b(rf, force); + break; +#endif + default: + break; + } + finish_time = _os_get_cur_time_us(); + halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_DACK, RFK_STOP); + dack->dack_time = HALRF_ABS(finish_time, start_time) / 1000; + RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] DACK processing time = %d.%dms\n", + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_rx_dck_trigger(void *rf_void, + enum phl_phy_idx phy_idx, bool is_afe) +{ + + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + u32 start_time, finish_time; + #if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + if (!(rf->support_ability & HAL_RF_RXDCK)) + return RTW_HAL_STATUS_SUCCESS; + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_START); + + halrf_tmac_tx_pause(rf, phy_idx, true); + +#if 0 + for (i = 0; i < 2000; i++) + halrf_delay_us(rf, 10); /*delay 20ms*/ +#endif + + start_time = _os_get_cur_time_us(); + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_rx_dck_8852a(rf, phy_idx, is_afe); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_rx_dck_8852b(rf, phy_idx, false); + break; +#endif + + default: + break; + } + + halrf_tmac_tx_pause(rf, phy_idx, false); + + finish_time = _os_get_cur_time_us(); + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_STOP); + + RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] RX_DCK processing time = %d.%dms\n", + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_iqk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 start_time, finish_time; + + #if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + if (!(rf->support_ability & HAL_RF_IQK)) + return RTW_HAL_STATUS_SUCCESS; + rf->rfk_is_processing = true; + start_time = _os_get_cur_time_us(); + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_IQK, RFK_START); + + halrf_tmac_tx_pause(rf, phy_idx, true); + + halrf_iqk_init(rf); + halrf_iqk(rf, phy_idx, force); + + halrf_tmac_tx_pause(rf, phy_idx, false); + rf->rfk_is_processing = false; + finish_time = _os_get_cur_time_us(); + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_IQK, RFK_STOP); + RF_DBG(rf, DBG_RF_IQK, "[IQK] IQK processing time = %d.%dms\n", + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + + return RTW_HAL_STATUS_SUCCESS; +} + +void halrf_lck_trigger(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + #if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; + #endif + + if (!(rf->support_ability & HAL_RF_LCK)) + return; + +#if 0 + while (*dm->is_scan_in_process) { + RF_DBG(dm, DBG_RF_IQK, "[LCK]scan is in process, bypass LCK\n"); + return; + } +#endif + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + break; +#endif + default: + break; + } + + +} + +enum rtw_hal_status halrf_dpk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + u32 start_time, finish_time; +#if 0 + if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) & + (hal_i->is_con_tx || + hal_i->is_single_tone || + hal_i->is_carrier_suppresion)) + return; + + if (hal_i->rfk_forbidden) + return; +#endif + + if (!(rf->support_ability & HAL_RF_DPK) || rf->phl_com->id.id == 0x1010a) /*USB buffalo*/ + return RTW_HAL_STATUS_SUCCESS; + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_DPK, RFK_START); + + halrf_tmac_tx_pause(rf, phy_idx, true); + + rf->rfk_is_processing = true; + + start_time = _os_get_cur_time_us(); + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_dpk_8852a(rf, phy_idx, force); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_dpk_8852b(rf, phy_idx, force); + break; +#endif + default: + break; + } + + rf->rfk_is_processing = false; + + finish_time = _os_get_cur_time_us(); + + halrf_tmac_tx_pause(rf, phy_idx, false); + + halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_DPK, RFK_STOP); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] DPK processing time = %d.%dms\n", + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_dpk_tracking(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dpk_info *dpk = &rf->dpk; + + if (!(rf->support_ability & HAL_RF_DPK_TRACK) || rf->rfk_is_processing || + rf->is_watchdog_stop || rf->psd.psd_progress) + return RTW_HAL_STATUS_SUCCESS; + + rf->is_watchdog_stop = true; /*avoid race condition*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_dpk_track_8852a(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_dpk_track_8852b(rf); + break; +#endif + default: + break; + } + + rf->is_watchdog_stop = false; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_tssi_tracking(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK)) + || rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress) + return RTW_HAL_STATUS_SUCCESS; + + rf->is_watchdog_stop = true; /*avoid race condition*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_tracking_8852a(rf); + break; +#endif + default: + break; + } + + rf->is_watchdog_stop = false; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_tssi_tracking_clean(void *rf_void, s16 power_dbm) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK)) + || rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress) + return RTW_HAL_STATUS_SUCCESS; + + rf->is_watchdog_stop = true; /*avoid race condition*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_tracking_clean_8852ab(rf, power_dbm); + break; +#endif + default: + break; + } + + rf->is_watchdog_stop = false; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_tssi_ant_open(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK)) + || rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress) + return RTW_HAL_STATUS_SUCCESS; + + rf->is_watchdog_stop = true; /*avoid race condition*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_ant_open_8852a(rf); + break; +#endif + default: + break; + } + + rf->is_watchdog_stop = false; + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 start_time, finish_time; + + start_time = _os_get_cur_time_us(); + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) { + if (tssi_info->tssi_type == TSSI_OFF ) { + rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK; + } + } + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) { + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_disable_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_disable_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + + return RTW_HAL_STATUS_SUCCESS; + } + + rf->rfk_is_processing = true; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_do_tssi_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_do_tssi_8852b(rf, phy_idx); + break; +#endif + default: + break; + } + + rf->rfk_is_processing = false; + + finish_time = _os_get_cur_time_us(); + RF_DBG(rf, DBG_RF_RFK, "[TSSI] %s processing time = %d.%dms\n", + __func__, + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + + return RTW_HAL_STATUS_SUCCESS; +} + +void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 start_time, finish_time; + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) + return; + + start_time = _os_get_cur_time_us(); + + rf->rfk_is_processing = true; + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_do_tssi_scan_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_do_tssi_scan_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + rf->rfk_is_processing = false; + + finish_time = _os_get_cur_time_us(); + + RF_DBG(rf, DBG_RF_RFK, "[TSSI] %s processing time = %d.%dms\n", + __func__, + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); +} + +void halrf_tssi_set_avg(void *rf_void, + enum phl_phy_idx phy_idx, bool enable) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) + return; + + rf->rfk_is_processing = true; + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_set_avg_8852ab(rf, phy_idx, enable); + break; +#endif + default: + break; + } + rf->rfk_is_processing = false; +} + +void halrf_tssi_default_txagc(void *rf_void, + enum phl_phy_idx phy_idx, bool enable) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) + return; + + rf->rfk_is_processing = true; + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_default_txagc_8852ab(rf, phy_idx, enable); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_default_txagc_8852b(rf, phy_idx, enable); + break; +#endif + + default: + break; + } + rf->rfk_is_processing = false; +} + +void halrf_tssi_set_efuse_to_de(void *rf_void, + enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) + return; + + rf->rfk_is_processing = true; + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_set_efuse_to_de_8852ab(rf, phy_idx); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_set_efuse_to_de_8852b(rf, phy_idx); + break; +#endif + default: + break; + } + rf->rfk_is_processing = false; +} + +void halrf_tssi_scan_ch(void *rf_void, enum rf_path path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) + return; + + rf->rfk_is_processing = true; + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_scan_ch_8852ab(rf, path); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_scan_ch_8852b(rf, path); + break; +#endif + default: + break; + } + rf->rfk_is_processing = false; +} + +void halrf_hw_tx(void *rf_void, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw, + bool enable) + +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_hw_tx_8852a(rf, HW_PHY_0, path, cnt, dbm, T_HT_MF, 0, enable); + break; +#endif + default: + break; + } +} + +void halrf_txgapk_init(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + //halrf_txgapk_init_8852a(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_txgapk_init_8852b(rf); + break; +#endif + default: + break; + } +} + +enum rtw_hal_status halrf_gapk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + u32 start_time, finish_time; + if (!(rf->support_ability & HAL_RF_TXGAPK)) + return RTW_HAL_STATUS_SUCCESS; + + rf->rfk_is_processing = true; + + start_time = _os_get_cur_time_us(); + + halrf_txgapk_init(rf); + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_do_txgapk_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_do_txgapk_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + + rf->rfk_is_processing = false; + + finish_time = _os_get_cur_time_us(); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] %s processing time = %d.%dms\n", + __func__, + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status halrf_gapk_enable(void *rf_void, + enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + rf->rfk_is_processing = true; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_txgapk_enable_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_txgapk_enable_8852b(rf, phy_idx); + break; +#endif + default: + break; + } + + rf->rfk_is_processing = false; + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status halrf_gapk_disable(void *rf_void, + enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + rf->rfk_is_processing = true; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_txgapk_write_table_default_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_txgapk_write_table_default_8852b(rf, phy_idx); + break; +#endif + default: + break; + } + + rf->rfk_is_processing = false; + + return RTW_HAL_STATUS_SUCCESS; +} + + +void halrf_rck_trigger(void *rf_void, + enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + u8 path = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + for (path = 0; path < 2; path++) + halrf_rck_8852a(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + for (path = 0; path < 2; path++) + halrf_rck_8852b(rf, path); + break; +#endif + default: + break; + } +} + +void halrf_gapk_save_tx_gain(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + //halrf_gapk_save_tx_gain_8852a(rf); + break; +#endif + default: + break; + } +} + +void halrf_gapk_reload_tx_gain(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + //halrf_gapk_reload_tx_gain_8852a(rf); + break; +#endif + default: + break; + } +} + + + +void halrf_lo_test(void *rf_void, bool is_on, enum rf_path path) +{ + + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; +#if 0 + if (hal_i->is_mp_mode && + hal_i->is_con_tx && + hal_i->is_single_tone && + hal_i->is_carrier_suppresion) + return; + + if (hal_i->rfk_forbidden) + return; +#endif + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_lo_test_8852a(rf, is_on, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_lo_test_8852b(rf, is_on, path); + break; +#endif + default: + break; + } +} + +void halrf_iqk_onoff(void *rf_void, bool is_enable) +{ + /*signal go throughput iqk or not*/ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u8 path = 0x0; + + if (!(rf->support_ability & HAL_RF_DPK)) + return; + + rf->rfk_is_processing = true; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_onoff_8852ab(rf, is_enable); + break; +#endif + default: + break; + } + rf->rfk_is_processing = false; + +} + +void halrf_dpk_onoff(void *rf_void, bool is_enable) +{ + /*signal go throughput dpk or not*/ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 path = 0; +#if 0 + if (hal_i->is_mp_mode && + hal_i->is_con_tx && + hal_i->is_single_tone && + hal_i->is_carrier_suppresion) + return; + + if (hal_i->rfk_forbidden) + return; +#endif + if (!(rf->support_ability & HAL_RF_DPK)) + return; + + rf->rfk_is_processing = true; + + dpk->is_dpk_enable = is_enable; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + for (path = 0; path < 2; path++) + halrf_dpk_onoff_8852a(rf, path, false); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + for (path = 0; path < 2; path++) + halrf_dpk_onoff_8852b(rf, path, false); + break; +#endif + default: + break; + } + rf->rfk_is_processing = false; +} + +void halrf_dpk_track_onoff(void *rf_void, bool is_enable) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + if (is_enable) + rf->support_ability = rf->support_ability | HAL_RF_DPK_TRACK; + else + rf->support_ability = rf->support_ability & ~HAL_RF_DPK_TRACK; +} + +void halrf_dpk_switch(void *rf_void, bool is_enable) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + if (is_enable) { + halrf_dpk_onoff(rf, true); + halrf_dpk_trigger(rf, HW_PHY_0, true); + halrf_dpk_track_onoff(rf, true); + halrf_wl_tx_power_control(rf, 0xffffeeee); + } else { + halrf_wl_tx_power_control(rf, 0xffff8034); + halrf_dpk_track_onoff(rf, false); + halrf_dpk_onoff(rf, false); + } +} + +void halrf_dpk_init(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 path, idx; + + for (path = 0; path < KPATH; path++) { + dpk->cur_idx[path] = 0; + for (idx = 0; idx < DPK_BKUP_NUM; idx++) { + dpk->bp[path][idx].band = 0; + dpk->bp[path][idx].bw = 0; + dpk->bp[path][idx].ch = 0; + dpk->bp[path][idx].path_ok = 0; + dpk->bp[path][idx].txagc_dpk = 0; + dpk->bp[path][idx].ther_dpk = 0; + dpk->bp[path][idx].gs = 0; + dpk->bp[path][idx].pwsf = 0; + } + } + + dpk->is_dpk_enable = true; + dpk->is_dpk_reload_en = false; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_dpk_init_8852a(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_dpk_init_8852b(rf); + break; +#endif + default: + break; + } +} + +void halrf_rx_dck_onoff(void *rf_void, bool is_enable) +{ + /*signal go throughput dpk or not*/ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; +#if 0 + if (hal_i->is_mp_mode && + hal_i->is_con_tx && + hal_i->is_single_tone && + hal_i->is_carrier_suppresion) + return; + + if (hal_i->rfk_forbidden) + return; +#endif + if (!(rf->support_ability & HAL_RF_RXDCK)) + return; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_rx_dck_onoff_8852a(rf, is_enable); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_rx_dck_onoff_8852b(rf, is_enable); + break; +#endif + default: + break; + } +} + +void halrf_gapk_onoff(void *rf_void, bool is_enable) +{ + /*parameter to default or not*/ + +} + +void halrf_dack_onoff(void *rf_void, bool is_enable) +{ + /*parameter to default or not*/ + +} + +void halrf_tssi_onoff(void *rf_void, bool is_enable) +{ + /*parameter to default or not*/ + +} + +bool halrf_get_iqk_onoff(void *rf_void) +{ + return 1; +} + +bool halrf_get_dpk_onoff(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_dpk_info *dpk = &rf->dpk; + + return dpk->is_dpk_enable; +} + +bool halrf_get_dpk_track_onoff(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + if (rf->support_ability & HAL_RF_DPK_TRACK) + return 1; + else + return 0; +} + +bool halrf_get_gapk_onoff(void *rf_void) +{ + return 1; +} +bool halrf_get_dack_onoff(void *rf_void) +{ + return 1; +} +bool halrf_get_tssi_onoff(void *rf_void) +{ + return 1; +} + +u8 halrf_get_thermal(void *rf_void, u8 rf_path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_thermal_8852a(rf, rf_path); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_get_thermal_8852b(rf, rf_path); +#endif + + return 0; + +} + +u32 halrf_get_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path) +{ + return 0; +} + +s32 halrf_get_online_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path, s32 dbm, s32 puot) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + s32 tmp = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + tmp = halrf_get_online_tssi_de_8852a(rf, phy_idx, path, dbm, puot); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + tmp = halrf_get_online_tssi_de_8852b(rf, phy_idx, path, dbm, puot); + break; +#endif + + default: + break; + } + + return tmp; +} + +void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_enable_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_enable_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } +} + +void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_disable_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_disable_8852b(rf, phy_idx); + break; +#endif + default: + break; + } +} + +s8 halrf_get_ther_protected_threshold(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + return halrf_get_ther_protected_threshold_8852a(rf); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + return halrf_get_ther_protected_threshold_8852b(rf); + break; +#endif + + default: + break; + } + + return 0; +} + +void halrf_set_tssi_de_for_tx_verify(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_tssi_de_for_tx_verify_8852a(rf, phy_idx, tssi_de, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_set_tssi_de_for_tx_verify_8852b(rf, phy_idx, tssi_de, path); + break; +#endif + + default: + break; + } +} + +u32 halrf_tssi_get_final(void *rf_void, enum phl_phy_idx phy_idx, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + return halrf_tssi_get_final_8852ab(rf, path); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + return halrf_tssi_get_final_8852b(rf, path); + break; +#endif + + default: + break; + } + + return 0; +} + +void halrf_set_tssi_de_offset(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de_offset, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_tssi_de_offset_8852a(rf, phy_idx, tssi_de_offset, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_set_tssi_de_offset_8852b(rf, phy_idx, tssi_de_offset, path); + break; +#endif + + default: + break; + } +} + +void halrf_set_tssi_avg_mp(void *rf_void, + enum phl_phy_idx phy_idx, s32 xdbm) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_tssi_avg_mp_8852a(rf, phy_idx, xdbm); + break; +#endif + default: + break; + } +} + +void halrf_set_rx_gain_offset_for_rx_verify(void *rf_void, + enum phl_phy_idx phy, + s8 rx_gain_offset, u8 path) +{ +#if 0 + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_rx_gain_offset_for_rx_verify_8852a(rf, phy, rx_gain_offset, path); + break; +#endif + default: + break; + } +#endif +} + +void halrf_set_power_track(void *rf_void, enum phl_phy_idx phy_idx, u8 value) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_tssi_info *tssi_info = &rf->tssi; + + tssi_info->tssi_type = value; + + if (value == TSSI_OFF) { + halrf_tssi_trigger(rf, phy_idx); + rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK; + } else if (value == TSSI_ON) { + rf->support_ability = rf->support_ability | HAL_RF_TX_PWR_TRACK; + halrf_tssi_trigger(rf, phy_idx); + } else if (value == TSSI_CAL) { + rf->support_ability = rf->support_ability | HAL_RF_TX_PWR_TRACK; + halrf_tssi_trigger(rf, phy_idx); + } else + rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK; + + +} + +u8 halrf_get_power_track(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_tssi_info *tssi_info = &rf->tssi; + + return tssi_info->tssi_type; +} + +void halrf_tssi_get_efuse_ex(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_tssi_get_efuse_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_get_efuse_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + halrf_get_efuse_power_table_switch(rf, phy_idx); +} + +bool halrf_tssi_check_efuse_data(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + return halrf_tssi_check_efuse_data_8852a(rf, phy_idx); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + return halrf_tssi_check_efuse_data_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + return false; +} + +void halrf_set_ref_power_to_struct(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_ref_power_to_struct_8852a(rf, phy_idx); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_set_ref_power_to_struct_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } +} + +void halrf_set_regulation_init(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_pwr_info *pwr = &rf->pwr_info; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + pwr->regulation_idx = 0xff; + break; +#endif + default: + break; + } +} + +void halrf_bf_config_rf(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_bf_config_rf_8852a(rf); + break; +#endif + default: + break; + } +} + +bool halrf_get_efuse_info(void *rf_void, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 autoload_status) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_efuse_info_8852a(rf, efuse_map, id, value, length, + autoload_status); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_get_efuse_info_8852b(rf, efuse_map, id, value, length, + autoload_status); +#endif + + return 0; +} + +void halrf_get_efuse_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx) +{ +#if 0 + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_get_efuse_rx_gain_k_8852a(rf, phy_idx); +#endif +#endif + +} + +void halrf_get_efuse_trim(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_get_efuse_trim_8852a(rf, phy_idx); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_get_efuse_trim_8852b(rf, phy_idx); +#endif + +} + +void halrf_do_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx) +{ +#if 0 + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_RXGAINK)) + return; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_do_rx_gain_k_8852a(rf, phy_idx); +#endif +#endif +} + +bool halrf_set_dbcc(void *rf_void, bool dbcc_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_set_dbcc_8852a(rf, dbcc_en); +#endif + return 0; +} + +bool halrf_wl_tx_power_control(void *rf_void, u32 tx_power_val) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool rtn = false; + + switch (hal_com->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + rtn = halrf_wl_tx_power_control_8852a(rf, tx_power_val); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + rtn = halrf_wl_tx_power_control_8852b(rf, tx_power_val); + break; +#endif + default: + break; + } + + return rtn; +} + +void halrf_watchdog(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + /*halrf_thermal_period(rf);*/ + halrf_tssi_ant_open(rf); + halrf_tssi_tracking(rf); + halrf_dpk_tracking(rf); + halrf_iqk_tracking(rf); +} + +u8 halrf_get_default_rfe_type(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_default_rfe_type_8852a(rf); +#endif + return 1; +} + +u8 halrf_get_default_xtal(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_default_xtal_8852a(rf); +#endif + return 0x3f; +} + +bool halrf_iqk_get_ther_rek(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_iqk_get_ther_rek_8852ab(rf); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_iqk_get_ther_rek_8852b(rf); +#endif + + return false; +} + +enum rtw_hal_status halrf_iqk_tracking(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_iqk_info *iqk = &rf->iqk; + + if (!(rf->support_ability & HAL_RF_IQK) || rf->rfk_is_processing || + rf->is_watchdog_stop) + return RTW_HAL_STATUS_SUCCESS; + + rf->is_watchdog_stop = true; /*avoid race condition*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_track_8852ab(rf); +#if 0 + if (halrf_iqk_get_ther_rek(rf)) + halrf_iqk(rf, 0x0, false); +#endif + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_track_8852b(rf); + break; +#endif + + default: + break; + } + + rf->is_watchdog_stop = false; + + return RTW_HAL_STATUS_SUCCESS; +} + +void halrf_psd_init(void *rf_void, enum phl_phy_idx phy, + u8 path, u8 iq_path, u32 avg, u32 fft) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_psd_init_8852a(rf, phy, path, iq_path, avg, fft); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_psd_init_8852b(rf, phy, path, iq_path, avg, fft); +#endif +} + +void halrf_psd_restore(void *rf_void, enum phl_phy_idx phy) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_psd_restore_8852a(rf, phy); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_psd_restore_8852b(rf, phy); +#endif +} + +u32 halrf_psd_get_point_data(void *rf_void, enum phl_phy_idx phy, s32 point) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_psd_get_point_data_8852a(rf, phy, point); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_psd_get_point_data_8852b(rf, phy, point); +#endif + + return 0; +} + +void halrf_psd_query(void *rf_void, enum phl_phy_idx phy, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_psd_query_8852a(rf, phy, point, start_point, stop_point, outbuf); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_psd_query_8852b(rf, phy, point, start_point, stop_point, outbuf); +#endif + +} + +void halrf_set_fix_power_to_struct(void *rf_void, + enum phl_phy_idx phy, s8 dbm) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + pwr->fix_power[RF_PATH_A] = true; + pwr->fix_power_dbm[RF_PATH_A] = dbm * 2; + + pwr->fix_power[RF_PATH_B] = true; + pwr->fix_power_dbm[RF_PATH_B] = dbm * 2; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_set_fix_power_to_struct_8852ab(rf, phy, dbm); + break; +#endif + default: + break; + } +} + +void halrf_pwr_by_rate_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_pwr_by_rate_info_8852a(rf, input, &used, + output, &out_len); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_pwr_by_rate_info_8852b(rf, input, &used, + output, &out_len); + break; +#endif + + default: + break; + } +} + +void halrf_pwr_limit_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_pwr_limit_info_8852a(rf, input, &used, + output, &out_len); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_pwr_limit_info_8852b(rf, input, &used, + output, &out_len); + break; +#endif + + default: + break; + } +} + +void halrf_pwr_limit_ru_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_pwr_limit_ru_info_8852a(rf, input, &used, + output, &out_len); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_pwr_limit_ru_info_8852b(rf, input, &used, + output, &out_len); + break; +#endif + + default: + break; + } +} + +void halrf_get_tssi_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_get_tssi_info_8852a(rf, input, &used, + output, &out_len); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_get_tssi_info_8852b(rf, input, &used, + output, &out_len); + break; +#endif + + default: + break; + } +} + +void halrf_get_tssi_trk_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_get_tssi_trk_info_8852a(rf, input, &used, + output, &out_len); + break; +#endif + default: + break; + } +} + +void halrf_tssi_backup_txagc(struct rf_info *rf, enum phl_phy_idx phy, bool enable) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_tssi_backup_txagc_8852b(rf, phy, enable); + break; +#endif + default: + break; + } +} + +void halrf_set_tx_shape(struct rf_info *rf, u8 tx_shape_idx) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_set_tx_shape_8852b(rf, tx_shape_idx); + break; +#endif + default: + break; + } +} + + +void halrf_ctl_bw(void *rf_void, enum channel_width bw) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_ctrl_bw_8852b(rf, bw); + break; +#endif + default: + break; + } + return; + +} + +void halrf_ctl_ch(void *rf_void, u8 central_ch) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_ctrl_ch_8852b(rf, central_ch); + break; +#endif + default: + break; + } + return; +} + +void halrf_rxbb_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_rxbb_bw_8852a(rf, phy, bw); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_rxbb_bw_8852b(rf, phy, bw); + break; +#endif + default: + break; + } + return; +} + +void halrf_config_radio_to_fw(void *rf_void) +{ + + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_config_8852a_radio_to_fw(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_config_8852b_radio_to_fw(rf); + break; +#endif + default: + break; + } +} + +void halrf_rfc_reg_backup(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_rfc_reg_backup_8852a(rf); + break; +#endif + default: + break; + } +} + +bool halrf_rfc_reg_check_fail(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + bool fail = false; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + fail = halrf_rfc_reg_check_fail_8852a(rf); + break; +#endif + default: + break; + } + return fail; +} + +void halrf_rfk_reg_backup(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_rfk_reg_backup_8852a(rf); + break; +#endif + default: + break; + } +} + +bool halrf_rfk_reg_check_fail(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + bool fail = false; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + fail = halrf_rfk_reg_check_fail_8852a(rf); + break; +#endif + default: + break; + } + return fail; +} + +bool halrf_dack_reg_check_fail(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + bool fail = false; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + fail = halrf_dack_reg_check_fail_8852a(rf); + break; +#endif + default: + break; + } + return fail; +} + +bool halrf_rfk_chl_thermal(void *rf_void, + u8 chl_idx, u8 ther_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool fail = false; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + fail = halrf_rfk_chl_thermal_8852a(rf, chl_idx, ther_idx); +#endif + return fail; + +} + +void halrf_rfk_recovery_chl_thermal(void *rf_void, u8 chl_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_rfk_recovery_chl_thermal_8852a(rf, chl_idx); +#endif +} + +u8 halrf_fcs_get_thermal_index(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + u8 idx = 0; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + idx = halrf_thermal_index_cal_8852a(rf); +#endif + return idx; +} + +void halrf_disconnect_notify(void *rf_void, struct rtw_chan_def *chandef ) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool fail = false; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_disconnect_notify_8852a(rf, chandef); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_disconnect_notify_8852b(rf, chandef); +#endif + + return; + +} + +bool halrf_check_mcc_ch(void *rf_void, struct rtw_chan_def *chandef ) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool fail = false; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + fail = halrf_check_mcc_ch_8852a(rf, chandef); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + fail = halrf_check_mcc_ch_8852b(rf, chandef); +#endif + + return fail; + +} + +void halrf_fw_ntfy(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_fw_ntfy_8852a(rf, phy_idx); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_fw_ntfy_8852b(rf, phy_idx); +#endif + + return; +} + +void halrf_set_regulation_from_driver(void *rf_void, + u8 regulation_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_set_regulation_from_driver_8852a(rf, regulation_idx); +#endif + return; +} + +u32 halrf_get_nctl_reg_ver(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_8852a_nctl_reg_ver(); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_get_8852b_nctl_reg_ver(); +#endif + return 0; + +} + +u32 halrf_get_radio_reg_ver(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_get_8852a_radio_reg_ver(); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_get_8852b_radio_reg_ver(); +#endif + return 0; +} + +u32 halrf_get_radio_ver_from_reg(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_rrf(rf, RF_PATH_A, 0x67, 0xfff); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_rrf(rf, RF_PATH_A, 0x9F, 0xfff); +#endif +#ifdef RF_8852C_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852C) + return halrf_rrf(rf, RF_PATH_A, 0xFE, 0xfff); +#endif + +#if 0 /* TBD */ +#ifdef RF_8832BR_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8832BR) + return halrf_rrf(rf, RF_PATH_A, 0xFE, 0xfff); +#endif +#ifdef RF_8192XB_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8192XB) + return halrf_rrf(rf, RF_PATH_A, 0xFE, 0xfff); +#endif +#endif + + return 0; +} + +void halrf_config_nctl_reg(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_config_8852a_nctl_reg(rf); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_config_8852b_nctl_reg(rf); +#endif + + return; +} + +void halrf_set_gpio(void *rf_void, enum phl_phy_idx phy, u8 band) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_set_gpio_8852a(rf, phy, band); +#endif +} + +bool halrf_mac_set_pwr_reg(void *rf_void, enum phl_phy_idx phy, + u32 addr, u32 mask, u32 val) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + u32 result = 0; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + result = halrf_mac_set_pwr_reg_8852a(rf, phy, addr, mask, val); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + result = halrf_mac_set_pwr_reg_8852b(rf, phy, addr, mask, val); +#endif + + if (result == 0) /*MAC: MACSUCCESS == 0*/ + return true; + else + return false; +} + +u32 halrf_mac_get_pwr_reg(void *rf_void, enum phl_phy_idx phy, + u32 addr, u32 mask) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_mac_get_pwr_reg_8852a(rf, phy, addr, mask); +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + return halrf_mac_get_pwr_reg_8852b(rf, phy, addr, mask); +#endif + + return 0; +} + +bool halrf_check_efem(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + return halrf_check_efem_8852a(rf, phy_idx); +#endif + return false; +} + +void halrf_2g_rxant(void *rf_void, enum halrf_ant ant) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_2g_rxant_8852a(rf, ant); +#endif +} + +s8 halrf_xtal_tracking_offset(void *rf_void, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (!(rf->support_ability & HAL_RF_XTAL_TRACK)) + return 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + return halrf_xtal_tracking_offset_8852a(rf, phy_idx); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + return halrf_xtal_tracking_offset_8852b(rf, phy_idx); + break; +#endif + + default: + break; + } + + return 0; +} + +void halrf_set_mp_regulation(void *rf_void, enum phl_phy_idx phy, u8 regulation) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_pwr_info *pwr = &rf->pwr_info; + + pwr->mp_regulation = regulation; +} + +#endif + diff --git a/phl/hal_g6/phy/rf/halrf.h b/phl/hal_g6/phy/rf/halrf.h new file mode 100644 index 0000000..04922fa --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf.h @@ -0,0 +1,289 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_H__ +#define __HALRF_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*H2C cmd ID*/ +/*Class 8*/ +/*Class 9*/ +/*Class a*/ +#define FWCMD_H2C_BACKUP_RFK 0 +#define FWCMD_H2C_RELOAD_RFK 1 +#define FWCMD_H2C_GET_MCCCH 2 +#define FWCMD_H2C_DPK_OFFLOAD 3 +#define FWCMD_H2C_IQK_OFFLOAD 4 + +/*@--------------------------[Enum]------------------------------------------*/ +enum halrf_func_idx { + RF00_PWR_TRK = 0, + RF01_IQK = 1, + RF02_LCK = 2, + RF03_DPK = 3, + RF04_TXGAPK = 4, + RF05_DACK = 5, + RF06_DPK_TRK = 6, + RF07_2GBAND_SHIFT = 7, + RF08_RXDCK = 8, + RF09_RFK = 9, + RF10_RF_INIT = 10, + RF11_RF_POWER = 11, + RF12_RXGAINK = 12, + RF13_THER_TRIM = 13, + RF14_PABIAS_TRIM = 14, + RF15_TSSI_TRIM = 15, + RF16_PSD = 16, + RF17_TSSI_TRK = 17, + RF18_XTAL_TRK = 18, + RF19_TX_SHAPE = 19 +}; + +enum halrf_rf_mode { + RF_SHUT_DOWN = 0x0, + RF_STANDBY = 0x1, + RF_TX = 0x2, + RF_RX = 0x3, + RF_TXIQK = 0x4, + RF_DPK = 0x5, + RF_RXK1 = 0x6, + RF_RXK2 = 0x7 +}; + +enum halrf_rfe_src_sel { + HALRF_PAPE_RFM = 0, + HALRF_GNT_BT_INV = 1, + HALRF_LNA0N = 2, + HALRF_LNAON_RFM = 3, + HALRF_TRSW_RFM = 4, + HALRF_TRSW_RFM_B = 5, + HALRF_GNT_BT = 6, + HALRF_ZERO = 7, + HALRF_ANTSEL_0 = 8, + HALRF_ANTSEL_1 = 9, + HALRF_ANTSEL_2 = 0xa, + HALRF_ANTSEL_3 = 0xb, + HALRF_ANTSEL_4 = 0xc, + HALRF_ANTSEL_5 = 0xd, + HALRF_ANTSEL_6 = 0xe, + HALRF_ANTSEL_7 = 0xf +}; + +/*@=[HALRF supportability]=======================================*/ +enum halrf_ability { + HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), + HAL_RF_IQK = BIT(RF01_IQK), + HAL_RF_LCK = BIT(RF02_LCK), + HAL_RF_DPK = BIT(RF03_DPK), + HAL_RF_TXGAPK = BIT(RF04_TXGAPK), + HAL_RF_DACK = BIT(RF05_DACK), + HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK), + HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT), + HAL_RF_RXDCK = BIT(RF08_RXDCK), + HAL_RF_RXGAINK = BIT(RF12_RXGAINK), + HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM), + HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM), + HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM), + HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK), + HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK), + HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE) +}; + +/*@=[HALRF Debug Component]=====================================*/ +enum halrf_dbg_comp { + DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), + DBG_RF_IQK = BIT(RF01_IQK), + DBG_RF_LCK = BIT(RF02_LCK), + DBG_RF_DPK = BIT(RF03_DPK), + DBG_RF_TXGAPK = BIT(RF04_TXGAPK), + DBG_RF_DACK = BIT(RF05_DACK), + DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK), + DBG_RF_RXDCK = BIT(RF08_RXDCK), + DBG_RF_RFK = BIT(RF09_RFK), + DBG_RF_INIT = BIT(RF10_RF_INIT), + DBG_RF_POWER = BIT(RF11_RF_POWER), + DBG_RF_RXGAINK = BIT(RF12_RXGAINK), + DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM), + DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM), + DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM), + DBG_RF_PSD = BIT(RF16_PSD), + DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK), + DBG_RF_FW = BIT(28), + DBG_RF_MP = BIT(29), + DBG_RF_TMP = BIT(30), + DBG_RF_CHK = BIT(31) +}; + + +/*@--------------------------[Structure]-------------------------------------*/ + +struct rfk_location { + enum band_type cur_band; + enum channel_width cur_bw; + u8 cur_ch; +}; + +struct halrf_fem_info { + u8 elna_2g; /*@with 2G eLNA NO/Yes = 0/1*/ + u8 elna_5g; /*@with 5G eLNA NO/Yes = 0/1*/ + u8 elna_6g; /*@with 6G eLNA NO/Yes = 0/1*/ + u8 epa_2g; /*@with 2G ePA NO/Yes = 0/1*/ + u8 epa_5g; /*@with 5G ePA NO/Yes = 0/1*/ + u8 epa_6g; /*@with 6G ePA NO/Yes = 0/1*/ +}; + +#if 1 /* all rf operation usage (header) */ + +/* clang-format on */ +#define RF_PATH_MAX_NUM (8) +#define RF_TASK_RECORD_MAX_TIMES (16) +#define RF_BACKUP_MAC_REG_MAX_NUM (16) +#define RF_BACKUP_BB_REG_MAX_NUM (16) +#define RF_BACKUP_RF_REG_MAX_NUM (16) + +struct halrf_iqk_ops { + u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx); + bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy, u8 path); + void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy, u8 path); + void (*iqk_preset)(struct rf_info *rf, u8 path); + void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); + void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); + void (*iqk_restore)(struct rf_info *rf, u8 path); + void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); +}; + +struct rfk_iqk_info { + struct halrf_iqk_ops *rf_iqk_ops; + u8 rf_max_path_num; + u32 rf_iqk_version; + u8 rf_iqk_ch_num; + u8 rf_iqk_path_num; + + const u32 *backup_mac_reg; + u32 backup_mac_reg_num; + const u32 *backup_bb_reg; + u32 backup_bb_reg_num; + const u32 *backup_rf_reg; + u32 backup_rf_reg_num; +}; +/* clang-format off */ +#endif /* all rf operation usage (header) */ + +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT +struct halrf_fw_offload { + enum rtw_mac_src_cmd_ofld src; + enum rtw_mac_cmd_type_ofld type; + u8 lc; + enum rtw_mac_rf_path rf_path; + u16 offset; + u16 id; + u32 value; + u32 mask; +}; +#endif + +struct halrf_rx_dck_info { + bool is_afe; + struct rfk_location loc[KPATH]; /*max RF path*/ +}; + +struct rf_info { + struct rtw_phl_com_t *phl_com; + struct rtw_hal_com_t *hal_com; + /*[Common Info]*/ + u32 ic_type; + u8 num_rf_path; + /*[System Info]*/ + bool rf_init_ready; + u32 rf_sys_up_time; + bool rf_watchdog_en; + bool rf_ic_api_en; + /*[DM Info]*/ + u32 support_ability; + u32 manual_support_ability; + /*[FW Info]*/ + u32 fw_dbg_component; + /*[Drv Dbg Info]*/ + u32 dbg_component; + u8 cmn_dbg_msg_period; + u8 cmn_dbg_msg_cnt; + /*[BTC / RFK Info ]*/ + bool rfk_is_processing; + bool is_bt_iqk_timeout; + /*[initial]*/ + u8 pre_rxbb_bw[KPATH]; + /*[TSSI Info]*/ + bool is_tssi_mode[4]; /*S0/S1*/ + /*[Thermal Trigger]*/ + bool is_thermal_trigger; + /*[Do Coex]*/ + bool is_coex; + /*[watchdog]*/ + bool is_watchdog_stop; + /*[thermal rek indictor]*/ + bool rfk_do_thr_rek; + /*reg check*/ + u32 rfk_reg[2048]; + u32 rfc_reg[2][10]; + u32 rfk_check_fail_count; + /*fast channel switch*/ + u8 ther_init; + u32 fcs_rfk_ok_map; + u8 pre_chl_idx; + u8 pre_ther_idx; + /* [Check NCTL Done status Read Times] */ + u32 nctl_ck_times[2]; /* 0xbff8 0x80fc*/ + u32 fw_ofld_enable; + + /*@=== [HALRF Structure] ============================================*/ + struct halrf_pwr_track_info pwr_track; + struct halrf_tssi_info tssi; + struct halrf_xtal_info xtal_track; + struct halrf_iqk_info iqk; + struct halrf_dpk_info dpk; + struct halrf_rx_dck_info rx_dck; + struct halrf_dack_info dack; + struct halrf_gapk_info gapk; + struct halrf_pwr_info pwr_info; + struct halrf_radio_info radio_info; + struct halrf_fem_info fem; + struct rf_dbg_cmd_info rf_dbg_cmd_i; + struct halrf_kfree_info kfree_info; + struct halrf_psd_data psd; + struct rfk_location iqk_loc[2]; /*S0/S1*/ + struct rfk_location dpk_loc[2]; /*S0/S1*/ + struct rfk_location gapk_loc[2]; /*S0/S1*/ + struct rfk_iqk_info *rfk_iqk_info; +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + struct halrf_fw_offload fwofld; +#endif +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ + + +#endif + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.c new file mode 100644 index 0000000..b7db3a9 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.c @@ -0,0 +1,815 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT +bool halrf_bw_setting_8852b(struct rf_info *rf, enum rf_path path, enum channel_width bw, bool is_dav) +{ + u32 rf_reg18 = 0; + u32 reg_reg18_addr = 0x0; + + RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__); + if(is_dav) + reg_reg18_addr =0x18; + else + reg_reg18_addr =0x10018; + + rf_reg18 = halrf_rrf(rf, path, reg_reg18_addr, MASKRF); + /*==== [Error handling] ====*/ + if (rf_reg18 == INVALID_RF_DATA) { + RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid RF_0x18 for Path-%d\n", path); + return false; + } + rf_reg18 &= ~(BIT(11) | BIT(10)); + /*==== [Switch bandwidth] ====*/ + switch (bw) { + case CHANNEL_WIDTH_5: + case CHANNEL_WIDTH_10: + case CHANNEL_WIDTH_20: + /*RF bandwidth */ + rf_reg18 |= (BIT(11) | BIT(10)); + break; + case CHANNEL_WIDTH_40: + /*RF bandwidth */ + rf_reg18 |= BIT(11); + break; + case CHANNEL_WIDTH_80: + /*RF bandwidth */ + rf_reg18 |= BIT(10); + break; + default: + RF_DBG(rf, DBG_RF_RFK, "[RFK]Fail to set CH\n"); + } + + /*==== [Write RF register] ====*/ + halrf_wrf(rf, path, reg_reg18_addr, MASKRF, rf_reg18); + RF_DBG(rf, DBG_RF_RFK, "[RFK] set %x at path%d, %x =0x%x\n",bw, path, reg_reg18_addr, halrf_rrf(rf, path, reg_reg18_addr, MASKRF)); + return true; +} + +bool halrf_ctrl_bw_8852b(struct rf_info *rf, enum channel_width bw) +{ + bool is_dav; + //RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__); + + /*==== Error handling ====*/ + if (bw >= CHANNEL_WIDTH_MAX ) { + RF_DBG(rf, DBG_RF_RFK,"[RFK]Fail to switch bw(bw:%d)\n", bw); + return false; + } + + //DAV + is_dav = true; + halrf_bw_setting_8852b(rf, RF_PATH_A, bw, is_dav); + halrf_bw_setting_8852b(rf, RF_PATH_B, bw, is_dav); + //DDV + is_dav = false; + halrf_bw_setting_8852b(rf, RF_PATH_A, bw, is_dav); + halrf_bw_setting_8852b(rf, RF_PATH_B, bw, is_dav); + + //RF_DBG(rf, DBG_RF_RFK, "[RFK] BW: %d\n", bw); + //RF_DBG(rf, DBG_RF_RFK, "[RFK] 0x18 = 0x%x\n",halrf_rrf(rf, RF_PATH_A, 0x18, MASKRF)); + + return true; +} + +void halrf_lck_check_8852b(struct rf_info *rf) +{ + u32 c = 0, temp; + + while (c < 1000) { + if (halrf_rrf(rf, 0, 0xb7, BIT(8)) == 0) + break; + c++; + halrf_delay_us(rf, 1); + } + RF_WARNING("c=%d, 0xc5= 0x%x\n", c, halrf_rrf(rf, 0, 0xc5, MASKRF)); + if (c == 1000) { + RF_WARNING("LCK timeout\n"); + } else { + if (halrf_rrf(rf, 0, 0xc5, BIT(15)) == 0) { + RF_WARNING("SYN MMD reset\n"); + /*MMD reset*/ + halrf_wrf(rf, 0, 0xd5, BIT(8), 0x1); + halrf_wrf(rf, 0, 0xd5, BIT(6), 0x0); + halrf_wrf(rf, 0, 0xd5, BIT(6), 0x1); + halrf_wrf(rf, 0, 0xd5, BIT(8), 0x0); + } + + halrf_delay_us(rf, 10); + if (halrf_rrf(rf, 0, 0xc5, BIT(15)) == 0) { + RF_WARNING("re-set RF 0x18\n"); + halrf_wrf(rf, 0, 0xd3, BIT(8), 0x1); + temp = halrf_rrf(rf, 0, 0x18, MASKRF); + halrf_wrf(rf, 0, 0x18, MASKRF, temp); + halrf_wrf(rf, 0, 0xd3, BIT(8), 0x0); + } + } +} + +bool halrf_ch_setting_8852b(struct rf_info *rf, enum rf_path path, u8 central_ch, + bool *is_2g_ch, bool is_dav) +{ + u32 rf_reg18 = 0; + u32 reg_reg18_addr = 0x0; + + RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__); + + if(is_dav) + reg_reg18_addr = 0x18; + else + reg_reg18_addr =0x10018; + + rf_reg18 = halrf_rrf(rf, path, reg_reg18_addr, MASKRF); + /*==== [Error handling] ====*/ + if (rf_reg18 == INVALID_RF_DATA) { + RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid RF_0x18 for Path-%d\n", path); + return false; + } + *is_2g_ch = (central_ch <= 14) ? true : false; + /*==== [Set RF Reg 0x18] ====*/ + rf_reg18 &= ~0x303ff; /*[17:16],[9:8],[7:0]*/ + rf_reg18 |= central_ch; /* Channel*/ + /*==== [5G Setting] ====*/ + if (!*is_2g_ch) + rf_reg18 |= (BIT(16) | BIT(8)); + halrf_wrf(rf, path, reg_reg18_addr, MASKRF, rf_reg18); + halrf_delay_us(rf, 100); + halrf_wrf(rf, path, 0xcf, BIT(0), 0); + halrf_wrf(rf, path, 0xcf, BIT(0), 1); + RF_DBG(rf, DBG_RF_RFK, "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", central_ch, path, reg_reg18_addr, halrf_rrf(rf, path, reg_reg18_addr, MASKRF)); + return true; +} + +bool halrf_ctrl_ch_8852b(struct rf_info *rf, u8 central_ch) +{ + bool is_2g_ch; + bool is_dav; + + //RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__); + + /*==== Error handling ====*/ + if ((central_ch > 14 && central_ch < 36) || + (central_ch > 64 && central_ch < 100) || + (central_ch > 144 && central_ch < 149) || + central_ch > 177 ) { + RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid CH:%d \n", central_ch); + return false; + } + //DAV + is_dav = true; + halrf_ch_setting_8852b(rf, RF_PATH_A, central_ch, &is_2g_ch, is_dav); + halrf_ch_setting_8852b(rf, RF_PATH_B, central_ch, &is_2g_ch, is_dav); + //DDV + is_dav = false; + halrf_ch_setting_8852b(rf, RF_PATH_A, central_ch, &is_2g_ch, is_dav); + halrf_ch_setting_8852b(rf, RF_PATH_B, central_ch, &is_2g_ch, is_dav); + //RF_DBG(rf, DBG_RF_RFK, "[RFK] CH: %d\n", central_ch); + RF_WARNING("===>%s\n", __func__); + halrf_lck_check_8852b(rf); + return true; +} + +void halrf_set_lo_8852b(struct rf_info *rf, bool is_on, enum rf_path path) +{ + if (is_on) { + halrf_rf_direct_cntrl_8852b(rf, path, false); + halrf_wrf(rf, path, 0x0, MASKRFMODE, 0x2); + halrf_wrf(rf, path, 0x58, BIT(1), 0x1); + halrf_wrf(rf, path, 0xde, 0x1800, 0x3); + halrf_wrf(rf, path, 0x56, 0x1c00, 0x1); + halrf_wrf(rf, path, 0x56, 0x1e0, 0x1); + } else { + halrf_wrf(rf, path, 0x58, BIT(1), 0x0); + halrf_rf_direct_cntrl_8852b(rf, path, true); + halrf_wrf(rf, path, 0xde, 0x1800, 0x0); + } +} + +void halrf_rf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb) +{ + if (is_bybb) + halrf_wrf(rf, path, 0x5, BIT(0), 0x1); + else + halrf_wrf(rf, path, 0x5, BIT(0), 0x0); +} + +void halrf_drf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb) +{ + if (is_bybb) + halrf_wrf(rf, path, 0x10005, BIT(0), 0x1); + else + halrf_wrf(rf, path, 0x10005, BIT(0), 0x0); +} + + +void halrf_lo_test_8852b(struct rf_info *rf, bool is_on, enum rf_path path) +{ + switch (path) { + case RF_PATH_A: + halrf_set_lo_8852b(rf, is_on, RF_PATH_A); + halrf_set_lo_8852b(rf, false, RF_PATH_B); + break; + case RF_PATH_B: + halrf_set_lo_8852b(rf, false, RF_PATH_A); + halrf_set_lo_8852b(rf, is_on, RF_PATH_B); + break; + case RF_PATH_AB: + halrf_set_lo_8852b(rf, is_on, RF_PATH_A); + halrf_set_lo_8852b(rf, is_on, RF_PATH_B); + break; + default: + break; + } +} + +u8 halrf_kpath_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx) { + + RF_DBG(rf, DBG_RF_RFK, "[RFK]dbcc_en: %x, PHY%d\n", rf->hal_com->dbcc_en, phy_idx); + + if (!rf->hal_com->dbcc_en) { + return RF_AB; + } else { + if (phy_idx == HW_PHY_0) + return RF_A; + else + return RF_B; + } +} + +void _rx_dck_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe) +{ + struct halrf_rx_dck_info *rx_dck = &rf->rx_dck; + + rx_dck->is_afe = is_afe; + rx_dck->loc[path].cur_band = rf->hal_com->band[phy].cur_chandef.band; + rx_dck->loc[path].cur_bw = rf->hal_com->band[phy].cur_chandef.bw; + rx_dck->loc[path].cur_ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] ==== S%d RX DCK (%s / CH%d / %s / by %s)====\n", path, + rx_dck->loc[path].cur_band == 0 ? "2G" : + (rx_dck->loc[path].cur_band == 1 ? "5G" : "6G"), + rx_dck->loc[path].cur_ch, + rx_dck->loc[path].cur_bw == 0 ? "20M" : + (rx_dck->loc[path].cur_bw == 1 ? "40M" : "80M"), + rx_dck->is_afe ? "AFE" : "RFC"); +} + +void halrf_set_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe) +{ + u8 phy_map; + u32 ori_val, i = 0; + + phy_map = (BIT(phy) << 4) | BIT(path); + + _rx_dck_info_8852b(rf, phy, path, is_afe); + + if (is_afe) { + ori_val = halrf_rreg(rf, 0x12a0 + (path << 13), MASKDWORD); + + halrf_wreg(rf, 0x12b8 + (path << 13), BIT(30), 0x1); /*debug en*/ + //halrf_wreg(rf, 0x12a0 + (path << 13), BIT(19), 0x1); + //halrf_wreg(rf, 0x12a0 + (path << 13), 0x00070000, 0x3); /*ADC 320M*/ + halrf_wreg(rf, 0x12a0 + (path << 13), 0x000F0000, 0xb); + //halrf_wreg(rf, 0x12d8 + (path << 13), BIT(5) | BIT(4), 0x3); /*offset manual en*/ + //halrf_wreg(rf, 0x12d8 + (path << 13), BIT(7) | BIT(6), 0x3); /*avg 0:16; 1:32; 2:64; 3:128*/ + halrf_wreg(rf, 0xc0f4 + (path << 8), 0x000000F0, 0xf); /*offset manual en*/ + halrf_wreg(rf, 0x030c, 0x0f000000, 0x3); /*adc en*/ + halrf_wreg(rf, 0x032c, BIT(30), 0x0); /*adc clk*/ + halrf_wreg(rf, 0x032c, BIT(22), 0x0); /*filter reset*/ + halrf_wreg(rf, 0x032c, BIT(22), 0x1); /*filter reset release*/ + halrf_wreg(rf, 0x032c, BIT(18) | BIT(17) | BIT(16), 0x1); /*connect with RXBB*/ + + halrf_wreg(rf, 0x5864, BIT(29), 0x1); /*iqk_control_sw_si*/ + + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080); + halrf_wreg(rf, 0x8034, MASKDWORD, 0x00000020); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00000100); + halrf_wreg(rf, 0x81e0, MASKDWORD, 0x02000000); + halrf_wreg(rf, 0x82e0, MASKDWORD, 0x02100000); + halrf_wreg(rf, 0x8000, BIT(2) | BIT(1), path); /*subpage_id*/ + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_START); + + halrf_wreg(rf, 0x80ac, MASKDWORD, 0xfc030000); + halrf_wreg(rf, 0x80ac, MASKDWORD, 0x7c030000); + + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x34); + + while ((halrf_rreg(rf, 0x80fc, BIT(16)) == 0x0) && (i < 500)) { + halrf_delay_us(rf, 2); + i++; + } + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_STOP); + + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x12b8 + (path << 13), BIT(30), 0x0); /*debug en*/ + halrf_wreg(rf, 0x12a0 + (path << 13), MASKDWORD, ori_val); + halrf_wreg(rf, 0x5864, BIT(29), 0x0); /*iqk_control_sw_si*/ + + } else { + halrf_wrf(rf, path, 0x93, 0x0000f, 0x0); /*0: from RFC; 1: from AFE*/ + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_START); + + halrf_wrf(rf, path, 0x92, BIT(0), 0x0); + halrf_wrf(rf, path, 0x92, BIT(0), 0x1); + + for (i = 0; i < 30; i++) /*delay 600us*/ + halrf_delay_us(rf, 20); + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_STOP); + } +#if 0 + RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] 0x92 = 0x%x, 0x93 = 0x%x\n", + halrf_rrf(rf, path, 0x92, MASKRF), + halrf_rrf(rf, path, 0x93, MASKRF)); +#endif +} + +bool halrf_rx_dck_check_8852b(struct rf_info *rf, enum rf_path path) +{ + u8 addr; + bool is_fail = false; + + if (halrf_rreg(rf, 0xc400 + path * 0x1000, 0xF0000) == 0x0) + return is_fail = true; + else if (halrf_rreg(rf, 0xc400 + path * 0x1000, 0x0F000) == 0x0) + return is_fail = true; + else if (halrf_rreg(rf, 0xc440 + path * 0x1000, 0xF0000) == 0x0) + return is_fail = true; + else if (halrf_rreg(rf, 0xc440 + path * 0x1000, 0x0F000) == 0x0) + return is_fail = true; + else { + for (addr = 0x0; addr < 0x20; addr++) { + if (halrf_rreg(rf, 0xc400 + path * 0x1000 + addr * 4, 0x00FC0) == 0x0) + return is_fail = true; + } + + for (addr = 0x0; addr < 0x20; addr++) { + if (halrf_rreg(rf, 0xc400 + path * 0x1000 + addr * 4, 0x0003F) == 0x0) + return is_fail = true; + } + } + + return is_fail; +} + +void halrf_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe) +{ + u8 path, dck_tune; + u32 rf_reg5; + + RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n", + RXDCK_VER_8852B, rf->hal_com->cv); + + for (path = 0; path < 2; path++) { + rf_reg5 = halrf_rrf(rf, path, 0x5, MASKRF); + dck_tune = (u8)halrf_rrf(rf, path, 0x92, BIT(1)); + + if (rf->is_tssi_mode[path]) + halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), 0x1); /*TSSI pause*/ + + halrf_wrf(rf, path, 0x5, BIT(0), 0x0); + halrf_wrf(rf, path, 0x92, BIT(1), 0x0); + //halrf_wrf(rf, path, 0x8f, BIT(11) | BIT(10), 0x1); /*EN_TIA_IDAC_LSB[1:0]*/ + halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX); + halrf_set_rx_dck_8852b(rf, phy, path, is_afe); +#if 0 + if (halrf_rx_dck_check_8852b(rf, path)) { + RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] S%d RX_DCK value = 0 happen!!!\n", path); + halrf_wrf(rf, path, 0x8f, BIT(11) | BIT(10), 0x2); /*EN_TIA_IDAC_LSB[1:0]*/ + halrf_set_rx_dck_8852b(rf, phy, path, is_afe); + } +#endif + halrf_wrf(rf, path, 0x92, BIT(1), dck_tune); + halrf_wrf(rf, path, 0x5, MASKRF, rf_reg5); + + if (rf->is_tssi_mode[path]) + halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), 0x0); /*TSSI resume*/ + + } +} + +void halrf_rx_dck_onoff_8852b(struct rf_info *rf, bool is_enable) +{ + u8 path; + + for (path = 0; path < 2; path++) { + halrf_wrf(rf, path, 0x93, BIT(0), !is_enable); + if (!is_enable) { + halrf_wrf(rf, path, 0x92, 0xFFC00, 0x220); /*[19:10]*/ + halrf_wrf(rf, path, 0x93, 0xFFC00, 0x220); /*[19:10]*/ + } + } +} + +void halrf_rck_8852b(struct rf_info *rf, enum rf_path path) +{ + u8 cnt = 0; + u32 rf_reg5; + u32 rck_val = 0; + + RF_DBG(rf, DBG_RF_RFK, "[RCK] ====== S%d RCK ======\n", path); + + rf_reg5 = halrf_rrf(rf, path, 0x5, MASKRF); + + halrf_wrf(rf, path, 0x5, BIT(0), 0x0); + halrf_wrf(rf, path, 0x0, MASKRFMODE, RF_RX); + + RF_DBG(rf, DBG_RF_RFK, "[RCK] RF0x00 = 0x%05x\n", halrf_rrf(rf, path, 0x00, MASKRF)); + + /*RCK trigger*/ + halrf_wrf(rf, path, 0x1b, MASKRF, 0x00240); + + while ((halrf_rrf(rf, path, 0x1c, BIT(3)) == 0x00) && (cnt < 10)) { + halrf_delay_us(rf, 2); + cnt++; + } + + rck_val = halrf_rrf(rf, path, 0x1b, 0x07C00); /*[14:10]*/ + + RF_DBG(rf, DBG_RF_RFK, "[RCK] rck_val = 0x%x, count = %d\n", rck_val, cnt); + + halrf_wrf(rf, path, 0x1b, MASKRF, rck_val); + + halrf_wrf(rf, path, 0x5, MASKRF, rf_reg5); + + RF_DBG(rf, DBG_RF_RFK, "[RCK] RF 0x1b = 0x%x\n", + halrf_rrf(rf, path, 0x1b, MASKRF)); +} + +void iqk_backup_8852b(struct rf_info *rf, enum rf_path path) +{ + return; +} + +void halrf_bf_config_rf_8852b(struct rf_info *rf) +{ + u8 i; + + for (i = 0; i < 2; i++) { + halrf_wrf(rf, (enum rf_path)i, 0xef, BIT(19), 0x1); + halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x1); + halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001); + halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0xb2120); + halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x2); + halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001); + halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0xfe124); + halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x3); + halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001); + halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7c); + halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0xa); + halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001); + halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7e); + halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0xb); + halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001); + halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7d); + halrf_wrf(rf, (enum rf_path)i, 0xef, BIT(19), 0x0); + } +} + +void halrf_set_dpd_backoff_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + u8 tx_scale, ofdm_bkof, path, kpath; + + kpath = halrf_kpath_8852b(rf, phy); + + ofdm_bkof = (u8)halrf_rreg(rf, 0x44a0 + (phy << 13), 0x0001F000); /*[16:12]*/ + tx_scale = (u8)halrf_rreg(rf, 0x44a0 + (phy << 13), 0x0000007F); /*[6:0]*/ + + if ((ofdm_bkof + tx_scale) >= 44) { /*move dpd backoff to bb, and set dpd backoff to 0*/ + dpk->dpk_gs[phy] = 0x7f; + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + if (kpath & BIT(path)) { + halrf_wreg(rf, 0x81bc + (path << 8), 0x007FFFFF, 0x7f7f7f); /*[22:0]*/ + RF_DBG(rf, DBG_RF_RFK, "[RFK] Set S%d DPD backoff to 0dB\n", path); + } + } + } else + dpk->dpk_gs[phy] = 0x5b; +} + +void halrf_dpk_init_8852b(struct rf_info *rf) +{ + halrf_set_dpd_backoff_8852b(rf, HW_PHY_0); +} + +void halrf_set_rxbb_bw_8852b(struct rf_info *rf, enum channel_width bw, enum rf_path path) +{ + halrf_wrf(rf, path, 0xee, BIT(2), 0x1); + halrf_wrf(rf, path, 0x33, 0x0001F, 0x12); /*[4:0]*/ + + if (bw == CHANNEL_WIDTH_20) + halrf_wrf(rf, path, 0x3f, 0x0003F, 0x1b); /*[5:0]*/ + else if (bw == CHANNEL_WIDTH_40) + halrf_wrf(rf, path, 0x3f, 0x0003F, 0x13); /*[5:0]*/ + else if (bw == CHANNEL_WIDTH_80) + halrf_wrf(rf, path, 0x3f, 0x0003F, 0xb); /*[5:0]*/ + else + halrf_wrf(rf, path, 0x3f, 0x0003F, 0x3); /*[5:0]*/ + + RF_DBG(rf, DBG_RF_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path, + halrf_rrf(rf, path, 0x3f, 0x0003F)); + + halrf_wrf(rf, path, 0xee, BIT(2), 0x0); +} + +void halrf_rxbb_bw_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw) +{ + u8 kpath, path; + + kpath = halrf_kpath_8852b(rf, phy); + + for (path = 0; path < 2; path++) { + if ((kpath & BIT(path)) && (rf->pre_rxbb_bw[path] != bw)) { + halrf_set_rxbb_bw_8852b(rf, bw, path); + rf->pre_rxbb_bw[path] = bw; + } else + RF_DBG(rf, DBG_RF_RFK, + "[RFK] S%d RXBB BW unchanged (pre_bw = 0x%x)\n", + path, rf->pre_rxbb_bw[path]); + } +} + +void halrf_disconnect_notify_8852b(struct rf_info *rf, struct rtw_chan_def *chandef ) { + + struct halrf_iqk_info *iqk_info = &rf->iqk; + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 path, ch; + + RF_DBG(rf, DBG_RF_RFK, "[IQK]===>%s\n", __func__); + /*[IQK disconnect]*/ + for (ch = 0; ch < 2; ch++) { + for (path = 0; path < KPATH; path++) { + if (iqk_info->iqk_mcc_ch[ch][path] == chandef->center_ch) + iqk_info->iqk_mcc_ch[ch][path] = 0x0; + } + + } + /*TXGAPK*/ + for (ch = 0; ch < 2; ch++) { + if (txgapk_info->txgapk_mcc_ch[ch] == chandef->center_ch) + txgapk_info->txgapk_mcc_ch[ch] = 0x0; + } +} + +bool halrf_check_mcc_ch_8852b(struct rf_info *rf, struct rtw_chan_def *chandef) { + + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 path, ch; + + bool check = false; + RF_DBG(rf, DBG_RF_RFK, "[IQK]===>%s, center_ch(%d)\n", __func__, chandef->center_ch); + /*[IQK check_mcc_ch]*/ + for (ch = 0; ch < 2; ch++) { + for (path = 0; path < KPATH; path++) { + if (iqk_info->iqk_mcc_ch[ch][path] == chandef->center_ch) { + check = true; + return check; + } + } + } + return check; +} + +void halrf_fw_ntfy_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx) { + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 i = 0x0; + u32 data_to_fw[5] = {0}; + u16 len = (u16) (sizeof(data_to_fw) / sizeof(u32))*4; + + data_to_fw[0] = (u32) iqk_info->iqk_mcc_ch[0][0]; + data_to_fw[1] = (u32) iqk_info->iqk_mcc_ch[0][1]; + data_to_fw[2] = (u32) iqk_info->iqk_mcc_ch[1][0]; + data_to_fw[3] = (u32) iqk_info->iqk_mcc_ch[1][1]; + data_to_fw[4] = rf->hal_com->band[phy_idx].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_RFK, "[IQK] len = 0x%x\n", len); + for (i =0; i < 5; i++) + RF_DBG(rf, DBG_RF_RFK, "[IQK] data_to_fw[%x] = 0x%x\n", i, data_to_fw[i]); + + halrf_fill_h2c_cmd(rf, len, FWCMD_H2C_GET_MCCCH, 0xa, H2CB_TYPE_DATA, (u32 *) data_to_fw); + + return; +} + +void halrf_before_one_shot_enable_8852b(struct rf_info *rf) { + + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + + /* set 0x80d4[21:16]=0x03 (before oneshot NCTL) to get report later */ + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x03); + + RF_DBG(rf, DBG_RF_RFK, "======> before set one-shot bit, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD)); +} + + +bool halrf_one_shot_nctl_done_check_8852b(struct rf_info *rf, enum rf_path path) { + + /* for check status */ + u32 r_bff8 = 0; + u32 r_80fc = 0; + bool is_ready = false; + u16 count = 1; + + rf->nctl_ck_times[0] = 0; + rf->nctl_ck_times[1] = 0; + + /* for 0xbff8 check NCTL DONE */ + while (count < 2000) { + r_bff8 = halrf_rreg(rf, 0xbff8, MASKBYTE0); + + if (r_bff8 == 0x55) { + is_ready = true; + break; + } + halrf_delay_us(rf, 10); + count++; + } + + halrf_delay_us(rf, 1); + /* txgapk_info->txgapk_chk_cnt[path][id][0] = count; */ + rf->nctl_ck_times[0] = count; + + RF_DBG(rf, DBG_RF_RFK, "======> check 0xBFF8[7:0] = 0x%x, IsReady = %d, ReadTimes = %d,delay 1 us\n", r_bff8, is_ready, count); + + + /* for 0x80fc check NCTL DONE */ + count = 1; + is_ready = false; + while (count < 2000) { + r_80fc = halrf_rreg(rf, 0x80fc, MASKLWORD); + + if (r_80fc == 0x8000) { + is_ready = true; + break; + } + halrf_delay_us(rf, 1); + count++; + } + + halrf_delay_us(rf, 1); + /* txgapk_info->txgapk_chk_cnt[path][id][1] = count; */ + rf->nctl_ck_times[1] = count; + + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + + RF_DBG(rf, DBG_RF_RFK, "======> check 0x80fc[15:0] = 0x%x, IsReady = %d, ReadTimes = %d, 0x%x= 0x%x \n", r_80fc, is_ready, count, 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD) ); + + return is_ready; +} + +static u32 check_rfc_reg[] = {0x9f, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x10000, 0x1, 0x10001, + 0x5, 0x10005, 0x8, 0x18, 0x10018, + 0x2, 0x10002, 0x11, 0x10011, 0x53, + 0x10055, 0x58, 0x63, 0x6e, 0x6f, + 0x7e, 0x7f, 0x80, 0x81, 0x8d, + 0x8f, 0x90, 0x92, 0x93, 0xa0, + 0xb2, 0xc5}; +static u32 check_dack_reg[] = {0x12a0, 0x32a0, 0x12b8, 0x32b8, 0x030c, + 0x032c, 0xc000, 0xc004, 0xc020, 0xc024, + 0xc100, 0xc104, 0xc120, 0xc124, 0xc0d4, + 0xc1d4, 0xc0f0, 0xc0f4, 0xc1f0, 0xc1f4, + 0xc05c, 0xc080, 0xc048, 0xc06c, 0xc060, + 0xc084, 0xc05c, 0xc080, 0xc048, 0xc06c, + 0xc060, 0xc084}; +static u32 check_iqk_reg[] = {0x8000, 0x8004, 0x8008, 0x8080, 0x808c, + 0x8120, 0x8124, 0x8138, 0x813c, 0x81dc, + 0x8220, 0x8224, 0x8238, 0x823c, 0x82dc, + 0x9fe0, 0x9fe4, 0x9fe8, 0x9fec, 0x9f30, + 0x9f40, 0x9f50, 0x9f60, 0x9f70, 0x9f80, + 0x9f90, 0x9fa0}; +static u32 check_dpk_reg[] = {0x80b0, 0x81bc, 0x82bc, 0x81b4, 0x82b4, + 0x81c4, 0x82c4, 0x81c8, 0x82c8, 0x58d4, + 0x78d4}; +static u32 check_tssi_reg[] = {0x0304, 0x5818, 0x581c, 0x5820, 0x1c60, + 0x1c44, 0x5838, 0x5630, 0x5634, 0x58f8, + 0x12c0, 0x120c, 0x1c04, 0x1c0c, 0x1c18, + 0x7630, 0x7634, 0x7818, 0x781c, 0x7820, + 0x3c60, 0x3c44, 0x7838, 0x78f8, 0x32c0, + 0x320c, 0x3c04, 0x3c0c, 0x3c18}; + +void halrf_quick_checkrf_8852b(struct rf_info *rf) +{ + u32 path, temp, i; + u32 len = sizeof(check_rfc_reg) / sizeof(u32); + u32 *add = (u32 *)check_rfc_reg; + + /*check RFC*/ + RF_DBG(rf, DBG_RF_CHK, "======RFC======\n"); + for (path = 0; path < 2; path++) { + for (i = 0; i < len; i++ ) { + temp = halrf_rrf(rf, path, add[i], MASKRF); + RF_DBG(rf, DBG_RF_CHK, "RF%d 0x%x = 0x%x\n", + path, + add[i], + temp); + } + } + /*check DACK*/ + RF_DBG(rf, DBG_RF_CHK, "======DACK======\n"); + len = sizeof(check_dack_reg) / sizeof(u32); + add = check_dack_reg; + for (i = 0; i < len; i++ ) { + temp = halrf_rreg(rf, add[i], MASKDWORD); + RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n", + add[i], + temp); + } + /*check IQK*/ + RF_DBG(rf, DBG_RF_CHK, "======IQK======\n"); + len = sizeof(check_iqk_reg) / sizeof(u32); + add = check_iqk_reg; + + for (i = 0; i < len; i++ ) { + temp = halrf_rreg(rf, add[i], MASKDWORD); + RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n", + add[i], + temp); + } + /*check DPK*/ + RF_DBG(rf, DBG_RF_CHK, "======DPK======\n"); + len = sizeof(check_dpk_reg) / sizeof(u32); + add = check_dpk_reg; + for (i = 0; i < len; i++ ) { + temp = halrf_rreg(rf, add[i], MASKDWORD); + RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n", + add[i], + temp); + } + /*check TSSI*/ + RF_DBG(rf, DBG_RF_CHK, "======TSSI======\n"); + len = sizeof(check_tssi_reg) / sizeof(u32); + add = check_tssi_reg; + for (i = 0; i < len; i++ ) { + temp = halrf_rreg(rf, add[i], MASKDWORD); + RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n", + add[i], + temp); + } +} + +static u32 backup_mac_reg_8852b[] = {0x0}; +static u32 backup_bb_reg_8852b[] = {0x2344}; +static u32 backup_rf_reg_8852b[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5}; + +#if 1 +static struct halrf_iqk_ops iqk_ops= { + .iqk_kpath = halrf_kpath_8852b, + .iqk_mcc_page_sel = iqk_mcc_page_sel_8852b, + .iqk_get_ch_info = iqk_get_ch_info_8852b, + .iqk_preset = iqk_preset_8852b, + .iqk_macbb_setting = iqk_macbb_setting_8852b, + .iqk_start_iqk = iqk_start_iqk_8852b, + .iqk_restore = iqk_restore_8852b, + .iqk_afebb_restore = iqk_afebb_restore_8852b, +}; + +struct rfk_iqk_info rf_iqk_hwspec_8852b = { + .rf_iqk_ops = &iqk_ops, + .rf_max_path_num = 2, + .rf_iqk_version = iqk_version_8852b, + .rf_iqk_ch_num = 2, + .rf_iqk_path_num = 2, + +#if 0 + .backup_mac_reg = backup_mac_reg_8852b, + .backup_mac_reg_num = ARRAY_SIZE(backup_mac_reg_8852b), +#else + .backup_mac_reg = backup_mac_reg_8852b, + .backup_mac_reg_num = 0, +#endif + + .backup_bb_reg = backup_bb_reg_8852b, + .backup_bb_reg_num = ARRAY_SIZE(backup_bb_reg_8852b), + .backup_rf_reg = backup_rf_reg_8852b, + .backup_rf_reg_num = ARRAY_SIZE(backup_rf_reg_8852b), +}; + +#endif +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.h new file mode 100644 index 0000000..3be14df --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_8852B_H__ +#define __HALRF_8852B_H__ +#ifdef RF_8852B_SUPPORT + +#define RXDCK_VER_8852B 0x1 +#define RCK_VER_8852B 0x1 + +void halrf_lo_test_8852b(struct rf_info *rf, bool is_on, enum rf_path path); +u8 halrf_kpath_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx); +void halrf_set_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe); +void halrf_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe); +void halrf_rx_dck_onoff_8852b(struct rf_info *rf, bool is_enable); +void halrf_rck_8852b(struct rf_info *rf, enum rf_path path); +void halrf_rf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb); +void halrf_drf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb); +void halrf_bf_config_rf_8852b(struct rf_info *rf); +extern struct rfk_iqk_info rf_iqk_hwspec_8852b; +void halrf_dpk_init_8852b(struct rf_info *rf); +bool halrf_ctrl_ch_8852b(struct rf_info *rf, u8 central_ch); +bool halrf_ctrl_bw_8852b(struct rf_info *rf, enum channel_width bw); +void halrf_rxbb_bw_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw); +void halrf_fw_ntfy_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx); +void halrf_disconnect_notify_8852b(struct rf_info *rf, struct rtw_chan_def *chandef ) ; +bool halrf_check_mcc_ch_8852b(struct rf_info *rf, struct rtw_chan_def *chandef) ; +void halrf_quick_checkrf_8852b(struct rf_info *rf); + +void halrf_before_one_shot_enable_8852b(struct rf_info *rf); +bool halrf_one_shot_nctl_done_check_8852b(struct rf_info *rf, enum rf_path path); +void halrf_lck_check_8852b(struct rf_info *rf); +#endif +#endif /* __HALRF_8852b_H__ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.c new file mode 100644 index 0000000..859f138 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.c @@ -0,0 +1,286 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT + +u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path) +{ + halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1); + halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x0); + halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1); + + halrf_delay_10us(rf, 20); + + return (u8)halrf_rrf(rf, rf_path, 0x42, 0x0007e); +} + +u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 addr, u32 mask) +{ + struct rtw_hal_com_t *hal = rf->hal_com; + u32 result, ori_val, bit_shift, reg_val; + + result = rtw_hal_mac_get_pwr_reg(hal, phy, addr, &ori_val); + if (result) + RF_WARNING("=======>%s Get MAC(0x%x) fail, error code=%d\n", + __func__, addr, result); + else + RF_DBG(rf, DBG_RF_POWER, "Get MAC(0x%x) ok!!! 0x%08x\n", + addr, ori_val); + + bit_shift = halrf_cal_bit_shift(mask); + reg_val = (ori_val & mask) >> bit_shift; + + return reg_val; +} + +u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 addr, u32 mask, u32 val) +{ + struct rtw_hal_com_t *hal = rf->hal_com; + u32 result; + + result = rtw_hal_mac_write_msk_pwr_reg(hal, phy, addr, mask, val); + if (result) { + RF_WARNING("=======>%s Set MAC(0x%x[0x%08x]) fail, error code=%d\n", + __func__, addr, mask, result); + return false; + } else + RF_DBG(rf, DBG_RF_POWER, "Set MAC(0x%x[0x%08x])=0x%08x ok!!! \n", + addr, mask, val); + + return result; +} + +bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u32 result; + s32 tmp_pwr; + u8 phy = 0; + u32 all_time_control = 0; + u32 gnt_bt_control = 0; + + RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__); + + all_time_control = tx_power_val & 0xffff; + gnt_bt_control = (tx_power_val & 0xffff0000) >> 16; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl]tx_power_val=0x%x all_time_control=0x%x gnt_bt_control=0x%x\n", + tx_power_val, all_time_control, gnt_bt_control); + + if (all_time_control == 0xffff) { + /*Coex Disable*/ + pwr->coex_pwr_ctl_enable = false; + pwr->coex_pwr = 0; + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Disable all_time_control=0xffff!!!\n"); + } else if (all_time_control == 0xeeee) { + /*DPK Disable*/ + pwr->dpk_pwr_ctl_enable = false; + pwr->dpk_pwr = 0; + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Disable all_time_control=0xeeee\n"); + } else { + if (all_time_control & BIT(15)) { + /*DPK*/ + pwr->dpk_pwr_ctl_enable = true; + pwr->dpk_pwr = all_time_control & 0x1ff; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Enable Set pwr->dpk_pwr = %d\n", + pwr->dpk_pwr); + } else { + /*Coex*/ + pwr->coex_pwr_ctl_enable = true; + pwr->coex_pwr = all_time_control & 0x1ff; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Enable Set pwr->coex_pwr = %d\n", + pwr->coex_pwr); + } + } + + if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == false) { + tmp_pwr = pwr->coex_pwr; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=false tmp_pwr=%d\n", + tmp_pwr); + } else if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == true) { + tmp_pwr = pwr->dpk_pwr; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=false dpk_pwr_ctl_enable=true tmp_pwr=%d\n", + tmp_pwr); + } else if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == true) { + if (pwr->coex_pwr > pwr->dpk_pwr) + tmp_pwr = pwr->dpk_pwr; + else + tmp_pwr = pwr->coex_pwr; + + RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=true tmp_pwr=%d\n", + tmp_pwr); + } else + tmp_pwr = 0; + + if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == false) { + /*all-time control Disable*/ + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0xfffffc00, 0x0); + + if (result) { + RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n", + __func__, result); + return false; + } else { + RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n"); + rf->is_coex = false; + } + } else { + /*all-time control*/ + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0xfffffc00, ((tmp_pwr & 0x1ff) | BIT(9))); + if (result) { + RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n", + __func__, result); + return false; + } else { + RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n"); + rf->is_coex = true; + } + } + + if (gnt_bt_control == 0xffff) { + /*GNT_BT control*/ + + RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n", + __func__, gnt_bt_control); + + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x0); + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xfffff007, 0x0); + if (result) { + RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n", + __func__, result); + return false; + } else { + RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n"); + rf->is_coex = false; + } + } else { + /*GNT_BT control*/ + + RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n", + __func__, gnt_bt_control); + + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x1); + result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xfffff007, ((gnt_bt_control & 0x1ff) << 3)); + if (result) { + RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n", + __func__, result); + return false; + } else { + RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n"); + rf->is_coex = true; + } + } + + return true; +} + +s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf) +{ + u8 tmp_a, tmp_b, tmp; + + tmp_a = halrf_get_thermal(rf, RF_PATH_A); + tmp_b = halrf_get_thermal(rf, RF_PATH_B); + + if (tmp_a > tmp_b) + tmp = tmp_a; + else + tmp = tmp_b; + + if (tmp > 0x32) + return -1; /*Tx duty reduce*/ + else if (tmp < 0x31) + return 1; /*Tx duty up*/ + else + return 0; /*Tx duty the same*/ +} + +s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_xtal_info *xtal_trk = &rf->xtal_track; + u8 thermal_a = 0xff, thermal_b = 0xff; + u8 tmp_a, tmp_b, tmp; + s8 xtal_ofst = 0; + + RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s phy=%d\n", + __func__, phy); + + tmp_a = halrf_get_thermal(rf, RF_PATH_A); + tmp_b = halrf_get_thermal(rf, RF_PATH_B); + halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal_a, 1); + halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal_b, 1); + + if (thermal_a == 0xff || thermal_b == 0xff || + thermal_a == 0x0 || thermal_b == 0x0) { + RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s PG ThermalA=%d ThermalB=%d\n", + __func__, thermal_a, thermal_b); + return 0; + } + + if (tmp_a > tmp_b) { + if (tmp_a > thermal_a) { + tmp = tmp_a - thermal_a; + if (tmp > DELTA_SWINGIDX_SIZE) + tmp = DELTA_SWINGIDX_SIZE - 1; + xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp]; + } else { + tmp = thermal_a - tmp_a; + if (tmp > DELTA_SWINGIDX_SIZE) + tmp = DELTA_SWINGIDX_SIZE - 1; + xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp]; + } + } else { + if (tmp_b > thermal_b) { + tmp = tmp_b - thermal_b; + if (tmp > DELTA_SWINGIDX_SIZE) + tmp = DELTA_SWINGIDX_SIZE - 1; + xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp]; + } else { + tmp = thermal_b - tmp_b; + if (tmp > DELTA_SWINGIDX_SIZE) + tmp = DELTA_SWINGIDX_SIZE - 1; + xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp]; + } + } + + RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalA=%d ThermalA=%d\n", + thermal_a, tmp_a); + + RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalB=%d ThermalB=%d\n", + thermal_b, tmp_b); + + RF_DBG(rf, DBG_RF_XTAL_TRACK, "xtal_ofst[%d]=%d\n", + tmp, xtal_ofst); + + return xtal_ofst; +} + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.h new file mode 100644 index 0000000..7a16343 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_8852B_API_H__ +#define __HALRF_8852B_API_H__ +#ifdef RF_8852B_SUPPORT + +u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path); + +u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 addr, u32 mask); + +u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 addr, u32 mask, u32 val); + +bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val); + +s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf); + +s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf, enum phl_phy_idx phy); + +#endif +#endif /* __INC_PHYDM_API_H_8852B__ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api_ex.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api_ex.h new file mode 100644 index 0000000..7b9a7dc --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api_ex.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_8852B_API_EX_H__ +#define __HALRF_8852B_API_EX_H__ +#ifdef RF_8852B_SUPPORT + +#endif +#endif /* __INC_PHYDM_API_H_8852B__ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.c new file mode 100644 index 0000000..dc60ace --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.c @@ -0,0 +1,702 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT + +#define t_avg 100 + + +void halrf_afe_init_8852b(struct rf_info *rf) +{ + halrf_wmac32(rf, 0x8040, 0xf); + halrf_wreg(rf, 0xc0d4, MASKDWORD, 0x4486888c); + halrf_wreg(rf, 0xc0d8, MASKDWORD, 0xc6ba10e0); + halrf_wreg(rf, 0xc0dc, MASKDWORD, 0x30c52868); + halrf_wreg(rf, 0xc0e0, MASKDWORD, 0x05008128); + halrf_wreg(rf, 0xc0e4, MASKDWORD, 0x0000272b); + halrf_wreg(rf, 0xc1d4, MASKDWORD, 0x4486888c); + halrf_wreg(rf, 0xc1d8, MASKDWORD, 0xc6ba10e0); + halrf_wreg(rf, 0xc1dc, MASKDWORD, 0x30c52868); + halrf_wreg(rf, 0xc1e0, MASKDWORD, 0x05008128); + halrf_wreg(rf, 0xc1e4, MASKDWORD, 0x0000272b); +} +void halrf_dack_init_8852b(struct rf_info *rf) +{ +} + +void halrf_drck_8852b(struct rf_info *rf) +{ + u32 c; + u32 rck_d; + RF_DBG(rf, DBG_RF_DACK, "[DACK]Ddie RCK start!!!\n"); + halrf_wreg(rf, 0xc0cc, BIT(6), 0x1); + c = 0; + while (halrf_rreg(rf, 0xc0d0, BIT(3)) == 0) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]DRCK timeout\n"); + break; + } + } + + halrf_wreg(rf, 0xc0cc, BIT(6), 0x0); + halrf_wreg(rf, 0xc094, BIT(9), 0x1); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0xc094, BIT(9), 0x0); + + /*manual write for LPS*/ + rck_d = halrf_rreg(rf, 0xc0d0, 0xf8000); + /*RCK_SEL=0*/ + halrf_wreg(rf, 0xc0cc, BIT(9), 0x0); + halrf_wreg(rf, 0xc0cc, 0x1f, rck_d); + RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc0cc = 0x%x\n", halrf_rreg(rf, 0xc0cc, MASKDWORD)); +} + +void halrf_addck_backup_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + + halrf_wreg(rf, 0xc0f4, 0x300, 0x0); + dack->addck_d[0][0] = (u16)halrf_rreg(rf, 0xc0fc,0xffc00) ; + dack->addck_d[0][1] = (u16)halrf_rreg(rf, 0xc0fc,0x003ff) ; + + halrf_wreg(rf, 0xc1f4, 0x300, 0x0); + dack->addck_d[1][0] = (u16)halrf_rreg(rf, 0xc1fc,0xffc00) ; + dack->addck_d[1][1] = (u16)halrf_rreg(rf, 0xc1fc,0x003ff) ; +} + +void halrf_addck_reload_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + /*S0*/ + halrf_wreg(rf, 0xc0f0, 0x3ff0000, dack->addck_d[0][0]); + halrf_wreg(rf, 0xc0f4, 0xf, (dack->addck_d[0][1] >> 6)); + halrf_wreg(rf, 0xc0f0, 0xfc000000, (dack->addck_d[0][1] & 0x3f)); + /*manual*/ + halrf_wreg(rf, 0xc0f4, 0x30, 0x3); + /*S1*/ + halrf_wreg(rf, 0xc1f0, 0x3ff0000, dack->addck_d[1][0]); + halrf_wreg(rf, 0xc1f4, 0xf, (dack->addck_d[1][1] >> 6)); + halrf_wreg(rf, 0xc1f0, 0xfc000000, (dack->addck_d[1][1] & 0x3f)); + /*manual*/ + halrf_wreg(rf, 0xc1f4, 0x30, 0x3); +} + +void halrf_dack_backup_s0_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u8 i; +// u32 temp; + +// halrf_wreg(rf, 0x5e00, BIT(3), 0x1); +// halrf_wreg(rf, 0x5e50, BIT(3), 0x1); + halrf_wreg(rf, 0x12b8, BIT(30), 0x1); + /*MSBK*/ +#if 0 + for (i = 0; i < 0x10; i++) { + /*S0*/ + halrf_wreg(rf, 0xc000, 0x1e, i); + temp = (u8)halrf_rreg(rf, 0xc04c, 0x7fc0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc04c %d = 0x%x\n", + i, temp); + } + + for (i = 0; i < 0x10; i++) { + /*S0*/ + halrf_wreg(rf, 0xc020, 0x1e, i); + temp = (u8)halrf_rreg(rf, 0xc070, 0x7fc0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc070 %d = 0x%x\n", + i, temp); + } +#endif + for (i = 0; i < 0x10; i++) { + /*S0*/ + halrf_wreg(rf, 0xc000, 0x1e, i); + dack->msbk_d[0][0][i] = (u8)halrf_rreg(rf, 0xc05c, 0xff000000); + halrf_wreg(rf, 0xc020, 0x1e, i); + dack->msbk_d[0][1][i] = (u8)halrf_rreg(rf, 0xc080, 0xff000000); + } + + + /*biasK*/ + dack->biask_d[0][0] = (u16)halrf_rreg(rf, 0xc048, 0xffc); + dack->biask_d[0][1] = (u16)halrf_rreg(rf, 0xc06c, 0xffc); + /*DADCK*/ + dack->dadck_d[0][0] = (u8)halrf_rreg(rf, 0xc060, 0xff000000); + dack->dadck_d[0][1] = (u8)halrf_rreg(rf, 0xc084, 0xff000000); +} + +void halrf_dack_backup_s1_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u8 i; +// u32 temp; + +// halrf_wreg(rf, 0x7e00, BIT(3), 0x1); +// halrf_wreg(rf, 0x7e50, BIT(3), 0x1); + halrf_wreg(rf, 0x32b8, BIT(30), 0x1); + /*MSBK*/ +#if 0 + for (i = 0; i < 0x10; i++) { + /*S0*/ + halrf_wreg(rf, 0xc100, 0x1e, i); + temp = (u8)halrf_rreg(rf, 0xc14c, 0x7fc0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc14c %d = 0x%x\n", + i, temp); + } + + for (i = 0; i < 0x10; i++) { + /*S0*/ + halrf_wreg(rf, 0xc120, 0x1e, i); + temp = (u8)halrf_rreg(rf, 0xc170, 0x7fc0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc170 %d = 0x%x\n", + i, temp); + } +#endif + + for (i = 0; i < 0x10; i++) { + /*S1*/ + halrf_wreg(rf, 0xc100, 0x1e, i); + dack->msbk_d[1][0][i] = (u8)halrf_rreg(rf, 0xc15c, 0xff000000); + halrf_wreg(rf, 0xc120, 0x1e, i); + dack->msbk_d[1][1][i] = (u8)halrf_rreg(rf, 0xc180, 0xff000000); + } + /*biasK*/ + dack->biask_d[1][0] = (u16)halrf_rreg(rf, 0xc148, 0xffc); + dack->biask_d[1][1] = (u16)halrf_rreg(rf, 0xc16c, 0xffc); + /*DADCK*/ + dack->dadck_d[1][0] = (u8)halrf_rreg(rf, 0xc160, 0xff000000); + dack->dadck_d[1][1] = (u8)halrf_rreg(rf, 0xc184, 0xff000000); +} + +void halrf_dack_reload_by_path_8852b(struct rf_info *rf, enum rf_path path) +{ + struct halrf_dack_info *dack = &rf->dack; + u8 i; + u32 oft; + + if (path == RF_PATH_A) + oft = 0; + else + oft = 0x100; + /*MSBK*/ + for (i = 0; i < 16; i++) { + halrf_wreg(rf, 0xc000+ oft, 0x1e, i); + halrf_wreg(rf, 0xc004+ oft, 0x3fc0, dack->msbk_d[path][0][i]); + } + for (i = 0; i < 16; i++) { + halrf_wreg(rf, 0xc020+ oft, 0x1e, i); + halrf_wreg(rf, 0xc024+ oft, 0x3fc0, dack->msbk_d[path][1][i]); + } + + /*biask*/ + halrf_wreg(rf, 0xc004+ oft, 0x3ff00000, dack->biask_d[path][0]); + halrf_wreg(rf, 0xc024+ oft, 0x3ff00000, dack->biask_d[path][1]); + /*DADCK*/ +} + +void halrf_dack_reload_8852b(struct rf_info *rf, enum rf_path path) +{ + u32 oft; + + if (path == RF_PATH_A) + oft = 0; + else + oft = 0x100; + + halrf_wreg(rf, 0xc004 + oft, 0x3, 0x2); + halrf_wreg(rf, 0xc024 + oft, 0x3, 0x2); + halrf_wreg(rf, 0xc004 + oft, BIT(5), 0x1); + halrf_wreg(rf, 0xc024 + oft, BIT(5), 0x1); + halrf_dack_reload_by_path_8852b(rf, path); + halrf_wreg(rf, 0xc004 + oft, 0x3, 0x0); + halrf_wreg(rf, 0xc024 + oft, 0x3, 0x0); +} + +void halrf_check_addc_8852b(struct rf_info *rf, enum rf_path path) +{ + u32 temp, dc_re, dc_im; + u32 i, m, p, t; + u32 re[t_avg], im[t_avg]; +#if 1 + halrf_wreg(rf, 0x20f4, BIT(24), 0x0); + halrf_wreg(rf, 0x20f8, 0x80000000, 0x1); + halrf_wreg(rf, 0x20f0, 0xff0000, 0x1); + halrf_wreg(rf, 0x20f0, 0xf00, 0x2); + halrf_wreg(rf, 0x20f0, 0xf, 0x0); + if (path == RF_PATH_A) + halrf_wreg(rf, 0x20f0, 0xc0, 0x2); + else + halrf_wreg(rf, 0x20f0, 0xc0, 0x3); + for (i = 0; i < t_avg; i++) { + temp = halrf_rreg(rf, 0x1730, 0xffffffff); + re[i] = (temp & 0xfff000) >> 12; + im[i] = temp & 0xfff; +// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n", +// path, re[i], im[i]); + } +#else + for (i = 0; i < t_avg; i++) { + if (path == RF_PATH_A) + temp = halrf_rreg(rf, 0x1c8c, MASKDWORD); + else + temp = halrf_rreg(rf, 0x3c8c, MASKDWORD); + + re[i] = (temp & 0xfff000) >> 12; + im[i] = temp & 0xfff; +// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n", +// path, re[i], im[i]); + } + +#endif + m = 0; + p = 0; + for (i = 0; i < t_avg; i++) { + if (re[i] > 0x800) + m = (0x1000 - re[i]) + m; + else + p = re[i] + p; + } + + if (p > m) { + t = p - m; + t = t / t_avg; + } else { + t = m - p; + t = t / t_avg; + if (t != 0x0) + t = 0x1000 - t; + } + dc_re = t; + + m = 0; + p = 0; + for (i = 0; i < t_avg; i++) { + if (im[i] > 0x800) + m = (0x1000 - im[i]) + m; + else + p = im[i] + p; + } + + if (p > m) { + t = p - m; + t = t / t_avg; + } else { + t = m - p; + t = t / t_avg; + if (t != 0x0) + t = 0x1000 - t; + } + dc_im = t; + + RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", + path, dc_re, dc_im); +} + +void halrf_addck_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u32 c; + /*S0*/ +#if 1 + /*manual off*/ + halrf_wreg(rf, 0xc0f4, 0x30, 0x0); + halrf_wreg(rf, 0xc1d4, 0x30, 0x0); + /*1.ADC & clk enable */ + halrf_wreg(rf, 0x12b8, BIT(30), 0x1); + halrf_wreg(rf, 0x032c, BIT(30), 0x0); + /*4.Reset calibration*/ + halrf_wreg(rf, 0x032c, BIT(22), 0x0); + halrf_wreg(rf, 0x032c, BIT(22), 0x1); + + halrf_wreg(rf, 0x030c, 0x0f000000, 0xf); + /*2.ADC input not from RXBB & ADC input short*/ + halrf_wreg(rf, 0x032c, BIT(16), 0x0); + halrf_wreg(rf, 0xc0d4, BIT(1), 0x1); + /*3.release ADC reset*/ + halrf_wreg(rf, 0x030c, 0x0f000000, 0x3); + RF_DBG(rf, DBG_RF_DACK, "[DACK]before S0 ADDCK\n"); + halrf_check_addc_8852b(rf, RF_PATH_A); + /*average 128 times*/ +// halrf_wreg(rf, 0xc0f4, BIT(7) | BIT(6), 0x3); + /*5.trigger dc offset calibration*/ + halrf_wreg(rf, 0xc0f4, BIT(11), 0x1); + halrf_wreg(rf, 0xc0f4, BIT(11), 0x0); + halrf_delay_us(rf, 1); + /*check if cal done*/ + halrf_wreg(rf, 0xc0f4, 0x300, 0x1); + c = 0; + while (halrf_rreg(rf, 0xc0fc, BIT(0)) == 0) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADDCK timeout\n"); + dack->addck_timeout[0] = true; + break; + } + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c); + RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 ADDCK\n"); + halrf_check_addc_8852b(rf, RF_PATH_A); + /*restore*/ + halrf_wreg(rf, 0xc0d4, BIT(1), 0x0); + halrf_wreg(rf, 0x032c, BIT(16), 0x1); + halrf_wreg(rf, 0x030c, 0x0f000000, 0xc); + halrf_wreg(rf, 0x032c, BIT(30), 0x1); + halrf_wreg(rf, 0x12b8, BIT(30), 0x0); +#endif + + /*S1*/ +#if 1 + /*1.ADC & clk enable */ + halrf_wreg(rf, 0x32b8, BIT(30), 0x1); + halrf_wreg(rf, 0x032c, BIT(30), 0x0); + /*4.Reset calibration*/ + halrf_wreg(rf, 0x032c, BIT(22), 0x0); + halrf_wreg(rf, 0x032c, BIT(22), 0x1); + + halrf_wreg(rf, 0x030c, 0x0f000000, 0xf); + /*2.ADC input not from RXBB & ADC input short*/ + halrf_wreg(rf, 0x032c, BIT(16), 0x0); + halrf_wreg(rf, 0xc1d4, BIT(1), 0x1); + /*3.release ADC reset*/ + halrf_wreg(rf, 0x030c, 0x0f000000, 0x3); + RF_DBG(rf, DBG_RF_DACK, "[DACK]before S1 ADDCK\n"); + halrf_check_addc_8852b(rf, RF_PATH_B); + /*average 128 times*/ +// halrf_wreg(rf, 0xc1f4, BIT(7) | BIT(6), 0x3); + /*5.trigger dc offset calibration*/ + halrf_wreg(rf, 0xc1f4, BIT(11), 0x1); + halrf_wreg(rf, 0xc1f4, BIT(11), 0x0); + halrf_delay_us(rf, 1); + /*check if cal done*/ + halrf_wreg(rf, 0xc1f4, 0x300, 0x1); + c = 0; + while (halrf_rreg(rf, 0xc1fc, BIT(0)) == 0) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADDCK timeout\n"); + dack->addck_timeout[1] = true; + break; + } + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c); + RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 ADDCK\n"); + halrf_check_addc_8852b(rf, RF_PATH_B); + /*restore*/ + halrf_wreg(rf, 0xc1d4, BIT(1), 0x0); + halrf_wreg(rf, 0x032c, BIT(16), 0x1); + halrf_wreg(rf, 0x030c, 0x0f000000, 0xc); + halrf_wreg(rf, 0x032c, BIT(30), 0x1); + halrf_wreg(rf, 0x32b8, BIT(30), 0x0); +#endif +} + +void halrf_check_dadc_8852b(struct rf_info *rf, enum rf_path path) +{ + halrf_wreg(rf, 0x032c, BIT(30), 0x0); + halrf_wreg(rf, 0x030c, 0x0f000000, 0xf); + halrf_wreg(rf, 0x030c, 0x0f000000, 0x3); + halrf_wreg(rf, 0x032c, BIT(16), 0x0); + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x12dc, BIT(0), 0x1); + halrf_wreg(rf, 0x12e8, BIT(2), 0x1); + halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x1); + } else { + halrf_wreg(rf, 0x32dc, BIT(0), 0x1); + halrf_wreg(rf, 0x32e8, BIT(2), 0x1); + halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x1); + } + halrf_check_addc_8852b(rf, path); + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x12dc, BIT(0), 0x0); + halrf_wreg(rf, 0x12e8, BIT(2), 0x0); + halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x0); + } else { + halrf_wreg(rf, 0x32dc, BIT(0), 0x0); + halrf_wreg(rf, 0x32e8, BIT(2), 0x0); + halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x0); + } + halrf_wreg(rf, 0x032c, BIT(16), 0x1); +} + +void halrf_dack_8852b_s0(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u32 c = 0; + + /*step 1*/ + halrf_wreg(rf, 0x12a0, BIT(15), 0x1); + halrf_wreg(rf, 0x12a0, 0x7000, 0x3); + /*step 2*/ + halrf_wreg(rf, 0x12b8, BIT(30), 0x1); + halrf_wreg(rf, 0x030c, BIT(28), 0x1); + halrf_wreg(rf, 0x032c, 0x80000000, 0x0); + /*step 3*/ + halrf_wreg(rf, 0xc0d8, BIT(16), 0x1); + /*step 4*/ + halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x3); + /*step 5*/ + halrf_wreg(rf, 0xc004, BIT(30), 0x0); + halrf_wreg(rf, 0xc024, BIT(30), 0x0); + /*step 6*/ + halrf_wreg(rf, 0xc004, 0x3ff00000, 0x30); +// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30); + /*step 7*/ + halrf_wreg(rf, 0xc004, BIT(31) | BIT(30), 0x0); +// halrf_wreg(rf, 0xc024, BIT(31) | BIT(30), 0x0); + /*step 8*/ + halrf_wreg(rf, 0xc004, BIT(17), 0x1); + halrf_wreg(rf, 0xc024, BIT(17), 0x1); + halrf_wreg(rf, 0xc00c, BIT(2), 0x0); + halrf_wreg(rf, 0xc02c, BIT(2), 0x0); + /*step 9*/ /*auto mode*/ + halrf_wreg(rf, 0xc004, BIT(0), 0x1); + halrf_wreg(rf, 0xc024, BIT(0), 0x1); + halrf_delay_us(rf, 1); + /*step 10*/ + c = 0x0; + while ((halrf_rreg(rf, 0xc040, BIT(31)) == 0) || (halrf_rreg(rf, 0xc064, BIT(31)) == 0)) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK timeout\n"); + dack->msbk_timeout[0] = true; + break; + } + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c); + /*step 11*/ + halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x0); + /*step 12*/ + halrf_wreg(rf, 0xc00c, BIT(2), 0x1); + halrf_wreg(rf, 0xc02c, BIT(2), 0x1); + /*step 13*/ + c = 0x0; + while ((halrf_rreg(rf, 0xc05c, BIT(2)) == 0) || (halrf_rreg(rf, 0xc080, BIT(2)) == 0)) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DADCK timeout\n"); + dack->dadck_timeout[0] = true; + break; + } + } + /*step 14*/ /*auto mode off*/ + halrf_wreg(rf, 0xc004, BIT(0), 0x0); + halrf_wreg(rf, 0xc024, BIT(0), 0x0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c); + /*step 15*/ + halrf_wreg(rf, 0xc0d8, BIT(16), 0x0); + /*step 16*/ + halrf_wreg(rf, 0x12a0, BIT(15), 0x0); + halrf_wreg(rf, 0x12a0, 0x7000, 0x7); + + RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 DADCK\n"); +// halrf_check_dadc_8852b(rf, RF_PATH_A); + + /*backup here*/ + halrf_dack_backup_s0_8852b(rf); +// halrf_dack_reload_8852b(rf, RF_PATH_A); + /*step 17*/ + halrf_wreg(rf, 0x12b8, BIT(30), 0x0); +} + +void halrf_dack_8852b_s1(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u32 c = 0; + + /*step 1*/ + halrf_wreg(rf, 0x32a0, BIT(15), 0x1); + halrf_wreg(rf, 0x32a0, 0x7000, 0x3); + /*step 2*/ + halrf_wreg(rf, 0x32b8, BIT(30), 0x1); + halrf_wreg(rf, 0x030c, BIT(28), 0x1); + halrf_wreg(rf, 0x032c, 0x80000000, 0x0); + /*step 3*/ + halrf_wreg(rf, 0xc1d8, BIT(16), 0x1); + /*step 4*/ + halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x3); + /*step 5*/ + halrf_wreg(rf, 0xc104, BIT(30), 0x0); + halrf_wreg(rf, 0xc124, BIT(30), 0x0); + /*step 6*/ + halrf_wreg(rf, 0xc104, 0x3ff00000, 0x30); +// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30); + /*step 7*/ + halrf_wreg(rf, 0xc104, BIT(31) | BIT(30), 0x0); +// halrf_wreg(rf, 0xc124, BIT(31) | BIT(30), 0x0); + /*step 8*/ + halrf_wreg(rf, 0xc104, BIT(17), 0x1); + halrf_wreg(rf, 0xc124, BIT(17), 0x1); + halrf_wreg(rf, 0xc10c, BIT(2), 0x0); + halrf_wreg(rf, 0xc12c, BIT(2), 0x0); + /*step 9*/ /*auto mode*/ + halrf_wreg(rf, 0xc104, BIT(0), 0x1); + halrf_wreg(rf, 0xc124, BIT(0), 0x1); + halrf_delay_us(rf, 1); + /*step 10*/ + c = 0x0; + while((halrf_rreg(rf, 0xc140, BIT(31)) == 0) && (halrf_rreg(rf, 0xc164, BIT(31)) == 0)) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK timeout\n"); + dack->msbk_timeout[1] = true; + break; + } + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c); + /*step 11*/ + halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x0); + /*step 12*/ + halrf_wreg(rf, 0xc10c, BIT(2), 0x1); + halrf_wreg(rf, 0xc12c, BIT(2), 0x1); + halrf_delay_us(rf, 1); + /*step 13*/ + c = 0x0; + while(halrf_rreg(rf, 0xc15c, BIT(2)) == 0 && halrf_rreg(rf, 0xc180, BIT(2)) == 0) { + c++; + halrf_delay_us(rf, 1); + if (c > 10000) { + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DADCK timeout\n"); + dack->dadck_timeout[1] = true; + break; + } + } + /*step 14*/ /*auto mode off*/ + halrf_wreg(rf, 0xc104, BIT(0), 0x0); + halrf_wreg(rf, 0xc124, BIT(0), 0x0); + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c); + /*step 15*/ + halrf_wreg(rf, 0xc1d8, BIT(16), 0x0); + /*step 16*/ + halrf_wreg(rf, 0x32a0, BIT(15), 0x0); + halrf_wreg(rf, 0x32a0, 0x7000, 0x7); + + RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 DADCK\n"); + halrf_check_dadc_8852b(rf, RF_PATH_B); + /*backup here*/ + halrf_dack_backup_s1_8852b(rf); +// halrf_dack_reload_8852b(rf, RF_PATH_B); + /*step 17*/ + halrf_wreg(rf, 0x32b8, BIT(30), 0x0); +} + +void halrf_dack_8852b(struct rf_info *rf) +{ + halrf_dack_8852b_s0(rf); + halrf_dack_8852b_s1(rf); +} + +void halrf_dack_dump_8852b(struct rf_info *rf) +{ + struct halrf_dack_info *dack = &rf->dack; + u8 i; + u8 t; + + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", + dack->addck_d[0][0], dack->addck_d[0][1] ); + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", + dack->addck_d[1][0], dack->addck_d[1][1] ); + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", + dack->dadck_d[0][0], dack->dadck_d[0][1] ); + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", + dack->dadck_d[1][0], dack->dadck_d[1][1] ); + + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", + dack->biask_d[0][0], dack->biask_d[0][1] ); + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", + dack->biask_d[1][0], dack->biask_d[1][1] ); + + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK ic:\n"); + for (i = 0; i < 0x10; i++) { + t = dack->msbk_d[0][0][i]; + RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t); + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK qc:\n"); + for (i = 0; i < 0x10; i++) { + t = dack->msbk_d[0][1][i]; + RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t); + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK ic:\n"); + for (i = 0; i < 0x10; i++) { + t = dack->msbk_d[1][0][i]; + RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t); + } + RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK qc:\n"); + for (i = 0; i < 0x10; i++) { + t = dack->msbk_d[1][1][i]; + RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t); + } +} + +void halrf_dac_cal_8852b(struct rf_info *rf, bool force) +{ + struct halrf_dack_info *dack = &rf->dack; + u32 rf0_0, rf1_0; + u8 phy_map; + + phy_map = (BIT(HW_PHY_0) << 4) | RF_AB; +#if 0 + if (dack->dack_en) { + if (!force) { + halrf_dack_reload_8852a(rf); + RF_DBG(rf, DBG_RF_DACK, "[DACK]reload dack value\n"); + return; + } + } else { + dack->dack_en = true; + } +#endif + dack->dack_done = false; + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK 0x1\n"); + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK start!!!\n"); + rf0_0 = halrf_rrf(rf,RF_PATH_A, 0x0, MASKRF); + rf1_0 = halrf_rrf(rf,RF_PATH_B, 0x0, MASKRF); +#if 1 + halrf_afe_init_8852b(rf); + halrf_drck_8852b(rf); + halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x0); + halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x0); + halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x337e1); + halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x337e1); +// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START); + halrf_addck_8852b(rf); +// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP); + halrf_addck_backup_8852b(rf); + halrf_addck_reload_8852b(rf); +// halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x40001); +// halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x40001); + halrf_wrf(rf, RF_PATH_A, 0x1, MASKRF, 0x0); + halrf_wrf(rf, RF_PATH_B, 0x1, MASKRF, 0x0); +// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START); + halrf_dack_8852b(rf); +// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP); + halrf_dack_dump_8852b(rf); + dack->dack_done = true; + halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, rf0_0); + halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, rf1_0); + halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x1); + halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x1); +#endif + dack->dack_cnt++; + RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK finish!!!\n"); +} +#endif + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.h new file mode 100644 index 0000000..32c5547 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_DACK_8852B_H__ +#define __HALRF_DACK_8852B_H__ +#ifdef RF_8852B_SUPPORT + +#define DACK_VER_8852B 0x5 + +void halrf_dack_recover_8852b(struct rf_info *rf, + u8 offset, + enum rf_path path, + u32 val, + bool reload); +void halrf_dac_cal_8852b(struct rf_info *rf, bool force); +#endif +#endif /* __INC_PHYDM_API_H_8852A__ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.c new file mode 100644 index 0000000..adb38e4 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.c @@ -0,0 +1,1599 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT + +/*8852B DPK ver:0x9 20210713*/ + +void _dpk_bkup_kip_8852b( + struct rf_info *rf, + u32 *reg, + u32 reg_bkup[][DPK_KIP_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < DPK_KIP_REG_NUM_8852B; i++) { + reg_bkup[path][i] = halrf_rreg(rf, reg[i] + (path << 8), MASKDWORD); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup 0x%x = %x\n", reg[i]+ (path << 8), reg_bkup[path][i]); + } +} + +void _dpk_bkup_bb_8852b( + struct rf_info *rf, + u32 *reg, + u32 reg_bkup[DPK_BB_REG_NUM_8852B]) +{ + u8 i; + + for (i = 0; i < DPK_BB_REG_NUM_8852B; i++) { + reg_bkup[i] = halrf_rreg(rf, reg[i], MASKDWORD); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup 0x%x = %x\n", reg[i], reg_bkup[i]); + } +} + +void _dpk_bkup_rf_8852b( + struct rf_info *rf, + u32 *rf_reg, + u32 rf_bkup[][DPK_RF_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < DPK_RF_REG_NUM_8852B; i++) { + rf_bkup[path][i] = halrf_rrf(rf, path, rf_reg[i], MASKRF); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup RF S%d 0x%x = %x\n", + path, rf_reg[i], rf_bkup[path][i]); + } +} + +void _dpk_reload_kip_8852b( + struct rf_info *rf, + u32 *reg, + u32 reg_bkup[][DPK_KIP_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < DPK_KIP_REG_NUM_8852B; i++) { + halrf_wreg(rf, reg[i] + (path << 8), MASKDWORD, reg_bkup[path][i]); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload 0x%x = %x\n", reg[i] + (path << 8), + reg_bkup[path][i]); + } +} + +void _dpk_reload_bb_8852b( + struct rf_info *rf, + u32 *reg, + u32 reg_bkup[DPK_BB_REG_NUM_8852B]) +{ + u8 i; + + for (i = 0; i < DPK_BB_REG_NUM_8852B; i++) { + halrf_wreg(rf, reg[i], MASKDWORD, reg_bkup[i]); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload 0x%x = %x\n", reg[i], + reg_bkup[i]); + } +} + +void _dpk_reload_rf_8852b( + struct rf_info *rf, + u32 *rf_reg, + u32 rf_bkup[][DPK_RF_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < DPK_RF_REG_NUM_8852B; i++) { + halrf_wrf(rf, path, rf_reg[i], MASKRF, rf_bkup[path][i]); + if (DPK_REG_DBG) + RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload RF S%d 0x%x = %x\n", + path, rf_reg[i], rf_bkup[path][i]); + } +} + +u8 _dpk_one_shot_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + enum dpk_id id) +{ + u8 r_bff8 = 0x0, phy_map; + u16 dpk_cmd = 0x0, count = 0; + + phy_map = (BIT(phy) << 4) | BIT(path); + + dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DPK, RFK_ONESHOT_START); + + halrf_wreg(rf, 0x8000, MASKDWORD, dpk_cmd); + + r_bff8 = (u8)halrf_rreg(rf, 0xbff8, MASKBYTE0); + while (r_bff8 != 0x55 && count < 2000) { + halrf_delay_us(rf, 10); + r_bff8 = (u8)halrf_rreg(rf, 0xbff8, MASKBYTE0); + count++; + } + + halrf_wreg(rf, 0x8010, MASKBYTE0, 0x0); + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DPK, RFK_ONESHOT_STOP); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] one-shot for %s = 0x%04x (count=%d)\n", + id == 0x06 ? "LBK_RXIQK" : (id == 0x10 ? "SYNC" : + (id == 0x11 ? "MDPK_IDL" : (id == 0x12 ? "MDPK_MPA" : + (id == 0x13 ? "GAIN_LOSS" : (id == 0x14 ? "PWR_CAL" : + (id == 0x15 ? "DPK_RXAGC" : (id == 0x16 ? "KIP_PRESET" : + (id == 0x17 ? "KIP_RESOTRE" : "DPK_TXAGC")))))))), + dpk_cmd, count); + + if (count == 2000) { + RF_DBG(rf, DBG_RF_DPK, "[DPK] one-shot over 20ms!!!!\n"); + return 1; + } else + return 0; +} + +void _dpk_information_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 kidx = dpk->cur_idx[path]; + + dpk->bp[path][kidx].band = rf->hal_com->band[phy].cur_chandef.band; + dpk->bp[path][kidx].ch = rf->hal_com->band[phy].cur_chandef.center_ch; + dpk->bp[path][kidx].bw = rf->hal_com->band[phy].cur_chandef.bw; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n", + path, dpk->cur_idx[path], phy, rf->is_tssi_mode[path] ? "on" : "off", + rf->hal_com->dbcc_en ? "on" : "off", + dpk->bp[path][kidx].band == 0 ? "2G" : (dpk->bp[path][kidx].band == 1 ? "5G" : "6G"), + dpk->bp[path][kidx].ch, + dpk->bp[path][kidx].bw == 0 ? "20M" : (dpk->bp[path][kidx].bw == 1 ? "40M" : "80M")); +} + +void _dpk_bb_afe_setting_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kpath) +{ + halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0303); + halrf_wreg(rf, 0x12b8, BIT(30), 0x1); + halrf_wreg(rf, 0x32b8, BIT(30), 0x1); + halrf_wreg(rf, 0x030c, MASKBYTE3, 0x13); + halrf_wreg(rf, 0x032c, MASKHWORD, 0x0041); + halrf_wreg(rf, 0x12b8, BIT(28), 0x1); + halrf_wreg(rf, 0x58c8, BIT(24), 0x1); + halrf_wreg(rf, 0x78c8, BIT(24), 0x1); + halrf_wreg(rf, 0x5864, BIT(31) | BIT(30), 0x3); + halrf_wreg(rf, 0x7864, BIT(31) | BIT(30), 0x3); + halrf_wreg(rf, 0x2008, 0x01FFFFFF, 0x1ffffff); + halrf_wreg(rf, 0x0c1c, BIT(2), 0x1); + halrf_wreg(rf, 0x0700, BIT(27), 0x1); + halrf_wreg(rf, 0x0c70, 0x000003FF, 0x3ff); + halrf_wreg(rf, 0x0c60, BIT(1) | BIT(0), 0x3); + halrf_wreg(rf, 0x0c6c, BIT(0), 0x1); + halrf_wreg(rf, 0x58ac, BIT(27), 0x1); + halrf_wreg(rf, 0x78ac, BIT(27), 0x1); + halrf_wreg(rf, 0x0c3c, BIT(9), 0x1); /*block OFDM CCA*/ + halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/ + halrf_wreg(rf, 0x4490, BIT(31), 0x1); + //halrf_wreg(rf, 0x12a0, BIT(14) | BIT(13) | BIT(12), 0x7); + //halrf_wreg(rf, 0x12a0, BIT(15), 0x1); + //halrf_wreg(rf, 0x12a0, BIT(18) | BIT(17) | BIT(16), 0x3); + //halrf_wreg(rf, 0x12a0, BIT(19), 0x1); + halrf_wreg(rf, 0x12a0, 0x000FF000, 0xbf); /*[19:12]*/ + //halrf_wreg(rf, 0x32a0, BIT(18) | BIT(17) | BIT(16), 0x3); + //halrf_wreg(rf, 0x32a0, BIT(19), 0x1); + halrf_wreg(rf, 0x32a0, BIT(19) | BIT(18) | BIT(17) | BIT(16), 0xb); + //halrf_wreg(rf, 0x0700, BIT(24), 0x1); + //halrf_wreg(rf, 0x0700, BIT(26) | BIT(25), 0x2); + halrf_wreg(rf, 0x0700, BIT(26) | BIT(25) | BIT(24), 0x5); + halrf_wreg(rf, 0x20fc, MASKHWORD, 0x3333); + + halrf_wreg(rf, 0x580c, BIT(15), 0x1); /*txbb_force_rdy*/ + halrf_wreg(rf, 0x5800, MASKLWORD, 0x0000);/*txbb_max_min*/ + halrf_wreg(rf, 0x780c, BIT(15), 0x1); /*txbb_force_rdy*/ + halrf_wreg(rf, 0x7800, MASKLWORD, 0x0000); /*txbb_max_min*/ + + if (rf->hal_com->band[phy].cur_chandef.bw == 2) {/*extend ADC LPF BW*/ + halrf_wreg(rf, 0xc0d8, BIT(13), 0x1); + halrf_wreg(rf, 0xc1d8, BIT(13), 0x1); + } +} + +void _dpk_bb_afe_restore_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kpath) +{ + halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0303); + halrf_wreg(rf, 0x12b8, BIT(30), 0x0); + halrf_wreg(rf, 0x32b8, BIT(30), 0x0); + halrf_wreg(rf, 0x5864, BIT(31) | BIT(30), 0x0); + halrf_wreg(rf, 0x7864, BIT(31) | BIT(30), 0x0); + halrf_wreg(rf, 0x2008, 0x01FFFFFF, 0x0); + halrf_wreg(rf, 0x0c1c, BIT(2), 0x0); + halrf_wreg(rf, 0x0700, BIT(27), 0x0); + halrf_wreg(rf, 0x0c70, 0x000003FF, 0x63); + halrf_wreg(rf, 0x12a0, 0x000FF000, 0x00); + halrf_wreg(rf, 0x32a0, 0x000FF000, 0x00); + halrf_wreg(rf, 0x0700, BIT(26) | BIT(25) | BIT(24), 0x0); + halrf_wreg(rf, 0x5864, BIT(29), 0x0); + halrf_wreg(rf, 0x7864, BIT(29), 0x0); + //halrf_wreg(rf, 0x0c3c, BIT(9), 0x0); /*block OFDM CCA*/ + //halrf_wreg(rf, 0x2344, BIT(31), 0x0); /*block CCK CCA*/ + halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0000); + halrf_wreg(rf, 0x58c8, BIT(24), 0x0); + halrf_wreg(rf, 0x78c8, BIT(24), 0x0); + halrf_wreg(rf, 0x0c3c, BIT(9), 0x0); /*block OFDM CCA*/ + + halrf_wreg(rf, 0x580c, BIT(15), 0x0); /*txbb_force_rdy*/ + halrf_wreg(rf, 0x58e4, BIT(28) | BIT(27), 0x1); /*force rst*/ + halrf_wreg(rf, 0x58e4, BIT(28) | BIT(27), 0x2); /*force rst release*/ + halrf_wreg(rf, 0x780c, BIT(15), 0x0); /*txbb_force_rdy*/ + halrf_wreg(rf, 0x78e4, BIT(28) | BIT(27), 0x1); /*force rst*/ + halrf_wreg(rf, 0x78e4, BIT(28) | BIT(27), 0x2); /*force rst release*/ + + if (rf->hal_com->band[phy].cur_chandef.bw == 2) {/*extend ADC LPF BW*/ + halrf_wreg(rf, 0xc0d8, BIT(13), 0x0); + halrf_wreg(rf, 0xc1d8, BIT(13), 0x0); + } +} + +void _dpk_tssi_pause_8852b( + struct rf_info *rf, + enum rf_path path, + bool is_pause) +{ + halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), is_pause); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d TSSI %s\n", path, + is_pause ? "pause" : "resume"); +} + +void _dpk_tpg_sel_8852b( + struct rf_info *rf, + enum rf_path path, + u8 kidx) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + if (dpk->bp[path][kidx].bw == CHANNEL_WIDTH_80) + halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x0); + else if (dpk->bp[path][kidx].bw == CHANNEL_WIDTH_40) + halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x2); + else + halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x1); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] TPG Select for %s\n", + dpk->bp[path][kidx].bw == CHANNEL_WIDTH_80 ? "80M" : + (dpk->bp[path][kidx].bw == CHANNEL_WIDTH_40 ? "40M" : "20M")); +} + +void _dpk_kip_pwr_clk_on_8852b( + struct rf_info *rf, + enum rf_path path) +{ + /*cip power on*/ + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080); + /*320M*/ + halrf_wreg(rf, 0x8088, MASKDWORD, 0x807f030a); + halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0xce000a08); + + //RF_DBG(rf, DBG_RF_DPK, "[DPK] KIP Power/CLK on\n"); +} + +void _dpk_kip_preset_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx) +{ + _dpk_tpg_sel_8852b(rf, path, kidx); + _dpk_one_shot_8852b(rf, phy, path, KIP_PRESET); +} + +void _dpk_kip_restore_8852b( + struct rf_info *rf, + enum rf_path path) +{ + /*cip power on*/ + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000); + /*CFIR CLK restore*/ + halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000); + /*clk/en/misc*/ + //halrf_wreg(rf, 0x808c, MASKDWORD, 0x00000000); + + //halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0x10010000); + + if (rf->hal_com->cv > 0x0) /*hw txagc_offset*/ + halrf_wreg(rf, 0x81c8 + (path << 8), BIT(15), 0x1); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d restore KIP\n", path); +} + +void _dpk_kip_set_txagc_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 txagc) +{ + halrf_wrf(rf, path, 0x10001, MASKRF, txagc); + halrf_wreg(rf, 0x5864, BIT(29), 0x1); + _dpk_one_shot_8852b(rf, phy, path, DPK_TXAGC); + halrf_wreg(rf, 0x5864, BIT(29), 0x0); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] set TXAGC = 0x%x\n", txagc); +} + +void _dpk_kip_set_rxagc_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path) +{ + halrf_wreg(rf, 0x8078, 0x000FFFFF, halrf_rrf(rf, path, 0x00, MASKRF)); /*copy ARFC 0x00*/ + halrf_wreg(rf, 0x5864, BIT(29), 0x1); /*enable kip control RFC*/ + _dpk_one_shot_8852b(rf, phy, path, DPK_RXAGC); + halrf_wreg(rf, 0x5864, BIT(29), 0x0); /*disable kip control RFC*/ + +#if 1 + halrf_wreg(rf, 0x80d4, 0x000F0000, 0x8); + RF_DBG(rf, DBG_RF_DPK, "[DPK] set RXBB = 0x%x (RF0x0[9:5] = 0x%x)\n", + halrf_rreg(rf, 0x80fc, 0x0000001F), + halrf_rrf(rf, path, 0x00, MASKRFRXBB)); +#endif +} + +void _dpk_read_rxsram_8852b( + struct rf_info *rf) +{ + u32 addr; + + halrf_wreg(rf, 0x80e8, BIT(7), 0x1); /*web_iqrx*/ + halrf_wreg(rf, 0x8074, BIT(31), 0x1); /*rxsram_ctrl_sel*/ + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00020000); /*rpt_sel*/ + + for (addr = 0; addr < 0x200; addr++) { + halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 | addr); + RF_DBG(rf, DBG_RF_DPK, "[DPK] RXSRAM[%03d] = 0x%x\n", addr, + halrf_rreg(rf, 0x80fc, MASKDWORD)); + } + halrf_wreg(rf, 0x80e8, BIT(7), 0x0); /*web_iqrx*/ + halrf_wreg(rf, 0x8074, BIT(31), 0x0); /*rxsram_ctrl_sel*/ +} + +void _dpk_lbk_rxiqk_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path) +{ + u8 i, cur_rxbb; + + cur_rxbb = (u8)halrf_rrf(rf, path, 0x00, MASKRFRXBB); + + halrf_wreg(rf, 0x8074, BIT(31), 0x1); /*RxSRAM_ctrl_sel 0:MDPK; 1:IQK*/ + halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000F, 0x0); /*[3:0] disable all rx_cfir_en*/ + + /*RF setting*/ + halrf_wrf(rf, path, 0x1f, MASKRF, halrf_rrf(rf, path, 0x18, MASKRF)); + halrf_wrf(rf, path, 0x00, MASKRFMODE, 0xd); + halrf_wrf(rf, path, 0x20, BIT(5), 0x1); /*IQKPLL_EN_BCN_A*/ + + if (cur_rxbb >= 0x11) + halrf_wrf(rf, path, 0x98, 0x0000007F, 0x13); /*[6:0] DPK_RXIQK Att*/ + else if (cur_rxbb <= 0xa) + halrf_wrf(rf, path, 0x98, 0x0000007F, 0x00); /*[6:0] DPK_RXIQK Att*/ + else + halrf_wrf(rf, path, 0x98, 0x0000007F, 0x05); /*[6:0] DPK_RXIQK Att*/ + + halrf_wrf(rf, path, 0x85, BIT(1) | BIT(0), 0x0); /*lower LNA LDO out*/ + + halrf_wrf(rf, path, 0x1e, BIT(19), 0x0); + halrf_wrf(rf, path, 0x1e, MASKRF, 0x80014); /*POW IQKPLL, 9.25MHz offset for IQKPLL*/ + + for (i = 0; i < 7; i++) + halrf_delay_us(rf, 10); /*IQKPLL's settling time*/ + + halrf_wreg(rf, 0x5864, BIT(29), 0x1); + halrf_wreg(rf, 0x802c, 0x0FFF0000, 0x025); /*[27:16] Rx_tone_idx=0x025 (9.25MHz)*/ + + _dpk_one_shot_8852b(rf, phy, path, LBK_RXIQK); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, halrf_rreg(rf, 0x813c, MASKDWORD)); + + halrf_wreg(rf, 0x5864, BIT(29), 0x0); + + halrf_wrf(rf, path, 0x20, BIT(5), 0x0); /*disable RXIQK PLL*/ + //halrf_wrf(rf, path, 0x1e, BIT(19), 0x0); /*POW IQKPLL*/ + + halrf_wreg(rf, 0x8074, BIT(31), 0x0); /*RxSRAM_ctrl_sel 0:MDPK; 1:IQK*/ + halrf_wreg(rf, 0x80d0, BIT(21) | BIT(20), 0x0); + halrf_wreg(rf, 0x81dc + (path << 8), BIT(1), 0x1); /*auto*/ + halrf_wrf(rf, path, 0x00, MASKRFMODE, 0x5); +} + +void _dpk_get_thermal_8852b(struct rf_info *rf, u8 kidx, enum rf_path path) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + //halrf_wreg(rf, 0x80d4, 0x003F0000, 0x32); + + //RF_DBG(rf, DBG_RF_DPK, "[DPK] thermal@DPK (by KIP)= 0x%x\n", halrf_rreg(rf, 0x80fc, 0x0000003F)); + + dpk->bp[path][kidx].ther_dpk = halrf_get_thermal_8852b(rf, path); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] thermal@DPK (by RFC)= 0x%x\n", dpk->bp[path][kidx].ther_dpk); +} + +void _dpk_tx_mapping_8852b( + struct rf_info *rf, + enum rf_path path, + u8 kidx, + u8 txagc) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u16 table_g[18] = {0xa043, 0xb043, 0xc043, 0xd043, 0xe043, + 0xf043, 0xa053, 0xb053, 0xc053, 0xd053, + 0xe053, 0xf053, 0x9063, 0xa063, 0xb063, + 0xc063, 0xd063, 0xe063}; + u16 table_a[18] = {0xd033, 0xe033, 0xf033, 0x3043, 0x4043, + 0x5043, 0x4053, 0x5053, 0x6053, 0x3063, + 0x4063, 0x5063, 0x6063, 0x7063, 0x8063, + 0x9063, 0xa063, 0xb063}; + u16 tx_gain = 0; + + if (dpk->bp[path][kidx].band == BAND_ON_24G) + tx_gain = table_g[txagc - 0x2e]; + if (dpk->bp[path][kidx].band == BAND_ON_5G) + tx_gain = table_a[txagc - 0x2e]; + + halrf_wrf(rf, path, 0x11, MASKRF, tx_gain); +} + +void _dpk_rf_setting_8852b( + struct rf_info *rf, + u8 gain, + enum rf_path path, + u8 kidx) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + if (dpk->bp[path][kidx].band == BAND_ON_24G) { /*2G*/ + halrf_wrf(rf, path, 0x00, MASKRF, 0x50220); + /*att*/ + halrf_wrf(rf, path, 0x83, 0x000FF, 0xf2); + /*TIA*/ + halrf_wrf(rf, path, 0xdf, BIT(12), 0x1); + halrf_wrf(rf, path, 0x9e, BIT(8), 0x1); + } else { /*5G*/ + halrf_wrf(rf, path, 0x00, MASKRF, 0x50220); + /*switch + att*/ + halrf_wrf(rf, path, 0x8c, 0x0FE00, 0x5); /*[15:9]*/ + /*TIA*/ + halrf_wrf(rf, path, 0xdf, BIT(12), 0x1); + halrf_wrf(rf, path, 0x9e, BIT(8), 0x1); + /*RXCIM3*/ + halrf_wrf(rf, path, 0x8b, MASKRF, 0x920FC); + halrf_wrf(rf, path, 0x90, MASKRF, 0x002C0); + halrf_wrf(rf, path, 0x97, MASKRF, 0x38800); + } + /*debug rtxbw*/ + halrf_wrf(rf, path, 0xde, BIT(2), 0x1); + /*txbb filter*/ + halrf_wrf(rf, path, 0x1a, BIT(14) | BIT(13) | BIT(12), dpk->bp[path][kidx].bw + 1); + /*rxbb filter*/ + halrf_wrf(rf, path, 0x1a, BIT(11) | BIT(10), 0x0); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] ARF 0x0/0x11/0x1a = 0x%x/ 0x%x/ 0x%x\n", + halrf_rrf(rf, path, 0x00, MASKRF), + halrf_rrf(rf, path, 0x11, MASKRF), + halrf_rrf(rf, path, 0x1a, MASKRF)); +} + +void _dpk_manual_txcfir_8852b( + struct rf_info *rf, + enum rf_path path, + bool is_manual) +{ + u8 tmp_pad, tmp_txbb; + + if (is_manual) { + halrf_wreg(rf, 0x8140 + (path << 8), BIT(8), 0x1); + /*set pad to pad_man*/ + tmp_pad = (u8)halrf_rrf(rf, path, 0x56, 0x003e0); /*[9:5]*/ + halrf_wreg(rf, 0x8144 + (path << 8), 0x0001f, tmp_pad); /*[4:0]*/ + + /*set txbb to txbb_man*/ + tmp_txbb = (u8)halrf_rrf(rf, path, 0x56, 0x0001f); /*[4:0]*/ + halrf_wreg(rf, 0x8144 + (path << 8), 0x01f00, tmp_txbb); /*[12:8]*/ + + /*cfir load shot*/ + halrf_wreg(rf, 0x81dc + (path << 8), BIT(1) | BIT(0), 0x1); + halrf_wreg(rf, 0x81dc + (path << 8), BIT(1) | BIT(0), 0x0); + + halrf_wreg(rf, 0x81dc + (path << 8), BIT(1), 0x1); /*auto*/ + + RF_DBG(rf, DBG_RF_DPK, "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", + tmp_pad, tmp_txbb); + } else { + halrf_wreg(rf, 0x8140 + (path << 8), BIT(8), 0x0); + RF_DBG(rf, DBG_RF_DPK, "[DPK] disable manual switch TXCFIR\n"); + } +} + +void _dpk_bypass_rxcfir_8852b( + struct rf_info *rf, + enum rf_path path, + bool is_bypass) +{ + if (is_bypass) { + halrf_wreg(rf, 0x813c + (path << 8), BIT(2), 0x1); + halrf_wreg(rf, 0x813c + (path << 8), BIT(0), 0x1); + //halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, 0x00004002); + RF_DBG(rf, DBG_RF_DPK, "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", + 1 + path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD)); + } else { + halrf_wreg(rf, 0x813c + (path << 8), BIT(2), 0x0); + halrf_wreg(rf, 0x813c + (path << 8), BIT(0), 0x0); + RF_DBG(rf, DBG_RF_DPK, "[DPK] restore 0x8%d3c = 0x%x\n", + 1 + path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD)); + } +} + +void _dpk_table_select_8852b( + struct rf_info *rf, + enum rf_path path, + u8 kidx, + u8 gain) +{ + u8 val; + + val = 0x80 + kidx * 0x20 + gain * 0x10; + + halrf_wreg(rf, 0x81ac + (path << 8), MASKBYTE3, val); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", + kidx, gain, val); +} + +bool _dpk_sync_check_8852b( + struct rf_info *rf, + enum rf_path path, + u8 kidx) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u16 dc_i, dc_q; + u8 corr_val, corr_idx; + + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x0); /*rpt_sel*/ + + corr_idx = (u8)halrf_rreg(rf, 0x80fc, 0x000000ff); + corr_val = (u8)halrf_rreg(rf, 0x80fc, 0x0000ff00); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", + path, corr_idx, corr_val); + + dpk->corr_idx[path][kidx] = corr_idx; + dpk->corr_val[path][kidx] = corr_val; + + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x9); /*rpt_sel*/ + + dc_i = (u16)halrf_rreg(rf, 0x80fc, 0x0fff0000); /*[27:16]*/ + dc_q = (u16)halrf_rreg(rf, 0x80fc, 0x00000fff); /*[11:0]*/ + + if (dc_i >> 11 == 1) + dc_i = 0x1000 - dc_i; + if (dc_q >> 11 == 1) + dc_q = 0x1000 - dc_q; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d DC I/Q, = %d / %d\n", path, dc_i, dc_q); + + dpk->dc_i[path][kidx] = dc_i; + dpk->dc_q[path][kidx] = dc_q; + + if ((dc_i > 200) || (dc_q > 200) || (corr_val < 170)) + return true; + else + return false; +} + +bool _dpk_sync_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx) +{ + _dpk_one_shot_8852b(rf, phy, path, SYNC); + + return _dpk_sync_check_8852b(rf, path, kidx); /*1= fail*/ +} + +u16 _dpk_dgain_read_8852b( + struct rf_info *rf) +{ + u16 dgain = 0x0; + + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x0); /*rpt_sel*/ + + dgain = (u16)halrf_rreg(rf, 0x80fc, 0x0FFF0000); /*[27:16]*/ + + RF_DBG(rf, DBG_RF_DPK, "[DPK] DGain = 0x%x\n", dgain); + + return dgain; +} + +s8 _dpk_dgain_mapping_8852b( + struct rf_info *rf, + u16 dgain) +{ + u16 bnd[15] = {0xbf1, 0xaa5, 0x97d, 0x875, 0x789, + 0x6b7, 0x5fc, 0x556, 0x4c1, 0x43d, + 0x3c7, 0x35e, 0x2ac, 0x262, 0x220}; + s8 offset = 0; + + if (dgain >= bnd[0]) + offset = 0x6; + else if ((bnd[0] > dgain) && (dgain >= bnd[1])) + offset = 0x6; + else if ((bnd[1] > dgain) && (dgain >= bnd[2])) + offset = 0x5; + else if ((bnd[2] > dgain) && (dgain >= bnd[3])) + offset = 0x4; + else if ((bnd[3] > dgain) && (dgain >= bnd[4])) + offset = 0x3; + else if ((bnd[4] > dgain) && (dgain >= bnd[5])) + offset = 0x2; + else if ((bnd[5] > dgain) && (dgain >= bnd[6])) + offset = 0x1; + else if ((bnd[6] > dgain) && (dgain >= bnd[7])) + offset = 0x0; + else if ((bnd[7] > dgain) && (dgain >= bnd[8])) + offset = 0xff; + else if ((bnd[8] > dgain) && (dgain >= bnd[9])) + offset = 0xfe; + else if ((bnd[9] > dgain) && (dgain >= bnd[10])) + offset = 0xfd; + else if ((bnd[10] > dgain) && (dgain >= bnd[11])) + offset = 0xfc; + else if ((bnd[11] > dgain) && (dgain >= bnd[12])) + offset = 0xfb; + else if ((bnd[12] > dgain) && (dgain >= bnd[13])) + offset = 0xfa; + else if ((bnd[13] > dgain) && (dgain >= bnd[14])) + offset = 0xf9; + else if (bnd[14] > dgain) + offset = 0xf8; + else + offset = 0x0; + + //RF_DBG(rf, DBG_RF_DPK, "[DPK] DGain offset = %d\n", offset); + + return offset; +} + +u8 _dpk_pas_check_8852b( + struct rf_info *rf) +{ + u8 fail = 0; + + halrf_wreg(rf, 0x80d4, MASKBYTE2, 0x06); /*0x80d6, ctrl_out_Kpack*/ + halrf_wreg(rf, 0x80bc, BIT(14), 0x0); /*query status*/ + halrf_wreg(rf, 0x80c0, MASKBYTE2, 0x08); + + halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x00); /*0x80C3*/ + if (halrf_rreg(rf, 0x80fc, MASKHWORD) == 0x0800) { + fail = 1; + RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS check Fail!!\n"); + } + + return fail; +} + +u8 _dpk_gainloss_read_8852b( + struct rf_info *rf) +{ + u8 result; + + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x6); /*rpt_sel*/ + halrf_wreg(rf, 0x80bc, BIT(14), 0x1); /*query status*/ + + result = (u8)halrf_rreg(rf, 0x80fc, 0x000000F0); /*[7:4]*/ + + RF_DBG(rf, DBG_RF_DPK, "[DPK] tmp GL = %d\n", result); + + return result; +} + +void _dpk_gainloss_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx) +{ + //_dpk_table_select_8852b(rf, path, kidx, 1); + + _dpk_one_shot_8852b(rf, phy, path, GAIN_LOSS); +} + +u8 _dpk_set_offset_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + s8 gain_offset) +{ + u8 txagc; + + txagc = (u8)halrf_rrf(rf, path, 0x10001, MASKRF); + + if (txagc - gain_offset < 0x2e) + txagc = 0x2e; + else if (txagc - gain_offset > 0x3f) + txagc = 0x3f; + else + txagc = txagc - gain_offset; + + _dpk_kip_set_txagc_8852b(rf, phy, path, txagc); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust TxAGC (offset %d) = 0x%x\n", gain_offset, txagc); + + return txagc; +} + +u8 _dpk_pas_read_8852b( + struct rf_info *rf, + u8 is_check) +{ + u8 i; + u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; + + halrf_wreg(rf, 0x80d4, MASKBYTE2, 0x06); /*0x80d6, ctrl_out_Kpack*/ + halrf_wreg(rf, 0x80bc, BIT(14), 0x0); /*query status*/ + halrf_wreg(rf, 0x80c0, MASKBYTE2, 0x08); + + if (is_check) { + halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x00); + val1_i = halrf_rreg(rf, 0x80fc, MASKHWORD); + if (val1_i >= 0x800) + val1_i = 0x1000 - val1_i; + val1_q = halrf_rreg(rf, 0x80fc, MASKLWORD); + if (val1_q >= 0x800) + val1_q = 0x1000 - val1_q; + halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x1f); + val2_i = halrf_rreg(rf, 0x80fc, MASKHWORD); + if (val2_i >= 0x800) + val2_i = 0x1000 - val2_i; + val2_q = halrf_rreg(rf, 0x80fc, MASKLWORD); + if (val2_q >= 0x800) + val2_q = 0x1000 - val2_q; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS_delta = 0x%x\n", + (val1_i * val1_i + val1_q * val1_q) / + (val2_i * val2_i + val2_q * val2_q)); + } else { + for (i = 0; i < 32; i++) { + halrf_wreg(rf, 0x80c0, MASKBYTE3, i); /*0x80C3*/ + RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS_Read[%02d]= 0x%08x\n", i, + halrf_rreg(rf, 0x80fc, MASKDWORD)); + } + } + + if ((val1_i * val1_i + val1_q * val1_q) >= ((val2_i * val2_i + val2_q * val2_q) * 8 / 5)) + return 1; + else + return 0; +} + +u8 _dpk_agc_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx, + u8 init_txagc, + u8 loss_only) +{ + u8 tmp_txagc, tmp_rxbb = 0, i = 0, tmp_gl_idx = 0; + u8 goout = 0, agc_cnt = 0, limited_rxbb = 0; + s8 offset = 0; + u16 dgain = 0; + + tmp_txagc = init_txagc; + + do { + switch (i) { + case 0: /*SYNC and Dgain*/ + if (_dpk_sync_8852b(rf, phy, path, kidx) == true) { + tmp_txagc = 0xff; + goout = 1; + break; + } + + dgain = _dpk_dgain_read_8852b(rf); + + if (loss_only == 1 || limited_rxbb == 1) + i = 2; + else + i = 1; + break; + + case 1: /*Gain adjustment*/ + tmp_rxbb = (u8)halrf_rrf(rf, path, 0x00, MASKRFRXBB); + offset = _dpk_dgain_mapping_8852b(rf, dgain); + + if (tmp_rxbb + offset > 0x1f) { + tmp_rxbb = 0x1f; + limited_rxbb = 1; + } else if (tmp_rxbb + offset < 0) { + tmp_rxbb = 0; + limited_rxbb = 1; + } else + tmp_rxbb = tmp_rxbb + offset; + + halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb); + RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb); +#if 1 + if (offset != 0 || agc_cnt == 0) { + if (rf->hal_com->band[phy].cur_chandef.bw < 2) + _dpk_bypass_rxcfir_8852b(rf, path, true); + else + _dpk_lbk_rxiqk_8852b(rf, phy, path); + } +#endif + if ((dgain > 1922) || (dgain < 342)) + i = 0; + else + i = 2; + + agc_cnt++; + break; + + case 2: /*GAIN_LOSS and idx*/ + _dpk_gainloss_8852b(rf, phy, path, kidx); + tmp_gl_idx = _dpk_gainloss_read_8852b(rf); + /*_dpk_pas_read_8852a(rf, false);*/ + + if ((tmp_gl_idx == 0 && _dpk_pas_read_8852b(rf, true) == 1) || tmp_gl_idx >= 7) + i = 3; /*GL > criterion*/ + else if (tmp_gl_idx == 0) + i = 4; /*GL < criterion*/ + else + i = 5; + break; + + case 3: /*GL > criterion*/ + if (tmp_txagc == 0x2e) { + goout = 1; + RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc@lower bound!!\n"); + } else { + tmp_txagc = _dpk_set_offset_8852b(rf, phy, path, 0x3); /*tx gain -3*/ +#if 0 + if (0x1f - tmp_rxbb > 2) + tmp_rxbb = tmp_rxbb + 2; + else + tmp_rxbb = 0x1f; + + halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb); + RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB = 0x%x\n", tmp_rxbb); +#endif + } + i = 2; + agc_cnt++; + break; + + case 4: /*GL < criterion*/ + if (tmp_txagc == 0x3f) { + goout = 1; + RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc@upper bound!!\n"); + } else { + tmp_txagc = _dpk_set_offset_8852b(rf, phy, path, 0xfe); /*tx gain +2*/ +#if 0 + if (tmp_rxbb - 2 > 0) + tmp_rxbb = tmp_rxbb - 2; + else + tmp_rxbb = 0x0; + + halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb); + RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB = 0x%x\n", tmp_rxbb); +#endif + } + i = 2; + agc_cnt++; + break; + + case 5: /*set tx gain for DPK*/ + tmp_txagc =_dpk_set_offset_8852b(rf, phy, path, tmp_gl_idx); +#if 0 + if (tmp_rxbb + tmp_gl_idx >= 0x1f) + tmp_rxbb = 0x1f; + else + tmp_rxbb = tmp_rxbb + tmp_gl_idx; + + halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb); +#endif + goout = 1; + agc_cnt++; + break; + + default: + goout = 1; + break; + } + } while (!goout && (agc_cnt < 6)); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", + tmp_txagc, tmp_rxbb); + + return tmp_txagc; +} + +void _dpk_set_mdpd_para_8852b( + struct rf_info *rf, + u8 order) +{ + switch (order) { + case 0: /*(5,3,1)*/ + halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order); + halrf_wreg(rf, 0x80a0, 0x00001F00, 0x3); /*[12:8] phase normalize tap*/ + halrf_wreg(rf, 0x8070, 0xF0000000, 0x1); /*[31:28] tx_delay_man*/ + break; + + case 1: /*(5,3,0)*/ + halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order); + halrf_wreg(rf, 0x80a0, 0x00001F00, 0x0); /*[12:8] phase normalize tap*/ + halrf_wreg(rf, 0x8070, 0xF0000000, 0x0); /*[31:28] tx_delay_man*/ + break; + + case 2: /*(5,0,0)*/ + halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order); + halrf_wreg(rf, 0x80a0, 0x00001F00, 0x0); /*[12:8] phase normalize tap*/ + halrf_wreg(rf, 0x8070, 0xF0000000, 0x0); /*[31:28] tx_delay_man*/ + break; + default: + RF_DBG(rf, DBG_RF_DPK, "[DPK] Wrong MDPD order!!(0x%x)\n", order); + break; + } + + RF_DBG(rf, DBG_RF_DPK, "[DPK] Set %s for IDL\n", order == 0x0 ? "(5,3,1)" : + (order == 0x1 ? "(5,3,0)" : "(5,0,0)")); +} + +void _dpk_idl_mpa_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx, + u8 gain) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + /*IDL*/ + if (dpk->bp[path][kidx].bw < CHANNEL_WIDTH_80 && + dpk->bp[path][kidx].band == BAND_ON_5G) + _dpk_set_mdpd_para_8852b(rf, 0x2); /*5,0,0*/ + else + _dpk_set_mdpd_para_8852b(rf, 0x0); /*5,3,1*/ + //_dpk_table_select_8852b(rf, path, kidx, 1); + + _dpk_one_shot_8852b(rf, phy, path, MDPK_IDL); +} + +u8 _dpk_order_convert_8852b( + struct rf_info *rf) +{ + u8 val; + + val = 0x3 >> (u8)halrf_rreg(rf, 0x80a0, 0x00000003); + + /*0x80a0 [1:0] = 0x0 => 0x81bc[26:25] = 0x3 //(5,3,1)*/ + /*0x80a0 [1:0] = 0x1 => 0x81bc[26:25] = 0x1 //(5,3,0)*/ + /*0x80a0 [1:0] = 0x2 => 0x81bc[26:25] = 0x0 //(5,0,0)*/ + + /*0x80a0->val : 0->3; 1->1; 2->0*/ + + RF_DBG(rf, DBG_RF_DPK, "[DPK] convert MDPD order to 0x%x\n", val); + + return val; +} + +u8 _dpk_pwsf_addr_cal_8852b( + struct rf_info *rf, + u8 t1, + u8 t2) +{ + u8 addr; + s8 offset; + + /*w/o TSSI : t2 = cur_thermal*/ + offset = t2 - t1; + addr = 0x78 + (offset << 3); /*due to TPG -3dB, start from 0x78*/ + + return addr; +} + +void _dpk_gs_normalize_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx, + u8 txagc, + u8 gs_ori, + u16 pwsf) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 gs; + u16 sqrt_out; + + if (dpk->bp[path][kidx].bw == 2) /*80M*/ + halrf_wreg(rf, 0x819c + (path << 8), MASKDWORD, 0x000300c0); + else + halrf_wreg(rf, 0x819c + (path << 8), MASKDWORD, 0x00030200); + + halrf_wreg(rf, 0x81c8 + (path << 8), 0x0000003F, txagc); /*man_txagc_vall*/ + halrf_wreg(rf, 0x81c8 + (path << 8), BIT(6), 0x1); /*man_txagc_en*/ + halrf_wreg(rf, 0x81c8 + (path << 8), MASKBYTE2, 0x08); /*man_pwsf_en*/ + halrf_wreg(rf, 0x81c8 + (path << 8), MASKBYTE1, pwsf - 24); /*man_pwsf_val*/ + + _dpk_one_shot_8852b(rf, phy, path, GAIN_CAL); + + halrf_wreg(rf, 0x81d4, 0x003F0000, 0x13); /*rpt_sel = pow_diff */ + sqrt_out = (u16)halrf_rreg(rf, 0x81fc, 0x000001FF); /*[8:0]*/ + + gs = (u8)(gs_ori * sqrt_out >> 8); + + /*ch0/gain0 [6:0]*/ + halrf_wreg(rf, 0x81bc + (path << 8), 0x0000007F, gs); + /*ch0/gain1 [14:8]*/ + halrf_wreg(rf, 0x81bc + (path << 8), 0x00007F00, gs); + /*ch1/gain0 [6:0]*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), 0x0000007F, gs); + /*ch1/gain1 [14:8]*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), 0x00007F00, gs); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] gs_ori/ sqrt_out/ gs_new = 0x%x/ %d/ 0x%x\n", + gs_ori, sqrt_out, gs); + +} + +void _dpk_fill_result_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 kidx, + u8 gain, + u8 txagc) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u16 pwsf = 0x78; + u8 gs = dpk->dpk_gs[phy]; + + halrf_wreg(rf, 0x8104 + (path << 8), BIT(8), kidx); + + /*read agc*/ + //txagc = (u8)(halrf_rrf(rf, path, 0x01, MASKTXPWR) + gain_offset); /*U(6.0)*/ + + /*cal pwsf*/ + //pwsf = _dpk_pwsf_addr_cal_8852b(rf, 0, 0); +#if 0 + /*read gs and normalize*/ + gs = (u8)halrf_rreg(rf, 0x81bc + path * PATH_OFST_8852B + ch * CH_OFST_8852B, + 0x7F << (gain * 8)); + gs = _dpk_gs_normalize_8852b(rf, gs, path); +#endif + RF_DBG(rf, DBG_RF_DPK, "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", + txagc, pwsf, gs); + + /*========== txagc_rf ==========*/ + dpk->bp[path][kidx].txagc_dpk = txagc; + halrf_wreg(rf, 0x81c4 + (path << 8), 0x3F << ((gain << 3) + (kidx << 4)), txagc); + /*ch0/gain0 [5:0]*/ + //halrf_wreg(rf, 0x81c4 + (path << 8), 0x0000003F, txagc); /*txagc_rf*/ + //halrf_wreg(rf, 0x8190 + (path << 8), 0x000001F8, txagc); /*txagc_orig*/ + /*ch0/gain1 [13:8]*/ + //halrf_wreg(rf, 0x81c4 + (path << 8), 0x00003F00, txagc); /*txagc_rf*/ + //halrf_wreg(rf, 0x8190 + (path << 8), 0x01F80000, txagc); /*txagc_orig*/ + /*ch1/gain0 [21:16]*/ + //halrf_wreg(rf, 0x81c4 + (path << 8), 0x003F0000, txagc); + /*ch1/gain1 [29:24]*/ + //halrf_wreg(rf, 0x81c4 + (path << 8), 0x3F000000, txagc); + + /*========== txagc_bb ==========*/ + /*ch0/gain0 [9:0]*/ + //halrf_wreg(rf, 0x81a4 + (path << 8), 0x000003FF, txagc_bb); + /*ch0/gain1 [25:16]*/ + //halrf_wreg(rf, 0x81a4 + (path << 8), 0x03FF0000, bb_gain); + /*ch1/gain0 [9:0]*/ + //halrf_wreg(rf, 0x81a8 + (path << 8), 0x000003FF, txagc_bb); + /*ch1/gain1 [25:16]*/ + //halrf_wreg(rf, 0x81a8 + (path << 8), 0x03FF0000, txagc_bb); + + /*========== pwsf ==========*/ + dpk->bp[path][kidx].pwsf = pwsf; + halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x1FF << (gain << 4), pwsf); + /*ch0/gain0 [8:0]*/ + //halrf_wreg(rf, 0x81b4 + (path << 8), 0x000001FF, pwsf); + /*ch0/gain1 [24:16]*/ + //halrf_wreg(rf, 0x81b4 + (path << 8), 0x01FF0000, pwsf); + /*ch1/gain0 [8:0]*/ + //halrf_wreg(rf, 0x81b8 + (path << 8), 0x000001FF, pwsf); + /*ch1/gain1 [24:16]*/ + //halrf_wreg(rf, 0x81b8 + (path << 8), 0x01FF0000, pwsf); + + /*========== road shot MDPD==========*/ + halrf_wreg(rf, 0x81dc + (path << 8), BIT(16), 0x1); + halrf_wreg(rf, 0x81dc + (path << 8), BIT(16), 0x0); + + //halrf_wreg(rf, 0x81bc + (path << 8), MASKDWORD, 0x075b5b5b); + + /*========== gs & MDPD order ==========*/ + dpk->bp[path][kidx].gs = gs; + if (dpk->dpk_gs[phy] == 0x7f) + halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKDWORD, 0x007f7f7f); + else + halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKDWORD, 0x005b5b5b); + + halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), BIT(26) | BIT(25), _dpk_order_convert_8852b(rf)); + /*order [26:25]*/ + /*ch0*/ + //halrf_wreg(rf, 0x81bc + (path << 8), 0x06000000, _dpk_order_convert_8852b(rf)); + /*ch1*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), 0x06000000, _dpk_order_convert_8852b(rf)); + //halrf_wreg(rf, 0x81bc + (path << 8), 0x007F0000, 0x5b); /*gs2 set to -3dB*/ + /*ch0/gain0 [6:0]*/ + //halrf_wreg(rf, 0x81bc + (path << 8), 0x0000007F, gs); + /*ch0/gain1 [14:8]*/ + //halrf_wreg(rf, 0x81bc + (path << 8), 0x00007F00, gs); + /*ch1/gain0 [6:0]*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), 0x0000007F, gs); + /*ch1/gain1 [14:8]*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), 0x00007F00, gs); + + /*========== mdpd_en ==========*/ + /*ch0*/ + //halrf_wreg(rf, 0x81bc + (path << 8), BIT(24), 0x1); + /*ch1*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), BIT(24), 0x1); + + /*========== release all setting for K==========*/ + //halrf_wreg(rf, 0x81c8, MASKDWORD, 0x0); + halrf_wreg(rf, 0x81a0 + (path << 8), MASKDWORD, 0x0); + + halrf_wreg(rf, 0x8070, 0x80000000, 0x0); /*BIT(31)*/ + + //_dpk_gs_normalize_8852b(rf, path, txagc, gs, pwsf); +} + +void _dpk_coef_read_8852b( + struct rf_info *rf, + enum rf_path path, + u8 kidx, + u8 gain) +{ + u32 reg, reg_start, reg_stop; + + halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00010000); + + reg_start = 0x9500 + kidx * 0xa0 + path * 0x200 + gain * 0x50; + + reg_stop = reg_start + 0x50; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] ===== [Coef of S%d[%d], gain%d] =====\n", + path, kidx, gain); + + for (reg = reg_start; reg < reg_stop ; reg += 4) { + RF_DBG(rf, DBG_RF_DPK, "[DPK][coef_r] 0x%x = 0x%08x\n", reg, + halrf_rreg(rf, reg, MASKDWORD)); + } + halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000000); +} + +bool _dpk_reload_check_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + bool is_reload = false; + u8 idx, cur_band, cur_ch; + + cur_band = rf->hal_com->band[phy].cur_chandef.band; + cur_ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + for (idx = 0; idx < DPK_BKUP_NUM; idx++) { + if ((cur_band == dpk->bp[path][idx].band) && (cur_ch == dpk->bp[path][idx].ch)) { + halrf_wreg(rf, 0x8104 + (path << 8), BIT(8), idx); + dpk->cur_idx[path] = idx; + is_reload = true; + RF_DBG(rf, DBG_RF_DPK, "[DPK] reload S%d[%d] success\n", path, idx); + } + } + + return is_reload; +} + +bool _dpk_main_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + enum rf_path path, + u8 gain) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 txagc = 0x38, kidx = dpk->cur_idx[path]; + bool is_fail = false; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx); + + halrf_rf_direct_cntrl_8852b(rf, path, false); /*switch control to direct write*/ + halrf_drf_direct_cntrl_8852b(rf, path, false); /*switch control to direct write*/ + + _dpk_kip_pwr_clk_on_8852b(rf, path); + _dpk_kip_set_txagc_8852b(rf, phy, path, txagc); + _dpk_rf_setting_8852b(rf, gain, path, kidx); + halrf_set_rx_dck_8852b(rf, phy, path, false); + + _dpk_kip_preset_8852b(rf, phy, path, kidx); + _dpk_kip_set_rxagc_8852b(rf, phy, path); + _dpk_table_select_8852b(rf, path, kidx, gain); +#if 0 + is_fail = _dpk_sync_8852b(rf, phy, path, kidx); + + if (is_fail) + goto _error; + + _dpk_dgain_read_8852b(rf); + _dpk_gainloss_8852b(rf, phy, path, kidx); + //tmp_gl_idx = _dpk_gainloss_read_8852b(rf); + + txagc = _dpk_set_offset_8852b(rf, phy, path, _dpk_gainloss_read_8852b(rf)); +#else + txagc = _dpk_agc_8852b(rf, phy, path, kidx, txagc, false); + + if (txagc == 0xff) { + is_fail = true; + goto _error; + } +#endif + /*_dpk_pas_read_8852b(rf, false);*/ + _dpk_get_thermal_8852b(rf, kidx, path); + + _dpk_idl_mpa_8852b(rf, phy, path, kidx, gain); + + halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX); +#if 0 + _dpk_coef_read_8852b(rf, path, kidx, gain); +#endif + _dpk_fill_result_8852b(rf, phy, path, kidx, gain, txagc); +_error: + + if (is_fail == false) + dpk->bp[path][kidx].path_ok = 1; + else + dpk->bp[path][kidx].path_ok = 0; + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] DPK %s\n", path, kidx, is_fail ? "Check" : "Success"); + + return is_fail; + +} + +void _dpk_cal_select_8852b( + struct rf_info *rf, + bool force, + enum phl_phy_idx phy, + u8 kpath) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u32 kip_bkup[DPK_RF_PATH_MAX_8852B][DPK_KIP_REG_NUM_8852B] = {{0}}; + u32 bb_bkup[DPK_BB_REG_NUM_8852B] = {0}; + u32 rf_bkup[DPK_RF_PATH_MAX_8852B][DPK_RF_REG_NUM_8852B] = {{0}}; + + u32 kip_reg[] = {0x813c, 0x8124, 0x8120}; + u32 bb_reg[] = {0x2344, 0x5800, 0x7800}; + u32 rf_reg[DPK_RF_REG_NUM_8852B] = {0xde, 0xdf, 0x8b, 0x90, 0x97, + 0x85, 0x5, 0x10005}; + + u8 path; + bool is_fail = true, reloaded[DPK_RF_PATH_MAX_8852B] = {false}; + + if (rf->phl_com->drv_mode != RTW_DRV_MODE_MP && DPK_RELOAD_EN_8852B) { + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + reloaded[path] = _dpk_reload_check_8852b(rf, phy, path); + if ((reloaded[path] == false) && (dpk->bp[path][0].ch != 0)) + dpk->cur_idx[path] = !dpk->cur_idx[path]; + else + halrf_dpk_onoff_8852b(rf, path, false); + } + } else { + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) + dpk->cur_idx[path] = 0; + } + + _dpk_bkup_bb_8852b(rf, bb_reg, bb_bkup); + + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + _dpk_bkup_kip_8852b(rf, kip_reg, kip_bkup, path); + _dpk_bkup_rf_8852b(rf, rf_reg, rf_bkup, path); + _dpk_information_8852b(rf, phy, path); + if (rf->is_tssi_mode[path]) + _dpk_tssi_pause_8852b(rf, path, true); + } + + _dpk_bb_afe_setting_8852b(rf, phy, path, kpath); + + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + is_fail = _dpk_main_8852b(rf, phy, path, 1); + halrf_dpk_onoff_8852b(rf, path, is_fail); + } + + _dpk_bb_afe_restore_8852b(rf, phy, path, kpath); + _dpk_reload_bb_8852b(rf, bb_reg, bb_bkup); + + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + _dpk_kip_restore_8852b(rf, path); + _dpk_reload_kip_8852b(rf, kip_reg, kip_bkup, path); + _dpk_reload_rf_8852b(rf, rf_reg, rf_bkup, path); + if (rf->is_tssi_mode[path]) + _dpk_tssi_pause_8852b(rf, path, false); + } +} + +u8 _dpk_bypass_check_8852b( + struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_fem_info *fem = &rf->fem; + + u8 result; + + if (fem->epa_2g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_24G)) { + RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 2G_ext_PA exist!!\n"); + result = 1; + } else if (fem->epa_5g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_5G)) { + RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 5G_ext_PA exist!!\n"); + result = 1; + } else if (fem->epa_6g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_6G)) { + RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 6G_ext_PA exist!!\n"); + result = 1; + } else + result = 0; + + return result; +} + +void _dpk_force_bypass_8852b( + struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 path, kpath; + + kpath = halrf_kpath_8852b(rf, phy); + + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + if (kpath & BIT(path)) + halrf_dpk_onoff_8852b(rf, path, true); + } +} + +void halrf_dpk_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + bool force) +{ + RF_DBG(rf, DBG_RF_DPK, "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", + DPK_VER_8852B, rf->hal_com->cv, RF_RELEASE_VERSION_8852B); + + RF_DBG(rf, DBG_RF_DPK, "[DPK] Driver mode = %d\n", rf->phl_com->drv_mode); +#if 1 + if (_dpk_bypass_check_8852b(rf, phy)) + _dpk_force_bypass_8852b(rf, phy); + else + _dpk_cal_select_8852b(rf, force, phy, RF_AB); +#else + _dpk_information_8852b(rf, 0, RF_PATH_A); + _dpk_bb_afe_setting_8852b(rf, 0, RF_PATH_A); + + //_dpk_main_8852b(rf, 0, 0, 1, RF_PATH_A); + _dpk_set_tx_pwr_8852b(rf, 1, RF_PATH_A); + _dpk_rf_setting_8852b(rf, 1, RF_PATH_A); + halrf_set_rx_dck_8852b(rf, RF_PATH_A, false); + + _dpk_cip_setting_8852b(rf, RF_PATH_A); + _dpk_manual_txcfir_8852b(rf, RF_PATH_A, true); + _dpk_bypass_rxcfir_8852b(rf, RF_PATH_A, true); + + //_dpk_sync_8852b(rf, RF_PATH_A); + //_dpk_dgain_read_8852b(rf); + //_dpk_gainloss_8852b(rf, RF_PATH_A); + _dpk_idl_mpa_8852b(rf, 0, 1, RF_PATH_A); + _dpk_fill_result_8852b(rf, 0, 1, RF_PATH_A, 0x36); + //halrf_dpk_onoff_8852b(rf, RF_PATH_A, 0); + //_dpk_reload_rf_8852b(rf, rf_reg, rf_bkup, kpath); + //halrf_rf_direct_cntrl_8852b(rf, RF_PATH_A, true); + //_dpk_bb_afe_restore_8852b(rf, phy, RF_PATH_A); + +#endif +} + +void halrf_dpk_onoff_8852b( + struct rf_info *rf, + enum rf_path path, + bool off) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + bool off_reverse; + u8 val, kidx = dpk->cur_idx[path]; + + if (off) + off_reverse = false; + else + off_reverse = true; + + val = dpk->is_dpk_enable & off_reverse & dpk->bp[path][kidx].path_ok; + + halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKBYTE3, + _dpk_order_convert_8852b(rf) << 1 | val); + + //halrf_wreg(rf, 0x81bc + (path << 8), BIT(24), dpk->is_dpk_enable & (!off)); /*ch0*/ + //halrf_wreg(rf, 0x81c0 + (path << 8), BIT(24), dpk->is_dpk_enable & (!off)); /*ch1*/ + + RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] DPK %s !!!\n", path, kidx, + (dpk->is_dpk_enable & off_reverse) ? "enable" : "disable"); +} + +void halrf_dpk_track_8852b( + struct rf_info *rf) +{ + struct halrf_dpk_info *dpk = &rf->dpk; + + u8 path, i, kidx; + u8 trk_idx = 0, txagc_rf = 0; + s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0; + u16 pwsf[2]; + u8 cur_ther, ther_avg_cnt = 0; + u32 ther_avg[2] = {0}; + s8 delta_ther[2] = {0}; + + for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) { + + kidx = dpk->cur_idx[path]; + + RF_DBG(rf, DBG_RF_DPK_TRACK, + "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n", + path, kidx, dpk->bp[path][kidx].ch); + + //cur_ther = halrf_get_thermal_8852b(rf, path); + cur_ther = (u8)halrf_rreg(rf, 0x1c10 + (path << 13), 0x3F000000); /*[29:24]*/ + + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] thermal now = %d\n", cur_ther); + + dpk->ther_avg[path][dpk->ther_avg_idx] = cur_ther; + + /*Average times */ + ther_avg_cnt = 0; + for (i = 0; i < THERMAL_DPK_AVG_NUM; i++) { + if (dpk->ther_avg[path][i]) { + ther_avg[path] += dpk->ther_avg[path][i]; + ther_avg_cnt++; +#if 0 + RF_DBG(rf, DBG_RF_DPK_TRACK, + "[DPK_TRK] thermal avg[%d] = %d\n", i, + dpk->thermal_dpk_avg[path][i]); +#endif + } + } + + /*Calculate Average ThermalValue after average enough times*/ + if (ther_avg_cnt) { + cur_ther = (u8)(ther_avg[path] / ther_avg_cnt); +#if 0 + RF_DBG(rf, DBG_RF_DPK_TRACK, + "[DPK_TRK] thermal avg total = %d, avg_cnt = %d\n", + ther_avg[path], ther_avg_cnt); +#endif + RF_DBG(rf, DBG_RF_DPK_TRACK, + "[DPK_TRK] thermal avg = %d (DPK @ %d)\n", + cur_ther, dpk->bp[path][kidx].ther_dpk); + } + + if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) + delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; + + if (dpk->bp[path][kidx].band == 0) /*2G*/ + delta_ther[path] = delta_ther[path] * 3 / 2; + else + delta_ther[path] = delta_ther[path] * 5 / 2; + + txagc_rf = (u8)halrf_rreg(rf, 0x1c60 + (path << 13), 0x0000003f); /*[5:0]*/ + + if (rf->is_tssi_mode[path]) { /*TSSI mode*/ + trk_idx = (u8)halrf_rrf(rf, path, 0x5D, 0xFC000); /*[19:14] for integer*/ + + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", + txagc_rf, trk_idx); + + txagc_bb = (s8)halrf_rreg(rf, 0x1c60 + (path << 13), MASKBYTE2); /*[23:16]*/ + txagc_bb_tp = (u8)halrf_rreg(rf, 0x1c04 + (path << 13), 0x00000007); /*[2:0]*/ + + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", + txagc_bb_tp, txagc_bb); + + txagc_ofst = (s8)halrf_rreg(rf, 0x1c60 + (path << 13), MASKBYTE3); /*[31:24]*/ + + + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n", txagc_ofst, delta_ther[path]); + + if (halrf_rreg(rf, 0x81c8 + (path << 8), BIT(15)) == 0x1) { + txagc_ofst = 0; /*hw txagc_offset*/ + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] HW txagc offset mode\n"); + } + + if (txagc_rf != 0 && cur_ther != 0) + ini_diff = txagc_ofst + (delta_ther[path]); + + if (halrf_rreg(rf, 0x58d4 + (path << 13), 0xf0000000) == 0x0) { + pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - txagc_bb + ini_diff; /*gain0*/ + pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - txagc_bb + ini_diff; /*gain1*/ + } else { + pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; /*gain0*/ + pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff; /*gain1*/ + } + + } else { /*without any tx power tracking mechanism*/ + pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; /*gain0*/ + pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; /*gain1*/ + } + + if (rf->rfk_is_processing != true && halrf_rreg(rf, 0x80f0, BIT(31)) == 0x0 && txagc_rf != 0) { + RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", + pwsf[0], pwsf[1]); + + halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x000001FF, pwsf[0]); + halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x01FF0000, pwsf[1]); + } + } + dpk->ther_avg_idx++; + + if (dpk->ther_avg_idx == THERMAL_DPK_AVG_NUM) + dpk->ther_avg_idx = 0; +} + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.h new file mode 100644 index 0000000..f528907 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_DPK_8852BH__ +#define __HALRF_DPK_8852BH__ +#ifdef RF_8852B_SUPPORT +/*--------------------------Define Parameters-------------------------------*/ +#define DPK_VER_8852B 0x9 +#define DPK_RF_PATH_MAX_8852B 2 +#define DPK_KIP_REG_NUM_8852B 3 +#define DPK_BB_REG_NUM_8852B 3 +#define DPK_RF_REG_NUM_8852B 8 +#define DPK_PATH_A_8852B 1 +#define DPK_PATH_B_8852B 1 +#define PATH_OFST_8852B 0x100 +#define CH_OFST_8852B 0x4 +#define PHY_OFST_8852B 0x80 +#define DPK_BY_NCTL_8852B 1 +#define DPK_RELOAD_EN_8852B 0 +#define DPK_REG_DBG 0 + +/*---------------------------End Define Parameters----------------------------*/ + +void halrf_dpk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force); + +void halrf_dpk_onoff_8852b(struct rf_info *rf, enum rf_path path, bool off); + +void halrf_dpk_track_8852b(struct rf_info *rf); + +#endif +#endif /* __HALRF_DPK_8852BH__ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.c new file mode 100644 index 0000000..a1da11a --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.c @@ -0,0 +1,337 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 autoload_status) +{ + struct rtw_hal_com_t *hal = rf->hal_com; + + u32 offset = 0; + u8 default_value = 0; + + if (length != 1) + return false; + + switch (id) { + case EFUSE_INFO_RF_PKG_TYPE: + offset = 0; + default_value = 0; + break; + case EFUSE_INFO_RF_PA: + offset = 0; + default_value = 0; + break; + case EFUSE_INFO_RF_VALID_PATH: + offset = 0; + default_value = 0; + break; + case EFUSE_INFO_RF_RFE: + offset = EFUSE_INFO_RF_RFE_8852B_ADDR; + default_value = EFUSE_INFO_RF_RFE_8852B_VALUE; + break; + case EFUSE_INFO_RF_TXPWR: + offset = 0; + default_value = 0; + break; + case EFUSE_INFO_RF_BOARD_OPTION: + offset = EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR; + default_value = EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE; + break; + case EFUSE_INFO_RF_CHAN_PLAN: + offset = EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR; + default_value = EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE; + break; + case EFUSE_INFO_RF_COUNTRY: + offset = 0; + default_value = 0; + break; + /*TSSI DE PathA CCK*/ + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6: + offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + /*TSSI DE PathA 2G MCS7 BW40M*/ + case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1: + offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2: + offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3: + offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4: + offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5: + offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + /*TSSI DE PathA 5G MCS7 BW40M*/ + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14: + offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + /*TSSI DE PathB CCK*/ + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6: + offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + /*TSSI DE PathB 2G MCS7 BW40M*/ + case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1: + offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2: + offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3: + offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4: + offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5: + offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + /*TSSI DE PathB 5G MCS7 BW40M*/ + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14: + offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR; + default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE; + break; + + case EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK: + offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR; + default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE; + break; + case EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD: + offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR; + default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE; + break; + case EFUSE_INFO_RF_RX_GAIN_K_A_5GL: + offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR; + default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE; + break; + case EFUSE_INFO_RF_RX_GAIN_K_A_5GM: + offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR; + default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE; + break; + case EFUSE_INFO_RF_RX_GAIN_K_A_5GH: + offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR; + default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE; + break; + /*Thermal*/ + case EFUSE_INFO_RF_THERMAL_A: + offset = EFUSE_INFO_RF_THERMAL_A_8852B_ADDR; + default_value = EFUSE_INFO_RF_THERMAL_A_8852B_VALUE; + break; + case EFUSE_INFO_RF_THERMAL_B: + offset = EFUSE_INFO_RF_THERMAL_B_8852B_ADDR; + default_value = EFUSE_INFO_RF_THERMAL_B_8852B_VALUE; + break; + case EFUSE_INFO_RF_XTAL: + offset = EFUSE_INFO_RF_XTAL_8852B_ADDR; + default_value = EFUSE_INFO_RF_XTAL_8852B_VALUE; + break; + default: + return false; + } + + if (autoload_status == 0) + hal_mem_cpy(hal, value, &default_value, 1); + else { + hal_mem_cpy(hal, value, efuse_map + offset, length); + + if (id == EFUSE_INFO_RF_XTAL) { + if (*((u8 *)value) == 0xff) + hal_mem_set(hal, value, 0x3f, 1); + } + } + + return true; +} + +#endif /*#ifdef RF_8852B_SUPPORT*/ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.h new file mode 100644 index 0000000..3de230e --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.h @@ -0,0 +1,111 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_EFUSE_8852B_H_ +#define _HALRF_EFUSE_8852B_H_ + +#ifdef RF_8852B_SUPPORT + +enum halrf_efsue_info_8852b_offset { + EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR = 0x2c1, + EFUSE_INFO_RF_RFE_8852B_ADDR = 0x2ca, + EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR = 0x2b8, + EFUSE_INFO_RF_XTAL_8852B_ADDR = 0x2b9, + EFUSE_INFO_RF_THERMAL_A_8852B_ADDR = 0x2d0, + EFUSE_INFO_RF_THERMAL_B_8852B_ADDR = 0x2d1, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR = 0x210, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR = 0x211, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR = 0x212, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR = 0x213, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR = 0x214, + EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR = 0x215, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR = 0x216, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR = 0x217, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR = 0x218, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR = 0x219, + EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR = 0x21a, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR = 0x222, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR = 0x223, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR = 0x224, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR = 0x225, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR = 0x226, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR = 0x227, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR = 0x228, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR = 0x229, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR = 0x22a, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR = 0x22b, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR = 0x22c, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR = 0x22d, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR = 0x22e, + EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR = 0x22f, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR = 0x23a, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR = 0x23b, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR = 0x23c, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR = 0x23d, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR = 0x23e, + EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR = 0x23f, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR = 0x240, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR = 0x241, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR = 0x242, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR = 0x243, + EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR = 0x244, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR = 0x24c, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR = 0x24d, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR = 0x24e, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR = 0x24f, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR = 0x250, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR = 0x251, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR = 0x252, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR = 0x253, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR = 0x254, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR = 0x255, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR = 0x256, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR = 0x257, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR = 0x258, + EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR = 0x259, + EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR = 0x2d6, + EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR = 0x2d4, + EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR = 0x2d8, + EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR = 0x2da, + EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR = 0x2dc +}; + +enum halrf_efsue_default_value_8852b { + EFUSE_INFO_RF_RFE_8852B_VALUE = 0x1, + EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE = 0x7f, + EFUSE_INFO_RF_XTAL_8852B_VALUE = 0x3f, + EFUSE_INFO_RF_THERMAL_A_8852B_VALUE = 0x22, + EFUSE_INFO_RF_THERMAL_B_8852B_VALUE = 0x22, + EFUSE_INFO_RF_TSSI_DE_8852B_VALUE = 0x0, + EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE = 0xf, + EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE = 0x1 +}; + +bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 autoload_status); + +#endif /*RF_8852B_SUPPORT*/ +#endif /*_HALRF_EFUSE_8852B_H_*/ + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.c new file mode 100644 index 0000000..8457a8a --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.c @@ -0,0 +1,1168 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#include "halrf_hwimg_raw_data_8852b.h" +#include "halrf_hwimg_nctl_raw_data_8852b.h" + +bool halrf_check_cond_8852b(struct rf_info *rf, u32 para_opt) +{ + struct rtw_hal_com_t *hal = rf->hal_com; + u32 cv_ver = (hal->cv == CAV) ? 15 : hal->cv; + /*[20200204][Dino]Request from SD7 Sinda, and need Sinda to tell us what is the correct pkg_type/rfe_type parameters in PHL layer for halbb reference*/ + u8 pkg_type = 0; /*(hal->efuse->pkg_type == 0) ? 15 : hal->efuse->pkg_type;*/ + u8 rfe_type = 0; /*hal->efuse->rfe_type;*/ + u32 drv_cfg = cv_ver << 16 | pkg_type << 8 | rfe_type; + u32 para_opt_tmp = 0; + + /*============== value Defined Check ===============*/ + /*Cart ver BIT[23:16]*/ + para_opt_tmp = para_opt & 0xff0000; + if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff0000))) + return false; + + /*PKG type, BIT[15:8]*/ + para_opt_tmp = para_opt & 0xff00; + if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff00))) + return false; + + /*RFE, BIT[7:0]*/ + para_opt_tmp = para_opt & 0xff; + if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff))) + return false; + + return true; +} + +u32 +halrf_get_8852b_nctl_reg_ver(void) +{ + return 0xa; +} + +u32 +halrf_get_8852b_radio_reg_ver(void) +{ + return RF_RELEASE_VERSION_8852B; +} + +void halrf_config_8852b_store_radio_a_reg(struct rf_info *rf, + u32 addr, u32 data) +{ + struct halrf_radio_info *radio = &rf->radio_info; + u32 page = radio->write_times_a / RADIO_TO_FW_DATA_SIZE; + u32 idx = radio->write_times_a % RADIO_TO_FW_DATA_SIZE; + u32 reg_tmp = 0; + + RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__); + + if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || + addr == 0xfa || addr == 0xf9) { + RF_DBG(rf, DBG_RF_INIT, "Radio parameter is delay return!!!\n"); + return; + } + + if (data > 0xfffff) + RF_DBG(rf, DBG_RF_INIT, "Radio parameter format error !!!\n"); + + /*DRFC only*/ + if (addr < 0x100) + return; + + addr &= 0xff; + reg_tmp = cpu_to_le32((addr << 20) | data); + radio->radio_a_parameter[page][idx] = reg_tmp; + + RF_DBG(rf, DBG_RF_INIT, "radioA->radio_parameter[%d][%03d]=0x%08x\n", + page, idx, radio->radio_a_parameter[page][idx]); + + radio->write_times_a++; +} + +void halrf_config_8852b_store_radio_b_reg(struct rf_info *rf, + u32 addr, u32 data) +{ + struct halrf_radio_info *radio = &rf->radio_info; + u32 page = radio->write_times_b / RADIO_TO_FW_DATA_SIZE; + u32 idx = radio->write_times_b % RADIO_TO_FW_DATA_SIZE; + u32 reg_tmp = 0; + + RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__); + + if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || + addr == 0xfa || addr == 0xf9) { + RF_DBG(rf, DBG_RF_INIT, "Radio parameter is delay return!!!\n"); + return; + } + + if (data > 0xfffff) + RF_DBG(rf, DBG_RF_INIT, "Radio parameter format error !!!\n"); + + /*DRFC only*/ + if (addr < 0x100) + return; + + addr &= 0xff; + + reg_tmp = cpu_to_le32((addr << 20) | data); + radio->radio_b_parameter[page][idx] = reg_tmp; + + RF_DBG(rf, DBG_RF_INIT, "radioB->radio_parameter[%d][%03d]=0x%08x\n", + page, idx, radio->radio_b_parameter[page][idx]); + + radio->write_times_b++; +} + + +void halrf_config_8852b_write_radio_a_reg_to_fw(struct rf_info *rf) +{ + struct halrf_radio_info *radio = &rf->radio_info; + u8 page = (u8)(radio->write_times_a / RADIO_TO_FW_DATA_SIZE); + u16 len = (radio->write_times_a % RADIO_TO_FW_DATA_SIZE) * 4; + u8 i; + + RF_DBG(rf, DBG_RF_INIT, "======> %s write_times_a=%d page=%d len=%d\n", + __func__, radio->write_times_a, page, len / 4); + + for (i = 0; i < page; i++) { + halrf_fill_h2c_cmd(rf, RADIO_TO_FW_DATA_SIZE * 4, i, 8, + H2CB_TYPE_LONG_DATA, radio->radio_a_parameter[i]); + RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4); + } + halrf_fill_h2c_cmd(rf, len, i, 8, + H2CB_TYPE_LONG_DATA, radio->radio_a_parameter[i]); + RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4); +} + +void halrf_config_8852b_write_radio_b_reg_to_fw(struct rf_info *rf) +{ + struct halrf_radio_info *radio = &rf->radio_info; + u8 page = (u8)(radio->write_times_b / RADIO_TO_FW_DATA_SIZE); + u16 len = (radio->write_times_b % RADIO_TO_FW_DATA_SIZE) * 4; + u8 i; + + RF_DBG(rf, DBG_RF_INIT, "======> %s write_times_b=%d page=%d len=%d\n", + __func__, radio->write_times_b, page, len / 4); + + for (i = 0; i < page; i++) { + halrf_fill_h2c_cmd(rf, RADIO_TO_FW_DATA_SIZE * 4, i, 9, + H2CB_TYPE_LONG_DATA, radio->radio_b_parameter[i]); + RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4); + } + halrf_fill_h2c_cmd(rf, len, i, 9, + H2CB_TYPE_LONG_DATA, radio->radio_b_parameter[i]); + RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4); +} + +void halrf_config_8852b_radio_to_fw(struct rf_info *rf) +{ + halrf_config_8852b_write_radio_a_reg_to_fw(rf); + halrf_config_8852b_write_radio_b_reg_to_fw(rf); +} + +void halrf_config_8852b_nctl_reg(struct rf_info *rf) +{ + u32 i = 0; + u32 array_len = 0x0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u32 cnt = 0x0; + RF_DBG(rf, DBG_RF_INIT, "[RFK]===> %s\n", __func__); + +//5. iqkdpk clk&rst + halrf_wreg(rf, 0x0c60, 0x00000003, 0x3); + halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1); + halrf_wreg(rf, 0x58ac, 0x08000000, 0x1); + halrf_wreg(rf, 0x78ac, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c60, 0x00000002, 0x1); + + array_len = sizeof(array_mp_8852b_nctl_reg) / sizeof(u32); + array = (u32 *) &array_mp_8852b_nctl_reg; + + // check 0x8080 + halrf_wreg(rf, 0x8000, MASKDWORD, 0x8); + while(cnt < 1000) { + cnt++; + halrf_wreg(rf, 0x8080, MASKDWORD, 0x4); + halrf_delay_us(rf, 1); + if(halrf_rreg(rf, 0x8080, MASKDWORD) == 0x4) + break; + } + halrf_write_fwofld_start(rf); + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + halrf_cfg_rf_nctl_8852b(rf, v1, MASKDWORD, v2); + i += 2; + } + halrf_write_fwofld_end(rf); + +} + +bool halrf_sel_headline_8852b(struct rf_info *rf, u32 *array, u32 array_len, + u8 *headline_size, u8 *headline_idx) +{ + bool case_match = false; + u8 cv_drv_org = rf->hal_com->cv; + u8 rfe_drv_org = rf->phl_com->dev_cap.rfe_type; + u32 cv_para = 0, rfe_para = 0; + u32 compare_target = 0; + u32 cv_max = 0; + u32 i = 0; + u32 cv_drv = (u32)cv_drv_org; + u32 rfe_drv = (u32)rfe_drv_org; + + *headline_idx = 0; + *headline_size = 0; + +#if 0 + if (rf->rf_dbg_i.cr_dbg_mode_en) { + rfe_drv = rf->rf_dbg_i.rfe_type_curr_dbg; + cv_drv = rf->rf_dbg_i.cv_curr_dbg; + } + + RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n", + rfe_drv, cv_drv, rf->rf_dbg_i.cr_dbg_mode_en); +#endif + + RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart}={%d, %d}\n", + rfe_drv, cv_drv); + + while ((i + 1) < array_len) { + if ((array[i] >> 28) != 0xf) { + *headline_size = (u8)i; + break; + } + RF_DBG(rf, DBG_RF_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n", + i, array[i], i+1, array[i+1]); + i += 2; + } + + RF_DBG(rf, DBG_RF_INIT, "headline_size=%d\n", i); + + if (i == 0) + return true; + + /*case_idx:1 {RFE:Match, cv:Match}*/ + compare_target = ((rfe_drv & 0xff) << 16) | (cv_drv & 0xff); + RF_DBG(rf, DBG_RF_INIT, "[1] CHK {RFE:Match, cv:Match}\n"); + for (i = 0; i < *headline_size; i += 2) { + if ((array[i] & 0x0fffffff) == compare_target) { + *headline_idx = (u8)(i >> 1); + return true; + } + } + RF_DBG(rf, DBG_RF_INIT, "\t fail\n"); + + /*case_idx:2 {RFE:Match, cv:Dont care}*/ + compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff); + RF_DBG(rf, DBG_RF_INIT, "[2] CHK {RFE:Match, cv:Dont_Care}\n"); + for (i = 0; i < *headline_size; i += 2) { + if ((array[i] & 0x0fffffff) == compare_target) { + *headline_idx = (u8)(i >> 1); + return true; + } + } + RF_DBG(rf, DBG_RF_INIT, "\t fail\n"); + + /*case_idx:3 {RFE:Match, cv:Max_in_table}*/ + RF_DBG(rf, DBG_RF_INIT, "[3] CHK {RFE:Match, cv:Max_in_Table}\n"); + for (i = 0; i < *headline_size; i += 2) { + rfe_para = (array[i] & 0x00ff0000) >> 16; + cv_para = array[i] & 0x0ff; + if (rfe_para == rfe_drv) { + if (cv_para > cv_max) { + cv_max = cv_para; + *headline_idx = (u8)(i >> 1); + RF_DBG(rf, DBG_RF_INIT, "cv_max:%d\n", cv_max); + case_match = true; + } + } + } + if (case_match) { + return true; + } + RF_DBG(rf, DBG_RF_INIT, "\t fail\n"); + + /*case_idx:4 {RFE:Dont Care, cv:Max_in_table}*/ + RF_DBG(rf, DBG_RF_INIT, "[4] CHK {RFE:Dont_Care, cv:Max_in_Table}\n"); + for (i = 0; i < *headline_size; i += 2) { + rfe_para = (array[i] & 0x00ff0000) >> 16; + cv_para = array[i] & 0x0ff; + if (rfe_para == DONT_CARE_8852B) { + if (cv_para >= cv_max) { + cv_max = cv_para; + *headline_idx = (u8)(i >> 1); + RF_DBG(rf, DBG_RF_INIT, "cv_max:%d\n", cv_max); + case_match = true; + } + } + } + if (case_match) { + return true; + } + RF_DBG(rf, DBG_RF_INIT, "\t fail\n"); + + /*case_idx:5 {RFE:Not_Match, cv:Not_Match}*/ + RF_DBG(rf, DBG_RF_INIT, "[5] CHK {RFE:Not_Match, cv:Not_Match}\n"); + RF_DBG(rf, DBG_RF_INIT, "\t all fail\n"); + return false; +} + +void halrf_flag_2_default_8852b(bool *is_matched, bool *find_target) +{ + *is_matched = true; + *find_target = false; +} + + +void +halrf_config_8852b_radio_a_reg(struct rf_info *rf, bool is_form_folder, + u32 folder_len, u32 *folder_array) +{ +#if 0 + struct rtw_hal_com_t *hal = rf->hal_com; + struct halrf_radio_info *radio = &rf->radio_info; + + u32 i = 0, j = 0; + u32 c_cond; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u32 tmp_val = 0; + u32 cv = 0; /*cv ver of para*/ + u8 rfe_type_org = 0; /*rfe ver of para*/ + u32 cv_curr = (u32)rf->hal_com->cv; + u8 rfe_type_curr_org = (u32)rf->phl_com->dev_cap.rfe_type; + u32 cv_max = 0; + u32 latest_rfe_match_entry = 0; + bool is_matched = true; + bool is_skipped = false; + bool is_rfe_match = false; + bool is_cart_match = false; + bool is_else_case = false; + bool is_rfe_ever_match = false; + u32 rfe_type = (u32)rfe_type_org; + u32 rfe_type_curr = (u32)rfe_type_curr_org; + + radio->write_times_a = 0; + hal_mem_set(hal, radio->radio_a_parameter, 0, sizeof(radio->radio_a_parameter)); + + RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_radioa) / sizeof(u32); + array = (u32 *)array_mp_8852b_radioa; + } + + RF_DBG(rf, DBG_RF_INIT, "RF CR form_folder=%d, len=%d\n", + is_form_folder, array_len); + RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart} = (%d, %d)\n", + rfe_type_curr, cv_curr); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & BIT(31)) { + /*Get para-setting from para-array*/ + c_cond = v1 >> 28; + if (c_cond == 0xb) {/*b:end*/ + is_matched = true; + is_skipped = false; + RF_DBG(rf, DBG_RF_INIT, "END\n"); + } else {/*8:if , 9:else if*/ + + tmp_val = (v1 & 0xff0000) >> 16; + if (tmp_val == DONT_CARE_8852b) { + is_rfe_match = true; /*dont care condition*/ + } else { + rfe_type = tmp_val; + is_rfe_match = (rfe_type == rfe_type_curr); + } + + tmp_val = v1 & 0xff; + if (tmp_val == DONT_CARE_8852b) { + is_cart_match = true; /*dont care condition*/ + } else { + cv = tmp_val; + is_cart_match = (cv == cv_curr); + } + + if (c_cond == 0xa) { /*a:else*/ + is_else_case = is_skipped ? false : true; + RF_DBG(rf, DBG_RF_INIT, "ELSE\n"); + if (!is_rfe_ever_match) { + /*RF_WARNING("Set Default CR\n");*/ + is_matched = is_skipped ? false : true; + } + } else if (c_cond == 0x9) { + RF_DBG(rf, DBG_RF_INIT, "ELSE IF (rfe=%d, cart=%d)\n", + rfe_type, cv); + } else { + RF_DBG(rf, DBG_RF_INIT, "IF (rfe=%d, cart=%d)\n", + rfe_type, cv); + } + + RF_DBG(rf, DBG_RF_INIT, "is_rfe_match=%d, is_cart_match=%d)\n", + is_rfe_match, is_cart_match); + } + } else if (v1 & BIT(30)) { + /*Check this para-setting meets driver's requirement or not*/ + if (is_skipped) { + is_matched = false; + } else { + //rpt = halbb_check_cond_8852b(bb, rfe_type, cv); + if (is_rfe_match && is_cart_match) { + is_matched = true; + is_skipped = true; + RF_DBG(rf, DBG_RF_INIT, " ==>match\n"); + } else { + is_matched = false; + is_skipped = false; + } + } + } else { + if (is_matched) { + halrf_cfg_rf_radio_a_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_a_reg(rf, v1, v2); + is_rfe_match = false; + is_else_case = false; + is_rfe_ever_match = false; + } else if (is_rfe_match) { + RF_DBG(rf, DBG_RF_INIT, "rfe_ever_match\n"); + if (cv >= cv_max) { + cv_max = cv; + is_rfe_ever_match = true; + latest_rfe_match_entry = i; + RF_DBG(rf, DBG_RF_INIT, "Update entry=%d\n", latest_rfe_match_entry); + } + is_rfe_match = false; + } else if (is_else_case) { + is_else_case = false; + is_rfe_ever_match = false; + is_rfe_match = false; + + j = latest_rfe_match_entry; + RF_DBG(rf, DBG_RF_INIT, "Set RFE match value, entry=%d\n", latest_rfe_match_entry); + + do { + v1 = array[j]; + v2 = array[j + 1]; + halrf_cfg_rf_radio_a_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_a_reg(rf, v1, v2); + j = j + 2; + } while (!(array[j] & 0xC0000000)); + + } + } + i += 2; + } +#else + struct rtw_hal_com_t *hal = rf->hal_com; + struct halrf_radio_info *radio = &rf->radio_info; + bool is_matched, find_target; + u32 cfg_target = 0, cfg_para = 0; + u32 i = 0; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u8 h_size = 0; + u8 h_idx = 0; + + halrf_write_fwofld_start(rf); + + RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, is_form_folder, folder_len); + + radio->write_times_a = 0; + hal_mem_set(hal, radio->radio_a_parameter, 0, sizeof(radio->radio_a_parameter)); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_radioa) / sizeof(u32); + array = (u32 *)array_mp_8852b_radioa; + } + + RF_DBG(rf, DBG_RF_INIT, "RFCR_form_folder=%d, len=%d\n", + is_form_folder, array_len); + + if (!halrf_sel_headline_8852b(rf, array, array_len, &h_size, &h_idx)) { + RF_WARNING("[%s]Invalid RF CR Pkg\n", __func__); + return; + } + + RF_DBG(rf, DBG_RF_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx); + + if (h_size != 0) { + cfg_target = array[h_idx << 1] & 0x0fffffff; + } + + i += h_size; + + RF_DBG(rf, DBG_RF_INIT, "cfg_target = 0x%x\n", cfg_target); + RF_DBG(rf, DBG_RF_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]); + + halrf_flag_2_default_8852b(&is_matched, &find_target); + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + i += 2; + + switch (v1 >> 28) { + case IF_8852B: + case ELSE_IF_8852B: + cfg_para = v1 & 0x0fffffff; + RF_DBG(rf, DBG_RF_INIT, "*if (rfe=%d, cart=%d)\n", + (cfg_para & 0xff0000) >> 16, cfg_para & 0xff); + break; + case ELSE_8852B: + RF_DBG(rf, DBG_RF_INIT, "*else\n"); + is_matched = false; + if (!find_target) { + RF_WARNING("Init RFCR Fail in Reg 0x%x\n", array[i]); + return; + } + break; + case END_8852B: + RF_DBG(rf, DBG_RF_INIT, "*endif\n"); + halrf_flag_2_default_8852b(&is_matched, &find_target); + break; + case CHK_8852B: + /*Check this para meets driver's requirement or not*/ + if (find_target) { + RF_DBG(rf, DBG_RF_INIT, "\t skip\n"); + is_matched = false; + break; + } + + if (cfg_para == cfg_target) { + is_matched = true; + find_target = true; + } else { + is_matched = false; + find_target = false; + } + RF_DBG(rf, DBG_RF_INIT, "\t match=%d\n", is_matched); + break; + default: + if (is_matched) { + halrf_cfg_rf_radio_a_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_a_reg(rf, v1, v2); + } + break; + } + } + + halrf_write_fwofld_end(rf); + RF_DBG(rf, DBG_RF_INIT, "RFCR Init Success\n"); + halrf_config_8852b_write_radio_a_reg_to_fw(rf); + +#endif +} + +void +halrf_config_8852b_radio_b_reg(struct rf_info *rf, bool is_form_folder, + u32 folder_len, u32 *folder_array) +{ +#if 0 + struct rtw_hal_com_t *hal = rf->hal_com; + struct halrf_radio_info *radio = &rf->radio_info; + + u32 i = 0, j = 0; + u32 c_cond; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u32 tmp_val = 0; + u32 cv = 0; /*cv ver of para*/ + u8 rfe_type_org = 0; /*rfe ver of para*/ + u32 cv_curr = (u32)rf->hal_com->cv; + u8 rfe_type_curr_org = (u32)rf->phl_com->dev_cap.rfe_type; + u32 cv_max = 0; + u32 latest_rfe_match_entry = 0; + bool is_matched = true; + bool is_skipped = false; + bool is_rfe_match = false; + bool is_cart_match = false; + bool is_else_case = false; + bool is_rfe_ever_match = false; + u32 rfe_type = (u32)rfe_type_org; + u32 rfe_type_curr = (u32)rfe_type_curr_org; + + radio->write_times_b = 0; + hal_mem_set(hal, radio->radio_b_parameter, 0, sizeof(radio->radio_b_parameter)); + + RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_radiob) / sizeof(u32); + array = (u32 *)array_mp_8852b_radiob; + } + + RF_DBG(rf, DBG_RF_INIT, "BBCR_form_folder=%d, len=%d\n", + is_form_folder, array_len); + RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart} = (%d, %d)\n", + rfe_type_curr, cv_curr); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & BIT(31)) { + /*Get para-setting from para-array*/ + c_cond = v1 >> 28; + if (c_cond == 0xb) {/*b:end*/ + is_matched = true; + is_skipped = false; + RF_DBG(rf, DBG_RF_INIT, "END\n"); + } else {/*8:if , 9:else if*/ + + tmp_val = (v1 & 0xff0000) >> 16; + if (tmp_val == DONT_CARE_8852b) { + is_rfe_match = true; /*dont care condition*/ + } else { + rfe_type = tmp_val; + is_rfe_match = (rfe_type == rfe_type_curr); + } + + tmp_val = v1 & 0xff; + if (tmp_val == DONT_CARE_8852b) { + is_cart_match = true; /*dont care condition*/ + } else { + cv = tmp_val; + is_cart_match = (cv == cv_curr); + } + + if (c_cond == 0xa) { /*a:else*/ + is_else_case = is_skipped ? false : true; + RF_DBG(rf, DBG_RF_INIT, "ELSE\n"); + if (!is_rfe_ever_match) { + /*RF_WARNING("Set Default CR\n");*/ + is_matched = is_skipped ? false : true; + } + } else if (c_cond == 0x9) { + RF_DBG(rf, DBG_RF_INIT, "ELSE IF (rfe=%d, cart=%d)\n", + rfe_type, cv); + } else { + RF_DBG(rf, DBG_RF_INIT, "IF (rfe=%d, cart=%d)\n", + rfe_type, cv); + } + + RF_DBG(rf, DBG_RF_INIT, "is_rfe_match=%d, is_cart_match=%d)\n", + is_rfe_match, is_cart_match); + } + } else if (v1 & BIT(30)) { + /*Check this para-setting meets driver's requirement or not*/ + if (is_skipped) { + is_matched = false; + } else { + //rpt = halbb_check_cond_8852b(bb, rfe_type, cv); + if (is_rfe_match && is_cart_match) { + is_matched = true; + is_skipped = true; + RF_DBG(rf, DBG_RF_INIT, " ==>match\n"); + } else { + is_matched = false; + is_skipped = false; + } + } + } else { + if (is_matched) { + halrf_cfg_rf_radio_b_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_b_reg(rf, v1, v2); + is_rfe_match = false; + is_else_case = false; + is_rfe_ever_match = false; + } else if (is_rfe_match) { + RF_DBG(rf, DBG_RF_INIT, "rfe_ever_match\n"); + if (cv >= cv_max) { + cv_max = cv; + is_rfe_ever_match = true; + latest_rfe_match_entry = i; + RF_DBG(rf, DBG_RF_INIT, "Update entry=%d\n", latest_rfe_match_entry); + } + is_rfe_match = false; + } else if (is_else_case) { + is_else_case = false; + is_rfe_ever_match = false; + is_rfe_match = false; + + j = latest_rfe_match_entry; + RF_DBG(rf, DBG_RF_INIT, "Set RFE match value, entry=%d\n", latest_rfe_match_entry); + + do { + v1 = array[j]; + v2 = array[j + 1]; + halrf_cfg_rf_radio_b_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_b_reg(rf, v1, v2); + j = j + 2; + } while (!(array[j] & 0xC0000000)); + + } + } + i += 2; + } +#else + struct rtw_hal_com_t *hal = rf->hal_com; + struct halrf_radio_info *radio = &rf->radio_info; + bool is_matched, find_target; + u32 cfg_target = 0, cfg_para = 0; + u32 i = 0; + u32 array_len = 0; + u32 *array = NULL; + u32 v1 = 0, v2 = 0; + u8 h_size = 0; + u8 h_idx = 0; + + halrf_write_fwofld_start(rf); + + RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, is_form_folder, folder_len); + + radio->write_times_b = 0; + hal_mem_set(hal, radio->radio_b_parameter, 0, sizeof(radio->radio_b_parameter)); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_radiob) / sizeof(u32); + array = (u32 *)array_mp_8852b_radiob; + } + + RF_DBG(rf, DBG_RF_INIT, "RFCR_form_folder=%d, len=%d\n", + is_form_folder, array_len); + + if (!halrf_sel_headline_8852b(rf, array, array_len, &h_size, &h_idx)) { + RF_WARNING("[%s]Invalid RF CR Pkg\n", __func__); + return; + } + + RF_DBG(rf, DBG_RF_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx); + + if (h_size != 0) { + cfg_target = array[h_idx << 1] & 0x0fffffff; + } + + i += h_size; + + RF_DBG(rf, DBG_RF_INIT, "cfg_target = 0x%x\n", cfg_target); + RF_DBG(rf, DBG_RF_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]); + + halrf_flag_2_default_8852b(&is_matched, &find_target); + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + i += 2; + + switch (v1 >> 28) { + case IF_8852B: + case ELSE_IF_8852B: + cfg_para = v1 & 0x0fffffff; + RF_DBG(rf, DBG_RF_INIT, "*if (rfe=%d, cart=%d)\n", + (cfg_para & 0xff0000) >> 16, cfg_para & 0xff); + break; + case ELSE_8852B: + RF_DBG(rf, DBG_RF_INIT, "*else\n"); + is_matched = false; + if (!find_target) { + RF_WARNING("Init RFCR Fail in Reg 0x%x\n", array[i]); + return; + } + break; + case END_8852B: + RF_DBG(rf, DBG_RF_INIT, "*endif\n"); + halrf_flag_2_default_8852b(&is_matched, &find_target); + break; + case CHK_8852B: + /*Check this para meets driver's requirement or not*/ + if (find_target) { + RF_DBG(rf, DBG_RF_INIT, "\t skip\n"); + is_matched = false; + break; + } + + if (cfg_para == cfg_target) { + is_matched = true; + find_target = true; + } else { + is_matched = false; + find_target = false; + } + RF_DBG(rf, DBG_RF_INIT, "\t match=%d\n", is_matched); + break; + default: + if (is_matched) { + halrf_cfg_rf_radio_b_8852b(rf, v1, v2); + halrf_config_8852b_store_radio_b_reg(rf, v1, v2); + } + break; + } + } + + halrf_write_fwofld_end(rf); + RF_DBG(rf, DBG_RF_INIT, "RFCR Init Success\n"); + halrf_config_8852b_write_radio_b_reg_to_fw(rf); +#endif +} + +void +halrf_config_8852b_store_power_by_rate(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + + u32 i, j; + u32 array_len = 0; + u32 *array = NULL; + + RF_DBG(rf, DBG_RF_INIT, "======> %s folder_len=%d\n", __func__, folder_len); + + if (is_form_folder) { + array_len = folder_len; + array = folder_array; + } else { + array_len = sizeof(array_mp_8852b_txpwr_byrate) / sizeof(u32); + array = (u32 *)array_mp_8852b_txpwr_byrate; + } + + for (i = 0; i < array_len; i += 4) { + u32 band = array[i]; + u32 tx_num = array[i + 1]; + u32 rate_id = array[i + 2]; + u32 data = array[i + 3]; + + halrf_power_by_rate_store_to_array(rf, band, tx_num, rate_id, data); + } + + for (i = 0; i < PW_LMT_MAX_BAND; i++) + for (j = 0; j < HALRF_DATA_RATE_MAX; j++) + RF_DBG(rf, DBG_RF_INIT, "pwr_by_rate[%d][%03d]=%d\n", + i, j, pwr->tx_pwr_by_rate[i][j]); + + /*compiler error*/ + pwr->tx_pwr_by_rate[0][0]++; + pwr->tx_pwr_by_rate[0][0]--; +} + +void +halrf_config_8852b_store_power_limit(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + const struct halrf_tx_pw_lmt *array = NULL; + struct halrf_tx_pw_lmt *parray = NULL; + struct halrf_pwr_info *pwr = &rf->pwr_info; + u32 i; + u32 array_len = 0; + u8 band, bandwidth, tx_num, rate, beamforming, regulation, chnl, val; + + RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, + is_form_folder, folder_len); + + if (is_form_folder) { + array_len = folder_len; + parray = (struct halrf_tx_pw_lmt *) folder_array; + + for (i = 0; i < array_len; i++) { + array = (struct halrf_tx_pw_lmt *)&parray[i]; + band = array->band; + bandwidth = array->bw; + tx_num = array->ntx; + rate = array->rs; + beamforming = array->bf; + regulation = array->reg; + chnl = array->ch; + val = array->val; + + pwr->regulation[band][regulation] = true; + + if (rate == PW_LMT_RS_CCK) { + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array->tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]); + } else { + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array->tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]); + } + + halrf_power_limit_store_to_array(rf, regulation, band, bandwidth, + rate, tx_num, beamforming, chnl, val); + } + } else { + array_len = sizeof(array_mp_8852b_txpwr_lmt) / sizeof(struct halrf_tx_pw_lmt); + array = array_mp_8852b_txpwr_lmt; + + for (i = 0; i < array_len; i++) { + band = array[i].band; + bandwidth = array[i].bw; + tx_num = array[i].ntx; + rate = array[i].rs; + beamforming = array[i].bf; + regulation = array[i].reg; + chnl = array[i].ch; + val = array[i].val; + + pwr->regulation[band][regulation] = true; + + if (rate == PW_LMT_RS_CCK) { + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array[i].tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]); + } else { + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array[i].tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]); + } + + halrf_power_limit_store_to_array(rf, regulation, band, bandwidth, + rate, tx_num, beamforming, chnl, val); + } + } + + halrf_power_limit_set_worldwide(rf); + halrf_power_limit_set_ext_pwr_limit_table(rf, 0); +} + +void +halrf_config_8852b_store_power_limit_ru(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + const struct halrf_tx_pw_lmt_ru *array = NULL; + struct halrf_tx_pw_lmt_ru *parray = NULL; + struct halrf_pwr_info *pwr = &rf->pwr_info; + u32 i; + u32 array_len = 0; + u8 band, bandwidth, tx_num, rate, regulation, chnl, val; + + RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, + is_form_folder, folder_len); + + if (is_form_folder) { + array_len = folder_len; + parray = (struct halrf_tx_pw_lmt_ru *) folder_array; + + for (i = 0; i < array_len; i++) { + array = (struct halrf_tx_pw_lmt_ru *)&parray[i]; + band = array->band; + bandwidth = array->bw; + tx_num = array->ntx; + rate = array->rs; + regulation = array->reg; + chnl = array->ch; + val = array->val; + + if (rate == PW_LMT_RS_CCK) { + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array->tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]); + } else { + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array->tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]); + } + + halrf_power_limit_ru_store_to_array(rf, band, bandwidth, tx_num, + rate, regulation, chnl, val); + } + } else { + array_len = sizeof(array_mp_8852b_txpwr_lmt_ru) / sizeof(struct halrf_tx_pw_lmt_ru); + array = array_mp_8852b_txpwr_lmt_ru; + + for (i = 0; i < array_len; i++) { + band = array[i].band; + bandwidth = array[i].bw; + tx_num = array[i].ntx; + rate = array[i].rs; + regulation = array[i].reg; + chnl = array[i].ch; + val = array[i].val; + + if (rate == PW_LMT_RS_CCK) { + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array[i].tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]); + } else { + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array[i].tx_shap_idx; + RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + __func__, band, regulation, + pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]); + } + + halrf_power_limit_ru_store_to_array(rf, band, bandwidth, tx_num, + rate, regulation, chnl, val); + } + } + + halrf_power_limit_ru_set_worldwide(rf); + halrf_power_limit_set_ext_pwr_limit_ru_table(rf, 0); +} + +void +halrf_config_8852b_store_pwr_track(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct halrf_pwr_track_info *tmp_info = NULL; + struct halrf_pwr_track_info *pwr_trk = &rf->pwr_track; + struct rtw_hal_com_t *hal = rf->hal_com; + + RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", + __func__, is_form_folder, folder_len); + + if (is_form_folder) { + tmp_info = (struct halrf_pwr_track_info *) folder_array; + + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_p, + tmp_info->delta_swing_table_idx_2ga_p, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_n, + tmp_info->delta_swing_table_idx_2ga_n, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_p, + tmp_info->delta_swing_table_idx_2gb_p, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_n, + tmp_info->delta_swing_table_idx_2gb_n, + DELTA_SWINGIDX_SIZE); + + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_p, + tmp_info->delta_swing_table_idx_2g_cck_a_p, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_n, + tmp_info->delta_swing_table_idx_2g_cck_a_n, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_p, + tmp_info->delta_swing_table_idx_2g_cck_b_p, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_n, + tmp_info->delta_swing_table_idx_2g_cck_b_n, + DELTA_SWINGIDX_SIZE); + + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_p, + tmp_info->delta_swing_table_idx_5ga_p, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_n, + tmp_info->delta_swing_table_idx_5ga_n, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_p, + tmp_info->delta_swing_table_idx_5gb_p, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_n, + tmp_info->delta_swing_table_idx_5gb_n, + DELTA_SWINGIDX_SIZE * 3); + + } else { + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_p, + (void *)delta_swingidx_mp_2ga_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_n, + (void *)delta_swingidx_mp_2ga_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_p, + (void *)delta_swingidx_mp_2gb_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_n, + (void *)delta_swingidx_mp_2gb_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_p, + (void *)delta_swingidx_mp_2g_cck_a_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_n, + (void *)delta_swingidx_mp_2g_cck_a_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_p, + (void *)delta_swingidx_mp_2g_cck_b_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_n, + (void *)delta_swingidx_mp_2g_cck_b_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE); + + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_p, + (void *)delta_swingidx_mp_5ga_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_n, + (void *)delta_swingidx_mp_5ga_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_p, + (void *)delta_swingidx_mp_5gb_p_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE * 3); + hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_n, + (void *)delta_swingidx_mp_5gb_n_txpwrtrkssi_8852b, + DELTA_SWINGIDX_SIZE * 3); + } +} + +void +_halrf_config_rfe_xtal_track_table_8852b(struct rf_info *rf) +{ +#if 0 + struct halrf_xtal_info *xtal_trk = &rf->xtal_track; + struct rtw_hal_com_t *hal = rf->hal_com; + + hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_p, + (void *)delta_swing_xtal_mp_p_txxtaltrack_8852b, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_n, + (void *)delta_swing_xtal_mp_n_txxtaltrack_8852b, + DELTA_SWINGIDX_SIZE); +#endif +} + +void +halrf_config_8852b_store_xtal_track(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct halrf_xtal_info *tmp_info = NULL; + struct halrf_xtal_info *xtal_trk = &rf->xtal_track; + struct rtw_hal_com_t *hal = rf->hal_com; + + if (is_form_folder) { + tmp_info = (struct halrf_xtal_info *) folder_array; + + hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_p, + tmp_info->delta_swing_xtal_table_idx_p, + DELTA_SWINGIDX_SIZE); + hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_n, + tmp_info->delta_swing_xtal_table_idx_n, + DELTA_SWINGIDX_SIZE); + } else { + _halrf_config_rfe_xtal_track_table_8852b(rf); + } +} + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.h new file mode 100644 index 0000000..4fe3398 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.h @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_HW_IMG_8852B_H_ +#define _HALRF_HW_IMG_8852B_H_ +#ifdef RF_8852B_SUPPORT + +#define DONT_CARE_8852B 0xff + +#define IF_8852B 0x8 +#define ELSE_IF_8852B 0x9 +#define ELSE_8852B 0xa +#define END_8852B 0xb +#define CHK_8852B 0x4 + +#if 0 +#define RADIO_TO_FW_PAGE_SIZE 6 +#define RADIO_TO_FW_DATA_SIZE 500 + +#define FWCMD_H2C_RADIO_A_INIT_0 0x0 +#define FWCMD_H2C_RADIO_A_INIT_1 0x1 +#define FWCMD_H2C_RADIO_A_INIT_2 0x2 +#define FWCMD_H2C_RADIO_A_INIT_3 0x3 +#define FWCMD_H2C_RADIO_A_INIT_4 0x4 +#define FWCMD_H2C_RADIO_A_INIT_5 0x5 +#define FWCMD_H2C_RADIO_A_INIT_6 0x6 +#define FWCMD_H2C_RADIO_A_INIT_7 0x7 +#define FWCMD_H2C_RADIO_A_INIT_8 0x8 +#define FWCMD_H2C_RADIO_A_INIT_9 0x9 + +#define FWCMD_H2C_RADIO_B_INIT_0 0x0 +#define FWCMD_H2C_RADIO_B_INIT_1 0x1 +#define FWCMD_H2C_RADIO_B_INIT_2 0x2 +#define FWCMD_H2C_RADIO_B_INIT_3 0x3 +#define FWCMD_H2C_RADIO_B_INIT_4 0x4 +#define FWCMD_H2C_RADIO_B_INIT_5 0x5 +#define FWCMD_H2C_RADIO_B_INIT_6 0x6 +#define FWCMD_H2C_RADIO_B_INIT_7 0x7 +#define FWCMD_H2C_RADIO_B_INIT_8 0x8 +#define FWCMD_H2C_RADIO_B_INIT_9 0x9 + +struct halrf_radio_info { + u32 write_times_a; + u32 write_times_b; + u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE]; + u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE]; +}; + +#endif +void halrf_config_8852b_nctl_reg(struct rf_info *rf); +void halrf_config_8852b_radio_a_reg(struct rf_info *rf, bool is_form_folder, + u32 folder_len, u32 *folder_array); +void halrf_config_8852b_radio_b_reg(struct rf_info *rf, bool is_form_folder, + u32 folder_len, u32 *folder_array); +void halrf_config_8852b_store_power_by_rate(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array); +void halrf_config_8852b_store_power_limit(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array); +void halrf_config_8852b_store_power_limit_ru(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array); +void halrf_config_8852b_store_pwr_track(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array); +void halrf_config_8852b_store_xtal_track(struct rf_info *rf, + bool is_form_folder, u32 folder_len, u32 *folder_array); + +u32 halrf_get_8852b_nctl_reg_ver(void); +u32 halrf_get_8852b_radio_reg_ver(void); + +void halrf_config_8852b_radio_to_fw(struct rf_info *rf); + +#endif +#endif /* _HALRF_HW_IMG_8852b_H_ */ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_nctl_raw_data_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_nctl_raw_data_8852b.h new file mode 100644 index 0000000..94c37d7 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_nctl_raw_data_8852b.h @@ -0,0 +1,1352 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_HW_IMG_NCTL_INIT_REG_8852B_H_ +#define _HALRF_HW_IMG_NCTL_INIT_REG_8852B_H_ + + const u32 array_mp_8852b_nctl_reg[] = { + //_Init0_IQKDPK_Init_Reg_52B_20210621 + 0x8000, 0x00000008, + 0x8008, 0x00000000, + 0x8004, 0xf0862966, + 0x800c, 0x78000000, + 0x8010, 0x88015000, + 0x8014, 0x80010100, + 0x8018, 0x10010100, + 0x801c, 0xa210bc00, + 0x8020, 0x000403e0, + 0x8024, 0x00072160, + 0x8028, 0x00180e00, + 0x8030, 0x400000c0, + 0x8034, 0x11000830, + 0x8038, 0x00000009, + 0x803c, 0x00000008, + 0x8040, 0x00000046, + 0x8044, 0x0010001f, + 0x8048, 0xf0000003, + 0x804c, 0x62ac6162, + 0x8050, 0xf2acf162, + 0x8054, 0x62ac6162, + 0x8058, 0xf2acf162, + 0x805c, 0x150c0b02, + 0x8060, 0x150c0b02, + 0x8064, 0x2aa00047, + 0x8074, 0x80000000, + 0x807c, 0x000000ee, + 0x8088, 0x80000000, + 0x8098, 0x0000ff00, + 0x809c, 0x0000001f, + 0x80a0, 0x00010300, + 0x80b8, 0x00001000, + 0x80b0, 0x00000000, + 0x80d0, 0x00000000, + 0x80ec, 0x00000002, + 0x810c, 0x33112200, + 0x8110, 0x33112200, + 0x8114, 0x00000000, + 0x8120, 0x10010000, + 0x8124, 0x00000000, + 0x812c, 0x0000c000, + 0x8138, 0x40000000, + 0x813c, 0x40000000, + 0x8140, 0x00000000, + 0x8144, 0x0b040b03, + 0x8148, 0x0a050b04, + 0x814c, 0x0a050b04, + 0x8150, 0xe4e40000, + 0x8158, 0xffffffff, + 0x815c, 0xffffffff, + 0x8160, 0xffffffff, + 0x8164, 0xffffffff, + 0x8168, 0xffffffff, + 0x816c, 0x1fffffff, + 0x81a0, 0x00000000, + 0x81ac, 0x003f2e2e, + 0x81b0, 0x003f2e2e, + 0x81bc, 0x005b5b5b, + 0x81c0, 0x005b5b5b, + 0x81b4, 0x00600060, + 0x81b8, 0x00600060, + 0x81cc, 0x00000000, + 0x81dc, 0x00000002, + 0x81e0, 0x00000000, + 0x81e4, 0x00000001, + 0x820c, 0x33112200, + 0x8210, 0x33112200, + 0x8214, 0x00000000, + 0x8220, 0x10010000, + 0x8224, 0x00000000, + 0x822c, 0x0000d000, + 0x8238, 0x40000000, + 0x823c, 0x40000000, + 0x8240, 0x00000000, + 0x8244, 0x0b040b03, + 0x8248, 0x0a050b04, + 0x824c, 0x0a050b04, + 0x8250, 0xe4e40000, + 0x8258, 0xffffffff, + 0x825c, 0xffffffff, + 0x8260, 0xffffffff, + 0x8264, 0xffffffff, + 0x8268, 0xffffffff, + 0x826c, 0x1fffffff, + 0x82a0, 0x00000000, + 0x82ac, 0x003f2e2e, + 0x82b0, 0x003f2e2e, + 0x82bc, 0x005b5b5b, + 0x82c0, 0x005b5b5b, + 0x82b4, 0x00600060, + 0x82b8, 0x00600060, + 0x82cc, 0x00000000, + 0x82dc, 0x00000002, + 0x82e0, 0x00100000, + 0x82e4, 0x00000001, + 0x81d8, 0x00000001, + 0x82d8, 0x00000001, + 0x8d00, 0x00000000, + 0x8d04, 0x00000000, + 0x8d08, 0x00000000, + 0x8d0c, 0x00000000, + 0x8d10, 0x00000000, + 0x8d14, 0x00000000, + 0x8d18, 0x00000000, + 0x8d1c, 0x00000000, + 0x8d20, 0x00000000, + 0x8d24, 0x00000000, + 0x8d28, 0x00000000, + 0x8d2c, 0x00000000, + 0x8d30, 0x00000000, + 0x8d34, 0x00000000, + 0x8d38, 0x00000000, + 0x8d3c, 0x00000000, + 0x8d40, 0x00000000, + 0x8d44, 0x00000000, + 0x8d48, 0x00000000, + 0x8d4c, 0x00000000, + 0x8d50, 0x00000000, + 0x8d54, 0x00000000, + 0x8d58, 0x00000000, + 0x8d5c, 0x00000000, + 0x8d60, 0x00000000, + 0x8d64, 0x00000000, + 0x8d68, 0x00000000, + 0x8d6c, 0x00000000, + 0x8d70, 0x00000000, + 0x8d74, 0x00000000, + 0x8d78, 0x00000000, + 0x8d7c, 0x00000000, + 0x8d80, 0x00000000, + 0x8d84, 0x00000000, + 0x8d88, 0x00000000, + 0x8d8c, 0x00000000, + 0x8d90, 0x00000000, + 0x8d94, 0x00000000, + 0x8d98, 0x00000000, + 0x8d9c, 0x00000000, + 0x8da0, 0x00000000, + 0x8da4, 0x00000000, + 0x8da8, 0x00000000, + 0x8dac, 0x00000000, + 0x8db0, 0x00000000, + 0x8db4, 0x00000000, + 0x8db8, 0x00000000, + 0x8dbc, 0x00000000, + 0x8dc0, 0x00000000, + 0x8dc4, 0x00000000, + 0x8dc8, 0x00000000, + 0x8dcc, 0x00000000, + 0x8dd0, 0x00000000, + 0x8dd4, 0x00000000, + 0x8dd8, 0x00000000, + 0x8ddc, 0x00000000, + 0x8de0, 0x00000000, + 0x8de4, 0x00000000, + 0x8de8, 0x00000000, + 0x8dec, 0x00000000, + 0x8df0, 0x00000000, + 0x8df4, 0x00000000, + 0x8df8, 0x00000000, + 0x8dfc, 0x00000000, + 0x8e00, 0x00000000, + 0x8e04, 0x00000000, + 0x8e08, 0x00000000, + 0x8e0c, 0x00000000, + 0x8e10, 0x00000000, + 0x8e14, 0x00000000, + 0x8e18, 0x00000000, + 0x8e1c, 0x00000000, + 0x8e20, 0x00000000, + 0x8e24, 0x00000000, + 0x8e28, 0x00000000, + 0x8e2c, 0x00000000, + 0x8e30, 0x00000000, + 0x8e34, 0x00000000, + 0x8e38, 0x00000000, + 0x8e3c, 0x00000000, + 0x8e40, 0x00000000, + 0x8e44, 0x00000000, + 0x8e48, 0x00000000, + 0x8e4c, 0x00000000, + 0x8e50, 0x00000000, + 0x8e54, 0x00000000, + 0x8e58, 0x00000000, + 0x8e5c, 0x00000000, + 0x8e60, 0x00000000, + 0x8e64, 0x00000000, + 0x8e68, 0x00000000, + 0x8e6c, 0x00000000, + 0x8e70, 0x00000000, + 0x8e74, 0x00000000, + 0x8e78, 0x00000000, + 0x8e7c, 0x00000000, + 0x8e80, 0x00000000, + 0x8e84, 0x00000000, + 0x8e88, 0x00000000, + 0x8e8c, 0x00000000, + 0x8e90, 0x00000000, + 0x8e94, 0x00000000, + 0x8e98, 0x00000000, + 0x8e9c, 0x00000000, + 0x8ea0, 0x00000000, + 0x8ea4, 0x00000000, + 0x8ea8, 0x00000000, + 0x8eac, 0x00000000, + 0x8eb0, 0x00000000, + 0x8eb4, 0x00000000, + 0x8eb8, 0x00000000, + 0x8ebc, 0x00000000, + 0x8ec0, 0x00000000, + 0x8ec4, 0x00000000, + 0x8ec8, 0x00000000, + 0x8ecc, 0x00000000, + 0x8ed0, 0x00000000, + 0x8ed4, 0x00000000, + 0x8ed8, 0x00000000, + 0x8edc, 0x00000000, + 0x8ee0, 0x00000000, + 0x8ee4, 0x00000000, + 0x8ee8, 0x00000000, + 0x8eec, 0x00000000, + 0x8ef0, 0x00000000, + 0x8ef4, 0x00000000, + 0x8ef8, 0x00000000, + 0x8efc, 0x00000000, + 0x8f00, 0x00000000, + 0x8f04, 0x00000000, + 0x8f08, 0x00000000, + 0x8f0c, 0x00000000, + 0x8f10, 0x00000000, + 0x8f14, 0x00000000, + 0x8f18, 0x00000000, + 0x8f1c, 0x00000000, + 0x8f20, 0x00000000, + 0x8f24, 0x00000000, + 0x8f28, 0x00000000, + 0x8f2c, 0x00000000, + 0x8f30, 0x00000000, + 0x8f34, 0x00000000, + 0x8f38, 0x00000000, + 0x8f3c, 0x00000000, + 0x8f40, 0x00000000, + 0x8f44, 0x00000000, + 0x8f48, 0x00000000, + 0x8f4c, 0x00000000, + 0x8f50, 0x00000000, + 0x8f54, 0x00000000, + 0x8f58, 0x00000000, + 0x8f5c, 0x00000000, + 0x8f60, 0x00000000, + 0x8f64, 0x00000000, + 0x8f68, 0x00000000, + 0x8f6c, 0x00000000, + 0x8f70, 0x00000000, + 0x8f74, 0x00000000, + 0x8f78, 0x00000000, + 0x8f7c, 0x00000000, + 0x8f80, 0x00000000, + 0x8f84, 0x00000000, + 0x8f88, 0x00000000, + 0x8f8c, 0x00000000, + 0x8f90, 0x00000000, + 0x8f94, 0x00000000, + 0x8f98, 0x00000000, + 0x8f9c, 0x00000000, + 0x8fa0, 0x00000000, + 0x8fa4, 0x00000000, + 0x8fa8, 0x00000000, + 0x8fac, 0x00000000, + 0x8fb0, 0x00000000, + 0x8fb4, 0x00000000, + 0x8fb8, 0x00000000, + 0x8fbc, 0x00000000, + 0x8fc0, 0x00000000, + 0x8fc4, 0x00000000, + 0x8fc8, 0x00000000, + 0x8fcc, 0x00000000, + 0x8fd0, 0x00000000, + 0x8fd4, 0x00000000, + 0x8fd8, 0x00000000, + 0x8fdc, 0x00000000, + 0x8fe0, 0x00000000, + 0x8fe4, 0x00000000, + 0x8fe8, 0x00000000, + 0x8fec, 0x00000000, + 0x8ff0, 0x00000000, + 0x8ff4, 0x00000000, + 0x8ff8, 0x00000000, + 0x8ffc, 0x00000000, + 0x9000, 0x00000000, + 0x9004, 0x00000000, + 0x9008, 0x00000000, + 0x900c, 0x00000000, + 0x9010, 0x00000000, + 0x9014, 0x00000000, + 0x9018, 0x00000000, + 0x901c, 0x00000000, + 0x9020, 0x00000000, + 0x9024, 0x00000000, + 0x9028, 0x00000000, + 0x902c, 0x00000000, + 0x9030, 0x00000000, + 0x9034, 0x00000000, + 0x9038, 0x00000000, + 0x903c, 0x00000000, + 0x9040, 0x00000000, + 0x9044, 0x00000000, + 0x9048, 0x00000000, + 0x904c, 0x00000000, + 0x9050, 0x00000000, + 0x9054, 0x00000000, + 0x9058, 0x00000000, + 0x905c, 0x00000000, + 0x9060, 0x00000000, + 0x9064, 0x00000000, + 0x9068, 0x00000000, + 0x906c, 0x00000000, + 0x9070, 0x00000000, + 0x9074, 0x00000000, + 0x9078, 0x00000000, + 0x907c, 0x00000000, + 0x9080, 0x00000000, + 0x9084, 0x00000000, + 0x9088, 0x00000000, + 0x908c, 0x00000000, + 0x9090, 0x00000000, + 0x9094, 0x00000000, + 0x9098, 0x00000000, + 0x909c, 0x00000000, + 0x90a0, 0x00000000, + 0x90a4, 0x00000000, + 0x90a8, 0x00000000, + 0x90ac, 0x00000000, + 0x90b0, 0x00000000, + 0x90b4, 0x00000000, + 0x90b8, 0x00000000, + 0x90bc, 0x00000000, + 0x9100, 0x00000000, + 0x9104, 0x00000000, + 0x9108, 0x00000000, + 0x910c, 0x00000000, + 0x9110, 0x00000000, + 0x9114, 0x00000000, + 0x9118, 0x00000000, + 0x911c, 0x00000000, + 0x9120, 0x00000000, + 0x9124, 0x00000000, + 0x9128, 0x00000000, + 0x912c, 0x00000000, + 0x9130, 0x00000000, + 0x9134, 0x00000000, + 0x9138, 0x00000000, + 0x913c, 0x00000000, + 0x9140, 0x00000000, + 0x9144, 0x00000000, + 0x9148, 0x00000000, + 0x914c, 0x00000000, + 0x9150, 0x00000000, + 0x9154, 0x00000000, + 0x9158, 0x00000000, + 0x915c, 0x00000000, + 0x9160, 0x00000000, + 0x9164, 0x00000000, + 0x9168, 0x00000000, + 0x916c, 0x00000000, + 0x9170, 0x00000000, + 0x9174, 0x00000000, + 0x9178, 0x00000000, + 0x917c, 0x00000000, + 0x9180, 0x00000000, + 0x9184, 0x00000000, + 0x9188, 0x00000000, + 0x918c, 0x00000000, + 0x9190, 0x00000000, + 0x9194, 0x00000000, + 0x9198, 0x00000000, + 0x919c, 0x00000000, + 0x91a0, 0x00000000, + 0x91a4, 0x00000000, + 0x91a8, 0x00000000, + 0x91ac, 0x00000000, + 0x91b0, 0x00000000, + 0x91b4, 0x00000000, + 0x91b8, 0x00000000, + 0x91bc, 0x00000000, + 0x91c0, 0x00000000, + 0x91c4, 0x00000000, + 0x91c8, 0x00000000, + 0x91cc, 0x00000000, + 0x91d0, 0x00000000, + 0x91d4, 0x00000000, + 0x91d8, 0x00000000, + 0x91dc, 0x00000000, + 0x91e0, 0x00000000, + 0x91e4, 0x00000000, + 0x91e8, 0x00000000, + 0x91ec, 0x00000000, + 0x91f0, 0x00000000, + 0x91f4, 0x00000000, + 0x91f8, 0x00000000, + 0x91fc, 0x00000000, + 0x9200, 0x00000000, + 0x9204, 0x00000000, + 0x9208, 0x00000000, + 0x920c, 0x00000000, + 0x9210, 0x00000000, + 0x9214, 0x00000000, + 0x9218, 0x00000000, + 0x921c, 0x00000000, + 0x9220, 0x00000000, + 0x9224, 0x00000000, + 0x9228, 0x00000000, + 0x922c, 0x00000000, + 0x9230, 0x00000000, + 0x9234, 0x00000000, + 0x9238, 0x00000000, + 0x923c, 0x00000000, + 0x9240, 0x00000000, + 0x9244, 0x00000000, + 0x9248, 0x00000000, + 0x924c, 0x00000000, + 0x9250, 0x00000000, + 0x9254, 0x00000000, + 0x9258, 0x00000000, + 0x925c, 0x00000000, + 0x9260, 0x00000000, + 0x9264, 0x00000000, + 0x9268, 0x00000000, + 0x926c, 0x00000000, + 0x9270, 0x00000000, + 0x9274, 0x00000000, + 0x9278, 0x00000000, + 0x927c, 0x00000000, + 0x9280, 0x00000000, + 0x9284, 0x00000000, + 0x9288, 0x00000000, + 0x928c, 0x00000000, + 0x9290, 0x00000000, + 0x9294, 0x00000000, + 0x9298, 0x00000000, + 0x929c, 0x00000000, + 0x92a0, 0x00000000, + 0x92a4, 0x00000000, + 0x92a8, 0x00000000, + 0x92ac, 0x00000000, + 0x92b0, 0x00000000, + 0x92b4, 0x00000000, + 0x92b8, 0x00000000, + 0x92bc, 0x00000000, + 0x92c0, 0x00000000, + 0x92c4, 0x00000000, + 0x92c8, 0x00000000, + 0x92cc, 0x00000000, + 0x92d0, 0x00000000, + 0x92d4, 0x00000000, + 0x92d8, 0x00000000, + 0x92dc, 0x00000000, + 0x92e0, 0x00000000, + 0x92e4, 0x00000000, + 0x92e8, 0x00000000, + 0x92ec, 0x00000000, + 0x92f0, 0x00000000, + 0x92f4, 0x00000000, + 0x92f8, 0x00000000, + 0x92fc, 0x00000000, + 0x9300, 0x00000000, + 0x9304, 0x00000000, + 0x9308, 0x00000000, + 0x930c, 0x00000000, + 0x9310, 0x00000000, + 0x9314, 0x00000000, + 0x9318, 0x00000000, + 0x931c, 0x00000000, + 0x9320, 0x00000000, + 0x9324, 0x00000000, + 0x9328, 0x00000000, + 0x932c, 0x00000000, + 0x9330, 0x00000000, + 0x9334, 0x00000000, + 0x9338, 0x00000000, + 0x933c, 0x00000000, + 0x9340, 0x00000000, + 0x9344, 0x00000000, + 0x9348, 0x00000000, + 0x934c, 0x00000000, + 0x9350, 0x00000000, + 0x9354, 0x00000000, + 0x9358, 0x00000000, + 0x935c, 0x00000000, + 0x9360, 0x00000000, + 0x9364, 0x00000000, + 0x9368, 0x00000000, + 0x936c, 0x00000000, + 0x9370, 0x00000000, + 0x9374, 0x00000000, + 0x9378, 0x00000000, + 0x937c, 0x00000000, + 0x9380, 0x00000000, + 0x9384, 0x00000000, + 0x9388, 0x00000000, + 0x938c, 0x00000000, + 0x9390, 0x00000000, + 0x9394, 0x00000000, + 0x9398, 0x00000000, + 0x939c, 0x00000000, + 0x93a0, 0x00000000, + 0x93a4, 0x00000000, + 0x93a8, 0x00000000, + 0x93ac, 0x00000000, + 0x93b0, 0x00000000, + 0x93b4, 0x00000000, + 0x93b8, 0x00000000, + 0x93bc, 0x00000000, + 0x93c0, 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0xe34b6e77, + 0x87e0, 0x21e8e3bf, + 0x87e4, 0x6e8b000b, + 0x87e8, 0xe3bfe34b, + 0x87ec, 0x000c21e8, + 0x87f0, 0xe34b6e9f, + 0x87f4, 0x0baae3bf, + 0x87f8, 0x21e87410, + 0x87fc, 0x6eb3000d, + 0x8800, 0xe34b6f0f, + 0x8804, 0x21e8e3bf, + 0x8808, 0x6ec7000e, + 0x880c, 0xe3bfe34b, + 0x8810, 0x74100bac, + 0x8814, 0x000f21e8, + 0x8818, 0x6f0f6edb, + 0x881c, 0xe3bfe34b, + 0x8820, 0x001021e8, + 0x8824, 0xe34b6eef, + 0x8828, 0xe3bfe3bf, + 0x882c, 0x001321e8, + 0x8830, 0x6f006e11, + 0x8834, 0xe3bfe34b, + 0x8838, 0x21e8e3bf, + 0x883c, 0x6e250014, + 0x8840, 0xe3bfe34b, + 0x8844, 0x21e8fbab, + 0x8848, 0x6e390015, + 0x884c, 0xe3bfe34b, + 0x8850, 0x001621e8, + 0x8854, 0xe34b6e4d, + 0x8858, 0xfcb0e3bf, + 0x885c, 0x001721e8, + 0x8860, 0xe34b6e61, + 0x8864, 0x21e8e3bf, + 0x8868, 0x6e750018, + 0x886c, 0xe3bfe34b, + 0x8870, 0x001921e8, + 0x8874, 0xe34b6e89, + 0x8878, 0x21e8e3bf, + 0x887c, 0x6e99001a, + 0x8880, 0xe3bfe34b, + 0x8884, 0xe2c5e367, + 0x8888, 0x00040001, + 0x888c, 0x42fc0004, + 0x8890, 0x60010007, + 0x8894, 0x42000004, + 0x8898, 0x62200007, + 0x889c, 0x00046200, + 0x88a0, 0x5b005501, + 0x88a4, 0x5b40e304, + 0x88a8, 0x00076605, + 0x88ac, 0x63006200, + 0x88b0, 0x0004e388, + 0x88b4, 0x0a010900, + 0x88b8, 0x0d000b40, + 0x88bc, 0x00320e01, + 0x88c0, 0x95090004, + 0x88c4, 0x790442fb, + 0x88c8, 0x43804200, + 0x88cc, 0x4d010007, + 0x88d0, 0x43000004, + 0x88d4, 0x05620007, + 0x88d8, 0x961d05a3, + 0x88dc, 0x0004e388, + 0x88e0, 0x0007e304, + 0x88e4, 0x07a306a2, + 0x88e8, 0x0004e388, + 0x88ec, 0xe378e304, + 0x88f0, 0xe3800002, + 0x88f4, 0x00074380, + 0x88f8, 0x00044d00, + 0x88fc, 0x42fe4300, + 0x8900, 0x42007900, + 0x8904, 0x00040001, + 0x8908, 0x000742fc, + 0x890c, 0x00046003, + 0x8910, 0x31cc4200, + 0x8914, 0x06a20007, + 0x8918, 0x31f807a3, + 0x891c, 0x77000005, + 0x8920, 0x52000007, + 0x8924, 0x42fe0004, + 0x8928, 0x60000007, + 0x892c, 0x42000004, + 0x8930, 0x60004380, + 0x8934, 0x62016100, + 0x8938, 0x00056310, + 0x893c, 0x55004100, + 0x8940, 0x5c020007, + 0x8944, 0x43000004, + 0x8948, 0xe2d70001, + 0x894c, 0x73000005, + 0x8950, 0xe2d70001, + 0x8954, 0x5d000006, + 0x8958, 0x42f70004, + 0x895c, 0x6c000005, + 0x8960, 0x42000004, + 0x8964, 0x0004e2de, + 0x8968, 0x00074380, + 0x896c, 0x4a004e00, + 0x8970, 0x00064c00, + 0x8974, 0x60007f00, + 0x8978, 0x00046f00, + 0x897c, 0x00054300, + 0x8980, 0x00017300, + 0x8984, 0xe2d70001, + 0x8988, 0x5d010006, + 0x898c, 0x61006002, + 0x8990, 0x00055601, + 0x8994, 0xe2e27710, + 0x8998, 0x73000005, + 0x899c, 0x43800004, + 0x89a0, 0x5e010007, + 0x89a4, 0x4d205e00, + 0x89a8, 0x4a084e20, + 0x89ac, 0x4c3f4960, + 0x89b0, 0x00064301, + 0x89b4, 0x63807f01, + 0x89b8, 0x00046010, + 0x89bc, 0x00064300, + 0x89c0, 0x00077402, + 0x89c4, 0x40004001, + 0x89c8, 0x0006ab00, + 0x89cc, 0x00077404, + 0x89d0, 0x40004001, + 0x89d4, 0x0004ab00, + 0x89d8, 0x00074380, + 0x89dc, 0x4e004d00, + 0x89e0, 0x4c004a00, + 0x89e4, 0x00064300, + 0x89e8, 0x63007f00, + 0x89ec, 0x00046000, + 0x89f0, 0x00014300, + 0x89f4, 0x73800005, + 0x89f8, 0x42fe0004, + 0x89fc, 0x6c010005, + 0x8a00, 0x000514c8, + 0x8a04, 0x00046c00, + 0x8a08, 0x00014200, + 0x8a0c, 0x0005e2ce, + 0x8a10, 0x00017300, + 0x8a14, 0x00040006, + 0x8a18, 0x42fa4380, + 0x8a1c, 0x42007c05, + 0x8a20, 0x7c5b0006, + 0x8a24, 0x7e5b7d5b, + 0x8a28, 0x00077f00, + 0x8a2c, 0x415b405b, + 0x8a30, 0x4300425b, + 0x8a34, 0x43000004, + 0x8a38, 0x00040001, + 0x8a3c, 0x60004380, + 0x8a40, 0x62016100, + 0x8a44, 0x42fa6310, + 0x8a48, 0x42007c00, + 0x8a4c, 0x00014300, + 0x8a50, 0x0001e2e5, + 0x8a54, 0x55000007, + 0x8a58, 0x74200004, + 0x8a5c, 0x79017711, + 0x8a60, 0x57005710, + 0x8a64, 0x00019700, + 0x8a68, 0x4e004f02, + 0x8a6c, 0x52015302, + 0x8a70, 0x43800001, + 0x8a74, 0x78006505, + 0x8a78, 0x7a007900, + 0x8a7c, 0x43007b00, + 0x8a80, 0x43800001, + 0x8a84, 0x43006500, + 0x8a88, 0x43800001, + 0x8a8c, 0x7c006405, + 0x8a90, 0x00014300, + 0x8a94, 0x64004380, + 0x8a98, 0x00014300, + 0x8a9c, 0x74200004, + 0x8aa0, 0x0005e392, + 0x8aa4, 0x73807388, + 0x8aa8, 0xe3a08f00, + 0x8aac, 0xe3920001, + 0x8ab0, 0x73810005, + 0x8ab4, 0x93007380, + 0x8ab8, 0x0001e3a0, + 0x8abc, 0xe2e5e3a7, + 0x8ac0, 0x0001e3ae, + 0x8ac4, 0xe3aee3a7, + 0x8ac8, 0x00040001, + 0x8acc, 0x24207410, + 0x8ad0, 0x14c80000, + 0x8ad4, 0x00002428, + 0x8ad8, 0x1a4215f4, + 0x8adc, 0x74300008, + 0x8ae0, 0x43800001, + 0x8ae4, 0x7a907b48, + 0x8ae8, 0x78027900, + 0x8aec, 0x55034300, + 0x8af0, 0x43803308, + 0x8af4, 0x7a807b38, + 0x8af8, 0x55134300, + 0x8afc, 0x43803308, + 0x8b00, 0x7a007b40, + 0x8b04, 0x55234300, + 0x8b08, 0x74007401, + 0x8b0c, 0x00018e00, + 0x8b10, 0x52300007, + 0x8b14, 0x74310004, + 0x8b18, 0x8e007430, + 0x8b1c, 0x52200007, + 0x8b20, 0x00010004, + 0x8b24, 0x57005702, + 0x8b28, 0x00018e00, + 0x8b2c, 0x561042ef, + 0x8b30, 0x42005600, + 0x8b34, 0x00018c00, + 0x8b38, 0x4e004f78, + 0x8b3c, 0x52015388, + 0x8b40, 0xe32b5b20, + 0x8b44, 0x54005480, + 0x8b48, 0x54005481, + 0x8b4c, 0x54005482, + 0x8b50, 0xbf1de336, + 0x8b54, 0xe2f13010, + 0x8b58, 0xe2ffe2f9, + 0x8b5c, 0xe3b3e312, + 0x8b60, 0xe3085523, + 0x8b64, 0xe3125525, + 0x8b68, 0x0001e3b3, + 0x8b6c, 0x54c054bf, + 0x8b70, 0x54c154a3, + 0x8b74, 0x4c1854a4, + 0x8b78, 0x54c2bf07, + 0x8b7c, 0xbf0454a4, + 0x8b80, 0x54a354c1, + 0x8b84, 0xe3c4bf01, + 0x8b88, 0x000154df, + 0x8b8c, 0x54e554bf, + 0x8b90, 0x54df050a, + 0x8b94, 0x16570001, + 0x8b98, 0x74307b80, + 0x8b9c, 0x7f404380, + 0x8ba0, 0x7d007e00, + 0x8ba4, 0x43007c02, + 0x8ba8, 0x55015b40, + 0x8bac, 0xe3165c01, + 0x8bb0, 0x54005480, + 0x8bb4, 0x54005481, + 0x8bb8, 0x54005482, + 0x8bbc, 0x74107b00, + 0x8bc0, 0xbfe5e336, + 0x8bc4, 0x56103010, + 0x8bc8, 0x8c005600, + 0x8bcc, 0x57040001, + 0x8bd0, 0x8e005700, + 0x8bd4, 0x57005708, + 0x8bd8, 0x57818e00, + 0x8bdc, 0x8e005780, + 0x8be0, 0x00074380, + 0x8be4, 0x5c005c01, + 0x8be8, 0x00041403, + 0x8bec, 0x00014300, + 0x8bf0, 0x0007427f, + 0x8bf4, 0x62006280, + 0x8bf8, 0x00049200, + 0x8bfc, 0x00014200, + 0x8c00, 0x0007427f, + 0x8c04, 0x63146394, + 0x8c08, 0x00049200, + 0x8c0c, 0x00014200, + 0x8c10, 0x42fe0004, + 0x8c14, 0x42007901, + 0x8c18, 0x14037420, + 0x8c1c, 0x57005710, + 0x8c20, 0x0001140f, + 0x8c24, 0x56010006, + 0x8c28, 0x54005502, + 0x8c2c, 0x7f000005, + 0x8c30, 0x77107e12, + 0x8c34, 0x75007600, + 0x8c38, 0x00047400, + 0x8c3c, 0x00014270, + 0x8c40, 0x42000004, + 0x8c44, 0x77000005, + 0x8c48, 0x56000006, + 0x8c4c, 0x00060001, + 0x8c50, 0x5f005f80, + 0x8c54, 0x00059900, + 0x8c58, 0x00017300, + 0x8c5c, 0x63800006, + 0x8c60, 0x98006300, + 0x8c64, 0x549f0001, + 0x8c68, 0x5c015400, + 0x8c6c, 0x540054df, + 0x8c70, 0x00015c02, + 0x8c74, 0x07145c01, + 0x8c78, 0x5c025400, + 0x8c7c, 0x5c020001, + 0x8c80, 0x54000714, + 0x8c84, 0x00015c01, + 0x8c88, 0x4c184c98, + 0x8c8c, 0x00040001, + 0x8c90, 0x74305c02, + 0x8c94, 0x0c010901, + 0x8c98, 0x00050ba6, + 0x8c9c, 0x00077780, + 0x8ca0, 0x00045220, + 0x8ca4, 0x60084380, + 0x8ca8, 0x6200610a, + 0x8cac, 0x000763ce, + 0x8cb0, 0x00045c00, + 0x8cb4, 0x00014300, + 0x8080, 0x00000004, + 0x8080, 0x00000000, + 0x8088, 0x00000000, +}; +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_raw_data_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_raw_data_8852b.h new file mode 100644 index 0000000..bb9656f --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_raw_data_8852b.h @@ -0,0 +1,10738 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 2.0.1.6*/ +#ifndef _HALRF_HWIMG_RAW_DATA_8852B_H +#define _HALRF_HWIMG_RAW_DATA_8852B_H + +#define D_S_SIZE DELTA_SWINGIDX_SIZE +#define D_ST_SIZE DELTA_SWINTSSI_SIZE + + +#if 0 +/* Please put following enum definitions in appropriate header file. */ +enum odm_pw_byrate_para_type { + PW_BYRATE_PARA_NSS1, + PW_BYRATE_PARA_NSS2, + PW_BYRATE_PARA_OFFS = 0xF +}; + +enum odm_pw_byrate_rate_type { + PW_BYRATE_RATE_11M_1M, + PW_BYRATE_RATE_18M_6M, + PW_BYRATE_RATE_54M_24M, + PW_BYRATE_RATE_MCS3_0, + PW_BYRATE_RATE_MCS7_4, + PW_BYRATE_RATE_MCS11_8, + PW_BYRATE_RATE_DCM4_0, + PW_BYRATE_RATE_AllRate2_1, /* CCK, OFDM, HT, VHT */ + PW_BYRATE_RATE_AllRate2_2, /* HE_HEDCM */ + PW_BYRATE_RATE_AllRate5_1, /* OFDM, HT, VHT, HE_HEDCM */ + PW_BYRATE_RATE_NULL = 0xF +}; + +enum odm_pw_lmt_regulation_type { + PW_LMT_REGU_FCC, + PW_LMT_REGU_ETSI, + PW_LMT_REGU_MKK, + PW_LMT_REGU_IC, + PW_LMT_REGU_KCC, + PW_LMT_REGU_ACMA, + PW_LMT_REGU_CHILE, + PW_LMT_REGU_UKRAINE, + PW_LMT_REGU_MEXICO, + PW_LMT_REGU_CN, + PW_LMT_REGU_WW13, + PW_LMT_REGU_NULL +}; + +enum odm_pw_lmt_band_type { + PW_LMT_BAND_2_4G, + PW_LMT_BAND_5G, + PW_LMT_BAND_NULL +}; + +enum odm_pw_lmt_bandwidth_type { + PW_LMT_BW_20M, + PW_LMT_BW_40M, + PW_LMT_BW_80M, + PW_LMT_BW_NULL +}; + +enum odm_pw_lmt_ru_bandwidth_type { + PW_LMT_RU_BW_RU26, + PW_LMT_RU_BW_RU52, + PW_LMT_RU_BW_RU106, + PW_LMT_RU_BW_NULL +}; + +enum odm_pw_lmt_ratesection_type { + PW_LMT_RS_CCK, + PW_LMT_RS_OFDM, + PW_LMT_RS_HT, + PW_LMT_RS_VHT, + PW_LMT_RS_HE, + PW_LMT_RS_NULL +}; + +enum odm_pw_lmt_beamform_type { + PW_LMT_BF, + PW_LMT_NONBF, + PW_LMT_NULL +}; + +enum odm_pw_lmt_rfpath_type { + PW_LMT_PH_1T, + PW_LMT_PH_2T, + PW_LMT_PH_3T, + PW_LMT_PH_4T, + PW_LMT_PH_NULL +}; + +struct halrf_tx_pw_lmt { + u8 band:1; + u8 bw:3; + u8 rs:2; + u8 ntx:2; + u8 bf:3; + u8 reg:5; + u8 ch; + s8 val; +}; + +struct halrf_tx_pw_lmt_ru { + u8 band:1; + u8 bw:2; + u8 ntx:2; + u8 rs:3; + u8 reg; + u8 ch; + s8 val; +}; +#endif + + +/****************************************************************************** + * radioa.TXT + ******************************************************************************/ + +const u32 array_mp_8852b_radioa[] = { + 0xF0010000, 0x00000000, + 0xF0020000, 0x00000001, + 0xF0010001, 0x00000002, + 0xF0020001, 0x00000003, + 0xF0030001, 0x00000004, + 0xF0040001, 0x00000005, + 0x005, 0x00000000, + 0x000, 0x00030000, + 0x10000, 0x00030000, + 0x018, 0x00011124, + 0x10018, 0x00011124, + 0x000, 0x00033C00, + 0x10000, 0x00033C00, + 0x01A, 0x00040004, + 0x0FE, 0x00000000, + 0x011, 0x00014073, + 0x067, 0x00000070, + 0x059, 0x000A0000, + 0x066, 0x00000100, + 0x057, 0x0000D589, + 0x05A, 0x0007FFFF, + 0x0A4, 0x0006FF12, + 0x043, 0x00005000, + 0x0E1, 0x00000001, + 0x0DD, 0x000001A0, + 0x0CA, 0x00002000, + 0x0D3, 0x00000103, + 0x0B3, 0x0004EFE0, + 0x0B4, 0x0007C07E, + 0x0B5, 0x0003A701, + 0x0B6, 0x000581E0, + 0x0B7, 0x00001A0A, + 0x0BB, 0x000C7000, + 0x0ED, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x00000543, + 0x033, 0x00000001, + 0x03F, 0x00000542, + 0x033, 0x00000002, + 0x03F, 0x00000541, + 0x033, 0x00000003, + 0x03F, 0x00000521, + 0x033, 0x00000004, + 0x03F, 0x00000343, + 0x033, 0x00000005, + 0x03F, 0x00000342, + 0x033, 0x00000006, + 0x03F, 0x00000341, + 0x033, 0x00000007, + 0x03F, 0x00000321, + 0x033, 0x00000008, + 0x03F, 0x000005C3, + 0x033, 0x00000009, + 0x03F, 0x000005C2, + 0x033, 0x0000000A, + 0x03F, 0x000005C1, + 0x033, 0x0000000B, + 0x03F, 0x000005A1, + 0x033, 0x0000000C, + 0x03F, 0x000002C3, + 0x033, 0x0000000D, + 0x03F, 0x000002C2, + 0x033, 0x0000000E, + 0x03F, 0x000002C1, + 0x033, 0x0000000F, + 0x03F, 0x000002A1, + 0x0ED, 0x00000000, + 0x0ED, 0x00002000, + 0x033, 0x00000002, + 0x03D, 0x0004A883, + 0x03E, 0x00000000, + 0x03F, 0x00000001, + 0x033, 0x00000006, + 0x03D, 0x0004A883, + 0x03E, 0x00000000, + 0x03F, 0x00000001, + 0x0ED, 0x00000000, + 0x018, 0x00001001, + 0x10018, 0x00001001, + 0x002, 0x0000000D, + 0x10002, 0x0000000D, + 0x0EE, 0x00000004, + 0x033, 0x0000000B, + 0x03F, 0x0000000B, + 0x033, 0x0000000C, + 0x03F, 0x00000012, + 0x033, 0x0000000D, + 0x03F, 0x00000019, + 0x0EE, 0x00000000, + 0x08F, 0x000D0F7A, + 0x0EF, 0x00080000, + 0x033, 0x00000008, + 0x03E, 0x000000C4, + 0x03F, 0x000034C0, + 0x033, 0x0000000A, + 0x03E, 0x000000C4, + 0x03F, 0x000035D0, + 0x033, 0x0000000B, + 0x03E, 0x000000C4, + 0x03F, 0x000035C8, + 0x0EF, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000006, + 0x03F, 0x00000700, + 0x033, 0x00000005, + 0x03F, 0x00090600, + 0x033, 0x00000004, + 0x03F, 0x000A3500, + 0x033, 0x00000003, + 0x03F, 0x000A3400, + 0x033, 0x00000002, + 0x03F, 0x00008B00, + 0x033, 0x00000001, + 0x03F, 0x00001B00, + 0x033, 0x00000000, + 0x03F, 0x00003A00, + 0x0EF, 0x00000000, + 0x0EE, 0x00000010, + 0x033, 0x00000006, + 0x03F, 0x00000003, + 0x033, 0x00000007, + 0x03F, 0x00000003, + 0x033, 0x00000008, + 0x03F, 0x00000001, + 0x0EE, 0x00000000, + 0x0EF, 0x00001000, + 0x033, 0x00000000, + 0x03F, 0x00000015, + 0x033, 0x00000001, + 0x03F, 0x00000017, + 0x0EF, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x00000000, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000001, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000002, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000003, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000004, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000005, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000006, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000008, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000009, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x0000000A, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x0000000B, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x0000000C, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x0000000D, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x0000000E, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000010, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000011, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000012, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000013, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000014, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000015, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000016, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000020, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000021, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000022, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000023, + 0x03E, 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0x000000EC, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000E7, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C6, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000A6, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C7, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 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0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001A, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000017, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000014, + 0xB0000000, 0x00000000, + 0x100EE, 0x00000000, + 0x100EE, 0x00004000, + 0x10033, 0x00000080, + 0x1003F, 0x000001A9, + 0x10033, 0x00000081, + 0x1003F, 0x000001A3, + 0x10033, 0x00000082, + 0x1003F, 0x0000019D, + 0x10033, 0x00000083, + 0x1003F, 0x00000197, + 0x10033, 0x00000084, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000191, + 0xB0000000, 0x00000000, + 0x10033, 0x00000085, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000018B, + 0xB0000000, 0x00000000, + 0x10033, 0x00000086, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000014D, + 0xB0000000, 0x00000000, + 0x10033, 0x00000087, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000010B, + 0xB0000000, 0x00000000, + 0x10033, 0x00000088, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xB0000000, 0x00000000, + 0x10033, 0x00000089, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008A, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D3, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008B, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000099, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000093, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008D, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000059, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008E, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000053, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008F, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000019, + 0xB0000000, 0x00000000, + 0x10033, 0x00000090, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000013, + 0xB0000000, 0x00000000, + 0x10033, 0x00000091, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A0, + 0x1003F, 0x000001A9, + 0x10033, 0x000000A1, + 0x1003F, 0x000001A3, + 0x10033, 0x000000A2, + 0x1003F, 0x0000019D, + 0x10033, 0x000000A3, + 0x1003F, 0x00000197, + 0x10033, 0x000000A4, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000191, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A5, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000018B, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A6, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000014D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A7, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000010B, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A8, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A9, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AA, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AB, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000099, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AC, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000093, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AD, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000059, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AE, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000053, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000019, + 0xB0000000, 0x00000000, + 0x10033, 0x000000B0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000013, + 0xB0000000, 0x00000000, + 0x10033, 0x000000B1, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C0, + 0x1003F, 0x000001A9, + 0x10033, 0x000000C1, + 0x1003F, 0x000001A3, + 0x10033, 0x000000C2, + 0x1003F, 0x0000019D, + 0x10033, 0x000000C3, + 0x1003F, 0x00000197, + 0x10033, 0x000000C4, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000191, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C5, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000018B, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C6, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000014D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C7, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000010B, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C8, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C9, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CA, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CB, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000099, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CC, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000093, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CD, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000059, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CE, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000053, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000019, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000013, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D1, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xB0000000, 0x00000000, + 0x100EE, 0x00000000, + 0x100EE, 0x00002000, + 0x10033, 0x00000000, + 0x1003F, 0x000000F6, + 0x10033, 0x00000001, + 0x1003F, 0x000000F3, + 0x10033, 0x00000002, + 0x1003F, 0x000000F0, + 0x10033, 0x00000003, + 0x1003F, 0x000000ED, + 0x10033, 0x00000004, + 0x1003F, 0x000000EA, + 0x10033, 0x00000005, + 0x1003F, 0x000000E7, + 0x10033, 0x00000006, + 0x1003F, 0x000000A6, + 0x10033, 0x00000007, + 0x1003F, 0x000000A3, + 0x10033, 0x00000008, + 0x1003F, 0x00000063, + 0x10033, 0x00000009, + 0x1003F, 0x00000060, + 0x10033, 0x0000000A, + 0x1003F, 0x00000023, + 0x10033, 0x0000000B, + 0x1003F, 0x00000020, + 0x10033, 0x0000000C, + 0x1003F, 0x0000001D, + 0x10033, 0x0000000D, + 0x1003F, 0x0000001A, + 0x10033, 0x0000000E, + 0x1003F, 0x00000017, + 0x10033, 0x0000000F, + 0x1003F, 0x00000014, + 0x10033, 0x00000010, + 0x1003F, 0x00000011, + 0x100EE, 0x00000000, + 0x100EE, 0x00004000, + 0x10033, 0x00000000, + 0x1003F, 0x000001AF, + 0x10033, 0x00000001, + 0x1003F, 0x000001A9, + 0x10033, 0x00000002, + 0x1003F, 0x000001A3, + 0x10033, 0x00000003, + 0x1003F, 0x0000019D, + 0x10033, 0x00000004, + 0x1003F, 0x00000197, + 0x10033, 0x00000005, + 0x1003F, 0x0000015F, + 0x10033, 0x00000006, + 0x1003F, 0x00000159, + 0x10033, 0x00000007, + 0x1003F, 0x0000011F, + 0x10033, 0x00000008, + 0x1003F, 0x00000119, + 0x10033, 0x00000009, + 0x1003F, 0x000000DF, + 0x10033, 0x0000000A, + 0x1003F, 0x000000D9, + 0x10033, 0x0000000B, + 0x1003F, 0x0000009F, + 0x10033, 0x0000000C, + 0x1003F, 0x00000099, + 0x10033, 0x0000000D, + 0x1003F, 0x0000005F, + 0x10033, 0x0000000E, + 0x1003F, 0x00000059, + 0x10033, 0x0000000F, + 0x1003F, 0x0000001F, + 0x10033, 0x00000010, + 0x1003F, 0x00000019, + 0x10033, 0x00000011, + 0x1003F, 0x00000013, + 0x100EE, 0x00000000, + 0x10005, 0x00000001, + 0x09F, 0x00000019, + +}; + + +/****************************************************************************** + * radiob.TXT + ******************************************************************************/ + +const u32 array_mp_8852b_radiob[] = { + 0xF0010000, 0x00000000, + 0xF0020000, 0x00000001, + 0xF0010001, 0x00000002, + 0xF0020001, 0x00000003, + 0xF0030001, 0x00000004, + 0xF0040001, 0x00000005, + 0x005, 0x00000000, + 0x000, 0x00030000, + 0x10000, 0x00030000, + 0x018, 0x00011124, + 0x10018, 0x00011124, + 0x000, 0x00033C00, + 0x10000, 0x00033C00, + 0x01A, 0x00040004, + 0x0FE, 0x00000000, + 0x011, 0x00014073, + 0x067, 0x00000070, + 0x059, 0x000A0000, + 0x066, 0x00000100, + 0x05A, 0x0007F000, + 0x0A4, 0x0006FF12, + 0x043, 0x00005000, + 0x0E1, 0x00000001, + 0x0DD, 0x000001A0, + 0x0CA, 0x00002000, + 0x0D3, 0x00000103, + 0x0B3, 0x0004EFE0, + 0x0B4, 0x0007C03E, + 0x0B5, 0x0003A201, + 0x0BB, 0x000C7000, + 0x0ED, 0x00002000, + 0x033, 0x00000002, + 0x03D, 0x0004A883, + 0x03E, 0x00000000, + 0x03F, 0x00000001, + 0x033, 0x00000006, + 0x03D, 0x0004A883, + 0x03E, 0x00000000, + 0x03F, 0x00000001, + 0x0ED, 0x00000000, + 0x018, 0x00001001, + 0x10018, 0x00001001, + 0x002, 0x0000000D, + 0x10002, 0x0000000D, + 0x0EE, 0x00000004, + 0x033, 0x0000000B, + 0x03F, 0x0000000B, + 0x033, 0x0000000C, + 0x03F, 0x00000012, + 0x033, 0x0000000D, + 0x03F, 0x00000019, + 0x0EE, 0x00000000, + 0x08F, 0x000D0F7A, + 0x0EF, 0x00080000, + 0x033, 0x00000008, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D30, + 0xA0000000, 0x00000000, + 0x03E, 0x000000C4, + 0x03F, 0x000034C0, + 0xB0000000, 0x00000000, + 0x033, 0x0000000A, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D74, + 0xA0000000, 0x00000000, + 0x03E, 0x000000C4, + 0x03F, 0x000035D0, + 0xB0000000, 0x00000000, + 0x033, 0x0000000B, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00000031, + 0x03F, 0x00000D72, + 0xA0000000, 0x00000000, + 0x03E, 0x000000C4, + 0x03F, 0x000035C8, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000007, + 0x03F, 0x00000707, + 0x033, 0x00000006, + 0x03F, 0x00000707, + 0x033, 0x00000005, + 0x03F, 0x00090607, + 0x033, 0x00000004, + 0x03F, 0x000A3507, + 0x033, 0x00000003, + 0x03F, 0x000A3407, + 0x033, 0x00000002, + 0x03F, 0x00008B07, + 0x033, 0x00000001, + 0x03F, 0x00001B07, + 0x033, 0x00000000, + 0x03F, 0x00003A07, + 0x033, 0x00000017, + 0x03F, 0x00000705, + 0x033, 0x00000016, + 0x03F, 0x00000705, + 0x033, 0x00000015, + 0x03F, 0x00090605, + 0x033, 0x00000014, + 0x03F, 0x000A3505, + 0x033, 0x00000013, + 0x03F, 0x000A3405, + 0x033, 0x00000012, + 0x03F, 0x00008B05, + 0x033, 0x00000011, + 0x03F, 0x00001B05, + 0x033, 0x00000010, + 0x03F, 0x00003A05, + 0x0EF, 0x00000000, + 0x0EE, 0x00000010, + 0x033, 0x00000006, + 0x03F, 0x00000003, + 0x033, 0x00000007, + 0x03F, 0x00000003, + 0x033, 0x00000008, + 0x03F, 0x00000001, + 0x0EE, 0x00000000, + 0x0EF, 0x00001000, + 0x033, 0x00000000, + 0x03F, 0x00000015, + 0x033, 0x00000001, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0xA0000000, 0x00000000, + 0x03F, 0x00000005, + 0xB0000000, 0x00000000, + 0x033, 0x00000002, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000017, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000015, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000015, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000015, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000015, + 0xA0000000, 0x00000000, + 0x03F, 0x00000017, + 0xB0000000, 0x00000000, + 0x033, 0x00000003, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0xA0000000, 0x00000000, + 0x03F, 0x00000007, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x00000000, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000001, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000002, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000003, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000004, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000005, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000006, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000008, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000009, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x0000000A, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x0000000B, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x0000000C, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x0000000D, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x0000000E, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000010, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000011, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000012, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000013, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000014, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000015, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000016, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000020, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000021, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000022, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000023, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000024, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000025, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000026, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000028, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000029, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x0000002A, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x0000002B, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x0000002C, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x0000002D, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x0000002E, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x033, 0x00000030, + 0x03E, 0x00004FC0, + 0x03F, 0x00000087, + 0x033, 0x00000031, + 0x03E, 0x000046C0, + 0x03F, 0x00000087, + 0x033, 0x00000032, + 0x03E, 0x00004240, + 0x03F, 0x00000087, + 0x033, 0x00000033, + 0x03E, 0x00008010, + 0x03F, 0x00000147, + 0x033, 0x00000034, + 0x03E, 0x0000A048, + 0x03F, 0x0000004F, + 0x033, 0x00000035, + 0x03E, 0x0000A030, + 0x03F, 0x0000005F, + 0x033, 0x00000036, + 0x03E, 0x0000A000, + 0x03F, 0x0000009F, + 0x0EF, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00004346, + 0x033, 0x00000001, + 0x03F, 0x00004346, + 0x033, 0x00000002, + 0x03F, 0x00004346, + 0x033, 0x00000003, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x00000004, + 0x03F, 0x00004346, + 0x033, 0x00000005, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004317, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004317, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004317, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004317, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x00000006, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x00000007, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x00000008, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x00000009, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004376, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x0000000A, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x0000000B, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x0000000D, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000043A6, + 0xA0000000, 0x00000000, + 0x03F, 0x00004346, + 0xB0000000, 0x00000000, + 0x033, 0x0000000E, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004366, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004366, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004346, + 0xA0000000, 0x00000000, + 0x03F, 0x00004366, + 0xB0000000, 0x00000000, + 0x033, 0x0000000F, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004366, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00004366, + 0x90010001, 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0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0xA0000000, 0x00000000, + 0x03F, 0x00027558, + 0xB0000000, 0x00000000, + 0x033, 0x0000002F, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0xA0000000, 0x00000000, + 0x03F, 0x00027558, + 0xB0000000, 0x00000000, + 0x033, 0x00000030, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00026458, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00026458, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0xA0000000, 0x00000000, + 0x03F, 0x00026458, + 0xB0000000, 0x00000000, + 0x033, 0x00000031, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00026458, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00026458, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022658, + 0xA0000000, 0x00000000, + 0x03F, 0x00026458, + 0xB0000000, 0x00000000, + 0x033, 0x00000032, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00022858, + 0xA0000000, 0x00000000, + 0x03F, 0x00027558, + 0xB0000000, 0x00000000, + 0x033, 0x00000033, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00027558, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0xA0000000, 0x00000000, + 0x03F, 0x00027558, + 0xB0000000, 0x00000000, + 0x033, 0x00000034, + 0x03E, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 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0x00000000, + 0x03F, 0x00020858, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00020858, + 0xA0000000, 0x00000000, + 0x03F, 0x00027558, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EE, 0x00000800, + 0x033, 0x00000000, + 0x03F, 0x00000001, + 0x033, 0x00000001, + 0x03F, 0x00000003, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x033, 0x00000003, + 0x03F, 0x00000007, + 0x033, 0x00000004, + 0x03F, 0x00000001, + 0x033, 0x00000005, + 0x03F, 0x00000003, + 0x033, 0x00000006, + 0x03F, 0x00000006, + 0x033, 0x00000007, + 0x03F, 0x00000007, + 0x0EE, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000000, + 0x03F, 0x00003000, + 0x033, 0x00000001, + 0x03F, 0x00003001, + 0x033, 0x00000002, + 0x03F, 0x00003003, + 0x033, 0x00000003, + 0x03F, 0x00003007, + 0x033, 0x00000004, + 0x03F, 0x0000300F, + 0x033, 0x00000005, + 0x03F, 0x0000310F, + 0x033, 0x00000006, + 0x03F, 0x0000330F, + 0x033, 0x00000007, + 0x03F, 0x0000330F, + 0x033, 0x00000008, + 0x03F, 0x00003000, + 0x033, 0x00000009, + 0x03F, 0x00003001, + 0x033, 0x0000000A, + 0x03F, 0x00003003, + 0x033, 0x0000000B, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003007, + 0xA0000000, 0x00000000, + 0x03F, 0x00003103, + 0xB0000000, 0x00000000, + 0x033, 0x0000000C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003107, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003107, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003107, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00003107, + 0x90030001, 0x00000000, 0x40000000, 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0x00001307, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00001307, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00001307, + 0xA0000000, 0x00000000, + 0x03F, 0x00000307, + 0xB0000000, 0x00000000, + 0x033, 0x0000000F, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000307, + 0xA0000000, 0x00000000, + 0x03F, 0x00000307, + 0xB0000000, 0x00000000, + 0x0EE, 0x00000000, + 0x0EE, 0x00000200, + 0x033, 0x00000000, + 0x03F, 0x00000001, + 0x033, 0x00000001, + 0x03F, 0x00000003, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x033, 0x00000003, + 0x03F, 0x00000007, + 0x0EE, 0x00000000, + 0x80010000, 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0x033, 0x00000003, + 0x03F, 0x000000FF, + 0x033, 0x00000004, + 0x03F, 0x000000FF, + 0x033, 0x00000005, + 0x03F, 0x000000FF, + 0x033, 0x00000006, + 0x03F, 0x000000FF, + 0x033, 0x00000007, + 0x03F, 0x000000FF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000001FF, + 0x033, 0x00000001, + 0x03F, 0x000001FF, + 0x033, 0x00000002, + 0x03F, 0x000001F7, + 0x033, 0x00000003, + 0x03F, 0x000000FF, + 0x033, 0x00000004, + 0x03F, 0x000000FF, + 0x033, 0x00000005, + 0x03F, 0x000000FF, + 0x033, 0x00000006, + 0x03F, 0x000000FF, + 0x033, 0x00000007, + 0x03F, 0x000000FF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000001FF, + 0x033, 0x00000001, + 0x03F, 0x000001FF, + 0x033, 0x00000002, + 0x03F, 0x0000013F, + 0x033, 0x00000003, + 0x03F, 0x000000FB, + 0x033, 0x00000004, + 0x03F, 0x000000FB, + 0x033, 0x00000005, + 0x03F, 0x000000FB, + 0x033, 0x00000006, + 0x03F, 0x000000FB, + 0x033, 0x00000007, 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0x0000007F, + 0x0EF, 0x00000000, + 0x06E, 0x00077A18, + 0x06F, 0x00077A18, + 0x06D, 0x00000C31, + 0x0EF, 0x00020000, + 0x033, 0x00000000, + 0x03F, 0x000005FF, + 0x0EF, 0x00000000, + 0x005, 0x00000001, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x094, 0x000000FC, + 0xA0000000, 0x00000000, + 0x094, 0x000001FC, + 0xB0000000, 0x00000000, + 0x100EE, 0x00002000, + 0x10033, 0x00000080, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020001, 0x00000000, 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0xB0000000, 0x00000000, + 0x10033, 0x00000088, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000063, + 0xB0000000, 0x00000000, + 0x10033, 0x00000089, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000060, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008A, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000026, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008B, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000023, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008C, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000020, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008D, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001D, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008E, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001A, + 0xB0000000, 0x00000000, + 0x10033, 0x0000008F, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000017, + 0xB0000000, 0x00000000, + 0x10033, 0x00000090, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000014, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F6, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A1, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A2, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F0, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A3, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000ED, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A4, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000EA, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A5, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000E7, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A6, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000A6, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A7, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000A3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A8, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000063, + 0xB0000000, 0x00000000, + 0x10033, 0x000000A9, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000060, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AA, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000026, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AB, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000023, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AC, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000025, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000020, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AD, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AE, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001A, + 0xB0000000, 0x00000000, + 0x10033, 0x000000AF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000017, + 0xB0000000, 0x00000000, + 0x10033, 0x000000B0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000014, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000FB, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F6, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C1, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F8, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C2, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F5, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000F0, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C3, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000F2, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000ED, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C4, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EF, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000EA, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C5, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000EC, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000E7, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C6, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000AB, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000A6, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C7, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000A8, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000A3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C8, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000068, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000063, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C9, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000065, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000060, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CA, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000002B, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000026, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CB, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000028, + 0x90020000, 0x00000000, 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0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000022, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001D, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CE, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000001A, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001C, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000017, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000014, + 0xB0000000, 0x00000000, + 0x100EE, 0x00000000, + 0x100EE, 0x00004000, + 0x10033, 0x00000080, + 0x1003F, 0x000001A9, + 0x10033, 0x00000081, + 0x1003F, 0x000001A3, + 0x10033, 0x00000082, + 0x1003F, 0x0000019D, + 0x10033, 0x00000083, + 0x1003F, 0x00000197, + 0x10033, 0x00000084, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000158, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000191, + 0xB0000000, 0x00000000, + 0x10033, 0x00000085, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000011F, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000018B, + 0xB0000000, 0x00000000, + 0x10033, 0x00000086, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000119, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000014D, + 0xB0000000, 0x00000000, + 0x10033, 0x00000087, + 0x80010000, 0x00000000, 0x40000000, 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0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000DF, + 0xB0000000, 0x00000000, + 0x10033, 0x000000C9, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000009F, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D9, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CA, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000099, + 0xA0000000, 0x00000000, + 0x1003F, 0x000000D3, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CB, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000005F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000099, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CC, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000059, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000093, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CD, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000001F, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000059, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CE, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000019, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000053, + 0xB0000000, 0x00000000, + 0x10033, 0x000000CF, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000013, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000019, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D0, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xA0000000, 0x00000000, + 0x1003F, 0x00000013, + 0xB0000000, 0x00000000, + 0x10033, 0x000000D1, + 0x80010000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020000, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90010001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90020001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90030001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0x90040001, 0x00000000, 0x40000000, 0x00000000, + 0x1003F, 0x00000007, + 0xA0000000, 0x00000000, + 0x1003F, 0x0000000D, + 0xB0000000, 0x00000000, + 0x100EE, 0x00000000, + 0x100EE, 0x00002000, + 0x10033, 0x00000000, + 0x1003F, 0x000000F6, + 0x10033, 0x00000001, + 0x1003F, 0x000000F3, + 0x10033, 0x00000002, + 0x1003F, 0x000000F0, + 0x10033, 0x00000003, + 0x1003F, 0x000000ED, + 0x10033, 0x00000004, + 0x1003F, 0x000000EA, + 0x10033, 0x00000005, + 0x1003F, 0x000000E7, + 0x10033, 0x00000006, + 0x1003F, 0x000000A6, + 0x10033, 0x00000007, + 0x1003F, 0x000000A3, + 0x10033, 0x00000008, + 0x1003F, 0x00000063, + 0x10033, 0x00000009, + 0x1003F, 0x00000060, + 0x10033, 0x0000000A, + 0x1003F, 0x00000023, + 0x10033, 0x0000000B, + 0x1003F, 0x00000020, + 0x10033, 0x0000000C, + 0x1003F, 0x0000001D, + 0x10033, 0x0000000D, + 0x1003F, 0x0000001A, + 0x10033, 0x0000000E, + 0x1003F, 0x00000017, + 0x10033, 0x0000000F, + 0x1003F, 0x00000014, + 0x10033, 0x00000010, + 0x1003F, 0x00000011, + 0x100EE, 0x00000000, + 0x100EE, 0x00004000, + 0x10033, 0x00000000, + 0x1003F, 0x000001AF, + 0x10033, 0x00000001, + 0x1003F, 0x000001A9, + 0x10033, 0x00000002, + 0x1003F, 0x000001A3, + 0x10033, 0x00000003, + 0x1003F, 0x0000019D, + 0x10033, 0x00000004, + 0x1003F, 0x00000197, + 0x10033, 0x00000005, + 0x1003F, 0x0000015F, + 0x10033, 0x00000006, + 0x1003F, 0x00000159, + 0x10033, 0x00000007, + 0x1003F, 0x0000011F, + 0x10033, 0x00000008, + 0x1003F, 0x00000119, + 0x10033, 0x00000009, + 0x1003F, 0x000000DF, + 0x10033, 0x0000000A, + 0x1003F, 0x000000D9, + 0x10033, 0x0000000B, + 0x1003F, 0x0000009F, + 0x10033, 0x0000000C, + 0x1003F, 0x00000099, + 0x10033, 0x0000000D, + 0x1003F, 0x0000005F, + 0x10033, 0x0000000E, + 0x1003F, 0x00000059, + 0x10033, 0x0000000F, + 0x1003F, 0x0000001F, + 0x10033, 0x00000010, + 0x1003F, 0x00000019, + 0x10033, 0x00000011, + 0x1003F, 0x00000013, + 0x100EE, 0x00000000, + 0x10005, 0x00000001, + 0x09F, 0x00000019, + +}; + + +/****************************************************************************** + * txpwr_lmt.TXT + ******************************************************************************/ + +const struct halrf_tx_pw_lmt array_mp_8852b_txpwr_lmt[] = { + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 80, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 72, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 72, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 58, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 70, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 58, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 76, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 58, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 68, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 68, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 52, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 44, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 44, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 74, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 48, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 64, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 64, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 36, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 32, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 66, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 78, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 1, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 1, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 1, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 1, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 1, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 2, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 2, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 2, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 2, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 2, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 3, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 3, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 3, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 3, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 3, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 4, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 4, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 4, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 4, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 4, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 5, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 5, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 5, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 6, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 6, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 6, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 7, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 7, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 7, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 8, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 8, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 8, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 9, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 9, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 9, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 10, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 10, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 10, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 11, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 11, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 11, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 12, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 12, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 12, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 13, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 13, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 13, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 76, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 40, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 40, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 1, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 1, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 2, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 2, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 3, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 3, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 3, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 3, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 3, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 4, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 4, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 4, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 4, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 4, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 5, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 5, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 5, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 5, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 5, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 6, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 6, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 6, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 6, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 6, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 7, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 7, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 7, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 7, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 7, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 8, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 8, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 8, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 8, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 8, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 9, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 9, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 9, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 9, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 9, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 10, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 10, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 10, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 10, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 10, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 11, 40, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 11, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 11, 68, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 11, 40, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 11, 36, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 12, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 12, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 13, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 13, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 74, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 62, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 50, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 36, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 36, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 36, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 36, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 36, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 40, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 40, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 40, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 40, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 40, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 44, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 44, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 44, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 44, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 44, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 48, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 48, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 48, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 48, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 48, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 52, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 52, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 52, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 52, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 52, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 56, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 56, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 56, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 56, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 56, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 60, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 60, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 60, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 60, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 60, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 64, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 64, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 64, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 64, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 64, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 100, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 100, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 100, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 104, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 104, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 104, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 108, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 108, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 108, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 112, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 112, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 112, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 116, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 116, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 116, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 120, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 120, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 120, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 124, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 124, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 124, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 128, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 128, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 128, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 132, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 132, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 132, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 132, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 132, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 136, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 136, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 136, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 136, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 136, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 140, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 140, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 140, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 140, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 144, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 149, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 149, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 149, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 153, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 153, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 153, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 157, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 157, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 157, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 161, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 161, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 161, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 165, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 165, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 165, 78, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 169, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 173, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 177, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 38, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 38, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 38, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 38, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 38, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 46, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 46, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 46, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 46, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 46, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 54, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 54, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 54, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 54, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 54, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 62, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 62, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 62, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 62, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 62, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 102, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 102, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 102, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 102, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 102, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 110, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 110, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 110, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 110, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 110, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 118, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 118, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 118, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 118, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 118, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 126, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 126, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 126, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 126, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 126, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 134, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 134, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 134, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 134, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 134, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 142, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 142, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 142, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 142, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 142, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 151, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 151, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 151, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 159, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 159, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 159, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 167, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 167, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 175, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 175, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 38, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 38, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 38, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 38, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 38, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 46, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 46, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 46, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 46, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 46, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 54, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 54, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 54, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 54, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 54, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 62, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 62, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 62, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 62, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 62, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 102, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 102, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 102, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 102, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 102, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 110, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 110, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 110, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 110, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 110, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 118, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 118, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 118, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 118, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 118, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 126, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 126, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 126, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 126, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 126, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 134, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 134, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 134, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 134, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 134, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 142, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 142, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 142, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 142, 78, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 142, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 151, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 151, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 151, 74, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 159, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 159, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 159, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 167, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 167, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 175, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 175, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 38, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 38, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 38, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 38, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 38, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 46, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 46, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 46, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 46, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 46, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 54, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 54, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 54, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 54, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 54, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 62, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 62, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 62, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 62, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 62, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 102, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 102, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 102, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 102, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 102, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 110, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 110, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 110, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 110, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 110, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 118, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 118, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 118, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 118, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 118, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 126, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 126, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 126, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 126, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 126, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 134, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 134, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 134, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 134, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 134, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 142, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 142, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 142, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 142, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 142, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 151, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 151, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 151, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 151, 74, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 159, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 159, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 159, 80, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 159, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 167, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 167, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 167, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 175, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 175, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 175, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 42, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 42, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 42, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 42, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 42, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 58, 68, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 58, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 58, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 58, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 58, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 106, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 106, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 106, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 106, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 106, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 122, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 122, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 122, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 122, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 122, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 138, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 138, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 138, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 155, 30, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 155, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 155, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 171, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 171, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 42, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 42, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 42, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 42, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 42, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 58, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 58, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 58, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 58, 54, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 58, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 106, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 106, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 106, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 106, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 106, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 122, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 122, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 122, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 122, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 122, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 138, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 138, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 138, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 155, 18, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 155, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 155, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 171, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 171, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 42, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 42, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 42, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 42, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 42, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 58, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 58, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 58, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 58, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 58, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 106, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 106, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 106, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 106, 58, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 106, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 122, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 122, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 122, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 122, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 122, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 138, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 138, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 138, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 138, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 155, 6, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 155, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 155, 76, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 155, 72, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 171, 60, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 171, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 171, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 171, 127, 0} +}; + + +/****************************************************************************** + * txpwr_lmt_ru.TXT + ******************************************************************************/ + +const struct halrf_tx_pw_lmt_ru array_mp_8852b_txpwr_lmt_ru[] = { + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 32, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 32, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 62, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 20, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 62, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 20, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 62, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 62, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 30, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 68, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 64, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 52, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 22, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 30, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 20, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 30, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 30, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 20, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 82, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 82, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 72, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 38, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 38, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 48, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 32, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 40, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 32, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 32, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 76, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 66, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 64, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 56, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 56, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 80, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 78, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 74, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 70, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 60, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 44, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 52, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 44, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 42, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3}, + {PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 24, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 24, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 24, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 24, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 26, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 46, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 24, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 0, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 4, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 14, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 0, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 14, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 0, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 14, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 14, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 32, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 34, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 12, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 38, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 82, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 20, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 20, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 20, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 36, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 36, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 36, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 36, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 58, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 62, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 52, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 64, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 64, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 10, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 14, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 20, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 10, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 20, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 10, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 20, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 20, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 40, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 42, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 40, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 40, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 44, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 38, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 22, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 48, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 42, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 48, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 82, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 82, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 32, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 46, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 46, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 46, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 66, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 68, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 70, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 72, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 48, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 66, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 70, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 76, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 56, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 56, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 56, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 20, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 18, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 22, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 22, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 34, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 52, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 56, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 36, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 54, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 50, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 60, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 44, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3}, + {PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0} +}; + + +/****************************************************************************** + * txpwr_tracktssi.TXT + ******************************************************************************/ + +const s8 delta_swingidx_mp_5gb_n_txpwrtrkssi_8852b[][D_S_SIZE] = { + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}, + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8}, + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, + 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}, +}; + +const s8 delta_swingidx_mp_5gb_p_txpwrtrkssi_8852b[][D_S_SIZE] = { + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8}, + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}, + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9}, +}; + +const s8 delta_swingidx_mp_5ga_n_txpwrtrkssi_8852b[][D_S_SIZE] = { + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, + 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4}, + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3}, + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3}, +}; + +const s8 delta_swingidx_mp_5ga_p_txpwrtrkssi_8852b[][D_S_SIZE] = { + {0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, + 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7}, + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9}, + {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, + 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, +}; + +const s8 delta_swingidx_mp_2gb_n_txpwrtrkssi_8852b[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2, -2}; +const s8 delta_swingidx_mp_2gb_p_txpwrtrkssi_8852b[] = { + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, + 3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 6, 6}; +const s8 delta_swingidx_mp_2ga_n_txpwrtrkssi_8852b[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +const s8 delta_swingidx_mp_2ga_p_txpwrtrkssi_8852b[] = { + 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, + 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5}; +const s8 delta_swingidx_mp_2g_cck_b_n_txpwrtrkssi_8852b[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}; +const s8 delta_swingidx_mp_2g_cck_b_p_txpwrtrkssi_8852b[] = { + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, + 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6}; +const s8 delta_swingidx_mp_2g_cck_a_n_txpwrtrkssi_8852b[] = { + 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -2, -2, + -2, -2, -2, -2, -2, -2, -3, -3, -3, -3, -3, -3, -3}; +const s8 delta_swingidx_mp_2g_cck_a_p_txpwrtrkssi_8852b[] = { + 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; + +/****************************************************************************** + * txpwr_byrate.TXT + ******************************************************************************/ + +const u32 array_mp_8852b_txpwr_byrate[] = { + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_11M_1M , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_18M_6M , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_54M_24M, 0x484c5050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS3_0 , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS7_4 , 0x44484c50, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS11_8, 0x34383c40, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_DCM4_0 , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS3_0 , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS7_4 , 0x44484c50, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS11_8, 0x34383c40, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_DCM4_0 , 0x50505050, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate2_1, 0x00000000, + PW_LMT_BAND_2_4G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate2_2, 0x00000000, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_18M_6M , 0x50505050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_54M_24M, 0x484c5050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS3_0 , 0x50505050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS7_4 , 0x44484c50, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS11_8, 0x34383c40, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_DCM4_0 , 0x50505050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS3_0 , 0x50505050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS7_4 , 0x44484c50, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS11_8, 0x34383c40, + PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_DCM4_0 , 0x50505050, + PW_LMT_BAND_5G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate5_1, 0x00000000 +}; + + +#endif /* _HALRF_HWIMG_RAW_DATA_8852B_H */ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.c new file mode 100644 index 0000000..9d1a2dc --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.c @@ -0,0 +1,2089 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +#ifndef __iram_func__ +#define __iram_func__ +#endif + + +const u32 array_set_nondbcc_path01_8852b[] = { +//02_BB_AFE_Non_DBCC_PHY0_path01 + 0x20fc, 0xffff0000, 0x0303, + 0x5864, 0x18000000, 0x3, + 0x7864, 0x18000000, 0x3, + 0x12b8, 0x40000000, 0x1, + 0x32b8, 0x40000000, 0x1, + 0x030c, 0xff000000, 0x13, + 0x032c, 0xffff0000, 0x0041, + 0x12b8, 0x10000000, 0x1, + 0x58c8, 0x01000000, 0x1, + 0x78c8, 0x01000000, 0x1, + 0x5864, 0xc0000000, 0x3, + 0x7864, 0xc0000000, 0x3, + 0x2008, 0x01ffffff, 0x1ffffff, + 0x0c1c, 0x00000004, 0x1, + 0x0700, 0x08000000, 0x1, + 0x0c70, 0x000003ff, 0x3ff, + 0x0c60, 0x00000003, 0x3, + 0x0c6c, 0x00000001, 0x1, + 0x58ac, 0x08000000, 0x1, + 0x78ac, 0x08000000, 0x1, + 0x0c3c, 0x00000200, 0x1, + 0x2344, 0x80000000, 0x1, + 0x4490, 0x80000000, 0x1, + 0x12a0, 0x00007000, 0x7, + 0x12a0, 0x00008000, 0x1, + 0x12a0, 0x00070000, 0x3, + 0x12a0, 0x00080000, 0x1, + 0x32a0, 0x00070000, 0x3, + 0x32a0, 0x00080000, 0x1, + 0x0700, 0x01000000, 0x1, + 0x0700, 0x06000000, 0x2, + 0x20fc, 0xffff0000, 0x3333, +}; + +const u32 array_restore_nondbcc_path01_8852b[] = { +//99_BB_AFE_Non_DBCC_PHY0_path01_restore + 0x20fc, 0xffff0000, 0x0303, + 0x12b8, 0x40000000, 0x0, + 0x32b8, 0x40000000, 0x0, + 0x5864, 0xc0000000, 0x0, + 0x7864, 0xc0000000, 0x0, + 0x2008, 0x01ffffff, 0x0000000, + 0x0c1c, 0x00000004, 0x0, + 0x0700, 0x08000000, 0x0, + 0x0c70, 0x0000001f, 0x03, + 0x0c70, 0x000003e0, 0x03, + 0x12a0, 0x000ff000, 0x00, + 0x32a0, 0x000ff000, 0x00, + 0x0700, 0x07000000, 0x0, + 0x20fc, 0xffff0000, 0x0000, + 0x58c8, 0x01000000, 0x0, + 0x78c8, 0x01000000, 0x0, + 0x0c3c, 0x00000200, 0x0, + 0x2344, 0x80000000, 0x0, +}; + +__iram_func__ +void iqk_backup_rf0_8852b( + struct rf_info *rf, u8 path, + u32 backup_rf0[rf_reg_num_8852b], + u32 backup_rf_reg0[rf_reg_num_8852b]) +{ + u8 i; + + if(path != RF_PATH_A) + return; + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + for (i = 0; i < rf_reg_num_8852b; i++) { + backup_rf0[i] = halrf_rrf(rf, RF_PATH_A, backup_rf_reg0[i], MASKRF); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]bk rf0, %x = %x\n", backup_rf_reg0[i], backup_rf0[i]); + } + return; +} + +__iram_func__ +void iqk_backup_rf1_8852b( + struct rf_info *rf, u8 path, + u32 backup_rf1[rf_reg_num_8852b], + u32 backup_rf_reg1[rf_reg_num_8852b]) +{ + u8 i; + + if(path != RF_PATH_B) + return; + + //DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK] 06 \n"); + for (i = 0; i < rf_reg_num_8852b; i++) { + backup_rf1[i] = halrf_rrf(rf, RF_PATH_B, backup_rf_reg1[i], MASKRF); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]bk rf1, %x = %x\n", backup_rf_reg1[i], backup_rf1[i]); + } + return; +} + +__iram_func__ +void iqk_restore_rf0_8852b( + struct rf_info *rf, u8 path, + u32 backup_rf0[rf_reg_num_8852b], + u32 backup_rf_reg0[rf_reg_num_8852b]) +{ + u32 i = 0; + + if(path != RF_PATH_A) + return; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + //DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK] 13 \n"); + for (i = 0; i < rf_reg_num_8852b; i++) { + halrf_wrf(rf, RF_PATH_A, backup_rf_reg0[i], MASKRF, backup_rf0[i]); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]restore rf0, 0x%x = 0x%x\n", backup_rf_reg0[i], halrf_rrf(rf, 0x0, backup_rf_reg0[i], MASKRF)); + } + return; +} + +__iram_func__ +void iqk_restore_rf1_8852b( + struct rf_info *rf, u8 path, + u32 backup_rf1[rf_reg_num_8852b], + u32 backup_rf_reg1[rf_reg_num_8852b]) +{ + u32 i; + + if(path != RF_PATH_B) + return; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + for (i = 0; i < rf_reg_num_8852b; i++) { + halrf_wrf(rf, RF_PATH_B, backup_rf_reg1[i], MASKRF, backup_rf1[i]); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]restore rf S%d = %x, value = %x\n", path, backup_rf_reg[path][i], halrf_rrf(rf, path, backup_rf_reg[path][i], MASKRF)); + } + return; +} + +#if 0 +static void _iqk_config_8852b_reg(struct rf_info *rf, u32 *array_map) +{ + u32 i = 0; + u32 array_len = 0x0; + u32 *array = NULL; + u32 addr = 0, mask = 0, val = 0; + + RF_DBG(rf, DBG_RF_INIT, "===> %s\n", __func__); + array_len = sizeof(array_map) / sizeof(u32); + array = (u32 *) &array_map; + while ((i + 1) < array_len) { + addr = array[i]; + mask = array[i + 1]; + val = array[i + 2]; + halrf_wreg(rf, addr, mask, val); + RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val); + i += 3; + } + +} +#endif + +__iram_func__ +static void _iqk_read_fft_dbcc0_8852b(struct rf_info *rf, u8 path) +{ + u8 i = 0x0; + u32 fft[6] = {0x0}; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00160000); + fft[0] = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00170000); + fft[1] = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00180000); + fft[2] = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00190000); + fft[3] = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x001a0000); + fft[4] = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x001b0000); + fft[5] = halrf_rreg(rf, 0x80fc, MASKDWORD); + for(i =0; i< 6; i++) + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x,fft[%x]= %x\n", path, i, fft[i]); + + return; +} + +__iram_func__ +static void _iqk_read_xym_dbcc0_8852b(struct rf_info *rf, u8 path) +{ + + u8 i = 0x0; + u32 tmp = 0x0; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + halrf_wreg(rf, 0x8000, 0x00000006, path); + halrf_wreg(rf, 0x801c, 0x00000003, 0x1); + + for (i = 0x0; i < 0x18; i++) { + halrf_wreg(rf, 0x8014, MASKDWORD, 0x000000c0 + i); + halrf_wreg(rf, 0x8014, MASKDWORD, 0x00000000); + tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = %x\n", path, 1 << path, tmp); + halrf_delay_us(rf, 1); + } + halrf_wreg(rf, 0x801c, 0x00000003, 0x0); + halrf_wreg(rf, 0x8138+ (path << 8), MASKDWORD, 0x40000000); + halrf_wreg(rf, 0x8014, MASKDWORD, 0x80010100); + halrf_delay_us(rf, 1); + + return; +} + +__iram_func__ +static void _iqk_read_txcfir_dbcc0_8852b(struct rf_info *rf, u8 path, u8 group) +{ + + u8 idx = 0x0; + u32 tmp = 0x0; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + halrf_wreg(rf, 0x81d8+ (path << 8), MASKDWORD, 0x00000001); + if (path == 0x0) { + switch (group) { + case 0: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x8f20 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f20 + (idx << 2), tmp); + } + break; + case 1: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x8f54 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f54 + (idx << 2), tmp); + } + break; + case 2: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x8f88 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f88 + (idx << 2), tmp); + } + break; + case 3: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x8fbc + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8fbc + (idx << 2), tmp); + } + break; + default: + break; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK]\n"); + tmp = halrf_rreg(rf, 0x8f50, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8f50 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8f84, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8f84 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8fb8, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8fb8 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8fec, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8fec = %x\n", tmp); + } else { + switch (group) { + case 0: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x9320 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9320 + (idx << 2), tmp); + } + break; + case 1: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x9354 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9354 + (idx << 2), tmp); + } + break; + case 2: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x9388 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9388 + (idx << 2), tmp); + } + break; + case 3: + for (idx = 0; idx < 0x0d; idx++) { + tmp = halrf_rreg(rf, 0x93bc + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x93bc + (idx << 2), tmp); + } + break; + default: + break; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK]\n"); + tmp = halrf_rreg(rf, 0x9350, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9350 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x9384, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9384 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x93b8, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x93b8 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x93ec, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x93ec = %x\n", tmp); + } + halrf_wreg(rf, 0x81d8+ (path << 8), MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x81d4 + (path << 8), 0x003f0000, 0xc); + halrf_delay_us(rf, 1); + tmp = halrf_rreg(rf, 0x81fc + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%xfc = %x\n", path, 1 << path, tmp); + + return; +} + +__iram_func__ +static void _iqk_read_rxcfir_dbcc0_8852b(struct rf_info *rf, u8 path, u8 group) +{ + + u8 idx = 0x0; + u32 tmp = 0x0; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000001); + + if (path == 0x0) { + switch (group) { + case 0: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x8d00 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d00 + (idx << 2), tmp); + } + break; + case 1: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x8d44 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d44 + (idx << 2), tmp); + } + break; + case 2: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x8d88 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d88 + (idx << 2), tmp); + } + break; + case 3: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x8dcc + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8dcc + (idx << 2), tmp); + } + break; + default: + break; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK]\n"); + tmp = halrf_rreg(rf, 0x8d40, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8d40 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8d84, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8d84 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8dc8, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8dc8 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x8e0c, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8e0c = %x\n", tmp); + } else { + switch (group) { + case 0: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x9100 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9100 + (idx << 2), tmp); + } + break; + case 1: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x9144 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9144 + (idx << 2), tmp); + } + break; + case 2: + for(idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x9188 + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9188 + (idx << 2), tmp); + } + break; + case 3: + for (idx = 0; idx < 0x10; idx++) { + tmp = halrf_rreg(rf, 0x91cc + (idx << 2), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x91cc + (idx << 2), tmp); + } + break; + default: + break; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK]\n"); + tmp = halrf_rreg(rf, 0x9140, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9140 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x9184, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9184 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x91c8, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x91c8 = %x\n", tmp); + tmp = halrf_rreg(rf, 0x920c, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x920c = %x\n", tmp); + } + halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x81d4 + (path << 8), 0x003f0000, 0xd); + tmp = halrf_rreg(rf, 0x81fc + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%xfc = %x\n", path, 1 << path, tmp); + + return; +} + +__iram_func__ +static void _iqk_sram_8852b(struct rf_info *rf, u8 path) +{ + + u32 tmp = 0x0; + u32 i = 0x0; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00020000); + halrf_wreg(rf, 0x80e8, MASKDWORD, 0x00000080); + halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000); + halrf_wreg(rf, 0x802c, 0x00000fff, 0x009); + + for (i = 0; i <= 0x9f; i++) { + halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 + i); + tmp = halrf_rreg(rf, 0x80fc, 0x0fff0000); + RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x\n", tmp); + } + + for (i = 0; i <= 0x9f; i++) { + halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 + i); + tmp = halrf_rreg(rf, 0x80fc, 0x00000fff); + RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x\n", tmp); + } + halrf_wreg(rf, 0x80e8, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00000000); + + return; +} + +__iram_func__ +static void _iqk_rxk_setting_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 tmp = 0x0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x0, 0xf0000, 0xc); + halrf_wrf(rf, path, 0x20, 0x00100, 0x1); + tmp = halrf_rrf(rf, path, 0x18, MASKRF); + halrf_wrf(rf, path, 0x1f, 0xfffff, tmp); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x0, 0xf0000, 0xc); + halrf_wrf(rf, path, 0x20, 0x00080, 0x1); + tmp = halrf_rrf(rf, path, 0x18, MASKRF); + halrf_wrf(rf, path, 0x1f, 0xfffff, tmp); + break; + default: + break; + } + return; +} + +__iram_func__ +static bool _iqk_check_cal_8852b(struct rf_info *rf, u8 path, u8 ktype) +{ + + //struct halrf_iqk_info *iqk_info = &rf->iqk; + bool notready = true, fail = true; + u32 delay_count = 0x0; + //u32 tmp = 0x0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + delay_count = 0x0; + while (notready) { + if (halrf_rreg(rf, 0xbff8, MASKBYTE0) == 0x55) { + halrf_delay_us(rf, 1); + if(halrf_rreg(rf, 0x8010, MASKBYTE0) == 0x55) + notready = false; + } else { + halrf_delay_us(rf, 1); + delay_count++; + } + if (delay_count > 8200) { + fail = true; + RF_DBG(rf, DBG_RF_IQK, "[IQK]IQK timeout!!!\n"); + break; + } + } + if (!notready) + fail = (bool)halrf_rreg(rf, 0x8008, BIT(26)); + halrf_wreg(rf, 0x8010, MASKBYTE0, 0x0); + + //DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK]%x\n", delay_count); +/* + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, cnt= %d\n", path, delay_count); + tmp = halrf_rreg(rf, 0x8008, MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, type= %x, 0x8008 = 0x%x \n", path, ktype, tmp); +*/ + return fail; +} + +__iram_func__ +static bool _iqk_one_shot_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path, u8 ktype) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool fail = false; + u32 iqk_cmd = 0x0; + u8 phy_map; + u32 addr_rfc_ctl = 0x0; + + phy_map = (BIT(phy_idx) << 4) | BIT(path); + + addr_rfc_ctl = 0x5864; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + //halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_IQK, RFK_ONESHOT_START); + switch (ktype) { + case ID_TXAGC: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d TXAGC ============\n", path); + iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); + break; + case ID_FLoK_coarse: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_coarse ============\n", path); + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1); + iqk_cmd = 0x108 | (1 << (4 + path)); + break; + case ID_FLoK_fine: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_fine ============\n", path); + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1); + iqk_cmd = 0x208 | (1 << (4 + path)); + break; + case ID_FLOK_vbuffer: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_fine ============\n", path); + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1); + iqk_cmd = 0x308 | (1 << (4 + path)); + break; + case ID_TXK: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_TXK ============\n", path); + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0); + iqk_cmd = 0x008 | (1 << (path + 4)) | (((0x8 + iqk_info->iqk_bw[path] ) & 0xf) << 8); + break; + case ID_RXAGC: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_RXAGC ============\n", path); + iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); + break; + case ID_RXK: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_RXK ============\n", path); + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1); + iqk_cmd = 0x008 | (1 << (path + 4)) | (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); + break; + case ID_NBTXK: + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0); + halrf_wreg(rf, 0x802c, 0x00000fff, 0x011); + iqk_cmd = 0x308 | (1 << (4 + path)); + break; + case ID_NBRXK: + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1); + halrf_wreg(rf, 0x802c, 0x0fff0000, 0x011); + iqk_cmd = 0x608 | (1 << (4 + path)); + break; + default: + return false; + break; + } + + halrf_wreg(rf, 0x8000, MASKDWORD, iqk_cmd + 1); + //halrf_delay_us(rf, 1); + halrf_delay_us(rf, 1); + fail = _iqk_check_cal_8852b(rf, path, ktype); + if (iqk_info->iqk_xym_en == true) + _iqk_read_xym_dbcc0_8852b(rf, path); + if (iqk_info->iqk_fft_en == true) + _iqk_read_fft_dbcc0_8852b(rf, path); + if (iqk_info->iqk_sram_en == true) + _iqk_sram_8852b(rf, path); + if (iqk_info->iqk_cfir_en == true) { + if (ktype == ID_TXK) { + _iqk_read_txcfir_dbcc0_8852b(rf, path, 0x0); + _iqk_read_txcfir_dbcc0_8852b(rf, path, 0x1); + _iqk_read_txcfir_dbcc0_8852b(rf, path, 0x2); + _iqk_read_txcfir_dbcc0_8852b(rf, path, 0x3); + } else { + _iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x0); + _iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x1); + _iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x2); + _iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x3); + } + } + + //8. IQK cotrol RFC + halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0); + + //halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_IQK, RFK_ONESHOT_STOP); + + return fail; +} + +__iram_func__ +static bool _rxk_group_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 gp = 0x0; + u32 a_idxrxgain[4] = {0x190, 0x198, 0x350, 0x352}; + u32 a_idxattc2[4] = {0x0f, 0x0f, 0x3f, 0x7f}; + u32 a_idxattc1[4] = {0x3, 0x1, 0x0, 0x0}; + + u32 g_idxrxgain[4] = {0x212, 0x21c, 0x350, 0x360}; + u32 g_idxattc2[4] = {0x00, 0x00, 0x28, 0x5f}; + u32 g_idxattc1[4] = {0x3, 0x3, 0x2, 0x1}; + bool fail = false; + bool kfail = false; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + + for (gp = 0; gp < 0x4; gp++) { + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x00, 0x03ff0, g_idxrxgain[gp]); + halrf_wrf(rf, path, 0x83, 0x1fc00, g_idxattc2[gp]); + halrf_wrf(rf, path, 0x83, 0x00300, g_idxattc1[gp]); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x00, 0x03ff0, a_idxrxgain[gp]); + halrf_wrf(rf, path, 0x8c, 0x0007f, a_idxattc2[gp]); + halrf_wrf(rf, path, 0x8c, 0x00180, a_idxattc1[gp]); + break; + default: + break; + } + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x0); + //halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, 0x0); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000007, gp); + fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_RXK); + halrf_wreg(rf, 0x9fe0, BIT(16 + gp + path * 4), fail); + kfail = kfail | fail; + } + halrf_wrf(rf, path, 0x20, 0x00080, 0x0); + + if (kfail) { + iqk_info->nb_rxcfir[path] = 0x40000002; + halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000f, 0x0); + iqk_info->is_wb_rxiqk[path] = false; + } else { + iqk_info->nb_rxcfir[path] = 0x40000000; + halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000f, 0x5); + iqk_info->is_wb_rxiqk[path] = true; + } +/* + tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x3c = 0x%x\n", path, 1 << path, tmp); +*/ + return kfail; +} + +__iram_func__ +static bool _iqk_nbrxk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 gp = 0x0; + u32 a_idxrxgain[4] = {0x190, 0x198, 0x350, 0x352}; + u32 a_idxattc2[4] = {0x0f, 0x0f, 0x3f, 0x7f}; + u32 a_idxattc1[4] = {0x3, 0x1, 0x0, 0x0}; + + u32 g_idxrxgain[4] = {0x212, 0x21c, 0x350, 0x360}; + u32 g_idxattc2[4] = {0x00, 0x00, 0x28, 0x5f}; + u32 g_idxattc1[4] = {0x3, 0x3, 0x2, 0x1}; + bool fail = false; + bool kfail = false; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + gp =0x3; + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x00, 0x03ff0, g_idxrxgain[gp]); + halrf_wrf(rf, path, 0x83, 0x1fc00, g_idxattc2[gp]); + halrf_wrf(rf, path, 0x83, 0x00300, g_idxattc1[gp]); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x00, 0x03ff0, a_idxrxgain[gp]); + halrf_wrf(rf, path, 0x8c, 0x0007f, a_idxattc2[gp]); + halrf_wrf(rf, path, 0x8c, 0x00180, a_idxattc1[gp]); + break; + default: + break; + } + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x0); + //halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, 0x0); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000007, gp); + halrf_wrf(rf, path, 0x1e, MASKRF, 0x80013); + halrf_delay_us(rf, 1); + fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_NBRXK); + halrf_wreg(rf, 0x9fe0, BIT(16 + gp + path * 4), fail); + kfail = kfail | fail; + halrf_wrf(rf, path, 0x20, 0x00080, 0x0); + + if (!kfail) { + iqk_info->nb_rxcfir[path] = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD) | 0x2; + } else { + iqk_info->nb_rxcfir[path] = 0x40000002; + } + //RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, result = %x, 0x8%x3c = 0x%x\n", path, fail, 1 << path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD)); + return kfail; +} + +__iram_func__ +static void _iqk_rxclk_setting_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + if (iqk_info->iqk_bw[path] == CHANNEL_WIDTH_80) { //BW80 + //07_CLK_Setting_RxIQK_BW80M_Non_DBCC_PHY0_path01 + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x0f); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x03); + halrf_wreg(rf, 0x032c, 0xffff0000, 0xa001); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x032c, 0xffff0000, 0xa041); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x2); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x2); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x1); + } else { + //07_CLK_Setting_RxIQK_BW40M_Non_DBCC_PHY0_path01 + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x0f); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x03); + halrf_wreg(rf, 0x032c, 0xffff0000, 0xa001); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x032c, 0xffff0000, 0xa041); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x0); + } + return; +} + +__iram_func__ +static bool _txk_group_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool fail = false; + bool kfail = false; + u8 gp = 0x0; + u32 a_power_range[4] = {0x0, 0x0, 0x0, 0x0}; + u32 a_track_range[4] = {0x3, 0x3, 0x6, 0x6}; + u32 a_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e}; + u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b}; + + u32 g_power_range[4] = {0x0, 0x0, 0x0, 0x0}; + u32 g_track_range[4] = {0x4, 0x4, 0x6, 0x6}; + u32 g_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e}; + u32 g_itqt[4] = { 0x09, 0x12, 0x1b, 0x24}; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + for (gp = 0x0; gp < 0x4; gp++) { + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x11, 0x00003, g_power_range[gp]); + halrf_wrf(rf, path, 0x11, 0x00070, g_track_range[gp]); + halrf_wrf(rf, path, 0x11, 0x1f000, g_gain_bb[gp]); + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, g_itqt[gp]); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x11, 0x00003, a_power_range[gp]); + halrf_wrf(rf, path, 0x11, 0x00070, a_track_range[gp]); + halrf_wrf(rf, path, 0x11, 0x1f000, a_gain_bb[gp]); + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, a_itqt[gp]); + break; + default: + break; + } + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); //man_sel_cfir_lut + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x1); //TX=0x1 or RX=0x0 + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0); //force to zero + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000003, gp);//remapping as {idx_rfgain, idx_txbb} + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_TXK); + halrf_wreg(rf, 0x9fe0, BIT(8 + gp + path * 4), fail); + kfail = kfail | fail; + } + if (kfail) { + iqk_info->nb_txcfir[path] = 0x40000002; + halrf_wreg(rf, 0x8124 + (path << 8), 0x00000f00, 0x0); + iqk_info->is_wb_txiqk[path] = false; + } else { + iqk_info->nb_txcfir[path] = 0x40000000; + halrf_wreg(rf, 0x8124 + (path << 8), 0x00000f00, 0x5); + iqk_info->is_wb_txiqk[path] = true; + } +/* + tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = 0x%x\n", path, 1 << path, tmp); +*/ + return kfail; +} + +__iram_func__ +static bool _iqk_nbtxk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool fail = false; + bool kfail = false; + u8 gp = 0x0; + u32 a_power_range[4] = {0x0, 0x0, 0x0, 0x0}; + u32 a_track_range[4] = {0x3, 0x3, 0x6, 0x6}; + u32 a_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e}; + u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b}; + + u32 g_power_range[4] = {0x0, 0x0, 0x0, 0x0}; + u32 g_track_range[4] = {0x4, 0x4, 0x6, 0x6}; + u32 g_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e}; + u32 g_itqt[4] = { 0x09, 0x12, 0x1b, 0x24}; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + gp = 0x3; + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x11, 0x00003, g_power_range[gp]); + halrf_wrf(rf, path, 0x11, 0x00070, g_track_range[gp]); + halrf_wrf(rf, path, 0x11, 0x1f000, g_gain_bb[gp]); + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, g_itqt[gp]); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x11, 0x00003, a_power_range[gp]); + halrf_wrf(rf, path, 0x11, 0x00070, a_track_range[gp]); + halrf_wrf(rf, path, 0x11, 0x1f000, a_gain_bb[gp]); + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, a_itqt[gp]); + break; + default: + break; + } + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); //man_sel_cfir_lut + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x1); //TX=0x1 or RX=0x0 + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0); //force to zero + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000003, gp);//remapping as {idx_rfgain, idx_txbb} + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_NBTXK); + kfail = kfail | fail; + + if (!kfail) { + iqk_info->nb_txcfir[path] = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD) | 0x2; + } else { + iqk_info->nb_txcfir[path] = 0x40000002; + } +/* + tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = 0x%x\n", path, 1 << path, + tmp); +*/ + return kfail; +} + +__iram_func__ +static void _lok_res_table_8852b(struct rf_info *rf, u8 path, u8 ibias) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, ibias = %x\n", path, ibias); + halrf_wrf(rf, path, 0xef, MASKRF, 0x2); + if (iqk_info->iqk_band[path] == BAND_ON_24G) + halrf_wrf(rf, path, 0x33, MASKRF, 0x0); + else + halrf_wrf(rf, path, 0x33, MASKRF, 0x1); + halrf_wrf(rf, path, 0x3f, MASKRF, ibias); + halrf_wrf(rf, path, 0xef, MASKRF, 0x0); + halrf_wrf(rf, path, 0x7c, BIT(5), 0x1); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x7c = %x\n", path, halrf_rrf(rf, path, 0x7c,MASKRF)); + + + return; +} + +__iram_func__ +static bool _lok_finetune_check_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool is_fail = false, is_fail1 = false, is_fail2 = false; + u32 temp = 0x0; + u32 core_i = 0x0; + u32 core_q = 0x0; + u32 fine_i = 0x0; + u32 fine_q = 0x0; + u8 ch = 0x0; + u32 vbuff_i = 0x0; + u32 vbuff_q = 0x0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + temp = halrf_rrf(rf, path, 0x58, MASKRF); + core_i = (temp & 0xf8000) >> 15; + core_q = (temp & 0x07c00) >> 10; + fine_i = (temp & 0x003c0) >> 6; + fine_q = (temp & 0x0003c) >> 2; + ch = ((iqk_info->iqk_times /2) % 2) & 0x1; + + if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) { + is_fail1 = true; + } else { + is_fail1 = false; + } + iqk_info->lok_idac[ch][path] = temp; + + temp = halrf_rrf(rf, path, 0x0a, MASKRF); + vbuff_i = (temp & 0xfc000) >> 14; + vbuff_q = (temp & 0x003f0) >> 4; + + if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d) { + is_fail2 = true; + } else { + is_fail2 = false; + } + iqk_info->lok_vbuf[ch][path] = temp; + + is_fail = is_fail1 | is_fail2; + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path, iqk_info->lok_idac[ch][path]); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path, iqk_info->lok_vbuf[ch][path]); + + return is_fail; +} + +__iram_func__ +static bool _iqk_lok_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool fail = false; + bool tmp = false; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + + //Init RF gain & tone idx= 8.25Mhz + halrf_wreg(rf, 0x802c, 0x00000fff, 0x021); + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + //halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + halrf_wrf(rf, path, 0x11, 0x00070, 0x4); + //halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + default: + break; + } + +//Step 1 small mod gain + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + case BAND_ON_5G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x4); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + default: + break; + } + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x9); + tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLoK_coarse); + iqk_info->lok_cor_fail[0][path] = tmp; + +//Step 2 large mod gain + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x12); + break; + case BAND_ON_5G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x4); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x12); + break; + default: + break; + } + + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x24); + tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLOK_vbuffer); + +//Step 3 small rf gain + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + case BAND_ON_5G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x4); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0); + break; + default: + break; + } + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x9); + halrf_wreg(rf, 0x802c, 0x00000fff, 0x021); + tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLoK_fine); + iqk_info->lok_fin_fail[0][path] = tmp; + +//Step 4 large rf gain + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x5); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x12); + break; + case BAND_ON_5G: + //halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + //halrf_wrf(rf, path, 0x11, 0x00070, 0x4); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x12); + break; + default: + break; + } + + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x24); + tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLOK_vbuffer); + + fail = _lok_finetune_check_8852b(rf, path); + + return fail; +} + +__iram_func__ +static void _iqk_txk_setting_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + //u32 tmp = 0x0; + + //TX init gain setting + /*0/1:G/A*/ + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + //05a_G_S0_TxLOK_52B_reg + halrf_wrf(rf, path, 0x90, 0x00300, 0x00); + halrf_wrf(rf, path, 0x51, 0x80000, 0x0); + halrf_wrf(rf, path, 0x51, 0x00800, 0x0); + halrf_wrf(rf, path, 0x52, 0x00800, 0x1); + halrf_wrf(rf, path, 0x55, 0x0001f, 0x0); + halrf_wrf(rf, path, 0xef, 0x00004, 0x1); + halrf_wrf(rf, path, 0x33, 0x000ff, 0x00); + halrf_wrf(rf, path, 0x0, 0xffff0, 0x403e); + halrf_delay_us(rf, 1); + break; + case BAND_ON_5G: + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + //05a_A_S0_TxLOK_52B__reg + halrf_wrf(rf, path, 0x85, 0x00003, 0x00); + halrf_wrf(rf, path, 0x60, 0x00007, 0x1); + halrf_wrf(rf, path, 0x55, 0x0001f, 0x0); + halrf_wrf(rf, path, 0xef, 0x00004, 0x1); + halrf_wrf(rf, path, 0x33, 0x000ff, 0x80); + halrf_wrf(rf, path, 0x0, 0xffff0, 0x403e); + halrf_delay_us(rf, 1); + break; + default: + break; + } +/* + tmp = halrf_rrf(rf, path, 0x00, MASKRF); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, rf%x = 0x%x\n", path, path, tmp); +*/ + return; +} + +__iram_func__ +static void _iqk_txclk_setting_8852b(struct rf_info *rf, u8 path) +{ + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + //04_CLK_Setting_TxIQK_DAC960MHz_nonDBCC_PHY0_path01_reg + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x1f); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0001); + halrf_delay_us(rf, 1); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + return; +} + +__iram_func__ +static void _iqk_info_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 tmp = 0x0; + bool flag = 0x0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + iqk_info->thermal[path] = halrf_get_thermal_8852b(rf, path); + iqk_info->thermal_rek_en = false; +/* + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_thermal = %d\n", path, + iqk_info->thermal[path] ); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_LOK_COR_fail= %d\n", path, + iqk_info->lok_cor_fail[0][path]); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, + iqk_info->lok_fin_fail[0][path]); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_TXIQK_fail = %d\n", path, + iqk_info->iqk_tx_fail[0][path]); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_RXIQK_fail= %d,\n", path, + iqk_info->iqk_rx_fail[0][path]); +*/ + flag = iqk_info->lok_cor_fail[0][path]; + halrf_wreg(rf, 0x9fe0, BIT(0) << (path * 4), flag); + flag = iqk_info->lok_fin_fail[0][path]; + halrf_wreg(rf, 0x9fe0, BIT(1) << (path * 4), flag); + flag = iqk_info->iqk_tx_fail[0][path]; + halrf_wreg(rf, 0x9fe0, BIT(2) << (path * 4), flag); + flag = iqk_info->iqk_rx_fail[0][path]; + halrf_wreg(rf, 0x9fe0, BIT(3) << (path * 4), flag); + + tmp = halrf_rreg(rf, 0x8124 + (path << 8), MASKDWORD); + iqk_info->bp_iqkenable[path] = tmp; + tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD); + iqk_info->bp_txkresult[path] = tmp; + tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD); + iqk_info->bp_rxkresult[path] = tmp; + + halrf_wreg(rf, 0x9fe8, 0x0000ff00, (u8)iqk_info->iqk_times); + + tmp = halrf_rreg(rf, 0x9fe0, 0x0000000f << (path * 4)); + if (tmp != 0x0) + iqk_info->iqk_fail_cnt++; + halrf_wreg(rf, 0x9fe8, 0x00ff0000 << (path * 4), iqk_info->iqk_fail_cnt); + return; + +} + +__iram_func__ +void iqk_set_info_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 tmp = 0x0; + bool flag = 0x0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + iqk_info->thermal[path] = halrf_get_thermal_8852b(rf, path); + iqk_info->thermal_rek_en = false; + + flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(0) << (path * 4)); + iqk_info->lok_cor_fail[0][path] = flag; + + flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(1) << (path * 4)); + iqk_info->lok_fin_fail[0][path] = flag; + + flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(2) << (path * 4)); + iqk_info->iqk_tx_fail[0][path] = flag; + + flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(3) << (path * 4)); + iqk_info->iqk_rx_fail[0][path] = flag; + + tmp = halrf_rreg(rf, 0x8124 + (path << 8), MASKDWORD); + iqk_info->bp_iqkenable[path] = tmp; + + tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD); + iqk_info->bp_txkresult[path] = tmp; + + tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD); + iqk_info->bp_rxkresult[path] = tmp; + + iqk_info->iqk_times = (u8) halrf_rreg(rf, 0x9fe8, 0x0000ff00); + iqk_info->iqk_fail_cnt = halrf_rreg(rf, 0x9fe8, 0x00ff0000 << (path * 4)); + return; +} + + +__iram_func__ +static void _iqk_by_path_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path) +{ + + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool lok_is_fail = false; + u8 ibias = 0x1; + u8 i = 0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + _iqk_txclk_setting_8852b(rf, path); + + //LOK + for (i = 0; i < 3; i++) { + _lok_res_table_8852b(rf, path, ibias++); + _iqk_txk_setting_8852b(rf, path); + lok_is_fail = _iqk_lok_8852b(rf, phy_idx, path); + if (!lok_is_fail) + break; + } + //TXK + if (iqk_info->is_nbiqk) { + iqk_info->iqk_tx_fail[0][path] = + _iqk_nbtxk_8852b(rf, phy_idx, path); + } else { + iqk_info->iqk_tx_fail[0][path] = + _txk_group_sel_8852b(rf, phy_idx, path); + } + //RX + _iqk_rxclk_setting_8852b(rf, path); + _iqk_rxk_setting_8852b(rf, path); + if (iqk_info->is_nbiqk) { + iqk_info->iqk_rx_fail[0][path] = + _iqk_nbrxk_8852b(rf, phy_idx, path); + } else { + iqk_info->iqk_rx_fail[0][path] = + _rxk_group_sel_8852b(rf, phy_idx, path); + } + _iqk_info_iqk_8852b(rf, phy_idx, path); + return; +} + +__iram_func__ +bool iqk_mcc_page_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path) +{ +#if 0 + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool flag = false; + + if (rf->hal_com->band[phy].cur_chandef.center_ch == iqk_info->iqk_mcc_ch[0][path]) { + halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, 0x0); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0); + _iqk_mcc_load_lok_8852b(rf, phy, path, iqk_info->lok_idac[0][path]); + flag = true; + } else if (rf->hal_com->band[phy].cur_chandef.center_ch == iqk_info->iqk_mcc_ch[1][path]) { + halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, 0x1); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x1); + _iqk_mcc_load_lok_8852b(rf, phy, path, iqk_info->lok_idac[1][path]); + flag = true; + } else + flag = false; +#endif + return false; +} + +__iram_func__ +void iqk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 reg_rf18 = 0x0; + u32 reg_35c = 0x0; + u8 ver; + u8 idx = 0; + u8 get_empty_table = false; + + for (idx = 0; idx < 2; idx++) { + if (iqk_info->iqk_mcc_ch[idx][path] == 0) { + get_empty_table = true; + break; + } + } + RF_DBG(rf, DBG_RF_IQK, "[IQK] (1) idx = %x\n", idx); + + if (false == get_empty_table) { + idx = iqk_info->iqk_table_idx[path] + 1; + if (idx > 1) { + idx = 0; + } + //RF_DBG(rf, DBG_RF_IQK, "[IQK]we will replace iqk table index(%d), !!!!! \n", idx); + } + RF_DBG(rf, DBG_RF_IQK, "[IQK] (2) idx = %x\n", idx); + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + reg_rf18 = halrf_rrf(rf, path, 0x18, MASKRF); + reg_35c = halrf_rreg(rf, 0x35c, 0x00000c00); + +#if 1 + iqk_info->iqk_band[path] = rf->hal_com->band[phy].cur_chandef.band; + iqk_info->iqk_bw[path] = rf->hal_com->band[phy].cur_chandef.bw; + iqk_info->iqk_ch[path] = rf->hal_com->band[phy].cur_chandef.center_ch; + iqk_info->iqk_mcc_ch[idx][path] = rf->hal_com->band[phy].cur_chandef.center_ch; + iqk_info->iqk_table_idx[path] = idx; + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n", path, reg_rf18, idx); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, iqk_info->iqk_band[path]); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", path, iqk_info->iqk_bw[path]); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", path, iqk_info->iqk_ch[path]); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_mcc_ch[%x][%x]= 0x%x\n", ch, path, iqk_info->iqk_mcc_ch[ch][path]); +#else + /*0/1:G/A*/ + if (((reg_rf18 & BIT(16)) >> 16)== 0x0) + iqk_info->iqk_band[path] = BAND_ON_24G; + else + iqk_info->iqk_band[path] = BAND_ON_5G; + + iqk_info->iqk_mcc_ch[ch][path] = (u8)reg_rf18 & 0xff; + iqk_info->iqk_ch[path] = (u8)reg_rf18 & 0xff; + + /*3/2/1:20/40/80*/ + if (((reg_rf18 & 0xc00) >> 10)== 0x3) + iqk_info->iqk_bw[path] = CHANNEL_WIDTH_20; //Bw20 + else if (((reg_rf18 & 0xc00) >> 10)== 0x2) + iqk_info->iqk_bw[path] = CHANNEL_WIDTH_40; //Bw40 + else + iqk_info->iqk_bw[path] = CHANNEL_WIDTH_80; //Bw80 +#endif +#if 1 + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x18= 0x%x\n", path, reg_rf18); + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", + path, phy, rf->hal_com->dbcc_en ? "on" : "off", + iqk_info->iqk_band[path] == 0 ? "2G" : (iqk_info->iqk_band[path] == 1 ? "5G" : "6G"), + iqk_info->iqk_ch[path] , + iqk_info->iqk_bw[path] == 0 ? "20M" : (iqk_info->iqk_bw[path] == 1 ? "40M" : "80M")); + RF_DBG(rf, DBG_RF_IQK, "[IQK] times = 0x%x, ch =%x\n", iqk_info->iqk_times , idx); + RF_DBG(rf, DBG_RF_IQK, "[IQK] iqk_mcc_ch[%x][%x] = 0x%x\n", (u8)idx, (u8)path, iqk_info->iqk_mcc_ch[idx][path]); +#endif +#if 1 + if (reg_35c == 0x01) + iqk_info->syn1to2 = 0x1; + else + iqk_info->syn1to2 = 0x0; +#else + iqk_info->syn1to2 = 0x1; +#endif + + RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path, iqk_info->syn1to2); + + halrf_wreg(rf, 0x9fe0, 0xff000000, iqk_version_8852b); + //2G5G6G = 0/1/2 + halrf_wreg(rf, 0x9fe4, 0x000f << (path * 16), (u8)iqk_info->iqk_band[path]); + //20/40/80 = 0/1/2 + halrf_wreg(rf, 0x9fe4, 0x00f0 << (path * 16), (u8)iqk_info->iqk_bw[path]); + halrf_wreg(rf, 0x9fe4, 0xff00 << (path * 16), (u8)iqk_info->iqk_ch[path]); + + ver = (u8) halrf_get_8852b_nctl_reg_ver(); + halrf_wreg(rf, 0x9fe8, 0x000000ff, ver); + + +#if 0 + if (iqk_info->iqk_band[path] == BAND_ON_5G) + RF_DBG(rf, DBG_RF_IQK, "[IQK]band = BAND_ON_5G\n"); + else + RF_DBG(rf, DBG_RF_IQK, "[IQK]band = BAND_ON_24G\n"); + + if (iqk_info->iqk_bw[path] == CHANNEL_WIDTH_20) + RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 20MHz\n"); + else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_40) + RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 40MHz\n"); + else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_80) + RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 80MHz\n"); + else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_160) + RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 160MHz\n"); + else + RF_DBG(rf, DBG_RF_IQK, "[IQK]!!!! Channle is not support !!!!\n"); +#endif + return; +} + +__iram_func__ +void halrf_iqk_reload_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 tmp; + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + iqk_info->reload_cnt++; + tmp = iqk_info->bp_iqkenable[path]; + halrf_wreg(rf, 0x8124 + (path << 8), MASKDWORD, tmp); + tmp = iqk_info->bp_txkresult[path]; + halrf_wreg(rf, 0x8138 + (path << 8), MASKDWORD, tmp); + tmp = iqk_info->bp_rxkresult[path]; + halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, tmp); + return; +} + +__iram_func__ +void iqk_start_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + _iqk_by_path_8852b(rf, phy_idx, path); + return; +} + +__iram_func__ +void iqk_restore_8852b(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool fail; + + halrf_wreg(rf, 0x8138 + (path << 8), MASKDWORD, iqk_info->nb_txcfir[path]); + halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, iqk_info->nb_rxcfir[path]); + halrf_wreg(rf, 0x8000, MASKDWORD, 0x00000e19 + (path << 4)); + halrf_delay_us(rf, 10); + fail = _iqk_check_cal_8852b(rf, path, 0x0); + + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000); + halrf_wreg(rf, 0x8120, 0x10000000, 0x0); + halrf_wreg(rf, 0x8220, 0x10000000, 0x0); + halrf_wreg(rf, 0x8220, 0x00010000, 0x0); + halrf_wrf(rf, path, 0xef, 0x00004, 0x0); + halrf_wrf(rf, path, 0xef, 0x00004, 0x0); + halrf_wrf(rf, path, 0x0, 0xf0000, 0x3); + halrf_wrf(rf, path, 0x5, 0x00001, 0x1); + halrf_wrf(rf, path, 0x10005, 0x00001, 0x1); + return; +} + +__iram_func__ +void iqk_afebb_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + u32 i = 0; + u32 array_len = 0x0; + u32 *array = NULL; + u32 addr = 0, mask = 0, val = 0; + + RF_DBG(rf, DBG_RF_IQK, "===> %s\n", __func__); + + switch(halrf_kpath_8852b(rf, phy_idx)) { + case RF_A: + break; + case RF_B: + break; + default: + array_len = sizeof(array_restore_nondbcc_path01_8852b) / sizeof(u32); + array = (u32 *) &array_restore_nondbcc_path01_8852b; + break; + } + + while ((i + 1) < array_len) { + addr = array[i]; + mask = array[i + 1]; + val = array[i + 2]; + halrf_wreg(rf, addr, mask, val); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, halrf_rreg(rf, addr, mask)); + i += 3; + } + return; +} + +__iram_func__ +void iqk_preset_8852b(struct rf_info *rf, u8 path) +{ + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + //03_IQK_Preset_Non_DBCC_PHY0_path01 + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 idx = 0; + + //ch = ((iqk_info->iqk_times /2) % 2) & 0x1; + + idx = iqk_info->iqk_table_idx[path]; + RF_DBG(rf, DBG_RF_IQK, "[IQK] (3) idx = %x\n", idx); + halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, idx); + halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, idx); + + halrf_wrf(rf, path, 0x5, 0x00001, 0x0); + halrf_wrf(rf, path, 0x10005, 0x00001, 0x0); + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080); + halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a); + RF_DBG(rf, DBG_RF_IQK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path, halrf_rreg(rf, 0x8154 + (path << 8), MASKDWORD)); + RF_DBG(rf, DBG_RF_IQK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path, halrf_rreg(rf, 0x8104 + (path << 8), MASKDWORD)); + + return; +} + +__iram_func__ +void iqk_macbb_setting_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + u32 i = 0; + u32 array_len = 0x0; + u32 *array = NULL; + u32 addr = 0, mask = 0, val = 0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__); + + switch(halrf_kpath_8852b(rf, phy_idx)) { + case RF_A: + break; + case RF_B: + break; + default: + array_len = sizeof(array_set_nondbcc_path01_8852b) / sizeof(u32); + array = (u32 *) &array_set_nondbcc_path01_8852b; + break; + } + + while ((i + 1) < array_len) { + addr = array[i]; + mask = array[i + 1]; + val = array[i + 2]; + halrf_wreg(rf, addr, mask, val); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, halrf_rreg(rf, addr, mask)); + i += 3; + } + return; +} + +__iram_func__ +void halrf_iqk_toneleakage_8852b(struct rf_info *rf, u8 path) +{ + iqk_macbb_setting_8852b(rf, HW_PHY_0, path); + iqk_preset_8852b(rf, path); + _iqk_txclk_setting_8852b(rf, path); + // main iqk single tone process + halrf_wrf(rf, path, 0x0, 0xf0000, 0x2); +#if 0 + switch (iqk_info->iqk_band[path]) { + case BAND_ON_24G: + halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0e); + break; + case BAND_ON_5G: + halrf_wrf(rf, path, 0x11, 0x00003, 0x0); + halrf_wrf(rf, path, 0x11, 0x00070, 0x6); + halrf_wrf(rf, path, 0x11, 0x1f000, 0x0e); + break; + default: + break; + } +#endif + halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a); + halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00300000); + halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0xce000a08); + halrf_wreg(rf, 0x8000, 0x00000006, path); + halrf_wrf(rf, path, 0x10001, 0x0003f, 0x3c); + halrf_wreg(rf, 0x8034, 0x00000030, 0x2); + halrf_wreg(rf, 0x8038, 0x00000100, 0x1); + halrf_wreg(rf, 0x8034, 0xff000000, 0x11); + halrf_wreg(rf, 0x5864, 0x20000000, 0x1); + halrf_wreg(rf, 0x8014, 0x10000000, 0x1); + halrf_wreg(rf, 0x8014, 0x10000000, 0x0); + halrf_delay_us(rf, 100); + halrf_wreg(rf, 0x5864, 0x20000000, 0x0); + halrf_wreg(rf, 0x8018, 0x70000000, 0x2); + halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x12); + halrf_wreg(rf, 0x802c, 0x00000fff, 0x009); + halrf_wreg(rf, 0x8034, 0x00000001, 0x1); + halrf_wreg(rf, 0x8034, 0x00000001, 0x0); + halrf_delay_us(rf, 1); + //halrf_wreg(rf, 0x8034, 0x00000030, 0x3); + //halrf_wreg(rf, 0x8038, 0x00000100, 0x0); + return; +} + +__iram_func__ +void halrf_iqk_dbcc_8852b(struct rf_info *rf, u8 path) +{ +#if 0 + bool bkdbcc = false; + u8 phy_idx = 0x0; + + bkdbcc = rf->hal_com->dbcc_en; + rf->hal_com->dbcc_en = true; + + if (path == 0x0) + phy_idx = HW_PHY_0; + else + phy_idx = HW_PHY_1; + + //iqk_mcc_page_sel_8852b(rf,phy_idx, path); + iqk_get_ch_info_8852b(rf,phy_idx, path); + iqk_macbb_setting_8852b(rf, phy_idx, path); + iqk_preset_8852b(rf, path); + iqk_start_iqk_8852b(rf, phy_idx, path); + iqk_restore_8852b(rf, path); + iqk_afebb_restore_8852b(rf, phy_idx, path); + rf->hal_com->dbcc_en = bkdbcc; +#endif + return; +} + +__iram_func__ +void halrf_iqk_onoff_8852b(struct rf_info *rf, bool is_enable) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (is_enable) { + halrf_wreg(rf, 0x8124, MASKDWORD, 0x00000505); /*ch0*/ + halrf_wreg(rf, 0x8224, MASKDWORD, 0x00000505); /*ch1*/ + iqk_info->is_iqk_enable = true; + } else { + halrf_wreg(rf, 0x8124, MASKDWORD, 0x00000000); /*ch0*/ + halrf_wreg(rf, 0x8224, MASKDWORD, 0x00000000); /*ch1*/ + iqk_info->is_iqk_enable = false; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK] IQK enable : %s !!!\n", + iqk_info->is_iqk_enable ? "enable" : "disable"); + return; +} + +__iram_func__ +void halrf_iqk_tx_bypass_8852b(struct rf_info *rf, u8 path) +{ + if (path == RF_PATH_A) { //path A + /*ch0*/ + halrf_wreg(rf, 0x8124, 0x00000f00, 0x0); + halrf_wreg(rf, 0x8138, MASKDWORD, 0x40000002); + } else { + /*ch1*/ + halrf_wreg(rf, 0x8224, 0x00000f00, 0x0); + halrf_wreg(rf, 0x8238, MASKDWORD, 0x40000002); + } + return; +} + +__iram_func__ +void halrf_iqk_rx_bypass_8852b(struct rf_info *rf, u8 path) +{ + if (path == RF_PATH_A) { //path A + /*ch0*/ + halrf_wreg(rf, 0x8124, 0x0000000f, 0x0); + halrf_wreg(rf, 0x813c, MASKDWORD, 0x40000002); + } else { + /*ch1*/ + halrf_wreg(rf, 0x8224, 0x0000000f, 0x0); + halrf_wreg(rf, 0x823c, MASKDWORD, 0x40000002); + } + return; +} + +__iram_func__ +void halrf_iqk_lok_bypass_8852b(struct rf_info *rf, u8 path) +{ + halrf_wrf(rf, path, 0xdf, 0x00004, 0x1); + halrf_wrf(rf, path, 0x58, MASKRF, 0x84220); + return; +} + +__iram_func__ +void halrf_nbiqk_enable_8852b(struct rf_info *rf, bool nbiqk_en) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (nbiqk_en) { + iqk_info->is_nbiqk = true; + } else { + iqk_info->is_nbiqk = false; + } + + return; +} + +__iram_func__ +void halrf_iqk_xym_enable_8852b(struct rf_info *rf, bool iqk_xym_en) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (iqk_xym_en) { + iqk_info->iqk_xym_en = true; + } else { + iqk_info->iqk_xym_en = false; + } + + return; +} + +__iram_func__ +void halrf_iqk_fft_enable_8852b(struct rf_info *rf, bool iqk_fft_en) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (iqk_fft_en) { + iqk_info->iqk_fft_en = true; + } else { + iqk_info->iqk_fft_en = false; + } + + return; +} + +__iram_func__ +void halrf_iqk_sram_enable_8852b(struct rf_info *rf, bool iqk_sram_en) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (iqk_sram_en) { + iqk_info->iqk_sram_en = true; + } else { + iqk_info->iqk_sram_en = false; + } + + return; +} + +__iram_func__ +void halrf_iqk_cfir_enable_8852b(struct rf_info *rf, bool iqk_cfir_en) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (iqk_cfir_en) { + iqk_info->iqk_cfir_en = true; + } else { + iqk_info->iqk_cfir_en = false; + } + return; +} + +__iram_func__ +void halrf_iqk_track_8852b( + struct rf_info *rf) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 path =0x0, i = 0x0; + u8 cur_ther = 0x0, ther_avg_cnt = 0; + u32 ther_avg[2] = {0}; + + /*only check path 0 */ + for (path = 0; path < 1; path++) { + cur_ther = halrf_get_thermal_8852b(rf, path); + iqk_info->ther_avg[path][iqk_info->ther_avg_idx] = cur_ther; + /*Average times */ + ther_avg_cnt = 0; + for (i = 0; i < 0x4; i++) { + if (iqk_info->ther_avg[path][i]) { + ther_avg[path] += iqk_info->ther_avg[path][i]; + ther_avg_cnt++; +#if 0 + RF_DBG(rf, DBG_RF_IQK, + "[IQK] thermal avg[%d] = %d\n", i, + iqk_info->ther_avg[path][i]); +#endif + } + } + /*Calculate Average ThermalValue after average enough times*/ + if (ther_avg_cnt) { + cur_ther = (u8)(ther_avg[path] / ther_avg_cnt); + } + if (HALRF_ABS(cur_ther, iqk_info->thermal[path] ) > IQK_THR_ReK) { + iqk_info->thermal_rek_en = true; + } + else { + iqk_info->thermal_rek_en = false; + } + //RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, iqk_ther =%d, ther_now = %d\n", path, iqk->thermal[path], cur_ther); + } + iqk_info->ther_avg_idx++; + if (iqk_info->ther_avg_idx == 0x4) + iqk_info->ther_avg_idx = 0; + return; +} + +__iram_func__ +bool halrf_iqk_get_ther_rek_8852b(struct rf_info *rf ) { + struct halrf_iqk_info *iqk_info = &rf->iqk; + + return iqk_info->thermal_rek_en; +} + +__iram_func__ +u8 halrf_iqk_get_mcc_ch0_8852b(struct rf_info *rf ) { + + struct halrf_iqk_info *iqk_info = &rf->iqk; + + return iqk_info->iqk_mcc_ch[0][0]; +} + +__iram_func__ +u8 halrf_iqk_get_mcc_ch1_8852b(struct rf_info *rf ) { + + struct halrf_iqk_info *iqk_info = &rf->iqk; + + return iqk_info->iqk_mcc_ch[1][0]; +} + +__iram_func__ +bool halrf_check_fwiqk_done_8852b(struct rf_info *rf) +{ + u32 counter = 0x0; + bool flag = false; + bool isfail = false; +#if 1 + while (1) { + if (halrf_rreg(rf, 0xbff8, MASKBYTE0) == 0xaa || counter > 3000) { + if(halrf_rreg(rf, 0x8010, MASKBYTE0) == 0xaa) { + flag = true; + break; + } + } + counter++; + halrf_delay_us(rf, 10); + }; +#else + for(counter = 0; counter < 6000; counter++) + halrf_delay_us(rf, 10); +#endif + if (counter < 10) + isfail = true; + else + isfail = false; + + if(flag) { + RF_DBG(rf, DBG_RF_IQK, "[IQK] Load FW Done, counter = %d!!\n", counter); + } else { + RF_DBG(rf, DBG_RF_IQK, "[IQK] Load FW Fail, counter = %d!!\n", counter); + halrf_iqk_tx_bypass_8852b(rf, RF_PATH_A); + halrf_iqk_tx_bypass_8852b(rf, RF_PATH_B); + halrf_iqk_rx_bypass_8852b(rf, RF_PATH_A); + halrf_iqk_rx_bypass_8852b(rf, RF_PATH_B); + halrf_iqk_lok_bypass_8852b(rf, RF_PATH_A); + halrf_iqk_lok_bypass_8852b(rf, RF_PATH_B); + } + halrf_wreg(rf, 0x8010, 0x000000ff,0x0); + return isfail; +} + +__iram_func__ +void halrf_enable_fw_iqk_8852b(struct rf_info *rf, bool is_fw_iqk) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + if (is_fw_iqk) { + iqk_info->is_fw_iqk = true; + } else { + iqk_info->is_fw_iqk = false; + } + return; +} + +__iram_func__ +u8 halrf_get_iqk_times_8852b(struct rf_info *rf) { + u8 times = 0x0; + + times = (u8) halrf_rreg(rf, 0x9fe8, 0x0000ff00); + return times; +} + +__iram_func__ +u32 halrf_get_iqk_ver_8852b(void) +{ + return iqk_version_8852b; +} + +__iram_func__ +void iqk_init_8852b(struct rf_info *rf) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 idx, path; + halrf_wreg(rf, 0x9fe0, MASKDWORD, 0x0); + if (!iqk_info->is_iqk_init) { + RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + iqk_info->is_iqk_init = true; + iqk_info->is_nbiqk = false; + iqk_info->iqk_fft_en = false; + iqk_info->iqk_sram_en = false; + iqk_info->iqk_cfir_en = false; + iqk_info->iqk_xym_en = false; + iqk_info->thermal_rek_en = false; + iqk_info->ther_avg_idx = 0x0; + iqk_info->iqk_times = 0x0; + /*channel/path/TRX(TX:0, RX:1) */ + iqk_info->iqk_times = 0x0; + iqk_info->is_fw_iqk = false; + for (idx = 0; idx < 2; idx++) { //channel + iqk_info->iqk_channel[idx] = 0x0; + for (path = 0; path < ss_8852b; path++) {//path + iqk_info->lok_cor_fail[idx][path] = false; + iqk_info->lok_fin_fail[idx][path] = false; + iqk_info->iqk_tx_fail[idx][path] = false; + iqk_info->iqk_rx_fail[idx][path] = false; + iqk_info->iqk_mcc_ch[idx][path] = 0x0; + iqk_info->iqk_table_idx[path] = 0x0; + } + } + } + return; +} +u8 halrf_iqk_get_rxevm_8852b(struct rf_info *rf) +{ + u8 rxevm =0x0; +#if 1 + halrf_wreg(rf, 0x738, 0x00000010, 0x1); + halrf_wreg(rf, 0x738, 0x000000c0, 0x1); + halrf_wreg(rf, 0x738, 0x70000000, 0x2); + halrf_wreg(rf, 0x738, 0x00000020, 0x0); + halrf_delay_us(rf, 100); + halrf_wreg(rf, 0x20f4, 0x01000000, 0x0); + halrf_wreg(rf, 0x20f8, 0x80000000, 0x1); + halrf_wreg(rf, 0x20f0, 0x00ff0000, 0x1); + halrf_wreg(rf, 0x20f0, 0x00000f00, 0x7); + halrf_wreg(rf, 0x20f0, 0x000000ff, 0x0); + halrf_wreg(rf, 0x738, 0x00000020, 0x1); + halrf_wreg(rf, 0x738, 0x0000ff00, 0x5); + rxevm = (u8) (halrf_rreg(rf, 0x1af0, 0x00ff0000) /4) ; +#else + rxevm = rtw_hal_bb_get_rxevm_single_user(rf->hal_com, HW_PHY_0, 0, 1); +#endif + return rxevm; +} + +u32 halrf_iqk_get_rximr_8852b(struct rf_info *rf, u8 path, u32 idx) +{ + u32 rximr =0x0; + u32 tone_idx = 0x0; + u32 main_idx = 0x0; + u32 rf0 = 0x0; + u32 pwr_sig = 0x0, pwr_img = 0x0; + u32 reg_0x800c = 0x0, reg_0x8018 = 0x0, reg_0x801c = 0x0, reg_0x81cc = 0x0, reg_0x82cc = 0x0; + + reg_0x800c = halrf_rreg(rf, 0x800c, MASKDWORD); + reg_0x8018 = halrf_rreg(rf, 0x8018, MASKDWORD); + reg_0x801c = halrf_rreg(rf, 0x801c, MASKDWORD); + reg_0x81cc = halrf_rreg(rf, 0x81cc, MASKDWORD); + reg_0x82cc = halrf_rreg(rf, 0x82cc, MASKDWORD); + + //tone_idx = idx * 320MHz/80MHz + if (idx <100) { + tone_idx = idx * 4 * 2; + main_idx = tone_idx & 0xfff; + } else { + tone_idx = (idx -100) *4 * 2; + main_idx = (0x1000-tone_idx) & 0xfff; + } + RF_DBG(rf, DBG_RF_IQK, "[IQK][IMR]S%x, idx = 0x%x, tone_idx = 0x%x, main_idx = 0x%x\n", path, idx, tone_idx, main_idx); + + iqk_macbb_setting_8852b(rf, HW_PHY_0, path); + + iqk_preset_8852b(rf, path); + _iqk_rxclk_setting_8852b(rf, path); + halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff0109); + halrf_wreg(rf, 0x8000, 0x00000006, path); + halrf_wreg(rf, 0x800c, MASKDWORD, 0x00000c00); + halrf_wreg(rf, 0x8018, 0x70000000, 0x4); + halrf_wreg(rf, 0x801c, 0x000e0000, 0x0); + halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00300000); + halrf_wreg(rf, 0x81cc + (path << 8), 0x0000003f, 0x3f); + halrf_wreg(rf, 0x8140 + (path << 8), 0x00000100, 0x1); + rf0 = halrf_rrf(rf, path, 0x00, 0x03800); + halrf_wreg(rf, 0x8144 + (path << 8), 0x00070000, rf0); + rf0 = halrf_rrf(rf, path, 0x00, 0x003e0); + halrf_wreg(rf, 0x8144 + (path << 8), 0x1f000000, rf0); + halrf_wreg(rf, 0x81dc + (path << 8), MASKDWORD, 0x00000001); + halrf_wreg(rf, 0x81dc + (path << 8), MASKDWORD, 0x00000000); + + halrf_wreg(rf, 0x802c, 0x0fff0000, main_idx); + halrf_wreg(rf, 0x8034, 0x00000001, 0x1); + halrf_wreg(rf, 0x8034, 0x00000001, 0x0); + halrf_delay_us(rf, 100); + + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002d0000); + pwr_sig = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002e0000); + pwr_sig = (pwr_sig << 25) + (halrf_rreg(rf, 0x80fc, MASKDWORD) >> 7); + + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002d0000); + pwr_img = halrf_rreg(rf, 0x80fc, 0x0000007f); + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002f0000); + pwr_img = (pwr_img << 25) + (halrf_rreg(rf, 0x80fc, MASKDWORD) >> 7); + + rximr = (u32) (pwr_sig / pwr_img); + RF_DBG(rf, DBG_RF_IQK, "[IQK][IMR]S%x, %x, %d,%d, %d\n", path, halrf_rrf(rf, path, 0x0, MASKRF),pwr_sig, pwr_img, rximr); + + halrf_wreg(rf, 0x800c, MASKDWORD, reg_0x800c); + halrf_wreg(rf, 0x8018, MASKDWORD, reg_0x8018); + halrf_wreg(rf, 0x801c, MASKDWORD, reg_0x801c); + halrf_wreg(rf, 0x81cc, MASKDWORD, reg_0x81cc); + halrf_wreg(rf, 0x82cc, MASKDWORD, reg_0x82cc); + + return rximr; +} + +#if 0 +__iram_func__ +void halrf_doiqk_8852b(struct rf_info *rf, bool force, enum phl_phy_idx phy_idx, u8 path) +{ + + + u32 backup_mac[2] = {0x0}; + u32 backup_bb[2] = {0x0}; + u32 backup_rf0[6] = {0x0}; + u32 backup_rf1[6] = {0x0}; + u32 backup_mac_reg[1] = {0x0}; + u32 backup_bb_reg[1] = {0x2344}; + u32 backup_rf_reg0[6] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x5}; + u32 backup_rf_reg1[6] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x5}; + + struct halrf_iqk_info *iqk_info = &rf->iqk; + + //halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START); + RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK strat!!!!!==========\n"); + iqk_info->version = iqk_version_8852b; + iqk_info->iqk_step = 0; + iqk_info->rxiqk_step = 0; + iqk_info->reload_cnt = 0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", iqk_version); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", 0x2); + //u32 addr = 0x0; + //for (addr = 0x8000; addr < 0x8300; addr += 0x4) + // RF_DBG(rf, DBG_RF_IQK, "[IQK] %8x, %8x \n", addr, halrf_rreg(rf, addr + 0x4, MASKDWORD)); + + if (iqk_mcc_page_sel_8852b(rf,phy_idx, path)) + return; + iqk_get_ch_info_8852b(rf,phy_idx, path); + iqk_backup_mac_bb_8852b(rf, path, backup_mac, backup_bb, backup_mac_reg, backup_bb_reg); + iqk_backup_rf0_8852b(rf, path, backup_rf0, backup_rf_reg0); + iqk_backup_rf1_8852b(rf, path, backup_rf1, backup_rf_reg1); + iqk_macbb_setting_8852b(rf, phy_idx, path); + iqk_preset_8852b(rf, path); + iqk_start_iqk_8852b(rf, phy_idx, path); + iqk_restore_8852b(rf, path); + iqk_afebb_restore_8852b(rf, phy_idx, path); + iqk_restore_mac_bb_8852b(rf, path, backup_mac, backup_bb, backup_mac_reg, backup_bb_reg); + iqk_restore_rf0_8852b(rf, path, backup_rf0, backup_rf_reg0); + iqk_restore_rf1_8852b(rf, path, backup_rf1, backup_rf_reg1); + iqk_info->iqk_times++; + //halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP); + RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK End!!!!!==========\n"); + return; +} + +__iram_func__ +void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) +{ + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + iqk_init_8852b(rf); + switch(halrf_kpath_8852b(rf, phy_idx)) { + case RF_A: + halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_A); + break; + case RF_B: + halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_B); + break; + case RF_AB: + halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_A); + halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_B); + break; + default: + break; + } + return; +} +#endif + +#endif + + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.h new file mode 100644 index 0000000..2b677c1 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.h @@ -0,0 +1,106 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_IQK_8852BH__ +#define __HALRF_IQK_8852BH__ +#ifdef RF_8852B_SUPPORT + +#define iqk_version_8852b 0xc +#define ss_8852b 2 +#define mac_reg_num_8852b 2 +#define bb_reg_num_8852b 1 +#define rf_reg_num_8852b 6 +#define iqk_delay_8852b 1 +#define iqk_step_8852b 2 +#define rxk_step_8852b 4 +#define path_baseaddr 0x8 +#define txagck 0 +#define lok 1 +#define txk 2 +#define rxk 3 +#define IQK_THR_ReK 8 + + +void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force); + +//cv b +void iqk_init_8852b(struct rf_info *rf); +void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force); +void halrf_doiqk_8852b(struct rf_info *rf, bool force, + enum phl_phy_idx phy_idx, u8 path); +void iqk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path); +bool iqk_mcc_page_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path); +void iqk_macbb_setting_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); +void iqk_preset_8852b(struct rf_info *rf, u8 path); +void iqk_start_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path); +void iqk_restore_8852b(struct rf_info *rf, u8 path); +void iqk_afebb_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); +void halrf_iqk_reload_8852b(struct rf_info *rf, u8 path); +void halrf_nbiqk_enable_8852b(struct rf_info *rf, bool nbiqk_en); +void halrf_iqk_toneleakage_8852b(struct rf_info *rf, u8 path); +void halrf_iqk_sram_enable_8852b(struct rf_info *rf, bool iqk_sram_en); +void halrf_iqk_xym_enable_8852b(struct rf_info *rf, bool iqk_xym_en); +void halrf_iqk_fft_enable_8852b(struct rf_info *rf, bool iqk_fft_en); +void halrf_iqk_cfir_enable_8852b(struct rf_info *rf, bool iqk_cfir_en); +void halrf_iqk_onoff_8852b(struct rf_info *rf, bool is_enable); +void halrf_iqk_lok_bypass_8852b(struct rf_info *rf, u8 path); +void halrf_iqk_rx_bypass_8852b(struct rf_info *rf, u8 path); +void halrf_iqk_tx_bypass_8852b(struct rf_info *rf, u8 path); + +void iqk_backup_mac_bb_8852b(struct rf_info *rf, u8 path, + u32 backup_mac[mac_reg_num_8852b], + u32 backup_bb[bb_reg_num_8852b], + u32 backup_mac_reg[mac_reg_num_8852b], + u32 backup_bb_reg[bb_reg_num_8852b]); +void iqk_backup_rf_8852b(struct rf_info *rf, u8 path, + u32 backup_rf[][rf_reg_num_8852b], + u32 backup_rf_reg[][rf_reg_num_8852b]); +void iqk_restore_mac_bb_8852b(struct rf_info *rf, u8 path, + u32 backup_mac[mac_reg_num_8852b], + u32 backup_bb[bb_reg_num_8852b], + u32 backup_mac_reg[mac_reg_num_8852b], + u32 backup_bb_reg[bb_reg_num_8852b]); +void iqk_restore_rf_8852b(struct rf_info *rf, u8 path, + u32 backup_rf[][rf_reg_num_8852b], + u32 backup_rf_reg[][rf_reg_num_8852b]); + +void halrf_iqk_track_8852b(struct rf_info *rf); + +bool halrf_iqk_get_ther_rek_8852b(struct rf_info *rf ); +void halrf_iqk_dbcc_8852b(struct rf_info *rf, u8 path); +u8 halrf_iqk_get_mcc_ch0_8852b(struct rf_info *rf ); +u8 halrf_iqk_get_mcc_ch1_8852b(struct rf_info *rf ); +bool halrf_check_fwiqk_done_8852b(struct rf_info *rf); +void iqk_set_info_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); +void halrf_enable_fw_iqk_8852b(struct rf_info *rf, bool is_fw_iqk); +u8 halrf_get_iqk_times_8852b(struct rf_info *rf) ; +u32 halrf_get_iqk_ver_8852b(void); +u8 halrf_iqk_get_rxevm_8852b(struct rf_info *rf); +u32 halrf_iqk_get_rximr_8852b(struct rf_info *rf, u8 path, u32 idx); + + +#endif +#endif /* __HALRF_IQK_8852BH__ */ + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.c new file mode 100644 index 0000000..42b7969 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.c @@ -0,0 +1,228 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +void _halrf_get_total_efuse_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_kfree_info *kfree = &rf->kfree_info; + u8 i; + + halrf_phy_efuse_get_info(rf, HIDE_EFUSE_START_ADDR_8852B, + HIDE_EFUSE_SIZE_8852B, kfree->efuse_content); + + for (i = 0; i < HIDE_EFUSE_SIZE_8852B; i++) + RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s efuse_con[0x%x] = 0x%x\n", + __func__, i + HIDE_EFUSE_START_ADDR_8852B, kfree->efuse_content[i]); +} + +void _halrf_get_1byte_efuse_8852b(struct rf_info *rf, u32 addr, u8 *value) +{ + struct halrf_kfree_info *kfree = &rf->kfree_info; + + if (addr < HIDE_EFUSE_START_ADDR_8852B || addr > HIDE_EFUSE_END_ADDR_8852B) { + RF_DBG(rf, DBG_RF_TSSI_TRIM, "===> %s addr(0x%x) < 0x%x(Min), > 0x%x(Max) Over Range Return !!!\n", + __func__, addr, HIDE_EFUSE_START_ADDR_8852B, HIDE_EFUSE_END_ADDR_8852B); + return; + } + + *value = kfree->efuse_content[addr - HIDE_EFUSE_START_ADDR_8852B]; +} + +s8 _halrf_efuse_exchange_8852b(struct rf_info *rf, u8 value, u8 mask) +{ + s8 tmp = 0; + + if (mask == LOW_MASK) { + tmp = value & 0xf; + + if (tmp & BIT(3)) + tmp = tmp | 0xf0; + } else { + tmp = (value & 0xf0) >> 4; + + if (tmp & BIT(3)) + tmp = tmp | 0xf0; + } + + return tmp; +} + +void _halrf_set_thermal_trim_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 thermal_a, thermal_b; + + RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s phy=%d\n", __func__, phy); + + if (!(rf->support_ability & HAL_RF_THER_TRIM)) { + RF_DBG(rf, DBG_RF_THER_TRIM, "<== %s phy=%d support_ability=%d Ther Trim Off!!!\n", + __func__, phy, rf->support_ability); + return; + } + + _halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852B, &thermal_a); + + _halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852B, &thermal_b); + + RF_DBG(rf, DBG_RF_THER_TRIM, "efuse Ther_A=0x%x Ther_B=0x%x\n", + thermal_a, thermal_b); + + if (thermal_a == 0xff && thermal_b == 0xff) { + RF_DBG(rf, DBG_RF_THER_TRIM, "Ther_A, Ther_B=0xff no PG Return!!!\n"); + return; + } + + thermal_a = thermal_a & 0x1f; + thermal_a = ((thermal_a & 0x1) << 3) | (thermal_a >> 1); + + thermal_b = thermal_b & 0x1f; + thermal_b = ((thermal_b & 0x1) << 3) | (thermal_b >> 1); + + RF_DBG(rf, DBG_RF_THER_TRIM, "After Exchange Ther_A=0x%x Ther_B=0x%x\n", + thermal_a, thermal_b); + + halrf_wrf(rf, RF_PATH_A, 0x43, 0x000f0000, thermal_a); + halrf_wrf(rf, RF_PATH_B, 0x43, 0x000f0000, thermal_b); +} + +void _halrf_set_pa_bias_trim_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 pa_bias_a, pa_bias_b; + u8 pa_bias_a_2g, pa_bias_b_2g, pa_bias_a_5g, pa_bias_b_5g; + + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "======> %s phy=%d\n", __func__, phy); + + if (!(rf->support_ability & HAL_RF_PABIAS_TRIM)) { + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "<== %s phy=%d support_ability=%d PA Bias K Off!!!\n", + __func__, phy, rf->support_ability); + return; + } + + _halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852B, &pa_bias_a); + + _halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852B, &pa_bias_b); + + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "efuse PA_Bias_A=0x%x PA_Bias_B=0x%x\n", + pa_bias_a, pa_bias_b); + + if (pa_bias_a == 0xff && pa_bias_b == 0xff) { + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "PA_Bias_A, PA_Bias_B=0xff no PG Return!!!\n"); + return; + } + + pa_bias_a_2g = pa_bias_a & 0xf; + pa_bias_a_5g = (pa_bias_a & 0xf0) >> 4; + + pa_bias_b_2g = pa_bias_b & 0xf; + pa_bias_b_5g = (pa_bias_b & 0xf0) >> 4; + + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_A_2G=0x%x PA_Bias_A_5G=0x%x\n", + pa_bias_a_2g, pa_bias_a_5g); + + RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_B_2G=0x%x PA_Bias_B_5G=0x%x\n", + pa_bias_b_2g, pa_bias_b_5g); + + halrf_wrf(rf, RF_PATH_A, 0x60, 0x0000f000, pa_bias_a_2g); + halrf_wrf(rf, RF_PATH_A, 0x60, 0x000f0000, pa_bias_a_5g); + + halrf_wrf(rf, RF_PATH_B, 0x60, 0x0000f000, pa_bias_b_2g); + halrf_wrf(rf, RF_PATH_B, 0x60, 0x000f0000, pa_bias_b_5g); +} + +void _halrf_get_tssi_trim_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi = &rf->tssi; + u8 i, j , check_tmp = 0; + + RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s phy=%d\n", __func__, phy); + + if (!(rf->support_ability & HAL_RF_TSSI_TRIM)) { + RF_DBG(rf, DBG_RF_TSSI_TRIM, "<== %s phy=%d support_ability=%d TSSI Trim Off!!!\n", + __func__, phy, rf->support_ability); + return; + } + + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][0]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][1]); + + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][2]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][3]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][4]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][5]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][6]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_A][7]); + + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][0]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][1]); + + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][2]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][3]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][4]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][5]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][6]); + _halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B, + (u8 *)&tssi->tssi_trim[RF_PATH_B][7]); + + for (i = 0; i < 2; i++) { + for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++) { + RF_DBG(rf, DBG_RF_TSSI_TRIM, "tssi->tssi_trim[%d][%d]=0x%x\n", i, j, tssi->tssi_trim[i][j]); + if ((tssi->tssi_trim[i][j] & 0xff) == 0xff) + check_tmp++; + } + } + + RF_DBG(rf, DBG_RF_TSSI_TRIM, "check_tmp=%d\n", check_tmp); + + if (check_tmp == 2 * TSSI_HIDE_EFUSE_NUM) { + for (i = 0; i < 2; i++) { + for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++) + tssi->tssi_trim[i][j] = 0; + } + + RF_DBG(rf, DBG_RF_TSSI_TRIM, "TSSI Trim no PG tssi->tssi_trim=0x0\n"); + } + +} + +void halrf_get_efuse_trim_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + _halrf_get_total_efuse_8852b(rf, phy); + _halrf_set_thermal_trim_8852b(rf, phy); + _halrf_set_pa_bias_trim_8852b(rf, phy); + _halrf_get_tssi_trim_8852b(rf, phy); +} + +#endif /*RF_8852B_SUPPORT*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.h new file mode 100644 index 0000000..0e08c15 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_KFREE_8852B_H_ +#define _HALRF_KFREE_8852B_H_ +#ifdef RF_8852B_SUPPORT + +/*@--------------------------Define Parameters-------------------------------*/ + +#define HIDE_EFUSE_START_ADDR_8852B 0x5A0 +#define HIDE_EFUSE_END_ADDR_8852B 0x5F0 +#define HIDE_EFUSE_SIZE_8852B HIDE_EFUSE_END_ADDR_8852B - HIDE_EFUSE_START_ADDR_8852B + +#define THERMAL_TRIM_HIDE_EFUSE_A_8852B 0x5DF +#define THERMAL_TRIM_HIDE_EFUSE_B_8852B 0x5DC + +#define PABIAS_TRIM_HIDE_EFUSE_A_8852B 0x5DE +#define PABIAS_TRIM_HIDE_EFUSE_B_8852B 0x5DB + +#define TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B 0x5D6 +#define TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B 0x5D5 +#define TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B 0x5D4 +#define TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B 0x5D3 +#define TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B 0x5D2 +#define TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B 0x5D1 +#define TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B 0x5D0 +#define TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B 0x5CF + +#define TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B 0x5AB +#define TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B 0x5AA +#define TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B 0x5A9 +#define TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B 0x5A8 +#define TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B 0x5A7 +#define TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B 0x5A6 +#define TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B 0x5A5 +#define TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B 0x5A4 + +/*@-----------------------End Define Parameters-----------------------*/ + +void halrf_get_efuse_trim_8852b(struct rf_info *rf, + enum phl_phy_idx phy); + +#endif +#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.c new file mode 100644 index 0000000..9082c9a --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.c @@ -0,0 +1,328 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +void _halrf_psd_backup_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD); + + RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", + reg[i], reg_backup[i]); + } +} + +void _halrf_psd_reload_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) + +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]); + + RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", + reg[i], reg_backup[i]); + } +} + +void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u8 path, u8 iq_path, u32 avg, u32 fft) +{ + struct halrf_psd_data *psd_info = &rf->psd; + u32 bb_reg[PSD_BACKUP_NUM_8852B] = { + 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, + 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, + 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, + 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, + 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, + 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, + 0x8220, 0x8018, 0x8000, 0x800c, 0x81cc, + 0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc, + 0x801c}; + + RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy); + + psd_info->psd_progress = 1; + + _halrf_psd_backup_bb_registers_8852b(rf, phy, bb_reg, + psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B); + + psd_info->path = path; + psd_info->iq_path = iq_path; + psd_info->avg = avg; + psd_info->fft = fft; + + /*02_BB_AFE_PHY0*/ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303); + halrf_wreg(rf, 0x5864, 0x18000000, 0x3); + halrf_wreg(rf, 0x7864, 0x18000000, 0x3); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + halrf_wreg(rf, 0x12b8, 0x10000000, 0x1); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1); + halrf_wreg(rf, 0x0700, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff); + halrf_wreg(rf, 0x0c60, 0x00000003, 0x3); + halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1); + halrf_wreg(rf, 0x58ac, 0x08000000, 0x1); + halrf_wreg(rf, 0x78ac, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1); + halrf_wreg(rf, 0x2320, 0x00000001, 0x1); + halrf_wreg(rf, 0x4490, 0x80000000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00007000, 0x7); + halrf_wreg(rf, 0x12a0, 0x00008000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x2); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x3333); + /*03_IQK_Preset_Non_DBCC_PHY0*/ + halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0); + halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0); + halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000080); + halrf_wreg(rf, 0x8080, 0xffffffff, 0x00000000); + halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff010a); + halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00200000); + halrf_wreg(rf, 0x8074, 0xffffffff, 0x80000000); + halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000000); + halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000000); + + /*07_CLK_Setting_RxIQK_BW80M_Non_DBCC_PHY0*/ + halrf_wreg(rf, 0x8120, 0xffffffff, 0x4d000a08); + halrf_wreg(rf, 0x8220, 0xffffffff, 0x4d000a08); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x2); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x2); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x1); + + /*windowing*/ + halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080); + + if (fft == 160) + halrf_wreg(rf, 0x801c, 0x00003000, 0x0); + else if (fft == 320) + halrf_wreg(rf, 0x801c, 0x00003000, 0x1); + else if (fft == 640) + halrf_wreg(rf, 0x801c, 0x00003000, 0x2); + else /*1280*/ + halrf_wreg(rf, 0x801c, 0x00003000, 0x3); + + if (avg == 1) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x0); + else if (avg == 2) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x1); + else if (avg == 4) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x2); + else if (avg == 8) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x3); + else if (avg == 16) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x4); + else if (avg == 64) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x6); + else if (avg == 128) + halrf_wreg(rf, 0x801c, 0x000e0000, 0x7); + else /*32*/ + halrf_wreg(rf, 0x801c, 0x000e0000, 0x5); + +} + +void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct halrf_psd_data *psd_info = &rf->psd; + u32 bb_reg[PSD_BACKUP_NUM_8852B] = { + 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, + 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, + 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, + 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, + 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, + 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, + 0x8220, 0x8018, 0x8000, 0x800c, 0x81cc, + 0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc, + 0x801c}; + + RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy); + + _halrf_psd_reload_bb_registers_8852b(rf, phy, bb_reg, + psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B); + + halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x1); + halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x1); + + psd_info->psd_progress = 0; + +#if 0 + /*98_IQK_Reg_Non_DBCC_PHY0_path01_Restore*/ + halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000000); + halrf_wreg(rf, 0x8074, 0xffffffff, 0x00000000); + halrf_wreg(rf, 0x8088, 0xffffffff, 0x80000000); + halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00000000); + halrf_wreg(rf, 0x80e0, 0x00000001, 0x0); + halrf_wreg(rf, 0x8120, 0xffffffff, 0x10010000); + halrf_wreg(rf, 0x8140, 0x00000100, 0x0); + halrf_wreg(rf, 0x8150, 0xffffffff, 0xe4e4e4e4); + halrf_wreg(rf, 0x8154, 0x00000100, 0x0); + halrf_wreg(rf, 0x81cc, 0x0000003f, 0x0); + halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000002); + halrf_wreg(rf, 0x8220, 0xffffffff, 0x10010000); + halrf_wreg(rf, 0x8240, 0x00000100, 0x0); + halrf_wreg(rf, 0x8250, 0xffffffff, 0xe4e4e4e4); + halrf_wreg(rf, 0x8254, 0x00000100, 0x0); + halrf_wreg(rf, 0x82cc, 0x0000003f, 0x0); + halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000002); + + /*99_BB_AFE_Non_DBCC_PHY0_path01_restore*/ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0); + halrf_wreg(rf, 0x0700, 0x08000000, 0x0); + halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03); + halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03); + halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x0700, 0x07000000, 0x0); + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); + halrf_wreg(rf, 0x2320, 0x00000001, 0x0); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x0); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x0); +#endif +} + +u32 halrf_psd_get_point_data_8852b(struct rf_info *rf, + enum phl_phy_idx phy, s32 point) +{ + struct halrf_psd_data *psd_info = &rf->psd; + u32 val_tmp, val, data; + + halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff0109); + + if (psd_info->path == RF_PATH_A) + halrf_wreg(rf, 0x8000, 0xffffffff, 0x00000008); + else + halrf_wreg(rf, 0x8000, 0xffffffff, 0x0000000a); + + halrf_wreg(rf, 0x800c, 0xffffffff, 0x00000c00); + halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080); + halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00300000); + + if (psd_info->path == RF_PATH_A) + halrf_wreg(rf, 0x81cc, 0x0000003f, 0x3f); + else + halrf_wreg(rf, 0x82cc, 0x0000003f, 0x3f); + + halrf_wreg(rf, 0x802c, 0x0fff0000, (point & 0xfff)); + halrf_wreg(rf, 0x8034, 0x00000001, 0x1); + halrf_wreg(rf, 0x8034, 0x00000001, 0x0); + halrf_delay_ms(rf, 1); + + halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002d0000); + val_tmp = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002e0000); + val = halrf_rreg(rf, 0x80fc, 0xffffffff); + + data = (val_tmp << 25) | (val >> 7); + + RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=0x%x data=0x%08x\n", + __func__, phy, point, data); + + return data; +} + +void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf) +{ + struct halrf_psd_data *psd_info = &rf->psd; + struct rtw_hal_com_t *hal = rf->hal_com; + u32 i = 0, j = 0; + s32 point_temp; + + RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=%d start_point=%d stop_point=%d\n", + __func__, phy, point, start_point, stop_point); + + if (psd_info->psd_result_running == true) { + RF_DBG(rf, DBG_RF_PSD, "======> %s PSD Running Return !!!\n", __func__); + return; + } + + psd_info->psd_result_running = true; + + hal_mem_set(hal, psd_info->psd_data, 0, sizeof(psd_info->psd_data)); + + i = start_point; + while (i < stop_point) { + if (i >= point) + point_temp = i - point; + else + { + point_temp = i - point; + point_temp = point_temp & 0xfff; + } + + psd_info->psd_data[j] = halrf_psd_get_point_data_8852b(rf, phy, point_temp); + + i++; + j++; + } + + RF_DBG(rf, DBG_RF_PSD, "psd_info->psd_data\n"); + + for (i = 0; i < 320; i = i + 10) { + RF_DBG(rf, DBG_RF_PSD, "%d %d %d %d %d %d %d %d %d %d\n", + psd_info->psd_data[i], psd_info->psd_data[i + 1], + psd_info->psd_data[i + 2], psd_info->psd_data[i + 3], + psd_info->psd_data[i + 4], psd_info->psd_data[i + 5], + psd_info->psd_data[i + 6], psd_info->psd_data[i + 7], + psd_info->psd_data[i + 8], psd_info->psd_data[i + 9]); + } + + hal_mem_cpy(hal, outbuf, psd_info->psd_data, + sizeof(psd_info->psd_data)); + + RF_DBG(rf, DBG_RF_PSD, "======> %s PSD End !!!\n", __func__); + + psd_info->psd_result_running = false; + +} + +#endif /*RF_8852B_SUPPORT*/ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.h new file mode 100644 index 0000000..b490b70 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_PSD_TSSI_8852B_H_ +#define _HALRF_PSD_TSSI_8852B_H_ + +#ifdef RF_8852B_SUPPORT + +#define PSD_VER_8852B 0x1 +#define PSD_BACKUP_NUM_8852B 41 + +/*@--------------------------Define Parameters-------------------------------*/ +/*@-----------------------End Define Parameters-----------------------*/ + +void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u8 path, u8 iq_path, u32 avg, u32 fft); + +void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy); + +u32 halrf_psd_get_point_data_8852b(struct rf_info *rf, + enum phl_phy_idx phy, s32 point); + +void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf); + +#endif /*RF_8852B_SUPPORT*/ +#endif /*_HALRF_PSD_TSSI_8852B_H_*/ + diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.c new file mode 100644 index 0000000..a670c5d --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.c @@ -0,0 +1,94 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT + +void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data) +{ +/*laod radio a table*/ + if (addr == 0xfe) + halrf_delay_ms(rf, 50); + else if (addr == 0xfd) + halrf_delay_ms(rf, 5); + else if (addr == 0xfc) + halrf_delay_ms(rf, 1); + else if (addr == 0xfb) + halrf_delay_us(rf, 50); + else if (addr == 0xfa) + halrf_delay_us(rf, 5); + else if (addr == 0xf9) + halrf_delay_us(rf, 1); + else + halrf_wrf(rf, RF_PATH_A, addr, MASKRF, data); + + RF_DBG(rf, DBG_RF_INIT, "[RF_a] %08X %08X\n", addr, data); + +} + +void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data) +{ +/*laod radio b table*/ + if (addr == 0xfe) + halrf_delay_ms(rf, 50); + else if (addr == 0xfd) + halrf_delay_ms(rf, 5); + else if (addr == 0xfc) + halrf_delay_ms(rf, 1); + else if (addr == 0xfb) + halrf_delay_us(rf, 50); + else if (addr == 0xfa) + halrf_delay_us(rf, 5); + else if (addr == 0xf9) + halrf_delay_us(rf, 1); + else + halrf_wrf(rf, RF_PATH_B, addr, MASKRF, data); + + RF_DBG(rf, DBG_RF_INIT, "[RF_b] %08X %08X\n", addr, data); + +} + +void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data) +{ +/*laod NCTL table*/ + if (addr == 0xfe) + halrf_delay_ms(rf, 50); + else if (addr == 0xfd) + halrf_delay_ms(rf, 5); + else if (addr == 0xfc) + halrf_delay_ms(rf, 1); + else if (addr == 0xfb) + halrf_delay_us(rf, 50); + else if (addr == 0xfa) + halrf_delay_us(rf, 5); + else if (addr == 0xf9) + halrf_delay_us(rf, 1); + else + halrf_wreg(rf, addr, mask, data); + + RF_DBG(rf, DBG_RF_INIT, "[RFK] %08X %08X\n", addr, data); +} + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.h new file mode 100644 index 0000000..83495d2 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_REG_CFG_8852B_H_ +#define _HALRF_REG_CFG_8852B_H_ + +#ifdef RF_8852B_SUPPORT + +void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data); +void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data); +void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data); + +#endif +#endif /* RTL8822C_SUPPORT*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.c new file mode 100644 index 0000000..25e3e60 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.c @@ -0,0 +1,1487 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +s8 _halrf_avg_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *value, s8 n) +{ + u8 i; + s16 total = 0; + + RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__); + + for (i = 0; i < n; i++) { + total = total + value[i]; + RF_DBG(rf, DBG_RF_POWER, "value[%d]=%d total=%d n=%d\n", i, value[i], total, n); + } + + total = total / n; + + return (s8)total; +} + +void _halrf_bub_sort_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *data, u32 n) +{ + s32 i, j, sp; + s8 temp; + u32 k; + + for (k = 0; k < n; k++) + RF_DBG(rf, DBG_RF_POWER, "===> %s Before data[%d]=%d\n", __func__, k, data[k]); + + for (i = n - 1; i >= 0; i--) { + sp = 1; + for (j = 0; j < i; j++) { + if (data[j] < data[j + 1]) { + temp = data[j]; + data[j] = data[j + 1]; + data[j + 1] = temp; + sp = 0; + } + } + if (sp == 1) + break; + } + + for (k = 0; k < n; k++) + RF_DBG(rf, DBG_RF_POWER, "<=== %s After data[%d]=%d\n", __func__, k, data[k]); +} + +bool halrf_set_power_by_rate_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; + u32 i, j; + + RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__); + + rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) / 2; + rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) / 2; + rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0) / 2; + rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2; + + rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM6, 0, 0) / 2; + rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM9, 0, 0) / 2; + rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM12, 0, 0) / 2; + rate->pwr_by_rate_lgcy[7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM18, 0, 0) / 2; + + rate->pwr_by_rate_lgcy[8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM24, 0, 0) / 2; + rate->pwr_by_rate_lgcy[9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM36, 0, 0) / 2; + rate->pwr_by_rate_lgcy[10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM48, 0, 0) / 2; + rate->pwr_by_rate_lgcy[11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS0, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS1, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS2, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS3, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS5, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS6, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS8, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS9, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS10, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS0, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS1, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS3, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS2, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS5, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS6, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS8, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS9, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS10, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS11, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + + /*CCK, Legacy, HT, VHT, HE*/ + tpu->pwr_ofst_mode[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 1) / 2; + tpu->pwr_ofst_mode[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_VHT_NSS1_MCS9, 0, 1) / 2; + tpu->pwr_ofst_mode[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_MCS7, 0, 1) / 2; + tpu->pwr_ofst_mode[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 1) / 2; + tpu->pwr_ofst_mode[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 1) / 2; + + for (i = 0; i < 12; i = i + 4) + RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n", + rate->pwr_by_rate_lgcy[i + 3], + rate->pwr_by_rate_lgcy[i + 2], + rate->pwr_by_rate_lgcy[i + 1], + rate->pwr_by_rate_lgcy[i]); + + for (j = 0; j < 2; j++) + for (i = 0; i < 16; i = i + 4) + RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n", + rate->pwr_by_rate[j][i + 3], + rate->pwr_by_rate[j][i + 2], + rate->pwr_by_rate[j][i + 1], + rate->pwr_by_rate[j][i]); + + RF_DBG(rf, DBG_RF_POWER, "power_by_rate_offset ==> %d %d %d %d %d\n", + tpu->pwr_ofst_mode[4], + tpu->pwr_ofst_mode[3], + tpu->pwr_ofst_mode[2], + tpu->pwr_ofst_mode[1], + tpu->pwr_ofst_mode[0]); + return true; +} + +bool halrf_set_power_by_rate_all_the_smae_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; + u32 i, j; + + RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__); + + rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2; + rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2; + rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2; + rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2; + + rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + + rate->pwr_by_rate_lgcy[8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + rate->pwr_by_rate_lgcy[11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_1T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_1T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2; + + rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2; + + /*CCK, Legacy, HT, VHT, HE*/ + tpu->pwr_ofst_mode[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 1) / 2; + tpu->pwr_ofst_mode[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_VHT_NSS1_MCS9, 0, 1) / 2; + tpu->pwr_ofst_mode[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_MCS7, 0, 1) / 2; + tpu->pwr_ofst_mode[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 1) / 2; + tpu->pwr_ofst_mode[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 1) / 2; + + for (i = 0; i < 12; i = i + 4) + RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n", + rate->pwr_by_rate_lgcy[i + 3], + rate->pwr_by_rate_lgcy[i + 2], + rate->pwr_by_rate_lgcy[i + 1], + rate->pwr_by_rate_lgcy[i]); + + for (j = 0; j < 2; j++) + for (i = 0; i < 16; i = i + 4) + RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n", + rate->pwr_by_rate[j][i + 3], + rate->pwr_by_rate[j][i + 2], + rate->pwr_by_rate[j][i + 1], + rate->pwr_by_rate[j][i]); + + RF_DBG(rf, DBG_RF_POWER, "power_by_rate_offset ==> %d %d %d %d %d\n", + tpu->pwr_ofst_mode[0], + tpu->pwr_ofst_mode[1], + tpu->pwr_ofst_mode[2], + tpu->pwr_ofst_mode[3], + tpu->pwr_ofst_mode[4]); + return true; +} + + +void halrf_get_power_limit_to_struct_20m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, lmt, 0, sizeof(*lmt)); + + /*1Tx CCK 20m NOBF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx CCK 20m BF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx CCK 40m NOBF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx CCK 40m BF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx OFDM NOBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*2Tx CCK 20m NOBF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx CCK 20m BF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx CCK 40m NOBF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx CCK 40m BF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx OFDM NOBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; +} + +void halrf_get_power_limit_to_struct_40m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, lmt, 0, sizeof(*lmt)); + + /*1Tx CCK 20m NONBF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2; + + /*1Tx CCK 20m BF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2; + + /*1Tx CCK 40m NONBF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx CCK 40m BF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx OFDM NONBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2; + + /*1Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2; + + /*1Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 2) / 2; + + /*1Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 2) / 2; + + /*1Tx 40m NOBF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx 40m BF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*2Tx CCK 20m NONBF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2; + + /*2Tx CCK 20m BF*/ + lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2; + + /*2Tx CCK 40m NONBF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx CCK 40m BF*/ + lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx OFDM NONBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2; + + /*2Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2; + + /*2Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 2) / 2; + + /*2Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 2) / 2; + + /*2Tx 40m NOBF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx 40m BF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; +} + +void halrf_get_power_limit_to_struct_80m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + s8 tmp, tmp1, tmp2; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, lmt, 0, sizeof(*lmt)); + + /*1Tx OFDM NONBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 6) / 2; + + /*1Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 6) / 2; + + /*1Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 6) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][2][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][3][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 6) / 2; + + /*1Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 6) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][2][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_1T][3][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 6) / 2; + + /*1Tx 40m NOBF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 4) / 2; + + lmt->pwr_lmt_40m[PW_LMT_PH_1T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 4) / 2; + + /*1Tx 40m BF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch - 4) / 2; + + lmt->pwr_lmt_40m[PW_LMT_PH_1T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch + 4) / 2; + + /*1Tx 80m NOBF*/ + lmt->pwr_lmt_80m[PW_LMT_PH_1T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx 80m BF*/ + lmt->pwr_lmt_80m[PW_LMT_PH_1T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2; + + /*1Tx 40m 0p5 NOBF*/ + tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 4) / 2; + tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 4) / 2; + if (tmp1 >= tmp2) + tmp = tmp2; + else + tmp = tmp1; + + lmt->pwr_lmt_40m_0p5[PW_LMT_PH_1T][PW_LMT_NONBF] = tmp; + + /*1Tx 40m 0p5 BF*/ + tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch - 4) / 2; + tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch + 4) / 2; + if (tmp1 >= tmp2) + tmp = tmp2; + else + tmp = tmp1; + + lmt->pwr_lmt_40m_0p5[PW_LMT_PH_1T][PW_LMT_BF] = tmp; + + /*2Tx OFDM NONBF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 6) / 2; + + /*2Tx OFDM BF*/ + lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 6) / 2; + + /*2Tx 20m NOBF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 6) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][2][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][3][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 6) / 2; + + /*2Tx 20m BF*/ + lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 6) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][2][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 2) / 2; + + lmt->pwr_lmt_20m[PW_LMT_PH_2T][3][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 6) / 2; + + /*2Tx 40m NOBF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 4) / 2; + + lmt->pwr_lmt_40m[PW_LMT_PH_2T][1][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 4) / 2; + + /*2Tx 40m BF*/ + lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch - 4) / 2; + + lmt->pwr_lmt_40m[PW_LMT_PH_2T][1][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch + 4) / 2; + + /*2Tx 80m NOBF*/ + lmt->pwr_lmt_80m[PW_LMT_PH_2T][0][PW_LMT_NONBF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx 80m BF*/ + lmt->pwr_lmt_80m[PW_LMT_PH_2T][0][PW_LMT_BF] = + halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2; + + /*2Tx 40m 0p5 NOBF*/ + tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 4) / 2; + tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 4) / 2; + if (tmp1 >= tmp2) + tmp = tmp2; + else + tmp = tmp1; + + lmt->pwr_lmt_40m_0p5[PW_LMT_PH_2T][PW_LMT_NONBF] = tmp; + + /*2Tx 40m 0p5 BF*/ + tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch - 4) / 2; + tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch + 4) / 2; + if (tmp1 >= tmp2) + tmp = tmp2; + else + tmp = tmp1; + + lmt->pwr_lmt_40m_0p5[PW_LMT_PH_2T][PW_LMT_BF] = tmp; +} + +bool halrf_set_power_limit_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i; + u8 bw = rf->hal_com->band[phy].cur_chandef.bw; + u32 i; + s8 tmp; + + RF_DBG(rf, DBG_RF_POWER, "======>%s bandwidth=%d\n", + __func__, bw); + + if (bw == CHANNEL_WIDTH_20) + halrf_get_power_limit_to_struct_20m_8852b(rf, phy); + else if (bw == CHANNEL_WIDTH_40) + halrf_get_power_limit_to_struct_40m_8852b(rf, phy); + else + halrf_get_power_limit_to_struct_80m_8852b(rf, phy); + + tmp = lmt->pwr_lmt_cck_40m[0][0]; + + for (i = 0; i < 2; i++) { + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_cck_40m[i][1], lmt->pwr_lmt_cck_40m[i][0], + lmt->pwr_lmt_cck_20m[i][1], lmt->pwr_lmt_cck_20m[i][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_20m[i][0][1], lmt->pwr_lmt_20m[i][0][0], + lmt->pwr_lmt_lgcy_20m[i][1], lmt->pwr_lmt_lgcy_20m[i][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_20m[i][2][1], lmt->pwr_lmt_20m[i][2][0], + lmt->pwr_lmt_20m[i][1][1], lmt->pwr_lmt_20m[i][1][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_20m[i][4][1], lmt->pwr_lmt_20m[i][4][0], + lmt->pwr_lmt_20m[i][3][1], lmt->pwr_lmt_20m[i][3][0]); + + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_20m[i][6][1], lmt->pwr_lmt_20m[i][6][0], + lmt->pwr_lmt_20m[i][5][1], lmt->pwr_lmt_20m[i][5][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_40m[i][0][1], lmt->pwr_lmt_40m[i][0][0], + lmt->pwr_lmt_20m[i][7][1], lmt->pwr_lmt_20m[i][7][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_40m[i][2][1], lmt->pwr_lmt_40m[i][2][0], + lmt->pwr_lmt_40m[i][1][1], lmt->pwr_lmt_40m[i][1][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_80m[i][0][1], lmt->pwr_lmt_80m[i][0][0], + lmt->pwr_lmt_40m[i][3][1], lmt->pwr_lmt_40m[i][3][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_160m[i][1], lmt->pwr_lmt_160m[i][0], + lmt->pwr_lmt_80m[i][1][1], lmt->pwr_lmt_80m[i][1][0]); + + RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n", + lmt->pwr_lmt_40m_2p5[i][1], lmt->pwr_lmt_40m_2p5[i][0], + lmt->pwr_lmt_40m_0p5[i][1], lmt->pwr_lmt_40m_0p5[i][0]); + } + + return true; +} + +void halrf_get_power_limit_ru_to_struct_20m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru)); + + /*1Tx RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch) / 2; + + /*1Tx RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch) / 2; + + /*1Tx RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch) / 2; + + /*2Tx RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch) / 2; + + /*2Tx RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch) / 2; + + /*2Tx RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch) / 2; +} + +void halrf_get_power_limit_ru_to_struct_40m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru)); + + /*1Tx RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 2) / 2; + + /*1Tx RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 2) / 2; + + /*1Tx RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 2) / 2; + + /*2TX RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 2) / 2; + + /*2TX RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 2) / 2; + + /*2TX RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 2) / 2; +} + +void halrf_get_power_limit_ru_to_struct_80m_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru)); + + /*1TX RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 6) / 2; + + /*1TX RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 6) / 2; + + /*1TX RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 6) / 2; + + /*2TX RU26*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 6) / 2; + + /*2TX RU52*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 6) / 2; + + /*2TX RU106*/ + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 6) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][1] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][2] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 2) / 2; + + tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][3] = + halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 6) / 2; +} + +bool halrf_set_power_limit_ru_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + u8 bw = rf->hal_com->band[phy].cur_chandef.bw; + u8 i, j, k; + + RF_DBG(rf, DBG_RF_POWER, "======>%s bandwidth=%d\n", + __func__, bw); + + if (bw == CHANNEL_WIDTH_20) + halrf_get_power_limit_ru_to_struct_20m_8852b(rf, phy); + else if (bw == CHANNEL_WIDTH_40) { + halrf_get_power_limit_ru_to_struct_40m_8852b(rf, phy); + } else if (bw == CHANNEL_WIDTH_80) { + halrf_get_power_limit_ru_to_struct_80m_8852b(rf, phy); + } + + tpu->pwr_lmt_ru_mem_size = tpu->pwr_lmt_ru_mem_size; + + for (k = 0; k < 2; k++) { + for (j = 0; j < PW_LMT_RU_BW_NULL; j++) { + for (i = 0; i < 8; i = i + 4) { + RF_DBG(rf, DBG_RF_POWER, + "power_limit_ru %dTx ==> %d %d %d %d\n", + k + 1, + tpu->pwr_lmt_ru[k][j][i + 3], + tpu->pwr_lmt_ru[k][j][i + 2], + tpu->pwr_lmt_ru[k][j][i + 1], + tpu->pwr_lmt_ru[k][j][i]); + } + } + } + return true; +} + +void _halrf_set_tx_shape_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + + u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch; + u8 reg; + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch); + + if (!(rf->support_ability & HAL_RF_TX_SHAPE)) { + RF_DBG(rf, DBG_RF_POWER, "======>%s rf->support_ability & HAL_RF_TX_SHAPE=%d Return!!!\n", + __func__, rf->support_ability & HAL_RF_TX_SHAPE); + return; + } + + if (pwr->set_tx_ptrn_shap_en == true) { + RF_DBG(rf, DBG_RF_POWER, "======>%s pwr->set_tx_ptrn_shap_en == true Return!!!\n", + __func__); + return; + } else { + RF_DBG(rf, DBG_RF_POWER, "======>%s pwr->set_tx_ptrn_shap_en == false Set TX shape Default\n", + __func__); + } + + if (ch >= 1 && ch <= 14) { + reg = halrf_get_regulation_info(rf, BAND_ON_24G); + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d regulation=%d\n", __func__, ch, reg); + RF_DBG(rf, DBG_RF_POWER, "tpu->tx_ptrn_shap_idx=%d pwr->tx_shap_idx[%d][CCK][%d]=%d pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + tpu->tx_ptrn_shap_idx, PW_LMT_BAND_2_4G, reg, + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg], + PW_LMT_BAND_2_4G, reg, + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg]); + + tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg]; + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK] = + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg]; + + halrf_bb_set_pow_patten_sharp(rf, ch, true, + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg], phy); /*cck*/ + + RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set CCK Tx Shape!!!\n", + tpu->tx_ptrn_shap_idx, ch); + + tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg]; + + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM] = + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg]; + + halrf_bb_set_pow_patten_sharp(rf, ch, false, + pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg], phy); /*ofdm*/ + + RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set OFDM Tx Shape!!!\n", + tpu->tx_ptrn_shap_idx, ch); + } else if (ch >= 36 && ch <= 177) { + reg = halrf_get_regulation_info(rf, BAND_ON_5G); + + RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d regulation=%d\n", __func__, ch, reg); + RF_DBG(rf, DBG_RF_POWER, "tpu->tx_ptrn_shap_idx=%d pwr->tx_shap_idx[%d][OFDM][%d]=%d\n", + tpu->tx_ptrn_shap_idx, PW_LMT_BAND_5G, reg, + pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg]); + + tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg]; + + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM] = + pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg]; + + halrf_bb_set_pow_patten_sharp(rf, ch, false, + pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg], phy); /*ofdm*/ + + RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set Tx Shape!!!\n", + tpu->tx_ptrn_shap_idx, ch); + } else { +#if 0 + reg = halrf_get_regulation_info(rf, BAND_ON_6G); + pwr->tx_shap_idx[PW_LMT_BAND_6G][reg]; +#endif + } +} + +bool _halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 i; + + RF_DBG(rf, DBG_RF_POWER, "======>%s phl_pwr_table=%d\n", __func__, pwr_table); + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_by_rate_switch=%d\n", + __func__, pwr->pwr_by_rate_switch); + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_limit_switch=%d\n", + __func__, pwr->pwr_limit_switch); + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Efuse pwr->pwr_table_switch_efuse=%d\n", + __func__, pwr->pwr_table_switch_efuse); + + if (pwr_table & PWR_BY_RATE) { + if (pwr->pwr_by_rate_switch == PW_BY_RATE_ALL_SAME) { + halrf_set_power_by_rate_all_the_smae_to_struct_8852b(rf, phy); + } else + halrf_set_power_by_rate_to_struct_8852b(rf, phy); + + if (pwr->pwr_limit_switch == PWLMT_BY_EFUSE) { + if (pwr->pwr_table_switch_efuse == 0) { + halrf_set_power_by_rate_to_struct_8852b(rf, phy); + } else if (pwr->pwr_table_switch_efuse == 2) { + halrf_set_power_by_rate_all_the_smae_to_struct_8852b(rf, phy); + } else { + halrf_set_power_by_rate_to_struct_8852b(rf, phy); + } + } + + halrf_mac_write_pwr_by_rate_reg(rf, phy); + halrf_mac_write_pwr_ofst_mode(rf, phy); + + if (rf->dbg_component & DBG_RF_POWER) { + halrf_delay_ms(rf, 100); + + for (i = 0; i < TX_PWR_BY_RATE_NUM_MAC; i = i + 4) + halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd2c0 + i), 0xffffffff); + } + } + + if (pwr_table & PWR_LIMIT) { + _halrf_set_tx_shape_8852b(rf, phy); + if (!halrf_set_power_limit_to_struct_8852b(rf, phy)) { + RF_DBG(rf, DBG_RF_POWER, "halrf_set_power_limit_to_struct_8852b return fail\n"); + return false; + } + + halrf_mac_write_pwr_limit_reg(rf, phy); + + if (rf->dbg_component & DBG_RF_POWER) { + halrf_delay_ms(rf, 100); + + for (i = 0; i < TX_PWR_LIMIT_NUM_MAC; i = i + 4) + halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd2ec + i), 0xffffffff); + } + } + + if (pwr_table & PWR_LIMIT_RU) { + _halrf_set_tx_shape_8852b(rf, phy); + if (!halrf_set_power_limit_ru_to_struct_8852b(rf, phy)) { + RF_DBG(rf, DBG_RF_POWER, "halrf_set_power_limit_ru_to_struct_8852b return fail\n"); + return false; + } + + halrf_mac_write_pwr_limit_rua_reg(rf, phy); + + if (rf->dbg_component & DBG_RF_POWER) { + halrf_delay_ms(rf, 100); + + for (i = 0; i < 48; i = i + 4) + halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd33c + i), 0xffffffff); + } + } + + return true; +} + +void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + + RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__); + + tpu->ofst_int = 0; + tpu->ofst_fraction = 0; + + /*Set ref power*/ + if (rfe_type > 50) + tpu->base_cw_0db = 0x21; + else + tpu->base_cw_0db = 0x27; + + tpu->tssi_16dBm_cw = 0x12c; + + /*[Ref Pwr]*/ + tpu->ref_pow_ofdm = 0; /*0dBm*/ + tpu->ref_pow_cck = 0; /*0dBm*/ + + halrf_bb_set_tx_pow_ref(rf, phy); +} + + +bool halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table) +{ +#if 0 + if (rf->is_coex == true) { + RF_DBG(rf, DBG_RF_POWER, "===>%s rf->is_coex==true return!!!\n", __func__); + return true; + } +#endif + + if (!_halrf_set_power_8852b(rf, phy, pwr_table)) { + RF_DBG(rf, DBG_RF_POWER, "_halrf_set_power_8852b return fail\n"); + return false; + } + + return true; +} + +void halrf_pwr_by_rate_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u32 bw = rf->hal_com->band[0].cur_chandef.bw; + u32 band = rf->hal_com->band[0].cur_chandef.band; + u32 reg_tmp, cck_ref, ofdm_ref; + s32 s_cck_ref, s_ofdm_ref; + s32 int_tmp[2], float_tmp[2]; + + u32 used = *_used; + u32 out_len = *_out_len; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RF Para Ver", RF_RELEASE_VERSION_8852B); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RFE type", rf->phl_com->dev_cap.rfe_type); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n", + "Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"), + channel, + bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M")); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n", + "Driver Swith / Efuse Switch", + (pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" : + (pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse", + (pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ? + ((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit") + : "From Driver"); + + cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00); + ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000); + (cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref); + (ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref); + int_tmp[0] = s_cck_ref / 4; + float_tmp[0] = s_cck_ref * 100 / 4 % 100; + float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0; + int_tmp[1] = s_ofdm_ref / 4; + float_tmp[1] = s_ofdm_ref * 100 / 4 % 100; + float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0; + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n", + "CCK REF / OFDM REF", + (int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "", + int_tmp[0], float_tmp[0], + (int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "", + int_tmp[1], float_tmp[1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "1SS\n"); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c0, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "CCK 11M / 5.5M / 2M / 1M", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c4, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "OFDM 18M / 12M / 9M / 6M", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c8, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "OFDM 54M / 48M / 36M / 24M", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s\n", + "HT / VHT / HE"); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2cc, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS3 / MCS2 / MCS1 / MCS0", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d0, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS7 / MCS6 / MCS5 / MCS4", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d4, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS11 / MCS10 / MCS9 / MCS8", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d8, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "DCM MCS4 / MCS3 / MCS1 / MCS0", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "2SS\n"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s\n", + "HT / VHT / HE"); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2dc, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS3 / MCS2 / MCS1 / MCS0", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e0, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS7 / MCS6 / MCS5 / MCS4", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e4, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "MCS11 / MCS10 / MCS9 / MCS8", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e8, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n", + "DCM MCS4 / MCS3 / MCS1 / MCS0", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10, + ((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10, + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10 + ); + + *_used = used; + *_out_len = out_len; + +} + +void halrf_pwr_limit_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u32 bw = rf->hal_com->band[0].cur_chandef.bw; + u32 band = rf->hal_com->band[0].cur_chandef.band; + u32 reg_tmp, cck_ref, ofdm_ref; + s32 s_cck_ref, s_ofdm_ref; + s32 int_tmp[2], float_tmp[2]; + + u32 used = *_used; + u32 out_len = *_out_len; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RF Para Ver", RF_RELEASE_VERSION_8852B); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RFE type", rf->phl_com->dev_cap.rfe_type); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n", + "Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"), + channel, + bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M")); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s / %s\n", + "Regulation 2G / 5G / 6G", + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_24G), + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_5G), + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_6G)); + + cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00); + ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000); + (cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref); + (ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref); + int_tmp[0] = s_cck_ref / 4; + float_tmp[0] = s_cck_ref * 100 / 4 % 100; + float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0; + int_tmp[1] = s_ofdm_ref / 4; + float_tmp[1] = s_ofdm_ref * 100 / 4 % 100; + float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0; + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n", + "CCK REF / OFDM REF", + (int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "", + int_tmp[0], float_tmp[0], + (int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "", + int_tmp[1], float_tmp[1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s\n", + "Power Limit (Reg)", + halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd208, BIT(21)) ? "Enable Limit" : "Disable Limit"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n", + "Driver Swith / Efuse Switch", + (pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" : + (pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse", + (pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ? + ((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit") + : "From Driver"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d / %d / %d\n", + "TX Shape CCK / 2G / 5G", + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK], + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM], + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "1SS\n"); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2ec, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "CCK 20M NOBF", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "CCK 40M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2, + ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2f0, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "OFDM NOBF", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "HT 20M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2, + ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd300, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "HT 40M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2, + ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd308, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "HT 80M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2, + ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "2SS\n"); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd314, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "CCK 20M NOBF", + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "CCK 40M NOBF", + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd318, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "OFDM NOBF", + (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n", + "HT 20M BF / NOBF", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd328, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n", + "HT 40M BF / NOBF", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd330, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n", + "HT 80M BF / NOBF", + ((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10, + ((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10); + + *_used = used; + *_out_len = out_len; + +} + +void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u32 bw = rf->hal_com->band[0].cur_chandef.bw; + u32 band = rf->hal_com->band[0].cur_chandef.band; + u32 reg_tmp, cck_ref, ofdm_ref; + s32 s_cck_ref, s_ofdm_ref; + s32 int_tmp[2], float_tmp[2]; + + u32 used = *_used; + u32 out_len = *_out_len; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RF Para Ver", RF_RELEASE_VERSION_8852B); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n", + "RFE type", rf->phl_com->dev_cap.rfe_type); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n", + "Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"), + channel, + bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M")); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s / %s\n", + "Regulation 2G / 5G / 6G", + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_24G), + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_5G), + halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_6G)); + + cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00); + ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000); + (cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref); + (ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref); + int_tmp[0] = s_cck_ref / 4; + float_tmp[0] = s_cck_ref * 100 / 4 % 100; + float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0; + int_tmp[1] = s_ofdm_ref / 4; + float_tmp[1] = s_ofdm_ref * 100 / 4 % 100; + float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0; + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n", + "CCK REF / OFDM REF", + (int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "", + int_tmp[0], float_tmp[0], + (int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "", + int_tmp[1], float_tmp[1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s\n", + "Power Limit (Reg)", + halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd208, BIT(20)) ? "Enable Limit" : "Disable Limit"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n", + "Driver Swith / Efuse Switch", + (pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" : + (pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse", + (pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ? + ((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit") + : "From Driver"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d / %d / %d\n", + "TX Shape CCK / 2G / 5G", + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK], + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM], + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM]); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd33c, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "RU26", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd344, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "RU52", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + + reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd34c, 0xffffffff); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n", + "RU106", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10); + + *_used = used; + *_out_len = out_len; + +} + +void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx) +{ + struct rtw_tpu_info *tpu = &rf->hal_com->band[0].rtw_tpu_i; + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 ch = rf->hal_com->band[0].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s ch=%d tx_shape_idx=%d\n", + __func__, ch, tx_shape_idx); + + tpu->tx_ptrn_shap_idx = tx_shape_idx; + + if (tx_shape_idx == 255) { + pwr->set_tx_ptrn_shap_en = false; + _halrf_set_tx_shape_8852b(rf, 0); + return; + } else + pwr->set_tx_ptrn_shap_en = true; + + if (ch <= 14) { + halrf_bb_set_pow_patten_sharp(rf, ch, true, tx_shape_idx, 0); /*cck*/ + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK] = tx_shape_idx; + } + + halrf_bb_set_pow_patten_sharp(rf, ch, false, tx_shape_idx, 0); /*ofdm*/ + + if (ch >= 1 && ch <= 14) + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM] = tx_shape_idx; + else + pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM] = tx_shape_idx; +} +#endif /*RF_8852B_SUPPORT*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.h new file mode 100644 index 0000000..d4e4ab6 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_SET_PWR_TABLE_8852B_H_ +#define _HALRF_SET_PWR_TABLE_8852B_H_ + +#ifdef RF_8852B_SUPPORT + +/*@--------------------------Define Parameters-------------------------------*/ +#define MAX_TX_PATH 2 +#define TPU_SIZE_RUA 3 /*{26, 52, 106}*/ +#define TPU_SIZE_BW20_SC 8 /*8 * 20M = 160M*/ + +/*@-----------------------End Define Parameters-----------------------*/ + +bool halrf_set_power_by_rate_to_mac_8852b(struct rf_info *rf, + enum phl_phy_idx phy); + +bool halrf_set_power_limit_to_mac_8852b(struct rf_info *rf, + enum phl_phy_idx phy); + +void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf, + enum phl_phy_idx phy); + +bool halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table); + +void halrf_pwr_by_rate_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_pwr_limit_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx); + +#endif /*RF_8852B_SUPPORT*/ +#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.c new file mode 100644 index 0000000..d3114b5 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.c @@ -0,0 +1,2729 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "../halrf_precomp.h" + +#ifdef RF_8852B_SUPPORT + +void _tssi_backup_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", + reg[i], reg_backup[i]); + } +} + +void _tssi_reload_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) + +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", + reg[i], reg_backup[i]); + } +} + +u8 _halrf_ch_to_idx(struct rf_info *rf, u8 channel) +{ + u8 channelIndex; + + if (channel >= 1 && channel <= 14) + channelIndex = channel - 1; + else if (channel >= 36 && channel <= 64) + channelIndex = (channel - 36) / 2 + 14; + else if (channel >= 100 && channel <= 144) + channelIndex = ((channel - 100) / 2) + 15 + 14; + else if (channel >= 149 && channel <= 177) + channelIndex = ((channel - 149) / 2) + 38 + 14; + else + channelIndex = 0; + + return channelIndex; +} + +u8 _halrf_idx_to_ch(struct rf_info *rf, u8 idx) +{ + u8 channelIndex; + + if (idx >= 0 && idx <= 13) + channelIndex = idx + 1; + else if (idx >= (0 + 14) && idx <= (14 + 14)) + channelIndex = (idx - 14) * 2 + 36; + else if (idx >= (15 + 14) && idx <= (37 + 14)) + channelIndex = (idx - 15 - 14) * 2 + 100; + else if (idx >= (38 + 14) && idx <= (52 + 14)) + channelIndex = (idx - 38 - 14) * 2 + 149; + else + channelIndex = 0; + + return channelIndex; +} + +void _halrf_tssi_hw_tx_8852b(struct rf_info *rf, + enum phl_phy_idx phy, u8 path, u16 cnt, u16 period, s16 dbm, u32 rate, u8 bw, + bool enable) +{ + struct rf_pmac_tx_info tx_info = {0}; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + tx_info.ppdu = rate; + tx_info.mcs = 7; + tx_info.bw = bw; + tx_info.nss = 1; + tx_info.gi = 1; + tx_info.txagc_cw = 0; + tx_info.dbm = dbm; + tx_info.cnt = cnt; + tx_info.time = 20; + tx_info.period = period; + tx_info.length = 0; + + halrf_set_pmac_tx(rf, phy, path, &tx_info, enable, false); +} + +void _halrf_tssi_rf_setting_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + if (channel >= 1 && channel <= 14) + halrf_wrf(rf, path, 0x7f, 0x00002, 0x1); + else + halrf_wrf(rf, path, 0x7f, 0x00100, 0x1); +} + +void _halrf_tssi_set_sys_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + halrf_wreg(rf, 0x12a8, 0x0000000f, 0x5); + halrf_wreg(rf, 0x32a8, 0x0000000f, 0x5); + halrf_wreg(rf, 0x12bc, 0x000ffff0, 0x5555); + halrf_wreg(rf, 0x32bc, 0x000ffff0, 0x5555); + halrf_wreg(rf, 0x0300, 0xff000000, 0x16); + halrf_wreg(rf, 0x0304, 0x000000ff, 0x19); + halrf_wreg(rf, 0x0314, 0xffff0000, 0x2041); + halrf_wreg(rf, 0x0318, 0xffffffff, 0x2041); + halrf_wreg(rf, 0x0318, 0xffffffff, 0x20012041); + halrf_wreg(rf, 0x0020, 0x00006000, 0x3); + halrf_wreg(rf, 0x0024, 0x00006000, 0x3); + halrf_wreg(rf, 0x0704, 0xffff0000, 0x601e); + halrf_wreg(rf, 0x2704, 0xffff0000, 0x601e); + halrf_wreg(rf, 0x0700, 0xf0000000, 0x4); + halrf_wreg(rf, 0x2700, 0xf0000000, 0x4); + halrf_wreg(rf, 0x0650, 0x3c000000, 0x0); + halrf_wreg(rf, 0x2650, 0x3c000000, 0x0); + + if (path == RF_PATH_A) { + if (channel >= 1 && channel <= 14) { + halrf_wreg(rf, 0x120c, 0x000000ff, 0x33); + halrf_wreg(rf, 0x12c0, 0x0ff00000, 0x33); + halrf_wreg(rf, 0x58f8, 0x40000000, 0x1); + halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1e); + } else { + halrf_wreg(rf, 0x120c, 0x000000ff, 0x44); + halrf_wreg(rf, 0x12c0, 0x0ff00000, 0x44); + halrf_wreg(rf, 0x58f8, 0x40000000, 0x0); + halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1d); + } + } else { + if (channel >= 1 && channel <= 14) { + halrf_wreg(rf, 0x32c0, 0x0ff00000, 0x33); + halrf_wreg(rf, 0x320c, 0x000000ff, 0x33); + halrf_wreg(rf, 0x78f8, 0x40000000, 0x1); + halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1e); + } else { + halrf_wreg(rf, 0x32c0, 0x0ff00000, 0x44); + halrf_wreg(rf, 0x320c, 0x000000ff, 0x44); + halrf_wreg(rf, 0x78f8, 0x40000000, 0x0); + halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1d); + } + } +} + +void _halrf_tssi_ini_txpwr_ctrl_bb_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x566c, 0x00001000, 0x0); + halrf_wreg(rf, 0x5800, 0xffffffff, 0x003f807f); +#if 0 + halrf_wreg(rf, 0x5804, 0x000001ff, 0x040); + halrf_wreg(rf, 0x5804, 0xfffc0000, 0x012c); + halrf_wreg(rf, 0x5808, 0x000001ff, 0x040); + halrf_wreg(rf, 0x5808, 0x07fc0000, 0x12c); +#endif + halrf_wreg(rf, 0x580c, 0x0000007f, 0x40); + halrf_wreg(rf, 0x580c, 0x0fffff00, 0x00040); + halrf_wreg(rf, 0x5810, 0xffffffff, 0x59010000); + halrf_wreg(rf, 0x5814, 0x01ffffff, 0x002d000); + halrf_wreg(rf, 0x5814, 0xf8000000, 0x00); + halrf_wreg(rf, 0x5818, 0xffffffff, 0x002c1800); + halrf_wreg(rf, 0x581c, 0x3fffffff, 0x1dc80280); + halrf_wreg(rf, 0x5820, 0xffffffff, 0x00002080); + halrf_wreg(rf, 0x580c, 0x10000000, 0x1); + halrf_wreg(rf, 0x580c, 0x40000000, 0x1); + halrf_wreg(rf, 0x5834, 0x3fffffff, 0x000115f2); + halrf_wreg(rf, 0x5838, 0x7fffffff, 0x0000121); + halrf_wreg(rf, 0x5854, 0x3fffffff, 0x000115f2); + halrf_wreg(rf, 0x5858, 0x7fffffff, 0x0000121); + halrf_wreg(rf, 0x5860, 0x80000000, 0x0); + halrf_wreg(rf, 0x5864, 0x07ffffff, 0x00801ff); + halrf_wreg(rf, 0x5898, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x589c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x58a4, 0x000000ff, 0x16); + halrf_wreg(rf, 0x58b0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x58b4, 0x7fffffff, 0x0a002000); + halrf_wreg(rf, 0x58b8, 0x7fffffff, 0x00007628); + + /*GNT_WL==0 & 0x58bc[18]==1, Bypass TSSI*/ + /*GNT_BT==1 & 0x58bc[20]==1, Bypass TSSI*/ + /*GNT_BT_TX==1 & 0x58bc[22]==1, Bypass TSSI*/ + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) + halrf_wreg(rf, 0x58bc, 0x07ffffff, 0x7f7807f); + else + halrf_wreg(rf, 0x58bc, 0x07ffffff, 0x7a7807f); + + halrf_wreg(rf, 0x58c0, 0xfffe0000, 0x003f); + halrf_wreg(rf, 0x58c4, 0xffffffff, 0x0003ffff); + halrf_wreg(rf, 0x58c8, 0x00ffffff, 0x000000); + halrf_wreg(rf, 0x58c8, 0xf0000000, 0x0); + halrf_wreg(rf, 0x58cc, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x58d0, 0x07ffffff, 0x2008101); + halrf_wreg(rf, 0x58d4, 0x000000ff, 0x00); + halrf_wreg(rf, 0x58d4, 0x0003fe00, 0x0ff); + halrf_wreg(rf, 0x58d4, 0x07fc0000, 0x100); + halrf_wreg(rf, 0x58d8, 0xffffffff, 0x8008016c); + halrf_wreg(rf, 0x58dc, 0x0001ffff, 0x0807f); + halrf_wreg(rf, 0x58dc, 0xfff00000, 0x800); + halrf_wreg(rf, 0x58f0, 0x0003ffff, 0x001ff); + halrf_wreg(rf, 0x58f4, 0x000fffff, 0x000); + } else { + halrf_wreg(rf, 0x566c, 0x00001000, 0x0); + halrf_wreg(rf, 0x7800, 0xffffffff, 0x003f807f); +#if 0 + halrf_wreg(rf, 0x7804, 0x000001ff, 0x040); + halrf_wreg(rf, 0x7804, 0xfffc0000, 0x012c); + halrf_wreg(rf, 0x7808, 0x000001ff, 0x040); + halrf_wreg(rf, 0x7808, 0x07fc0000, 0x12c); +#endif + halrf_wreg(rf, 0x780c, 0x0000007f, 0x40); + halrf_wreg(rf, 0x780c, 0x0fffff00, 0x00040); + halrf_wreg(rf, 0x7810, 0xffffffff, 0x59010000); + halrf_wreg(rf, 0x7814, 0x01ffffff, 0x002d000); + halrf_wreg(rf, 0x7814, 0xf8000000, 0x00); + halrf_wreg(rf, 0x7818, 0xffffffff, 0x002c1800); + halrf_wreg(rf, 0x781c, 0x3fffffff, 0x1dc80280); + halrf_wreg(rf, 0x7820, 0xffffffff, 0x00002080); + halrf_wreg(rf, 0x780c, 0x10000000, 0x1); + halrf_wreg(rf, 0x780c, 0x40000000, 0x1); + halrf_wreg(rf, 0x7834, 0x3fffffff, 0x000115f2); + halrf_wreg(rf, 0x7838, 0x7fffffff, 0x0000121); + halrf_wreg(rf, 0x7854, 0x3fffffff, 0x000115f2); + halrf_wreg(rf, 0x7858, 0x7fffffff, 0x0000121); + halrf_wreg(rf, 0x7860, 0x80000000, 0x0); + halrf_wreg(rf, 0x7864, 0x07ffffff, 0x00801ff); + halrf_wreg(rf, 0x7898, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x789c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x78a4, 0x000000ff, 0x16); + halrf_wreg(rf, 0x78b0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x78b4, 0x7fffffff, 0x0a002000); + halrf_wreg(rf, 0x78b8, 0x7fffffff, 0x00007628); + + /*GNT_WL==0 & 0x78bc[18]==1, Bypass TSSI*/ + /*GNT_BT==1 & 0x78bc[20]==1, Bypass TSSI*/ + /*GNT_BT_TX==1 & 0x78bc[22]==1, Bypass TSSI*/ + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) + halrf_wreg(rf, 0x78bc, 0x07ffffff, 0x7f7807f); + else + halrf_wreg(rf, 0x78bc, 0x07ffffff, 0x7a7807f); + + halrf_wreg(rf, 0x78c0, 0xfffe0000, 0x003f); + halrf_wreg(rf, 0x78c4, 0xffffffff, 0x0003ffff); + halrf_wreg(rf, 0x78c8, 0x00ffffff, 0x000000); + halrf_wreg(rf, 0x78c8, 0xf0000000, 0x0); + halrf_wreg(rf, 0x78cc, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x78d0, 0x07ffffff, 0x2008101); + halrf_wreg(rf, 0x78d4, 0x000000ff, 0x00); + halrf_wreg(rf, 0x78d4, 0x0003fe00, 0x0ff); + halrf_wreg(rf, 0x78d4, 0x07fc0000, 0x100); + halrf_wreg(rf, 0x78d8, 0xffffffff, 0x8008016c); + halrf_wreg(rf, 0x78dc, 0x0001ffff, 0x0807f); + halrf_wreg(rf, 0x78dc, 0xfff00000, 0x800); + halrf_wreg(rf, 0x78f0, 0x0003ffff, 0x001ff); + halrf_wreg(rf, 0x78f4, 0x000fffff, 0x000); + } + +} + +void _halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x58a0, MASKDWORD, 0x000000fe); + halrf_wreg(rf, 0x58e4, 0x0000007f, 0x1f); + } else { + halrf_wreg(rf, 0x78a0, MASKDWORD, 0x000000fe); + halrf_wreg(rf, 0x78e4, 0x0000007f, 0x1f); + } +} + +void _halrf_tssi_set_dck_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x580c, 0x0fff0000, 0x000); + halrf_wreg(rf, 0x5814, 0x003ff000, 0x0ef); + halrf_wreg(rf, 0x5814, 0x18000000, 0x0); + } else { + halrf_wreg(rf, 0x780c, 0x0fff0000, 0x000); + halrf_wreg(rf, 0x7814, 0x003ff000, 0x0ef); + halrf_wreg(rf, 0x7814, 0x18000000, 0x0); + } +} + +void _halrf_tssi_set_bbgain_split_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5818, 0x08000000, 0x1); + halrf_wreg(rf, 0x58d4, 0xf0000000, 0x7); + halrf_wreg(rf, 0x58f0, 0x000c0000, 0x1); + halrf_wreg(rf, 0x58f0, 0xfff00000, 0x400); + } else { + halrf_wreg(rf, 0x7818, 0x08000000, 0x1); + halrf_wreg(rf, 0x78d4, 0xf0000000, 0x7); + halrf_wreg(rf, 0x78f0, 0x000c0000, 0x1); + halrf_wreg(rf, 0x78f0, 0xfff00000, 0x400); + } +} + +void _halrf_tssi_set_tmeter_tbl_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_pwr_track_info *pwr_trk = &rf->pwr_track; + struct halrf_tssi_info *tssi_info = &rf->tssi; + struct rtw_hal_com_t *hal = rf->hal_com; + + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + u8 i, thermal = 0xff, j; + //u8 rate = phydm_get_tx_rate(dm); + u32 thermal_offset_tmp = 0; + s8 thermal_offset[64] = {0}; + s8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0}; + s8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0}; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (tssi_info->tssi_type == TSSI_CAL) { + halrf_wreg(rf, 0x5810, 0x00010000, 0x0); + halrf_wreg(rf, 0x5810, 0x01000000, 0x1); + + halrf_wreg(rf, 0x7810, 0x00010000, 0x0); + halrf_wreg(rf, 0x7810, 0x01000000, 0x1); + + halrf_wreg(rf, 0x5810, 0x0000fc00, 32); + halrf_wreg(rf, 0x5864, 0x03f00000, 32); + halrf_wreg(rf, 0x7810, 0x0000fc00, 32); + halrf_wreg(rf, 0x7864, 0x03f00000, 32); + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp); + halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x5c00 + i), thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x7c00 + i), thermal_offset_tmp); + } + + halrf_wreg(rf, 0x5864, BIT(26), 0x1); + halrf_wreg(rf, 0x5864, BIT(26), 0x0); + + halrf_wreg(rf, 0x7864, BIT(26), 0x1); + halrf_wreg(rf, 0x7864, BIT(26), 0x0); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s TSSI Calibration Mode return !!!\n", __func__); + + return; + } + + if (channel >= 1 && channel <= 14) { + hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_2ga_p, sizeof(thermal_up_a)); + hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_2ga_n, sizeof(thermal_down_a)); + hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_2gb_p, sizeof(thermal_up_b)); + hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_2gb_n, sizeof(thermal_down_b)); + } else if (channel >= 36 && channel <= 64) { + hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[0], sizeof(thermal_up_a)); + hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[0], sizeof(thermal_down_a)); + hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[0], sizeof(thermal_up_b)); + hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[0], sizeof(thermal_down_b)); + } else if (channel >= 100 && channel <= 144) { + hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[1], sizeof(thermal_up_a)); + hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[1], sizeof(thermal_down_a)); + hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[1], sizeof(thermal_up_b)); + hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[1], sizeof(thermal_down_b)); + } else if (channel >= 149 && channel <= 177) { + hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[2], sizeof(thermal_up_a)); + hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[2], sizeof(thermal_down_a)); + hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[2], sizeof(thermal_up_b)); + hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[2], sizeof(thermal_down_b)); + } + + /*path s0*/ + if (path == RF_PATH_A) { + hal_mem_set(hal, thermal_offset, 0, sizeof(thermal_offset)); + halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal, 1); + + /*thermal = 32;*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] channel=%d thermal_pahtA=0x%x tssi_info->tssi_type=%d\n", + channel, thermal, tssi_info->tssi_type); + + halrf_wreg(rf, 0x5810, 0x00010000, 0x0); + halrf_wreg(rf, 0x5810, 0x01000000, 0x1); + + if (thermal == 0xff) { + halrf_wreg(rf, 0x5810, 0x0000fc00, 32); + halrf_wreg(rf, 0x5864, 0x03f00000, 32); + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x5c00 + i), thermal_offset_tmp); + } + } + + tssi_info->thermal[RF_PATH_A] = thermal; + + if (thermal != 0xff) { + halrf_wreg(rf, 0x5810, 0x0000fc00, (thermal & 0x3f)); + halrf_wreg(rf, 0x5864, 0x03f00000, (thermal & 0x3f)); + + i = 0; + for (j = 0; j < 32; j++) { + if (i < DELTA_SWINGIDX_SIZE) + thermal_offset[j] = -1 * thermal_down_a[i++]; + else + thermal_offset[j] = -1 * thermal_down_a[DELTA_SWINGIDX_SIZE - 1]; + } + + i = 1; + for (j = 63; j >= 32; j--) { + if (i < DELTA_SWINGIDX_SIZE) + thermal_offset[j] = thermal_up_a[i++]; + else + thermal_offset[j] = thermal_up_a[DELTA_SWINGIDX_SIZE - 1]; + } + + for (i = 0; i < 64; i = i + 4) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n", + i, thermal_offset[i + 3] & 0xff, thermal_offset[i + 2] & 0xff, + thermal_offset[i + 1] & 0xff, thermal_offset[i] & 0xff); + } + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x5c00 + i), thermal_offset_tmp); + } + } + halrf_wreg(rf, 0x5864, BIT(26), 0x1); + halrf_wreg(rf, 0x5864, BIT(26), 0x0); + } else { + /*path s1*/ + hal_mem_set(hal, thermal_offset, 0, sizeof(thermal_offset)); + halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal, 1); + + /*thermal = 32;*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] channel=%d thermal_pahtB=0x%x tssi_info->tssi_type=%d\n", + channel, thermal, tssi_info->tssi_type); + + halrf_wreg(rf, 0x7810, 0x00010000, 0x0); + halrf_wreg(rf, 0x7810, 0x01000000, 0x1); + + if (thermal == 0xff) { + halrf_wreg(rf, 0x7810, 0x0000fc00, 32); + halrf_wreg(rf, 0x7864, 0x03f00000, 32); + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x7c00 + i), thermal_offset_tmp); + } + } + + tssi_info->thermal[RF_PATH_B] = thermal; + + if (thermal != 0xff) { + halrf_wreg(rf, 0x7810, 0x0000fc00, (thermal & 0x3f)); + halrf_wreg(rf, 0x7864, 0x03f00000, (thermal & 0x3f)); + + i = 0; + for (j = 0; j < 32; j++) { + if (i < DELTA_SWINGIDX_SIZE) + thermal_offset[j] = -1 * thermal_down_b[i++]; + else + thermal_offset[j] = -1 * thermal_down_b[DELTA_SWINGIDX_SIZE - 1]; + } + + i = 1; + for (j = 63; j >= 32; j--) { + if (i < DELTA_SWINGIDX_SIZE) + thermal_offset[j] = thermal_up_b[i++]; + else + thermal_offset[j] = thermal_up_b[DELTA_SWINGIDX_SIZE - 1]; + } + + for (i = 0; i < 64; i = i + 4) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n", + i, thermal_offset[i + 3] & 0xff, thermal_offset[i + 2] & 0xff, + thermal_offset[i + 1] & 0xff, thermal_offset[i] & 0xff); + } + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (0x7c00 + i), thermal_offset_tmp); + } + } + halrf_wreg(rf, 0x7864, BIT(26), 0x1); + halrf_wreg(rf, 0x7864, BIT(26), 0x0); + } + +} + +void _halrf_tssi_set_tmeter_tbl_zere_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + u8 i; + u32 thermal_offset_tmp = 0; + u32 ftable_reg[TSSI_PATH_MAX_8852B] = {0x5c00, 0x7c00}; + u32 ftable_base_reg[TSSI_PATH_MAX_8852B] = {0x5810, 0x7810}; + u32 ftable_trigger_reg[TSSI_PATH_MAX_8852B] = {0x5864, 0x7864}; + s8 thermal_offset[64] = {0}; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + halrf_wreg(rf, ftable_base_reg[path], 0x00010000, 0x0); + halrf_wreg(rf, ftable_base_reg[path], 0x01000000, 0x1); + + halrf_wreg(rf, ftable_base_reg[path], 0x0000fc00, 32); + halrf_wreg(rf, ftable_trigger_reg[path], 0x03f00000, 32); + + for (i = 0; i < 64; i = i + 4) { + thermal_offset_tmp = (thermal_offset[i] & 0xff) | + (thermal_offset[i + 1] & 0xff) << 8 | + (thermal_offset[i + 2] & 0xff) << 16 | + (thermal_offset[i + 3] & 0xff) << 24; + + halrf_wreg(rf, (ftable_reg[path] + i), MASKDWORD, thermal_offset_tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] write addr:0x%x value=0x%08x\n", + (ftable_reg[path] + i), thermal_offset_tmp); + } + + halrf_wreg(rf, ftable_trigger_reg[path], BIT(26), 0x1); + halrf_wreg(rf, ftable_trigger_reg[path], BIT(26), 0x0); + +} + +void _halrf_tssi_set_dac_gain_tbl_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x58b0, 0x00000400, 0x1); + halrf_wreg(rf, 0x58b0, 0x00000fff, 0x000); + halrf_wreg(rf, 0x58b0, 0x00000800, 0x1); + halrf_wreg(rf, 0x5a00, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a04, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a08, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a0c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a10, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a14, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a18, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a1c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a20, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a24, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a28, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a2c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a30, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a34, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a38, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a3c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a40, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a44, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a48, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a4c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a50, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a54, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a58, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a5c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a60, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a64, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a68, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a6c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a70, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a74, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a78, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a7c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a80, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a84, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a88, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a8c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a90, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a94, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a98, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5a9c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5aa0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5aa4, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5aa8, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5aac, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5ab0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5ab4, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5ab8, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5abc, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x5ac0, MASKDWORD, 0x00000000); + } else { + halrf_wreg(rf, 0x78b0, 0x00000fff, 0x000); + halrf_wreg(rf, 0x78b0, 0x00000800, 0x1); + halrf_wreg(rf, 0x7a00, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a04, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a08, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a0c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a10, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a14, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a18, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a1c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a20, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a24, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a28, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a2c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a30, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a34, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a38, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a3c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a40, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a44, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a48, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a4c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a50, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a54, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a58, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a5c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a60, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a64, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a68, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a6c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a70, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a74, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a78, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a7c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a80, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a84, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a88, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a8c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a90, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a94, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a98, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7a9c, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7aa0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7aa4, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7aa8, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7aac, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7ab0, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7ab4, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7ab8, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7abc, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x7ac0, MASKDWORD, 0x00000000); + } + +} + +void _halrf_tssi_slope_cal_org_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5608, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x560c, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x5610, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x5614, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x5618, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x561c, 0x000001ff, 0x008); + halrf_wreg(rf, 0x561c, 0xffff0000, 0x0808); + halrf_wreg(rf, 0x5620, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x5624, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x5628, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x562c, 0x0000ffff, 0x0808); + halrf_wreg(rf, 0x581c, 0x00100000, 0x0); + } else { + halrf_wreg(rf, 0x7608, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x760c, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x7610, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x7614, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x7618, 0x07ffffff, 0x0201008); + halrf_wreg(rf, 0x761c, 0x000001ff, 0x008); + halrf_wreg(rf, 0x761c, 0xffff0000, 0x0808); + halrf_wreg(rf, 0x7620, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x7624, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x7628, 0xffffffff, 0x08080808); + halrf_wreg(rf, 0x762c, 0x0000ffff, 0x0808); + halrf_wreg(rf, 0x781c, 0x00100000, 0x0); + } +} + + +void _halrf_tssi_slope_cal_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + s16 power_2g_high[4] = {80, 24, 0, -24}; + s16 power_2g_low[4] = {56, 8, -16, -36}; + s16 power_5g_high[4] = {80, 24, 0, -36}; + s16 power_5g_low[4] = {56, 8, -16, -44}; + s16 power_high[4] = {0}, power_low[4] = {0}; + u32 tssi_cw_rpt_high = 0, tssi_cw_rpt_low = 0, + tssi_cw_rpt_offset[4] = {0}; + + u32 tssi_trigger[TSSI_PATH_MAX_8852B] = {0x5820, 0x7820}; + u32 tssi_cw_rpt_addr[TSSI_PATH_MAX_8852B] = {0x1c18, 0x3c18}; + + u8 i, j, k; + u32 rate = T_HT_MF; + u8 bw = 0; + u8 phy_map; + + phy_map = (BIT(phy) << 4) | BIT(path); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n", + __func__, channel, path); + + if (channel >= 1 && channel <= 14) { + for (i = 0; i < 4; i++) { + power_high[i] = power_2g_high[i]; + power_low[i] = power_2g_low[i]; + } + } else { + for (i = 0; i < 4; i++) { + power_high[i] = power_5g_high[i]; + power_low[i] = power_5g_low[i]; + } + } + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_ONESHOT_START); + for (j = 0; j < 4; j++) { + /*high power*/ + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0); + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1); + + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, true); + + for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) { + halrf_delay_us(rf, 1); + + if (k > 100) { + //halrf_set_pseudo_cw(rf, i, power_high[j], false); + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > 100us path=%d\n", + i); + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false); + return; + } + } + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false); + tssi_cw_rpt_high = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff); + + /*low power*/ + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0); + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1); + + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_low[j], rate, bw, true); + + for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) { + halrf_delay_us(rf, 1); + + if (k > 100) { + //halrf_set_pseudo_cw(rf, i, power_low[j], false); + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > 100us path=%d\n", + i); + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false); + return; + } + } + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false); + tssi_cw_rpt_low = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff); + + tssi_cw_rpt_offset[j] = tssi_cw_rpt_high - tssi_cw_rpt_low; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] power_high[%d]=%d power_low[%d]=%d\n", + j, power_high[j], j, power_low[j]); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_cw_rpt_offset[%d](0x%x) = tssi_cw_rpt_high(0x%x) - tssi_cw_rpt_low(0x%x)\n", + j, tssi_cw_rpt_offset[j], tssi_cw_rpt_high, tssi_cw_rpt_low); + + //halrf_set_pseudo_cw(rf, i, power_low[j], false); + + } + + halrf_wreg(rf, 0x581c, 0x00100000, 0x1); + halrf_wreg(rf, 0x58cc, 0x00001000, 0x1); + halrf_wreg(rf, 0x58cc, 0x00000007, 0x7); + halrf_wreg(rf, 0x58cc, 0x00000038, 0x6); + halrf_wreg(rf, 0x58cc, 0x000001c0, 0x3); + halrf_wreg(rf, 0x58cc, 0x00000e00, 0x1); + + halrf_wreg(rf, 0x5828, 0x7fc00000, tssi_cw_rpt_offset[0]); + halrf_wreg(rf, 0x5898, 0x000000ff, power_high[0] - power_low[0]); + + halrf_wreg(rf, 0x5830, 0x7fc00000, tssi_cw_rpt_offset[0]); + halrf_wreg(rf, 0x5898, 0x0000ff00, power_high[0] - power_low[0]); + + halrf_wreg(rf, 0x5838, 0x7fc00000, tssi_cw_rpt_offset[1]); + halrf_wreg(rf, 0x5898, 0x00ff0000, power_high[1] - power_low[1]); + + halrf_wreg(rf, 0x5840, 0x7fc00000, tssi_cw_rpt_offset[1]); + halrf_wreg(rf, 0x5898, 0xff000000, power_high[1] - power_low[1]); + + halrf_wreg(rf, 0x5848, 0x7fc00000, tssi_cw_rpt_offset[2]); + halrf_wreg(rf, 0x589c, 0x000000ff, power_high[2] - power_low[2]); + + halrf_wreg(rf, 0x5850, 0x7fc00000, tssi_cw_rpt_offset[2]); + halrf_wreg(rf, 0x589c, 0x0000ff00, power_high[2] - power_low[2]); + + halrf_wreg(rf, 0x5858, 0x7fc00000, tssi_cw_rpt_offset[3]); + halrf_wreg(rf, 0x589c, 0x00ff0000, power_high[3] - power_low[3]); + + halrf_wreg(rf, 0x5860, 0x7fc00000, tssi_cw_rpt_offset[3]); + halrf_wreg(rf, 0x589c, 0xff000000, power_high[3] - power_low[3]); + + halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_ONESHOT_STOP); + +} + +void _halrf_tssi_set_rf_gap_tbl_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } +} + +void _halrf_tssi_alignment_default_8852ba(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n", + __func__, channel, path); + + if (path == RF_PATH_A) { + if (channel >= 1 && channel <= 14) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x01cfb3d6); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000074); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else if (channel >= 36 && channel <= 64) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x01e053ee); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else if (channel >= 100 && channel <= 144) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x02807ff9); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000078); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else if (channel >= 149 && channel <= 177) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x025067f1); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } + } else { + if (channel >= 1 && channel <= 14) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x018fa3d2); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000079); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else if (channel >= 36 && channel <= 64) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x01a047eb); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000079); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else if (channel >= 100 && channel <= 144) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x02506ff7); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000076); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else if (channel >= 149 && channel <= 177) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x01a04bf0); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000076); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } + } +} + +void _halrf_tssi_alignment_default_8852bb(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path, bool all) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n", + __func__, channel, path); + + if (path == RF_PATH_A) { + if (channel >= 1 && channel <= 14) { + if (all == true) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00ef77c3); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00ef77c3); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074); + } + } else if (channel >= 36 && channel <= 64) { + if (all == true) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + } + } else if (channel >= 100 && channel <= 144) { + if (all == true) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + } + } else if (channel >= 149 && channel <= 177) { + if (all == true) { + halrf_wreg(rf, 0x5604, 0x80000000, 0x1); + halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1); + halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075); + halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000); + } + } + } else { + if (channel >= 1 && channel <= 14) { + if (all == true) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009f4fbe); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000080); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009f4fbe); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000080); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079); + } + } else if (channel >= 36 && channel <= 64) { + if (all == true) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + } + } else if (channel >= 100 && channel <= 144) { + if (all == true) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x013027e6); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x013027e6); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + } + } else if (channel >= 149 && channel <= 177) { + if (all == true) { + halrf_wreg(rf, 0x7604, 0x80000000, 0x1); + halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721); + halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101); + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000); + } else { + halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da); + halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070); + halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000); + halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000); + } + } + } + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n", + __func__, + 0x5600 + (path << 13), halrf_rreg(rf, 0x5600 + (path << 13), 0xffffffff), + 0x5604 + (path << 13), halrf_rreg(rf, 0x5604 + (path << 13), 0xffffffff), + 0x5630 + (path << 13), halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff), + 0x5634 + (path << 13), halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff), + 0x5638 + (path << 13), halrf_rreg(rf, 0x5638 + (path << 13), 0xffffffff), + 0x563c + (path << 13), halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff), + 0x5640 + (path << 13), halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff), + 0x5644 + (path << 13), halrf_rreg(rf, 0x5644 + (path << 13), 0xffffffff)); +} + +void _halrf_tssi_run_slope_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5820, 0x80000000, 0x0); + halrf_wreg(rf, 0x5820, 0x80000000, 0x1); + } else { + halrf_wreg(rf, 0x7820, 0x80000000, 0x0); + halrf_wreg(rf, 0x7820, 0x80000000, 0x1); + } +} + +void _halrf_tssi_set_tssi_slope_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5814, 0x00000800, 0x1); + halrf_wreg(rf, 0x581c, 0x20000000, 0x1); + halrf_wreg(rf, 0x5814, 0x20000000, 0x1); + } else { + halrf_wreg(rf, 0x7814, 0x00000800, 0x1); + halrf_wreg(rf, 0x781c, 0x20000000, 0x1); + halrf_wreg(rf, 0x7814, 0x20000000, 0x1); + } +} + +void _halrf_tssi_set_tssi_track_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5814, 0x00000800, 0x0); + } else { + halrf_wreg(rf, 0x7814, 0x00000800, 0x0); + } +} + +void _halrf_tssi_set_txagc_offset_mv_avg_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x58e4, 0x000ff800, 0x010); + } else { + halrf_wreg(rf, 0x78e4, 0x000ff800, 0x010); + } +} + +u32 _halrf_tssi_get_cck_efuse_group_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u32 offset_index = 0; + + if (channel >= 1 && channel <= 2) + offset_index = 0; + else if (channel >= 3 && channel <= 5) + offset_index = 1; + else if (channel >= 6 && channel <= 8) + offset_index = 2; + else if (channel >= 9 && channel <= 11) + offset_index = 3; + else if (channel >= 12 && channel <= 13) + offset_index = 4; + else if (channel == 14) + offset_index = 5; + + return offset_index; +} + +u32 _halrf_tssi_get_ofdm_efuse_group_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u32 offset_index = 0; + + if (channel >= 1 && channel <= 2) + offset_index = 0; + else if (channel >= 3 && channel <= 5) + offset_index = 1; + else if (channel >= 6 && channel <= 8) + offset_index = 2; + else if (channel >= 9 && channel <= 11) + offset_index = 3; + else if (channel >= 12 && channel <= 14) + offset_index = 4; + else if (channel >= 36 && channel <= 40) + offset_index = 5; + else if (channel >= 44 && channel <= 48) + offset_index = 6; + else if (channel >= 52 && channel <= 56) + offset_index = 7; + else if (channel >= 60 && channel <= 64) + offset_index = 8; + else if (channel >= 100 && channel <= 104) + offset_index = 9; + else if (channel >= 108 && channel <= 112) + offset_index = 10; + else if (channel >= 116 && channel <= 120) + offset_index = 11; + else if (channel >= 124 && channel <= 128) + offset_index = 12; + else if (channel >= 132 && channel <= 136) + offset_index = 13; + else if (channel >= 140 && channel <= 144) + offset_index = 14; + else if (channel >= 149 && channel <= 153) + offset_index = 15; + else if (channel >= 157 && channel <= 161) + offset_index = 16; + else if (channel >= 165 && channel <= 169) + offset_index = 17; + else if (channel >= 173 && channel <= 177) + offset_index = 18; + else if (channel > 40 && channel < 44) + offset_index = 0x0506; + else if (channel > 48 && channel < 52) + offset_index = 0x0607; + else if (channel > 56 && channel < 60) + offset_index = 0x0708; + else if (channel > 104 && channel < 108) + offset_index = 0x090a; + else if (channel > 112 && channel < 116) + offset_index = 0x0a0b; + else if (channel > 120 && channel < 124) + offset_index = 0x0b0c; + else if (channel > 128 && channel < 132) + offset_index = 0x0c0d; + else if (channel > 136 && channel < 140) + offset_index = 0x0d0e; + else if (channel > 153 && channel < 157) + offset_index = 0x0f10; + else if (channel > 161 && channel < 165) + offset_index = 0x1011; + else if (channel > 169 && channel < 173) + offset_index = 0x1112; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] ======> %s offset_index=0x%x(%d) channel=%d\n", + __func__, offset_index, offset_index, channel); + + return offset_index; +} + +s8 _halrf_tssi_get_ofdm_efuse_tssi_de_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 group_idx; + s8 first_de = 0, second_de = 0, final_de; + + group_idx = _halrf_tssi_get_ofdm_efuse_group_8852b(rf, phy); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s group_idx=0x%x(%d)\n", + __func__, group_idx, group_idx); + + if (group_idx >= 0x0506) { + first_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx >> 8]; + + second_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx & 0xff]; + + final_de = (first_de + second_de) / 2; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] first_de=%d second_de=%d final_de=%d\n", + first_de, second_de, final_de); + } else { + final_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx]; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] final_de=%d\n", + final_de); + } + + return final_de; +} + + +u32 _halrf_tssi_get_tssi_trim_efuse_group_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u32 group_index = 0; + + if (channel >= 1 && channel <= 8) + group_index = 0; + else if (channel >= 9 && channel <= 14) + group_index = 1; + else if (channel >= 36 && channel <= 48) + group_index = 2; + else if (channel >= 52 && channel <= 64) + group_index = 3; + else if (channel >= 100 && channel <= 112) + group_index = 4; + else if (channel >= 116 && channel <= 128) + group_index = 5; + else if (channel >= 132 && channel <= 144) + group_index = 6; + else if (channel >= 149 && channel <= 177) + group_index = 7; +#if 0 + else if (channel > 48 && channel < 52) + group_index = 0x0203; + else if (channel > 120 && channel < 124) + group_index = 0x0405; + else if (channel > 161 && channel < 165) + group_index = 0x0607; +#endif + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] ======> %s offset_index=0x%x(%d) channel=%d\n", + __func__, group_index, group_index, channel); + + return group_index; +} + +s8 _halrf_tssi_get_ofdm_tssi_trim_de_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 group_idx; + s8 first_de = 0, second_de = 0, final_de; + + group_idx = _halrf_tssi_get_tssi_trim_efuse_group_8852b(rf, phy); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] ======> %s group_idx=0x%x(%d)\n", + __func__, group_idx, group_idx); + + if (group_idx >= 0x0203) { + first_de = tssi_info->tssi_trim[path][group_idx >> 8]; + + second_de = tssi_info->tssi_trim[path][group_idx & 0xff]; + + final_de = (first_de + second_de) / 2; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] Trim_first_de=%d Trim_second_de=%d Trim_final_de=%d\n", + first_de, second_de, final_de); + } else { + final_de = tssi_info->tssi_trim[path][group_idx]; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] Trim_final_de=%d\n", + final_de); + } + + return final_de; +} + +void _halrf_tssi_alimentk_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + s16 power_2g[4] = {48, 20, 4, 4}; + s16 power_5g[4] = {48, 20, 4, 4}; + s16 power[4] = {0}; + s32 tssi_alim_offset[4] = {0}; + s32 aliment_diff, tssi_cw_default; + u32 tssi_cw_rpt[4] = {0}, tx_couter, tx_couter_tmp, tmp, retry; + + u32 tssi_trigger[TSSI_PATH_MAX_8852B] = {0x5820, 0x7820}; + u32 tssi_cw_rpt_addr[TSSI_PATH_MAX_8852B] = {0x1c18, 0x3c18}; + + u32 tssi_cw_default_addr[TSSI_PATH_MAX_8852B][4] = + {{0x5634, 0x5630, 0x5630, 0x5630}, + {0x7634, 0x7630, 0x7630, 0x7630}}; + + u32 tssi_cw_default_mask[4] = + {0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff}; + + + //u32 bb_reg[5] = {0x5820, 0x7820, 0x4978, 0x58e4, 0x78e4}; + //u32 bb_reg_backup[5] = {0}; + //u32 backup_num = 5; + + u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4, 0x78e4, + 0x49c0, 0x0d18, 0x0d80}; + u32 bb_reg_backup[8] = {0}; + u32 backup_num = 8; + + u8 i, j, k; + u32 rate = T_HT_MF; + u8 bw = 0, band; + u8 phy_map; + + u32 start_time, finish_time; + + phy_map = (BIT(phy) << 4) | BIT(path); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n", + __func__, channel, path); + + start_time = _os_get_cur_time_us(); + + halrf_hal_bb_backup_info(rf, phy); + + if (channel >= 1 && channel <= 14) { + for (i = 0; i < 4; i++) { + power[i] = power_2g[i]; + } + } else { + for (i = 0; i < 4; i++) { + power[i] = power_5g[i]; + } + } + + if (channel >= 1 && channel <= 14) + band = TSSI_ALIMK_2G; + else if (channel >= 36 && channel <= 64) + band = TSSI_ALIMK_5GL; + else if (channel >= 100 && channel <= 144) + band = TSSI_ALIMK_5GM; + else if (channel >= 149 && channel <= 177) + band = TSSI_ALIMK_5GH; + else + band = TSSI_ALIMK_2G; + + _tssi_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + halrf_wreg(rf, 0x5820, 0x0000f000, 0x8); + halrf_wreg(rf, 0x7820, 0x0000f000, 0x8); + + halrf_wreg(rf, 0x58e4, 0x00003800, 0x2); + halrf_wreg(rf, 0x78e4, 0x00003800, 0x2); + + //halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_START); + for (j = 0; j < 2; j++) { + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0); + halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1); + + tx_couter = halrf_rreg(rf, 0x1a40, 0xffff); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] 0x%x = 0x%08x path=%d\n", + tssi_trigger[path], + halrf_rreg(rf, tssi_trigger[path], 0xffffffff), path); + + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, true); + + //halrf_delay_ms(rf, 10); + + tx_couter_tmp = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] First HWTXcounter=%d path=%d\n", + tx_couter_tmp, path); + + for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) { + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) { + halrf_delay_ms(rf, 1); + retry = 30; + } else { + halrf_delay_us(rf, 30); + retry = 100; + } + + tx_couter_tmp = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n", + k, tx_couter_tmp, path); + + if (k > retry) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n", + k, path); + _tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, false); + return; + } + } + + tssi_cw_rpt[j] = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff); + + _halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, false); + + tx_couter = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] Fianl HWTXcounter = %d path=%d\n", + tx_couter, path); + + } + + for (j = 0; j < 2; j++) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] power[%d]=%d tssi_cw_rpt[%d]=%d\n", + j, power[j], j, tssi_cw_rpt[j]); + } + + tmp = halrf_rreg(rf, tssi_cw_default_addr[path][1], + tssi_cw_default_mask[1]); + + if (tmp & BIT(8)) + tssi_cw_default = tmp | 0xfffffe00; + else + tssi_cw_default = tmp; + + tssi_alim_offset[1] = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) - + tssi_cw_rpt[1] + tssi_cw_default; + + aliment_diff = tssi_alim_offset[1] - tssi_cw_default; + + /*tssi_alim_offset[2]*/ + tmp = halrf_rreg(rf, tssi_cw_default_addr[path][2], + tssi_cw_default_mask[2]); + + if (tmp & BIT(8)) + tssi_cw_default = tmp | 0xfffffe00; + else + tssi_cw_default = tmp; + + tssi_alim_offset[2] = tssi_cw_default + aliment_diff; + + /*tssi_alim_offset[3]*/ + tmp = halrf_rreg(rf, tssi_cw_default_addr[path][3], + tssi_cw_default_mask[3]); + + if (tmp & BIT(8)) + tssi_cw_default = tmp | 0xfffffe00; + else + tssi_cw_default = tmp; + + tssi_alim_offset[3] = tssi_cw_default + aliment_diff; + + if (path == RF_PATH_A) { + tmp = ((tssi_alim_offset[1] & 0x3ff) << 20) | + ((tssi_alim_offset[2] & 0x3ff) << 10) | + (tssi_alim_offset[3] & 0x3ff); + halrf_wreg(rf, 0x5630, 0x3fffffff, tmp); + halrf_wreg(rf, 0x563c, 0x3fffffff, tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", + halrf_rreg(rf, 0x5634, 0x000003ff), + halrf_rreg(rf, 0x5630, 0x3ff00000), + halrf_rreg(rf, 0x5630, 0x000ffc00), + halrf_rreg(rf, 0x5630, 0x000003ff) + ); + } else { + tmp = ((tssi_alim_offset[1] & 0x3ff) << 20) | + ((tssi_alim_offset[2] & 0x3ff) << 10) | + (tssi_alim_offset[3] & 0x3ff); + halrf_wreg(rf, 0x7630, 0x3fffffff, tmp); + halrf_wreg(rf, 0x763c, 0x3fffffff, tmp); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", + halrf_rreg(rf, 0x7634, 0x000003ff), + halrf_rreg(rf, 0x7630, 0x3ff00000), + halrf_rreg(rf, 0x7630, 0x000ffc00), + halrf_rreg(rf, 0x7630, 0x000003ff) + ); + } + + tssi_info->alignment_done[path][band] = true; + tssi_info->alignment_value[path][band][0] = halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff); + tssi_info->alignment_value[path][band][1] = halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff); + tssi_info->alignment_value[path][band][2] = halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff); + tssi_info->alignment_value[path][band][3] = halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n", + path, band, 0x5630 + (path << 13), tssi_info->alignment_value[path][band][0]); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n", + path, band, 0x5634 + (path << 13), tssi_info->alignment_value[path][band][1]); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", + path, band, 0x563c + (path << 13), tssi_info->alignment_value[path][band][2]); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", + path, band, 0x5640 + (path << 13), tssi_info->alignment_value[path][band][3]); + + + _tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + halrf_hal_bb_restore_info(rf, phy); + + if (rf->phl_com->drv_mode != RTW_DRV_MODE_MP) + halrf_tx_mode_switch(rf, phy, 0); + + finish_time = _os_get_cur_time_us(); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] %s processing time = %d.%dms\n", + __func__, + HALRF_ABS(finish_time, start_time) / 1000, + HALRF_ABS(finish_time, start_time) % 1000); +} + +void _halrf_tssi_alimentk_done_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u8 band; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d path=%d\n", __func__, phy, path); + + if (channel >= 1 && channel <= 14) + band = TSSI_ALIMK_2G; + else if (channel >= 36 && channel <= 64) + band = TSSI_ALIMK_5GL; + else if (channel >= 100 && channel <= 144) + band = TSSI_ALIMK_5GM; + else if (channel >= 149 && channel <= 177) + band = TSSI_ALIMK_5GH; + else + band = TSSI_ALIMK_2G; + + if (tssi_info->alignment_done[path][band] == true) { + halrf_wreg(rf, 0x5630 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][0]); + halrf_wreg(rf, 0x5634 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][1]); + halrf_wreg(rf, 0x563c + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][2]); + halrf_wreg(rf, 0x5640 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][3]); + } + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n", + 0x5600 + (path << 13), halrf_rreg(rf, 0x5600 + (path << 13), 0xffffffff), + 0x5604 + (path << 13), halrf_rreg(rf, 0x5604 + (path << 13), 0xffffffff), + 0x5630 + (path << 13), halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff), + 0x5634 + (path << 13), halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff), + 0x5638 + (path << 13), halrf_rreg(rf, 0x5638 + (path << 13), 0xffffffff), + 0x563c + (path << 13), halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff), + 0x5640 + (path << 13), halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff), + 0x5644 + (path << 13), halrf_rreg(rf, 0x5644 + (path << 13), 0xffffffff)); +} + +void halrf_tssi_backup_txagc_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool enable) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u8 bw = rf->hal_com->band[phy].cur_chandef.bw; + s8 power, power_tmp; + s16 xdbm; + u32 i, j, tx_couter = 0; + u8 ch_idx = _halrf_ch_to_idx(rf, channel); + u8 channel_tmp; + + //u32 bb_reg[4] = {0x5820, 0x7820, 0x58e4, 0x78e4}; + //u32 bb_reg_backup[4] = {0}; + //u32 backup_num = 4; + + u32 bb_reg[7] = {0x5820, 0x7820, 0x58e4, 0x78e4, + 0x49c0, 0x0d18, 0x0d80}; + u32 bb_reg_backup[7] = {0}; + u32 backup_num = 7; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d enable=%d\n", __func__, phy, enable); + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s phy=%d rf->phl_com->drv_mode == RTW_DRV_MODE_MP return!!!\n", + __func__, phy); + return; + } + + if (enable == false) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s phy=%d enable=%d return!!!\n", + __func__, phy, enable); + return; + } + + if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n", + __func__, phy); + return; + } + + if (tssi_info->check_backup_txagc[ch_idx] == true) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s check_backup_txagc[%d]==true Backup 0x1c60=0x%x 0x3c60=0x%x channel=%d return!!!\n", + __func__, ch_idx, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx], + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx], + channel); + + halrf_wreg(rf, 0x5818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]); + halrf_wreg(rf, 0x7818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]); + + halrf_wreg(rf, 0x5818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x5818 , 0x10000000, 0x1); + + halrf_wreg(rf, 0x7818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x7818 , 0x10000000, 0x1); + + return; + } + + halrf_hal_bb_backup_info(rf, phy); + + _tssi_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + halrf_wreg(rf, 0x5820, 0x0000f000, 0x8); + halrf_wreg(rf, 0x7820, 0x0000f000, 0x8); + + halrf_wreg(rf, 0x58e4, 0x00003800, 0x2); + halrf_wreg(rf, 0x78e4, 0x00003800, 0x2); + + if (bw == CHANNEL_WIDTH_40) + channel_tmp = channel - 2; + else if (bw == CHANNEL_WIDTH_80) + channel_tmp = channel - 6; + else + channel_tmp = channel; + + power = halrf_get_power_limit(rf, phy, RF_PATH_A, + RTW_DATA_RATE_MCS0, CHANNEL_WIDTH_20, + PW_LMT_NONBF, PW_LMT_PH_1T, channel_tmp); + + if (power > 17 * 4) + power_tmp = 17 * 4; + else + power_tmp = power; + + xdbm = power_tmp * 100 / 4; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d limit_table=%d power_tmp=%d xdbm=%d\n", + __func__, phy, power, power_tmp, xdbm); + + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START); + halrf_tmac_tx_pause(rf, phy, true); + + /*Path A*/ + tx_couter= halrf_rreg(rf, 0x1a40, 0xffff); + + _halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_AB, 1000, 100, power_tmp, T_HT_MF, 0, true); + +#if 0 + /*Path B*/ + tx_couter[RF_PATH_B] = halrf_rreg(rf, 0x1a40, 0xffff); + + _halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_B, 1000, 100, xdbm, T_HT_MF, 0, true); + halrf_delay_ms(rf, 15); + _halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_B, 1000, 100, xdbm, T_HT_MF, 0, false); +#endif + + for (i = 0; i < 6; i++) { + for (j = 0; j < 300; j++) + halrf_delay_us(rf, 10); + + if (halrf_rreg(rf, 0x1c60, 0xff000000) != 0x0 && + halrf_rreg(rf, 0x3c60, 0xff000000) != 0x0) { + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx] = + halrf_rreg(rf, 0x1c60, 0xff000000); + + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx] = + halrf_rreg(rf, 0x3c60, 0xff000000); + + tssi_info->check_backup_txagc[ch_idx] = true; + break; + } + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "Get %d times 0x1c60=0x%x 0x3c60=0x%x\n", + i, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx], + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]); + } + + tssi_info->backup_txagc_oft_ther[RF_PATH_A][ch_idx] = + halrf_get_thermal_8852b(rf, RF_PATH_A); + + tssi_info->backup_txagc_oft_ther[RF_PATH_B][ch_idx] = + halrf_get_thermal_8852b(rf, RF_PATH_B); + + _halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_AB, 1000, 100, power_tmp, T_HT_MF, 0, false); + + tx_couter = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s tx couter=%d\n", + __func__, tx_couter); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "Backup TSSI TXAGC Offset ch_idx=%d 0x1c60=0x%x therA=0x%x channel=%d\n", + ch_idx, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx], + tssi_info->backup_txagc_oft_ther[RF_PATH_A][ch_idx], + channel); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "Backup TSSI TXAGC Offset ch_idx=%d 0x3c60=0x%x therB=0x%x channel=%d\n", + ch_idx, + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx], + tssi_info->backup_txagc_oft_ther[RF_PATH_B][ch_idx], + channel); + + halrf_wreg(rf, 0x5818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]); + halrf_wreg(rf, 0x7818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]); + + halrf_wreg(rf, 0x5818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x5818 , 0x10000000, 0x1); + + halrf_wreg(rf, 0x7818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x7818 , 0x10000000, 0x1); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", + __func__, + halrf_rreg(rf, 0x5818, 0x000000ff), + halrf_rreg(rf, 0x7818, 0x000000ff)); + + _tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + halrf_hal_bb_restore_info(rf, phy); + halrf_tx_mode_switch(rf, phy, 0); + + halrf_tmac_tx_pause(rf, phy, false); + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP); + + //_tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, backup_num); +} + +void halrf_do_tssi_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u8 ch_idx = _halrf_ch_to_idx(rf, channel); + u32 i; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d ch=%d ch_idx=%d\n", + __func__, phy, channel, ch_idx); + + tssi_info->check_backup_txagc[ch_idx] = false; + + halrf_tssi_disable_8852b(rf, phy); + + for (i = RF_PATH_A; i < TSSI_PATH_MAX_8852B; i++) { + _halrf_tssi_rf_setting_8852b(rf, phy, i); + _halrf_tssi_set_sys_8852b(rf, phy, i); + _halrf_tssi_ini_txpwr_ctrl_bb_8852b(rf, phy, i); + _halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(rf, phy, i); + _halrf_tssi_set_dck_8852b(rf, phy, i); + //_halrf_tssi_set_bbgain_split_8852b(rf, phy, i); + _halrf_tssi_set_tmeter_tbl_8852b(rf, phy, i); + _halrf_tssi_set_dac_gain_tbl_8852b(rf, phy, i); + _halrf_tssi_slope_cal_org_8852b(rf, phy, i); + _halrf_tssi_set_rf_gap_tbl_8852b(rf, phy, i); + + if (rf->hal_com->cv == CAV) + _halrf_tssi_alignment_default_8852ba(rf, phy, i); + else + _halrf_tssi_alignment_default_8852bb(rf, phy, i, true); + + _halrf_tssi_set_tssi_slope_8852b(rf, phy, i); + + //halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START); + //halrf_tmac_tx_pause(rf, phy, true); + + //if (rfe_type <= 50) + //_halrf_tssi_slope_cal_8852b(rf, phy, i); + + //halrf_tmac_tx_pause(rf, phy, false); + //halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP); + + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START); + halrf_tmac_tx_pause(rf, phy, true); + _halrf_tssi_alimentk_8852b(rf, phy, i); + halrf_tmac_tx_pause(rf, phy, false); + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP); + } + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) { + if (tssi_info->tssi_type == TSSI_ON || tssi_info->tssi_type == TSSI_CAL) { + halrf_tssi_enable_8852b(rf, phy); + halrf_tssi_set_efuse_to_de_8852b(rf, phy); + } else + halrf_tssi_disable_8852b(rf, phy); + + } else { + if (rf->support_ability & HAL_RF_TX_PWR_TRACK) { + halrf_tssi_enable_8852b(rf, phy); + halrf_tssi_set_efuse_to_de_8852b(rf, phy); + halrf_tssi_backup_txagc_8852b(rf, phy, true); + } + } + + tssi_info->do_tssi = true; +} + +void halrf_do_tssi_scan_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 i; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + u8 band; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d channel=%d\n", + __func__, phy, channel); + + if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n", + __func__, phy); + return; + } + + if (channel >= 1 && channel <= 14) + band = TSSI_ALIMK_2G; + else if (channel >= 36 && channel <= 64) + band = TSSI_ALIMK_5GL; + else if (channel >= 100 && channel <= 144) + band = TSSI_ALIMK_5GM; + else if (channel >= 149 && channel <= 177) + band = TSSI_ALIMK_5GH; + else + band = TSSI_ALIMK_2G; + + halrf_write_fwofld_start(rf); + + halrf_tssi_disable_8852b(rf, phy); + + for (i = RF_PATH_A; i < TSSI_PATH_MAX_8852B; i++) { + _halrf_tssi_rf_setting_8852b(rf, phy, i); + _halrf_tssi_set_sys_8852b(rf, phy, i); + //_halrf_tssi_ini_txpwr_ctrl_bb_8852b(rf, phy, i); + //_halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(rf, phy, i); + //_halrf_tssi_set_dck_8852b(rf, phy, i); + //_halrf_tssi_set_bbgain_split_8852b(rf, phy, i); + _halrf_tssi_set_tmeter_tbl_8852b(rf, phy, i); + //_halrf_tssi_set_dac_gain_tbl_8852b(rf, phy, i); + //_halrf_tssi_slope_cal_org_8852b(rf, phy, i); + //_halrf_tssi_set_rf_gap_tbl_8852b(rf, phy, i); + //_halrf_tssi_set_tssi_slope_8852b(rf, phy, i); + + if (tssi_info->alignment_done[i][band] == true) + _halrf_tssi_alimentk_done_8852b(rf, phy, i); + else { + if (rf->hal_com->cv == CAV) + _halrf_tssi_alignment_default_8852ba(rf, phy, i); + else + _halrf_tssi_alignment_default_8852bb(rf, phy, i, false); + } + } + + halrf_tssi_enable_8852b(rf, phy); + halrf_tssi_set_efuse_to_de_8852b(rf, phy); + + halrf_write_fwofld_end(rf); +} + +void halrf_tssi_get_efuse_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + s8 de_offset = 0; + u32 i, j; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + /*path s0*/ + for (i = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6; i++, j++) { + halrf_efuse_get_info(rf, i, &de_offset, 1); + tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j] = de_offset; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n", + i, tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j]); + } + + for (i = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14; i++, j++) { + halrf_efuse_get_info(rf, i, &de_offset, 1); + tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j] = de_offset; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n", + i, tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j]); + } + + /*path s1*/ + for (i = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6; i++, j++) { + halrf_efuse_get_info(rf, i, &de_offset, 1); + tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j] = de_offset; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n", + i, tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j]); + } + + for (i = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14; i++, j++) { + halrf_efuse_get_info(rf, i, &de_offset, 1); + tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j] = de_offset; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n", + i, tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j]); + } +} + +bool halrf_tssi_check_efuse_data_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 i, j, countr = 0; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + halrf_tssi_get_efuse_8852b(rf, phy); + + /*path s0*/ + for (i = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6; i++, j++) { + if ((tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j] & 0xff) == 0xff) + countr++; + } + + for (i = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14; i++, j++) { + if ((tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j] & 0xff) == 0xff) + countr++; + } + + /*path s1*/ + for (i = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6; i++, j++) { + if ((tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j] & 0xff) == 0xff) + countr++; + } + + for (i = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14; i++, j++) { + if ((tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j] & 0xff) == 0xff) + countr++; + } + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] countr == %d\n", countr); + + if (countr == 50) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse all are 0xff, return false!!!\n"); + return false; + } + + return true; +} + +void halrf_set_tssi_de_for_tx_verify_8852b(struct rf_info *rf, + enum phl_phy_idx phy, u32 tssi_de, u8 path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 tssi_de_tmp; + s32 s_tssi_de, tmp; + s8 tssi_trim; + u32 addr_cck_long[2] = {0x5858, 0x7858}; + u32 addr_cck_short[2] = {0x5860, 0x7860}; + u32 addr_cck_bitmask[2] = {0x003ff000, 0x003ff000}; + u32 addr_mcs_20m[2] = {0x5838, 0x7838}; + u32 addr_mcs_40m[2] = {0x5840, 0x7840}; + u32 addr_mcs_80m[2] = {0x5848, 0x7848}; + u32 addr_mcs_80m_80m[2] = {0x5850, 0x7850}; + u32 addr_mcs_5m[2] = {0x5828, 0x7828}; + u32 addr_mcs_10m[2] = {0x5830, 0x7830}; + u32 addr_mcs_bitmask[2] = {0x003ff000, 0x003ff000}; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d tssi_de=0x%x path=%d\n", + __func__, phy, tssi_de, path); + + if (tssi_de & BIT(7)) + s_tssi_de = tssi_de | 0xffffff00; + else + s_tssi_de = tssi_de; + + tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, path); + tmp = s_tssi_de + tssi_trim; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tmp(%d) = s_tssi_de(%d) + tssi_trim(%d)\n", + tmp, s_tssi_de, tssi_trim); + + tssi_de_tmp = tmp & 0x3ff; + + halrf_wreg(rf, addr_cck_long[path], addr_cck_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_cck_short[path], addr_cck_bitmask[path], tssi_de_tmp); + + halrf_wreg(rf, addr_mcs_20m[path], addr_mcs_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_mcs_40m[path], addr_mcs_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_mcs_80m[path], addr_mcs_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_mcs_80m_80m[path], addr_mcs_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_mcs_5m[path], addr_mcs_bitmask[path], tssi_de_tmp); + halrf_wreg(rf, addr_mcs_10m[path], addr_mcs_bitmask[path], tssi_de_tmp); + tssi_info->tssi_de[path] = tmp; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x%x[21:12]=0x%x 0x%x[21:12]=0x%x path=%d\n", + addr_mcs_20m[path], + halrf_rreg(rf, addr_mcs_20m[path], 0x003ff000), + addr_cck_long[path], + halrf_rreg(rf, addr_cck_long[path], 0x003ff000), + path); + + /*Save TSSI data for WINCLI*/ + tssi_info->curr_tssi_cck_de[path] = + (s8)(halrf_rreg(rf, addr_cck_long[path], addr_cck_bitmask[path]) & 0xff); + tssi_info->curr_tssi_ofdm_de[path] = + (s8)(halrf_rreg(rf, addr_mcs_20m[path], addr_mcs_bitmask[path]) & 0xff); + tssi_info->curr_tssi_efuse_cck_de[path] = (s8)s_tssi_de; + tssi_info->curr_tssi_efuse_ofdm_de[path] = (s8)s_tssi_de; + tssi_info->curr_tssi_trim_de[path] = tssi_trim; +} + +void halrf_set_tssi_de_offset_8852b(struct rf_info *rf, + enum phl_phy_idx phy, u32 tssi_de_offset, u8 path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + s32 tssi_tmp, s_tssi_de_offset; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d tssi_de_offset=0x%x path=%d\n", + __func__, phy, tssi_de_offset, path); + + if (tssi_de_offset & BIT(7)) + s_tssi_de_offset = tssi_de_offset | 0xffffff00; + else + s_tssi_de_offset = tssi_de_offset; + + s_tssi_de_offset = s_tssi_de_offset * -1; + + if (path == RF_PATH_A) { + tssi_tmp = tssi_info->tssi_de[RF_PATH_A] + s_tssi_de_offset; + tssi_tmp = tssi_tmp & 0x3ff; + halrf_wreg(rf, 0x5838, 0x003ff000, tssi_tmp); /*20M*/ + halrf_wreg(rf, 0x5858, 0x003ff000, tssi_tmp); /*CCK long*/ + halrf_wreg(rf, 0x5828, 0x003ff000, tssi_tmp); /*5M*/ + halrf_wreg(rf, 0x5830, 0x003ff000, tssi_tmp); /*10M*/ + halrf_wreg(rf, 0x5840, 0x003ff000, tssi_tmp); /*40M*/ + halrf_wreg(rf, 0x5848, 0x003ff000, tssi_tmp); /*80M*/ + halrf_wreg(rf, 0x5850, 0x003ff000, tssi_tmp); /*80M+80M*/ + halrf_wreg(rf, 0x5860, 0x003ff000, tssi_tmp); /*CCK short*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tssi_tmp(%d) = tssi_info->tssi_de[RF_PATH_A](%d) + s_tssi_de_offset(%d) path=%d\n", + tssi_tmp, tssi_info->tssi_de[RF_PATH_A], + s_tssi_de_offset, path); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x path=%d\n", + halrf_rreg(rf, 0x5838, 0x003ff000), + halrf_rreg(rf, 0x5858, 0x003ff000), + path); + } else { + tssi_tmp = tssi_info->tssi_de[RF_PATH_B] + s_tssi_de_offset; + tssi_tmp = tssi_tmp & 0x3ff; + halrf_wreg(rf, 0x7838, 0x003ff000, tssi_tmp); /*20M*/ + halrf_wreg(rf, 0x7858, 0x003ff000, tssi_tmp); /*CCK long*/ + halrf_wreg(rf, 0x7828, 0x003ff000, tssi_tmp); /*5M*/ + halrf_wreg(rf, 0x7830, 0x003ff000, tssi_tmp); /*10M*/ + halrf_wreg(rf, 0x7840, 0x003ff000, tssi_tmp); /*40M*/ + halrf_wreg(rf, 0x7848, 0x003ff000, tssi_tmp); /*80M*/ + halrf_wreg(rf, 0x7850, 0x003ff000, tssi_tmp); /*80M+80M*/ + halrf_wreg(rf, 0x7860, 0x003ff000, tssi_tmp); /*CCK short*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tssi_tmp(%d) = tssi_info->tssi_de[RF_PATH_B](%d) + s_tssi_de_offset(%d) path=%d\n", + tssi_tmp, tssi_info->tssi_de[RF_PATH_B], + s_tssi_de_offset, path); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x path=%d\n", + halrf_rreg(rf, 0x7838, 0x003ff000), + halrf_rreg(rf, 0x7858, 0x003ff000), + path); + } +} + +void halrf_set_tssi_de_offset_zero_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + halrf_wreg(rf, 0x5838, 0x003ff000, 0x0); /*20M*/ + halrf_wreg(rf, 0x5858, 0x003ff000, 0x0); /*CCK long*/ + halrf_wreg(rf, 0x5828, 0x003ff000, 0x0); /*5M*/ + halrf_wreg(rf, 0x5830, 0x003ff000, 0x0); /*10M*/ + halrf_wreg(rf, 0x5840, 0x003ff000, 0x0); /*40M*/ + halrf_wreg(rf, 0x5848, 0x003ff000, 0x0); /*80M*/ + halrf_wreg(rf, 0x5850, 0x003ff000, 0x0); /*80M+80M*/ + halrf_wreg(rf, 0x5860, 0x003ff000, 0x0); /*CCK short*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE Zero 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x\n", + halrf_rreg(rf, 0x5838, 0x003ff000), + halrf_rreg(rf, 0x5858, 0x003ff000)); + + halrf_wreg(rf, 0x7838, 0x003ff000, 0x0); /*20M*/ + halrf_wreg(rf, 0x7858, 0x003ff000, 0x0); /*CCK long*/ + halrf_wreg(rf, 0x7828, 0x003ff000, 0x0); /*5M*/ + halrf_wreg(rf, 0x7830, 0x003ff000, 0x0); /*10M*/ + halrf_wreg(rf, 0x7840, 0x003ff000, 0x0); /*40M*/ + halrf_wreg(rf, 0x7848, 0x003ff000, 0x0); /*80M*/ + halrf_wreg(rf, 0x7850, 0x003ff000, 0x0); /*80M+80M*/ + halrf_wreg(rf, 0x7860, 0x003ff000, 0x0); /*CCK short*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE Zero 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x\n", + halrf_rreg(rf, 0x7838, 0x003ff000), + halrf_rreg(rf, 0x7858, 0x003ff000)); +} + +void halrf_tssi_enable_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 i; + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s\n", __func__); + + for (i = 0; i < TSSI_PATH_MAX_8852B; i++) { + /*_halrf_tssi_set_tssi_slope_8852b(rf, phy, i);*/ + _halrf_tssi_set_tssi_track_8852b(rf, phy, i); + _halrf_tssi_set_txagc_offset_mv_avg_8852b(rf, phy, i); + + if (i == RF_PATH_A) { + halrf_wreg(rf, 0x58e4, 0x00004000, 0x0); + halrf_wreg(rf, 0x5820, 0x80000000, 0x0); + halrf_wreg(rf, 0x5820, 0x80000000, 0x1); + halrf_wrf(rf, i, 0x10055, 0x00080, 0x1); + halrf_wreg(rf, 0x5818, 0x18000000, 0x3); + + rf->is_tssi_mode[RF_PATH_A] = true; + } else { + halrf_wreg(rf, 0x78e4, 0x00004000, 0x0); + halrf_wreg(rf, 0x7820, 0x80000000, 0x0); + halrf_wreg(rf, 0x7820, 0x80000000, 0x1); + halrf_wrf(rf, i, 0x10055, 0x00080, 0x1); + halrf_wreg(rf, 0x7818, 0x18000000, 0x3); + + rf->is_tssi_mode[RF_PATH_B] = true; + } + } +} + +void halrf_tssi_disable_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + +#if 0 + halrf_wreg(rf, 0x5820, 0x80000000, 0x0); + + /*Request by Jerry for DPK*/ + halrf_wreg(rf, 0x5818, 0x18000000, 0x1); + + halrf_wreg(rf, 0x7820, 0x80000000, 0x0); + + /*Request by Jerry for DPK*/ + halrf_wreg(rf, 0x7818, 0x18000000, 0x1); + + /*Path A*/ + halrf_wreg(rf, 0x5818, 0x000000ff, 0x0); /*TXAGC_OFFSET init = 0*/ + halrf_wreg(rf, 0x58dc, 0x80000000, 0x0); /*rst release*/ + halrf_wreg(rf, 0x58dc, 0x80000000, 0x1); /*rst*/ + + /*Path B*/ + halrf_wreg(rf, 0x7818, 0x000000ff, 0x0); /*TXAGC_OFFSET init = 0*/ + halrf_wreg(rf, 0x78dc, 0x80000000, 0x0); /*rst release*/ + halrf_wreg(rf, 0x78dc, 0x80000000, 0x1); /*rst*/ +#endif + + halrf_wreg(rf, 0x5820, 0x80000000, 0x0); + halrf_wreg(rf, 0x5818, 0x18000000, 0x1); + halrf_wreg(rf, 0x58e4, 0x00004000, 0x1); + + halrf_wreg(rf, 0x7820, 0x80000000, 0x0); + halrf_wreg(rf, 0x7818, 0x18000000, 0x1); + halrf_wreg(rf, 0x78e4, 0x00004000, 0x1); + + rf->is_tssi_mode[RF_PATH_A] = false; + rf->is_tssi_mode[RF_PATH_B] = false; +} + +s32 halrf_get_online_tssi_de_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path, s32 dbm, s32 puot) +{ + s32 de = ((puot - dbm) * 8) / 100; + s32 s_tssi_offset; + u32 tssi_offset; + s8 tssi_trim; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d\n", __func__, phy_idx); + + if (path == RF_PATH_A) { + tssi_offset = halrf_rreg(rf, 0x5838, 0x003ff000); + /*tssi_offset = halrf_rreg(rf, 0x5858, 0x003ff000);*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x path=%d\n", + halrf_rreg(rf, 0x5838, 0x003ff000), + halrf_rreg(rf, 0x5858, 0x003ff000), + path); + } else { + tssi_offset = halrf_rreg(rf, 0x7838, 0x003ff000); + /*tssi_offset = halrf_rreg(rf, 0x7858, 0x003ff000);*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x path=%d\n", + halrf_rreg(rf, 0x7838, 0x003ff000), + halrf_rreg(rf, 0x7858, 0x003ff000), + path); + } + + if (tssi_offset & BIT(9)) + s_tssi_offset = tssi_offset | 0xfffffc00; + else + s_tssi_offset = tssi_offset; + + tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy_idx, path); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] de(%d) = de(%d) + s_tssi_offset(%d) - tssi_trim(%d) path=%d\n", + (de + s_tssi_offset - tssi_trim), de, s_tssi_offset, tssi_trim, path); + + de = de + s_tssi_offset - tssi_trim; + + de = de & 0xff; + + return de; +} + +void halrf_tssi_set_efuse_to_de_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + + u32 addr_cck_long[2] = {0x5858, 0x7858}; + u32 addr_cck_short[2] = {0x5860, 0x7860}; + u32 addr_cck_bitmask[2] = {0x003ff000, 0x003ff000}; + u32 addr_mcs_20m[2] = {0x5838, 0x7838}; + u32 addr_mcs_40m[2] = {0x5840, 0x7840}; + u32 addr_mcs_80m[2] = {0x5848, 0x7848}; + u32 addr_mcs_80m_80m[2] = {0x5850, 0x7850}; + u32 addr_mcs_5m[2] = {0x5828, 0x7828}; + u32 addr_mcs_10m[2] = {0x5830, 0x7830}; + u32 addr_mcs_bitmask[2] = {0x003ff000, 0x003ff000}; + u32 i, group_idx; + s32 tmp; + s8 ofmd_de, tssi_trim; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__); + + if (tssi_info->tssi_type == TSSI_CAL) { + /*halrf_set_tssi_de_offset_zero_8852b(rf, phy);*/ + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s TSSI_CAL mode set TSSI Trim !!!\n", __func__); + + for (i = 0; i < TSSI_PATH_MAX_8852B; i++) { + tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i); + + tmp = (s32)tssi_trim; + + halrf_wreg(rf, addr_cck_long[i], addr_cck_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_cck_short[i], addr_cck_bitmask[i], + (u32)(tmp & 0x3ff)); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] TSSI_CAL Set TSSI Trim CCK DE 0x%x[21:12]=0x%x\n", + addr_cck_long[i], halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i])); + + halrf_wreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_40m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_80m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_80m_80m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_5m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_10m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] TSSI_CAL Set TSSI Trim MCS DE 0x%x[21:12]=0x%x\n", + addr_mcs_20m[i], halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i])); + + /*Save TSSI data for WINCLI*/ + tssi_info->curr_tssi_cck_de[i] = + (s8)(halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]) & 0xff); + tssi_info->curr_tssi_ofdm_de[i] = + (s8)(halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]) & 0xff); + tssi_info->curr_tssi_efuse_cck_de[i] = 0; + tssi_info->curr_tssi_efuse_ofdm_de[i] = 0; + tssi_info->curr_tssi_trim_de[i] = tssi_trim; + } + return; + } + + for (i = 0; i < TSSI_PATH_MAX_8852B; i++) { + /*CCK*/ + group_idx = _halrf_tssi_get_cck_efuse_group_8852b(rf, phy); + tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i); + + tmp = tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx] + + tssi_trim; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] tmp(0x%x) = tssi_efuse_cck[%d](0x%x) + tssi_trim(0x%x) path=%d\n", + tmp, group_idx, tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx], + tssi_trim, i); + + halrf_wreg(rf, addr_cck_long[i], addr_cck_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_cck_short[i], addr_cck_bitmask[i], + (u32)(tmp & 0x3ff)); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", + addr_cck_long[i], halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i])); + + /*OFDM*/ + ofmd_de = _halrf_tssi_get_ofdm_efuse_tssi_de_8852b(rf, phy, i); + tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i); + tmp = ofmd_de + tssi_trim; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "[TSSI] tmp(0x%x) = tssi_efuse_ofdm(0x%x) + tssi_trim(0x%x) path=%d\n", + tmp, ofmd_de, tssi_trim, i); + + halrf_wreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_40m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_80m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_80m_80m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_5m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + halrf_wreg(rf, addr_mcs_10m[i], addr_mcs_bitmask[i], + (u32)(tmp & 0x3ff)); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", + addr_mcs_20m[i], halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i])); + + /*Save TSSI data for WINCLI*/ + tssi_info->curr_tssi_cck_de[i] = + (s8)(halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]) & 0xff); + tssi_info->curr_tssi_ofdm_de[i] = + (s8)(halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]) & 0xff); + tssi_info->curr_tssi_efuse_cck_de[i] = tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx]; + tssi_info->curr_tssi_efuse_ofdm_de[i] = ofmd_de; + tssi_info->curr_tssi_trim_de[i] = tssi_trim; + } + +} + +void halrf_tssi_default_txagc_8852b(struct rf_info *rf, + enum phl_phy_idx phy, bool enable) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u8 ch_idx = _halrf_ch_to_idx(rf, channel); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s ch=%d\n", __func__, channel); + + if (enable == true) { + /*SCAN_START*/ + tssi_info->start_time = _os_get_cur_time_us(); + if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n", + __func__, phy); + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s SCAN_START\n", __func__); + halrf_do_tssi_8852b(rf, phy); + return; + } + } else { + /*SCAN_END*/ + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", + __func__, + halrf_rreg(rf, 0x5818, 0x000000ff), + halrf_rreg(rf, 0x7818, 0x000000ff)); + + halrf_wreg(rf, 0x5818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]); + halrf_wreg(rf, 0x7818, 0x000000ff, + tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]); + + halrf_wreg(rf, 0x5818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x5818 , 0x10000000, 0x1); + + halrf_wreg(rf, 0x7818 , 0x10000000, 0x0); + halrf_wreg(rf, 0x7818 , 0x10000000, 0x1); + + _halrf_tssi_alimentk_done_8852b(rf, phy, RF_PATH_A); + _halrf_tssi_alimentk_done_8852b(rf, phy, RF_PATH_B); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", + __func__, + halrf_rreg(rf, 0x5818, 0x000000ff), + halrf_rreg(rf, 0x7818, 0x000000ff)); + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s SCAN_END\n", __func__); + + tssi_info->finish_time = _os_get_cur_time_us(); + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] %s processing time = %d.%dms\n", + __func__, + HALRF_ABS(tssi_info->finish_time, tssi_info->start_time) / 1000, + HALRF_ABS(tssi_info->finish_time, tssi_info->start_time) % 1000); + } +} + +void halrf_tssi_scan_ch_8852b(struct rf_info *rf, enum rf_path path) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 tssi_trk_man[2] = {0x5818, 0x7818}; + u32 tssi_en[2] = {0x5820, 0x7820}; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u8 ch_idx = _halrf_ch_to_idx(rf, channel); + u8 band; + + if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s rf->is_tssi_mode[A&B] != true return!!!\n", + __func__); + return; + } + + if (channel >= 1 && channel <= 14) + band = TSSI_ALIMK_2G; + else if (channel >= 36 && channel <= 64) + band = TSSI_ALIMK_5GL; + else if (channel >= 100 && channel <= 144) + band = TSSI_ALIMK_5GM; + else if (channel >= 149 && channel <= 177) + band = TSSI_ALIMK_5GH; + else + band = TSSI_ALIMK_2G; + + if (!(rf->phl_com->drv_mode == RTW_DRV_MODE_MP)) { + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, + "======>%s Restore_txagc_offset[%d][%d]=0x%x ther=0x%x channel=%d path=%d\n", + __func__, path, ch_idx, tssi_info->backup_txagc_offset[path][ch_idx], + tssi_info->backup_txagc_oft_ther[path][ch_idx], channel, path); + + if (tssi_info->alignment_done[path][band] == true) + _halrf_tssi_alimentk_done_8852b(rf, 0, path); + else { + if (rf->hal_com->cv == CAV) + _halrf_tssi_alignment_default_8852ba(rf, 0, path); + else + _halrf_tssi_alignment_default_8852bb(rf, 0, path, false); + } + + halrf_wreg(rf, tssi_en[path], BIT(31), 0x0); + halrf_wreg(rf, tssi_en[path], BIT(31), 0x1); + halrf_wreg(rf, tssi_trk_man[path], 0x000000ff, + tssi_info->backup_txagc_offset[path][ch_idx]); + halrf_wreg(rf, tssi_trk_man[path], BIT(28), 0x0); + halrf_wreg(rf, tssi_trk_man[path], BIT(28), 0x1); + } +} + +u32 halrf_tssi_get_final_8852b(struct rf_info *rf, enum rf_path path) +{ + u32 i; + + RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", + __func__, path); + + if (path == RF_PATH_A) { + halrf_wreg(rf, 0x5818, 0x10000000, 0x0); + halrf_wreg(rf, 0x5820, 0x80000000, 0x0); + halrf_wreg(rf, 0x5820, 0x80000000, 0x1); + halrf_wreg(rf, 0x58b4, 0x0000001f, 0x7); + for (i = 0; i < 300; i ++) + halrf_delay_us(rf, 10); + return halrf_rreg(rf, 0x1c00, 0x0003fe00); + } else { + halrf_wreg(rf, 0x7818, 0x10000000, 0x0); + halrf_wreg(rf, 0x7820, 0x80000000, 0x0); + halrf_wreg(rf, 0x7820, 0x80000000, 0x1); + halrf_wreg(rf, 0x78b4, 0x0000001f, 0x7); + for (i = 0; i < 300; i ++) + halrf_delay_us(rf, 10); + return halrf_rreg(rf, 0x3c00, 0x0003fe00); + } +} + +void halrf_get_tssi_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len) +{ + struct halrf_tssi_info *tssi_info = &rf->tssi; + u32 tmp, tmp1, pg_ther, cur_ther; + s32 delta_tssi; + s32 diff_ther; + s32 int_tmp[TSSI_PATH_MAX_8852B], float_tmp[TSSI_PATH_MAX_8852B]; + s8 txagc_offset[TSSI_PATH_MAX_8852B] = {0}; + + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %x\n", + "RF Para Ver", halrf_rrf(rf, RF_PATH_A, 0x9f, 0xfff)); + + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = 0x%x / 0x%x\n", + "TSSI DCK A / B", halrf_rreg(rf, 0x1c04, 0x00FFF000), + halrf_rreg(rf, 0x3c04, 0x00FFF000)); + + tmp = halrf_rreg(rf, 0x1c78, 0x1ff); + tmp1 = halrf_rreg(rf, 0x3c78, 0x1ff); + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d.%d / %d.%d\n", + "T-MAC xdbm A / B", + tmp / 4, tmp * 100 / 4 % 100, + tmp1 / 4, tmp1 * 100 / 4 % 100); + + halrf_wreg(rf, 0x58b4, 0x0000001f, 0x7); + tmp = halrf_rreg(rf, 0x1c00, 0x0ffc0000); + if (tmp & BIT(9)) + delta_tssi = tmp | 0xfffffc00; + else + delta_tssi = tmp; + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d\n", + "TSSI C / Final / Delta A", halrf_rreg(rf, 0x1c00, 0x000001ff), + halrf_rreg(rf, 0x1c00, 0x0003fe00), delta_tssi); + + halrf_wreg(rf, 0x78b4, 0x0000001f, 0x7); + tmp = halrf_rreg(rf, 0x3c00, 0x0ffc0000); + if (tmp & BIT(9)) + delta_tssi = tmp | 0xfffffc00; + else + delta_tssi = tmp; + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d\n", + "TSSI C / Final / Delta B", halrf_rreg(rf, 0x1c00, 0x000001ff), + halrf_rreg(rf, 0x1c00, 0x0003fe00), delta_tssi); + + pg_ther = halrf_rreg(rf, 0x5810, 0x0000fc00); + cur_ther = halrf_rreg(rf, 0x1c10, 0xff000000); + diff_ther = pg_ther - cur_ther; + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d / %d\n", + "TherA PG / Cur / Diff / F", ((tssi_info->thermal[RF_PATH_A] == 0xff) ? 0xff : pg_ther), + cur_ther, diff_ther, + (s8)halrf_rreg(rf, 0x1c08, 0xff000000)); + + pg_ther = halrf_rreg(rf, 0x7810, 0x0000fc00); + cur_ther = halrf_rreg(rf, 0x3c10, 0xff000000); + diff_ther = pg_ther - cur_ther; + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d / %d\n", + "TherB PG / Cur / Diff / F", ((tssi_info->thermal[RF_PATH_B] == 0xff) ? 0xff : pg_ther), + cur_ther, diff_ther, + (s8)halrf_rreg(rf, 0x3c08, 0xff000000)); + + txagc_offset[RF_PATH_A] = (s8)halrf_rreg(rf, 0x1c60, 0xff000000); + txagc_offset[RF_PATH_B] = (s8)halrf_rreg(rf, 0x3c60, 0xff000000); + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = 0x%x (%d) / 0x%x (%d)\n", + "TXAGC Offset A / B", + (txagc_offset[RF_PATH_A] & 0xff), txagc_offset[RF_PATH_A], + (txagc_offset[RF_PATH_B] & 0xff), txagc_offset[RF_PATH_B]); + + int_tmp[RF_PATH_A] = txagc_offset[RF_PATH_A] * 125 / 1000; + float_tmp[RF_PATH_A] = txagc_offset[RF_PATH_A] * 125 % 1000; + float_tmp[RF_PATH_A] < 0 ? float_tmp[RF_PATH_A] = float_tmp[RF_PATH_A] * -1 : 0; + int_tmp[RF_PATH_B] = txagc_offset[RF_PATH_B] * 125 / 1000; + float_tmp[RF_PATH_B] = txagc_offset[RF_PATH_B] * 125 % 1000; + float_tmp[RF_PATH_B] < 0 ? float_tmp[RF_PATH_B] = float_tmp[RF_PATH_B] * -1 : 0; + RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %s%d.%ddB / %s%d.%ddB\n", + "TXAGC Offset dB A / B", + (int_tmp[RF_PATH_A] == 0 && txagc_offset[RF_PATH_A] < 0) ? "-" : "", + int_tmp[RF_PATH_A], float_tmp[RF_PATH_A], + (int_tmp[RF_PATH_B] == 0 && txagc_offset[RF_PATH_B] < 0) ? "-" : "", + int_tmp[RF_PATH_B], float_tmp[RF_PATH_B]); +} + +#endif /*RF_8852B_SUPPORT*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.h new file mode 100644 index 0000000..1854189 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_TSSI_8852B_H_ +#define _HALRF_TSSI_8852B_H_ +#ifdef RF_8852B_SUPPORT + +#define TSSI_VER_8852B 0x18 + +#define TSSI_PATH_MAX_8852B 2 + +/*@--------------------------Define Parameters-------------------------------*/ + + +/*@-----------------------End Define Parameters-----------------------*/ +void halrf_tssi_get_efuse_8852b(struct rf_info *rf, + enum phl_phy_idx phy); +bool halrf_tssi_check_efuse_data_8852b(struct rf_info *rf, + enum phl_phy_idx phy); +void halrf_set_tssi_de_for_tx_verify_8852b(struct rf_info *rf, + enum phl_phy_idx phy, u32 tssi_de, u8 path); +void halrf_set_tssi_de_offset_8852b(struct rf_info *rf, + enum phl_phy_idx phy, u32 tssi_de_offset, u8 path); +void halrf_set_tssi_de_offset_zero_8852b(struct rf_info *rf, + enum phl_phy_idx phy); +void halrf_do_tssi_8852b(struct rf_info *rf, enum phl_phy_idx phy); +void halrf_do_tssi_scan_8852b(struct rf_info *rf, enum phl_phy_idx phy); +void halrf_tssi_enable_8852b(struct rf_info *rf, enum phl_phy_idx phy); +void halrf_tssi_disable_8852b(struct rf_info *rf, enum phl_phy_idx phy); +s32 halrf_get_online_tssi_de_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, + u8 path, s32 dbm, s32 puot); +void halrf_tssi_cck_8852b(struct rf_info *rf, enum phl_phy_idx phy, + bool is_cck); +void halrf_set_tssi_avg_mp_8852b(struct rf_info *rf, + enum phl_phy_idx phy_idx, s32 xdbm); +void halrf_tssi_set_efuse_to_de_8852b(struct rf_info *rf, + enum phl_phy_idx phy); +void halrf_tssi_default_txagc_8852b(struct rf_info *rf, + enum phl_phy_idx phy, bool enable); + +void halrf_tssi_scan_ch_8852b(struct rf_info *rf, enum rf_path path); + +void halrf_tssi_backup_txagc_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool enable); + +u32 halrf_tssi_get_final_8852b(struct rf_info *rf, enum rf_path path); + +void halrf_get_tssi_info_8852b(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); +#endif +#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.c b/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.c new file mode 100644 index 0000000..47ce44a --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.c @@ -0,0 +1,2120 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "../halrf_precomp.h" +#ifdef RF_8852B_SUPPORT + +void _txgapk_backup_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", + reg[i], reg_backup[i]); + } +} + +void _txgapk_reload_bb_registers_8852b( + struct rf_info *rf, + enum phl_phy_idx phy, + u32 *reg, + u32 *reg_backup, + u32 reg_num) + +{ + u32 i; + + for (i = 0; i < reg_num; i++) { + halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", + reg[i], reg_backup[i]); + } +} + +void _halrf_txgapk_bkup_rf_8852b( + struct rf_info *rf, + u32 *rf_reg, + u32 rf_bkup[][TXGAPK_RF_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < TXGAPK_RF_REG_NUM_8852B; i++) { + rf_bkup[path][i] = halrf_rrf(rf, path, rf_reg[i], MASKRF); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Backup RF S%d 0x%x = %x\n", + path, rf_reg[i], rf_bkup[path][i]); + } +} + +void _halrf_txgapk_reload_rf_8852b( + struct rf_info *rf, + u32 *rf_reg, + u32 rf_bkup[][TXGAPK_RF_REG_NUM_8852B], + u8 path) +{ + u8 i; + + for (i = 0; i < TXGAPK_RF_REG_NUM_8852B; i++) { + halrf_wrf(rf, path, rf_reg[i], MASKRF, rf_bkup[path][i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Reload RF S%d 0x%x = %x\n", + path, rf_reg[i], rf_bkup[path][i]); + } +} + + +void _halrf_txgapk_bb_afe_by_mode_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path, bool is_dbcc) +{ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + if (!is_dbcc) { + /* nodbcc */ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303); + halrf_wreg(rf, 0x5864, 0x18000000, 0x3); + halrf_wreg(rf, 0x7864, 0x18000000, 0x3); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + halrf_wreg(rf, 0x12b8, 0x10000000, 0x1); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1); + halrf_wreg(rf, 0x0700, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff); + halrf_wreg(rf, 0x0c60, 0x00000003, 0x3); + halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1); + halrf_wreg(rf, 0x58ac, 0x08000000, 0x1); + halrf_wreg(rf, 0x78ac, 0x08000000, 0x1); +#ifdef CF_PHL_BB_CTRL_RX_CCA + halrf_bb_ctrl_rx_cca(rf, false, phy); +#else + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1); + halrf_wreg(rf, 0x2344, 0x80000000, 0x1); + + halrf_wreg(rf, 0x0704, BIT(1), 0x0); /*bb rst*/ + halrf_wreg(rf, 0x0704, BIT(1), 0x1); + halrf_delay_us(rf, 1); +#endif + + halrf_wreg(rf, 0x4490, 0x80000000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00007000, 0x7); + halrf_wreg(rf, 0x12a0, 0x00008000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x2); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x3333); + } else { + if (phy == HW_PHY_0) { + /* dbcc phy0 path 0 */ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0101); + halrf_wreg(rf, 0x5864, 0x18000000, 0x3); + halrf_wreg(rf, 0x7864, 0x18000000, 0x3); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + halrf_wreg(rf, 0x12b8, 0x10000000, 0x1); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1); + halrf_wreg(rf, 0x0700, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff); + halrf_wreg(rf, 0x0c60, 0x00000003, 0x3); + halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1); + halrf_wreg(rf, 0x58ac, 0x08000000, 0x1); +#ifdef CF_PHL_BB_CTRL_RX_CCA + halrf_bb_ctrl_rx_cca(rf, false, phy); +#else + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1); + /* halrf_wreg(rf, 0x2344, 0x80000000, 0x1); */ + if (halrf_rreg(rf, 0x4970, BIT(1)) == 0x0) /*CCK @PHY0*/ + halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/ + + halrf_wreg(rf, 0x0704, BIT(1), 0x0); /*bb rst*/ + halrf_wreg(rf, 0x0704, BIT(1), 0x1); + halrf_delay_us(rf, 1); +#endif + halrf_wreg(rf, 0x4490, 0x80000000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00007000, 0x7); + halrf_wreg(rf, 0x12a0, 0x00008000, 0x1); + halrf_wreg(rf, 0x12a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x12a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x0700, 0x01000000, 0x1); + halrf_wreg(rf, 0x0700, 0x06000000, 0x2); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x1111); + } else if (phy == HW_PHY_1) { + /* dbcc phy1 path 1 */ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0202); + halrf_wreg(rf, 0x7864, 0x18000000, 0x3); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + halrf_wreg(rf, 0x32b8, 0x10000000, 0x1); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x1); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x3); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff); + halrf_wreg(rf, 0x2c1c, 0x00000004, 0x1); + halrf_wreg(rf, 0x2700, 0x08000000, 0x1); + halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff); + halrf_wreg(rf, 0x0c60, 0x00000003, 0x3); + halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1); + halrf_wreg(rf, 0x78ac, 0x08000000, 0x1); +#ifdef CF_PHL_BB_CTRL_RX_CCA + halrf_bb_ctrl_rx_cca(rf, false, phy); +#else + halrf_wreg(rf, 0x2c3c, 0x00000200, 0x1); + + if (halrf_rreg(rf, 0x4970, BIT(1)) == 0x1) /*CCK @PHY1*/ + halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/ + + halrf_wreg(rf, 0x2704, BIT(1), 0x0); /*bb rst*/ + halrf_wreg(rf, 0x2704, BIT(1), 0x1); + halrf_delay_us(rf, 1); +#endif + halrf_wreg(rf, 0x6490, 0x80000000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00007000, 0x7); + halrf_wreg(rf, 0x32a0, 0x00008000, 0x1); + halrf_wreg(rf, 0x32a0, 0x00070000, 0x3); + halrf_wreg(rf, 0x32a0, 0x00080000, 0x1); + halrf_wreg(rf, 0x2700, 0x01000000, 0x1); + halrf_wreg(rf, 0x2700, 0x06000000, 0x2); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x2222); + } + } + +} + + + + +void _halrf_txgapk_iqk_preset_by_mode_8852b(struct rf_info *rf, + enum phl_phy_idx phy, enum rf_path path, bool is_dbcc) +{ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + if (!is_dbcc) { + /* nodbcc */ + halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0); + halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0); + + /* D-Die BB_Direct_SEL */ + halrf_wrf(rf, RF_PATH_A, 0x10005, 0x00001, 0x0); + halrf_wrf(rf, RF_PATH_B, 0x10005, 0x00001, 0x0); + + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080); + + halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a); + + } else { + /* dbcc */ + if (phy == HW_PHY_0) + halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0); + else if (phy == HW_PHY_1) + halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0); + + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080); + halrf_wreg(rf, 0x8080, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x8088, MASKDWORD, 0x83ff010a); + halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00200000); + halrf_wreg(rf, 0x8074, MASKDWORD, 0x80000000); + + if (phy == HW_PHY_0) + halrf_wreg(rf, 0x81dc, MASKDWORD, 0x00000000); + else if (phy == HW_PHY_1) + halrf_wreg(rf, 0x82dc, MASKDWORD, 0x00000000); + } + +} + + + +void _halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc) +{ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + if (!is_dbcc) { + /* nodbcc */ + halrf_wreg(rf, 0x12b8, 0x40000000, 0x1); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x1); + halrf_delay_us(rf, 1); + + halrf_wreg(rf, 0x030c, 0xff000000, 0x1f); + halrf_delay_us(rf, 1); + + halrf_wreg(rf, 0x030c, 0xff000000, 0x13); + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0001); + halrf_delay_us(rf, 1); + + halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041); + + } else { + /* dbcc */ + if (phy == HW_PHY_0) + halrf_wreg(rf, 0x8120, MASKDWORD, 0xce000a08); + else if (phy == HW_PHY_1) + halrf_wreg(rf, 0x8220, MASKDWORD, 0xce000a08); + + } + +} + +void _halrf_txgapk_before_one_shot_enable_8852b + (struct rf_info *rf) +{ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + + /* set 0x80d4[21:16]=0x03 (before oneshot NCTL) to get report later */ + halrf_wreg(rf, 0x80d4, 0x003F0000, 0x03); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> before set one-shot bit, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD)); +} + +void _halrf_txgapk_one_shot_nctl_done_check_8852b + (struct rf_info *rf, enum txgapk_id id, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + /* for check status */ + u32 r_bff8 = 0; + u32 r_80fc = 0; + bool is_ready = false; + u16 count = 1; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + /* for 0xbff8 check NCTL DONE */ + while (count < 2000) { + r_bff8 = halrf_rreg(rf, 0xbff8, MASKBYTE0); + + if (r_bff8 == 0x55) { + is_ready = true; + break; + } + /* r_bff8 = 0; */ + halrf_delay_us(rf, 10); + count++; + } + + halrf_delay_us(rf, 1); + txgapk_info->txgapk_chk_cnt[path][id][0] = count; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> check 0xBFF8[7:0] = 0x%x, IsReady = %d, ReadTimes = %d,delay 1 us\n", r_bff8, is_ready, count); + + + + /* for 0x80fc check NCTL DONE */ + count = 1; + is_ready = false; + while (count < 2000) { + r_80fc = halrf_rreg(rf, 0x80fc, MASKLWORD); + + if (r_80fc == 0x8000) { + is_ready = true; + break; + } + /* r_80fc = 0; */ + halrf_delay_us(rf, 1); + count++; + } + + halrf_delay_us(rf, 1); + txgapk_info->txgapk_chk_cnt[path][id][1] = count; + + halrf_wreg(rf, 0x8010, 0x000000ff, 0x00); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> check 0x80fc[15:0] = 0x%x, IsReady = %d, ReadTimes = %d, 0x%x= 0x%x \n", r_80fc, is_ready, count, 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD) ); + +} + + +void _halrf_txgapk_track_table_nctl_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + u32 i; + u32 d[17] = {0}, ta[17] = {0}; + + u32 itqt[2] = {0x81cc, 0x82cc}; + u32 gapk_on_table0_setting[2] = {0x8158, 0x8258}; + + u32 cal_path[2] = {0x00002019, 0x00002029}; + + + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, path = %d\n", __func__, path); + + halrf_wrf(rf, path, 0x00, MASKRF, 0x503e0); + halrf_wrf(rf, path, 0xdf, 0x01000, 0x1); + halrf_wrf(rf, path, 0x9e, 0x00100, 0x1); + halrf_wrf(rf, path, 0x83, 0x00007, 0x2); + halrf_wrf(rf, path, 0x83, 0x000f0, 0xf); + halrf_wreg(rf, itqt[path], 0x0000003f, 0x3f); +#if 0 + halrf_wrf(rf, path, 0x94, 0x003fc, 0x7f); + halrf_wrf(rf, path, 0x93, 0x00008, 0x0); + halrf_wrf(rf, path, 0x92, 0x00001, 0x0); + halrf_wrf(rf, path, 0x92, 0x00001, 0x1); + + for (i = 0; i < 100; i++) + halrf_delay_us(rf, 1); +#else + halrf_set_rx_dck_8852b(rf, phy, path, false); +#endif + + halrf_wrf(rf, path, 0x92, 0x00001, 0x0); + + for (i = 0; i < 100; i++) + halrf_delay_us(rf, 1); + + halrf_wrf(rf, path, 0x1005e, MASKRF, 0xc0000); + halrf_wreg(rf, 0x801c, 0x000e0000, 0x2); + + halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f); + halrf_wreg(rf, 0x80e0, 0x0000f000, 0x0); + halrf_wreg(rf, 0x8038, 0x003f0000, 0x24); + halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x001554); + halrf_wreg(rf, 0x5864, 0x20000000, 0x1); + halrf_wreg(rf, itqt[path], 0x0000003f, 0x1b); + halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009); + + + _halrf_txgapk_before_one_shot_enable_8852b(rf); + halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]); + + _halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_TRACK, path); + + + halrf_wreg(rf, 0x5864, 0x20000000, 0x0); + halrf_wrf(rf, path, 0x1005e, MASKRF, 0x0); + + /* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */ + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3); + + d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4); + d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5); + d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6); + d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7); + d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9); + ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa); + ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb); + ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc); + ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd); + ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff); + + + + /* for debug */ + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x0000007f); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + + + + halrf_wreg(rf, itqt[path], MASKDWORD, 0x09); + halrf_wreg(rf, 0x80d0, 0x00100000, 0x1); + + + for (i = 0; i < 17; i++) { + if (d[i] & BIT(6)) + txgapk_info->track_d[path][i] = (s32)(d[i] | 0xffffff80); + else + txgapk_info->track_d[path][i] = (s32)(d[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track d[%d][%d]=0x%x\n", + path, i, txgapk_info->track_d[path][i]); + } + + for (i = 0; i < 17; i++) { + if (ta[i] & BIT(7)) + txgapk_info->track_ta[path][i] = (s32)(ta[i] | 0xffffff00); + else + txgapk_info->track_ta[path][i] = (s32)(ta[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track ta[%d][%d]=0x%x\n", + path, i, txgapk_info->track_ta[path][i]); + } + +} + + +void _halrf_txgapk_track_table_nctl_5g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + u32 i; + u32 d[17] = {0}, ta[17] = {0}; + + u32 itqt[2] = {0x81cc, 0x82cc}; + u32 gapk_on_table0_setting[2] = {0x8158, 0x8258}; + + u32 cal_path[2] = {0x00002019, 0x00002029}; + + + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, path = %d\n", __func__, path); + + + halrf_wrf(rf, path, 0x00, MASKRF, 0x503e0); + halrf_wrf(rf, path, 0xdf, 0x01000, 0x1); + halrf_wrf(rf, path, 0x9e, 0x00100, 0x1); + halrf_wrf(rf, path, 0x8c, 0x0e000, 0x0); + halrf_wrf(rf, path, 0x8c, 0x01800, 0x3); + halrf_wrf(rf, path, 0x8c, 0x00600, 0x1); + halrf_wreg(rf, itqt[path], 0x0000003f, 0x3f); +#if 0 + halrf_wrf(rf, path, 0x94, 0x003fc, 0x7f); + halrf_wrf(rf, path, 0x93, 0x00008, 0x0); + halrf_wrf(rf, path, 0x92, 0x00001, 0x0); + halrf_wrf(rf, path, 0x92, 0x00001, 0x1); + + for (i = 0; i < 100; i++) + halrf_delay_us(rf, 1); +#else + halrf_set_rx_dck_8852b(rf, phy, path, false); +#endif + + halrf_wrf(rf, path, 0x92, 0x00001, 0x0); + + for (i = 0; i < 100; i++) + halrf_delay_us(rf, 1); + + + halrf_wrf(rf, path, 0x1005e, MASKRF, 0xc0000); + halrf_wreg(rf, 0x801c, 0x000e0000, 0x2); + + halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f); + halrf_wreg(rf, 0x80e0, 0x0000f000, 0x0); + halrf_wreg(rf, 0x8038, 0x003f0000, 0x24); + halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x003550); + halrf_wreg(rf, 0x5864, 0x20000000, 0x1); + halrf_wreg(rf, itqt[path], 0x0000003f, 0x24); + halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009); + + _halrf_txgapk_before_one_shot_enable_8852b(rf); + halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]); + + _halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_TRACK, path); + + + halrf_wreg(rf, 0x5864, 0x20000000, 0x0); + halrf_wrf(rf, path, 0x1005e, MASKRF, 0x0); + + /* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */ + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3); + d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4); + d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5); + d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6); + d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7); + d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9); + ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa); + ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb); + ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc); + ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd); + ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff); + + + /* debug */ + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x0000007f); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + + + halrf_wreg(rf, itqt[path], MASKDWORD, 0x09); + halrf_wreg(rf, 0x80d0, 0x00100000, 0x1); + + for (i = 0; i < 17; i++) { + if (d[i] & BIT(6)) + txgapk_info->track_d[path][i] = (s32)(d[i] | 0xffffff80); + else + txgapk_info->track_d[path][i] = (s32)(d[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track d[%d][%d]=0x%x\n", + path, i, txgapk_info->track_d[path][i]); + } + + for (i = 0; i < 17; i++) { + if (ta[i] & BIT(7)) + txgapk_info->track_ta[path][i] = (s32)(ta[i] | 0xffffff00); + else + txgapk_info->track_ta[path][i] = (s32)(ta[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track ta[%d][%d]=0x%x\n", + path, i, txgapk_info->track_ta[path][i]); + } + +} + + +void _halrf_txgapk_track_table_nctl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_track_table_nctl_2g_8852b(rf, phy, path); + else + _halrf_txgapk_track_table_nctl_5g_8852b(rf, phy, path); +} + +void _halrf_txgapk_write_track_table_default_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_default_5gl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_default_5gm_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_default_5gh_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias)); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_default_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_write_track_table_default_2g_8852b(rf, phy, path); + else if (channel >= 36 && channel <= 64) + _halrf_txgapk_write_track_table_default_5gl_8852b(rf, phy, path); + else if (channel >= 100 && channel <= 144) + _halrf_txgapk_write_track_table_default_5gm_8852b(rf, phy, path); + else if (channel >= 149 && channel <= 177) + _halrf_txgapk_write_track_table_default_5gh_8852b(rf, phy, path); +} + +void _halrf_txgapk_write_track_table_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + u8 pa_change[6] = {0}; + + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + if (rfe_type <= 50) { + /* NIC */ + /* AP iFEM */ + pa_change[0] = 2; + pa_change[1] = 4; + pa_change[2] = 6; + pa_change[3] = 8; + pa_change[4] = 10; + pa_change[5] = 12; + } + else { + /* AP eFEM */ + pa_change[0] = 1; + pa_change[1] = 3; + pa_change[2] = 5; + pa_change[3] = 7; + pa_change[4] = 9; + pa_change[5] = 11; + } + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_5gl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 pa_change[6] = {0}; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + pa_change[0] = 4; + pa_change[1] = 6; + pa_change[2] = 8; + pa_change[3] = 10; + pa_change[4] = 12; + pa_change[5] = 13; + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ + +} + +void _halrf_txgapk_write_track_table_5gm_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 pa_change[6] = {0}; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + pa_change[0] = 4; + pa_change[1] = 6; + pa_change[2] = 8; + pa_change[3] = 10; + pa_change[4] = 12; + pa_change[5] = 13; + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ + +} + +void _halrf_txgapk_write_track_table_5gh_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 pa_change[6] = {0}; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 8; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + pa_change[0] = 4; + pa_change[1] = 6; + pa_change[2] = 8; + pa_change[3] = 10; + pa_change[4] = 12; + pa_change[5] = 13; + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f); + + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_track_table_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_write_track_table_2g_8852b(rf, phy, path); + else if (channel >= 36 && channel <= 64) + _halrf_txgapk_write_track_table_5gl_8852b(rf, phy, path); + else if (channel >= 100 && channel <= 144) + _halrf_txgapk_write_track_table_5gm_8852b(rf, phy, path); + else if (channel >= 149 && channel <= 177) + _halrf_txgapk_write_track_table_5gh_8852b(rf, phy, path); +} + +void _halrf_txgapk_power_table_nctl_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + /* u8 rfe_type = rf->phl_com->dev_cap.rfe_type; */ + + u32 i; + u32 d[17] = {0}, ta[17] = {0}; + u32 gapk_on_table0_setting[2] = {0x8170, 0x8270}; + /* u32 path_setting[2] = {0x5864, 0x7864}; */ + u32 itqt[2] = {0x81cc, 0x82cc}; + u32 cal_path[2] = {0x00002119, 0x00002129}; + + + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f); + halrf_wreg(rf, 0x8038, 0x003f0000, 0x24); + halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x000540); + halrf_wreg(rf, 0x5864, 0x20000000, 0x1); + halrf_wreg(rf, itqt[path], 0x0000003f, 0x24); + halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009); + + _halrf_txgapk_before_one_shot_enable_8852b(rf); + halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]); + + _halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_PWR, path); + + halrf_wreg(rf, 0x5864, 0x20000000, 0x0); + + + + /* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */ + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3); + d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4); + d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5); + d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6); + d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7); + d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f); + + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9); + ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa); + ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb); + ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc); + ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd); + ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff); + + + /* debug */ + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x0000007f); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + + halrf_wreg(rf, 0x801c, 0x000e0000, 0x0); + + /* for debug */ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> afr restore 0x801c, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD)); + + + halrf_wreg(rf, itqt[path], MASKDWORD, 0x1b); + halrf_wreg(rf, 0x80d0, 0x00100000, 0x1); + + for (i = 0; i < 17; i++) { + if (d[i] & BIT(6)) + txgapk_info->power_d[path][i] = (s32)(d[i] | 0xffffff80); + else + txgapk_info->power_d[path][i] = (s32)(d[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power d[%d][%d]=0x%x\n", + path, i, txgapk_info->power_d[path][i]); + } + + for (i = 0; i < 17; i++) { + if (ta[i] & BIT(7)) + txgapk_info->power_ta[path][i] = (s32)(ta[i] | 0xffffff00); + else + txgapk_info->power_ta[path][i] = (s32)(ta[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power ta[%d][%d]=0x%x\n", + path, i, txgapk_info->power_ta[path][i]); + } + +} + + +void _halrf_txgapk_power_table_nctl_5g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + /* u8 rfe_type = rf->phl_com->dev_cap.rfe_type; */ + + u32 i; + u32 d[17] = {0}, ta[17] = {0}; + u32 gapk_on_table0_setting[2] = {0x8170, 0x8270}; + /* u32 path_setting[2] = {0x5864, 0x7864}; */ + u32 itqt[2] = {0x81cc, 0x82cc}; + u32 cal_path[2] = {0x00002119, 0x00002129}; + + + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + + halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f); + halrf_wreg(rf, 0x8038, 0x003f0000, 0x24); + halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x000540); + halrf_wreg(rf, 0x5864, 0x20000000, 0x1); + halrf_wreg(rf, itqt[path], MASKDWORD, 0x24); + halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009); + + _halrf_txgapk_before_one_shot_enable_8852b(rf); + halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]); + + _halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_PWR, path); + + halrf_wreg(rf, 0x5864, 0x20000000, 0x0); + + /* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */ + halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3); + d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4); + d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5); + d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6); + d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f); + d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80); + d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000); + d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7); + d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f); + + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9); + ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa); + ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb); + ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc); + ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff); + ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00); + ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000); + ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000); + + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd); + ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff); + + + /* debug */ + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x0000007f); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2); + // = halrf_rreg(rf, 0x80fc, 0x007f0000); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf); + // = halrf_rreg(rf, 0x80fc, MASKDWORD); + + + halrf_wreg(rf, 0x801c, 0x000e0000, 0x0); + + /* for debug */ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> afr restore 0x801c, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD)); + + + halrf_wreg(rf, itqt[path], MASKDWORD, 0x1b); + halrf_wreg(rf, 0x80d0, 0x00100000, 0x1); + + for (i = 0; i < 17; i++) { + if (d[i] & BIT(6)) + txgapk_info->power_d[path][i] = (s32)(d[i] | 0xffffff80); + else + txgapk_info->power_d[path][i] = (s32)(d[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power d[%d][%d]=0x%x\n", + path, i, txgapk_info->power_d[path][i]); + } + + for (i = 0; i < 17; i++) { + if (ta[i] & BIT(7)) + txgapk_info->power_ta[path][i] = (s32)(ta[i] | 0xffffff00); + else + txgapk_info->power_ta[path][i] = (s32)(ta[i]); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power ta[%d][%d]=0x%x\n", + path, i, txgapk_info->power_ta[path][i]); + } + +} + + +void _halrf_txgapk_power_table_nctl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_power_table_nctl_2g_8852b(rf, phy, path); + else + _halrf_txgapk_power_table_nctl_5g_8852b(rf, phy, path); + +} + +void _halrf_txgapk_write_power_table_default_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_default_5gl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_default_5gm_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_default_5gh_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + /* NIC */ + /* AP iFEM */ + /* AP eFEM */ + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_default_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_write_power_table_default_2g_8852b(rf, phy, path); + else if (channel >= 36 && channel <= 64) + _halrf_txgapk_write_power_table_default_5gl_8852b(rf, phy, path); + else if (channel >= 100 && channel <= 144) + _halrf_txgapk_write_power_table_default_5gm_8852b(rf, phy, path); + else if (channel >= 149 && channel <= 177) + _halrf_txgapk_write_power_table_default_5gh_8852b(rf, phy, path); +} + +void _halrf_txgapk_write_power_table_2g_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + u8 pa_change[3] = {0}; + + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + if (rfe_type <= 50) { + /* NIC */ + /* AP iFEM */ + + pa_change[0] = 6; + pa_change[1] = 8; + pa_change[2] = 10; + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } + else { + /* AP eFEM */ + pa_change[0] = 14; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x1); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + } + + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_5gl_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + u8 pa_change[3] = {0}; + + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + if (rfe_type < 50) { + /* NIC */ + pa_change[0] = 6; + pa_change[1] = 8; + pa_change[2] = 10; + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else if (rfe_type == 50) { + /* AP iFEM */ + pa_change[0] = 6; + pa_change[1] = 9; + pa_change[2] = 10; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x21); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x23); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x26); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else { + /* AP eFEM */ + pa_change[0] = 14; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x21); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + } + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_5gm_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + u8 pa_change[3] = {0}; + + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + if (rfe_type < 50) { + /* NIC */ + pa_change[0] = 6; + pa_change[1] = 8; + pa_change[2] = 10; + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else if (rfe_type == 50) { + /* AP iFEM */ + pa_change[0] = 6; + pa_change[1] = 9; + pa_change[2] = 10; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x29); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x2b); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x2e); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else { + /* AP eFEM */ + pa_change[0] = 14; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x29); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + } + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_5gh_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + u8 pa_change[3] = {0}; + + u32 bias = 0; + + /* table1 */ + if (txgapk_info->txgapk_table_idx == 1) + bias = 4; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias); + + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */ + + if (rfe_type < 50) { + /* NIC */ + pa_change[0] = 6; + pa_change[1] = 8; + pa_change[2] = 10; + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + + halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias); + halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else if (rfe_type == 50) { + /* AP iFEM */ + pa_change[0] = 6; + pa_change[1] = 9; + pa_change[2] = 10; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x31); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x33); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f); + halrf_wrf(rf, path, 0x33, 0x01fff, 0x36); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f); + } else { + /* AP eFEM */ + pa_change[0] = 14; + + halrf_wrf(rf, path, 0x33, 0x01fff, 0x31); + halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f); + } + + halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */ +} + +void _halrf_txgapk_write_power_table_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path) +{ + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + if (channel >= 1 && channel <= 14) + _halrf_txgapk_write_power_table_2g_8852b(rf, phy, path); + else if (channel >= 36 && channel <= 64) + _halrf_txgapk_write_power_table_5gl_8852b(rf, phy, path); + else if (channel >= 100 && channel <= 144) + _halrf_txgapk_write_power_table_5gm_8852b(rf, phy, path); + else if (channel >= 149 && channel <= 177) + _halrf_txgapk_write_power_table_5gh_8852b(rf, phy, path); +} + +void _halrf_txgapk_iqk_bk_reg_by_mode_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc) +{ + u32 path_setting[2] = {0x0e19, 0x0e29}; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + if (!is_dbcc) { + /* no dbcc */ + + _halrf_txgapk_before_one_shot_enable_8852b(rf); + halrf_wreg(rf, 0x8000, MASKDWORD, path_setting[path]); + + _halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_IQKBK, path); + + + halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000); + halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000); + + } else { + /* dbcc */ + if (phy == HW_PHY_0) { + halrf_wreg(rf, 0x8120, MASKDWORD, 0x10010000); + halrf_wreg(rf, 0x8140, 0x00000100, 0x0); + halrf_wreg(rf, 0x8150, MASKDWORD, 0xe4e4e4e4); + halrf_wreg(rf, 0x8154, 0x00000100, 0x0); + halrf_wreg(rf, 0x81cc, 0x0000003f, 0x0); + halrf_wreg(rf, 0x81dc, MASKDWORD, 0x00000002); + } else if (phy == HW_PHY_1) { + halrf_wreg(rf, 0x8220, MASKDWORD, 0x10010000); + halrf_wreg(rf, 0x8240, 0x00000100, 0x0); + halrf_wreg(rf, 0x8250, MASKDWORD, 0xe4e4e4e4); + halrf_wreg(rf, 0x8254, 0x00000100, 0x0); + halrf_wreg(rf, 0x82cc, 0x0000003f, 0x0); + halrf_wreg(rf, 0x82dc, MASKDWORD, 0x00000002); + } + } + + halrf_wrf(rf, path, 0xef, 0x00004, 0x0); + + halrf_wrf(rf, path, 0x0, 0xf0000, 0x3); + + halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x1); + halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x1); + + halrf_wrf(rf, RF_PATH_A, 0x10005, 0x00001, 0x1); + halrf_wrf(rf, RF_PATH_B, 0x10005, 0x00001, 0x1); + +} + + + +void _halrf_txgapk_afe_bk_reg_by_mode_8852b + (struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc) +{ + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__); + + if (!is_dbcc) { + /* no dbcc */ + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0); + halrf_wreg(rf, 0x0700, 0x08000000, 0x0); + halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03); + halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03); + halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x0700, 0x07000000, 0x0); + + #if 1 /* jerry recommand to fix */ + /* halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); */ + halrf_wreg(rf, 0x2344, 0x80000000, 0x0); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x0); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x0); + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); /* block OFDM CCK */ + #else /* default */ + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); + halrf_wreg(rf, 0x2344, 0x80000000, 0x0); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x0); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x0); + #endif + } else { + /* dbcc */ + if (phy == HW_PHY_0) { + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0101); + halrf_wreg(rf, 0x12b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x5864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000); + halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0); + halrf_wreg(rf, 0x0700, 0x08000000, 0x0); + halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03); + halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03); + halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x0700, 0x07000000, 0x0); + halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); + halrf_wreg(rf, 0x2344, 0x80000000, 0x0); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000); + halrf_wreg(rf, 0x58c8, 0x01000000, 0x0); + } else if (phy == HW_PHY_1) { + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0202); + halrf_wreg(rf, 0x32b8, 0x40000000, 0x0); + halrf_wreg(rf, 0x7864, 0xc0000000, 0x0); + halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000); + halrf_wreg(rf, 0x2c1c, 0x00000004, 0x0); + halrf_wreg(rf, 0x2700, 0x08000000, 0x0); + halrf_wreg(rf, 0x0cf0, 0x000001ff, 0x000); + halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00); + halrf_wreg(rf, 0x2700, 0x07000000, 0x0); + halrf_wreg(rf, 0x2c3c, 0x00000200, 0x0); + halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000); + halrf_wreg(rf, 0x78c8, 0x01000000, 0x0); + halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03); + } + } + +} + + + + +void _halrf_do_non_dbcc_txgapk_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u8 i; + + u32 bb_reg[1] = {0x2344}; + u32 bb_reg_backup[1] = {0}; + u32 backup_num = 1; + + u32 rf_3wire_a_die[2] = {0}; + u32 rf_3wire_d_die[2] = {0}; + + u32 rf_bkup[TXGAPK_RF_PATH_MAX_8852B][TXGAPK_RF_REG_NUM_8852B] = {{0}}; + u32 rf_reg[TXGAPK_RF_REG_NUM_8852B] = {0xdf}; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy); + + + _txgapk_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + for (i = 0; i < TXGAPK_RF_PATH_MAX_8852B; i++) { + _halrf_txgapk_bkup_rf_8852b(rf, rf_reg, rf_bkup, i); + } + + /*rf_0[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x0, 0xfffff);*/ + /*rf_0[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x0, 0xfffff);*/ + + rf_3wire_a_die[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x5, 0xfffff); + rf_3wire_a_die[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x5, 0xfffff); + + rf_3wire_d_die[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x10005, 0xfffff); + rf_3wire_d_die[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x10005, 0xfffff); + + /*halrf_wrf(rf, RF_PATH_A, 0x0, 0x00001, 0x1);*/ + /*halrf_wrf(rf, RF_PATH_B, 0x0, 0x00001, 0x1);*/ + + for (i = 0; i < 2; i++) { + /*_halrf_txgapk_iqk_dpk_init_reg_8852b(rf, phy, RF_PATH_A);*/ + /*_halrf_txgapk_nctl_8852b(rf, phy, RF_PATH_A);*/ + + _halrf_txgapk_write_track_table_default_8852b(rf, phy, i); + _halrf_txgapk_write_power_table_default_8852b(rf, phy, i); + + _halrf_txgapk_bb_afe_by_mode_8852b(rf, phy, i, false); + _halrf_txgapk_iqk_preset_by_mode_8852b(rf, phy, i, false); + _halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b(rf, phy, i, false); + + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START); + halrf_tmac_tx_pause(rf, phy, true); + + _halrf_txgapk_track_table_nctl_8852b(rf, phy, i); + _halrf_txgapk_write_track_table_8852b(rf, phy, i); + _halrf_txgapk_power_table_nctl_8852b(rf, phy, i); + _halrf_txgapk_write_power_table_8852b(rf, phy, i); + + halrf_tmac_tx_pause(rf, phy, false); + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP); + + _halrf_txgapk_iqk_bk_reg_by_mode_8852b(rf, phy, i, false); + _halrf_txgapk_afe_bk_reg_by_mode_8852b(rf, phy, i, false); + } + + /*halrf_wrf(rf, RF_PATH_A, 0x0, 0x00001, rf_0[RF_PATH_A]);*/ + /*halrf_wrf(rf, RF_PATH_B, 0x0, 0x00001, rf_0[RF_PATH_B]);*/ + + for (i = 0; i < TXGAPK_RF_PATH_MAX_8852B; i++) { + _halrf_txgapk_reload_rf_8852b(rf, rf_reg, rf_bkup, i); + } + + halrf_wrf(rf, RF_PATH_A, 0x5, 0xfffff, rf_3wire_a_die[RF_PATH_A]); + halrf_wrf(rf, RF_PATH_B, 0x5, 0xfffff, rf_3wire_a_die[RF_PATH_B]); + + halrf_wrf(rf, RF_PATH_A, 0x10005, 0xfffff, rf_3wire_d_die[RF_PATH_A]); + halrf_wrf(rf, RF_PATH_B, 0x10005, 0xfffff, rf_3wire_d_die[RF_PATH_B]); + + _txgapk_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); +} +void _halrf_do_dbcc_txgapk_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + u32 bb_reg[1] = {0x2344}; + u32 bb_reg_backup[1] = {0}; + u32 backup_num = 1; + u32 rf_3wire[2] = {0}; + enum rf_path path = 0; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy); + + _txgapk_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + + rf_3wire[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x5, 0xfffff); + rf_3wire[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x5, 0xfffff); + + /* halrf_wrf(rf, RF_PATH_A, 0x00, 0x00001, 0x1); */ + /* halrf_wrf(rf, RF_PATH_B, 0x00, 0x00001, 0x1); */ + + + /*_halrf_txgapk_iqk_dpk_init_reg_8852b(rf, phy, RF_PATH_A);*/ + /*_halrf_txgapk_nctl_8852b(rf, phy, RF_PATH_A);*/ + + if (phy == HW_PHY_0) + path = RF_PATH_A; + else if (phy == HW_PHY_1) + path = RF_PATH_B; + + _halrf_txgapk_write_track_table_default_8852b(rf, phy, path); + _halrf_txgapk_write_power_table_default_8852b(rf, phy, path); + + _halrf_txgapk_bb_afe_by_mode_8852b(rf, phy, path, true); + _halrf_txgapk_iqk_preset_by_mode_8852b(rf, phy, path, true); + _halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b(rf, phy, path, true); + + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START); + halrf_tmac_tx_pause(rf, phy, true); + + _halrf_txgapk_track_table_nctl_8852b(rf, phy, path); + _halrf_txgapk_write_track_table_8852b(rf, phy, path); + + + _halrf_txgapk_power_table_nctl_8852b(rf, phy, path); + _halrf_txgapk_write_power_table_8852b(rf, phy, path); + + halrf_tmac_tx_pause(rf, phy, true); + halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP); + + _halrf_txgapk_iqk_bk_reg_by_mode_8852b(rf, phy, path, true); + _halrf_txgapk_afe_bk_reg_by_mode_8852b(rf, phy, path, true); + + /* halrf_wrf(rf, RF_PATH_A, 0x00, 0x00001, 0x0); */ + /* halrf_wrf(rf, RF_PATH_B, 0x00, 0x00001, 0x0); */ + + halrf_wrf(rf, RF_PATH_A, 0x5, 0xfffff, rf_3wire[RF_PATH_A]); + halrf_wrf(rf, RF_PATH_B, 0x5, 0xfffff, rf_3wire[RF_PATH_B]); + + _txgapk_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, + backup_num); + +} +void _halrf_txgapk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + u8 idx = 0; + u8 get_empty_table = false; + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s \n", __func__); + + for (idx = 0; idx < 2; idx++) { + if (txgapk_info->txgapk_mcc_ch[idx] == 0) { + get_empty_table = true; + break; + } + } + //RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] (1) idx = %x\n", idx); + + if (false == get_empty_table) { + idx = txgapk_info->txgapk_table_idx + 1; + if (idx > 1) { + idx = 0; + } + //RF_DBG(rf, DBG_RF_IQK, "[IQK]we will replace iqk table index(%d), !!!!! \n", idx); + } + //RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] (2) idx = %x\n", idx); + + + txgapk_info->txgapk_table_idx = idx; + txgapk_info->txgapk_mcc_ch[idx] = rf->hal_com->band[phy].cur_chandef.center_ch; + txgapk_info->ch[0] = rf->hal_com->band[phy].cur_chandef.center_ch; + + + + +} +void halrf_do_txgapk_8852b(struct rf_info *rf, + enum phl_phy_idx phy) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + txgapk_info->is_txgapk_ok = true; + txgapk_info->r0x8010[0] = halrf_rreg(rf, 0x8010, MASKDWORD); + + _halrf_txgapk_get_ch_info_8852b(rf, phy); + + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d, dbcc_en = %d, table = %d \n", __func__, phy, rf->hal_com->dbcc_en, txgapk_info->txgapk_table_idx); + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> version = 0x%x\n", TXGAPK_VER_8852B); + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> before GapK process, 0x%x= 0x%x\n", 0x8010, txgapk_info->r0x8010[0]); + + + /* 0:table_0, 1:table_1 */ + halrf_wrf(rf, RF_PATH_A, 0x18, 0x80000, txgapk_info->txgapk_table_idx); + halrf_wrf(rf, RF_PATH_B, 0x18, 0x80000, txgapk_info->txgapk_table_idx); + halrf_wrf(rf, RF_PATH_A, 0x10018, 0x80000, txgapk_info->txgapk_table_idx); + halrf_wrf(rf, RF_PATH_B, 0x10018, 0x80000, txgapk_info->txgapk_table_idx); + + if (rf->hal_com->dbcc_en) + _halrf_do_dbcc_txgapk_8852b(rf, phy); + else + _halrf_do_non_dbcc_txgapk_8852b(rf, phy); + + txgapk_info->r0x8010[1] = halrf_rreg(rf, 0x8010, MASKDWORD); + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> After GapK process, 0x%x= 0x%x\n", 0x8010, txgapk_info->r0x8010[1]); +} + +void halrf_txgapk_init_8852b(struct rf_info *rf) +{ + struct halrf_gapk_info *txgapk_info = &rf->gapk; + u8 idx; + + if(!txgapk_info->is_gapk_init) { + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s \n", __func__); + txgapk_info->is_gapk_init = true; + + for (idx = 0; idx < 2; idx++) { //channel + txgapk_info->txgapk_mcc_ch[idx] = 0; + } + txgapk_info->txgapk_table_idx = 0; + } + +} + + +void halrf_txgapk_enable_8852b + (struct rf_info *rf, enum phl_phy_idx phy) +{ + u8 i; + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy); + + for (i = RF_PATH_A; i < 2; i++) { + _halrf_txgapk_write_track_table_8852b(rf, phy, i); + _halrf_txgapk_write_power_table_8852b(rf, phy, i); + } +} + +void halrf_txgapk_write_table_default_8852b + (struct rf_info *rf, enum phl_phy_idx phy) +{ + u8 i; + RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy); + + for (i = RF_PATH_A; i < 2; i++) { + _halrf_txgapk_write_track_table_default_8852b(rf, phy, i); + _halrf_txgapk_write_power_table_default_8852b(rf, phy, i); + } +} + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.h new file mode 100644 index 0000000..210db1d --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_TXGAPK_8852B_H__ +#define __HALRF_TXGAPK_8852B_H__ + +#ifdef RF_8852B_SUPPORT + +#define TXGAPK_VER_8852B 0x06 + +/*--------------------------Define Parameters-------------------------------*/ +#define TXGAPK_RF_PATH_MAX_8852B 2 + +#define TXGAPK_RF_REG_NUM_8852B 1 + +#define TXGAPK_DEBUGMASK_8852B 0x100EE + +#define TXGAP_TB_ADDR_8852B 0x10033 + +#define TXGAP_TB_VAL_8852B 0x1003F + + +/*---------------------------End Define Parameters----------------------------*/ + + + + +void halrf_txgapk_enable_8852b + (struct rf_info *rf, enum phl_phy_idx phy); + +void halrf_txgapk_write_table_default_8852b + (struct rf_info *rf, enum phl_phy_idx phy); + +void halrf_do_txgapk_8852b(struct rf_info *rf, enum phl_phy_idx phy); + + +void halrf_txgapk_init_8852b(struct rf_info *rf); + +#endif /* RF_8852B_SUPPORT */ +#endif /*#ifndef __HALRF_TXGAPK_8852B_H__*/ diff --git a/phl/hal_g6/phy/rf/halrf_8852b/halrf_version_rtl8852b.h b/phl/hal_g6/phy/rf/halrf_8852b/halrf_version_rtl8852b.h new file mode 100644 index 0000000..26e6d05 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_8852b/halrf_version_rtl8852b.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +/*RTL8852B RF Parameters*/ +#define RF_RELEASE_VERSION_8852B 19 diff --git a/phl/hal_g6/phy/rf/halrf_api.c b/phl/hal_g6/phy/rf/halrf_api.c new file mode 100644 index 0000000..f959e70 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_api.c @@ -0,0 +1,414 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + +#include "halrf_precomp.h" + +u32 phlrf_psd_log2base(struct rf_info *rf, u32 val) +{ + u32 j; + u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; + u32 result, val_fractiond_b = 0; + u32 table_fraction[21] = { + 0, 432, 332, 274, 232, 200, 174, 151, 132, 115, + 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0}; + + if (val == 0) + return 0; + + tmp = val; + + while (1) { + if (tmp == 1) + break; + + tmp = (tmp >> 1); + shiftcount++; + } + + val_integerd_b = shiftcount + 1; + + tmp2 = 1; + for (j = 1; j <= val_integerd_b; j++) + tmp2 = tmp2 * 2; + + tmp = (val * 100) / tmp2; + tindex = tmp / 5; + + if (tindex > 20) + tindex = 20; + + val_fractiond_b = table_fraction[tindex]; + + result = val_integerd_b * 100 - val_fractiond_b; + + return result; +} + +void phlrf_rf_lna_setting(struct rf_info *rf, enum phlrf_lna_set type) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + break; +#endif + default: + break; + } + +} + +void halrf_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num) +{ + u32 i; + + for (i = 0; i < reg_num; i++) + bp[i] = halrf_rreg(rf, bp_reg[i], MASKDWORD); +} + +void halrf_bkprf(struct rf_info *rf, u32 *bp_reg, u32 bp[][4], u32 reg_num, u32 path_num) +{ + u32 i, j; + + for (i = 0; i < reg_num; i++) { + for (j = 0; j < path_num; j++) + bp[i][j] = halrf_rrf(rf, j, bp_reg[i], MASKRF); + } +} + +void halrf_reload_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num) +{ + u32 i; + + for (i = 0; i < reg_num; i++) + halrf_wreg(rf, bp_reg[i], MASKDWORD, bp[i]); +} + +void halrf_reload_bkprf(struct rf_info *rf, + u32 *bp_reg, + u32 bp[][4], + u32 reg_num, + u8 path_num) +{ + u32 i, path; + + for (i = 0; i < reg_num; i++) { + for (path = 0; path < path_num; path++) + halrf_wrf(rf, (enum rf_path)path, bp_reg[i], + MASKRF, bp[i][path]); + } +} + +u8 halrf_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + +u8 path = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + path = halrf_kpath_8852a(rf, phy_idx); + break; +#endif + default: + break; + } + return path; +} + +void halrf_wait_rx_mode(struct rf_info *rf, u8 kpath) +{ + u8 path, rf_mode = 0; + u16 count = 0; + + for (path = 0; path < 4; path++) { + if (kpath & BIT(path)) { + rf_mode = (u8)halrf_rrf(rf, path, 0x00, MASKRFMODE); + + while (rf_mode == 2 && count < 2500) { + rf_mode = (u8)halrf_rrf(rf, path, 0x00, MASKRFMODE); + halrf_delay_us(rf, 2); + count++; + } + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Wait S%d to Rx mode!! (count = %d)\n", path, count); + } + } +} + +void halrf_tmac_tx_pause(struct rf_info *rf, enum phl_phy_idx band_idx, bool is_pause) +{ + halrf_tx_pause(rf, band_idx, is_pause, PAUSE_RSON_RFK); + + RF_DBG(rf, DBG_RF_RFK,"[RFK] Band%d Tx Pause %s!!\n", + band_idx, is_pause ? "on" : "off"); + + if (is_pause) + halrf_wait_rx_mode(rf, halrf_kpath(rf, band_idx)); +} + +void halrf_trigger_thermal(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_trigger_thermal_8852a(rf, RF_PATH_A); + halrf_trigger_thermal_8852a(rf, RF_PATH_B); + break; +#endif + default: + break; + } +} + +u8 halrf_only_get_thermal(struct rf_info *rf, enum rf_path path) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + return halrf_only_get_thermal_8852a(rf, path); + break; +#endif + default: + break; + } + + return 0; +} + +void halrf_btc_rfk_ntfy(struct rf_info *rf, u8 phy_map, enum halrf_rfk_type type, + enum halrf_rfk_process process) +{ + u32 cnt = 0; + u8 band; + /*idx : use BIT mask for RF path PATH A: 1, PATH B:2, PATH AB:3*/ + + band = rf->hal_com->band[(phy_map & 0x30) >> 5].cur_chandef.band; + + phy_map = (band << 6) | phy_map; + + RF_DBG(rf, DBG_RF_RFK, "[RFK] RFK notify (%s / PHY%d / K_type = %d / path_idx = %d / process = %s)\n", + band == 0 ? "2G" : (band == 1 ? "5G" : "6G"), (phy_map & 0x30) >> 5, type, + phy_map & 0xf, process == 0 ? "RFK_STOP" : (process == 1 ? "RFK_START" : + (process == 2 ? "ONE-SHOT_START" : "ONE-SHOT_STOP"))); +#if 1 + if (process == RFK_START && rf->is_bt_iqk_timeout == false) { + while (halrf_btc_ntfy(rf, phy_map, type, process) == 0 && cnt < 2500) { + halrf_delay_us(rf, 40); + cnt++; + } + if (cnt == 2500) { + RF_DBG(rf, DBG_RF_RFK, "[RFK] Wait BT IQK timeout!!!!\n"); + rf->is_bt_iqk_timeout = true; + } + } else + halrf_btc_ntfy(rf, phy_map, type, process); +#endif +} + +void halrf_fcs_init(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_fcs_init_8852a(rf); +#endif +} + +void halrf_fast_chl_sw_backup(struct rf_info *rf, u8 chl_index, u8 t_index) +{ + u32 t[2]; + + t[0] = chl_index; + t[1] = t_index; + + halrf_fill_h2c_cmd(rf, 8, FWCMD_H2C_BACKUP_RFK, 0xa, H2CB_TYPE_DATA, t); + RF_DBG(rf, DBG_RF_RFK, "FWCMD_H2C_BACKUP_RFK chl=%d t=%d\n", chl_index, t_index); +} + +void halrf_fast_chl_sw_reload(struct rf_info *rf, u8 chl_index, u8 t_index) +{ + u32 t[2]; + + t[0] = chl_index; + t[1] = t_index; + + halrf_fill_h2c_cmd(rf, 8, FWCMD_H2C_RELOAD_RFK, 0xa, H2CB_TYPE_DATA, t); + RF_DBG(rf, DBG_RF_RFK, "FWCMD_H2C_RELOAD_RFK chl=%d t=%d\n", chl_index, t_index); +} + +void halrf_quick_check_rf(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) + halrf_quick_check_rfrx_8852a(rf); +#endif +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) + halrf_quick_checkrf_8852b(rf); +#endif +} + +void halrf_wifi_event_notify(void *rf_void, + enum phl_msg_evt_id event, enum phl_phy_idx phy_idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + if (event == MSG_EVT_SCAN_START) { + halrf_tssi_default_txagc(rf, phy_idx, true); + halrf_tssi_set_avg(rf, phy_idx, true); + halrf_dpk_track_onoff(rf, false); + } else if (event == MSG_EVT_SCAN_END) { + halrf_tssi_default_txagc(rf, phy_idx, false); + halrf_tssi_set_avg(rf, phy_idx, false); + halrf_dpk_track_onoff(rf, true); + } else if (event == MSG_EVT_DBG_RX_DUMP) { + halrf_quick_check_rf(rf); + } else if (event == MSG_EVT_SWCH_START) { + halrf_tssi_backup_txagc(rf, phy_idx, true); + } +} + +void halrf_write_fwofld_start(struct rf_info *rf) +{ +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0); + + rf->fw_ofld_enable = true; + + RF_DBG(rf, DBG_RF_FW, "======> %s fw_ofld=%d rf->fw_ofld_enable=%d\n", + __func__, fw_ofld, rf->fw_ofld_enable); +#endif +} + +void halrf_write_fwofld_end(struct rf_info *rf) +{ +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + struct rtw_mac_cmd cmd = {0}; + struct halrf_fw_offload *fwofld_info = &rf->fwofld; + bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0); + u32 rtn; + + RF_DBG(rf, DBG_RF_FW, + "======>%s src=%d type=%d lc=%d rf_path=%d\n", + __func__, fwofld_info->src, fwofld_info->type, + fwofld_info->lc, fwofld_info->rf_path); + + RF_DBG(rf, DBG_RF_FW, + "======>%s offset=0x%x mask=0x%x value=0x%x fw_ofld=%d\n", + __func__, fwofld_info->offset, fwofld_info->mask, + fwofld_info->value, fw_ofld); + + cmd.src = fwofld_info->src; + cmd.type = fwofld_info->type; + cmd.lc = 1; + cmd.rf_path = fwofld_info->rf_path; + cmd.offset = fwofld_info->offset; + cmd.value = fwofld_info->value; + cmd.mask = fwofld_info->mask; + + if (fw_ofld) { + rtn = halrf_mac_add_cmd_ofld(rf, &cmd); + if (rtn) { + RF_WARNING("======>%s return fail error code = %d !!!\n", + __func__, rtn); + } + } + + rf->fw_ofld_enable = false; +#endif +} + +void halrf_ctrl_bw_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch, + enum band_type band, enum channel_width bw) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + halrf_ctl_ch(rf, central_ch); + halrf_ctl_bw(rf, bw); + halrf_rxbb_bw(rf, phy, bw); +} + +u32 halrf_test_event_trigger(void *rf_void, + enum phl_phy_idx phy, enum halrf_event_idx idx, enum halrf_event_func func) { + + struct rf_info *rf = (struct rf_info *)rf_void; + + switch (idx) { + case RF_EVENT_PWR_TRK: + if (func == RF_EVENT_OFF) + halrf_tssi_disable(rf, phy); + else if (func == RF_EVENT_ON) + halrf_tssi_enable(rf, phy); + else if (func == RF_EVENT_TRIGGER) + halrf_tssi_trigger(rf, phy); + break; + + case RF_EVENT_IQK: + if (func == RF_EVENT_OFF) + halrf_iqk_onoff(rf, true); + else if (func == RF_EVENT_ON) + halrf_iqk_onoff(rf, false); + else if (func == RF_EVENT_TRIGGER) { + halrf_nbiqk_enable(rf, false); + halrf_iqk_trigger(rf, phy, false); + } + break; + + case RF_EVENT_DPK: + if (func == RF_EVENT_OFF) + halrf_dpk_onoff(rf, false); + else if (func == RF_EVENT_ON) + halrf_dpk_onoff(rf, true); + else if (func == RF_EVENT_TRIGGER) + halrf_dpk_trigger(rf, phy, false); + break; + + case RF_EVENT_TXGAPK: + if (func == RF_EVENT_OFF) + halrf_gapk_disable(rf, phy); + else if (func == RF_EVENT_ON) + halrf_gapk_enable(rf, phy); + else if (func == RF_EVENT_TRIGGER) + halrf_gapk_trigger(rf, phy, true); + break; + + case RF_EVENT_DACK: + if (func == RF_EVENT_OFF) + halrf_dack_onoff(rf, false); + else if (func == RF_EVENT_ON) + halrf_dack_onoff(rf, true); + else if (func == RF_EVENT_TRIGGER) + halrf_dack_trigger(rf, true); + break; + + default: + break; + } + return 0; +} + + diff --git a/phl/hal_g6/phy/rf/halrf_api.h b/phl/hal_g6/phy/rf/halrf_api.h new file mode 100644 index 0000000..37ec202 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_api.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_API_H_ +#define _HALRF_API_H_ +/*@--------------------------[Define] ---------------------------------------*/ +#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a)) +/*@--------------------------[Enum]------------------------------------------*/ +enum phlrf_lna_set { + PHLRF_LNA_DISABLE = 0, + PHLRF_LNA_ENABLE = 1, +}; + +enum halrf_rfk_type { + RF_BTC_IQK = 0, + RF_BTC_LCK = 1, + RF_BTC_DPK = 2, + RF_BTC_TXGAPK = 3, + RF_BTC_DACK = 4, + RF_BTC_RXDCK = 5, + RF_BTC_TSSI = 6 +}; + +enum halrf_rfk_process { + RFK_STOP = 0, + RFK_START = 1, + RFK_ONESHOT_START = 2, + RFK_ONESHOT_STOP = 3 +}; + +enum halrf_event_idx { + RF_EVENT_PWR_TRK = 0, + RF_EVENT_IQK = 1, + RF_EVENT_DPK = 2, + RF_EVENT_TXGAPK = 3, + RF_EVENT_DACK = 4 +}; + +enum halrf_event_func { + RF_EVENT_OFF = 0, + RF_EVENT_ON = 1, + RF_EVENT_TRIGGER = 2 +}; + + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct rf_info; + +u32 phlrf_psd_log2base(struct rf_info *rf, u32 val); + +void phlrf_rf_lna_setting(struct rf_info *rf, enum phlrf_lna_set type); + +void halrf_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num); + +void halrf_bkprf(struct rf_info *rf, u32 *bp_reg, u32 bp[][4], u32 reg_num, u32 path_num); + +void halrf_reload_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num); + +void halrf_reload_bkprf(struct rf_info *rf, + u32 *bp_reg, + u32 bp[][4], + u32 reg_num, + u8 path_num); + +u8 halrf_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx); + +void halrf_tmac_tx_pause(struct rf_info *rf, enum phl_phy_idx band_idx, bool pause); + +void halrf_trigger_thermal(struct rf_info *rf); + +u8 halrf_only_get_thermal(struct rf_info *rf, enum rf_path path); + +void halrf_thermal_period(struct rf_info *rf); + +void halrf_btc_rfk_ntfy(struct rf_info *rf, u8 phy_map, enum halrf_rfk_type type, + enum halrf_rfk_process process); +void halrf_fcs_init(struct rf_info *rf); +void halrf_fast_chl_sw_backup(struct rf_info *rf, u8 chl_index, u8 t_index); +void halrf_fast_chl_sw_reload(struct rf_info *rf, u8 chl_index, u8 t_index); + +/*FW Offload*/ +void halrf_write_fwofld_start(struct rf_info *rf); +void halrf_write_fwofld_end(struct rf_info *rf); + +void halrf_quick_check_rf(void *rf_void); +#endif diff --git a/phl/hal_g6/phy/rf/halrf_dack.h b/phl/hal_g6/phy/rf/halrf_dack.h new file mode 100644 index 0000000..7f08c95 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dack.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_DACK_H_ +#define _HALRF_DACK_H_ + +/*@--------------------------Define Parameters-------------------------------*/ + + +/*@-----------------------End Define Parameters-----------------------*/ + +struct halrf_dack_info { + bool dack_done; + u8 msbk_d[2][2][16]; + u8 dadck_d[2][2]; /*path/IQ*/ + u16 addck_d[2][2]; /*path/IQ*/ + u16 biask_d[2][2]; /*path/IQ*/ + u32 dack_cnt; + u32 dack_time; + bool addck_timeout[2]; + bool dadck_timeout[2]; + bool msbk_timeout[2]; + bool dack_fail; +}; + + +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_dbg.c b/phl/hal_g6/phy/rf/halrf_dbg.c new file mode 100644 index 0000000..81b982f --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dbg.c @@ -0,0 +1,1439 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "halrf_precomp.h" + +void halrf_dbg_setting_init(struct rf_info *rf) +{ + rf->fw_dbg_component = 0; + rf->dbg_component = + /*DBG_RF_TX_PWR_TRACK | */ + /*DBG_RF_IQK | */ + /*DBG_RF_LCK | */ + /*DBG_RF_DPK | */ + /*DBG_RF_TXGAPK | */ + /*DBG_RF_DACK | */ + /*DBG_RF_DPK_TRACK | */ + /*DBG_RF_RXDCK | */ + /*DBG_RF_RFK | */ + /*DBG_RF_MP | */ + /*DBG_RF_TMP | */ + /*DBG_RF_INIT | */ + /*DBG_RF_POWER | */ + /*DBG_RF_RXGAINK | */ + /*DBG_RF_THER_TRIM | */ + /*DBG_RF_PABIAS_TRIM | */ + /*DBG_RF_TSSI_TRIM | */ + /*DBG_RF_PSD | */ + /*DBG_RF_CHK | */ + /*DBG_RF_XTAL_TRACK | */ + 0; + + rf->cmn_dbg_msg_cnt = HALRF_WATCHDOG_PERIOD; + rf->cmn_dbg_msg_period = HALRF_WATCHDOG_PERIOD; +} + +void halrf_iqk_log(struct rf_info *rf) +{ +#if 0 + struct halrf_iqk_info *iqk_info = &rf->iqk; + + /* IQK INFO */ + RF_DBG(rf, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======"); + RF_DBG(rf, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count", + iqk_info->iqk_cnt, iqk_info->iqk_fail_cnt); + RF_DBG(rf, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk", + (iqk_info->segment_iqk) ? "True" : "False"); +#endif +} + +void halrf_lck_log(struct rf_info *rf) +{ + RF_DBG(rf, DBG_RF_LCK, "%-20s\n", "====== LCK Info ======"); +} + +void halrf_support_ability(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 value[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) + if (input[i + 1]) + _os_sscanf(input[i + 1], "%d", &value[i]); + + if (value[0] == 100) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[RF Supportability]\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "00. (( %s ))Power Tracking\n", + ((rf->support_ability & HAL_RF_TX_PWR_TRACK) ? + ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "01. (( %s ))IQK\n", + ((rf->support_ability & HAL_RF_IQK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "02. (( %s ))LCK\n", + ((rf->support_ability & HAL_RF_LCK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "03. (( %s ))DPK\n", + ((rf->support_ability & HAL_RF_DPK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "04. (( %s ))HAL_RF_TXGAPK\n", + ((rf->support_ability & HAL_RF_TXGAPK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "05. (( %s ))HAL_RF_DACK\n", + ((rf->support_ability & HAL_RF_DACK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "06. (( %s ))DPK_TRACK\n", + ((rf->support_ability & HAL_RF_DPK_TRACK) ? ("V") : + ("."))); +#ifdef CONFIG_2G_BAND_SHIFT + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "07. (( %s ))HAL_2GBAND_SHIFT\n", + ((rf->support_ability & HAL_2GBAND_SHIFT) ? ("V") : + ("."))); +#endif + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "08. (( %s ))HAL_RF_RXDCK\n", + ((rf->support_ability & HAL_RF_RXDCK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "13. (( %s ))HAL_RF_THER_TRIM\n", + ((rf->support_ability & HAL_RF_THER_TRIM) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "14. (( %s ))HAL_RF_PABIAS_TRIM\n", + ((rf->support_ability & HAL_RF_PABIAS_TRIM) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "15. (( %s ))HAL_RF_TSSI_TRIM\n", + ((rf->support_ability & HAL_RF_TSSI_TRIM) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "17. (( %s ))HAL_RF_TSSI_TRK\n", + ((rf->support_ability & HAL_RF_TSSI_TRK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "18. (( %s ))HAL_RF_XTAL_TRACK\n", + ((rf->support_ability & HAL_RF_XTAL_TRACK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "19. (( %s ))HAL_RF_TX_SHAPE\n", + ((rf->support_ability & HAL_RF_TX_SHAPE) ? ("V") : + ("."))); + } else { + if (value[1] == 1) /* enable */ + rf->support_ability |= BIT(value[0]); + else if (value[1] == 2) /* disable */ + rf->support_ability &= ~(BIT(value[0])); + else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[Warning!!!] 1:enable, 2:disable\n"); + } + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Curr-RF_supportability = 0x%x\n\n", rf->support_ability); + + *_used = used; + *_out_len = out_len; +} + +void halrf_dbg_trace(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 one = 1; + u32 used = *_used; + u32 out_len = *_out_len; + u32 value[10] = {0}; + u8 i; + + for (i = 0; i < 5; i++) + if (input[i + 1]) + _os_sscanf(input[i + 1], "%d", &value[i]); + + if (value[0] == 100) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[RF Debug Trace Selection]\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "00. (( %s ))TX_PWR_TRACK\n", + ((rf->dbg_component & DBG_RF_TX_PWR_TRACK) ? ("V") : + ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "01. (( %s ))IQK\n", + ((rf->dbg_component & DBG_RF_IQK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "02. (( %s ))LCK\n", + ((rf->dbg_component & DBG_RF_LCK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "03. (( %s ))DPK\n", + ((rf->dbg_component & DBG_RF_DPK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "04. (( %s ))TXGAPK\n", + ((rf->dbg_component & DBG_RF_TXGAPK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "05. (( %s ))DACK\n", + ((rf->dbg_component & DBG_RF_DACK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "06. (( %s ))DPK_TRACK\n", + ((rf->dbg_component & DBG_RF_DPK_TRACK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "08. (( %s ))RXDCK\n", + ((rf->dbg_component & DBG_RF_RXDCK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "09. (( %s ))RFK\n", + ((rf->dbg_component & DBG_RF_RFK) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "10. (( %s ))INIT\n", + ((rf->dbg_component & DBG_RF_INIT) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "11. (( %s ))POWER\n", + ((rf->dbg_component & DBG_RF_POWER) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "28. (( %s ))FW\n", + ((rf->dbg_component & DBG_RF_FW) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "29. (( %s ))MP\n", + ((rf->dbg_component & DBG_RF_MP) ? ("V") : ("."))); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "30. (( %s ))TMP\n", + ((rf->dbg_component & DBG_RF_TMP) ? ("V") : ("."))); + + } else if (value[0] == 101) { + rf->dbg_component = 0; + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Disable all DBG COMP\n"); + } else { + if (value[1] == 1) /*enable*/ + rf->dbg_component |= (one << value[0]); + else if (value[1] == 2) /*disable*/ + rf->dbg_component &= ~(one << value[0]); + } + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Curr-RF_Dbg_Comp = 0x%x\n", rf->dbg_component); + + *_used = used; + *_out_len = out_len; +} + +void halrf_dump_rfk_reg(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 addr = 0; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===================[ RFK Reg start ]===================\n"); + + for (addr = 0x8000; addr < 0xa000; addr += 0x10) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr, + halrf_rreg(rf, addr, MASKDWORD), + halrf_rreg(rf, addr + 0x4, MASKDWORD), + halrf_rreg(rf, addr + 0x8, MASKDWORD), + halrf_rreg(rf, addr + 0xc, MASKDWORD)); + + *_used = used; + *_out_len = out_len; +} + +void _halrf_dpk_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dpk_info *dpk = &rf->dpk; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 dpk_ver = 0; + u32 rf_para = 0; + u32 rfk_init_ver = 0; + u8 path, kidx; + u32 rf_para_min = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + dpk_ver = DPK_VER_8852A; + rf_para_min = 16; + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + ic_name = "8852B"; + dpk_ver = DPK_VER_8852B; + break; +#endif + default: + break; + } + + rf_para = halrf_get_radio_reg_ver(rf); + rfk_init_ver = halrf_get_nctl_reg_ver(rf); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ DPK info %s ]===============\n", ic_name); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "DPK Ver", dpk_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d (%s)\n", + "RF Para Ver", rf_para, rf_para >= rf_para_min ? "match" : "mismatch"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "RFK init ver", rfk_init_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n", + "Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g, + rf->phl_com->dev_cap.rfe_type); + + if (dpk->bp[0][0].ch == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n", + "No DPK had been done before!!!"); + return; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n", + "DPK Cal / OK / Reload", dpk->dpk_cal_cnt, dpk->dpk_ok_cnt, + dpk->dpk_reload_cnt); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "BT IQK timeout", rf->is_bt_iqk_timeout ? "Yes" : "No"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "DPD status", dpk->is_dpk_enable ? "Enable" : "Disable"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "DPD track status", (rf->support_ability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %s\n", + "DBCC / TSSI", rf->hal_com->dbcc_en ? "On" : "Off", + rf->is_tssi_mode[0] ? "On" : "Off"); + + for (path = 0; path < KPATH; path++) { + for (kidx = 0; kidx < DPK_BKUP_NUM; kidx++) { + if (dpk->bp[path][kidx].ch == 0) + break; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "=============== S%d[%d] ===============\n", path, kidx); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n", + "Band / CH / BW", dpk->bp[path][kidx].band == 0 ? "2G" : (dpk->bp[path][kidx].band == 1 ? "5G" : "6G"), + dpk->bp[path][kidx].ch, + dpk->bp[path][kidx].bw == 0 ? "20M" : (dpk->bp[path][kidx].bw == 1 ? "40M" : "80M")); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s \n", + "DPK result", dpk->bp[path][kidx].path_ok ? "OK" : "Fail"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n", + "DPK TxAGC / Gain Scaling", dpk->bp[path][kidx].txagc_dpk, dpk->bp[path][kidx].gs); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Corr (idx/val)", dpk->corr_idx[path][kidx], dpk->corr_val[path][kidx]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "DC (I/Q)", dpk->dc_i[path][kidx], dpk->dc_q[path][kidx]); + } + } + *_used = used; + *_out_len = out_len; + +} + +void halrf_dpk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 1 + char *cmd[5] = {"-h", "on", "off", "info", "trigger"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_DPK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DPK is Unsupported!!!\n"); + return; + } + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 5; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DPK is Enabled!!\n"); + halrf_dpk_onoff(rf, true); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DPK is Disabled!!\n"); + halrf_dpk_onoff(rf, false); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + _halrf_dpk_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0){ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " DPK Trigger start!!\n"); + _os_sscanf(input[1], "%d", &val); + halrf_dpk_trigger(rf, val, false); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " DPK Trigger finish!!\n"); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +#endif +} + +void halrf_rx_dck_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_rx_dck_info *rx_dck = &rf->rx_dck; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 rxdck_ver = 0; + u8 path; + u32 addr = 0; + u32 reg_05[KPATH]; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + rxdck_ver = RXDCK_VER_8852A; + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + ic_name = "8852B"; + rxdck_ver = RXDCK_VER_8852B; + break; +#endif + default: + break; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ RX_DCK info %s ]===============\n", ic_name); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "RX_DCK Ver", rxdck_ver); + + if (rx_dck->loc[0].cur_ch == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n", + "No RX_DCK had been done before!!!"); + return; + } + + for (path = 0; path < KPATH; path++) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " S%d:", path); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s / %s\n", + "Band / CH / BW / Cal", rx_dck->loc[path].cur_band == 0 ? "2G" : + (rx_dck->loc[path].cur_band == 1 ? "5G" : "6G"), + rx_dck->loc[path].cur_ch, + rx_dck->loc[path].cur_bw == 0 ? "20M" : + (rx_dck->loc[path].cur_bw == 1 ? "40M" : "80M"), + rx_dck->is_afe ? "AFE" : "RFC"); + } + + for (path = 0; path < KPATH; path++) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n---------------[ S%d DCK Value ]---------------\n", path); + reg_05[path] = halrf_rrf(rf, path, 0x5, MASKRF); + halrf_wrf(rf, path, 0x5, BIT(0), 0x0); + halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX); + + for (addr = 0; addr < 0x20; addr++) { + halrf_wrf(rf, path, 0x00, 0x07c00, addr); /*[14:10]*/ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "0x%02x | 0x%02x/ 0x%02x 0x%02x/ 0x%02x\n", addr, + halrf_rrf(rf, path, 0x92, 0xF0000), /*[19:16]*/ + halrf_rrf(rf, path, 0x92, 0x0FC00), /*[15:10]*/ + halrf_rrf(rf, path, 0x93, 0xF0000), /*[19:16]*/ + halrf_rrf(rf, path, 0x93, 0x0FC00)); /*[15:10]*/ + } + halrf_wrf(rf, path, 0x5, BIT(0), reg_05[path]); + } + *_used = used; + *_out_len = out_len; +} + +void halrf_get_rx_dck_value(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + u32 val_1 = 0, val_2 = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 reg_05[KPATH]; + + _os_sscanf(input[2], "%d", &val_1); /*RF path*/ + _os_sscanf(input[3], "%x", &val_2); /*RF 0x0*/ + + if (val_1 > 3) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Wrong path number!!\n"); + return; + } + + reg_05[val_1] = halrf_rrf(rf, val_1, 0x5, MASKRF); + + halrf_wrf(rf, val_1, 0x5, BIT(0), 0x0); + halrf_wrf(rf, val_1, 0x00, MASKRF, val_2); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Input S%d RF0x00 = 0x%x\n", val_1, val_2); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Get I : RXBB / TIA = 0x%x / 0x%x\n", + halrf_rrf(rf, val_1, 0x92, 0xF0000), /*[19:16]*/ + halrf_rrf(rf, val_1, 0x92, 0x0FC00)); /*[15:10]*/ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Get Q : RXBB / TIA = 0x%x / 0x%x\n", + halrf_rrf(rf, val_1, 0x93, 0xF0000), /*[19:16]*/ + halrf_rrf(rf, val_1, 0x93, 0x0FC00)); /*[15:10]*/ + + halrf_wrf(rf, val_1, 0x5, BIT(0), reg_05[val_1]); + + *_used = used; + *_out_len = out_len; +} + +void halrf_rx_dck_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char *cmd[6] = {"-h", "on", "off", "info", "trigger", "get"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val_1 = 0, val_2 = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_RXDCK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RX_DCK is Unsupported!!!\n"); + return; + } + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 6; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RX_DCK is Enabled!!\n"); + halrf_rx_dck_onoff(rf, true); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RX_DCK is Disabled!!\n"); + halrf_rx_dck_onoff(rf, false); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + halrf_rx_dck_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RX DCK Trigger\n"); + _os_sscanf(input[2], "%d", &val_1); + _os_sscanf(input[3], "%d", &val_2); + halrf_rx_dck_trigger(rf, val_1, (bool)val_2); + } else if (_os_strcmp(input[1], cmd[5]) == 0) { + halrf_get_rx_dck_value(rf, input, &used, output, &out_len); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + *_used = used; + *_out_len = out_len; +} + +void halrf_dack_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_dack_info *dack = &rf->dack; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 dack_ver = 0; + u32 rf_para = 0; + u32 rfk_init_ver = 0; + u8 i; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + dack_ver = DACK_VER_8852AB; + rf_para = halrf_get_radio_reg_ver(rf); + break; +#endif + default: + break; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ DACK info %s ]===============\n", ic_name); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "DACK Ver", dack_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "RF Para Ver", rf_para); + + if (dack->dack_cnt == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n", + "No DACK had been done before!!!"); + return; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "DACK count", dack->dack_cnt); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d ms\n", + "DACK processing time", dack->dack_time); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-60s = %d / %d / %d / %d / %d / %d\n", + "DACK timeout(ADDCK_0/ADDCK_1/DADCK_0/DADCK_1/MSBK_0/MSBK_1):", + dack->addck_timeout[0], dack->addck_timeout[1], + dack->dadck_timeout[0], dack->dadck_timeout[1], + dack->msbk_timeout[0], dack->msbk_timeout[1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "DACK Fail(last)", (dack->dack_fail) ? "TRUE" : "FALSE"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===============[ ADDCK result ]===============\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S0_I/ S0_Q", dack->addck_d[0][0], dack->addck_d[0][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S1_I/ S1_Q", dack->addck_d[1][0], dack->addck_d[1][1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===============[ DADCK result ]===============\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S0_I/ S0_Q", dack->dadck_d[0][0], dack->dadck_d[0][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S1_I/ S1_Q", dack->dadck_d[1][0], dack->dadck_d[1][1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===============[ biask result ]===============\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S0_I/ S0_Q", dack->biask_d[0][0], dack->biask_d[0][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n", + "S1_I/ S1_Q", dack->biask_d[1][0], dack->biask_d[1][1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===============[ MSBK result ]===============\n"); + for (i = 0; i < 16; i++) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s [%2d] = 0x%x/ 0x%x/ 0x%x/ 0x%x\n", + "S0_I/S0_Q/S1_I/S1_Q", + i, + dack->msbk_d[0][0][i], dack->msbk_d[0][1][i], + dack->msbk_d[1][0][i], dack->msbk_d[1][1][i]); + } + + *_used = used; + *_out_len = out_len; +} + +void halrf_dack_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 1 + char *cmd[5] = {"-h", "on", "off", "info", "trigger"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_DACK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DACK is Unsupported!!!\n"); + return; + } + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 5; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DPK is Enabled!!\n"); + halrf_dack_onoff(rf, true); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "DPK is Disabled!!\n"); + halrf_dack_onoff(rf, false); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + halrf_dack_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0){ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " DACKTrigger start!!\n"); + _os_sscanf(input[1], "%d", &val); + halrf_dack_trigger(rf, true); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " DACK Trigger finish!!\n"); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +#endif +} + +void _halrf_tssi_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_tssi_info *tssi_info = &rf->tssi; + struct halrf_dpk_info *dpk = &rf->dpk; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u32 bw = rf->hal_com->band[0].cur_chandef.bw; + u32 band = rf->hal_com->band[0].cur_chandef.band; + u8 txsc_ch = rf->hal_com->band[0].cur_chandef.chan; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 tssi_ver = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + tssi_ver = TSSI_VER_8852A; + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + ic_name = "8852B"; + tssi_ver = TSSI_VER_8852B; + break; +#endif + default: + break; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ TSSI info %s ]===============\n", ic_name); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "TSSI Ver", tssi_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n", + "Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g, + rf->phl_com->dev_cap.rfe_type); + + //RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + // "BT IQK timeout", rf->is_bt_iqk_timeout ? "Yes" : "No"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s/%s\n", + "TSSI status A/B", + rf->is_tssi_mode[RF_PATH_A] ? "Enable" : "Disable", + rf->is_tssi_mode[RF_PATH_B] ? "Enable" : "Disable"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %s\n", + "DBCC / DPK", rf->hal_com->dbcc_en ? "On" : "Off", + dpk->is_dpk_enable ? "On" : "Off"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s / %d\n", + "Band / CH / BW / TXSC", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"), + channel, + bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"), + txsc_ch); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n", + "TSSI DE CCK A", + tssi_info->curr_tssi_cck_de[RF_PATH_A], + tssi_info->curr_tssi_efuse_cck_de[RF_PATH_A], + tssi_info->curr_tssi_trim_de[RF_PATH_A]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n", + "TSSI DE CCK B", + tssi_info->curr_tssi_cck_de[RF_PATH_B], + tssi_info->curr_tssi_efuse_cck_de[RF_PATH_B], + tssi_info->curr_tssi_trim_de[RF_PATH_B]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n", + "TSSI DE OFDM A", + tssi_info->curr_tssi_ofdm_de[RF_PATH_A], + tssi_info->curr_tssi_efuse_ofdm_de[RF_PATH_A], + tssi_info->curr_tssi_trim_de[RF_PATH_A]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n", + "TSSI DE OFDM B", + tssi_info->curr_tssi_ofdm_de[RF_PATH_B], + tssi_info->curr_tssi_efuse_ofdm_de[RF_PATH_B], + tssi_info->curr_tssi_trim_de[RF_PATH_B]); + + halrf_get_tssi_info(rf, input, &used, output, &out_len); + + *_used = used; + *_out_len = out_len; + +} + +void halrf_tssi_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char *cmd[7] = {"-h", "on", "off", "info", "trk", "trigger", "final"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0, val1 = 0; + u8 i; + +#if 0 + if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI is Unsupported!!!\n"); + return; + } +#endif + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 7; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI is Enabled!!\n"); + halrf_tssi_enable(rf, val); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI is Disabled!!\n"); + halrf_tssi_disable(rf, val); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + _halrf_tssi_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0) { + halrf_get_tssi_trk_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[5]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI Trigger start!!\n"); + _os_sscanf(input[2], "%d", &val); + halrf_tssi_trigger(rf, val); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI Trigger finish, TSSI ON!!!\n"); + } else if (_os_strcmp(input[1], cmd[6]) == 0){ + _os_sscanf(input[1], "%d", &val); + _os_sscanf(input[2], "%d", &val1); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI Final Path%s\n", (val1 == RF_PATH_A) ? "A" : "B"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TSSI Final Path%s Result:%d\n", + (val1 == RF_PATH_A) ? "A" : "B", + halrf_tssi_get_final(rf, val, (u8)val1)); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +} + +static void _halrf_iqk_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + struct halrf_iqk_info *iqk_info = &rf->iqk; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 ver = 0; + u32 rfk_init_ver = 0; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__); + switch (hal_i->chip_id) { + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + ver = halrf_get_iqk_ver(rf); + rfk_init_ver = halrf_get_nctl_reg_ver(rf); + break; + default: + break; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ IQK info %s ]===============\n", ic_name); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "IQK Version", ver); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "RFK init ver", rfk_init_ver); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n", + "IQK Cal / Fail / Reload", iqk_info->iqk_times, iqk_info->iqk_fail_cnt, + iqk_info->reload_cnt); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n", + "S0 Band / CH / BW", iqk_info->iqk_band[0]== 0 ? "2G" : (iqk_info->iqk_band[0] == 1 ? "5G" : "6G"), + iqk_info->iqk_ch[0], + iqk_info->iqk_bw[0] == 0 ? "20M" : (iqk_info->iqk_bw[0] == 1 ? "40M" : "80M")); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S0 NB/WB TXIQK", iqk_info->is_wb_txiqk[0]? "WBTXK" : "NBTXK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S0 NB/WB RXIQK", iqk_info->is_wb_rxiqk[0]? "WBRXK" : "NBRXK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S0 LOK status", (iqk_info->lok_cor_fail[0][0] | iqk_info->lok_fin_fail[0][0]) ? "Fail" : "Pass"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S0 TXK status", iqk_info->iqk_tx_fail[0][0]? "Fail" : "Pass"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S0 RXK status", iqk_info->iqk_rx_fail[0][0]? "Fail" : "Pass"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n", + "S1 Band / CH / BW", iqk_info->iqk_band[1]== 0 ? "2G" : (iqk_info->iqk_band[1] == 1 ? "5G" : "6G"), + iqk_info->iqk_ch[1], + iqk_info->iqk_bw[1] == 0 ? "20M" : (iqk_info->iqk_bw[1] == 1 ? "40M" : "80M")); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S1 NB/WB TXIQK", iqk_info->is_wb_txiqk[1]? "WBTXK" : "NBTXK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S1 NB/WB RXIQK", iqk_info->is_wb_rxiqk[1]? "WBRXK" : "NBRXK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S1 LOK status", (iqk_info->lok_cor_fail[0][1] | iqk_info->lok_fin_fail[0][1]) ? "Fail" : "Pass"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S1 TXK status", iqk_info->iqk_tx_fail[0][1]? "Fail" : "Pass"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "S1 RXK status", iqk_info->iqk_rx_fail[0][1]? "Fail" : "Pass"); + *_used = used; + *_out_len = out_len; + return; +} +void halrf_iqk_bypass_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 1 + char *cmd[4] = {"-h", "lok", "txk", "rxk"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_IQK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "IQK is Unsupported!!!\n"); + return; + } + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 4; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "LOK is Bypass!!\n"); + halrf_iqk_lok_bypass(rf, 0x0); + halrf_iqk_lok_bypass(rf, 0x1); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TOK is Bypass!!\n"); + halrf_iqk_tx_bypass(rf, 0x0); + halrf_iqk_tx_bypass(rf, 0x1); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RXK is Bypass!!\n"); + halrf_iqk_rx_bypass(rf, 0x0); + halrf_iqk_rx_bypass(rf, 0x1); + } else { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + } + *_used = used; + *_out_len = out_len; +#endif +} + +void halrf_iqk_klog_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 1 + char *cmd[6] = {"-h", "fft", "sram", "xym", "cfir", "off"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_IQK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "IQK is Unsupported!!!\n"); + return; + } + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 6; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "FFT message turn on!!\n"); + halrf_iqk_fft_enable(rf, true); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Sram message turn on!!\n"); + halrf_iqk_sram_enable(rf, true); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "XYM message turn on!!\n"); + halrf_iqk_xym_enable(rf, true); + } else if (_os_strcmp(input[1], cmd[4]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "CFIR message turn on!!\n"); + halrf_iqk_cfir_enable(rf, true); + } else if (_os_strcmp(input[1], cmd[4]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "all message turn off!!\n"); + halrf_iqk_fft_enable(rf, false); + halrf_iqk_sram_enable(rf, false); + halrf_iqk_xym_enable(rf, false); + halrf_iqk_cfir_enable(rf, false); + } else { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + } + *_used = used; + *_out_len = out_len; +#endif +} +void halrf_iqk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char *cmd[7] = {"-h", "on", "off", "info", "trigger", "nbiqk", "rxevm"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + u8 rxevm = 0x0; + + if (!(rf->support_ability & HAL_RF_IQK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "IQK is Unsupported!!!\n"); + return; + } + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 8; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "IQK is Enabled!!\n"); + halrf_iqk_onoff(rf, true); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "IQK is Disabled!!\n"); + halrf_iqk_onoff(rf, false); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + _halrf_iqk_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0){ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " WBIQK Trigger start!!\n"); + halrf_nbiqk_enable(rf, false); + halrf_iqk_trigger(rf, HW_PHY_0, false); + } else if (_os_strcmp(input[1], cmd[5]) == 0){ + halrf_nbiqk_enable(rf, true); + halrf_iqk_trigger(rf, val, false); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " NBIQK Trigger!!\n"); + } else if (_os_strcmp(input[1], cmd[6]) == 0){ + rxevm = halrf_iqk_get_rxevm( rf); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " RXEVM = -%d dB!!\n", rxevm); + } else { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + } + *_used = used; + *_out_len = out_len; +} + +void halrf_pwr_table_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + char *cmd[7] = {"-h", "rate", "limit", "limit_ru", "set_all", "set", "txshape"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u32 tmp; + u8 i; + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 7; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Power by rate info\n"); + halrf_pwr_by_rate_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Power limit info\n"); + halrf_pwr_limit_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Power limit RU info\n"); + halrf_pwr_limit_ru_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0) { + pwr->fix_power[RF_PATH_A] = false; + pwr->fix_power_dbm[RF_PATH_A] = 0; + + pwr->fix_power[RF_PATH_B] = false; + pwr->fix_power_dbm[RF_PATH_B] = 0; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Reset Power by Rate, Power limit and Power Limit RU to Default\n"); + halrf_set_power(rf, HW_PHY_0, PWR_BY_RATE); + halrf_set_power(rf, HW_PHY_0, PWR_LIMIT); + halrf_set_power(rf, HW_PHY_0, PWR_LIMIT_RU); +#ifndef RTW_FLASH_98D + //halrf_set_power(rf, HW_PHY_1, PWR_BY_RATE); + //halrf_set_power(rf, HW_PHY_1, PWR_LIMIT); + //halrf_set_power(rf, HW_PHY_1, PWR_LIMIT_RU); +#endif + } else if (_os_strcmp(input[1], cmd[5]) == 0) { + _os_sscanf(input[2], "%d", &tmp); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set Power by Rate, Power limit and Power Limit RU %d.%ddBm\n", + tmp / 2, tmp * 10 / 2 % 10); + + halrf_set_fix_power_to_struct(rf, HW_PHY_0, (s8)tmp); + } else if (_os_strcmp(input[1], cmd[6]) == 0) { + _os_sscanf(input[2], "%d", &tmp); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set TX Shape = 255, disable Set Tx shape function\n"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Set TX Shape = %d\n", tmp); + + halrf_set_tx_shape(rf, (u8)tmp); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +} + +void halrf_rfk_check_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 1 + char *cmd[3] = {"-h", "backup", "check"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 3; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RFK backup!!\n"); + halrf_rfk_reg_backup(rf); + halrf_rfc_reg_backup(rf); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RFK check!!\n"); +#if 1 + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[RFK]DACK reg check : %s \n", (halrf_dack_reg_check_fail(rf)) ? "FAIL" : "OK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[RFK]RFK reg check : %s \n", (halrf_rfk_reg_check_fail(rf))?"FAIL" : "OK"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[RFK]RFC reg check : %s \n", (halrf_rfc_reg_check_fail(rf))?"FAIL" : "OK"); +#endif + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +#endif +} + +void halrf_test_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if 0 + + u32 used = *_used; + u32 out_len = *_out_len; + + u32 val[10] = {0}; + u8 i; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + HALRF_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]); + } + + if (val[0] == 0) { + halrf_rfk_chl_thermal(rf, (u8)val[1], (u8)val[2]); + }else if (val[0] == 1) { + halrf_rfk_recovery_chl_thermal(rf, (u8)val[1], (u8)val[2]); + } + + *_used = used; + *_out_len = out_len; +#endif +} + +void _halrf_gapk_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + struct halrf_gapk_info *txgapk_info = &rf->gapk; + struct halrf_iqk_info *iqk_info = &rf->iqk; + u8 i; + u8 channel = rf->hal_com->band[0].cur_chandef.center_ch; + u32 bw = rf->hal_com->band[0].cur_chandef.bw; + u32 band = rf->hal_com->band[0].cur_chandef.band; + + u32 used = *_used; + u32 out_len = *_out_len; + char *ic_name = NULL; + u32 txgapk_ver = 0; + u32 rf_para = 0; + u32 rfk_init_ver = 0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + ic_name = "8852A"; + txgapk_ver = TXGAPK_VER_8852A; + rf_para = halrf_get_radio_reg_ver(rf); + rfk_init_ver = halrf_get_nctl_reg_ver(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + ic_name = "8852B"; + txgapk_ver = TXGAPK_VER_8852B; + rf_para = halrf_get_radio_reg_ver(rf); + rfk_init_ver = halrf_get_nctl_reg_ver(rf); + break; +#endif + default: + break; + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "\n===============[ TxGapK info %s ]===============\n", ic_name); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "TxGapK Ver", txgapk_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "RF Para Ver", rf_para); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n", + "RFK init ver", rfk_init_ver); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n", + "Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g, + rf->phl_com->dev_cap.rfe_type); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n", + "Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"), + channel, + bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M")); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "=======================\n"); + /* table info */ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "iqk_info->iqk_mcc_ch[0][0]/[0][1]", iqk_info->iqk_mcc_ch[0][0], iqk_info->iqk_mcc_ch[0][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "iqk_info->iqk_mcc_ch[1][0]/[1][1]", iqk_info->iqk_mcc_ch[1][0], iqk_info->iqk_mcc_ch[1][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "iqk_info->iqk_table_idx[0]/[1]", iqk_info->iqk_table_idx[0], iqk_info->iqk_table_idx[1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "txgapk_info->txgapk_mcc_ch[0]", txgapk_info->txgapk_mcc_ch[0]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "txgapk_info->txgapk_mcc_ch[1]", txgapk_info->txgapk_mcc_ch[1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "txgapk_info->txgapk_table_idx", txgapk_info->txgapk_table_idx); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n", + "txgapk_info->ch", txgapk_info->ch[0]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "===============[ TxGapK result ]===============\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n", + "TXGapK OK(last)", (txgapk_info->is_txgapk_ok) ? "TRUE" : "FALSE"); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n", + "Read0x8010 Befr /Aftr GapK", txgapk_info->r0x8010[0], txgapk_info->r0x8010[1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[ NCTL Done Check Times R_0xbff / R_0x80fc ]\n"); + + /* txgapk_info->txgapk_chk_cnt[2][2][2]; */ /* path */ /* track pwr */ /* 0xbff8 0x80fc*/ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_0 Track", txgapk_info->txgapk_chk_cnt[0][TXGAPK_TRACK][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_TRACK][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_0 PWR",txgapk_info->txgapk_chk_cnt[0][TXGAPK_PWR][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_PWR][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_0 IQKBK", txgapk_info->txgapk_chk_cnt[0][TXGAPK_IQKBK][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_IQKBK][1]); + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_1 Track", txgapk_info->txgapk_chk_cnt[1][TXGAPK_TRACK][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_TRACK][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_1 PWR", txgapk_info->txgapk_chk_cnt[1][TXGAPK_PWR][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_PWR][1]); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n", + "Path_1 IQKBK", txgapk_info->txgapk_chk_cnt[1][TXGAPK_IQKBK][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_IQKBK][1]); + + + for (i = 0; i < 17; i++) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s [%2d] = 0x%02x/ 0x%02x/ 0x%02x/ 0x%02x\n", + "S0: Trk_d/Trk_ta/Pwr_d/Pwr_ta", + i, + txgapk_info->track_d[0][i]&0xff, txgapk_info->track_ta[0][i]&0xff, + txgapk_info->power_d[0][i]&0xff, txgapk_info->power_ta[0][i]&0xff); + } + for (i = 0; i < 17; i++) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s [%2d] = 0x%02x/ 0x%02x/ 0x%02x/ 0x%02x\n", + "S1: Trk_d/Trk_ta/Pwr_d/Pwr_ta", + i, + txgapk_info->track_d[1][i]&0xff, txgapk_info->track_ta[1][i]&0xff, + txgapk_info->power_d[1][i]&0xff, txgapk_info->power_ta[1][i]&0xff); + } + + *_used = used; + *_out_len = out_len; + +} + +void halrf_txgapk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char *cmd[5] = {"-h", "on", "off", "info", "trigger"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u8 i; + + if (!(rf->support_ability & HAL_RF_TXGAPK)) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TXGAPK is Unsupported!!!\n"); + return; + } + + if (_os_strcmp(input[1], cmd[0]) == 0) { + for (i = 1; i < 5; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %s\n", cmd[i]); + } else if (_os_strcmp(input[1], cmd[1]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TXGAPK is Enabled!!\n"); + halrf_gapk_enable(rf, val); + } else if (_os_strcmp(input[1], cmd[2]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TXGAPK is Disabled!!\n"); + halrf_gapk_disable(rf, val); + } else if (_os_strcmp(input[1], cmd[3]) == 0) { + _halrf_gapk_info(rf, input, &used, output, &out_len); + } else if (_os_strcmp(input[1], cmd[4]) == 0){ + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TXGAPK Trigger start!!\n"); + _os_sscanf(input[1], "%d", &val); + halrf_gapk_trigger(rf, val, true); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "TXGAPK Trigger finish, TXGAPK ON!!!\n"); + } else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " No CMD find!!\n"); + + *_used = used; + *_out_len = out_len; +} + +void halrf_dump_rf_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + char *cmd[1] = {"-h"}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val = 0; + u32 i; + u32 start_addr = 0, end_addr = 0, range_value = 0, path = 0; + + _os_sscanf(input[1], "%x", &path); + _os_sscanf(input[2], "%x", &start_addr); + _os_sscanf(input[3], "%x", &range_value); + end_addr = start_addr + range_value; + + if (_os_strcmp(input[1], cmd[0]) == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Command parameters :\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " : 0/1/2/3 = rf-A/B/C/D\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " : rf start offset (HEX)\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " : number of offset to dump (HEX)\n"); + } else if (path < RTW_PHL_MAX_RF_PATH) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " Dump RF Register Path:%d 0x%X ~ 0x%X\n", path, start_addr, end_addr - 1); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " See Result in DebugView or Debug Log\n"); + + for (i = start_addr; i < end_addr; i = i + 4) { + if (!(i % 4)) { + RF_DBG_VAST(out_len, used, output + used, out_len - used, + " RF-%d (0x%02X) = ", path, i); + } + + RF_DBG_VAST(out_len, used, output + used, out_len - used, + "%05X %05X %05X %05X\n", + halrf_rrf(rf, path, i, 0xfffff), + halrf_rrf(rf, path, i + 1, 0xfffff), + halrf_rrf(rf, path, i + 2, 0xfffff), + halrf_rrf(rf, path, i + 3, 0xfffff)); + } + + RF_DBG_VAST(out_len, used, output + used, out_len - used, "\n\n\n"); + + for (i = start_addr; i < end_addr; i++) { + RF_DBG_VAST(out_len, used, output + used, out_len - used, + " RF-%d (0x%02X) = %05X\n", path, i, + halrf_rrf(rf, path, i, 0xfffff)); + } + } else { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " echo rf dump -h\n"); + } + + *_used = used; + *_out_len = out_len; +} \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_dbg.h b/phl/hal_g6/phy/rf/halrf_dbg.h new file mode 100644 index 0000000..9cd7a95 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dbg.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_DBG_H__ +#define __HALRF_DBG_H__ + +/*@--------------------------[Define] ---------------------------------------*/ +#define HALRF_WATCHDOG_PERIOD 2 /*second*/ + + + +//#define RFDBG_TRACE_EN +#ifdef RFDBG_TRACE_EN + #define RF_DBG(rf, comp, fmt, ...) \ + do {\ + if(rf->dbg_component & comp)\ + _os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\ + } while (0) + + #define RF_TRACE(fmt, ...) \ + do {\ + _os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\ + } while (0) + + #define RF_WARNING(fmt, ...) \ + do {\ + _os_dbgdump("[WARNING][RF]" fmt, ##__VA_ARGS__);\ + } while (0) + + #define RF_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do {\ + _os_dbgdump(fmt, ##__VA_ARGS__);\ + } while (0) + + #define RF_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) +#else + #define RF_DBG + #define RF_TRACE + #define RF_WARNING + #define RF_DBG_CNSL /*Print on Consol,CLI */ + #define RF_DBG_VAST /*Print to Comport, Debug View*/ +#endif + + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct rf_info; +void halrf_dbg_setting_init(struct rf_info *rf); +void halrf_iqk_log(struct rf_info *rf); +void halrf_lck_log(struct rf_info *rf); +void halrf_dump_rfk_reg(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_support_ability(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_dbg_trace(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_dpk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_rx_dck_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_dack_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_tssi_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_iqk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halrf_iqk_bypass_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halrf_iqk_klog_cmd(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halrf_pwr_table_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_rfk_check_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_test_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_scanf(char *in, enum rf_scanf_type type, u32 *out); +void halrf_txgapk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); +void halrf_dump_rf_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len); + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_dbg_cmd.c b/phl/hal_g6/phy/rf/halrf_dbg_cmd.c new file mode 100644 index 0000000..8f68ec1 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dbg_cmd.c @@ -0,0 +1,397 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halrf_precomp.h" + +struct halrf_cmd_info { + char name[16]; + u8 id; +}; + +enum HALRF_CMD_ID { + HALRF_HELP, + HALRF_SUPPORTABILITY, + HALRF_DBG_COMP, + HALRF_PROFILE, + HALRF_IQK, + HALRF_IQK_DEBUG, + HALRF_DPK, + HALRF_DACK, + HALRF_DACK_DEBUG, + HALRF_RX_DCK, + HALRF_DUMP_RFK_REG, + HALRF_LO_TEST, +#ifdef CONFIG_2G_BAND_SHIFT + HAL_BAND_SHIFT, +#endif + HALRF_RCK, + HALRF_WATCHDOG, + HALRF_SINGLETONE_EN, + HALRF_IQK_BYPASS, + HALRF_IQK_KLOG, + HALRF_TSSI, + HALRF_PWR_TABLE, + HALRF_IQK_DBCC, + HALRF_RFK_CHECK, + HALRF_RFK_TEST, + HALRF_TXGAPK, + HALRF_FW_IQK, + HALRF_DUMP, + HALRF_IQK_RXIMR, + HALRF_THER, + HALRF_XTAL_TRK, + HALRF_HWTX +}; + +struct halrf_cmd_info halrf_cmd_i[] = { + {"-h", HALRF_HELP}, + {"ability", HALRF_SUPPORTABILITY}, + {"dbg", HALRF_DBG_COMP}, + {"profile", HALRF_PROFILE}, + {"iqk", HALRF_IQK}, + {"dpk", HALRF_DPK}, + {"dack", HALRF_DACK}, + {"dack_dbg", HALRF_DACK_DEBUG}, + {"rx_dck", HALRF_RX_DCK}, + {"dump_rfk_reg", HALRF_DUMP_RFK_REG}, + {"lo_test", HALRF_LO_TEST}, + {"rck", HALRF_RCK}, + {"rfk_check", HALRF_RFK_CHECK}, +#ifdef CONFIG_2G_BAND_SHIFT + {"band_shift", HAL_BAND_SHIFT}, +#endif + {"watchdog_stop", HALRF_WATCHDOG}, + {"iqk_tone", HALRF_SINGLETONE_EN}, + {"iqk_bypass", HALRF_IQK_BYPASS}, + {"iqk_klog", HALRF_IQK_KLOG}, + {"iqk_dbcc", HALRF_IQK_DBCC}, + {"iqk_rximr", HALRF_IQK_RXIMR}, + {"tssi", HALRF_TSSI}, + {"pwr_table", HALRF_PWR_TABLE}, + {"test", HALRF_RFK_TEST}, + {"txgapk", HALRF_TXGAPK}, + {"iqk_fw", HALRF_FW_IQK}, + {"dump", HALRF_DUMP}, + {"ther", HALRF_THER}, + {"xtal_trk", HALRF_XTAL_TRK}, + {"hwtx", HALRF_HWTX}, +}; + +void halrf_cmd_parser(struct rf_info *rf, char input[][RF_MAX_ARGV], + u32 input_num, char *output, u32 out_len) +{ + + struct rf_dbg_cmd_info *rf_dbg_cmd = &rf->rf_dbg_cmd_i; + + u32 used = 0; + u8 id = 0; + u32 i, val_1 = 0, val_2 = 0; + u32 halrf_ary_size = rf_dbg_cmd->cmd_size; + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n"); + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < halrf_ary_size; i++) { + if (_os_strcmp(halrf_cmd_i[i].name, input[0]) == 0) { + id = halrf_cmd_i[i].id; + break; + } + } + if (i == halrf_ary_size) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "HALRF command not found!\n"); + return; + } + } + + switch (id) { + case HALRF_HELP: { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "RF cmd ==>\n"); + + for (i = 0; i < halrf_ary_size - 1; i++) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " %-5d: %s\n", i, halrf_cmd_i[i + 1].name); + } + break; + case HALRF_SUPPORTABILITY: + halrf_support_ability(rf, input, &used, output, &out_len); + break; + case HALRF_DBG_COMP: + halrf_dbg_trace(rf, input, &used, output, &out_len); + break; + case HALRF_DUMP_RFK_REG: + halrf_dump_rfk_reg(rf, input, &used, output, &out_len); + break; + case HALRF_IQK: + halrf_iqk_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_DPK: + halrf_dpk_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_DACK: + halrf_dack_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_RX_DCK: + halrf_rx_dck_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_LO_TEST: + _os_sscanf(input[1], "%d", &val_1); + _os_sscanf(input[2], "%d", &val_2); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "S%d LO test %s!!\n", val_2, val_1 ? "on" : "off"); + halrf_lo_test(rf, (bool)val_1, val_2); + break; + case HALRF_RCK: + halrf_rck_trigger(rf, HW_PHY_0); + break; + case HALRF_WATCHDOG: + _os_sscanf(input[1], "%d", &val_1); + rf->is_watchdog_stop = (bool)val_1; + if (val_1 == true) + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Halrf watchdog STOP!!\n"); + else + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Halrf watchdog GO!!\n"); + break; + case HALRF_SINGLETONE_EN: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[IQK]single tone enable => 0: path 0; 1: path 1\n"); + _os_sscanf(input[1], "%d", &val_1); + halrf_iqk_toneleakage(rf, val_1 & 0x1); + break; + case HALRF_IQK_BYPASS: + halrf_iqk_bypass_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_IQK_KLOG: + halrf_iqk_klog_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_TSSI: + halrf_tssi_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_PWR_TABLE: + halrf_pwr_table_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_IQK_DBCC: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[IQK]dbcc enable => 0: PHY0; 1: PHY1\n"); + _os_sscanf(input[1], "%d", &val_1); + halrf_iqk_dbcc(rf, val_1 & 0x1); + break; + case HALRF_RFK_CHECK: + halrf_rfk_check_reg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_RFK_TEST: + halrf_test_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_TXGAPK: + halrf_txgapk_dbg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_FW_IQK: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[IQK] IQK TYPE => 0: DRV, 1: FW\n"); + _os_sscanf(input[1], "%d", &val_1); + halrf_enable_fw_iqk(rf, val_1 & 0x1); + break; + case HALRF_DUMP: + halrf_dump_rf_reg_cmd(rf, input, &used, output, &out_len); + break; + case HALRF_IQK_RXIMR: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "[IQK] -path -idx \n"); + _os_sscanf(input[1], "%d", &val_1); + _os_sscanf(input[2], "%d", &val_2); + i= halrf_iqk_get_rximr(rf, (u8)val_1, val_2); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + " dec, rximr = %d !!\n", i); + break; + case HALRF_THER: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Thermal A: %d\n", halrf_get_thermal(rf, RF_PATH_A)); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Thermal B: %d\n", halrf_get_thermal(rf, RF_PATH_B)); + break; + case HALRF_XTAL_TRK: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Xtal Tracking offset PHY0 : %d\n", + halrf_xtal_tracking_offset(rf, 0)); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Xtal Tracking offset PHY1 : %d\n", + halrf_xtal_tracking_offset(rf, 1)); + break; + case HALRF_HWTX: + { + u32 value[10] = {0}; + u8 i; + + for (i = 0; i < 4; i++) + if (input[i + 1]) + _os_sscanf(input[i + 1], "%d", &value[i]); + + if (_os_strcmp(input[1], "-h") == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "echo rf hwtx enable path cnt dB\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Enable / Disable = 1 / 0\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "PathA / PathB = 0 / 1\n"); + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "EX:echo rf hwtx 1 0 0 10\n"); + } + + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "==>Enable:%d Path:%d Count:%d Power:%ddB\n", value[0], value[1], value[2], value[3]); + + //halrf_tssi_hw_tx_8852a(rf, 0, path, cnt, dbm, T_HT_MF, 0, enable); + if (value[0] == 1) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "HW TX Start\n"); + + halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_TSSI, RFK_START); + halrf_tmac_tx_pause(rf, HW_PHY_0, true); + + halrf_hw_tx(rf, (u8)value[1], (u16)value[2], + (s16)(value[3] * 4), T_HT_MF, 0, 1); + } + + if (value[0] == 0) { + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "HW TX Stop\n"); + + halrf_hw_tx(rf, (u8)value[1], (u16)value[2], + (s16)(value[3] * 4), T_HT_MF, 0, 0); + + halrf_tx_mode_switch(rf, HW_PHY_0, 0); + + halrf_tmac_tx_pause(rf, HW_PHY_0, false); + halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_TSSI, RFK_STOP); + } + } + break; + default: + RF_DBG_CNSL(out_len, used, output + used, out_len - used, + "Do not support this command\n"); + break; + } + +} +void halrf_cmd_parser_init(struct rf_info *rf) +{ + struct rf_dbg_cmd_info *rf_dbg_cmd = &rf->rf_dbg_cmd_i; + + rf_dbg_cmd->cmd_size = sizeof(halrf_cmd_i) / sizeof(struct halrf_cmd_info); + +} +#if 0 +#ifndef strsep +char *strsep(char **s, const char *ct) +{ + char *sbegin = *s; + char tmp = 0; + char *end = &tmp; + + if (!sbegin) + return NULL; + + //end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + return sbegin; +} +#endif +#endif + +s32 halrf_cmd(struct rf_info *rf, char *input, char *output, u32 out_len) +{ + char *token; + u32 argc = 0; + char argv[RF_MAX_ARGC][RF_MAX_ARGV]; + + do { + token = _os_strsep(&input, ", "); //smae name in bb + if (token) { + if (_os_strlen(token) <= RF_MAX_ARGV) + _os_strcpy(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < RF_MAX_ARGC); + + if (argc == 1) + argv[0][_os_strlen(argv[0]) - 1] = '\0'; + + halrf_cmd_parser(rf, argv, argc, output, out_len); + return 0; +} + +u32 halrf_get_multiple(u8 pow, u8 base) +{ + u8 i; + u32 return_value = 1; + + for (i = 0; i < pow; i++) + return_value *= base; /*base ^ pow*/ + + return return_value; +} + +u32 halrf_str_2_dec(u8 val) +{ + if (val >= 0x30 && val <= 0x39) /*0~9*/ + return (val - 0x30); + else if (val >= 0x41 && val <= 0x46) /*A~F*/ + return (val - 0x41 + 10); + else if (val >= 0x61 && val <= 0x66) /*a~f*/ + return (val - 0x61 + 10); + else + return 1; +} + +void halrf_scanf(char *in, enum rf_scanf_type type, u32 *out) +{ + char buff[HALRF_DCMD_SCAN_LIMIT]; + u32 multiple = 1; + u8 text_num = 0; + u8 base = 10; + u8 i = 0, j = 0; + + *out = 0; + + for (i = 0; i < HALRF_DCMD_SCAN_LIMIT; i++) { + if (in[i] != 0x0) { /* 0x0 = NULL. */ + buff[i] = in[i]; + continue; + } + + if (type == DCMD_CHAR) { + *out = *in; + break; + } + + base = (type == DCMD_DECIMAL) ? 10 : 16; + text_num = i; + + for (j = 0; j < text_num; j++) { + multiple = halrf_get_multiple(text_num - 1 - j, base); + *out += halrf_str_2_dec(buff[j]) * multiple; + } + break; + } +} + diff --git a/phl/hal_g6/phy/rf/halrf_dbg_cmd.h b/phl/hal_g6/phy/rf/halrf_dbg_cmd.h new file mode 100644 index 0000000..55c2821 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dbg_cmd.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_DBG_CMD_H_ +#define _HALRF_DBG_CMD_H_ +/*@--------------------------[Define] ---------------------------------------*/ +#define RF_MAX_ARGC 20 +#define RF_MAX_ARGV 16 + +#define HALRF_SCAN halrf_scanf +#define HALRF_DCMD_SCAN_LIMIT 10 +/*@--------------------------[Enum]------------------------------------------*/ + enum rf_scanf_type +{ + DCMD_DECIMAL = 1, + DCMD_HEX = 2, + DCMD_CHAR = 3, +}; +/*@--------------------------[Structure]-------------------------------------*/ + +struct rf_dbg_cmd_info { + u8 cmd_size; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +void halrf_cmd_parser_init(struct rf_info *rf); + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_dbg_cmd_ex.h b/phl/hal_g6/phy/rf/halrf_dbg_cmd_ex.h new file mode 100644 index 0000000..bc33153 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dbg_cmd_ex.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_DBG_CMD_EX_H__ +#define __HALRF_DBG_CMD_EX_H__ +#define RF_MAX_ARGV 16 + +struct rf_info; + +s32 halrf_cmd(struct rf_info *rf, char *input, char *output, u32 out_len); + +void halrf_cmd_parser(struct rf_info *rf, char input[][RF_MAX_ARGV], + u32 input_num, char *output, u32 out_len); + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_dpk.h b/phl/hal_g6/phy/rf/halrf_dpk.h new file mode 100644 index 0000000..069eed9 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_dpk.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HALRF_DPK_H__ +#define __HALRF_DPK_H__ + +/*@--------------------------Define Parameters-------------------------------*/ +#define AVG_THERMAL_NUM_DPK 8 +#define THERMAL_DPK_AVG_NUM 1 + +#if defined (RF_8852A_SUPPORT) || defined (RF_8852B_SUPPORT) +#define KPATH 2 +#else +#define KPATH 1 +#endif +#define DPK_BKUP_NUM 2 + +enum dpk_id { + LBK_RXIQK = 0x06, + SYNC = 0x10, + MDPK_IDL = 0x11, + MDPK_MPA = 0x12, + GAIN_LOSS = 0x13, + GAIN_CAL = 0x14, + DPK_RXAGC = 0x15, + KIP_PRESET = 0x16, + KIP_RESTORE = 0x17, + DPK_TXAGC = 0x19 +}; + +struct dpk_bkup_para { + enum band_type band; /* 2.4G,5G,6G*/ + enum channel_width bw; + u8 ch; + u8 path_ok; + u8 txagc_dpk; /*txagc@dpk with path*/ + u8 ther_dpk; /*thermal@dpk with path*/ + //u8 trk_idx_dpk; /*track_idx@dpk with path*/ + //u8 ther_tssi; /*thermal@tssi with path*/ + u8 gs; + u16 pwsf; +}; + +/*@---------------------------End Define Parameters---------------------------*/ + +struct halrf_dpk_info { + + bool is_dpk_enable; + bool is_dpk_reload_en; + u8 dpk_gs[2]; /*PHY*/ + u8 ther_avg[KPATH][AVG_THERMAL_NUM_DPK]; /*path*/ + u8 pre_pwsf[KPATH]; + u8 ther_avg_idx; + u32 dpk_cal_cnt; + u32 dpk_ok_cnt; + u32 dpk_reload_cnt; + u16 dc_i[KPATH][DPK_BKUP_NUM]; /*path*/ + u16 dc_q[KPATH][DPK_BKUP_NUM]; /*path*/ + u8 corr_val[KPATH][DPK_BKUP_NUM]; /*path*/ + u8 corr_idx[KPATH][DPK_BKUP_NUM]; /*path*/ + u8 cur_idx[KPATH]; /*path*/ + + struct dpk_bkup_para bp[KPATH][DPK_BKUP_NUM]; /*path/index*/ +}; + +#endif /*__HALRF_DPK_H__*/ + diff --git a/phl/hal_g6/phy/rf/halrf_ex.c b/phl/hal_g6/phy/rf/halrf_ex.c new file mode 100644 index 0000000..7745009 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_ex.c @@ -0,0 +1,16 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + diff --git a/phl/hal_g6/phy/rf/halrf_ex.h b/phl/hal_g6/phy/rf/halrf_ex.h new file mode 100644 index 0000000..a18f35d --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_ex.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_EX_H__ +#define __HALRF_EX_H__ + +struct rf_info; + +/**************halrf.c**************/ +void halrf_watchdog(void *rf_void); +enum rtw_hal_status halrf_chl_rfk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force); +enum rtw_hal_status halrf_dack_trigger(void *rf_void, bool force); +enum rtw_hal_status halrf_rx_dck_trigger(void *rf_void, + enum phl_phy_idx phy_idx, bool is_afe); +enum rtw_hal_status halrf_iqk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force); +void halrf_lck_trigger(void *rf_void); +enum rtw_hal_status halrf_dpk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, + bool force); +enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx); +enum rtw_hal_status halrf_gapk_trigger(void *rf_void, + enum phl_phy_idx phy_idx, bool force); +enum rtw_hal_status halrf_gapk_enable(void *rf_void, + enum phl_phy_idx phy_idx); +enum rtw_hal_status halrf_gapk_disable(void *rf_void, + enum phl_phy_idx phy_idx); +void halrf_rck_trigger(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_iqk_onoff(void *rf_void, bool is_enable); +void halrf_dpk_onoff(void *rf_void, bool is_enable); +void halrf_dpk_track_onoff(void *rf_void, bool is_enable); +void halrf_dpk_switch(void *rf_void, bool is_enable); +void halrf_dpk_init(void *rf_void); +void halrf_rx_dck_onoff(void *rf_void, bool is_enable); +void halrf_gapk_onoff(void *rf_void, bool is_enable); +void halrf_dack_onoff(void *rf_void, bool is_enable); +void halrf_tssi_onoff(void *rf_void, bool is_enable); +bool halrf_get_iqk_onoff(void *rf_void); +bool halrf_get_dpk_onoff(void *rf_void); +bool halrf_get_dpk_track_onoff(void *rf_void); +bool halrf_get_gapk_onoff(void *rf_void); +bool halrf_get_dack_onoff(void *rf_void); +bool halrf_get_tssi_onoff(void *rf_void); +void halrf_lo_test(void *rf_void, bool is_on, enum rf_path path); +int halrf_get_predefined_pw_lmt_regu_type_from_str(const char *str); +const char * const *halrf_get_predefined_pw_lmt_regu_type_str_array(u8 *num); +const char *halrf_get_pw_lmt_regu_type_str(struct rf_info *rf, u8 band); +s8 halrf_get_power_by_rate(struct rf_info *rf, + enum phl_phy_idx phy, + u8 rf_path, u16 rate, u8 dcm, u8 offset); +s8 halrf_get_power_by_rate_band(struct rf_info *rf, + enum phl_phy_idx phy, u16 rate, u8 dcm, u8 offset, u32 band); +s8 halrf_get_power_limit(struct rf_info *rf, + enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth, + u8 beamforming, u8 tx_num, u8 channel); +s8 halrf_get_power_limit_ru(struct rf_info *rf, + enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth, + u8 tx_num, u8 channel); +s16 halrf_get_power(void *rf_void, + u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth, + u8 beamforming, u8 channel); +u8 halrf_get_thermal(void *rf_void, u8 rf_path); +u32 halrf_get_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path); +s32 halrf_get_online_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path, s32 dbm, s32 puot); +void halrf_set_tssi_de_for_tx_verify(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de, u8 path); +void halrf_set_tssi_de_offset(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de_offset, u8 path); +void halrf_set_tssi_avg_mp(void *rf_void, enum phl_phy_idx phy_idx, s32 xdbm); + +void halrf_set_rx_gain_offset_for_rx_verify(void *rf_void, enum phl_phy_idx phy, + s8 rx_gain_offset, u8 path); +void halrf_set_power_track(void *rf_void, enum phl_phy_idx phy_idx, u8 value); +u8 halrf_get_power_track(void *rf_void); +void halrf_tssi_get_efuse_ex(void *rf_void, enum phl_phy_idx phy_idx); +bool halrf_tssi_check_efuse_data(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_set_ref_power_to_struct(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_bf_config_rf(void *rf_void); +void halrf_rfk_reg_backup(void *rf_void); +void halrf_rfc_reg_backup(void *rf_void); +bool halrf_rfc_reg_check_fail(void *rf_void); +bool halrf_rfk_reg_check_fail(void *rf_void); +bool halrf_dack_reg_check_fail(void *rf_void); +bool halrf_rfk_chl_thermal(void *rf_void, u8 chl_index, u8 ther_index); +void halrf_rfk_recovery_chl_thermal(void *rf_void, u8 chl_index); +u8 halrf_fcs_get_thermal_index(void *rf_void); + +/**************halrf_init.c**************/ +enum rtw_hal_status halrf_dm_init(void *rf_void); +enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **rf_out); +void halrf_deinit(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void *rf); +/**************halrf_hw_cfg.c**************/ +bool halrf_init_reg_by_hdr(void *rf_void); +bool halrf_nctl_init_reg_by_hdr(void *rf_void); +bool halrf_config_radio(void *rf_void, enum phl_phy_idx phy); +bool halrf_config_radio_a_reg(void *rf_void, bool is_form_folder, + u32 folder_len, u32 *folder_array); +bool halrf_config_radio_b_reg(void *rf_void, bool is_form_folder, + u32 folder_len, u32 *folder_array); +bool halrf_config_store_power_by_rate(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array); +bool halrf_config_store_power_limit(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array); +bool halrf_config_store_power_limit_ru(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array); +bool halrf_config_store_power_track(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array); +bool halrf_config_store_xtal_track(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array); +void halrf_gapk_save_tx_gain(struct rf_info *rf); +void halrf_gapk_reload_tx_gain(struct rf_info *rf); +/*******************************************/ +void halrf_dack_recover(void *rf_void, + u8 offset, + enum rf_path path, + u32 val, + bool reload); + +bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table); + +bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx); + +void halrf_set_power_table_switch(struct rf_info *rf, + enum phl_phy_idx phy, u8 pwr_by_rate, u8 pwr_limt); + +bool halrf_get_efuse_info(void *rf_void, u8 *efuse_map, + enum rtw_efuse_info id, void *value, u32 length, + u8 autoload_status); + +bool halrf_set_dbcc(void *rf_void, bool dbcc_en); + +bool halrf_wl_tx_power_control(void *rf_void, u32 tx_power_val); + +void halrf_get_efuse_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx); + +void halrf_get_efuse_trim(void *rf_void, enum phl_phy_idx phy_idx); + +void halrf_do_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx); + +enum rtw_hal_status halrf_dpk_tracking(void *rf_void); + +enum rtw_hal_status halrf_tssi_tracking(void *rf_void); + +enum rtw_hal_status halrf_tssi_tracking_clean(void *rf_void, s16 power_dbm); + +u8 halrf_get_default_rfe_type(void *rf_void); + +u8 halrf_get_default_xtal(void *rf_void); + +void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf, + enum phl_phy_idx phy); + +void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf, + enum phl_phy_idx phy); +enum rtw_hal_status halrf_iqk_tracking(void *rf_void); + +bool halrf_iqk_get_ther_rek(void *rf_void); + +void halrf_psd_init(void *rf_void, enum phl_phy_idx phy, + u8 path, u8 iq_path, u32 avg, u32 fft); + +void halrf_psd_restore(void *rf_void, enum phl_phy_idx phy); + +u32 halrf_psd_get_point_data(void *rf_void, enum phl_phy_idx phy, s32 point); + +void halrf_psd_query(void *rf_void, enum phl_phy_idx phy, + u32 point, u32 start_point, u32 stop_point, u32 *outbuf); + +void halrf_config_radio_to_fw(void *rf_void); + +void halrf_set_fix_power_to_struct(void *rf_void, + enum phl_phy_idx phy, s8 dbm); + +void halrf_pwr_by_rate_info(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_pwr_limit_info(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_pwr_limit_ru_info(struct rf_info *rf, + char input[][16], u32 *_used, char *output, u32 *_out_len); + +void halrf_get_tssi_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void halrf_get_tssi_trk_info(struct rf_info *rf, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void halrf_set_tx_shape(struct rf_info *rf, u8 tx_shape_idx); + +void halrf_disconnect_notify(void *rf_void, struct rtw_chan_def *chandef); +bool halrf_check_mcc_ch(void *rf_void, struct rtw_chan_def *chandef ); +void halrf_ctl_bw(void *rf_void, enum channel_width bw); +void halrf_ctl_ch(void *rf_void, u8 central_ch); +void halrf_rxbb_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw); +void halrf_ctrl_bw_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch, + enum band_type band, enum channel_width bw); +void halrf_fw_ntfy(void *rf_void, enum phl_phy_idx phy_idx); +u32 halrf_get_nctl_reg_ver(struct rf_info *rf); +u32 halrf_get_radio_reg_ver(struct rf_info *rf); +void halrf_config_nctl_reg(struct rf_info *rf); +void halrf_set_gpio(void *rf_void, enum phl_phy_idx phy, u8 band); +bool halrf_check_efem(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_set_regulation_from_driver(void *rf_void, u8 regulation_idx); +void halrf_set_regulation_init(void *rf_void, enum phl_phy_idx phy_idx); +void halrf_tssi_default_txagc(void *rf_void, + enum phl_phy_idx phy_idx, bool enable); +void halrf_tssi_set_avg(void *rf_void, + enum phl_phy_idx phy_idx, bool enable); +void halrf_wifi_event_notify(void *rf_void, + enum phl_msg_evt_id event, enum phl_phy_idx phy_idx); +void halrf_2g_rxant(void *rf_void, enum halrf_ant ant); +s8 halrf_get_ther_protected_threshold(void *rf_void); + +void halrf_tssi_set_efuse_to_de(void *rf_void, + enum phl_phy_idx phy_idx); + +void halrf_tssi_scan_ch(void *rf_void, enum rf_path path); + +bool halrf_mac_set_pwr_reg(void *rf_void, enum phl_phy_idx phy, + u32 addr, u32 mask, u32 val); + +u32 halrf_mac_get_pwr_reg(void *rf_void, enum phl_phy_idx phy, + u32 addr, u32 mask); +s8 halrf_get_ther_protected_threshold(void *rf_void); + +s8 halrf_xtal_tracking_offset(void *rf_void, enum phl_phy_idx phy_idx); + +void halrf_hw_tx(void *rf_void, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw, + bool enable); + +void halrf_set_mp_regulation(void *rf_void, enum phl_phy_idx phy, u8 regulation); +u32 halrf_tssi_get_final(void *rf_void, enum phl_phy_idx phy_idx, u8 path); + +void halrf_tssi_backup_txagc(struct rf_info *rf, enum phl_phy_idx phy, bool enable); +void halrf_reload_pwr_limit_tbl_and_set(struct rf_info *rf, + enum phl_phy_idx phy, enum phl_pwr_table pwr_table); + +u32 halrf_test_event_trigger(void *rf_void, + enum phl_phy_idx phy, enum halrf_event_idx idx, enum halrf_event_func func); + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_export_fun.h b/phl/hal_g6/phy/rf/halrf_export_fun.h new file mode 100644 index 0000000..c29bab4 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_export_fun.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_EXPORT_FUN_H__ +#define __HALRF_EXPORT_FUN_H__ +#if 1 +#include "halrf_ic_hw_info.h" +#include "halrf_hw_cfg_ex.h" +#include "halrf_init_ex.h" +#include "halrf_ex.h" +#include "halrf_dbg_cmd_ex.h" +#ifdef RF_8852A_SUPPORT +#include "halrf_8852a/halrf_8852a_api_ex.h" +#endif +#endif +#endif + diff --git a/phl/hal_g6/phy/rf/halrf_headers.h b/phl/hal_g6/phy/rf/halrf_headers.h new file mode 100644 index 0000000..9b043bf --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_headers.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_HEADERS_H_ +#define _HALRF_HEADERS_H_ +#include "../../hal_headers_le.h" +#include "halrf_struct.h" + +#endif /*_HALRF_HEADERS_H_*/ diff --git a/phl/hal_g6/phy/rf/halrf_hw_cfg.c b/phl/hal_g6/phy/rf/halrf_hw_cfg.c new file mode 100644 index 0000000..78fdc97 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_hw_cfg.c @@ -0,0 +1,230 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halrf_precomp.h" + +bool halrf_init_reg_by_hdr(void *rf_void) +{ + bool result = true; +#if 0 + struct rf_info *rf = (struct rf_info *)rf_void; + +#ifdef RF_8852A_SUPPORT + if (rf->ic_type == RF_RTL8852A) { + halrf_config_8852a_radio_a_reg(rf, is_form_folder, + folder_len, folder_array); + halrf_config_8852a_radio_b_reg(rf, is_form_folder, + folder_len, folder_array); + } +#endif +#endif + return result; +} + +bool halrf_nctl_init_reg_by_hdr(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + + bool result = true; +#ifdef RF_8852A_SUPPORT + if (rf->ic_type == RF_RTL8852A) { + halrf_config_8852a_nctl_reg(rf); + } +#endif +#ifdef RF_8852B_SUPPORT + if (rf->ic_type == RF_RTL8852B) { + halrf_config_8852b_nctl_reg(rf); + } +#endif + + return result; +} + +bool halrf_config_radio_a_reg(void *rf_void, bool is_form_folder, + u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_radio_a_reg(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_radio_a_reg(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_radio_b_reg(void *rf_void, bool is_form_folder, + u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_radio_b_reg(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_radio_b_reg(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_store_power_by_rate(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_store_power_by_rate(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_store_power_by_rate(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_store_power_limit(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_store_power_limit(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_store_power_limit(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_store_power_limit_ru(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_store_power_limit_ru(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_store_power_limit_ru(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_store_power_track(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_store_pwr_track(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_store_pwr_track(rf, is_form_folder, + folder_len, folder_array); + } +#endif + + return result; +} + +bool halrf_config_store_xtal_track(void *rf_void, + bool is_form_folder, u32 folder_len, u32 *folder_array) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_config_8852a_store_xtal_track(rf, is_form_folder, + folder_len, folder_array); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_config_8852b_store_xtal_track(rf, is_form_folder, + folder_len, folder_array); + } +#endif + return result; +} + diff --git a/phl/hal_g6/phy/rf/halrf_hw_cfg.h b/phl/hal_g6/phy/rf/halrf_hw_cfg.h new file mode 100644 index 0000000..f5a2ba4 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_hw_cfg.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_HW_CFG_H__ +#define __HALRF_HW_CFG_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ + +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_hw_cfg_ex.h b/phl/hal_g6/phy/rf/halrf_hw_cfg_ex.h new file mode 100644 index 0000000..f4b3fa3 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_hw_cfg_ex.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_HW_CFG_EX_H_ +#define _HALRF_HW_CFG_EX_H_ + +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct rf_info; +bool halrf_init_reg_by_hdr(void *rf_void); +bool halrf_nctl_init_reg_by_hdr(void *rf_void); +#endif diff --git a/phl/hal_g6/phy/rf/halrf_hwimg.h b/phl/hal_g6/phy/rf/halrf_hwimg.h new file mode 100644 index 0000000..1c454d4 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_hwimg.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef _HALRF_HWIMG_H_ +#define _HALRF_HWIMG_H_ + +#define RADIO_TO_FW_PAGE_SIZE 6 +#define RADIO_TO_FW_DATA_SIZE 500 + +struct halrf_radio_info { + u32 write_times_a; + u32 write_times_b; + u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE]; + u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE]; +}; + +#endif /* _HALRF_HW_IMG_8852A_H_ */ diff --git a/phl/hal_g6/phy/rf/halrf_ic_hw_info.h b/phl/hal_g6/phy/rf/halrf_ic_hw_info.h new file mode 100644 index 0000000..371bc8e --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_ic_hw_info.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_IC_HW_INFO_H__ +#define __HALRF_IC_HW_INFO_H__ + +enum halrf_ic { + RF_RTL8852A = BIT(0), + RF_RTL8852B = BIT(1), + RF_RTL8834A = BIT(2), + RF_RTL8852C = BIT(3), +}; + +#define RF_N_1SS 0 +#define RF_N_2SS 0 +#define RF_N_3SS 0 +#define RF_N_4SS 0 + +#define RF_AC_1SS 0 +#define RF_AC_2SS 0 +#define RF_AC_3SS 0 +#define RF_AC_4SS 0 + +#define RF_AX_1SS 0 +#define RF_AX_2SS (RF_RTL8852A | RF_RTL8852B | RF_RTL8852C) +#define RF_AX_3SS 0 +#define RF_AX_4SS (RTL8834A) + +/*@====the following macro DO NOT need to update when adding a new IC======= */ +#define RF_1SS (RF_N_1SS | RF_AC_1SS | RF_AX_1SS) +#define RF_2SS (RF_N_2SS | RF_AC_2SS | RF_AX_2SS) +#define RF_3SS (RF_N_3SS | RF_AC_3SS | RF_AX_3SS) +#define RF_4SS (RF_N_4SS | RF_AC_4SS | RF_AX_4SS) + + +#define RF_N_SERIES (RF_N_1SS | RF_N_2SS | RF_N_3SS |\ + RF_N_4SS) +#define RF_AC_SERIES (RF_AC_1SS | RF_AC_2SS |\ + RF_AC_3SS | RF_AC_4SS) +#define RF_AX_SERIES (RF_AX_1SS | RF_AX_2SS |\ + RF_AX_3SS | RF_AX_4SS) +/*@==========================================================================*/ + +/*@==========================================================================*/ + +/*@==========================================================================*/ + + + +/*@==========================================================================*/ + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum rf_path_bit { + RF_A = BIT(0), + RF_B = BIT(1), + RF_C = BIT(2), + RF_D = BIT(3), + + RF_AB = (RF_A | RF_B), + RF_AC = (RF_A | RF_C), + RF_AD = (RF_A | RF_D), + RF_BC = (RF_B | RF_C), + RF_BD = (RF_B | RF_D), + RF_CD = (RF_C | RF_D), + + RF_ABC = (RF_A | RF_B | RF_C), + RF_ABD = (RF_A | RF_B | RF_D), + RF_ACD = (RF_A | RF_C | RF_D), + RF_BCD = (RF_B | RF_C | RF_D), + + RF_ABCD = (RF_A | RF_B | RF_C | RF_D), +}; + +enum halrf_ant { + RF_MAIN_ANT = 1, + RF_AUX_ANT = 2, +}; + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_ic_sw_info.h b/phl/hal_g6/phy/rf/halrf_ic_sw_info.h new file mode 100644 index 0000000..6a1dbdf --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_ic_sw_info.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_IC_SW_INFO_H__ +#define __HALRF_IC_SW_INFO_H__ + +#define HLARF_CODE_BASE "HALRF_TRUNK" +#define HALRF_RELEASE_DATE "20200106.0" + + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum halrf_api_host { + RUN_IN_FW = 0, + RUN_IN_DRIVER = 1 +}; +#endif diff --git a/phl/hal_g6/phy/rf/halrf_init.c b/phl/hal_g6/phy/rf/halrf_init.c new file mode 100644 index 0000000..82c48a1 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_init.c @@ -0,0 +1,379 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halrf_precomp.h" + +void halrf_cmn_info_self_init(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + if (hal_i->chip_id == CHIP_WIFI6_8852A) + rf->ic_type = RF_RTL8852A; + else if (hal_i->chip_id == CHIP_WIFI6_8834A) + rf->ic_type = RF_RTL8834A; + else if (hal_i->chip_id == CHIP_WIFI6_8852B) + rf->ic_type = RF_RTL8852B; + else if (hal_i->chip_id == CHIP_WIFI6_8852C) + rf->ic_type = RF_RTL8852C; + + if (rf->ic_type & RF_AX_1SS) + rf->num_rf_path = 1; + else if (rf->ic_type & RF_AX_2SS) + rf->num_rf_path = 2; + else if (rf->ic_type & RF_AX_3SS) + rf->num_rf_path = 3; + else if (rf->ic_type & RF_AX_4SS) + rf->num_rf_path = 4; + else + rf->num_rf_path = 1; + + rf->manual_support_ability = 0xffffffff; + rf->rf_init_ready = false; + rf->rf_sys_up_time = 0; + rf->rf_watchdog_en = true; + rf->rf_ic_api_en = true; + /*[Drv Dbg Info]*/ + rf->dbg_component = 0; + rf->cmn_dbg_msg_period = 2; + rf->cmn_dbg_msg_cnt = 0; + + /*@=== [HALRF Structure] ============================================*/ + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + rf->rfk_iqk_info = &rf_iqk_hwspec_8852a; + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + rf->rfk_iqk_info = &rf_iqk_hwspec_8852b; + break; +#endif + default: + break; + } +} + +void halrf_rfk_self_init(struct rf_info *rf) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + struct halrf_gapk_info *txgapk_info = &rf->gapk; + + u8 path; + + RF_DBG(rf, DBG_RF_RFK, "===> %s\n", __func__); + + /* [TXGAPK init] */ + txgapk_info->is_gapk_init = false; + + /*[IQK init]*/ + iqk_info->is_iqk_init = false; + + /*[DPK init]*/ + halrf_dpk_init(rf); + + /*[RXBB BW]*/ + for (path = 0; path < KPATH; path++) + rf->pre_rxbb_bw[path] = 0xff; +} + +void halrf_rfability_init_mp(struct rf_info *rf) +{ + //u64 support_ability = 0; + + switch (rf->ic_type) { +#ifdef RF_8852A_SUPPORT + case RF_RTL8852A: + rf->support_ability |= + /*HAL_RF_TX_PWR_TRACK |*/ + HAL_RF_TSSI_TRK | + HAL_RF_IQK | + /*HAL_RF_LCK |*/ + HAL_RF_DPK | + HAL_RF_DACK | + HAL_RF_TXGAPK | + HAL_RF_DPK_TRACK | + HAL_RF_RXDCK | + HAL_RF_RXGAINK | + HAL_RF_THER_TRIM | + HAL_RF_PABIAS_TRIM | + HAL_RF_TSSI_TRIM | + /*HAL_RF_XTAL_TRACK |*/ + 0; + break; +#endif +#ifdef RF_8852B_SUPPORT + case RF_RTL8852B: + rf->support_ability |= + /*HAL_RF_TX_PWR_TRACK |*/ + HAL_RF_IQK | + /*HAL_RF_LCK |*/ + HAL_RF_DPK | + HAL_RF_DACK | + HAL_RF_TXGAPK | + HAL_RF_DPK_TRACK | + HAL_RF_RXDCK | + /*HAL_RF_RXGAINK |*/ + HAL_RF_THER_TRIM | + HAL_RF_PABIAS_TRIM | + HAL_RF_TSSI_TRIM | + /*HAL_RF_XTAL_TRACK |*/ + HAL_RF_TX_SHAPE | + 0; + break; +#endif +#ifdef RF_8852C_SUPPORT + case RF_RTL8852C: + rf->support_ability = + /*HAL_RF_TX_PWR_TRACK |*/ + /*HAL_RF_IQK |*/ + /*HAL_RF_LCK |*/ + /*HAL_RF_DPK |*/ + /*HAL_RF_DACK |*/ + /*HAL_RF_TXGAPK |*/ + /*HAL_RF_DPK_TRACK |*/ + 0; + break; +#endif + default: + rf->support_ability = + /*HAL_RF_TX_PWR_TRACK |*/ + /*HAL_RF_IQK |*/ + /*HAL_RF_LCK |*/ + /*HAL_RF_DPK |*/ + /*HAL_RF_DACK |*/ + /*HAL_RF_TXGAPK |*/ + /*HAL_RF_DPK_TRACK |*/ + 0; + break; + } +} + +void halrf_rfability_init(struct rf_info *rf) +{ + + switch (rf->ic_type) { +#ifdef RF_8852A_SUPPORT + case RF_RTL8852A: + rf->support_ability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_TSSI_TRK | + HAL_RF_IQK | + /*HAL_RF_LCK |*/ + HAL_RF_DPK | + HAL_RF_DACK | + HAL_RF_TXGAPK | + HAL_RF_DPK_TRACK | + HAL_RF_RXDCK | + HAL_RF_RXGAINK | + HAL_RF_THER_TRIM | + HAL_RF_PABIAS_TRIM | + HAL_RF_TSSI_TRIM | + HAL_RF_XTAL_TRACK | + 0; + break; +#endif +#ifdef RF_8852B_SUPPORT + case RF_RTL8852B: + rf->support_ability |= + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + /*HAL_RF_LCK |*/ + HAL_RF_DPK | + HAL_RF_DACK | + HAL_RF_TXGAPK | + HAL_RF_DPK_TRACK | + HAL_RF_RXDCK | + /*HAL_RF_RXGAINK |*/ + HAL_RF_THER_TRIM | + HAL_RF_PABIAS_TRIM | + HAL_RF_TSSI_TRIM | + /*HAL_RF_XTAL_TRACK |*/ + HAL_RF_TX_SHAPE | + 0; + break; +#endif +#ifdef RF_8852C_SUPPORT + case RF_RTL8852C: + rf->support_ability |= + /*HAL_RF_TX_PWR_TRACK |*/ + /*HAL_RF_IQK |*/ + /*HAL_RF_LCK |*/ + /*HAL_RF_DPK |*/ + /*HAL_RF_DACK |*/ + /*HAL_RF_TXGAPK |*/ + /*HAL_RF_DPK_TRACK |*/ + 0; + break; +#endif + default: + rf->support_ability = + /*HAL_RF_TX_PWR_TRACK |*/ + /*HAL_RF_IQK |*/ + /*HAL_RF_LCK |*/ + /*HAL_RF_DPK |*/ + /*HAL_RF_DACK |*/ + /*HAL_RF_TXGAPK |*/ + /*HAL_RF_DPK_TRACK |*/ + 0; + break; + } +} + +void halrf_set_rfability(struct rf_info *rf) +{ + if (rf->manual_support_ability && + rf->manual_support_ability != 0xffffffff) + rf->support_ability = rf->manual_support_ability; + else if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) + halrf_rfability_init_mp(rf); + else + halrf_rfability_init(rf); + + PHL_INFO("[PHL]%x\n", rf->dbg_component); + RF_DBG(rf, DBG_RF_INIT, + "IC = ((0x%x)), mp=%d, RF_Supportability Init = ((0x%x))\n", + rf->ic_type, rf->phl_com->drv_mode, rf->support_ability); +} + +void halrf_rfe_init(struct rf_info *rf) +{ + u8 rfe_type = rf->phl_com->dev_cap.rfe_type; + + switch (rf->ic_type) { +#ifdef RF_8852A_SUPPORT + case RF_RTL8852A: + /*2G FEM check*/ + if (rfe_type == 11 || rfe_type == 12 || rfe_type == 17 || + rfe_type == 18 || rfe_type == 51 || rfe_type == 52 || + rfe_type == 53 || rfe_type == 54) { + rf->fem.epa_2g = 1; + rf->fem.elna_2g = 1; + } + /*5G FEM check*/ + if (rfe_type == 9 || rfe_type == 10 || rfe_type == 11 || + rfe_type == 12 || rfe_type == 15 || rfe_type == 16 || + rfe_type == 17 || rfe_type == 18 || rfe_type == 37 || + rfe_type == 38 || rfe_type == 51 || rfe_type == 52 || + rfe_type == 53 || rfe_type == 54) { + rf->fem.epa_5g = 1; + rf->fem.elna_5g = 1; + } + /*6G FEM check*/ + if (rfe_type == 13 || rfe_type == 14 || rfe_type == 15 || + rfe_type == 16 || rfe_type == 17 || rfe_type == 18 || + rfe_type == 37 || rfe_type == 38 || rfe_type == 51 || + rfe_type == 52 || rfe_type == 53 || + rfe_type == 54) { + rf->fem.epa_6g = 1; + rf->fem.elna_6g = 1; + } + break; +#endif + default: + break; + } +} + +void halrf_rfe_type_gpio_setting(struct rf_info *rf) +{ + u32 band = rf->hal_com->band[HW_PHY_0].cur_chandef.band; + + RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__); + + halrf_set_gpio(rf, HW_PHY_0, (u8)band); +} + +enum rtw_hal_status halrf_dm_init(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + if (!rf) { + RF_DBG(rf, DBG_RF_INIT, "[%s] *rf = NULL", __func__); + return RTW_HAL_STATUS_FAILURE; + } + + halrf_cmn_info_self_init(rf); + halrf_dbg_setting_init(rf); + halrf_cmd_parser_init(rf); + halrf_set_rfability(rf); + halrf_rfe_init(rf); + halrf_rfe_type_gpio_setting(rf); + halrf_config_nctl_reg(rf); + halrf_rfk_self_init(rf); + + /*Set Power table ref power*/ + halrf_set_ref_power_to_struct(rf, HW_PHY_0); + + halrf_rck_trigger(rf, HW_PHY_0); + //halrf_gapk_save_tx_gain_8852a(rf); + halrf_dack_trigger(rf, false); + halrf_rx_dck_trigger(rf, HW_PHY_0, true); + + /*RX Gain K Get efuse*/ + /*halrf_get_efuse_rx_gain_k(rf, HW_PHY_0);*/ + + /*Thermal Trim, PA Bias k, TSSI Trim get efuse and set reg*/ + halrf_get_efuse_trim(rf, HW_PHY_0); + + /*TSSI Init*/ + halrf_tssi_get_efuse_ex(rf, HW_PHY_0); + /*halrf_tssi_get_efuse_ex(rf, HW_PHY_1);*/ + + /*Set MAC 0xd220[1]=0 r_txagc_BT_en=0 by Bryant*/ + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) + halrf_wl_tx_power_control(rf, 0xffffffff); + + halrf_fcs_init(rf); + + return hal_status; +} + +enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **rf_out) +{ + //enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct rf_info *rf = NULL; + + rf = hal_mem_alloc(hal_com, sizeof(struct rf_info)); + + if (!rf) + return RTW_HAL_STATUS_RF_INIT_FAILURE; + + *rf_out = rf; +// PHL_INFO("[PHL] %s - halrf(%p), *rf(%p)\n", __func__, halrf, *rf); +// PHL_INFO("[PHL] %s\n", __func__); + + rf->phl_com = phl_com;/*shared memory for all components*/ + rf->hal_com = hal_com;/*shared memory for phl and hal*/ + + + return RTW_HAL_STATUS_SUCCESS; +} + +void halrf_deinit(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void *rf) +{ + //enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + struct rf_info *halrf = (struct rf_info *)rf; + + /*stop FSM of RF or free memory*/ + PHL_INFO("[PHL] %s - halrf(%p)\n", __func__, halrf); + + if(halrf) { + hal_mem_free(hal_com, halrf, sizeof(struct rf_info)); + } +} diff --git a/phl/hal_g6/phy/rf/halrf_init.h b/phl/hal_g6/phy/rf/halrf_init.h new file mode 100644 index 0000000..3c47b6b --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_init.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_INIT_H_ +#define _HALRF_INIT_H_ +#include "../../hal_headers_le.h" + + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + + /*@--------------------------[Prptotype]-------------------------------------*/ +struct rf_info; +void halrf_cmn_info_self_init(struct rf_info *rf); +void halrf_rfability_init_mp(struct rf_info *rf); +void halrf_rfability_init(struct rf_info *rf); +void halrf_set_rfability(struct rf_info *rf); +#endif diff --git a/phl/hal_g6/phy/rf/halrf_init_ex.h b/phl/hal_g6/phy/rf/halrf_init_ex.h new file mode 100644 index 0000000..1eeebe8 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_init_ex.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_INIT_EX_H_ +#define _HALRF_INIT_EX_H_ + + /*@--------------------------[Define] ---------------------------------------*/ + + /*@--------------------------[Enum]------------------------------------------*/ + + /*@--------------------------[Structure]-------------------------------------*/ + + /*@--------------------------[Prptotype]-------------------------------------*/ +#if 0 +struct rf_info; +void halrf_cmn_info_self_init(struct rf_info *rf); +void halrf_rfability_init_mp(struct rf_info *rf); +void halrf_rfability_init(struct rf_info *rf); +void halrf_set_rfability(struct rf_info *rf); + +enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void **rf_out); +void halrf_deinit(struct rtw_phl_com_t *phl_com, + struct rtw_hal_com_t *hal_com, void *rf); +#endif + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_interface.c b/phl/hal_g6/phy/rf/halrf_interface.c new file mode 100644 index 0000000..261251a --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_interface.c @@ -0,0 +1,191 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "halrf_precomp.h" + +u32 halrf_get_sys_time(struct rf_info *rf) +{ + return 0; +} + +u32 halrf_cal_bit_shift(u32 bit_mask) +{ + u32 i; + + for (i = 0; i <= 31; i++) { + if ((bit_mask >> i) & BIT0) + break; + } + return i; +} + +void halrf_wreg(struct rf_info *rf, u32 addr, u32 mask, u32 val) +{ + u32 ori_val, bit_shift; +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + struct rtw_mac_cmd cmd = {0}; + struct halrf_fw_offload *fwofld_info = &rf->fwofld; + u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0); + u32 rtn; +#endif + +// u32 page_temp; +// u32 offset_temp; +// u32 temp = 0; + +// page_temp = addr & 0xff00; +// offset_temp = addr & 0xff; + +// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) { +// if (offset_temp <= 0x9c) +// temp = halrf_r32(rf, offset_temp | 0x4c00); +// } + +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + if (fw_ofld == true && rf->fw_ofld_enable == true) { + RF_DBG(rf, DBG_RF_FW, + "[FW_Ofld] addr=0x%08x mask=0x%08x val=0x%08x\n", + addr, mask, val); + + hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info)); + + cmd.src = RTW_MAC_BB_CMD_OFLD; + cmd.type = RTW_MAC_WRITE_OFLD; + cmd.lc = 0; + cmd.offset = (u16)addr; + cmd.value = val; + cmd.mask = mask; + + fwofld_info->src = RTW_MAC_BB_CMD_OFLD; + fwofld_info->type = RTW_MAC_WRITE_OFLD; + fwofld_info->lc = 1; + fwofld_info->offset = (u16)addr; + fwofld_info->value = val; + fwofld_info->mask = mask; + + rtn = halrf_mac_add_cmd_ofld(rf, &cmd); + if (rtn) { + RF_WARNING("======>%s return fail error code = %d !!!\n", + __func__, rtn); + } + } + else +#endif + { + if (mask != MASKDWORD) { + ori_val = halrf_r32(rf, addr); + bit_shift = halrf_cal_bit_shift(mask); + val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask); + } + halrf_w32(rf, addr, val); + } + +// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) { +// if (offset_temp <= 0x9c) +// halrf_w32(rf, offset_temp | 0x4c00, temp); +// } +} + +u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 mask) +{ + u32 reg_val = 0, ori_val, bit_shift; + + ori_val = halrf_r32(rf, addr); + bit_shift = halrf_cal_bit_shift(mask); + reg_val = (ori_val & mask) >> bit_shift; + + return reg_val; +} + +void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val) +{ +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT + struct rtw_mac_cmd cmd = {0}; + struct halrf_fw_offload *fwofld_info = &rf->fwofld; + u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0); + u32 rtn; + + if (fw_ofld == true && rf->fw_ofld_enable == true) { + RF_DBG(rf, DBG_RF_FW, + "[FW_Ofld] addr=0x%08x mask=0x%08x val=0x%08x path=%d\n", + addr, mask, val, path); + + hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info)); + + cmd.src = RTW_MAC_RF_CMD_OFLD; + cmd.type = RTW_MAC_WRITE_OFLD; + cmd.lc = 0; + cmd.rf_path = path; + cmd.offset = (u16)addr; + cmd.value = val; + cmd.mask = mask; + + fwofld_info->src = RTW_MAC_RF_CMD_OFLD; + fwofld_info->type = RTW_MAC_WRITE_OFLD; + fwofld_info->lc = 1; + fwofld_info->rf_path = path; + fwofld_info->offset = (u16)addr; + fwofld_info->value = val; + fwofld_info->mask = mask; + + rtn = halrf_mac_add_cmd_ofld(rf, &cmd); + if (rtn) { + RF_WARNING("======>%s return fail error code = %d !!!\n", + __func__, rtn); + } + } else +#endif + rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val); +} + + +void halrf_delay_10us(struct rf_info *rf, u32 count) +{ + u32 i; + + for (i = 0; i < count; i++) + halrf_delay_us(rf, 10); +} + +void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid, + u8 classid, u32 cmdtype, u32 *pval) +{ + u32 rt_val = 0; + struct rtw_g6_h2c_hdr hdr = {0}; + struct rtw_hal_com_t *hal_com = NULL; + + hdr.h2c_class = classid; + hdr.h2c_func = cmdid; + hdr.type = cmdtype; + hdr.content_len = cmdlen; + hal_com = rf->hal_com; + RF_DBG(rf, DBG_RF_IQK, "[IQK]======>%s H2C: %x %x %x\n", + __func__, classid, cmdid, cmdlen); + rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval); + if (rt_val != 0) { + RF_WARNING("Error H2C CLASS=%d, ID=%d\n", classid, cmdid); + RF_DBG(rf, DBG_RF_IQK, "Error H2C CLASS=%d, ID=%d\n", classid, cmdid); + } +} + diff --git a/phl/hal_g6/phy/rf/halrf_interface.h b/phl/hal_g6/phy/rf/halrf_interface.h new file mode 100644 index 0000000..c7d44da --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_interface.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_INTERFACE_H__ +#define __HALRF_INTERFACE_H__ + +#ifdef CONFIG_FW_IO_OFLD_SUPPORT +#define HALRF_CONFIG_FW_IO_OFLD_SUPPORT +#endif + +#define CF_PHL_BB_CTRL_RX_CCA + +/*@--------------------------[Define] ---------------------------------------*/ +/*[IO Reg]*/ +#define RF_OFST 0x10000 +#define halrf_btc_ntfy(rf, idx, type, process) rtw_hal_btc_wl_rfk_ntfy((rf)->hal_com, idx, type, process) +#define halrf_r32(rf, addr) hal_read32((rf)->hal_com, (addr | RF_OFST)) +#define halrf_r16(rf, addr) hal_read16((rf)->hal_com, (addr | RF_OFST)) +#define halrf_r8(rf, addr) hal_read8((rf)->hal_com, (addr | RF_OFST)) +#define halrf_w32(rf, addr, val) hal_write32((rf)->hal_com, (addr | RF_OFST), val) +#define halrf_w16(rf, addr, val) hal_write16((rf)->hal_com, (addr | RF_OFST), val) +#define halrf_w8(rf, addr, val) hal_write8((rf)->hal_com, (addr | RF_OFST), val) +#define halrf_rrf(rf, path, addr, mask) rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask) +/*#define halrf_wrf(rf, path, addr, mask, val) rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val)*/ +#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val) +#define halrf_rmac32(rf, addr) hal_read32((rf)->hal_com, addr) + +#define halrf_read_mem(rf, addr, cnt, pmem) hal_read_mem((rf)->hal_com, addr, cnt, pmem) + +/*[TX]*/ +#define halrf_tx_pause(rf, band_idx, tx_pause, rson) rtw_hal_tx_pause((rf)->hal_com, band_idx, tx_pause, rson) +#define halrf_set_pmac_pattern(rf, ppdu_type, case_id, phy_idx) rtw_hal_bb_set_plcp_pattern((rf)->hal_com, ppdu_type, case_id, phy_idx) +#define halrf_set_pmac_plcp_tx(rf, plcp, usr, phy_idx, sts) rtw_hal_bb_set_plcp_tx((rf)->hal_com, plcp, usr, phy_idx, sts) +#define halrf_set_pmac_packet_tx(rf, enable, is_cck, cnt, period, time, phy_idx) rtw_hal_bb_set_pmac_packet_tx((rf)->hal_com, enable, is_cck, cnt, period, time, phy_idx) +#define halrf_set_pmac_power(rf, dbm, phy_idx) rtw_hal_bb_set_power((rf)->hal_com, dbm, phy_idx) +#define halrf_cfg_tx_path(rf, path) rtw_hal_bb_cfg_tx_path((rf)->hal_com, path) +#define halrf_cfg_rx_path(rf, path) rtw_hal_bb_cfg_rx_path((rf)->hal_com, path) +#define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, mode) +#define halrf_query_regulation_info(rf, info) rtw_hal_query_regulation((rf)->phl_com->phl_priv, info) +#define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx) +#define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx) + +/*[Delay]*/ +#define halrf_delay_ms(rf, ms) _os_delay_ms(rf->hal_com->drv_priv, ms) +#define halrf_delay_us(rf, us) _os_delay_us(rf->hal_com->drv_priv, us) + +/*[Memory Access]*/ +#define halrf_mem_alloc(rf, buf_sz) _os_mem_alloc(rf->hal_com->drv_priv, buf_sz) +#define halrf_mem_free(rf, buf, buf_sz) _os_mem_free(rf->hal_com->drv_priv, (void *)buf, buf_sz) +#define halrf_mem_set(rf, buf, value, size) _os_mem_set(rf->hal_com->drv_priv, (void *)buf, value, size) +#define halrf_mem_cpy(rf, dest, src, size) _os_mem_cpy(rf->hal_com->drv_priv, (void *)dest, (void *)src, size) +#define halrf_mem_cmp(rf, dest, src, size) _os_mem_cmp(rf->hal_com->drv_priv, (void *)dest, (void *)src, size) + +/*[Timer]*/ +#define halrf_init_timer(rf, timer, call_back_func, context, sz_id) _os_init_timer(rf->hal_com->drv_priv, timer, call_back_func, context, sz_id) +#define halrf_set_timer(rf, timer, ms_delay) _os_set_timer(rf->hal_com->drv_priv, timer, ms_delay) +#define halrf_cancel_timer(rf, timer) _os_cancel_timer(rf->hal_com->drv_priv, timer) +#define halrf_release_timer(rf, timer) _os_release_timer(rf->hal_com->drv_priv, timer) + +/*efuse*/ +#ifndef RTW_FLASH_98D +#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_efuse_get_info((rf)->hal_com, info_type, (void *)value, size) +#else +#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_flash_get_info((rf)->hal_com, info_type, (void *)value, size) +#endif /*RTW_FLASH_98D*/ +#define halrf_phy_efuse_get_info(rf, addr, size, value) rtw_hal_mac_read_phy_efuse((rf)->hal_com, addr, size, value) + +/*GPIO*/ +#ifndef RF_8852B_SUPPORT +#define halrf_gpio_setting_all(rf, rfe_idx) rtw_hal_bb_gpio_setting_all((rf)->hal_com, rfe_idx) +#define halrf_gpio_setting(rf, gpio_idx, path, inv, src) rtw_hal_bb_gpio_setting((rf)->hal_com, gpio_idx, path, inv, src) +#define halrf_set_gpio_func(rf, func, gpio_cfg) rtw_hal_mac_set_gpio_func((rf)->hal_com, func, gpio_cfg) +#endif + +/*Set power by rate, power limit, power */ +#define halrf_mac_write_pwr_limit_rua_reg(rf, band) rtw_hal_mac_write_pwr_limit_rua_reg((rf)->hal_com, band) +#define halrf_mac_write_pwr_limit_reg(rf, band) rtw_hal_mac_write_pwr_limit_reg((rf)->hal_com, band) +#define halrf_mac_write_pwr_by_rate_reg(rf, band) rtw_hal_mac_write_pwr_by_rate_reg((rf)->hal_com, band) +#define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx) +#define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, phy_idx) +#define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_idx) +#define halrf_mac_write_pwr_limit_en(rf, phy_idx) rtw_hal_mac_write_pwr_limit_en((rf)->hal_com, phy_idx) +#define halrf_bb_set_pow_patten_sharp(rf, channel, is_cck, sharp_id, phy_idx) rtw_hal_bb_set_pow_patten_sharp((rf)->hal_com, channel, is_cck, sharp_id, phy_idx) + +#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT +/*FW offload*/ +#define halrf_mac_add_cmd_ofld(rf, cmd) rtw_hal_mac_add_cmd_ofld((rf)->hal_com, cmd) +#endif + +/*BB related*/ +#define halrf_bb_ctrl_rx_cca(rf, cca_en, phy_idx) rtw_hal_bb_ctrl_rx_cca((rf)->hal_com, cca_en, phy_idx) + +/*@--------------------------[Enum]------------------------------------------*/ + + +/*@--------------------------[Structure]-------------------------------------*/ + +/*@--------------------------[Prptotype]-------------------------------------*/ +struct bb_info; + +u32 halrf_cal_bit_shift(u32 bit_mask); + +u32 halrf_get_sys_time(struct rf_info *rf); + +void halrf_wreg(struct rf_info *rf, u32 addr, u32 bit_mask, u32 val); + +u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 bit_mask); + +void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val); + +void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid, + u8 classid, u32 cmdtype, u32 *pval); +void halrf_delay_10us(struct rf_info *rf, u32 count); +#endif diff --git a/phl/hal_g6/phy/rf/halrf_iqk.c b/phl/hal_g6/phy/rf/halrf_iqk.c new file mode 100644 index 0000000..ca151de --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_iqk.c @@ -0,0 +1,833 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halrf_precomp.h" + +#define OLD_BACKUP_RESTORE_ENABLE (0) + +//#ifdef RF_8852A_SUPPORT +u8 iqk_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx) +{ + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + return iqk_ops->iqk_kpath(rf, phy_idx); +} + +void iqk_restore(struct rf_info *rf, u8 path) +{ + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + iqk_ops->iqk_restore(rf, path); + return; +} + +void iqk_backup_mac_reg(struct rf_info *rf, u32 *backup_mac_reg_val) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_mac_reg_num; i++) { + if (i >= RF_BACKUP_MAC_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s backup size not enough\n", __func__); + break; + } + *(backup_mac_reg_val + i) = + halrf_rreg(rf, iqk_info->backup_mac_reg[i], MASKDWORD); +/* + RF_DBG(rf, DBG_RF_IQK, "[IQK]backup mac reg : %x, value =%x\n", + iqk_info->backup_mac_reg[i], *(backup_mac_reg_val + i)); +*/ + } +} + +void iqk_backup_bb_reg(struct rf_info *rf, u32 *backup_bb_reg_val) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_bb_reg_num; i++) { + if (i >= RF_BACKUP_BB_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s backup size not enough\n", __func__); + break; + } + *(backup_bb_reg_val + i) = + halrf_rreg(rf, iqk_info->backup_bb_reg[i], MASKDWORD); +/* + RF_DBG(rf, DBG_RF_IQK, "[IQK]backup bb reg : %x, value =%x\n", + iqk_info->backup_bb_reg[i], *(backup_bb_reg_val + i)); +*/ + } +} + +void iqk_backup_rf_reg(struct rf_info *rf, u32 *backup_rf_reg_val, u8 rf_path) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_rf_reg_num; i++) { + if (i >= RF_BACKUP_RF_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s backup size not enough\n", __func__); + break; + } + *(backup_rf_reg_val + i) = halrf_rrf( + rf, rf_path, iqk_info->backup_rf_reg[i], MASKRF); +/* + RF_DBG(rf, DBG_RF_IQK, + "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path, + iqk_info->backup_rf_reg[i], *(backup_rf_reg_val + i)); +*/ + } +} + +void iqk_restore_mac_reg(struct rf_info *rf, u32 *backup_mac_reg_val) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_mac_reg_num; i++) { + if (i >= RF_BACKUP_MAC_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s restore size not enough\n", __func__); + break; + } + halrf_wreg(rf, iqk_info->backup_mac_reg[i], MASKDWORD, + *(backup_mac_reg_val + i)); +/* + RF_DBG(rf, DBG_RF_IQK, + "[IQK]restore mac reg : %x, value =%x\n", + iqk_info->backup_mac_reg[i], *(backup_mac_reg_val + i)); +*/ + } +} + +void iqk_restore_bb_reg(struct rf_info *rf, u32 *backup_bb_reg_val) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_bb_reg_num; i++) { + if (i >= RF_BACKUP_BB_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s restore size not enough\n", __func__); + break; + } + halrf_wreg(rf, iqk_info->backup_bb_reg[i], MASKDWORD, + *(backup_bb_reg_val + i)); +/* + RF_DBG(rf, DBG_RF_IQK, "[IQK]restore bb reg : %x, value =%x\n", + iqk_info->backup_bb_reg[i], *(backup_bb_reg_val + i)); +*/ + } +} + +void iqk_restore_rf_reg(struct rf_info *rf, u32 *backup_rf_reg_val, u8 rf_path) +{ + struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info; + u32 i; + for (i = 0; i < iqk_info->backup_rf_reg_num; i++) { + if (i >= RF_BACKUP_RF_REG_MAX_NUM) { + RF_DBG(rf, DBG_RF_IQK, + "[IQK] %s restore size not enough\n", __func__); + break; + } + halrf_wrf(rf, rf_path, iqk_info->backup_rf_reg[i], MASKRF, + *(backup_rf_reg_val + i)); +/* + RF_DBG(rf, DBG_RF_IQK, + "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path, + iqk_info->backup_rf_reg[i], *(backup_rf_reg_val + i)); +*/ + } +} +void iqk_macbb_setting(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ +#if 1 + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__); + iqk_ops->iqk_macbb_setting(rf, phy_idx, path); + +#else + iqk_macbb_setting_8852a(rf, path, dbcc_en); +#endif + return; +} + +void iqk_preset(struct rf_info *rf, u8 path) +{ +#if 1 + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + iqk_ops->iqk_preset(rf, path); + +#endif + return; +} + +void iqk_afebb_restore(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ +#if 1 + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + //RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__); + iqk_ops->iqk_afebb_restore(rf, phy_idx, path); +#else + + iqk_afebb_restore_8852a(rf, path); +#endif + return; +} + +void iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ +#if 1 + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + iqk_ops->iqk_get_ch_info(rf, phy_idx, path); +#else + + iqk_get_ch_info_8852a(rf, phy_idx, path); +#endif + return; +} + +bool iqk_mcc_page_sel(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + return iqk_ops->iqk_mcc_page_sel(rf, phy_idx, path);; +} + +void iqk_start_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ +#if 1 + struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops; + + iqk_ops->iqk_start_iqk(rf, phy_idx, path); +#else + + iqk_start_iqk_8852a(rf, phy_idx, path); +#endif + return; +} + +void halrf_iqk_init(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + iqk_init_8852ab(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + iqk_init_8852b(rf); + break; +#endif + default: + break; + } +return; +} + +void halrf_doiqk(struct rf_info *rf, bool force, enum phl_phy_idx phy_idx, + u8 path) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + + u32 backup_mac_val[RF_BACKUP_MAC_REG_MAX_NUM] = {0x0}; + u32 backup_bb_val[RF_BACKUP_BB_REG_MAX_NUM] = {0x0}; + u32 backup_rf_val[RF_PATH_MAX_NUM][RF_BACKUP_RF_REG_MAX_NUM] = {{0x0}}; + u8 rf_path = 0x0; + +#if 0 + if(!force) { + if (!phl_is_mp_mode(rf->phl_com)) { + if(iqk_mcc_page_sel(rf, phy_idx, path)) { + RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK reload!!!!==========\n"); + return; + } + } + } +#endif + + //halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START); + //iqk_info->version = iqk_version; + RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK strat!!!!!==========\n"); + //RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", iqk_info->version); + iqk_get_ch_info(rf, phy_idx, path); + iqk_backup_mac_reg(rf, &backup_mac_val[0]); + iqk_backup_bb_reg(rf, &backup_bb_val[0]); + iqk_backup_rf_reg(rf, &backup_rf_val[path][0], path); + iqk_macbb_setting(rf, phy_idx, path); + iqk_preset(rf, path); + iqk_start_iqk(rf, phy_idx, path); + iqk_restore(rf, path); + iqk_afebb_restore(rf, phy_idx, path); + iqk_restore_mac_reg(rf, &backup_mac_val[0]); + iqk_restore_bb_reg(rf, &backup_bb_val[0]); + iqk_restore_rf_reg(rf, &backup_rf_val[path][0], path); + iqk_info->iqk_times++; + //halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP); + return; +} + +void halrf_drv_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) { + + /*drv_iqk*/ + RF_DBG(rf, DBG_RF_IQK, "[IQK]==== DRV IQK ==== \n"); + switch (iqk_kpath(rf, phy_idx)) { + case RF_A: + halrf_doiqk(rf, force, phy_idx, RF_PATH_A); + break; + case RF_B: + halrf_doiqk(rf, force, phy_idx, RF_PATH_B); + break; + case RF_AB: + halrf_doiqk(rf, force, phy_idx, RF_PATH_A); + halrf_doiqk(rf, force, phy_idx, RF_PATH_B); + break; + default: + break; + } + +} + +bool halrf_check_fwiqk_done(struct rf_info *rf) +{ + + struct rtw_hal_com_t *hal_i = rf->hal_com; + bool isfail = false; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + isfail = halrf_check_fwiqk_done_8852ab(rf); + break; +#endif + +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + isfail = halrf_check_fwiqk_done_8852b(rf); + break; +#endif + default: + break; + } + return isfail; +} + +void halrf_iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + iqk_get_ch_info_8852ab(rf, phy_idx, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + iqk_get_ch_info_8852b(rf, phy_idx, path); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_set_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + iqk_set_info_8852ab(rf, phy_idx, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + iqk_set_info_8852b(rf, phy_idx, path); + break; +#endif + default: + break; + } + + return; +} + +u8 halrf_get_iqk_times(struct rf_info *rf) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u8 times =0x0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + times = halrf_get_iqk_times_8852ab(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + times = halrf_get_iqk_times_8852b(rf); + break; +#endif + default: + break; + } + return times ; +} + + +bool halrf_fw_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) { + + struct halrf_iqk_info *iqk_info = &rf->iqk; + u32 data_to_fw[2] = {0}; + u16 len = (u16) (sizeof(data_to_fw) / sizeof(u32))*4; + bool isfail = true; + + RF_DBG(rf, DBG_RF_IQK, "[IQK]==== FW IQK START v3 ==== \n"); + data_to_fw[0] = (u32) phy_idx; + data_to_fw[1] = (u32) rf->hal_com->dbcc_en; + halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START); + RF_DBG(rf, DBG_RF_IQK, "[IQK] phy_idx = 0x%x\n", data_to_fw[0]); + RF_DBG(rf, DBG_RF_IQK, "[IQK] dbcc_en = 0x%x\n", data_to_fw[1]); + halrf_iqk_get_ch_info(rf, phy_idx, RF_PATH_A); + halrf_iqk_get_ch_info(rf, phy_idx, RF_PATH_B); + halrf_fill_h2c_cmd(rf, len, FWCMD_H2C_IQK_OFFLOAD, 0xa, H2CB_TYPE_DATA, (u32 *) data_to_fw); + halrf_check_fwiqk_done(rf); + iqk_info->iqk_times = halrf_get_iqk_times(rf); + halrf_iqk_set_info(rf, phy_idx, RF_PATH_A); + halrf_iqk_set_info(rf, phy_idx, RF_PATH_B); + halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP); + + RF_DBG(rf, DBG_RF_IQK, "[IQK]==== FW IQK FINISH ==== \n"); + return isfail; +} + + +void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) +{ + struct halrf_iqk_info *iqk_info = &rf->iqk; + bool isfail = true; + +#if 0 + if ((rf->phl_com->id.id & 0x7)== 0x2) //USB + iqk_info->is_fw_iqk = true; + else + iqk_info->is_fw_iqk = false; +#endif + + if (iqk_info->is_fw_iqk) { + isfail = halrf_fw_iqk(rf, phy_idx, force); + if (isfail) { + iqk_info->is_iqk_init = false; + halrf_iqk_init(rf); + isfail = halrf_fw_iqk(rf, phy_idx, force); + } + } else { + halrf_drv_iqk(rf, phy_idx, force); + } + return; +} + +////////////// debg command ////////////////////////// + +u32 halrf_get_iqk_ver(struct rf_info *rf) +{ + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 tmp = 0x0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + tmp = halrf_get_iqk_ver_8852a(); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + tmp =halrf_get_iqk_ver_8852b(); + break; +#endif + default: + break; + } + return tmp; + +} +void halrf_iqk_toneleakage(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_toneleakage_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_toneleakage_8852b(rf, path); + break; +#endif + default: + break; + } + + return; +} + +void halrf_iqk_tx_bypass(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_tx_bypass_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_tx_bypass_8852b(rf, path); + break; +#endif + default: + break; + } + + return; +} + +void halrf_iqk_rx_bypass(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_rx_bypass_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_rx_bypass_8852b(rf, path); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_lok_bypass(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_lok_bypass_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_lok_bypass_8852b(rf, path); + break; +#endif + default: + break; + } + return; +} + +void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_nbiqk_enable_8852ab(rf, iqk_nbiqk_en); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_nbiqk_enable_8852b(rf, iqk_nbiqk_en); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_xym_enable_8852ab(rf, iqk_xym_en); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_xym_enable_8852b(rf, iqk_xym_en); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_fft_enable_8852ab(rf, iqk_fft_en); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_fft_enable_8852b(rf, iqk_fft_en); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_cfir_enable_8852ab(rf, iqk_cfir_en); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_cfir_enable_8852b(rf, iqk_cfir_en); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_sram_enable_8852ab(rf, iqk_sram_en); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_sram_enable_8852b(rf, iqk_sram_en); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_reload(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_reload_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_reload_8852b(rf, path); + break; +#endif + default: + break; + } + return; +} + +void halrf_iqk_dbcc(void *rf_void, u8 path) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_iqk_dbcc_8852ab(rf, path); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_iqk_dbcc_8852b(rf, path); + break; +#endif + default: + break; + } + return; +} + +u8 halrf_iqk_get_mcc_ch0(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u8 tmp = 0x0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + tmp = halrf_iqk_get_mcc_ch0_8852ab(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + tmp = halrf_iqk_get_mcc_ch0_8852b(rf); + break; +#endif + default: + break; + } + return tmp; + +} + +u8 halrf_iqk_get_mcc_ch1(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u8 tmp = 0x0; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + tmp= halrf_iqk_get_mcc_ch0_8852ab(rf); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + tmp = halrf_iqk_get_mcc_ch0_8852b(rf); + break; +#endif + default: + break; + } + return tmp; + +} +void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + + switch (hal_i->chip_id) { +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + halrf_enable_fw_iqk_8852ab(rf, is_fw_iqk); + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + halrf_enable_fw_iqk_8852b(rf, is_fw_iqk); + break; +#endif + default: + break; + } + + return; +} + +u8 halrf_iqk_get_rxevm(void *rf_void) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u8 rxevm =0x0; + + switch (hal_i->chip_id) { + +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + rxevm = halrf_iqk_get_rxevm_8852b(rf); + break; +#endif + default: + break; + } + return rxevm; +} + +u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct rtw_hal_com_t *hal_i = rf->hal_com; + u32 rximr =0x0; + + switch (hal_i->chip_id) { + +#ifdef RF_8852A_SUPPORT + case CHIP_WIFI6_8852A: + break; +#endif +#ifdef RF_8852B_SUPPORT + case CHIP_WIFI6_8852B: + rximr = halrf_iqk_get_rximr_8852b(rf, path, idx); + break; +#endif + default: + break; + } + return rximr; +} + + +//#endif diff --git a/phl/hal_g6/phy/rf/halrf_iqk.h b/phl/hal_g6/phy/rf/halrf_iqk.h new file mode 100644 index 0000000..2bc01a9 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_iqk.h @@ -0,0 +1,116 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_IQK_H_ +#define _HALRF_IQK_H_ + +/*@--------------------------Define Parameters-------------------------------*/ +#define TXIQK 0 +#define RXIQK 1 +#define RXIQK1 2 +#define RXIQK2 3 +#define NBTXK 4 +#define NBRXK 5 +//#define NUM 2 + +#define ID_TXAGC 0x0 +#define ID_FLoK_coarse 0x1 +#define ID_FLoK_fine 0x2 +#define ID_TXK 0x3 +#define ID_RXAGC 0x4 +#define ID_RXK 0x5 +#define ID_NBTXK 0x6 +#define ID_NBRXK 0x7 +#define ID_FLOK_vbuffer 0x8 + +#define ID_TX_PAD_GainGapK 0xe +#define ID_TX_PA_GainGapK 0xf + +/*@-----------------------End Define Parameters-----------------------*/ + +struct halrf_iqk_info { + bool lok_cor_fail[2][NUM]; /*channel/path */ + bool lok_fin_fail[2][NUM]; /*channel/path */ + bool iqk_tx_fail[2][NUM]; /*channel/path */ + bool iqk_rx_fail[2][NUM]; /*channel/path */ + u32 iqk_cnt; + u32 iqk_fail_cnt; + bool segment_iqk; + bool is_iqk_enable; + bool is_iqk_init; + bool is_reload; + u32 iqk_channel[2]; + u8 iqk_band[NUM]; + u8 iqk_ch[NUM]; + u8 iqk_bw[NUM]; + u8 kcount; + u8 iqk_times; + u8 rxiqk_step; + u8 iqk_step; + u8 version; + u32 lok_idac[2][NUM]; + u32 lok_vbuf[2][NUM]; + u32 iqc_gain; + u32 rftxgain[NUM]; + u32 rfrxgain[NUM]; + u32 nb_txcfir[NUM]; + u32 nb_rxcfir[NUM]; + u32 rximr[NUM]; + u32 syn1to2; + u32 bp_txkresult[2]; + u32 bp_rxkresult[2]; + u32 bp_lokresult[2]; + u32 bp_iqkenable[2]; + u32 reload_cnt; + bool is_wb_txiqk[2]; + bool is_wb_rxiqk[2]; + bool is_nbiqk; + bool iqk_fft_en; + bool iqk_xym_en; + bool iqk_sram_en; + bool iqk_cfir_en; + u8 ther_avg[2][8]; /*path*/ + u8 ther_avg_idx; + u8 thermal[2]; + bool thermal_rek_en; + u8 iqk_mcc_ch[2][NUM]; + u8 iqk_table_idx[NUM]; + bool is_fw_iqk; +}; + +void halrf_iqk_init(struct rf_info *rf); +void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force); +u32 halrf_get_iqk_ver(struct rf_info *rf); +void halrf_iqk_toneleakage(void *rf_void, u8 path); +void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en); +void halrf_iqk_tx_bypass(void *rf_void, u8 path); +void halrf_iqk_rx_bypass(void *rf_void, u8 path); +void halrf_iqk_lok_bypass(void *rf_void, u8 path); +void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en); +void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en); +void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en); +void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en); +void halrf_iqk_reload(void *rf_void, u8 path); +void halrf_iqk_dbcc(void *rf_void, u8 path); +u8 halrf_iqk_get_mcc_ch0(void *rf_void); +u8 halrf_iqk_get_mcc_ch1(void *rf_void); +void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk); +u8 halrf_iqk_get_rxevm(void *rf_void); +u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx); +bool halrf_check_fwiqk_done(struct rf_info *rf); + + + + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_kfree.h b/phl/hal_g6/phy/rf/halrf_kfree.h new file mode 100644 index 0000000..e48a567 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_kfree.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_KFREE_H_ +#define _HALRF_KFREE_H_ + +#define RX_GAIN_K_PATH_MAX 2 +#define RX_GAIN_K_OFFSET_MAX 5 +#define RX_GAIN_K_HIDE_OFFSET_MAX 4 + +enum BITMASK { + LOW_MASK = 0, + HIGH_MASK = 1 +}; + +struct halrf_kfree_info{ + u8 efuse_content[80]; +#if 0 + bool efuse_chenk; + bool hide_efuse_chenk; + s8 rx_gain_offset[RX_GAIN_K_PATH_MAX][RX_GAIN_K_OFFSET_MAX]; + s8 rx_gain_cs[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX]; + s8 rx_gain_cg[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX]; + + s8 rx_lna_err_2g[RX_GAIN_K_PATH_MAX][7]; + s8 rx_lna_err_5g[RX_GAIN_K_PATH_MAX][7]; + + s8 rx_frontend_loss[RX_GAIN_K_PATH_MAX]; + s8 rx_rpl_bias_comp[RX_GAIN_K_PATH_MAX]; + s8 rx_rssi_bias_comp[RX_GAIN_K_PATH_MAX]; +#endif +}; + +#endif /*_HALRF_SET_PWR_TABLE_H_*/ diff --git a/phl/hal_g6/phy/rf/halrf_pmac.c b/phl/hal_g6/phy/rf/halrf_pmac.c new file mode 100644 index 0000000..b3c138b --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_pmac.c @@ -0,0 +1,173 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + +#include "halrf_precomp.h" + +void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path, + u16 txagc_cw, bool en) +{ + u32 cw_addr[2] = {0x7c10, 0x7d10}; + + halrf_wreg(rf, cw_addr[path], 0x000001FF, txagc_cw & 0x1ff); + halrf_wreg(rf, cw_addr[path], BIT(9), en); + + if (en) + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set S%d Pseudo_CW RF:0x%x, BB:%d(x0.125)\n", + path, (txagc_cw & 0x1f8) >> 3, txagc_cw & 0x7); + else + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set S%d Pseudo_CW off!!\n", path); +} + +void halrf_set_plcp_usr_info(struct rf_info *rf, struct rf_plcp_param_t *plcp, + struct rf_pmac_tx_info *tx_info) +{ + plcp->usr[0].mcs = tx_info->mcs; + plcp->usr[0].mpdu_len = 0; /*def*/ + plcp->usr[0].n_mpdu = 0; /*def*/ + plcp->usr[0].fec = 0; + plcp->usr[0].dcm = 0; + plcp->usr[0].aid = 0; + plcp->usr[0].scrambler_seed = 100; /*rand(1~255)*/ + plcp->usr[0].random_init_seed = 100; /*rand(1~255)*/ + plcp->usr[0].apep = tx_info->length; + plcp->usr[0].ru_alloc = 0; + plcp->usr[0].nss = tx_info->nss; + plcp->usr[0].txbf = 0; /*def*/ + plcp->usr[0].pwr_boost_db = 0; + + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set PLCP usr (mcs:%d, length:%d, nss:%d)\n", + tx_info->mcs, tx_info->length, tx_info->nss); +} + +void halrf_set_plcp_para_info(struct rf_info *rf, struct rf_plcp_param_t *plcp, + struct rf_pmac_tx_info *tx_info) +{ + plcp->dbw = tx_info->bw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/ + plcp->source_gen_mode = 3; /*def*/ + plcp->locked_clk = 1; /*def*/ + plcp->dyn_bw = 0; /*def*/ + plcp->ndp_en = 0; /*def*/ + plcp->long_preamble_en = tx_info->long_preamble_en; + plcp->stbc = 0; + plcp->gi = tx_info->gi; + plcp->tb_l_len = 0; + plcp->tb_ru_tot_sts_max = 0; + plcp->vht_txop_not_allowed = 0; + plcp->tb_disam = 0; + plcp->doppler = 0; /*def*/ + plcp->he_ltf_type = 0; + plcp->ht_l_len = 0; /*def*/ + plcp->preamble_puncture = 0; /*def*/ + plcp->he_mcs_sigb = 0; + plcp->he_dcm_sigb = 0; + plcp->he_sigb_compress_en = 1; /*def*/ + plcp->max_tx_time_0p4us = 0; + plcp->ul_flag = 0; /*def*/ + plcp->tb_ldpc_extra = 0; + plcp->bss_color = 0; + plcp->sr = 0; /*def*/ + plcp->beamchange_en = 1; /*def*/ + plcp->he_er_u106ru_en = 0; + plcp->ul_srp1 = 0; /*def*/ + plcp->ul_srp2 = 0; /*def*/ + plcp->ul_srp3 = 0; /*def*/ + plcp->ul_srp4 = 0; /*def*/ + plcp->mode = 0; + plcp->group_id = 0; + plcp->ppdu_type = tx_info->ppdu; + plcp->txop = 127; /*def*/ + plcp->tb_strt_sts = 0; + plcp->tb_pre_fec_padding_factor = 0; + plcp->cbw = 0; + plcp->txsc = 0; + plcp->tb_mumimo_mode_en = 0; + plcp->nominal_t_pe = 2; /*def*/ + plcp->ness = 0; /*def*/ + plcp->n_user = 1; + plcp->tb_rsvd = 0; /*def*/ + + /*halrf_mem_cpy(rf, plcp->usr, rf->usr, 4*sizeof(struct rf_usr_plcp_gen_in));*/ + + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set PLCP para (BW:%d, long_preamble:%d, GI:%d, PPDU:%d)\n", + tx_info->bw, tx_info->long_preamble_en, tx_info->gi ,tx_info->ppdu); +} + +void halrf_set_pmac_plcp_gen(struct rf_info *rf, enum phl_phy_idx phy_idx, + struct rf_pmac_tx_info *tx_info) +{ + struct rf_plcp_param_t plcp = {0}; + u8 sts = 0; + + halrf_set_plcp_usr_info(rf, &plcp, tx_info); + + halrf_set_plcp_para_info(rf, &plcp, tx_info); + + halrf_set_pmac_plcp_tx(rf, (void*)&plcp, (void*)&plcp.usr, phy_idx, &sts); +} + +void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx, + enum rf_path path, struct rf_pmac_tx_info *tx, + u8 enable, bool by_cw) +{ + if (enable) { + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set S%d PMAC Tx (PHY%d)\n", path, phy_idx); + + halrf_set_pmac_plcp_gen(rf, phy_idx, tx); + halrf_cfg_tx_path(rf, path); + halrf_cfg_rx_path(rf, path); + if (by_cw) + halrf_set_pseudo_cw(rf, path, tx->txagc_cw, true); + else + halrf_set_pmac_power(rf, tx->dbm, phy_idx); + } else + RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n"); + + halrf_set_pmac_packet_tx(rf, enable, tx->is_cck, tx->cnt, + tx->period, tx->time, phy_idx); +} + +#if 0 +void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx, + enum rf_path path, enum rf_ppdu_type ppdu_type, u8 case_id, + s16 dbm, u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period) +{ +#if 1 + if (enable) { + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set PMAC Tx (PHY%d, S%d, PPDU:%d, case:%d)\n", + phy_idx, path, ppdu_type, case_id); + RF_DBG(rf, DBG_RF_RFK, + "[RFK] Set PMAC Tx (%ddBm, Cnt:%d, time:%d, period:%d)\n", + dbm, cnt, time, period); + + //halrf_set_pmac_pattern(rf, ppdu_type, case_id, phy_idx); + halrf_set_pmac_plcp_gen(rf, 7, 0, 1, 0, 0, 1, ppdu_type, phy_idx); + halrf_cfg_tx_path(rf, path); + //halrf_set_pmac_power(rf, dbm, phy_idx); + halrf_set_pseudo_cw(rf, path, 0x1d0, true); + } else + RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n"); + + halrf_set_pmac_packet_tx(rf, enable, is_cck, cnt, period, time, phy_idx); +#endif +} +#endif + diff --git a/phl/hal_g6/phy/rf/halrf_pmac.h b/phl/hal_g6/phy/rf/halrf_pmac.h new file mode 100644 index 0000000..3c83522 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_pmac.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_PMAC_H_ +#define _HALRF_PMAC_H_ +/*@--------------------------[Define] ---------------------------------------*/ + +/*@--------------------------[Enum]------------------------------------------*/ +enum rf_ppdu_type { + T_CCK = 0, + T_LEGACY = 1, + T_HT_MF = 2, + T_VHT = 3, + T_HE_SU = 4, + T_HE_ER_SU = 5, + T_HE_MU_OFDMA = 6, + T_HE_TB = 7, +}; + +/*@--------------------------[Structure]-------------------------------------*/ +struct rf_pmac_tx_info { + enum rf_ppdu_type ppdu; + u8 mcs; + u8 bw; + u8 nss; + u8 long_preamble_en; + u8 gi; + u16 case_id; + s16 dbm; + u16 txagc_cw; + u8 is_cck; + u16 cnt; + u16 time; + u16 period; + u16 length; +}; + +struct rf_usr_plcp_gen_in { + u32 mcs : 6; + u32 mpdu_len : 14; + u32 n_mpdu : 9; + u32 fec : 1; + u32 dcm : 1; + u32 rsvd0 : 1; + u32 aid : 12; + u32 scrambler_seed : 8; // rand (1~255) + u32 random_init_seed : 8; // rand (1~255) + u32 rsvd1 : 4; + u32 apep : 22; + u32 ru_alloc : 8; + u32 rsvd2 : 2; + u32 nss : 4; + u32 txbf : 1; + u32 pwr_boost_db : 5; + u32 rsvd3 : 22; +}; + +struct rf_plcp_param_t { + u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 + u32 source_gen_mode : 2; + u32 locked_clk : 1; + u32 dyn_bw : 1; + u32 ndp_en : 1; + u32 long_preamble_en : 1; //bmode + u32 stbc : 1; + u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 + u32 tb_l_len : 12; + u32 tb_ru_tot_sts_max : 3; + u32 vht_txop_not_allowed : 1; + u32 tb_disam : 1; + u32 doppler : 2; + u32 he_ltf_type : 2;//0:1x,1:2x,2:4x + + u32 ht_l_len : 12; + u32 preamble_puncture : 1; + u32 he_mcs_sigb : 3;//0~5 + u32 he_dcm_sigb : 1; + u32 he_sigb_compress_en : 1; + u32 max_tx_time_0p4us : 14; + + + u32 ul_flag : 1; + u32 tb_ldpc_extra : 1; + u32 bss_color : 6; + u32 sr : 4; + u32 beamchange_en : 1; + u32 he_er_u106ru_en : 1; + u32 ul_srp1 : 4; + u32 ul_srp2 : 4; + u32 ul_srp3 : 4; + u32 ul_srp4 : 4; + u32 mode : 2; + + u32 group_id : 6; + u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB + u32 txop : 7; + u32 tb_strt_sts : 3; + u32 tb_pre_fec_padding_factor : 2; + u32 cbw : 2; + u32 txsc : 4; + u32 tb_mumimo_mode_en : 1; + u32 rsvd1 : 3; + + u8 nominal_t_pe : 2; // def = 2 + u8 ness : 2; // def = 0 + u8 rsvd2 : 4; + + u8 n_user; + u16 tb_rsvd : 9;//def = 0 + u16 rsvd3 : 7; + + struct rf_usr_plcp_gen_in usr[4]; +}; + +/*@--------------------------[Prptotype]-------------------------------------*/ +void halrf_set_pmac_cw(struct rf_info *rf, enum rf_path path, u16 txagc_cw, bool en); + +void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx, + enum rf_path path, struct rf_pmac_tx_info *tx, + u8 enable, bool by_cw); + +void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path, + u16 txagc_cw, bool en); + +#if 0 +void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx, + enum rf_path path, u8 ppdu_type, u8 case_id, s16 dbm, + u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period); +#endif + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_precomp.h b/phl/hal_g6/phy/rf/halrf_precomp.h new file mode 100644 index 0000000..a3f1200 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_precomp.h @@ -0,0 +1,150 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_PRECOMP_H__ +#define __HALRF_PRECOMP_H__ + +/*@--------------------------[Define] ---------------------------------------*/ + +#ifdef CONFIG_RTL8852A + #define RF_8852A_SUPPORT +#endif + +#ifdef CONFIG_RTL8852B + #define RF_8852B_SUPPORT +#endif + +#ifdef CONFIG_RTL8852C + #define RF_8852C_SUPPORT +#endif + +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define MASKRF 0xfffff +#define MASKRFMODE 0xf0000 +#define MASKRFRXBB 0x003e0 +#define MASKTXPWR 0x0003f +#define INVALID_RF_DATA 0xffffffff + + +/*---[Define Only] ----------------------------------------------------------*/ +#include "../../hal_headers_le.h" +#include "halrf_ic_hw_info.h" +#include "halrf_ic_sw_info.h" + +/*---[Include structure & prototype] ----------------------------------------*/ + +#include "halrf_hw_cfg.h" +#include "halrf_hw_cfg_ex.h" +#include "halrf_interface.h" +#include "halrf_dbg_cmd.h" +#include "halrf_dbg.h" +#include "halrf_txgapk.h" +#include "halrf_pwr_track.h" +#include "halrf_iqk.h" +#include "halrf_dpk.h" +#include "halrf_dack.h" +#include "halrf_pmac.h" +//#include "halrf_dbg_cmd.h" +#include "halrf_dbg_cmd_ex.h" +#include "halrf_init.h" +#include "halrf_init_ex.h" +#include "halrf_pwr_table.h" +#include "halrf_api.h" +#include "halrf_psd.h" +#include "halrf_kfree.h" +#include "halrf_hwimg.h" +#ifdef RF_8852A_SUPPORT +#include "halrf_8852a/halrf_dack_8852a.h" +#include "halrf_8852a/halrf_hwimg_8852a.h" +#include "halrf_8852a/halrf_kfree_8852a.h" +#endif + +#ifdef RF_8852B_SUPPORT +#include "halrf_8852b/halrf_dack_8852b.h" +#include "halrf_8852b/halrf_hwimg_8852b.h" +#include "halrf_8852b/halrf_kfree_8852b.h" +#endif + +#ifdef RF_8852C_SUPPORT +//#include "halrf_8852c/halrf_dack_8852c.h" +//#include "halrf_8852c/halrf_hwimg_8852c.h" +//#include "halrf_8852c/halrf_kfree_8852c.h" +#endif + +#include "halrf.h" +#include "halrf_ex.h" + +#ifdef RF_8852A_SUPPORT + #include "halrf_8852a/halrf_efuse_8852a.h" + #include "halrf_8852a/halrf_reg_cfg_8852a.h" + #include "halrf_8852a/halrf_8852a.h" + #include "halrf_8852a/halrf_8852a_api.h" + #include "halrf_8852a/halrf_8852a_api_ex.h" + #include "halrf_8852a/halrf_iqk_8852a.h" + #include "halrf_8852a/halrf_dpk_8852a.h" + #include "halrf_8852a/halrf_txgapk_8852a.h" + #include "halrf_8852a/halrf_version_rtl8852a.h" + #include "halrf_8852a/halrf_set_pwr_table_8852a.h" + #include "halrf_8852a/halrf_tssi_8852a.h" + #include "halrf_8852a/halrf_psd_8852a.h" +#endif + +#ifdef RF_8852B_SUPPORT + #include "halrf_8852b/halrf_efuse_8852b.h" + #include "halrf_8852b/halrf_reg_cfg_8852b.h" + #include "halrf_8852b/halrf_8852b.h" + #include "halrf_8852b/halrf_8852b_api.h" + #include "halrf_8852b/halrf_8852b_api_ex.h" + #include "halrf_8852b/halrf_iqk_8852b.h" + #include "halrf_8852b/halrf_dpk_8852b.h" + #include "halrf_8852b/halrf_txgapk_8852b.h" + #include "halrf_8852b/halrf_version_rtl8852b.h" + #include "halrf_8852b/halrf_set_pwr_table_8852b.h" + #include "halrf_8852b/halrf_tssi_8852b.h" + #include "halrf_8852b/halrf_psd_8852b.h" +#endif + +#ifdef RF_8852C_SUPPORT +// #include "halrf_8852c/halrf_efuse_8852c.h" +// #include "halrf_8852c/halrf_reg_cfg_8852c.h" + #include "halrf_8852c/halrf_8852c.h" +// #include "halrf_8852c/halrf_8852c_api.h" +// #include "halrf_8852c/halrf_8852c_api_ex.h" +// #include "halrf_8852c/halrf_iqk_8852c.h" +// #include "halrf_8852c/halrf_dpk_8852c.h" +// #include "halrf_8852c/halrf_txgapk_8852c.h" +// #include "halrf_8852c/halrf_version_rtl8852c.h" +// #include "halrf_8852c/halrf_set_pwr_table_8852c.h" +// #include "halrf_8852c/halrf_tssi_8852c.h" +#endif + + + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_psd.h b/phl/hal_g6/phy/rf/halrf_psd.h new file mode 100644 index 0000000..d534767 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_psd.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_PSD_H_ +#define _HALRF_PSD_H_ + +/*@--------------------------Define Parameters-------------------------------*/ + + +/*@-----------------------End Define Parameters-----------------------*/ +struct halrf_psd_data { + u8 path; + u8 iq_path; + u32 avg; + u32 fft; + u32 point; + u32 start_point; + u32 stop_point; + u32 average; + u32 buf_size; + u32 psd_data[450]; + u32 psd_progress; + bool psd_result_running; + u32 psd_reg_backup[256]; +}; + + +#endif /*_HALRF_PSD_H_*/ diff --git a/phl/hal_g6/phy/rf/halrf_pwr_table.c b/phl/hal_g6/phy/rf/halrf_pwr_table.c new file mode 100644 index 0000000..c943ec9 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_pwr_table.c @@ -0,0 +1,1311 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "halrf_precomp.h" + +const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM] = { + /* elements not listed here will get NULL */ + [PW_LMT_REGU_WW13] = "WW", + [PW_LMT_REGU_ETSI] = "ETSI", + [PW_LMT_REGU_FCC] = "FCC", + [PW_LMT_REGU_MKK] = "MKK", + [PW_LMT_REGU_NA] = "NONE", + [PW_LMT_REGU_IC] = "IC", + [PW_LMT_REGU_KCC] = "KCC", + [PW_LMT_REGU_ACMA] = "ACMA", + [PW_LMT_REGU_NCC] = "NCC", + [PW_LMT_REGU_MEXICO] = "MEXICO", + [PW_LMT_REGU_CHILE] = "CHILE", + [PW_LMT_REGU_UKRAINE] = "UKRAINE", + [PW_LMT_REGU_CN] = "CN", + [PW_LMT_REGU_QATAR] = "QATAR", + [PW_LMT_REGU_EXT_PWR] = "EXT", + [PW_LMT_REGU_NULL] = NULL, +}; + +int halrf_get_predefined_pw_lmt_regu_type_from_str(const char *str) +{ + int i; + + for (i = 0; i < PW_LMT_MAX_REGULATION_NUM; i++) + if (_pw_lmt_regu_type_str[i] && _os_strcmp(_pw_lmt_regu_type_str[i], str) == 0) + return i; + return -1; +} + +const char * const *halrf_get_predefined_pw_lmt_regu_type_str_array(u8 *num) +{ + if (num) + *num = PW_LMT_REGU_PREDEF_NUM; + return _pw_lmt_regu_type_str; +} + +const enum halrf_pw_lmt_regulation_type _regulation_to_pw_lmt_regu_type[REGULATION_MAX] = { + /* elements not listed here will get PW_LMT_REGU_WW13(0) */ + [REGULATION_WW] = PW_LMT_REGU_WW13, + [REGULATION_ETSI] = PW_LMT_REGU_ETSI, + [REGULATION_FCC] = PW_LMT_REGU_FCC, + [REGULATION_MKK] = PW_LMT_REGU_MKK, + [REGULATION_KCC] = PW_LMT_REGU_KCC, + [REGULATION_NCC] = PW_LMT_REGU_NCC, + [REGULATION_ACMA] = PW_LMT_REGU_ACMA, + [REGULATION_NA] = PW_LMT_REGU_NA, + [REGULATION_IC] = PW_LMT_REGU_IC, + [REGULATION_CHILE] = PW_LMT_REGU_CHILE, + [REGULATION_MEX] = PW_LMT_REGU_MEXICO, +}; + +const enum halrf_pw_lmt_regulation_type _tpo_to_pw_lmt_regu_type[TPO_NA] = { + /* elements not listed here will get PW_LMT_REGU_WW13(0) */ + [TPO_CHILE] = PW_LMT_REGU_CHILE, + [TPO_QATAR] = PW_LMT_REGU_QATAR, + [TPO_UKRAINE] = PW_LMT_REGU_UKRAINE, + [TPO_CN] = PW_LMT_REGU_CN, +}; + +u8 halrf_get_regulation_info(struct rf_info *rf, u8 band) +{ + struct rtw_regulation_info rg_info = {0}; + struct halrf_pwr_info *pwr = &rf->pwr_info; + enum halrf_pw_lmt_regulation_type pw_lmt_type = PW_LMT_REGU_NULL; + u8 reg = REGULATION_NA; + u8 extra_regd_idx; + const char *bstr = NULL; + + halrf_query_regulation_info(rf, &rg_info); + + RF_DBG(rf, DBG_RF_INIT, "======>%s band=%d\n", __func__, band); + + RF_DBG(rf, DBG_RF_INIT, "domain_code=%d regulation_2g=%d regulation_5g=%d chplan_ver=%d country_ver=%d rg_info.tpor=%d\n", + rg_info.domain_code, rg_info.regulation_2g, rg_info.regulation_5g, rg_info.chplan_ver, rg_info.country_ver, rg_info.tpo); + + extra_regd_idx = halrf_get_power_limit_extra(rf); + if (extra_regd_idx != 0xff) + return extra_regd_idx; + +#ifdef RTW_FLASH_98D + if (pwr->regulation_idx != 0xff) + return pwr->regulation_idx; +#else + if (band == BAND_ON_24G) { + reg = rg_info.regulation_2g; + bstr = "2g"; + } else if (band == BAND_ON_5G) { + reg = rg_info.regulation_5g; + bstr = "5g"; + } else if (band == BAND_ON_6G) { + /* TODO: 6G regulation */ + bstr = "6g"; + } + + /* TODO: consider _hal_file_regd_ext */ + + if (rg_info.tpo != TPO_NA) { + pw_lmt_type = tpo_to_pw_lmt_regu_type(rg_info.tpo); + RF_DBG(rf, DBG_RF_INIT, "%s extra pw_lmt_regu=%s(%d)\n", + bstr, pw_lmt_regu_type_str(pw_lmt_type), pw_lmt_type); + } else { + if (reg == REGULATION_NA) + return PW_LMT_REGU_NULL; /* return this to distinguish from PW_LMT_REGU_NA done by NONE option from TXPWR_LMT.txt */ + pw_lmt_type = regulation_to_pw_lmt_regu_type(reg); + } + + if (pwr->regulation[band][pw_lmt_type] != true) { + RF_DBG(rf, DBG_RF_INIT, "%s pw_lmt_regu=%s(%d) is not exist return WW13 !!!\n", + bstr, pw_lmt_regu_type_str(pw_lmt_type), pw_lmt_type); + return PW_LMT_REGU_WW13; + } +#endif + + if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) + return regulation_to_pw_lmt_regu_type(pwr->mp_regulation); + + return pw_lmt_type; +} + +const char *halrf_get_pw_lmt_regu_type_str(struct rf_info *rf, u8 band) +{ + u8 reg = halrf_get_regulation_info(rf, band); + + return pw_lmt_regu_type_str(reg); +} + +void halrf_power_by_rate_store_to_array(struct rf_info *rf, + u32 band, u32 tx_num, u32 rate_id, u32 data) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + + RF_DBG(rf, DBG_RF_INIT, "======>%s band=%d tx_num=%d rate_id=%d data=0x%x\n", + __func__, band, tx_num, rate_id, data); + + if (band != (u32)BAND_ON_24G && band != (u32)BAND_ON_5G && band != (u32)BAND_ON_6G) + RF_DBG(rf, DBG_RF_INIT, "Invalid Band %d\n", band); + + if (tx_num > 4 && tx_num != 15) + RF_DBG(rf, DBG_RF_INIT, "Invalid TxNum %d\n", tx_num); + + if (band == 0 && tx_num == 0 && rate_id == 0) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK1] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK2] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK5_5] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK11] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 1) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM6] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM9] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM12] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM18] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 2) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM24] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM36] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM48] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM54] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 3) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS2] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS3] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS2] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS3] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS2] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS3] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 4) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS4] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS5] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS6] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS7] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS4] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS5] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS6] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS7] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS4] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS5] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS6] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS7] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 5) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS8] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS9] = (s8)((data & 0xff00) >> 8); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS8] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS9] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS10] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS11] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 0 && rate_id == 6) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS3] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS4] = (s8)((data & 0xff000000) >> 24); + } else if (band == 0 && tx_num == 15 && rate_id == 7) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_OFFSET] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HT_OFFSET] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM_OFFSET] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK_OFFSET] = (s8)((data & 0xff000000) >> 24); + } else if (band == 0 && tx_num == 15 && rate_id == 8) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_OFFSET] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 1 && rate_id == 3) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS8] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS9] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS10] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS11] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS2] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS3] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS2] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS3] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 1 && rate_id == 4) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS12] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS13] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS14] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS15] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS4] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS5] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS6] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS7] = (s8)((data & 0xff000000) >> 24); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS4] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS5] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS6] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS7] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 1 && rate_id == 5) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS8] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS9] = (s8)((data & 0xff00) >> 8); + + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS8] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS9] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS10] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS11] = (s8)((data & 0xff000000) >> 24); + } else if (tx_num == 1 && rate_id == 6) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS0] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS1] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS3] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS4] = (s8)((data & 0xff000000) >> 24); + } else if (band == 1 && tx_num == 15 && rate_id == 9) { + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_OFFSET] = (s8)(data & 0xff); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_OFFSET] = (s8)((data & 0xff00) >> 8); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HT_OFFSET] = (s8)((data & 0xff0000) >> 16); + pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM_OFFSET] = (s8)((data & 0xff000000) >> 24); + } +} + +u8 halrf_get_ch_idx_to_limit_array(struct rf_info *rf, u8 channel) +{ + u8 channelIndex; + + if (channel >= 1 && channel <= 14) + channelIndex = channel - 1; + else if (channel >= 36 && channel <= 64) + channelIndex = (channel - 36) / 2; + else if (channel >= 100 && channel <= 144) + channelIndex = ((channel - 100) / 2) + 15; + else if (channel >= 149 && channel <= 177) + channelIndex = ((channel - 149) / 2) + 38; + else + channelIndex = 0; + + return channelIndex; +} + +u8 halrf_get_limit_ch_idx_to_ch_idx(struct rf_info *rf, u8 band, u8 channel) +{ + u8 channelIndex; + + if (band == PW_LMT_BAND_2_4G) { + if (channel >= 0 && channel <= 13) + channelIndex = channel + 1; + else + channelIndex = 0; + } else { + if (channel >= 0 && channel <= 14) + channelIndex = channel * 2 + 36; + else if (channel >= 15 && channel <= 37) + channelIndex = (channel - 15) * 2 + 100; + else if (channel >= 38 && channel <= 52) + channelIndex = (channel - 38) * 2 + 149; + else + channelIndex = 0; + } + + return channelIndex; +} + +u16 halrf_hw_rate_to_pwr_by_rate(struct rf_info *rf, u16 rate) +{ + u16 ret_rate = HALRF_DATA_RATE_OFDM6; + + switch(rate) { + case RTW_DATA_RATE_CCK1: ret_rate = HALRF_DATA_RATE_CCK1; break; + case RTW_DATA_RATE_CCK2: ret_rate = HALRF_DATA_RATE_CCK2; break; + case RTW_DATA_RATE_CCK5_5: ret_rate = HALRF_DATA_RATE_CCK5_5; break; + case RTW_DATA_RATE_CCK11: ret_rate = HALRF_DATA_RATE_CCK11; break; + case RTW_DATA_RATE_OFDM6: ret_rate = HALRF_DATA_RATE_OFDM6; break; + case RTW_DATA_RATE_OFDM9: ret_rate = HALRF_DATA_RATE_OFDM9; break; + case RTW_DATA_RATE_OFDM12: ret_rate = HALRF_DATA_RATE_OFDM12; break; + case RTW_DATA_RATE_OFDM18: ret_rate = HALRF_DATA_RATE_OFDM18; break; + case RTW_DATA_RATE_OFDM24: ret_rate = HALRF_DATA_RATE_OFDM24; break; + case RTW_DATA_RATE_OFDM36: ret_rate = HALRF_DATA_RATE_OFDM36; break; + case RTW_DATA_RATE_OFDM48: ret_rate = HALRF_DATA_RATE_OFDM48; break; + case RTW_DATA_RATE_OFDM54: ret_rate = HALRF_DATA_RATE_OFDM54; break; + + case RTW_DATA_RATE_MCS0: ret_rate = HALRF_DATA_RATE_MCS0; break; + case RTW_DATA_RATE_MCS1: ret_rate = HALRF_DATA_RATE_MCS1; break; + case RTW_DATA_RATE_MCS2: ret_rate = HALRF_DATA_RATE_MCS2; break; + case RTW_DATA_RATE_MCS3: ret_rate = HALRF_DATA_RATE_MCS3; break; + case RTW_DATA_RATE_MCS4: ret_rate = HALRF_DATA_RATE_MCS4; break; + case RTW_DATA_RATE_MCS5: ret_rate = HALRF_DATA_RATE_MCS5; break; + case RTW_DATA_RATE_MCS6: ret_rate = HALRF_DATA_RATE_MCS6; break; + case RTW_DATA_RATE_MCS7: ret_rate = HALRF_DATA_RATE_MCS7; break; + case RTW_DATA_RATE_MCS8: ret_rate = HALRF_DATA_RATE_MCS8; break; + case RTW_DATA_RATE_MCS9: ret_rate = HALRF_DATA_RATE_MCS9; break; + case RTW_DATA_RATE_MCS10: ret_rate = HALRF_DATA_RATE_MCS10; break; + case RTW_DATA_RATE_MCS11: ret_rate = HALRF_DATA_RATE_MCS11; break; + case RTW_DATA_RATE_MCS12: ret_rate = HALRF_DATA_RATE_MCS12; break; + case RTW_DATA_RATE_MCS13: ret_rate = HALRF_DATA_RATE_MCS13; break; + case RTW_DATA_RATE_MCS14: ret_rate = HALRF_DATA_RATE_MCS14; break; + case RTW_DATA_RATE_MCS15: ret_rate = HALRF_DATA_RATE_MCS15; break; + case RTW_DATA_RATE_MCS16: ret_rate = HALRF_DATA_RATE_MCS16; break; + case RTW_DATA_RATE_MCS17: ret_rate = HALRF_DATA_RATE_MCS17; break; + case RTW_DATA_RATE_MCS18: ret_rate = HALRF_DATA_RATE_MCS18; break; + case RTW_DATA_RATE_MCS19: ret_rate = HALRF_DATA_RATE_MCS19; break; + case RTW_DATA_RATE_MCS20: ret_rate = HALRF_DATA_RATE_MCS20; break; + case RTW_DATA_RATE_MCS21: ret_rate = HALRF_DATA_RATE_MCS21; break; + case RTW_DATA_RATE_MCS22: ret_rate = HALRF_DATA_RATE_MCS22; break; + case RTW_DATA_RATE_MCS23: ret_rate = HALRF_DATA_RATE_MCS23; break; + case RTW_DATA_RATE_MCS24: ret_rate = HALRF_DATA_RATE_MCS24; break; + case RTW_DATA_RATE_MCS25: ret_rate = HALRF_DATA_RATE_MCS25; break; + case RTW_DATA_RATE_MCS26: ret_rate = HALRF_DATA_RATE_MCS26; break; + case RTW_DATA_RATE_MCS27: ret_rate = HALRF_DATA_RATE_MCS27; break; + case RTW_DATA_RATE_MCS28: ret_rate = HALRF_DATA_RATE_MCS28; break; + case RTW_DATA_RATE_MCS29: ret_rate = HALRF_DATA_RATE_MCS29; break; + case RTW_DATA_RATE_MCS30: ret_rate = HALRF_DATA_RATE_MCS30; break; + case RTW_DATA_RATE_MCS31: ret_rate = HALRF_DATA_RATE_MCS31; break; + + case RTW_DATA_RATE_VHT_NSS1_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS0; break; + case RTW_DATA_RATE_VHT_NSS1_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS1; break; + case RTW_DATA_RATE_VHT_NSS1_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS2; break; + case RTW_DATA_RATE_VHT_NSS1_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS3; break; + case RTW_DATA_RATE_VHT_NSS1_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS4; break; + case RTW_DATA_RATE_VHT_NSS1_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS5; break; + case RTW_DATA_RATE_VHT_NSS1_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS6; break; + case RTW_DATA_RATE_VHT_NSS1_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS7; break; + case RTW_DATA_RATE_VHT_NSS1_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS8; break; + case RTW_DATA_RATE_VHT_NSS1_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS9; break; + case RTW_DATA_RATE_VHT_NSS2_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS0; break; + case RTW_DATA_RATE_VHT_NSS2_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS1; break; + case RTW_DATA_RATE_VHT_NSS2_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS2; break; + case RTW_DATA_RATE_VHT_NSS2_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS3; break; + case RTW_DATA_RATE_VHT_NSS2_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS4; break; + case RTW_DATA_RATE_VHT_NSS2_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS5; break; + case RTW_DATA_RATE_VHT_NSS2_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS6; break; + case RTW_DATA_RATE_VHT_NSS2_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS7; break; + case RTW_DATA_RATE_VHT_NSS2_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS8; break; + case RTW_DATA_RATE_VHT_NSS2_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS9; break; + case RTW_DATA_RATE_VHT_NSS3_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS0; break; + case RTW_DATA_RATE_VHT_NSS3_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS1; break; + case RTW_DATA_RATE_VHT_NSS3_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS2; break; + case RTW_DATA_RATE_VHT_NSS3_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS3; break; + case RTW_DATA_RATE_VHT_NSS3_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS4; break; + case RTW_DATA_RATE_VHT_NSS3_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS5; break; + case RTW_DATA_RATE_VHT_NSS3_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS6; break; + case RTW_DATA_RATE_VHT_NSS3_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS7; break; + case RTW_DATA_RATE_VHT_NSS3_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS8; break; + case RTW_DATA_RATE_VHT_NSS3_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS9; break; + case RTW_DATA_RATE_VHT_NSS4_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS0; break; + case RTW_DATA_RATE_VHT_NSS4_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS1; break; + case RTW_DATA_RATE_VHT_NSS4_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS2; break; + case RTW_DATA_RATE_VHT_NSS4_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS3; break; + case RTW_DATA_RATE_VHT_NSS4_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS4; break; + case RTW_DATA_RATE_VHT_NSS4_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS5; break; + case RTW_DATA_RATE_VHT_NSS4_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS6; break; + case RTW_DATA_RATE_VHT_NSS4_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS7; break; + case RTW_DATA_RATE_VHT_NSS4_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS8; break; + case RTW_DATA_RATE_VHT_NSS4_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS9; break; + + case RTW_DATA_RATE_HE_NSS1_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS0; break; + case RTW_DATA_RATE_HE_NSS1_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS1; break; + case RTW_DATA_RATE_HE_NSS1_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS2; break; + case RTW_DATA_RATE_HE_NSS1_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS3; break; + case RTW_DATA_RATE_HE_NSS1_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS4; break; + case RTW_DATA_RATE_HE_NSS1_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS5; break; + case RTW_DATA_RATE_HE_NSS1_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS6; break; + case RTW_DATA_RATE_HE_NSS1_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS7; break; + case RTW_DATA_RATE_HE_NSS1_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS8; break; + case RTW_DATA_RATE_HE_NSS1_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS9; break; + case RTW_DATA_RATE_HE_NSS1_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS10; break; + case RTW_DATA_RATE_HE_NSS1_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS11; break; + case RTW_DATA_RATE_HE_NSS2_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS0; break; + case RTW_DATA_RATE_HE_NSS2_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS1; break; + case RTW_DATA_RATE_HE_NSS2_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS2; break; + case RTW_DATA_RATE_HE_NSS2_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS3; break; + case RTW_DATA_RATE_HE_NSS2_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS4; break; + case RTW_DATA_RATE_HE_NSS2_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS5; break; + case RTW_DATA_RATE_HE_NSS2_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS6; break; + case RTW_DATA_RATE_HE_NSS2_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS7; break; + case RTW_DATA_RATE_HE_NSS2_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS8; break; + case RTW_DATA_RATE_HE_NSS2_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS9; break; + case RTW_DATA_RATE_HE_NSS2_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS10; break; + case RTW_DATA_RATE_HE_NSS2_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS11; break; + case RTW_DATA_RATE_HE_NSS3_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS0; break; + case RTW_DATA_RATE_HE_NSS3_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS1; break; + case RTW_DATA_RATE_HE_NSS3_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS2; break; + case RTW_DATA_RATE_HE_NSS3_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS3; break; + case RTW_DATA_RATE_HE_NSS3_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS4; break; + case RTW_DATA_RATE_HE_NSS3_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS5; break; + case RTW_DATA_RATE_HE_NSS3_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS6; break; + case RTW_DATA_RATE_HE_NSS3_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS7; break; + case RTW_DATA_RATE_HE_NSS3_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS8; break; + case RTW_DATA_RATE_HE_NSS3_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS9; break; + case RTW_DATA_RATE_HE_NSS3_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS10; break; + case RTW_DATA_RATE_HE_NSS3_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS11; break; + case RTW_DATA_RATE_HE_NSS4_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS0; break; + case RTW_DATA_RATE_HE_NSS4_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS1; break; + case RTW_DATA_RATE_HE_NSS4_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS2; break; + case RTW_DATA_RATE_HE_NSS4_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS3; break; + case RTW_DATA_RATE_HE_NSS4_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS4; break; + case RTW_DATA_RATE_HE_NSS4_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS5; break; + case RTW_DATA_RATE_HE_NSS4_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS6; break; + case RTW_DATA_RATE_HE_NSS4_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS7; break; + case RTW_DATA_RATE_HE_NSS4_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS8; break; + case RTW_DATA_RATE_HE_NSS4_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS9; break; + case RTW_DATA_RATE_HE_NSS4_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS10; break; + case RTW_DATA_RATE_HE_NSS4_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS11; break; + + } + + return ret_rate; +} + +u16 halrf_get_dcm_offset_pwr_by_rate(struct rf_info *rf, u16 rate, + u8 dcm, u8 offset) +{ + u16 rate_tmp = 0; + + if (dcm == 0) + rate_tmp = halrf_hw_rate_to_pwr_by_rate(rf, rate); + else if (dcm == 1) { + if (rate == RTW_DATA_RATE_HE_NSS1_MCS0) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS0; + else if (rate == RTW_DATA_RATE_HE_NSS1_MCS1) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS1; + else if (rate == RTW_DATA_RATE_HE_NSS1_MCS3) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS3; + else if (rate == RTW_DATA_RATE_HE_NSS1_MCS4) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS4; + else if (rate == RTW_DATA_RATE_HE_NSS2_MCS0) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS0; + else if (rate == RTW_DATA_RATE_HE_NSS2_MCS1) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS1; + else if (rate == RTW_DATA_RATE_HE_NSS2_MCS3) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS3; + else if (rate == RTW_DATA_RATE_HE_NSS2_MCS4) + rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS4; + } + + if (offset == 1) { + /*if (dcm == 1)*/ + if (rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rate <= RTW_DATA_RATE_HE_NSS4_MCS11) + rate_tmp = HALRF_DATA_RATE_HEDCM_OFFSET; + if (rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS4_MCS9) + rate_tmp = HALRF_DATA_RATE_VHT_OFFSET; + if (rate >= RTW_DATA_RATE_MCS0 && rate <= RTW_DATA_RATE_MCS31) + rate_tmp = HALRF_DATA_RATE_HT_OFFSET; + if (rate >= RTW_DATA_RATE_OFDM6 && rate <= RTW_DATA_RATE_OFDM54) + rate_tmp = HALRF_DATA_RATE_OFDM_OFFSET; + if (rate >= RTW_DATA_RATE_CCK1 && rate <= RTW_DATA_RATE_CCK11) + rate_tmp = HALRF_DATA_RATE_CCK_OFFSET; + + } + + return rate_tmp; + +} + +u8 halrf_hw_rate_to_limit_rate_tx_num(struct rf_info *rf, u16 rate) +{ + if (rate >= RTW_DATA_RATE_CCK1 && rate <= RTW_DATA_RATE_CCK11) + return PW_LMT_RS_CCK; + else if (rate >= RTW_DATA_RATE_OFDM6 && rate <= RTW_DATA_RATE_OFDM54) + return PW_LMT_RS_OFDM; + else if (rate >= RTW_DATA_RATE_MCS0 && rate <= RTW_DATA_RATE_MCS7) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_MCS8 && rate <= RTW_DATA_RATE_MCS15) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_MCS16 && rate <= RTW_DATA_RATE_MCS23) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_MCS24 && rate <= RTW_DATA_RATE_MCS31) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS1_MCS9) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_VHT_NSS2_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS2_MCS9) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_VHT_NSS3_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS3_MCS9) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_VHT_NSS4_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS4_MCS9) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rate <= RTW_DATA_RATE_HE_NSS1_MCS11) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_HE_NSS2_MCS0 && rate <= RTW_DATA_RATE_HE_NSS2_MCS11) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_HE_NSS3_MCS0 && rate <= RTW_DATA_RATE_HE_NSS3_MCS11) + return PW_LMT_RS_HE; + else if (rate >= RTW_DATA_RATE_HE_NSS4_MCS0 && rate <= RTW_DATA_RATE_HE_NSS4_MCS11) + return PW_LMT_RS_HE; + else + return PW_LMT_RS_HE; + +} + +void halrf_power_limit_store_to_array(struct rf_info *rf, + u8 regulation, u8 band, u8 bandwidth, u8 rate, + u8 tx_num, u8 beamforming, u8 chnl, s8 val) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 ch = halrf_get_ch_idx_to_limit_array(rf, chnl); + + RF_DBG(rf, DBG_RF_INIT, "======>%s regulation=%d band=%d bandwidth=%d rate=%d\n", + __func__, regulation, band, bandwidth, rate); + + RF_DBG(rf, DBG_RF_INIT, "======>%s tx_num=%d beamforming=%d chnl=%d ch=%d val=%d\n", + __func__, tx_num, beamforming, chnl, ch, val); + + if (band == PW_LMT_BAND_2_4G) { + pwr->tx_pwr_limit_2g[regulation][bandwidth][rate][beamforming][ch][tx_num] = val; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n", + val, regulation, bandwidth, rate, beamforming, ch, tx_num); + } else if (band == PW_LMT_BAND_5G) { + pwr->tx_pwr_limit_5g[regulation][bandwidth][rate][beamforming][ch][tx_num] = val; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n", + val, regulation, bandwidth, rate, beamforming, ch, tx_num); + } +} + +void halrf_power_limit_set_worldwide(struct rf_info *rf) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u32 reg, bw, rate, bf, ch, tx_num; + s8 tmp; + + RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) { + for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_MAX_2G_BANDWITH_NUM; bw++) { + tmp = 127; + for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) { + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n", + reg, bw, rate, bf, ch, tx_num ,pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]); + if (tmp > pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] && + pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] > 0) { + tmp = pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]; + } + } + if (tmp == 127) + tmp = 0; + pwr->tx_pwr_limit_2g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num] = tmp; + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_WW13, bw, rate, bf, ch, tx_num ,pwr->tx_pwr_limit_2g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num]); + } + } + } + } + } + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) { + for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_MAX_BANDWIDTH_NUM; bw++) { + tmp = 127; + for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) { + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n", + reg, bw, rate, bf, ch, tx_num, pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]); + if (tmp > pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] && + pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] > 0) { + tmp = pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]; + } + } + if (tmp == 127) + tmp = 0; + pwr->tx_pwr_limit_5g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num] = tmp; + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_WW13, bw, rate, bf, ch, tx_num, pwr->tx_pwr_limit_5g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num]); + } + } + } + } + } + + RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__); + +} + +void halrf_power_limit_ru_store_to_array(struct rf_info *rf, + u8 band, u8 bandwidth, u8 tx_num, u8 rate, + u8 regulation, u8 chnl, s8 val) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 ch = halrf_get_ch_idx_to_limit_array(rf, chnl); + + RF_DBG(rf, DBG_RF_INIT, "======>%s regulation=%d band=%d bandwidth=%d rate=%d\n", + __func__, regulation, band, bandwidth, rate); + + RF_DBG(rf, DBG_RF_INIT, "======>%s tx_num=%d chnl=%d ch=%d val=%d\n", + __func__, tx_num, chnl, ch, val); + + if (band == PW_LMT_BAND_2_4G) { + pwr->tx_pwr_limit_ru_2g[regulation][bandwidth][rate][ch][tx_num] = val; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]\n", + val, regulation, bandwidth, rate, ch, tx_num); + } else if (band == PW_LMT_BAND_5G) { + pwr->tx_pwr_limit_ru_5g[regulation][bandwidth][rate][ch][tx_num] = val; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]\n", + val, regulation, bandwidth, rate, ch, tx_num); + } +} + +void halrf_power_limit_ru_set_worldwide(struct rf_info *rf) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u32 reg, bw, rate, ch, tx_num; + s8 tmp; + + RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) { + tmp = 127; + for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) { + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n", + reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]); + + if (tmp > pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] && + pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] > 0) { + tmp = pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]; + } + } + if (tmp == 127) + tmp = 0; + pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num] = tmp; + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_WW13, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num]); + + } + } + } + } + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) { + tmp = 127; + for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) { + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n", + reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]); + + if (tmp > pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] && + pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] > 0) { + tmp = pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]; + } + } + if (tmp == 127) + tmp = 0; + pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num] = tmp; + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_WW13, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num]); + + } + } + } + } + + RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__); + +} + +void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf, + enum phl_phy_idx phy) +{ +#ifdef SPF_PHL_RF_019_SAR + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_hal_com_t *hal = rf->hal_com; + u32 reg, bw, rate, bf, ch, tx_num; + s8 ext_pwr = 0; + u8 real_ch; + + RF_DBG(rf, DBG_RF_INIT, "======>%s phy=%d\n", __func__, phy); + + reg = (u32)halrf_get_regulation_info(rf, BAND_ON_24G); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_2_4g[tx_num]; + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) { + for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_MAX_2G_BANDWITH_NUM; bw++) { + + RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_2_4g[%d]=%d pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n", + tx_num, ext_pwr, + reg, bw, rate, bf, ch, tx_num , pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]); + + if (ext_pwr > 0) { + if (pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] > 0 && + pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] < ext_pwr) { + pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = + pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]; + } else { + pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = ext_pwr; + } + } else { + pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = + pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]; + } + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d] = %d\n", + PW_LMT_REGU_EXT_PWR, bw, rate, bf, ch, tx_num , + pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num]); + } + } + } + } + } + + reg = (u32)halrf_get_regulation_info(rf, BAND_ON_5G); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) { + real_ch = halrf_get_limit_ch_idx_to_ch_idx(rf, PW_LMT_BAND_5G, (u8)ch); + if (real_ch >= 36 && real_ch <= 48) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band1[tx_num]; + else if (real_ch >= 50 && real_ch <= 64) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band2[tx_num]; + else if (real_ch >= 100 && real_ch <= 144) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band3[tx_num]; + else if (real_ch >= 149 && real_ch <= 177) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band4[tx_num]; + + for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_MAX_BANDWIDTH_NUM; bw++) { + + RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_5g[%d]=%d pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n", + tx_num, ext_pwr, + reg, bw, rate, bf, ch, tx_num , pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]); + + if (ext_pwr > 0) { + if (pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] > 0 && + pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] < ext_pwr) { + pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = + pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]; + } else { + pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = ext_pwr; + } + } else { + pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = + pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]; + } + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_EXT_PWR, bw, rate, bf, ch, tx_num, + pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num]); + } + } + } + } + } + + RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__); +#endif +} + +void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf, + enum phl_phy_idx phy) +{ +#ifdef SPF_PHL_RF_019_SAR + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_hal_com_t *hal = rf->hal_com; + u32 reg, bw, rate, ch, tx_num; + s8 ext_pwr = 0; + u8 real_ch; + + RF_DBG(rf, DBG_RF_INIT, "======>%s phy=%d\n", __func__, phy); + + reg = (u32)halrf_get_regulation_info(rf, BAND_ON_24G); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_2_4g[tx_num]; + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) { + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) { + + RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_2_4g[%d]=%d pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n", + tx_num, ext_pwr, + reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]); + + if (ext_pwr > 0) { + if (pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] > 0 && + pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] < ext_pwr) { + pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = + pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]; + } else { + pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = ext_pwr; + } + } else { + pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = + pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]; + } + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d] = %d\n", + PW_LMT_REGU_EXT_PWR, bw, rate, ch, tx_num, + pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num]); + } + } + } + } + + reg = (u32)halrf_get_regulation_info(rf, BAND_ON_5G); + + for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) { + for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) { + real_ch = halrf_get_limit_ch_idx_to_ch_idx(rf, PW_LMT_BAND_5G, (u8)ch); + if (real_ch >= 36 && real_ch <= 48) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band1[tx_num]; + else if (real_ch >= 50 && real_ch <= 64) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band2[tx_num]; + else if (real_ch >= 100 && real_ch <= 144) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band3[tx_num]; + else if (real_ch >= 149 && real_ch <= 177) + ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band4[tx_num]; + + for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) { + for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) { + + RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_5g[%d]=%d pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n", + tx_num, ext_pwr, + reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]); + + if (ext_pwr > 0) { + if (pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] > 0 && + pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] < ext_pwr) { + pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = + pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]; + } else { + pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = ext_pwr; + } + } else { + pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = + pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]; + } + + RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n", + PW_LMT_REGU_EXT_PWR, bw, rate, ch, tx_num, + pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num]); + } + } + } + } + + RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__); +#endif +} + + +s8 halrf_get_power_by_rate(struct rf_info *rf, + enum phl_phy_idx phy, + u8 rf_path, u16 rate, u8 dcm, u8 offset) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u8 band; + u16 rate_tmp; + s8 pwr_by_rate; + u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch; + + RF_DBG(rf, DBG_RF_POWER, "======>%s rf_path=%d rate=0x%x dcm=%d\n", + __func__, rf_path, rate, dcm); + + if (channel >= 1 && channel <= 14) + band = PW_LMT_BAND_2_4G; + else + band = PW_LMT_BAND_5G; + + rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset); + + if ((rate_tmp >= HALRF_DATA_RATE_CCK1 && rate_tmp <= HALRF_DATA_RATE_CCK11) || + rate_tmp == HALRF_DATA_RATE_CCK_OFFSET) { + pwr_by_rate = pwr->tx_pwr_by_rate[PW_LMT_BAND_2_4G][rate_tmp]; + + RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] channel=%d\n", + pwr_by_rate, PW_LMT_BAND_2_4G, rate_tmp, channel); + } else { + pwr_by_rate = pwr->tx_pwr_by_rate[band][rate_tmp]; + + RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] channel=%d\n", + pwr_by_rate, band, rate_tmp, channel); + } + + return pwr_by_rate; +} + +s8 halrf_get_power_by_rate_band(struct rf_info *rf, + enum phl_phy_idx phy, u16 rate, u8 dcm, u8 offset, u32 band) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + u16 rate_tmp; + s8 pwr_by_rate; + + RF_DBG(rf, DBG_RF_POWER, "======>%s rate=0x%x dcm=%d band=%d\n", + __func__, rate, dcm, band); + + rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset); + + if ((rate_tmp >= HALRF_DATA_RATE_CCK1 && rate_tmp <= HALRF_DATA_RATE_CCK11) || + rate_tmp == HALRF_DATA_RATE_CCK_OFFSET) { + pwr_by_rate = pwr->tx_pwr_by_rate[PW_LMT_BAND_2_4G][rate_tmp]; + + RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] band=%d\n", + pwr_by_rate, PW_LMT_BAND_2_4G, rate_tmp, band); + } else { + pwr_by_rate = pwr->tx_pwr_by_rate[band][rate_tmp]; + + RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] band=%d\n", + pwr_by_rate, band, rate_tmp, band); + } + + return pwr_by_rate; +} + +s8 halrf_get_power_limit(struct rf_info *rf, + enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth, + u8 beamforming, u8 tx_num, u8 channel) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_phl_com_t *phl = rf->phl_com; + +#ifdef SPF_PHL_RF_019_SAR + struct rtw_hal_com_t *hal = rf->hal_com; +#endif + s8 pwr_limit; + u8 limit_rate = PW_LMT_RS_CCK, limit_ch, reg; + + RF_DBG(rf, DBG_RF_POWER, "======>%s rf_path=%d rate=0x%x beamforming=%d\n", + __func__, rf_path, rate, beamforming); + + limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate); + limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel); + + if (channel >= 1 && channel <= 14) { + +#ifdef SPF_PHL_RF_019_SAR + if (hal->ext_pwr_lmt_en == true) + reg = PW_LMT_REGU_EXT_PWR; + else +#endif + reg = halrf_get_regulation_info(rf, BAND_ON_24G); + + pwr_limit = pwr->tx_pwr_limit_2g[reg][bandwidth][limit_rate][beamforming][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n", + pwr_limit, reg, bandwidth, limit_rate, beamforming, limit_ch, tx_num); + } else { +#ifdef SPF_PHL_RF_019_SAR + if (hal->ext_pwr_lmt_en == true) + reg = PW_LMT_REGU_EXT_PWR; + else +#endif + reg = halrf_get_regulation_info(rf, BAND_ON_5G); + + pwr_limit = pwr->tx_pwr_limit_5g[reg][bandwidth][limit_rate][beamforming][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n", + pwr_limit, reg, bandwidth, limit_rate, beamforming, limit_ch, tx_num); + } + + if (pwr_limit == 127) + pwr_limit = 0; + + return pwr_limit; +} + +s8 halrf_get_power_limit_ru(struct rf_info *rf, + enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth, + u8 tx_num, u8 channel) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_phl_com_t *phl = rf->phl_com; + +#ifdef SPF_PHL_RF_019_SAR + struct rtw_hal_com_t *hal = rf->hal_com; +#endif + s8 pwr_limit_ru; + u8 limit_rate = PW_LMT_RS_CCK, limit_ch, reg; + + RF_DBG(rf, DBG_RF_POWER, "======>%s phy=%d rf_path=%d rate=0x%x\n", + __func__, phy, rf_path, rate); + + limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate); + limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel); + + if (channel >= 1 && channel <= 14) { +#ifdef SPF_PHL_RF_019_SAR + if (hal->ext_pwr_lmt_en == true) + reg = PW_LMT_REGU_EXT_PWR; + else +#endif + reg = halrf_get_regulation_info(rf, BAND_ON_24G); + + pwr_limit_ru = pwr->tx_pwr_limit_ru_2g[reg][bandwidth][limit_rate][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]\n", + pwr_limit_ru, reg, bandwidth, limit_rate, limit_ch, tx_num); + } else { +#ifdef SPF_PHL_RF_019_SAR + if (hal->ext_pwr_lmt_en == true) + reg = PW_LMT_REGU_EXT_PWR; + else +#endif + reg = halrf_get_regulation_info(rf, BAND_ON_5G); + + pwr_limit_ru = pwr->tx_pwr_limit_ru_5g[reg][bandwidth][limit_rate][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]\n", + pwr_limit_ru, reg, bandwidth, limit_rate, limit_ch, tx_num); + } + + if (pwr_limit_ru == 127) + pwr_limit_ru = 0; + + return pwr_limit_ru; +} + +s16 halrf_get_power(void *rf_void, + u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth, + u8 beamforming, u8 channel) +{ + struct rf_info *rf = (struct rf_info *)rf_void; + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_phl_com_t *phl = rf->phl_com; + u8 band, limit_rate = PW_LMT_RS_CCK, tx_num = PW_LMT_PH_1T, limit_ch; + u16 rate_tmp; + s16 pwr_by_rate, pwr_limit, power; + + RF_DBG(rf, DBG_RF_INIT, "======>%s rf_path=%d rate=%d dcm=%d bw=%d bf=%d ch=%d\n", + __func__, rf_path, rate, dcm, bandwidth, beamforming, channel); + + if (channel >= 1 && channel <= 14) + band = PW_LMT_BAND_2_4G; + else + band = PW_LMT_BAND_5G; + + tx_num = rf_path; + + rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset); + + pwr_by_rate = (s16)pwr->tx_pwr_by_rate[band][rate_tmp]; + + RF_DBG(rf, DBG_RF_INIT, "pwr_by_rate(%d)=(s16)pwr->tx_pwr_by_rate[%d][%d]\n", + pwr_by_rate, band, rate_tmp); + + limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate); + limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel); + + if (channel >= 1 && channel <= 14) { + pwr_limit = (s16)pwr->tx_pwr_limit_2g[halrf_get_regulation_info(rf, BAND_ON_24G)][bandwidth][limit_rate][beamforming][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_INIT, "pwr_limit(%d) = (s16)pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n", + pwr_limit, halrf_get_regulation_info(rf, BAND_ON_24G), bandwidth, limit_rate, beamforming, limit_ch, tx_num); + } else { + pwr_limit = (s16)pwr->tx_pwr_limit_5g[halrf_get_regulation_info(rf, BAND_ON_5G)][bandwidth][limit_rate][beamforming][limit_ch][tx_num]; + RF_DBG(rf, DBG_RF_INIT, "pwr_limit(%d) = (s16)pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n", + pwr_limit, halrf_get_regulation_info(rf, BAND_ON_5G), bandwidth, limit_rate, beamforming, limit_ch, tx_num); + } + + if (pwr_by_rate > pwr_limit) + power = pwr_limit; + else + power = pwr_by_rate; + + RF_DBG(rf, DBG_RF_INIT, "power = %d\n", power); + + return power; +} + +bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy, + enum phl_pwr_table pwr_table) +{ + struct rtw_hal_com_t *hal_com = rf->hal_com; + bool result = true; + +#ifdef RF_8852A_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852A) { + halrf_set_power_8852a(rf, phy, pwr_table); + } +#endif + +#ifdef RF_8852B_SUPPORT + if (hal_com->chip_id == CHIP_WIFI6_8852B) { + halrf_set_power_8852b(rf, phy, pwr_table); + } +#endif + + return result; +} + +bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx) +{ + struct rtw_phl_com_t *phl_com = rf->phl_com; + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_tpu_info *tpu = &rf->hal_com->band[phy_idx].rtw_tpu_i; + bool result = true; + + pwr->pwr_table_switch_efuse = phl_com->dev_cap.rf_board_opt & 0x3; + pwr->pwr_by_rate_switch = phl_com->dev_cap.pwrbyrate_off; + pwr->pwr_limit_switch = phl_com->dev_cap.pwrlmt_type; + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_by_rate_switch=%d\n", + __func__, pwr->pwr_by_rate_switch); + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_limit_switch=%d\n", + __func__, pwr->pwr_limit_switch); + + RF_DBG(rf, DBG_RF_POWER, "======>%s From Efuse pwr->pwr_table_switch_efuse=%d\n", + __func__, pwr->pwr_table_switch_efuse); + + if (pwr->pwr_limit_switch == PWLMT_DISABLE) + tpu->pwr_lmt_en = false; + else if (pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) + tpu->pwr_lmt_en = true; + else { + if (pwr->pwr_table_switch_efuse == 0) + tpu->pwr_lmt_en = false; + else if (pwr->pwr_table_switch_efuse == 2) + tpu->pwr_lmt_en = false; + else + tpu->pwr_lmt_en = true; + } + + halrf_mac_write_pwr_limit_en(rf, phy_idx); + + return result; +} + +void halrf_set_power_table_switch(struct rf_info *rf, + enum phl_phy_idx phy, u8 pwr_by_rate, u8 pwr_limt) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + + pwr->pwr_by_rate_switch = pwr_by_rate; + pwr->pwr_limit_switch = pwr_limt; +} + +u8 halrf_get_power_limit_extra(struct rf_info *rf) +{ + struct halrf_pwr_info *pwr = &rf->pwr_info; + struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL; + struct _halrf_file_regd_ext *pregd_codemap = NULL; + struct _halrf_file_regd_ext *array = NULL; + struct rtw_regulation_info rg_info = {0}; + struct rtw_hal_com_t *hal = rf->hal_com; + u8 i, j, regd_idx = 0xff; + + pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_info; + pregd_codemap = (struct _halrf_file_regd_ext *) pwrlmt_info->ext_reg_codemap; + + if (pwrlmt_info->para_src == 0) { + RF_DBG(rf, DBG_RF_POWER, "======>%s is_form_folder=%d Return!!!\n", + __func__, pwrlmt_info->para_src); + return 0xff; + } + + RF_DBG(rf, DBG_RF_POWER, "======>%s total_regd_idx=%d extra_limit_idx=%d\n", + __func__, pwrlmt_info->ext_regd_arridx, pwrlmt_info->ext_reg_map_num); + + halrf_query_regulation_info(rf, &rg_info); + + RF_DBG(rf, DBG_RF_POWER, "domain_code=0x%x country=%s regulation_2g=%d regulation_5g=%d chplan_ver=%d country_ver=%d\n", + rg_info.domain_code, rg_info.country, rg_info.regulation_2g, rg_info.regulation_5g, rg_info.chplan_ver, rg_info.country_ver); + + for (i = 0; i <= pwrlmt_info->ext_regd_arridx; i++) + RF_DBG(rf, DBG_RF_POWER, "ext_regd_name[%d]=%s\n", i, pwrlmt_info->ext_regd_name[i]); + + RF_DBG(rf, DBG_RF_POWER, "======> Start domain code Search\n"); + for (i = 0; i < pwrlmt_info->ext_reg_map_num; i++) { + array = (struct _halrf_file_regd_ext *)&pregd_codemap[i]; + + RF_DBG(rf, DBG_RF_POWER, "======> %d\n", i); + RF_DBG(rf, DBG_RF_POWER, "ent->domain=0x%x\n", array->domain); + RF_DBG(rf, DBG_RF_POWER, "ent->country=%s\n", array->country); + RF_DBG(rf, DBG_RF_POWER, "ent->reg_name=%s\n", array->reg_name); + + if (rg_info.domain_code == (u8)array->domain) { + RF_DBG(rf, DBG_RF_POWER, "Search rg_info.domain_code == Power limit array->domain\n"); + for (j = 0; j <= pwrlmt_info->ext_regd_arridx; j++) { + if (_os_strcmp(array->reg_name, pwrlmt_info->ext_regd_name[j]) == 0) { + regd_idx = j; + i = (u8)pwrlmt_info->ext_reg_map_num; + RF_DBG(rf, DBG_RF_POWER, "======> Search regd_idx=%d\n", regd_idx); + break; + } + } + } + } + RF_DBG(rf, DBG_RF_POWER, "<====== End domain code Search\n"); + + RF_DBG(rf, DBG_RF_POWER, "======> Start Country code Search\n"); + for (i = 0; i < pwrlmt_info->ext_reg_map_num; i++) { + array = (struct _halrf_file_regd_ext *)&pregd_codemap[i]; + + RF_DBG(rf, DBG_RF_POWER, "======> %d\n", i); + RF_DBG(rf, DBG_RF_POWER, "ent->domain=0x%x\n", array->domain); + RF_DBG(rf, DBG_RF_POWER, "ent->country=%s\n", array->country); + RF_DBG(rf, DBG_RF_POWER, "ent->reg_name=%s\n", array->reg_name); + + if (hal_mem_cmp(hal, rg_info.country, array->country, 2) == 0 && _os_strcmp(rg_info.country, "") != 0) { + RF_DBG(rf, DBG_RF_POWER, "Search rg_info.country == Power limit array->country\n"); + for (j = 0; j <= pwrlmt_info->ext_regd_arridx; j++) { + if (_os_strcmp(array->reg_name, pwrlmt_info->ext_regd_name[j]) == 0) { + regd_idx = j; + i = (u8)pwrlmt_info->ext_reg_map_num; + RF_DBG(rf, DBG_RF_POWER, "======> Search regd_idx=%d\n", regd_idx); + break; + } + } + } + } + RF_DBG(rf, DBG_RF_POWER, "<====== End Country code Search\n"); + + RF_DBG(rf, DBG_RF_POWER, "Return regd_idx = %d\n", regd_idx); + + return regd_idx; +} + +void halrf_reload_pwr_limit_tbl_and_set(struct rf_info *rf, + enum phl_phy_idx phy, enum phl_pwr_table pwr_table) +{ + struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL; + + bool is_form_folder; + u32 folder_len; + u32 *folder_array; + + RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__); + + if (pwr_table == PWR_LIMIT) { + pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_info; + + is_form_folder = pwrlmt_info->para_src; + folder_len = pwrlmt_info->para_data_len; + folder_array = pwrlmt_info->para_data; + + RF_DBG(rf, DBG_RF_POWER, "Reload power limit table and set. is_form_folder=%d folder_len=%d\n", + is_form_folder, folder_len); + + halrf_config_store_power_limit(rf , is_form_folder, + folder_len, folder_array); + + halrf_set_power(rf, phy, pwr_table); + } + + if (pwr_table == PWR_LIMIT_RU) { + pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_ru_info; + + is_form_folder = pwrlmt_info->para_src; + folder_len = pwrlmt_info->para_data_len; + folder_array = pwrlmt_info->para_data; + + RF_DBG(rf, DBG_RF_POWER, "Reload power limit RU table and set. is_form_folder=%d folder_len=%d\n", + is_form_folder, folder_len); + + halrf_config_store_power_limit_ru(rf , is_form_folder, + folder_len, folder_array); + + halrf_set_power(rf, phy, pwr_table); + } + + RF_DBG(rf, DBG_RF_POWER, "<======%s finish!\n", __func__); +} diff --git a/phl/hal_g6/phy/rf/halrf_pwr_table.h b/phl/hal_g6/phy/rf/halrf_pwr_table.h new file mode 100644 index 0000000..92fb657 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_pwr_table.h @@ -0,0 +1,375 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_PWR_TABLE_H_ +#define _HALRF_PWR_TABLE_H_ + +/*@--------------------------Define Parameters-------------------------------*/ +#define TX_PWR_BY_RATE_NUM_BAND 3 +#define TX_PWR_BY_RATE_NUM_RF 4 + +#define PW_LMT_MAX_2G_BANDWITH_NUM 2 +#define PW_LMT_MAX_CHANNEL_NUMBER_2G 14 +#define PW_LMT_MAX_CHANNEL_NUMBER_5G 53 + +#define TX_PWR_BY_RATE_NUM_MAC 44 +#define TX_PWR_LIMIT_NUM_MAC 80 +#define TX_PWR_LIMIT_RU_NUM_MAC 30 + +#define RADIO_TO_FW_PAGE_SIZE 6 +#define RADIO_TO_FW_DATA_SIZE 500 + + +/*@-----------------------End Define Parameters-----------------------*/ +/*power by rate*/ +enum halrf_pw_by_rate_para_type { + PW_BYRATE_PARA_NSS1, + PW_BYRATE_PARA_NSS2, + PW_BYRATE_PARA_OFFS = 0xF +}; + +enum halrf_pw_by_rate_rate_type { + PW_BYRATE_RATE_11M_1M, + PW_BYRATE_RATE_18M_6M, + PW_BYRATE_RATE_54M_24M, + PW_BYRATE_RATE_MCS3_0, + PW_BYRATE_RATE_MCS7_4, + PW_BYRATE_RATE_MCS11_8, + PW_BYRATE_RATE_DCM4_0, + PW_BYRATE_RATE_AllRate2_1, /* CCK, OFDM, HT, VHT */ + PW_BYRATE_RATE_AllRate2_2, /* HE_HEDCM */ + PW_BYRATE_RATE_AllRate5_1, /* OFDM, HT, VHT, HE_HEDCM */ + PW_BYRATE_RATE_NULL = 0xF +}; + +struct _halrf_file_regd_ext { + u16 domain; + char country[2]; + char reg_name[10]; +}; + +/*power limit*/ +struct halrf_tx_pw_lmt { + u8 band; + u8 bw; + u8 ntx; + u8 rs; + u8 bf; + u8 reg; + u8 ch; + s8 val; + u8 tx_shap_idx; +}; + +struct halrf_tx_pw_lmt_ru { + u8 band; + u8 bw; + u8 ntx; + u8 rs; + u8 reg; + u8 ch; + s8 val; + u8 tx_shap_idx; +}; + +enum halrf_tx_pw_lmt_ru_bandwidth_type { + PW_LMT_RU_BW_RU26 = 0, + PW_LMT_RU_BW_RU52, + PW_LMT_RU_BW_RU106, + PW_LMT_RU_BW_NULL +}; + +enum halrf_pw_lmt_regulation_type { + PW_LMT_REGU_WW13 = 0, + PW_LMT_REGU_ETSI = 1, + PW_LMT_REGU_FCC = 2, + PW_LMT_REGU_MKK = 3, + PW_LMT_REGU_NA = 4, + PW_LMT_REGU_IC = 5, + PW_LMT_REGU_KCC = 6, + PW_LMT_REGU_ACMA = 7, + PW_LMT_REGU_NCC = 8, + PW_LMT_REGU_MEXICO = 9, + PW_LMT_REGU_CHILE = 10, + PW_LMT_REGU_UKRAINE = 11, + PW_LMT_REGU_CN = 12, + PW_LMT_REGU_QATAR = 13, + /* place predefined ones above */ + PW_LMT_REGU_EXT_PWR, + PW_LMT_REGU_PREDEF_NUM, + PW_LMT_REGU_NULL, /* declare this to PW_LMT_MAX_REGULATION_NUM after limit array remove usage of PW_LMT_REGU_NULL */ + PW_LMT_MAX_REGULATION_NUM = 32 +}; + +enum halrf_tx_shape_modu_type { + TX_SHAPE_CCK, + TX_SHAPE_OFDM, + TX_SHAPE_MAX +}; + +enum halrf_pw_lmt_band_type { + PW_LMT_BAND_2_4G = 0, + PW_LMT_BAND_5G = 1, + PW_LMT_BAND_6G = 2, + PW_LMT_MAX_BAND = 3 +}; + +enum halrf_pw_lmt_bandwidth_type { + PW_LMT_BW_20M = 0, + PW_LMT_BW_40M = 1, + PW_LMT_BW_80M = 2, + PW_LMT_BW_160M = 3, + PW_LMT_MAX_BANDWIDTH_NUM = 4 +}; + +enum halrf_pw_lmt_ratesection_type { + PW_LMT_RS_CCK = 0, + PW_LMT_RS_OFDM = 1, + PW_LMT_RS_HT = 2, + PW_LMT_RS_VHT = 3, + PW_LMT_RS_HE = 4, + PW_LMT_MAX_RS_NUM = 5 +}; + +enum halrf_pw_lmt_rfpath_type { + PW_LMT_PH_1T = 0, + PW_LMT_PH_2T = 1, + PW_LMT_PH_3T = 2, + PW_LMT_PH_4T = 3, + PW_LMT_MAX_PH_NUM = 4 +}; + +enum halrf_pw_lmt_beamforming_type { + PW_LMT_NONBF = 0, + PW_LMT_BF = 1, + PW_LMT_MAX_BF_NUM = 2 +}; + +enum halrf_data_rate { + HALRF_DATA_RATE_CCK1 = 0, + HALRF_DATA_RATE_CCK2 = 0x1, + HALRF_DATA_RATE_CCK5_5, + HALRF_DATA_RATE_CCK11, + HALRF_DATA_RATE_OFDM6, + HALRF_DATA_RATE_OFDM9, + HALRF_DATA_RATE_OFDM12, + HALRF_DATA_RATE_OFDM18, + HALRF_DATA_RATE_OFDM24, + HALRF_DATA_RATE_OFDM36, + HALRF_DATA_RATE_OFDM48 = 10, + HALRF_DATA_RATE_OFDM54, + HALRF_DATA_RATE_MCS0, + HALRF_DATA_RATE_MCS1, + HALRF_DATA_RATE_MCS2, + HALRF_DATA_RATE_MCS3, + HALRF_DATA_RATE_MCS4, + HALRF_DATA_RATE_MCS5, + HALRF_DATA_RATE_MCS6, + HALRF_DATA_RATE_MCS7, + HALRF_DATA_RATE_MCS8 = 20, + HALRF_DATA_RATE_MCS9, + HALRF_DATA_RATE_MCS10, + HALRF_DATA_RATE_MCS11, + HALRF_DATA_RATE_MCS12, + HALRF_DATA_RATE_MCS13, + HALRF_DATA_RATE_MCS14, + HALRF_DATA_RATE_MCS15, + HALRF_DATA_RATE_MCS16, + HALRF_DATA_RATE_MCS17, + HALRF_DATA_RATE_MCS18 = 30, + HALRF_DATA_RATE_MCS19, + HALRF_DATA_RATE_MCS20, + HALRF_DATA_RATE_MCS21, + HALRF_DATA_RATE_MCS22, + HALRF_DATA_RATE_MCS23, + HALRF_DATA_RATE_MCS24, + HALRF_DATA_RATE_MCS25, + HALRF_DATA_RATE_MCS26, + HALRF_DATA_RATE_MCS27, + HALRF_DATA_RATE_MCS28 = 40, + HALRF_DATA_RATE_MCS29, + HALRF_DATA_RATE_MCS30, + HALRF_DATA_RATE_MCS31, + HALRF_DATA_RATE_VHT_NSS1_MCS0, + HALRF_DATA_RATE_VHT_NSS1_MCS1, + HALRF_DATA_RATE_VHT_NSS1_MCS2, + HALRF_DATA_RATE_VHT_NSS1_MCS3, + HALRF_DATA_RATE_VHT_NSS1_MCS4, + HALRF_DATA_RATE_VHT_NSS1_MCS5, + HALRF_DATA_RATE_VHT_NSS1_MCS6 = 50, + HALRF_DATA_RATE_VHT_NSS1_MCS7, + HALRF_DATA_RATE_VHT_NSS1_MCS8, + HALRF_DATA_RATE_VHT_NSS1_MCS9, + HALRF_DATA_RATE_VHT_NSS2_MCS0, + HALRF_DATA_RATE_VHT_NSS2_MCS1, + HALRF_DATA_RATE_VHT_NSS2_MCS2, + HALRF_DATA_RATE_VHT_NSS2_MCS3, + HALRF_DATA_RATE_VHT_NSS2_MCS4, + HALRF_DATA_RATE_VHT_NSS2_MCS5, + HALRF_DATA_RATE_VHT_NSS2_MCS6 = 60, + HALRF_DATA_RATE_VHT_NSS2_MCS7, + HALRF_DATA_RATE_VHT_NSS2_MCS8, + HALRF_DATA_RATE_VHT_NSS2_MCS9, + HALRF_DATA_RATE_VHT_NSS3_MCS0, + HALRF_DATA_RATE_VHT_NSS3_MCS1, + HALRF_DATA_RATE_VHT_NSS3_MCS2, + HALRF_DATA_RATE_VHT_NSS3_MCS3, + HALRF_DATA_RATE_VHT_NSS3_MCS4, + HALRF_DATA_RATE_VHT_NSS3_MCS5, + HALRF_DATA_RATE_VHT_NSS3_MCS6 = 70, + HALRF_DATA_RATE_VHT_NSS3_MCS7, + HALRF_DATA_RATE_VHT_NSS3_MCS8, + HALRF_DATA_RATE_VHT_NSS3_MCS9, + HALRF_DATA_RATE_VHT_NSS4_MCS0, + HALRF_DATA_RATE_VHT_NSS4_MCS1, + HALRF_DATA_RATE_VHT_NSS4_MCS2, + HALRF_DATA_RATE_VHT_NSS4_MCS3, + HALRF_DATA_RATE_VHT_NSS4_MCS4, + HALRF_DATA_RATE_VHT_NSS4_MCS5, + HALRF_DATA_RATE_VHT_NSS4_MCS6 = 80, + HALRF_DATA_RATE_VHT_NSS4_MCS7, + HALRF_DATA_RATE_VHT_NSS4_MCS8, + HALRF_DATA_RATE_VHT_NSS4_MCS9, + HALRF_DATA_RATE_HE_NSS1_MCS0, + HALRF_DATA_RATE_HE_NSS1_MCS1, + HALRF_DATA_RATE_HE_NSS1_MCS2, + HALRF_DATA_RATE_HE_NSS1_MCS3, + HALRF_DATA_RATE_HE_NSS1_MCS4, + HALRF_DATA_RATE_HE_NSS1_MCS5, + HALRF_DATA_RATE_HE_NSS1_MCS6 = 90, + HALRF_DATA_RATE_HE_NSS1_MCS7, + HALRF_DATA_RATE_HE_NSS1_MCS8, + HALRF_DATA_RATE_HE_NSS1_MCS9, + HALRF_DATA_RATE_HE_NSS1_MCS10, + HALRF_DATA_RATE_HE_NSS1_MCS11, + HALRF_DATA_RATE_HE_NSS2_MCS0, + HALRF_DATA_RATE_HE_NSS2_MCS1, + HALRF_DATA_RATE_HE_NSS2_MCS2, + HALRF_DATA_RATE_HE_NSS2_MCS3, + HALRF_DATA_RATE_HE_NSS2_MCS4 = 100, + HALRF_DATA_RATE_HE_NSS2_MCS5, + HALRF_DATA_RATE_HE_NSS2_MCS6, + HALRF_DATA_RATE_HE_NSS2_MCS7, + HALRF_DATA_RATE_HE_NSS2_MCS8, + HALRF_DATA_RATE_HE_NSS2_MCS9, + HALRF_DATA_RATE_HE_NSS2_MCS10, + HALRF_DATA_RATE_HE_NSS2_MCS11, + HALRF_DATA_RATE_HE_NSS3_MCS0, + HALRF_DATA_RATE_HE_NSS3_MCS1, + HALRF_DATA_RATE_HE_NSS3_MCS2 = 110, + HALRF_DATA_RATE_HE_NSS3_MCS3, + HALRF_DATA_RATE_HE_NSS3_MCS4, + HALRF_DATA_RATE_HE_NSS3_MCS5, + HALRF_DATA_RATE_HE_NSS3_MCS6, + HALRF_DATA_RATE_HE_NSS3_MCS7, + HALRF_DATA_RATE_HE_NSS3_MCS8, + HALRF_DATA_RATE_HE_NSS3_MCS9, + HALRF_DATA_RATE_HE_NSS3_MCS10, + HALRF_DATA_RATE_HE_NSS3_MCS11, + HALRF_DATA_RATE_HE_NSS4_MCS0 = 120, + HALRF_DATA_RATE_HE_NSS4_MCS1, + HALRF_DATA_RATE_HE_NSS4_MCS2, + HALRF_DATA_RATE_HE_NSS4_MCS3, + HALRF_DATA_RATE_HE_NSS4_MCS4, + HALRF_DATA_RATE_HE_NSS4_MCS5, + HALRF_DATA_RATE_HE_NSS4_MCS6, + HALRF_DATA_RATE_HE_NSS4_MCS7, + HALRF_DATA_RATE_HE_NSS4_MCS8, + HALRF_DATA_RATE_HE_NSS4_MCS9, + HALRF_DATA_RATE_HE_NSS4_MCS10 = 130, + HALRF_DATA_RATE_HE_NSS4_MCS11, + HALRF_DATA_RATE_HEDCM_NSS1_MCS0, + HALRF_DATA_RATE_HEDCM_NSS1_MCS1, + HALRF_DATA_RATE_HEDCM_NSS1_MCS3, + HALRF_DATA_RATE_HEDCM_NSS1_MCS4, + HALRF_DATA_RATE_HEDCM_NSS2_MCS0, + HALRF_DATA_RATE_HEDCM_NSS2_MCS1, + HALRF_DATA_RATE_HEDCM_NSS2_MCS3, + HALRF_DATA_RATE_HEDCM_NSS2_MCS4, + HALRF_DATA_RATE_HEDCM_OFFSET = 140, + HALRF_DATA_RATE_VHT_OFFSET, + HALRF_DATA_RATE_HT_OFFSET, + HALRF_DATA_RATE_OFDM_OFFSET, + HALRF_DATA_RATE_CCK_OFFSET, + HALRF_DATA_RATE_MAX +}; + +struct halrf_pwr_info { + /*Power by Rate and Power Limit Switch*/ + u8 pwr_table_switch_efuse; + u8 pwr_by_rate_switch; + u8 pwr_limit_switch; + + bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_REGULATION_NUM]; + u8 tx_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_REGULATION_NUM]; + s8 tx_pwr_by_rate[TX_PWR_BY_RATE_NUM_BAND][HALRF_DATA_RATE_MAX]; + + s8 tx_pwr_limit_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_2G_BANDWITH_NUM] + [PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH]; + + s8 tx_pwr_limit_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM] + [PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH]; + + s8 tx_pwr_limit_ru_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL] + [PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH]; + + s8 tx_pwr_limit_ru_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL] + [PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH]; + + s8 tx_pwr_by_rate_mac[HW_PHY_MAX][TX_PWR_BY_RATE_NUM_MAC]; + + s8 tx_pwr_limit_mac[HW_PHY_MAX][TX_PWR_LIMIT_NUM_MAC]; + + s8 tx_pwr_limit_ru_mac[HW_PHY_MAX][TX_PWR_LIMIT_RU_NUM_MAC]; + s16 tx_pwr_limit_ru26_mac[HW_PHY_MAX]; + s16 tx_pwr_limit_ru52_mac[HW_PHY_MAX]; + s16 tx_pwr_limit_ru106_mac[HW_PHY_MAX]; + bool coex_pwr_ctl_enable; + bool dpk_pwr_ctl_enable; + s32 coex_pwr; + s32 dpk_pwr; + u8 mp_regulation; + u8 regulation_idx; + u8 regulation_str[10]; + bool fix_power[MAX_HALRF_PATH]; + s8 fix_power_dbm[MAX_HALRF_PATH]; + bool set_tx_ptrn_shap_en; + u8 set_tx_ptrn_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX]; +}; + +extern const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM]; +#define pw_lmt_regu_type_str(lmt) ((lmt) < PW_LMT_MAX_REGULATION_NUM ? _pw_lmt_regu_type_str[(lmt)] : NULL) + +extern const enum halrf_pw_lmt_regulation_type _regulation_to_pw_lmt_regu_type[REGULATION_MAX]; +#define regulation_to_pw_lmt_regu_type(reg) ((reg) < REGULATION_MAX ? _regulation_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13) + +extern const enum halrf_pw_lmt_regulation_type _tpo_to_pw_lmt_regu_type[TPO_NA]; +#define tpo_to_pw_lmt_regu_type(reg) ((reg) < TPO_NA ? _tpo_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13) + +u8 halrf_get_regulation_info(struct rf_info *rf, u8 band); + +void halrf_power_by_rate_store_to_array(struct rf_info *rf, + u32 band, u32 tx_num, u32 rate_id, u32 data); +void halrf_power_limit_store_to_array(struct rf_info *rf, + u8 regulation, u8 band, u8 bandwidth, u8 rate, + u8 tx_num, u8 beamforming, u8 chnl, s8 val); +void halrf_power_limit_set_worldwide(struct rf_info *rf); +void halrf_power_limit_ru_store_to_array(struct rf_info *rf, + u8 band, u8 bandwidth, u8 tx_num, u8 rate, + u8 regulation, u8 chnl, s8 val); +void halrf_power_limit_ru_set_worldwide(struct rf_info *rf); + +u8 halrf_get_power_limit_extra(struct rf_info *rf); + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_pwr_track.h b/phl/hal_g6/phy/rf/halrf_pwr_track.h new file mode 100644 index 0000000..8785dd7 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_pwr_track.h @@ -0,0 +1,214 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_PWR_TRACK_H_ +#define _HALRF_PWR_TRACK_H_ + +/*@--------------------------Define Parameters-------------------------------*/ +#define AVG_THERMAL_NUM 8 +#define MAX_RF_PATH 4 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 3 +#define DELTA_SWINTSSI_SIZE 61 +#define TSSI_EFUSE_RATE 2 +#define TSSI_EFUSE_NUM 19 +#define TSSI_HIDE_EFUSE_NUM 8 +#define AVG_THERMAL_NUM_TSSI 2 +#define MAX_CH_NUM 67 +#define TSSI_ALIMK_VAULE_NUM 8 + +#define MAX_HALRF_PATH 2 + +/*@---------------------------End Define Parameters---------------------------*/ + +enum halrf_tssi_rate_type { + EFUSE_TSSI_CCK = 0, + EFUSE_TSSI_MCS +}; + +enum halrf_tssi_type{ + TSSI_OFF = 0, + TSSI_ON, + TSSI_CAL +}; + +enum halrf_tssi_alimk_band{ + TSSI_ALIMK_2G = 0, + TSSI_ALIMK_5GL, + TSSI_ALIMK_5GM, + TSSI_ALIMK_5GH, + TSSI_ALIMK_MAX +}; + +struct halrf_pwr_track_info { + /* u8 is_txpowertracking; */ + u8 tx_powercount; + bool is_txpowertracking_init; + bool is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_path[MAX_RF_PATH]; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_avg_index_path[MAX_RF_PATH]; + s8 power_index_offset_path[MAX_RF_PATH]; + + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + bool txpowertracking_in_progress; + + bool is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset; + s8 delta_power_index; + s8 delta_power_index_path[MAX_RF_PATH]; + s8 delta_power_index_last; + s8 delta_power_index_last_path[MAX_RF_PATH]; + bool is_tx_power_changed; + + /*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/ + u8 delta_lck; + s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; + u8 bb_swing_idx_ofdm_base; + u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH]; + bool bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + bool bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + bool modify_tx_agc_flag_path_a; + bool modify_tx_agc_flag_path_b; + bool modify_tx_agc_flag_path_c; + bool modify_tx_agc_flag_path_d; + bool modify_tx_agc_flag_path_a_cck; + bool modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ +}; + +struct halrf_tssi_info{ + u8 thermal[MAX_HALRF_PATH]; + u8 do_tssi_thermal[MAX_HALRF_PATH]; + s32 tssi_de[MAX_HALRF_PATH]; + u8 tssi_type; + s8 tssi_efuse[MAX_HALRF_PATH][TSSI_EFUSE_RATE][TSSI_EFUSE_NUM]; + s8 tssi_trim[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM]; + s32 tssi_xdbm; + s8 curr_tssi_cck_de[MAX_HALRF_PATH]; + s8 curr_tssi_efuse_cck_de[MAX_HALRF_PATH]; + s8 curr_tssi_ofdm_de[MAX_HALRF_PATH]; + s8 curr_tssi_efuse_ofdm_de[MAX_HALRF_PATH]; + s8 curr_tssi_trim_de[MAX_HALRF_PATH]; + bool do_tssi; + bool base_thermal_check[MAX_HALRF_PATH]; + u32 base_thermal[MAX_HALRF_PATH]; + u32 tssi_stop_power[MAX_HALRF_PATH]; + bool tssi_tracking_check[MAX_HALRF_PATH]; + u8 ther_avg[MAX_HALRF_PATH][AVG_THERMAL_NUM_TSSI]; /*path*/ + u8 ther_avg_idx[MAX_HALRF_PATH]; + u8 ther_avg_fifo_idx[MAX_HALRF_PATH]; + u32 ther_avg_final[MAX_HALRF_PATH]; + s8 extra_ofst[MAX_HALRF_PATH]; + /*bool normal_tssi_tracking;*/ + u8 normal_tssi_tracking_times; + u8 default_txagc_offset_check; + u8 default_txagc_offset_times; + u32 default_txagc_offset[MAX_HALRF_PATH]; + s16 ref_pow_ofdm; /*-> HW: s(9,2)*/ + s16 ref_pow_ofdm_offset; + u32 high_pwr_rst_cnt; + u8 cur_ch; + u8 cur_bw; + u32 backup_txagc_offset[MAX_HALRF_PATH][MAX_CH_NUM]; + u8 backup_txagc_oft_ther[MAX_HALRF_PATH][MAX_CH_NUM]; + bool check_backup_txagc[MAX_CH_NUM]; + u32 start_time, finish_time; + u32 alignment_value[MAX_HALRF_PATH][TSSI_ALIMK_MAX][TSSI_ALIMK_VAULE_NUM]; + bool alignment_done[MAX_HALRF_PATH][TSSI_ALIMK_MAX]; +}; + +struct halrf_xtal_info{ + s8 delta_swing_xtal_table_idx_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_xtal_table_idx_n[DELTA_SWINGIDX_SIZE]; +}; + +#endif \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/halrf_struct.h b/phl/hal_g6/phy/rf/halrf_struct.h new file mode 100644 index 0000000..c35efcd --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_struct.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_STRUCT_H_ +#define _HALRF_STRUCT_H_ + + +struct hal_rf_t { + struct rtw_phl_com_t *phl_com; + struct rtw_hal_com_t *hal_com; + +}; + +#endif /*_HALRF_STRUCT_H_*/ diff --git a/phl/hal_g6/phy/rf/halrf_txgapk.h b/phl/hal_g6/phy/rf/halrf_txgapk.h new file mode 100644 index 0000000..9761c50 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_txgapk.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HALRF_TXGAPK_H_ +#define _HALRF_TXGAPK_H_ +#include "halrf_headers.h" + +#define NUM 4 + +enum txgapk_id { + TXGAPK_TRACK = 0x00, + TXGAPK_PWR = 0x01, + TXGAPK_IQKBK = 0x02 +}; + + +struct halrf_gapk_info { + + bool is_gapk_init; + u32 gapk_rf3f_bp[5][12][NUM]; /* band(2Gcck/2GOFDM/5GL/5GM/5GH)/idx/path */ + bool gapk_bp_done; + s8 offset[12][NUM]; + s8 fianl_offset[12][NUM]; + u8 read_txgain; + bool is_gapk_enable; + u8 band[NUM]; + u8 ch[NUM]; + u8 bw[NUM]; + s32 track_d[2][17]; + s32 track_ta[2][17]; + s32 power_d[2][17]; + s32 power_ta[2][17]; + + bool is_txgapk_ok; + u32 r0x8010[2]; /* before and after txgapk */ + u32 txgapk_chk_cnt[2][3][2]; /* path */ /* track pwr iqkbk*/ /* 0xbff8 0x80fc*/ + + /* u8 txgapk_mcc_ch[2][NUM]; */ + /* u8 txgapk_table_idx[NUM]; */ + u8 txgapk_mcc_ch[2]; /* channel */ + u8 txgapk_table_idx; +}; + +#endif diff --git a/phl/hal_g6/phy/rf/halrf_wpp.h b/phl/hal_g6/phy/rf/halrf_wpp.h new file mode 100644 index 0000000..f063498 --- /dev/null +++ b/phl/hal_g6/phy/rf/halrf_wpp.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HALRF_WPP_H__ +#define __HALRF_WPP_H__ + +#define HALRF_WPP_CONTROL_GUIDS \ + WPP_DEFINE_CONTROL_GUID( \ + HalrfGuid, (C01A40AB,B69E,4CF6,BB09,4E0672EA2FC6), \ + WPP_DEFINE_BIT(DBG_RF_TX_PWR_TRACK) \ + WPP_DEFINE_BIT(DBG_RF_IQK) \ + WPP_DEFINE_BIT(DBG_RF_LCK) \ + WPP_DEFINE_BIT(DBG_RF_DPK) \ + WPP_DEFINE_BIT(DBG_RF_TXGAPK) \ + WPP_DEFINE_BIT(DBG_RF_DACK) \ + WPP_DEFINE_BIT(DBG_RF_DPK_TRACK) \ + WPP_DEFINE_BIT(DBG_RF_RXDCK) \ + WPP_DEFINE_BIT(DBG_RF_RFK) \ + WPP_DEFINE_BIT(DBG_RF_INIT) \ + WPP_DEFINE_BIT(DBG_RF_POWER) \ + WPP_DEFINE_BIT(DBG_RF_RXGAINK) \ + WPP_DEFINE_BIT(DBG_RF_THER_TRIM) \ + WPP_DEFINE_BIT(DBG_RF_PABIAS_TRIM) \ + WPP_DEFINE_BIT(DBG_RF_TSSI_TRIM) \ + WPP_DEFINE_BIT(DBG_RF_FW) \ + WPP_DEFINE_BIT(DBG_RF_MP) \ + WPP_DEFINE_BIT(DBG_RF_TMP) \ + WPP_DEFINE_BIT(DBG_RF_PSD) \ + ) + +#endif /* __HALRF_WPP_H__ */ \ No newline at end of file diff --git a/phl/hal_g6/phy/rf/rf.mk b/phl/hal_g6/phy/rf/rf.mk new file mode 100644 index 0000000..5d36cc1 --- /dev/null +++ b/phl/hal_g6/phy/rf/rf.mk @@ -0,0 +1,94 @@ +# All needed files would be added to _HAL_INTFS_FILES, and it would include +# hal_g6/phy/rf and all related files in directory hal_g6/phy/rf/. +# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC +# (CONFIG_RTL*) setting are all ready! + +HAL = hal_g6 + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/hal_g6 +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := hal_g6 +phl_path_d1 := $(src)/$(HAL) +endif + +# Base directory +path_halrf_d1 := $(phl_path)/phy/rf + +halrf-y += $(path_halrf_d1)/halrf.o \ + $(path_halrf_d1)/halrf_pmac.o \ + $(path_halrf_d1)/halrf_api.o \ + $(path_halrf_d1)/halrf_dbg.o \ + $(path_halrf_d1)/halrf_dbg_cmd.o \ + $(path_halrf_d1)/halrf_ex.o \ + $(path_halrf_d1)/halrf_hw_cfg.o \ + $(path_halrf_d1)/halrf_init.o \ + $(path_halrf_d1)/halrf_interface.o \ + $(path_halrf_d1)/halrf_pwr_table.o \ + $(path_halrf_d1)/halrf_iqk.o \ + +ifeq ($(CONFIG_RTL8852A), y) +ic := 8852a + +# Level 2 directory +path_halrf_8852a := $(path_halrf_d1)/halrf_$(ic) + +halrf-y += $(path_halrf_8852a)/halrf_8852a.o \ + $(path_halrf_8852a)/halrf_8852a_api.o \ + $(path_halrf_8852a)/halrf_hwimg_8852a.o\ + $(path_halrf_8852a)/halrf_txgapk_8852a.o\ + $(path_halrf_8852a)/halrf_iqk_8852a.o\ + $(path_halrf_8852a)/halrf_reg_cfg_8852a.o\ + $(path_halrf_8852a)/halrf_dpk_8852a.o\ + $(path_halrf_8852a)/halrf_dack_8852a.o\ + $(path_halrf_8852a)/halrf_set_pwr_table_8852a.o\ + $(path_halrf_8852a)/halrf_efuse_8852a.o\ + $(path_halrf_8852a)/halrf_tssi_8852a.o\ + $(path_halrf_8852a)/halrf_kfree_8852a.o\ + $(path_halrf_8852a)/halrf_psd_8852a.o +endif + +ifeq ($(CONFIG_RTL8852B), y) +ic := 8852b + +# Level 2 directory +path_halrf_8852b := $(path_halrf_d1)/halrf_$(ic) + +halrf-y += $(path_halrf_8852b)/halrf_8852b.o\ + $(path_halrf_8852b)/halrf_8852b_api.o \ + $(path_halrf_8852b)/halrf_hwimg_8852b.o\ + $(path_halrf_8852b)/halrf_txgapk_8852b.o\ + $(path_halrf_8852b)/halrf_iqk_8852b.o\ + $(path_halrf_8852b)/halrf_reg_cfg_8852b.o\ + $(path_halrf_8852b)/halrf_dack_8852b.o \ + $(path_halrf_8852b)/halrf_dpk_8852b.o \ + $(path_halrf_8852b)/halrf_set_pwr_table_8852b.o\ + $(path_halrf_8852b)/halrf_efuse_8852b.o\ + $(path_halrf_8852b)/halrf_tssi_8852b.o\ + $(path_halrf_8852b)/halrf_kfree_8852b.o\ + $(path_halrf_8852b)/halrf_psd_8852b.o +endif + +ifeq ($(CONFIG_RTL8852C), y) +ic := 8852c + +# Level 2 directory +path_halrf_8852c := $(path_halrf_d1)/halrf_$(ic) + +halrf-y += $(path_halrf_8852c)/halrf_8852c.o \ +// $(path_halrf_8852a)/halrf_8852c_api.o \ +// $(path_halrf_8852a)/halrf_hwimg_8852c.o\ +// $(path_halrf_8852a)/halrf_txgapk_8852c.o\ +// $(path_halrf_8852a)/halrf_iqk_8852c.o\ +// $(path_halrf_8852a)/halrf_reg_cfg_8852c.o\ +// $(path_halrf_8852a)/halrf_dpk_8852c.o\ +// $(path_halrf_8852a)/halrf_dack_8852c.o\ +// $(path_halrf_8852a)/halrf_set_pwr_table_8852c.o\ +// $(path_halrf_8852a)/halrf_efuse_8852c.o\ +// $(path_halrf_8852a)/halrf_tssi_8852c.o\ +// $(path_halrf_8852a)/halrf_kfree_8852c.o\ +// $(path_halrf_8852a)/halrf_psd_8852c.o +endif + +_HAL_RF_FILES += $(halrf-y) diff --git a/phl/hal_g6/rtl8852b/hal_trx_8852b.c b/phl/hal_g6/rtl8852b/hal_trx_8852b.c new file mode 100644 index 0000000..03c0e91 --- /dev/null +++ b/phl/hal_g6/rtl8852b/hal_trx_8852b.c @@ -0,0 +1,651 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TRX_8852B_C_ +#include "../hal_headers.h" +#include "rtl8852b_hal.h" + +static void _hal_trx_8852b_dump_rxcnt(struct hal_ppdu_sts *ppdu_sts) +{ + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "ppdu_sts->rx_cnt_size = 0x%x\n", ppdu_sts->rx_cnt_size); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_FAM]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_OK = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_OK]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_FAIL = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_FAIL]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_PPDU = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_PPDU]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_FAM = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_FAM]); + + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_FULLDRP = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_FULLDRP]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_FULLDRP_PKT = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_FULLDRP_PKT]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_PKTFLTR_DRP = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_PKTFLTR_DRP]); + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_RXDMA = 0x%x\n", + ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_RXDMA]); +} + +static void _hal_dump_rxdesc(u8 *buf, struct rtw_r_meta_data *mdata) +{ + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "%s ==>\n", __FUNCTION__); + + debug_dump_data(buf, 56, "_hal_dump_rxdesc:: "); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pktlen = 0x%X\n", mdata->pktlen); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->shift = 0x%X\n", mdata->shift); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->wl_hd_iv_len = 0x%X\n", + mdata->wl_hd_iv_len); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bb_sel = 0x%X\n", + mdata->bb_sel); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mac_info_vld = 0x%X\n", + mdata->mac_info_vld); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rpkt_type = 0x%X\n", + mdata->rpkt_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->drv_info_size = 0x%X\n", + mdata->drv_info_size); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->long_rxd = 0x%X\n", + mdata->long_rxd); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_type = 0x%X\n", + mdata->ppdu_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_cnt = 0x%X\n", + mdata->ppdu_cnt); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sr_en = 0x%X\n", + mdata->sr_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->user_id = 0x%X\n", + mdata->user_id); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_rate = 0x%X\n", + mdata->rx_rate); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_gi_ltf = 0x%X\n", + mdata->rx_gi_ltf); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->non_srg_ppdu = 0x%X\n", + mdata->non_srg_ppdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->inter_ppdu = 0x%X\n", + mdata->inter_ppdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bw = 0x%X\n", + mdata->bw ); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->freerun_cnt = 0x%X\n", + mdata->freerun_cnt); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->a1_match = 0x%X\n", + mdata->a1_match); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sw_dec = 0x%X\n", + mdata->sw_dec); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->hw_dec = 0x%X\n", + mdata->hw_dec); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu = 0x%X\n", + mdata->ampdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu_end_pkt = 0x%X\n", + mdata->ampdu_end_pkt); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu = 0x%X\n", + mdata->amsdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu_cut = 0x%X\n", + mdata->amsdu_cut); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->last_msdu = 0x%X\n", + mdata->last_msdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bypass = 0x%X\n", + mdata->bypass); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->crc32 = 0x%X\n", + mdata->crc32); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->icverr = 0x%X\n", + mdata->icverr); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->magic_wake = 0x%X\n", + mdata->magic_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->unicast_wake = 0x%X\n", + mdata->unicast_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_wake = 0x%X\n", + mdata->pattern_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->get_ch_info = 0x%X \n", + mdata->get_ch_info); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_statistics = 0x%X", + mdata->rx_statistics); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_idx = 0x%X", + mdata->pattern_idx); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->target_idc = 0x%X", + mdata->target_idc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->chksum_ofld_en = 0x%X", + mdata->chksum_ofld_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->with_llc = 0x%X", + mdata->with_llc); + if (mdata->long_rxd == 1) { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frame_type = 0x%X", + mdata->frame_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mc = 0x%X", + mdata->mc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bc = 0x%X", + mdata->bc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_data = 0x%X", + mdata->more_data); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_frag = 0x%X", + mdata->more_frag); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pwr_bit = 0x%X", + mdata->pwr_bit); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->qos = 0x%X", + mdata->qos); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->tid = 0x%X", + mdata->tid); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->eosp = 0x%X", + mdata->eosp); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->htc = 0x%X", + mdata->htc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->q_null = 0x%X", + mdata->q_null); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->seq = 0x%X", + mdata->seq); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frag_num = 0x%X", + mdata->frag_num); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sec_cam_idx = 0x%X", + mdata->sec_cam_idx); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam = 0x%X", + mdata->addr_cam); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->macid = 0x%X\n", + mdata->macid); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_id = 0x%X", + mdata->rx_pl_id); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam_vld = 0x%X", + mdata->addr_cam_vld); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_fwd_en = 0x%X", + mdata->addr_fwd_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_match = 0x%X", + mdata->rx_pl_match); + + debug_dump_data(mdata->mac_addr, 6, "mdata->mac_addr = \n"); + } +} + + static enum rtw_hal_status + hal_handle_chaninfo_8852b(struct hal_info_t *hal) + { + return RTW_HAL_STATUS_SUCCESS; + } + + /** + * SW Parsing Rx Desc - hal_parsing_rx_wd_8852b + * description: + * Parsing Rx WiFi Desc by Halmac or SW Manually + * input: + * hal : hal ic adapter + * desc : pointer of the start of rx desc + * output: + * pkt : pointer of the start of pkt; + * pkt_len : the pkt length + * rxwd : rx desc + */ +static enum rtw_hal_status +_hal_parsing_rx_wd_8852b(struct hal_info_t *hal, u8 *desc, + struct rtw_r_meta_data *mdata) +{ + /* ToDo: Parse word by word with byte swap once for + * each word + */ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct rtw_hal_com_t *hal_com = hal->hal_com; + + mdata->pktlen = GET_RX_AX_DESC_PKT_LEN_8852B(desc); + mdata->shift = GET_RX_AX_DESC_SHIFT_8852B(desc); + mdata->bb_sel = GET_RX_AX_DESC_BB_SEL_8852B(desc); + mdata->mac_info_vld = GET_RX_AX_DESC_MAC_INFO_VLD_8852B(desc); + mdata->rpkt_type = GET_RX_AX_DESC_RPKT_TYPE_8852B(desc); + mdata->drv_info_size = GET_RX_AX_DESC_DRV_INFO_SIZE_8852B(desc); + mdata->long_rxd = GET_RX_AX_DESC_LONG_RXD_8852B(desc); + + if ( (mdata->rpkt_type == RX_8852B_DESC_PKT_T_WIFI) + || (mdata->rpkt_type == RX_8852B_DESC_PKT_T_PPDU_STATUS)) { + mdata->wl_hd_iv_len = GET_RX_AX_DESC_HDR_IV_L_8852B(desc); + + mdata->ppdu_type = GET_RX_AX_DESC_PPDU_TYPE_8852B(desc); + mdata->ppdu_cnt = GET_RX_AX_DESC_PPDU_CNT_8852B(desc); + mdata->sr_en = GET_RX_AX_DESC_SR_EN_8852B(desc); + mdata->user_id = GET_RX_AX_DESC_USER_ID_8852B(desc); + mdata->rx_rate = GET_RX_AX_DESC_RX_DATARATE_8852B(desc); + mdata->rx_gi_ltf = GET_RX_AX_DESC_RX_GI_LTF_8852B(desc); + mdata->non_srg_ppdu = GET_RX_AX_DESC_NON_SRG_PPDU_8852B(desc); + mdata->inter_ppdu = GET_RX_AX_DESC_INTER_PPDU_8852B(desc); + mdata->bw = GET_RX_AX_DESC_BW_8852B(desc); + + mdata->freerun_cnt = GET_RX_AX_DESC_FREERUN_CNT_8852B(desc); + + mdata->a1_match = GET_RX_AX_DESC_A1_MATCH_8852B(desc); + mdata->sw_dec = GET_RX_AX_DESC_SW_DEC_8852B(desc); + mdata->hw_dec = GET_RX_AX_DESC_HW_DEC_8852B(desc); + mdata->ampdu = GET_RX_AX_DESC_AMPDU_8852B(desc); + mdata->ampdu_end_pkt = GET_RX_AX_DESC_AMPDU_EDN_PKT_8852B(desc); + mdata->amsdu = GET_RX_AX_DESC_AMSDU_8852B(desc); + mdata->amsdu_cut = GET_RX_AX_DESC_AMSDU_CUT_8852B(desc); + mdata->last_msdu = GET_RX_AX_DESC_LAST_MSDU_8852B(desc); + mdata->bypass = GET_RX_AX_DESC_BYPASS_8852B(desc); + mdata->crc32 = GET_RX_AX_DESC_CRC32_8852B(desc); + mdata->icverr = GET_RX_AX_DESC_ICVERR_8852B(desc); + mdata->magic_wake = GET_RX_AX_DESC_MAGIC_WAKE_8852B(desc); + mdata->unicast_wake = GET_RX_AX_DESC_UNICAST_WAKE_8852B(desc); + mdata->pattern_wake = GET_RX_AX_DESC_PATTERN_WAKE_8852B(desc); + mdata->get_ch_info = GET_RX_AX_DESC_CH_INFO_8852B(desc); + mdata->rx_statistics = GET_RX_AX_DESC_STATISTICS_8852B(desc); + + mdata->pattern_idx = GET_RX_AX_DESC_PATTERN_IDX_8852B(desc); + mdata->target_idc = GET_RX_AX_DESC_TARGET_IDC_8852B(desc); + mdata->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD_8852B(desc); + mdata->with_llc = GET_RX_AX_DESC_WITH_LLC_8852B(desc); + + if (mdata->long_rxd == 1) { + mdata->frame_type = GET_RX_AX_DESC_TYPE_8852B(desc); + mdata->mc = GET_RX_AX_DESC_MC_8852B(desc); + mdata->bc = GET_RX_AX_DESC_BC_8852B(desc); + mdata->more_data = GET_RX_AX_DESC_MD_8852B(desc); + mdata->more_frag = GET_RX_AX_DESC_MF_8852B(desc); + mdata->pwr_bit = GET_RX_AX_DESC_PWR_8852B(desc); + mdata->qos = GET_RX_AX_DESC_QOS_8852B(desc); + + mdata->tid = GET_RX_AX_DESC_TID_8852B(desc); + mdata->eosp = GET_RX_AX_DESC_EOSP_8852B(desc); + mdata->htc = GET_RX_AX_DESC_HTC_8852B(desc); + mdata->q_null = GET_RX_AX_DESC_QNULL_8852B(desc); + + mdata->seq = GET_RX_AX_DESC_SEQ_8852B(desc); + mdata->frag_num = GET_RX_AX_DESC_FRAG_8852B(desc); + + mdata->sec_cam_idx = GET_RX_AX_DESC_CAM_IDX_8852B(desc); + mdata->addr_cam = GET_RX_AX_DESC_ADDR_CAM_8852B(desc); + + mdata->addr_cam_vld = GET_RX_AX_DESC_CAM_VLD_8852B(desc); + if (mdata->addr_cam_vld == 0) + mdata->macid = 0xFF; + else + mdata->macid = GET_RX_AX_DESC_MACID_8852B(desc); + + mdata->rx_pl_id = GET_RX_AX_DESC_PL_ID_8852B(desc); + + mdata->addr_fwd_en = GET_RX_AX_DESC_FWD_EN_8852B(desc); + mdata->rx_pl_match = GET_RX_AX_DESC_PL_MATCH_8852B(desc); + + _os_mem_cpy(hal_com->drv_priv, + (void*)&mdata->mac_addr, (void*)(desc + 24), MAC_ALEN); + mdata->sec_type = GET_RX_AX_DESC_SEC_TYPE_8852B(desc); + } + } + + if(mdata->pktlen == 0) + hstatus = RTW_HAL_STATUS_FAILURE; + else + hstatus = RTW_HAL_STATUS_SUCCESS; + + return hstatus; +} + +/** + * hal_parsing_rx_wd_8852b + * description: + * Parsing Rx WiFi Desc by Halmac or SW Manually + * input: + * hal : hal ic adapter + * desc : pointer of the start of rx desc + * output: + * pkt : pointer of the start of pkt; + * pkt_len : the pkt length + * rxwd : rx desc + */ + +enum rtw_hal_status +hal_parsing_rx_wd_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u8 **pkt, u16 *pkt_len, + struct rtw_r_meta_data *mdata) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + u8 halmac_rx = 0; + u8 shift = 0; + u8 *desc = NULL; + u8 desc_l = 0; + + do { + if (NULL == buf) + break; + + if (phl_com->hci_type == RTW_HCI_PCIE) + desc = buf + RX_BD_INFO_SIZE; + else + desc = buf; + + if (!halmac_rx) { + hstatus = _hal_parsing_rx_wd_8852b(hal, desc, mdata); + } else { + /* halmac_ax_ops->parse_rxdesc( */ + /* hm_info->halmac_ax_apter, */ + /* rxpkt_info, */ + /* buf, */ + /* len); */ + } + + + if (RTW_HAL_STATUS_SUCCESS != hstatus) + break; + /* TODO :: Need Double Check*/ + desc_l = mdata->long_rxd ? RX_DESC_L_SIZE_8852B : + RX_DESC_S_SIZE_8852B; + + shift = (u8)(mdata->shift * 2 + mdata->drv_info_size * 8 + desc_l); + + if ((1 == mdata->mac_info_vld) && + (RX_8852B_DESC_PKT_T_PPDU_STATUS != mdata->rpkt_type)) + *pkt = desc + shift + RX_PPDU_MAC_INFO_SIZE_8852B; + else + *pkt = desc + shift; + + *pkt_len = (u16)mdata->pktlen; + + } while (false); + + + //_hal_dump_rxdesc(desc, mdata); + + return hstatus; +} + + +static void +_hal_rx_wlanhdr_check_8852b(void *drvpriv, void *hdr, struct rtw_r_meta_data *mdata) +{ + /*Check Retry BIT*/ + u8 retry = 0; + u16 seq_num = 0; + u8 type = 0; + + type = PHL_GET_80211_HDR_TYPE(hdr); + retry = PHL_GET_80211_HDR_RETRY(hdr); + seq_num = PHL_GET_80211_HDR_SEQUENCE(hdr); + PHL_GET_80211_HDR_ADDRESS2(drvpriv, hdr, mdata->ta); + if (retry) { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[TP Debug] RETRY PKT!!!! seq_num = %d \n", seq_num); + } + if (type == 9) { /* trigger */ + PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_, "rx trigger\n"); + PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_, + "addr cam hit=%d\n", mdata->addr_cam_vld); + PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_, + "addr cam idx=%d\n", mdata->addr_cam); + PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_, + "macid = %d\n", mdata->macid); + } +} + +static void +_hal_rx_sts_8852b(struct hal_info_t *hal, struct rtw_r_meta_data *meta) +{ + struct rtw_hal_com_t *hal_com = hal->hal_com; + struct rtw_trx_stat *trx_stat = &hal_com->trx_stat; + + /* todo: shall drop rx in PHL if hw err */ + if (meta->crc32 || meta->icverr) + trx_stat->rx_err_cnt++; + else + trx_stat->rx_ok_cnt++; +} + +enum rtw_hal_status +hal_handle_rx_buffer_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u32 buf_len, + struct rtw_phl_rx_pkt *phl_rx) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + void *drv = hal_to_drvpriv(hal); + struct rtw_recv_pkt *r = &phl_rx->r; + struct rtw_pkt_buf_list *pkt = &r->pkt_list[0]; + struct rtw_r_meta_data *mdata = &r->mdata; +#ifdef CONFIG_PHL_TEST_SUITE + struct test_bp_info bp_info; +#endif + hstatus = hal_parsing_rx_wd_8852b(phl_com, hal, buf, + &pkt->vir_addr, &pkt->length, mdata); + + if (RTW_HAL_STATUS_SUCCESS != hstatus) + return hstatus; + if( (pkt->vir_addr + pkt->length) > (buf + buf_len) ) + return RTW_HAL_STATUS_FAILURE; + + /* hana_todo */ + r->pkt_cnt = 1; + + switch (mdata->rpkt_type) { + case RX_8852B_DESC_PKT_T_WIFI : + { + phl_rx->type = RTW_RX_TYPE_WIFI; + _hal_rx_wlanhdr_check_8852b(drv, pkt->vir_addr, mdata); + _hal_rx_sts_8852b(hal, mdata); + hal_rx_ppdu_sts_normal_data(phl_com, pkt->vir_addr, mdata); + } + break; + case RX_8852B_DESC_PKT_T_TX_PD_RELEASE_HOST : + { + phl_rx->type = RTW_RX_TYPE_TX_WP_RELEASE_HOST; + } + break; + case RX_8852B_DESC_PKT_T_PPDU_STATUS : + { + struct hal_ppdu_sts ppdu_sts = {0}; + u8 is_su = 1; + + phl_rx->type = RTW_RX_TYPE_PPDU_STATUS; + PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, + "==> RX_8852B_DESC_PKT_T_PPDU_STATUS :band %d ; ppdu_cnt %d ; freerun_cnt %d \n", + mdata->bb_sel, mdata->ppdu_cnt, mdata->freerun_cnt); + rtw_hal_mac_ax_parse_ppdu_sts(hal, mdata->mac_info_vld, + pkt->vir_addr, mdata->pktlen, + (void *)&ppdu_sts, + (void *)mdata); + if (ppdu_sts.rx_cnt_size != 0) { + _hal_trx_8852b_dump_rxcnt(&ppdu_sts); + } + if (ppdu_sts.phy_st_size != 0) { + if((mdata->ppdu_type == RX_8852B_DESC_PPDU_T_VHT_MU)|| + (mdata->ppdu_type == RX_8852B_DESC_PPDU_T_HE_MU)|| + (mdata->ppdu_type == RX_8852B_DESC_PPDU_T_HE_TB)) { + is_su = 0; + } + rtw_hal_bb_parse_phy_sts(hal, (void *)&ppdu_sts, + phl_rx, is_su); + + hal_rx_ppdu_sts(phl_com, phl_rx, &ppdu_sts); +#ifdef CONFIG_PHL_TEST_SUITE + bp_info.type = BP_INFO_TYPE_MP_RX_PHYSTS; + bp_info.ptr = (void *)(ppdu_sts.phy_st_ptr); + bp_info.len = ppdu_sts.phy_st_size; + rtw_phl_test_setup_bp(phl_com, &bp_info, TEST_SUB_MODULE_MP); +#endif + } + } + break; + case RX_8852B_DESC_PKT_T_DFS_RPT : + { + #ifdef CONFIG_PHL_DFS + struct mac_ax_dfs_rpt dfs_rpt = {0}; + struct hal_dfs_rpt hal_dfs = {0}; + + phl_rx->type = RTW_RX_TYPE_DFS_RPT; + + rtw_hal_mac_parse_dfs(hal,pkt->vir_addr, mdata->pktlen, &dfs_rpt); + #ifdef DBG_PHL_DFS + PHL_INFO("RX DFS RPT, pkt_len:%d\n", mdata->pktlen); + PHL_INFO("[DFS] mac-hdr dfs_num:%d\n", dfs_rpt.dfs_num); + PHL_INFO("[DFS] mac-hdr drop_num:%d\n", dfs_rpt.drop_num); + PHL_INFO("[DFS] mac-hdr max_cont_drop:%d\n", dfs_rpt.max_cont_drop); + PHL_INFO("[DFS] mac-hdr total_drop:%d\n", dfs_rpt.total_drop); + #endif + hal_dfs.dfs_ptr = dfs_rpt.dfs_ptr; + hal_dfs.dfs_num = dfs_rpt.dfs_num; + hal_dfs.phy_idx = 0; + + if (rtw_hal_bb_radar_detect(hal, &hal_dfs)) + PHL_INFO("[DFS] radar detected\n"); + + #endif + } + break; + case RX_8852B_DESC_PKT_T_CHANNEL_INFO : + { + #ifdef CONFIG_PHL_CHANNEL_INFO + enum rtw_hal_status status= RTW_HAL_STATUS_SUCCESS; + u8* buf_addr; + struct ch_rpt_hdr_info ch_hdr_rpt = {0}; + struct phy_info_rpt phy_rpt = {0}; + struct ch_info_drv_rpt drv_rpt = {0}; + u32 idle_num = CHAN_INFO_PKT_TOTAL; + struct chan_info_t *chan_info_old = NULL; + + phl_rx->type = RTW_RX_TYPE_CHANNEL_INFO; + /* Channel Report */ + /* TODO: need to discuss the final csi header format further.*/ + idle_num = rtw_phl_get_chaninfo_idle_number(drv, phl_com); + + if (idle_num == CHAN_INFO_PKT_TOTAL) + phl_com->chan_info = rtw_phl_query_idle_chaninfo(drv, phl_com); + + if (phl_com->chan_info == NULL) { + /*hstatus = RTW_HAL_STATUS_SUCCESS is expected*/ + PHL_INFO("channel info packet not avaialbe due to no pakcet handle\n"); + break; + } + buf_addr = phl_com->chan_info->chan_info_buffer; + status = rtw_hal_bb_ch_info_parsing(hal, pkt->vir_addr, + mdata->pktlen, + buf_addr + phl_com->chan_info->length, + &ch_hdr_rpt, &phy_rpt, &drv_rpt); + + if (status == RTW_HAL_STATUS_FAILURE) + phl_com->chan_info->length = 0; + else + phl_com->chan_info->length += drv_rpt.raw_data_len; + /* store phy info if seg#0 is success*/ + if (drv_rpt.seg_idx_curr == 0 && status != RTW_HAL_STATUS_FAILURE) + _hal_fill_csi_header_phy_info(hal, &(phl_com->chan_info->csi_header), + &ch_hdr_rpt, &phy_rpt); + if (status == RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG) { + /* Fill remain csi header to buffer */ + _hal_fill_csi_header_remain(hal, + &(phl_com->chan_info->csi_header), mdata); + /* push compelete channel info resourecs to busy queue */ + chan_info_old = rtw_phl_recycle_busy_chaninfo(drv, phl_com, phl_com->chan_info); + if (chan_info_old) + rtw_phl_enqueue_idle_chaninfo(drv, phl_com, chan_info_old); + phl_com->chan_info = rtw_phl_query_idle_chaninfo(drv, phl_com); + if(phl_com->chan_info == NULL) + PHL_INFO("channel info packet not avaialbe after recycle\n"); + } + #else + phl_rx->type = RTW_RX_TYPE_CHANNEL_INFO; + #endif /* CONFIG_PHL_CHANNEL_INFO */ + } + break; + case RX_8852B_DESC_PKT_T_F2P_TX_CMD_RPT : + { + /* DL MU Report ; UL OFDMA Trigger Report */ + } + break; + case RX_8852B_DESC_PKT_T_C2H : + { + struct rtw_c2h_info c = {0}; + + phl_rx->type = RTW_RX_TYPE_C2H; + rtw_hal_mac_parse_c2h(hal, pkt->vir_addr, mdata->pktlen, (void *)&c); + + hal_c2h_post_process(phl_com, hal, (void *)&c); + } + break; + case RX_8852B_DESC_PKT_T_TX_RPT: + { + u8 expected_pkt_num = 0; + u8 diff_pkt_num = 0; + u8 tx_pkt_num = 0; + phl_rx->type = RTW_RX_TYPE_TX_RPT; + /* + * Write CR 0xC660[3:2] = 0, Dump TXRPT to driver + * TXRPT offset12[7:0]: PTCL expected_pkt_num + * TXRPT offset16[27:24]: diff_pkt_num + */ + expected_pkt_num = pkt->vir_addr[12]; + diff_pkt_num = (pkt->vir_addr[19] & 0xF); + tx_pkt_num = expected_pkt_num - diff_pkt_num; + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, + "expected_pkt_num: %d, diff_pkt_num: %d, tx_pkt_num: %d\n", + expected_pkt_num, diff_pkt_num, tx_pkt_num); + } + break; + + default: + break; + } + + return hstatus; +} + diff --git a/phl/hal_g6/rtl8852b/hal_trx_8852b.h b/phl/hal_g6/rtl8852b/hal_trx_8852b.h new file mode 100644 index 0000000..881affd --- /dev/null +++ b/phl/hal_g6/rtl8852b/hal_trx_8852b.h @@ -0,0 +1,172 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_TRX_8852B_H_ +#define _HAL_TRX_8852B_H_ + +/* wifi packet(RXD.RPKT_TYPE = 0x0) = 32 bytes, otherwise 16 bytes */ +#define RX_DESC_L_SIZE_8852B 32 +#define RX_DESC_S_SIZE_8852B 16 + +#define RX_BD_INFO_SIZE 4 + +#define RX_PPDU_MAC_INFO_SIZE_8852B 4 + +#define ACH0_QUEUE_IDX_8852B 0x0 +#define ACH1_QUEUE_IDX_8852B 0x1 +#define ACH2_QUEUE_IDX_8852B 0x2 +#define ACH3_QUEUE_IDX_8852B 0x3 +#define ACH4_QUEUE_IDX_8852B 0x4 +#define ACH5_QUEUE_IDX_8852B 0x5 +#define ACH6_QUEUE_IDX_8852B 0x6 +#define ACH7_QUEUE_IDX_8852B 0x7 +#define MGQ_B0_QUEUE_IDX_8852B 0x8 +#define HIQ_B0_QUEUE_IDX_8852B 0x9 +#define FWCMD_QUEUE_IDX_8852B 0xc + +/* AX RX DESC */ +/* DWORD 0 ; Offset 00h */ +#define GET_RX_AX_DESC_PKT_LEN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) +#define GET_RX_AX_DESC_SHIFT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 2) +#define GET_RX_AX_DESC_HDR_IV_L_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 6) +#define GET_RX_AX_DESC_BB_SEL_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 22, 1) +#define GET_RX_AX_DESC_MAC_INFO_VLD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_AX_DESC_RPKT_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 4) +#define GET_RX_AX_DESC_DRV_INFO_SIZE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 3) +#define GET_RX_AX_DESC_LONG_RXD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) + +/* DWORD 1 ; Offset 04h */ +#define GET_RX_AX_DESC_PPDU_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 4) +#define GET_RX_AX_DESC_PPDU_CNT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 4, 3) +#define GET_RX_AX_DESC_SR_EN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1) +#define GET_RX_AX_DESC_USER_ID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 8) +#define GET_RX_AX_DESC_RX_DATARATE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 9) +#define GET_RX_AX_DESC_RX_GI_LTF_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 3) +#define GET_RX_AX_DESC_NON_SRG_PPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 1) +#define GET_RX_AX_DESC_INTER_PPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 29, 1) +#define GET_RX_AX_DESC_BW_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 2) + +/* DWORD 2 ; Offset 08h */ +#define GET_RX_AX_DESC_FREERUN_CNT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 32) + +/* DWORD 3 ; Offset 0ch */ +#define GET_RX_AX_DESC_A1_MATCH_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 1) +#define GET_RX_AX_DESC_SW_DEC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 1, 1) +#define GET_RX_AX_DESC_HW_DEC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 2, 1) +#define GET_RX_AX_DESC_AMPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 3, 1) +#define GET_RX_AX_DESC_AMPDU_EDN_PKT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 4, 1) +#define GET_RX_AX_DESC_AMSDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 5, 1) +#define GET_RX_AX_DESC_AMSDU_CUT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 6, 1) +#define GET_RX_AX_DESC_LAST_MSDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 1) +#define GET_RX_AX_DESC_BYPASS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 8, 1) +#define GET_RX_AX_DESC_CRC32_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 9, 1) +#define GET_RX_AX_DESC_ICVERR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) +#define GET_RX_AX_DESC_MAGIC_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) +#define GET_RX_AX_DESC_UNICAST_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 1) +#define GET_RX_AX_DESC_PATTERN_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 13, 1) + +#define GET_RX_AX_DESC_CH_INFO_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 14, 1) +#define GET_RX_AX_DESC_STATISTICS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 15, 1) +#define GET_RX_AX_DESC_PATTERN_IDX_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 5) +#define GET_RX_AX_DESC_TARGET_IDC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 21, 3) +#define GET_RX_AX_DESC_CHKSUM_OFFLOAD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 24, 1) +#define GET_RX_AX_DESC_WITH_LLC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 25, 1) + + +/* DWORD 4 ; Offset 10h */ +#define GET_RX_AX_DESC_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 2) +#define GET_RX_AX_DESC_MC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 2, 1) +#define GET_RX_AX_DESC_BC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 3, 1) +#define GET_RX_AX_DESC_MD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 4, 1) +#define GET_RX_AX_DESC_MF_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 5, 1) +#define GET_RX_AX_DESC_PWR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 6, 1) +#define GET_RX_AX_DESC_QOS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 7, 1) +#define GET_RX_AX_DESC_TID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 4) +#define GET_RX_AX_DESC_EOSP_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 12, 1) +#define GET_RX_AX_DESC_HTC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 13, 1) +#define GET_RX_AX_DESC_QNULL_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 14, 1) + +#define GET_RX_AX_DESC_SEQ_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 12) +#define GET_RX_AX_DESC_FRAG_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 28, 4) + +/* DWORD 5 ; Offset 14h */ +#define GET_RX_AX_DESC_CAM_IDX_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 8) +#define GET_RX_AX_DESC_ADDR_CAM_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 8, 8) +#define GET_RX_AX_DESC_MACID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 16, 8) +#define GET_RX_AX_DESC_PL_ID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 24, 4) +#define GET_RX_AX_DESC_CAM_VLD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 28, 1) +#define GET_RX_AX_DESC_FWD_EN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 29, 1) +#define GET_RX_AX_DESC_PL_MATCH_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 30, 1) + +/* DWORD 6 ; Offset 18h */ +//#define GET_RX_AX_DESC_MAC_ADDR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+24, 0, 32) + +/* DWORD 7 ; Offset 1ch */ +//#define GET_RX_AX_DESC_MAC_ADDR_H_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+28, 0, 16) +#define GET_RX_AX_DESC_SEC_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+28, 17, 4) + + +/* +0000: WIFI packet +0001: PPDU status +0010: channel info +0011: BB scope mode +0100: F2P TX CMD report +0101: SS2FW report +0110: TX report +0111: TX payload release to host +1000: DFS report +1001: TX payload release to WLCPU +1010: C2H packet */ +#define RX_8852B_DESC_PKT_T_WIFI 0 +#define RX_8852B_DESC_PKT_T_PPDU_STATUS 1 +#define RX_8852B_DESC_PKT_T_CHANNEL_INFO 2 +#define RX_8852B_DESC_PKT_T_BB_SCOPE 3 +#define RX_8852B_DESC_PKT_T_F2P_TX_CMD_RPT 4 +#define RX_8852B_DESC_PKT_T_SS2FW_RPT 5 +#define RX_8852B_DESC_PKT_T_TX_RPT 6 +#define RX_8852B_DESC_PKT_T_TX_PD_RELEASE_HOST 7 +#define RX_8852B_DESC_PKT_T_DFS_RPT 8 +#define RX_8852B_DESC_PKT_T_TX_PD_RELEASE_WLCPU 9 +#define RX_8852B_DESC_PKT_T_C2H 10 + + +#define RX_8852B_DESC_PPDU_T_LCCK 0 +#define RX_8852B_DESC_PPDU_T_SCCK 1 +#define RX_8852B_DESC_PPDU_T_OFDM 2 +#define RX_8852B_DESC_PPDU_T_HT 3 +#define RX_8852B_DESC_PPDU_T_HTGF 4 +#define RX_8852B_DESC_PPDU_T_VHT_SU 5 +#define RX_8852B_DESC_PPDU_T_VHT_MU 6 +#define RX_8852B_DESC_PPDU_T_HE_SU 7 +#define RX_8852B_DESC_PPDU_T_HE_ERSU 8 +#define RX_8852B_DESC_PPDU_T_HE_MU 9 +#define RX_8852B_DESC_PPDU_T_HE_TB 10 +#define RX_8852B_DESC_PPDU_T_UNKNOWN 15 + + +struct rx_ppdu_status{ + u32 mac_info_length; + u32 phy_info_length; + //struct mac_info macinfo; + //struct phy_info phyinfo; +}; + +enum rtw_hal_status +hal_handle_rx_buffer_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + u8 *buf, u32 buf_len, + struct rtw_phl_rx_pkt *phl_rx); + +#endif /*_HAL_TRX_8852B_H_*/ diff --git a/phl/hal_g6/rtl8852b/rtl8852b.h b/phl/hal_g6/rtl8852b/rtl8852b.h new file mode 100644 index 0000000..cc1063a --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8852B_H_ +#define _RTL8852B_H_ +#include "../hal_headers.h" + +/*to communicate with upper-hal*/ +#ifdef CONFIG_PCI_HCI +void hal_set_ops_8852be(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +u32 hal_hook_trx_ops_8852be(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info); +#endif + +#ifdef CONFIG_USB_HCI +void hal_set_ops_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +u32 hal_hook_trx_ops_8852bu(struct hal_info_t *hal_info); + +#endif + +#ifdef CONFIG_SDIO_HCI +void hal_set_ops_8852bs(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +u32 hal_hook_trx_ops_8852bs(struct hal_info_t *hal_info); + +#endif + +#endif /* _RTL8852B_H_ */ diff --git a/phl/hal_g6/rtl8852b/rtl8852b.mk b/phl/hal_g6/rtl8852b/rtl8852b.mk new file mode 100644 index 0000000..783282f --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b.mk @@ -0,0 +1,50 @@ +EXTRA_CFLAGS += -DCONFIG_RTL8852B +IC_NAME := rtl8852b + +ifeq ($(CONFIG_MP_INCLUDED), y) +### 8852B Default Enable VHT MP HW TX MODE ### +#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE +#CONFIG_MP_VHT_HW_TX_MODE = y +endif + +ifeq ($(CONFIG_PHL_ARCH), y) +HAL = phl/hal_g6 +else +HAL = hal_g6 +endif + +ifeq ($(CONFIG_USB_HCI), y) + FILE_NAME = rtl8852bu +endif +ifeq ($(CONFIG_PCI_HCI), y) + FILE_NAME = rtl8852be +endif +ifeq ($(CONFIG_SDIO_HCI), y) + FILE_NAME = rtl8852bs +endif + + +_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(IC_NAME)_halinit.o \ + $(HAL)/$(IC_NAME)/$(IC_NAME)_mac.o \ + $(HAL)/$(IC_NAME)/$(IC_NAME)_cmd.o \ + $(HAL)/$(IC_NAME)/$(IC_NAME)_phy.o \ + $(HAL)/$(IC_NAME)/$(IC_NAME)_ops.o \ + $(HAL)/$(IC_NAME)/hal_trx_8852b.o + +_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_halinit.o \ + $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_halmac.o \ + $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_io.o \ + $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_led.o \ + $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_ops.o + +#ifeq ($(CONFIG_SDIO_HCI), y) +#_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852bs.o +#endif + +ifeq ($(CONFIG_USB_HCI), y) +_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852bu.o +endif + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852be.o +endif \ No newline at end of file diff --git a/phl/hal_g6/rtl8852b/rtl8852b_cmd.c b/phl/hal_g6/rtl8852b/rtl8852b_cmd.c new file mode 100644 index 0000000..2915563 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_cmd.c @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_CMD_C_ +#include "../hal_headers.h" + + diff --git a/phl/hal_g6/rtl8852b/rtl8852b_hal.h b/phl/hal_g6/rtl8852b/rtl8852b_hal.h new file mode 100644 index 0000000..9c6bb7a --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_hal.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8852B_HAL_H_ +#define _RTL8852B_HAL_H_ +#include "../hal_headers.h" + +/*usage under rtl8852b folder*/ +#include "rtl8852b_spec.h" +#include "hal_trx_8852b.h" + +#ifdef CONFIG_PCI_HCI +#include "pci/rtl8852be_hal.h" +#endif + +#ifdef CONFIG_USB_HCI +#include "usb/rtl8852bu_hal.h" +#endif + +#ifdef CONFIG_SDIO_HCI +#include "sdio/rtl8852bs_hal.h" +#endif + +enum hw_stype_8852b { + EFUSE_HW_STYPE_NONE_8852B = 0, + EFUSE_HW_STYPE_VF1_CG_8852B = 0xe, + EFUSE_HW_STYPE_GENERAL_8852B = 0xf +}; + +/* rtl8852b_halinit.c */ +void init_hal_spec_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +enum rtw_hal_status hal_cfg_fw_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + char *ic_name, + enum rtw_fw_type fw_type); + +/* rtl8852b_ops.c */ +void hal_set_ops_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +/*void hal_set_trx_ops_8852b(struct hal_info_t *hal);*/ + +void init_default_value_8852b(struct hal_info_t *hal); +enum rtw_hal_status hal_get_efuse_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + struct hal_init_info_t *init_info); +enum rtw_hal_status hal_start_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + struct hal_init_info_t *init_info); +enum rtw_hal_status hal_stop_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + +#ifdef CONFIG_WOWLAN +enum rtw_hal_status +hal_wow_init_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta, + struct hal_init_info_t *init_info); +enum rtw_hal_status +hal_wow_deinit_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta, + struct hal_init_info_t *init_info); +#endif /* CONFIG_WOWLAN */ + +#ifdef RTW_PHL_BCN +enum rtw_hal_status hal_config_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); +enum rtw_hal_status hal_update_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); +#endif + +enum rtw_hal_status +hal_mp_init_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info); +enum rtw_hal_status +hal_mp_deinit_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info); + + +#endif /* _RTL8852B_HAL_H_ */ diff --git a/phl/hal_g6/rtl8852b/rtl8852b_halinit.c b/phl/hal_g6/rtl8852b/rtl8852b_halinit.c new file mode 100644 index 0000000..ace7fe7 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_halinit.c @@ -0,0 +1,668 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_HALINIT_C_ +#include "../hal_headers.h" +#include "../hal_api.h" +#include "rtl8852b_hal.h" + +void init_hal_spec_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com); + struct rtw_hal_com_t *hal_com = hal->hal_com; + struct protocol_cap_t *hw_proto_cap = hal_com->proto_hw_cap; + + hal_spec->ic_name = "rtl8852b"; + hal_spec->macid_num = hal_mac_get_macid_num(hal); + /* hal_spec->sec_cam_ent_num follow halmac setting */ + hal_spec->sec_cap = SEC_CAP_CHK_BMC; + + hal_spec->rfpath_num_2g = 2; + hal_spec->rfpath_num_5g = 2; + hal_spec->rf_reg_path_num = 2; + hal_com->rfpath_rx_num = 2; + hal_com->rfpath_tx_num = 2; + hal_com->phy_hw_cap[0].rx_num = 2; + hal_com->phy_hw_cap[0].tx_num = 2; + hal_com->phy_hw_cap[1].rx_num = 2; + hal_com->phy_hw_cap[1].tx_num = 2; + hal_com->phy_hw_cap[0].hw_rts_time_th = 0; + hal_com->phy_hw_cap[1].hw_rts_time_th = 0; + hal_com->phy_hw_cap[0].hw_rts_len_th = 0; + hal_com->phy_hw_cap[1].hw_rts_len_th = 0; + hal_spec->max_tx_cnt = 2; + + hal_spec->tx_nss_num = 2; + hal_spec->rx_nss_num = 2; + hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G | BAND_CAP_6G; + hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M; + hal_spec->port_num = 5; + hal_spec->wmm_num = 2; + + hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | + PROTO_CAP_11AC | PROTO_CAP_11AX; + + hal_spec->wl_func = 0 + | WL_FUNC_P2P + | WL_FUNC_MIRACAST + | WL_FUNC_TDLS + ; + + hal_spec->max_csi_buf_su_nr = 2; + hal_spec->max_csi_buf_mu_nr = 6; + hal_spec->max_bf_ent_nr = 16; + hal_spec->max_su_sta_nr = 16; + hal_spec->max_mu_sta_nr = 6; +#ifdef RTW_WKARD_PHY_CAP + /* HE */ + hw_proto_cap[0].he_su_bfme = 1; + hw_proto_cap[0].he_su_bfmr = 1; + hw_proto_cap[0].he_mu_bfme = 1; + hw_proto_cap[0].he_mu_bfmr = 1; + + hw_proto_cap[1].he_su_bfme = 1; + hw_proto_cap[1].he_su_bfmr = 1; + hw_proto_cap[1].he_mu_bfme = 1; + hw_proto_cap[1].he_mu_bfmr = 0; + + hw_proto_cap[0].trig_cqi_fb = 1; + hw_proto_cap[0].non_trig_cqi_fb = 1; + hw_proto_cap[1].trig_cqi_fb = 1; + hw_proto_cap[1].non_trig_cqi_fb = 1; + + /* VHT */ + hw_proto_cap[0].vht_su_bfmr = 1; + hw_proto_cap[0].vht_su_bfme = 1; + hw_proto_cap[0].vht_mu_bfmr = 1; + hw_proto_cap[0].vht_mu_bfme = 1; + + hw_proto_cap[1].vht_su_bfmr = 1; + hw_proto_cap[1].vht_su_bfme = 1; + hw_proto_cap[1].vht_mu_bfmr = 0; + hw_proto_cap[1].vht_mu_bfme = 1; + + /* HT */ + hw_proto_cap[0].ht_su_bfmr = 1; + hw_proto_cap[0].ht_su_bfme = 1; + + hw_proto_cap[1].ht_su_bfmr = 1; + hw_proto_cap[1].ht_su_bfme = 1; + + /* STBC Tx*/ + hw_proto_cap[0].stbc_tx = 1; /* Revmoe later */ + hw_proto_cap[1].stbc_tx = 1; /* Revmoe later */ + hw_proto_cap[0].stbc_ht_tx = 1; + hw_proto_cap[1].stbc_ht_tx = 1; + hw_proto_cap[0].stbc_vht_tx = 1; + hw_proto_cap[1].stbc_vht_tx = 1; + hw_proto_cap[0].stbc_he_tx = 1; + hw_proto_cap[1].stbc_he_tx = 1; + hw_proto_cap[0].stbc_tx_greater_80mhz = 0; + hw_proto_cap[1].stbc_tx_greater_80mhz = 0; + + /* STBC Rx*/ + hw_proto_cap[0].stbc_ht_rx = 1; + hw_proto_cap[1].stbc_ht_rx = 1; + hw_proto_cap[0].stbc_vht_rx = 1; + hw_proto_cap[1].stbc_vht_rx = 1; + hw_proto_cap[0].stbc_he_rx = 1; + hw_proto_cap[1].stbc_he_rx = 1; + hw_proto_cap[0].stbc_rx_greater_80mhz = 0; + hw_proto_cap[1].stbc_rx_greater_80mhz = 0; +#endif + + /*get mac capability*/ + phl_com->dev_cap.hw_sup_flags = HW_SUP_AMSDU | + HW_SUP_TCP_TX_CHKSUM | + HW_SUP_TCP_RX_CHKSUM | + HW_SUP_TXPKT_CONVR; + + phl_com->dev_cap.hw_sup_flags |= HW_SUP_OFDMA | HW_SUP_CHAN_INFO; + phl_com->dev_cap.hw_sup_flags |= HW_SUP_TSSI | HW_SUP_TANK_K; + + +#ifdef RTW_WKARD_LAMODE + hal_com->dev_hw_cap.la_mode = true;/*TODO : get info from halbb*/ +#endif + +#ifdef CONFIG_DBCC_SUPPORT + if (phl_com->dev_cap.hw_sup_flags & HW_SUP_DBCC) + hal_com->dev_hw_cap.dbcc_sup = true;/*get info from efuse*/ +#endif + hal_com->dev_hw_cap.hw_hdr_conv = true; + + hal_com->dev_hw_cap.sta_ulru = RTW_HW_CAP_ULRU_ENABLE; +#ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA + hal_com->dev_hw_cap.sta_ulru_2g40mhz = RTW_HW_CAP_ULRU_DISABLE; +#endif + hal_com->dev_hw_cap.tx_mu_ru = false; + +#ifdef CONFIG_MCC_SUPPORT + hal_com->dev_hw_cap.mcc_sup = true; +#endif /* CONFIG_MCC_SUPPORT */ + +#ifdef CONFIG_PHL_TWT + /* wait for fw support sta twt */ + hal_com->dev_hw_cap.twt_sup = 0; +#endif /* CONFIG_PHL_TWT */ + + hal_com->dev_hw_cap.ps_cap.ips_cap = PS_CAP_PWR_OFF; + hal_com->dev_hw_cap.ps_cap.ips_wow_cap = 0; + hal_com->dev_hw_cap.ps_cap.lps_cap = + PS_CAP_PWRON | PS_CAP_RF_OFF | PS_CAP_CLK_GATED | PS_CAP_PWR_GATED; + hal_com->dev_hw_cap.ps_cap.lps_wow_cap = + PS_CAP_PWRON | PS_CAP_RF_OFF | PS_CAP_CLK_GATED | PS_CAP_PWR_GATED; + + hal_com->dev_hw_cap.hw_stype_cap = EFUSE_HW_STYPE_NONE_8852B; + hal_com->dev_hw_cap.wl_func_cap = EFUSE_WL_FUNC_NONE; + hal_com->dev_hw_cap.rpq_agg_num = 0; +} + + +void init_default_value_8852b(struct hal_info_t *hal) +{ +} + +u32 _hal_cfg_rom_fw_8852b(enum rtw_fw_type fw_type, struct rtw_fw_info_t *fw_info, + char *ic_name) +{ + char *hal_phy_folder = FW_FILE_CONFIG_PATH; + char *filename_postfix = ""; + + switch (fw_type) { + case RTW_FW_NIC: + filename_postfix = FW_FILE_NIC_POSTFIX; + break; + case RTW_FW_WOWLAN: + filename_postfix = FW_FILE_WOWLAN_POSTFIX; + break; + case RTW_FW_SPIC: + filename_postfix = FW_FILE_SPIC_POSTFIX; + break; + case RTW_FW_AP: + filename_postfix = FW_FILE_AP_POSTFIX; + break; + default: + break; + } + + _os_snprintf(fw_info->rom_path, MAX_PATH_LEN, "%s%s%s%s", hal_phy_folder, + ic_name, _os_path_sep, "rtl8852bfw_rom.bin"); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %s\n", __func__, fw_info->rom_path); + + fw_info->rom_size = _os_read_file(fw_info->rom_path, + fw_info->rom_buff, + RTW_MAX_FW_SIZE); + if (!fw_info->rom_size) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +u32 _hal_cfg_intnal_fw_8852b(struct rtw_phl_com_t *phl_com,enum rtw_fw_type fw_type,struct rtw_fw_info_t *fw_info) +{ + /* any related to fw from header can be defined here */ + return RTW_HAL_STATUS_SUCCESS; +} + +static u32 _hal_read_fw_8852b(enum rtw_fw_type fw_type, + u8 *tgt_buf, u32 *tgt_buf_size, char *ic_name) +{ + char *hal_phy_folder = FW_FILE_CONFIG_PATH; + char *filename_postfix = ""; + char path[256] = {0}; + + if (tgt_buf == NULL) + return RTW_HAL_STATUS_FAILURE; + + switch (fw_type) { + case RTW_FW_NIC: + filename_postfix = FW_FILE_NIC_POSTFIX; + break; + case RTW_FW_WOWLAN: + filename_postfix = FW_FILE_WOWLAN_POSTFIX; + break; + case RTW_FW_SPIC: + filename_postfix = FW_FILE_SPIC_POSTFIX; + break; + case RTW_FW_AP: + filename_postfix = FW_FILE_AP_POSTFIX; + break; + default: + return RTW_HAL_STATUS_FAILURE; + } + + _os_snprintf(path, MAX_PATH_LEN, "%s%s%s%s%s%s", hal_phy_folder, + ic_name, _os_path_sep, "rtl8852bfw", filename_postfix, ".bin"); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %s\n", __func__, path); + + if (0 == *tgt_buf_size) { + *tgt_buf_size = _os_read_file(path, tgt_buf, RTW_MAX_FW_SIZE); + /* reading fw file failed */ + if (0 == *tgt_buf_size) + return RTW_HAL_STATUS_FAILURE; + } + + return RTW_HAL_STATUS_SUCCESS; +} + +static u32 _hal_cfg_extnal_fw_8852b(struct rtw_phl_com_t *phl_com, + enum rtw_fw_type fw_type, struct rtw_fw_info_t *fw_info, char *ic_name) +{ + void *d = phlcom_to_drvpriv(phl_com); + u8 *tgt_buf = NULL; + u32 tgt_buf_size = 0; + + switch (fw_type) { + case RTW_FW_NIC: + _hal_read_fw_8852b(RTW_FW_NIC, fw_info->buf, + &fw_info->buf_size, ic_name); + /* preload wowlan fw */ + _hal_read_fw_8852b(RTW_FW_WOWLAN, fw_info->wow_buf, + &fw_info->wow_buf_size, ic_name); + /* target is still NIC */ + tgt_buf = fw_info->buf; + tgt_buf_size = fw_info->buf_size; + break; + case RTW_FW_WOWLAN: + _hal_read_fw_8852b(RTW_FW_WOWLAN, fw_info->wow_buf, + &fw_info->wow_buf_size, ic_name); + tgt_buf = fw_info->wow_buf; + tgt_buf_size = fw_info->wow_buf_size; + break; + case RTW_FW_SPIC: + _hal_read_fw_8852b(RTW_FW_SPIC, fw_info->buf, + &fw_info->buf_size, ic_name); + tgt_buf = fw_info->buf; + tgt_buf_size = fw_info->buf_size; + break; + case RTW_FW_AP: + _hal_read_fw_8852b(RTW_FW_AP, fw_info->buf, + &fw_info->buf_size, ic_name); + tgt_buf = fw_info->buf; + tgt_buf_size = fw_info->buf_size; + break; + default: + return RTW_HAL_STATUS_FAILURE; + } + + /* fw has been downloaded */ + if (tgt_buf && (0 != tgt_buf_size)) { + _os_mem_cpy(d, fw_info->ram_buff, tgt_buf, + tgt_buf_size); + fw_info->ram_size = tgt_buf_size; + return RTW_HAL_STATUS_SUCCESS; + } else { + fw_info->ram_size = 0; + return _hal_read_fw_8852b(fw_type, fw_info->ram_buff, + &fw_info->ram_size, ic_name); + } + +} + +enum rtw_hal_status hal_cfg_fw_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + char *ic_name, + enum rtw_fw_type fw_type) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct rtw_fw_info_t *fw_info = &phl_com->fw_info; + struct rtw_fw_cap_t *fw_cap = &phl_com->dev_cap.fw_cap; + + FUNCIN(); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : fw_src %d.\n", __func__, + fw_cap->fw_src); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : dlram_en %d.\n", __func__, + fw_cap->dlram_en); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : dlrom_en %d.\n", __func__, + fw_cap->dlrom_en); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : fw_type %d.\n", __func__, + fw_type); + + fw_info->fw_en = false; + + if (!fw_cap->dlram_en) + return hstatus; + + /* Should handle fw src from header */ + if (fw_cap->dlrom_en) { + if (RTW_HAL_STATUS_SUCCESS !=_hal_cfg_rom_fw_8852b(fw_type, fw_info, + ic_name)) + goto init_fw_fail; + } + + /* RAM */ + if (fw_cap->fw_src == RTW_FW_SRC_EXTNAL) { + fw_info->fw_src = RTW_FW_SRC_EXTNAL; + if (RTW_HAL_STATUS_SUCCESS != _hal_cfg_extnal_fw_8852b(phl_com, fw_type, + fw_info, ic_name)) + goto init_fw_fail; + } else if (fw_cap->fw_src == RTW_FW_SRC_INTNAL) { + fw_info->fw_src = RTW_FW_SRC_INTNAL; + if (RTW_HAL_STATUS_SUCCESS != _hal_cfg_intnal_fw_8852b(phl_com, fw_type, + fw_info)) + goto init_fw_fail; + } else { + goto init_fw_fail; + } + + fw_info->fw_type = fw_type; + fw_info->fw_en = true; + fw_info->dlram_en = fw_cap->dlram_en; + fw_info->dlrom_en = fw_cap->dlrom_en; + + /* fw_en, dlram_en, dlrom_en, ram_buff, ram_size, rom_buff, rom_size are ready here. */ + + hstatus = RTW_HAL_STATUS_SUCCESS; + +init_fw_fail: + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s : fw_en %d.\n", __func__, fw_info->fw_en); + return hstatus; +} + +enum rtw_hal_status hal_get_efuse_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + struct hal_init_info_t *init_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + FUNCIN(); + + hal_status = rtw_hal_mac_hal_fast_init(phl_com, hal, init_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_fast_init_fail; + + rtw_hal_efuse_process(hal, init_info->ic_name); + + hal_status = rtw_hal_mac_power_switch(phl_com, hal, 0); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_power_off_fail; + + FUNCOUT(); + + return RTW_HAL_STATUS_SUCCESS; + +hal_power_off_fail: +hal_fast_init_fail: + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "==> %s : hal get efuse fail\n", __func__); + return hal_status; +} + +enum rtw_hal_status hal_start_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, + struct hal_init_info_t *init_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct phy_cap_t *phy_cap = phl_com->phy_cap; + u8 val = 0; + + /* Read phy parameter files */ + rtw_hal_dl_all_para_file(phl_com, init_info->ic_name, hal); + + hal_status = rtw_hal_mac_hal_init(phl_com, hal, init_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_init_fail; + + rtw_hal_set_rxfltr_by_mode(hal, HW_BAND_0, RX_FLTR_MODE_STA_NORMAL); + /* MAC Suggested : 11264 Byte */ + rtw_hal_mac_set_rxfltr_mpdu_size(hal->hal_com, HW_BAND_0, 0x2c00); + rtw_hal_mac_set_hw_rts_th(hal, HW_BAND_0, + phy_cap[HW_BAND_0].hw_rts_time_th, + phy_cap[HW_BAND_0].hw_rts_len_th); + if (hal->hal_com->dbcc_en == true) { + rtw_hal_set_rxfltr_by_mode(hal, HW_BAND_1, RX_FLTR_MODE_STA_NORMAL); + rtw_hal_mac_set_rxfltr_mpdu_size(hal->hal_com, HW_BAND_1, 0x2c00); + rtw_hal_mac_set_hw_rts_th(hal, HW_BAND_1, + phy_cap[HW_BAND_1].hw_rts_time_th, + phy_cap[HW_BAND_1].hw_rts_len_th); + } +#ifdef CONFIG_BTCOEX + /* power on config for btc */ + rtw_hal_btc_power_on_ntfy(hal); +#endif + + /* EFUSE config */ + rtw_hal_efuse_process(hal, init_info->ic_name); + rtw_hal_final_cap_decision(phl_com, hal); + + /*[Pre-config BB/RF] BBRST / RFC reset */ + rtw_hal_mac_enable_bb_rf(hal, 0); + rtw_hal_mac_enable_bb_rf(hal, 1); + + /* load parameters or config mac, phy, btc, ... */ +#ifdef USE_TRUE_PHY + rtw_hal_init_bb_reg(hal); + rtw_hal_init_rf_reg(phl_com, hal); +#endif + +#ifdef CONFIG_BTCOEX + /* After mac/bb/rf initialized, set btc config */ + rtw_hal_btc_init_coex_cfg_ntfy(hal); +#endif + /* start watchdog/dm */ + rtw_hal_bb_dm_init(hal); + rtw_hal_rf_dm_init(hal); + + hal_status = rtw_hal_mac_get_append_fcs(hal, &val); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_init_fail; + else + phl_com->append_fcs = val; + + hal_status = rtw_hal_mac_get_acpt_icv_err(hal, &val); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_init_fail; + else + phl_com->append_fcs = val; + +#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE + rtw_hal_mac_config_hw_mgnt_sec(hal, false); +#endif + + PHL_INFO("==> Default ENABLE RX_PPDU_STS for Band0\n"); + /* Enable PPDU STS in default for BAND-0 for phy status */ + hal->hal_com->band[HW_BAND_0].ppdu_sts_appen_info = HAL_PPDU_MAC_INFO | HAL_PPDU_PLCP | HAL_PPDU_RX_CNT; + hal->hal_com->band[HW_BAND_0].ppdu_sts_filter = (HAL_PPDU_HAS_CRC_OK | HAL_PPDU_HAS_A1M); + rtw_hal_mac_ppdu_stat_cfg( + hal, HW_BAND_0, true, + hal->hal_com->band[HW_BAND_0].ppdu_sts_appen_info, + hal->hal_com->band[HW_BAND_0].ppdu_sts_filter); + + phl_com->ppdu_sts_info.en_ppdu_sts[HW_BAND_0] = true; + /*TODO Enable PPDU STS in default for BAND-1 for phy status */ + + hal_status = rtw_hal_hdr_conv_cfg(hal, phl_com->dev_cap.hw_hdr_conv); + if (hal_status != RTW_HAL_STATUS_SUCCESS) + goto hal_init_fail; + + /* Enable FW basic logs */ + hal_fw_en_basic_log(hal->hal_com); + + return RTW_HAL_STATUS_SUCCESS; + +hal_init_fail: + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "==> %s : hal init fail\n", __func__); + return hal_status; +} + +enum rtw_hal_status hal_stop_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + +#ifdef CONFIG_BTCOEX + /* power off config for btc */ + rtw_hal_btc_power_off_ntfy(hal); +#endif + hal_status = rtw_hal_mac_hal_deinit(phl_com, hal); + rtw_hal_bb_dm_deinit(phl_com, hal); + return hal_status; +} + +#ifdef CONFIG_WOWLAN +enum rtw_hal_status +hal_wow_init_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta, + struct hal_init_info_t *init_info) +{ + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_WOWLAN); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_redownload_fw(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_mac_role_sync(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: role sync fail!\n", __func__); + goto exit; + } + + hal_status = rtw_hal_update_sta_entry(hal_info, sta, true); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: update sta entry fail(%d)!!\n", __func__, hal_status); + goto exit; + } + +#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE + rtw_hal_mac_config_hw_mgnt_sec(hal_info, true); +#endif + +exit: + return hal_status; +} + +enum rtw_hal_status +hal_wow_deinit_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta, + struct hal_init_info_t *init_info) +{ + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + /* AOAC Report */ + + hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_redownload_fw(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_mac_role_sync(hal_info, sta); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: role sync fail!\n", __func__); + goto exit; + } + + hal_status = rtw_hal_update_sta_entry(hal_info, sta, true); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: update sta entry fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + /* To Do : Recover RA ? */ + +#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE + rtw_hal_mac_config_hw_mgnt_sec(hal_info, false); +#endif + +exit: + return hal_status; +} +#endif /* CONFIG_WOWLAN */ + +#ifdef RTW_PHL_BCN /* fill 8852b bcn ops */ +enum rtw_hal_status hal_config_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry) +{ + if(hal_mac_ax_config_beacon(hal, bcn_entry) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status hal_update_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry) +{ + if(hal_mac_ax_send_beacon(hal, bcn_entry) == RTW_HAL_STATUS_FAILURE) + return RTW_HAL_STATUS_FAILURE; + + return RTW_HAL_STATUS_SUCCESS; +} + +#endif /* RTW_PHL_BCN */ + + +enum rtw_hal_status +hal_mp_init_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info) +{ + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_redownload_fw(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } +exit: + return hal_status; +} + +enum rtw_hal_status +hal_mp_deinit_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_info) +{ + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS; + + hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + + hal_status = rtw_hal_redownload_fw(phl_com, hal_info); + if (hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status); + goto exit; + } + +exit: + return hal_status; +} diff --git a/phl/hal_g6/rtl8852b/rtl8852b_mac.c b/phl/hal_g6/rtl8852b/rtl8852b_mac.c new file mode 100644 index 0000000..24857c2 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_mac.c @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_MAC_C_ +#include "../hal_headers.h" + + diff --git a/phl/hal_g6/rtl8852b/rtl8852b_ops.c b/phl/hal_g6/rtl8852b/rtl8852b_ops.c new file mode 100644 index 0000000..49b26d7 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_ops.c @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_OPS_C_ +#include "../hal_headers.h" +#include "rtl8852b_hal.h" + +static void read_chip_version_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + hal_mac_get_hwinfo(hal, &(phl_com->hal_spec)); + +} + +/*******************temp common IO APIs *******************/ +extern u32 hal_read_macreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask); +extern void hal_write_macreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data); +extern u32 hal_read_bbreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask); +extern void hal_write_bbreg(struct hal_info_t *hal, + u32 offset, u32 bit_mask, u32 data); +extern u32 hal_read_rfreg(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask); +extern void hal_write_rfreg(struct hal_info_t *hal, + enum rf_path path, u32 offset, u32 bit_mask, u32 data); + +void hal_set_ops_8852b(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + struct hal_ops_t *ops = hal_get_ops(hal); + + /*** initialize section ***/ + ops->read_chip_version = read_chip_version_8852b; + ops->hal_cfg_fw = hal_cfg_fw_8852b; + + ops->read_macreg = hal_read_macreg; + ops->write_macreg = hal_write_macreg; + ops->read_bbreg = hal_read_bbreg; + ops->write_bbreg = hal_write_bbreg; + ops->read_rfreg = hal_read_rfreg; + ops->write_rfreg = hal_write_rfreg; + +#ifdef RTW_PHL_BCN + ops->cfg_bcn = hal_config_beacon_8852b; + ops->upt_bcn = hal_update_beacon_8852b; +#endif + + ops->pkt_ofld = rtw_hal_mac_pkt_ofld; + ops->pkt_update_ids = rtw_hal_mac_pkt_update_ids; +} + +#if 0 +void hal_set_trx_ops_8852b(struct hal_info_t *hal) +{ + struct hal_trx_ops_t *ops = hal_get_trx_ops(hal); + + ops->get_txdesc_len = get_txdesc_len_8852b; + ops->fill_txdesc_h2c = fill_txdesc_h2c_8852b; + ops->fill_txdesc_fwdl = fill_txdesc_fwdl_8852b; + ops->fill_txdesc_pkt = fill_txdesc_pkt_8852b; +} +#endif + diff --git a/phl/hal_g6/rtl8852b/rtl8852b_phy.c b/phl/hal_g6/rtl8852b/rtl8852b_phy.c new file mode 100644 index 0000000..34e3270 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_phy.c @@ -0,0 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852B_PHY_C_ +#include "../hal_headers.h" + diff --git a/phl/hal_g6/rtl8852b/rtl8852b_phy.h b/phl/hal_g6/rtl8852b/rtl8852b_phy.h new file mode 100644 index 0000000..fcda24c --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_phy.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8852B_PHY_H__ +#define __RTL8852B_PHY_H__ +/* rtl8852b_phy.c */ + + +#endif /*__RTL8852B_PHY_H__*/ diff --git a/phl/hal_g6/rtl8852b/rtl8852b_spec.h b/phl/hal_g6/rtl8852b/rtl8852b_spec.h new file mode 100644 index 0000000..c7e9439 --- /dev/null +++ b/phl/hal_g6/rtl8852b/rtl8852b_spec.h @@ -0,0 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8852B_SPEC_H__ +#define __RTL8852B_SPEC_H__ + + +#endif /* __RTL8852B_SPEC_H__ */ diff --git a/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.c b/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.c new file mode 100644 index 0000000..46595aa --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.c @@ -0,0 +1,402 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TRX_8852BU_C_ +#include "../../hal_headers.h" +#include "../rtl8852b_hal.h" +#include "hal_trx_8852bu.h" + + +static void _hal_dump_rxdesc(u8 *buf, struct rtw_r_meta_data *mdata) +{ + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "%s ==>\n", __FUNCTION__); + + debug_dump_data(buf, 56, "_hal_dump_rxdesc:: "); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pktlen = 0x%X\n", mdata->pktlen); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->shift = 0x%X\n", mdata->shift); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->wl_hd_iv_len = 0x%X\n", + mdata->wl_hd_iv_len); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bb_sel = 0x%X\n", + mdata->bb_sel); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mac_info_vld = 0x%X\n", + mdata->mac_info_vld); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rpkt_type = 0x%X\n", + mdata->rpkt_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->drv_info_size = 0x%X\n", + mdata->drv_info_size); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->long_rxd = 0x%X\n", + mdata->long_rxd); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_type = 0x%X\n", + mdata->ppdu_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_cnt = 0x%X\n", + mdata->ppdu_cnt); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sr_en = 0x%X\n", + mdata->sr_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->user_id = 0x%X\n", + mdata->user_id); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_rate = 0x%X\n", + mdata->rx_rate); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_gi_ltf = 0x%X\n", + mdata->rx_gi_ltf); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->non_srg_ppdu = 0x%X\n", + mdata->non_srg_ppdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->inter_ppdu = 0x%X\n", + mdata->inter_ppdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bw = 0x%X\n", + mdata->bw ); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->freerun_cnt = 0x%X\n", + mdata->freerun_cnt); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->a1_match = 0x%X\n", + mdata->a1_match); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sw_dec = 0x%X\n", + mdata->sw_dec); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->hw_dec = 0x%X\n", + mdata->hw_dec); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu = 0x%X\n", + mdata->ampdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu_end_pkt = 0x%X\n", + mdata->ampdu_end_pkt); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu = 0x%X\n", + mdata->amsdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu_cut = 0x%X\n", + mdata->amsdu_cut); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->last_msdu = 0x%X\n", + mdata->last_msdu); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bypass = 0x%X\n", + mdata->bypass); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->crc32 = 0x%X\n", + mdata->crc32); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->icverr = 0x%X\n", + mdata->icverr); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->magic_wake = 0x%X\n", + mdata->magic_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->unicast_wake = 0x%X\n", + mdata->unicast_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_wake = 0x%X\n", + mdata->pattern_wake); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->get_ch_info = 0x%X \n", + mdata->get_ch_info); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_statistics = 0x%X\n", + mdata->rx_statistics); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_idx = 0x%X\n", + mdata->pattern_idx); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->target_idc = 0x%X\n", + mdata->target_idc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->chksum_ofld_en = 0x%X\n", + mdata->chksum_ofld_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->with_llc = 0x%X\n", + mdata->with_llc); + + + if (mdata->long_rxd==1) + { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frame_type = 0x%X\n", + mdata->frame_type); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mc = 0x%X\n", + mdata->mc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bc = 0x%X\n", + mdata->bc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_data = 0x%X\n", + mdata->more_data); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_frag = 0x%X\n", + mdata->more_frag); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pwr_bit = 0x%X\n", + mdata->pwr_bit); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->qos = 0x%X\n", + mdata->qos); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->tid = 0x%X\n", + mdata->tid); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->eosp = 0x%X\n", + mdata->eosp); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->htc = 0x%X\n", + mdata->htc); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->q_null = 0x%X\n", + mdata->q_null); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->seq = 0x%X\n", + mdata->seq); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frag_num = 0x%X\n", + mdata->frag_num); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sec_cam_idx = 0x%X\n", + mdata->sec_cam_idx); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam = 0x%X\n", + mdata->addr_cam); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->macid = 0x%X\n\n", + mdata->macid); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_id = 0x%X\n", + mdata->rx_pl_id); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam_vld = 0x%X\n", + mdata->addr_cam_vld); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_fwd_en = 0x%X\n", + mdata->addr_fwd_en); + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_match = 0x%X\n", + mdata->rx_pl_match); + + debug_dump_data(mdata->mac_addr, 6, "mdata->mac_addr = \n"); + } + + + +} + + +/** + * the function will initializing 8852bu specific data and hw configuration + */ +enum rtw_hal_status hal_trx_init_8852bu(struct hal_info_t *hal) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + return hstatus; +} +/** + * the function will deinitializing 8852bu specific data and hw configuration + */ +static void hal_trx_deinit_8852bu(struct hal_info_t *hal) +{ +} + +static u8 hal_mapping_hw_tx_chnl_8852bu(u16 macid, enum rtw_phl_ring_cat cat, + u8 band) +{ + u8 dma_ch = 0; + + /* hana_todo, decided by tid only currently, + we should consider more situation later */ + + if (0 == band) { + switch (cat) { + case RTW_PHL_RING_CAT_TID0:/*AC_BE*/ + case RTW_PHL_RING_CAT_TID3: + dma_ch = ACH2_QUEUE_IDX_8852B; + break; + case RTW_PHL_RING_CAT_TID1:/*AC_BK*/ + case RTW_PHL_RING_CAT_TID2: + dma_ch = ACH3_QUEUE_IDX_8852B; + break; + case RTW_PHL_RING_CAT_TID4:/*AC_VI*/ + case RTW_PHL_RING_CAT_TID5: + dma_ch = ACH1_QUEUE_IDX_8852B; + break; + case RTW_PHL_RING_CAT_TID6:/*AC_VO*/ + case RTW_PHL_RING_CAT_TID7: + dma_ch = ACH0_QUEUE_IDX_8852B; + break; + case RTW_PHL_RING_CAT_MGNT: + dma_ch = MGQ_B0_QUEUE_IDX_8852B; + break; + case RTW_PHL_RING_CAT_HIQ: + dma_ch = HIQ_B0_QUEUE_IDX_8852B; + break; + default: + dma_ch = ACH0_QUEUE_IDX_8852B; + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown category (%d)\n", + cat); + break; + } + } else { + dma_ch = ACH0_QUEUE_IDX_8852B; + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown band (%d)\n", + band); + } + + return dma_ch; +} + +static enum rtw_hal_status hal_query_info_8852bu(struct hal_info_t *hal, u8 info_id, void *value) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS; + + switch (info_id){ + case RTW_HAL_RXDESC_SIZE: + /* wifi packet(RXD.RPKT_TYPE = 0x0) = 32 bytes, otherwise 16 bytes */ + *((u8 *)value) = RX_DESC_S_SIZE_8852B; + break; + default: + hstatus = RTW_HAL_STATUS_FAILURE; + break; + } + return hstatus; +} + +static enum rtw_hal_status hal_pltfm_tx_8852bu(void *hal, + struct rtw_h2c_pkt *pkt) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + return hstatus; +} + +u8 hal_get_bulkout_id_8852bu(struct hal_info_t *hal, u8 dma_ch, u8 mode) +{ + return hal_mac_get_bulkout_id(hal, dma_ch, mode); +} + +u8 hal_get_max_bulkout_wd_num_8852bu(struct hal_info_t *hal) +{ + return hal_mac_usb_get_max_bulkout_wd_num(hal); +} + +/** + * the function update wd page, including wd info, wd body, seq info + * @hal: see struct hal_info_t + * @phl_pkt_req: see struct rtw_phl_pkt_req + */ +enum rtw_hal_status +hal_fill_wd_8852bu(struct hal_info_t *hal, struct rtw_xmit_req *tx_req, + u8 *wd_buf, u32 *wd_len) +{ + return rtw_hal_mac_ax_fill_txdesc(hal->mac, tx_req, wd_buf, wd_len); +} + +enum rtw_hal_status +hal_usb_tx_agg_cfg_8852bu(struct hal_info_t *hal, u8* wd_buf, u8 agg_num) +{ + return hal_mac_usb_tx_agg_cfg(hal, wd_buf, agg_num); +} + +enum rtw_hal_status +hal_usb_rx_agg_cfg_8852bu(struct hal_info_t *hal, u8 mode, u8 agg_mode, + u8 drv_define, u8 timeout, u8 size, u8 pkt_num) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + /*u8 drv_define, u8 timeout, u8 size, u8 pkt_num*/ + /*mode 0: disable*/ + /*mode 1: default (0x2005)*/ + /*mode 2: 0x0101*/ + switch (mode){ + case PHL_RX_AGG_DISABLE: + hstatus = hal_mac_usb_rx_agg_cfg(hal, 0, 0, 0, 0, 0); + break; + case PHL_RX_AGG_DEFAULT: + hstatus = hal_mac_usb_rx_agg_cfg(hal, MAC_AX_RX_AGG_MODE_USB, + 0, 0, 0, 0); + break; + case PHL_RX_AGG_SMALL_PKT: + hstatus = hal_mac_usb_rx_agg_cfg(hal, MAC_AX_RX_AGG_MODE_USB, + 1, 0x01, 0x01, 0); + break; + case PHL_RX_AGG_USER_DEFINE: + hstatus = hal_mac_usb_rx_agg_cfg(hal, agg_mode, + drv_define, timeout, size, pkt_num); + break; + default: + hstatus = RTW_HAL_STATUS_FAILURE; + break; + } + return hstatus; +} + +static void _hal_show_tx_failure_rsn_8852bu(u8 txsts) +{ + + switch (txsts) { + + case TX_STATUS_TX_FAIL_REACH_RTY_LMT: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is tx fail (REACH_RTY_LMT)\n"); + break; + case TX_STATUS_TX_FAIL_LIFETIME_DROP: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is tx fail (LIFETIME_DROP)\n"); + break; + case TX_STATUS_TX_FAIL_MACID_DROP: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is tx fail (MACID_DROP)\n"); + break; + case TX_STATUS_TX_FAIL_SW_DROP: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is tx fail (SW_DROP)\n"); + break; + default: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is tx fail (UNKNOWN)\n"); + break; + } + +} + +u16 hal_handle_rx_report_8852bu(struct hal_info_t *hal, u8 *rp, + u16 len, u8 *mac_id, u8 *ac_queue, u8 *txsts) +{ + u8 polluted = false; + u16 rsize = 0; + u8 qsel_value = 0; + + do { + if (len < RX_RP_PACKET_SIZE) + break; + + *mac_id = (u8)GET_RX_RP_PKT_MAC_ID(rp); + qsel_value = (u8)GET_RX_RP_PKT_QSEL(rp); + *txsts = (u8)GET_RX_RP_PKT_TX_STS(rp); + /* wp_seq useless for usb case, then skip parsing*/ + polluted = (u8)GET_RX_RP_PKT_POLLUTED(rp); + + *ac_queue = qsel_value % RTW_MAX_AC_QUEUE_NUM; + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Get recycle report: qsel = %d, macid = %d, ac_queue = %d\n", + qsel_value, *mac_id, *ac_queue); + + if (TX_STATUS_TX_DONE != *txsts) { + + _hal_show_tx_failure_rsn_8852bu(*txsts); + + } else if (true == polluted) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp is polluted\n"); + /*todo handle sw retry */ + } else { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "this wp tx done\n"); + } + + rsize = RX_RP_PACKET_SIZE; + } while (false); + + return rsize; +} + +u8 hal_get_fwcmd_queue_idx_8852bu(void) +{ + return FWCMD_QUEUE_IDX_8852B; +} + +static struct hal_trx_ops ops= { + .init = hal_trx_init_8852bu, + .deinit = hal_trx_deinit_8852bu, + .map_hw_tx_chnl = hal_mapping_hw_tx_chnl_8852bu, + .get_bulkout_id = hal_get_bulkout_id_8852bu, + .hal_fill_wd = hal_fill_wd_8852bu, + .handle_rx_buffer = hal_handle_rx_buffer_8852b, + .query_hal_info = hal_query_info_8852bu, + .usb_tx_agg_cfg = hal_usb_tx_agg_cfg_8852bu, + .usb_rx_agg_cfg = hal_usb_rx_agg_cfg_8852bu, + .get_fwcmd_queue_idx = hal_get_fwcmd_queue_idx_8852bu, + .get_max_bulkout_wd_num = hal_get_max_bulkout_wd_num_8852bu, + .handle_wp_rpt = hal_handle_rx_report_8852bu, +}; + +u32 hal_hook_trx_ops_8852bu(struct hal_info_t *hal_info) +{ + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + if (NULL != hal_info) { + hal_info->trx_ops = &ops; + hstatus = RTW_HAL_STATUS_SUCCESS; + } + + return hstatus; +} diff --git a/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.h b/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.h new file mode 100644 index 0000000..487106d --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/hal_trx_8852bu.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_TRX_8852BU_H_ +#define _HAL_TRX_8852BU_H_ + +/* Release report size and format*/ +#define RX_RP_PACKET_SIZE 4 + +#define GET_RX_RP_PKT_POLLUTED(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 31, 1) +#define GET_RX_RP_PKT_PCIE_SEQ(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 16, 15) +#define GET_RX_RP_PKT_TX_STS(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 13, 3) +#define GET_RX_RP_PKT_QSEL(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 8, 5) +#define GET_RX_RP_PKT_MAC_ID(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 0, 8) + + +#endif /*_HAL_TRX_8852BU_H_*/ diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu.h b/phl/hal_g6/rtl8852b/usb/rtl8852bu.h new file mode 100644 index 0000000..b0bb7f3 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8852BU_H_ +#define _RTL8852BU_H_ +/*provide IC-BUS's function declaration or definition to IC*/ + + + +#endif /* _RTL8852BU_H_ */ diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_hal.h b/phl/hal_g6/rtl8852b/usb/rtl8852bu_hal.h new file mode 100644 index 0000000..b247093 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_hal.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8852BU_HAL_H_ +#define _RTL8852BU_HAL_H_ + +/* rtl8852bu_halinit.c */ +#ifdef CONFIG_WOWLAN +enum rtw_hal_status hal_wow_init_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); +enum rtw_hal_status hal_wow_deinit_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); +#endif /* CONFIG_WOWLAN */ +enum rtw_hal_status hal_get_efuse_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + +enum rtw_hal_status hal_init_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +void hal_deinit_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + +enum rtw_hal_status hal_start_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); +enum rtw_hal_status hal_stop_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + +enum rtw_hal_status hal_mp_init_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal); +enum rtw_hal_status hal_mp_deinit_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal); + +u32 hal_hci_cfg_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_ic_info *ic_info); + +void init_hal_spec_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal); + +bool hal_recognize_int_8852bu(struct hal_info_t *hal); +u32 hal_int_hdler_8852bu(struct hal_info_t *hal); + +#endif /* _RTL8852BU_HAL_H_ */ diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_halinit.c b/phl/hal_g6/rtl8852b/usb/rtl8852bu_halinit.c new file mode 100644 index 0000000..01f3685 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_halinit.c @@ -0,0 +1,341 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852BU_HALINIT_C_ +#include "../../hal_headers.h" +#include "../rtl8852b_hal.h" + +static void _hal_pre_init_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info, + struct hal_init_info_t *init_52bu) +{ + struct mac_ax_trx_info *trx_info = &init_52bu->trx_info; + struct mac_ax_host_rpr_cfg *rpr_cfg = (struct mac_ax_host_rpr_cfg *)hal_info->rpr_cfg; + + if (true == phl_com->dev_cap.tx_mu_ru) + trx_info->trx_mode = MAC_AX_TRX_SW_MODE; + else + trx_info->trx_mode = MAC_AX_TRX_HW_MODE; + + if (hal_info->hal_com->dbcc_en == false) + trx_info->qta_mode = MAC_AX_QTA_SCC; + else + trx_info->qta_mode = MAC_AX_QTA_DBCC; + + #ifdef RTW_WKARD_LAMODE + PHL_INFO("%s : la_mode %d\n", __func__, phl_com->dev_cap.la_mode); + if (phl_com->dev_cap.la_mode) + trx_info->qta_mode = MAC_AX_QTA_LAMODE; + #endif + + if (phl_com->dev_cap.rpq_agg_num) { + rpr_cfg->agg_def = 0; + rpr_cfg->agg = phl_com->dev_cap.rpq_agg_num; + } else { + rpr_cfg->agg_def = 1; + } + + rpr_cfg->tmr_def = 1; + #ifdef CONFIG_PHL_USB_RELEASE_RPT_ENABLE + rpr_cfg->txok_en = MAC_AX_FUNC_EN; + rpr_cfg->rty_lmt_en = MAC_AX_FUNC_EN; + rpr_cfg->lft_drop_en = MAC_AX_FUNC_EN; + rpr_cfg->macid_drop_en = MAC_AX_FUNC_EN; + #else + rpr_cfg->txok_en = MAC_AX_FUNC_DEF; + rpr_cfg->rty_lmt_en = MAC_AX_FUNC_DEF; + rpr_cfg->lft_drop_en = MAC_AX_FUNC_DEF; + rpr_cfg->macid_drop_en = MAC_AX_FUNC_DEF; + #endif /* CONFIG_PHL_USB_RELEASE_RPT_ENABLE */ + trx_info->rpr_cfg = rpr_cfg; + + init_52bu->ic_name = "rtl8852bu"; +} + +void init_hal_spec_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + struct rtw_hal_com_t *hal_com = hal->hal_com; + struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap; + + init_hal_spec_8852b(phl_com, hal); + phl_com->dev_cap.hw_sup_flags |= HW_SUP_USB_MULTI_FUN; + bus_hw_cap->tx_buf_size = 20480; + bus_hw_cap->tx_buf_num = 4; + bus_hw_cap->tx_mgnt_buf_size = 1536; + bus_hw_cap->tx_mgnt_buf_num = 32; + bus_hw_cap->tx_h2c_buf_num = MAX_H2C_PKT_NUM; + bus_hw_cap->rx_buf_size = 512*60; + bus_hw_cap->rx_buf_num = 128; + bus_hw_cap->in_token_num = 6; + + hal->hal_com->dev_hw_cap.ps_cap.lps_pause_tx = true; +} + +enum rtw_hal_status hal_get_efuse_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct hal_init_info_t init_52bu; + + _os_mem_set(hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + _hal_pre_init_8852bu(phl_com, hal_info, &init_52bu); + + return hal_get_efuse_8852b(phl_com, hal_info, &init_52bu); +} + +enum rtw_hal_status hal_init_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + /* allocate memory for hal */ + hal_info->rpr_cfg = _os_mem_alloc(phlcom_to_drvpriv(phl_com), + sizeof(struct mac_ax_host_rpr_cfg)); + if (hal_info->rpr_cfg == NULL) { + hal_status = RTW_HAL_STATUS_RESOURCE; + PHL_ERR("%s: alloc rpr_cfg failed\n", __func__); + goto error_rpr_cfg; + } + + hal_status = RTW_HAL_STATUS_SUCCESS; + +error_rpr_cfg: + return hal_status; +} + +void hal_deinit_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + /* free memory for hal */ + _os_mem_free(phlcom_to_drvpriv(phl_com), + hal_info->rpr_cfg, + sizeof(struct mac_ax_host_rpr_cfg)); +} + +enum rtw_hal_status hal_start_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal_info) +{ + struct hal_init_info_t init_52bu; + + _os_mem_set(hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + _hal_pre_init_8852bu(phl_com, hal_info, &init_52bu); + + return hal_start_8852b(phl_com, hal_info, &init_52bu); +} + +static void hal_deinit_misc_8852bu(struct hal_info_t *hal) +{ + +} +#ifdef CONFIG_WOWLAN +enum rtw_hal_status +hal_wow_init_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct hal_init_info_t init_52bu; + struct mac_ax_trx_info *trx_info = &init_52bu.trx_info; + + _os_mem_set( hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + if (true == phl_com->dev_cap.tx_mu_ru) + trx_info->trx_mode = MAC_AX_TRX_SW_MODE; + else + trx_info->trx_mode = MAC_AX_TRX_HW_MODE; + trx_info->qta_mode = MAC_AX_QTA_SCC; + + init_52bu.ic_name = "rtl8852bu"; + + return hal_wow_init_8852b(phl_com, hal_info, sta, &init_52bu); +} + +enum rtw_hal_status +hal_wow_deinit_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info, + struct rtw_phl_stainfo_t *sta) +{ + struct hal_init_info_t init_52bu; + struct mac_ax_trx_info *trx_info = &init_52bu.trx_info; + + _os_mem_set( hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + if (true == phl_com->dev_cap.tx_mu_ru) + trx_info->trx_mode = MAC_AX_TRX_SW_MODE; + else + trx_info->trx_mode = MAC_AX_TRX_HW_MODE; + trx_info->qta_mode = MAC_AX_QTA_SCC; + + init_52bu.ic_name = "rtl8852bu"; + + return hal_wow_deinit_8852b(phl_com, hal_info, sta, &init_52bu); +} +#endif /* CONFIG_WOWLAN */ + + +enum rtw_hal_status hal_stop_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = hal_stop_8852b(phl_com, hal); + return hal_status; +} + +static const char *const _usb_sp[] = { + "USB_SPEED_LOW", + "USB_SPEED_FULL", + "USB_SPEED_HIGH", + "USB_SPEED_SUPER", + "USB_SPEED_SUPER_10G", + "USB_SPEED_SUPER_20G", + "USB_SPEED_UNKNOWN" +}; +#define usb_speed_str(_spidx) (((_spidx) >= RTW_USB_SPEED_UNKNOWN)\ + ? _usb_sp[RTW_USB_SPEED_UNKNOWN] : _usb_sp[(_spidx)]) + +u32 hal_hci_cfg_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal, struct rtw_ic_info *ic_info) +{ + struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com); + + /*get USB Bus-info from os*/ + PHL_INFO("%s ===>\n", __func__); + PHL_INFO("%s\n", usb_speed_str(ic_info->usb_info.usb_speed)); + PHL_INFO("Bulk-Out size - %d\n", ic_info->usb_info.usb_bulkout_size); + PHL_INFO("Bulk-Out Number - %d\n", ic_info->usb_info.outep_num); + PHL_INFO("Bulk-In Number - %d\n", ic_info->usb_info.inep_num); + + hal_spec->max_bulkin_num = ic_info->usb_info.inep_num; + hal_spec->max_bulkout_num = ic_info->usb_info.outep_num; + hal_spec->cts2_thres_en = false; + hal_spec->cts2_thres = 0; + + return RTW_HAL_STATUS_SUCCESS; +} + + +bool hal_recognize_int_8852bu(struct hal_info_t *hal) +{ + struct rtw_hal_com_t *hal_com = hal->hal_com; + bool recognized = false; + u32 usb_isr = 0; + + usb_isr = hal_read32(hal_com, R_AX_HUSBISR); + + if (usb_isr & B_AX_HS0ISR_IND_INT) { /*B_AX_HS0ISR_IND_INT*/ + /* halt c2h */ + hal_com->intr.halt_c2h_int.intr = hal_read32(hal_com, R_AX_HISR0); + hal_com->intr.halt_c2h_int.intr &= hal_com->intr.halt_c2h_int.val_mask; + hal_write32(hal_com,R_AX_HISR0, hal_com->intr.halt_c2h_int.intr); + } else { + hal_com->intr.halt_c2h_int.intr = 0; + } + + if (usb_isr & B_AX_HD0ISR_IND_INT) { /*B_AX_HD0ISR_IND_INT*/ + /* watchdog timer */ + hal_com->intr.watchdog_timer_int.intr = hal_read32(hal_com, R_AX_HD0ISR); + hal_com->intr.watchdog_timer_int.intr &= hal_com->intr.watchdog_timer_int.val_mask; + hal_write32(hal_com,R_AX_HD0ISR, hal_com->intr.watchdog_timer_int.intr); + } else { + hal_com->intr.watchdog_timer_int.intr = 0; + } + + if (hal_com->intr.halt_c2h_int.intr || hal_com->intr.watchdog_timer_int.intr) + recognized = true; + + return recognized; +} + +static u32 hal_halt_c2h_handler_8852bu(struct hal_info_t *hal, u32 *handled) +{ + u32 ret = 0; + struct rtw_hal_com_t *hal_com = hal->hal_com; + + if (hal_com->intr.halt_c2h_int.intr & B_AX_HALT_C2H_INT_EN) { + handled[0] |= B_AX_HALT_C2H_INT_EN; + ret = 1; + } + + return ret; +} + +static u32 hal_watchdog_timer_handler_8852bu(struct hal_info_t *hal, u32 *handled) +{ + u32 ret = 0; + struct rtw_hal_com_t *hal_com = hal->hal_com; + + if (hal_com->intr.watchdog_timer_int.intr & B_AX_WDT_PTFM_INT_EN) { + handled[1] |= B_AX_WDT_PTFM_INT_EN; + ret = 1; + } + + return ret; +} + +u32 hal_int_hdler_8852bu(struct hal_info_t *hal) +{ + u32 int_hdler_msk = 0x0; + u32 generalhandled[8] = {0}; + + /* Start General interrupt type */ + /* <4> Halt C2H related */ + int_hdler_msk |= (hal_halt_c2h_handler_8852bu(hal, generalhandled) << 4); + + /* <4>watchdog timer related */ + int_hdler_msk |= (hal_watchdog_timer_handler_8852bu(hal, generalhandled) << 5); + + PHL_TRACE(COMP_PHL_DBG,_PHL_INFO_, "%s: int_hdler_msk = 0x%x\n", __func__, int_hdler_msk); + + return int_hdler_msk; +} + +enum rtw_hal_status +hal_mp_init_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_init_info_t init_52bu; + + FUNCIN_WSTS(hal_status); + + _os_mem_set(hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + + init_52bu.ic_name = "rtl8852bu"; + + hal_status = hal_mp_init_8852b(phl_com, hal_info, &init_52bu); + + FUNCOUT_WSTS(hal_status); + return hal_status; +} + +enum rtw_hal_status +hal_mp_deinit_8852bu(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_init_info_t init_52bu; + + FUNCIN_WSTS(hal_status); + + _os_mem_set(hal_to_drvpriv(hal_info), &init_52bu, 0, sizeof(init_52bu)); + + init_52bu.ic_name = "rtl8852bu"; + + hal_status = hal_mp_deinit_8852b(phl_com, hal_info, &init_52bu); + + if (RTW_HAL_STATUS_SUCCESS != hal_status) { + + PHL_ERR("hal_mp_deinit_8852bu: status = %u\n", hal_status); + return hal_status; + } + + FUNCOUT_WSTS(hal_status); + return hal_status; +} + + diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_halmac.c b/phl/hal_g6/rtl8852b/usb/rtl8852bu_halmac.c new file mode 100644 index 0000000..195e910 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_halmac.c @@ -0,0 +1,16 @@ +/****************************************************************************** + * + * Copyright(c) 22019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852BU_HALMAC_C_ + diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_io.c b/phl/hal_g6/rtl8852b/usb/rtl8852bu_io.c new file mode 100644 index 0000000..c688433 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_io.c @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852BU_IO_C_ +#include "../../hal_headers.h" +#include "../../hal_usb.h" + +void hal_usb_set_io_ops_8852bu(struct hal_info_t *hal, struct hal_io_ops *ops) +{ +/* + ops->_read8 = &usb_read8; + ops->_read16 = &usb_read16; + ops->_read32 = &usb_read32; + + ops->_write8 = &usb_write8; + ops->_write16 = &usb_write16; + ops->_write32 = &usb_write32; + ops->_write_mem = &usb_write_mem; +*/ +} diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_led.c b/phl/hal_g6/rtl8852b/usb/rtl8852bu_led.c new file mode 100644 index 0000000..a558dd7 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_led.c @@ -0,0 +1,16 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852BU_LED_C_ + diff --git a/phl/hal_g6/rtl8852b/usb/rtl8852bu_ops.c b/phl/hal_g6/rtl8852b/usb/rtl8852bu_ops.c new file mode 100644 index 0000000..7b26fe7 --- /dev/null +++ b/phl/hal_g6/rtl8852b/usb/rtl8852bu_ops.c @@ -0,0 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTL8852BU_OPS_C_ +#include "../rtl8852b_hal.h" +#include "rtl8852bu.h" + +static void init_default_value_8852bu(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg) +{ + struct rtw_hal_com_t *hal_com = hal->hal_com; + + init_default_value_8852b(hal); + + hal_com->intr.halt_c2h_int.val_default = (u32)( + (cfg->halt_c2h_en == 1 ? B_AX_HALT_C2H_INT_EN : 0) | + 0); + + hal_com->intr.watchdog_timer_int.val_default = (u32)( + (cfg->wdt_en == 1 ? B_AX_WDT_PTFM_INT_EN : 0) | + 0); + + hal_com->intr.halt_c2h_int.val_mask = hal_com->intr.halt_c2h_int.val_default; + hal_com->intr.watchdog_timer_int.val_mask = hal_com->intr.watchdog_timer_int.val_default; +} + +void hal_set_ops_8852bu(struct rtw_phl_com_t *phl_com, + struct hal_info_t *hal) +{ + struct hal_ops_t *ops = hal_get_ops(hal); + + hal_set_ops_8852b(phl_com, hal); + + ops->init_hal_spec = init_hal_spec_8852bu; + ops->hal_get_efuse = hal_get_efuse_8852bu; + ops->hal_init = hal_init_8852bu; + ops->hal_deinit = hal_deinit_8852bu; + ops->hal_start = hal_start_8852bu; + ops->hal_stop = hal_stop_8852bu; +#ifdef CONFIG_WOWLAN + ops->hal_wow_init = hal_wow_init_8852bu; + ops->hal_wow_deinit = hal_wow_deinit_8852bu; +#endif /* CONFIG_WOWLAN */ + + ops->hal_mp_init = hal_mp_init_8852bu; + ops->hal_mp_deinit = hal_mp_deinit_8852bu; + + ops->hal_hci_configure = hal_hci_cfg_8852bu; + ops->init_default_value = init_default_value_8852bu; + ops->recognize_interrupt = hal_recognize_int_8852bu; + ops->interrupt_handler = hal_int_hdler_8852bu; +} + + + diff --git a/phl/hal_g6/test/hal_test_module.c b/phl/hal_g6/test/hal_test_module.c new file mode 100644 index 0000000..a22650c --- /dev/null +++ b/phl/hal_g6/test/hal_test_module.c @@ -0,0 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MODULE_C_ + +#ifdef CONFIG_HAL_TEST_SUITE +#endif /*ifdef CONFIG_HAL_TEST_SUITE*/ diff --git a/phl/hal_g6/test/mp/hal_test_mp.c b/phl/hal_g6/test/mp/hal_test_mp.c new file mode 100644 index 0000000..6eff541 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp.c @@ -0,0 +1,34 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" +#include "hal_test_mp_api.h" + + +#ifdef CONFIG_HAL_TEST_MP + +void rtw_hal_mp_cfg(struct rtw_phl_com_t *phl_com, void *hal) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + + if (true == phl_is_mp_mode(phl_com)) + hal_ops->hal_mp_init(phl_com, hal_info); + else + hal_ops->hal_mp_deinit(phl_com, hal_info); +} + +#endif /* CONFIG_HAL_TEST_MP */ \ No newline at end of file diff --git a/phl/hal_g6/test/mp/hal_test_mp_api.h b/phl/hal_g6/test/mp/hal_test_mp_api.h new file mode 100644 index 0000000..e94f414 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_api.h @@ -0,0 +1,255 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _HAL_TEST_MP_H_ +#define _HAL_TEST_MP_H_ + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_cal_trigger( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_set_capability( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_get_capability( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_get_tssi_de( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_set_tssi_de( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_get_txpwr_final_abs( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_cal_trigger_dpk_tracking( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_set_tssi_avg( + struct mp_context *mp, struct mp_cal_arg *arg); +/* PSD */ +enum rtw_hal_status rtw_hal_mp_psd_init( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_psd_restore( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_psd_get_point_data( + struct mp_context *mp, struct mp_cal_arg *arg); +enum rtw_hal_status rtw_hal_mp_psd_query( + struct mp_context *mp, struct mp_cal_arg *arg); + +enum rtw_hal_status rtw_hal_mp_config_start_dut( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_get_dev_info( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_set_phy_idx( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_get_bw_mode( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_set_trx_path( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_reset_phy_cnt( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_config_reset_mac_cnt( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_config_reset_drv_cnt( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_config_set_modulation( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_get_modulation( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_set_rate( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_get_mac_addr( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_set_mac_addr( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_set_ch_bw( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_config_swith_btc_path( + struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_trigger_fw_conflict(struct mp_context *mp, struct mp_config_arg *arg); +enum rtw_hal_status rtw_hal_mp_ic_hw_setting_init( + struct mp_context *mp); +/* WIFI EFUSE */ +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_read( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_write( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_update( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_reload( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_offset_mask( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_usage( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_log_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_get_avl_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_get_shadowmap_from_val( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_autoload_status( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_shadow2buf( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_file_map_load( + struct mp_context *mp, char *pfilepath); +enum rtw_hal_status rtw_hal_mp_efuse_file_mask_load( + struct mp_context *mp, char *pfilepath); +enum rtw_hal_status rtw_hal_mp_efuse_get_info( + struct mp_context *mp, struct mp_efuse_arg *arg); + +/* BT EFUSE */ +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_read( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_write( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_update( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_reload( + struct mp_context *mp); +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_offset_mask( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_usage( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_log_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_avl_size( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow2buf( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_file_map_load( + struct mp_context *mp, char *pfilepath); +enum rtw_hal_status rtw_hal_mp_efuse_bt_file_mask_load( + struct mp_context *mp, char *pfilepath); +enum rtw_hal_status rtw_hal_mp_efuse_bt_read_hidden( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_bt_write_hidden( + struct mp_context *mp, struct mp_efuse_arg *arg); +enum rtw_hal_status rtw_hal_mp_efuse_read_phy_map( + struct mp_context *mp, struct mp_efuse_arg *arg, u8 type); +enum rtw_hal_status rtw_hal_mp_efuse_renew( + struct mp_context *mp, struct mp_efuse_arg *arg, u8 type); + +enum rtw_hal_status rtw_hal_mp_reg_read_macreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_write_macreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_read_rfreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_write_rfreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_read_rf_syn( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_write_rf_syn( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_read_bbreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_write_bbreg( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_get_xcap( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_set_xcap( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_get_xsi( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_reg_set_xsi( + struct mp_context *mp, struct mp_reg_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_phy_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_phy_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_mac_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_mac_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_drv_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_drv_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_get_rssi( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_get_rssi_ex( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_get_rxevm( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_trigger_rxevm( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_rx_set_gain_offset( + struct mp_context *mp, struct mp_rx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_plcp_gen( + struct mp_context *mp, struct mp_tx_arg *arg,struct mp_plcp_param_t *plcp_tx_struct); +enum rtw_hal_status rtw_hal_mp_tx_pmac_packet( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_pmac_continuous( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_pmac_fw_trigger( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_single_tone( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_carrier_suppression( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_phy_ok_cnt( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_mode_switch( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_tx_f2p_cmd( + struct mp_context *mp, struct mp_tx_arg *arg, struct mp_mac_ax_f2p_test_para *f2p_para_struct, + struct mp_mac_ax_f2p_wd *f2p_wd_struct, struct mp_mac_ax_f2p_tx_cmd *f2p_tx_cmd_struct); +void rtw_hal_mp_check_tx_idle( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_set_dpd_bypass( + struct mp_context *mp, struct mp_tx_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_read_table( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwrtrack( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwrtrack( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_idx( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr_idx( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_thermal( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_tssi( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_online_tssi_de( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_set_pwr_lmt_en( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_get_pwr_lmt_en( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi_offset( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref_cw( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_get_txinfo_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg); +enum rtw_hal_status rtw_hal_mp_txpwr_ctrl_rf_mode( + struct mp_context *mp, struct mp_txpwr_arg *arg); +void rtw_hal_mp_set_tx_pow_patten_sharp( + struct mp_context *mp, struct mp_txpwr_arg *arg); + +void rtw_hal_mp_cfg(struct rtw_phl_com_t *phl_com, void *hal); +#endif /* CONFIG_HAL_TEST_MP */ + +#endif /* _HAL_TEST_MP_H_ */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_cal.c b/phl/hal_g6/test/mp/hal_test_mp_cal.c new file mode 100644 index 0000000..2235f0b --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_cal.c @@ -0,0 +1,285 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_CAL_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_cal_trigger( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: cal_type = %d. \n",__FUNCTION__, arg->cal_type); + + switch(arg->cal_type){ + case MP_CAL_CHL_RFK: + PHL_INFO("MP_CAL_CHL_RFK: cur_phy_idx = %d.\n", mp->cur_phy); + hal_status = rtw_hal_rf_chl_rfk_trigger(mp->hal, mp->cur_phy, false); + break; + case MP_CAL_DACK: + PHL_INFO("MP_CAL_DACK: . \n"); + hal_status = rtw_hal_rf_dack_trigger(mp->hal, false); + break; + case MP_CAL_IQK: + PHL_INFO("MP_CAL_IQK: cur_phy_idx = %d.\n", mp->cur_phy); + hal_status = rtw_hal_rf_iqk_trigger(mp->hal, mp->cur_phy, false); + break; + case MP_CAL_LCK: + PHL_INFO("MP_CAL_LCK \n"); + hal_status = rtw_hal_rf_lck_trigger(mp->hal); + break; + case MP_CAL_DPK: + PHL_INFO("MP_CAL_DPK: cur_phy_idx = %d.\n", mp->cur_phy); + hal_status = rtw_hal_rf_dpk_trigger(mp->hal, mp->cur_phy, false); + break; + case MP_CAL_TSSI: + PHL_INFO("MP_CAL_TSSI: cur_phy_idx = %d.\n", mp->cur_phy); + hal_status = rtw_hal_rf_tssi_trigger(mp->hal, mp->cur_phy); + break; + case MP_CAL_GAPK: + PHL_INFO("MP_CAL_GAPK: cur_phy_idx = %d.\n", mp->cur_phy); + hal_status = rtw_hal_rf_gapk_trigger(mp->hal, mp->cur_phy, false); + break; + default: + PHL_INFO("Unknown calibration type.\n"); + break; + } + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_set_capability( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: cal_type = %d, enable = %d\n", + __FUNCTION__, arg->cal_type, arg->enable); + + switch(arg->cal_type){ + case MP_CAL_DACK: + PHL_INFO("MP_CAL_DACK.\n"); + hal_status = rtw_hal_rf_set_capability_dack(mp->hal, + arg->enable); + break; + case MP_CAL_IQK: + PHL_INFO("MP_CAL_IQK.\n"); + hal_status = rtw_hal_rf_set_capability_iqk(mp->hal, + arg->enable); + break; + case MP_CAL_DPK: + PHL_INFO("MP_CAL_DPK.\n"); + hal_status = rtw_hal_rf_set_capability_dpk(mp->hal, + arg->enable); + break; + case MP_CAL_DPK_TRACK: + PHL_INFO("MP_CAL_DPK_TRACK.\n"); + hal_status = rtw_hal_rf_set_capability_dpk_track(mp->hal, + arg->enable); + break; + case MP_CAL_TSSI: + PHL_INFO("MP_CAL_TSSI.\n"); + hal_status = rtw_hal_rf_set_capability_tssi(mp->hal, + arg->enable); + break; + case MP_CAL_GAPK: + PHL_INFO("MP_CAL_GAPK.\n"); + hal_status = rtw_hal_rf_set_capability_gapk(mp->hal, + arg->enable); + break; + default: + PHL_INFO("Unknown calibration type.\n"); + break; + } + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_get_capability( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: cal_type = %d. \n",__FUNCTION__,arg->cal_type); + + switch(arg->cal_type){ + case MP_CAL_DACK: + PHL_INFO("MP_CAL_DACK.\n"); + hal_status = rtw_hal_rf_get_capability_dack(mp->hal, + &arg->enable); + break; + case MP_CAL_IQK: + PHL_INFO("MP_CAL_IQK.\n"); + hal_status = rtw_hal_rf_get_capability_iqk(mp->hal, + &arg->enable); + break; + case MP_CAL_DPK: + PHL_INFO("MP_CAL_DPK.\n"); + hal_status = rtw_hal_rf_get_capability_dpk(mp->hal, + &arg->enable); + break; + case MP_CAL_DPK_TRACK: + PHL_INFO("MP_CAL_DPK_TRACK.\n"); + hal_status = rtw_hal_rf_get_capability_dpk_track(mp->hal, + &arg->enable); + break; + case MP_CAL_TSSI: + PHL_INFO("MP_CAL_TSSI.\n"); + hal_status = rtw_hal_rf_get_capability_tssi(mp->hal, + &arg->enable); + break; + case MP_CAL_GAPK: + PHL_INFO("MP_CAL_GAPK.\n"); + hal_status = rtw_hal_rf_get_capability_gapk(mp->hal, + &arg->enable); + break; + default: + PHL_INFO("Unknown calibration type.\n"); + break; + } + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_get_tssi_de( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + /*hal_status = rtw_hal_rf_get_tssi_de_value(mp, arg);*/ + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_set_tssi_de( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + /*hal_status = rtw_hal_rf_set_tssi_de_tx_verify(mp->hal, arg);*/ + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_get_txpwr_final_abs( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + /*hal_status = rtw_hal_rf_get_txpwr_final_abs(mp->hal, arg);*/ + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_cal_trigger_dpk_tracking( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_trigger_dpk_tracking(mp->hal); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_set_tssi_avg( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_set_tssi_avg(mp->hal, mp->cur_phy, arg->xdbm); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +/* PSD */ + +enum rtw_hal_status rtw_hal_mp_psd_init( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_psd_init(mp->hal, mp->cur_phy, arg->path, + arg->iq_path, arg->avg, arg->fft); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} +enum rtw_hal_status rtw_hal_mp_psd_restore( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_psd_restore(mp->hal, mp->cur_phy); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} +enum rtw_hal_status rtw_hal_mp_psd_get_point_data( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_psd_get_point_data(mp->hal, mp->cur_phy, + arg->point, &arg->buf); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} +enum rtw_hal_status rtw_hal_mp_psd_query( + struct mp_context *mp, struct mp_cal_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_psd_query(mp->hal, mp->cur_phy, arg->upoint, + arg->start_point, arg->stop_point, arg->outbuf); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_config.c b/phl/hal_g6/test/mp/hal_test_mp_config.c new file mode 100644 index 0000000..c22f521 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_config.c @@ -0,0 +1,409 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_CONFIG_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_config_start_dut( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__); + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_get_dev_info( + struct mp_context *mp, struct mp_config_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + arg->bustype = 0; + // arg->bustype = mp->phl_com->hci_type; + + switch(hal_info->hal_com->chip_id) { + case CHIP_WIFI6_8852A: + arg->chipid = 0x8852a; + break; + case CHIP_WIFI6_8834A: + arg->chipid = 0x8834a; + break; + case CHIP_WIFI6_8852B: + arg->chipid = 0x8852b; + break; + case CHIP_WIFI6_MAX: + default: + PHL_INFO("Unknown chip: %d\n", hal_info->hal_com->chip_id); + return RTW_HAL_STATUS_FAILURE; + break; + } + + PHL_INFO("%s: bustype = 0x%x, chipid = 0x%x\n", + __FUNCTION__, arg->bustype, arg->chipid); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_config_set_phy_idx( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + PHL_INFO("%s: phy index = 0x%x\n", __FUNCTION__, arg->cur_phy); + + mp->cur_phy = arg->cur_phy; + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_get_bw_mode( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + /* call hal api*/ + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_set_trx_path( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct rtw_phl_com_t *phl_com = mp->phl_com; + + u8 bb_rx_path, bb_tx_path = 0; + + PHL_INFO("%s: ant_tx=0x%x, ant_rx=0x%x\n", + __FUNCTION__, arg->ant_tx, arg->ant_rx); + + if((hal_info->hal_com->chip_id == CHIP_WIFI6_8852A) && + (phl_com->phy_cap[mp->cur_phy].txss == 1)) { + if(arg->ant_tx != RF_PATH_B){ + hal_status = RTW_HAL_STATUS_FAILURE; + PHL_INFO("%s: Invaled TX path (%d)\n", + __FUNCTION__, arg->ant_tx); + goto exit; + } + } + + bb_tx_path = arg->ant_tx; /* warning !!! it should be convert to enum bb_path, to be discussed */ + bb_rx_path = arg->ant_rx; /* warning !!! it should be convert to enum bb_path, to be discussed */ + + hal_status = rtw_hal_bb_cfg_tx_path(hal_info->hal_com, bb_tx_path); + if(hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_INFO("%s: rtw_hal_bb_cfg_tx_path fail (%x)\n", + __FUNCTION__, hal_status); + goto exit; + } + + hal_status = rtw_hal_bb_cfg_rx_path(hal_info->hal_com, bb_rx_path); + if(hal_status != RTW_HAL_STATUS_SUCCESS){ + PHL_INFO("%s: rtw_hal_bb_cfg_rx_path fail (%x)\n", + __FUNCTION__, hal_status); + goto exit; + } + +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_reset_phy_cnt( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s !\n", __FUNCTION__); + + hal_status = rtw_hal_bb_set_reset_cnt(mp->hal); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_reset_mac_cnt( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s !\n", __FUNCTION__); + + hal_status = rtw_hal_mac_set_reset_rx_cnt(mp->hal, mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_reset_drv_cnt( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_trx_stat *trx_stat = &hal_com->trx_stat; + + PHL_INFO("%s !\n", __FUNCTION__); + + trx_stat->rx_ok_cnt = 0; + trx_stat->rx_err_cnt = 0; + hal_status = RTW_HAL_STATUS_SUCCESS; + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_set_modulation( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("set modulation = 0x%x\n", arg->modulation); + /* need assign arg->modulation to driver current wirelessmode */ + + PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__); + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_get_modulation( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__); + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_set_rate( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__); + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_get_mac_addr( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 mac_addr[6] = {0x00, 0xE0, 0x4C, 0xbb, 0xbb, 0xbb}; + + PHL_INFO("%s: NOT READY!!! Assign fixed mac address.\n", __FUNCTION__); + _os_mem_cpy(mp->phl_com->drv_priv, arg->mac_addr, mac_addr, 6); + hal_status = RTW_HAL_STATUS_SUCCESS; + + /* [TEMP] need assign driver mac addr to arg->mac_addr */ + PHL_INFO("%s: get mac addr = %x:%x:%x:%x:%x:%x\n", __FUNCTION__, + arg->mac_addr[0],arg->mac_addr[1],arg->mac_addr[2], + arg->mac_addr[3],arg->mac_addr[4],arg->mac_addr[5]); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_set_mac_addr( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 mac_addr[6] = {0}; + + PHL_INFO("%s: NOT READY!!! ignore it.\n", __FUNCTION__); + _os_mem_cpy(mp->phl_com->drv_priv, mac_addr, arg->mac_addr, 6); + hal_status = RTW_HAL_STATUS_SUCCESS; + + /* [TEMP] need assign arg->mac_addr to driver mac addr */ + PHL_INFO("%s: set mac addr = %x:%x:%x:%x:%x:%x\n", __FUNCTION__, + mac_addr[0],mac_addr[1],mac_addr[2], + mac_addr[3],mac_addr[4],mac_addr[5]); + + return hal_status; +} + +u8 hal_mp_primary_channel_decision(u8 cent_ch, enum channel_width bw, u8 tx_sc) +{ + u8 pri_ch = 0; + + if(bw == CHANNEL_WIDTH_20){ + pri_ch = cent_ch; + } + else if(bw == CHANNEL_WIDTH_40){ + if(tx_sc == 1) + pri_ch = cent_ch + 2; + else if(tx_sc == 2) + pri_ch = cent_ch - 2; + else + pri_ch = cent_ch - 2; /* tx_sc == 0 */ + } + else if(bw == CHANNEL_WIDTH_80){ + if((tx_sc == 10) || (tx_sc == 4)) + pri_ch = cent_ch - 6; + else if((tx_sc == 9) || (tx_sc == 1)) + pri_ch = cent_ch + 2; + else if(tx_sc == 2) + pri_ch = cent_ch - 2; + else if(tx_sc == 3) + pri_ch = cent_ch + 6; + else + pri_ch = cent_ch - 6; /* tx_sc == 0 */ + } + else{ + PHL_WARN("%s: 80+80 and 160 not consider yet!\n", __FUNCTION__); + } + + return pri_ch; +} + +enum chan_offset +hal_mp_chan_offset_decision(u8 pri_ch, u8 cent_ch, enum channel_width bw) +{ + enum chan_offset offset = CHAN_OFFSET_NO_EXT; + + if(bw == CHANNEL_WIDTH_20){ + offset = CHAN_OFFSET_NO_EXT; + } + else if(bw == CHANNEL_WIDTH_40){ + if(cent_ch > pri_ch) + offset = CHAN_OFFSET_UPPER; + else + offset = CHAN_OFFSET_LOWER; + } + else if(bw == CHANNEL_WIDTH_80){ + if(cent_ch > pri_ch){ + if((cent_ch - pri_ch) == 6) + offset = CHAN_OFFSET_UPPER; + else + offset = CHAN_OFFSET_LOWER; + } + else{ + if((pri_ch - cent_ch) == 6) + offset = CHAN_OFFSET_LOWER; + else + offset = CHAN_OFFSET_UPPER; + } + } + else{ + PHL_WARN("%s: 80+80 and 160 not consider yet!\n", __FUNCTION__); + } + return offset; +} + +enum rtw_hal_status rtw_hal_mp_config_set_ch_bw( + struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 pri_chan = 0; + u8 cent_ch = arg->channel; + u8 tx_sc = arg->sc_idx; + struct rtw_chan_def chdef = {0}; + enum channel_width bw = arg->bandwidth; + + PHL_INFO("%s: phy index = %d.\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: central channel = %d.\n", __FUNCTION__, arg->channel); + PHL_INFO("%s: bandwith = %d.\n", __FUNCTION__, arg->bandwidth); + PHL_INFO("%s: sc_idx = %d.\n", __FUNCTION__, arg->sc_idx); + + pri_chan = hal_mp_primary_channel_decision(cent_ch, bw, tx_sc); + + if(pri_chan == 0){ + PHL_ERR("%s Invalid primary channel!\n", __FUNCTION__); + hal_status = RTW_HAL_STATUS_FAILURE; + goto exit; + } + + chdef.chan = pri_chan; + chdef.band = rtw_phl_get_band_type(pri_chan); + chdef.bw = bw; + chdef.offset = hal_mp_chan_offset_decision(pri_chan, cent_ch, bw); + + PHL_INFO("%s: pri_ch(%d) bw(%d) offset(%d)\n", + __FUNCTION__, chdef.chan, chdef.bw, chdef.offset); + + hal_status = rtw_hal_set_ch_bw(mp->hal,mp->cur_phy, + &chdef, false); + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Set ch bw fail!\n", __FUNCTION__); + goto exit; + } + + hal_status = rtw_hal_bb_set_txsc(mp->hal, arg->sc_idx, mp->cur_phy); + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s Set txsc fail!\n", __FUNCTION__); + goto exit; + } + + hal_status = rtw_hal_rf_chl_rfk_trigger(mp->hal, mp->cur_phy, false); + if(hal_status != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s chl rfk fail!\n", __FUNCTION__); + goto exit; + } + +exit: + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_config_swith_btc_path( + struct mp_context *mp, struct mp_config_arg *arg) +{ + mp->phl_com->dev_cap.btc_mode = arg->btc_mode; + mp->phl_com->dev_sw_cap.btc_mode = arg->btc_mode; + + PHL_INFO("%s: btc_mode = %d.\n", __FUNCTION__, arg->btc_mode); + PHL_INFO("%s: phl_com->dev_sw_cap.btc_mode = %d.\n", __FUNCTION__, mp->phl_com->dev_sw_cap.btc_mode); + +#ifdef CONFIG_BTCOEX + rtw_hal_btc_init_coex_cfg_ntfy(mp->hal); +#endif + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_trigger_fw_conflict(struct mp_context *mp, struct mp_config_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: offset = %d.\n", __FUNCTION__, arg->offset); + + hal_status = rtw_hal_mac_trigger_fw_conflict(mp->hal, arg->offset, arg->voltag); + + return hal_status; +} + + +enum rtw_hal_status rtw_hal_mp_ic_hw_setting_init(struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + hal_status = rtw_hal_bb_ic_hw_setting_init(mp->hal); + + return hal_status; +} + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_efuse.c b/phl/hal_g6/test/mp/hal_test_mp_efuse.c new file mode 100644 index 0000000..f21d5e0 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_efuse.c @@ -0,0 +1,496 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_EFUSE_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP + +/* WIFI EFUSE */ +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_read( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset); + + hal_status = rtw_hal_efuse_shadow_read(mp->hal, + arg->io_type, + arg->io_offset, + &arg->io_value, + true); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_write( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value); + + hal_status = rtw_hal_efuse_shadow_write(mp->hal, + arg->io_type, + arg->io_offset, + arg->io_value, + true); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_update( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + /* PG limit part of logical efuse map in MP*/ + hal_status = rtw_hal_efuse_shadow_update(mp->hal, true); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_reload( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + /* Reload limit part of logical efuse map in MP*/ + hal_status = rtw_hal_efuse_shadow_load(mp->hal, true); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_offset_mask( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_offset_mask(mp->hal, + arg->io_offset, + (u8 *)&arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: wifi offset mask = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_usage( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_usage(mp->hal, (u32 *)&arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: wifi usage(bytes/percentage) = %d\n", + __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_log_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_logical_size(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: wifi logical size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_size(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: wifi size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_get_avl_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_avl(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: available size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_get_shadowmap_from_val( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_shadowmap_from(mp->hal, (u8*)&arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: val=%d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_autoload_status( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_check_efuse_autoload(mp->hal, &arg->autoload); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: autoload status = %d\n", __FUNCTION__, arg->autoload); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_shadow2buf( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + if (arg->poutbuf != NULL && arg->buf_len != 0) + hal_status = rtw_hal_efuse_shadow2buf(mp->hal, arg->poutbuf, arg->buf_len); + else + PHL_INFO("%s: buf null, buf len = %d\n", __FUNCTION__, arg->buf_len); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_file_map_load( + struct mp_context *mp, char *pfilepath) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + if (pfilepath) + hal_status = rtw_hal_efuse_file_map_load(mp->hal, pfilepath, true); + else + PHL_INFO("%s: pfilepath null\n", __FUNCTION__); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_file_mask_load( + struct mp_context *mp, char *pfilepath) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + if (pfilepath) + hal_status = rtw_hal_efuse_file_mask_load(mp->hal, pfilepath, true); + else + PHL_INFO("%s: pfilepath null\n", __FUNCTION__); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_get_info( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_get_info(hal_info->hal_com, + arg->io_type, + arg->poutbuf, + (u8)arg->buf_len); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +/* BT EFUSE */ +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_read( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset); + + hal_status = rtw_hal_efuse_bt_shadow_read(mp->hal, + arg->io_type, + arg->io_offset, + &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_write( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value); + + hal_status = rtw_hal_efuse_bt_shadow_write(mp->hal, + arg->io_type, + arg->io_offset, + arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_update( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_shadow_update(mp->hal); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_reload( + struct mp_context *mp) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_shadow_load(mp->hal); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_offset_mask( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_get_offset_mask(mp->hal, + arg->io_offset, + (u8 *)&arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: bt offset mask = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_usage( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_get_usage(mp->hal, (u32 *)&arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: bt usage(bytes/percentage) = %d\n", + __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_log_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_get_logical_size(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: bt logical size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_get_size(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: bt size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow2buf( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + if (arg->poutbuf != NULL && arg->buf_len != 0) + hal_status = rtw_hal_efuse_bt_shadow2buf(mp->hal, arg->poutbuf, arg->buf_len); + else + PHL_INFO("%s: buf null, buf len = %d\n", __FUNCTION__, arg->buf_len); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_get_avl_size( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_bt_get_avl(mp->hal, &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: bt available size = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_file_map_load( + struct mp_context *mp, char *pfilepath) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + if (pfilepath) + hal_status = rtw_hal_efuse_bt_file_map_load(mp->hal, pfilepath); + else + PHL_INFO("%s: pfilepath null\n", __FUNCTION__); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_file_mask_load( + struct mp_context *mp, char *pfilepath) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + if (pfilepath) + hal_status = rtw_hal_efuse_bt_file_mask_load(mp->hal, pfilepath); + else + PHL_INFO("%s: pfilepath null\n", __FUNCTION__); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_read_hidden( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + u8 value = (u8)arg->io_value; + + PHL_INFO("%s\n", __FUNCTION__); + PHL_INFO("%s: offset = %x size = %x\n", __FUNCTION__, arg->io_offset, arg->io_type); + + hal_status = rtw_hal_efuse_bt_read_hidden(mp->hal, arg->io_offset, arg->io_type, + &value); + arg->io_value = value; + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: io_value = %d\n", __FUNCTION__, arg->io_value); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_bt_write_hidden( + struct mp_context *mp, struct mp_efuse_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + PHL_INFO("%s: offset = %x value = %x\n", __FUNCTION__, arg->io_offset, arg->io_value); + + hal_status = rtw_hal_efuse_bt_write_hidden(mp->hal,arg->io_offset, + (u8)arg->io_value); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_read_phy_map( + struct mp_context *mp, struct mp_efuse_arg *arg, u8 type) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + PHL_INFO("%s: offset = %x size = %x\n", __FUNCTION__, arg->io_offset, arg->buf_len); + + hal_status = rtw_hal_efuse_read_phy_efuse(mp->hal, arg->io_offset, arg->buf_len, + arg->poutbuf, type); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_efuse_renew( + struct mp_context *mp, struct mp_efuse_arg *arg, u8 type) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_efuse_renew(mp->hal, type); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + return hal_status; +} + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_reg.c b/phl/hal_g6/test/mp/hal_test_mp_reg.c new file mode 100644 index 0000000..4679ea2 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_reg.c @@ -0,0 +1,311 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_REG_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_reg_read_macreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + arg->io_value = hal_ops->read_macreg(mp->hal, + arg->io_offset, + convert_mask); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_write_macreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + hal_ops->write_macreg(mp->hal, arg->io_offset, + convert_mask, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_read_rfreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: rfpath = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %x\n", __FUNCTION__, arg->io_offset); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + arg->io_value = hal_ops->read_rfreg(mp->hal, arg->rfpath, + arg->io_offset, convert_mask); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_write_rfreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: rfpath = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + hal_ops->write_rfreg(mp->hal, arg->rfpath, arg->io_offset, + convert_mask, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_read_rf_syn( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + + PHL_INFO("[MP] call hal api: not ready\n"); + hal_status = RTW_HAL_STATUS_SUCCESS; + /* + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + */ + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_reg_write_rf_syn( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + PHL_INFO("[MP] call hal api: not ready\n"); + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_reg_read_bbreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + arg->io_value = hal_ops->read_bbreg(mp->hal, + arg->io_offset, + convert_mask); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_write_bbreg( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct hal_ops_t *hal_ops = hal_get_ops(hal_info); + u32 convert_mask = 0x0; + + PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type); + PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset); + PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value); + + switch(arg->io_type){ + case 1: + convert_mask = 0x000000ff; + break; + case 2: + convert_mask = 0x0000ffff; + break; + case 4: + convert_mask = 0xffffffff; + break; + default: + PHL_INFO("io_type error\n"); + return RTW_HAL_STATUS_FAILURE; + } + + hal_ops->write_bbreg(mp->hal, arg->io_offset, + convert_mask, arg->io_value); + + return RTW_HAL_STATUS_SUCCESS; +} + +enum rtw_hal_status rtw_hal_mp_reg_get_xcap( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_get_xcap(hal_info->hal_com, arg->sc_xo, + &arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: xcap capability = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_reg_set_xcap( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: xcap capability = %d\n", __FUNCTION__, arg->io_value); + + hal_status = rtw_hal_mac_set_xcap(hal_info->hal_com, arg->sc_xo, + arg->io_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_reg_get_xsi( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_get_xsi(hal_info->hal_com, + arg->xsi_offset, + &arg->xsi_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: xsi = %d\n", __FUNCTION__, arg->io_value); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_reg_set_xsi( + struct mp_context *mp, struct mp_reg_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: xsi = %d\n", __FUNCTION__, arg->io_value); + + hal_status = rtw_hal_mac_set_xsi(hal_info->hal_com, + arg->xsi_offset, + arg->xsi_value); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_rx.c b/phl/hal_g6/test/mp/hal_test_mp_rx.c new file mode 100644 index 0000000..b43206d --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_rx.c @@ -0,0 +1,203 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_RX_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_rx_phy_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + + hal_status = rtw_hal_bb_get_rx_ok(mp->hal, + mp->cur_phy, &arg->rx_ok); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: crc ok count = %d\n", __FUNCTION__, arg->rx_ok); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_phy_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + + hal_status = rtw_hal_bb_get_rx_crc(mp->hal, mp->cur_phy, &arg->rx_err); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: crc error count = %d\n", __FUNCTION__, arg->rx_err); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_mac_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_get_rx_cnt(mp->hal, mp->cur_phy, MAC_AX_RX_CRC_OK, &arg->rx_ok); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: mac crc OK count = %d\n", __FUNCTION__, arg->rx_ok); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_mac_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_get_rx_cnt(mp->hal, mp->cur_phy, MAC_AX_RX_CRC_FAIL, &arg->rx_err); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: mac crc error count = %d\n", __FUNCTION__, arg->rx_err); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_drv_crc_ok( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_trx_stat *trx_stat = &hal_com->trx_stat; + + PHL_INFO("%s\n", __FUNCTION__); + + arg->rx_ok = trx_stat->rx_ok_cnt; + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: drv ok count = %d\n", __FUNCTION__, arg->rx_ok); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_drv_crc_err( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + struct rtw_trx_stat *trx_stat = &hal_com->trx_stat; + + PHL_INFO("%s\n", __FUNCTION__); + + arg->rx_err = trx_stat->rx_err_cnt; + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: drv err count = %d\n", __FUNCTION__, arg->rx_err); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_get_rssi( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rx_path: %d\n", __FUNCTION__, arg->rx_path); + + hal_status = rtw_hal_bb_get_rssi(mp->hal, arg->rx_path, &arg->rssi); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: rssi = %d\n", __FUNCTION__, arg->rssi); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_get_rssi_ex( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rx_path: %d\n", __FUNCTION__, arg->rx_path); + + hal_status = rtw_hal_bb_get_rssi_ex(mp->hal, arg->rx_path, &arg->rssi_ex, mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_get_rxevm( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + + hal_status = rtw_hal_bb_get_rxevm(mp->hal, arg->user, arg->strm, arg->rxevm_table, &arg->rx_evm); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: rx_evm = %d\n", __FUNCTION__, arg->rx_evm); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_trigger_rxevm( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + + hal_status = rtw_hal_bb_trigger_rxevm(mp->hal, mp->cur_phy, + &arg->phy0_user0_rxevm, &arg->phy0_user1_rxevm, &arg->phy0_user2_rxevm, &arg->phy0_user3_rxevm, + &arg->phy1_user0_rxevm, &arg->phy1_user1_rxevm, &arg->phy1_user2_rxevm, &arg->phy1_user3_rxevm); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + PHL_INFO("%s: phy0_user0_rxevm = %d\n", __FUNCTION__, arg->phy0_user0_rxevm); + PHL_INFO("%s: phy0_user1_rxevm = %d\n", __FUNCTION__, arg->phy0_user1_rxevm); + PHL_INFO("%s: phy0_user2_rxevm = %d\n", __FUNCTION__, arg->phy0_user2_rxevm); + PHL_INFO("%s: phy0_user3_rxevm = %d\n", __FUNCTION__, arg->phy0_user3_rxevm); + + PHL_INFO("%s: phy1_user0_rxevm = %d\n", __FUNCTION__, arg->phy1_user0_rxevm); + PHL_INFO("%s: phy1_user1_rxevm = %d\n", __FUNCTION__, arg->phy1_user1_rxevm); + PHL_INFO("%s: phy1_user2_rxevm = %d\n", __FUNCTION__, arg->phy1_user2_rxevm); + PHL_INFO("%s: phy1_user3_rxevm = %d\n", __FUNCTION__, arg->phy1_user3_rxevm); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_rx_set_gain_offset( + struct mp_context *mp, struct mp_rx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + + PHL_INFO("%s: offset: %d\n", __FUNCTION__, arg->offset); + PHL_INFO("%s: rf_path: %d\n", __FUNCTION__, arg->rf_path); + + hal_status = rtw_hal_bb_set_gain_offset(mp->hal, arg->offset, arg->rf_path, mp->cur_phy, arg->iscck); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_tx.c b/phl/hal_g6/test/mp/hal_test_mp_tx.c new file mode 100644 index 0000000..b8da533 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_tx.c @@ -0,0 +1,211 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _HAL_TEST_MP_TX_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_tx_plcp_gen( + struct mp_context *mp, struct mp_tx_arg *arg, struct mp_plcp_param_t *plcp_tx_struct) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + hal_status = rtw_hal_bb_set_plcp_tx(hal_info->hal_com, + plcp_tx_struct, + mp->usr, + mp->cur_phy, + &arg->plcp_sts); + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_pmac_packet( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx); + PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck); + PHL_INFO("%s: tx count: %d\n", __FUNCTION__, arg->tx_cnt); + PHL_INFO("%s: period: %d\n", __FUNCTION__, arg->period); + PHL_INFO("%s: tx time: %d\n", __FUNCTION__, arg->tx_time); + + hal_status = rtw_hal_bb_set_pmac_packet_tx(hal_info->hal_com, + arg->start_tx, + arg->is_cck, + arg->tx_cnt, + arg->period, + arg->tx_time, + mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_pmac_continuous( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx); + PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck); + + hal_status = rtw_hal_bb_set_pmac_cont_tx(hal_info->hal_com, + arg->start_tx, + arg->is_cck, + mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_pmac_fw_trigger( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx); + PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck); + PHL_INFO("%s: tx count: %d\n", __FUNCTION__, arg->tx_cnt); + PHL_INFO("%s: tx duty: %d\n", __FUNCTION__, arg->tx_time); + + hal_status = rtw_hal_bb_set_pmac_fw_trigger_tx(hal_info->hal_com, + arg->start_tx, + arg->is_cck, + arg->tx_cnt, + (u8)arg->tx_time, + mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + + + +enum rtw_hal_status rtw_hal_mp_tx_single_tone( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx); + PHL_INFO("%s: rf path: %d\n", __FUNCTION__, arg->tx_path); + + hal_status = rtw_hal_rf_set_singletone_tx(mp->hal, + arg->start_tx, + arg->tx_path); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_carrier_suppression( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_set_suppression_tx(mp->hal); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_phy_ok_cnt( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + /* + hal_status = rtw_hal_bb_get_tx_ok(phl_info->hal, + mp->cur_phy, &arg->tx_ok); + */ + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: phy ok cnt = %d\n", __FUNCTION__, arg->tx_ok); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_mode_switch( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s\n", __FUNCTION__); + + /* mode: 0 = tmac, 1 = pmac */ + hal_status = rtw_hal_bb_tx_mode_switch(hal_info->hal_com, mp->cur_phy, arg->tx_mode); + + hal_status = RTW_HAL_STATUS_SUCCESS; + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: tx_mode = %d\n", __FUNCTION__, arg->tx_mode); + PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy); + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_tx_f2p_cmd( + struct mp_context *mp, struct mp_tx_arg *arg, struct mp_mac_ax_f2p_test_para *f2p_para_struct, + struct mp_mac_ax_f2p_wd *f2p_wd_struct, struct mp_mac_ax_f2p_tx_cmd *f2p_tx_cmd_struct + ) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + u8 psigb_addr[64] = {0}; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_mac_f2p_test_cmd(hal_info, f2p_para_struct, f2p_wd_struct, f2p_tx_cmd_struct, psigb_addr); + + hal_status = RTW_HAL_STATUS_SUCCESS; + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_set_dpd_bypass( + struct mp_context *mp, struct mp_tx_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy); + PHL_INFO("%s: dpd_bypass: %d\n", __FUNCTION__, arg->dpd_bypass); + + hal_status = rtw_hal_bb_set_dpd_bypass(hal_info->hal_com, + arg->dpd_bypass, + mp->cur_phy); + + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +void rtw_hal_mp_check_tx_idle(struct mp_context *mp, struct mp_tx_arg *arg) +{ + arg->tx_state = rtw_hal_bb_check_tx_idle(mp->hal, mp->cur_phy); +} + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hal_g6/test/mp/hal_test_mp_txpwr.c b/phl/hal_g6/test/mp/hal_test_mp_txpwr.c new file mode 100644 index 0000000..6096697 --- /dev/null +++ b/phl/hal_g6/test/mp/hal_test_mp_txpwr.c @@ -0,0 +1,316 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_TEST_MP_TXPWR_C_ +#include "../../hal_headers.h" +#include "../../../test/mp/phl_test_mp_def.h" + +#ifdef CONFIG_HAL_TEST_MP +enum rtw_hal_status rtw_hal_mp_txpwr_read_table( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: rate = %d\n", __FUNCTION__, arg->rate); + PHL_INFO("%s: bandwidth = %d\n", __FUNCTION__, arg->bandwidth); + PHL_INFO("%s: channel = %d\n", __FUNCTION__, arg->channel); + + hal_status = rtw_hal_rf_read_pwr_table(hal_info->hal_com, arg->rfpath, + arg->rate, arg->bandwidth, + arg->channel, arg->offset, + arg->dcm, arg->beamforming, + &arg->table_item); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwrtrack( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s\n", __FUNCTION__); + + hal_status = rtw_hal_rf_get_pwrtrack(mp->hal, &arg->txpwr_track_status); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: pwr track status = %d\n", __FUNCTION__, + arg->txpwr_track_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwrtrack( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: pwr track status = %d\n", __FUNCTION__, arg->txpwr_track_status); + + hal_status = rtw_hal_rf_set_pwrtrack(mp->hal, mp->cur_phy, arg->txpwr_track_status); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: tx power = %d\n", __FUNCTION__, arg->txpwr); + PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy); + + hal_status = rtw_hal_bb_set_power(hal_info->hal_com, + arg->txpwr, mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy); + + /* Call hal API */ + hal_status = rtw_hal_bb_get_power(hal_info->hal_com, + &arg->txpwr, mp->cur_phy); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: tx power = %d\n", __FUNCTION__, arg->txpwr); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_idx( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: tx path = %d\n", __FUNCTION__, arg->tx_path); + PHL_INFO("%s: is ofdm = %d\n", __FUNCTION__, arg->is_cck); + + hal_status = rtw_hal_bb_get_pwr_index(mp->hal, + &arg->txpwr_index, + arg->tx_path, arg->is_cck); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: tx power index = %d\n", __FUNCTION__, arg->txpwr_index); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr_idx( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: tx path = %d\n", __FUNCTION__, arg->tx_path); + PHL_INFO("%s: is ofdm = %d\n", __FUNCTION__, arg->is_cck); + + hal_status = rtw_hal_bb_set_pwr_index(mp->hal, + arg->txpwr_index, + arg->tx_path, arg->is_cck); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: tx power index = %d\n", __FUNCTION__, arg->txpwr_index); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_thermal( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + + hal_status = rtw_hal_rf_get_thermal(mp->hal, arg->rfpath, &arg->thermal); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: thermal = %d\n", __FUNCTION__, arg->thermal); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: tssi = %d\n", __FUNCTION__, arg->tssi); + + hal_status = rtw_hal_rf_set_tssi(mp->hal, mp->cur_phy, arg->rfpath, arg->tssi); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi_offset( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: tssi_de_offset = %d\n", __FUNCTION__, arg->tssi_de_offset); + + hal_status = rtw_hal_rf_set_tssi_offset(mp->hal, mp->cur_phy,arg->tssi_de_offset,arg->rfpath); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_tssi( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + + hal_status = rtw_hal_rf_get_tssi(mp->hal, mp->cur_phy, arg->rfpath, &arg->tssi); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: tssi = %d\n", __FUNCTION__, arg->tssi); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_online_tssi_de( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath); + PHL_INFO("%s: dbm = %d\n", __FUNCTION__, arg->dbm); + PHL_INFO("%s: pout = %d\n", __FUNCTION__, arg->pout); + + hal_status = rtw_hal_rf_get_online_tssi_de(mp->hal, mp->cur_phy, arg->rfpath, arg->dbm, arg->pout, &arg->online_tssi_de); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: online tssi de = %d\n", __FUNCTION__, arg->online_tssi_de); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_set_pwr_lmt_en( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + struct hal_info_t *hal_info = mp->hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + PHL_INFO("%s: arg pwr_lmt_en = %d\n", __FUNCTION__, arg->pwr_lmt_en); + + hal_status = rtw_hal_mac_set_pwr_lmt_en_val(hal_com, mp->cur_phy, arg->pwr_lmt_en); + PHL_INFO("%s: set_pwr_lmt_en_val status = %d\n", __FUNCTION__, hal_status); + + if (hal_status == RTW_HAL_STATUS_FAILURE) + return hal_status; + hal_status = rtw_hal_mac_write_pwr_limit_en(hal_com, mp->cur_phy); + PHL_INFO("%s:write_pwr_limit_en status = %d\n", __FUNCTION__, hal_status); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_get_pwr_lmt_en( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + struct hal_info_t *hal_info = mp->hal; + struct rtw_hal_com_t *hal_com = hal_info->hal_com; + + PHL_INFO("%s: \n", __FUNCTION__); + arg->pwr_lmt_en = rtw_hal_mac_get_pwr_lmt_en_val(hal_com, mp->cur_phy); + + PHL_INFO("%s: pwr_lmt_en = %d\n", __FUNCTION__, arg->pwr_lmt_en); + + return RTW_HAL_STATUS_SUCCESS; +} + + +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: is cck=%d, tx path = %d\n", __FUNCTION__, + arg->is_cck, arg->tx_path); + + /* Call hal API */ + hal_status = rtw_hal_bb_get_txpwr_ref(mp->hal, + arg->is_cck, + arg->tx_path, + &arg->txpwr_ref); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: txpwr_ref = %d\n", __FUNCTION__, arg->txpwr_ref); + + return hal_status; +} +enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref_cw( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + PHL_INFO("%s: is cck=%d, tx path = %d\n", __FUNCTION__, + arg->is_cck, arg->tx_path); + + /* Call hal API */ + hal_status = rtw_hal_bb_get_pwr_index(mp->hal, + &arg->txpwr_index, + arg->tx_path, + arg->is_cck + ); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: txpwr_ref = %d\n", __FUNCTION__, arg->txpwr_index); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_get_txinfo_pwr( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + /* Call hal API */ + hal_status = rtw_hal_bb_get_txinfo_power(mp->hal, + &arg->txpwr); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: txinfo power = %d\n", __FUNCTION__, arg->txpwr); + + return hal_status; +} + +enum rtw_hal_status rtw_hal_mp_txpwr_ctrl_rf_mode( + struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE; + + /* Call hal API */ + hal_status = rtw_hal_bb_ctrl_rf_mode(mp->hal, + arg->rf_mode); + PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status); + PHL_INFO("%s: rf mode = %d\n", __FUNCTION__, arg->rf_mode); + + return hal_status; +} + +void rtw_hal_mp_set_tx_pow_patten_sharp(struct mp_context *mp, struct mp_txpwr_arg *arg) +{ + struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal; + + rtw_hal_bb_set_pow_patten_sharp(hal_info->hal_com, arg->channel, arg->is_cck, arg->sharp_id, mp->cur_phy); +} + + +#endif /* CONFIG_HAL_TEST_MP */ diff --git a/phl/hci/phl_trx_def_usb.h b/phl/hci/phl_trx_def_usb.h new file mode 100644 index 0000000..75f2f17 --- /dev/null +++ b/phl/hci/phl_trx_def_usb.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_TRX_DEF_USB_H_ +#define _PHL_TRX_DEF_USB_H_ + +/* Release report related format */ +#define WP_TID_INDIC_RESERVED_BIT BIT(14) +#define WP_RESERVED_SEQ 0xFFF +#define WP_MAX_SEQ_NUMBER WP_RESERVED_SEQ +#define TX_STATUS_TX_DONE 0 +#define TX_STATUS_TX_FAIL_REACH_RTY_LMT 1 +#define TX_STATUS_TX_FAIL_LIFETIME_DROP 2 +#define TX_STATUS_TX_FAIL_MACID_DROP 3 +#define TX_STATUS_TX_FAIL_SW_DROP 4 + +/* for tx */ +struct phl_usb_buf { + _os_list list; + u8 *buffer; + u32 buf_len; + u8 type; +}; + + +/* for rx */ +struct rtw_rx_buf { + _os_list list; + u8 *buffer; + u32 buf_len; + u32 transfer_len; + u8 pipe_idx; + + _os_lock lock; // using phl_queue?? + int pktcnt; // for usb aggregation + void *os_priv; +}; + +#endif /* _PHL_TRX_DEF_USB_H_ */ diff --git a/phl/hci/phl_trx_usb.c b/phl/hci/phl_trx_usb.c new file mode 100644 index 0000000..b4764dd --- /dev/null +++ b/phl/hci/phl_trx_usb.c @@ -0,0 +1,2006 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_TRX_USB_C_ +#include "../phl_headers.h" +#include "phl_trx_usb.h" + +#define IDX_NONE (0xffffffff) +#define GET_SHIFT_OFFSET(_bulk_size) \ + ((_bulk_size) == USB_SUPER_SPEED_BULK_SIZE) ? (10) : \ + (((_bulk_size) == USB_HIGH_SPEED_BULK_SIZE) ? (9) : (6)) + +enum rtw_phl_status +phl_release_rxbuf_usb(struct phl_info_t *phl_info, void *r, u8 ch, enum rtw_rx_type type); + +static enum rtw_phl_status enqueue_usb_buf( + struct phl_info_t *phl_info, + struct phl_queue *pool_list, + struct phl_usb_buf *usb_buf, u8 pos) +{ + void *drv = phl_to_drvpriv(phl_info); + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + _os_spinlockfg sp_flags; + + if (usb_buf != NULL) { + _os_spinlock(drv, &pool_list->lock, _irq, &sp_flags); + if (_tail == pos) + list_add_tail(&usb_buf->list, &pool_list->queue); + else if (_first == pos) + list_add(&usb_buf->list, &pool_list->queue); + pool_list->cnt++; + _os_spinunlock(drv, &pool_list->lock, _irq, &sp_flags); + + pstatus = RTW_PHL_STATUS_SUCCESS; + } + + return pstatus; + +} + +static struct phl_usb_buf *dequeue_usb_buf(struct phl_info_t *phl_info, + struct phl_queue *pool_list) +{ + void *drv = phl_to_drvpriv(phl_info); + struct phl_usb_buf *usb_buf = NULL; + _os_spinlockfg sp_flags; + + _os_spinlock(drv, &pool_list->lock, _irq, &sp_flags); + if (list_empty(&pool_list->queue)) { + usb_buf = NULL; + } else { + usb_buf = list_first_entry(&pool_list->queue, struct phl_usb_buf, list); + + list_del(&usb_buf->list); + pool_list->cnt--; + } + _os_spinunlock(drv, &pool_list->lock, _irq, &sp_flags); + return usb_buf; +} + +static void _phl_free_txbuf_usb(struct phl_info_t *phl_info, + struct phl_usb_buf *tx_buf) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (NULL != tx_buf) { + if (tx_buf->buffer) { + _os_kmem_free(drv, tx_buf->buffer, tx_buf->buf_len); + tx_buf->buffer = NULL; + } + _os_mem_free(drv, tx_buf, sizeof(struct phl_usb_buf)); + tx_buf = NULL; + } +} + + +static void _phl_free_txbuf_pool_usb(struct phl_info_t *phl_info, u8 *txbuf_pool) +{ + struct phl_usb_tx_buf_resource *ring = NULL; + struct phl_usb_buf *tx_buf = NULL; + FUNCIN(); + + ring = (struct phl_usb_tx_buf_resource *)txbuf_pool; + if (NULL != ring) { + while (1) { + tx_buf = dequeue_usb_buf(phl_info, &ring->idle_txbuf_list); + if (tx_buf == NULL) + break; + + _phl_free_txbuf_usb(phl_info, tx_buf); + } + while (1) { + tx_buf = dequeue_usb_buf(phl_info, &ring->mgmt_txbuf_list); + if (tx_buf == NULL) + break; + + _phl_free_txbuf_usb(phl_info, tx_buf); + } + while (1) { + tx_buf = dequeue_usb_buf(phl_info, &ring->h2c_txbuf_list); + if (tx_buf == NULL) + break; + + _phl_free_txbuf_usb(phl_info, tx_buf); + } + _os_mem_free(phl_to_drvpriv(phl_info), ring, + sizeof(struct phl_usb_tx_buf_resource)); + ring = NULL; + } + + FUNCOUT(); +} + + +static struct phl_usb_buf * +_phl_alloc_txbuf_usb(struct phl_info_t *phl_info, u32 tx_buf_size) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct phl_usb_buf *tx_buf = NULL; + + tx_buf = _os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(struct phl_usb_buf)); + if (tx_buf != NULL) { + tx_buf->buffer= _os_kmem_alloc(phl_to_drvpriv(phl_info), + tx_buf_size); + if (NULL == tx_buf->buffer) { + pstatus = RTW_PHL_STATUS_RESOURCE; + goto exit; + } + tx_buf->buf_len = tx_buf_size; + INIT_LIST_HEAD(&tx_buf->list); + pstatus = RTW_PHL_STATUS_SUCCESS; + } + + return tx_buf; + +exit: + if (RTW_PHL_STATUS_SUCCESS != pstatus) + _phl_free_txbuf_usb(phl_info, tx_buf); + + return tx_buf; +} + +static enum rtw_phl_status +_phl_alloc_txbuf_pool_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct phl_usb_tx_buf_resource *tx_buf_ring = NULL; + struct phl_usb_buf *tx_buf = NULL; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + u32 i; + FUNCIN_WSTS(pstatus); + + tx_buf_ring = _os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(struct phl_usb_tx_buf_resource)); + + if (NULL != tx_buf_ring) { + INIT_LIST_HEAD(&tx_buf_ring->mgmt_txbuf_list.queue); + INIT_LIST_HEAD(&tx_buf_ring->idle_txbuf_list.queue); + INIT_LIST_HEAD(&tx_buf_ring->h2c_txbuf_list.queue); + _os_spinlock_init(phl_to_drvpriv(phl_info), &tx_buf_ring->mgmt_txbuf_list.lock); + _os_spinlock_init(phl_to_drvpriv(phl_info), &tx_buf_ring->idle_txbuf_list.lock); + _os_spinlock_init(phl_to_drvpriv(phl_info), &tx_buf_ring->h2c_txbuf_list.lock); + for (i = 0; i < bus_cap->tx_buf_num; i++) { + + /*YiWei_todo tx_buf_size need do n bytes aligment*/ + tx_buf = _phl_alloc_txbuf_usb(phl_info, bus_cap->tx_buf_size); + if (NULL == tx_buf) { + pstatus = RTW_PHL_STATUS_RESOURCE; + goto exit; + } + tx_buf->type = RTW_PHL_PKT_TYPE_DATA; + enqueue_usb_buf(phl_info, &tx_buf_ring->idle_txbuf_list, tx_buf, _tail); + pstatus = RTW_PHL_STATUS_SUCCESS; + } + for (i = 0; i < bus_cap->tx_mgnt_buf_num; i++) { + /*YiWei_todo tx_buf_size need do n bytes aligment*/ + tx_buf = _phl_alloc_txbuf_usb(phl_info, bus_cap->tx_mgnt_buf_size); + if (NULL == tx_buf) { + pstatus = RTW_PHL_STATUS_RESOURCE; + goto exit; + } + tx_buf->type = RTW_PHL_PKT_TYPE_MGNT; + enqueue_usb_buf(phl_info, &tx_buf_ring->mgmt_txbuf_list, tx_buf, _tail); + pstatus = RTW_PHL_STATUS_SUCCESS; + } + for (i = 0; i < bus_cap->tx_h2c_buf_num; i++) { + + tx_buf = _os_mem_alloc(phl_to_drvpriv(phl_info), + sizeof(struct phl_usb_buf)); + if (NULL == tx_buf) { + pstatus = RTW_PHL_STATUS_RESOURCE; + goto exit; + } + tx_buf->type = RTW_PHL_PKT_TYPE_H2C; + enqueue_usb_buf(phl_info, &tx_buf_ring->h2c_txbuf_list, tx_buf, _tail); + pstatus = RTW_PHL_STATUS_SUCCESS; + } + /*PHL_INFO("%s, mgmt_buf_cnt = %d\n", __func__, + tx_buf_ring->mgmt_txbuf_list.cnt); + PHL_INFO("%s, idle_buf_cnt = %d\n", __func__, + tx_buf_ring->idle_txbuf_list.cnt); + PHL_INFO("%s, h2c_buf_cnt = %d\n", __func__, + tx_buf_ring->h2c_txbuf_list.cnt);*/ + } + + if (RTW_PHL_STATUS_SUCCESS == pstatus) { + phl_info->hci->txbuf_pool = (u8 *)tx_buf_ring; + } + FUNCOUT_WSTS(pstatus); +exit: + if (RTW_PHL_STATUS_SUCCESS != pstatus) + _phl_free_txbuf_pool_usb(phl_info, (u8 *)tx_buf_ring); + + return pstatus; + +} + + +void _phl_fill_tx_meta_data_usb(struct rtw_t_meta_data *mdata, + u16 packet_len) +{ + mdata->wp_offset = 0; + mdata->wd_page_size = 1; + mdata->pktlen = packet_len; + mdata->hw_amsdu = 0; + mdata->bk = 1; + mdata->ampdu_en = 0; +} + +/* [SD7_Ref] HalUsbInMpdu */ +enum rtw_phl_status _phl_in_token_usb(struct phl_info_t *phl_info, u8 pipe_idx) +{ + void *drv = phl_to_drvpriv(phl_info); + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + u8 rx_desc_sz=0; + struct rtw_rx_buf *rx_buf = NULL; + _os_list* obj = NULL; + + //PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[1] %s:: 000 idle_rxbuf_list.cnt=%d\n", + // __FUNCTION__, rx_buf_ring->idle_rxbuf_list.cnt); + + if(pq_pop(drv, &rx_buf_ring->idle_rxbuf_list, &obj, _first, _irq)) { + rx_buf = (struct rtw_rx_buf*)obj; + } + else + return RTW_PHL_STATUS_RESOURCE; + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[1] %s:: ==> [%p] idle_rxbuf_list.cnt=%d\n", + __FUNCTION__, rx_buf, rx_buf_ring->idle_rxbuf_list.cnt); + + hstatus = rtw_hal_query_info(phl_info->hal, RTW_HAL_RXDESC_SIZE, &rx_desc_sz); + if(RTW_HAL_STATUS_FAILURE == hstatus) + return RTW_PHL_STATUS_FAILURE; + + /* Send the bulk IN request down. */ + rx_buf->pipe_idx = pipe_idx; + + pq_push(drv, &rx_buf_ring->busy_rxbuf_list, &rx_buf->list, _tail, _irq); + + if(os_send_usb_in_token(drv, (void*)rx_buf, rx_buf->buffer, + rx_buf->buf_len, pipe_idx, rx_desc_sz) != RTW_PHL_STATUS_SUCCESS) + { + /* TODO:: temp::error hanlding */ + PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "[1] %s:: [Error] os_send_usb_in_token\n", + __FUNCTION__); + pq_del_node(drv, &rx_buf_ring->busy_rxbuf_list, &rx_buf->list, _irq); + phl_release_rxbuf_usb(phl_info, rx_buf, 0, RTW_RX_TYPE_MAX); // usb doesn't care rtw_rx_type + + return RTW_PHL_STATUS_FAILURE; + } + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[1] %s:: <== [%p] busy_rxbuf_list.cnt=%d\n", + __FUNCTION__, rx_buf, rx_buf_ring->busy_rxbuf_list.cnt); + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status _phl_rx_start_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + u8 pipe_idx = 0; + + for (pipe_idx = 0; pipe_idx < hal_spec->max_bulkin_num ; pipe_idx++) { + + /* Send the bulk IN request down. */ + if( pipe_idx==WLAN_IN_MPDU_PIPE_IDX ) + { + while(rx_buf_ring->busy_rxbuf_list.cnt < (int)(bus_cap->in_token_num)) + { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[0] %s:: rx_buf_ring->busy_rxbuf_list.cnt =%d\n", + __FUNCTION__, rx_buf_ring->busy_rxbuf_list.cnt ); + + pstatus = _phl_in_token_usb(phl_info, pipe_idx); + + if(pstatus != RTW_PHL_STATUS_SUCCESS) + { + break; + } + } + } + /*else if( pipe_idx==WLAN_IN_INTERRUPT_PIPE_IDX ) + { + if(_phl_in_token_usb(phl_info, pipe_idx) != RTW_PHL_STATUS_SUCCESS) + { + pstatus = RTW_PHL_STATUS_FAILURE; + break; + } + }*/ + } + + return pstatus; +} + + +void _phl_rx_stop_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + + _os_cancel_timer(drv, &rx_buf_ring->deferred_timer); +} + + +/* [ERROR Handling]: driver call this function to check pipe status */ +static void _phl_rx_deferred_in_token(void *phl) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[5] %s:: ==>\n", + __FUNCTION__); + + /* [1] Check driver/nic state*/ + + /* [2] Check in token num*/ + pstatus = _phl_rx_start_usb(phl_info); + + // set timer again + if(pstatus == RTW_PHL_STATUS_RESOURCE){ + _phl_indic_new_rxpkt(phl_info); + _os_set_timer(drv, &rx_buf_ring->deferred_timer, 10); + } +} + +/* [SD7_Ref] : HalUsbAllocInResource */ +/* [SD4_Ref] : _rtw_init_recv_priv */ +/* [phl_ref] : _phl_alloc_rxbuf_pool_pcie */ +static enum rtw_phl_status +_phl_rx_init_usb(struct phl_info_t *phl_info, u8 pipe_cnt, u32 num_rxbuf) +{ + void *drv = phl_to_drvpriv(phl_info); + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_rx_buf_ring *rx_buf_ring = NULL; + struct rtw_rx_buf *rx_buf = NULL; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + + u16 i = 0; + FUNCIN_WSTS(pstatus); + + rx_buf_ring = _os_mem_alloc(drv, sizeof(struct rtw_rx_buf_ring)); + if (NULL != rx_buf_ring) { + + /* Initialize list for available rtw_rx_buf objects. */ + _os_spinlock_init(drv, &rx_buf_ring->idle_rxbuf_list.lock); + _os_spinlock_init(drv, &rx_buf_ring->busy_rxbuf_list.lock); + _os_spinlock_init(drv, &rx_buf_ring->pend_rxbuf_list.lock); + INIT_LIST_HEAD(&rx_buf_ring->idle_rxbuf_list.queue); + INIT_LIST_HEAD(&rx_buf_ring->busy_rxbuf_list.queue); + INIT_LIST_HEAD(&rx_buf_ring->pend_rxbuf_list.queue); + rx_buf_ring->idle_rxbuf_list.cnt = 0; + rx_buf_ring->busy_rxbuf_list.cnt = 0; + rx_buf_ring->pend_rxbuf_list.cnt = 0; + + rx_buf_ring->block_cnt_alloc = pipe_cnt * num_rxbuf; + + /* Allocate memory for rtw_rx_buf objects. */ + rx_buf_ring->total_blocks_size = sizeof(struct rtw_rx_buf) * rx_buf_ring->block_cnt_alloc; + + rx_buf_ring->rxbufblock= _os_mem_alloc(drv, rx_buf_ring->total_blocks_size); + if (NULL != rx_buf_ring->rxbufblock) { + /* Initialize all rtw_rx_buf objects allocated and */ + /* put them into the list for further use. */ + rx_buf = (struct rtw_rx_buf*)rx_buf_ring->rxbufblock; + for (i = 0; i < rx_buf_ring->block_cnt_alloc; i++) { + /* MAX_RECEIVE_BUFFER_SIZE = 512(RX_AGG_BLOCK_SIZE) * 60(MAX_RX_AGG_BLKCNT) */ + rx_buf->buf_len = bus_cap->rx_buf_size; + rx_buf->buffer = _os_kmem_alloc(drv, rx_buf->buf_len); + if (NULL == rx_buf->buffer) { + pstatus = RTW_PHL_STATUS_FAILURE; + break; + } + + INIT_LIST_HEAD(&rx_buf->list); + _os_spinlock_init(drv, &rx_buf->lock); + rx_buf->pktcnt = 0; + + pq_push(drv, &rx_buf_ring->idle_rxbuf_list, &rx_buf->list, _tail, _irq); + + rx_buf++; + } + + _os_init_timer(drv, &rx_buf_ring->deferred_timer, + _phl_rx_deferred_in_token, phl_info, "phl_rx_deferred_timer"); + + pstatus = RTW_PHL_STATUS_SUCCESS; + } + } + + + if (RTW_PHL_STATUS_SUCCESS == pstatus) + phl_info->hci->rxbuf_pool = (u8 *)rx_buf_ring; + + FUNCOUT_WSTS(pstatus); + + return pstatus; +} + +static void _phl_rx_deinit_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + struct rtw_rx_buf *rx_buf = NULL; + u32 total_cnt = 0; + //_os_list* obj = NULL; + u16 i = 0; + + _os_cancel_timer(drv, &rx_buf_ring->deferred_timer); + _os_release_timer(drv, &rx_buf_ring->deferred_timer); + + total_cnt = rx_buf_ring->idle_rxbuf_list.cnt + + rx_buf_ring->busy_rxbuf_list.cnt + + rx_buf_ring->pend_rxbuf_list.cnt; + + if(total_cnt != rx_buf_ring->block_cnt_alloc) + PHL_ERR("%s:: alloc(%d)!=idle(%d)+ busy(%d)+ pend(%d)\n", __FUNCTION__, + rx_buf_ring->block_cnt_alloc, rx_buf_ring->idle_rxbuf_list.cnt, + rx_buf_ring->busy_rxbuf_list.cnt, rx_buf_ring->pend_rxbuf_list.cnt); + +#if 0 + // rtw_rx_buf may queue in phl_rx or recv_pkt , check it later. + while(rx_buf_ring->idle_rxbuf_list.cnt) + { + obj = NULL; + if(pq_pop(drv, &rx_buf_ring->idle_rxbuf_list, &obj, _first, _irq)) { + rx_buf = (struct rtw_rx_buf*)obj; + _os_spinlock_free(drv, &rx_buf->lock); + _os_kmem_free(drv, rx_buf->buffer, rx_buf->buf_len); + } + } + + while(rx_buf_ring->pend_rxbuf_list.cnt) + { + obj = NULL; + if(pq_pop(drv, &rx_buf_ring->pend_rxbuf_list, &obj, _first, _irq)) { + rx_buf = (struct rtw_rx_buf*)obj; + _os_spinlock_free(drv, &rx_buf->lock); + _os_kmem_free(drv, rx_buf->buffer, rx_buf->buf_len); + } + } + + while(rx_buf_ring->busy_rxbuf_list.cnt) + { + obj = NULL; + if(pq_pop(drv, &rx_buf_ring->busy_rxbuf_list, &obj, _first, _irq)) { + rx_buf = (struct rtw_rx_buf*)obj; + _os_spinlock_free(drv, &rx_buf->lock); + _os_kmem_free(drv, rx_buf->buffer, rx_buf->buf_len); + } + } + +#else + // DeInitialize all rtw_rx_buf objects. + // + rx_buf = (struct rtw_rx_buf *)rx_buf_ring->rxbufblock; + for (i = 0; i < rx_buf_ring->block_cnt_alloc; i++) + { + // + // Free of this rtw_usb_rx_buf->buffer object. + // + _os_spinlock_free(drv, &rx_buf->lock); + _os_kmem_free(drv, rx_buf->buffer, rx_buf->buf_len); + rx_buf++; + } +#endif + + /* Free memory block allocated for phl_usb_buf objects. */ + _os_mem_free(drv, rx_buf_ring->rxbufblock, rx_buf_ring->total_blocks_size); + + _os_mem_free(drv, rx_buf_ring, sizeof(struct rtw_rx_buf_ring)); +} + +void phl_rx_handle_normal(struct phl_info_t *phl_info, + struct rtw_phl_rx_pkt *phl_rx) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + _os_list frames; + + INIT_LIST_HEAD(&frames); + + if (phl_rx->r.mdata.rx_rate <= RTW_DATA_RATE_HE_NSS4_MCS11) + phl_info->phl_com->phl_stats.rx_rate_nmr[phl_rx->r.mdata.rx_rate]++; + + pstatus = phl_rx_reorder(phl_info, phl_rx, &frames); + if (pstatus == RTW_PHL_STATUS_SUCCESS) + phl_handle_rx_frame_list(phl_info, &frames); + else + PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "[WARNING]handle normal rx error (0x%08X)!\n", pstatus); +} + +enum rtw_phl_status phl_tx_release_buf_usb(void *phl, u8 *tx_buf_ptr) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_usb_tx_buf_resource *tx_buf_res = NULL; + struct phl_usb_buf *release_tx_buf = (struct phl_usb_buf *)tx_buf_ptr; + + tx_buf_res = + (struct phl_usb_tx_buf_resource *)phl_info->hci->txbuf_pool; + + if (release_tx_buf->type == RTW_PHL_PKT_TYPE_H2C) { + phl_enqueue_idle_h2c_pkt(phl_info, + (struct rtw_h2c_pkt *)release_tx_buf->buffer); + release_tx_buf->buffer = NULL; + pstatus = enqueue_usb_buf(phl_info, + &tx_buf_res->h2c_txbuf_list, release_tx_buf, _tail); + } else if (release_tx_buf->type == RTW_PHL_PKT_TYPE_MGNT) + pstatus = enqueue_usb_buf(phl_info, + &tx_buf_res->mgmt_txbuf_list, release_tx_buf, _tail); + else + pstatus = enqueue_usb_buf(phl_info, + &tx_buf_res->idle_txbuf_list, release_tx_buf, _tail); + + return pstatus; +} + +enum rtw_phl_status +phl_prepare_tx_usb(struct phl_info_t *phl_info, struct rtw_xmit_req *tx_req) +{ + return true; +} + + +enum rtw_phl_status +_phl_prepare_tx_usb(struct phl_info_t *phl_info, struct rtw_xmit_req *tx_req, + u8 *tx_buf_data, u32 *packet_len) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + enum rtw_phl_status precycle = RTW_PHL_STATUS_FAILURE; +/* struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; */ + struct rtw_pkt_buf_list *pkt_buf = NULL; +/* struct rtw_phl_pkt_req phl_pkt_req; */ + struct rtw_phl_evt_ops *ops = &phl_info->phl_com->evt_ops; + u32 wd_len = 0; + u8 dummy = 0; + u8 i = 0; + + do { + if (NULL == tx_req) + break; + + /*tx_req->mdata.usb_pkt_ofst = 1;*/ + + hstatus = rtw_hal_fill_wd(phl_info->hal, tx_req, tx_buf_data, &wd_len); + if (hstatus != RTW_HAL_STATUS_SUCCESS) { + PHL_ERR("%s, fill_wd fail hstatus = %d\n", __func__, hstatus); + break; + } else { + /*PHL_INFO("%s, wd_len = %d\n", __func__, wd_len);*/ + if(tx_req->mdata.usb_pkt_ofst == 1) + dummy = PKT_OFFSET_DUMMY; + tx_buf_data = tx_buf_data + wd_len + dummy; + *packet_len = *packet_len + wd_len + dummy; + /*PHL_INFO("%s, packet_len = %d\n", __func__, *packet_len);*/ + } + + /*tx_buf_data = tx_buf_data + 8;*/ + /**packet_len = *packet_len + 8;*/ + + pkt_buf = (struct rtw_pkt_buf_list *)tx_req->pkt_list; + for (i = 0; i < tx_req->pkt_cnt; i++) { + /*PHL_INFO("%s, pkt[%d] 0x%p length = %d\n", __func__, i, + (void *)pkt_buf->vir_addr, pkt_buf->length);*/ + if (pkt_buf->vir_addr) { + _os_mem_cpy(phl_to_drvpriv(phl_info), + tx_buf_data, pkt_buf->vir_addr, pkt_buf->length); + tx_buf_data = tx_buf_data + pkt_buf->length; + *packet_len = *packet_len + pkt_buf->length; + /*PHL_INFO("%s, packet_len = %d\n", __func__, *packet_len);*/ + } + pkt_buf++; + } + pstatus = RTW_PHL_STATUS_SUCCESS; + + } while (false); + + if (RTW_PHL_TREQ_TYPE_TEST_PATTERN == tx_req->treq_type) { + if (NULL != ops->tx_test_recycle) { + precycle = ops->tx_test_recycle(phl_info, tx_req); + if (RTW_PHL_STATUS_SUCCESS != precycle) + PHL_WARN("tx_test_recycle fail\n"); + } + } else if (RTW_PHL_TREQ_TYPE_NORMAL == tx_req->treq_type) { + if (NULL != ops->tx_recycle) { + precycle = ops->tx_recycle(phl_to_drvpriv(phl_info), + tx_req); + if (RTW_PHL_STATUS_SUCCESS != precycle) + PHL_WARN("tx recycle fail\n"); + } + } + + return pstatus; +} + +static enum rtw_phl_status phl_tx_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + + return pstatus; +} + + +void phl_trx_deinit_usb(struct phl_info_t *phl_info) +{ + FUNCIN(); + + os_out_token_free(phl_to_drvpriv(phl_info)); + _phl_free_txbuf_pool_usb(phl_info, phl_info->hci->txbuf_pool); + + os_in_token_free(phl_to_drvpriv(phl_info)); + _phl_rx_deinit_usb(phl_info); + + FUNCOUT(); +} + +void phl_req_tx_stop_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + + _os_atomic_set(drv, &phl_info->phl_sw_tx_sts, + PHL_TX_STATUS_STOP_INPROGRESS); +} + +void phl_tx_stop_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + + _os_atomic_set(drv, &phl_info->phl_sw_tx_sts, PHL_TX_STATUS_SW_PAUSE); +} + +void phl_req_rx_stop_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + + _os_atomic_set(drv, &phl_info->phl_sw_rx_sts, + PHL_RX_STATUS_STOP_INPROGRESS); +} + +void phl_rx_stop_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + + _os_atomic_set(drv, &phl_info->phl_sw_rx_sts, PHL_RX_STATUS_SW_PAUSE); +} + +bool phl_is_tx_sw_pause_usb(struct phl_info_t *phl_info) +{ + void *drvpriv = phl_to_drvpriv(phl_info); + + if (PHL_TX_STATUS_SW_PAUSE == _os_atomic_read(drvpriv, + &phl_info->phl_sw_tx_sts)) + return true; + else + return false; +} + +bool phl_is_rx_sw_pause_usb(struct phl_info_t *phl_info) +{ + void *drvpriv = phl_to_drvpriv(phl_info); + + if (PHL_RX_STATUS_SW_PAUSE == _os_atomic_read(drvpriv, + &phl_info->phl_sw_rx_sts)) + return true; + else + return false; +} + +void phl_tx_resume_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + _os_atomic_set(drv, &phl_info->phl_sw_tx_sts, PHL_TX_STATUS_RUNNING); +} + +void phl_rx_resume_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + _os_atomic_set(drv, &phl_info->phl_sw_rx_sts, PHL_RX_STATUS_RUNNING); +} + +void phl_trx_resume_usb(struct phl_info_t *phl_info, u8 type) +{ + if (PHL_CTRL_TX & type) + phl_tx_resume_usb(phl_info); + + if (PHL_CTRL_RX & type) + phl_rx_resume_usb(phl_info); +} + +void phl_reset_tx_usb(struct phl_info_t *phl_info) +{ + +} + +void phl_reset_rx_usb(struct phl_info_t *phl_info) +{ + +} + +void phl_trx_reset_usb(struct phl_info_t *phl_info, u8 type) +{ + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + struct rtw_stats *phl_stats = &phl_com->phl_stats; + + if (PHL_CTRL_TX & type) { + phl_reset_tx_usb(phl_info); + phl_reset_tx_stats(phl_stats); + } + + if (PHL_CTRL_RX & type) { + phl_reset_rx_usb(phl_info); + phl_reset_rx_stats(phl_stats); + } +} + +static void _phl_tx_flow_ctrl_usb(struct phl_info_t *phl_info, + struct phl_ring_status *target_ring, + struct phl_usb_buf **tx_buf) +{ + struct phl_usb_tx_buf_resource *reso = NULL; + + reso = (struct phl_usb_tx_buf_resource *)phl_info->hci->txbuf_pool; + /*PHL_INFO("%s, idle_txbuf_cnt = %d\n", __func__, reso->idle_txbuf_cnt);*/ + + if (reso) { + if (target_ring) { + if (target_ring->ring_ptr->tid == MGMT_TID) + *tx_buf = dequeue_usb_buf(phl_info, &reso->mgmt_txbuf_list); + else + *tx_buf = dequeue_usb_buf(phl_info, &reso->idle_txbuf_list); + } + } else { + PHL_ERR("%s, phl_usb_tx_buf_resource == NULL\n", __func__); + } + + if (*tx_buf == NULL && target_ring != NULL) { + if (target_ring->ring_ptr->tid == MGMT_TID) + PHL_WARN("%s, mgnt tx_buf NULL free ring sts\n", __func__); + else + PHL_DBG("%s, idle tx_buf NULL free ring sts\n", __func__); + phl_release_ring_sts(phl_info, target_ring); + target_ring = NULL; + } +} + +static void _usb_tx_agg_preprocess(struct phl_info_t *phl_info, u8 max_bulkout_wd_num, + struct phl_ring_status *ring_sts, + u32 *last_idx, u8 *add_dummy) +{ + struct rtw_phl_tx_ring *tring = ring_sts->ring_ptr; + struct rtw_xmit_req *tx_req = NULL; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + u32 total = ring_sts->req_busy; + u16 cnt = 0; + u16 rptr = 0; + void *drv_priv = phl_to_drvpriv(phl_info); + u32 bulk_size = phl_info->hci->usb_bulkout_size; + u32 tx_len = 0; + u32 wd_len = MAX_WD_LEN; + u32 packet_len = 0; + u32 packet_align_len = 0; + u8 trasc_agg_cnt = 0; + u8 trasc_idx = 0; + u8 shift_offset = GET_SHIFT_OFFSET(bulk_size); + u16 idx = 0; + + *last_idx = IDX_NONE; + *add_dummy = false; + + rptr = (u16)_os_atomic_read(drv_priv, &tring->phl_next_idx); + while(cnt < total) { + idx = (rptr + cnt) % MAX_PHL_RING_ENTRY_NUM; + tx_req = (struct rtw_xmit_req *)tring->entry[idx]; + if (NULL == tx_req) { + *last_idx = (cnt) ? (cnt - 1) : (IDX_NONE); + break; + } + if (tx_req->mdata.wdinfo_en ==1) + wd_len = MAX_WD_LEN; + else + wd_len = MAX_WD_BODY_LEN; + if (( _ALIGN(wd_len + tx_req->total_len, + 8) + tx_len) > bus_cap->tx_buf_size - PKT_OFFSET_DUMMY) { + *last_idx = (cnt) ? (cnt - 1) : (IDX_NONE); + break; + } + /* packet_len represens the length of PREVIOUS copied tx req + * not the current one. + */ + packet_align_len = _ALIGN(packet_len, 8); + packet_align_len -= packet_len; +#ifdef RTW_WKARD_USB_TXAGG_BULK_END_WD + if(! ((tx_len + wd_len + packet_align_len) % bulk_size)) { + *last_idx = (cnt) ? (cnt - 1) : (IDX_NONE); + break; + } +#endif + /* if current tx req is accepted for aggregation + * 8 byte alignment is required before copying current data. + */ + tx_len += packet_align_len; + + /* update packet_len for next alignment reference */ + packet_len = wd_len + tx_req->total_len; + tx_len += packet_len; + /* chip only allow a limited number of WD + * placed inside per bulk transaction. + * */ + trasc_agg_cnt++; + if(trasc_idx != tx_len >> shift_offset) { + trasc_idx = (u8)(tx_len >> shift_offset); + trasc_agg_cnt = 0; + } + if (trasc_agg_cnt >= max_bulkout_wd_num) { + *last_idx = cnt; + break; + } + cnt++; + if( tx_req->mdata.type != RTW_PHL_PKT_TYPE_DATA) + break; +#ifndef CONFIG_PHL_USB_TX_AGGREGATION + break; +#endif + } + if(*last_idx == IDX_NONE && tx_len && cnt <= total) + *last_idx = cnt - 1; + if( tx_len && ! (tx_len % bulk_size) ) + *add_dummy = true; +} +static void _phl_tx_callback_usb(void *context); +static enum rtw_phl_status _phl_handle_xmit_ring_usb(struct phl_info_t *phl_info, + struct phl_ring_status *ring_sts, struct phl_usb_buf *tx_buf) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; +/* struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops; */ + struct rtw_phl_tx_ring *tring = ring_sts->ring_ptr; + struct rtw_xmit_req *tx_req = NULL; + struct phl_usb_tx_buf_resource *tx_buf_res = NULL; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + u16 rptr = 0, next_idx = 0; + u32 packet_len = 0; + u32 packet_align_len = 0; + u32 tx_len = 0; + u8 *tx_buf_data = NULL; + u8 bulk_id = 0; + u8 agg_cnt = 0; + u8 dma_ch = tring->dma_ch; + enum rtw_packet_type type = 0; + u8 is_dummy = false; + u8 trasc_agg_cnt = 0; + u32 wd_len = 0; + u32 bulk_size = phl_info->hci->usb_bulkout_size; + u32 last_idx = IDX_NONE; +#ifdef CONFIG_PHL_USB_TX_AGGREGATION + u8 agg_en = 1; + u8 trasc_idx = 0; + u8 shift_offset = GET_SHIFT_OFFSET(bulk_size); + u8 max_bulkout_wd_num = rtw_hal_get_max_bulkout_wd_num(phl_info->hal); +#endif + void *drv_priv = phl_to_drvpriv(phl_info); +#ifdef CONFIG_PHL_USB_TX_PADDING_CHK + _usb_tx_agg_preprocess(phl_info, max_bulkout_wd_num, ring_sts, + &last_idx, &is_dummy); +#endif + tx_buf_data = tx_buf->buffer; + while (0 != ring_sts->req_busy) { + rptr = (u16)_os_atomic_read(drv_priv, &tring->phl_next_idx); + + tx_req = (struct rtw_xmit_req *)tring->entry[rptr]; + if (NULL == tx_req) { + PHL_ERR("tx_req is NULL!\n"); + break; + } + + tx_req->mdata.macid = ring_sts->macid; + tx_req->mdata.band = ring_sts->band; + tx_req->mdata.wmm = ring_sts->wmm; + tx_req->mdata.hal_port = ring_sts->port; + /*tx_req->mdata.mbssid = ring_sts->mbssid;*/ + tx_req->mdata.tid = tring->tid; + tx_req->mdata.dma_ch = tring->dma_ch; + tx_req->mdata.pktlen = (u16)tx_req->total_len; + type = tx_req->mdata.type; + if (tx_req->mdata.wdinfo_en == 1) + wd_len = MAX_WD_LEN; + else + wd_len = MAX_WD_BODY_LEN; + if(last_idx != IDX_NONE && agg_cnt == (u8)last_idx && is_dummy) { + tx_req->mdata.usb_pkt_ofst = 1; + wd_len += PKT_OFFSET_DUMMY; + } +#ifdef CONFIG_PHL_USB_TX_PADDING_CHK + if (_ALIGN(wd_len + tx_req->total_len, + 8) + tx_len > (bus_cap->tx_buf_size - PKT_OFFSET_DUMMY)) + break; +#else + if (_ALIGN(wd_len + tx_req->total_len, + 8) + tx_len > bus_cap->tx_buf_size) + break; +#endif + +#ifdef CONFIG_PHL_USB_TX_AGGREGATION + if (agg_en && type == RTW_PHL_PKT_TYPE_DATA) { + packet_align_len = _ALIGN(packet_len, 8); + tx_buf_data = tx_buf_data + packet_align_len; + +#ifdef RTW_WKARD_USB_TXAGG_BULK_END_WD + if (tx_len !=0) { + int check_len = 0; + check_len = tx_len + wd_len + packet_align_len - packet_len; + /*PHL_INFO("%s, tx_len(%d),wd_len(%d),packet_align_len(%d),packet_len(%d)\n", + __func__, tx_len, wd_len ,packet_align_len ,packet_len);*/ + if(! (check_len % bulk_size)) { + PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_, "%s:AGG break!\n", __func__); + break; + } + } +#endif + + if (packet_align_len > packet_len) + tx_len = tx_len + (packet_align_len - packet_len); + } +#endif + + packet_len = 0; + pstatus = _phl_prepare_tx_usb(phl_info, tx_req, + tx_buf_data, &packet_len); + /*PHL_INFO("%s, packet_len = %d\n", __func__, packet_len);*/ + + tx_len = tx_len + packet_len; + /*PHL_INFO("%s, tx_len = %d\n", __func__, tx_len);*/ + + if (RTW_PHL_STATUS_SUCCESS == pstatus) { + ring_sts->req_busy--; + + /* hana_todo, workaround here to update phl_index */ + _os_atomic_set(drv_priv, &tring->phl_idx, rptr); + + agg_cnt++; + trasc_agg_cnt++; + + if (type != RTW_PHL_PKT_TYPE_DATA) + break; + +#ifdef CONFIG_PHL_USB_TX_AGGREGATION + /* chip only allow a limited number of WD + * placed inside per bulk transaction. + * */ + if(trasc_idx != tx_len >> shift_offset) { + trasc_idx = (u8)(tx_len >> shift_offset); + trasc_agg_cnt = 0; + } + if (trasc_agg_cnt >= max_bulkout_wd_num) { + /*PHL_PRINT("%s, hit wd limit(%d), break agg\n", + __func__, max_bulkout_wd_num);*/ + break; + } +#else + if (agg_cnt == 1) + break; +#endif + + if (0 != ring_sts->req_busy) { + next_idx = rptr + 1; + + if (next_idx >= MAX_PHL_RING_ENTRY_NUM) { + _os_atomic_set(drv_priv, + &tring->phl_next_idx, 0); + + } else { + _os_atomic_inc(drv_priv, + &tring->phl_next_idx); + } + } + + } else { + _os_atomic_set(drv_priv, &tring->phl_idx, rptr); + PHL_INFO("HCI prepare tx fail\n"); + break; + } + } + + if (pstatus == RTW_PHL_STATUS_SUCCESS) { + tx_buf_data = tx_buf->buffer; +#ifdef CONFIG_PHL_USB_TX_PADDING_CHK + if( ! (tx_len % bulk_size) ) + PHL_ERR("%s: no padding dummy\n", __func__); +#endif +#ifdef CONFIG_PHL_USB_TX_AGGREGATION + /*PHL_INFO("%s, agg_cnt = %d\n", __func__, agg_cnt);*/ + if (agg_en && type == RTW_PHL_PKT_TYPE_DATA && agg_cnt > 1) + rtw_hal_usb_tx_agg_cfg(phl_info->hal, tx_buf_data, agg_cnt); +#endif + bulk_id = rtw_hal_get_bulkout_id(phl_info->hal, + dma_ch, 0); + pstatus = os_usb_tx(phl_to_drvpriv(phl_info), + (u8 *)tx_buf, bulk_id, tx_len, tx_buf_data); + } + + if (pstatus != RTW_PHL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] phl_tx fail!\n"); + if (tx_buf) { + tx_buf_res = + (struct phl_usb_tx_buf_resource *)phl_info->hci->txbuf_pool; + + if (tring->tid == MGMT_TID) + pstatus = enqueue_usb_buf(phl_info, + &tx_buf_res->mgmt_txbuf_list, tx_buf, _tail); + else + pstatus = enqueue_usb_buf(phl_info, + &tx_buf_res->idle_txbuf_list, tx_buf, _tail); + } + } + + phl_release_ring_sts(phl_info, ring_sts); + + return pstatus; +} + +static void _phl_tx_callback_usb(void *context) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_phl_handler *phl_handler + = (struct rtw_phl_handler *)phl_container_of(context, + struct rtw_phl_handler, + os_handler); + struct phl_info_t *phl_info = (struct phl_info_t *)phl_handler->context; +/* struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops; */ + struct phl_ring_status *ring_sts = NULL, *t; + struct phl_usb_buf *tx_buf = NULL; + void *drvpriv = phl_to_drvpriv(phl_info); + _os_list sta_list; + bool tx_pause = false; +#ifdef CONFIG_POWER_SAVE + _os_atomic *trx_more = &phl_info->phl_sw_tx_more; +#endif + + INIT_LIST_HEAD(&sta_list); + + /* check datapath sw state */ + tx_pause = phl_datapath_chk_trx_pause(phl_info, PHL_CTRL_TX); + if (true == tx_pause) + goto end; + +#ifdef CONFIG_POWER_SAVE + /* check ps state when tx is not paused */ + if ((true == _os_atomic_read(drvpriv, trx_more)) && (false == phl_ps_is_datapath_allowed(phl_info))) { + PHL_WARN("%s(): datapath is not allowed now... may in low power.\n", __func__); + goto chk_stop; + } +#endif + + if (true == phl_check_xmit_ring_resource(phl_info, &sta_list)) { + phl_tx_flow_ctrl(phl_info, &sta_list); + + phl_list_for_loop_safe(ring_sts, t, struct phl_ring_status, + &phl_info->t_fctrl_result, list) { + + list_del(&ring_sts->list); + _phl_tx_flow_ctrl_usb(phl_info, ring_sts, &tx_buf); + + if (ring_sts && tx_buf) + pstatus = _phl_handle_xmit_ring_usb(phl_info, + ring_sts, + tx_buf); + else if (!ring_sts) + PHL_DBG("%s, ring_sts NULL\n", __func__); + else if (!tx_buf) + PHL_DBG("%s, tx_buf NULL\n", __func__); + } + + /*pstatus = hci_trx_ops->tx(phl_info);*/ + } +#ifdef CONFIG_POWER_SAVE +chk_stop: +#endif + /* for the pause PHL Tx handshake with USB SER */ + if (PHL_TX_STATUS_STOP_INPROGRESS == + _os_atomic_read(drvpriv, &phl_info->phl_sw_tx_sts)) + phl_tx_stop_usb(phl_info); + +end: + phl_free_deferred_tx_ring(phl_info); +} + +static void _phl_rx_callback_usb(void *context) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_phl_handler *phl_handler + = (struct rtw_phl_handler *)phl_container_of(context, + struct rtw_phl_handler, + os_handler); + struct phl_info_t *phl_info = (struct phl_info_t *)phl_handler->context; + struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops; + bool rx_pause = false; + + /* check datapath sw state */ + rx_pause = phl_datapath_chk_trx_pause(phl_info, PHL_CTRL_RX); + if (true == rx_pause) + goto end; + + do { + if (false == phl_check_recv_ring_resource(phl_info)) + break; + + pstatus = hci_trx_ops->rx(phl_info); + + if (RTW_PHL_STATUS_FAILURE == pstatus) { + PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "[WARNING] hci_trx_ops->rx fail!\n"); + } + } while (false); + +end: + return; +} + +enum rtw_phl_status phl_trx_init_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com); + struct rtw_phl_handler *tx_handler = &phl_info->phl_tx_handler; + struct rtw_phl_handler *rx_handler = &phl_info->phl_rx_handler; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + struct bus_cap_t *bus_cap = &hal_com->bus_cap; + void *drv_priv = phl_to_drvpriv(phl_info); + + FUNCIN_WSTS(pstatus); + PHL_INFO("%s, bus_cap->tx_buf_num(%d)\n", __func__, bus_cap->tx_buf_num); + PHL_INFO("%s, bus_cap->tx_buf_size(%d)\n", __func__, bus_cap->tx_buf_size); + PHL_INFO("%s, bus_cap->tx_mgnt_buf_num(%d)\n", __func__, bus_cap->tx_mgnt_buf_num); + PHL_INFO("%s, bus_cap->tx_mgnt_buf_size(%d)\n", __func__, bus_cap->tx_mgnt_buf_size); + PHL_INFO("%s, bus_cap->tx_h2c_buf_num(%d)\n", __func__, bus_cap->tx_h2c_buf_num); + PHL_INFO("%s, bus_cap->rx_buf_num(%d)\n", __func__, bus_cap->rx_buf_num); + PHL_INFO("%s, bus_cap->rx_buf_size(%d)\n", __func__, bus_cap->rx_buf_size); + PHL_INFO("%s, bus_cap->in_token_num(%d)\n", __func__, bus_cap->in_token_num); + do { + tx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; /* tasklet */ + tx_handler->callback = _phl_tx_callback_usb; + tx_handler->context = phl_info; + tx_handler->drv_priv = drv_priv; + pstatus = phl_register_handler(phl_info->phl_com, tx_handler); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + rx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; + rx_handler->callback = _phl_rx_callback_usb; + rx_handler->context = phl_info; + rx_handler->drv_priv = drv_priv; + pstatus = phl_register_handler(phl_info->phl_com, rx_handler); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + /* usb tx sw resource */ + /*YiWei_to need use correct txbuf num and txbuf size*/ + pstatus = _phl_alloc_txbuf_pool_usb(phl_info); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + /* allocate rx packet buffer block */ + pstatus = _phl_rx_init_usb(phl_info, hal_spec->max_bulkin_num, bus_cap->rx_buf_num); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + /* allocate platform in token */ + /* OS maintain in token (number/init/free)*/ + pstatus = os_in_token_alloc(phl_to_drvpriv(phl_info)); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + pstatus = os_out_token_alloc(phl_to_drvpriv(phl_info)); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + break; + + os_enable_usb_out_pipes(phl_to_drvpriv(phl_info)); + os_enable_usb_in_pipes(phl_to_drvpriv(phl_info)); + + } while (false); + + if (RTW_PHL_STATUS_SUCCESS != pstatus) + phl_trx_deinit_usb(phl_info); + + FUNCOUT_WSTS(pstatus); + return pstatus; +} + +/* phl_trx_start_usb */ +enum rtw_phl_status phl_trx_cfg_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + +#ifdef CONFIG_PHL_USB_RX_AGGREGATION + rtw_hal_usb_rx_agg_cfg(phl_info->hal, PHL_RX_AGG_DEFAULT, + 0, 0, 0, 0, 0); +#endif + os_enable_usb_out_pipes(phl_to_drvpriv(phl_info)); + os_enable_usb_in_pipes(phl_to_drvpriv(phl_info)); + + pstatus = _phl_rx_start_usb(phl_info); + + return pstatus; +} + + +void phl_trx_stop_usb(struct phl_info_t *phl_info) +{ + _phl_rx_stop_usb(phl_info); + os_disable_usb_out_pipes(phl_to_drvpriv(phl_info)); + os_disable_usb_in_pipes(phl_to_drvpriv(phl_info)); +} + + +/*enqueue */ +/* usb_read_port_complete */ +enum rtw_phl_status +phl_pend_rxbuf_usb(struct phl_info_t *phl_info, void *rxobj, u32 inbuf_len, u8 status_code) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + struct rtw_rx_buf *rx_buf = (struct rtw_rx_buf *)rxobj; + + if(!list_empty(&rx_buf_ring->busy_rxbuf_list.queue)) { + + pq_del_node(drv, &rx_buf_ring->busy_rxbuf_list, &rx_buf->list, _irq); + } + else + PHL_ASSERT("[2] %s:: [Notice] rxbuf isn't in busy_rxbuf_list\n", __FUNCTION__); + + if(status_code == RTW_PHL_STATUS_SUCCESS) + { + rx_buf->transfer_len = inbuf_len; + if(pq_push(drv, &rx_buf_ring->pend_rxbuf_list, &rx_buf->list, _tail, _irq)) + pstatus = RTW_PHL_STATUS_SUCCESS; + } + else + { + PHL_TRACE(COMP_PHL_RECV, _PHL_INFO_, "[2] %s:: [Error] Complete\n", + __FUNCTION__); + phl_release_rxbuf_usb(phl_info, rx_buf, 0, RTW_RX_TYPE_MAX); // usb doesn't care rtw_rx_type + } + +#if 0 + /* for the pause PHL Rx handshake with USB SER */ + if (PHL_RX_STATUS_SW_PAUSE == _os_atomic_read(drv, + &phl_info->phl_sw_rx_sts)) + return RTW_PHL_STATUS_SUCCESS; +#endif + + if(status_code == RTW_PHL_STATUS_SUCCESS) + { + if(_phl_in_token_usb(phl_info, rx_buf->pipe_idx) == RTW_PHL_STATUS_RESOURCE) + { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[5] RTW_PHL_STATUS_RESOURCE :: idle_rxbuf_list or in_token empty \n"); + + _os_set_timer(drv, &rx_buf_ring->deferred_timer, 10); + } + } + + return pstatus; +} + +enum rtw_phl_status +phl_release_rxbuf_usb(struct phl_info_t *phl_info, void *r, u8 ch, enum rtw_rx_type type) +{ + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_rx_buf_ring *rx_buf_ring = NULL; + struct rtw_rx_buf *rx_buf = (struct rtw_rx_buf *)r; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + _os_spinlockfg sp_flags; + bool ret = false; + + rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + if (rx_buf_ring != NULL && rx_buf != NULL) { + + _os_spinlock(drv, &rx_buf->lock, _irq, &sp_flags); + if(rx_buf->pktcnt) + rx_buf->pktcnt--; + + if(!rx_buf->pktcnt) + { + _os_mem_set(drv, rx_buf->buffer, 0, rx_buf->buf_len); + INIT_LIST_HEAD(&rx_buf->list); + _os_spinunlock(drv, &rx_buf->lock, _irq, &sp_flags); + + ret = pq_push(drv, &rx_buf_ring->idle_rxbuf_list, &rx_buf->list, _tail, _irq); + if(ret) + pstatus = RTW_PHL_STATUS_SUCCESS; + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[4] %s:: [%p] idle_rxbuf_list.cnt=%d\n", __FUNCTION__, rx_buf, rx_buf_ring->idle_rxbuf_list.cnt); + } + else + { + _os_spinunlock(drv, &rx_buf->lock, _irq, &sp_flags); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[4] %s:: [%p] pktcnt =%d\n", __FUNCTION__, rx_buf, rx_buf->pktcnt); + pstatus = RTW_PHL_STATUS_SUCCESS; + } + } + + return pstatus; +} + +struct rtw_phl_rx_pkt *phl_get_single_rx(struct phl_info_t *phl_info, + struct rtw_rx_buf *rx_buf) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + void *drv = phl_to_drvpriv(phl_info); + struct rtw_phl_rx_pkt *phl_rx = NULL, *phl_rxhead = NULL; + + u8 *pkt_buf, *pkt_buf_end, ref_cnt = 0; + u8 *netbuf = NULL; + s32 transfer_len = 0; + s32 pkt_offset = 0, align_offset = 0; + bool brel = true, balloc = false; + _os_spinlockfg sp_flags; + u8 mfrag = 0, frag_num = 0; + u16 netbuf_len = 0; + + //initialize for compiler + pkt_buf = rx_buf->buffer; + pkt_buf_end = rx_buf->buffer + rx_buf->transfer_len; + transfer_len = (s32)rx_buf->transfer_len; + + do { + balloc = false; + phl_rx = rtw_phl_query_phl_rx(phl_info); + if (NULL == phl_rx) { + PHL_TRACE(COMP_PHL_RECV, _PHL_ERR_, "[3] %s(%d):: [Error] phl_rx out of resource\n", + __func__, __LINE__); + + pstatus = RTW_PHL_STATUS_RESOURCE; + break; + + } + + // TODO:: Hal handle rx packet (rx desc/physts/hal rx data statistic) + hstatus = rtw_hal_handle_rx_buffer(phl_info->phl_com, + phl_info->hal, + pkt_buf, transfer_len, + phl_rx); + + if (RTW_HAL_STATUS_SUCCESS != hstatus) { + phl_release_phl_rx(phl_info, phl_rx); + phl_rx = NULL; + pstatus = RTW_PHL_STATUS_FAILURE; + + /*ToDo:: Should we take care that one of ampdu damaged?*/ + if(ref_cnt) + PHL_ASSERT("[3] %s:: [Notice] one of ampdu damaged\n", __FUNCTION__); + break; + } + + pkt_offset = (s32)(phl_rx->r.pkt_list[0].vir_addr - pkt_buf) + phl_rx->r.pkt_list[0].length; + +#ifdef CONFIG_PHL_USB_RX_AGGREGATION + align_offset = _ALIGN(pkt_offset, 8); /*8 bytes aligned*/ +#else + align_offset = pkt_offset; +#endif + + if(phl_rxhead == NULL) + { + phl_rxhead = phl_rx; + INIT_LIST_HEAD(&phl_rxhead->list); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[3] %s:: [head %p]: transfer_len=%d\n", + __FUNCTION__, phl_rx->r.pkt_list[0].vir_addr, transfer_len); + } + else + { + list_add_tail(&phl_rx->list, &phl_rxhead->list); + + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_,"[3] %s:: [child %p]: offset[%d -> %d] transfer_len=%d\n", + __FUNCTION__, phl_rx->r.pkt_list[0].vir_addr, pkt_offset, align_offset, transfer_len); + } + + //shift buffer pointer + pkt_buf = pkt_buf + align_offset; + + transfer_len -= align_offset; + + if (phl_rx->type == RTW_RX_TYPE_WIFI) + { + /* Pre-alloc netbuf and replace pkt_list[0].vir_addr */ + + /* For first fragment packet, driver need allocate 1536 to defrag packet.*/ + mfrag = PHL_GET_80211_HDR_MORE_FRAG(phl_rx->r.pkt_list[0].vir_addr); + frag_num = PHL_GET_80211_HDR_FRAG_NUM(phl_rx->r.pkt_list[0].vir_addr); + + if (mfrag == 1 && frag_num == 0) { + if (phl_rx->r.pkt_list[0].length < RTW_MAX_ETH_PKT_LEN) + netbuf_len = RTW_MAX_ETH_PKT_LEN; + else + netbuf_len = phl_rx->r.pkt_list[0].length; + } else { + netbuf_len = phl_rx->r.pkt_list[0].length; + } + + netbuf = _os_alloc_netbuf(drv, + netbuf_len, + &(phl_rx->r.os_priv)); + + if (netbuf) { + _os_mem_cpy(drv, netbuf, + phl_rx->r.pkt_list[0].vir_addr, phl_rx->r.pkt_list[0].length); + phl_rx->r.pkt_list[0].vir_addr = netbuf; + phl_rx->r.os_netbuf_len = netbuf_len; + balloc = true; + } + } + + if(!balloc) + { + /* every phl_rx assign the same rx_buf */ + phl_rx->rxbuf_ptr = (u8 *)rx_buf; + brel = false; + ref_cnt++; + } + + pstatus = RTW_PHL_STATUS_SUCCESS; + + } while (transfer_len > 0); + + + if(phl_rxhead) + { + if(brel) + { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[3] %s:: prealloc netbuff for all ampdu\n", + __FUNCTION__); + phl_release_rxbuf_usb(phl_info, rx_buf, phl_rxhead->r.mdata.dma_ch, phl_rxhead->type); + } + else + { + _os_spinlock(drv, &rx_buf->lock, _irq, &sp_flags); + rx_buf->pktcnt= ref_cnt; + _os_spinunlock(drv, &rx_buf->lock, _irq, &sp_flags); + /*PHL_TRACE(COMP_PHL_RECV,_PHL_DEBUG_,"[3] %s:: phl_rx=%p, ref_cnt= %d\n", + __FUNCTION__, phl_rx, ref_cnt);*/ + } + } + return phl_rxhead; +} + +void rtw_phl_post_in_complete(void *phl, void *rxobj, u32 inbuf_len, u8 status_code) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops; + + pstatus = hci_trx_ops->pend_rxbuf(phl_info, rxobj, inbuf_len, status_code); + + if(pstatus==RTW_PHL_STATUS_SUCCESS) + rtw_phl_start_rx_process(phl); +} + +void phl_wp_report_record_sts_usb(struct phl_info_t *phl_info, u8 macid, u16 ac_queue, + u8 txsts) +{ + struct rtw_phl_stainfo_t *phl_sta = NULL; + struct rtw_hal_stainfo_t *hal_sta = NULL; + struct rtw_wp_rpt_stats *wp_rpt_stats= NULL; + + phl_sta = rtw_phl_get_stainfo_by_macid(phl_info, macid); + + if (phl_sta) { + hal_sta = phl_sta->hal_sta; + /* Record Per ac queue statistics */ + wp_rpt_stats = &hal_sta->trx_stat.wp_rpt_stats[ac_queue]; + + _os_spinlock(phl_to_drvpriv(phl_info), &hal_sta->trx_stat.tx_sts_lock, _bh, NULL); + if (TX_STATUS_TX_DONE == txsts) { + /* record total tx ok*/ + hal_sta->trx_stat.tx_ok_cnt++; + /* record per ac queue tx ok*/ + wp_rpt_stats->tx_ok_cnt++; + } else { + /* record total tx fail*/ + hal_sta->trx_stat.tx_fail_cnt++; + /* record per ac queue tx fail*/ + if (TX_STATUS_TX_FAIL_REACH_RTY_LMT == txsts) + wp_rpt_stats->rty_fail_cnt++; + else if (TX_STATUS_TX_FAIL_LIFETIME_DROP == txsts) + wp_rpt_stats->lifetime_drop_cnt++; + else if (TX_STATUS_TX_FAIL_MACID_DROP == txsts) + wp_rpt_stats->macid_drop_cnt++; + } + _os_spinunlock(phl_to_drvpriv(phl_info), &hal_sta->trx_stat.tx_sts_lock, _bh, NULL); + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,"macid: %u, ac_queue: %u, tx_ok_cnt: %u, rty_fail_cnt: %u, " + "lifetime_drop_cnt: %u, macid_drop_cnt: %u\n" + , macid, ac_queue, wp_rpt_stats->tx_ok_cnt, wp_rpt_stats->rty_fail_cnt + , wp_rpt_stats->lifetime_drop_cnt, wp_rpt_stats->macid_drop_cnt); + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,"totoal tx ok: %u \n totoal tx fail: %u\n" + , hal_sta->trx_stat.tx_ok_cnt, hal_sta->trx_stat.tx_fail_cnt); + } else { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s: PHL_STA not found\n", + __FUNCTION__); + } +} + +void _phl_rx_handle_wp_report_usb(struct phl_info_t *phl_info, + struct rtw_phl_rx_pkt *phl_rx) +{ + struct rtw_recv_pkt *r = &phl_rx->r; + u8 *pkt = NULL; + u16 pkt_len = 0; + u16 rsize = 0; + u8 macid = 0, ac_queue = 0, txsts = 0; + + pkt = r->pkt_list[0].vir_addr; + pkt_len = r->pkt_list[0].length; + + while (pkt_len > 0) { + rsize = rtw_hal_handle_wp_rpt_usb(phl_info->hal, pkt, pkt_len, + &macid, &ac_queue, &txsts); + if (0 == rsize) + break; + + phl_wp_report_record_sts_usb(phl_info, macid, ac_queue, txsts); + pkt += rsize; + pkt_len -= rsize; + } +} + + +static void phl_rx_process_usb(struct phl_info_t *phl_info, + struct rtw_phl_rx_pkt *phl_rxhead) +{ + struct rtw_phl_rx_pkt *phl_rx = NULL; + + do { + /* Get head of link list */ + phl_rx = phl_rxhead; + + /* assign next entry to head */ + phl_rxhead = list_entry(phl_rx->list.next, struct rtw_phl_rx_pkt, list); + + if(phl_rx == phl_rxhead) + phl_rxhead=NULL; + + list_del(&phl_rx->list); + + switch (phl_rx->type) { + case RTW_RX_TYPE_WIFI: + // phl_recycle_rx_buf would in phl_rx_handle_normal or core_rx. +#ifdef CONFIG_PHL_RX_PSTS_PER_PKT + if (false == phl_rx_proc_wait_phy_sts(phl_info, phl_rx)) { + PHL_TRACE(COMP_PHL_PSTS, _PHL_DEBUG_, + "phl_rx_proc_wait_phy_sts() return false \n"); + phl_rx_handle_normal(phl_info, phl_rx); + } +#else + phl_rx_handle_normal(phl_info, phl_rx); +#endif + break; + case RTW_RX_TYPE_PPDU_STATUS: + phl_rx_proc_ppdu_sts(phl_info, phl_rx); +#ifdef CONFIG_PHL_RX_PSTS_PER_PKT + phl_rx_proc_phy_sts(phl_info, phl_rx); +#endif + phl_recycle_rx_buf(phl_info, phl_rx); + break; + case RTW_RX_TYPE_TX_WP_RELEASE_HOST: + #ifdef CONFIG_PHL_USB_RELEASE_RPT_ENABLE + _phl_rx_handle_wp_report_usb(phl_info, phl_rx); + phl_recycle_rx_buf(phl_info, phl_rx); + phl_rx = NULL; + break; + #endif /* CONFIG_PHL_USB_RELEASE_RPT_ENABLE */ + case RTW_RX_TYPE_C2H: + case RTW_RX_TYPE_CHANNEL_INFO: + case RTW_RX_TYPE_TX_RPT: + case RTW_RX_TYPE_DFS_RPT: + case RTW_RX_TYPE_MAX: + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "phl_rx_process_usb(): Unsupported case:%d, please check it\n", + phl_rx->type); + phl_recycle_rx_buf(phl_info, phl_rx); + phl_rx = NULL; + break; + default : + PHL_TRACE(COMP_PHL_RECV, _PHL_INFO_, "[3] %s:: [Warning] rx type(0x%X) recycle \n", + __FUNCTION__, phl_rx->type); + phl_recycle_rx_buf(phl_info, phl_rx); + phl_rx = NULL; + break; + } + } while(phl_rxhead != NULL); +} + +static enum rtw_phl_status phl_rx_usb(struct phl_info_t *phl_info) +{ + void *drv = phl_to_drvpriv(phl_info); + struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci; + struct rtw_phl_rx_pkt *phl_rx = NULL; + struct rtw_rx_buf_ring *rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool; + struct rtw_rx_buf *rx_buf = NULL; + _os_list* obj = NULL; + + while (rx_buf_ring->pend_rxbuf_list.cnt) + { + PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[3] %s:: pend_rxbuf_list.cnt =%d\n", + __FUNCTION__, rx_buf_ring->pend_rxbuf_list.cnt ); + + if(pq_pop(drv, &rx_buf_ring->pend_rxbuf_list, &obj, _first, _irq)) { + rx_buf = (struct rtw_rx_buf*)obj; + } + else + break; + + switch(rx_buf->pipe_idx){ + case WLAN_IN_MPDU_PIPE_IDX: + { + /* phl_rx maybe single or link-list */ + phl_rx = phl_get_single_rx(phl_info, rx_buf); + + if(phl_rx) + { + phl_rx_process_usb(phl_info, phl_rx); + } + } + break; + + case WLAN_IN_INTERRUPT_PIPE_IDX: + break; + + default: + break; + } + + if (phl_rx==NULL && NULL != rx_buf) { + PHL_TRACE(COMP_PHL_RECV, _PHL_INFO_, "[3] %s:: [Error] [%p] pipe_idx = %d \n", + __FUNCTION__, rx_buf, rx_buf->pipe_idx); + phl_release_rxbuf_usb(phl_info, rx_buf, 0, RTW_RX_TYPE_MAX); // usb doesn't care rtw_rx_type + rx_buf=NULL; + } + + } + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status phl_pltfm_tx_usb(struct phl_info_t *phl_info, + void *pkt) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_h2c_pkt *h2c_pkt = (struct rtw_h2c_pkt *)pkt; + struct phl_usb_tx_buf_resource *reso = NULL; + struct phl_usb_buf *tx_buf = NULL; + u8 bulk_id = 0; + u8 dma_ch = rtw_hal_get_fwcmd_queue_idx(phl_info->hal); + + reso = (struct phl_usb_tx_buf_resource *)phl_info->hci->txbuf_pool; + + if (reso) + tx_buf = dequeue_usb_buf(phl_info, &reso->h2c_txbuf_list); + else + PHL_DBG("%s, phl_usb_tx_buf_resource == NULL\n", __func__); + + if (tx_buf) { + tx_buf->buffer = (u8 *)h2c_pkt; + + bulk_id = rtw_hal_get_bulkout_id(phl_info->hal, + dma_ch, 0); + pstatus = os_usb_tx(phl_to_drvpriv(phl_info), + (u8 *)tx_buf, bulk_id, h2c_pkt->data_len, h2c_pkt->vir_head); + if (pstatus == RTW_PHL_STATUS_FAILURE) { + phl_enqueue_idle_h2c_pkt(phl_info, + (struct rtw_h2c_pkt *)tx_buf->buffer); + tx_buf->buffer = NULL; + enqueue_usb_buf(phl_info, + &reso->h2c_txbuf_list, tx_buf, _tail); + } + } + return pstatus; +} + +static void _phl_free_h2c_pkt_buf_usb(struct phl_info_t *phl_info, + struct rtw_h2c_pkt *_h2c_pkt) +{ + struct rtw_h2c_pkt *h2c_pkt = _h2c_pkt; + + _os_kmem_free(phl_to_drvpriv(phl_info), + h2c_pkt->vir_head, h2c_pkt->buf_len); +} + +enum rtw_phl_status _phl_alloc_h2c_pkt_buf_usb(struct phl_info_t *phl_info, + struct rtw_h2c_pkt *_h2c_pkt, + u32 buf_len) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_h2c_pkt *h2c_pkt = _h2c_pkt; + + h2c_pkt->vir_head = _os_kmem_alloc(phl_to_drvpriv(phl_info), buf_len); + + if (h2c_pkt->vir_head) + pstatus = RTW_PHL_STATUS_SUCCESS; + + return pstatus; +} + +void *phl_get_txbd_buf_usb(struct phl_info_t *phl_info) +{ + return NULL; +} + +void *phl_get_rxbd_buf_usb(struct phl_info_t *phl_info) +{ + return NULL; +} + +void phl_recycle_rx_pkt_usb(struct phl_info_t *phl_info, + struct rtw_phl_rx_pkt *phl_rx) +{ + /* Using r.os_priv seems imprperly. */ + /* free netbuff for error case*/ + if (phl_rx->r.os_priv) + _os_free_netbuf(phl_to_drvpriv(phl_info), + phl_rx->r.pkt_list[0].vir_addr, + phl_rx->r.os_netbuf_len, + phl_rx->r.os_priv); + + phl_recycle_rx_buf(phl_info, phl_rx); +} + +enum rtw_phl_status phl_register_trx_hdlr_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct rtw_phl_handler *tx_handler = &phl_info->phl_tx_handler; + struct rtw_phl_handler *rx_handler = &phl_info->phl_rx_handler; + void *drv_priv = phl_to_drvpriv(phl_info); + + tx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; /* tasklet */ + tx_handler->callback = _phl_tx_callback_usb; + tx_handler->context = phl_info; + tx_handler->drv_priv = drv_priv; + pstatus = phl_register_handler(phl_info->phl_com, tx_handler); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + PHL_ERR("%s : register tx_handler fail.\n", __FUNCTION__); + + rx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; + rx_handler->callback = _phl_rx_callback_usb; + rx_handler->context = phl_info; + rx_handler->drv_priv = drv_priv; + pstatus = phl_register_handler(phl_info->phl_com, rx_handler); + if (RTW_PHL_STATUS_SUCCESS != pstatus) + PHL_ERR("%s : register rx_handler fail.\n", __FUNCTION__); + + return pstatus; +} + +void phl_tx_watchdog_usb(struct phl_info_t *phl_info) +{ + +} + +static struct phl_hci_trx_ops ops= { + .hci_trx_init = phl_trx_init_usb, + .hci_trx_deinit = phl_trx_deinit_usb, + .prepare_tx = phl_prepare_tx_usb, + .recycle_tx_buf = phl_tx_release_buf_usb, + .recycle_rx_buf = phl_release_rxbuf_usb, + .tx = phl_tx_usb, + .rx = phl_rx_usb, + .trx_cfg = phl_trx_cfg_usb, + .trx_stop = phl_trx_stop_usb, + .pend_rxbuf = phl_pend_rxbuf_usb, + .pltfm_tx = phl_pltfm_tx_usb, + .alloc_h2c_pkt_buf = _phl_alloc_h2c_pkt_buf_usb, + .free_h2c_pkt_buf = _phl_free_h2c_pkt_buf_usb, + .trx_reset = phl_trx_reset_usb, + .trx_resume = phl_trx_resume_usb, + .req_tx_stop = phl_req_tx_stop_usb, + .req_rx_stop = phl_req_rx_stop_usb, + .is_tx_pause = phl_is_tx_sw_pause_usb, + .is_rx_pause = phl_is_rx_sw_pause_usb, + .get_txbd_buf = phl_get_txbd_buf_usb, + .get_rxbd_buf = phl_get_rxbd_buf_usb, + .recycle_rx_pkt = phl_recycle_rx_pkt_usb, + .register_trx_hdlr = phl_register_trx_hdlr_usb, + .rx_handle_normal = phl_rx_handle_normal, + .tx_watchdog = phl_tx_watchdog_usb +}; + +enum rtw_phl_status phl_hook_trx_ops_usb(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + + if (NULL != phl_info) { + phl_info->hci_trx_ops = &ops; + pstatus = RTW_PHL_STATUS_SUCCESS; + } + + return pstatus; +} + +u8 rtw_phl_usb_tx_ep_id(void *phl, u16 macid, u8 tid, u8 band) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + u8 dma_ch = 0; + u8 bulk_id = 0; + dma_ch = rtw_hal_tx_chnl_mapping(phl_info->hal, macid, + tid, band); + bulk_id = rtw_hal_get_bulkout_id(phl_info->hal, + dma_ch, 0); + return bulk_id; +} + +enum rtw_phl_status +phl_force_usb_switch(struct phl_info_t *phl_info, u32 speed) +{ + + if(speed <= RTW_USB_SPEED_HIGH) + rtw_hal_force_usb_switch(phl_info->hal, USB_2_0); + else if(speed < RTW_USB_SPEED_MAX) + rtw_hal_force_usb_switch(phl_info->hal, USB_3_0); + PHL_INFO("%s (%d) !!\n", __FUNCTION__, speed); + + return RTW_PHL_STATUS_SUCCESS; +} +#ifdef CONFIG_CMD_DISP +enum rtw_phl_status +rtw_phl_cmd_force_usb_switch(void *phl, u32 speed, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + u32 usb_speed = speed; + + if (cmd_type == PHL_CMD_DIRECTLY) + psts = phl_force_usb_switch(phl_info, usb_speed); + else { + psts = phl_cmd_enqueue(phl_info, + band_idx, + MSG_EVT_FORCE_USB_SW, + (u8*)&usb_speed, + sizeof(u32), + NULL, + PHL_CMD_WAIT, + 0); + + if (is_cmd_failure(psts)) { + /* Send cmd success, but wait cmd fail*/ + psts = RTW_PHL_STATUS_FAILURE; + } else if (psts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + psts = RTW_PHL_STATUS_FAILURE; + } + } + return psts; +} +#else /*for FSM*/ +enum rtw_phl_status +rtw_phl_cmd_force_usb_switch(void *phl, u32 speed, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + return phl_force_usb_switch((struct phl_info_t *)phl, speed); +} +#endif /*CONFIG_CMD_DISP*/ + +enum rtw_phl_status +rtw_phl_cmd_get_usb_speed(void *phl, u32* speed, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + +#ifdef CONFIG_CMD_DISP + psts = phl_cmd_enqueue(phl_info, + band_idx, + MSG_EVT_GET_USB_SPEED, + (u8*)speed, + sizeof(u32), + NULL, + PHL_CMD_WAIT, + 0); + if (is_cmd_failure(psts)) { + /* Send cmd success, but wait cmd fail*/ + psts = RTW_PHL_STATUS_FAILURE; + } else if (psts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + psts = RTW_PHL_STATUS_FAILURE; + } +#else + psts = phl_get_cur_usb_speed(phl_info, speed); +#endif + return psts; +} +enum rtw_phl_status +rtw_phl_cmd_get_usb_support_ability(void *phl, u32* ability, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + +#ifdef CONFIG_CMD_DISP + psts = phl_cmd_enqueue(phl_info, + band_idx, + MSG_EVT_GET_USB_SW_ABILITY, + (u8*)ability, + sizeof(u32), + NULL, + PHL_CMD_WAIT, + 0); + + if (is_cmd_failure(psts)) { + /* Send cmd success, but wait cmd fail*/ + psts = RTW_PHL_STATUS_FAILURE; + } else if (psts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + psts = RTW_PHL_STATUS_FAILURE; + } +#else + psts = phl_get_usb_support_ability(phl_info, ability); +#endif + return psts; +} + +enum rtw_phl_status phl_get_cur_usb_speed(struct phl_info_t *phl_info, u32 *speed) +{ + u32 mode = rtwl_hal_get_cur_usb_mode(phl_info->hal); + struct hci_info_t *hci = phl_info->hci; + + switch(mode) { + case USB_1_1: + *speed = RTW_USB_SPEED_FULL; + hci->usb_bulkout_size = USB_FULL_SPEED_BULK_SIZE; + break; + case USB_2_0: + *speed = RTW_USB_SPEED_HIGH; + hci->usb_bulkout_size = USB_HIGH_SPEED_BULK_SIZE; + break; + case USB_3_0: + *speed = RTW_USB_SPEED_SUPER; + hci->usb_bulkout_size = USB_SUPER_SPEED_BULK_SIZE; + break; + default: + *speed = RTW_USB_SPEED_UNKNOWN; + break; + } + PHL_PRINT("%s (%d) bulk size(%d) !!\n", __FUNCTION__, *speed, + phl_info->hci->usb_bulkout_size); + + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status +phl_get_usb_support_ability(struct phl_info_t *phl_info, u32 *ability) +{ + *ability = rtwl_hal_get_usb_support_ability(phl_info->hal); + /* refer enum rtw_usb_sw_ability for definition of ability */ + PHL_INFO("%s (%d) !!\n", __FUNCTION__, *ability); + return RTW_PHL_STATUS_SUCCESS; +} + diff --git a/phl/hci/phl_trx_usb.h b/phl/hci/phl_trx_usb.h new file mode 100644 index 0000000..97f5762 --- /dev/null +++ b/phl/hci/phl_trx_usb.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_TRX_USB_H_ +#define _PHL_TRX_USB_H_ + +#define MGMT_TID 8 +#define PKT_OFFSET_DUMMY (8) +// +// USB specific. +// +#define WLAN_IN_MPDU_PIPE_IDX 0 //EP1, RxIn Pipe +#define WLAN_IN_INTERRUPT_PIPE_IDX 1 //EP7, HISR or C2H Cmd In Pipe + +struct rtw_rx_buf_ring { + // + // Memory block of phl_usb_rx_pkt. + // + struct rtw_rx_buf *rxbufblock; + u32 block_cnt_alloc; // Total number of rtw_rx_buf allocated. + u32 total_blocks_size; // block_cnt_alloc * sizeof( rtw_rx_buf ) + + struct phl_queue idle_rxbuf_list; + struct phl_queue busy_rxbuf_list; + struct phl_queue pend_rxbuf_list; + _os_timer deferred_timer; +}; + + +struct phl_usb_tx_buf_resource { + struct phl_queue idle_txbuf_list; + struct phl_queue mgmt_txbuf_list; + struct phl_queue h2c_txbuf_list; +}; + + +enum rtw_phl_status +phl_hook_trx_ops_usb(struct phl_info_t *phl_info); +enum rtw_phl_status +phl_force_usb_switch(struct phl_info_t *phl_info, u32 speed); +/* refer enum rtw_usb_speed for definition of speed */ +enum rtw_phl_status +phl_get_cur_usb_speed(struct phl_info_t *phl_info, u32 *speed); +/* refer enum phl_usb_ability for definition of ability */ +enum rtw_phl_status +phl_get_usb_support_ability(struct phl_info_t *phl_info, u32 *ability); + +#endif /* _PHL_TRX_USB_H_ */ diff --git a/phl/phl.mk b/phl/phl.mk new file mode 100644 index 0000000..34c9c80 --- /dev/null +++ b/phl/phl.mk @@ -0,0 +1,121 @@ +########### COMMON PATH ################################# +ifeq ($(CONFIG_HWSIM), y) + HAL = hal_sim +else + ifeq ($(CONFIG_WIFI_6), y) + HAL = hal_g6 + else + HAL = hal + endif +endif + +ifeq ($(CONFIG_PHL_ARCH), y) +phl_path := phl/ +phl_path_d1 := $(src)/phl/$(HAL) +else +phl_path := +phl_path_d1 := $(src)/$(HAL) +endif + +_PHL_FILES := $(phl_path)phl_init.o \ + $(phl_path)phl_debug.o \ + $(phl_path)phl_tx.o \ + $(phl_path)phl_rx.o \ + $(phl_path)phl_rx_agg.o \ + $(phl_path)phl_api_drv.o \ + $(phl_path)phl_role.o \ + $(phl_path)phl_sta.o \ + $(phl_path)phl_mr.o \ + $(phl_path)phl_sec.o \ + $(phl_path)phl_chan.o \ + $(phl_path)phl_sw_cap.o \ + $(phl_path)phl_util.o \ + $(phl_path)phl_pkt_ofld.o \ + $(phl_path)phl_connect.o \ + $(phl_path)phl_chan_info.o \ + $(phl_path)phl_wow.o\ + $(phl_path)phl_dm.o \ + $(phl_path)phl_chnlplan.o \ + $(phl_path)phl_country.o \ + $(phl_path)phl_chnlplan_6g.o \ + $(phl_path)phl_regulation.o \ + $(phl_path)phl_regulation_6g.o \ + $(phl_path)phl_led.o \ + $(phl_path)phl_trx_mit.o \ + $(phl_path)phl_acs.o \ + $(phl_path)phl_mcc.o \ + $(phl_path)phl_ecsa.o \ + $(phl_path)test/phl_dbg_cmd.o \ + $(phl_path)test/phl_ser_dbg_cmd.o \ + $(phl_path)phl_msg_hub.o \ + $(phl_path)phl_sound.o \ + $(phl_path)phl_twt.o \ + $(phl_path)phl_notify.o \ + $(phl_path)phl_sound_cmd.o \ + $(phl_path)phl_p2pps.o \ + $(phl_path)phl_thermal.o \ + $(phl_path)phl_txpwr.o + +ifeq ($(CONFIG_POWER_SAVE), y) +_PHL_FILES += $(phl_path)phl_ps.o \ + $(phl_path)test/phl_ps_dbg_cmd.o \ + $(phl_path)phl_cmd_ps.o +endif + +ifeq ($(CONFIG_FSM), y) +_PHL_FILES += $(phl_path)phl_fsm.o \ + $(phl_path)phl_cmd_fsm.o \ + $(phl_path)phl_cmd_job.o \ + $(phl_path)phl_ser_fsm.o \ + $(phl_path)phl_btc_fsm.o \ + $(phl_path)phl_scan_fsm.o \ + $(phl_path)phl_sound_fsm.o +endif + +_PHL_FILES += $(phl_path)phl_cmd_dispatch_engine.o\ + $(phl_path)phl_cmd_dispatcher.o\ + $(phl_path)phl_cmd_dispr_controller.o \ + $(phl_path)phl_cmd_ser.o \ + $(phl_path)phl_cmd_general.o \ + $(phl_path)phl_cmd_scan.o \ + $(phl_path)phl_cmd_btc.o \ + $(phl_path)phl_sound_cmd.o \ + $(phl_path)phl_watchdog.o + +ifeq ($(CONFIG_PCI_HCI), y) +_PHL_FILES += $(phl_path)hci/phl_trx_pcie.o +endif +ifeq ($(CONFIG_USB_HCI), y) +_PHL_FILES += $(phl_path)hci/phl_trx_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_PHL_FILES += $(phl_path)hci/phl_trx_sdio.o +endif + +ifeq ($(CONFIG_PHL_CUSTOM_FEATURE), y) +_PHL_FILES += $(phl_path)custom/phl_custom.o +ifeq ($(CONFIG_PHL_CUSTOM_FEATURE_FB), y) +_PHL_FILES += $(phl_path)custom/phl_custom_fb.o +endif +endif + +ifeq ($(CONFIG_PHL_TEST_SUITE), y) +_PHL_FILES += $(phl_path)test/trx_test.o +_PHL_FILES += $(phl_path)test/test_module.o +_PHL_FILES += $(phl_path)test/cmd_disp_test.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_config.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_tx.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_rx.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_reg.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_efuse.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_txpwr.o +_PHL_FILES += $(phl_path)test/mp/phl_test_mp_cal.o +_PHL_FILES += $(phl_path)test/verify/phl_test_verify.o +_PHL_FILES += $(phl_path)test/verify/dbcc/phl_test_dbcc.o +endif + +OBJS += $(_PHL_FILES) + +EXTRA_CFLAGS += -I$(phl_path_d1) +include $(phl_path_d1)/hal.mk diff --git a/phl/phl_acs.c b/phl/phl_acs.c new file mode 100644 index 0000000..9cff472 --- /dev/null +++ b/phl/phl_acs.c @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_ACS_C_ +#include "phl_headers.h" + +#ifdef CONFIG_RTW_ACS +void phl_acs_mntr_trigger(struct phl_info_t *phl_info, u8 idx, u16 channel, u16 monitor_time) +{ + struct auto_chan_sel *acs = &phl_info->acs; + + if ((idx < 0) || (idx >= MAX_CHANNEL_NUM)) { + PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx); + return; + } else if (idx == 0) { + _os_mem_set(phl_to_drvpriv(phl_info), acs, 0, sizeof(struct auto_chan_sel)); + } + + acs->curr_idx = idx; + acs->chset[idx] = channel; + + rtw_hal_acs_mntr_trigger(phl_info->hal, monitor_time); +} + +void phl_acs_mntr_result(struct phl_info_t *phl_info) +{ + struct auto_chan_sel *acs = &phl_info->acs; + u8 idx = acs->curr_idx; + enum rtw_hal_status status; + struct auto_chan_sel_report rpt = {0}; + + status = rtw_hal_acs_mntr_result(phl_info->hal, &rpt); + + + if (idx >= MAX_CHANNEL_NUM) { + PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx); + return; + } + + if (status == RTW_HAL_STATUS_SUCCESS) { + acs->clm_ratio[idx] = rpt.clm_ratio; + acs->nhm_pwr[idx] = rpt.nhm_pwr; + } +} + +u16 rtw_phl_acs_get_channel_by_idx(void *phl, u8 idx) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct auto_chan_sel *acs = &phl_info->acs; + + if (idx >= MAX_CHANNEL_NUM) { + PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx); + return 0; + } + + return acs->chset[idx]; +} + +u8 rtw_phl_acs_get_clm_ratio_by_idx(void *phl, u8 idx) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct auto_chan_sel *acs = &phl_info->acs; + + if (idx >= MAX_CHANNEL_NUM) { + PHL_ERR("%s [ACS] idx(%d) is invalid\n", __func__, idx); + return 0; + } + + return acs->clm_ratio[idx]; +} + +s8 rtw_phl_noise_query_by_idx(void *phl, u8 idx) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct auto_chan_sel *acs = &phl_info->acs; + + if (idx >= MAX_CHANNEL_NUM) { + PHL_ERR("%s [ACS] idx(%d) is invalid\n", __func__, idx); + return 0; + } + + /* dBm = RPL - 110 */ + return acs->nhm_pwr[idx] - 110; +} +#endif /* CONFIG_RTW_ACS */ + +void rtw_phl_get_env_rpt(void *phl, struct rtw_env_report *env_rpt, struct rtw_wifi_role_t *wrole) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + + rtw_hal_env_rpt(hal_com, env_rpt, wrole); + +} diff --git a/phl/phl_acs.h b/phl/phl_acs.h new file mode 100644 index 0000000..b4234bb --- /dev/null +++ b/phl/phl_acs.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_ACS_H_ +#define _PHL_ACS_H_ + +/* avoid clm/nhm result not ready when scan done */ +#define MONITOR_TIME_TOLERANCE 15 + +void phl_acs_mntr_trigger(struct phl_info_t *phl_info, u8 ch_idx, u16 channel, u16 monitor_time); +void phl_acs_mntr_result(struct phl_info_t *phl_info); + +#endif /*_PHL_ACS_H_*/ diff --git a/phl/phl_api.h b/phl/phl_api.h new file mode 100644 index 0000000..fccd0ff --- /dev/null +++ b/phl/phl_api.h @@ -0,0 +1,684 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_API_H_ +#define _PHL_API_H_ + +u8 rtw_phl_read8(void *phl, u32 addr); +u16 rtw_phl_read16(void *phl, u32 addr); +u32 rtw_phl_read32(void *phl, u32 addr); +void rtw_phl_write8(void *phl, u32 addr, u8 val); +void rtw_phl_write16(void *phl, u32 addr, u16 val); +void rtw_phl_write32(void *phl, u32 addr, u32 val); + +u32 rtw_phl_read_macreg(void *phl, u32 offset, u32 bit_mask); +void rtw_phl_write_macreg(void *phl, + u32 offset, u32 bit_mask, u32 data); +u32 rtw_phl_read_bbreg(void *phl, u32 offset, u32 bit_mask); +void rtw_phl_write_bbreg(void *phl, + u32 offset, u32 bit_mask, u32 data); +u32 rtw_phl_read_rfreg(void *phl, + enum rf_path path, u32 offset, u32 bit_mask); +void rtw_phl_write_rfreg(void *phl, + enum rf_path path, u32 offset, u32 bit_mask, u32 data); +enum rtw_phl_status rtw_phl_interrupt_handler(void *phl); +void rtw_phl_enable_interrupt(void *phl); +void rtw_phl_disable_interrupt(void *phl); +bool rtw_phl_recognize_interrupt(void *phl); +void rtw_phl_clear_interrupt(void *phl); +void rtw_phl_restore_interrupt(void *phl); + + +#ifdef PHL_PLATFORM_LINUX +void rtw_phl_mac_reg_dump(void *sel, void *phl); +void rtw_phl_bb_reg_dump(void *sel, void *phl); +void rtw_phl_bb_reg_dump_ex(void *sel, void *phl); +void rtw_phl_rf_reg_dump(void *sel, void *phl); +#endif +bool rtw_phl_get_sec_cam(void *phl, u16 num, u8 *buf, u16 size); +bool rtw_phl_get_addr_cam(void *phl, u16 num, u8 *buf, u16 size); + +struct rtw_phl_com_t *rtw_phl_get_com(void *phl); +enum rtw_phl_status rtw_phl_init(void *drv_priv, void **phl, + struct rtw_ic_info *ic_info); +void rtw_phl_deinit(void *phl); + +void rtw_phl_watchdog_init(void *phl, + u16 period, + void (*core_sw_wdog)(void *drv_priv), + void (*core_hw_wdog)(void *drv_priv)); +void rtw_phl_watchdog_deinit(void *phl); +void rtw_phl_watchdog_start(void *phl); +void rtw_phl_watchdog_stop(void *phl); + +enum rtw_phl_status rtw_phl_trx_alloc(void *phl); +void rtw_phl_trx_free(void *phl); +void rtw_phl_trx_free_handler(void *phl); +void rtw_phl_trx_free_sw_rsc(void *phl); +void rtw_phl_cap_pre_config(void *phl); +enum rtw_phl_status rtw_phl_preload(void *phl); +enum rtw_phl_status rtw_phl_start(void *phl); +void rtw_phl_stop(void *phl); +bool rtw_phl_is_init_completed(void *phl); + +void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson); +enum rtw_phl_status rtw_phl_ps_set_rf_state(void *phl, u8 band_idx, enum rtw_rf_state rf_state); + +enum rtw_phl_status rtw_phl_suspend(void *phl, struct rtw_phl_stainfo_t *sta, u8 wow_en); +enum rtw_phl_status rtw_phl_resume(void *phl, struct rtw_phl_stainfo_t *sta, u8 *hw_reinit); + +enum rtw_phl_status rtw_phl_tx_req_notify(void *phl); +enum rtw_phl_status rtw_phl_add_tx_req(void *phl, struct rtw_xmit_req *tx_req); +void rtw_phl_tx_stop(void *phl); +void rtw_phl_tx_resume(void *phl); +u16 rtw_phl_tring_rsc(void *phl, u16 macid, u8 tid); +u16 rtw_phl_query_new_rx_num(void *phl); +struct rtw_recv_pkt *rtw_phl_query_rx_pkt(void *phl); + +void rtw_phl_rx_deferred_In_token(void *phl); +void rtw_phl_post_in_complete(void *phl, void *rxobj, u32 inbuf_len, u8 status_code); +enum rtw_phl_status rtw_phl_return_rxbuf(void *phl, u8* rxpkt); + +enum rtw_phl_status rtw_phl_recycle_tx_buf(void *phl, u8 *tx_buf_ptr); + +enum rtw_phl_status +rtw_phl_cmd_cfg_ampdu(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +void rtw_phl_proc_cmd(void *phl, char proc_cmd, + struct rtw_proc_cmd *incmd, char *output, u32 out_len); + +void rtw_phl_get_fw_ver(void *phl, char *ver_str, u16 len); + +enum rtw_fw_status rtw_phl_get_fw_status(void *phl); + +/* command thread jobs */ +enum rtw_phl_status rtw_phl_job_run_func(void *phl, + void *func, void *priv, void *parm, char *name); + +/*WIFI Role management section*/ +u8 rtw_phl_wifi_role_alloc(void *phl, u8 *mac_addr, enum role_type type, + u8 ridx, struct rtw_wifi_role_t **wifi_role, bool ignore_hw_fail); + +enum rtw_phl_status +rtw_phl_cmd_wrole_change(void *phl, + struct rtw_wifi_role_t *wrole, + enum wr_chg_id chg_id, u8 *chg_info, u8 chg_info_len, + enum phl_cmd_type cmd_type, u32 cmd_timeout); + +void rtw_phl_wifi_role_free(void *phl, u8 role_idx); + +/*WIFI sta_info management section*/ +struct rtw_phl_stainfo_t * +rtw_phl_alloc_stainfo_sw(void *phl, + u8 *sta_addr, + struct rtw_wifi_role_t *wrole); + +enum rtw_phl_status +rtw_phl_free_stainfo_sw(void *phl, struct rtw_phl_stainfo_t *sta); + +enum rtw_phl_status +rtw_phl_cmd_alloc_stainfo(void *phl, + struct rtw_phl_stainfo_t **sta, + u8 *sta_addr, + struct rtw_wifi_role_t *wrole, + bool alloc, + bool only_hw, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +enum rtw_phl_status +rtw_phl_cmd_change_stainfo(void *phl, + struct rtw_phl_stainfo_t *sta, enum sta_chg_id chg_id, + u8 *chg_info, u8 chg_info_len, + enum phl_cmd_type cmd_type, u32 cmd_timeout); + +enum rtw_phl_status +rtw_phl_cmd_update_media_status(void *phl, + struct rtw_phl_stainfo_t *sta, + u8 *sta_addr, + bool is_connect, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +struct rtw_phl_stainfo_t * +rtw_phl_get_stainfo_self(void *phl, struct rtw_wifi_role_t *wrole); + +struct rtw_phl_stainfo_t * +rtw_phl_get_stainfo_by_addr(void *phl, struct rtw_wifi_role_t *wrole, u8 *addr); + +struct rtw_phl_stainfo_t * +rtw_phl_get_stainfo_by_macid(void *phl, u16 macid); + +u8 +rtw_phl_get_sta_rssi(struct rtw_phl_stainfo_t *sta); + +enum rtw_phl_status +rtw_phl_query_rainfo(void *phl, struct rtw_phl_stainfo_t *phl_sta, + struct rtw_phl_rainfo *ra_info); + +void rtw_phl_sta_up_rx_bcn(void *phl, struct rtw_bcn_pkt_info *info); + +/*macid management section, temporary for debuge*/ +u16 +rtw_phl_get_macid_max_num(void *phl); + +u16 +rtw_phl_wrole_bcmc_id_get(void *phl, struct rtw_wifi_role_t *wrole); + +u8 +rtw_phl_macid_is_bmc(void *phl, u16 macid); + +u8 +rtw_phl_macid_is_used(void *phl, u16 macid); + +enum rtw_phl_status +rtw_phl_cmd_add_key(void *phl, + struct rtw_phl_stainfo_t *sta, + struct phl_sec_param_h *crypt, + u8 *keybuf, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +enum rtw_phl_status +rtw_phl_cmd_del_key(void *phl, + struct rtw_phl_stainfo_t *sta, + struct phl_sec_param_h *crypt, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); +/* phy msg forwarder functions*/ +enum rtw_phl_status rtw_phl_msg_hub_register_recver(void* phl, + struct phl_msg_receiver* ctx, enum phl_msg_recver_layer layer); +enum rtw_phl_status rtw_phl_msg_hub_update_recver_mask(void* phl, + enum phl_msg_recver_layer layer, u8* mdl_id, u32 len, u8 clr); +enum rtw_phl_status rtw_phl_msg_hub_deregister_recver(void* phl, + enum phl_msg_recver_layer layer); +enum rtw_phl_status rtw_phl_msg_hub_send(void* phl, + struct phl_msg_attribute* attr, struct phl_msg* msg); + + +u8 rtw_phl_trans_sec_mode(u8 unicast, u8 multicast); + +u8 rtw_phl_get_sec_cam_idx(void *phl, struct rtw_phl_stainfo_t *sta, + u8 keyid, u8 key_type); + +void rtw_phl_test_txtb_cfg(struct rtw_phl_com_t* phl_com, void *buf, + u32 buf_len, u8 *cfg_bssid, u16 cfg_aid, u8 cfg_bsscolor); +/* command dispatcher module section*/ +enum rtw_phl_status rtw_phl_register_module(void *phl, u8 band_idx, + enum phl_module_id id, + struct phl_bk_module_ops* ops); +enum rtw_phl_status rtw_phl_deregister_module(void *phl,u8 band_idx, + enum phl_module_id id); +u8 rtw_phl_is_fg_empty(void *phl, u8 band_idx); +/* opt: refer to enum phl_msg_opt */ +enum rtw_phl_status rtw_phl_send_msg_to_dispr(void *phl, struct phl_msg* msg, + struct phl_msg_attribute* attr, u32* msg_hdl); +enum rtw_phl_status rtw_phl_cancel_dispr_msg(void *phl, u8 band_idx, u32* msg_hdl); + +enum rtw_phl_status rtw_phl_add_cmd_token_req(void *phl, u8 band_idx, + struct phl_cmd_token_req* req, u32* req_hdl); +enum rtw_phl_status rtw_phl_cancel_cmd_token(void *phl, u8 band_idx, u32* req_hdl); +enum rtw_phl_status rtw_phl_set_cur_cmd_info(void *phl, u8 band_idx, + struct phl_module_op_info* op_info); +enum rtw_phl_status rtw_phl_query_cur_cmd_info(void *phl, u8 band_idx, + struct phl_module_op_info* op_info); + +enum rtw_phl_status rtw_phl_free_cmd_token(void *phl, u8 band_idx, u32* req_hdl); +enum rtw_phl_status rtw_phl_set_bk_module_info(void *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info* op_info); +enum rtw_phl_status rtw_phl_query_bk_module_info(void *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info* op_info); +enum rtw_phl_status rtw_phl_set_msg_disp_seq(void *phl, + struct phl_msg_attribute *attr, + struct msg_self_def_seq* seq); + +/* BA session management */ +void rtw_phl_stop_rx_ba_session(void *phl, struct rtw_phl_stainfo_t *sta, + u16 tid); +enum rtw_phl_status +rtw_phl_start_rx_ba_session(void *phl, struct rtw_phl_stainfo_t *sta, + u8 dialog_token, u16 timeout, u16 start_seq_num, + u16 ba_policy, u16 tid, u16 buf_size); +void rtw_phl_rx_bar(void *phl, struct rtw_phl_stainfo_t *sta, u8 tid, u16 seq); +void rtw_phl_flush_reorder_buf(void *phl, struct rtw_phl_stainfo_t *sta); +enum rtw_phl_status +rtw_phl_enter_mon_mode(void *phl, struct rtw_wifi_role_t *wrole); +enum rtw_phl_status +rtw_phl_leave_mon_mode(void *phl, struct rtw_wifi_role_t *wrole); +#ifdef RTW_PHL_BCN +enum rtw_phl_status rtw_phl_free_bcn_entry(void *phl, struct rtw_wifi_role_t *wrole); +enum rtw_phl_status +rtw_phl_cmd_issue_beacon(void *phl, + struct rtw_wifi_role_t *wifi_role, + struct rtw_bcn_info_cmn *bcn_cmn, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); +enum rtw_phl_status +rtw_phl_cmd_stop_beacon(void *phl, + struct rtw_wifi_role_t *wifi_role, + u8 stop, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); +#endif + +#ifdef CONFIG_CMD_DISP +enum rtw_phl_status +rtw_phl_cmd_chg_op_chdef(struct rtw_wifi_role_t *wrole, + struct rtw_chan_def *new_chdef, bool cmd_wait, u32 cmd_timeout, + void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status)); + + +enum rtw_phl_status +rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef, + bool do_rfk, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +enum rtw_phl_status +rtw_phl_cmd_enqueue(void *phl, + enum phl_band_idx band_idx, + enum phl_msg_evt_id evt_id, + u8 *cmd_buf, + u32 cmd_len, + void (*core_cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status), + enum phl_cmd_type cmd_type, + u32 cmd_timeout); + +#endif /*CONFIG_CMD_DISP*/ + +u8 rtw_phl_get_cur_ch(struct rtw_wifi_role_t *wifi_role); +enum rtw_phl_status +rtw_phl_get_cur_hal_chdef(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *cur_chandef); + +enum band_type rtw_phl_get_band_type(u8 chan); +u8 rtw_phl_get_center_ch(u8 ch, + enum channel_width bw, enum chan_offset offset); + +enum rtw_phl_status +rtw_phl_cmd_dfs_tx_pause(struct rtw_wifi_role_t *wifi_role, bool pause, + enum phl_cmd_type cmd_type, u32 cmd_timeout); + +u8 +rtw_phl_get_operating_class( + struct rtw_chan_def chan_def +); + +bool +rtw_phl_get_chandef_from_operating_class( + u8 channel, + u8 operating_class, + struct rtw_chan_def *chan_def +); +/* + * export API from sw cap module + */ +void rtw_phl_final_cap_decision(void *phl); + + +enum rtw_phl_status +rtw_phl_get_dft_proto_cap(void *phl, u8 hw_band, enum role_type rtype, + struct protocol_cap_t *role_proto_cap); +enum rtw_phl_status +rtw_phl_get_dft_cap(void *phl, u8 hw_band, struct role_cap_t *role_cap); + +void rtw_phl_mac_dbg_status_dump(void *phl, u32 *val, u8 *en); + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_phl_status +rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param); +#endif +/* + * API for config channel info CR + */ +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_phl_status +rtw_phl_cmd_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta, + u8 enable, enum phl_cmd_type cmd_type, u32 cmd_timeout); +enum rtw_phl_status rtw_phl_query_chan_info(void *phl, u32 buf_len, + u8* chan_info_buffer, u32 *length, struct csi_header_t *csi_header); +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +void rtw_phl_set_edcca_mode(void *phl, enum rtw_edcca_mode mode); +enum rtw_edcca_mode rtw_phl_get_edcca_mode(void *phl); + +bool rtw_phl_set_user_def_chplan(void *phl, struct rtw_user_def_chplan *udef); +bool rtw_phl_valid_regulation_domain(u8 domain); +bool rtw_phl_regulation_set_domain(void *phl, u8 domain, + enum regulation_rsn reason); +bool rtw_phl_regulation_set_country(void *phl, char *country, + enum regulation_rsn reason); +bool rtw_phl_regulation_set_capability(void *phl, + enum rtw_regulation_capability capability); +bool rtw_phl_regulation_query_chplan( + void *phl, enum rtw_regulation_query type, + struct rtw_chlist *filter, + struct rtw_regulation_chplan *plan); +bool rtw_phl_query_specific_chplan(void *phl, u8 domain, + struct rtw_regulation_chplan *plan); +bool rtw_phl_query_country_chplan(char *country, + struct rtw_regulation_country_chplan *country_chplan); +bool rtw_phl_generate_scan_instance(struct instance_strategy *strategy, + struct rtw_regulation_chplan *chplan, + struct instance *inst); +bool rtw_phl_scan_instance_insert_ch(void *phl, struct instance *inst, + enum band_type band, u8 channel, + u8 strategy_period); +bool rtw_phl_regulation_valid_channel(void *phl, enum band_type band, + u16 channel, u8 reject); +bool rtw_phl_regulation_dfs_channel(void *phl, enum band_type band, + u16 channel, bool *dfs); +bool rtw_phl_query_regulation_info(void *phl, struct rtw_regulation_info *info); +bool rtw_phl_regulation_query_ch(void *phl, enum band_type band, u8 channel, + struct rtw_regulation_channel *ch); +u8 rtw_phl_get_domain_regulation_2g(u8 domain); +u8 rtw_phl_get_domain_regulation_5g(u8 domain); + +enum rtw_phl_status rtw_phl_get_mac_addr_efuse(void* phl, u8 *addr); + +/** + * rtw_phl_usb_tx_ep_id - query USB tx end point index + * identified by macid, tid and band + * @macid: input target macid is 0 ~ 127 +* @tid: input target tid, range is 0 ~ 7 + * @band: input target band, 0 for band 0 / 1 for band 1 + * + * returns corresponding end point idx of a specific tid + */ +u8 rtw_phl_usb_tx_ep_id(void *phl, u16 macid, u8 tid, u8 band); + +enum rtw_phl_status +rtw_phl_cfg_trx_path(void* phl, enum rf_path tx, u8 tx_nss, + enum rf_path rx, u8 rx_nss); + +void rtw_phl_reset_stat_ma_rssi(struct rtw_phl_com_t *phl_com); + +u8 +rtw_phl_get_ma_rssi(struct rtw_phl_com_t *phl_com, + enum rtw_rssi_type rssi_type); + +bool rtw_phl_chanctx_chk(void *phl, struct rtw_wifi_role_t *wifi_role, + u8 chan, enum channel_width bw, enum chan_offset offset); +bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role, + u8 *chan, enum channel_width *bw, enum chan_offset *offset); +int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chan_def); +enum rtw_phl_status rtw_phl_chanctx_del_no_self(void *phl, struct rtw_wifi_role_t *wifi_role); +int rtw_phl_mr_get_chanctx_num(void *phl, struct rtw_wifi_role_t *wifi_role); +enum rtw_phl_status rtw_phl_mr_get_chandef(void *phl, struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chandef); +enum rtw_phl_status rtw_phl_mr_upt_chandef(void *phl, struct rtw_wifi_role_t *wifi_role); + +#ifdef CONFIG_MCC_SUPPORT +u8 rtw_phl_mr_query_mcc_inprogress (void *phl, struct rtw_wifi_role_t *wrole, + enum rtw_phl_mcc_chk_inprocess_type check_type); +#endif + +u8 rtw_phl_mr_dump_mac_addr(void *phl, + struct rtw_wifi_role_t *wifi_role); +u8 rtw_phl_mr_buddy_dump_mac_addr(void *phl, + struct rtw_wifi_role_t *wifi_role); +enum rtw_phl_status +rtw_phl_mr_rx_filter(void *phl, struct rtw_wifi_role_t *wrole); + +#ifdef CONFIG_FSM +enum rtw_phl_status +rtw_phl_mr_offch_hdl(void *phl, + struct rtw_wifi_role_t *wrole, + bool off_ch, + void *obj_priv, + u8 (*issue_null_data)(void *priv, u8 ridx, bool ps), + struct rtw_chan_def *chandef); +#endif +void rtw_phl_mr_ops_init (void *phl, struct rtw_phl_mr_ops *mr_ops); + +#ifdef PHL_MR_PROC_CMD +void rtw_phl_mr_dump_info(void *phl, bool show_caller); +void rtw_phl_mr_dump_band_ctl(void *phl, bool show_caller); +bool rtw_phl_chanctx_test(void *phl, struct rtw_wifi_role_t *wifi_role, bool is_add, + u8 *chan, enum channel_width *bw, enum chan_offset *offset); +#endif +void rtw_phl_sta_dump_info(void *phl, bool show_caller, struct rtw_wifi_role_t *wr, u8 mode); + +bool rtw_phl_mr_query_info(void *phl, struct rtw_wifi_role_t *wrole, + struct mr_query_info *info); + +u8 rtw_phl_mr_get_opch_list(void *phl, struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef_list, u8 list_size); + +void rtw_phl_mr_dump_cur_chandef(void *phl, struct rtw_wifi_role_t *wifi_role); + +enum mr_op_mode +rtw_phl_mr_get_opmode(void *phl, struct rtw_wifi_role_t *wrole); + +void rtw_phl_led_set_ctrl_mode(void *phl, enum rtw_led_id led_id, + enum rtw_led_ctrl_mode ctrl_mode); +void rtw_phl_led_set_toggle_intervals(void *phl, u8 intervals_idx, + u32 *intervals, u8 intervals_len); +void rtw_phl_led_set_action(void *phl, enum rtw_led_event event, + enum rtw_led_state state_condition, + struct rtw_led_action_args_t *action_args_arr, + u8 action_args_arr_len, u32 toggle_delay_unit); +void rtw_phl_led_control(void *phl, enum rtw_led_event led_event); + +#ifdef CONFIG_RTW_ACS +u16 rtw_phl_acs_get_channel_by_idx(void *phl, u8 ch_idx); +u8 rtw_phl_acs_get_clm_ratio_by_idx(void *phl, u8 ch_idx); +s8 rtw_phl_noise_query_by_idx(void *phl, u8 ch_idx); +#endif /* CONFIG_RTW_ACS */ + +void rtw_phl_get_env_rpt(void *phl, struct rtw_env_report *env_rpt, struct rtw_wifi_role_t *wrole); + +#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP +enum rtw_phl_status +rtw_phl_bfee_ctrl(void *phl, struct rtw_wifi_role_t *wrole, bool ctrl); +#endif + +enum rtw_phl_status +rtw_phl_snd_init_ops_send_ndpa(void *phl, + enum rtw_phl_status (*snd_send_ndpa)(void *, + struct rtw_wifi_role_t *, + u8 *, + u32 *, + enum channel_width)); + +u8 rtw_phl_snd_chk_in_progress(void *phl); + +enum rtw_phl_status +rtw_phl_sound_start(void *phl, u8 wrole_idx, u8 st_dlg_tkn, u8 period, u8 test_flag); + +enum rtw_phl_status +rtw_phl_sound_abort(void *phl); + +enum rtw_phl_status +rtw_phl_set_power_lmt(void *phl, u8 hw_band); + +s8 rtw_phl_get_power_limit(void *phl, u8 hw_band, + u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel); + +void +rtw_phl_enable_ext_pwr_lmt(void *phl, u8 hw_band, + struct rtw_phl_ext_pwr_lmt_info *ext_pwr_lmt_info); + +void rtw_phl_init_ppdu_sts_para(struct rtw_phl_com_t *phl_com, + bool en_psts_per_pkt, bool psts_ampdu, + u8 rx_fltr); + +enum rtw_phl_status rtw_phl_rf_on(void *phl); +enum rtw_phl_status rtw_phl_rf_off(void *phl); + + +#ifdef CONFIG_PHL_TWT +enum rtw_phl_status +rtw_phl_twt_alloc_twt_config(void *phl, struct rtw_wifi_role_t *role, + struct rtw_phl_twt_setup_info setup_info, u8 benable, u8 *id); + +enum rtw_phl_status +rtw_phl_twt_free_twt_config(void *phl, u8 id); + +enum rtw_phl_status +rtw_phl_twt_enable_twt_config(void *phl, u8 id); + +enum rtw_phl_status +rtw_phl_twt_free_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role); + +enum rtw_phl_status +rtw_phl_twt_disable_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role); + +enum rtw_phl_status +rtw_phl_twt_enable_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role); + +enum rtw_phl_status +rtw_phl_twt_add_sta_info(void *phl, struct rtw_phl_stainfo_t *phl_sta, + u8 config_id, u8 id); + +enum rtw_phl_status +rtw_phl_twt_teardown_sta(void *phl, struct rtw_phl_stainfo_t *phl_sta, + struct rtw_phl_twt_flow_field *twt_flow, u8 *bitmap); + +enum rtw_phl_status +rtw_phl_twt_get_new_flow_id(void *phl, struct rtw_phl_stainfo_t *phl_sta, u8 *id); + + +enum rtw_phl_status +rtw_phl_twt_accept_for_sta_mode(void *phl, struct rtw_phl_stainfo_t *phl_sta, + struct rtw_phl_twt_setup_info *setup_info, u8 *id); + +enum rtw_phl_status +rtw_phl_twt_teardown_for_sta_mode(void *phl, struct rtw_phl_stainfo_t *phl_sta, + struct rtw_phl_twt_flow_field *twt_flow); + +enum rtw_phl_status +rtw_phl_twt_delete_all_sta_info(void *phl, struct rtw_phl_stainfo_t *phl_sta, + u8 *bitmap); + +enum rtw_phl_status +rtw_phl_twt_get_target_wake_time(void *phl, u8 port, u8 id, u16 offset, u32 *tsf_h, + u32 *tsf_l); + +enum rtw_phl_status +rtw_phl_twt_sta_announce_to_fw(void *phl, u16 macid); + +enum rtw_phl_status +rtw_phl_twt_handle_c2h(void *phl_com, void *c); + +enum rtw_phl_status +rtw_phl_twt_fill_twt_element(struct rtw_phl_twt_element *twt_ele, u8 *buf, + u8 *length); + +enum rtw_phl_status +rtw_phl_twt_fill_flow_field(struct rtw_phl_twt_flow_field *twt_flow, u8 *buf, + u16 *length); +enum rtw_phl_status +rtw_phl_twt_parse_element(u8 *twt_ele, u16 length, + struct rtw_phl_twt_element *twt_element); + +enum rtw_phl_status +rtw_phl_twt_parse_setup_info(u8 *pkt, u16 length, + struct rtw_phl_twt_setup_info *setup_info); + +enum rtw_phl_status +rtw_phl_twt_parse_flow_field(u8 *ie_twt_flow, u16 length, + struct rtw_phl_twt_flow_field *twt_flow); +#endif /* CONFIG_PHL_TWT */ + +enum rtw_phl_status +rtw_phl_snd_cmd_set_vht_gid(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_gid_pos_tbl *tbl); + +enum rtw_phl_status +rtw_phl_snd_cmd_set_aid(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + u16 aid); + +#ifdef RTW_WKARD_P2PPS_REFINE +#ifdef CONFIG_PHL_P2PPS +enum rtw_phl_status +rtw_phl_p2pps_noa_update(void *phl, struct rtw_phl_noa_desc *in_desc); + +void +rtw_phl_p2pps_init_ops(void *phl, struct rtw_phl_p2pps_ops *ops); + +void rtw_phl_p2pps_noa_disable_all(void *phl, struct rtw_wifi_role_t *w_role); +#endif +#endif +enum rtw_phl_status +rtw_phl_snd_cmd_set_vht_gid(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_gid_pos_tbl *tbl); + +void rtw_phl_event_notify(void *phl, enum phl_msg_evt_id event, + struct rtw_wifi_role_t *wrole); +void rtw_phl_notification(void *phl, + enum phl_msg_evt_id event, + struct rtw_wifi_role_t *wrole); +void rtw_phl_dev_terminate_ntf(void *phl); + +enum rtw_phl_status +rtw_phl_cmd_force_usb_switch(void *phl, u32 speed, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout); +enum rtw_phl_status +rtw_phl_cmd_get_usb_speed(void *phl, u32* speed, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout); +enum rtw_phl_status +rtw_phl_cmd_get_usb_support_ability(void *phl, u32* ability, + enum phl_band_idx band_idx, + enum phl_cmd_type cmd_type, u32 cmd_timeout); +u8 rtw_phl_get_sta_mgnt_rssi(struct rtw_phl_stainfo_t *psta); + +enum rtw_phl_status +rtw_phl_txsts_rpt_config(void *phl, struct rtw_phl_stainfo_t *phl_sta); + +#ifdef CONFIG_USB_HCI +/* tx_ok/tx_fail are from release report*/ +enum rtw_phl_status +rtw_phl_get_tx_ok_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_ok_cnt, + enum phl_ac_queue qsel); + +enum rtw_phl_status +rtw_phl_get_tx_fail_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_fail_cnt, + enum phl_ac_queue qsel); + +/* tx retry is from ra sts report.*/ +enum rtw_phl_status +rtw_phl_get_tx_retry_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_retry_cnt, + enum phl_ac_queue qsel); +#endif /* CONFIG_USB_HCI */ + +enum rtw_rx_status rtw_phl_get_rx_status(void *phl); + +void rtw_phl_dbg_dump_rx(void *phl, struct rtw_wifi_role_t *wrole); + +/****************************************************************************** + * + * TX power APIs + * + *****************************************************************************/ +const char *rtw_phl_get_pw_lmt_regu_type_str(void *phl, enum band_type band); + +bool rtw_phl_get_pwr_lmt_en(void *phl, u8 band_idx); + +enum rtw_phl_status rtw_phl_set_tx_power(void *phl, u8 band_idx); + +#endif /*_PHL_API_H_*/ + diff --git a/phl/phl_api_drv.c b/phl/phl_api_drv.c new file mode 100644 index 0000000..9bf11b2 --- /dev/null +++ b/phl/phl_api_drv.c @@ -0,0 +1,159 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_API_DRV_C_ +#include "phl_headers.h" + +void *rtw_phl_get_txbd_buf(struct rtw_phl_com_t *phl_com) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + + return phl_info->hci_trx_ops->get_txbd_buf(phl_info); +} + +void *rtw_phl_get_rxbd_buf(struct rtw_phl_com_t *phl_com) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + + return phl_info->hci_trx_ops->get_rxbd_buf(phl_info); +} + +struct rtw_h2c_pkt *rtw_phl_query_h2c_pkt(struct rtw_phl_com_t *phl_com, + enum rtw_h2c_pkt_type type) +{ + struct rtw_h2c_pkt *h2c_pkt = NULL; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + + h2c_pkt = (struct rtw_h2c_pkt *)phl_query_idle_h2c_pkt(phl_info, type); + + if (!h2c_pkt) + phl_dump_h2c_pool_stats(phl_info->h2c_pool); + + return h2c_pkt; +} + +enum rtw_phl_status rtw_phl_pltfm_tx(struct rtw_phl_com_t *phl_com, + struct rtw_h2c_pkt *pkt) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + + #ifdef CONFIG_PCI_HCI + struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops; + hci_trx_ops->recycle_busy_h2c(phl_info); + #endif + + pstatus = phl_info->hci_trx_ops->pltfm_tx(phl_info, pkt); + + return pstatus; +} + +void rtw_phl_proc_cmd(void *phl, char proc_cmd, + struct rtw_proc_cmd *incmd, + char *output, u32 out_len) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct hal_info_t *hal_info = (struct hal_info_t *)phl_info->hal; + + if (RTW_PROC_CMD_PHL == proc_cmd) + rtw_phl_dbg_proc_cmd(phl_info, incmd, output, out_len); + else if (RTW_PROC_CMD_CORE == proc_cmd) + rtw_phl_dbg_core_cmd(phl_info, incmd, output, out_len); + else + rtw_hal_proc_cmd(hal_info, proc_cmd, incmd, output, out_len); +} + +void rtw_phl_get_fw_ver(void *phl, char *ver_str, u16 len) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + rtw_hal_get_fw_ver(phl_info->hal, ver_str, len); +} + +enum rtw_fw_status rtw_phl_get_fw_status(void *phl) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + return rtw_hal_get_fw_status(phl_info->hal); +} + +enum rtw_phl_status rtw_phl_msg_hub_hal_send(struct rtw_phl_com_t *phl_com, + struct phl_msg_attribute* attr, struct phl_msg* msg) +{ + return phl_msg_hub_send((struct phl_info_t*)phl_com->phl_priv, attr, msg); +} +void rtw_phl_test_txtb_cfg(struct rtw_phl_com_t* phl_com, + void *buf, u32 buf_len, u8 *cfg_bssid, u16 cfg_aid, u8 cfg_bsscolor) +{ + /* Get parameters from MP UL */ + u8 ui_bssid[6]={0x00, 0x09, 0x08, 0x07, 0x06, 0x05}; + u16 ui_aid = 2; + u8 ui_bsscolor = 1; + u8 cfg; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_wifi_role_t *role = &phl_com->wifi_roles[0]; + struct rtw_phl_stainfo_t *sta = rtw_phl_get_stainfo_self( + phl_com->phl_priv, role); + + cfg = (u8)*((u8 *)buf); + switch (cfg) { + case 0: + /* disable */ + role->mstate = MLME_NO_LINK; + _os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr, + role->mac_addr, MAC_ALEN); + rtw_hal_update_sta_entry(phl_info->hal, sta, false); + rtw_hal_role_cfg(phl_info->hal, role); + break; + + case 1: + role->mstate = MLME_LINKED; + _os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr, + cfg_bssid, MAC_ALEN); + sta->wmode = WLAN_MD_MAX; + sta->aid = cfg_aid; + sta->asoc_cap.bsscolor = cfg_bsscolor; + sta->asoc_cap.pkt_padding = 2; + rtw_hal_update_sta_entry(phl_info->hal, sta, false); + rtw_hal_role_cfg(phl_info->hal, role); + break; + + case 2: + role->mstate = MLME_LINKED; + _os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr, + ui_bssid, MAC_ALEN); + sta->wmode = WLAN_MD_MAX; + sta->aid = ui_aid; + sta->asoc_cap.bsscolor = ui_bsscolor; + sta->asoc_cap.pkt_padding = 2; + rtw_hal_update_sta_entry(phl_info->hal, sta, false); + rtw_hal_role_cfg(phl_info->hal, role); + break; default: + break; + } +} + +void rtw_phl_pkt_ofld_reset_all_entry(struct rtw_phl_com_t* phl_com) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + + phl_pkt_ofld_reset_all_entry(phl_info); +} + +void rtw_phl_dbg_dump_rx(void *phl, struct rtw_wifi_role_t *wrole) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + phl_rx_dbg_dump(phl_info, wrole->hw_band); +} \ No newline at end of file diff --git a/phl/phl_api_drv.h b/phl/phl_api_drv.h new file mode 100644 index 0000000..87b8ff0 --- /dev/null +++ b/phl/phl_api_drv.h @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_API_DRV_H_ +#define _PHL_API_DRV_H_ + +void *rtw_phl_get_txbd_buf(struct rtw_phl_com_t *phl_com); +void *rtw_phl_get_rxbd_buf(struct rtw_phl_com_t *phl_com); + +/** + * rtw_phl_query_h2c_pkt - provide h2c buffer for halmac + * @phl_com: see struct rtw_phl_com_t + * @type: the type of h2c buf + * + * returns struct rtw_h2c_pkt* + */ +struct rtw_h2c_pkt *rtw_phl_query_h2c_pkt(struct rtw_phl_com_t *phl_com, + enum rtw_h2c_pkt_type type); + +/** + * rtw_phl_pltfm_tx - h2c platform transmit + * @phl_com: see struct rtw_phl_com_t + * @pkt: the h2c pkt + * + * returns enum RTW_PHL_STATUS + */ +enum rtw_phl_status rtw_phl_pltfm_tx(struct rtw_phl_com_t *phl_com, + struct rtw_h2c_pkt *pkt); + +enum rtw_phl_status rtw_phl_msg_hub_hal_send(struct rtw_phl_com_t *phl_com, + struct phl_msg_attribute* attr, struct phl_msg* msg); + +struct rtw_phl_stainfo_t * +rtw_phl_get_stainfo_self(void *phl, struct rtw_wifi_role_t *wrole); +struct rtw_phl_stainfo_t * +rtw_phl_get_stainfo_by_macid(void *phl, u16 macid); + + +/* For hal wow use */ +void rtw_phl_pkt_ofld_reset_all_entry(struct rtw_phl_com_t *phl_com); + + +bool rtw_phl_query_regulation_info(void *phl, struct rtw_regulation_info *info); + +enum band_type rtw_phl_get_band_type(u8 chan); +u8 rtw_phl_get_center_ch(u8 ch, + enum channel_width bw, enum chan_offset offset); + +bool rtw_phl_btc_send_cmd(struct rtw_phl_com_t *phl_com, + u8 *buf, u32 len, u16 ev_id); + +#ifdef CONFIG_PHL_CHANNEL_INFO +/* Channel info queue operation*/ +u32 rtw_phl_get_chaninfo_idle_number(void *drvpriv, struct rtw_phl_com_t *phl_com); +u32 rtw_phl_get_chaninfo_busy_number(void *drvpriv, struct rtw_phl_com_t *phl_com); +struct chan_info_t *rtw_phl_query_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com); + +struct chan_info_t *rtw_phl_query_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com); + +struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void *drvpriv, struct rtw_phl_com_t *phl_com); + +void rtw_phl_enqueue_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com, + struct chan_info_t *chan_info_pkt); + +struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com, + struct chan_info_t *chan_info_pkt); +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +enum rtw_phl_status rtw_phl_ser_l2_notify(struct rtw_phl_com_t *phl_com); + +struct rtw_wifi_role_t * +rtw_phl_get_wrole_by_ridx(struct rtw_phl_com_t *phl_com, u8 rold_idx); + +#ifdef CONFIG_CMD_DISP +enum rtw_phl_status +rtw_phl_cmd_notify(struct rtw_phl_com_t *phl_com, + enum phl_msg_evt_id event, + void *hal_cmd, + u8 hw_idx); +#endif /* CONFIG_CMD_DISP */ + +enum rtw_phl_status phl_ps_hal_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req); + +#endif /* _PHL_API_DRV_H_ */ + diff --git a/phl/phl_btc.h b/phl/phl_btc.h new file mode 100644 index 0000000..f4d78f3 --- /dev/null +++ b/phl/phl_btc.h @@ -0,0 +1,34 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_BTC_H__ +#define __PHL_BTC_H__ + +/* For EXTERNAL application to notify btc (expose) */ +/* @phl: refer to phl_infi_t + * @notify: notification event + * @ntfy: notify information (optional) + * return value: + * 0: no wait + * 1: have to wait call back info->ntfy_cb() + * -1: Failure + */ +int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify, + struct rtw_phl_btc_ntfy *info); +void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate); +void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg); +void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type); +u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type); + +#endif /* __PHL_BTC_H__ */ diff --git a/phl/phl_btc_def.h b/phl/phl_btc_def.h new file mode 100644 index 0000000..dd4fba6 --- /dev/null +++ b/phl/phl_btc_def.h @@ -0,0 +1,181 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_BTC_DEF_H__ +#define __PHL_BTC_DEF_H__ + +#define RTW_PHL_BTC_CTRL_BUF 40 +#define RTW_PHL_BTC_FWINFO_BUF 1280 + + +/***************************************** + * Please contact the member of BTC submodule if you + * need to revise this section + *****************************************/ +#define RTW_BTINFO_MAXLEN 10 +#define RTW_SCBD_MAXLEN 10 + +#define BTC_C2H_CAT 2 /* C2H Category for OutSrc */ +#define BTC_CLASS_MIN 0x10 +#define BTC_CLASS_FEV 0x12 +#define BTC_CLASS_MAX 0x17 + +enum { + BTC_FEV_REPORT = 0, + BTC_FEV_BT_INFO = 1, + BTC_FEV_BT_SCBD = 2, + BTC_FEV_BT_REG = 3 +}; +/*****************************************/ + +enum { + BTC_HMSG_TMR_EN = 0x0, + BTC_HMSG_BT_REG_READBACK = 0x1, + BTC_HMSG_SET_BT_REQ_SLOT = 0x2, + BTC_HMSG_FW_EV = 0x3, + BTC_HMSG_BT_LINK_CHG = 0x4, + BTC_HMSG_MAX +}; + +enum { + BTC_CTRL_TYPE_MANUAL, + BTC_CTRL_TYPE_EN_REPORT, + BTC_CTRL_TYPE_SET_SLOTS, + BTC_CTRL_TYPE_SET_MREGS, + BTC_CTRL_TYPE_SET_TDMA, + BTC_CTRL_TYPE_SET_1SLOT, + BTC_CTRL_TYPE_SET_POLICY, + BTC_CTRL_TYPE_SET_GPIO_DBG, + BTC_CTRL_TYPE_SEND_HUB_MSG, + BTC_CTRL_TYPE_TEST, + BTC_CTRL_TYPE_MAX +}; + +enum { + BTC_TIMER_PERIODIC, + BTC_TIMER_WL_SPECPKT, + BTC_TIMER_WL_RFKTO, + BTC_TIMER_BT_A2DPPLAY, + BTC_TIMER_MAX +}; + +enum RTW_PHL_BTC_CTRL_TYPE { + PHL_BTC_CTRL_MANUAL, + PHL_BTC_CTRL_MAX +}; + +enum { + PHL_BTC_CNTFY_BTINFO, + PHL_BTC_CNTFY_MAX +}; + +enum PHL_BTC_NTFY_REASON { + PHL_BTC_NTFY_RSN_PERIOTIC +}; + +enum RTW_PHL_BTC_NOTIFY { + PHL_BTC_NTFY_SCAN_START, + PHL_BTC_NTFY_SCAN_STOP, + PHL_BTC_NTFY_COEX_INFO, + PHL_BTC_NTFY_ROLE_INFO, + PHL_BTC_NTFY_CTRL, + PHL_BTC_NTFY_FWINFO, + PHL_BTC_NTFY_RADIO_STATE, + PHL_BTC_NTFY_WLSTA, + PHL_BTC_NTFY_PACKET_EVT, + PHL_BTC_NTFY_TIMER, + PHL_BTC_NTFY_MAX +}; + +enum { + BTC_MODE_NORMAL, + BTC_MODE_WL, + BTC_MODE_BT, + BTC_MODE_WLOFF, + BTC_MODE_MAX +}; + +enum { + BTC_RFCTRL_WL_OFF, + BTC_RFCTRL_WL_ON, + BTC_RFCTRL_LPS_WL_ON, + BTC_RFCTRL_FW_CTRL, + BTC_RFCTRL_MAX +}; + +struct rtw_phl_btc_ops { + void (*print)(const char *msg); +}; + +struct rtw_phl_btc_coex_info_param { + u8 query_type; +}; + +struct rtw_phl_btc_role_info_param { + u8 role_id; + enum role_state rstate; +}; + +struct rtw_phl_btc_wl_sta_param { + u8 role_id; + u16 mac_id; + u8 reason; +}; + +struct rtw_phl_btc_pkt_param { + u8 role_id; + u8 pkt_evt_type; +}; + +struct rtw_phl_btc_ctrl_param { + u8 type; + u16 len; + u8 buf[RTW_PHL_BTC_CTRL_BUF]; +}; + +struct rtw_phl_btc_fwinfo_param { + u8 c2h_class; + u8 c2h_func; +}; + +struct rtw_phl_btc_radio_state_param { + u8 rf_on; +}; + +struct rtw_phl_btc_tmr_param { + void *timer; +}; + +struct rtw_phl_btc_ntfy { + enum RTW_PHL_BTC_NOTIFY notify; + struct rtw_phl_btc_ops *ops; + + /* real parameter for different notifications */ + union { + struct rtw_phl_btc_coex_info_param cinfo; + struct rtw_phl_btc_role_info_param rinfo; + struct rtw_phl_btc_ctrl_param ctrl; + struct rtw_phl_btc_radio_state_param rfst; + struct rtw_phl_btc_fwinfo_param finfo; + struct rtw_phl_btc_wl_sta_param wsta; + struct rtw_phl_btc_pkt_param pkt; + struct rtw_phl_btc_tmr_param tmr; + } u; + + void *priv; + int (*ntfy_cb)(void *priv, enum RTW_PHL_BTC_NOTIFY ntfy, + struct rtw_phl_btc_ntfy *info); +}; + +#endif /* __PHL_BTC_DEF_H__ */ diff --git a/phl/phl_btc_fsm.c b/phl/phl_btc_fsm.c new file mode 100644 index 0000000..64615f8 --- /dev/null +++ b/phl/phl_btc_fsm.c @@ -0,0 +1,464 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "phl_headers.h" + +#ifdef CONFIG_FSM +#include "phl_btc_fsm.h" + +struct btc_obj { + struct fsm_main *fsm; + struct fsm_obj *fsm_obj; + struct phl_info_t *phl_info; + + struct rtw_phl_btc_ntfy *ntfy; +}; + +enum BTC_STATE_ST { + BTC_ST_IDLE, + BTC_ST_SERVICE +}; + +enum BTC_EV_ID { + BTC_EV_START, + BTC_EV_UPDATE_ROLE_INFO, + BTC_EV_FWINFO, + BTC_EV_WLSTA, + BTC_EV_TIMER, + BTC_EV_PACKET_EVT, + BTC_EV_MAX +}; + +static int btc_idle_st_hdl(void *obj, u16 event, void *param); +static int btc_service_st_hdl(void *obj, u16 event, void *param); + +/* STATE table */ +static struct fsm_state_ent btc_state_tbl[] = { + ST_ENT(BTC_ST_IDLE, btc_idle_st_hdl), + ST_ENT(BTC_ST_SERVICE, btc_service_st_hdl) + //{BTC_ST_MAX, "BTC_ST_MAX", NULL} /* ST_MAX for fsm safety checking */ +}; + +/* EVENT table */ +static struct fsm_event_ent btc_event_tbl[] = { + EV_ENT(BTC_EV_START), + EV_ENT(BTC_EV_UPDATE_ROLE_INFO), + EV_ENT(BTC_EV_FWINFO), + EV_ENT(BTC_EV_WLSTA), + EV_DBG(BTC_EV_TIMER), + EV_ENT(BTC_EV_PACKET_EVT), + EV_ENT(BTC_EV_MAX) /* EV_MAX for fsm safety checking */ +}; + + +/* + * btc idle handler + */ +static int btc_idle_st_hdl(void *obj, u16 event, void *param) +{ + struct btc_obj *pbtc = (struct btc_obj *)obj; + + FSM_DBG(pbtc->fsm, "[BTC], %s, event : 0x%x\n", __func__, event); + switch (event) { + case FSM_EV_STATE_IN: + break; + + case FSM_EV_TIMER_EXPIRE: + break; + + case BTC_EV_START: + phl_fsm_state_goto(pbtc->fsm_obj, BTC_ST_SERVICE); + break; + + case FSM_EV_STATE_OUT: + break; + + default: + break; + } + return 0; +} + +static int btc_service_st_hdl(void *obj, u16 event, void *param) +{ + struct btc_obj *pbtc = (struct btc_obj *)obj; + struct phl_info_t *phl_info = pbtc->phl_info; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + int rtn = FSM_FREE_PARAM; + + FSM_DBG(pbtc->fsm, "[BTC], %s, event : 0x%x\n", __func__, event); + switch (event) { + case FSM_EV_STATE_IN: + break; + + case BTC_EV_UPDATE_ROLE_INFO: + if (param) { + struct rtw_phl_btc_role_info_param *prinfo = NULL; + struct rtw_wifi_role_t *wrole = NULL; + struct rtw_phl_stainfo_t *sta = NULL; + + pbtc->ntfy = param; + prinfo = &pbtc->ntfy->u.rinfo; + + if (prinfo->role_id < MAX_WIFI_ROLE_NUMBER) { + wrole = &phl_com->wifi_roles[prinfo->role_id]; + sta = rtw_phl_get_stainfo_self(phl_info, wrole); + } +#ifdef CONFIG_BTCOEX + rtw_hal_btc_update_role_info_ntfy(phl_info->hal, + prinfo->role_id, wrole, sta, prinfo->rstate); +#endif + if (pbtc->ntfy->ntfy_cb) + pbtc->ntfy->ntfy_cb(pbtc->ntfy->priv, + pbtc->ntfy->notify, + pbtc->ntfy); + + rtn = FSM_FREE_PARAM; + } + break; + + case BTC_EV_FWINFO: +#ifdef CONFIG_BTCOEX + rtw_hal_btc_fwinfo_ntfy(phl_info->hal); +#endif + break; + + case BTC_EV_TIMER: + { +#ifdef CONFIG_BTCOEX + struct rtw_phl_btc_tmr_param *tmr = NULL; + + pbtc->ntfy = param; + tmr = &pbtc->ntfy->u.tmr; + + rtw_hal_btc_timer(phl_info->hal, tmr->timer); +#endif + } + break; + + case BTC_EV_PACKET_EVT: + if (param) { + struct rtw_phl_btc_pkt_param *pkt = NULL; + struct rtw_wifi_role_t *wrole = NULL; + pbtc->ntfy = param; + pkt = &pbtc->ntfy->u.pkt; + + if (pkt->role_id < MAX_WIFI_ROLE_NUMBER) { + wrole = &phl_com->wifi_roles[pkt->role_id]; + } +#ifdef CONFIG_BTCOEX + rtw_hal_btc_packet_event_ntfy(phl_info->hal, + pkt->pkt_evt_type); +#endif + if (pbtc->ntfy->ntfy_cb) + pbtc->ntfy->ntfy_cb(pbtc->ntfy->priv, + pbtc->ntfy->notify, + pbtc->ntfy); + + rtn = FSM_FREE_PARAM; + } + break; + + case FSM_EV_TIMER_EXPIRE: + break; + + case FSM_EV_CANCEL: + phl_fsm_state_goto(pbtc->fsm_obj, BTC_ST_IDLE); + break; + + case FSM_EV_STATE_OUT: + phl_fsm_cancel_alarm(pbtc->fsm_obj); + break; + + default: + break; + } + return rtn; +} + +static void btc_dump_obj(void *obj, char *s, int *sz) +{ + /* nothing to do for now */ +} + +static void btc_dump_fsm(void *fsm, char *s, int *sz) +{ + /* nothing to do for now */ +} + +/* For EXTERNAL application to create a btc FSM */ +/* @root: FSM root structure + * @phl_info: private data structure to invoke hal/phl function + * + * return + * fsm_main: FSM main structure (Do NOT expose) + */ +struct fsm_main *phl_btc_new_fsm(struct fsm_root *root, + struct phl_info_t *phl_info) +{ + void *d = phl_to_drvpriv(phl_info); + struct fsm_main *fsm = NULL; + struct rtw_phl_fsm_tb tb; + + _os_mem_set(d, &tb, 0, sizeof(tb)); + tb.max_state = sizeof(btc_state_tbl)/sizeof(btc_state_tbl[0]); + tb.max_event = sizeof(btc_event_tbl)/sizeof(btc_event_tbl[0]); + tb.state_tbl = btc_state_tbl; + tb.evt_tbl = btc_event_tbl; + tb.dump_obj = btc_dump_obj; + tb.dump_obj = btc_dump_fsm; + tb.dbg_level = FSM_DBG_INFO; + tb.evt_level = FSM_DBG_INFO; + + fsm = phl_fsm_init_fsm(root, "btc", phl_info, &tb); + + return fsm; +} + +/* For EXTERNAL application to destory btc fsm */ +/* @fsm: see fsm_main + */ +void phl_btc_destory_fsm(struct fsm_main *fsm) +{ + if (fsm == NULL) + return; + + /* deinit fsm local variable if has */ + + /* call FSM Framewro to deinit fsm */ + phl_fsm_deinit_fsm(fsm); +} + +/* For EXTERNAL application to create btcoex object */ +/* @fsm: FSM main structure which created by phl_btc_new_fsm() + * @phl_info: private data structure to invoke hal/phl function + * + * return + * btc_obj: structure of command object (Do NOT expose) + */ +struct btc_obj *phl_btc_new_obj(struct fsm_main *fsm, + struct phl_info_t *phl_info) +{ + struct fsm_obj *obj; + struct btc_obj *pbtc; + + pbtc = phl_fsm_new_obj(fsm, (void **)&obj, sizeof(*pbtc)); + + if (pbtc == NULL || obj == NULL) { + /* TODO free fsm; currently will be freed in deinit process */ + FSM_ERR(fsm, "btc: malloc obj fail\n"); + return NULL; + } + pbtc->fsm = fsm; + pbtc->fsm_obj = obj; + pbtc->phl_info = phl_info; + + return pbtc; +} + +/* For EXTERNAL application to destory btc object */ +/* @pbtc: local created command object + * + */ +void phl_btc_destory_obj(struct btc_obj *pbtc) +{ + if (pbtc == NULL) + return; + + /* inform FSM framewory to recycle fsm_obj */ + phl_fsm_destory_obj(pbtc->fsm_obj); +} + +/* For EXTERNAL application to start btcoex service (expose) */ +/* @pbtc: btc object + */ +enum rtw_phl_status phl_btc_start(struct btc_obj *pbtc) +{ + void *d = phl_to_drvpriv(pbtc->phl_info); + enum rtw_phl_status phl_status = RTW_PHL_STATUS_SUCCESS; + struct fsm_msg *msg; + + /* Start FSM */ + phl_status = phl_fsm_start_fsm(pbtc->fsm); + if (phl_status != RTW_PHL_STATUS_SUCCESS) + return phl_status; + + if (pbtc->fsm_obj == NULL) + return RTW_PHL_STATUS_FAILURE; + + /* NEW message to start btc object */ + msg = phl_fsm_new_msg(pbtc->fsm_obj, BTC_EV_START); + if (msg == NULL) { + FSM_ERR(pbtc->fsm, "btc: alloc msg fail\n"); + return RTW_PHL_STATUS_RESOURCE; + } + if (phl_fsm_sent_msg(pbtc->fsm_obj, msg) != RTW_PHL_STATUS_SUCCESS) { + _os_kmem_free(d, msg, sizeof(*msg)); + return RTW_PHL_STATUS_FAILURE; + } + + return phl_status; +} + +/* For EXTERNAL application to stop btc service (expose) */ +/* @pbtc: btc to be cancelled + */ +enum rtw_phl_status phl_btc_cancel(struct btc_obj *pbtc) +{ + return phl_fsm_cancel_obj(pbtc->fsm_obj); +} + +/* For EXTERNAL application to notify btc (expose) */ +/* @phl: refer to phl_infi_t + * @notify: notification event + * @ntfy: notify information (optional) + * return value: + * 0: no wait + * 1: have to wait call back info->ntfy_cb() + * -1: Failure + */ +int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify, + struct rtw_phl_btc_ntfy *ntfy) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct btc_obj *pbtc = phl_info->btc_obj; + int wait = 0, sz = 0; + u16 event; + + if (ntfy) + sz = sizeof(*ntfy); + + switch (notify) { + case PHL_BTC_NTFY_ROLE_INFO: + event = BTC_EV_UPDATE_ROLE_INFO; + break; + case PHL_BTC_NTFY_FWINFO: + event = BTC_EV_FWINFO; + break; + case PHL_BTC_NTFY_PACKET_EVT: + event = BTC_EV_PACKET_EVT; + break; + case PHL_BTC_NTFY_MAX: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "rtw_phl_btc_notify(): Unsupported case:%d, please check it\n", + notify); + return wait; + case PHL_BTC_NTFY_TIMER: + event = BTC_EV_TIMER; + break; + default: + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "rtw_phl_btc_notify(): Unrecognize case:%d, please check it\n", + notify); + return wait; + } + phl_fsm_gen_msg(phl, pbtc->fsm_obj, ntfy, sz, event); + return wait; +} + +void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate) +{ + struct rtw_phl_btc_ntfy ntfy = {0}; + struct rtw_phl_btc_role_info_param *prinfo = &ntfy.u.rinfo; + + prinfo->role_id = role_id; + prinfo->rstate = rstate; + + ntfy.notify = PHL_BTC_NTFY_ROLE_INFO; + ntfy.ops = NULL; + ntfy.priv = NULL; + ntfy.ntfy_cb = NULL; + + rtw_phl_btc_notify(phl, ntfy.notify, &ntfy); +} + +#ifndef CONFIG_PHL_CMD_BTC +void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type) +{ + struct rtw_phl_btc_ntfy ntfy = {0}; + struct rtw_phl_btc_pkt_param *pkt = &ntfy.u.pkt; + + pkt->role_id = role_id; + pkt->pkt_evt_type = pkt_evt_type; + + ntfy.notify = PHL_BTC_NTFY_PACKET_EVT; + ntfy.ops = NULL; + ntfy.priv = NULL; + ntfy.ntfy_cb = NULL; + + rtw_phl_btc_notify(phl, ntfy.notify, &ntfy); +} + +u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type) +{ + u8 pkt_evt_type = BTC_PKT_EVT_MAX; + + switch (packet_type) { + case PACKET_NORMAL: + pkt_evt_type = BTC_PKT_EVT_NORMAL; + break; + case PACKET_DHCP: + pkt_evt_type = BTC_PKT_EVT_DHCP; + break; + case PACKET_ARP: + pkt_evt_type = BTC_PKT_EVT_ARP; + break; + case PACKET_EAPOL: + pkt_evt_type = BTC_PKT_EVT_EAPOL; + break; + case PACKET_EAPOL_START: + pkt_evt_type = BTC_PKT_EVT_EAPOL_START; + break; + default: + PHL_ERR("%s packet type(%d) not support\n", + __func__, packet_type); + break; + } + + return pkt_evt_type; +} +#endif + +static void _btc_fsm_tmr(void *phl, void *timer) +{ + struct rtw_phl_btc_ntfy ntfy = {0}; + struct rtw_phl_btc_tmr_param *tmr = &ntfy.u.tmr; + + tmr->timer = timer; + + ntfy.notify = PHL_BTC_NTFY_TIMER; + ntfy.ops = NULL; + ntfy.priv = NULL; + ntfy.ntfy_cb = NULL; + + rtw_phl_btc_notify(phl, ntfy.notify, &ntfy); +} + +void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg) +{ + u8 mdl_id = MSG_MDL_ID_FIELD(msg->msg_id); + u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + switch (mdl_id) { + case PHL_MDL_BTC: + if (evt_id == BTC_HMSG_TMR_EN) { + _btc_fsm_tmr(phl, msg->inbuf); + } else if (evt_id == BTC_HMSG_FW_EV) { + rtw_phl_btc_notify(phl, PHL_BTC_NTFY_FWINFO, NULL); + } + break; + default: + break; + } +} +#endif /*CONFIG_FSM*/ + diff --git a/phl/phl_btc_fsm.h b/phl/phl_btc_fsm.h new file mode 100644 index 0000000..bfa9313 --- /dev/null +++ b/phl/phl_btc_fsm.h @@ -0,0 +1,40 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_BTC_FSM_H__ +#define __PHL_BTC_FSM_H__ + +/* Header file for application to invoke btcoex service */ + +#define RTW_BTC_FWBUF_NUM 4 +#define RTW_BTC_NAME_MAX 20 + +struct fsm_root; +struct fsm_main; +struct btc_obj; + +/* function form btcoex service management */ +struct fsm_main *phl_btc_new_fsm(struct fsm_root *fsm_m, + struct phl_info_t *phl_info); +void phl_btc_destory_fsm(struct fsm_main *fsm); +struct btc_obj *phl_btc_new_obj(struct fsm_main *fsm, + struct phl_info_t *phl_info); +void phl_btc_destory_obj(struct btc_obj *pbtc); + +/* function form btcoex service */ +enum rtw_phl_status phl_btc_start(struct btc_obj *pbtc); +enum rtw_phl_status phl_btc_cancel(struct btc_obj *pbtc); + +#endif /* __PHL_BTC_FSM_H__ */ + diff --git a/phl/phl_chan.c b/phl/phl_chan.c new file mode 100644 index 0000000..2528f4b --- /dev/null +++ b/phl/phl_chan.c @@ -0,0 +1,1532 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CHAN_C_ +#include "phl_headers.h" + +const char *const _band_str[] = { + "BAND_ON_24G", + "BAND_ON_5G", + "BAND_ON_6G", + "BAND_UNKNOWN" +}; +#define _get_band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)]) + +const char *const _bw_str[] = { + "BW_20M", + "BW_40M", + "BW_80M", + "BW_160M", + "BW_80_80M", + "BW_5M", + "BW_10M", + "BW_UNKNOWN" +}; +#define _get_bw_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _bw_str[CHANNEL_WIDTH_MAX] : _bw_str[((bw))]) + +#ifdef DBG_PHL_CHAN +void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller, + struct rtw_chan_def *chandef) +{ + if (show_caller) + PHL_INFO("###### FUN - %s LINE - %d #######\n", caller, line); + + PHL_INFO("\t[CH] band:%s\n", _get_band_str(chandef->band)); + PHL_INFO("\t[CH] chan:%d\n", chandef->chan); + PHL_INFO("\t[CH] center_ch:%d\n", chandef->center_ch); + PHL_INFO("\t[CH] bw:%s\n", _get_bw_str(chandef->bw)); + PHL_INFO("\t[CH] offset:%d\n", chandef->offset); + + PHL_INFO("\t[CH] center_freq1:%d\n", chandef->center_freq1); + PHL_INFO("\t[CH] center_freq2:%d\n", chandef->center_freq2); + PHL_INFO("\t[CH] hw_value:%d\n", chandef->hw_value); + + if (show_caller) + PHL_INFO("#################################\n"); +} +#endif + +#ifdef CONFIG_PHL_DFS +static enum rtw_phl_status +phl_radar_detect_hdl(struct phl_info_t *phl_info, + u8 channel, enum channel_width bwmode, enum chan_offset offset) +{ + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + struct rtw_dfs_t *dfs_info = &phl_com->dfs_info; + enum rtw_phl_status rst = RTW_PHL_STATUS_FAILURE; + bool overlap_radar_range; + + overlap_radar_range = rtw_hal_in_radar_domain(phl_info->hal, + channel, bwmode); + if (overlap_radar_range) + PHL_INFO("chan in DFS domain ch:%d,bw:%d\n", channel, bwmode); + + + if (overlap_radar_range && !dfs_info->dfs_enabled) { + /*radar_detect_enable*/ + if (rtw_hal_radar_detect_cfg(phl_info->hal, true) == + RTW_HAL_STATUS_SUCCESS) { + dfs_info->dfs_enabled = true; + PHL_INFO("[DFS] chan(%d) in radar range, enable dfs\n", + channel); + rst = RTW_PHL_STATUS_SUCCESS; + } + else { + PHL_ERR("[DFS] chan(%d) in radar range, enable dfs failed\n", + channel); + } + + } else if (!overlap_radar_range && dfs_info->dfs_enabled) { + /*radar_detect_disable*/ + if (rtw_hal_radar_detect_cfg(phl_info->hal, false) == + RTW_HAL_STATUS_SUCCESS) { + dfs_info->dfs_enabled = false; + PHL_INFO("[DFS] chan(%d) not in radar range, disable dfs\n", + channel); + rst = RTW_PHL_STATUS_SUCCESS; + } + else { + PHL_ERR("[DFS] chan(%d) not in radar range, disable dfs failed\n", + channel); + } + } + return rst; +} +#endif /*CONFIG_PHL_DFS*/ + +enum rtw_phl_status +phl_set_ch_bw(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef, bool do_rfk) +{ + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + chdef->band = rtw_phl_get_band_type(chdef->chan); +#ifdef CONFIG_PHL_DFS + phl_radar_detect_hdl(phl_info, chdef->chan, chdef->bw, chdef->offset); +#endif + hstatus = rtw_hal_set_ch_bw(phl_info->hal, wifi_role->hw_band, + chdef, do_rfk); + if (RTW_HAL_STATUS_SUCCESS != hstatus) + PHL_ERR("%s rtw_hal_set_ch_bw: statuts = %u\n", __func__, hstatus); + + return RTW_PHL_STATUS_SUCCESS; +} + +#ifdef CONFIG_CMD_DISP +struct setch_param { + struct rtw_wifi_role_t *wrole; + struct rtw_chan_def chdef; + bool do_rfk; +}; + +static void +_phl_chg_op_chdef_done(void *drv_priv, u8 *cmd, u32 cmd_len, + enum rtw_phl_status status) +{ + if (cmd) { + struct chg_opch_param *param = (struct chg_opch_param *)cmd; + + if (param->chg_opch_done) { + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + + if (RTW_PHL_STATUS_CMD_SUCCESS == status && + RTW_PHL_STATUS_CMD_SUCCESS == param->cmd_start_sts) + psts = RTW_PHL_STATUS_SUCCESS; + param->chg_opch_done(drv_priv, param->wrole->id, + psts); + } + _os_kmem_free(drv_priv, cmd, cmd_len); + cmd = NULL; + PHL_INFO("%s.....\n", __func__); + } +} + +static void _phl_chg_op_chdef_start_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + if (cmd) { + struct chg_opch_param *param = (struct chg_opch_param *)cmd; + + param->cmd_start_sts = status; + PHL_INFO("%s.....\n", __func__); + } +} + +enum rtw_phl_status +phl_cmd_chg_op_chdef_start_hdl(struct phl_info_t *phl, u8 *param) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + struct chg_opch_param *ch_param = (struct chg_opch_param *)param; + void *drv = phl_to_drvpriv(phl); + enum phl_upd_mode mode = PHL_UPD_STA_INFO_CHANGE; + struct phl_queue *sta_queue = NULL; + struct rtw_phl_stainfo_t *sta = NULL; + struct rtw_chan_def chctx_result = {0}; + + sta = rtw_phl_get_stainfo_self(phl, ch_param->wrole); + if (NULL == sta) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: cannot get stainfo_self\n", + __FUNCTION__); + goto exit; + } + /* Update MR chctx */ + if (RTW_PHL_STATUS_SUCCESS != phl_mr_chandef_chg(phl, ch_param->wrole, + &ch_param->new_chdef, &chctx_result)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: MR chang chdef failed!\n", + __FUNCTION__); + goto exit; + } + /* Up Role chdef */ + _os_mem_cpy(drv, &ch_param->wrole->chandef, &ch_param->new_chdef, + sizeof(struct rtw_chan_def)); + /* Update self Sta chdef */ + _os_mem_cpy(drv, &sta->chandef, &ch_param->new_chdef, + sizeof(struct rtw_chan_def)); + /* Notify rf for the suspended channel */ + rtw_hal_disconnect_notify(phl->hal, &ch_param->ori_chdef); + /* Switch channel */ + if (RTW_PHL_STATUS_SUCCESS != phl_set_ch_bw(ch_param->wrole, + &chctx_result, true)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Switch ch failed!\n", + __FUNCTION__); + goto exit; + } + if (ch_param->wrole->mstate == MLME_LINKED) { + /*Up STA setting(RA....) */ + sta_queue = &ch_param->wrole->assoc_sta_queue; + _os_spinlock(drv, &sta_queue->lock, _bh, NULL); + phl_list_for_loop(sta, struct rtw_phl_stainfo_t, + &sta_queue->queue, list) { + if (sta) + phl_change_stainfo(phl, sta, mode); + } + _os_spinunlock(drv, &sta_queue->lock, _bh, NULL); + } + pstatus = RTW_PHL_STATUS_SUCCESS; +exit: + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: pstatus(%d)\n", + __FUNCTION__, pstatus); + return pstatus; +} + +enum rtw_phl_status +rtw_phl_cmd_chg_op_chdef(struct rtw_wifi_role_t *wrole, + struct rtw_chan_def *new_chdef, bool cmd_wait, u32 cmd_timeout, + void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status)) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl = wrole->phl_com->phl_priv; + void *drv = phl_to_drvpriv(phl); + u32 param_len = sizeof(struct chg_opch_param); + struct chg_opch_param *param = _os_kmem_alloc(drv, param_len); + + if (param == NULL) { + PHL_ERR("%s: alloc param failed!\n", __func__); + goto _exit; + } + param->wrole = wrole; + _os_mem_cpy(drv, ¶m->new_chdef, new_chdef, + sizeof(struct rtw_chan_def)); + _os_mem_cpy(drv, ¶m->ori_chdef, &wrole->chandef, + sizeof(struct rtw_chan_def)); + param->chg_opch_done = chg_opch_done; + psts = phl_cmd_enqueue(phl, + wrole->hw_band, + MSG_EVT_CHG_OP_CH_DEF_START, + (u8 *)param, + param_len, + _phl_chg_op_chdef_start_done, + PHL_CMD_NO_WAIT, + 0); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_INFO("%s: Fail to issue change op chdef start!!\n", + __func__); + if (!is_cmd_failure(psts)) { + /* Send cmd fail */ + _os_kmem_free(drv, param, param_len); + psts = RTW_PHL_STATUS_FAILURE; + } + goto _exit; + } + psts = phl_cmd_enqueue(phl, + wrole->hw_band, + MSG_EVT_CHG_OP_CH_DEF_END, + (u8 *)param, + param_len, + _phl_chg_op_chdef_done, + cmd_wait ? PHL_CMD_WAIT : PHL_CMD_NO_WAIT, + cmd_timeout); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_INFO("%s: Fail to issue change op chdef start!!\n", + __func__); + if (!is_cmd_failure(psts)) { + /* Send cmd fail */ + _os_kmem_free(drv, param, param_len); + psts = RTW_PHL_STATUS_FAILURE; + } + goto _exit; + } +_exit: + PHL_INFO("%s: Issue cmd, status(%d)\n", __func__, psts); + return psts; +} + +enum rtw_phl_status +phl_cmd_set_ch_bw_hdl(struct phl_info_t *phl_info, u8 *param) +{ + struct setch_param *ch_param = (struct setch_param *)param; + + return phl_set_ch_bw(ch_param->wrole, + &(ch_param->chdef), + ch_param->do_rfk); +} + +static void _phl_set_ch_bw_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + if (cmd) { + _os_kmem_free(drv_priv, cmd, cmd_len); + cmd = NULL; + PHL_INFO("%s.....\n", __func__); + } +} + +enum rtw_phl_status +rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef, + bool do_rfk, + enum phl_cmd_type cmd_type, + u32 cmd_timeout) +{ + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + void *drv = wifi_role->phl_com->drv_priv; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct setch_param *param = NULL; + u32 param_len; + + if (cmd_type == PHL_CMD_DIRECTLY) { + psts = phl_set_ch_bw(wifi_role, chdef, do_rfk); + goto _exit; + } + + param_len = sizeof(struct setch_param); + param = _os_kmem_alloc(drv, param_len); + if (param == NULL) { + PHL_ERR("%s: alloc param failed!\n", __func__); + goto _exit; + } + param->wrole = wifi_role; + _os_mem_cpy(drv, ¶m->chdef, chdef, sizeof(struct rtw_chan_def)); + param->do_rfk = do_rfk; + + psts = phl_cmd_enqueue(phl_info, + wifi_role->hw_band, + MSG_EVT_SWCH_START, + (u8 *)param, + param_len, + _phl_set_ch_bw_done, + cmd_type, + cmd_timeout); + + if (is_cmd_failure(psts)) { + /* Send cmd success, but wait cmd fail*/ + psts = RTW_PHL_STATUS_FAILURE; + } else if (psts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + _os_kmem_free(drv, param, param_len); + psts = RTW_PHL_STATUS_FAILURE; + } +_exit: + return psts; +} +#endif /*CONFIG_CMD_DISP*/ + +u8 rtw_phl_get_cur_ch(struct rtw_wifi_role_t *wifi_role) +{ + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + + return rtw_hal_get_cur_ch(phl_info->hal, wifi_role->hw_band); +} + +enum rtw_phl_status +rtw_phl_get_cur_hal_chdef(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *cur_chandef) +{ + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + + rtw_hal_get_cur_chdef(phl_info->hal, wifi_role->hw_band, cur_chandef); + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_dfs_hw_tx_pause(struct rtw_wifi_role_t *wifi_role, bool tx_pause) +{ + + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE; + + hstatus = rtw_hal_dfs_pause_tx(phl_info->hal, wifi_role->hw_band, tx_pause); + + if (RTW_HAL_STATUS_SUCCESS == hstatus) { + return RTW_PHL_STATUS_SUCCESS; + } else { + PHL_ERR("%s Failure :%u\n",__func__, hstatus); + return RTW_PHL_STATUS_FAILURE; + } +} + +#ifdef CONFIG_CMD_DISP +struct dfs_txpause_param { + struct rtw_wifi_role_t *wrole; + bool pause; +}; + +enum rtw_phl_status +phl_cmd_dfs_tx_pause_hdl(struct phl_info_t *phl_info, u8 *param) +{ + struct dfs_txpause_param *dfs = (struct dfs_txpause_param *)param; + + PHL_INFO("%s(), dfs param, wrole = %p, pause = %d\n", + __func__, dfs->wrole, dfs->pause); + + return _dfs_hw_tx_pause(dfs->wrole, dfs->pause); +} + +static void _phl_dfs_tx_pause_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + if (cmd) { + _os_kmem_free(drv_priv, cmd, cmd_len); + cmd = NULL; + PHL_INFO("%s.....\n", __func__); + } +} +#endif /*CONFIG_CMD_DISP*/ + +enum rtw_phl_status +rtw_phl_cmd_dfs_tx_pause(struct rtw_wifi_role_t *wifi_role, bool pause, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ +#ifdef CONFIG_CMD_DISP + struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv; + void *drv = wifi_role->phl_com->drv_priv; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct dfs_txpause_param *param = NULL; + u32 param_len; + + param_len = sizeof(struct dfs_txpause_param); + param = _os_kmem_alloc(drv, param_len); + if (param == NULL) { + PHL_ERR("%s: alloc param failed!\n", __func__); + goto _exit; + } + param->wrole = wifi_role; + param->pause = pause; + + psts = phl_cmd_enqueue(phl_info, + wifi_role->hw_band, + MSG_EVT_DFS_PAUSE_TX, + (u8 *)param, param_len, + _phl_dfs_tx_pause_done, + cmd_type, cmd_timeout); + + if (is_cmd_failure(psts)) { + /* Send cmd success, but wait cmd fail*/ + psts = RTW_PHL_STATUS_FAILURE; + } else if (psts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + _os_kmem_free(drv, param, param_len); + psts = RTW_PHL_STATUS_FAILURE; + } + +_exit: + return psts; +#else + PHL_ERR("%s(), CONFIG_CMD_DISP need to be enabled for MSG_EVT_DFS_PAUSE_TX \n",__func__); + + return RTW_PHL_STATUS_FAILURE; +#endif +} + + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_phl_status +rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE; + + switch (id){ + case DBCC_PRE_CFG : + { + bool dbcc_en = *(bool *)param; + + PHL_INFO("[DBCC] PRE_CFG :%s\n", (dbcc_en) ? "EN" : "DIS"); + hsts = rtw_hal_dbcc_pre_cfg(phl_info->hal, phl_info->phl_com, dbcc_en); + } + break; + + case DBCC_CFG : + { + bool dbcc_en = *(bool *)param; + + PHL_INFO("[DBCC] CFG :%s\n", (dbcc_en) ? "EN" : "DIS"); + hsts = rtw_hal_dbcc_cfg(phl_info->hal, phl_info->phl_com, dbcc_en); + } + break; + case DBCC_CLEAN_TXQ : + hsts = rtw_hal_clean_tx_queue(phl_info->hal); + break; + default : + PHL_ERR("%s unknown DBCC Test ID:%d\n",__func__, id); + break; + } + + return RTW_PHL_STATUS_SUCCESS; +} +#endif + +#define MAX_CHANCTX_QUEUE_NUM 2 + + +static enum rtw_phl_status +_phl_chanctx_add(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + list_add_tail(&chanctx->list, &chan_ctx_queue->queue); + chan_ctx_queue->cnt++; + if (chan_ctx_queue->cnt > MAX_CHANCTX_QUEUE_NUM) { + PHL_ERR("%s chan_ctx_queue cnt(%d) > 2\n", __func__, chan_ctx_queue->cnt); + _os_warn_on(1); + } + + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_phl_chanctx_add_with_lock(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + _phl_chanctx_add(phl_info, chan_ctx_queue, chanctx); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_phl_chanctx_del(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + /*if (!list_empty(&chan_ctx_queue->queue)) {*/ + if (chan_ctx_queue->cnt) { + list_del(&chanctx->list); + chan_ctx_queue->cnt--; + if (chan_ctx_queue->cnt < 0) { + PHL_ERR("%s chan_ctx_queue cnt(%d) < 0\n", __func__, chan_ctx_queue->cnt); + _os_warn_on(1); + } + } + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_phl_chanctx_del_with_lock(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + _phl_chanctx_del(phl_info, chan_ctx_queue, chanctx); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + return RTW_PHL_STATUS_SUCCESS; +} + +static inline enum rtw_phl_status +_phl_chanctx_rmap_set(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + u8 ridx = wifi_role->id; + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + #ifdef DBG_CHCTX_RMAP + if (chanctx->role_map & BIT(ridx)) + PHL_ERR("wifi_role idx(%d) has in chanctx->role_map(0x%02x)\n", + ridx, chanctx->role_map); + #endif + chanctx->role_map |= BIT(ridx); + wifi_role->chanctx = chanctx; + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_phl_chanctx_rmap_set_with_lock(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + _phl_chanctx_rmap_set(phl_info, wifi_role, chan_ctx_queue, chanctx); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + return RTW_PHL_STATUS_SUCCESS; +} + +static inline enum rtw_phl_status +_phl_chanctx_rmap_clr(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + u8 ridx = wifi_role->id; + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + #ifdef DBG_CHCTX_RMAP + if (!(chanctx->role_map & BIT(ridx))) + PHL_ERR("ridx(%d) hasn't in chanctx->role_map(0x%02x)\n", ridx, chanctx->role_map); + #endif + wifi_role->chanctx = NULL; + chanctx->role_map &= ~BIT(ridx); + + return RTW_PHL_STATUS_SUCCESS; +} + +static enum rtw_phl_status +_phl_chanctx_rmap_clr_with_lock(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (!chanctx) + return RTW_PHL_STATUS_FAILURE; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + _phl_chanctx_rmap_clr(phl_info, wifi_role, chan_ctx_queue, chanctx); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + return RTW_PHL_STATUS_SUCCESS; +} + +u8 phl_chanctx_get_rnum(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + u8 i; + u8 role_num = 0; + + for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) + if (chanctx->role_map & BIT(i)) + role_num++; + return role_num; +} + +u8 phl_chanctx_get_rnum_with_lock(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx) +{ + void *drv = phl_to_drvpriv(phl_info); + u8 role_num = 0; + + if (!chanctx) + return role_num; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + return role_num; +} + +/** + * _phl_is_chbw_grouped - test if the two ch settings can be grouped together + * @ch_a: ch of set a + * @bw_a: bw of set a + * @offset_a: offset of set a + * @ch_b: ch of set b + * @bw_b: bw of set b + * @offset_b: offset of set b + */ +static bool _phl_is_chbw_grouped(u8 ch_a, enum channel_width bw_a, enum chan_offset offset_a + , u8 ch_b, enum channel_width bw_b, enum chan_offset offset_b) +{ + bool is_grouped = false; + + if (ch_a != ch_b) { + /* ch is different */ + goto exit; + } else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80) + && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80) + ) { + if (offset_a != offset_b) + goto exit; + } + + is_grouped = true; + +exit: + return is_grouped; +} + + +static inline bool +_phl_feature_check(struct rtw_phl_com_t *phl_com, u8 flg) +{ + return (phl_com->dev_cap.hw_sup_flags & flg) ? true : false; +} + +static u8 _phl_get_offset_by_chbw(u8 ch, enum channel_width bw, enum chan_offset *r_offset) +{ + u8 valid = 1; + enum chan_offset offset = CHAN_OFFSET_NO_EXT; + + if (bw == CHANNEL_WIDTH_20) + goto exit; + + if (bw >= CHANNEL_WIDTH_80 && ch <= 14) { + valid = 0; + goto exit; + } + + if (ch >= 1 && ch <= 4) + offset = CHAN_OFFSET_UPPER; + else if (ch >= 5 && ch <= 9) { + if (*r_offset == CHAN_OFFSET_UPPER || *r_offset == CHAN_OFFSET_LOWER) + offset = *r_offset; /* both lower and upper is valid, obey input value */ + else + offset = CHAN_OFFSET_LOWER; /* default use upper */ + } else if (ch >= 10 && ch <= 13) + offset = CHAN_OFFSET_LOWER; + else if (ch == 14) { + valid = 0; /* ch14 doesn't support 40MHz bandwidth */ + goto exit; + } else if (ch >= 36 && ch <= 177) { + switch (ch) { + case 36: + case 44: + case 52: + case 60: + case 100: + case 108: + case 116: + case 124: + case 132: + case 140: + case 149: + case 157: + case 165: + case 173: + offset = CHAN_OFFSET_UPPER; + break; + case 40: + case 48: + case 56: + case 64: + case 104: + case 112: + case 120: + case 128: + case 136: + case 144: + case 153: + case 161: + case 169: + case 177: + offset = CHAN_OFFSET_LOWER; + break; + default: + valid = 0; + break; + } + } else + valid = 0; + +exit: + if (valid && r_offset) + *r_offset = offset; + return valid; +} + +/** + * _phl_adjust_chandef - obey g_ch, adjust g_bw, g_offset, bw, offset + * @req_ch: pointer of the request ch, may be modified further + * @req_bw: pointer of the request bw, may be modified further + * @req_offset: pointer of the request offset, may be modified further + * @g_ch: pointer of the ongoing group ch + * @g_bw: pointer of the ongoing group bw, may be modified further + * @g_offset: pointer of the ongoing group offset, may be modified further + */ +static void _phl_adjust_chandef(u8 *req_ch, enum channel_width *req_bw, enum chan_offset *req_offset, + u8 *g_ch, enum channel_width *g_bw, enum chan_offset *g_offset) +{ + + *req_ch = *g_ch; + + if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) { + /*2.4G ch, downgrade to 40Mhz */ + *req_bw = CHANNEL_WIDTH_40; + } + + switch (*req_bw) { + case CHANNEL_WIDTH_80: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + _phl_get_offset_by_chbw(*req_ch, *req_bw, req_offset); + + if (*req_offset == CHAN_OFFSET_NO_EXT) { + PHL_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__); + _os_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_40: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + _phl_get_offset_by_chbw(*req_ch, *req_bw, req_offset); + + if (*req_offset == CHAN_OFFSET_NO_EXT) { + PHL_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__); + _os_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_20: + *req_offset = CHAN_OFFSET_NO_EXT; + break; + default: + PHL_ERR("%s req unsupported BW:%u\n", __func__, *req_bw); + _os_warn_on(1); + } + + if (*req_bw > *g_bw) { + *g_bw = *req_bw; + *g_offset = *req_offset; + } +} + +static enum rtw_phl_status +_phl_chanctx_create(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + enum band_type band, u8 chan, + enum channel_width bw, enum chan_offset offset) +{ + enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE; + void *drv = phl_to_drvpriv(phl_info); + struct rtw_chan_ctx *chanctx = NULL; + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_info->phl_com); + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]); + + chanctx = _os_kmem_alloc(drv, sizeof(struct rtw_chan_ctx)); + if (chanctx == NULL) { + PHL_ERR("alloc chanctx failed\n"); + goto _exit; + } + + chanctx->chan_def.band = band; + chanctx->chan_def.chan = chan; + chanctx->chan_def.bw = bw; + chanctx->chan_def.offset = offset; + chanctx->chan_def.center_ch = rtw_phl_get_center_ch(chan, bw, offset); + phl_sts = _phl_chanctx_add_with_lock(phl_info, &band_ctrl->chan_ctx_queue, chanctx); + + if (phl_sts == RTW_PHL_STATUS_SUCCESS) + _phl_chanctx_rmap_set_with_lock(phl_info, wifi_role, + &band_ctrl->chan_ctx_queue, chanctx); +_exit: + return phl_sts; +} +bool phl_chanctx_add(struct phl_info_t *phl_info, struct rtw_wifi_role_t *wifi_role, + u8 *chan, enum channel_width *bw, enum chan_offset *offset) +{ + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE; + void *drv = phl_to_drvpriv(phl_info); + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com); + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]); + struct rtw_chan_ctx *chanctx = NULL; + struct rtw_chan_def *chandef = NULL; + _os_list *chan_ctx_list = &band_ctrl->chan_ctx_queue.queue; + bool is_ch_grouped = false; + enum band_type band = (*chan > 14) ? BAND_ON_5G : BAND_ON_24G; + int chanctx_num = 0; + + if (wifi_role == NULL) { + PHL_ERR("%s wrole == NULL\n", __func__); + goto _exit; + } + + PHL_INFO("%s new chan_def - hw_band_idx:%d, chan:%d, bw:%d, offset:%d\n", + __func__, wifi_role->hw_band, *chan, *bw, *offset); + + chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + if (chanctx_num == 0) { + phl_sts = _phl_chanctx_create(phl_info, wifi_role, + band, *chan, *bw, *offset); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s failed\n", __func__); + _os_warn_on(1); + } + else { + is_ch_grouped = true; + } + } + else { + _os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + phl_list_for_loop(chanctx, struct rtw_chan_ctx, chan_ctx_list, list) { + chandef = &chanctx->chan_def; + is_ch_grouped = _phl_is_chbw_grouped( + chandef->chan, chandef->bw, chandef->offset, + *chan, *bw, *offset); + if (is_ch_grouped) { + _phl_adjust_chandef(chan, bw, offset, + &chandef->chan, &chandef->bw, &chandef->offset); + + *chan = chandef->chan; + *bw = chandef->bw; + *offset = chandef->offset; + PHL_INFO("%s grouped chan_def - hw_band_idx:%d, chan:%d, bw:%d, offset:%d\n", + __func__, wifi_role->hw_band, *chan, *bw, *offset); + _phl_chanctx_rmap_set(phl_info, wifi_role, + &band_ctrl->chan_ctx_queue, chanctx); + break; + } + } + _os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + + if (is_ch_grouped == false) { /*MCC or DBCC*/ + PHL_INFO("%s chan:%d, bw:%d, offset:%d could not grouped\n", + __func__, *chan, *bw, *offset); + + #ifdef CONFIG_MCC_SUPPORT + if (phl_com->dev_cap.mcc_sup == false) { + PHL_ERR("%s don't support MCC\n", __func__); + goto _exit; + } + + if (chanctx_num >= 2) { + PHL_ERR("chan_ctx cnt(%d) >= 2\n", chanctx_num); + /*DBCC ?*/ + goto _exit; + } + if (band == chandef->band) { /*MCC*/ + phl_sts = _phl_chanctx_create(phl_info, wifi_role, + band, *chan, *bw, *offset); + if (phl_sts == RTW_PHL_STATUS_SUCCESS) + is_ch_grouped = true; + } else { + /*DBCC*/ + #ifdef CONFIG_DBCC_SUPPORT + if (phl_com->dev_cap.dbcc_sup == true) { + PHL_INFO("%s support DBC\n", __func__); + goto _exit; + } + #endif + /*MCC*/ + phl_sts = _phl_chanctx_create(phl_info, wifi_role, + band, *chan, *bw, *offset); + if (phl_sts == RTW_PHL_STATUS_SUCCESS) + is_ch_grouped = true; + + } + #endif + } + } + +_exit: + return is_ch_grouped; +} + +enum rtw_phl_status +phl_chanctx_free(struct phl_info_t *phl_info, struct hw_band_ctl_t *band_ctl) +{ + int chanctx_num = 0; + struct rtw_chan_ctx *chanctx = NULL; + struct phl_queue *chan_ctx_queue = &band_ctl->chan_ctx_queue; + void *drv = phl_to_drvpriv(phl_info); + + chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctl); + if (chanctx_num == 0) + return RTW_PHL_STATUS_SUCCESS; + + PHL_INFO("%s band_idx:%d chctx_num:%d\n", __func__, band_ctl->id, chanctx_num); + do { + _os_spinlock(drv, &band_ctl->chan_ctx_queue.lock, _ps, NULL); + if (list_empty(&chan_ctx_queue->queue)) { + chanctx = NULL; + } else { + chanctx = list_first_entry(&chan_ctx_queue->queue, + struct rtw_chan_ctx, list); + list_del(&chanctx->list); + chan_ctx_queue->cnt--; + } + _os_spinunlock(drv, &band_ctl->chan_ctx_queue.lock, _ps, NULL); + + if (chanctx) { + _os_kmem_free(drv, chanctx, sizeof(struct rtw_chan_ctx)); + } + } while (chanctx != NULL); + return RTW_PHL_STATUS_SUCCESS; +} + +/* used for get all role under band_idx */ +u8 phl_get_chanctx_rolemap(struct phl_info_t *phl_info, u8 band_idx) +{ + void *drv = phl_to_drvpriv(phl_info); + struct hw_band_ctl_t *band_ctrl = get_band_ctrl(phl_info, band_idx); + _os_list *chan_ctx_list = &band_ctrl->chan_ctx_queue.queue; + struct rtw_chan_ctx *chanctx = NULL; + u8 role_map =0; + + _os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + phl_list_for_loop(chanctx, struct rtw_chan_ctx, chan_ctx_list, list) { + role_map |= chanctx->role_map; + } + _os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + + return role_map; +} + + +bool rtw_phl_chanctx_chk(void *phl, struct rtw_wifi_role_t *wifi_role, + u8 chan, enum channel_width bw, enum chan_offset offset) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + void *drv = phl_to_drvpriv(phl_info); + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com); + u8 band_idx = wifi_role->hw_band; + bool is_ch_group = false; + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[band_idx]); + int chanctx_num = 0; + struct rtw_chan_ctx *chanctx = NULL; + struct rtw_chan_def *chandef = NULL; + + if (chan == 0) { + PHL_ERR("%s req chan = 0 \n", __func__); + goto _exit; + } + + /*status check*/ + if (mr_ctl->is_sb) { + if (band_idx == 1) { + PHL_ERR("wrole:%d in band_idx:%d\n", wifi_role->id, band_idx); + _os_warn_on(1); + goto _exit; + } + } + + chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + + if (chanctx_num > 0) { + _os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + phl_list_for_loop(chanctx, struct rtw_chan_ctx, &band_ctrl->chan_ctx_queue.queue, list) { + chandef = &chanctx->chan_def; + is_ch_group = _phl_is_chbw_grouped( + chandef->chan, chandef->bw, chandef->offset, + chan, bw, offset); + if (is_ch_group) + break; + } + /* consider MCC case (support max 2 diff ch for MCC currently) */ + #ifdef CONFIG_MCC_SUPPORT + if (phl_com->dev_cap.mcc_sup == true && is_ch_group == false && chanctx_num < 2) { + is_ch_group = true; + } + #endif + _os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + } else { + is_ch_group = true; + } +_exit: + PHL_DUMP_MR_EX(phl_info); + return is_ch_group; +} + + +/* + * Add new operating chdef to MR. + * @new_chan: Input: new chdef; Output: the final operating ch ctx. + * ex: In the scc case, it will be the group chdef. + */ +bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role, + u8 *chan, enum channel_width *bw, enum chan_offset *offset) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + void *drv = phl_to_drvpriv(phl_info); + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com); + u8 band_idx = wifi_role->hw_band; + bool is_ch_grouped = false; + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[band_idx]); + int chanctx_num = 0; + u8 chctx_role_num = 0; + + if(!chan || !bw || !offset) + goto _exit; + + if (*chan == 0) { + PHL_ERR("%s req chan = 0 \n", __func__); + goto _exit; + } + + /*status check*/ + if (mr_ctl->is_sb) { + if (band_idx == 1) { + PHL_ERR("wrole:%d in band_idx:%d\n", wifi_role->id, band_idx); + goto _exit; + } + } + + + is_ch_grouped = phl_chanctx_add(phl_info, wifi_role, chan, bw, offset); + if (is_ch_grouped) { + chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + if (chanctx_num == 2) { + band_ctrl->op_mode = MR_OP_MCC; + } else if (chanctx_num == 1) { + struct rtw_chan_ctx *chanctx = NULL; + struct phl_queue *chan_ctx_queue = &band_ctrl->chan_ctx_queue; + + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + chanctx = list_first_entry(&chan_ctx_queue->queue, + struct rtw_chan_ctx, list); + chctx_role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx); + if (chctx_role_num >= 2) + band_ctrl->op_mode = MR_OP_SCC; + else + band_ctrl->op_mode = MR_OP_NON; + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + } + } + #ifdef CONFIG_DBCC_SUPPORT + else { + if ((phl_com->dev_cap.hw_sup_flags & HW_SUP_DBCC) && (phl_com->dev_cap.dbcc_sup)) { + /*TODO - info core layer */ + } + } + #endif +_exit: + PHL_DUMP_MR_EX(phl_info); + return is_ch_grouped; +} + +enum rtw_phl_status +rtw_phl_chanctx_del_no_self(void *phl, struct rtw_wifi_role_t *wifi_role) +{ + enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + void *drv = phl_to_drvpriv(phl_info); + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com); + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]); + struct rtw_chan_ctx *chanctx = NULL; + int chctx_num = 0; + + chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + if (chctx_num > 2) { + PHL_ERR("%s ERR - chanctx_num(%d) > 2\n", __func__, chctx_num); + _os_warn_on(1); + goto _exit; + } + + if (chctx_num == 0) { + phl_sts = RTW_PHL_STATUS_SUCCESS; + PHL_INFO("%s - chctx_num = 0\n", __func__); + goto _exit; + } + else if (chctx_num == 1) { /*SCC*/ + _os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + if (!list_empty(&band_ctrl->chan_ctx_queue.queue)) { + chanctx = list_first_entry(&band_ctrl->chan_ctx_queue.queue, + struct rtw_chan_ctx, list); + phl_sts = _phl_chanctx_del(phl_info, &band_ctrl->chan_ctx_queue, chanctx); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("_phl_chanctx_del failed\n"); + _os_warn_on(1); + } + } + _os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL); + _os_kmem_free(drv, chanctx, sizeof(struct rtw_chan_ctx)); + } + else if (chctx_num == 2) { /*MCC*/ + } + +_exit: + PHL_DUMP_MR_EX(phl_info); + return phl_sts; +} + +int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chan_def) +{ + enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + void *drv = phl_to_drvpriv(phl_info); + struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com); + struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]); + struct phl_queue *chan_ctx_queue = &band_ctrl->chan_ctx_queue; + struct rtw_chan_ctx *target_chanctx = NULL; + struct rtw_chan_ctx *chanctx = NULL; + int chctx_num = 0; + u8 chctx_role_num = 0; + u8 band_role_num = 0; + + if (wifi_role == NULL) { + PHL_ERR("%s wifi_role == NULL!!\n", __func__); + /*_os_warn_on(1);*/ + goto _exit; + } + + target_chanctx = wifi_role->chanctx; + if (target_chanctx == NULL) { + PHL_ERR("%s wifi_role->chanctx == NULL\n", __func__); + /*_os_warn_on(1);*/ + goto _exit; + } + /*init chan_def*/ + if (chan_def) + chan_def->chan = 0; + + chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + band_role_num = phl_mr_get_role_num(phl_info, band_ctrl); + + chctx_role_num = phl_chanctx_get_rnum_with_lock(phl_info, chan_ctx_queue, target_chanctx); + + if (chctx_num == 0 || chctx_role_num == 0) { + PHL_ERR("%s ERR - chanctx_num(%d), role_num(%d)\n", __func__, chctx_num, chctx_role_num); + _os_warn_on(1); + goto _exit; + } + if (chctx_num > 2) { + PHL_ERR("%s ERR - chanctx_num(%d) > 2\n", __func__, chctx_num); + _os_warn_on(1); + goto _exit; + } + + if (chctx_role_num == 1) { /*single role on this chctx*/ + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + phl_sts = _phl_chanctx_rmap_clr(phl_info, wifi_role, + chan_ctx_queue, target_chanctx); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("_phl_chanctx_rmap_clr failed\n"); + + phl_sts = _phl_chanctx_del(phl_info, chan_ctx_queue, target_chanctx); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("_phl_chanctx_del failed\n"); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + + _os_kmem_free(drv, target_chanctx, sizeof(struct rtw_chan_ctx)); + + } else { /*multi roles on this chctx*/ + phl_sts = _phl_chanctx_rmap_clr_with_lock(phl_info, wifi_role, + chan_ctx_queue, target_chanctx); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("_phl_chanctx_rmap_clr_with_lock failed\n"); + + phl_sts = phl_mr_chandef_upt(phl_info, band_ctrl, target_chanctx); + if (phl_sts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("phl_mr_chandef_upt failed\n"); + _os_warn_on(1); + goto _exit; + } + } + + chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl); + if (chctx_num == 0) { + band_ctrl->op_mode = MR_OP_NON; + } + else if (chctx_num == 1) { + _os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL); + chanctx = list_first_entry(&chan_ctx_queue->queue, + struct rtw_chan_ctx, list); + chctx_role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx); + if (chan_def) + _os_mem_cpy(drv, chan_def, &chanctx->chan_def, sizeof(struct rtw_chan_def)); + _os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL); + + #ifdef DBG_PHL_MR + if (chctx_role_num == 0) { + PHL_ERR("chctx_num=1, chctx_role_num=0\n"); + _os_warn_on(1); + } + #endif + band_ctrl->op_mode = (chctx_role_num == 1) ? MR_OP_NON : MR_OP_SCC; + } else if (chctx_num == 2) { + if (chan_def) + _os_mem_cpy(drv, chan_def, &target_chanctx->chan_def, sizeof(struct rtw_chan_def)); + band_ctrl->op_mode = MR_OP_MCC; + } + + phl_sts = RTW_PHL_STATUS_SUCCESS; + PHL_INFO("%s - Bidx(%d) - Total role_num:%d, chctx_num:%d, target-chctx rnum:%d, op_mode:%d\n", + __func__, band_ctrl->id, band_role_num, chctx_num, chctx_role_num, band_ctrl->op_mode); + +_exit: + PHL_DUMP_MR_EX(phl_info); + return chctx_num; +} + +#ifdef PHL_MR_PROC_CMD +bool rtw_phl_chanctx_test(void *phl, struct rtw_wifi_role_t *wifi_role, bool is_add, + u8 *chan, enum channel_width *bw, enum chan_offset *offset) +{ + bool rst = true; + int chanctx_num = 0; + struct rtw_chan_def chan_def = {0}; + + if (is_add) { + rst = rtw_phl_chanctx_add(phl, wifi_role, chan, bw, offset); + } + else { + chanctx_num = rtw_phl_chanctx_del(phl, wifi_role, &chan_def); + PHL_ERR("%s chctx_num = %d\n", __func__, chanctx_num); + PHL_DUMP_CHAN_DEF(&chan_def); + } + return rst; +} +#endif +enum band_type rtw_phl_get_band_type(u8 chan) +{ + /*TODO - BAND_ON_6G*/ + return (chan > 14) ? BAND_ON_5G : BAND_ON_24G; +} +u8 rtw_phl_get_center_ch(u8 ch, + enum channel_width bw, enum chan_offset offset) +{ + u8 cch = ch; + + if (bw == CHANNEL_WIDTH_160) { + if (ch % 4 == 0) { + if (ch >= 36 && ch <= 64) + cch = 50; + else if (ch >= 100 && ch <= 128) + cch = 114; + } else if (ch % 4 == 1) { + if (ch >= 149 && ch <= 177) + cch = 163; + } + + } else if (bw == CHANNEL_WIDTH_80) { + if (ch <= 14) + cch = 7; /* special case for 2.4G */ + else if (ch % 4 == 0) { + if (ch >= 36 && ch <= 48) + cch = 42; + else if (ch >= 52 && ch <= 64) + cch = 58; + else if (ch >= 100 && ch <= 112) + cch = 106; + else if (ch >= 116 && ch <= 128) + cch = 122; + else if (ch >= 132 && ch <= 144) + cch = 138; + } else if (ch % 4 == 1) { + if (ch >= 149 && ch <= 161) + cch = 155; + else if (ch >= 165 && ch <= 177) + cch = 171; + } + + } else if (bw == CHANNEL_WIDTH_40) { + if (offset == CHAN_OFFSET_UPPER) + cch = ch + 2; + else if (offset == CHAN_OFFSET_LOWER) + cch = ch - 2; + + } else if (bw == CHANNEL_WIDTH_20 + || bw == CHANNEL_WIDTH_10 + || bw == CHANNEL_WIDTH_5) { + ; /* the same as ch */ + } + else { + PHL_ERR("%s failed\n", __func__); + } + return cch; +} + +/* + * Refer to 80211 spec Annex E Table E-4 Global operating classes + * Handle 2.4G/5G Bandwidth 20/40/80/160 + */ +u8 +rtw_phl_get_operating_class( + struct rtw_chan_def chan_def +) +{ + u8 operating_class = 0; + + if(chan_def.bw == CHANNEL_WIDTH_20){ + if(chan_def.chan <= 13) + operating_class = 81; + else if(chan_def.chan ==14) + operating_class = 82; + else if(chan_def.chan >= 36 && chan_def.chan <= 48) + operating_class = 115; + else if(chan_def.chan >= 52 && chan_def.chan <= 64) + operating_class = 118; + else if(chan_def.chan >= 100 && chan_def.chan <= 144) + operating_class = 121; + else if(chan_def.chan >= 149 && chan_def.chan <= 169) + operating_class = 125; + else + PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan); + } + else if(chan_def.bw == CHANNEL_WIDTH_40){ + if(chan_def.offset == CHAN_OFFSET_UPPER){ + if(chan_def.chan >= 1 && chan_def.chan <= 9) + operating_class = 83; + else if(chan_def.chan == 36 || chan_def.chan == 44) + operating_class = 116; + else if(chan_def.chan == 52 || chan_def.chan == 60) + operating_class = 119; + else if(chan_def.chan == 100 || chan_def.chan == 108 || + chan_def.chan == 116 || chan_def.chan == 124 || + chan_def.chan == 132 || chan_def.chan == 140) + operating_class = 122; + else if(chan_def.chan == 149 || chan_def.chan == 157) + operating_class = 126; + else + PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan); + } + else if(chan_def.offset == CHAN_OFFSET_LOWER){ + if(chan_def.chan >= 5 && chan_def.chan <= 13) + operating_class = 84; + else if(chan_def.chan == 40 || chan_def.chan == 48) + operating_class = 117; + else if(chan_def.chan == 56 || chan_def.chan == 64) + operating_class = 120; + else if(chan_def.chan == 104 || chan_def.chan == 112 || + chan_def.chan == 120 || chan_def.chan == 128 || + chan_def.chan == 136 || chan_def.chan == 144) + operating_class = 123; + else if(chan_def.chan == 153 || chan_def.chan == 161) + operating_class = 127; + else + PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan); + } + else{ + PHL_WARN("%s: Invalid offset(%d)\n", + __FUNCTION__, chan_def.offset); + } + } + else if(chan_def.bw == CHANNEL_WIDTH_80){ + if(chan_def.center_ch == 42 || chan_def.center_ch == 58 || + chan_def.center_ch == 106 || chan_def.center_ch == 122 || + chan_def.center_ch == 138 || chan_def.center_ch == 155) + operating_class = 128; + else + PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.center_ch); + } + else if(chan_def.bw == CHANNEL_WIDTH_160){ + if(chan_def.center_ch == 50 || chan_def.center_ch == 114) + operating_class = 129; + else + PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.center_ch); + } + else{ + PHL_WARN("%s: Not handle bandwidth (%d)\n", __FUNCTION__, chan_def.bw); + } + + return operating_class; +} + +bool +rtw_phl_get_chandef_from_operating_class( + u8 channel, + u8 operating_class, + struct rtw_chan_def *chan_def +) +{ + bool ret = true; + if(operating_class == 81 || operating_class == 82 || + operating_class == 115 || operating_class == 118 || + operating_class == 118 || operating_class == 121 || + operating_class == 125){ + chan_def->chan = channel; + chan_def->bw = CHANNEL_WIDTH_20; + chan_def->offset = CHAN_OFFSET_NO_EXT; + chan_def->center_ch = rtw_phl_get_center_ch(channel, + CHANNEL_WIDTH_20, + CHAN_OFFSET_NO_EXT); + } + else if(operating_class == 83 || operating_class == 116 || + operating_class == 119 || operating_class == 122 || + operating_class == 126){ + chan_def->chan = channel; + chan_def->bw = CHANNEL_WIDTH_40; + chan_def->offset = CHAN_OFFSET_UPPER; + chan_def->center_ch = rtw_phl_get_center_ch(channel, + CHANNEL_WIDTH_40, + CHAN_OFFSET_UPPER); + } + else if(operating_class == 84 || operating_class == 117 || + operating_class == 120 || operating_class == 123 || + operating_class == 127){ + chan_def->chan = channel; + chan_def->bw = CHANNEL_WIDTH_40; + chan_def->offset = CHAN_OFFSET_LOWER; + chan_def->center_ch = rtw_phl_get_center_ch(channel, + CHANNEL_WIDTH_40, + CHAN_OFFSET_LOWER); + } + else if(operating_class == 128){ + chan_def->chan = channel; + chan_def->bw = CHANNEL_WIDTH_80; + chan_def->offset = CHAN_OFFSET_NO_DEF; + chan_def->center_ch = rtw_phl_get_center_ch(channel, + CHANNEL_WIDTH_80, + CHAN_OFFSET_NO_DEF); + } + else if(operating_class == 129){ + chan_def->chan = channel; + chan_def->bw = CHANNEL_WIDTH_160; + chan_def->offset = CHAN_OFFSET_NO_DEF; + chan_def->center_ch = rtw_phl_get_center_ch(channel, + CHANNEL_WIDTH_40, + CHAN_OFFSET_NO_DEF); + } + else{ + PHL_ERR("%s: Unknown operating class (%d)\n", __FUNCTION__, operating_class); + ret = false; + } + + return ret; +} \ No newline at end of file diff --git a/phl/phl_chan.h b/phl/phl_chan.h new file mode 100644 index 0000000..498184e --- /dev/null +++ b/phl/phl_chan.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CHANA_H_ +#define _PHL_CHANA_H_ + +u8 phl_chanctx_get_rnum(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx); + +u8 phl_chanctx_get_rnum_with_lock(struct phl_info_t *phl_info, + struct phl_queue *chan_ctx_queue, + struct rtw_chan_ctx *chanctx); + +u8 phl_get_chanctx_rolemap(struct phl_info_t *phl_info, u8 band_idx); + +enum rtw_phl_status +phl_chanctx_free(struct phl_info_t *phl_info, struct hw_band_ctl_t *band_ctl); + +enum rtw_phl_status +phl_set_ch_bw(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef, bool do_rfk); + + +bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role, + u8 *chan, enum channel_width *bw, enum chan_offset *offset); + +int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chan_def); + +#ifdef CONFIG_CMD_DISP +enum rtw_phl_status +phl_cmd_chg_op_chdef_start_hdl(struct phl_info_t *phl, u8 *param); + +enum rtw_phl_status +phl_cmd_set_ch_bw_hdl(struct phl_info_t *phl_info, u8 *param); +enum rtw_phl_status +rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role, + struct rtw_chan_def *chdef, + bool do_rfk, + enum phl_cmd_type cmd_type, + u32 cmd_timeout); +enum rtw_phl_status +phl_cmd_dfs_tx_pause_hdl(struct phl_info_t *phl_info, u8 *param); +#endif + +#ifdef DBG_PHL_CHAN +void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller, + struct rtw_chan_def *chandef); +#define PHL_DUMP_CHAN_DEF(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, false, _chandef); +#define PHL_DUMP_CHAN_DEF_EX(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, true, _chandef); +#else +#define PHL_DUMP_CHAN_DEF(_chandef) +#define PHL_DUMP_CHAN_DEF_EX(_chandef) +#endif + +#ifdef CONFIG_DBCC_SUPPORT +enum rtw_phl_status +rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param); +#endif + +enum band_type rtw_phl_get_band_type(u8 chan); +u8 rtw_phl_get_center_ch(u8 ch, + enum channel_width bw, enum chan_offset offset); +u8 +rtw_phl_get_operating_class( + struct rtw_chan_def chan_def +); + +bool +rtw_phl_get_chandef_from_operating_class( + u8 channel, + u8 operating_class, + struct rtw_chan_def *chan_def +); +#endif /*_PHL_CHANA_H_*/ diff --git a/phl/phl_chan_info.c b/phl/phl_chan_info.c new file mode 100644 index 0000000..c9d0b90 --- /dev/null +++ b/phl/phl_chan_info.c @@ -0,0 +1,366 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CHAN_INFO_C_ +#include "phl_headers.h" + +#ifdef CONFIG_PHL_CHANNEL_INFO + +struct chinfo_param { + struct rtw_phl_stainfo_t *sta; + u8 enable; +}; + +enum rtw_phl_status +_phl_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta, u8 enable) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + if (RTW_HAL_STATUS_SUCCESS == rtw_hal_cfg_chinfo(phl_info->hal, sta, enable)) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +#ifdef CONFIG_CMD_DISP +enum rtw_phl_status +phl_cmd_cfg_chinfo_hdl(struct phl_info_t *phl_info, u8 *param) +{ + struct chinfo_param *chinfo = (struct chinfo_param *)param; + + return _phl_cfg_chinfo(phl_info, chinfo->sta, chinfo->enable); +} + +static void _phl_cfg_chinfo_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status) +{ + if (cmd) { + _os_kmem_free(drv_priv, cmd, cmd_len); + cmd = NULL; + PHL_INFO("%s.....\n", __func__); + } +} + +enum rtw_phl_status +_phl_cmd_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta, u8 enable, + enum phl_cmd_type cmd_type, u32 cmd_timeout) +{ + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct chinfo_param *param = NULL; + u32 param_len; + + if (cmd_type == PHL_CMD_DIRECTLY) { + return _phl_cfg_chinfo(phl, sta, enable); + } + + param_len = sizeof(struct chinfo_param); + param = _os_kmem_alloc(phl_to_drvpriv(phl_info), param_len); + if (param == NULL) { + PHL_ERR("%s: alloc param failed!\n", __func__); + goto _exit; + } + + param->enable = enable; + param->sta =sta; + + sts = phl_cmd_enqueue(phl, + sta->wrole->hw_band, + MSG_EVT_CFG_CHINFO, + (u8 *)param, + param_len, + _phl_cfg_chinfo_done, + cmd_type, cmd_timeout); + + if (is_cmd_failure(sts)) { + /* Send cmd success, but wait cmd fail*/ + sts = RTW_PHL_STATUS_FAILURE; + } else if (sts != RTW_PHL_STATUS_SUCCESS) { + /* Send cmd fail */ + _os_kmem_free(phl_to_drvpriv(phl_info), param, param_len); + sts = RTW_PHL_STATUS_FAILURE; + } + +_exit: + return sts; +} +#endif + +enum rtw_phl_status rtw_phl_cmd_cfg_chinfo(void *phl, + struct rtw_phl_stainfo_t *sta, + u8 enable, + enum phl_cmd_type cmd_type, + u32 cmd_timeout) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + +#ifdef CONFIG_CMD_DISP + return _phl_cmd_cfg_chinfo(phl, sta, enable, cmd_type, cmd_timeout); +#else + return _phl_cfg_chinfo(phl_info, sta, enable); +#endif +} + +enum rtw_phl_status rtw_phl_query_chan_info(void *phl, u32 buf_len, + u8* chan_info_buffer, u32 *length, struct csi_header_t *csi_header) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *drv_priv = phl_to_drvpriv(phl_info); + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + struct chan_info_t *chan_info_pkt_latest = NULL; + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + + if(chan_info_buffer == NULL){ + PHL_ERR("buffer is not ready.\n"); + return status; + } + + /* Get the latest channel info from busy queue. */ + chan_info_pkt_latest = rtw_phl_query_busy_chaninfo_latest(drv_priv, phl_com); + if (chan_info_pkt_latest != NULL) { + if (buf_len < chan_info_pkt_latest->length) { + PHL_ERR("%s: Buffer length not sufficient! \n", __func__); + rtw_phl_enqueue_idle_chaninfo(drv_priv, phl_com, chan_info_pkt_latest); + return status; + } + /* copy raw data resources. */ + _os_mem_cpy(drv_priv, chan_info_buffer, + chan_info_pkt_latest->chan_info_buffer, chan_info_pkt_latest->length); + _os_mem_cpy(drv_priv, csi_header, + &chan_info_pkt_latest->csi_header, sizeof(struct csi_header_t)); + *length = chan_info_pkt_latest->length; + + rtw_phl_enqueue_idle_chaninfo(drv_priv, phl_com, chan_info_pkt_latest); + status = RTW_PHL_STATUS_SUCCESS; + } else { + PHL_INFO("%s: There is no channel info packet.\n", __func__); + } + return status; +} + +/*channel info packet pool init/deinit*/ +static void _phl_chaninfo_deinit (struct phl_info_t *phl_info) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + u8* chan_info_buffer = NULL; + u32 buf_len, i = 0; + FUNCIN(); + + chan_info_pool = (struct rx_chan_info_pool *)phl_info->phl_com->chan_info_pool; + if (NULL != chan_info_pool) { + _os_spinlock_free(phl_to_drvpriv(phl_info), + &chan_info_pool->idle_lock); + _os_spinlock_free(phl_to_drvpriv(phl_info), + &chan_info_pool->busy_lock); + for (i = 0; i < CHAN_INFO_PKT_TOTAL; i++) { + chan_info_buffer = chan_info_pool->channl_info_pkt[i].chan_info_buffer; + if (chan_info_buffer != NULL) { + _os_mem_free(phl_to_drvpriv(phl_info), chan_info_buffer, + CHAN_INFO_MAX_SIZE); + chan_info_pool->channl_info_pkt[i].chan_info_buffer = NULL; + } + } + buf_len = sizeof(*chan_info_pool); + _os_mem_free(phl_to_drvpriv(phl_info), chan_info_pool, buf_len); + } + + FUNCOUT(); +} + +static enum rtw_phl_status _phl_chaninfo_init(struct phl_info_t *phl_info) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct rx_chan_info_pool *chan_info_pool = NULL; + struct chan_info_t *chan_info_pkt = NULL; + u32 buf_len = 0, i = 0; + FUNCIN_WSTS(pstatus); + + buf_len = sizeof(*chan_info_pool); + chan_info_pool = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len); + + if (NULL != chan_info_pool) { + _os_mem_set(phl_to_drvpriv(phl_info), chan_info_pool, 0, buf_len); + INIT_LIST_HEAD(&chan_info_pool->idle); + INIT_LIST_HEAD(&chan_info_pool->busy); + _os_spinlock_init(phl_to_drvpriv(phl_info), + &chan_info_pool->idle_lock); + _os_spinlock_init(phl_to_drvpriv(phl_info), + &chan_info_pool->busy_lock); + chan_info_pool->idle_cnt = 0; + + for (i = 0; i < CHAN_INFO_PKT_TOTAL; i++) { + chan_info_pkt = &chan_info_pool->channl_info_pkt[i]; + chan_info_pkt->chan_info_buffer = _os_mem_alloc(phl_to_drvpriv(phl_info), + CHAN_INFO_MAX_SIZE); + if (NULL != chan_info_pkt->chan_info_buffer) { + chan_info_pkt->length = 0; + INIT_LIST_HEAD(&chan_info_pkt->list); + list_add_tail(&chan_info_pkt->list, &chan_info_pool->idle); + chan_info_pool->idle_cnt++; + } else { + pstatus = RTW_PHL_STATUS_RESOURCE; + break; + } + } + phl_info->phl_com->chan_info_pool = chan_info_pool; + } else { + pstatus = RTW_PHL_STATUS_RESOURCE; + } + + if (RTW_PHL_STATUS_SUCCESS != pstatus) + _phl_chaninfo_deinit(phl_info); + FUNCOUT_WSTS(pstatus); + + return pstatus; +} + +enum rtw_phl_status phl_chaninfo_init(struct phl_info_t *phl_info) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + + phl_status = _phl_chaninfo_init(phl_info); + if (phl_status != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("channel info pool allocate fail\n"); + + return phl_status; +} + +void phl_chaninfo_deinit(struct phl_info_t *phl_info) +{ + _phl_chaninfo_deinit(phl_info); +} + +u32 rtw_phl_get_chaninfo_idle_number(void* drv_priv, struct rtw_phl_com_t *phl_com) +{ + u32 number; + struct rx_chan_info_pool *chan_info_pool = NULL; + + chan_info_pool = phl_com->chan_info_pool; + number = chan_info_pool->idle_cnt; + return number; +} + +u32 rtw_phl_get_chaninfo_busy_number(void* drv_priv, struct rtw_phl_com_t *phl_com) +{ + u32 number; + struct rx_chan_info_pool *chan_info_pool = NULL; + + chan_info_pool = phl_com->chan_info_pool; + number = chan_info_pool->busy_cnt; + return number; +} + +struct chan_info_t *rtw_phl_query_idle_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + struct chan_info_t *chan_info_pkt = NULL; + + chan_info_pool = phl_com->chan_info_pool; + + _os_spinlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL); + if (false == list_empty(&chan_info_pool->idle)) { + chan_info_pkt = list_first_entry(&chan_info_pool->idle, + struct chan_info_t, list); + list_del(&chan_info_pkt->list); + chan_info_pool->idle_cnt--; + } + _os_spinunlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL); + + return chan_info_pkt; +} + +struct chan_info_t *rtw_phl_query_busy_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + struct chan_info_t *chan_info_pkt = NULL; + + chan_info_pool = phl_com->chan_info_pool; + + _os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + if (false == list_empty(&chan_info_pool->busy)) { + chan_info_pkt = list_first_entry(&chan_info_pool->busy, + struct chan_info_t, list); + list_del(&chan_info_pkt->list); + chan_info_pool->busy_cnt--; + } + _os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + + return chan_info_pkt; +} + +struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void* drv_priv, struct rtw_phl_com_t *phl_com) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + struct chan_info_t *chan_info_pkt = NULL; + + chan_info_pool = phl_com->chan_info_pool; + + _os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + if (false == list_empty(&chan_info_pool->busy)) { + chan_info_pkt = list_last_entry(&chan_info_pool->busy, + struct chan_info_t, list); + list_del(&chan_info_pkt->list); + chan_info_pool->busy_cnt--; + } + _os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + + return chan_info_pkt; +} + + +void rtw_phl_enqueue_idle_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com, + struct chan_info_t *chan_info_pkt) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + + chan_info_pool = phl_com->chan_info_pool; + + _os_spinlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL); + _os_mem_set(drv_priv, &chan_info_pkt->csi_header, 0, + sizeof( chan_info_pkt->csi_header)); + _os_mem_set(drv_priv, chan_info_pkt->chan_info_buffer, 0, + CHAN_INFO_MAX_SIZE); + chan_info_pkt->length = 0; + INIT_LIST_HEAD(&chan_info_pkt->list); + list_add_tail(&chan_info_pkt->list, &chan_info_pool->idle); + chan_info_pool->idle_cnt++; + _os_spinunlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL); +} + +struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void* drv_priv, + struct rtw_phl_com_t *phl_com, struct chan_info_t *chan_info_pkt) +{ + struct rx_chan_info_pool *chan_info_pool = NULL; + struct chan_info_t *chan_info_pkt_recycle = NULL; + + chan_info_pool = phl_com->chan_info_pool; + + _os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + /* enqueue the latest first. */ + INIT_LIST_HEAD(&chan_info_pkt->list); + list_add_tail(&chan_info_pkt->list, &chan_info_pool->busy); + chan_info_pool->busy_cnt++; + + /* if the number is greater than max, dequeue the oldest one.*/ + if (chan_info_pool->busy_cnt > MAX_CHAN_INFO_PKT_KEEP) { + chan_info_pkt_recycle = list_first_entry(&chan_info_pool->busy, + struct chan_info_t, list); + list_del(&chan_info_pkt_recycle->list); + chan_info_pool->busy_cnt--; + } + _os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL); + + return chan_info_pkt_recycle; +} + +#endif /* CONFIG_PHL_CHANNEL_INFO */ diff --git a/phl/phl_chan_info.h b/phl/phl_chan_info.h new file mode 100644 index 0000000..2936412 --- /dev/null +++ b/phl/phl_chan_info.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CHAN_INFO_H_ +#define _PHL_CHAN_INFO_H_ + +#ifdef CONFIG_PHL_CHANNEL_INFO +enum rtw_phl_status phl_chaninfo_init(struct phl_info_t *phl_info); +void phl_chaninfo_deinit(struct phl_info_t *phl_info); + +/* Channel info queue operation*/ +u32 rtw_phl_get_chaninfo_idle_number(void *drvpriv, struct rtw_phl_com_t *phl_com); +u32 rtw_phl_get_chaninfo_busy_number(void *drvpriv, struct rtw_phl_com_t *phl_com); +struct chan_info_t *rtw_phl_query_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com); + +struct chan_info_t *rtw_phl_query_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com); + +struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void *drvpriv, struct rtw_phl_com_t *phl_com); + + +void rtw_phl_enqueue_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com, + struct chan_info_t *chan_info_pkt); + +struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com, + struct chan_info_t *chan_info_pkt); + +enum rtw_phl_status +phl_cmd_cfg_chinfo_hdl(struct phl_info_t *phl_info, u8 *param); +#endif /* CONFIG_PHL_CHANNEL_INFO */ +#endif /* _PHL_CHAN_INFO_H_ */ diff --git a/phl/phl_chnlplan.c b/phl/phl_chnlplan.c new file mode 100644 index 0000000..afe1b51 --- /dev/null +++ b/phl/phl_chnlplan.c @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "phl_headers.h" +#include "phl_chnlplan.h" + +const struct chdef_2ghz chdef2g[MAX_CHDEF_2GHZ] = { + {0, {0x00, 0x00}, {0x00, 0x00}}, + {1, {0xff, 0x1f}, {0x00, 0x18}}, + {2, {0xff, 0x1f}, {0x00, 0x00}}, + {3, {0xff, 0x07}, {0x00, 0x00}}, + {4, {0xff, 0x3f}, {0x00, 0x00}}, + {5, {0x00, 0x1e}, {0x00, 0x00}}, + {6, {0xff, 0x3f}, {0x00, 0x38}}, +}; + + +const struct chdef_5ghz chdef5g[MAX_CHDEF_5GHZ] = { + {0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {1, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00}, + {2, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x00, 0x00, 0x00}, + {3, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x00, 0x00}, + {4, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x01}, {0x00, 0x00}, {0xff, 0x01}, 0x1f, 0x00, 0x00}, + {5, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x7f, 0x00}, {0x00, 0x00}, {0x7f, 0x00}, 0x0f, 0x00, 0x00}, + {6, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {7, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {8, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00}, + {9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {10, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x00, 0x00, 0x00}, + {12, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00}, + {13, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {14, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00}, + {16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0xff, 0x07}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {17, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x07}, {0x00, 0x00}, {0x00, 0x07}, 0x1f, 0x00, 0x00}, + {18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00}, + {19, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x00, 0x00, 0x00}, + {20, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x0f, 0x00, 0x00}, + {21, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x07}, {0x00, 0x00}, {0x00, 0x07}, 0x00, 0x00, 0x00}, + {22, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x1f, 0x00, 0x00}, + {23, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x00}, {0x00, 0x00}, {0xff, 0x00}, 0x1f, 0x00, 0x00}, + {24, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {25, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {26, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {27, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x1f, 0x07}, {0x1f, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {28, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {29, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {30, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {31, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {32, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00}, + {33, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x0f}, {0x00, 0x00}, {0x1f, 0x0f}, 0x1f, 0x00, 0x00}, + {34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00}, + {35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x00, 0x00, 0x00}, + {36, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x0f, {0xff, 0x0f}, {0xff, 0x0f}, {0xff, 0x0f}, 0x1f, 0x1f, 0x00}, + {37, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {38, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x00, 0x00, 0x00}, + {39, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x00}, {0x00, 0x00}, {0xff, 0x00}, 0x1f, 0x00, 0x1f}, + {40, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00}, + {41, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x1f, 0x00}, + {42, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x1f, 0x00}, + {43, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x06}, {0xff, 0x06}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {44, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x1f, 0x07}, {0x1f, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {45, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x1f, 0x00}, + {46, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00}, + {47, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x00, 0x00, 0x00}, + {48, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x00, 0x00, 0x00}, + {49, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x01}, {0x00, 0x00}, {0xff, 0x01}, 0x00, 0x00, 0x00}, + {50, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x0f}, {0x00, 0x00}, {0x00, 0x0f}, 0x1f, 0x00, 0x00}, + {51, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x00}, {0x00, 0x00}, {0x1f, 0x00}, 0x00, 0x00, 0x00}, + {52, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0xff, 0x00, 0x00}, + {53, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x0f, 0x00}, {0x00, 0x00}, {0x0f, 0x00}, 0x1f, 0x00, 0x00}, +}; + + +const struct regulatory_domain_mapping rdmap[MAX_RD_MAP_NUM] = { + {0x00, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 49}}, + {0x01, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 50}}, + {0x02, {REGULATION_ETSI, 3}, {REGULATION_ETSI, 7}}, + {0x03, {REGULATION_ACMA, 2}, {REGULATION_ACMA, 33}}, + {0x04, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 51}}, + {0x05, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 6}}, + {0x06, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 7}}, + {0x07, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 23}}, + {0x08, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 21}}, + {0x09, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 17}}, + {0x1b, {REGULATION_FCC, 2}, {REGULATION_FCC, 52}}, + {0x1c, {REGULATION_KCC, 2}, {REGULATION_KCC, 53}}, + {0x20, {REGULATION_WW, 1}, {REGULATION_NA, 0}}, + {0x21, {REGULATION_ETSI, 2}, {REGULATION_NA, 0}}, + {0x22, {REGULATION_FCC, 3}, {REGULATION_NA, 0}}, + {0x23, {REGULATION_MKK, 4}, {REGULATION_NA, 0}}, + {0x24, {REGULATION_ETSI, 5}, {REGULATION_NA, 0}}, + {0x25, {REGULATION_FCC, 3}, {REGULATION_FCC, 3}}, + {0x26, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 2}}, + {0x27, {REGULATION_MKK, 4}, {REGULATION_MKK, 2}}, + {0x28, {REGULATION_KCC, 1}, {REGULATION_KCC, 5}}, + {0x29, {REGULATION_FCC, 1}, {REGULATION_FCC, 6}}, + {0x2a, {REGULATION_FCC, 2}, {REGULATION_NA, 0}}, + {0x2b, {REGULATION_IC, 2}, {REGULATION_IC, 33}}, + {0x2c, {REGULATION_MKK, 2}, {REGULATION_NA, 0}}, + {0x2d, {REGULATION_CHILE, 1}, {REGULATION_CHILE, 22}}, + {0x2e, {REGULATION_WW, 3}, {REGULATION_WW, 37}}, + {0x2f, {REGULATION_CHILE, 1}, {REGULATION_CHILE, 38}}, + {0x30, {REGULATION_FCC, 1}, {REGULATION_FCC, 7}}, + {0x31, {REGULATION_FCC, 1}, {REGULATION_FCC, 8}}, + {0x32, {REGULATION_FCC, 1}, {REGULATION_FCC, 9}}, + {0x33, {REGULATION_FCC, 1}, {REGULATION_FCC, 10}}, + {0x34, {REGULATION_FCC, 3}, {REGULATION_FCC, 1}}, + {0x35, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 3}}, + {0x36, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 4}}, + {0x37, {REGULATION_MKK, 4}, {REGULATION_MKK, 10}}, + {0x38, {REGULATION_MKK, 4}, {REGULATION_MKK, 11}}, + {0x39, {REGULATION_NCC, 3}, {REGULATION_NCC, 12}}, + {0x3a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 2}}, + {0x3b, {REGULATION_ACMA, 2}, {REGULATION_ACMA, 1}}, + {0x3c, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 10}}, + {0x3d, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 15}}, + {0x3e, {REGULATION_KCC, 2}, {REGULATION_KCC, 3}}, + {0x3f, {REGULATION_FCC, 3}, {REGULATION_FCC, 22}}, + {0x40, {REGULATION_NCC, 3}, {REGULATION_NCC, 13}}, + {0x41, {REGULATION_WW, 6}, {REGULATION_NA, 0}}, + {0x42, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 14}}, + {0x43, {REGULATION_FCC, 3}, {REGULATION_FCC, 6}}, + {0x44, {REGULATION_NCC, 3}, {REGULATION_NCC, 9}}, + {0x45, {REGULATION_ACMA, 1}, {REGULATION_ACMA, 1}}, + {0x46, {REGULATION_FCC, 3}, {REGULATION_FCC, 15}}, + {0x47, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 10}}, + {0x48, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 7}}, + {0x49, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 6}}, + {0x4a, {REGULATION_IC, 3}, {REGULATION_IC, 33}}, + {0x4b, {REGULATION_KCC, 2}, {REGULATION_KCC, 22}}, + {0x4c, {REGULATION_FCC, 3}, {REGULATION_FCC, 28}}, + {0x4d, {REGULATION_MEX, 2}, {REGULATION_MEX, 1}}, + {0x4e, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 42}}, + {0x4f, {REGULATION_NA, 0}, {REGULATION_MKK, 43}}, + {0x50, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 16}}, + {0x51, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 9}}, + {0x52, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 17}}, + {0x53, {REGULATION_NCC, 3}, {REGULATION_NCC, 18}}, + {0x54, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 15}}, + {0x55, {REGULATION_FCC, 3}, {REGULATION_FCC, 1}}, + {0x56, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 19}}, + {0x57, {REGULATION_FCC, 3}, {REGULATION_FCC, 20}}, + {0x58, {REGULATION_MKK, 2}, {REGULATION_MKK, 14}}, + {0x59, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 21}}, + {0x5a, {REGULATION_NA, 0}, {REGULATION_FCC, 44}}, + {0x5b, {REGULATION_NA, 0}, {REGULATION_FCC, 45}}, + {0x5c, {REGULATION_NA, 0}, {REGULATION_FCC, 43}}, + {0x5d, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 8}}, + {0x5e, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 3}}, + {0x5f, {REGULATION_MKK, 2}, {REGULATION_MKK, 47}}, + {0x60, {REGULATION_FCC, 3}, {REGULATION_FCC, 9}}, + {0x61, {REGULATION_FCC, 2}, {REGULATION_FCC, 1}}, + {0x62, {REGULATION_FCC, 2}, {REGULATION_FCC, 3}}, + {0x63, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 23}}, + {0x64, {REGULATION_MKK, 2}, {REGULATION_MKK, 24}}, + {0x65, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 24}}, + {0x66, {REGULATION_FCC, 3}, {REGULATION_FCC, 27}}, + {0x67, {REGULATION_FCC, 3}, {REGULATION_FCC, 25}}, + {0x68, {REGULATION_FCC, 2}, {REGULATION_FCC, 27}}, + {0x69, {REGULATION_FCC, 2}, {REGULATION_FCC, 25}}, + {0x6a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 25}}, + {0x6b, {REGULATION_FCC, 1}, {REGULATION_FCC, 29}}, + {0x6c, {REGULATION_FCC, 1}, {REGULATION_FCC, 26}}, + {0x6d, {REGULATION_FCC, 2}, {REGULATION_FCC, 28}}, + {0x6e, {REGULATION_FCC, 1}, {REGULATION_FCC, 25}}, + {0x6f, {REGULATION_NA, 0}, {REGULATION_ETSI, 6}}, + {0x70, {REGULATION_NA, 0}, {REGULATION_ETSI, 30}}, + {0x71, {REGULATION_NA, 0}, {REGULATION_ETSI, 25}}, + {0x72, {REGULATION_NA, 0}, {REGULATION_ETSI, 31}}, + {0x73, {REGULATION_FCC, 1}, {REGULATION_FCC, 1}}, + {0x74, {REGULATION_FCC, 2}, {REGULATION_FCC, 19}}, + {0x75, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 32}}, + {0x76, {REGULATION_FCC, 2}, {REGULATION_FCC, 22}}, + {0x77, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 34}}, + {0x78, {REGULATION_FCC, 3}, {REGULATION_FCC, 35}}, + {0x79, {REGULATION_MKK, 2}, {REGULATION_MKK, 2}}, + {0x7a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 28}}, + {0x7b, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 46}}, + {0x7c, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 47}}, + {0x7d, {REGULATION_MKK, 4}, {REGULATION_MKK, 48}}, + {0x7e, {REGULATION_MKK, 2}, {REGULATION_MKK, 48}}, + {0x7f, {REGULATION_WW, 1}, {REGULATION_WW, 36}}, +}; + + + diff --git a/phl/phl_chnlplan.h b/phl/phl_chnlplan.h new file mode 100644 index 0000000..c12fdbc --- /dev/null +++ b/phl/phl_chnlplan.h @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CHNLPLAN_H_ +#define _PHL_CHNLPLAN_H_ + +#define REGULATION_CHPLAN_VERSION 58 + +enum REGULATION { + REGULATION_WW = 0, + REGULATION_ETSI = 1, + REGULATION_FCC = 2, + REGULATION_MKK = 3, + REGULATION_KCC = 4, + REGULATION_NCC = 5, + REGULATION_ACMA = 6, + REGULATION_NA = 7, + REGULATION_IC = 8, + REGULATION_CHILE = 9, + REGULATION_MEX = 10, + REGULATION_MAX = 11, +}; + +struct chdef_2ghz { + /* ch_def index */ + u8 idx; + + /* support channel list + * support_ch[0]: bit(0~7) stands for ch(1~8) + * support_ch[1]: bit(0~5) stands for ch (9~14) + */ + u8 support_ch[2]; + + /* passive ch list + * passive[0]: bit(0~7) stands for ch(1~8) + * passive[1]: bit(0~5) stands for ch (9~14) + */ + u8 passive[2]; +}; + +struct chdef_5ghz { + /* ch_def index */ + u8 idx; + + /* + * band1 support channel list, passive and dfs + * bit0 stands for ch36 + * bit1 stands for ch40 + * bit2 stands for ch44 + * bit3 stands for ch48 + */ + u8 support_ch_b1; + u8 passive_b1; + u8 dfs_b1; + + /* + * band2 support channel list, passive and dfs + * bit0 stands for ch52 + * bit1 stands for ch56 + * bit2 stands for ch60 + * bit3 stands for ch64 + */ + u8 support_ch_b2; + u8 passive_b2; + u8 dfs_b2; + + /* + * band3 support channel list, passive and dfs + * byte[0]: + * bit0 stands for ch100 + * bit1 stands for ch104 + * bit2 stands for ch108 + * bit3 stands for ch112 + * bit4 stands for ch116 + * bit5 stands for ch120 + * bit6 stands for ch124 + * bit7 stands for ch128 + * byte[1]: + * bit0 stands for ch132 + * bit1 stands for ch136 + * bit2 stands for ch140 + * bit3 stands for ch144 + */ + u8 support_ch_b3[2]; + u8 passive_b3[2]; + u8 dfs_b3[2]; + + /* + * band4 support channel list, passive and dfs + * bit0 stands for ch149 + * bit1 stands for ch153 + * bit2 stands for ch157 + * bit3 stands for ch161 + * bit4 stands for ch165 + * bit5 stands for ch169 + * bit6 stands for ch173 + * bit7 stands for ch177 + */ + u8 support_ch_b4; + u8 passive_b4; + u8 dfs_b4; +}; + +struct freq_plan { + u8 regulation; + u8 ch_idx; +}; + +struct regulatory_domain_mapping { + u8 domain_code; + struct freq_plan freq_2g; + struct freq_plan freq_5g; +}; + +#define MAX_CHDEF_2GHZ 7 +#define MAX_CHDEF_5GHZ 54 +#define MAX_RD_MAP_NUM 108 + + + +#endif /* _PHL_CHNLPLAN_H_ */ diff --git a/phl/phl_chnlplan_6g.c b/phl/phl_chnlplan_6g.c new file mode 100644 index 0000000..db629e6 --- /dev/null +++ b/phl/phl_chnlplan_6g.c @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "phl_headers.h" +#include "phl_chnlplan.h" +#include "phl_chnlplan_6g.h" + +const struct chdef_6ghz chdef6g[MAX_CHDEF_6GHZ] = { + {0, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, + {1, {0xff, 0xff, 0xff}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, + {2, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x3f, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, + {3, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0xff, 0xff, 0x03}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, + {4, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0xff, 0x07}, {0x00, 0x00}}, + {5, {0xff, 0xff, 0xff}, {0xff, 0xff, 0xff}, 0x3f, 0x3f, {0xff, 0xff, 0x03}, {0xff, 0xff, 0x03}, {0xff, 0x07}, {0xff, 0x07}}, +}; + +const struct regulatory_domain_mapping_6g rdmap6[MAX_RD_MAP_NUM_6GHZ] = { + {0x00, REGULATION_NA, 0}, + {0x01, REGULATION_FCC, 1}, + {0x02, REGULATION_FCC, 2}, + {0x03, REGULATION_FCC, 3}, + {0x04, REGULATION_FCC, 4}, + {0x7f, REGULATION_WW, 5}, +}; + + + diff --git a/phl/phl_chnlplan_6g.h b/phl/phl_chnlplan_6g.h new file mode 100644 index 0000000..86a92d7 --- /dev/null +++ b/phl/phl_chnlplan_6g.h @@ -0,0 +1,85 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CHNLPLAN_6GHZ_H_ +#define _PHL_CHNLPLAN_6GHZ_H_ + + +/* + * 6 GHz channel group from UNII-5 to UNII-8 + * channel index diff is 4 : minimum working bandwidth : 20 MHz + * => next channel index = current index + 4 + */ + +struct chdef_6ghz { + /* ch_def index */ + u8 idx; + + /* + * UNII-5 support channel list, ch1 ~ ch93, total : 24 + * bit0 stands for ch1 + * bit1 stands for ch5 + * bit2 stands for ch9 + * ... + * bit23 stands for ch93 + */ + u8 support_ch_u5[3]; + u8 passive_u5[3]; + + /* + * UNII-6 support channel list, ch97 ~ ch117, total : 6 + * bit0 stands for ch97 + * bit1 stands for ch101 + * bit2 stands for ch105 + * bit3 stands for ch109 + * bit4 stands for ch113 + * bit5 stands for ch117 + */ + u8 support_ch_u6; + u8 passive_u6; + + /* + * UNII-7 support channel list, ch121 ~ ch189, total : 18 + * bit0 stands for ch121 + * bit1 stands for ch125 + * bit2 stands for ch129 + * ... + * bit17 stands for ch189 + */ + u8 support_ch_u7[3]; + u8 passive_u7[3]; + + /* + * UNII-8 support channel list, ch193 ~ ch237, total : 12 + * bit0 stands for ch193 + * bit1 stands for ch197 + * bit2 stands for ch201 + * ... + * bit10 stands for ch233 + */ + u8 support_ch_u8[2]; + u8 passive_u8[2]; +}; + +struct regulatory_domain_mapping_6g { + u8 domain_code; + u8 regulation; + u8 ch_idx; +}; + +#define MAX_CHDEF_6GHZ 6 +#define MAX_RD_MAP_NUM_6GHZ 6 + + +#endif /* _PHL_CHNLPLAN_6GHZ_H_ */ diff --git a/phl/phl_cmd_btc.c b/phl/phl_cmd_btc.c new file mode 100644 index 0000000..358206b --- /dev/null +++ b/phl/phl_cmd_btc.c @@ -0,0 +1,515 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_BTC_C_ +#include "phl_headers.h" + +#ifdef CONFIG_BTCOEX +#ifdef CONFIG_PHL_CMD_BTC +static void _fail_hdlr(void *phl, struct phl_msg *msg) +{ +} + +static void _hdl_tmr(void *phl, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + rtw_hal_btc_timer(phl_info->hal, (void *)msg->inbuf); +} + +static void _hdl_role_notify(void *phl, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_role_cmd *rcmd = NULL; + struct rtw_wifi_role_t *wrole = NULL; + struct rtw_phl_stainfo_t *sta = NULL; + + if (msg->inbuf && (msg->inlen == sizeof(struct rtw_role_cmd))) { + rcmd = (struct rtw_role_cmd *)msg->inbuf; + wrole = rcmd->wrole; + sta = rtw_phl_get_stainfo_self(phl_info, wrole); + + rtw_hal_btc_update_role_info_ntfy(phl_info->hal, + rcmd->wrole->id, wrole, sta, rcmd->rstate); + } else { + PHL_ERR("%s: invalid msg, buf = %p, len = %d\n", + __func__, msg->inbuf, msg->inlen); + } +} + +static void _hdl_pkt_evt_notify(void *phl, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_pkt_evt_ntfy *pkt_evt = NULL; + struct rtw_wifi_role_t *wrole = NULL; + + if (msg->inbuf && (msg->inlen == sizeof(struct rtw_pkt_evt_ntfy))) { + pkt_evt = (struct rtw_pkt_evt_ntfy *)msg->inbuf; + wrole = pkt_evt->wrole; /* not used currently */ + + rtw_hal_btc_packet_event_ntfy(phl_info->hal, + (u8)pkt_evt->type); + } else { + PHL_ERR("%s: invalid msg, buf = %p, len = %d\n", + __func__, msg->inbuf, msg->inlen); + } +} + +static enum phl_mdl_ret_code _btc_cmd_init(void *phl, void *dispr, + void **priv) +{ + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + *priv = phl; + return MDL_RET_SUCCESS; +} + +static void _btc_cmd_deinit(void *dispr, void *priv) +{ + PHL_INFO("[BTCCMD], %s(): \n", __func__); +} + +static enum phl_mdl_ret_code _btc_cmd_start(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + return ret; +} + +static enum phl_mdl_ret_code _btc_cmd_stop(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + return ret; +} + +static enum phl_mdl_ret_code +_btc_internal_pre_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + /*PHL_INFO("[BTCCMD], msg->band_idx = %d, msg->msg_id = 0x%x\n", + msg->band_idx, msg->msg_id);*/ + + switch(evt_id) { + case MSG_EVT_BTC_REQ_BT_SLOT: + PHL_INFO("[BTCCMD], MSG_EVT_BTC_REQ_BT_SLOT \n"); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_BTC_PKT_EVT_NTFY: + PHL_INFO("[BTCCMD], MSG_EVT_BTC_PKT_EVT_NTFY \n"); + _hdl_pkt_evt_notify(phl_info, msg); + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_btc_internal_post_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + switch(evt_id) { + case MSG_EVT_BTC_TMR: + PHL_DBG("[BTCCMD], MSG_EVT_BTC_TMR \n"); + _hdl_tmr(phl_info, msg); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_BTC_FWEVNT: + PHL_DBG("[BTCCMD], MSG_EVT_BTC_FWEVNT \n"); + rtw_hal_btc_fwinfo_ntfy(phl_info->hal); + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_btc_internal_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + ret = _btc_internal_pre_msg_hdlr(phl_info, dispr, msg); + else + ret = _btc_internal_post_msg_hdlr(phl_info, dispr, msg); + + return ret; +} + +static enum phl_mdl_ret_code +_btc_external_pre_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + enum band_type band = BAND_ON_5G; + struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal); + enum phl_phy_idx phy_idx = HW_PHY_0; + + /*PHL_INFO("[BTCCMD], msg->band_idx = %d, msg->msg_id = 0x%x\n", + msg->band_idx, msg->msg_id);*/ + + switch(evt_id) { + case MSG_EVT_SCAN_START: + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_SCAN) + break; + + if (msg->band_idx == HW_BAND_1) + phy_idx = HW_PHY_1; + PHL_INFO("[BTCCMD], MSG_EVT_SCAN_START \n"); + band = hal_com->band[msg->band_idx].cur_chandef.band; + rtw_hal_btc_scan_start_ntfy(phl_info->hal, phy_idx, band); + + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_CONNECT_START: + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_CONNECT) + break; + + PHL_INFO("[BTCCMD], MSG_EVT_CONNECT_START \n"); + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_btc_external_post_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + struct hal_info_t *hal_info = (struct hal_info_t *)phl_info->hal; + enum phl_phy_idx phy_idx = HW_PHY_0; + + switch(evt_id) { + case MSG_EVT_SCAN_END: + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_SCAN) + break; + + if (msg->band_idx == HW_BAND_1) + phy_idx = HW_PHY_1; + PHL_DBG("[BTCCMD], MSG_EVT_SCAN_END \n"); + rtw_hal_btc_scan_finish_ntfy(hal_info, phy_idx); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_CONNECT_END: + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_CONNECT) + break; + + PHL_DBG("[BTCCMD], MSG_EVT_CONNECT_END \n"); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_ROLE_NTFY: + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_MDL_MRC) + break; + + PHL_DBG("[BTCCMD], MSG_EVT_ROLE_NTFY \n"); + _hdl_role_notify(phl_info, msg); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_BTC_TMR: + PHL_DBG("[BTCCMD], MSG_EVT_BTC_TMR \n"); + _hdl_tmr(phl_info, msg); + ret = MDL_RET_SUCCESS; + break; + + case MSG_EVT_BTC_FWEVNT: + PHL_DBG("[BTCCMD], MSG_EVT_BTC_FWEVNT \n"); + rtw_hal_btc_fwinfo_ntfy(phl_info->hal); + ret = MDL_RET_SUCCESS; + break; + + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_btc_external_msg_hdlr(struct phl_info_t *phl_info, + void *dispr, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + ret = _btc_external_pre_msg_hdlr(phl_info, dispr, msg); + else + ret = _btc_external_post_msg_hdlr(phl_info, dispr, msg); + + return ret; +} + +static enum phl_mdl_ret_code +_btc_msg_hdlr(void *dispr, void *priv, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + + FUNCIN(); + + if (IS_MSG_FAIL(msg->msg_id)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "%s: cmd dispatcher notify cmd failure: 0x%x.\n", + __FUNCTION__, msg->msg_id); + _fail_hdlr(phl_info, msg); + FUNCOUT(); + return MDL_RET_FAIL; + } + + if (IS_PRIVATE_MSG(msg->msg_id)) { + FUNCOUT(); + return ret; + } + + switch(MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_MDL_BTC: + ret = _btc_internal_msg_hdlr(phl_info, dispr, msg); + break; + + default: + ret = _btc_external_msg_hdlr(phl_info, dispr, msg); + break; + } + + FUNCOUT(); + return ret; +} + +static enum phl_mdl_ret_code +_btc_set_info(void *dispr, void *priv, + struct phl_module_op_info *info) +{ + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_btc_query_info(void *dispr, void *priv, + struct phl_module_op_info *info) +{ + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + return MDL_RET_SUCCESS; +} + +enum rtw_phl_status phl_register_btc_module(struct phl_info_t *phl_info) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_bk_module_ops bk_ops = {0}; + + PHL_INFO("[BTCCMD], %s(): \n", __func__); + + bk_ops.init = _btc_cmd_init; + bk_ops.deinit = _btc_cmd_deinit; + bk_ops.start = _btc_cmd_start; + bk_ops.stop = _btc_cmd_stop; + bk_ops.msg_hdlr = _btc_msg_hdlr; + bk_ops.set_info = _btc_set_info; + bk_ops.query_info = _btc_query_info; + + phl_status = phl_disp_eng_register_module(phl_info, HW_BAND_0, + PHL_MDL_BTC, &bk_ops); + if (RTW_PHL_STATUS_SUCCESS != phl_status) { + PHL_ERR("Failed to register BTC module in cmd dispr of hw band 0\n"); + } + + return phl_status; +} + +bool rtw_phl_btc_send_cmd(struct rtw_phl_com_t *phl_com, + u8 *buf, u32 len, u16 ev_id) +{ + struct phl_info_t *phl_info = phl_com->phl_priv; + u8 band_idx = HW_BAND_0; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + msg.inbuf = buf; + msg.inlen = len; + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_BTC); + msg.band_idx = band_idx; + switch (ev_id) { + case BTC_HMSG_TMR_EN: + SET_MSG_EVT_ID_FIELD(msg.msg_id, + MSG_EVT_BTC_TMR); + break; + case BTC_HMSG_SET_BT_REQ_SLOT: + SET_MSG_EVT_ID_FIELD(msg.msg_id, + MSG_EVT_BTC_REQ_BT_SLOT); + break; + case BTC_HMSG_FW_EV: + SET_MSG_EVT_ID_FIELD(msg.msg_id, + MSG_EVT_BTC_FWEVNT); + break; + default: + PHL_ERR("%s: Unknown msg !\n", __func__); + return false; + } + + if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != + RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s: [BTC] dispr_send_msg failed !\n", __func__); + return false; + } + + return true; +} + +static void +_phl_pkt_evt_ntfy_done(void* priv, struct phl_msg* msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + + if(msg->inbuf && msg->inlen){ + _os_mem_free(phl_to_drvpriv(phl_info), + msg->inbuf, msg->inlen); + } +} + +void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_pkt_evt_ntfy *pkt_evt = NULL; + + pkt_evt = (struct rtw_pkt_evt_ntfy *)_os_mem_alloc( + phl_to_drvpriv(phl_info), sizeof(struct rtw_pkt_evt_ntfy)); + if (pkt_evt == NULL) { + PHL_ERR("%s: alloc packet cmd fail.\n", __func__); + return; + } + + pkt_evt->type = pkt_evt_type; + + msg.inbuf = (u8 *)pkt_evt; + msg.inlen = sizeof(struct rtw_pkt_evt_ntfy); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_BTC); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_BTC_PKT_EVT_NTFY); + msg.band_idx = HW_BAND_0; + attr.completion.completion = _phl_pkt_evt_ntfy_done; + attr.completion.priv = phl_info; + + if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != + RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s: dispr_send_msg failed !\n", __func__); + goto cmd_fail; + } + + return; + +cmd_fail: + _os_mem_free(phl_to_drvpriv(phl_info), pkt_evt, + sizeof(struct rtw_pkt_evt_ntfy)); +} + +u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type) +{ + u8 pkt_evt_type = BTC_PKT_EVT_MAX; + + switch (packet_type) { + case PACKET_NORMAL: + pkt_evt_type = BTC_PKT_EVT_NORMAL; + break; + case PACKET_DHCP: + pkt_evt_type = BTC_PKT_EVT_DHCP; + break; + case PACKET_ARP: + pkt_evt_type = BTC_PKT_EVT_ARP; + break; + case PACKET_EAPOL: + pkt_evt_type = BTC_PKT_EVT_EAPOL; + break; + case PACKET_EAPOL_START: + pkt_evt_type = BTC_PKT_EVT_EAPOL_START; + break; + default: + PHL_ERR("%s packet type(%d) not support\n", + __func__, packet_type); + break; + } + + return pkt_evt_type; +} +#endif /*CONFIG_PHL_CMD_BTC*/ + +#ifndef CONFIG_FSM +int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify, + struct rtw_phl_btc_ntfy *ntfy) +{ + PHL_ERR("CMD_BTC not support :%s\n", __func__); + return 0; +} +void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate) +{ + struct rtw_phl_btc_ntfy ntfy = {0}; + struct rtw_phl_btc_role_info_param *prinfo = &ntfy.u.rinfo; + + prinfo->role_id = role_id; + prinfo->rstate = rstate; + + ntfy.notify = PHL_BTC_NTFY_ROLE_INFO; + ntfy.ops = NULL; + ntfy.priv = NULL; + ntfy.ntfy_cb = NULL; + + rtw_phl_btc_notify(phl, ntfy.notify, &ntfy); +} + +void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg) +{ +} +#endif + +#endif /*CONFIG_BTCOEX*/ + diff --git a/phl/phl_cmd_btc.h b/phl/phl_cmd_btc.h new file mode 100644 index 0000000..f518293 --- /dev/null +++ b/phl/phl_cmd_btc.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_BTC_DISPATCH_H_ +#define _PHL_BTC_DISPATCH_H_ + +enum rtw_phl_status phl_register_btc_module(struct phl_info_t *phl_info); + + +#endif /* _PHL_BTC_DISPATCH_H_ */ diff --git a/phl/phl_cmd_dispatch.h b/phl/phl_cmd_dispatch.h new file mode 100644 index 0000000..a6e6ce2 --- /dev/null +++ b/phl/phl_cmd_dispatch.h @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_CMD_DISP_ENG_H_ +#define __PHL_CMD_DISP_ENG_H_ +#define SHARE_THREAD_MODE (0x1) +#define SOLO_THREAD_MODE (0x2) +/** + * phl_cmd_dispatch_engine, + * @phl_info: for general reference usage. + * @dispatcher: array of cmd dispatcher, + * each dispatch is design to address coexist issue for each PHY instance. + * @phy_num: current PHY instance number + * @token_mgnt_thread: token mgnt thread + * @token_chk: semaphore to wake up token mgnt thread + * @thread_mode: indicate current thread operation mode. + * SHARE_THREAD_MODE means all dispatcher share an background thread + * SOLO_THREAD_MODE means each disaptcher has a dedicated background thread + * @msg_q_sema: (opt) only used in SHARE_THREAD_MODE, used to wake up shared background thread + * @share_thread: (opt) only used in SHARE_THREAD_MODE, context of shared background thread + */ +struct phl_cmd_dispatch_engine { + struct phl_info_t *phl_info; + void **dispatcher; //an array of struct cmd_dispatcher + u8 phy_num; + u8 thread_mode; + _os_sema msg_q_sema; + _os_thread share_thread; +#ifdef CONFIG_CMD_DISP_SOLO_MODE + _os_sema dispr_ctrl_sema; /* keep msg from different dispr sequentially forward to ctrl*/ +#endif +}; + + +/* functions called in phl layer*/ +enum rtw_phl_status phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num); +enum rtw_phl_status phl_disp_eng_deinit(struct phl_info_t *phl); +enum rtw_phl_status phl_disp_eng_start(struct phl_info_t *phl); +enum rtw_phl_status phl_disp_eng_stop(struct phl_info_t *phl); + +/* bk module would be initialized in phl_disp_eng_register_module call + * as for de-initialization, user can use phl_disp_eng_deregister_module as pair-wise operation + * or phl_disp_eng_deinit would deinit all bk modules per dispatcher +*/ +enum rtw_phl_status phl_disp_eng_register_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_bk_module_ops *ops); + +enum rtw_phl_status phl_disp_eng_deregister_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id); +enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx); +u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx); +u8 phl_disp_eng_is_fg_empty(struct phl_info_t *phl, u8 band_idx); +enum rtw_phl_status phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl, u8 band_idx, + struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl, u8 band_idx, + struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_set_bk_module_info(struct phl_info_t *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_query_bk_module_info(struct phl_info_t *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_set_src_info(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_query_src_info(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_module_op_info *op_info); +enum rtw_phl_status phl_disp_eng_send_msg(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_msg_attribute *attr, u32 *msg_hdl); +enum rtw_phl_status phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl); +enum rtw_phl_status phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx); + +enum rtw_phl_status phl_disp_eng_add_token_req(struct phl_info_t *phl, u8 band_idx, + struct phl_cmd_token_req *req, u32 *req_hdl); +enum rtw_phl_status phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl); +enum rtw_phl_status phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl); +enum rtw_phl_status phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id mdl_id, + bool allow_io); +void phl_disp_eng_notify_shall_stop(struct phl_info_t *phl); + +enum rtw_phl_status phl_disp_eng_set_msg_disp_seq(struct phl_info_t *phl, + struct phl_msg_attribute *attr, + struct msg_self_def_seq *seq); +u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl); +#ifdef CONFIG_CMD_DISP +/* following functions are only used inside phl_cmd_dispatch_eng.c */ +enum rtw_phl_status dispr_init(struct phl_info_t *phl, void **dispr, u8 idx); +enum rtw_phl_status dispr_deinit(struct phl_info_t *phl, void *dispr); +enum rtw_phl_status dispr_start(void *dispr); +bool is_dispr_started(void *dispr); +enum rtw_phl_status dispr_stop(void *dispr); +enum rtw_phl_status dispr_register_module(void *dispr, + enum phl_module_id id, + struct phl_bk_module_ops *ops); +enum rtw_phl_status dispr_deregister_module(void *dispr, + enum phl_module_id id); +enum rtw_phl_status dispr_module_init(void *dispr); +enum rtw_phl_status dispr_module_deinit(void *dispr); +enum rtw_phl_status dispr_module_start(void *dispr); +enum rtw_phl_status dispr_module_stop(void *dispr); +enum rtw_phl_status dispr_get_cur_cmd_req(void *dispr, void **handle); +enum rtw_phl_status dispr_set_cur_cmd_info(void *dispr, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_query_cur_cmd_info(void *dispr, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_get_bk_module_handle(void *dispr, + enum phl_module_id id, + void **handle); +enum rtw_phl_status dispr_set_bk_module_info(void *dispr, void *handle, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_query_bk_module_info(void *dispr, void *handle, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_set_src_info(void *dispr, struct phl_msg *msg, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_query_src_info(void *dispr, struct phl_msg *msg, + struct phl_module_op_info *op_info); +enum rtw_phl_status dispr_send_msg(void *dispr, struct phl_msg *msg, + struct phl_msg_attribute *attr, u32 *msg_hdl); +enum rtw_phl_status dispr_cancel_msg(void *dispr, u32 *msg_hdl); +enum rtw_phl_status dispr_clr_pending_msg(void *dispr); + +enum rtw_phl_status dispr_add_token_req(void *dispr, + struct phl_cmd_token_req *req, u32 *req_hdl); +enum rtw_phl_status dispr_cancel_token_req(void *dispr, u32 *req_hdl); +enum rtw_phl_status dispr_free_token(void *dispr, u32 *req_hdl); +enum rtw_phl_status dispr_notify_dev_io_status(void *dispr, enum phl_module_id mdl_id, bool allow_io); +void dispr_notify_shall_stop(void *dispr); +u8 dispr_is_fg_empty(void *dispr); +void dispr_share_thread_loop_hdl(void *dispr); +void dispr_share_thread_leave_hdl(void *dispr); +void dispr_share_thread_stop_prior_hdl(void *dispr); +void dispr_share_thread_stop_post_hdl(void *dispr); + +enum rtw_phl_status dispr_set_dispatch_seq(void *dispr, struct phl_msg_attribute *attr, + struct msg_self_def_seq* seq); + +/*ollowing functions are called inside phl_cmd_dispatcher.c */ +#define IS_DISPR_CTRL(_mdl_id) ((_mdl_id) < PHL_BK_MDL_ROLE_START) +#define disp_eng_is_solo_thread_mode(_phl) \ + ((_phl)->disp_eng.thread_mode == SOLO_THREAD_MODE) +void disp_eng_notify_share_thread(struct phl_info_t *phl, void *dispr); +void dispr_ctrl_hook_ops(void *dispr, struct phl_bk_module_ops *ops); +u8 disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl); +#ifdef CONFIG_CMD_DISP_SOLO_MODE +void dispr_ctrl_sema_down(struct phl_info_t *phl); +void dispr_ctrl_sema_up(struct phl_info_t *phl); +#endif +#endif +#endif /* __PHL_PHY_H_ */ diff --git a/phl/phl_cmd_dispatch_engine.c b/phl/phl_cmd_dispatch_engine.c new file mode 100644 index 0000000..6bf4f6a --- /dev/null +++ b/phl/phl_cmd_dispatch_engine.c @@ -0,0 +1,770 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_PHY_MGNT_C_ +#include "phl_headers.h" +#ifdef CONFIG_CMD_DISP + +enum rtw_phl_status phl_disp_eng_bk_module_deinit(struct phl_info_t *phl); +enum rtw_phl_status _disp_eng_get_dispr_by_idx(struct phl_info_t *phl, + u8 band_idx, + void **dispr); + +int share_thread_hdl(void *param) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)param; + void *d = phl_to_drvpriv(phl_info); + struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng); + u8 i = 0; + + PHL_INFO("%s enter\n", __FUNCTION__); + while (!_os_thread_check_stop(d, &(disp_eng->share_thread))) { + + _os_sema_down(d, &disp_eng->msg_q_sema); + + /* A simple for-loop would guarantee + * all dispatcher split entire bandwidth of shared thread evenly, + * if adopting FIFO rule here, + * would lead to disproportionate distribution of thread bandwidth. + */ + for (i = 0 ; i < disp_eng->phy_num; i++) { + if(_os_thread_check_stop(d, &(disp_eng->share_thread))) + break; + dispr_share_thread_loop_hdl(disp_eng->dispatcher[i]); + } + } + for (i = 0 ; i < disp_eng->phy_num; i++) + dispr_share_thread_leave_hdl(disp_eng->dispatcher[i]); + _os_thread_wait_stop(d, &(disp_eng->share_thread)); + PHL_INFO("%s down\n", __FUNCTION__); + return 0; +} + +enum rtw_phl_status +phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num) +{ + u8 i = 0; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + void *d = phl_to_drvpriv(phl); + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + if (disp_eng->dispatcher != NULL) { + PHL_ERR("[PHY]: %s, not empty\n",__FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + disp_eng->phl_info = phl; + disp_eng->phy_num = phy_num; +#ifdef CONFIG_CMD_DISP_SOLO_MODE + disp_eng->thread_mode = SOLO_THREAD_MODE; +#else + disp_eng->thread_mode = SHARE_THREAD_MODE; +#endif + disp_eng->dispatcher = _os_mem_alloc(d, sizeof(void*) * phy_num); +#ifdef CONFIG_CMD_DISP_SOLO_MODE + _os_sema_init(d, &(disp_eng->dispr_ctrl_sema), 1); +#endif + if (disp_eng->dispatcher == NULL) { + disp_eng->phy_num = 0; + PHL_ERR("[PHY]: %s, alloc fail\n",__FUNCTION__); + return RTW_PHL_STATUS_RESOURCE; + } + + for (i = 0 ; i < phy_num; i++) { + status = dispr_init(phl, &(disp_eng->dispatcher[i]), i); + if(status != RTW_PHL_STATUS_SUCCESS) + break; + } + + if (status != RTW_PHL_STATUS_SUCCESS) + phl_disp_eng_deinit(phl); + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +phl_disp_eng_deinit(struct phl_info_t *phl) +{ + u8 i = 0; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + void *d = phl_to_drvpriv(phl); + + if (disp_eng->dispatcher == NULL) + return RTW_PHL_STATUS_FAILURE; + + phl_disp_eng_bk_module_deinit(phl); + + for (i = 0 ; i < disp_eng->phy_num; i++) { + if(disp_eng->dispatcher[i] == NULL) + continue; + dispr_deinit(phl, disp_eng->dispatcher[i]); + disp_eng->dispatcher[i] = NULL; + } +#ifdef CONFIG_CMD_DISP_SOLO_MODE + _os_sema_free(d, &(disp_eng->dispr_ctrl_sema)); +#endif + if (disp_eng->phy_num) { + _os_mem_free(d, disp_eng->dispatcher, + sizeof(void *) * (disp_eng->phy_num)); + disp_eng->dispatcher = NULL; + disp_eng->phy_num = 0; + } + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +phl_disp_eng_bk_module_deinit(struct phl_info_t *phl) +{ + u8 i = 0; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + + for (i = 0 ; i < disp_eng->phy_num; i++) { + if(disp_eng->dispatcher[i] == NULL) + continue; + dispr_module_deinit(disp_eng->dispatcher[i]); + } + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +phl_disp_eng_start(struct phl_info_t *phl) +{ + u8 i = 0; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + void *d = phl_to_drvpriv(phl); + + _os_sema_init(d, &(disp_eng->msg_q_sema), 0); + if (!disp_eng_is_solo_thread_mode(phl)) { + _os_thread_init(d, &(disp_eng->share_thread), share_thread_hdl, phl, + "disp_eng_share_thread"); + _os_thread_schedule(d, &(disp_eng->share_thread)); + } + for (i = 0 ; i < disp_eng->phy_num; i++){ + if(disp_eng->dispatcher[i] == NULL) + continue; + dispr_start(disp_eng->dispatcher[i]); + dispr_module_start(disp_eng->dispatcher[i]); + } + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +phl_disp_eng_stop(struct phl_info_t *phl) +{ + u8 i = 0; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + void *d = phl_to_drvpriv(phl); + u8 solo_mode = (disp_eng_is_solo_thread_mode(phl)) ? (true) : (false); + + if (disp_eng->dispatcher == NULL) { + PHL_ERR("[PHY]: %s, abnomarl state\n",__FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; + } + + for (i = 0 ; i < disp_eng->phy_num; i++) { + if(disp_eng->dispatcher[i] == NULL) + continue; + dispr_module_stop(disp_eng->dispatcher[i]); + if (solo_mode == true) + dispr_stop(disp_eng->dispatcher[i]); + else + dispr_share_thread_stop_prior_hdl(disp_eng->dispatcher[i]); + } + + if (solo_mode == false) { + _os_thread_stop(d, &(disp_eng->share_thread)); + _os_sema_up(d, &(disp_eng->msg_q_sema)); + _os_thread_deinit(d, &(disp_eng->share_thread)); + + for (i = 0 ; i < disp_eng->phy_num; i++) + dispr_share_thread_stop_post_hdl(disp_eng->dispatcher[i]); + } + _os_sema_free(d, &(disp_eng->msg_q_sema)); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +rtw_phl_register_module(void *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_bk_module_ops *ops) +{ + return phl_disp_eng_register_module((struct phl_info_t *)phl, + band_idx, id, ops); +} + +enum rtw_phl_status +rtw_phl_deregister_module(void *phl,u8 band_idx, enum phl_module_id id) +{ + return phl_disp_eng_deregister_module((struct phl_info_t *)phl, + band_idx, + id); +} + +u8 rtw_phl_is_fg_empty(void *phl,u8 band_idx) +{ + return phl_disp_eng_is_fg_empty((struct phl_info_t *)phl, band_idx); +} + +enum rtw_phl_status +rtw_phl_send_msg_to_dispr(void *phl, + struct phl_msg *msg, + struct phl_msg_attribute *attr, + u32 *msg_hdl) +{ + return phl_disp_eng_send_msg(phl, msg, attr, msg_hdl); +} + +enum rtw_phl_status +rtw_phl_cancel_dispr_msg(void *phl, u8 band_idx, u32 *msg_hdl) +{ + return phl_disp_eng_cancel_msg(phl, band_idx, msg_hdl); +} + +enum rtw_phl_status +rtw_phl_add_cmd_token_req(void *phl, + u8 band_idx, + struct phl_cmd_token_req *req, + u32 *req_hdl) +{ + return phl_disp_eng_add_token_req(phl, band_idx, req, req_hdl); +} + +enum rtw_phl_status +rtw_phl_cancel_cmd_token(void *phl, u8 band_idx, u32 *req_hdl) +{ + return phl_disp_eng_cancel_token_req(phl, band_idx, req_hdl); +} + +enum rtw_phl_status +rtw_phl_free_cmd_token(void *phl, u8 band_idx, u32 *req_hdl) +{ + return phl_disp_eng_free_token(phl, band_idx, req_hdl); +} + +enum rtw_phl_status +rtw_phl_set_cur_cmd_info(void *phl, + u8 band_idx, + struct phl_module_op_info* op_info) +{ + return phl_disp_eng_set_cur_cmd_info(phl, band_idx, op_info); +} + +enum rtw_phl_status +rtw_phl_query_cur_cmd_info(void *phl, + u8 band_idx, + struct phl_module_op_info* op_info) +{ + return phl_disp_eng_query_cur_cmd_info(phl, band_idx, op_info); +} + +enum rtw_phl_status +rtw_phl_set_bk_module_info(void *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_module_op_info *op_info) +{ + return phl_disp_eng_set_bk_module_info(phl, band_idx, id, op_info); +} + +enum rtw_phl_status +rtw_phl_query_bk_module_info(void *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_module_op_info *op_info) +{ + return phl_disp_eng_query_bk_module_info(phl, band_idx, id, op_info); +} + +enum rtw_phl_status +rtw_phl_set_msg_disp_seq(void *phl, + struct phl_msg_attribute *attr, + struct msg_self_def_seq* seq) +{ + return phl_disp_eng_set_msg_disp_seq(phl, attr, seq); +} + +enum rtw_phl_status +_disp_eng_get_dispr_by_idx(struct phl_info_t *phl, u8 band_idx, void **dispr) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + + if (band_idx > (disp_eng->phy_num - 1) || (dispr == NULL)) { + PHL_WARN("%s invalid input :%d\n", __func__, band_idx); + return RTW_PHL_STATUS_INVALID_PARAM; + } + (*dispr) = disp_eng->dispatcher[band_idx]; + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +phl_disp_eng_register_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_bk_module_ops *ops) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + u8 idx = band_idx; + + if ((band_idx + 1) > disp_eng->phy_num) { + PHL_WARN("%s invalid input :%d\n", __func__, band_idx); + return RTW_PHL_STATUS_INVALID_PARAM; + } + + return dispr_register_module(disp_eng->dispatcher[idx], id, ops); +} + +enum rtw_phl_status +phl_disp_eng_deregister_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + u8 idx = band_idx; + + if ((band_idx + 1) > disp_eng->phy_num) { + PHL_WARN("%s invalid input :%d\n", __func__, band_idx); + return RTW_PHL_STATUS_INVALID_PARAM; + } + + return dispr_deregister_module(disp_eng->dispatcher[idx], id); +} + +void disp_eng_notify_share_thread(struct phl_info_t *phl, void *dispr) +{ + void *d = phl_to_drvpriv(phl); + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + + _os_sema_up(d, &(disp_eng->msg_q_sema)); +} + +u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx) +{ + void* dispr = NULL; + void *handle = NULL; + + if (_disp_eng_get_dispr_by_idx(phl, band_idx, &dispr) != RTW_PHL_STATUS_SUCCESS) + return false; + if (dispr_get_cur_cmd_req(dispr, &handle) == RTW_PHL_STATUS_SUCCESS) + return true; + else + return false; +} + +enum rtw_phl_status +phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl, + u8 band_idx, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_set_cur_cmd_info(dispr, op_info); +} + +enum rtw_phl_status +phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl, + u8 band_idx, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_query_cur_cmd_info(dispr, op_info); +} + +enum rtw_phl_status +phl_disp_eng_set_bk_module_info(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + void* handle = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + status = dispr_get_bk_module_handle(dispr, id, &handle); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_set_bk_module_info(dispr, handle, op_info); +} + +enum rtw_phl_status +phl_disp_eng_query_bk_module_info(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + void* handle = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + status = dispr_get_bk_module_handle(dispr, id, &handle); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_query_bk_module_info(dispr, handle, op_info); +} + +enum rtw_phl_status +phl_disp_eng_set_src_info(struct phl_info_t *phl, + struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_set_src_info(dispr, msg, op_info); +} + +enum rtw_phl_status +phl_disp_eng_query_src_info(struct phl_info_t *phl, + struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_query_src_info(dispr, msg, op_info); +} + +enum rtw_phl_status +phl_disp_eng_send_msg(struct phl_info_t *phl, + struct phl_msg *msg, + struct phl_msg_attribute *attr, + u32 *msg_hdl) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_send_msg(dispr, msg, attr, msg_hdl); +} + +enum rtw_phl_status +phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_cancel_msg(dispr, msg_hdl); +} + +enum rtw_phl_status +phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_clr_pending_msg(dispr); +} + +enum rtw_phl_status +phl_disp_eng_add_token_req(struct phl_info_t *phl, + u8 band_idx, + struct phl_cmd_token_req *req, + u32 *req_hdl) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_add_token_req(dispr, req, req_hdl); +} + +enum rtw_phl_status +phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_cancel_token_req(dispr, req_hdl); +} + +enum rtw_phl_status +phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_free_token(dispr, req_hdl); +} + +enum rtw_phl_status +phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id mdl_id, + bool allow_io) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + u8 i = 0; + + band_idx = HW_BAND_MAX; /* force all band stop IO */ + if (band_idx != HW_BAND_MAX) + return dispr_notify_dev_io_status(disp_eng->dispatcher[band_idx], mdl_id, allow_io); + + for (i = 0; i < disp_eng->phy_num; i++) + dispr_notify_dev_io_status(disp_eng->dispatcher[i], mdl_id, allow_io); + + return RTW_PHL_STATUS_SUCCESS; +} + +void phl_disp_eng_notify_shall_stop(struct phl_info_t *phl) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + u8 i = 0; + + for (i = 0; i < disp_eng->phy_num; i++) { + if (is_dispr_started(disp_eng->dispatcher[i])) + dispr_notify_shall_stop(disp_eng->dispatcher[i]); + } +} + +u8 phl_disp_eng_is_fg_empty(struct phl_info_t *phl, u8 band_idx) +{ + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + u8 i = 0; + + if (band_idx != HW_BAND_MAX) + return dispr_is_fg_empty(disp_eng->dispatcher[band_idx]); + + for (i = 0; i < disp_eng->phy_num; i++) + if (false == dispr_is_fg_empty(disp_eng->dispatcher[i])) + return false; + + return true; +} + +#ifdef CONFIG_CMD_DISP_SOLO_MODE +void dispr_ctrl_sema_down(struct phl_info_t *phl_info) +{ + _os_sema_down(phl_to_drvpriv(phl_info), + &(phl_info->disp_eng.dispr_ctrl_sema)); +} + +void dispr_ctrl_sema_up(struct phl_info_t *phl_info) +{ + _os_sema_up(phl_to_drvpriv(phl_info), + &(phl_info->disp_eng.dispr_ctrl_sema)); +} +#endif + +enum rtw_phl_status +phl_disp_eng_set_msg_disp_seq(struct phl_info_t *phl, + struct phl_msg_attribute *attr, + struct msg_self_def_seq *seq) +{ +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng); + void* dispr = NULL; + + status = _disp_eng_get_dispr_by_idx(phl, HW_BAND_0, &dispr); + if (RTW_PHL_STATUS_SUCCESS != status) + return status; + + return dispr_set_dispatch_seq(dispr, attr, seq); +#else + return RTW_PHL_STATUS_FAILURE; +#endif +} + +u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl) +{ + return disp_query_mdl_id(phl, bk_mdl); +} + +#else +enum rtw_phl_status rtw_phl_set_bk_module_info(void *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status rtw_phl_query_bk_module_info(void *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num) +{ + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status phl_disp_eng_deinit(struct phl_info_t *phl) +{ + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status phl_disp_eng_start(struct phl_info_t *phl) +{ + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status phl_disp_eng_stop(struct phl_info_t *phl) +{ + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status phl_disp_eng_register_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id, + struct phl_bk_module_ops *ops) +{ + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status phl_disp_eng_deregister_module(struct phl_info_t *phl, + u8 band_idx, + enum phl_module_id id) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx) +{ + return RTW_PHL_STATUS_FAILURE; +} + +u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx) +{ + return true; +} +enum rtw_phl_status phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl, u8 band_idx, + struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl, u8 band_idx, + struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_set_bk_module_info(struct phl_info_t *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_query_bk_module_info(struct phl_info_t *phl, u8 band_idx, + enum phl_module_id id, struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_set_src_info(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_query_src_info(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_send_msg(struct phl_info_t *phl, struct phl_msg *msg, + struct phl_msg_attribute *attr, u32 *msg_hdl) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx) +{ + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status phl_disp_eng_add_token_req(struct phl_info_t *phl, u8 band_idx, + struct phl_cmd_token_req *req, u32 *req_hdl) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl) +{ + return RTW_PHL_STATUS_FAILURE; +} +enum rtw_phl_status phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl, u8 band_idx, + enum phl_module_id mdl_id, bool allow_io) +{ + return RTW_PHL_STATUS_FAILURE; +} +} + +void +phl_disp_eng_notify_shall_stop(struct phl_info_t *phl) +{ +} + +enum rtw_phl_status rtw_phl_set_msg_disp_seq(void *phl, + struct phl_msg_attribute *attr, + struct msg_self_def_seq* seq) +{ + return RTW_PHL_STATUS_FAILURE; +} + +u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl) +{ + return PHL_MDL_ID_MAX; +} + +#endif diff --git a/phl/phl_cmd_dispatcher.c b/phl/phl_cmd_dispatcher.c new file mode 100644 index 0000000..a8c1139 --- /dev/null +++ b/phl/phl_cmd_dispatcher.c @@ -0,0 +1,2482 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_DISPR_C_ +#include "phl_headers.h" +#ifdef CONFIG_CMD_DISP + +#define MAX_PHL_MSG_NUM (24) +#define MAX_CMD_REQ_NUM (8) +#define MODL_MASK_LEN (PHL_BK_MDL_END/8) + +#define GEN_VALID_HDL(_idx) ((u32)(BIT31 | (u32)(_idx))) +#define IS_HDL_VALID(_hdl) ((_hdl) & BIT31) +#define GET_IDX_FROM_HDL(_hdl) ((u8)((_hdl) & 0xFF)) + +#define GET_CUR_PENDING_EVT( _obj, _mdl_id) \ + ((u16)((_obj)->mdl_info[(_mdl_id)].pending_evt_id)) +#define SET_CUR_PENDING_EVT( _obj, _mdl_id, _evt_id) \ + ((_obj)->mdl_info[(_mdl_id)].pending_evt_id = (_evt_id)) + +#define IS_EXCL_MDL(_obj, _mdl) ((_obj)->exclusive_mdl == (_mdl)) +#define SET_EXCL_MDL(_obj, _mdl) ((_obj)->exclusive_mdl = (_mdl)) +#define CLEAR_EXCL_MDL(_obj) ((_obj)->exclusive_mdl = PHL_MDL_ID_MAX) +#define STOP_DISPATCH_MSG(_ret) \ + ((_ret) != MDL_RET_SUCCESS && (_ret) != MDL_RET_IGNORE) + +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ +#define SET_MDL_HANDLE( _obj, _mdl_id, _handle) \ + ((_obj)->mdl_info[(_mdl_id)].handle = (void*)(_handle)) +#define GET_MDL_HANDLE( _obj, _mdl_id) \ + ((_obj)->mdl_info[(_mdl_id)].handle) +#endif + +enum phl_msg_status { + MSG_STATUS_ENQ = BIT0, + MSG_STATUS_RUN = BIT1, + MSG_STATUS_NOTIFY_COMPLETE = BIT2, + MSG_STATUS_CANCEL = BIT3, + MSG_STATUS_PRE_PHASE = BIT4, + MSG_STATUS_FAIL = BIT5, + MSG_STATUS_OWNER_BK_MDL = BIT6, + MSG_STATUS_OWNER_REQ = BIT7, + MSG_STATUS_CLR_SNDR_MSG_IF_PENDING = BIT8, + MSG_STATUS_PENDING = BIT9, + MSG_STATUS_FOR_ABORT = BIT10, + MSG_STATUS_PENDING_DURING_CANNOT_IO = BIT11, +}; + +enum cmd_req_status { + REQ_STATUS_ENQ = BIT0, + REQ_STATUS_RUN = BIT1, + REQ_STATUS_CANCEL = BIT2, + REQ_STATUS_LAST_PERMIT = BIT3, + REQ_STATUS_PREPARE = BIT4, +}; + +enum phl_mdl_status { + MDL_INIT = BIT0, + MDL_STARTED = BIT1, +}; + +enum dispatcher_status { + DISPR_INIT = BIT0, + DISPR_STARTED = BIT1, + DISPR_SHALL_STOP = BIT2, + DISPR_MSGQ_INIT = BIT3, + DISPR_REQ_INIT = BIT4, + DISPR_NOTIFY_IDLE = BIT5, + DISPR_CLR_PEND_MSG = BIT6, + DISPR_CTRL_PRESENT = BIT7, + DISPR_WAIT_ABORT_MSG_DONE = BIT8, + DISPR_CANNOT_IO = BIT9, +}; + +enum token_op_type { + TOKEN_OP_ADD_CMD_REQ = 1, + TOKEN_OP_FREE_CMD_REQ = 2, + TOKEN_OP_CANCEL_CMD_REQ = 3, + TOKEN_OP_RENEW_CMD_REQ = 4, +}; + +/** + * phl_bk_module - instance of phl background module, + * @status: contain mgnt status flags, refer to enum phl_mdl_status + * @id: refer to enum phl_module_id + * @priv: private context + * @ops: interface to interacting with phl_module + */ +struct phl_bk_module { + _os_list list; + u8 status; + u8 id; + void *priv; + struct phl_bk_module_ops ops; +}; +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ +struct dispr_msg_attr { + struct msg_self_def_seq self_def_seq; +}; +#endif +/** + * phl_dispr_msg_ex - phl msg extension, + * @status: contain mgnt status flags, refer to enum phl_msg_status + * @idx: idx in original msg_ex pool + * @msg: msg content from external module + * @premap: notifty map in pre-role phase, refer to enum phl_module_id + * @postmap: notifty map in post-role phase, refer to enum phl_module_id + * @completion: msg completion routine. + * @priv: private context to completion routine. + * @module: module handle of msg source, only used when msg fails + */ +struct phl_dispr_msg_ex { + _os_list list; + u16 status; + u8 idx; + struct phl_msg msg; + u8 premap[MODL_MASK_LEN]; + u8 postmap[MODL_MASK_LEN]; + struct msg_completion_routine completion; + struct phl_bk_module *module; /* module handle which assign in msg_id*/ +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + struct dispr_msg_attr *attr; +#endif +}; + +/** + * phl_token_op_info - for internal mgnt purpose, + * @info: mgnt data + */ +struct phl_token_op_info { + _os_list list; + u8 used; + enum token_op_type type; + u8 data; +}; +/** + * phl_cmd_token_req_ex - cmd token request extension, + * @status: contain mgnt status flags, refer to enum cmd_req_status + * @idx: idx in original req_ex pool + * @req: req content from external module. + */ +struct phl_cmd_token_req_ex { + _os_list list; + u8 idx; + u8 status; + struct phl_cmd_token_req req; + struct phl_token_op_info add_req_info; + struct phl_token_op_info free_req_info; +}; + +struct mdl_mgnt_info { + u16 pending_evt_id; +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + void* handle; +#endif +}; + +/** + * cmd_dispatcher, + * @idx: idx in dispatch engine, corresponding to band idx + * @status: contain mgnt status flags, refer to enum dispatcher_status + * @phl_info: for general reference usage. + * @module_q: module queue that link each modules based on priority + * @msg_ex_pool: msg extension pool + * @bk_thread: background thread + * @token_req_ex_pool: req extension pool + * @token_cnt: current token count, + * cmd req can be executed when dispatcher's token count is 0 + * @bitmap: cosist of existing background modules loaded in current dispatcher, + * refer to enum phl_module_id + * @basemap: BK modules that must be notified when handling msg + * @controller: instance of dispr controller module + * @renew_req_info: used to trigger next token req registration + * @exclusive_mdl: In certain conditions, like dev IO status change, + * dispr would only allow designated module to send msg and cancel the rest, + */ +struct cmd_dispatcher { + u8 idx; + u16 status; + struct phl_info_t *phl_info; + struct phl_queue module_q[PHL_MDL_PRI_MAX]; + struct phl_dispr_msg_ex msg_ex_pool[MAX_PHL_MSG_NUM]; + _os_sema msg_q_sema; /* wake up background thread in SOLO_THREAD_MODE*/ + struct phl_queue msg_wait_q; + struct phl_queue msg_idle_q; + struct phl_queue msg_pend_q; + _os_thread bk_thread; + struct phl_cmd_token_req_ex token_req_ex_pool[MAX_CMD_REQ_NUM]; + struct phl_queue token_req_wait_q; + struct phl_queue token_req_idle_q; + struct phl_queue token_op_q; + _os_lock token_op_q_lock; + _os_atomic token_cnt; // atomic + struct phl_cmd_token_req_ex *cur_cmd_req; + u8 bitmap[MODL_MASK_LEN]; + u8 basemap[MODL_MASK_LEN]; + struct mdl_mgnt_info mdl_info[PHL_MDL_ID_MAX]; + struct phl_bk_module controller; + struct phl_token_op_info renew_req_info; + u8 exclusive_mdl; +}; + +enum rtw_phl_status dispr_process_token_req(struct cmd_dispatcher *obj); +void send_bk_msg_phy_on(struct cmd_dispatcher *obj); +void send_bk_msg_phy_idle(struct cmd_dispatcher *obj); +enum rtw_phl_status send_dev_io_status_change(struct cmd_dispatcher *obj, u8 allow_io); +void _notify_dispr_controller(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex); +static u8 dispr_enqueue_token_op_info(struct cmd_dispatcher *obj, struct phl_token_op_info *op_info, + enum token_op_type type, u8 data); + +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ +static void free_dispr_attr(void *d, struct dispr_msg_attr **dispr_attr); +static enum phl_mdl_ret_code run_self_def_seq(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, + enum phl_bk_module_priority priority, u8 pre_prot_phase); +#endif + +inline static +enum phl_bk_module_priority _get_mdl_priority(enum phl_module_id id) +{ + if (id < PHL_BK_MDL_ROLE_START) + return PHL_MDL_PRI_MAX; + else if (id <= PHL_BK_MDL_ROLE_END) + return PHL_MDL_PRI_ROLE; + else if ( id <= PHL_BK_MDL_MDRY_END) + return PHL_MDL_PRI_MANDATORY; + else if (id <= PHL_BK_MDL_OPT_END) + return PHL_MDL_PRI_OPTIONAL; + else + return PHL_MDL_PRI_MAX; +} + +inline static u8 _is_bitmap_empty(void *d, u8 *bitmap) +{ + u8 empty[MODL_MASK_LEN] = {0}; + + return (!_os_mem_cmp(d, bitmap, empty, MODL_MASK_LEN))?(true):(false); +} + +inline static void _print_bitmap(u8 *bitmap) +{ + u8 k = 0; + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "print bitmap: \n"); + + for (k = 0; k < MODL_MASK_LEN; k++) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_,"[%d]:0x%x\n", k, bitmap[k]); + } +} + +static void notify_bk_thread(struct cmd_dispatcher *obj) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + if (disp_eng_is_solo_thread_mode(obj->phl_info)) + _os_sema_up(d, &(obj->msg_q_sema)); + else + disp_eng_notify_share_thread(obj->phl_info, (void*)obj); +} + +static void on_abort_msg_complete(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + /* since struct phl_token_op_info is used to synchronously handle token req in background thread + * here use add_req_info to notify background thread to run dispr_process_token_req again before handling next msg + */ + CLEAR_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE); + dispr_enqueue_token_op_info(obj, &obj->renew_req_info, TOKEN_OP_RENEW_CMD_REQ, 0xff); +} + +static u8 pop_front_idle_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex **msg) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_msg = NULL; + + (*msg) = NULL; + if (pq_pop(d, &(obj->msg_idle_q), &new_msg, _first, _bh)) { + (*msg) = (struct phl_dispr_msg_ex *)new_msg; + (*msg)->status = 0; + (*msg)->module = NULL; + (*msg)->completion.priv = NULL; + (*msg)->completion.completion = NULL; + _os_mem_set(d, (*msg)->premap, 0, MODL_MASK_LEN); + _os_mem_set(d, (*msg)->postmap, 0, MODL_MASK_LEN); + _os_mem_set(d, &((*msg)->msg), 0, sizeof(struct phl_msg)); +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + (*msg)->attr = NULL; +#endif + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_idle_q.cnt); + return true; + } else { + return false; + } +} + +static void push_back_idle_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex *ex) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_NOTIFY_COMPLETE) && + ex->completion.completion) { + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL)) + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANCEL); + ex->completion.completion(ex->completion.priv, &(ex->msg)); + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_NOTIFY_COMPLETE); + } + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FOR_ABORT)) + on_abort_msg_complete(obj, ex); + ex->status = 0; + if(GET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id)) == MSG_EVT_ID_FIELD(ex->msg.msg_id)) + SET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id), MSG_EVT_MAX); + ex->msg.msg_id = 0; +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + free_dispr_attr(d, &(ex->attr)); +#endif + pq_push(d, &(obj->msg_idle_q), &(ex->list), _tail, _bh); +} + +static u8 pop_front_wait_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex **msg) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_msg = NULL; + + (*msg) = NULL; + if (pq_pop(d, &(obj->msg_wait_q), &new_msg, _first, _bh)) { + (*msg) = (struct phl_dispr_msg_ex *)new_msg; + SET_STATUS_FLAG((*msg)->status, MSG_STATUS_RUN); + CLEAR_STATUS_FLAG((*msg)->status, MSG_STATUS_ENQ); + CLEAR_STATUS_FLAG((*msg)->status, MSG_STATUS_PENDING); + return true; + } else { + return false; + } +} + +static void push_back_wait_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex *ex) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ); + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN); + pq_push(d, &(obj->msg_wait_q), &(ex->list), _tail, _bh); + notify_bk_thread(obj); +} + + u8 is_higher_priority(void *d, void *priv,_os_list *input, _os_list *obj) + { + struct phl_dispr_msg_ex *ex_input = (struct phl_dispr_msg_ex *)input; + struct phl_dispr_msg_ex *ex_obj = (struct phl_dispr_msg_ex *)obj; + + if (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex_input->msg.msg_id)) && + !IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex_obj->msg.msg_id))) + return true; + return false; + } + +static void insert_msg_by_priority(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex *ex) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ); + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN); + pq_insert(d, &(obj->msg_wait_q), _bh, NULL, &(ex->list), is_higher_priority); + notify_bk_thread(obj); +} + +static u8 pop_front_pending_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex **msg) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_msg = NULL; + + (*msg) = NULL; + if (pq_pop(d, &(obj->msg_pend_q), &new_msg, _first, _bh)) { + (*msg) = (struct phl_dispr_msg_ex *)new_msg; + return true; + } else { + return false; + } +} + +static void push_back_pending_msg(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex *ex) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ); + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN); + + if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_CLR_SNDR_MSG_IF_PENDING)) + SET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id), MSG_EVT_ID_FIELD(ex->msg.msg_id)); + pq_push(d, &(obj->msg_pend_q), &(ex->list), _tail, _bh); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_pend_q.cnt); +} + +static void clear_pending_msg(struct cmd_dispatcher *obj) +{ + struct phl_dispr_msg_ex *ex = NULL; + + if(!TEST_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG)) + return; + CLEAR_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG); + while (pop_front_pending_msg(obj, &ex)) { + if (IS_DISPR_CTRL(MSG_EVT_ID_FIELD(ex->msg.msg_id))) + insert_msg_by_priority(obj, ex); + else + push_back_wait_msg(obj, ex); + } +} + +static void clear_waiting_msg(struct cmd_dispatcher *obj) +{ + struct phl_dispr_msg_ex *ex = NULL; + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_idle_q.cnt); + while(obj->msg_idle_q.cnt != MAX_PHL_MSG_NUM) { + while (pop_front_pending_msg(obj, &ex)) + push_back_wait_msg(obj, ex); + while (pop_front_wait_msg(obj, &ex)) + push_back_idle_msg(obj, ex); + } +} + +static bool is_special_msg(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + u8 mdl_id = MSG_MDL_ID_FIELD(ex->msg.msg_id); + u16 evt = MSG_EVT_ID_FIELD(ex->msg.msg_id); + + if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) { + if ( IS_EXCL_MDL(obj, mdl_id) || + evt == MSG_EVT_DEV_CANNOT_IO || + evt == MSG_EVT_DEV_RESUME_IO || + evt == MSG_EVT_PHY_ON || + evt == MSG_EVT_PHY_IDLE) + return true; + } + return false; +} + +static bool is_msg_canceled(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + u16 pending_evt = GET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id)); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || + TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL)) + return true; + + if (pending_evt != MSG_EVT_MAX && pending_evt != MSG_EVT_ID_FIELD(ex->msg.msg_id)) { + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled, cur pending evt(%d)\n", pending_evt); + return true; + } + + if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled due to SHALL STOP status\n"); + + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO); + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); + return true; + } + + if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) { + if( is_special_msg(obj, ex)) { + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "special msg found, still sent with CANNOT IO flag set\n"); + } + else if (!TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING_DURING_CANNOT_IO)) { + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled due to CANNOT IO status\n"); + return true; + } else { + SET_STATUS_FLAG(ex->status, MSG_STATUS_PENDING); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg pending due to CANNOT IO status\n"); + } + } + + return false; +} + +void init_dispr_msg_pool(struct cmd_dispatcher *obj) +{ + u8 i = 0; + void *d = phl_to_drvpriv(obj->phl_info); + + if (TEST_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT)) + return; + pq_init(d, &(obj->msg_idle_q)); + pq_init(d, &(obj->msg_wait_q)); + pq_init(d, &(obj->msg_pend_q)); + _os_mem_set(d, obj->msg_ex_pool, 0, + sizeof(struct phl_dispr_msg_ex) * MAX_PHL_MSG_NUM); + for (i = 0; i < MAX_PHL_MSG_NUM; i++) { + obj->msg_ex_pool[i].idx = i; + push_back_idle_msg(obj, &(obj->msg_ex_pool[i])); + } + + SET_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT); +} + +void deinit_dispr_msg_pool(struct cmd_dispatcher *obj) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT)) + return; + CLEAR_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT); + + pq_deinit(d, &(obj->msg_idle_q)); + pq_deinit(d, &(obj->msg_wait_q)); + pq_deinit(d, &(obj->msg_pend_q)); +} + +void cancel_msg(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + /* zero bitmap to ensure msg would not be forward to + * any modules after cancel. + * */ + _reset_bitmap(d, ex->premap, MODL_MASK_LEN); + _reset_bitmap(d, ex->postmap, MODL_MASK_LEN); + + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); +} + +void cancel_running_msg(struct cmd_dispatcher *obj) +{ + u8 i = 0; + + for (i = 0; i < MAX_PHL_MSG_NUM;i++) { + if(TEST_STATUS_FLAG(obj->msg_ex_pool[i].status, MSG_STATUS_RUN)) + cancel_msg(obj, &(obj->msg_ex_pool[i])); + } +} +void set_msg_bitmap(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, u8 mdl_id) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + /* ensure mandatory & wifi role module recv all msg*/ + _os_mem_cpy(d, ex->premap, obj->bitmap, MODL_MASK_LEN); + _os_mem_cpy(d, ex->postmap, obj->bitmap, MODL_MASK_LEN); + if(_chk_bitmap_bit(obj->bitmap, mdl_id)) { + _add_bitmap_bit(ex->premap, &mdl_id, 1); + _add_bitmap_bit(ex->postmap, &mdl_id, 1); + } +//_print_bitmap(ex->premap); +} + +void set_msg_custom_bitmap(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, + enum phl_msg_opt opt, u8 *id_arr, u32 len, u8 mdl_id) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + if (opt & MSG_OPT_SKIP_NOTIFY_OPT_MDL) { + _os_mem_cpy(d, ex->premap, obj->basemap, MODL_MASK_LEN); + _os_mem_cpy(d, ex->postmap, obj->basemap, MODL_MASK_LEN); + } + if (opt & MSG_OPT_BLIST_PRESENT) { + _clr_bitmap_bit(ex->premap, id_arr, len); + _clr_bitmap_bit(ex->postmap, id_arr, len); + } else { + _add_bitmap_bit(ex->premap, id_arr, len); + _add_bitmap_bit(ex->postmap, id_arr, len); + } + if(_chk_bitmap_bit(obj->bitmap, mdl_id)) { + _add_bitmap_bit(ex->premap, &mdl_id, 1); + _add_bitmap_bit(ex->postmap, &mdl_id, 1); + } +} + +u8 *get_msg_bitmap(struct phl_dispr_msg_ex *ex) +{ + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_PRE_PHASE)) { + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_PRE_PHASE); + return ex->premap; + } else { + CLEAR_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_PRE_PHASE); + return ex->postmap; + } +} + + +void init_dispr_mdl_mgnt_info(struct cmd_dispatcher *obj) +{ + u8 i = 0; + + for (i = 0; i < PHL_MDL_ID_MAX; i++) + SET_CUR_PENDING_EVT(obj, i, MSG_EVT_MAX); + +} + +static u8 pop_front_idle_req(struct cmd_dispatcher *obj, + struct phl_cmd_token_req_ex **req) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_req = NULL; + + (*req) = NULL; + if (pq_pop(d, &(obj->token_req_idle_q), &new_req, _first, _bh)) { + (*req) = (struct phl_cmd_token_req_ex*)new_req; + (*req)->status = 0; + _os_mem_set(d, &((*req)->req), 0, + sizeof(struct phl_cmd_token_req)); + _os_mem_set(d, &((*req)->add_req_info), 0, + sizeof(struct phl_token_op_info)); + _os_mem_set(d, &((*req)->free_req_info), 0, + sizeof(struct phl_token_op_info)); + return true; + } else { + return false; + } +} + +static void push_back_idle_req(struct cmd_dispatcher *obj, + struct phl_cmd_token_req_ex *req) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + req->status = 0; + SET_CUR_PENDING_EVT(obj, req->req.module_id, MSG_EVT_MAX); + pq_push(d, &(obj->token_req_idle_q), &(req->list), _tail, _bh); +} + +static u8 pop_front_wait_req(struct cmd_dispatcher *obj, + struct phl_cmd_token_req_ex **req) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_req = NULL; + + (*req) = NULL; + if (pq_pop(d, &(obj->token_req_wait_q), &new_req, _first, _bh)) { + (*req) = (struct phl_cmd_token_req_ex*)new_req; + SET_STATUS_FLAG((*req)->status, REQ_STATUS_PREPARE); + CLEAR_STATUS_FLAG((*req)->status, REQ_STATUS_ENQ); + return true; + } else { + return false; + } +} + +static void push_back_wait_req(struct cmd_dispatcher *obj, + struct phl_cmd_token_req_ex *req) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + pq_push(d, &(obj->token_req_wait_q), &(req->list), _tail, _bh); + SET_STATUS_FLAG(req->status, REQ_STATUS_ENQ); +} + +static void clear_wating_req(struct cmd_dispatcher *obj) +{ + struct phl_cmd_token_req_ex *ex = NULL; + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s: remain cnt(%d)\n", __FUNCTION__, obj->token_req_idle_q.cnt); + while(obj->token_req_idle_q.cnt != MAX_CMD_REQ_NUM) { + while (pop_front_wait_req(obj, &ex)) { + ex->req.abort(obj, ex->req.priv); + push_back_idle_req(obj, ex); + } + } +} + +void deregister_cur_cmd_req(struct cmd_dispatcher *obj, u8 notify) +{ + struct phl_cmd_token_req *req = NULL; + void *d = phl_to_drvpriv(obj->phl_info); + u8 i = 0; + struct phl_dispr_msg_ex *ex = NULL; + + if (obj->cur_cmd_req) { + req = &(obj->cur_cmd_req->req); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id(%d), status(%d)\n", + __FUNCTION__, req->module_id, obj->cur_cmd_req->status); + CLEAR_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_RUN); + for (i = 0; i < MAX_PHL_MSG_NUM; i++) { + ex = &(obj->msg_ex_pool[i]); + if (req->module_id != MSG_MDL_ID_FIELD(ex->msg.msg_id)) + continue; + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_REQ); + cancel_msg(obj, ex); + if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING)) { + dispr_clr_pending_msg((void*)obj); + /* inserted pending msg from this sepecific sender back to wait Q before abort notify + * would guarantee msg sent in abort notify is exactly last msg from this sender + * */ + clear_pending_msg(obj); + } + } + if (notify == true) { + SET_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_LAST_PERMIT); + req->abort(obj, req->priv); + CLEAR_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_LAST_PERMIT); + } +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + SET_MDL_HANDLE(obj, obj->cur_cmd_req->req.module_id, NULL); +#endif + push_back_idle_req(obj, obj->cur_cmd_req); + _os_atomic_set(d, &(obj->token_cnt), + _os_atomic_read(d, &(obj->token_cnt))-1); + } + obj->cur_cmd_req = NULL; + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); +} + +u8 register_cur_cmd_req(struct cmd_dispatcher *obj, + struct phl_cmd_token_req_ex *req) +{ + void *d = phl_to_drvpriv(obj->phl_info); + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + + SET_STATUS_FLAG(req->status, REQ_STATUS_RUN); + CLEAR_STATUS_FLAG(req->status, REQ_STATUS_PREPARE); + obj->cur_cmd_req = req; + _os_atomic_set(d, &(obj->token_cnt), + _os_atomic_read(d, &(obj->token_cnt))+1); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id(%d)\n", __FUNCTION__, obj->cur_cmd_req->req.module_id); + ret = obj->cur_cmd_req->req.acquired((void*)obj, obj->cur_cmd_req->req.priv); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, ret(%d)\n", __FUNCTION__, ret); + + if (ret == MDL_RET_FAIL) { + deregister_cur_cmd_req(obj, false); + return false; + } + else { +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + SET_MDL_HANDLE(obj, req->req.module_id, req); +#endif + return true; + } +} + +void cancel_all_cmd_req(struct cmd_dispatcher *obj) +{ + u8 i = 0; + struct phl_cmd_token_req_ex* req_ex = NULL; + + for (i = 0; i < MAX_CMD_REQ_NUM;i++) { + req_ex = &(obj->token_req_ex_pool[i]); + if (req_ex->status) + SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL); + } +} + +void init_cmd_req_pool(struct cmd_dispatcher *obj) +{ + u8 i = 0; + void *d = phl_to_drvpriv(obj->phl_info); + + if (TEST_STATUS_FLAG(obj->status, DISPR_REQ_INIT)) + return; + pq_init(d, &(obj->token_req_wait_q)); + pq_init(d, &(obj->token_req_idle_q)); + pq_init(d, &(obj->token_op_q)); + _os_mem_set(d, obj->token_req_ex_pool, 0, + sizeof(struct phl_cmd_token_req_ex) * MAX_CMD_REQ_NUM); + for (i = 0; i < MAX_CMD_REQ_NUM;i++) { + obj->token_req_ex_pool[i].idx = i; + pq_push(d, &(obj->token_req_idle_q), + &(obj->token_req_ex_pool[i].list), _tail, _bh); + } + SET_STATUS_FLAG(obj->status, DISPR_REQ_INIT); +} + +void deinit_cmd_req_pool(struct cmd_dispatcher *obj) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + CLEAR_STATUS_FLAG(obj->status, DISPR_REQ_INIT); + + pq_deinit(d, &(obj->token_req_wait_q)); + pq_deinit(d, &(obj->token_req_idle_q)); + pq_deinit(d, &(obj->token_op_q)); +} + +u8 chk_module_ops(struct phl_bk_module_ops *ops) +{ + if (ops == NULL || + ops->init == NULL || + ops->deinit == NULL || + ops->msg_hdlr == NULL || + ops->set_info == NULL || + ops->query_info == NULL || + ops->start == NULL || + ops->stop == NULL) + return false; + return true; +} + +u8 chk_cmd_req_ops(struct phl_cmd_token_req *req) +{ + if (req == NULL || + req->module_id < PHL_FG_MDL_START || + req->abort == NULL || + req->acquired == NULL || + req->msg_hdlr == NULL || + req->set_info == NULL || + req->query_info == NULL) + return false; + return true; +} +static u8 pop_front_token_op_info(struct cmd_dispatcher *obj, + struct phl_token_op_info **op_info) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *new_info = NULL; + + (*op_info) = NULL; + if (pq_pop(d, &(obj->token_op_q), &new_info, _first, _bh)) { + (*op_info) = (struct phl_token_op_info *)new_info; + return true; + } else { + return false; + } +} + +static u8 push_back_token_op_info(struct cmd_dispatcher *obj, + struct phl_token_op_info *op_info, + enum token_op_type type, + u8 data) +{ + void *d = phl_to_drvpriv(obj->phl_info); + _os_spinlockfg sp_flags; + + _os_spinlock(d, &obj->token_op_q_lock, _bh, &sp_flags); + if (op_info->used == true) { + _os_spinunlock(d, &obj->token_op_q_lock, _bh, &sp_flags); + return false; + } + op_info->used = true; + op_info->type = type; + op_info->data = data; + _os_spinunlock(d, &obj->token_op_q_lock, _bh, &sp_flags); + pq_push(d, &(obj->token_op_q), &(op_info->list), _tail, _bh); + notify_bk_thread(obj); + return true; +} + +void _handle_token_op_info(struct cmd_dispatcher *obj, struct phl_token_op_info *op_info) +{ + struct phl_cmd_token_req_ex *req_ex = NULL; + void *d = phl_to_drvpriv(obj->phl_info); + + switch (op_info->type) { + case TOKEN_OP_RENEW_CMD_REQ: + /* fall through*/ + case TOKEN_OP_ADD_CMD_REQ: + dispr_process_token_req(obj); + break; + case TOKEN_OP_FREE_CMD_REQ: + if (op_info->data >= MAX_CMD_REQ_NUM) + return; + req_ex = &(obj->token_req_ex_pool[op_info->data]); + if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN)) + break; + deregister_cur_cmd_req(obj, false); + dispr_process_token_req(obj); + break; + case TOKEN_OP_CANCEL_CMD_REQ: + if (op_info->data >= MAX_CMD_REQ_NUM) + return; + req_ex = &(obj->token_req_ex_pool[op_info->data]); + if (TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_ENQ)) { + pq_del_node(d, &(obj->token_req_wait_q), &(req_ex->list), _bh); + /* + * Call command abort handle, abort handle + * should decide it has been acquired or not. + */ + req_ex->req.abort(obj, req_ex->req.priv); + push_back_idle_req(obj, req_ex); + } else if (TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN)){ + deregister_cur_cmd_req(obj, true); + dispr_process_token_req(obj); + } + break; + default: + break; + } +} + +void token_op_hanler(struct cmd_dispatcher *obj) +{ + struct phl_token_op_info *info = NULL; + + while (pop_front_token_op_info(obj, &info)) { + _handle_token_op_info(obj, info); + info->used = false; + } +} +static u8 +dispr_enqueue_token_op_info(struct cmd_dispatcher *obj, + struct phl_token_op_info *op_info, + enum token_op_type type, + u8 data) +{ + return push_back_token_op_info(obj, op_info, type, data); +} + +u8 bk_module_init(struct cmd_dispatcher *obj, struct phl_bk_module *module) +{ + if (TEST_STATUS_FLAG(module->status, MDL_INIT)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s module_id:%d already init\n", + __FUNCTION__, module->id); + return false; + } + + if (module->ops.init((void*)obj->phl_info, (void*)obj, + &(module->priv)) == MDL_RET_SUCCESS) { + SET_STATUS_FLAG(module->status, MDL_INIT); + return true; + } else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s fail module_id: %d \n", __FUNCTION__, module->id); + return false; + } +} + +void bk_module_deinit(struct cmd_dispatcher *obj, struct phl_bk_module *module) +{ + if (TEST_STATUS_FLAG(module->status, MDL_INIT)) + module->ops.deinit((void*)obj, module->priv); + CLEAR_STATUS_FLAG(module->status, MDL_INIT); +} + +u8 bk_module_start(struct cmd_dispatcher *obj, struct phl_bk_module *module) +{ + if (!TEST_STATUS_FLAG(module->status, MDL_INIT) || + TEST_STATUS_FLAG(module->status, MDL_STARTED)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s module_id:%d already start\n", __FUNCTION__, + module->id); + return false; + } + + if (module->ops.start((void*)obj, module->priv) == MDL_RET_SUCCESS) { + SET_STATUS_FLAG(module->status, MDL_STARTED); +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + SET_MDL_HANDLE(obj, module->id, module); +#endif + return true; + } else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s fail module_id: %d \n", __FUNCTION__, module->id); + return false; + } +} + +u8 bk_module_stop(struct cmd_dispatcher *obj, struct phl_bk_module *module) +{ + if (!TEST_STATUS_FLAG(module->status, MDL_STARTED)) + return false; + CLEAR_STATUS_FLAG(module->status, MDL_STARTED); +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + SET_MDL_HANDLE(obj, module->id, NULL); +#endif + if (module->ops.stop((void*)obj, module->priv) == MDL_RET_SUCCESS) { + return true; + } else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s fail module_id: %d \n", __FUNCTION__, + module->id); + return false; + } +} + +void cur_req_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req; + + if (cur_req == NULL) + return; + if (!TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) || + TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL)) + return; + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FOR_ABORT)) + return; + cur_req->req.msg_hdlr((void*)obj, cur_req->req.priv, &(ex->msg)); +} + +void notify_msg_fail(struct cmd_dispatcher *obj, + struct phl_dispr_msg_ex *ex, + enum phl_mdl_ret_code ret) +{ + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + + SET_STATUS_FLAG(ex->status, MSG_STATUS_FAIL); + + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_FAIL); + if (ret == MDL_RET_CANNOT_IO) + SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO); + + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL) && + (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex->msg.msg_id)) || _chk_bitmap_bit(obj->bitmap, ex->module->id))) { + ex->module->ops.msg_hdlr(obj, ex->module->priv, &(ex->msg)); + } + + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_REQ)) { + cur_req_hdl(obj, ex); + } +} + +enum phl_mdl_ret_code feed_mdl_msg(struct cmd_dispatcher *obj, + struct phl_bk_module *mdl, + struct phl_dispr_msg_ex *ex) +{ + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u8 *bitmap = NULL; + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, "%s, id:%d \n", __FUNCTION__, mdl->id); + ret = mdl->ops.msg_hdlr(obj, mdl->priv, &(ex->msg)); + if (ret == MDL_RET_FAIL || ret == MDL_RET_CANNOT_IO) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "id:%d evt:0x%x fail\n", + mdl->id, ex->msg.msg_id); + ex->msg.rsvd[0] = mdl; + notify_msg_fail(obj, ex, ret); + } else if (ret == MDL_RET_PENDING) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "id:%d evt:0x%x pending\n", + mdl->id, ex->msg.msg_id); + SET_STATUS_FLAG(ex->status, MSG_STATUS_PENDING); + } else { + if (MSG_INDC_FIELD(ex->msg.msg_id) & MSG_INDC_PRE_PHASE) + bitmap = ex->premap; + else + bitmap = ex->postmap; + _clr_bitmap_bit(bitmap, &(mdl->id), 1); + } + return ret; +} + +void msg_pre_phase_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + s8 i = 0; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_bk_module *mdl = NULL; + _os_list *node = NULL; + struct phl_queue *q = NULL; + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u8 owner_id = (ex->module)?(ex->module->id):(PHL_MDL_ID_MAX); + enum phl_bk_module_priority priority = PHL_MDL_PRI_MAX; + + if (owner_id <= PHL_BK_MDL_END) + priority = _get_mdl_priority(owner_id); + + for (i = PHL_MDL_PRI_MAX - 1 ; i >= PHL_MDL_PRI_ROLE ; i--) { +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + ret = run_self_def_seq(obj, ex, i, true); + if (STOP_DISPATCH_MSG(ret)) + return; +#endif + if (priority == i && _chk_bitmap_bit(ex->premap, owner_id)) { + ret = feed_mdl_msg(obj, ex->module, ex); + if (STOP_DISPATCH_MSG(ret)) + return; + } + q = &(obj->module_q[(u8)i]); + + if (pq_get_front(d, q, &node, _bh) == false) + continue; + + do { + mdl = (struct phl_bk_module*)node; + if (!_chk_bitmap_bit(ex->premap, mdl->id) || + !TEST_STATUS_FLAG(mdl->status, MDL_STARTED)) + continue; + ret = feed_mdl_msg(obj, mdl, ex); + if (STOP_DISPATCH_MSG(ret)) + return; + } while(pq_get_next(d, q, node, &node, _bh)); + } +} + +void msg_post_phase_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + s8 i = 0; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_bk_module *mdl = NULL; + _os_list *node = NULL; + struct phl_queue *q = NULL; + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u8 owner_id = (ex->module)?(ex->module->id):(PHL_MDL_ID_MAX); + enum phl_bk_module_priority priority = PHL_MDL_PRI_MAX; + + if (owner_id <= PHL_BK_MDL_END) + priority = _get_mdl_priority(owner_id); + + for (i = PHL_MDL_PRI_ROLE ; i < PHL_MDL_PRI_MAX ; i++) { +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + ret = run_self_def_seq(obj, ex, i, false); + if (STOP_DISPATCH_MSG(ret)) + return; +#endif + if (priority == i && _chk_bitmap_bit(ex->postmap, owner_id)) { + ret = feed_mdl_msg(obj, ex->module, ex); + if (STOP_DISPATCH_MSG(ret)) + return; + } + q = &(obj->module_q[(u8)i]); + if (pq_get_tail(d, q, &node, _bh) == false) + continue; + do { + mdl = (struct phl_bk_module*)node; + if (!_chk_bitmap_bit(ex->postmap, mdl->id)|| + !TEST_STATUS_FLAG(mdl->status, MDL_STARTED)) + continue; + ret = feed_mdl_msg(obj, mdl, ex); + if (STOP_DISPATCH_MSG(ret)) + return; + } while(pq_get_prev(d, q, node, &node, _bh)); + } +} + +u8 get_cur_cmd_req_id(struct cmd_dispatcher *obj, u32 *req_status) +{ + struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req; + + if(req_status) + *req_status = 0; + + if (cur_req == NULL ) + return (u8)PHL_MDL_ID_MAX; + + if(req_status) + *req_status = cur_req->status; + + if(!TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) || + TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL)) + return (u8)PHL_MDL_ID_MAX; + else + return cur_req->req.module_id; +} + +#define MSG_REDIRECT_CHK(_ex) \ + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FAIL)|| \ + TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL)) \ + goto recycle;\ + if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING)) \ + goto reschedule; + +void msg_dispatch(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + u8 *bitmap = get_msg_bitmap(ex); + void *d = phl_to_drvpriv(obj->phl_info); + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, + "%s, msg_id:0x%x status: 0x%x\n", __FUNCTION__, ex->msg.msg_id, ex->status); + MSG_REDIRECT_CHK(ex); + + _notify_dispr_controller(obj, ex); + + MSG_REDIRECT_CHK(ex); + + if ((MSG_INDC_FIELD(ex->msg.msg_id) & MSG_INDC_PRE_PHASE) && + _is_bitmap_empty(d, bitmap) == false) + msg_pre_phase_hdl(obj, ex); + + MSG_REDIRECT_CHK(ex); + + if (_is_bitmap_empty(d, bitmap)) { + /* pre protocol phase done, switch to post protocol phase*/ + CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_PRE_PHASE); + bitmap = get_msg_bitmap(ex); + } else { + PHL_ERR("%s, invalid bitmap state, msg status:0x%x \n", __FUNCTION__, ex->status); + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); + goto recycle; + } + + if (_is_bitmap_empty(d, bitmap) == false) + msg_post_phase_hdl(obj, ex); + + MSG_REDIRECT_CHK(ex); + + if (_is_bitmap_empty(d, bitmap)) { + /* post protocol phase done */ + cur_req_hdl(obj, ex); + goto recycle; + } else { + PHL_ERR("%s, invalid bitmap state, msg status:0x%x \n", __FUNCTION__, ex->status); + SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL); + goto recycle; + } +reschedule: + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, msg:0x%x reschedule \n", __FUNCTION__, + ex->msg.msg_id); + if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING)) + push_back_pending_msg(obj, ex); + else + push_back_wait_msg(obj, ex); + return; +recycle: + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, + "%s, msg:0x%x recycle \n", __FUNCTION__, + ex->msg.msg_id); + push_back_idle_msg(obj, ex); +} + +void dispr_thread_loop_hdl(struct cmd_dispatcher *obj) +{ + struct phl_dispr_msg_ex *ex = NULL; + + /* check pending msg need in advance. + * if pending msg is not empty before while loop breaks, + * these msg would be cleared in deinit_dispr_msg_pool. + */ + clear_pending_msg(obj); + /* token op Q in advance. + * if req wait Q is not empty before while loop breaks, + * these msg would be cleared in deinit_cmd_req_pool. + */ + token_op_hanler(obj); + + if (pop_front_wait_msg(obj, &ex)) { + if (is_msg_canceled(obj, ex)) { + push_back_idle_msg(obj, ex); + return; + } + /* ensure all modules set in msg bitmap + exists in cur dispatcher*/ + _and_bitmaps(obj->bitmap, ex->premap, MODL_MASK_LEN); + _and_bitmaps(obj->bitmap, ex->postmap, MODL_MASK_LEN); + msg_dispatch(obj, ex); + } +} + +void dispr_thread_leave_hdl(struct cmd_dispatcher *obj) +{ + deregister_cur_cmd_req(obj, true); + /* clear remaining pending & waiting msg */ + clear_waiting_msg(obj); + /* pop out all waiting cmd req and notify abort. */ + clear_wating_req(obj); +} + +int background_thread_hdl(void *param) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)param; + void *d = phl_to_drvpriv(obj->phl_info); + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s enter\n", __FUNCTION__); + while (!_os_thread_check_stop(d, &(obj->bk_thread))) { + + _os_sema_down(d, &obj->msg_q_sema); + + if(_os_thread_check_stop(d, &(obj->bk_thread))) + break; + dispr_thread_loop_hdl(obj); + } + dispr_thread_leave_hdl(obj); + _os_thread_wait_stop(d, &(obj->bk_thread)); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s down\n", __FUNCTION__); + return 0; +} + +u8 search_mdl(void *d, void *mdl, void *priv) +{ + enum phl_module_id id = *(enum phl_module_id *)priv; + struct phl_bk_module *module = NULL; + + module = (struct phl_bk_module *)mdl; + if (module->id == id) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s :: id %d\n", __FUNCTION__, id); + return true; + } + else + return false; +} + +u8 get_module_by_id(struct cmd_dispatcher *obj, enum phl_module_id id, + struct phl_bk_module **mdl) +{ + void *d = phl_to_drvpriv(obj->phl_info); + u8 i = 0; + _os_list *node = NULL; + + if (mdl == NULL) + return false; + + if (IS_DISPR_CTRL(id)) { + if (!TEST_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT)) + return false; + *mdl = &(obj->controller); + return true; + } + + if (!_chk_bitmap_bit(obj->bitmap, id)) + return false; + + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + + if(pq_search_node(d, &(obj->module_q[i]), &node, _bh, false, &id, search_mdl)) { + *mdl = (struct phl_bk_module*)node; + return true; + } + } + *mdl = NULL; + return false; +} + +enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + + if (dispr == NULL) + return RTW_PHL_STATUS_FAILURE; + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || idx == NULL) + return RTW_PHL_STATUS_FAILURE; + *idx = obj->idx; + return RTW_PHL_STATUS_SUCCESS; +} + +/* Each dispr has a controller. + * A dispr controller is designed for phl instance to interact with dispr modules that are belonged to a specific hw band, + * phl instance can perform follwing actions via dedicated controller: + * 1. allow (phl status/non-dispr phl modules) to monitor & drop msg + * 2. allow dispr modules, that are belonged to same dispr, to sequentially communicate with phl instance & call phl api, + * and also allow (phl status/non-dispr phl modules) to notify dispr by hw band. + * *Note* + * 1. when cmd dispatch engine is in solo thread mode (each dispr has its own dedicated thread). + * phl instance might receive msg from different dispr simutaneously and + * currently using semaphore (dispr_ctrl_sema) to prevent multi-thread condition. + * 2. when cmd dispatch engine is in share thread mode, msg from different dispr would pass to controller sequentially. + + * PS: + * phl instance: means phl_info_t, which include phl mgnt status & non-dispr phl modules + * dispr modules: all existing background & foreground modules. + * non-dispr phl module : Data path (TX/Rx), etc + * phl mgnt status : stop/surprise remove/cannot io +*/ +static enum rtw_phl_status _register_dispr_controller(struct cmd_dispatcher *obj) +{ + struct phl_bk_module *ctrl = &(obj->controller); + + dispr_ctrl_hook_ops(obj, &(ctrl->ops)); + ctrl->id = PHL_MDL_PHY_MGNT; + + if(bk_module_init(obj, &(obj->controller)) == true) + return RTW_PHL_STATUS_SUCCESS; + else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__); + return RTW_PHL_STATUS_FAILURE; + } +} + +static void _deregister_dispr_controller(struct cmd_dispatcher *obj) +{ + bk_module_deinit(obj, &(obj->controller)); +} + +static enum rtw_phl_status _start_dispr_controller(struct cmd_dispatcher *obj) +{ + if (bk_module_start(obj, &(obj->controller)) == true) { + SET_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT); + return RTW_PHL_STATUS_SUCCESS; + } + else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__); + return RTW_PHL_STATUS_FAILURE; + } +} + +static enum rtw_phl_status _stop_dispr_controller(struct cmd_dispatcher *obj) +{ + CLEAR_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT); + if (bk_module_stop(obj, &(obj->controller)) == true) + return RTW_PHL_STATUS_SUCCESS; + else { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__); + return RTW_PHL_STATUS_FAILURE; + } +} + +void _notify_dispr_controller(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex) +{ + if (!TEST_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT)) + return; +#ifdef CONFIG_CMD_DISP_SOLO_MODE + dispr_ctrl_sema_down(obj->phl_info); +#endif + feed_mdl_msg(obj, &(obj->controller), ex); +#ifdef CONFIG_CMD_DISP_SOLO_MODE + dispr_ctrl_sema_up(obj->phl_info); +#endif + +} + +void dispr_thread_stop_prior_hdl(struct cmd_dispatcher *obj) +{ + CLEAR_STATUS_FLAG(obj->status, DISPR_STARTED); + _stop_dispr_controller(obj); + cancel_all_cmd_req(obj); + cancel_running_msg(obj); +} + +void dispr_thread_stop_post_hdl(struct cmd_dispatcher *obj) +{ + void *d = phl_to_drvpriv(obj->phl_info); + + /* have to wait for bk thread ends before deinit msg & req*/ + deinit_dispr_msg_pool(obj); + deinit_cmd_req_pool(obj); + _os_atomic_set(d, &(obj->token_cnt), 0); + _os_sema_free(d, &(obj->msg_q_sema)); +} + +enum rtw_phl_status dispr_init(struct phl_info_t *phl_info, void **dispr, u8 idx) +{ + struct cmd_dispatcher *obj = NULL; + void *d = phl_to_drvpriv(phl_info); + u8 i = 0; + + (*dispr) = NULL; + + obj = (struct cmd_dispatcher *)_os_mem_alloc(d, sizeof(struct cmd_dispatcher)); + if (obj == NULL) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, alloc fail\n", __FUNCTION__); + return RTW_PHL_STATUS_RESOURCE; + } + + obj->phl_info = phl_info; + obj->idx = idx; + _os_atomic_set(d, &(obj->token_cnt), 0); + for (i = 0 ; i < PHL_MDL_PRI_MAX; i++) + pq_init(d, &(obj->module_q[i])); + + (*dispr) = (void*)obj; + _os_spinlock_init(d, &(obj->token_op_q_lock)); + SET_STATUS_FLAG(obj->status, DISPR_INIT); + SET_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE); + _register_dispr_controller(obj); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, size dispr(%d), msg_ex(%d), req_ex(%d) \n", + __FUNCTION__, (int)sizeof(struct cmd_dispatcher), + (int)sizeof(struct phl_dispr_msg_ex), + (int)sizeof(struct phl_cmd_token_req_ex)); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_deinit(struct phl_info_t *phl, void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + u8 i = 0; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT)) + return RTW_PHL_STATUS_SUCCESS; + dispr_stop(dispr); + _deregister_dispr_controller(obj); + for (i = 0 ; i < PHL_MDL_PRI_MAX; i++) + pq_deinit(d, &(obj->module_q[i])); + _os_spinlock_free(d, &(obj->token_op_q_lock)); + _os_mem_free(d, obj, sizeof(struct cmd_dispatcher)); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_start(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + + if (TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + init_dispr_msg_pool(obj); + init_cmd_req_pool(obj); + init_dispr_mdl_mgnt_info(obj); + _os_mem_set(d, &(obj->renew_req_info), 0, + sizeof(struct phl_token_op_info)); + _os_sema_init(d, &(obj->msg_q_sema), 0); + CLEAR_EXCL_MDL(obj); + if (disp_eng_is_solo_thread_mode(obj->phl_info)) { + _os_thread_init(d, &(obj->bk_thread), background_thread_hdl, obj, + "dispr_solo_thread"); + _os_thread_schedule(d, &(obj->bk_thread)); + } + SET_STATUS_FLAG(obj->status, DISPR_STARTED); + _start_dispr_controller(obj); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +bool is_dispr_started(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + + if (TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return true; + return false; +} + +enum rtw_phl_status dispr_stop(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + dispr_thread_stop_prior_hdl(obj); + if (disp_eng_is_solo_thread_mode(obj->phl_info)) { + _os_thread_stop(d, &(obj->bk_thread)); + _os_sema_up(d, &(obj->msg_q_sema)); + _os_thread_deinit(d, &(obj->bk_thread)); + } + dispr_thread_stop_post_hdl(obj); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_register_module(void *dispr, + enum phl_module_id id, + struct phl_bk_module_ops *ops) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_bk_module *module = NULL; + u8 ret = true; + enum phl_bk_module_priority priority = _get_mdl_priority(id); + + FUNCIN(); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || + priority == PHL_MDL_PRI_MAX || + chk_module_ops(ops) == false || + _chk_bitmap_bit(obj->bitmap, id) == true) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, register fail\n", __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + module = (struct phl_bk_module *)_os_mem_alloc(d, sizeof(struct phl_bk_module)); + if (module == NULL) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, allocte fail\n", __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + module->id = id; + _os_mem_cpy(d, &(module->ops), ops, sizeof(struct phl_bk_module_ops)); + pq_push(d, &(obj->module_q[priority]), &(module->list), _tail, _bh); + + ret = bk_module_init(obj, module); + if (ret == true && TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) { + ret = bk_module_start(obj, module); + if (ret == true) + _add_bitmap_bit(obj->bitmap, &(module->id), 1); + if (ret == true && priority != PHL_MDL_PRI_OPTIONAL) + _add_bitmap_bit(obj->basemap, &(module->id), 1); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s id:%d, ret:%d\n",__FUNCTION__, id, ret); + if (ret == true) { + return RTW_PHL_STATUS_SUCCESS; + } else { + bk_module_deinit(obj, module); + _os_mem_free(d, module, sizeof(struct phl_bk_module)); + return RTW_PHL_STATUS_FAILURE; + } +} + +enum rtw_phl_status dispr_deregister_module(void *dispr, + enum phl_module_id id) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_bk_module *module = NULL; + _os_list *mdl = NULL; + enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE; + enum phl_bk_module_priority priority = _get_mdl_priority(id); + + FUNCIN(); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || + priority == PHL_MDL_PRI_MAX) + return phl_stat; + + if(pq_search_node(d, &(obj->module_q[priority]), &mdl, _bh, true, &id, search_mdl)) { + module = (struct phl_bk_module *)mdl; + _clr_bitmap_bit(obj->bitmap, &(module->id), 1); + _clr_bitmap_bit(obj->basemap, &(module->id), 1); + bk_module_stop(obj, module); + bk_module_deinit(obj, module); + _os_mem_free(d, module, sizeof(struct phl_bk_module)); + phl_stat = RTW_PHL_STATUS_SUCCESS; + } + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id: %d stat:%d\n", __FUNCTION__, id, phl_stat); + return phl_stat; +} + +enum rtw_phl_status dispr_module_init(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *mdl = NULL; + u8 i = 0; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT)) + return RTW_PHL_STATUS_FAILURE; + + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false) + continue; + do { + bk_module_init(obj, (struct phl_bk_module *)mdl); + } while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh)); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_module_deinit(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *mdl = NULL; + u8 i = 0; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT)) + return RTW_PHL_STATUS_FAILURE; + + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + while (pq_pop(d, &(obj->module_q[i]), &mdl, _first, _bh)) { + bk_module_deinit(obj, (struct phl_bk_module *)mdl); + _os_mem_free(d, mdl, sizeof(struct phl_bk_module)); + } + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_module_start(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *mdl = NULL; + struct phl_bk_module *module = NULL; + u8 i = 0; + u8 ret = false; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false) + continue; + do { + module = (struct phl_bk_module*)mdl; + ret = bk_module_start(obj, module); + if (ret == true) + _add_bitmap_bit(obj->bitmap, &(module->id), 1); + if (ret == true && i != PHL_MDL_PRI_OPTIONAL) + _add_bitmap_bit(obj->basemap, &(module->id), 1); + } while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh)); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + /*_print_bitmap(obj->bitmap);*/ + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_module_stop(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *mdl = NULL; + struct phl_bk_module *module = NULL; + u8 i = 0; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false) + continue; + do { + module = (struct phl_bk_module *)mdl; + _clr_bitmap_bit(obj->bitmap, &(module->id), 1); + _clr_bitmap_bit(obj->basemap, &(module->id), 1); + bk_module_stop(obj, module); + } while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh)); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + /*_print_bitmap(obj->bitmap);*/ + return RTW_PHL_STATUS_SUCCESS; +} + +/** + * dispr_get_cur_cmd_req -- background module can call this function to + * check cmd dispatcher is idle to know the risk or conflict for the I/O. + * @dispr: dispatcher handler, get from _disp_eng_get_dispr_by_idx + * @handle: get current cmd request, NULL means cmd dispatcher is idle + + * return RTW_PHL_STATUS_SUCCESS means cmd dispatcher is busy and can get + * current cmd request from handle parameter + * return RTW_PHL_STATUS_FAILURE means cmd dispatcher is idle + */ +enum rtw_phl_status +dispr_get_cur_cmd_req(void *dispr, void **handle) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + struct phl_cmd_token_req_ex *cur_req = NULL; + enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT|DISPR_STARTED) || handle == NULL) { + phl_stat = RTW_PHL_STATUS_UNEXPECTED_ERROR; + return phl_stat; + } + + (*handle) = NULL; + cur_req = obj->cur_cmd_req; + + if (cur_req == NULL || + !TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) || + TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL)) + return phl_stat; + + *handle = (void *)cur_req; + phl_stat = RTW_PHL_STATUS_SUCCESS; + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, + "%s, req module id:%d phl_stat:%d\n", __FUNCTION__, + cur_req->req.module_id, phl_stat); + return phl_stat; +} + +enum rtw_phl_status +dispr_set_cur_cmd_info(void *dispr, + struct phl_module_op_info *op_info) +{ + void *handle = NULL; + struct phl_cmd_token_req_ex *cmd_req = NULL; + struct phl_cmd_token_req *req = NULL; + + if (RTW_PHL_STATUS_SUCCESS != dispr_get_cur_cmd_req(dispr, &handle)) + return RTW_PHL_STATUS_FAILURE; + + cmd_req = (struct phl_cmd_token_req_ex *)handle; + req = &(cmd_req->req); + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, req->module_id); + if (req->set_info(dispr, req->priv, op_info) == MDL_RET_SUCCESS) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status +dispr_query_cur_cmd_info(void *dispr, + struct phl_module_op_info *op_info) +{ + void *handle = NULL; + struct phl_cmd_token_req_ex *cmd_req = NULL; + struct phl_cmd_token_req *req = NULL; + + if (RTW_PHL_STATUS_SUCCESS != dispr_get_cur_cmd_req(dispr, &handle)) + return RTW_PHL_STATUS_FAILURE; + + cmd_req = (struct phl_cmd_token_req_ex *)handle; + req = &(cmd_req->req); + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, "%s, id:%d\n", __FUNCTION__, req->module_id); + if (req->query_info(dispr, req->priv, op_info) == MDL_RET_SUCCESS) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status +dispr_get_bk_module_handle(void *dispr, + enum phl_module_id id, + void **handle) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + _os_list *mdl = NULL; + enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE; + enum phl_bk_module_priority priority = _get_mdl_priority(id); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || + handle == NULL || + priority == PHL_MDL_PRI_MAX || + !_chk_bitmap_bit(obj->bitmap, id)) + return phl_stat; + + (*handle) = NULL; + + + if(pq_search_node(d, &(obj->module_q[priority]), &mdl, _bh, false, &id, search_mdl)) { + (*handle) = mdl; + phl_stat = RTW_PHL_STATUS_SUCCESS; + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat); + return phl_stat; +} + +enum rtw_phl_status +dispr_set_bk_module_info(void *dispr, + void *handle, + struct phl_module_op_info *op_info) +{ + struct phl_bk_module *module = (struct phl_bk_module *)handle; + struct phl_bk_module_ops *ops = &(module->ops); + + if (!TEST_STATUS_FLAG(module->status, MDL_INIT)) + return RTW_PHL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, module->id); + if (ops->set_info(dispr, module->priv, op_info) == MDL_RET_SUCCESS) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status +dispr_query_bk_module_info(void *dispr, + void *handle, + struct phl_module_op_info *op_info) +{ + struct phl_bk_module *module = (struct phl_bk_module *)handle; + struct phl_bk_module_ops *ops = &(module->ops); + + if (!TEST_STATUS_FLAG(module->status, MDL_INIT)) + return RTW_PHL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, module->id); + if (ops->query_info(dispr, module->priv, op_info) == MDL_RET_SUCCESS) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status +dispr_set_src_info(void *dispr, + struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE; + u8 id = MSG_MDL_ID_FIELD(msg->msg_id); + struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req; + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + struct phl_dispr_msg_ex *ex = (struct phl_dispr_msg_ex *)msg; + u8 cur_req_id = get_cur_cmd_req_id(obj, NULL); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || + (!_chk_bitmap_bit(obj->bitmap, id) && + cur_req_id != id)) + return phl_stat; + + if (cur_req_id == id) { + ret = cur_req->req.set_info(dispr, cur_req->req.priv, op_info); + } else if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL)) { + ret = ex->module->ops.set_info(dispr, ex->module->priv, + op_info); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat); + if (ret == MDL_RET_FAIL) + return RTW_PHL_STATUS_FAILURE; + else + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +dispr_query_src_info(void *dispr, + struct phl_msg *msg, + struct phl_module_op_info *op_info) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE; + u8 id = MSG_MDL_ID_FIELD(msg->msg_id); + struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req; + struct phl_dispr_msg_ex *ex = (struct phl_dispr_msg_ex *)msg; + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + u8 cur_req_id = get_cur_cmd_req_id(obj, NULL); + + if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || + (!_chk_bitmap_bit(obj->bitmap, id) && + cur_req_id != id)) + return phl_stat; + + if (cur_req_id == id) { + ret = cur_req->req.query_info(dispr, cur_req->req.priv, op_info); + } else if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL)) { + ret = ex->module->ops.query_info(dispr, ex->module->priv, + op_info); + } + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat); + if (ret == MDL_RET_FAIL) + return RTW_PHL_STATUS_FAILURE; + else + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +dispr_send_msg(void *dispr, + struct phl_msg *msg, + struct phl_msg_attribute *attr, + u32 *msg_hdl) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_dispr_msg_ex *msg_ex = NULL; + u8 module_id = MSG_MDL_ID_FIELD(msg->msg_id); /* msg src */ + u32 req_status = 0; + u8 cur_req_id = get_cur_cmd_req_id(obj, &req_status); + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) { + sts = RTW_PHL_STATUS_UNEXPECTED_ERROR; + goto err; + } + + if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)){ + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,"%s: dispr shall stop\n", __FUNCTION__); + sts = RTW_PHL_STATUS_UNEXPECTED_ERROR; + goto err; + } + + if(attr && attr->notify.id_arr == NULL && attr->notify.len) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s attribute err\n",__FUNCTION__); + sts = RTW_PHL_STATUS_INVALID_PARAM; + goto err; + } + + if (!IS_DISPR_CTRL(module_id) && + !_chk_bitmap_bit(obj->bitmap, module_id) && + ((cur_req_id != PHL_MDL_ID_MAX && cur_req_id != module_id) || + (cur_req_id == PHL_MDL_ID_MAX && req_status == 0)|| + (cur_req_id == PHL_MDL_ID_MAX && !TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT)))) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s module not allow to send\n", __FUNCTION__); + sts = RTW_PHL_STATUS_INVALID_PARAM; + goto err; + } + + if (!pop_front_idle_msg(obj, &msg_ex)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s idle msg empty\n", __FUNCTION__); + sts = RTW_PHL_STATUS_RESOURCE; + goto err; + } + + if (msg_hdl) + *msg_hdl = 0; + + _os_mem_cpy(d, &msg_ex->msg, msg, sizeof(struct phl_msg)); + + set_msg_bitmap(obj, msg_ex, module_id); + if (attr) { +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + msg_ex->attr = (struct dispr_msg_attr *)attr->dispr_attr; + attr->dispr_attr = NULL; +#endif + set_msg_custom_bitmap(obj, msg_ex, attr->opt, + attr->notify.id_arr, attr->notify.len, module_id); + if (attr->completion.completion) { + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_NOTIFY_COMPLETE); + msg_ex->completion.completion = attr->completion.completion; + msg_ex->completion.priv = attr->completion.priv; + } + if (TEST_STATUS_FLAG(attr->opt, MSG_OPT_CLR_SNDR_MSG_IF_PENDING)) + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_CLR_SNDR_MSG_IF_PENDING); + + if (TEST_STATUS_FLAG(attr->opt, MSG_OPT_PENDING_DURING_CANNOT_IO)) + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_PENDING_DURING_CANNOT_IO); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, opt:0x%x\n",__FUNCTION__, attr->opt); + } + + if (get_module_by_id(obj, module_id, &(msg_ex->module)) == true) { + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_BK_MDL); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s module(%d) found\n", __FUNCTION__, module_id); + } else if ((cur_req_id == module_id) || + (cur_req_id == PHL_MDL_ID_MAX && TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT))) { + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ); + } + + if(TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ) && + TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT) && + (attr == NULL || !TEST_STATUS_FLAG(attr->opt, MSG_OPT_SEND_IN_ABORT))) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s msg not allow since cur req is going to unload\n", __FUNCTION__); + SET_MSG_INDC_FIELD(msg_ex->msg.msg_id, MSG_INDC_FAIL); + push_back_idle_msg(obj, msg_ex); + sts = RTW_PHL_STATUS_FAILURE; + goto exit; + } + + if (TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ) && + TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT)) { + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_FOR_ABORT); + SET_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE); + } + + SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_PRE_PHASE); + + if (IS_DISPR_CTRL(module_id)) + insert_msg_by_priority(obj, msg_ex); + else + push_back_wait_msg(obj, msg_ex); + + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, status:0x%x\n",__FUNCTION__, msg_ex->status); + if(msg_hdl) + *msg_hdl = GEN_VALID_HDL(msg_ex->idx); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, msg_id:0x%x\n", __FUNCTION__, msg->msg_id); + return RTW_PHL_STATUS_SUCCESS; +err: +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + if(attr) + free_dispr_attr(d,(struct dispr_msg_attr **) &(attr->dispr_attr)); +#endif +exit: + return sts; +} + +enum rtw_phl_status dispr_cancel_msg(void *dispr, u32 *msg_hdl) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + struct phl_dispr_msg_ex *msg_ex = NULL; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || msg_hdl == NULL) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + if (!IS_HDL_VALID(*msg_hdl) || + GET_IDX_FROM_HDL(*msg_hdl) >= MAX_PHL_MSG_NUM) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, HDL invalid\n", __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + msg_ex = &(obj->msg_ex_pool[GET_IDX_FROM_HDL(*msg_hdl)]); + *msg_hdl = 0; + if (!TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_ENQ) && + !TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_RUN)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, HDL status err\n", __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + cancel_msg(obj, msg_ex); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status dispr_clr_pending_msg(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + + SET_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG); + notify_bk_thread(obj); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + return RTW_PHL_STATUS_SUCCESS; +} +enum rtw_phl_status +dispr_add_token_req(void *dispr, + struct phl_cmd_token_req *req, + u32 *req_hdl) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_cmd_token_req_ex *req_ex = NULL; + enum rtw_phl_status stat = RTW_PHL_STATUS_SUCCESS; + _os_list *node = NULL; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || + req_hdl == NULL || + chk_cmd_req_ops(req) == false) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)){ + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,"%s: dispr shall stop\n", __FUNCTION__); + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + } + + if (!pop_front_idle_req(obj, &req_ex)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s idle req empty\n", __FUNCTION__); + return RTW_PHL_STATUS_RESOURCE; + } + _os_mem_cpy(d, &(req_ex->req), req, sizeof(struct phl_cmd_token_req)); + + push_back_wait_req(obj, req_ex); + *req_hdl = GEN_VALID_HDL(req_ex->idx); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, id:%d, hdl:0x%x token_cnt:%d\n", __FUNCTION__, + req->module_id, + *req_hdl, + _os_atomic_read(d, &(obj->token_cnt))); + + if (pq_get_front(d, &(obj->token_op_q), &node, _bh) == false && + _os_atomic_read(d, &(obj->token_cnt)) == 0) + stat = RTW_PHL_STATUS_SUCCESS; + else + stat = RTW_PHL_STATUS_PENDING; + dispr_enqueue_token_op_info(obj, &req_ex->add_req_info, TOKEN_OP_ADD_CMD_REQ, req_ex->idx); + return stat; +} + +enum rtw_phl_status dispr_cancel_token_req(void *dispr, u32 *req_hdl) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + struct phl_cmd_token_req_ex *req_ex = NULL; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || req_hdl == NULL) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + if (!IS_HDL_VALID(*req_hdl) || + GET_IDX_FROM_HDL(*req_hdl) >= MAX_CMD_REQ_NUM) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s, HDL(0x%x) invalid\n", __FUNCTION__, *req_hdl); + return RTW_PHL_STATUS_FAILURE; + } + req_ex = &(obj->token_req_ex_pool[GET_IDX_FROM_HDL(*req_hdl)]); + if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_ENQ) && + !TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN) && + !TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_PREPARE)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s, HDL(0x%x) status err\n", __FUNCTION__, *req_hdl); + return RTW_PHL_STATUS_FAILURE; + } + SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL); + if (dispr_enqueue_token_op_info(obj, &req_ex->free_req_info, TOKEN_OP_CANCEL_CMD_REQ, req_ex->idx)) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status dispr_free_token(void *dispr, u32 *req_hdl) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_cmd_token_req_ex *req_ex = NULL; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || req_hdl == NULL) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + if (obj->cur_cmd_req == NULL || + _os_atomic_read(d, &(obj->token_cnt)) == 0 || + !IS_HDL_VALID(*req_hdl) || + GET_IDX_FROM_HDL(*req_hdl) >= MAX_CMD_REQ_NUM) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s, HDL(0x%x) invalid\n", __FUNCTION__, *req_hdl); + return RTW_PHL_STATUS_FAILURE; + } + req_ex = &(obj->token_req_ex_pool[GET_IDX_FROM_HDL(*req_hdl)]); + if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN) && + !TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_PREPARE)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, + "%s, HDL(0x%x) mismatch\n", __FUNCTION__, *req_hdl); + return RTW_PHL_STATUS_FAILURE; + } + SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL); + if (dispr_enqueue_token_op_info(obj, &req_ex->free_req_info, TOKEN_OP_FREE_CMD_REQ, req_ex->idx)) + return RTW_PHL_STATUS_SUCCESS; + else + return RTW_PHL_STATUS_FAILURE; +} + +enum rtw_phl_status dispr_notify_dev_io_status(void *dispr, enum phl_module_id mdl_id, bool allow_io) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + + if (allow_io == false) { + if (!TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) { + SET_STATUS_FLAG(obj->status, DISPR_CANNOT_IO); + SET_EXCL_MDL(obj, mdl_id); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, mdl_id(%d) notify cannot io\n", __FUNCTION__, mdl_id); + status = send_dev_io_status_change(obj, allow_io); + } + } + else { + if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) { + CLEAR_STATUS_FLAG(obj->status, DISPR_CANNOT_IO); + CLEAR_EXCL_MDL(obj); + status = send_dev_io_status_change(obj, allow_io); + dispr_clr_pending_msg(dispr); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, mdl_id(%d) notify io resume\n", __FUNCTION__, mdl_id); + } + } + return status; +} + +void dispr_notify_shall_stop(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + + if (!TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) { + SET_STATUS_FLAG(obj->status, DISPR_SHALL_STOP); + dispr_clr_pending_msg(dispr); + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, notify shall stop\n", __FUNCTION__); + } +} + +u8 dispr_is_fg_empty(void *dispr) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + bool is_empty = true; + void *drv = phl_to_drvpriv(obj->phl_info); + struct phl_queue *q = NULL; + _os_list *node = NULL; + + do { + /* shall check wait queue first then check token op queue + * to avoid to get the incorrect empty state of fg cmd + */ + q = &(obj->token_req_wait_q); + _os_spinlock(drv, &(q->lock), _bh, NULL); + if(!list_empty(&q->queue) && (q->cnt > 0)) { + is_empty = false; + _os_spinunlock(drv, &(q->lock), _bh, NULL); + break; + } + _os_spinunlock(drv, &(q->lock), _bh, NULL); + + if (pq_get_front(drv, &(obj->token_op_q), &node, _bh) == true || + _os_atomic_read(drv, &(obj->token_cnt)) > 0) { + is_empty = false; + break; + } + } while(false); + + return is_empty; +} + +enum rtw_phl_status dispr_process_token_req(struct cmd_dispatcher *obj) +{ + void *d = phl_to_drvpriv(obj->phl_info); + struct phl_cmd_token_req_ex *ex = NULL; + + do { + if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) + return RTW_PHL_STATUS_UNEXPECTED_ERROR; + + if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s: dispr shall stop\n", __FUNCTION__); + + return RTW_PHL_STATUS_FAILURE; + } + + if (_os_atomic_read(d, &(obj->token_cnt)) > 0) + return RTW_PHL_STATUS_FAILURE; + + if (TEST_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE)) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, + "%s, wait for abort msg sent from prev req finish before register next req \n", __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + if (pop_front_wait_req(obj, &ex) == false) { + if (!TEST_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE)) { + SET_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE); + send_bk_msg_phy_idle(obj); + } + return RTW_PHL_STATUS_SUCCESS; + } + + if (TEST_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE)) { + CLEAR_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE); + send_bk_msg_phy_on(obj); + } + + }while(!register_cur_cmd_req(obj, ex)); + + return RTW_PHL_STATUS_SUCCESS; +} + +void dispr_share_thread_loop_hdl(void *dispr) +{ + dispr_thread_loop_hdl( (struct cmd_dispatcher *)dispr); +} + +void dispr_share_thread_leave_hdl(void *dispr) +{ + dispr_thread_leave_hdl((struct cmd_dispatcher *)dispr); +} + +void dispr_share_thread_stop_prior_hdl(void *dispr) +{ + dispr_thread_stop_prior_hdl((struct cmd_dispatcher *)dispr); +} + +void dispr_share_thread_stop_post_hdl(void *dispr) +{ + dispr_thread_stop_post_hdl((struct cmd_dispatcher *)dispr); +} + +u8 disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl) +{ + struct phl_bk_module *mdl = NULL; + + if (bk_mdl != NULL) { + mdl = (struct phl_bk_module *)bk_mdl; + return mdl->id; + } else { + return PHL_MDL_ID_MAX; + } +} + +void send_bk_msg_phy_on(struct cmd_dispatcher *obj) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PHY_ON); + dispr_send_msg((void*)obj, &msg, &attr, NULL); +} + +void send_bk_msg_phy_idle(struct cmd_dispatcher *obj) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PHY_IDLE); + dispr_send_msg((void*)obj, &msg, &attr, NULL); +} + +enum rtw_phl_status send_dev_io_status_change(struct cmd_dispatcher *obj, u8 allow_io) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u16 event = (allow_io == true) ? (MSG_EVT_DEV_RESUME_IO) : (MSG_EVT_DEV_CANNOT_IO); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, event); + return dispr_send_msg((void*)obj, &msg, &attr, NULL); +} + +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ +enum phl_mdl_ret_code loop_through_map(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, + enum phl_bk_module_priority priority, struct msg_notify_map *map, u8 pre_prot_phase) +{ + u8 i = 0; + struct phl_bk_module *mdl = NULL; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + u8 *bitmap = (pre_prot_phase == true) ? (ex->premap) : (ex->postmap); + + for (i = 0 ; i < map->len; i++) { + if (map->id_arr[i] >= PHL_FG_MDL_START) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_WARNING_, + "%s, cmd req does not take precedence over bk module\n", __FUNCTION__); + continue; + } + mdl = (struct phl_bk_module *)GET_MDL_HANDLE(obj, map->id_arr[i]); + if (mdl == NULL || !_chk_bitmap_bit(bitmap, mdl->id)) + continue; + /*only allow sequence rearrange for modules at the same priority*/ + if ( _get_mdl_priority(mdl->id) != priority) + continue; + ret = feed_mdl_msg(obj, mdl, ex); + if (STOP_DISPATCH_MSG(ret)) + return ret; + } + return ret; +} + +static enum phl_mdl_ret_code run_self_def_seq(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, + enum phl_bk_module_priority priority, u8 pre_prot_phase) +{ + struct msg_notify_map *map = NULL; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct msg_dispatch_seq* seq = NULL; + + if (ex->attr == NULL) + return ret; + /*MANDATORY modules cannot change dispatch order*/ + if (pre_prot_phase == true) + seq = &(ex->attr->self_def_seq.pre_prot_phase); + else + seq = &(ex->attr->self_def_seq.post_prot_phase); + + return loop_through_map(obj, ex, priority, &(seq->map[priority]), pre_prot_phase); +} +void reset_self_def_seq(void *d, struct msg_self_def_seq* self_def_seq) +{ + u8 i = 0; + u8 cnt = 0; + struct msg_dispatch_seq *seq = (struct msg_dispatch_seq *)self_def_seq; + + while (cnt++ < 2) { + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + if (seq->map[i].len) + _os_kmem_free(d, seq->map[i].id_arr, seq->map[i].len); + seq->map[i].id_arr = NULL; + seq->map[i].len = 0; + } + seq++; + } + +} + +u8 copy_self_def_seq(void *d, struct msg_self_def_seq* self_def_dest, struct msg_self_def_seq* self_def_src) +{ + u8 i = 0; + u8 cnt = 0; + struct msg_dispatch_seq *dest = (struct msg_dispatch_seq *)self_def_dest; + struct msg_dispatch_seq *src = (struct msg_dispatch_seq *)self_def_src; + + while (cnt++ < 2) { + for (i = 0; i < PHL_MDL_PRI_MAX; i++) { + if (src->map[i].len) { + dest->map[i].id_arr = _os_kmem_alloc(d, src->map[i].len); + if (dest->map[i].id_arr == NULL) + return false; + dest->map[i].len = src->map[i].len; + _os_mem_cpy(d, dest->map[i].id_arr, src->map[i].id_arr, dest->map[i].len); + } + } + dest++; + src++; + } + return true; +} + +inline static u8 alloc_dispr_attr(void *d, struct phl_msg_attribute *attr) +{ + if (attr->dispr_attr == NULL) + attr->dispr_attr = _os_kmem_alloc(d, sizeof(struct dispr_msg_attr)); + if (attr->dispr_attr != NULL) + _os_mem_set(d, attr->dispr_attr, sizeof(struct dispr_msg_attr)); + return (attr->dispr_attr == NULL) ? (false) : (true); +} + +enum rtw_phl_status dispr_set_dispatch_seq(void *dispr, struct phl_msg_attribute *attr, + struct msg_self_def_seq* seq) +{ + struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr; + void *d = phl_to_drvpriv(obj->phl_info); + struct dispr_msg_attr *dispr_attr = NULL; + + if (attr == NULL || seq == NULL) + return RTW_PHL_STATUS_INVALID_PARAM; + + if (alloc_dispr_attr(d, attr) == false) + goto err_attr_alloc; + + dispr_attr = attr->dispr_attr; + reset_self_def_seq(d, &(dispr_attr->self_def_seq)); + + if (copy_self_def_seq(d, &(dispr_attr->self_def_seq), seq) == false) + goto err_seq_copy; + return RTW_PHL_STATUS_SUCCESS; +err_seq_copy: + free_dispr_attr(d, &(attr->dispr_attr)); +err_attr_alloc: + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_WARNING_, + "%s, err\n", __FUNCTION__); + return RTW_PHL_STATUS_RESOURCE; +} + +static void free_dispr_attr(void *d, struct dispr_msg_attr **dispr_attr) +{ + struct dispr_msg_attr *attr = NULL; + + if (dispr_attr == NULL || *dispr_attr == NULL) + return; + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__); + attr = *dispr_attr; + reset_self_def_seq(d, &(attr->self_def_seq)); + _os_kmem_free(d, attr, sizeof(struct dispr_msg_attr)); + *dispr_attr = NULL; +} +#endif +#endif diff --git a/phl/phl_cmd_dispr_controller.c b/phl/phl_cmd_dispr_controller.c new file mode 100644 index 0000000..4f882ae --- /dev/null +++ b/phl/phl_cmd_dispr_controller.c @@ -0,0 +1,684 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_DISPR_CONTROLLER_C_ +#include "phl_headers.h" + +#ifdef CONFIG_CMD_DISP + +struct cmd_controller { + struct phl_info_t *phl_info; + u32 mon_mdl_id; /* monitor module id */ + bool mon_mdl; +}; + + +/* Each dispr has a controller. + * A dispr controller is designed for phl instance to interact with dispr modules that are belonged to a specific hw band, + * phl instance can perform follwing actions via dedicated controller: + * 1. allow (phl status/non-dispr phl modules) to monitor & drop msg + * 2. allow dispr modules, that are belonged to same dispr, to sequentially communicate with phl instance & call phl api, + * and also allow (phl status/non-dispr phl modules) to notify dispr by hw band. + * *Note* + * 1. when cmd dispatch engine is in solo thread mode (each dispr has its own dedicated thread). + * phl instance might receive msg from different dispr simutaneously and + * currently using semaphore (dispr_ctrl_sema) to prevent multi-thread condition. + * 2. when cmd dispatch engine is in share thread mode, msg from different dispr would pass to controller sequentially. + + * PS: + * phl instance: means phl_info_t, which include phl mgnt status & non-dispr phl modules + * dispr modules: all existing background & foreground modules. + * non-dispr phl module : Data path (TX/Rx), etc + * phl mgnt status : stop/surprise remove/cannot io +*/ + +enum phl_mdl_ret_code +_dispr_resume_io_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + do { + ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_, + "[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n", + phl_info->pause_tx_id, ctl.id, + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + break; + } + + ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, + "[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n", + phl_info->pause_rx_id, ctl.id, + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + break; + } + + ret = MDL_RET_SUCCESS; + } while (false); + + return ret; +} + + +enum phl_mdl_ret_code +_dispr_cannot_io_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_, + "[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_hw_trx_rst_resume_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_HW_TRX_RST_RESUME; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] HW T/Rx reset and resume fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_hw_trx_pause_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_HW_TRX_PAUSE; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] HW T/Rx pause fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_tx_resume_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id); + + /* tx pause by MDL_POWER_MGNT, tx resume by MDL_TX/MDL_RX */ + if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX) + ctl.id = PHL_MDL_POWER_MGNT; + else + ctl.id = mdl_id; + ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME; + + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n", + phl_info->pause_tx_id, ctl.id, + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_rx_resume_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id); + + /* rx pause by MDL_POWER_MGNT, rx resume by MDL_TX/MDL_RX */ + if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX) + ctl.id = PHL_MDL_POWER_MGNT; + else + ctl.id = mdl_id; + ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME; + + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n", + phl_info->pause_rx_id, ctl.id, + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_tx_pause_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Tx pause fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_rx_pause_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_SW_RX_PAUSE; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Rx pause fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_tx_reset_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_SW_TX_RESET; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Tx reset fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_sw_rx_reset_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_SW_RX_RESET; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW Rx reset fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_trx_sw_pause_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_trx_sw_resume_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_TRX_SW_RESUME; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW T/Rx resume fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_trx_pause_w_rst_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_TRX_PAUSE_W_RST; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW T/Rx pause with reset fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_trx_resume_w_rst_ctrl(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.cmd = PHL_DATA_CTL_TRX_RESUME_W_RST; + ctl.id = MSG_MDL_ID_FIELD(msg->msg_id); + sts = phl_data_ctrler(phl_info, &ctl, msg); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "[DATA_CTRL] SW T/Rx resume with reset fail by module(%d) with event(%d)\n", + ctl.id, MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_FAIL; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +enum phl_mdl_ret_code +_dispr_mdl_stop_ctrl(struct phl_info_t *phl_info, + struct cmd_controller *cmd_ctrl) +{ + if (cmd_ctrl->mon_mdl_id != 0) { + cmd_ctrl->mon_mdl = true; + return MDL_RET_PENDING; + } else { + return MDL_RET_SUCCESS; + } +} + +enum phl_mdl_ret_code +_dispr_ctrl_init(void *phl, + void *dispr, + void **priv) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct cmd_controller *cmd_ctrl = NULL; + void *drv = phl_to_drvpriv(phl_info); + + PHL_INFO("%s(): \n", __func__); + + (*priv) = NULL; + cmd_ctrl = (struct cmd_controller *)_os_mem_alloc(drv, + sizeof(struct cmd_controller)); + + if (cmd_ctrl == NULL) { + PHL_ERR(" %s, alloc fail\n",__FUNCTION__); + return MDL_RET_FAIL; + } + + cmd_ctrl->phl_info = phl_info; + (*priv) = (void*)cmd_ctrl; + return MDL_RET_SUCCESS; +} + +void _dispr_ctrl_deinit(void *dispr, void *priv) +{ + struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv; + void *drv = phl_to_drvpriv(cmd_ctrl->phl_info); + + _os_mem_free(drv, cmd_ctrl, sizeof(struct cmd_controller)); + + PHL_INFO("%s(): \n", __func__); +} + +enum phl_mdl_ret_code _dispr_ctrl_start(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv; + struct phl_info_t *phl_info = (struct phl_info_t *)cmd_ctrl->phl_info; + void *drv = phl_to_drvpriv(cmd_ctrl->phl_info); + + PHL_INFO("%s(): \n", __func__); + + _os_mem_set(drv, cmd_ctrl, 0, sizeof(struct cmd_controller)); + cmd_ctrl->phl_info = phl_info; + + return ret; +} + +enum phl_mdl_ret_code _dispr_ctrl_stop(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + + PHL_INFO("%s(): \n", __func__); + + return ret; +} + +static void _fail_hdlr(void *dispr, struct phl_info_t *phl_info, struct phl_msg *msg) +{ + +} + +static enum phl_mdl_ret_code +_ctrler_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_DEV_RESUME_IO: + ret = _dispr_resume_io_ctrl(phl_info, msg); + break; + case MSG_EVT_DEV_CANNOT_IO: + ret = _dispr_cannot_io_ctrl(phl_info, msg); + break; + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_tx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_TRX_PWR_REQ: + /* ps module handle MSG_EVT_TRX_PWR_REQ itself */ + default: + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_rx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_TRX_PWR_REQ: + /* ps module handle MSG_EVT_TRX_PWR_REQ itself */ + default: + break; + } + + return ret; +} + +static void _mon_msg_hdlr(struct cmd_controller *cmd_ctrl, + struct phl_msg *msg) +{ + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_SER_L0_RESET: + case MSG_EVT_SER_M1_PAUSE_TRX: + case MSG_EVT_SER_M3_DO_RECOV: + cmd_ctrl->mon_mdl_id = PHL_MDL_SER; + break; + case MSG_EVT_SER_M5_READY: + cmd_ctrl->mon_mdl_id = 0; + if (cmd_ctrl->mon_mdl) + phl_disp_eng_clr_pending_msg(cmd_ctrl->phl_info, msg->band_idx); + cmd_ctrl->mon_mdl = false; + break; + } +} + +static enum phl_mdl_ret_code _internal_msg_hdlr(void *dispr, + struct cmd_controller *cmd_ctrl, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct phl_info_t *phl_info = cmd_ctrl->phl_info; + + /* sender is controller itself */ + if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_PHY_MGNT) { + ret = _ctrler_msg_hdlr(phl_info, msg); + } else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_TX) { + ret = _tx_msg_hdlr(phl_info, msg); + } else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_RX) { + ret = _rx_msg_hdlr(phl_info, msg); + } + + return ret; +} + +static enum phl_mdl_ret_code +_external_msg_hdlr(void *dispr, + struct cmd_controller *cmd_ctrl, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = cmd_ctrl->phl_info; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + if (phl_com->dev_state & RTW_DEV_RESUMING) { + PHL_WARN("Controller: MDL_ID(%d)-EVT_ID(%d) is sent during RTW_DEV_RESUMING!\n", + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + } + + if (phl_com->dev_state & RTW_DEV_SURPRISE_REMOVAL) { + PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "Controller: msg fail due to invalid device state\n"); + return MDL_RET_FAIL; + } + + _mon_msg_hdlr(cmd_ctrl, msg); + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_HW_TRX_RST_RESUME: + ret = _dispr_hw_trx_rst_resume_ctrl(phl_info, msg); + break; + case MSG_EVT_HW_TRX_PAUSE: + ret = _dispr_hw_trx_pause_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_TX_RESUME: + ret = _dispr_sw_tx_resume_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_RX_RESUME: + ret = _dispr_sw_rx_resume_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_TX_PAUSE: + ret = _dispr_sw_tx_pause_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_RX_PAUSE: + ret = _dispr_sw_rx_pause_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_TX_RESET: + ret = _dispr_sw_tx_reset_ctrl(phl_info, msg); + break; + case MSG_EVT_SW_RX_RESET: + ret = _dispr_sw_rx_reset_ctrl(phl_info, msg); + break; + case MSG_EVT_TRX_SW_PAUSE: + ret = _dispr_trx_sw_pause_ctrl(phl_info, msg); + break; + case MSG_EVT_TRX_SW_RESUME: + ret = _dispr_trx_sw_resume_ctrl(phl_info, msg); + break; + case MSG_EVT_TRX_PAUSE_W_RST: + ret = _dispr_trx_pause_w_rst_ctrl(phl_info, msg); + break; + case MSG_EVT_TRX_RESUME_W_RST: + ret = _dispr_trx_resume_w_rst_ctrl(phl_info, msg); + break; + case MSG_EVT_MDL_CHECK_STOP: + ret = _dispr_mdl_stop_ctrl(phl_info, cmd_ctrl); + break; + default: + break; + } + + return ret; +} +enum phl_mdl_ret_code +_dispr_ctrl_msg_hdlr(void *dispr, + void *priv, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv; + + FUNCIN(); + if (IS_MSG_FAIL(msg->msg_id)) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "%s: cmd dispatcher notify cmd failure: 0x%x.\n", + __FUNCTION__, msg->msg_id); + _fail_hdlr(dispr, cmd_ctrl->phl_info, msg); + FUNCOUT(); + return MDL_RET_FAIL; + } + + if (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(msg->msg_id))) + ret = _internal_msg_hdlr(dispr, cmd_ctrl, msg); + else + ret = _external_msg_hdlr(dispr, cmd_ctrl, msg); + FUNCOUT(); + return ret; +} + +enum phl_mdl_ret_code +_dispr_ctrl_set_info(void *dispr, + void *priv, + struct phl_module_op_info *info) +{ + PHL_INFO("%s(): \n", __func__); + + return MDL_RET_IGNORE; +} + +enum phl_mdl_ret_code +_dispr_ctrl_query_info(void *dispr, void *priv, + struct phl_module_op_info *info) +{ + PHL_INFO("%s(): \n", __func__); + + return MDL_RET_IGNORE; +} + +void dispr_ctrl_hook_ops(void *dispr, struct phl_bk_module_ops *ops) +{ + if (ops == NULL) + return; + ops->init = _dispr_ctrl_init; + ops->deinit = _dispr_ctrl_deinit; + ops->start = _dispr_ctrl_start; + ops->stop = _dispr_ctrl_stop; + ops->msg_hdlr = _dispr_ctrl_msg_hdlr; + ops->set_info = _dispr_ctrl_set_info; + ops->query_info = _dispr_ctrl_query_info; +} +#endif + diff --git a/phl/phl_cmd_fsm.c b/phl/phl_cmd_fsm.c new file mode 100644 index 0000000..a543e04 --- /dev/null +++ b/phl/phl_cmd_fsm.c @@ -0,0 +1,782 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: vincent_fann@realtek.com + * + *****************************************************************************/ +#include "phl_headers.h" + +#ifdef CONFIG_FSM + +/* #define DEBUG_CMD_FSM_MODULE */ + +#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y)) +#ifdef FSM_DBG_MEM_OVERWRITE +#define _os_kmem_alloc(a, b) fsm_kmalloc(b) +#define _os_kmem_free(a, b, c) fsm_kfree(b, c) +#endif + +#define pstr(s) (s +_os_strlen((u8 *)s)) +#define lstr(s, l) (size_t)(l - _os_strlen((u8 *)s)) + +#ifdef CONFIG_RTW_SCAN_FSM +struct _adapter; +#endif +#define MAX_POWER_ON_TIME 100 +#define WDOG_ALARM_ID 1 +#define WD_DURATION 2000 /* 2sec */ + +enum CMD_STATE_ST { + CMD_ST_IDLE, + CMD_ST_REQ_PWR, + CMD_ST_SERVICE +}; + +enum CMD_EV_ID { + CMD_EV_REQ_PWR, + CMD_EV_DO_JOB, + CMD_EV_JOB_NOTIFY, + CMD_EV_PWR_ON_OK, + CMD_EV_PWR_ON_TIMEOUT, + CMD_EV_PWR_EXPIRE, + CMD_EV_WD_EXPIRE, + CMD_EV_WD_DO_JOB, + CMD_EV_MAX +}; + +static int cmd_idle_st_hdl(void *obj, u16 event, void *param); +static int cmd_req_pwr_st_hdl(void *obj, u16 event, void *param); +static int cmd_service_st_hdl(void *obj, u16 event, void *param); + +/* STATE table */ +static struct fsm_state_ent cmd_state_tbl[] = { + ST_ENT(CMD_ST_IDLE, cmd_idle_st_hdl), + ST_ENT(CMD_ST_REQ_PWR, cmd_req_pwr_st_hdl), + ST_ENT(CMD_ST_SERVICE, cmd_service_st_hdl), +}; + +/* EVENT table */ +static struct fsm_event_ent cmd_event_tbl[] = { + EV_ENT(CMD_EV_REQ_PWR), + EV_ENT(CMD_EV_DO_JOB), + EV_ENT(CMD_EV_JOB_NOTIFY), + EV_ENT(CMD_EV_PWR_ON_OK), + EV_ENT(CMD_EV_PWR_ON_TIMEOUT), + EV_ENT(CMD_EV_PWR_EXPIRE), + EV_DBG(CMD_EV_WD_EXPIRE), + EV_ENT(CMD_EV_WD_DO_JOB), + EV_ENT(CMD_EV_MAX) /* EV_MAX for fsm safety checking */ +}; + +/* + * command thread state sub function + */ + +void cmd_pm_cb(void *phl, void *hdl, void *ctx, enum rtw_phl_status stat) +{ + struct _cmd_obj *pcmd = (struct _cmd_obj *)ctx; + + if (stat == RTW_PHL_STATUS_SUCCESS) + phl_fsm_gen_msg(phl, pcmd->fsm_obj, NULL, 0, CMD_EV_PWR_ON_OK); + else + phl_fsm_gen_msg(phl, pcmd->fsm_obj, NULL, 0, FSM_EV_CANCEL); +} + +int cmd_dequeue_job(struct _cmd_obj *pcmd) +{ + void *d = phl_to_drvpriv(pcmd->phl_info); + struct fsm_msg *msg; + + msg = phl_fsm_dequeue_ext(pcmd->fsm); + if (msg == NULL) + return -1; + + if (phl_fsm_sent_msg(pcmd->fsm_obj, msg) != RTW_PHL_STATUS_SUCCESS) { + if (msg->param && msg->param_sz) + _os_kmem_free(d, (u8 *)msg->param, msg->param_sz); + _os_kmem_free(d, (u8 *)msg, sizeof(*msg)); + return -1; + } + return 0; +} + +static void cmd_do_wdog_job(struct _cmd_obj *pcmd) +{ +#if defined(PHL_PLATFORM_LINUX) + void *d = phl_to_drvpriv(pcmd->phl_info); + struct phl_cmd_job *job; + + /* Tempoary test in Linux, + * make sure Windows doesn't run to here + */ + + _os_mutex_lock(d, &pcmd->wd_q_lock); + phl_list_for_loop(job, struct phl_cmd_job, &pcmd->wd_q, list) { + job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, false); + +#ifdef DEBUG_CMD_FSM_MODULE + FSM_INFO(pcmd->fsm, "%s: wdog %s:%s\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job_name(pcmd, (u8)job->id), + (char *)job->u.cmd.name); +#endif + } + _os_mutex_unlock(d, &pcmd->wd_q_lock); + rtw_phl_watchdog_callback(pcmd->phl_info); +#endif +} + +static void cmd_add_wdog_event(struct _cmd_obj *pcmd) +{ + struct fsm_msg *msg; + + msg = phl_fsm_new_msg(pcmd->fsm_obj, CMD_EV_WD_DO_JOB); + if (msg == NULL) + return; + /* Always enqueue msg to extra queue */ + phl_fsm_enqueue_ext(pcmd->fsm, msg, 0); +} + +/* + * CMD state handler + */ + +/* + * cmd idle handler + * This state has no power; Able to run no_io job + * For jobs don't need to request power (no_io job) + */ +static int cmd_idle_st_hdl(void *obj, u16 event, void *param) +{ + struct _cmd_obj *pcmd = (struct _cmd_obj *)obj; + int rtn = FSM_FREE_PARAM; + + /* has no power */ + switch (event) { + case FSM_EV_SWITCH_IN: + phl_fsm_set_alarm_ext(pcmd->fsm_obj, + WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL); + break; + + case FSM_EV_STATE_IN: + break; + + case CMD_EV_WD_EXPIRE: + + /* restart watchdog alarm */ + phl_fsm_set_alarm_ext(pcmd->fsm_obj, + WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL); + + if (pcmd->wdog_pwr_level < PWR_BASIC_IO) { + cmd_do_wdog_job(pcmd); + break; + } + /* We need to request power */ + cmd_add_wdog_event(pcmd); + + /* fall through */ + + case CMD_EV_REQ_PWR: + phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_REQ_PWR); + break; + + case CMD_EV_JOB_NOTIFY: + cmd_dequeue_job(pcmd); + break; + + case CMD_EV_DO_JOB: + /* TODO check MUST BE no_io cmd */ + rtn = phl_cmd_do_job(pcmd, param); + break; + + case FSM_EV_STATE_OUT: + break; + + case FSM_EV_SWITCH_OUT: + phl_fsm_cancel_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID); + break; + + default: + break; + } + return rtn; +} + +/* This stete is designed to request power */ +static int cmd_req_pwr_st_hdl(void *obj, u16 event, void *param) +{ + struct _cmd_obj *pcmd = (struct _cmd_obj *)obj; + struct fsm_msg *msg; + int rtn = FSM_FREE_PARAM; + enum rtw_phl_status phl_st; + + switch (event) { + case FSM_EV_STATE_IN: + + /* TODO: request power */ + phl_st = RTW_PHL_STATUS_SUCCESS; + + if (phl_st == RTW_PHL_STATUS_PENDING) { + /* we have to wait CMD_EV_PWR_ON_OK */ + phl_fsm_set_alarm(pcmd->fsm_obj, + MAX_POWER_ON_TIME, CMD_EV_PWR_ON_TIMEOUT); + break; + } + + if (phl_st != RTW_PHL_STATUS_SUCCESS) { + FSM_ERR(pcmd->fsm, "%s: power on fail(%d)\n", + phl_fsm_obj_name(pcmd->fsm_obj), phl_st); + phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE); + + /* drop fail cmd */ + msg = phl_fsm_dequeue_ext(pcmd->fsm); + if (msg != NULL) + cmd_discard_msg_job(pcmd, msg); + break; + } + + /* RTW_PHL_STATUS_SUCCESS */ + /* fall through */ + + case CMD_EV_PWR_ON_OK: + pcmd->has_power = true; + phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_SERVICE); + break; + + case CMD_EV_PWR_ON_TIMEOUT: + case FSM_EV_CANCEL: + phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE); + break; + + case CMD_EV_WD_EXPIRE: + /* restart watchdog alarm */ + phl_fsm_set_alarm_ext(pcmd->fsm_obj, + WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL); + + /* enqueue watchdog job */ + cmd_add_wdog_event(pcmd); + break; + + case FSM_EV_STATE_OUT: + phl_fsm_cancel_alarm(pcmd->fsm_obj); + break; + + default: + break; + } + return rtn; +} + +/* This state has basic power supply. + * Able to do both PWR_BASIC_IO and PWR_NO_IO jobs. + */ + +static int cmd_service_st_hdl(void *obj, u16 event, void *param) +{ + struct _cmd_obj *pcmd = (struct _cmd_obj *)obj; + struct phl_cmd_job *job; + int rtn = FSM_FREE_PARAM; + + switch (event) { + case FSM_EV_STATE_IN: + case CMD_EV_JOB_NOTIFY: + cmd_dequeue_job(pcmd); + break; + + case CMD_EV_DO_JOB: + + rtn = phl_cmd_do_job(pcmd, param); + + /* hold power for a while */ + job = (struct phl_cmd_job *)param; + if (job->pwr_level >= PWR_BASIC_IO) + phl_fsm_set_alarm(pcmd->fsm_obj, + MAX_POWER_ON_TIME, CMD_EV_PWR_EXPIRE); + + /* dequeue jobs */ + cmd_dequeue_job(pcmd); + break; + + case CMD_EV_WD_EXPIRE: + case CMD_EV_WD_DO_JOB: + + cmd_do_wdog_job(pcmd); + + /* hold power for a while */ + phl_fsm_set_alarm(pcmd->fsm_obj, + MAX_POWER_ON_TIME, CMD_EV_PWR_EXPIRE); + + /* restart watchdog alarm */ + phl_fsm_set_alarm_ext(pcmd->fsm_obj, + WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL); + break; + + case CMD_EV_PWR_EXPIRE: + + /* make sure no more commands */ + if (cmd_dequeue_job(pcmd) >= 0) + break; + + /* no more commands */ + /* fall through */ + + case FSM_EV_CANCEL: + phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE); + break; + + case FSM_EV_STATE_OUT: + phl_fsm_cancel_alarm(pcmd->fsm_obj); + pcmd->has_power = false; + break; + + default: + break; + } + return rtn; +} + +static void cmd_dump_obj(void *obj, char *p, int *sz) +{ + /* nothing to do for now */ +} + +static void cmd_dump_fsm(void *fsm, char *p, int *sz) +{ + /* nothing to do for now */ +} + +static void cmd_dbg_help(struct _cmd_obj *pcmd, char *p, int *sz) +{ + int len = *sz; + + _os_snprintf(pstr(p), lstr(p, len), + "usage:\n\t<%s> ,\n", + phl_fsm_obj_name(pcmd->fsm_obj)); + *sz = len; +} + +static void cmd_debug(void *obj, char input[][MAX_ARGV], u32 input_num, + char *output, u32 *out_len) +{ + struct _cmd_obj *pcmd = (struct _cmd_obj *)obj; + char *ptr = output; + int len = *out_len; + + if (input_num < 2) { + cmd_dbg_help(pcmd, ptr, &len); + goto done; + } + + if (!_os_strcmp(input[0], "wdog")) { + if (!_os_strcmp(input[1], "pause")) { + /* wdog,pause */ + rtw_phl_cmd_pause_wdog(pcmd->phl_info, "debug cmd"); + + _os_snprintf(pstr(ptr), lstr(ptr, len), + "\n%s: pause watchdog\n", + phl_fsm_obj_name(pcmd->fsm_obj)); + + } else if (!_os_strcmp(input[1], "resume")) { + /* wdog,resume */ + rtw_phl_cmd_resume_wdog(pcmd->phl_info, "debug cmd"); + _os_snprintf(pstr(ptr), lstr(ptr, len), + "\n%s: resume watchdog\n", + phl_fsm_obj_name(pcmd->fsm_obj)); + } + } else + cmd_dbg_help(pcmd, ptr, &len); +done: + *out_len = len; +} + +/* return value + * 0: timeout + * >0: success + */ +static int wait_completion(void *d, struct phl_cmd_job *job, int m_sec) +{ + job->wait.max_wait_time = m_sec; + job->wait.submit_time = _os_get_cur_time_ms(); + + _os_event_init(d, &(job->wait.done)); + + /* wait here */ + return _os_event_wait(d, &(job->wait.done), m_sec); +} + +/* For EXTERNAL application to create a cmd FSM */ +/* @root: FSM root structure + * @phl_info: private data structure to invoke hal/phl function + * + * return + * fsm_main: FSM main structure (Do NOT expose) + */ +struct fsm_main *phl_cmd_new_fsm(struct fsm_root *root, + struct phl_info_t *phl_info) +{ + void *d = phl_to_drvpriv(phl_info); + struct fsm_main *fsm = NULL; + struct rtw_phl_fsm_tb tb; + + + _os_mem_set(d, &tb, 0, sizeof(tb)); + tb.max_state = sizeof(cmd_state_tbl)/sizeof(cmd_state_tbl[0]); + tb.max_event = sizeof(cmd_event_tbl)/sizeof(cmd_event_tbl[0]); + tb.state_tbl = cmd_state_tbl; + tb.evt_tbl = cmd_event_tbl; + tb.dump_obj = cmd_dump_obj; + tb.dump_fsm = cmd_dump_fsm; + tb.dbg_level = FSM_DBG_WARN; + tb.evt_level = FSM_DBG_WARN; + tb.debug = cmd_debug; + + fsm = phl_fsm_init_fsm(root, "cmd", phl_info, &tb); + + return fsm; +} + +/* For EXTERNAL application to destory cmd fsm */ +/* @fsm: see fsm_main + */ +void phl_cmd_destory_fsm(struct fsm_main *fsm) +{ + if (fsm == NULL) + return; + + /* deinit fsm local variable if has */ + + /* call FSM Framewro to deinit fsm */ + phl_fsm_deinit_fsm(fsm); +} + +/* For EXTERNAL application to create command object */ +/* @fsm: FSM main structure which created by phl_cmd_new_fsm() + * @phl_info: private data structure to invoke hal/phl function + * + * return + * _cmd_obj: structure of command object (Do NOT expose) + */ +struct _cmd_obj *phl_cmd_new_obj(struct fsm_main *fsm, + struct phl_info_t *phl_info) +{ + void *d = phl_to_drvpriv(phl_info); + struct fsm_obj *obj; + struct _cmd_obj *pcmd; + + + pcmd = phl_fsm_new_obj(fsm, (void **)&obj, sizeof(*pcmd)); + + if (pcmd == NULL) { + FSM_ERR(fsm, "cmd: malloc obj fail\n"); + return NULL; + } + pcmd->fsm = fsm; + pcmd->fsm_obj = obj; + pcmd->phl_info = phl_info; + pcmd->has_power = false; + + cmd_set_job_tbl(pcmd); + INIT_LIST_HEAD(&pcmd->wd_q); + _os_mutex_init(d, &pcmd->wd_q_lock); + + return pcmd; +} + +/* For EXTERNAL application to destory command object */ +/* @pcmd: local created command object + * + */ +void phl_cmd_destory_obj(struct _cmd_obj *pcmd) +{ + void *d; + struct phl_cmd_job *job, *job_t; + + if (pcmd == NULL) + return; + + d = phl_to_drvpriv(pcmd->phl_info); + + /* deinit and free all local variables */ + + /* watchdog job */ + /* TODO spin lock is not necessary */ + phl_list_for_loop_safe(job, job_t, + struct phl_cmd_job, &pcmd->wd_q, list) { + + _os_mutex_lock(d, &pcmd->wd_q_lock); + list_del(&job->list); + _os_mutex_unlock(d, &pcmd->wd_q_lock); + + if (job->id == JOB_RUN_FUNC) { + + if (job->u.cmd.parm && job->u.cmd.parm_sz != 0) + _os_kmem_free(d, (u8 *)job->u.cmd.parm, + job->u.cmd.parm_sz); + _os_kmem_free(d, (u8 *)job, sizeof(*job)); + + } else { + FSM_ERR(pcmd->fsm, "%s: free wdog %s fail\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job_name(pcmd, (u8)job->id)); + } + } + _os_mutex_deinit(d, &pcmd->wd_q_lock); + + /* inform FSM framewory to recycle fsm_obj */ + phl_fsm_destory_obj(pcmd->fsm_obj); +} + +/* For EXTERNAL application to pause all watchdog jobs (expose) */ +/* @phl: phl private structure + * @reason: reason for pause watchdog (option) + */ +enum rtw_phl_status rtw_phl_cmd_pause_wdog(void *phl, char *reason) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct _cmd_obj *pcmd = phl_info->cmd_obj; + + phl_fsm_pause_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID); + pcmd->wdog_pause_num++; + + FSM_INFO(pcmd->fsm, "%s: pause wdog (%s) %d\n", + phl_fsm_obj_name(pcmd->fsm_obj), + (reason == NULL) ? "" : reason, pcmd->wdog_pause_num); + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to resume all watchdog jobs (expose) */ +/* @phl: phl private structure + * @reason: reason for resume watchdog (option) + */ +enum rtw_phl_status rtw_phl_cmd_resume_wdog(void *phl, char *reason) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct _cmd_obj *pcmd = phl_info->cmd_obj; + + FSM_INFO(pcmd->fsm, "%s: resume wdog (%s) %d\n", + phl_fsm_obj_name(pcmd->fsm_obj), + (reason == NULL) ? "" : reason, pcmd->wdog_pause_num); + + if (pcmd->wdog_pause_num == 0) + return RTW_PHL_STATUS_FAILURE; + + if (--(pcmd->wdog_pause_num) != 0) + return RTW_PHL_STATUS_SUCCESS; + + /* reset timer to original period */ + phl_fsm_set_alarm_ext(pcmd->fsm_obj, + WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL); + + phl_fsm_resume_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID); + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to register watchdog job (expose) */ +/* @phl: phl private structure + * @func: function pointer to be runed + * @priv: 1st param of function pointer + * @parm: 2nd param of function pointer + * @name: function name for debug message (optional) + * @pwr: refers to enum PWR_LEVEL + */ +enum rtw_phl_status rtw_phl_job_reg_wdog(void *phl, + int (*fptr)(void *priv, void *param, bool discard), + void *priv, void *parm, int parm_sz, char *name, enum PWR_LEVEL pwr) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct _cmd_obj *pcmd = phl_info->cmd_obj; + struct phl_cmd_job *job; + void *d = phl_to_drvpriv(phl_info); + char wd[] = "wdog"; + + if (phl_info->cmd_obj == NULL) { + PHL_ERR("cmd: %s fsm module doesn't init \n", __func__); + return -1; + } + + /* allocate memory for job parameter */ + job = _os_kmem_alloc(d, sizeof(*job)); + if (job == NULL) { + FSM_ERR(pcmd->fsm, "%s: alloc wdog job fail\n", + phl_fsm_obj_name(pcmd->fsm_obj)); + return RTW_PHL_STATUS_RESOURCE; + } + + _os_mem_set(d, job, 0, sizeof(job)); + job->id = JOB_RUN_FUNC; + job->pwr_level = pwr; + job->u.cmd.fptr = fptr; + job->u.cmd.priv = priv; + job->u.cmd.parm = parm; + job->u.cmd.parm_sz = parm_sz; + _os_mem_set(d, job->u.cmd.name, 0, RTW_PHL_JOB_NAME_LEN); + if (name != NULL) + _os_mem_cpy(d, job->u.cmd.name, name, + MIN((RTW_PHL_JOB_NAME_LEN - 1), + _os_strlen((u8 *)name))); + else + _os_mem_cpy(d, job->u.cmd.name, wd, + MIN((RTW_PHL_JOB_NAME_LEN - 1), + _os_strlen((u8 *)wd))); + + pcmd->wdog_pwr_level = (u8)MAX(pwr, pcmd->wdog_pwr_level); + + _os_mutex_lock(d, &pcmd->wd_q_lock); + list_add_tail(&job->list, &pcmd->wd_q); + _os_mutex_unlock(d, &pcmd->wd_q_lock); + + FSM_INFO(pcmd->fsm, "%s: wdog hooks %s, pwr_level = %d\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job->u.cmd.name, pwr); + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to invoke command service (expose) */ +/* @pcmd: cmd object + * @msg: refert to struct fsm_msg + */ +enum rtw_phl_status phl_cmd_enqueue_and_wait_job(struct _cmd_obj *pcmd, + struct fsm_msg *msg) +{ + struct phl_cmd_job *job = (struct phl_cmd_job *)msg->param; + void *d = phl_to_drvpriv(pcmd->phl_info); + int max_wait_time = 1000; + int remain = 0; + +#if 0 + FSM_INFO(pcmd->fsm, "%s: enqueue %s:%s\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job_name(pcmd, (u8)job->id), (char *)job->u.cmd.name); +#endif + /* Always enqueue msg to extra queue */ + phl_fsm_enqueue_ext(pcmd->fsm, msg, 0); + + if ((pcmd->has_power == false) && (job->pwr_level >= PWR_BASIC_IO)) + /* request power */ + phl_fsm_gen_msg(pcmd->phl_info, + pcmd->fsm_obj, NULL, 0, CMD_EV_REQ_PWR); + else + phl_fsm_gen_msg(pcmd->phl_info, + pcmd->fsm_obj, NULL, 0, CMD_EV_JOB_NOTIFY); + + if (job->wait.sync == JOB_WAIT_COMPLETION) { + + job->wait.result = JOB_SUCCESS; + /* WAIT completion; context switch */ + remain = wait_completion(d, job, max_wait_time); + if (remain == 0) { + job->wait.result = JOB_TIMEOUT; + FSM_WARN(pcmd->fsm, "job: %s timeout %d ms\n", + job_name(pcmd, (u8)job->id), max_wait_time); + return RTW_PHL_STATUS_FAILURE; + } + } + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to invoke command service (expose) */ +/* @phl: refer to struct phl_info_t + * @pjob: job to be completed + */ +enum rtw_phl_status phl_cmd_complete_job(void *phl, struct phl_cmd_job *pjob) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct _cmd_obj *pcmd = phl_info->cmd_obj; + struct phl_cmd_job *job; + struct fsm_msg *msg; + void *d = phl_to_drvpriv(pcmd->phl_info); + + if (pjob == NULL) + return RTW_PHL_STATUS_FAILURE; + +#ifdef HAS_NO_COMPLETION + if (pjob->wait.sync == JOB_WAIT_COMPLETION) { + pjob->wait.sync = JOB_ASYNC; + FSM_ERR(pcmd->fsm, + "cmd: %s doesn't support SYNC mdoe use ASYNC mode\n", + job_name(pcmd, (u8)pjob->id)); + } +#endif + /* NEW message to start cmd service */ + msg = phl_fsm_new_msg(pcmd->fsm_obj, CMD_EV_DO_JOB); + if (msg == NULL) { + FSM_ERR(pcmd->fsm, "cmd: alloc msg fail\n"); + return RTW_PHL_STATUS_RESOURCE; + } + + /* allocate memory for command parameter */ + if (pjob->wait.sync == JOB_WAIT_COMPLETION) { + /* TODO check interrupt context */ + /* SYNC mode, use call loacl job varable */ + job = pjob; + } else { + /* ASYNC mode */ + /* allocate memory for command parameter */ + job = _os_kmem_alloc(d, sizeof(*job)); + if (job == NULL) { + FSM_ERR(pcmd->fsm, "cmd: alloc job fail\n"); + _os_kmem_free(d, (u8 *)msg, sizeof(*msg)); + return RTW_PHL_STATUS_RESOURCE; + } + _os_mem_cpy(d, job, pjob, sizeof(*job)); + } + msg->param = (void *)job; + msg->param_sz = sizeof(*job); + + return phl_cmd_enqueue_and_wait_job(pcmd, msg); +} + +/* For EXTERNAL application to start command service (expose) */ +/* @pcmd: cmd object + */ +enum rtw_phl_status phl_cmd_start(struct _cmd_obj *pcmd) +{ + /* Start FSM */ + return phl_fsm_start_fsm(pcmd->fsm); +} + +/* For EXTERNAL application to stop cmd obj + * @phl_info: private data structure to invoke hal/phl function + * + */ +void phl_fsm_cmd_stop(struct phl_info_t *phl_info) +{ + struct _cmd_obj *pcmd = phl_info->cmd_obj; + //void *d = phl_to_drvpriv(pcmd->phl_info); + struct phl_cmd_job *job; + struct fsm_msg *msg; + + while ((msg = phl_fsm_dequeue_ext(pcmd->fsm)) != NULL) { + job = (struct phl_cmd_job *)msg->param; + cmd_discard_msg_job(pcmd, msg); + } + + phl_fsm_stop_fsm(phl_info->cmd_fsm); +} + +/* For EXTERNAL application to stop cmd service (expose) */ +/* @pcmd: cmd job will be cancelled + */ +enum rtw_phl_status phl_cmd_cancel(struct _cmd_obj *pcmd) +{ +#ifdef PHL_INCLUDE_FSM + return phl_fsm_cancel_obj(pcmd->fsm_obj); +#else + return RTW_PHL_STATUS_FAILURE; +#endif /* PHL_INCLUDE_FSM */ +} +#endif /*CONFIG_FSM*/ + diff --git a/phl/phl_cmd_fsm.h b/phl/phl_cmd_fsm.h new file mode 100644 index 0000000..fb0706a --- /dev/null +++ b/phl/phl_cmd_fsm.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_CMD_FSM_H__ +#define __PHL_CMD_FSM_H__ + +#include "phl_cmd_job.h" + +/* Header file for application to invoke command service */ + +struct phl_cmd_job; +struct job_hdl_ent; +struct fsm_root; +struct fsm_main; +struct _cmd_obj; + +struct _cmd_obj { + struct fsm_main *fsm; + struct phl_info_t *phl_info; + struct fsm_obj *fsm_obj; + struct job_hdl_ent *job_tbl; + + u8 wdog_pwr_level; + u32 wdog_pause_num; + bool has_power; + + struct list_head wd_q; + _os_mutex wd_q_lock; +}; + +/* function form command service management */ +struct fsm_main *phl_cmd_new_fsm(struct fsm_root *fsm_m, + struct phl_info_t *phl_info); +void phl_cmd_destory_fsm(struct fsm_main *fsm); +struct _cmd_obj *phl_cmd_new_obj(struct fsm_main *fsm, + struct phl_info_t *phl_info); +void phl_cmd_destory_obj(struct _cmd_obj *pcmd); +void phl_fsm_cmd_stop(struct phl_info_t *phl_info); + +/* function form command service */ +enum rtw_phl_status phl_cmd_start(struct _cmd_obj *pcmd); +enum rtw_phl_status phl_cmd_cancel(struct _cmd_obj *pcmd); + +#endif /* __PHL_CMD_FSM_H__ */ + diff --git a/phl/phl_cmd_general.c b/phl/phl_cmd_general.c new file mode 100644 index 0000000..5aed83c --- /dev/null +++ b/phl/phl_cmd_general.c @@ -0,0 +1,658 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_GENERAL_C_ +#include "phl_headers.h" + +#ifdef CONFIG_CMD_DISP + +enum phl_cmd_sts { + PHL_CMD_SUBMITTED = -1, + PHL_CMD_DONE_SUCCESS = 0, + PHL_CMD_DONE_TIMEOUT, + PHL_CMD_DONE_CMD_ERROR, + PHL_CMD_DONE_CMD_DROP, + PHL_CMD_DONE_CANNOT_IO, + PHL_CMD_DONE_UNKNOWN, +}; + +struct phl_sync { + u32 submit_time; + u32 timeout_ms; /* 0: wait forever, >0: up to ms waiting */ + enum phl_cmd_sts status; /* status for operation */ + _os_event done; +}; + +struct phl_cmd_sync { + enum phl_msg_evt_id evt_id; + struct phl_sync sync; + _os_lock lock; +}; + +struct phl_cmd_obj { + enum phl_msg_evt_id evt_id; /* u8 id */ + u8 *buf; + u32 buf_len; + bool no_io; + void (*cmd_complete)(void* priv, u8 *buf, u32 buf_len, enum rtw_phl_status status); + /*cmd sync*/ + bool is_cmd_wait; + _os_atomic ref_cnt; + struct phl_cmd_sync cmd_sync; +}; + + +#define DBG_CMD_SYNC + +#ifdef DBG_CMD_SYNC +static void _phl_cmd_sync_dump(struct phl_cmd_sync *cmd_sync, const char *caller) +{ + PHL_INFO("[CMD_SYNC] %s\n", caller); + PHL_INFO("[CMD_SYNC] evt_id:%d status:%d\n", cmd_sync->evt_id, cmd_sync->sync.status); + PHL_INFO("[CMD_SYNC] take:%d ms\n", phl_get_passing_time_ms(cmd_sync->sync.submit_time)); +} +#endif + +static void _phl_cmd_sync_init(struct phl_info_t *phl_info, + enum phl_msg_evt_id evt_id, + struct phl_cmd_sync *cmd_sync, u32 timeout_ms) +{ + void *drv = phl_to_drvpriv(phl_info); + + _os_spinlock_init(drv, &cmd_sync->lock); + cmd_sync->evt_id = evt_id; + cmd_sync->sync.timeout_ms = timeout_ms; + cmd_sync->sync.submit_time = _os_get_cur_time_ms(); + _os_event_init(drv, &(cmd_sync->sync.done)); + cmd_sync->sync.status = PHL_CMD_SUBMITTED; +} + +static void _phl_cmd_sync_deinit(struct phl_info_t *phl_info, + struct phl_cmd_sync *cmd_sync) +{ + #ifdef DBG_CMD_SYNC + _phl_cmd_sync_dump(cmd_sync, __func__); + #endif + _os_event_free(phl_to_drvpriv(phl_info), &(cmd_sync->sync.done)); + _os_spinlock_free(phl_to_drvpriv(phl_info), &cmd_sync->lock); +} + +inline static enum rtw_phl_status _cmd_stat_2_phl_stat(enum phl_cmd_sts status) +{ + if (status == PHL_CMD_DONE_TIMEOUT) + return RTW_PHL_STATUS_CMD_TIMEOUT; + else if(status == PHL_CMD_DONE_CANNOT_IO) + return RTW_PHL_STATUS_CMD_CANNOT_IO; + else if (status == PHL_CMD_DONE_CMD_ERROR) + return RTW_PHL_STATUS_CMD_ERROR; + else if (status == PHL_CMD_DONE_CMD_DROP) + return RTW_PHL_STATUS_CMD_DROP; + else + return RTW_PHL_STATUS_CMD_SUCCESS; +} + +static enum rtw_phl_status +_phl_cmd_wait(struct phl_info_t *phl_info, struct phl_cmd_sync *cmd_sync) +{ + void *drv = phl_to_drvpriv(phl_info); + u32 cmd_wait_ms = cmd_sync->sync.timeout_ms;/*0: wait forever, >0: up to ms waiting*/ + + #ifdef DBG_CMD_SYNC + PHL_INFO("evt_id:%d %s in...............\n", cmd_sync->evt_id, __func__); + #endif + + if (_os_event_wait(drv, &cmd_sync->sync.done, cmd_wait_ms) == 0) { + _os_spinlock(drv, &cmd_sync->lock, _bh, NULL); + cmd_sync->sync.status = PHL_CMD_DONE_TIMEOUT; + _os_spinunlock(drv, &cmd_sync->lock, _bh, NULL); + PHL_ERR("%s evt_id:%d timeout\n", __func__, cmd_sync->evt_id); + } + #ifdef DBG_CMD_SYNC + PHL_INFO("evt_id:%d %s out...............\n", cmd_sync->evt_id, __func__); + _phl_cmd_sync_dump(cmd_sync, __func__); + #endif + return _cmd_stat_2_phl_stat(cmd_sync->sync.status); +} + +static bool _phl_cmd_chk_wating_status(enum phl_cmd_sts status) +{ + switch (status) { + case PHL_CMD_SUBMITTED: + /* fall through */ + case PHL_CMD_DONE_UNKNOWN: + return true; + default: + return false; + } +} + +static void _phl_cmd_done(struct phl_info_t *phl_info, + struct phl_cmd_sync *cmd_sync, enum phl_cmd_sts status) +{ + void *drv = phl_to_drvpriv(phl_info); + + if (!cmd_sync) { + PHL_ERR("%s cmd_sync is NULL\n", __func__); + _os_warn_on(1); + return; + } + #ifdef DBG_CMD_SYNC + PHL_INFO("evt_id:%d %s in...............\n", cmd_sync->evt_id, __func__); + #endif + _os_spinlock(drv, &cmd_sync->lock, _bh, NULL); + if (_phl_cmd_chk_wating_status(cmd_sync->sync.status)) { + PHL_INFO("%s status:%d\n", __func__, status); + cmd_sync->sync.status = status; + } + _os_spinunlock(drv, &cmd_sync->lock, _bh, NULL); + + _os_event_set(drv, &cmd_sync->sync.done); + #ifdef DBG_CMD_SYNC + PHL_INFO("evt_id:%d %s out...............\n", cmd_sync->evt_id, __func__); + _phl_cmd_sync_dump(cmd_sync, __func__); + #endif +} +/********************************************************/ +static enum rtw_phl_status +_phl_cmd_general_pre_phase_msg_hdlr(struct phl_info_t *phl_info, void *dispr, + struct phl_msg *msg) +{ + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_obj *phl_cmd = NULL; + + phl_cmd = (struct phl_cmd_obj *)msg->inbuf; + + switch (evt_id) { + case MSG_EVT_DBG_RX_DUMP: + /* Do Nothing */ + psts = RTW_PHL_STATUS_SUCCESS; + break; + case MSG_EVT_NONE: + /* fall through */ + default: + psts = RTW_PHL_STATUS_SUCCESS; + break; + } + + return psts; +} + +static enum rtw_phl_status +_phl_cmd_general_post_phase_msg_hdlr(struct phl_info_t *phl_info, void *dispr, + struct phl_msg *msg) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + struct phl_cmd_obj *phl_cmd = NULL; + + phl_cmd = (struct phl_cmd_obj *)msg->inbuf; + + switch (evt_id) { + case MSG_EVT_CHG_OP_CH_DEF_START: + psts = phl_cmd_chg_op_chdef_start_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_SWCH_START: + psts = phl_cmd_set_ch_bw_hdl(phl_info, phl_cmd->buf); + break; + + #if defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN) + case MSG_EVT_PCIE_TRX_MIT: + psts = phl_evt_pcie_trx_mit_hdlr(phl_info, phl_cmd->buf); + break; + #endif + case MSG_EVT_DBG_RX_DUMP: + { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> %s : MSG_EVT_DBG_RX_DUMP\n", __func__); + rtw_hal_notification(phl_info->hal, MSG_EVT_DBG_RX_DUMP, HW_PHY_0); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== %s : MSG_EVT_DBG_RX_DUMP\n", __func__); + psts = RTW_PHL_STATUS_SUCCESS; + } + break; + case MSG_EVT_WATCHDOG: + { + if (IS_MSG_CANNOT_IO(msg->msg_id)) + psts = RTW_PHL_STATUS_CANNOT_IO; + else if (IS_MSG_FAIL(msg->msg_id)) + psts = RTW_PHL_STATUS_FAILURE; + else if (IS_MSG_CANCEL(msg->msg_id)) + psts = RTW_PHL_STATUS_FAILURE; + else + psts = RTW_PHL_STATUS_SUCCESS; + psts = phl_watchdog_cmd_hdl(phl_info, psts); + } + break; + +#if defined(CONFIG_USB_HCI) + case MSG_EVT_FORCE_USB_SW: + psts = phl_force_usb_switch(phl_info, *(u32*)(phl_cmd->buf)); + break; + case MSG_EVT_GET_USB_SPEED: + psts = phl_get_cur_usb_speed(phl_info, (u32*)(phl_cmd->buf)); + break; + case MSG_EVT_GET_USB_SW_ABILITY: + psts = phl_get_usb_support_ability(phl_info, (u32*)(phl_cmd->buf)); + break; +#endif + case MSG_EVT_CFG_AMPDU: + psts = phl_cmd_cfg_ampdu_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_DFS_PAUSE_TX: + psts = phl_cmd_dfs_tx_pause_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_ROLE_RECOVER: + psts = phl_role_recover(phl_info); + break; + case MSG_EVT_ROLE_SUSPEND: + psts = phl_role_suspend(phl_info); + break; + +#if defined(CONFIG_PCI_HCI) + case MSG_EVT_HAL_SET_L2_LEAVE: + if (rtw_hal_set_l2_leave(phl_info->hal) == RTW_HAL_STATUS_SUCCESS) + psts = RTW_PHL_STATUS_SUCCESS; + break; +#endif + + case MSG_EVT_NOTIFY_HAL: + psts = phl_notify_cmd_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_ISSUE_BCN: +#ifdef RTW_PHL_BCN + psts = phl_cmd_issue_bcn_hdl(phl_info, phl_cmd->buf); +#endif + break; + case MSG_EVT_STOP_BCN: +#ifdef RTW_PHL_BCN + psts = phl_cmd_stop_bcn_hdl(phl_info, phl_cmd->buf); +#endif + break; + + case MSG_EVT_SEC_KEY: + psts = phl_cmd_set_key_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_ROLE_START: + psts = phl_wifi_role_start_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_ROLE_CHANGE: + psts = phl_wifi_role_chg_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_ROLE_STOP: + psts = phl_wifi_role_stop_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_STA_INFO_CTRL: + psts = phl_cmd_alloc_stainfo_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_STA_MEDIA_STATUS_UPT: + psts = phl_update_media_status_hdl(phl_info, phl_cmd->buf); + break; + + case MSG_EVT_CFG_CHINFO: +#ifdef CONFIG_PHL_CHANNEL_INFO + psts = phl_cmd_cfg_chinfo_hdl(phl_info, phl_cmd->buf); +#endif + break; + + case MSG_EVT_STA_CHG_STAINFO: + psts = phl_cmd_change_stainfo_hdl(phl_info, phl_cmd->buf); + break; + + default: + psts = RTW_PHL_STATUS_SUCCESS; + break; + } + + return psts; +} + +static enum phl_mdl_ret_code _phl_cmd_general_init(void *phl, void *dispr, + void **priv) +{ + *priv = phl; + return MDL_RET_SUCCESS; +} + +static void _phl_cmd_general_deinit(void *dispr, void *priv) +{ + +} + +static enum phl_mdl_ret_code _phl_cmd_general_start(void *dispr, void *priv) +{ + u8 dispr_idx = 0; + + if (RTW_PHL_STATUS_SUCCESS != phl_dispr_get_idx(dispr, &dispr_idx)) + return MDL_RET_FAIL; + + #if defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN) + { + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + + if (RTW_PHL_STATUS_SUCCESS != + phl_pcie_trx_mit_start(phl_info, dispr_idx)) + return MDL_RET_FAIL; + } + #endif + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _phl_cmd_general_stop(void *dispr, void *priv) +{ + return MDL_RET_SUCCESS; +} + +static void _fail_evt_hdlr(void *dispr, void *priv, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + u8 idx = 0; +#ifdef CONFIG_POWER_SAVE + struct phl_module_op_info op_info = {0}; +#endif + + phl_dispr_get_idx(dispr, &idx); + + switch (evt_id) { + case MSG_EVT_WATCHDOG: + /* watchdog do not need to handle fail case */ + PHL_DBG("%s do simple watchdog!\n", __func__); + rtw_hal_simple_watchdog(phl_info->hal, false); + break; + default: +#ifdef CONFIG_POWER_SAVE + op_info.op_code = PS_MDL_OP_CANCEL_PWR_REQ; + op_info.inbuf = (u8 *)&evt_id; + phl_disp_eng_set_bk_module_info(phl_info, idx, + PHL_MDL_POWER_MGNT, &op_info); +#endif + break; + } +} + +static enum phl_mdl_ret_code _phl_cmd_general_msg_hdlr(void *dispr, void *priv, + struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + + if (IS_MSG_FAIL(msg->msg_id)) { + + PHL_INFO("%s :: MDL_ID(%d)_FAIL - MSG_EVT_ID=%d \n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), + MSG_EVT_ID_FIELD(msg->msg_id)); + + _fail_evt_hdlr(dispr, priv, msg); + + return MDL_RET_FAIL; + } + + if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_MDL_GENERAL) + return MDL_RET_IGNORE; + + /* + * GENERAL is optional module, msg pass through mandatory module, + * optional module, and wifi role(protocol). So msg shall be handled + * at post phase to make sure that wifi role is at valid state + * if the msg is relative to wifi role(protocol) + */ + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + status = + _phl_cmd_general_pre_phase_msg_hdlr(phl_info, dispr, msg); + else + status = + _phl_cmd_general_post_phase_msg_hdlr(phl_info, dispr, msg); + + if (status != RTW_PHL_STATUS_SUCCESS) + return MDL_RET_FAIL; + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_phl_cmd_general_set_info(void *dispr, void *priv, + struct phl_module_op_info *info) +{ + return MDL_RET_SUCCESS; +} + +enum rtw_phl_status +phl_cmd_get_cur_cmdinfo(struct phl_info_t *phl_info, + u8 band_idx, + struct phl_msg *msg, + u8 **cmd, + u32 *cmd_len) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_obj *phl_cmd = NULL; + + phl_cmd = (struct phl_cmd_obj *)msg->inbuf; + if (NULL != phl_cmd) { + *cmd = phl_cmd->buf; + *cmd_len = phl_cmd->buf_len; + psts = RTW_PHL_STATUS_SUCCESS; + } + + return psts; +} + +static enum phl_mdl_ret_code +_phl_cmd_general_query_info(void *dispr, void *priv, + struct phl_module_op_info *info) +{ + return MDL_RET_SUCCESS; +} + +enum rtw_phl_status phl_register_cmd_general(struct phl_info_t *phl_info) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng); + struct phl_bk_module_ops bk_ops; + u8 band_idx = 0; + + bk_ops.init = _phl_cmd_general_init; + bk_ops.deinit = _phl_cmd_general_deinit; + bk_ops.start = _phl_cmd_general_start; + bk_ops.stop = _phl_cmd_general_stop; + bk_ops.msg_hdlr = _phl_cmd_general_msg_hdlr; + bk_ops.set_info = _phl_cmd_general_set_info; + bk_ops.query_info = _phl_cmd_general_query_info; + + for (band_idx = 0; band_idx < disp_eng->phy_num; band_idx++) { + status = phl_disp_eng_register_module(phl_info, band_idx, + PHL_MDL_GENERAL, &bk_ops); + if (status != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR( + "%s register MDL_GENRAL in cmd disp failed :%d\n", + __func__, band_idx + 1); + break; + } + } + + return status; +} + +static enum rtw_phl_status +_phl_cmd_obj_free(struct phl_info_t *phl_info, struct phl_cmd_obj *phl_cmd) +{ + void *drv = phl_to_drvpriv(phl_info); + + if(phl_cmd == NULL) { + PHL_ERR("%s phl_cmd is NULL\n", __func__); + _os_warn_on(1); + return RTW_PHL_STATUS_FAILURE; + } + + if (phl_cmd->is_cmd_wait == true) + _phl_cmd_sync_deinit(phl_info, &phl_cmd->cmd_sync); + _os_kmem_free(drv, phl_cmd, sizeof(struct phl_cmd_obj)); + phl_cmd = NULL; + return RTW_PHL_STATUS_SUCCESS; +} + +static void _phl_cmd_complete_msg_hdlr(struct phl_info_t *phl_info, + struct phl_msg *msg) +{ + u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + switch (evt_id) { + case MSG_EVT_WATCHDOG: + phl_watchdog_cmd_complete_hdl(phl_info); + break; + default: + break; + } +} + +static void _phl_cmd_complete(void *priv, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + void *drv = phl_to_drvpriv(phl_info); + struct phl_cmd_obj *phl_cmd = (struct phl_cmd_obj *)msg->inbuf; + enum phl_cmd_sts csts = PHL_CMD_DONE_UNKNOWN; + enum rtw_phl_status pstst = RTW_PHL_STATUS_SUCCESS; + + PHL_DBG("%s evt_id:%d\n", __func__, phl_cmd->evt_id); + + /* no matter msg status, must execute complete handler */ + _phl_cmd_complete_msg_hdlr(phl_info, msg); + + if (IS_MSG_CANNOT_IO(msg->msg_id)) + csts = PHL_CMD_DONE_CANNOT_IO; + else if (IS_MSG_FAIL(msg->msg_id)) + csts = PHL_CMD_DONE_CMD_ERROR; + else if (IS_MSG_CANCEL(msg->msg_id)) + csts = PHL_CMD_DONE_CMD_DROP; + else + csts = PHL_CMD_DONE_SUCCESS; + + if (phl_cmd->is_cmd_wait) + _phl_cmd_done(phl_info, &phl_cmd->cmd_sync, csts); + + pstst = _cmd_stat_2_phl_stat(csts); + if (phl_cmd->cmd_complete) + phl_cmd->cmd_complete(drv, phl_cmd->buf, phl_cmd->buf_len, pstst); + + if (phl_cmd->is_cmd_wait) { + #define PHL_MAX_SCHEDULE_TIMEOUT 100000 + u32 try_cnt = 0; + u32 start = _os_get_cur_time_ms(); + + do { + if (_os_atomic_read(drv, &(phl_cmd->ref_cnt)) == 1) + break; + _os_sleep_ms(drv, 10); + try_cnt++; + if (try_cnt == 50) + PHL_ERR("F-%s, L-%d polling is_cmd_wait to false\n", + __FUNCTION__, __LINE__); + } while (phl_get_passing_time_ms(start) < PHL_MAX_SCHEDULE_TIMEOUT); + } + + _phl_cmd_obj_free(phl_info, phl_cmd); +} + +enum rtw_phl_status +phl_cmd_enqueue(struct phl_info_t *phl_info, + enum phl_band_idx band_idx, + enum phl_msg_evt_id evt_id, + u8 *cmd_buf, + u32 cmd_len, + void (*cmd_complete)(void* priv, u8 *buf, u32 buf_len, enum rtw_phl_status status), + enum phl_cmd_type cmd_type, + u32 cmd_timeout) +{ + void *drv = phl_to_drvpriv(phl_info); + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_obj *phl_cmd = NULL; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + phl_cmd = _os_kmem_alloc(drv, sizeof(struct phl_cmd_obj)); + if (phl_cmd == NULL) { + PHL_ERR("%s: alloc phl_cmd failed!\n", __func__); + psts = RTW_PHL_STATUS_RESOURCE; + goto _exit; + } + phl_cmd->evt_id = evt_id; + phl_cmd->buf = cmd_buf; + phl_cmd->buf_len = cmd_len; + phl_cmd->cmd_complete = cmd_complete; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_GENERAL); + SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id); + msg.inbuf = (u8 *)phl_cmd; + msg.inlen = sizeof(struct phl_cmd_obj); + msg.band_idx = band_idx; + attr.completion.completion = _phl_cmd_complete; + attr.completion.priv = phl_info; + + if (cmd_type == PHL_CMD_WAIT) { + phl_cmd->is_cmd_wait = true; + _os_atomic_set(drv, &phl_cmd->ref_cnt, 0); + _phl_cmd_sync_init(phl_info, evt_id, &phl_cmd->cmd_sync, cmd_timeout); + } + + psts = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if (psts == RTW_PHL_STATUS_SUCCESS) { + if (cmd_type == PHL_CMD_WAIT) { + psts = _phl_cmd_wait(phl_info, &phl_cmd->cmd_sync); + /*ref_cnt++ for cmd wait done*/ + _os_atomic_inc(drv, &phl_cmd->ref_cnt); + /* Check wait cmd status */ + if (psts == RTW_PHL_STATUS_CMD_SUCCESS) + psts = RTW_PHL_STATUS_SUCCESS; + } else { + psts = RTW_PHL_STATUS_SUCCESS; + } + } else { + PHL_ERR("%s send msg failed\n", __func__); + _phl_cmd_obj_free(phl_info, phl_cmd); + } + +_exit: + return psts; +} + +enum rtw_phl_status +rtw_phl_cmd_enqueue(void *phl, + enum phl_band_idx band_idx, + enum phl_msg_evt_id evt_id, + u8 *cmd_buf, + u32 cmd_len, + void (*core_cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status), + enum phl_cmd_type cmd_type, + u32 cmd_timeout) +{ + return phl_cmd_enqueue((struct phl_info_t *)phl, + band_idx, + evt_id, + cmd_buf, + cmd_len, + core_cmd_complete, + cmd_type, + cmd_timeout); +} + +#endif /*CONFIG_CMD_DISP*/ + diff --git a/phl/phl_cmd_general.h b/phl/phl_cmd_general.h new file mode 100644 index 0000000..4576723 --- /dev/null +++ b/phl/phl_cmd_general.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CMD_GENERAL_H_ +#define _PHL_CMD_GENERAL_H_ + +enum rtw_phl_status +phl_cmd_get_cur_cmdinfo(struct phl_info_t *phl_info, + u8 band_idx, + struct phl_msg *msg, + u8 **cmd, u32 *cmd_len); + +enum rtw_phl_status phl_register_cmd_general(struct phl_info_t *phl_info); + +enum rtw_phl_status +phl_cmd_enqueue(struct phl_info_t *phl_info, + enum phl_band_idx band_idx, + enum phl_msg_evt_id evt_id, + u8 *cmd_buf, + u32 cmd_len, + void (*cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status), + enum phl_cmd_type cmd_type, + u32 cmd_timeout); +#endif /*_PHL_CMD_GENERAL_H_*/ diff --git a/phl/phl_cmd_job.c b/phl/phl_cmd_job.c new file mode 100644 index 0000000..0952576 --- /dev/null +++ b/phl/phl_cmd_job.c @@ -0,0 +1,198 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: vincent_fann@realtek.com + * + *****************************************************************************/ +#include "phl_headers.h" + +#ifdef CONFIG_FSM + +#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y)) + +/** + * Deal with original command thread comd + */ +char unknow_func[8] = "no_name"; + +void *cmd2hal(struct _cmd_obj *pcmd) +{ + return pcmd->phl_info->hal; +} + +/* usually called when stopping fsm */ +void cmd_discard_msg_job(struct _cmd_obj *pcmd, struct fsm_msg *msg) +{ + void *d = phl_to_drvpriv(pcmd->phl_info); + struct phl_cmd_job *job = (struct phl_cmd_job *)msg->param; + + /* inform core to free param */ + if (job->id == JOB_RUN_FUNC && + (job->u.cmd.fptr || job->u.cmd.func)) { + FSM_INFO(pcmd->fsm, "%s: discard %s:%s\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job_name(pcmd, (u8)job->id), + (char *)job->u.cmd.name); + + /* we have to callback to core to free job + * Also release wait_complition if has + */ + job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, true); + } else + FSM_INFO(pcmd->fsm, "%s: discard %s\n", + phl_fsm_obj_name(pcmd->fsm_obj), + job_name(pcmd, (u8)job->id)); + + _os_kmem_free(d, (u8 *)msg->param, msg->param_sz); + _os_kmem_free(d, (u8 *)msg, sizeof(*msg)); +} + +enum rtw_phl_status rtw_phl_job_fill_fptr(void *phl, struct phl_cmd_job *job, + void *func, void *priv, void *parm, char *name, enum PWR_LEVEL pwr) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *d = phl_to_drvpriv(phl_info); + + job->id = JOB_RUN_FUNC; + job->pwr_level = pwr; + job->u.cmd.fptr = (int (*)(void *priv, void *param, bool discard))func; + job->u.cmd.priv = priv; + job->u.cmd.parm = parm; + _os_mem_set(d, job->u.cmd.name, 0, RTW_PHL_JOB_NAME_LEN); + if (name != NULL) + _os_mem_cpy(d, job->u.cmd.name, name, + MIN((RTW_PHL_JOB_NAME_LEN - 1), + _os_strlen((u8 *)name))); + else + _os_mem_cpy(d, job->u.cmd.name, unknow_func, + MIN((RTW_PHL_JOB_NAME_LEN - 1), + _os_strlen((u8 *)unknow_func))); + return RTW_PHL_STATUS_SUCCESS; +} + +/** + * @phl: phl private structure + * @func: function pointer to be runed + * @priv: 1st param of function pointer + * @parm: 2nd param of function pointer + * @name: function name for debug message (optional) + * @pwr: refers to enum PWR_LEVEL + */ +/* TODO remove below when no reference */ +enum rtw_phl_status rtw_phl_job_add_fptr(void *phl, void *func, + void *priv, void *parm, char *name, enum PWR_LEVEL pwr) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_cmd_job job; + + _os_mem_set(phl_to_drvpriv(phl_info), &job, 0, sizeof(job)); + rtw_phl_job_fill_fptr(phl, &job, func, priv, parm, name, pwr); + + return phl_cmd_complete_job(phl, &job); +} + +static int job_run_func_hdl(struct _cmd_obj *pcmd, void *param) +{ + struct phl_cmd_job *job = (struct phl_cmd_job *)param; + + if (job->u.cmd.fptr) + return job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, false); + else /* TODO remove else */ + return job->u.cmd.func(job->u.cmd.priv, job->u.cmd.parm); +} + +/** JOB_ADD_STA + * For EXTERNAL application to add sta entry (expose) + * @phl: phl private structure + * @sta: see rtw_phl_stainfo_t + * @sync: Async or SYNC mode + */ +enum rtw_phl_status rtw_hal_add_sta_entry_job(void *phl, + struct rtw_phl_stainfo_t *sta, enum JOB_SYNC sync) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *d = phl_to_drvpriv(phl_info); + struct phl_cmd_job job; + + _os_mem_set(d, &job, 0, sizeof(job)); + job.id = JOB_ADD_STA_ENTRY; + job.u.sta.sta = sta; + job.wait.sync = sync; + + return phl_cmd_complete_job(phl, &job); +} + +static int job_add_sta_entry_hdl(struct _cmd_obj *pcmd, void *param) +{ + struct phl_cmd_job *job = (struct phl_cmd_job *)param; + + return rtw_hal_add_sta_entry(cmd2hal(pcmd), job->u.sta.sta); +} + +static int job_add_macid_hdl(struct _cmd_obj *pcmd, void *param) +{ + FSM_INFO(pcmd->fsm, "job: %s()\n", __func__); + return 0; +} + +struct job_hdl_ent job_hdl_tbl[] = { + {JOB_RUN_FUNC, "JOB_RUN_FUNC", job_run_func_hdl}, + {JOB_ADD_STA_ENTRY, "JOB_ADD_STA_ENTRY", job_add_sta_entry_hdl}, + {JOB_ADD_MACID, "JOB_ADD_MACID", job_add_macid_hdl} +}; + +void cmd_set_job_tbl(struct _cmd_obj *pcmd) +{ + pcmd->job_tbl = job_hdl_tbl; +} + +char *job_name(struct _cmd_obj *pcmd, u8 id) +{ + if (id >= JOB_MAX) + FSM_ERR(pcmd->fsm, "%s: job id %d not found\n", + phl_fsm_obj_name(pcmd->fsm_obj), id); + + return job_hdl_tbl[id].name; +} + +int phl_cmd_do_job(struct _cmd_obj *pcmd, void *param) +{ + struct phl_cmd_job *job = (struct phl_cmd_job *)param; + void *d = phl_to_drvpriv(pcmd->phl_info); + int rtn = FSM_FREE_PARAM; + + + if (job->id == JOB_RUN_FUNC) + FSM_INFO(pcmd->fsm, "%s: %s (%s)\n", + phl_fsm_obj_name(pcmd->fsm_obj), + (char *)job_name(pcmd, (u8)job->id), + (char *)job->u.cmd.name); + else + FSM_INFO(pcmd->fsm, "%s: %s\n", + phl_fsm_obj_name(pcmd->fsm_obj), + (char *)job_name(pcmd, (u8)job->id)); + + job->wait.rtn = pcmd->job_tbl[job->id].job_func(pcmd, job); + + if (job->wait.sync == JOB_WAIT_COMPLETION) { + + _os_event_set(d, &(job->wait.done)); + /* Inform fsm framwork do NOT free param + * SYNC mode use caller's local job variable + */ + rtn = FSM_KEEP_PARAM; + } + return rtn; +} +#endif /*CONFIG_FSM*/ + diff --git a/phl/phl_cmd_job.h b/phl/phl_cmd_job.h new file mode 100644 index 0000000..43b3d62 --- /dev/null +++ b/phl/phl_cmd_job.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: vincent_fann@realtek.com + * + *****************************************************************************/ +#ifndef __PHL_CMD_JOB_H__ +#define __PHL_CMD_JOB_H__ + +#define RTW_PHL_JOB_NAME_LEN 32 +#ifndef MIN +#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y)) +#endif +struct fsm_msg; +struct _cmd_obj; + +/* command job */ +enum JOB_ID { + JOB_RUN_FUNC, + JOB_ADD_STA_ENTRY, + JOB_ADD_MACID, + JOB_MAX, +}; + +struct job_hdl_ent { + u16 job_id; + char name[RTW_PHL_JOB_NAME_LEN]; + int (*job_func)(struct _cmd_obj *pcmd, void *param); +}; + +enum JOB_RESULT { + JOB_SUCCESS, + /* caller thread will be schedule out until job is completed */ + JOB_TIMEOUT, + JOB_FAILURE +}; + +struct wait_completion { + + u8 sync; + u32 submit_time; + + /* <0: not synchronous, + * 0: wait forever, + * >0: max waitting time (ms) + */ + int max_wait_time; + + _os_event done; + + /* JOB_WAIT_COMPLETION use */ + int rtn; /* handle return value */ + enum JOB_RESULT result; /* operation result */ +}; + +struct phl_cmd_job { + _os_list list; + u16 id; + struct wait_completion wait; + u8 pwr_level; + union { + struct { /* JOB_RUN_FUNC */ + int (*func)(void *priv, void *param); /* TODO remove */ + int (*fptr)(void *priv, void *param, bool discard); + void *priv; + void *parm; + int parm_sz; + char name[RTW_PHL_JOB_NAME_LEN]; + } cmd; + + struct { /* JOB_ADD_STA_ENTRY */ + struct rtw_phl_stainfo_t *sta; + } sta; + } u; +}; + +enum PWR_LEVEL { + PWR_DONT_CARE, /* able to run in any kind of power mode */ + PWR_NO_IO, /* without register read write */ + PWR_BASIC_IO /* leave 32K and PG */ +}; + +enum JOB_SYNC { + JOB_ASYNC, + /* caller thread will be schedule out until job is completed */ + JOB_WAIT_COMPLETION +}; + +char *job_name(struct _cmd_obj *pcmd, u8 id); +void cmd_set_job_tbl(struct _cmd_obj *pcmd); +void cmd_discard_msg_job(struct _cmd_obj *pcmd, struct fsm_msg *msg); +int phl_cmd_do_job(struct _cmd_obj *pcmd, void *param); + +/* command thread jobs */ +/* TODO remove below when no reference */ +enum rtw_phl_status rtw_phl_job_add_fptr(void *phl, void *func, + void *priv, void *parm, char *name, enum PWR_LEVEL pwr); + +enum rtw_phl_status rtw_phl_job_fill_fptr(void *phl, struct phl_cmd_job *job, + void *func, void *priv, void *parm, char *name, enum PWR_LEVEL pwr); + +enum rtw_phl_status phl_cmd_enqueue_and_wait_job(struct _cmd_obj *pcmd, + struct fsm_msg *msg); + +enum rtw_phl_status phl_cmd_complete_job(void *phl, struct phl_cmd_job *job); + +enum rtw_phl_status rtw_phl_job_reg_wdog(void *phl, + int (*func)(void *priv, void *param, bool discard), + void *priv, void *parm, int parm_sz, char *name, enum PWR_LEVEL pwr); +enum rtw_phl_status rtw_phl_cmd_pause_wdog(void *phl, char *reason); +enum rtw_phl_status rtw_phl_cmd_resume_wdog(void *phl, char *reason); + +enum rtw_phl_status rtw_hal_add_sta_entry_job(void *phl, + struct rtw_phl_stainfo_t *sta, enum JOB_SYNC sync); + +#endif /* __PHL_CMD_JOB_H__ */ diff --git a/phl/phl_cmd_ps.c b/phl/phl_cmd_ps.c new file mode 100644 index 0000000..7af28e9 --- /dev/null +++ b/phl/phl_cmd_ps.c @@ -0,0 +1,1900 @@ +/****************************************************************************** + * + * Copyright(c) 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_PS_C_ +#include "phl_headers.h" +#ifdef CONFIG_POWER_SAVE +/* structure of a power request */ +struct pwr_req { + _os_list list; + u16 evt_id; +}; + +struct rt_ps { + enum phl_ps_rt_rson rt_rson; + bool ps_allow; +}; + +enum { + PS_STATE_NONE = 0, + PS_STATE_LEAVED, + /** + * lps: protocol only + * ips: won't in this state + */ + PS_STATE_PROTO, + /** + * lps: protocol + power + * ips: power + */ + PS_STATE_ENTERED +}; + +static const char *_ps_state_to_str(u8 ps_state) +{ + switch (ps_state) { + case PS_STATE_ENTERED: + return "PS_ENTERED"; + case PS_STATE_PROTO: + return "PS_PROTOCOL"; + case PS_STATE_LEAVED: + return "PS_LEAVED"; + default: + return "NONE"; + } +} + +struct _ps_mr_info { + bool ap_active; + bool gc_active; +}; + +#define CMD_PS_TIMER_PERIOD 100 +#define MAX_PWE_REQ_NUM 16 +struct cmd_ps { + struct phl_info_t *phl_info; + void *dispr; + _os_timer ps_timer; + + struct phl_queue req_busy_q; + struct phl_queue req_idle_q; + struct pwr_req req_pool[MAX_PWE_REQ_NUM]; + + bool rej_pwr_req; /* reject all pwr request */ + bool btc_req_pwr; /* btc request pwr or not */ + bool stop_datapath; + + /* current state */ + u8 cur_pwr_lvl; + u8 ps_state; + u8 ps_mode; + char enter_rson[MAX_CMD_PS_RSON_LENGTH]; + char leave_rson[MAX_CMD_PS_RSON_LENGTH]; + + /* lps */ + struct rtw_phl_stainfo_t *sta; /* sta entering/leaving lps */ + u16 macid; + u32 null_token; + bool pre_phase_leave_ps; + + /* refs. enum "phl_ps_rt_rson" */ + enum phl_ps_rt_rson rt_stop_rson; + + struct _ps_mr_info mr_info; + + /* rssi */ + u8 rssi_bcn_min; +}; + +/** + * determine leave lps or not + * return true if rssi variation reach threshold + * @ps: see cmd_ps + */ +static bool _chk_rssi_diff_reach_thld(struct cmd_ps *ps) +{ + struct phl_info_t *phl_info = ps->phl_info; + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + u8 cur_rssi_bcn_min = 0; + u8 *rssi_bcn_min = &ps->rssi_bcn_min; + bool leave_ps = false; + + cur_rssi_bcn_min = phl_get_min_rssi_bcn(phl_info); + + do { + if (*rssi_bcn_min == 0 || *rssi_bcn_min == 0xFF) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): (criteria = %d, cur = %d) criteria invalid, set criteria to cur\n", + __func__, *rssi_bcn_min, cur_rssi_bcn_min); + *rssi_bcn_min = cur_rssi_bcn_min; /* update with current_rssi */ + break; + } + + if (DIFF(*rssi_bcn_min, cur_rssi_bcn_min) < ps_cap->lps_rssi_diff_threshold) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): (criteria = %d, cur = %d) RSSI diff < %d, do nothing\n", + __func__, *rssi_bcn_min, cur_rssi_bcn_min, ps_cap->lps_rssi_diff_threshold); + break; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): leave ps and update criteria from %d to %d\n", __func__, *rssi_bcn_min, cur_rssi_bcn_min); + + leave_ps = true; + *rssi_bcn_min = cur_rssi_bcn_min; + } while (0); + + return leave_ps; +} + +/** + * determine leave lps or not + * return true if beacon offset changed + * @ps: see cmd_ps + */ +bool _chk_bcn_offset_changed(struct cmd_ps *ps) +{ + struct phl_info_t *phl_info = ps->phl_info; + u8 ridx = MAX_WIFI_ROLE_NUMBER; + struct rtw_wifi_role_t *wrole = NULL; + struct rtw_bcn_offset *b_ofst_i = NULL; + bool leave_ps = false; + + for (ridx = 0; ridx < MAX_WIFI_ROLE_NUMBER; ridx++) { + wrole = rtw_phl_get_wrole_by_ridx(phl_info->phl_com, ridx); + if (wrole == NULL) + continue; + + if (rtw_phl_role_is_client_category(wrole) && wrole->mstate == MLME_LINKED) { + b_ofst_i = phl_get_sta_bcn_offset_info(phl_info, wrole); + + if (b_ofst_i->conf_lvl >= CONF_LVL_MID && + b_ofst_i->offset != b_ofst_i->cr_tbtt_shift) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): update ridx(%d) bcn offset from %d to %d TU\n", + __func__, ridx, b_ofst_i->cr_tbtt_shift, b_ofst_i->offset); + leave_ps = true; + break; + } + } + } + return leave_ps; +} + +/** + * check whether to leave/enter lps + * return true if ps need to change to the target state + * @ps: see cmd_ps + * @mac_id: macid of corresponding sta + * @cur_state: currently lps state + * @target_state: the target ps state + */ +static bool +_lps_state_judge_changed(struct cmd_ps *ps, u16 macid, u8 cur_state, u8 target_state) +{ + struct phl_info_t *phl_info = ps->phl_info; + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + struct rtw_stats *phl_stats = &phl_info->phl_com->phl_stats; + struct rtw_phl_stainfo_t *sta = NULL; + bool change_state = false; + u8 rssi = 0; + + sta = rtw_phl_get_stainfo_by_macid(phl_info, macid); + if (sta == NULL) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): cannot get sta of macid %d.\n", __func__, macid); + return false; + } + + rssi = rtw_hal_get_sta_rssi(sta); + + if (target_state == PS_STATE_ENTERED) { + if (cur_state == PS_STATE_LEAVED || cur_state == PS_STATE_PROTO) { + if (rssi > ps_cap->lps_rssi_enter_threshold && + phl_stats->tx_traffic.lvl == RTW_TFC_IDLE && + phl_stats->rx_traffic.lvl == RTW_TFC_IDLE) { + change_state = true; + } + } + } else { + if (cur_state == PS_STATE_ENTERED || cur_state == PS_STATE_PROTO) { + if (_chk_rssi_diff_reach_thld(ps) || + _chk_bcn_offset_changed(ps) || + rssi < ps_cap->lps_rssi_leave_threshold || + phl_stats->tx_traffic.lvl != RTW_TFC_IDLE || + phl_stats->rx_traffic.lvl != RTW_TFC_IDLE) { + change_state = true; + } + } + } + + if (change_state) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): state %s -> %s, Tx(%s), Rx(%s), RSSI(%d)\n", + __func__, _ps_state_to_str(cur_state), _ps_state_to_str(target_state), + phl_tfc_lvl_to_str(phl_stats->tx_traffic.lvl), + phl_tfc_lvl_to_str(phl_stats->rx_traffic.lvl), rssi); + } + + return change_state; +} + +static void _set_ps_rson(struct cmd_ps *ps, u8 enter, char *rson) +{ + if (enter) { + _os_mem_set(phl_to_drvpriv(ps->phl_info), ps->enter_rson, 0, MAX_CMD_PS_RSON_LENGTH); + _os_mem_cpy(phl_to_drvpriv(ps->phl_info), ps->enter_rson, rson, MAX_CMD_PS_RSON_LENGTH); + } else { + _os_mem_set(phl_to_drvpriv(ps->phl_info), ps->leave_rson, 0, MAX_CMD_PS_RSON_LENGTH); + _os_mem_cpy(phl_to_drvpriv(ps->phl_info), ps->leave_rson, rson, MAX_CMD_PS_RSON_LENGTH); + } +} + +/** + * Leave power saving + * return RTW_PHL_STATUS_SUCCESS if leave ps ok + * @ps: see cmd_ps + * @leave_proto: whether to leave protocol + */ +enum rtw_phl_status _leave_ps(struct cmd_ps *ps, bool leave_proto, char *rson) +{ + struct phl_info_t *phl_info = ps->phl_info; + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct ps_cfg cfg = {0}; + + if (ps->ps_state == PS_STATE_LEAVED) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): not in power saving.\n", __func__); + return RTW_PHL_STATUS_SUCCESS; + } + + cfg.cur_pwr_lvl = ps->cur_pwr_lvl; + + if (ps->ps_mode == PS_MODE_LPS) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): target macid to leave lps %d (leave_proto %d).\n", + __func__, ps->macid, leave_proto); + if (!leave_proto) { + if (ps->ps_state == PS_STATE_PROTO) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): in lps protocal only.\n", __func__); + return RTW_PHL_STATUS_SUCCESS; + } + cfg.pwr_cfg = true; + cfg.proto_cfg = false; + } else { + if (ps->ps_state == PS_STATE_PROTO) { + cfg.pwr_cfg = false; + cfg.proto_cfg = true; + } else { + cfg.pwr_cfg = true; + cfg.proto_cfg = true; + } + } + cfg.macid = ps->macid; + cfg.token = &ps->null_token; + cfg.pwr_lvl = PS_PWR_LVL_PWRON; + cfg.ps_mode = ps->ps_mode; + } else if (ps->ps_mode == PS_MODE_IPS) { + cfg.pwr_lvl = PS_PWR_LVL_PWRON; + cfg.ps_mode = ps->ps_mode; + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): unknown ps mode!\n", __func__); + } + + _set_ps_rson(ps, false, rson); + + status = phl_ps_leave_ps(phl_info, &cfg); + + if (status == RTW_PHL_STATUS_SUCCESS) { + ps->cur_pwr_lvl = cfg.pwr_lvl; + if (ps->ps_mode == PS_MODE_LPS) { + ps->ps_mode = (leave_proto != true) ? PS_MODE_LPS : PS_MODE_NONE; + ps->ps_state = (leave_proto != true) ? PS_STATE_PROTO : PS_STATE_LEAVED; + ps->macid = (leave_proto != true) ? ps->macid : 0xFFFF; + } else { + ps->ps_mode = PS_MODE_NONE; + ps->ps_state = PS_STATE_LEAVED; + ps->macid = 0xFFFF; + } + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): leave ps success, reason(%s).\n", __func__, rson); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): ps mode(%s), pwr lvl(%s), ps state(%s)\n", + __func__, phl_ps_ps_mode_to_str(ps->ps_mode), + phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl), _ps_state_to_str(ps->ps_state)); + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): leave ps fail! reason(%s).\n", __func__, rson); + } + + return status; +} + +/** + * Enter power saving + * return RTW_PHL_STATUS_SUCCESS if enter ps ok + * @ps: see cmd_ps + * @ps_mode: target ps mode to enter + * @macid : target macid to enter lps + */ +enum rtw_phl_status _enter_ps(struct cmd_ps *ps, u8 ps_mode, u16 macid, char *rson) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct ps_cfg cfg = {0}; + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + + if (ps->ps_state == PS_STATE_ENTERED) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): already in power saving.\n", __func__); + return RTW_PHL_STATUS_SUCCESS; + } + + cfg.cur_pwr_lvl = ps->cur_pwr_lvl; + + if (ps_mode == PS_MODE_LPS) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): target macid to enter lps %d.\n", __func__, macid); + cfg.proto_cfg = (ps->ps_state == PS_STATE_PROTO) ? false : true; + cfg.pwr_cfg = true; + cfg.macid = macid; + cfg.token = &ps->null_token; + cfg.pwr_lvl = phl_ps_judge_pwr_lvl(ps_cap->lps_cap, ps_mode, true); + cfg.ps_mode = ps_mode; + cfg.awake_interval = ps_cap->lps_awake_interval; + cfg.listen_bcn_mode = ps_cap->lps_listen_bcn_mode; + cfg.smart_ps_mode = ps_cap->lps_smart_ps_mode; + } else if (ps_mode == PS_MODE_IPS) { + cfg.pwr_lvl = PS_PWR_LVL_PWROFF; + cfg.ps_mode = ps_mode; + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): unknown ps mode!\n", __func__); + } + + _set_ps_rson(ps, true, rson); + + status = phl_ps_enter_ps(ps->phl_info, &cfg); + + if (status == RTW_PHL_STATUS_SUCCESS) { + ps->cur_pwr_lvl = cfg.pwr_lvl; + ps->ps_mode = cfg.ps_mode; + ps->macid = cfg.macid; + ps->ps_state = PS_STATE_ENTERED; + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): enter ps success, reason(%s).\n", __func__, rson); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): ps mode(%s), pwr lvl(%s), ps state(%s)\n", + __func__, phl_ps_ps_mode_to_str(ps->ps_mode), + phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl), _ps_state_to_str(ps->ps_state)); + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): enter ps fail! reason(%s).\n", __func__, rson); + } + + return status; +} + +static bool _pop_idle_req(struct cmd_ps *ps, struct pwr_req **req) +{ + void *d = phl_to_drvpriv(ps->phl_info); + _os_list *new_req = NULL; + bool ret = false; + + (*req) = NULL; + if (pq_pop(d, &(ps->req_idle_q), &new_req, _first, _bh)) { + (*req) = (struct pwr_req *)new_req; + ret = true; + } else { + ret = false; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): remaining idle req cnt %d.\n", __func__, ps->req_idle_q.cnt); + + return ret; +} + +static void _push_idle_req(struct cmd_ps *ps, struct pwr_req *req) +{ + void *d = phl_to_drvpriv(ps->phl_info); + + pq_push(d, &(ps->req_idle_q), &(req->list), _tail, _bh); + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): remaining idle req cnt %d.\n", __func__, ps->req_idle_q.cnt); +} + +static bool _pop_busy_req(struct cmd_ps *ps, struct pwr_req **req) +{ + void *d = phl_to_drvpriv(ps->phl_info); + _os_list *new_req = NULL; + bool ret = false; + + (*req) = NULL; + if (pq_pop(d, &(ps->req_busy_q), &new_req, _tail, _bh)) { + (*req) = (struct pwr_req *)new_req; + ret = true; + } else { + ret = false; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): current busy req cnt %d.\n", __func__, ps->req_busy_q.cnt); + + return ret; +} + +static void _push_busy_req(struct cmd_ps *ps, struct pwr_req *req) +{ + void *d = phl_to_drvpriv(ps->phl_info); + + pq_push(d, &(ps->req_busy_q), &(req->list), _tail, _bh); + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): current busy req cnt %d.\n", __func__, ps->req_busy_q.cnt); +} + +static void _cancel_pwr_req(struct cmd_ps *ps, u16 evt_id) +{ + struct pwr_req *req = NULL; + + if (!_pop_busy_req(ps, &req)) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): busy queue is empty.\n", __func__); + return; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): evt_id %d\n", __func__, req->evt_id); + + if (req->evt_id != evt_id && MSG_EVT_PHY_IDLE != evt_id) + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): evt_id mismatch.\n", __func__); + + req->evt_id = MSG_EVT_NONE; + + _push_idle_req(ps, req); +} + +static enum rtw_phl_status _add_pwr_req(struct cmd_ps *ps, u16 evt_id) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct pwr_req *req = NULL; + + if (!_pop_idle_req(ps, &req)) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): idle queue is empty.\n", __func__); + return RTW_PHL_STATUS_RESOURCE; + } + + req->evt_id = evt_id; + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): evt_id %d\n", __func__, evt_id); + + _push_busy_req(ps, req); + + return status; +} + +static void _init_pwr_req_q(struct cmd_ps *ps) +{ + void *d = phl_to_drvpriv(ps->phl_info); + u8 i = 0; + + pq_init(d, &ps->req_busy_q); + pq_init(d, &ps->req_idle_q); + + _os_mem_set(d, ps->req_pool, 0, + sizeof(struct pwr_req) * MAX_PWE_REQ_NUM); + + for (i = 0; i < MAX_PWE_REQ_NUM; i++) { + pq_push(d, &(ps->req_idle_q), + &(ps->req_pool[i].list), _tail, _bh); + } +} + +static void _reset_pwr_req_q(struct cmd_ps *ps) +{ + void *d = phl_to_drvpriv(ps->phl_info); + u8 i = 0; + + pq_reset(d, &ps->req_busy_q, _bh); + pq_reset(d, &ps->req_idle_q, _bh); + + _os_mem_set(d, ps->req_pool, 0, + sizeof(struct pwr_req) * MAX_PWE_REQ_NUM); + + for (i = 0; i < MAX_PWE_REQ_NUM; i++) { + pq_push(d, &(ps->req_idle_q), + &(ps->req_pool[i].list), _tail, _bh); + } +} + +static void _deinit_pwr_req_q(struct cmd_ps *ps) +{ + void *d = phl_to_drvpriv(ps->phl_info); + + pq_deinit(d, &ps->req_busy_q); + pq_deinit(d, &ps->req_idle_q); +} + +static void _init_ps_dflt_sw_cap(struct cmd_ps *ps) +{ + struct rtw_ps_cap_t *sw_cap = _get_ps_sw_cap(ps->phl_info); + + sw_cap->init_rf_state = RTW_RF_ON; + sw_cap->init_rt_stop_rson = PS_RT_RSON_NONE; + sw_cap->leave_fail_act = PS_LEAVE_FAIL_ACT_NONE; + + sw_cap->ips_en = PS_OP_MODE_DISABLED; + sw_cap->ips_cap = 0; + sw_cap->ips_wow_en = PS_OP_MODE_DISABLED; + sw_cap->ips_wow_cap = 0; + + sw_cap->lps_en = PS_OP_MODE_DISABLED; + sw_cap->lps_cap = 0; + sw_cap->lps_awake_interval = 0; + sw_cap->lps_listen_bcn_mode = RTW_LPS_RLBM_MIN; + sw_cap->lps_smart_ps_mode = RTW_LPS_TRX_PWR0; + sw_cap->lps_rssi_enter_threshold = 40; + sw_cap->lps_rssi_leave_threshold = 35; + sw_cap->lps_rssi_diff_threshold = 5; + + sw_cap->lps_wow_en = PS_OP_MODE_DISABLED; + sw_cap->lps_wow_cap = 0; + sw_cap->lps_wow_awake_interval = 0; + sw_cap->lps_wow_listen_bcn_mode = RTW_LPS_RLBM_MAX; + sw_cap->lps_wow_smart_ps_mode = RTW_LPS_TRX_PWR0; +} + +static void _cmd_ps_timer_cb(void *context) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct cmd_ps *ps = (struct cmd_ps *)context; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + PHL_DBG("[PS_CMD], %s(): \n", __func__); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PS_PERIOD_CHK); + msg.band_idx = HW_BAND_0; + + pstatus = phl_disp_eng_send_msg(ps->phl_info, &msg, &attr, NULL); + if (pstatus != RTW_PHL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to send MSG_EVT_PS_PERIOD_CHK.\n", __func__); + } +} + +static enum phl_mdl_ret_code _ps_mdl_init(void *phl, void *dispr, void **priv) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct cmd_ps *ps = NULL; + + PHL_INFO("[PS_CMD], %s(): \n", __func__); + + if (priv == NULL) + return MDL_RET_FAIL; + + (*priv) = NULL; + ps = (struct cmd_ps *)_os_mem_alloc(phl_to_drvpriv(phl_info), + sizeof(struct cmd_ps)); + if (ps == NULL) { + PHL_ERR("[PS_CMD], %s(): allocate cmd ps fail.\n", __func__); + return MDL_RET_FAIL; + } + + _os_mem_set(phl_to_drvpriv(phl_info), ps, 0, sizeof(struct cmd_ps)); + + ps->phl_info = phl_info; + ps->dispr = dispr; + (*priv) = (void *)ps; + ps->cur_pwr_lvl = PS_PWR_LVL_PWRON; + ps->ps_state = PS_STATE_LEAVED; + ps->ps_mode = PS_MODE_NONE; + ps->rej_pwr_req = false; + ps->rt_stop_rson = PS_RT_RSON_NONE; + + _os_init_timer(phl_to_drvpriv(phl_info), + &ps->ps_timer, + _cmd_ps_timer_cb, + ps, + "phl_cmd_ps_timer"); + + _init_pwr_req_q(ps); + + _init_ps_dflt_sw_cap(ps); + + return MDL_RET_SUCCESS; +} + +static void _ps_mdl_deinit(void *dispr, void *priv) +{ + struct cmd_ps *ps = (struct cmd_ps *)priv; + + PHL_INFO("[PS_CMD], %s(): \n", __func__); + + _os_release_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer); + + _deinit_pwr_req_q(ps); + + if (ps != NULL) + _os_mem_free(phl_to_drvpriv(ps->phl_info), ps, sizeof(struct cmd_ps)); +} + +static void _dump_ps_cap(struct cmd_ps *ps) +{ + struct rtw_ps_cap_t *ps_cap = NULL; + + ps_cap = _get_ps_cap(ps->phl_info); + + PHL_INFO("[PS_CMD], %s(): \n", __func__); + PHL_INFO("[PS_CMD], init_rf_state: %d\n", ps_cap->init_rf_state); + PHL_INFO("[PS_CMD], init_rt_stop_rson: 0x%x\n", ps_cap->init_rt_stop_rson); + PHL_INFO("[PS_CMD], leave_fail_act: 0x%x\n", ps_cap->leave_fail_act); + PHL_INFO("[PS_CMD], ips_en: %d\n", ps_cap->ips_en); + PHL_INFO("[PS_CMD], ips_cap: %d\n", ps_cap->ips_cap); + PHL_INFO("[PS_CMD], ips_wow_en: %d\n", ps_cap->ips_wow_en); + PHL_INFO("[PS_CMD], ips_wow_cap: %d\n", ps_cap->ips_wow_cap); + PHL_INFO("[PS_CMD], lps_en: %d\n", ps_cap->lps_en); + PHL_INFO("[PS_CMD], lps_cap: %d\n", ps_cap->lps_cap); + PHL_INFO("[PS_CMD], lps_awake_interval: %d\n", ps_cap->lps_awake_interval); + PHL_INFO("[PS_CMD], lps_listen_bcn_mode: %d\n", ps_cap->lps_listen_bcn_mode); + PHL_INFO("[PS_CMD], lps_smart_ps_mode: %d\n", ps_cap->lps_smart_ps_mode); + PHL_INFO("[PS_CMD], lps_rssi_enter_threshold: %d\n", ps_cap->lps_rssi_enter_threshold); + PHL_INFO("[PS_CMD], lps_rssi_leave_threshold: %d\n", ps_cap->lps_rssi_leave_threshold); + PHL_INFO("[PS_CMD], lps_rssi_diff_threshold: %d\n", ps_cap->lps_rssi_diff_threshold); + PHL_INFO("[PS_CMD], lps_wow_en: %d\n", ps_cap->lps_wow_en); + PHL_INFO("[PS_CMD], lps_wow_cap: %d\n", ps_cap->lps_wow_cap); + PHL_INFO("[PS_CMD], lps_wow_awake_interval: %d\n", ps_cap->lps_wow_awake_interval); + PHL_INFO("[PS_CMD], lps_wow_listen_bcn_mode: %d\n", ps_cap->lps_wow_listen_bcn_mode); + PHL_INFO("[PS_CMD], lps_wow_smart_ps_mode: %d\n", ps_cap->lps_wow_smart_ps_mode); + PHL_INFO("[PS_CMD], lps_pause_tx: %d\n", ps_cap->lps_pause_tx); +} + +static void _leave_success_hdlr(struct cmd_ps *ps) +{ + struct phl_data_ctl_t ctl = {0}; + + if (ps->stop_datapath) { + /* resume tx datapath */ + ctl.id = PHL_MDL_POWER_MGNT; + ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME; + phl_data_ctrler(ps->phl_info, &ctl, NULL); + ps->stop_datapath = false; + } +} + +static void _leave_fail_hdlr(struct cmd_ps *ps) +{ + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + + PHL_WARN("[PS_CMD], %s(): action 0x%x\n", __func__, ps_cap->leave_fail_act); + + /* reject all power operation */ + if (ps_cap->leave_fail_act & PS_LEAVE_FAIL_ACT_REJ_PWR) + ps->rej_pwr_req = true; + + /* L2 should be the last one */ + if (ps_cap->leave_fail_act & PS_LEAVE_FAIL_ACT_L2) + phl_ser_send_msg(ps->phl_info, RTW_PHL_SER_L2_RESET); +} + +static enum phl_mdl_ret_code _ps_mdl_start(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + struct cmd_ps *ps = (struct cmd_ps *)priv; + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + u8 idx = 0; + + ps->rt_stop_rson = ps_cap->init_rt_stop_rson; + + _reset_pwr_req_q(ps); + + phl_dispr_get_idx(dispr, &idx); + + if (idx == 0) { + _dump_ps_cap(ps); + PHL_INFO("[PS_CMD], %s(): init rf state %d, reject pwr req %d\n", + __func__, ps_cap->init_rf_state, ps->rej_pwr_req); + if (ps_cap->init_rf_state == RTW_RF_OFF) + ps->rej_pwr_req = true; + if (ps->rej_pwr_req == true) + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "mdl start with rf off"); + _os_set_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer, CMD_PS_TIMER_PERIOD); + } + return ret; +} + +static enum phl_mdl_ret_code _ps_mdl_stop(void *dispr, void *priv) +{ + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + struct cmd_ps *ps = (struct cmd_ps *)priv; + + if (ps->ps_state == PS_STATE_ENTERED) { + PHL_WARN("[PS_CMD], %s(): module stop in power saving!\n", __func__); + _leave_ps(ps, true, "mdl stop"); + } + + _os_cancel_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer); + + PHL_INFO("[PS_CMD], %s(): \n", __func__); + + return ret; +} + +static bool _chk_role_all_inactive(struct cmd_ps *ps) +{ + struct phl_info_t *phl_info = ps->phl_info; + u8 role_idx = 0; + bool ret = true; + + for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) { + if (phl_info->phl_com->wifi_roles[role_idx].mstate != MLME_NO_LINK) { + ret = false; + break; + } + } + + return ret; +} + +static struct rtw_wifi_role_t *_get_role_of_ps_permitted(struct cmd_ps *ps) +{ + struct phl_info_t *phl_info = ps->phl_info; + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + u8 role_idx = 0; + + for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) { + if (phl_com->wifi_roles[role_idx].active == false) + continue; + if (phl_com->wifi_roles[role_idx].type == PHL_RTYPE_STATION && + phl_com->wifi_roles[role_idx].mstate == MLME_LINKED) { + return &(phl_com->wifi_roles[role_idx]); + } + } + + return NULL; +} + +/** + * go through all wifi roles and check whether input + * ps mode desired is allowed with existing wroles + * @ps: see cmd_ps + * @target_mode: the desired ps mode (lps or ips) + * @macid: target macid to enter lps + */ +static bool _chk_wrole_with_ps_mode(struct cmd_ps *ps, + u8 target_mode, u16 *macid) +{ + struct rtw_wifi_role_t *role = NULL; + bool ret = false; + struct rtw_phl_stainfo_t *sta = NULL; + + if (ps->mr_info.ap_active || ps->mr_info.gc_active) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): ap %d or gc %d, is active.\n", __func__, + ps->mr_info.ap_active, ps->mr_info.gc_active); + return false; + } + + if (target_mode == PS_MODE_IPS) { + if (_chk_role_all_inactive(ps)) + ret = true; + } else if (target_mode == PS_MODE_LPS) { + role = _get_role_of_ps_permitted(ps); + if (role == NULL) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): there is no suitable role to enter lps.\n", __func__); + return false; + } + sta = rtw_phl_get_stainfo_self(ps->phl_info, role); + if (sta == NULL) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): cannot get sta info.\n", __func__); + return false; + } + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): role id to enter ps (%d).\n", __func__, role->id); + ps->sta = sta; + *macid = sta->macid; + ret = true; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): decide enter ps(%s), target mode(%s).\n", + __func__, (ret) ? "Yes" : "No", phl_ps_ps_mode_to_str(target_mode)); + + return ret; +} + +static enum rtw_phl_status _stop_datapath(struct cmd_ps *ps) +{ + struct phl_data_ctl_t ctl = {0}; + + /* stop tx datapath */ + ctl.id = PHL_MDL_POWER_MGNT; + ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE; + + if (phl_data_ctrler(ps->phl_info, &ctl, NULL) == RTW_PHL_STATUS_SUCCESS) { + ps->stop_datapath = true; + return RTW_PHL_STATUS_SUCCESS; + } + + return RTW_PHL_STATUS_FAILURE; +} + +static bool _is_datapath_active(struct cmd_ps *ps) +{ + struct phl_info_t *phl_info = ps->phl_info; + + return (_os_atomic_read(phl_to_drvpriv(phl_info), &phl_info->phl_sw_tx_sts) + != PHL_TX_STATUS_SW_PAUSE) ? true : false; +} + +/** + * check current capability of power saving + * return able to enter ps or not + * @ps: see cmd_ps + * @mode: the target ps mode to be check + */ +static bool _chk_ps_cap(struct cmd_ps *ps, u8 mode) +{ + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): mode(%s), lps_en(%d), ips_en(%d), runtime stop reason(0x%x).\n", + __func__, phl_ps_ps_mode_to_str(mode), ps_cap->lps_en, ps_cap->ips_en, ps->rt_stop_rson); + + switch (mode) { + case PS_MODE_LPS: + if (ps_cap->lps_en == PS_OP_MODE_DISABLED) { + return false; + } else if (ps_cap->lps_en == PS_OP_MODE_FORCE_ENABLED) { + /* force enable */ + return true; + } else if (ps_cap->lps_en == PS_OP_MODE_AUTO) { + if (ps->rt_stop_rson == PS_RT_RSON_NONE) + return true; + } + break; + case PS_MODE_IPS: + if (ps_cap->ips_en == PS_OP_MODE_DISABLED) { + return false; + } else if (ps_cap->ips_en == PS_OP_MODE_FORCE_ENABLED) { + /* force enable */ + return true; + } else if (ps_cap->ips_en == PS_OP_MODE_AUTO) { + if (ps->rt_stop_rson == PS_RT_RSON_NONE) + return true; + } + break; + default: + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): unknown ps mode.\n", __func__); + return false; + } + + return false; +} + +/** + * check the condition of ips + * return whether to enter ips or not + * @ps: see cmd_ps + */ +static bool _chk_ips_enter(struct cmd_ps *ps) +{ + if (TEST_STATUS_FLAG(ps->phl_info->phl_com->dev_state, RTW_DEV_RESUMING)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): resume in progress.\n", __func__); + return false; + } + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return false; + } + + if (!_chk_ps_cap(ps, PS_MODE_IPS)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): ips is not allowed.\n", __func__); + return false; + } + + if (!phl_disp_eng_is_fg_empty(ps->phl_info, HW_BAND_0)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): fg exist.\n", __func__); + return false; + } + + if (ps->req_busy_q.cnt) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): req q is not empty.\n", __func__); + return false; + } + + if (ps->btc_req_pwr) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): btc req pwr.\n", __func__); + return false; + } + + if (!_chk_wrole_with_ps_mode(ps, PS_MODE_IPS, NULL)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): no need to enter ips.\n", __func__); + return false; + } + + return true; +} + +/** + * check the condition of lps + * return whether to enter lps or not + * @ps: see cmd_ps + */ +static bool _chk_lps_enter(struct cmd_ps *ps, u16 *macid) +{ + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info); + + /* check enter lps or not */ + + if (TEST_STATUS_FLAG(ps->phl_info->phl_com->dev_state, RTW_DEV_RESUMING)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): resume in progress.\n", __func__); + return false; + } + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return false; + } + + /* check capability */ + if (!_chk_ps_cap(ps, PS_MODE_LPS)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps is not allowed.\n", __func__); + return false; + } + + /* check fg module */ + if (!phl_disp_eng_is_fg_empty(ps->phl_info, HW_BAND_0)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): fg exist.\n", __func__); + return false; + } + + /* ref cnt */ + if (ps->req_busy_q.cnt) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): req q is not empty.\n", __func__); + return false; + } + + /* btc */ + if (ps->btc_req_pwr) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): btc req pwr.\n", __func__); + return false; + } + + if (ps->pre_phase_leave_ps == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): just leave ps in watchdog prephase.\n", __func__); + return false; + } + + /* check wifi role */ + if (!_chk_wrole_with_ps_mode(ps, PS_MODE_LPS, macid)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): no need to enter lps.\n", __func__); + return false; + } + + /* lps */ + if (_lps_state_judge_changed(ps, *macid, ps->ps_state, PS_STATE_ENTERED)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps state changed.\n", __func__); + /* check data path stop or not */ + if (ps_cap->lps_pause_tx) { + if (!_is_datapath_active(ps)) { + return true; + } else { + if (_stop_datapath(ps) == RTW_PHL_STATUS_SUCCESS) + return true; + } + } else { + return true; + } + } + + return false; +} + +static void _ps_watchdog_info_dump(struct cmd_ps *ps) +{ + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "========== CMD PS Info ========== \n"); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "ps mode(%s), pwr lvl(%s), ps state(%s)\n", + phl_ps_ps_mode_to_str(ps->ps_mode), + phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl), + _ps_state_to_str(ps->ps_state)); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "req idle cnt(%d), req busy cnt(%d)\n", + ps->req_idle_q.cnt, ps->req_busy_q.cnt); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "ap active(%s), gc active(%s)\n", + (ps->mr_info.ap_active ? "yes" : "no"), (ps->mr_info.gc_active ? "yes" : "no")); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "reject all pwr req(%s), btc req pwr(%s), runtime stop reason(0x%x)\n", + (ps->rej_pwr_req ? "yes" : "no"), (ps->btc_req_pwr ? "yes" : "no"), ps->rt_stop_rson); + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "========== CMD PS Info ========== \n"); +} + +/** + * pre-phase handler of watchdog + * will check whether to leave lps or not + * @ps: see cmd_ps + */ +static enum phl_mdl_ret_code +_ps_watchdog_pre_hdlr(struct cmd_ps *ps) +{ + /* check leave lps or not */ + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): pwr lvl(%s).\n", __func__, phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl)); + + ps->pre_phase_leave_ps = false; + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + if (ps->ps_mode == PS_MODE_IPS) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): power off.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + if (ps->ps_state == PS_STATE_LEAVED) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): not in power saving.\n", __func__); + return MDL_RET_SUCCESS; + } else { + if (_lps_state_judge_changed(ps, ps->macid, ps->ps_state, PS_STATE_LEAVED)) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps state changed.\n", __func__); + if (_leave_ps(ps, true, "watchdog") == RTW_PHL_STATUS_SUCCESS) { + ps->pre_phase_leave_ps = true; + _leave_success_hdlr(ps); + return MDL_RET_SUCCESS; + } else { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): going to L2 reset!\n", __func__); + _leave_fail_hdlr(ps); + return MDL_RET_CANNOT_IO; + } + } + if (ps->ps_state == PS_STATE_PROTO) + return MDL_RET_SUCCESS; + else + return MDL_RET_CANNOT_IO; + } +} + +/** + * post-phase handler of watchdog + * will check whether to enter lps or not + * @ps: see cmd_ps + */ +static enum phl_mdl_ret_code +_ps_watchdog_post_hdlr(struct cmd_ps *ps) +{ + u16 macid = 0xFFFF; + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): pwr lvl(%s).\n", __func__, phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl)); + + if (_chk_lps_enter(ps, &macid)) + _enter_ps(ps, PS_MODE_LPS, macid, "watchdog"); + else if (_chk_ips_enter(ps)) + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "watchdog"); + + _ps_watchdog_info_dump(ps); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _phy_on_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_PHY_ON\n"); + if (_leave_ps(ps, true, "phy on") == RTW_PHL_STATUS_SUCCESS) { + _add_pwr_req(ps, MSG_EVT_ID_FIELD(msg->msg_id)); + _leave_success_hdlr(ps); + ret = MDL_RET_SUCCESS; + } else { + _leave_fail_hdlr(ps); + } + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +static enum phl_mdl_ret_code _tx_pwr_req_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_TRX_PWR_REQ\n"); + if (_leave_ps(ps, false, "tx req") == RTW_PHL_STATUS_SUCCESS) { + _leave_success_hdlr(ps); + ret = MDL_RET_SUCCESS; + } else { + _leave_fail_hdlr(ps); + } + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +static enum phl_mdl_ret_code _phy_idle_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_PHY_IDLE\n"); + _cancel_pwr_req(ps, MSG_EVT_ID_FIELD(msg->msg_id)); + /* check enter ips or not */ + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__); + if (_chk_ips_enter(ps)) { + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "phy idle"); + } + ret = MDL_RET_SUCCESS; + } else { + ret = MDL_RET_SUCCESS; + } + + return ret; +} + +/** + * pre-phase handler of msg + * leave ps and return corresponding status + * @ps: see cmd_ps + * @evt_id: evt id of msg + */ +static enum phl_mdl_ret_code +_ext_msg_pre_hdlr(struct cmd_ps *ps, u16 evt_id) +{ + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + /* power request */ + if (_leave_ps(ps, true, "ext msg req") == RTW_PHL_STATUS_SUCCESS) { + _add_pwr_req(ps, evt_id); + _leave_success_hdlr(ps); + return MDL_RET_SUCCESS; + } else { + _leave_fail_hdlr(ps); + } + + return MDL_RET_CANNOT_IO; +} + +/** + * post-phase handler of msg + * cancel power req and chk enter ips or not + * @ps: see cmd_ps + * @evt_id: evt id of msg + */ +static enum phl_mdl_ret_code +_ext_msg_post_hdlr(struct cmd_ps *ps, u16 evt_id) +{ + /* cancel power request */ + _cancel_pwr_req(ps, evt_id); + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__); + if (_chk_ips_enter(ps)) { + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "ext msg done"); + } + + return MDL_RET_SUCCESS; +} + +static void _ps_mr_info_upt(struct cmd_ps *ps, struct rtw_wifi_role_t *role) +{ + struct phl_info_t *phl_info = ps->phl_info; + struct rtw_wifi_role_t *wr = NULL; + u8 role_idx = 0; + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): id %d, type %d, mstate %d\n", __func__, + role->id, role->type, role->mstate); + #ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): is_gc %d\n", __func__, role->is_gc); + #endif + + _os_mem_set(phl_to_drvpriv(phl_info), &ps->mr_info, 0, sizeof(struct _ps_mr_info)); + + for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) { + wr = &(phl_info->phl_com->wifi_roles[role_idx]); + if (wr->active == false) + continue; + #ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS + if (wr->type == PHL_RTYPE_STATION) { + if(wr->is_gc == true && wr->mstate != MLME_NO_LINK) + ps->mr_info.gc_active = true; + } + #endif + if (wr->type == PHL_RTYPE_AP || wr->type == PHL_RTYPE_VAP || + wr->type == PHL_RTYPE_MESH ||wr->type == PHL_RTYPE_P2P_GO) + ps->mr_info.ap_active = (wr->mstate == MLME_NO_LINK) ? false : true; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): gc_active %d, ap_active %d\n", __func__, + ps->mr_info.gc_active, ps->mr_info.ap_active); +} + +static bool _is_ignored_mrc_evt(u16 evt_id) +{ + return false; +} + +static enum phl_mdl_ret_code +_mrc_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + struct rtw_role_cmd *rcmd = NULL; + struct rtw_wifi_role_t *role = NULL; + + if (_is_ignored_mrc_evt(MSG_EVT_ID_FIELD(msg->msg_id))) + return MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_ROLE_NTFY: + if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + if (msg->inbuf && (msg->inlen == sizeof(struct rtw_role_cmd))) { + rcmd = (struct rtw_role_cmd *)msg->inbuf; + role = rcmd->wrole; + _ps_mr_info_upt(ps, role); + } + } + ret = MDL_RET_SUCCESS; + break; + default: + if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_CANNOT_IO; + } else { + ret = MDL_RET_SUCCESS; + } + break; + } + + return ret; +} + +static bool _is_ignored_ser_evt(u16 evt_id) +{ + if (MSG_EVT_SER_M9_L2_RESET != evt_id) + return true; + + return false; +} + +static enum phl_mdl_ret_code +_ser_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (_is_ignored_ser_evt(MSG_EVT_ID_FIELD(msg->msg_id))) + return MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_SER_M9_L2_RESET: + ret = MDL_RET_SUCCESS; + break; + default: + if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", + __func__, + MSG_MDL_ID_FIELD(msg->msg_id), + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_CANNOT_IO; + } else { + ret = MDL_RET_SUCCESS; + } + break; + } + + return ret; +} + +static bool _is_ignored_general_evt(u16 evt_id) +{ + bool ret = false; + + switch (evt_id) { + case MSG_EVT_GET_USB_SW_ABILITY: + case MSG_EVT_GET_USB_SPEED: + ret = true; + break; + default: + ret = false; + break; + } + + return ret; +} + +#ifdef RTW_WKARD_LINUX_CMD_WKARD +static enum phl_mdl_ret_code +_linux_cmd_wkard_hdlr(struct cmd_ps *ps) +{ + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + /* power request */ + if (_leave_ps(ps, true, "linux cmd wkard") == RTW_PHL_STATUS_SUCCESS) { + _leave_success_hdlr(ps); + return MDL_RET_SUCCESS; + } else { + _leave_fail_hdlr(ps); + } + + return MDL_RET_CANNOT_IO; +} +#endif /* RTW_WKARD_LINUX_CMD_WKARD */ + +static enum phl_mdl_ret_code +_general_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (_is_ignored_general_evt(MSG_EVT_ID_FIELD(msg->msg_id))) + return MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_CHG_OP_CH_DEF_START: + case MSG_EVT_CHG_OP_CH_DEF_END: + case MSG_EVT_SWCH_START: + case MSG_EVT_PCIE_TRX_MIT: + case MSG_EVT_FORCE_USB_SW: + case MSG_EVT_GET_USB_SPEED: + case MSG_EVT_GET_USB_SW_ABILITY: + case MSG_EVT_CFG_AMPDU: + case MSG_EVT_DFS_PAUSE_TX: + case MSG_EVT_ROLE_RECOVER: + case MSG_EVT_ROLE_SUSPEND: + case MSG_EVT_HAL_SET_L2_LEAVE: + case MSG_EVT_NOTIFY_HAL: + case MSG_EVT_ISSUE_BCN: + case MSG_EVT_STOP_BCN: + case MSG_EVT_SEC_KEY: + case MSG_EVT_ROLE_START: + case MSG_EVT_ROLE_CHANGE: + case MSG_EVT_ROLE_STOP: + case MSG_EVT_STA_INFO_CTRL: + case MSG_EVT_STA_MEDIA_STATUS_UPT: + case MSG_EVT_CFG_CHINFO: + case MSG_EVT_STA_CHG_STAINFO: +#ifdef RTW_WKARD_LINUX_CMD_WKARD + case MSG_EVT_LINUX_CMD_WRK_TRI_PS: +#endif /* RTW_WKARD_LINUX_CMD_WKARD */ + case MSG_EVT_DBG_RX_DUMP: + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) in %s phase.\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id), + (IS_MSG_IN_PRE_PHASE(msg->msg_id) ? "pre-protocol" : "post-protocol")); + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + ret = _ext_msg_pre_hdlr(ps, MSG_EVT_ID_FIELD(msg->msg_id)); + else + ret = _ext_msg_post_hdlr(ps, MSG_EVT_ID_FIELD(msg->msg_id)); + break; +#ifdef RTW_WKARD_LINUX_CMD_WKARD + case MSG_EVT_LINUX_CMD_WRK: + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + ret = _linux_cmd_wkard_hdlr(ps); + else + ret = MDL_RET_SUCCESS; + break; +#endif /* RTW_WKARD_LINUX_CMD_WKARD */ + case MSG_EVT_WATCHDOG: + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + ret = _ps_watchdog_pre_hdlr(ps); + if (ret == MDL_RET_SUCCESS) { + ps->rssi_bcn_min = phl_get_min_rssi_bcn(ps->phl_info); + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): update rssi_bcn_min to %d\n", __func__, ps->rssi_bcn_min); + } + } else { + ret = _ps_watchdog_post_hdlr(ps); + } + break; + case MSG_EVT_RF_ON: + if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_RF_ON\n"); + ps->rej_pwr_req = false; + } + ret = MDL_RET_SUCCESS; + break; + case MSG_EVT_RF_OFF: + if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_RF_OFF\n"); + ps->rej_pwr_req = true; + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "msg rf off"); + } + ret = MDL_RET_SUCCESS; + break; + case MSG_EVT_PHY_ON: + ret = _phy_on_msg_hdlr(ps, msg); + break; + case MSG_EVT_PHY_IDLE: + ret = _phy_idle_msg_hdlr(ps, msg); + break; + default: + if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", + __func__, + MSG_MDL_ID_FIELD(msg->msg_id), + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_CANNOT_IO; + } else { + ret = MDL_RET_SUCCESS; + } + break; + } + + return ret; +} + +static bool _is_ignored_datapath_evt(u16 evt_id) +{ + return false; +} + +static enum phl_mdl_ret_code +_datapath_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (_is_ignored_datapath_evt(MSG_EVT_ID_FIELD(msg->msg_id))) + return MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_TRX_PWR_REQ: + ret = _tx_pwr_req_msg_hdlr(ps, msg); + break; + default: + if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", + __func__, + MSG_MDL_ID_FIELD(msg->msg_id), + MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_CANNOT_IO; + } else { + ret = MDL_RET_SUCCESS; + } + break; + } + + return ret; +} + +/** + * bypass msg of specific module + * @msg: see phl_msg + */ +static bool _is_ignored_mdl(struct phl_msg *msg) +{ + if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_BTC) + return true; + if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_LED) + return true; + + return false; +} + +static enum phl_mdl_ret_code +_ps_mdl_hdl_external_evt(void *dispr, struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + if (_is_ignored_mdl(msg)) { + /* PHL_INFO("[PS_CMD], %s(): ignore MDL_ID(%d)-EVT_ID(%d).\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); */ + return MDL_RET_SUCCESS; + } + + switch (MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_MDL_GENERAL: + ret = _general_mdl_msg_hdlr(ps, msg); + break; + case PHL_MDL_MRC: + ret = _mrc_mdl_msg_hdlr(ps, msg); + break; + case PHL_MDL_TX: + case PHL_MDL_RX: + ret = _datapath_mdl_msg_hdlr(ps, msg); + break; + case PHL_MDL_SER: + ret = _ser_mdl_msg_hdlr(ps, msg); + break; + /* handle ohters mdl here */ + default: + if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + ret = MDL_RET_CANNOT_IO; + } else { + ret = MDL_RET_SUCCESS; + } + break; + } + + return ret; +} + +static enum phl_mdl_ret_code _ps_cap_chg_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_ps_rt_rson rt_rson = PS_RT_RSON_NONE; + bool ps_allow = false; + struct rt_ps *rt_ps_info= NULL; + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + rt_ps_info = (struct rt_ps *)msg->inbuf; + ps_allow = rt_ps_info->ps_allow; + rt_rson = rt_ps_info->rt_rson; + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): update -> ps_allow(%d), reason(%d).\n", __func__, ps_allow, rt_rson); + + if (ps_allow) { + if (TEST_STATUS_FLAG(ps->rt_stop_rson, rt_rson) == true) + CLEAR_STATUS_FLAG(ps->rt_stop_rson, rt_rson); + else + return MDL_RET_SUCCESS; + } else { + if (TEST_STATUS_FLAG(ps->rt_stop_rson, rt_rson) == false) + SET_STATUS_FLAG(ps->rt_stop_rson, rt_rson); + else + return MDL_RET_SUCCESS; + } + + if (ps->rej_pwr_req == true) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__); + return MDL_RET_CANNOT_IO; + } + + if (ps->rt_stop_rson != PS_RT_RSON_NONE) { + if (_leave_ps(ps, true, "cap chg") == RTW_PHL_STATUS_SUCCESS) { + _leave_success_hdlr(ps); + return MDL_RET_SUCCESS; + } else { + _leave_fail_hdlr(ps); + return MDL_RET_CANNOT_IO; + } + } + } else { + if (ps->rt_stop_rson == PS_RT_RSON_NONE) { + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__); + if (_chk_ips_enter(ps)) { + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "cap chg"); + } + } + } + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ps_period_chk_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + u16 macid = 0xFFFF; + + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + return MDL_RET_SUCCESS; + + if (ps->ps_state == PS_STATE_LEAVED) { + + PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): \n", __func__); + if (_chk_lps_enter(ps, &macid)) + _enter_ps(ps, PS_MODE_LPS, macid, "period chk"); + /* else if (_chk_ips_enter(ps)) + _enter_ps(ps, PS_MODE_IPS, 0xFFFF, "period chk"); */ + } + + _os_set_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer, CMD_PS_TIMER_PERIOD); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ps_dbg_lps_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + u16 macid = 0xFFFF; + u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id); + + if (evt_id == MSG_EVT_PS_DBG_LPS_ENTER) { + if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + if (!_chk_wrole_with_ps_mode(ps, PS_MODE_LPS, &macid)) + return MDL_RET_SUCCESS; + _enter_ps(ps, PS_MODE_LPS, macid, "dbg lps enter"); + ps->rej_pwr_req = true; + } + } else { /* MSG_EVT_PS_DBG_LPS_LEAVE */ + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) { + _leave_ps(ps, true, "dbg lps leave"); + ps->rej_pwr_req = false; + } + } + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code _ps_dbg_ips_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg) +{ + /* fw do not support ips currently */ + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_ps_mdl_hdl_internal_evt(void *dispr, struct cmd_ps *ps, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_PHY_ON: + ret = _phy_on_msg_hdlr(ps, msg); + break; + case MSG_EVT_PHY_IDLE: + ret = _phy_idle_msg_hdlr(ps, msg); + break; + case MSG_EVT_PS_CAP_CHG: + ret = _ps_cap_chg_msg_hdlr(ps, msg); + break; + case MSG_EVT_PS_PERIOD_CHK: + ret = _ps_period_chk_hdlr(ps, msg); + break; + case MSG_EVT_PS_DBG_LPS_ENTER: + case MSG_EVT_PS_DBG_LPS_LEAVE: + ret = _ps_dbg_lps_msg_hdlr(ps, msg); + break; + case MSG_EVT_PS_DBG_IPS_ENTER: + case MSG_EVT_PS_DBG_IPS_LEAVE: + ret = _ps_dbg_ips_msg_hdlr(ps, msg); + break; + default: + ret = MDL_RET_CANNOT_IO; + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_ps_mdl_msg_hdlr(void *dispr, void *priv, struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + struct cmd_ps *ps = (struct cmd_ps *)priv; + + if (IS_MSG_FAIL(msg->msg_id)) { + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) fail.\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + return MDL_RET_SUCCESS; + } + + switch (MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_MDL_POWER_MGNT: + ret = _ps_mdl_hdl_internal_evt(dispr, ps, msg); + break; + default: + ret = _ps_mdl_hdl_external_evt(dispr, ps, msg); + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_ps_mdl_set_info(void *dispr, void *priv, struct phl_module_op_info *info) +{ + struct cmd_ps *ps = (struct cmd_ps *)priv; + + switch (info->op_code) { + case PS_MDL_OP_CANCEL_PWR_REQ: + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): cancel pwr req, evt_id %d\n", __func__, *(u16 *)info->inbuf); + if (ps->rej_pwr_req == false) + _cancel_pwr_req(ps, *(u16 *)info->inbuf); + break; + case PS_MDL_OP_BTC_PWR_REQ: + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): btc req pwr %d\n", __func__, *(bool *)info->inbuf); + ps->btc_req_pwr = *(bool *)info->inbuf; + break; + } + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_ps_mdl_query_info(void *dispr, void *priv, struct phl_module_op_info *info) +{ + struct cmd_ps *ps = (struct cmd_ps *)priv; + u8 pwr_lvl = PS_PWR_LVL_PWROFF; + struct phl_cmd_ps_basic_info *basic_info = NULL; + + /* PHL_INFO("[PS_CMD], %s(): opcode %d.\n", __func__, info->op_code); */ + + switch (info->op_code) { + case PS_MDL_OP_CUR_PWR_LVL: + pwr_lvl = ps->cur_pwr_lvl; + _os_mem_cpy(phl_to_drvpriv(ps->phl_info), (void *)info->inbuf, + &pwr_lvl, sizeof(pwr_lvl)); + break; + case PS_MDL_OP_BASIC_INFO: + basic_info = (struct phl_cmd_ps_basic_info *)info->inbuf; + basic_info->ps_mode = ps->ps_mode; + basic_info->cur_pwr_lvl = ps->cur_pwr_lvl; + basic_info->rej_pwr_req = ps->rej_pwr_req; + basic_info->btc_req_pwr = ps->btc_req_pwr; + basic_info->rt_stop_rson = ps->rt_stop_rson; + basic_info->ap_active = ps->mr_info.ap_active; + basic_info->gc_active = ps->mr_info.gc_active; + basic_info->sta = ps->sta; + /* enter/leave ps reason */ + _os_mem_set(phl_to_drvpriv(ps->phl_info), basic_info->enter_rson, 0, MAX_CMD_PS_RSON_LENGTH); + _os_mem_cpy(phl_to_drvpriv(ps->phl_info), basic_info->enter_rson, ps->enter_rson, MAX_CMD_PS_RSON_LENGTH); + _os_mem_set(phl_to_drvpriv(ps->phl_info), basic_info->leave_rson, 0, MAX_CMD_PS_RSON_LENGTH); + _os_mem_cpy(phl_to_drvpriv(ps->phl_info), basic_info->leave_rson, ps->leave_rson, MAX_CMD_PS_RSON_LENGTH); + break; + } + + return MDL_RET_SUCCESS; +} + +enum rtw_phl_status phl_register_ps_module(struct phl_info_t *phl_info) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng); + struct phl_bk_module_ops bk_ops = {0}; + u8 i = 0; + + PHL_INFO("[PS_CMD], %s(): \n", __func__); + + bk_ops.init = _ps_mdl_init; + bk_ops.deinit = _ps_mdl_deinit; + bk_ops.start = _ps_mdl_start; + bk_ops.stop = _ps_mdl_stop; + bk_ops.msg_hdlr = _ps_mdl_msg_hdlr; + bk_ops.set_info = _ps_mdl_set_info; + bk_ops.query_info = _ps_mdl_query_info; + + for (i = 0; i < disp_eng->phy_num; i++) { + phl_status = phl_disp_eng_register_module(phl_info, i, + PHL_MDL_POWER_MGNT, &bk_ops); + if (phl_status != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("register cmd PS module of phy%d failed.\n", i + 1); + break; + } + } + + return phl_status; +} + +u8 phl_ps_get_cur_pwr_lvl(struct phl_info_t *phl_info) +{ + struct phl_module_op_info op_info = {0}; + u8 pwr_lvl = PS_PWR_LVL_MAX; + + op_info.op_code = PS_MDL_OP_CUR_PWR_LVL; + op_info.inbuf = (u8 *)&pwr_lvl; + op_info.inlen = sizeof(pwr_lvl); + + phl_disp_eng_query_bk_module_info(phl_info, HW_BAND_0, + PHL_MDL_POWER_MGNT, &op_info); + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): pwr lvl(%s)\n", __func__, phl_ps_pwr_lvl_to_str(pwr_lvl)); + + return pwr_lvl; +} + +bool phl_ps_is_datapath_allowed(struct phl_info_t *phl_info) +{ + struct phl_module_op_info op_info = {0}; + bool io_allowed = false; + u8 pwr_lvl = PS_PWR_LVL_MAX; + struct rtw_ps_cap_t *ps_cap = _get_ps_cap(phl_info); + + if (!ps_cap->lps_pause_tx) + return true; + + op_info.op_code = PS_MDL_OP_CUR_PWR_LVL; + op_info.inbuf = (u8 *)&pwr_lvl; + op_info.inlen = sizeof(pwr_lvl); + + phl_disp_eng_query_bk_module_info(phl_info, HW_BAND_0, + PHL_MDL_POWER_MGNT, &op_info); + + if (pwr_lvl == PS_PWR_LVL_PWRON) + io_allowed = true; + + return io_allowed; +} + +static void _ps_set_rt_cap_done(void *priv, struct phl_msg *msg) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + + if (msg->inbuf && msg->inlen) { + _os_mem_free(phl_to_drvpriv(phl_info), + msg->inbuf, msg->inlen); + } + +} + +void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct rt_ps *ps_rt_info = NULL; + + ps_rt_info = (struct rt_ps *)_os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(struct rt_ps)); + if (ps_rt_info == NULL) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to alloc ps_rt_info memory.\n", __func__); + return; + } + + ps_rt_info->rt_rson = rt_rson; + ps_rt_info->ps_allow = ps_allow; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PS_CAP_CHG); + msg.band_idx = band_idx; + msg.inbuf = (u8*)ps_rt_info; + msg.inlen = sizeof(struct rt_ps); + attr.completion.completion = _ps_set_rt_cap_done; + attr.completion.priv = phl_info; + + if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != + RTW_PHL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to notify batter change.\n", __func__); + goto cmd_fail; + } + + return; + +cmd_fail: + _os_mem_free(phl_to_drvpriv(phl_info), ps_rt_info, sizeof(ps_rt_info)); +} + +void phl_ps_dbg_set_ps(struct phl_info_t *phl_info, u8 ps_mode, bool enter) +{ + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u16 evt_id = 0; + + if (ps_mode == PS_MODE_LPS) { + evt_id = (enter ? MSG_EVT_PS_DBG_LPS_ENTER : MSG_EVT_PS_DBG_LPS_LEAVE); + } else if (ps_mode == PS_MODE_IPS) { + PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): dbg ips is not support now.\n", __func__); + /* evt_id = (enter ? MSG_EVT_PS_DBG_IPS_ENTER : MSG_EVT_PS_DBG_IPS_LEAVE); */ + } else { + return; + } + + PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): debug set %s %s\n", __func__, + phl_ps_ps_mode_to_str(ps_mode), (enter ? "enter" : "leave")); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id); + msg.band_idx = HW_BAND_0; + + if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != + RTW_PHL_STATUS_SUCCESS) { + PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to set dbg ps.\n", __func__); + } + + return; +} + +enum rtw_phl_status +rtw_phl_ps_set_rf_state(void *phl, u8 band_idx, enum rtw_rf_state rf_state) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum phl_msg_evt_id evt_id = (rf_state == RTW_RF_ON) ? MSG_EVT_RF_ON : MSG_EVT_RF_OFF; + + phl_cmd_enqueue(phl_info, band_idx, evt_id, NULL, 0, NULL, PHL_CMD_WAIT, 0); + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status phl_ps_hal_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct phl_module_op_info op_info = {0}; + + if (src != HAL_BTC_PWR_REQ) + return RTW_PHL_STATUS_FAILURE; + + op_info.op_code = PS_MDL_OP_BTC_PWR_REQ; + op_info.inbuf = (u8 *)&pwr_req; + status = phl_disp_eng_set_bk_module_info(phl_info, HW_BAND_0, + PHL_MDL_POWER_MGNT, &op_info); + + return status; +} +#endif diff --git a/phl/phl_cmd_ps.h b/phl/phl_cmd_ps.h new file mode 100644 index 0000000..6af6eab --- /dev/null +++ b/phl/phl_cmd_ps.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * + * Copyright(c) 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CMD_PS_H_ +#define _PHL_CMD_PS_H_ +#ifdef CONFIG_POWER_SAVE +enum ps_mdl_opcode { + PS_MDL_OP_NONE = 0, + PS_MDL_OP_CANCEL_PWR_REQ, + PS_MDL_OP_CUR_PWR_LVL, + PS_MDL_OP_BASIC_INFO, + PS_MDL_OP_BTC_PWR_REQ +}; + +#define MAX_CMD_PS_RSON_LENGTH 30 +struct phl_cmd_ps_basic_info { + u8 ps_mode; + u8 cur_pwr_lvl; + bool rej_pwr_req; + bool btc_req_pwr; + enum phl_ps_rt_rson rt_stop_rson; + bool ap_active; + bool gc_active; + struct rtw_phl_stainfo_t *sta; + char enter_rson[MAX_CMD_PS_RSON_LENGTH]; + char leave_rson[MAX_CMD_PS_RSON_LENGTH]; +}; + +enum rtw_phl_status phl_register_ps_module(struct phl_info_t *phl_info); +u8 phl_ps_get_cur_pwr_lvl(struct phl_info_t *phl_info); +bool phl_ps_is_datapath_allowed(struct phl_info_t *phl_info); +void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson); +void phl_ps_dbg_set_ps(struct phl_info_t *phl_info, u8 ps_mode, bool enter); + +#endif +#endif /* _PHL_CMD_PS_H_ */ diff --git a/phl/phl_cmd_scan.c b/phl/phl_cmd_scan.c new file mode 100644 index 0000000..48d7a5c --- /dev/null +++ b/phl/phl_cmd_scan.c @@ -0,0 +1,966 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: vincent_fann@realtek.com + * + *****************************************************************************/ +#define _PHL_CMD_SCAN_C_ +#include "phl_headers.h" +#include "phl_scan.h" + +#define param_to_phlcom(_param) (_param->wifi_role->phl_com) + +#ifdef CONFIG_PHL_CMD_SCAN + + +enum _CMD_SCAN_STATE { + CMD_SCAN_ACQUIRE = BIT0, + CMD_SCAN_STARTED = BIT1, + CMD_SCAN_DF_IO = BIT2, /* Disable Function : IO */ +}; + +static void _cmd_scan_timer(void* role); + +#define DBG_SCAN_CHAN_DUMP + +#ifdef DBG_SCAN_CHAN_DUMP +static void +_cmd_estimated_swch_seq(struct rtw_phl_scan_param *param, u8 op_num) +{ + u8 chidx = 0; + u8 opidx = 0; + u8 total_ch_num = 0; + + if ((param->back_op_mode == SCAN_BKOP_CNT) && + (param->back_op_ch_cnt == 0)) { + PHL_ERR("%s bkop_cnt == 0\n", __func__); + _os_warn_on(1); + return; + } + + /*swicth channel sequence by cmd_scan's estimated */ + PHL_INFO("%s:: Estimated channel sequence:\n", __func__); + + if (param->back_op_mode == SCAN_BKOP_CNT) { + PHL_INFO("[SCAN_BKOP_CNT]\n"); + for(chidx = 0; chidx < param->ch_num; chidx++) { + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "%3d, ", param->ch[chidx].channel); + total_ch_num++; + if(!((chidx + 1) % param->back_op_ch_cnt)) { + if (op_num) { + for(opidx = 0; opidx < op_num; opidx++) { + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, + "[%3d], ", param->back_op_ch[opidx].channel); + total_ch_num++; + } + } + } + if(!((chidx + 1) % (param->back_op_ch_cnt * 2))) + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n"); + } + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n"); + + } + #ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME + else if (param->back_op_mode == SCAN_BKOP_TIMER) { + u16 ch_dur; + + PHL_INFO("[SCAN_BKOP_TIMER]\n"); + for(chidx = 0; chidx < param->ch_num; chidx++) { + total_ch_num++; + ch_dur = (op_num) ? param->back_op_off_ch_dur_ms : param->ch[chidx].duration; + PHL_INFO("\t%3d, dur:%d(ms)\n", param->ch[chidx].channel, ch_dur); + } + if (op_num) { + for(opidx = 0; opidx < op_num; opidx++) { + total_ch_num++; + PHL_INFO("\t[%3d], dur:%d(ms)\n", + param->back_op_ch[opidx].channel, param->back_op_ch[opidx].duration); + } + } + PHL_INFO("max_listen_time:%d (ms)\n", param->max_listen_time); + PHL_INFO("op_ch_dur_ms:%d, off_ch_dur_ms:%d, off_ch_ext_dur_ms:%d (ms)", + param->back_op_ch_dur_ms, + param->back_op_off_ch_dur_ms, + param->back_op_off_ch_ext_dur_ms); + } + #endif + else if (param->back_op_mode == SCAN_BKOP_NONE) { + PHL_INFO("[SCAN_BKOP_NONE]\n"); + for(chidx = 0; chidx < param->ch_num; chidx++) { + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "%3d, ", param->ch[chidx].channel); + total_ch_num++; + if(!((chidx + 1) % 6)) + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n"); + } + PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n"); + } + + PHL_INFO("Scan chan num:%d , Total num:%d, repeat:%d\n", + param->ch_num, total_ch_num, param->repeat); + PHL_INFO("--------\n"); +} +#endif /*DBG_SCAN_CHAN_DUMP*/ + +static void +_cmd_scan_update_chlist(void *drv, struct rtw_phl_scan_param *param) +{ + u8 idx = 0; + + INIT_LIST_HEAD(¶m->chlist.queue); + for(idx = 0; idx < param->ch_num; idx++) { + INIT_LIST_HEAD(¶m->ch[idx].list); + pq_push(drv, ¶m->chlist, ¶m->ch[idx].list, _tail, _ps); + } +} + +/* + * Insert op channel list + * Ex. ch_intvl =3 + * ch_idx : -1, 0, 1, 2, 3, 4, 5, 6 + * ^ ^ + * op0~op5 op0~op5 + * + * => 0,1,2,[op0],[op1],3,4,5,[op0],[op1],6,7,8,[op0],[op1] + */ + +static inline void +_cmd_scan_enqueue_opch(void *drv, struct rtw_phl_scan_param *param, struct phl_queue *q) +{ + u8 idx = 0; + + for(idx = 0; idx < MAX_WIFI_ROLE_NUMBER; idx ++) { + if(param->back_op_ch[idx].channel) + pq_push(drv, ¶m->chlist, ¶m->back_op_ch[idx].list, _first, _ps); + else + break; + } +} +static struct phl_scan_channel *_cmd_scan_select_chnl( + void *drv, struct rtw_phl_scan_param *param) +{ + struct phl_scan_channel *scan_ch = NULL; + _os_list* obj = NULL; + bool back_op_is_required = (param->back_op_ch[0].channel)? true:false; + +next_ch: + if(pq_pop(drv, ¶m->chlist, &obj, _first, _ps)) { + scan_ch = (struct phl_scan_channel*)obj; + + if(scan_ch->scan_mode == NORMAL_SCAN_MODE) { + /* 1- enable, 2- BK_CNT mode, 3- prev is non-op, 4- ch_intvl's turn */ + if (back_op_is_required && param->back_op_mode == SCAN_BKOP_CNT) { + if(param->scan_ch && + !((param->ch_idx + 1) % param->back_op_ch_cnt)) { + _cmd_scan_enqueue_opch(drv, param, ¶m->chlist); + } + } + param->ch_idx++; + } + #ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME + else if (scan_ch->scan_mode == P2P_LISTEN_MODE) { + if (back_op_is_required && param->back_op_mode == SCAN_BKOP_TIMER) { + scan_ch->duration = param->back_op_off_ch_dur_ms; + _cmd_scan_enqueue_opch(drv, param, ¶m->chlist); + } + param->ch_idx++; + } + #endif + param->scan_ch = scan_ch; + } + else if(param->repeat > 0) { + _cmd_scan_update_chlist(drv, param); + param->ch_idx = 0; + /* 255 means loop forever */ + if (param->repeat != 255) + param->repeat--; + goto next_ch; + } + else { + return NULL; + } + + PHL_INFO("%s: repeat[%d] ch_idx=[%d/%d], ch_number=%d, scan_mode= %s\n", __func__, + param->repeat, param->ch_idx, param->ch_num, param->scan_ch->channel, + (param->scan_ch->scan_mode == BACKOP_MODE)? "OP_CH": "Non-OP"); + + return param->scan_ch; +} + +/* Notification complete */ +void _cmd_scan_timer_notify_cb( + void *role, struct phl_msg *msg) +{ + if (IS_MSG_CANNOT_IO(msg->msg_id)) { + PHL_ERR("%s: SWCH_DONE failure by CANNOT IO\n", __func__); + return; + } + + if (IS_MSG_CANCEL(msg->msg_id)) { + /* Last event occured MSG_STATUS_PENDING */ + PHL_ERR("%s: SWCH_DONE pending or abort Occurred!\n", __func__); + + _cmd_scan_timer(role); + } +} + +static void _cmd_scan_timer(void* role) +{ + struct rtw_wifi_role_t *wifi_role = (struct rtw_wifi_role_t *)role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + u8 band_idx = wifi_role->hw_band; + + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + PHL_INFO("%s \n", __func__); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN); +/** When listen state of each channel entry expired, + * timer callback send MSG_EVT_LISTEN_STATE_EXPIRE for additional condition check + * If nothing specitail occured, then send MSG_EVT_SWCH_START to proceed for the rest of channel list + * therefore, additional process delay for MSG_EVT_LISTEN_STATE_EXPIRE would prolong listen period + * */ + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_LISTEN_STATE_EXPIRE); + msg.rsvd[0] = (u8*)role; + msg.band_idx = band_idx; + + attr.completion.completion = _cmd_scan_timer_notify_cb; + attr.completion.priv = role; + + if(phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s: [SCAN_TIMER] phl_disp_eng_send_msg failed !\n", __func__); +} + +/* Notification complete */ +void _cmd_swch_done_notify_cb( + void *drv, struct phl_msg *msg) +{ + if (msg->inbuf) { + _os_mem_free(drv, msg->inbuf, msg->inlen); + } +} + +enum rtw_phl_status _cmd_swch_done_notify( + void *dispr, void *drv, struct rtw_phl_scan_param *param) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct phl_scan_channel *scan_ch = param->scan_ch; + struct rtw_phl_com_t *phl_com = param_to_phlcom(param); + struct phl_info_t *phl = (struct phl_info_t *) phl_com->phl_priv; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + u8 *info = NULL; + u8 idx = 0xff; + + info = _os_mem_alloc(drv, sizeof(struct phl_scan_channel)); + if (info == NULL) { + PHL_ERR("%s: [SWCH_DONE] alloc buffer failed!\n", __func__); + return RTW_PHL_STATUS_FAILURE; + } + + _os_mem_cpy(drv, info, scan_ch, sizeof(*scan_ch)); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SWCH_DONE); + + attr.opt = MSG_OPT_CLR_SNDR_MSG_IF_PENDING; + attr.completion.completion = _cmd_swch_done_notify_cb; + attr.completion.priv = drv; + + msg.inbuf = info; + msg.inlen = sizeof(struct phl_scan_channel); + msg.rsvd[0] = (u8*)param->wifi_role; + phl_dispr_get_idx(dispr, &idx); + msg.band_idx = idx; + pstatus = phl_disp_eng_send_msg(phl, &msg, &attr, NULL); + if(pstatus != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s: [SWCH_DONE] phl_disp_eng_send_msg failed!\n", __func__); + _os_mem_free(drv, info, sizeof(struct phl_scan_channel)); + } + return pstatus; +} + +void _cmd_scan_end( + void *drv, struct rtw_phl_scan_param *param) +{ + struct rtw_wifi_role_t *wifi_role = param->wifi_role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + + PHL_INFO("_cmd_scan_end \n"); + + param->end_time = _os_get_cur_time_ms(); + + /* dump scan time */ + param->total_scan_time = + phl_get_passing_time_ms(param->enqueue_time); + + pq_deinit(drv, ¶m->chlist); + + /* acquire state */ + _os_cancel_timer(drv, ¶m->scan_timer); + _os_release_timer(drv, ¶m->scan_timer); + + if(TEST_STATUS_FLAG(param->state, CMD_SCAN_STARTED) && + !TEST_STATUS_FLAG(param->state, CMD_SCAN_DF_IO) ) + { + rtw_hal_com_scan_restore_tx_lifetime(phl_info->hal, wifi_role->hw_band); + + rtw_hal_scan_set_rxfltr_by_mode(phl_info->hal, wifi_role->hw_band, + false, ¶m->fltr_mode); + rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, false); + + rtw_hal_notification(phl_info->hal, MSG_EVT_SCAN_END, wifi_role->hw_band); + } + + if (param->ops->scan_complete) + param->ops->scan_complete(param->priv, param); +} + +/* Notification complete */ +void _cmd_abort_notify_cb( + void *drv, struct phl_msg *msg) +{ + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param *)msg->inbuf; + + if(IS_MSG_CANNOT_IO(msg->msg_id)) + SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO); + + _cmd_scan_end(drv, param); +} + +void _cmd_abort_notify(void *dispr, void *drv, + struct rtw_phl_scan_param *param, bool abort) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_com_t *phl_com = param_to_phlcom(param); + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + struct phl_info_t *phl = (struct phl_info_t *) phl_com->phl_priv; + u8 idx = 0xff; + + if(TEST_STATUS_FLAG(param->state, CMD_SCAN_ACQUIRE)) + { + param->result = SCAN_REQ_CANCEL; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SCAN_END); + + if(abort) + attr.opt = MSG_OPT_SEND_IN_ABORT; + attr.completion.completion = _cmd_abort_notify_cb; + attr.completion.priv = drv; + + msg.inbuf = (u8*)param; + msg.rsvd[0] = (u8*)param->wifi_role; + #ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + msg.rsvd[1] = (u8*)param->ops->scan_issue_null_data; + #endif + + phl_dispr_get_idx(dispr, &idx); + msg.band_idx = idx; + pstatus = phl_disp_eng_send_msg(phl, &msg, &attr, NULL); + if (RTW_PHL_STATUS_SUCCESS != pstatus) { + /* (1) dispr_stop + (2) idle msg empty .*/ + + PHL_ERR("%s :: [Abort] dispr_send_msg failed (0x%X)\n", + __func__, pstatus); + + if(pstatus == RTW_PHL_STATUS_UNEXPECTED_ERROR || + TEST_STATUS_FLAG(phl_com->dev_state, RTW_DEV_SURPRISE_REMOVAL)) { + /* clean sw resource only */ + /* (1) driver is going to unload */ + /* (2) Supprise remove */ + SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO); + } + _cmd_abort_notify_cb(drv, &msg); + } + } + else { + param->result = SCAN_REQ_ABORT; + pq_deinit(drv, ¶m->chlist); + + if (param->ops->scan_complete) + param->ops->scan_complete(param->priv, param); + } +} + +enum phl_mdl_ret_code _cmd_scan_fail_ev_hdlr( + void* dispr, void* priv, struct phl_msg* msg) +{ + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + struct rtw_wifi_role_t *wifi_role = param->wifi_role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + void *d = phlcom_to_drvpriv(phl_com); + u8 idx = 0xff; + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_SCAN); + phl_dispr_get_idx(dispr, &idx); + nextmsg.band_idx = idx; + switch(MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_SCAN_START: + /* fall through */ + case MSG_EVT_SWCH_START: + /* fall through */ + case MSG_EVT_SWCH_DONE: + PHL_INFO("SCAN_START/SWCH_START/SWCH_DONE:: failed/timeout handler \n"); + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SCAN_END); + nextmsg.rsvd[0] = (u8*)param->wifi_role; + #ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + nextmsg.rsvd[1] = (u8*)param->ops->scan_issue_null_data; + #endif + pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(pstatus != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s :: [SWCH_START][1] phl_disp_eng_send_msg failed\n", __func__); + break; + + case MSG_EVT_SCAN_END: + // free token + // release timer + PHL_INFO("MSG_EVT_SCAN_END:: failed/timeout handler \n"); + pstatus = phl_disp_eng_free_token(phl_info, idx, ¶m->token); + if(pstatus == RTW_PHL_STATUS_SUCCESS) + { + if(IS_MSG_CANNOT_IO(msg->msg_id)) + SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO); + + _cmd_scan_end(d, param); + } + break; + + default: + /* unknown state */ + break; + } + + return MDL_RET_SUCCESS; +} + +enum phl_mdl_ret_code _cmd_scan_hdl_external_evt( + void* dispr, void* priv, struct phl_msg* msg) +{ + PHL_DBG("%s :: From others MDL =%d , EVT_ID=%d\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + return MDL_RET_IGNORE; +} + +u8 _cmd_chk_ext_act_scan(struct rtw_phl_scan_param *param) +{ +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + /** suppose to query the time of last recieved beacon in current channel here + * then change state to EXT_ACT_SCAN_TRIGGER if needed + * but, PHL does not store bss list at the moment, therefore, + * core layer use set_info (FG_REQ_OP_NOTIFY_BCN_RCV) to notify scan module incoming bcn + * and change state to EXT_ACT_SCAN_TRIGGER accordingly. + */ +#endif + if (param->scan_ch->type == RTW_PHL_SCAN_PASSIVE && + param->scan_ch->ext_act_scan == EXT_ACT_SCAN_TRIGGER) { + if (param->ops->scan_issue_pbreq) + param->ops->scan_issue_pbreq(param->priv, param); + param->scan_ch->ext_act_scan = EXT_ACT_SCAN_DONE; + return true; + } + return false; +} + +void +_cmd_scan_start(struct phl_info_t *phl_info, + struct rtw_wifi_role_t *wifi_role, + struct rtw_phl_scan_param *param) +{ + rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, true); + rtw_hal_scan_set_rxfltr_by_mode(phl_info->hal, wifi_role->hw_band, + true, ¶m->fltr_mode); + rtw_hal_com_scan_set_tx_lifetime(phl_info->hal, wifi_role->hw_band); +} + +enum phl_mdl_ret_code _cmd_scan_hdl_internal_evt( + void* dispr, void* priv, struct phl_msg* msg) +{ + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + struct rtw_wifi_role_t *wifi_role = param->wifi_role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = phl_com->phl_priv; + void *d = phlcom_to_drvpriv(phl_com); + u32 diff_time = 0; + + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + u8 idx = 0xff; + struct phl_scan_channel *scan_ch = NULL; + bool tx_pause = true; + struct rtw_chan_def chdef = {0}; + + phl_dispr_get_idx(dispr, &idx); + diff_time = phl_get_passing_time_ms(param->enqueue_time); + + if (param->max_scan_time && diff_time >= param->max_scan_time) { + PHL_WARN("%s:: Timeout! %d > max_time %d\n", + __func__, diff_time, param->max_scan_time); + + /* Abort scan request */ + /* Based on [CN3AXSW-552] + * ex. max_scan_time = 4sec + * Usb dongle would abort scan_req in 29~33th chnl + * If chnllist insert op-chnl, scan_req would be aborted in 21~23th chnl. + * It means that usb dongle always can't do fully scan. + * So, abort scan_req or not, depend on core layer. + */ + /*_cmd_scan_fail_ev_hdlr(dispr, priv, msg); + return MDL_RET_FAIL; */ + } + else { + PHL_INFO("%s:: TimeIntvl: %u \n", __func__, diff_time); + } + + #ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME + if (param->max_listen_time && diff_time >= param->max_listen_time) { + PHL_WARN("%s:: Timeout! %d > max_listen_time %d\n", + __func__, diff_time, param->max_listen_time); + #if 0 + _cmd_scan_fail_ev_hdlr(dispr, priv, msg); + return MDL_RET_FAIL; + #endif + } + #endif + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_SCAN); + nextmsg.band_idx = idx; + + switch(MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_SCAN_START: + _cmd_scan_start(phl_info, wifi_role, param); + rtw_hal_notification(phl_info->hal, MSG_EVT_SCAN_START, + wifi_role->hw_band); + + /* [scan start notify] */ + if (param->ops->scan_start) + param->ops->scan_start(param->priv, param); + + SET_STATUS_FLAG(param->state, CMD_SCAN_STARTED); + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SWCH_START); + nextmsg.rsvd[0] = (u8*)wifi_role; + pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(pstatus != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s :: [SCAN_START] phl_disp_eng_send_msg failed\n", __func__); + break; + case MSG_EVT_LISTEN_STATE_EXPIRE: + if (_cmd_chk_ext_act_scan(param)) { + _os_set_timer(d, ¶m->scan_timer, param->ext_act_scan_period); + PHL_INFO("%s :: extend listen state of ch %d by %d ms, and reset timer\n", + __func__, param->scan_ch->channel, param->ext_act_scan_period); + break; + } + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SWCH_START); + nextmsg.rsvd[0] = (u8*)wifi_role; + + pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(pstatus != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s :: [LISTEN_STATE_EXPIRE] dispr_send_msg failed\n", __func__); + + break; + + case MSG_EVT_SWCH_START: + /* ycx++ + ycx > length(yclist) ? SCAN_EV_END : switch channel */ + + PHL_INFO("MSG_EVT_SWCH_START \n"); + + /* For the first time, param->scan_ch would be NULL */ + /* Current channel scan_mode */ + if (param->scan_ch && param->scan_ch->scan_mode == BACKOP_MODE) { + tx_pause = false; + } + + scan_ch = _cmd_scan_select_chnl(d, param); + if (scan_ch == NULL) { + /* no more channel, we are done */ + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SCAN_END); + nextmsg.rsvd[0] = (u8*)param->wifi_role; + #ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + nextmsg.rsvd[1] = (u8*)param->ops->scan_issue_null_data; + #endif + pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(pstatus != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s :: [SWCH_START][1] dispr_send_msg failed\n", __func__); + break; + } + + /* Next channel scan_mode */ + if ((scan_ch->scan_mode != BACKOP_MODE) && !tx_pause) { + /* Tx pause */ + rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, true); + tx_pause = true; + } + chdef.band = scan_ch->band; + chdef.chan = (u8)scan_ch->channel; + chdef.bw = scan_ch->bw; + chdef.offset = scan_ch->offset; + + phl_set_ch_bw(wifi_role, &chdef, false); + + if ((scan_ch->scan_mode != BACKOP_MODE) && + (scan_ch->type == RTW_PHL_SCAN_ACTIVE)) { + /* Notify RF to do tssi backup */ + rtw_hal_notification(phl_info->hal, MSG_EVT_SWCH_START, wifi_role->hw_band); + if (param->ops->scan_issue_pbreq) + param->ops->scan_issue_pbreq(param->priv, param); + } + + if ((scan_ch->scan_mode == BACKOP_MODE) && tx_pause) { + /* Tx un-pause */ + rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, false); + } + + _os_set_timer(d, ¶m->scan_timer, scan_ch->duration); + #ifdef DBG_SCAN_CHAN_DUMP + PHL_INFO("[SCAN] band:%d chan:%d bw:%d offset:%d duration:%d (ms)\n", + scan_ch->band, scan_ch->channel, scan_ch->bw, + scan_ch->offset, scan_ch->duration); + #endif + + pstatus = _cmd_swch_done_notify(dispr, d, param); + break; + + case MSG_EVT_SWCH_DONE: + if (param->ops->scan_ch_ready) + param->ops->scan_ch_ready(param->priv, param); + + PHL_INFO("MSG_EVT_SWCH_DONE :: duration=%d\n", param->scan_ch->duration); + break; + + case MSG_EVT_SCAN_END: + PHL_INFO("MSG_EVT_SCAN_END \n"); + pstatus = phl_disp_eng_free_token(phl_info, idx, ¶m->token); + if(pstatus == RTW_PHL_STATUS_SUCCESS) { + + param->result = SCAN_REQ_COMPLETE; + + _cmd_scan_end(d, param); + } + else + PHL_WARN("%s :: [SCAN_END] Abort occurred, skip!\n", __func__); + + break; + + default: + /* unknown state */ + break; + } + + return MDL_RET_SUCCESS; +} + + +enum phl_mdl_ret_code _phl_cmd_scan_req_acquired( + void* dispr, void* priv) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + struct rtw_phl_com_t *phl_com = param_to_phlcom(param); + void *d = phlcom_to_drvpriv(phl_com); + u32 diff_time = 0; + struct phl_info_t *phl_info = phl_com->phl_priv; + u8 idx = 0xff; + + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + FUNCIN(); + + param->start_time = _os_get_cur_time_ms(); + + /* check max scan time */ + if (param->max_scan_time > 0) { + diff_time = phl_get_passing_time_ms(param->enqueue_time); + + if (diff_time >= param->max_scan_time) { + PHL_WARN("%s:: Timeout! %u > max_time %d\n", + __func__, diff_time, param->max_scan_time); + goto error; + } + } + + _os_init_timer(d, ¶m->scan_timer, _cmd_scan_timer, + param->wifi_role, "phl_cmd_scan_req_timer"); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SCAN_START); + msg.rsvd[0] = (u8*)param->wifi_role; + phl_dispr_get_idx(dispr, &idx); + msg.band_idx = idx; + pstatus = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + + if(pstatus != RTW_PHL_STATUS_SUCCESS) { + _os_release_timer(d, ¶m->scan_timer); + goto error; + } + else { + SET_STATUS_FLAG(param->state, CMD_SCAN_ACQUIRE); + return MDL_RET_SUCCESS; + } + +error: + _cmd_abort_notify(dispr, d, param, false); + return MDL_RET_FAIL; +} + +enum phl_mdl_ret_code _phl_cmd_scan_req_abort( + void* dispr, void* priv) +{ + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + struct rtw_phl_com_t *phl_com = param_to_phlcom(param); + void *d = phlcom_to_drvpriv(phl_com); + + PHL_INFO("_phl_cmd_scan_req_abort \n"); + _cmd_abort_notify(dispr, d, param, true); + return MDL_RET_SUCCESS; +} + +enum phl_mdl_ret_code _phl_cmd_scan_req_ev_hdlr( + void* dispr, void* priv, + struct phl_msg* msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + if(IS_MSG_FAIL(msg->msg_id)) { + PHL_INFO("%s :: MSG(%d)_FAIL - EVT_ID=%d \n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + + _cmd_scan_fail_ev_hdlr(dispr, priv, msg); + return MDL_RET_FAIL; + } + + switch(MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_FG_MDL_SCAN: + ret = _cmd_scan_hdl_internal_evt(dispr, priv, msg); + break; + + default: + ret = _cmd_scan_hdl_external_evt(dispr, priv, msg); + break; + } + return ret; +} + +enum phl_mdl_ret_code _phl_cmd_scan_req_set_info( + void* dispr, void* priv, struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + switch(info->op_code) { + case FG_REQ_OP_NOTIFY_BCN_RCV: + { + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + u16 channel = 0; + + /* this workaround might have race condition with background thread*/ + channel = *(u8*)info->inbuf; + if (param->scan_ch && + param->scan_ch->channel == channel && + param->scan_ch->ext_act_scan == EXT_ACT_SCAN_ENABLE) { + param->scan_ch->ext_act_scan = EXT_ACT_SCAN_TRIGGER; + PHL_INFO(" %s :: channel %d extend for active scan\n", __func__, channel); + } + if (param->scan_ch && + param->scan_ch->channel != channel) + PHL_INFO(" %s :: channel %d mismatch from listen channel %d\n", __func__, channel, param->scan_ch->channel); + ret = MDL_RET_SUCCESS; + } + break; + default: + break; + } +#endif + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + return ret; +} + +enum phl_mdl_ret_code _phl_cmd_scan_req_query_info( + void* dispr, void* priv, struct phl_module_op_info* info) +{ + struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv; + struct rtw_phl_com_t *phl_com = param_to_phlcom(param); + void *d = phlcom_to_drvpriv(phl_com); + u8 ucInfo = 0; + void* pInfo = NULL; + + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + + switch(info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8*)param->wifi_role; + ret = MDL_RET_SUCCESS; + break; + + case FG_REQ_OP_GET_MDL_ID: + ucInfo= PHL_FG_MDL_SCAN; + pInfo = (void*) &ucInfo; + info->outlen=1; + _os_mem_cpy(d, (void*)info->outbuf, pInfo, info->outlen); + ret = MDL_RET_SUCCESS; + break; +#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + case FG_REQ_OP_GET_SCAN_PARAM: + info->outbuf = (u8*)param; + ret = MDL_RET_SUCCESS; + break; +#endif + default: + break; + } + + return ret; +} + +#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME +static void +_cmd_scan_update_chparam(void *drv, struct rtw_phl_scan_param *param) +{ + u8 idx = 0; + u16 scan_section_ms = 0; + u16 total_scan_ms = 0; + + for(idx = 0; idx < param->ch_num; idx++) { + if (param->ch[idx].scan_mode == P2P_LISTEN_MODE) { + param->max_listen_time = param->ch[idx].duration; + total_scan_ms = param->ch[idx].duration; + break; + } + } + + scan_section_ms = param->back_op_ch_dur_ms + param->back_op_off_ch_dur_ms; + if (scan_section_ms) + param->repeat = total_scan_ms / scan_section_ms; +} +#endif + +static void +_phl_cmd_scan_req_init(void *phl, struct phl_cmd_token_req *fgreq, + struct rtw_phl_scan_param *param) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *drv = phl_to_drvpriv(phl_info); + struct rtw_chan_def chdef_list[MAX_WIFI_ROLE_NUMBER] = {0}; + u8 op_num = 0; + u8 idx = 0; + + pq_init(drv, ¶m->chlist); + param->enqueue_time = _os_get_cur_time_ms(); + + _cmd_scan_update_chlist(drv, param); + if (param->back_op_mode != SCAN_BKOP_NONE) { + op_num = rtw_phl_mr_get_opch_list(phl_info, param->wifi_role, + chdef_list, (u8)MAX_WIFI_ROLE_NUMBER); + if(op_num) { + for(idx = 0; idx < op_num; idx++) { + if(chdef_list[idx].chan) { + INIT_LIST_HEAD(¶m->back_op_ch[idx].list); + param->back_op_ch[idx].channel = chdef_list[idx].chan; + param->back_op_ch[idx].bw = chdef_list[idx].bw; + param->back_op_ch[idx].offset = chdef_list[idx].offset; + param->back_op_ch[idx].duration = param->back_op_ch_dur_ms; + param->back_op_ch[idx].scan_mode = BACKOP_MODE; + } + } + } + #ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME + if (op_num && param->back_op_mode == SCAN_BKOP_TIMER) + _cmd_scan_update_chparam(drv, param); + #endif + } + + #ifdef DBG_SCAN_CHAN_DUMP + /* debug information*/ + _cmd_estimated_swch_seq(param, op_num); + #endif + + /* Fill foreground command request */ + fgreq->module_id= PHL_FG_MDL_SCAN; + fgreq->priv = param; + fgreq->role = param->wifi_role; + + fgreq->acquired = _phl_cmd_scan_req_acquired; + fgreq->abort = _phl_cmd_scan_req_abort; + fgreq->msg_hdlr = _phl_cmd_scan_req_ev_hdlr; + fgreq->set_info = _phl_cmd_scan_req_set_info; + fgreq->query_info = _phl_cmd_scan_req_query_info; +} + + +/* For EXTERNAL application to request scan (expose) */ +/* @pscan: scan object + * @pbuf: scan parameter, will be freed by caller after retrun + * @order: queuing order + */ +enum rtw_phl_status rtw_phl_cmd_scan_request(void *phl, + struct rtw_phl_scan_param *param, enum PRECEDE order) +{ + enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE; + u8 band_idx = param->wifi_role->hw_band; + struct phl_cmd_token_req fgreq={0}; + + _phl_cmd_scan_req_init(phl, &fgreq, param); + + /* cmd_dispatcher would copy whole phl_cmd_token_req */ + pstatus = phl_disp_eng_add_token_req(phl, band_idx, &fgreq, ¶m->token); + if((pstatus != RTW_PHL_STATUS_SUCCESS) && + (pstatus != RTW_PHL_STATUS_PENDING)) + goto error; + + pstatus = RTW_PHL_STATUS_SUCCESS; + +error: + return pstatus; +} +enum rtw_phl_status rtw_phl_cmd_scan_cancel(void *phl, + struct rtw_phl_scan_param *param) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + u8 band_idx = param->wifi_role->hw_band; + + return phl_disp_eng_cancel_token_req(phl_info, band_idx, ¶m->token); +} + +int rtw_phl_cmd_scan_inprogress(void *phl, u8 band_idx) +{ + struct phl_module_op_info op_info = {0}; + u32 mdl = 0; + + op_info.op_code = FG_REQ_OP_GET_MDL_ID; + op_info.outbuf = (u8*)&mdl; + op_info.outlen = 4; + + if(phl_disp_eng_query_cur_cmd_info(phl, band_idx, + &op_info)== RTW_PHL_STATUS_SUCCESS ) { + + if(mdl == PHL_FG_MDL_SCAN) + return true; + } + return false; +} + +#endif /* CONFIG_PHL_CMD_SCAN */ diff --git a/phl/phl_cmd_ser.c b/phl/phl_cmd_ser.c new file mode 100644 index 0000000..3a2da88 --- /dev/null +++ b/phl/phl_cmd_ser.c @@ -0,0 +1,918 @@ + +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_CMD_SER_C_ +#include "phl_headers.h" +#include "phl_api.h" + +#define CMD_SER_L0 0x00000001 +#define CMD_SER_L1 0x00000002 +#define CMD_SER_L2 0x00000004 + +enum _CMD_SER_EVENT_SOURCE { + CMD_SER_SRC_UNKNOWN = 0, + CMD_SER_SRC_INT = BIT0, // ser event from interrupt + CMD_SER_SRC_POLL = BIT1, // ser event by polling io + CMD_SER_SRC_INT_NOTIFY = BIT2, // ser event from interrupt and ser state from mac +}; + +enum _CMD_SER_TIMER_STATE { + CMD_SER_NOT_OCCUR = 0, + CMD_SER_M1 = BIT0, //POLL_IO + CMD_SER_M2 = BIT1, //POLL_FW + CMD_SER_M3 = BIT2, + CMD_SER_M4 = BIT3, + CMD_SER_M5 = BIT4, + CMD_SER_M9 = BIT5, +}; + +#define CMD_SER_FW_TIMEOUT 1000 /* ms */ +#define CMD_SER_POLLING_INTERVAL 10 /* ms */ +#define CMD_SER_USB_POLLING_INTERVAL_IDL 1000 /* ms */ +#define CMD_SER_USB_POLLING_INTERVAL_ACT 10 /* ms */ + +#define CMD_SER_POLL_IO_TIMES 200 +#define CMD_SER_USB_POLL_IO_TIMES 300 + +#define CMD_SER_LOG_SIZE 10 + +struct sts_l2 { + _os_list list; + u8 idx; + u8 ser_log; +}; + +struct cmd_ser { + struct phl_info_t *phl_info; + void* dispr; + u8 state; + _os_lock _lock; + + u8 evtsrc; + int poll_cnt; + _os_timer poll_timer; + + /* L2 log : + // If L2 triggered, set ser_log = state-of-cmd_ser + */ + struct phl_queue stslist; + struct sts_l2 stsl2[CMD_SER_LOG_SIZE]; + u8 bserl2; + u8 (*ser_l2_hdlr)(void *drv); +}; + +static void _ser_int_ntfy_ctrl(struct phl_info_t *phl_info, + enum rtw_phl_config_int int_type) +{ + if (RTW_PHL_CLR_HCI_INT == int_type) + rtw_hal_clear_interrupt(phl_info->hal); + else + rtw_hal_config_interrupt(phl_info->hal, int_type); +} + +static enum rtw_phl_status +_ser_event_notify(void *phl, u8 *p_ntfy) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET; + struct phl_msg msg = {0}; + u32 err = 0; + + notify = rtw_hal_ser_get_error_status(phl_info->hal, &err); + + if (p_ntfy != NULL) + *p_ntfy = notify; + + phl_info->phl_com->phl_stats.ser_event[notify]++; + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "_ser_event_notify, error 0x%x, notify 0x%x\n", err, notify); + + if (notify == RTW_PHL_SER_L0_RESET) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, hit L0 Reset\n"); + return RTW_PHL_STATUS_SUCCESS; + } + + if (notify == RTW_PHL_SER_LOG_ONLY) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, RTW_PHL_SER_LOG_ONLY\n"); + return RTW_PHL_STATUS_SUCCESS; + } + + if (notify == RTW_PHL_SER_DUMP_FW_LOG) { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, RTW_PHL_SER_DUMP_FW_LOG\n"); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DUMP_PLE_BUFFER); + phl_msg_hub_send(phl_info, NULL, &msg); + + return RTW_PHL_STATUS_SUCCESS; + } + + return phl_ser_send_msg(phl, notify); +} + +void _ser_dump_stsl2(struct cmd_ser *cser) +{ + u8 idx =0; + + for (idx = 0; idx < CMD_SER_LOG_SIZE; idx++) { + if (cser->stsl2[idx].ser_log || cser->stsl2[idx].idx >= CMD_SER_LOG_SIZE) { + PHL_ERR("%s :: [%d] %d - ser_log = 0x%X \n", __func__, + idx, cser->stsl2[idx].idx, cser->stsl2[idx].ser_log); + } + } +} + +void _ser_reset_status(struct cmd_ser *cser) +{ + void *drv = phl_to_drvpriv(cser->phl_info); + + _os_spinlock(drv, &cser->_lock, _bh, NULL); + cser->state = CMD_SER_NOT_OCCUR; + _os_spinunlock(drv, &cser->_lock, _bh, NULL); + + if (CMD_SER_SRC_POLL == cser->evtsrc) { + cser->poll_cnt = 0; + _os_set_timer(drv, + &cser->poll_timer, + CMD_SER_USB_POLLING_INTERVAL_IDL); + } else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) { + _ser_int_ntfy_ctrl(cser->phl_info, RTW_PHL_EN_HCI_INT); + } +} + +void _ser_set_status(struct cmd_ser *cser, u8 serstatus) +{ + void *drv = phl_to_drvpriv(cser->phl_info); + + _os_spinlock(drv, &cser->_lock, _bh, NULL); + cser->state |= serstatus; + _os_spinunlock(drv, &cser->_lock, _bh, NULL); +} + +void _ser_clear_status(struct cmd_ser *cser, u8 serstatus) +{ + void *drv = phl_to_drvpriv(cser->phl_info); + + _os_spinlock(drv, &cser->_lock, _bh, NULL); + cser->state &= ~(serstatus); + _os_spinunlock(drv, &cser->_lock, _bh, NULL); +} + +static void _ser_l1_notify(struct cmd_ser *cser) +{ + struct phl_msg nextmsg = {0}; + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER); + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_L1); + phl_msg_hub_send(cser->phl_info, NULL, &nextmsg); +} + +static void _ser_l2_notify(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + struct sts_l2 *stsl2 = NULL; + struct phl_msg nextmsg = {0}; + _os_list* obj = NULL; + + rtw_hal_ser_reset_wdt_intr(phl_info->hal); + + if (pq_pop(drv, &cser->stslist, &obj, _first, _ps)) { + stsl2 = (struct sts_l2*)obj; + + /* Rotate stslist : 0~ (CMD_SER_LOG_SIZE-1) are unused index */ + stsl2->idx+= CMD_SER_LOG_SIZE; + stsl2->ser_log = cser->state; + pq_push(drv, &cser->stslist, &stsl2->list, _tail, _ps); + } + _ser_dump_stsl2(cser); + + /* L2 can't be rescued, bserl2 wouldn't reset. */ + /* comment out: wait for new ser flow to handle L2 */ + cser->bserl2 = true; + + if (cser->ser_l2_hdlr) + cser->ser_l2_hdlr(phl_to_drvpriv(phl_info)); + + phl_disp_eng_clr_pending_msg(cser->phl_info, HW_BAND_0); + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER); + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_L2); + phl_msg_hub_send(cser->phl_info, NULL, &nextmsg); +} + +static void _ser_m2_notify(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_SER_HANDSHAKE_MODE); + + _ser_clear_status(cser, CMD_SER_M1); + _ser_set_status(cser, CMD_SER_M2); + + /* send M2 event to fw */ + status = rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L1_DISABLE_EN); + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "_ser_m2_notify:: RTW_PHL_SER_L1_DISABLE_EN, status 0x%x\n", status); +} + +static void _ser_m3_m5_waiting(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + int poll_cnt = 0, intvl = CMD_SER_FW_TIMEOUT; + + if (cser->evtsrc == CMD_SER_SRC_POLL) { + /* CMD_SER_POLLING_INTERVAL = CMD_SER_FW_TIMEOUT/ CMD_SER_USB_POLLING_INTERVAL_ACT */ + poll_cnt = CMD_SER_POLLING_INTERVAL; + intvl = CMD_SER_USB_POLLING_INTERVAL_ACT; + } + + cser->poll_cnt = poll_cnt; + /* wait M3 or M5 */ + _os_set_timer(drv, &cser->poll_timer, intvl); +} + +static void _ser_m4_notify(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_SER_HANDSHAKE_MODE); + + _ser_clear_status(cser, CMD_SER_M3); + _ser_set_status(cser, CMD_SER_M4); + + /* send M4 event */ + status = rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L1_RCVY_EN); + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "_ser_m4_notify:: RTW_PHL_SER_L1_RCVY_EN, status 0x%x\n", status); +} + +static void _ser_poll_timer_cb(void *priv) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER); + + if (TEST_STATUS_FLAG(cser->state, CMD_SER_M1)) { + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_IO_TIMER_EXPIRE); + } else if (TEST_STATUS_FLAG(cser->state, CMD_SER_M2)) { + if (cser->poll_cnt > 0) /* polling mode */ + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK); + else + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_FW_TIMER_EXPIRE); + } else if (TEST_STATUS_FLAG(cser->state, CMD_SER_M4)) { + if (cser->poll_cnt > 0) /* polling mode */ + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK); + else + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_FW_TIMER_EXPIRE); + } else { + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK); + } + + nextmsg.band_idx = HW_BAND_0; + + if (MSG_EVT_ID_FIELD(nextmsg.msg_id)) { + PHL_DBG("%s :: nextmsg->msg_id= 0x%X\n", __func__, MSG_EVT_ID_FIELD(nextmsg.msg_id)); + pstatus = phl_disp_eng_send_msg(cser->phl_info, &nextmsg, &attr, NULL); + if (pstatus != RTW_PHL_STATUS_SUCCESS) + PHL_ERR("%s :: [SER_TIMER_CB] dispr_send_msg failed\n", __func__); + } +} + +static void _ser_m1_pause_trx(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.id = PHL_MDL_SER; + + ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): pause sw tx failure\n", __func__); + goto err; + } + + ctl.cmd = PHL_DATA_CTL_HW_TRX_PAUSE; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): pause hw trx failure\n", __func__); + goto err; + } + + ctl.cmd = PHL_DATA_CTL_SW_RX_PAUSE; + sts = phl_data_ctrler(phl_info, &ctl, NULL); +#ifdef RTW_WKARD_SER_L1_EXPIRE + if (RTW_PHL_STATUS_SUCCESS != sts && RTW_PHL_STATUS_CMD_TIMEOUT != sts) { + PHL_WARN("%s(): pause sw rx failure\n", __func__); + goto err; + } +#else + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): pause sw rx failure\n", __func__); + goto err; + } +#endif + + ctl.cmd = PHL_DATA_CTL_SW_TX_RESET; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): reset sw tx failure\n", __func__); + goto err; + } + + ctl.cmd = PHL_DATA_CTL_SW_RX_RESET; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): reset sw rx failure\n", __func__); + goto err; + } + + _ser_m2_notify(cser); + _ser_m3_m5_waiting(cser); + + return; +err: + _ser_l2_notify(cser); + _ser_reset_status(cser); + + return; +} + +static void _ser_m3_reset_hw_trx(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + ctl.id = PHL_MDL_SER; + + ctl.cmd = PHL_DATA_CTL_HW_TRX_RST_RESUME; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): resume hw trx failure\n", __func__); + goto err; + } + + ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) { + PHL_WARN("%s(): resume sw rx failure\n", __func__); + goto err; + } + + _ser_m4_notify(cser); + _ser_m3_m5_waiting(cser); + + return; +err: + _ser_l2_notify(cser); + _ser_reset_status(cser); + + return; +} + +enum phl_mdl_ret_code +_ser_fail_ev_hdlr(void *dispr, void *priv, struct phl_msg *msg) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + + PHL_INFO("%s :: [MSG_FAIL] MDL =%d , EVT_ID=%d\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + + if (cser->evtsrc != CMD_SER_SRC_POLL) + return MDL_RET_SUCCESS; + + _os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_IDL); + + return MDL_RET_SUCCESS; +} + +enum phl_mdl_ret_code +_ser_hdl_external_evt(void *dispr, void *priv, struct phl_msg *msg) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + + /* + 1. SER inprogress: pending msg from others module + 2. SER recovery fail: clr pending event from MDL_SER & msg return failed from others module + 3. SER recovery done: clr pending event & msg return ignor from others module + 4. SER NOT OCCUR: MDL_RET_IGNORE + */ + if (cser->bserl2) { + PHL_ERR("%s: [2] L2 Occured!! From others MDL =%d , EVT_ID=%d\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + return MDL_RET_FAIL; + } else if (cser->state) { /* non-CMD_SER_NOT_OCCUR */ + PHL_WARN("%s: [1] Within SER!! From others MDL =%d , EVT_ID=%d\n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + return MDL_RET_PENDING; + } + + return MDL_RET_IGNORE; +} + +static void _ser_msg_hdl_polling_chk(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + + if (CMD_SER_SRC_POLL != cser->evtsrc) + return; + + if (true == rtw_hal_recognize_interrupt(phl_info->hal)) { + rtw_phl_interrupt_handler(phl_info); + } else { + if (cser->poll_cnt > 0) { + /* wait for m3/m5, polling 10*10 */ + cser->poll_cnt--; + _os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_ACT); /* 10ms */ + } else { + /* no ser occur, set next polling timer */ + _os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_IDL); /* 1000ms */ + } + } +} + +static enum rtw_phl_status +_ser_msg_hdl_evt_chk(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + + if (CMD_SER_SRC_INT == cser->evtsrc) { + psts = _ser_event_notify(phl_info, NULL); + } else if (CMD_SER_SRC_POLL == cser->evtsrc) { + psts = _ser_event_notify(phl_info, NULL); + } else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) { + u8 notify = RTW_PHL_SER_L0_RESET; + + /* disable interrupt notification and read ser value */ + if (true == rtw_hal_recognize_halt_c2h_interrupt(phl_info->hal)) { + psts = _ser_event_notify(phl_info, ¬ify); + + if ((notify == RTW_PHL_SER_L0_RESET) || (notify == RTW_PHL_SER_L2_RESET)) + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_EN_HCI_INT); + } else { + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_EN_HCI_INT); + } + } + + return psts; +} + +static void _ser_msg_hdl_m1(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + + if (CMD_SER_SRC_POLL == cser->evtsrc) + _os_cancel_timer(drv, &cser->poll_timer); + else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_DIS_HCI_INT); + + _ser_set_status(cser, CMD_SER_M1); + _ser_l1_notify(cser); + + _ser_m1_pause_trx(cser); +} + +static void _ser_msg_hdl_fw_expire(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + + if (CMD_SER_SRC_POLL == cser->evtsrc) { + _ser_set_status(cser, CMD_SER_M9); + + _os_set_timer(drv, + &cser->poll_timer, + CMD_SER_USB_POLLING_INTERVAL_IDL); + } + + cser->bserl2 = true; +} + +static void _ser_msg_hdl_m3(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + + if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) + _ser_int_ntfy_ctrl(phl_info, RTW_PHL_CLR_HCI_INT); + + _os_cancel_timer(drv, &cser->poll_timer); + _ser_clear_status(cser, CMD_SER_M2); + _ser_set_status(cser, CMD_SER_M3); + + _ser_m3_reset_hw_trx(cser); +} + +static void _ser_msg_hdl_m5(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + _os_cancel_timer(drv, &cser->poll_timer); + _ser_clear_status(cser, CMD_SER_M4); + _ser_set_status(cser, CMD_SER_M5); + + ctl.id = PHL_MDL_SER; + ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) + PHL_WARN("%s(): resume sw tx failure\n", __func__); + + _ser_reset_status(cser); + + phl_disp_eng_clr_pending_msg(cser->phl_info, HW_BAND_0); +} + +static void _ser_msg_hdl_m9(struct cmd_ser *cser) +{ + struct phl_info_t *phl_info = cser->phl_info; + void *drv = phl_to_drvpriv(phl_info); + enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE; + struct phl_data_ctl_t ctl = {0}; + + _os_cancel_timer(drv, &cser->poll_timer); + _ser_set_status(cser, CMD_SER_M9); + + if (cser->state > CMD_SER_NOT_OCCUR) { + ctl.id = PHL_MDL_SER; + ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) + PHL_WARN("%s(): resume sw tx failure\n", __func__); + + ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME; + sts = phl_data_ctrler(phl_info, &ctl, NULL); + if (RTW_PHL_STATUS_SUCCESS != sts) + PHL_WARN("%s(): resume sw rx failure\n", __func__); + } + + _ser_l2_notify(cser); + _ser_reset_status(cser); +} + +enum phl_mdl_ret_code +_ser_hdl_internal_evt(void *dispr, void *priv, struct phl_msg *msg) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + enum phl_mdl_ret_code ret = MDL_RET_SUCCESS; + + switch (MSG_EVT_ID_FIELD(msg->msg_id)) { + case MSG_EVT_SER_POLLING_CHK: + PHL_DBG("MSG_EVT_SER_POLLING_CHK\n"); + _ser_msg_hdl_polling_chk(cser); + break; + + case MSG_EVT_SER_EVENT_CHK: + PHL_INFO("MSG_EVT_SER_EVENT_CHK\n"); + _ser_msg_hdl_evt_chk(cser); + break; + + case MSG_EVT_SER_M1_PAUSE_TRX: + PHL_WARN("MSG_EVT_SER_M1_PAUSE_TRX\n"); + _ser_msg_hdl_m1(cser); + break; + + case MSG_EVT_SER_IO_TIMER_EXPIRE: + PHL_INFO("MSG_EVT_SER_IO_TIMER_EXPIRE\n"); + break; + + case MSG_EVT_SER_FW_TIMER_EXPIRE: + PHL_WARN("MSG_EVT_SER_FW_TIMER_EXPIRE (state %d), do nothing and wait FW WDT\n", + cser->state); + _ser_msg_hdl_fw_expire(cser); + break; + + case MSG_EVT_SER_M3_DO_RECOV: + PHL_INFO("MSG_EVT_SER_M3_DO_RECOV\n"); + _ser_msg_hdl_m3(cser); + break; + + case MSG_EVT_SER_M5_READY: + PHL_INFO("MSG_EVT_SER_M5_READY\n"); + _ser_msg_hdl_m5(cser); + break; + + case MSG_EVT_SER_M9_L2_RESET: + PHL_WARN("MSG_EVT_SER_M9_L2_RESET\n"); + _ser_msg_hdl_m9(cser); + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_init(void *phl, void *dispr, void **priv) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *drv = phl_to_drvpriv(phl_info); + struct cmd_ser *cser = NULL; + u8 idx = 0; + + FUNCIN(); + if (priv == NULL) + return MDL_RET_FAIL; + + (*priv) = NULL; + cser = (struct cmd_ser *)_os_mem_alloc(drv, sizeof(struct cmd_ser)); + if (cser == NULL) { + PHL_ERR(" %s, alloc fail\n",__FUNCTION__); + return MDL_RET_FAIL; + } + + _os_mem_set(drv, cser, 0, sizeof(struct cmd_ser)); + _os_spinlock_init(drv, &cser->_lock); + _os_init_timer(drv, + &cser->poll_timer, + _ser_poll_timer_cb, + cser, + "cmd_ser_poll_timer"); + + INIT_LIST_HEAD(&cser->stslist.queue); + for (idx =0; idx < CMD_SER_LOG_SIZE; idx++) { + INIT_LIST_HEAD(&cser->stsl2[idx].list); + cser->stsl2[idx].idx = idx; + pq_push(drv, &cser->stslist, &cser->stsl2[idx].list, _tail, _ps); + } + + cser->phl_info = phl_info; + cser->dispr = dispr; + (*priv) = (void*)cser; + + if (phl_info->phl_com->hci_type == RTW_HCI_PCIE) + cser->evtsrc = CMD_SER_SRC_INT; + else if (phl_info->phl_com->hci_type == RTW_HCI_USB) + cser->evtsrc = CMD_SER_SRC_POLL; + else if (phl_info->phl_com->hci_type == RTW_HCI_SDIO) + cser->evtsrc = CMD_SER_SRC_INT_NOTIFY; + + PHL_INFO("%s:: cser->evtsrc = %d\n", __func__, cser->evtsrc); + FUNCOUT(); + + return MDL_RET_SUCCESS; +} + +static void _phl_ser_mdl_deinit(void *dispr, void *priv) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + void *drv = phl_to_drvpriv(cser->phl_info); + + FUNCIN(); + + _os_cancel_timer(drv, &cser->poll_timer); + _os_release_timer(drv, &cser->poll_timer); + _os_spinlock_free(drv, &cser->_lock); + _os_mem_free(drv, cser, sizeof(struct cmd_ser)); + PHL_INFO(" %s\n", __FUNCTION__); +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_start(void *dispr, void *priv) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + struct phl_info_t *phl_info = cser->phl_info; + + if (CMD_SER_SRC_POLL == cser->evtsrc) { + /* Disable L0 Reset Notify from FW to driver */ + rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L0_CFG_DIS_NOTIFY); + } + + _ser_reset_status(cser); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_stop(void *dispr, void *priv) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + void *drv = phl_to_drvpriv(cser->phl_info); + + _os_cancel_timer(drv, &cser->poll_timer); + + return MDL_RET_SUCCESS; +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_msg_hdlr(void *dispr, + void *priv, + struct phl_msg *msg) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + if (IS_MSG_FAIL(msg->msg_id)) { + PHL_INFO("%s :: MSG(%d)_FAIL - EVT_ID=%d \n", __func__, + MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); + + return _ser_fail_ev_hdlr(dispr, priv, msg); + } + + switch (MSG_MDL_ID_FIELD(msg->msg_id)) { + case PHL_MDL_SER: + if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) + ret = _ser_hdl_internal_evt(dispr, priv, msg); + break; + + default: + ret = _ser_hdl_external_evt(dispr, priv, msg); + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_set_info(void *dispr, + void *priv, + struct phl_module_op_info *info) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + + switch (info->op_code) { + case BK_MODL_OP_INPUT_CMD: + if (info->inbuf) { + cser->ser_l2_hdlr=(u8 (*)(void *))info->inbuf; + } + ret = MDL_RET_SUCCESS; + break; + } + + return ret; +} + +static enum phl_mdl_ret_code +_phl_ser_mdl_query_info(void *dispr, + void *priv, + struct phl_module_op_info *info) +{ + struct cmd_ser *cser = (struct cmd_ser *)priv; + void *drv = phl_to_drvpriv(cser->phl_info); + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + + switch (info->op_code) { + case BK_MODL_OP_STATE: + _os_mem_cpy(drv, (void*)info->inbuf, &cser->state, 1); + ret = MDL_RET_SUCCESS; + break; + } + return ret; +} + +static struct phl_bk_module_ops ser_ops= { + .init = _phl_ser_mdl_init, + .deinit = _phl_ser_mdl_deinit, + .start = _phl_ser_mdl_start, + .stop = _phl_ser_mdl_stop, + .msg_hdlr = _phl_ser_mdl_msg_hdlr, + .set_info = _phl_ser_mdl_set_info, + .query_info = _phl_ser_mdl_query_info, +}; + +enum rtw_phl_status +phl_register_ser_module(struct phl_info_t *phl_info) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + + phl_status = phl_disp_eng_register_module(phl_info, + HW_BAND_0, + PHL_MDL_SER, + &ser_ops); + if (RTW_PHL_STATUS_SUCCESS != phl_status) { + PHL_ERR("%s register SER module in cmd disp failed! \n", __func__); + } + + return phl_status; +} + +#ifdef CONFIG_PHL_CMD_SER +u8 phl_ser_inprogress(void *phl) +{ + struct phl_module_op_info op_info = {0}; + u8 state = 0; + + op_info.op_code = BK_MODL_OP_STATE; + op_info.inbuf = (u8*)&state; + op_info.inlen = 1; + + if (rtw_phl_query_bk_module_info(phl, + HW_BAND_0, + PHL_MDL_SER, + &op_info) == RTW_PHL_STATUS_SUCCESS) { + if (state) /* non-CMD_SER_NOT_OCCUR */ + return true; + } + return false; +} + +enum rtw_phl_status +phl_ser_send_msg(void *phl, enum RTW_PHL_SER_NOTIFY_EVENT notify) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + u16 event = 0; + + switch (notify) { + case RTW_PHL_SER_PAUSE_TRX: /* M1 */ + event = MSG_EVT_SER_M1_PAUSE_TRX; + break; + case RTW_PHL_SER_DO_RECOVERY: /* M3 */ + event = MSG_EVT_SER_M3_DO_RECOV; + break; + case RTW_PHL_SER_READY: /* M5 */ + event = MSG_EVT_SER_M5_READY; + break; + case RTW_PHL_SER_L2_RESET: /* M9 */ + event = MSG_EVT_SER_M9_L2_RESET; + break; + case RTW_PHL_SER_EVENT_CHK: + event = MSG_EVT_SER_EVENT_CHK; + break; + case RTW_PHL_SER_L0_RESET: + default: + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "phl_ser_send_msg(): unsupported case %d\n", + notify); + return RTW_PHL_STATUS_FAILURE; + } + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "phl_ser_send_msg(): event %d\n", event); + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER); + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, event); + nextmsg.band_idx = HW_BAND_0; + + phl_status = rtw_phl_send_msg_to_dispr(phl, + &nextmsg, + &attr, + NULL); + if (phl_status != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("[CMD_SER] send_msg_to_dispr fail! (%d)\n", event); + } + + return phl_status; +} +#endif + +#ifndef CONFIG_FSM +/* The same as phl_fw_watchdog_timeout_notify of fsm-ser */ +enum rtw_phl_status +phl_fw_watchdog_timeout_notify(void *phl) +{ + enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "phl_fw_watchdog_timeout_notify triggle L2 Reset !!!\n"); + + return phl_ser_send_msg(phl, notify); +} + +enum rtw_phl_status rtw_phl_ser_l2_notify(struct rtw_phl_com_t *phl_com) +{ + enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET; + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_phl_ser_l2_notify triggle L2 Reset !!!\n"); + + return phl_ser_send_msg(phl_com->phl_priv, notify); +} + +/* The same as rtw_phl_ser_dump_ple_buffer of fsm-ser */ +enum rtw_phl_status +rtw_phl_ser_dump_ple_buffer(void *phl) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "rtw_phl_ser_dump_ple_buffer\n"); + + rtw_hal_dump_fw_rsvd_ple(phl_info->hal); + + return RTW_PHL_STATUS_SUCCESS; +} +#endif /*#ifndef CONFIG_FSM*/ + diff --git a/phl/phl_cmd_ser.h b/phl/phl_cmd_ser.h new file mode 100644 index 0000000..1dda4d8 --- /dev/null +++ b/phl/phl_cmd_ser.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PHL_CMD_SER_H__ +#define __PHL_CMD_SER_H__ + +#ifndef CONFIG_FSM +enum rtw_phl_status phl_fw_watchdog_timeout_notify(void *phl); +enum rtw_phl_status rtw_phl_ser_dump_ple_buffer(void *phl); +#endif + +enum rtw_phl_status phl_ser_send_msg(void *phl, enum RTW_PHL_SER_NOTIFY_EVENT notify); + +#ifdef CONFIG_PHL_CMD_SER +enum rtw_phl_status +phl_register_ser_module(struct phl_info_t *phl_info); +#endif + +#endif /* __PHL_CMD_SER_H__ */ diff --git a/phl/phl_config.h b/phl/phl_config.h new file mode 100644 index 0000000..97e54fe --- /dev/null +++ b/phl/phl_config.h @@ -0,0 +1,431 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CONFIG_H_ +#define _PHL_CONFIG_H_ + +/* Define correspoding PHL Feature based on information from the Core */ +#ifdef PHL_PLATFORM_AP +#define PHL_FEATURE_AP +#elif defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS) +#define PHL_FEATURE_NIC +#else +#define PHL_FEATURE_NONE +#endif + +/******************* PLATFORM Section **************************/ +#ifdef PHL_FEATURE_NONE/* enable compile flag for phl only compilation check */ + #define CONFIG_DFS 1 + #define CONFIG_USB_TX_AGGREGATION + #define CONFIG_USB_RX_AGGREGATION + #define CONFIG_USB_TX_PADDING_CHK + #define CONFIG_LOAD_PHY_PARA_FROM_FILE + + #define CONFIG_WOW + #define CONFIG_WPA3_SUITEB_SUPPORT + #define CONFIG_SYNC_INTERRUPT + + #define CONFIG_MR_SUPPORT + #ifdef CONFIG_MR_SUPPORT + #define CONFIG_SCC_SUPPORT + #define CONFIG_MCC_SUPPORT + #ifdef CONFIG_MCC_SUPPORT + #define MCC_ROLE_NUM 2 + #define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA + #define RTW_WKARD_HALRF_MCC + #define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE + #endif /*CONFIG_MCC_SUPPORT*/ + + #define CONFIG_DBCC_SUPPORT + + #define DBG_PHL_CHAN + #define DBG_PHL_MR + #define PHL_MR_PROC_CMD + #define DBG_CHCTX_RMAP + #endif /*CONFIG_MR_SUPPORT*/ + + #define DBG_PHL_MAC_REG_RW + + #define CONFIG_RTW_ACS + #define CONFIG_RX_PSTS_PER_PKT + + #define CONFIG_PHL_TXSC + #define RTW_PHL_BCN + #define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL + #define CONFIG_PHL_TWT + #define CONFIG_CMD_DISP + #ifdef CONFIG_CMD_DISP + #define CONFIG_PHL_ECSA + /*#define CONFIG_CMD_DISP_SOLO_MODE*/ + #define CONFIG_PHL_CMD_SCAN + #define CONFIG_PHL_CMD_SER + #define CONFIG_PHL_CMD_BTC + #endif + #ifdef CONFIG_PCI_HCI + #define PCIE_TRX_MIT_EN + #endif + #define CONFIG_PHL_P2PPS + #define CONFIG_6GHZ + #define RTW_WKARD_BFEE_SET_AID + #define CONFIG_PHL_THERMAL_PROTECT + #define CONFIG_PHL_TX_DBG +#endif /* PHL_FEATURE_NONE */ + +#ifdef PHL_PLATFORM_WINDOWS + #ifndef CONFIG_FSM + #define CONFIG_FSM + #endif + #ifndef CONFIG_CMD_DISP + #define CONFIG_CMD_DISP + #endif +#endif + +#ifdef PHL_PLATFORM_LINUX + /* comment out cfg temporarily */ + /* + #define CONFIG_FSM + + #ifndef CONFIG_FSM + #define CONFIG_CMD_DISP + #endif + */ +#endif + +/******************* Feature flags **************************/ + +#ifdef CONFIG_PHL_TEST_SUITE +#define CONFIG_PHL_TEST_MP +#define CONFIG_PHL_TEST_VERIFY +#endif + +#ifdef CONFIG_CORE_SYNC_INTERRUPT +#define CONFIG_SYNC_INTERRUPT +#endif + +#ifdef CONFIG_WOW +#define CONFIG_WOWLAN +/* #define RTW_WKARD_WOW_SKIP_AOAC_RPT */ +/* #define RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG */ +#define RTW_WKARD_WOW_L2_PWR +#define DBG_RST_BDRAM_TIME +#endif + +#define DBG_PHY_ON_TIME + +/*CONFIG_IFACE_NUMBER*/ +#ifdef CONFIG_IFACE_NUMBER +#define MAX_WIFI_ROLE_NUMBER CONFIG_IFACE_NUMBER +#else +#define MAX_WIFI_ROLE_NUMBER 5 +#endif + +#ifdef CONFIG_CONCURRENT_MODE +#define CONFIG_MR_SUPPORT +#endif + +#ifdef CONFIG_REUSED_FWDL_BUF + #define CONFIG_PHL_REUSED_FWDL_BUF +#endif + +#ifdef CONFIG_MR_SUPPORT +#define CONFIG_SCC_SUPPORT +#define CONFIG_MCC_SUPPORT +#ifdef CONFIG_MCC_SUPPORT +#define MCC_ROLE_NUM 2 +#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA +#define RTW_WKARD_HALRF_MCC +#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE +#endif /*CONFIG_MCC_SUPPORT*/ +/*#define CONFIG_DBCC_SUPPORT*/ + +#define DBG_PHL_CHAN +#define DBG_PHL_MR +#define PHL_MR_PROC_CMD +#define DBG_CHCTX_RMAP +#endif + +#define DBG_PHL_STAINFO +#define PHL_MAX_STA_NUM 128 + +/**** CONFIG_CMD_DISP ***/ +#ifdef DISABLE_CMD_DISPR +#undef CONFIG_CMD_DISP +#endif + +#ifdef CONFIG_CMD_DISP +/* enable SOLO mode define to create seperated background thread per dispatcher, + * otherwise, all dispatcher would share single background thread, which is in share mode. +*/ +/*#define CONFIG_CMD_DISP_SOLO_MODE*/ + +/* Enable Self-Defined Sequence feature for sender to rearrange dispatch order, + * Since this is not a mandatory feature and would have addiional memory cost (arround 2200 Bytes) + * Disable by default. +*/ +/*#define CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ*/ + +#ifndef CONFIG_FSM + #define CONFIG_SND_CMD +#endif + +#define CONFIG_PHL_CMD_SCAN + +#ifdef CONFIG_CMD_SER +#define CONFIG_PHL_CMD_SER +#endif + +#define CONFIG_PHL_CMD_BTC +#endif /**** CONFIG_CMD_DISP ***/ + +#define CONFIG_GEN_GIT_INFO 1 +/*#define CONFIG_NEW_HALMAC_INTERFACE*/ + +#define CONFIG_BTCOEX + +#ifdef CONFIG_USB_TX_PADDING_CHK +#define CONFIG_PHL_USB_TX_PADDING_CHK +#endif + +#ifdef CONFIG_USB_TX_AGGREGATION +#define CONFIG_PHL_USB_TX_AGGREGATION +#endif + +#ifdef CONFIG_USB_RX_AGGREGATION +#define CONFIG_PHL_USB_RX_AGGREGATION +#endif + +#if CONFIG_DFS +#define CONFIG_PHL_DFS +#endif + +#ifdef CONFIG_PHL_DFS +/*#define CONFIG_PHL_DFS_REGD_FCC*/ +/*#define CONFIG_PHL_DFS_REGD_JAP*/ +#define CONFIG_PHL_DFS_REGD_ETSI +#endif + +#ifdef CONFIG_WPP +#define CONFIG_PHL_WPP +#endif + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX +#define CONFIG_PHL_CSUM_OFFLOAD_RX +#endif + +#ifdef CONFIG_RX_PSTS_PER_PKT +#define CONFIG_PHL_RX_PSTS_PER_PKT +#define RTW_WKARD_DISABLE_PSTS_PER_PKT_DATA +#endif + +#ifdef CONFIG_SDIO_RX_NETBUF_ALLOC_IN_PHL +#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL +#endif + +#ifdef CONFIG_SDIO_READ_RXFF_IN_INT +#define CONFIG_PHL_SDIO_READ_RXFF_IN_INT +#endif + +#ifdef CONFIG_ECSA +#define CONFIG_PHL_ECSA +#ifdef CONFIG_ECSA_EXTEND_OPTION +#define CONFIG_PHL_ECSA_EXTEND_OPTION +#endif +#endif + +#ifdef CONFIG_TWT +#define CONFIG_PHL_TWT +#endif + +#ifdef CONFIG_RA_TXSTS_DBG +#define CONFIG_PHL_RA_TXSTS_DBG +#endif + +#ifdef CONFIG_USB_RELEASE_RPT +#define CONFIG_PHL_USB_RELEASE_RPT_ENABLE +#endif + +#ifdef CONFIG_P2PPS +#define CONFIG_PHL_P2PPS +#endif + +#ifdef CONFIG_TX_DBG +#define CONFIG_PHL_TX_DBG +#endif +#ifdef CONFIG_PCI_HCI +#ifdef CONFIG_PCIE_TRX_MIT +#define PCIE_TRX_MIT_EN +#endif +#endif +#ifdef CONFIG_THERMAL_PROTECT +#define CONFIG_PHL_THERMAL_PROTECT +#endif + +#ifdef CONFIG_RX_BATCH_IND +#define PHL_RX_BATCH_IND +#endif + +#ifdef CONFIG_TDLS +#define CONFIG_PHL_TDLS +#endif + +#ifdef CONFIG_SDIO_HCI +/* For SDIO TX TP TST - START */ +#ifdef CONFIG_SDIO_TX_AGG_NUM_MAX +#define PHL_SDIO_TX_AGG_MAX CONFIG_SDIO_TX_AGG_NUM_MAX +#endif /* CONFIG_SDIO_TX_AGG_NUM_MAX */ +#define SDIO_TX_THREAD /* Use dedicate thread for SDIO TX */ +/* For SDIO TX TP TST - ENDT */ +#endif /* CONFIG_SDIO_HCI */ + +#ifdef CONFIG_MAC_REG_RW_CHK +#define DBG_PHL_MAC_REG_RW +#endif + +/******************* WKARD flags **************************/ +#define RTW_WKARD_P2PPS_REFINE +#define RTW_WKARD_P2PPS_SINGLE_NOA +#define RTW_WKARD_P2PPS_NOA_MCC + +#ifdef PHL_PLATFORM_LINUX +#define RTW_WKARD_RF_CR_DUMP +#define RTW_WKARD_LINUX_CMD_WKARD +#endif + +#ifdef PHL_PLATFORM_WINDOWS +/* Workaround for doing hal reset in changing MP mode will lost the mac entry */ +#define RTW_WKARD_MP_MODE_CHANGE +#define RTW_WKARD_WIN_TRX_BALANCE +#define RTW_WKARD_DYNAMIC_LTR +#endif + +#define RTW_WKARD_PHY_CAP + +#define RTW_WKARD_LAMODE + +#define RTW_WKARD_TXSC + +#define RTW_WKARD_BB_C2H + +/* + * One workaround of EFUSE operation + * 1. Dump EFUSE with FW fail + */ +#define RTW_WKARD_EFUSE_OPERATION + +#define RTW_WKARD_STA_BCN_INTERVAL + +#define RTW_WKARD_SER_L1_EXPIRE + +#ifdef CONFIG_USB_HCI +#define RTW_WKARD_SER_USB_POLLING_EVENT +#endif + +/* #define RTW_WKARD_SER_USB_DISABLE_L1_RCVY_FLOW */ + +#define RTW_WKARD_BTC_RFETYPE + +#define RTW_WKARD_TXBD_UPD_LMT /* 8852AE/8852BE txbd index update limitation */ + +#ifdef CONFIG_WPA3_SUITEB_SUPPORT +#define RTW_WKARD_HW_MGNT_GCMP_256_DISABLE +#endif + +/* Workaround for cmac table config + * - Default is disabled until halbb is ready + * - This workaround will be removed once fw handles this cfg + */ +/*#define RTW_WKARD_DEF_CMACTBL_CFG*/ + +/* Workaround for efuse read hidden report + * - Default is disabled until halmac is ready + */ + +#define RTW_WKARD_PRELOAD_TRX_RESET + +/* Workaround for cmac table config + * - This workaround will be removed once fw handles this cfg + */ +#define RTW_WKARD_DEF_CMACTBL_CFG + +#define RTW_WKARD_USB_TXAGG_BULK_END_WD +#ifdef CONFIG_HOMOLOGATION +#define CONFIG_PHL_HOMOLOGATION +#endif + +#ifdef RTW_WKARD_TX_DISABLE_BFEE +#define RTW_WKARD_DYNAMIC_BFEE_CAP +#endif + +#ifdef RTW_WKARD_NTFY_MEDIA_STS +#define RTW_WKARD_PHL_NTFY_MEDIA_STS +#endif + +#ifdef RTW_WKARD_PHY_INFO_NTFY +#define CONFIG_PHY_INFO_NTFY +#endif + +#ifdef PHL_PLATFORM_WINDOWS +#define CONFIG_WOW_WITH_SER +#endif + +#ifdef PHL_PLATFORM_WINDOWS +#define CONFIG_DBG_H2C_TX +#endif + +/* + * Workaround for MRC bk module call phl_mr_offch_hdl with scan_issue_null_data + * ops, this should be replaced with phl issue null data function. + */ +#define RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + +/* + * Workaround for phl_mr_offch_hdl sleep after issue null data, + * - This workaround will be removed once tx report is ready + */ +#ifndef RTW_WKARD_TX_NULL_WD_RP +#define RTW_WKARD_ISSUE_NULL_SLEEP_PROTECTION +#endif +#ifdef RTW_WKARD_LPS_IQK_TWICE +#define RTW_WKARD_PHL_LPS_IQK_TWICE +#endif + +#ifdef RTW_WKARD_FSM_SCAN_PASSIVE_TO_ACTIVE +#define RTW_WKARD_PHL_FSM_SCAN_PASSIVE_TO_ACTIVE +#endif + +#define RTW_WKARD_BUSCAP_IN_HALSPEC + +#define RTW_WKARD_IBSS_SNIFFER_MODE + + +#define RTW_WKARD_SINGLE_PATH_RSSI + +/* #define CONFIG_6GHZ */ + + +#define RTW_WKARD_BFEE_DISABLE_NG16 + +#define RTW_WKARD_HW_WMM_ALLOCATE + +#ifdef RTW_WKARD_BFEE_AID +#define RTW_WKARD_BFEE_SET_AID +#endif + +#define RTW_WKARD_AP_CLIENT_ADD_DEL_NTY + +#ifdef RTW_WKARD_DISABLE_2G40M_ULOFDMA +#define RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA +#endif + +#endif /*_PHL_CONFIG_H_*/ diff --git a/phl/phl_connect.c b/phl/phl_connect.c new file mode 100644 index 0000000..fe28c9f --- /dev/null +++ b/phl/phl_connect.c @@ -0,0 +1,533 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "phl_headers.h" + +#ifdef CONFIG_STA_CMD_DISPR +enum rtw_phl_status rtw_phl_connect_prepare(void *phl, + struct rtw_wifi_role_t *wrole, + u8 *addr) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_START); + msg.band_idx = wrole->hw_band; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} + +enum rtw_phl_status +rtw_phl_connect_linked(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + u8 *sta_addr) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_LINKED); + msg.band_idx = wrole->hw_band; + msg.rsvd[0] = sta; + msg.rsvd[1] = sta_addr; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} + +enum rtw_phl_status rtw_phl_connected(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_END); + msg.band_idx = wrole->hw_band; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} + +enum rtw_phl_status rtw_phl_disconnect(void *phl, + struct rtw_wifi_role_t *wrole, + bool is_disconnect) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + if(is_disconnect) { + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_DISCONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT_PREPARE); + } else { + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT); + } + + msg.band_idx = wrole->hw_band; + msg.rsvd[0] = (u8*)wrole; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} +#else /* CONFIG_STA_CMD_DISPR */ +enum rtw_phl_status rtw_phl_connect_prepare(void *phl, + struct rtw_wifi_role_t *wrole, + u8 *addr) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); + wrole->mstate = MLME_LINKING; + psts = phl_role_notify(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s role notify failed\n", __func__); + goto _exit; + } + psts = phl_mr_info_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s mr info upt failed\n", __func__); + goto _exit; + } + + psts = rtw_phl_mr_rx_filter(phl, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_rx_filter failed\n", __func__); + goto _exit; + } + +#ifdef CONFIG_PHL_P2PPS + /* pasue all NoA */ + phl_p2pps_noa_all_role_pause(phl, wrole->hw_band); +#endif + + PHL_DUMP_MR_EX(phl_info); +_exit: + FUNCOUT(); + return psts; +} + +enum rtw_phl_status rtw_phl_connected(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); + if (wrole->type == PHL_RTYPE_STATION || wrole->type == PHL_RTYPE_P2P_GC) { + psts = phl_role_notify(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s role notify failed\n", __func__); + goto _exit; + } + } + + psts = phl_mr_info_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s mr info upt failed\n", __func__); + goto _exit; + } + + psts = rtw_phl_mr_rx_filter(phl, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_rx_filter failed\n", __func__); + goto _exit; + } + + psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_STA_CONN_END); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_tsf_sync failed\n", __func__); + goto _exit; + } + #if 0 + psts = phl_mr_state_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s phl_mr_state_upt failed\n", __func__); + goto _exit; + } + #endif + + PHL_DUMP_MR_EX(phl_info); +_exit: + FUNCOUT(); + return psts; +} +enum rtw_phl_status rtw_phl_disconnect_prepare(void *phl, + struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); +#ifdef CONFIG_PHL_P2PPS + /* disable NoA for this role */ + phl_p2pps_noa_disable_all(phl_info, wrole); + /* pasue buddy NoA */ + phl_p2pps_noa_all_role_pause(phl_info, wrole->hw_band); +#endif + FUNCOUT(); + return psts; +} + +enum rtw_phl_status rtw_phl_disconnect(void *phl, + struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); + if (wrole->type == PHL_RTYPE_STATION || wrole->type == PHL_RTYPE_P2P_GC) { + psts = phl_role_notify(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s role notify failed\n", __func__); + goto _exit; + } + } + + psts = phl_mr_info_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s mr info upt failed\n", __func__); + goto _exit; + } + + psts = rtw_phl_mr_rx_filter(phl, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_rx_filter failed\n", __func__); + goto _exit; + } + + psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_STA_DIS_CONN); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_tsf_sync failed\n", __func__); + goto _exit; + } + psts = phl_mr_state_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s phl_mr_state_upt failed\n", __func__); + goto _exit; + } + rtw_hal_disconnect_notify(phl_info->hal, &wrole->chandef); + +#ifdef CONFIG_PHL_P2PPS + /* resume buddy NoA */ + phl_p2pps_noa_all_role_resume(phl, wrole->hw_band); +#endif + PHL_DUMP_MR_EX(phl_info); +_exit: + FUNCOUT(); + return psts; +} +#endif + +#ifdef CONFIG_AP_CMD_DISPR +enum rtw_phl_status rtw_phl_ap_started(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_START); + msg.band_idx = wrole->hw_band; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} + +enum rtw_phl_status rtw_phl_ap_stop(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_STOP); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_STOP_PREPARE); + msg.band_idx = wrole->hw_band; + msg.rsvd[0] = (u8*)wrole; + + phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(phl_status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n", + __FUNCTION__); + goto exit; + } + +exit: + return phl_status; +} +#else /* CONFIG_AP_CMD_DISPR */ +enum rtw_phl_status rtw_phl_ap_start_prepare(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + + FUNCIN(); +#ifdef CONFIG_PHL_P2PPS + /* pasue all NoA */ + phl_p2pps_noa_all_role_pause(phl, wrole->hw_band); +#endif + FUNCOUT(); + return psts; +} +enum rtw_phl_status rtw_phl_ap_started(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); + psts = phl_role_notify(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s role notify failed\n", __func__); + goto _exit; + } + psts = phl_mr_info_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s mr info upt failed\n", __func__); + goto _exit; + } + psts = rtw_phl_mr_rx_filter(phl, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_rx_filter failed\n", __func__); + goto _exit; + } + + psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_AP_START); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_tsf_sync failed\n", __func__); + goto _exit; + } + psts = phl_mr_state_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s phl_mr_state_upt failed\n", __func__); + goto _exit; + } + + PHL_DUMP_MR_EX(phl_info); + +_exit: + FUNCOUT(); + return psts; +} + +enum rtw_phl_status rtw_phl_ap_stop_prepare(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); +#ifdef CONFIG_PHL_P2PPS + /* disable NoA for this role */ + phl_p2pps_noa_disable_all(phl_info, wrole); + /* pasue buddy NoA */ + phl_p2pps_noa_all_role_pause(phl_info, wrole->hw_band); +#endif + FUNCOUT(); + return psts; +} + +enum rtw_phl_status rtw_phl_ap_stop(void *phl, struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + FUNCIN(); + wrole->mstate = MLME_NO_LINK; + psts = phl_role_notify(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s role notify failed\n", __func__); + goto _exit; + } + + psts = phl_mr_info_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s mr info upt failed\n", __func__); + goto _exit; + } + psts = rtw_phl_mr_rx_filter(phl, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_rx_filter failed\n", __func__); + goto _exit; + } + + psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_AP_STOP); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s set mr_tsf_sync failed\n", __func__); + goto _exit; + } + psts = phl_mr_state_upt(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s phl_mr_state_upt failed\n", __func__); + goto _exit; + } + +#ifdef RTW_PHL_BCN + psts = rtw_phl_free_bcn_entry(phl_info, wrole); + if (psts != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s phl_free_bcn_entry failed\n", __func__); + goto _exit; + } +#endif + rtw_hal_disconnect_notify(phl_info->hal, &wrole->chandef); +#ifdef CONFIG_PHL_P2PPS + /* resume buddy NoA */ + phl_p2pps_noa_all_role_resume(phl, wrole->hw_band); +#endif + PHL_DUMP_MR_EX(phl_info); +_exit: + FUNCOUT(); + return psts; +} +#endif + +#ifdef CONFIG_IBSS_CMD_DISPR +enum rtw_phl_status rtw_phl_ibss_started(void *phl, struct rtw_wifi_role_t *wrole) +{ + PHL_ERR("%s failed, cmd dispatcher not support\n", __func__); + return RTW_PHL_STATUS_FAILURE; +} +#else /* CONFIG_IBSS_CMD_DISPR */ +enum rtw_phl_status rtw_phl_ibss_started(void *phl, struct rtw_wifi_role_t *wrole) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + +#ifdef RTW_WKARD_IBSS_SNIFFER_MODE + rtw_hal_set_rxfltr_by_mode(phl_info->hal, wrole->hw_band, + RX_FLTR_MODE_SNIFFER); +#endif + + return RTW_PHL_STATUS_SUCCESS; +} + +#endif + +enum rtw_phl_status +rtw_phl_disconnected_resume_hdlr(void *phl, + struct rtw_wifi_role_t *wrole) +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s wrole->id(%d)\n", + __func__, wrole->id); +#ifdef CONFIG_PHL_P2PPS + /* resume buddy NoA */ + phl_p2pps_noa_all_role_resume(phl_info, wrole->hw_band); +#endif +#ifdef CONFIG_MCC_SUPPORT + /* Enable MR coex mechanism(if needed) */ + psts = phl_mr_coex_handle(phl_info, wrole, 0, wrole->hw_band, + MR_COEX_TRIG_BY_DIS_LINKING); +#endif + PHL_DUMP_MR_EX(phl_info); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s psts(%d)\n", + __func__, psts); + return psts; +} + +enum rtw_phl_status +rtw_phl_ap_stop_resume_hdlr(void *phl, + struct rtw_wifi_role_t *wrole) + +{ + enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s wrole->id(%d)\n", + __func__, wrole->id); +#ifdef CONFIG_PHL_P2PPS + /* resume buddy NoA */ + phl_p2pps_noa_all_role_resume(phl_info, wrole->hw_band); +#endif +#ifdef CONFIG_MCC_SUPPORT + /* Enable MR coex mechanism(if needed) */ + psts = phl_mr_coex_handle(phl_info, wrole, 0, wrole->hw_band, + MR_COEX_TRIG_BY_DIS_LINKING); +#endif + PHL_DUMP_MR_EX(phl_info); + PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s psts(%d)\n", + __func__, psts); + return psts; +} + +#ifdef RTW_WKARD_P2P_LISTEN +enum rtw_phl_status rtw_phl_p2p_listen_start(void *phl, struct rtw_wifi_role_t *wrole) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + rtw_hal_set_rxfltr_by_mode(phl_info->hal, wrole->hw_band, + RX_FLTR_MODE_SNIFFER); + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status rtw_phl_p2p_listen_end(void *phl, struct rtw_wifi_role_t *wrole) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + /* restore rx filter mode */ + rtw_phl_mr_rx_filter(phl_info, wrole); + + return RTW_PHL_STATUS_SUCCESS; +} +#endif /* RTW_WKARD_P2P_LISTEN */ diff --git a/phl/phl_connect.h b/phl/phl_connect.h new file mode 100644 index 0000000..786b57c --- /dev/null +++ b/phl/phl_connect.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_CONNECT_H_ +#define _PHL_CONNECT_H_ + +/** + * rtw_phl_connect_prepare() - Prepare hardware setting for connecting + * @phl: struct phl_info_t * + * @wrole: struct rtw_wifi_role_t * + * @addr: target mac address + * + * Do all necessary hardware setting for connecting. + * + * Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail. + */ +enum rtw_phl_status rtw_phl_connect_prepare(void *phl, + struct rtw_wifi_role_t *wrole, + u8 *addr); + +/** + * rtw_phl_connect_linked() - update media status + * @phl: struct phl_info_t * + * @wrole: struct rtw_wifi_role_t * + * @sta: struct rtw_phl_stainfo_t * + * @sta_addr: target mac address + * + * Do all necessary hardware setting for linked. + * + * Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail. + */ +enum rtw_phl_status +rtw_phl_connect_linked(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta, + u8 *sta_addr); + +/** + * rtw_phl_connected() - Config hardware setting for connected + * @phl: struct phl_info_t * + * @wrole: struct rtw_wifi_role_t * + * @sta: target station info + * + * Do all necessary hardware setting for connected. + * + * Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail. + */ +enum rtw_phl_status rtw_phl_connected(void *phl, + struct rtw_wifi_role_t *wrole, + struct rtw_phl_stainfo_t *sta); + +#ifdef CONFIG_STA_CMD_DISPR +enum rtw_phl_status rtw_phl_disconnect(void *phl, + struct rtw_wifi_role_t *wrole, + bool is_disconnect); +#else +enum rtw_phl_status rtw_phl_disconnect_prepare(void *phl, + struct rtw_wifi_role_t *wrole); +enum rtw_phl_status rtw_phl_disconnect(void *phl, + struct rtw_wifi_role_t *wrole); +#endif + +enum rtw_phl_status rtw_phl_ap_start_prepare(void *phl, + struct rtw_wifi_role_t *wrole); +enum rtw_phl_status rtw_phl_ap_started(void *phl, + struct rtw_wifi_role_t *wrole); +enum rtw_phl_status rtw_phl_ap_stop_prepare(void *phl, + struct rtw_wifi_role_t *wrole); +enum rtw_phl_status rtw_phl_ap_stop(void *phl, + struct rtw_wifi_role_t *wrole); + +enum rtw_phl_status rtw_phl_ibss_started(void *phl, + struct rtw_wifi_role_t *wrole); + +enum rtw_phl_status +rtw_phl_disconnected_resume_hdlr(void *phl, + struct rtw_wifi_role_t *wrole); + +enum rtw_phl_status +rtw_phl_ap_stop_resume_hdlr(void *phl, + struct rtw_wifi_role_t *wrole); + +#ifdef RTW_WKARD_P2P_LISTEN +enum rtw_phl_status rtw_phl_p2p_listen_start(void *phl, struct rtw_wifi_role_t *wrole); + +enum rtw_phl_status rtw_phl_p2p_listen_end(void *phl, struct rtw_wifi_role_t *wrole); +#endif /* RTW_WKARD_P2P_LISTEN */ + +#endif /* _PHL_CONNECT_H_ */ diff --git a/phl/phl_country.c b/phl/phl_country.c new file mode 100644 index 0000000..9821a32 --- /dev/null +++ b/phl/phl_country.c @@ -0,0 +1,260 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "phl_headers.h" +#include "phl_country.h" + +const struct country_domain_mapping cdmap[MAX_COUNTRY_NUM] = { + {0x4d, 0x00, {'A', 'R'}, TPO_NA, 0x0f}, /* 0000 */ + {0x61, 0x00, {'B', 'O'}, TPO_NA, 0x0f}, /* 0001 */ + {0x62, 0x00, {'B', 'R'}, TPO_NA, 0x0f}, /* 0002 */ + {0x76, 0x00, {'C', 'L'}, TPO_CHILE, 0x0f}, /* 0003 */ + {0x76, 0x00, {'C', 'O'}, TPO_NA, 0x0f}, /* 0004 */ + {0x76, 0x00, {'C', 'R'}, TPO_NA, 0x0f}, /* 0005 */ + {0x76, 0x00, {'E', 'C'}, TPO_NA, 0x0f}, /* 0006 */ + {0x76, 0x00, {'S', 'V'}, TPO_NA, 0x0f}, /* 0007 */ + {0x76, 0x00, {'G', 'T'}, TPO_NA, 0x0f}, /* 0008 */ + {0x32, 0x00, {'H', 'N'}, TPO_NA, 0x0f}, /* 0009 */ + {0x4d, 0x00, {'M', 'X'}, TPO_NA, 0x0f}, /* 0010 */ + {0x76, 0x00, {'N', 'I'}, TPO_NA, 0x0f}, /* 0011 */ + {0x76, 0x00, {'P', 'A'}, TPO_NA, 0x0f}, /* 0012 */ + {0x76, 0x00, {'P', 'Y'}, TPO_NA, 0x0f}, /* 0013 */ + {0x76, 0x00, {'P', 'E'}, TPO_NA, 0x0f}, /* 0014 */ + {0x76, 0x7f, {'U', 'S'}, TPO_NA, 0x0f}, /* 0015 */ + {0x30, 0x00, {'U', 'Y'}, TPO_NA, 0x0f}, /* 0016 */ + {0x30, 0x00, {'V', 'E'}, TPO_NA, 0x0f}, /* 0017 */ + {0x76, 0x00, {'P', 'R'}, TPO_NA, 0x0f}, /* 0018 */ + {0x76, 0x00, {'D', 'O'}, TPO_NA, 0x0f}, /* 0019 */ + {0x5e, 0x00, {'A', 'T'}, TPO_NA, 0x0f}, /* 0020 */ + {0x5e, 0x00, {'B', 'E'}, TPO_NA, 0x0f}, /* 0021 */ + {0x5e, 0x00, {'C', 'Y'}, TPO_NA, 0x0f}, /* 0022 */ + {0x5e, 0x00, {'C', 'Z'}, TPO_NA, 0x0f}, /* 0023 */ + {0x5e, 0x00, {'D', 'K'}, TPO_NA, 0x0f}, /* 0024 */ + {0x5e, 0x00, {'E', 'E'}, TPO_NA, 0x0f}, /* 0025 */ + {0x5e, 0x00, {'F', 'I'}, TPO_NA, 0x0f}, /* 0026 */ + {0x5e, 0x00, {'F', 'R'}, TPO_NA, 0x0f}, /* 0027 */ + {0x5e, 0x00, {'D', 'E'}, TPO_NA, 0x0f}, /* 0028 */ + {0x5e, 0x00, {'G', 'R'}, TPO_NA, 0x0f}, /* 0029 */ + {0x5e, 0x00, {'H', 'U'}, TPO_NA, 0x0f}, /* 0030 */ + {0x5e, 0x00, {'I', 'S'}, TPO_NA, 0x0f}, /* 0031 */ + {0x5e, 0x00, {'I', 'E'}, TPO_NA, 0x0f}, /* 0032 */ + {0x5e, 0x00, {'I', 'T'}, TPO_NA, 0x0f}, /* 0033 */ + {0x5e, 0x00, {'L', 'V'}, TPO_NA, 0x0f}, /* 0034 */ + {0x5e, 0x00, {'L', 'I'}, TPO_NA, 0x0f}, /* 0035 */ + {0x5e, 0x00, {'L', 'T'}, TPO_NA, 0x0f}, /* 0036 */ + {0x5e, 0x00, {'L', 'U'}, TPO_NA, 0x0f}, /* 0037 */ + {0x5e, 0x00, {'M', 'T'}, TPO_NA, 0x0f}, /* 0038 */ + {0x5e, 0x00, {'M', 'C'}, TPO_NA, 0x0f}, /* 0039 */ + {0x5e, 0x00, {'N', 'L'}, TPO_NA, 0x0f}, /* 0040 */ + {0x5e, 0x00, {'N', 'O'}, TPO_NA, 0x0f}, /* 0041 */ + {0x5e, 0x00, {'P', 'L'}, TPO_NA, 0x0f}, /* 0042 */ + {0x5e, 0x00, {'P', 'T'}, TPO_NA, 0x0f}, /* 0043 */ + {0x5e, 0x00, {'S', 'K'}, TPO_NA, 0x0f}, /* 0044 */ + {0x5e, 0x00, {'S', 'I'}, TPO_NA, 0x0f}, /* 0045 */ + {0x5e, 0x00, {'E', 'S'}, TPO_NA, 0x0f}, /* 0046 */ + {0x5e, 0x00, {'S', 'E'}, TPO_NA, 0x0f}, /* 0047 */ + {0x5e, 0x00, {'C', 'H'}, TPO_NA, 0x0f}, /* 0048 */ + {0x5e, 0x00, {'G', 'B'}, TPO_NA, 0x0f}, /* 0049 */ + {0x5e, 0x00, {'A', 'L'}, TPO_NA, 0x0f}, /* 0050 */ + {0x5e, 0x00, {'A', 'Z'}, TPO_NA, 0x0f}, /* 0051 */ + {0x06, 0x00, {'B', 'H'}, TPO_NA, 0x0f}, /* 0052 */ + {0x5e, 0x00, {'B', 'A'}, TPO_NA, 0x0f}, /* 0053 */ + {0x5e, 0x00, {'B', 'G'}, TPO_NA, 0x0f}, /* 0054 */ + {0x5e, 0x00, {'H', 'R'}, TPO_NA, 0x0f}, /* 0055 */ + {0x3c, 0x00, {'E', 'G'}, TPO_NA, 0x0f}, /* 0056 */ + {0x5e, 0x00, {'G', 'H'}, TPO_NA, 0x0f}, /* 0057 */ + {0x05, 0x00, {'I', 'Q'}, TPO_NA, 0x0f}, /* 0058 */ + {0x5e, 0x00, {'I', 'L'}, TPO_NA, 0x0f}, /* 0059 */ + {0x05, 0x00, {'J', 'O'}, TPO_NA, 0x0f}, /* 0060 */ + {0x5e, 0x00, {'K', 'Z'}, TPO_NA, 0x0f}, /* 0061 */ + {0x5e, 0x00, {'K', 'E'}, TPO_NA, 0x0f}, /* 0062 */ + {0x5e, 0x00, {'K', 'W'}, TPO_NA, 0x0f}, /* 0063 */ + {0x5e, 0x00, {'K', 'G'}, TPO_NA, 0x0f}, /* 0064 */ + {0x5e, 0x00, {'L', 'B'}, TPO_NA, 0x0f}, /* 0065 */ + {0x5e, 0x00, {'L', 'S'}, TPO_NA, 0x0f}, /* 0066 */ + {0x3a, 0x00, {'M', 'K'}, TPO_NA, 0x0f}, /* 0067 */ + {0x3c, 0x00, {'M', 'A'}, TPO_NA, 0x0f}, /* 0068 */ + {0x5e, 0x00, {'M', 'Z'}, TPO_NA, 0x0f}, /* 0069 */ + {0x5e, 0x00, {'N', 'A'}, TPO_NA, 0x0f}, /* 0070 */ + {0x75, 0x00, {'N', 'G'}, TPO_NA, 0x0f}, /* 0071 */ + {0x5e, 0x00, {'O', 'M'}, TPO_NA, 0x0f}, /* 0072 */ + {0x5e, 0x00, {'Q', 'A'}, TPO_QATAR, 0x0f}, /* 0073 */ + {0x5e, 0x00, {'R', 'O'}, TPO_NA, 0x0f}, /* 0074 */ + {0x09, 0x00, {'R', 'U'}, TPO_NA, 0x0f}, /* 0075 */ + {0x5e, 0x00, {'S', 'A'}, TPO_NA, 0x0f}, /* 0076 */ + {0x3a, 0x00, {'S', 'N'}, TPO_NA, 0x0f}, /* 0077 */ + {0x5e, 0x00, {'R', 'S'}, TPO_NA, 0x0f}, /* 0078 */ + {0x3a, 0x00, {'M', 'E'}, TPO_NA, 0x0f}, /* 0079 */ + {0x5e, 0x00, {'Z', 'A'}, TPO_NA, 0x0f}, /* 0080 */ + {0x5e, 0x00, {'T', 'R'}, TPO_NA, 0x0f}, /* 0081 */ + {0x5e, 0x00, {'U', 'A'}, TPO_UKRAINE, 0x0f}, /* 0082 */ + {0x5e, 0x00, {'A', 'E'}, TPO_NA, 0x0f}, /* 0083 */ + {0x3a, 0x00, {'Y', 'E'}, TPO_NA, 0x0f}, /* 0084 */ + {0x5e, 0x00, {'Z', 'W'}, TPO_NA, 0x0f}, /* 0085 */ + {0x5e, 0x00, {'B', 'D'}, TPO_NA, 0x0f}, /* 0086 */ + {0x5e, 0x00, {'K', 'H'}, TPO_NA, 0x0f}, /* 0087 */ + {0x06, 0x00, {'C', 'N'}, TPO_CN, 0x0f}, /* 0088 */ + {0x5e, 0x00, {'H', 'K'}, TPO_NA, 0x0f}, /* 0089 */ + {0x06, 0x00, {'I', 'N'}, TPO_NA, 0x0f}, /* 0090 */ + {0x5d, 0x00, {'I', 'D'}, TPO_NA, 0x0f}, /* 0091 */ + {0x4b, 0x00, {'K', 'R'}, TPO_NA, 0x0f}, /* 0092 */ + {0x07, 0x00, {'M', 'Y'}, TPO_NA, 0x0f}, /* 0093 */ + {0x51, 0x00, {'P', 'K'}, TPO_NA, 0x0f}, /* 0094 */ + {0x5e, 0x00, {'P', 'H'}, TPO_NA, 0x0f}, /* 0095 */ + {0x5e, 0x00, {'S', 'G'}, TPO_NA, 0x0f}, /* 0096 */ + {0x5e, 0x00, {'L', 'K'}, TPO_NA, 0x0f}, /* 0097 */ + {0x76, 0x00, {'T', 'W'}, TPO_NA, 0x0f}, /* 0098 */ + {0x5e, 0x00, {'T', 'H'}, TPO_NA, 0x0f}, /* 0099 */ + {0x5e, 0x00, {'V', 'N'}, TPO_NA, 0x0f}, /* 0100 */ + {0x03, 0x00, {'A', 'U'}, TPO_NA, 0x0f}, /* 0101 */ + {0x03, 0x00, {'N', 'Z'}, TPO_NA, 0x0f}, /* 0102 */ + {0x5e, 0x00, {'P', 'G'}, TPO_NA, 0x0f}, /* 0103 */ + {0x2b, 0x00, {'C', 'A'}, TPO_NA, 0x0f}, /* 0104 */ + {0x7d, 0x00, {'J', 'P'}, TPO_NA, 0x0f}, /* 0105 */ + {0x76, 0x00, {'J', 'M'}, TPO_NA, 0x0f}, /* 0106 */ + {0x76, 0x00, {'A', 'N'}, TPO_NA, 0x0f}, /* 0107 */ + {0x76, 0x00, {'T', 'T'}, TPO_NA, 0x0f}, /* 0108 */ + {0x04, 0x00, {'T', 'N'}, TPO_NA, 0x0f}, /* 0109 */ + {0x42, 0x00, {'A', 'F'}, TPO_NA, 0x0f}, /* 0110 */ + {0x00, 0x00, {'D', 'Z'}, TPO_NA, 0x0f}, /* 0111 */ + {0x76, 0x00, {'A', 'S'}, TPO_NA, 0x0f}, /* 0112 */ + {0x3a, 0x00, {'A', 'D'}, TPO_NA, 0x0f}, /* 0113 */ + {0x5e, 0x00, {'A', 'O'}, TPO_NA, 0x0f}, /* 0114 */ + {0x5e, 0x00, {'A', 'I'}, TPO_NA, 0x0f}, /* 0115 */ + {0x26, 0x00, {'A', 'Q'}, TPO_NA, 0x0f}, /* 0116 */ + {0x76, 0x00, {'A', 'G'}, TPO_NA, 0x0f}, /* 0117 */ + {0x5e, 0x00, {'A', 'M'}, TPO_NA, 0x0f}, /* 0118 */ + {0x76, 0x00, {'A', 'W'}, TPO_NA, 0x0f}, /* 0119 */ + {0x76, 0x00, {'B', 'S'}, TPO_NA, 0x0f}, /* 0120 */ + {0x76, 0x00, {'B', 'B'}, TPO_NA, 0x0f}, /* 0121 */ + {0x08, 0x00, {'B', 'Y'}, TPO_NA, 0x07}, /* 0122 */ + {0x76, 0x00, {'B', 'Z'}, TPO_NA, 0x0f}, /* 0123 */ + {0x3a, 0x00, {'B', 'J'}, TPO_NA, 0x0f}, /* 0124 */ + {0x76, 0x00, {'B', 'M'}, TPO_NA, 0x0f}, /* 0125 */ + {0x5e, 0x00, {'B', 'T'}, TPO_NA, 0x0f}, /* 0126 */ + {0x5e, 0x00, {'B', 'W'}, TPO_NA, 0x0f}, /* 0127 */ + {0x5e, 0x00, {'B', 'V'}, TPO_NA, 0x0f}, /* 0128 */ + {0x3a, 0x00, {'I', 'O'}, TPO_NA, 0x0f}, /* 0129 */ + {0x76, 0x00, {'V', 'G'}, TPO_NA, 0x0f}, /* 0130 */ + {0x06, 0x00, {'B', 'N'}, TPO_NA, 0x0f}, /* 0131 */ + {0x5e, 0x00, {'B', 'F'}, TPO_NA, 0x0f}, /* 0132 */ + {0x3a, 0x00, {'M', 'M'}, TPO_NA, 0x0f}, /* 0133 */ + {0x3a, 0x00, {'B', 'I'}, TPO_NA, 0x0f}, /* 0134 */ + {0x5e, 0x00, {'C', 'M'}, TPO_NA, 0x0f}, /* 0135 */ + {0x5e, 0x00, {'C', 'V'}, TPO_NA, 0x0f}, /* 0136 */ + {0x76, 0x00, {'K', 'Y'}, TPO_NA, 0x0f}, /* 0137 */ + {0x3a, 0x00, {'C', 'F'}, TPO_NA, 0x0f}, /* 0138 */ + {0x3a, 0x00, {'T', 'D'}, TPO_NA, 0x0f}, /* 0139 */ + {0x03, 0x00, {'C', 'X'}, TPO_NA, 0x0f}, /* 0140 */ + {0x3a, 0x00, {'C', 'C'}, TPO_NA, 0x0f}, /* 0141 */ + {0x3a, 0x00, {'K', 'M'}, TPO_NA, 0x0f}, /* 0142 */ + {0x3a, 0x00, {'C', 'G'}, TPO_NA, 0x0f}, /* 0143 */ + {0x3a, 0x00, {'C', 'D'}, TPO_NA, 0x0f}, /* 0144 */ + {0x5e, 0x00, {'C', 'K'}, TPO_NA, 0x0f}, /* 0145 */ + {0x42, 0x00, {'C', 'I'}, TPO_NA, 0x0f}, /* 0146 */ + {0x3a, 0x00, {'D', 'J'}, TPO_NA, 0x0f}, /* 0147 */ + {0x76, 0x00, {'D', 'M'}, TPO_NA, 0x0f}, /* 0148 */ + {0x5e, 0x00, {'G', 'Q'}, TPO_NA, 0x0f}, /* 0149 */ + {0x3a, 0x00, {'E', 'R'}, TPO_NA, 0x0f}, /* 0150 */ + {0x3a, 0x00, {'E', 'T'}, TPO_NA, 0x0f}, /* 0151 */ + {0x3a, 0x00, {'F', 'K'}, TPO_NA, 0x0f}, /* 0152 */ + {0x3a, 0x00, {'F', 'O'}, TPO_NA, 0x0f}, /* 0153 */ + {0x76, 0x00, {'F', 'J'}, TPO_NA, 0x0f}, /* 0154 */ + {0x3a, 0x00, {'G', 'F'}, TPO_NA, 0x0f}, /* 0155 */ + {0x3a, 0x00, {'P', 'F'}, TPO_NA, 0x0f}, /* 0156 */ + {0x3a, 0x00, {'T', 'F'}, TPO_NA, 0x0f}, /* 0157 */ + {0x5e, 0x00, {'G', 'A'}, TPO_NA, 0x0f}, /* 0158 */ + {0x3a, 0x00, {'G', 'M'}, TPO_NA, 0x0f}, /* 0159 */ + {0x5e, 0x00, {'G', 'E'}, TPO_NA, 0x0f}, /* 0160 */ + {0x3a, 0x00, {'G', 'I'}, TPO_NA, 0x0f}, /* 0161 */ + {0x5e, 0x00, {'G', 'L'}, TPO_NA, 0x0f}, /* 0162 */ + {0x76, 0x00, {'G', 'D'}, TPO_NA, 0x0f}, /* 0163 */ + {0x3a, 0x00, {'G', 'P'}, TPO_NA, 0x0f}, /* 0164 */ + {0x76, 0x00, {'G', 'U'}, TPO_NA, 0x0f}, /* 0165 */ + {0x5e, 0x00, {'G', 'G'}, TPO_NA, 0x0f}, /* 0166 */ + {0x3a, 0x00, {'G', 'N'}, TPO_NA, 0x0f}, /* 0167 */ + {0x3a, 0x00, {'G', 'W'}, TPO_NA, 0x0f}, /* 0168 */ + {0x44, 0x00, {'G', 'Y'}, TPO_NA, 0x0f}, /* 0169 */ + {0x76, 0x00, {'H', 'T'}, TPO_NA, 0x07}, /* 0170 */ + {0x03, 0x00, {'H', 'M'}, TPO_NA, 0x0f}, /* 0171 */ + {0x3a, 0x00, {'V', 'A'}, TPO_NA, 0x0f}, /* 0172 */ + {0x3a, 0x00, {'I', 'M'}, TPO_NA, 0x0f}, /* 0173 */ + {0x3a, 0x00, {'J', 'E'}, TPO_NA, 0x0f}, /* 0174 */ + {0x5e, 0x00, {'K', 'I'}, TPO_NA, 0x0f}, /* 0175 */ + {0x5e, 0x00, {'L', 'A'}, TPO_NA, 0x0f}, /* 0176 */ + {0x5e, 0x00, {'L', 'R'}, TPO_NA, 0x0f}, /* 0177 */ + {0x5e, 0x00, {'L', 'Y'}, TPO_NA, 0x0f}, /* 0178 */ + {0x5e, 0x00, {'M', 'O'}, TPO_NA, 0x0f}, /* 0179 */ + {0x5e, 0x00, {'M', 'G'}, TPO_NA, 0x0f}, /* 0180 */ + {0x5e, 0x00, {'M', 'W'}, TPO_NA, 0x0f}, /* 0181 */ + {0x3c, 0x00, {'M', 'V'}, TPO_NA, 0x0f}, /* 0182 */ + {0x5e, 0x00, {'M', 'L'}, TPO_NA, 0x0f}, /* 0183 */ + {0x76, 0x00, {'M', 'H'}, TPO_NA, 0x0f}, /* 0184 */ + {0x3a, 0x00, {'M', 'Q'}, TPO_NA, 0x0f}, /* 0185 */ + {0x5e, 0x00, {'M', 'R'}, TPO_NA, 0x0f}, /* 0186 */ + {0x5e, 0x00, {'M', 'U'}, TPO_NA, 0x0f}, /* 0187 */ + {0x5e, 0x00, {'Y', 'T'}, TPO_NA, 0x0f}, /* 0188 */ + {0x76, 0x00, {'F', 'M'}, TPO_NA, 0x0f}, /* 0189 */ + {0x5e, 0x00, {'M', 'D'}, TPO_NA, 0x0f}, /* 0190 */ + {0x5e, 0x00, {'M', 'N'}, TPO_NA, 0x0f}, /* 0191 */ + {0x3a, 0x00, {'M', 'S'}, TPO_NA, 0x0f}, /* 0192 */ + {0x3a, 0x00, {'N', 'R'}, TPO_NA, 0x0f}, /* 0193 */ + {0x06, 0x00, {'N', 'P'}, TPO_NA, 0x0f}, /* 0194 */ + {0x3a, 0x00, {'N', 'C'}, TPO_NA, 0x0f}, /* 0195 */ + {0x5e, 0x00, {'N', 'E'}, TPO_NA, 0x0f}, /* 0196 */ + {0x03, 0x00, {'N', 'U'}, TPO_NA, 0x0f}, /* 0197 */ + {0x03, 0x00, {'N', 'F'}, TPO_NA, 0x0f}, /* 0198 */ + {0x76, 0x00, {'M', 'P'}, TPO_NA, 0x0f}, /* 0199 */ + {0x76, 0x00, {'P', 'W'}, TPO_NA, 0x0f}, /* 0200 */ + {0x3a, 0x00, {'R', 'E'}, TPO_NA, 0x0f}, /* 0201 */ + {0x5e, 0x00, {'R', 'W'}, TPO_NA, 0x0f}, /* 0202 */ + {0x3a, 0x00, {'S', 'H'}, TPO_NA, 0x0f}, /* 0203 */ + {0x76, 0x00, {'K', 'N'}, TPO_NA, 0x0f}, /* 0204 */ + {0x76, 0x00, {'L', 'C'}, TPO_NA, 0x0f}, /* 0205 */ + {0x76, 0x00, {'M', 'F'}, TPO_NA, 0x0f}, /* 0206 */ + {0x76, 0x00, {'S', 'X'}, TPO_NA, 0x0f}, /* 0207 */ + {0x3a, 0x00, {'P', 'M'}, TPO_NA, 0x0f}, /* 0208 */ + {0x76, 0x00, {'V', 'C'}, TPO_NA, 0x0f}, /* 0209 */ + {0x76, 0x00, {'W', 'S'}, TPO_NA, 0x0f}, /* 0210 */ + {0x3a, 0x00, {'S', 'M'}, TPO_NA, 0x0f}, /* 0211 */ + {0x76, 0x00, {'S', 'T'}, TPO_NA, 0x0f}, /* 0212 */ + {0x76, 0x00, {'S', 'C'}, TPO_NA, 0x0f}, /* 0213 */ + {0x5e, 0x00, {'S', 'L'}, TPO_NA, 0x0f}, /* 0214 */ + {0x3a, 0x00, {'S', 'B'}, TPO_NA, 0x0f}, /* 0215 */ + {0x3a, 0x00, {'S', 'O'}, TPO_NA, 0x0f}, /* 0216 */ + {0x3a, 0x00, {'G', 'S'}, TPO_NA, 0x0f}, /* 0217 */ + {0x74, 0x00, {'S', 'R'}, TPO_NA, 0x0f}, /* 0218 */ + {0x3a, 0x00, {'S', 'J'}, TPO_NA, 0x0f}, /* 0219 */ + {0x5e, 0x00, {'S', 'Z'}, TPO_NA, 0x0f}, /* 0220 */ + {0x5e, 0x00, {'T', 'J'}, TPO_NA, 0x0f}, /* 0221 */ + {0x5e, 0x00, {'T', 'Z'}, TPO_NA, 0x0f}, /* 0222 */ + {0x5e, 0x00, {'T', 'G'}, TPO_NA, 0x0f}, /* 0223 */ + {0x03, 0x00, {'T', 'K'}, TPO_NA, 0x0f}, /* 0224 */ + {0x3a, 0x00, {'T', 'O'}, TPO_NA, 0x0f}, /* 0225 */ + {0x3a, 0x00, {'T', 'M'}, TPO_NA, 0x0f}, /* 0226 */ + {0x3a, 0x00, {'T', 'C'}, TPO_NA, 0x0f}, /* 0227 */ + {0x21, 0x00, {'T', 'V'}, TPO_NA, 0x01}, /* 0228 */ + {0x3a, 0x00, {'U', 'G'}, TPO_NA, 0x0f}, /* 0229 */ + {0x76, 0x00, {'V', 'I'}, TPO_NA, 0x0f}, /* 0230 */ + {0x3c, 0x00, {'U', 'Z'}, TPO_NA, 0x0f}, /* 0231 */ + {0x26, 0x00, {'V', 'U'}, TPO_NA, 0x0f}, /* 0232 */ + {0x3a, 0x00, {'W', 'F'}, TPO_NA, 0x0f}, /* 0233 */ + {0x3c, 0x00, {'E', 'H'}, TPO_NA, 0x0f}, /* 0234 */ + {0x5e, 0x00, {'Z', 'M'}, TPO_NA, 0x0f}, /* 0235 */ + {0x3a, 0x00, {'I', 'R'}, TPO_NA, 0x01}, /* 0236 */ + {0x5e, 0x00, {'P', 'S'}, TPO_NA, 0x0f}, /* 0237 */ +}; + + + diff --git a/phl/phl_country.h b/phl/phl_country.h new file mode 100644 index 0000000..ceb41db --- /dev/null +++ b/phl/phl_country.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_COUNTRY_H_ +#define _PHL_COUNTRY_H_ + +#define REGULATION_COUNTRY_VERSION 31 + +#define MAX_COUNTRY_NUM 238 +enum TP_OVERWRITE { + TPO_CHILE = 0, + TPO_QATAR = 1, + TPO_UKRAINE = 2, + TPO_CN = 3, + TPO_NA = 4 +}; + +#define COUNTRY_CODE_LEN 2 +struct country_domain_mapping { + u8 domain_code; + u8 domain_code_6g; + char char2[COUNTRY_CODE_LEN]; + u8 tpo; /* tx power overwrite */ + + /* + * bit0: accept 11bgn + * bit1: accept 11a + * bit2: accept 11ac + * bit3: accept 11ax + */ + u8 support; +}; + + +#endif /* _PHL_COUNTRY_H_ */ diff --git a/phl/phl_debug.c b/phl/phl_debug.c new file mode 100644 index 0000000..0266835 --- /dev/null +++ b/phl/phl_debug.c @@ -0,0 +1,217 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_DEBUG_C_ +#include "phl_headers.h" + +#ifdef CONFIG_RTW_DEBUG + +u32 phl_log_components = COMP_PHL_DBG | + COMP_PHL_XMIT | + COMP_PHL_WOW | + /* COMP_PHL_CMDDISP |*/ + COMP_PHL_RECV | + COMP_PHL_MAC | +// COMP_PHL_PS | 0; + 0; +u8 phl_log_level = _PHL_INFO_; +struct dbg_mem_ctx debug_memory_ctx; + +void debug_dump_mac_address(u8 *mac_addr) +{ + if (mac_addr == NULL) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[dump mac addr] mac_addr is NULL\n"); + return; + } + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[MAC ADDRESS]\n"); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, + "%02X-%02X-%02X-%02X-%02X-%02X\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5]); +} + +void debug_dump_data(u8 *buf, u32 buf_len, const char *prefix) +{ + u32 i; + + if (buf == NULL) { + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "[debug dump] buf is NULL\n"); + return; + } + + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "[debug dump] %s\n", prefix); + for (i = 0; i < buf_len; i++) { + if (!(i % 8)) + PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "\n"); + PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "%02X ", buf[i]); + } + PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "\n"); +} + +void rt_alloc_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size, + const u8 *file_name, u32 line_num, const u8 *func_name) +{ + _os_list *list = &debug_memory_ctx.alloc_buf_list; + _os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct dbg_alloc_buf *dbg_buf = NULL; + u32 name_size = 0; + + FUNCIN(); + + dbg_buf = _os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(*dbg_buf)); + + dbg_buf->buf_ptr = buf_ptr; + dbg_buf->buf_size = buf_size; + + name_size = (_os_strlen((u8 *)file_name) > DEBUG_MAX_NAME_LEN) ? + DEBUG_MAX_NAME_LEN : _os_strlen((u8 *)file_name); + _os_mem_cpy(phl_to_drvpriv(phl_info), dbg_buf->file_name, (u8 *)file_name, name_size); + + dbg_buf->line_num = line_num; + + name_size = (_os_strlen((u8 *)func_name) > DEBUG_MAX_NAME_LEN) ? + DEBUG_MAX_NAME_LEN : _os_strlen((u8 *)func_name); + _os_mem_cpy(phl_to_drvpriv(phl_info), dbg_buf->func_name, (u8 *)func_name, name_size); + + _os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + + list_add_tail(&(dbg_buf->list), list); + debug_memory_ctx.alloc_buf_cnt++; + + _os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Allocate Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n", + dbg_buf->buf_ptr, dbg_buf->buf_size, dbg_buf->file_name, + dbg_buf->line_num, dbg_buf->func_name); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d", + debug_memory_ctx.alloc_buf_cnt); + + FUNCOUT(); +} + + +void rt_free_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size, + const u8 *file_name, u32 line_num, const u8 *func_name) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + _os_list *list = &debug_memory_ctx.alloc_buf_list; + _os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock; + struct dbg_alloc_buf *dbg_buf = NULL , *t; + u8 found = false; + + FUNCIN(); + + _os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + + phl_list_for_loop_safe(dbg_buf, t, struct dbg_alloc_buf, list, list) { + if (dbg_buf->buf_ptr == buf_ptr) { + list_del(&dbg_buf->list); + found = true; + break; + } + } + _os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + + if (true == found) { + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Free Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n", + dbg_buf->buf_ptr, dbg_buf->buf_size, file_name, + line_num, func_name); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d", + debug_memory_ctx.alloc_buf_cnt); + _os_mem_free(phl_to_drvpriv(phl_info), dbg_buf, sizeof(*dbg_buf)); + debug_memory_ctx.alloc_buf_cnt--; + } else { + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, + "WARNING, can not find allocated buffer in list\n"); + } + + FUNCOUT(); +} + + +void rt_mem_dbg_init(void *phl) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + _os_list *list = &debug_memory_ctx.alloc_buf_list; + _os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock; + + FUNCIN(); + debug_memory_ctx.alloc_buf_cnt = 0; + INIT_LIST_HEAD(list); + _os_spinlock_init(phl_to_drvpriv(phl_info), lock); + FUNCOUT(); +} + +void rt_mem_dbg_deinit(void *phl) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + _os_list *list = &debug_memory_ctx.alloc_buf_list; + _os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock; + struct dbg_alloc_buf *dbg_buf = NULL; + + FUNCIN(); + while (true != list_empty(list) || + 0 != debug_memory_ctx.alloc_buf_cnt) { + + _os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + dbg_buf = list_first_entry(list, struct dbg_alloc_buf, list); + list_del(&dbg_buf->list); + _os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL); + + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "FOUND non-freed Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n", + dbg_buf->buf_ptr, dbg_buf->buf_size, + dbg_buf->file_name, dbg_buf->line_num, + dbg_buf->func_name); + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d", + debug_memory_ctx.alloc_buf_cnt); + _os_mem_free(phl_to_drvpriv(phl_info), dbg_buf, sizeof(*dbg_buf)); + debug_memory_ctx.alloc_buf_cnt--; + } + _os_spinlock_init(phl_to_drvpriv(phl_info), lock); + + FUNCOUT(); +} + + +void phl_dbg_show_log_comp(u8 comp_bit) +{ + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[DBG] phl_log_components = 0x%x \n", phl_log_components); +} + +void phl_dbg_set_log_comp(u8 comp_bit) +{ + phl_log_components |= BIT(comp_bit); +} + +void phl_dbg_clear_log_comp(u8 comp_bit) +{ + phl_log_components &= (~BIT(comp_bit)); +} + +u32 rtw_phl_dbg_ctrl_comp(u8 ctrl, u8 comp_bit) +{ + if (1 == ctrl) { + phl_dbg_set_log_comp(comp_bit); + } else if (2 == ctrl) { + phl_dbg_clear_log_comp(comp_bit); + } + phl_dbg_show_log_comp(comp_bit); + + return phl_log_components; +} +#endif /* #ifdef CONFIG_PHL_DEBUG */ + diff --git a/phl/phl_debug.h b/phl/phl_debug.h new file mode 100644 index 0000000..c3c14f3 --- /dev/null +++ b/phl/phl_debug.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_DEBUG_H_ +#define _PHL_DEBUG_H_ + +/* phl log level */ +enum { + _PHL_NONE_ = 0, + _PHL_ALWAYS_ = 1, + _PHL_ERR_ = 2, + _PHL_WARNING_ = 3, + _PHL_INFO_ = 4, + _PHL_DEBUG_ = 5, + _PHL_MAX_ = 6 +}; + +#define PHL_PREFIX "PHL: " +#define HALPS_PREFIX "HALPS:" + +#define PHL_DBG_OUTBUF(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\ + do { \ + u32 *used_len_tmp = &(used_len); \ + if (*used_len_tmp < max_buff_len) \ + *used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\ + } while (0) + +#ifdef CONFIG_RTW_DEBUG + +/*Define the tracing components*/ +#define COMP_PHL_DBG BIT0 /* For function call tracing. */ +#define COMP_PHL_RECV BIT1 +#define COMP_PHL_XMIT BIT2 +#define COMP_PHL_MAC BIT3 +#define COMP_PHL_SOUND BIT4 +#define COMP_PHL_WOW BIT5 +#define COMP_PHL_TRIG BIT6 +#define COMP_PHL_PKTOFLD BIT7 +#define COMP_PHL_FSM BIT8 +#define COMP_PHL_PS BIT9 +#define COMP_PHL_PSTS BIT10 +#define COMP_PHL_BB BIT11 +#define COMP_PHL_RF BIT12 +#define COMP_PHL_LED BIT13 +#define COMP_PHL_MCC BIT14 +#define COMP_PHL_P2PPS BIT15 +#define COMP_PHL_ECSA BIT16 +#define COMP_PHL_CMDDISP BIT17 +#define COMP_PHL_BTC BIT18 +#define COMP_PHL_TWT BIT19 + +extern u32 phl_log_components; +extern u8 phl_log_level; +#define DEBUG_MAX_NAME_LEN 50 + +struct dbg_alloc_buf { + _os_list list; + u8 file_name[DEBUG_MAX_NAME_LEN]; + u8 func_name[DEBUG_MAX_NAME_LEN]; + u32 line_num; + u32 buf_size; + u8 *buf_ptr; +}; + +struct dbg_mem_ctx { + _os_list alloc_buf_list; + _os_lock alloc_buf_list_lock; + u32 alloc_buf_cnt; +}; + + +#undef PHL_TRACE +#define PHL_TRACE(comp, level, fmt, ...) \ + do {\ + if(((comp) & phl_log_components) && (level <= phl_log_level)) {\ + _os_dbgdump(PHL_PREFIX fmt, ##__VA_ARGS__);\ + } \ + } while (0) + +#undef PHL_DATA +#define PHL_DATA(comp, level, fmt, ...) \ + do {\ + if(((comp) & phl_log_components) && (level <= phl_log_level)) {\ + _os_dbgdump(KERN_CONT fmt, ##__VA_ARGS__);\ + } \ + } while (0) + +#undef PHL_ASSERT +#define PHL_ASSERT(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "ERROR " fmt, ##__VA_ARGS__);\ + _os_assert(true); \ + } while (0) + + +#undef PHL_PRINT +#define PHL_PRINT(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_ALWAYS_, fmt, ##__VA_ARGS__);\ + } while (0) + +#undef PHL_ERR +#define PHL_ERR(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "ERROR " fmt, ##__VA_ARGS__);\ + } while (0) + +#undef PHL_WARN +#define PHL_WARN(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "WARN " fmt, ##__VA_ARGS__);\ + } while (0) + +#undef PHL_INFO +#define PHL_INFO(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, fmt, ##__VA_ARGS__);\ + } while (0) + +#undef PHL_DBG +#define PHL_DBG(fmt, ...) \ + do {\ + PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, fmt, ##__VA_ARGS__);\ + } while (0) + +#define FUNCIN() PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Enter %s\n", __FUNCTION__) +#define FUNCOUT() PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Leave %s\n", __FUNCTION__) +#define FUNCIN_WSTS(_sts) PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Enter with 0x%08X %s\n", _sts, __FUNCTION__) +#define FUNCOUT_WSTS(_sts) PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Leave with 0x%08X %s\n", _sts, __FUNCTION__) + +void debug_dump_data(u8 *buf, u32 buf_len, const char *prefix); +void rt_alloc_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size, + const u8 *file_name, u32 line_num, const u8 *func_name); +void rt_free_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size, + const u8 *file_name, u32 line_num, const u8 *func_name); +void rt_mem_dbg_init(void *phl); +void rt_mem_dbg_deinit(void *phl); +u32 rtw_phl_dbg_ctrl_comp(u8 ctrl, u8 comp_bit); +void debug_dump_mac_address(u8 *mac_addr); + +#define phl_ops_error_msg(ops_fun) \ + PHL_ERR("### %s - Please hook phl_hci_ops.%s ###\n", __func__, ops_fun) + +#define hal_error_msg(ops_fun) \ + PHL_PRINT("### %s - Error : Please hook hal_ops.%s ###\n", __FUNCTION__, ops_fun) + +#else /* CONFIG_RTW_DEBUG */ + +#define PHL_TRACE(comp, level, fmt, ...) +#define PHL_PRINT(fmt, ...) +#define PHL_ERR(fmt, ...) +#define PHL_WARN(fmt, ...) +#define PHL_INFO(fmt, ...) +#define PHL_DBG(fmt, ...) +#define PHL_DATA(fmt, ...) +#define PHL_ASSERT(fmt, ...) +#define FUNCIN() +#define FUNCOUT() +#define FUNCIN_WSTS(_sts) +#define FUNCOUT_WSTS(_sts) +#define debug_dump_data(_buf, _buf_len, _prefix) +#define debug_dump_mac_address(_mac_addr) +#define rt_alloc_dbg_buf(_phl, _buf, _buf_size, _file_name, _line_num, \ + _func_name) +#define rt_free_dbg_buf(_phl, _buf, _buf_size, _file_name, _line_num, \ + _func_name) +#define rt_mem_dbg_init(_phl) +#define rt_mem_dbg_deinit(_phl) + +#define rtw_phl_dbg_ctrl_comp(_ctrl, _comp_bit) 0 +#define phl_ops_error_msg(ops_fun) do {} while (0) +#define hal_error_msg(ops_fun) do {} while (0) + +#endif /* CONFIG_RTW_DEBUG */ +#endif /* _PHL_DEBUG_H_ */ diff --git a/phl/phl_def.h b/phl/phl_def.h new file mode 100644 index 0000000..d7616b4 --- /dev/null +++ b/phl/phl_def.h @@ -0,0 +1,3200 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_DEF_H_ +#define _PHL_DEF_H_ + +enum phl_packet_type { + PACKET_NORMAL, + PACKET_DHCP, + PACKET_ARP, + PACKET_EAPOL, + PACKET_EAPOL_START, + PACKET_MAX +}; + +/*HW_BAND0 - CMAC0 + PHY0 + S0*/ +/*HW_BAND1 - CMAC1 + PHY1 + S1*/ +/*wifi_role->hw_band*/ +enum phl_band_idx { + HW_BAND_0, + HW_BAND_1, + HW_BAND_MAX +}; + +/*wifi_role->hw_port*/ +enum phl_hw_port { + HW_PORT0, + HW_PORT1, + HW_PORT2, + HW_PORT3, + HW_PORT4, + HW_PORT_MAX, +}; + +#define RTW_MAX_TID_NUM 8 +#define RTW_MAX_AC_QUEUE_NUM 4 +enum phl_ac_queue { + PHL_BE_QUEUE_SEL = 0, + PHL_BK_QUEUE_SEL = 1, + PHL_VI_QUEUE_SEL = 2, + PHL_VO_QUEUE_SEL = 3, + PHL_AC_QUEUE_TOTAL +}; + +/** + * struct rtw_chan_def - channel defination + * @chan: the (control/primary) channel + * @center_ch: the center channel + * @bw: channel bandwidth + * @center_freq1: center frequency of first segment + * @center_freq2: center frequency of second segment + * (only with 80+80 MHz) + */ + +struct rtw_chan_def { + enum band_type band; /* protocol -2.4G,5G,6G*/ + enum channel_width bw; + enum chan_offset offset; + u8 chan; /*primary channel*/ + u8 center_ch; + u16 hw_value; + u32 center_freq1; + u32 center_freq2; +}; + +struct chg_opch_param { + struct rtw_wifi_role_t *wrole; + struct rtw_chan_def new_chdef; + struct rtw_chan_def ori_chdef; + enum rtw_phl_status cmd_start_sts; + void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status); +}; + +/** + * struct rtw_chan_ctx - channel context + * @list: + * @chan_ctx_lock: + * @chan_def: + */ +struct rtw_chan_ctx { + _os_list list; + struct rtw_chan_def chan_def; + u8 role_map; /*used role_idx*/ + bool dfs_enabled; +}; + + +#ifdef CONFIG_PCI_HCI +struct rtw_pci_info { + u8 dummy; +}; +#endif + + +#ifdef CONFIG_USB_HCI +struct rtw_usb_info { + enum rtw_usb_speed usb_speed; /* USB 1.1, 2.0 or 3.0 */ + u16 usb_bulkout_size; + u8 outep_num; + u8 inep_num; +}; + +enum phl_usb_rx_agg_mode { + PHL_RX_AGG_DISABLE, + PHL_RX_AGG_DEFAULT, + PHL_RX_AGG_SMALL_PKT, + PHL_RX_AGG_USER_DEFINE, +}; +/* + * refers to _usb.h + * #define SWITCHMODE 0x2 + * #define FORCEUSB3MODE 0x1 + * #define FORCEUSB2MODE 0x0 +*/ +enum rtw_usb_sw_ability { + RTW_USB2_ONLY = 0, + RTW_USB3_ONLY, + RTW_USB_SUPPORT_SWITCH, + RTW_USB_SUPPORT_MAX +}; +#endif + +#ifdef CONFIG_SDIO_HCI +struct rtw_sdio_info { + unsigned int clock; + unsigned int timing; + u8 sd3_bus_mode; + u16 block_sz; + u16 io_align_sz; + u16 tx_align_sz; + bool tx_512_by_byte_mode; /* Send 512 bytes by cmd53 byte or */ + /* block mode. */ +}; +#endif + +enum rtw_rx_status { + RTW_STATUS_RX_OK, + RTW_STATUS_RXDMA_HANG, + RTW_STATUS_RXFIFO_HANG +}; + +struct rtw_ic_info { + enum rtl_ic_id ic_id; + enum rtw_hci_type hci_type; + #ifdef CONFIG_SDIO_HCI + struct rtw_sdio_info sdio_info; + #endif + + #ifdef CONFIG_USB_HCI + struct rtw_usb_info usb_info; + #endif + + #ifdef CONFIG_PCI_HCI + struct rtw_pci_info pci_info; + #endif +}; + +enum rtw_proc_cmd_type { + RTW_PROC_CMD_UNKNOW, + RTW_PROC_CMD_BB, /* 1 */ + RTW_PROC_CMD_RF, /* 2 */ + RTW_PROC_CMD_MAC, /* 3 */ + RTW_PROC_CMD_PHL, /* 4 */ + RTW_PROC_CMD_CORE, /* 5 */ + RTW_PROC_CMD_BTC, /* 6 */ + RTW_PROC_CMD_EFUSE, /* 7 */ + RTW_PROC_CMD_MAX +}; + +enum rtw_arg_type { + RTW_ARG_TYPE_UNKNOW, + RTW_ARG_TYPE_BUF, /* 1 */ + RTW_ARG_TYPE_ARRAY, /* 2 */ + RTW_ARG_TYPE_MAX +}; + +#define MAX_ARGC 20 +#define MAX_ARGV 16 + + +struct rtw_proc_cmd { + enum rtw_arg_type in_type; + u32 in_cnt_len; + union { + char *buf; + char vector[MAX_ARGC][MAX_ARGV]; + }in; +}; + +enum rtw_para_src { + RTW_PARA_SRC_INTNAL, /* 0 */ + RTW_PARA_SRC_EXTNAL, /* 1 */ + RTW_PARA_SRC_CUSTOM, /* 2 */ + RTW_PARA_SRC_MAX +}; + +struct rtw_para_info_t { + enum rtw_para_src para_src; + char para_path[256]; + + u32 para_data_len; + u32 *para_data; +}; + +#define regd_name_max_size 32 + +struct rtw_para_pwrlmt_info_t { + enum rtw_para_src para_src; + char para_path[256]; + + u32 para_data_len; + u32 *para_data; + + char ext_regd_name[regd_name_max_size][10]; + u16 ext_regd_arridx; + u16 ext_reg_map_num; + u8 *ext_reg_codemap; +}; + +#define RTW_PHL_HANDLER_STATUS_INITIALIZED BIT0 +#define RTW_PHL_HANDLER_STATUS_SET BIT1 +#define RTW_PHL_HANDLER_STATUS_RELEASED BIT2 + +#define RTW_PHL_HANDLER_PRIO_HIGH 0 +#define RTW_PHL_HANDLER_PRIO_NORMAL 1 +#define RTW_PHL_HANDLER_PRIO_LOW 2 + +enum rtw_phl_evt { + RTW_PHL_EVT_RX = BIT0, + RTW_PHL_EVT_TX_RECYCLE = BIT1, + + RTW_PHL_EVT_MAX = BIT31 +}; + +enum rtw_phl_config_int { + RTW_PHL_STOP_RX_INT, + RTW_PHL_RESUME_RX_INT, + RTW_PHL_SER_HANDSHAKE_MODE, + RTW_PHL_EN_HCI_INT, + RTW_PHL_DIS_HCI_INT, + RTW_PHL_CLR_HCI_INT, + RTW_PHL_CONFIG_INT_MAX +}; + +/** + * phl_handler - scheduled by core layer or phl itself + * and the properties is assigned by different hanlder type + * @status: handler current status defined by RTW_PHL_HANDLER_STATUS_XXX + * @type: define different properties of handler - tasklet, thread, workitem + * @handle: store different type of handler structure + * @callback: handler callback function + * @context: context used in handler callback function + */ +struct rtw_phl_handler { + char status; + char type; + void *drv_priv; + struct _os_handler os_handler; + void (*callback)(void *context); + void *context; +}; + +struct rtw_xmit_req; +struct rtw_aoac_report; +struct rtw_phl_evt_ops { + enum rtw_phl_status (*rx_process)(void *drv_priv); + enum rtw_phl_status (*tx_recycle)(void *drv_priv, struct rtw_xmit_req *txreq); + enum rtw_phl_status (*tx_test_recycle)(void *phl, struct rtw_xmit_req *txreq); + bool (*set_rf_state)(void *drv_priv, enum rtw_rf_state state_to_set); + void (*wow_handle_sec_info_update)(void *drv_priv, struct rtw_aoac_report *aoac_info, u8 aoac_report_get_ok, u8 phase); + void (*indicate_wake_rsn)(void *drv_priv, u8 rsn); +#ifdef CONFIG_SYNC_INTERRUPT + void (*interrupt_restore)(void *drv_priv, u8 rx); + void (*set_interrupt_caps)(void *drv_priv, u8 en); +#endif /* CONFIG_SYNC_INTERRUPT */ + void (*ap_ps_sta_ps_change)(void *drv_priv, u8 role_id, u8 *sta_mac, + int power_save); + u8 (*issue_null_data)(void *priv, u8 ridx, bool ps); +}; + +/* + * PHL CMD support direct execution, no-wait: synchronization, wait:asynchronization + * PHL_CMD_CMD_DIRECTLY: call PHL API including I/O operation directly + * PHL_CMD_NO_WARIT: send phl cmd msg to cmd dispatcher and do not wait for completion + * PHL_CMD_WAIT: send phl cmd msg to cmd dispatcher and wait for completion + */ +enum phl_cmd_type { + PHL_CMD_DIRECTLY, + PHL_CMD_NO_WAIT, + PHL_CMD_WAIT, + PHL_CMD_MAX, +}; + +enum role_type { + PHL_RTYPE_NONE, + PHL_RTYPE_STATION, + PHL_RTYPE_AP, + PHL_RTYPE_VAP, + PHL_RTYPE_ADHOC, + PHL_RTYPE_ADHOC_MASTER, + PHL_RTYPE_MESH, + PHL_RTYPE_MONITOR, + PHL_RTYPE_P2P_DEVICE, + PHL_RTYPE_P2P_GC, + PHL_RTYPE_P2P_GO, + PHL_RTYPE_TDLS, + PHL_RTYPE_NAN, + PHL_MLME_MAX +}; + +enum role_state { + PHL_ROLE_START, /* 0 - PHL*/ + PHL_ROLE_STOP, /* 1 - PHL*/ + PHL_ROLE_CHG_TYPE, /* 2 - PHL*/ + PHL_ROLE_UPDATE_NOA, /* 3 - PHL*/ + PHL_ROLE_MSTS_STA_CONN_START, /*CORE*/ + PHL_ROLE_MSTS_STA_CONN_END,/*CORE*/ + PHL_ROLE_MSTS_STA_DIS_CONN,/*CORE*/ + PHL_ROLE_MSTS_AP_START,/*CORE*/ + PHL_ROLE_MSTS_AP_STOP,/*CORE*/ + PHL_ROLE_STATE_UNKNOWN, +}; + +enum mlme_state { + MLME_NO_LINK, + MLME_LINKING, + MLME_LINKED +}; +enum wr_chg_id { + WR_CHG_TYPE, + WR_CHG_MADDR, + WR_CHG_AP_PARAM, + WR_CHG_EDCA_PARAM, + WR_CHG_MU_EDCA_PARAM, + WR_CHG_MU_EDCA_CFG, + WR_CHG_BSS_COLOR, + WR_CHG_RTS_TH, + WR_CHG_DFS_HE_TB_CFG, + WR_CHG_TRX_PATH, + WR_CHG_MAX, +}; + +enum wr_status{ + WR_STATUS_PS_ANN = BIT0, + WR_STATUS_BCN_STOP = BIT1, + WR_STATUS_TSF_SYNC = BIT2, + WR_STATUS_MAX = BIT7 +}; + +enum rtw_cfg_type { /* sync with pcfg_type */ + CFG_TBTT_AGG, + CFG_TBTT_SHIFT, + CFG_HIQ_WIN, + CFG_HIQ_DTIM, + CFG_HIQ_MAX, + CFG_BCN_INTERVAL, /* Beacon Interval */ + CFG_BSS_CLR +}; + +struct rtw_ap_param { + u32 cfg_id; + u32 value; +}; + +struct rtw_edca_param { + /* Access Category, 0:BE, 1:BK, 2:VI, 3:VO */ + u8 ac; + /* + * EDCA parameter + * |31...16|15...12|11...8|7...0| + * | TXOP| CWMAX| CWMIN| AIFS| + */ + u32 param; +}; + +struct rtw_mu_edca_param { + u8 ac; + u8 aifsn; + u8 cw; + u8 timer; +}; + +struct rtw_trx_path_param { + enum rf_path tx; + enum rf_path rx; + u8 tx_nss; + u8 rx_nss; +}; + +#define MAX_STORE_BCN_NUM 3 +enum conf_lvl { + CONF_LVL_NONE = 0, + CONF_LVL_LOW, + CONF_LVL_MID, + CONF_LVL_HIGH +}; + +struct rtw_bcn_offset { + u16 offset; /*TU*/ + enum conf_lvl conf_lvl; /*confidence level*/ + u16 cr_tbtt_shift; /* CR current setting */ +}; + +/* + * Store rx bcn tsf info + * @num: the store noumber of "info" array + * @idx: store current index of "info" array + * @info: store array. info[0]: store tsf, info[1]: store mod(TU), info[2]: store hw rx time + * @offset_i: Bcn offset info. Dont't access directionly this variable for application. + You can get offset_i info from phl_get_sta_bcn_offset_info. + */ +struct rtw_rx_bcn_info { + u8 idx; + u8 num; + u64 info[3][MAX_STORE_BCN_NUM]; + struct rtw_bcn_offset offset_i; +}; + +struct rtw_bcn_pkt_info { + struct rtw_phl_stainfo_t *sta; + u64 tsf; + u64 hw_tsf; +}; + +struct rtw_rts_threshold { + u16 rts_time_th; + u16 rts_len_th; +}; + +enum phl_module_id{ + /* 0 ~ 128 PHL background module starts from here*/ + /* 1,2,3 cmd controller section */ + PHL_BK_MDL_START = 0, + PHL_MDL_PHY_MGNT = 1, + PHL_MDL_TX = 2, + PHL_MDL_RX = 3, + + /* above enum is fixed, add new module id from here*/ + /* 10 ~ 40 protocol, wifi role section*/ + PHL_BK_MDL_ROLE_START = 10, + PHL_MDL_MRC = 10, /* Multi-Role Controller intead of STA/P2P role /NAN/AP*/ + PHL_MDL_SOUND = 11, + + PHL_BK_MDL_ROLE_END = 40, + + /* 41 ~ 70 mandatory background module section*/ + PHL_BK_MDL_MDRY_START = 41, + PHL_MDL_POWER_MGNT = 41, + PHL_MDL_SER = 42, + + PHL_BK_MDL_MDRY_END = 70, + + /* 70 ~ 127 optional background module section*/ + PHL_BK_MDL_OPT_START = 71, + PHL_MDL_BTC = 71, + /*PHL_MDL_RSVD = 72,*/ + PHL_MDL_CUSTOM = 73, + PHL_MDL_WOW = 74, + PHL_MDL_PSTS = 75, + PHL_MDL_LED = 76, + PHL_MDL_GENERAL = 77, + PHL_MDL_REGU = 78, + + PHL_BK_MDL_OPT_END = 127, + + /* Fixed BK MDL Max Value*/ + PHL_BK_MDL_END = 128, + + /* 129 ~ 256 PHL foreground module starts from here*/ + PHL_FG_MDL_START = 129, + PHL_FUNC_MDL_TEST_MODULE = 129, + PHL_FG_MDL_SCAN = 130, + PHL_FG_MDL_CONNECT = 131, + PHL_FG_MDL_DISCONNECT = 132, + PHL_FG_MDL_AP_START = 133, + PHL_FG_MDL_AP_STOP = 134, + PHL_FG_MDL_ECSA = 135, + PHL_FG_MDL_END = 254, + + /* Fixed MDL Max Value*/ + PHL_MDL_ID_MAX = 255 +}; + +/* General phl event id shall share this common enum definition + * if definition of private events for a specific module is required, + * please be sure to start its enum from PRIVATE_EVT_START(0x8000) + */ +enum phl_msg_evt_id { + MSG_EVT_NONE = 0, + MSG_EVT_PHY_ON = 1, + MSG_EVT_PHY_IDLE = 2, + MSG_EVT_SCAN_START = 3, + MSG_EVT_SCAN_END = 4, + MSG_EVT_CONNECT_START = 5, + MSG_EVT_CONNECT_LINKED = 6, + MSG_EVT_CONNECT_END = 7, + MSG_EVT_SER_L1 = 8, + MSG_EVT_SER_L2 = 9, + MSG_EVT_FWDL_OK = 10, + MSG_EVT_FWDL_FAIL = 11, + MSG_EVT_HAL_INIT_OK = 12, + MSG_EVT_HAL_INIT_FAIL = 13, + MSG_EVT_MP_CMD_DONE = 14, + /* wow */ + MSG_EVT_WOW_ENTER = 15, + MSG_EVT_WOW_LEAVE = 16, + MSG_EVT_WOW_WAKE_RSN = 17, + MSG_EVT_BCN_RESEND = 18, + MSG_EVT_DUMP_PLE_BUFFER = 19, + MSG_EVT_MP_RX_PHYSTS = 20, + MSG_EVT_ROLE_NTFY = 21, + MSG_EVT_RX_PSTS = 22, + MSG_EVT_SWCH_START = 23, + MSG_EVT_SWCH_DONE = 24, + MSG_EVT_DISCONNECT_PREPARE = 25, + MSG_EVT_DISCONNECT = 26, + MSG_EVT_TSF_SYNC_DONE = 27, + MSG_EVT_TX_RESUME = 28, + MSG_EVT_AP_START_PREPARE =29, + MSG_EVT_AP_START = 30, + MSG_EVT_AP_START_END = 31, + MSG_EVT_AP_STOP_PREPARE = 32, + MSG_EVT_AP_STOP = 33, + MSG_EVT_PCIE_TRX_MIT = 34, + MSG_EVT_BTC_TMR = 35, + MSG_EVT_BTC_FWEVNT = 36, + MSG_EVT_BTC_REQ_BT_SLOT = 37, + MSG_EVT_BTC_PKT_EVT_NTFY = 38, + /* ser*/ + MSG_EVT_SER_L0_RESET = 39, /* L0 notify only */ + MSG_EVT_SER_M1_PAUSE_TRX = 40, + MSG_EVT_SER_IO_TIMER_EXPIRE = 41, + MSG_EVT_SER_FW_TIMER_EXPIRE = 42, + MSG_EVT_SER_M3_DO_RECOV = 43, + MSG_EVT_SER_M5_READY = 44, + MSG_EVT_SER_M9_L2_RESET = 45, + MSG_EVT_SER_EVENT_CHK = 46, + MSG_EVT_SER_POLLING_CHK = 47, + MSG_EVT_ECSA_START = 48, + MSG_EVT_ECSA_UPDATE_FIRST_BCN_DONE = 49, + MSG_EVT_ECSA_COUNT_DOWN = 50, + MSG_EVT_ECSA_SWITCH_START = 51, + MSG_EVT_ECSA_SWITCH_DONE = 52, + MSG_EVT_ECSA_CHECK_TX_RESUME = 53, + MSG_EVT_ECSA_DONE = 54, + MSG_EVT_LISTEN_STATE_EXPIRE = 55, + /* beamform */ + MSG_EVT_SET_VHT_GID = 56, + MSG_EVT_WATCHDOG = 57, + MSG_EVT_DEV_CANNOT_IO = 58, + MSG_EVT_DEV_RESUME_IO = 59, + MSG_EVT_FORCE_USB_SW = 60, + MSG_EVT_GET_USB_SPEED = 61, + MSG_EVT_GET_USB_SW_ABILITY = 62, + MSG_EVT_CFG_AMPDU = 63, + MSG_EVT_DFS_PAUSE_TX = 64, + MSG_EVT_ROLE_RECOVER = 65, + MSG_EVT_ROLE_SUSPEND = 66, + MSG_EVT_HAL_SET_L2_LEAVE = 67, + MSG_EVT_NOTIFY_HAL = 68, + MSG_EVT_ISSUE_BCN = 69, + MSG_EVT_FREE_BCN = 70, + MSG_EVT_STOP_BCN = 71, + MSG_EVT_SEC_KEY = 72, + MSG_EVT_ROLE_START = 73, + MSG_EVT_ROLE_CHANGE = 74, + MSG_EVT_ROLE_STOP = 75, + MSG_EVT_STA_INFO_CTRL = 76, + MSG_EVT_STA_MEDIA_STATUS_UPT = 77, + MSG_EVT_CFG_CHINFO = 78, + MSG_EVT_STA_CHG_STAINFO = 79, + MSG_EVT_HW_TRX_RST_RESUME = 80, + MSG_EVT_HW_TRX_PAUSE = 81, + MSG_EVT_SW_TX_RESUME = 82, + MSG_EVT_SW_RX_RESUME = 83, + MSG_EVT_SW_TX_PAUSE = 84, + MSG_EVT_SW_RX_PAUSE = 85, + MSG_EVT_SW_TX_RESET = 86, + MSG_EVT_SW_RX_RESET = 87, + MSG_EVT_TRX_SW_PAUSE = 88, + MSG_EVT_TRX_SW_RESUME = 89, + MSG_EVT_TRX_PAUSE_W_RST = 90, + MSG_EVT_TRX_RESUME_W_RST = 91, + /* Regulation*/ + MSG_EVT_REGU_SET_DOMAIN = 92, + MSG_EVT_RF_ON = 93, + MSG_EVT_RF_OFF = 94, + MSG_EVT_WPS_PRESSED = 95, + MSG_EVT_WPS_RELEASED = 96, + MSG_EVT_SURPRISE_REMOVE = 97, + MSG_EVT_DATA_PATH_START = 98, + MSG_EVT_DATA_PATH_STOP = 99, + MSG_EVT_TRX_PWR_REQ = 100, + /* tdls */ + MSG_EVT_TDLS_SYNC = 101, + /* beamformee */ + MSG_EVT_SET_BFEE_AID = 102, + /* ccx */ + MSG_EVT_CCX_REPORT_TX_OK = 103, + MSG_EVT_CCX_REPORT_TX_FAIL = 104, + /* ps */ + MSG_EVT_PS_CAP_CHG = 105, + MSG_EVT_PS_PERIOD_CHK = 106, + MSG_EVT_PS_DBG_LPS_ENTER = 107, + MSG_EVT_PS_DBG_LPS_LEAVE = 108, + MSG_EVT_PS_DBG_IPS_ENTER = 109, + MSG_EVT_PS_DBG_IPS_LEAVE = 110, + /* Change operating ch def(ch / bw) */ + MSG_EVT_CHG_OP_CH_DEF_START = 111, + MSG_EVT_CHG_OP_CH_DEF_END = 112, + MSG_EVT_MDL_CHECK_STOP = 113, + MSG_EVT_HW_RF_CHG = 114, + /* dbg */ + MSG_EVT_DBG_SIP_REG_DUMP = 200, + MSG_EVT_DBG_FULL_REG_DUMP = 201, + MSG_EVT_DBG_L2_DIAGNOSE = 202, + MSG_EVT_DBG_RX_DUMP = 203, + MSG_EVT_DBG_TX_DUMP = 204, + /* dbg end */ + /* p2pps */ + MSG_EVT_TSF32_TOG = 205, + /* p2pps end */ + /*Add EVT-ID for linux core cmd temporality*/ + + /* sub module IO */ + MSG_EVT_NOTIFY_BB = 300, + MSG_EVT_NOTIFY_RF = 301, + MSG_EVT_NOTIFY_MAC = 302, + /* sub module IO end*/ + + MSG_EVT_LINUX_CMD_WRK = 888, + MSG_EVT_LINUX_CMD_WRK_TRI_PS = 889, + /* LED */ + MSG_EVT_LED_TICK = 5000, + MSG_EVT_LED_EVT_START = 5001, + MSG_EVT_LED_EVT_END = 5050, + MSG_EVT_MAX = 0x7fff +}; + + + +enum phl_msg_recver_layer { + MSG_RECV_PHL = 0, + MSG_RECV_CORE = 1, + MSG_RECV_MAX +}; + +enum phl_msg_indicator { + MSG_INDC_PRE_PHASE = BIT0, + MSG_INDC_FAIL = BIT1, + MSG_INDC_CANCEL = BIT2, + MSG_INDC_CANNOT_IO = BIT3 +}; + +enum phl_msg_opt { + MSG_OPT_SKIP_NOTIFY_OPT_MDL = BIT0, + MSG_OPT_BLIST_PRESENT = BIT1, + MSG_OPT_CLR_SNDR_MSG_IF_PENDING = BIT2, + MSG_OPT_SEND_IN_ABORT = BIT3, + MSG_OPT_PENDING_DURING_CANNOT_IO = BIT4, +}; + + +/* all module share this common enum definition */ +enum phy_bk_module_opcode { + BK_MODL_OP_NONE = 0, + BK_MODL_OP_CHK_NEW_MSG, + BK_MODL_OP_INPUT_CMD, + BK_MODL_OP_STATE, + BK_MODL_OP_CUS_SET_ROLE_CAP, + BK_MODL_OP_CUS_UPDATE_ROLE_CAP, + BK_MODL_OP_MAX +}; + +/* Foreground cmd token opcode */ +enum phy_fg_cmd_req_opcode { + FG_REQ_OP_NONE = 0, + FG_REQ_OP_GET_ROLE, + FG_REQ_OP_GET_MDL_ID, +#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS + FG_REQ_OP_GET_SCAN_PARAM, + FG_REQ_OP_GET_ISSUE_NULL_OPS, +#endif +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN + FG_REQ_OP_NOTIFY_BCN_RCV, +#endif +#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTION_FRAME_TX + FG_REQ_OP_NOTIFY_ACTION_FRAME_TX, +#endif + FG_REQ_OP_MAX +}; + +/* priority of phl background +module which would be considered when dispatching phl msg*/ +enum phl_bk_module_priority { + PHL_MDL_PRI_ROLE = 0, + PHL_MDL_PRI_OPTIONAL, + PHL_MDL_PRI_MANDATORY, + PHL_MDL_PRI_MAX +}; + +enum phl_data_ctl_cmd { + PHL_DATA_CTL_HW_TRX_RST_RESUME = 1, + PHL_DATA_CTL_HW_TRX_PAUSE = 2, + PHL_DATA_CTL_SW_TX_RESUME = 3, + PHL_DATA_CTL_SW_RX_RESUME = 4, + PHL_DATA_CTL_SW_TX_PAUSE = 5, + PHL_DATA_CTL_SW_RX_PAUSE = 6, + PHL_DATA_CTL_SW_TX_RESET = 7, + PHL_DATA_CTL_SW_RX_RESET = 8, + PHL_DATA_CTL_TRX_SW_PAUSE = 9, + PHL_DATA_CTL_TRX_SW_RESUME = 10, + PHL_DATA_CTL_TRX_PAUSE_W_RST = 11, + PHL_DATA_CTL_TRX_RESUME_W_RST = 12, + PHL_DATA_CTL_MAX = 0xFF +}; + +/** + * phl_msg - define a general msg format for PHL/CORE layer module to handle + * one can easily extend additional mgnt info by encapsulating inside a file + * refer to + * struct phl_msg_ex in phl_msg_hub.c + * struct phl_dispr_msg_ex in phl_cmd_dispatcher.c + * + * @msg_id: indicate msg source & msg type + * BYTE 3: RSVD + * BYTE 2: PHL Module ID, refer to enum phl_module_id + * BYTE 0-1: event id, refer to enum phl_msg_evt_id + * @inbuf: input buffer that sent along with msg + * @inlen: input buffer length + * @outbuf: output buffer that returned after all phl modules have recved msg. + * @outlen: output buffer length + * @band_idx: index of Band(PHY) which associate to this msg + + * @rsvd: feature reserved, passing object pointer. + * For example, + * - cmd_scan : [0]: wifi_role. + * - CANNOT_IO error: [0]: mdl handle. + */ +struct phl_msg{ + u32 msg_id; + enum phl_band_idx band_idx; + u8* inbuf; + u8* outbuf; + u32 inlen; + u32 outlen; + void *rsvd[4]; +}; + +struct msg_notify_map { + u8* id_arr; + u8 len; +}; +struct msg_dispatch_seq { + struct msg_notify_map map[PHL_MDL_PRI_MAX]; +}; +struct msg_self_def_seq { + struct msg_dispatch_seq pre_prot_phase; + struct msg_dispatch_seq post_prot_phase; +}; +struct msg_completion_routine { + void* priv; + void (*completion)(void* priv, struct phl_msg* msg); +}; +/** + * phl_msg_attribute: used in phl_disp_eng_send_msg + * @opt: refers to enum phl_msg_opt. + * @notify: input id array (refer to enum phl_module_id) + * for indicating additional dependency + * @completion: completion routine + */ +struct phl_msg_attribute { + u8 opt; + struct msg_notify_map notify; + struct msg_completion_routine completion; +#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ + void *dispr_attr; +#endif +}; + +/** + * phl_module_op_info - set by core layer or phl itself, + * op code process is an synchronous process. + * which would be handled directly by module handler + * @op_code: refer to enum phy_module_opcode + * @inbuf: input buffer that sent along with msg + * @inlen: input buffer length + * @outbuf: output buffer that returned after all phy modules have recved msg. + * @outlen: output buffer length + */ +struct phl_module_op_info{ + u32 op_code; + u8* inbuf; + u8* outbuf; + u32 inlen; + u32 outlen; +}; + +/** + * phl_cmd_token_req - request foramt for applying token of a specific cmd + * dispatcher. + * cmd token request is regarded as foreground module, thus, + * need to contend for cmd token. + * Normally, these req would be linked to a specific wifi role + * and acquiring RF resource for a specific task. + * + * @module_id: starting from PHL_FG_MDL_START + * @priv: private context from requestor + * @role: designated role info associated with current request. + * ----------------------------------------- + * regarding on "return code" for following ops, refer to enum phl_mdl_ret_code + * ----------------------------------------- + * @acquired: notify requestor when cmd token has acquired for this cmd and + cannot have any I/O operation. + * @abort: notify requestor when cmd has been canceled + after calling rtw_phl_phy_cancel_token_req and + cannot have any I/O operation. + * @msg_hdlr: notify requestor about incoming msg. + * @set_info: notify requestor to handle specific op code. + * @query_info: notify requestor to handle specific op code. + */ + +struct phl_cmd_token_req{ + u8 module_id; + void* priv; + void* role; + enum phl_mdl_ret_code (*acquired)(void* dispr, void* priv); + enum phl_mdl_ret_code (*abort)(void* dispr, void* priv); + enum phl_mdl_ret_code (*msg_hdlr)(void* dispr, void* priv, + struct phl_msg* msg); + enum phl_mdl_ret_code (*set_info)(void* dispr, void* priv, + struct phl_module_op_info* info); + enum phl_mdl_ret_code (*query_info)(void* dispr, void* priv, + struct phl_module_op_info* info); +}; +/** + * phl_module_ops - standard interface for interacting with a cmd dispatcher. + * ----------------------------------------- + * regarding on "return code" for following ops, refer to enum phl_mdl_ret_code + * ----------------------------------------- + * @init: notify module for initialization. + * @deinit: notify module for de-initialization. + * @start: notify module to start. + * @stop: notify module to stop. + * @msg_hdlr: notify module about incoming msg. + * @set_info: notify module to handle specific op code. + * @query_info: notify module to handle specific op code. + */ +struct phl_bk_module_ops { + enum phl_mdl_ret_code (*init)(void* phl_info, void* dispr, void** priv); + void (*deinit)(void* dispr, void* priv); + enum phl_mdl_ret_code (*start)(void* dispr, void* priv); + enum phl_mdl_ret_code (*stop)(void* dispr, void* priv); + enum phl_mdl_ret_code (*msg_hdlr)(void* dispr, void* priv, + struct phl_msg* msg); + enum phl_mdl_ret_code (*set_info)(void* dispr, void* priv, + struct phl_module_op_info* info); + enum phl_mdl_ret_code (*query_info)(void* dispr, void* priv, + struct phl_module_op_info* info); +}; + +/** + * phl_data_ctl_t - datapath control parameters for dispatcher controller + * @cmd: data path control command + * @id: module id which request data path control + */ +struct phl_data_ctl_t { + enum phl_data_ctl_cmd cmd; + enum phl_module_id id; +}; + +#define MSG_MDL_ID_FIELD(_msg_id) (((_msg_id) >> 16) & 0xFF) +#define MSG_EVT_ID_FIELD(_msg_id) ((_msg_id) & 0xFFFF) +#define MSG_INDC_FIELD(_msg_id) (((_msg_id) >> 24) & 0xFF) +#define IS_PRIVATE_MSG(_msg_id) ((_msg_id) & PRIVATE_EVT_START) +#define IS_MSG_FAIL(_msg_id) ((_msg_id) & ( MSG_INDC_FAIL << 24)) +#define IS_MSG_IN_PRE_PHASE(_msg_id) ((_msg_id) & ( MSG_INDC_PRE_PHASE << 24)) +#define IS_MSG_CANCEL(_msg_id) ((_msg_id) & ( MSG_INDC_CANCEL << 24)) +#define IS_MSG_CANNOT_IO(_msg_id) ((_msg_id) & ( MSG_INDC_CANNOT_IO << 24)) +#define SET_MSG_MDL_ID_FIELD(_msg_id, _id) \ + ((_msg_id) = (((_msg_id) & 0xFF00FFFF) | ((u32)(_id) << 16))) +#define SET_MSG_EVT_ID_FIELD(_msg_id, _id) \ + ((_msg_id) = (((_msg_id) & 0xFFFF0000) | (_id))) +#define SET_MSG_INDC_FIELD(_msg_id, _indc) \ + ((_msg_id) = (((_msg_id) & ~((u32)(_indc) << 24))|((u32)(_indc) << 24))) +#define CLEAR_MSG_INDC_FIELD(_msg_id, _indc) ((_msg_id) &= ~((_indc) << 24)) + +#define RTW_MAX_FW_SIZE 0x400000 + +enum rtw_fw_src { + RTW_FW_SRC_INTNAL, /* 0 */ + RTW_FW_SRC_EXTNAL, /* 1 */ + RTW_FW_SRC_MAX +}; + +enum rtw_fw_rsn { + RTW_FW_RSN_INIT, /* 0 */ + RTW_FW_RSN_SPIC, /* 1 */ + RTW_FW_RSN_LPS, /* 2 */ + RTW_FW_RSN_MCC, /* 3 */ + RTW_FW_RSN_WOW, /* 4 */ + RTW_FW_RSN_MAX +}; + +struct rtw_fw_cap_t { + enum rtw_fw_src fw_src; + u32 offload_cap; + u8 dlram_en; + u8 dlrom_en; +}; + +#define INVALID_WIFI_ROLE_IDX MAX_WIFI_ROLE_NUMBER +#define UNSPECIFIED_ROLE_ID 0xFF +#define MAX_SECCAM_NUM_PER_ENTRY 7 + +/* Role hw TX CAP*/ +struct role_cap_t { + enum wlan_mode wmode; + enum channel_width bw; + u8 rty_lmt; /* retry limit for DATA frame, 0xFF: invalid */ + u8 rty_lmt_rts; /* retry limit for RTS frame, 0xFF: invalid */ + + u8 tx_num_ampdu; + u8 tx_amsdu_in_ampdu; /*from SW & HW*/ + u8 tx_ampdu_len_exp; /*from SW & HW*/ + u8 tx_htc; + u8 tx_sgi; + + u8 tx_ht_ldpc:1; + u8 tx_vht_ldpc:1; + u8 tx_he_ldpc:1; + u8 tx_ht_stbc:1; + u8 tx_vht_stbc:1; + u8 tx_he_stbc:1; + + u8 supported_rates[12]; +}; + +struct role_sw_cap_t { + u16 bf_cap; /* use define : HW_CAP_BFER_XX_XX */ + u16 stbc_cap;/* use define: HW_CAP_STBC_XX */ +}; + +/* +Protocol - RX CAP from 80211 PKT, +driver TX related function need to +reference __rx__ of rtw_phl_stainfo_t->asoc_cap +*/ +struct protocol_cap_t { + /* MAC related */ + u16 bcn_interval; /* beacon interval */ + u8 num_ampdu; + u8 ampdu_density:3; /* rx ampdu cap */ + u8 ampdu_len_exp; /* rx ampdu cap */ + u8 amsdu_in_ampdu:1; /* rx ampdu cap */ + u8 max_amsdu_len:2; /* 0: 4k, 1: 8k, 2: 11k */ + u8 htc_rx:1; + u8 sm_ps:2; + u8 trig_padding:2; + u8 twt:6; + u8 all_ack:1; + u8 a_ctrl:4; + u8 ops:1; + u8 ht_vht_trig_rx:1; + u8 bsscolor; + u16 rts_th:10; + + u8 short_slot:1; /* Short Slot Time */ + + u8 preamble:1; /* Preamble, 0: long, 1: short */ + u8 sgi_20:1; /* HT Short GI for 20 MHz */ + u8 sgi_40:1; /* HT Short GI for 40 MHz */ + u8 sgi_80:1; /* VHT Short GI for 80 MHz */ + u8 sgi_160:1; /* VHT Short GI for 160/80+80 MHz */ + struct rtw_edca_param edca[4]; /* Access Category, 0:BE, 1:BK, 2:VI, 3:VO */ + u8 mu_qos_info; + struct rtw_mu_edca_param mu_edca[4]; + + /* BB related */ + u8 ht_ldpc:1; + u8 vht_ldpc:1; + u8 he_ldpc:1; + u8 he_su_bfmr:1; + u8 he_su_bfme:1; + u8 he_mu_bfmr:1; + u8 he_mu_bfme:1; + u8 bfme_sts:3; + u8 num_snd_dim:3; + + u8 ht_su_bfmr:1; + u8 ht_su_bfme:1; + u8 vht_su_bfmr:1; + u8 vht_su_bfme:1; + u8 vht_mu_bfmr:1; + u8 vht_mu_bfme:1; + u8 ht_vht_ng:2; + u8 ht_vht_cb:2; + /* + * supported_rates: Supported data rate of CCK/OFDM. + * The rate definition follow Wi-Fi spec, unit is 500kb/s, + * and the MSB(bit 7) represent basic rate. + * ex. CCK 2Mbps not basic rate is encoded as 0x04, + * and OFDM 6M basic rate is encoded as 0x8c. + * Suppose rates come from Supported Rates and Extended Supported + * Rates IE. + * Value 0 means it is end of array, and no more valid data rate follow. + */ + u8 supported_rates[12]; + u8 ht_rx_mcs[4]; + u8 ht_tx_mcs[4]; + u8 ht_basic_mcs[4]; /* Basic rate of HT */ + u8 vht_rx_mcs[2]; + u8 vht_tx_mcs[2]; + u8 vht_basic_mcs[2]; /* Basic rate of VHT */ + u8 he_rx_mcs[6];/*80,160,80+80*/ + u8 he_tx_mcs[6];/*80,160,80+80*/ + u8 he_basic_mcs[2]; /* Basic rate of HE */ + u8 stbc_ht_rx:2; + u8 stbc_vht_rx:3; + u8 stbc_he_rx:1; + u8 stbc_tx:1; + u8 stbc_ht_tx:1; + u8 stbc_vht_tx:1; + u8 stbc_he_tx:1; + u8 ltf_gi; + u8 doppler_tx:1; + u8 doppler_rx:1; + u8 dcm_max_const_tx:2; + u8 dcm_max_nss_tx:1; + u8 dcm_max_const_rx:2; + u8 dcm_max_nss_rx:1; + u8 partial_bw_su_in_mu:1; + u8 bfme_sts_greater_80mhz:3; + u8 num_snd_dim_greater_80mhz:3; + u8 stbc_tx_greater_80mhz:1; + u8 stbc_rx_greater_80mhz:1; + u8 ng_16_su_fb:1; + u8 ng_16_mu_fb:1; + u8 cb_sz_su_fb:1; + u8 cb_sz_mu_fb:1; + u8 trig_su_bfm_fb:1; + u8 trig_mu_bfm_fb:1; + u8 trig_cqi_fb:1; + u8 partial_bw_su_er:1; + u8 pkt_padding:2; + u8 ppe_thr[8][4]; + u8 pwr_bst_factor:1; + u8 max_nc:3; + u8 dcm_max_ru:2; + u8 long_sigb_symbol:1; + u8 non_trig_cqi_fb:1; + u8 tx_1024q_ru:1; + u8 rx_1024q_ru:1; + u8 fbw_su_using_mu_cmprs_sigb:1; + u8 fbw_su_using_mu_non_cmprs_sigb:1; + u8 er_su:1; + u8 tb_pe:3; + u16 txop_du_rts_th; + u8 he_rx_ndp_4x32:1; + + /* RF related */ + u8 nss_tx:3; + u8 nss_rx:3; + + u8 num_ampdu_bk; +}; + + + +#define LOAD_MAC_REG_FILE BIT0 +#define LOAD_BB_PHY_REG_FILE BIT1 +#define LOAD_BB_PHY_REG_MP_FILE BIT2 +#define LOAD_RF_RADIO_FILE BIT3 +#define LOAD_RF_TXPWR_BY_RATE BIT4 +#define LOAD_RF_TXPWR_TRACK_FILE BIT5 +#define LOAD_RF_TXPWR_LMT_FILE BIT6 +#define LOAD_RF_TXPWR_LMT_RU_FILE BIT7 +#define LOAD_BB_PHY_REG_GAIN_FILE BIT8 + +#define PHL_UNDEFINED_SW_CAP 0xFF + +struct rtw_pcie_ltr_lat_ctrl { + enum rtw_pcie_bus_func_cap_t ctrl; + u32 val; +}; + +enum rtw_pcie_ltr_state { + RTW_PCIE_LTR_SW_ACT = 1, + RTW_PCIE_LTR_SW_IDLE = 2 +}; + +struct bus_sw_cap_t { +#ifdef CONFIG_PCI_HCI + enum rtw_pcie_bus_func_cap_t l0s_ctrl; + enum rtw_pcie_bus_func_cap_t l1_ctrl; + enum rtw_pcie_bus_func_cap_t l1ss_ctrl; + enum rtw_pcie_bus_func_cap_t wake_ctrl; + enum rtw_pcie_bus_func_cap_t crq_ctrl; + u32 txbd_num; + u32 rxbd_num; + u32 rpbd_num; + u32 rxbuf_num; + u32 rpbuf_num; + u8 clkdly_ctrl; + u8 l0sdly_ctrl; + u8 l1dly_ctrl; + struct rtw_pcie_ltr_lat_ctrl ltr_act; + struct rtw_pcie_ltr_lat_ctrl ltr_idle; + u8 ltr_init_state; + u16 ltr_sw_ctrl_thre; /* [15:8] tx [7:0] rx */ + u8 ltr_sw_ctrl; + u8 ltr_hw_ctrl; + u32 ltr_last_trigger_time; + u32 ltr_sw_act_tri_cnt; + u32 ltr_sw_idle_tri_cnt; + u8 ltr_cur_state; +#elif defined (CONFIG_USB_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 tx_h2c_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; + u32 in_token_num; +#elif defined(CONFIG_SDIO_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; +#else + u8 temp_for_struct_empty; /* for undefined interface */ +#endif +}; +struct bus_cap_t { +#ifdef CONFIG_PCI_HCI + enum rtw_pcie_bus_func_cap_t l0s_ctrl; + enum rtw_pcie_bus_func_cap_t l1_ctrl; + enum rtw_pcie_bus_func_cap_t l1ss_ctrl; + enum rtw_pcie_bus_func_cap_t wake_ctrl; + enum rtw_pcie_bus_func_cap_t crq_ctrl; + u32 txbd_num; + u32 rxbd_num; + u32 rpbd_num; + u32 rxbuf_num; + u32 rpbuf_num; + u8 clkdly_ctrl; + u8 l0sdly_ctrl; + u8 l1dly_ctrl; + struct rtw_pcie_ltr_lat_ctrl ltr_act; + struct rtw_pcie_ltr_lat_ctrl ltr_idle; + u8 ltr_init_state; + u8 ltr_sw_ctrl; + u8 ltr_hw_ctrl; +#elif defined (CONFIG_USB_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 tx_h2c_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; + u32 in_token_num; +#elif defined(CONFIG_SDIO_HCI) + u32 tx_buf_size; + u32 tx_buf_num; + u32 tx_mgnt_buf_size; + u32 tx_mgnt_buf_num; + u32 rx_buf_size; + u32 rx_buf_num; +#else + u8 temp_for_struct_empty; /* for undefined interface */ +#endif +}; + +#ifdef CONFIG_PHL_TWT + +#define DELETE_ALL 0xFF +#define IGNORE_CFG_ID 0xFF +#define IGNORE_MACID 0xFF + +enum rtw_phl_twt_sup_cap { + RTW_PHL_TWT_REQ_SUP = BIT(0), /* REQUESTER */ + RTW_PHL_TWT_RSP_SUP = BIT(1)/* RESPONDER */ +}; + +enum rtw_phl_nego_type { + RTW_PHL_INDIV_TWT = 0, /*individual TWT*/ + RTW_PHL_WAKE_TBTT_INR = 1, /*wake TBTT and wake interval*/ + RTW_PHL_BCAST_TWT = 2, /*Broadcast TWT*/ + RTW_PHL_MANAGE_BCAST_TWT = 3 /*Manage memberships in broadcast TWT schedules*/ +}; + +enum rtw_phl_wake_dur_unit{ /*wake duration unit*/ + RTW_PHL_WAKE_256US = 0, + RTW_PHL_WAKE_1TU = 1 +}; + +enum rtw_phl_setup_cmd{ + RTW_PHL_REQUEST_TWT = 0, + RTW_PHL_SUGGEST_TWT = 1, + RTW_PHL_DEMAND_TWT = 2, + RTW_PHL_TWT_GROUPING = 3, + RTW_PHL_ACCEPT_TWT = 4, + RTW_PHL_ALTERNATE_TWT = 5, + RTW_PHL_DICTATE_TWT = 6, + RTW_PHL_REJECT_TWT = 7 +}; + +enum rtw_phl_flow_type{ + RTW_PHL_ANNOUNCED_TWT = 0, + RTW_PHL_UNANNOUNCED_TWT = 1 +}; + +enum rtw_phl_twt_sta_action { + TWT_STA_NONE = 0, + TWT_STA_ADD_MACID = 1, + TWT_STA_DEL_MACID = 2, + TWT_STA_TETMINATW_SP = 3, + TWT_STA_SUSPEND_TWT = 4, + TWT_STA_RESUME_TWT = 5 +}; + +enum rtw_phl_twt_cfg_action { + TWT_CFG_ADD = 0, + TWT_CFG_DELETE = 1, + TWT_CFG_MODIFY = 2 +}; + +struct rtw_phl_twt_flow_type01 { + u8 twt_flow_id; + u8 teardown_all; +}; + +struct rtw_phl_twt_flow_type2 { + u8 reserved; +}; + +struct rtw_phl_twt_flow_type3 { + u8 bcast_twt_id; + u8 teardown_all; +}; + +struct rtw_phl_twt_flow_field{ + enum rtw_phl_nego_type nego_type; + union { + struct rtw_phl_twt_flow_type01 twt_flow01; + struct rtw_phl_twt_flow_type2 twt_flow2; + struct rtw_phl_twt_flow_type3 twt_flow3; + } info; +}; + +/*phl_twt_setup_info Start*/ + +/*Broadcast TWT Parameter Set field*/ +struct rtw_phl_bcast_twt_para_set{ + u8 reserved; /*todo*/ +}; + +/*Individual TWT Parameter Set field*/ +struct rtw_phl_twt_group_asgmt{ + u8 reserved; /*todo*/ +}; + +struct rtw_phl_req_type_indiv{ + enum rtw_phl_setup_cmd twt_setup_cmd; /*twt setup command*/ + enum rtw_phl_flow_type flow_type; + u8 twt_request; + u8 trigger; + u8 implicit; + u8 twt_flow_id; + u8 twt_wake_int_exp;/*twt wake interval exponent*/ + u8 twt_protection; +}; + +struct rtw_phl_indiv_twt_para_set{ + struct rtw_phl_req_type_indiv req_type; + struct rtw_phl_twt_group_asgmt twt_group_asgmt; /* twt group assignment*/ + u32 target_wake_t_h; /* if contain twt_group_assignment then don't contain target_wake_time*/ + u32 target_wake_t_l; + u16 twt_wake_int_mantissa; /*twt wake interval mantissa*/ + u8 nom_min_twt_wake_dur; /*nominal minimum twt wake duration*/ + u8 twt_channel; +}; + +struct rtw_phl_twt_control{ + enum rtw_phl_nego_type nego_type; /*negotiation type*/ + enum rtw_phl_wake_dur_unit wake_dur_unit; /*wake duration unit*/ + u8 ndp_paging_indic; /*ndp paging indicator*/ + u8 responder_pm_mode; + u8 twt_info_frame_disable; /*twt information frame disable*/ +}; +struct rtw_phl_twt_element{ +/* element info*/ + /*control filed*/ + struct rtw_phl_twt_control twt_ctrl; + /*twt para info*/ + union { + struct rtw_phl_indiv_twt_para_set i_twt_para_set; + struct rtw_phl_bcast_twt_para_set b_twt_para_set; + } info; +}; + +struct rtw_phl_twt_setup_info{ + struct rtw_phl_twt_element twt_element; + //struct rtw_phl_stainfo_t *phl_sta; //sta entry + u8 dialog_token; +}; +/*phl_twt_setup_info End*/ + + +/*phl_twt_info Start*/ +struct rtw_twt_sta_info{ + _os_list list; + struct rtw_phl_stainfo_t *phl_sta; /*sta entry*/ + u8 id; /*twt_flow_identifier or broadcast_twt_id*/ +}; + +struct rtw_phl_twt_info{ + enum rtw_phl_wake_dur_unit wake_dur_unit; + enum rtw_phl_nego_type nego_type; + enum rtw_phl_flow_type flow_type; + u8 twt_id; /*config id*/ + u8 bcast_twt_id; /*ignore in individual TWT*/ + u8 twt_action; + u8 responder_pm_mode; + u8 trigger; + u8 implicit_lastbcast; /*implicit or lastbroadcast*/ + u8 twt_protection; + u8 twt_wake_int_exp; + u8 nom_min_twt_wake_dur; + u16 twt_wake_int_mantissa; + u32 target_wake_time_h; + u32 target_wake_time_l; +}; + + +#endif /* CONFIG_PHL_TWT */ + + +enum rtw_lps_listen_bcn_mode { + RTW_LPS_RLBM_MIN = 0, + RTW_LPS_RLBM_MAX = 1, + RTW_LPS_RLBM_USERDEFINE = 2, + RTW_LPS_LISTEN_BCN_MAX, +}; + +enum rtw_lps_smart_ps_mode { + RTW_LPS_LEGACY_PWR1 = 0, + RTW_LPS_TRX_PWR0 = 1, + RTW_LPS_SMART_PS_MAX, +}; + +struct rtw_wow_cap_t { + u8 magic_sup; + u8 pattern_sup; + u8 ping_pattern_wake_sup; + u8 arp_ofld_sup; + u8 ns_oflod_sup; + u8 gtk_ofld_sup; +}; + +/** + * enum phl_ps_leave_fail_act decide the action when leave ps fail + * BIT 0 : reject all subsequent power request + * BIT 1 : trigger L2 reset + */ +enum phl_ps_leave_fail_act { + PS_LEAVE_FAIL_ACT_REJ_PWR = BIT0, + PS_LEAVE_FAIL_ACT_L2 = BIT1 +}; +#define PS_LEAVE_FAIL_ACT_NONE 0 + +enum phl_ps_operation_mode { + PS_OP_MODE_DISABLED = 0, + PS_OP_MODE_FORCE_ENABLED = 1, + PS_OP_MODE_AUTO = 2 +}; + +enum phl_ps_pwr_lvl { + PS_PWR_LVL_PWROFF = 0, /* hal deinit */ + PS_PWR_LVL_PWR_GATED = 1, /* FW control*/ + PS_PWR_LVL_CLK_GATED = 2, /* FW control*/ + PS_PWR_LVL_RF_OFF = 3, /* FW control*/ + PS_PWR_LVL_PWRON = 4, /* hal init */ + PS_PWR_LVL_MAX +}; + +/** + * enum phl_stop_rson record the reason to stop power saving + * BIT 0 : by core initialization setting + * BIT 1 : by debug flow setting + * BIT 2 : by battery change + */ +enum phl_ps_rt_rson { + PS_RT_DEBUG = BIT0, + PS_RT_CORE_INIT = BIT1, + PS_RT_BATTERY_CHG = BIT2, +}; +#define PS_RT_RSON_NONE 0 + +#define PS_CAP_PWRON BIT0 +#define PS_CAP_RF_OFF BIT1 +#define PS_CAP_CLK_GATED BIT2 +#define PS_CAP_PWR_GATED BIT3 +#define PS_CAP_PWR_OFF BIT4 + +/** + * ips_en/lps_en + * refs. structure "phl_ps_operation_mode" + * 0: disable -> disable all ps mechanism + * 1: force enable -> ignore all other condition, force enter ps + * 2: auto -> will be affected by runtime capability set by core + * + * ips_cap/ips_wow_cap/lps_cap/lps_wow_cap are bit defined + * corresponding bit is set if specific power level is supported + * BIT0: Power on + * BIT1: Rf off + * BIT2: Clock gating + * BIT3: Power gating + * BIT4: Power off + */ +struct rtw_ps_cap_t { + /* rf state */ + enum rtw_rf_state init_rf_state; + u8 init_rt_stop_rson; + u8 leave_fail_act; /* action when leave ps fail */ + /* ips */ + u8 ips_en; + u8 ips_cap; + u8 ips_wow_en; + u8 ips_wow_cap; + /* lps */ + u8 lps_en; + u8 lps_cap; + u8 lps_awake_interval; + enum rtw_lps_listen_bcn_mode lps_listen_bcn_mode; + enum rtw_lps_smart_ps_mode lps_smart_ps_mode; + u8 lps_rssi_enter_threshold; + u8 lps_rssi_leave_threshold; + u8 lps_rssi_diff_threshold; + bool lps_pause_tx; + /* wow lps */ + u8 lps_wow_en; + u8 lps_wow_cap; + u8 lps_wow_awake_interval; + enum rtw_lps_listen_bcn_mode lps_wow_listen_bcn_mode; + enum rtw_lps_smart_ps_mode lps_wow_smart_ps_mode; +}; + +struct rtw_edcca_cap_t { + u8 edcca_adap_th_2g; + u8 edcca_adap_th_5g; + + u8 edcca_carrier_sense_th; +}; + +struct phy_sw_cap_t { + struct rtw_para_info_t mac_reg_info; + struct rtw_para_info_t bb_phy_reg_info; + struct rtw_para_info_t bb_phy_reg_mp_info; + struct rtw_para_info_t bb_phy_reg_gain_info; + + struct rtw_para_info_t rf_radio_a_info; + struct rtw_para_info_t rf_radio_b_info; + struct rtw_para_info_t rf_txpwr_byrate_info; + struct rtw_para_info_t rf_txpwrtrack_info; + + struct rtw_para_pwrlmt_info_t rf_txpwrlmt_info; + struct rtw_para_pwrlmt_info_t rf_txpwrlmt_ru_info; + + u8 proto_sup; + u8 band_sup; + u8 bw_sup; + u8 txss; + u8 rxss; + u16 hw_rts_time_th; + u16 hw_rts_len_th; + bool bfreed_para; +}; + +/* final capability of phy */ +struct phy_cap_t { + u8 proto_sup; + u8 band_sup; + u8 bw_sup; + u8 txss; + u8 rxss; + u16 hw_rts_time_th; + u16 hw_rts_len_th; +}; + +/* final capability of device */ +struct dev_cap_t { + u64 hw_sup_flags;/*hw's feature support flags*/ +#ifdef RTW_WKARD_LAMODE + bool la_mode; +#endif + u8 pkg_type; + u8 rfe_type; + u8 bypass_rfe_chk; + u8 xcap; + struct rtw_fw_cap_t fw_cap; +#ifdef CONFIG_MCC_SUPPORT + bool mcc_sup; +#endif +#ifdef CONFIG_DBCC_SUPPORT + bool dbcc_sup; +#endif +#ifdef CONFIG_PHL_TWT + u8 twt_sup; +#endif /* CONFIG_PHL_TWT */ + + struct rtw_wow_cap_t wow_cap; + struct rtw_ps_cap_t ps_cap; + u8 hw_hdr_conv; + u8 domain; + u8 btc_mode; + u8 ap_ps; /* support for AP mode PS in PHL */ + u8 pwrbyrate_off; + u8 pwrlmt_type; + u8 rf_board_opt; + u8 sta_ulru; /* support UL OFDAM for STA mode (reply trigger frame) */ +#ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA + u8 sta_ulru_2g40mhz; /* when "sta_ulru" is enabled, support UL OFDAM on 2.4G 40MHz ? */ +#endif + u8 tx_mu_ru; + struct rtw_edcca_cap_t edcca_cap; +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + bool bfree_para_info; /* keep load file para info buf,default 0*/ +#endif + u8 hw_stype_cap; + u8 wl_func_cap; + u8 rpq_agg_num; /* 0: no adjust, use mac default size: 121 */ +}; + +#ifdef RTW_PHL_BCN //phl def + +#define BCN_ID_MAX (0xFF) +#define MAX_BCN_SIZE 1000 + +enum bcn_offload_flags{ + BCN_HW_SEQ = 0, + BCN_HW_TIM, + + BCN_HW_MAX = 32, +}; + +struct rtw_bcn_info_cmn { + u8 role_idx; + u8 bcn_id; + u8 bcn_added; + + u8 bssid[6]; + u32 bcn_interval; + + u8 bcn_buf[MAX_BCN_SIZE]; + u32 bcn_length; + u32 bcn_rate; + + u32 bcn_dtim; + u32 ie_offset_tim; + + u32 bcn_offload; +}; + +struct rtw_bcn_info_hw { + u8 band; + u8 port; + u8 mbssid; + u8 mac_id; +}; + +struct rtw_bcn_entry { + _os_list list; + struct rtw_bcn_info_cmn *bcn_cmn; //fill by core + struct rtw_bcn_info_hw bcn_hw; //fill by phl //?? void mapping ?? for 8852, 8834 ...blabla +}; +#endif + +struct rtw_phl_com_t; + +struct phl_msg_receiver { + void* priv; + void (*incoming_evt_notify)(void* priv, struct phl_msg *msg); +}; + +#ifdef CONFIG_PHL_P2PPS + +#define MAX_NOA_DESC 5 +#define NOAID_NONE 0xFF + +enum p2pps_trig_tag { + P2PPS_TRIG_GO = 0, + P2PPS_TRIG_GC = 1, + P2PPS_TRIG_GC_255 = 2, + P2PPS_TRIG_MCC = 3, + P2PPS_TRIG_2G_SCC_1AP_1STA_BT = 4, + P2PPS_TRIG_MAX = MAX_NOA_DESC +}; + +struct rtw_phl_noa_desc { + u8 enable; /*false=disable, true=enable*/ + struct rtw_wifi_role_t *w_role; + enum p2pps_trig_tag tag; + u32 start_t_h; + u32 start_t_l; + u32 interval; + u32 duration; + u8 count; + u8 noa_id; /*filed by phl noa module*/ +}; + +struct rtw_phl_opps_desc { + u16 ctw; + u8 all_slep; +}; + +struct rtw_phl_tsf32_tog_rpt{ + u8 band; + u8 port; + u8 valid; + u16 early; + u16 status; + u32 tsf_l; + u32 tsf_h; +}; + +struct rtw_phl_p2pps_ops { + void *priv; /* ops private, define by core layer*/ + void (*tsf32_tog_update_noa)(void *priv, struct rtw_wifi_role_t *w_role, + struct rtw_phl_tsf32_tog_rpt *rpt); + void (*tsf32_tog_update_single_noa)(void *priv, + struct rtw_wifi_role_t *w_role, + struct rtw_phl_noa_desc *desc); +}; + + +#endif + +struct rtw_wifi_role_t { + struct rtw_phl_com_t *phl_com;/*point to phl_com*/ + #ifdef RTW_WKARD_ROLE_TYPE + enum role_type real_type; + #endif /* RTW_WKARD_ROLE_TYPE */ + enum role_type type;/*will mapping to net type*/ + enum role_type target_type; + #ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS + bool is_gc; + #endif + enum mlme_state mstate; + bool active; + enum wr_status status; + u8 id;/* recode role_idx in phl_com */ + u8 hw_wmm; /*HW EDCA - wmm0 or wmm1*/ + #ifdef RTW_WKARD_HW_WMM_ALLOCATE + _os_atomic hw_wmm0_ref_cnt; + #endif + u8 mac_addr[MAC_ALEN]; + u8 hw_band; /*MAC Band0 or Band1*/ + u8 hw_port; /*MAC HW Port*/ + /* + * final protocol capability of role from intersection of + * sw role cap, sw protocol cap and hw protocol cap + */ + struct protocol_cap_t proto_role_cap; + + /* + * final capability of role from intersection of + * sw role cap, final phy cap and final dev cap + */ + struct role_cap_t cap; + + /*#ifdef CONFIG_AP*/ +#ifdef RTW_PHL_BCN + struct rtw_bcn_info_cmn bcn_cmn; //todo: ieee mbssid case & multi-bcn (in one iface) case + u8 hw_mbssid; +#endif + u8 dtim_period; + u8 mbid_num; + u32 hiq_win; + /*#endif CONFIG_AP*/ + + struct rtw_chan_def chandef; + struct rtw_chan_ctx *chanctx;/*point to chanctx*/ + + struct phl_queue assoc_sta_queue; + +#ifdef CONFIG_PHL_TWT + struct rtw_phl_twt_setup_info twt_setup_info; +#endif /* CONFIG_PHL_TWT */ + +#ifdef CONFIG_PHL_P2PPS + struct rtw_phl_noa_desc noa_desc[MAX_NOA_DESC]; +#endif + + void *core_data; /* Track back to counter part in core layer */ +#ifdef RTW_WKARD_BFEE_SET_AID + u16 last_set_aid; +#endif +}; + +#define TXTP_CALC_DIFF_MS 1000 +#define RXTP_CALC_DIFF_MS 1000 + +#define TX_ULTRA_LOW_TP_THRES_KBPS 100 +#define RX_ULTRA_LOW_TP_THRES_KBPS 100 +#define TX_LOW_TP_THRES_MBPS 2 +#define RX_LOW_TP_THRES_MBPS 2 +#define TX_MID_TP_THRES_MBPS 10 +#define RX_MID_TP_THRES_MBPS 10 +#define TX_HIGH_TP_THRES_MBPS 50 +#define RX_HIGH_TP_THRES_MBPS 50 + + +enum rtw_tfc_lvl { + RTW_TFC_IDLE = 0, + RTW_TFC_ULTRA_LOW = 1, + RTW_TFC_LOW = 2, + RTW_TFC_MID = 3, + RTW_TFC_HIGH = 4, + RTW_TFC_LVL_MAX = 0xFF +}; + +enum rtw_tfc_sts { + TRAFFIC_CHANGED = BIT0, + TRAFFIC_INCREASE = BIT1, + TRAFFIC_DECREASE = BIT2, + TRAFFIC_STS_MAX = BIT7 +}; + +struct rtw_traffic_t { + enum rtw_tfc_lvl lvl; + enum rtw_tfc_sts sts; +}; + +struct rtw_stats_tp { + u64 last_calc_bits; + u32 last_calc_time_ms; +}; +/*statistic*/ +struct rtw_stats { + u64 tx_byte_uni;/*unicast tx byte*/ + u64 rx_byte_uni;/*unicast rx byte*/ + u64 tx_byte_total; + u64 rx_byte_total; + u32 tx_tp_kbits; + u32 rx_tp_kbits; + u16 tx_moving_average_tp; /* tx average MBps*/ + u16 rx_moving_average_tp; /* rx average MBps*/ + u32 last_tx_time_ms; + u32 last_rx_time_ms; + u32 txreq_num; + u32 rx_rate; + u32 rx_rate_nmr[RTW_DATA_RATE_HE_NSS4_MCS11 +1]; + u64 ser_event[8]; /* RTW_PHL_SER_MAX */ + struct rtw_stats_tp txtp; + struct rtw_stats_tp rxtp; + struct rtw_traffic_t tx_traffic; + struct rtw_traffic_t rx_traffic; + u32 rx_tf_cnt; /* rx trigger frame number (accumulated, only reset in disconnect) */ +}; +enum sta_chg_id { + STA_CHG_BW, + STA_CHG_NSS, + STA_CHG_RAMASK, + STA_CHG_SEC_MODE, + STA_CHG_MBSSID, + STA_CHG_RA_GILTF, + STA_CHG_MAX +}; + +enum phl_upd_mode { + PHL_UPD_ROLE_CREATE, + PHL_UPD_ROLE_REMOVE, + PHL_UPD_ROLE_TYPE_CHANGE, + PHL_UPD_ROLE_INFO_CHANGE, + PHL_UPD_STA_INFO_CHANGE, + PHL_UPD_STA_CON_DISCONN, + PHL_UPD_ROLE_MAX +}; + +#ifdef CONFIG_PHL_TXSC +#define PHL_TXSC_ENTRY_NUM 8 +#define MAX_WD_SIZE 128 + +struct phl_txsc_entry { + bool txsc_wd_cached; + u8 txsc_wd_cache[MAX_WD_SIZE]; + u8 txsc_wd_len; + u32 txsc_cache_hit; +}; +#endif + +struct rtw_hal_stainfo_t; +struct rtw_phl_stainfo_t { + _os_list list; + struct rtw_wifi_role_t *wrole; + bool active; + u16 aid; + u16 macid; + u8 mac_addr[MAC_ALEN]; + + struct rtw_chan_def chandef; + struct rtw_stats stats; + enum wlan_mode wmode; + + /*mlme protocol or MAC related CAP*/ + u8 bcn_hit_cond; + u8 hit_rule; + u8 tf_trs; + u8 tgt_ind; + u8 frm_tgt_ind; + u8 addr_sel; + u8 addr_msk; + + /* rx agg */ + struct phl_tid_ampdu_rx *tid_rx[8]; /* TID_MAX_NUM */ + _os_lock tid_rx_lock; /* guarding @tid_rx */ + _os_event comp_sync; /* reorder timer completion event */ + _os_timer reorder_timer; /* reorder timer for all @tid_rx of the + * stainfo */ + /* TODO: add missing part */ + + /*mlme protocol or PHY related CAP*/ + struct protocol_cap_t asoc_cap; + enum rtw_protect_mode protect; + + /*security related*/ + u8 wapi; + u8 sec_mode; + + /* + * STA powersave, those could be implemented as bit flags but there's no + * corresponding atomic bit operations available on Windows. + */ + _os_atomic ps_sta; /* the sta is in PS mode or not */ + + struct rtw_hal_stainfo_t *hal_sta; + +#ifdef CONFIG_PHL_TXSC + struct phl_txsc_entry phl_txsc[PHL_TXSC_ENTRY_NUM]; +#endif + struct rtw_rx_bcn_info bcn_i; + void *core_data; /* Track back to counter part in core layer */ +}; + + + + +#define WL_FUNC_P2P BIT0 +#define WL_FUNC_MIRACAST BIT1 +#define WL_FUNC_TDLS BIT2 +#define WL_FUNC_FTM BIT3 +#define WL_FUNC_BIT_NUM 4 + + +/* HW MAC capability*/ +#define HW_SUP_DBCC BIT0 +#define HW_SUP_AMSDU BIT1 +#define HW_SUP_TCP_TX_CHKSUM BIT2 +#define HW_SUP_TCP_RX_CHKSUM BIT3 +#define HW_SUP_TXPKT_CONVR BIT4 +#define HW_SUP_RXPKT_CONVR BIT5 +#define HW_SUP_MULTI_BSSID BIT6 +#define HW_SUP_OFDMA BIT7 +#define HW_SUP_CHAN_INFO BIT8 +#define HW_SUP_TSSI BIT9 +#define HW_SUP_TANK_K BIT10 + +/*BUS Section CAP */ +#define HW_SUP_PCIE_PLFH BIT20 /*payload from host*/ +#define HW_SUP_USB_MULTI_FUN BIT21 +#define HW_SUP_SDIO_MULTI_FUN BIT22 + +/* Beamform CAP */ +#define HW_CAP_BF_NON_SUPPORT 0 +#define HW_CAP_BFEE_HT_SU BIT(0) +#define HW_CAP_BFER_HT_SU BIT(1) +#define HW_CAP_BFEE_VHT_SU BIT(2) +#define HW_CAP_BFER_VHT_SU BIT(3) +#define HW_CAP_BFEE_VHT_MU BIT(4) +#define HW_CAP_BFER_VHT_MU BIT(5) +#define HW_CAP_BFEE_HE_SU BIT(6) +#define HW_CAP_BFER_HE_SU BIT(7) +#define HW_CAP_BFEE_HE_MU BIT(8) +#define HW_CAP_BFER_HE_MU BIT(9) +#define HW_CAP_HE_NON_TB_CQI BIT(10) +#define HW_CAP_HE_TB_CQI BIT(11) + +#define RTW_HW_CAP_ULRU_AUTO 0 +#define RTW_HW_CAP_ULRU_DISABLE 1 +#define RTW_HW_CAP_ULRU_ENABLE 2 + +/* STBC CAP */ +#define HW_CAP_STBC_HT_TX BIT(0) +#define HW_CAP_STBC_VHT_TX BIT(1) +#define HW_CAP_STBC_HE_TX BIT(2) +#define HW_CAP_STBC_HE_TX_GT_80M BIT(3) +#define HW_CAP_STBC_HT_RX BIT(4) +#define HW_CAP_STBC_VHT_RX BIT(5) +#define HW_CAP_STBC_HE_RX BIT(6) +#define HW_CAP_STBC_HE_RX_GT_80M BIT(7) + +struct hal_spec_t { + char *ic_name; + u16 macid_num; + + u8 sec_cam_ent_num; + u8 sec_cap; + u8 wow_cap; + + u8 rfpath_num_2g:4; /* used for tx power index path */ + u8 rfpath_num_5g:4; /* used for tx power index path */ + u8 rf_reg_path_num; + u8 max_tx_cnt; + + u8 tx_nss_num:4; + u8 rx_nss_num:4; + + u8 band_cap; /* value of BAND_CAP_XXX */ + u8 bw_cap; /* value of BW_CAP_XXX */ + u8 port_num; + u8 wmm_num; + u8 proto_cap; /* value of PROTO_CAP_XXX */ + u8 wl_func; /* value of WL_FUNC_XXX */ + + /********* xmit ************/ + + + /********* recv ************/ + u8 rx_bd_info_sz; + + u16 rx_tag[2]; + #ifdef CONFIG_USB_HCI + u8 max_bulkin_num; + u8 max_bulkout_num; + #endif + #ifdef CONFIG_PCI_HCI + u16 txbd_multi_tag; + u8 txbd_upd_lmt; + #ifdef RTW_WKARD_BUSCAP_IN_HALSPEC + u8 phyaddr_num; + #endif + #endif + u8 cts2_thres_en; + u16 cts2_thres; + /********* beamformer ************/ + u8 max_csi_buf_su_nr; + u8 max_csi_buf_mu_nr; + u8 max_bf_ent_nr; + u8 max_su_sta_nr; + u8 max_mu_sta_nr; + +}; + +#define phl_get_hci_type(_phlcom) (_phlcom->hci_type) +#define phl_get_ic_spec(_phlcom) (&_phlcom->hal_spec) +#define phl_get_fw_buf(_phlcom) (_phlcom->fw_info.ram_buff) +#define phl_get_fw_size(_phlcom) (_phlcom->fw_info.ram_size) + +enum rtw_drv_mode { + RTW_DRV_MODE_NORMAL = 0, + RTW_DRV_MODE_EQC = 1, + RTW_DRV_MODE_HIGH_THERMAL = 2, + + /* 11~20 for MP submodule section*/ + RTW_DRV_MODE_MP_SMDL_START = 11, + RTW_DRV_MODE_MP = 11, + RTW_DRV_MODE_HOMOLOGATION = 12, + RTW_DRV_MODE_MP_SMDL_END = 20, + + /* 21~30 for FPGA submodule section*/ + RTW_DRV_MODE_FPGA_SMDL_START = 21, + RTW_DRV_MODE_FPGA_SMDL_END = 30, + + /* 31~60 for VERIFY submodule section*/ + RTW_DRV_MODE_VERIFY_SMDL_START = 31, + RTW_DRV_MODE_VERIFY_SMDL_END = 60, + + /* 61~80 for TOOL submodule section*/ + RTW_DRV_MODE_TOOL_SMDL_START = 61, + RTW_DRV_MODE_TOOL_SMDL_END = 80, + + /* Fixed Max Value*/ + RTW_DRV_MODE_MAX = 255 +}; + +struct rtw_evt_info_t { + _os_lock evt_lock; + enum rtw_phl_evt evt_bitmap; +}; + +// WiFi FW +struct rtw_fw_info_t { + u8 fw_en; + u8 fw_src; + u8 fw_type; + u8 dlram_en; + u8 dlrom_en; + u8 *rom_buff; + u32 rom_addr; + u32 rom_size; + char rom_path[256]; + u8 *ram_buff; + u32 ram_size; + char ram_path[256]; + u8 *buf; + u32 buf_size; + u8 *wow_buf; + u32 wow_buf_size; + u8 *sym_buf; + u32 sym_buf_size; +}; + +enum rtw_fw_status { + RTW_FW_STATUS_OK, + RTW_FW_STATUS_NOFW, + RTW_FW_STATUS_ASSERT, + RTW_FW_STATUS_EXCEP, + RTW_FW_STATUS_RXI300, + RTW_FW_STATUS_HANG +}; + +#ifdef CONFIG_PHL_DFS +enum dfs_regd_t { + DFS_REGD_UNKNOWN = 0, + DFS_REGD_FCC = 1, + DFS_REGD_JAP = 2, + DFS_REGD_ETSI = 3, +}; +struct rtw_dfs_t { + u8 region_domain; + bool dfs_enabled; +}; +#endif + +#ifdef CONFIG_PHL_CHANNEL_INFO + +#define CHAN_INFO_MAX_SIZE 65535 +#define MAX_CHAN_INFO_PKT_KEEP 2 +#define CHAN_INFO_PKT_TOTAL MAX_CHAN_INFO_PKT_KEEP + 1 + +struct csi_header_t { + u8 mac_addr[6]; /* mdata: u8 ta[6]? */ + u32 hw_assigned_timestamp; /* mdata: u32 freerun_cnt */ + u8 channel; /* Drv define */ + u8 bandwidth; /* mdata: u8 bw */ + u16 rx_data_rate; /* mdata: u16 rx_rate */ + u8 nc; /* ch_rpt_hdr_info */ + u8 nr; /* ch_rpt_hdr_info */ + u16 num_sub_carrier; /* Drv define*/ + u8 num_bit_per_tone; /* Drv define per I/Q */ + u8 avg_idle_noise_pwr; /* ch_rpt_hdr_info */ + u8 evm[2]; /* ch_rpt_hdr_info */ + u8 rssi[2]; /* phy_info_rpt */ + u32 csi_data_length; /* ch_rpt_hdr_info */ + u8 rxsc; /* phy_info_rpt */ + u8 ch_matrix_report; /* mdata: u8 get_ch_info */ + u8 csi_valid; /* ch_rpt_hdr_info */ +}; + +struct chan_info_t { + _os_list list; + u8* chan_info_buffer; + u32 length; + struct csi_header_t csi_header; +}; + +struct rx_chan_info_pool { + struct chan_info_t channl_info_pkt[CHAN_INFO_PKT_TOTAL]; + _os_list idle; + _os_list busy; + _os_lock idle_lock; /* spinlock */ + _os_lock busy_lock; /* spinlock */ + u32 idle_cnt; + u32 busy_cnt; +}; + +#endif /* CONFIG_PHL_CHANNEL_INFO */ + +#ifdef CONFIG_MCC_SUPPORT +#define BT_SEG_NUM 2 +#define SLOT_NUM 4 +#define MIN_TDMRA_SLOT_NUM 2 +#define NONSPECIFIC_SETTING 0xff + +/*Export to core layer. Phl get the judgement of slot mode*/ +enum rtw_phl_mcc_coex_mode { + RTW_PHL_MCC_COEX_MODE_NONE = 0, + RTW_PHL_MCC_COEX_MODE_BT_MASTER, + RTW_PHL_MCC_COEX_MODE_WIFI_MASTER, + RTW_PHL_MCC_COEX_MODE_BT_WIFI_BALANCE +}; + +enum rtw_phl_tdmra_wmode { + RTW_PHL_TDMRA_WMODE_NONE = 0, + RTW_PHL_TDMRA_AP_CLIENT_WMODE, + RTW_PHL_TDMRA_2CLIENTS_WMODE, + RTW_PHL_TDMRA_AP_WMODE, + RTW_PHL_TDMRA_UNKNOWN_WMODE +}; + +enum rtw_phl_mcc_dbg_type { + MCC_DBG_NONE = 0, + MCC_DBG_STATE, + MCC_DBG_OP_MODE, + MCC_DBG_COEX_MODE, + MCC_DBG_BT_INFO, + MCC_DBG_EN_INFO +}; + +enum rtw_phl_mcc_state { + MCC_NONE = 0, + MCC_CFG_EN_INFO, + MCC_TRIGGER_FW_EN, + MCC_FW_EN_FAIL, + MCC_RUNING, + MCC_TRIGGER_FW_DIS, + MCC_FW_DIS_FAIL, + MCC_STOP +}; + +enum rtw_phl_mcc_dur_lim_tag { + RTW_MCC_DUR_LIM_NONE = 0, + RTW_MCC_DUR_LIM_NOA +}; + +/*Export to core layer and hal layyer. Phl get the c2h report mode and config to halmac*/ +enum rtw_phl_mcc_rpt { + RTW_MCC_RPT_OFF = 0, + RTW_MCC_RPT_FAIL_ONLY, + RTW_MCC_RPT_ALL +}; + +/*Export to core layer. Phl get switch ch setting of role from core layer*/ +struct rtw_phl_mcc_setting_info { + struct rtw_wifi_role_t *wrole; + u8 role_map;/*the wifi role map in operating mcc */ + u8 tx_null_early; + u16 dur; /*core specific duration in a period of 100 ms */ + bool en_fw_mcc_log; + u8 fw_mcc_log_lv;/* fw mcc log level */ +}; + +/*Export to core layer. Core get NOA info to update p2p beacon*/ +struct rtw_phl_mcc_noa { + struct rtw_wifi_role_t *wrole; + u32 start_t_h; + u32 start_t_l; + u16 dur; + u16 interval; + u8 cnt; +}; + +struct rtw_phl_mcc_ops { + void *priv; /* ops private, define by core layer*/ + int (*mcc_update_noa)(void *priv, struct rtw_phl_mcc_noa *param); + int (*mcc_get_setting)(void *priv, struct rtw_phl_mcc_setting_info *param); +}; + +/* + * Export to phl layer and hal layer. + * Record the debug info. +*/ +struct rtw_phl_mcc_dbg_slot_info { + bool bt_role; + u16 dur; + u16 ch; + u16 macid; +}; + +struct rtw_phl_mcc_dbg_hal_info { + u8 slot_num; + struct rtw_phl_mcc_dbg_slot_info dbg_slot_i[SLOT_NUM]; + bool btc_in_group; +}; + +struct rtw_phl_mcc_macid_bitmap { + u32 *bitmap; + u8 len; +}; + +struct rtw_phl_mcc_sync_tsf_info { + u8 sync_en; + u16 source; + u16 target; + u16 offset; +}; + +struct rtw_phl_mcc_dur_lim_info { + bool enable; + enum rtw_phl_mcc_dur_lim_tag tag; + u16 max_tob; + u16 max_toa; + u16 max_dur; +}; + +struct rtw_phl_mcc_dur_info { + u16 dur; + struct rtw_phl_mcc_dur_lim_info dur_limit; +}; + +struct rtw_phl_mcc_policy_info { + u8 c2h_rpt; + u8 tx_null_early; + u8 dis_tx_null; + u8 in_curr_ch; + u8 dis_sw_retry; + u8 sw_retry_count; + struct rtw_phl_mcc_dur_info dur_info; + u8 rfk_chk; + u8 protect_bcn; + u8 courtesy_en; + u8 courtesy_num; + u8 courtesy_target; +}; + +struct rtw_phl_mcc_role { + struct rtw_wifi_role_t *wrole; + struct rtw_phl_mcc_macid_bitmap used_macid; + struct rtw_chan_def *chandef; + struct rtw_phl_mcc_policy_info policy; + u16 macid; + u16 bcn_intvl; + bool bt_role; + u8 group; +}; + +/* + * @c_en: Enable courtesy function + * @c_num: the time slot of src_role replace by tgt_role + */ +struct rtw_phl_mcc_courtesy { + bool c_en; + bool c_num; + struct rtw_phl_mcc_role *src_role; + struct rtw_phl_mcc_role *tgt_role; +}; + +/* + * @slot: duration, unit: TU + * @bt_role: True: bt role, False: Wifi role + * @mrole: mcc role info for Wifi Role + */ +struct rtw_phl_mcc_slot_info { + u16 slot; + bool bt_role; + struct rtw_phl_mcc_role *mrole; +}; + +/* + * @slot_num: total slot num(Wifi+BT) + * @bt_slot_num: total BT slot num + * | Dur1 | Dur2 | + * bcn bcn + * |tob_r | toa_r|tob_a | toa_a| + */ +struct rtw_phl_mcc_pattern { + u8 slot_num; + u8 bt_slot_num; + struct rtw_phl_mcc_role *role_ref; + struct rtw_phl_mcc_role *role_ano; + s16 tob_r; + s16 toa_r; + s16 tob_a; + s16 toa_a; + u16 bcns_offset; + + u16 calc_fail; + /** + * |tob_r|toa_r| + * ---------------------- + * |tob_a|toa_a| + **/ + u16 d_r_d_a_spacing_max; + struct rtw_phl_mcc_courtesy courtesy_i; + /*record slot order for X wifi slot + Y bt slot*/ + struct rtw_phl_mcc_slot_info slot_order[SLOT_NUM]; +}; + +/* + * Enable info for mcc + * @ref_role_idx: the index of reference role + * @mrole_map: use mcc role num + * @mrole_num: use mcc role num + * @group: assigned by halmac mcc, the group resource of fw feture, phl layer ignore it + * fw mcc can handle differenec slot pattern, and the group is the id of slot pattern. + * @tsf_high, tsf_low: Start TSF + * @tsf_high_l, tsf_low_l: Limitation of Start TSF + * @dbg_hal_i: Debug info for hal mcc + */ +struct rtw_phl_mcc_en_info { + struct rtw_phl_mcc_role mcc_role[MCC_ROLE_NUM]; + struct rtw_phl_mcc_sync_tsf_info sync_tsf_info; + struct rtw_phl_mcc_pattern m_pattern; + u8 ref_role_idx; + u8 mrole_map; + u8 mrole_num; + u8 group; + u16 mcc_intvl; + u32 tsf_high; + u32 tsf_low; + u32 tsf_high_l; + u32 tsf_low_l; + struct rtw_phl_mcc_dbg_hal_info dbg_hal_i; +}; + +/* + * Bt info + * @bt_dur: bt slot + * @bt_seg: segment bt slot + * @bt_seg_num: segment num + * @add_bt_role: if add_bt_role = true, we need to add bt slot to fw + */ +struct rtw_phl_mcc_bt_info { + u16 bt_dur; + u16 bt_seg[BT_SEG_NUM]; + u8 bt_seg_num; + bool add_bt_role; +}; + +enum rtw_phl_mcc_chk_inprocess_type { + RTW_PHL_MCC_CHK_INPROGRESS = 0, + RTW_PHL_MCC_CHK_INPROGRESS_SINGLE_CH, + RTW_PHL_MCC_CHK_INPROGRESS_MULTI_CH, + RTW_PHL_MCC_CHK_MAX, +}; + +enum mr_coex_trigger { + MR_COEX_TRIG_BY_BT, + MR_COEX_TRIG_BY_LINKING, + MR_COEX_TRIG_BY_DIS_LINKING, + MR_COEX_TRIG_BY_CHG_SLOT, + MR_COEX_TRIG_BY_SCAN, + MR_COEX_TRIG_BY_ECSA, + MR_COEX_TRIG_BY_CHG_OP_CHDEF, + MR_COEX_TRIG_MAX, +}; + +#endif /* CONFIG_MCC_SUPPORT */ + +/*multi-roles control components*/ +enum mr_op_mode { + MR_OP_NON, + MR_OP_SCC, + MR_OP_MCC, + MR_OP_MAX, +}; + +enum mr_op_type { + MR_OP_TYPE_NONE, + MR_OP_TYPE_STATION_ONLY, + MR_OP_TYPE_AP_ONLY, + MR_OP_TYPE_STATION_AP, + MR_OP_TYPE_MAX, +}; + +struct mr_info { + u8 sta_num; + u8 ld_sta_num; + u8 lg_sta_num; /* WIFI_STATION_STATE && WIFI_UNDER_LINKING */ + + u8 ap_num; + u8 ld_ap_num; /*&& asoc_sta_count > 2*/ + u8 monitor_num; + + u8 p2p_device_num; + u8 p2p_gc_num; + u8 p2p_go_num; + +#ifdef CONFIG_PHL_TDLS + u8 ld_tdls_num; /* phl_role->type == PHL_RTYPE_TDLS */ +#endif + +#if 0 +#ifdef CONFIG_AP_MODE + u8 starting_ap_num; /*WIFI_FW_AP_STATE*/ +#endif + u8 adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE */ + u8 ld_adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE && asoc_sta_count > 2 */ +#ifdef CONFIG_RTW_MESH + u8 mesh_num; /* WIFI_MESH_STATE && WIFI_ASOC_STATE */ + u8 ld_mesh_num; /* WIFI_MESH_STATE && WIFI_ASOC_STATE && asoc_sta_count > 2 */ +#endif +#endif +}; + +enum mr_coex_mode { + MR_COEX_MODE_NONE = 0, + MR_COEX_MODE_2GSCC_1AP_1STA_BTC = 1, + MR_COEX_MODE_TDMRA = 2 +}; + +/*export to core layer*/ +struct mr_query_info { + struct mr_info cur_info; + enum mr_op_mode op_mode; + enum mr_op_type op_type; +}; + +struct hw_band_ctl_t { + _os_lock lock; + u8 id; + u8 port_map; /*used port_idx*/ + u8 role_map; /*used role_idx*/ + u8 wmm_map; + struct mr_info cur_info; + enum mr_op_mode op_mode; + enum mr_op_type op_type; + enum phl_hw_port tsf_sync_port; + struct phl_queue chan_ctx_queue;/*struct rtw_chan_ctx*/ + enum mr_coex_mode coex_mode; +#ifdef CONFIG_MCC_SUPPORT + void *mcc_info; /*struct phl_mcc_info*/ +#endif +}; + +#define MAX_BAND_NUM 2 +struct rtw_hal_com_t; + +#ifdef CONFIG_PHL_P2PPS +struct rtw_phl_noa { + struct rtw_wifi_role_t *wrole; + enum p2pps_trig_tag tag; + u32 start_t_h; + u32 start_t_l; + u16 dur; + u8 cnt; + u16 interval; +}; +#endif + +struct rtw_phl_mr_ops { + void *priv; /* ops private, define by core layer*/ +#ifdef CONFIG_PHL_P2PPS + int (*phl_mr_update_noa)(void *priv, struct rtw_phl_noa *param); +#endif +#ifdef CONFIG_MCC_SUPPORT + struct rtw_phl_mcc_ops *mcc_ops; +#endif +}; + +struct mr_ctl_t { + struct rtw_hal_com_t *hal_com; + _os_lock lock; + struct hw_band_ctl_t band_ctrl[MAX_BAND_NUM]; + struct phl_bk_module_ops bk_ops; + u8 role_map; + bool is_sb; + struct rtw_phl_mr_ops mr_ops; +#ifdef CONFIG_MCC_SUPPORT + u8 init_mcc; + void *com_mcc;/*struct phl_com_mcc_info*/ +#endif +}; + +enum rtw_rssi_type { + RTW_RSSI_DATA_ACAM, + RTW_RSSI_DATA_ACAM_A1M, + RTW_RSSI_DATA_OTHER, + RTW_RSSI_CTRL_ACAM, + RTW_RSSI_CTRL_ACAM_A1M, + RTW_RSSI_CTRL_OTHER, + RTW_RSSI_MGNT_ACAM, + RTW_RSSI_MGNT_ACAM_A1M, + RTW_RSSI_MGNT_OTHER, + RTW_RSSI_UNKNOWN, + RTW_RSSI_TYPE_MAX +}; + +#define PHL_MAX_RSSI 110 +#define PHL_RSSI_MAVG_NUM 16 +#define UPDATE_MA_RSSI(_RSSI, _TYPE, _VAL) \ + do { \ + u8 oldest_rssi = 0; \ + if(_RSSI->ma_rssi_ele_idx[_TYPE] < PHL_RSSI_MAVG_NUM) { \ + oldest_rssi = _RSSI->ma_rssi_ele[_TYPE][\ + _RSSI->ma_rssi_ele_idx[_TYPE]]; \ + _RSSI->ma_rssi_ele[_TYPE][_RSSI->ma_rssi_ele_idx[_TYPE]] = \ + ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ + } else { \ + _RSSI->ma_rssi_ele_idx[_TYPE] = 0; \ + oldest_rssi = _RSSI->ma_rssi_ele[_TYPE][0]; \ + _RSSI->ma_rssi_ele[_TYPE][0] = \ + ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ + } \ + _RSSI->ma_rssi_ele_sum[_TYPE] -= oldest_rssi;\ + _RSSI->ma_rssi_ele_sum[_TYPE] += \ + ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ + _RSSI->ma_rssi_ele_idx[_TYPE]++; \ + if(_RSSI->ma_rssi_ele_cnt[_TYPE] < PHL_RSSI_MAVG_NUM) \ + _RSSI->ma_rssi_ele_cnt[_TYPE]++; \ + _RSSI->ma_rssi[_TYPE] = (u8)(_RSSI->ma_rssi_ele_sum[_TYPE] / \ + _RSSI->ma_rssi_ele_cnt[_TYPE]);\ + } while (0) + +#define PHL_TRANS_2_RSSI(X) (X >> 1) + +struct rtw_phl_rssi_stat { + _os_lock lock; + u8 ma_rssi_ele_idx[RTW_RSSI_TYPE_MAX]; + u8 ma_rssi_ele_cnt[RTW_RSSI_TYPE_MAX]; /* maximum : PHL_RSSI_MAVG_NUM */ + u8 ma_rssi_ele[RTW_RSSI_TYPE_MAX][PHL_RSSI_MAVG_NUM]; /* rssi element for moving average */ + u32 ma_rssi_ele_sum[RTW_RSSI_TYPE_MAX]; + u8 ma_rssi[RTW_RSSI_TYPE_MAX]; /* moving average : 0~PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ +}; + +#define PHL_MAX_PPDU_CNT 8 +#define PHL_MAX_PPDU_STA_NUM 4 +struct rtw_phl_ppdu_sts_sta_ent { + u8 vld; + /*u8 rssi;*/ + u16 macid; +}; +struct rtw_phl_ppdu_phy_info { + bool is_valid; + u8 rssi; /*signal power : 0 - PHL_MAX_RSSI, rssi dbm = PHL_MAX_RSSI - value*/ + u8 rssi_path[RTW_PHL_MAX_RF_PATH];/*PATH A, PATH B ... PATH D*/ + u8 ch_idx; + u8 tx_bf; + u8 frame_type; /* type + subtype */ +}; +#ifdef CONFIG_PHY_INFO_NTFY +struct rtw_phl_ppdu_sts_ntfy { + bool vld; + u8 frame_type; + u8 src_mac_addr[MAC_ADDRESS_LENGTH]; + struct rtw_phl_ppdu_phy_info phy_info; +}; +#endif +struct rtw_phl_ppdu_sts_ent { + /* from normal data */ + u8 frame_type; + u8 addr_cam_vld; + u8 crc32; + u8 ppdu_type; + u16 rx_rate; + u8 src_mac_addr[MAC_ADDRESS_LENGTH]; + + /* from ppdu status */ + bool valid; + bool phl_done; + u8 usr_num; + u32 freerun_cnt; + struct rtw_phl_ppdu_phy_info phy_info; + struct rtw_phl_ppdu_sts_sta_ent sta[PHL_MAX_PPDU_STA_NUM]; +#ifdef CONFIG_PHL_RX_PSTS_PER_PKT + /* for ppdu status per pkt */ + struct phl_queue frames; +#endif +}; +struct rtw_phl_ppdu_sts_info { + struct rtw_phl_ppdu_sts_ent sts_ent[HW_BAND_MAX][PHL_MAX_PPDU_CNT]; + u8 cur_rx_ppdu_cnt[HW_BAND_MAX]; + bool en_ppdu_sts[HW_BAND_MAX]; + bool latest_rx_is_psts[HW_BAND_MAX]; +#ifdef CONFIG_PHL_RX_PSTS_PER_PKT + bool en_psts_per_pkt; + bool psts_ampdu; +#define RTW_PHL_PSTS_FLTR_MGNT BIT(RTW_FRAME_TYPE_MGNT) +#define RTW_PHL_PSTS_FLTR_CTRL BIT(RTW_FRAME_TYPE_CTRL) +#define RTW_PHL_PSTS_FLTR_DATA BIT(RTW_FRAME_TYPE_DATA) +#define RTW_PHL_PSTS_FLTR_EXT_RSVD BIT(RTW_FRAME_TYPE_EXT_RSVD) + u8 ppdu_sts_filter; + u8 en_fake_psts; + u8 cur_ppdu_cnt[HW_BAND_MAX]; +#endif +#ifdef CONFIG_PHY_INFO_NTFY +#define MAX_PSTS_MSG_AGGR_NUM 10 + struct rtw_phl_ppdu_sts_ntfy msg_aggr_buf[MAX_PSTS_MSG_AGGR_NUM]; + u8 msg_aggr_cnt; +#endif +}; + +struct rtw_phl_gid_pos_tbl { +#define RTW_VHT_GID_MGNT_FRAME_GID_SZ 8 +#define RTW_VHT_GID_MGNT_FRAME_POS_SZ 16 + u8 gid_vld[RTW_VHT_GID_MGNT_FRAME_GID_SZ]; /* from 0 - 63 */ + u8 pos[RTW_VHT_GID_MGNT_FRAME_POS_SZ]; /* 0 - 63, per 2 bit*/ +}; + + +struct rtw_iot_t { + u32 id; +}; + +#ifdef CONFIG_PHL_THERMAL_PROTECT +enum phl_thermal_protect_action{ + PHL_THERMAL_PROTECT_ACTION_NONE = 0, + PHL_THERMAL_PROTECT_ACTION_LEVEL1 = 1, + PHL_THERMAL_PROTECT_ACTION_LEVEL2 = 2, +}; +#endif + +struct rtw_phl_evt_ops; +struct rtw_phl_com_t { + struct rtw_wifi_role_t wifi_roles[MAX_WIFI_ROLE_NUMBER]; + struct mr_ctl_t mr_ctrl; /*multi wifi_role control module*/ + struct rtw_phl_evt_ops evt_ops; + enum rtw_hci_type hci_type; + enum rtw_drv_mode drv_mode;/*normal or mp mode*/ + enum rtw_dev_state dev_state; + + struct hal_spec_t hal_spec; + + struct role_sw_cap_t role_sw_cap; /* SW control capability of role for any purpose */ + struct protocol_cap_t proto_sw_cap[2]; /* SW control wifi protocol capability for any purpose */ + struct phy_sw_cap_t phy_sw_cap[2]; /* SW control phy capability for any purpose */ + struct phy_cap_t phy_cap[2]; /* final capability of phy (intersection of sw/hw) */ + + struct dev_cap_t dev_sw_cap; + struct dev_cap_t dev_cap; /* final capability of device (intersection of sw/hw) */ + + struct bus_sw_cap_t bus_sw_cap; /* SW controlled bus capability */ + + struct rtw_fw_info_t fw_info; + struct rtw_evt_info_t evt_info; + struct rtw_stats phl_stats; + #ifdef CONFIG_PHL_DFS + struct rtw_dfs_t dfs_info; + #endif + struct rtw_iot_t id; + /* Flags to control/check RX packets */ + bool append_fcs; + bool accept_icv_err; + + u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS, get_min from registery and hal_spec*/ + u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS, get_min from registery and hal_spec*/ + u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/ + u8 rf_path_num; /*GET_HAL_RFPATH_NUM*/ + u8 regulation; /*regulation*/ + u8 edcca_mode; + +#ifdef CONFIG_PHL_CHANNEL_INFO + struct rx_chan_info_pool *chan_info_pool; + struct chan_info_t *chan_info; /* Handle channel info packet */ +#endif /* CONFIG_PHL_CHANNEL_INFO */ + void *p2pps_info; + + struct rtw_phl_ppdu_sts_info ppdu_sts_info; + struct rtw_phl_rssi_stat rssi_stat; +#ifdef CONFIG_PHL_THERMAL_PROTECT + enum phl_thermal_protect_action thermal_protect_action; +#endif + void *test_mgnt; + + void *phl_priv; /* pointer to phl_info */ + void *drv_priv; +#ifdef RTW_WKARD_BFEE_SET_AID + u8 is_in_lps; +#endif +}; + +struct phl_sec_param_h { + u8 keyid; + u8 enc_type; + u8 key_type; + u8 key_len; + u8 spp; +}; + +#define PHL_MAX_AGG_WSIZE 32 + +struct mp_usr_sw_tx_gen_in { + u32 data_rate : 9; + u32 mcs : 6; + u32 mpdu_len : 14; + u32 n_mpdu : 9; + u32 fec : 1; + u32 dcm : 1; + u32 rsvd0 : 1; + u32 aid : 12; + u32 scrambler_seed : 8; // rand (1~255) + u32 random_init_seed : 8; // rand (1~255) + u32 rsvd1 : 4; + u32 apep : 22; + u32 ru_alloc : 8; + u32 rsvd2 : 2; + u32 nss : 4; + u32 txbf : 1; + u32 pwr_boost_db : 5; + u32 rsvd3 : 22; +}; + + +struct mp_sw_tx_param_t { + u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 + u32 source_gen_mode : 2; + u32 locked_clk : 1; + u32 dyn_bw : 1; + u32 ndp_en : 1; + u32 long_preamble_en : 1; //bmode + u32 stbc : 1; + u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 + u32 tb_l_len : 12; + u32 tb_ru_tot_sts_max : 3; + u32 vht_txop_not_allowed : 1; + u32 tb_disam : 1; + u32 doppler : 2; + u32 he_ltf_type : 2;//0:1x,1:2x,2:4x + + u32 ht_l_len : 12; + u32 preamble_puncture : 1; + u32 he_mcs_sigb : 3;//0~5 + u32 he_dcm_sigb : 1; + u32 he_sigb_compress_en : 1; + u32 max_tx_time_0p4us : 14; + + + u32 ul_flag : 1; + u32 tb_ldpc_extra : 1; + u32 bss_color : 6; + u32 sr : 4; + u32 beamchange_en : 1; + u32 he_er_u106ru_en : 1; + u32 ul_srp1 : 4; + u32 ul_srp2 : 4; + u32 ul_srp3 : 4; + u32 ul_srp4 : 4; + u32 mode : 2; + + u32 group_id : 6; + u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB + u32 txop : 7; + u32 tb_strt_sts : 3; + u32 tb_pre_fec_padding_factor : 2; + u32 cbw : 2; + u32 txsc : 4; + u32 tb_mumimo_mode_en : 1; + u32 rsvd1 : 3; + + u8 nominal_t_pe : 2; // def = 2 + u8 ness : 2; // def = 0 + u8 rsvd2 : 4; + + u8 n_user; + u16 tb_rsvd : 9;//def = 0 + u16 rsvd3 : 7; + + struct mp_usr_sw_tx_gen_in usr[4]; +}; + +struct mp_usr_plcp_gen_in { + u32 mcs : 6; + u32 mpdu_len : 14; + u32 n_mpdu : 9; + u32 fec : 1; + u32 dcm : 1; + u32 rsvd0 : 1; + u32 aid : 12; + u32 scrambler_seed : 8; // rand (1~255) + u32 random_init_seed : 8; // rand (1~255) + u32 rsvd1 : 4; + u32 apep : 22; + u32 ru_alloc : 8; + u32 rsvd2 : 2; + u32 nss : 4; + u32 txbf : 1; + u32 pwr_boost_db : 5; + u32 rsvd3 : 22; +}; + +enum pkt_ofld_type { + PKT_TYPE_PROBE_RSP = 0, + PKT_TYPE_PS_POLL = 1, + PKT_TYPE_NULL_DATA = 2, + PKT_TYPE_QOS_NULL = 3, + PKT_TYPE_CTS2SELF = 4, + PKT_TYPE_ARP_RSP = 5, + PKT_TYPE_NDP = 6, + PKT_TYPE_EAPOL_KEY = 7, + PKT_TYPE_SA_QUERY = 8, + PKT_TYPE_REALWOW_KAPKT = 9, /* RealWoW Keep Alive Packet */ + PKT_TYPE_REALWOW_ACK = 10, /* RealWoW Ack Patten */ + PKT_TYPE_REALWOW_WP = 11, /* RealWoW Wakeup Patten */ + PKT_OFLD_TYPE_MAX, +}; + +struct mp_plcp_param_t { + u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 + u32 source_gen_mode : 2; + u32 locked_clk : 1; + u32 dyn_bw : 1; + u32 ndp_en : 1; + u32 long_preamble_en : 1; //bmode + u32 stbc : 1; + u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 + u32 tb_l_len : 12; + u32 tb_ru_tot_sts_max : 3; + u32 vht_txop_not_allowed : 1; + u32 tb_disam : 1; + u32 doppler : 2; + u32 he_ltf_type : 2;//0:1x,1:2x,2:4x + + u32 ht_l_len : 12; + u32 preamble_puncture : 1; + u32 he_mcs_sigb : 3;//0~5 + u32 he_dcm_sigb : 1; + u32 he_sigb_compress_en : 1; + u32 max_tx_time_0p4us : 14; + + + u32 ul_flag : 1; + u32 tb_ldpc_extra : 1; + u32 bss_color : 6; + u32 sr : 4; + u32 beamchange_en : 1; + u32 he_er_u106ru_en : 1; + u32 ul_srp1 : 4; + u32 ul_srp2 : 4; + u32 ul_srp3 : 4; + u32 ul_srp4 : 4; + u32 mode : 2; + + u32 group_id : 6; + u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB + u32 txop : 7; + u32 tb_strt_sts : 3; + u32 tb_pre_fec_padding_factor : 2; + u32 cbw : 2; + u32 txsc : 4; + u32 tb_mumimo_mode_en : 1; + u32 rsvd1 : 3; + + u8 nominal_t_pe : 2; // def = 2 + u8 ness : 2; // def = 0 + u8 rsvd2 : 4; + + u8 n_user; + u16 tb_rsvd : 9;//def = 0 + u16 rsvd3 : 7; + + struct mp_usr_plcp_gen_in usr[4]; +}; + + + +#define MP_MAC_AX_MAX_RU_NUM 4 + +struct mp_mac_ax_tf_depend_user_para { + u8 pref_AC: 2; + u8 rsvd: 6; +}; + +struct mp_mac_ax_tf_user_para { + u16 aid12: 12; + u16 ul_mcs: 4; + u8 macid; + u8 ru_pos; + + u8 ul_fec_code: 1; + u8 ul_dcm: 1; + u8 ss_alloc: 6; + u8 ul_tgt_rssi: 7; + u8 rsvd: 1; + u16 rsvd2; +}; + + +struct mp_mac_ax_tf_pkt_para { + u8 ul_bw: 2; + u8 gi_ltf: 2; + u8 num_he_ltf: 3; + u8 ul_stbc: 1; + u8 doppler: 1; + u8 ap_tx_power: 6; + u8 rsvd0: 1; + u8 user_num: 3; + u8 pktnum: 3; + u8 rsvd1: 2; + u8 pri20_bitmap; + + struct mp_mac_ax_tf_user_para user[MP_MAC_AX_MAX_RU_NUM]; + struct mp_mac_ax_tf_depend_user_para dep_user[MP_MAC_AX_MAX_RU_NUM]; +}; + +struct mp_mac_ax_tf_wd_para { + u16 datarate: 9; + u16 mulport_id: 3; + u16 pwr_ofset: 3; + u16 rsvd: 1; +}; + +struct mp_mac_ax_f2p_test_para { + struct mp_mac_ax_tf_pkt_para tf_pkt; + struct mp_mac_ax_tf_wd_para tf_wd; + u8 mode: 2; + u8 frexch_type: 6; + u8 sigb_len; +}; + +struct mp_mac_ax_f2p_wd { + /* dword 0 */ + u32 cmd_qsel:6; + u32 rsvd0:2; + u32 rsvd1:2; + u32 ls:1; + u32 fs:1; + u32 total_number:4; + u32 seq:8; + u32 length:8; + /* dword 1 */ + u32 rsvd2; +}; + +struct mp_mac_ax_f2p_tx_cmd { + /* dword 0 */ + u32 cmd_type:8; + u32 cmd_sub_type:8; + u32 dl_user_num:5; + u32 bw:2; + u32 tx_power:9; + /* dword 1 */ + u32 fw_define:16; + u32 ss_sel_mode:2; + u32 next_qsel:6; + u32 twt_group:4; + u32 dis_chk_slp:1; + u32 ru_mu_2_su:1; + u32 dl_t_pe:2; + /* dword 2 */ + u32 sigb_ch1_len:8; + u32 sigb_ch2_len:8; + u32 sigb_sym_num:6; + u32 sigb_ch2_ofs:5; + u32 dis_htp_ack:1; + u32 tx_time_ref:2; + u32 pri_user_idx:2; + /* dword 3 */ + u32 ampdu_max_txtime:14; + u32 rsvd0:2; + u32 group_id:6; + u32 rsvd1:2; + u32 rsvd2:4; + u32 twt_chk_en:1; + u32 twt_port_id:3; + /* dword 4 */ + u32 twt_start_time:32; + /* dword 5 */ + u32 twt_end_time:32; + /* dword 6 */ + u32 apep_len:12; + u32 tri_pad:2; + u32 ul_t_pe:2; + u32 rf_gain_idx:10; + u32 fixed_gain_en:1; + u32 ul_gi_ltf:3; + u32 ul_doppler:1; + u32 ul_stbc:1; + /* dword 7 */ + u32 ul_mid_per:1; + u32 ul_cqi_rrp_tri:1; + u32 rsvd3:6; + u32 rsvd4:8; + u32 sigb_dcm:1; + u32 sigb_comp:1; + u32 doppler:1; + u32 stbc:1; + u32 mid_per:1; + u32 gi_ltf_size:3; + u32 sigb_mcs:3; + u32 rsvd5:5; + /* dword 8 */ + u32 macid_u0:8; + u32 ac_type_u0:2; + u32 mu_sta_pos_u0:2; + u32 dl_rate_idx_u0:9; + u32 dl_dcm_en_u0:1; + u32 rsvd6:2; + u32 ru_alo_idx_u0:8; + /* dword 9 */ + u32 pwr_boost_u0:5; + u32 agg_bmp_alo_u0:3; + u32 ampdu_max_txnum_u0:8; + u32 user_define_u0:8; + u32 user_define_ext_u0:8; + /* dword 10 */ + u32 ul_addr_idx_u0:8; + u32 ul_dcm_u0:1; + u32 ul_fec_cod_u0:1; + u32 ul_ru_rate_u0:7; + u32 rsvd8:7; + u32 ul_ru_alo_idx_u0:8; + /* dword 11 */ + u32 rsvd9:32; + /* dword 12 */ + u32 macid_u1:8; + u32 ac_type_u1:2; + u32 mu_sta_pos_u1:2; + u32 dl_rate_idx_u1:9; + u32 dl_dcm_en_u1:1; + u32 rsvd10:2; + u32 ru_alo_idx_u1:8; + /* dword 13 */ + u32 pwr_boost_u1:5; + u32 agg_bmp_alo_u1:3; + u32 ampdu_max_txnum_u1:8; + u32 user_define_u1:8; + u32 user_define_ext_u1:8; + /* dword 14 */ + u32 ul_addr_idx_u1:8; + u32 ul_dcm_u1:1; + u32 ul_fec_cod_u1:1; + u32 ul_ru_rate_u1:7; + u32 rsvd12:7; + u32 ul_ru_alo_idx_u1:8; + /* dword 15 */ + u32 rsvd13:32; + /* dword 16 */ + u32 macid_u2:8; + u32 ac_type_u2:2; + u32 mu_sta_pos_u2:2; + u32 dl_rate_idx_u2:9; + u32 dl_dcm_en_u2:1; + u32 rsvd14:2; + u32 ru_alo_idx_u2:8; + /* dword 17 */ + u32 pwr_boost_u2:5; + u32 agg_bmp_alo_u2:3; + u32 ampdu_max_txnum_u2:8; + u32 user_define_u2:8; + u32 user_define_ext_u2:8; + /* dword 18 */ + u32 ul_addr_idx_u2:8; + u32 ul_dcm_u2:1; + u32 ul_fec_cod_u2:1; + u32 ul_ru_rate_u2:7; + u32 rsvd16:7; + u32 ul_ru_alo_idx_u2:8; + /* dword 19 */ + u32 rsvd17:32; + /* dword 20 */ + u32 macid_u3:8; + u32 ac_type_u3:2; + u32 mu_sta_pos_u3:2; + u32 dl_rate_idx_u3:9; + u32 dl_dcm_en_u3:1; + u32 rsvd18:2; + u32 ru_alo_idx_u3:8; + /* dword 21 */ + u32 pwr_boost_u3:5; + u32 agg_bmp_alo_u3:3; + u32 ampdu_max_txnum_u3:8; + u32 user_define_u3:8; + u32 user_define_ext_u3:8; + /* dword 22 */ + u32 ul_addr_idx_u3:8; + u32 ul_dcm_u3:1; + u32 ul_fec_cod_u3:1; + u32 ul_ru_rate_u3:7; + u32 rsvd20:7; + u32 ul_ru_alo_idx_u3:8; + /* dword 23 */ + u32 rsvd21:32; + /* dword 24 */ + u32 pkt_id_0:12; + u32 rsvd22:3; + u32 valid_0:1; + u32 ul_user_num_0:4; + u32 rsvd23:12; + /* dword 25 */ + u32 pkt_id_1:12; + u32 rsvd24:3; + u32 valid_1:1; + u32 ul_user_num_1:4; + u32 rsvd25:12; + /* dword 26 */ + u32 pkt_id_2:12; + u32 rsvd26:3; + u32 valid_2:1; + u32 ul_user_num_2:4; + u32 rsvd27:12; + /* dword 27 */ + u32 pkt_id_3:12; + u32 rsvd28:3; + u32 valid_3:1; + u32 ul_user_num_3:4; + u32 rsvd29:12; + /* dword 28 */ + u32 pkt_id_4:12; + u32 rsvd30:3; + u32 valid_4:1; + u32 ul_user_num_4:4; + u32 rsvd31:12; + /* dword 29 */ + u32 pkt_id_5:12; + u32 rsvd32:3; + u32 valid_5:1; + u32 ul_user_num_5:4; + u32 rsvd33:12; +}; + +u8 mp_start(void *priv); + +#ifdef CONFIG_DBCC_SUPPORT +enum dbcc_test_id { + DBCC_PRE_CFG, + DBCC_CFG, + DBCC_CLEAN_TXQ, +}; +#endif + +struct rtw_role_cmd { + struct rtw_wifi_role_t *wrole; + enum role_state rstate; +}; + +enum phl_btc_pkt_evt_type { + BTC_PKT_EVT_NORMAL, + BTC_PKT_EVT_DHCP, + BTC_PKT_EVT_ARP, + BTC_PKT_EVT_EAPOL, + BTC_PKT_EVT_EAPOL_START, + BTC_PKT_EVT_ADD_KEY, + BTC_PKT_EVT_MAX +}; + +struct rtw_pkt_evt_ntfy { + struct rtw_wifi_role_t *wrole; + enum phl_btc_pkt_evt_type type; +}; + +struct role_ntfy_info { + u8 role_id; + u16 macid; + enum role_state rstate; +}; + +struct battery_chg_ntfy_info { + bool ips_allow; + bool lps_allow; +}; + +struct ps_ntfy_info { + bool sync; + void *ctx; + void (*cb)(void *phl, void *hdl, void *ctx, enum rtw_phl_status stat); +}; + +struct set_rf_ntfy_info { + enum rtw_rf_state state_to_set; + _os_event done; +}; + + +/** + * rtw_phl_rainfo - structure use to query RA information + * from hal layer to core/phl layer + * @rate: current rate selected by RA, define by general definition enum rtw_data_rate + * @bw: current BW, define by general definition enum channel_width + * @gi_ltf: current gi_ltf, define by general definition enum rtw_gi_ltf + */ +struct rtw_phl_rainfo { + enum rtw_data_rate rate; + enum channel_width bw; + enum rtw_gi_ltf gi_ltf; +}; + +struct rtw_pcie_trx_mit_info_t { + u32 tx_timer; + u8 tx_counter; + u32 rx_timer; + u8 rx_counter; + u8 fixed_mitigation; /*no watchdog dynamic setting*/ + void *priv; +}; + +struct rtw_env_report { + bool rpt_status; /*1 means CCX_SUCCESS,0 means fail*/ + u8 clm_ratio; + u8 nhm_ratio; + u8 nhm_pwr; + u8 nhm_cca_ratio; +}; + +enum rtw_phl_ser_lv1_recv_step { + RTW_PHL_SER_LV1_RCVY_STEP_1 = 0, + RTW_PHL_SER_LV1_SER_RCVY_STEP_2, + + /* keep last */ + RTW_PHL_SER_LV1_RCVY_STEP_LAST, + RTW_PHL_SER_LV1_RCVY_STEP_MAX = RTW_PHL_SER_LV1_RCVY_STEP_LAST, + RTW_PHL_SER_LV1_RCVY_STEP_INVALID = RTW_PHL_SER_LV1_RCVY_STEP_LAST, +}; + +#endif /*_PHL_DEF_H_*/ diff --git a/phl/phl_dm.c b/phl/phl_dm.c new file mode 100644 index 0000000..c13413a --- /dev/null +++ b/phl/phl_dm.c @@ -0,0 +1,136 @@ + +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_DM_C_ +#include "phl_headers.h" + +void rtw_phl_set_edcca_mode(void *phl, enum rtw_edcca_mode mode) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + PHL_INFO("[Cert], set phl_com edcca_mode : %d !! \n", mode); + phl_info->phl_com->edcca_mode = mode; +} + +enum rtw_edcca_mode rtw_phl_get_edcca_mode(void *phl) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + return phl_info->phl_com->edcca_mode; +} + +#ifdef CONFIG_PCI_HCI +#ifdef RTW_WKARD_DYNAMIC_LTR +enum rtw_phl_status +phl_ltr_sw_trigger(struct rtw_phl_com_t *phl_com, void *hal, + enum rtw_pcie_ltr_state state) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap; + + status = rtw_hal_ltr_sw_trigger(hal, state); + + if (status == RTW_HAL_STATUS_SUCCESS) { + sw_cap->ltr_cur_state = state; + sw_cap->ltr_last_trigger_time = _os_get_cur_time_us(); + state == RTW_PCIE_LTR_SW_ACT ? + sw_cap->ltr_sw_act_tri_cnt++ : sw_cap->ltr_sw_idle_tri_cnt++; + return RTW_PHL_STATUS_SUCCESS; + } else { + return RTW_PHL_STATUS_FAILURE; + } +} + +/* Switching sw ctrl will trigger active ltr at the same time +to prevent inconsistent state */ +/* usage : echo phl ltr set [enable/disable] */ +enum rtw_phl_status +phl_ltr_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal, bool enable) +{ + enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE; + + status = phl_ltr_sw_trigger(phl_com, hal, RTW_PCIE_LTR_SW_ACT); + + if (status == RTW_HAL_STATUS_SUCCESS) { + phl_com->bus_sw_cap.ltr_sw_ctrl = enable; + return RTW_PHL_STATUS_SUCCESS; + } else { + return RTW_PHL_STATUS_FAILURE; + } +} + +/* switch to hw control. it's valid that only hw supports hw mode */ +/* usage : echo phl ltr set [enable/disable] */ +void +phl_ltr_hw_ctrl(struct rtw_phl_com_t *phl_com, bool enable) +{ + phl_com->bus_sw_cap.ltr_hw_ctrl = enable; +} + +/* For pm module, this will not trigger active ltr since halmac will take care of*/ +void phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t *phl_com, bool enable) +{ + phl_com->bus_sw_cap.ltr_sw_ctrl = enable; +} + +u8 phl_ltr_get_cur_state(struct rtw_phl_com_t *phl_com) +{ + return phl_com->bus_sw_cap.ltr_cur_state; +} + +u32 phl_ltr_get_last_trigger_time(struct rtw_phl_com_t *phl_com) +{ + return phl_com->bus_sw_cap.ltr_last_trigger_time; +} + +u32 phl_ltr_get_tri_cnt(struct rtw_phl_com_t *phl_com, + enum rtw_pcie_ltr_state state) +{ + struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap; + + return state == RTW_PCIE_LTR_SW_ACT ? + sw_cap->ltr_sw_act_tri_cnt : sw_cap->ltr_sw_idle_tri_cnt; +} + +#define TP_MBPS 100 +void phl_ltr_ctrl_watchdog(struct phl_info_t *phl_info) +{ + struct rtw_phl_com_t *phl_com = phl_info->phl_com; + struct rtw_stats *sts = &phl_com->phl_stats; + u32 tx_tp_m = 0, rx_tp_m = 0; + static bool start = false; + + /* only valid if it's currenlty running hw mode */ + if (!rtw_hal_ltr_is_hw_ctrl(phl_com, phl_info->hal)) + return; + + tx_tp_m = sts->tx_tp_kbits >> 10; + rx_tp_m = sts->rx_tp_kbits >> 10; + + /* PHL_INFO("%s tx_tp_m = %u /rx_tp_m = %u \n", __func__, tx_tp_m, rx_tp_m);*/ + + if ((tx_tp_m > TP_MBPS || rx_tp_m > TP_MBPS) && !start) { + start = true; + rtw_hal_ltr_en_hw_mode(phl_info->hal, false); + rtw_hal_ltr_sw_trigger(phl_info->hal, RTW_PCIE_LTR_SW_ACT); + } + + if (start && tx_tp_m < TP_MBPS && rx_tp_m < TP_MBPS) { + start = false; + rtw_hal_ltr_en_hw_mode(phl_info->hal, true); + } +} +#endif /* RTW_WKARD_DYNAMIC_LTR */ +#endif /* CONFIG_PCI_HCI */ \ No newline at end of file diff --git a/phl/phl_dm.h b/phl/phl_dm.h new file mode 100644 index 0000000..7daf858 --- /dev/null +++ b/phl/phl_dm.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2021 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_DM_H_ +#define _PHL_DM_H_ + +#ifdef CONFIG_PCI_HCI +#ifdef RTW_WKARD_DYNAMIC_LTR +enum rtw_phl_status +phl_ltr_sw_trigger(struct rtw_phl_com_t *phl_com, void *hal, + enum rtw_pcie_ltr_state state); +enum rtw_phl_status +phl_ltr_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal, bool enable); +void +phl_ltr_hw_ctrl(struct rtw_phl_com_t *phl_com, bool enable); +void phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t *phl_com, bool enable); +u8 phl_ltr_get_cur_state(struct rtw_phl_com_t *phl_com); +u32 phl_ltr_get_last_trigger_time(struct rtw_phl_com_t *phl_com); +u32 phl_ltr_get_tri_cnt(struct rtw_phl_com_t *phl_com, + enum rtw_pcie_ltr_state state); +void phl_ltr_ctrl_watchdog(struct phl_info_t *phl_info); +#endif +#endif + +#endif /*_PHL_DM_H_*/ \ No newline at end of file diff --git a/phl/phl_ecsa.c b/phl/phl_ecsa.c new file mode 100644 index 0000000..7f7bc98 --- /dev/null +++ b/phl/phl_ecsa.c @@ -0,0 +1,974 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_ECSA_C_ +#include "phl_headers.h" + +#ifdef CONFIG_PHL_ECSA +void +_phl_ecsa_dump_param( + struct rtw_phl_ecsa_param *param +) +{ + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Channel %d\n", __FUNCTION__, + param->ch); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Op class %d\n", __FUNCTION__, + param->op_class); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Count %d\n", __FUNCTION__, + param->count); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Mode %d\n", __FUNCTION__, + param->mode); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Delay time %d\n", __FUNCTION__, + param->delay_start_ms); + PHL_DUMP_CHAN_DEF(&(param->new_chan_def)); +} + +enum rtw_phl_status +_phl_ecsa_tx_pause( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + + /* Pause SW Tx */ + rtw_phl_tx_stop(phl_info); + rtw_phl_tx_req_notify(phl_info); + + /* Disable hw tx all */ + if (rtw_hal_dfs_pause_tx(phl_info->hal, wifi_role->hw_band, true) == + RTW_HAL_STATUS_SUCCESS) { + status = RTW_PHL_STATUS_SUCCESS; + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "[ECSA] hw tx pause OK\n"); + } else { + status = RTW_PHL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "[ECSA] hw tx pause fail\n"); + } + + return status; +} + +enum rtw_phl_status +_phl_ecsa_tx_resume( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + + /* Enable hw tx all */ + if (rtw_hal_dfs_pause_tx(phl_info->hal, wifi_role->hw_band, false) == + RTW_HAL_STATUS_SUCCESS) { + status = RTW_PHL_STATUS_SUCCESS; + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "[ECSA] hw tx unpause OK\n"); + } else { + status = RTW_PHL_STATUS_FAILURE; + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "[ECSA] hw tx unpause fail\n"); + } + + rtw_phl_tx_resume(phl_info); + + return status; +} + +u32 +_phl_ecsa_calculate_next_timer_ap( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_bcn_info_cmn *bcn_cmn = NULL; + u32 tsf_h = 0, tsf_l = 0; + u64 tsf = 0; + u32 beacon_period_us = 0, timeslot_us = 0, next_timeslot_us = 0; + u32 current_time_ms = _os_get_cur_time_ms(); + + if (RTW_HAL_STATUS_SUCCESS != rtw_hal_get_tsf(phl_info->hal, + ecsa_ctrl->role->hw_port, + &tsf_h, + &tsf_l)) { + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "_phl_ecsa_timer_callback(): Get tsf fail\n"); + return 0; + } + tsf = tsf_h; + tsf = tsf << 32; + tsf |= tsf_l; + + bcn_cmn = &ecsa_ctrl->role->bcn_cmn; + beacon_period_us = bcn_cmn->bcn_interval * TU; + + timeslot_us = (u32)_os_modular64(tsf, beacon_period_us); + + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: CurTimeMs = %d State = %x timeslot = %d\n", + __FUNCTION__, current_time_ms, ecsa_ctrl->state, timeslot_us); + + if(ecsa_ctrl->state == ECSA_STATE_START){ + next_timeslot_us = beacon_period_us - timeslot_us + (2 * TU); + } + /* To make sure first ECSA IE show in Beacon */ + else if(ecsa_ctrl->state == ECSA_STATE_UPDATE_FIRST_BCN_DONE){ + next_timeslot_us = (beacon_period_us - timeslot_us - + ECSA_UPDATE_BCN_BEFORE_TBTT_US); + ecsa_ctrl->expected_tbtt_ms = current_time_ms + + (beacon_period_us - timeslot_us)/1000; + } + else if(ecsa_ctrl->state == ECSA_STATE_COUNT_DOWN){ + if(ecsa_ctrl->ecsa_param.count == 1){ + next_timeslot_us = (beacon_period_us - timeslot_us) + + ECSA_SWITCH_TIME_AFTER_LAST_COUNT_DOWN; + } + else{ + next_timeslot_us = (beacon_period_us - timeslot_us) + + (beacon_period_us - ECSA_UPDATE_BCN_BEFORE_TBTT_US); + + ecsa_ctrl->expected_tbtt_ms = current_time_ms + + (2 * beacon_period_us - timeslot_us)/1000; + } + } + + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Expected tbtt %d!\n", __FUNCTION__, ecsa_ctrl->expected_tbtt_ms); + return next_timeslot_us/1000; +} + +u32 +_phl_ecsa_calculate_next_timer_sta( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_phl_stainfo_t *sta = NULL; + u32 beacon_period_us = 0, next_timeslot = 0; + u32 current_time_ms = 0; + + current_time_ms = _os_get_cur_time_ms(); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: CurTimeMs = %d State = %x\n", + __FUNCTION__, current_time_ms, ecsa_ctrl->state); + + sta = rtw_phl_get_stainfo_self(phl_info, wifi_role); + if(sta == NULL){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_ERR_, "%s: Get sta info fail!\n", + __FUNCTION__); + return 0; + } + + beacon_period_us = sta->asoc_cap.bcn_interval * TU; + + if(ecsa_ctrl->state == ECSA_STATE_START){ + next_timeslot = 0; + } + else if(ecsa_ctrl->state == ECSA_STATE_COUNT_DOWN){ + u8 count = ecsa_ctrl->ecsa_param.count; + next_timeslot = (beacon_period_us * count) / 1000; /* ms */ + } + else if(ecsa_ctrl->state == ECSA_STATE_SWITCH){ + next_timeslot = 1000; /* 1s */ + } + + return next_timeslot; +} + +void +_phl_ecsa_calculate_next_timer( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + void *d = phlcom_to_drvpriv(phl_com); + u32 next_timeslot = 0; /* ms */ + + if(IS_ECSA_TYPE_AP(ecsa_ctrl)) + next_timeslot = _phl_ecsa_calculate_next_timer_ap(ecsa_ctrl); + + if(IS_ECSA_TYPE_STA(ecsa_ctrl)) + next_timeslot = _phl_ecsa_calculate_next_timer_sta(ecsa_ctrl);; + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: Next time slot %d!\n", __FUNCTION__, next_timeslot); + _os_set_timer(d, &ecsa_ctrl->timer, next_timeslot); + +} + +void _phl_ecsa_state_change_ap( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + void *d = phlcom_to_drvpriv(phl_com); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_ECSA); + + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: CurTimeMs = %d State = %x\n", + __FUNCTION__, _os_get_cur_time_ms(), ecsa_ctrl->state); + + /* Protect ECSA state change to prevent timer callback racing */ + _os_spinlock(d, &(ecsa_ctrl->lock), _bh, NULL); + + if(ecsa_ctrl->state == ECSA_STATE_WAIT_DELAY){ + status = rtw_phl_ecsa_cmd_request(phl_info, ecsa_ctrl->role); + if(status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: ECSA command fail!\n", __FUNCTION__); + ecsa_ctrl->state = ECSA_STATE_NONE; + } + else{ + ecsa_ctrl->state = ECSA_STATE_START; + } + + } + else if(ecsa_ctrl->state == ECSA_STATE_START){ + ecsa_ctrl->state = ECSA_STATE_UPDATE_FIRST_BCN_DONE; + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_UPDATE_FIRST_BCN_DONE); + + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + /* To make sure first ECSA IE show in Beacon */ + else if(ecsa_ctrl->state == ECSA_STATE_UPDATE_FIRST_BCN_DONE){ + ecsa_ctrl->state = ECSA_STATE_COUNT_DOWN; + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_COUNT_DOWN); + + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + else if(ecsa_ctrl->state == ECSA_STATE_COUNT_DOWN){ + if(ecsa_ctrl->ecsa_param.count == 1){ + ecsa_ctrl->state = ECSA_STATE_SWITCH; + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_SWITCH_START); + msg.rsvd[0] = (u8*)ecsa_ctrl->role; + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + else{ + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_COUNT_DOWN); + + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + } + _os_spinunlock(d, &(ecsa_ctrl->lock), _bh, NULL); +} + +void _phl_ecsa_state_change_sta( + struct phl_ecsa_ctrl_t *ecsa_ctrl +) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct rtw_phl_com_t *phl_com = ecsa_ctrl->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + void *d = phlcom_to_drvpriv(phl_com); + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_ECSA); + + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: CurTimeMs = %d State = %x\n", + __FUNCTION__, _os_get_cur_time_ms(), ecsa_ctrl->state); + + /* Protect ECSA state change to prevent timer callback racing */ + _os_spinlock(d, &(ecsa_ctrl->lock), _bh, NULL); + + if(ecsa_ctrl->state == ECSA_STATE_WAIT_DELAY){ + status = rtw_phl_ecsa_cmd_request(phl_info, ecsa_ctrl->role); + if(status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: ECSA command fail!\n", __FUNCTION__); + ecsa_ctrl->state = ECSA_STATE_NONE; + } + else{ + ecsa_ctrl->state = ECSA_STATE_START; + } + } + else if(ecsa_ctrl->state == ECSA_STATE_START){ + ecsa_ctrl->state = ECSA_STATE_COUNT_DOWN; + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_COUNT_DOWN); + + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + else if(ecsa_ctrl->state == ECSA_STATE_COUNT_DOWN){ + ecsa_ctrl->state = ECSA_STATE_SWITCH; + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_SWITCH_START); + msg.rsvd[0] = (u8*)ecsa_ctrl->role; + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + else if(ecsa_ctrl->state == ECSA_STATE_SWITCH){ + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_CHECK_TX_RESUME); + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + _os_spinunlock(d, &(ecsa_ctrl->lock), _bh, NULL); +} + +void +_phl_ecsa_timer_callback( + void *context + ) +{ + struct phl_ecsa_ctrl_t *ecsa_ctrl = (struct phl_ecsa_ctrl_t *)context; + + if(IS_ECSA_TYPE_AP(ecsa_ctrl)) + _phl_ecsa_state_change_ap(ecsa_ctrl); + + if(IS_ECSA_TYPE_STA(ecsa_ctrl)) + _phl_ecsa_state_change_sta(ecsa_ctrl); +} + +void +_phl_ecsa_cmd_abort_hdlr( + void* dispr, + void* priv, + bool abort +) +{ + struct phl_ecsa_ctrl_t *ecsa_ctrl = (struct phl_ecsa_ctrl_t *)priv; + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct rtw_phl_ecsa_ops *ops = &ecsa_ctrl->ops; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS; + void *d = phlcom_to_drvpriv(phl_com); + + _os_cancel_timer(d, &ecsa_ctrl->timer); + + /* ECSA AP abort handle */ + if(IS_ECSA_TYPE_AP(ecsa_ctrl) && + ecsa_ctrl->ecsa_param.flag != 0){ + ecsa_ctrl->state = ECSA_STATE_NONE; + CLEAR_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_BCN); + CLEAR_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_PROBERSP); + /* Update Bcn */ + if(ops->update_beacon) + ops->update_beacon(ops->priv, wifi_role); + } + + /* ECSA STA abort handle */ + if(IS_ECSA_TYPE_STA(ecsa_ctrl)){ + if(ecsa_ctrl->ecsa_param.mode == true) + _phl_ecsa_tx_resume(ecsa_ctrl); + + if(ops->ecsa_complete) + ops->ecsa_complete(ops->priv, wifi_role); + } + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_ECSA); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_DONE); + + if(abort) + attr.opt = MSG_OPT_SEND_IN_ABORT; + + pstatus = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + + if(pstatus != RTW_PHL_STATUS_SUCCESS) { + PHL_ERR("%s:[ECSA] dispr_send_msg failed (0x%X)\n", + __FUNCTION__, pstatus); + } +} + +enum phl_mdl_ret_code +_phl_ecsa_cmd_acquired( + void* dispr, + void* priv) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + enum phl_mdl_ret_code ret = MDL_RET_FAIL; + struct phl_ecsa_ctrl_t *ecsa_ctrl = (struct phl_ecsa_ctrl_t *)priv; + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + struct phl_msg msg = {0}; + struct phl_msg_attribute attr = {0}; + + SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_ECSA); + SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_ECSA_START); + + status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + goto exit; + } + + ret = MDL_RET_SUCCESS; +exit: + return ret; +} + +enum phl_mdl_ret_code +_phl_ecsa_cmd_abort( + void* dispr, + void* priv) +{ + _phl_ecsa_cmd_abort_hdlr(dispr, priv, true); + return MDL_RET_SUCCESS; +} + +enum phl_mdl_ret_code +_phl_ecsa_cmd_msg_hdlr( + void* dispr, + void* priv, + struct phl_msg* msg) +{ + struct phl_ecsa_ctrl_t *ecsa_ctrl = (struct phl_ecsa_ctrl_t *)priv; + struct rtw_wifi_role_t *wifi_role = ecsa_ctrl->role; + struct rtw_phl_com_t *phl_com = wifi_role->phl_com; + struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv; + void *d = phlcom_to_drvpriv(phl_com); + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct phl_msg nextmsg = {0}; + struct phl_msg_attribute attr = {0}; + struct rtw_phl_ecsa_ops *ops = &ecsa_ctrl->ops; + u32 current_time_ms = _os_get_cur_time_ms(); + struct rtw_bcn_info_cmn *bcn_cmn = &ecsa_ctrl->role->bcn_cmn; + u32 beacon_period_ms = bcn_cmn->bcn_interval * TU / 1000; + u8 countdown_n = 1; + struct rtw_chan_def chdef_to_switch = {0}; + + if(MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_ECSA) { + return MDL_RET_IGNORE; + } + + if(IS_MSG_FAIL(msg->msg_id)) { + _phl_ecsa_cmd_abort_hdlr(dispr, priv, false); + status = phl_disp_eng_free_token(phl_info, + wifi_role->hw_band, + &ecsa_ctrl->req_hdl); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_WARN("%s: Free token fail!\n", __FUNCTION__); + return MDL_RET_SUCCESS; + } + + SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_ECSA); + + switch(MSG_EVT_ID_FIELD(msg->msg_id)){ + case MSG_EVT_ECSA_START: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_START\n", __FUNCTION__); + if(IS_ECSA_TYPE_AP(ecsa_ctrl)){ + SET_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_BCN); + /* Update Bcn */ + if(ops->update_beacon) + ops->update_beacon(ops->priv, wifi_role); + } + + if(IS_ECSA_TYPE_STA(ecsa_ctrl) && + ecsa_ctrl->ecsa_param.mode == true){ + _phl_ecsa_tx_pause(ecsa_ctrl); + } + _phl_ecsa_calculate_next_timer(ecsa_ctrl); + break; + case MSG_EVT_ECSA_UPDATE_FIRST_BCN_DONE: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_UPDATE_FIRST_BCN_DONE\n", __FUNCTION__); + SET_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_PROBERSP); + _phl_ecsa_calculate_next_timer(ecsa_ctrl); + break; + case MSG_EVT_ECSA_COUNT_DOWN: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_COUNT_DOWN\n", __FUNCTION__); + + /* Count down mode of STA ECSA only calculate the switch time */ + if(IS_ECSA_TYPE_STA(ecsa_ctrl)){ + _phl_ecsa_calculate_next_timer(ecsa_ctrl); + break; + } + + /* Count down mode of AP ECSA calculate the update beacon time */ + if(ecsa_ctrl->expected_tbtt_ms > current_time_ms){ + countdown_n = 1; + } + else{ + /* + * There may be delay time during msg delivery, + * calulate the actual countdown value + */ + countdown_n = (u8)((current_time_ms-(ecsa_ctrl->expected_tbtt_ms))%beacon_period_ms+1); + + } + + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: count down %d\n", __FUNCTION__, countdown_n); + + if(ecsa_ctrl->ecsa_param.count > countdown_n){ + ecsa_ctrl->ecsa_param.count -= countdown_n; + /* Update Bcn */ + if(ops->update_beacon) + ops->update_beacon(ops->priv, wifi_role); + _phl_ecsa_calculate_next_timer(ecsa_ctrl); + } + else{ + /* + * If the countdown value is less than 1, + * we have to switch channel immediately + */ + ecsa_ctrl->ecsa_param.count = 0; + ecsa_ctrl->state = ECSA_STATE_SWITCH; + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_ECSA_SWITCH_START); + nextmsg.rsvd[0] = (u8*)ecsa_ctrl->role; + status = phl_disp_eng_send_msg(phl_info, + &nextmsg, + &attr, + NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: Send msg fail!\n", __FUNCTION__); + } + break; + case MSG_EVT_ECSA_SWITCH_START: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_SWITCH_START\n", __FUNCTION__); + + /* Update channel info */ + if(ops->update_chan_info){ + ops->update_chan_info(ops->priv, + wifi_role, + ecsa_ctrl->ecsa_param.new_chan_def); + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: update_chan_info done!\n", __FUNCTION__); + } + else{ + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: update_chan_info is NULL!\n", __FUNCTION__); + } + + /* AP mode ECSA should update beacon to remove ECSA IE and update the channel info */ + if(IS_ECSA_TYPE_AP(ecsa_ctrl)){ + CLEAR_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_BCN); + CLEAR_STATUS_FLAG(ecsa_ctrl->ecsa_param.flag, + ECSA_PARAM_FLAG_APPEND_PROBERSP); + /* Update Bcn */ + if(ops->update_beacon) + ops->update_beacon(ops->priv, wifi_role); + } + + /* + * We should use chandef of the chanctx to switch, + * the bw may not be same as the ECSA operating class + * because of the SCC mode with different bandwidth. + */ + if(wifi_role->chanctx != NULL){ + _os_mem_cpy(d, &chdef_to_switch, &(wifi_role->chanctx->chan_def), + sizeof(struct rtw_chan_def)); + if(wifi_role->chanctx->chan_def.chan != + ecsa_ctrl->ecsa_param.new_chan_def.chan) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: channel is not same as ECSA parameter!\n", + __FUNCTION__); + } + else{ + _os_mem_cpy(d, &chdef_to_switch, &(ecsa_ctrl->ecsa_param.new_chan_def), + sizeof(struct rtw_chan_def)); + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: chanctx of role is NULL use ECSA parameter!\n", + __FUNCTION__); + } + + /* Switch channel */ + phl_set_ch_bw(wifi_role, &chdef_to_switch, true); + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_ECSA_SWITCH_DONE); + nextmsg.rsvd[0] = (u8*)ecsa_ctrl->role; + status = phl_disp_eng_send_msg(phl_info, + &nextmsg, + &attr, + NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: Send msg fail!\n", __FUNCTION__); + break; + case MSG_EVT_ECSA_SWITCH_DONE: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_SWITCH_DONE\n", __FUNCTION__); + if(IS_ECSA_TYPE_STA(ecsa_ctrl) && + ecsa_ctrl->ecsa_param.mode == true){ + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_ECSA_CHECK_TX_RESUME); + status = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: Send msg fail!\n", __FUNCTION__); + break; + } + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_ECSA_DONE); + status = phl_disp_eng_send_msg(phl_info, + &nextmsg, + &attr, + NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: Send msg fail!\n", __FUNCTION__); + break; + case MSG_EVT_ECSA_CHECK_TX_RESUME: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_CHECK_TX_RESUME\n", __FUNCTION__); + if(IS_ECSA_TYPE_STA(ecsa_ctrl) && + ecsa_ctrl->ecsa_param.mode == true){ + /* + * TODO: If driver support DFS-slave with radar + * detection, ECSA should tx un-pause directly + * and the tx pause should be handled by DFS-slave. + */ + if(ops->check_tx_resume_allow){ + if(!ops->check_tx_resume_allow(ops->priv, wifi_role)){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: Keep Tx pause...\n", __FUNCTION__); + _phl_ecsa_calculate_next_timer(ecsa_ctrl); + break; + } + } + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: Tx resume!\n", __FUNCTION__); + _phl_ecsa_tx_resume(ecsa_ctrl); + } + + SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_ECSA_DONE); + status = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: Send msg fail!\n", __FUNCTION__); + + break; + case MSG_EVT_ECSA_DONE: + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, + "%s: MSG_EVT_ECSA_DONE\n", __FUNCTION__); + ecsa_ctrl->state = ECSA_STATE_NONE; + + if(ops->ecsa_complete){ + ops->ecsa_complete(ops->priv, wifi_role); + } + else{ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: ecsa_complete is NULL!\n", __FUNCTION__); + } + + status = phl_disp_eng_free_token(phl_info, + wifi_role->hw_band, + &ecsa_ctrl->req_hdl); + if(status != RTW_PHL_STATUS_SUCCESS) + PHL_WARN("%s: Free token fail!\n", __FUNCTION__); + break; + default: + break; + } + return ret; +} + +enum phl_mdl_ret_code +_phl_ecsa_cmd_set_info( + void* dispr, + void* priv, + struct phl_module_op_info* info) +{ + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + return ret; +} + +enum phl_mdl_ret_code +_phl_ecsa_cmd_query_info( + void* dispr, + void* priv, + struct phl_module_op_info* info) +{ + struct phl_ecsa_ctrl_t *ecsa_ctrl = (struct phl_ecsa_ctrl_t *)priv; + enum phl_mdl_ret_code ret = MDL_RET_IGNORE; + /* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */ + + switch(info->op_code) { + case FG_REQ_OP_GET_ROLE: + info->outbuf = (u8*)ecsa_ctrl->role; + ret = MDL_RET_SUCCESS; + break; + default: + break; + } + + return ret; +} + +enum rtw_phl_status +rtw_phl_ecsa_cmd_request( + void *phl, + struct rtw_wifi_role_t *role + ) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + struct phl_cmd_token_req req={0}; + + if(ecsa_ctrl == NULL) + goto exit; + + /* Fill foreground command request */ + req.module_id= PHL_FG_MDL_ECSA; + req.priv = ecsa_ctrl; + req.role = role; + + req.acquired = _phl_ecsa_cmd_acquired; + req.abort = _phl_ecsa_cmd_abort; + req.msg_hdlr = _phl_ecsa_cmd_msg_hdlr; + req.set_info = _phl_ecsa_cmd_set_info; + req.query_info = _phl_ecsa_cmd_query_info; + + status = phl_disp_eng_add_token_req(phl, role->hw_band, &req, + &ecsa_ctrl->req_hdl); + if((status != RTW_PHL_STATUS_SUCCESS) && + (status != RTW_PHL_STATUS_PENDING)) + goto exit; + + status = RTW_PHL_STATUS_SUCCESS; + +exit: + return status; +} + +enum rtw_phl_status +rtw_phl_ecsa_start( + void *phl, + struct rtw_wifi_role_t *role, + struct rtw_phl_ecsa_param *param + ) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *d = phlcom_to_drvpriv(phl_info->phl_com); + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + struct rtw_phl_ecsa_param *ecsa_param = &(ecsa_ctrl->ecsa_param); + + if(ecsa_ctrl == NULL) + return RTW_PHL_STATUS_FAILURE; + if(ecsa_ctrl->state != ECSA_STATE_NONE){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, "%s: ECSA already started!\n", + __FUNCTION__); + return RTW_PHL_STATUS_FAILURE; + } + + ecsa_ctrl->role = role; + _os_mem_cpy(d, ecsa_param, param, sizeof(struct rtw_phl_ecsa_param)); + _phl_ecsa_dump_param(ecsa_param); + ecsa_ctrl->state = ECSA_STATE_WAIT_DELAY; + PHL_TRACE(COMP_PHL_ECSA, _PHL_INFO_, "%s: ECSA start after %dms !\n", + __FUNCTION__, ecsa_ctrl->ecsa_param.delay_start_ms); + _os_set_timer(d, &ecsa_ctrl->timer, ecsa_ctrl->ecsa_param.delay_start_ms); + + return RTW_PHL_STATUS_SUCCESS; +} + +enum rtw_phl_status +rtw_phl_ecsa_cancel( + void *phl, + struct rtw_wifi_role_t *role + ) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + void *d = phlcom_to_drvpriv(phl_info->phl_com); + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + + if(ecsa_ctrl == NULL){ + status = RTW_PHL_STATUS_FAILURE; + goto exit; + } + + if(ecsa_ctrl->state == ECSA_STATE_NONE) + goto exit; + + _os_cancel_timer(d, &ecsa_ctrl->timer); + + _os_spinlock(d, &(ecsa_ctrl->lock), _bh, NULL); + if(ecsa_ctrl->state > ECSA_STATE_WAIT_DELAY){ + status = phl_disp_eng_cancel_token_req(phl_info, + role->hw_band, + &ecsa_ctrl->req_hdl); + + if(status != RTW_PHL_STATUS_SUCCESS){ + PHL_TRACE(COMP_PHL_ECSA, _PHL_WARNING_, + "%s: ECSA cancel req fail!\n", __FUNCTION__); + } + + } + else{ + ecsa_ctrl->state = ECSA_STATE_NONE; + } + _os_spinunlock(d, &(ecsa_ctrl->lock), _bh, NULL); + +exit: + return status; +} + +enum rtw_phl_status +rtw_phl_ecsa_get_param( + void *phl, + struct rtw_phl_ecsa_param **param + ) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + + if(ecsa_ctrl == NULL) + goto exit; + + *param = &ecsa_ctrl->ecsa_param; +exit: + return status; +} + +enum rtw_phl_status +phl_ecsa_ctrl_init( + struct phl_info_t *phl_info + ) +{ + void *drv_priv = phl_to_drvpriv(phl_info); + struct phl_ecsa_ctrl_t *ecsa_ctrl = NULL; + + ecsa_ctrl = _os_mem_alloc(drv_priv, sizeof(struct phl_ecsa_ctrl_t)); + if (ecsa_ctrl == NULL) { + phl_info->ecsa_ctrl = NULL; + return RTW_PHL_STATUS_FAILURE; + } + + phl_info->ecsa_ctrl = ecsa_ctrl; + + /* set default value */ + ecsa_ctrl->state = ECSA_STATE_NONE; + ecsa_ctrl->phl_com = phl_info->phl_com; + ecsa_ctrl->role = NULL; + ecsa_ctrl->expected_tbtt_ms = 0; + + _os_init_timer(drv_priv, &ecsa_ctrl->timer, _phl_ecsa_timer_callback, + ecsa_ctrl, "phl_ecsa_timer"); + + _os_spinlock_init(drv_priv, &(ecsa_ctrl->lock)); + + return RTW_PHL_STATUS_SUCCESS; +} + +void +phl_ecsa_ctrl_deinit( + struct phl_info_t *phl_info + ) +{ + void *drv_priv = phl_to_drvpriv(phl_info); + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)(phl_info->ecsa_ctrl); + + if (ecsa_ctrl == NULL) + return; + _os_spinlock_free(drv_priv, &(ecsa_ctrl->lock)); + _os_release_timer(drv_priv, &ecsa_ctrl->timer); + _os_mem_free(drv_priv, ecsa_ctrl, sizeof(struct phl_ecsa_ctrl_t)); + + phl_info->ecsa_ctrl = NULL; +} + +enum rtw_phl_status +rtw_phl_ecsa_init_ops( + void *phl, + struct rtw_phl_ecsa_ops *ops) +{ + enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE; + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + + if(ecsa_ctrl == NULL) + goto exit; + + ecsa_ctrl->ops.priv = ops->priv; + ecsa_ctrl->ops.update_beacon = ops->update_beacon; + ecsa_ctrl->ops.update_chan_info = ops->update_chan_info; + ecsa_ctrl->ops.check_ecsa_allow = ops->check_ecsa_allow; + ecsa_ctrl->ops.ecsa_complete = ops->ecsa_complete; + ecsa_ctrl->ops.check_tx_resume_allow = ops->check_tx_resume_allow; + status = RTW_PHL_STATUS_SUCCESS; +exit: + return status; +} + +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION +void +rtw_phl_ecsa_extend_option_hdlr( + u32 extend_option, + struct rtw_phl_ecsa_param *param +) +{ + if ((extend_option & ECSA_EX_OPTION_FORCE_BW20) && + (param->new_chan_def.bw != CHANNEL_WIDTH_20)) { + /* force 20M mode, set attributes accordingly */ + param->new_chan_def.bw = CHANNEL_WIDTH_20; + param->new_chan_def.center_ch = param->new_chan_def.chan; + param->new_chan_def.offset = CHAN_OFFSET_NO_EXT; + param->op_class = rtw_phl_get_operating_class(param->new_chan_def); + } +} +#endif + +bool +rtw_phl_ecsa_check_allow( + void *phl, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def, + enum phl_ecsa_start_reason reason, +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION + u32 *extend_option, +#endif + u32 *delay_start_ms +) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct phl_ecsa_ctrl_t *ecsa_ctrl = + (struct phl_ecsa_ctrl_t *)phl_info->ecsa_ctrl; + struct rtw_phl_ecsa_ops *ops = &(ecsa_ctrl->ops); + bool ecsa_allow = false; + + if(ops->check_ecsa_allow) + ecsa_allow = ops->check_ecsa_allow(ops->priv, + role, + chan_def, + reason, +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION + extend_option, +#endif + delay_start_ms); + return ecsa_allow; +} +#endif /* CONFIG_PHL_ECSA */ \ No newline at end of file diff --git a/phl/phl_ecsa.h b/phl/phl_ecsa.h new file mode 100644 index 0000000..ecc5b2b --- /dev/null +++ b/phl/phl_ecsa.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_ECSA_H_ +#define _PHL_ECSA_H_ + +#define ECSA_UPDATE_BCN_BEFORE_TBTT 25 /* unit: TU */ +#define ECSA_UPDATE_BCN_BEFORE_TBTT_US (ECSA_UPDATE_BCN_BEFORE_TBTT * TU) + +#define ECSA_DEFAULT_CHANNEL_SWITCH_COUNT 10 +#define ECSA_SWITCH_TIME_AFTER_LAST_COUNT_DOWN (10 * TU) + +#define IS_ECSA_TYPE_AP(_ecsa_ctrl) (_ecsa_ctrl->ecsa_param.ecsa_type == ECSA_TYPE_AP) +#define IS_ECSA_TYPE_STA(_ecsa_ctrl) (_ecsa_ctrl->ecsa_param.ecsa_type == ECSA_TYPE_STA) + +enum phl_ecsa_state{ + ECSA_STATE_NONE = 0, + ECSA_STATE_WAIT_DELAY = 1, + ECSA_STATE_START, + ECSA_STATE_UPDATE_FIRST_BCN_DONE, + ECSA_STATE_COUNT_DOWN, + ECSA_STATE_SWITCH, + ECSA_STATE_DONE +}; + +struct phl_ecsa_ctrl_t{ + enum phl_ecsa_state state; + struct rtw_phl_com_t *phl_com; + struct rtw_wifi_role_t *role; + struct rtw_phl_ecsa_param ecsa_param; + struct rtw_phl_ecsa_ops ops; + _os_timer timer; + _os_lock lock; + u32 expected_tbtt_ms; + u32 req_hdl; +}; + +#ifdef CONFIG_PHL_ECSA +enum rtw_phl_status phl_ecsa_ctrl_init(struct phl_info_t *phl_info); +void phl_ecsa_ctrl_deinit(struct phl_info_t *phl_info); +#else +#define phl_ecsa_ctrl_init(_phl_info) RTW_PHL_STATUS_SUCCESS +#define phl_ecsa_ctrl_deinit(_phl_info) +#endif /* CONFIG_PHL_ECSA */ + +#endif /*_PHL_ECSA_H_*/ diff --git a/phl/phl_ecsa_export.h b/phl/phl_ecsa_export.h new file mode 100644 index 0000000..61c5b54 --- /dev/null +++ b/phl/phl_ecsa_export.h @@ -0,0 +1,150 @@ +/****************************************************************************** + * + * Copyright(c) 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_ECSA_EXPORT_H_ +#define _PHL_ECSA_EXPORT_H_ + +#define CHANNEL_SWITCH_MODE_NORMAL 0 +#define CHANNEL_SWITCH_MODE_STOP_TX 1 + +enum phl_ecsa_type{ + ECSA_TYPE_NONE = 0, + ECSA_TYPE_AP = 1, + ECSA_TYPE_STA = 2 +}; + +enum phl_ecsa_param_flag{ + ECSA_PARAM_FLAG_APPEND_BCN = BIT0, + ECSA_PARAM_FLAG_APPEND_PROBERSP = BIT1, +}; + +enum phl_ecsa_start_reason{ + ECSA_START_MCC_24G_TO_24G = 0, + ECSA_START_MCC_5G_TO_5G = 1, + ECSA_START_MCC_24G_TO_5G = 2, + ECSA_START_MCC_5G_TO_24G = 3, + ECSA_START_CORE_TRIGGER = 4, + ECSA_START_UNKNOWN +}; + +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION +enum phl_ecsa_extend_option{ + ECSA_EX_OPTION_FORCE_BW20 = BIT0, +}; +#endif + +struct rtw_phl_ecsa_param{ + enum phl_ecsa_type ecsa_type; + u8 flag; + u8 mode; /* CHANNEL_SWITCH_MODE_NORMAL or CHANNEL_SWITCH_MODE_STOP_TX */ + u8 op_class; + u8 ch; + u8 count; + u32 delay_start_ms; + struct rtw_chan_def new_chan_def; +}; + +/* + * priv: ops private, define by core layer + * update_beacon: Notify core to construct and update beacon + * update_chan_info: Notify core to update AP mode channel information + * check_ecsa_allow: Provide reason and ask core if ecsa is allowed or not, + * core can provide a delay time(ms) to delay start ECSA + * ecsa_complete: Notify core to reset csa related Information + * check_tx_resume_allow: Check core is allowed to resume tx paused by csa mode == 1 + */ +struct rtw_phl_ecsa_ops{ + void *priv; + void (*update_beacon)(void *priv, struct rtw_wifi_role_t *role); + void (*update_chan_info)(void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def); + bool (*check_ecsa_allow)(void *priv, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def, + enum phl_ecsa_start_reason reason, +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION + u32 *extend_option, +#endif + u32 *delay_start_ms); + void (*ecsa_complete)(void *priv, struct rtw_wifi_role_t *role); + bool (*check_tx_resume_allow)(void *priv, struct rtw_wifi_role_t *role); +}; + +#ifdef CONFIG_PHL_ECSA +enum rtw_phl_status +rtw_phl_ecsa_init_ops( + void *phl, + struct rtw_phl_ecsa_ops *ops + ); + +enum rtw_phl_status +rtw_phl_ecsa_cmd_request( + void *phl, + struct rtw_wifi_role_t *role + ); + +enum rtw_phl_status +rtw_phl_ecsa_start( + void *phl, + struct rtw_wifi_role_t *role, + struct rtw_phl_ecsa_param *param + ); + +enum rtw_phl_status +rtw_phl_ecsa_cancel( + void *phl, + struct rtw_wifi_role_t *role + ); + +enum rtw_phl_status +rtw_phl_ecsa_get_param( + void *phl, + struct rtw_phl_ecsa_param **param + ); + +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION +void +rtw_phl_ecsa_extend_option_hdlr( + u32 extend_option, + struct rtw_phl_ecsa_param *param + ); +#endif + +bool +rtw_phl_ecsa_check_allow( + void *phl, + struct rtw_wifi_role_t *role, + struct rtw_chan_def chan_def, + enum phl_ecsa_start_reason reason, +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION + u32 *extend_option, +#endif + u32 *delay_start_ms + ); +#else +#define rtw_phl_ecsa_init_ops(_phl, _ops) RTW_PHL_STATUS_SUCCESS +#define rtw_phl_ecsa_cmd_request(_phl, _role) RTW_PHL_STATUS_SUCCESS +#define rtw_phl_ecsa_start(_phl, _role, _param) RTW_PHL_STATUS_SUCCESS +#define rtw_phl_ecsa_cancel(_phl, _role) RTW_PHL_STATUS_SUCCESS +#define rtw_phl_ecsa_get_param(_phl, _param) RTW_PHL_STATUS_SUCCESS +#ifdef CONFIG_PHL_ECSA_EXTEND_OPTION +#define rtw_phl_ecsa_extend_option_hdlr(_extend_option, _param) +#define rtw_phl_ecsa_check_allow(_phl, _role, _chan_def, _reason, _extend_option, _delay_start_ms) false +#else +#define rtw_phl_ecsa_check_allow(_phl, _role, _chan_def, _reason, _delay_start_ms) false +#endif +#endif + +#endif /*_PHL_ECSA_EXPORT_H_*/ diff --git a/phl/phl_ext_tx_pwr_lmt.c b/phl/phl_ext_tx_pwr_lmt.c new file mode 100644 index 0000000..940c945 --- /dev/null +++ b/phl/phl_ext_tx_pwr_lmt.c @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _PHL_EXT_TX_PWR_LMT_C_ +#include "phl_headers.h" + +/** + * The function to update current TX power limit value to HW register + * @phl: see struct phl_info_t + * @hw_band: 0x0: band0, 0x1: band1 + * + */ +enum rtw_phl_status +rtw_phl_set_power_lmt(void *phl, u8 hw_band) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE; + + if (rtw_hal_set_power_lmt(phl_info->hal, hw_band)==RTW_HAL_STATUS_SUCCESS) + phl_status = RTW_PHL_STATUS_SUCCESS; + + return phl_status; +} + +/** + * The function to get TX power limit value with specific parameters + * @phl: see struct phl_info_t + * @hw_band: 0x0: band0, 0x1: band1 + * @rate: data rate + * @bandwidth: banddwidth + * @beamforming: 0: TX w/o BF, 1: TX w/ BF + * @tx_num: tx number, 0: 1TX, 1: 2TX + * @channel: center channel + * + */ +s8 rtw_phl_get_power_limit(void *phl, u8 hw_band, + u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + + return rtw_hal_rf_get_power_limit(phl_info->hal, hw_band, rate, + bandwidth, beamforming, tx_num, channel); +} + +/** + * The function to update user defined extended tx power limit to halrf + * @phl: see struct phl_info_t + * @hw_band: 0x0: band0, 0x1: band1 + * @ext_pwr_lmt_info: table of extended tx power limit value + * + * Note, + * This function will enable extended tx power limit mechanism. + * After enabled this mechanism, halrf will use + * min(original tx power limit, extended tx power limit) to be + * final tx power limit value. + * + */ +void +rtw_phl_enable_ext_pwr_lmt(void *phl, u8 hw_band, + struct rtw_phl_ext_pwr_lmt_info *ext_pwr_lmt_info) +{ + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct rtw_tpu_ext_pwr_lmt_info tpu_ext_pwr_lmt_info = {0}; + u8 i; + + for (i = 0; i < HAL_MAX_PATH; i++) { + tpu_ext_pwr_lmt_info.ext_pwr_lmt_2_4g[i] + = ext_pwr_lmt_info->ext_pwr_lmt_2_4g[i]; + + tpu_ext_pwr_lmt_info.ext_pwr_lmt_5g_band1[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band1[i]; + tpu_ext_pwr_lmt_info.ext_pwr_lmt_5g_band2[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band2[i]; + tpu_ext_pwr_lmt_info.ext_pwr_lmt_5g_band3[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band3[i]; + tpu_ext_pwr_lmt_info.ext_pwr_lmt_5g_band4[i] + = ext_pwr_lmt_info->ext_pwr_lmt_5g_band4[i]; + } + + rtw_hal_enable_ext_pwr_lmt(phl_info->hal, hw_band, + &tpu_ext_pwr_lmt_info); +} + + diff --git a/phl/phl_ext_tx_pwr_lmt_def.h b/phl/phl_ext_tx_pwr_lmt_def.h new file mode 100644 index 0000000..fd82022 --- /dev/null +++ b/phl/phl_ext_tx_pwr_lmt_def.h @@ -0,0 +1,29 @@ + +/****************************************************************************** + * + * Copyright(c) 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _PHL_EXT_TX_PWR_LMT_DEF_H_ +#define _PHL_EXT_TX_PWR_LMT_DEF_H_ + + +struct rtw_phl_ext_pwr_lmt_info { /* external tx power limit information */ + s8 ext_pwr_lmt_2_4g[RTW_PHL_MAX_RF_PATH]; + s8 ext_pwr_lmt_5g_band1[RTW_PHL_MAX_RF_PATH]; /*CH36 ~ CH48*/ + s8 ext_pwr_lmt_5g_band2[RTW_PHL_MAX_RF_PATH]; /*CH52 ~ CH64*/ + s8 ext_pwr_lmt_5g_band3[RTW_PHL_MAX_RF_PATH]; /*CH100 ~ CH144*/ + s8 ext_pwr_lmt_5g_band4[RTW_PHL_MAX_RF_PATH]; /*CH149 ~ CH165*/ +}; + + +#endif /*_PHL_EXT_TX_PWR_LMT_DEF_H_*/ diff --git a/phl/phl_fsm.c b/phl/phl_fsm.c new file mode 100644 index 0000000..7b9c416 --- /dev/null +++ b/phl/phl_fsm.c @@ -0,0 +1,2197 @@ +/****************************************************************************** + * + * Copyright(c) 2019 - 2020 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: vincent_fann@realtek.com + * + *****************************************************************************/ +#include "phl_headers.h" + +#ifdef CONFIG_FSM + +#define PHL_DEBUG_FSM + +#define CLOCK_NUM 10 +#define CLOCK_UNIT 10 +#define IS_CLK_OFF(clk) (clk->remain < 0) /* Negative value means disabled */ +#define IS_CLK_ON(clk) (clk->remain >= 0) +#define IS_CLK_EXP(clk) (clk->remain < (CLOCK_UNIT >> 1)) /* expire */ + +#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y)) +#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y)) +#define pstr(s) (s +_os_strlen((u8 *)s)) +#define lstr(s, l) (size_t)(l - _os_strlen((u8 *)s)) + +#define FSM_INITIAL_STATE 0 + +#ifdef FSM_DBG_MEM_OVERWRITE +void *fsm_kmalloc(u32 sz) +{ + char *ptr; + + ptr = kmalloc(sz+4, GFP_KERNEL); + memset(ptr+sz, 0xff, 4); + PHL_INFO("+AA %p %d\n", ptr, sz); + return ptr; +} + +void fsm_kfree(void *ptr, u32 sz) +{ + u32 ptn = 0xffffffff; + u32 *p = (u32 *)(ptr+sz); + + PHL_INFO("-AA %p %d", ptr, sz); + if ((*p&ptn) != ptn) { + PHL_ERR("- %p %d", ptr, sz); + PHL_ERR("OVER WRITE %x\n", ptn); + } + kfree(ptr); +} +#define _os_kmem_alloc(a, b) fsm_kmalloc(b) +#define _os_kmem_free(a, b, c) fsm_kfree(b, c) +#endif + +struct fsm_event_ent int_event_tbl[] = { + EV_ENT(FSM_INT_EV_MASK), + EV_ENT(FSM_EV_CANCEL), + EV_ENT(FSM_EV_TIMER_EXPIRE), + EV_ENT(FSM_EV_END), + + EV_ENT(FSM_EV_SWITCH_IN), + EV_ENT(FSM_EV_SWITCH_OUT), + EV_ENT(FSM_EV_STATE_IN), + EV_ENT(FSM_EV_STATE_OUT), + + /* Global event for announcement */ + /* BE CAUREFUL the EVENT ORDER + * please also modify enum FSM_EV_ID{} in phl_fsm.h + */ + EV_ENT(FSM_GB_SCAN_START), + EV_ENT(FSM_GB_SCAN_COMPLETE), + + EV_ENT(FSM_EV_MAX) +}; + +/* + * FSM status + */ +enum FSM_STATUS { + FSM_STATUS_NONE, /* default value */ + + FSM_STATUS_INITIALIZED, /* insert module ok, + * all mem/queue/timer were allocated + * has a pending thread + * phl_fsm_new_fsm() + * phl_fsm_stop_fsm() + */ + + FSM_STATUS_READY, /* interface up, schedule thread, timer. + * Does NOT receive message + * phl_fsm_start_fsm() + */ + + FSM_STATUS_ENABLE, /* Normal running; Reack msg + * Internal use + * fsm_enable() + */ + + FSM_STATUS_DISABLE, /* Does NOT reack msg, able to receiving msg + * Internal use + * fsm_disable() + */ +}; + +/* @obj: obj that will be infomred to when time's up + * @counter: clock time period + * @event: event that will delivered when time's up + * @end: end time + * @pause: stop countdown + */ +struct fsm_clock { + u16 event; + void *priv; + u8 pause; + u32 start; + u32 end; + int remain; /* ms */ +}; + +struct fsm_queue { + struct list_head q; + _os_lock lock; +}; + +struct fsm_main { + struct list_head list; + char name[FSM_NAME_LEN]; + u8 status; + u8 obj_cnt; + u8 oid_seq; /* starts from 1 */ + u8 en_clock_num; + _os_lock clock_lock; + + _os_thread thread; + _os_timer fsm_timer; /* unit in ms */ + + struct fsm_root *root; + struct fsm_queue obj_queue; + struct fsm_queue msg_queue; + struct fsm_queue evt_queue; + _os_sema msg_ready; + bool should_stop; + + /* extra custom queue; for fsm private */ + struct fsm_queue ext_queue; + + struct phl_info_t *phl_info; /* phl_info */ + struct rtw_phl_fsm_tb tb; +}; + +/* + * @event: event id + * @param: additional param of the event + * @param_sz: param size + */ +struct fsm_evt { + struct list_head list; + u16 event; /* event id */ + struct fsm_main *fsm; + + void *param; + int param_sz; +}; + +/* @obj_id: object id + * @state: current state + * @prive: object's private date + */ +struct fsm_obj { + struct list_head list; + u8 oid; + u8 state; + char name[FSM_NAME_LEN]; + struct fsm_clock clock[CLOCK_NUM]; + struct fsm_main *fsm; + + void *custom_obj; + int custom_len; /* custom obj length */ + + /* Global event use */ + struct gbl_param my_gbl_req; /* my announcemnt to all */ + struct fsm_queue gbl_queue; /* all received global events */ + u16 gbl_q_len; /* number of received global event */ +}; + +/* Main structure to handle all standalone fsm */ +struct fsm_root { + _os_thread thread; + struct list_head list; + struct fsm_queue q_share_thd; + struct fsm_queue q_alone_thd; + struct phl_info_t *phl_info; + u8 gbl_seq; + + _os_sema msg_ready; + + u32 status; /* refer to enum FSM_ROOT_STATUS_FLAGS */ +}; + +/* Static function porto type */ +static int fsm_handler(struct fsm_main *fsm); +static char *fsm_state_name(struct fsm_main *fsm, u8 state); +static u8 fsm_get_evt_level(struct fsm_main *fsm, u16 event); + +static void fsm_status_set(struct fsm_main *fsm, enum FSM_STATUS status) +{ + fsm->status = status; +} + +static enum FSM_STATUS fsm_status(struct fsm_main *fsm) +{ + return fsm->status; +} + +/* unit ms */ +u32 phl_fsm_time_pass(u32 start) +{ + u32 now = _os_get_cur_time_ms(); + u32 pass; + + if (start <= now) + pass = now - start; + else + pass = 0xffffffff - start + now; + + return pass; +} + +u32 phl_fsm_time_left(u32 start, u32 end) +{ + u32 total, pass; + int left = 0; + + pass = phl_fsm_time_pass(start); + + if (end >= start) + total = end - start; + else + total = 0xffffffff - start + end; + + left = total - pass; + + if (left < 0) + left = 0; + + return (u32)left; +} + +#if 0 +static struct fsm_main *fsm_dequeue_fsm(struct fsm_root *root, u8 fsm_mode) +{ + void *d = phl_to_drvpriv(root->phl_info); + struct fsm_main *fsm; + struct fsm_queue *queue = (fsm_mode == FSM_ALONE_THREAD) ? + (&root->q_alone_thd) : (&root->q_share_thd); + + if (list_empty(&queue->q)) + return NULL; + + _os_spinlock(d, &queue->lock, _bh, NULL); + fsm = list_first_entry(&queue->q, struct fsm_main, list); + list_del(&fsm->list); + _os_spinunlock(d, &queue->lock, _bh, NULL); + return fsm; +} + +static struct fsm_obj *fsm_dequeue_obj(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj; + + if (list_empty(&fsm->obj_queue.q)) + return NULL; + + _os_spinlock(d, &fsm->obj_queue.lock, _bh, NULL); + obj = list_first_entry(&fsm->obj_queue.q, struct fsm_obj, list); + list_del(&obj->list); + _os_spinunlock(d, &fsm->obj_queue.lock, _bh, NULL); + return obj; +} +#endif + +static struct fsm_msg *fsm_dequeue_msg(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_msg *msg; + + if (list_empty(&fsm->msg_queue.q)) + return NULL; + + _os_spinlock(d, &fsm->msg_queue.lock, _bh, NULL); + msg = list_first_entry(&fsm->msg_queue.q, struct fsm_msg, list); + list_del(&msg->list); + _os_spinunlock(d, &fsm->msg_queue.lock, _bh, NULL); + return msg; +} + +static struct fsm_evt *fsm_dequeue_evt(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_evt *evt; + + if (list_empty(&fsm->evt_queue.q)) + return NULL; + + _os_spinlock(d, &fsm->evt_queue.lock, _bh, NULL); + evt = list_first_entry(&fsm->evt_queue.q, struct fsm_evt, list); + list_del(&evt->list); + _os_spinunlock(d, &fsm->evt_queue.lock, _bh, NULL); + return evt; +} + +/* For EXTERNAL application to enqueue message to extra queue (expose) + * + * @fsm: fsm that object belonged to + * @msg: message to be enqueued + * @to_head: enqueue message to the head + */ +int phl_fsm_enqueue_ext(struct fsm_main *fsm, struct fsm_msg *msg, u8 to_head) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_queue *queue = &fsm->ext_queue; + + _os_spinlock(d, &queue->lock, _bh, NULL); + if (to_head) + list_add(&msg->list, &queue->q); + else + list_add_tail(&msg->list, &queue->q); + _os_spinunlock(d, &queue->lock, _bh, NULL); + + return 0; +} + +/* For EXTERNAL application to dequeue message from extra queue (expose) + * + * @fsm: fsm that object belonged to + */ +struct fsm_msg *phl_fsm_dequeue_ext(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_msg *msg; + + if (list_empty(&fsm->ext_queue.q)) + return NULL; + + _os_spinlock(d, &fsm->ext_queue.lock, _bh, NULL); + msg = list_first_entry(&fsm->ext_queue.q, struct fsm_msg, list); + list_del(&msg->list); + _os_spinunlock(d, &fsm->ext_queue.lock, _bh, NULL); + return msg; +} + +/* For EXTERNAL application to dequeue message from extra queue (expose) + * + * @fsm: fsm that object belonged to + */ +int phl_fsm_is_ext_queue_empty(struct fsm_main *fsm) +{ + return list_empty(&fsm->ext_queue.q); +} + +static int fsm_new_oid(struct fsm_main *fsm) +{ + u8 oid = fsm->oid_seq++; + + if (fsm->oid_seq == 0xFF) { + PHL_WARN("%s: reach MAX object ID 0x%x\n", + fsm->name, oid); + } + return oid; +} + +static int fsm_enqueue_list(void *d, struct fsm_main *fsm, + struct fsm_queue *queue, struct list_head *list) +{ + _os_spinlock(d, &queue->lock, _bh, NULL); + list_add_tail(list, &queue->q); + _os_spinunlock(d, &queue->lock, _bh, NULL); + return 0; +} + +static enum fsm_run_rtn fsm_state_run(struct fsm_obj *obj, + u16 event, void *param) +{ + struct fsm_main *fsm = obj->fsm; + + /* TODO protect incorrect event */ + + FSM_EV_MSG(fsm, fsm_get_evt_level(fsm, event), + "%s-%d %-18s %s\n", fsm->name, obj->oid, + fsm_state_name(fsm, obj->state), phl_fsm_evt_name(obj, event)); + + return fsm->tb.state_tbl[obj->state].fsm_func(obj->custom_obj, + event, param); +} + +static void fsm_remove_all_queuing_msg(struct fsm_main *fsm) +{ + struct fsm_msg *msg; + struct fsm_evt *evt; + void *d = phl_to_drvpriv(fsm->phl_info); + + /* go through msg queue and free everything */ + while ((msg = fsm_dequeue_msg(fsm)) != NULL) { + if (msg->param) + _os_kmem_free(d, (void *)msg->param, msg->param_sz); + _os_kmem_free(d, (void *)msg, sizeof(*msg)); + } + + /* go through event queue and free everything */ + while ((evt = fsm_dequeue_evt(fsm)) != NULL) { + if (evt->param) + _os_kmem_free(d, (void *)evt->param, evt->param_sz); + _os_kmem_free(d, (void *)evt, sizeof(*evt)); + } + + /* go through ext queue and free everything */ + while ((msg = phl_fsm_dequeue_ext(fsm)) != NULL) { + if (msg->param) + _os_kmem_free(d, (void *)msg->param, msg->param_sz); + _os_kmem_free(d, (void *)msg, sizeof(*msg)); + } +} + +static int fsm_cancel_all_running_obj(struct fsm_main *fsm) +{ + struct fsm_obj *obj; + + phl_list_for_loop(obj, struct fsm_obj, &fsm->obj_queue.q, list) { + phl_fsm_gen_msg(fsm->phl_info, obj, NULL, 0, FSM_EV_CANCEL); + } + + return 0; +} + +u8 phl_fsm_dbg_level(struct fsm_main *fsm, u8 level) +{ + if (fsm->tb.dbg_level >= level) + return fsm->tb.dbg_level; + + return 0; +} + +u8 phl_fsm_evt_level(struct fsm_main *fsm, u8 level) +{ + if (fsm->tb.evt_level >= level) + return fsm->tb.evt_level; + + return 0; +} + +static u8 fsm_get_evt_level(struct fsm_main *fsm, u16 event) +{ + u16 ev; + + /* fsm internal event */ + if (event & FSM_INT_EV_MASK) { + ev = (u8)(event & ~(FSM_EV_MASK)); + return int_event_tbl[ev].evt_level; + } + + if (event == FSM_EV_UNKNOWN) + return FSM_DBG_INFO; + + if (event > fsm->tb.max_event) + return FSM_DBG_INFO; + + /* user event */ + return fsm->tb.evt_tbl[event].evt_level; +} + +static void fsm_init_queue(void *d, struct fsm_queue *queue) +{ + INIT_LIST_HEAD(&queue->q); + _os_spinlock_init(d, &queue->lock); +} + +static void fsm_deinit_queue(void *d, struct fsm_queue *queue) +{ + _os_spinlock_free(d, &queue->lock); +} + +/* For External obj to check sould stop status + * + * @fsm: fsm to get state + */ +bool phl_fsm_should_stop(struct fsm_main *fsm) +{ + return fsm->should_stop; +} + +int fsm_thread_share(void *param) +{ + struct fsm_main *fsm, *fsm_t; + struct fsm_root *root = (struct fsm_root *)param; + void *d = phl_to_drvpriv(root->phl_info); + + while (1) { + + _os_sema_down(d, &root->msg_ready); + if (_os_thread_check_stop(d, &(root->thread))) + break; + phl_list_for_loop_safe(fsm, fsm_t, + struct fsm_main, &root->q_share_thd.q, list) { + if (fsm_status(fsm) == FSM_STATUS_ENABLE) + fsm_handler(fsm); + } + } + _os_thread_wait_stop(d, &root->thread); + PHL_INFO("fsm: [root] thread down\n"); + + return 0; +} + +int fsm_thread_alone(void *param) +{ + struct fsm_main *fsm = (struct fsm_main *)param; + void *d = phl_to_drvpriv(fsm->phl_info); + + while (1) { + + _os_sema_down(d, &fsm->msg_ready); + if (_os_thread_check_stop(d, &(fsm->thread))) + break; + + if (fsm_status(fsm) == FSM_STATUS_ENABLE) + fsm_handler(fsm); + } + _os_thread_wait_stop(d, &fsm->thread); + FSM_INFO(fsm, "fsm: [%s] thread down\n", fsm->name); + + return 0; +} + +static struct fsm_obj *fsm_get_obj(struct fsm_main *fsm, u8 oid) +{ + struct fsm_obj *obj, *obj_t; + void *d = phl_to_drvpriv(fsm->phl_info); + + + _os_spinlock(d, &fsm->obj_queue.lock, _bh, NULL); + phl_list_for_loop_safe(obj, obj_t, + struct fsm_obj, &fsm->obj_queue.q, list) { + if (oid == (obj->oid)) { + _os_spinunlock(d, &fsm->obj_queue.lock, _bh, NULL); + return obj; + } + } + _os_spinunlock(d, &fsm->obj_queue.lock, _bh, NULL); + return NULL; +} + +struct fsm_msg *phl_fsm_new_msg(struct fsm_obj *obj, u16 event) +{ +#ifdef PHL_INCLUDE_FSM + struct fsm_msg *msg = NULL; + void *d = phl_to_drvpriv(obj->fsm->phl_info); + + if (fsm_status(obj->fsm) != FSM_STATUS_ENABLE) { + PHL_ERR("%s: is out of service, ignore message %s!\n", + obj->fsm->name, phl_fsm_evt_name(obj, event)); + return NULL; + } + + msg = (struct fsm_msg *)_os_kmem_alloc(d, sizeof(*msg)); + + if (msg == NULL) + return NULL; + + _os_mem_set(d, msg, 0, sizeof(*msg)); + msg->event = event; + + if (obj) { + msg->fsm = obj->fsm; + msg->oid = obj->oid; + } + return msg; +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); + return NULL; +#endif +} + +enum rtw_phl_status phl_fsm_sent_msg(struct fsm_obj *obj, struct fsm_msg *msg) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + + if (fsm_status(obj->fsm) != FSM_STATUS_ENABLE) { + PHL_ERR("fsm: %s is out of service, ignore message %s!\n", + obj->fsm->name, phl_fsm_evt_name(obj, msg->event)); + return RTW_PHL_STATUS_RESOURCE; + } + fsm_enqueue_list(d, obj->fsm, &obj->fsm->msg_queue, &msg->list); + + if (obj->fsm->tb.mode == FSM_ALONE_THREAD) + _os_sema_up(d, &obj->fsm->msg_ready); + else + _os_sema_up(d, &obj->fsm->root->msg_ready); + + return RTW_PHL_STATUS_SUCCESS; +} + +static struct fsm_msg *fsm_new_timer_msg(struct fsm_obj *obj, + u16 event, void *priv) +{ + struct fsm_msg *msg = NULL; + void *d = phl_to_drvpriv(obj->fsm->phl_info); + + msg = (struct fsm_msg *)_os_kmem_alloc(d, sizeof(*msg)); + if (msg == NULL) + return msg; + + _os_mem_set(d, msg, 0, sizeof(*msg)); + msg->event = event; + msg->oid = obj->oid; + msg->param = priv; + + return msg; +} + +static int fsm_post_message(struct fsm_obj *obj, u16 event, void *priv) +{ + struct fsm_msg *msg; + struct fsm_main *fsm = obj->fsm; + void *d = phl_to_drvpriv(obj->fsm->phl_info); + + msg = fsm_new_timer_msg(obj, event, priv); + if (msg == NULL) + return -1; + + fsm_enqueue_list(d, fsm, &fsm->msg_queue, &msg->list); + if (obj->fsm->tb.mode == FSM_ALONE_THREAD) + _os_sema_up(d, &fsm->msg_ready); + else + _os_sema_up(d, &fsm->root->msg_ready); + return 0; +} + +void fsm_timer_callback(void *context) +{ + struct fsm_main *fsm = (struct fsm_main *)context; + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj; + struct fsm_clock *clk; + int i; + + _os_set_timer(d, &fsm->fsm_timer, CLOCK_UNIT); + + if (fsm->en_clock_num == 0) + return; + + /* go through clock and descrease timer + * if timer was expired, issue event + */ + phl_list_for_loop(obj, struct fsm_obj, &fsm->obj_queue.q, list) { + + _os_spinlock(d, &obj->fsm->clock_lock, _bh, NULL); + for (i = 0; i < CLOCK_NUM; i++) { + + clk = &obj->clock[i]; + + if (IS_CLK_OFF(clk) || clk->pause) + continue; + + clk->remain = (int)phl_fsm_time_left(clk->start, + clk->end); + //(clk->remain < 0 ) ? 0 : clk->remain; + + /* timer expired */ + if (!IS_CLK_EXP(clk)) + continue; +#ifdef PHL_DBG_FSM + FSM_DBG(obj->fsm, "%s: expire in %d ms\n", + phl_fsm_evt_name(obj, clk->event), + phl_fsm_time_pass(clk->start)); +#endif + clk->end = 0; + clk->remain = -1; + /* send message to obj */ + + /* check fsm status before posting */ + if (fsm_status(fsm) != FSM_STATUS_INITIALIZED && + fsm_status(fsm) != FSM_STATUS_DISABLE) + fsm_post_message(obj, clk->event, clk->priv); + + fsm->en_clock_num--; + } + _os_spinunlock(d, &obj->fsm->clock_lock, _bh, NULL); + } +} + +/* allocate and init fsm resource */ +struct fsm_main *phl_fsm_init_fsm(struct fsm_root *root, const char *name, + void *priv, struct rtw_phl_fsm_tb *tb) +{ +#ifdef PHL_INCLUDE_FSM + struct fsm_main *fsm; + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + void *d = phl_to_drvpriv(phl_info); + //char name_t[FSM_NAME_LEN+10]; + + /* check event table */ + if (tb->evt_tbl[tb->max_event-1].event != tb->max_event-1) { + PHL_ERR("Event mismatch ? Is max event = %d != %d ?\n", + tb->evt_tbl[tb->max_event-1].event, + tb->max_event-1); + return NULL; + } + + /* check state table */ + if (tb->state_tbl[tb->max_state-1].state != tb->max_state-1) { + PHL_ERR("State mismatch ? Is max state = %d != %d) ?\n", + tb->state_tbl[tb->max_state-1].state, + tb->max_state-1); + return NULL; + } + + fsm = (struct fsm_main *)_os_kmem_alloc(d, sizeof(*fsm)); + + if (fsm == NULL) + return NULL; + + _os_mem_set(d, fsm, 0, sizeof(*fsm)); + _os_mem_cpy(d, &fsm->tb, (void *)tb, sizeof(*tb)); + _os_mem_cpy(d, &fsm->name, (void *)name, + MIN(FSM_NAME_LEN-1, _os_strlen((u8 *)name))); + + fsm->root = root; + fsm->phl_info = phl_info; + + fsm_init_queue(d, &(fsm->obj_queue)); + fsm_init_queue(d, &(fsm->msg_queue)); + fsm_init_queue(d, &(fsm->evt_queue)); + fsm_init_queue(d, &(fsm->ext_queue)); + _os_spinlock_init(d, &fsm->clock_lock); + + _os_init_timer(d, &fsm->fsm_timer, fsm_timer_callback, fsm, "fsm"); + fsm->oid_seq = 1; + + /* link fsm_main to fsm_root */ + if (tb->mode == FSM_ALONE_THREAD) { + _os_sema_init(d, &fsm->msg_ready, 0); + fsm_enqueue_list(d, fsm, &root->q_alone_thd, &fsm->list); + } else + fsm_enqueue_list(d, fsm, &root->q_share_thd, &fsm->list); + + FSM_INFO(fsm, "fsm: [%s] initialized\n", fsm->name); + fsm_status_set(fsm, FSM_STATUS_INITIALIZED); + return fsm; +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); + return NULL; +#endif /* PHL_INCLUDE_FSM */ +} + +/* For EXTERNAL application to deinit fsm (expose) + * @fsm: see struct fsm_main + */ +enum rtw_phl_status phl_fsm_deinit_fsm(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj, *obj_t; + + _os_release_timer(d, &fsm->fsm_timer); + + /* remove fsm form link list */ + list_del(&fsm->list); + + phl_list_for_loop_safe(obj, obj_t, + struct fsm_obj, &fsm->obj_queue.q, list) { + + list_del(&obj->list); + phl_fsm_flush_gbl(obj); + fsm_deinit_queue(d, &(obj->gbl_queue)); + /* free custom_obj */ + _os_kmem_free(d, obj->custom_obj, obj->custom_len); + + /* free fsm_obj */ + _os_kmem_free(d, obj, sizeof(*obj)); + } + fsm_deinit_queue(d, &(fsm->obj_queue)); + fsm_deinit_queue(d, &(fsm->msg_queue)); + fsm_deinit_queue(d, &(fsm->evt_queue)); + fsm_deinit_queue(d, &(fsm->ext_queue)); + _os_spinlock_free(d, &fsm->clock_lock); + + if (fsm->tb.mode == FSM_ALONE_THREAD) + _os_sema_free(d, &fsm->msg_ready); + + FSM_INFO(fsm, "fsm: [%s] uninitilized\n", fsm->name); + _os_kmem_free(d, fsm, sizeof(*fsm)); + + return RTW_PHL_STATUS_SUCCESS; +} + +char *phl_fsm_evt_name(struct fsm_obj *obj, u16 event) +{ + struct fsm_main *fsm = obj->fsm; + u8 ev; + + /* TODO handle global, internal, user event */ + /* global event */ + if (event & FSM_GBL_EV_MASK) + return "global"; + + /* fsm internal event */ + if (event & FSM_INT_EV_MASK) { + ev = (u8)(event & ~(FSM_EV_MASK)); + return int_event_tbl[ev].name; + } + + if (event == FSM_EV_UNKNOWN) + return "FSM_EV_UNKNOWN"; + + if (event > fsm->tb.max_event) + return "undefine"; + + /* user event */ + return fsm->tb.evt_tbl[event].name; +} + +static char *fsm_state_name(struct fsm_main *fsm, u8 state) +{ + if (state > fsm->tb.max_state) + return "unknown"; + + return fsm->tb.state_tbl[state].name; +} + +/* For EXTERNAL application to get state id (expose) + * + * @obj: obj to get state + */ +u8 phl_fsm_state_id(struct fsm_obj *obj) +{ + return obj->state; +} + +/** init obj internal variable + * + * @fsm: fsm that object belonged to + * default init to the 1st state in state_tbl + + */ +static void fsm_obj_switch_in(struct fsm_obj *obj) +{ + struct fsm_main *fsm = obj->fsm; + //void *d = phl_to_drvpriv(fsm->phl_info); + + /* default init to the 1st state in state_tbl */ + obj->state = fsm->tb.state_tbl[0].state; + FSM_INFO(fsm, "%s-%d %-18s -> %s\n", fsm->name, obj->oid, + "switch in", fsm_state_name(fsm, obj->state)); + + /* make it alive! Hello OBJ! */ + fsm_state_run(obj, FSM_EV_SWITCH_IN, NULL); +} + +/** deinit obj internal variable + * + * @fsm: fsm that object belonged to + * default init to the 1st state in state_tbl + + */ +static void fsm_obj_switch_out(struct fsm_obj *obj) +{ + struct fsm_main *fsm = obj->fsm; + //void *d = phl_to_drvpriv(fsm->phl_info); + + /* default init to the 1st state in state_tbl */ + obj->state = fsm->tb.state_tbl[0].state; + FSM_INFO(fsm, "%s-%d %-18s -> %s\n", fsm->name, obj->oid, + "switch out", fsm_state_name(fsm, obj->state)); + + /* make it alive! Hello OBJ! */ + fsm_state_run(obj, FSM_EV_SWITCH_OUT, NULL); +} + +/* For EXTERNAL application to new a fsm object (expose) + * + * @fsm: fsm that object belonged to + * @fsm_obj: obj param when calling FSM framework function + * @priv_len: custom obj length + * + * return value: NULL :fail + * other :cusomer obj handler (success) + */ +void *phl_fsm_new_obj(struct fsm_main *fsm, + void **fsm_obj, int sz) +{ +#ifdef PHL_INCLUDE_FSM + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj; + int i; + + obj = (struct fsm_obj *)_os_kmem_alloc(d, sizeof(*obj)); + if (obj == NULL) + return NULL; + + _os_mem_set(d, obj, 0, sizeof(*obj)); + obj->custom_obj = _os_kmem_alloc(d, sz); + + if (obj->custom_obj == NULL) { + _os_kmem_free(d, obj, sizeof(*obj)); + return NULL; + } + _os_mem_set(d, obj->custom_obj, 0, sz); + + for (i = 0; i < CLOCK_NUM; i++) + obj->clock[i].remain = -1; /* Negative means disable */ + + fsm_init_queue(d, &(obj->gbl_queue)); + obj->custom_len = sz; + obj->oid = (u8)fsm_new_oid(fsm); + obj->fsm = fsm; + + _os_mem_set(d, obj->name, 0, FSM_NAME_LEN); + _os_snprintf(obj->name, FSM_NAME_LEN, + "%s-%d", obj->fsm->name, obj->oid); + *fsm_obj = obj; + fsm_enqueue_list(d, fsm, &fsm->obj_queue, &obj->list); + + return obj->custom_obj; +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); + return NULL; +#endif /* PHL_INCLUDE_FSM */ +} + +/* For EXTERNAL application to destory a fsm object (expose) + * + * @fsm_obj: obj param when calling FSM framework function + */ +void phl_fsm_destory_obj(struct fsm_obj *obj) +{ + struct fsm_main *fsm = obj->fsm; + void *d = phl_to_drvpriv(fsm->phl_info); + + list_del(&obj->list); + phl_fsm_flush_gbl(obj); + fsm_deinit_queue(d, &(obj->gbl_queue)); + + /* free custom_obj */ + _os_kmem_free(d, obj->custom_obj, obj->custom_len); + + /* free fsm_obj */ + _os_kmem_free(d, obj, sizeof(*obj)); +} + +bool phl_fsm_is_alarm_off_ext(struct fsm_obj *obj, u8 id) +{ + struct fsm_clock *clock = &obj->clock[id]; + + return IS_CLK_OFF(clock); +} + +bool phl_fsm_is_alarm_off(struct fsm_obj *obj) +{ + struct fsm_clock *clock = &obj->clock[0]; + + return IS_CLK_OFF(clock); +} + +static void fsm_set_alarm(struct fsm_obj *obj, int ms, + u16 event, u8 id, void *priv) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct fsm_clock *clock = &obj->clock[id]; + u32 now; + + if (ms == 0) + fsm_post_message(obj, event, priv); + + _os_spinlock(d, &obj->fsm->clock_lock, _bh, NULL); + /* turn on clock from off */ + if (IS_CLK_OFF(clock)) + obj->fsm->en_clock_num++; + + now = _os_get_cur_time_ms(); + clock->event = event; + clock->priv = priv; + clock->start = now; + clock->end = now + ms; + clock->remain = (int)phl_fsm_time_left(clock->start, clock->end); + _os_spinunlock(d, &obj->fsm->clock_lock, _bh, NULL); + +#ifdef PHL_DBG_FSM + FSM_DBG(obj->fsm, "%s:%s now=0x%08x, end=0x%08x, remain=0x%08x\n", + phl_fsm_obj_name(obj), phl_fsm_evt_name(obj, event), + clock->start, clock->end, clock->remain); +#endif +} + +/* For EXTERNAL application to extend alarm time (expose) + * + * @obj: obj param when calling FSM framework function + * @event: alarm will issue this event while timer expired + * @ms: time period for the alarm + * remain time does not less than 'ms' + * @id: alarm id; start from 1 + */ +void phl_fsm_extend_alarm_ext(struct fsm_obj *obj, int ms, u8 id) + +{ + struct fsm_clock *clk = &obj->clock[id]; + int remain = ms; + + if (id == 0 || id >= CLOCK_NUM) { + PHL_ERR("%s: %s_%d fail\n", + phl_fsm_obj_name(obj), __func__, id); + return; + } + + if (IS_CLK_OFF(clk)) + return; + + remain = MAX((int)phl_fsm_time_left(clk->start, clk->end), ms); + phl_fsm_set_alarm_ext(obj, remain, clk->event, id, clk->priv); +} + +/* For EXTERNAL application to setup alarm (expose) + * + * @obj: obj param when calling FSM framework function + * @event: alarm will issue this event while timer expired + * @ms: time period for the alarm + * @id: alarm id; start from 1 + */ +void phl_fsm_set_alarm(struct fsm_obj *obj, int ms, u16 event) +{ + fsm_set_alarm(obj, ms, event, 0, NULL); +} + +/* For EXTERNAL application to setup alarm_ext (expose) + * + * @obj: obj param when calling FSM framework function + * @event: alarm will issue this event while timer expired + * @ms: time period for the alarm + * @id: alarm id; start from 1 + * @priv: priv from caller + */ +void phl_fsm_set_alarm_ext(struct fsm_obj *obj, + int ms, u16 event, u8 id, void *priv) +{ + if (id >= CLOCK_NUM) { + PHL_ERR("%s: set alarm_ext_%d to %d ms fail\n", + phl_fsm_obj_name(obj), id, ms); + return; + } + fsm_set_alarm(obj, ms, event, id, priv); +} + +static void fsm_cancel_alarm(struct fsm_obj *obj, u8 id) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct fsm_clock *clock = &obj->clock[id]; + + _os_spinlock(d, &obj->fsm->clock_lock, _bh, NULL); + /* turn off clock from on */ + if (IS_CLK_ON(clock)) + obj->fsm->en_clock_num--; + + //obj->clock[id].counter = -1; + obj->clock[id].end = 0; + obj->clock[id].remain = -1; + obj->clock[id].pause = 0; + _os_spinunlock(d, &obj->fsm->clock_lock, _bh, NULL); +} + +/* For EXTERNAL application to cancel alarm (expose) + * + * @obj: obj param when calling FSM framework function + */ +void phl_fsm_cancel_alarm(struct fsm_obj *obj) +{ + fsm_cancel_alarm(obj, 0); +} + +/* For EXTERNAL application to cancel alarm_ext (expose) + * + * @obj: obj param when calling FSM framework function + * @id: alarm id; start from 1 + */ +void phl_fsm_cancel_alarm_ext(struct fsm_obj *obj, u8 id) +{ + if (id == 0 || id >= CLOCK_NUM) { + PHL_ERR("%s: cancel alarm_ext_%d fail\n", + phl_fsm_obj_name(obj), id); + return; + } + fsm_cancel_alarm(obj, id); +} + +static void fsm_pause_alarm(struct fsm_obj *obj, u8 id) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + + _os_spinlock(d, &obj->fsm->clock_lock, _bh, NULL); + obj->clock[id].pause = 1; + _os_spinunlock(d, &obj->fsm->clock_lock, _bh, NULL); +} + +/* For EXTERNAL application to pause alarm (expose) + * + * @obj: obj param when calling FSM framework function + */ +void phl_fsm_pause_alarm(struct fsm_obj *obj) +{ + fsm_pause_alarm(obj, 0); +} + +/* For EXTERNAL application to pause alarm_ext (expose) + * + * @obj: obj param when calling FSM framework function + * @id: alarm id; start from 1 + */ +void phl_fsm_pause_alarm_ext(struct fsm_obj *obj, u8 id) +{ + if (id == 0 || id >= CLOCK_NUM) { + PHL_ERR("%s: pause alarm_%d fail\n", phl_fsm_obj_name(obj), id); + return; + } + fsm_pause_alarm(obj, id); +} + +static void fsm_resume_alarm(struct fsm_obj *obj, u8 id) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + u32 cur = _os_get_cur_time_ms(); + + /* extrend end time */ + _os_spinlock(d, &obj->fsm->clock_lock, _bh, NULL); + obj->clock[id].end = cur + obj->clock[id].remain; + obj->clock[id].pause = 0; + _os_spinunlock(d, &obj->fsm->clock_lock, _bh, NULL); +} + +/* For EXTERNAL application to resume alarm (expose) + * + * @obj: obj param when calling FSM framework function + */ +void phl_fsm_resume_alarm(struct fsm_obj *obj) +{ + fsm_resume_alarm(obj, 0); +} + +/* For EXTERNAL application to resume alarm_ext (expose) + * + * @obj: obj param when calling FSM framework function + * @id: alarm id; start from 1 + */ +void phl_fsm_resume_alarm_ext(struct fsm_obj *obj, u8 id) +{ + if (id == 0 || id >= CLOCK_NUM) { + PHL_ERR("%s: resume alarm_ext_%d fail\n", + phl_fsm_obj_name(obj), id); + return; + } + fsm_resume_alarm(obj, id); +} + +/* For EXTERNAL application to change state (expose) + * + * @obj: obj that changes state + * @new_state: new state + */ +void phl_fsm_state_goto(struct fsm_obj *obj, u8 new_state) +{ + struct fsm_main *fsm = NULL; + + if (obj->state == new_state) + return; + + fsm = obj->fsm; + + fsm_state_run(obj, FSM_EV_STATE_OUT, NULL); + + FSM_MSG(fsm, FSM_DBG_DBG, "\n"); + FSM_MSG(fsm, FSM_DBG_DBG, "%s-%d %-18s -> %s\n", fsm->name, obj->oid, + fsm_state_name(fsm, obj->state), + fsm_state_name(fsm, new_state)); + + obj->state = new_state; /* new state */ + fsm_state_run(obj, FSM_EV_STATE_IN, NULL); +} + +static void fsm_user_evt_handler(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_msg *msg; + struct fsm_obj *obj; + int rtn = FSM_FREE_PARAM; + + + while ((msg = fsm_dequeue_msg(fsm)) != NULL) { + + rtn = FSM_FREE_PARAM; + obj = fsm_get_obj(fsm, msg->oid); + + if (obj == NULL) { + PHL_WARN("%s-%d: obj not found\n", + fsm->name, msg->oid); + goto obj_not_found; + } + + /* DO NOT deliver event when fsm->should_stop is true */ + if ((fsm->should_stop == true) && + (obj->state == FSM_INITIAL_STATE) && + (msg->event < FSM_INT_EV_MASK)) { + + PHL_INFO("%s: should stop skip msg %s\n", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, msg->event)); + goto skip_msg; + } + + /* run state machine */ + rtn = fsm_state_run(obj, msg->event, msg->param); +skip_msg: +obj_not_found: + if ((rtn == FSM_FREE_PARAM) && + (msg->param_sz > 0) && + (msg->param != NULL)) + _os_kmem_free(d, (void *)msg->param, msg->param_sz); + _os_kmem_free(d, (void *)msg, sizeof(*msg)); + } +} + +static int fsm_update_status(struct fsm_main *fsm) +{ + struct fsm_obj *obj; + + phl_list_for_loop(obj, struct fsm_obj, &fsm->obj_queue.q, list) { + if (obj->state != FSM_INITIAL_STATE) { + PHL_INFO("%s: state %s\n", + phl_fsm_obj_name(obj), + fsm_state_name(fsm, obj->state)); + return 0; + } + } + + /* all objs are at INITAL_STATE + * fsm module is ready to stop + */ + fsm_status_set(fsm, FSM_STATUS_INITIALIZED); + + return 0; +} + +static int fsm_handler(struct fsm_main *fsm) +{ + /* USER EVENT */ + fsm_user_evt_handler(fsm); + + if (fsm->should_stop == true) + fsm_update_status(fsm); + + return 0; +} + +/* For EXTERNAL application to get fsm name (expose) + * @fsm: fsm to be get name + */ +char *phl_fsm_fsm_name(struct fsm_main *fsm) +{ + return fsm->name; +} + +/* For EXTERNAL application to get obj name (expose) + * @obj: obj to be get name + * For example: scan-1 (sacn obj with object id 1) + */ +char *phl_fsm_obj_name(struct fsm_obj *obj) +{ + return obj->name; +} + +/* For EXTERNAL application to cancel sma (expose) + * @obj: obj job will be cancelled + */ +enum rtw_phl_status phl_fsm_cancel_obj(struct fsm_obj *obj) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct fsm_msg *msg; + int rtn; + + /* NEW message to cancel obj task */ + msg = phl_fsm_new_msg(obj, FSM_EV_CANCEL); + if (msg == NULL) { + PHL_ERR("%s: alloc msg fail\n", obj->fsm->name); + return RTW_PHL_STATUS_RESOURCE; + } + rtn = phl_fsm_sent_msg(obj, msg); + + if (rtn != RTW_PHL_STATUS_SUCCESS) + _os_kmem_free(d, msg, sizeof(*msg)); + + return rtn; +} + +/* For EXTERNAL application to init FSM framework (expose) */ +/* @obj: obj job will be cancelled + */ +struct fsm_root *phl_fsm_init_root(void *priv) +{ +#ifdef PHL_INCLUDE_FSM + struct fsm_root *root; + struct phl_info_t *phl_info = (struct phl_info_t *)priv; + void *d = phl_to_drvpriv(phl_info); + int max, size; + + /* check size of internal event table */ + max = FSM_EV_MAX & ~(int_event_tbl[0].event); + size = sizeof(int_event_tbl)/sizeof(int_event_tbl)[0]; + if (size != max + 1) { + PHL_ERR("fsm: int_event_tbl[%d] != %d size mismatch!!", + size, max); + return NULL; + } + root = (struct fsm_root *)_os_kmem_alloc(d, sizeof(*root)); + if (root == NULL) + return NULL; + + _os_mem_set(d, root, 0, sizeof(*root)); + fsm_init_queue(d, &(root->q_share_thd)); + fsm_init_queue(d, &(root->q_alone_thd)); + + _os_sema_init(d, &root->msg_ready, 0); + root->phl_info = phl_info; + + PHL_INFO("fsm: [root] initialized\n"); + return root; +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); + return 0; +#endif /* PHL_INCLUDE_FSM */ +} + +/* For EXTERNAL application to deinit FSM framework (expose) + * @root: FSM framework handler + */ +void phl_fsm_deinit_root(struct fsm_root *root) +{ +#ifdef PHL_INCLUDE_FSM + void *d = phl_to_drvpriv(root->phl_info); + void *c = NULL; + + fsm_deinit_queue(d, &(root->q_alone_thd)); + fsm_deinit_queue(d, &(root->q_share_thd)); + + _os_sema_free(d, &root->msg_ready); + + /* free fsm_root */ + _os_kmem_free(d, root, sizeof(*root)); + + FSM_INFO(c, "fsm: [root] uninitilized\n"); +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); +#endif /* PHL_INCLUDE_FSM */ +} + +/* For EXTERNAL application to start fsm root (expose) + * @fsm: see struct fsm_main + */ +enum rtw_phl_status phl_fsm_start_root(struct fsm_root *root) +{ + void *d = phl_to_drvpriv(root->phl_info); + +#ifdef CONFIG_LINUX_THREAD + root->thread = kthread_create(fsm_thread_share, root, + "fsm_thread_share"); + wake_up_process(root->thread); +#else + _os_thread_init(d, &(root->thread), fsm_thread_share, root, + "fsm_thread_share"); + _os_thread_schedule(d, &(root->thread)); +#endif + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to stop fsm root (expose) + * @fsm: see struct fsm_main + */ +enum rtw_phl_status phl_fsm_stop_root(struct fsm_root *root) +{ + void *d = phl_to_drvpriv(root->phl_info); + void *c = NULL; + + _os_thread_stop(d, &(root->thread)); + _os_sema_up(d, &root->msg_ready); + _os_thread_deinit(d, &(root->thread)); + + FSM_INFO(c, "fsm: [root] stopped\n"); + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to start fsm (expose) + * @fsm: see struct fsm_main + */ +enum rtw_phl_status phl_fsm_start_fsm(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj; + + phl_list_for_loop(obj, struct fsm_obj, &fsm->obj_queue.q, list) { + fsm_obj_switch_in(obj); + } + if (fsm->tb.mode == FSM_ALONE_THREAD) { + _os_thread_init(d, &(fsm->thread), fsm_thread_alone, fsm, + "fsm_thread_alone"); + _os_thread_schedule(d, &(fsm->thread)); + } + + _os_set_timer(d, &fsm->fsm_timer, CLOCK_UNIT); + fsm->status = FSM_STATUS_READY; + + fsm_status_set(fsm, FSM_STATUS_ENABLE); + FSM_INFO(fsm, "fsm: [%s] started\n", fsm->name); + + return RTW_PHL_STATUS_SUCCESS; +} + +#define WAIT_DUR 10 +#define WAIT_TIMES 20 +/* For EXTERNAL application to stop fsm (expose) + * @fsm: see struct fsm_main + */ +enum rtw_phl_status phl_fsm_stop_fsm(struct fsm_main *fsm) +{ + void *d = phl_to_drvpriv(fsm->phl_info); + struct fsm_obj *obj; + int wait = WAIT_TIMES; + + fsm->should_stop = true; + + /* CANCEL all objs within fsm */ + fsm_cancel_all_running_obj(fsm); + + /* wait fsm module finish its task elegantly */ + while ((fsm->status != FSM_STATUS_INITIALIZED) && --wait) + _os_sleep_ms(d, WAIT_DUR); + + if (wait < (WAIT_TIMES >> 1)) + FSM_INFO(fsm, "%s: take %dms to disable\n", + fsm->name, (WAIT_TIMES-wait)*WAIT_DUR); + + fsm_status_set(fsm, FSM_STATUS_DISABLE); + + _os_spinlock(d, &fsm->clock_lock, _bh, NULL); + _os_cancel_timer(d, &fsm->fsm_timer); + _os_spinunlock(d, &fsm->clock_lock, _bh, NULL); + + phl_list_for_loop(obj, struct fsm_obj, &fsm->obj_queue.q, list) { + fsm_obj_switch_out(obj); + phl_fsm_flush_gbl(obj); + } + fsm_remove_all_queuing_msg(fsm); + + if (fsm->tb.mode == FSM_ALONE_THREAD) { + _os_thread_stop(d, &(fsm->thread)); + _os_sema_up(d, &fsm->msg_ready); + _os_thread_deinit(d, &(fsm->thread)); + } + fsm->should_stop = false; + + FSM_INFO(fsm, "fsm: [%s] stopped\n", fsm->name); + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL application to generate message buffer (expose) + * Generate message quickly and simply + * @phl: phl_info_t + * @obj: fsm_obj (msg receiver) + * @pbuf: message parameter + * @sz: message parameter size + * @event: event for the message + */ +enum rtw_phl_status phl_fsm_gen_msg(void *phl, struct fsm_obj *obj, + void *pbuf, u32 sz, u16 event) +{ +#ifdef PHL_INCLUDE_FSM + struct phl_info_t *phl_info = (struct phl_info_t *)phl; + struct fsm_msg *msg; + void *d = phl_to_drvpriv(phl_info); + void *param = NULL; + int rtn = RTW_PHL_STATUS_RESOURCE; + + /* NEW mem for message */ + msg = phl_fsm_new_msg(obj, event); + if (msg == NULL) { + FSM_ERR(obj->fsm, "%s: alloc msg %s fail\n", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, event)); + goto msg_fail; + } + + /* NEW mem for param */ + if (pbuf && sz) { + param = _os_kmem_alloc(d, sz); + if (param == NULL) { + FSM_ERR(obj->fsm, + "%s: alloc param %s fail\n", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, event)); + goto param_fail; + } + _os_mem_cpy(d, param, pbuf, sz); + } + msg->param = (void *)param; + msg->param_sz = sz; + + rtn = phl_fsm_sent_msg(obj, msg); + + if (rtn != RTW_PHL_STATUS_SUCCESS) + goto send_fail; + + return rtn; + +send_fail: + if (msg->param && msg->param_sz) + _os_kmem_free(d, msg->param, msg->param_sz); +param_fail: + _os_kmem_free(d, msg, sizeof(*msg)); +msg_fail: + + return rtn; +#else + PHL_WARN("fsm: %s exclude FSM\n", __func__); + return RTW_PHL_STATUS_FAILURE; +#endif /* PHL_INCLUDE_FSM */ +} + +enum rtw_phl_status phl_fsm_flush_gbl(struct fsm_obj *obj) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct gbl_param *p; + + _os_mem_set(d, &obj->my_gbl_req, 0, sizeof(obj->my_gbl_req)); + + /* flush obj->gbl_queue */ + phl_list_for_loop(p, + struct gbl_param, &obj->gbl_queue.q, list) { + + list_del(&p->list); + FSM_WARN(obj->fsm, "%s: del non replied %s:%s #%d\n", + phl_fsm_obj_name(obj), + phl_fsm_obj_name(p->obj_from), + phl_fsm_evt_name(obj, p->event), p->seq); + + _os_kmem_free(d, (void *)p, sizeof(*p)); + } + obj->gbl_q_len = 0; + + return RTW_PHL_STATUS_SUCCESS; +} + +/* For EXTERNAL fsm module to announce global msg (expose) + * + * !!! ONLY ALLOW fsm MODULE to call !!! + * !!! Otherwise will have reaing issue !!! + * + * Global msg will go throughs all fsm modules + * Limitation: + * Only supports ONE Glboal announcement at a time + * The latest one always overwrite previous one + * + * reference: phl_fsm_gbl_not_reply_num() + * + * @obj: fsm_obj + * @gbl_evt: Global event to be announced + * @cb_evt: call back event when things was done + * return: wait time(ms); 0: success, waiting is not necessary + * when wait > 0; callee will reply event to caller within ms + * negative value: fail + */ +int phl_fsm_gbl_msg_announce(struct fsm_obj *obj, u16 gbl_evt, u16 cb_evt) +{ + struct fsm_root *root = obj->fsm->root; + void *d = phl_to_drvpriv(root->phl_info); + struct fsm_main *fsm = obj->fsm; + struct fsm_main *fsm_t; + struct fsm_obj *obj_t; + int i; + + if (obj->my_gbl_req.count > 0) { + /* Should not happen!! + * Have ongoing announcement + * We are waiting for some GBL event reply + */ + for (i = 0; i < PHL_FSM_MAX_WAIT_OCUNT; i++) { + if (obj->my_gbl_req.wait_list[i]) + FSM_WARN(fsm, + "%s: drop not replied %s:%s #%d\n", + phl_fsm_obj_name(obj), + phl_fsm_obj_name( + obj->my_gbl_req.wait_list[i]), + phl_fsm_evt_name(obj, + obj->my_gbl_req.event), + obj->my_gbl_req.seq); + } + } + + /* create param for announcement */ + _os_mem_set(d, &obj->my_gbl_req, 0, sizeof(obj->my_gbl_req)); + obj->my_gbl_req.event = gbl_evt; + obj->my_gbl_req.cb_evt = cb_evt; + obj->my_gbl_req.obj_from = obj; + if (obj->fsm->root->gbl_seq == 0) /* 0 reserved */ + obj->fsm->root->gbl_seq = 1; + obj->my_gbl_req.seq = obj->fsm->root->gbl_seq++; + + /* GLOBAL EVENT will go through all fsms */ + phl_list_for_loop(fsm_t, struct fsm_main, &root->q_share_thd.q, list) { + if (fsm_status(fsm_t) != FSM_STATUS_ENABLE) { + FSM_INFO(fsm_t, "fsm: [%s] disabled, skip %s\n", + phl_fsm_fsm_name(fsm_t), + phl_fsm_evt_name(obj, gbl_evt)); + continue; + } + /* go through objs */ + phl_list_for_loop(obj_t, struct fsm_obj, + &fsm_t->obj_queue.q, list) { + + /* skip myself */ + if (obj_t == obj) + continue; + + fsm_state_run(obj_t, gbl_evt, &obj->my_gbl_req); + + if (obj->my_gbl_req.result < 0) { + FSM_ERR(fsm_t, + "%s: announce %s to %s fail(%d)\n", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj_t, gbl_evt), + phl_fsm_obj_name(obj_t), + obj->my_gbl_req.result); + + return obj->my_gbl_req.result; + } + } + } + return obj->my_gbl_req.wait_ms; +} + +/** For GBL announcer to get the number of un-replied fsm (espose) + * + * !!! ONLY ALLOW fsm MODULE to call !!! + * + * reference: phl_fsm_gbl_msg_announce() + * @obj: fsm_obj + * @param: see gbl_param + * return: 0 means there is no non-reply reqest, it's ready to go; + * otherwise yet ready + */ +int phl_fsm_gbl_not_reply_num(struct fsm_obj *obj, struct gbl_param *param) +{ + if (param == NULL) + return obj->my_gbl_req.count; + + /* we don't have any waitting reply; GBL may be cancelled earlier */ + if (obj->my_gbl_req.obj_from == NULL) { + FSM_WARN(obj->fsm, "%s: doesn't expect reply %s:%s #%d\n", + phl_fsm_obj_name(obj), + phl_fsm_obj_name(param->obj_to), + phl_fsm_evt_name(obj, param->event), param->seq); + return -1; + } + /* Are we looking for receiving event ? */ + if (param->event != obj->my_gbl_req.event) + return -2; + + if (param->seq != obj->my_gbl_req.seq) + return -3; + + FSM_INFO(obj->fsm, "%s: got reply %s:%s #%d\n", + phl_fsm_obj_name(obj), + phl_fsm_obj_name(param->obj_to), + phl_fsm_evt_name(obj, param->event), param->seq); + + /* clear incoming reporter from waitting list */ + param->wait_list[param->count] = NULL; + + return --obj->my_gbl_req.count; +} + +/** For Global event reciver to inform announcer to wait confirmation (espose) + * + * !!! ONLY ALLOW fsm MODULE to call !!! + * + * Call the function if Global receiver know that it can't finish task in time + * Global event receiver expect FSM_EV_GBL_REPLY to confirm task is finish + * reference : phl_fsm_gbl_msg_release() + * + * @obj: see fsm_obj + * @param: see gbl_param + * @ms: How long(max) can finish task according to received Global event + * caller will set an alarm to react if we can't finish the job on time + * return: negative value : fail + * postive value : seq number of this GBL event + */ +int phl_fsm_gbl_msg_hold(struct fsm_obj *obj, + struct gbl_param *param, u32 ms) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct gbl_param *p; + + if (param->count >= PHL_FSM_MAX_WAIT_OCUNT) { + param->result = -(GBL_ST_WAIT_REACH_MAX); + FSM_ERR(obj->fsm, "%s: hold %s reach max counter %d (%d)", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, param->event), param->count, + param->result); + return param->result; + } + + if (obj->gbl_q_len >= PHL_FSM_MAX_WAIT_OCUNT) { + param->result = -(GBL_ST_REPLY_REACH_MAX); + FSM_ERR(obj->fsm, "%s: reply %s reach max counter %d (%d)", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, param->event), + obj->gbl_q_len, param->result); + return param->result; + } + + p = (struct gbl_param *)_os_kmem_alloc(d, sizeof(*p)); + + if (p == NULL) { + param->result = -GBL_ST_ALLOC_MEM_FAIL; + FSM_ERR(obj->fsm, "%s: reply %s, alloc mem fail (%d)", + phl_fsm_obj_name(obj), + phl_fsm_evt_name(obj, param->event), + param->result); + return param->result; + } + + /* fill info to inform caller that we need time to process */ + param->obj_to = obj; + param->wait_list[param->count] = obj; + param->wait_ms = MAX(param->wait_ms, ms); + param->count++; + + /* save param for replying later */ + _os_mem_cpy(d, p, (void *)param, sizeof(*param)); + fsm_enqueue_list(d, obj->fsm, &obj->gbl_queue, &p->list); + + FSM_DBG(obj->fsm, "%s: require %d ms to handle %s:%s #%d\n", + phl_fsm_obj_name(obj), ms, + phl_fsm_obj_name(param->obj_from), + phl_fsm_evt_name(obj, param->event), + param->seq); + + return p->seq; +} + +/** For Global event reciver to inform announcer that task was done (espose) + * + * !!! ONLY ALLOW fsm MODULE to call !!! + * + * Call the function when Global receiver finish the task + * This is a ASYNC confirmation to Global event announcer + * Global event announcer will receive FSM_EV_GBL_REPLY when function is called + * reference: phl_fsm_gbl_msg_hold() + * + * @obj: see fsm_obj + * @param: see gbl_param + * @obj: see fsm_obj + * @event: event to be replied + * @seq: event to be replied + * @result: result to be replied + */ +enum rtw_phl_status phl_fsm_gbl_msg_release(struct fsm_obj *obj, + u16 event, u32 seq, enum gbl_evt_result result) +{ + void *d = phl_to_drvpriv(obj->fsm->phl_info); + struct gbl_param *p, *p_t; + + /* handle multiple Global event requests + * go through link list to get reply param according to event + */ + + phl_list_for_loop_safe(p, p_t, + struct gbl_param, &obj->gbl_queue.q, list) { + if ((event == p->event) && (seq == p->seq)) { + + p->result = result; + FSM_INFO(obj->fsm, "%s: reply %s:%s #%d, result %d\n", + phl_fsm_obj_name(obj), + phl_fsm_obj_name(p->obj_from), + phl_fsm_evt_name(obj, event), p->seq, result); + + phl_fsm_gen_msg(obj->fsm->phl_info, p->obj_from, + p, sizeof(*p), p->cb_evt); + + list_del(&p->list); + _os_kmem_free(d, (void *)p, sizeof(*p)); + break; + } + } + return RTW_PHL_STATUS_SUCCESS; +} + +/** Debug funcitons + * + */ +#ifdef PHL_DEBUG_FSM +static void fsm_dbg_dump_fsm_queue(struct fsm_queue *fsmq, + char *s, int *sz,bool detail) +{ + struct fsm_main *fsm, *fsm_t; + + char *ptr = s; + int len = *sz; + + phl_list_for_loop_safe(fsm, fsm_t, + struct fsm_main, &fsmq->q, list) { + _os_snprintf(pstr(ptr), lstr(ptr, len), "\t%4s : %s\n", fsm->name, + fsm->tb.mode ? "STANDALONE":"SHARE"); + + if (fsm->tb.dump_fsm && detail) { + len = lstr(ptr, len); + ptr = pstr(ptr); + fsm->tb.dump_fsm(fsm, ptr, &len); + } + } + *sz = len; +} + +static void fsm_dbg_help(struct fsm_main *fsm, char *s, int *sz, bool detail); +static void fsm_dbg_dump_fsm(struct fsm_main *fsm, + char *s, int *sz, bool detail) +{ + int len = *sz; + char *ptr = s; + + _os_snprintf(pstr(ptr), lstr(ptr, len), "\t%4s : %s\n", fsm->name, + fsm->tb.mode ? "STANDALONE":"SHARE"); + + if (fsm->tb.dump_fsm && detail) { + len = lstr(ptr, len); + ptr = pstr(ptr); + fsm->tb.dump_fsm(fsm, ptr, &len); + } + +} + +static void fsm_dbg_dump_state(struct fsm_main *fsm, + char *s, int *sz, bool detail) +{ + int i; + int len = *sz; + + _os_snprintf(pstr(s), lstr(s, len), + "[%s] state table\n", fsm->name); + for (i = 0; i < fsm->tb.max_state; i++) + _os_snprintf(pstr(s), lstr(s, len), "\t%4d : %s\n", + i, fsm->tb.state_tbl[i].name); + *sz = len; +} + +static void fsm_dbg_dump_event(struct fsm_main *fsm, + char *s, int *sz, bool detail) +{ + int i, max; + int len = *sz; + + /* internal event */ + _os_snprintf(pstr(s), lstr(s, len), "[Internal] event table\n"); + + max = FSM_EV_END & ~(int_event_tbl[0].event); /* FSM_INT_EV_MASK */ + for (i = 1; i < max; i++) + _os_snprintf(pstr(s), lstr(s, len), "\t0x%4x : %s\n", + int_event_tbl[i].event, int_event_tbl[i].name); + + /* user event */ + _os_snprintf(pstr(s), lstr(s, len), "\n[%s] event table max %d\n", fsm->name, fsm->tb.max_event); + for (i = 0; i < fsm->tb.max_event-1; i++) + _os_snprintf(pstr(s), lstr(s, len), "\t0x%4x : %s\n", + fsm->tb.evt_tbl[i].event, fsm->tb.evt_tbl[i].name); + *sz = len; +} + +static void fsm_dbg_dump_obj(struct fsm_main *fsm, + char *s, int *sz, bool detail) +{ + struct fsm_obj *obj, *obj_t; + int len = *sz; + char *ptr = s; + + phl_list_for_loop_safe(obj, obj_t, + struct fsm_obj, &fsm->obj_queue.q, list) { + + _os_snprintf(pstr(ptr), lstr(ptr, len), "%s-%d : state %s", + fsm->name, obj->oid, fsm_state_name(fsm, obj->state)); + + if (fsm->tb.dump_obj && detail) { + len = lstr(ptr, len); + ptr = pstr(ptr); + fsm->tb.dump_obj(obj->custom_obj, ptr, &len); + } + } + *sz = len; +} + +static void fsm_dbg_max(struct fsm_main *fsm, char *s, int *sz, bool detail) +{ + int len = *sz; + + _os_snprintf(pstr(s), lstr(s, len), + "ERR: fsm %s sould not run to here!!\n", __func__); + *sz = len; +} + +struct fsm_debug_ent { + char *opt; + void (*func)(struct fsm_main *fsm, char *s, int *sz, bool detail); + char *desc; +}; + +struct fsm_debug_ent debug_opt[] = { + {"help", fsm_dbg_help, "help message"}, + {"fsm", fsm_dbg_dump_fsm, "all fsm name"}, + {"st", fsm_dbg_dump_state, "state name"}, + {"ev", fsm_dbg_dump_event, "event name"}, + {"obj", fsm_dbg_dump_obj, "obj detail"}, + {"max", fsm_dbg_max, "max_opt"} +}; + +static void _fsm_dbg_help(struct fsm_root *root, char *s, int *sz, bool detail) +{ + int i, max_opt; + int len = *sz; + char *ptr = s; + + _os_snprintf(pstr(ptr), lstr(ptr, len), + "usage:\tfsm d